[ { "path": "LICENSE", "content": "MIT License\n\nCopyright (c) 2016-2018 David Shah \n\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the \"Software\"), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and/or sell\ncopies of the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in all\ncopies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\nSOFTWARE.\n" }, { "path": "README.md", "content": "# MIPI CSI-2 IP Cores\n\nThe _vhdl\\_rx_ folder contains a tried-and-tested high performance CSI-2 receiver core in VHDL. This can handle 4k video at over 30fps (most likely 60fps with a suitable camera module). This has been tested with the OV13850 camera module with a Xilinx Kintex-7 FPGA. It is currently limited to a 4-lane and 10bpp without modification, other parameters such as timing can be modified at compile time. Also in this folder are an example project and some miscellaneous VHDL support IP such as an AXI-4 framebuffer controller.\n\nThe _verilog\\_cores_ contains work-in-progress CSI-2 transmit and receive cores in Verilog. These are designed to be more flexible and run on a variety of platforms. The first target will be 640x480 video using a Raspberry Pi camera with an iCE40 FPGA.\n\nAll cores are licensed under the MIT License, see LICENSE for details.\n" }, { "path": "misc/caminit/.gitignore", "content": "/caminit\n" }, { "path": "misc/caminit/picam_init.cc", "content": "// Simple I2C using MPSSE bitbang implementation (passed thru FPGA) to initialise a PiCam2\n// Some code taken from iceprog\n#include \n#include \n#include \n\nstatic struct ftdi_context ftdic;\nstatic bool ftdic_open = false;\nstatic bool verbose = false;\nstatic bool ftdic_latency_set = false;\nstatic unsigned char ftdi_latency;\n\n\n/* MPSSE engine command definitions */\nenum mpsse_cmd\n{\n\t/* Mode commands */\n\tMC_SETB_LOW = 0x80, /* Set Data bits LowByte */\n\tMC_READB_LOW = 0x81, /* Read Data bits LowByte */\n\tMC_SETB_HIGH = 0x82, /* Set Data bits HighByte */\n\tMC_READB_HIGH = 0x83, /* Read data bits HighByte */\n\tMC_LOOPBACK_EN = 0x84, /* Enable loopback */\n\tMC_LOOPBACK_DIS = 0x85, /* Disable loopback */\n\tMC_SET_CLK_DIV = 0x86, /* Set clock divisor */\n\tMC_FLUSH = 0x87, /* Flush buffer fifos to the PC. */\n\tMC_WAIT_H = 0x88, /* Wait on GPIOL1 to go high. */\n\tMC_WAIT_L = 0x89, /* Wait on GPIOL1 to go low. */\n\tMC_TCK_X5 = 0x8A, /* Disable /5 div, enables 60MHz master clock */\n\tMC_TCK_D5 = 0x8B, /* Enable /5 div, backward compat to FT2232D */\n\tMC_EN_3PH_CLK = 0x8C, /* Enable 3 phase clk, DDR I2C */\n\tMC_DIS_3PH_CLK = 0x8D, /* Disable 3 phase clk */\n\tMC_CLK_N = 0x8E, /* Clock every bit, used for JTAG */\n\tMC_CLK_N8 = 0x8F, /* Clock every byte, used for JTAG */\n\tMC_CLK_TO_H = 0x94, /* Clock until GPIOL1 goes high */\n\tMC_CLK_TO_L = 0x95, /* Clock until GPIOL1 goes low */\n\tMC_EN_ADPT_CLK = 0x96, /* Enable adaptive clocking */\n\tMC_DIS_ADPT_CLK = 0x97, /* Disable adaptive clocking */\n\tMC_CLK8_TO_H = 0x9C, /* Clock until GPIOL1 goes high, count bytes */\n\tMC_CLK8_TO_L = 0x9D, /* Clock until GPIOL1 goes low, count bytes */\n\tMC_TRI = 0x9E, /* Set IO to only drive on 0 and tristate on 1 */\n\t/* CPU mode commands */\n\tMC_CPU_RS = 0x90, /* CPUMode read short address */\n\tMC_CPU_RE = 0x91, /* CPUMode read extended address */\n\tMC_CPU_WS = 0x92, /* CPUMode write short address */\n\tMC_CPU_WE = 0x93, /* CPUMode write extended address */\n};\n\n\nstatic void check_rx()\n{\n\twhile (1) {\n\t\tuint8_t data;\n\t\tint rc = ftdi_read_data(&ftdic, &data, 1);\n\t\tif (rc <= 0)\n\t\t\tbreak;\n\t\tfprintf(stderr, \"unexpected rx byte: %02X\\n\", data);\n\t}\n}\n\nstatic void error(int status)\n{\n\tcheck_rx();\n\tfprintf(stderr, \"ABORT.\\n\");\n\tif (ftdic_open) {\n\t\tif (ftdic_latency_set)\n\t\t\tftdi_set_latency_timer(&ftdic, ftdi_latency);\n\t\tftdi_usb_close(&ftdic);\n\t}\n\tftdi_deinit(&ftdic);\n\texit(status);\n}\n\nstatic uint8_t recv_byte()\n{\n\tuint8_t data;\n\twhile (1) {\n\t\tint rc = ftdi_read_data(&ftdic, &data, 1);\n\t\tif (rc < 0) {\n\t\t\tfprintf(stderr, \"Read error.\\n\");\n\t\t\terror(2);\n\t\t}\n\t\tif (rc == 1)\n\t\t\tbreak;\n\t\tusleep(100);\n\t}\n\treturn data;\n}\n\nstatic void send_byte(uint8_t data)\n{\n\tint rc = ftdi_write_data(&ftdic, &data, 1);\n\tif (rc != 1) {\n\t\tfprintf(stderr, \"Write error (single byte, rc=%d, expected %d).\\n\", rc, 1);\n\t\terror(2);\n\t}\n}\n\nstatic void set_gpio(bool sda, bool scl)\n{\n\tuint8_t gpio = 0;\n\tif (sda) gpio |= 0x01; //BDBUS0\n\tif (scl) gpio |= 0x02; //BDBUS1\n\tsend_byte(MC_SETB_LOW);\n\tsend_byte(gpio);\n\tsend_byte(0x03); //both outputs\n}\n\nstatic void i2c_start() {\n\tset_gpio(1, 1);\n\tset_gpio(0, 1);\n\tset_gpio(0, 0);\n}\n\nstatic void i2c_send(uint8_t data) {\n\tfor (int i = 7; i >= 0; i--) {\n\t\tbool bit = (data >> i) & 0x1;\n\t\tset_gpio(bit, 0);\n\t\tset_gpio(bit, 1);\n\t\tset_gpio(bit, 0);\n\t}\n\tset_gpio(1, 0);\n\tset_gpio(1, 1);\n\tset_gpio(1, 0);\n}\n\nstatic void i2c_stop() {\n\tset_gpio(0, 0);\n\tset_gpio(0, 1);\n\tset_gpio(1, 1);\n}\n\nstatic void write_cmos_sensor(uint16_t addr, uint8_t value) {\n\tfprintf(stderr, \"cam[0x%04X] <= 0x%02X\\n\", addr, value);\n\ti2c_start();\n\ti2c_send(0x10 << 1);\n\ti2c_send((addr >> 8) & 0xFF);\n\ti2c_send(addr & 0xFF);\n\ti2c_send(value);\n\ti2c_stop();\n}\n\nconst int framelength = 666;\nconst int linelength = 3448;\n\nstatic void cam_init() {\n\t// Based on \"Preview Setting\" from a Linux driver\n\twrite_cmos_sensor(0x0100, 0x00); //standby mode\n\twrite_cmos_sensor(0x30EB, 0x05); //mfg specific access begin\n\twrite_cmos_sensor(0x30EB, 0x0C); //\n\twrite_cmos_sensor(0x300A, 0xFF); //\n\twrite_cmos_sensor(0x300B, 0xFF); //\n\twrite_cmos_sensor(0x30EB, 0x05); //\n\twrite_cmos_sensor(0x30EB, 0x09); //mfg specific access end\n\twrite_cmos_sensor(0x0114, 0x01); //CSI_LANE_MODE: 2-lane\n\twrite_cmos_sensor(0x0128, 0x00); //DPHY_CTRL: auto mode (?)\n\twrite_cmos_sensor(0x012A, 0x18); //EXCK_FREQ[15:8] = 24MHz\n\twrite_cmos_sensor(0x012B, 0x00); //EXCK_FREQ[7:0]\n\twrite_cmos_sensor(0x0160, ((framelength >> 8) & 0xFF)); //framelength\n\twrite_cmos_sensor(0x0161, (framelength & 0xFF));\n\twrite_cmos_sensor(0x0162, ((linelength >> 8) & 0xFF));\n\twrite_cmos_sensor(0x0163, (linelength & 0xFF));\n\twrite_cmos_sensor(0x0164, 0x00); //X_ADD_STA_A[11:8]\n\twrite_cmos_sensor(0x0165, 0x00); //X_ADD_STA_A[7:0]\n\twrite_cmos_sensor(0x0166, 0x0A); //X_ADD_END_A[11:8]\n\twrite_cmos_sensor(0x0167, 0x00); //X_ADD_END_A[7:0]\n\twrite_cmos_sensor(0x0168, 0x00); //Y_ADD_STA_A[11:8]\n\twrite_cmos_sensor(0x0169, 0x00); //Y_ADD_STA_A[7:0]\n\twrite_cmos_sensor(0x016A, 0x07); //Y_ADD_END_A[11:8]\n\twrite_cmos_sensor(0x016B, 0x80); //Y_ADD_END_A[7:0]\n\twrite_cmos_sensor(0x016C, 0x02); //x_output_size[11:8] = 640\n\twrite_cmos_sensor(0x016D, 0x80); //x_output_size[7:0]\n\twrite_cmos_sensor(0x016E, 0x01); //y_output_size[11:8] = 480\n\twrite_cmos_sensor(0x016F, 0xE0); //y_output_size[7:0]\n\twrite_cmos_sensor(0x0170, 0x01); //X_ODD_INC_A\n\twrite_cmos_sensor(0x0171, 0x01); //Y_ODD_INC_A\n\twrite_cmos_sensor(0x0174, 0x02); //BINNING_MODE_H_A = x4-binning\n\twrite_cmos_sensor(0x0175, 0x02); //BINNING_MODE_V_A = x4-binning\n\twrite_cmos_sensor(0x018C, 0x08); //CSI_DATA_FORMAT_A[15:8]\n\twrite_cmos_sensor(0x018D, 0x08); //CSI_DATA_FORMAT_A[7:0]\n\twrite_cmos_sensor(0x0301, 0x08); //VTPXCK_DIV\n\twrite_cmos_sensor(0x0303, 0x01); //VTSYCK_DIV\n\twrite_cmos_sensor(0x0304, 0x03); //PREPLLCK_VT_DIV\n\twrite_cmos_sensor(0x0305, 0x03); //PREPLLCK_OP_DIV\n\twrite_cmos_sensor(0x0306, 0x00); //PLL_VT_MPY[10:8]\n\twrite_cmos_sensor(0x0307, 0x14); //PLL_VT_MPY[7:0]\n\twrite_cmos_sensor(0x0309, 0x08); //OPPXCK_DIV\n\twrite_cmos_sensor(0x030B, 0x02); //OPSYCK_DIV\n\twrite_cmos_sensor(0x030C, 0x00); //PLL_OP_MPY[10:8]\n\twrite_cmos_sensor(0x030D, 0x0A); //PLL_OP_MPY[7:0]\n\twrite_cmos_sensor(0x455E, 0x00); //??\n\twrite_cmos_sensor(0x471E, 0x4B); //??\n\twrite_cmos_sensor(0x4767, 0x0F); //??\n\twrite_cmos_sensor(0x4750, 0x14); //??\n\twrite_cmos_sensor(0x4540, 0x00); //??\n\twrite_cmos_sensor(0x47B4, 0x14); //??\n\twrite_cmos_sensor(0x4713, 0x30); //??\n\twrite_cmos_sensor(0x478B, 0x10); //??\n\twrite_cmos_sensor(0x478F, 0x10); //??\n\twrite_cmos_sensor(0x4793, 0x10); //??\n\twrite_cmos_sensor(0x4797, 0x0E); //??\n\twrite_cmos_sensor(0x479B, 0x0E); //??\n\t\n\t//write_cmos_sensor(0x0157, 232); // ANA_GAIN_GLOBAL_A\n\t//write_cmos_sensor(0x0257, 232); // ANA_GAIN_GLOBAL_B\n\n\t\n\t//write_cmos_sensor(0x0600, 0x00); // Test pattern: disable\n\t//write_cmos_sensor(0x0601, 0x00); // Test pattern: disable\n\n#if 0\n\twrite_cmos_sensor(0x0600, 0x00); // Test pattern: solid colour\n\twrite_cmos_sensor(0x0601, 0x01); //\n\n\twrite_cmos_sensor(0x0602, 0x02); // Test pattern: red\n\twrite_cmos_sensor(0x0603, 0xAA); //\n\n\twrite_cmos_sensor(0x0604, 0x02); // Test pattern: greenR\n\twrite_cmos_sensor(0x0605, 0xAA); //\n\n\twrite_cmos_sensor(0x0606, 0x02); // Test pattern: blue\n\twrite_cmos_sensor(0x0607, 0xAA); //\n\n\twrite_cmos_sensor(0x0608, 0x02); // Test pattern: greenB\n\twrite_cmos_sensor(0x0609, 0xAA); //\n\n\n\twrite_cmos_sensor(0x0624, 0x0A); // Test pattern width\n\twrite_cmos_sensor(0x0625, 0x00); //\n\t\n\twrite_cmos_sensor(0x0626, 0x07); // Test pattern height\n\twrite_cmos_sensor(0x0627, 0x80); //\n\n\n#endif\n\t\n\twrite_cmos_sensor(0x0100, 0x01);\n}\n\nint main() {\n\tenum ftdi_interface ifnum = INTERFACE_B;\n\tfprintf(stderr, \"init..\\n\");\n\tftdi_init(&ftdic);\n\tftdi_set_interface(&ftdic, ifnum);\n\n\tif (ftdi_usb_open(&ftdic, 0x0403, 0x6010) && ftdi_usb_open(&ftdic, 0x0403, 0x6014)) {\n\t\tfprintf(stderr, \"Can't find FTDI USB device (vendor_id 0x0403, device_id 0x6010 or 0x6014).\\n\");\n\t\terror(2);\n\t}\n\n\tif (ftdi_usb_reset(&ftdic)) {\n\t\tfprintf(stderr, \"Failed to reset FTDI USB device.\\n\");\n\t\terror(2);\n\t}\n\n\tif (ftdi_usb_purge_buffers(&ftdic)) {\n\t\tfprintf(stderr, \"Failed to purge buffers on FTDI USB device.\\n\");\n\t\terror(2);\n\t}\n\n\tif (ftdi_get_latency_timer(&ftdic, &ftdi_latency) < 0) {\n\t\tfprintf(stderr, \"Failed to get latency timer (%s).\\n\", ftdi_get_error_string(&ftdic));\n\t\terror(2);\n\t}\n\n\t/* 1 is the fastest polling, it means 1 kHz polling */\n\tif (ftdi_set_latency_timer(&ftdic, 1) < 0) {\n\t\tfprintf(stderr, \"Failed to set latency timer (%s).\\n\", ftdi_get_error_string(&ftdic));\n\t\terror(2);\n\t}\n\n\tif (ftdi_set_bitmode(&ftdic, 0xff, BITMODE_MPSSE) < 0) {\n\t\tfprintf(stderr, \"Failed to set BITMODE_MPSSE on iCE FTDI USB device.\\n\");\n\t\terror(2);\n\t}\n\n\t// enable clock divide by 5\n\tsend_byte(MC_TCK_D5);\n\n\t// set 6 MHz clock\n\tsend_byte(MC_SET_CLK_DIV);\n\tsend_byte(0x00);\n\tsend_byte(0x00);\n\n\tcam_init();\n}\n" }, { "path": "verilog_cores/.gitignore", "content": "*.o\nwork/\n*.cf\n*.blif\n*.json\n" }, { "path": "verilog_cores/Makefile", "content": "SOURCES=$(wildcard phy/*.v csi/*.v link/*.v)\nLINT_TOP=csi_rx_ice40 # temp\nSYN_TOP=csi_rx_ice40\n\nlint: $(SOURCES)\n\tverilator --top-module $(LINT_TOP) --lint-only $^ /usr/local/share/yosys/ice40/cells_sim.v\n\nsyn: $(SOURCES)\n\tyosys -p \"synth_ice40 -top ${SYN_TOP} -blif top.blif\" $^\n\n.PHONY: lint syn\n" }, { "path": "verilog_cores/README.md", "content": "# Verilog MIPI CSI-2 Cores - WIP\n" }, { "path": "verilog_cores/csi/header_ecc.v", "content": "/**\n * The MIT License\n * Copyright (c) 2016-2018 David Shah\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in\n * all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n * THE SOFTWARE.\n *\n */\n\n/**\n * MIPI CSI-2 header ECC computation\n */\n\n module csi_header_ecc (\n\t input [23:0] data,\n\t output [7:0] ecc\n);\n\tassign ecc[7:6] = 2'b00;\n\tassign ecc[5] = data[10] ^ data[11] ^ data[12] ^ data[13] ^ data[14] ^ data[15] ^ data[16] ^ data[17] ^ data[18] ^ data[19] ^ data[21] ^ data[22] ^ data[23];\n\tassign ecc[4] = data[4] ^ data[5] ^ data[6] ^ data[7] ^ data[8] ^ data[9] ^ data[16] ^ data[17] ^ data[18] ^ data[19] ^ data[20] ^ data[22] ^ data[23];\n\tassign ecc[3] = data[1] ^ data[2] ^ data[3] ^ data[7] ^ data[8] ^ data[9] ^ data[13] ^ data[14] ^ data[15] ^ data[19] ^ data[20] ^ data[21] ^ data[23];\n\tassign ecc[2] = data[0] ^ data[2] ^ data[3] ^ data[5] ^ data[6] ^ data[9] ^ data[11] ^ data[12] ^ data[15] ^ data[18] ^ data[20] ^ data[21] ^ data[22];\n\tassign ecc[1] = data[0] ^ data[1] ^ data[3] ^ data[4] ^ data[6] ^ data[8] ^ data[10] ^ data[12] ^ data[14] ^ data[17] ^ data[20] ^ data[21] ^ data[22] ^ data[23];\n\tassign ecc[0] = data[0] ^ data[1] ^ data[2] ^ data[4] ^ data[5] ^ data[7] ^ data[10] ^ data[11] ^ data[13] ^ data[16] ^ data[20] ^ data[21] ^ data[22] ^ data[23];\nendmodule\n" }, { "path": "verilog_cores/csi/rx_packet_handler.v", "content": "/**\n * The MIT License\n * Copyright (c) 2016-2018 David Shah\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in\n * all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n * THE SOFTWARE.\n *\n */\n\n/**\n * MIPI CSI-2 receive packet handler\n *\n * This controls wait_for_sync and packet_done handshaking with\n * byte/word aligners; keeps track of whether in frame\n * by detecting FS/FE; and extracts video payload from long packets\n */\n\nmodule csi_rx_packet_handler #(\n\tparameter [1:0] VC = 2'b00, // MIPI CSI-2 \"virtual channel\"\n\tparameter [5:0] FS_DT = 6'h00, // Frame start data type\n\tparameter [5:0] FE_DT = 6'h01, // Frame end data type\n\tparameter [5:0] VIDEO_DT = 6'h2A, // Video payload data type (6'h2A = 8-bit raw, 6'h2B = 10-bit raw, 6'h2C = 12-bit raw)\n\tparameter [15:0] MAX_LEN = 8192 // Max expected packet len, used as timeout\n) (\n\tinput clock, // byte/word clock\n\tinput reset, // active high sync reset\n\tinput enable, // active high clock enable\n\n\tinput [31:0] data, // data from word aligner\n\tinput data_enable, // data enable for less than 4-lane links\n\tinput data_frame, // data framing from word combiner\n\n\tinput lp_detect, // D-PHY LP mode detection, forces EoP\n\n\toutput sync_wait, // sync wait output to byte/word handlers\n\toutput packet_done, // packet done output to word combiner\n\n\toutput reg [31:0] payload, // payload output\n\toutput reg payload_enable, // payload data enable\n\toutput reg payload_frame, // payload framing\n\n\toutput reg vsync, // quasi-vsync for FS signal\n\toutput reg in_frame,\n\toutput reg in_line\n);\n\n\twire [1:0] hdr_vc;\n\twire [5:0] hdr_dt;\n\twire [15:0] hdr_packet_len;\n\twire [7:0] hdr_ecc, expected_ecc;\n\twire long_packet, valid_packet;\n\twire is_hdr;\n\n\treg [15:0] packet_len;\n\treg [2:0] state;\n\treg [15:0] bytes_read;\n\n\talways @(posedge clock)\n\tbegin\n\t\tif (reset) begin\n\t\t\tstate <= 3'b000;\n\n\t\t\tpacket_len <= 0;\n\t\t\tbytes_read <= 0;\n\n\t\t\tpayload <= 0;\n\t\t\tpayload_enable <= 0;\n\t\t\tpayload_frame <= 0;\n\n\t\t\tvsync <= 0;\n\t\t\tin_frame <= 0;\n\t\t\tin_line <= 0;\n\t\tend else if (enable) begin\n\n\t\t\tif (lp_detect) begin\n\t\t\t\tstate <= 3'b000;\n\t\t\tend else begin\n\t\t\t\tcase (state)\n\t\t\t\t\t3'b000: state <= 3'b001; // init\n\n\t\t\t\t\t3'b001: begin // wait for start\n\t\t\t\t\t\tbytes_read <= 0;\n\t\t\t\t\t\tif (data_enable) begin\n\t\t\t\t\t\t\tpacket_len <= hdr_packet_len;\n\t\t\t\t\t\t\tif (long_packet && valid_packet)\n\t\t\t\t\t\t\t\tstate <= 3'b010;\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\tstate <= 3'b011;\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\n\t\t\t\t\t3'b010: begin // rx long packet\n\t\t\t\t\t\tif (data_enable) begin\n\t\t\t\t\t\t\tif ((bytes_read < (packet_len - 4)) && (bytes_read < MAX_LEN))\n\t\t\t\t\t\t\t\tbytes_read <= bytes_read + 4;\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\tstate <= 3'b011;\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\n\t\t\t\t\t3'b011: state <= 3'b100; // end of packet, assert packet_done\n\t\t\t\t\t3'b100: state <= 3'b001; // wait one cycle and reset\n\n\t\t\t\t\tdefault: state <= 3'b000;\n\t\t\t\tendcase\n\t\t\tend\n\n\t\t\tif (is_hdr && hdr_dt == FS_DT && valid_packet)\n\t\t\t\tin_frame <= 1'b1;\n\t\t\telse if (is_hdr && hdr_dt == FE_DT && valid_packet)\n\t\t\t\tin_frame <= 1'b0;\n\n\t\t\tif (is_hdr && hdr_dt == VIDEO_DT && valid_packet)\n\t\t\t\tin_line <= 1'b1;\n\t\t\telse if (state != 3'b010 && state != 3'b001)\n\t\t\t\tin_line <= 1'b0;\n\n\t\t\tvsync <= (is_hdr && hdr_dt == FS_DT && valid_packet);\n\n\t\t\tpayload <= data;\n\t\t\tpayload_frame <= (state == 3'b010);\n\t\t\tpayload_enable <= (state == 3'b010) && data_enable;\n\t\tend\n\tend\n\n\tassign hdr_vc = data[7:6];\n\tassign hdr_dt = data[5:0];\n\tassign hdr_packet_len = data[23:8];\n\tassign hdr_ecc = data[31:24];\n\n\tcsi_header_ecc ecc_i (\n\t\t.data(data[23:0]),\n\t\t.ecc(expected_ecc)\n\t);\n\n\tassign long_packet = hdr_dt > 6'h0F;\n\tassign valid_packet = (hdr_vc == VC)\n\t\t\t\t\t\t\t&& (hdr_dt == FS_DT || hdr_dt == FE_DT || hdr_dt == VIDEO_DT)\n\t\t\t\t\t\t\t&& (hdr_ecc == expected_ecc);\n\n\tassign is_hdr = data_enable && (state == 3'b001);\n\n\tassign sync_wait = (state == 3'b001);\n\tassign packet_done = (state == 3'b011) || lp_detect;\nendmodule\n" }, { "path": "verilog_cores/csi2.core", "content": "CAPI=2:\n\nname : ::csi2:0\n\nfilesets:\n icebreaker:\n files:\n - misc/downsample.v : {file_type : verilogSource}\n - test/icebreaker/uart.v : {file_type : verilogSource}\n - test/icebreaker/top.v : {file_type : verilogSource}\n - test/icebreaker/icecam.pcf : {file_type : PCF}\n core:\n files:\n - phy/dphy_iserdes.v\n - phy/dphy_oserdes.v\n - phy/word_combiner.v\n - phy/byte_aligner.v\n - csi/header_ecc.v\n - csi/rx_packet_handler.v\n file_type : verilogSource\n link_ice40:\n files:\n - link/csi_rx_ice40.v : {file_type : verilogSource}\n depend : [\"!tool_icestorm? (yosys:techlibs:ice40)\"]\n\ntargets:\n default:\n filesets : [core, link_ice40]\n\n icebreaker:\n default_tool : icestorm\n filesets: [core, link_ice40, icebreaker]\n tools:\n icestorm:\n pnr : next\n nextpnr_options : [--up5k]\n toplevel : top\n\n lint:\n default_tool : verilator\n filesets: [core, link_ice40]\n tools:\n verilator:\n mode : lint-only\n toplevel : csi_rx_ice40\n" }, { "path": "verilog_cores/link/csi_rx_ice40.v", "content": "/**\n * The MIT License\n * Copyright (c) 2016-2018 David Shah\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in\n * all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n * THE SOFTWARE.\n *\n */\n\n/*\n * Example CSI-2 receiver for iCE40\n*/\n\nmodule csi_rx_ice40 #(\n\tparameter LANES = 2, // lane count\n\tparameter PAIRSWAP = 2'b10, // lane pair swap (inverts data for given lane)\n\n\tparameter [1:0] VC = 2'b00, // MIPI CSI-2 \"virtual channel\"\n\tparameter [5:0] FS_DT = 6'h00, // Frame start data type\n\tparameter [5:0] FE_DT = 6'h01, // Frame end data type\n\tparameter [5:0] VIDEO_DT = 6'h2A, // Video payload data type (6'h2A = 8-bit raw, 6'h2B = 10-bit raw, 6'h2C = 12-bit raw)\n\tparameter [15:0] MAX_LEN = 8192 // Max expected packet len, used as timeout\n)(\n\tinput dphy_clk_lane,\n\tinput [LANES-1:0] dphy_data_lane,\n\tinput dphy_lp_sense,\n\n\tinput areset,\n\n\toutput word_clk,\n\toutput [31:0] payload_data,\n\toutput payload_enable,\n\toutput payload_frame,\n\n\toutput [2*LANES-1:0] dbg_raw_ddr,\n\toutput [8*LANES-1:0] dbg_raw_deser,\n\toutput [8*LANES-1:0] dbg_aligned,\n\toutput [LANES-1:0] dbg_aligned_valid,\n\toutput dbg_wait_sync,\n\n\toutput vsync,\n\toutput in_line,\n\toutput in_frame\n);\n\n\twire dphy_clk, dphy_clk_pre;\n\n\tSB_IO #(\n\t\t.PIN_TYPE(6'b000001),\n\t\t.IO_STANDARD(\"SB_LVDS_INPUT\")\n\t) clk_iobuf (\n\t\t.PACKAGE_PIN(dphy_clk_lane),\n\t\t.D_IN_0(dphy_clk_pre)\n\t);\n\t\n\tSB_GB clk_gbuf (\n\t\t.USER_SIGNAL_TO_GLOBAL_BUFFER(dphy_clk_pre),\n\t\t.GLOBAL_BUFFER_OUTPUT(dphy_clk)\n\t);\n\t\n\twire dphy_lp;\n\tSB_IO #(\n\t\t.PIN_TYPE(6'b000001),\n\t\t.IO_STANDARD(\"SB_LVDS_INPUT\")\n\t) lp_compare (\n\t\t.PACKAGE_PIN(dphy_lp_sense),\n\t\t.D_IN_0(dphy_lp)\n\t);\n\n\treg [1:0] div;\n\talways @(posedge dphy_clk or posedge areset)\n\t\tif (areset)\n\t\t\tdiv <= 0;\n\t\telse\n\t\t\tdiv <= div + 1'b1;\n\tassign word_clk = div[1];\n\t\n\twire sreset;\n\treg [7:0] sreset_ctr;\n\talways @(posedge word_clk or posedge areset)\n\t\tif (areset)\n\t\t\tsreset_ctr <= 0;\n\t\telse if (!(&sreset_ctr))\n\t\t\tsreset_ctr <= sreset_ctr + 1'b1;\n\t\t\t\n\tassign sreset = !(&sreset_ctr);\n\t\n\twire byte_packet_done, wait_for_sync;\n\twire [LANES*8-1:0] aligned_bytes;\n\twire [LANES-1:0] aligned_bytes_valid;\n\n\n\tgenerate\n\tgenvar ii;\n\tfor (ii = 0; ii < LANES; ii++) begin\n\t\twire [1:0] din_raw;\n\t\tSB_IO #(\n\t\t\t.PIN_TYPE(6'b000000),\n\t\t\t.IO_STANDARD(\"SB_LVDS_INPUT\")\n\t\t) data_iobuf (\n\t\t\t.PACKAGE_PIN(dphy_data_lane[ii]),\n\t\t\t.INPUT_CLK(dphy_clk),\n\t\t\t.D_IN_0(din_raw[0]),\n\t\t\t.D_IN_1(din_raw[1])\n\t\t);\n\t\tassign dbg_raw_ddr[2*ii+1:2*ii] = din_raw;\n\n\t\twire [7:0] din_deser;\n\t\tdphy_iserdes #(\n\t\t\t.REG_INPUT(1'b1)\n\t\t) iserdes_i (\n\t\t .dphy_clk(dphy_clk),\n\t\t .din(din_raw),\n\t\t .sys_clk(word_clk),\n\t\t .areset(areset),\n\t\t .dout(din_deser)\n\t );\n\n \twire [7:0] din_deser_swap = PAIRSWAP[ii] ? ~din_deser : din_deser;\n\t\tassign dbg_raw_deser[8*ii+7:8*ii] = din_deser_swap;\n\n\t\tdphy_rx_byte_align baligner_i (\n\t\t\t.clock(word_clk),\n\t\t\t.reset(sreset),\n\t\t\t.enable(1'b1),\n\t\t\t.deser_byte(din_deser_swap),\n\t\t\t.wait_for_sync(wait_for_sync),\n\t\t\t.packet_done(byte_packet_done),\n\t\t\t.valid_data(aligned_bytes_valid[ii]),\n\t\t\t.data_out(aligned_bytes[8*ii+7:8*ii])\n\t\t);\n\n\tend\n\tendgenerate\n\n\tassign dbg_aligned = aligned_bytes;\n\tassign dbg_aligned_valid = aligned_bytes_valid;\n\n\twire [31:0] comb_word;\n\twire comb_word_en, comb_word_frame;\n\twire word_packet_done;\n\n\tdphy_rx_word_combiner #(\n\t\t.LANES(LANES)\n\t) combiner_i (\n\t\t.clock(word_clk),\n\t\t.reset(sreset),\n\t\t.enable(1'b1),\n\t\t.bytes_in(aligned_bytes),\n\t\t.bytes_valid(aligned_bytes_valid),\n\t\t.wait_for_sync(wait_for_sync),\n\t\t.packet_done(word_packet_done),\n\t\t.byte_packet_done(byte_packet_done),\n\n\t\t.word_out(comb_word),\n\t\t.word_enable(comb_word_en),\n\t\t.word_frame(comb_word_frame)\n\t);\n\n\tassign dbg_wait_sync = wait_for_sync;\n\n\tcsi_rx_packet_handler #(\n\t\t.VC(VC),\n\t\t.FS_DT(FS_DT),\n\t\t.FE_DT(FE_DT),\n\t\t.VIDEO_DT(VIDEO_DT),\n\t\t.MAX_LEN(MAX_LEN)\n\t) handler_i (\n\t\t.clock(word_clk),\n\t\t.reset(sreset),\n\t\t.enable(1'b1),\n\n\t\t.data(comb_word),\n\t\t.data_enable(comb_word_en),\n\t\t.data_frame(comb_word_frame),\n\n\t\t.lp_detect(!dphy_lp),\n\n\t\t.sync_wait(wait_for_sync),\n\t\t.packet_done(word_packet_done),\n\n\t\t.payload(payload_data),\n\t \t.payload_enable(payload_enable),\n\t\t.payload_frame(payload_frame),\n\n\t\t.vsync(vsync),\n\t\t.in_frame(in_frame),\n\t\t.in_line(in_line)\n\t);\nendmodule\n" }, { "path": "verilog_cores/misc/downsample.v", "content": "/**\n * The MIT License\n * Copyright (c) 2016-2018 David Shah\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in\n * all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n * THE SOFTWARE.\n *\n */\n\n/*\n * Simple downsampler and buffer 640x480 => 40x30\n*/\n\nmodule downsample (\n\tinput pixel_clock,\n\tinput in_line,\n\tinput in_frame,\n\tinput [31:0] pixel_data,\n\tinput data_enable,\n\n\tinput read_clock,\n\tinput [5:0] read_x,\n\tinput [4:0] read_y,\n\toutput reg [7:0] read_q\n);\n\n\n\treg [7:0] buffer[0:2047];\n\n\treg [11:0] pixel_acc;\n\treg [7:0] pixel_x;\n\treg [8:0] pixel_y;\n\treg last_in_line;\n\n\twire [11:0] next_acc = pixel_acc + pixel_data[7:0] + pixel_data[15:8] + pixel_data[23:16] + pixel_data[31:24];\n\n\talways @(posedge pixel_clock)\n\tbegin\n\t\tif (!in_frame) begin\n\t\t\tpixel_acc <= 0;\n\t\t\tpixel_x <= 0;\n\t\t\tpixel_y <= 0;\n\t\t\tlast_in_line <= in_line;\n\t\tend else begin\n\t\t\tif (in_line && data_enable) begin\n\t\t\t\tif (pixel_y[3:0] == 0) begin\n\t\t\t\t\tif (&(pixel_x[1:0])) begin\n\t\t\t\t\t\tpixel_acc <= 0;\n\t\t\t\t\t\tbuffer[{pixel_y[8:4], pixel_x[7:2]}] <= next_acc[11:4];\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tpixel_acc <= next_acc;\n\t\t\t\t\tend\n\t\t\t\t\tif (pixel_x < 160)\n\t\t\t\t\t\tpixel_x <= pixel_x + 1;\n\t\t\t\tend\n\t\t\tend else if (!in_line) begin\n\t\t\t\tpixel_x <= 0;\n\t\t\t\tpixel_acc <= 0;\n\t\t\t\tif (last_in_line)\n\t\t\t\t\tpixel_y <= pixel_y + 1'b1;\n\t\t\tend\n\t\t\tlast_in_line <= in_line;\n\t\tend\n\tend\n\n\talways @(posedge read_clock)\n\t\tread_q <= buffer[{read_y, read_x}];\nendmodule\n" }, { "path": "verilog_cores/phy/byte_aligner.v", "content": "/**\n * The MIT License\n * Copyright (c) 2016-2018 David Shah\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in\n * all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n * THE SOFTWARE.\n *\n */\n\n/**\n * MIPI D-PHY byte aligner\n * This receives raw, unaligned bytes (which could contain part of two actual bytes)\n * from the SERDES and aligns them by looking for the D-PHY sync pattern\n *\n * When wait_for_sync is high the entity will wait until it sees the valid header at some alignment,\n * at which point the found alignment is locked until packet_done is asserted\n *\n * valid_data is asserted as soon as the sync pattern is found, so the next byte\n * contains the CSI packet header\n *\n * In reality to avoid false triggers we must look for a valid sync pattern on all k lanes,\n * if this does not occur the word aligner (a seperate entity) will assert packet_done immediately\n *\n */\n`default_nettype none\nmodule dphy_rx_byte_align(\n\tinput clock, // byte clock\n\tinput reset, // active high sync reset\n\tinput enable, // byte clock enable\n\tinput [7:0] deser_byte, // raw bytes from iserdes\n\tinput wait_for_sync, // when high will look for a sync pattern if sync not already found\n\tinput packet_done, // assert to reset synchronisation status\n\toutput reg valid_data, // goes high as soon as sync pattern is found (so data out on next cycle contains header)\n\toutput reg [7:0] data_out //aligned data out, typically delayed by 2 cycles\n);\n\n\treg [7:0] curr_byte;\n\treg [7:0] last_byte;\n\treg [7:0] shifted_byte;\n\n\treg found_sync;\n\treg [2:0] sync_offs; // found offset of sync pattern\n\treg [2:0] data_offs; // current data offset\n\n\talways @(posedge clock)\n\tbegin\n\t\tif (reset) begin\n\t\t\tvalid_data <= 1'b0;\n\t\t\tlast_byte <= 0;\n\t\t\tcurr_byte <= 0;\n\t\t\tdata_out <= 0;\n\t\t\tdata_offs <= 0;\n\t\tend else if (enable) begin\n\t\t\tlast_byte <= curr_byte;\n\t\t\tcurr_byte <= deser_byte;\n\t\t\tdata_out <= shifted_byte;\n\n\t\t\tif (packet_done) begin\n\t\t\t\tvalid_data <= found_sync;\n\t\t\tend else if (wait_for_sync && found_sync && !valid_data) begin\n\t\t\t\t// Waiting for sync, just found it now so use sync position as offset\n\t\t\t\tvalid_data <= 1'b1;\n\t\t\t\tdata_offs <= sync_offs;\n\t\t\tend\n\t\tend\n\tend\n\n\tlocalparam [7:0] sync_word = 8'b10111000;\n\treg was_found;\n\treg [2:0] offset;\n\tinteger i;\n\n\twire [15:0] concat_word = {curr_byte, last_byte};\n\n\talways @(*)\n\tbegin\n\t\toffset = 0;\n\t\twas_found = 1'b0;\n\t\tfound_sync = 1'b0;\n\t\tsync_offs = 0;\n\t\tfor (i = 0; i < 8; i = i + 1) begin\n\t\t\tif ((concat_word[(1+i) +: 8] == sync_word) && (last_byte[i:0] == 0)) begin\n\t\t\t\twas_found = 1'b1;\n\t\t\t\toffset = i;\n\t\t\tend\n\t\tend\n\t\tif (was_found) begin\n\t\t\tfound_sync = 1'b1;\n\t\t\tsync_offs = offset;\n\t\tend\n\tend\n\n\tassign shifted_byte = concat_word[(1 + data_offs) +: 8];\n\n\nendmodule\n" }, { "path": "verilog_cores/phy/dphy_iserdes.v", "content": "/**\n * The MIT License\n * Copyright (c) 2018 David Shah\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in\n * all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n * THE SOFTWARE.\n *\n */\n\n/**\n * MIPI D-PHY input SERDES\n * This is designed to take 2 inputs per clock from an architecture specific\n * DDR primitive\n */\n\nmodule dphy_iserdes(\n\tinput dphy_clk, // Fast D-PHY DDR clock (4x sys_clk)\n\tinput [1:0] din, // Input from arch DDR primitive, D1 should be the bit after D0\n\tinput sys_clk, // System byte clock\n\tinput areset, // Active high async reset\n\toutput [7:0] dout // Output data\n);\n\n\tparameter REG_INPUT = 1'b0;\n\tparameter NUM_OUT_SYNCFFS = 2;\n\twire [1:0] iserdes_din;\n\n\tgenerate\n\tif (REG_INPUT) begin\n\t reg [1:0] din_reg;\n\t\talways @(posedge dphy_clk, posedge areset)\n\t\t if (areset)\n\t\t\t\tdin_reg <= 2'b00;\n\t\t\telse\n\t\t\t\tdin_reg <= din;\n\t\tassign iserdes_din = din_reg;\n\tend else begin\n\t assign iserdes_din = din;\n\tend\n\tendgenerate\n\n\treg [7:0] reg_word;\n\n\talways @(posedge dphy_clk, posedge areset)\n\t\tif (areset)\n\t\t\treg_word <= 0;\n\t\telse\n\t\t\treg_word <= {iserdes_din, reg_word[7:2]}; // MIPI interface uses LSB first\n\n\treg [7:0] out_sync_regs[0:NUM_OUT_SYNCFFS-1];\n\tinteger i;\n\talways @(posedge sys_clk, posedge areset)\n\t\tif (areset)\n\t\t\tfor (i = 0; i < NUM_OUT_SYNCFFS; i = i + 1)\n\t\t\t\tout_sync_regs[i] <= 0;\n\t\telse begin\n\t\t\tfor (i = 1; i < NUM_OUT_SYNCFFS; i = i + 1)\n\t\t\t\tout_sync_regs[i] <= out_sync_regs[i-1];\n\t\t\tout_sync_regs[0] <= reg_word;\n\t\tend\n\n\tassign dout = out_sync_regs[NUM_OUT_SYNCFFS-1];\nendmodule\n" }, { "path": "verilog_cores/phy/dphy_oserdes.v", "content": "/**\n * The MIT License\n * Copyright (c) 2018 David Shah\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in\n * all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n * THE SOFTWARE.\n *\n */\n\n/**\n * MIPI D-PHY output SERDES\n * This is designed to generate 2 outputs per clock for an architecture specific\n * DDR primitive\n */\n\nmodule dphy_oserdes(\n\tinput sys_clk, // System byte clock\n\tinput areset, // Active high async reset\n input [7:0] din, // Input from CSI-2 packetiser\n\tinput dphy_clk, // Fast D-PHY DDR clock (4x sys_clk)\n\toutput reg [1:0] dout // Output data, bit 1 should be the second bit transmitted\n);\n\n\tparameter NUM_SYNCFFS = 2;\n\n\treg [8:0] dclk_sclk_din[0:NUM_SYNCFFS-1];\n\n\t// Input\n\tinteger i;\n\talways @(posedge dphy_clk, posedge areset)\n\t\tif (areset) begin\n\t\t\tfor (i = 0; i < NUM_SYNCFFS; i = i + 1)\n\t\t\t\tdclk_sclk_din[i] <= 0;\n\t\tend else begin\n\t\t\tfor (i = 1; i < NUM_SYNCFFS; i = i + 1)\n\t\t\t\tdclk_sclk_din[i] <= dclk_sclk_din[i-1];\n\t\t\tdclk_sclk_din[0] <= {sys_clk, din};\n\t\tend\n\n\twire dclk_sclk = dclk_sclk_din[NUM_SYNCFFS-1][8];\n\twire [7:0] dclk_din = dclk_sclk_din[NUM_SYNCFFS-1][7:0];\n\treg last_sclk;\n\n\treg [7:0] reg_word;\n\n\talways @(posedge dphy_clk, posedge areset)\n\t\tif (areset) begin\n\t\t\tlast_sclk <= 1'b0;\n\t\t\tdout <= 2'b00;\n\t\t\treg_word <= 0;\n\t\tend else begin\n\t\t\tlast_sclk <= dclk_sclk;\n\t\t\tdout <= reg_word[1:0]; // LSB first\n\t\t\tif (dclk_sclk && !last_sclk) begin\n\t\t\t\treg_word <= dclk_din;\n\t\t\tend else begin\n\t\t\t\treg_word <= {reg_word[1:0], reg_word[7:2]};\n\t\t\tend\n\t\tend\nendmodule\n" }, { "path": "verilog_cores/phy/word_combiner.v", "content": "/**\n * The MIT License\n * Copyright (c) 2016-2018 David Shah\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in\n * all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n * THE SOFTWARE.\n *\n */\n\n/**\n * MIPI D-PHY word combiner\n * This receives aligned bytes from the byte aligner(s), controls the byte aligner(s)\n * and assembles the data stream back into 32-bit words for consistency across different\n * widths\n *\n */\n\nmodule dphy_rx_word_combiner #(\n\tparameter LANES = 2\n) (\n\tinput clock, // byte clock\n\tinput reset, // active high sync reset\n\tinput enable, // active high clock enable\n\tinput [8*LANES-1:0] bytes_in, // input bytes from lane byte aligners\n\tinput [LANES-1:0] bytes_valid, // valid signals from lane byte aligners\n\tinput wait_for_sync, // input from packet handler\n\tinput packet_done, // packet done input from packet handler\n\toutput byte_packet_done, // packet done output to byte aligners\n\n\toutput reg [31:0] word_out, //fixed width 32-bit data out\n\toutput reg word_enable, // word enable used when in less than 4-lane mode\n\toutput reg word_frame // valid output high during valid packet even if word enable low\n);\n\twire triggered = |bytes_valid;\n\twire all_valid = &bytes_valid;\n\twire invalid_start = triggered && !all_valid;\n\n\treg valid;\n\n\treg [31:0] word_int;\n\treg [1:0] byte_cnt;\n\n\talways @(posedge clock)\n\tbegin\n\t\tif (reset) begin\n\t\t\tvalid <= 0;\n\t\t\tword_int <= 0;\n\t\t\tbyte_cnt <= 0;\n\n\t\t\tword_out <= 0;\n\t\t\tword_enable <= 0;\n\t\t\tword_frame <= 0;\n\t\tend else if (enable) begin\n\t\t\tif (all_valid && !valid && wait_for_sync) begin\n\t\t\t\tbyte_cnt <= 0;\n\t\t\t\tword_frame <= 1'b1;\n\t\t\t\tvalid <= 1'b1;\n\t\t\tend else if (packet_done) begin\n\t\t\t\tword_frame <= 1'b0;\n\t\t\t\tvalid <= 1'b0;\n\t\t\tend\n\n\t\t\tif (valid) begin\n\t\t\t\tif (LANES == 4) begin\n\t\t\t\t\tword_out <= bytes_in;\n\t\t\t\t\tword_enable <= 1'b1;\n\t\t\t\tend else begin\n\t\t\t\t\tbyte_cnt <= byte_cnt + LANES;\n\t\t\t\t\tword_int <= {bytes_in, word_int[31:8*LANES]};\n\t\t\t\t\tif ((byte_cnt + LANES) % 4 == 0) begin\n\t\t\t\t\t\tword_out <= {bytes_in, word_int[31:8*LANES]};\n\t\t\t\t\t\tword_enable <= 1'b1;\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tword_enable <= 1'b0;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend else begin\n\t\t\t\tword_enable <= 1'b0;\n\t\t\tend\n\t\tend\n\tend\n\n\tassign byte_packet_done = packet_done | invalid_start;\nendmodule\n" }, { "path": "verilog_cores/test/icebreaker/.gitignore", "content": "*.blif\n*.json\n*.asc\n*.bin\n*.rpt\n*.log\n" }, { "path": "verilog_cores/test/icebreaker/Makefile", "content": "SOURCES = $(wildcard ../../csi/*.v ../../phy/*.v ../../link/*.v ../../misc/*.v uart.v top.v)\nPROJ=camera\nPIN_DEF=icecam.pcf\nDEVICE=up5k\n\nall: $(PROJ).rpt $(PROJ).bin\n\n%.json: $(SOURCES)\n\tyosys -ql yosys.log -p 'synth_ice40 -top top -json $@' $(SOURCES)\n\n%.asc: %.json $(PIN_DEF)\n\tnextpnr-ice40 --pre-pack constraints.py --up5k --pcf $(PIN_DEF) --json $< --asc $@ --freq 40\n\ngui: %.json $(PIN_DEF)\n\tnextpnr-ice40 --up5k --pcf $(PIN_DEF) --json $< --asc $@ --freq 40 --gui\n\n%.bin: %.asc\n\ticepack $< $@\n\n%.rpt: %.asc\n\ticetime -d $(DEVICE) -mtr $@ $<\n\nprog: $(PROJ).bin\n\ticeprog $<\n\nsudo-prog: $(PROJ).bin\n\t@echo 'Executing prog as root!!!'\n\tsudo iceprog $<\n\nclean:\n\trm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin\n\n.SECONDARY:\n.PHONY: all prog clean gui\n" }, { "path": "verilog_cores/test/icebreaker/constraints.py", "content": "ctx.addClock(\"csi_rx_i.dphy_clk\", 96)\nctx.addClock(\"video_clk\", 24)\nctx.addClock(\"uart_i.sys_clk_i\", 12)\n" }, { "path": "verilog_cores/test/icebreaker/icecam.pcf", "content": "set_io mpsse_sda 6 #FTDI D0\nset_io mpsse_scl 9 #FTDI D1\n\nset_io cam_enable 3 #P1A7\nset_io cam_sda 34 #P1B3\nset_io cam_scl 28 #P1B10\n\nset_io dphy_clk 32 #P1B9\nset_io dphy_data[0] 42 #P1B7\nset_io dphy_data[1] 43 #P1B1\nset_io dphy_lp 48 #P1A8\n\nset_io BTN_N 10\nset_io LEDR_N 11\nset_io LEDG_N 37\n\nset_io LED2 27\nset_io LED3 25\nset_io LED5 21\nset_io BTN2 19\nset_io LED1 26\nset_io LED4 23\nset_io BTN1 20\nset_io BTN3 18\n\nset_io clk12 35\nset_io dbg_tx 13\n" }, { "path": "verilog_cores/test/icebreaker/top.v", "content": "/**\n * The MIT License\n * Copyright (c) 2018 David Shah\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in\n * all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n * THE SOFTWARE.\n *\n */\n\nmodule top(input clk12,\n\t\t input mpsse_sda, mpsse_scl, inout cam_sda, cam_scl, output cam_enable,\n\t\t input dphy_clk, input [1:0] dphy_data, input dphy_lp,\n\t\t output LEDR_N, LEDG_N, LED1, LED2, LED3, LED4, LED5,\n\t\t input BTN_N, BTN1, BTN2, BTN3,\n\t\t output dbg_tx);\n\n\twire areset = !BTN_N;\n\tassign cam_scl = mpsse_scl ? 1'bz : 1'b0;\n assign cam_sda = mpsse_sda ? 1'bz : 1'b0;\n\tassign cam_enable = 1'b1;\n\twire video_clk;\n\twire in_line, in_frame, vsync;\n\twire [31:0] payload_data;\n\twire payload_valid;\n\twire [15:0] raw_deser;\n\twire [15:0] aligned_deser;\n\twire [3:0] raw_ddr;\n\twire [1:0] aligned_valid;\n\twire wait_sync;\n\twire payload_frame;\n\n\tcsi_rx_ice40 #(\n\t\t.LANES(2), // lane count\n\t\t.PAIRSWAP(2'b10), // lane pair swap (inverts data for given lane)\n\n\t\t.VC(2'b00), // MIPI CSI-2 \"virtual channel\"\n\t\t.FS_DT(6'h12), // Frame start data type\n\t\t.FE_DT(6'h01), // Frame end data type\n\t\t.VIDEO_DT(6'h2A), // Video payload data type (6'h2A = 8-bit raw, 6'h2B = 10-bit raw, 6'h2C = 12-bit raw)\n\t\t.MAX_LEN(8192) // Max expected packet len, used as timeout\n\t) csi_rx_i (\n\t\t.dphy_clk_lane(dphy_clk),\n\t\t.dphy_data_lane(dphy_data),\n\t\t.dphy_lp_sense(dphy_lp),\n\n\t\t.areset(areset),\n\n\t\t.word_clk(video_clk),\n\t\t.payload_data(payload_data),\n\t\t.payload_enable(payload_valid),\n\t\t.payload_frame(payload_frame),\n\n\t\t.vsync(vsync),\n\t\t.in_line(in_line),\n\t\t.in_frame(in_frame),\n\n\t\t.dbg_aligned_valid(aligned_valid),\n\t\t.dbg_raw_deser(raw_deser),\n\t\t.dbg_raw_ddr(raw_ddr),\n\t\t.dbg_wait_sync(wait_sync)\n\t);\n\n\n\treg [22:0] sclk_div;\n\talways @(posedge video_clk)\n\t\tsclk_div <= sclk_div + 1'b1;\n\t\n\treg [15:0] vsync_monostable = 0;\n\talways @(posedge video_clk)\n\t\tif (vsync || vsync_monostable != 0)\n\t\t\tvsync_monostable <= vsync_monostable + 1'b1;\n\t\n\t\n\tassign LEDR_N = !sclk_div[22];\n\tassign LEDG_N = !(|vsync_monostable);\n\tassign LED1 = video_clk;\n\tassign {LED5, LED4, LED3, LED2} = (payload_frame&&payload_valid) ? payload_data[5:2] : 0;\n\n\treg [5:0] read_x;\n\treg [4:0] read_y;\n\twire [7:0] read_data;\n\tdownsample ds_i(\n\t\t.pixel_clock(video_clk),\n\t\t.in_line(in_line),\n\t\t.in_frame(!vsync),\n\t\t.pixel_data(payload_data),\n\t\t.data_enable(payload_frame&&payload_valid),\n\n\t\t.read_clock(clk12),\n\t\t.read_x(read_x),\n\t\t.read_y(read_y),\n\t\t.read_q(read_data)\n\t);\n\n\treg do_send = 1'b0;\n\twire uart_busy;\n\treg uart_write;\n\treg [13:0] btn_debounce;\n\treg btn_reg;\n\treg [12:0] uart_holdoff;\n\n\talways @(posedge clk12)\n\tbegin\n\t\tbtn_reg <= BTN1;\n\n\t\tif (btn_reg)\n\t\t\tbtn_debounce <= 0;\n\t\telse if (!&(btn_debounce))\n\t\t\tbtn_debounce <= btn_debounce + 1;\n\n\n\t\tuart_write <= 1'b0;\n\t\tif (btn_reg && &btn_debounce && !do_send) begin\n\t\t\tdo_send <= 1'b1;\n\t\t\tread_x <= 0;\n\t\t\tread_y <= 0;\n\t\tend\n\n\t\tif (uart_busy)\n\t\t\tuart_holdoff <= 0;\n\t\telse if (!&(uart_holdoff))\n\t\t\tuart_holdoff <= uart_holdoff + 1'b1;\n\n\t\tif (do_send) begin\n\t\t\tif (read_x == 0 && read_y == 30) begin\n\t\t\t\tdo_send <= 1'b0;\n\t\t\tend else begin\n\t\t\t\tif (&uart_holdoff && !uart_busy && !uart_write) begin\n\t\t\t\t\tuart_write <= 1'b1;\n\t\t\t\t\tif (read_x == 39) begin\n\t\t\t\t\t\tread_y <= read_y + 1'b1;\n\t\t\t\t\t\tread_x <= 0;\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tread_x <= read_x + 1'b1;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tend\n\n\tuart uart_i (\n\t // Outputs\n\t .uart_busy(uart_busy), // High means UART is transmitting\n\t .uart_tx(dbg_tx), // UART transmit wire\n\t // Inputs\n\t .uart_wr_i(uart_write), // Raise to transmit byte\n\t .uart_dat_i(read_data), // 8-bit data\n\t .sys_clk_i(clk12), // System clock, 12 MHz\n\t .sys_rst_i(areset) // System reset\n\t);\n\nendmodule\n" }, { "path": "verilog_cores/test/icebreaker/uart.v", "content": "// From http://www.excamera.com/sphinx/fpga-uart.html\n\nmodule uart(\n // Outputs\n uart_busy, // High means UART is transmitting\n uart_tx, // UART transmit wire\n // Inputs\n uart_wr_i, // Raise to transmit byte\n uart_dat_i, // 8-bit data\n sys_clk_i, // System clock, 12 MHz\n sys_rst_i // System reset\n);\n\n input uart_wr_i;\n input [7:0] uart_dat_i;\n input sys_clk_i;\n input sys_rst_i;\n\n output uart_busy;\n output uart_tx;\n\n reg [3:0] bitcount;\n reg [8:0] shifter;\n reg uart_tx;\n\n wire uart_busy = |bitcount[3:1];\n wire sending = |bitcount;\n\n // sys_clk_i is 12MHz. We want a 3MHz clock\n\n reg [28:0] d;\n wire [28:0] dInc = d[28] ? (3000000) : (3000000 - 12000000);\n wire [28:0] dNxt = d + dInc;\n always @(posedge sys_clk_i)\n begin\n d = dNxt;\n end\n wire ser_clk = ~d[28]; // this is the 115200 Hz clock\n\n always @(posedge sys_clk_i)\n begin\n if (sys_rst_i) begin\n uart_tx <= 1;\n bitcount <= 0;\n shifter <= 0;\n end else begin\n // just got a new byte\n if (uart_wr_i & ~uart_busy) begin\n shifter <= { uart_dat_i[7:0], 1'h0 };\n bitcount <= (1 + 8 + 2);\n end\n\n if (sending & ser_clk) begin\n { shifter, uart_tx } <= { 1'h1, shifter };\n bitcount <= bitcount - 1;\n end\n end\n end\n\nendmodule\n" }, { "path": "vhdl_rx/.gitignore", "content": "*.o\nwork/\n*.cf\n" }, { "path": "vhdl_rx/LICENSE.notes", "content": "All of the source code written by me (in particular */*.vhd except the examples\nfolder) is licensed under the MIT license,see the LICENSE file for more\ninformation.\n\nFor obvious reasons this does not extend to any files in the example project\ngenerated or included by Xilinx's tools (including but not limited to Xilinx's\nIP cores such as the DDR3 interface). The copyright on these belongs to Xilinx\nand Xilinx's restrictions will apply.\n\nThe register values in the `ov13850_4k_regs.vhd` file were based on open source\nLinux drivers, but it is my understanding that these are not copyrightable in\nthemselves.\n\nAll mentioned trademarks are property of their respective owners.\n" }, { "path": "vhdl_rx/README.md", "content": "# 4k MIPI CSI-2 FPGA Camera Interface\n\n## Overview\nThis project is an open source (MIT license) MIPI CSI-2 receive core for Xilinx FPGAs, supporting 4k resolution at greater than 30fps.\nIt includes a complete demo project, designed for the Genesys 2 board with a custom FMC to camera card, that writes the 4k video into a DDR3 framebuffer and\noutputs at 1080p (with a choice of scaled or cropped) to the HDMI and VGA ports. The demo camera module is the Omnivision OV13850 (using the Firefly camera module),\nwhich supports 4k at up to 30fps, although the demo runs at 24fps where it seems performance is better - this may partly be down to the choice of register values though. Although the OV13850\nsensor/ADC does not seem to work much above 30fps; the camera also has a \"test pattern\" mode which bypasses this and which I have used to test my driver up to 45fps.\n\n## Structure\n - The `mipi-csi-rx` folder contains all the components (except the `video_timing_ctrl` timing generator, in the `video-misc` folder) needed for the CSI-2 Rx itself.\n - `csi_rx_top` is the top level for the CSI-2 interface, this is what you should use in your design\n - `csi_rx_4_lane_link` encapsulates the link layer. In particular\n - `csi_rx_hs_lane_phy` is the low-level data PHY, one for each lane, containing the input buffer and input SERDES\n - `csi_rx_byte_align` ensures bytes are correctly aligned by looking for the sync byte that precedes packets\n - `csi_rx_word_align` corrects any slight alignment differences between lanes, concatenating the 4 lane byte inputs to a single 32-bit word output\n - `csi_rx_hs_clk_phy` handles the clock input and contains the necessary clock buffers\n - `csi_rx_packet_handler` processes packets, looking for video packets and seperating off the payload\n - `csi_rx_10bit_unpack` converts 32-bit packet payload input and outputs 4 10-bit pixels (with a `valid` output, as it does not produce pixels every clock cycle)\n - `csi_rx_video_output` synchronises the CSI-2 clock domain to the pixel clock domain using a line buffer and outputs standard video format\n - `ov-cam-control` contains a I2C interface for camera configuration, the 4k24 configuration for the OV13850, and `ov13850_control_top` which handles camera reseting\n and writes the register values from the configuration ROM to the I2C interface.\n - `framebuffer-ctrl` contains the framebuffer controller, which interfaces with external framebuffer memory (providing an AXI4 master to interface with the Xilinx DDR3 controller) to scale or crop the 4k frames from the camera to 1080p for the video output.\n - `video-misc` contains the video timing controller, a test pattern generator for debugging, a video register for timing purposes and the basic ISP (a simple debayering core and colour channel gain adjustment for white balance).\n - `dvi-tx` contains a simple DVI transmitter, for the Genesys 2 HDMI output port\n - `demo-top` contains the top level files for the demo project; and `examples` contains the Vivado project itself for the demo\n\n## Test Hardware\nThe current test platform is the Digilent Genesys 2 (Kintex-7 XC7K325T-2) with an OV13850 camera. The CSI-2 lanes connect to 2.5V LVDS inputs on the FPGA, using\na custom FMC interface board. Earlier testing was done on a Virtex-6 FPGA, unfortunately I no longer have access to this platform so support cannot be guaranteed.\n\nThe exact camera used was the Firefly RK3288 camera module, which is a convenient way of obtaining the OV13850 camera - search for \"OV13850 Firefly RK3288\" and various sites selling it can be\nfound starting from $40 or so. In the future I'm looking into using smartphone replacement camera modules. I have ordered some IUNI U2 replacement back cameras which are P16V01A modules based\non the 4k60-capable OV16825 and have a publicly available pinout.\n\nThe FMC board also has a connector for the 4k 5.5\" Z5 premium LCD; which I am also working on code to drive. The KiCad board designs and gerbers are in the [DSITx](https://github.com/daveshah1/DSITx/tree/master/hardware/fmc-v1.2) repo.\n\nA quick picture of my test setup is below.\n\n![4k Camera Testing](http://ds0.me/csi_rx/csi_testing.jpg)\n\n## Customisation\nSee `csi_rx_top.vhd` for more information on the parameters that need to be adjusted depending on your camera and application.\n\n## Future Work\nIn the future the debayering block needs to be improved to reduce colour fringing at sharp edges. A driver for the focus voice coil driver inside the camera module\nneeds to be added; along with autofocus and AEC/AGC (at the moment gain and exposure are buried deep within the camera config ROM).\n" }, { "path": "vhdl_rx/demo-top/framebuffer_top.vhd", "content": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.NUMERIC_STD.ALL;\n\n--Top Level Framebuffer and Video Output Design\n--Copyright (C) 2016 David Shah\n--Licensed under the MIT License\n\nentity framebuffer_top is\n port(\n --Video input port\n input_pixck : in std_logic;\n input_vsync : in std_logic;\n input_line_start : in std_logic;\n input_den : in std_logic;\n input_data_even : in std_logic_vector(23 downto 0);\n input_data_odd : in std_logic_vector(23 downto 0);\n \n --System/control inputs\n system_clock : in std_logic;\n system_reset : in std_logic;\n zoom_mode : in std_logic;\n freeze : in std_logic;\n \n --Video output port\n output_pixck : in std_logic;\n output_vsync : out std_logic;\n output_hsync : out std_logic;\n output_den : out std_logic;\n output_line_start : out std_logic;\n output_data : out std_logic_vector(23 downto 0);\n \n --DDR3 interface\n ddr3_addr : out std_logic_vector(14 downto 0);\n ddr3_ba : out std_logic_vector(2 downto 0);\n ddr3_cas_n : out std_logic;\n ddr3_ck_n : out std_logic_vector(0 downto 0);\n ddr3_ck_p : out std_logic_vector(0 downto 0);\n ddr3_cke : out std_logic_vector(0 downto 0);\n ddr3_ras_n : out std_logic;\n ddr3_reset_n : out std_logic;\n ddr3_we_n : out std_logic;\n ddr3_dq : inout std_logic_vector(31 downto 0);\n ddr3_dqs_n : inout std_logic_vector(3 downto 0);\n ddr3_dqs_p : inout std_logic_vector(3 downto 0);\n ddr3_cs_n : out std_logic_vector(0 downto 0);\n ddr3_dm : out std_logic_vector(3 downto 0);\n ddr3_odt : out std_logic_vector(0 downto 0)\n );\nend framebuffer_top;\n\narchitecture Behavioral of framebuffer_top is\n signal ui_clock : std_logic;\n signal axi_resetn : std_logic;\n \n signal axi_awid : std_logic_vector(0 downto 0);\n signal axi_awaddr : std_logic_vector(29 downto 0);\n signal axi_awlen : std_logic_vector(7 downto 0);\n signal axi_awsize : std_logic_vector(2 downto 0);\n signal axi_awburst : std_logic_vector(1 downto 0);\n signal axi_awlock : std_logic_vector(0 downto 0);\n signal axi_awcache : std_logic_vector(3 downto 0);\n signal axi_awprot : std_logic_vector(2 downto 0);\n signal axi_awqos : std_logic_vector(3 downto 0);\n signal axi_awvalid : std_logic;\n signal axi_awready : std_logic;\n \n signal axi_wdata : std_logic_vector(255 downto 0);\n signal axi_wstrb : std_logic_vector(31 downto 0);\n signal axi_wlast : std_logic;\n signal axi_wvalid : std_logic;\n signal axi_wready : std_logic;\n \n signal axi_bid : std_logic_vector(0 downto 0);\n signal axi_bresp : std_logic_vector(1 downto 0);\n signal axi_bvalid : std_logic;\n signal axi_bready : std_logic;\n \n signal axi_arid : std_logic_vector(0 downto 0);\n signal axi_araddr : std_logic_vector(29 downto 0);\n signal axi_arlen : std_logic_vector(7 downto 0);\n signal axi_arsize : std_logic_vector(2 downto 0);\n signal axi_arburst : std_logic_vector(1 downto 0);\n signal axi_arlock : std_logic_vector(0 downto 0);\n signal axi_arcache : std_logic_vector(3 downto 0);\n signal axi_arprot : std_logic_vector(2 downto 0);\n signal axi_arqos : std_logic_vector(3 downto 0);\n signal axi_arvalid : std_logic;\n signal axi_arready : std_logic;\n \n signal axi_rid : std_logic_vector(0 downto 0);\n signal axi_rdata : std_logic_vector(255 downto 0);\n signal axi_rresp : std_logic_vector(1 downto 0);\n signal axi_rlast : std_logic;\n signal axi_rvalid : std_logic;\n signal axi_rready : std_logic;\n \n signal fbc_ovsync : std_logic;\n signal fbc_data : std_logic_vector(23 downto 0);\n \n signal output_line_start_int : std_logic;\n signal output_den_int : std_logic;\n \n component ddr3_if is\n port(\n ddr3_addr : out std_logic_vector(14 downto 0);\n ddr3_ba : out std_logic_vector(2 downto 0);\n ddr3_cas_n : out std_logic;\n ddr3_ck_n : out std_logic_vector(0 downto 0);\n ddr3_ck_p : out std_logic_vector(0 downto 0);\n ddr3_cke : out std_logic_vector(0 downto 0);\n ddr3_ras_n : out std_logic;\n ddr3_reset_n : out std_logic;\n ddr3_we_n : out std_logic;\n ddr3_dq : inout std_logic_vector(31 downto 0);\n ddr3_dqs_n : inout std_logic_vector(3 downto 0);\n ddr3_dqs_p : inout std_logic_vector(3 downto 0);\n init_calib_complete : out std_logic;\n ddr3_cs_n : out std_logic_vector(0 downto 0);\n ddr3_dm : out std_logic_vector(3 downto 0);\n ddr3_odt : out std_logic_vector(0 downto 0);\n \n ui_clk : out std_logic;\n ui_clk_sync_rst : out std_logic;\n mmcm_locked : out std_logic;\n aresetn : in std_logic;\n app_sr_req : in std_logic;\n app_ref_req : in std_logic;\n app_zq_req : in std_logic;\n app_sr_active : out std_logic;\n app_ref_ack : out std_logic;\n app_zq_ack : out std_logic;\n \n s_axi_awid : in std_logic_vector(0 downto 0);\n s_axi_awaddr : in std_logic_vector(29 downto 0);\n s_axi_awlen : in std_logic_vector(7 downto 0);\n s_axi_awsize : in std_logic_vector(2 downto 0);\n s_axi_awburst : in std_logic_vector(1 downto 0);\n s_axi_awlock : in std_logic_vector(0 downto 0);\n s_axi_awcache : in std_logic_vector(3 downto 0);\n s_axi_awprot : in std_logic_vector(2 downto 0);\n s_axi_awqos : in std_logic_vector(3 downto 0);\n s_axi_awvalid : in std_logic;\n s_axi_awready : out std_logic;\n \n s_axi_wdata : in std_logic_vector(255 downto 0);\n s_axi_wstrb : in std_logic_vector(31 downto 0);\n s_axi_wlast : in std_logic;\n s_axi_wvalid : in std_logic;\n s_axi_wready : out std_logic;\n \n s_axi_bid : out std_logic_vector(0 downto 0);\n s_axi_bresp : out std_logic_vector(1 downto 0);\n s_axi_bvalid : out std_logic;\n s_axi_bready : in std_logic;\n \n s_axi_arid : in std_logic_vector(0 downto 0);\n s_axi_araddr : in std_logic_vector(29 downto 0);\n s_axi_arlen : in std_logic_vector(7 downto 0);\n s_axi_arsize : in std_logic_vector(2 downto 0);\n s_axi_arburst : in std_logic_vector(1 downto 0);\n s_axi_arlock : in std_logic_vector(0 downto 0);\n s_axi_arcache : in std_logic_vector(3 downto 0);\n s_axi_arprot : in std_logic_vector(2 downto 0);\n s_axi_arqos : in std_logic_vector(3 downto 0);\n s_axi_arvalid : in std_logic;\n s_axi_arready : out std_logic;\n \n s_axi_rid : out std_logic_vector(0 downto 0);\n s_axi_rdata : out std_logic_vector(255 downto 0);\n s_axi_rresp : out std_logic_vector(1 downto 0);\n s_axi_rlast : out std_logic;\n s_axi_rvalid : out std_logic;\n s_axi_rready : in std_logic;\n \n sys_clk_i : in std_logic;\n sys_rst : in std_logic\n );\n end component;\n\nbegin\n \n axi_resetn <= not system_reset;\n \n fbctl : entity work.framebuffer_ctrl_crop_scale\n generic map(\n burst_len => 16,\n input_width => 3840,\n input_height => 2160,\n output_width => 1920,\n output_height => 1080,\n crop_xoffset => 1024,\n crop_yoffset => 540,\n scale_xoffset => 0,\n scale_yoffset => 0)\n port map(\n input_clock => input_pixck,\n input_vsync => input_vsync,\n input_line_start => input_line_start,\n input_den => input_den,\n input_data_even => input_data_even,\n input_data_odd => input_data_odd,\n \n output_clock => output_pixck,\n output_vsync => fbc_ovsync,\n output_line_start => output_line_start_int,\n output_den => output_den_int,\n output_data => fbc_data,\n \n axi_clock => ui_clock,\n axi_resetn => axi_resetn,\n \n axi_awid => axi_awid,\n axi_awaddr => axi_awaddr,\n axi_awlen => axi_awlen,\n axi_awsize => axi_awsize,\n axi_awburst => axi_awburst,\n axi_awlock => axi_awlock,\n axi_awcache => axi_awcache,\n axi_awprot => axi_awprot,\n axi_awqos => axi_awqos,\n axi_awvalid => axi_awvalid,\n axi_awready => axi_awready,\n \n axi_wdata => axi_wdata,\n axi_wstrb => axi_wstrb,\n axi_wlast => axi_wlast,\n axi_wvalid => axi_wvalid,\n axi_wready => axi_wready,\n \n axi_bid => axi_bid,\n axi_bresp => axi_bresp,\n axi_bvalid => axi_bvalid,\n axi_bready => axi_bready,\n \n axi_arid => axi_arid,\n axi_araddr => axi_araddr,\n axi_arlen => axi_arlen,\n axi_arsize => axi_arsize,\n axi_arburst => axi_arburst,\n axi_arlock => axi_arlock,\n axi_arcache => axi_arcache,\n axi_arprot => axi_arprot,\n axi_arqos => axi_arqos,\n axi_arvalid => axi_arvalid,\n axi_arready => axi_arready,\n \n axi_rid => axi_rid,\n axi_rdata => axi_rdata,\n axi_rresp => axi_rresp,\n axi_rlast => axi_rlast,\n axi_rvalid => axi_rvalid,\n axi_rready => axi_rready,\n \n zoom_mode => zoom_mode,\n freeze => freeze\n );\n \n output : entity work.video_fb_output\n generic map(\n video_hlength => 2200,\n video_vlength => 1125,\n \n video_hsync_pol => true,\n video_hsync_len => 44,\n video_hbp_len => 148,\n video_h_visible => 1920,\n \n video_vsync_pol => true,\n video_vsync_len => 5,\n video_vbp_len => 36,\n video_v_visible => 1080)\n port map(\n pixel_clock => output_pixck,\n reset => system_reset,\n \n fbc_vsync => fbc_ovsync,\n fbc_data => fbc_data,\n \n video_vsync => output_vsync,\n video_hsync => output_hsync,\n video_den => output_den_int,\n video_line_start => output_line_start_int,\n video_data => output_data);\n \n output_den <= output_den_int;\n output_line_start <= output_line_start_int;\n \n memctl : ddr3_if\n port map(\n ddr3_addr => ddr3_addr,\n ddr3_ba => ddr3_ba,\n ddr3_cas_n => ddr3_cas_n,\n ddr3_ck_n => ddr3_ck_n,\n ddr3_ck_p => ddr3_ck_p,\n ddr3_cke => ddr3_cke,\n ddr3_ras_n => ddr3_ras_n,\n ddr3_reset_n => ddr3_reset_n,\n ddr3_we_n => ddr3_we_n,\n ddr3_dq => ddr3_dq,\n ddr3_dqs_p => ddr3_dqs_p,\n ddr3_dqs_n => ddr3_dqs_n,\n init_calib_complete => open,\n ddr3_cs_n => ddr3_cs_n,\n ddr3_dm => ddr3_dm,\n ddr3_odt => ddr3_odt,\n \n ui_clk => ui_clock,\n ui_clk_sync_rst => open,\n mmcm_locked => open,\n aresetn => axi_resetn,\n app_sr_req => '0',\n app_ref_req => '0',\n app_zq_req => '0',\n app_sr_active => open,\n app_ref_ack => open,\n app_zq_ack => open,\n \n s_axi_awid => axi_awid,\n s_axi_awaddr => axi_awaddr,\n s_axi_awlen => axi_awlen,\n s_axi_awsize => axi_awsize,\n s_axi_awburst => axi_awburst,\n s_axi_awlock => axi_awlock,\n s_axi_awcache => axi_awcache,\n s_axi_awprot => axi_awprot,\n s_axi_awqos => axi_awqos,\n s_axi_awvalid => axi_awvalid,\n s_axi_awready => axi_awready,\n \n s_axi_wdata => axi_wdata,\n s_axi_wstrb => axi_wstrb,\n s_axi_wlast => axi_wlast,\n s_axi_wvalid => axi_wvalid,\n s_axi_wready => axi_wready,\n \n s_axi_bid => axi_bid,\n s_axi_bresp => axi_bresp,\n s_axi_bvalid => axi_bvalid,\n s_axi_bready => axi_bready,\n \n s_axi_arid => axi_arid,\n s_axi_araddr => axi_araddr,\n s_axi_arlen => axi_arlen,\n s_axi_arsize => axi_arsize,\n s_axi_arburst => axi_arburst,\n s_axi_arlock => axi_arlock,\n s_axi_arcache => axi_arcache,\n s_axi_arprot => axi_arprot,\n s_axi_arqos => axi_arqos,\n s_axi_arvalid => axi_arvalid,\n s_axi_arready => axi_arready,\n \n s_axi_rid => axi_rid,\n s_axi_rdata => axi_rdata,\n s_axi_rresp => axi_rresp,\n s_axi_rlast => axi_rlast,\n s_axi_rvalid => axi_rvalid,\n s_axi_rready => axi_rready,\n \n sys_clk_i => system_clock,\n sys_rst => '1');\n\nend Behavioral;\n" }, { "path": "vhdl_rx/demo-top/mig_a.prj", "content": "\n\n\n ddr3_if\n 1\n 1\n OFF\n 1024\n ON\n Enabled\n xc7k325t-ffg900/-2\n 4.0\n No Buffer\n Use System Clock\n ACTIVE LOW\n FALSE\n 0\n OFF\n 0\n \n DDR3_SDRAM/Components/MT41J256m16XX-107\n 1250\n 2.0V\n 4:1\n 200\n 0\n 800\n 1.000\n 1\n 1\n 1\n 1\n 32\n 1\n 1\n Disabled\n Normal\n 2\n FALSE\n \n 15\n 10\n 3\n 1.5V\n ROW_BANK_COLUMN\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 8 - Fixed\n Sequential\n 11\n Normal\n No\n Slow Exit\n Enable\n RZQ/7\n Disable\n Enable\n RZQ/6\n 0\n Disabled\n Enabled\n Output Buffer Enabled\n Full Array\n 8\n Enabled\n Normal\n Dynamic ODT off\n AXI\n \n RD_PRI_REG_STARVE_LIMIT\n 30\n 256\n 1\n 0\n \n \n\n\n" }, { "path": "vhdl_rx/demo-top/ov13850_demo.vhd", "content": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.NUMERIC_STD.ALL;\n\nlibrary UNISIM;\nuse UNISIM.VComponents.all;\n\n--OV13850 Demo Top Level Design\n--Copyright (C) 2016 David Shah\n--Licensed under the MIT License\n\nentity ov13850_demo is\n Port (\n clock_p : in std_logic;\n clock_n : in std_logic;\n reset_n : in std_logic;\n\n hdmi_clk : out std_logic_vector(1 downto 0);\n hdmi_d0 : out std_logic_vector(1 downto 0);\n hdmi_d1 : out std_logic_vector(1 downto 0);\n hdmi_d2 : out std_logic_vector(1 downto 0);\n \n vga_hsync : out std_logic;\n vga_vsync : out std_logic;\n vga_r : out std_logic_vector(4 downto 0);\n vga_g : out std_logic_vector(5 downto 0);\n vga_b : out std_logic_vector(4 downto 0);\n\n zoom_mode : in std_logic;\n freeze : in std_logic;\n\n --Camera CSI port\n csi0_clk : in std_logic_vector(1 downto 0);\n csi0_d0 : in std_logic_vector(1 downto 0);\n csi0_d1 : in std_logic_vector(1 downto 0);\n csi0_d2 : in std_logic_vector(1 downto 0);\n csi0_d3 : in std_logic_vector(1 downto 0);\n\n --Camera control port\n cam_mclk : out std_logic;\n cam_rstn : out std_logic;\n cam_i2c_sda : inout std_logic;\n cam_i2c_sck : inout std_logic;\n\n --DDR3 interface\n ddr3_addr : out std_logic_vector(14 downto 0);\n ddr3_ba : out std_logic_vector(2 downto 0);\n ddr3_cas_n : out std_logic;\n ddr3_ck_n : out std_logic_vector(0 downto 0);\n ddr3_ck_p : out std_logic_vector(0 downto 0);\n ddr3_cke : out std_logic_vector(0 downto 0);\n ddr3_ras_n : out std_logic;\n ddr3_reset_n : out std_logic;\n ddr3_we_n : out std_logic;\n ddr3_dq : inout std_logic_vector(31 downto 0);\n ddr3_dqs_n : inout std_logic_vector(3 downto 0);\n ddr3_dqs_p : inout std_logic_vector(3 downto 0);\n ddr3_cs_n : out std_logic_vector(0 downto 0);\n ddr3_dm : out std_logic_vector(3 downto 0);\n ddr3_odt : out std_logic_vector(0 downto 0)\n );\nend ov13850_demo;\n\narchitecture Behavioral of ov13850_demo is\n\n signal sys_clock : std_logic;\n\n signal reset : std_logic;\n signal dvi_pixel_clock, dvi_bit_clock : std_logic;\n\n signal dvi_data : std_logic_vector(23 downto 0);\n signal dvi_den, dvi_hsync, dvi_vsync : std_logic;\n\n signal i2c_clk_in, i2c_clk_div_1, i2c_clk_div : std_logic;\n signal cam_loading, csi_en, csi_rst : std_logic;\n\n signal camera_rstn_int : std_logic;\n signal input_pixel_clock : std_logic;\n\n signal camera_line_start, camera_den, camera_hsync, camera_vsync, camera_odd_line : std_logic;\n signal camera_data, camera_prev_line_data : std_logic_vector(19 downto 0);\n\n signal debayer_line_start, debayer_den, debayer_hsync, debayer_vsync : std_logic;\n signal debayer_data_even, debayer_data_odd : std_logic_vector(29 downto 0);\n\n signal fbin_line_start, fbin_den, fbin_hsync, fbin_vsync : std_logic;\n signal fbin_data_even, fbin_data_odd : std_logic_vector(23 downto 0);\n\n component dvi_pll is\n port(\n sysclk : in std_logic;\n pixel_clock : out std_logic;\n dvi_bit_clock : out std_logic);\n end component;\n\n component camera_pll is\n port(\n sysclk : in std_logic;\n camera_pixel_clock : out std_logic;\n camera_mclk : out std_logic;\n i2c_clkin : out std_logic);\n end component;\n\n\nbegin\n reset <= not reset_n;\n\n clkbuf : IBUFGDS\n generic map(\n DIFF_TERM => TRUE,\n IBUF_LOW_PWR => FALSE,\n IOSTANDARD => \"DEFAULT\")\n port map(\n O => sys_clock,\n I => clock_p,\n IB => clock_n);\n\n pll1 : dvi_pll\n port map(\n sysclk => sys_clock,\n pixel_clock => dvi_pixel_clock,\n dvi_bit_clock => dvi_bit_clock\n );\n\n pll2 : camera_pll\n port map(\n sysclk => sys_clock,\n camera_pixel_clock => input_pixel_clock,\n camera_mclk => cam_mclk,\n i2c_clkin => i2c_clk_in\n );\n\n --Divide 5MHz from PLL to slower I2C/reset controller input clock\n i2c_clkdiv : BUFR\n generic map(\n BUFR_DIVIDE => \"8\",\n SIM_DEVICE => \"7SERIES\")\n port map(\n O => i2c_clk_div_1,\n CE => '1',\n CLR => reset,\n I => i2c_clk_in);\n\n i2c_clkdiv2 : BUFR\n generic map(\n BUFR_DIVIDE => \"4\",\n SIM_DEVICE => \"7SERIES\")\n port map(\n O => i2c_clk_div,\n CE => '1',\n CLR => reset,\n I => i2c_clk_div_1);\n\n cam_ctl : entity work.ov13850_control_top\n port map (\n reset => reset,\n clock => i2c_clk_div,\n i2c_sda => cam_i2c_sda,\n i2c_sck => cam_i2c_sck,\n rst_out => camera_rstn_int,\n loading_out => cam_loading);\n\n cam_rstn <= camera_rstn_int;\n csi_rst <= not camera_rstn_int;\n csi_en <= not cam_loading;\n\n csi_rx : entity work.csi_rx_4lane\n generic map(\n fpga_series => \"7SERIES\",\n dphy_term_en => true,\n d0_invert => false,\n d1_invert => false,\n d2_invert => false,\n d3_invert => false,\n d0_skew => 10,\n d1_skew => 10,\n d2_skew => 10,\n d3_skew => 10,\n video_hlength => 4041,\n video_vlength => 2992,\n video_hsync_pol => true,\n video_hsync_len => 48,\n video_hbp_len => 122,\n video_h_visible => 3840,\n video_vsync_pol => true,\n video_vsync_len => 3,\n video_vbp_len => 23 ,\n video_v_visible => 2160,\n pixels_per_clock => 2,\n generate_idelayctrl => true)\n port map(\n ref_clock_in => sys_clock,\n pixel_clock_in => input_pixel_clock,\n byte_clock_out => open,\n enable => csi_en,\n reset => csi_rst,\n video_valid => open,\n\n dphy_clk => csi0_clk,\n dphy_d0 => csi0_d0,\n dphy_d1 => csi0_d1,\n dphy_d2 => csi0_d2,\n dphy_d3 => csi0_d3,\n\n video_hsync => camera_hsync,\n video_vsync => camera_vsync,\n video_den => camera_den,\n video_line_start => camera_line_start,\n video_odd_line => camera_odd_line,\n video_data => camera_data,\n video_prev_line_data => camera_prev_line_data);\n\n db : entity work.simple_debayer\n port map(\n clock => input_pixel_clock,\n input_vsync => camera_vsync,\n input_hsync => camera_hsync,\n input_den => camera_den,\n input_odd_line => camera_odd_line,\n input_line_start => camera_line_start,\n input_data => camera_data,\n input_prev_line_data => camera_prev_line_data,\n \n output_vsync => debayer_vsync,\n output_hsync => debayer_hsync,\n output_den => debayer_den,\n output_line_start => debayer_line_start,\n output_data_even => debayer_data_even,\n output_data_odd => debayer_data_odd);\n\n wb : entity work.image_gain_wb\n generic map(\n red_gain => 10,\n green_gain => 7,\n blue_gain => 9)\n port map(\n clock => input_pixel_clock,\n input_vsync => debayer_vsync,\n input_hsync => debayer_hsync,\n input_den => debayer_den,\n input_line_start => debayer_line_start,\n input_data_even => debayer_data_even,\n input_data_odd => debayer_data_odd,\n \n output_vsync => fbin_vsync,\n output_hsync => fbin_hsync,\n output_den => fbin_den,\n output_line_start => fbin_line_start,\n output_data_even => fbin_data_even,\n output_data_odd => fbin_data_odd);\n\n fbtest : entity work.framebuffer_top\n port map(\n input_pixck => input_pixel_clock,\n input_vsync => fbin_vsync,\n input_line_start => fbin_line_start,\n input_den => fbin_den,\n input_data_even => fbin_data_even,\n input_data_odd => fbin_data_odd,\n\n system_clock => sys_clock,\n system_reset => reset,\n zoom_mode => zoom_mode,\n freeze => freeze,\n\n output_pixck => dvi_pixel_clock,\n output_vsync => dvi_vsync,\n output_hsync => dvi_hsync,\n output_den => dvi_den,\n output_line_start => open,\n output_data => dvi_data,\n\n --DDR3 interface\n ddr3_addr => ddr3_addr,\n ddr3_ba => ddr3_ba,\n ddr3_cas_n => ddr3_cas_n,\n ddr3_ck_n => ddr3_ck_n,\n ddr3_ck_p => ddr3_ck_p,\n ddr3_cke => ddr3_cke,\n ddr3_ras_n => ddr3_ras_n,\n ddr3_reset_n => ddr3_reset_n,\n ddr3_we_n => ddr3_we_n,\n ddr3_dq => ddr3_dq,\n ddr3_dqs_n => ddr3_dqs_n,\n ddr3_dqs_p => ddr3_dqs_p,\n ddr3_cs_n => ddr3_cs_n,\n ddr3_dm => ddr3_dm,\n ddr3_odt => ddr3_odt\n );\n\n dvi_tx : entity work.dvi_tx\n port map(\n pixel_clock => dvi_pixel_clock,\n ddr_bit_clock => dvi_bit_clock,\n reset => reset,\n den => dvi_den,\n hsync => dvi_hsync,\n vsync => dvi_vsync,\n pixel_data => dvi_data,\n\n tmds_clk => hdmi_clk,\n tmds_d0 => hdmi_d0,\n tmds_d1 => hdmi_d1,\n tmds_d2 => hdmi_d2\n );\n \n vga_hsync <= dvi_hsync;\n vga_vsync <= dvi_vsync;\n vga_r <= dvi_data(23 downto 19);\n vga_g <= dvi_data(15 downto 10);\n vga_b <= dvi_data(7 downto 3);\nend Behavioral;\n" }, { "path": "vhdl_rx/dvi-tx/dvi_tx_clk_drv.vhd", "content": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\n\nlibrary UNISIM;\nuse UNISIM.VComponents.all;\n\n--DVI Transmitter clock lane driver\n--Copyright (C) 2016 David Shah\n--Licensed under the MIT License\n\n--This drives the TMDS clock lane, taking the pixel clock as input\nentity dvi_tx_clk_drv is\n port(\n pixel_clock : in std_logic;\n tmds_clk : out std_logic_vector(1 downto 0));\nend dvi_tx_clk_drv;\n\narchitecture Behavioral of dvi_tx_clk_drv is\n signal tmds_clk_pre : std_logic;\nbegin\n --Using an ODDR simplifies clock routing and avoids the need for a clock capable output\n clk_oddr : ODDR\n generic map(\n DDR_CLK_EDGE => \"OPPOSITE_EDGE\",\n INIT => '0',\n SRTYPE => \"SYNC\")\n port map(\n Q => tmds_clk_pre,\n C => pixel_clock,\n CE => '1',\n D1 => '1',\n D2 => '0',\n R => '0',\n S => '0');\n\n clk_obuf : OBUFDS\n generic map (\n IOSTANDARD => \"DEFAULT\",\n SLEW => \"FAST\")\n port map (\n O => tmds_clk(1),\n OB => tmds_clk(0),\n I => tmds_clk_pre);\nend Behavioral;\n" }, { "path": "vhdl_rx/dvi-tx/dvi_tx_tmds_enc.vhd", "content": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.NUMERIC_STD.ALL;\n\n--DVI Transmitter TMDS encoder\n--Copyright (C) 2016 David Shah\n--Licensed under the MIT License\n\n--This encodes TMDS 'characters' according to the algorithm in the DVI specification\n\nentity dvi_tx_tmds_enc is\n port(\n clock : in std_logic; --TMDS character clock\n reset : in std_logic; --synchronous reset input\n den : in std_logic; --display data enable\n data : in std_logic_vector(7 downto 0); --8bit display data\n ctrl : in std_logic_vector(1 downto 0); --2bit control (vsync+hsync for ch0)\n tmds : out std_logic_vector(9 downto 0) --10bit encoded TMDS to transmit\n );\nend dvi_tx_tmds_enc;\n\narchitecture Behavioral of dvi_tx_tmds_enc is\n signal data_lat : std_logic_vector(7 downto 0);\n signal den_lat : std_logic;\n signal ctrl_lat : std_logic_vector(1 downto 0);\n signal tmds_int : std_logic_vector(9 downto 0);\n signal cnt_q : integer range -256 to 255;\n signal cnt_d : integer range -256 to 255;\n\n signal q_m : std_logic_vector(8 downto 0);\n\n function count_ones(x : std_logic_vector) return integer is\n variable count : natural := 0;\n begin\n for i in x'range loop\n if x(i) = '1' then\n count := count + 1;\n end if;\n end loop;\n return count;\n end function;\n\n function count_zeros(x : std_logic_vector) return integer is\n variable count : natural := 0;\n begin\n for i in x'range loop\n if x(i) = '0' then\n count := count + 1;\n end if;\n end loop;\n return count;\n end function;\n\nbegin\n\n process(clock)\n begin\n if rising_edge(clock) then\n if reset = '1' then\n data_lat <= (others => '0');\n ctrl_lat <= (others => '0');\n den_lat <= '0';\n tmds <= (others => '0');\n cnt_q <= 0;\n else\n data_lat <= data;\n den_lat <= den;\n ctrl_lat <= ctrl;\n tmds <= tmds_int;\n cnt_q <= cnt_d;\n end if;\n end if;\n end process;\n\n process(data_lat)\n variable q_m_temp : std_logic_vector(8 downto 0);\n begin\n q_m_temp(0) := data_lat(0);\n if count_ones(data_lat) > 4 or ((count_ones(data_lat) = 4) and data_lat(0) = '0') then\n for i in 1 to 7 loop\n q_m_temp(i) := not(q_m_temp(i-1) xor data_lat(i));\n end loop;\n q_m_temp(8) := '0';\n else\n for i in 1 to 7 loop\n q_m_temp(i) := q_m_temp(i-1) xor data_lat(i);\n end loop;\n q_m_temp(8) := '1';\n end if;\n q_m <= q_m_temp;\n end process;\n\n process(cnt_q, q_m, den_lat, ctrl_lat)\n variable q_out : std_logic_vector(9 downto 0);\n begin\n if den_lat = '0' then\n cnt_d <= 0;\n case ctrl_lat is\n when \"00\" =>\n q_out := \"1101010100\";\n when \"01\" =>\n q_out := \"0010101011\";\n when \"10\" =>\n q_out := \"0101010100\";\n when \"11\" =>\n q_out := \"1010101011\";\n when others => --never occurs in synthesised system but keeps sims happy\n q_out := \"0000000000\";\n end case;\n else\n if cnt_q = 0 or count_ones(q_m(7 downto 0)) = 4 then\n q_out(9) := not q_m(8);\n q_out(8) := q_m(8);\n if q_m(8) = '1' then\n q_out(7 downto 0) := q_m(7 downto 0);\n cnt_d <= cnt_q + 2 * (count_ones(q_m(7 downto 0)) - 4);\n else\n q_out(7 downto 0) := not q_m(7 downto 0);\n cnt_d <= cnt_q + 2 * (4 - count_ones(q_m(7 downto 0)));\n end if;\n else\n if ((cnt_q > 0) and (count_ones(q_m(7 downto 0)) > 4))\n or ((cnt_q < 0) and (count_ones(q_m(7 downto 0)) < 4)) then\n q_out(9) := '1';\n q_out(8) := q_m(8);\n q_out(7 downto 0) := not q_m(7 downto 0);\n if q_m(8) = '1' then\n cnt_d <= cnt_q + 2 + 2 * (4 - count_ones(q_m(7 downto 0)));\n else\n cnt_d <= cnt_q + 2 * (4 - count_ones(q_m(7 downto 0)));\n end if;\n else\n q_out(9) := '0';\n q_out(8) := q_m(8);\n q_out(7 downto 0) := q_m(7 downto 0);\n if q_m(8) = '0' then\n cnt_d <= (cnt_q - 2) + 2 * (count_ones(q_m(7 downto 0)) - 4);\n else\n cnt_d <= cnt_q + 2 * (count_ones(q_m(7 downto 0)) - 4);\n end if;\n end if;\n end if;\n end if;\n tmds_int <= q_out;\n end process;\nend Behavioral;\n" }, { "path": "vhdl_rx/dvi-tx/dvi_tx_tmds_phy.vhd", "content": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\n\nlibrary UNISIM;\nuse UNISIM.VComponents.all;\n\n--DVI Transmitter TMDS PHY for Xilinx 7-series devices\n--Copyright (C) 2016 David Shah\n--Licensed under the MIT License\n\n--This handles the actual serialisation and transmission of 10bit encoded\n--TMDS data\n\nentity dvi_tx_tmds_phy is\n port(\n pixel_clock : in std_logic; --DVI pixel clock in\n ddr_bit_clock : in std_logic; --DDR bit clock i.e. pixel_clock*5 - must be from same MMCM/PLL as pixel_clock\n reset : in std_logic; --SERDES reset input\n data : in std_logic_vector(9 downto 0);\n tmds_lane : out std_logic_vector(1 downto 0) --1 is P, 0 is N\n );\nend dvi_tx_tmds_phy;\n\narchitecture Behavioral of dvi_tx_tmds_phy is\n signal reset_lat : std_logic; --reset latched to pixel clock\n signal shift_1, shift_2 : std_logic; --used to link master and slave OSERDES\n signal data_se : std_logic; --serialised data before output buffer\nbegin\n process(pixel_clock)\n begin\n if rising_edge(pixel_clock) then\n reset_lat <= reset;\n end if;\n end process;\n\n master_oserdes : OSERDESE2\n generic map(\n DATA_RATE_OQ => \"DDR\",\n DATA_RATE_TQ => \"SDR\",\n DATA_WIDTH => 10,\n INIT_OQ => '0',\n INIT_TQ => '0',\n SERDES_MODE => \"MASTER\",\n SRVAL_OQ => '0',\n SRVAL_TQ => '0',\n TBYTE_CTL => \"FALSE\",\n TBYTE_SRC => \"FALSE\",\n TRISTATE_WIDTH => 1)\n port map(\n CLK => ddr_bit_clock,\n CLKDIV => pixel_clock,\n D1 => data(0),\n D2 => data(1),\n D3 => data(2),\n D4 => data(3),\n D5 => data(4),\n D6 => data(5),\n D7 => data(6),\n D8 => data(7),\n OCE => '1',\n OFB => open,\n OQ => data_se,\n RST => reset_lat,\n SHIFTIN1 => shift_1,\n SHIFTIN2 => shift_2,\n SHIFTOUT1 => open,\n SHIFTOUT2 => open,\n TBYTEIN => '0',\n TCE => '1',\n TFB => open,\n TQ => open,\n T1 => '0',\n T2 => '0',\n T3 => '0',\n T4 => '0');\n\n slave_oserdes : OSERDESE2\n generic map(\n DATA_RATE_OQ => \"DDR\",\n DATA_RATE_TQ => \"SDR\",\n DATA_WIDTH => 10,\n INIT_OQ => '0',\n INIT_TQ => '0',\n SERDES_MODE => \"SLAVE\",\n SRVAL_OQ => '0',\n SRVAL_TQ => '0',\n TBYTE_CTL => \"FALSE\",\n TBYTE_SRC => \"FALSE\",\n TRISTATE_WIDTH => 1)\n port map(\n CLK => ddr_bit_clock,\n CLKDIV => pixel_clock,\n D1 => '0',\n D2 => '0',\n D3 => data(8),\n D4 => data(9),\n D5 => '0',\n D6 => '0',\n D7 => '0',\n D8 => '0',\n OCE => '1',\n OFB => open,\n OQ => open,\n RST => reset_lat,\n SHIFTIN1 => '0',\n SHIFTIN2 => '0',\n SHIFTOUT1 => shift_1,\n SHIFTOUT2 => shift_2,\n TBYTEIN => '0',\n TCE => '1',\n TFB => open,\n TQ => open,\n T1 => '0',\n T2 => '0',\n T3 => '0',\n T4 => '0');\n\n outbuf : OBUFDS\n generic map (\n IOSTANDARD => \"DEFAULT\",\n SLEW => \"FAST\")\n port map (\n O => tmds_lane(1),\n OB => tmds_lane(0),\n I => data_se);\nend Behavioral;\n" }, { "path": "vhdl_rx/dvi-tx/dvi_tx_top.vhd", "content": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\n\n--Simple DVI Transmitter for Xilinx 7-series devices\n--Copyright (C) 2016 David Shah\n--Licensed under the MIT License\n\n--This is a minimal DVI transmitter core designed for Xilinx 7-series devices\n--and tested using the HDMI output the Digilent Genesys 2 board (Kintex-7 XC7K325T)\n\nentity dvi_tx is\n port(\n pixel_clock : in std_logic; --pixel clock input\n ddr_bit_clock : in std_logic; --DDR bit clock i.e. pixel_clock*5 - must be from same MMCM/PLL as pixel_clock\n reset : in std_logic; --synchronous active high reset input\n den : in std_logic; --video data valid input (active high)\n hsync : in std_logic; --video hsync input (polarity is timing dependent)\n vsync : in std_logic; --video vsync input (polarity is timing dependent)\n pixel_data : in std_logic_vector(23 downto 0); --24-bit video data\n\n tmds_clk : out std_logic_vector(1 downto 0); --TMDS clock lane; 1 is P, 0 is N\n tmds_d0 : out std_logic_vector(1 downto 0); --TMDS data lanes; 1 is P, 0 is N\n tmds_d1 : out std_logic_vector(1 downto 0);\n tmds_d2 : out std_logic_vector(1 downto 0));\nend dvi_tx;\n\narchitecture Behavioral of dvi_tx is\n signal ctrl : std_logic_vector(5 downto 0); --TMDS control signal states\n signal tmds_enc : std_logic_vector(29 downto 0); --TMDS encoded data\n\n type tmds_lanes_t is array (0 to 2) of std_logic_vector(1 downto 0);\n signal tmds_lanes : tmds_lanes_t;\n\nbegin\n ctrl(0) <= hsync;\n ctrl(1) <= vsync;\n ctrl(5 downto 2) <= \"0000\";\n\n gen_lane : for i in 0 to 2 generate\n lane_enc : entity work.dvi_tx_tmds_enc\n port map(\n clock => pixel_clock,\n reset => reset,\n den => den,\n data => pixel_data(((8*i) + 7) downto (8*i)),\n ctrl => ctrl(((2*i) + 1) downto (2*i)),\n tmds => tmds_enc( ((10*i) + 9) downto (10*i)));\n\n lane_phy : entity work.dvi_tx_tmds_phy\n port map(\n pixel_clock => pixel_clock,\n ddr_bit_clock => ddr_bit_clock,\n reset => reset,\n data => tmds_enc( ((10*i) + 9) downto (10*i)),\n tmds_lane => tmds_lanes(i));\n end generate;\n\n clock_phy : entity work.dvi_tx_clk_drv\n port map(\n pixel_clock => pixel_clock,\n tmds_clk => tmds_clk);\n\n tmds_d0 <= tmds_lanes(0);\n tmds_d1 <= tmds_lanes(1);\n tmds_d2 <= tmds_lanes(2);\n\nend Behavioral;\n" }, { "path": "vhdl_rx/examples/.gitignore", "content": "#########################################################################################################\n##\tThis is an example .gitignore file for Vivado, please treat it as an example as\n##\tit might not be complete. In addition, XAPP 1165 should be followed.\n#########################################################################################################\n#########\n#Exclude all\n#########\n*\n!*/\n!.gitignore\n###########################################################################\n##\tVIVADO\n###########################################################################\n#########\n#Source files:\n#########\n#Do NOT ignore VHDL, Verilog, block diagrams or EDIF files.\n!*.vhd\n!*.v\n!*.bd\n!*.edif\n#########\n#IP files\n#########\n#.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products\n#.xci + .dcp: implementation possible but not re-synthesis\n#*.xci(www.spiritconsortium.org)\n!*.xci\n*.dcp(checkpoint files)\n#!*.dcp\n*.vds\n*.pb\n#All bd comments and layout coordinates are stored within .ui\n!*.ui\n!*.ooc\n#########\n#System Generator\n#########\n!*.mdl\n!*.slx\n!*.bxml\n#########\n#Simulation logic analyzer\n#########\n!*.wcfg\n!*.coe\n#########\n#MIG\n#########\n!*.prj\n!*.mem\n#########\n#Project files\n#########\n#XPR + *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version)\n#Do NOT ignore *.xpr files\n!*.xpr\n#Include *.xml files for 2013.4 or earlier version\n*.xml\n#########\n#Constraint files\n#########\n#Do NOT ignore *.xdc files\n!*.xdc\n#########\n#TCL - files\n#########\n!*.tcl\n#########\n#Journal - files\n#########\n*.jou\n#########\n#Reports\n#########\n*.rpt\n*.txt\n*.vdi\n#########\n#C-files\n#########\n!*.c\n!*.h\n!*.elf\n!*.bmm\n!*.xmp\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.cache/ip/54144841a4506c29/54144841a4506c29.xci", "content": "\n\n xilinx.com\n ipcache\n 54144841a4506c29\n 0\n \n \n dvi_pll\n \n \n MMCM\n false\n empty\n cddcdone\n cddcreq\n clkfb_in_n\n clkfb_in\n clkfb_in_p\n SINGLE\n clkfb_out_n\n clkfb_out\n clkfb_out_p\n clkfb_stopped\n 50.0\n 0.010\n 100.0\n 0.010\n BUFG\n 136.844\n false\n 157.836\n 50.000\n 124\n 0.000\n 1\n true\n BUFG\n 105.471\n false\n 157.836\n 50.000\n 620\n 0.000\n 1\n true\n BUFG\n 0.0\n false\n 0.0\n 50.000\n 100.000\n 0.000\n 1\n false\n BUFG\n 0.0\n false\n 0.0\n 50.000\n 100.000\n 0.000\n 1\n false\n BUFG\n 0.0\n false\n 0.0\n 50.000\n 100.000\n 0.000\n 1\n false\n BUFG\n 0.0\n false\n 0.0\n 50.000\n 100.000\n 0.000\n 1\n false\n BUFG\n 0.0\n false\n 0.0\n 50.000\n 100.000\n 0.000\n 1\n false\n 600.000\n Custom\n Custom\n clk_in_sel\n pixel_clock\n false\n dvi_bit_clock\n false\n clk_out3\n false\n clk_out4\n false\n clk_out5\n false\n clk_out6\n false\n clk_out7\n false\n CLK_VALID\n auto\n dvi_pll\n daddr\n dclk\n den\n Custom\n Custom\n din\n dout\n drdy\n dwe\n false\n false\n false\n false\n false\n false\n false\n false\n false\n FDBK_AUTO\n input_clk_stopped\n frequency\n Enable_AXI\n Units_MHz\n Units_UI\n UI\n No_Jitter\n locked\n OPTIMIZED\n 31\n 0.000\n false\n 5.0\n 10.0\n 10\n 0.500\n 0.000\n false\n 2\n 0.500\n 0.000\n false\n 1\n 0.500\n 0.000\n false\n 1\n 0.500\n 0.000\n false\n false\n 1\n 0.500\n 0.000\n false\n 1\n 0.500\n 0.000\n false\n 1\n 0.500\n 0.000\n false\n false\n ZHOLD\n 5\n None\n 0.010\n 0.010\n false\n 2\n false\n false\n WAVEFORM\n false\n UNKNOWN\n OPTIMIZED\n 4\n 0.000\n 10.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n CLKFBOUT\n SYSTEM_SYNCHRONOUS\n 1\n None\n 0.010\n power_down\n 1\n sysclk\n PLL\n mmcm_adv\n 200\n 0.010\n 10.000\n Global_buffer\n psclk\n psdone\n psen\n psincdec\n 100.0\n REL_PRIMARY\n Custom\n reset\n ACTIVE_HIGH\n 100.000\n 0.010\n 10.000\n clk_in2\n Single_ended_clock_capable_pin\n CENTER_HIGH\n 250\n 0.004\n STATUS\n empty\n 100.0\n 100.0\n 100.0\n 100.0\n false\n false\n false\n false\n false\n false\n false\n true\n false\n false\n false\n false\n false\n false\n true\n false\n false\n false\n false\n false\n kintex7\n \n xc7k325t\n ffg900\n VERILOG\n \n MIXED\n -2\n \n TRUE\n TRUE\n e2451eba\n 54144841a4506c29\n dvi_pll\n IP_Unknown\n 2\n TRUE\n .\n \n .\n 2016.3\n GLOBAL\n \n \n \n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.cache/ip/54144841a4506c29/dvi_pll_sim_netlist.v", "content": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// --------------------------------------------------------------------------------\n// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016\n// Date : Tue Nov 15 16:22:12 2016\n// Host : david-desktop-arch running 64-bit unknown\n// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix\n// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dvi_pll_sim_netlist.v\n// Design : dvi_pll\n// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified\n// or synthesized. This netlist cannot be used for SDF annotated simulation.\n// Device : xc7k325tffg900-2\n// --------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* NotValidForBitStream *)\nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix\n (pixel_clock,\n dvi_bit_clock,\n sysclk);\n output pixel_clock;\n output dvi_bit_clock;\n input sysclk;\n\n wire dvi_bit_clock;\n wire pixel_clock;\n wire sysclk;\n\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dvi_pll_clk_wiz inst\n (.dvi_bit_clock(dvi_bit_clock),\n .pixel_clock(pixel_clock),\n .sysclk(sysclk));\nendmodule\n\nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dvi_pll_clk_wiz\n (pixel_clock,\n dvi_bit_clock,\n sysclk);\n output pixel_clock;\n output dvi_bit_clock;\n input sysclk;\n\n wire clkfbout_buf_dvi_pll;\n wire clkfbout_dvi_pll;\n wire dvi_bit_clock;\n wire dvi_bit_clock_dvi_pll;\n wire pixel_clock;\n wire pixel_clock_dvi_pll;\n wire sysclk;\n wire sysclk_dvi_pll;\n wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED;\n wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED;\n wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED;\n wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED;\n wire NLW_plle2_adv_inst_DRDY_UNCONNECTED;\n wire NLW_plle2_adv_inst_LOCKED_UNCONNECTED;\n wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED;\n\n (* BOX_TYPE = \"PRIMITIVE\" *) \n BUFG clkf_buf\n (.I(clkfbout_dvi_pll),\n .O(clkfbout_buf_dvi_pll));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n BUFG clkin1_bufg\n (.I(sysclk),\n .O(sysclk_dvi_pll));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n BUFG clkout1_buf\n (.I(pixel_clock_dvi_pll),\n .O(pixel_clock));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n BUFG clkout2_buf\n (.I(dvi_bit_clock_dvi_pll),\n .O(dvi_bit_clock));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n PLLE2_ADV #(\n .BANDWIDTH(\"OPTIMIZED\"),\n .CLKFBOUT_MULT(31),\n .CLKFBOUT_PHASE(0.000000),\n .CLKIN1_PERIOD(5.000000),\n .CLKIN2_PERIOD(0.000000),\n .CLKOUT0_DIVIDE(10),\n .CLKOUT0_DUTY_CYCLE(0.500000),\n .CLKOUT0_PHASE(0.000000),\n .CLKOUT1_DIVIDE(2),\n .CLKOUT1_DUTY_CYCLE(0.500000),\n .CLKOUT1_PHASE(0.000000),\n .CLKOUT2_DIVIDE(1),\n .CLKOUT2_DUTY_CYCLE(0.500000),\n .CLKOUT2_PHASE(0.000000),\n .CLKOUT3_DIVIDE(1),\n .CLKOUT3_DUTY_CYCLE(0.500000),\n .CLKOUT3_PHASE(0.000000),\n .CLKOUT4_DIVIDE(1),\n .CLKOUT4_DUTY_CYCLE(0.500000),\n .CLKOUT4_PHASE(0.000000),\n .CLKOUT5_DIVIDE(1),\n .CLKOUT5_DUTY_CYCLE(0.500000),\n .CLKOUT5_PHASE(0.000000),\n .COMPENSATION(\"BUF_IN\"),\n .DIVCLK_DIVIDE(5),\n .IS_CLKINSEL_INVERTED(1'b0),\n .IS_PWRDWN_INVERTED(1'b0),\n .IS_RST_INVERTED(1'b0),\n .REF_JITTER1(0.010000),\n .REF_JITTER2(0.010000),\n .STARTUP_WAIT(\"FALSE\")) \n plle2_adv_inst\n (.CLKFBIN(clkfbout_buf_dvi_pll),\n .CLKFBOUT(clkfbout_dvi_pll),\n .CLKIN1(sysclk_dvi_pll),\n .CLKIN2(1'b0),\n .CLKINSEL(1'b1),\n .CLKOUT0(pixel_clock_dvi_pll),\n .CLKOUT1(dvi_bit_clock_dvi_pll),\n .CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED),\n .CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED),\n .CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED),\n .CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED),\n .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DCLK(1'b0),\n .DEN(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]),\n .DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED),\n .DWE(1'b0),\n .LOCKED(NLW_plle2_adv_inst_LOCKED_UNCONNECTED),\n .PWRDWN(1'b0),\n .RST(1'b0));\nendmodule\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.cache/ip/54144841a4506c29/dvi_pll_stub.v", "content": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// --------------------------------------------------------------------------------\n// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016\n// Date : Tue Nov 15 16:22:12 2016\n// Host : david-desktop-arch running 64-bit unknown\n// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix\n// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dvi_pll_stub.v\n// Design : dvi_pll\n// Purpose : Stub declaration of top-level module interface\n// Device : xc7k325tffg900-2\n// --------------------------------------------------------------------------------\n\n// This empty module with port declaration file causes synthesis tools to infer a black box for IP.\n// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.\n// Please paste the declaration into a Verilog source file or add the file as an additional source.\nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(pixel_clock, dvi_bit_clock, sysclk)\n/* synthesis syn_black_box black_box_pad_pin=\"pixel_clock,dvi_bit_clock,sysclk\" */;\n output pixel_clock;\n output dvi_bit_clock;\n input sysclk;\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.cache/ip/548aa35948ad692b/548aa35948ad692b.xci", "content": "\n\n xilinx.com\n ipcache\n 548aa35948ad692b\n 0\n \n \n camera_pll\n \n \n MMCM\n false\n empty\n cddcdone\n cddcreq\n clkfb_in_n\n clkfb_in\n clkfb_in_p\n SINGLE\n clkfb_out_n\n clkfb_out\n clkfb_out_p\n clkfb_stopped\n 50.0\n 0.010\n 100.0\n 0.010\n BUFG\n 280.569\n false\n 321.802\n 50.000\n 145\n 0.000\n 1\n true\n BUFG\n 391.507\n false\n 321.802\n 50.000\n 24.4\n 0.000\n 1\n true\n BUFG\n 519.540\n false\n 321.802\n 50.000\n 5\n 0.000\n 1\n true\n BUFG\n 0.0\n false\n 0.0\n 50.000\n 100.000\n 0.000\n 1\n false\n BUFG\n 0.0\n false\n 0.0\n 50.000\n 100.000\n 0.000\n 1\n false\n BUFG\n 0.0\n false\n 0.0\n 50.000\n 100.000\n 0.000\n 1\n false\n BUFG\n 0.0\n false\n 0.0\n 50.000\n 100.000\n 0.000\n 1\n false\n 600.000\n Custom\n Custom\n clk_in_sel\n camera_pixel_clock\n false\n camera_mclk\n false\n i2c_clkin\n false\n clk_out4\n false\n clk_out5\n false\n clk_out6\n false\n clk_out7\n false\n CLK_VALID\n auto\n camera_pll\n daddr\n dclk\n den\n Custom\n Custom\n din\n dout\n drdy\n dwe\n false\n false\n false\n false\n false\n false\n false\n false\n false\n FDBK_AUTO\n input_clk_stopped\n frequency\n Enable_AXI\n Units_MHz\n Units_UI\n UI\n No_Jitter\n locked\n OPTIMIZED\n 25.375\n 0.000\n false\n 5.0\n 10.0\n 4.375\n 0.500\n 0.000\n false\n 26\n 0.500\n 0.000\n false\n 127\n 0.500\n 0.000\n false\n 1\n 0.500\n 0.000\n false\n false\n 1\n 0.500\n 0.000\n false\n 1\n 0.500\n 0.000\n false\n 1\n 0.500\n 0.000\n false\n false\n ZHOLD\n 8\n None\n 0.010\n 0.010\n false\n 3\n false\n false\n WAVEFORM\n false\n UNKNOWN\n OPTIMIZED\n 4\n 0.000\n 10.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n CLKFBOUT\n SYSTEM_SYNCHRONOUS\n 1\n None\n 0.010\n power_down\n 1\n sysclk\n MMCM\n mmcm_adv\n 200\n 0.010\n 10.000\n Global_buffer\n psclk\n psdone\n psen\n psincdec\n 100.0\n REL_PRIMARY\n Custom\n reset\n ACTIVE_HIGH\n 100.000\n 0.010\n 10.000\n clk_in2\n Single_ended_clock_capable_pin\n CENTER_HIGH\n 250\n 0.004\n STATUS\n empty\n 100.0\n 100.0\n 100.0\n 100.0\n false\n false\n false\n false\n false\n false\n false\n true\n false\n false\n false\n false\n false\n false\n true\n false\n false\n false\n false\n false\n kintex7\n \n xc7k325t\n ffg900\n VERILOG\n \n MIXED\n -2\n \n TRUE\n TRUE\n e2451eba\n 548aa35948ad692b\n camera_pll\n IP_Unknown\n 2\n TRUE\n .\n \n .\n 2016.3\n GLOBAL\n \n \n \n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.cache/ip/548aa35948ad692b/camera_pll_sim_netlist.v", "content": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// --------------------------------------------------------------------------------\n// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016\n// Date : Tue Nov 15 14:32:35 2016\n// Host : david-desktop-arch running 64-bit unknown\n// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix\n// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ camera_pll_sim_netlist.v\n// Design : camera_pll\n// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified\n// or synthesized. This netlist cannot be used for SDF annotated simulation.\n// Device : xc7k325tffg900-2\n// --------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* NotValidForBitStream *)\nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix\n (camera_pixel_clock,\n camera_mclk,\n i2c_clkin,\n sysclk);\n output camera_pixel_clock;\n output camera_mclk;\n output i2c_clkin;\n input sysclk;\n\n wire camera_mclk;\n wire camera_pixel_clock;\n wire i2c_clkin;\n wire sysclk;\n\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_camera_pll_clk_wiz inst\n (.camera_mclk(camera_mclk),\n .camera_pixel_clock(camera_pixel_clock),\n .i2c_clkin(i2c_clkin),\n .sysclk(sysclk));\nendmodule\n\nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_camera_pll_clk_wiz\n (camera_pixel_clock,\n camera_mclk,\n i2c_clkin,\n sysclk);\n output camera_pixel_clock;\n output camera_mclk;\n output i2c_clkin;\n input sysclk;\n\n wire camera_mclk;\n wire camera_mclk_camera_pll;\n wire camera_pixel_clock;\n wire camera_pixel_clock_camera_pll;\n wire clkfbout_buf_camera_pll;\n wire clkfbout_camera_pll;\n wire i2c_clkin;\n wire i2c_clkin_camera_pll;\n wire sysclk;\n wire sysclk_camera_pll;\n wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;\n wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;\n wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;\n wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;\n wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;\n wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;\n wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;\n wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;\n wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;\n wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;\n wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;\n wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;\n wire NLW_mmcm_adv_inst_LOCKED_UNCONNECTED;\n wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;\n wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;\n\n (* BOX_TYPE = \"PRIMITIVE\" *) \n BUFG clkf_buf\n (.I(clkfbout_camera_pll),\n .O(clkfbout_buf_camera_pll));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n BUFG clkin1_bufg\n (.I(sysclk),\n .O(sysclk_camera_pll));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n BUFG clkout1_buf\n (.I(camera_pixel_clock_camera_pll),\n .O(camera_pixel_clock));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n BUFG clkout2_buf\n (.I(camera_mclk_camera_pll),\n .O(camera_mclk));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n BUFG clkout3_buf\n (.I(i2c_clkin_camera_pll),\n .O(i2c_clkin));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n MMCME2_ADV #(\n .BANDWIDTH(\"OPTIMIZED\"),\n .CLKFBOUT_MULT_F(25.375000),\n .CLKFBOUT_PHASE(0.000000),\n .CLKFBOUT_USE_FINE_PS(\"FALSE\"),\n .CLKIN1_PERIOD(5.000000),\n .CLKIN2_PERIOD(0.000000),\n .CLKOUT0_DIVIDE_F(4.375000),\n .CLKOUT0_DUTY_CYCLE(0.500000),\n .CLKOUT0_PHASE(0.000000),\n .CLKOUT0_USE_FINE_PS(\"FALSE\"),\n .CLKOUT1_DIVIDE(26),\n .CLKOUT1_DUTY_CYCLE(0.500000),\n .CLKOUT1_PHASE(0.000000),\n .CLKOUT1_USE_FINE_PS(\"FALSE\"),\n .CLKOUT2_DIVIDE(127),\n .CLKOUT2_DUTY_CYCLE(0.500000),\n .CLKOUT2_PHASE(0.000000),\n .CLKOUT2_USE_FINE_PS(\"FALSE\"),\n .CLKOUT3_DIVIDE(1),\n .CLKOUT3_DUTY_CYCLE(0.500000),\n .CLKOUT3_PHASE(0.000000),\n .CLKOUT3_USE_FINE_PS(\"FALSE\"),\n .CLKOUT4_CASCADE(\"FALSE\"),\n .CLKOUT4_DIVIDE(1),\n .CLKOUT4_DUTY_CYCLE(0.500000),\n .CLKOUT4_PHASE(0.000000),\n .CLKOUT4_USE_FINE_PS(\"FALSE\"),\n .CLKOUT5_DIVIDE(1),\n .CLKOUT5_DUTY_CYCLE(0.500000),\n .CLKOUT5_PHASE(0.000000),\n .CLKOUT5_USE_FINE_PS(\"FALSE\"),\n .CLKOUT6_DIVIDE(1),\n .CLKOUT6_DUTY_CYCLE(0.500000),\n .CLKOUT6_PHASE(0.000000),\n .CLKOUT6_USE_FINE_PS(\"FALSE\"),\n .COMPENSATION(\"BUF_IN\"),\n .DIVCLK_DIVIDE(8),\n .IS_CLKINSEL_INVERTED(1'b0),\n .IS_PSEN_INVERTED(1'b0),\n .IS_PSINCDEC_INVERTED(1'b0),\n .IS_PWRDWN_INVERTED(1'b0),\n .IS_RST_INVERTED(1'b0),\n .REF_JITTER1(0.010000),\n .REF_JITTER2(0.010000),\n .SS_EN(\"FALSE\"),\n .SS_MODE(\"CENTER_HIGH\"),\n .SS_MOD_PERIOD(10000),\n .STARTUP_WAIT(\"FALSE\")) \n mmcm_adv_inst\n (.CLKFBIN(clkfbout_buf_camera_pll),\n .CLKFBOUT(clkfbout_camera_pll),\n .CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),\n .CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),\n .CLKIN1(sysclk_camera_pll),\n .CLKIN2(1'b0),\n .CLKINSEL(1'b1),\n .CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),\n .CLKOUT0(camera_pixel_clock_camera_pll),\n .CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),\n .CLKOUT1(camera_mclk_camera_pll),\n .CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),\n .CLKOUT2(i2c_clkin_camera_pll),\n .CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),\n .CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),\n .CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),\n .CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),\n .CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),\n .CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),\n .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DCLK(1'b0),\n .DEN(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),\n .DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),\n .DWE(1'b0),\n .LOCKED(NLW_mmcm_adv_inst_LOCKED_UNCONNECTED),\n .PSCLK(1'b0),\n .PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),\n .PSEN(1'b0),\n .PSINCDEC(1'b0),\n .PWRDWN(1'b0),\n .RST(1'b0));\nendmodule\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.cache/ip/548aa35948ad692b/camera_pll_stub.v", "content": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// --------------------------------------------------------------------------------\n// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016\n// Date : Tue Nov 15 14:32:35 2016\n// Host : david-desktop-arch running 64-bit unknown\n// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix\n// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ camera_pll_stub.v\n// Design : camera_pll\n// Purpose : Stub declaration of top-level module interface\n// Device : xc7k325tffg900-2\n// --------------------------------------------------------------------------------\n\n// This empty module with port declaration file causes synthesis tools to infer a black box for IP.\n// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.\n// Please paste the declaration into a Verilog source file or add the file as an additional source.\nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(camera_pixel_clock, camera_mclk, i2c_clkin, \n sysclk)\n/* synthesis syn_black_box black_box_pad_pin=\"camera_pixel_clock,camera_mclk,i2c_clkin,sysclk\" */;\n output camera_pixel_clock;\n output camera_mclk;\n output i2c_clkin;\n input sysclk;\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.cache/ip/75280199e9655e6a/75280199e9655e6a.xci", "content": "\n\n xilinx.com\n ipcache\n 75280199e9655e6a\n 0\n \n \n dvi_pll\n \n \n MMCM\n false\n empty\n cddcdone\n cddcreq\n clkfb_in_n\n clkfb_in\n clkfb_in_p\n SINGLE\n clkfb_out_n\n clkfb_out\n clkfb_out_p\n clkfb_stopped\n 50.0\n 0.010\n 100.0\n 0.010\n BUFG\n 111.449\n false\n 139.507\n 50.000\n 148\n 0.000\n 1\n true\n BUFG\n 87.091\n false\n 139.507\n 50.000\n 740\n 0.000\n 1\n true\n BUFG\n 0.0\n false\n 0.0\n 50.000\n 100.000\n 0.000\n 1\n false\n BUFG\n 0.0\n false\n 0.0\n 50.000\n 100.000\n 0.000\n 1\n false\n BUFG\n 0.0\n false\n 0.0\n 50.000\n 100.000\n 0.000\n 1\n false\n BUFG\n 0.0\n false\n 0.0\n 50.000\n 100.000\n 0.000\n 1\n false\n BUFG\n 0.0\n false\n 0.0\n 50.000\n 100.000\n 0.000\n 1\n false\n 600.000\n Custom\n Custom\n clk_in_sel\n pixel_clock\n false\n dvi_bit_clock\n false\n clk_out3\n false\n clk_out4\n false\n clk_out5\n false\n clk_out6\n false\n clk_out7\n false\n CLK_VALID\n auto\n dvi_pll\n daddr\n dclk\n den\n Custom\n Custom\n din\n dout\n drdy\n dwe\n false\n false\n false\n false\n false\n false\n false\n false\n false\n FDBK_AUTO\n input_clk_stopped\n frequency\n Enable_AXI\n Units_MHz\n Units_UI\n UI\n No_Jitter\n locked\n OPTIMIZED\n 37\n 0.000\n false\n 5.0\n 10.0\n 10\n 0.500\n 0.000\n false\n 2\n 0.500\n 0.000\n false\n 1\n 0.500\n 0.000\n false\n 1\n 0.500\n 0.000\n false\n false\n 1\n 0.500\n 0.000\n false\n 1\n 0.500\n 0.000\n false\n 1\n 0.500\n 0.000\n false\n false\n ZHOLD\n 5\n None\n 0.010\n 0.010\n false\n 2\n false\n false\n WAVEFORM\n false\n UNKNOWN\n OPTIMIZED\n 4\n 0.000\n 10.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n CLKFBOUT\n SYSTEM_SYNCHRONOUS\n 1\n None\n 0.010\n power_down\n 1\n sysclk\n PLL\n mmcm_adv\n 200\n 0.010\n 10.000\n Global_buffer\n psclk\n psdone\n psen\n psincdec\n 100.0\n REL_PRIMARY\n Custom\n reset\n ACTIVE_HIGH\n 100.000\n 0.010\n 10.000\n clk_in2\n Single_ended_clock_capable_pin\n CENTER_HIGH\n 250\n 0.004\n STATUS\n empty\n 100.0\n 100.0\n 100.0\n 100.0\n false\n false\n false\n false\n false\n false\n false\n true\n false\n false\n false\n false\n false\n false\n true\n false\n false\n false\n false\n false\n kintex7\n \n xc7k325t\n ffg900\n VERILOG\n \n MIXED\n -2\n \n TRUE\n TRUE\n e2451eba\n 75280199e9655e6a\n dvi_pll\n IP_Unknown\n 2\n TRUE\n .\n \n .\n 2016.3\n GLOBAL\n \n \n \n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.cache/ip/75280199e9655e6a/dvi_pll_sim_netlist.v", "content": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// --------------------------------------------------------------------------------\n// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016\n// Date : Tue Nov 15 17:05:27 2016\n// Host : david-desktop-arch running 64-bit unknown\n// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix\n// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dvi_pll_sim_netlist.v\n// Design : dvi_pll\n// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified\n// or synthesized. This netlist cannot be used for SDF annotated simulation.\n// Device : xc7k325tffg900-2\n// --------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* NotValidForBitStream *)\nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix\n (pixel_clock,\n dvi_bit_clock,\n sysclk);\n output pixel_clock;\n output dvi_bit_clock;\n input sysclk;\n\n wire dvi_bit_clock;\n wire pixel_clock;\n wire sysclk;\n\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dvi_pll_clk_wiz inst\n (.dvi_bit_clock(dvi_bit_clock),\n .pixel_clock(pixel_clock),\n .sysclk(sysclk));\nendmodule\n\nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dvi_pll_clk_wiz\n (pixel_clock,\n dvi_bit_clock,\n sysclk);\n output pixel_clock;\n output dvi_bit_clock;\n input sysclk;\n\n wire clkfbout_buf_dvi_pll;\n wire clkfbout_dvi_pll;\n wire dvi_bit_clock;\n wire dvi_bit_clock_dvi_pll;\n wire pixel_clock;\n wire pixel_clock_dvi_pll;\n wire sysclk;\n wire sysclk_dvi_pll;\n wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED;\n wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED;\n wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED;\n wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED;\n wire NLW_plle2_adv_inst_DRDY_UNCONNECTED;\n wire NLW_plle2_adv_inst_LOCKED_UNCONNECTED;\n wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED;\n\n (* BOX_TYPE = \"PRIMITIVE\" *) \n BUFG clkf_buf\n (.I(clkfbout_dvi_pll),\n .O(clkfbout_buf_dvi_pll));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n BUFG clkin1_bufg\n (.I(sysclk),\n .O(sysclk_dvi_pll));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n BUFG clkout1_buf\n (.I(pixel_clock_dvi_pll),\n .O(pixel_clock));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n BUFG clkout2_buf\n (.I(dvi_bit_clock_dvi_pll),\n .O(dvi_bit_clock));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n PLLE2_ADV #(\n .BANDWIDTH(\"OPTIMIZED\"),\n .CLKFBOUT_MULT(37),\n .CLKFBOUT_PHASE(0.000000),\n .CLKIN1_PERIOD(5.000000),\n .CLKIN2_PERIOD(0.000000),\n .CLKOUT0_DIVIDE(10),\n .CLKOUT0_DUTY_CYCLE(0.500000),\n .CLKOUT0_PHASE(0.000000),\n .CLKOUT1_DIVIDE(2),\n .CLKOUT1_DUTY_CYCLE(0.500000),\n .CLKOUT1_PHASE(0.000000),\n .CLKOUT2_DIVIDE(1),\n .CLKOUT2_DUTY_CYCLE(0.500000),\n .CLKOUT2_PHASE(0.000000),\n .CLKOUT3_DIVIDE(1),\n .CLKOUT3_DUTY_CYCLE(0.500000),\n .CLKOUT3_PHASE(0.000000),\n .CLKOUT4_DIVIDE(1),\n .CLKOUT4_DUTY_CYCLE(0.500000),\n .CLKOUT4_PHASE(0.000000),\n .CLKOUT5_DIVIDE(1),\n .CLKOUT5_DUTY_CYCLE(0.500000),\n .CLKOUT5_PHASE(0.000000),\n .COMPENSATION(\"BUF_IN\"),\n .DIVCLK_DIVIDE(5),\n .IS_CLKINSEL_INVERTED(1'b0),\n .IS_PWRDWN_INVERTED(1'b0),\n .IS_RST_INVERTED(1'b0),\n .REF_JITTER1(0.010000),\n .REF_JITTER2(0.010000),\n .STARTUP_WAIT(\"FALSE\")) \n plle2_adv_inst\n (.CLKFBIN(clkfbout_buf_dvi_pll),\n .CLKFBOUT(clkfbout_dvi_pll),\n .CLKIN1(sysclk_dvi_pll),\n .CLKIN2(1'b0),\n .CLKINSEL(1'b1),\n .CLKOUT0(pixel_clock_dvi_pll),\n .CLKOUT1(dvi_bit_clock_dvi_pll),\n .CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED),\n .CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED),\n .CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED),\n .CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED),\n .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DCLK(1'b0),\n .DEN(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]),\n .DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED),\n .DWE(1'b0),\n .LOCKED(NLW_plle2_adv_inst_LOCKED_UNCONNECTED),\n .PWRDWN(1'b0),\n .RST(1'b0));\nendmodule\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.cache/ip/75280199e9655e6a/dvi_pll_stub.v", "content": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// --------------------------------------------------------------------------------\n// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016\n// Date : Tue Nov 15 17:05:27 2016\n// Host : david-desktop-arch running 64-bit unknown\n// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix\n// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dvi_pll_stub.v\n// Design : dvi_pll\n// Purpose : Stub declaration of top-level module interface\n// Device : xc7k325tffg900-2\n// --------------------------------------------------------------------------------\n\n// This empty module with port declaration file causes synthesis tools to infer a black box for IP.\n// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.\n// Please paste the declaration into a Verilog source file or add the file as an additional source.\nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(pixel_clock, dvi_bit_clock, sysclk)\n/* synthesis syn_black_box black_box_pad_pin=\"pixel_clock,dvi_bit_clock,sysclk\" */;\n output pixel_clock;\n output dvi_bit_clock;\n input sysclk;\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/ip/camera_pll/camera_pll_stub.v", "content": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// --------------------------------------------------------------------------------\n// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016\n// Date : Tue Nov 15 14:32:35 2016\n// Host : david-desktop-arch running 64-bit unknown\n// Command : write_verilog -force -mode synth_stub -rename_top camera_pll -prefix\n// camera_pll_ camera_pll_stub.v\n// Design : camera_pll\n// Purpose : Stub declaration of top-level module interface\n// Device : xc7k325tffg900-2\n// --------------------------------------------------------------------------------\n\n// This empty module with port declaration file causes synthesis tools to infer a black box for IP.\n// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.\n// Please paste the declaration into a Verilog source file or add the file as an additional source.\nmodule camera_pll(camera_pixel_clock, camera_mclk, i2c_clkin, \n sysclk)\n/* synthesis syn_black_box black_box_pad_pin=\"camera_pixel_clock,camera_mclk,i2c_clkin,sysclk\" */;\n output camera_pixel_clock;\n output camera_mclk;\n output i2c_clkin;\n input sysclk;\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/ip/ddr3_if/ddr3_if_stub.v", "content": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// --------------------------------------------------------------------------------\n// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016\n// Date : Tue Nov 15 09:09:09 2016\n// Host : david-xilinx-vm running 64-bit unknown\n// Command : write_verilog -force -mode synth_stub -rename_top ddr3_if -prefix\n// ddr3_if_ ddr3_if_stub.v\n// Design : ddr3_if\n// Purpose : Stub declaration of top-level module interface\n// Device : xc7k325tffg900-2\n// --------------------------------------------------------------------------------\n\n// This empty module with port declaration file causes synthesis tools to infer a black box for IP.\n// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.\n// Please paste the declaration into a Verilog source file or add the file as an additional source.\nmodule ddr3_if(ddr3_dq, ddr3_dqs_n, ddr3_dqs_p, ddr3_addr, \n ddr3_ba, ddr3_ras_n, ddr3_cas_n, ddr3_we_n, ddr3_reset_n, ddr3_ck_p, ddr3_ck_n, ddr3_cke, \n ddr3_cs_n, ddr3_dm, ddr3_odt, sys_clk_i, ui_clk, ui_clk_sync_rst, mmcm_locked, aresetn, \n app_sr_req, app_ref_req, app_zq_req, app_sr_active, app_ref_ack, app_zq_ack, s_axi_awid, \n s_axi_awaddr, s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, \n s_axi_awprot, s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, \n s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bready, s_axi_bid, s_axi_bresp, s_axi_bvalid, \n s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, \n s_axi_arcache, s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rready, \n s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, init_calib_complete, \n device_temp, sys_rst)\n/* synthesis syn_black_box black_box_pad_pin=\"ddr3_dq[31:0],ddr3_dqs_n[3:0],ddr3_dqs_p[3:0],ddr3_addr[14:0],ddr3_ba[2:0],ddr3_ras_n,ddr3_cas_n,ddr3_we_n,ddr3_reset_n,ddr3_ck_p[0:0],ddr3_ck_n[0:0],ddr3_cke[0:0],ddr3_cs_n[0:0],ddr3_dm[3:0],ddr3_odt[0:0],sys_clk_i,ui_clk,ui_clk_sync_rst,mmcm_locked,aresetn,app_sr_req,app_ref_req,app_zq_req,app_sr_active,app_ref_ack,app_zq_ack,s_axi_awid[0:0],s_axi_awaddr[29:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[255:0],s_axi_wstrb[31:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bready,s_axi_bid[0:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_arid[0:0],s_axi_araddr[29:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rready,s_axi_rid[0:0],s_axi_rdata[255:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,init_calib_complete,device_temp[11:0],sys_rst\" */;\n inout [31:0]ddr3_dq;\n inout [3:0]ddr3_dqs_n;\n inout [3:0]ddr3_dqs_p;\n output [14:0]ddr3_addr;\n output [2:0]ddr3_ba;\n output ddr3_ras_n;\n output ddr3_cas_n;\n output ddr3_we_n;\n output ddr3_reset_n;\n output [0:0]ddr3_ck_p;\n output [0:0]ddr3_ck_n;\n output [0:0]ddr3_cke;\n output [0:0]ddr3_cs_n;\n output [3:0]ddr3_dm;\n output [0:0]ddr3_odt;\n input sys_clk_i;\n output ui_clk;\n output ui_clk_sync_rst;\n output mmcm_locked;\n input aresetn;\n input app_sr_req;\n input app_ref_req;\n input app_zq_req;\n output app_sr_active;\n output app_ref_ack;\n output app_zq_ack;\n input [0:0]s_axi_awid;\n input [29:0]s_axi_awaddr;\n input [7:0]s_axi_awlen;\n input [2:0]s_axi_awsize;\n input [1:0]s_axi_awburst;\n input [0:0]s_axi_awlock;\n input [3:0]s_axi_awcache;\n input [2:0]s_axi_awprot;\n input [3:0]s_axi_awqos;\n input s_axi_awvalid;\n output s_axi_awready;\n input [255:0]s_axi_wdata;\n input [31:0]s_axi_wstrb;\n input s_axi_wlast;\n input s_axi_wvalid;\n output s_axi_wready;\n input s_axi_bready;\n output [0:0]s_axi_bid;\n output [1:0]s_axi_bresp;\n output s_axi_bvalid;\n input [0:0]s_axi_arid;\n input [29:0]s_axi_araddr;\n input [7:0]s_axi_arlen;\n input [2:0]s_axi_arsize;\n input [1:0]s_axi_arburst;\n input [0:0]s_axi_arlock;\n input [3:0]s_axi_arcache;\n input [2:0]s_axi_arprot;\n input [3:0]s_axi_arqos;\n input s_axi_arvalid;\n output s_axi_arready;\n input s_axi_rready;\n output [0:0]s_axi_rid;\n output [255:0]s_axi_rdata;\n output [1:0]s_axi_rresp;\n output s_axi_rlast;\n output s_axi_rvalid;\n output init_calib_complete;\n output [11:0]device_temp;\n input sys_rst;\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/ip/dvi_pll/dvi_pll_stub.v", "content": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// --------------------------------------------------------------------------------\n// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016\n// Date : Tue Nov 15 17:05:27 2016\n// Host : david-desktop-arch running 64-bit unknown\n// Command : write_verilog -force -mode synth_stub\n// /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_stub.v\n// Design : dvi_pll\n// Purpose : Stub declaration of top-level module interface\n// Device : xc7k325tffg900-2\n// --------------------------------------------------------------------------------\n\n// This empty module with port declaration file causes synthesis tools to infer a black box for IP.\n// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.\n// Please paste the declaration into a Verilog source file or add the file as an additional source.\nmodule dvi_pll(pixel_clock, dvi_bit_clock, sysclk)\n/* synthesis syn_black_box black_box_pad_pin=\"pixel_clock,dvi_bit_clock,sysclk\" */;\n output pixel_clock;\n output dvi_bit_clock;\n input sysclk;\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/ip/ila_0/ila_0_stub.v", "content": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// --------------------------------------------------------------------------------\n// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016\n// Date : Sat Nov 12 19:23:02 2016\n// Host : david-desktop-arch running 64-bit unknown\n// Command : write_verilog -force -mode synth_stub\n// /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/ila_0/ila_0_stub.v\n// Design : ila_0\n// Purpose : Stub declaration of top-level module interface\n// Device : xc7k325tffg900-2\n// --------------------------------------------------------------------------------\n\n// This empty module with port declaration file causes synthesis tools to infer a black box for IP.\n// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.\n// Please paste the declaration into a Verilog source file or add the file as an additional source.\n(* X_CORE_INFO = \"ila,Vivado 2016.3\" *)\nmodule ila_0(clk, probe0)\n/* synthesis syn_black_box black_box_pad_pin=\"clk,probe0[8:0]\" */;\n input clk;\n input [8:0]probe0;\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/ip/input_line_buffer/input_line_buffer_stub.v", "content": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// --------------------------------------------------------------------------------\n// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016\n// Date : Tue Nov 15 09:41:00 2016\n// Host : david-desktop-arch running 64-bit unknown\n// Command : write_verilog -force -mode synth_stub\n// /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_stub.v\n// Design : input_line_buffer\n// Purpose : Stub declaration of top-level module interface\n// Device : xc7k325tffg900-2\n// --------------------------------------------------------------------------------\n\n// This empty module with port declaration file causes synthesis tools to infer a black box for IP.\n// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.\n// Please paste the declaration into a Verilog source file or add the file as an additional source.\n(* x_core_info = \"blk_mem_gen_v8_3_4,Vivado 2016.3\" *)\nmodule input_line_buffer(clka, ena, wea, addra, dina, clkb, addrb, doutb)\n/* synthesis syn_black_box black_box_pad_pin=\"clka,ena,wea[0:0],addra[11:0],dina[63:0],clkb,addrb[9:0],doutb[255:0]\" */;\n input clka;\n input ena;\n input [0:0]wea;\n input [11:0]addra;\n input [63:0]dina;\n input clkb;\n input [9:0]addrb;\n output [255:0]doutb;\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/ip/output_line_buffer/output_line_buffer_stub.v", "content": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// --------------------------------------------------------------------------------\n// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016\n// Date : Tue Nov 15 09:42:01 2016\n// Host : david-desktop-arch running 64-bit unknown\n// Command : write_verilog -force -mode synth_stub\n// /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_stub.v\n// Design : output_line_buffer\n// Purpose : Stub declaration of top-level module interface\n// Device : xc7k325tffg900-2\n// --------------------------------------------------------------------------------\n\n// This empty module with port declaration file causes synthesis tools to infer a black box for IP.\n// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.\n// Please paste the declaration into a Verilog source file or add the file as an additional source.\n(* x_core_info = \"blk_mem_gen_v8_3_4,Vivado 2016.3\" *)\nmodule output_line_buffer(clka, ena, wea, addra, dina, clkb, addrb, doutb)\n/* synthesis syn_black_box black_box_pad_pin=\"clka,ena,wea[0:0],addra[9:0],dina[255:0],clkb,addrb[11:0],doutb[63:0]\" */;\n input clka;\n input ena;\n input [0:0]wea;\n input [9:0]addra;\n input [255:0]dina;\n input clkb;\n input [11:0]addrb;\n output [63:0]doutb;\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/ipstatic/hdl/fifo_generator_v13_1_rfs.v", "content": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`pragma protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`pragma protect key_block\niCMCAmpnUKHzhjQEOGn7uHF8rzR6z6Q1KaqR86pF7GoO/ymK5vTIDTnNa9nKFdhoYtxNaHsWt5kN\nVFJc10LTKA==\n\n`pragma protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nFFKI8J5LdjZtpODsN7pt+4OeAKOC8QjdxFp3gAJt8IiHZrmYepy7EgOh0P0ffApbaq0puFw9svm5\n4aBPja6YuWgg7h7xNLN7wLHVUwJu+lOgLAKpk+f6Ng68Hdt4pc7b+sadbOGpLgi6XNE8X7BaPE1/\n1UBvmcWYAEvHJ5euTyA=\n\n`pragma protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`pragma protect key_block\nUFtUuQ7LNNNstYC8OJZ1mZ8iEM878Hd3HgzdT2mKNF5tupw+rz5pwpvEiTElyG4e6KhcApeDVHom\nF+ge+iphHc+EkBINqnnEWPeyK9vbiYFxgP9RhiPBYDlGkGNxTDdYmM0kdg4/KuxlCNFqZNHWOpbR\n25RTOqHyC1NGXpqnLgY=\n\n`pragma protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\n1bvgu80gmzu2/2STP2z1dP+c59762Ntm9HVjEj1cQ5zpmEgBhYnZAWC3I1Aub88d7zlgY3jC5WfF\nyJfrBnrex+QQB+omjWcIgNmHSlVQEAa8B/7ZfapdLEtyPWbhR3ESAdT9ifMNXhbIKI6/6pxI69xL\nWQeXxSwjZUSeD3l1R5DlYnccG0/coE4cjAbDpLxadhd4XbPE5Eb/l5zjOutFozEOMJuJifhGPxpt\nclWZDvrK2ebtrkdJeOLIqPrryQhuh2Ul0Fe89cfqvhP4pfTSQuHM6wjgf3g4gI8CoyqLJ+7RcfBv\nXF4xiBcq7ly4eqDmBZ6ESOSNUR9K4pzdpVpxRw==\n\n`pragma protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nV2wQbj5ws+RFb01e4/hVx3v2DLlfwLikAIjVjWf3BTaVlJVidhZ8Mn8kAflGhKRNAmXAG3wXOif8\nfifCIiVrnszRJfRpY4Okq9RA0lc43SIZjIHWpZWN9SFT8BS5rDysaaFrV+4xQKTB4K6W38YFUiG/\nPPc0osc/cnjCbXrgDV/DVsMBdtlpBq83LRpqWAIodFoHpQGf31BfsX/EoOTo5ntXFZoovFM+69rJ\nOUIZuCQ1otv4tQToThhbG5Gj4A/t/exgA2L2Biwt3pyTStnNwZrfRTuJqcCVtGkLNZTl3DlwxxnT\nvf7FZye/qhmPNSIR1DNeHWm0xYYZ/jwy6FD4EQ==\n\n`pragma protect key_keyowner = \"Xilinx\", key_keyname = \"xilinx_2016_05\", key_method = \"rsa\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`pragma protect key_block\nwwnJlZhlzdPKP+rMWc3Dx2+QDO+OuWE3mTPC5QjO9fGoMAbyT6CyUraAY0Sp+z0iQOkVvPSPGzzp\nx0e52CDZxf1mho3TicK7tIy7J3D+PZiccAgUujw31RoihkpPVapt35uQWL4Pu8q6yJ7s7fvQ2G1/\nYwwQD6yp8SZsGJ7k0TslbLRJvfZze0XcsIIgLYwlD5gGulXXXi5yGaezKBYwqmZAru4DfBecphz9\nY87nmRqjgFW9rAU2SwckBn8xsSirT4eSKeSRHQvXV78dfm36vYul3r82HYgpAVax6qQqXR8tt/pV\nD1CodXioEFNGvtJqV29rJVkNa9RD1q5qLsbOpQ==\n\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 438576)\n`pragma protect data_block\nPpwd2Ot4t2UGFpv57+IF7Bgd0fA+7s1yVCuCO3q986PbCIPay4El6J5fl1RF2/CIMAS0I7qwsewa\n2QukhxV2KQgR8gtYtwzIkuE/Zkww6WVgXB/XNTz0mBN15AeyNy+axXmZy6+iDsfBytMNFV60E+bl\npKvuo/bIBVc5mQdEbc0X/t4F0Fs7MhSahL4zEucnoxU2drgy6bTz9aK1O3Bjddb7xof9agt2+PxT\nNBCex10JBPmnfohv67nRStY07MhrH/TdJJsLzzi1XPjTWfMSy6KERthXgEsEP4iluZkIRzGyuq61\nFVO4I7dsIrmXGoFjkSX928jKTzS4b3nhtxtQBXZaiTgCyLqMrl8aOTugJ0XbM2EuGJ6yEqSrzKCj\nv/PMsMGVUKMIkgCo1xJe/MOd8LCU4zcUlYM+xGEYd/P+lxK8kC0aDXMIJWaswq5RkqaJ76t/LNPt\nhkRZjimzOlc8VsPZwnW93LEpv3S2ndQIr+enEl+YPOhG6dH8TWtLHd+3jgEzypW7lC2PpmBs4IWY\nge2GbPf3V1BwedZMJ4xJ3vXMuC8Ldz4RgoZ5UYNKt4LJNere5rOBAGckX8YaKaYncI23opNYunhn\n1czsV69khZniNwleqV/Dfy0S6M14d0nwMMDeVFSCSP5wdf/RrUSeWxPkymF6Qoz1nnpMafUIt0n0\nx4ytpveZWwAENy11qK1WIhy1JqBQhn67pOsvDOi/JkH3mdfUu7FcpiZnNLhPPdJUtrffX3trHkNu\njEQgdjtavFbNSE0iMNHMEqbN0+EYN4IqzLU0UnI8VBrGNeiaHCDteTHF91Fnd/z+WVoEwoH4Q51p\nzFXBZVpOB41fF1UL5wO+4uELKch2ACsCYHnW3Ookh1b2fCvzPLHmtS1r5B8SFhar7Bv+GkO9xA3K\nrjoiirDFUgFjx2NQ4YdNhYCaVQNmILM60cOFVKU+tOpocL2/jSx3s6PeR9FVrUyRuwLBxXLO2Kb5\nCg45nCnqDMnqtmFUX/gu4QQCHg2AfTrGJh1ujzRGn1J09pOUpkd3n8mPLohNErAXBOX52rtSaGdR\nOY4xPq9+JDvvFdzKxFTKjSfOza4bG7u99peLjceMoj9RCovs3d6Al4c6F/kbpmXFxs1B7pFDFDK8\nZF+4R4jt6WlmN5OMzrF6fragIUDJj6/+LhI4N+f/5TNAhIKItQvatGmHTXvTro2x7E4GKVG24fGX\nX2ZFK7OZb2gjTzDVAnAz++0T7r34EcKRucUAikKM0Lvi+XNc54x8pvIGU/hqPhh8FBV4G4t3bCw6\nmVUB7NnMkGQCQejwQCmNf1aVqRVful1XwUqm2zxmW1r/w2L4dQdmqm7OuL1QMeAcD/84PpFgdfYO\n9A4+OolFIPGWrqBEWh4VSoVDChY1pIukXQ+EvddXLFOULCPMZfsZcNa/lBrmqw70ygO297/21hPs\nI8zwnlGtnjrdjszOpBwVS48PaWZM/NcLLNZRStroSiwAnxe25USsSLiyuH7Hk++sqkePsXjPqeA+\n2cEtPxt2TwdWpIgk9PIBsGkRatE03Ay95rrIFRMvRSL4HgY2acxroi8IpU/tc7srpKRTKGCo3n+z\nbMHU8lo0FP2tKjG/Uqqn6grA5BKCfe1HAdZiCo/zcu9liGgsVdQrVwMbRS7r+8ifOkHYQZkCNsL+\n52vlrFOwauUt912efZTr4KUAVGtxklTBgaKlVDVUfmmqsVhPddezYi8+L++OGLzmjOgSWnQ/JOYx\nhwLeR2o7n33i9ye+PLhy9U/1ROygMPB4DWUuOPjgNjQELsRSV9tWL1euirpsUoT1wO2xqcO9W+qN\nZFs9QQmw5H5XF/3Oj1aozbCBrfBi0+QXOwdbbEzlsjpDQeddWJBllKwBC/Wo5B95Q/GlnIjjQefZ\nMGlXzBTx1u5nMDoTcNXw48aVd3Ie1Jox8d3hJCphJEK0vqMtgTXmlZu2dLjaBfcf2I+Jzqrl+9cw\nJzFOUZ2gTLkX4VC/JZBnNFKQa0/ldycgNqBNvVGKlzGN1GNP4l2CDdlmeKhMVVmJYZud9AM9NN8i\n0GK5gjRy+F59Tujg1QjNv8FAyuv+AsWqVYjVU0WCvZkRcIomRSqfRIRrkRsKlEO2UKKKI8K2DYLY\npXLEfjxLgF3M+ULmlEkUSSBchvW8crPb+NZmlQIPzmkUZ0TGiVHpRTSCwAcHAoYo8kkIH9NLhwKp\nGqtTZgUOBemW5V06LnEZJn3jGrOecY7IPs2XvbTwCNl9L6GiHwxYKyaAprr2XC48ilgakYWaWRP0\nKyvhOeKxzWOnbnsWskaHCEatyLlfuGrwTUq7ZPw7Pr+s6dHDMOvf4XJQ67OIvjBmv44FAFjsGl7k\nEIaajCX++XtHSY0JNcThxF53uVALV4yrKVOVx0m39sGlIyV4hwtln2l8fYAt3Fy+40+XO5/yWVIf\ner1d/SrsTn84kx3H/J7k1oi2kkbnbC6NAB1rD5jMIWZ76lLzURBTehg83ibyhtlElbd4kXLLpg/r\nXn3/1TTscoLDu0tbj/p37gYAWEQJqxX53IkLO5BFCZCDgylQAtYqeOC3EPZdDRD/aNLEQzzshP6y\nrn/6NtkX3B8WXIN7ZmBf8e5atOIWu2qHRjhGzbniLZ0d0zC3q3xfc030cWJRzgHTJXXqVbs9Dnt4\n5dx9u49WPBn7zaQZBAv9lCtnkob1FnjB7S21l+XMfJoT/Ty696jscibxLUW7Tde4a08tG0bzpBgi\nenUN5epvXmUW7Hr2Zg0ex+jhoX2komcBiHEdDXgqkdi9feq4nPzT4EgogkyrSi3cXgPAx81RVZh7\nYRBYpm8HLKutrqpWZTrAHRxP1SMaY7ANgQhfyHQx2Q44UXZhHn3vKi9TblJQylrOzPuU7+BK/z/M\n+HDNsfAPVZIodZdwbzmgK2hiiCyFkzyw2muASjdcapd3+WvlJaErAi9dxDwSHq4kKhnjPuYYN4/i\nU8VoeOyPdDb+Dmt2aYxIa2xrFl/T2lZL5jgrq8VWyAgUoOxhDeYpq2SEY6xlutd5X100MgvfZmtY\nrj7+BlvpRgMKLsz5Jz3DXlgoxovzKCxzoL4DSH9GfxfFgSLFziy376yV44cPzm9m3t18kxkDJK5u\n1qmSBs/LBVEWSFfPSEv6x9wDkevOla+GP+xZoznBYoqTQYhAuH6yILeud2X2RMr/fcRwrmegzpvs\npWg2PSk0j3HUmqTWQmx0YnxEON1IIPTuxqP+rtjdtIGFqDXcwSUAOCUZSfebCCRKBjn8MqkAb64D\noN4n0DWznVieNDFEgRiscn4xzD+IzmL+TlJo/HjxsYy3nmqTJxTfnc6htcB7y2cfL4kS2YxGqIcU\nzyPv4Po32ho5cX+emBSLkJpVUi1ZipmvMDEAitiZuQjh65k1VciAzdDJwLgpiqiBhzHiM6k+0mp/\nwGWDG6ovaUHpW4OBDiqyVuzmaklK9Y5RNubG4rmVHHL2OY7tYkiQRZwNa1+IfaZce8053vAA2dOx\n+wH0Ta4ROvXHjUp5sgtyKfcOp9l0AKRHb5ZTdvWn1Mk/xKgA6X/9FCtLnDkkJRJc6L1CdUFrzaqw\nyQn5MNs5DNBfiLleAMUAxwogMwjqqyljYOHqZK1kCAEZDd5fW1LlO5P/0Nam1zCKS1f9oItihU01\njDZGa3QsYrCWS+WFYfyJYHOs5KPb4/LdmzfVnpJbWyMs7HydBcKODQ6dboevtikBL+V2BrqFQfLm\nL9wYPrJVNy+WsvV7BAwE9HGnfZq4ADPPhOxKsTDvFpuLr1I5Arrh04Fnk9PXI0y9ZXsaoItLEMfL\niTueoe6W82VNwQipZc8pMBXN8aAIGKuwSA+XRyoCTcD13o7vbA7X8zczV/panbT1HfyEbp60vPhd\nwsKYq3u1tIgW0ZLQsklzyDYcS39wpad4MD7r6CD4VxQKqtKBw46r9s9fOnjL0rpyVv1+ZBVTgF4d\n1CoTEi1FiCSm5skyhPbRlk1iVGpvOOibfs5HFxTtluikbonZ2vvaiyePFjGe14NKwGCH4EvMQC2w\n28inlnx5qib36KwThgHnKogPlY10ggL+Cyjgj6bGgnqJ4VnXMn9MYsA1J4fRyOlcvivnFndk0cvx\n5rv3VWruaKgnidbzbgsnw5GLijtaPfgRcUSMVvmXBawFGumGb5qGOEFuNkbTAtCaGsA8sPEAJghX\nv1WzcwxdtNjNTPk3UBZluLqO77l/eqpnFZRO1fEXT22FNXybGDHVyobmDnvflhrWkGbuAlnD0LY2\n6rsyDxr3TW8B65H40fELsnBs0iFg0oKBCPwjSggJPckQIcIv3YIt/bSlYgF8b67pcbTodlg5clGz\n+Uu+PP2daR4WYeuOiiRneVMpLl/IMxMIB+/KTBMSPGrgdZV1VPH/HXCpo8AzEVrdQSEK5oxSUVt8\nrMPHvhlMSt+RPuAP1qCQJ0RVakAZSCBapyj5ePtn0wywuUM+6ygTu0Hw09CbDkbD9qKE02yHttra\nIbAuhs1HMrMwfLUICPRhDsGHfG1wnHSODaJF6g7VkzEgYQeloUb/MkY720Wv7Qb31wmTmSy+NJ43\nktqU6EGdEm97XMktJaBsNqza0E2wsG8FwXE3rQuH2sJgu5tLBQ0+7EjupZfuiVG/mtNZd8AzAvPg\nmf0Sw0z4Zkv/iMaLIvMcxV+TDuIXFaL+MBTIr1p+Jn2NMls5cEzyVHrLdBw/LjIucx5WMBSa55hf\n3TC/8lRB2X9JRPxl5LV/wrNXFwxKZJ6mo6sK3oE/6hOR+/61QfEvu1ba9NM3r5JJp1voGz1lA7SZ\nYF530oTWrtcfpysPaLPPr1snRgzankyUQutarDRwv+zb1Rwnxn4yjiyl4Dt4PHKU8UnBHVzULx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Qo/C9ZcZobaEBRAA++s7qcpovHJ6FTTzrb1yJCxYauDWqOH3mX3lfHy8kcxi7U0jB5DkYfYG\nApKp2fWM56eW/H5v68m4tARTubOf5dUKB2sKUnwnZnQFh3b/x97xCc212aQD4tP5Ywe/pXF8xrn3\nKVF4XZf3r35KxGX3p8UHwCEc3upGI48C4J7vECjnIEq5BElIXHdbTDeqn/w/Y361Wfmr/akQZeA5\n3vAIyQNYTmBQvX8zKCD2NIrhO+Ww1fGYfT0ztc7/oriYZxPyxCiqsG4c7HtONDacUlVp9PjtLNg9\n38UrMUo6VeSyGaPgqbRZEgWSkpRCnqSgWRi6VrU9VURgaGPiwFiBG27wVJitrdBcTpUm47itxz1v\n+4Pw9djw4xFY6A3e1bRxODY8ApqUQzkUGMH7de5TkoUoQfmNPv4yOQWh6MNBGCYGI8C2YgI6wcn4\nFTHTLhzKO3TCAJb8tE8cuL7mSq27u74k+JHB5OHTu+n2HskW8eTZjxgoo4o7Sq0YDHqFHHbDHYMi\n0peQydZem3nqpkZC9QemiwaGaGGCglV9p4Mm3GOc1hBIGyEbGti/fpJfeLPIpffqlQtLPOpNd7lk\ntZKMYd+MrqmnieFVmTKvWQMzLq79jZidp58QVhWnJhDqR1SbWVm+Vl8R4xN405uEzY2Ol/K0A2be\nw4WuYdOKvpVDrVWDzyxbgYzaKsG3Cm7fuPc56a90FWsKsXvra3h2Z3B6b5WqMb3fVJi8qws5L2Ms\n84xOv95YncvvD8jIc3JsE53esJcaqjRlK4iFM4CA/VEXWi+3LYr6q9xDb+be0Oecb0lGfGL08sJK\nWQX9QMZQXw12/yP9woYBqE7lZCllGZdaL+HB+ewtZ4iqsCXKOIDuMeN+TZiSixm415GSiFoe67+7\nagL3FtVc2Ti/USj4D245hb93mQCTRD+1inah8I6Gne/NfAARIWio+/iZOxh/7VwoQ3m0EAIvoChh\nZbkTQkHJh92e91SUXe3VSqij9+P40EgAmoffrPG3bW8bDMrZhypbnPcxGGOzMVDGaxCXc/ha6hoF\n7ev/iung3B1T9zSuBy/sGkm6xkKb2vZYuTtJyt/BYlUQzYUpdEx/TZi59DHC0y5LtVbMZM7JF2h0\nFu+GnN2Y+8mf4ojs1yHLO+WTUbhGu7YzaPt7tuLVTk1xO1gHBJt4tT1UBREWWEwYfW+GmtJD7l17\nDhYt68PSPHX03x5M98TVZzJaLQ/lM0bQ2UxySsb+y+2jEZql2vkFbZeIT8NXh7q/DojU6h7OeOTY\nQH1+wzpSyoM5lZCEc2AKsOGXczRsOAtq1XJFNPL6Y5nv19s1e5H+HgwVVglTsdmyQ8GI8vitNGKY\n8P234QQygtBEBRFoG4+ybVqYmSDwMiQfPTlepNunTh0YhfaEi+JsjvTLGdWCAYVOsIEs6zth7wC2\ntsPob9z17stNqYy0Q7sQXcki9bTrnEBsBB4YcIDYpCjF39efFa5LfLPuu/EuEeS2bWzVa1RE2w6J\nwMayV7hkX1bCLv6TUpw7SFYwSkvwqqTAksPUf2FbFF32uZVi/XzFwffW321INXO+np4lHDncKymy\nNUXJFKwrlDfEB0kDt9egWZNXvGWzk5paBqLVPlYqPUDMjK61Su8JC0Qtz8AeqMrdv7BLxxPeyHin\nWLRb6R2j6Ea1sYygTOF0pH5jULOuU/zeEnUpJ7lDC1ifeJsy3P+rNaTDa2jdASdRYy5FJnszOsl4\nQhpOkSpTFKPb+h4iGLuKekMT0u4385dkwuRFEVhRfqcVf38CsGSmINIRb23QPrjHa7AphG3n+kg/\nTXBhH8g1QWg4pJsnZzsRbyLMpRYMGsiR+jFGtl3F0P7cwXt5ehKGuGcDNM/fHJKxIs8O+5oSOq6R\nvIttztDVimdAiLHSbmT6d7FKzxkHDAhgJbYTKVL2s6IH2aUk1uurFVVi27VWlRcfdlo6PhhIIig4\nsTBA5yOdGqHNhh9nZIolPN+jv0RJXj57HVVhJAXY7Sd6CjY9/1mF3JBl3C2SONy7GkX0AXd9kgWL\neuHZ9kvZYIKknSi8vw3DKO+7mV5pAJJY7DiAT19FW9NgIMS/sk1Kl2jnnD2owLn1pGKOGn3N1e7D\nOe6oamk58PNRaDkbjQ6JiKgk6WRtjcH/pEyZNwV1MhevK4B4CvhT1X1UbjxLqTFzfoUBbhk+RX85\nSFN60jBFBuKQEKdeizGIYgNzwez3lphiqtdK647CzDoG2JG19qZxCXLbqzdHvbbUc5mKpo1Ewi1w\nr8GZ0iiXtmlZnU8CyMzlJ5wL1mHulERxGu9eH0odxHoWXA+9IbL6lFJqOUtInvMOkUZ1oS3hZTo5\nHtYP4ZO9T7eH31dAScy1fODKkIf77SU3LvOW+Q+IWLlAMUz9dIgpBaPEfU7BSjV/DHG2HmZNjJ+b\nKCwjuhTsoFxdZUfvPZOJ7JNS25a1y38a5jWifPuzRvJ0xtXa9+IX32x9OpLc0HoAIfUes22rUATb\nFCKtMEveNLEtf7pS6NAPYlDg0MZIUoOdwFO8NKurQ6x3UbHhHWkGyq6z78s5dovJBK9a7TgjnZUd\nlqmB/QTvlLKY59LtcvBIj95co5PubhG8fJfvxokp4sLBmP4d74Eq16T1gOLMIJwNIS4Z2uxR7Gs8\nBtJNWSag4tD8OWSQ9/wrNQjoPrTZLoDG4H4ZT8ccg5r9zToNiFTtiVhAf2zDqEo8PB+xXMA88jaF\nDM1VgbtxZfMj6fPb0cJz1qjt8dsLZY21mZaHXuyNLWGlP6Kj3Dt0tpQHl4cv8kRBsQq4UJ7Zh2dg\nbkUPlM0J72oCE/rEIjetopI1zCYTPPVcOKr4+e8jY6G9TkNRWj6alCl+TvJf7TWEYmhl/GJmKyA3\nPH+2NxurqURACJfAXDEgZFb/QTAtE/IViPfUAF8nl1gVxhauVfNS4HUfzSQGK3dNqkujk6AcNUXM\nwlTteZr+JfuVJagGZ0GHOw9mp5ydXEfKVhl/mRICpZ/AhGN4rfr2tXOYJzl/D3xkLB6wwvR6Pot6\n4Omy5uXUNAK12gUq82ZQDM+IF+foq0BnXkn9RwIrLH/t+jCBToZRb7pHtGlPTNSp5mHlpANWcP8z\nyeEowm4WKzEJkgOALdbh+wIa0TL49waUrtbRksYoQO/9sYRW9wVS2sV9KQWrLWk+bRngrmw5skQN\nE4iK/Mvw2Q82LeCw9uuhHiDCJauzvq7bY74oMxGo3gs2LzDkdi2woySBo32ydxB8paXWr/ZdPZ/d\nshuUbpd/7i555E+xS8sN2/hoG6nMwVaInJqURklrR51a5SRO5VbZVKEVXs5eGrQ4YwqvyB9oX+4F\nx6r03mCc7ZRHHU3q10sX7m87XDq5RbbG1Rh3VnKE76f+ixO7HmMsa+PxxmIHXUBeVB7hpogtyocp\nizxxUZ+4RmTzVYYjDfMr4bIPUfdWxdzE/M+GPKa3NPrOjL/vFVABU5aChDTiyL0mZvNm1mhBTNxc\nkoxP5mF4H1ISbT1go7189Lx/DudDe+pNV3IPugIuIqNYor8u5z6GqKT2cPY5JikevSd7nGd64m1F\nkgxOWteiKZpiMogoJBFlOjLekA5dK7rFiJIP7NbWbk1LLUqfmun/If9H2gmgrjrRJXJ5R8TnZzXe\nEarFM4IxiIEgjY71uq8fUZmQMvz9o0y7pVKknIGSoPRh3wjqiu0Fe7LJWalujxZl/eYyK96ZIjj/\ng70OP6NvHAdnW5tvI9ojUfUlys10F7zTmSo6QfZ4nR7YsTNMlHcZNuHSc1e7ilal+2kBfXBQgf6n\noRGdOv/BrefhYfSZAJpnwb3b3BSio8fkmKQLeaCTynY14yqOfEyeaesOl0V1x3b5AOSP208hmWAX\nAUykQlzaTfjk2a26rnfMmL51m2VNEfCzBkdt0GjLDfOWufAn5/ipraeKMBc4v9FKY44yVloQwGWt\nFnQoG5GjgnvQRdUxmPPKAo91Krx25kVEw3O1NBHD4DB9NS0xEb8TRT+WZoGpjeFPDr3Tau0aATmq\nGDKB3DkaPwJI/ymbU8Y0aDTL+xT/KEX3gpG5yT3lavwAv/3I2C+HjthWGTMtcVbGPBl/DNNk5Seu\neH2zuJOHT65X7vXtAlM7Dw4vJJlvRiqA5wP5XgGzAkgOeE8NxDFNw585UwLfOL9Y1XCjkTEW5S1I\nBAugdHzb5u8PBypFB2F4KPxJfDOYqpUza0IOaML3Kh4s6Nh1FU3vtoOFK/AL5KqAu3IQBR4oqN3f\nJ3tgFRscuaxN3ZDNw/lhU8Skmnwcun9NrQIOxT8RTmf3W6TH61wq5WoaiX+Bow8b8p0MuOw7Zjn3\nNG2HSHfRqxDGiZyqz064O8VyMjqDFrDEmUM+tnt20F2iuyHPORjgAsTXkUGl2wsZIzmu96yo65QX\n8ytPAfIjNdVYHN3ba9WILxy5+uZl72kTj92bMFUs9yvAbZ2PLPR+ryWnXpbrnHY06eS5aarfmkqM\nLQFhi4eo/KEzPTTsk29pjT1A0uEC2W0OXnkwGjmCGvZfelsdYihfUnstv0ecCeX1Wz5dnf8IZATv\nsI2+suGqUbrLgKa42z7ob2gFw1zKy+vg6RyFJC4IHHMiM3NgubTlon+++R986/o/I0fm57u4GvLs\nq0Za2hi7fstJ9Yej5Qq7mSVtQ03o6PlyBEOSaFbMWKOb1eY6OrmERVkhDHpTuaJ3XXspJBAOU+id\nWJYE9gIXMJWTtuvByrpnGL171Sqmb9tWWNVKyEMQBaI9vt9lfZOIr7Om+oTKKYsxblVEQfxHTIwA\nWAa86kOpT8VIVlLaTFQmJF1yzS83fF2y6NblEN64Isdkw1zXLskcph2m0loDvX2QEZhjll9rO3Qq\nXOuuKuVxYcFGPPSVccq637ResazF27yhf51KTKuQmEo4VfrlqtfDpS+huOA0GyPjdoQsRRQbqiwv\nBMomQGXfgJqhKphhfmHgXVeXX0JedQWid3W/sTC+q+eXdMQjtFNCPo9u/q4LpiGFqYkYYzV9efab\nn5pt6hW5skSwRk7GnEwaxvMNixtm1+G4PyesnK+rMQiul/fzZjL0JFmiCexHdvOkFWU69neUuVAI\n1zVVpNEwh67kNRzp/uc0JtiNDzLmrakuHAa9zhfMCBtw2l60wA88mWxOoP8H+U2UKpe/6C4HN01R\nzcVNPOe71HTbcSpVOEXYmyR7F1k2kgETFQTlXWBFhqHLvAj7YiALEy+ZuAZx1JlPacnchxc7LCk6\n2BbACcCqea7HNsEF3K5sTl0HsYAvRHNYqqa8sp6jS/k2maZSRaKB79VShQFJ8qB5VAyJZ571qI3w\nlyZ1U0KxARNyVFRFoFHR3WwYNJ5pY+Z2hBRXy3Bu+DdbxNXrBtcXQ8hE15foDtCq/FQJN1RTlVdY\nrKcijCxnK16UVcDtbG/JYqfAVpwMWYGieCP+2D8Pj0ZORNOYvcoj18PZgq1EfnqjyynUZs++/dfH\n43v+0K2em/zT4X0CFFQHLsX4qQCYep+hlLVmc7VJMG6SN/o38koJKdavZ48I5ooxFGdPu60Wg9Os\nOJ7nn9ZS90ekaKsSpaXIoTlEQnETDxJAas7ZYVyP9/Jz6irorVftvfraOY28fODmOlJ9EXTxPFxM\nM7j94ham9GZxTz5gxz2KlTiMRp0K5zH6YgSbjFvxnLvnxpoBHy1mhB5L3DsKmV/AAOh7kBoc62aS\nyQNZg84h3FrzoEE+sgNepwACyGkoCe0Zu1mP8nyko6LPGehLAQ6VoIbu4Tdy1AE6Rr+81w04Xhpw\nSa7r6QovxIPzlhM8b+Bns/nKIQaxHDjt9kWArE7Hy2x55mO9e9rYYOb7Ss4mojyD4wbELNBVaDmg\nJoWKkf0+KyJzgziXIvHJfIIbaRbJJmBK6A1isK054UIDfFuiYPTkLPi3QVLKLVTctbwBPX541waz\nbbi96IFmwpqgd83EjZ1rm4pOnqZILsBdTITouKG6BuOSWjh2GnYqy024Lz4cRNedhytK7geQu4KY\nrPfMtjhF3SqfeuYHCfNJmhN5h50Pjl6UBaMamxclg26gn6386mYoCmDDQUJ/cGK9JgZYrFX27qmt\nkQ46Y2AE9urommZW4tHrrOnWjlTnMdjAKnSzGHLPoXsFDPOCmb+Dki9SxFd89mKwTpcY0R2XlFJz\nFYotmkMvjjcVlopUCRGsPUCfdGfJHMot6JYDY8LdKsnhibwhCjBetUxzZSFFpDvIZunI8FlWKT+C\n9/z5p0RPn6DYngl5kFedJmCYY8joq78/t1xumPyNwUr+KP7hJEsQ4QYI8SKpQPp6IwiL3cakjYLu\np4hpqL+u3MpOFRmek1u2WJIUDEaWiTWc04L2BT0z6JvZHG2VbnDTmVFYlD98d+HirXNBImyJSaqC\nJJp4aaFV9KS7cj2ePhce2gsF3TQm1KA7jOQAWK7oaoI2NS91JuOmabbY5VwtplB7t4RsoBpWkuiL\nh8DfKeCB+a6H7O/VoCBgplwm9KaJCsCAN4qMLghEhLF5lYT1eRdjoq7n34ckFV4ByTqy4A+p1mbN\nMSRPVHU5ec6NwLk2EHptr26StBsnCXv4g/1m5zO5YZnThTGHDVORH50ELldsT8ViOQZm8iVokp6Y\nThPudSqZ5175mlwloO1JtPA0fQ/3Nc2YYiJ+eDjx3fYNWBZ7vXfhhnwA7Kt+O/pLQMwbpsYUBx+T\nxme+qsPdj2Fsbhc3Sfpngcgp6UxuWJf3wv695ZryMB7a/+kybXWRMkfOOEO66hI/PSFvwvXNlM7g\ndRLeCGQwkJFWNUArdNPf0lrHW7MljGrRPx2YA22syZ+7wdkQvpqCALD28/p94w+30jVCdzyaIstr\nF/U9Mw5tVgkjhxjgXASToWe6ZivmFg77FeV9uWJN+9whQZKc4lVnz88lqca05p54njJgULrW0jFS\n7oMdjfldM7iJpg+oYhfrEkfsLRuGcjuvZOmiy7MY8jWuePXbwx5+WFT6a1euUMg+sSMZSYurd2Pi\n3BeaC63RJpStMvEAYd+GxoIC5dwAH8ADQy0tcFYqaHNxEuzkaE+YyQCeOOEqGvg8yNKmfip+sh++\nsR/Bnzcj0eOTzcVclEn/81okR+anAZAsTyHi3zrXwN2QlGIYP0EhOw6MRZM8GByNvlC6ybSH2m8m\ngbAQ8hbP75mE56xTimFbvxH5i/ywj7iO6wF+Q/VYZrESmIcuWZy9ZopNwdiyEohOmH2CwqXJx+r8\ngp5HHgQZwlMsDXx8THSdVwUVW+1KLcmv0m9/FxiTkxxmXgQ4GDMuhe4l/XXmnlZA3ocvnzHICsLH\n/GhGyDxNb0Hb7IFRdc3NC7jR9+dvCPDwZy3CqZPwOo99wDHdd6O6jXc4fq0C3+dv/hxfj4IrPEyR\nBH6xRSclYcw+4YKBWHR0j6SQB5mhi1yIHXERaU3ey2zs1TbAoYka01hRDAZyVJ0Waf555NZ2QcBS\nJdbfYlMXjbQ/2Az2PFHvLwXBUpcnvzqgjB9VMfess7UrfH+7swI8To3sUIpdQpSu25kgCGpY7edC\np/KtAYcXwyZR2/gL7U3MGdCvpLHCAsVI9C7XUZEyqft94iJtfmqSfd6v6+8LEqZtNifTQNCORBbr\nFVy9tA/OjnMsQJG3hpci38+5oms8XPKybPHI4BaD8zulweClZca2zLd+osveNsvLjUqjuVeLQDSE\nXsB+SKx2qm99KxfjsQVGyDcL6wsEnxuHvvyfDRqhGXvJlyUBu0URcqwdt+nVn7Q2fK5gt1lQXIdX\nOUazzEQJWLlqx2s9nb7YM7hRdwi3dQTHONgiBcPCwjleg/EIB30CDNFeD3R+HtkVdfjB1UsbBRp5\nf7Aq27FmQsRRd7R7FHQV2qEuXBstdZEbW+92KPZiwK+x6XooY18DAaOzvE+eX2kqSr1ZZwQkpM+Q\nytxaMU7yFkOYUt8hddr1qg5vv3eCWbmVecpW933wYhNjYh/HH4ePMYmd+Nzmh3BeoW2wijdXcOZk\nMdMbY+ZWxdf/5ovaW8Wg4a2mGM/m8hAyXDkpAlRXqo1smE8I4E0DFw/8ccHlWyOtgjA+F8NHDxIj\ns3acCUPEK2ntOBArFQRCCRMcvcSfDwuUyTPcDW5ejj9q6NiA7KnBEcjF0UFCcroXNRA0plD9CkaJ\nEsCUVF02DXrMg1CjhtHqLj5wG7hTccSMRAtSz4ixUy5Oqw3+yVoio5MBptlUO6by3cyJu0vEXaww\nCpJI0Aoatr5Oj3hv2jeXEyTWlbbYsLQFoJak3KxJWk/jByPFHMZQhTt7/qWjAhg0oksZwzSPyCqW\nGJW1TVCTk4xajcLKhiVFN+9079Y5cLvXdiGnnBbNnqg0DMHtpXCNlGagBUpvGYj3+/Gy9oQgce5M\n9QaY3upX1SAL+Zdhr2TZN60oQp0LT4kXSf5yjksr1JDG8/Omd1aeNAgDuILjoUIWk1L4lWtM3+31\nYsKno6Bhq7hx5tm7nlXUjdABZE8viEToEHn5p9ZbYYBr3LybdJJwXv3smYVr8auOJTEy2OMhtOs9\nigT1MM6918Gmt4vQ4DLLGZ8YOJXOYMjVo4nrClSUz9DEni9maJWZCvC5NsdAjjm6Y3nf2cV18ylq\nqp1fJJvKEo075Jezjipd0OAZD7Qd0qwKxdnPi13FFkBXb3ZRgOCkMLrb4mrittOAHL6a/I2wihlC\nj5KTTCqSPc4ydbkCdNQDPB1OUQoJYukn13lTSW1i4lM603n+/ZkYZ0IS33WX9KGh0tC4pQUBXJzr\nZ5B2JenI5o866aPbfz+byFSRBAwKKCyqtVuwHJHiYpBST0BpwfjfapzdB0P/sXColV0g+B8shtlE\nvOPRJs5lAjJ/dy4Irj0jB1hHiIUTWl/HTJiV/2u21gHDZ4Ic5be8JJnu60oofIQFQ4Lp8G2CKBm5\nw+RwtKyZUNhLj0vOsQJsyr7BE96UoFPOWP/LRC0551h7hXVv9T6fD6muOXJu9yktl1+Izf38I2Ex\nJIoztkbVGUxArgvzoQxBtM9Wi+zfL9Y4+VNXG4/l4vi/3fldZ8IFlVX6X3rrDSmhUyjJRpHW8vN/\nQYdl5Ndh7lUalV7VwAkSf54DuaJIT+FG8b3Xv4nm8t6zvd1mexTlV6DRN8qB9DJ0SztNS3I58kSA\nfbx2f5lF0kvvOwPgmcfG7bdaQf5xn21O50ZruyZBTeDYFdFJpE0VpuhCBro+MGlZsYUPnnSNg4zA\ntFCzEB5rrpz+nxmz1+ex353CBK6luYF/Ulq8IXbao5+/uq0H60G9Upafq9EbHWOFtg9wmYM1DzgG\naPeLWGaq5cIYUpYmar3LA/NvoGHccEBcs+0VnmDG2RNwxErrjCR0CH2d19d3tAyLnF97fBTQ1CxO\n/LAluTk1lpNd0faKybsS+GuLbKgFkXk7+1agK1WUVI3dPsdwtrHiewozrynZNNkKkbMGRdJ7y1GF\nrXiCsxc1t46ex3kr6T2GR9xOovLF+lPracZrt1HRQ/HX5T6lkk70l6F+W/AH1YeJdqpF+Zh6+zf6\nBJmUe4Y+9mH4EQWVFEMOMNxBdOE6cEh3IYunOFw37ue6uu9FOYW3OMnIBO2dKe1czhYOpBfwlHLy\nGR5X8wp8cRtH6aVRRaSeuf++pQaDWtkbZtZhIizCTyNW5+4Zf0y81MXOD4zxS0iiVyTYPicKTnpi\nKV+qFxw+50gOSYZjPAMxwCnp6Roi2+hwlb9kn+ZlG0CgqUQhMx80+2Y3xmsa5NWAf2X+2UTkA7Ih\nbsl2Lkj35BYINiWzzpdQp7Y4cfYD1M9uzO/1CsJGi8kY1coXDmBsx1oCsmFGHjFYvrR6COuBNkYn\ntVaz82jmt5k6zFvEQ9uZnbM9nGalIJneAmpvaqru4URbhLwJ5r4+EihquAflQFya4hlfJX/W2kSi\nS/VpH6lUGwjIUSU08ajk3Hz9Mh74C1IdTOz1/VFINc8ynEBLDQpz/cw2BIpQh4gzr6KuAehID4nD\n+yVFRguosJCF+xsAZdcRAA3jX6fkrHFy77Ed96zn1CpLcjt0GY0l67w2DfDZcK+7lIKQAA032SAH\nQ8uSql/VX7zs8zI+DLmTcW2PsX+bsgQKGpVOmMcjMYxV1SNovqqcinPSTahrShMKhJXRNKJydiy3\n1YrB0zhbyXUUuspInM3tYfbK0duoPYbR5VdcXn0SOSiIZ+Ksp2KoASCfYr/XClfJ7WwUQwjNu3Wo\n9HttHRwicBYIgFrwmRt6TS35yxZjIipgCtlrdM/gjdxr6XWX3P5GHo0/paSqwe4L2GtZg/U2rdMD\n5rjQg146OOye5ezEFDuYb+VKbNSGZnqSLcR7ZSYYTs4TGTOGvyQDUzdY9e2JCcgCNGLf7625ltUB\nGaSZU6HkM0nOGgdEio0MFP701/YYXDQihcUJMj23hoMSZOJ4iZ6ETHBw9CTRN3YjN9Ty9A2axzZo\nrsXTgNMLDdTDyaU+rx3QXpTDUcrZU5EPLmCK47sS0EAmorP1TJFNJldmRepXuG809iGTOlVOiGD+\ns6NCuDxfJ+QRpPUKPV4yVTai6XAcSlfTk2rCH+GtKVEj2DYl82nhdnttQP/SkZHhmVRYNPh6IxpA\n9QhKqwsxaBdh3NcCLrcNcjuHywZ39tktxsL6NioTf2NXZuX+kCnNxINeOv0Pyr4CPVEgSek3UhV9\nvkNE1fFeu10dzzmSQGwkyX7XwJAKIOjBK+theLR6RBPrs9c1rwgL4h3P4WTfOWuJ0pTJC5MtL2uz\nhHZ6PSu20UwiQeLDL0exOU/WbHg7V/NlPlnFR0BISGEt6O5Az7NZO7VxeuTgRAYjKC2AZHpW4ot3\nv2RRLXZUbZLG+uwZOeWeRHJLeMC5uZZNOTM2Wzno96BXCRlaDXWb/uGxYP9hRVXQ7ckyD1iW6n1P\nVH9TDMhbK+Evj+1U0qMkw/1IrQarw7hXW9im38Td0jg4k9oP9IgKXPe/5eY/4LNlb7/YRtQqvFrx\nzhJjJT91XUnkauTTFeu2kXJakckK50ykQ4U/RyNL4dZQgmiSNWUUUeLTGAbBnKUeryWoH4ZD5HZ1\nVeCKMY5EHacWkyrIPVHhbsJvmfMoLa/x9Pr2ki2RhyWkZN97O1bfBaCqDEvWjMbqHwl0s76MjEvP\nUC/vum7CZRTw3wEwabB2Q6R+YxVkl/zrN8v0shGLmpZ63NfXvC50WLyNfIseTJJ0vO4ffDZsO2EM\nm5RBnpRl9/n0wx4hPztWG55aMoT7HnZ8DMkPDLEXz4KRL2BbvLdHbQGbfKaj0Q6yPGHb9M6KjKwn\nMwh17P/a0QCOUaMcfo6AaMWV0Ss1I3M5v+mQZICQjngeNTnKT5INt+nPymcuduBBXNcUrCb8WbhC\nZbgHpZSuP2CuyhtgtBDAfpCzTCQ/lG1YtbdPo9G7ecjmCLzTn0iSdsIMZgmvCFgUW+ERgRb2mJ1h\nfw5v+daWTAQedr/YdaLMWY8LnH9AIm6GHyKLJmSYFwDmHjIjW+5xwxKPn+rp2gVFMA0Buxu+CXtM\nfHFJ7641D/fzWB9KpJWkZrm8ov2SObB2OQxlZJ9SCS4eSAp7pX/Fcqgj/XyM19l4joqpquyRYq9E\n9rNUEZel4XAjceBNOtizBt+WXof2ZyVTGoV7rXrCHvY/wbXMbHIu8vW01lXBHjrtHPuZkyRC+kuR\nb7v85HBmwjRO1OZL75N7Tby6XTEWGvabMukfihzgtuXJ9dK+h+n4q6BqyGjq4QOmkc/OYfGUjfnw\nTGokO4z0Alhhmre+bt/Z3wJIvQDyjaHDAAJciZgIsnnzrfi5j3aIPmbsNWS3mvk38/Bsvh1zGFWJ\nHYyG+HqcDKaU+1I0093zma1SjE3x+d602Nq0mF+toKTC+R4woK6RzsvIaZGm1xbtgOiQBN8WEkEG\nCQGBcFJC4zacPhnTf5Q7VxbTyUHe9e52jnBZWZEFTmYjv/ZWkoPtdapgFMABDe2C5G3k4GhXPOZF\ncV3bnDYTonhS6rw7VQCkpvtVnUBZsr805bIfk0XxVU2zkcESdPbMUv8ATuRK4vNn6BMflx/nLajO\n8ih3Q63MBRyAifxDDvRklVFfDI4spVOAgVzC+8eV5JWD7BwZMpO0zCF6r6BSMAbxiakD98e75kJk\neyGxYx2OLeYLvYP8KCwSufjxzu/d1KvhjQtxgEwLy5FTA81j+8Q6NI1kGqFIMhCgiITRQrJ3s20w\nhg1NKeXulVEezhmcqpWLjCRJjNR+UC5VDiQocAm+XBCXSkDkZYGD2L7Jsn6LXCuSzhZjr5sQwKAN\nmMeAaNiM8/P+ds5ovI8MLUVtS+Hr7rlG1vMg5N3KHNs0yJPWP4ewUQqSMV8AknpwMOprgX1a0bk3\nbPylW57zwO2JpJGOj/8pa9MuNYREpCwYHlWvT4VrLKIh3mSkX9COEPtIlvf0gESS1RojVXwjFwJp\nGU2hAOzhygyqzwDdnzrUmwRKC8EPZfhKXfyY5QHYU8vd3LLw3rF/iEfxnl1q09/YTjqkXZD+/DHf\n/IotTvHqU/eYCHWKrSEz+V3ZRnAYbnN9ObXoWktSZzmQrNm32rdEGr/hwdFwDYrJ3jt+ybEBACTZ\nvJPzGRLw/YPEi3gjLiV/p7UZMFQeKwqasUpzgPVFT+tiLJnwUUSXXyHXrVMhTqee9Lum1TpcZqqo\neHYaMSYf6hWavCWne5bEtwDm8gqTPNPXon6HpIXnAeOGzJPNd+4A6eyQ8ZtySI1cPYGSSvw0FBNm\nR081p1FIu+UdzcaqebMiKQLowyph9b7tB9dz2J2X9F4kOTAtqQLt8jaZeTL+JqfexqZM5A8E+bo5\nM8DbaTX34gLZ6M7guqMHRiCcBgqlyhzIN+6FDli1niIcScmSRWrMoLEnbVZCwAPxUHdYVr3W4MXm\nZSkPC+8yWPRzrSUIVZ+bpNAsi6h9iohgpbvwTZuJurCm0uJte0eob6hCMJmcIsxhYG0WSH1yPDxI\n7pKHG5kQvwfb1463i6sblx9k6OMDUVXG/QsQb+iz0ZK4rSXNjR9nk6Fv8cgE9YzqIwUFLSAJPvMv\n3rDDSjA91PI+PhRG/p0+d1wWQJt7IGzrAigeCNkCiG/pwVCBG8gKb2lsnL2YkW+O+Ce5NfS67Qdp\ni84X6vix0gU+iRZj7hhs0MyRA9xepN89mkTzIEbjMYCsNZ4MiJADwkqImqgG5wsm0StsnR4LOcii\nZbZWvJ+iQtWkWOzfnhK4VYV7mk3+unCPO79AdfUyxmFIA8USbh3ENTj13MgVAsfZQAGcxSaX/mIB\nOnPmJCwWdSlMh9LPxFA3Bq+JVpOzzLBEykuJ+OCrXBEX28vko4GflYumu1jKvaLtiSkga7qBRX/1\n2TkmrDugYfk1kMJMdYxx6nsjAbiozhi1S+3sOa5v3KFG2bgOSusyJqNEIff3MVJ7CRk319KayWEo\ni6ZbraHhdoM4QC09miKXmZPI6D4vVCMYCUeK2vharLI3x2d9E7P6mqstumjtOkunuTPyvAkgwH0L\nVykYnTgoQyJSpOKyLTimtm9j/+abctPAHuGDx9pyNNp22deHOK8kWf8o/DgDmQtUFc8BnBUZv4af\n6ZHMxsLu6+VOaymeDQvHmmmfkejKlESScyXNtLm8XrT0K4i4ibG2xtgdRl8aIBP+thW+UYv1m6rF\n9xZA8dKPrPLdim4skE5cZF6AUjGXNhquQBVUtthhn+ppHTpNuqbD2W/E1zyFR7OjrHVtzktuIllU\nRv+d/aD5cVDyeyTGHcGNhYMHrBLQbsPiikpwLZVnEteWtrXxwC+zF7YrM0eFblM7vAv2Vra2yoaH\nhCkSUheEm0tLv6EnAbyEMq1cxYlOMBghpN15HTuwSc7PVjXBrB2O74VRpXYFOxNWaqH3kGHvYDMG\nvpO4nBGpV1jaREPiasBjkcS1QQ5aMoQmrcDdtQK3RmCvzUadWtglhsMYboi0wD/+kHk2g8dnkuD9\n52JGRy/PcwWU2VredPLHQVnMKZq3iuqH47SWd1scwcRVFa1GqoodKhYSorNbA22Euyd19uDwzGmy\nXi5dIXFQpHu6aBiEEBK9fMNOL/Fj9c4O3sETvHUfo2H0yUrDs8U8N4273v8PtxZbDYhKLPf60Hbi\n9jof5vWJkhgwpgFakPMdHLvR1frPNnp9EFFGVDrEjxvgDzlDNVDPCE7JLXl2lSbJH31wpnWDX8Tl\n8ijmvoiEIKf1h6b7stl5zqLpcERiI4Rgp+J+8EkZpOCB9gYGxaSv7M+4ziDGMgOtg7znXOKrECZ3\n18rn02UFiPfyVGDXsKpmZEvq6zC6beFvRXH4AJwu353geDcpM26pJLaz1Scy4BbsPzx/3X4bmN/M\njPv2h6iTBIFI3aMdCN+fLX8rOJhtTUDLfluUD2J5aOc6JBB23QuTwGWgHHDqSWZ4AMLw0zAciO+U\nJDL0d4v4cwbte7zb8Ugf5hDfLh9E54SyAUHdhIsICxrqBAUvJH4MpDvxwkXVaHCSTzAsbLOtjz+9\n68+01jaNuogyyFggEFHHNx8h3LItBTZL5gCH+3vqqB/b5vJDsG5EHUEQaDUpRbTiBQvXTjHnAm9O\ngFmxuwxDLIorjXSd9eKXPkeI/tjLk9HDaDEVkkEtuaaK++IqO8+0s0rc1ZWEqFzvs8Desro2BrG5\nj3sEP8qbX+DArtAaU4kmJGkHHR7GskTQdSbngOFzE6GX+bGr16kJCNOFU3207LvrpSN2cmOiihbk\nptsG+zzvH4IDIQQXddDg259nMuLio9QsDgmRVDThSK8Nvm+QJ0CMenwe1QwlTRDrNgQclq98+rlJ\nZ0mzz5dfxffxMElcjxshuBV7uYx+PzCxj/MmN/SjB/buYS2M5GJ9+7ddOCdv7gWVt4pUAUl1S8MD\n+sgtrH6C5bFw8Uskji4dNjbo3NKIT+MFWq5Asc18m+cA8nWdvzKDOUe/wxadulwEBAYdSd7uKwhj\nXO4q1kVGyL2hkE9fgaKTl2OCEhLcxsdmxbgMl2Xhnf8hRzn+TsYlJatZnyZf4ikbyQnx4l2JLphh\nTblJYWbqJ860mNwWK0M+2d4vtLALlyXOz0tjbDTiuvp/XdPFyqx4PEcQAFkJL14bEYVTS2IQr550\nM06jbnvlL7ejHB7hjSKu2LfBYyMXUmMdhESxz92FU9JwGnmeHeVtxrsY6HFv2yPKLc13ny8Giio9\nbgn0guZOB+3B0ka0ZfapU/vv72q1Fzcm/q1d1uvNVZ/2wqfL2EUkwKabznxRmCvzQYKLQFrRXt0Z\nhGQf7Hhtk4e+MYTI5Iwek96ISOnrI62fzaELABk/LMmA7RJVqGMyX5fN/h8CxmGtFOHHsxJUi7Mt\n7gQIXaQMGnbwXqgrqlIvsUnIk4wVMdKX5CAfUweEBz4RjkhoD0jG7pyBrep+lTkRovOTF/E+8p4U\nLgYTYqGqUZ6NdedCq00QU1flMWf88ONFxvLyi5JTKe87eZNSzE2NbAUFxWslQ4p8wujuzHAnLneK\nSDQj0YXqNQ8QQpmH/+gj4QX6+lA1GthhhhfwIVkktREgwk9tobFc4IEijbl3XUA9qKbPaITheNnP\np+zbPLxfQ7BYx9RFC6nAVCd6IG50sPjxmYraib1paOToczieXuv0xQjxTTn1RHehBy5UXK0qYGi3\nPYG7JQXKJO3um/fFuib61sHZao4mvlYLT6DC/+06hCmEhuoGICe2nW18AG36efZF+K/KbS6vC2JI\nQVYaBBpXZUmQ8cKi3Z3Tl+GDkIPgmIRKatkIaw9eb+kDMVdut+kzVUMDe84kqFzmaOq61Rvequ+f\ncRMaPVrpWPMsGRrIXrA/sEAGsB7GBn/6YdUGY/GStf0jCsXgWMayq5PhWBvyezC+zf1iey9s6TZS\nbOUv+rTZSMbzPfMP4eWi79S8aIk3+EuqoLf2uDcKkwfr4lwKmHuIQLaWmcLNZU50wlvcF4xetuKe\njd40YkDJ4WwG5Q9p9H+Mqyb9Zf5eT7Ugpu4KND4tgfo3lTWosbNpvbS6xYxP8fDPaOTCpCA2NBkL\nY/GWxtHKV/8a5azxAUoVuNV40LQXhjInowHUtY1ncGk0wUIZAAKqDvgXfqNDvZQ+5cfyZ4i04pkE\nlVYI+qaT8gLMYxDcsxB9Z8pNokO0PE+R7pGpfyFTYVImPQkEgD6caZZSmj165PYd+BXDV3TJ+1j/\nUnnujYpdMbWoKEqHqKO/QHMjsetgx50pWZe7aqR2JYU0D6btpL/DXUQWGlo8xt7KDXa8JcdYp6HQ\n5O0fpPP/l19ZKYl1xu/IcNqm5fa8edvyoiZuqY0twDA9kOKCOjGFfN6nObgiET9pxxJkj6WWTYUo\nIPwdiBggw1yAzUQ5VUr0SXO0fmxv8APITzBACphzKahdiisSxXJeJlusPbPhCmdFp9bYWqzaoTJN\n068pYHZEFGRB5t6DPT+vdMqrTa9rtz3yF0Noy9c/kK0xc0EZVz9SzCEyI7wOeXzuRWt/8Orhv8PK\nvDI+gqWvi6eZ5rx6+tM65HQmiwgOnsgscZDEBrX0XqknFBJt+NeF7UNhlRsJu3YeSxqgb9Hv+V8j\nn9Wm079exOF000uNE4eN+Qa11qV5KsiJ7w/QbE1FThyHaArlX0JGkjnNc7yM7s6IeKLA8l1FNjDv\nrT/TntYeZUaSnLVIJGcKwX+2u4QAaZ85H4xis3WlruV7Z0rUJX49uN1RsqIM/UPcYBqexS3OVqrG\nJRU+ypBYuYvSGbtzfrS7BHsPxNmM7dwOCAgvLJnOO83v7FjDIpKEtBtQ3kt90j13wR/PI/hTL1Tx\nVP1yGPjTX5efSrzAFqiNsX8lQvxoFdy3RnB53gL4lavldXX9aQEcxETu52Twz5iLFWqCXlxU7AZT\n0bZ+2N/28DVj2KG6onYOYfWfG6mn3DGnUV0xyVfp9NQjI9bIMgAKh+iqJbjDJ50KMx3fnM6QY/PN\nsQmE9zsNj8QN8N3oh7TDfaiOF7LBeanRRdSfLTu79fJLBtxW6fFXMbU1vaBsRBOJhDWG/awHfQUg\nIMmys3L1nsjNzGinQX8gchisGYn8x8dhcIoZjva7B1MUjn3j9VuWiMOMIf1PFqvS68eKS0gdO4YN\nrhik5psQzoRSCa8X7ddHpeVE35kZta2dFN3n1DA7QSq53IVdp4hFpJxG4F1YzTA6LIUy3wEDsMF4\nha6pzNsj1dA5Ydj+hrnJbYhXqG622EEj3ectacWZ6iKvJY4RAjRBIINGADLKcxDHKcU1xqYGydWV\npzcQvRYLIQOAAeclm5Z3f2Ix/Qly6PxDPrcv2ezhuF3u4L8tdinmU+fiBvVNpOvBi5GFzo6bGKXM\nFKDPr947hXhHzP7j81IJM0wngcAQ3Amp59tNsGkZjBn03J5xcx1zkOKXahNHA4Jrs5mm3FjuaWuZ\ns1KBKsBXvmApSe5ID0c6NzfrGxqpRIyB7uLSizbUoM0J/qkPciyEh66TYWkPq6kj/oWzV61tjcME\nt1uzRxOioD5MQdasUx0gmNEGgau/bBiZMC/lM2dGyukgqkN6DlopbQvxHv08ppCIKDcYF3pgdWr3\nG7im1l0uBP4yPfnkjR6XhWtn+ndyY5MA+GHHodAXM6l9X5L5cnvX1oOkjWLvdlnq2o3qAMmvXeum\nW0hcE+XNatgFahaEm3e6TVrAYUWVg53ZjxraYQlBMKY6TeIn9u6jt3ba1ePyLfq3ICNfIhPfOsDo\n8+uJNa7eLyDbcp9wjF1DznD9mtypq8xeDCqCBBe7YzdUUDQ20qxZYpfRN+fiWLGEJP0X7XvSce5q\nRFr4kELsGhUR24147U5Pak347KGJbR09BuOJLpwq4ox5I8SeXd3AoTgsF6LLU618IHayh0mCTldQ\nEKBOV0DdKTNCKmYETYAcNTE2g1JrLsKN4mS2nD7cwXGUFFA3onq3V6ChVMK7raeJ3A4WotvC5fYf\ni57qKfWDacR6NIXVCbdvfFzEccq1xfXFld2jS7j9VJhh0PIl6AgFCvbI1Bzjh1O83GWE7ClgNZxE\ntmLELxQr/lNOV7K3MLi/ncdom5JdM218anDl6Kdu8rgNmMn3/6UgfPtOefDU7pyk1rkNOK5JvShW\nKbWBQuFCOywt2nll38M/O/FEGuXoitKxBDeJbbdu7A3ZXDfkW2UHqxxRP4g+LGedd3EbKfPT8RUd\nm527jhkNMA9RFYQAgRL+YM68wMypzitolt0p8kzJoQ31dqDHuVJ6X/8RutN3g5f2vDxeUzejbvem\nM23+DVoy+oe9cQaSQwRTQhXp6ddIKLUhS/cim4EOyR5YrePquuRpRLKVD3ruWEHyrA8crABNTyHB\nxUcImAoqNftcaZTrpgBUe4vjtSEPUzdEtqAhcQNXsfqmB78eiOL7W33M6M+FM1ZL+7DrHMD+gmcT\n41LCLZE+41XBMMdjCStJ/fxSJf5JIz696zUq4GCP14nms8GIjiQJFlcEDfbkL6Ybgk/pwI+lqxWH\nTpTHSqnkOKZ60RaM8r0abvr7rpQp/eXxVg0rrX66TUfU9SzkKtkq2axg4j+J+Hy25ZCj/dALtcbN\n2uxUONrEJzLop2B/Tx4KdAEiiEiV89VzDGBS4um7rdmUaWhy+xI2AXcLr/uLo5Ucu9E4P1ergrQM\nhyEx/sMXEZAK732SQfIaCASlzUiNaCQLsv9hb7ECLthsd/FNzYDjHTdjy/5yH8hOoBRq72LL+tlw\njSYjySP7fqFYqAl33JD6bm8MwZSgr20gSlhOj6z+w6sITHtFrXcjnNAVhTCGD/scrTVUwFYVy3h1\ncY8C2JbXDJp96Gwv68YibtaSbi3ETK+zXg7VMShxasj9iMnNQ1Fqti6MDLxbcly8j14cXbNsyvuG\nyZiH1bt6xiTx62igve+uEpKtdepPmEWg5kkJFxOdGs6zhkf+Z+zf5nMmzfw66jy6GVE0nC51RrQS\nqt9Ck+vPtblW9P6X9B2zbJNI1v9EivEHvM5fvsd9eZ4fwIqv43cJAes7ctcoxjgrQET0vNo66IgL\nLyrrlR4PIgc5iLdIkmo/v6iA/fWmFmOmQ5o20ad2CO6e5r1au9Btr2WfsHSCrYiW71v0tJ0BUDLd\nllSUvwcyPSVmziszYfVdO82dkWnHyqbkpGAPbT4IVLIE2o0F0FwBaBfiXjojTyBEir4qj7Eyp+Nl\nSVBuvoBH+8MiIwYZOdlXesHfaoFH4vTa3sbmXsCZWNLRWFErStT4ZudR40RQkpaF1ks9SyvZV/bl\nXyYGexVWfypMAMyAHO1mxDcl8tJBeKmFbj9Ofm7AQ6aHKjhCgJY3EtfU2Ik/G9gSm/8soD6y3hFM\n3CprQ/LZGkFX2qU7VqAQzoErhJ6paN98O251LerlqfvI0cfC3kHpQ/88NO5Eol/DhIpyQP9FQuZm\natPgXHXN/oTij1/wdWsmxKanZive22oBi8/EhI55BRmYQaU+FSqcOx5ws3RQbtRprucT4lSYuoXg\nqGtJBODvlc27EOfRoyvyTGGjOlLFbA/FACEjZcA3pfdfV/Sgoiu5zDjC+h9/VmvxJpUqf8R+sU/d\naaarOj56mQLa1fySkLA7KyO/luN68rntYdcN1L62VLD0aHP/vr4vz00w5ehtICboBz75Rg89gaeJ\nRd6QLjDi0ssuNapzS6M7oIIM+DLPfEsYZGBZGB4VXrgxfnq1Jm2SInhkmy6jml/WrM1jq3ZULPOs\nZNVSwHhmQ86YU39BIx4D6E3u6XFeOa37/1AoaYW2fd2FRegXYtl/VocUvuOPoi5phqCbzaqBz5T0\n95vVOS1caembm1XM9r9vfGFdugHyOLEHf2ppezu/QX3EcJqw0xI089WWA5FcSPjLn/RmuyfsUPLF\noFm6vFODDfVeFghtCQMtipcI+vdonMDL5JCAUF6/8wJ9Y090W12ismEQ1xo6SxXAOeSVCJE7Rv1n\n94BSFSW/njvcQS6TeCH3fF52Dt2aY4cXWmOG3ljnX96taVpuHL/9LeCG8C6kU32pYbCD72xguO4g\nCu+7fR6JzYW0FIrvguhT2Vd1Ibejg8xit19E+rJpJXTKzSGrr05+qMFRTNnQ5y4hOJ0tVbYNZDf/\n1n7e2LiDp3g6OHIJ9X2jZf+kXRB+934EvQ/EkAe2ZuEfPZ2t6BNsCH+75/JyILvJdGl1OLm+/THN\nfZWGkyL3P1OjPqXStm4SdabIT2UfW6dmgPo5y1RMCTwjfZHLDL4SgHIrGzW2xYLk4PPhYMqOL7+d\nT+8H6OMaarMcMfzwSKDFbbdTJXvBu/NXMYVisavgdtfFuvIkDW7qbkUifsc66+mYvMYa1cUbPk/U\nl+mCOSZjflE4d0cj6vpA2TGSYPpvA1MwtIZRLzSoZedwticjQilgoKj/o51qRwQviTi35YTN/2nD\nRwblPi6arnIF0KkeT+LpGr5bbdFpfNMRMlhPohJxMcZqVvy1MHwJNSiN/1CdYuRZBupLbViPH8Pg\nblbYivqT9t1vFcFGX8KQ9M17qJwxuauF/iG5FJtLKB/JE7ji4sOeZrxV3Z55+Iie6QiyhYmtX5t4\nrfdYwXRkMoxLxLtGEfTryKGAtOQIPJ6W0oGrK0CQZ1YJQPyUoQsNdfznRxDAkpZqB3EKQyfSldzr\nrHzupfgryNeC0OAynQzJeqrrTEdxybptLH0Qu9yGYmRFHGxzQESjEK5uwcAbyRX9Nqqml50EkBdB\nYoYSOjuzvt/jTg7nP1aaHTg3awp5hcrr7YZP8Pgla8x3JFwWqseizj7jT1POifDneevnBJoBlWDI\nDg/h1XzMdd8WfBCGKXPBH3NaSSRDW7I5o4zpW9NTeCG57BwnWbRu6W/xUiqkiRB/EQYzw2+Hx9BM\n1pVBlUsJrGhK5x2uoGsRwNzTsHLtXvhLAovRlnZB01I9wazKFbWhFQoilBO7yiz7HBBZ3GIua8o8\nFCeU/KcUTkF4MAUpUMzt4fwkFZ9SP/e5GHWBDXIpw+hfX4oNlcXrTz2o8kT6tWnCSCRLZdT2Pb+A\nX/UoE3aUPlJ/TLUhxDoa7cYJR4uEY1f543B/dj8p9/2buzSTV3wqM4+0gceqb63j/yh/KLC2AYXs\nU0euL5TS8WPGQRPjI1jzx9PMGdv3aX7Z/x/viMBi6+LSNrD+q0eKCcNK6ezQQKu7QzHo1CKwiQnl\nGUsXLmi1BKUB5yiw+PAB4lSxLmgICJk6Lqu33QegBjRQekZC3d30beohNg5ohy+Kus8bJx1MSHnA\nnWO3L6M5Vduc0VGlhNra7MNoQJ7M5xwxHswP8C3d17OLyj71J5agbj/kvIH1wps/NTB7IC/GOANm\nscMTh/K4vRyWF/6DkfvuFmcGrtwYyJwZPrdmeHfJVJJPFrHmMNVrgsT4w6M+t9RcV4u7Un/gPUQN\nJEgsXADwE8Au0U+FEDknGlPjP8hpoPk4bUJoDq11m6hZIb8IagwCLYjVnny3y1GQGgESiYbEYszF\nB5OT5RXVkmmQl4DaZGaeVrwZmz6aEASaWpCUFN373EQQer38yUoKcdzO1kMkYr1HD4Mw3Ov6odSG\nqWvKDq5i/YQjm1KXCSgwHz8MB/sRoGeCueP1U8GW7Ijr5XFO/z/OX3T6s7jzoXEKuH0MSh9FvyZ7\nddHu1q7NyS8Ijw0lI8eQa9ePYBM2EBVUu3j/CHV+sEQBs0mHyGdMiuLSgzko1NSWcy5eys5dKHwK\nKKZ9HX1nrruBbD+rMptprl8mWb1NaZ7QMytmPf8gk6wkfLmtGYTtBtzfvR2jUrvTSFILSo74wtc0\nu0rnLYVliKm6kFFX6oKM05hUdUw/6+FIDxFlCGOUH5x0Sac4aZuCDkSrslaPW5whyNieXR2zLc1f\nAjxoKEzNhzbRfp/OkYEjqNfYLHPBChqhWfPNn2ERVSHBPwm9rvIEU0OjyoJwIHStMukyB+BoI2Sl\nHtouW8SGPPJbQjCdmZ0xixKrSrlm+90CBEn2XkuQLQ6hMOxnRyTkSUydULJS7rHYGCxVkRBe0Tc7\nh+4SeQ4+XPrc99B46bvbp1oJznaMORJ9UK39BfnRp3QTpvN1wSacu+k2ZyhgntU/jcNM8f6AcHwp\n/4Y2cWiXy/AiwLrjjGQl+Mx+0IR8vtvqkRctJUuZsUmhRwQUxTXg56F8zzKcgJJGqEXxekmGDe2D\noDwQgx1hj3GKnZ+Iarnx+DYzmJcWzfe/C59/N9apI73fBS/d9ydiFR8OOIOSRO/6qmPJtlDweZc2\nRHaXXFmWpfuiIVjo2G/OZPG3HXQhqvyYh02J4mPbmMrJG/XOaF+ZOCoqkTWBZWNJw4vxAi/jj4+e\nBeG7rZEfn0HyoKS8Ws5AG9QA/4grud3DrLd3BcrWLtzb+weBPKgaQG2VM9kzEVgpXrI1oZN5yAJy\nJfyUJ/6ZQ58dwvLU9CSbLuftAx3vmaP4bHhtII5iSvK1DFrStVO/nZ7qgYfUppkSrF6IeuMPyAWT\nS/xHR5qyaQ7lR66GThcmLxWq1B7kRoaIBqxlqh13rQugnIee8tbdGtKvEUK7XLwvKYlY+ZbJKx5A\naOMrskfrXyP+CBWw6B++3lUGfjXnjoi4cRe/E0LMOj1zoTt/+dchFB5lHiZ1RTYJKVGerq8S066D\nbFUT29xDosyCt++H5bkRrpghZG2ig3D5/G5qxO9Q1Wf0zimI+wmQ6PSCYUlyQpxyKtLyBVhP7MUQ\n/e4zI/AWzPkISL9ONtMwcAj0gDs2n/cY3uKY0s547Z3q1m1jnue88GBH+L0psViiSPI481k4w07r\n/JEdXSTrRx6yuwTxGv3J9Y4YClFO3KLgMSvDv8aXXV0PuElS71wxtvI7OA/dh/n+vnjmZBOIAQm2\nre1d0DiPe/LO2bieRYW8jEpssZeKVHObWmkIHCfN0GatSL0QJWPvoC5yw63pmVyOErFPEy+52Lz+\nJQAsbhNu175KlH1SAkB0s70GMc6fMVoUvCRMQItEFx58Gq8jisq66YK8cMbV9pGhTmXrP1kMfa71\nd5VIRcufsOkcXVfZKCj1DK+07SPddKqxsjeMp6IDbrQErCfpGX7ptz8mS2bc7bjaaO+Qleg6BZUI\nATjUiJwF4Q+Wsq+WY+AozS/DhU7UlyLp5PnGAu+qRy5LdggrEDS+52bJIyB1Uwc3Mq7Z1E4g3NnC\nD0rHikSZ64afbjoahda+ggQGhQgkQni+jZxxXJ7w3dbY0R+hgT6dVVJIckUwChVgej6e5GvOZSMK\nPp8dOj3+3HUoUQWaAXswR/WHpTNzevz4tUunmYbWcWH9WhgXUvNmWCfEUdRvhTsLF3rjCXW7QdDk\nc8qVQR7u+eJooSOnDTumG5fAnQNdsQP6eSKJuU2npVMF5KV4zlkMf2K/UoW6HDUb/x+1SsNbKLed\nWvf+MR7wtTXSck4idSEpxjy+/zaSwY1P/ENh+hSH/kBYIRaZkrlq78yaMCtoW4AidU4ic3ehuLzi\nDUCaXKunDG6cpPtof35FmvNlJGVXVEXDNBr3vWtc3niftTYYrmlBlLu4ws96k8cMWC9tF7hi5zCG\nN35oejdgdeo3680mEIFLj1NkGGl2uIxQVSa49zI9rqfBA38QcfF82/U5qZQD0HbK1ZPn+vCDwJfD\n1udrh2fE19vtAhJktUtvF227BpMQurgUJnYml9+19xqhH4nt/0r53/yXJ4j/eo/kWKpr7FECLdjV\ndNftVcyitTk8X4AJKcmjIUK//D1Z5rh8awW+JqmQOuxoKD0tON2sPm2C72ZpxqzJrE1PztMyo3kf\nFFVj5VGnmx4jLNO4h/j8LmVbwskBF7BCUgjVq8kH55pjc5tp0rt39RGW+qV3s61yoXHImEaIJbaJ\nPlHPt0iAQj2ELiKN/vkizViRji4CpLXIk25YmjloGIU4n6iOZnoIZvQDEcaoV2NhoG5FNYFLmc6D\nO7w2ZqAUGP3h3MW80Vu1SBCNzZPZtGl39JopaqvKZXdyHDS3Y8EfzhkuamFHj711ag63RgC8M++5\nuFNchW8F6mDed7QN4jU8SI3FD8y7l+qcHSd/JrRmn213mzfOA3j1NZToaIZgpUzGJdESZYJHFuMP\nblCTEj4h/6avWz+V2RLK7f4i50+JjJgcpYw0KgiZiI7Xv5GLfzLyc22vlGMjb4oiarzs3kEmpZrt\nKTTyrGGOFz2hEhrQywi8qWZmohvRBj/6MS8TCPBM/u5OOojvODUTcfafJ7c9KK4//RYVA/iVPKxX\n0tKwSAJ/MnEJbJ37hb4L/iGnCjzIRikxbzcbGA4flrtVYVyuxjDlcR5ze1Fp8+xCMYzefldXKtF4\nz3tlllBb0hHeBTTa6bgUk0iJpepsoFoW3HPJO4/iDUOfPlKIv8ew6TgwuZoex2Pok2lhzjCmxVfF\nX1/jTFxw+Uvs6WaGKZT+yC1azM0eg2QQ3K8fxqD7lis2pHUAYLfHP63KCoo5pzI/ixb+RE7S4KSV\n3H4LMGVxu4mI0AZLBbb/FUYHTkry8esup/YoWDZCoiEsMzEpQNFGsOtOBmJG7PEJZA/PoIMrYWaD\n0ar5CA+0UHWxTZjHr+JlfLqf02SGLRCUgnS0wMjTgOXq4i8pwaR6soBkv8APd2cWOynPNSMAhH/L\n4BayY1q+lPzsJ+dmvFA60hzoZLzAyqQFjlDUfmNENrg8bI/Nqtvp5zeMHlMVH5d9Mhk+cnEckHBF\nvxeXFVnqQcuNJRMm2QSjKUyTv8Lh4z+fwNT5lkTV0i4vOpWf9Ov4SlXm/q4hoXAIeT586D6pkZ47\nrVqhCInLgl3TGfy23x1yTR1Mp3mG6EkJ8PDRbNOiCrHu3rmJ1CN8r/EVw8S34mz6YdJ4R1hnsqX9\nR+UxThLeP98ayJZoPBIUdquN6+GOStezutu4poVOyGb5/mdWEnWUW77kNsaYLuqM2e5xRxjGGU+W\nlEgrWY1F0mnyY/AUY0pOS3RxwIlNfyCQx3+/PANvXkVGFv56pnV9pfVueE0+uZhAU9xUttWiGj5M\nNu9sgwOg+aQBww/c3unc7G+9JmZJJANfAmhYGgKZGdPJRGGHRiz4F638PjZyARTeouHptC4cVPZu\n1XGVjJo+H79+1uiPXjiI9/yDdOz52IlIVBaCDr82mR9Q7In2jgZVwrbGcC3xrFAxEViEm+bi+zGE\n3d0lXll3Sxve8nLZKKPsMYFvWyLVNGJQ7HUerfUmF2/nZIiO0V8bk59OtkPewR6JkJa50ud+lfgR\nYDtLFtjGW5vOTCOzSvQb+CHJ8HT5RjB/Q8V/pZMq+abtWu05jQ2GGBD2Pegp6MS49s6qaIBmmKrd\nSl929FzgpeXBa7yXytZyNjxpiflo3mQ6cx80EZwhWL+myaG5YyvFAtzqYe8pMHKqwuKQTTfrQrfT\nF1vMv6o1ZOay60k19wJ3X3SieHPE+55cYyfv0sF6G5ih1s/lrQXfUlPWLU/3QndYmJtISLDonS+3\nnMx9EwYLBezAbCRw+r7t2tDfnfwRSscGWz41xmr1qLYwH4lsUl/4mUnE2WoKBKLIPwfvnGWXkdpK\nsXNb12WHn7EYtDUgrkT4BEjrV2U0DYRdW+M4DXRv5p4EsflQteQfFZKRJE10MP2lD+MqUd0pvIju\nT0/8WXy3xkMTVVHC9HDoo6+cLclj523q8iaYKObWR840X8TKVoaG1sl5SWJ054P1/3y4C8OknbUq\n9CNz5Q58M3VwJgKM1PYZiIoXIfFkUiT8hBMnvZJWoJd7RNK3X2kDQJvhN/9u2SoYRRFcyGQUi4U6\nteC1kmm9N+d87qEPO/0jAC+VGpY7tCyoMFUejFVUak0Dt3Y0YPyIAxtBpX6tsbjuQtLr4xnP/iIT\ny26i7dCYZ4dUofSpOWQa290lVm2DdJnhM6mlmxesKpkee8mwmyeUhuPNi4bPdNFIfGndmV/j5MOE\nOYGuYqurA+CL/kGIcHezlB9m67HmmOthV33+0M8A8FToAVoNfVwbCbrYhAhTR0yWMLcZposkIKKE\nskNqFKoEOHnpny23ebehUB8Ll5negFEqb/jBqqrYCaai1J+POtj8XNU5yRerWu94mmdjGCCSkti5\ncRxixA8vtZW7HE7ksS0yrdhLFPZn5zJ1jiGhyg4Q7Gql5YvW5yywUSsAvxiDfKJncPoD3NBt+dNI\n5wNdVj7U+iV+RyCGSAC1e2vfX3lqwFWmjFx7De1LFVYo6f6wDs5aU2QdNxNgHiJ2JafqFj5x/wlh\ni4g+ec7LCL1kr2JTgRjJcpPqNYSFcXKlWiBUWAdBAf+b2YVioqB5iiGrRFhc7g0t/vc7UU/FQLK0\nblhzZWVre6vxMHuL+iGWYeR3UA8+ll0ssQY/n82ldRAG/zVT2exC0TZeZo0u8eVSxD1sx24zjosd\n7pyT5cXOZpLswnjwIkRO/HOJ7cAmFLxDlFgzGXWbVa4xmtkmAKxblofmTXnypytu5Yl+LFF7oACo\ndkR5Bxs8EoKodB4+PPmgk9xJeeY4hpGrFrv/lcW10W/iKg9pX+KCKllu8WDgrEM5iE5GNS+qEy2V\n93NhaT5bQoM+s3VW1igQqtSuZSVaU79STVd/G7XNRPC5Aq7v+2YUhJ+n13Zb7x/4lxjgDR9PCAHg\nNyWITQ2MPSgTsNgEjcaH4v9xrHYAVkcE0WfK3M/VdqMaUSYKYdi2ocAbMlL4h/cthRqpVIwlQWKy\nz/0VLR2/thJdGaGUgjAkD0tjQusK9U0wiRQsdt88rRqtL8w544qpL/Dqa9Ifb3CDMxeATwtlmy8z\nv03PxBaj7Wqqn4CX0pOjElUh+2BsZyGBYKzdcXC8zTvjfpkdTODKrz2neWmqfTkfO2RiJt2AzMGw\n1qEjus+MKhOejkqoaQX5eTN0eEfHzG3leUBtVn5oeyYD7c9qLnYceElyCFbZQUKwwQ8BuCYNXHeQ\n4cbMRaTE9ROSzH4QJCRUCh+j46+U9z8tSvyV6QxOpmlDU8fs28rgOK+5llSRw6Ay28x4jg2bfIPR\nmLATFzPR3cjs5c4Um/gwDJUFiZZdFEUPG6LJE+9jqgP9F0BzV73t1ICECTPeImhv6WKvkq+xqDf+\ntPj5cltCozPByyDTP3kP2gi/itZN23OspG6dGPXNStgBjf+n0KFscCet4LQPvx3xSHjYIIYfBRV6\nhm2L9AnUe5dZ3bKnMlt/J4SzdYycAkxK2GPouKW5l7p2AZJZbqx3fgEK7Q33ic0kEtKq/gqQfpG1\nRsScsMLqcrqP/f0e0a4Zs5LzmqqSsSYUQYUb14JxEyvpasUxpXtxZWOcDsAlaSZq3xQ41m2Oyw4u\n+dq1KBY/5s1EkplYyzHqluglbTdHIWNlL/DGSZcE7ivVJKdRmqgMJ7AuHn/nftbo0teFT90SKl3g\nsRrPlt4nwhcsijy3DTSnkS4jhvjQh30V66ABoGqgo+Mkw/lSgxtfjbahJNCgpDEZKK0zLfh9OFp9\nlDmEeTN5xWpoeoflqV6DXDQPXaFlMLek9+bnVhftUarV3/PxG9Ybfc7vzeh9+zcXADP19xerpnuZ\nqJD/006EQKL4Urq5r7GLcKyqVETuFiRvfxNI22tyCVvidCQlMOayAsJvl6aoP/gGlREBaoWTX321\neZkZgT2CGEJKhT9CWtBmgTCnOSYo3831WGqkyCL/uoGhFVvlbinxf4g+DC5FtiLlpyvXX1si09UD\n6gVlRVqZvz1H5hBsGwJUUq3oH3qMw4T9lpo3lbeogrQvgj29tn/iBfrWq3XHMSIij1hcCSeeqqnt\nnvtLYjLFVxQEY2rfainEQk89CWwXZnBHS9s15Xzr+czSrjySMNnDAP5IzKplHaNHMKD1Tsx445l8\nFoUpFP7dYSUh3cU5SyOTCK2meMGwfth11AYUXgBniRhUj4+rZjuNqBzLv/nfDf03WtiEogyVzixp\nt0xkenlRaWGcA0KuiEFLVcsikGb37aMzCZ+pbjp5uDc1/2Pf88wk3v6Iaq+wEV4rv+g/6QSAOTGY\nhcnf8x3ew9ZPumWrQlYatteTg2DPeORiBzTwXdtM7XTkYM7H7JerGIXfgccSTR3cx54/l+zCiLXc\n8nzCddrLpViYh2r9m24xALksb+sDUgKHJVLcAldNa95KcFzL/IP2xUVeQXtl38HXf3evcvQnPS7n\n9nr3dySrnvqyrK4WmP1FX6dcQYqfKWGKAUG13lRziHLSA4KUYdHTNOQy8faXA/XiZYeUNi0MAlJf\nYCcb7NzqupUuQRIC5Uso5Uz4UYCJEhi2VpZOTwczQvogWUhb9DeTAssmOMvvP5g5qR94nWsm/V3g\n6cj1manQB1oVZjMZ8tu3oqp4SCo4WcykOGWSFk1UB+Dmu1g+65EkP14pNb2oKVqTuJ0avdK+C98g\nNcS/oD8uuDYXnZyiKyK1Wo5KcV3dHtOWIDRzovrMm9kYG/XF3RWtx9bmq+/t2MouL/AuWTdN0xEh\nCQQLOi8IprSEe2YzBlZzlphVGV70casPf6Q9Zvh/eIaf6G+pNc9hML3hD2Hh1JAc1u3IohgIUBF7\niCGMrcSRu2pyvz1P6QJfD637JJt8A6DBlfZtYC5GC0dk9w83gtEoRoK/54ypi0jODm15J6kn/MnG\nOYkoPg2ZywS0M3namOiVNzs3rzhGIr7rl246giM84HZ3d3f4SpZhobM+2Wo+onL7MhfMK6Uj2g5K\nbxXKFaKCsUa6wfd7+ey6RITktehWoZpP/09a5QR2S6jw4pcKvWVY3DONeblDUTylDbn6QW9IGLnk\nN0mmwggq44YMIhICsesktgH6m3XUTmjAvqOcRXJBhWKWKy8ZmOcj2oNHIZDhHGMEvtiWmGGYubwP\nAVlw2JrcQ3MIjLXHx0s809bSb3e4OB0ELQhcw8BGU2z58oAypjGf5YUs8pUXiTxyZVFrkYYQGzDL\nY/m6GlFa4P7DoYAj5HQO5a9rm3kb38V5Mn8efeoOL6bFEN6NkZUXzqnxyPZWgCdfUFz4DvPNW6hZ\n/bA1HElKmstCnNgWIO73BBOBAY3G58m0lmbwJqEWuwpKRaesnLCkE+n1XteWyhwwjOyrPL9Avgz4\nNYJQDgKCZjJcjvWOMYAM69P3xa9keaZZRxdMRsMMrvaTRc7fQptb0+9GgJTo/Fd35MSkL8NURS+V\nBqKyydVZGX5h9QBqbZS0j6SxjuoDT0CCWU4qkZLKzxZXcdntd0YQHMTEZyEqnMKPOs2eMlTAjC4q\nZuPvKDN8mwYk3l3mArInEi8WeSqsioN0+fGi7NiruDskWbPh+Ih0smNptRN2py1mVh9EtSsvNvC3\nbKt9dwNpRRSaIwc5+j/lT+2EjzkoVRbj2IrELpXO4DsRM+ffHiTEWoARS7UQDX0zIGPCAT+FElEQ\nJNLDUkJYib5fMUjEjECAJUPrmjlpO4Gk7clYHyJvWbg2Mi5Eqbr5wDfT6zbZkinIDh6pSAv+UA8W\nRCtYza3x1YSDkj5GyaEbF/Huog07e1QudC3GAszZUw5Tgf4VT+ClgyO+RqLt4KFuP9uOTEfOvcSz\nLBu4SgvsbyAxrWljXMpnzz15ho2xoCuCvsCGozWgpo3YGnDbqtPovajpe1rzJnBnyyd7dvAnOM4B\n0XeNa9UNboM11sMVuCX25N81KtA4X+xu7WRqt2AweTN7YY8yVMusZ5M4nqpj6rsGsYIct0xIETth\naZs0L1yhW2uz5qtL/r5KkOkNXuhcqeQrZIzd7pyUjtTfSM4coUlibKVlN8fBtgNdrOd8HrnjULTd\nJwy4gtW+VKKcAEu6FLYqBSoA06EaccRfmQnFmi9hHceLcc4G46ByaM8M3S+ogV/3V9QkWcd8FG06\niDfrn3+Uak5GlC/mBY63QUDimxF41AQ1ioALaNXn0ezKFCsFV6cCGIfOzuQttWDzGSiVLo0ZBHkW\nJqzHbD+d8MB7nhDtEspuTETRMlPAmEmiFb4dv+thMMis922NbJznixdT39ksA6qzeAUjSObhn7ss\nT4AkJmaSl9QebFAylRoObZ9cnEzxwau5vVNsUX7WwgW7ixLkD31ycbKR4CKMbELx+KJmaLy4DuC9\nwEYu+5SR0hbpe6QVXQbjETrE/6rBVZoYaTOCaew8K932EJBgn0cUSDc/J+HrY7HgxATKiJIUbQ57\nt7RMLFShURujhtYov9ALfZFyl1gxuMq9uwYRAxqbo8MJJGIX5oabX0awoEiRqQJtJWeptO1uxwAz\ns1JWcsKClfTZgbJUGBigFlV/dPtb6yQaCIbYGTHHFYtVqTldlUetq5TcOL01xT6R6bqkwE2Qf7Qb\nbNJFLw+vBkZabol5OQBcBzqsls75NFWuKqJbMo/UOLidFwk0VgmDAuXYI9KvKa0VllSEmGO2zro/\ntMW5lv0NRs3x5XfDwP0mH7bZOGVPu6GQYfMywhGsXFxc4gAODmV2ZbUbnRiMC6dIR8g+H7xBXVg1\npvp7kKZhoTht2c/pc3KeApvfW9/XZIfFJX7p6NfUTs1NE2j4jEA9B9NV2P1mHueor7K2k3QAn0Rx\nzwWTbgGyfXlDmhi2OXKssbfLPPDDLXB/kRuQ9aDDI3cXMDUVhO/srqcabfgJT0JpmhACSFZVaOqE\nCpq5Tnon/Uwu4tpqzuwFd43K7AHaMhYEgxeCVPI9Ut5BxV1FW0l/NFl01JfUTc9eJJNXQoOgpn9k\nCJwaDAvATDhkJ3rBotd3NnyC7TQL4LnSKQ8xCcAHqL0ZVJbRkyif+M/BEsaB/N1aWSz9byt/WDqJ\nDXBRg5gSBAMt75jVavlzH/Tc2Z0b9zMVEeAWbRnQ1nL7XJjCgjIUwh+bAaLR4J20u1czFIUO1YcY\nnBY8IfbdnkZQOIflRU2q9r0eBkc3I7PqzWlYoMLgrYjjBNAp9zwoyT8bf6kPoD/guSNMyTjL0I7e\nz2RJpF/kk+kp5QHjwX2HIWD76+ZrKdIY8XSLZzCqUz2VpJJX16F/GRHQYzrQDFHTyvdhK8xEAq34\np0THKJ7xUecjazQ/xVyGPr1ezk3OXQMxKSbyDVGPPWUGROkgxALbws2tD1+NtrC9wPjaqDcga10h\nMyeLOFCwLRSi01ESOK9rAFmXcXEz/vTT1KWr38bH6mZd/f1+DidwoDLqU68PhdiQI+OzscAQvduq\nFOuMYKb4hiMDWmU9X6+RAtFgz3bsCmDgtLNv1qapQMhfcwUJmMoNE8WKQLCOK1FVNIcdCxg0ZCCJ\na3kiNo3ah28ylHtAPfA+86xceIJ5ZUrJL7HdAZQTi8jNyPMIeABtIHeeqmTDHwkQEBBEq6GaezOV\nTZVZ+uV6m/7LR79cHH6V4o4uEF2htLhlS10tEgCdNCap9vKFuuUmwDrKKMIWmdHuUHrXqVK7qzM5\n4MzXLgUJ4b4aPw4KegTDUWmYLc+oRBMOTgftHQU9zquLoct79AiTSRrWBx8gIySiWhSzaUqfEA9u\nQ9ve23TKmzzYbntg8i8ZtYtkoETFBCjNziMhQXLHZVXsMN2yA8OjImpYzfbcDftpQkVeSJtQOJal\nk/tb0YB3UesdztDKE7H7JsZWjQXdDK2azvenKpn/fgbmtMypzeYBR7dfgq4e8aWg5VlQ5LEvngrv\nH9lAMyRp+LgSWWm2YMAkILmEDPtYt8jf6uQPLSVhMsaH03lPNk5SYW24pQ3NLSwdtft9UDZWQOEC\nYGUT6CA0XmtH14EADfM7UWnoA0l3OEF9VzDJ9hxDyc0fU7W2UNFxqHrROSn/nh6EaDSoitYX/F2p\nBdyF154tBSNrtFRCY844CR8+ssFTbM3L/sjremQGnwynV4THVF3c872REa9vj/XHKdoCq+t20Rkf\n7OlxQZIcKLgLbn6Jv4q4YFKERAUZgmQr5H9OgwEH0H0hjg4AXqBM4CKFVlOgTr9RTCxnqxQhvj1o\n2ZSH4lkZ/EEx6WoM0/SJwsGSjsCi+kU0LP2iwR7LCocPUcFF2UshnUwdlZ6MZ3Y98/4YQs6Qv3i2\n4zVbHr1NzBupHwCHCpI4Dmf9J58tGqKvJXSwEpKjW9pV4RBLHhyt/fIjy5rse8WQAAYPEeP14JHr\nye9oid86O4afLfPNseYjbx86cixY/T5bMPiIufS19tcTY2IOD37VzAOxTq4e9ujeb9BgeHB0BAkP\nQKSjyKZs7FUHENwTfFDODSrg63B+aNWncG5B67Q+n6DPoshl7kRcdApelJNSnbfPWd+Cq+UZoAe4\neYn2K6lYtZ3PYy0ppXrSeMem78cCeUB/djZ0/OIOImEa/c312mW7EuVszAVDtMyXh1AYyIbiFfJO\n19p8QOJ+z20UZpy2xHMG5riHtm9KgvmYaEgcaKaS/WlLNqngsdRY0OfuRLuepOOP7RI6zxybCde7\npdSuA3ClqFvdxMMJQwLQw6eL4lx/rl2Rei6dO9vtsDjLDhRHiVp4tRiH1KyQ3UZF6FPfnFCE9vRD\nfNUc7bEORoG4YaTsL2H/4tLWlFusM7aP8+1fc+n0ldzbvVjxNuA1sKp3e2uqYz0SWyJ0ofbIxm3S\nF0TxdRM5V7UxopmS9zcBr4xCcY2XPvuIW3raqsyuO2FM1iHaAnOn9j9hDgiLFcuEhnJEXkxlXqlw\ndQPMwjipzNd0WjbXwzwpwSUkvLBJolHsb3zlK2BM918BH4xKLYhwEKWKLb+haJNxxqXMCuZk/2Fy\n29b8jSMhwsRGeyOf65aPrQ1KNryphIswqJkNmV24naOHK5HiSySt/VZr7Xr5GtThx2gWvGeFEK+s\nxUdgNULFejFlIf8qccGSHVu7Qt6Z2tM2ZSx7KYIrYkMNcBsEA3FCoAJZbej3M0jUgP1yBkcXpn0b\noFYOGOXBVBWpw0PTD1e5jP5cEwJrHVWcTVf7/P8gLZZkfEv17Kl9fKReql/7pEbujKIb3Sn5AgPO\nBggLAGGNS7qkGD9hu2I4gUkUptVYMOxgXoPIrDNkf/As7ltitXgGjnAGmOFoS+o49VEl4syKTP1g\n4ut2t4YwqKjzQCYHikDSr+Uz9Y1dW7L09qIAowAnrobQjeFeokpTsoxdI2k8A5mXq+sSTrnMuEaE\nYKOGC5MCb+iXo6sfqZgDOi5iHkObxtLt0gTTk2sCFxATFp/DO51vWaZQe3B1jEVDF2byArKNhKLs\nskFl0UhSflQRnxYRR4tsQFlabO4NMoXepoTXvD8cNpPSnzd05QZT2WjtpUeDiOrXcpnS5MfqKpVn\nswAzxJ4QVds4GHY1wHi/2DSEOXL5Tg2TUcZJjvYu5YS0u33BHCyR2KResDaMG8AOSroZpjv73pDz\nH8reJZY2krRXG/yDH41bwtp4hk9a7kNx7O8F7xc1mqz3ebLviFQ1FNn1pWFHq732IjHNcMplF6+j\nmaKD9yHXgfIOONKtszo7dev3E77V3DOSc6pNetKOe7kqXrmGlIJcTvQoCkUQqQRGptPnzreTuiYb\nIpw/DH8QekFMJ/L+vnfMgQ4Nq3ippW4zsVNMmtvdbhT3aBkvYPgfvN/R0w+/pvleUAMKkmdnYCVZ\nYHFPus0DTK1XSQ6T8J/APl4CASEL/mTJyirLeGF4mlXcouHhU/NXLi+vDc2sqyIb5CA9lxCrS7B/\n+KoJoRTRamlkjX6VbCQ6/LtpKs+OQ/VOW/a/jq6NDg84TWt00ZEky8YgJCxf7H6Xzwj9IBWlszEI\nCM7gAllysLSij2yqrc6//tDITPWDcCTdSGffoAmzyinYC4xgyubTNIfqrmB3eMu5+UTLkdVIzSlP\nIBzmdBPv6AyfMrmIJ/R/R11yUWWWPtz8tdA4aBXPaC+lNgJlboZwQjhNBjVB0f5nzmWEwP+F8csv\ntc4WCYYt1tPbvChNLRq5jDO/pQ6B0YjU0ob6V/R5EzA43dhZkaitjlELM5Es6LdGt5kaXw1NWeSo\nthEqXMwXtcs6ZjvhTs3Um5vFTwI7VPMrVKLTCfjKWYs9dRhNex/i7MGROOyIKxYLqrC76/mk8yHt\nf/DdfJt/PmAgTnzmdXvwTAQCrtxjxwjf36aTVHkgDY/B09yIoaGM7ZtdyVPJ5IKcaD98z/kkTHhM\nPeJ19neO3Zhh+Naf9JKz9VexqdyQtRdNnbrGr7e/gHr6dAhYcDaEcm6zEzfQVYTz0LqPQC7i3kTD\nH0ef7iWxIsjJbNzYeyki5s43zXUm5ADpf8Dne9RUDT1ndvfuRRjDlbuDAVzlR0ps2wzpjCuzfrGi\nPowd0lfxqKtvrXbnog6qIypp2iLlN1TIdkcCaOtOa0Dh15ozTAG819qBIS99I2Q5bWFPaIKla9q2\n40ksqEJYcn+BUGmQu7/K0tCds9pL1WKin4mHcyYv2mpQl0RtuFc79jUyrXs7JcM4XFbyHumyuUgH\nNbmwO9XCwuCEgmxqrktGYl4gSfTqsQgTiCcYBGIOdR4JdYKU6CEXOUSoxUTXc3HnJJP3vnTik/km\nPiQ8IxOnlIkZ41PVF3YSUKri5NAQKwrXNYwzMAZ70o6UYQSpZlFa82pOFD0yD+jC3rnbNYuiiGp6\nd654KxRnPiZS837SEuhqueTEndEe9oNTCQztMRgalvwJnIaGgoEKGCsmtqcSPhwzvlzAuJmOcdTm\nxVNgnQ0TFOzY74fXbS8S47dHqAkenvyw/iwEHJw2yXCnUvU9EFBh7h9yoM/5H+uFiE2sKe9pOUld\nndrRXYMhdjzKWkVTY9c9uhzjekZvZrmHUNjFmxo+PjNl9KW0xI6a0AvY/oUPioclM1O5yMTRVPDW\nDagnd+UhwtC9acKGG3dDs1nKJHXKo/qwYOkWEVd+a8gsGcsVn8pa22SDOrz/xheVxMxivahXZTCy\naSM+PdxFxa7V3MfuDCTxDr45D0lq4fpcehMB9ytNNL3EJd0bZn39MK35yYwKKNZ0XzsFZHQ6pO/M\n5m/J1XN9kIY8fK8V3d1ryAMU2RQ9T9goxRP1CERnWQq5aqG/zGRzaJ/lFdL8UNHSPzFD6DZLgVD5\nUZ5CIbTH5HY2b5h7N1fikM6g9d8NOeNw8MfXEimswCZgUKEIzCJY1YC1u6FXRk7ROQuZfEmkxmQy\npWtDSKeL7AEmVQ3io6DkY0x/7oQtycPLfG/jngARRGflzJ7F3uCwKh9FWQVXTz4uG4KQvKVCNFt0\nVnPqjb6mB8h/UCDXONuPIPyZc35IKGcTX3QOp9ul6UuxJ59WJSEDt8P8O8up7VGriZuGNn7ndTXF\nhTwmlt0gQkxSi+olPaudjTVOfOKsoeIc8/vn5RDrVc6oZBAVt6AkTDRH3Q4OPCC6FLNN3nmPj6cO\n2oP2LCAi78Czh+ybgqy1GrDBgYLHWuiG6FS/cLXFy8PF/xYxAAjylKC+U7mznlSaCpj4v80efl9N\nS6WH6WfkI8AiViTwEuQyQyER3YXspf+sq2NiSdGwlyQxlptPfMsg3SBmCGc9SA/BeuTdgIE9yDZL\nia3RPToopk5WfKd9p5VfEFYbafUrgBCqtr3/xj2nMHVin4Fqjh0sW8BrdjoFW+QBWF/weU3Wgm1Y\njq4WuW/rXhikVlInaUDAoVHtXhuI37dlAaFU5dxda0teCTOl1kQY41vCTPXvmQYpHA5xaSVug4Iw\nV/1I+3sFXaPfuAfZCTmJLzcciAPj7IzYTREvOfTKxvfMd0Ttnmb5C/vA12DTXaCrhkpQzdFrW7Ge\nuojNbm5gt5dLoEr061kiMQ7wRgD47J1anuovxDZVldo6DqjONmLtN4WaV5bqWW/s5lou/+lZT3AX\nnGq5W0nnKj/L1tl3nZ6tpc1RTWZO2cnztwt608DvszkHycUYevNL9OTqU+cD16Lw5sts0oa1dpDP\nwTBVLtC4HqRL3UsBQ6zUw+LRuErcs2/ea0qUtcC39BYtKKHO5eqVgUeTIb1SkWKFsSkYBvOO4ewS\n4ak2ppW5cQPuzkyAxPKkYLC/d7Qi9tUkoo+j0Gx7FyZ5FMjVvDSLtuVCe7BgfBLGe3P8WJLMJsTL\nOaH9PlzmXWK0/aVQFWXq5DL5H9Lje8qYEWmdeYh7VCcnWPOiAXthdJ1FJ0MrM1kWeScVSwJz2q6X\nlg57Pxh5mA2aicXeJ7Pvu0nO5KNGmacJp8qPqVL/IiZSgvjDTeTRu24eYsRRs5cVwahSaaooh8QX\nKyIt5fFBlX7NgmLok6BMjU/xm6drMXVbTKSpsLuOru17uWV7pDG1GCy1JZidw5I2X7XN5iZrHYB0\nEykDUHDnwDnyP3VEZYJ8vk2dHvHkG7YAZM4N9dIfJkrKKGXSvJrRGbLB5CNkS4DZbFK3ETJHkKhp\n9b1eIhGp2qM0XyjbKZQUETJlPcfx84P2uaUcWxwjDakWrSMoRegAt1uA2yTPxzuYyocSBjxYFIxQ\nDUlF5NIXcrqjL1aqx23l4l0TAxveZ8VI8Z58kuA7hcmdKXgN/yICIYn8HyqOW1JN09vHZiLQ4Pi/\nDQIux+kLdjvSMzOkp9uf66ZQVM3y+JEtep9f+oF011zTRlBpCTmi4EVMvFgfHzOmO/m6WBRV5fh7\n/AogP+3cwN3e95hfzTGXESjmWc8NVIgsdGwqRoNCRNuJFVsRMXVJwrvU7JBNzGgCcAVskzppyJMr\nulXSGO3wPc7K6TYmDHBxYnUhj4GUPCQKTGGB+90RLrcDZokf4gLzxo3ZNBBMcKS1PZ/SAg66sVOO\nor/Ldl5b/yBVNix1KQ0IzyfiZIfboddYWYwr70ot9DXVlgsFVn69EjvWO29hJi7n4pTeZErLnli5\nFlsddhArS5G4E+w5iKjf2FyIutWVlI3RLVBM3j3bJDvmGTGepXw12nQLIdvn+CWI4Btjz2gEi33n\ng4m1XV07Ky1m882N4OVqVLBxczCO4ag7NAjSZawMgcUffG4G8z5o2tbM8VgYkx9+tny6ZK95yEud\n3pLCV1lJ3wTG0x2NzjTIMqdEBPJY6cvC4v9jnRmKpgQ9ssMz3JqpVQ2ysQu6UIHGNkJ8Q64lVsPz\nrg9PmcdexaGKCGHVQUkuH6ZuleLod7c/ClA/1wFPXrdrvdNn8x5qtVUADKs7Hn6zYxvXh4Ro8ZGm\nKttayH6lGc9CXz/8n9hM/lEgFxnffn2RZ+A2fO/aQ3bCUv+Z8HtulzpDzxkhgHcs+/xdoOYub/N0\nOpZzpiQaSUnec+SX8W/gr10ZZazH9iPHSUXtSfG1hIVXC7IjfojL8VAnY/97BFtLQ4DNWfpR2gXV\nl+o5G4oJRwCPGTkHGpoQ+wHFlJTJgcVmsjSMAXjUlNTkT5b0piarpNcB/0kkeXS9k3zRK46F1C8O\ntNo3NnHT/cDptcgVMx7OrRo+jb2l+XTnCvNQyql7vZO2thwEKLnSbJlGDhtJD7Vas27NMVhiv80j\nzZXX09gzAoneerIjAMF9JhVdPz8N//A4AAlGEDXEybLBk5ySVse+GlNMhEkYOJVjiO/9l8cn2xqE\nXJ/Fbt9PdATsLTnZkqW7/DzDH81pK3g9N3UO07fDofsp5dC4JNcN78yo+S5J79q/AC8wwNpygnXl\nI7tDlJ3+dNmdwU1xH0GM1RUX4/WZkX1UZ3ixX0SB8JsyQkVzd+b4J/uvpz/MfFp8nQLeksvpqTAk\nl6xiqQvY+CymjeYVcV6iMJeTO0qUOH+R/l/cPgZrPWh9TIusALN+c9zeatrdO8gM6YuWkBdOFxnZ\nIr20n5J0zZY4KhLwTrcmhPdRPswU0WO59nE82sMz6Qj7C+ZYuSlfDSfabD2+HQnfBWRh68V7Dn5L\n/PQSBjg/LcWo//womYvS6Iup5wjOQKJqOJL8moVR0SXU02HBVY6pYv01f61iBVuFVO07VGuRKDin\nlhTrAVCzf4wdbjvtzbHtCtu5OA+XVaNOaxOF1OhsEeLIovm4Tj6jPx7DrzqcuR7e6mPeUpCcZjDY\nV+jqO1qWbx8OKur8k8wJKSlAe5Vzi7ICAwD3WcUHwIusAUp7RX1Mp53LoaXA0+qyV8Hwoml6ej5g\ne8fE2zeY3P8wn/f1IQvL2MmAi0lBqe/jEZuhy3Z4E4aOAPpzggnVNRASo2K7+eDFcfaBJzttHPeY\n8YOkCfA1GHlo6gkVQsXjAx3AdZR03kkaLy4P3EK/BLRPxfRYUvxvOdyPsS+PtY8FHQCGH66lulym\noVsVt5Y+/yL0p55qcSNd3Rnm/Kwly5gng4oNH/F0kp5ALKycwm0uoB70QYZe7QM0YTdWaXNRieoo\nScMxpoWWeTawaASRe129t0tvS0xKqz8i7w6jyO7yqlqRHlx3IfTEkidqvKrhecc5TdyRUQr0mjEE\nGptAbh9cHZZPWVq1WClPfmGVyIxVI01vLUfk2xpADobH1rQoj7YueN3JiH8FgGtJXP6N1mo1XxYw\nMFdt2WgW40WBwLel8vv4Bf60zGrxZgsoi9oYj0SaW6QoKSeAW23pww2AJSBOjkbAQojRdtNNPg8W\n2N9zxFfXyQ9zMHAOS1slfyrlM49fFpEfUVjl+mQnDxLwgWOK1xpIuzw8nkW5IFPCYIpt4LuDT/+w\nHP0WcaVZJ96ALSTYByR2g6FNG/+Nsk6ojvcXz/Jwt0p6i2Bdn2vaT2H6yJvFP0BIXUL0YPqEz71x\nbHBfg5Vnoc+KHtDOWQgauUabxXbeDpP3e68ic8mhW5wNIhO03QQSxYSb88fI9Kb2CUQ23dI42wsM\nCszUqSuU6tOrscdi7WSX7q6xzCP3XOCLFZ6tqaYvPIR/5nOMMfmDo7a5OqVbzjbPTgNK3LkRAlbI\nVEf80zfo5e4KenbGeJG3Ls+SYhksOlP2HNTXln9MpQ+itL62IVjDdhjg1OAqm+9cQrz7GJA0NTSy\nWQ2GJdysJrQFkN+M3n51Vq0Q+sw7/eVf+InTjvDIJkDvy+yvsVw8fcty18HJxWA6ewaUa64zKfFz\ns62w/JadFr0Bh1S+Snvu0MehB2h2nBVnM344Jk1UPLD5ir6gwF7e2TgcLeNGXXEXQbM2HleJiI+H\n5C7Gv9mgWZ/EyM9t5JDeV+bTYq1h8TcFfaMUy1cACEtzOlt7EZPCrl/NeaPvUjSNX6jR7Cyc7cCJ\nhis8m4qTK6ewNMqDpDIqVxWZRnq8FtuOEDvvEy3RfRuAP18BCvY2/f9jjoHZ2uW3xpDi8zfKNdoL\naHsnw4xoDPsVKbmheCjFCCkn50QFRHDAeHxacC59nf1faPrQX9eN4ld2U5F/2UbkPwSRHiEJYCTl\n1LkLxDkIEsE8++P39pwu4+2jtsUs99dAdYruZfBDNJaHCWfTXvkp3p8lOS2ZZwUKYdo8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0wplbVuhtaThbYwq+gfUEfiPdbQV2TvfTh/MV0Y7oIFr84a7zQ3r8KGIT+1XGB\nDr3/368z9C4P8YEMjta4Ohh3tjP93yRvV+IQ0uwayAACmdbxwrivdI8qFzSXz5/5zkD5VuMxRU5c\n6lYTDn2ROATq8dYCYw7G5rXLYo3WmgAYWJkrP+8HyOc9pI8kEKV/lq8BihKOnxSeh50U15N+47ko\nyzYcQBMq61/X48pYg16LJv4o+uvAHspW2mhRKj6exlrnEX2BgOaCTg9HYNN3jNY9UrcYt9aDHohI\nVO7OKCL+4cuu3uNcKHVHUfPkzh6kK8pqppcPIJP/bXliOK99qsuM0oHuMwEhBOdKXskWmtugV/eB\nVivK9r/t9w25Ausilj04IYeqOMqui8wwYI5dawYvL7FXFxscOMQfcIky+dFXAiZXxjZamu5GAZ90\neEsontKmaAlS+Pzoryf++pKAQaVHQCByIP0U4ktCB4CMvpOPH5RiPp9FyLN3BGK9nN8dmJFIe/wE\n2nLDfonpSRJhHpfKPv9XhNROuAlyhHlIYfp8rFRPpMOFMf0+x4dUSMYquNhoBW8uRhyCKpREHJQS\nb3+9akvAcBb8raYZMQ/738jA+u9D4yGvuME7BXITxxHAKCyN2oQiiSHCIpyr/CLkk1tIgfsu+7Fn\nBD2sc9f5ti3z+p8nWoRuF1Ps4iqHTdqhRHwlVyRIvcPVhPOkiy7dPeuBcorRhw59anDvaEeKGh3J\n/s/RI517jh0qTAequ0A6+5fqlyx+mdng5nT1v69KvLoSYlAMrWGdkL/o37ez1I0YgxQGPM7zVeBZ\nWiYapwDNAsNQ5Ih2zPy+3MZMkM9BrsWgPv65zU+xlejUN9/aPL6Hn7tiW9twgdxCNPp31Wx7TYFA\nIryLJAflSeGomUfa1s3Hie8KJJULRq/zJsYXnz2M+oRwQOxIjthHy26H90EYCSeACAZ+l+UtaLnk\ne5e37esW1OVbmInyGdZDOdGTmVJQB7DiOV6q4Fa0ml30oIWRwh3kDKRoGZ2UbTBZCgBYXMm+U897\nMOahXI9VAx3Ijo/zk/z14qYD/gUq5zMFJAf+B9ATvl3pIOyJexGXFV8L7t5w1cknpVA1ZvOhE7in\nGFJt57SXz7ny65MmQyUeVCc5eH8c+RRZ8TrKfLRPwWWFSOu/GpxgD5EW2XfS5vQQtUs1cgMt/wTK\nTs9vUv/QQmKXmWUjWhSPNZ/jXHNqoZfo1eelk1DE8UTFyrqE6l/DrQsEyhi9ZpDMyAbawGnovLiR\nlaPaBhkKtL2meTYY8YqNka4Kmg4eYL2q6cqTDNq5j7kkooARaZNavYOKRUxOVsjGKnI5gglZ14nA\n4GGA0dYFdqsEY5UgW0S9zrCh4SxvSptyNNBil92SahLI2MZw1l0CXqxH3NinyUGUKBrmEKrjcWGf\n+VOojgg/eeTZBFC10amIBw1gFcWvx/ICr7vhbcsxiFzdw2GTnfYd1mOSKy7rGWGAJHOcSkkzxc5B\noz6dzm5QxBtBCLxc8jTjrYJh8mEexlog8RYfyywWyEDxqtn0WsRWp8+Rnv+E/GaRsIWfAIizYOoc\nAf1UotkRocJ/4GoVhBOfS7Q6a4/LwoyvJQKB8Urz7w5OBieeohOnUwlwbwPRDVj86BYJzix448Ik\nNznV6mikSBqbkU3U8xuJWLoqzEX1B2aeupABdqxI8rdH6k45n2WKZqaAm9VbT5f63u58t5UQNOBb\nJ7fytvj6T2K3Vf1TQ0jpiqxfR94TaAS5bTNN6Qt9FK+MU4pW4EJTbcr9XNAXyuazECqOGoienOrM\nKCbl2s38ezt6z/X/LL4aP31wrv0L57ZWqe1682mmxsUs1P/A+mwRyCm6iYVcWNZyIfFFa/JwNnk+\nf7W7fDAKy08wjGJs/oy3U93oR3Ldc/GG3V5IM7yh6++oTaG1W1POVG0F20oAOCWnvQOre1t8ReKr\nIrhXDI6oq8jjy8FF0C0w9TWt12vTP35Efv4xdf4YOPTxPpeZ6Fcl+bQCdB9vSxyZbZuPuyMXGcei\nGJUbGXAgbSnsFn0bBPVEKDjVG8r/LIHA2fP4GLhewBBpWtOdb5bSQJnKWEtoJG+qVGCfikJ1A4vi\n9au/tyV1g3kvCrqLbQODmCnfFTipwhQKs+zQ58xnltdg1fLFdyGSYDzE8f80EYURboz/kuzAWpRS\nETQpi72kvWOND2Moe67Zr65kIZhQMdKR9uv0N5WX+toN2kRo77HKO/VtVrPYxGzyC+vVQ4h+WVBf\n1Mi+B/vXBgNfNK4bgJgK2SwhmJvgrdxZdt6soStYrbEWQpBErIxoEZqaxUnwwQxd4sBbi8hBI9Bg\nMhg7p86PaDGrpCtOSVk2vD+JxX3fZ2c/nYKwosf0tF2MhpN8iJ3ECxdJyiT2/YwJbkIf7Ojt/bvM\nNId+7WKd1tyZmZyXW6dHMHhMo1L6cS4BTVQEguoJqweufJMhbhTRn2MJp6iQvbVzPRroQ/meaVbs\nQ0lGUmm5i6RTPs4+rVd/D2Dkp3rQ8yAw9LFyTR7WwJql3DbDcPQwv4JtVkICQg5g94jtYZQtyitf\nnpLeEEnCA4EM1sEUVzOG6ZiBahYN0esvSCVk/7o7U5krjPtEErpCFNpL+9c26Tf/eZx14Pv155EE\ndAYpsCDMp89DjVp+Br0hA4KZw3YYwYTEbYbwtOIrXNZQmEMUNfuuKfZpFCoiVlP3SAFkdblARGxb\nnGmcavZmmQpmRvM8KqEdDMwM2WnJqqSHUteL4mX8c5DNovGymajPZxX7ZiE5jENPPVW5SkwqeBxe\nSzBmTiQknwUMPEcbH6aI90TUBI8DAIPCuXWrymYYlcNtHppnjObOtKbztuGooilnBwb1U7Cti4KG\nGrqBRefZHQxNfOQ/k4r/DhV/epVWHRXSSF4+8ogJYJc3rS5Ir+boQU0VQ/Iam67cq22l6YqGtn2+\nqZBp1YIYTR6Oaxv4i3u/8PuTwB6dHtfvsK2U9pzQzSwINJhENXfvvEmNl2DFpu1anbubYAe7jUDc\njB5W5aErbKbkb76gQpQLvqFpto30sbfD+u3OZIqjte/BoMIXB0dyJWfPWYU9l82wSDIteGve8Cwi\nXrXm6U/d9Kt1MwRHqItyyfUaM40NyLuV4YF3disFrPMO7oHC+49WDp1T5GoKNXh4HxSWCtVH29Wb\nM/O5LQLZ1CJYOdkZIQgw9HGnOkUrqt1wrkl0ujf0/vQj4OcONqEjONyhJv7bqdyrUvQQa9L4A2bF\nmoqMUkJXWBsQd+TGaYU8J/L9ML5ItkmDXFhAvUpbs8yuI+BEMebgHnK4JKU0odsEuyNUQaZsLAFG\n0ZthJgKsE+MFQniwrsui/MBDCSarIxcqeXdhkaD38U4n8CoLsnaSqoKnE1n1AQWrnBZ0lbopEjdM\nk4RUuEtXSUYqmxBOIFABYgKIK5OAJAJfOVhaPmZf7+fiChN3o2xneBrrEZ52jAMaxcBsZaD8iED0\nBfmOAT9twieROmanm7fzawwTxsqNKR6O8d6W8+sOGROswGMtKjETUbYYLmsiBvNFV/ZTh8eI8t4q\nM4ZoCwYkvwO5EymUm5dfrtDgj4BcjfkPVxm4/K8oC1opChjna4jUgvW0ITemydN/Ctuto5EIKQDA\nDiyr8cFE1xJGJsc7MA2ou/tEvj8RaQ+2RQW6e/AS7Q5Sf825cQUB65SwSHaMu0r9OmXgWxcvP0yG\n2yElBgSArt+3BQDADLNYUH/8T4de/s4o2yCsoDHSRuXprwYkdExNQDqfbYAPDbpxUovWa7vbnytc\nJkCSPnEK2/RH58pgfnte048SL0QsproqcspRKHEJTkcD5Um2bOydem99PYj5FGYT8koK/cr1HdpV\n43d+i7A9t61BtURiKZkB/EkRxuqBaANcSyXu3dAQnZQA5bDfV4lZoZJ/FjkXBfDJC/4ju+LFTGdH\nNf/4xTBGgYHcYEr59MqS8LnhhU3ik5KWbGxD9v+JVsM3Y1Ea4FJhoWNzwQXfIkQyvCsLghEBqX+1\nAdKTKR27rc/Zt5ZgFMcWL1v5ZldUwHk57YMxIIRZtOVc3lcRjp+vtUnm9KIshW6WE9hkc/pQY/+K\nE2uqOpTpV3AKqF41q64FH2YUZ9Lm5Sm1nezfoN5JTCdB5xIGobA5/VbUrXpUVHYQyz62wm9A6AfT\nmdmtkc/XWivRklYwf4TzrIeQ1vIWOoB/1Rj/6K4IZtgpu/Yjow2tdQO20YwwTDmmljoTBtZS4e7X\nfPI7rUKXxMbfE9S9RctFom3Bump4m9+q/nRnQoRiw00CraHHRP6ZSkslyoMzvJ1YMaGhh2aMlr7n\nRvHd8rwTgIaes3ljVrFTrsuwS0cCzTX9TxssltQ19hJ5kVPRrH3cy6bgLO8dqfW5atZI97UifHpW\ndmp9yqGNnTlF/d6p0UDUSUruxSmeDBxRLf7jghAj3iNQfEfciJ/2quo3A62vRkpVBWvuilC9h9+C\nCWRETppg2UtqTwiAOXIJXH/mfvXLSdh5GK43yZdttTNxZiFaiJZwRpwkG4Bkl32FNJ08xAtnmtjx\nCLyC5Y0RlBQisLJBNmUfHMKGdfBZOi8v220iPxLbbb/WQGKyks1EcW6BLRqjnVWGLRbOor0rVB47\n93tRY6m166yOQLNX1jumAakRVvoyua3ldkpHPG/IsWn8bNr+7KlH7BQELZFcvH4JqyJykM/pl4uX\nCjtwtuWZYJybPMVPi7I5955OnYLq28aGp/WYeqU9mGJK7vn1sKg3Q6zXMzaODCXP7TR2ri0gqd98\nnlkHpwGQXkKgFZ3rJ+4PmlN8LuP58fkW61uimtSpKXB8JwN1qvQFdxafZsvCTXqSaCVj4YCv6VTx\nGrQ7O71wXh8L0r/HmrYXqMvpO2WWhrdyE9Xv7Mm/+IMFc1Wk6Q6Hy62NGvGEt93dJTY0b/kBZSqK\ndFQODy38/SkAnj5ARVOWYClumuHZA0jmCsJtXC2CWeyvZ0O26u37qpDqjfQqxTSL1h/TG+Y23ZWz\n91itNaLV/e1PXQMFPcV3ZwYXi462di0mF3bXYzabeuMwRRaGz4FUzrgES8mGwJA5LFA4dgaDGBnG\nwW9i659F2/lRRTD45oC/Kmy7uHq4BgUGBAbboooFtv4bb0YM0z0HCsoVyfhg3ZHIt7MrDGyxDxJD\nbLaPcORvD62yHAvOyBI2ZWjJYhEaZ8gv+UMgNXadZIXD8jCyaiqnnWeJxZTI40gwAV7zKzb2kcwH\natceyCNGqiBORhfsct66ErTJaAl5etbH0tIDfx0SM+ui9mdkgs3ZAQHrf+EniMgGFzG8IjiCjM2p\n7msk6OQ6m4a9A+CBAarkbWrHJ/RPNM30wuCioQ/jFtnDmispKjmF0NVlSSNCc1VVeclARx3xogCW\nYDl7QMj9udZNHOjjaeTiJ4vpcfOH4A80OC3q1NyqQmIqoG6S9LbuvHBEqwz2+ySJrkpWBhb+W65i\nx1BIYKLCP5MJtfRoGKDAbj2ys0Ik47VaIYrc37VpaGntzgqaT/mTZivrZojuOhbQhYjHvdSs2WUe\nDeuNIspKpSs+GBpfjlFQBg80TxQCwSVIFR4lR1oCC6P6S/36vecj8DUtukrlLa9iJbXGsmZvj6a4\ncLiGFv5Zck5yc7Y4OePcBLIJXLvEwhKWw065L0jRGtOn8igHd2fPa1ubDXMEl9+OZnswaRH/34f/\nFtZO3sgSzwO/OfrcDvI8xwh6UjS0csEInL/s6/1JkRGvUoM2QQHVWk2illsVMm3FhkJxCui7DOn5\nnjxJGC3+0VXVdVXLTyOL0Mjo6iFfEHAeedDX5hApw5lLm4y09LhCs4AuqBHp1cfgkLBHc+awLr7x\nKt5l57yicX9DSvwyDMSreperwYvV8QfTBUK99f4kxFxLrWKPgK6BB9vG4Q8ZLM76GGBMRxfbQN9X\npMBlq7PsJUDnKj7pUHPDrCHKOU1tfsxhtVxgyfyK2l4TTz0Ec4bsCneFx0HvKDIBzSEk40924UHB\ngWSvNXxLAnhygvOXi3OOXb/5GDrCkOHXPpHymho7TvcAf7Jw/qbcJvENUgQTy5Vi03W1H40Ez0Fs\nu5fQKzNbqM7gGZHAvifAhd/rV6kT9Hg8jV6mc+OKiq3hvYPPdET75puOGv9l680aJdXxRxDYDMbS\nKmpjd2V9LC5hsUtVMDXDiN4M0oOjmzx8sjeAfM5Tp+nvTz+Scu72T34Ubwtu4HNdVNyeC2k+SrbO\nlfpMrzPmIMVvn2mSbzli4tSg0Glw3W25l7d4g/JkLtL3tD0RirGZIpQcQQPtNDxfG873KEIG8fce\nWwQH6+2plDytMd/LoyEO+Qm00AhX+kYupsE0PgHhUxnvsBmf69uUjjYeDoikjabyukas7bXBAaNY\nzdlkH2hpN9Kxk+1EJEW21Oa6ZUXGkE30gMM9XU9hbYGpFGTF/v/Wp+9lu+fh+ih6yJa7WIBXYt8F\n+9R1lIdNhWAsYQiZRZvUa2QbYk3BLpkW5KYHDulSEZLq0tHrK/J59vNnjs5UXAKbi+zpYH5kTdAQ\nzWV6aLwkFNmdK/iJx2FBIyCU8BLMVp7FMJ3n6VBbAm8/RcrFbM65qiZL6SqW19PQWgp/vYD6RqRA\nm/UQQXgSBa4vL6B7uZu7t+HYW+9HJ2CTzhI3VXf3md59MDYDuebqK5Va9gB1Z1AYa+lRjxSb9We2\nALbD+N2EuD55jw0+sUYPlF4Sl2XAX+sFqKs3cStdv12r9sfXBm+hyb5JLNSmj7F8ZxvD9O+KaPqg\ngpgfMUqvohKx1caxDOVr07b5zLTWqmS8uIDmj866+dRkMb0eFNVm2NPAiIePo9xhInuZnKm1qZZI\nuiNGBaakOKJJHFPwJpL7CeYxxouiKsMd9lBolQw0KwqwUFSioO/ai5H0GJX5UkXIDnHBAzrexKvO\nf+yfcl+ViZZS+1GTd37pcUzGqgaJD7xGzFSNE0Ltc4OS1ZFsUO6yBZ6ix0aL28eBLBUKGdcFMMkZ\n0DgDdrdA+NQB/SIVutpu0i9ASgpcdWIXz7ftLZWA4ai2N5J5OLE93dXkJe0XRW17Ty2ThvTKggss\noq3Gsa6vBqwqEQcdJnYPWHy+279W/bWKtz/lP9M94I22lULsc8Sg4mn63arND+Ut/+ik2i0OrL3H\nBgLqqD62jFixFegTWVeg3e9nsQHVZf6PkX0I1G6JwcjjTklZtInRXsYoZ6THoAxNZz+ZtF5ev4YP\neDmex9CvZgIa4bnrLsffWIwAw365PJ92fdBw076Ab2g43S7RmppYEzoFYOzefUUNGhXnxpqvyXuG\n4vgv0hdpAam7QjnXUTLKk/d5LlOQptJY+hAzZkNdv/kNZObEIsyNZDSXiHVl+EZH4dkCFkkdeA0F\nU2tLn3dgBLBX4nfkQCxtPkXO2LgQrt/7j4er9Rebhq8gl4A2JsNNdXmcnPIKfU9e/FwkGKbxVg9R\nj+o+DbL0RAGcrVebah8sykfDs61ZXhWQuwoLglSUYkYMqvyDVX6U1cfSy17Sr2MS4ERqlziu/17q\niyhZIS28x/Vg1n2bFomMTCQIYbTqemXrGJP2LDz1lm74BjTqQdhBH6+KoWiy8jHCVK7lF2Gr6NU5\nYSbXU2fZ137ZGQyzAX1RhsnjQd+6bi7gnxofJ19hfjNyRfeexbC5O9faETv9dZdm9MqmUgHq2MWw\nG9Z1hHP2t+pc0zdicDaMYTqd6IpZsR96UEh0jnG6XfiT0qbmVWBRSkrHEuU+RY5J99BNMfk+HjVc\nlH/55DyAK82P06//yV7bhbaIAY+3BgQMK3jnCssePdIVQW+SPyb8Liw/HgB5IQz/7wjkOu/PFmN9\nzxpmDEbVAFiFq1VZXQWzqLSZnVu14SM4nTj9Jjy3TNn09ysMvXO7Sn0rMnCgbDf5/jaIWtFHjcWb\nM1dl1HSkQwgN4jLemAg36GhqxV6JCXLoAEYfGFW9myeORhFCbMyXm1l3Rphh2w9L/hogVzXSeDtb\nAn9vOmqQpGoWdX9FnrJzgbTnqLxOctZgXeL6yTaUXsav4q+Hca3vKy1TsXU10g4XqoH/Mg5ibfHv\nJhYta+94am+UlLqCUtBtZN6gIBaaq8Uciy5Ly4mL4Zi+hwc80In6leO2oVT+KDdpX6//GboeSUqw\njQGFi8JOYuoUN78kyejHGvlH//1Gt9Q6txdO22SapjTX9dXdU98WRa5UytjB40I6/BcfDOJkoSGm\nfNLiDKqD5sOOlCb7mty4iLZQsPK/gJ3AlntFU1xJLls96SzX9gvOps4mraEFHl7VOSRV/zA+hasW\njgAG6zU0QFWF0kWt/Qbviw0MYYOoVeRWf4IhTWbZqLkzsiw7/5gnwQSGQ6gGjZDbQL5Pp5IZxBII\nlQoD1mgXryrEh5cW8SXARfqmRxXa/4VIDnOcPvqSG0wG/pNTeFa9L5YjNmduIgUpLjG+R6Uo14s7\nUDmZiXxWNeSm+g7EHcSVGjEBn5agtQZqyR6Q0kseP31vk9lH1LEz7Q/ZzT2sEKaQll9FdF8XNLTh\nP/jYpvxzimUa6SLkAWB6gcgpono/5I0jWEf9AsHdSpUq70DrIZtje8kDbV091J33jNggE8QsOZNc\nbht90DwxSXSwrL6J/5MSmafaFFvxGAL5To4NFZSYPQaCYrmM5CqTQRhX9SGTZeZraBiQTJnlhL6g\n1DdXg2qPC+73i81IiSHH8aqsKnZpEn+DmXKIdQ4XJSCG0kXes/+x+MsMc7dyJSPTdtXWITLhptVH\n6W4ZDp6UuHgPNPkumxKLcqjickX7cW/AfkJyKEKwt/nyB9jjm5AFp9LuxUUcnDCTuTMg/P7zkHsP\nto9y8KebtPlrudQy0vZiznxcWxlmKbq0ZkZCOqZnWRe9LQJSeSa5KNowDEoa3WAVcHn7oQnlinMt\nmntTnlvTYguH90i44yOA35JMvSWJNfdQdu6xIn24lxn4I5nnFJXB4NuQpF3gIlrN5+zEQn1t0OY/\nxFzdSGXrCR2qOAMEBWw+hmtKbGn8urmiHo8ZbZIO7m22PUbnQdiQLBloE91BtFrsyi7mhzLwTx/H\nQ9aZAoaRVbXKD7aGH0+rqx6mB+GH9XQk38dhNQfCA2BYkHBI7KRvHoXOGZr0sD7zbcXsFO2bDFhN\n2IRST/E5H2ReOw7uIdW+cLu0YxLta15cvpPD5iuJ5UoltLprmXKR2tJEnwgdD+Ijt0fFaJ0bY/Ak\n/FgIWjx+1ZXx9v+lA6kg3dWorsaicrfo1H/ftJhwqf4XC4500JQUUJSEeWH6u7+qnsVPYuj/crCH\nn6pMSgoYtIX3OImdnoxKDqHd7110DYG7150yf18rU7tQ6y/1T/dJNe4qRx0rqQaQhK3/xzZ/vPs/\nTS/ZB6z8aZ0+I8bGulZ4dqvmwCoRLeU/HkZ64R1+i6Fd2YT09qBLpanWMnzYwCaq3hgWE4f+3Q4o\nAZpqBZWLUXqLWmjgiDmTO7kaylFcny2oG+aJbzuCvjbtkYb67EanVglHqV/VMWzHDfLAJMSi7ltn\nI0dKH1wCmquriNcB15dzUeIaz3Jzlrls+T1YPyBeq0uhsv6QTKtkYJ04RD8qKR51aZCO5GPZEtMH\nyLRs1PFkLnyg1utwdL+DshubzYDN+9S8hXunyizNsepj/ZkMfqqpuXR+9tf2UR1GlTm9Fvz8OpmA\nGFWE79gKzrh1SGRU62HxYWT2YOj7e9HWqPq/qMs2f12mY7EchO0K+YHnI04qcqS/rNHC6pnm5ogT\nDW7MsBlKs8siikhnTHNvjswGr9qAb7WO9vi9whf48JwELZK69/QaSz/o/r7GzLT7L4Y040MkDi8g\nEtNvfDgpD8T8a6iDUum2/dm5TlwWm3nngx7778j6FaH8l2/7SUWQFhIb/0Rbkdd62v/kJfOLB2dM\nPsOMBzI6i/GzFimfliS1IIxbq+QQyoM2CyYs77Wie8DFkhj/TStq7xvM2a2dYZZAOjmJcGJAaHoE\nc//UO8e8tyWcBFfXhlt/tXG0ywC9zq71poS1WyzIy8uz1b/GqY5C674A8wY3tj9X2CSbZwytH54v\nxmdutHaN3GTW5q6M3MmS/fP9vUm9NfkkwKAl42WMh5MgNFu4A8eQVFAG9/tr4ORGwhXUj/93cgVQ\niwn70/hwK7hLjB73iZdAauD3C9U2jCR6ZSv98/McKJEP4awbCGP/1hytJcvlpgb8skNCBnFCEEbo\nmqndDCaV0eENdT4omoqyw8gwPwI673TI0nzkpLR/0UhTOndaPVws/b21tAmLFKkDecmtaiKqMeBw\nLo40Nh323thr4KE27X/RCH4ozG3ry13w3JT4vQlG6mqLhkJ7MyJWJ+WNwffzyWcuWfvdw9mQ77G6\nG5v+mlyUUooHF0wRJ986TAm83M6G4CY2H2/qkBC0fL2gbwuEwPzYBWvaPEuTOaV2ORoEg2ffAMoV\npoKu+j+wj0j2W6YRhzG7Zuta2a+pB8tfJDrtmgQrAAYXnjQnPMbW7IEhEjpcIMQgH9dyaqs7wprD\nkIVOhcXangaEomJEXqB3KreLVa5s+BvzhICd4Gb+E2Y8YojKflMf71a13TWdklO5PYIFLCIgT0Xl\nBKZ8W9+6C8gvN1c57/q9cDBtY2uIwiaUIj1rn4Zaw50IokkNN1RQHHTTmUCY88iOhyx7taPV//UF\nOd7cS+rfBfv7ybZ4BwWUCTeW6qgMLK/jzpF2Ed41GoBzUd/GvBpQyrkk+3Ncwys9e/bDDh1jWL5I\nzoGrwFU9RuXXWtCvbn1HommmxKAZFnsgclGRNmmZzMktaNwD04O6u8Ut/FYhTX9sWe0D/3LDbXqr\nUApN4xFDMgYn+q0li2/145FrwNQ0qTFzn15HfwxP2KlDWAkEWoTevRA1aXvUALQYreGP/pKj9TLX\nP3LEj9LMRZ0c/my3SlopI8HPs8bzru7BB3TvWDooGNJlwvwAAX+GLi/9qb1r8lxyUmZYLHPCYlhX\nmpMJ0nhxL0VqmS7RFzmlKcTHLYw3Hyj2WBlICy4fFJ7GZt3gcIWDbsJ4+HywRLQ0TObjCxEZA9/i\nBVsS6z/p0H10QwkgJaM2NjHWSHb/f3FYHtHWFBVsCEXnKphrTwp4ADTwLxgxlGYYFQzpnv8Oa4VQ\nWeuzibx31iRa89AE/V3SRTjRr7Km2DlbNKP7x3xtj9ygZwiuKicxv2uixhsw+5bNArgrupqUYlWg\n01qL0hMLqehWRnnonvU/C4lAvJfb9hH2rbq4gSsomGnJFl4LMtLZdEnfRpey15jPB8/kr9d3ApP4\nMp0eeQXVOL6x0oShjjfwI93/g4rQYxjyuw69wWQPXcNJWbgqBp8xMGa7HLdJxoSOJnTjG8xssoyf\nMm05pZhM3NoPEiIG2DVrwAj5h4u43ED2YUsViWQ9lgPBIBiyH599CL6Z6EOWL6uYeU8W5h8oi4Ou\nuVwcMyZApbw3sn31vyQ3K1BylFzc9lgcSDSBP6ieKS7vFsTtYfzwk05pSkwEKNTLrHFNHVYwjkrk\ndCfUhs2BzoG1SyXiI7LOBCvzXla01z9vYRDnxeruOqIZNwE47dxK6YzFqnkXM5eeBW90Zy8g0Ld0\n/4S8ZB6WhywVXZJ4RsuWJLBfhB0cNfa7X9ml8D2rDgkH1Zpsk8xdK5s6MIDFGtj5HqyXO7xyYaQC\n8yacVU+gnYQeglpDvmL53lGIg3tBMb0QAUBcs4SWmfIIjQJAaFt+BCqBwKF8UPPb7LyBTVm7gHgL\nq56aOSQhk7n2Qw6IgOxG2p2Qa9OhbY2eLxCgT4H6W20rpMG6yJPWlpciXUpkaqo4ydVDkgpVVH4v\nwsqqNo5r8mT1irnFkrem/eRhgKCkvmT/ZWj61dXiA601CoWZAzvAsE4JMDIZqYd7F/BeKSjZVcRt\n5GBoLTXFGGQ0iu5kV82RID/vzG5+pC4+DboOm41hw7ch5+euBBY4ATAW59ooVf33sofPbTacuoR0\nSkJzyARta264kYK+Yj9Tp85va884qnVR3AaW9wHdMjIZYPEyQslfDIaI3ZriBuoZU/9nHdytf4nx\nL9F0YZO427l9baOPGUZEstb1aCUH8FeTa0uoQMjtuvKUKoDS1j3zTaUEzb04cEwZ1jUP6HbjUVrd\ncywIrmgJbESjxbZvMHY/BXf8RpISYMcjLvNNUIrhanGQlLJJ4HRMX+W7YjuByBHLN0up0N0qHldW\nhMMwKLiQDOipqlbeGBDW6SYOM68eezbcNXJk0r8JqRI/Wa0jGCM5nfyo2UH2BkDWS4Ay7EbliQag\nDl3JfelRrC0Is9O+Kz6r7uK/Jx3gd+k2U/T5HekTE0K54jABwqHubpi+pmLaTwHRpIm+0QWSZQ9e\nkoUVCXoaqr6bdT4C9egBVsQuoJqtBBdL+eRf/BJ2F9y0ALs198HTVzZK0dmykMRT3H60StNmkAFD\nawbzgW6IHRIzzIrrwOjvQBA9cSvww3D0+PLG3Md+n9CSwcKfH7XQJ0lXqAVwT5dVqxhToR24sYem\nnzXeJDGNfULjbq4b57A8GiYgpXa+HeCYEB4xfmpHTxveNhjEwDD9uFzJS9Wah3JLhnHLfpHCn2XA\nQsVnOG/MUff6KQZbFlo5wUQHRzEoZrcNBTTLup7q7YDaKRFxkdKM3hMf/XJS2uXR2Lw2Rh5lxLZM\nY9e+VGMUUX7FiE7xqPPKBDDJcTZo9qmKjSiErCl0/sESWlam9Z3vXx1Gn5PIbhuBOL7nSqgvuAgm\nfJ7M2x2JkJz3MI06Agbog8CUia6ZJFPNYnDHgd1EmE4qvm0ihODnN084yQ6bWfYwU/KA+cvz1XDk\nWrAxmr8TOEqx6VUUdpW47EuCMEAoChPwszaHKjjk+unfsgkAhNPY2DHa9uNWTE0yLabgwQ/B5aKh\nELRDhmq+HCbUnCWcxX90K+Ba90Q5e37hWUEg1EPaC8pt1haT+t19jrK762cbv2cUywrZpr7uxt2t\n6vpqDooau1MS/RXLH/plUvhl3HZDA8sgBmnc1Fk+chSeozeW7LEsyJYLK+BimI80xu/b4LERclmD\nLfLMFo7BZTitH1ZJ4Zre13wNaz/FsJkquDUY0j3U1TbVtzElFsTqgFLgXvTpcMMoiCGpTFZvLPh7\nzrokRh792WOUPHwqBe5OuEPgj3Y4cR5a01VcazgS+uZ1fU7kOf/YsinzMg6ga2bjWbNF2ZZh8Ouo\n5YZgOVFjQksUMmDdo/WQAdbxFYZ68N+e4wF2jrYRM5FLMqlAp3nMY9ReHXOwd+fdCiTPSvJF3DAf\nbmyT9nFxEv8U8pSJY+dOujDxh7EAmmqNoeflOVXC6cULxmLlZPhokRecTp8JIGI45LaGxJb0TYfO\ngk/usWYUWYceqcm7EF9upB4MoisEvSMiT4DmnlviWoqqnXgV7b21n3PVN3Z5RTbeMOSNroOUfqxj\nGl8okP+hlrRVxeE67ItNbi+mgwFwD0ypRV11tFAcTfNcXVDjpaBsXW6xO8Wduo3aPS+GoGcJIcqF\n7tiBdP2090iLYfVxFFe1Kq9GGvYBGBO0G/5rGZjtEXp/c1KE+mArcgZZV82uzXRf1qLmn8d2LX4+\n8Mm217PfCNe2TbXKb3ClFUBlcfF8bAxf1sZtWZ2e2T1sqAUSOj/kAN80UKPCayi+D+HuWbaWbuox\npXIJrJvAs2YySEMXE7Fa4ITlI/88p1f0W8bFNdVxGpHL+GYRohah61zUQ6dsyAhnCgDR+DsYT8PK\nAKl9fhhFLAfWIpPL7ZW1UGaPdFMvRC3SuPhvsBDtz5yfisWiiiyw3gpqHyoFTthaLNeonk7WQVuy\n1/sOErlwtvq5vHR2Qp1YBjGwqwK9/ITTXJjTW8FpSWizCVBdX8wqObJx+FQJz0jb8sQ56jqA/ezQ\ncPQAfFH0vr23+kAvuJh08SSvUOBRL4u49Vpiz/aT7IUGezGb590CfEmigyOWZuH0ZUIixHkETOZO\nmadzPZsGd3sB8kkP7W86Fp/D49BXrh75qHvouom9MoDMiKQbawrAEfYrgzsKjHeZoNHOTNmx3K71\n6ruOAcXJMFcC+KAH0McWJ36Dz8CPDa1BxcNOYlBX2jvWmMPAWZD/x+TFojBboIp/9SuZqVAdANwX\nJ9Mf+kSCSZ+ux0OWi8DSQaXJLYQHOZCPuP1+EEkKhk4AbK55ws7O0FtkQXfjMi4sR7swJVbyUaqR\n8YV9WkMWoFJ4qybfbrwH5DQZtUw0Wdv+3q1su64Rv33JNVQ57GBXbVkIzVBpd0MsHyjwJCR/5mi9\nRTk0oV8OxUn896IV+oyeVtOQCvoDaxQvBrWjcKyltYtfraOR80HgPpLsMJ/7Rr/zdPismaJL5bTc\n2QQqs3lH1bEk1n+w5aFIJuQ80Tx3VpjeUzuKJiR6v8SqeBZKOr2RIZp/UhQuqagZ9mcvsYWVWvzb\ncsvptHV847LNI/0yLQlysCidEHSV+0qF9qSwbrJA4I51bo/9Bx0egeJtVmcHTQUdPE/VkGxKJ9Lo\nmiS7soez8eZguwDYr7DXv5DBZgaIsVYSsGfBahOKlRoKeRuOUFhz2cNd+xSaoCdqC+vsBbwAq9sr\n8NEXmgBwF43K4YH4MFVcH6XQXc9wKHxpjjxzDCGcePe5a5vdDoJV8CRd2gO27CJB8HnhvRcCVLqW\nsP97acXvu/eNp/msjOnEyO0/bF/Lbi49PnoT6dNsv/+dsKRc2mFXnHp7890HK5syUu0ncse2AzDb\neRlwUDXCYilbGgXHWv0v847h4UT4H+As8Eslnll1gqztxq18pXxHmrAqozbfgLdY9aJ/k+TS50lX\nf1JcHpmv61+LorVw7ThWXlVu+ffoNpOAfvyG4ZOI5siA9KfIUR/YLStSenpWZGiKb32cVbSxt29Q\nlha6Jqg9xnI/xNAp0VxTl+2BytspzI9YtAeTkacXxXu8MxvGid4FOwDhp1JQsRYS3VunmE27M7XE\nnTZ/izxI1AFR+8U0fi1XbQFLew1C54vF/mVb5zfbGpK8UNQ5hL4yRF/uxMZM2Pj1aUgy9Grw5pFP\ngr7TCrVG/SxpXJKTnGR3CGdYsoeOBa3QhT4nyVI1slagWBj2r3fc/g/tvPvR5Q48u1iPdbcYmhrr\ns1QN+t8TEfl+z93Pv4aNAS020TcbwFcTlpZ8wyAB8bxXpYbdxh27VmouVt8gXX5feN5teNFqgcUl\n+PAUHjKyhPr9/pnTWGt/5paYiDYY9FvYSEJSGl0Bnj5hZIbw9+hVtMxYeZzr27TcB0TOftYF3++s\nSXTep5+BK6e+piMFzhepIE9Mpn2y60YDkRzb7i2NBS/OZy7jQ+Q5weucdtTBoWSurSQZPO+kiFH8\nI62YFRr23IhrCTP00hMgX40hku9wZ7g13LRi67d+8y9GefOsZpbFP6SqMFwUa7gUEVMXxwVecQ9c\nRkwWOpfYpkKL0S21Q5anrfcl1O4GPsOHzSL8kFFXpgJ4vQOAT/58Z28rzlMHOf8MkuhG1zrBd27M\n3XJl31k9xl0T00uOB2vIuOcOBPB707vEq8dl74xKhGSctrh26uy/oPZZ+opWSW3/qoWCQKWYDIou\n+6Kzjqd19lx5O3pkTP3XkXyOI4g2rVQFO3pB8qG7GtS5dVh8JhvnsZNjYvFtw3yRDaUtoTgmiAa2\n4Zm881peB4mGU0Lh3rADjjQLsF54BGGDMscxCWyJL/PNJqF3ig0NCjFI65TYU10hUOA0w+wrauke\nvMneKWM+N+SzuxUrFp/6s177GftTwtRXFBX8TKE1bqjzbj2IAQ5d0oi9xmyMlYPzMsLcrUgMiIf1\nlUduD5xz7Gd8opcp0BimD4iNrZLimbOH7ii2helhFzTQnkNPe8dZdZNtKAVu01A1Vblud5z/e3mO\n5Q2JrTO5HZJYSQt1m1GwIog87eY295KLLEn190av10b9OyVGUJWLetypRzfIoqyPdPtzTxJoBuoJ\nYCTPrs+7oSAyCAhvV7xm50xqHTmHzpofT53mqIcBHa4qh2rPdMcKce6bJLe5oMv5y7+VCE2pFRt5\n2D7CKzdD42I4hGblruWWdhp32S7Y1NFxFRBnR7fn08mGVrDQg2WXw1F+CbBtsgW0SosN+Ffz+UkE\nQhizX5oeUBnZOQLNJsl1vto9cDPjOs11zZQ18H46vKypAmgzBLvj/yV/1LLaUJ5peAxAhQ8zG3EF\nuPPIXDgHd2lE7X+Lck0HKNmZNjNSvZ03VXed9YqmHXhFgh/MtF3hiCTo6dr5mc6ZOB2qupNbKmUa\nThuzQmf1ua+cauGo/lVGUFAOGBLb8aNHMKpepM7KCpOU5Yjz3eIiFePyb1VgJ5lth+hJnA7GhhJH\nlgmYBtaReJ3Aq/nRdvWD23Iv/VxgYCnMemibcHdtno5zs+bwBVCsxTAFot+ezpD7eXxbzs8a7wIc\nj1O3uzGsLFf3yCKySFMdvSpIMhMKpZ+sAKj9X1vVYSG6gs+c3WPeoeQNAGuvFDVPkLmp0LyQONkC\nYLCI9nVXjwFCBpG2mWQN5LB4D9jPQv5lFdkVLg+ALNTvJHxRNuqbDX5IPOhMwmr8f0mXdZntVm8P\nilIAaHkWuEV09Zv4uz0vtpdfHv8livbnylcifRHLUVtFnzxhnRS0i37Df4STDMEnvo3ZZ3lIFEjF\nc/jQxTQU6agycnwN6y9KYU7+TMesz1AwH6JOhohgXZxGiJjFsLJa32Gp24eLl687GAFjAHlzsox6\n5T0i2muededM41iijGxC3NPq5tMqHUk+I8/cWU7D7jLeReZgSo1qXEDVBDgCwtjVlG2liloNSnMi\nUC2fOorxciBjAc2Axm/u47pkCTVXh88PvzfX+MAa0XS42nzmLdtIUYbRDwu55OoqJWRdJIy7XXEW\nF+4X6kDbnil4JWjgQT89W+NOi7dgOo4n477obg9l6MiTFi6isEhWzoQle47RWMWIhF2DMjb14pcJ\n0otjaB5DC+ac33IDF02GPFj/SShqdiN0owZbVqDXLkx9gAmRofEa0cE8/70LrtG6EFeilFsWlu3K\no3A4frwgXt6FQJO5qGqoG/J3h2cGn/nghKOuBuiWUptGgTVFFis+t/M6oRnnxq9JgidziNZzr5/g\nPEfH9aTOJiH1QbjpXb/1XCntfHQUH4RXKGfm0d3+R8wU80OW4d/dEHRWPf+FwzrsOTE/9YQM6yqq\ndv2v7lNqEgUWGKSG/MkUIDz6qVFSzsOw3LW/wIlI3fuDvjvAwR+ZA0FxBamllElAsAKriRLs1o/8\nicjTMgoSFXmaTNDCE3auhj9DBtQfynRl0d8QZNm8RZyxn8wWp2TIv81Ycsrh9d/p6NP/P8oFm34+\nHuzCYQWRNEB/wwJwnr8V1+BE6rWKWc9H/6fW/LyhfLZ6XEQbOblh51tc31svgKjFAm33grHInWBR\ne1pZOl9nK55/Tp15ms5YxZSoduJeANgyu2Ad3QppEUTyuAHtM97hyy1Jw8bPSFcIw1svJVYh6Z+0\nydVWcN8Tq7qGaqM0N+8igaRaqTn4cEdhYYsCkSq66D2ro5ccx56SgZgcj9FqMU4nglaQtfYRhyrO\n1Itum9kDZKkte4QyBIGNiG9GmHctmEcvk/EEEdf6o3VJVtrMIC97X5Ux2mSrJfZi1aAZWDYqb5vO\nm0g7YiH3MiMYquE6zpqBRHBbPl8aAIIw4jzqzgEFBUAfsuyKgO6qatshRQjjY5nPkasnojk225xw\nPV32pvEk6I+Rv1IRcPTkN991QkCmH4/mqjLWc2kMrxQAoV72rg5i4D5M4g3KNHGIRaDyLOE2sntq\nndc4qF+QDKCtsrkvC2CNZ6VK/WX3uHtxRf7U2HQ4oGUOY4rx4Yznr+Z6fAlB7MQF6IK8l+ohq/5D\nMzalV++5uYD8T4TOXnshZGhhZo3GQrF5R9TZhB6y4Pv9wuX9g6PEASADX9vnsVfIIImcvRI+fy8O\nDEYQsR3M6eabW+gYL2ka4Qkb1LMvT/sIGHlHAknvNqvgYTvN/QsonFOhcrMyQjEv95DmDcO9rqF0\nRIk1scdzoVyWc+EYl+fRV7RHWsBFdd4qesgt2sy6sMcwld7hZ6ZYKcyI4rCMwkuCf5ByY3g+x3mZ\nLLd/igEogE25XeovKNLaTNrbpM6ECvYUg1QC+lXWNLaVd+m3/rcb8GsNohTnjzN/LUZejeICEVJj\nDygEJdyrCAt7RrP/iXrMV1WaOTiajXSA9feFid73e1lhXrsjSuiHf0F/3hdxun9UHE6uJqTD/pcc\n8RubWdpQ2fy62NAT9xALTnoB8n/r91V626LSee5K93EgG4cgjQP/ItrQSV44DKywpCG00ZwKcRec\n2UlS1S8bPVE+m1+I+ul0eKoJhIh89D6fY23rAAbwHxf2AuC6C5syOvY0+NgrZ4N1bcaaCChP3JdK\nU/NZ5uhxsA5EIp+AJi6ezTsnDvhW+rT3p2JRcjQ58udrMZEn/0Ozoywq/VW/VuMvoALnmXNwoJMx\nSmGgnObnRz4qj52FdrbVwLM1D9p2HUs7r1DHs5+BhKLVj1M4Jp/kkapRH+e/2PTu2p6/y1iFTFWY\n+Uus/AoKlBH4YNK0MzzOzVTbI1XDz2aL3DVxNnVxMJhJ2Cgbl6XpcgAdL/Mo5AB3R/IhTLE9gSDr\nK47cYllMY3lsQwnYyJcVTAmGRm8yZmdBjvSvuMX0huh/WnciNxkTb/h791mVBxYFM5/5+V0niiwU\ndfUMUBWPv8cMY2XQzpHTrpia69xc6rs3qIzR5110rvVErroezdORbiM64TQ2GL3Eg7x02ysFZ5FS\nchfz91zMW97aa55nmhP/en9cSpWwhV1D0Nv/yhtTEek9Apac/dZXOIHZ6efnJKSiEVC7QxvnCyeN\na5YORKLMnHsOIcHiIRGRjLe2V0a8wYUe24WtyUbR4mZgdu0UvhHsa04pwEbXCrXRHKSmXfppZksI\n2ycuhUTzLBiPqJ01yJPQTbGy3YqO3jFb7vAyWouAAffCOH8rD3LK5TWHqU5N8oRmSucQlUZErlqm\np+8VhsJHlheyGHHXrpDWEi/6SLPyedRlWtBtKpOstpSfxz/yKCo07ZIxjktqsGRGugRqk0rnXSdr\nD6SfVkMsOaz8N+tgStVBa/f1NbCVbtsCnVb/9jGdzI40ts7OVYtgt5vBR6rAWq45bjH2yelSwc7r\nh/P2fUiIddlJ42brK/prVIULQG8LyYndrs8mW1KMvafgiYFZeEAec3iohKYRCByEuAWrCj0mnQey\nrK2AluuK0hoYk6wEO25L1jxhCbSKjW+kz6IcAbTVuvTnj+W3J+DTA/eAeZl3XdXT98i9GxfLawSh\nNubav28CHT83mXAr8pnb4hrRaaLWbbTZ1QxNOPYVsk1WS4haTMwXQ1UQ+ZaoJbLnXsE/8AV3J+QX\ncIEa8iv9Vf4r6ZagVPa+zmwsl1azpf12Ss4iWYUKJcW+7TzP4ZbYDYuBzYA2eJoKtlsk32DbQkQK\nKK3F52MBDSxbvhTE0WPF2GncyBKDKGhDloLDTHUgzkDVRH5CF+2GLq9cA0cGP0Ut+Kr9azYA2pkB\nwGhvG+dfTO8chdpdhQBHlKbMOfBCm9f0ECLwsdFb9X2vZj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HpCPMA4ViR5RsR\noFuwzAAW9lCpvad5pr7YmJoXihH/WbQTG03U91Hobf5AMM4S5+qEtzNvYdCTZlJ8LHvGa+BP2M2T\ny8fzwXFtAwixg0PLZ3HjrDHmWKHxhNxCKElCLQRPLgirW6hP3Zxi0fHZO/aqBlDfaQmT4U6gM5nj\n31forBNWMoAD/1WVUtvgcrvVZsKl8DpS1wkcKIisF0lFweW5+jI+w+drsy07uqRSEcLjn0VMXfjN\ntFHPLwFTuJMeVQBDs4zD3UWwDuLSg6Xb2nOHMbSso1Uj4Mw6xbFGLdGYdFJDtJp+4Dsz4vXg1HW4\nb2gpIS2e4M+pmKUnjLWXR4Rj6LCzWpm0WQqA1I+Hf1w0OKGEBHLnybvI7n7u+pANCTRy9PnjG2Ed\nzHnaMWcE2zHId28HvStUh3mMrOX+2BAhbFQ3frrY1aPhJ88+0OTuY1LWS1ASbLpY5gd2W8X9SXpw\nTrCSmEmncnQVry1cjBoq576HmMwNnsHVU4ByNVwsKjxblq3YuSTB9Kx1MGgDWeBfJKAEFzJg8dXm\nmiCPE21sUgzFo9217tm4/ckAHFsArBrb1yOpWws7hTyPiZug6lD61Ds2/jkRXE79RopGIPV3Uj/D\nQ6zzfz/HvFkCPj1wZaQD+UAGeUk9rc+M34qE6NyXyFvJXt1dgUCjjYOCZ2qRZCh6MMIy1AZMbG5G\n5Tltz3kdEucTK/jYYk2quJ/e2AlQT7PQ0gY3Zy6menmWfy0oZrZpdysINnk+mAfHxDP1P0MM+wUe\nwI3+06k6BEjqNtcSZEzjPfU+h11jxfHKLMQ9IcNw1h14ZhchnaJzJn59msHZ8gUquGjDA/i1ova1\nTMypCjsIqLRa1eTHsePzRpXHu8E2qCRfabRyutwdtswOAYIiT7YOXzHwdiVlYUB19SKGD2F2wZhD\nkCtkZ0AtlL2Kml+ldaVYXY1qiJsx+m8+i5tfdU07T4sRsd10ja2A70y8RpD8MwYrslZstu7MaOst\nzEB9TsVG09dilYZu3gVo6zZnh9bOArFTgubQ3kKxSYXpeMwRGqbnJutKZvyMz+iWVvjznAgsRgQi\nTh03QDz7+/28LOUY29Kbu0IquZ1/EMtHSU3JJDGMetcnehNspxEbjyxwYmJbGs1ZWXKfd94uavjp\n6o3nEgob3/yC83HneR20YLtmHtBZ7xsARQi9f904nGDlMD3JAeT10WBB6gffeWOLNTGlKBE8uQSF\noBaBCIt8jU8FhvI13EC1rO6GCFOijE4CId+opUVMuwLBqAdojJComy6BfNZjUgI5xLA/4vChNjCU\nK4UpNsGwhdCloXes74ouuua20ltOXcOXbYhnQ2vRi8P0DBNQM2M1FFroQHB8GE3cGnA4drLNQAfY\nsDJygWzaypfgAUqc/bZqJGr25J2vC/OmT5G1G18XZ9Z+l5k0ARAhWYP4PHYu7QHgV+CJub2YhOnA\nrwEV/RchxfzwnBo0Yk3kyNO6Z2fxF9cEJFZY2rei/mXz+RjvPuFBwLqK2cn7fs6gaL7jjbNFuIZQ\nsVBuQyEXvyFEnPIw+0faEHWy4QPWpitHoAVpjmoCDZnqKiACmMLXH8AgxkUGhv5ARyaTrrQO9OMk\nQtIoj6yuY5qlpux/L8FVEA4/gE8hIyd6VqT3DAgFTLHI3OXiOjziwWlROY+7v/ZIHv9kt39icFum\nphlAwY6+qihK/NmRBU2pTFOB3PMrg+uUet0uRelMt7OOdL37NuraoywRJyr60WJGLhBDUm09MDx9\nqNcXrYMUyoV+UXUJPAki/JrIEL0FeEQ8CpVE/zCrKYUmky7MmgWs47WC0FjEtgtjCpHikMnJJRyh\n80yFQucOngfnrPSYO227ia+hFvx/us04JdwYeFKqIni7HnazYB1GYNMCN0eI+U9F5GDLQE34E+Zn\nuJ2u9b+zYJ3UBjb4liH8uDj77tmlRVC5aPK7nMa8sehhxljk5sSq9hAJRM58giNUuMAPRzOqEYm3\nsLRXhY5tWVLLK1Jbvelxb6mNaHJx1J5Z6/mOPWrcSPO9H5lZszSFTHezykp0kdSTS0jbcLBixnaY\nah6h8uUAzsQTAR9fzTicDrRdBwRa3Gs3W3k7j1WmK07kREitagxIeLHJLQMivKiqJnctJBhkW/Cy\niY0c845TihXkhd9jo/vA4h4rRcrKAt3d82M3gbIbvYYElilpDQBuhrqTc6BL/V2eY3W87D7nKFJx\nhL9aC2NgoCQYGR5f9+oNJ/kFxMWRdKpRmxpulPdcz6yf/bof2Voj/2/CNO0onX4iZkMfKnxWd65m\n92SpHgD8C23K/ZCHTkSJoc1nIr2Q9m5xfBZFWcVPiIq9B9mfDLSY90YKQZCwqDGbBrA1kBR91qpF\nPHYgaXyPP6fs6M1rJ2uWnslu491P+ea40uazVezzuoBSNPANNiT8Wt8Dif5IXH1O5d8zuxj+yBqM\nXNGQ7CiTKhHuxWt+gmQwMrVUEI2QkrxA8lxmF4sXhfe6VSqGpHop6m1Qe4gX65cBzPmveh8tx4zM\nFeC5ciNG+C9JHBThTnG29vy6etjjqS2/xUwsFkE3McfI5OOC/UARWKe618mrbIHvf+364RT1wvHS\nOb8E37+Cxzs5eHCguvZowV/ffvzWA0TKZjcVfPc/TLvu8b2RY2k7VU6Xc5EEkBgEi3Tg1DP46Qaq\nxuBMoBBe5HCeW18YmBlrWb7PneNuTyx2ZVgMFmkFpP7HVzm6br8KmCW2ZFUbwre+eMiLvbXTGvWS\n9IxPR1TsoS13nPQ731+UMy0sa1dp00/PkgY/kkyylIYRIMjXDhJV4xyGSH7JWCTGflipAAQ/l8nC\nBaf9DrsEs2BMskrCukOMVW9z/qE6lxUcSBn9XZTvQBYSfMDIcxKdU/ZktvPKTrEUILgd00f6waS2\nsI+xckp/OgEDEnhr7jddNY8mn7I30KTIh7ZdW+sBBp5f+g/2pdiH6xAMSwqKOytdru5nRPJDsNQt\nN9oWAHx9ynY7Pn2Km8f+wI6XxEV5bGmXI+HMidUYVk3f060O9L5m9bq9ZLFEHQ6rgMN2T2cP+s8l\n7oByuOKvsmWWSjI2FxcnN6nP8+IB55SmNTpTAx3fvccGnAtOAdEeBPRcQBqhVxoK2Nbb1P1vKjAh\nkXIVH5woLLR8R6zHbmvWKWwSwiDzuNnGd5Erei/S0IXIpaNW/Xp+MYlgd+X4mLDmXLloa6Iqd//3\nTtrhXCZ5KSJe0H0eHi7aHWn0hN1/FRa0lI9EL8gScHao5UFrroxNXWR/11SCEgcmbRmbWy++TLHg\nzpfCM7s5h9KWAF+TRAafSiz/swg8AUHElr4OkUGfgVT9nb5bR/iMso9+1DjfmssnuRvmGXtIVMYD\naYHlbhAk3ZW+8Oz+tzRwfvE5bhcQc/JxM+Q+Az9+R0frWe5n456gNfwQPrR2ABVz3d1OCWZOdP8d\n+DYb2a5tcUYqSIO54FB/H/aVEsCFJK4lRuHeHmBNAx5srh5p5xhSViBYwXPMbG6H1cSdeJ4GctoT\nKg2T8QxWwcE3sOy0spjLQHg8+X0cZvsuwzDzpJ8zUEVSNYZd0xxdtqqFkGOrOHHRtCNczs5RBhui\nLwJWyrJ2rCwwXuxUn5tXEp+6q0SiEdJ8v8SoZmeTJ/dDudA8So6hvMcKZr6dfBiQPc9Y/QPSJ/zr\n8G+xMHWsRg3vCRH/PcwEbNb0iNuyfOw4jNAmQjYDqezY2I5GrBG499kkYUCQ26C78NhES+VEgrh2\ndUGOTFmDKbBrhZysLsYdpXWvGdfk2Zpqj7vQEQXOicZte0TDZO/cMbNAZqEmseDxIWKSRAZ4lnX7\nsQTxTJvrxsjb9tfTBGSMxmVlJOIsD2JKT/1GO8Uboq5Iw/7CQIkQwVqdt9y+jIb6iCSXGAmf//SO\n31RNL2Gu/onL+zVosoePLt6xpNAXRScx7YhSzyIMHxryCxYm2wOlLZrn2BQsdqma3Vu0oW+/c4mY\nEkEzjcV+ptzPEP7ls6gaGKdLbLSXMiADG8j8dvWs/7pFfIfW1nFHs61+siRI7JqVSAi6AS4Bh5fC\nM4D18FkzgYose9JBNRkDwqLudhJ7VkFOhDmM6ICBC5UwSQlFDqVLAEM0CUjOm7FIS8IBgu3bg75r\nNiXbuZoJYqlDnYTh3Ruas1Yfc4gDJ3zPXr1dPpb5vMLYfuuJKoGcgOnq8ndpvxUzKqiZDPdhLVTK\n0NzXeULmHT20p2L8jFBkN45ypPquaiAAvWO01rZTSxmrBPWIjfE33aKt0VPSHcJGO0lUYhy2n4CN\nurZfcErIW8Xlnt8xVo7icoadDC30lcyIl6DNNSy4ZrAnCXmYJRsCU9N0PkadywucDxnkRZcoIe5O\n9UW/kSLJ+18SU3v1mNkpAuNXLgyQHzFDpWeMcXfVRvtrsJcjln2N6w/qPob2177E/Sx6zNVpDKRF\nfDMC0J/SWbegTVdQkmjTlE8MYKLbLTas5atCQXdY5E5mqRLrNv2b7XEOqEAoz1X7b9mF53sz5Xj/\nqV5RGpm7+uGyNSd+912N4V6Xjm7jteOJdHEjMlgsdJenMAiBR8QujxTNiN/K0bLw7rEh1kTee6fZ\n2ekifzPjRA1TKU/ANX6W1fG9aKzqeI/cfJOEbIMTNbBymrupvFa5LHpCBM0VjadHMHED9U+lzM3n\nFC1/HOdBMxazNx00wECwMWAzgyTzCmpZzHz53P52ShTaleCB6OrsaYp7fIr1aWaGKNLBaPtZlR4U\nLCqoe1s7OrUjtDix6D1YHyn4RweSI8sHgyLbLrFTnx7WxIYlUKvaw7DFpu9ZL3gVg1HvMZrYZn0e\ngXkpPZiPuVbYzsPyllucmx2GWOXE5irTUxsuRy5gEtuESqemn5q49B/XsZX1eQYEqtEc+n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PNQqEo8oUXEFDJ8zWIlFi76LTbnLEZ7rlxagT5VDOr6ahvtgvENVujqDb13S/lQ1mLjy\nBBIMRwW40qjfBmn8l8nVAeAzVFjpuLtFrgcpA4tKEVPLOPC8EmkB5M7q3Nv8ls3Y886EjJAMp4xQ\nLoPTrOxT9IoMXXyiUdQ3vfVJHiprKCz2IwwBIONY9mweFtU3j+M+4lORJJpVzu1O/hw1hmz9rHEU\nPMyPIXGvAqguZ0EDYHrZtBlABh3lry++hiLkII12g37QBoPSqmmcjgUl0b8xQeZnhvONpBorgC47\nT9HEgsaphyMqCdyiJrUqIlMAmQRV769IajQiItZfS+JCKK6WEu4X4U7Z/gKm3QHLMRId1KXVKZ4a\nNMkEr8kOs8HdCHCmZRF2LE7iQ4LYT8RHUmtA5kaadjAsRUUC0WQL2crF8hAWElmApYruQNFDQ7nO\nlTPVPcZGmg4K43LVEJOCDnZpa0nQN2Sk6IyocLBL+ruydz3ROdkiCEoWRdMCdQoSjv7hzYRbFPGa\nh3IyEggU/KlffZ9hnWX/KGiZl9xGGitkq+I4vOmiXqfG/knWwpUKIitsgI9uSCFh1HZgpwgak8EW\nvrMQqw+8wH9cTnoMf8piwW/ze351TK9B69qXDyqjc6A/ADukZPFWAJsx+cDjN11xbUL3lgmEX4us\nZt27wg07AjROpueXXucQ2e5rdw3vypzauww2p+cZ0inMVJs7inKfTlSHvAQyaQHBSgqmRFFtH7sd\nC+FI7r04nJWi4OPLEvlixhOPRvIxccf80zsgyQr6mLU7joD9iDIAIBzxMlOvcVro6IlKqtWZ0K6J\nmd8XrmDrJ0M1A61TDwxnuG0PTS4PMj1Zqs/BzfwjpXfmxX3H+tp2+x2nOgirMOnQn+vMMn61t+1b\nZr4JOiKNlo9WVg4lgtfFhMGcSx6CKEvGfofvBhM7Az0Cd8BZ410gRcLgULE9lZuuA0wa4zfSoBlk\n/1UVLOZpJPZ5/GNz/7j7PZp/7cL5BBnxBIFRdiEGhgKutLisjXa4U1k3BnVk1ISMxLeuHqAsGWo2\nPd4C23dalFD5wQJVswelxN6hZzuTY07os5HuGa3WLWHcjrBul2Pt9WrGCEtTIR3Yv+Nd1SOcuaLo\nCzlCEH5k1pP0RQDNBX/DALvL22LpWXVdxz1Iwkd7KYy7nObu2gcWfLJxfTcyHWWMCDqJEAsx9LoA\nkmub051WPTyklUKwVS8/LgW2uvCAPZ0JeNpo2RWql+yR83hxO2xmylK31gEO129XVJVG1rsEUMd/\nb8Cz3P2zzoaUKZ8R3xpR9AoljDpl+7t9Dz3Jx3Vr4kFx6VeL86nj0O+kieVRCiVx73Y/3ZBdMW5F\nMAq5rbnr5ZrK3+qCbv9ydb2zuuISx6m/tQfo7E+u6m83HEJhySjnCkzGZg+giqtcizXYeAfsgtjK\niQKYmh6Lo6ZP48SJtT2zpS3HSVrQM/RC9a1kvgph9y3P6FfalJ6SG6HaY/07OfOmv4/TJ6wpS1I9\ng75y0XWk3Cdjd/9Y5tybxT32qimQrCG5zl/B+SAkSkGUkgMxNqkNaE6wM5UZYoRLI9WRyEvzmr5g\nMbcAnWwFuPlacvkAv9YXqAeNSER/IB+DqslC2XGu+abPrA8Tpk6G9aHbYtupt3fOzaZZLppPTf0/\nRm5KsOEqBdi4sz7PZmx4dmnuRRjAtWNLtZsFNyQgfn9PMtSX5Vajn2FhblV+/7mkN+Abjhp5FOXn\n3tUNPPaVaBzazWMMOogM//zSmJbY8HqgM+xOSglTF7NunV2Pe1XVuaIVQOD7Wu7LpoEnkSHloKWS\nAIocMPH3E8bT8PsrolcKxeEZtfBfaM2YQ3FoPrW+XAJqKKd/Y/ZB8FxgWr1jI4BRYICXYWrN4dAo\n1QYUBfVklMsihy3a49hr6/rzhfOu/Y+4i935c9attvz1xCXxIve8XQCSfhQCUOVD3LKeJeIzuvWE\nhgTFOqc8gRyXCUsdXXidvRK34Chd6w09BnnutLbmfnWlwI9D71WG1YTL72oigyAasN18u27Ky8TH\ngs7YU/HQrU7HpTlDOFrL1ge70W5si6+oN3ErRxIBZBrp7NSy7ZP9NQOZjN+mn0mP+pg7GkDajhBJ\naAVWNX4kPlOBRk80QZjMnM/KdGms/90iWyKs0Pgc8bEFjzNWl3s6gYKRraUjMMbcmXcWJf0Py5zT\n29nATZ8nJhiFgCXgVThWsypsxaLGTlPqW1m9RC7o+ODJEjAwCpJB1+OsP39Y2sutycZs19EkJ3UG\nGJ+GaRLnTERA3Ny2tls1GKOMMXLI53kfXt7xT3gsmPmBlUOaQmyfx38vPx3kziRAupY7DKUHUTxu\nXpzkPcErpJNU8L5gmknESGjsepFkGk9PWEtarTPqMpEGk6dPXBPn88PfiH3Gy0wEEhlrRAUhdmC1\n3SLtieV0BDTSxVKJFG+NG1cM8YQG5IeKvOq7yGZTNN447SWKpr6YBxPdQD2ADlASQpOP03//a6ap\n1qgxyVVQlmCdXBT3fXOgcuR0JipTepksLAZhHnBsXbMP+3zzaZN+zZAh6Ti5eJSWutZ5WgTXdzqD\niFyNAdZhQBvFtgYAebtFg1WibXrK+GLLbwqqgp1q1OjVFvX4LoqkGG1IzAqVPPV9ZrB+Zesd+BSk\nEd9Wng22c4ociqUEdvUflkAjGSJrrbDlst6azSqK2i28IMFU/JG4cHPnk4xz9AJA+Y3F41LcrTZ0\nFRes6Bls/nnBUrvk69Bo8Ug/jWYhH4qbT9STELsavJFaiEbsPkVlB7kw142BYUB12ZxvOgkcmVnU\nCoL70NkdR581Z1rcdnE46yDSbvsHV0VXa3cmO2iAD3UPFsWzp3xHb/wL+UMFtCexGG/bpTbrPQnO\nNxVMvRJqgvSAyn/0ZywxvJnUPo9dxFxFa+kmzPQFpE1I4oMXjWJUBzc78si9ARuMIl9NDt+fLLFB\n/81hXs8hpJCK3L28WU/aVWn48iv4sfcXx4vjC0jdY3REjkwAhqB5hdWQZ1CUBMleMnfMqa3kAI3s\nX0JcDN9lnrqNjF7ILwAdkRyZHgLnYELU09FPH8u3HBM5RZUHmwxnndWb9NrVNMrDwV0xBf/j8RWn\naeunNB0//6J8JcxcmZ+6NOgr0L64SEA/aUXrHHi+d8lNrsCIInetcuoqBgAp+i4ULeHgMNizuEg4\n5VbrtkCdX0Qtpp7EcdNb1Nlq3+kezmna/O0JDazrxLyS6GeIMTKUJfLfwdg60zdvAcSXUTIYWz/m\nkvX97vi7Ypdo7V+JkOHCg0RbFCZtrO1KOiiHTaFtB5MbCcw0xacnA3Ge4+M+6K3P/r/lw7joU7LH\n8/NrWFZ4HFs0e0zV2M41g2TSiCfmvB5sEn+uQcSTRpbNhqoSGCOSXD5aDNUKHWlEllfPic8+/j+k\nnNXSwP7ZxIC3LofOBHTZG/JXn36TZa46mz5PA3KO/8rhHfVHvmJYYreKE5WeE2Ts7GbJf5aOMD90\nvDu5v44RGk5bUt/cKrAhN8PJGOsiZ5t+HdT73Ez5l2lA+GW/Oygsm7o8d8bgpRHhJSraM/Up8ZNR\nYWGwZRk/tv+w8qRhChcMjBirb6iMWtRmcwOinpTKOKY/zAx8qN0xtzpxDf+dYeMjbz94Dagtwkm7\n+2pN6UGLQoD7E7+wcrBZgfW8BbdRRklrkKuW+AgJeanttmP8Kod2hibSco3hDQCc+inzy5cRuWQ1\nicTKItNXWWycfVSH007qUf5QGZiz/MGogGE93bpsE37NOoCenZTJAOSsUPGKTuf+UrNG+0ENQvx3\nFYhkBy97IRee+4P2AgB9lRE7/AFiWbhnDMXiSstWAD3uiFHUD1YACZSCGDJ73+FHUC6ScyxhWfly\nPAdaV2ItcQkWR25DREbPaZNmXNrTQ42uobZtxaEefI+GoqCB2qzKrc/IeaZYrY1mNfP98N1FRNyY\nDJiYUPXILHbZ6GJkRDWSFseriCQM/nhxumZiGo1P/lg3d8LIV8IRb6KR9ie9XNIWruIKIhh6NCox\noREQI6sZWZsyIx5POKet/WkDbK9q4hakOE92urcJz4eOQm+TzQa5eTJOXXyW2GVT1jfMFgwN16il\nIUMi4JQ3JQP153fkoPINVqvVYzIvPKgzmhI4YYFo8dBFVYEuZZWY9aJ2nzDI8ONkWGTeDG16eNwQ\n3j/4PJeVFbTw5/sHXp1gNeAyWYs0fhV/h8GLievgiAtgELqbkUoY2dKEmYIT68GyUUA9BtUP2Z03\nPY0NKRhAt+rurf5FADkm+O8GI/V60eAarntVyC380iMN9zI+kYFROYlkevVA5rXv6EEc24foPSZV\naXrY0Bzqr/zDbBUeTfR2dmJdjfsUkgb/orm2aO4sFItW0v4VbxE3n+NYmspBJH0hDSdN7ESzofGC\n1hjpUYS6IR7pPPx7C4WUJFefSMqkT9T1QQgkUuLnS8HCAoHjrdVlZJ0YJmeiIOR+tGW4XhRdAlSN\nnXhz4IVzGfph6l7JoXERMa9QouzLKbPlMbHSA5hzpAaxlK76Tqk955/C8cv9Wbtf4Q9DzLcOKx8a\nOuuQiqskjs3nK/CEQCTtK9A048cKIuqEKwejUikyW50PzHrrBwMNXw/ecEHcvxF7oV3LjCjnZHpb\nRDoPq6UmQ1144QUtbEQntJm+YlUr49lQcRZEAtxtaadIlmGyJ9yJWSnPL4ii+MmRVHDAySFoIij8\nkb3YfysQbdaTU8MlpgB/w7vL+pN1cgchFvfxRivbt6hcDhw/R33DXPcWUlZWjI69t8vyWRUOyJm0\n2uonAPHSj7+7kY/1JrpIzqojQVbntkvFq/OFo01xrHmtS0w3m4nm3asIkAtUoFBNFnBwMKb9N1lM\nDTSbqyMfh3QS5YfOJV4QFEiSmFqVp2qDfxtLXq0UYqjnGmVm5MtoqzPvuAbYtwijELbd38NeBxri\nm5x2WiLjeknIL+hdlHwAd+NUFRQD7VRGtvJiZj/W17RowIQHwojd7HQ7GmJViyVipA6v3pEmEL8J\nnsfrpvdjJijwloTnrWDbFOfOO3led8+NccOaBbiLZJKND67gt/a4imKQS3DR6a444HvbimGs0pZN\nBDvoorMh9hV66S05gBK9lz5vwEW+fj1ZVdDyMbW0o+Jazm2cK+8yCOCpA9qSaf9c5ho4eWpfZwAz\nEoesjoT/mKhvty9M+Rgtj4nrAVxKuOv/78tcB0od+hdDL6oeMoSvmaP7O/ONGC5sOulX5AkRUud5\n4H0+6afYpCVXGjI3dnserM4CSsbvyNZuvx0pJD1/p0UH0rWGlNpJdt9L1GgeuV4WWvWsz6wDf0Fx\n7P1nv9IPwUPzaC3pwUdSisyay+x55Z8Y1P3SuKQ9YRmjTZ5y4fd/SvMTBojW1bkfUjbEc4HteY5h\nq6VO7LIT7peRjpabzciLMDjx37wE47y5ZVdPhinSkii617K4weT775/ErpjsJfgpU/coe7UJGy1M\nRqZ6RsmY9zGLraPgQ2+ItlqSS3+317B5Z3kzZeUr9ZH0gmiGdYrZjZWO5dQ8VeKWz3GaPF53lbAI\nTG3DYAX2tK57sSKOTRR9ILc/qLH0iqSzgzo89RUt2yRw1dBurFWgKMLvFAxDN94zwf1AqH3or4dl\n8gN7doKqxneS2cd9g5C9VKrO+Zj9DotG4jCN2o9wuJuBmHEjQogtGbjtubC11bVFuoyPZP5OS5Fm\nkqAw+TXN2tigExBfjyziIqyD6FzT6dbm5L3R81AxBf/1HZMQTe0YiskTJfW8Odv0kbtCfUqqbz2S\n6Q9gowjDk6fEHnrNmymB/iJx8Zldcpxk0lUDdZ2CpGR+JBmdFk2BHevhQhdvD7pSswtSsKntzKN4\nLnFB4d5IpKY7bH4syKRPZ0tmjoK5khFC/SA2OA7szRnzkjml4FhwrVFpwdBy6V4yvcMr26f/SF9W\nzOYXIn7EN9RkzJ6Q2D2dyx+LkzoGp5Qq3gJSvVs6G9yqtji33JIto1mXkLGZgVhccPsyo6ORgapG\nhcyfs0XlWScEzrsInCCZSP0CU0/5x6AqxkZcdikYCRIXll2EBYi/ZOXW5Ld37YvjSXDMqtEN8X9z\nibNupzoDvPFE04pWhkQ3h2LPHZzMqkgpuff24zsa/Pc3/cYISmHFkCyF3XSXnpEOmxuAkztgm8kE\nrj4ljCgFqRMKo0upfGwGVT43QRf8jmxCL6tVqA8T1AU7K+CQ81h1LdW09fz1K3zwBwihPkEtrExa\nbDHjpaFDCfWW0JwXhquQsWNfgvwccx8EkKid71uczktDlIjGmTQ6lZyHWaaC7v4Mw6bQmdCXCdY3\nzlcZzWYE31scuSppX2jy8BKWGbcEsQhK45Z05F+7w4QwMCypvepuvh0T12XnmoXfhQUphO8WQ9eX\nMN+BaTJisEGW0JJ9K9CBvnDasiH0zUnsLm5N1LFWxQueMH6i0BkZKNmuagzAKzbtpmnn1HndZgHa\nUYxaO1xsPjaRSEpJTdmN4yrgW3IkD0WukgirEUAX5iIF0H9YOWzMVtSKeuPZTkoW6Tdq6Iv5Q1yt\nrnJXK2ZC8AQposeSD742Mq/14YmY7sfgwb3v1Jfiwugq8GIAIM0c6eOzbXk8EgHvzyvEZeu1FkM3\nsI/Dd4Ir2Wmxw2qeA1JPv3Vkw3H9kb337qQZioebWc/23IziCxcCkL64eDXSNa3bwUbVLT3Ho02K\noQ3gZx2CuTiweb+AyqFJY3W3t6PxoS8uoZ/hiygp4XhsUo64faGH6fzfLWm1V+pakXlK2Az3DnZV\nntnoWqH5wI9hm0cF9QG3FIB4pz8UV/FrzU2TkDsU3eECzXMFM8zqrygIqTTo1fncbvst3fBpabEA\nWS+oJUGzJDsYJLXI4a7nwxqoYHTz4ZJdGPB7iP/yxqXv1ORdV0+4en23KHi0sBOPKivpfOWkL536\nehHsxnRne6e3sjWg8pH+C1NsfzF6y5YmAFhDgzer6x3qiyGezGXP2p8EdACKJdfRRn/bmb/q7/sT\nhFStLgt7FiaTbXLQJrAo/Yo2a46Ibjnh0YJDiq00I50OxSTdRYpd4mSwrArgxD+1Vkio1JN5AJWh\nV71LYYN89PcnMaJxyBd1CGqWtOG4KW895ZWjQZRaB0t9nQLonL8H9bfapFvGsQH3H+Wvo/Q94mQf\nF3amAXzlmXedRDbyPOyzrTEFtjHqq2x/Bu4Asf03hDSwdMlcB4H+7FoiX9Y/9sfkaJ+ypA8iC7kD\nEmj3p6niWyY/+NjDts3m1lgoDqFYfUXf57KsBtyQuBzHpIsvRQzJo8lPEYeR/GAYsAstBkgQo+ix\nVsgCs9FlQwF4eKyDcIukgN7r2fQh0iV5qs0AptFkCI59ZFP7mZQsDM50/tl1KY/nfc2q1IWAhBQr\nls9TmflpaVttYSDHbr4I+8K3Wn0RVxdZoRfiG0nZeuxV3TcjHUJxnM6BjH5/GmDFBtaST2iVZZV5\n24E1/E5Cix5nOGAxzzch9j1LeBjiwtimFkslCtkH7jMnKq3/CGuX2x5oljvbxy9eDzHrXl/xerY5\nFAcCik8xAClMvT8mGBCvtsReKi4l6s43rewp/VdEnuFAq7auwtlRn+YlU1Rsfs5FbHkuuiiGspYG\n6u4Sz9djXvp/mMr2r9F+x1+cUpADjTVc3QYt6sIvH5tvZ0Q3j6T2pEdqrB7hDwSTOjIU9c/ETdJ/\nOz2lmzXFn0xovovdtfdZeGLWNRWkhvI0aCYPvqeFdGeTtP31Ixh2qsT1StcYdA9ncA7ELKJn98Ri\notZK+SsB7SCDgLjU3p8QRjY8rlhxGueL+dGqt1lXl/BNXEykyNcdvYG///KBcDB4dD6dw97c8lw0\naWeSbSYAFQtc8tFC8NmiVCBNZ1IaBgpH2WDynrQA6QeVa+4ebdA0N+dvtThJ2z+XpuHlruCi59gj\nfOYB43t8oWrJVkoL6tCqntCOyiMIV3CEmWoLNcKqjie9GxI1YikVl3UGyhQgabviq9bPttRrxfas\nFt5jqIxlQqNEiv1q6iaNI5g52OqbXgkRrU2fycX98BiZw0RzwZokqW6a3ALVZS33M48PLzjc/AKi\ngiXB3RLgL9RnuMXB8LJy+Vp5RTdaspODjyIMb1EfynJvAMOjQuAOTQP9x0MX2FtQXhVynzpwD/xe\nNaPz5Avb8oOUFxaN3grCnmuCdd7ntQ0Y0SLj85yoS6/kPq5MAU2wiQQNQGXW1GO0cA7ovi0TLyW6\nw4Qz1W/0kFHyEcDpK9TUYS4d9PWj165qLZJQ9Mkrj5yOmwmlbs14FprvEVSp5c/VDn2N1oTioTUM\nJqLjF5RBcEIxi4cZJl+Jm5Vjfx9btIQvUSHq8bgfbouhCMQU5X/hNau6wMSZBeL3hD4vMU69nsXI\n5l6ns6gEiZ51iKa0S/B4dmzqLj3XNtL2GrI8igJ+WlgBYgcI5D3uOKd2TXsRjP7ioIfA1NtrGsLg\n8ZdmsdOg/LAWVnMfHkYQcPxbaOPj8Irlx0R8LMpbaJg4pafeM/DE5+jIl451PfqhJudJM5nBxJVb\n7q/xgEAleFEZVDAjDGB70p5mEyCrS6iM+ntitc0RlIoAp3ZaFPZXcpnlyFVVTO8uivqQHDc8oYnV\n1TBXiHj9/fmu+Q3jDBx0yh2Pe4ZXUiiS3zurwZU4Tg/xFiDKdAlRV/r2e19GtkTDA7Gm38PxFqcL\nUtPqhgH7gYdEm34n0BEpBL9mpIH9M/ze5wG+p6uUOyB8VtI6RzjEk0/FpTlBK2EGqLi3PpOWjzJl\nCEz2j7wLKyNfZMvghbyseao2zm3HR6XYEQ5VSTH+pbYLS7zP1UvHDbp54NR8SF73vPh0e4Q7PxTN\nnPnkOXhWu0/TbboTWG2cp70coyajkcM7aLDWdS3fRp4Rg0mU/gxQOA+UgohOUKdzvv1gvM5VQH1D\nTmk9s5or3i2lkPXrPDK5K/ObHLk9mjVvPJYjJRnC+HTeQbFY5QCYVCzAOkxQtMK7xEgDomOUhsqi\njRssN3ul9WuR9wYAYY2ksPtv74P/jdr0875hcbqZS4T9SLi6zFEwAjs9FQcF+YGdHqPmJ5FW6JcB\npfOxdCtWwJoYYv0CgSSOTgM+Usn0y39ngYqmKs4W8/Rv7yLl+NL7NHZje9ONaml/VMxOWiGsCmIp\n2EGu/50bkzkZlMHRGZqZNlvV1TgRAnJRrRlVSISM+94k7xmxyiQMtqXLvSw7YxH5hqgUOjpreGvt\nd3HpiQR0R/8VHHEZPu0GHly27uj/jDWLLLmcDfwWCfqdQyMrjWgvTxqQzJ7rFwM3yfUpcb5ls5nm\n+4VvQOMvwGe0TIIf9M5sm4DzxiWxobCwEjPGCldfGeP37EkoV+PtmEsO0t/lQEJm5M1DTVOHrndB\nymJd+KCJnEQx8SET0Fg+LCCQhjcSsi48Pce5NdgqsVP0DZHMIWEJeFIlBU/v96xi73kqIicuBr5p\ni6dXkutYnE+4piUqZ6dA4kDRMpn+EkDnXeeU4Ms5Ge7Pr1fdbzYeGSW3B1zk/Y48WCOJiwx3o6OM\nLDf9Iono4RtkFgABuRGCaBUYYZ4OsgUZJsRHSGCHriRzygdTCh13T6Uu9e0t/lWnj6d59oUpbmR0\nKgS9YCnnXro3B82uVNUv3/y1ibUVvgkHsU5Qb3Ygn5G2zV0AsDHC/Wt93b7pwfDFyxCg22q154tX\nwuIF9lACg37K7b8KWl05e51g3TGMiQwvU+f0lKzcSzb0kJtMPCht/85QSRcP/IAwF0/NxAYthzUN\n6bVlrCWZjJvB43mDaTXRg5zUSmGGPJYI13zGn2gMvtgLtuAucpHWyg9SACCYusOQbhPKQgDdNMis\nbFjBvXSuu3SSEOEck59ftXgQIE2q7kPi5vKtdXJjJ8TWKIPOcFXicM1b0cLB4D+WDht7ikIkwfep\nOXtO7sUxf0JlU5Xs2uqFFB+tqGI3ZXpyH7wQ9KBciL1vT/XzCL8ibbULr3LzL4cJoK4E5NjSpr9g\nP6ppKkvKu0AlKfYsFv/oj147IvrzdkbGqr+9n3JHMBfU23kCQxjU4cIM+6PsaGPWbFcefXlFd9Tw\nRJE5lv6D+FzwiH9PIrlVMKhFSsROJGMOjX/JkBYrrPl9XbyGW1U6MAD5cq84MoqaBbyEtV31HIum\nBIo1P60Wz+eC6narO7p9pLihkkuTQtPiTSRd5odedWZcRTzhWKqkFC8eW4I55B4JySrIWR6C9zYU\n2KQxQgx6OC1DA4WMLVlj7MpCyZDGKwv0TGR4mg0GYSgWJklGWt8Wvj66y/8i21U5yh+85t5D8+wH\nYIj6l+4MUhuG04AbrXVSx+EekVlGkBvYGF9knStNeBGO/KfnePKkwA9tB4Fb5uP1cqpAc04ilHC3\nJigxP/qJrwvOqoHnAs+QC02jfnTh9qVjL5pniXJ/q86Q6x8oTTtb2NFvIvu2C8MZhfdhoZQ7NHa4\nUGH8pnuPH8OLtPQEpqHyUHOfjixYIF4Cu6WxDmYIxbS/tQQqijm0weOgStvvJQTX7dHMclS1SIVZ\nlldE/QzdhOMoPlxGlh0uQ+AwXAjGV0zfYiiygQ9EwpWo9C+zWJrscqO5Ny5yEF4sAdrmLrCwqcTw\npzZ11k80e49Trhk8/fniJ2d+IjVoDSPBzp0NUlCWBgAFhcxItCNdBx/63c8dRgaSY++FrEQc2dsK\nzh6qaVHLDpHMhhyJNr5nZcTUW8de5jQnWyGM0RaIcpDPs2bspemIQwJr6LDWprZDzRECfDJ+gsr/\nTyHRsMD4g9KbxeK7+o3pfSh+wzqIUVvc/qllqYO7nBm1cYWIQiP1qCK68EOnb/UBhtjhPb9qZHJv\nGTPaFx+SuXlU63pIuRplrOBD22VDpYSeRdr4FjujnNHt99z5iXBf4SZMvcq3oCiKRo1ggJ1AQ3Ot\nD3Pfd6HI2R1BvxI9XXqlof7l3WLiWM4XJ9Jx8MExQR7W19HUnvXZmG/3DmpUPoxNfgnonu8urJPx\nysEjIAYyWXQwTunu/xD7chYkcZEcz2K96L0NU+01vXWihfp7LZ2RzGUrcFuGZ185R1xYUh8ZhmGH\n0Q8jQLcCDkOkvu7y1NUYm3tIdvTWEW/1xYIJo+NR++unpmrxfKtihANh9ImDzeRHyypcbu3c2uAh\nXYrRAhyn63AZlxD6HqIBs2rQ6PIXPiDQWEm+dqYnCPI8sAX3KVfaHTnjVGfE30jj/xyroDQvgx0k\nFkh72sdxoEQELNJLHOABY4xcLdklvgUd9pm4Lv/RYuSy5gD4ZuzEF35YpU4OHNdbhinN0WEg1B8c\nSv0LQBaqTlk5LrmgiNIF/l5dLY7LMSU3tjRlhttAMD08Nqp6WFttB7QpgyaBgc+Ue/l4WmHmUWlH\nI4oXogRYKAV5FXi5r4TxTFrOJrAYiOx4n3ZQfxhtCchifWgrBue5gUHcEqfxrvNM7+231v/mmWtk\npKWgBWrd/iETtwtnWnbWOv1rqL+OHVPffx2VUuwLnA31VsLWeTR9+1LvJsK334HIwGaesBZZd0HK\nwSoHh7ZLMcmTEvFZYPzpTLOIxR7txf7ptPS6gGMnnA+kZylxMZxdtTqtWvyEs4FBVl73VQ5RcdtZ\nSsckIYkdETRTemYbvUZWvU/juTw2sjHArK/41R2m1YVRNWlbL/iu5epNWnyendyThiokGQ9iWUdQ\nu283FK8cXLXChMSIVnC1V1qBpWpGne0cl6EVTo5RQuYB8MCFTueypY+KlAGMBvrahSwgtq5Wu7ET\n3+iAhcO0B351v1MRXJAZxhi+1gkS2YVnpXX4c1lnwOEeudIWm9xYC8fy+SsjPpQ1Wio52xRJooo0\nwnv/9yP2cV9jxqUKtILS52u4PQiicZGb3rs/aIvIo2XXHl7bAaMZBwGhNNAxNy0F3RB4X9sxrTDh\nIoq/S7eYbsi8/1RsHWwppRM2Rp+rcWYgYOSk74Hdlgnb+OjpeCaxsxwWD77jhfpE3P7AIJ4GAUV8\n5iDaM+AW+u4lWpmPG8usTdaLCO4tcFGTEVztVZBTQlE69YZBWnMEYwL9O8VvFgmKyW0APoxLu3AD\nkyOU2maqudqORLGDgmeS/rayl6PllLhCTy5PLiRtLpJOuBp4NIGjUhdzjX2KUbTw+B15NhK7UYl+\nSpo7l1vOueGtgE0Au9IMCBVKnJ3gmJpaenr6Ip8kExglCssOXCfhkdpQuum+nOoqALodo6DCVhWG\nkA/zm8z4LTLIG1BpBWYWpdms4GlUjHZuU3vTLMMyayn6qQB43dub3VjNBCuY6gHodtmaNGCJGZfa\nTCBfTgVTXqLyaVYB/o1dpAxkDfNjCeGTVFKmxtdsOwd5IodV8PpilDdshGssF8e0G13qCDyJlAPo\nnah0fuv2ByxJdBaM3Fa2AXpMHGzy/e6RIeEvfpYrt4lSOGatnQCDORXnGMl625nhpsbkAGyCl/zB\nytE8GWQfggIcsLPF3J4Y3TjvsGG9zoAHmwdv3lvL4mxpcFFakp3OLWKDMWCGchZOw+V4JQJWUocv\nTBMhNJmqAMRH7kcKzdd5Ot46HQCrwNk7Lf6yHhCSmGUss46KooeAt/mqP/aFA3P6lshVBgXDC+2o\nZrG/QyoMorOwb/jzFbRGb+Bfu1AUftkKFvDR39vHIr4jCW+3EmQsYNDZ5Jooj2F3zywgu0UGrTrn\n9Umyztzb1fOHyKN4ci3BoC5IoQP8pMGw9njeTfuoxciep/1nkLwwnktcbY543M9tmYuq9hbYFyfo\nZU7A8yY7snnlOd7svGKK1C385Hu5aYRm7qZGIFtof1KhCPGHXCmH2uAT/uZH4/TjBlcfmDaFDG1g\nzT6bKTZj48rvTnLybO2H5PvO3eI5YG8vgcZtGjeQQt9Hm0ayGGVCpVpCDqfHr5v3wcxASxsn5dCv\nksXSo0ouatYIWUVn8vgC2hzp7bklMo/6jiVjNl5lvjIG3priA1heBzxdkb1PV/RQAuVBaJ9KSmCs\nZN/PUIQw6id5k0RB4W373FtnXYiMX3oWHvDUH/ij7iC3gTmISM9UzqFotFSEK4MYRc2UsVFlymyW\nBINJEtWij0Rxw6GHJ1TOnxF40e6LxITSzzfBcQivZ4zbpTw/5Yw2IAm2uda4Os9UGMr1Nnbl84NH\n6jndCi3z9A8zf0EHAXfsmKg9ba93nRFXUrvGUaCAToMZo9qfA5Hyy8XT0aQ4y7FlkcRK1biCvaNt\nTdvpMf9SvYPXo2CiAlTH+xJ9DyOZZsKMmq3HfFPex6DL5401pC1fBjP2VHrLZrx1LZHOBKAg1Hhq\nnXpNc0IAqdEisr81LRDK9kugyPlcTQvaUnw6aYwXE8gQcXVkuO7uCS+iwXZaVa9k6XjifiUzz5FV\nVnMFXEfDDbHuvqHJQkb3Xrh1ufZ5uVJbyrpixMvVVTGvG0hfHMiiaS0Q7qPk/JD58xsAutbtx/U3\nautYW2tsU5fQCov6duYEnSKQxdOsF64tZ4vtsHtpMFWAY6rWNqltMT4gxJIIDe8oiA9t2PR+eX2b\ngiYejOxu91VNy4lai50xIK5gvIBrlUib0xMGaACvebKGpTO2u5ttyUzqNu8GrTfMHLoikJ4DHr9G\nK1pQ4RmIvpxUwi94t+lZ7iEk1UC5jlTLdwQ+jgHzbP0ZiL70touj2zQQguleg2/Ev1SMLCeHJ3eo\n4BxAsChHdWdbP/eU/5O4IhxTj9DOe69kK6nyLRU04wnLmR7S06K+w3gGg0crKSixtaVJHEh0o3rd\nw9mTSbNWmpyIbqRD0a68IeSsoObbjuDD+VX2xtT6tWiCQ6fr11kvMVsJubZc+/gFN9+fonKHbB6p\nL5Z5VFzdyEtEO0f3Q51wIbkJ1ISubMCjrOFhZPZiyCdxPyOzIMBRKkcgNK3ZBxjFfFjGkd5Kl0Ot\nnOghM2WM0af9+KteLl7zydTU9ZjcdA8FN8oq57ShlfCg/OHKmOkUpYRAw5TQS/2QRX1Gcc/Ugsof\nBkfSIWcazr7hdQV50u1B3R/LcsTYym27NqJmUJ03iF5jjhGxpJXxfIjgiR7R54Y7Jr0jGYWVGmze\n5znZSIwNMx3cGOs0TgztOYIEgcv2oaPeijCTMC0kE3vUuSkSPqgn4xixcyb7597s3KCNTkxrik39\nTHeD5A8Au/7F4txPDD4hSAyo1m3C6pLLC68Zkjak6fdjKaL5rqBLso3YyJ085ljnWThm/Qq6bTl0\nM8eiqYZHc3CGv4bGB9AdUrdH9Fvf19zw4c421m8nnbxrjJRaDF+B0mAg7E8z+0hotkxa2dMRbVhm\nauFUY0fyta1YtNs/jB84VXcuNU3OadWvQcuPASBSgmuNNDT+4r936lQSEzraH4l6UuxwdQoo+5yE\nSs94ZrFuv7yxZYkX1AjOyXNQMhRuUgaJ85xLBPR7Z3CaqFxQLBPpGtoskdWnGXFkAnhFiE2mihyU\ng8gkBEXx+A6NukZS3E2bbY/yD3n0aLaIKUdViV/WM6/7VdOFcy8q9SA0uRHfTFGRgs+LTjTLhaPV\nZ5wNkX/lxIIee09sOu996S6T7pPGUeeUbCL5kbZq61fbP+cjTUbFwanG0ciBRtPrCinMKDdzvSXR\nM47p3aunbUIE6Yyf49vVEEyzEyPPf21IbxVjP64MerB0CfEbGZ4u3RaoWKYFD+lHXospw4FMZL9a\nXoGWwhylKUHf+IgeQDIaOsyfCI6c17dMKF71G0maEpBBcfqjIHNH7P5Z69HSThbEhKdToJpew/8U\n1wUiqpEHfNK0sjeFM6Mq3GiDT1QVCrqD+1KotIfXyND6rlxB/r6lNUG12sHX35ORgMqzIreZ+cdH\nASby+cSVdkMItD2K2Hw+0wYAi/NzL2guzjCIr5zrQLNp4nsY6pGK+39Nskz55ZgTuGumjIe3mRdo\nvdjzpg3wEoA0VF02x/NQ3dhcKF02ZEngnRdkpjBFDQrZoWf9/yZ7UAWd451neQDimYqBzO4QAU0s\nF+CgqZqax5uW6XrvgCagPEctIW3NlzDWnhxNcRymmIMQdzfOEDuIhCnxCYRhjuS+SmK6JhSSR4aa\nMF17ogRz+PI8PmPGDlMEQWd4Z0K46aVjxDc/h4o49m4Z8nSLIWxFiNulJK3QfuknxsSOZA0OJN1N\nMZFC/OtaUlAjENfdkPAbHhUSdYlBzfjHHTGO8wvKvc7Lz/dVFcwadcDjnJbx0mnoDC/69gePou6t\nYV4Sn37rRbGGtXCqjh8QZCVxDSC4l4VVrrKxYWu7Jl6J/FVJ+DOWnYjjJ0JKU0eAx4QCemH6TXY+\nd2o39P63jY8l0a774GWYHnA5pibwK6OhEP4eoNlENsg/ShDpCK7wHDpA1sLtfN69qXFnZvTb2pCm\nLoWFimTRFJGCnSdOpBIW5IPcCY6f/AFJUk0s0AnBTb+1KSsxchhLoknGvMY22kmW09epDwz1BVP3\nPPYBXtAbUwsthtyusPWFKvhMxdplUZnxWwL7SrItLdTkwRwosCU13fpgS6xhBAzbeCqwpVvblg46\nCOh0wXgm7kbo4DSN+zNDet4bRsGryiM3oJGH4Cb30uO85E8L5ydL5U8GyKIkFATHeiWUFOWpsu5t\n4Q5OFMHZjL6wFXqJxEZBPuWaB4KewcrZV44KrlhKMJMr2C7xXJgodaozd5jPYRTe/LNSyZWw2elk\nX+peZMi3eMcM3Erj95ryYXhfJ3agF7CMKIDJg9If+7pnSXi2fEZCu/5pVL6SGy8GoDN8KFHYwPbN\nhE2A0/iE2yqW+DgyW5N0k9DdJW1cRU1N05Bk1xYklw/ZrX039RvVGHrDV/odQW0w/DH4RovIQHlq\n36M2+o7ucg4TqFXmZpyV646SiDKoBRZ4seAwH04T2Px6Jt1RlunpLJi1UERLqOhkqNMtsJ9E4KgL\ns6lzhBkH0gGnu3Q4NNfZCJRcTcglYMlH+XUTkXlvn9IQgyZG+pqiNiHSVentl4Edzv2hxks4/zu0\nOyTic6HoI2zN+aMheH8tFMeqGdlebMlUl8lgq/zX9Ei4woVSJ1YvuLyck06pykCuPRooRM7x2Boi\n4ADYJc2vOHul/ia8+ldBVm6PuS/hpthNYiCknllVSMK0VNKdIuSjoh4TjCvELhsWRu+oMl5hooLN\nn4bIxI/qLtu4jP8p62QdmM4tKMD6sYL0aXDTYHdziiuNBKGqN7PLfU1vk+6f21KTfQ9EwP8meVYB\nLP4rJOwTuyA1/r/x9Vbd2tWJhJfgOLXt33IaUlRevFWiK0aJgCAhRFRTgvuJ3l3oAxKrW8QZWL9Q\nM7keXeRg8PTNjLt5d0YqSIQLxBxZigwHpXBTfg27CZ/Ts7C+v8VNw+X0n/QrQTGXby2EZJQDdP3L\nkf9D78YuJyJGrggyzdqAYlEpNOG/g7v90wLeewKbD51lH02XE9HK1bsD2207nUOWOMcXJhdPrTBN\nFQQ/9W6mpjtde2AUUY86Ufuhz1bL34FKd5dS6QytgKKGCTwBwcKtL3KOugIG/lFQmgQ1FfLb4gUJ\n11sLSLRwPw3mU/sD59LdUPPsUvUI+Att5Ykifys1EunoQS4hSMqj+k9+iDx+aBEKUZWplQy6f6Ye\n0gFYPM0+ffLU7H6qjtwLkx4nSFGseDuvS2dHqwCYO4aFdUyzPjoKYRh6mNhyHUOevyFhpNpg83Gx\nhMGS1VoPQtFenpBZnTk5iL+a7IVzX7bxVCIT/gaTZaChDLvSEwKAiavVt+5+Wbr8HqoTJmmQbKeu\n6LI0hBCE39NaQMBQZpcEQY2aL0/h3fOyEZELJXZ0jX8KVpR/8fHxT1zKEkhqG+XkQCHZpP+BligP\nNeMpzqiZx0qRbUF8H5HDsgR/YwQ45TL8s1LbpocgyKWOm74XuOOgj0E80bysEIvk6oPvqyrH0gTU\n6ETpUz3/6XpR5YkNStPQ0eyPrj1Ujm2epbPvMUra5L4Ss9BwRPvPZINF+BshqJCa9Z1OhUdsoww1\nGQGlDsoBtKaY4E4Nw0dl19S28aB/rwf1bPEWZHhlPIrdbju06OVaRwMrIBRwGewVFZzPfRg8iQhG\nhXsO4sQ9Nk2a5hFFXaeVPH+BgwJbH5wCt/fOKsQ9Gg/7GYIAeyVOe3k8Y7oHpMBAjKJ+8WeEwHYl\niwbTUN7ffdlarsW8HSZhrVVF8B1sLdFOwjeWsKAKKEg9m6W41cqpr/CiPTQ2T/77DOOUDh0/Ioly\nGVcmJVHgDqNTBM4rJfbp9Toouh3xvtu0yhTidJhEOaS5BMOBZVv03Vx/9XSj2M7OduAAMV9GQeqC\not0OrDnXvV7fE5xiq0LlKAFPYXpuoXFBMHbohXLkQzw7VHOQNoLAChevj3lNI0cunfdsw/YD00OI\naShnPS5y2hslUiZHfT5C9I5sZ5tGmTm0m8ojy4jk9jtvhM3rREYQIJCpyuA1O6fekvDFUV1MULib\nr+9AQlVUtz50M8Y28htL+IL1/KPOJ/qcSx3StITwUJFf4F+bFJOJY5VRtwdVLi4+6NsUJoybOUKA\n4hO+StgoOYwsKwjbD8DSTsSBM+JBdfpGI3V/Lr1lu1WuAvD/hH75uCTcVYbuA/xS+QHgiqN+xT1m\n/2Yqrty3fCIH2Cn9TaLq8BhTiqW+sB8iBWFKelTti+LY8WapBP2G/XlINf3o8fJzLxWmX7P6/C0S\nwsJQe5+Bqx+WhvByrw3+Cx2PIbHO7fe6xyVTmsLs/MmfGTM6RlRdBUa9g3dLwatZwp/B7HzogVqV\nJkPglaJ6eujQH8AhZJ8L/KAbAAx/VD7FAYbbkc+hePZWRs94C/TXBNVRXC33wz8RC6hOeNwWRN+9\nOWGWL96dOSIWFnO7yYYI3H7Q011PluZrso4GAq/a5NUEYZJOyh4MDaDy9NcM7ka+D77kXf/s1j5M\nBfCiy0dtPoxNyPWjwJ2HFudDgGfCZ13VLPoiDZgfBWc18nHcDBlvK/ewfuNb0W3/K8gXN+iGTvt/\nn/WJCA6+IiFV4m6/TK4Kp8JUklpX/p08gkExKlCVhBsHooQg7ZCwmUD9gm5e+4PoekKmOfE714iV\nGLCtzwisCobaA/g4FpLPiz9CzQLpGb6FbuEim5WYEvtmZekMq3dowBacc7gDX3YiP7DmuvBsXADb\nIJDYVdNfRmRyUnL4hzIDtashTGu40+zI1onH4sh1Qj85wXDw426Z/SZdQTTlM8JXzjP5uoVG98Ij\nUQyQVugDGiRbuhxEOAcYEJn8GqOUIuveYwp7MlVtSrF7Fns50BR2G/XZumU37t5zZULUcVLaAPWr\nv7EmkblDllqxYRF68RrDNjyIOPKjNrBN5iTr6vBhl7ka8SZdHdAMxnMVb4/MSy0Lt19jxOpfUUWS\ng7rgYMvsMwNGkLtgu5Nc6S+imPFdi2ccRKeDYtwuSJnhnsCvma0LWxLxRZQpbCAf/bD6zlZKejEH\nHV8OA77o8WdCLmtRWFnuQVljwG+batqSxJFuP1xQses2advO4vZ0p7UwXbgI8oZAv2nZmxDA8qpW\npHooKsGvAOziB51vVl/Y3h4uvRtOJSRG2qxFaGLs8uwJrwtRonHTF2xRzBIohk4hQiLom8MPvmYP\nUiRR9lii65jFIUZm958RYZsgLUTDPEjl8RaLDvT2HvxHX1gr+/QmJb4MPF/aeIH6HGr2nrCqN9X/\nZnN5uuidWq8mNH/IEx9a5odqim4rUYwnAwbXnT8jCy1vDX32Mp2ovzk8bucvQhQkAcP+zj6lY65l\n5FWfM+kgzgNitDaYevrl90+s34bUXHO443gzN8CP+YyFrZm+tvyMrJ62Z0HpM6Znm8rDuMR0dIuo\nxF/WlTerQQmAIsOIW8J21+o+nJpPHWiJJ7TMi9qC2ksnrAPkDp03m8CvsXtOibQ0ziSvCskzLcWR\nX8TIiK33jHV37e2kNj6QUeqHKjkbAehY601TwCl+UqjkFfm3whAfAeHdVLAU8lHXL98m3+4rmTg7\nI7WoVJWx74R2KWzEfT2gptJNPNzLX+NGI5nWYEIMu3HIrzZ+d3GDnqJ4uBTvVkUUq4RWK9ztChqM\n7tPO8VsQDFbeO8LZte9qdodDY0SW/Jwd9Qo17UxMy7I81XtA8Fize4KylVxRlAazWYmwsQvdjIoN\nF8bHw1DpIvpWR6uWi3U6BY9mJD0H0Dmq1Rmvy2ByD+wL5ZE2w+H8xLDDrCGVn8V4mDiNYxvTBhiR\n/5/YaGraNluwdIyY6PLaBPnkzKuTAdRtpDyE16D+f4CsxpHe41QDsC2BRmUSs/vm7nRJ2VAiStEL\nsQpet6IrLnsE9MnvhtlMwjfz6zsEmI6xxE4PNxXeVWiiSEpKtif7qmllkUejg8CCFO4u6jFtKMqZ\nyZA+bBzIsfRfBo48aUhjVRSMTytxY6hvl14tSE2xLCVp6ROjr84ksxCj2a9IRVJoCAuhNRiwo0+T\nWdwyN2cthw++AdTlTBDJ7dNhVKBYT4MkBZ52GiH9e/X6pnZIP87SMGizWXZiHJWmT6u553VPp1DA\nXO41acwsQmlGu/sk+sb1bKstkcAERKIMpDqmldIv4L45Ft9LU05KuBj30YIEegquzBpnHpxZutOH\nIE+MX744YHxa3URCCRlo2lC7f75WFfy8kvBWGhZ3W/i+DtaY7f1M8TEwZiOvhK/LarQnl0r1jKgV\n7diut58yspZ/jPkn38/ESgXv/2IluvvHQ4ZlYHSt0bgmtJGean6AsEhQ7dmm1Y8A7FLy9rTSs/dl\npMO6tgljBzK8TdJZa0p2lkV0PgJ80g4HAv7/4IJQnXqYprkU6dRbcJSLiCEgC4Uv/t279w3t+ZRD\nUhQya5GZaXQPbWkINuUa4wiDz1Ji5bF+6s1NbhSNlgdEKLfcpErpRe2/FUran3EKTs5NIBiWCB1F\n0GbI3ua+msihXqIswvx0/xAM4OU+haOvWrcfgdwgE5w5H3c/RztLOVb8EEe7hN3GQtHUr2/xdkKU\naMcXNIZyDoIvBB/ca2v8o/VcZN8q1w1szW+c5iVe0HtlznmrhDdmtqdAHuuxMiw2QCyZ78AhVlMl\nZYSfsGd0+jS+wvYJdfwceLbXsvcNRAZewxYslnuqoTYK5aUyJmV9CUVDhgbiK7iBowJBTgORZQwn\nHHwDdWBQEHuLYR+kQZOSJwRDSC7beQxitrW5P/HReQgUHMAp/slLK9ceKgyOZct9nlcqN8x7QBg7\nI/Dju/993cDZ+QTnCQx8CKxtsigdk78ES91bOnyaOgDXkBVExnfjgmARKi70XgZtFi2EwoCKWRxP\ny2SVE73GKT+ESTZgJ+u/MKwi4E3+nXklahsqKcmv/83fWPII+VwAwd58YyZsSNJbu9d8fOCkQWkH\nK2822uzFDwWrI36QI/m2Q1/Nht/O6PYQ6L0iXWWZ5It7531YYHjD+1VofGAIHuv+LHhQRyFXLEY8\nErx7qML+dkOkzZ96yhyfIPeWh7rKgp6uf1HxBRbXzspGa18EqOCWJvylchiit8H4mGTvofbfxgMu\nzsLY8gS5u47kfTpXRu7ATqmcyJD7XejwAe6RJM43W3/o/CPf8juhDk1RRyC9kmjctjIGsMeI+pas\nreayYzX3vmPF60axMrDXArs4md+HZywq/vX8YDp4YnLhip0BFAgkuxW32TYAj5XSA/Ob4VB578q1\nsjvIZxxXYOoW28rs56XWz3YGqEeOOej/E0seOfdxlgYGbVogHoepp4riiSzrfjWQOvKbZDGSUprK\nN58GqkyetwCBysEKXgGLXjjXaLN71/TKRxmXfC5ohHwEqwhFY7NdAIp+Eyzfv7lFG3RBGarKdpEm\n9BRUKwap8N6E8/0KuCpxzgoBtGK/+5HPPYaZ8TRnR/laIhplbBbR1BNDEHzNK4+YmWwEIvuHL8ZE\ngplstpk4KeK+fvHv+a47veO4kO0OaqQ4ih8wQbEQTnandzkEfPkN+UfEXya2ZGD2PhoT+YJ88Iao\n40LemCkvWft0GyhvgTgcEmBD42ubuFv2ZzEXwjOLfDOAyr5EUHpRDSvKkp8ya8n95BFaEGTrN/Nz\n8Q/pNydqsohKQ0chmRiYtuIXZHbSTVpd7Uvu1bszqtR4TxOOez1z1SyZ2P8hc9BkDzQCU1vx9cZk\nXUQ3yozk5E2QlpviGUc3Q7IY5yuxk+glPbHnZ5zKyITYs8BqYd1+I+Gju0cydpqWnJhBJ6oYSEPh\n7KesrXtFDyhuSvztJa4AT+gW68fmdBzG1rSR5vbkkY97+aC5fV1m0UK1gGLRQZUgpbUW5VxPIjit\nZAm8CoodmKrsS9h3+JejYkrFi64l0USfAUXvg6Ejy/Y05Gekzjldj+S6uRPTjZSazIRdnLUY+XMU\nqw6WDWF5/9Fy182XPWEVK32k8Etlmq1bAGjzHIsxDwt9WOO1NQ9CWdjak8LpJmGm7rEtgY6IQSk1\n2J/vzHPUEQZ7czvEdVK2w0IAquD6KrrbyhbRbgfSEDa4abIR5XlIPOOQAEO33g90xw8y1uufLMz4\nTlBOpjWjM0ubrvAD5QKrlnL+PTbx0W01dHgVwwdM/WqQXgdoKbQ+L0kYh9POHn3b1xINBxwMgfSW\n2XyPbys8rF/p1hwYQL20xSF5ZRE0Luz5VQEFq3jDJkvErbIg/z8VxCesKgOLrtX2COU8srpSaoea\nBHJy4RbE8uPd/CKEudo7+AAbbM+QvQ7gFS6zkU9HyOcVrMMyushpSEnnO+jgXb/BEnZhyH1mc8sf\n3qSb6iaE4ZxT57Kr1sx6lB0hGsGEFNQO154es09mh1Lg9G4sSW0tONjQyoOB1B8nan5RHEvfWExn\nRmReaXoQ2AfmV5wBffzstaIoElai1SU9Z2lGmNeMHvF4AfiYWA2sat07HtPbPi/p7x3uesRhvIGC\n82KwMLrvp5R0Z3MWRPeqmQ1uuFaRHYXowLA3Dkwla/andsDXThfKAcvue1kG//exC5BNNG9kd6mk\ndv4ahh0kn92E8TicFn4R9gn+i82c2Y5c0hr5FIHsQRbajlI+diVEbhL30auJIq7+OaL4MZWcIw16\nNic6VaCbEK4twAuQa0Z2gSjh3isZm9kqVIaJAIkIE3jjhOH+cq/TOtylMTU9OMwt3wJa7b8Zj4Vb\nPQ9Eiz8leQlcx/65aDWIhO3Sg4XDaCuXEgJBs7WtvcQt5O91djs2lGr7QgYnvQgADFDHuyDnRBLm\n9qfjHg/06fTOPwT/SNTqrIU+kKZRIBrwfqeggNNapYOs9xrSxPNY+OiQ9/Yk+pc43z5ePl1F44dR\nB1yrXSh+z1di5CIQsT6tETIW1jJWnKW0+IVMmV37gswSbPldR52pi8He8252T+w1YnCGJKNk6YXR\nuhbOPrTooSJR2TnsDV4LNK6wTi0tPIAYwWlRgIC+MfquxT+XPhCEUCpKfs3I1ZimijGqDYHrNrDS\nzQDgK38Ql0JthsBV0PDVSBVdqrYajJCN8K/U3AqZ//FJtaGh9KIHyUtn6GROAjTchosdWlABTVI3\nx219wVtQPDaHNnwG6WoPYo5KRGLSNz/EHaIcc0bK6r1us5q8LSR0umk/D+hoN9om17ALG9DvE37x\nejMRnvSc5dAqy0etcvqPA7NDNVX7kNrwJJ5FbE40bp+TAt2ar8o5z0mZ7eLBxwdZov6LpuzPAgIV\n3SJqFzc5rZ4SuVYwQF5Euv3psGTSLEHBKSXUSOj/2yf6xd32BZ4RYi83sIpT7eCZ89a9HQwhJNz9\n8EMA1hY4GHydlkLx6/e9Cq6tqOYuYe5qFWh4EcbD6kQxbzz8BXw/mvKJAfq38Oie0t0I5LRVmKQk\nOYWihfXanIAjCGNbRNEClxOuvM2tXmJJk2KcjEG/kEmzX3CHKOAJoVDNV8v/yuhVO/C4Lajckcb5\n/swcoxNoZVjhZijZjooP7UKZDOSl+bDBy5NP+DWetcbBi2QGeAFAHmJuDI6tQTpJ1F/hHpP2ylfZ\n+3MeGlbkO3Rue1D6rFgTOqtkHbcPUhkOHMaVyfltgtDNhFpgKrK3bPxw4grHQ1PH3mOR+WbFWN42\nuXurkbKnAUqBVL0+EtM6zfEZBmbMLLdaR21ZRbKSc9FON4aRm+T5CdXmqlOxLT8vBQN5NQyN9R6F\nlpqHheyFFqUaeMUtRCJgg5S3Qb4pYFRZc5sK7lS0tlHmxNQ9MrYoYnBL1O6OrD52j1yqpvJgCQbG\nHI4Z73a2JNlKzu6txh8L1t7EpOpbMyYQijN7AGpZRMOzlVTaoFEet1SO157Wr0xx1QQcDSF5xLvY\nYE35m/9mpmskp6pEbLo3fcUl97udr2oD6Jv8aB3S7+a4i9T6JsfdpIzFydnkFRLKodh4VfRZz4tV\nNdw+dri+Wp30lU8TsrOoKlBVLJMIGySicpwDB30DmCHSn6n7CsZcXw1DBaERgJ8U4X2I+9CyuyjD\n5lFgOR/7aMjz94bGburLb/kPC4w/HO3ryzzKK5MGXDWMY+1eWJ3ccS26zrmD0qD8dD+eFRQxyq/O\n7ksEqOIJPhIDrT2uBRqbQlAUznPnx5084nPJLaMob/EGPLg3f2eo7sN4HhZFu2pE0xbLSB6wYxjU\nPrGsVTpsxCC13EKC603IsJsjev0acSaO4VNalEy3N/GP0TN7ASZxF5eZaZz+QtoFX+br8UxR5tSI\nGOwJgzB16XMiIfeMz1c+hp6J35jTervCLkuGV4Fl7EA6rSgiY3Ex5dK8vJ9zJCy7U3zn+OiXhUqB\nC2fRKXxUDjdspS1hzl/W2gDJx0nq+UllM4nMgklVYTan+GqhfVt3i8Xc4mBqZDqws5WJsU/Q+GbK\nod+8AwniwuplHmHReL5hatzkunCZ+2M3s2x7jyIvVHDwGW1m8/NYgpu0WFr7T/4daJ0YU4S4efe7\no97Qs6d1yf04MwzBuW2UkPh6LFczvWB3Gl5nGnjQPa1ZHVn5GO+EY7VCdXmsxRxrcNDf6/ncpibA\nEepR2k1ewG+No1cZxjCKKTSux8ANusuulOBlUttpN8af5yJF3fqk+l29BWEgRS3ZUvy8odRUrWxp\nOCqKod3G94zJe8i2D+zANTNKUU8P/94tMzyKNKuahJFQxY8addUudNHW6Xfzz/8pCINP8gsrb8B7\n7gk+FnPhUUl7rT9Hm3UwYkl/3X+kBgnQQoYecPbn0NrvjnWVqdUc3Qf3Q6pFNl4HZyis/5OfgDEV\nUxfH/UZJa1AYCLXDKdEGVor/5OfzgbzppzzwpyEfKma36Snxug3VZQdX3lGvJKBV+KzuSlp9zqga\n2aQHpOZKyn29ydRWNa2pzUWyo4KdB/2LLU4cFnHHbTNsAcFhid7DEfYzUKxKj5FlDjvCmHZhcFWK\n/N83P1rOY5gMypjgn580qt7bel6RQYgVHDh4Z30ur8o/j2YrJ6NZduif89P59FJMILU7zCwh+aoN\n6oVeffUDUKaEUDyJj3tUJppvryZniroyqInKSR67MrlUZOCd2Wk+fygLuX9zG2MnSMGvJPk4BMGq\nDPtXqXftxmWrXK7n6SjCes0MfLsmuxeDasGmCrl1UejcEZIOI3k41NqXTFFDc3G2Y863CpaxuGS9\nDtCn1yJo6rUneKQVyKctxLjnb/Xf+9t6kr2baEbSmzlcZAjXqPQZpuaORt32xCBQC+4vW/51M+TD\nMPE/X8nOxtAv6ACiJoLG9fmEOBYDra2veUYH3Ye29py7H7NOPhwlvO/j1Cd3AByhUeJzgg40t0Wc\ngdKQfwuYtfZgGlUBPm1GXm7Y/A4j030GC9oe1Ti6eWdmXFLt1QbH0irYOI96MU1TL2029UNUUaWp\nYth5HvJicUNPAAKaxxG0kXFbgPAhpmng9F1XO0QZGBgsEV6uce9cfSVjDXwSpGOAbf4YLSG6FMgo\nbZGbc9or5vjyfBGQud4A/fW/I1OEebM8dCUp99Dr8pFm9SJYkdgo93kMV+826g7+h3Q+VlRX/xnk\nyJc/Clbut6CD/qqSKA9XBvs6AFzjjwRj0RYzZ+XYmuXsv06P7vjXvws93l3i3PLOV+xZ9EeT5KyL\n7G7gJaOFk5zAsbfa4bC+EkkRw7t5rY6XtMjUeCzsu2MoGzCrrpYT5kN6sfpOJC7ZJigDAXypc4Zc\npSf+l5vTXhcINu8hkI9yei5DL7H52mhC4EMXUFhl+VBPOQ2eT3OlsVV+L+UFBQzcbVp8YStXAQNT\nruk2ix0rcUh7uDrJTFlebxnXERnuG7HJa73bVHNnsYmo/rmkgeRimETPh/LezlH2CGNwcx/lB7Z8\nxE4w9KYuFtjLoughXz5nWrQCD1FCs9yBVFSn7DaG4/IDhWOURGznEPWCdNRDvot3sC8kMM/5O/4O\nuL1RoLJZdzj0j8NQklqO/LLoJ8DMwfESaIOo37rPDjCJu264P3sOR7zhrC0KfBG7U6BxgrJQRY++\nCn6bWa6EVsOYyNjOdsLTAfDv55dYyJHmkjYd2c8Xbhltx7zrjNsMVq4+c0dxZL91V/951Osnm5En\n32b2u224PKpmCtj9HeIg7YaDXQjpqbMP2hbNTF55ZDdpmtYOfsVz6bnCSYH4VlPtbkvQGy/MIjwq\naHdOipCb0uzDwLcZrgERwnxUXzPFx1v3pmyKrsMPjw502f31lCzO5Us4HQWvY1d/+7UyMpNZbh1v\nLf15b8eUueCuMUVngG3kAH32VsFPRRdpQgaTgapbtcYwi4Z9iWMIKrI45/x+ZzbqOoBcufPjeJmk\ny6cHPRHmDshWK8j1oWHoZHAuwvIKP8WPcfe6tgOZGWIbIoqcT/IYqZV7YRb1WOeTm+rzJuuzxtT3\nQLbY+SaG59YnVfhWMoq2RoJYahqT9MAzjRMiSGysfddCjy2spykva6DA/4phDv+rKJKU+B5kPPsE\n/A1HzCiBU98AiQvmNDixKhieBFEz4vbCpbTmI5voQZRl6u0jtiH8mhkitu5W/DpW6zGuvAc3tYnr\nhRraG4A1KcmKeWNUnaBrJOi8kuiVLf9o6IqCe+0/SFo7vTpIiRVR868EpdT9sg90Spl6BTs8v63x\n0Jw/XYtENHWR486TR7sxRgZ7GBWbyhrQz+rLPThdhNBNTuFW56Er0gMrKnKMSMEIwG8+3hEO7zXn\nr8GOiXyHlOMeag+Cftqh1MWXFJ8ZkAAJn2AuaehExwLCAsz6A56LIShbZShQSEyqdVtnyravRzOb\nwjfSQnpW/PNb5RvEg8C9BCULfip07RkjjvaFgmKrjGlK1cDfV/+5FKvLCOT+vb1RVO4wVy2mp539\nAE44EkQYWQtlV0RyywhmWaa2zaeqGHfm7Z9DzKVkjArRHwxDK9qQNaZnZfT/+iC02J2ycvy/6W1G\nPSQjAL5WvbCKbLDL/v2umwmQacQ97WchrPZWNb7VkIFBvxJAb9GCEafQy7yWtu4Dd8IaNYR9BdDD\nSLZoC7NovDzACfnWAcVJr6AZJeLEMKfwdAclLW4yjNiKtm9gYHrSxtiXsDQJhWrI9V0M83TRBTKp\n/vHwkSn53Vw7qVYF/sPuAaaN4E8GyremOz1qS4QW3WHe/cyp3K1MGnRlZoHyACwrG2JTxIMwBxHm\nQBf7RkjyXwPuDXbBz4d1jgU4KY3K+BvthkiVBcF8NeTuaYcSwr42TaavBQJ4fRlcsWVzHwpah2fw\nYvgr2bLMfLy5Iywm/37B5QMl/jhSLlJ+SWbOZegEpCqHeM09fsYjfqNruHWITud+7JIOLCl5JkAk\nybFHZ5NvojzQzI8EUyKGJwaneNE9vP4EVssIS7mhlDybvvR2sY0xlxab/1lnGu3Ks3d9C2vgMUj8\nfESezljsDEtRiIsoZ4LtP5K+ONs5kuTSHWJ3VFA8XSug+1h7opTcpNR/HDoBfzWmXgLocywqaT5X\nn2L7w+DZ7LUeGdU2bzvVVn3F7q4awCJtBfzuTJgCIPcs/icYu2f9EnzchKHIfyu5anTGhs08aBU+\nr5RjRgDUZL0zQo8eeEwEDXObi6PPbl+tpMrwOxoxSpe3DSMiuRKWYIWAtqqKKwYNo3JjFS0WcopH\nsdqVJW4PErxWj/c3fUqEMDiGpifC4JP+mo7egZNb96XM5nvKRdFactoTCNQYSKsW2ekbguWa+VJp\nGY9O1DxfBbOGnxeJ6F4KYEzGghZ1DtxlCVVagDExC5RUE3lYmY0RLCIBrS+yLyivJ3fLG/cRgKAH\nB0L7bCkagLzbBqNPtA79BdNX54OTER7kN2M3zfonZ1h9u1g8W/nwJNkEZTwira6jLeKZayStsmmX\nZ7OUZHYh4uZYGlTxk0xttjnhUhEi4+SGMRo+7v26fmAwNqX7NSJCADJtW1+7iKcfW9JseO8sA3f6\nR6ZByqnO2hjYslXzVIH8BMkw6D49xIXS5Xvzr3U6Yr0oGfKNpL59OVv44QAXKlG3Zr3uAhpMjz4g\nUtxVyJWnMgdQEGW5FnyCpylF08P21i3da7UZlRKVNQrHMuDDTpE2IQgrMlm4OkijdqoEWpple+VT\nYLx9CaKjNQX0NbzX+heCs8mlIkZjmg9VoP2hMkzYBEvVuxex3WOna69OelxnCAjz+2LKQWwxO7Z8\nqvtLRGKvtP/tbxETw835IS8KcDH7379DXMtLhwBWt4wrDl31tUX/I865cBqSzkrYhBuFL/gqpMq8\nxVNwZRcrpZS3R7DjqOEF0gNt1znIEkhk4AB5f3IfenIPFnJ1IGD3+v+q8DiMMI1vajt904HOkgHx\nQsJPuuOzkuOBufxgr0Lxx7TytGz9dzU9IUIpgYC4axYyt7OqoR5rPbmCNFgHU57RllEkCE2T2vHf\n5iTJjSgDJXenJbmYrPktC74fykZSGs1tOZwFYlaUMW4QaKfyGcHl4qqtWSZDLvlHG8JY0t4S4vS2\n88yLD3jf118/07ctmEmmNBx8XcGRr5KCwuy47U3HcpDFoXqSi2ZFNKI58cEuAY4EYqHbiobrdPtF\niBP16D9WzeW6pVeNSVKcEo7anTYURQU673sNSpQTotxNpovqASX0/sOWpnwuBDwM67El461FoWRf\nOwSjuLyMnRAo/YAo0unJVZVcL0YDoA0yTiEpEN9xJvx6MVMGZLsaCyLwuaAxAoyN9f++xZsxloyH\nY0wcaEU955ID5tze5l340TtiJaNwgRvDZxirwq3R8RT7gj8swfToPoyPeXcuJTVSnlzNrv0lGE0n\n4yQU4+eGe+3ciqsUSB1uGvshsJo84+dIun6dDhAy/fxCD4Lgw4DaZAbGB8I1I46eVuTKg1PUX8UH\nIV3H2t89RRjdjvSmSf+oiG7js46d0R9RPmu6Nem12sQhblKg9ngYOBryRGchUPUB0BF+uz6XlQ9d\n+n3Sw08O2OnLWCjkeVpd95TIZswNA6xejMn6wHRYWLr+ny3osCVBB0k6+W74TSEC8qs5O0qVWkcQ\nTGZbvBc0XCGtNPMszs7Idjj0idDpwLuhqa5mCFr5aVyo01rckpKkDlThVntXuUoKLTtV5VIPV8zI\nmpi46EK62ifmUA+Q8fyBn2Avtf7/B2oCvMzsRZxcnobP0cN4eLyfIQ0l1NknXbbF09WYNUjsMNMa\nU0JoBRAhsWZd2HiI/IewD1ODQN1N1Alc78JhXXW6MppdMjT/A17UcmtIySotRoVI+ZTs1dkFIVzC\nYOsgtrkDxVS0eQXEVj7HVlZaT01AOb1JmgSsj04FQ+k9Ah2my+fOCU/VO7+ltKu9QRBm5hoVTrwL\n3FcHLrSWJPqiwTojE5Rv0Y6UTPjeUOKRaDaLdvBZzBXbs3QjKEbBbw1FO3m/QFAG8cfF18jVwxk0\nc+A5a839TEJOvk47QCJtWGv1z/4U7zK8LgnA2gIrV/n33kWucaChOi7/uTYRILLi/afxPCH33BPT\nWJ33bhmp6tbJpx6QSQqbAG08R64ZDhFwapjAavd0VGzp8cPmug4+qarkG3tBG5jCXdEkEr57nVug\nJm/qvYBqrqA95JVn/YesgfrsFKRDyRBDaZyuli6cHhAb5qVkxuaWydutw+EE13X5oQLHQCM/gu4V\nt2NHLSdZZL38xqC9fbD0UC+EijW8hW84NkB3KnffGjK1NuxjN2yqdzx4bWh7KTLDsAc9kGaq4wG3\nUZ6bhhc7qZUBHsLe5ZTQuzrts2MkgAgyA31wxqADPX8ORsNGtULT1zSQ+CqfzJ2+bMGTV6OLEQrP\nVjOiTr/Vz+LPdkRFIpwu+/UZk5EHgiVcNvaZhsTDwofpuSI5NqHGjoE9dSy515zk8tfTuVjgP3VD\n/LXoL2sVV7iRpAo1sjpfIDrhU/q0vnsS9BMZkB2zP6iYGJZDDdc5zQ20nfwne8s2MeyK+y4eKhAH\noLz2UoD+fic8z5LvUQ+7Ti8aAuj2unRkQvSuinCqECt4Ia1AHKQOB8MrAMVfOOAZzGn3+goAi1FT\nZ944bHtk9kdpfU+LFOLRLDdaU//4fS4oUvvhVIV4PGly5G/2ucpfArU3faiO5yxd05o9s9fUcA9x\nc2WV6Bc9SIarlp7yjg0UFN6tSwOnObM4efSB0Oitt+fdaafAJ88dAK4iUwSBUj4/y7NP5/Uet2JU\n91yP7Tvi6mFQb23aiKGq4NfGNp/lyBL2IoO3eUgWEjUc0MeWtBxDoNgbouTBI5l6wtHnmXVRsSsu\n6fSTm2/8nVmTm57/a9vnQk2HpHKcMKgM+6ay0JtUTasqvGI6e0LHNEId0vnIX+vcDBzXwjBy22QB\nHh7EyqfR2aC4zhmjia2nIDxupWoO/U9KqbyouG1tkL5iKnvuRvVwml8T7GfcB8zkcU9yX1qp2Mmi\no2R8GMjzvMVGG0ZILvoouZXgQABRvVJWjon+Klcmu2n2nnrYlaBgY28xlmdWK7k53xPSrZ3fbfb5\n7BhMEzqm+tgS02ZajPZijyNKJhWkjPGBiNQJzcuKmMoK7TZqbFFx7Wa9pOV4/Y1Qv+63meMCiWAG\nloSyfqgWYOdocdhUtmx6RV/uddA/nEgWTyleY8z1WBpGya3XibytEkUpktBTJUcxZYS7MNZYS6HL\ncsOnBx9pTp+ii7PRHCCL+GktDFgZkB4sYW+ZQR1Vg662RXY8FuhZHdCmzRGH+UWLoMyQZCUwcjUs\nw5dzHZbc/ETKqoiYRmVuJwhSGWqWvsNMdmULABOOpkS49ZV7C7T7DJSKRgnQ4YMzbqlhEGeFt/CC\nbcUdocwvgocB7/x7DJkchhQdAtdSpCtN/lUmVpJ1pR9MIwzoO1Sp0WTUuz4+v1tOvu55l5y88FGl\nrQewdHlEZe3ukPKCZz2KtYphlNJNT875h55Ngph/4OFSFYniIING1KO36Iro9oCP7aHEW+7SyBJi\nvhTHPeeOxjeDWxlWuEbbBzwEsiQpiDY4svd6foLCYp+tmoA/kG6G6/YwoTQ7REQUmY7Dn4jBfLTv\nkg4ey4lyhFYJFoXyTiLkjdecuX3/ig7+mZdYfogB2BfOdEoDB266m/t5VHT6DGWgUOnvbJyFx3N0\noEVBDSkdwhhLfVa2Wy2QTxXhfKOwxRZVNl60hA1RWeWEGepVtETHNLkrFARYGJ+7/3CyAZos5NnQ\ntSJCvRFp3T+U4Fif+3Li5mR4meIdDZFXwhWvOmG3nqo3snHeqxEu6E5ni9sfTq80YmyQprOL9vwV\nC2h3S4arifuZ88b+Ik0Pp7mOpv1fBqnoDJNJPJ5WznpuyaatuF15uuRAl+nWYsuWZfTbt5l16hUD\nt9lG2w6rNaf5CaTPF2aScO9q/lQpZ6OF1Zpd+X8rJdnqQdQxSRjwE5TZpvSM/YQXmnbbu95o5qgQ\nAxnJNSA43xQ2GWKAjSvihckewZjOZW0susYbCiDJ1j2M8V2tPrywgd8WeTFfeEtFAg6vLmOcxMEV\nnZs/5g5UUCKUl6SQAkhFQMjTFO4oyChTP+yUWrvEgY9D2FeaA5LrMEu16aGTry3DQ7uUqpssY21+\nYe8Jtc7vqfFSr+P1huwQzpBav/B0Ev0q8eBSuaDwTwDljrNXJ3uIP3TRbzmsb/8rfsLljM7ciFKn\n3PbAAVqjPAyl4K0y03NpRevNuafPqtzwjqW5jrWj1Ox0TXeDX3V9WEKz+YA02PzvK0fEpONRZSWy\n9+NVR4d1N03yCkTNyr9SRA1zxZcgnlcVHtMj1lNw+BX6Ibqtzvaoi/ov+ullVq6xRnMKthoXcOpp\ngG3RnOHslAk8blN4fOllDj+gDcrblyc9nmcAt2d+GszUVZ0/vyLPNg85yP/5EIAGzJQWq8tU3Xsb\n2xGPEgNO0C9pUMEcc0fI2FNJk/Wm16LFB64oXzVfZuU3VgdecJ5p2dsjuPXLj59JZM7urif7obvt\neKIkmXXZn6V06M7TSjZ+IHhY1C2+Qsu5v5UJU8mGq6dnXGA9hMSXQ8CxpmlwtJ+7z/dVwLTzQfRi\nLU8cMsYat9ZcX7VJv3MQTEuxoHWMHXiOKjMjjh/YIcbrEuMChEnFOm8WjqmE2gzzXHdVKKf/gBpj\n8HLIBZPBEW+YrqGFKQ0IWxXvyB8zR2Io2xMGuFxzXo04PpMorXVfHfwiCZdBjOaEA8nRXEL3N7OS\nLGQn+KIwMmk6gyQUtdYu8iR6BceX8cDZzi6JEFfARoUlJSNt2LBonWN2WvFSLxNzE5zFXp3L2Qj0\nlb2VWlNLHJoNZ1UJYTUTg/k1SDPKTkblwujjVMtN1fusIZBTru9YE4aMt8u5DB870VoSBZuqWGu9\nTVKSgVo12nMMEwGLkq8X/iXq2Tr2jnMJkKt0LLD7luzCBn03EHECFCpyooIoWEzUDbGnNdm5ku3N\nxg7h839dKpDnNslJVs3ZaGyasmrsgTf6M044sWzOQUUcT+2AyWmlmQ6I3Wr9ZtZzKEESihIlrnDZ\nqzr3lUDLqAFXLIC/fMpVzvuhEmGihhWsfV3ZKxx9oOdfjCnTksvZsC3FkE73Sph35uPsIYcnzGo0\nTcNzR+gBxBPmzp+Q8lV16ZEMjxMHhRI7dIEFeeAKxG1uJuv9TdT7KF/k7sP0yoQt1ysIO8mv9t5j\nAoTEWLwb/EOq3Mm/Zi5CXslJipobUXZMPbckSJWeIVbVw0DnPskSjty6d1e5nzt+sz7bArOnpQ1K\nL3q/nAYSVKtXSJe/WDj+GCDfNU2LKAD98y43lR41TaykO4cyCEcmwznSbmcIJO4DOlWc6htXBha/\nGNjPYKNNwnZM5tIJFyrlcIjk6nH3hRVZ+I0bf1ybG+6wiRXghbSqMX3qhmfsRlpXPriASe3o6N2z\n+IO2MNvAGqWQkMoU4mkV+UIuf3mxZRqus+oaj88z9o+D5O/nbpwAG7QEwkjJ88VCO3M7Bfj2AX+Z\nTn/tudLY1cyoS5Nhn55oi5XG9D/0aD6UT3Iaes6PfnkzVz4pGOz4BC/0QAdjD49viV05bTevDUx5\nkG99baOTULPlmjikpQue4dHf//GZM92+j3faJsw7RJA5o9K/nxle8nW6EWIbLHNltmGftmOEqBK0\nuztkdtcruaEGBWxQrSTD4K2lxSqJXZJ0PBUjN57JSv0RetF5tQyah9fiQa89eoGz6tENNQhSJYVv\nb2pUVkp2hVqhR5AAe+p91ETpgDx3x7g05IrXSYg/V6+Jf3vlQr9UBNW4GHn+mjjZhcA3/MJ8o/YG\nrSf7L3W1Wm0VBl0H7N0QnRKXhNn3C2YiNbGrh8sWkG0tfPSZezNHoxBdFE1hAHJ6RLsbqZWUsA8f\nmn/wzg3JdGRpfZz+E754d7vRFiwwYK+WfPlje9s+HxVQHvLrRntKCS9iyOpBghyp6opQWq7x2Rin\n3XL74ga+cc+KcA3J5xin9TbSzXF8NM+2dSDi4bvDS31WcK75JuNVtKOiEh40qKudgJyVUX2pp6aW\njxIi3LDY2ly3WJEk6lNTgBttgrgnbxClZCe2TWJCajyzbSiI8mnJOaBMMa+oqZpf6fsT4TgafbSa\nDviApIO2yBhBKJ2nnkoNK2wf6l4OSIFDWUQm7U2a98rnngaE/yoCNZmCeKiy3kaoLjkXod+OFIxJ\nlqc7hGn/R5MDidKhasjWczPUCAY25qDgBWtxX+HnRJdI3bE1JYfPWCFhDL3Rrv6uY0ah+acD2/aU\nNiMhH2IgWtnHIAKx0Wsw7PVep+nc8Oxc0uJo2qC0hqC4WEVkJ+dMIojmPuAk9SDo1poLr71z7ajk\nkml7V1WG/dWdixOG0HMMMFZzECgQJ2mDicAUB4vSNQ2cJdWK5dg+s+Asjhsk96yrKD0iuG2Ouwvw\nBB5nzlnScfUrAqJ1d2ZFR/kMxjUhAtnLoN/LTwvPYxQLciCEd2ih2HTm/gZVMfSE5xeaSA4CoAev\n3TBu5igZWzQjcbFobSMzNMZgDQqTDCtPuNpWUAxeIWb3FcHr11cRujSmxCJwr5iOHqAdnP9lhws+\nPC1rR7oE/Y1HJetxFB2yA1aAJPl6T7GaKxAh6zQzduX/nqr6kmRNcqegsm1Z0EdW9VNIQ4N2kg4Y\nNkxaPaJH+IUeGZvlbUsgf59X+Lepi1JUNgqRiUaoZd/kL0jznaKovt74S4p9IznTD21zw9ubrEcW\nYZah4MO2M+TGOMtw+PjPTgR6/Qb2W7gekAkPh5IPQCop326J4oHTpKxuCR33KQOj8yxq74VbppWq\n126C6Qam/xFNrFfETx7X6ARyrHRfjLW4CC84Y2Gx7kayT1nUKYoqhp9odhJF24TD3Hyo7ePcKfcG\n+aKJUZhMyRPaodyQNLmL0QYr6pJegeBFKORBH0DsoiMU723OzZGpog00swCU4nNtRq2tGCDjnNcZ\nW5SA5+1Gl7NY5kpx3+bogRq8gVgvEBM8clunZZSQQqQ6UW6eeBwbH77WdeUTphPjuvn9UtPSbq/y\nqctIUI43O0coWhTLgbxhG6v6YlUozWvxN3SEvmHhHwGggC1mPYyZuI+7K0EuRaVO0OTBqn+v4j0A\nK0P7kt/vAl/+zl4XAdJ5YeV6fa+6l5ftidVt0tym60eyctcDWwcxh/BV6GkIdtDt1PNh9ctE/HMl\n5gaCOJtkhVPMiG3rUv0YEPovOrz1TXw6Wu/ZCpGGamyQZPsAC/fdblr3oOrXf4eX90mER+J+s5GK\noOEgMXD0Uvpxcz2/rSEh1sAawlst/RXCunwGF9kOZSdwU60MLkSmXSU1aBsdiiNLku5bYEHYt3YT\nU4YyN9lhL1tKBBaFEyaWWoT75kLKtc1dT/yjHrifcH4Phf4VeisRvL0odtbWtDx2nNSIFGLFN5ta\n5+ubd9HUBdqMkyUZ0ByYxd5ss3OPXmBUf4Vle5VPLrggo9PcEqVUdRzXfVedUhjCPiwpxY1etD9g\nX1g1Pg6H5Qt5e/ixxl8Oo/QxYXxpwZ0lrWwRiQ9ZNDOujAG9u5YOMgRNuv41Wy2xpwWjlRNhW2ro\n4btHu2v0+sbFhTo+1b3ifnRIGcPZcn2sBeDO8b6rnAxaSUbdVtel9XXJLVOYYpqB0pMmI0h5JPju\nHA6OUFzEnp12gjHAYSQnCdShAP7+rcA/gyECo+k08/UxzHEazCvMrzvUm2QTeeQyM+emgLGFW/DL\nyR/rIBPr8ivMmKuHOeGPtHO5A9dmTMz7kqTItqE+aDuTpcAOJnkYyN02gJG4DyebbjAhRv7CUepU\nCuJD22w6VXupWQeochoSaWRdxO0OL5B/hdXoYGtQc9Ss1zWqmF5EJL7G3oNkO7hOGt7qug4D77Ud\n2Z4oVDIt1tDlAtS6T2adRo15WNlzAsXi9r1v+ZmuKAk8nn8/vhEnpg0MYNdKoKnrZaY8zWCgYJgl\nIMFNCzcORBgMO9fbOf9ShL2NI2Avn8HbMyChX8jI8LGzQOPnfy0ayebjbTyP9OW5XlW6FDsq07ml\n/sllb0g8fLyJrtJO+t0ft+zGIgjD/pSNQsOM8Fbj6EkM4dYwU3zM3SKUezun64FPHHia624KKZAL\ne4UhudfaMkHuOAGyXO0mLsayEvkfIEnDFsUKazGrGspVro8kIMdFiz2jG3TPYTo0+nIsIptQ+k5M\nE4Oz2/1jUvV7O1g6S4jwJh5s2YWOHmonHzgZbiuxyLX5UN8vCR3j/ymYkuh5Nndy5PywOcU3lKG5\nC4vpChWKmXGq5IbArxuuR13lyyUKFNYaX3cZrXHlPgr6iKOUAqfyS++fepaLF5B5v7dcRxcjeI4+\n3DKM+YM9FEvlPisZQ0pEDXqZWEyOxQ/RJqEgGnxxJRV8RjNtYi6e9FO2PxCRHKFs/1X42FNSLVT+\nJvMxqRbe/vGJTuI936IdFGTW1KBN3DYvcF/GFGI8C3EZ0UrTxOxOfoEzZqUoxh2GD8DWeCpL0xAc\nwDEF+C+0f9WCyieAuwCeCzcMlnPrkOT4yLLkEOTQlQ7V2rUXfzEk0uIZt4aaijTfTivn9k9ZYdi9\nE8jXAaETRvmpYf5xioQlqyb4H2TZIQsyMa9DsApmzlVk4cd7M3CpUB7bg0/ne+jiWvn/VYphGPPO\nKvL7M7ciU6Ldq7YCa+r6fHwQ6DDxETeMvHrQLqioeFRK+8h48XshUkEb/ZP17rQdZinYIC4ekslV\nCEVohFjhhRfOEWVR+j0fC362emUSWOJXF8Nd0H9yb0P+TDevz4o5mhYB9lZUSwY0vLGXkjBljTIb\nx5rForQndcK7A6QyZRRM2whO3AZ/WzYk2UQQkWIjnY/ib1zbaVBPx/C9JNy6/jH+XFYu6SfDS1ib\nT5wTklnVAklX6+E3JCSLvQysVGG5mGax458dVJR2RvrqcgFGa0PL9Pen6CcBjegKTgpYBjpSVqvN\nke9U14g0sBU9E1ZuT37EWQgmSeb43Nn1dpHS3krkDiS3VrGz6H/o9+0LU1/FDJV5WJaIsrGCn/ok\nJET0FvdpNG23ay5V49o2o3M7oqSDsAB5Z1nI0fKpx3sjsTjVGvtX+n81TAgwdsOdF6DhfBCrmxjr\n9OYaw8TzEt/qRjVydqHxO0vC6gkNsOVUm4B4Jcd+FPFzxnRv4CTCE6j7oKpWVazT0knZEVThIsVj\nX8j2yvJRs8gZifGjJ9f0UeljfNurAR7J4bR1Mo85ikEE1e47194FkOcDPNp0SeHfzA/oRL13jUXV\nuv4zwWFvf3FFcgSOMw1twEwrdtmkT4wASKsMRYXOjnJJasP0Z+gucIvV0BLFpwPB3K/tjVXcwcTn\nFKBAhbFJdmuT6UYCdfCt2qTIcGA/gtGd3R0hIGriloMUuiZydKkPFdSNikEgE7Tk9QXf6vdc48uu\nJEkUbJhlnDVPZ/p6y3Oy/02fEywkbsQY9E6bihC+M39Ki+Jx9ycmBFirlOKKXBqk4YwuLGTpT8Zx\ncaoYxnIyngdDwfIXr+h2busxiVhspjg15NweCCYiMFuelziE/oU4oLA7j7CMXRvjSAJFbEjuN6X/\n3bdEfPX7A4Ax81RZ82kn31nz9YBLR6BObtCYEN0Ro0nrf6eFo619fJZcXNMXSzoQy2EHHLkV/kvz\nXYVazwujPQqUdmACaemQiI56j4blmtHf8HT0S6uT+omMUb0jjM/9X3X8+AxAy3MWTk35WAkpsuF3\nDJpMtIwPRKVwDY7ABiR5hdwLtMGj0wOLrUmcVKxx0Osxf8H2humKzvgeLmXwrIjhn/QA+VcCxHrg\nOBar5oi1YH7ihC93UQWmxg2JlR+j24Hd1Rxg5wduZrBz5GQMaeWJr1kHYIAF8PWJQgNGA6W82EEY\n88g1LodwhyB2ywfa42C2wmMv/RkPmdYz1nrKsCzc5jUR/kgG4piUx12LgZPK/n5pvEjOXetQLgsr\nslh+UyNdU0oPpd+tQVd+yIzEUa0KpJenJgrLNrSHLtPlPd6y7IqmQK/CbGXNbMpZ1uPSxwv6z4dm\nJG5TtjIhVnora91fJzijLcKJF8T8netbU0uO8MwYLYseNImWXCF0OKpjn7I7OrVAcQdgsXMKF9ca\nTYeekcFWQ++mw/OAKb58AZt8hNUq5zojgbzqL5bqi+NCzgINLxF5FbBOMJUoQFSWPH4PnsSmrQPV\nWNxz85ypV7XAvmMiUvAIDvBD4+/bMaemEbikOkgRILBHAty4pVhCszPqTUxcaIeomlyJQ9AlQRzq\ngZT5TdA4ME7zO/NEMmnoXbO92Ql3nmARCs9hvTpcMWSkRJtE6UPgSaqI7Fo1y45EPEznKVlZnsGX\nf3weh4OTqpfcU6b0mzMco5qnm50RUoRkH9RI2G9kcH4N7pygVvknq6xTlcCd8mQtLZXqzq0ISzmW\nv0NgRT7dF7SIMsxDa34Io53AAamRnSF4p74cRHXZNa/NwQ16H88bJtZiPAnHGxQUvlr3OnsMBVH1\n+/zBXtZUcoNMdQruuASY9M4kxJmyBS18pTHQPIAlDkhE5A6bBDq+8p+WIDHC33SQoWRB7ZO7Xb67\nI+GneA7WDoqsK2pNwEeaHcvmUX5WdRw1w2vuEf2/g01iznNdILmzUtblLoP4BYJgyDwzy03t8i3s\nn0EtbF0cpZnEGORt38LHF0ep1Jjmvrlf+Mzc69B8ajfmr54BeR5c7yG0jrOpJURCR9z4vPnAKATa\nwZM14pwaOOdhzNru5aOjWEwh+Wc1ewvx9mAF9YGRSnIYCIAV8oQgbVgs5iZBSLXXK8mfhNPeLQ8W\nWA/WZE27Xns04nw3tG++rP1GuXSpnA/D3q6DT/M/Whzqu9fV2jw4rrYfDSBGHrT5VuduU7TJuQQc\nsCgpLg+ADfH+2yQBPQ4hVBX/khCD+4L2IIRkwl9XMK0BnXMH51fVMuy/H3Xy4iQE20N69iqBlomQ\nLOzbHIR9NUa9nURk9AGuCcyNNMV5DJ71OUIUxM0R6sTbgh386SU0+e72T81yGVapa7QGk2jCF/xN\nR/YF0jnOpA8sI7Y+cFxZwvsZAjtWuuzrerPQ1UcCcxSXyOjH3T0daVjx/2SSJuTUMXtFLff4kZG9\nohZfcHLagOZzO8N3LTotTL0sN5WsnLleq6la4XaKWKuO+xRmJXRoPoo7USQH61GbKvNN2ZCbD1gx\n3BpMlid5fuB5ogtdJl5umRyNorefzj+Yxunn3Z3vIdknaiBUKGXXyhasgzLRIVMKvaib5C4UqHO6\ncsmndt6DGr0/iiGdpsWCM3ula1m/9WIcR5CEponQcaCyZY4dhVLfpv03j82q7nxQJ2PyRj78IJ5p\nrvxPXxK1HAxIgxoXJ6vXXa9x2QjlNjEknt29jn/HjesyQjIGD496GenOBTBpHl6RMrjMc9BnmgB3\nVd2/YWFP6dHCMDURb7mLdMVJsDlGqWbuCiSFsNe1AmskB30hoQcozpLipq2C+fOK2Ri0+xRfWfqW\n0qgo4/r7rXzvmuxFw5L/ZYZeR9HN1SYguQNQ9JR50UqJXeEAU+luU8lVAY41gnnwcX3NfMsDqwHL\nhLgN9py5/ds0838SaMHbLCzm8OwEqGq/7+hFS/fxE1yYOtCzpXWpeKYS+9q4k5/Q0iKSqq9tEWA8\nqN2bEF+IRUTdMFNz6OjiicOdrey77Us0Ju4CDV/a7ylhWiHMexvci4c9ZiZzhWPn4HZhnZlJWaI+\ni8+3sxfuAhchxbExoCPdoY0VlF8NcbuvO2n4wvaQ2zmfnGDE6oidqT0OC/MYJd8xbmbgSkww8+oB\nUxSPkSFLES6VwgN28MDXRailtV8QXjiy6c8gKiEmb2eoUMOEcKhXFUoXwD0mNuUYiYxTEdLGutm4\neCxV36xXSdpXt1W2yiist6oXLlX4lZIov8t0dZ6m9y2zSH0kCw4bdB4wMD+X0KU4/SUhoLHJteXk\nbY8x1xSwKOxag+VsvtsTBkHAU+/k3eeOuJOwoV0AKHvm3wSVua0Xny7OY6xEleL+3AQKb/KOe76X\nNJBwGfn3rodoaGdIJN8BAUPLdkAGc7Jo/JhMgtqzw4rOYNAsZ5SuxOjd+vXJcjpLM+Nr+BWn/Ybc\nLZ+TqsXahfaN31CZQon33iMpxQIaYdyjUXNr0SOsW+EtFbOGWJ1nOOR5ShyASyp+HqF3z/qoihLZ\nu5mC44BEaC/5WaC2GUK1xZyvpaTna9zN95Iuk3S7uFc0Ye82QBk0uQTmEfw4nDtmN5FZ9cTg2DgR\nKmhdP8zTyF4144dIwyA8+jAo+HPwPyjM6vOxtrJ+BEYFGo+z0ngndBkslr9VBfBWCS0sdrgt8FQw\ncIEXa6R2YugyAhQkMFmhs5q7Kh1QmNt/M40bkHWNgBiOWeJ/bosTXnRIW1im896PDX9If6xjZ9cH\nDrxcYtFzg+wJomTsYfBhQTqL8fxjybUpgppiiI9yuOg4gaAOSw5C1mjzdU/SjHAajenWXhfN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BH3V+tFPGF9q4g1Z9o2Jb3PbLBJoyIPBggF75rcBjgddl3AEv8dRoFSwAEblYJOaul1ITwbKc5\nAruVPc3w+nNQI5Txs4o5x73ZnRenslSlD/zjnA3BKhuJSmsnbWnRlQGHMauwypp+tkh+1B+wjBCJ\n+L8VUXLzmV4NAl0EtG2S12qwxKQLmzmt5fqX2rT5kZH8zpHz9N70/I1E5VEcoZySXhIeXfffTDNz\nUHvvmStL/9exlTj/5vMK/eIESNQQ3Ja3YblHxXvGJV6NHaM7ujLVdzeyapExLuqiISleZuPvFzq5\noT6VP44J0asE4HWkmHinSW9Ux2u8zumNsg2fdEHwvIKf1p557NZzJZ34UkhsLhSMnT/y9/lgmLYd\nI9F+0h18qDKh+a0S8mGqRHhIG0JmMz9HM2PhfXftTwmaKwbrPyZVpo3+onrv6yYvdOEH9JSuWSSI\nz/goEudML2bPRIS8VUOA1L8wauuBMWwMnIhYPkLpfworcpeAcSzsZQ02NHyjJAnM60koFPYL8MKG\nYvECUFBs6cVhjVZ7Ma4lP0YX9q0n7tkOuTLt1toqDn/q6PoYYM4K0NJFED7t4BR+Dyzne+mxn02b\nrkjJTK5xGpJYaQlilikxAD2m8U575wtyiNivhWEkN0wesqKk1t6Qrm7XZBZcD48Gflziq67Vo7Ll\nelLJU6hp2piXLeWH8YQPxSKr8kIlBcwTXX2RP5CpW/VFstupR6dGFigXz8hQd8y48btjlkCSCMRb\n0U7RkGFnJ8QkSOF8hB1+sQ1sGDLbmMpm/Hc0l7vwlbOopK3MlfZjHmJ3Dgl4rmWlBP6gOGIKh3uE\nVhR6heUCBH5vwHa5WzNEkB7kiqMIiSMwzbJWVkd/Xt0jKvido9Lhf/mZYRnY3My5b802aS+oxXTj\nPjugDLyaLw++eEzjpuc67ICtb9qrciHR49mpZsHuqnRwqZdKoLZgfSOCS2Y7TPRqWpYIQTvCvTU9\ng+xyLRNN1XDum7tgpyToX8vlNRsWTj+ynRpFLUEcR8a0RZER5YWKkXhTNCrC2xhK5OtUKUXV4QiT\nDO8JTgpOQvPjjaLtXp1edSWGLa5dTMUdYaT/suf9wZzOMPy4/fEYIqbgEUWH4uJ7gyQVmo1LJiOl\nVwN750B0yqnNUEh/SwrxICaA3vBua8mmpQDej8zuymViJWunh4bUUwcgb7IeCWFMSsxjuA9LonQJ\nrWraM7phog06zWr6YlfZz9MnMWlV0Lrfq2iVMoyRW/fAEkhGtBQc+dKr0BTQdQFvm6FBu/kSzJNq\nkhzLQ4zNo6ls4eqDMMHoulNRjWUKORiLOZP5l4geYmFY9jBEbWZYFyqNmNBOYxDUa9WDdlBD+n85\n/PHTTS2fKh7i6gCkNZ4F6a7dTleSuYS9FDHOq8oTroh1oWBFk3nQf0Lf18RpFUiO+54XqjcLpbS8\nj4jgse19h55M+U4zkueazzN/pSKshvVtoRdE3zhbDHviDa4dx5gMldAaD1BjKgIc5+IKUgyFVVLB\ndYCsEHbB04q5BbJAfXqoHk3snNg5xy+NnDw5Tt4BuLrN6fFigVPN0rC5bKzzEkLhM5l7KXdrY5tK\nsraWIEuJismUExL1Nz4iejQUUcu56aEM7rlwcYEfsjrtizQqq7WLGGeaMkhr5WAo9vRX7mS1E3kM\n2unb/5t95EtJetFYHeJrBZ9yqudoSPUFcntTo9n2WJ6i3dqfu/jRZzVldmnvfC6vNTCNJasFw1jJ\ndLHiMINPjmHlZapxtxEa0ENKOQDrFL2psY1bgkjT4j3pUNvqv0xRcwBeeGdSLrMzOkmKm9Mk0T2t\nGFMRMW4i3ZaBhD/NR6b4wO2LBda1J9IpOfaNWBuyCxwLDPy/hKud38emPtShK0d4Pm4gfOoHHNSx\nDma1jT644L4yEZv1lJCRsYV1RO1BnafX4NZxX+KG9EXf+lIxnX8hU9hikqph3Gqcq88SuuBsxQEg\n86u0BCTbfgGX22DDcr+wLgF+OUhUa0CfSwaT55BPL397QzYCzCNzrtykx8c8PkgtPivgsdbG6iE9\n0O4XzUPoLOIkXWxEt7dlFdZzVFCFULzWbrrMSDorqgZj7I/HbDDVMstPWIZasgxMmp0DMatVyPAb\nGE29aKhC+vUPKos60ieKTp/gXySvjarzf2Nk85x73b460D3G+0nWQv9o6TC3BSeqMiy+9dq3fyO3\nFwFB8pFqy2PxkdSBbV+oK7nkxtH2c4GKSqWz0dMzRhpzsSQiBGPzfkCR6U6xKrqzlPYYyhcIVYiS\n4GJn9MT6mk2Qm4HJTUbg0IpSVrjr6h9mBWc3FFD0v9Cu8bBxerl565e3jynODm+pxQcIrwqbdVqM\nwYtZWgrP03MGRQpTboMwqgNAT5/7am1r9qUpDqQQikPIoaFh0LaeC0B6OWuh+/n8JOcOHzYUKd80\nqzWoaKYPi0qYW2nvt4cDOn4XbJHl7ytmq7WJrFa/H63xySEy53Dsb02SwucRQtIJRU8h1ccGl5Y5\nC1/0aboa5qjm+nsWOm6OqCbWyYR/5/3r2uQWIlaa4fOfO4adcSj4Ac62W6FS3BRki8i/o/R7qT50\neJOMCkully0yvySt1tF7bY8HeTt/glRiOzEgiGD4vwCm1DdVcpPPnSXB9jMDyjwkQ/FrxbpuFD9X\nqQi05Nz9YQrYmx7LWwOzUe9FADJNrQ94x1Op6ypAzKknoWCfbYUkm6FFdTLIQIgejAvP9rE8Z3YV\nlLQFN0iSefjdrG/fj2C9CesSfnKl2NjL37LLH8Q71M/fzV9DWul4MOzMUIWGgewLfmyUcw3WZjZC\nb5uHgH0Zl+tLtk/B8MpKxHY/lZgkeY64fpfw95Doji9rbB5VKadDwJ4VN0JYMh4jwc1vxJ4wNs7v\nNAzZNnWHp2nbLHEWLxL5xp7UwndnO7YJhFk/m+Xal/z5bjZfieHZLUeADecX0DUEpxdVLbuuYqJI\nME8VQPc0Pspp4zajWcSWv29sWnNbfB/IlWduYsQo97mDcpz7G1NsPY5AnXivNKfGvP+QycUNojGy\nsKmu1bpbW8SRoZO8uQtXUDR6qOEbCeW3wvbXIddkO4DyHcdx8f5HlqdGYrSajBa8M5XtcOuhGcp5\nkFzOyK7wQO3ZRdeUgwnBM0nAn+K7P/ilqe+HojNDpCpXAhHRel/3MAZuIVVlZ9hhyp0thIZNMul2\n79CjFuXRlvLsvt23gnvAuFcuPCPYL+yTENGNxzfnwCRtC+5KK0yYUeUoN/I5/caAjhXxkGpiRbi7\nFGD6WzLLgI74zdKVTqlNQqXI+qm4WJOA5wzz/Pr0NEUFvwROPgGJAmCMNjkp/rs3KzqvCO9qy4yF\nSWJTQeodsQCvZggaYpWxs3H9Ol4urrsPmqj/Ge9jv40iVAEv8Qj91AJ4w3t77Es5MBBzxqEf4LHw\nMTP6GtuJEF+RVIWnELWVijFndYaCewMtrcA/03FsDaoJeUipbFlgqoGDOytsl4Kbfedz0xjvNQrz\ny9d2Gb3NpYCG5ibpZBIx7XFnHX+AKWbHJdT8gE6P22LwaAYabzAlDvg9SQUFpqj+TpsoueasD7/R\n0AqvxsKFQFE+rLOQ/J40wIZ9FyQHjW0pEsxHFR0GDDs2bM3qINdQDdvVYLzQPw5n0BVDMwWNOx9E\n04MGGOj4HU8fEAZ2m68h/0NqYLaxToWiYfriXbNChZN7V86PgBZefeli9J8K/EnzOxcGVCB9QbbH\n22XNMtJsW7N7C10mVkASYBE/MawY/fkwbP52yNRSEvL6YJaHmEe93ikMMLiKq0r7oI2bAaeFWhNf\nxUk8+BUJ6ZrbU3nbCN1343qrWebePvutk9JgFXkxw1Vk85WJqIqi+nYPuzpGmHCHQps5Ec9BqxdE\nMiNnIpZaaEX4gKPf8dhtb4z614JaYyBkHlIIlTPMzRwgcPLhhzMfaemNnX5N6NkIeH49E/+1U3UC\n2FI8PxxxkpeyGISoPcmEzc9C5EhYqxl1NapbHpGaEDiZlhkHpp73ExsNBeGlQGKej4rZZg0+Jxg6\nbn2QsX1ce3JQHmdr5AxiL6WqiDcBet/COH+FZUvdLiKC76FwvyUjNQvVbeO3B2VxPPPhK+cJ8LDa\nnyYSreOe81f+r3XjYWhR/Fz5Y5iWQlRO7u9Q1mqetJp1oAJruG9Ov0N6Z4V6Th+p6kELL3SsYj/6\nqVuYtXa5anoHUpJ3JQgw4oZZfbF7MNUFDb3OJON/5MuyKykZiqUgwtOGACH+q5ia8Xg9vzIjXEnD\neIJkhS24+YeZrBOYsi4pVkUWvunPyPwJC8ZFpg643+9sR5JDdMK0uXvMnPzuYnakVvgAd2daDWJl\nA+KKbUWM/DMYW+OJJ00YJwID8D6MZNB2DIFzOIPzgWobbGAk8DYmkRWCfbihwS6j5Ne8zkGNFa7T\nygukKLfPRFNGCDgLdNqH38BDUKLiStJhYTxquba8dD8WbQh65aTUtZDkKyOUbJDCrgO//OV2Gbmk\nq4mT6h0xP9zWgo/qudtzkwwGRrkw7r7dHrJmjSJqbvpdFaxAv/yofbaGr25/PwLEAjj6FX6aVVAg\nVX0AtO7lVUbnl2tywlHOqYvMimoiKVBBP5zKbRxI80JGtfKPPCa4qbATNePVHqtBQ4YchyIssqS4\n5//IQMsgJzBdGsvqi/ASQ3prxj2XAc0ADKnrcnLoQr8fMwR5MpX4axzl/jtqJIL7CxkidNBh8cKs\nocT1+YQ+ToXm7QtzaC1KnTlsnCywlQWLkfK8YXRKj71lSPTglwN0+w7OMnDBSOcfXgv+QD+eQSEl\nlzkiHXHMognmVEJGidUUr86mEq/PynqADH+EtFxIIlzqT8q2tXb1wmXizHCnjyPoRF8KUjtAVnMU\nc9qp0YZZbepbaVnEO/P7EoONAfFogEOTDg1lFSF2ooqjM4kM6r4DQw9Br1Cj4Cv7oikU5Jk08CzF\nIFJzyoZYs4BgwIUD+6fr5kSvYfoPBOysgq7s7miKlrOpC/3+d+0KYjPoQg/S3hAlYKd5bXEedJko\nDLnhmGqxht/i9ENvcUHCm3LnC5yMKhXzjxbdV2IXiRAC6Lx55JoDk5MqWe7mhcP94RlgjnPAc00J\nkI6s1jsMtt2Z3Tu73/rWv+KkRlZkJV0ppvG71SoH1gxKT1k6o1dOGk2K6wNhg/ZnMBE4oxVCmEA0\nWOOOndw9p6o6m5n+MVTmRr41Yg7mf4LO4NLQRfvq+u0Uh6CbqOR2yVYzvWAPcT2OD50VKQeIBh3z\n0AOtMMFIbYVIgYuXODyyD6eKxMXDH9A2b+brQdFzZruN6GGryMuwGN/X1BWIkGkzefJg6ixFNeWc\nzbhPemXvv2QBl9sRKG8dBxrmS8rQpaAWHA1Yo5zxAYnAWjlH7DVTOIrhLjNDHYbP4arg+Q7rNtEO\nUaoSHEoa8iFZAvBPs3fdhp6vRHf9nI55HnYaWmFEVISgjRsU/cTh4ESdyO0INq7Lqtil2XhFcXtF\nJBCJYioB6DT2yCPEjgsD9QIII2hW5KdgWyWP7vXFYXO5PuCVAhdu5ihcGejfcF7N2ad//657erB5\n5GQ6SsE1J+KUJIYQAhEc892CZ6TdA1cL69GrNBkziSslwHxyU1DTZn8KUEIpjCyG0AWpOq7wQkCI\nMhOLEJLfYKFD/UVZIQM5HFnEw6TWmleYju2yJ0oVMxLGH0dCovqemuwIesU0onVQ1iUgjJd9i0vd\nR/a8qMuzYOBIX/rML8cyrV4pnaMgOjFRfnGr8wH3QYzWpLSAMHYuAI2yQYO4kTzpPkfaXghXRk9S\nJsTTNy333iURLP75IFHLxgJ0vd9brNuiueDFK+TN7flhdr0iblsDCXiTPKlS+9eW1IQnc6pMbdn6\n6Nif2o3db5eIwwdykknWyEI1VvqphZtrE6wWQCPJZjcMrCz9o/Vzyew5lfqRisebEYv+jEBozBU4\nTwn9zcJ68nWIkxlXwiFi9yLQIZpS4eZOFd7asBa6ZryJA8sKieE5uo7BVdAB5iRX4AkMXCwkQLl0\nUSnEV0rfqyY2AsgOaDSODf37fqrE/XKKMqR9c89B7aUgi13GNfeHceXXL2v0xfDJf5Nz0fI+jyRK\n3XBFpw8Eyp2XlvGIHS+L/5eTvLe/Rm/9w1L0xMbjYDv6fXSqEBSB6myLLvTRXSPrVRD4n+cU8A5w\na4a2zuePSx7EH0FyVH2cJbmkb02T4XXZR/52J+n0a+jOGrRiiVGRwVKtIvlKivm5fEOOLP0UVCxN\nUEtUvRbnBcGPUPYBO7CfNy7Ew1a/PYs9y6Y+3i1vNW5LO84rvJRd3s4/kigLCuuuRAso0qqaomHQ\nRmzEgtg11iqhZ4AodN+q6MJgWMOhgUrT51WJoMZDZKQADsArK4G/Qsg+2/uErQ9kZuXffj0gJe7i\neqEcx7DNnll0AUYPpb8DvKaBB0mt6UCd0xzS7moSRtGDAbePI7kzmMCi9jECBGcdgtcD5DA9Vv/P\nkxKRA7UI3Ku2qLPMuy7qOIbdWJbt9mBoyTHhmwAU/dfodXYWS0fN7LiqbqvNz5LSfW2jyvoN/xlq\ngu/FyiRSVv8HaXBfF+fzHDJxEPTmN2UAInUlAjvFQW9oilavDwZR595BLQozobrdHWRYeX45AOmV\nXHPIF0MmYMFNzD4bJEsjPcicKZPnoF4k70wC8YmgoyZc3Hd+2Qwx1fFdRsgbJBpj1M9ODdBvKwgf\nIC2xgUj9h7Z5azOKOPff5neQmv65MuupA7M0efIbCsDXYkp5uDuh2H0Kk1U7KcfiCuxZ63hDOSmt\nTwTkfAfj2fGZfSfciFehaKrdEbZVoeut7I22EYgCbojeLWLtWXU4smYGeHeR+gB0ywzlLtNfXXWr\nNICoHqCb0Ci6AYBsh/BRTp4Ma+2N8D8+Lob1zC9sKYxMRfzYkZuBvmYGiJ4tNbnAB4Du3lWA4eRM\nc3qNhdoG3o2HkU7D7FtZpFoEWnRrr0/m6IxTrFHCqxYEaWXw0+0nlH5X0ZIp7HuHyS+W7iosyTc2\nVC790bfFy4Ky5UoMNQs0NDqCBbVZNmIkGdIzHMiu1g09UCTT2nG1mZklyqxuxAqYHNrLyV328HoD\nhnFHPvWEOzFuFkbPWRCzS8xK2oIxIHe6Rd5FHA3XeWtBXgNo1/BTQZoRcANghUe7Nr0UFzzEEVtp\n1yllHUtvrtZraLIljuYSFw2xbzdigoQ47igttRePI4+oJD0YYmq59EdruEG/GHyNEE71v5iUU4ZB\nU4tDGhIpAff243v3iEabuHHelyklr42etqBanBzuADMKtQuoeXKzLeegYQDCy4dMdruNH6rHHJi0\nwylTMLrd7RSpu3hNgMmTBq2aAvclDzmqSmz60J++saG9UNd7JD1s+4biYZvdnD2MAHQMeKcVG1gR\nXxDRjn1w3GG4XFMPzzBQbwa+qDALvJfEXAVwd38kQ+qHUc0MYRiAMb8NgbuBGzdF7gpGBzxaXfhZ\nFbRd/k6yr8OyQZnsTp+zqyTN4BlxCYsItcBV7HJlOXIyueuyA8xtJSkN+n06eZwFirJUfEF41I13\n8LkUlA3pvpUClEtVVISobBT+9/V0k+wJar0Ocb6AOL8t8TDXc1DgXadmSTzcyOmSQiR2O89UIfWM\nYXsiYqSsv4rwUc7UF6Q+F2uEHGKlkMImb3Ocvz79fVF96Yk6NzMvuxslC54BXxpJi7lL73dZKi2z\nZ0azf1y9iH/EWWWGocxl8UjwREy5lQaohbobMukxySTWhiMxcWNyOZd1G7PyQefloQ1Tq4Rbq5Q1\ncrW3rgV1tQsLeb7RmVUGJDXomdIXHYqQgXUVM0Xkj/Gyc31IqN3pOilsx2JLG9mJPRHRNx6NVqaw\nC031eCz5YOJm2P00dmvXzlboGtqbE6zikaYWPIWFH3BA6s2Hkmjxu5k7Z/qeOaXn99dKJzL04U9J\n+pvkyatl7I6dzxK/L71QbRj06BxsFcw0rBozK7ifNkZEyTACyacjNInA5NAa42LzX4jcNHelbGs8\ngWkZp/Te2inwddUd9F6tTNSchugcvM4AfUweOwmWWOC1tyEQa8pnyiBwZOAaD98IagH7dv9Tc34R\nZCDGt/hPfspOT7LeZfnha6KxL8feSgNzNCBKfowUslCVdrabWuS7EEcf+Ju5f9qYJwYQmSH5RjOl\nHwik9Ha9dhSkOT4rhUwKgAxbDtslYMa//PqyGc0FAlLTvt9n6UtjKK+IOx80dmRdWh5mY22WDYZm\npseC+n3vDF69LTTHAk0ITSeSL5NGNsjgfeUW9tmPkLg54sS1+vGRlGXMb+YSOqmLHMxfd/4qofyw\nq7fXlIVGiPCTzN+bTK6CW2TqtCP9rPE/lISDEuJ/MuC3ZvaaiVizgwf1APxRoun+rLAVzajRsRZ/\nnbKqYjt8NUL5xC+3WTILxVIzfweShnxBOU1qd8u6vJ3aJ55xUOHnEMMZYwyerm4B6+ur3Ai70eAS\nMfD0/rFO1bCddcwSY/GM1P1jwbbR5atsU9M2UzObYvW6/Amfju3wRwdMK3GsodKKpQtEFXpjDUnB\nK8wjPyS2gsQk8rcBAq1HdqTzhx6tTxtxDoMF60VInkCul+kokg+VN2MXygn/AVx13JmIuyaIOA3k\nKEhIt5FoBRBUfyB9zs3KEA3chwaln+cASXCGpPKLcRtrm+3tecGXf/sK5mXOVkOpWa1RtIDQd6oR\n2h6L4pUJAXnzxRovwtR95YuVQC3prcb/MQ3B+6hRJm1LPGiT8yNAXBria2V/zOw3iG3u/kB5CpiU\nJZC5qJyIDVdpkZyarmSssGAwK9NNFtkqbKfjvyFdQib6Qic6LRP3yNyrlAD8TwsT3zkPBFVrTZYo\nVHbrLfZbJECUeJaF5+v3bhjpKTkVH6o0U3lCnGhrxPZ80m2vtEqJkA4cdURlt2sbr4cJ+tTfZJCi\ndrnzZvPvHJXVWtuq/0CdBThwcoHULI1yogW4DM82Zw7Qkr4RelOpjDy/8YZ46u/+Yq1kC0CsHCBj\nDpkoIANyGnEZ/b4q9h0hCg1QaZWqWJRQ0fQspb9M2nQy1zepjPpAdVnF8nVQjScR+P/k2Aq9skIs\n5/ITDMeyQhj5NKmfotVNeY2eYyzQTdHlFfI2b4mfLcsvpnnBMRDyqrb0CiIQ+eunAzZ272Pb1OYS\nma/aboYPdkHDw4HVAH1vdw8mhdrTEI5tSYcvDp3jfk/QJoH4Rk5JZcrWfXjzePN5BuP2D0elroHZ\nV/7djru+lLZnGOOeB3J1KbTMpxMBGlK47ynUQuF/e6BDOtl6ImfDHOcEE9lWF2BIzueVvfjjnGw6\nF+JOwSLBsXBYUb4s3AGQjRfn0mrXnQ8V8s5QZN6cmei+C9nztEu7jQx4U9Qt0X+1No9n4vgSrwxr\nqbIkQqhbE7BxPS/c6tkPgEbhOQk4Kux/LxC9QR2gL0xQRlP2FI0XY4PDq0IovW044yMQ+u5X0Zjn\n7leVnNVGuLUWYl85Gv+d9HqZaNy4S3RYu1duw+Lh8CUmtEICMjzB0d897vw76Q8XF+XhNjBn7YqA\naFiLmM6OHDbcNIcG1Loiby3tAuO2zLsI4uQFHgFkIzSKLLmNd/tzc5G1K5mLocEgvsHFeFslJef9\nr0UKCyDVIuWWT7b2ZElgnFgzrks4C2Zss96Wnl5UNix6Qkn2+f4OuPa29p/ADuGPV8D3O/X3yZGS\nnwrTJEE8/fI17pcrmEvGALF36hvY6kLWNdrZGqWl38oeAfTi1qHSWylYYGmiq42kJ24x8CYMcnEa\n1zw1V0bGdCiws4Z13/nqZQRQoTJEiuOsoD2Daek2tDJPJud+2oHO27KqrCqG24tyIg7anBW+D/CB\nCFRZa05zCO02bBQnNW9FFqL1jdyiB+IAeetWih52ZCjF1ez9AGvomQO7pHg+QVwj7PxHt+NRxI5w\ntjB832Vu1kDgcSZmW3EgrWLbqKcVU6rZ11USzBiBHOwyTnqfNvd36WLgaje3MdBln2VxqgWNgbMF\nK8S8EC0IGPFqyjsoQRwjFgRDy+JvqdVjYsiHbjvzzDs799sJUX7cv5L7EcAGp/pxv4xbM/KtESR+\nIov9ZcZ8I/uaOGHjSuVP4LoHMLtvtjYcbI2HeCc0FEhgWoD0nfFHNdX6xrRJBcN0OkdOsKgX3ROn\nwZV1qECVpVDXFlyX/ED2yGBAf+kFa36PtCE8eAv3afGbM9kprCOKltcbDRqSeSgigA1sifnbSpvZ\n7tyGbk0GWEqcyxrM1uZsgQC7LK9QfWhgBELOKkH/zkPi5zjDySHh8NS1NhOafkaIr5n5Xh4ieqND\n7KYyJIVHUtZios6QjvYu2m1nJMDaJ2XcqkN8beXij5QSkB5k1LkaOvbEmIqw+UJQg+Db1IWpHW2s\n8q9xAASI7J2Pw2oAtwHlQlSq/97Kp8uQw4T7spDxSCVnpRBpsK1kEzWWMbIw6eiAOKSwuQqrBnbR\n+wY6L1bJxwoJJUq11J5OzwPVZ+t6Fi9s786LyJtIUV7N87Amgxm5bsqIzec14wsKzYJBf1+OTtvx\nOnsiwYgHKmlt88QrXqcj+nCE/KuCGfIe1AEBb2J091WxDTtL44Q/L4crcSaQFiLHJgp9DP0rFUTc\nTo1+XiHgQqlgjQywlcONr4ctQxdXeLuA0tEzI3L1A6O/c/5V4XnYbCvj2FLxedVcZDlYgl/fVT+6\nwWm1u/DQA/8xqQY2xOmQySY3KkHZ+xbqiBiOmVB52CJBu8+foQiuq6PDG02HPO7KISsZ6e/9DW7H\n039Ue3R1yh0lBRXNV2oqzWEhfDy7Oj5Bkr7SZX4cr3HW1rEkoIgxNRL0gwdvKRyMK1DcaxAmrqEv\nTIRLo/kLSMoKzrYxKZTK2lWlrqDyQaf12+IhA+Sg+aESFRBlwfSFGeygYyBPAas09QEw7txjl0nQ\noK3RTVApPHVOHa/+0mvw6rJ7iB48L1W5as3RklCPb0SdIHPGZukIKsgw82tYFt0DkSVctOR5vNiW\nE8FrR8rZwqwU9okYZ8021hPv6sQBbewiCCamoRjob+dt6ACdLoErn6i8tJz0LdHdlkjhX0bD3adJ\nmwtbLnYYiakzG+qUsJg7yUkKwJwEhrZkSjFAUFlHlAuw0WI20782NBYgynMmcOUEl6evpQv7TmAh\n9ydfZZwCBoUyGVwJlNm/rXEmdaxRJhlYhphld3SaQOW5apkBOdI7H4dOXu56+XQw4p8tlA8zvqP9\nKoN3kiAC1bgLY+ALNvn1jgBbdSQ+x7l0QyDg4TFHGiGg9PKu3ZmLXYHZGk8oIG+62+dLExAtiH6I\n4tUYswaX6eZHXLGNLK7yrONqr8qDpQc0p22p7yG+yVV6ibZK0Kx6lPXaBt8FtzCoIzkuVAThE7sb\nivSSjtxmH3Ccy8AWh9dyh2PJ1w7Yl5oIngZZ+wN8M72BLi3PDS6MKfNeUpDYoqVbQJHVRzxXmCLn\nEciYTyJNNmc+OmKz478GLEB8tF6M6SVkzxUt1vbHbf+mkB47DD5VRw/u93ENIAouP6oDT9q4HJhj\nIZq/mLTdZLHHfa9PS/hQaJpV1VmSwcrtFdhpznqh47DLRJv5u80TZMaZfS/cwEImGi4x2BL/QTIJ\nkdWBYShIcZ1M6HpZID20uOius3zd3ItXQ7HuBIBzJclq08OqxYGFtTAmusUXeqyQPVOC5T8QXvkQ\nZQ+ZOyvanhB3NBBrwhoPB7OFtBv/rNcI7SrNBZM4iFuzPksedh6ZO+mLx4Hr44VD5yqFLL1SpUpQ\n8l2vGEQ+nVSYF1siLd7naCx2vp9bAayOorLqNULdc1QZ+Y1GmPlm1tm71idbUDfEA+kP0GC9lwqE\nObGMuEyVEs+vGSt4dlZzPAKS5HdNaXbFlvCm+xUmH96BDUjwvsXIJUIs116gQVF+7KI3m8n1VWH2\nGSFFWabxpDZZ/BUkNt5BBjezsMBZP8SAnjFO+4wbD7NtH9J5WkRTjFOClVu02LjyKgvDG1lLJvGo\nI5RUxQCUlU8qr4P0r5y6qUPL7hWtiGAtm2qMcvDCs4e2QxHzpOlkfXqPqoi287Sp4oU8e4+Ssg8L\nlTPGilA/zqYxumHYUrMSao1HwvcTaovGudQTNhQ6O9oOiHHKB5JPrguY7bvLMUjEjxLZXcO2PDX1\n5QAxvdKuEcdjQcHoE9ZOLAzr4as27r7RrTpyyNshKgdYBmZoBHBNl4a/29DQJu6qFUOLkUmeC5XP\nADf30QKB4cP7sxrCAqCgWsZs8JPOvhAgDq9dO2ILt+rovEndlRza3gjaxmTHkgKD/wHktiayk5GY\n0ufS+N1xPyYlzyFsCOpYgajE3/X/rb4Yv9uu22TC0B1Rgsmma68cbqxpeVn7i6mpN5dUzkmWZvtI\nq3g32rbjaH6LV3LjEJ6B5izzulJsML5Nk3KXdgaxB6zbImo0QmQUWphdMhroGaxbueHZEJVBlj17\npAkedHl8h1SRLW3eMwOe8md4WfkLcQzwyZCpZHTZApyZlaDVtdQTgnCWdhNEF+HKh9MQow7OOPFE\nFQhI7mAQc355qjMtHeb7Daa0s9q9gGsSho6k9QK+S0NlBzF7NnLPHU5La8OPo3Ikr1zF1sfa9vrd\n5SD1cHT24wTGNwvFn4afysqYHiAh5kZrs0sELbIu7yLrg8/9Q1RrwoKPcWr8DuU+XQnIxENWJVty\ncJcoYMiV/nuousORBrZbHwUOHn32fUQs3InQBBMJ7XOvpB2L7hQpOG9CkBnVUv7UVHbIJM6rulVG\n0JYk5kPzgTMUnQ8bjvPM5SXk38aohZscoGjN/7kMcKM/V3XngsT51veeFPs4ttsGuO/SH8HMcg1A\n3LJd8RCCTF5gMPjEK3Y77H0fVHIUTar736FhOrdp5drOrXZG0ngGxSltLfKwj+orPG8RxCzlCfsz\nEtti5uKGPf4Jn42rnUfXjhMHcomGV8Iu2W2wJLLCaz247nPeWMbRMrKZLdkeifYtnL/Z3VeQA1HO\nHT+uqTV55X83Lcgi0pOY7YFXS7ytVn4S/NgP3MH0nJG5/qHxOyEF9Bbab4Fwao1LIqfLG4ujWX83\nk1jthMEjnq9hSE/mSlfdKfEOJ4FNPG5FgRSTE7ig0F0gx36Mak0Ceqa3S7nZKFM4faGx406mUBy9\nEg5PYIj+9VnfNEzp6SpwSlwKxFDO1pse0FA4pPy3fHD3/UlfUXne/Lpym/a/vP/s21v8eSNVvIbp\nAifN64XwORQCZ3+BhrRUgMGJ3TpphmECoJHwIrn7rd9zpICtfpoGfUuD7FDYO4u1mzGdiy5ZnMoe\n7Cw1VCcWBCX8WE+xqll4OAYtyrSsmYXpVFAvXB/pfUDb4SADaBZF1L9F9N9pF334Ggz63B8Qxnx1\nCYbQm6zToBa1tAghys/58XGNqABWy0hGzbBapn2Zr5SLbAFQKR6JX5IKW8KoBtW+97el5FIOxbQC\nFEOUz+/PYWkv2AEkXhqsSlUBKEag52d8k4uShZ752+R7RPkAA0nChmbcYJFRe5ClVq9TT4QfmmMb\n2H22r0fNYFTH03UhvvhlyZJdYkX/OXPhHrS9ndLETppezyCAoZrdBgwSbF59bjn656MzSMC39cxD\nKOpGEayfDf5Lo4pyKvZRqtSdiLUKrPs6fWyR5ax1VhEdRsapSKBoEXokItjsrZuv2oaiHqc/O1UD\nMQH94T9SiJzyIWR/IrlRVqCl+bFHSaICd233fsQBNl4hv+lNZsUMzUKDPkD3tUe5PFNRGaXczDnR\nptYtKXjuQZgkn8wgd3zbAtYn/hQLLBz8hVDnDsDzkPEaSwK3HVIBCy/IwX63AGkjsQ6peWmObQg9\nOjdyFO70ftOlSPqoJpmjrAFeB1u1a4hEtZclLDwOKDeA6DCbWT0Dkp3zzXt0c5tVggHtqfgw5fd2\nLRn6xEAZSLvYzZeImgHk+8d3otWT0sv+4rW4j4GNWC9hK9jwWgcyGNelboSH3HIGe6cdzhg+gMVT\nxihR5LFFe+2KLnoky3oOKyB6JpYtdbShtdWih4nUlT5llAAlFxtM1YT+srK6NRmrCWGE5V8Bpt+5\n7BNg/ihlfD5VjX+Vj8ckREMNeRToEItpdgc7PNGfNthaOp8kQT4Zi9zCrmdUDBF6zVZm3X0aq51j\ng1Q2wpUEfd9NFXtYkf/zKbYxWyLxr22PPWJwkCao9iHUj5WIM8njTTNEa3Xzkqf8FcM2jJJRxuxX\nquzVsKjbKGNZJuvMEjL/gnQp8oph/1n09OHn9WYzn7B6pN3hx5CIbmJ3PrWp+muuixGzK8IkktaK\n5XEFp1ykRITduj0igx0jUdCcy0+YFxWCOhGgKBB6m/kHlpX2SjqjKEoYdqTOcmJszha1K2Jr2R7A\nM7EUhWcYfAoUOpXsRS6ooNkUFH/0Z9lW8I0dFIAyStkDo8JK+9aBwRsjYxE3wBafVq4wP/Q9hhKr\nbZ8E7ZLF90zP5r8ABTQo7QR8WpXQcQCdK8YUyFbe+40hGPmGYZasTKZ2zUypo2zBMqzorx5ryuC4\n7vZrFR6yOxJEKsWojHpa5ZU2hgddm0X9gmlGgbM6kAGA+SWoaLe1mrpCvmnF4uVwG+Kbec45Cika\n1P9jQ3XPJXYurW8HpoS5U4zoUkFBcJKtpzBcKj+TZmdSlX7tHVffyd84asiUkQ2sGdTZ6zduZhfX\nk5nQITME7H/mi6bl/IhiVplBvFYkISStisuI0/lUvzsQ+y5LIAbncg16ABeQN1qEDZ8TeVjSXOys\nsV4xGpT2wCpDKAt5L0QjX/DmjDvkUpVsCTSSL8zpz8xPLosFrJHcZRccAXmbluktawfmvBWObf13\nsBYrMGxwKVmiXa8p5uB4+vf9AyAoQpy+DgH7m3KgjhZmixEdZax3LUoe9AaA0jRdUxc85wy6tePY\nogFtZ+xC3BZncOxRElBu8UDRNSk+Io4/HfiFqb2EOlqAVnTrhKBuqejXWSkmAvw+dS5IytiWI/it\n30Ad44xc1GIRygJiZ5VDKTVFDx6QwP48Hp/XwWrOIi52YXcVgDr9aarTlpzEC+1TGhANDFB/oZ3j\nU7+Mr3etbGKVIJ65dBegx6bwD+ngRv6ZGSKFCpm6tSW+OYbdMwr+QmvA7an2XuOvmoss124cCVMQ\nP2KwuMdmwGTxz9QLH8jS80cPjzcea2bAxT0Hqm7OThhtoZ4ZNXOFjGFYUGZ77loqb5zcaNHxtw3P\nJ2BJpgqwSRBG5P+BzWMCdTCWXWBdsemNX9Cn1r6Iedm9x1s9elFWnzBynC+c0LxTgZ/mTk+nqGkH\nagVTuDTXofqKrfsB+jRUUNRlU1LKvYU+wBU0wdzXE5iS/Mv3+g0RxcRrwyaGYGQRqxZ0V/QUt65I\nUA8+MtmEjyLX7ntJ9iZ8UBfOodjkHevADOcnPO+QNfgTh05C2rtab2eTj5xWySjt0IFvW4BHJ5n1\nPczcaC6ufH3e3JerkpwpkJd73RgwmD5DD8J7w3EKzDVM+HgZ56UjFLv22bomISriJtxlDXS+eVh/\nBbJLLwO5Z+cPj+nSusr/8Q90UA29nGB94pGM32yFUbAWP0LWRUayKK314FnSP2c5NDJDNUeEowFP\nmZCCUkS7nZ78YyWv1Ja6IsX0Mn0BZI4vdYB053Q6qakvg+uGfg3wxyitD3unvvpm5kZ77ZLIOBMw\ncQtGEYZKmANTx9Q9XhyROfRZl6B7GtL8iAqiTMCJNJJk+YuxGEJ/ecidEPk/eZktrZeWHtezBqFb\nZgUD+ZT6vtNakzfJmj3+khHRE7cIBRpelxsClZ8Za6DMA3sK11zmp9xadXUia/SPUdsj9xQv36mf\nZmxB12V5QdWBqj7xiHBq3eZafTbxe+XxtUN2+4L571tiHtdV2UnupLex0oU85kIdGC8ntLFeO4W/\nV+0gDrR/qYOENvXl6UOdLpCXJrtKS72laqW/3AG2xrz2Hc773pXY8tEDPvS3P5Nmv6VpPpk8AonN\nIPwTTE5bVQF7wV7HQ+FSs6TCp+yKMx+ndo0BJ7JBHxqsXBRlm8eTHJv795pJ5uLJmxz0iZqtt9UC\n4Qn1iIvA+y3+BdhzxQAAcDoSxtc2ahfgl+OZj8yFJ2fwYCr7OLNIoY4VVzSgPQIPt511Ir51pjS+\n3kiJWYFf2BaUY2w3TY6yUzMzq0u9Cq8fxGxGzDkUOkC6HVZ/8lKI5CnN6o5k4fBNfy87Mc2QhwUD\nDqsZJPKqze7xDs6eGn2NAkH7Wmf3MwS82i8TeOKkUm4QOBqw0buWC/iyJXpTewmwHJUxPIy2vI6Z\n7/YSSjlyZIxQqylIsCJntaIbcZos4i/PDl7uz6yt54NWX430gfn/SSyGTNqKuE+2rBscwHI7MKIJ\nrdg9dMIDNg7J6ZcUd/7E+seiPQsilMvDMcisXNJdbrrb6rpmS7lT5hNsH2nZf/jmOnSgaAI07Ndi\nlbQ5wgamkOkGr2WRTqFLXNXHootRo+RlVOimybXSPRI4epKWjgfIdgKtHdfp6KnM1vjmI2k+asl8\n1PlKJLk1lCdIz+MKMVJceiwQwsPkrODGPUGC0jMNpIPlrRLBuBwg81Lzqi1Sz0gP1NzKUBXf6Hm5\nW8DIz2hUX8Y1iruchvWra9qjOvluQLWgIxxQ9cg47nxE9Gsjq/znC7GAbgCmqWOgLsoJVjj2SLnD\ntva1YRq7dr9ednhOzzNYvbU2HmTSMnXBsRqqpdQlmXdjYp4C8MUmB/l55G98nhW5DAW661IOjPLJ\nBdQ0Ura+HlMSg4OArj+m/rz20gLUh6pSzRkkLmJiVg/K77J0lu/AgF7c9xQwVw4+6bmqY6d6/tE0\neIhKgioSqcMLZtdpd04zMoNQZl2zMfs51vzQx/4a1RvCf3ggWpPOMas1mgiFdmNzg3jjIzJH+Tea\nClk3HebFmtU7J0Bq/7OCAyVZ8cO3iXVSrE3Wcjx3Uz3xeQ+jim5Pgm2VEPVou84Q+hpwzDV8B9S6\nRtpIv9b9XweEQF6SgwjLxAcxrrYCWT2TV22lYGWfIMxYHMJj/qz0dfzyu3dDx388gq+IdDaQ/UAA\nUObREta8u9eAQTuOlyycWlVW7VmagZom9TIVQGGNrbNWztsxQsQV6KtnkrYVgOyoMfLRFbwbAkcd\nJVl6Y8VAR34YDjnry+z0A/d0It0Ker8VDaZROxOIhfm4F7FaHRCvELj8xkcFKMs4NPiQUwxoA4Mm\nNTztrGAEkGOjfs7iJcSA7WDMsJdqtaBA1al+GsnBPbIXDCGpXr+FQS3usymqz3KNDCcfm3IdtojC\nVQx8edEv9WxZGOuY+o8wbkrzeXvrmUIyjTWEiADwa7fpizZj9E3bbe8mpdPRUxwshYlXusOIgxeR\nM6DCElwlng+9Ooz0qjsQjW80W05XHsAPFmfGIhcPExlefj8qMOcu2ja9CG/kSz7cvxvm6tbaszOD\nUCgG3kshMBD2GVqcJcT5vmpQErwEq7mjdXxKlsmNODnTL2s4fI44GB3rcvwJKsBDPfPujjmOsQ8X\nlVdZsLzJdZV08a7xuDqk5rKRd7PJ5+9TrHxhWzwGcR0u4M6MyhUMIcgLALNnc/4ShsQH9N40JZU2\n0wePKVoeNLuG0ojvgnCZjwvqiKz+2ltevhKFHncA3rARmUosnNpI+c5Wpej31HSfYcoAT4tjIQRg\nVqRfuMa2EED4wd5jaPcBvfBoEf558llVnrwyq/Y85N5+oI3ZnC03XhC1g7o4eo9m1bqwqKc2i5dZ\ntDzj8qfjoRRMg8eQZtu0SlFKRZrkC+OnznEwVNYnj7vVvE0zl1p1QeNnL/N0ubFSnRVWrUNYG6MW\nQhbFDgKIT9yDxm0elr0s2Ob83GBDVzdvV3gTbk6+hELIRih3uFDPPmUT7t/mmOdkbRejNIjF2WFa\nWdVa6F63N3cjZI//ylbyswJWEDfNvpOH5xHqSkdnreOcv4BWVoVdVlxP+c+54RIw2Ly012JM3L68\nEBCToj1EYY9c8Xyf//doLIRgr36MtpHUj6d753byLTEzM6HADMrqhNfUjosG89LjXpPUh66g/r3S\nw3LoMWtSLbDMsv82Q6WDeYb0gVqPVgI4pvovdMzhr8Gbn6nMeI0BzsweZkWJkX36iERcdt04NWOG\nEEM4abu95e3vnU0BzYHGBcMgwsWr2tMHsNRYzQQo69qS4UZoPJ1nxfYghtH0xv92TotwiKPsIFSu\nsITTMn/na93KUxmgNoutyyX/1u/opnfzvtwzBoA/5Goq3o56uacg2P1t/wcw9PUfxxnoZSla1w8L\nNJhE1Tb1VgwjBzhYGxqzB7F3OFQehMq/eTREZ+nJWq3mHlfafqUoMUbcBNNN4S6pott7TyY1qz7m\ntfED0+RCaCBY9Wme1p9ELglGHZNpGUmR1GxYLfiPmndWZrL3Zbx89V/K8K7FY9AjXLDsRtNWL2No\ncoEibeNAfYQeoLdmmVYiIInNIHwfei6D9Ygj1J3roBuH/VEnji0JOMPHvmxv6PHFNQMfMpXUsJ5X\nz9mQtXYIhd4Z1ctRA1f+UoJtrQFrqZJWzWM7i4Ltcu4/dWrFE9yxYX6OFqxWo5OcG1fgr5+EHiKt\nT1JZYI1bHFvFaBjpsGbFX8cvBR7adWvcRmsqO8ByvT2HVwMtuYm+bM2f2x9eSPPfa5Mvxg7XWtCX\nq4UeXqKcmLNm4PbIvjOINm/a8y2zEK3BUbe3PEs+pjYMVV+Z532mA0wpC9PBPGgEcSCtULR4wOW3\ni7j8iVw6NHhkn7Uv8qapqGbYihtb3ViNaTgHTjImcqfJBCsxnenjOF2025eQaEN/asTIt2uc1yJQ\nWGptO04udtOOd+7HTumubbMKd4a/j33AnIdy5XB0znsdKFPMF2r0E0o8BBp7X3P1y/GWvKjIZXyn\nYWcVJ46rKsu3NsfFQvDqRwGuG2AImaRPYAFAEcYn1Q5rcvAOM29d3Ynd5RkLnbdH/RtJIldp8EDv\nfFYPdrwXCJVUfsQeg/mrD4bmjfnND+YUrczyHY+GEiTV7GTiFReoJqUZuMveMYEWJDWZat3pwUG4\nZLElmizHeJtSyTvoDHHFDVHSzK+L37d6AF+FlGT6vzv6ZhacE3I1OSBGh7AqU4n91Ti1bTGj1pOd\nGqto2WyvgI3iwF+ixS2/OCRzpzmWlQXPuRK/Uphdg+mN+ujseQEb6gFnaDrbk2gN14royJaYLVA5\nQW2gC0UHkg/UqsNA1XaaNE5sqvSlw8n7gr2PQPBpha1k5MRnhn4xVJydtEYy4wP+t5Pf+ApjFGc8\nQyB4eHtgruNf1pqNE3P3F6ghV3/e8H0HEd4oBjwNqjmAND6ZrIan4fJ1YoIVcflHINVRfko6LTXI\n/0MGg7myDwnsPmxq11sKm4G5yTL7ZdKBeJeUva0V9lTNwjC8waYk9b9HLODGzT7H+EEu8i1MpB8A\nLzAKlFIfOP1dIEC/w9vqkwAbeQg/4XAZvj9Vo2SKv4YPLXC/LsDHhp/YI3U2GJe/3YV486twcTMa\n4vh4vsM/5R7v/Mg/uUaPgR4+3QbqsRS8tBFsnMcChH57WZGe5W6Bs6NYSncjKwP1pa6+YI4fi5dY\nlV1Sf0I6ge8rKCZT4P8hOutC51J3szGldpOmM641TzCcDSTaCOlRtqEJMGFp9zdDfgFtkBJA1N2H\npcmSyh4ucpUuJvKnp8bsdIaL2j+wzfAyntUy27DDML33g9is9VMcTHEpeMp1tSzP1ryXaX31tGVY\nwAdGVD9DorAH/ggL0zWy02jeoNVkROI9OwaQlT1/uQ7o5HXTirc85rblol72Y8f/6JCZ5sOjwqXV\nlismVF1kfhUTgI97M6Z05WchktRqUomPk3IJYeISUZgqyEh+41JrK5M+ABafM47G30ESnc+ZXLSd\nZOHlf4LioerbEntF9PnPHtOXhFljQBm4+Ro9z+sS6E5hVO7kQgsx10tYEs3eHSQpUDJUW8qGMtb9\nFjCJ0/ZpXxOc/K5XuxsbX7Dm6GEe2mE1dasonVWO2btn+zLnqE4DNlRcrvtdzBPE5TkAqLZQukn3\nCMf0dW4AUwm63J6pkLj2p9czXX+8b2sfAI8hLoeW7KqiHkWeYUMXfvNM5iF24umbsUYzG8KgEZAl\nBTJJ/WemG2TA8vL8Ti/UFokUpTldg7lxCb1jWqomNTRdX2EgUIxaxWPAOMwYsyS8L+q3tWNetBFd\nQ9NclBmzhCnLypYc0sgObu1j00L0W15+v6LQUqHZas1++xHhPN3uHdzSPt8IN1N+E9CxKACLCe+k\nuYwkje2Qz96yl4PHGBRFHLBbgrBDq3UfiiaLYYEuI7nRm6+zUZxf587eltSUTwHuT7lGda9XcdDs\n/rRC2B50VQ75101MWSvuszZLyZOaA4Nn76jze2Er05mKCozTPwTSQm19hNxrnmB73mlRTe9wVxVD\n3Q3Qj41B1kXXO2bdGyaNLmzxqrkc+5N9obPOLkkJJJZmVZVSktmgB3CqD1iKiu6wWXHZ/5FuPPjj\nfTq0eVdzM1BxfHcL23jjPgHsnGGw2ih2BStaz/aujJL5S80EFxdNbCSPTa6/CSri5gylOCmiOLq2\nG8duHJzgEvcPePEqsugDyZqUCV+WY5n7kl+iM0oTuqwK1nnwLAe6HhoZ36TxFhA/8ZXiKALZDQlB\nbCppP00pBhB6Q+qEFSPa28f5PgSTY8Sr9fMcnjHv3dOXfHHoljWaJjPZBMw7sfoqR1n0suLSoJtL\n9o3Iq61DDYwiteYnKospxn3UiJVXgmkBNFPrB1A2HWMy0J+4WGyhAZyZyr4ig0EI2fnav4/VPAge\n1Lem/a2XvlGSJd2aBSpPlqQOlFEgL9TLwjm0CgrBMJowE7nUFmDBPalvGE0/qalz9yuwWN6XYg5q\nVWMwyXsiNhK06otMRsewPpuLcZDdznh1V5OTFeI0bqfhDMXLhb5w7rRdBMwdewayhCp5qeqBkIAx\ntV7tDXl7hfPT3MrCfkHDq5BBJn+zNEs3o94mUbv92AGposo0CbrBdWGc+m4XMQaYA8zKV8KUSTg8\nY1cLvjZLdJroijWxg113aLKzebZCwN/vEjd4xkzXb5iP8u1XPDaWwb/kaKcYmgZhFun5mGb/bVJC\n5xPG0HLYX9XQfMIP6iKigvntJS422yepgIkHDukDLrhuRfmmo50qNpNNSzYeK7PxgWIbYRSCfS/t\nM6zIGPvG2NCMN3A93nI8btAmdK6+btSZ+csVQYUnBK32nvnuhft9ilakW+LHkKcaElYLEdcbjO5y\nNRTBNSwQlqEv5hJ/bczg0H8XwuZvo23epPf5WY1I7yuqMq6WutwQxapNUVDz8AyTwEGdFevgqjzk\nm5aSIRs8E1VJ80zrSFxaRl7hDsFFJd6bfHqEB9EEeYyYTKC3Gmyaxj/nqOapAlD1VwtWnFU15f62\nSMswXCyiIDJiSR2bI7eIZ8k4VsqiXyZidBm6bsHjWKBLPWgb7Ja5B1/5x63xJd9c/ZHoZeke1CJB\n0umguzRJmqqhjwqmBw4wY4C1zPAemJ04Zf8ct4Z2JAeleYYLOvNTHul5KfK4h/ZFKMjWpFTVJ/RB\nsxM4OAT0HBktqO8TimRCgIWDCV+I/4LjwtGasjeLeX2TW+26YStTSsrA2nupMO8fu7BXaHLZoNHw\nOHkWFU/DxoQyxAcTMKJ+W0WOOcqv1qtyB9EvwyMMemZNULY6LD47pM1aLCmuka7t1zbCfZ91bKp7\n6pvFbnMO0VGrM4lGG/79eDbXBdv7oAW5wZxgMXpGq9x+N8YKQTVwGBRwd2XXWEJ2jF7q2b5IFxom\n6uV4YQBQBIt1RMJZ6CEHLshpbC6/G1WUlIArGhc7bLLaLzSyZAx3EEqJFYbro9XHkggL26Piv7wM\nYI8gxbrL0PzHImHdp302Bu/1DPieKEPY9uU3Csc0lgGq+clPvdx6R79R2kVUWUx2XJInCuafzTyL\nSq7ZN6HwBt3vJiWYDakrFBZVfB/vCTG0bUQSlYmU1VG/H20JjaaaMaBZsNMGba1lynPs702O19uA\n/YF+Zpzp+Q0a8VMQidIkP1tEi+PUjbZCtmYrc9QJ5SXGIclkDaimSSB3vltyn5yDeNsUapiIXUXU\n48spzVPvvdXRdi/kxoj3nfwnuXnp+yfMCBmr0g8oo5URSmRoghVbJ8IteI2jBLml0oQcqjD+Uwhf\nv1VPFOT7HWn2L8Xnuwbbc89nQGADtHvFUSrqGtxBRJQez+70zpVR5cQYrG+tS1E1/e4TCZWu7T3m\n/PzIl7sXXSkIWigLd7x3iOJPSCPMfWmDp3kOxa7b3Zdsh3qEiOg9IT7vQLeSzH5ZY/9yqLQ+71XE\nc9t4ZORugfkzW3dxb/xzEqPyMjiB98VA6u/PdOdKYbZ0caL1EyLaLdJNkq9MUsYsPwi7M092eB9p\nXKdVoBoqxfpvOl+Ti16TLH5fIXqknqHC1Od5Vb8oEsb/XaIUgUa2hVyOV8EcZbEZ5BPGh3RG4D5w\n8AsfxBBqReb8lHiC+QBBwyowZ4QUt1zKoKla7VzGITLo+HB/Sr9QPYtaeiE0Qnf0YWb6793RpsGf\nFdkgTf9y8GjS0UFubmB3oWARB1L0rnLDylAfke3Ae/FZGTZQ8zAaavf3UK3lNOA9zNztl8nPpxhH\n7Iv0vBSKyDPOOd8Ot+vkgBvO3w/vQWu1YwOHXX5JzLLWyzpBrQf7ryKXZOr+ciaaF5utiMELvRzp\n10vsy/bFLGcHmTSq95llxxvB587OdpEMTsUPU6F823khuBgvdo3boasRcQhu87rZdvPfUC/DGWYJ\no5dieoiVN0CcZ1kBj94QwvTFGmg947xdyYkyfrTFMGir5HAlN6mEFxChrfhFlT1yd89jsrscpHRB\nZkQX289xXCSSuRRzOZ0j6Dr02mRxyOd56Wd18kATxxrNDJAERpV/q5nr7Mks3FZ5e9RJUS+OwBVZ\nS84S4geFxVGY+xAXBIM/OyAW3HWWqOt3k5u4/txxEJaFfGY4Z3u56IgmY5rZh53Z57NODLJO5ziY\nRrjmX7Sbk7J8iBmMkG/hFfIMOhGAf0sZpaCOz5daT9ZHlFY8Ex+Ea2PgdzR+4Yt346ignisxpjbB\n9qnsY5WeOVuToR9aougCxRtEPWernjJDNcNoeMV1zAXKNTyxs1g3yhnSeKAXv7cY3KIKJ3SB9J63\nAaIBtUv0fwuiDafashLpZvSSCKfOeNHZZn2PKV8aT4l1ehhAM0NW87FAYWcwwVRrdixL14SDLPfF\naaiCrbWWUUNsvuW8EN5/o/5TmtqbI1uXxqFjVVgcd4V7eC0URNzXYM8nmNCgDmfZqsqoRmlcyBmv\nt/o8EGDE/vU0zc6lAHB0IfwK/SXh1qloqFQ/Fhk2YpO+pH65vxucYu17PR+Qqb5TrhK4eQhrEe0m\nmKl167CtC0AoEVQY0MWnMhZqV+8ba1T6n8+1s0bOlwlNEBsl2TCvfyPA8aqEo0lQfandeL2A9qGR\nhqh0QWhIzQSdGFD/xyJInTE+GG4GpW7l6zc2KRLRSKz+/JqOmAajjhkt4I9abKB2I6rW1KdLmSG2\n6KpANt9kFY+/Keulqlgkw1f/W0Pn52QcxpBlMEhBZt5lBIgCsjBtkjkHY/tRKZ3HwjZgpEKLn8o8\nvyF4R104Ew5Sv5pOEZaFZOiR6aGAuEUErVJp7gce1olb80v96UTCUAaaXKltfXr9U7fM3Q20+fM7\nUNz8uNMjHmJDXkX9Q2eyMGACCrpcg2y+GHo6tWLY7lg8gf5F/r2YzfMr2zcuPJUDQMb7lCpoMNkg\n7vxYLbdRubnYk+eBgzIpZ0uTqe2JrW3g8FsqE5aPLiuNW0CBt19FH63mtJvEgWD6c0ojXmzCIiO1\n2HgCJfz0Mygk2TI1FFqI4fXPioRQ442R2hjwNCamaLd82gRGwJCa8eWauAQu8/av7xvi44eVInOy\nJimShS559TpV9nrQLQVjhmttrHMjt/NZlHii4OHmMSgOWDWbnBArTijVD/OnOAV7WrJ8FezY82ts\n2+nHzlTaO5rX2V0hvLFX42efoLHGgeqXcURAFuy+U5x4dKBK6jReKsCsbD6fmzzE5sZWn24hOHUN\n8e2201KhO/JA356IeqNZIPDKdgyCknrSubEspwL602LD7qV3hkAr6/cQd1IKYkbT04ECARWaO9+e\nX5p657kzL/EkOCiN2+3GLcNqqZfSbflvqSwTmF2yPKBlHKHiaMz7r9dtlbTvloe9RYDxk9jEem3f\nzhBB4zS9fb3O5znOw8f6M3Ya4sTDTCjszF2+Xx+ow4Bf0GUNuRu3A0esuUSvCCIUyoHgLz87Qi9y\n4SYxqdrVEoSw3lIuTEdLhgkTI1ipqQeJ5rbI6MkM8Bq++o5vr4apXcUEO8Icu4Cn5wEa3txC9oIv\nK8lvA/3FqeHzK177L55YfqAsuzqWSbB3xzodX/1L7RvBWLwSsYR38XFQ13LTg0ov0f6D2W32G1TK\n9sSlAGcm5ROWyMG/LY/2dGzFAtX1bAOCKEdW9juc0Ks/bcslEZJsLFCpLwb57PRiqmPTVLz9Knmx\n3AR9M+GYDDbdpRB68/y5ACEQR5cLhTiLSyjipH9zZrC63Cvx5iy2JKHho5RXPyja3g35PjRsP01k\njSf9N37euNSFjHHrwCOze4b7dPTlsehCrcZg2VvsA6YKmXflk4F+JUFjlW0Y54ElnS+PZzxYYUoX\nzBBsCuacZs7iXSTdMPsvTZo5JjqE1njALFKKJwjO3c3B0GxaPeN8BltrT91EdWC+3TU4TEAGF3UK\nhPmoI0TTb2ccHru57HF0OwxC/k+7ytb/85S/J4cVu4kFaiZVEZQtSv6Y1iqhTbN63oAHC2mzyb4g\n2ADTUxc286GL2Fht4l4GpO2B8HsYlBRsTMDeZhpf4bag2wXLA9J5I5IAhgUQ0zDWsqbYQ8sB/u1W\n/zeNw2H8IYZeTNHylybqWMufAa4rJ4s8ml1avztNxEnztJnS2yEXdjC5rnY8dClEMRh8N3dTndmy\n1e4Hg21kEy/DViXNfaFUkWNsXVh2m/ZZDyXVNP0TSkpmeTxnlclUhjnxpJnDEpkz+aIvjW5Uj2fv\nPiQ5FYJPbUQTJ4CE7anlukiyLFSfPV1u/rEGKR0Pos4ds1GskM1kVoRUxDCwIlKezEgmF9Ejo/p+\n9XsmpLNGq/ISKlaaS3EyXtSpKTsBPVzVfwzcEB+VcKsm6QdivP4JwUYLUiP0PpjMZbYjHP9umMsH\nZY6t4xhEboI6isGdvw7gpvEckuc5FSHUPEcHSr7Y2Y5JFQ9l8FkCLM8P8yvrgES1Ki1CCK/Z99Pm\njQRjoWl8eXrHi6OnuXW/X8P/PDATE6sVk9Ihi3qfvyoBRm8QAb8NeBEfFUkVvUAJlge8+0U9zrGD\nd9+ut50qdP1rvJ0XveI2mH+RK/Z3BFMxGMnzgoGhpkXuu5S0IQtBBE6X1WdUnOk1Y/ppHBYxSIZw\n+fZ2ACUKnx6QkEmvlcL0JerEFJjDGdxAw160CqyMD93HDdzQu3az5Ew5N23J6Sh/CnbNe4egLh0m\nKiYglHk2j3rsL/veS4zk/pnCQ+G7JWYIqIz+/gw2SFjOLWH2Elw/TcKeatubX9Rkgc6f0dVFZrmg\nUk4Vj+sihQQQkkLOKxiv9iSj2Cvc+YsHUA18y6uAs34MzkREUxMvof3C2mf9jzicX75Ksc0/JQxJ\n1B4ba7QsQc3IohCFgT/VZY9NOVbk1Uyp7MxMePjB1GTy4mhxhRy88flxCxJ56OsGO2LTGSXmgu+8\n3jbMFCEnwt+iMAPEKWdErklzsFFA4+7RDJczsGmJY9Sumg8cMGMCtXegk+hYEXRmMcEECk5SeNfp\nymGYbArKZNuVmOGpCL9Pv4we3qGPPEGpQQzV8iYRn1aHZC1EMRAFFgdIUKB2g2vcHISjIO9WtEYw\n4+u0VrLYot7bbPSwNbjWQWbKVe0CMruhemMmEtoNSZGW7HLU6qKvsIAoeAePXh7+1UO9UhA5ICTE\n2EAPqeABYkIKsjiAf+qBtckjDf9gfHydhsF1xvTBNwX9zhSRiW141uZcVawbx8wUKQtO0WaG46KU\nsGK1yVApZTw8+QNEJUXK1ZI9L6rPPh5t6bwNqfk5WpXw+Fc+bS2ZRgpJ9WFaQSplgHrGcvFbwLyq\nWeY5R3NYAgwOBuPwOJXB3FnSdskIEHrLQ0PjCbrNjFeAy5RDxv7tG5nAWLZVGcLNdHFK4+YnSF1K\nMtX+r6RCpc57j9UvXa+bis4d73rAi4pm33+sD+FnyDGjDelTsUYkTFc9WLc/kl24MjnuU3Ye5m7L\nXTukBRH0N5DXaHNFT1jWkZzRmVsQaXUcBE2cDpAcZS7NDIh56TZcnsXKeYcBw75wgVhC1iRQHCH9\n45TAQhtCSKwKskBm/YngRYDWOYB/nFYaxUTVRoDkpghgMr8tzFp4vyOc4r3AX9oFsRquKFba7sxR\nAk0w3BRCMrpAECOVm/te+5IG6U9klpt9WRms/21amjqPqnpCu4CB2F4dnQarPbzzRHF6+7IIJHEn\nwP7ovbyfQJoc1LZh0jZuftlNWgZsNHJJD4lmVph7nx7GnJCu6L4cIubkQsXeX3dTdneIUXeGKZPq\n6pgB6rQ2hAglNLuhv2xkdQqSWHlPOQtYihPaOuAiJ0uzhX3z2Sp6TPbyzYWReirYG9NK7Nl3Fi0M\nJV/KaNYv9rNhK399cRCjDG/t3ixxYms5EZn4FMIRBM4IWHeppZCkaSbgHPmv/FJHC/xtCGu+JvaE\nR6sB6h2Idj7M4fxlVzcyl38rgg/PGErJO3scMvekl0sTmNGDnF0Cbu9D8VqajvC5WsqZwOECPk14\nFrat3yRFE5WSQiuOicKmJMEQa0189PGn7AsB6AfaP4lY8WV5edml9+n8Qwqg5sfzkkcMDOe6aTdw\nNjnfo7hQ4CaZiCtNakMtWb1mOwppUz9hQEJyKmeKFH/nvtieDa2QeDK1JtIHg9HjwmIXp3ZvqsIx\nL1H159iz/Il1IKzBzD6Q1fURui2Iy9EWNRBSYto88Knzan83mxIzuGY67KcjjYlzmDxome1G5OQi\nzz3PoYteVhT2oMtbn0RoF0ANHLsfyShPeCuwWIVKMpuMuc82QF12lqgq84SbFOmcbzL9yQekhPdv\nxPgdHr6td5yfNabqLra6JdLYHwnSqruSo9yNIwJM89MiOs25DuTSEjnv+ubtmssnHS/BR2mZ+Eno\n7R5XzBei7ZrR3DRdyZhtQ9U4fHOKrByzf7SJUwf2RFleLnJ5euKvpOFDaPBtE6x5nFRi0JYZIqrl\ndYLec5/7Niuuczu0Q1ksMqZCyDCHOf30BSvQcCF6fiy8lUW1imvmm2FlNNRgDlKKegSfw8r916wk\nDrbqgo+OdWXdWzWbUTEF+A0TQ75RMXSN7diLvdOByDglgtxiNS+3ozib8FIhgPVKO3n4a95gKbcr\n2DU+rkFa0wEMwLlJl+GRwdiS02K7NpDAd4/nYvzbpIOlTE7nD3H7JzN82hmdBsSLMHXZlvyRlEqd\nxlPH/kirtiEi5hNOOMlXfke5FdhqoewyLmY3R5CLUgo6dv4hqV1+0wMBFchu4vL9lKJ/xAexD4mv\nYtxkrypGWNSrO6cbIvI0IkS4iuHmBv5rTofeiuUxdV8QoecwNfVHXymO82uILfuDRkqc57kWVs6i\nD6+bVnIESLWR9RZPv067rBZu/jVDtmp3WlAET6ilj/jUNxmUx4HlaDNEwjMlx49CZn7mgYnSVxAU\nVnsPTEnwDw4sE1mXhtb46Q/iv6qOrWtDZUTD0RRwLlyGoPM1XNhQR0iH5ehckaYeydsKjuNws+hl\nCq9InX4lU0wIKu83yfsoQz9Ooxg2MJwpd3AzHlojGpaCb+HTpXpyttG1RmdG9yZTQ0duUXVMRxD/\n6j463QiynKuJAnJGSbyKf03IZuT21HVEYj7vguJHe+aYtrUH1J5wgZP98heo/8E+RvRGRGvopd91\nZ6zZlaHB76Ok+AQbpNEm9h8Fk0jIrUJIlXMkowERRb1hNF80ulEnGsmcSnGccWT4UBamtoHCZj2l\n9RnYzS8wTUUYoXMT9Fnwy7EPhp5y4W0SewHX1vbr3FWIB+1vmqPuzKvqwDCPhrj55Q4zqjs0Zl4x\n6oc8CuKBEENTp7wYtzMGBDelWU9l6+6GL4+4GLtqiyuRLzS7GUWEhmSnsOlzcFDdLjHhUHmF4zBC\nlQAHd64jlQDuM2Q+7Fwls+KzEKTwX1E8P7M7d8HDCnC1ChOkVvyPPhLTZF3IMHmz7KBVjt7dr+ot\nzuw6GC1ef1fibVamX5zzTQa+K6YxovZzka3o3YgfDEjaLV5re/8OIRpSvwkmlF/cvo0EHcwcnENm\nK4KFbRZWE6JTmasr6edEsr11B/dczuIXYDsQ/1EtNNI3xAYDwfYrhhsuAD3rybtFp9pT8WfGk+gF\n6CRcXa3JSgY4KmeaeZXT9GZaSxUWE2AckNn5fivGdeA881YX5lDxFXIx0MtWnaXIgx1+c05/B7C9\nkvFH9tKSTcwfLKJV+LnSLzTRU8Y+H1TBSO1S+2cTr1yoe6+WSdDptUywh4H5zpVmpQ6Hj1C9gb7Z\njx0wF1Z+w/5qTqyT60q38Lb8gNygeqz9P33dUL+JIyWe6f/7+bs/5z0z6/9sJ8FHJraZWyQcIHtk\nzo+TYOSTT9Hmgkxz+uAkHNn00BwG19UIx1t7FJUR/9fsjScoNVjqvnijdWgwVDmU8X0F/Ou0u6ZI\n7yDH+TLTVGTjV5yD6DERCmbxNRHIuKid8fVFpTAwRjh8sLkQti/0l7wMpch3O/tGV3hrrZo5U0ab\nUK96P32ysp/yS0bdh9IrYsxujDUk0oBmvEhx1/0SpivoiKctoAUm+i6Who/7mHADQZfN2IWjibUh\nK5ULPKV/+edFYDhw9RqqRdLeOfYZsFUrcGSxnklb8q/SdDDIwbZieu3SjOb+IiaOPpsPNx1q4Pb8\ndwIWO+LQYaPlDmdeqkw4bYd+Qi3OOX+Zr3CoDk8s5wUuLG1hI/MFAWpveCYK3RWPtscdZanWdBO8\nQAn43BzKDF9ohALRT0M2XNzOYlkXm91ibjCd25dJx/VBxpyW55yykQX2No0OckCrUKWcSLAIahIz\nr53xw/QO1JUBaORAFhpXYPfynza0tO5m9MJGIqMo0WuEYo1clxliRwBgk3uXXyaDgZmN+JVuBuyr\nt5zf0FO3mzpLarXlGpR3I9Er4BtcNfEiJDqcm+3J+sqyzb7j6gpWMq0gbCw3XTBd5/i0wLGGkhti\nntqYVjxqdIuZ8qRJvHt42zX6isoFlpEpzdkOcnSLmZvEY2a9LpxkV5RijeSHNUzxxXNjxeprDaS4\nraCM62uTYMRGaSM6hsODPL5mxntKGVwNTZ8fHYULZcM6h6qb3jDPXNRGhbtIs2rMIoa9332qPE5c\nnYhSAVeyGdd/wyf4CveOsoAmVSCWRpL8GFNeh1kijFrnIOVymEQHfWWwpXXrz2O2od+VqIAIK+Kt\nOYomztz75CcF33HbGfHIuWRbKpYyMrkLpSZgKUlL7uUgavEYnlKQ4vVQYrGBiDeI/ZDN5zXwC6o3\nYt+/FCVs5AH6X0IMlNA7/5t7emm1juZGzkSY2A5n35RLt99Dcj3ARQJjykhIcdGREsUN7CF100k1\nIVMnFDW0fvXGwxZVSDAqeHxNpaqdhN/CSl+vshh4/uMZP+MNqb4vCTb5m2WI/JgFh7sz5zQhWF7l\n9lghNDrsLcOL/BDnHIUPNaSQFY81ijkfjXNQnv8E599pYburXifzdgs83KYpkbIvjlz155PM6EQa\nODWQwd1T1QPwE8VO1mh9TTOTbZFBML5EmEER5LiG7BIriw3Wu+VYj5wzo/OoBC568et+6BUpaXfP\nz1sdJcF7NZ8CZLS6AWYU/fu/jjscbDY40Xs+p3OsrVXov7HRcZ9Zwp94gCJ0n1EAiA8IJimBLZl2\n7Hmxr/2yGBLse++bVq7tBmjwoq8xBo5Ca5w12z3It3SSh+xJmWj7JSwsT1QrQWxNZuHs46UO1W4F\nPJbveW+mEGJ+IpBdizhKyWQBtV1zoeAE6wFEM899EY9J3xT+nKyybHEkTSnOiSRfisgfo/WOt575\nCWijnC016FPTevpFEa9ah0NqcLZCQqN6mzkSRxjt132925ecEoweSRIQNvclpQuiNFw9VwfZBkkQ\nbLg4DE2rXxIgSmR0+d4JuHSYz3pCerm8CXk2UEazX64gocViefZYoX96BySYxyzxhNYbRvpG37d1\n8qc7Cz0mgg/dGQ4459CyjILJpkjbsqjhg9JMke9740/IB/nDmBzjIWuKe5xFpUJWAcmHGOMt/zyz\ns/TkWfzZFBkFusiR629XCSD6ebwhFMk2nHH7THKr9tXDP9vK75ZpuoM7DRLt5TER4elTh0nbAZLJ\npmm649PKvjx7/bBJQiziNVvLVdMxd/vhMjdJ1d8f7gKqUWPbbzli/Aoy1PYbUtDVSE/YGYVM28pz\nowyzG39okYAl4gEEbRVBauK0U5Tx6DhKOp30/8ZkQSzfTH4FxGZIBYjETmHN4K+ON0ClYxhVOcRE\ngZAPooEUcylE4zxfQViH4Evnngf/I3xb6/6Ne4N4sT6jS3ZGE+8A8l+C6srAtjbC/7xXpmMA0Pdu\n7gQ7lqOBj+vnN8mt1eayn7RPemzewKRlfAm7gHTfHIkdqw4H42DOMo0sBWW6bEvnBAW1hI9we5nV\nz5ccx7q2Qvt85gZb7X3ZdhjVM0PjLvDfywC8Gp1gtN4HCBoTAjjM+gU/Nd61VCBPXX1i5WtOQG8l\n4gzlhGhUDQ8KmDhMiANC0/8w0cbR2erFu6aSMaEhxyJp9IzcGjOPBrnPhIwb3GQslpbNK5woAdEg\ngJeHtzAAbou8lMZYuFJqsbFgJms5BVTPLiqzc+go8C/lJER1yvkLmmEs55k64Wylh1kj1TzeoNLl\nHO8cglxiEvdjTrZiBTMWhHFckrLgmitNndQYY9HUM3r03kLEpPBVpZEhhYTV2r/yzguhvmvTOlRG\n/vBUIZwpWRm8qTgg1qCGvWj0nTuivraq1fxXrkyTefnq1gwO2o3asVpLaXU/MZNW13jTR8JTvnJj\nfmktsrgB9VirxbPwtNxR/FwQXx9+Yff4p4ljmlPBDMuz8LyUlFb3rasfziWrXjd10JKHhAH30ES3\nbwWbWTSxCRA9jxBRuUe9x/DicnrtBaPNdR/j3F5HJiG9iF5VJFHTsXoMjUUyGuVORfQp/Nn91nzU\nMqG+9tAYIyCY8YX86G8efx4D0s+OO8Z0RAroPva3a5/Deeghbct9Wxw4MqegDl8d5gcaeHGntzDz\n8ht6bWz/b3FR0FdGV9l+8Dbk4vDcLWOxWoJGiVR0gOTC5y+l2PT4CKdHlX6dbNQvhhQLajSBCimH\nqYmI+WYPqWcnh++DzCdZYcJNpwnHHgiFbqnL1j8+5zlC9hUCdxTf4MHIgkaLgMDDfkQsohwVdfr6\nDzsKjby3bj/sEAs0gvNX5fUkBHhKDQa/Rw8EhfRWfrWYQuAXOCyQo6Jyx+IQf6aVNDM1cq2nPPEQ\nMNYXgmdvOmjMgWDAhnCt41X2eMCMqV8nOce1bmAli8juO2hCpGUxcSbawnWzkUC2DJqTrvf86FKo\nzB8aB83upkuagOovIxTNnEm5nTPtcml0ixutpb2o7A7Lt8z7sOmHyHqjHDDXvdDCOuWRkCvFDJz1\nA2AyH/tL2dEFv6t+0ZS33fqBBxVUUINIWXxn4R5lB+zoB9lZT9WmNmat99MHyTvAkw1utUW8lPtG\n8duL075FXU2kE2mQuGsRwjow7qWLA9PTPwwsKyZIrtkAHAKYtdGCe/2hXKoe4EXzAUDMCgNkDwnw\nrzMMC84yDx7qKFdYtyGlDNzlB7m7AeoxkdRIsVbqTNurhGV9S6FIWqS0Nxpy9tmPDRvY2BFBFi15\nhYQE+AvUwEJqHoJ5Uj/T2tF/I1kN4nJNbRcMpTNODRCox8A+PpsdC5ORxvohAO4mUK0ERCQWmscf\n5kfU0AdRhqDzwcfrY++3ch5Nmx9dY/AsVfxnUogZWLw2gKc/yn8FFOVpFmyMcFRL8xZKGNfkDMzV\n4u0DM3ez/GhPVjhhpScLbIhaY6NAamjdN83B5exoTDcKW3c6FRNR3AdXGWnw5GRVXXwB0PzZA8a7\ndhuWzwLgADFtXRnOhVaEQdbIonB7QTUvYgmLRPAVnoSkBsXavt+TyEtPoYH0b5IXDyVlyWleD0cc\nBxi49IeblyjMrUriNgxUebBTpuqJplKO0y/pjW6Is72csjEmYwIcqoPQ8svOtZEP3y0xoGEQ6aQv\nlU+GRloWJNN/1sWGP7i3GwjEJjNCP13MZN0PbuB5xuUmrHZjPHmLt0KhVTbyx6zWQK3mZ3mMU68+\ne7045AYMB1Yv5hP8l7/qbGHBvzcGWowUhaqx1vw9RbiPGoAjE4Wu4Eb1QRvzj95S3ucFnMxNE8XE\nEUnjgGBYJ7JNHqAoo+7bxv52POlLmhb0nWjo8tRe+Rjep1NgbtR194/rqD45XUlEHDnmBjIzRlAz\nePVGSK4Bi4EiYvmp3zeUp7pM9iRCcQfMQTSuG/EZ70sPf4iUn+J2tpA1sMF66Xn3abKorFeC8Kz9\nO6sv0USIA4cZcZtbNg34RPKbclC6TSp+0ln4RuMTGF1wAqpwT5rhy6FML/G1wHZdplnnE6cu6IpU\n7A7h8tW4Vu750k3LasiBLNxVf/4RYA1uHrWV6c68lbkU6ebmLf6gGsfsDiL41AnlFkRzmxrqWsAo\nP0iQFhRCHCZZpkpyKjjna1kVY0TcCtUrK2HZAMTJTaIYfecTvMomKPDn1FmUo5SBkStZ+5yF5TWA\nnZPLdXzolzXtYisekMlxP22Uoyzg5b3MD0mhVTgkvVu/LL4ikU5tzjc/qiTPF8mSzLrcb8fhpvdd\nnDfExIDdglqaLUa1flcz7FnxnSzFcckd0VZo9ega6XsYvSnu69LamNqTUtpkAagJI0W/r+CA7HH1\nvSDxvmJOUa4gE/8iK8AhjCh/rGjl9EVuMeHcx74teEA+ZDMJpVjrwiBUl2hzcFoeJvuZcIQ6RyPE\nF1DX6GlG0fg4sNTMmxUMjhim53SYx2BAT1X1G51yscz9f7BUqu58zCWAWnW98DJdpS7VzsowAgii\nY28qychfJt55I2T+5jzKrYORbY3u4HLLwmwCjnNM3cZyhEiOSnWXfb2LTTCD6AVrWG9R11g5LPNL\nq/eAf5sjD2zSWAJBiwfmwpjjPIlMuCfFwIA7g1uYqaxEbDAy5pPy5SGiqinDvs7IN2QkquKRqzak\ntlIKbgp4T3/DMPNY+KXDza4PZ9tSmLYe+vi72MZBximMhLD72J/jKKFIjZ6Az3pb/I57Sy1e/H5g\n9EHXS+vZy9n2+ocH/M7xVGnfvCn+MIYd93o4MUXmGrYF+0XMsDsfbF7LcRpLxDzWHv4qBz55xeDa\nH+mThSKs5PBSKo8XOVs8Envxjw2tk7CPK5qqQvidu7KnQ9dfJCUaqr2v3muXdu4QosVGx0T0tmDa\n7C0Z0cRrAhgbXjOCS0KUYacnthTLCCr6rJM/tgpn+4YmpI2BIOMTURwbs42m3l50K5knlY9UgEy9\n4jiKgcemI7NefkYCfbIzKvjZKmxBu9Ko92I0+JWnBeViGe29MObJbx2hOGBUXTCSvSwcazUjURx5\nMgyYUlrwINyMnCOjJfCpCzwLIPVzPMcOv5zFf4b0KtwRX3jHxT8k8lAX5LT1bpvQyzPy+FzXQEvf\nBgTytQhYNz6+1KTmOVE5b9hN9Psfjq7FD7jWRlHcWr2/SJi0gqj6IznAEwENrXC2DWFxFzw+98ss\nGQKWeEQguxxh5JW9orNCV/sbRllG99cPyUENi6j1I53uU3dFLjrBEPpEzGkzX4p2dR2Ud0K9975m\nngwUPCuCFNY5K6g4HQLnT0LRWuKx7JG2Bx0TtLuimPs1eeQddraHU3a9f9mbT6mFLS6g5O4ejed5\n++HvB5QmzVJ7SVhLm6ooznYxyW51JjAQFj/RJRkEp00LtQBI0OT5B79jDbYopQOZJUvar+3sbY6d\nFrInGqCTBgbGrtpXM2InxTb3+OKpPFaqj5ewC8KVhuXzNYK2L1TIJSAN3rRRgu21unC5Ap1wBiuC\nz5Y58eUrc2N+cjUX0dhZk3rGhvnvgLcQo/iSQ3TgoPMidkAFrZc2v7aARvez1VQgk5ubhpfwODnx\n/aU7CDrrr7DibJJ3NHbwk5c+9sB/WMnbhDYtQ4+d1+L/BlyCGtq4JdfOkP5k2NYv/F0kOIuu86q0\nel1cSq9j32Hp7n57LPWGOS2FdYQGXirj6OSOMWUUFc1GompQ4pIoIJw3L89Hwrcahq4BCLIdRNx6\nH6l05WC+fUkIVTUpJEw5TGlH2zVjbmWcnbQLV/p2s4kHVHShkRGd0eLxW8FqYotJtM4w2Kd8cm1c\nbpBreY0A5qhhpkOGaTvnH7zOEKWriM6rPgvEQl4/6HH8z2CHx2y2nmHrM46n2kWbAWXwr8i60K8P\nOd2khR3DgXzRkHTqB7w5Vp6Vich/ePg7oMLjrSzkraU0ZPNAofguTGkU15Kha9Y1FzQ2gk0O8Kh2\naR/GogMyZ9n/uxIMDaG9Yp4xruB609qDPqi+qV43mgr2mgOQbh9lDcfVxZS37FWzQPhSeJJTweiE\nOLcyUhQkt6G+XvZTsR1BIkcIRYXL+XLaWCWmddhBO5U9gi5p0TUELsPRc1WOYGfaR+IlLo9/RSnO\npH8OUOF2fFNWQ2bY4bJwxPsqq3QoL8zk/ba912zRdLDMeyEHGOGGmkfVHNp5ueJ+/pQ3huDdrisZ\ncFJnHo3G+oNgjiDNtcMEFSo/i10h2fKhYFpGHPPURYcAoIqEfdmbgGqtF/+2ZP6yw5EAbRgNdpau\nHh+GeI3EdZflAd6J0I0lqUHKcf3cx6vZhMjTqtgVO+aRYsKlibgXBzdiSyP6Vlo/Xg/uxMJEu1Hr\nPLgLIZpbOsQExvaRyP+sClndhX6Ut2F1PK2FgRlrLyy0lsPeGsLej8hwCOrGRFYfFJylSvaZjH9k\n3L8afEvPG/zfxxIQsT0mwCGo+t80fHPRA+u8bip4nObtkgGindmsbNf1Z/uJvx6PwKfv0h3FT9ea\nZanl1zpU6yvrqJCDc6O+u4fOZ7yyAcSrez0ypnVz0vsKL6lESkXj+xCh1RXMjEiBlL/BlASWsuQI\nq00C0TngE//Fy2PTyNMTtqvyQq7XDeJc19OhI7xF/5oEbuqk2BKYgL4tAM4omUG6o/DEqqObVQtQ\nrO0E7Eke7RK7iU3RWzynyrjAw63Z2K4wicXOeakBXh8SOaD6TSVwpnzGXUGJIIei66hq6QCw19wW\n5n1weyyucF+TSpy54hBsuQyySQFPGo3bPK9lR0G46NMQ/AisLk0lQxeXt5IzojZFYHRDlYgGntWT\nDdAi+IX2Puby2FSdugUsXvq7MbL8DxaT2GDMDs3AQBoqdXZrb/Cnzw7o66j+N7v1RBCrkz3f9I2+\nG5PEddyAPVw3J+oBsfnkJZNJ2dtNP09/oQkOtX6PeosdT6Q4FyklKGCUuDCoxDTT9aEUC/kV1I2x\nH1HejQL5ISDJKFo9//m3l72h6X9B2N8Fw/JJEcdpo8PZt8m+o0n3Gwkd8Wtdyqv0s8rjjPq8duoX\nkE930db51WjcFEUjtAMyloTOfARx4g/Rr/xGYuFgWXtdBCr1v9qczIjZKoAFDq2WAsOJGNNeuG7Q\nbXCVCvO2wCJCTg/h8uww/tRlou8v/4V6qV8hz/aTjyCan5nDy35ISxGFgpt6FQcNTIK6mcZn9xf/\nYIxwMViTD+YUKYoDRfLBMNpPYFw2kyZGPUVVnRgvphpynm+RW5M1dJdDhsapmCBRh47rHx5TXLTj\nvGOJA+r83Vg3AwjxoO+uEff0psXMRPjnbTL9blTlyw/b+Nj+K9mk76FMLDa2xESoZPYecevbQ5D2\naXEpviMr/Pp7onKOsNJKc7D25DnyLWn8Rr1771wAGzZylIY9LwSFkeV7UMQ0TuLu4yTd6FJbXuZZ\nbSRns6kaQz/0j6mgfzD2Jp006OcsJUu5CdYf2r0K/Sd0o+1cRi8HT2A1NaXws3K+CsYHYmSzazat\nN6gUKtsQ5jn44jQq1EyVcZA7G0vIn5/ZYbahmt+WQZ3KBUSAY1X0Friz6BSCDMcspbYOBpSoez77\nO3TULUU3Opc9Kp5yK9ejxeiJllBzLbsZgs6V+PJ5TzFE8grlF1jIt7Ed9P56oetCX0NrYNDn/aCV\nflrVWUyRyS5/2CAilf+H+BVZBX5YLbbgl3dL1X9Er2T4Y+fT3Nc3A4GnjtuWPrUo5IItVQAISnw3\nWXjoAt6Y+5uNjq+D5AfeHvVGARSH25iqD99AIg7viobNwPabTul1UeFFMX26y2+z91/MuQMWbxPR\n5GlF6f8U4VEq7r3AXfLvVAzJW50SKP6MaRZK4qrZBk90/g09tfKDGshrNOYdjQHKWcxklCyaLWYr\ndEFiw6YOX99tgL9JcSrUSQOYAxXNmkPGmUtxbtST+XAY0az7RdeVEBDfV/BqZDrhbohBsUm5FEzo\nrAwCNLgEaSvwDE/Z8EWW3GMm5gG+cKtkkdMX9snIrjberIqEXU54W3QjhHJz1Vbh53a0A2ajG2Kj\nYRZQvt8iiropi1KrZdabn7+CKb+tSF17wbEbr0lu/QS91U1fCh/q1+B16+bzsPfXzC++3qayv1Il\nQ+CrM/GN4PDAovDLoxsPRx0G2LaaNpj5B/qvMvNhuWjR3VVz7j7EZ/InGOWzHm3OiSzoY8HX6OH2\nyFUvc4TNbpMfKvRuBTFlM9we0zLt0bkMGTmFEkydZgUTUBCntx6UBa2BM32MWlfQFOu0tujxqJuA\nqB4YPlb8cN2f/MVVYH0q3iRQTopacjHh2VciMyg8pkbsel/HvvYX9+2yZFcMN1jOxWKrqay2ZPIg\n10ku0zTbX2cKYUUPpaM/9gXSKl0tgxsvHHqTqLO/LrVIx3Wk2MdrID1A5Hj6r+9u+ryqcEOnMOGT\nNzufSARuNUVEM81XEaZ7gC9XqqKtiEnOa8bJfaInwjkzifJ2j+2Chza0xH5JgMZ6g/ZQIvTgafny\nGDgjrYF/FGYEbRUZ406+rkZ8jhNRQmRuxSIZp3SIIxz8eVNtQ7oF4VfRED1SzDfVvZiJbqBaqRcs\nw3TVbS3YcBYcBoHm2cp8xBBcYy70TiRoIxTV9q21wuydY1PEUgiCkLRG30cr9w/t+XmMwlJ0ohvS\nzNagt9tfWDXuskYypQlF6T5PMDc+WAM8aLEcM7obAHcheZLUVvJjM9qu6Cll74LzqZ+GO49pdiGK\nBN+MZdlpcVHrzJn0p74n8IcpNwV0mit6ApHpB3Lb8STYSX3dt4KXBfw4t8yBjDmJCXdwVi9N+yqc\nB2UDWjP1DflU+9eXbO8DyCGInsfc+MHPfDn50AN/9QaGHrzQzKlbdcNbei3qeIWsOOp+tlQ7w6mw\nDfOdUc4YNfNGh4coBtzH8dZ8QIBO1cRCCVmcxFisxgw9DQjL0wApFR1n0LRBHCNvTmaAiMfv/G0f\nyX1+lMOEDjokl6zpWOleOvZfUl6wEKyFmivNRliLoPBkNL0tz6F0V7HMjXH+gGOzaWWDnI5ONFcT\nZJxRh4O1ZW8LVDZ6Wj6DpEne7OvCOi4h9GwioCLp+gKRcCh/4uGmYqcurqDTR3VSpMHn957w0MJg\nbR0TBJowWMawBTbX66CoM9d278I5LK1k5qD9u7kJURMRc2akAWVLVHeyBt+Dj5e2qtgfa3Y7raai\nZbkm2aNMDeHEt2MQJ2yrSi/oG+ewo7ycjoVvTLoIura9vsLehqbs+QGfOUizAx3mq9xl9ipgfSAl\nfe9HxZC3JNr3kR4kL5gr9ZJCy24U+Nrtl6I7xnOF7gs1P/rdEa4l8YOH1ZTlXNSdH7Dd8SIkQVbv\nE52E0Ee86jdKCGYfvZ8tQJ9P5fSHFw2tCmh6MJTijoDrnX7sVs9/lpfxxLfLH+GOywuNQ0qGOpRm\n0OxgJf5iZ7yjJ0+Jh2Mk0zLhkmZxRe+vvhWQ8HtjU+bro6rxx+OURuFEu34WsyFQvy+l43nY5Szy\nu9gcAaJ8fYG/wR9xHpVScIdi9NUMpDA2DEdVY1kbc6Zd8R4HCR4M/QVLV1c9LeuvOAxEpUFvrnm8\nXx1y176L4LoocFSSVdOtHAPM/Y90LUHto8ZRg9a9OWxW+9IC5agJaIHBgAt20q2CdNJxYYV+11E0\npxv9zR2tQ4NK1k2XAPvMwJEBSs+p1ul9t+ImYfeX/G+yPeD1dPrLBMMXLmraB9BEFweW1Og/bwmD\nclQGXeSCNHU1NOTWp3DrNyktOKJkhE2LXRICZo7q3xCXSsg2lkg15ckeFEwaiC9SH1gkn4KebKhx\nW/1JI7QAVL+8Gqobf9iV9SO/OdLTzysS5soxXBabDA7hef4EWi1qS4fBolTWyRMYAgpUBqenjtdO\nFlGZgnop0mXvSsDFgR0jGxudBre670ifiOByYye7c1UkI99IDyt+7FZqoUvrsvEzx+UgdcaYH/gg\n8p8ST+54H/1KE2fo68qeHSYJlvYClAflv0EQu3Vej/Mz2XpQkm1G6Ecedz0cr7RsYRh/2EcK2tVA\nwhDGaesF8R3TRd9r7R0CvGrAiapxZzbm1DhkV8MKYZO18xpK5QQ6bXb8DM1nfW9O69I/blh8ahg4\nS/68+ovgHBFZ5PZ0ckqUB0lHAl3KPJBl6fvCWmx0rwyOwVKr8q8sYhDEXT+hM20mNzzhj9jpGaxR\now/ymsAZGz8sgHRruPGyldavtWl8yiUsNkn2tivPjh9H43xmW27AtEnLPIg54QwplZuE6X1OSifj\nrP4hGoRix/XaGLTGuGyBuuP3O+iMhkMZFTxKcn4COuh5Y9dkSiMcc6yaaxZEh8be4TVQozAuKvEF\nHHECAqXwDi2brXrkvZa3A1B0HOA8KAJd05Km1CTvuilTxIyf9SmcjJjEf12H+HsQ9ZjyMRoTnsOF\nUFvq1ueTZW27f4VQyrLx97pzFYSqo6dUpSTz2Q96QiS1STDajR6Q1NIvOYhceNhj53evdlMBlZPf\nHwJbI8+XvLqK9AZMx7xQTTGhNi9KWn7cIlLN8U8ggriwsr2JsLHl2hSyP/Te4mwlpZwtCxY4C4jI\n2p4WrVdtjbjIfnm82GFOPO1cobDrxXW+emBlY/fmk5VT7DID8897eQoJcH6cb10rvdkvPA5D17iL\nu4eXp6933R0zZT1GGhxq5cpjpguH7EoUa473KMHoF7zpiGzPnCJqoUnsM7oIA62ntePc9nyIROax\nIYCScv/VgKvvjCs9e1JAtzDvWgk5eSj4oYJNPavMUz9A0Ys0d5JLGSBdi0rWBZEC0prqsg5zf7uP\nr4Ix7TPsWZKb4B1GCM2NukfU2MNK7zV3xAJbideCtmBYKHRoXGK+6pz0crfhVZu+V1NtHy9kWjpd\nGQZ/fTLJ0YJe6I9MxXntSHs9ILWJDczaTuiLp5RL4bUpUejOrv0XgmchfqYmo+5nWhFYB2ezRiGG\n1f5vNlK3sHCSpG5uvh3EIJcjnXRNX3WS6HwhKsVNyNtWglFzARs1cZwyNHNL9zrppR8E32L5ffYw\nKiOKdZ8eQ5Rzdgb5NL4rFfgjVGQ9j+RT5w80BKKVJKo+hwrx4z/7zYUGagaNerP8W1g7N0qPuMiM\nwy8yBZOiSaR9bGHZpsxRW50vmmUVp8DKcqcHRBG4XgPfLG9cknewLLZK2kUPk3zk5Zsxxp0znhls\nL+8GHl4d68CFfpKhxBiG8h0jCafOiR+7KjAlIUH7xonQzvP9SIJ0PwjSA2MLYtOj/oFl5mfAHWav\naTbRfHBtLmzGbW65Sd3w9sCzyqLf7jN1AiN0NFSX/Cc7yAJA9fRrSM673K9ozxEr4OJhaQoJ6LL6\nc6RaXFDAJMgfLl+nmWgLYL26bmeG48oD9NbPwHTrZmIV9Jp3Qn0ElP0EnemC57dNbWIj5ChLRsNL\nmTI/DxT4MivncW2Z0CfTZkPtPXbDFDceVs8zmKojkVrnxf96JYL/EalLo9WxX1W6icwbEkOJCogb\niJrfkoVFeAXHBqsuOpN9my/KcCEPSSFm9Wfwpz2A4HTdO4d+TlfDXXsnMfL+aFHAlfI2R3b8FvjA\nD1Dazf6qiz4YbT+UQKb0Zxzr2FVX2XYlAt5uCU59Q5UAFG+wvS3seSBlY6lcBt3A3mYlYG8fMemS\nZ9SFJW/hrjvN1SDSKc9vXy2yaiynlsOJmamuqVw6eKMN8JOG8D2XvxsZlGCZL98nFY8JL2/Nj31d\n1VVIe3E8PCfXvbULutxFaqls/50Yktja7E6UHBMo6gmGBFMbxx2V5CFxigTSUx4tYaq9FV1tUECI\nsGOvxJZHbl2He/jpiOPSiU19PD8UB2OA2I+fhu8aAYL4xc/iEpK5+toZqOS71J4MipWfloa/eel9\nsxLpGw0DHWMYzucAEPojSHufcSc0W5hbNEN8bhGDe4q0fqCZhmnv5SLx9qlWalKofCBk+fjDauEj\n9HScxUhinAQoRL31E9kVLrNGDvdgwRxjtLK6dgLy+u5DEwCIlZV8OHFo7xpyoeVmB2IlnhKQAwYA\n87IA82gKmaEXrCtoRPr3vlqWAFgdjKZpHJBkzss+LMWhZZpC4dvgex2dHc+dTSTW1OY8amKClRhq\npGLe/ypHC86phuVqrwCOMU+yiSwwAl+VHWOlW9c7OO5HT9SWPOiq7zOv4gmHBifjeqW6uxZxwSRL\n7eBiv0XZ77GIW8WyUZZhmcIWWSBJhxTEmuSMD1Tgjwt9V7G24QdqINJlOQvKjK3FERgzDTWStYfP\nXSP0Gi4kfPEb8aP90k6tLPCucilPq49Q6qQXA7lxROkDXMb7xbaaZHHSXIwRsgKREHW8yBwR35WV\nGt5uthNFm3MCcs9jZAdzTeQEwvRtG3c+jq6D/bY0rI1Rk9GgS2FrTXJMXOYxW5TXC/OkEUiB9X9t\nOE4wUy/3RpMv7Q9h8QMrFR7yI4vmnlf8ehcScqnFQ7T6BZY5FRZtaljDFgChANF10ECIZt8P8HmV\nhjyMyF1D9vIqaQffrMLQduh89caHqyFaJMXJ0Q07eqqfhk9XhkEp+B8lPIpU8cM8fdlsXF7UdrYB\nnGi4kps/IulxXB85FG/8uel8kWwIx2zNTlLBeX8ZGAHUouRZOiH8RU+zNyTpHYFsn+6IBQYdd8kx\nt4RrshKrXfpSfhS6+kiy7VyzulZXAHg45IukwRYp5EdqSv6AXeO9R5HIC/dEEndVJ5Etdr7QeLcv\nZ9lBBM7XCNduO/QoV1xw9ENcyxAfECobPRUdj/pDMW2rbHF5bqorcyJvlkwF2eAe9DDdxd3tG51q\nlX6KODWKpfVihALwOlOTSKB3S1TuNgId3zjgvrT/nUQOyECTx6cowqn9whk6tl1e06imLwMjupAN\ne4QlIDPBqsDJmD0mbqekmfbbavMUMPPIE0BzF94kJYmNGuu1w9h4zQzE1LzYUgyz2TF10jzj8lBC\nx37E7bLfp189xshVcnIZTqQGRGFh0Grx6YYvf/NfCfHvxzVBezreULMD8b55sKVh/nbS3DXGd5Sb\njqrgymJygFmz8+f9FoGURvmqn7+hvsaQSPpCbJn3Zwlp85AGqn1WRxvvjEhuBq3Hzmz8WmbsEAII\nfvx4A/sHAm6rj1qGupDfySmLFbud4Oy6tL4I/3e7MAV7JjVy/lgaAqZbQ5plB6udrouFsnkaVAjV\n84OTvcMyD56GHVMNs6Cjr4wEwfzg/xXXkvNP3fSdH0VUlzxrgWJa+COvVUGALvrTQzDt9wBEBwtZ\nt+hStB6aQHAVgdt0p3gTrokKa2NcFvHHGtk9SPyJtDWZpCCkurLKHzoefIYOoPvekpaqZspDzqKP\noItroVYOBKpbzNkkXqiF6fiUTK0gGOhF8QHLBgY7K++8Aje34zlkF0dR3ggn9e4+9kh1BxRoCiXa\nTvfY+HGiESmI0YDj+A89/xoBhNe2LpyWUBePzXsDqqxVqOCFjJqLjGgll4cLTuV6jB5KMAmEXdEG\n48aVm3VUxm40xgRYmjs9jcKj3DXNuJdEW3ICdIZJMNiYsY1zigRQgPBn/iSAKQfSLGBfxxFm92Cu\nUCLC9OXkAPt4JWVAvp22RM73SZYhW8RatGy+XAX15UwrTHndE7fxpo8YxvnGsP/FSOt3kXCcIwtv\nU1AAYBnBWmy27S6kjkKTBS+9HwidYXk3cQj86crhpqtd3dRY+B0hvQF+5fYwpFHNwYDA4yykLuKE\nNT7daTU6tfaiJUotYaZxc6OzY493l28/X7yxPJs2Z1GS+MEluriH2vtePPiENVm+vz1sHQsImZtR\nd1lKoP3HXEW2WNGk8K+GK3x+uMcW5cu3xk2Pl+U1X2VGi5Qo5H9100QjA02ou5flG/NXmXZS9Vp4\neRWCEy2gEiksC/OeEhUTJ6AYQKRigiIH0h3HoC/sSaPmmYpEIvzpnZfl1ugAEU3SEWyWDtmP3lI5\nTl6MNy/vXIuK38FmSWWl0Ad0GN9lBL78Cpr5TqsFizIV0osP2jG1xaa/L5tOjNLxv8bIoCKVYIOC\nYqO+zbX/Ly0dn6jeDZxFuxurpoli9P64keKIAwWWkXPWvZSIveHCZQs32LNKPHJQ8UzIlqJBsnD2\nHD8tKhY9+MamMDBcxBWVlVQWNxoVSowKbxBCrKA7KuGBa+uklKdLiQuSro6q22DcnXx2aHTL4ieG\nsRYedXftBVv5m6yuMZE6n+UAJr+ERHIDOlNErBBujbsb8to5Ir9NNunIWQzExE7pZ5+D4ZZ6w1d4\n2zjJ/yKZVDBM4Q7aJelzOuPOmLLraplMk4+D1RCokdBQVt+spOZ3gTBB2sNPfMSjXmcyAHUwggIk\nInE6+Chx+BwmYRRC2qnkeUEBM54rPKao+lBTS0YEHdxuAOXiYyOkqnENKH7hmXdK9eopxaUZxPJy\nYjUQnXnjKqLhA29/F2ICSdxNU2NS80EPdg/4wySpBd6iH1vdX+MbqhYJoFRUfPsIigrp8/ZOxi05\n8GJozJl/nP4XtV9OSHu51zS5xmo4xd7YxBEiGSJ5yLhe8Ry9nZRZEhgpYc2hVx40Itn6JcI6fQg3\nCBaehc7fvgOqebS9/IWs+ns5sL+x8OIzU9g/Z+izPJD/6hLOwvwbH2+H50K+qdH2Nieh9CV2S7HV\nk1DZEv6v89AbzLi7e98qb0PaGhagSAchbQ4Egy1XIgkrCfyBy7HC3aLf259eNJPNhats/Wn1/Zfr\nFxjPdQOB1mBbmwTdlxAZ/aw72lLwTza0wtf9eZbR7PoT06KQmTaSqyTiDzuR3K8kJFR4HpjDYFj2\nA2IaWVFKMRBVs4G6hzUBPD0lR00UpYk4o7PM5MQ7ondb5gHjH1PDVvpTp2I2tAlp7KPRpDlsUcsG\nDWiAkBRcFyM57nb1xvnef8VTTbRqBv3isoAX4IFCyVMrHVAtJBpQ08En4yV+XtDXoVCZfNmkA576\n83mHQFQIuYcFZNwDkeV78s3iegqdykW55V+RPfC5BLEOMYaFcn58y3g1LJDEpV8dIxQAevYq1Fij\nUz64al5i3qoXFOxhkC2/2z24s9vJ0/REK1vsGJMwUASG6u6Xqs5nUORuOUEnBUW0drFZgYUFB2pa\nq6vCLBI+RDCn7/SdGcoBYNRH2h4bvVAdR2zau2lCZh2hv8jGx2rH0jHeKgXeC6I5G6vvU1OEfzPf\nhxd2MIehPbrrbqr179G1gkLd8+KycZkqV8FS2bLDYKiav4iPulBBYPC0co5xblaILoIWOAwmoOm8\nP2UgsHp+myOh42fmgOrh6VOB4BMvr2TNBYhWK51tQz8WaBPob6tVcvAwvWZkRQHJCiPY+LHRORDv\niiCcWMyTTEQxxUx+4uIZCK9sJdI1cHOH4mjnOdyO8rUrgfhnNPlIw/LJ1Vjpxx6VTgmiTNIry35T\nl2S1Y5nL0uAfqN67lgV0y0DNZjYrNKuGIWE+hPEc1RsUvcLKgouHg8EYLc6E86zeLcpd66r1Lv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/aDNzBOYEMDCLnZm5ZyFIuIMh7lefQDj/rDL+duRNOkt0XYDtGidqeYybU+lRkNRDi417cAM\n7malJSPeyHvWTj7uigMmtMZviHxEjNaxrU3+47Se0SuRXoctvNu57n0BjX+fSLvQsUmSBQupcT79\nrc6ykBNnm8AgXtnlUxq7LTOUEAQWci83Kot06xxwVuJzfdGgSbjJb4pbdQqj+GiV2l7Ipm3EdduH\nMlQ07hxLDNSonNxsIriBYy53cwH6BD0kLcEhf353wjXeYnvCN6XchPJwJeRD9/iCvtjzADuPbUge\nBqJmBltLP9XQj3I09NZN7J+2SyoNTL5tZ2eRPr0TrqO/q3D17DJxqLUmSjTeL2OrCLQEuCFtnwX2\nlwqqW4kNdtW/qh8wuICcVhP/WHYCwl+Nj3Pxn+FC7ukQP+AF0uXc3xinlH9UVJO/Oyo/x9wE42/n\nl6GiiMQq69kQAsJhBaCahIRsYI3qBcbNvLjpqRr7UcNxGK34GjMYBkOlcKXyW3VHUevH3D0TF9zT\nQzbbu9vZmFUZAJqJYmC8INvZP1Rxgc6xowBQdT1QDZUMT9MjAlWNX2YQLSRzllXvLpNrjAzXWBfR\na1mwpG6A0r8ZiwF+WJSiar3wRibGR8AySQTwotexjJCFWt484FM6EZwKJD7CRZOFwJWecMD0JjpL\nC/cfgXipxHAan2abn6OgV8v9u/2+3QlhPkT3oL/gYihggae8nbu5k/TqufGWobINFYG47J/SpKDF\nlbSTxOdiAyMzHGutvCUCsWVgSr5CbyIfze/pd+YZBhwN7uHKp2r/baGPZB4qfRyCj1GqNdqqCS/G\nBLKpMlvr2qLzLBYYn0tKArAi7vy+Qhm8a0P5nPCRC0lJDxLpI2HIaNaRlhofFXeuzP35147n2r03\nkUiYiWd/WXwHRqFPDBLAYWNq2oVRMXd3WbrGv2tgHyVYGFmqoXHoazzzPToIRt9JXWlEOUBsV0ZH\nEqEr9pobGNOa/zBoPhvbi7cjONiyEdRfi7mMmbCcFjNbNDmPIodkiVo62YfavD4Za2zc/yUAYvHi\nt4qf8cdyCBJGmoogswKV/kF1DbYOfm1ok/SXhaR4VKMTn2wWmMURAlbC7+cF5Sx9ynEKhfW1uu3G\nOYTPSaxodEXUyVBE0c4sWvnf+QMnGtUYQf586DYJBtsaszZH6UCdGhSYJ2jz8Mc9/oijedSJCn7z\n7UNkibAhSOO97pPrP+BjfIMw9KXOIm0scPk5AtK9DNiQswBJ5yhMOKOfln7Wm6MCs3Eb9obJ7xDC\nNotnckUt4Wypu9qtSNb8vkb/qchUiH+rgBdNQjHLXAR9xvGdq7BNkpdlOrRSqAQ7iTqJxD9tqgsO\naRSektXxtlSOeGAAYHifkSRsF23833L0u17wM0I1hDkS8ceQrNqyNDRtbQx4m10SmImsl6bZezz+\nVlajdXkz5RZHGtL63Qk3ruzBOChRIx/Mncpp3qH+/FDeJhOkLkNzxW7Xf91VFE/0zLqbJ7+YFB/j\nGgfY0RKeuClWbKwro4eH9X6dMwEoBU++YJn39s5ilSmDTVJYUlxYf3xJw9liAbeqBpbFgWzSwj+X\nUx+SAlJ03XJLuFC8dk8jbFjn9FhnhXwj4PpaxoWHOYyVqD2AjRCU+S5DIS8oJaHqcyE+QtDNeo02\njjAuXCc3jCMcyEZWfHoN5/mkKw58yxIGPwabvEPz6ABs6Z5SnYobLqMw0VGljfoSY/Sl3yWqHIh4\n5ewo3aaXDrZ+n9EuUNxY97pdAbAAeEnixRy4l7v+nyti1jA7lAp90DOvjhedIgtROrVMkLzGv1mz\ntM+cR2O+6ou3pPI/OlN9xI97KdPbLTBvvSRdBRNyRDBAE0GuKa439aQFXf6XZo2bLupe3rKCq4eX\nYNVXvNHsxXVpaVHH+AuRiHri/41KWzZpaEzhBGBcYo8silToA+SS4uEqKcS+Qifk3+8Ui6OrQAxN\nhMGVvadj/2QQGOjXPWGSuVN4RKj7DU210mmphQQyquZ2vlcmUlW3qYcyTLGISVFz+vQCvXkXGRG6\nbDhhUd/ezx3vZnPEKv7se1YA8nqAqRgOkt2FYz0IceLfLcP6kPijt11iQf+nmD9X5QLIdbER1Zch\nqpZ0yIPX9chDbjR4hudGCoT3/zJgGGJaWwHsD3FAZ2W6GqtJqw3r46pO6EtRFWViS6RXV3/x52Po\n6G/rHtjv7+yAJG6q/HWkJV+4pGJkseM01gXslD3TIhLXXZVjD704srCWRt9zQXJTupbJUXRp633W\nMu+4gMPZsdDD0lrPCDKG+fVKOfYkREH+C7V2v0+krjtQD0MkWRmkADBdZEbfGoK4Lm4N+3z5eCem\n540C7jL3WCXi2nCmQHnjTdN3c4ImB4k0ZkymCMhrLcO0uqbOa6E3eVRBMoRWy0vnlSJu0Afylrgz\nqgCyJkmiKVfepXe8IA/y3KLJ7eXnDTOypwgs6Z47DKNxLu0NXRwdcB5kiuqcKUBa9bzRTiRRiggZ\n9I0rGBwxmEBpuCxwuWCIicgTSoG5CrdjDQFmggniE85P/fUoZMBO0UbLE4wnB0a8UMHsjJIe457H\naXs3UGcedPZpvX9owkDVjg8+Yf4TF/Kn8FMnNzukmkj00Fu2Yi/UMAiSCSM3iJ1mhqsrmy75JMXO\nwy8XwtY0Kx+Igh0vOsjEdHF201+ySP6mIKlWPAZopz0GuSUk/9iGBMiej3wW67LiAzcrVZ7hCkYV\ncu6/BFk+ytRJJC1xM9wvpBqA1D4qg+F01Oul86JXTXlpt8gGKEH9WHE+/MTFo8aJT4Jbrr/6cx7E\n4jBgLYH6XeHgZrFRsHZajUXbl7RB6/pIREmCC7hDzpTKkBji+Zl++nVoZzFKKJ+VLzRXXPEx+SF6\n0JdEPTnLMwLe5GBY7NBdSKdi5X05j6Oou/bRTUJMi3/Xl9Xzwr+DPk3ki5mszrMzi+Y8VY5Q///i\ngkQ8+jkDLIH5pIExroFIXieZHEPZ58plx27AZcIzZ5uiqh8XMS0fV4kY6Y9SJhgR8ckxlz/ZZK8v\naRmx+yMkZ04POcv1598tpJl8yBrxpE1UgA/QXpkKyLVR+sQdCobMhvNDXDgdsV0kPvxTdRIEMa3t\nFy42lyiMN6HHzkEYrAZx1cLG+XurSNmJ+Y2qwt1qoMmC+7AWX/6Zd3V/F9JHo0eLvSrhtBdlCZeK\npFDfeDO2+s6QuXxbuabsgigplmnIrjotXMSHTalKlbkG3UOBwgdjbFi0h104P/AepNOSx5ykUbzM\novz4aqETyLglMMXSggaBd+MnyQ/OC2bn+WgtkOH96xQp2vyAEP/YrrFty7jHA6mredidt9Nv3X39\nl4zAokhJhBNRczbk+FJGFp83BoDYoonn8mk2JHAfY+9wBKQhXsChqwwej0x2alylXfC6UDDalvYS\n/VxmQfPVz23wCJfwS6D/aFsWH974WzUgT/qYo+m5+H6fJP8ekWJbL1IP5wz2B9TAWGQKRqJ353It\nl+hOwTYVKd8g5TMo8yika1UYErgR4Njw9UGwa5rdFrn2I9QJB5HPXynB8K38raBfc1XjdxSq0D9Y\n6uZKcVYj7QYJ2OS4AYdBG7G6Um65ddghFwpWNccfFSBhIIyoJARgf3McqjohtGy3j3TfIYn4/waE\nYy4DlPW4SBXgrYUw81SAECNVOxyQ6ohuF21QVkJ+W+kn0gR1RqCp6URaNT2gvRZtlzheZ3AWCJ7n\nHoITrFGu7kOqBHU+cOGX7LIt5RMBe3OCKREEDknEr00Ti5XQ96k6CiJBdRWIetFkYzE8wodTSWQQ\nk6TQh5FyUPc52BP049EykecY0qkEFdHhKcX/N2EPiJTd+b3lG4G4H7t05c2VtQGuvsFp1Zhur69R\ngX+Y1Cg6XH4XbjV3ev4UhKL2FndDthkLQO3xcPIHe00BDJRXpf1F80aASIaiYHcIMGSLJCS24s0F\nj/MrLGSVvE9nZidgb5ih3CVRWgsKJbbF9TzNRJtfBxvRchdEHds0M8gOicxT6O57IXteGeOXnwaS\nFT3iV2xm6JQKxTvM2sOTUAxjN+09yiGQ7jMM0L7jJwHos0aG/e+GoRWcf00zXFCY85++lEGyAnjc\nl4n+yG+HkSq9Ebgaq+EovcTLKvKRIGsixK/a+S0UMTQfT4Yx61goufSWRA1RJXliWJcxhSKGFh50\nD5tNiPvIRXk7iacVghz/vCS/oDS/odKDCNE74jz/ZQ5hbKu2Mps3M6kRU8HPYyMJO8r+lrtN8Ta4\nmAk6eBW3ZTzOE5V93IRVzywapxOUvct4Wvj74ieacTdumutebdo13POxnVa55dEokUWISq/7ZxLJ\nmk46WB708S7rV9KMFiZ8c5rhagSNrpUPz/x6FGXObZNBifFl1qR4gHB7OHJcWW3xN4qWaVvTBee3\nDIIAitpIuhlLAwikYE3si0JnOyRaH0z+iepzixJcNHvkeYSIx76w1kOXHKg5SgXctxf98ha0tKp0\n7eaefxP2FnUJNZvUkitiXQ1bMKDjvGHyUM7vumh3UnMstAnsoUMcvxLfF8XV63nAdLb2X7d0NJaH\nxW7jpJaGwxSbtLfOsbKWTjGrFND/5gSDf6n8iXiibPwFcAmWkGDP4SEmaToRXwe3oGMxz72ApB/C\n3OXBrpL8nJDfCYPSJ1l3Ath63hsONu4Dq6lWxY7C+zo9PR24YHz+tTdSp3+U+JhIOnlYBU2m6GNj\nIHTfTg59CJx82kLq26UnUEzK+dGVCEcvWVweic4l7NhVvabklQ3zW0puTQFrye4xwzw7GlvY7s+2\nw15IwN3z9awLWdH2K38iF6g8HSq2uSD3ZYr90txxEqpQxUeNCv0VMUNLU+1ymTfKK4KQTNIUPoKL\n1wFepCM6cxkwNSOXBftkSsWueDJkC6fVZr/QZgzgsLDCAMYtfuwVXyMDmBrLc9O5tgbe0+2nncln\nQEzwn9SY6dbs+4aQCXubvpL5XligRG0MUBJB+EN7E8G26d9SJb15j3SVv59Mhd/gP/ZTHEMCULrT\n3HMFm88JByf/qSAbvZfKF0CZYj5rwz9EB7nJq5CoqZzZ40R39ofk3hv0QaoD3J+g+zJxKMRO8BB5\nlFQasoZKLachRINWOoh9GzeG19MEE5TvGLDdaqVpoM2SoT9WK9lItWjkXsnrs361qi/pE14JL+yf\naiLnRyJsfIP0IhoqTG2eAod6K1NzydPA5evRoirHLNG54iZLhSVBEZU62v2dndZcsLPk6YLbTUeq\nMNxQEDBfj0eh/sPlk2MHU0axoBb9DRZALjw0GBCdmfVUOzP4IgSR6fThiHWxS+6V76LI4DLnZUKO\nDzgc2pM3KCJfxIU7Q5uyT6Zk7S8SX+rjuwnBjTUPFmFNcRNyH1RqZ8Yk/DjQgvRfPZIBkzclKpB+\njPLlMGykGdm15AHJy7CJIwC/bFgBOMSQuMlgdiARkefDNoMu6napDTDnSswkLX6VCoT4WVFUHOT9\nC8F3FsDOX8Tti7FwqOX/eQDuBRXAEo1FU8Kuda42fKw12hBpAdj3WNrInqiK7W9lv3Hm2TeLBpRA\n+388xBuAWavo0r7i3Gs1d92OfcPgVOeGa5pl2WkA4/4+tarF0VVAbUIrXaggrnsoYlHoGkiokRut\n6UfYDthUpvpyzTDKL2xHGpBPk2hQC9Yv3Sld5M0hrHygcaKsgzqLbqQm8vUplIMm1ObC4vspjtYu\neneSh3ZWohFmWoENumaF2/XED57J2DTPa7Yq8vYnYDW3JlOlfc7nc3OddhExjcTxEXjEfp/VGehk\nJGO/rkaRkWj2S9oPXPKpbCUM8m+VjaAn7wNYlX+9y/mbyxy6pO1DUgAzR3cI/yy1PkSWqmWfAsV9\n2WaLvjqZfQyQRwpEuX6lL0pkazodzfNihyNgCb8AMCFtWMzPkzHkRsBsz6apA67oBDtDMgsFK5PY\nBrybv5YOodIt/2EwIsrytGw3Ya0LiWE23Qk7cVu3MAKIdPZLu7OmEwxKlJlzBIEWq8ccY1DmTF06\ntkfa5BK03pjygfxcbud5Q9CjGxD+YDnMyvVsEtJQ823jNRK1i2SwJklGym/3fewwuCB0IGdsHn3J\nK86XK8Jbqe9Zru3tDZDCHB+mypQFp1jlVWRmttBYEZMxtZoozgzNBjyDeMCMlpct4yAu+XNAKIRQ\n+pD15Vczd8R5GU1uCGmIk4nQCZxyWQotY5YWHIPDncBah27MSWQKEGEObqe0/a8+OJcqqcaY5yt3\nhfl9HLYIVoreJMDO6alsg65viRtr9jTV/N1/hUXye0ot+9HyngV+jpkundueMkadhd2ri4LLxYxX\nlARgp4Fa6+XgINHrFRqZuPHN3mQZdmlqzUdqcDoK3uCNN2khIdoi4azDKcXQ6NaNFz0vaP1A9WIt\nD+amkChFa5P4141p+LVbk9VDFJaFQ+44hRqMv/xcK4Rh8xQZSthdfmgE/mriNhmKQwat3QzPxp8i\nXGNwDxpdvrpWSFXlhssHLQu1dOv+jTykOKabrI6EdZUOYh2uNjP3Hpoe7yxbOto46qGHem6oEmEl\nkXOyIAZi1E/1lxAMeaHz6U0KsP3DbzeampqlEcei25kOaNYwu6BLGfTcm5dxulFvgvigF/OZNCuA\nu5F/ZoVO2sVKkcrttsNOgVesuTN69FKqWAMjeO7TGmo2S23oZvVLmYLsHRPyXkSzJ1opcTYm8xTT\n1eVVu/TzTXeVkRkPHHpE+BblMUkQ9qTC6bDKd3lR2Ay00jNwoLq4xI2bQQXqGbH5cv/z3wt8MiAT\nPvp5Pe31nDUr9wjmDYZoU1NWHuK7Z0KcYHN8wM9jzMH0RYSql+15SgEAMGTefEjf70D76HqTXdKI\ne9oskF94cz/LykHoT5SiGljeh8fwnmfjG07e/TMDnNNSsEaPAb8L+Tmhg7hc+eGLU37v0IpXau3I\n9n95ZsusVo+mutVm+AJ2RzbPoTR9ycLVGDpia3JvSaVIsR8w9sS/HlQS8nItM1HZFCPpjGfxZa2D\nsZTdULmKWgqMOqfrY59Rj6q20P6FFvKns0YXJ6DozEL58+4qr6Ua1f0IS5xB3btUUPOk5vJHm+yM\nh2XtQR9edFtO8JlPNI/LbGumzlRYz41Gwcu4AwSQVaK9+AdvNQ7a4hjc4IMk1RvInzAv1Y2EWWA/\nhCkdKB994qS2SmBJBbrOgsW0tDVXZS8WEsj7v8G8FyKRLGjLzTGlsQnN8+e4AdhK3/UP2Ec6cM/F\nq3rxWalJsaDTPqQNNuLL6r15X4z4BunK7HYzH3MBPDSyyb2qSxAj7VbhJnXytpiMZ42ndMNUibmr\nqBzjANeEUrG7A0/U1qoCvs/pi2uUZ4QAQ4Z7aY0cw5OuvJczKfc3UIM0K5ZG8jdhBdZSEkKRVhT3\nyFd669DqfFsRNG7zPMm3e+B2pfXrrqfzmoQgJNJDBFstxowijOF9wL/YRZhrVTLNgoEgV6MVODpa\njPTEJIatd0PwhMX3zJoiD+wbh3mrRfCy4cc+2b4uAWtY+DDgpn7U6UGzNOc7ABKahCh3CcV+i9iU\nxo1vvtMnCe6SYLy6rJktFNkmUPSg1dpYR729iRTmMs0ksCI3sp0KjiDimMOiq+mmi6Esz26L66DZ\n6hddgiw97AFsbAnAny3RWWhL8o5BLpdwAsQnjpifPfMB2iw7bW5NxgGH7BV1Omi6m7WFqxb6ugK/\nh8gXNdGGAChOmes/2ugceLoSo+QlpWgS2/Z5q3v/gj/Ean3OhY6TeRRtX+AjeMAFE9ehy0/iTqa3\nXTi0MZ89I1wZLcnBkqU5pYBSerdbAoW6HqVNxGTtwcdmOSvkwwgb8b5xjji+HSS7p7FuMljRC/ei\ngpMlRZN8H14IOcbT+1JoMpIgxlNaeN/afD9iroKYN6w1tX1Vx270DUBDXh2WWVz2qPeElrflQUsp\n2Cu/JXnYOs96shq3Acwf8D8JSBnf3ufMIz+1uXoXE8uFaBzVCRVBfcROSnuCu7CTfBOnkeWtwROL\n75KumjjXIhi2+XdK1NF/XWKfhtPRzX/0oGOr8eLRpe2w2ruwsf7Hc60Ew90nTZN41HGAaBfENqs/\nRopwhw3sabBXom8EYhs0a+63WVppINfxUJn81FtPNUMjuzThp3vpIQL65g0Z2R9Y3xySMtomB/92\nsMcIweXKnKauB7bL2VL45ws1SjF2Bs2cvi8pUSTDu5rxI8Fg3t9f8GGDkv2fcLujNnnA1FOGFoPn\nqiDf2x/mWurhmPHjlBKSyLKL8sN85hX0e/IsoknQL/3+/H/o46m9lSOVXZdoMDqx10cIMjdMo7Wc\nuUBWPwfKy4gpcC3f3JdYmH+hvIwiCGjq/9WfaMYOIsThVW5bHN5vwQFcS47AEINuNPyHK+fMyJw/\nXVsWiuhIxUIKu3OQnlWK+m7Wp7guvoVBns8mygQJoozHE16aA32W2uM5wC+5U1E7pB+SiSBi8g2w\n201nC2yEAJHW7mZeq9fBcV69zdGi2ub0uWgl0nfZ/+FkH9AOgqoH9oq9X8Vtkg/93CFCYd7vr4LF\ni+9oTXAS0awDIqoOamHgE4aVraoXiqJfKBUWQ3u88LjPZ2AzZJ9wrfeCS9ethCBUSdfDQU4GRzRx\nfK9rdturUGw6Yi0ze7Ss2tuY5QnGxLjVl5NTvUHXkNEXtPH4cgD+sd7D9DvpS5DKTah5yduSk6ny\nfHLeFc8voSwdsotgimACL5SdXpuAyTz4wR7+4dQvoVh+TnDER8v/vIpbJaaZT6WzSNBCLibRqTAY\nGdiBujAKDpu4+Ylag+k7RLrkJXdH46OWl65Q4AoolTM6TvCUO2++JQymVhTZ8wsGNp6aroNF9BPx\ni1hPtNIG0+saHIGT5T7O8ioBjAumVEsTMIBi+X+6F0Q5JbfJJcdVUGcJLLXcaZ9+pXdxBmo/LGg+\n0NpBFQxzpaoiezPQsmuJiD6DcwG4kYSqTQ2gbhCTyVMvfwET+Orw5a4lIGysPKv2hu//LES33eXt\nR+q5WcbvEkbIbalL1WD1xcrVMEVD/EPFvboOfFfuQ9thZ29NH6++Ts169z6YVZcPGfJlsIUlLoGm\n7LpCkswSWtUi3PjXu5TCCNWnhQfD9EVmkuuiQet+dHftrq41IXTMsHUet23rQOwQ8CYU4pI2CiKB\nBtYd1TR/8m744knmdvYWWWWFJ5BlkipjqfrgMKmu4VqlbALnXR5vyR+woQQEkUYySCPf3RCaXSz6\nuq6O1oLkkrKSpk7Z5H0hJb3FGKtLoOhRo8iv8G2xaUfRNjoa6lUBQ1zUORz6loOWFGA11OUK8hQ0\nwnfXkj8eEEePiHFp+lg8a5QaIzg7b+5qxWv+NRtMWrsnccqGkRbTnzVdEO/bC9V0IfBrUSkxV9eI\nbsMWh2G9FuH9V6hnBlMozvtrJrEJLhWsZ64xs6+X+W3PqofbOOYSPmzl1ZxQSRMD2bnmng7POo5Y\nNigi4pia7MWUzT+ORLzrssWZ+1iWVVd/gHw92gtZbDM9o4Hsxgn7SxxiiUISF3q+7bCtIZ1Ge7yl\nKhlxYHz9oYJqVUfhKtKrFOh8TB1GQGvjYx3JkfnUptNg1uotAUWohdRY/kQVGMfmVJ/vrhq9nmNX\nlLAm9t403ZfgqOu8k9OBmny4n74qq1bpFpMcwFeAHn6T+9X5oghnI4VtKQUZ+nb0op07/UiJbnDh\nYLkXf34molv6f7D/T9gmEvPq73mA7+4BDQH9NnMvp6dSIJycIuWvCIy5Cfe6AbPrPkYyqqLwmVEo\n6mdxtDo/G/2bu7y/SyHdKhUzNjE3IOzWL+cmFRk035faGFaxVC0cmQ9oA20eBELvftDa7YwDAgMx\n+Hfl9qozQA7Zt922SwM5qeWwXfqwxZPNoifKpzvCJ8LtQ2UOQbzMaD+rfbiePGU2HomDjwWOnvn0\nvHRGUtMdw40RW3hlFW05f8SN79bDy/jrh52wmdxPCN5lUiPX4TsTRH20M6+FSi7+6DXCKsdyYIxj\nzR/Qjco5qNzwM1CWV+9Zdvsw0LsHuL8UZITq5Op3RHmDQt34RpNWslqFyqMqDaXi2n74mJBxUq8h\nMpILnplpo4QvAIByenK5zf7TieonZw9Sr81weoqm0HtTjEZUrTeoPwlcAGmvOaEpPydTHoY8fGJd\nlktjGvHJU3GJKwSR0V6al9fdbcTpxnMmHwy+4o5Wfs5RJYEVk5dHvDFydLsQJ+v+b6YJ+JuB2ahO\n44v2fQ8WxTnngJQlH49sAUAC9L2sFtEaGCfS1CKFGdw2XZlx4lu70JUQE8vorMnLYq3kVyt0uS4G\n4nlsMf/dSFzbl0FKVv3Yy6dGAPLXq0sTXZhUZx2iwKJqR42oxC7d0FApryDXdZpJWaPIJe6knNLG\nGkByMWqBXlGdrKaJkwJeasUjLamzulJuyCtdW1RgsEYZyl7y16tWkTjZCQcXOA5Quw8oKYmz9Qfp\npQJISaPiXzHyPw6GFuPDYcgKwnNT3fGRJzunW+pim6xLFLC4LvEdQLxNBWGJQT3CY3b0LzoNgMOV\nMYBqNBEBS3klxb21Qjoeqnus8hM8286EOayJy26l9vf+2yeAc1JsxvlWDbyRv6aXW2iuD9rJY+lX\nQU0CtQb+1mzsflT9rgesh0/UXEzegFaCF6Tq+A1PSqdjUp9Zxk4wPCClf4ql76Q1GY0fnyuja2uW\nRPGjqddvJKJotMxbHn83xv4CTy+fAZtZcMlwjfhnPnETLHmaWIl5J/x34Cno2tO2F+EO6FqVTlPm\nu51yA+zAlSLwIfOYwDchB5//K5kF+V1hFZpzuKMLakhmS4pl88e6CE6zq3Xs7RUTajoYfqHJKHMl\ncnzaO41TMKA5fECUlQ5kCyLdUTcZfTcOpqBVPhSFECBo44kOu1a0GwL/qFyKX38qFPcgCjDthXn9\nUCBWJG8xudW07FVH6XQZOpr9ETeEnkBl5kpBZlh1aTCbNe/NJeB2LyVWmf79620lPfjpt59IGUOC\nR4E15B9R/D8LxUHyKjQ2PfwVvXwgLy6cphu3WPA1p8pON6b+CCiYZ+JdDNOCr4BnEUIRQJy9dIY9\nzbibGbKMKVL3zgjb16qlQQTQZx8KekaVboDLkQOlh9nCfFinLeadyz6bpFtvAaXyu90VXPbeJFDU\nu+yZH4k3SpHy8/GnBy2PM+r2vCtIuI2zV3nUwVwNqtWLpI3QrShhQ3AQZToSEhmXxvtLJYeTJttP\nXd0ryQWwahnuaL90gbYDWoKlj32PEaSVbANK0LsYmP5w7hOJN4xSmAd2c4JH4vHyZ6YcgyDgWVxo\n1jEue2Win/bOzOjerT63hnkIBZKMXYCMfFR4VkluEhRHna2b/iE7VZSwmDhcq0ldCi8oHws49Smg\nmxA5+QBtzzyG957qOoHBlaEl2gX+n7OPZgBCAYIPch4/jia3Zkwz4UhgLyz4wPOj3R1DCf2KRqjh\nJw9jm7I2coFp5+37btk6J0Z18kZ6u+43q5MeB5+TRjpV908RDo8N1ADpfuBbMY/+JBU75wX3+9x4\nmdrrGpNRoDXN3SzL7Ie3p5a7o2KP59ktTAlngu7pZ+O6UfSkuXeQgmDf0iPu0vvd1zRk3KO89lIw\nISpXZD4lx+QDPk2mIj80iMqEeymfkdEp3cyGU8gmxOFZUnGlypY0R7EF+yaLB06lIljZg7PaR5S5\nGk2FX4OXdrza29N8AOjp7ahEC4D+utCr50RGFXsExzgAA4y6O806Jcu0m6jjCWSZVwENB/pXIfzv\nfvbHVjtrkgi8OyVPz/6woOWuDknVA8TcG9qPtpfk6q8PrLdozc94LIZJC2G6eL12hDxqIIF30HwQ\nXFQBxIk51grQ9/5SqA534i5mrgdH6T0hKqyWpdcH1WuGf+hf2PegczyXWcdtqnmRsDpgjYBAtBWT\nNVQ6nNa2VImpZg8HjAxxTBH5ljZDWKzo/XoMjtZ8li7blD431ie/2Ooqdku5aV7HPwzJRe3GQxCm\nf/CFCeuatdYuvSJWqQDv+Y3a7YO+q7fPC5sac7DfbnoxwHWYm7xi35997A1F2B0NAVK6QtlM2Fcp\n2c+1m9elG0mmj2yf7B25vfR2/47mbCCm95cp5R+5f/RqwKBnzC9rBaRqM6FMsM4aL/V5uf3Fm8zT\npQZLffw6JSPuRMl1vaDg6lDcPFXcFJzwH2mr8k3mkcPfefY0UkB5Sy8bJdS59YOTeg8r4Q8AaJUH\n/XB015irWuCeHLUk+aJnr2QaBS2x59AK3ryhvsX7mMSW5ZlMBFxaVSvp/CoQTJfF8RYoQZiOcPn6\nOoHc1qFiCO96lKLHMRlgx3BWxS3k60MNF8JuV/L2dtvbff0gBCKfjdu1fnGeccCfaQN9bPa5DLqS\nBXXlavkhFaUnXAVo31e+koJ2CiYoELTLD3BzrUXmBV7FzaGkw4CGVUkCQrEqnzmL43BCgLwUArkB\nEKakCfQ5HZfOxK4guKHeOFFUwlvmebQVGrSGSr3VyTqlyQhyFnvawuebWxT+32uXWTMlqhyMR3y5\nglq1g82EdUYM1Ju95YJ+GxtGP4n06NjpKBetyA2U41YsHj97wYx5hD8xgUVUftW8fThM7z31pF69\nFGsJDuGDICyi2OGfOgeFjWigROZgaqjKcU9/CX6VLdB4KuHipsmypUJNGawoHvQS75LZz2n2DZ3g\n23fHaxbnFTSz03xiK8HumzD0dhDf0xeTBnPw+LzaeSiPmRQPzyjWvd6oVlMQKfMIDWj1pfRGoQ5x\nGuoHsbxmIczwfKZdNmLahbybUClMzUq2u595V3yjIsWKki6F0w3xZjmSQfbex32bBrUFaeovmMr2\nZUkZYImFKlCVeMjUfC3KWLgM4LmXtE4372fhJncuVWnLWusTCc/zsxN9uCDCxecfdrQIsPkUvw+n\n+VS/g2HB86jaAbnb8LS/wuZ6vPg8akvleZF5q/7VAZ+eY3KYSnphfdQC+QlZjX8IutU7JmjzAnqs\nNpsD5GM/410J6LIOJUM7pVY5hTYM4Y2nscYDTJU4/enQeXH1StKIA0qr/DQU9GGSXTWPjkpeBj3I\nhreN5HsCAFymDZJcCqGRnxixwSKCGFKhAn4kZi2arn8i1olxRLmi/OJ+/fcGplH0FP6Gio+neHbc\nbGf0fVS06eF+ySQO82+1zxhnFWJfQYZ0osagBUNdgqz0Agr0W39AHBKn/kio0Vol1l292GpvRSpM\nRhCG16PJMdtx6ke2fm118lkuTO8kHW5A5Rtsnmp3DWidD2rjKS4L1NDhQxw35MSj1t3Fdaqm1qrP\nJRu+oqp9XwGpt2wRbyNxeXBEjy3L3umsWTdMTXytwljYLTHmEXfsZY2X5arLzMShpfASK4+qEgw+\n/VQzdY8qkkkALFxI4WjI9BEHXqvDwXT3pTz7Gs4bnEwV0adTOzT+NzX5WENYG/XTk0tDTY3cTJ/f\nUconElz1cBGGkhz0XsHU1acmXRKMPDblT87zJOny+eNbCObV8KatOJy8sEaSCOwX7w0JxalnQ4zd\nvVFJIV+cOZX0Re9Icj8+ENdnNnITHMNx/qlI73oNX4sWASP+BR+IjVC2XpLztznUrTp8awCHTJaE\n/4WkjHJcFoH0K4HnPDtkR9eUodsOWmV9m+sGcNNEVm6Kdo65/d+Q55p4HtFu8CZgdelkNXw1Ik3N\nFPqaWjeM/2LFtkmhjCWxuiUyBtMbgfDMG38NrOV2BXq7B092UW0O3EEsF3cXRb5y344zZl6T2zda\nevlrVzl7TfsnyIw2kpJ6Fi3vkRgNrpYOZHWr2Yw/ysTkdGO5JgSCjR2GjciLEJb4hT40e25mN3HJ\nf6UY5btWVL8vcQQb963Ir1EjuIGpNPxJWMVh8Dbu0BSQ3COBLHWj/pe4dz91ne053KQZtR76VqpY\nFFmsekbyURl12h6jpz07AeB1qS+KYsmSP8pkp1WYs6yZ7ybxFBcUFZN7QtgQpGEzYQ9qbzGqO04C\nxa1fAt8OccKcNvYUxnANplguvV/L+27CamQePR38RPd14TjyYVLHMcLX8WzQjEifDXYADnKQObUr\n+fOdSXBsSk77aX4wvAr5r1s4JVDDDfB/FCtxfAdC4iZ23s8QJfWZqBvJMeotTu7CpClB5r3aiH38\ntN5IJzj1TFtzY1kh7ClUOX5G8fr0PnrYxutRB4y4JVUtrSGGn3qd9DAg8PwzXxIys+KZq6iplABl\nlan7qmvG2x987RlX36nqpvTZFZ/Be7N9vVFsZ3COVwHZLdpF06Pfw/FZGsGtFHOYPIEO1je5jrhX\nJfZnx40DGxIw4NE1ak1lehbSwzDicveGgw7LGb5Q8lrlfKOPg2RfivJP5RdaXPLTmwM00sdbRrsf\n8ei9afO0ZxM5MtVPMIMeua15Vgvwlsncuc+rXO9rNbNyqet/uXVOciCDoiikX9859uRwNV2WxuCI\nBmjtDTNRSVAEi3DcYWRSNtXMv0eR4+X2V1S16JQPqAbu9QdTO7nCKbCPPSz4itRHZFNP33CVVmID\nTc6tbN9uFaFpuKr3FKh0cGPpZ9WkHXFwcM9rXnLLnf/6wnsgT0s0VhO+D+beEjXyRhrauIvyuFWD\nSD6LEIBivyFgpMCVHkPlDI9aWMXnLu10kdL+8F2mePNeM7NMW/1exmbTJqMqIx7togBfS2ScPpEz\n/e7fTQARGUHLw/KFLdrNnNKut8UkLE/O3XH/OK8lBvVPqJm0hIoNjBEkczRsdOfm2droLQP8yh5X\n4neQvAhP3rGVzAkwM8oSHoQdZEaxP5g/TsdwbSoRgT/Dy2BrUvHLkOT4EoEkXjiEQ19qwkNZYtvu\nv25uael7dudITZJT99f2c9kcv8fYFKo+V7iMngsUdQF2uhwFPQdkTJWDbt605Ws9EWJ6J2Mncgk1\nwWAJEz0VdMwxz7dIa0Iu+yWBVqBN/nyzkEQ58i36uhojj1G/+76FwEZy2bVWce2Rq7YZ6Nr3GV/3\nfo0K4pUw8iEUId/BjZhLflCc8PpSeD1gipP5IoKxUQUjUYeX2ih321sW+Umhd4vQ09GUW0Bm5X8Z\nrC0glqqFSHObrgdb2dA01VVAOGKvZAuLNPkT5bKghVxzW1u36yf8MEPp6GPiYn163xk8+WMxzYF7\ncBGuJXNN28rvncocqmQY/2yWYRJ4cAxEzoLC6CwNRq/ZDRLvMawUBnpxKq5N872eDZE25kYCsynp\nWb92WYg0X++oHDTAazd6Kq8BzvurwO1vTKrLwepPIQXYVOnAbX/TPrIkx4pyHVGN8/ICMYI2/vum\nLh/e6TciZvVpY7Q3iHS0KEd1cMi4iSAg5T/djgBI7a0iqyXgd2g7Qtol2kdSPJmwsac4961w1uEg\nxxiOrxg1znfRycSyfk2s6xXqq3YZfQX+c+j0coZEu1v4i8dHOLxKzG8bgG008nISovWwxJTHU82+\n3HFui6+EfzS6cS5j7u0bKyIu1HzEzjqzKzpqaY19VquWYD0baOZcTouncYug5WZ50TZ79Rxha7+0\nWfDad4d87I43qVTpN0gdo8zOtf4hNJ/E3PsQKfkF/syBwwGO1YezrWlSsmmXrln/sIQyfHcy5TXr\nMGLORhus5qqPrrhX0S0/+gajutsNHV+P+bPQLh7H0ATOn6uxf5TSqSBh0+nBU4nd1oi7dcwtgZVG\n//+FeTsi9BZs527ZOyHWb3cYSgKOvuPhLX30gFiG9lzADzdsb5jn9t3p9hMVnSxsFQWfzuG4tt1z\nzPQ4NHw3zrDiLBM3Jz8C9Q57Z+AxGO3jFfwS2sfRMDQ363aSu12Z8mw8ryNQz6rQVWThD8p6W+Fj\n5sLq7mIcGHKZZgHKEcP+6QgURLYKsYgcvPH+T7kbgYRVk//awYt8UpDKo8vIZZFECZNdawUvcHJ3\njdhIXcd9q9KBvuf8bqnu/y2BD7eOiic5o3Z4J0AdM1EftOk83E6loHwzqZQivRCV1vkCO6AK0DiO\nD5Dav+ZMNeiuWOmGJikbMMbS5TnYyul8YBz2j89mD9GHE/0X2aXHo4bICxBIDn/6ezB3qm1ZE+bt\n12Ulhqba5uLuT6WGJYL7T/FpKHZIpWUdaafu4+B2OoQWkoi5RYRz42XKTBmON9PtEudnZZcyjVDg\n3ESKRo5EkGnct9rYGR/HHlbM7fL2H20gYWcZIzV/wFLFZthSRwChPXI9E02LpycHsTQwlnRB4gJR\nrAIy+Ixxa0tf2WnSqjFh2mPDkisx8EkE+q8Cnf76T1lBSBAo4EriAda37Jo38Od9Itz7w11Lsd41\nR/ri1V3rGDTidFs4BrQElyWxW60Pg/Yy+wsegoHcJmP5zK6fl+HgTmecf0PzzosoMW/M/36CXbzA\n78BdYD41aDk+bCkQ/movrVSagiBc2QR9MKmjBkmB0S5r901pKQdgkLMO7U2oHIrquVMyq9SEAaHw\nINTTeq0TD1lFBoOqzhwvzXamt05vBmJKlSaCgRh4Hdsw+xOnHFat+grA+T3m8acDkMrH+fJkOqUS\n+HuPyU6mVDksEuALLvrzXmJGQCY2V9086aLctbF7qQhiQAyoEHHbNS1J9zCZQazAC3NQwDfP+IZ8\npIuvXDveYJXAZpcVOGn+dEdPmBcjCV049qXC87r42d0OMK78/0n9R84+qVsTFk/2A4gEX2g1/pv2\n/SMVxg8+psjxpYWWoUc6Z9rEW9l/yZdHBQle3PD3fxAt+OPTV0gYdVyRy3biU12EmdjjrwqEWTwe\n3vMMU8eTnN+1yj1SrruF1x0UI9Bq4k8DMVaj4/bZuWsC5UUMt7rw2e4q4TRZg80aQDAIWFcBVtME\nMJx2c9XP5DlGZgLjfSc3ydqMgN8rPCeljXHoB0o1mRmgSmCUiOChNkXNhzSinNWLIMznlfrIi1VG\n6nYzwx6Q9ye0r51RAN59NvNB+Br8Q9oWKEkAKgxmMktOw/10I02eIzoHVxx7mFjz4MEtN5AGc3KW\nQvFze2iuRVKugBsyuHuWW7JDhJXODqUgUSpiNQLdXjaxIJX30vVPd8Ozak8GNxWAkn5RkI2WJumK\noDOOfRSUSIv5Qzwmf/Y+TvclSYqropZE/kxaGTrGakqivoVP+VmWnlkyC+IotYjrKaCWD3X/3PJ0\nOa5ewhzJVOObssvxwD7ruGf+kVHdnuRMMQvB8Pw0pWa12mwPdHaWNUS2+0kHFIpXWbHwpN4K5ZKI\nfrSs66CJ6pJDk/GTSdrHMsTcit2NibYqVwNyAF4P8qZTfoWlARfFnIEmRdNGZ3jS8ZOrj4pcBgTj\nzKvigQeYZ9HRony5w0ZHnazztyK0p6dJQXEJ4rjjbWs0Bp9KPdjp04B7xN/esLfz/TyBRtp2gZ9A\nJOPfMTon3wnKJDCPEnn8Q5NZ1L0Aq+n0yh3T4r9+sjaPa2UvQq3pnzjNVVnZYJbHOhJRLAKwif/r\nRdYiv7V8XAJqUGSqPyb2O/oIqtOu1fd7uObgz+4vGAdkKZjIDyx+e3a4T6CJMSEzl3k8LbKaxeHw\nBxCJZkkLIV7RRpYTJ913/CQ1NACoEMuj633Af1JHPtwcQK7nLfsixwTtPK8tGvikiVuxzSBvL+Cv\nDR0pEt4kNlzeR8wsADXYDPaCaBDtgIaCblyUZhQiUIjLxPVhjatLcq8VbehTXk1OiZ1TMnH5gHd2\nZOr9hocy1kIte3pV1U0SivboM9jC9fMABHBljvsyvIW1ZKxn+TS+oaLFoLJPe8zJzBHOT8d98q7X\n02PRNlS5+MnMOj3ihwV+ErBPju4DsydugIpUNbhSI51T8hk5cc8sLNVr2SxIxfdMtW5C9cpjpIAX\n2Ww1Y1/RYfvxs+WxFfBSGV0RvhB1hGGsm/xW5et43PWTKLBpah02ywEzaqqpiN9sRM9BoEBJ2nC3\nLWtjorJ8RKPs4ypBpISKci6y8+Vir6C+CopXA6Ga+9HenKFVtuJgsidwanCCA7riQJpnsn7SdrJk\nQlZ0iffS2ADHsJgNorUSZ2yF52RbQqh7IY3IP9PbJHFMuUzuupsrfoFu2IuwARMEN7LnFpkr1Y+o\nQQ360g7h+XB12u8PChQwCGljH9Tj/LxqNNffqWA64F8ROMT1cLJXzuBacSbcvPQGSScWAALZDvae\nb2cWpr1qBZPP5uHC0fUA/LU95iMyeMktoxLIimf7v1TmGad96pTMcUDoG6cK2lyIaRucNMTOvYKv\n+8lyISDWMW8JTFhl3WVUUh/C4pC0E66vgqbrBDegPAA4SkcNuUI8wmSpgLhQgDS/vVmyxXvYtQaV\nKMZ54GM3cflDUUQ+pLHxuHjYMQGoBnJZHkD2IkOmjAJI6+VCKCA2NvnnaIrbAUrd1sIbPlEfbvGC\n5Q9xEdOWVa7aOxKmt4l5E4cJR/McFvs1EXdsHETVIw5HAD2u+sGh8kWM0G8oJl5VchIAnOYwoihH\nvZVI2Wk0lrjU4ak3KqkPZt+lZWpfsT3a/4vV1+Lc+5iepZ3XU4+99hwpf1C0ACbLxIMuhBFhv7TX\nI/PO24/eEqg2kg+cZqVvirjvOAkJjDZSYkJ8qTJ4iNotCJa55fsPFEYg2tpCE19mrQaC5c7TtpCl\nGbFOajbG/xiEf7KraceZbjZ31fho3RYsyaH/hP3LwIU2fEuIhFbA/Eekv8DbTAwlOnmGRxR7fyIz\neM8Ud6bYbjFuSMB2H+/2BD+3so/CsXNJhsFeewjYFf0DuWCZsoHcR0yBiMP3i8wSeIxSwhdVNRxj\n7U8h17ftq9blbkhKFxVuMWEK+J7t4NZ7W5eqDH6TeAZ9zJjL2zVpfkiR5/Fa1Fp231s2ewg4gX6M\nhZiwyNVGeT1Log8g3k/UCGLtuQ3x5+ft7kkKP4pF/eyFWrOn1BdWkYcY7+5EmaZQQjyMgIa3SMxY\nB4Nb+lWCiTl2gArscHkvbU36LKAHvwj1gOQ7HUP61v5KI+e0MsIvWQ7ZPzx5QnCph542y4dyGGjd\nLK8UJfOST34eVHMYlAhLMbyByC8CO4e/Pm9AHdg9GPgvESC44VTuImlUw4tybmmBg86MpZSXtSnj\nkNqMZijPYbR9fSHFshkimvPDaOcZOFxtW8mQXajTeccnAsaNKpI1ETJvralTBDrnT/OdRZDnrcoT\nEICNiPCvkkIZIf5iPlgtmPRwbxjiXvJkSrEZEXecGxy/7xeJHosVqE190iK2ZEaG+7MrfpjdKTNM\n6AaUSgnYgTu2iSEWcHjufVYz0Zn9s50t+unju+zQJlcAtNYfYE39KDcE6Vd5HTlyh/VCj+NbncLU\nQMuBq6wbpRHFfiEq9IQHEeP4ilF+m8JSEzfslQ3WijTQvOlaSBRQLrcqiXMuSuFmIBIOiAEu0Q7e\n5KFqYazW5LrNoRWiUJvc0mw0eseRW9znyMXDGx5MpoHICqInA+rFH0R2nndVg7xBjn4uBaA33sEv\ny6FAl71lO4pcRfb0nC9dbqwxc1ZNMAPxhK3K49zVosc2uDiuVFo59PoHGUBUnDnvs4BqsHwmq8mJ\ndobdEL2qE/BDJuEc+z9PbQmCH013BSUtHKCXEPg0ZXUwawOj/YrR0oIDDBsi87agu2GiQGoWi6H7\nHbN+iU3lKP5ntIX3BHflX4spJtID7dNRlylpH5faTd0gLDNb+Qvaj7zkcRn4meyHUpkVgh/Vyitn\naii8UEi8mIHTny73YxjkI+BYmXqnc5Q6TGuuY183LxO/nvEzmhilHVLLGlG55NqA8W7QHGu/kaWZ\n7BZ3Yu+M0QD4s++8C8X0IARNbtE5T+AtyR0n/SWbOLjFx1Nw33EUxubEl/stu2aOtwWi94y8gbsj\nHfq5LcRISbmS2fqH4OE0+Y7xhxM+ZD6uq40QBXkcUMcn3RKSwoVtE3bP5IfyOXkpSfxIjs2ja159\n3VlZlFnoaJVqUo3X2YAM+waPvJWRHChnYcFqSFDLz9h1C+yrIXRuHiWVgE5PEa4xaToQali6elDp\nuCD/uGUD3r/5z9jtZjDsH07XOeRz+LePZmS2Xh8/LWD/4eSgpdpP+jMattHhAYu4tBqpB9gaOtsB\nNhD57UwFsVdl/sR6LBK7wyvXtAchxIy4cXH2zRVhaHp53LOm/Y+m5xdyzU/oxaNy/GK5vVv+UQb7\nLtt+O/VXsgB9+r11r+x0olT2nyEYKWe2oxHgdvjg3uJfBZvCx8oukK1FN/3G8TrUiTzUL5iffPFJ\n5mdQvJBxbKjoiIimykRkZl6Qs/xxidWzPp55MB1dINpLJ4TGeo0w2lQgz+/3iDcZc+I/VGT1T/IS\nVX4zlRMw/smy9Vh3DC7CcZ/Tv9H53cTdIIdppLEbZJZh8ueLreoGUJKYAa7jyhiYB/Lo4uvXJFrR\nIGIgEPCA/MwhQhgpPlNhxzYRfkbuHbD2ELMr/Cjl/WDJjcTQSI36UqBiw3O0Dmn5FG5SfSwADkpN\niJYejRhSm/aUABLzWRtJyhESXIEHzmx2B3vgqqhEIb7TvxfM4LedbYFAXQTLJjPeMpVaiBcyqQ1H\nNymgPp0mS8LoWbToKzX0AMgV2P/Zavpli0Z7g4ytZoKFrtutsRLbmBmTjalrNmtsHNoymIBmc33J\ng4A3kVB2pI5RpugSkxsrruhzy43n7cffpzeYz7u19Ps2wpU6I/aT9j15+QSP3LtKxPMVtghe2fUN\nzeP7g+Q9+8O98WWi4zGQl5CCaDISnjsoBFK5ZiqUVeVThpSPW6haLO45B5H/Rb/F86DV/oytiUVa\nThz9I/UPVgpRZlEmZK0grPBDQtCga3nQmGESXWjx8CJMeo4zo3fVuPBbZMp5MA0sQB9eJn7D99Hy\nSrBYTLRHl+apJibf86r+Fx5VZ+fx0/w5tx7ejBTHTaSlBlGCKugGCiAZGeJGdCsEGMdM2B6hHzuB\ncD/Vs7SdcgnQaIv06UcizfAii2t6lo2PQo1e7PUcMBJjw1osuptfuhq1fMf0aWEjn2nYMjaG1hsO\ntPdBkKa4XqNJzbI2RC+zv9P8+0fBnOGG4g3KzD5Xkl1WiIOqyXMcOLWai34ZJrExc4S0P2UOBF30\niVcrj7Cwt2X/UrbZtX7PjE0afa+1Whe6kUEHDNdrE5UW4vCgdI37meEPkn4p98k+qM9ToP9Yw2fo\nCFzNfpxUxlr1Bzw4Rhh+/UndwJvcgAg2ugOzXCDxs9lX1GN6stgUKwpSE5yITGij7koZoPa6KQ57\nhhcinY6JaGmtoRUe7LzJcVSV3BlUws7nozScIxWirfJ/9zCQ4eS4taBc99JOU/OCb5wHGHP12HRT\nilR4obyNiPdTzpLTlflbEJ9VCEQrrPdw6sz3BI5n4LSl0ZmdHjuW7P9WujPjfUUCCuAIbgMSVsBj\n6EesEzC+HxWNr3eKDjnWiFVmv+mfVnOubeYz8RI2t63iAxo7OTdh9d+tKB1otNsMCqUZNAua+kF1\neJjZ3fYBWXCk1fr7GVkgOfoQoekjW3taA+49qeGv7h8VTXo7bQWcMQLSYXUbQEKUU9sVVC1JzXxS\nW6lEymRBrw4Ix/dCub3QiLmBzI8jFfdAIoOJASYuS0DJAfM78xuJSLQp1a14he2TEQyfyUu1SYrT\nghZhAAXuhfBoPdAnR2hOet4sFRnMFClwhu0FCGhbZ0pY0Yh3AWL9HW4KphjvCoJ47AqhN83S2XXn\nJ430AkN+7KFuiDE1RD2rw3p0yq7iO026OsTJ6IGl6qc2D3imOFLjwLALeZ72Yk9faJRIGNc7makU\nrK8zL5BdC+93vKq9zc2Auz/Ul3lKymchEHqqBqVNgDMo/z53rrF8x2LxVP05fBbPNjCiQ7uJ0DYk\nGGG1jCrap3LxX5ZGtDnOoAPJkMKyD2I+xglnNOR6Mgk/2RcvobxRHKCSO/Jjy4Pg9LtnudcOI9an\nrxTIYZly/snpKip1kSV8zNTV2Bu6Z3rOdEZNK9rJBvLfI10/iw7ehgtZzg13e3AkKnLfYqnp8Mag\nORggBFpDP/iju3fG8c5TGsG9KKi09/w4FhCkEHuTXdli1h57bNuG72m04va6gTE36lqbhfq/AVSy\ndCvwvuuzlyEitv4CaMrT7BnPJg+yjaekxF5W+a5ygRV+h1gfmBdXdXfNYIr5BKne2YDhFqehi4FJ\nwoct7FjWbEy5u7wqi5zPd1LMMZ2YgIpSQUFT5HXygj9Ru2UTeW31aH3gWwt5DXDdRQU/Cm7jVo8f\nNepeS9BYy1SmtiPyWsXTGxbsQlqBLEg/sI6wW48FceMed2TcSsngX909Sww+WsC/zxqbLjDvw1rE\nt8dHqStZ5HbZZ2u7TvkHSN8wV8vvsdqblNt4ewonY5sDXfzrgFW7nVlbd+uNj767Sc39KhfpzOKo\nTbTLo8y2/Jvsc4r6V7DLnzDzuPriFxIiO2RkqJF+wB1MXAu/v0nunpsmvj1TVQj046+8oEqWWZsO\nAAzB3LSWi1RWci7Tm70xtUwdI60tlxsBLDITdgsJ1/jBfhlDmkNLXGpCQe3B0Nghh5kn+TigvvVB\nk95tAnarWnPgQU/u557027+AcLUfm3iKq8U0fh90W0uTxL4Y0WL+gNiX9qSqrv49NcdJmRssO3E1\nTw6SYmUB4uOeWVtWeDKDcHN3e7MplHFBXbVp8wLyzaDsTJaNEXeKpqGL1VqNN2Ugg0dd6Afrafbg\nsWRQsUbP9c8ApibcoU+H6mY9D/FPz3eve4kw8CFCDTv5BMVfaIobH1HyOe1PETgaih5AmYbjg9vu\n+8WI7WXasepwyzvkg3UJDaM8SlNH2v97FQpIlfO46bzErJU0v3CyOOG2AXpSoDVVEuV6lnowd02c\nh1DNMsyPhNtUVFdnzkEFM0hLBdTZ1/pGSvKIn7ThyfUPFX85qEO5rmxiXUCmY2IB6GkWpu+kfCin\nxcs42Y4caFuSJis6jJ4n57FoIbXmPItz/9EAKfagPpTLqex3VtO8sZRSOVzu2lBY1cB8REt3Y8ly\nMSGHv+XX5TMtk4ozVHQ7frENjNBJjKZZG9PggmW+MogCo4CHvBfPUrewD1bs7G48HwCIeKw9QbWh\nar2k0lOo//wvW447ThLZnfdCCi8n8b+5YLi1vT9a2MAVcHxZQQ0HCV0fJfwa+uOTd3P/o6uwzbIK\n6G5DJm/4MjQD3TBSeYWzZMA/eNriyw0Ry4GjRhvk/qY7hk6TIWhRSONQX97Nw8lYxZp1lUvMraJ7\nSNb9ZjjZSzFCTf76Glv01eHlDhJ8RsIj9Q/LzDzEaLzeNSR/DQl1OTV7nm1RzfAI3/sKF6JxgrSI\nO/42HL0tPgXXCJAD1H3PreqpnYZGyJfYDIJB6mgcK3Insz0IqsYBPHapuOa47aL1vrgkbxf81tcP\nOZXQ2jD9MCr4kwtxu8SML8m2Km528ABwYO0+wMHsg4NWxjp9mK2EhTwWWKek+8wj8M0lfOwAit1x\nl8dW5nRqJ9sz8yVgedg7qK94HQgviAKPNN1b+m7tyjO/fXwyZzp/3ZwmPD8+ewnIYXOvUBinJ+HB\nhrwq9UHxSPyAV9Zz3P5a7gJm4RJ2KLlt1TO3XFDSNdGMXfMawx3H8EiGRuIz+CoUt4Y7u/BNJdoQ\n2YLSjbAycLypfwLkKfH4e0rLqa2+MNE5bWl8RWv7kJj2/y5l/oKRWVioNd/iW8CI6LE8LAWC0oRY\nkry+6DGkbiZeU7QmyMIjJpHuvRCe6CvcXPOUSbMLuPtyCRZkK/604+EOqp4Y2YlMS0+alCH7KQK5\nC6yip/JB8KmyL+RPi44fYfnuay+ykLuU6Yiv5liQtdNxtXDtUgb6sQ4U7oOvfCbX4xWchKHi2j8N\n5DbqctLr0AKtJoX7H20klF560PdRjDoMLPTCHvnRe7EbZGc7OaotlBbhDXf3+NTM/T9LSEjzZSMo\nQhd6HRZU0TNVxMZIYrgyx3z2NZSxSJpYJclLJxrb+s5mF0koCzEMZR0j72AKUBUFe8uABXWuVcpv\nu2/sn4ttlhXVsKtPyXC8ZjFua2z69T5hxeS59b5AeZeMajHlTELqSxGisLbgILLxC+nvozJEvymU\ntOzGPasVJvGn7I5BsvbzVqXyTZSPONW264Mt/5Z1aWgjHnWuaNM0aGAg30z9bm2RpGppDEMv2ZjK\nQPAAOhqVHKGjx748uh3pgPdRUKhZ/pzy4+nkqMokGXAtpnGwDpfkTUk9aKqVGgZUj4vlcfdMjMeD\nmtY7V0+DWTIzV41gS2tr91Ahl7qowTWsKQ93HkT8Gprs1oREkrybIzApT8w7OSze6NZ9VTx4hjEI\nlW1RdM0a1STMurlUCu4deGGSt1Aa3+apQenN15ixfoAaGQWbV7HIDhcyimz4TMFtrWB1v7XGQtVs\nd67hwecoEVrIXlCX9UFgAEHvMpsUeLxBu/SuHGZsMVTIT8L26/V7MPd9krQvAgBtg3eBHmM869Xu\n5IJ19vSMlhHmN6g+wDDh7qSfp8vIIVkBzjPMCteJKO2nWWJ+U7Ioy1vMoS6VMTK3c3/RmqsHc0iu\ne0BKgvrhUxaBhXXiI5MANcULjDfZ/gmOs+5QnPywMeVMQitNiUNdmLi67PcaUhQmJ14NxZkbNL3D\n7s/qm4qrvarvEQD1ktquCk3pNuhiH2MircCXas0EetA5kl3J2c9b3FksAA1EQ1rHVupWI2yUE2MQ\nCOUBuAvBFEWK0TpfXklpJCVwJVpe5nDc8WZGQR53L6Rasvba6NsDduMN2VgDzEoBMBNVQt1odFku\nlZTCTjkak7rgZedahf2GD8QWum5IIFvonWQIZ7PC4JybguA55GIwW1ZgTsi+uIuwXetuuoDJbENR\nT2WhgxFOG5IzzQfNJ3OqzuQa9E+NjCExN7WU4D4wZlv3BmwVD2K+V5WghDpQKph+EoSfPFkDMpOv\nzvSmw8+UxzVoft0e5n61LYfASTcEvvgIw8AIifFVCcMFP70bkdftX6azfWdLgiiBI5pcQijcz52D\nRDF/xwIXhqV3Qi85wGcpQoItB6pa3qTvywhrKGywFgq0yF5iejTlxYCAs+3GXOpVh4xLmdadZSuf\nTcTf2Rrn7Bv1UeVXBtN72RWwUwfgqc5rSGT9vspZ7yzE7G36uDTd2Zp3FrfeU0/ckcgYI7dxSdau\nttqD9dw7sZ3WfMoBsZ5hVgS/irIeLoJllXTR7+gUyB6/bpP6+BRlgThy0Rq0KADe8F87okd4I0Ax\nDzNL4k6ZGlpB3+JzkXU3j4IxpTdAzVvrpTLYxQ86BGz7Uf3fyGPBcue0rdVsJVsUus0F6zm7Fti3\nqZ8167LL6EmdSZok1kbsy8c7WOeXb5U2MLwfMsGzNu9iVLrAoia8GIjlkt296FMOS1F8FTdq5wCD\nTkcbC9lxA2NL2u3vXZyJ++i88uWcmP0f78xvFzhSFZd/0ieNAkbC292xbPcfTmB6jAd8lszMS61N\nY4NvVqRI3vexeL8qAiyKk6JnPCjbfik0j90Y+RgAJpUsxdQG4AREUaGQ4zX5LCW6zTV4xkWbPXdk\nJ5qH1orq1qyx5GxXR+qyFMj1OyTKdgMVbQN2WJbIH4kTduqsX7NP8LeEJWwX0diK/3w8Pp0utyY7\nGT2IwXo1Bc9pzbadELozfZK4acoCbDWhreNslfemnUkeadVWnfoTGHERYS0IGyjNwkZUDkzqHtpQ\nWZV2LzTFJFLSeh78S7JobR/4FwZmZIHruT6fgDpK37EA1C5+tRUDXgo2Ft0m5A4zv993tdK2GaGw\nZZD0uVqkKMGmXEqUL1e0RfK/CrjL0Ojcx9C8DxSVGUL2KLlRyzcwvhrxGIn6NhjqdQoLv5VrIjty\nHmGZwQfSvHSoS05b8F4MSbhwP8Kt0MHgIBaraWe2xBTNuNck4ZS1NUybvt4kaq33RTC4Bg++Xie/\nIR8EXoxNqbipeYqVDv5ARsD/saZrfnAjlg2YEoCbAjqqrZjzBaYCxY3LHoCwR9cg+0LA8fDDBd4i\ntHxlyOG9dYSj6Dv0EwkHkeAKWZEcjg8kLu5S5+Cs7LzvWkAsCcicis0/kRF62X6tQAURsMTcIvYB\nE3Is1B73x5tNFAw6Ltdyeyk/nm22hAcYcB1HOgjGk4nGAky5h5uHwp6HQYV5ih0lTd/PkDczKiza\nZj07HQpLffVsM99DijJnxsmsWKhBSyDn3As3Ac0i0JL0z8Hq8lQUPWdeMR0Fgst904Qmz8McqsQl\nfgha8CLS8RQRGQdAYHj+K9Exan+raIbfaxQOZr1mzy9/ur+rP+aAxyoqEAdzSky5LKWMewP78j2E\nOROy+w9z9nC0REYTYyG+XGDhiSFHWQKNwGooH6bUJGZlSoPYDhz3wEDlSoWcu2o3q8DaWU/vSYLf\nV4d6SJFusz40Tfu8rqDtVwNRfVuuHF4K8HKVAOUKs64IUMPLcGf4PjJf1eNeQ2IIIdTlRlt4nHJP\nZ8cyZVt2+XIgrcWWYWhlejvR2g3QRdbnpxJ2d6evdMYY2ZWfiBo0fsxCwJu9yRw5fpxecUggQiPQ\n8SwwW2aboF8uOaCt4+G3McZRA2tySMn2yJLZel777PgJuXhZVUyD47+lDbPgCWuYgFzJvv/csHod\nO4wtOaz+GCIxyhvrdsuX5I8Xz8d39yMnirrm27Qn013tIdW4c8sJr25jvubtzK8eD/sGJParrJMH\nO9//IR9L6oWEOp3xneLurp5h8SqyNXLf2drcQxR2336zR/BKT3fkB7NXV4vfQXo4bqpOGcm4CmxF\nTbuCgxXLwNz4HilhK7N4tPivTvnYIYxm2J77ekkBf44+r7Asij/BiV443YVP9b5LqgHTP0zcU6Nj\n7H6X5KFotv+eco+TJy/JSsgnm1zRe+JvPFigtSFoxn+NAtRGJWDROxyO9yIO4leOcsBbVy4g+amV\nocLzZTk4wdNcIX/a58DyNCTl7cJzixejc1VR5IFu52Y9WyrjjcYmv+iJ7Jn3SynBFEpIhAIdFdjE\nSngWF2XsY1EEp+FCirbavZyUHoWMGrOoMLZbArzw8Dsi0sNPvJY2+UwAouIs1ZDoYBr1xB1xQdqS\n/u/ChTTH50/RItywMI29bgq91W31qBG8vlqIDFGy+ymASJ36eljVw7dVh5nVNQQZ25ot913xpBSQ\nRuS0w+VPXCxk4KAtPs83cC3qYshYrXTqbICswpX0kXcZLUfKraN2ydGj2oEMIYUi38RBdmSv4IVt\nFBNS5HQvNLrhG0VOqVEXao5B15J1wQkvS9Wob1fLV+mmrV73aE3jQkmhdftpk26ksAnfdtBfhVZk\noY1MwLHdYcbGRPa9mB1L1cjfCDSY58NGoosNv3dilEpgsseoxeru179OjTIFbO1yJ8TcmRVnQk+w\nJIe2Xp7CQKubAEIHavVbJWRODKUKUdedG3RO8ehe7UJxX+T6g6Ptb+CpQCLqzwWI0cx1airm+18I\nLHOB4B5gdIf5z/YthRk8cSqDWcmrIp1q5lr1B5z1THS4z9VFsEEC3LcKLCJh00dXQq5XFvuuDUNr\nT05U/GjxQCqd/rqqIgDaul0iBRRlhHssqjMwu9da8FJeOE28NABoamCev1ctCbdBCf5jOi+J782M\nyQJ8Kgapbd+fBogesgLVlNumvaCGGyw3FF2ZvJOhzstsf/20JovnNGvtErmhu2ZrSGfZo7CV6spx\nnGcDLe7S5mBbTSLhimhma7uK+1+mXlbUrYKSS3egdhv/afzXe3mU/QGrc7BxafwZZGPww7hBJErd\n6oDhfTeHHOVZPugFenEeqr8SwjJaSU0pZchbATSD9UfsUedvcjorryuVlGBiUhIk3S4S6IQOhvoQ\n1BUO8H7qM8T3S3w8hzgUyuMVOkfSBGx1/2kYMy7gd9DIFNfOrg5RJtuk3a0HhlUI8GRxFeUm71vt\nGjSpebbofdHRuW0ExC85d6OnwpAVB+cQCGR4JQQnAuT0TWZ24ZiY1W6eOhxxb832n5VitJ+4+r/O\nMrki9akvnr+eNFz4l3wK11GM6wxVFXg13HkbSaKTrZv1K4XdSuhW0+4vMSFaPuQ39cDbQtQM/8BU\n5MNciGUn0XLup3qtXxq48jIoqHy2pUjyxHt3jdC/CB6xpPS+5Fgutbf8PCDLAetc23+ixnfKY7+M\nVsnCsgGsdCf41it0MXFsAJdkv69PAz7f+dhP2/5Hb6usx6P+YKXVnl7JVgV4JJT9RjINeKBZLtsk\nlsFT8np06tlEn7r036ja/f3z09JG9CIL/NzR220nB6PFjUYR2PYKsAGjnyVSSbkQ3b6ehv1iD0+c\nyKaBfQHSFOSorUvRue2bKzIOyawQDwsy4b3G7RG4iylNXSyJTp+DHk8Zc5TU3KCVFCDu2ra9Q04t\n/ocD0o+I5KnD3+Hyu0wM1jEsoK+4DqGymqgd1HN6o+c45iiRLnKOniWeJLl/8jVOGkUyWVzq//FV\nzRzFhg3zMSmGBKvV/dpmrx4Q7tZEn8XkRiumktUEA3Iup8P1om9rTTe8+JBkw7fVJ3ape7Gf8tW0\nutJF2ch29T1jMN7JAYdvJlFzjQp0N6NDRScNpBzJEq+JdnYKT7iuJGqRJI1cbNjAzytW3MkGpawC\ncDFTiTrIK02zP0wYI8JMUGszMUGyCxpsG8ucVic3EStz4KNV8Ua7gSLKatnqxKWbms/k53bt2kVW\n3K/VNjYIbZxqgy1wSAUDLJEslJQhxNgfnQCLaWUtc2dfSAYIOWb/CQWNvpgj9HHYPfOJRBDIXiUf\n9rWwwD7sB1F32z9GpRj/FzEkCjdH4H+rIBthOi8dWH1ZWiz38K/Z8VEv1hZwHDqSwRNpTkLfNl7h\nvEOIp7ndIDEPQCC/JNimsljVo+ZHMedgv8aSUntnYKW3UiMPyOXRqUVOZmxuIGHvX1mGxJCuFj7j\nRKfY/CfuQrVxOEiDHB/QBCKot69d2KbNpWLI+QaVX27d7g+pFKD5ILWa5Q1KRBawjYz9sS3QNUdL\nwroRIKXq+kqQuQlgAAsHnTII+Iyn+acZGIj246ho2zT43T+lIOAeSP4YhdyW3juOUfInP9cP9mCR\nrbmR7k4JIc+p2YJ7OXY6s+TwRN97XI9t6l1V2JXsqo1ZF2Z12dopl2QIark+uGoe22LH6CnAfWca\nPjDTEgYWRZFNLTu1d4HvdzVwaBE8DMikY4qKJAZSqXq7BnyA4DFgigexfMK9C+AYV2fivd0ON/9D\nGb0va9dRlbzuIcT2hrcHY3C5sQUUxGkZd0bRgufsUi/lRopBDLPs/JWlrsDkgr2FTsTgB/2WMBVZ\ni/4/bdnKENmqYkO+L9MnsXDlU5T1pcYFlR9MbmZI3uaWkuaIwZuGWEiKuQ91bm0HFIRGZGL9gkIF\npB6uKN5O75NDWORPPKZbQKog8ErzDhcOHoMndEIdNonVijmJu4RiHe1bagkOxkAUkGowGIs4A0aI\nWLP808TJNYC74rWu0CFS4Q9d8LUKRuW6Xr5mmt7Gd7CQmnWtRH7Ob5+Guhx0iQpYjUhyg6QmVB2o\nosrubqFQbK8EBp96dcDtA8gbdcyPsc9WZkSHc0cJgzLVrRF1BPKm7B+XYP9F0PC71qOub2CmOAmL\n9CC+5s9ET3PcfZRzyT6zVEWpydk7/zz1duSkBOyfEAq5qY03dLzLzXLbuLshJywXQjVi1cjRxbJs\nSgWUTVUPjjaRm2y+dhufHu4xmp3ilGf6e6jp3XPwAUyI4TzZpHWtfFiyWxijwAgQCv1V0AxOedyG\nS/rnFNkZTPdhYBMtwKoIwgIfJiOTbW5uBa8zqI9cbdmsZaEvZOVRbjoFdobtI9333AG+Oi3TKfSD\nzvxsPFlnxzAv+elIsVaLj1MMQTKcSRlmQA8UjIfNwkYSr3BJ7Iqfn3mx8bldfW/iyrgEIfClcYt0\njcuQnf2UcyPZCKPTW/HSdVmDz9xyy9w9R6WuGfzgyYjTXos2VYN2wz9gg7D0lQTfVZs5UNVMc3Zu\nrK7iLzZX9XDSGIn8Z3/gS/uybzVebtzXf6W9H7yVXmzMMY8PVe3bAW385qXmGoAD0duS77JOjNam\nhxhcS8+Dd+5c5yIaeEnVavqD5KVOxcspGzbnZ+4N6QsatKhCY3+qTcwY+0ntqZrDqEDTs3+sp9Ac\n0ncQQzMbGcD9h7RFwQzThPOFN4op+ZZ3bFHlx3M4BoGXk/OJvp24nV9NeYUgOce8z+WguGRtEZzR\nZmDoP3eRvolLlfpohomVcOHt/DrdBxBkA2YN/hW+1SNBIWgsSGsR7CbjHrWUMnrjRVJYmPgZK5NX\n1N0eAlraO+iG8zt4/taTqhfRa8wlMU5XXtp6nxPGImyq0OeMQSYLohHCsURzJXbp0EwsPNo9R+j0\nPNLH+4A3y3nTPtiGc1PNQzyoKGKIheiln7BZ1Sr+5fmWg+RzoifDtZi1yLLoLyxmk6wXNMjR6gYi\nj20CeYaFOuijXmHbncx3KQo/V5GUZIqCkfPI2cGgI1gdm1tOhFLEoiTkU7p4f4IF5UnoFnCbXMP2\no6FPC3D9BdvtK+ctqKQufmgRPfsepZpPBFzHnUpYN2B4DKkr1FSAnHaBtg23pl0yJXVWuhVHKO8Q\nG3ySylAp6CpurcWZIUF0WDOCrRVcX7HBPpPoqeanEcSfHh2IoctmxBhYQLXRzb3SosuzzVfNOfXI\nxEH9IjKDOTrQFAZQmw0quH2bb3ZzDuP2DphieGx277v1ubD45cKJ+wRKDdnWsSmDZpGsc5bAGfaH\noudE4EticTncndjbzOplJLHt5jJfCBEQWDY7AxJbJaHLcmOgoZ9EffjRgHIdLrAxFkLXsU30310R\nFoKeuzod+KgdRxm2Y0rOkd2b6WaO7GqA0/hj6bvB8/wC5YdKfqR3obv6OpIkb2+sdSCABQbv/Uks\nvJ3A5CpzfDNacPy/gjpSYy/AH1z8qcJ0C7u0gDioRGTYPxvuFESMSMYbj9iD90gd1D2sszNTZKbG\njmEbRYtSnTUCwlGFjDZckxEs7s7hDDGOwnVJhZXBKoS87vE973z8gl7u/qySmuLnW0+GRgpxEZIg\nVM7SNPIp6gRwHeHdzx1o0gL/jMKwfSSu66JmLXLD5MGtCnm8nL6g7+1RxxalvXzLHCMovIByPjm9\n+QZIPgOYmXhq4PVxOtFrDINSeaT1nydiKOstBUqdqQA6HQX0sC3qjcCwwUBeyhHpdEcXPkHx8SW9\n/luh2dUvwiNLB4zFx5Ngr5hr6QbLh61RjzLp7qPG6lozBXLxg+jK2HAzi7saRezyO2gJ2mOW6wE4\nN7Srsoj9baJNwdEKNR/9nAL7JyTWfidgS87iAC7ml0jukYCt6BCH46x6y8y6M2p4v47Z2PenyUS7\nA1ddgADpbXvUU1mTFZwHA9pmxD0t7+bM/rG+cr1ddga/aLhTqHQ2IRuZpWEdkdRRjSDjC1T+lcHb\n4L7GpoVmpHPfm6DLWRDPPCaT2U5RyC+SoetD718yu70/96BN6jGD2T2I5l6X2djW8yOPusta/ADh\ntEsYN07RvomutC7yDfpjBSlsNpg/5lcbL/GcjggitpYiZ3TntranzRY7CiDp3W+h4OYdYsErKjlr\nhLG4nm6CJjk3uKtrsfUzn3jNttMn3MkriszW/uetecv+NdvLLtCqwci1irJ++U8O8+qPnc5evX2p\nGG5oPMjJLI9maNQFiVC2SQmiLPAt/Qd6t+NtPvXcxTN6Glsq9fL+8Dv3neGumretMmMXbLj7h0CY\n0+e321bYxNf/QOIOe3kaNwtkhbTmK0JUuxxh7t5pZo8Y2c80UUDnQaALarY7CwJcWj0BkKKbLxHR\n+d26RpAphufRP0GI7hleXWPxnHP8bCuuVdaC4VR+D19KFzY8g6PWlOlSqSMng13ogSk/BkAkNk+f\nX32XESch5VgCUV+4HitzNgmWb4wmg/hTXzmX+keJRh8ijOUunLaqmnxarO7sAJ3CSVoKibVsEeaZ\ns1SQohhkDEBimiMnpLvRZdQmoAObxbdRLwL5f6KZ503JUkdcuIBTOUA93Y1MEQAiV9+4fiX6ZQUw\nWgGRfv1S9KZAAcAGYH8fr9ApY1RhyQMUo2Y0HyGMDzzeni99PF2rOZgEQchMXQYbicJ48GqeTI3F\ndq8doOhsO4JiQ/BI7Idadxu8oXhuJmgbhhfQN7vlXkuYXzWMB28ujL+9ZZPw1E4dBXye9ZJrCylM\n2BLg3gg+OWtWF61doBUdvdYdgKO5QnjSZbmf9SC9WIeTSqKw70Ln1y/zXV18/kD6yI3JFrYQYbzA\nqjvheqSBtXuFK9bp2VO/IlnsreW+2crUwMmoh8JsDf9c1eRyJ6oluTpxWZ/d6fEv277ZW5X41Vti\noINv8x7S/OE+KhtdbGx5kbSnbmjSVHzE2lvqBQEgL+P0tOHrLdY1KGvkloknliCIxqQtWr9Qbgif\n00hpXw0vQkO1CEJrqEGuby6tEv1meF4+u3gJmgWBb+yqYQ/ozbNyGocy4SHbSXlgo4zWA17KlaRZ\niAVuiMCV4z/SQ1/1mY/vdZhLRxwfqcYXcJlwduKZDx0ywXqSJzUI/CKn2qdOEY+m2rkcsyD42Oi5\n+fF8uaOClkm4aFC7K/r0IQ1IFVkCceKbzUMDTeQSjn08qigfJTwo8ftzo6q2DtDm4LOvKHReoo7L\nj1urrnJd5tqXXp0hyZSvfvIOkMRbgYnfbz2N5YN0M74BiJFaKbO3AaGv+Zk6iq31iOdpPJj7k53e\n2CNDO9pg3lxMfj3+3KQpgxsGBlVQM9Cpri47922DEiTh6FCpXtgRlHrmgP8I1KH82n3Eu9mlhV31\nlBb+TnnkzT5k+09lBXHqNuZN1UI2eWczm76bt8Ne0WZ+FAP33wXc99RMAUFN+1ENx6mTdM+chMEd\n5q0jUJxn2MfLw/9aio4UvUKzwvlHStNlrFEaBKsksrq3pexR/cMlA57CySfZkt4c5bMExNFzYlZm\nefDrD4jCl4Ulie34CEzoTzYciERoWBJbFSd2GN397YRIjxr5YqF1oEkSnxtr/Kznrk3p+Ec38tqi\nYmqz9n+n8AkIMtXeluz3TVLNscImgCI0xPpxWse8eHPJe4S77vm+JXJapiXrxspE7u+wxVEjlX3a\nwOr9WF9VQbTyuXQsG4QiMOvlmOiz9uVy/qFWGiTp58Xwv9HVbGv88ILzyNbZXtfPs6Gw/GdPncAA\nR7VDLn04hoLUktzdqRYq3bD9ChXVAd7SD26ew7i+TAdaF5ucvSBdI+S+ENDxBypNit9KdcwQgpZS\nNLWfQoUbi+raOIlR5OMcEPsPHHn1mXv8lDbbA3DG+BA2DNRPYes8ruSehG9ORWAnkKSE4HImqRuq\n9bU53W9Udm1Fkzp1XRK4EDfzL8C9GVQ13oBXgrKpz1WYyYq1EQhmuE3kOMoUJ6UNHebW+yp9INc2\n22KmZIgdXQC0QEDfCvrehWfxpwu1cbE4ugpWRMbmHsU87ftpj9UupMvZwmUXwfTWfMsND/aUZgHT\n5E2JmqdzMJ3qmqbmED2dLdixXR1II+BERM7GVjFuR5ra+Lsi6cfy5ZmunNMKs/x4Mlz9UEZv0/De\nXba8W4ck/0YqTa1APdvx0CohzYwL/1Sxu1bTSkQBZxqtrOKM5exRYn4hqJRrAnA8UHL/rJ9Qgzlp\nfZvdyOAvHeA8GZAjMxXVdmRRPU2HI6jdGwa12Xj7YygKGS9EYVfczWgasvhsA83idZKe0Y5FcX6w\nTJBokfd8ppvWidv/oufnJBCMo1WCGFOapWf1ciNxOFVZSuG8lQzmw1ywpMhgmsscSPb5MvZGjmAl\nVbWHSVK66XxLYPn/eY2N/y/ki7+v9mX/yNHb58nIXj98KZNj4Toc3XEgyy42skzfXHY1MucS1a7b\n2CE6oxKI3XtTs5Hmo7l5tWuSTWyyOccOEQ5UNTo1eLukP3vtV2wnZ7CKtTcVocSqZjy7xCHKPbxJ\ndk4aJLv3cVXqnivRvdzwRR0/w91rnTZhhIr9IiD2+kTA4J247UeR9iYwqsaen/YbrwPXkPApxTvT\n9dxVo8DBpWswz0+9pkhTTSoLqzX/EvNH/pNYnkDJ03iFfMGpKc8XPk80yTSYrruUdssLHf+qFoMv\nJci9qGyzd4XKzNZfRnhf3yX6oMjeRV/T2jJUGbdfVnFfJ9ncm6hUxTgKBnCb8Pvwsr+tlantp3tT\n9VM3t9aF6mt+jrs1K+goM23ugLXzGAbH22tCXVuW6HiN3j6wXXAKSMLJZMnh97vzCwSUo6vL1ZCX\n2eyTTMUlJmxK1U6UGtc6fSTlxv3CpgGtQH4rgU94j8TiY2RLzkxJr2csJPG4FAQA5JP8h6dz81hw\naB4gAzrwBrV6GDP5cIcpF4HGyud/a3O3vP8kWcZqSqtSbKl7uEi5Btb36a7pjuQH+PzgxL6OO7oJ\ndHbhFOf6BsZW8vc3wxBcRoct8aRHRr96g5UFrxBhlcCyGKKTer8GD0dGTaJbRyPWk+82Ic+G2mLt\nV+D42fodbF2GmZmJkOhTTn584SReNP1Nlfobgx+KGdU2IOC4urzkZ2J8fx3GTE+RHu5Kr+XBUTit\nmeReDMMQM/oxIWU9zRmXQbBHjfjOgKTP8QvqFsB2FIdep8pUTBZV7VWfXXd2SrvKD+nKbThy+FuI\nrd4O2mER35bz797T9gA++hPi2NUJ4b7SmWdeX1FoOJrPEqDSSZZuxumkrPoSC3CmA0NgG2/v4JDF\ngpzWObTO04aa5VtT9ObwTQ/l4GoAVDjyWUuCGrwY8TkwvJ+tk2s8C0F14pKRk31reEwsxjxFHZ3o\nSlm0tZumDBrJYE4Hy5ffv9HPZFpY9dWhGLzlOOtP0Ryfr8akB/yKhMMmvwwFZEOU3uhEXc/nsDMj\nXG2vLoSZH2biKg5eGQPL1NWEp4prNsslCMhByMXPpIOc1Ls0XTUYkjEuHMEtnlAEw5lYhHOVHnSY\nCJbv4OAEsq0mSZIpCpJZh2QijwMIKrhYx5XfqtgrYTjpTXPVeJh60zbPAqUEq21UQ3qXwklKP76W\nJCbJSeFN+87dc6ChK6Kx+oCxJJ+b6bXe/qztPtwr+4vy4xet5vXwhg7cLNhdg9/C+AemnIymK1ZI\nav0qKq6yngMA55OKbFqq5XHcxQUBcIKqXo4EwQ9fZR/RrgwDsOt/9OPn650SSOJ4nOnUxBjHRYky\nCIsboHKhUw/EoPX0vH8mZFkznMC7KPOVY2FQKcOgjtkPnBKb/hMrE6po19CL0od4cThcHOpwx4ff\nDzfMdc4vKFHRO/2BBKnbqEWUeUss6obiyD7aNUok477+QbUk3X5rJbHhYB1sZnlajy4MZ1b1I2XH\neg03QCGTauCXVScO+9VoKe3UBcx00NMkHriCDkOozGXlxlK94b3pbSc/CjyOrSPEsTm2WJexf2yi\nXNlw1xlp/HYSCIWoilRZ5dmo6EexJBqvC3+WA408Z6ONQ4Hj6cVUFLIYDbLOh+KpchD3ikkpzZqV\nvylkfUuOUs201Qj9IQkMwNmQvNmJmuIoj+AaBVKoKO6NCHBtqK8iw6rMVcKUcIV2uLTvQFTC6BI0\nXJKoEj+Ol0XYP09TfIdMzTbQ3f3ufV/9urLWsL8Jlj4ETJ1Bw0OAUZz051/hOTpPy8NxrIMI8W+L\ne+ZiMU6NdSv2cZyyIaDq2sNhDCTKRdMzIMbsRr5fqEp0ubi/sptTW0jCEOzlpmZ/nJAdKvOitZXA\nZMRTbQU4RbUh016G3wxJ+niqU5qWY1Lov2s3TZT9uzXRzpRK4jmGc0dVmH5z9NPTfresX1NktYmB\nOEaEtLtLTQ6wZ6KRzJmd6mpq+Op9+G/FYMKVK9JGZELQx5WOjfR5agcqUTVSIUwILOQK59LPSnuM\nh8uGXOcdFIZ5HulwvHVhwmP+gD5toJvOK7vLfdopsvK/6T14y4x5uBXvQhhDtBiEFyy2FZXoAaep\n53I+4kUvZeuCkhb9bGCvwPzWnVjscajacnQrSRtjyugkRVltSQfn642+V0DU5clmT9RJ1y5zyAeM\nMoLTsBIYEaEzro91fY2YF4M+b1qmrdWOg4iKoD/h72CfA1E33eoVCaCWv4WtGkJX9/I4/sil87qC\nvtkYRQe5rvFyZ+pj9ATXCLYI/j0Zts3t5pRWXTonx4ctOES7TizMJ93jfcipp3+idhSHQxCrZz5E\nXvQtRavdnjzOhek/ffJaCZGyHllphfnMuXRD9+YbPQ9e90NkM+J2wWiVjwV+SBlJ35LGvqa3w9Up\nmc09UFLFXFNzvG0u7m5mAtalfZ7/P5wU8CsCATBlmWm0/GiL+T74FpNclFChNnrXjWxf8UY2tssJ\nCR8jZeclach4jF7sBvMZbS4YwIgYHzne2PMkyA9h/fp0T2YKNXozT+Y6mK+ZG6mOBrGdFDu4/GEn\nbREhnJ/mLs0ORx9ukoFZnHMsFRmKUYfYrm38pOmtqq6grAWDmYf4lLZKi/XKEje45O6ICV63rm0f\nbuaplVlXp2BxM4iGaAWddITjbNYTGFwNBTCHl0rFubZ1GiAyLlf+Ew44BhRknlX3SxyrU4DmsnsM\nHd9fcbskyMzCNkcqm2Qy6+M3OKauGvrwb2EnvFS0wl8m5JsLr65OLaS9b0Q6hsXwnGOhNsi7hzOm\nzIN5CmKnzF5ULc9bg8fKcITtG0cZ2GshF3/US8OmNH1z3nGkOtUvBXaj9z6FM5kdlK8EA+ficR42\n73AFkVhZ8cPHeFwVXbsbL4OdQUD5Mxq/E5E7I5468gfbQsHKO99ZH1fa2+agfg8K7b1op3zuXOB9\nvNY5y2o0k7CK4IGPB2N/qrb++hhaKPgrcAB4ZlL3gIpJOmcM4I6EHbKg9rxNVMC4UnD+NI61Dm94\npLHi9HSPHIpRcD5vOT6pqKN6bAFwUT42pyNUxFiyE8l3SoOjZAiPLKiCM6ymRjBssjZDtYzQkfbm\nKkUgzdP9nLnU42nTSB3IGm70cS/BnyAPCEgtBHy5OBtrhUjGIBNcfBnFXW1bNySAWswPSxWww0fV\nBGQsRDvyJHD3oL9dGfyjJAgLWvNJUIjIVqQfbwS8zAARVyngNPxelrhf4zpVZqqfbzi0mNNlEHt9\nMUIsL2jKGwqluOPzKidqL9/Pg+5dFY7+hcMb0XtGXMYyZ3tUcd5bRB8xE1n8kwafz3/ToZS63Sqn\nFGlLu/M+XG+Wnd+dSxPgAJLDP2VD8SUVXBeUKNHBwqCtiaHgcOHp1ZP8ay52VzpraGDVuRcOp/k+\n9NspOCTceCjqpZF1e+U7tEkcxDJtOtzb52y+NFEFLMQmXRydgrOQlZ3HrTQMSYXDSdnG3WglpmO2\nci/DGIJl9/rphlyanvDOxyGWz4EAlh1rOCQK+h+xAHZ1+a+Pmm/rX/4lRkQxzym9S2tPHiLzOZxm\nP/gWZ9keq+o2KE4gRczKklhTRGFB55k4sR8UgJ+9+UOkqRAJzbzyFEBfjo1CIAB/twM02OJoODae\nHK8WGxF9GbnM3oTGE9phaReS22ce4bIUA3GQmVq6xHC+tbMFA9Hz6t2zzoSCEVH934Aw3e4vERKd\nxF0BNO1rMFXQFFTdMzmb5jINr2uBhHHc4vm/pvJi4s5ApEOtoSIta1mD56UWRDL5wJsjVxIAzLIO\n06gN6oV5xXIclGzf5fvp6Y1X96NWHJOUiLVbqKI7JPQnn/VRgIdzIoqv4XQKf4hNzli7ifuM1t9i\n3GlGs7eAL+EW3PB3BExzfeB0MzBJWGbfwryTM9fswZhqWX9e7q9RhATWxri9KJI7q3U808783Sgp\nbELOK+MbH9eraBjjVnXiaSZGJYBHif/6BDONlbOF1py3UsAhLNLLN4JG1Bkg6eviaAQCa8N+eAhE\nwpdhCouDLiw1Mh/mp3Nh532sGwGN3Jqp2HA9gsU9kJ4zFAH7NCaDdmcZ1zSYl7qluV58iVOFgX0b\ncaB8zAm6qz5rl6GOdpry7SUhS6BmhCjyQRNH22B8tKAnAf8SyGHW3YstBN2qy0LNUlzUwR0vmmE8\nd5PzLZN8SkbvaAJ6+Iuq8A2SSzaCOWgsk7w/dsmk8tl32lyQCGLYVD6tN27tNeFfTAfySvS3bKgj\nHD1dq8HrO0kQaqLEwj4/8I6RqIy0sWSPFzzNIt2vHWEM32VQpk3NSHWJj9adtdH9WPf9+4TXPSxQ\nL198riEPY3PlNLsoi+USGSaWv30TzCxbk96NSBsUTt7JsmJCls2I634zYjRq65ixK1nJzJJTzKrY\nCvbs09s70ryxgr3L1p+KJfrEDZPviWMJvUsnbEREmYrMLIa09CMkM7HJhfx6cxhcwgg1Okb06cay\nIK1D8/pRMIqK9ob/XGw0OYkMTgzvh5WCC8Ai0tD0hoI6Dql/Pyh23pyQYbTGDQJwSEKxhrEEmU75\naT+0gPcUnVisCUQraInjAiJSuv5ICWhC8szE6sPdBrG8oBBXMtFYJKyeqZkgCIPWH238htmo3IR/\nkUo1ALNvpas3VocPatC1qGTP2Rsoo9/1oAqfaWrCU+EhyOPT3gp/SpF32YNSAOmuS9cbmEbdwR/6\ncK2yL3JMEv4ZgDiBPLIee6tWd/mVwfGbZhGfeFbk7vBPTkNHHafDu6hWQyjqEHq1XD6p3L6vQZix\neuSScQBu78qYICoGP80xDAVpMw84pfLdMZ8GhcAVws/E21jS3CgAqcNc0OQ23ng/s8e8jf02U0Oc\n75HYlCT409Sja5ubt8GtZkPss+TGatXm5e20eDjYFkjeibXiE/rniooN8z6ZgQV+25tJ+1C1mq0r\nzCpd2n7ka/HonzS0fTDg6/9DUPPs3pjJjnjxLeSAzPpK9MTpqJ5I0v3PH768gSv0nGrNktDxYI5W\nMLMd4zjHvY4drRHgiYaHDmREFnnT9ueDW1NFg4eXAfyFY3nfGe/YLhMuT2UKOcCf/vIER5NNJNoI\n1BZ63euq5Df/xCporudwJfV+l8hUeCj0FlAY7wUbR8l16tYCOjPYmKJ/Mphikr/f20bejbJPCRnx\n32Epp6FQwRq7tI1ieOCyLhuZYs2GqVPHs7ZYBtSIMr3JnW1ozD7UAytcA29IVKseiNMiSjAAi063\nvuKYH1CTpfDjJqLl3QAhMeEJ4n5aLSE5sdKsB+K6ycerV/rbxibOQOZB4xGGwliz5uTUhfPsRWLD\nsRpX7h1h3N/6jxkCJZ5tGI2LAPFRnK1QYZzJ7lDZB2vRhKAof7yXP+dCU1SMiNbVjo/rN183wQAt\nRTPhRD69IxdHx2KhkkXoy+XVNordIRaUxuxLRyOxN/vvj3Iowoa/kmrLBldefBLZRAFK5ux5vqAe\nq+T0kSlI9HD218JPKTnv/jFaw28l8fNLdSpfjKy27x0pmunEtJfxMDPAM1tGbs2wO/quSP0Aoq2R\nixup3kduBlobleX/DNLpCmaj9Uea6vudXdB+8qE/Ru+nbjGlu5rn/MtyMgoZfkb/BR2x6CjADF11\n7mQ1qmsXmqdjTOsn0IiUcszUK00gIJZNHy7rn4UfTLksndlyPvEfvpkpqeYlxL/nkV29i8ukJvWw\nupPW3BkLeaO0zctuQG2B+k74qGdAfpz4fzpcwvhjx0o+bMwXSj3sTF65RilAJaH1SJqd+gCy4MbR\nP12X8XT54ajS7Hix07uEZx0t5RkafBSrF34Co/Aa3NCYFwJH7Hx89IXtPKIajips4tDxEIAC1lHY\nv7SZx063NpKKAV8DPus5UntydvEFnzE0m+bpmJfFzb6hVsZeGoMCplomU5TcY9HDL7YT96BT2aZY\nDZcjpwKOA4I1F94AKqse23UC9upWjyZ8ICIwQidfqCO0UUX/scTKo3fw1ZXMOBrK5CVMMKq51ch8\nF6eHuAHz1nNFejctVEvPeFMMZUdxXSFYAwy8IiJqvWuZiWGMkkilADHkB2IOMsJrF6dCGr4kra81\nZvFci6wKys3+jryTHh0orI3vG3nUL+y95IYIz5H1yMzmWM95XHJfqiYBxjzhzfH83PZVqPzixro0\ns/32gIiPl+WSCHvMOaGQWeMXsJDzSNZ6ART+x4a2kVryHKh9acOmy1ywwRS8pjjRErO84eVr1bnr\nZ0Qxm5uB1oBoWKC7CFLKd7YUG8XHSmMrXQ3eZI0P6sjlIcw6oiwsFwPfBPwhKX0e7FGhr5MkpUxP\nGF5s+Eh73fyUj5U0j3WyF/IAMUGMkoWTkpUjGHK3JeDYqNiQMDIZpnG0gkhF+HSwDvGsNzRmcc/Y\nggQtoNTtCn8t6JLfOLpL3g+TJRgNOSOhW1HqSjtrHgXBpPfR8/4vaMF3rD0LwEfVrh9RKAnlwnYg\n82ZlU7sRL0zGDVxQBRalTz4bMRILk/ih6vajugFvkYmO2x+kEl0M67VSKy5RzlDwud00DZslHaJ2\n54ygvNbDUuxx1VC+nOUlMNX3jXz1zFQZp7JUe7+eiyRLIPn7IckXTF5cvT4/ZiKkgIrVIz9GjzUx\npXpEO/uGU2y5364XogI3znqwtGe+J0w4e1loZrNpY/OG02qRIEwVfbIY3X6I9rUqehIbDAiNNIqX\n19wIU+Hld7jQufZeY/b341J+sWzy1pjvLKPz7kboM14Da6y/IuCabUI6scndVxzU1Jb+J4fU/NGB\nJp40fSw0iDfJHAgXNKwmYRzXZVYAk3KfjR8eeIABceG6o9VOx6u4Dh810HYsEkIPckp5eyzFtVEZ\nJ59QlO+dRPmpw4UOb8x2QrkhPoTiFDEEhKB7PGHSa1zS93ARo4c3m0yMRuFyAR9uOOpC268Zef5D\nnheBtKj7qmRI6hXYseSC3u997/3ZLg0ZJQFwGGfnN3SKoCwA9tLNmoqvvrPYHHt3pnW2paQMCIJo\nkfGP4qSIsI5ADDaKRLmtyKUV9ZZCsQoAkrqJHmFGZ4X3/HyolUkaOo8jJ5IxzkxTJM4YyGegEVgw\ndMMvTSuI2L5lLUb1k9rQqfAnbVAg3mcq/2inaDFcweif+N37yhmI2xmUpmUwI13K7xiFNPwoOUG4\nZvIbCSeFIk54MJJI8V30o4qRRzAm3UzXKorn7Ax953xwdBKU9FvqNM60lwdyu9diGvjkViuH4cS5\noy8VS99w62Lh0slpduSCxiKOpgefTDrj+HIJ2mzgSm48k+6nIAKcdp6OvYy8rqK6yazwGDu2yX3U\nmMsjXXPekcN2zsCCJdH0nfqH416wpBrJY+9vQVSYGSbLQWAsz6rEnGA858ql8D6KFv+4Ht/Le5Eq\nXUyMclLcLtUpld/MdZl0Rkx5hYj0eJNdtLjk9pj9mk+pP44KvKs/kOa6fpdPGGDvRLrIKNOAH5aB\nAjejBHQoPFMinLhoQ3ez7qCbNuVi+ETE2bcZ+bXETjzoFCdJuWXaW9AhcN9mXjPuaTnFMDaOHdzE\neYA7TGHxMrRkk8ZcsGlt6k+HkEkIQ6wljBkBbQGdxvR7QPZ6qs6XXfZPrKHowx8GBKqOsVoixoof\nrBV8kTSpXEZqafIjwQ5r//tPTmsgnpMcHUaa0XLYQo1Uty4RqlvY/hNTEezsNyDJwWKbHVxvnzue\nRf+v96HOwHkST21yQGfx2KFMjt7Wou1h99POMFyeavWFz7eRXC6k9LHWOBA/tWYybx/fvjZT8+p4\ndioEm50GDKnPziLt1bL5I3fuTSMG8wsWtinfPQWJqHbRIYi3O8O+UMRPVex5tgfRduT7zjnxeSeg\nwU2zJKvYPPIfkhrlbk8elPhhccLkWjLtjWIpjQev4cBBuJ3AtQGbTtZD1yYAzvJR6PlelqxUmL7M\nfA5M+zdhkd7YQQrJHzumYyo/GHUVNzsShbVdN/7IUtM8/ENA2YzSVzLESAqm9N3jcMHZJdNCkV9b\ngJiUlmiWxr8WfgPbo/O70WTNxgOqH6yU/wvjxViSlwA88L/dgI27Hm7IQCpovT2g8xO8Lv78Ivve\nkeEXePJQNzZEgQmQD0agO7PetjaQBoPAnNWROXSThmNjHABycxD9n3qPHZ5pdSHEXBb2GmHKHyB8\nY3yDtQM/6HBHKI27sFvB7NY8MdIn1botLaF/F60169E0FW7GGlu2Y4jK7+7NdZMfBasMpw66KSHa\nLs1d0X3ISLgLTA1TvYuq1vZtwXErpIZZi85kK5z3R1UqH6gyHNEfgiTciJa8/DQ2QiuVPybw3gMb\nIPDgednhEpZn+7aWYX7ePmAgAFRZHnPrIsRfHAi7LTxOHE/wB8hZLsSUqFgT3J2qVkLKQN9zvf1B\n0kbHCDQU68oIbqE2TKMnMmM4zqs++a+utOwflaCsM5VDK6KBDpueTTSSNRm76ddwhGbHYpyPtvLA\nTfp5teu4BVjB+rgV3lxk/PVA0eqLAHVNAucre9j1N2Ghdb2jsZJ+PF43wo4xMzJ1o+LutCcNOhvq\n7UzEMA2YUYDdyWjSAPaSa8GGV4MB5DN3E9VsjIZJ0tW0to3BiatyLSCEboONGvZETrAbF5Hqc7Dl\nmcvZa17WfL4vWtDWpzoY1bxVDwB6CD322xRMB3C9eRSRiw30/ogGmFcBD5xbw6psoGRgoJFB9iRg\nbvqrM1NZMIUoUrfLVO5OeszpBjw1Fkhz44OvrOduII3e5rV5b6nYCtCyB59QBq9IgFVUo80sVb54\nndy6Qn6Lrkp8Hswak3GdJHcQeYGU6nF4/TUyZEJYAN75PkHeTanler1IIUYWww6d/OsWD01J2APu\nQyEcfLq7EFyrrH53Wz+XnpYy0gyGlw0dqshDPT/sNb0hTMezbR8skGmeTy9IUT64Bdi0I80OkUvz\nEhAJCRIcKBiyKMthZU3vmeiZhNlqOEY04bLjaQMwzHoXHa8EEaNwaIwnQ2Kv65Y6QFqiUPDloHHS\nHPAlfRTgRAjpFL6/SrwwmS7/l6hfMvcQ34OF1TM9riRqG/5kCbWwXlgbSW3dTB3PyDHdWePclf3M\nwxgYczqlU7EONsxviPi+14DGA0bn+8de74gku3JSwLu2RSKPJNvDNMujgyU5YcAWf/vNxJs/b5cJ\nJ0vvF03X5x5GtvVFYHvunrO2Em+PLdAhVvs6Ac2+fD4xMlfB9a2Czm/ta2MoJHIZB8RPUNZHnVro\nnO9+P71DsGgP0OmiRz0k0giRWD/0dB0sG5klk8lMGte89zeW5KYczOpSm0ZT7fKFxm/GnU51oHG0\nOb/2S+JxcgtKluA32lXNUJiFTto9k4cMWkh62m820FzW+2SF+6HIRZF1GLvl4NihaYGRSShd48Wj\ncKPeFbHpOsaR/cUc+jSk93AGiI8IybJIUckToC2HOMJ0aFcd2n3HLpPAfbDmdxrllOQaVG1RJa5D\n846Ky38IeLWHQ9SZLO1n0VNysK13Mp3tB8rvWcakMwmLevuVxjBbvElcEOOLOaW0VdtaO/78ncrD\neBfh47N8o96sKXjGKoWGkDzQhubsyOQ9UYr4HZ2ioNsYjCE8Dy0w9SsTTXktPUhUoxTt4ep0JvKX\n2gbVvUMGzD+y1kjyoa4YjXSUPdfRFjCP946jgKuwdLSK5+AmK8iV1v8V0MLidf621cE0SAAN5PEf\nAQEXgx0HuMRQE8jmoRshoem9m73xf29OkfSU41rehqxetzYUyfD4P/Q/V+7pWKtOFphbP9ePVYml\nFMdpnRFlom7M3IwAMGZQ4X8vnl8fFmg23DOrFRveTmwZeJ2XK68ELX/ddHvH7x9nrqgZzq3/fcmp\n0z7Cx2Jk9Irx/6AM2FcSp3qcptaiUpER1XclkYWj63fo6QlsaGkeb2V0j47d+ceY5ZxXJJlAJmgF\nCpubkxBUShp0KbkmAdt+pjl5fsN/7u4Y0kbMdyBZ+4DM76/Lls3SgNuyaQaFeGtjJHg/EUpBtMQ2\nU/9zsvrS0o01oCptqwzZ/i9HfrZMP1Jfjxxm4MO3TejIg5qYY0kd+iqnwimpsA0EKT2nPouK081C\ndfWJr8fA52AKWSToPDDbOa2UsomfwH860DKSix6krKjcTnh/4WvAveFXT6CPxKBTwXBt85HxUxTm\ndyBSe5y5vKswiEQ2jnqpItZppI7iYFCO6WP8bmRzGlXaFxF5WddmVXQC3MpjHCn20pob7CUrYQA/\no6/Phh4xmczVe3stMUilTEXxIqzAsSuyPv85NoFL+a2xB+CXhNlbATd+Kr/qj0epeYNTUiyDKaXR\noW0w90H33XHnzJjEcHu7HMwcmUSNWm0enHo/EmTAnj3oDeURvUvGq51igHjO3qT1CbYKpVpE6sJ6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vb+RKHNRE+QGUZOtmno5Cn3ejpupJixruWhB2jBMYv4mvZxtPAZqMd1oMM5h71NoPv4inr\nQG5yNE5KXNO9ADSck+EIVokFvFrij+f+9STxzc/ovEH3oGCDqIgsav8VxXfTx3Qx5tj4qaatzS36\nlskdgdwkNAphKd47mazff1atLaWJAAL8u/YOr8aHS1JkgMREpnCyQyRqK+D/9EXzmDz1ir4HSW8+\nLWW8cjbi1NC28chQSAli3vJu7nc4K4yO2kjtx0qbIhcu8NYuSiXC8CEG9Xt9k/i9kzTas6TyLGoo\nRi2ujW+jsPaJHsBdEQulpveRdUqiev3PKYcqmgvhACvLRD3mRfjq5QysVgLrSzqBfFc+TZVYm7UV\nT+dfSULqoBpLDPPTQvmtdWPA17wFGzyAx2xTm+62Xr2//D1AceECLMG7hPW5/vgrROlhZA+zFgWX\naHXQv6dtg0DjSQSMmvDWiuUEGWIOgApEqQxgsIt/KwOW/bJw5/YFIJF+gWoF9tR0UEUqg2v1NqRK\nStmVkjV5TnpMTPoOFddIMk2+Xzpe3ZGLS7FBfKeaCFA2tzgbC63L9+Pw4nP1APXREK4L+GAxUkbI\n6eqmKwnKjU5goUpy82ChuGgdrFSLzfffJRbrkUTJYRVFMqfx16zY6mm/hIbjLNm4WGx014/dQ7C5\n2Y7+IFnIU3L6kLWVIkmnozE9228edU++lya+ZpTc6V51bGpPZ+4uze8iMXTqUzssyULqR7dWGkn1\npxVqKU6l490a050QRRyiUbfg8pWA6uXKRW7MdTEnZp9XkKg4ShJDR/SPtT9VJoLH9GdjimQZxHUY\nfk53v1W7J4ErB1xNKybRf8bsBFJXEtpBGPYRdHoYNEaPN+LTepT8i/rnB82akUcDdVkEBQUUbPzg\nLZMnaNAqRBgmtlB33fur8BchM1Va8Zqqs/tE+8MkGoiO24YRtwZwl8Riwg16M9cF/t2BRc/6rWAR\nCSzlPQ7myaNdQXQIrNEIAKX88RjrkA3sAahXVpeZDGq4FUed7fPOtdzfIv/UiVTnyCFyJXr+9hZe\n382wbkbTgcatItJZPXokLko+oknY+77DryAiUsb9BTLu0cb68/rW94xJbHhLeE8UwlTZJ9cp2n5X\nF+moHDyvU8rpMR9jBcqTS8PXfxFmW1e+QjcDlSj1PPZjzeA/8kC5pU15s7Piu4GDTJQHjvl/A0h1\n0TDGXEsO9RNfNpfzF9gMICG7FeQvDQfmRv9i84SdyZhnPjraHlUNJrbK6DBoCrCWIUvi6YIvGxOz\nq5OF+zX9pkKMDKue1HKuF4vaIJCqLhgIsCaWi5oYSqNPcY9Z5eU9VckrrU3KK7XLbCB22yXi7ssO\nuCMwaDCaBPgHvr7p3wF/vOl7nGhSaHuZm0NMS0p87NoiUdl+Ay8Dfc8ZeCkLFc58FmGkAH39fxkm\n2WlTSgI7+Y/hMRmnX0DeXw/V15A1l6XhNqJwKtFNONN0dqgYToF3ebTpokLJOExNp8hjYo71nL+r\nelo9YfGtaYAsSoxkPYK6f9IhwcaPJZLPEmXjU3aveBSKTYUspvWSgr4x+cXH12pi5NmV7BNLSXoI\nlI6NqbaGnOK4RKg9ne41dc1bDJWed4iTl/88XEzW+rZCqOwWqno85DhROanBSUknpsSyZHC2wi0E\n3S9jj1yOpsAFTT61rN2woUCsW60XIVODMZy1La7WN4fiPCd5O0FLrDWmfjdttuMzX/eQlLOe5GXH\naIUsF/LpNG+dqey1x9eOvEeZepZpTw33hBBuD1VAKknpSlBKu9RhBbdw6Xj5j1cdjbgYnexFEzdy\nfY51Z5A/ax1mjEu5B6/8dHjzI5ei0NzTmxuygbc6MThs24yK1Oj5H0QV+vRNHIn1tY9LHoY4DOZf\nDro6dtGXo+RsloDgSWfYMpn/g0d0O1k8Nf3Sw7nfvUc0OOuQZeHezHeCBsLBVVHFzTd15yKCQ3+o\nH7ypM0c7cEZw6G/bcIQclaMsL6QBGPbebXaath1c5A9pmKRcoHSCvVThLMhz2zugx1M540u486+5\nmUYpXgKt2FP++v24FjHLnjMiCBBw+dJ2BZMlZQR9bcWsxtYHD3aht7yJGIoUV7vAbu1DWIy9wHE2\nZTxYg77Lj7SVLf7df/n/2kjyHUceXbd+Qsl0Quycf8MEjhMwrSYKcnn7Fdhu+TjKg8i7C437KBZp\noclpUxlTLBjbPMBqD/lIMnqufpnAuUjejfDF5jsRT6HhNfMFWzDfgVIxk1WW9xGSIBFTYkht0ZKu\nc7FClzB0aZLoC0K5+0yN6lp67TZrzDJ94nAxNqq+J999GGQMQwTiNX1UKgfHhG91UBGggT63JhNo\nzqKkRFJpBbZma01n9fpQn4Q97jdX97zzfKYdQz2XRtAOq6PBZUntWM+UEFwZiaHN9yDKJ42gELEp\n1s8iT/3UFmRY5DHQx2X/sWWiROOfFqy0Oc4rvKwTdVZdu64rPSDEsiizrJSKs2phg7UttpkU1O/A\nHyaStUH922Ctx0/k5MRL7Ukaje3pj74MT0MKPIMZHZsTpoqFS/hH1TRqNYWkESyfNpYi2qolrhg/\n/6UBhS7bfVFhKkRDPohC6I+0ryLxvkeEIRvFYV849ZBDdl3TATE7svdvyODx9kv6KEF00NnJKaf8\nI3UoNS5xaleIKfA8hI6Ed2xJmNqKoKOuiGk9asTB4mvO3rrQnsTOymWf/yMW0ltyPZGIQlZO0cBl\nXU245zb0JOIVhWbLSrlKmm/Qs8z5201GAvnCLZqHL7IwgMDPxnTSQrLUxtcbsyzM+99qYu0wkoue\nU/R7h2cMq0qGMzltfJm0m6aP48m5VIHvof+ur2TUS6xR0mZXKj99B7DdaUb4ajQetQWNJF24GgGh\nnqWs/s+CO6Zq9/mXHT9nvPXV2yIGLMkxYza+LYYhSuZxfmvF2GsdkDkDLcLHHDag6JiAz3WwpKsT\nKxDmArr32q4VfD5hkFOIrMZT8ArsrJwGU3NMMcsBarcWIYZswmcMIGXcOzjaZLhGJl/RrrAznzdj\nS+i9qaC0Rz0Zg3LGUBdXZu/9x9/7DgYxoi/+DidV1e76XE7fndBuacnx7HIPiDZvB9quKgZ4s/s1\nnVPfc/45//USvlXNVjrYQEC8n0Oc9iAvrV4DMdVFm3nLpaltwLFsZijTSqAlyYFdUGQ0ZzTvdzeQ\n23p1hSRJcUIZdtStSxpODuCS2zBdh0rI6mTOeh65dcJzVbaOmKkIwjwxuGAHZlyL7BFZbS+FYyjE\n8bGpgbTMk6qxMAF8Nptv5n4ApJMHQ7oDgbhvClfsShEtJ9NI9bvFiE4KcUfpNtN6KV2JTdYZTAvn\nPYqd5UzVHUfIOol8W+DMqHTb70JDQ7A8qvpKneJV6JVxx7yPh7LD3yjNUzpchBl+nUkDOlne0ooM\n0KL+mNG8mwaLu5mp6c7iXZjH5L7x1ALK+xRzXy8sGnSuWqT8PUYxDbfA7ZNwJWIWUy/uRa+ycafT\nVurP+c2MAxFfeN0z5Ho+Xf6k2kng2ZpznxoqgTEAVIn+x3F6kDtC8hJt5PvHFm8ryuQuELHns162\nlMCctjws0wDSvui4uPElRqvOUjyxGOUxc+gHTf/BDsu47XvkEuGQu56VCodLCwYEaKt311U5hPei\nQQlIohpVeWcS0C0+uFfZcm8J6n5JSHIL0xKXiWHSIrJaS1wHNLxhe62rQMZD9IbfNlwZJO2+enla\n/2Qpvzc1UzCb8paeAWVfLORZ3NqyJ0D5of2UDjg8KUYCZLMs3poe5ylLceU9Sx3f28iRr2uxQ4OC\nSgzlTESFdXKVqgtaHwBWjtXWGkbe2czwPwzKYrSczkJTfMCAxH40iNS0peMjvC/8JOBwFe0zpGT0\nGJ96FCOw8UgYxYmA+kgEdrKfRvQdr48Ot82wlZtZbdoeQw7FkBIcNu2wl015RafC1mQk9hv/GnIB\nfaFyUUU2kjDpSm7yv1kbqHz75+njbjvWzWydfRT/FHDyEX2IQncw+4hPW9amBCWaideXkZK6tHwj\nm7M1dU68LvKPa8ne0MHebX3vawQ10pbvSi+mA51M/lwcdXgsO5L9TDkMoDTTCFTxsIaGjW+xb95V\ndVaqgMgIjl0zTNRJUyP78NxoC6T99Ji1kqUbCEWme+LHmkBV5n8FadB2Lx4PB9eFoU6fyxUb2Rvu\nMWlJL6qeCs2nahBow4bq26pQmSjPBWfoMRZIQtVsN1s9uywDOlT2G2G2sDD8/ATFUsStm8lvpJ1z\nQ578gpHSsphvcHrASIi606rAtNIZK4A8QSRbA39rakiOlPmK0w+iFdC+kTK+ejXRS2jVMpDx+JSq\nPGEsbWeG3EJdlMnXnzmj+DnUEqeTDhhDgf49WQRf+MfCb1zRJXeMIegTVXw+COPXCB62fwBz29bw\niNDfZbjmVi6sXSUn3ephBmfmuJzsHThUzpq728YchlQdEMZDj7kq9YMMPZsRi7xTcB3+veo2z2Nm\nsfcULkwjSd6FQS+PN32T/hWgdqAHHQ9IfEompDM1HKZhTg825Iju7ayhDhNJgxaDojAqMrz6ALwd\n5NS6APX+R+YVZsvC8rjgAAJaSTDS3od1FXtWGRkXi0oqiSwFpppblVu7WaMKeonTzokdjBouNmA0\nHTUC4FNjP00rfGpSJMIIuymxQelKDfBHtHhgvK9baIdh0jCo18CccDe8HDb7XzT1ZtBEplWlLmjz\nq9RBFn4rGnJl4TQt6Vcn2oiqcHYnu72pDHWUxPbw+W3IkIoBbq5THSRGXIWioykVX39MZhiyHKsS\n9xfzEXPa2wQ33VvsbypyCjiVqOZR7mTX2gpjvDi1lQREmQKuF65WxOm+7/wIJIGg1zyGXA24VeGx\nWCtjBnH1whm/TERxS7h4OSn1GrWpNi9nbO9beK6bPBAYgg9PnB2Tsd3oNVbgun1DbWNfm+DG8oRf\njnK4rZouQF1yVD5xZXsy0KjQoB9jZCrOtzQT0PkXyordmDMN6yFcVQqOZfdPOTlpWe+M9useAlu0\nM134FIMcMCajUwyiEreCetyA5BJD7vkSkjC6aM2lZIUTPYeiGai7ybTOLWZGf17L/rHtP5hX18+O\nfYQjmXZ31Vj+A7avXhbcIIrggt+rEOChhTnaMlLFHHjZEija0+MrLDQpdjQncxywRRVSaI+eihg6\nbVV6xqJ9Dm0tb/g+FqvztdTBy/isAMR3UUguSQSteaiyGu/VRxj0uqrqq/L5v1vWDHuwLQ0bssEL\nurwFbkiBX2vLTPqrBS3/gPfNgmZ425avd+lqUlb+QJ5a34/gsWGtQZHPcIvhVd2mwFFN5+JnvmhD\n0raIB92PWi1kaKTAMuG7k1jQqfUSVB7/7BW25lL69tktgjOH0kuJLVNlMmunCVcPR6ZfShMGpVkD\nbcvnJIRJTMWqFyttW6e/ehKTCLWllkvb7Th9fTx8kM8c3fpc1PddJsuiEPbwrQQT6zZLQkOKLKT1\nuPB8z+SRT+fDoZtX4QmjKb+m/UYEmLxAFL0hVi7yIftqUs3dkT3S3bfeABLkTbYhLJLLFoDCOxWZ\nEqAkmbxzb6om8D/I36vNvRyKyjJpHcjxoLuFCs6qA2FgFrn1NcgtpEDpq8Xu9t78AOb7mvfBQjn1\nwnbj098Wyt9SDZ5gxlfuF55eubhAu/S7SavshoQLhM3/CHIU1UjZzSSZlExN+fadIsj/ZIKLOES+\nRtItjPKj0INqsOTeBNcPB+dWQZUYxIxmuifmb9qw6U30EhebNWHZbQjrP+5a4czmemif+Jq0O8FN\nCDSMdE6SVs797A39K0K1XkAQoQdxo0McqQxH+Gei7MmsP0/HYb6XIkiaRONT08oP4r2amctFp03o\nm6r4sjjo5aedmgDb1Hz2d3Hj3L9uwYIHcVRgAaZugf6z8zMnPoPOsv0D9TMY/UDpvpRjsSa0yCv2\nPUttntG/0ppP5YfXnv4HJpO/+S7ZVC/slVo6yCXstJVt/sZe/XoS0h8vjoPeBLL7+Ju/6//rM243\nzBK7wM8+PmQxeT9ODJDXG0F6Hq0mZG7dy9lCR4kTT4F5BPumnM9/6ktJljEJWqbPnRXTZds2yz1Y\nOQ+A2lOF8+HkyUbrXT2oSXfJzpqnr87gVdhwOVjkRABQUW2ROs3IPcBGNLVoTq6hK3M6EOuE5WVw\nyf9UKVs93hIBC6RUHMKgREvWPqrmrwJHTyhlakIF8G3V3A9SA9VXwi3+f/5a5h1HrTA5iuAo4klm\nPn00ROLUJDRxZ18eCEyoxfByGhB0Xyzed2pLfex/Q0GzSRwmL7qb9fnMBqphUYdX/sB2zwz2Ggdh\nI7lurbbR7j6MW+mRCUjRuJkQmx323voYPnFC77nPNKYSuhVfkmmd834ERqvNItY+sIS1uObcvtR8\nE9tJtaxsW+QXbBP2e7rrkDOcx2QXPh9Psd247vfq8sP5D7MPRiAbPhW3+3O/QHNkzz9kYavF3W0b\nCSZsZ70bG+z51ByrKSxOfhJuK0cNG6PIv4j5fZzl2klnkudX6E7Lxb6vVjh/laqoPQsHTYKkPJRH\n3QXqs7Dry3zuutkoN+G9YFHas6+z0jAmtAee5vpsPDM3y6ejiJEZRjFv/BvmbNLFFgYSm+iizTCp\nU4spuCgGnue3N2rCDN+qbg8gD3/CiqNSZsyzAPmpqb5N7sZl7izJA9QHmoMJ96z4/oxEYjnfj2Lh\nq0JDIL9g99XZ8sDhQT721tvFj3wBtyiAcuFzScId1oAfuvvNK3DdoIBaOLV4mtzFBuTxOYGeuKd9\nzEJGavKHL3y1k8VNWExLMA02UNu5fijIWhlZt2JVZwRtYcWmmlm/ed+aDf7aKEH1fjPVjBrq+YOn\nkPB6wHmtfHIwIiYhXSMmQlYhkG8fGExKN+9A46uhPzCy14cl0iWV1NqY2kA1jjyIL83G+Yg5JWq3\nJBmSPIKpy2D96hF/G/1yqzqov8jxyzZIyRVzlzt8tzQWaKzU0+RR+cEniqzqAIxJZ+MUFYl+DlJl\nI26hG1nZqzk1nu48Yt5cYm8bkG8rcv3R93Qk18lUUkyg8Z3aJ0CNQhWPpH2YcS32/tth7XIopJhJ\nLlold3OTC5cLjHptTDhtd42llY2p9vAw8oTazxqp0tM3hwP1+IhVc+7EMIv0OmrL4m4Y35GKDmHA\nGsUcjUhepKJD3bKhjIEBp9bD6jZJec6sov/y8hboMjqrYwZFBD6HqKvg2tiQo8Kwd154HEto8v+6\np0vfkpSnQd72Ht0SKg0NvwXiWkfVogDiD61zfcPMEqSxvRY6TEpgMEfgZpZX28VSYbvxNnyV/zpk\n2KACfSKjWOzPtDfAIgkEP16UZ/YtcBdHRIoMRXv+FT5LCb4UEnsUM4Lr7gzNfQq7JVx2rdpftFZ7\n/Wk0zPLMZUfySZT4L2zn9uH4bkaRvPXH91Xms4odjNj3zE6eeC5QDJA+PMf5Kx671w76U6LiMI3h\nJF+IkpunlgoIzunUHvSNprYq11ImhMLvI6KpizU2DVAZZCYd/gRmihY6O1/ReFaIp9XDe0l4/6qv\nkcSZhK8wEcvjTIRzf2bKPdYcbKIAnRZO5hY+slVOKHeJeDf2xmBykD2HC9GHi+uEQWoeBYDXeyU5\nltUd7jNA7JWe3yMoo6s99/h01tmZrOjldERzBLk0daMqdrILmKtC25ZHzoTBbES0LDmyjhIHHs1O\nv0VNwHcqg9Nbz8Q7zBjtdQrKYAqcOZzWXDUpdQ/M0kCKkXyobGsX2tipknyOW5UA3OvNd2w38mP6\npW8UOn/GrmEQiG+3b4/cF60D7A7WVwnEHlZLPfqGoC/F+76QYTiIGHJrgLHaCLBYCTpHJCGUPM+s\nylzXk2/X9XsqLevN78tTWV0Ch5mvkc/Dw6JBg8HyO3jdjOJCjKHUPb0cnV7Frb+gEy46Ll3MBhUM\nLllmjjbdxO6OWLU6ZRtNoNa7lC9QMu3F6HBmOI1gIourgzQL6F6BZEbIKpr+W8H2AToLga4lgHu+\nCdCADLgvBY0vj/eP1+5IuHmII4aDgwHdxYqszxp3PDm764jnvncNOTuDOuyTI2ntcUhommqZShk4\nHWblsbIXrhmw1FrSeEdZeeqG4UDgTR7RN2jsQWcorx8MCvPk55/kNUHeMPG8JDRSM16mXXUjJqlt\nTl610i/1O39yalyCUYqdMHCXAtayI/hlPAhTsqd9lGDNLEdRwst4yadD5onmWa//P6Nqn9U0PPKo\nRw98ifRsNmFYHpRfWyj4EBkQpohDebDWh9hfdcb3c/FZYRB7F0aAk6ZBniBBy3uO3vQimLD4TfOR\nB66d8kSlfYZXVlBUGxP8BDEBmrqYnFji4N1yrngxLjoagDQ3ngFCGn6H0LehrB9+TBeSCDy5Ssfi\npOmXbW2YsbjKuFzWF8ibhCnAfAV7qXU5mbj3nh+rKVgaN9Uyw7ODt50QnARklSDokEafSQohu6lU\nzBhB8RGug9oEJejB0oKgvCOXr47barDXYXGe6GDXSK36TboVKKHKJtydy8VCeBK7eQqppyS8cVz1\nsPMsGA34SPeyV1xKZmm5Ll7LtKhiX5o+3VVC3bJeZHipjYQES4VyON+IonByjagsYctspDkJOH6V\nEzhhm7TYA8FUnM0yKhRM1G5ukDaVrIqSQKyLCV91sJU5S2tAl76z3NseN6GZpQBegk05WRjWrOIp\nCDUnOC+Ri/oshr//Np+2X47qIgadQDS32TzZQumvoHq0DsizNkabDi+Wfxgw75pbA44duvhfJW1C\nu/SRC2dmDLur7M0b4BsAlL6p5fZvov8XdtN0rzg5yQJJ0QSY98l+Kyng49LDk2WY75kF1GCx9/+l\nIkzEj3C6hVYLQD7z10OZa+jOOKXqDZcgL5+elglhb+ob/SxC2rtBuT+bqGNMDQMns+HNXPBUxFRN\negiaDeHKQ/4FIBBTR+4Myo/ERK8lXMvG1aiNG7BDN7mt7hMvyDpmUp8yDbz+5S3wtuayBYkNQQxa\nK3zYgPNBXBgYSg2TpWMF0h1G3DbAVhTd5r+xVtC46hBfadfnfXDKJp0G4JEJv2NiqqXdsL8F6f+r\nFN9h1eHaiHlGgNDcfl5PlWsGetlzFLv4iLWJGE3otykwhpz+gN6EcpeXVM4KH7+avBpIo5C6sR3v\nKYv44I7CHz+Slvx8sgucgN0qy10OyaMxRLBAwVFpK/vVyENOw04hDEa6CpYL20qStGnRPGkZ/fR+\nBxOzYBHUUgQ3J/2Ur5IimJSnx2vw2ru6sa/sB/EIZMY6HVYIM7MGuRVtAVsT50m9uYMCbXZ6oGip\nzKDL/qKuVmYExtc0OzFNJIBX37/gHG7ZUNNCR7lRxTQeNBxrh6pzsVI7LefaCZ718IGkRYKJdUdH\nXXep346EGarkxdZMs8JhYKkrHsqyCE+iSFL6ZdHcniez8OpvhzxbIxeuHP5DAO+vEXOKxt9SHQLC\nb0OEfYxfwE7BPe6r+njnPiCnQJD0LTPhdqF8kad36kQ3hf3lxU5Ll+oPZi1kblPmK0Pz0gPkCYnV\nCjW8BLAWHSx3jbCrl6IGTog+nvQ7+7BwMAGeFueIsryWvCRDwSmk0GbHsDANSDI0jWzN6/nhL0sj\nPKQ5c+mL11Fqn+FRNm+xnJc5RwSOHCrDN96bJHNSUQbfDUhjIMuxJ+48gZ8kMuoYUttftfukj20n\nLeU+n0npxGWihA0jeSt3Axm0K/AEBBrDD7CtgoiWEvO887fxPkA/AD5PTwHqJFA0Pjdy+lzU/73j\nWVE/0RhV6uQfrrx0uOzntla8vmEcRwi/vT2a2DVCJ/rWeovlnMNDSCkvWWnA8ibyHFA7k/4xKrWq\nWh4aAUFw799sq+/r+AkMgML8+t9SXNIfiIWECIOkCJ1PDp6iHa9MskDVHRVHcpaC/McjtqnkfL28\n+4RyqJD6iYHugQU/kbuuH28hbiTBMm8OvyhAMdVZJQFuCSlL3WrPg366Y1cDY0ybOCjYt6HRpK8A\nMSYpAX1ZJq4BOMkKMjGOoD2bGGoneng+pOJZ6NTJPtM/7crd5pMJpnwNT50l1XAYB1/kNMf5p5qL\n729cVaRBxa6qZOIspg4DLTCqqmaCxyks/eAxw5VhnyCkGjawH5l2kPHTzIu3oqAcm4e2ij75puUI\n1tJ1Mlx9LmSVa/d2jvNVI+i+t3pxQvQzduUHTQGndoLZOhf9elIq1oCIGjggfh1TSWMNyYba5Gg+\ndDT2EFyRw6XJYqG/oasXhkZUtT3cbC83P1zqSgbvxRKUTjDZc4Wf7PY9jgq2TbAs+5GUBavrKN2x\n011GKjkCvB5O6AejH9F20463ahGsS18nQBUewp+u+6RK/rCqZwnjZwah4pHmAYl5e33MFGOW9YlK\nzNAwFUcvex+0waxKzEQ0m1Ez0TNYo3wWsmOgxvCVXBfkgbODcyZU+6IH8G31jCrbTFkwaEF7IZOX\nitE8d5m1OwwDxquC07ONM4qmnQM/4lOSl84dI0Fq7n9qfFbdcawzUCNl0aIZp8CGo/C0m8M7NDUu\n1yr0Im4NkTNuQdepfgRN2CImrQvj8Kft7JQJSGOI2p9VvFWbuY4Rlz6Q/VWxLHFHQeLzuvrCykWq\n/THGsbROYYYOQ/kyoLvs2WtFc9RHhk8mznlPIyUaWKiXWHYRKEJS8gCTsNJXdR+t3L9zbywx8ynj\nsn2VTm9lPQVqxID3aN5Q86wor1/wltou3BlE+5zi9sk9iuL15XwKvKwehuFyMuwlB/woqr+3D8SZ\nRyiFZg++Kz5L4iDON809Z5qxN28U3uYGgusCnkH4rDVigXnkr2xNyLnXJSYUrXtqPy1+1BXiX9JP\nMK1985tSVWDj7EVdeF1CIQjXgcaHk2BoHKgvaccl1hT6eTYSo8qgRN6ylGFulvPIokx8MdVv7Om8\n733REa+dzIM/KOeUsoiOA3FjhD4f2LXE6oApsDLREMKf/T5aLaCeDTyIUNpQqRKcSno0kTx22dO7\nAYS5awM3afbG8zH26GifFLH0TB0HtrvCKYc876Svr/jNDdfe2Ysp4BSw82v3OK094RNGEKx+y7zf\nX0BtOlK+t0bY/MdKi2HsXvZl7HYlCeVTRHkoU6CeyZKwX4IJzidtVILx0HTflevlwzNYaQhD5u2Q\ncim0/PluHEhRH6nBFo5Be9HpX+KkcWAqXcD5wqUbDYMAqvOSRekDMVKGhstnbqxesIpTOlL+eAhb\nldN2h7qjvtD++BN0q5hoMFbx8cdcPqnPY93HZyBLboxxjgL82+66cOsg6aA7F/xTkBI8UAqU+DrC\nb8CqEfOqedTrYUe2HVaMgYxNk6xDKWvWFQq06pXiimyoH8noDg90vPLDNrvOVw0H7BqZd7bWMRy9\nsDxzsT62bn5894Elq5nUWIYu6plNgSRl0geEHPOu41+d1ND95S4TU/qmKqJbjSXUHwH7bLYpPWu+\nHx+om3k+iN3/IzF9+vfXDSwQeAmSuOPDyM3Vy7pNijpq5oBxHC7hUkmczXnosKawGE5Mycx9XbiZ\n+WQDwusm4yQrzxD3q8Ln1wbFC2pBG64a0Np/hsB1JeXOD35DpRDkTyG1G+wsDCmpOlJWi52fLABo\nEphxJ1mljboBXMmmvk+mtPhWwqkB6s+WXtCuW6jHlLSGLvv3O8OI+qkaYqdkvyZKFBqxaJc7RlP6\nZsxv/+ypvDG2IOCwSQMxX3l2gHvZmI783zc/KrsXnr5uj2M/s7wdECOTPDGz9qrXPD8beWjlwPtn\nEphJ/arqWDwwtaAXC8yUbR1sxDpLVEVz+rkHLbZ6sqTHkSfS1QSiobuyDWAXydBWMxDdmdkzvZ5R\netrV8HxsmksGj/0Xq8hfgocvBKxto1fNDa3YTJiF/uPD/nJGGFJTHJyQEyX1UGOc34s7fyNmyfMv\noY5vCi9SpkZk//7+XFSwYk0qsY2IUzu2vt3JIvD5s3Gb8Pl6PCpalK1H4b3ogU6qdhA0nQmf4N9J\nFdm1Sz+7APLH3uAmiB0RJanKuuDhjSE+l9qNTvz0Y1704zm+Mt7Ye0gdSfMMNVUq2ohdKOWNKJVO\nrzy0GFaKIkqAxECCAZhF32wWo+3Jmth7n1t6nslEw1k+QuWHVGkMZjwA7WpmNWVWkUMMa80ewq0A\nPF0CWag4wfmGYn673JLe2L+QsLW2+DPiRCBA9wSnHyejt1cA2edtfNSFIXhuJZOZ1KZdpdHrjPso\ngrUiTkbiwoK1U22YV0X4qyH2ToaZ03H7rIPfQCP9Wqm2DzHa5WEFsDHKnBSK5d7nRSH1WxtihiK4\nRqPx9QjptANcT0TkuBABTbaq5xUFP83tvQ9PXRbWxLM9GUm3yz1jNDc9x/q2im4W3nuLhewppm0u\nBpDZtoz6fmbTHizKD3ruLz3dJDnSFgdTurh2s9emz4+tHjYKvT4Pbz19kVMlTaUu5JYmDvfta0Hr\n/m/eHRZOfN3lDn9aTjBhJVpIpmQzWxErDvQuh+xW8Zj8+s7gl+jGBD128cjPDL/t3TsDR87Ggiyf\nklqpVT6cQXtP5GQgEbjrISybkJ63Hiws+CZqPDMxVSvTQcp2GqgezqUNxQ8be02PAuBGDXA+V27E\nC5lr181lPsfKSaZOQlrRo9Lzks83Sh5c9jqQRGCX+k1qWEp/u5VE1KI9Qcth5BZK4aGkl38eNavD\ndtp0NbmDZ41pclvdSdLXI9LvdJ0j7zdAabdC8JVtZp+11x5PXvmO0yDL6T5J+VobDwTJSUGIFACf\nepGf8aygcPaE2UHdXXcMYBNvMkVpUU2Sc9GbZaBbXglyZN0bY7IBLrfBi/1bPywgqdoCicn9ywPr\nxL1GZS2/ew0USNKc/hv66rXRTZhRc1DDQxjJPYRHaW1H8H4CITAmtzTP1bgsMfbuktLpL+eiG7TY\n7C2oWGcX6gdB3E6+TG1HWwMhgXJmBphm39zynVpu/sRMquz+ZZb2J204wXmWSLNvXg5J+NjxlNe0\n3xEFapj4qn3526aoWGM4lpZpIk2fDgjM85acw2CQVLqdtlBVY/CpQjfeJHFmYpnWcA0wGhxhJeZ+\nK/X3TCwxGHbzHKbw/6WesIxX1SZFf9BxHqSUg9Lm7jCB4JYWU0k5THQD5WLcQURTSN2SikgPaGGU\nWXTJoIbN7XhvJtJJO+46PAtWbC3XtdvZG/Lp7XP+0jeHhXY3ySZrF0qxElJs0Cy4C87cXSQgfdaU\nEjxQCTkzdC1vzCfqBkIqadib/8fr77ioa+ff+0B6u5Z+863C64L79fm8adg4elH0ozo/utKZpk/1\nr4RQYmm1EuyWiKQw0IvlQ6mBYNmx7W02Hxy+mJuZFJAKTe+jM4hGtoCnzxp7YISBFMSvA+1nIwMZ\nNjIdaFFfvtMzFtpvdkpFprg7W2zHM50xf8BKl6dzX5N7pL+epM8AW9EYjmqvbueFv6GSYgRNZHdo\nqvWCY92b+uxjVhovHAooniX29Yur9ti4aK/0tuE0e3AIlxD3hkjf/SoFiZB5booMQOPE29drTd64\njimwiyju7B8f8UNr4IVE5DnWtluS3nmJTGBif288+jkBJ2oxLh4NEhsNmXRLoaya3ngmzRdtTC8R\nbI5rPxmAGv6PAH1Ssrck/SkRSOnU6eilNo2sgooTP6jUmLgGtOmmoFKHrnya27ttAzEc1EP58vFH\nhovBcV4hbBNAvslxxYISnS1SbjfX1H6vusEwBBu4/7AzG1DKwwTVxGT8z7aBVcaf6Q0JdJXZIDCP\nMdmSfJ6IpKi4Ly/ZJtJrPZOR2dnSMq9XK0oCgRBpJ4LvbEWRGP1x5hfvh8l9JK2z53eWizuMC/px\nVkYg3hYeyqGmac87lcCPygrfoPRiAWi435GXMlPvcGiK/sX/lc3scXBQLXYn4CAdEUN6BCDHgKuv\nJHQuiBZyjqiItp1npwXpV/OPmab0hvZbd7HuDtbnPxdwrxwmVDc9vgZkY4PC4jmhGQjIoj6t9ILU\nmyjCbygVz0BJFWLoHH1DT+QoMaKlnQeog3LKnMYbryQcGEolE3qRma+9z/JTLIBhGCGZ7v35kulm\nX17ETEnu/mnduY6EfUa7rVoZgRboiQiFne6HYb9g+du+dTIBPE1e6DVYVQL+/mx9tq6r1exNWyMR\nlCfyZvN768RQDqv5ckeEcx/xfmg5bdR/6ZQ/JYGVmGM+EQ4MIr8GGffrloQMTza4mNMjlB0/OjOL\nsgTzbmz5cirz6A2LJann5uEgxlT9J9V9xDbTCMWdRbJPHsNasAnfuROl1MkZizqP76ndZddH2icX\nbvjsuhhSyez5pN+kgKwvYMJVVuZyxbQVztJInPsYwXow3AUpIVqBgx1Hzwx3NFIfaTLdVgupGNLP\ntOAGU+kcno4KCeEHdY/0dW+8hbY2lAf0v283xl2qiQ42XxL1CFYYDZW3TLdZlpBreRmO8y5AW7vL\nKbTeWQsEg5c6ThaCoXFGcBSkiMPDChG22MwehY3HTVsPuQKiRPs+18PS9OeWZYVjufyogU98nRvo\nBatmQ65H0G6RaAaaQWRxsqgD+t0zQwIeKs2xz+X+EoBSKQuyzT1uyW8dBBWvmBnFVJE2RlI7JOnk\nifWDT2VWtTM9dTqhFt92GIe3epYwkxdDA1TerZowSr9G74ofI/CUcyTMKoHPhiu4OaZX5V6gGcCw\nURCiIu5ED5MK4UdG9ZFpEIsLUbwxxKhWBOeOsIEOgb+jc+IVSOEn70ssskp2N1De/M+hx3yPY5Gr\n9YrhQvrs2B2EJ7/+JpKspukS4ny3PzoJ3gkqQXfKlncAA43sJgSyDojBUBmtEMpVD2EdlhrR+eaU\nuYFy6SIS63QLauA7JmpoOdiXx/MBnAWE/fFCmPK2h1OclwcHtyR8XBnwhRJe+rtnl8LTq6k4ni3M\nBXhJfRDpsx32RcnjPgGnZkhKn/JSqF671/jFV1f6xfgfLMGuYITf4W5umhPKe6N3S42qRqMd8Hmr\nP40jlrCX/0I1fwxmsdG/TPPjhmWr6Vr5lNWsvWjV9RRoTdcYx5OLMvRmyp6feWFT4vWLOowDsyAd\nZrYp8ul0rBOgsUAAemj2wsZ07CthWE0BHGWJdxY2Kx/B8NA5kqPvLfSfQK9/XPKQylYoJW4kn2Mx\nVxryq4kai+MpwKFNdAKY7SxIN5DmWtvic276uBTau+L/GcrV4JTrFTiE3u6wr1biKabr9AkCUpUI\n709H5blJVO77kzMfMGgv1kqs0XiuNXvXx2h0N2OtCgWjnEmS0cHlFfctWNuazEoJUQlH1QgSTqKB\nslWBB4eExIFxgP6BPN8fYR3HjuIgxpcCMtNtm0YiFxvTaY36KYPqoPJB0DBAEkJpW6zG8/oWqgKW\noCz131gg3WwDBaCa2xRWFj9SbKxSlXcQY4wHfDmDngNqOw6TfWiFYjhxYh3Me7NX8UphroUWIVQ2\n2zz24fDmzJ7rzLAHtIcm/AdLAw49w1uZrOng2g9xoquCdiexWaWukg1pA3trz87yIrXqypph5UZh\n0LHAgW4UCk/moBMPkxU5+bOnWr4nFEDJpVZram+4XBPT51VDfmjWzxf0MveXYBV6ElITrCdjONBd\n1HG6sY/amiqg35viZhAttaPFmeEqQ0IINkEGVkJjZuTQP5p2xfKbDOxT37AFi0Nz1MyXeYFk1ASe\nwD8PKw1Te1ZBLx2Nt6mBMwCx24ggDkZQJ3ck73H7EAjAkMyfL660UXu3xz69EkwkJt1CIzhJ/YSU\nx4a9PpZ+kax6ozsP1V4QtZQ5GjdZYKbxwRdZgI0sw0Q+UHL8aPOPaK1wvRMSsajMngdb/BfHy+qQ\n2wvKqSX5rvNwpXxhYArhhE+NSvVosR9D4ajFPaVtKQo2KfwzDyGjf7rVTzo5YZliwq9hksquF6FE\nivdPvYvz/muszMdAMWbWnEiOV68zOHJ7NynLj7kiwNGg8figOPjTwObS4WODic5k5gPcnb03eoln\nB667zwftrcfj2FlNNpCA/GujVxEGsOKm8PR3eFHuLPS4ZiutzsERwuDsCsk3eUrgiHs/GOByZLq5\nBZEePwHx1X+NRokn9AbvOV94zyyRM9VfOxBrr2lR0lxUus8viq6uXGSB6Kv0fZzkTSe0En/VSN+j\nBgNXmIqSCnDAemsonkw3jM5u/oHXQ749PZsOW+gukRDEKYuyQRvP3iLRHqoLq4OAYokCTY8p/9y4\nAkJLu1yyPRilQHX0bEuS52NMYywU73zGPVQyHUxOPc470EdckcMSak57oQQbD+Qz9lZyivNSFZTG\nYI4RID+Wf582qSml4khQjqd2G5gWirausrA2yVZ0rX+CEGXFSf25kid9WeiFEAXwTLbr9vGvhcC+\nrILHCq/PsaJ92GoM+c79ysYXOiwKvwhLqTVTx52DraPlGGjk2IskO5OrhdzDsRil7SyGjyb713Gz\nHUp+YRmxsrv1OU7SAXPGrYcsiWVYl5sE/PKPkvfvK2Gd3Gys8xIROR2fgUtXw3T7JFVEAFBZkkBV\nGXz10iHL7l42jY4v5jlRYEo/uMq1nxcfJj0UEL3rmamutDiKiwQu0/dAEn1Ug8wJD5a4RxCm4tiM\nn5xdy5bvlG8FvVCSm77Bm5/J88DrYlC18lxYVQ2LwlLGWvutdkqlQf+kdsgZ7Ir2nKNqG2wCcj9a\nHVo3f2cRyRP4Io/l1a3dVgZ9Dql7rJR1RZ3Jkyh4/4l1oyGEB4dDmg2i+23yLjZnIRqAQAlmt0/s\nGCHPTe4OkE02tllSeCnoFDWevUsBKV9uYTnwJO5qqkyLOn/+x1ll5kgDY7zBYcc5+H1GaF4knsz8\nem9soeVqmBwpw/Iek+c7UyVtbjTNhnvleCfgENpzOXQRFtM1aELTLtsbQVddVAoWWvIf1bTH9Yoo\nPohi4gmVEYLMHBHO0hKO3PMH8OCmnqfVDS8xs86HcTI+/MGYzVsK6pj9UGrTrrMCT8VYnX4vgXdl\nw1OrRhBfr63+8WXNTW+W0ufqQg/DsWuZTxf/BWDD/KhKGcpurCagBWKc5TSwhqjmTpsi28H5erWS\n2gDxmDqoU8fnDrtlLPwtV7AVhJ/voYjqPqfywx0V43wzZEBprtlLnDK5EdCpPNNK+U6FsfJiMYXy\n69GriMK6vTmu6C+IRhcpZVJSqReQAWMoC0w54aB3PhNXH7/bafFR2VdRlyZwT7d4fYiZQ8O6CxbK\nhGgpolq4BCR/XtvzaHo+5WUHmgxRmpGSKk7/MYBo1L8vpatNlrTIt8iXnci4PyqMKuGtzg9DdUaP\ndFHx0kZPg4uBJSpWTEED4LtO9Y8797UZ7WGg9VUIs4Cjsz1/2MykdIa/uUaINkYTQ8+s0BsoIW74\nz+cyFdifbvzzCLryDr0ASqGW5Rz5cAZmky6C17Tjy3S6YLch6/BazzVnfZinIAV+DklV2zHq4iqs\nFKcMWgo/xgAEK/nBTXJlDBJBA1u4vRATjAKnnj6ChMau+kfmUldG7DXLpF+NiSTerXPWz4SVp3dJ\ncTgdF9mjQkTf8knKtYKf3h4P+dNrTuEbivMF2/iRoshq4MY9iHh1K1tLWuoW5QDYB9MEF+7FQFOw\nRez36e30goHvRQxfGzMMTiNy4nprV8YBXjlD7fBls1gJhJHCEFZYCwPbNbz+OsaQvmBRb6hBcx+H\nVDur+UBFHxuiWOz/E6Hi5YJfxmvk5kI2xa64xmKQh/FcBzoXPuQllVHQewNjIQ8MPD/OjD1GTCoI\n5EQ8BkdpDJ1OVTx3r63xVqsZJgaXz9Cv3mRug+Bls/6FtgmLNJ4N1BY4P6h+sFWSr88eLLs8awK6\nWsXbazUvFxjTbDvhvsl4Cxd4uLXC2N7dEhH4woP1dKOu1uHIxTNbBa4SLZySQ2acPgb1bampEDmn\nbAgfljF/h6nwVPHx9xZOYz2b+ESWs9jJvPaIwieYzHjHqA44D/e0dlFI1YaMTNRYSDhv9SKf7Xx2\nSoJKbhTr5eomTl/O29XT8cvvHv5GmlDw2fvB+5gIO1gA21nKRXYbP9NCe3JGaOx1bHSKJQhJ2TPn\n//Y5W1kDjRLNoXrH16K5ff514uzepojuB9zcY/qy3qq+u6DHy/NrXG8U1xdxQxUc5B6YbYfLjq2x\nspr+qLR/lfHg226FL7xrsoqfeUq/BpdL5LAJMU0Jwek+WsPTM1JIUxmmI1cp65XarnIBT8lDXAc4\nBsSPAzUM1WA8unXEfWRSIX0gmKfrZ96xaeokzG0LSZX0z0EAfPJ8wfqjOhv/jTrWTTvbsBaYEmGx\nulBh+lFkBpmPt8yp63lZjXWGETTkZtfHdpkWuwHiYec0L+9UW+Hr/Kh0dnrdB9nEf+f9YZMCTBnj\nq9lVVhyITjEYhpFNFjJ1cvD6GJ+vsyDQNP769DFzldlH6iN2Q2t8Q/WXdpclaqN4znE0O31aPtJa\nsw/rPfJaXrmnHBEbr8vhvNXdMcE/UKIkLeAz2EB+je/knxds+yTGxeDOH2mUfQG4g+v91U6qt9Tg\nI8x1tzT62x67N9aOXVzeFiMgu7r3AthP7XYtNfxJg+cirDQ1JMpZiGa5Dl5KkWREbTHiDuI/hSHK\nClZ2HD99AXapKRpo7gJ6wwuwGSqtJ6gqpiHpk3BkJjFt5CuTcvE2/IxI9xu/0TnJ+9lEa5DrPIY4\nGqcsT+1+BS889U5mZWLc9svTYFBOHNaxoldse/oMk7Zp68eULShs0NiD+aNPCLnXRvEhpeCSRER6\nIX6FaF/IZKkwNkQqNYO8tn3JTHmSHf12xyTjut2w8+4z3MeD+ZezkBXPk05zVqadtUnzz1CAoLLN\nCv9IopmcDHndPiW/WJY7dPKVuPDGueyF3oBcr/FXZHNc5LmCl2ZkVqLu72De7juBt4x2Iur2cqKj\nRxK8gBzfye+5nQqFdsYRNHmbRCxPzQhY6vG/XDFKyIJeuY9RTMzXsOHwpb90lza+wFcHI0SAe/xd\nFeIjIkwwG+tNVmkpTlqj4NHB8sh+AloT8QyqQaQcmoWXhv50MAmKWJDk/Sb70oIjgmfjqp8XrqfK\nYETre6DC9O602u5XkyEdi7sJBuP1FQg5Fv9y2HLlWS58wgRpMvK96zBUqvGawJSL1T6Y8QO+bB3c\ncvYf6O/16j4l3dLqWEHu0nF0rdwwf+3sHsK5B2zhRkHqwbW/sqqIgAcedcCyKq5pwgqssLq4PsL5\nhdBKbWuqaC2dLc5ASDlaQnwnFdwta/zuRn6CFsdSyhXpKdzoeiWGK6/R7+AYTgkW3RiNRS9cRLo5\nCEVmIvYfJK+RuD4IKuvpz+Swi1OBJdiiGUSIIaTYeus5xEb5/axeM5/ix6qtiiJdFCd9fYMIoUuo\n3YDWULJS5FPeu5rUK5gMkYvYgkaA8J40t78mV7nLtFuiDbFxRnOYf/MezhIZGixqXS2efovUMWXD\noPyMJOKDCwW+u88GatWqn5Pq1YS/aNl2lJmewLbxbVo8xomxVFMySN6FL2Q+MsaUAjccDMao9hky\nd/ZNUc/dUf5F2fjnklzMUQ3M0cqINbVxSRkuKsPcxf2vZ483IgiHF4wVTW69MVvSNqfzX03/97pe\nscygGpGULm1yGbTL/w/tToCQ9zkcfA5DJtGl2fsNdyZ0H45BR9nl6zsaE7IB+Ngw/r7aaTJa2PbI\n6ASc+kFStodyfyHbxathzcCr3Ws6xW0TuXwKT+t975+tK6+ULxY2n/vud/0QcBSS4NcA1NyPHM+k\nnRAAEImw44XX+sGAvtYkdImcLKIi9aIL1v9E2jkz5Q8nZzfR8Juv14rbG3Nrgnu8YGxsdaDTkREo\nDiJ/lYiiCTIZFJCYh9Jm+q1CPfQQV/XAvopXmmFTu2tHXyyoFozVjRob6sXWYfxdz46dRFWbJffs\ng7/7hdiYQc941gKo6jvbDPEUgNqQcHOglLkfhSX+Qe7NBmAxqlluKemuPfeYrEXCM9Q45Blp2tc6\nFynECBb3Z85+rF3QewiiVLTuT8+3kwoZY8LI/qqis7FqrHnVI0MMtB2B/e3G1vGcHt4n1RG8dXpJ\nWQv4/Kl9QVOah0O5bvPmAoEQtUM8swbrgzON53k01xH9bZrAleZuYgLivcQ6lqn5bEemvgcgie+b\npa5wi4C4FJjmacNyHaR/NaS1ga8UCWX9iEm+rLMIZhoIBrbUIrZeIg8pT3VOkQBtjPlOkaG+PxXM\nOYPNCmkMOSl8jUG9XrzTGDXi1LgBpAybnfzi9cabLlIDr2rKyybsgt3nfhdNbGUPWRKU5Zk/yLRh\n2is8cxUBCm3+rEw8J1zQr9gQHuNfPxKtS3lHvQtpMIBLwLlAuFI7onS/cOI1rBoNAcJdNP9UoU7N\n3k1MKCgj/r+7k2tTzS3qT/ybiRLf2Bv429eqz9sczsWLY3JctSyAvG8hZDBXq2+RhrmiasxW2edj\nly3dCmDUbpjoyQZ+XvZRLo3RU0llSVl7Dw49yKFMIGcCP2fNRW3kBoCGRHbx9q3D/BZoHzPUACUN\nNcNfZUub8M955BPAmh3m6L7TT0VF7jR4YnxLXRSbRsrIXPDMg27k1rdluyRezxITCgQp7cJxO30f\nwDOxNTmgOcHRtorGLgZuN9yypc1GhjsNTwzk0/iotACslO/I97QhYAK2c6pOxcL9jvYDwMbivkhN\nQk9XNuGwviAMqr+9sJmpvO5gykXHMwUpziWhxk9gmS/68DZUnaqQpPFd1CcKqni5bexJW6IGWyUd\nTi5TnJVVN0SGtvN7085Xg8nzPplEcrJUq2PzJHpthkPhPM6oMPo2T852tCLCCOxJVUaO2q54996K\nEwHoSLn26KwkruKUKa0u552ql04jI2EBBBmm7oG2N3PS4TgqJj4PfMcrLOQUUgryMxHGttzTtPm8\ng6AnGruGmUTTSUJ0s8bCsTGCzMc3RJbQxI5iB1d5kecK0y4IQqlRfEyUAYXkinpvbjvMgNRSs9Yu\nDEW74R+f+I6BrcGXMuw4c0ep059Io431vLJnrwDns+20EThDVtms+/tlynm/c3Ln2FyEmty9Q58R\n77/SJfay0qKqqZ3MfOs5jgcCL9Y9T8Qqu+ePN+W+daOO8AzPupCAOElktLiH7gj5Ctfz9nCRbAfI\n1Dvy+bsWYqxhfbrGCy1ri2c892y0YX6B/Kmx8rlH4YMD0Bepixu7grBC78grnSaGkhWtrS6iFbiU\nlx05QnzO1ts5flabJxjfblmIGB4CGI5vP1+QLPzmIVAYpBFfs1l3RCfzgohsw5pgnaN9TgBDyauU\n0GEy++KY6bcKQ7ikaviJY6atPNLEfMjqToPoAMGMHTC0uOT5a/bzGBtKYRcy1cLGXPu8lR5+7cFx\nKCqRWbNMOInpLOW486ZBbbjAF5Gt1Zo8rQiA6FSXCl/jvb3Nw3ysD3uotGJdiZ4IZCCWScXkH5HR\nTJlRHtuUDerkgDvCWN3Y/dG/O/fraZukj2Uge/R0+KOwwIJyk/r8CATe8uRAWY4vgiYK+fT+mBYk\nlvEiy5R/O3iIu9F1P/UTcHmq5xoNvQDyRwnYEBAYFUcAUbH1PsGl1jPbZ8ktTvn74w10c5cqWgdE\nh4kDCGkpWd31V+BnLCXlkMyE83LCxwuAhm7kaTae9BlaK54kztsOfs9RuBTSpqDYsO0HayW/+zJ9\n+ccyXTJkWQGo01HZ2fNqawzRQtapSENuOsotlEo/BmlW1FicV5A2f5YBurNpeU/c8cGZgTKXZzCS\nL2KW4idctYgBlzfsjnE8x8mEom7umgzD1/vaejX/ZGVLFJbZ0i8YlBsL/2TMxwTOaeFUHFlzk+St\nIwjnMv7uk+trAn3qvscSHbvp5Iqx1QcwSzoQ0NCygEgbfilJY+ch3mfjZXDmBvId119lMvFRCVzv\nLk4GTlw3K2G8NYz3GgFJimKboHYN28/KZDSmBCxXWEIc9tUbK3ltiYsLJQ0nI23TzTmTPZVpfSLZ\nREYkmqhF/742WLyw5nGo1sK1OlqLhawkhkpnnSNe+LE1y1rxL1SOBrAItqGhoRqv8G5xV2N/BrpX\n8bdZU8Fo5pSwXEaq5+mUJ7f+Dl/UWkn/wfAXULyoyIBVB52ukrDtqX37i/dzQoAb4T/p1/AU9xe2\n4Qrzy6iKPSyQmVUwtLLA4ebdFIdnjwXr2DAgsjuO9SF8C3NUtt+JR5CgabxRKJtkzdIVZXdNoXKF\n+FiH/BEZ2rP75YE+v21hGmPLunnlfwAKCbqfbi+RIQI8RwYBBTlMWBAOg1O6GJdAuHSHCYMzLqV7\ntIzyM4Jj8drLvr+Kq8cBOLj5frMEx/fRnSEx4xFQyYh/NiW/08fpMSFSIwVogDgOecjoWdY/6TM3\nHsVdEuDi3hFdr2SMa/bMZWKNwZHBtlEp/EKZtuVoHO2DqxodLWdATXIxdxGYkyoazz1heyP7khvO\nfii6FMbVGqQt6K/c68BRJFE6zEjXbnNyVxlUf29pXzhtoectiXNIIKaYsf1gnaB+qxXazT1n7k1U\nUKTa5Unqy91w5eySgB7MrhrRsxoqCGDX4UUxZKiUn6RMKt5xKjhNjm80UQW8heJS1c85uJaceqoQ\ntNQgQXFD8hEEO3+rG6Q1L9+3LVEOVnDVLP+xBDFKCU1Tq4WAcn0ZD+nExl7KVWFg3QRuzCtPO+n+\ncLlUXoe3Nejjpj2kpXazJXnnCs5LXC82W8c6ajarVqQqmrhylUQrkABxS358uGeMUaPHcSMTHsfd\nlU2BhskbAXUkTSDY5F/RYDIaQJpCdB6iKm3LS1wlb23TOE4U/ueeWTZKGh6SZUnD78SEABhRB6L+\nOFsOnMNWo+4szGVp4YY8BaL/uQ6pTpImw46HRSt1kKPp2xoz/5sayfauoPMZryTvFR/Z3Oca5dCK\nZfqo65B/ozycjVKutboivH/BbW2QSMKlWFG4ByRL3kOpvp1s47PU7mM0UD+SKPw1a8p8UR/AlZ+V\n+5ZqBjhFRm7a6TA3wsbttEZgstXaw4SkEBZNV8hxVmNRkP1YkN44mrnTBnoFi4HawZtGBVk5DKdH\nXMteLmXyXPkdt8AcpIFkfW0SVQSOMMahdu5rN308YLwa8CLT+nIyMHKso/VS/7RBSbHc+YBOxb90\nkOEAqPqyYcBh8SigOzYhu05vZ6hFXzcEM/Pnwhe+ge/w7bQm/6Ui8Z7Gzsa6Xf3rzc+pPDB/xl04\nZ+dc7OHMPwFAjmhndKZsC9a0pDUwiERWCDp9XPAuiBBj0NGmm2BS5a501tEp6/IVJyrnRMrf4Z3W\nLGeX1+TlgYjE2nYC3dADGiqzGOZAmkTBqxqDgizBz1NcXd1MTN7J53adqEZHylKwojwuR81j1shl\nFksrlkEynq48ehNfo7q/LrJLjSKmltR2zCsDG7HPSUD92m6+/LQXWyOGfAKuUEEch5V8B8yOAzFd\n4e2V0pLIuuZrM9mzbvk6iTEB74/scZ+Vzi6KSSQ11nyaeC/QcwS2NURMsmqESs0FydtvvFL6sCCE\ns6SUUD7P8TxLc1dGzb7hpTHcJ8VtEH4EU9Pc/BWAKro82b/0GxB9tJe7XD2G3Q6H9mNiuy4jKux/\nw5lTrP6qYGo/MghUzYfasvTGZizgvF3aLmL1eHZe2rQfeL0X4PjzNDelX8jgAuhVZUovIF9GB6bD\nF2qCi82jkXOh/0N6s3h0+0+h5TQx22d1j/3aP25kNCR74MAfBPR+jWhUofDspghZvyLDXB7h8eNI\njQEth1Ewfmb0Q+i9jP81tp/yOMG6nQucy2kxmqpYYqkv0+cOumCWYOG5FZFZGRD51oCG2hQVQG+3\nXXplIL/lpE2khuRx1y+/ZONAs96TG+COWtYTbvV6msMrWqFCwpxEBrh6CGHhYBSdFnE+0yBKWSt4\nQ/BdfIo86Etv+HYot0qJvo70S5POC2taNFyugXiABn7pWjXyZTNqamuYXNIWbSzzSaYBh9vC19P2\n+Ud8lRnV1/s8yY6yRhwKm2z/99vMaGzVLIuggGeFo3Vw4AeIoy1zwVt+apEU6Y7fw2uI+rZLGMPn\ng+BHGgahyv5xRen+hawu1zsqnFx5ZU8oyXZeicIRWSqPIFbZqPggLXxko73xSO292RuvpphmzG8I\nQwYiP6lpMHAXN7nxx+UdRfD5N1azw7YJFDIKeuiPkCmOH+8SsXPQvXqgswgx3RTHvS5Zzd8PYuYD\nhMkFSUoGR5Zwg2Tw7fmujhXKcs4nx5kXi4DDpBgwrxwdi5oxxjycrjn0oNMXWtSx7kR+/avCd7nz\nSrbUO7OPYCS+DnDqbfwBS4zRRplbTy8CfCnfsoAr7mr/qCSsue6NquI4ZS4ukjOIjhiMTmzmk+8M\nxsYseimeHKTVmV+wB5CJNVwso5zcmyogGYNn8RgJyubiqCMbU9cynyXcBp0x5sGcjTvU60+g4SfI\nWqQPYaBuyUchlF2WCYCbYAFObdnmY3QpFmuHiVwoe+4Ue3xnLtrv55qVThzgGGXxHdLa2OZeoh6K\nlzc/t+AiqnErkvDdzPE1z8exSR06jkmgtcjW/J03yserD2MtLDQRorj1BHZjXlkC/d7ZtbBJo5Qw\nJvAUOuTHgsTR3GbK9c2XGAhFbp3lsS3puwspZXQ5ta972NnMwD3VeBKAOoX5qWxq2uU9+rtCFTNJ\nmnnF2CDbtspFNnIXJQCLC4WrsMd9TmZsaErEMOtsNLF674HQ0AZFgQA6eEzxZHsTqtgQtYbwZocZ\nYY1/yL06L1u1ibpjYRUDIoxkVjOd/S4hNcxKi99xCCx2TONorOR1jfdhoJ3FpPZ/R1ZoppFJvUkr\n9ibibugmp09kr/bJAh1JQiiIeMHN4/Pif2UKUgGK4mBSJ/sazTrAQqdQdNXodV+f6yAGr+ZeT2bs\n98jL8jFOd+qpE3VTgyohXd4uIyZvsSQ9wgyYxKSHlT56bK9offP0dQRC17GbebVye6YIn4ovm8xB\nshjA+3ymghupEkqHJGuvPAEjq5tsfiBVLW+2e18dCKbjhmbMPPPiaBPcVv/xptCbPJiAbUE91UNq\nSWxI7shHahR9xblyjlq5WoKvxqmISf+oQJwkXE3nHZ8qY1Tc9OSQ075pe/dMUzxL7Y3yrAXe5FlG\n1XXZ1X0FRzguz+WBkWaPaykgPnzPoTbj8Dt7ygkSaKtUme3m3OriDZuNN5vru3hmCwUd1LpS0XJj\nQ4rgA40LBn9GMVCvpv+gnmpRSIaDcqv91MD9U4GOiqXjcT1M5DkpM9q4P4B8v9/2rm+jPwCWalI3\nU/141SMuwYpjTbkzfZM2rE91Nrb/JI83fg1a+02+kpD8LSxshi9Ph75WdiXBE6af50pZkqRplRin\n6StdWYy3eanPgSJ43JHJNdJqLqNoRYZrHJA1ok7/ZJew8DpwTNJ/UvBdW8A9F50SZC8Ef0W7cI4x\nGJO3yFvRBlgh9qCY0JfrAWx99ykIwoVpls3duGokTylpkZ2rWYaHKvImrRtChrcIdVorG787tynQ\nnabSIZLWXX8GwSBfHlFbHzljXw7BmyGBlPthgq0DOG6o90ADXxeIi6TSQ1xUY6Clg8bDC5zsOaay\nEC+4HcnN5LHKZZ7yZr0n/f0DvwUHaN9NLnPQN5nHhVAloxWbWXyTVDy8xXtgfy9i4dXiD5iexU4/\n8SPQH6Pyt3fg1gbq+OxJzLp6Qs4kHS04IgISUZV7otZl0Jm0HDXdMvqFjvruCrpzgbULF5qOUyV+\nbQs13O1O3T9CliMTKTKbI5Vnuy8k3PwSiILUH1hJ7y4ZzEwpRLyIfgiZjgk4geoczZbElEsSp6/C\nwkaVjE5Db0jKEd9S2KIva9tLfhtcoXkGCabfs2Jajxpzj3gR/I8zI6zQNwOTAxIZC9cplK6lzxoO\n5TolvfWcSyspScVsmk+CNn8tCYVhHqNwf/IEqN/d9N8vvu6m1FdMXlRlhCiJMaPBvRwHDf+uCNnc\nhO1Ta0DEocdiP7lnqLAYJjdDUtNU2G0LnXImwVICzBBp9hwT6SNSte3SnDvhNgiOekZZWD6WTJco\njTzspkN9seEIlIDEcMkrRwlqo92fSE7cgXbGkZVkUur9xD52FS8XwY2+CH6U36bAPDt0yirVzERM\nGbdtGI+8v5NjXOM5YfoegnZxVydCVFzpq7exnGsYo5tjKTVxsyT7p+DCsQG+Ub3GqIO0HM/KmGYX\n3dG932z5jNAVZ402DLhgCe4oSwWWVmbV01mfURfTynH2OhslHIX7uqpa3fGnT8xSFgiRDbNhFeUv\nRRFxsgrKJNjOA4h3GnlidmPlL7uy98xnMzXwzOc9O5il9RjARfe6gTEUG6c4on0S1lJ/1NMWl39S\n+gtdy8irYvDX1TuonJ28S/PCK2D4UiRNmzkUzCDBDEjg7nGjK6Qc+mCU2ODE6CG18exxg9OdYnPx\n3Kll9Vzgk4G5yZZMYMn6lJoqeojjd5WRejm6UaKVuZeB6znFcitsS0e/F3HAuagi0y5kw8jKD/S5\namV6IzjxFWGqDPgQgvxVhGZQeRTF1OPYTEl13+JmuS9EfscEoKiKoUAgsTGPJAMQZJCEt5Vnzh5G\nDv3lTeDZPujZEYlkJCZ0bic4Hfz+F410VrVef5TcHHIZeLUIpY321ERr2Y5r2C41R7KBsWfT0koK\naImDsvLZ3mnZvWMy7eW0jLqn3RMYWRJv8jh+SpKmfRhrug6QmUP+HVYcbhN0NAQickrDzMYvdMQb\nTKFgo0I2Bcqpc4mTGJayYMc7jeA3E2aDGNitQijBj/CyFtqNIjFe/5QQK9pOjRt8hi4yhCg1UFc1\npLZnpWBPpdAupYLMENAcNSB2p8UKBuLKs8Fhzmcrn8XCsmzE95ulijgA+GgqhwbDJ09xZkW5DRDS\nRodi67yoXztom4FTsFh0ZjtFvYqSXaCU0IDN2WxB2rFiR4olRwXsgKVK32ii5eC9vvTaN2lAaDm1\ntCDpKCucRNhYz+8SrlgduQhbx9vYTzjJ/7ykiUUyTM00bbTj/1QD02x25MPJUEsQKCRbLweQYQWh\njBFdirlh/bzyV/BKyznTVFW5hcRuCtCcDzPYPeWtI+tlZvD3RyXINTv5ofQ3UeOLukBj6JFAdeeC\ny24rVTTQ2mJ+Rt7YeHpBA2IPPSz+gSEXaOok88DrDe4uCxk14RhtLrpA/9g7r+CkkcKupgvarguz\n7rWVc0LPjVsuPfWUBpvJLz5x3SrR2ohW+8YBQV+5VoJFNSEPl1n0jkBEbEhr01Do6q7MrE/Ladwv\nQhi/zc7qc8Pqx5UimYEzb1F9VrqUTKP9C/ptCqNVTgUOZ/Z6Ip8G8VrI9MYKKspIgfH8WqBmMbyF\n+GAWkAzYfSAtuR2bmGL6J+TfVUa7Q8uWjpjARb2eQb7YmXXWqvbj3PRE/FcesS+ebTEpT/oABP3R\nB+54tSj0wYQ7ojfN0L2onspi8Dxq/dqbTJAmUDbd91XiTpGtiCoCSNVBAMQddXCLuSNqSETwD1li\n676vaT+QWG3jM16xu7eGNn8pwBdmiU/SaWQdGphXYZCcv5RPofouNfefkJnAszHWSC81q8PGoDmZ\nSGmAosfLxAIW3DljmAoDX9ZPQUbA0evKYcRo2si1uNFzuzVnKImk0oRVL9u1SidFgOwMOqod5Uvp\nxK481vMYRjiSFa0AN/yoty2REpoRdw5oQxK1+KRTIzfs7XxzuOzlhBbFaHKYXP8K71SoeBeE+cu+\norBGBIfY5prFFcvmaSNxnFzq/VUSqtUeHh6aLKkPPNrlcnFkPXAK/ILTJxoI7GyjQuhxJp/Zg01g\nmIlCyfrTWtfiKI5wGVHywIPeMPnSJeOEm3EmPS/8YPk+fmk3urh5MiHK68owi+qlljEiV8nJfKfY\nyMC5sU5efPUI/febqyh+nW4usxGwVUlRljQK8EO6BjQviU1+wp6/0dZO3CBgCJ/spdxGlSW8OTGW\nKTOSZmqXV+tO3aJqQuwE2NWqwKLoBMkRbWNcjAKre3ItkMEEgmczHg/Qio5O+G6426aJ3lI7Qao1\n4sqEcpWVL3fHFZiAtRu2Q0yAaVEjL8K6buOFP6RP/USS1Mo8BTrQ5jz/kNqqmbBKbX79eh5vosT3\nMEvxHRGI36klNx2hWl0tpyRRtvn6Q1Q3jMvL2pKpvFPaHdeMZftzRmCvinL9FrNEtQqmGJ7cjCOi\nyPOtOKiMFWSk/xqEuc0glWWNE8RZp78rveFB0a1TcxFwUpT+HgVFS/v2YIga6K7dAFLOMQGxd4fY\nhpXmajtHcl3651BBOy+s5IRmCOWZqOxevo57yNvaeSMn66JjxS5LZRP5Ua7euVHOB4auucZZD/t1\nxykgfmd07/BaQ9MJMKSy8E9Y/xdYhvdo5cm6/BEnBhiBqO0eeFQyF0+nbKTo9UZoPS8qV3W5O89x\nS4aTH2femxhQkYdT5DkfKcB+A+cX+Zi/lX17pc5ncAWqK50HmIbDeNRnnPStq6J3ohdshmRFmZbR\n+7ls+9YqvK45e+L4IiolLreLk4dcP8G3Oj5Q9m+2/9DSXcJ91G/WvE4HUzIOIgGzFYQmKlub4Aff\nYqoH7GeYvWS8kcnXveFllm4G+LLSt8OeWhBaaajQjFGy7DZHSnJKpFYQPl+ukXncJEBo9eJrpWNy\nYIB07Wvwlggl595uLG6dnMFelvc6BQf9ECjAiTJ+DTn2UbxrYHZ+lIMZ0tXq6I6KGoZdpAsXbYOj\nybK3He7yxcCDwZcbzHtSwTOt1gIXfv8ZGqxDYkg9f3ezOWPnWw1E+yDf0A0M2JJskWS1UlIHpEx6\n3ebEQn1YH3gnA1Uj2fUg8V8TFQ8Ql1YvI1hRdffxxFCRLjRrQw3AGfk4xjpVaLxsTa6vFn8c9h0W\nvWLVNVhSMIgS1b+brbH7fQsetM0PoFM5A/fWBSwmqT+zO4C21CGKu65qIsNQJugZJLbVSSCvhCOM\n3YRi7YDfRjdL0Qjs7TrU4vTVhEnzyT1cy8nRByeFD2DyQjJmjkInE51JsREOhd5ls0Nk2Wtpb2/p\n30oEfuc3eleLrCnkt6SmOhLCaKU7jtA3ZmuVFZE7sZ/kk4Kl/KVPBEgtNtlg600TIPSVssdfQw5q\nNzuId2AFwe6DoPQ2czeSFSftvX6n13vGkRqAPYVf7ErB1kJY7hpeJc7pf738M2ntXrVcFD/1t6fs\nDDbkMOzm6KY42AA8anfR08r0d4XgsyhuaVpYr1itNBksfkCfFEIAjSKqgcUA1anfmP8TCSohM3HQ\noogBCwxIhtUJUCiQk4Es1R3VDTW+dwlmNwkztre71J5Mq72LNQVAAMM+5ghnWnq9QnJb31e1ndPq\nee988GD1hCtcqIqAgXZm1s5l8y2PNiVTXTVs9zSvFoCvkEXqtzGJdxAammzWqzGvh06LC8fyZIhY\nBAxTcadMTt/UKwtt/nGoxLW2kY3jT4T4Szd8f2YOWrILPaE1J7zfLx6LCHKhQ8pqsmkdiGmPVvc5\nlnDJFOGTEEPpkgi+2RBJNJQaG0nhBhsCt3pFMhhxenLNfIXzcYF9ECd6D2+Lmdk6SsYEHcMGnmkI\nkmUtwuSpYS8DtIbKymKdmQZU0hXtGSLRbFJUKd8Ra+IELwNKl6a0A7JXLpZsfyfhet+qaJOFwnwc\nqEo8SoTa0w8/++77x9AciZY/PktFNZzsBxLhRA6Ff1TVQIQDOkBYcKV9CgFnZ9/mblnEfKTz0RXB\nw8AXOzuPdwcMmP3ES3TPrvSodxyPsQ05F1AIUqxunml5XXXYqVe0nSnUroXPlJFXv6Hg19SoqCm+\nC2wbLuwEzqLVDIfLHLeCsxII9RD/21YJ0IhA9M48ok3T8/FKkQH9EysHZdb0cyFb/J3WQvFmriTn\nuKIcOXEHaJYO1RaETZsY2i3ItwMqvOj/lH1f1OmlmhcCHHxVs80lcd5ZxCz2qJMzo1mJwy1UYf9Z\nt61Z5tInrHUWTmvZqEhYlq/iumvnh5W5GhHobz7xuGExQ9YBUyLnpC7mpG5iNL9ca3brmcbPvb/q\n1QObjqvdHK92lUxIAHFmAd2isM0Krf8tVIzRBG1EfhLRT7CgScca7RtzIUlWKpGNqfZDiE5UT91s\ndTYgLRVdM6I7Cg4TRB1yi1PLOEGG8udSZKyw4+jNZJ0ivgmG8EKmkmCY4r75xKeTz+F0evA4HIg0\nrVjwvJdDXH7ai9HRKSQL95rhbmPvX015VMNfFLao2xORR/u1zChKJjb14flOW0Mb7Z6txkI5/mi0\nBQuuHRsxUPzQCXpnh7LWYbTLSkzbYeEjLmzMv1EYm0fVlWfigI4z6EmKgjcSlZzXMWnY+OXAt6HE\n4oc61c5+4pi+77VMpO2iiSHnhTL+kVnoIBtjl2JZOhSn2UE4k30m7ddYJxWk9aUAFr699WEVl5JB\nI30PeK2jtJNPKVszbroZmnKwTuTOXsb8xgFDsOvmv79ot99ix7W34XZ5TlJyXwFKa/N0ZRlUFxB8\na4g8I3KJiUaWPF3spLMh37v/OAD34IjOgHHVwNiLYzd2K/oi461vQvbAg0Aet27azVAspinPsBsf\nEQD+58z1wMK9d4A/mveIiJz7oRpcz7F2GZp3E8aT0LWprRMZ9HNgOiq4jUpskDbYdTWEx6QNa9gn\nhnEg8DPvdzgLWGzImLDMIb3kik/ApCKtNQs9/SY2DouI7V7WjsFNxjasxNq3OIo5joFXSFOj9lnr\npzp6bbBv8XLEXFBG7K0ydxiQmNd3aVc1M4r/OUaaLKfLDNWpJaAqtBxyxcO0+5Y55eME3IEcO24x\nq5hw9430mkDVhALG2KLca+WEUMWP7b+81VD1N7a7sGky5y9JZB70fz1vwPiQs1V7aSZxa9As1zPJ\nGcFIvcSkpZmbLS5kTKvqbdWHvuGZi+GZmgLEmye76U3c2EAPsC3MdMfsvWODAtMLhmlPieEEAhuQ\nv3IdlaFzg8YkdeyPInKKO3WuvYypWhIjBWnmP2OebyZVsD8HrUqsaLPmIpUJKwdaTFDCrf20M+Ci\n5vHzUFD0tqRQijzmo0SIQV+egzgyF8p5mqFDBjyNWHAHRvrbuzpBRVjw9jjiL2esrjWu+xqbnyBw\nlHWe8I8CwWcRytbqgaYPOt5k8RFcMGPGHlIgYGIk1G7O4JSKwQ4ZmM+r6EChft7808+huikZLn+W\n2t7/YFCH+3S8v2G6qMD3STHqY1RKH4VKSosrRnZe3B85lUHpYE7i30U8pnVbQ1q97olq30RR8eYv\nWqlRNCu2AL2BFdfA+FewDWpqSwKMd16Z/JJpxV4ecQPJ7XDz4g9pCeRfWCiNaZ+F6TA719E3jaLR\n32x0SZY4QRTXSRJ84t4X4n+ht0+kAC1zSPfvlfZYpUeGXY1HQWTN8VJzRJIJ9pIfRzk/HNnsyPP+\nzMOHylX0wlVNnOVFjnvZEOfxi3/QCYTfm/bGQF+nSx+TCzyS9xp7tqGvK4u0JkG0JQ7SdBy10hwB\n9OAt5npM3zBRvJwcrLQTkVYS44nuvvFrPQ9jTM0gPb0YCSjab8KGRlXTcIhBLBGZurcQCr+2xnhC\nAPA00fw4Yvnk+gzj9dvqT2bzOAyTrO96JLQzATuxg0idHiTwlyYE7xIxjq0nZ288lnw1MFKlpwup\nFqgQkjs3a0bkloJZuF3VivDrXw1r5Ipd1iO7Pvd5hmtYsTdeuzv/tryOdrIdk3zEzXXtsjubXJ3H\naNaqFNV/mU2sjjaoKdca98yaYFC4Vb4R5tI9aOhmGmSweXIwu7b+/zCgG61+wjpHfG3zGRfQhqFi\nAAqqllyfqBrlX3INrMqso8jAzF5jdcOKUBuWrdRU+HpMoCY4v0nF1hfk/Nbcg/VtYYYObRVVR6d8\nJUlija97s6pYNDvc3X3mwdBvBPIg/WbckVyteAK5kSN1r0Ejqb8XsJwcNXLnFs/kozjcQNlmWDiq\nPz3REBj/DfpmTHZZ/xXRdbyd+n/GVhFAUkyKyWLBrLjgH/fTsu4MqC93z1k3WP+wLa7y2ZtQqcBD\n4tifJt0970peDRTT7WW2wGcrIB/QWK78i+gPgNDHOX1r2OI48VFI+aXYULBfuDmZiaWgOZvyODTS\nzG3JbV765QG5vTRrQ+sY20vKKfaLG4bQgdVLsw0JveArC/e97l78Okryhyc9ptGrQht0FQJvo6v2\nKYywkbXlPI3uN5MpdcdQiR4tZ0AjYS8r6BKr3Zjg7o6lzJPcxxjugoemCtLIr/yQLDz2iQlxUDOe\nnYwrQYjFV+xS3X6usDY/esfuRzKnulno8pz157FKtzzoWspV3SgfnWJWcOiGBOL1Mm7naHCuFkc5\nbtsQQ0l2GQkjqglHCmIO3Mj5eYaCDs1aYICWVC2fvrSmjPzRaTJgOt7m1ZLIAhN1fQtTyEhjAESA\nmiGzfRA85PpNhTRNbxXIZW40UbFFohkPLQRmEBrmqsP5X2WCIeslaYVl6O7JEeM68boGmleoRGTZ\nfWphSY/+k1nKE2Pbbf3a+c1QKQaXguK+z/SqjWly7zhlLCIM5Flgu8tiIzaJf0ClL6HpKD7aQFe1\nm8SSs4c4ZXzQOMCdGtZ+0+a9ntvrosMZSMvaSpnz6EYdlBeKaAxqe/aqnHge0ft46OxUG5YlnCnG\nHXvEYl9bWF15xvz0NV8T96Vpi3QWU833DypaCL3Ryn4HmzSgV99ZF1BVEOHKEZhSlJgHmXBQ49IH\nDJfArEmkTpbIpSeVNNQuzuuZei8fp4CF2m85IgbRAcySijgc6ROIbWPVJhzZx1THhQaXpQk3X5jH\n5s8jgCwD4OrT7nwH1kaApCRrDlRfmx4wg36m5SxX5IoDGeOpZvC5atwT3IoXKHZ09XL3GEDyj9Wi\nRmAcUaqgjMOTRdl6cb8TxVEMAafhuoNtCzsM/q+2ZcxBpFTXw5zQMwMqmV2HbPEiGorgMaIjm+Dw\nXBWFivIf30sa90q4YXFBEBKFmJwJp3gLXey6rhVn2Qt2e/mnHyQyVozcp+725uXNds4M48H33jkY\nowtXUXk5h/FFH5IWT+hfKFizaN/dOtgzYn5nkNnGUicT4OiiH/4Ox/j9Rb/b5cU3bsfgZqhpHkBB\nt2OzBhLyAUnWpaCB8AY99R0Ae/qFfZeKVjX4h6WPkM3V8la3CQRPWODRf3gqxc3lIIOFwDTwoVT6\nmsd1UujvMQMISQTu36M/YLAIHLHZvDVthvro9MCj39YWp3wqKeuJwtq6FCisozZ1Z0390sca05bh\nQriRRZY3hZznn/N88ItLwX7AsAqrnRR9BJssRfbP/NClzK4RqCLI/80Qtcw6gFjYD5KFHjXcAacH\neFQr1PMKKiSk9Ac9/Vw3coBXY/Tl8lbTz6azk8W/pWxM1hTC3lsvEyWBvhY7x6zVI2op4vwKZ4DG\nBhRFiwLojW7kqs8EOxkAMw+7Xog4hI8Y3yOAaSz8sR1/tdr5p+YJA/1mMeyA1y8OvU5nkkEXMr2y\nSlx1A20RcyZhbTmpnlvxT6fn/fQPYer2IoqYWeFyGPwxt3v5oKxdtXg73SCaZEc4m3g104JTmBjB\nZI9S9fReCQm/x5C9Q8wI7x0mHhYaaNqe6KYZdzK3x8GOsXPbNhHBm54x88mpJekIEmp7PsdMrnqO\nZtJJILEVYKI+vYlbPFvDVfwHNp461LxuKVn5v9XnLsJ8Z9UVmWQyITi5Cgz6ruG4inPCYFu94weI\n5ZZifWrWSSd7mZ7wRGlzbTwQLQ16OJbnnjABd8H8YVe4LuFzZWSqIM+XfAqtoWPWnZ5vlqZ4Spjq\nJ4hE5FCZYsc7IZTAJR0Ws+e9b9G4Tw0g830SvUmw/9hSMvWlx4XWv1+cMFt9Z5tfoHuPb1/gYRi3\nPLHjyZvxSkr//SlrEYPZ0uUwyFrqpW2NtZKXWZ7FhzTdn1vFFo7AvGv3IS97fUVPR8qjrNEQ3aSX\nQlcoKamRJj1/eQAe8AUENm1UU48pbIFiL47Ddcyf0LFcAunFLQkqc4SDTWqOBGByXBNjYRDguUZU\nIjSIesfwPRsTl2aP1aGnVW9PswZjy97NaD6Gj9k0k7KsGeYqTV7ad/YcIWAomtND1lCAHAmUjMdh\nt2h69NSEEPTsDNjnUibBrkNrc0cKRZ28CXPHS+dCjM3y7m6RvYbItiCh59jZ8wWYYhVebEL05764\nWZl6eF9QWPEoylEHLEnALQcksesYemKz939JQVEGfOKdveOgi8GgeqpVf+oZtr1iapUsgu2aQ+YW\nh/1yDeIg1dH7jPvxuVRIB3i0vI7qFYXtS6d8BU7raWloELVzpMDD/CFI19xXEAaSi7pP+Ayd7Ha7\nRK7ZFe5pS7dG6oabq970OUWoF/yUTSB3xG4Vu0jgtAyck1efnp+KiFZAhRYRGqyHGD9s7lO1kTwK\nl5wqonlZlp9IqdWI7Hvi6kqG8AAdN1vohH2t3/TodiDgF7c26MHQ279A8NGqQgCmxHQjAKYsGjkF\nt4d8sH/FWRK7OwbOluVbqJuoEN4iplLSRwhFPg3y9YTXrQ3vdGjGkk6jf8zgiWP+38+XncXdq/Q2\nVF6RWdnLYN/Hl3+sHiRxKHwRmTOHv8WQGbG4sTMH3bWAaSiEA6oKqpwk+/lyVxpItXAj98YpenDS\nm3NmLcA+COQjAHSSqfEgAFm6oPKcjddMvECaCQLGd2Ya0qO1412FIa+FaYl7H5T02NEjm9iAk96E\nVveUyuE+YxkgBKd04ijtgLTlYwsVWzP3B9cmAk+441OUsr6rG1dAlumgQ0jJ0+LEYX/Xc5loQm0J\nW8CxEw6oFVxlSZins3E9oTpMPA5pK/012kUOEc0wBDe+i9zCbjUjninxxCAur5ngzwFrZLOoAspD\nBg9zcvH1Exf7Egw4JKnNmubJntWHktBAcwMVW4ICgKpB/606zrFtXnSYusrML1RhNpsPD3EFHgb1\nbT2MNS1+rtYLBUtUbuf3DblFgLYbzZOWm8ZQH5VMISdIFbmC18t34o9J9Uh7oyejk6Os3WVhK+Ze\ngczan1o1ysdhlm3XiUhTdlsCPnxMzhkDiVzniFknYh4c5ESlCOFLO0pHPCs+SM2HOBv790mBbjUN\nEm3kNRASZd4vSDHVjRz876SkBfIjooM6XRrwmoQOTZ43w4nkBR53BmSywcvNCR7xOhBH6eS1VVns\nDQHGAH3k1QmQ9hxkn90nsL3k/JYyV4XJdc8D1DY/r0bnX8HI012w1cE0JRe8GTDLSvV7PG1K9lAn\nOoO3NdjWMIGwWXiD6ILsnSXk471mjpdM4HSau4L99CCtbueulkaqYgihmRvsb+cNxNhDWb6yRjYj\ndt5L1lO4DRmMD5KYOeL2k56HBkfbQ+u/fumVw1vZ34YFs9dXskq0LjUxLqBv6XJvAVpwejpawKdb\nu5m9wa3gcrk7w9ZMK7sXHf4M7xX9aLaxP8gXRD914Igxo/XCxufGFhhkqPJEJKM7UXHhw6nmXUNw\nph3xVEXDCX7SJ5hFOIfBMK8cPsEtmNAo1NHbqrwPJnQ0iygUoqnVgEXIXSyWDf4BsNId0hezNUa/\naqu/IX2b4y+sNvA28VUm9GQVAZfxhubqFpmh+BVmuFCnB629/PTq0BXJ+vifoKC5oD/ob/ESV+5D\n/3pfzbfsF5nqkZdfaQO0oR3i2IhIv3v8dkI/ozKmuJ+3brsMWyhebPRqdh7ritzybmudM0XedLzg\nGUVveIn+lh8vLgx8pQnlyCWUgcAFylCyBlVOWwMTvkVcHSWYSmetv1kVhxHStIP0WVyrKy/Zdq4O\nAmZkm8SFlkSQAUiCYQtcM6NK2W0ZZM38NLQsYOsuQezRzJxRTofRmJ8GTuV28rK0/4/L7hgIYtgy\nl532KivKCzoi+zlDkc1jnpbjkYZ2iT7r0C08+S8ZE1MA2sK3kVpBvjWH1nfqerR3SPKGZzT5s0TI\njV6mQIH+iKVz7M3U60JPwl74C4ZkH47FD7JSMgFPpi/tDB+V8wZHUAHujm+FmU9ZclLkG647xEue\nHbU4Tc+LpyuLYXzd0ApDsNFxjDsM7CFZU0+Teev3Dvn6LXzG8EFW9yP5UYpmVoOIGNOu+UD5umPK\nAd9H7lZkaz+7pTJP83yhXKW/RvhCSKLJzyLlBAzKzqiGMaHI/0ukU4s4A1ggMQAnVTvgce5y4HYa\nbq9LXXoDOe8RN6E6Z0VkXSaRasWA8Vt9+vzH2bXHPfrABiP51GcdCZOmmM610dinjPKsLv8/PMqS\njODejkUTPHpEsaWlRUY/lMSwV38fMTtjTjBnJ6rwBqqrw/BzWNUzsFqjU+R3Nfxjxr/7RvDYSsiX\nJYjAvPbXdCmY1u0R7wHt2uF4bB5KzGS8nMhcecnk5GFKaRt3i+JDtQIOgNoVsARuG+o2KcYp3tCz\ndN+cDf9/BWrv94tTivBEaQ6Ku9s4FajBm64aQGGUpJFM5eV3zMwRbR1Fr6zk25YVHV4s1R/qEXS3\nIH58xmfG1Tfe2flzpJH+yOhP3gasFOalcLnyrWibmaVOd2WG734HJBy+i0WlRKy7VtrOA4huSrW/\ns0XpACl60QsyX5YwxxNzdq0zObd4mb1aWg2w+OdagOeHhZs+EcbGGTietIYUO8OKaNWwI5BGxIol\nbFL3mqcfIvB405DWTweVK9WERPD0EN499gPKu387MjsGjKgN3swzndrudsk4eqztRf3RwWdl0bCl\n3gJSObwbcu0xeNOPls8spYWXNCOXRslzMKz8yUWSD+LE3ucg5Qi0hA7sM40DDHcv1s5x8/yXKuzP\nSCaGMHjwI1J92EGZtMK/BSZ4G6x/iPhi1D1iRwesv4DLbF9egHWuagEuTMmhtlZ7/GkH5UVpKbv7\nJwL67WvVRg3iLQ3f0eeDxfYZGddqo8kaGJFDVDZFiB5osRsxQw3uOVzXMdUDtAmxxrZX1VncOgqC\nveXdaJeTqEV8eLdDvI1W+5kaxTybGN1EjYGvmnXJT8Tw35TiKYUlbiCEakGkgu4OaAWchgIlIbE3\nrlD81XHUGmHAXkp/IIcKA0p8C4wNJL/8/mx2HRPvdpdQWlg92ZAjCBqqLRRO2R7952oOhbwtKKAj\no4vmhmZ0K4Sbt3ZrWtxuLn7DNySBjJSvjHpn3LRhPXadtllc+zq89T6cx81TPrOhdXJKW4RKTqv0\nFcqcFq/CY6kdXAh6V+jLQP6e7i8rurrKB/limbm/5A4lm2BIRKt5E85DOAoQVPL3cyLuayuHIARk\nW/9iSXRWPtMLwOPrpUnn8C7tZnYi1sXQ6v7cpse3tkzlrrNmHWnfsYMw3PuG6rYoGovWlJycQxpm\nQWH3x4zWRXjnd20CzQWwB2TrVq+P1NFtCdmLqxWTqlza1+d9U8XfZ1zwazTiO8mgy5tFMnASWZc7\n6vjFMcT5hFGTpcI8SLOblKIqzulQFE3EOi8uph/6ioFfcILSHRJEQRKCObirlKbi8uJkwZgI+oyK\nkgeLPzqgAlz2TimmNimom9giG6TcwZz6+RFyN2/jscZTvKrEHPHjWSFBLmMFMw8lFY7AuW8rhZCq\nBADBQi4w5H6uHadXMSWMioARVddNNReLNxh2XSvsRK+YfGhv1QM8+ON3u0vTaxVm8dTgWhlc3KiL\n2TQwqzwxGtd+Q+NTdGpj30zRTvb4omRM/2WnOHoccfD+8Hb4pP2P0x6MB62jCruVQDBBig+/tBKF\nmar+qrRopiigbXWOUFLCP2NI2gEJZaNL6lvfqB2JmSjQxnNShAhMFjcwkLUAdXWI7y3ytvT1bOPH\nmTy1ciVSGOvlwgN7kHTBIrU9xBwEnvpRq5AcS9hu63M5/lVUFDqeX/wqYTPwDDoFKtgGmJQaT5gP\nwsOkuv4RxdrZhm+zrst80Hq7C0fgacQOIG6mIov/hnvelxEeJird872mgvlSIduEZlFp1NA4VWxv\nezdrKNDG9mWAenuWPUI/hxs7lyzPgUyxM/LdY7tztSB3s13Q3iq/+1S8J5OP2Mm9bzVJXAVocFon\nIFyYIi256MNp2HhKgbuAJayqWEhkxreQu3eBxxkCeHrhc2gBSpAwqogLbxyfaf8gJMVoPOBgYLpO\nvsBKMMGnlxH68xHOQKaFDfmHF/Ai5xOaAzZcT9ekrJxp69Y6SJIRtpuZ5jLxwFZtPT7MjrC+2Qzk\ngPJ0lZlY/y5SuRtz9He9MdxOtgVfHYomdDtoAHYedfc9zggOwXslXwPwhhnKyaY6fhCXZ9BVxsXn\nQh+SQ0zNrdBRZw5iOR7D8Uv6v/or4ErZNX1npVCtnKSUZTY/OCEeKhF+lABnUcGw7Se30Q02kyuk\n/FSfbgL6TJTpABCMvzAr+t00I6bPOVdo5wDcFs01FcyodngmXYg5v2XHTNBnIrc91K8rxh8wiI/z\njXAWLNubQROpxuEWhaQiw2omtn37+/ZAyZmaqV6cPZe+yb7yO9lpAxXfw9/wbHIf/QoXYyK3vl4Q\nCow/LkXgSmqg7fUo2MTd/Hx6pu5fjGcVnu8rkjWRCZFP+zALiJm2UY6bg2EveXXwjjSEortDRsqw\nPP87v1+JWTSuu9uxuCnV7YcshQz85G98G1r1vQuAReVGfKh+rzakTux5WcKAGrr9suZHxYpo0/nj\n63wPurnEsCk6bsPFIF5L1/qtp+qgeGkKm98K/fxc64vz64rpjbZspt2+Es+djLO679lCt2b/sPjU\nId1jtVSEAUm9Uwz4v/648SQOQghJZl31VXheIhUnTf4kwgb7FUlRBZSUVI6/rglsYnxCg1lOrQXz\nUgwC5o1rScLQ6Bk/7RQ952VYslZO3+hbolWfSwGIwoxLRMc5CYnocKLR2bGlYFf2lWhXiNNDspKW\nqXQOpBtSXcZc92u/1gQ7X9b5sMsHUgRYqAqPvzZcQOum3lQoEhTrMukLp9agLQfiVMzQQHfaG2gx\nJrD2HMeqm6vREOTczmgcx/hkK4Vjs4mhBakf73yYIxI8WfoI2AMPuFRqImnvSCCcue16se6MEZ14\n3EfLJASd7+AE4ETeIs132WdPVWuHnfpuHLvLRXIyty07Znbx3f1Dr+pstqCs1kbW/UaOU7SGQ8Iy\ne9eHfF1vEA1YSvE8yRU9Cou8Fr+Gp01EeDlQj0SkSoEVtkwXK/pcGVrTLAhIqHaLAMBYaXQtITQQ\ntcdF4uCqi6T2KWtEbmqZXq34PfSms8Y0ziHP9Ws6NacSXpWC3ENTk0SZEQbpI5nO7xgBNKkJEABA\nAHLsnEBsXDX4BeXJ/PIdS8hBuY1SjQgWnq2yPNGvpRH+YXLI8uwFCXjL4YQ6hLaDl41eoybsZhvu\nVBiV7P9/kRcZy68uz4CdzJ/orhkstC8q1TBmOE15Vws6jSGAAPDBQ9nuKsTVyBku487W2R0BuV3T\nI4lL/GVI4ToaCMmbxGXqa9mZgxpBixy6JhzxURrGh/CU17IhcU5ObJiZ9jF63U6J7yoH8EJqYeQy\nY9cR5C+K5sdrI0DtTFgUXR8Z2jcT3fG5HB+In/B5IRGrIfmy+te64F+l0LrxYf1b+ErPrrq5ADJ6\nzTHAvzoMnnfvZWgXoSi/D2BURca5GB1Azu6jyVa5TuMG3PONezYwgs5mIVVEGi4WDNpf9esZcPvj\nlZJ4zUyAKOJV44Qzv4oPDUNhJATiY1Opcm+RpyTJOExqTK5LTvjMpf5sbV0dDaOBLWhhLmLQc3MZ\n9DQHzEVGEV7VKoviqyUyYt6B36UJDeHYbLIikavLBcB4YPNDcWeGqJN0ksKNrnFks8/Zuo7bFHTR\nPLER289H/T2VSn6K6Qs5nrJitSVhraCt7Ykb4Y+29F84jiznnYrRAM5wbL18MBdue7rd0eDuNU6G\nuR/4YvjzefREHLwHgC+PwhY1xVMGwLV2QUylq9pTypxHV3dUFlyrNkc+IbsUOOAV7aodnMSpcu1u\nV7AXYHjkEKwvhnv2nbMRUYHSN3/57Pm1xwRj12dNc/+FsmCM7TBCx/pFh1szM4YJvURWe76Ew/lf\nQe08WGdRr7ttOYr/x5z/zLIt6WHBo1sKv/IEVt6U2dq5wS8RUMswRaCt9n4dzzRrmrU2gV2+X5vz\npTq5vDfZMYiI0HhT6tW+Jflb35f9WFezHqRrj6b9RdU4jiYmjRRRkoWkFWBhgR9zBykC1bcIGBxt\n4VG/tCAirSeyiOlaLPHmFR7uqaP4MoLFvS/AMpQK7zJzrbdw69XoZxwmWMfzM00Q3Y62plLJ0/Lw\nGa0BZoXDQ3JU19HS7nEC4V3zkDjMDzZkO6ox6miByODkkD7urrAgBHizPyrEEfunIOtjfkgskBOU\nO4kMm2xEHzcnYXT6im6iaFZrYzn2wEtO9ATl/O1Zt4UQCgwcMZBOjxBD0Y1s9EzOFPKeGvrxu9gJ\nuJUGt0DWX3T12zispoBMGDTSXOwCH/QrjzVjBCjsTnZccGZDJKoQvO87CfofX5rjD9ThL04wE5FS\niBf1LS9Yvpue6BSNVBSLAThjQgqI+useYhW+k24aRtjfXBtc5HCiAnrU4Lb2qUbRTVI9pbu3qfVu\nrFw5QIByvSQ9nOoOKTCwPP5LtuDxNHThnMZ9KilkE64bU5mumzUBbJecmmF35k+6ZwotNgAaJ+wL\nskH+bbpLbCgRkjCeG0JszGKZKnS3x4CDDKvdD2paPvXPQB4AgI3UwrINtFmgwDwHYh9E1cvh8TjD\nbLrTlyevuwwKF33ioOcMPsx2U7Yhogtjw+8kgRuyR/bKM2yO9WKFqpe+x//9MbHta/1Et/1eYKg5\ngKCFY+w8+T4SXqtExi1p+j/BBl+j25EJUsP8Ds72ozHopQ9Bo1AebVilmr1p+BQDjjQewSELgtZ1\nTu1/VzvLtUYaNVOYS86hQZixLmIrLbrNetmMDf3mc0bTVKbOXR02+0XcTOktBZfbguqbtmMaDkDw\nFNQYPTxwiheiMmxSNpaf7dTYJf6u4OYcthcl7KbJuGbcLkHrnjekwOv1gDvxSO96XMcen2CMu+Dc\nPeiYwvGxJGV/DlNe3Hw0XRIYGfG1JUMIz2sAm7HsaF32dwmmWy7/rRY+JPWKtf5HJhgxhl78OIoE\n8mtjsCcv6XR/LOFNOp1LPGGNRi4ZkQMwX6ju0OjaYOfSy1qsJAXSspNupD9/M5Bi904NLXeHbfJg\nUl1pKY46tTjO1ZBEupd4TLDoGbkgk4uUurbm0PMgiEabJJkRqvPK1R0Gd61yg7lD2OZ36KTVc91m\nh25U3f9TUjgmm1G5gdHuZosN0/Bvso56K+67YDnNb5UuscePkDW7CRf5L/PdpsnJX8TSOOUwkyjB\n2oHv90Xmzc/XOR1t17srvN1xo2CYUj9L3BiJenwUVYlVubq8DoFLReBqBPcGmRvOIOdw8kjc0SvW\nd5NBIJm/g1vnUedEi3QETyPk95GCSUQn0cDuGMKht+KIgTHNHKCfvy3NJd0QI96cIMRUxIFcn8pW\nqLmltwjxudDkh+h+wlCbj0lL616Fs03WhexujchtuWmpbQzRfXG+o/db+ebwSVNOgngS9Es9J/Pk\nrCKjDQMpDzHQN3Y6SnwbBCEbfFHIgEF6DWWbdZaDuXVvhMt38kcCS3VljarUCf3SAOZH373pQepI\n34MHmJc74eWDtEEbDswOHsiylZ3FsI85uOpRbXt1kd16BagFhI7vi/yed0tlYi3ThV6B2/gEkV8a\ngBGGB6bC+qXwOPcCY+oNJxfQGXFBmGsdC7o0i6HTOpI4s+IaE3DjAlnPwlcBrzjPqwa+egI8aBLF\nSZ2kh9mrASjPDo4yUOfpxA5gKbskyyfJh/M7EYIfT1v61MegCQvlU0GhnI4fI+gX/8OJc7xJcT7E\nTkk7F320KOwvnJaTIDGzX7sxGG2RkGQJwQekp7gE5iEO2AQ2j35votCZlrDLi/+Q4MTwVonEPfaX\nlB75kM8668yYMr53OY0l/K1p12n7TgB7a/Q2p9IhywXHFv8ydebE6Zh5RO73qNPVvgWaLH+Wg9/c\nAFEyWhtxRHoQYo0CIGybZgRhyZEmczC3zlZcCdVxuLfBmY/btdiY/mpCAliSckSkcqA5tsExFywP\nhc1Ae7lCsP9hV2LgloUEePoT0bxxUpLy+LPPGOJe+bP3QDhwYMZ3Ro0HpxDDWsgq0FwuqgwX7P3a\nwJ/3weO63tZYwWctdCq6rPbSJK9YYfm3TurLUM8mmigT1L9fMZf5s5uqomWGGVrQB7eCZhohg9Pw\nDgZI3d13ubUwpK6ZbL2Wnx+r6W5ISE42b0RXRpqsS/T/Ke8Cb210XM/oN3kqe2X4Wbetc/+GYH4N\nT3DEVvmHItzkS8ouG1caYWH9ijAJ2XkbFC3FmIFqNKEPY1t+fh16OrGBc56jjlC68BmMaHdoM5tI\nVEjKzple8SW/OK0Lqgl6jgZePsu3XjuK6F1kYwSjoxihyRcuIafotxZgvZhR8ttpkENhak34X19+\nICGrnGL5kUK5s40NJjJCga1ZJuRymwxIAc/YwDc5xYWt1rXjSztOyNlcTUVbzTfWLLkLMUGz5/uc\nZa3iLJaYCvjdUSpx3eX9wtTuPbpwAjmRW3bby7pi7I9i+NwW7SBK/MjPHVyeikUDzVxU+9Age0ZD\nlsjdWjPyYS69p/U3FMt9jI25eiVj4YdqoQd7lDkvE16szJGpHNHWEIraaihhfr2TeNWFjve6s4+s\nW1jL+elV5rBIh/Qtaj9ZOxnbJWzVFO7XcvKnSLwmSCUnPRZX/6JchbvDH+aWlCtK/weDYb8W1deZ\n63R8Z0nBQBnhWAl7W1GtFJf0B5x0tFgDV1o5UwoiG9WKF6OxOg2m/svrPDHiCb5KIAPZBt/JPgbl\nR0BxVqkOTOlVIsSqbBurGHnS+v/KaD1EPVezFYsdPuJWY8ESWE4umNB7SAMM8BaG0ngVqeSexu7W\nyph3xC3MEhra+sdssC5Dh0ECwKAKWAS0XQ7dbi/Wvpq0nXWJLx707EDe9+7Em+QigWMOraMJGOA7\nBv6ajx8UllOpj1aVVb8hyT9xFN8+iXJ+GiMclHuSRW+qfrlZ+0r6B1BZtIfV0adiWGjeLf5nPorQ\nRwl0XQn5a44AJcVIo1vhB98SNNxeNiY5FqZHd4+uXzIO5UlZdS53FP/YM6kzRiZeYiERYUxdz+XC\n2XUfY6lqlSK6D1jov+iPVLnGw4pz2eB+q2nDdTNIloUf2dzmAyzyIY9sJlwlUAUw+dvwQYpdt7Cy\nutFnP/5TyXX1yEji1EEH8/QAiiXAbsWnskYkGCEGc3w5r9sSrDK5FfGCYXukB+JwxvabbvJWPrUV\nUqg0eqGSE/FMHnP0Mk2s+a4Jx4Ej5PQkTOyEJRHiTAmkyW/iKoGpxyuTj9QefztfxFLEFmh4Npgw\nz/x78S+CWnVB7L2Pe9CmWNVmyT7OMXYAdE4K5W77TvfTwlVFXY/5bHoPLGItRGckkyd8+0HfmXZi\nmsmMITpwJG2LYBeATQl2h6sSb/2lMCSHy27zFrdxNhkWnDHVXH4VSiw+UV+25bKh/BonAqrwTHtv\nxkakqJuktx9cunEtpRmwPmz0A1muEPzAdPHBE8MfqhbQgA1qobXpgIXD6+Ofl2PddJ2i4bJldgUZ\nVwN4XHaviLFFyOsp3zeEbrLLicSrkoBrBOXVcXlnd237gl2PWF0hOtQYWImfd+fD/hrN5VZejLb7\nDEUhbU+w7Val+BZKIIQ8DOWZUa4s6k9UE1hnFk2MMZ6B+G3oYp8e9XKK6OViKHYQ04cUGNKWdSu8\nwzXhKbfx9sQWNkdPEfqbKcEvzbYypYIxkRBpICUGk4j7+vhk2al7T/dKGcd/rLV1PdEu+xfVZUpE\nSrJlBLdwPWMWFiG74Z4Vv5aKDz87oy+S3acXfdXO2LLlW1Z4M9M5ZsqJLGt/i0mqG5rxDGQh5+xP\ncsQ6yHKH84KlrvxLc2WYw1xEsrnxZLUPnJ7rEVDziWukJz/izP1nZ5opc8GqSjqmdgWeUkYrVWEN\nKaPvp/BRsuLuaL0L1tYHhtIpTx6EgWEbNWiWe8MXAaghJ73H6hOeaTnR7LnN1rWOll1VpBgSDXIu\nzK+qXKy5iunV3PHDv6GgqFEjdcHPzWfS1LDTfUm5WdWj5XjQp9kohCwiI8oJORlMwYVH32QUyoGn\nP9bPynkizpXo4RMwvR4XX3LRMLdyiBEeK6SFMalgmfX9q+E2sAdnFuxJ6EMB0PgQOJO2gC/5L4tQ\nAfALz0mw2QqkGTj3dZv3/5sThljMWLI/a+EnzCHTKdfNfCIvYPd6X/PIEqNugr2CiYm1Su8oiREY\nnHJCJybdSMmt/2vcHGJx4dbRaOQPT26V8YEFfGKVTI07uwVs5GoFMJWFmRq3G1wiJzHa3jSjQfc/\ntVpG95CxnUR+ecJHE5qKF6nrks8165PcV8QSWOiRe2RkhLxGFeHP2PKph0Ab9GH37IhYZ3FsVzLe\nE+a+fDmIiHn428VymEQSgokokt9xzBZ1lLSU+5LDjGK3a257QROohaTnuhXSlEM42Dr5MtQupKBA\n1hIu2lFV30JFUam3SXMveCgThC2rt6+SWFPhirb2j1TyZUpDv9FA0PPAxNF9NydrBApsg2D54A13\nZfXBnBWeXIEWOTbDd3fJTE8cpBo7ydstNk31hui0qx1ZPQ9VG3/4X+hxWL4tUAbAzvLWtZFJ+qWX\nZhm9/KhrtWVU+4BmykTsMQFR9XmRXLckB5N6aDXQaAPCHL9twCKMbZ4BKOUnds+AbuQ2mNleMPck\n3hlV1+5CbgCWg1xwyXeXgApJe10KVydtFzZ9ny2pVJXO5565PfGvfW52dNKvKfL8Onse7k9q+z9I\n/x1l5gazJikxgRks/EtbAR+Ea6XJGuqYFD9RCJFOxoYBExcSRJeVajmvHIJI7JrGuiU4lTIP+YlX\ngBgOaa8FUhpD26vPspdJM7MOZWDTlnCkwRddEDw9FMLzQoiLwzEtn1AyQRqApz7DSyGvNyVZ2dKi\naR2G8C78JK2vHa30pCr7wyrJcnfP7RqXbRsgtETJYyzFPXvH6IaSKH1Y/eOnXxnX1ZINilIG1swS\nN1qdSdI2zRbhYMIMr4CB9AFgAxfi2+nG0TeiAlrSBzprwyJxSy15Ca8Jv+puwrUGyA6dxE79SgYm\nqkY7U1M6MLoJCUjV83nl5SLO3Ciw5JuJ84yHosoPUyxFXSlqmvZsbl8PnNP8MqLuEU/CizjBvA4x\nABIABUEANvlwUocnYaQsakAN5g1D2ac+mbdD0lAVYwXpjx5Idk5ZKRtw7ewQ5v0FZ1rGYXZR/qys\nSKnshxaKql71I3UE75M1mHk1LqW6juSlnFl+UZPAx4RYWKFuSxKWLZzRWztpll66rV42Z5SYkAmw\nCfXaXch/O0pYUZh+INcmS7T7AAgvK7iR8lMvchRJKrxJfntpTfpgqUtV0IdwIcHUi8kDy4T4I1gZ\nd1si9ymN0hVBbJW5x2T/DZKBe46i4ZAB1RWUJ+ggMA/WY7++gFlE78V7R1N+tjVfJzManHeW01pc\nt0c/imikipV+Dwq5PFwI+RopbILjVeXNVmIycg3yGnQXym8wkgBM7SibBDYPfvbs+X1lcnzX1Ja0\nZ0OvU9oYQ2JI/mSUAhUCxHyI9YC+EE6ES7Yf8WLH38Q2KBtVXZ5znTShmXkzw3oN22/1GKY3k1O8\nudQu4lJFD29NQ2M8vQ4dm/nKj/D77e1oGn5VwMhWcjX3peyEcUI78XvHD5ZDhvrHtgv2agdjtr78\nSZRkHWJcATOUb4c7mmWo9b2EQWpvxy84l7fmskTKcEs3BGVYU7iNCBm9RFufJZQeKu0bh5mW69MP\nFc6cJFaZZQxfXDWbdKYFFFRmx9Uy94WqLxlq9JlNhwVHCfRvWZfnhiYx2PVASKXBIVryj5O4FRyQ\nw+TqfPKxPq3UVqlxKszMc9qdSgEtP82REBG0ZYIPb9FKUDt0bcmPzBdSKfzZI4jjSnj7gZWApjQb\nvliib2FITtEpnpsN4AhobrJcHLQGpEs5YIjfnJBwt3IXNaamcjiJ0N9h3u9b19vhCzb1C0RIpjnm\nr5WggAgre/oVUWqDpMBXxce71qZO5rLW4MjMvIJZkyYCGsvwPFBiNXysSGnLMsLiaWhSvKkkCGwB\n1VQYYi8OYbx4m19Sv1T5cXyrWrCxpLcnblVZnJ9+38J2nZiHoLx5QoAh6YM1853A5K0CFC/P9LeM\n+6D/kFPuenrqn3OXIsP3zTPHT+KHAlEqc9GPcK0z9OdKOS0fSXbyIc/ZNRvSvkf4TZFPmy7hJSfg\nW18QJeXROwheuALNFXhjNcQbK8X1VNT2Nm4jcw8HB3LPF6tdzpyUF7khxb71s5fiBKX0JAuLGDSl\nFrHaheAo80i5949UphtJsZDrSb+zbkjkLySPfaAJ8NvYsQQ0VhuJsABJ+WEgNkhpJIwpRd2kcYJF\n7RD5a+po1qX/gAbpPIULfR5+J7Rya8tRAfL4fJ32ERvjY9lLPfDP2/nKnN6rAtLOQo+kBF601sxs\nlm7nCzMvtkLBxzYg3ZmVGz+Yv9pDySxu6IUswQQdzHE5cAY66PCVHiqM0RBmhalX1kMWTD9ElUKt\ndeh7BGk9SxDojBxFEaW3/WyQGqdXnqi1ouBy7fuWB7ZI2/VE6rre2TRS5MFDTSkq7rqniCqZYpn4\nqevimnygk/qT8sVBXXrboAMYXolkIsal27POxL0fmzqTM7DQptd8d6EOJ1yX0wzg4amE71Txb0Mx\nxwxMBwVbiz8gUbjMWFMPjg2QouRnXTitGdmuGiEzVA/P7YkWS+bOZGOlc75IBQO+PtQWb+/uLFme\nGhkZyL5ston3FszG0CeECQA4mDXzkby81AzxuoK4DyW4z0cVzjycEzzXH4sY4MX55aTh12CO+w9+\nMsMcLF0hIloFgrUAyFuymI3M1sElHB+7dEhkmleFdS1/ir1n7BBY2aGkVxBL45bYwJNJTswVaF8e\niuHoGmTrxYPLKNSqDRZvz3juQOVXGyql3tfrmdm4vtDSxkbp1fRcC7VeIYzS6PutWIphyRyRKUf7\n1iSK1yULRVs7ccgPkWT+rBz3CJgh6vKSpuNx5SQ348bv5AyyJHLEiELV6QysXgmsP6OOoZF52s8n\nEqA9S8eHYeMk7O5nyOGu79+AceAWkNfz8vawCLbT+ZrZxoAv1fFxDuZpPGRMSJ3MzyQeqGYu2HxW\nwLrRhG00qCJBjabSUIltyxETNEY4o9dLhFJCYnIzazWL8ug3+EfbVfAzGPO0A0atjXcRgIOOqdTQ\nJpxE3DGBALY89Mx5quyydDs7qpWxn/AjKUaoPT6J71oH+X3h1UlLJX+FlpppBy2h2OTQanxgkLrR\n1w2IY+omq30l8hgIDLqmbZWkZuFprtbpdEakVKoRV7GA76kT7D1JepJuSDMlWHq07tRn468KXOtP\nj5Hmb46bPMshccRzmsPFCln56qr01j1dBgREMP32XlTgcOeLRupLrLWKCOG8uSPpbdpl4mZDNQzA\nFRjS9FE4JdzVP2stqwHFOg6zRcXS9lEK8ETs79hTJF7hpRYaE55jhKCayen6+tzV2ND2BfDTbX9A\ncPIio9dQ8Dxjk5/nIWSf5tHakvCAmAlFc5ynF4dNTuQEdRx3qkkv+FN/0j2pyT+Ltk7QRYOEiGqi\nxSlh4ktcwEV81U6KemfbzKd+SifI0tXD+i7c5F2q4sYmQxjgHCqvZFBun3FTJLRoLHZkeEeKZyce\naIPGjEIvxj+RGPLnhU1Q4cYhoIAWSnVeX3jWrbvnz/umF2ZZJVyOoSPittmZ3tUGSPG97AxHT6Pj\nLmu6X4pCm9bxq39sEO2UMuqzThJtg2jms+kMUE7rM532UIaq+gOhlDhbOHZPg24qmCCRfDlIDWgm\nUCFndqFRwbJ2p9Jy4WhaQJO6BapqFIcVtOWHDBJEFSNyN8UGEhGUrRkvsytuCc4JO2hnogmsTSvX\ns5yid2oPNHo4VqhphSfSs7D+WTTOz5Ek0rZD9xOFggFSqsxwWRju6O9ejJKLt7cpUd1FlyVKQItj\n+hF2kpphbhfgBVJyiciPLY5q01uGYXzLkFBPeeV9ABilDB0vbxw+kk1/98w6XmMXtqezFOQOBUZ3\nhoDagvUFmbKk97xW7keLxggbn+8iH2CKfBDmKyLb9KniqnhCafZcGapqd4aj1llj/oYYNJKWlbEJ\nvlANnU2pdZ+1AT88VV95KZT0kI44TOmO2m8G/JJDJaHPbWpO6zrSsZCmiIkbWC4VNpbgUNOV0eAW\nmFN0EuSiX0xuJAxylgXxSSIp9xAQvPaj0O6raEL8WEGoROzQrWXjXAW+XEaKTkaZfqnJ11iE9f8n\nlskhbqEY7RJu4xA3AxiI38KkVJ18pG8Z/O5C/kMVf3dtGn4/6U339hgi7fw/CmPMkByKZHf5aB5r\nHhQH+qNq7vJWccV20sZa8DQyutidVw23frS+KG7HCkuvq4LVf4arAjP8+Fy8k0bkwRf3ZsKoitV9\nsmOAEDY5CTNDwnTjh5WxeW/RTAhdEyBGUtPOIgjQn6DgA+fAtN7KSpBuGdSYcRiKF9nHIzLgcWsh\nKjVQOayG1Tc0GeDxtqDwvl6Lb153JFfXBrl6clKSFJmxT64WT3n2G6NqJAbjOU0xB/Bv4H9eg6YB\nxH5bbLvysPJG3kJFqp5mEJW+eIf5B2d0nZuBX7FvlKDBl9cIvPPR3IjP8XmUCwVU/iNG+60xJ8vG\nOCwgsdKlekapRwdDVglajGjhG3SRGgP/UFBsYvD4rwLz3irvRrswcy7Z9Fm8UE6sgqqwQb7WTFT0\nduEURUVieE4gY7u8Zths8TVUT4devaxdmRuH6zRahCUNrGvNL6nTl2RNWWIPzbhYYjfvgk4lVl53\nNiFlWlDww/1/blXLpClY1K4v6oTmXLlDtyoVpNP1zAzmo8fwej+P3bJnTWMMjlMcp/F3IA80vzup\nv4l1TGROqzdhyKzJ0VRYsifl6ZKkHSA6fmdXTRLO5yoNgmXs+wBgvQ2PRy+elH1WV78/HWvITLhs\nXJu80pNuVsbit/3bMQ1bRXTKJ5zeybKf0XlH/UcbLq6ievg620ENif4wrvxqV7SwfbpVXLEAJW+q\nEQkBkjqhDVxWOwr5N4hN5bl04NGGwNK9tyfGbkguDhOmWboaCXSBmRJ4wiMEGq3htB/WXk/6f0tI\nqT1AvIABOEpVv73/QbXzXiz/D8ivVuX1VLB7iqMGT7I1T7nuQWYWIYMncq4s5AuPHnLwLFYBSuGv\nlyDcU00vlNWTs+bASGfIh76ztmPqFSM5z9FuWLTUPhH6HfLbhUw5hhw+vumVO1kAnoS0WSiBMqzT\nLC9gmqgOp0yu+ZSVJ9v9X34I0Qzqozd5bi+EV3Q7nVdWDNbwCHQ3BMzir9gv5lDqCeInzsL+Ks1U\nWSwwsf5kpR0iPif1EJ58k/jrhuGfuUg7/TIKoY2CN6NXW/QGEu6K/8/T88ljbHOZO76r+a+IkiXZ\nB3s/SkRGcEziw//aUVxn1y0MK3+E3TPHpkDYOTMMLkuPhJmTWwqJCBKn2G5pFm2ecdTlAJAAprRp\nSgYa+3wXf468al976uAMVFraNpJYu6Hg2afcZXyHm0AzfTpbUxBpPuoCI0JLR8l05epUXK0ShonQ\nl264KNBBQC+coXDDeLnI0LBvuGik2YCnXo9WlVWDV6KKQA4ec3JJfjAunQBfwydmmpN6sg0ZnhNs\n9QP9mR0BRyt05cpYb+W09GdXIhGTXlzNFZg5IcHGOYQM9D00CrARy7cq4nsr7fn7qUzGQ9zznhKX\nK/dvrZ3SYgeci5rxTOUx8vFLrjFYE5/cbuGZSrajFg7965CwfsaPMf1YvQmu6q/qYIx0ILvY0Tpe\naOQi6hXyMvhpWfoh5VEg5sfCkYYhjxclkaHIvC5fG34IkKV7R2KqI/B62ZvuAg5lmmFnn54e6Co/\nF9crysp5jZsieAWlOrYLR/6RspJu0f0E1/Y6wQHdkzysHg75jnCbGQOL7jfZSVtKiuvj4zHxflWR\nIHKWAmXPXUZbaj0EXjKBt+ncVZspu+nobDrWU1rSLzezGujmBRfosrlCtaLR6ppVcjrATFNAUp3R\nSwMu0W8i9Zvz8EdhQ3uMb05FYmd56mmCHYM99M/f0ur1ol0kxhmmwzi4MWMvSsHceMUyEKqcv/2H\nJbMoJkk6R4Obj6b+OHAmSSV+H+ZI1UVaiTLCwpEYSfrcXV+Z/xzpBnVlog1hsPBOlHusj+Qn5YTo\n01tasdsWEEOL1PRrkxHPR7YUp96LvyfFi5ujm5zsbLCGpgNXackWqpVqAgebKzLFjgELUZvUvELE\ncGx4/qNUEhDbMPWS2WGd4IFgUNnD2qr7liC0lb7g2jzB6Hw6gPnfIbjgKfuovMZg1iwKQ0OqX0Fl\nQeqcCpCEmcMqpJ1zZaEvyzZc3jjJndqpTPFx40h4peGLDY9ADlWorz3SosX05sMqrkKJqlk7dMB1\ncaQBm/ItHJ9oM8m4YEy6mH2FtDkBMbJej7AyqsMi4pLHoLFMjE5VzeG+RHWt6kGEV4akyXF1Y3VF\neTUg6Qf0DWSp2vyAEnNeNxuIvHGhHoFf5aDdyiysyfyEKh86/I95bDXrhbqoCF93rWp8tdLmawgR\n2biB3UcbKUAPnDwfbKfrVVb9SqesX5JFFLkxvYkA1V41dQ2MlNeA8SoPVfyXB8kPJJIiQp6NRs3o\nYtdcdw4hpBq563LPwsXzDFmk1cefvr/4t+b0gjy9/HZp7ThEsDm/913Tja/1EYZzKRNoniwPO5PA\nivo4wDfI72LPIzkFvXY9hwDzkCgjKnTwZm8g7jOIAV2f7GiLW56/lpVodDYT0MFe3FuEylfUAmdv\nlo9kTlRDAjEFuDiIvmAYtzZ+DTJTg0AdqWFQUAEeyimKy18YjYToMJLSaQaHp/bQfrIYMFUXoo8I\n4Od7OeBhi1lMGcXdjgyyhwwyyKhflavWQywXR/OtGhHKja6LXB2T1K4Cp2g6W/CMB1mPZLU9CYU3\nwGVBL22cwFJy1aNo6qW28Eai2/ulPMUa9tVCSAtyCVZPA6F56MD982NXeSohkwC5S+YqR4RcXdeD\nf6vW6DvCndSLmRzCJrIHgpJaex5VimiUC9aMxVUbNiI14M6iGug8BDac0I82mdown7pS1OCF+FpN\nzBTDdtDreOQ08ND+qpmDjHHOGOZnaiUYST5wnA5sD0dC9Gl/f182P5MFEndmVClATXzPo9sttTfF\nJ9RGjd4cy9Xo8YVBPr6TF0bcnycbiNkewQSollkYtC7RHN5aAvz/uchWu8xVW6Z3gmQkrc3V5F2H\n907K3YCbYkk/fYtQrq4GY3cD7Vpw+n/hUHz1eESFEKyjaPPvnHs3yz+fQRBHsiBPNXKx+x28lw7z\nVEBPEvgbT8//2Umr8sJorl2DfjZLLHeC2pK2GCYwXASsiQeEeuLKYJv/V5poOEZh3cPFxizGLQTz\nzZ5uoDfqigN3CqY0j73CClJ8+syqBAp8t1n3tQ3kPuw3J5O3T60MWJCgKf21TkzVZJDuB5aaE9dg\nMVktdHxJrikylS60vZ/m1cjUKNxoiDPI39roeYY9VDvsCpgImNgylVe/WKtDOm3AS0OuxJ5GRo1G\nNv8ueRhL411geYgF7OYc0W5YUJ0lbrOwAjyc9YsUC+ArWb2xx0Zfj5Ul98LogFEge9068IrfVk01\n4BF74+1GCN6ZDkA9YvJrMTJM4w1XheEIqHHW5ZZZOfuEogI+0QfU3t5wHGqyiFaHyA3rIj2RMqi9\nJrt4iTXodxdtEcK0OWmv0tdoRe9qZLGT+VfxqDPJ2/BD5wCpgCjqbvfEr10DscbhFLCpndPpEajg\nqFXTjp0X3OTaC8pi4w6XNaNOQMberDRTn08gf5l0x98UxA9SOMqdZfOC2RlCYz3vmDzlajtSiCfo\nEMYpfjWEX+zmIEojb0GGhfKzBJ7e2+djOCiLdDQSPdmpB7FZULMVeA8LYGATUvixrWMPk7/eyKkI\nbMsMjBUTCeotJhdrmHHd6XqN6auF/SJcsyQbhL22WrYjJe0y+7VI0Z8guJy3kwJkIQ8fm4ygWYlF\nq4b+5/zVkuL0U5PGlZeqZi0tTyITFaDPnU3XM88qvVW8qGg+Q+RBVOoDcMUWTllzM0/4UeLq8U6r\nPTEWJDQ1OeqxQnou04LHCcJMA8PbDA8ZqL8V15Sgc4hMABc89bWy1thlgq5SIaWBQv1Eb58N3hd2\n1/IKZyCkgTCeUgG3DuqZn4T/1Yi5XdrmQonbeNMWaqhqHb35/rPD5Mh2zY6O/NiSa+8vPgE6+UXh\nl02r97SPcgjQu02ECp+8vjdk+EPmOk2pGdfp8TSMWzmPHS4Tzh+VM3VV9heEPghkORjjQ9p5GTsN\n2JTtaqBlcZEqjdK+wd1JqWB3l/Y34NCxWxIEYn+iDJr7/OcgMgPgV6ve8czc/VJQqPajIStDj7CS\nmEvXTvLBFK/NHJUQqymk69rgXEHLT+NPxtVxBx4pCU5p1X15hRGMEOCRjKE0UbKWsJQgKoSqv1JF\ncik5E12gD5D889uqk5FuZaG5JpFnn614/NkBAln2TyvyBdKXtB2C0qbrq0xNl5ScoJMIMaiS7Viz\nK1ni501N7+dbvXPfIiZoSC5PMDN+J8uLoM7Hb0oPVDqRkD/sO1rvYikgYV/C0SGoL5PQwRlXtsGy\nvkjtZvgOaWTsPsVhIqevL5tWypSOt04oaNzY2Z/sR7RakQZBsxJYTCJgXq/4jowxKvqSXfZ/GZYN\nFSP5ubbQ1cYkoG+TSw/oDNFSmeoFVsS/bnl950K3iQWQhVf+Zt/i61tUfbnMeyeyoLkQajS4KmVc\nWiFnoBgzK2LmRW6sYMtYag1y31CzSINt7NL7bgbXxTUaUURxexD9elo2nz8TMBPAaG3I3Y7jzxHm\ntV1y1yFxWVHcNywk2rGNzpPj2kMQx30pMAIIo5x6AYMyOoGGfSk3RgMLEAswqofpRsZ0Z0nuOjeJ\nYaa/GpdEYkXMa9quM7oYt5t/1AlMbbyfy448sX5mkPC3ptbnQ+Cu6eL8HWt0OMB2CdWK+zZLpKom\n8PTtGTo2iux/41ZcOwnYhE6IvftrpkIp2jBSZlZO4piBfdEDJins4Z9uaktvzMUBGMAyE3nQIHHc\njb/flypubye21EW69MKb2xH4FgEjlhov0Pigeo131GJdQPcyJ3pLJ3DB1/TnF9hechMh80fCKB4w\nHoIhIK05r6gRBP8Q/w1AIE5qNfyfnx86N0UviSiu453VsFoTlqRKkcyB6D/uKyiApHfvQPbSmNVB\ndNvsjs5JFqKNeFlwCa7PqpcjQ40JMNHRwR+AzNRWpUsQ1HOLxfYGoDinhwE3qXwFSRFuSMeTbAow\ntcdxtWa4yrm/I8tWRKDgtDocMf73Xswiq5w7ycbVFDSl1PuQT35LMbzNRI3MYn8zoyAUJi/o4wxx\n3EecAOoiT5ypaWTlAkTXUY5/7DK0ZnCk+dVKAMEn0xLQcutge6JTeyUvElQCoEjM0ziLFJN9ehqr\nLF7hnOP/PGE+voVPtIpzE1BEaq3ZfJTdc8eajof7qW6IiBCkfa5d0bLZhWJUVCgk2/jQCcAlkaMG\nbKBqVmzvw85NLaQze3GKS61RQxSUZTHIJriEtMfLNsRkvsiAld3S8cjdFhhf710C4jHyFr/hkDfP\ncPTeRzgAO1Jqw32Jr1qJZ9A3X4lPxOSeVdyhOLjKovWI9pDUEPqDo/EjqtCHdExEdj3f5vPJcsM5\nHM+Sg9GOIKHEkqUJttyu6JvcMT1q+AKdlU5XwWfzRO3K1Bpi2EQaDY18CdU7X/Ww8H37GKtFkjjy\nz/V6Om3uTpp+bGwlyOjwTCoX1CA2deZT/PIjHD/bRDqXVD4lLO3UZLL8M85D8EWnKKbUuS5UkjPY\nTSJnHKt0NfCG3djbulfNX+7GcfqTpt++9G3OCsT1NYPdxlUj230Pux57NjKjflUxb9OohFOQWejX\ngdNjuE8bb/g/b8JnQ8yDUNoPmPdPdo9dxzfskEsP5OSmlo7jI276d93Rpiiji2CUAds3TSFA7MF9\ni0alV+KSgA/QqUWOj0ZDiR5FGSY9dIYyBFeKXirgEwKgfj3S5ZN4wT0Bvlk3nNBJpb8kaisDTKdc\nRX6KSHuItqtQjV39BhX4o0lyF/CtEohX2t6BCwDQtx4lxnuZHAVly485jtbFlM6GKnEqDfNy8Wbo\nxISNl2OdM7vIa7BrI13lJmkJKUEEiQOwfYay9j87xywrsyHQO58KvovEBxmfyjM3hd3ZT5D/WvE1\nFmWlF/gx2QSzCYuljdoU1ifq5+KaiFkzQqyeaz3h1oxtrwP84XylDhqZqHT/EpCsYJg5VsdobHcr\n/R8o0dBbVjv29idhsyfxikXCLJl//NubYRoJld/26Z/U4Ng0xVa5nXV2wndYQTmMLRCZ8AetikXf\nfWi78H4yXs71EoAtgyO5G6WIgiyarMnKtvEiw7CeTAEuuezVYoI16ikCTqq1qOrDqZ8U8FbAlRT1\nDSu9iD21AKyhuv6TinuOsxw5J6lWdt+DS8DprJDJcTRnU0AGuBPfttAdvLLQfUMB8yc54mRQY1Qc\nh0L9z51PphTlHOtbZ22Vsb1W9EwOJX/jC+r8d4m3kDAWQBt18i21ULJIurrvsDELR5weHIPKVzoG\nOliJTAGerhc2gBCGleC9eKxhz6IB62KOzFFVWh9mu58ZpfMSbglLznfxLa/LKmBsjnt05OgkYgmS\n+ttTgn+eyy0wFO3QL0gCasC/2F3vIh6VWm8aDBaoVCbLxXRgWgF92E3l/FaA2jieoHihaYyStSDF\nOp3CckqmZZNaCcTY6L0Jw6h1JRhX6DUojX2Uq+PJDvLsdeCH5vT04ocIhtVWJ4jAuzPayOLZSCbE\ncHNZieVs1rICiXAj2JzNfVQ71xGyz4V9WPjpnpz0TXOtBw47U8O6ZWtp+f8J0XNhH2iv52U6uiFo\nzhX8hMWsxSugTLHno9vwk1zFpQ+MNs3puOnsNkOcxYUU83Iq2MxQWve3UaMKv3m+XGcdSdtsHs0Q\ntaINa5FW/pkrUd8lJXpE2cx5Xse6dr249znZtp3ZQxuQMYMI3RRm0kkGtookE1Yssrt9MOR/u9eu\nR7jnp6t8EPX04dBSUkohObJK+N1vQwxRhT+5r6AxlDQgSsz9jhMbAGHMR78oJ0kbwUstE5moSVCS\nhqUEjqNPUZkklA7Y5IOMvTASsDVZWrZF199jW3SOKyeu2qpu3qSTfn1eyG0k3vzdohBM5/auPNje\nt8gxcOMl7vVTcHKArYIULqah88m+U1z6dzCwBiW3Zsextd3KaNB/UuNKquqxUyFxzgQAnwToiBZm\nbDRj6DkJVgvCgvp7/tKRlxBGMsKUvqZFkHv3xS/aEmrIJHMAvFy4nzQB7e6e361DJbznKNrNbW+N\nbewABpwBH3Nvi8mRKNhd0ZLxkm2+/lXLlRcAw4q0Ve9Q/tHbXao+hHPXbrL8jv+bY20KptAOl2TZ\n0HuOQQxeWGHnrQOm3rh3fitQmu+bXs1YQ5XwwIooFViBzt/GQNTNN+/mc2Mg4le7cRvpCtKxVfw2\n7RB1myXM/69j/qTF4eiRVMJPR8tKYLWKCdwFkWnowR0dcjb1yfVVYljZ8iJP0+SK4C6zk/CbqXCx\nFbn2JqLXBLn403yprbYtZvG77oLeKbIkc7jMJo8Yy+gDam19wqigGu67KkaZb5n0yyJwn73yLjA2\nLYBinmLPMZh3g+SfacTZhJyubLhJwS3wqVgNucLrU/18Kj2N2NU4gogQ/ggTgQoysllcXKSwTuiC\ndEm8MAuVPCpD/xCbKQaq3+m7hfL7kHaWd70FTM09wKDtW09U6IQGZQSf6ljWP6yutbNmijdwV1iA\nyd/GZxcYTGHZsLWnhKJyNyI++2XDp+S/Td8ULMzhh5hS0My1wENvZMbfV3wXsU0VEipdYjbbvlgR\n3HnCjbEYhlQljGIONf2/3ceFSbD8flm+v38cOaUQxYqP6JSjlOrjWcUm+sgT4uvD8FfHWKnWz0Gk\nEBl/uVDTA6xeDCNAt5AlYinV5rQt1jCzXIr+eCNv0W3pxdHwgBJsW3D6k7yyv9iToKz/2tJkM+rx\ntxg/madBtL/egyAcVxS7G2zDHWza6hj+7cWlP2V5JF7Sbwg+GEB5MCy2/flPR5Ko0lD6Nv/OMZmO\nr8klvVjoOGO2LZlpeOogFL46e3uekX1rdXVWatDyr/CJDLGlMjGYFMV9BlKl+/dYxLkJRKtWfFc4\nYXEU2jYOrolgVM5qtrEQ/S0Lr7KEJbHSVtNCirc1GM2SenfWbuEF1XZ5lMPE7SyLl6hgwsSlYhQ0\nvPNd/+Zf56vMDqzU3fmRpOU5izNOPfgxTynKu83+xJedMAlK3pPMAWGXbLFqOFr7ta4sk2gCDSYm\n9KDac4h6svLJVCJIfwjOJaWCVDE814xd6whKu/QumnPfx/ToVXt2GgzqNOw9FJewjgjWcpss8tSc\nxIaeMKdJz6/J4fxYipLpMT1ybZzm9uq1cTFwd3obl+NYXG0LU2WqAoQNLSse4nsUbY9o6BbFEb/d\naLUwtUguw4BYaBO2fwJeqrWYdNeLI6Ng91fACDgzjaT83wBpIeqc+Pqb1ovTZfvQcHD5G/rOuxAm\nt7DedDuAbiXmKyKZI8MujP3ZaA/nvHmxlNt01K4cSPUesW5lph+BjakLUg7XDah5Umvt+wtBRC/m\n11AkNPrGHc16MZSkQ5CurvBpW1j+TMyC0odq44AQsAKhRSVhCNW9OoFuZ6Pu91fwjxMTwJmpfFGl\ndCRyhDflybNRZttD9BHr2y2dSxPrlCOEZ0SZIOXQU1ESEzWeqPxjfCIxq39v1dWRrV1hp+iGevWl\njDA8/abdXdb1cqSNnzFrbii+WOCyRkDK0lh590S8YvhjmpPWqn8jzUYGdZqgR9UGZGeYoNVypvmt\n+OTv7vCAW3oGMb/R+GlW6fwjBc6atexYYHhx3qIbWFj8O24D4w2Rif1FQVTsH5834zcNsdMXUN7d\nkpnjPZbDjGXIXHjKba2849ICxkiX3TzuRc+KOYXHMXDaJv/QohjNW/+bRlfazbREpjvKr3TZpTp2\ndSy6YNYYY+GYS2gsM5EDD+3p4BliTOwkvpjYdzKIOtgISpAtMfzWrxikmObRwk0HVfm/n3OKy59O\nd0XjjKUuEDYq5nLn5/WIfPUDsM1udd9AMce08Hmelb5+o/Hbs0VSmKxuojBdiw4uKXvwXBeVfqh+\n0FWzyF9D3+1JlgMgOWBrwb9bbp4f/m2TMvCmTr+OW9A44yQUTK3/+1eVrNDk6ebMzsxXMFss/vbV\n6SVYKgxRXKHlzER6SQUZmDagt+96aVuC8jfxKsqeh1SMyztQSB//ylLCAnhmRqaDOW2VECUAp8BA\nXUZnG+iwM+UUVYddG/ojUWKAKr3GOItHsj1LFeavi+86yG4JXsIMvztAshnn3FO71FoGZuGuSKHd\nAyGhphBHTfzxSusL3zl2cDQzAmjy1ohLrDA1Lz7WMdN5mL0Ch1Zp31wv/6or5H0PBcd2jW20nm7N\n8EeUIlrylUpqG51KbhxCbcDT4JZ7qG3Ei6qnLpHPurt+1hXsbMmFlJ6/X6l9Os/WszWkv4hIW+pH\ndEDUJIuWYlRtc3Gk367WdJTiLqmHT119RdB3RpTsEzh0PMAUCuJQPHw2ZpnRkgd99O3ZF5UANsei\nwrQddia19aqodTkgvYRaFVMoakzNtSXayyg2dT5E8836EX1TI3amHiAHHenb1z+Bnt0PWNkL3Rhs\n/Sr3r4e0zv2ukRzXku9ms+7Fv4qep8Y3MmQ/I8zpMa2I9HGaWFMy4WLWfE1HknH5cdbibM+fe1hO\nN8VHHXKCViSGglsa7dafqFYO9GjhhP9Fga3bndEDUcv32SVD/7BofdM8QQBFit3+gqboCKThPn85\nNfcAMGIit+YlOjOLbDXqUXmx352zrAHFKSZW+CqbZEpa9DpenPaU5nJa849eBw2TSt77DLcuGGiw\nr3/V1SgS5sh3H3zxp4MiiWY223H/ksgQ2i1L5ZtUONYnc5tl/4kaT+WTjbobyoQkwOBPssG4jIaa\nu1Al/YLyr49oRpFeDIijZpEXBbOtwvYVPQvUgxd0a2xcHr2fkyu5B8u+P7Y/3VwBuQ+JzzKNIg/t\nL5ms+hnxn7U/GoK5rkUPGbylSXFz/UFxkqt6+/mgDd13wn3jGVecC+k42A6E5lbYrpQ/ZTd6Wq6c\ngOO/nLp+fqLZlkLeGJQ+PuPCM2mqJN90qIiKRN/0M36jGitcB1OPPCSkYGMTzQrq1niKq5Nj/Ftr\nIVeZL4oNiNzE0n/+04yiVqj7o4YwHKbN1BM7/HhdEpFjqh09QIy1FnSKXl6/N/mki+rJpjoVSQrt\nzWQviC0Lq6lTgYc7JVhWSomhbapbIXTq8B6kond51zpIZF7n057caSRRJIX6LH8pKez9EzCnzTeX\n/IUVMuyW8TASjc0k3s+XLVK/D+9zOll9ExGHKfT89IQEdyLE+Wcb6G0I6T9/ntuMJe9yAsJrVlJr\nHXqUhplMRIwH9BF+aoDe1U0MwzJTEXEIru9G3YizqGQusYqMIB3x9sG04xG45tSc4eIg/XGOy8pW\nopvWnxy3bXPmxpwsPi9Zj4/IgTe9Uw0/uHZaGuH/eW0fX10SHon4A2DmK6+Lh8TbzcUYzs6j4FXC\nhHDpXcQKbJKwjVgLX/PBPQbNv8C4XSs4He0MSigV2hrEvZ9b9Ccgr7ZTn6p48ooFsgENlrFYQF6V\n5En05e+qNJvPLaOVrzyaqi+JJXu0yzRCa9/rc3Ibwhs6mQ2caLVP/5QfdZ04OgmjHpqaj0R/e6oe\nJLtJlgjg6IW9F86ZHNb0/n0PRsQ6eCghKPGXTkhjC1LpUCglcJpEFSWoU8utwRF3d5t9ymR4uH8e\nxl1b76MrzBgwzWASuODkGNzlsi3rvAtWvxIg3rBaTVOTEPlnqJnx1tjSTxDmxmfpxs7Uone5QyWm\nu20+CcewAeSid85H589tjQha5pAvS6/NNDkceROhBeXufhW4OS+BzEBdLm/Ijflriz5s92YU7f7p\nfnbWN/fwYwpIlVtYJG6dZZixO/kOPWintkN05Ij2ozVll2b6DnE4jR79l6/VtXZiD/i9U6QKrFVn\nKxrFSdbdD6DqAQ2saR5Zpzpa9OEclGSMy5vyR4ouMJP5UhhYIbG2KKqYkeODdbnZsD/dxpfbZddf\nas2+nxw2Wxx/JvIRQdGeY1hF+6WHv2YGsoJ96HuDPQDDR6IyUpnzS43br6tshfA5aXMibtLnmuIG\nb2x3wz8VD43Pc689qG4uOCk/kZHT+fR0qmDFbfFGn/9jJxJuGmH3kFmHEPX2l/ftmonRCHFtR7OM\nVDBK0Yu0nIliqY02l2bMVX5u6q2MM3OObcrbq3vhQRgHom+D77re50LPZxWCjPKYFknemXUu0GZi\na0434Mb5eLE+K2xtcJyHtdHWu/6nX5zcloDiDFKa1LL78o9Wya7LinmkMAa+GXiaGD7oB+mD95QG\nKfOeNU+yFoXRu00MpBMQ/RKLeKzpavE0JYky5gXC9QK3DT7zIv0x+D4XxTxdRvL5ZN02EsL5xNN5\nq09BtAkJcITc5DkG9QHDhqgWQbEJZkKK5i853XGx3RWZZ67FXiX1YtbF8fnlicPmDRb+TwHO+1v8\ngcSsPnJpjJ4wSK9m3cW3fq7yLE+gNz1M39Yg0yKX0QmjBjlEBb/e3zcwbt8grnXTL7fHQZqDtv5Z\nmWF2YaW+nPsoXQBflGDpy3ZVxYEVbRo737X6tTTtzHiYb+YymPorGL7uMIK6JxZMvepXB4qQfUXQ\nInj6mGEzb5qsjsL2Jcfdbq9F1+TuAwBWOaNu9emT45HHwOYgd3GKf7XS43eyLvg/yU+rgF/FRaZK\nriOqG6Ngr/d20fWQKGL9Azr+5rRgitZrPE8/FFvtMeCbBgy6cVUfqlpqeRuJRl15f1nONoS31AxB\niScvYhcvRg8AWis0awXGb02WCT8UIws9bz4bl00Q3BItdbgw6OrD+4yUIvRbqqEicg4hbyK8P8an\nWVxP2mIuZ85OCEtRfUz41GBG57Z7cbJtUtjXHDd6bRzxCQPHnZK26Kb+JUBFE8W9BDdmP0Z6oeSM\nlxEmNTWFgJfzD0nAbcBCkxUapRB1d299NxOV5LOSjsnrZpmObj6kun/h/kiVKcb8A4vaFbeF4Z1k\nPL3/feK9pLPHAkyQMdnFMILuj80gqfpfC23yNkqvddosBV//iJZiBUHbofJ9scnkh9XUNkskkvDq\nFxNsVwY6whyxEmFd2pnMbBRwBJWDYuwxdbIq2jhlxxlPO8i636rO/SBC+1L7wHvZZci1+efTtmlS\nIBtdvt9jXfxpIrFiMWukKk4N9VmA5sURNNmFsYsxYZglwjRfeNtxA1WWnziNrp9t24vSJEjSMIG0\nUrIW/IXapNKHJbZnII5BlMHkMyIdoGwTUcD6dGj+p4Ld7KGLdYzzJN6fgpJsbJAsIdzJEwTn/3ba\nyX9i/YqkgMNYAMdSZpiLur8Cix7uSZAhrq7tvq7R9Qnz+/jitRXbigtfU0FmexeRHwRCViA7+mW4\nJvjm0a8ePZp2P12uwW5YGOHfO8jojnuQNsomj0yXQj72HxmS8l2NajXwBNYTdmABU7Nfra525yFL\nmb6HJslaM/4qWFSbWj7ZAJLgSwbgMfxhMnc6UoLJPWIBLrblrfuiMYHZh3G+bWFl1R8Y4pUIDM3+\nM5DsRtMV7883OBrw1hIwwzK+AXMgh4Tqnnob5dbA/8RDBzax4vzLV0ZlFlOkNtlIQFGsxR8hWH3h\nE3vB6jdzvztZWY6sFeVC2uia1QIvS6ZJGsG56JCLXfxvtgXCLxP5bezZhUAZD+N/YoR4Z9uNcCaI\n3py29Mg0uYAfo1uu1exWkpWE1C3fpnqzNKHukcmKMa0sXEz0yuSvNWzO8BT49hTWDPairj9FP0ga\n3NVJ8IjOhRJ4eWg/iGYVG/bjftY++MgmhSqNHcpiyM6BSGlpQ7z8NK5ae1W4nbRXGIX5H9/mGyq/\nuGb7hChbhXRdj1MdCTYoO6deAuNXjK/g8xARMjLqX9rm/C7KFV6GLUNup4sVfJ4BHrG0kfTt6AX+\nZP8u3lGcbZFVphE7hDesh6itNq87qNDdU1eLq6kTrSkukaNS2MWcmNGknc47KwklFN15Iadt5sQj\npasOB5yOfKTnF6LGo24EbhlcaliLTtq2Amh20yY6QZuL4UhLdTpg2zSM0e/c3kry583qz45pDZIG\nlRfRMzirV6ZYWInw7e39IIYa6Kc0UcOD/Si6GjNmiL0bLaqmncrljex1AnNtcSntEuXZUhHE5le2\nM8IkMI+vW45yev1dS0suh9Acd7QtG08IkNdDR+3D0efQDt6WooW+GtxDtZ3io56gJP5spVv2bbhW\nYit6mfmgdqLtiepIhDxdMawr5q0vXxvbf6lWTgc3rt69smeElEHpKQ8b6Fe+24UK2v1QFgtohueZ\nEvdxQCzzH4QUxsYDtf5pO6vBonfemJA90m4vKDgTQ8KPj/+mrktrXayHz4GA169mn0cQJ6cpiQtG\nR4JRgp1sV9u6UDVYWmWcGbP17lEMk6Z/sXQfwO5MMJ7BquB9whCA02Rbn+/vMcEn+dy1R6ArZ+ag\nG9WQrSyUQLCxwwGvYbYS7K48VQEBopBiVwNReF/Uu0FLwp6KNlUVRHz+crTCGdcAx56wR6RM9hqB\ngTtqiN7MzgWCRyER4+b1lRQWmZ0Q6U+/vViKHqJoqMkXeFX6HH7UVDt3/1WKgpsGSU4yJzyhR1uH\nptpdIiKijZZyqvruAXmmdZb/dteypouDF0W9Q2GM706SNUIN1dAE39rgTIskXxn7S+dGxKbRTMwW\ng7uwLllmWubEyUs7GhYM2u5SxR5xfPlpfTj/9RiSGCUk5PXj50dAh2OyrA7Tj1K3MNJ6us8katvD\nqtgTT4MlJuthUFCW81C3U9AkpFHaw6W0ivGS5Xh0+viHPOChM3Yo+hT3JUaUP6s4uCBiOCbao7tT\nydPk5yY+jCUf/iPZl7HpaFCF0axrcifLPQlSUrQo5S5NA0vpku8YruvZnOgS7vOlR3JgUjdhbrPf\n0kO+OOTvjF9TfC9e/ND0ZOqMM7OJThbfFFOL1UXQuk9YLxompZwAG97Yw0aRO7NTT54YIQyj2RGb\nkVwBfg/OVR/7u+I+QFvfBKfVlBL3VjonNC6AlYttNdzVCSUmHd+LJ5E84PzIdSU+oaEEEJH3Yymu\nvGwYrXJ9dbPEVp2kt4kIIO/uvghdjEpXFBLl82HKIIVi66HLbfLCVPkH56akGwREtnhBqRjLJMbs\nvs0RkgecsT4Kmh9rOkBxcRN5z5meamLGkicpbJODovMdS509cIyLsdDbP2oP3iyjEG48GIMRpUME\nUjDIbBtZM4L19N6h4zqRWFE74sTzPNE7+ELN5qi69XLwWv5INN9jRKxPM/NFKfWMbWZMWHqCx6oa\nWtWB6VRVjDAI6xEA+TILBr+7n2kHUDNLFZdMalc5dnq2W9TkBo0xJBtW+QimfvGBUYRSY2szTJQ3\nebhlBysIODqHNcwhd3+6ODOr5H87m6PLNoYSYz2izEosmaUkPKH0M7ih90kVLSdUOBmlQgJmyB1H\nil/yp3F8r731/udJv2/uHtn+UHnlnV68B7MpPhoJMkK10IxSRYiZp+Guav4RGK2G81dEVNzY9Y0u\nW4I5W8IqI+z5BgPxbv0L2ZwqZktalJ30tEAktJ7KDvvgqUjaJAtqdTNRojAieodZ/UiEW+uihggG\nM+kiZUy0WvS3TidSVlxTqOZl9vROukLIFlhCi91NpI8lp4Tey46WZYqvkzSfUsBkHuS1xD25YBKG\nu6u6RqQqSqFlIDE/QyQTfUjrPXXixBaAsZbE372wC3LevDXLlPiGolmF51vc8u8Pn3ivR66MhAqk\nQIBf3wg+TXOBoqg3It8U784q51psBuIc0zFTgjTBgGSUD2LB4+dekDz/VZz0avO6SqmIIfjE6aIj\nSCWHWrSYVIgZiS/iAQ5/tv+THTOWCHMNC+Yu6S8XMKa51JRFu88twJG3/vSmnYubvrQh/v1LIgxx\nxnHetebzIcXTwplSddar4DdBu08DkRMRwfHz6lIKs3eJ91snHbLdAXyQYJF4OSIq4To2y10rRNzP\nTH0qyku7uMlvgEm1p5xqX4AB5VxUUyyZQz4doRmZ2/tkSMZcPxxzkYQFlqrgrEuJ9pJt1qzpfoBj\nL4hMFykKzDLIplC0ku3Dpe1rpV+T7xBSGqki4NQnDcm5O8xPv4CKSi6EBfdgVc8IDbfIh9S9+BQi\nH0Rr2VVQDgW2mgf+0Mop5p3Z/WXckC2GFGOxAGkHaj5FXUSDynyWGNne7jpZfDVvIaQI1tEDKFN7\nv44h8xkhz41qc4VCfJSG2PFaSFJDM+1K33jtWB/CPEyWMzNsNJ51XlJMkkUlTwUh/gkjPNQkE33c\nds1vjoRw0NWxyPdBVHwAnpw0SuWgARYIycYta6Pj8S1OvPkXjWQZw67GMemP83XJrATiS6ws1h5e\nSY99pRAVIa0YWlswvxYOe34SC/SuzvSciFganzxWvzy5fodfCoEfZ99gdg6n5EHqjPbWz8eJm/0+\nDXBhj+VHNuhjtsqYVYyooqxC8qOvS9HakveX3y2ANFiIKye3t5XP48W2+zj61i5Ceo5UKw2qU9fx\nq+zrA0RNZj9Ydwh9vzKOKVGJOj7CCaY3duhwhIY+CmGV8DoMMY0G4IWrbXgqWKhOxuYWFrfPjenl\nSBMUItyiTQvvTyv5/jyOk2CyTrBQGgiSN62x/k6ufWjtqdV6ZPXQI4soaqxFuX0RfHvQHx0YmbEG\nKSmvcfXq0UkRhEqIaUUXGHM9gaf/GD6L4sRwmUEtuWKoqh5XkGbqKP/BQESK+CQjpDbl8QWo4Epm\nQngE+gxx8kVqLB35nJk+qlNDX2XVGJisz3RN+5E2vI2yakV3KP5K+EjUd8KNeakWalV1Dcliv51C\ny/mqhlj44AftAlWTEcVfZV7Y6LUc+3s909lnwZpU2Js11sF/vhD733VYMOlzfiyNjQDAxkJTmAOk\n13lXikyWym3iw3e2hDNWrHht//5teteQuhI4O2I28n3SAta0D/fiC50tQkow19A5pVO5nuEhEoV7\n9rPwC5aWQhUPHxENLLsHdYVaU89W8im4ZhyduwMctMYzugf0CRHbf0TZRmZ+hFVu3SV0eSL7V5cA\nWwt/yJRVbUTikbY6skr+K8jVQQD4/DV8JgQDnWxGLdJxDiBf9BDFckT2RtxT29VFr5dMtNKMx92d\nUj4cv8UsXgxftPGbByoRnhuYtTkRts/TMYHga2J8VTj4UxuPXqVG6TWyfwTDPUmeUPTDFcKqHxBD\n/vq+hhjTB7bP5qEobC7PaUqIssBLLTZ9cFlt3r1uwrvkjsBSP0SjqgaLQJXQtUkqEhbsVX7acTCa\nltY6zE9XBwPProeF7pnBfBHCz38irUDnoYjY5SHOFXd2/ftycfGKUDJaR5Y/kCuqfSiGhSxvDFAw\n53Lv3f7/2GWVO93t0+kHtwYWsNtl5T3mjm4stTYaKj2O2XwtdYwD0sIT8Di0dgPRiMnD2+NkuI01\noLKfoQ8u8tNeRGNfK9qyBDyzSbxQp4RkhbfSIfndfsRJQW0unqGjCDGjk8DJWZzoU7Q2JbA3FgvV\nwWthO5sVHhEU2oASv8LJ5IaDmmiIdzn12NmrPoG1N5gOuWXQPlFNMKApG+CTjj9BAUGeN55E0tJM\n2b6JtHp/hjqwsYoURhuQ9sUaP1QRGef1XgzoXUrC4zXVXR0vo50HdlBkGwvxP9FX27sW+O9Y0kJr\npMhhacSkZFcTsutNBsy30LXWY/oelGaUAP8woSJKcfyqwUYAijhBg1Hzh+0Q1zz96kocKsTFMazA\nDLu5VKyKc8z149fIvYC/jdfn0cOq/hhGNSd35TKbcSIrAVcKp2ksCCPOWo54b9RnQi5BRxpRc8bW\nren9KRHNnQVFacVUVSWgeZ8Vr6KrG1Z7J8PCVgi0oI6b47tMgs0h5uAr5YCIFj3fqDZ5Fub2gBCS\nNGknbpoZFjonjLrBrXMs2V/G0ieSDchNc+OABNM1GS2FfzOUqRnIoo5u5RLyIeiG11YzItlctPSO\noKTZoO2dZzGukeoTaD1ICsknAKUXCHlsO1V5RaLqwDkROIKitwMYYII5QSDFmLynIWEt3gkzUtXN\nf6ADQfftWzOTuFUEGd89U00HCGSGLvNNbEZqQ1gf7PsTwSFYgjcVyfM/kljxrX0chPgdb5c8jGUE\nTWR4J4hpJ1iDZoMIOxXV1qAMuNgrUuBLmr9sw2fGYF8VLHQHMjT4ZCIZibmrf/caSaIMlMdtze+o\nAVyDQmrUSZGO3zjF2MVX7GHQLAqLJjSJ5dVHBBk/9Q4OFA3Ygpy+lYxRCyUMewH/vUcee+CO+52Z\n6saEyn0UDuWuf1LKf8U5xIUn26qYVgrHY9ThTsxv5UktFigfOvamnq3bH0rqpEqzBIDbHQGkrauR\nZM9XhKnNh0GcKqopBDnltk2wLfaF88njao8/6v0SJmfsYvwlIBP4Dqsa7G6lFeKw+ze/BQKMRE4u\nu7HiFe8Ns3i9BniUhLjgVdYk5kY3AqMOun09n48+jOuY4+vyHPhjve1eqxr5FRxpr6/K9OZAlE5c\nQnObgDcAO//nfc6Z+NmOaYpt8iN7mXdctH3HDoF4tHZWaVuzJHVZrbUtLrXz4oos01SwYMZRZn0y\nfRmwxO2XEte+TtKAfr6cQN70r8yGN8p1ilyyX/PTCJqgjxZiYLZ7gnnOH4Adr2gGLy3Ma10+2tVg\n6yyRPpwkCRe+K2lIqjxKky4C2wE6KfTobwbyKBUto/x3AhmCyzWooq1rYVXlAshgTFSBFCGD/D44\nOwRZmQOqwfe72A/+KkqDub01SaEpdcdMIKDoOQ97RKmOiiUgsMUY+5pqNvYzfi8lBeHX7qDCAv6b\n/qtPpMEf4x5Ok7qSnSHRXpFu5jCi6iarEx936vlvWo3mmuYuG7c5smdyCkNL3c3qzWLbHw5T+WwY\nW4AaxuFhcWxoG74GwaVi7/eln0UiNVhLNVO1C48Yz+zn296N0OtjDbE9bwaP+q9AzKfnsSr0tAWu\nhTPQduAGmggVMhEr3lAqHdnOXqFQp6Qkmhk3CKN9cVVXV+XO3LqpSm/ZIuzk1Pg83Q2T3CkVSTow\ndx09uPmLaWWxVRP4f7M9YgyFbKcrMs2HRd8axIO2QWOCAmB4pswDetiRd0LPEkdIw/f1m+/Hehu8\nyES2A8lzptKMt2K/1qM9SA2Y9lYi8QweUXVkillVoOFZi4z+l0Rnzj+qRj2eeymwGGtGLJRoKClj\ng5gHnPShaepxL1KjhdD8ZOBlekepgRTZytwsVLaG70FwRJuyqKGdq0pxbMMCPqLNxdRIQQzoZ+Oc\na7+drdqWF1YRARLuQDKHN2wocd6QiD9zgoGLce/KX/NXcr2awrlqj8HSRKF0TkqpM2TQniKOJmJG\nnH45js7kF13VJiK+T8bvxXHiYctmG5ucw29N2fVMzRrMsKT7STT1CTAmq0e/vlC1ISuBoQeNY2Gr\nsxGooOIgpNNIyOYvI7eRXoPR/+Lkg6adDGFn0C066Fo0zstQBhrCrCwO7lZsu3qJLCWn5FWha1xf\nlC9rDo31Yse3DpxbY8PDoRRfYVlQ/hDQLvTSabtTF0Lc0BwQ7K/8f4KiTEzeLglz4uJIHYiZWdDI\npFXvn5pfQLoclU3xU/gs+L9GBjURWVSps0UWztwqUGv+iNUHzmJNdS39F4D//HmxZQ5RypgEp9jj\n12jg55It6bB6GIgVlWqUQVNiy2E8KVo7XmFPzb9/DL+pmrc3JwEXD6MqWCXR0m6NDeMrQcprrCI7\nuhfyjED8MqDYYopXkJtZHC1+21TfRcj4Hp+PxkFUmKFDysX+9mxDEK90MLK8zqXBdkznCxVl6gP3\nExj/UVpugbVlLaVpC8Y/YYWBaoGt7hkHUxV2UZBF22l9l9ng/zxwD1guaAKD5pq/B5jeGQ+waTl5\ndSFk/Mp8y1IaDO5oma7SEujTuEWRj9YAouVAsaYsfQTHY8H+9Ia4aTAc9pkaB6g8Fbw9+w65mpZS\nmNr35F9220wyNqbMqySLt2+KwbMzDw/T/Eb1CD7LCetakGCk6gIOYIPfAN0tTQTFgEvq3W9N17Uj\nY70Cek2vUlkf/clX1SHXsyXqw+CP8pb/v8x/srXErtSG8kAwQ2LOir5wjQb+zQ+ekH1ankDNTr5K\nMm9dBP/zFVEKuwzio2LKTxQ7lQgAezzibXGpoBmOpMZLPY/jRSDCz38XlKnlt5n8sHF43lXRegHh\nhXOkG0LeZRJEcweEanmbd/tp/qblxNLFXzjXA4aPTogDw986MJI0wLfQUDIxqHTKZH2JrZkKbdu4\nf5McTbfNr+DAPuQs3Ia42JbKCuGavOZqaaBA/LAEW1dDsiThoO7Sw7910O2GcJOSzLMANZVtDvPS\nRRns+YGZZzrhWif/vq2Cz1jEXcDpFTje7T76XVXp+L/p+PnemWTRiH97keY3uBwvCChKOy2h7Ngg\nsS1mdcNTFvzVYfrbEWOIwDzYwmCG6vD0xrefXccaE5kwZkvesMBlZcy8+Ivz7F5tY4ka6P8TPZgI\nWlvb+EVIpo7OE96B+PQiSlyfBmRZs5LOasv9ZpUTdOZC87xjO1nGXppvPuR48roSRPQTrlrN8VbP\nmYTuC8nHxOjsXzPBTkwwKwXsipM06sBzJfMAYbtkMNplBJ/IrLXwhkN8hF8gOV/JeSvjet5yz0XW\nU9n6wE96SnB1K4N6FdF2ZCN6RwJUJcIaBzYHFu4bseydR9kDrbFRlZamlmNzsp0Y2sULCsg3LE+R\nfI/36FdcdO0KbLxmGHhpI+T/c4R58RGBpuWTHCKTJlnhBBuTu/jXIgQrKX3KYaDZh6rJuVPNUyu0\nkpzU565ymiYavi8YWTEsE9fdpqJtTjBfS4/8Dgreuyd1tKjPjZtHZmnocpmmZZ3V3t1/ppjtP32B\nlQ5ezHhPuosz51a1nMY35fgGbkzZnReVVEwhYI3SZsDwFi3tWDyf7k29ujlDf37xnGUWejv+v8J8\n9Sie0mwYSV0imkM/hlaxmwR9DE4dVJI1DI+YxPiLpq4D+YP8NGW87BB9TT2pQHiSPDVo5uEBFyH8\nFTxCyxKSYWp21Xsl4uHSAOJUqzduG7vK8wHmxf00TXPr6IWAsMPf3I+kV+yugDDE2FjWEHmptT5r\nA9V/6e3sVGn0EIvw1ygP9enclWcUHmmpNVnxIWguvI380B/QVm72vrWcTzUw4TBhdyX5+VWWsOo2\nYRKDdF2ok4MKUnG0xwvmLeA1wIh08ev94nU8fnFag326oKCki2/KeehhU1ZOfW8Vyal5P+T3c7Dn\noc5T7Py4XeuJ9/mj+eWsDdrjviijdmSDeutgdnTRCoexD5hRCmIjq7oNfSTV0w3kLXa1EdJTg3r+\ngWzL2Z9+PTotWrI5zTZKyuiqwxkqUeisnQIUIkOnb8fzZxhjXobWCanymU6QStxDgC+XQspT+alq\nzKMWKkKdaIQ9U8SzcyvI08Nkw1o+1eUt15AdP7YowC82kmr8JCohjkqkanqgU2iabxQE3gZ2EIH/\n1v8G4Hri0E8cpRTb47IneEIt61EPelTent/NVvyuNavqwyBMzpJ8lR1rrmgLg/PXcOMIR9+r/9nv\ny0wYB9lV8tVKIzNheHjCBaGA6DfTcDVZvxez/S9dFBbzg4pSQUGSLzlUWwp1L+S5fLzskNjDlufy\nW3EBWMCVyqT8loptQGMwRh+Z65OEkWdmmacif9pSS/AmA+UFtauVRVgpgf3H2bLwyWdGdfhHy//m\n5yMe0gv+S2mEmPZoZ2aBV3y1VceqYsag9n5NC0Iy0g+m9pxdiC1hixMG2Y4eBd/VEGaHuVOO5BIC\nYAjFQDyxV7GLbaS8PZAxTFqXeJ9vRhPdjnsPOjsRS8EVEk7ybAH+P0OfUMxos71a6fdpXfpiq3nM\nDF1NU/GhpYXLjy8WJvvUIqCcjpUrG2Cj1kIHjzIGS6qAOOIaJGWHyHUx12JitcG8MquDo6lJxUU2\n/gdUMVSSoTuSMb1s5E42TxaP7jh8S26kgi+twywcxZv1stnRTapU2FY0ngbJgBEoT25U+Bg2Zi18\nSuwluiGuuIQ1vtpoBPl4U8JuaXBYQMfyc07nNi4dWPMMU8Z99KcJ31YZ/cV9tRbRYQ4Odq8SQtMb\nq7HtSan07elooOcfC1aLWBj3pikkDE71KcbkB368ApAlllD2bJvj2UbH8fz9gCQ4f1luBDU3Xb3z\n4cQgLAYNL0WTfoMp/lMe3B1OkH7a+MaA/1XeQS/6XcRF4QzxzP+rLlIZZmmUqSyYGr7LVIg+0bNo\nc9vu+NH8QhGid42YvahNhqRKWA7suHQKP0gcSll0Xcsyg4zLAZfENYmU0fW93RIwiXsRSXhVrZAY\ne/y3+oqmCzYCXXUbKtCjbdcYUZtWZM0mJj6Bo/gslF2jFpnXqFoWHJC4ERaITbNmDbCp4NTiUcXa\no0Q5slf/Luacmtm0ab1Q//Em9UGJqGDsMk8MeSHODZrG5aQIOdPyyI3SGQUdZjBbg47IpMjASyLJ\nTIahPwMz/M7cu5clwtykMbXakYTWbeYFO3VDAFkhIBMdCTh5u0Dk5cpJlKQk5O1Xwzmi80LMq2DT\nPcBcJt6GF6ghZ7nf1/iJCa5ebhhPJXK00rk1SSDaMXOj7Rtx/2nM3uSpKgDjy4WuTqZPAG7x31q2\n56G8lM1c4S5rNYB6X3Wzcms6W3JhxYpmoP4x/BGyNsPFa6+jAH/gEa9xYhPF7mqDdSmKyOSQYs3H\nBu+3xn8kAgahlTpYWSdEb4XLQKQ5fXuyBiqHqVJcaUoAaH3tebsqp71tJNHN/ONAzzbZvML+D25N\nPqTH7s3InYyKMvSEdwYMzEc5KTywPfHdXw0XIx/B+nWHct6Z+yGWlbhpMJhEtlEoniydvC/3Ocjk\n+AAUcGo8syvHlKbwTMPzZLVYJ7eziUL/h/DiLTbjkG0xvQUcjzVbc/CJkghiUXNNOkUKvKM/5KNI\nQxyhB23TD6HFFbyKgwztGZq0eWrpF6EwG9flWAFrpJyIpAlYrvXUfmlqRi63My/4WoSaj3xSovA2\nHhKKRuZkDvW4eLKALDPwCddpJ+rWGOteN3fP/g4bVY3bKIm4nSKnTL5QwnfP+Q0ZB931PGhVWOBo\n76AhppLNQznNfSFtX5kPtjDHEt2pqhYXlL10z5VycsYf07C8aTugP6a0pljlT1AdcSGuf50MZI4T\nGgHRTyZebXSqe7J08+xeU7YGV9MJAJ/cx6Sx2vs0S476m6F6n0ONqtg5pxYAnhgnWPqWvbycmxqE\n6a/Y4IDymxxYHPqUXs6FKL+KjzCIkyha2s5tdvJ5FPWTwUjbRbpdqqR2kx9ki+myOX5sWywj1kXe\n4udauXZz+Yr/Us4j9hjsqhVROS7KGgw81td6ud7/S4iU/jbVbgshA7Il6FwhLNah82pbaRIzJY3l\nxCrDXamS8ajxI3Rc0+C2CmhUicvGm5ZkQt+tvbqbna8IUjLS1oiOsw6w7K0K5q1WavUzXlN9tmoe\nZ2bZSxhz+/Wzk6WHKN7IqzJCv0I6lklNs2YMhsvamXXgR9nkV6rbow4jkdlCQm7EJOfAm+6tsBrV\n6Ozhe7ZwnXdd8TlpWVJcC3P0sGaVYSt2DJ+5F64xm8MI5rwSFZAoOjMxWYYkd+DNzRS++J/3b+gI\nI4rS+C6VAOlZm6lc6ziUTksCShyfL9ss/8xploJVYR0WmPjg5GFz5fqBG2peaFi63U/1uZCYzgDz\nl+rchwBGovyKIbiphYFsTFrLwcb1xzgy2U5UY1NiwpFpA3AhDHeZkJzT6XAsULjXTiqsvDm/OYf5\nIz5462BzXym1rgN4mUAR6Wk3MjoymGxxAT+qMA+rfZN+aWQcFZebjw/gedTXq4NohrGXoccWzVaN\npvmMKfTnB9qT1UGS+3J+LpOtLUgV/HlctY4W0j8cQkxkOoRrLJsRKzt4jECjlIMP/HxTCnv22oBc\nNiw3RPJNRZ5c+rwpHqdohpPy166pwV3OYugW2rtjW/nSffCiQwV6zq0NCLgarGpdkfdudOXZy17k\nCvaEeBynx6U+IYNq/ge/UcD08Yh/ATvAJuB5gn7M47NuC7i/2KM9XCYl4we3vT+8B9JXX6bqpzm+\nVT8HZqKER4VVU4A+hTjpb7okvoWJU5fpupEZTAmQPEKmTE4u79HZJ/6NYFLb9o1jjuMQtUd34Nto\nnatLAJbCo0bq8sFB7m8Y8TdmXrpFiCP3PkXhemRN4jKkcsnoRHiPj9w52hRaVV4w9hzL9AfAAyfo\nzNLPClUxaZMpOBTzk6F8EP7psB7M52dYWYQfNq+mPgPZ5fRxR9cLSiBssIW51Wly90j5OkoEN7R6\nm9rJRt7bxGkv4deYhUsAbmiC5BVBn23hdaJr0+x4EkmxLrOL2+pP5CeJ5e5vcno7d4HS3m+Vqtks\nB6bmtD7c4c2Whs932ls3JBAEKnEHI0YRUlwLTOSkb98d1kUjdsbkxQ/jAtbn0GKG8vY+SG33MLZI\nb6mf8TTBXSE3P53ZcL+JhWP4VA2/7oo6IHTtxFP4nrexD1rJLDOIaxZk2tQH0M6uvymwcmYepVUA\nf0ruONi6cYxkTS77kzVZjZUawtqS4YiaRkHWp20EgnoneLkJPBB58nPHkcUMq/HYB5mOxEgOSv2X\nsNDnl9X5aSkiHUkNs4ff4o1dgQJSniup33MZfolOXlM48jcXfQvVgQ+e5b8T+8acQnrS7gLJ3m32\nkkSwdZqLmi/JuUL8+9rJepv4MMo1ncKL6BAJc6Yel2dYyfWITZzoRquHPqHXCCrBy3MGHZDN1RS6\nWSngstcV0GmLotvG2QH+OfL1t+heN/cQTwVNHG9nyW31C4Gw0x/xxTQ+XCNAvF6u8ChlTPAJTn1F\ncsKJUgNe8FNg0AN/8rmmzn5aAeMHRAH8ASdXyMJIWNC5RxV85XlLQVU3mvs7Megl3SnOwSyt9Ycj\n/RyJYiBPfeUT2nokSDkBd8WFizSLVjYjTnDWY9cibBeWM376bRuXL2KQio2sfnY7Ano9Gw1PgPNd\nrq8VcKon30x8Rfl/TYPFTboSIBpri9bBpJ0D8MgFL8hP34t0VFMJBr8uv96r7j8AuYGtCNviT5aw\nG/SR/WQWNUh9MqLyO94moIge1UjLTEsP0QvIumIxKlyXXXtHbCvmsLAOH1jCqXm0aixX4H2VwIJx\nnNArz8ELNRv+uEFcNIN1vWpbGX/qu13v5OPh3AoTL7RhjyegQ8ZOJFEhTLtm6zjUTiUC0jwZnoQU\nQvhvxngWBPqgrlnRH4ku59EQ9658Q3J2VRY97el0JgV4IemD34nRoVN/u8H79iBlWcukxfn4yJys\nqD0u9V2+hxiYxAg9F4EmZf/MmB+D1/7pbQeXjb+WLC2BUhY+FGoUlcwbdxCDJtl3xMMDjAfeZM1r\nryJgtV9/YIFr3QUaqR2BeqbNyOigV8rZkOdySj4krxTofPxN5QzjHcyoYTsDC+fxVwVwO/swVkbY\n3fYmBt55dax6bST4qoaSW5TLLkrEYO3d5fBJhyI/L/B0dxLM+N1bxE6gq9D3sWtnARthyydm8827\nk8AOlgyr4Wh79U3W7KUzivAhfwFVWwHzSWAjoG56B2GENjMPZg5xfOCpQl9n4w2aN+ozOFAtsHY6\naa9Bw6qVj9uneZI/1ChI739DfKh2RHewZiGAzEp3eGx4imCeJZRVtA3JC4fsYA/yBYhIkzKQaJUB\n++PBbURu3z0HG/jJ21B5Q2l0diEF+ujfo8BG6+BgS78BEgttXjGLTQCgZdN4HgflGgsP9XtWQNrY\n4jcDkqZ5CDhRW9wMpHQjU7Co1M/2bMofj32o5aPHg0xtylwsfT0I/rnxkfN3m0FX7R2flHrXwAN/\ntOsBmJOm9riltyd4eASlsOBVkWhGwwIMNgRWl5f6JmOfVa4npWEhP//er/y3MbQnUfI6YhVrNkIR\nmiFZHQOUJjR4HwXREKF1oT0CPehxCP2rJmxKHc8wlxPrT8auVIp0uMKa5BuoHDAvAbiRuZQQmaHi\nIUW/AQ30jauPhofNWropVN89ONBKLeRtJZOpJMvPR2hBWyccbXd4YgNeJrWAOP4Bclk5RyB54sRW\nUWUmCFUB2lXOLvCMcP3cfB8KpNxAtP4ptSGVFussgbrkuGjHoPOGEX0CyDQVHsciN8BvCTGq4cn+\nh7uqSLnNOtx1Mw8dMl2z1N2AeRj20RUjSqoIZv0Q63jhSH6CgWUfFvqQ/Fkx6wa0lLcNG+M/novF\nc8xcu3mPe7z97g235bpr/EXIwcxMAMZcXtpu5eDl+3sysnbJyDJHsrLaxYThiDt+RzjSoKTo8PPm\n50ryljP8z8x6s16QDkuNsBm9MrH1qAF7aO+h3cb5erdoyGlt9L01VjGZMxCOrBIi7ktRrVwWNp5x\nRWfXTYfJpQEsxhJv4Mm2YMamONNeRny7FJraF4d5X2cu9zVVvrjnRctbFsZmcMaBOwuzF6YdYqIb\n72bssPuL5CkfzINWgcRLzRW0zyj7mlgoePWcJw0C+fqNsFTQo8eOZMT+r68VT5mGlU7rLiXe2F3a\nT3mjTZjZXjSyEXiKTB4Z7AfsQqhRIxVUZc/F3kvhMehOMha8BsICxmNFt6y3sPSWbLZxSsfMmKnk\nrFbpsxmHH88nQbpjRjnGCO48kn5m1WM3OfdCho0PgNBAb2MVVS7NoQv6bXlqX1BYf7xmWpnFtb92\nrkbo68c67iTtKsOJII9Rqb3mll/dyTWW2kExA24JgzEl9TyfplM+gb3g67OVLN01fi1fG8mloejX\n0bEuYGE7biutah7+YWsnz7AG1ijJQXuvvt5sSeMjWW75IbMtidPVCeP8TWIRTx++qw6ET+Fg/GQF\nyOQripPxVIvJTnmK3Itg902jX8xqkFmoI3E3j6n47RvZbOEOIfAU1VxmISgKdbN6qzaUxnbWytZw\nVeXbCPvnqpe0hjS+Mhd4jyM75+lnJib+tQWInlNM0Zsdng+HMh5d1VLgy82xSKl/Vedb71A2JZ2M\nHGUH85xSrCgZp1EN+A47QJ5BsjjqKuUqvoG0k5YTbDy0TX+vvoeaDOyXW1JR9hWTegyfCUnGjkLY\nAJpR4CQw7dj19kj1eGyfGSWlqZ6Z1MLKKHF7i4JRaq0PgSjLGEOe1msVZ6ysUVUk1/3qz10cqLVx\n7Y0athWUcpOh9YHoRy98R90RnTqba7J6HTg4SG5uC8Nle5ESGbgiAHWZ/g3FBo6CY5Wu0+eO8bVG\nNNTimWIfac1bO7EQEvFhOMUNm2oW64BelWFlnd/l4O3LWY98fbCXttVLEBILO7WQtPiQIyOjqmgH\naSMADx5/flIVwTqGyzaFR5TJNglbLS5hQSyQpwtsHttkkBEsLaHmMh3oUb3xVvN0rMPyyZPRLatK\n7vBt7bAFVkA6JbHbXN9Y6xnaWnK4reOQHjjHrG2BBgL4viejOzAC6SF+vsh/B/0MWvQ/t82pKJKK\nR+/A5a+x3Nfhll7w4jknKs/5R6bFF8SbUrKjS1bXFbQRhcMlogxI7GLLmSsVQ+WEJXkZALZ+ga9p\nBK+HAjzu10QyKcKyAF/87/CN9tjagxxAgx/5UIxtKVLN0QZyfic0jMRI3tmaCUDMIII8IvLabJxg\nuj1uqDHSZsb3o8v4uU0NKeROe/B80T7A0nn+PyLLb/1DgcN/O991D5YXRSvVyngvjVAkkvIoMcot\nDEA5gzVpjFlgWxnOgpBT11dO2fFpSX9b9ih4g4LdGI+N7HcEWXnjrh/bZ7QBBuOa5CwiVIj81jPD\nHVbtjohGnikk156SBdydiXcwPRTKbBtEs4fXgmWdSY5XbgY821a1pWpcOeT/NugbcjkG/F7v6QH5\nKns5yWALtzoA3w9rWUpMni6B9BeeXik4XhBJUyGLP+jCZ8eCCj4fmOuywuZc552g9Rq3+H3/k3ur\nBw5+ReHjf73Y89NXIpW1pAUVIjabjBE6tiL8ciIbt5FMHi/JqWVjPEF6qRrsremP17lLeySBROvo\nf4YIU7UHGHBMjUL4biAgcgfgTe6/KsOofZ4iW+7/IXpanppi8bum+kUj+1GgVeSkI+IAlTsLWf2E\nHjEGInlCgw+pU1vWZ2J4JWRlAT+a3aEBh4rsyC8fbPCbbCNQBJlrbaM8SUXxw4Voul/y9WRifpNn\nZdv7pHVV4o378BMAXDiTLtt4K2IPtfX+1BfLFuBOkNa44Pt4qbv7bl719+ZdAlmkky0u75eWqd0Q\nK6svJSsWsHX8rTgRBrAak1gDBjSwzXBz5a+Qy7XyMrq2ylzVu9en7fZH/ih4XFd6JbH28F27HOnc\nZ8+eJJkHRa+0u/X3yPPwEJ3nGERavIQV3CT1ZaDK3Q9JdIZZBj9Zjgazn44tIx6a6JhsvXMQ+aGO\na8iKoEvXSbMuORJq4oCQhXMrcmtLePPI3VrLtmX2Z5ofe0tOF/1oZHHmUJxX0XAsd34w2HvxzZJF\nBSlz76kAuvAuHYUh6OPpri4/HgpXEpHgxO8I9QJIDxaSU8QPaiO0t2JY63y66Tw3qYjXXXkIoSsz\nKw/VSGcVStDXjh3yZMUFTS33c/ie6XjCP/SKk6+ELZZEjulHLhHaCT4gXmxqYQaqAsyPb2wZaxTb\nuIzotJZvzlPEa9S73E02YRr31czTit4nj/Km92OBJIoJwd7Yh+5kIKOtm7EAPEFIHOENrbsfhbdx\nqaROkQkl1qRaz2u/zFk/ibUU7HML5jq5zM/Og/AcguwLc5vLSjd8Erhrad5lM/CADvQgPE0rkbkx\nxKRIC5m2yWke/HbrItxZCgk+fR9G5m96ay+arqaz6duoHw/IFQ4B5qkfeLjXifbtE26AuOVVSnOf\nrcYVn8Z2tBe/rMLRIzPpD2mBQM14W0gbFEba7be7Jsj4Dbn6FTmib6NAZYJIgEuvlsWCvj1PnCOL\nwNZa771dJhZG5lYbtHm94+SsUScpl2C3H7fTEJfPwtGtanqGOjHF8EG+/aN40BXpnh61dJZ3y5k0\nhShV8AgAPUKY1RUYXtKk/gECXSgr+cLJ4ZOMhlSMLuYqaHZCsTHxaL2Mq6leccGQFNFK8wYzsET/\nXWUJINyXcojeyRHaK9e81ZT1YpMx7CWkybfd9pPiVu5QraVyk2Gban+tizqW70frzl9CWk7pB7vw\nBKN78HZb1NWpFkeuOEYSrjZGUGhbMo2EggrEFkrm6f60h5wKb2YC4mjedbe8VIKBw03D5tg6VuhP\nRXEs4+z1Ngt6HbLm/BqZ9fA1NJUp4a7slw9Fae97ykwMl7ut6gNzJ2xHEuq3RmvOJHz7RZDujt0b\nrOsz6F7Ru3FBeKTyi//N6M9siGQ6a3UkRDE4r52Ong3u7u6N8MH5jJMDsGn7FnmxMl+k9pXseYGr\nc/aarANaesqmvdH+Lmz/TUohFOcHRgAwVQAOCK90mB/rZ5bkRpi2izrlqy/UB6CpBVIevNnvOpU9\n25McMY5q7Xh65jT7P3tP71q78Sl4V9felfA0KTzHzaFKq/GfLrPKLoBcKFRs11ivLRbMk7urGC5t\n3XUz+pdxcMDSIlrQ5q3xE3C5iLkLXiYzruOweLxMDOmrerdk3a8L3lCyzHw88KHBVRDNPII1I+/L\neBek6Lrs7lyzEBJMVIl7NXQnKLLMDvpAgqtoKEay6yq4Iof8vuq2sKB/9ag0j2gY7aapNFqxP/tG\nsgcvEEMnO7WHtakxH2HPdGHxhC4RXMFsrfW7P0r5KOlR0EkkJI/OmF4YSqwuA1CuEAWDWGJT9ifE\nsGI2WKw2TRnea1wWMGBqKvr/XiKrIOp0X26RaeCwXYi3Dme8Wz8xv56TrsSv4Eg+XI9tMyVCtNbC\nuveDpSl82qXUuFLkuuO3h4fA9pIttmc6BIk7euT+Qcy3gNXVm7zvya/Jkkni3yJ4kmfhcYM4ZYP/\nXrRdSaCL3GNN7anXK7Z7uT30dz/65vqZ2CdUzv3abLgGTrOQWOuWwEIvpEDXTjWiUDGK3erNWol0\nL22xD3/rUg0KQk4MpZD7D5THxtj6Sj16seGfNLgiWr8yMRB+CZUEE5iQkoZze1M5DNGiYiX6WkaM\nyC9DgvWUrVhs8ZY8RH3NooDRZ8qAUz0/8qrqqK3OFRph3TJWallm0FBpHixfhTUEVxexW8KcAxkb\n/wHsp0lVXxG7NGAjUEWQAQvaWnfmn8UZJiqrPaI65QyL2bhLb91jJX0epRvcsBhXFWZtDxCc0RmV\nvYUc+0UjGMqTTEXomeMsCyR2GBtCJUT8wv+JomMNvB5fDuJnPaE9lArjG3LSoiaRXTpCiTq3vvKK\nBTyOnVxmGm4ZJFcVIbIfwupkPwlqDxBUKHaK6vCCTdB7CyBHJ905kiZ4enk/tSEpN+TEroTg46NW\nlQVah8dLIq5F9r01+Yk8OJJTKPmLgRRQ9a8/L68I4tD2ps8FZYscqvJw41awTjcUv4AZ+MLxyNiy\nucys+f4wR25URgyvg+DkOe2PAiIO1YWh7AeAfXB+7k/u9SBurz9xZBI2AyPdtM8NmoH3kmMU4f5i\nSh650ueyt1h281gatVYeIn6C7fLLwD/ONxws0sQspkm4jikdwpfu15+51xBgeMOdjrG6sSsaw/6K\nha+hV4ncAs5kfqB8QDqTvu6lWuR8ZqzWtlX+oOOoB0e9gJ3UXVZsHFkWCz4QccQjbpfHCeAVB+sp\nGRdINMrTG20YcU0IW7/dU52AgvL8H0AiG2RFD04rDVefP5dY35x/YdZinm5PiwYP4DQyCHofWgpr\nS5IGvH1QfumFMGeyJ/r/gOG5cZo4HubsWj0svo3G7lXc51diq5YzRbayFE29OrW2veRkMJ/RqgOj\nzuOu0bnvzjbU1H+o9AgOXWvS+Z0wQnx5tldjKRYAedREXU1i5TaNo71Dvdn5zWyqmv0Y4h8V0aZK\nxpv0nK4RKzsYAxwolzxewQr22fQtXGnYAGTJpQI0U0g6shh9TxUYmFCJXwt68MPPYkbgndviz+ms\nQZelgxs/e+/cSaNtu2QRw8p3g5QcrnzOThjkObKuSO4At1dxdDoJ5GN9AUOjW2DVln6OkW0NA9V6\nyrbSsxXNR3BEVDDc93CbadWe2dfDz4bgfMnLJjwTu3iNKHesT140eUSDhayga2gymIAp8p1ivlAb\n36RL6vaUzVAuQb2kly9OBkLrPUifiqRl1KgqDbfQyAh9n6xCF5+lmDJup5x0aRrV8WbZlWthv3uZ\nMJFOq2OMCBiy9Cioo6OHT2grdepe/WAW2EUIu+N7iFH68EaYaaWe5DVmLJORjW1njJGu5juvRBnd\nIWKzJ+RwslwkRjCd3qPuz2KLAv4+WKAkG5E9GD17HVr8e8FXpCadMNosBte36TmrfYLrWQp8qvgT\nPlCLc814ZyOV0HIJEGC22zT0KvzbsHSqcCwF3YAYNopdfVB9K4XuYDnn8lZUzhCDVkq0VztDIFBf\n8kErSD6dAJKOHiBN14SUQPd+7F5qR6eK/r6ZxQSUId89rE0gf9qMIzvXz/ygPhoN/qWTLTQWd9MI\nTqqFSfV+IhVzhiJ7SLIcqjDRwxLatUxMi80au/ljMwdk+CMrnsrhWEMN7NmPYcE8ZbswjDLjViQK\nD6szUQPzUEAnC+hmRDoKMco/2HNML/MnnK98YJSftrss1VTxYjSvJ4CWFey1oaLExNRdMhevE45L\nihgjWTa1o1HtKgzg5A5QrPfBceIYBeq9HsQ9QXZfQ6R6HTmN6qPGf83g2EFwFQUoPtlVvz/jWdTM\n2wKMgKDOGoukMAwG2szX+2mjql1K5Q3lbDraub9S80Ue1d1fJsSeroC+4XQrykklOw8cLq3E1dSs\nyYqEUnKSgBSMekRZfjMg0uepUGINgjEln753bxtjGJ55xmKGPkzbbfGSuEvzpBWUAyhDznrj1Dc6\nb8oPEf/xB2hnba7oEF0HyIwbcdvVP5G6EUEkKlBgOOR+Fcb2pG+xG7UYcd9tQB1BipUHkYwtmsxt\nLVpZAiNogaWPAWMzNER7r1746I07LkT1mjuVfc/9fRzsFwdNFtgtQbqGifw3QfWhZaDmjVd3yzy4\nzsErLC3vhPxxT5+ghotTamUJBp+55zocJBpH9iKiCFPwfoLuMOvAyD3fBO9EccYJMqMddujXzEqR\nCsQ6Cwr55TdojRtfeju8ls7WgmLQedQ7ldADSJjvS6A22+jWnWrPZzROakIuwKvHJYr9pQrdVejv\nrXYpLvFGNIjFjBo7lDp7UejP7FZqKr/vQjQ/gqSKrqovPkWOkkP3Wbb1cqT10dYfEZRZm4CEftBT\nBtGquHilqKNTbCpx6D/kj2innSiNSTzO1YOxV1xwmAh8IwVsXX0AwcwMf31X9/42ipwv7rwq0Zks\noD5G52WSWxKPJAlw6mRxJP9DwFEWy1Y7OdyFBOuDzhm2zBEpEWfoulgzMkzPBiEj7fBgfkxf2EpJ\n5bY1t7V6p0z1gecnxZG5IvS4199CeJKlRa2fGov40vqX7H8IBeN71kJrXaDrGk4qRdUeIbNWJ7YZ\niCen6QSaoDyOGUvrcVivZA3KQjDV10m0gGS8oiNPsNopRWSFFxmo32y6pIL+cUdjZ+7VsVRx/Zi+\ncNUefqNyCqFqNapzigSvk4EDIajdAYVIb8jb8FSqjY02kJP4RIDDYHXLpsU8p/bcBYQ33fIGL8py\nBTApDHfvjpqQ+n2Scn825KXiddB1gqsbohr3b63Yiod0VdTXUXBplyUEqv3TTTITuN9W3Ia4RoMt\n6c9LQTMGqjGzIuSwXxwE0C7/ttHQGq77tZjpjCnuE8uf/JdySUKwLkHTGDfby0EB0+uYUdTLBPPy\nVYIUzIMVGGK+h4tdsuj/PPIGby0E9sUOPQL7yKWOGW49wIvV0kj9PQYveASUgM6hrNTlP8HGGn0C\nWHe+FpgCeJVQDvp7Kpm6dIyJd7sOvtv8BxcV7FUPHCR0aXRTQaY+LKoI/ak58HWhU0CpdjyMp3gq\nC2QzyU8jNnhOBINzLtks2CpfIMNiL1AkLQkuMr3cdnedYU72f6OtTfUC+UfQslTREMlyZotbPTWq\nzFz3gkWjKTuLuQGWZygGjB3hzxdctwD4NXtYjsBeDKxzys0o3cnGZ4LUbghgOE6OdQTsVxp4/2sD\nANGFHJkbQE0uEYEKh5CRCrCRJ4DIfe7PVyEzPsLckKYDAWf2uw3zw7XC4Fflj9kSog/qeZ6zhm0g\nJHTV4ySs21Jo33LOGr3gncgREbIoKL7bJgbTQyqfGGMsWD7/1FMBg9kPYiynj3OAqXM0rz2iyeP2\ncObN2LeilH3kc1WL0ZQiJgXmivTou04EK21ak7RZ2zr3OHETJZHdabfUAWIvS7a0+2nBAA4Yuq84\nEkjakFNZAiPvS8gFa/RXJVnKw9mgk+Wq9en8l/MKYxKPjdmseppVY86kn9W5Pk5AsEIB7IwsnmBx\nBlka55jAAVyrveYnurBwiX1rMKxJOOwC11VOWMyFYW/1eyo0nxDmS4VArbuecvYjvJdjfmSxAmRk\n/Uh+SJljpldbNk5oWYYvRPGw/Exxhf25jv2815JwbMEgS8JflETRjVQq4FSdytBswa7ZPkZ+Md5V\nxSi0IPHONbCrkWMhY0imjPX9W8v+uUwAXCeEiKVDkxpprBah4L45QpKKf/uV4uyGnp22V1/gcOsJ\nb6pOY/27OhEo7476+yOXvwaorUowz0e5tr1La+0G2VpYSFt2iV/rCjFm2suKiLwpN0xjIjgDC2j6\nOfi0UKqfex95+pkIsbCAtkQNw24mpG4vzZwGBbMC3oHrBXCm3I7bg5mnI/X2eOX8bI+PFS670Z1f\nFvsMICqnGPYexTJgVGsDmjD+Qla/+Sv0INMdHZqGp6+T0ez3ckN/OjO91eb+/HTG7UE6L7ZWVMBX\noywMQZWjVgt0tj3mEOzzO+UcqjBFBM6TPdBrEwUs1JHD1Mci9k/aHVM5mgYwEZWtfHfO4uS1qjuv\nEunuKb7d4rnxxybHStOpFiC7LPMhg+1A8q3DBzvX9aC74Qh7/z7Jq9b1Y2UX6qAnLZr0LeBjxN80\nXOY0f0nQwW7MqJvZftwqu1RtPa1dEd6VXwPF1pGYdIrL26+E1ZZcy5CBU4whFQ1Cs+hGTFdsJlOY\n+pb+N5zFb/4VjrbepLZ8i3KvNwJv0jM3ikQJX4AjjoU70tXegJRHkqcE1GmF9sa57t79WNypKjiO\nenXC71c8VGDVeTeatReKajbwWB373z4dwK6li2LD8kzafTe5nKiBmlvGX7eyrkVydMKGZTIEh0hC\nq2f85LJXaQxP0isG4R2I48eLIEQoK08rfDJuDR9NQ4iBH3fg0KAZxNMrDtvAa5wn9t/m45vaekyc\n9heYH7Pp37/hm1TPFw1xEB2kaIDIvQwlttvER0ix/zlRhVuzBpFERJkh8iqcS9OiMptGrnIPinzT\n0/3JzcdBnvYXX0NrW3NEwJ1Z6nrElQ8YQtUnG30JNHdBXCTquMpVaR+2TaSyY7jrQhHENAYqyR7T\nOvpt/Buul0rn0nTsLtqverVLgvK74YUJsvjECEKwYjUDY6n1HY2qtjuXTVfybcA/ifaNwmONLuHR\nxaRPmePrcrufnLgP7QJ/mABqDvWRWapOPLKV9WnddNMQS47n/O4dYFq9+tuMAV9g6pNHILsjTNFb\n19d0MAHbWP6LVNGxoXgcIPWodei+NtWtfvb4EAmo1+o7mBG9h2mlRUxL8v2VIygmzGIkLOrGmm9w\nWDvBpTMKIdpFBtJ3VTQqilkdmMJ9RaLjDgq5jHUGT2NFUslUIbBfiJ0vgIb8hJsYcRk6xofaIycN\nq1OwEB+4H+qH4hrR+K1sK9sSrIrPGneerLxRf5AOTLfOu9Woq34XOoSAJH5ih0yX9R28L41j5J+q\nf3U5bqol5WHt+AwjVMUNpFiwnux6ynKCIN2G/LkUE5KFOckH9gPuSylC88byeRpLPx5ajh8pImKM\nzLbNbzJnSqQjdUDK1Iu9v0NHOapYllK/0Y19ccCQ3kKI7Ir6R7Km5tOj5xF2TLye3UVlWEK4kGbg\nCvL5iTGUa38fTxKgV15ZE2rNn0n79MgBqFv2OQ39hm4Yy/+3Om5aVKt+A4pa72cRFOtv3SJSU4BX\nMlWdkKHJreN2nocpFRIExCVCR4bR0cr8YDbRph4aaEcdEHRyeAgDzQ4lYy2o3zqprKcVl6lQ+D8L\nPqyW3Vm9BwG9G3qM4a1CvfHb0SM3B8q0JQlGSB9ApZMAz00uyqNkIEuhaO6HaeAaE/r3CzA71+1z\nuNuBDo1Cfz8mI4ZTlWv+L5he3Do53tm8cVCmuLsXXr+8aK9e1xIEP+snDKzUPIB3xeBD11/XyipP\nKwpLsNj94N8Haee1GcqCcmpnmzcdm0MlJtoaWNIhi9/zUeiP8raMIhoFc6Ov4wrA9Z++Jlql+/I0\nM/riuqwdFztk/ROJNl//2vxWu9x0aHxyi3gJuxe6wFdWhlVaEK7LUL7cdatNEvN4APwsedEMVDJJ\nPoHYQvJC1CKXVB2AFRcq5lKaMrqYXnRiRU0+pLesvr4em+KOhWm2u/5aEX7cSYW8BQkK24t4FFdq\n+Z4vs6Z9iKed+x5uKElErIstRkVBFmIyMVZC5chIBb610h7P2gmFIjhTyc9PfHFTJFhzVQEPCM1P\nRc0++5KKFCoDDAO+bA6OPkT6uD+nVB+sXv7XpJJQ1oDfVPxAhvNRkzqypWAtkRnHYmqiuuD0TLV7\ntoPyDa8F+z2ztG6DuiIOp2IDShHqeiI0ofqIECo1BNtsL5WmiGvYj0eQScXtj465F/qr9zy0KHqR\nvFp82u83tLyEYf2p2G01IPfzUq0NOCIhdQCGi1HBNW8nwefe/lYWL5sFCroHCTeMSZiRzV/lpjMb\na0vzWmek1MkozXqJoStV0Tm3IbMLLgEDFMaLdaLdqk8z/T0r4r5maNdxl1CnsmJRKzYDKuOC6avz\ndAYK0ajLc7LXe1R4yFQt1xCaQqRIpIK67w5YXTuerd2HMT+bXHxHSkPI8WyzwIdshHu3pP83t5fV\nIF2Fic5wxGEd8yZIVKcxKHmdW0PDjl4ObUh7313+hXqiDzfUWMiJzPnHQBrRmeOAP0JAfjYniX1h\n6FwFAndkqD37Oi3ANfPvaDz/d/fwjZ3PIx1qeBpAC4PNAUwYzg5VjH+tgUE0IhuhZleoOQnE81Ko\nhZ7L6Z1ORKVZwar8HWyLgdTZBjKnI+J2mTEp57D1usEqa5N42PMxoLWY8Df/vs9RJxAArbSlJ8W8\nuhwu5vz7jkicRxeIxUeBByGJzigVEz9pK3SOgx+oR/6S9EEafa5jcKciU76sjdHzlst5IYaUnu6H\nkJEgPB0odGHLhT7ylSIVIRuidr7vKqywO6xS14AhvB0urSgggHxCDwXLraLm+q7uwlsTWtB+/mSi\nyyd9WguKaBUCJQIWAVeqVcxtFqiEI/Vw8XdPT6Fu/azlsa5s/6/c2Pi1odas5ljcPV6XMQzT1zuQ\nWmPfYmT5KZ/omcVkxnzb/K6StbOrG0YZp2KMyOQmWNfY5EZvLtehBn0vcSGWmIJzhzQZGcMEzjDP\nau2aNrR1i3oJku5BANvQ6rt1vy8oiaD3oj8hdleuBSEgMXIsk2DpMwgs+IZIl4ABoGStnV0CdxNf\nAm3xVjs0dVXMz1HZABU4odD3ZGAZuJSjgYDOZoBWEtXIGtCy0YAxUS7LV6SwWHa6oZ53ntP2Onla\nHhdk5j0CHfyY34C/FRD+HtcS72o7woZ60Khy/L7gxp3g0R5To26Z/YC7sPRQRnNZGSnNcFBcaW46\nVw9pDvM9FdWWjSlqNgDL5vW7eFhJNDv5lrCHXnlVgtv0cxeNMI0H3614Xo5sC/pLGpL/8o3TI5R1\nZ1/ZdT3tE/YkTD5BvxpH9f6yF1KtBf9EpNOJ2C9YI4tphTgVSd/yIoKZulXsWAEvuOUZJMzsAR5g\nMinJlf6wyQD7wUndBz1BiBPoDLlYMu5Dwt84r0LrX1Gr+KtCbpGosysh5miNiXQtSA3y0Z+nO70k\nwUy748Mp7yj4HKSzROY7qVItlR1Te+1vacGIpUbINgNY/seswofWd6cLcuVuXxSV68ktlScTVhwi\n5wXtPyc5IVtXKebZWme2x08I5edNFEu65qW12JgTtE77mY8M1OK0hiOCp0Bj3ER94RKBF2QWGi3O\n1KhiLJ5u8S/0ixMqKKEFwx84U7cJZ8XB4RgNtPpVpD5hJqmxplsHcTltMZTqSTwefKuWUrA/W+Pe\nCdyY/h1toLY413GZGJyUfK2iylrCVGXXF48Wpg6stkc1pj+pc3RyCJ5RxMlJEknv/fl2kewSJ16r\nbtXe4mFo3C7n92HD5M6p/hdt1C5e17q3Pcf0VyV9i2Tn0ecfJNEY7TioBCupTsUoU/0WtosVA243\nbXgcIzv/p2FfDG/c+HaOYGD0BAnKM9FfbHz7pQrkE8xIwuGi0VJx0VU7lTq0Inyh9zDzC9AeVIVs\n0KordoFEFcGwsJL3YrcYOeaV0gcfDindx6np6QjkEfIdwvrWYsjx438/aiVV910aFHldaV5uIvqE\njAIzJ5foHSMjCFlVqbY06nawYu1pvTA0GBzFz81/s5Y8oIaEVnoz6fg88qp87L1VQ3M1M/b1ZgF1\nT37aE1NFgxCN53n+cq0W20FWeH9J6RrqEeIP6dIfIOUagfYlGbFSKoqsSkR7MOEcHCLBARuWij5e\nj0rOWM5zomDP9L+CElGw7+2EeuWQnp0Ddpjo0Iivyt/z/2kPbs6rblziyTGlvNb9riuT4h7IuT3v\nZMbm0RtvAfEUvaXNdPVDqlkg4YrgGKvgo2gcnICgss4A6SmnzO8aMzFOLY4HdDF1w133/0zs6ucz\nuD0YGty4Il4K/NkdifjzKCEc9tfKMKoiaUunDK+PWbq8M6qFMITTuZmzHqsscWKNcokXaAzB7VcO\nUMNa8A+xEjKylc7ipotn3F9c3UPfmOiDv9lVFsaT1jN3DTs9ILrOlHimHsHFkOqGGHyT7voQXbDQ\n7744p8Mfz8COMFH8mW6WIFsqjQyreKUWpOR/Nl6L4Hnn6cg5fY5pom0Hh+7Z6WCaxcQb4ovzn0se\nZmRveJF+i+y3PcT0bOMkcT1d6QcQpnjCradKIabdgz9pQdfW0Njt5ZEm+XPLMpMceW7TnhTdkDGx\ncfGiYVDm7zUP+gfR+0i0fVaCIuSb5k0AtqT2uKJkX1O+NH0/5Jr0MpgWdmtH7K6ItOtJT2bQplGn\nnLf+ZnSx9zYv3EBUvsJkT2hntZAWRcZEQD+JQdjs5ndPFSojnf8EZaYNS322vNfM7yTehHYPm+Ti\nVSXmn612pDMfBq0ZG0X9UKeK/PcqDm/N9yvrQ2fuhITCzFGeP5akwtiNlB6Gu55eUDzmZIFfxMpg\n5rg9OK5/tdSSMLw/EgTEeSTBJEmFmsYdoIvpvrSF9N5+WNdBnU0umUWgi8Ku1tuGp48T/LlXMW45\n3OV9NWfPIFRV34JbY7a7isX8I66p6ODVvUNxMaNAaCnWeAnLwyWLrU8kU5sKvG0RYeTCVPqdDSKG\n9eC9QXhTw9OQYjkKmQXHuRA5ozeM7QzNSAadoD6rWwZxTNMRCBY+pk/czIX1qaXFrmA8wi7ca3/Z\nBFyQ7pCciRizvzORgc65N0tYUgCpDU3MwudFapwE3j1q/1YbMGdJTqeoaEw+R0Ca4SDM2PPLlG9X\nCFToA7+a6iTHbp79eGUTH+XgRtKvf2NqomrwGBZCzeqw/TTxKGzzB337R3DZlR7DLT2s3Nsva8UT\nMiGk0shxnGA2vVpv2gW5bcOaChbvjRnyDz6Wxdj+qYdMee5mjE2DLPtXSzk/gcTOaelV+x5UllEU\nRWHgKkPZcJhJ4CC+d62sPL0q3wV2EKOYAFrqxZHYaDcsZe9v8RyzUDWo2jJYt6HUiXPAFHNiYKNZ\nAW7n1huktAIRo/ovLEoDK7qWFSBOMlYUc9gnNcMpgbnm7+Bw5vjLTim0F9znRtJMacGPZkxI8i1O\n8o/s1PzghqBff0IWMhcDUlgZzoUfS6Jh6Vm14JlJql0EgzYBtoDv8y9Iz5Y2mIAnfzfPApeS3eby\n1aSii7rYPklyIv5zzc1/gCyicADjQevrMOyoQU8XfYOX50bHi71MT5yCLI5Nm0JykRQ8xdZVa6nY\nFLMhFPRqpCGepZ0Jzg1mjZO/s/ZTvPm2A4A184DJndtP+K2BcZzsfTfcNqEEpqXJ99VQ+qeKYlpJ\nm7IrKhT1x0PQtoMVwJderKq60UUdomo9qWVKRyGTOwlTnBAIg0CC3Z2piWrKuDb+HFBBfTa7MLsf\nVvlnNTqs/j/TM3KyrGG+7DmWhH+zYYEbrpmknAq5OEkiBMknbZjGO6fplOIH8pF3eYxd/1bwtNmv\nG4cCTSBvpOIAChqcUr6CddtQfhDVUxwBXDA3oNtlkH8LLlgMz3r/H6VhOf6DaIYe7qLrsHcK7NtE\nqClE84qVHHxRu6hBfidWkAW1IXvuJbC0VyySgnx3mWCFthUc7uKO+UCbDLeDazcF9ab8TGphTxTr\nw0SAD55PdfWQ6zjslISqxeSLdhHMC/iQ8AI6TcfiN5xlpyCuAQhBXSBPtt3Zvv8TkJTiEP5DBAzP\nHmij5pLekJ/5urX1akJSyUVC9Hw4BEjoCQRlOuQXTDN7odgV8k4oT0WuGo8u3A02gVAacV2tTCQG\nqo28+r0tQ2d+4LNuh6QHTiI1SJ26jauuqsKjwRvqLiTxziecNYNjt4/w/0Eac+3RLL04P2F1z9qs\niNE5/rumLZcU5FjCK+rx+A4mT6rZKyOUEwEklOb/N3oCLfL0KdjocgvqDbnyqiIwHpNV9bPIyfYz\n8z7kJlqNJL+SZaP4S/Q0roLVNGZFACOwhDQxITvnypC4ABt2U1Y1HgPnGmR3bt1ZjEdrM8PMOdde\nZvBPJJzGFGl5HvKGtKwn2ZthZZeLbg1FTlnWYD5ZKjfJIyF9gADb84cS4zGcB+GXL+5SfoNUFOy0\nYC4jMeCDdgNUVetxXyR+14aX0hR6scfo4ycxZuJt+tOPriEytYG/gb0rQKz21zvDUB9zL7CEK4ch\nNDsDQSfSjKycDpJ0BTShI78w1LsixcKmBiZ/BR1gbK6kcl+sRR+qIPUeMdOT1gu8slqK0KefvBGO\nsV03+M0QL8FEMgW7m6iEdm21fUKHsDMSf9x1kEbnGGJjQdHq0pyQJwsclacAFk9WhtKgw7OIzqHL\nSiToIHFVQkA13B9bb/d+F7fdhPCUzCTsqiwrHeIYaqwmtLjfOM4wH0HOb6AEO4bizzlfoDhC3Bmc\n1iu4yj+4umcjWCvorsCxDEat9aSAOCcomGWQFTHriNtn0u3/9DoJYHoCFgmuKgXQGDxliayqXwXK\nbEFzBKKkOA2jaA/eQBH0m0/RUXYHdtS952uYyVjBWyfKHfHlivfFDwonQYDXSXkK15bdeplfkUmK\nYwdut6Ntre1DqQx2szASvuDqmewSOxMD4dQGKlL4RErEyOiD67Ri1ViUDsanUMntzvML/KQv8UT0\nth5MkQaOx8RP2JAETO6eK12hqM6tjnYmP0W7/lpsNn8hQ9PiXMUGPCN9jzwDuUsXLUN7DZGy2wP4\nFlcIL1zAae8fBMqeVOeZvX6pJbWoC9QWlPi7veKerGBEOU8/D1c9uhiedUOZlwPswCQZqyYfpMv0\nKrHblsF8WfvsrlcP0flqR4IhVfyxguanxTyGV0v99Mz6q5+yRWwCxwFSZ5Bq0dvND59F1s27L7+D\ngjCG7clOaCF3kCqNdluLbBF8YAxPeygj5Z2GdC+PBsu6QH5ty7ziHI6ItNIxtDjaLYNkcvkd+qKJ\nK+HffjkDNjiVW7oy4fVWBiVoVfOdFYHWk3tABR5AScrz+osN16ODc801V+FYfx1DeFvdkNfvUfBW\nc70MY4ccjfJVHHxAvCIKD3CH8V2K9q8e0O2BQg5SRwUEJqUar+j7H/WEFC1OJ2ik6DXeDg/Uj0FS\nC2GAFkkvMsXYEMdCXXe+RN1hKYXyYg3GCBPuv05guV1WCkT9trWM7jq4ojy+ZCcw8ooeA/qPUMpG\nC7eB9g9gw8tR0LTD4V2/8cTigLfI49sqcbf/SUyoF3teZX3HtPa+Yq1395LnpyKERqSP3qk3BjJ4\ndG+tB8kQDe5rLfe8dYioH2pGOCzic0cNEPPzU8TI+nyzFyU3erYtPE5tSRDEnucBnAfyrmIsyvVx\nXWLtJZXBfSwxapXFFbsYR0GZZN3ok0pRZkB2ivq8rQ3JsHevoEyKnsxrrxtu2ZB9Lif63iQdNKn8\nYIWmsXknrNF5iZqJVBIIE8BcRVqF/dO3fL0no1IkHC+gkeuFOU+gn5YB5cheMwoaDE34UvMupSEZ\nWxyokrnGMlsEnhXQBtyhVjabBIGiduvyZXiyMPfEL/Dd0yGWAQMFVPMy3xznxC3Hm6AhgsT0sFdZ\nWAn8hDlM6M3I41Ec3u9L4HtNJdmOH4Zmicvs9MNv7KB0ZdgQFoBJuWEcONr8I2su3aw9br44q2rw\nQ/z+2zcH4PvLRAozFQks6fF1cSWuZQK5ReNB9GOtdy79s+YdJ1dydOOLdvmVuqiiJMCtxPQknUul\nrjTyPEB09L3SKB1KuLFEd5dZE84Ts3I/3kZxz4G3um39oDlISdG3t+HovWfO4eakdrTxyqXTHKer\n06d1kXlmUsgVE964UKRpq6Np+PXI2Cpp9BtbOspzdZ+5BwiX4kB6+zgczD5ZULtlf434NBO4sgNj\nxu5TmiC9A6+E5H7rDFZcFclQZVGwnJLG21CNJGqUH0C1+08UdDSI0usPJGe3P3uZIXrlVIFuFrly\nxeRUrdCzTLD/G4ve/uWrvPZjRFT6TsJI6Grm7qHMHL26deVerGG3ImsA5koDQSyTFeueoY3Rp5Am\niQwKjB4ZdrXI6zA4//Jf+VmoO8Ryj3M071oRn9dJNgZcEipZ6gYm6m/fzIrY8TL/eDjGZQ0ybvMr\nrWOAiw5CVZ12eomJpn+yRprOCr8AcAzw5bRpN1PzenE4vQnJN/YaxNdAO/UFzLgLc3ZMbopjK72E\nS3zI7LyW+/4jVsElspJxI3EMl2KlJE/knPhXlaBXYwxdFBcOcf6LZyurPP+ixYoxNrf/o/AKkGcN\nDbW4etewLU2TRSq5gP6vDb0QB9CJYuAHVe+kLOFkpKhIr7XBdVMuzJUhxc/eq7BDNCZcscuFztt/\nE0goovmpdzkrwqkwTPW9Yjbe9e5YdmxzbgNbsyLD8+uLaPZ47o8vPVgdf6HttQ/KTHEHtp0/XwV1\n1FdTl3GGfuaKb/lu6fWYgoG3Bxzj61QB2xXa9dUJCzkb3onXb+wc7FSBL3MrEbF6VscHmEkIBMlM\nnEpFM6YH96EDL0y9XrXtetI5z7XR8oWG/3KYWOl5bR+RrcOfYZ9USt/bexx7wy5/aNxde2CeRNPx\n97H2mLTu324YEEQOTVwY+u59fVpeKWSLk9OvS/J28geKK9GyQHkiT4s1P09nT2XWoZzsD4OzxQ1h\nynF4Ze2aOz7txnVq9r3NHXSXOldB3WbZ2DHHijDBpEjnAJKxe8flaxtKnbeZpQ/Hr3wwDGsMPaKR\nU/ZGOndXubH/oRV5Chu2K4TYcnD4GG/ufV2XDAg3SK92XWQ+/Rk/qlM3YIUbieCkiiIPUK40l9nu\nbmWzd5U24lgfYsAZQD+4PA9wS2RzczKW1UtvIeFPFw6DloefA24JD4jRybSieMQnvHdvw5QfKVnN\nz784kio5sy5iW0gtFTCKi/3DOoB4otEY5b92vZt7LusXVL5EPRRfYAn7cH/SUJU5xs6uvKOd0bzj\n/fBxlsZfJAOtbedLQBSvvJNckOciN+dD1nMVCcK0llkihlnKYehg9un8foI9pWay2C3ABdepvGJb\ndufT947S1tcWo6PWW/xlmNpw5ak+uF0OPo1Kz9Dq+cca3bdeO8VJA8wzRV+rtVhni+0dq76V6FkX\najVJeHcMQeBoMzB5vjRnHGJxETYxyDaYP83oKyZt/1SzLnxGjxfMC0sy+3iMxTOou5hdXOIXGodB\np9eMqclwyl19mWZm5ZShZzqVJXPJ47Vuu7CEwQkeeVvaIRQ17f29lmfKXvGYkjo1Nf4DDcISoVPd\njGo0jUtn8VUeTk2iKzfqpkGqAHFWscEEXWK0b5i73Vv3XkY2Wy7hDwio1mUcvB7d4jMO+kfuIgwm\n+THWkOUwATRmmRA5gI0x1XmPMuXHkfx8JFmw/nVp7WJ3unl3jQSk6XbmY9uzJNaSwFFR58E7VIk3\nyn8vouSLDNHAwjNW9F6OiHPzH9aPjAD4xECbC/JrOJwu0Z+bn2JsgXJxXAUOqMQ+dvEgRCu/9cpC\nLR/x/fCvq7i6Qlq0Fqgvk79g9QfrNAACCH05u3G7Tak7qrGgplI4CjC7hh1TfsbQ0J9Neo/oGuju\nOtjFoVPzJmrqs1hUITqfpCjiKyH5A9IIb7rPT4BIHsAvZ+uqPS5zlWkCoi5HinfLh7Rzdbm0xWn/\nFOVKLxzH41nsa5QTfZiIv8tido8LI2q2f6o8cC6WkCmOZ17LtF7znB9Ho3vRNbzIGckxclvPtoN0\niOifLOu7dOcv3otFFNLPS3lJVg1WMTYK/VXN5qNIKA1TRSmQVcHHPf9suOpvtLbPnglJkIqXynGY\ncEMjCXYeUTL6klZ5iYgnModqzK6DrswUg4zyDlJqs6tC1K7+uwKlLl/MdWu42LviRaXanXJLG4Xo\nBzvGfm5/ckAfGLebNNRym/vpO6QtVIScCMskRy22e+cWWN3DgPI4p/+gNBtcN+AIXttzYCEM9WM4\n9uDADtneankaIaEsnI4M9v+ifaVZjroGfc2hodA5sEITVN770+iu4CG6hK5mff4fU6gVVhI3d/Wp\nHYWNqeDkcXwQoCMs8eb0xRibUdm2d2f6+hm9BYvS2QNkIDtxoUIgevTldqcQeZE6P9VQSr/i+aBZ\n8AN5V/JMsl6xicxMdJvdVJGa3x+WdPMT83D8Sm6+JskZLwiO//r3uPLyQxKsDQ3QYbow8yjFYck1\nGgm3DaZsLdmsLfk2SEGGDsG6trqjFbL8HYNMUCQ/XoBblw7KLAn6ESCRUtPMKK7J77cTJUrLTmxT\nDfvrMh1+iFodCG6P3ccVsOZY7yRnK6hDngM+9kqoeH6gZVf+6+XJ47i71PxwYF4R0rJiClt6qJwl\nN5LtwEkfv3+LRz/5jkWWwZ8p79he60pOf5sKNAmWOfHfRIrSergkM0MErxZ8YNQSUfqUQlvnnFla\nvFygXsylhV06gJwi/Epd1kUFASAB6s9PFj1hnRRigLvIkzxOk+q+TqCCNzUkQu9KkUyLfZr4n74p\n1DPKuoJPvzCpWMCHTX7XMDkqSmz4KKbXLw/Apu3e/kKtM2guG2F0S4w1EMGaXy9vHiwP0YG0WcCp\nOoorvOenXAkgem+Osp32CtXvvchYguK9QSSPP2ubElW6D0/OIa+621FVRlrr7PSAcZjznZkLviMc\nAPQgfo2ZMU3iM/EvNxlzVgjzTIDlBOWC3XTWa0xOsRfn90nyPw5mD7R16L9+twT07FHjekXGSStS\nxGrwMsO9Ws5KYQH9MeXBZ6JBKK28BIVUyonWl0Wgl6fX4KWbwPQbwAgKiiFpelsKc8zogCfflspX\nuVbrX5IX5Cz9dAa7445Kp7oizpr8OE/otQ2HCSKs+dnwAEpBKcdPTnrIqqq/kFK3Ps4hOVKUFwZS\nuZ948jRikfCt0Aj07eQac5DWlW63FralaYNcd4si+Z1asdP/f8QwXI8h057rJeqktTftYAVnQGE9\nbcQzwG6tt/dsbspIbets2rC2hYezwZmQtuYEd1EflITqX4XDqbHwxHkpH/sl649nM4XO0Gg08Ttt\nAuLtblDnnWaKn+mxGvXeMCr7OEgNPlUdZa/9XuDe6IH7XkBxLGh6Hd+mYVesj378qkZJ8l1RyVuZ\n8bPQuJpV2cEV256N+4ZNSmbGROlnqxA/mFw7ayLRdUQoc8oD/6tZF/dvWUSuhsdcb1ymEzL0Xo0r\nqj8+6QPCPW5f/MWi5B5EUMKcptevey6Uyvlhu+wHqs44onA3YUxvtQ7RPI41SJflg8CcGMC2qjSh\n++sv+DYDgpJBhgJS5GK+k7Y1qhE326F0lnZeXlxgJa9yjtw0xEyG2+DstZtriJ+9mE78isdEBLRW\nDFoZKl+gGpyVuW7U4OcWqjqDQUyFDtlyQdWQ3WMAM1d9qTVIvdHj0RlEQ2nEWSD3i1NyuOlHBhyi\nwgI8x07w/gJVBYGhKxJXSuJ0Yx2UYEymhIJPjF9v7I6kGus2NSbbDWtsq45zHh+EfB0xlsfrHmvl\n+tSxe6fOWj/HTgqk4o1t+uwL4wv2ZcLaZaoyQGWSWVwyMLpnjym1YM9zygrw907LsfTA1OxUjCbd\n0jAn/PqpYcLO4TlGZVoVeSMKmzHbqujcQNROm8LtNiIPvC1+iZRHKHzQw1alquxd4vNXRZMFQ4RR\nceDo+RDGSl0kAtTnBXekyUlKevCDQy74A1ml3tMY5CuG8xqi88l2Fl8QC449YEUV8VfiiE3WphjN\nYA1U21vDckleBiBa+53ZoTD5i7kAXcyGnoaB3l5+OIZrW1sz6DalvVT0TmffQvhs4vWoTCujL+is\nFivYgSLhLmtorRU+mrJtTd7Nlh56CGrsIZWRbD3EuTuLPhA/VOcORttRBx4hK8KUHMls1MISjNER\nHEB3HK2FQxFHIOclMW0jqirfL+KaiOfilCbOO100QKee66G2BLpyJSVZhWYnj7s1xS0rs3+2P9Cf\nSXHMM+k9b3pQH96DDr4cTWoVMRadPdXO+zLqphzsu7SXMxzTrxGv9YMsBn/sMa8juh01T60TkFPw\nndcq2wCzF6QgQYlcROr2wVTIf2Q8MH7WKaEMe17Yn3IpK6k+d/gJAdB8C79Dx1dU1a2Tdzp8mq9z\nV5Xg3fJLeHuwP4bxcU1uhfyyfSXywB8FE9Sdgu1iq6T32K+bXhodW0LcEwlxhR8LTvEMLPYbL7oc\n/MPVQQdqJx5NEiPGKVDqIA5B/HVGwX24N0rYXX3mOkY00XRI5Z82f5CdYLy1KaiYlTHUXQ8cCkmb\nPQtIgyfTydEmAtt7+x4o9c83hL+VpkXyBSSJwOxX9fShxpfOFWKpRTd4ggVwTgmVL1EZJMH4FwFv\nv6DO9yK932qSAlWq7axdEEglvCFANv4nP7jTS5HVeNHxqxRrkuqnN+Td5WJuYdptAfWQjeSxsFAI\nObkCIDOVoJUEMNDplXuHY8dHvXxghVBerjO4hutN1+Zh1nZ56VqQcqbESjYO2Bn75YXGo15h80Wd\n4Tmy2qGT+pahuccjS9lWKo3fxL1vfMYl0vu71Nn2XYiHBrDOSNhdIQFznwM8P9+GsOCUQ4fQFrZf\nDJHgNQbReQsammffCfTvyvBYEwWxEWPunE/ffQTQdQ11ptEKhc3Pjv2UhGP9LURrkruCXUtoEKtZ\n/yyj0ghGvhjxy5++1aH6U+wiApdX/Xkn28ACSruR/i/ErLUu+VfWBRh8mXI5d8faAurGLqe1dJ6z\nJTkdo9PpQ8Lk4BknrS7+K/tV51znY2BG8vTELJOVZq7bWrVhPJOfuaIRup+4Ll48VYYuEV0u4p8D\n/f/ZFEq8zJzU7o5IJJUvR3t4VDAfSVjYqL4Rk1AEQPj3FiSv4kFoloxYV2bqwy53SHO4GjAlJATb\nILDBQJRw9Z0NIsm3LaVEvdFYOyvnI2TE7EaMImLSRDRXnW2s4vpPkgnP3X5gcA4dmU3LOYRNySE9\ntIAMi8Um3v6yIIdUjvVf916FQOxEJ5OPDpEI5thXulz2QHOqUBJ62vbKKWh7xp6Dm2IODJCtY4nH\nTUhMACvwLYkh8kUJFempyEQWYGEVW39P4U3eD5AAK/wVlS+2cZUl0TFbzFvGqPBYAnjTOR8j9AeC\ndu3to+AvmmQMW7ZCQ+OUjP2t9jJVxkNixkv21944aXAdZDp47/n3i+GXefT4G5deuxLhgMnv5SOD\nWhucdxnKMn+6n8QNEwsYeuPu8wwFJ6DoHvhqW6WbkBPXtt60HpD7a3h94c5BoId7ueTuqEfXDL2g\n4WNge+i8vLIJ0bWlq8ePHRfGRw1+G+hnDI1t6feHtB8FXllV/PXtzlyzeSmhTknC8Szc2vYoFFQb\niRbyHo0Gpp/WNOE8TjRmdMHHb4979h719cC92LfLI4oJRUHVPdC41IBDNAdE6BHeBlq7qIHopl/0\ndfGoLrrOH/MEPaN2AE2vboMNhpkXnq46Cctd3vbuHdWVXzLlkyi4S8Q7js7txFqlMi8tfhxtqEQp\nS9jQqlQYTa1f2Uua20YYVl8i6eyyH8pfR9yzYdnHNnVUZ3pdNbuVW/mSnAwTDGCWb/ugYglj0YAw\nw3P5QDp3cMB/une9KWxsWolX19w+e2VdcBaSaPYDlC7GkaYnbgXqqJeJIFd7/awaUbGFtehHYaeE\n3Lp0wVVwdPbkSTwYr88IGAydoEEvI0fN3tAYVvOhbsvPopKKPdOVPrad9LH/zgK00+ZxaU8g5+AH\n1xG7VQXYggcceCAqdlpwh414WOVGxinO0OmWf8mVuAHdvUJlbz7YKB5z4N6rGuUglnxpRSMxjeMd\n5BfXtgdZ5ZHsD68Yi3emWmtFElr03GZ4MMDZKlhJcQlR6QzvY1lO+DjoQIgQDS5T2hV63vPR1hrz\nVlkOxqNoQf0JOGYIno97gYEExKKp32RxDhCWXBlTq158wBTchhf1n4DIOh3U21+qXsX9BABM9WlV\nMuJ1R/fALbSEfbzDt4Fog6vJ03hcrjF8NSxHFj9xPalMHP1FGfg3avr+skb0dhV9az5dF9USDslo\njHDwC3Onfj0L7tmM0N8SZAXoZiLfXTJ7Zm6HLk3MmF/Q2TXverdsMNl7bIVzseOFP0Nfg4qkILjI\nIL59jz+liRFx6zU9ubQq+cLXfxFRbYk94mE/U/y76HyXgsh144FlwUrYGjPE8EAry4qYtaRR7cuM\nuugB9P1uUETLVzivpCtp5mL0W9pQk9FOjIbXkga1rh0H1eU+z2RnVr+Ur//GCgaqUUnrrbfIPbdJ\nXF+4I5L7MuAQvkyxIGRPFcFOeQ9SrTSytfN4pKqbh+dn5FMP8w4XdplYMdvRQ1jGuP4nBx421qyd\nBuXAr9okGI6bHoe1RL3mrJzSsoBS3Pjy/6Rv3K7DGVofvPFv73R4Mgj+3/lCCqj0hOJjvhxsxJcf\n+3xAcHfrpyBl232uDKeVKKPGGN8tVKMHx8axjsLfKCJ11YmOcoRlIyTak4oknVDXFSGTDq//GL4V\nNBvuj/oBfmbi4RZ7qAmzc7Y/fm3tGmyUL0sH4SO0YVCduWRSsUe6EhXiPp6D9DldcfTQdTqd7Fit\nMfcGxoyaKq2yngAEBZPECnFuOzrQOpRB7cVQH+A0n/+tBrO9csvd6HbG/551/vhrMqyzbITGpv4C\n7IcDpMoC4BBvpRFlQ5FWUV9txATpx1kvmoKRSOsnw+2FjnxK23aHOgeMinkjbqk8BoNS8B9tjeHT\nKF/wkCjQLviDexazicDqc6FrN9RUYtocJS+18yf44h+YHAdM6xqvxzmqn9hb7ODT2swYO3WBpdTV\nvUVHctwL6hOS+DmBbQyLbcRHCrlavjJoZc6oDzExrdrpTbIcGzps+K0FeP3maxSEpf1vbhlV/ALy\nLnPLhfq+O1dgoMdpfwkEoI4s8c0IXbjHO5U+BtV8RG5rBD8Lp8Du+y7+9JTV2b3H7nI4056YKpwm\nqNvn3RJL5uSdaijMply4VCbiaclPNKHqF2yX2SjqooJ8lBpn7EK0Upr0dOzL6seEIU6bEhJBYiEh\nRPnred4Y2VZ5GD5gj/aXEey1okTuyd+zBnGatqWXnhnULK0jaNMGw+/JusjoZpT1o5m7Yojv1zI+\nOVpJ8YYUbuiGOvszPwKfMiAez8Mba1/Hf91cKDEbRKKQtOVMtrKpQFvUeR275wDVyzeNVFcBaM2p\nL0pkyQMNzZtitzfDRRv/FiK6ZCZ4Rj2IDkamvbx7zH9VpGlJax0ZqIjNAyxgXGGxYdi7zrvLS0Ng\nRcAkKeDT58+NKj+0tJWcRo7nLeqQAhFa9diUyqlV4+OekLJsqn3bJes4sh5KuXZStusUYq2zxtOt\nwOK6Tjc11pesim2IQCTUjZ2o99sw1vO/W2kony4DPTsnUD5i1Jm9mXsBja/4oAhkp3M35vYYcG/M\ngOJhq31laFktxJcc+/LZ7PhtJlkw6QeS2uGwnDxKqS63XYT7dhP3ej5eMpsjvVC9hoyZKr4EJlVt\njrPn0bsd+5SWP72WLUmY+cOGS/B6caFfMah5TNQQfQbfyI4wAYmFrmNqAz0ZksD1fqmG9aPg0of3\neItNA3k9vq87ctzMNrFMhjiygkxN+2zrXzpM7AFu+T5QnwdF1JKsUcIfCmWVofFxRaFl4KQ4G7eC\npCrQoOXK2z7WpCM1bHS38K/VclXj12GJaaw4Rr9FKZwKhtvTJdqMV9DHEF94wx6BLOFih77qGjjh\nfYjDPTosOr/Tz96oa54lWZLXRY4veH7xyDHg9Obd2uR21XAiA08qYNcky9/DS2sh6MD0HjZodikX\n3KPI9xR1x4Phmn3lFlyT5LSBcg6U3oElfjbVd46+r8BqF8/kGvQtIU4da/XsaFEZlqvofiWHH963\ns0bASbzwWO1plA9nS4K8FRFodmR5yJL1dTju9dXmpGxgVcOJRxAwDXBhiq/3qPa2jHhe8Z/FiSNx\n0cQxj8DHHLGSt4cw5J2wrqDeAVSqlwWrwRKRcR+0drGEiEkxvtfmcxesfKNKiCDnndHZXcs0hlK+\n91C9v9Ttgbp2Tg0jyKB8lVMGX3jy5e0kWEJZn//cNhep/qqHXJX92P+2zmAKgk4c3JArUVIJu/CS\nm7xdzsBvg8X3Zruc9twVkygsfxvvg/gROl8BQAbSyRxvUoVDR966mcgJ9WkGqSmBq72LmM4Da4Mb\nXLHjZpW53Ew9N60zSoiw1uvikMgYTSXGbhDIuTwWYWOdy7a6+Pd9qY5fHCOkZcAvpHJ1hH1Bn6Mb\nkLUw8+wZEBlxl1WAF+W/bcHy3JDzyHiUKxlE//m5CozNxEzVW18+fWZOkHys84TjY1uZUKgF4qQS\nh0j7htM42qBpsJmMCFJZDZrmgR/FNMoW7hg9YaK3Dggp3oH78cDTkJxJH/N1p48kh+LuojklHN/9\neEdwwQq4QjFySUfVBL1etO+WJJ+octgUuir8RDkUQxYa8+JVRlauZvjkewivRTcyFB85oJlo8M1o\nkAnbNns15ggr1MYs/SCmAU4dBDDKoYSQ2vLn9ROqo2NOy9L/GhMCE8WUgGwbx0nIHLPFbIvkmJwz\nH6jPTTXxYgMR9rnM0yEzcZ42eNsBYGsa2x4KFGVrGbRVNwYkmu2g0UYO08Pyd7Dcnhyi/aZkLhkJ\no/TMEGoABYfHc1dOAI1YQQyOIuF3Qqg9e3Tx5CVFw3RIYJ+X7jrOM2yOs33cmpKx+Dk8jo4BzfLu\n855ClDN4gijRcJ14pNvRGL0v5U+6C+3oFx18ROsN3HgKKgWJDfd0/EFVm3ckqfwZcv+TS0v+UIxi\nziTycMpHnXlMbdKQQ11tkeXYhvIlwwlyrJV+RdHE83oGL33mwTyYhO9fLXCk28XJlZhRfPrhZB+p\nLV69h5M22WpqWMlsi7r5C+qxoc9KklbyRi+mw0la5N7MLSIBzKAvv51dEg+ui3zlEvo7a4sUbcmV\n7QulFhw4eC7VfY5x/rBplyl6XWyxaPdpL4PiB1M1RY+sjpFxb/0WPVG+zN5/RFCO5beB2GIkhvyS\nV6rPp0+VpxcxffbaPTUHbrsCrvEcNFt68eRj26gcPLWf434QMpncR9hhaAjTXYey1sCD7sCBgehb\nHOz0wPF2zpSxZNqsPanKeGtBh3k+OR1Zbqm9DOp0uj/N+H03Yc3SIWuMuxxvzdAbXSjNJ7Uc3KG5\n1xuXi2p7ChCm5TWKLeKJz0fdPuJ0T4V1zFU/egvB7VRa9zzrdZboiACBiI3TSkbX6N803xfJ9csQ\n7fZMvKfNhPkMTI9M2kBlQrMQNrSiResBx3QlbgmrOhHYYkxBopE05QSOg1CBOl18dg6IgFhV5XBS\nRhDcjwhFHd4qnYO1irRmuFAh4RwYhY1HzYXjIUJ0DJpaLoIl/X0hAbDVfUBLZqY0Bfo3S41GVAO/\noMUCx8bzW3KaDaCruQP2v59r3cITv94tlctybgnctwQmZV3JOg3pbqk3iTBcgIDjOqNybDE4Mny+\nRc2ICjcmQvjaCvrru+v3kynMr0oo+Z419pcsLOKDiJAlYtYI3idRAR1L9a43i2V4SCcuejRbgsm/\nLjqvzyO6uKz0Q9u/DQv6Mqyq4NxpZo+e3pKgwA+e0V3sFecKEcx6FnsT727teDGMMAxThq65jTc+\nrpu7CCMMwxnYq99lLni6etHEdzsgLg8EbBUmfOkggeVj9LQkK+uVpltv/Xc1qT0zHvGCNMnofWzS\nDuLYeXgNvQNoZrbWEZtBdMyC9INPAjR1d27/gs5ek89f5QvR6Lu5QBwZxXI9aWFg6oyvpOniPr5L\netou/+CXcGdXr0Nl9H/gDOekDAdvAh1EnHVhzg4XF4eWSY000v+vDhzWr8QZorfWSJ/WIXaQDFeO\nvMPnWksktGNGSiV2h+UKMlV2UXleULc+XT0mhLcbg6OBR7VJdzIdGykA7T4y9gsgCisQA3PntLIK\nSJtWYByBOn00jXAJqlRqX0PTiF5Znu3YuRuf3veN8ipiQSJ8bFK7CCRchBGlriDTFzNvv/9axYxi\nKdLKBp05mndZmYJGiP32W4kEGW7x1L42YXQdvkzTKEeuOFOAa9YgX3pGqLEseO6XV/kroA+/Sii6\nbUCjQ90hGb0Vpp9w6b4ZDbnFWW5U8PJraFOFwOTVwhIYrHG4BNn/5nVa9RuzXD3JSXSBUYUNHfOn\n5+aRrBTZ/5AhOboN57eSbwnnEqPoNOR7pxd0igwgPSpbA1efGgxkkgT8/ydj5X3xahb7tLvHVTzh\nKvF3aGueybUi4KceTo2KUaDGImRQNr9HxqwM8FLN+4uCWghn8xrZlfjeCGdfvwgpc2G8acuiS0H3\naZ5GR9dkgb2t0NSuI0epJtebvAOPTXdPO6Ri12AeV4hQb7tzij/skfMSeU9pTJfkj/WGsdP4xGih\n1liAkB4nHDmc0v4UGGJMFB4KbxxtLZ1dxW5tBYAy21EnYdKzz+PAt58+7kwaVwVek+Mu2++VBeyE\nLJ2eqpCDVj+oBNW6Ms+5vHBt+ROzZizKCxNAyFn3Zzmc9C2bNpAaCRCea/cGkhZB23/rSV9Dy9IA\nNfI+ztDuc0KKBNxdPW5kkrLAQAv5+mLUzx1aXbdwKcVv+r8FQFRZAUwGlnGp45pO8pdx8MixWAq3\nzuQapvp7kSad2v8Q6L39u2zgeV2tVVt9ed+WuT/vT7UU5VQdnsy2N1e4Pg5j6F2kKLZqXqIDsfoJ\nK9EIAd7fgEbBch1H48q/F3i9bTJ51bBAZZIaEHY07RMK5q6/jbbkbH+pQ3AY5neKEpZwIQ2aykxM\nJOsOsSor/58b62Q5xhOVcCZyK5XYBkpj5vbMgjuYHEtka8XiCtG/GTbKOsrS5GCAuVIGQ/qPuH1M\nz6BI95Np+zFF6FZVZlY171lW6NLmSUUpx6UQ251mU43BrI+RGCUlwYSDBf2BFs1kf0msJYQohBkR\n5quoLjPW0y2GeVZfDiKGk58vZPVWxiroW4LpTvys8tZ7IlSEwmAgsQnQJarfNdkEHIE3fYXaQO6q\nzAtmfjA81ZXCcefA77+SHc5EBR6bnYVyD4Ni4zONmd+B34v77knAJCFuFI6Z4X4gT1+ekJAe5Y4A\neQ2tTKCMTJvkDxK0VEzmqwhhXZZrcMYea4K0uYVgHnMnLbBOu+T7REmRduHbGd7FxhJnu5jwuTvV\nvlCJa9I0Iv8w8Kg+mki01y6rFmqxg0/f6uds/JRPqXLYbyqYDbVpkiJ6Wl2pKJ3AVFaiofQCEO8Z\nd/A2VCSFb7K/kweI14Q0UySq2+Y1Xtxi6deiGiNqCBNZoxhhmGCi+q3a7hYd1uW7UuYaY8JR5dlw\nCDB8PsjIrA5TwcDhPrhkwVBRHHxTqAlK3Uffl8eRMqEkbAquB9tiXK3HMupiSELgq7XK7uxnAlQT\nAFQQi92w0caZh5vGEh7O/8kI6t3LvipNJ/J1OlGTilBllOldUU6262RPo94oDUOc63SX/l1CBcHz\nUk0jzqoaoqw6nbYcFUoPzsJQlPhJEa24U6ql72dGIokxlY0nsXRM1s02Y/FKfFfTkI65DStCBrLM\nwBAVLrjIzLMO/pPaNPr3PQdjwVja1NIWSI+iauuVw3NjEnu6nhi+MTaTIQW5Av2Z5AAU2IRHSBSX\nrwdBeAtrptZgZESo/KaUAGRXFFEEb6XvnX3BIxGH6s27tTHVCOuReOH39boLo57qy24WgFvBpwvh\ndAkt8frdxtgV+5pWGsw18jLzs1266sRFsUgvU2KUiNWd2EW4KTfoGuFuo3ZFdu3809CDJcwtA6oU\nnymBlv4SBXFxgGo5P2KrjcCIRdVEMiFUMw5xSQcyLdoCZOE5LkvkRiLqkEUmGplFZMFfiv2MUG8Z\nKdMS48wyJDFB4HKF9hsT44hJbbdJn0KNFxy3WCtqvnssaYYTLkIeiAbA3X2mdz+wm/pAbdmbRR6y\nfyBum/9hvxV8K7mcvc0iYnka1Ir1MLW/3lKI1S/o60a6BRdf0N4EZ6O1mc3imLFelgnWz0164la6\nPAxCM8Tc2KzlgnoVaD8P1RQmPDE+UXAUDMBNeeUwxE3xmcqb9b4WHOwfOoqZC05nmPTSRCjG8HX9\nNs4RoLvUweaTxATPnEqc3k3AzBjDT2M+TU/mHwXX2zxH7MMKvm/buz1MaU1ATRCGcjyFOc7k+XbU\nA5jA/SjAsRrRiTYDpkW+WiVnDeIIH7d4/4dJBux/PDM+ECSnA2qysF9dTsWNi6/ZQJZt/lqpJRGW\nY/bga+3Ygpw4D8zUumPwZBwNurLovDyRYs++IJizbsqVole4MUmATKJx+3orJqJUeLtHRDwTaeMz\nQ+sYV+mJVJlmWjVbRfAP/scZam7pHZw799vmHrBsg2MkkGhoFPpqtKjzZWKWleumsP49PU0aftz5\n9TFXOVEoqbT+neQszjtVtEyXImIv5/RHYxaHy0/N/Cmu9aP46HTEFstF3qhb1jdQL+CeRs93wlNV\nHhAq84+TXVRC1Ios6u8r76ptSfHmW6w5YeirCK4Zytc/zyL5y49fwdrf7Y2QQc/bqXTupSZtRbN7\nLCQxNHuttMhclZoCA6ydwIJ3kpr6I2guQcsYmjVdHd5n7HTsWsOeRGex0cqxLSOE2NjtfNtCbZnL\n12lTfavQt3ZB30S3S0aZi7zNY/3DZAyINZY7f/JQYay4u1UK2/cW51xwx53O1VRRC8WwfNZtmXzU\nqRsdxNhPfuEpZ4lWJ3QL5kgrvhYAxHpr8RnV7mLutAKHG6VomwmGNLtf2ZOU6A0B4rVX9KOSnVjz\nguOWjU0DPJVPOrpZI3/jqnAXYdIXrgTr5g0ix/WA1U8bTG9wrfS5dpRIbNZ77Lf2Ns2SsInT6/gA\nPooOtSQVBlO//FIkZseFR9+rQYMI9exoP+Mfk4BK+xesPn3BviQSpVMVsOYbTZdO1rY5EwqgjF38\njJBH/E3ugho3G4m1aEpTvHElT3gmDsKCCruX4PTlbm+3+oL/iIgt5Mc/MSRZTB9lBZ7kGfMoaer5\n0s9V7u1O7nOHM0YWshuzXl4cJsaSr/YI54tcsV3fYuTocAiuGxVLjEQNbhbOCj+9/BOhBUk7GKST\nnYxYtsIuwlHA/mztg7LaFNQSVrdRevWtwGYft361WjZZmpfkMubR2nMEAUP/TpocL3IkMJlKdrsc\nHfUFYdKwARkhRgzMCSEegYlViSLuE+/LUQXA9vzvkXyUTmHK9f2/izfBilwgh1qTXz9vsyyoIfIK\n/4vVEfQsV7eU2qTtNKKJFyLLDYAg+MutzNPFDV1LuR+9ZCDUmkS5Li0sJxQWRENlptXwAfFsCnKy\n8jLaa20DlU7qa+ECZUstS3NJUz3uBdKxpfMg1BM/FWWtR+ucj4J/AvLYSs6cfSiOccK+o2txgUj4\n/eeAsx77F21PGOQEIsRMVbfn3J27jUNMIRkilr+AbONGHtJh42rOSBw3iFQ/HzUj1zai2nU9G7pN\nAkTxRo77SuL3BoDIQd0LJl2fvcU/gWQHo9DElQq7XRpQ9MuxnsD7SrE/AcVtxNkiBaDCIb+UzcxF\nSKDoBNVGjAa8j99zOKiYLQMpenjPAnrA6vCKjC8vQfZPq72VQn9LD0LESo7sqWpULJgZe4ApvYJf\ncRFlL9xWz1hdb4IYK7zGg7jTlHX6/mloqt8V9eoKlEV/aXiIbzOlIlLXm2ujX7a4w3RR5EqnpJ0B\nvvSZIxTfFzu9i5qkax16hBAOfJJwvvJk+y3qDVyW4PrEFc0hCbyhDmfX1YI0cspEbWxR1nOd6hSt\nDO1aW21DA9MZuXhwb5rQoPFvTFvdbs1z+F/Svhl155Urleo2at7f2c/IH9Y9aVx7tMGKLQOAx/5U\ngKUV/+yW4yPPOGsQg7jDoRdt8e6Lml67Vntna+VcaHP8JxI1Nk+JHL1v3RbBKKnAjVIJmYce+V8D\nr/1Gpfya7XK6+4miRsPnSpLy7MO631OB+ZtDk8EvyCSoWRuRekCdnZStcWhElDB3poAsnTRUB+84\nCv6s0yP1zJDd1cZr7fsRPHZqUZGuJMSpCFcvQjIwis01svQgTn1O0G+uQlLpGTWY+pyBJWrzoveG\nlgKc5TOgJYGOiMB3n0zhve3rarw/jOJZlFPfk2oF8Q3iIKQnDcPZ0k354gVky/FOjCF4MBzBjaIa\nk5ctfGf+7vnj7oN0s0cUCjBFiCEWaZt2n1dsNx3YCXj+N2TPXh2imb4GuN24pX3cYQWeOJyOm08A\nBVJy74thKyzaiMD/IFvq5Ns8Z8V184Pve7INLqO90Mwhlh3O1fWOmVO18wzNoEsoT/AVbEJfIP/+\nh9FJz64S9YByUpl+ecibgt+v3+CNcnUX6bJh6YmjD5bFnFphPf0BfiyLT6UKsVnL5/Gs9zNpYdb5\nm6z+m0zX+M1Z6Rlos1ozkfrjBJAVAUWd4IjwFlWmCpzws/oAbPhJCWZpycr1CTw+T0iunLN974RQ\nUebYBoavsrcq2+Qq6JfjDiyLL+MqZkMOJWfg/6mLO0mj32NSIkO4e9IVkWbIaw5Eecld7KL7Imee\niSPtnyiGcsr56auFL5NNj1UASslnTsV0gPbUn7WE0LhLuPkGGJTz3+3rL8g/jYw5EKRB3+rEQD+1\nrXSEAT640uMNC2kehPyYnGeTqc7W9M1o5kT1uh6Z+sycoMmUf5mPpM37cyTJlPZUIj36zTQrT69x\n7HeGxg0Vg+mIj/YCHYRYjfAiM25dw/m5JHTDDrG7/8vh426+qjyp9jgSAtT/TgjsfM0LRXLtUKzU\nMOE3An1K+4VNtUfxOC5wv1Kkit21roVAlWIjAs2EX1/zmPlNCyzwe8lEGuVCJNZOPddqAcn1bN2r\nekEZ9yyd9Yhk/0MWBDtqDdrpo+0xe2fedFlo3Ct6L2WjfBKkBN9n7liABOK4un6BY1N55n+iPe4n\ncrGRrmIE0KDd+e7xnL4qk3yZh20faxBVvuA4N53JaWKaRiqgHKCub2MpZApvW5wWKHk12qm8oB19\nGsMxmS1NJtZNtE8i2zwvjI1d215q2P3t0vDsTrmdF80grpbSgLgo6NgpKvVZMIJa974lLo/AHD+P\nO2AmEHwpR1UxtDJRexkTri33ONTD0lhZzX92Q7PYrHHKer6W4XDdHYqY2oXOapBlWWZjjjvXAEE3\nRlP32/orBoI75uk942+myk3x3ZrBM70uch1r7y05iiqBYC9o/zBB0iCln/FIBBuYxVKP0L9XlHQa\nXxaqZPaR50Zya67t1mWZTK4QwDfRupC5FJwpj/GOxhA0TZTPVIvI/wuW8xEP6oMUwlbwYK9GDdyW\nrtnk5IWhuyPEgTZ6E7GWYjDj0HOczEC6gM70hks8V3/l1AswLI0CVrVQtSSXtTV66CnoFuHrV5sk\nqnYJUJX02rYz/rCMwXu33EBEdJczSEKGW3M9NTbuT+CLHzPCV4CGu5ZlMLF1iIAxMD6CCiF7LTHP\nMPPB0QccI+0mKbfDk/3siahftBIcsvzvfNkLbf/6bry5tANbHlARHDZ8W6Y6n0lXNASxUcGcbdc3\nIAznpLWQEhBx5TB3ywSq9m3yxt/dTWY7MGIKTFo5BfNB/R8YznsGEsvcBl0lQnRA0Jpj6Sk+0ihO\nm0sBJk8xMHubNU36YGiQf0ISfMgD3qGKBMB/a3blfUlW9JFGCYGYNsYZ+dhe1Rtkg4VT7Kw9Lxq2\nvFsI6Fxggsex7o0MP0xOnYPy0FF9E7RJk2AvobjUXIzFbPCE/hh4bIZgdRZZUpkJPPgedD/Dd9QT\npY6n81dnW+YNW41bpNfOzxIwsyWNlR74j4qpxUoV5SxslgGtdB3kFiOS64Z0WU80s83JSoP4jnHm\n9TES+tw/zTESGAA3xk26iLgjDKubcH3eOY20OzDtcxwwFCmbUx9xpGt72fSd8jXN6kccuaodVda/\n7c1ZTLJ9goXq3Rc3Y6jEcxxgtnWhN/LvM6lPOOwuIVBEkEfwkyAyN18m2wRig38PvV5zBGvaAu5J\n5OV3UGXJYkRjSCqBO3yDypU1OmoGghAlZEduruT16l8F4EsPD6H+/I/76/0bCMOrb0iQP+SrxKBE\ntMdl/JmbmPp7+34lqLD9CBRv7jqpw6QN+r+vcYqeqUaUcJgHwhiN0HkFBz18UYeoIZsRsI17Yrq3\ncH+1rBNGCe1o2M9MI6ICJMyGle99JiQslHeB58E3s2DnCVBJ0t5IB8kiluTAzzJIz1mtwnH7vU+3\nRcZ8nFnrbnyRqYOK7OQsEBQgCuWdEnZZDHZlugMxO8ztZa1UcEyowbneeBZqNNwiQ5+FzDdR/tgm\nlmK1swaJ/v4OCX1uq50M9cJLbsfshV2pFSUc/xGMkpyC7C8kj1ZRgaqZwFAOafBFffSqy2fPfz8W\ncogN8ZpB2mFhgfrEOIbgIZ7dmKSWe49T0Ydu3JeHJSx1ENA1X4aPMzr8HZwkqdcRC2hEoRBLmBwZ\nhEGvZQEg/EEs3nghWDY1jAikaPa6vztxPkWQeF8emhM3fn14z7DOHdFNRpKIMYijNLosvsabWbG2\n8Sq+ZA4yaXXPCstHLL25JZJIXXjSiwvkFCgdsLxBmHHympXwNET/HBWYKMjIa3zInPDtzcJFEFnk\nAwHVl7dZ2Y6GfPJtu2plRAB4t5RK6NvwVFVk7CRm0zdyILIEyaUM+no5Nf3xFhvn20lOOpT+poWN\nHppQFK1a3pcWchw59WDN7GOTdVkYxscF2u8Hs8zcu8JwIvhU7Lngzk5XELHOxiienxtA58O7nsPi\nmR+cGXJA4pATVlvCii62gBaplYqx+uQkslR0e4pPSfwXFZw8PQu2OWUztWofg3yQe3VxkZ/K5tGe\nw2MlVm1zeZunH+hC2F/4+tjhnptrBRYX6LuH6NbT7nX91DL78RDTqngYUZKpdzmhuo/g0IDbxdE2\n5uilouPFOeyQMrhtBLHg0AepbddiNW9f4f+f9sTTqmOFxeZ0u/9fu+QKnUwUiVtA6+yBbQY2nRIT\n+cM7WP+k/M9HgaDRaYPGo8zJwut1qy8ea35cnISTZRBhxrLy2IeBn9yNSi4v8cvJ3R38KPlx/EXf\nhtW01Q8NQFB+WddAAkve2dIWMz4/C4qkwngf5FJvRPhrAO9CQDcvO8QOsIrBKtFfgYkQBX1hvF3Y\n+KhpeFqgf7m/dy+4Wt73Qw6uend1HnVsF9zXTbXYw9bEQbskVAPYsXpYSjGbqriev7Yvvq+WoeR9\nxMjtnX8f0QpxqJ2GovVCSuE+BKa/ihk7DjbhJPScLti1TgsMbRKlA/Lu0BIwqJUPLUfX0smZ0N/Z\nHPYMYWCFLC3pzJ6IizX0lqekCAtb8gHwPgnQ1HBzt3C+FMMvWm9JyRLdyXj93yLnsAqEFHI7QJYN\nHM/mv2GM7JPGUJ4IHpijXvh/8GL9VISVTf+G4y6SFc7j4JjMMTDoiJfHPPteYtJx/prGTAR2Ni2v\no3rS2xYoBQZ4KDf4kJL+Zm7esVR+qYzzlRBPjRgTvAM2NPNsRK6mAPI7XwYfIjKAJSsllu3WoXsD\n4+HX1jXKr/7acrte83IPshJugOF2aamnUMhyAEt9lfjSHmoozHOtiRER8IzD0A54JOELnZyRrenC\nw0lnA+YeVdhNRROm8dGFyXfHy+cyHxSDjCvUNAEnu+7Jzd8pRxCIEoDUSPUHafotM4ODJhlufKc4\nxW9pi7w4J66Lb5yMpAkDj7IBIG/evZAB4rOpkmwrP/jvATY7WF3Kc3QwqsXisWKHo2x5hy0XOhqi\ndUPN0biDy2x++atxfkyl8b+rrMo38lxJVE2pWlK7sWQAACMrMUi1Asz8ejYJJFAvnZeo0qPl5c1u\n1Mk3FQHnOT7RXET6dXW5vix0Wa9OsTpRHXfFVaHQITot3JLD4/VMu7i51CwwrFvk0Bguw2e9sEMh\nnJejskYZ7oip1iy35DGa3y6Jfi/acE26M4SP+te5eJtlfOG1no5QfCmanOBk805vxtjO6vI7c+OM\noEZJlx9YLX8Oehs+ksQQDmy/hW4i7N4zKJNabapy2iPw2HOvC71jQOp8EoiFuF6inHFoIHOMhvdb\nkJjz8dPCWoyXduq+DBwoI/DIH+NExV8Ss1R5YTX6OV1EpGNx63oZvGSI6Ae6+GFtQa/BEC6X4Vvb\nYhCN/sKZUDBsbfU0Yjz5TdT9TRe9OaFfS0NlVVb8uQXT7tGjeLDCQNQ42EN0uUAWamGcYXM4c7rP\nyjgXP5pJbU3Tye7gC5wKLgUu51FgAGVXF6NsoqrgJmE2UFr4x4r0QB9Dwdf2eoqtwvtbO7Y3jCNM\n8WYB/WtLTmauPpkodWHpHelfi+USD/U6XrZS9lsT0xclWfx6CCYj13L155vYdSW7EgZVABA94XcL\n8wHflo4ElIQifwHvNPo3LZJnCVTMnVIKD+ihwKp+EhTFHqemWYPhAXk+ZvHrW7mO+PImreqn8uyZ\nbddcbmz+cPHWhhzciFlpRULBvhe8cBxl1NFDomZ4RCsWJFxEkMTFRCciMz+7EEGN+7J2rJwm1+NM\n/ClbLY0trzmB9XdM76xouj+2yGpeROfXjIHXO8mo53stVCqIxPC6p4WgC9rRs8RaJ7iPS7NItFCg\nKfORI3UX04rr6oqVx+iJ2hRd0yi5jtoohfNvvc9dcvCTPgPdLWX1YKPAJi37zYkdRp3azXd5sGZi\nBI9sCU+fE9u3EcLM5tJGTvzRt2fecnanQlqdLkyiFBZSvmrtedKUSdxZxrsGmQ2GPKuEt6pphaky\nZczqiwp7FhqvIyztutYbIUiJ2+10axM9r6IuU7UZCfgjAb+qy4QmkuSegjfmqJZOxKj0esOjZJMD\npqdG9pZsUG0/PVG/u/nTqa+BuiFJWDF1HPVW6PyDithrNerVG5NyTfc9yphzo6f2D71TEQNSsQAr\n8Vn4UxDIYE1ELRXLPwNMk6LIBx3E4U9uDTMo596yxY+seffCkPuBpkySbceQgB4feoOrnCBM47qy\nQl3tRE7gX8HeqS40FROh02xI4FH3ZNMJDWb/78YtY3FCBUpa26mDaNGbBkyZ7E9hLpQJlut2qu62\nn+UnQqqNNXlq9Dw7N9T+EMX2oIrGL0U2Q8X4BetOzY9CWcNPF14wrOKXfIeCV/G41ZCqQYKmrFTn\nllr3TUlksflpFUmkVvFXsBSGcEc/ebezmAHPzh4o5GfI1p7LMe6zQWar7gucfBFENER+3ENjoa3E\nEgqkXpygxr9CwpLqD8yp0F7p1lM5ajlK7tvpJNoD1/QzL0cWFwCe9QIyNUc6sbBXbBGjgzFyOP3w\n6wS8i4Ob0qoFCLWDa5cmxxB5Pk903V4rCQdC7+ZBUKzu8mGeQU3m5qeuWhHCw2bn0nxRCSuH0HjU\nB4f31OLHXa8eV6VTYLBjYHoZbRamC705ZcxNT9cngSlA7hwT4XU9ClGOw1s+IIf3OOes+8rbHe7l\nV4Styg2hR1WciEP0azKUJdUUKepsafr9uZvZqY0ust8ahMAi2R8ttyw98FIvyL2Y2PPRNaYuaam7\nfPk7ZeC6HJ97l42nMTrrMr8HHMeniW+QMgz8uC01m7NYDYeY4tCSRffti0+Xlx7WAcscXlHkoLPq\nmeFv1W9Jurxqr+1KzBdVeo5zbkZLaLQLgcGtXdXCvkWtThpRKwO/Y09K3vXzXokndmt6IIx1kLJl\nEclccE7E2F/t6mNTxuJ+jaVi1UTlfgydLKpUTl1J54LB+1RNNHRrqSX7jkQfGu945pmsQWeiIUO0\nPNLtveV2vHoOEvGUHUv9R2EJ1qh44ufxko2ipVLlRllhiKlF3/vIPS3SOY0/YR9Cd5DwrtkblAU8\nkcg2xVa/aaXtHLAoJhb/yj6eOmjccOqnKKeafhTzTGNf9sV5XU2kg3kyikfZOylKqzMI9K/5qY9s\ns0ms47ABJcd8jxXzNxoqhQ9DmVq0X6DSskjwGnvdx/SywkL73gyg4IdiCpv26cJCqsJQ7CqD4gbL\n2HijxA21uaEVJdVZU8Nj8hRgkIPe3XeZuhsPWWlFGY9v+qzmiwU0uAzqgsOAvOg1vxCWFveM2UG9\n4AgRv5Gs8FzkDyKzSSDTdlnXIFMwbi2L1Bu3tP6h6kfqbeuB6jRP7t4nktgUKOub3GgbJFpjOMXC\ncXO3yX1ybh96rGo6fGAppJckiiXQ4GlZeoGGz8Tmz0YRPHxGu5wLBwN4Yc6KNv5hlJ7dIHfFA3dS\n9+VV2E8kkYhNK0fcXkijcLAMQjVcD5EtFpNkblaKxUrWC6UkqP8AzRRoWLTOlQAFBH0esRmSPZhj\nHuY+nVDJm/Kvlkwfrikb4aaLf+2pu1SCN+bUR+vewYrR5W90xYQqxDEub8hrvIeAMgpgj5KuZK8k\nAOg3hEj9d+jP5WpjeeyKkoT0APQEOwsH1EoMNJq0mNWbrhyQ3sJlKFFG17HTlcV3RxW7GvUvLyf5\nNYoEt6x/W1UqsAlJ+P5bAM0j1zAQ25zokUSwuXe+UOO23irRqD78Hru+xmt6HJSxoko5USnAG1t8\nwdbrqbJc8HQwr5+3lKLMpHWsE17+AMYoFgl2d4HLH5SLIpWb1+K4P5OQUzm+ezKk2RnFDLIpy7M8\ntfG4vxj5+OaFzwhggPwsbRmeZbLi81ku3FBqNNl/NZhW2+vsa7pL87MI9d1qLrZWcuAbcarFXLEc\n/Se/Q2lv3I5G7Xj1wDdRjPW0WBY5/CIhhL0tYKzXINXGEu66nP5xozdOEYOwJZEP61W0YeBVBkAv\nMgWch1E5W7z++yZKivsYcQu/UlZgJ/qiwjrcTqPd0LV7lqCAp1fmBNCtMS7aZW+KAZK4KoMQgVk7\nXFycz2L6FH+q+voM+2lrtCVapH4xvuTz1PRcsgurynKKGwlOOPMzw4bslqHOv8td/RTm4MVSYYGh\nYjeC/Y+qvPlFBvqTiAd8lol/FJBsAF2W70/qhj1B832tHha0KWu/ZPWvEiRchlihTRoulFFH/tXk\nudYA/Vd3WtkYnHQfzYBQqn7rtelZ5z/RJ7xNSNe6wuHml88eJPaQ8tquI/Kld2Xg7nIIjDsdujxI\n127txMjvoXUZXkTQARuRLemr/XvRndodl8LSpTMktCfDr+t14oVLAf9OZy6zi29LuzjF8kIZIXLu\nGjlKcWtJVtnTCH8QRS0jNWBuMw2yTe3lBgo6lnu6fYNtWY9F5RPuJGnIeNCbkQ0iHYiDIE+EkcB7\nD8M0y/xJzSZ+0fKrPcJHRN2c8BHXBDyiteVlmotjfFGdv4Zr+708uls0ekvIeeirtQY5SfmIVqKN\nnt57IYoBFYcP8EcnJUW/EH/NamsfWyX8dxcGjLkJnE8dyNPtwG/zaNxtD7UfTjS5RBWJe6WdYn/x\nOgInPzv/NvYd6zu65Xdj4ZQ+QkPhlBzRTg5Hbbk2acCxQ4OEVpZvQ8DoApwc+dxwWlJeVnlEl44o\nsZ868sQ0L2WcuNUmtu5uWvpBH2WYXjGIcfAlTmntYnFtL6TnqnwrFJ4fHkXf7Z6amrTjTjz6ZCiU\nD7g/NJCyu6Z0nvrWGAn2Lu/wjUPms2q0kQYvE2gh1LVdvCRODOxcsLcR+G2/kY3NDj+PsZ7j7Gtn\nU/lisvg2jq247EEZhrAMcaFsGYaLuFB56ummjUEuqswP5heBtn9b07bXuHBZ/XrtYzQdusm3gd9P\ndrJRzkNiD8F3aKF2Dll3a9rI0mz3QNjHPeNJeLVUtCldl7FwunPWvAM7GgZJ07oOcFGKHmeqaHON\nOB+/QAZNB+xRObwzQrKbYajNWdRhO0aGJ+zF3inshLmpxMsTSZWOwE/Hz/JIJMSdgmAaitgNEK+O\nFDxLqcrVI0I1Rm+csPihXYZJ+6UjyRZZuO3Nl6/npeZYnX4PpRpRcw4iLfKQDCgqH+7wgKn76vn/\n00uJd4X9Twc9+dOFVdtYJKeiocp/rvkl/UXQA3cZsXVAld0JgVaFW9RQRuFpZFmG8oCaoymB7Wkw\nExfxkTOPTSKa6LJbzlgFx1A4WoYv71EIzJRuTL8fg8Ak7Q0vvN1ya+BpTq2MKlyHgQPL4e2Ev2Cu\nW7ytPHrw6I569+N2vXlmRQncWQuUXWQ5HeL2XxS9cU/d3df2TRfjG2KF4BEgKv/Hs1M72nOMcYyo\n4vVwhaJBQwb0/OF77cjGlR7iYM23C1DNoOGDFxBRIY52BBlns4IyXkOJv/DT+uMtQR5j9ZajuF4D\nZxR7Fdfo49ZrD7VjWPx/WWEUdDvFQ1b5HfqkwiZHiyk6iCCQ9crrebMefM/rDSl5265mnLcG/Ph7\ngMI8keUofVCTud4stYX/4bTIPUbDYCJbJAP9jHWs/sT/+4SEPphQj1qPig4B2nKeLcOQQxQKYAw8\nyXZRaho91dUgSZTlUWfssf7XsamkeBNLd9Qw1zkgZ9Hk0ALcLu2vv7Bsrw2ca3IC55Xh0oF14mn8\nuQzes3pJWMqI7E8pnDsvGJDW9rVEAHKKeSXkUO9cWkwCZXj3/yOXO0J0s8TxeIoG9yCbSW/wY2F8\nu6J9U5vnmOQdd8l2jFLuXwlggzIJGEp+FWRi6AifhbjaLP8Zb8lnwFrMw31oFMFQXp+/mSOYuS0i\n2Y1FFq9EVTW5z7JymkxeP0vv3x0Qbqv4WqNP5yCvEUNSpo/Da2+ZOUsiaDdGDW71w5d6YfORcQtr\nYiv/qgnItyHEA//dafhYDet3eGi0Ho+vL1I9f6EdYkhd8L4BYk93+J8QQksMhJKhecGXwEMi7a3A\nXZPAHEWLWMYo1/lEoeMJG+vmzMyLEr0bv54r38CJKc2C1hjhpP2kN0fsfM7lJxNQZBFEtUQ6AlHm\nuB3xDoB0uSP81ny/HYfE6xOKg7EufRSpn4SbX1gxCpy8URICBRN/z8mlpUhZwb/wVQsO12bR3L0n\nob3hN66URK/K0CoKlLDjOQsbHiebydVju/u+HE9xijAmKmTU2GWupTbvc3QxQhvnymXC2HYre/5h\nvhDgbRXrfBc/X+so384+l78zFag4TaemfENJJM6xKJUUel+UgHHI2A9sbQrMStCi/UEOWJAvx56J\nShXrAeAwnMJzGt5GIFZ3OVz26eeLPIQ/O3REFv3uZkTfac9BKuW3rtIxdyv7Nj3Mq+QBQtHAgCod\nVqwYQZza8g2AtMdsfZkHGlPUbA9k5NMM4XqJuPobDL+puIl/QSvdj4OLy6EMSpt0QBh+/TO8mns/\nOJ5V6/BOmtfJ3zgObfsWIcjNF/sEQMSBEk1UwOeQdCj0MtqGuRsYcSpa1JKlJDV7uZCnnYxb0InQ\nRhmmGmNw1aLxaE2EwS3/bQ+gwyaI8HN2tEW6NPsUlwi9VgbGEC8NNmPHDud443MfZaIZQlySGLbI\n/iPUbKGj2fHSjA+932PD3NjMq4+DgFK1xh0r2mgUMfEABjyFSel+yamJMbsO5pUYDEv2fqxJFOPA\niaHWqfBUCUgCh0vxPo15jGRBJ11BaWQrIIUy4JoBe2xwDSWXBeOhcHqb3YcXAHJU4BT3/kbAlBIe\nAhaI4HP0LDLv0N7bRGkv3wIvhtKXZ6re82BfKQ+b4PulY5k3rdeiBR9tJesZ+KpIWIq7kK9d2YwW\n4fKfgq4Pnq36v9ndMkTdPAbdBkasWsvLazmZCMJydaw4UVeRR8yLhpHq4Al4nqRmIVdkBflSvpsQ\nbyB+mMoLmLxm3fOofQDYHBXRF9d22tDAr4Cel3Y2TeM2ngeDZPqwok+jXKVsQBjTLlStJrZS/joR\nysdZtRWzd+Y9xIny1yp8ZNf7rnqCF1ogm6aLImzVEpWD0dFGk4yBWnfxGJN4WX8TCEzvyinDeCto\nxKtdndzpBmy0NAt8mU/QNqQnqdbJnUrcMSdJF7dNa24UFdtSOzknsrEhAhIGAr5RqvAP7RuIa0IB\na6xpJvq9X2JPFA/zmevXyfsJNcAIU0wY8ETz9yCoLmX36kdM1eEVQdJWomHliO525dzITzfUpQmp\n5hLJpgNxOPgnJ1R1wYTH16uMYENdwYCasW6xs1TrY5lbe/vyMCsz0Gqn2P8fCNsv00KhqYrIFvCc\nqImIN8i0U9JAIYqpUYKtA0b8Er4+9VFi7bUBeS/9b1r6aDkIhzsE/xS692HR9aNzhMzpJbYI77O1\nDXQQF5j2HwoeZQsZo35Tb5viIFbMis5cGEa9TvEje0x7SU1zW++wWaO3bTzHcpDXRTiLktkoaNQc\n2dkmU+iTp3Km5HFYdwhrSSdPzmH+NDJISNB/PzMugifD27p7SFVFmtZYjk9kxfozA0HGeyGi0vOH\nrZ5h/4tnYlY8+99IdaYNRihOElOn+z4fMOOo7k1+Rtk0DhO611DL4X541SxlOLw3snj3eCs+gF/m\n0+g/YsRF52yqQtpASTWT9GuALOO5aodJ43Y2PHuAp+eUAg9lYmCC4wrN7FHTfMTp+MlSQdxeX8WM\n5l5lawHFRozNdDuYlB+wJoi8ZhSyxGijwNQ+XsTPM+0NxDVsLjq2SAJk2SjbI0N+DpclooH1MVRW\nc5stMCOeejDPZsPxT8Oec9tHrmdSf9C9Y5kLbY0GYSwK2ANdqRRP9ovqzADl1EYTa7ZFYTdLl7oF\nwxAnQHenXynHiBa0dsjbUp2O0l1J2TZtb64EMObg1xUXhAtrrqU4p8+/u7LgiuUo4vXnJvHg8J/t\nwwqWkJq7uxceG7yKtC9co5h08YaICLiAdoSQfTUJGCGeNB/DLQSUkC4XkkF4i128iodOkBvghaqe\nIhJYw02sDaGcjENSZf7ogAwNAMezxhFIKwiFlIGcKXVFt+BP6odZkL985cfD/MmYRfidMInlze+i\nk5gDGqRtFCYYGEKdmoNQJeqfP1qR1Q53J2aGDswFxFxKUdCm5Rl+s+YYudGr+pRBhZfxEOmI6yyF\nhEe9dTnlRvyLgmi7Fm+x0jy7UmOuXJhnlfaVQnLnoNGO0igHglCwL02NnpQ8OWT7ykHSr8uDrgZH\nTAmlkbqQUT6VWHXs4avtuSBQmPPpcgK9upNPhN9mortCCx6JQXvB3EooXD/PL9ZGe9UA6ZbX+214\nnoNzebuTrDuEZ+sICo7AsCw6534qf2VjDgI6eprwX4imFwilZatzuc7NIceSySRvgpg1p1s3Tr1p\nVcGXm2ReYM2mBEZF4A7CdkuoCYAo/46a4CDWmRV5HSu5efQSW0tGGgd3Dv6Y0LNOdCHbGdRKlSz4\nX0ld0Z/tLtVpAy8/2gKbRGvh4VcWgfA/90gDgRgjQgJWPhcJGk+soWEdaW+a3D+IATkoe34kfHLw\nyk1Tq06tL12TVvpiZfWh2Gj6nT0meXFlR+/N5pTwvITII+OrWl77fHwNiRUY4vO2NoBRQvGYV/Xz\nDmtWQfBXjn8RfxL0h6PWUz7oTvT+JkoXNNjqxv9oixmasVUbMka/lLy7VwGcn7iJUSfqMcDouEzS\nHQHu8fprk8YpFcVQqeAz/8wxGzcyQeKvFqU1AVWhrqbvALpQ6xRo3joiw5QPFMfD9nU3xJnLYAHw\nP1763Odb87qjcvLABfMLEKnCDSenrmQjn7ADXuTINjwQ63cW3gc3VTvu9q24wIsIOhssxKp48kCH\niy8R3Xv1zmx2wiszcwlaz5OzHGg1o60mKOMN7ZvXT1uMdTvEZ4GrA8yz1hiEyzftYK3FXRMa96rs\nuaCK1qG61Yr4pfqvgyPPahDfw8nBf9EBcGvDA+h0pP/Lt68C5lwA+tYLIsKJjDm52T0QRtSnWe0w\nCqeHk7zFY8sH4qQ5TCbgA9fXL+2auqPTAY4uj/ib0fat6e2nnhabFs5ivNzioBjmBy4jzEKzFfBY\ncA2zvRlo1vhlsdylZKRE0ug16CGjIHTAR6UxJl78ccETg64GMVDJoVMadKVULIxr2tvHRRjuuWXA\nAm9QcJ6aHA+2Q/1hdu4x+9mB/b7mPTXBSSuVNdbnN4vPFe8QuP8RDPDszIJCB9COVDAKeTa8nMn+\nbDjgxUuQjhUHTfK95be+iNcOnct9R+NSc/fmz6ojVaEv0+ZW3mDZk6/NTfgy3JJn28xF+WMdLIoF\n19xCUUtKTrSHaOsR1NS/wsiCqrrQQRxjtEGwTmPJJcEfT2/AvZkbkZQJynoVVBJ1jTs26tj4wLxT\njYtS4jXUtsZld5F/QbVwQYgVpig+WlT4yXXHfMaIhVYRWuJ5wuqpo+iY+Y7mWAJc3qUTvEM2BBwS\n4AQ+ICG9jXwWa2jX7CdCDygPOOEQ4/9NSBVNiX9LLF4MPdsLkmFzVSJac2sYcXzuhuxfRx7iTd5+\nFDuUFToAfEw5bs79slTTWhKOnz1ds/5bYgrfkLnap3LlZkazcHy5rsIGT9eu6Yu1yw/I1ApIGFtM\nttnjIxlS7nYk8jpH5PIcvJROWZA4WveqZBc0V7kSmcyOLClyr3gEnLiZhAFInuftiCwUBKuGWy3V\nnYDGCVEJoBjcxy4wXDWgcvuadX9zLX5rYpCqzLtxlwYXMTuUdzOtdYBeqkFO7Cf6MZv5HMiQfX2q\nTQ68RJz/CjEHtuAqMl40aD6Y3R31e58hWYTWdgbzGtOlWTeQPZB3dUBVwOodhlJ7Qm81xOQPviIj\nClcES1K/V7NLE7hMPE0tBgRlFOmDDIHZKrkUwFssTV83DXCnfbST0q3YrdFMycqMln+zauH6O0UP\nSdb7hIx6WhL6GMiq7xEI5ruVcZmhzJYiIjaPARbV9plqIj7aRNHr0ieYHM7VpVOjGSCPnSnnidBa\nzwD8zLwCt94csMDcFHdeIiMVRE8Q34OkmIWukv9bor5pfZoqGrN/ibVx+Va7V97KPpM6hgEOnw+8\nKKQYpJm4JtSUUZKM6nQ32tDOwYrHmnwzpYIxfaxu5IBp+iycRgLkA0D0ejhBhqE45OGxrjnta6qm\nxE0bL1nUI6f/0t3vyl6s7NEX4OWo5WKO7tDX1MAGW64Duqo0cDwAdPUAC/1yqvesFj7U2N01OuGr\n14a8W3euE1jzgO4VpdAWrfdJ2nT5eMqlouQ2KzCAGiUfB4CypdZWcIU1G7MThbyF23u/dvrJQweN\ngC/OxVbP2yndpSCfvMf2AzwCjq35Jdl4bvZ1DmfXfqM/kriN/wG5OMQvzRYnDZ5qviCouwXA4zET\nqrkgBv/ZdXhU5ahrSA0nWAe/hbvtsq9ogCoc8JBM5If6bQk/KXgNFZVO/1rR5mjsLJFB9i5QSi4J\nFn+uI2v63XuJw+3TEfJr4dOaoCcaxCpAFj1AuDezgwRm6S9IvKhLl9hEhXkUUbMM0UCPtEuPL7cH\nqwXhYuOH/VzaQAnsia4kEmkdm8wc8G1ObaRHdLifcIQjMFc0vBcMR1bHYELQ4UPx4jmyTqyGZ8Os\npFwDNYnL91QrF/jXwLzpOZ+J6+cAmZLDxbtel++Cs8L3p6Hyg3RrnJNotATgJejHH+eOFDGre4Oh\nHixuyTOXPR1DDAw27uoUfSVyt9hZJfEIiCDkoh0Z0lOrEvOdiqCqiqe+xGkGRBNF3HYuMcB6B8fd\nkrr6KYJte+HQkEPDliQ5HxKoROG3Od0V0cNQOhugFYlPCwkfJhKK9+skPsdN5bOK2Kg0mDpHHylD\njyG+B8T745AvI6aN9ipM+gHQXPvi6vdXJ2xJhHZDZwOEZ6aM4q/Z0dJW8q/zNT8C6nCKOuzCHc7H\nGCYOpJbdOvnybXWpE9GpADPZv9hxLoPX1/NcGx52H+khxwyIF9kqtb2DRh6PN0bcvhh1wb4JEUVs\nzm8pMq/cQ4Hxg3x8b6r7VPylx4CkkXkJSmNKoC13xOS1OXjCYAeHxWXzBHXM2Hc1t8x702unGXtR\nwLg/n9YFnsX1urzgr2JJcEvUZKsuV/6X/b8syzoIgaQnTYiSHYmXJLxeCSPHiC3wh/n+a8Kl/bLE\nnQ6YgDDzZk/tqbfe2a4hgko77ykFpypjp3kab8QQIAhKGPl75eLmxELBK3R0AKA0UXX8tEKEWkPO\nFZkSE+ALAdM3ZxeMQdH1pzlyqhYvfaFcxF98Bd2Doc6luQH+yJjsws8h8YJIZfje5zjaS6d/ADyo\n5yQQtYcoYR8UVd+vurV6q35Ns5mDzZhRhjxTHsHzd/lgNPjeGgwwz5O4dsUJECOcw10rSuFb7zUR\n7Z9USLiylG5WmNDz49vh2dC8gQGIEdeHagHhgpy43lY1pq5rwKOkGioq4W8yqE+DgLi61SnIV4Op\nSHuGEGCfzfRbdwdf7iUWemCNhT4Zm2B04RWbQMJxJX1oTL57P1RzxnxMTTZ5PgNLA9VyzuB+mBqp\n/fkYTKncHdcFMTBlr5h9NKTeMjxPBk9DwDFgRT8pUoJGAFqIOCJTEyzPCs4XeAmV9JKDEZfEf2Vf\nwa9/cqqiUrC6YgNUEQVvNxrHrRnTPBUUJ0s0g8GBM2DItO7x77yMFdswgglfnXLxtPpAre60inPd\ncVX909+ltGmx1lw3rzEJkT2vu8RpWNGSHk51RBaFo+c/e1Hf1Oz8v+WvkjUx0mMpgVEDxdue41tA\nmDg+l9FEDl8xfS2lUeoHqf/68H+58VDLlTikAIAhYkZtOE8qHCLpQRnQfuCrI2VF/Q2iMZfNcti9\nxKCN3zr9UR5+A8P18Z6k9inTUJWDH1gL9eMuMemvEuoI1UjdyqCoKS9fO2bzj5lmdQZLTAfLR+ZG\nssa2oUkDq+43O3jr2cEYbhejsJ+RQ1+b9A7RN0k18h1tf7SqwaLO5OQNGe/R3Ha62x9ypQUiXFsB\nVqqsWjayWu8bTFYvjetZVoiw9iwZqK4Tp6qkDzYCmCbUqRf+8+VjpPiLwMPhlYGVII0Ne6uo/BSP\nZymCeNs4WappRKAWBr5gdmT/x16CJNS9weDnLgLPf48x4XkpwqHq3wl59ndcsKKmKdi1SBKm+ccb\nDYpuKQhGTseOUw6HBu1bkKC+vgPAD3obm81kkTwrLXSSVv0NLM/0eImoM7ApisOExAWRk6rqbqjD\nIJyGPy+pmlgA8W2QBl4KRXrTZAfEhE+RdE5ZOQF5F+qeaES+xKgHMWUTQZApcHbSZLu875mHneSd\nYUd2BfmrIGoxs5pDDBUzULhmRQZq7vailhFa8dbyfbUtKSLzPWxcxAtRgAEPzxqNvAiOpa8xoSbI\nbCcrtcfOFhAGZwCuzilDioua3+kTZFR4OH57nfJO1qIcsK2TQ1BK5I3FB/ImNTRpRuFqBZFUJYiB\nRDsq0nc88vaI13Km0XUq8isYRyw3omqy8TxUJLneB2ZbxoyZ13WokGpOAOAqdK+3VCsRQv8bmzm4\nV2s0kl52e1WltTiYJIDhuRqW0riwECH0Pk3dyM9eA7O9iEJeWyuHUQc46GYeikE7PPXMWe18y0bo\nozMGdq153GNKeKqlWsocyI924rODlpIb6YkU+F+X4n++0ecUy4PVjBZkphTtPXfBjloyJ8mWMSMu\n4RyOHdX49mzUIizlJn2Ab7cgxpZ84qUFcGSFnOodLX8m+JXW9TzM9xYll/JSi1u+PGHmU28jq/B3\nyJSXY7wkrxLDzx7z5VF5FnPymS2SnYfIiEnO5lXa0RkKhgYdKWoy3zvETHewpsp7Ikv8TTRmJkQX\nt275f59ihHqCZenMrWM+qb3sQbPXAolNNkIJupPgTB5NMvynoJIeOkR6XzmBdzCF2X7P9isyLMKH\nStu8c/a9+gnPR4nrFhnffJ8lQnHgZXLLtpkLzoUID5OmamiThK3IP/ONLRNkJe4gsbOQ6bw7cpPV\njfGP+rLvLFsb5tKqQD4W/rkAnLWa7aSmCFglYo5G0y8feeXcuHl1xmBuK+pfJbBfGbsncnJIrmCc\nQGILkYr/N/CPi/gddqNlRiiGALEwlqaTx17AKZBANZjxMJUDvS1ZW2rFYkvkUV5kXkYVwcqND9ZZ\nHtFIMKuVDFG5VMkqofxytZLstr/xIDO2uc58iz7HIIYZgeStmrYRdc8R+hFXU7mFTYlnRDkWspd0\noWuBczw2VYRinqjjCY9boA95euq4OLKtepBP1FhoVn4tNprrAlCbrnGKws0cmXU8YD8gUqDK7KUA\npHPnzMM3XKozqb6GIJO2emf5iW+XUle7+DYX/H+GdUtsUGeaTEsSYiMBvvt6XQf/fd1xgngqdxAg\nTzbEcBQEf8REVr5RhYmv6XNlQn0i287y35lZd5um9TbhAzozkfFXgpBfCBF7LFF3I0OqRvSbz2CQ\nGqVx8RVc0A0I4SHR+xb6R+e9phWaNvDkJedK+oObtJNFcq1hNqCR7yNkQtLH747DsxgBP59VUIrh\nDAuV/eUolz3rbwuVkXgVStv+fvIa4eNscV78KOUIGV2Dn/bZehBQ6gB4UD8efL+JV1XU0hfNtX/t\nQYMXroUHkORqvU549kzGDSlkAWRrP0htgIujiLmzIlV6hplFDmqMKqDl7ZdAldyj/lGOLe6vW8Xq\nNvdpZzMVjqoPGn44ga9tUJiVL0Q6muPuj2QdGgYMk7gaj2VIWle05coLDXfEdQ38Zlqk6HcWX+Mt\njN7yODDM6BhruTaXAAsh0wRWNz4ivh94K79km8moZAz5NLyySCMBvtCQ7Fte3o6N3s262gZSjfxv\naqqsfQH69aG8nyk9xD8O6bkJATssKMLlgCdKKWGXXmuhxV8sqSiVfhDy6BnXMitCxWiphc8lsTAd\nBbU+qy+8edu2CdTUn4xQtEwIZrMPNZ5Shob+DJQI1ZwLc+w77Zqg/ypr7LW8ulliv9TajUbINFHk\nLGVZvuY5jYn9RvkgyQ3hSA3nE7vHjoByOZTe4bXYcUZG34paZiNO5LDn/qnWNsFEoTjVT6BomziD\nnfGBC4jZ7H3B14t+JeziYx7XKnUo3xA9mllUCm8bUOF+rPFcFgWkgOcWL9fICsYgdi/HEcqvugvU\nSrhC51IG9UjrmCkBP3e/RNZJ6Wbbd+mZZxOKRCuOSeAFdz2k2HkzQZ6XQNLBHfnsImEV8u1MU6sQ\nFhSVPyJEdkQ1nvopyRED5AaqICFuPLw6E2OahwHfiKiEk8V6Di2PLytH56QDeCvvnY0xpyqOqGKR\nq2ChmCtcNgbTz79fl/xlcR18cGzfGI/d13tzYPm1NMAq9jZ109IEtTTYou0K2C60hN0cnQrkq8BU\nmQ847vAtkaAVFIji4PNPQwwJgF2W3RuvmC9U+NGvt2WtYr4wcahOI7bO6X6Tqyp8NekDFbEDGcnR\nd/AZmkJRtquEdGCaq2QRhLKMI5tnigw/2DITRPk/u/0GAgV1rdX2D0aAx0/vgPAoC7x8d+d3udM+\nxc3mjdQZ5LLVt+KpxLZuuNsaY8LQbIgGzPIBiMYUhxhPbHtlsUT4jtNyz91HNuu0LYDWsxz5iBz6\nu5ivTMG3xsh2c0nfB8eumNMYtZL6ST7SqVL1bD4IhVorsRGqMawReIlCUtYm+UPHs6IFTQ6xlTR9\nOePCEgzLOx3XTnJmNHx+umbk+noovAdFiBHYnbxIn0Ns9ITyaV64BY+pYSV/JkoGwlckeThTrRjd\nimInLKL/e1HAAVYwxJTsB/OBzmajXMwD3WMfbOCHFGczBp3/pm2kyfxDJlPbPMmcAkY8jHwJpGpH\nkkGiJjvorJF59C/NNkLeci2ZPmdEtlO1vOCPiXkhcLgWIgbK4C5eTjU4EpVZGUkDuVoWyEi+TEbc\n6BWqcUfrZKZOiT3woVESXIx8opzRHY9+Miv0OwYW2Gn2s4/LmM/zPWuf7PWAIcCJBulzuTNgmRAP\noCbOdnCiOxbVAGpa+f1Cc3/pgROo1lS8QyKHpBT7g9+8IzlUiiYCHZQ6dPWUusafe+VN7skP+Pla\nFQLmtgDUDKCRXbUTo03tyymUOd4OPd607/vR/afhmj/s4GsfRIShYH/BpRMkdrdHQJi+w4AeLNxm\njdWiVHsMHc6wR4nh8f2B/KzbAxGYq+CgVIOKxvajhuyJ2q68r96jAP6HMB+RVhgah2X3b1p0LKkg\n73WWeqhSGmWN27v6MpXJonJXEWBntbkblU/EyK8ykHiCPLC+AuQ6aqdsD9u9rCH7nHSTaXl8RCq+\njUboqkl61vay+uWx33p2gjLtBrOeO0hHVjfPQwXJMhc+frL+npXikeAerGNrH1HhoalilTwy+Tn/\n7UeV5F7krVXS5kLWsNYazdXHcpe64fsqrbV84uGokK35u7Xg0ILcPYtq5SmVyHfiqCdpr2KPBu7c\nkx6cWh2VgWQwOWbSkIjUv9lhNR7G5/zcQRpOh14OqmcOYPFywB+4xV3y7YmoNNdDG9sICgtMkfuZ\nBqgHsRGct8RS3VzC1vJXJaBMddOE9+owiUHEK6JyP3+iYD9KZyaBpCZuKzQ46XvgjrErHtoDT0Qv\nFK7gXRhkl8jduOdMbJR5v+btkUHuhD1CLtGUoZRN9cbgKXISTx9f/k8giIMyYOBxzFXyYNxynqra\n0EdYpW2BMLIkXL3Yw9j6sVomq5ielosZfbuhANHYxxqDPOOgcdm0DA2gcyQPF2wTBApMOJ+iFs9H\nn8FhVA6Za6vDlDHHzz72aZPrI9bJZ+nyBpykECINv0uSNBCgPxgc8bzzivt0mXW8bpPY+G9c0wLL\n/YkfoCO3wik+0YzacIsHc2H9JewsBNo6czS23WeMGxpqe+23ESF63zjrkQWbWMttXunnFMovjsd+\nG6duogY1uoIh0eymJWx1vyFDFHHck+NkBhLMsm0i+QZAkbkn070VuBR0b+OS3bWa1PrNmNiXgT6x\nDPqwa6YuLFCgTwKJ8yo8oEW1AClBKOW77mjjB1uu76EFhxsx3LnVB+wcL8Liw68v7VGsNrSsQJWl\nVGQMXCNrIRI7sbqeuRpqAkaOFQ6GtMMshADNRchN04U+2EQE2MC85S5yeI1P0syzNxaeyHsNJ4V+\nUpCv+4Te9uV4jKPfHNUh479fKwmEw/bZhxMD/BKGeAoLpERwzBwbVFVwsz5DqW99CmUiBsiLJJzM\nTe0UFPAaDNK0nY7pEc6fE1I0UHOaO4puXT7KxpIGREtUpWc8YyTKPdj0YkejYO+Tqj4JKhIUcLjD\na6mYnAEa4YcCwAF07ZCBaz5wYWF8yVHnAGL9sIhb0A3AeMFCnIjRb3pqcK2gXb8DvYA0QMclRRMZ\n7WTzGTGJ3RScZ/s7Roq4wUoBp/CmA/3g6n1LNzC4s3/g/iRca3cl0gPqP1W3DuzmvR1pgXcdaIQF\nuy18OpgcaUC6RfssvZJPzsMZ62hCXw0sJR0O3Q6MYdZh+xZFNI7gZXYZ286Eccc+XJzmJPSFusKT\nNZRMrdmPVrVH18SE95VA9IEmu/fy35KNGYRnTOUHERSLKeYWIb2ciPz1uSu0J+2LO0T68jsaa2YA\n7zpvLMKPW8gqtM8DOjjPqfbMtzxSPBer2zOvSXSFmwX75l6BoWKVxPvuVziJLxxvFJeNs43idNz3\nmp/H8r0tGZwEhgGY7IFOrAitUtiQtE6tl6yQFzvZ9ZZHkLASlHWnETdByjaQrgpXN543SC8Gqs7C\nJxrPxNEL+M5AFsYR04A9FtdQvXZgnxhv5pxOA6BAbRwbmNxBnATGhZInJZE1EJAdHRWJDU1MRCBE\nB1kQmpyBetANT4g5OctukHdXU5GgxyrecmrZjT0wqi29zEuwHPniyX93NCQEct49bej/dDJWW4Dd\nmh5/naleX+tZNIzXr/6+uM8EXlPBblDSVwzY0hYbs0P9NzAxn4cybmkRw+uQljfg+P/SKgWlMvXi\nrU32HVgoAqXobjcfWh8HLYuziPo5xYHBl5M3RKQunBOSI+Lzsde0DinRGePYd16ODpIM3iwgO4yP\nRQ28+CXyu/3nubPcbuv7ERQtbzZH8y0hx0Tuu0DufT4CIDwz6hHCST/MmVODwDYTizd31d7MOshC\n55JW7qWvv/FnrXPdYlQ8yU7+IDFnbXzzHtUb4tbt2ZBGyvoiNcjeamnBTEy8W/z0KpWv8OaVSamG\nQo6q9brFwVzF91GYxhyqSjemx0x139ZdEJeAEWn3iUEHEEFrRyXuRkuO34xzkflj1+fgrXs9eJmu\nMS1drLs9XqBXQG3jy3kUfImE82Ltlwm41I8tf3bf1z3LOA0lSoa7n3fiW4xYReXOWapFPIP3FfLu\noLItAQeNr2wKrNsSGH1if4lNEx5sikoHrfgn/TpfxXTisOmI4VAs045JHWbXYBkUFLqa7VJvM+5S\nimKHJlKGiNVUeerNw8mrGmXa+xzuzfjZjp0M+cwJhOt+ey5z6E8zPjop9RoET1FAUpycE1fxK5Cy\n32m1rs12MKwZZm4+alQd8egaRsyKDmy+4NuHYeri83srEYXC37bukW/yWct59M+ijNqxYXC8Lf4N\neWdyGp7ToG4/t/QsZioy+ClOd06DLpDd4i79+5lZB/tVB60aTueoSJzQzvCvP7CX4egi1d75i59s\nJKDQ5bvVCKU+2yJdq49KQAywTqmFn80h3KaU49OGPIlcAKm5A9kI4BptR4oSnVZqOdn3NHeRFB1D\nvhl/aoMBaVZC9kRgENAfrxmYcqrbAGL+G698jXgFIV7qgxNKeOoPYnBbllfWdQ0NX+u5gUhXuCYA\n3bAGL71s9VRWAIUwTD5JQZ7wfct3BdYoa68s3c9gvTiYEFQUaub/Uu0DG9BjcDEr83AK31h2sLlj\njo9r8Nu9+NhpU5EvMS6EgHrRc9UclTDzMwq01ZryMnP/9pW6UsXewGu3i3KmbIggTPsaIPzgn64h\npfxKFYwRAUgYUpRyGwXBRRQLwsqWJgEP7VGTBEN8AWBUQgyyP2lES+YH9Xfq3I5otDh4X0CjmQjP\nB+KyzGnLDZp8clG3jdCnL1QrtnG2NGGnQQBXSOdV/SGKatm4wBvNR0TbosDyidMczquHx21vXs7i\noI2r8ui/pDLZA2uF1Ih4TasdzLHwSMqsupR1Rcr6KNwDV79WbQF+VIHVPDInK5/V+LiNXeJR63h+\n3UmvTlH0pgTbRrx+7Y7ezmmLJ/n6LHy9cKqdmmCL7M9SnuXARiUoSagNKnOq58ZFeb1cxdI/Y6Zb\n/95NeHA9eSO9kOwmB5Tv5/7qRz+yXQcUeLT3k72gwAheUMFq4lMmM9Eg80ZVOI9lWWJglh9hgpe7\numpdsQNexwy17+n0e1McZuqUaddntfuiWCgIr3ru5OI8FaDXQhIU20wCVffWaBzjiU7b3SYHaWyI\n3Da7VUu+0kGOrk7ObVO/vSBRK8+0j5XBRE3Kzi3qyDqTMQY7Vu9Mx7EGWRsTyAz7ZkEbRT/GMjKn\nE7Utt80SH/nWGGT9UvdMSbgzVzz3pKhrGewUdUXFgkgSDy5/tsqyhRJ3XO8j4+kuCU5Ilz/sbb20\nlhcxMp/n08bku86jNO1DUngb6FoixqsSeHBM0tDVH5pq8eHvjymZ8ATPpCRU5makayK3Kt1tjkuK\nCHFav/CzGZq08ZAckTVsra76ts/kTHBq1+CXu93bizYj2Qh95eGY2Ddn65bPQ/gc41vnvhr5Tbwh\nLr3kZoDWmltXQwwyGHZBsV8CuKuvR/qFnWShP3IlpMW1igsfLC8Jkg6pg7kUSvbjvtCmof9ubbfx\nPtDfohEaBwAHAFxj2lNH4bIRgML+YfaTGFlZF9Uw9qt5isMlueAadS2yuRptBZ8ZXfx2sCpIFkll\njlWjh0PV55ZJYcB77X6sjn4Kh4jcsYQVhjFUr+oLHizWddLUfN2S3wQmAaq+VLXI1FThu05rH/nJ\n/5ttOnq7Taz6KqGajhufgJDK2Bfb9hI+sOKTTxw2gLFBQq3gOcTTfWpqo9ZoANjIHhoSr2fGeOMz\nRLGa4/uoMif9m6x+OupbuxMkKnb42PdedhYF400c4LeHtDbh6CJqrXAgV83/72hFQf/fXQ82TiQ2\nvdx5I8JeFVdDaJ+jzts6sR/4CDW+Gnp+o4hrTK8tI+eeK6ZTImzEkjuMDMBrvjne/xCP/dIDZ1VH\nKoms8juMExxLcOeMKoQ8ytehXFkJFgekQflYDpXPCNYewlLgc0/lVWxqdHp5suvT/+pSyCyuNI92\neZQGegbHlPvm7EJobjRTGMbmyXZWdu91vofwhWAV03j/xWaRPi9owiZROECrzXuqr/LcPqpaDkYC\ni0dmbG/9/HiqBRAko68adyiIwxlTpID9KXNfyBlg22SJA2Jbc/6+uRAwSOnzKNhAdlLb2i/LDPVK\nS1wDpDTvaamBMJtnDVbLvgFlIAnx7HfFHnxWgXAQElIhnVfWgbcBuXVnq6s6WTr6XuTe9zRJkreq\narPN9XcPeTgyJwuQIkSJhWDHhP2GLuvUMsSK7/05tqPz0Cl7h8rlnT6aCtj3DbhNb2tLlrrmsnDb\nz0w5JTQTbKS8Z3e8heuxz/uiirzQZt2N/L302epCLWPzU7mzBJ2AKBmPy2XSdAlO9mUCQFUr+AcS\nB5CWNcTp6VuA3O7j6jwc4irkOGSDmmMQxRtd09ZKGsw97uwJz1GKhCGSc/h7axseRV5SQFVMJ43T\nLYZpwUJOZHCKJkY8f1H05RiA0lP+wbHTJVgM7+JZUwTMoDF9AGfWbY79tR0lFbavdbTyfpoQbHsS\nfH41pfW/bgDJJ5WZZQynKw4vaBomM4uX0Lb2vffRG3avDOj+IB/YiVa3EZUsng6OfMysNntN7N6g\nHKAk8qf7eCLquXDQvRhLsMKHkS2gYdLqnrP7UY2x3O9g0WFTD0s1oRuUxzHT2fK1YZiRpB87Vy5Q\nImbAb7RJPQ4JXYY9U3jm1egRCAisBPK6wlk7tudZPu2Iv8r7iZyI8Yu5Ef3D8dR6rlrv7O5EtOwW\niP10WPNZh9oGkpwOTf3Ejzc3Hbj5nAtEKiuBcdn08l6gaE6HKpF3Mj65QWhRRGLXUFhMpH+ivX/T\n4D7q0Z+av/HnagCxK1881FrCGNHkvbHMSlWVOMHkxZeae7H0q+azvg0GIHFpNxig06oZd1y2tLkV\nQ+Gu1+gdxSJ2UMkQ8JSQ5foLagf179K7/3AU6Aq4zUDGWcnOwNMZhVdWxzLa40kO3hOkwVUuwQns\ncwlm/i5WvTr2q7gpUvlpYWtRGSTfaJos9vlS98PkfHKi/Dpw8bGMTqhi1vSVJX9sPNwj8f6YmwEO\nmtwCDQmDDvTuU78ChjHJ8GiO/ahE7DR5WvXaBxcGfdrQHYiOZH6uvVo0zcYT1B82r1r02v9OktUX\nsGDWkl/maFUx3Egljl69gySgtalbyn76TYfBp0jTSzYkhAasPTH8KdQwfYCqbHUCPNzpeQ8F2kem\nA69a6JGJUO9ir3oY2k+FIXJ0X8Zr5FhoJWjiD5Ukcor+22oxGvBvlbIkDXZwzwYpZnfsAw0QN995\nxJU9HFn9Oz6OXJlVHC4OLPNGX+dFt+PunnvEhIXVfpL3dxiKDXvsy70QrjWBBAOPHIo/Zlqtpy/O\nlDMd9F6QD+HKU7nmQPECx8euihrpmMlcfDgYpPSsqAf4xZ96YpDI2mhJkaPILwg2nDVehNosQCjR\nWzkYG+f8jDrUbyHYCa20rIyMZNWS0r3DcbjEhg0EctbdzMUmmGEc3Bc0q8a4wmOswD2fi7+lC/Mn\nXN/02UPIgfvY3y760NJ0qQIMVuYFKYe7eZHdYmJPCaFCGwNzG6MCtczRTo+ABLIJR0uzj8/K2RvT\nWs8thvOFViwGReb5/JxWeiLz3eTJGOfIURLfTDjxKX55tylczBXMfpxhYDEPldyl8ytoT5UB1IzX\nCNzbZ7ChBJ8uDRcrC9QfxhSdCDI+y795n3RmPe8L/e8SQu3v2utw6WL4P9SdZrxQxP0lo+/CRTT0\nwoxXomZOOBiqsE9z4PBj8jeKJblyS/0F9ave65LMu88WGtV4akaIdkkuK+2r8B2Ml1QMEPmV7mvr\n1dOextQo0Gyxl+qlLijOEv1IR6S99e7yUqYR+kq4Z+vKcqCnmGbRRFhZpxV2Olq/XWKeDkvIelKH\nQvdv0k/f6DiexqrnrcXwmZugQk4IOAryg/WyGB5u9pj7bWK+zmJoDm2unj+bTFAiktrIWEvpZ5c0\nAI76RmN9r4j8/JXcASVr44EgwSqNrQ6nAUXt4jzC1GKflqjkvlXFZ3vw48OdL6eXtfX3Beo7WGIz\nREad/jU4j+TdCI8bsNH/k7gBtz7B+ebJGZ6aPF3/2kex5T4AS8XRooXsE1AKcMj4ArqqzYBy19rh\n1xjiNY6kYo/RGwCMaSRkUkQYLw/K39HDy32MXGxcbLVyyuack1hmQyfoLTwdfAh7D0tcmin8nRbU\n2aNK198OSOAS4xjUPoNtM7vPNVqr+OC4fRyWtEHJUhlY2/DaPajdP6MPA+qKoT67bDs5DZNidzkY\nc7LjIDSzOYM9PxmeEpyLRz/cg523Y5+1gygR4jNcXPwqz29VtJ2pGGtvNa1AqHruteUV4nBp4qkb\nxstS1USIf6BBHPn5chGQVDnrFfwXKcUL2FqzwGhg9cXFJNnUkFMzoMlVJfAAwxtC+R5/twnpU5Vl\nsp7yxlj3WAsZ5251J2X7YsgUDoBuelc23J6kzpNJsFHNkmED2buGQRbjhh5oEEN2SdC18r+2jsUl\nMb3D51J8TcSdfC9U1+YyIXq/dHFur81w8kjL1LQ9x5SLfvbmyNqDaYeQlYsdEvKKW4Lvdj04OOqD\nEJzGmbxGGO8QQk0pX66Ka0+Ph7CW1hlowSCZv4bomkOUjHX4NOhUkKY7xuSEeR9UwHu46ONxguTE\neR74ZgCoCR4YtjjmL8Ef8NiHHVdYhBeX/MJhZ1RNp3qMfMWOOtlkWUaB957bt0eT/q9qW9h7gWJk\nmN0NsY7EqeQ6etc5CiB0CWgMMMe8Qh6fuXwPJQppVDcnkS0nvCTePOeKK0u7slxys3w+apmzyt6J\nGmMhqtJdXd9DbTdPEkD5g55QUtYEvqEhm7qvVhANITRK/AaawzFqP8kju0hvkkpv4beZCsVtPKT2\nAN4/xLy0nJHKGiNV7gw/yf472Dkw0LWC+aG4jUbUEZZtiESWs3d1CmMHtTTV5xdAFabZWwqhOnie\nQ0dLEHoE6b2s5kJUrPr7frmsIyxxVUrSM51u8xiHYsv3Iill5kmYVFJcdjCVfcHlW4+IREoU9BUk\nBEyBSZVYpfELzZbayDCg3wHJCaSM7EBIEjLgZSNTOHEauSVzK4FdWGQgaZz9pkTzfO+RHDY/9LE7\nt2aJTimUJeD8CQ4K4nNG5Xinq4qhluKG9tO0pbTHNVSmzUxpBRjUG2iJEWL9w2HaaT43bRK7RuKJ\nxutSuH1hmUKbR503mL9GPwWxRZ+YEvDSTwEuPRrtmwGE7mXLlSxsjehRsviQvO5F3jep9BgjJgdy\nSxr/+to+G3PKSrL8xRfOE0YeXPClilUPiuDaYGs0kTsiSXX7Nr9GHnxN32V64psr1h06zCFWY7kV\n31Y6E4yH+YLRUjOnGWFczT//yRcv6s4l3YTOhpQ/2CTk0bDnYVvSpMc8fO/wK1fWJCEU+QPbik9+\nGUksrlRSRR8PX/+JYSz9HyF/d2QqmjUmzxPd8MkGo6WhZwQI7MqyZ4N1oE6tn+HMxVphLlWU2TBN\nXK7d6ycMq61rYYpQRj9SwqDptR2WbVo68NqsMH4r9lwO+qXM1RWYtNINXvt11qORNRSyJJULWL/M\nsvpQJBVs3wzw6UwRE+oqOPyq6cfbwA6Fnim9coczBm8eIsw7oZAZyA5VODia+NYORzHG9IzrWea3\nNoLAmcSZtVUj5LqAnaQ8358opoxCv7DPNJawZOJ6SSFpqOaJa6OpInIgkiN9E76rxOZw83RFG0BA\n0824Of00iDa3MuDbiSsaDOMDzFTP1KANpq4r1XTelCHWR5nJcljHpm55A+iRr/0bCaMZ9WsMX8Co\nOYPGJSZJr9k8eEHy8OwMHrFXXPwioIxhqHGbfzITAs88j6u4h99HWr6MdavazHoPHThDkSzB536K\nc+BrO/zKw5ro/RkEl2QDBSSZ7FkJ1BepJnSP5P6nL8OXgjz6oUPjxgg4dupjIzs3mV+v/Ns/fuAb\nsGGK144fCXWoi2VYj+AJIs0egKlaqYDDbdaz0IQ+31bIkhUPDMPBjdj33W2/QI7IeJFMOR+4l632\nZtdbPndwewdCmKgdFOZVczmPafIl8Gp0TXVvAep1M6yaTOVoDypZlx07DkGdbZLy48J1jFfsR8BE\nrkvUHr1kiJ2O23o6UJOXrEH7tjIBQ/7S6Ba3wc+Lf9LboTMbjwdHosbiAtjN7NqN/z4sl+6a0rym\nW9q7B0h9MjhIS4drQxTXNcPtKPqUayZYS7R+6hxBCd2YbCD/fKSO0pKcbsc7LJv2mchi8svEqCTu\n4wdjiGvUkfO/JHEYpwjzobZaD2MTwzR2c3PgTEY2O03u/ufKPzcfn1VFh8SFFW3twmO+WUKM6TJ6\nSByaISq20bAg8/l7z4MHEivIKQ8rhnX/AORJKuMAB0XGRvVn8AwEORMLYg3/E2iH7LGrEAINwyWk\nh6og1SKs5Y1YIzurQuE/B+0DoaRn+BnVc3ojez+qcH6wF+bb8QOsOQeq3tNuTiStXOAJFcOqqUKi\nSRz1/Dv8ix/jlxYBwja6huNp5E2uY3he6SGMbWL5hvQ6056luGLypeeSuD7Lyz7tJSHAWCmYh9hC\nSjLctor9d1KN8fHU3fDjW3nFHnpTYlBvu5aUTRzYUln3F7x2gfTJkgAZGDVHHdz2Zd2L1TiUh142\n1AgSM/8Yg201v/o1Z8t+o8kOBZBjbai8C196YlptEWRey9vdpmBa5MwPy6xlLiO9oRuqqILJOUSQ\njOTy4CKQTedIQCNMGro2AWOn929UQSYcT5NOhdOLOcSRLwipG3ejZZRXWkskiNgUpAcsNdXRrlZ7\n/kACCj31hiZeb5rum/FWCw3XJIa8J1yYTtQ9ILEo0z1zAemKMfQpPtIGHUbE6uVdSuVs5mW6gyim\n3XAB09Lm3S1VLUVFhuv+1irDoi39kmXrmOqvgC0Vjf5PqpJRkCmdHw1dt/VPI4zN0Q68dS3fBWDr\n03WOS64yT6K7xfSENYx7tqn1wS210rsWnSkdh7vyhJ9lcJoi9UqEaIi9x/0V4fTmt2muSpIX7KVu\naXfohruy0KPa67OkGocQT6pDvMq4lvSzqeRXNygimVIlYfBpUs7HENiQIlXtAmmQShztQO7lGPKy\n24FWZP6XQn9j1eYQ5JWyAChIb3M7gIu9t7xVJYQMz6DH2j0X5oUCBw/ZdN/boBt90jvpVaohxxPR\nzJW5RVtuhkCIi0vLfZNN2ZPfWvTAUMiH0oZaD89+61OZXR2iIHBfIYQsRifXoafi8gwVOE4gnKVB\nRMlnPB5P0usjnYicTQ3JuYWhiNNNGd9IEuKqRFGkJyoUFSPFXuKoDyOFvxK6QWR8tf1nfSGUUgMS\n9mwASt1zshDFSNMxaUa0NCpTzEJp+MkY/gEJ/7IDsBiw9bu7pIIkhLUfSx6An5Z9OhChDZjuxGsd\nu6QPypLawWzbYGlQjSeOulXkVPpyEDd/tPvE5mabb235ORNJEONZXCsn3M5XorO7fIxmsiEVynKc\njqjxXUHRiCK0f9DPaxokgsMn/U6WfmmGJI1UE++TUG4jiA6jug5W529v86XfUOaamuoXBoe5xHK9\n9NofUXD/2W3wOpNha6xSt192mQswypob5UhJfot3Y5AQHcY9mBgpYwJY0T0y86p0FsQNh97UNuyf\nW7ncpocne5ZjVm48lEtDv16ZXP7Uyy2D5ZghT9x1qa+RBxRoe6uZ7XGNX2Ux16Pl7REY531iMOXe\nUWsspgx7aZUfD8aUQFemFJB4W0sBIUbC98hzxYPqOv+oAZXLPc9hyCYEEiEcdk2/qThEdREFzZvk\n7hJju5uuC624rSfIzyoRg7mmvq8EP8l7KOygpqwXDoaoaJTUOJda/0z3MrQipPW91W8hF6gns3be\nFdt3gEq9qiM5L5lXJTLF7CZJAImo3EdoURoRphKuDVVumhBdZl3SyY6Mg1QAx9PHIWcrmj3oFwNP\nCx80j2pjIZTSXVKZ+TIbXlK6eH24+QM51Yw0wYCTFZlEkuZq8EjhddLMPtglN70ckyezoOeCpgA4\nK1f5DkCyM9cZJiTpVfm18EyJc5W2LLy32xBwW9AEvEm4uMndkFjH6ELLp+7e9kjxYldyZdkbDF8/\n6ojIuJ/lkf1/8ht2cAJ05CttUPl7H1m4sfUuSjZyYzsBDUhKT6jUsffczwwCGD8Rn1gORxW9Fptf\nt9HIajTCSvOQnVDceW5rMaEb/Edn9LwW6PR+QDPz2Dk78BuDn7e9+eO7eW4kVigAnGlymi0J6yjN\nf7KT85xFu/Gbj5YrSm5qNllNJj+fFWKG1tZGyrt3EMvEffd7YM+GiAZe+JMTk9LUguyUUep/0n8Y\nxirBGkx5ww5yL6t9aMUOaO2LIBRrg5PwBq7mTpBiT4qF+/Sj1K1zzcE+gbCCgHJcENwVFoQSyt9d\nwyBDFU55Gl/XxVYiiyx8+ovBSmuBC6sovokaKfixE5j9tgvO0LOu0+tAOu47gG0Zg8wRq40MfEUG\nQIPu6vLBthk1E8v8xiTvKLme9eIOoHWXuF/L4y90Q0u7YnRsKWUrgsrrla2GaVPKUeqRBMuK+hLJ\nWx1aq0vUy6spPws+0VtksFPXVHgUiACMlpwUXrzWxNaLs4kxEtdTxQ8wya0IjzVBfmwsmtFjg22r\nU5OdN/AelweVz5AdYhM10kMi3UWNRTalUAjewX0QpiLRKLIWw8YPSvosRjH/97MbmWILNZSpsPiF\n1+Htehrd+YzIjoiyJpKxMHvqblL6uNNXYFhdcmu6GuL9AwsZFmP4MBjUaeymnVzsAkp6o/mjQOYE\nWU2W5R6NMvz6zmqduM5BR+bYttDxVSUTzFTibgA8lPYSZ4DAQuqPecUVbi82kLQMcyt1iEeIEBj1\njdCX7N7WT8M6hNpXl15aVXJ9MBsxi2DMeypjqTPTHFZqx3yejZMZaQVZbbHSvXs5tiQC2r9H+Waw\nkKwYICYaCpiTEzEcvhE/yVabPReFxLhpDmyi9TOc+picMBUqTx7Rxg3AA+SxX2HJDZhehYe7r/YF\nnKJRY+EO9ZxmCCEfq3w4K1MRF7AX4lVXk673ezVleYUme0AqCGbKATXWsGLMyyb2bomJZedjNHMc\nXXo4/ZirCt1Gn/OigzsqaxrTT1ErGsdY05+kMTcMv4m6CI/YUY9hriMjq7RH9d8pUw4EjCxSxH5h\n5eqVhMapSZCJmBLpJ8B+bTZ86Ced9be7L7nKnU44xXv6lvSUzQ6eeZTPrHdOrtnH3iupHRB51ZFH\nUh8gd36qtJDFbfOUjD9ICzqwz9Evi7DfotJp/7/UNGNoEovRKc5y/FPRDLHffsxyowSO089KpTD1\nY+jIHpi+TaLzU5YuRb5x9Qf64MksIoV4j2JuqhLYcBL7mMBX7oDdXo8W7fYGWhST1PhQ3Ck279LX\nIIFAMn0LcYbrKhprtYKQTdG2qLHj6qsYM5cT/5MExZXENmUKnW2EUprTyOluuQd+VpBWFuIRazqQ\n8/Ipy/sqOpkiEKL9fdGnmTbT/5sbp4umjdHsIKb8lL27ZutmWE0x7IV4A1Cq27lAziZs80cm8KQG\nzJeExoNquiQvvPAd1JPKQizfjccJx0nMa7k7SNCBinF7rY0dOJoji5RgGqY6DO4vMSMo9XFCc21l\nemLnRCkFKFkXR8loWTO/EiZWatkEphm2wgAYnVUGzu4NdAiM2153TTN2XcJswtDylKEcEWKqIJVl\nUzwFmnW10YJw0zSm8bskOqB/6Dyw9YihXLmynoOmxaujT1TO5BQZhR/UlsJz0dpL9BR4fAlCCuOo\nPSjmjeMiSZZ2qGU7YrhKF0F6WruiAyIqjfFiFkW9Y/X2qTqZdVdcBnHLL5RwhAHukD5qVo1dXF1Y\nUQty6/P5NVn90Vl9YkjnLkyGkTB86d1yqRA4cEmuIrFC6RdJXZPatEP6tLYfqkBwYUbXpN5Xxn63\nx5zInvFp1I+pDB+K3Va8xjCGd0x6Qu/pVpoCZPSGZCukxQ/osq5/2U6ror0hz9B8MBF+jbyrUmRr\n1hlxC1tO67ZPxTAtt13qbHqU3K7wx7aQAZ1bt9bdtYNam9sS1HV3v8GdOgEeHlAT6w+3gILyTOTt\nGFSnLMDvRqVQXc5+S6LcpelHN7AsucAluidqIOd/XsHk7OL5r9QhOIYr+x8czBJqq8cJtc2HUgC5\nZ0/UjCd7mvbYbx3HkG5yA7t3kViaEdsbys1zDal1OPPeNygkuGQIEylHpcFSIgAo3g2EVFAJ3LSt\nVnjvu4VC3eWyOyRmtvdN705AEdP8akk0j/ZVlB1SQMVjf74x/zI2r0YluOUWPYQSxMExShRaQLA/\nG/it8+vL4yDsaYKJ6TuPIIcAf5dF+2K81MPEQOJFAytl4CNrwjViYvgitVw8hH0huoRep86arcSm\nDCJiJqXIvoAKK5BSlu2b+AOjCpspPXPqiw5VFo5661GOj/Y8PZdMdROy6nX0km58+QqaLovaTnNA\niD6gfYlnjGcSAkcrpp4afOE0LolR8+k8Ci+dNdiD1VnVLcyjT9NZcYjSUcf26LVrRHCvaWdF80rA\nV+1h/xYDs/QawT4idmR5pWWWP0+aRegDAWdMdpDrTemTsN+SNGjUIbTYmtRgQ0POe7evaSXbeBo1\n++Bqg4uDO/cN1eZFgOzrhsJx74gUcPLx+Ci8pBG/ybMcacPpdyvi/wHkva9buMW1ZsbdOYHC76ww\nDcE1qQBZUI4YuFYzEm3RPSSX0KIvnS7xpJCaOUAmYLz6I/Rwo5pFfhNS8tD+CzGGoBf48MJdmzNR\ndzD+SWEXto+RZgjO1xiG7tG30PxChCh+uFE6UkOhl9PkjqIvPY20oCpFfwrMv14GsjZuCbjfd25Q\nU7s52B6y/oCGBvFrPX6m73UN+fMGjSOE0bza/00ylz8n6eA0ScJmswUeRNMYKSm9zBjzMkN+P/v5\nIvobvJ9CNONggf0yzkpktZKxHJv4TfIVQP6JB69cK2sKFM66AO51SvDOBMPPcklRacPUnHnM6OUh\nb16DowF/e6zAFGCMnm+v4NZ2Sb1vgzOC6ZDw6tBNqRNmbuqYPd/fe2AJA7NHGfHDysXNr06Y6xzd\nPX8dj8lAC95gfaT4TLwXsHcghsBwHAPLRF3D+0aHiWcOQdZUuRaUKTslvCPhBsephJo3D70vcwh7\nlzT5V8P5xXpIyfVNXrL/HioGbp+/ryVJr6m0iHU664n1t+/CHoi5OAY6fpBZCQhBN91Hhic+0DEt\nbtvBPHdn1OsRCaDurIEqlPpwDGicusrJpPBszNL8YL7s6KNQEPxAgYtD0NEL01h/BT/xARx7OyqI\ncxFK0GQMK0uRjwUjfW3rRyMtxGS51hz0ZzP/ZfNudvdqYdvJhYZlI/RwS2yus4v4GfKy71CLWTZ4\nCRvCyQ/c7snoWZYBchGHdqUOR56URJ3aNNz9YeVNX4aGe4oZxIBidtaRZ3cfGG2q7TsbmcSABXn5\n+WUmaNly44ZSXUIJSAG543p8Eh3gxqabPTPIdeZciT94q02V+LVvmifhf3Q8uR5JnBzXCkCjP/BY\nJdxE4Bq9Lq/kDXMLA4PS/K8ZU1YPgNFL/VCGP5hplRbmedc2KAh+d7rBtos0pCAVpkR/vXj5kCVo\nMsI34U9xRS2lucR0SP6wD+zjOmw6291DjCiMOQA3uy91S0N48KcsRiWFZFxXbhClh6bMc/uoZAAM\nRr++W48J6oS9E4SW3PpGY3v2cVipSVq1XrAMmdg+1Q/uyMGcaJLtFK2o2CzDqLkBU29mQa0QCPz9\nKyMQaUdt614BzQQatyeGMsc7TfS2DaT28qjfd7KZeOnEX2MkePA1Nsyg7KFhY2sTd6873fa2+UN9\nxeKjpjlJRWcWzIJLScCTmSmEthdwtYgn0U9DHlnmitv0kbag0Q/NGKjtJf5ZTE40Bu9zrt59GLNo\n31iHTM1EZPKXuIPMzBJHLZZ4GP4udgERLBuarZbVCReEfMaFNvl+Tr4Q57TrKAtoNvxS/CPIN16M\n1hlWA0MOCNJzIo1c/LZEWtZMddQQV7FNvcX5bY4Pz/LhruWhcjl412Sqep6q8cC1f8qM6vzsn99e\nV5HJFMgUJRypemjWOy3BpnH/j/Ieq9KnSp8zFInNLTF/0FZYRMyRUabPx10GZBGlz2tBdeEt0sNH\npcCy74QH0F1yS/n0TKZwNFt7MPd1Dr3Ckv1rB7igcQMJds6h4ar4hlq4qWG0cgXcVvJ9K9cYxLyv\nyTLzsKYT8/j/Ycm+tiCiS+m44qT2bwSVrTRnr8e0WHAqcNWIz1vN8C23Bi2PCpDzukWLlYUG0t1f\nseYZFIiN3vNG8OeX5d2rM9uOjPG/M3uzalDuL2Cy81E7SfdUOBorxL026ieyufAaeaaHAAihvqj1\n7pdsGWiwcqqvg1mjPDxSnudvE0DbZxf5253Io4EteLf0dF8UJBfnjOnRDL+rp2cTAGcI/WHMpstL\ng9FeKT7hZXiqfC8eEWCao25G66mi+VaEgmflIvuy+sxxsMhuhlD1HCEoAxLSnDv1FV4Mwe0MIVJk\ntIROwiscF7EMr50UY3NeRyNIDJ0+pISlsozVPg45LkwNsWxSbOyVhiWoci4ieyszn6DMo/6IlsuJ\n757JfRrk+w7DMs4gMkwfvsNCnivHVlNHwc3k7FNnkMcS2rBg9uzDRBlV3jAzSwi7V201v9TKvMYL\naQOkOzCoZLTFFFosDQjF5U4VPA0R9d5lgLLBOjotBT+SgEOHOgXl0deRgZbnOFfvs/Qm97NHKxCl\njEH3TNDV1sB3fnsCLHndnuW3pHSaq/EnXbJI80FQ2qWlt3vziXkinnT1nbHxku/EFGZp1jyFV95F\nQjb9DEaWRTsvpKkg4qfRnEYzeDjG2b3tZs+kIDcJ/qfCQkEHcTSAZPCmqHulD3jZDOwan3G7bm/W\nWmnfUX669iZAKIZ3QFhZg9eyzc2z1aJVxqWWRUyg82V2e+6YV6EAEw+r68awV4pUU2DVGyb4r6Bh\nj2ZrCJL27A9uLe1bGRp1aJl+GSj4FMGl7pLWrxQS2WNeGMtrO/Ge+2ESkefRT6cAgsuaOi+kb3to\nvAvIBL1TavcKvYUt009hLm9cgFeYK2oaRPieM46gcYo5zg8Q1+MRW7joxwbuM52qGqe4MBi3BsYm\n63Amv3AtQlLqQ7oo5uLyM6X2oh4j07TS5XfIKJKhN6Ia4dcY9185W0gqY7FObXJkR7756yOpryQr\nzyN04YztX827vY/KcL6sFVE7P6cFPqtwTgEEZAGMNDfEVuw34KOJF5z2AS2+33/AuYeWFq3ACSIX\nvieqtrF1cdXfPn1bmwe1TWaFCGCSclWCWhq8mkHuoBA3KgSU/nmFh9easdjG7og35c9tkA2+WHdl\njQ9GuAbKWX/mjFdcDqVTvA6iGOCsV1ynDLC7mtOZYB2pM04pyb1SH1cw5uko/X9mwQmizKYPkUhE\nn+0uX3OdlZ0ms6mv5oH2TOgRNdXu6/gNYqoc+Du7I+/uCcOHReGDXygsIJX32sgGqxU6gc0odrE0\nCEZipvRkH48ry9zmAegxO5SMEhmmUt2f/7vjdkBIEdgr1qdsurKJtjmyyPzekbnL1UEGfngi92nM\nCLhnn3FlZYVcuIB5zHbP2Ui/LlixqYwyS7DujAzi2g0eg9HemlaXZg6264WPCYAqcEGG4HAmo6ha\nwz30iTN3zs2CVWm632LbcgqYIxlBz8JfJYOI6hI2iNTBdOlgIK5OxEyvpnztwm3ZoanTkk8o+1Yr\nA2Omtzgc8jw7BqDFmYzhIoWD1oggbMhlCpj8ekCfqLNBUDtRoGOZne/pXqGLfIIjBen6HZw+s5Ge\nh4w2vNnouuB6NUEWvEKW1MSNmpXkiAdYejsYaA7bq2EuWcjfHcO1HEUwWvZeiZROsxsS+daqAuHX\n4kylbKpacwAV46iNMtL+jLZD8jskS1r46lxMaPXnN8DlRt++0J9eUthHzpcq81wQ5Es88OJ/chjH\nwiPXpGKQkrgERrEoRU4ssNKs5HehBklldHwcPeto0dY+DBJsYN/1oBI70kGxGWMkjrXsVhyMJGn4\n4t50yefZR0WkvPvJK4lgjdkl/sWRCXXKqMuIDfeTxJWKp7SyAHlRNeuK2AT/zMX3HkHGLdF8UT+L\naJUwDXYXVO51qbuKZE9Z0LeEKmMf9S+YQ5u/SMaD6+soKRdx+wR+Fpnv4yMUaFfCgVmKkk/QkOKS\n8olHK+TTCyJw/VFPHGd223SP+PzbSSVeLCMgTZFnLkilbbUGWSFpYkBsGolUj9fSabTTIQ0XXJ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152CENK/mcrnEBtzlGEqeXvXzG296UFl1k88E4mFYCLg6klvvzD9XERq2owuoR8dTuMC59uP\nwabo1CoT9NgRyKXQqiMgJouNyeEFtitpCsrsACn6151E8kOdytxFDd/luRC3++8rEBr0sD7sIHCr\nLZDJfnc85D9PIobMjHhQBLakVFtOg2LTpEOXxvyjvwUy3xyWdpE9+PIXU8zBdd+YpAltKMDOUgtR\nfy8917PJ9OfUYvKqSiHC0XYQf7EDOblbzmxOD0sOUkOwrtkVKi0HO0GqLuTF8BjtMzcpNkDlpfv7\n01x4lrJx7jv2nwjFDeyoTYREbdO97EZS+0YuHxkz/WRKvbWxIXdaCN4AxoOimY1JTqo53bONr5cT\n1xt4mzdAoNQjuSkhMchFBeX5jiAqhOXnFMJKtBF1GqPepIwCmP4HWAVewNqb43TzOIdpe3/Sfugy\n8JPWGTgLb1dbDVoAp+QyY1XspikH/UMgB+8c+SAhQBkPssRit8g4FHLbkduHV2ibi1//g/BaSRim\nbENmfKJIjoaUo7QvZt9zL9nxR1ewxM9PpsZBYqiNVVemq2wyWi4Fj/MW0cKjo7f5GFJxzcbTzn41\nWwRwqel0HJrtmWGmVul4zCZWI3g2FGEy2X/BnGuxlvbUf1JE2ehm6W9OBhG5KpbJMnB9a1PlPsux\n9u+t8Qx/OVraEjeRtprWRoHGcMlqJwFSynYXbWNzJi2jeGg6+FIlovTjOo3tWup/amfxAe0O53TX\nQWJ3RV9Tu8X+w/FBELQROk/VJ+9JpB92ctFyyCu7/n9+NoiJlMPInutRgxb3wZGpiQ4/5D3nNMGI\nbpatgkN29xcv/QAuLTF5LGKNpIpOWbQqnzzeaDAduQSoCO9QWOsSukgJzqWUEY3jHXSmwHsVdbjk\n3C8L4m1wVmaoa3Uy/USnQukf1zU38E3ZZm5GmNMDXUaMyt6TjwbKgqpmtEv/hNZhthZrkxlhcyQL\n+wGCyQ3tiHlizuupyqpqY5CcRlC1nxTvHc09vSBJsceSp/JIDwa8zimYzM7RMsy5hewL6tXSlmwc\nQnVLKnAoV4nP8l+KnoXPnQSjtm/xMYBl0mNPdC41rTJRcDx/DpSedcqeE0RmslafkCaj7LM13RW5\ndSyy7F0QjaW1FTvU9EeNnHDsAaYzIA3VtJkDeSccsa1l8xNvibrUTRtcEZsCocZ/BbhL1aJFD9nD\nkHijgpb14J5CHQbh8v1Ij2ACuZffhhvB49w1qEPc2LxDT6eqqMKh9wbsKM0JEUhPp4W+Tg35k4+1\nXQDChqwgg3ejb+9GuN2dqa99hlKrSg+urZmldP2+B7+BIszxz+6Qwx1zdOhnR6q/dQnjm3Z6LbO3\nNFb2+DO6SIRMQW3jNslp/KZs4/hnZ70cmxC5NOOBMLcuIXSET4JDVSlqJqT38QzrfyG6gwFVrK36\nm8ag2hZnmx3WahXfEExKWWCcv56g4ZMzd75rZFd4htde2qA5c07+kE/WdYvKPWmd28qrt2ODLqk0\nw2zr0df8HQ47L6KO0iMU8CNySOkUMw/nexJeCAGbb1N8fEuQYZgVAnf7PWnXS1J4hzM66voHHe5X\nPj0zdoI84jI4Aldt5MhbkZjkvwRTvPgNTdkm5rrbXyOBpJP3Xn1wril7M0IvrRIFBd5EBuVsP97r\nM7u2LHz26B4em5x68L5GsFguqT8/wUuMUyVy/ZSsqj0PP+FVw2n4IUgbZMTDpp+MsVDmdpRwf9cc\nHESg+GZU8VmANj4/IqCtESgbd0Cljr+Fd5bjZs0pfuD/MGtWoWwLQ12C0e/FVJg7ofxm1Q6Fu8Y8\nC8O5uyYe7Ct23855TpLWEPmgzW911mmtSguf2IEoUG3WXKS9yv04x1mO9pj980abQajPusaNvLfn\nFfX9z1kuzhBrjTTJ+1FaQTNV8/+xNapdETkeSsl/f5jtZ4CG0ZorXqEH99Hg5JjjTsUDGzuh3iMb\nXtVPJAkqh3k4yrAKYzP1CHV3wm7+89MYXCbSkTtViO2XizC7zbze/G51ccSsEKJXt2aObGjYbjHO\niQ9y/tTLJPIJmeAbztuMBGL5HnV8iKnipfjsMjPE0plu+Eal7aCwcxYct35YG4shhiClfSaGRHJ1\nVTbUkygcHw03WvkAtrLtTQWvpytkcjE9YNrx8O1mqwGgkO26PNV8uC3E2jtDU7GWZPwXLIhhmp//\nKMl6Nf3sc5vefoQCgf7Bm5n+/jWr0md1z5ycwb/8ycZGGn29PsuTJxiCzVHDDiLTsJ690jBW2HOR\nX2wZjCddyrB4wKoULWjXBo4he2j8AYuC0C4gXevjACHdNjRZpqLWE2oe2S+pyeRgy22zQBzORNbB\n74VK+oGU0akWWGiIelOqvgds7AybvQPc/TtttBj5chsHCFBHVBaxOgv5zBC8L9qftEcve86FzfSa\nRhaAVnixdDZcXlBLuXtBk2hPGPuLGMPmGt0chRYtKvi4y7AP7Y4VSPvT29zI7xNL9/ReOxzmxVkC\nPCBXhhinn8wlJ24cs5osgGRUnLkA7gr1beS0gnPDfHfvOirMLgddDiIJQNWtMeCyYIjW7C9SJN5k\nUbwdHpAqd21dyohuwarpOBdihS2E+LVk5dIsa1d6h3grFJHYmeVFLSs9DIXm8rOP8D6xHOqBk/7Y\nfVhcPKjxN6b+5Q0UiKNDqOemQ/LJraIDFq30LXm0yvKd2yE+AXWpnKAaGxfMTZn/dx8dQnHT+YAN\n9ry4bWhbWbEyHmuJoDcjWp/ChADzjLjWtS5t8J5o5H6YsGXDQDGzNMLtyZSFUOgILCElmZPlfZLP\nS8rQDi4McmmzAbfYnhYFwIVIn+xccpgYHLFcAit1S4diQONcsc/Yuculd//Y3NbQ+GDlRdeks6ld\nn+8Z0+bZocJH87eRVUuqifn7VZUqMysoSYHhYxwdY3rHJopiFR1VnQgY9FEHQJQGLLW9N/7T0TU9\nTVG8oP/TKH/ZXfa0RWGvYmy8ig3N0vkWNffgtai5yfcwsT+vc3p3JtlNg59SRkxwVJvIHuTKyl/6\nvp3J2X1eUmGkEAg/czuWoMjlqyXfSI/B6HwsVxURgbsIsNeCFmNgprKqF3T1LMJnbMlVaJg/FPDm\nX7Ac889dIFNqvnSg9JG92bYMPbRR35H2DFFa1/dbfdl5VWnXcCSegjJ81vyAG5X//+n/5BID4dj1\nc33DaTz+j2PxQYtur4Ei1PFa6W2DVyx2WU9zTIwyLlEMzTPqLxXCbx9p5xqad+rvsRvTk48m5ciN\nuhYRSmhKwYE5G17/YW6VHtXP6XJHXqudcf2yzEF6cydkrES7gf6FUZMG7/FshWUKpZP2Qg5U+oGH\n+ft8zQjcaOrdAVaj3ruO/sRKSsSiEmLHUjR4jy2rxTN7Rgoaa3mxjs5UECEof+EoD35ep64qTiHk\nHQup4RvatkWv/aiboDhAeujRWV2TTPs+s7RkOVfc9Bwfg5duCNcoyV8bqcr8UoT99DvIkay/q08K\nH44hlSr4/zlIWxpGr4grBk0GA0JslTOO/Bb4GlWhIuOLObPCpetcRUwaSgO/6LxM+89shP1VrmMr\nqIJwvCs2yBiprcxY4Nu5HEyupLwzoGQSQmCu4Jz0PxzxlZ1ugSW+1d9buwvEO2DmjlxbehAvzCad\nSqpn4YSF64DcVY/IIkKqkDpWw+1cyNWW8txwvIg6gp8M8QsskrDbfwNOLU+8aunhr9tNJB3wNSAA\nDdVUKRuOLU29DlMR1QkxDtsBT8POJhJeMeN6f2RnpMVYP3KHiDS8jsz2vqcWAdQCOc+oq+6uP3PE\n8DJ7kCFGpF6M1VpTxZ190mKJ0RK5phfOSmxyoCl7K/QLNWT7DzTRfjZQ0BV8s18KT3ne//WCnuZz\nppugw0KcwQoFVW+uxaXaz4NfrKpsA5Ccb273DeXvtxlT0Ylmi2UbUcK1ppOCjuvDRirm6MtzcfGn\nWa8pDoSH77KRLSWBIKI9Vcl7Sl8YutcjTg0uHh+xOv9o4QCGwWtzYfHlW79Z8JV7S35zwtJNhvpz\nctx9hsXqswdBIIT5KRZOtB92/Viis4E5hocf99E2T3/3c3b17qzKKasCAuyEkM8/jhcBfLxJ6CQK\nUfk4XVtf1+d/pk5jDDqW+dM0FlG3KJD3JIyIfkGHjvylydYKZgiacO0cSHyCLx2Bh42zK08u9d0q\njBTgSUX2VOHkwhw0ed3jYiOpzXPh60FgggzFxehmYOUESHjiGR42sd/CfnDWF1A+qTblOMuj5WBP\nI5HozcQ4evu/azLVwL0fV6U5DIW8cru9SoJbh/bSfsMHHHcbt++19Kg3VjAU2pzwdxecC/BD1+eD\nlEBRx18lL+Xne/arSKWvjnmd/0Qa5mb/hA7bWW13BXi/NRfl8wPCLZg81OV8W8Ou5H2P+GXlVFJB\nLlef12RpIFa7Qk6zyWXGGBIJ0YTl8faaJOoee1N/zV0DltG9IQ+HDcdQQAreeaURoy15pEzm6Ib0\nZNuTLja8EmHo31wdBGnTcvt1AtQlLlQ5yA0aRrMZ/qN2uflx1hogJyLihuZ7nhAZAroxY3QnLoAH\nIMQlPsxGGrBb2mTKw14bQsy/2GwFohIJEkfpYpfdMYXhIP8c5WH7Qyyyi8o4wUXkkQTRQXfBYzWt\n77HJMuwZMTDMzD4Ya+6zADWFUVehswYmRtKw0Ur1Oy2Bu2NVHOG5xRtUYg1hdtAOfJ4l1Q1Jl/Xh\n8V/hPsaX57UZrPCBzUOMls2AlVaf0gUWSukdC8xwqDsOlpugKms/yJiVa44jmokKGYsFjI/2F/Zs\ngE5BRpgAjQyEmt11Kc8pfgMLWcpq6YNNNUnbo+3eDhM1sEixLsup1PxanWr7TNV0p/1v6IR4qZAJ\nqgkM5U68TMWnHUP3nHOAWwEWO4wnPacXBGO9fr9HMhgkgRaVS9HxivDHorT1IW5BtHH8fMnovk2G\nDBc/fGK/RY8ZVK+Y7VuvuSCD6T+KwhRKNDOXljIJ5i4gAQGe89ZaRvGu9tAsUnN8z3ZVZ4D6qutb\nFt1ps8Ff6zAl66F3/h7qidZ8cTWhsrexJj2I0bjXbJuq4aHO1ZaMVGg5u2BoDsPXr/6dDDCuiL/4\nNDpebe7Y87W1affA0weklOeeoQBzyAw2tkgaCZEZTucb9BFxQX0dChhIaaIQkjBIONiN+yOTWX54\npq+8XjGXzvJ+CDU32TwCY5vzhk/p/YYm4/qS7SbA1pqPLZQidQqB0TqBJrvAEt3xTnKretQ1xfNv\nIJ+bztPuzlYtIL810Q5atd8EYL0lYGmDGMOYoDn2NKzvQqLW74gzdwmNHXaNshT3H0MI16A3ZDLm\nopzzGcvR4DC6ldePmG76rg2ad/YkVUQgYDLtW/Jc4HS875NZ9EnVq23bgwQqPoeOtEC2Tw/kCZyu\nPbG8qBcubOxcBK60GZovpYcpAH8IvacNml2W2pqtUi7tUpNxBMEud+Qoh57DqYgUN8X8OsKkfouz\nYveMM2F/k2RO5dubBVSBBHdq4CHEeRlSsRFF3IwgAiE0tPKHbXgBF5HNmvNXgTeTSO12Qg82tzmS\n6YYZdRN6aY1H8oF48bGaLhmi3+DoeGRgWJtJVGEG5fCKe5mkNtePvwkDARf+9J+ie0ZVH0hbEb63\nppUejKkwpmM5193uvSFMI3SpbkEuGnxtaGlBQKi91F1AEO7FfQLExm9rDTFEPDUyRQ6a0Y91J8Ru\nJF879+IerO5+Ro1ww8pkMh0pGPCMzT1OIYHY5KCyw11fzLmRmIwwZ4BmJzxhnf0+AIq6nPe4v5Ne\ndUu2qRtSBc+tDn5j32ZnyPmeiOFc6dUm7LA+bLdLxq6PKWkkk/nFrvE4YO8kcvMWRHfPaGnEXchF\nDROEr6y9tzC2agyje7IrWHZTsuMVBI9EcwIerfZomGUqoVkgQk1Ji+N+lILZgYOgcLimYZMNhxXV\nSnSoyn2WGAPE1PdarsW/WVqqMhF6Ulb8inwllvp8VA7WOxeCHZnY2ACeY9BPPj63D3+PtSN6ExiJ\ndsgfHgESD3zvDOUrHHncbPoNPqI2owqBxB8QoKewBEipAlxTUrcozbfjpNn/ZtK9DwbzqbcGfuLR\nVZXE0p6ZpaDmKRw03kInvwYQTvC8HzPSFAYoUxPdBwTScPGO7Snxux7h4Am1xIQ33gTsF4fF5FMY\n5Y3NaiymkeBw17TgrocYRyWdKs90IyksiSkatGww//RKmYCnuONRx9ui+cem/iSbhwL4evivI9s3\nuW51P69FNVLrrmxRYOM3K77uJidaUSGY15R9rlXXovqICTSLGz2ccFm0Coz/panIIPGCB1Qv28Cq\nvliKEQSl+5Ay9M7oMlNrTkeSVn/Tq6SxeExjQMlREcKn8KcCgRoFgBJUt5x72f3GFy0D1lCAhIOx\nHXSwsKcaofOUzwyQ5ZVtL1ozDI3/6cZWP41KmXIBCnsE5jUJvDwvmcs9f06EbBEKB5WnwkEVA9fx\n/HI+4uIWypNINYX+yKXwrzByXtRR/e895ERMSh+Utt6NVxMv/NVQDy2xTycJkLj7551EID1v9ojj\n/LnS8ThvGy+GpGnzPXyB2EZQa301mlH4fY41wrxBf+veqmA4MONsN2S+Jiti9oAUTrQIdiuPwrtR\nw+ui/FGrtQhp6iYwpzb4yQ5MsQgJkB3Z6QvFEy4IYPEuLtCwpl1rvTL7pX6MR3B/RJzIUYuUT4q6\nVvDdNi6oM3HwmVKgRF16CIhRfcfNa+gB3Dmb9RqrqTOg0ktNO5SqYe0Gy0LzsKgML8YnC322E1++\nen9Nd5XjOZPJg93vFpOtG+lIljgxNoMcIqa6XTexbRZQiwLNZLsQ5rZ3l0yXSal/F+mJek2Bvo3O\nmLiQ1KAi8acPTRuocBl1OVXd4tJMCr2AV9HBm3nPrI4nelC5ReKXZlJd+WnMomce3lHPBbn0LDXC\n07g6+Aqu0pexDyUbnYxSR87GgRKJTyjPG0MzVkc/KlstPTrW3fAAByrYGyUPymClzrHJBaNRzf0q\nXLy/RPNxa6rq9sLmDVot0WPL94Sc4ZSJB+04AOgSduauphU9b9midMoO4dYA2l4/ppz2//5MhKZz\no2T4UD0NNh2QInKbFiEtfzLgxlcUihSLIzwQHyhP0VjjcX9Qk2APXd3jBTbMH0vsTICoGKgVyJ9l\nwDgs4ZmmlVeAorfLXETU1ETaooYeZ1RHyN6WRNfn5cSaOx8ewWTqSCwNh/AF/7Ho7A1SNG+I4k2Y\nNVPLXKY9oJ505ucp8Kf+LfmkYIdpOIk0ctx5DstEHV4RsJ7lKyiV8zUCj5sygOcKbE7qXMxrpcA2\nAuAimomNk/KfApUVAWyj+xT/tmMADFAb5V5fDTchYi9ZddkrIYgUr3yjOuW/kX9wcTn07o4pekjn\nRiqPEaNVhTW+9UiL2mmP5R1MGDcM4mTvACZ5dZbGGdSk2jCNeLyNPoWQD4W+IXHHYwQtWEC9fYz7\n0kpVXr/gJY1FILS112md8JfI/Ey/lhmHP6h2immZJRlH031x9QiBftFlq74mkdZObqAKF/h5UBFH\n2WKj536OLYg5B9pHVfa1HM9ykM0Hk8ZXvs14I8he7dP8H9K2reIjsSgyBV1nIZYAHP3hqkyEoqsQ\nYqkCdMH540iB/RSM6ECmgdm0HTZl+6NLAmWNqAtp2Mg1gHYb4mW/ohUf7+rNIqyDkCTZxZ9np8zj\nlNOj/QYaSxoezPLi/wpF6L6Vv65kBtUJ3mAiTpL/OsTiYR53oIstTJAtNfGTo90TWfBoFUdKQDQ0\nZ7qfmHAngmeAibBAhb6j099Gi0IDNeHWUAeH4kBZP2pWIF0KrCOgzyVG1kZtF+qfQj7+YIGH9nBK\nuxDYjCGjv0iYdBj0piujB21ehjKgE/v47z9lpzd17MiUr4F9cx9FewLtzIfc9oQB9wDsSIZ2J5uQ\nh1KSB5dCRUoNpB9OMHt+gJNBThr4jH80WN+rnx1KTqqAr/zwGRfnyO+xxABjtiWMt2NAScWh1i/n\nc4kFxx0HQbly19JKieVeM4Qh0EZqPx8n8fv03+PLoraIbx42+aZmQh9FQ9toAdsqyLHN8GhZ68ZC\nF2vmfaMWSTaqa9TOYmKQ3w2bMPMYCuA/xGfy+g/NbdKOWfYHyXHedZBG5JBl8w9y5T8NWLHdJ5ib\nGOdQD9YgdDDQGQziv8dLYi1GsgCflBmJZBvsTEaZYtfmIcqif9liPJ8ApnGF7KysmNQbekeNTiV1\nq3Kzvuie+xksBazF5xmH2Q69fmjj33+4qfJaj+XECm1KRbIMFHkbsRPxrkOIBo6y45P/PQOdHQIg\ngIew/lYIM9CJBCm8M8zY5mSgE3f42IkdFtEObUChgFTYjovHXdzaJqZYcgnd7WPcC+7OP1migpW2\nY2ELX7L87N+4YAE1+Ed8dR1pxMKqAhlC9TLfxVUS/zn1yhyn+dz4AfQvNaQlTVflI3g/jhMHxEJt\n/cQsIZMCNOVRbNVJwzTSRbT8Ej0vjXLKhSSJfCFzLIQtawTkRLpR+SrbT+EMzlT6veA0y0R2KGxA\nWZ/hwNslVcTeHpdz/FR+ScH5rzOQRDZMUAgf1H/5OefM1wlz7KdX+vAz2IFZhQCkpS+XBCFndg4U\nG0nyrHPjOI/PqagHjTmM7zaPQhx49LQFbFDqjyb56NjLj+S6/CfJqyxV7/3UYBT6iv8QmmnKYjxJ\nyTjdQYJHEKHTgGTKUqh0Vp3MlPnEVxTbRbofUWAeCSC9hCuwKn+NHBujjhBw30hhwt6xvz4Z5yKG\n2Bey1/YQ3YhC7O+nBnTf7lU5deMs6sTyzzLiv8Rk79B/ScHyH6ahkcOCN5Sy7X9NqfZYyKsBDkgs\nfUW0Gl6dl+bdVPqSyL3/YmtY6Oi9rpW8kM7qTJtBWHzN6AYzMGGBRqjq5+rE/dlP089SP1SG3WcR\n+OqSEsKUw1hEh9hjFHKj0Uw97teMmBRHToaW/Es6ylVpNNnaVOp0snjWmFqMjpIb2KwMA3cximY7\nEJdiMsuMCV1Q8aFunkGIOEAfHOVAV47vmO3Oht53tnn7C1s13N9/6/sjuFlaZrDcdpiUU08m3kl+\nu8wAGwhP1NcCvE6luVzRbZCGCdUwZvGPbxMILqWBmXRfyFrpSKDaVDdMglr5+oRET0w7qc2Z5v6+\nAgdYLkfH3nZTuWaDtpkRBxYuEvPgJYBr5JiKGhKpUBq6j1XB6eo8PbhZbqXtCtN+C4C2LLWCmNNz\nrQA3efz/DWAwBM1WMYLFC9S9+hVC6V2JuRJu5aHYmvevgQIbcoLUhSjxdERikVJxZg0CZkofvsa1\ng/59Cs0Obis+kLHbAgvF2tgIqb8yvjH/mPhBQ7WUHj3U36SmqF7XsWKS+p8rPDolO5EpLdu2aavz\nSwq3q84M0XwGX1LZ9nNSInZMUPBhDggd6wtzJL3R5GM3uUG6ypom5c6e4GtBFweoy28ecqhccW1o\nxhcQZNuGP0nwBxfncr1bhzWdyhJglIq3DwywMpjKYgLx/Fm9SOT3h6NQQUa1/pPEyOOFo1e2cP2I\n05Tn/lPTO62Jzuei7P7+5rlIUFuMxSyFHYRCTVRln+jKy6HJjvPiASjxoRXBMxYEzr9CixuFSnyy\neZhVW/QTRgrz4sDb3JU8gErSYePBu8kTymj4AkU8qCa5fQ+JzGosayrjEI6v6rWWatV6sXK5Wxia\nDfPZdCnMbxxucbKG8c2ywq78G0fYcKhUyqZ0j+RR8uZzYubKuAPg9xShXHTcO3ZhZJbEciDVoP2a\nOgm2OeYzK4SsX/ps2pDaWctDZ3GnBZixyyLNGv7HADLTj3LmVXz6AJUIiwtbYDlgbFu1nMWzICoj\nfdRgLpt7vXKLYyZIPaYtNovYzZMWsV/s3IHKX/tOYp2uE9S49SJ8LPuAepJzYicvolUDyeLgImCb\n3p3oj4ttsT9OFJ0HwkeTn5FzRQpBgUSCzHrBKJtjiBLPGtSrX2hXHijxrXaWybemO0sTeUUaq15m\n30niefem3wmrxNHyfUP34LlRPaQL6GnjgLuIPq8gvf/bo4MMqRxFHw0e/fJqpqXmwPRa0Hu5un10\nO85V0Nu/YGJR2sDA21t8LSsDn/Edzxbw0XTPL9F2e0kTHLkX94sLGMLJBvt0/O2vw1/n2BQW4bIe\nYo0zDmUdUrvraP+sq3uVWFXQZSrV9E215RDOq87a4QOxLwsE+qxX9GTuUiNCELcbkE9rYZl53IsJ\n1LhM7g78za691NP8PqxMNDjkz+ATwpk0q56lrtd01FvS+NvfFr71YcL/0rn6x8PCF4EIcNzP/nGP\n62CbSXeiPHdhSi6QvZkFf0qjtC/zkgA2xMwMhxm6B75n2n/MA8pKDKa2xDn7O8ZTRe9MJSdlBV5d\nHkEDZc2fBfB354mNDTNIXuUNCvKmDN5MNpOb/dRpYhgd3SJg9c1fxwh5RVP7EqLixAG6ZhA94UES\nBaIPTXd2n5AB2AsnG4/PokbNT2vONCMrCj4mCw1BJ3T9wvQ/261t80XGDoZSC/iXvemnteNrWI2x\n96RNC0s/BwqaNaOlAinvW/bm3o3JzHMsbiAeFq8Qyta2ictLKyBSXWuJmIDJue9YFeNsgsHl5EsM\nS0I0kGMg1ivpOPvSJ9mkzEWLO94INxCNWE1yh9+NC1ZGUCEWvbwMpfrV8OGB8kB9srpuSLYR3iGi\n6sqp9S8aRuK6mao9Aupq351sqsacNNQ9bh9602brhAQZAt6mHuWbszxAC/yN533II/BrmCx4RomE\nmDcwxZqJsxFLvN+KrsSHcjPNGwnYoQlkK3Bwp46U6mDnGXjNOcLowKRSOHXTUoGqjyHxOSdo+afQ\npozZH9K0HifrJ9gM5d80D19PQ/OYVcWmZRyNw4Xhigo6KtTFVdHFKSMBjACRq2kUfFEcimTMCfsQ\nWd4Yt7enYk1BJfs/qyjAPkpdKHe/PiPLIujleYDGnhdON3LdAgX2uV7AwIHyY+oBQbIAnvL58jNa\ngYYsA3j3CUnVZsfEvBVn6aR1549vj9c1COyCZKEKceRKTDsDu3pnVgxeHxfhFmXCK3tc8ex6jSvI\ng+Tbj7yPIgcLHHoOjoT0CwC/QthoPjelEgHN5sxdUBTZIN/vaiHyhdhfk2wPy3nwAztMUuq7bny/\njIw62czjUjp2oSx7sUh7rRmACihhWjj8QdsR7t5VOQVJRWiXU53CWGF1Z/e9gDmQ24zb5sWuMKgd\nhkgD9psXRZBRCEJIKACWbTOUIGqwiwVuSKMiBAobBkXXJGFv6qFLK2qurnHB8cSt9LI1RtX88/ey\nR5kuiMNiddycnLNUdk6f8FPw5VRBCFkv5xenPM5TxsKFa0C46MgRSDqqrtRcVaWBX68is6nCYiMj\nwu8JqRcjr52+ITDdxCuoK+lJN5K8CdCQy6fJh6wyTRDHmshrq6wQ3l32vyi9shfdDTj8HfgFkQp7\n7lOYz/f2acC2Aed3Hj7gWPlm3n5x5VVwPEGKTnGTAcDe959RnW1HQtDahsHFJoK/oH+ZKvvo9CvH\nRD6+9sJ/+SiHlupaKaU2Wz/O+Gtj06YxbmW1vYYlXgz+6BeKcWD3k3PY0mcYiR4+A3TlDDHP3L6g\nuY5yGzJLsCTrSR56Pr7UEFcIL1HrUcWcxWr1CcSKzT0csFsb/oV1Fhyp1pgNihFIwxbfAUS0DTZI\n2FsHlfPqq7nmd4DniQ1RO4NXhAHXOsUxfwSlxbuhcLmIFLsVxsqLWyHHM0s5JYoyRb8U9UuZINGT\nsAnOGeUM5MS8Mspr1lmvTgxOq1wCJk3KfoORszhQdA8E7QZCGjWfiKEemUWPw0FN4Hcp43jrU6yP\nnq/T0JH7sIdLJ1DKBAPwqyBg8zE2piNgZpLwsLqG1WVLOvTqU8AMq1T/Yf77QsNmW4dJNDc62s/r\n5YDDGrzq4kU0lVaxtDxKnAXpYEBXINtZ1FyJw7EYH7c7SNFkN24VaFwJ4fSmoKoYKIkcNdrypbcr\nAnVw0E4tYU4qkKyMEnZwGJHKTvP0XBYTSQ2YO+PsASXms4yizSJ6ZpRJz0raVhr5gs5aEHhWd157\nXiofpODK2g9ykkjr7VYTJgppi2S5pnzEZYygP81SsRjrxbm05qaA2IUBFdGGKFR7GUmj8px5c1do\nwPwS9Ny3jvJFf0tTN031GJ08O3Hbzl2jtjQju2pZeMBIYA9HQINie7T1bH7IKy+LEtJfbSLoCkkg\nymJIQuxUr5OfFvqzoqGOJpDri2pca8qHBRBh8sGhR8sqA7W6QBZDASA9YPlb//gOCgGZdYwmDSfK\nLgOfJS3unpZBf+mZIWwKsfIx2nWHaRzjbre4vz0xX9QGiygN8/BnXF8O7VNsFlUNyBKZOyScfPgP\n1kpDYXf9ndhVB9w2d7CmNvmY4vB+Q2mojBFJx9ZJs8n3svDfb3cnLAk2Aa5avq1EBlVW/kVr+1La\nrAI4WMLhfD6px1yPwDdkzCKxJqAY9PElBDC51a1Q/g22E29lj7jeQOtFP9CjXuqhgYZMP4xLLN9M\nD4/hBsJQXl17n0LzDj+z7Geyt4dq5eQzUOwI+RsgUJtrOzOjiGtzzRCySdKaqT5XzkF4QNMv6eML\nltISwT1u3H3vA2kfb1iUm77d307vWfrSga7zf9Mpo+JlhaYYtWx4KzVvxACWf2bpUrhW8ND9wWhx\n6dfRw17FJ7kgxPT+fg+qYt3SpzGmALfzPVeA6vSioDG8AIY0YaqDLMUTnKDBl64qLWtspaNSlHeM\nrLek20rPbGJIQSO1ICj7tuRA7Quqg90EDXLrjg2uuaUZcFWx4sXBwA1pJ8Gl+O/x8c9Y06P7eXqL\nIw6+iTOqoIP3Wo0EZHu0tXiOJurgvfb+wcCf2E1o9XJgXWbGsBUqPdPnXMZ7x//bpfSHFiIqKeAw\narlLF/irnJ5Y7R1JEvvWWtGVvMvP4Nb2t/jYvG4bWDH2/XPxrKlTnAUkhHA3h1/oLuxOl2Ope3Zl\nF9L0XCHdCfumz/6xOXtqxgEgvfp8kZjbn28Nh0Ba/Iubr0dnutVxrmXpAzN0UuFheW7TAaR7gvyt\n3WrHMhwGqlIT50MS9bSoRiQ1RlFyivoCboPW8ATd5FrWu7dkkLpSD/2QqjZwqnzHXk1Y8yr6c72r\nqTf8VZ4bbknm+gjuW0fFnKDVtfEFzhEMmwP4XMlwToaiyl06UdIm5sQGkP2qHqxD/Xx6SWbm0uFC\nBWKBnXFh4gQq+xPQ4sqfCEO6pkSxx027LCRZOrT1Sq44rhnRchsggtiE/qGXOidOaKVnee4Vqfu5\nIDGpv6m378Qe9w5Kt8ubk3nkW1SbnsNWtcYeEnLRfOZVWip0WdJnwDB4Hce+3MGeqyP88T5DY9gZ\nwYJ7dNlPzJfQsaa01b2BilAUa8CZjLLxrX1WvUF5Dm4Ugl8em0Y7kT3LhtrqYT0mlTv7e/sST6F8\nW3oOh/c+vicZyuMcEevpd5clM4P0WSHYUqmoicsRtQW/iiyqWwtLLHpA+UggXPHGcl0mHdRLlMGl\nJlZujKEA4z98THShz6LoZ756dO/HrOHb/PNCgj7Od0Iv8Pis1J7uxXFsHsXF8lLGdq8RtTx4/w20\nZBc01dyC2gxEbF38lKT2ImJEUajuGOHWmw74N7HlbXuJjrZL2MAJMTkHr9gEC1cNVZM8TXxwOZzL\neDFi1LSF2loi0Ha50iTXGR/G1eLO0UD94vp4DGgkjZnFVfQUB+cOLoajZBQn93Q3BHLot7NgtU8j\nfjcQuNfTa9sIXwTXKRwEcbsCZIPsvstaRlpEHGFbXSwMzPuOYzCpKWZEz0Q1F26KcIb4cLO65edd\nBpxa8NYGBPGsCMGm1ieC5AnXe3D13NVNJ7o/KVFCJm4KFehwpJNTbhmeyOIdLZOccJrTmGD234wp\n06lOq6Fw4h18hqXds6BVHokfro0tTXvmmsHo6eM1Og94h+nMb2/a8dr+x7P0mrvNFLOqhPnCNDfX\nHfHhd0qBeyDqdXjXNJlim2UJD3J0Lw/tn0LRqUJfEHjnkLsWiRTb1sS51wvVPLnKnbsrCBr8vWM2\nenZfnz1zh7bQzGQLFdA+09XyxHA0Vtv9AjWoBE9ijD+xji812+pRa6Xm1tx6cL7RXh5v6w8EXb4k\nWNAUEwXycP0XmFaGR7Chxpe1761SSOgnvpZUtls1BphHg2Mg6HM3LY2D/sHcHT6b7uoq0X1FEW9H\nK190zAeaAND6xjAtxcj9AV1R/5MbWqbU4nggFaZFyMKX8zX5xFcMXJ8GZLs4Y+pZTmBu91a0+Ahz\nhCP1Fw+meeAkGipnTfIrnjeGBRKuooF3slVpmTJfM1+Ae3NmqfDkHQKPk4t1qIz9W6EgROa0tNHp\nq2cMV57iRU2kkivUAmRkjrGnUzfFqO6H4x5rMflhk5i2Cuhzui4vBVPmGJpB/BqIuesiMblh7YUa\nUjuLm3sGfQW8G2/D3X3d0sqDURQKarBDXJ9CySRMpzYY1C9GBN5FfNnZbfpgrz5owMwnsY2+ySEW\nJ55i9qSFmTo0u/QtdY/rQb/2phbjesCwuPO2pk4RaWM/LjgBDzeTfNXzwCVnw61Q7blbCvvdjUib\n+KbclQayVPYd6dJK1QUohEtj/h1YBfqC0OdrJVZiMU7SDEsDpgCrIWWqaNoo/zVkZzW+q1krs8ZE\nqZgCQrfN1uVEO9bHOE/4xzJO8DYOoa376LpUHe2gAQWeZXG+nI3L7VOUsM4HyDJvM5hipyv/A51G\nPPzup8b5Cj/frueThMsRmodHecttCwn2EQA7b5mqM3CSK0z9+bTf0+sBplTNtet4QnWaNu7HFl2u\nFDhqELKzFIe7iPWmYh1mMR+JPxJfoWjaIOW8y3qVRU+2VS3cDW6c2b+vg8KrtdrfOhJEE1AAJm2w\nurBADuvawQL+blZgzLLM/1hY00THffL0mHB3n39xY5/8Mw7GC4ryg/vrWPQ7hk24OChfD/+BTNct\nxkn/Qt2WfhIOKMAeh2zXrHSluAJBj71xDE+anUj6Ktus8KR+tW2mvaHrbIFsot+v9nqTlniYV5C1\n4AyY1N/fk4490rIBHvJzGuRaWPko0klKhDEp41WB1cyp2V1h7kylT3a0RIhlBQM9U1/lrt0dAzc+\nGgH118SokkxEpl84+Om0iBWzXlBNVfMWb0R7Ta4yO4zCat11mULQfwuBxDeh9FS1V1a3hfcyWsE6\n2hX/kyzK7Ube6qVIr56/o8Ax7cZFMAPR0Up8dieBgxiMhRbn8XSwfNcMwCm7MkXBoteqwvW6IXDt\nT82EZRi0z9N0L02qMvZ4n5lp/88FGUM+ayciXpHH77pMcLmTimp5UagV5Ef7XjcL13I5BW4xjDtN\neAcHOQtkGTuLvcML4tD+xYUlsMHimGKm7zIgAuwnEhPThtCRFV1VHcRBIg43mutzFvAimYIjVzlU\nwMNLhhO5GXdWD4H1Xr2Tlua+CVuAMI+vuvnKSET00+4bkcKVrTTfb1LRYE9bDNN6O1N5egdC8C2O\nWJ5TfoLRTYBsp7oRLypp003PczYuQNGeVbDUm+EiUzLPSLqCGnzKVPLuiwymh+8iq8lUrWzxJ1RJ\n/8kkbO4EYhEBdDZBD/1mlCS9Cb0xhAM1JX2Jfai9jYYXWNDAwiHxnAiunU6ZkZXnMVG4vNUDzFtn\ninE4fuHRvHqnRUG2qzYu3ylqGHd0jE93ZsYWQElPAVxPUw/clRK3uVVOOgig+1GJHw2Vq1LSms1L\nRjMh78rHnEG6mCfKN1OvCeLNsTzzGN0ZVQFJ/drKsS6uh75Y0QD1B46TnsIJ2RT0o/os7HupOSbz\n8vkdYBAXpmrvVpcPWJhAGOFr3iruU6rvQUszH5dPiJi0Ly5uoe+MtcYUdrQDmgUI2xiW2OH03Za2\nU0XQHL7ynfRinevo6BOR/Qyezp0/s3JZvDRp2ODaV8LK5J5mj+qp2Bc+RC/HY+kd3KALIpqGLrLk\nvIF7dame4+EgXKUlzsRpnanGfjbWGYTn1kvSTcJGYwMieOj/t/PQj4udazexcGkWrgqEiy8qioQe\nYgE22t57v3ZmsPIJopI5k06WQpzVvhjoSWf9pyuZksM48Dauq5pudeuH5/M3yv32UsXrFb/kq1Sd\namHkD9iBF+2W2VpPpinsnFVqkBSBKRtl3qTBMNcyPSlNHrsyouw9Xii5hYraRU9kAOtPQg1eHXiD\nOObjrWa3Vp0MiJQbhs7Ny5XexiQHE6KsDcoTBYBYgI2UStP+4vueEuPCPNEMAFeb4iXTOgEp5umZ\nTHZIyBcf8KACjtt2kqPmDkXUbXdLVE1qCfb8DirgxEeNuVleU5gfzgM0EPEXNxSD3GcXGoIcRtUX\nYiwKiTJyr1BtN6DiokJh+HZFuZNpyiytde7uvAuZ2lb9OgNDRu/PuVaHPQg0y1ic5FfLbdYuUiKP\nYHdj8u4DKp4M2P4YY3Qe8oERLx1nrQljwUhOSOpiiLZXaOCU2I4gJ5nLWum8INxQ/q/3J3rok7x+\nnCcYellLBpG0rYaCubqSnIbOmvsbyL82VoyoLxyGoLiDniR+eIZoyi6K/ZegaS0qi4l4EMfLBjse\nUqst/apWMnLvkm7FLMtgorPo4S/CTN+b06AZhlXuTHPSbX6qZ0DAxhkTav7J80McLseCcHegOv68\nACr0bwcWzo86uOTsKw5hAyNnT6drW7Drf6KxyV3N8qQBrnQWLznw2Duer6l6e58PmRWI2C4zZXce\nzwlt97CQKSd50rRNxy3So7dp1KbyfNMb/jBo5kxLs9EatyZtFSSHJqnvyGdKrZj3T8VAHC+fdwaW\nSnJ/ERkBzjHx++9Y4YhHdUQr37HutFbVyb6YxZWEwtMqw/5Az9RO6rqD2JYM7V6HXYyWAJNAfjlh\nKU1L7L2rxwOkjroNYv+4YUsDwywYoEJ4PZuHdYP4Mn6T+vd1KRoOUSLCwMayDsYC0DbUemfGcVIm\nWsnko2y9v77BicLHCAU2XzGyJ57M2zm06bY2ifLJdbZZGrkQtFh3DGrpMpaTVADDWmIuWDzo0Q9p\nvEmkKZHGqNffm2TuWf7jvvM9823RD3Kd9gxGNibvMKZUv302hIxxjh0s4XTRXP4V6lYQlI37+WJx\n3GhAeUEt3SAkq8TECjd18HtqeBK1Iis7rIwz0LRdrFClSyy30hjphDIE/RCVcGjfxekRmiokCM4A\n3QNDXZaM/vMgrJSieOTDSJeQlJOb/9K9aId5H9e9D5rhhBYVcGMfcshzH63R8kI9KIkBddG3xIgZ\nknaRb0R10/r9NgDlvhGmDt0IwiRcvWi4vtpo0P5aAMC4jJUBO1j16wnJWkDaJLQMgKPwzBxMih0p\nXJVmihWh14q/dzbHEiQPOTvkHv25RFsaE23XuFqHp1tbzjilaG2OHl5LUeFufN35jx0uyT2vXrPg\nPPlUCVwx4fOLP+L976lQ2YDNTja4BRY+MnwfeNhHIx6FRVxXU/y6Uta4MlliOmTAOsII3ZLwKKEQ\ntorQzV0mQLjArBJhW6cTXDGLJvxIrIlWZtEDNB9ZBuFcUsEfl8+T8/LfUGhEGihkuUyAX+3MVUUm\nbqZvDpMl/hFEEBxAlbtgwykvT1jpxOTbqljYnrBGBfCuHbQOUsWfoWQXITw5dZQqSVvbjPpI15KT\n3AunJgUdIP8Qpzob5tS2Dtz5nSFrBaNM4NbBLcHlUwEugbju4z0PvFqLqqKhstX6oY4cqdTwIZAr\n9XKWcfhsFae3FBwXOfy2sz/pV/wJuiGJTYNhFMs/V12BPTG4ZBMGGGou0FL+KynS3R2OwvXrAnsM\nA62ORfeRDNOEzMtlb8Yyd0L9KltVBMFuFEBVPuThbQhm5aGDN1PdQUwLr0RrHnr4BeloOwZGs/Am\nOV/HWOjN/2opqdBRaVCaPjc8nJtK5wibd3itAqfp1qIScwBD2e29bh381fMJmNjvbk//fPb5I1ai\n7hK0LwHgWsm3qzexA8uXj4WGkjWWtyh/1wJoU/dj9sccGgtyF61qFhz3ad5tZakz6IiGKFc4w7pg\n84mORPCTvD0fBoPuNTLx+whJ24DmoOFegN1SvYTJ/Vset3J16Laf/ByVuTHE2LfU74vTIYV2YYPr\nmL8HJNGFS6cFvxKHTICzuFJh15c/T7BS6gXoRdvyyFaWO8CRqECm4MprsQyD2luSR923BNJVS6db\nZ5m+gKhleSdO0SAAyTc4tYzqf21NvEogpHx7vzlgtB9SRTqBmEfQDXO22XlHepcCQrlOs0hg4gsg\nK6x5Nz+Lg3rh+QGMM731JMFwyxaLXXAcjwZMEImj6jsQjoCEMzLoX3BXf7axbtnT1YxQSbKyUq3y\nsDcV5UfjaA8RxwlkafH3nQFGgEThgmjjS5Qt9bh/1oS3PhjVHXb1Lh0dgiprZRpm/EA5u/ZeoBPS\nYWHwTLqNsu2D80QQhHkJdnj1g4gdZl20cgSc/4ZPMjUiEi/aSP1+cOZQYXPu8hpkboAtPp7DDc0f\nzxMZAQwGIdUlm+3wTrfrpl/LAo5Fi0pTkuCf6PWnoDgPzfQQz/zPaHc+1KlJY5OnkyZuPJWsMA7w\n9zJpIR7aQyFKqRcDqsNtFgkFYo0zWd3xOnXa1vMXmK3I2vsfvhbUzD9R0ctJvuFFQGhc5HfaYtbR\nHvD8JPxiTDPJ0JuZYbPaHZ+TbhR8gKNgfzjbUkRUIMdxHVsaPj1OjQDGE1RHQehzzi1Vb4TPyDhR\nm+DqE5ToXzrFZ1+D9kQoMBUNNYGwqZ0pulcWE2kW5NSckdJLGMXdujHA+rEF45uf0jP9CslTPQ4F\norx4hRr+DN8940cJM7e9tjrA1GFe34T6XFz84i+zNhjHVl0mfD3Rrdz6tdPSYCYIxiuDXQ/olIgg\nPQikmzopDeS31KQSnLEvHX5RGDwJFzZthaQP+0bKJsfRfi0QbhNdnLkc5P7AO0PEbITrZx1NNASa\nXB/ANa/RC9NESUu5bYfS1Odb/UzKd47QB3v1Pw8dWtr8QwXyWsMI3fTpLlFpBLQs+ihEj2SpajcW\nRfuGqPqtttqVgkWQ4+qf666oKy4ZOV0Suk55J0yivby20IFiZbw4BOLQFIVYGKVhEmR2fo6rX/kf\nQ1IrVl8NLBw6Y2jMfLAlsx+pUXCybnRjP/p2P2mV3rq9+zyUZDirfSGq6rt/cRLAIdC7c+b8ZYN1\ne1V/KGk9BDtNsGYSS8Eo9zWZIxp0FuC8poXwyU84AAP57QpNmd1nwfUX0iEsicCJZC1RDQ8QMKjt\n1xFLcUuNgFsLnFrXlR2przRxWci3wnPwIDpZ7HutmZg2fQwYGxxb+GXNr6s5Ush2YPZd1iF/tpPz\nAy/J7N70//uYzSESguq6/3WkYdZZosow20jbq/fIRd41OZIEH0TqKFqayGyaLrskN3/0ooAZZRjX\n1Ei2zZU7danyCG8n1G9NHo8o83xQGthKIZx2OyaYSELlA3+FrHmUDZY/xR6oj6CKaBRmeoQlEE1Z\nP/5RmQDnwJbix8eqXkFVZgDXwknL9RmZBhlCwKBearD2GvRBh96sRC58H365w5TW8xE3yLSnY/vq\npBAlKEv/cjlw48jNq+IFwdBVfYA88fyuRMb7Nh/l85ia0LPWTWKpSrYpXWI7D0IfxJt2qjlaGsU6\nb/AHpIFp7U065cTjNo3NskjGhTZDIEXL7zaGOFK4W9Zu8IURTnz4DkLOIFFhAtgO179TpSN7jCpL\nqBp9scy6qdnmZSL09fHrn+ud/WK0tYz+ilkebGgHyb77v5nDYFdE6m00kB8OhD4h+5bkGeY+Wp/+\nZ/iKyITplx0Gx+cfCMNI84q0hmnysimxFH0HSGi1w4T522zlcu4+hpirOe6vA8rikigaXuZwYs0D\nj/R1uwVpv97W0ylwDs09imnnpD/e7sswDAdm4ez1NbMn8RkHGTNBp8PicN0k4zGF6UkgEDJAJXIm\nBRnsM/7PJOSTPjVnAHPdcLgxmxPc77+walUNR31R3t0Z6S7kQgzgQs6QeGvq21m7tJayCmyj05sj\n4Y34kMC2a4IPAqyE3f6K/J4pg4lHQFyh1qhsXgQ53PT5qgbzit2JZU9VjaZ1pTYBNwX0wEjqz0mx\nshdIXLZvkF7VcX3gc1TYG6677qA+ALIdlEXNZNFNkAPCU98DbEe37JHMkiHJbYayiW0HZcNQA4zV\nxttqB1uIEIAzcHqGjojd2J00LSj0ehXZ+vBV+1Ae7EHOuVsfWdrPsGwiiMTJpFHZVO1Gd2+mrMpj\nK9ia36muEQZdCNK7kurcL8t5WPVfLPgS0CD/o3q5HCUmic3KGYFpaHrkltcSxnvVuWlfBZ87ps70\n6uASp2DZZ4WG+/30X53B8rk1Z0xhO2P5M5f3FqNm7FABFduG+VPn1jAIyzSF9W81d1s2T2lw2lRl\n5TGTemca+HoARee+yF8xSvr0QdvPuLSZKBaqieD37cMbRn2H9K4ODtXiRN1Xui7nmio39g/ILADE\nj+pMHhd0khjSmUA7EqmLO+FWvoTRA3QWvpZ3duXf61V7SWQ/txkQ49DSksRhCgZpDCmGXxGkZzbb\n2faZfLqhDzjxMo0d4nJz3yiuMxCqITbK2IgpmDD5wHMr4Wnl+gkpUJy5ELWi3ZBJMhLOWdqcm6Aj\nrLrSNu8JyqIyXjH6aCXLgBUlgjxmJF8zv19jPZIgAY8lh9uAMYNV78InfsQL4jxHnlXgUWRnjDtk\n0OjZj65QZZWd8wExcNzWILXAAYQdQx7SrY/wpoQnaA+BYwwG+DkLLtYLDu5gdpADUZ5EmTOFYuI0\nMrKw/F6wAGUsbpGMJ6FgLlknSJYJxj1kwfwcfFFOLuWjARFEo5NbzekfiwFMphYGwRg8CvC/c/T+\njDjZa83clulrtH2stXW4P9Dslnw6RPmfQ194/lunJhiSaw7CXYVym5p8SLAOsIlkxS2yt1mot9hQ\n+dStFTHh6TZ69b5T8UXHK+KN52y8SKbaAf1KTK6tFcYevCOUr3eQ+3KDd5ks9IuKyg5Ccor7xqGY\npSu3Vrm9hULAqGJ2YBSPIiGCjYPKRKn6kwWPK+Yx+535PgiNORITnPDHLyWP3fgN4YZXMobwmkSx\niuHvyl/E+D1Q8BURQGQ+UbVXeaRIMAUX6PM1pvfmVaxTPzuDqkzrsXqWTFOkuu/kkDtu5UQe5E0D\n4qwSgvUEhBbJXoASYIERdEAPBQnWTvwAvbtweDQiKiF2sYRvwL147LOjsRFu8Yw19f9u2vAcDh4b\nA9hPveD8tAFz77mhyMsGGj2FU83XlbTQL+JslOZhldJVAHt0NzdihO/JnnjpcQ7Snurn0xlYHbFN\nJDEVQO45GkCoBftdVlxZ8S68RWXHKGo0epCkJfW6Kd9x8ywQmmzGRrFWNisLRVMivZ184bv4HuT1\nm4eGWMYAuYrCubBcClrvGlQJ5Igr8XUeBQ87iKxU4gd8gELryCbvimYm/68R60+zzzqaWtRm2KeM\n5RZl7dj3jjO7IMn+svHriyv4/5kfelDFcno6aSzjrVB9F5NfyAU0WFTBy4wxCKvHCHP18zUSRg27\neSRWRQCIF0Xs90aWz80iiNLcIUQ/0ueSwVT8L9QAWZsqW9NQ6p4huBn2ZNTbB21XauPX2k/ACRdu\nwGDMEZDaPTmhz7gija+fs808XEYGOzZ2UiNJmG4DbFnq9lLwxkYkTs1g9eveb+iA+Nw0iyLZ+N7/\nHdVjBSTo6kf3a/7p+Vomq0LPzSWkRFylFOQH+uh+S+ZH8mnRJUBivHie90yPgUD3LlFtAqm+cL4a\nLF/o5FMp8rtFL+JlvP0tQZK1Q6hF2JE7zVIr/0jEDYdKCLMtohSRVx/MT55Fjf3LEY0B8UxnAjLZ\naKiinS3j0PncuZH4/O7o7pfnoeehdk8ab702Jxrr4DXrwyP9kDu63K8sGhxrDCfrmJ+mpppcrK/a\njgVsfCo2agH7beSHBkMV7TRCVTTEU77XUaYFCB3bMms+RD9DIc3hLcMFn9ThhTBqt5IBGp6vqikH\nz+iNW8kT+mxQlRwkycOo7hgLnLgoPR1N7tT1D8p54Wg+e4eS5Wb8RK1Z/kT9a+wM8JHDjxfDZpda\n5ACoiHPAero6F3gWwcP7qTOVsGCXpKkESUUVK+83CNCfalLBJYlXolYB/8QTvBCqyCAjJaivpLKG\nADhoLm2tEHwSp5rtq9u6DS5gdWzbKSY5OQ99vZZNF6po0LXEgn7jZCQZpfpAPSdjuLu3i78Wnsre\nuMFSkA3QnwPg03io/mjYGttwOi1kMYansXj6QN+QDbeamCIbSobQpbbG96FjNF4v6OTDyyZ9+rdH\nJITqSnEyqTVntWbCwIl5R5jyOhc/FqN9se22gjuh4QNVHVYhuUm2LKYMlVGyq4GHF1CmwZIMhPWF\nPx5QmcKeFELV5yGmQkvx25Rtdq+Ulp2GM0GxRpKgfXacoTzVj8z73dJzqZgvvXnG67yODgATBAEd\nPN6GBe7kQppu1alFJZDSbrrIGXw78h4G7D0uoWQn4gIhrHUGYuhYrZICRqcGRxxdY/OUMlls/m2s\nSAEzIY03FdqNpbNUbMNXRniLAAS2hVBT9QORek4BmDcYTILqfQejT7XFKVOQBGN5r1UYHXfCbfU6\nzex9dmiErCFmsOug1TLU1TVWoUg5GYWXI+d6YeKNxM1AMRGX2Z+zMy9KO9BQDeLRZCkaKgTe+jWe\neby4WDGlOI93fNyk9rbUaJXdeoFKPzduRqm9aYsaJixORXbVQgL1kYwkPEgL80N4UB+TexzMd2tw\nVLljpvraZripz9S2DTohpU6IY2d8EfDB1mdCiiilXqz4fjfsAHHEaSFf+mOmVcs82H1niW29wKEJ\nyy0uVzZQDgYJume6fW9wpnFwSXep0kmsGlC2zbYtzTfJM2npHqhZBdra5uMBdsf0pCCHpkYow8uw\nDmmr6iahzlCF8CN5xepSaxmEBLD8lrgntVl+pkDnwPSWLC3k1cNTv7scEHiUzIwNvhw2m8GoWzKG\nK6a+wBDLXzP3Jhqvn4+It6lKdJhlsyf4Z1VryOpKKwu3D6Db0g7oRN0n1TyHUDBi0fcLMdPB3BAu\nY2vP52Vx/rhNDWKrrNIlibse3S+vhf52RnV3OQkTOuBVfWPHc4ujnMR0UAHRqGi5lMtxyOXxzHEr\n7wQH95lRolx6RVze45qs+cOjw2clJvTECgVrXQQaWABG20Em5eBgZiashXhdKrN74mZ8KTgpbZFQ\nbiG0Aen0CTnKO1/fiQQokWJAd7OWaCOq0yE5TZzVnnrdaTTx6nnF5EweItwFtl0qDcS0s1FSNdf7\nRH+HXrdT89XPmsYMA3MFONFyW7qZGzfZX7JD3zzpa7BvnJPOMjyHy0130Q/9wt+id3mW1hcvi5wH\njdQ9q9VC0buT9gSTY8UJWSaDPJLGcCzbBi0j7DCky4OloDm7jfFJzCfQB8LeTRMc83FF5Ab1rwQB\ntuC/dciGwEZ9wrPrSXJUAtvQkzYU/djIr5tvPG9XOAfLtapV9SrPyPPWOx55Q/j32JMCqqOfk7Jo\n6pdfd26Je+RpFeBlkcTP3f/GOEf1eWmKNZOHIx3Iwkq2v0q3EXQnod+G1ydVFQufrrSNQtL/4yzt\nbWircYxg4Iafj1hYZGYFyTgdrD4nht9FvM0TUJBRkUhdzN1f23lvmBZ8DpsjxdD/+/66PLd3VaXu\nMolqUCDw9oeYcxy3u0aR6WO+x7U+/E6Ol9Jh3zO8WXzYJNrIaW14/BTK8SpgxWUwoktTYGaMWFIz\nJrcSxLM2NoX8vkeUasee80ei8isgNV6MZW9MzCCHrFQeK2FND0EOzHUKAq1u4jvH1TzMoNLpuzob\nYu3qJHc7D9gsxK31+FIj+z1FRV/Ypk1Ik4h0XmoFnGVbl44OCulvP9U69reulSPgFMRQYmL+Ztp9\nO04aJPLf0dG6veRao8ZxdAEbBRMe0p+P6XZXM93pvBhRRKPxKRzYSVJVcHeVo13O/ALRYxIbZmsL\nZLTA4hD0DG/gPWezlqp03bDNEzQ0CyrwyTQwOda5lnA4633uQ+B7NrMKLew9n9PtU7Yt4A/mufpW\nxdD+HD0kBpMp1V242winZR81MPZ8GayHIb8FZuf3IooAAFa+gyL4a9pooUq7u7fr4p6b7oxA9UK0\nHwv85/LLP/mcbqTjDxv9FJLMA7ocFiV3BrOKBKEzj3rVOBDnC/PND1+4kx44Pp66yGONtvbynIs0\nqyqkG39uD8Hq00kIOnq1azl4krIZWURQj6XJCEIBd8rLnHr1FFVtMEVrtnuF6eswBM2ARM+VN3yP\nUNvLr5zzvliBeIrU1jxvoh9NzSqGd4wIMU0Jv9L/nEto9RWKQxgLZrE/OUbEO5663PdZUy/0eguX\naRY1m1ZF9kC6hkVqHhNsYRLMKV2kJmRxQS2qOzxCn2ckJED4bbtriu2L2SUDzh7e3NrICLFGk6Qc\nSzUk4w7vLoYRSxxoxkDVPaipBLtOyNQf3JSlj4PlfjJt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sWmC4Y11A7VpGfgUt5DdyPuI\n4f0c/+liMBy6TUVloVVx/y3VnwHJtOomChs6Id2vlq1iA4pI+uVnzbc/tq4PdxqcLnzMBOSrfZDv\nkH+L5CZkZvlBrs9bM6uMlFDG/DTjdVynNKWqcZME5CVSgN2P8gTAkhlB5dqJa5CRg3+Y7OtcNrto\nkop9l+LM1AbhwPWf+reRsIv3Wq0iwxU/kOjRj/vsLAESd34YCc/D4qth1RA38HvlyS+Yy+AHV/d0\nrp7u44rT9P6ybVJG9Nk2AMAehiOViarp2RRyiNDBOsjzN3oMwO038nNpkuVlRMzNklGtCe6k+M9I\nXFonGs/WqHtpfKeXGVOpXbD5nP8GqTrS/EUlCegS1kVmdNV7AedY1glGCl4fkcH02PgJluEOVAe0\n44WPlxPiLZ8Yl9eHc+DqK9vD6COI+SnRhTYxmMk/JafTFSv2+FP6DHGpZNsTfGodxn7zPNYLnowM\nRUE2LkLTEpDnAqMnpIoE2Rn5r10drfYWFdn8lSt0jgqMX2jfdX4RVAf/C+zrdDk5R9fGHgcGLlEh\n0CelIFG4HLf4VmZr+aq8nALGK5XQcEPzcX5gHimUFYIGpCQRicMM+NpJNJ0AsLOhMSYsjLODccp4\njuH5YAUQu5ArwGUkz2UObuWNjzXr/0mbTSDLCr+jPt/COm/qsieNXvLxEgYpFoi6nNzdHRoKY4Ac\n1NrDE/h3S9xqcAWJ1iw8eszu0Fg8zbalccZXkztD/R2HdpuenR2Mdt8e8UK+eBsisOrOSoBnphNv\n/ABoEvNkbj47YF4U+yrt9S71HVP2nWXetWCHSDJT4tE72EwJkhzcldndjNLrfgiN6HDeO3uHjzdm\n9Tl9OyWKMTlN2iXdKghJnog1ggcTH67OlJ4knQMDErA4Nuq2OPwZwAMgdqAzOzyRBkAqJz4qGD+R\n1MZ35yhuer4Hp6akF5tNCp5ksZZXedGj1nG4Tg/coBtUWI/L+Op1kd7wlxCLSbaiqT911TPZ7bqJ\n0xIy3wG/0kL5gVlTMosp20w8fnCX9X/R1HxhhYr0hYO+z7Kfk51vgXKj2SoR4d5Hwae9VQREk3Wi\nqG8QM6KCeNL1ujRlc8xxh+o9gKGeK6ooFIIFobvTU05Yas+a1XOBK9Xwz131np9e/oXazkszXwRe\nEWMzjmQ8gpnXqk/Ts35IRVpLsrDE+GmcfU7AIKI/eYTvawRNGR/KCitLD2dDQzDbUGmLSRrsxvcA\nD0xSHigP/ibeqfiTtqcYhdv3PjnyE7jKEV0C1YZSF42V7KdWYa1fAZ611pvOgGPwzjr6WlVIdZgr\nJ6cpAHtRFbERNcj+LS4pyhH+R4gSuN98LhWQLNfESmVQDOEoJErwC2j+OZDsTrYg21VDA5hoCrHB\nk7q2YZQh1y13iMqh64OAceT5Ipz96yidf99b3Cee8S7pMX2B/WEnI2EfCbKiX1aLEhpQB++xuDr/\npxrxgaSyYFq0+9csYPRnl9WJTbzRz4WROF0AFSkNUXC6gMJLyXubuaHoYv0/PBU1DqB2So9KjIrq\n19ADtXKxHc4QYQHKpitPuP9ft38uIHraFDMKhTS8kTFpGKt6ktCG/BMvO9LSWOJCuugvi1jtwFfk\nByL/fQnfkDxac+2A5TaOiabPjGbYGgonxiEwzqYBK4AxLVQFlr4bSKzJBlPtqrUmcEIlvAHyrV0M\nTVRpAuwTfCHb5YUFj0Lx/ZX9bsoJGPkQF9SXVBgY9RJKMpDqMnkWFlCawEBPLf5WEzsvYkuSVbx6\nNJ5u2pd0qp7Ox1oo3t5Da2H+Yq7vDoCBp55XOUFzFCcAMdD/wj31w2JdHO81QpUoQy0bJNniqnf+\nWc3nF3YJ15zA5Ij/ATlDAAmKahSkEw/g/nfcpGsa4VOlFvoP2E5Ll7u7aUXfxMHv7ZVRLS3m5RqN\nVwVUey3B9OIx7Vt5OS3NoeukevWFwjiqLfNq2bNAyaz/DI2KHq5/sCvx9Os0WMk5YT1tnQ7ontAT\n2vLmZl9yxzYI7BoibK82KaUmRL/W/JAqM3kd/WpPZ8es3IOYaqMP6Vx8Q48ViFKFtnSQIdqiFOUT\nggxgOl7yRTKtmllM2f4fFOE5jG3tfrtklm89Kcb0Y9R+BX6lXHQMzQv5EfYmYyoXSDG+ncZJp6Lq\nUEX4Ie+NPRD6f+3ZVGcmOEEWsmV95jdCASJFETxY2R+KgYpPbIjDuW8uWkxK1jBjo5QYbTPK1Xfy\nrbGmeVU/c5uRkibOnb1i5A1d+svPfUF5XkzmsetvfKKOclvSX2XoeSULoeLwl22HWdpmQo8eLaL/\noqpwoConKc3znY9HJdh2Bh6yCR/0BrlSfnFNDTa5ygbtOPtg6pER/S8tRlhyIi/Et8/hP6jJSOWh\nwiqM2YA7C8snbWhkzyMdiFPplu/sS1TmjX6JgnMvcHK/WTzHtlttJ/7hFgUBo5vS0NzPa2KjuKR1\nnnYMxMb8lF/E1l6AJZSkPvGYZWKd8xVF0IfQDcY9TN2hIHOrbXeY5YXW+//tbR+O2639X+a6zyF+\nSM6T+6pKtkFHYY+CwHvW2vTzgwLmfRqqnoMQM+MRQKuc6V8j7VeYaqjRo53awqa5CaX7f4qHgc3K\n7V0ekyNbunN1k5+1/V82C4H2g1R4rb2oLYtFb+4uRglxs7AdJOu/32Y3LuQRgBMkLWQqP1prjogD\nndN0kBs82prt7/3PlEggqDrr00/udoiHBciJhzG0WPM3kDrD2f5U8Vfj6YICL7fGgJEgFSqkCt1Z\nhORPmvRs9d+S+/5vBdB92X+1ZKtQzp8AxyeRsIZG24HlYpONLh77QrQ8Rs4aB9cbiSTJLcZ1pYc8\nDDLQIdsPNxKg3sGeHQmWp4vMdFcxoyYPgeDb1DslgFJLy9lKIWBpxgCkpLa9Cb1xIvdup6z6xHZ1\nXgUB37+C9HlEPPN3cTWRyI/RRJtGx25g6B97LgnFZOYzYjca3FxQhehpoVNz7SI+g/+YWAnl6kK6\n5lLBWx0XmwSI9R8aJBLr2rHCAlBVxPEIyAjn0Tweu/1KTO+MmkVCHFOlPpFmOwe315lgMYRXLQvv\n5WX5M+4jgi+vJ+UVP60piSmePxsZrZ1a9+oZl7uZUMczukSWXb9um2EzhbdXyAjMxHLDiCC/cyMc\nZ1x04dnKSCgZP3G2csbGFsX7hoz1QHwBBXAkge38WPBlrXd1G8d5AxZnU7vvaBX2fwFEbP1bUmi8\nrIQ/F/GDPYPQAx/oLv47W1qPHxzm7utLu5JZr445ghLQIenN2QwnuiA7ZTlLL8q9fq9n1T8m/J/E\nkJeGDGBPVpF0W+Jeq+M5UfrbY9vm7pRiQzEYQ7ShWX+WZV0lrXbHu+NHSkzDfIdckS3zb7/mUYDo\neBSsAoBwA9A87EOg5uqE7Ia83KPWO+Hz01DnHRzqdHwZbtkYEWEoVj2gFw8q94ysrLMM1pAT50Hy\nWGIzrQ3hQOMJUyDjvhq077U1GdIpA7BJzEFlZToiPfgYW5gf/MzRFVjftLtBVQdwO/ypWZbEiIRb\nAEoAb+x3xzWZ5A/5LECuDdM5XMthQmiAqQVOvIUnLe+Fyur0V/EpbduXTLcVuSX2RuJi9J8Lvdk+\n170NU1FwPuwPdjyR3g6xZiM7rUjQWTul7e4R9exKgSPTjOCWgnx3ccC58rSWItros2ulcYnAd5AB\nOiVrwIOEN4UqDahBRC1el1dAON6Tci4+87Rix6MsvkHePEDvwgQ+Q5s7482wvMOH6+pvuqR918ME\nLpjIhxS3uwpzjTpLSIxTiWPM6fY/i0GgFVwIQvYMe8QIQYQUZEtQQBPDhBkKuBvEmXg7ziktlWHY\nOkV8EOJ82pMZYEicgWw0eCK2qHo547fMX56AKFsQ3w9n6HB6j9TZpduyHMKd+jzRY/7n30zyT0zA\n/VQ36d7D9jCV5X1ZSFvqY2BH/X+0WAg1jti1kHY9TKVMDJkcyBTBihb0ROtr569vne58jJU74J0d\nLoFUMVdGKXBzWmwTld/wHwgYC1DUSYexLogHXuqNCxD7LR6A94dIBHSqKPZNqzq4ISDPXU9HYVLk\nQoiFt/vGfImyiwTItdYJ8XcQigFym52A69dQ+cvu+aQS7UL5eHzVjcYk6I3r4/ORvoBkD04yWU5j\ndeB9qHDOjxyQQ2Hk3TCztPpA2dwKKbgqiwzMMGmmWOc2wSQS7zDTm/meLgZ5Xh5l1ptugX7hXbu4\nlDOfZSWzSOW7lT6auI5iTYzH0+V31rxoE81htcISk0kEHMjeaOZe88QCF83/iuUxZcDyBxB/pouL\ncOBFXl4b0mjnTGCaalZDYELElWxe4JofA4D8ccuBLX45s4DnJhIaXZpkzTtv5EMJL2Z1BZhI8dm1\nL66NgJrqDc8Rk7GVpIxl3zn23g4BgHnU0tmslCnRio9LuIwdyOq9lLnlSU5nWwrmuGS9EQUwaIQr\n/kQ0vsrAW1vx/Riwc3KdDe5OBbJjq+Y8rQlUHRvD0PEmbkR4HNkh7MHRnfvanu9u8bATtDpxEEjv\nd154gnyiWeq/xWPDpOrEsV8UGCzShfjMw/5K0zhlByNLAvU1Joz9o4Km+/yDcMJxSXLjjqF1LrA6\nVJ96PecyJYlTi7qnxkGzPrSOGajSsdoXzFogK/HLSTzaqe7lI+nZfUlT75t5gB0SfuWFyx5Ne784\nBZBpjrzjdqNHiNrT0phac8CZt5h4+mVqhwGmM/iAaseOzRABNR97sb/ib9EGBlVwFphMQnzo5sW5\nzDZpkw0ha5BUX36RPYFr+okllYC3fhW1w4TogE5Qx3sRkoo+L1j+j35rey/5bESXISTAigKU1zhE\nS6M16mYmIAq57h0+EsNwY2M6B3wkY0VKYUXv9zSwuj55iOjwwDibyTE0gZpp+IDECR5bgCOiRtBx\n7Ss0O74BngcJUkpDwrFhlbyyUU6oaMPSa1T2lIPD2GjgMcRIsWbgG3FbUoCiMa8wdJRqqdRYNo5F\nHlRy8jmoR5mfa2Eerrx0qclEwDuluSvVK4KCdEegQr1bQOHxgmHitAm5rGMWZEX3qulI8ykrZ1AZ\ngAsBLzS1SSDe8Osz1YZLS3/L9s/W8JiHpVS/9IwCwOtuu+cuw4wrZ3XhltZbPPrv0p9UOkRJcEgl\nMr4qrDRi/UKdxfCe9qOQbZLH9bdUHSCnEdKPplC7G7QN96cW1ob9juhw1ncxcUR/o/fkDbOzEUQl\n4bE/wRyiYiz+XNFW6tk07LTIOPQR2IZcTrjzSiHdWJH37bYTzjGpIl+TFmaDMwyDvO4j3sOjUyTv\nuOTxpp+Uh5jCqipcbykdYheMKquU4c2gpZph64CQtT7N+cDHztRjCgBMH7CVaR8OEF1yeugKiWMk\n9Tkg8fsQsT7+JN8/fxKKzKyD5o3L3L85Rx3CjXgAbeufEH19E4/Nh+4E0WaH7AZ8IBM/E4WYrsHI\njDhVTUDzyN67I52YqnMEDFuLeMzD+65iDmvf4VKp60nNK7nSKNqSOl283HFuquuCFk6isHkCHu3y\nfqxdTBFhRsRBMpwjBmK6+ih4qbVuxsoALY2T+LTcnNaurBg4boRvgI27IHyCSB07f9ya8RlPsdBY\n9QD9MnU7qUqgkHeJO8psQ5Rnv3P3OSotx4XJM3fWuLlIW9v7e93xRQAfdhqp4vfapxJLotSQuqzD\nM0qp/gk2KWrKS4DXK91B+S/rdnhgvUBvxVuKjiQD6VIvCPXOxGzkPqCqK9elHwO0VWEtPwjnFKKe\n8y5o45K8RrwoDX+hpnhBAERTb/QUwoFilIW40eqGgWOL/gwOiPo58B3p4GRSeaIBNn8TnMuXAq1p\n8K5rVpBOE9F8lFu8Klm+DFe9XVw0oSLnjqVLlhJAs5yZmbCHlg5T6mCMYptw9t8RbuQwDXbD860Y\nKs4Gz90fQw5T7CUMhNwZSvGmWihgBoskn11/XAWUGmWY9BGioW+VPwjVIRpNVvbviLw6sHZNRazp\n2DuWANTv3CiwLLryP7tpKCgzu2uCMV5LoJu/Z0kWjKOZC6LJJ0w3I1kyPsggf91t+v+f4mICydBf\nRrJd9GLz1TE5LmD3Q6hynnDht+Ax6wEyn/5kIWrop+bmBfG7XqMrx/VUOy7EkXVKAsw626LvBWSu\n3Xw6jn/HtUe/Q+MsZBVO1b8xvAienjGTK1Fg1ysNCD0ZfI1czrFbVQZ4AZW8AiDDYB0sVv9qHv7Q\nwhru3I0FS3NDSbaIY+hlk76QSnq/l/jG9+krS9rnAQi4PlaSGYz8QhrlT/hed2TtQwqtxGNyVyFC\njkHwVGuQ6FlH3o+Bd5Ygud9mYvCg3FyJhoJ64jfB5y+6EYn2PI9DoI9cS4tYkd0oTz1KQsI3N/K/\nOQPCP/KO3DBN7LIEk3YsvKfNbyHkPZ4vH8k5RAkB/5/vMNTUwTfAGsPcxVXLHYSv4dtj4FoaRaZV\ndwDAe+3r7ZCrMAjHw1hejhraJgb2j8ujw1Y7gvjQ0dTfO/iLOC2UNNRRYTgELzijxV86hABH1FNI\nhKTg4ge9tparDfldnfr3MIOS6EU6Dxs3Yf4qWzS/vNPfdQoQ6w6cadzIkzgMP3PM+mlzwX77jfuf\nF1zcQ/CSy2nG38bNWHcrt34vKy8QUgjrznTqhWivhmK/SjDdVNN+FqI8fQyX6HH3jn1y/wLULgsK\ntjhEeTT6IPYp8JoCk4rAtalHkGivjxp3xfl6qF5QSphkpigf2fXowueAeB7AFwj6VwDmfgOQExkw\niuD8eCW3rwlKOcUwusKdIOwFH74ftuhr/BS643x9iYy0EmPMZhGevyUmhcT/kdJws+twwFcxwueg\nq6PThFIhv9GeZhQeQxAiLFcW8pAxze72CEfRZmCO880s5hxpqXTcDDZOceoujYPJlSy7UMkT9sHK\ntbp/8SoaWa+f3WtjIfScKSMNqZbOa6XAQ3TL8ZtCApzKNhNvQy1U2FSjJDA2uYxfppsV4iG+x5/4\nkIkkK64ql6JeZb/aHqrz+BH4NVIvk1ALHtab69kxpbI7BSAF1dSgTwbWB8V5PvCtLqeJT+7bomr3\njET0dhziP0ivwGQ5Dzy7XcwUw+HJaycDyUH+3b4/hYa+svlwCc47QpXNdtzYZj01Ex7ncSn4ggjm\nYAgEof9sM0BDfy1XoPJLaz19+iP45Zyb0c0CMEgZw0o5YLD8+aANtjp7wMIF0a4FqU8/F3lwvxzU\n2jMv3L84+mCcDuG+NLTgoYdAg5zxUSd+4aMa8CF8tEKjkn1/WhxINoJAGQCTlhDk4OfIkKJ4sRWg\ndVl9q5l4xR1xmsnDHJrU/WQmAAaBojW62vcsSpgCWbVGaAhjGR4y7dwzYDynpWLT5ME6n3cG4NBp\no2HW3sKYoYC+uWpYFb47XwZfAdl6snH/H8iPMkDvEv0WdnmjA40+7HBSw9dEOzA/Irp63HYeH/qG\npagTLYSxKCg6PlTRmEC4Wtq/uS/+GUutNlfdGEg8hCHZmcWcEX0SwoPXfqmmaEk9iV1c7nvZLu8L\nyizTKOLdwbs4I8Tg5tDe7yxjzjJhC6XJhAKFWyfG7mdQCwUmTIIIWaKyUc0xprIjPgaboXu5SzOa\n5dFGcsI+omutFIWPsvZDUnuVKpCXWBz5nIctX54d8EvHSkKbnADB/r6pf23ib5Q7WXQxW5R5wsZb\nj+iafzfjdjNAxq3d1DJGC4LfOUOPhv3Rkrb3uspc6cYOoEPsuMjI5DvNK5K/YREMpJFj32PvHzHb\nD2BuoaON8s+MnBv8enEZzeUhmld6vy9mIvFpmiRlc1+/9qQQ0YnumzIaOJJCXNG06jO2LXZkeHuf\nRbxrEccIapjj0ZJ4o2VMJfH5EUCwklYucvx/23dgy1SnUeuFSPvy0lmRgKMJGFSwhd1aa+3nP/KW\nmmabVbxX/HfXRLIAJBB8Q8i5zJ5nXYhrNHM4EPHru/SY5cmGp7JgREia78S/ueNzEDtJcZZv19Rd\nu0+bZu3PxhcPrz1H9Vpo48Gbmc2wkOPjD/658YGrbfy2sX8MYIosj0ShTk8uaDWoYpEephaHVz4V\nFMalKqrWJfFfiZNylm5RYSLWBZ2lWX4buKhW4FnmMQLOgYhH4CFXpsuW5VBoexomX9KoMG5ASO69\n8WIhc1ajAX6GFS//6by7B7cjMhT0oZybXn8XJVXfgsfcSazDdhOHnTEFyK6XUuXb0AUksk+76jsw\n9M1Rp0qmMdFNH8CUkHkIE7stp9YKt6zLQ4g8wWkUHrjXWjZnc+tZI6Ew5VkeXtbZxUppZUs+jcpR\nMqoV78JyMxbXL0IXxrSaZvMjBPA2jTzon0uzS9c/3TGzqTWUaz//EoF/I02VBBqkJjYr5ZaFfXg4\n5QNnDgtX7DbKVvTTx+TJV9iHO1AEALDCwZH/R/9x6kxGpfzQNKX7rbbEPiRSzNoKmwOiFUEwGicL\nfVtieBbwjnQMBiKgSNjgZD060INgwQXo6rXx1qQHMTEEOLYoGinb4Hp89ASyeHx3ikp0sFQnNBJZ\nrQfjdPvF/jdJTPyTPQk4QhNnv1jZlxy+5rX7S8gcqAQMUg2tGzO+stv+BT2Ylr4ubE3ZED11dobt\n2fbzAT/dRi5lGiSWNyjEt0rrO8gL3MNcLI+EyDCQBWPNO/aWOriOxBQCbNQn1dwoqYG3bl7ZE1g3\ng9CZr4Nt+v6LOkrrZkLtyJKKbCJBbunAmyvc2tmhRciX+TmFwimMDrrld3W7MjoPDJ7OTrhu5YDH\nG32K5iZIE+Mud+b0PesQyJNbo+E67CJ6AtfqEpOHVVOLwd3+HdfaPQgIErnDCc8QNRHOnxTdLdj6\nZyO1hKqy3TpqwRZAbAu5cTg8u7+KnKAmk7soJgBOuS+OUqvwD6i26jzYZBwkGUOLnBn2dAMr0Kv/\nY/6iYbMFbpvnpw/Qb56WqLsOg7hsVM/9ow4yHlemLm448a50jxY5X3/TRTlh5v14gjwzp+3G2zKa\ng/uCTlhOdABINX+0H5epFAxIl5BGSoIVUSVMkxKDEiJXRhkQnUkR65/yyxEx2bgPrGwESmLEe7M2\nJT4LcugdY8ahq6s72K2czOtpu614oNFIf34tkgVFOOlx+E8iC9U64tCIYwUDkZ81V8NuPeOAPuk9\nWwnmVRhWvQcbxJyTAoZjFTYETv/rl76kNn0IGWPJ16XbUNv0hNmqPMzjljr9OTNp2rDRtCyLKkLB\n2IHLnt4PWJ9Errpv9QsMW/f10RKJVIxe2Ghd42KZ6H55tYkjD7Uk/XPP0nnwNX+I8MHp5MN9GBnl\nUIh7KfbGyTla0EQKH8p9Q/oK50zooW35Osv4lfSvO0v2Pe0hhBPMiMFELIHNkL8TBe6oNAUGnZ6q\ng8FA+szAXM1sv+p8tiurm/Ylk95OZ1jZLyq8ab/sCHyaKcF+DNO52ku9nyy3XlbGhBofJq8vj8yf\nvq94RBlx1r+qDP78l32AtMFv0Oyu/U17GIMj1cAiRWPb6dhzFaxdAB5of4FT7QFC9WBpPLlNdbJ5\nEJzbHq8U+X0Bp/cQZyysPLsT37jiksQE4UKjaoewGjHvzcEx8ucUkKN83vnsc9r2td7UFVfkdW4Q\ng3MP0flNHxzMQjQkZ7ETKE1ugJuKuGQ5aCyPJkw7WTN/8KETttlaanJb8G1qjeym9PXTOb2TXgFh\nIIGRNMYDN626fMpdcPx4JbJYNN0FXvUEzmKcRh5SvHdxeWreuLcFssWrxb+yV906kRNxxB45V24Q\nacztFibYKrTjLIra3euzzX0iUUV2PyTNli03W4Wgax6UFYF30iBL/i7cdriP3cX/LtOXREKFIyhF\n+e4BqtKRol+hpvBwzluVHKr9dbgVyb/ljVUTeTSplKHdJSeyt51hFIVBKd/8h7fsMdyI41+aZaoh\nRga6+ZSIB+QyGOuHrnXgBzwNDushPrwZ57Wk1+i5B5pzd2ph2NyNnlRPImkrNuq+kUaEbBWr7j3C\ntOAx23OpLxWxI/rJqrOH2xpF1A6zl3J5Ko0LbUaH1mU5A+lfhY7BTraIFh2pSWW6EE4AxvhBnVDJ\n6IdeRm03vu3qDXiYxx31rySYpQaI/ZozNEV1fGvpKTyFlvB9soRwTkWewiM2oUmfW05VLrnW8M07\nvf2hRPZoFsbZJ5/l3n8KHFk4mpSa4QGPQ7Z+2/d6TSCcKunG0Rq8QTLAHLZfvN3Ri553jM+FhcNq\nTv/VHGucU49ADey/aFaFXwjIr8QD8Eh1FouhRUbWcOMHt2pNGMjZRHaJe6n536RoxXWQVglm2aBM\n50TngpRz3ALwCEv46sQGPIhY4vmFKWSt+fGReS7StDETxV07y84CR4WestuncblVe+V3/BMjLJJ8\n2crhgnB4aaAHAHoy38NdtZO0CBvixxC+9AbGzbGBR9l8pVvsA4LLg+5F51vq+bTazgqt5D6k+2nU\nAlL3CUEqiU0AjkBefcroDryLiXyniPQtaWKJPzt/oGqxBSoTT6tDKRRfA3N/5LRmjcI3nv0IHcY5\nyItUL22iADBxXRfGornST47f/TNqt9eK1LVxIIK23ma+sPHW5+GSwQvL+SNRGRc9nZwmafHVbk12\nvGhQ9qVUUyk0fiU+or14YdRlcrliRjurYrVpmOwNkKQFVAJSv/Cqys3eVYp3DGYEq/+Ie6+MMVkv\nBi/l2o6depl71H13NizuflAmR6fnviBY+PlZe7TWE7t3PiOHAmxGdhTsW5TzZdgycZIvaAxbd5vh\ns3rmT6Cufd/VSpzTnkYHrQ4gU/kVxryUwo42chVlzmQDIXR5yP6nq9vrf19+hERFT1hZQ1dODETv\n9BsRG70Bdibc/6R1RRERX+m0wpNiJa3DNZX+xP1ERutpKokyy/FpqXktslI8yxVyH7ALc/prwaAw\n8QpMRl5uaq0jFtC3854AP1m39qRgkRSOMRtxXD2zlR97aTz0YdZiaxKBtAgA+f42DyYFG07ZRd/Z\nPKFtVt6CAJcvz7JjFoy3F3iS00OfwfGUcJq2dwIMgbEdSDcD6KGvoeifdyokQCP+pm0bRJatx1dA\ntVFsF4SMewKmsOfJXtj6aKzduCY4GBZwAxNpQsdq23cNFtHTmIXDAGOcxgHY7kspJ2aC2MNuXX9G\n3u0xJTNbnUsDs2EsNq+dGVvNW2NcySbOAd1oQGt9Mi//fnaRyYPbEIJjhtAFLTRJW+3irIXqWWRF\nfz1AlxYg6cmpZeJ1hkzNqOUYglfLOb3zuOPes3mD7bA6PZleH+kS52+L9o6sQWxPi76jbK9/95zd\nqZVEEIAuheC7d41fpDveJSObtZyFU9K8nZMmm8Frl0/MyktcBDB4yp45xhXI1wycFs340z75a3zp\nFbvs86XMZbwNUy9csX7ay1qinY+GPLOoLQwsUQp08GXlJbWjBtgw5UZRWSQYpne3pMUkxks6HMzi\n9u8PxQxc1xEERiDe8BONM/jLhYRbbcUFeHEgQazjX7OzXqbGVlTVa67tJIcP6fjrv3V24OIyhrPm\nQRAOuCiK2F3tTwzegvQttSeriqOudqkPSR3IkDI6mXegnBUpxIiI8v9BMvWufEvn2f7X99h0/G4M\nzOKujZbIiNNd3gLpIDUv899g8PQVHSKP8rHRs0nhHEaWGu2aQupRM0+Guwk6jApVatkaqIZvblwT\nUHx8Ryg1xDGBDSOAEGoUToDGTODlLTzchF0/s3Ih4Kll/sdA2sybyxGQMG8DQGwoh8NYHp4AP2IR\nVHPz7KFn3OlaE/B+8Rqx7kshHd4yI+P0HegEsSSUz5UndhyyeLaFx3Tbx8EnQOGZ+msNVdOPXJgc\n9gJC9DoTb37EKabFmrwQ7nva9PMVnA8qXBmQSIxV0YHXx21Cj8uUGXToQjo8Fyy4tngm6q8uEFdo\nIfXS0nhkBFBalUkItiaJ8ToZtDTZzsIp5ukKEYdwmxN1OmzAMcTKH0ZEUyNGbV9YuKh7QK4i6UKB\nXyTEUsFtB5UOosjEDDohpqLETYcvWJApDaT0RtLWU9yTu+SHeSJ+dIpnsFI+WQsJegWLQ6/ugejg\nYxz9BE9dGXf/qIZinnCHbLp7jAM7wKeFjaMNMW0py67a7mCyaCWQoWpzzGXEAb0rhPHb+gJqiKVM\nMscbL9jTMHX6TEWijCF9LUzwSlCtsn1wVeglV2w2X3bdn7ZrHPkw6MDMdP4Bcrhtkt5rF5dRNSxl\nszOoZCIyYLF3OGNSYrOnqtE+RG07oaoTNFjXAlYx16vFH4tyDNHk4xpVc9359phpzC0pZbBkX6zJ\nLz4BRhONHkJiJGiYw/RG3+87gCJBlaewBaE+oFpDY1pJJWKODPPsZ9yVAAw62Uc4qYYH+871Od7M\nitG4AJQRGCSUs1SgMRaNC9O/XDasEF0k6XyulnTKSor1umenJjAyb3Bc69LQQVOb5Kt4GTb+qK+x\n42iU6u99UZObyVbN6Pykztlkw8eB4NU+/8eez93ZznFwLQ5FBNDgM8v+uONuQCNMxqMlHahnWQIL\nJH9de5oEftNJ9iOgdlBSpl6rZrUVkPPcyWWJ4roTKaAZ6D0hq/Pj+k963mmva/j00vPMA1XKYmb1\nD3fOpCcFJE4Ek2/USp6qh6b3c//IbSd9YqEB4QT9NdDiT3TklxqiqSpi1lTqk6bH21/aqzeHTeRk\nvrytHbdH+tEAAzdxAwWJ7jQgW23if8RLt9M6mO3igURnWJ1OTA+aZnAY0VPWCUBU102AouZ0RjSc\njn7WCQDZd3wsG5pfkS0h31XG+jtzmBolzgn9RVRSoH98Tbkl6fgnBRLnSvOa9AJ8rdIRx/3K6sXM\nhCDorXBf4ci9Gh/KolplYiQsZFWpaGB7LwRlQQreLInr1/isa3rkIzxSjF/tJBjQrAoee33a7UDQ\nUV/CgO+ONVFGrdM6/juLe4eLOEZNto1BVJP57GW+FkcLPYRVLlwiLwApXL7L5DeB9rm5zle7AcxQ\nB2mKJU7NGP1LCd3pJVJcwJA+CHyzAVdEZZcTMrnKG/Igs+FcJNDanzJoZEN8OpJL2CFfLVfXueVU\n/rHDEanUZ1d87Q0GFuJ8zzi5DxL8+k7K19oAxVDp2k/Js2hx79XGs57QgW8zDYVDt9bsW/bvqFUu\n4ZI+cOY20hmvAYrZ2nM5GKgQk0nGdeb2rQFsnHnLmz5tAQ0IxH0ZKr+G7W/NiBYXI6NswLa1usDj\nh3pHtlT5KBqHvyKVZgS1zsrPXRWZVq9J3A5TYR9ktnGHWO7aTj/HJyZrUOba09Xrwbqf/OdlJ1eb\nRLFf2nrgSVuPbM9bUHryqALNvJ6uYIg28jd/qcmEgZ7DFbP9TKmpBTSNliS3X4kJv3Y1xY4Wy+XQ\n0bmRbWkMBCMaGa+9nxAR1I9aSqO4cqY7BKAlBuLBAHJJoARkDIFW/9TfuFW0ja15kJGUlpXfWGmq\nFw+0uL5woHZexoK4QwjDnYw586SUG2zk1dSjCCWO2YIZA9SWVVUdT4wfy0Vd3H1H+dl/IMOFjOdT\nWQYxKFmxrowpe0UMNhbMB5gbp/RGp5gbVQlUFIF+r111XmvWz7ZOR0JKEJydgPhWlvgEQwYeaktl\nbxZAtkoTKkP/Tc+aOXQWF2L/CJ72e7riw6DAy1E650VA5Jq04O3yoHDjpaw19J7No8QRhUNZhA3o\nSkNk6U5m3fLoM9YPm1KIWmeDkfIiiGanEiLlwsqMDa4PTKqihaeWHdc59nLi34w4N/CCQ0tkqZcQ\ntdnT9H91n6gEjP9jPtigW+s6xAE271cSbA00fhBrZpYSE6BFefMkb5dlomnlRhHFsYbk2Uxjo7Qj\nvPvqKCNL1sSTox0BmqUVDcOjzKzv/VQr5UEq7tRaurS2+XzO0/NSuvNxBXbq5eiLiUQWFDMV+heg\nnAKNvYxQdb4rdkgqMRzF32mJb/qVr+oPdyzvIccIO2pW0A7hM7Yva7XI3x7yKFB3XZXkKUO5dAEO\nW5TPBulWyiGiGX5NDT4lTlSye+rbhCs6wfhK1FWQvxEstUbM03fbmUBq+W8bjiPorBsLgj0aX49y\n0wsX8e1Eu1QINMh19fAyxU8vBaRU1Y6X9Goc9mc1bQ7KBVv2yNbwoEU4Mh7R8cH8YjiwvhSk62RM\nnMQs+vJtm7A2JgUtPdcgSXZ3U3rZFvvvT6Wi2eWzFmnneDv0p4Xd5/6t2vR4csynUlQOu7EfUBsY\nDK5puvl29AJNDICEBfdaLE1iVmXykq9/wEU+hznkpXeQHxhiesJgnBXCNNRYFpfa83+1j8rRAIrw\n2tZKy3kU7/M+zfafieWnaomB4rgTTDt7/KIvK+kUMFBmgeRJnlWveCIJ+Sj+4iF8pK/6fOm8cfP0\nBHAwvsvNSY3RQYZ+VOjQEM11GukfDfsVMjTvxjiMbKqCLU8843YQtRY/MoAvWzrnMjbJEV99yGUq\n5nmORmxQPWdae/gkkJ/lUjC+4VOzRfCR7PNWbn/PT2E5PHnLT949EI5QZUt3dIIc8pXHqU1am1zV\niC/4+M50hQK67N5UvGHyiGDxTfbmDbDtsLDSIck9dmgnTUhF7+8+nNuzm8tUGPl+onVCeQdqda4C\n72GeTSh2SfYKOWg891v7UhtG/kUPRShjqiNrQcwYx6606/Sxp2eFkXm6tsb4yBgDxPkUmkyvBsfW\nul13CHPgRditjd5/s1BcxDLb6esY1AgALbs2WP1osrN+f9nVtpSBPYHxjhkRbBMCyh6wzHExuywg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PBWG+ZzD1emNAwcvc0AJ+YHH8lKJFlBhcJWPBTT8/c1mYRTevcJX4ng3gI/fv618jYtmdO\nSu6oMnTXstWvQ9p/fXzL/lQsb0f3AY1fZAakvGMMMZ8JHPOwfflijDx/U0Sa5mZPSzaz2J0dbHxv\nVIvzMnfPhHiKf/+QaEQz5fzj/FCi8jU0UrRMmRuIlLV0bgHLH55Y7nTQl95kHMaPR7kk+4RWwCc7\nxPgXlHW3cQAgvLapaOGPWqKY3XmXTSh2BIeuarzJWCh2qJZcwZNd//UxRDaGseRW4lo4BGUecARg\nfutqZzJMi3hAsJrQNTBnns+Vb82NNF0isTWNWRbYsGQz+LDz8Bc0tNpaWnoRTh6JyCmWq4OaciNu\n0RIFZg96p0pVFswSdhhvIIGYmlb9MZ4O+Fl9e+yqe9XXq/+fsmXQaX4PrzXh2xo8wlMH1kpOIqAv\nVcuf8FYiHjGxTxItRczwzoA2BXCymYVBtaGKBdbSwt2GwneVz0eZMhltamCMynUp8hYwPD1llMJt\n4ACx44FpLIVe/9CL3WmIzTamThoR7JrvqfTkqRirYsAtyhDj04YObnKfdAWxDQXnLshmz/ZVEUcc\nCGKDfrW/lUVJlEfnEX8+Ayna2ihAl9mVUWjZs7WXTizJwLhwpFt/nElMfkKKe4rsTppZj6IS9SRo\nuwyPOEXf+yFPCpksGJDp7xHCZ/gnvI59xnBpie84wYvDs+fmtN4g4WPtP7tENTqTJlydg5XCPG8d\niaeBnHRN2lj26dOjMMHV8Mv62QIzXkkyaNUW94B8PITwl9NjapYFqo903gWt99DyOTOFZcrswOIV\nKcxFOMyBTG6XUQif2MBo+koDQ089Ze+IE1XxvK14seKalanoB25iP/tEb8ZlCDywLtwD1p+6jLYA\nBxlPXAzFLKqFyFZ3OVyEUQ3FNitJ9SP8LFKEapIzm7NSEjLs4N08X1YsWw0BKfX6rEhM1CFvTgNU\nsIxsMJg/siAaZwf35U4WpUfHsUC71v+jaFylDJgVmO3kVQMmcWUJrQUPD5ySh2jAOueSM9Gy5Q4E\nlARVtTaW5VxE/uLWLoV+EVsKPZoSPmosP6nzsJyUYQxOzUsTk8H6H4dFwBrteu69euJAe1cTOVmc\n+WK4iczCxQt4V97nSsfDQuuparxXjkWYbQxDOicfesbvEK1S8Zg+b3ji04eHMOkjvt3+1Xhrii+C\nv5LhITKADULfcZFui7S38G7BcL5YtZ5Mz83NL2Bs5rLOZXTC68OyjQW1zVkUm+VtGyDUqThncF67\n5a4DzllOKXWji7rS4H+ESIV5D71sIOr6axRjs4Gs4It5qXoKhMzd2efQ+659F/bzNDTI5ZOMaTg7\nmQEDR8x9A8V4uh2PmIhAZaYwEMrZ/3gy579F6ZTb8rvZLpKwJ2IqkkwCFmOvMn4K/3lgR3UoEbX4\nUbZGBAQGd2cypZMOM7uA9ei2C18amTE8OjAnbNrouf9RA3SA2khtEIglBydDcmLjTTgx/dyhAKNB\ns5Ct3H/IG1W1TTnDGkr1S/Vsfbs9l4kHNXMDJFHPN6sTlSK84iIxN6i1l4OkhH4O7aln8toQeZff\nSLlSSS7Fjbb4ZGT/hfslP4LaNx6Kl7viE6Aw0xQ5Lm1O6gOj8r2fkDpMoKntaint1ERBXFObEgzh\nqRPPpnS2iF5YJ2eGSc/b3HhjqMShggswYxxpT/IihC+Ie8YWfNNRb52210OWBkrAYEius1kwO+Ai\neAfo7+IwCsl/bcIvjKYXFnCY8yuUl4eMBOjBrtsUk4aPLUWb3AD6uzRX8o1BBqHUrqpUGDclF8wC\ngzfrOrGsifMeOgdP+bSfHBjtJPWooIPCWbaOqgs1NuTRbWf/Haa58pUU9YuMPFvG61R/NVeBEBeu\np7kSuIDpHX7XatEcq3Q/7gs0VWN0brtIv+JHAqJEZyzdYacn7RW0tTg0YdfFNwPb9Cfg+kVnGwol\nGQhGkxqpEflN7p2WuDxqRxiJQXBwiEAs60bHG/QJ/PukrgVpQ6QJ9OhDXMGRlLqZ7RRE4NUY5zXh\nr0WcYM4hyAtRl8pbJks4qe+amdcbNGZhgQzf/Q7moREqeVA3F7acz/KoOySzvpX/4XJ9HO0lNfwI\nIy7Ax/QLsJ+ctjXA7FoWRqj2c37DSUfOvvJPdPz8EqmUBCAn5ao/7X7U1OROMIvtIGLWcpg9TLMI\nR1WAp4diyY3cWvmcD5gVj7hshTZCc+09wMOlBsA6XA7eAkL71YAMNkvbSd6f5yxu7KYIpeaEiwLk\n+sy1KbTCVcUtbOVdM6buPeJ2dJw5K02eS0kMWL1yArNqEjVQT41/hzUq8LGlbaKM7OthvCp7vmon\nxWjnpMENYllqw1qp155QnUJ0s45mobaYcCZ7v97pkAXEAwM2o9OATMiN4PHYCWhHRvKaE94x2EcU\nJbV4wIpxSda3wQHer9uOb2BFf6fLJN9PQk6LMV23pv1o9AbTNotrVAAz19CeVGXCoRMds2F9m1Sd\n7Kpf9c4luy53eEdNGxFTaxlRNeDtAeuJdDNkyHnMWsZFnOuHuAv5lEMHyu+IFzmm/E3jl8mf+Pm0\nFCvbS/AlINYU5FH/b/9hKg0ycqCt51m2vlpIT9TbbB7EWiW9rER/h00QtvWbab6I4L7TT0b+wiie\nRKvg2ioB2ArPRGaZuRmIRASA/6e6bNXzthlyMUqc0Y5kZF6hiyuVWVRDEkctaYHo9qDAmXzSPiRh\nNJ62UgI7EhE/PdyGOGjujGMVSVfDHg/S3SvjbwlgBObLkKUSYNauEcCpMUMF2bosKm+0hdOQUwyk\nXjSL7D1DgkSk+gH6rofFMo1v7GeKLEQ5UhuMBcwvI8QvyxM867Dd7onPcp80cdhTGd9mHmcdlDzU\n98oo/2Od4qKUKyrQyPer/6qrkKkxlswfbvdu9H3x39GNVzJpXdzxX9txQM9NLNUTrRFd2Eb6HabF\ntRbocf+1yoMDxdlFeKSuDyTTgMvsm5FeHEuzoX0HIHLSDtxd58haWd5lHqeSl4OdUwx8tBIwiD92\nGhfGp0GLkaLgY7rZXlVt6psh8eMSgyPvGjfaijkQG8wsJazgpZmvPF/TjkdkZFtWAjrc5MDrkr4Q\nqf7J4JV6lSU/6uUvmDIXK6DAhMA587Gfw09wXDmbAyaad4fC/JOidha+KQrnrflcCsYI36ACcxzg\n7pMmEpFY8ausne/RMKvcCC17umzPYiGe9GMGI3NJfOJN5LQzEipcRSfbGNdanqpkCt5DckXZHHjc\nxebCF7zKpp5UUgplgyHXBXkSJX6Iui69DxGNF8S0fY16SUJcbDz/dTH5R/gylhowO3aje+g8IIBr\nIQcikNuyR4j7ENJAmEyf4iWCK4CG4qWc4rc8hXI1C2yHr4SSeMylT4DINtBIuGJFAQS958nqGrwH\nJViQbKgFLWqSJeNFcBrUPSjx/WA1Vfa5B/9cPdgpZv+SHYPWy6onafZ0LyAJE2PdDf34X1TiVHKN\nYtw5vrBfKpa9M6jar6bNzOqq4n0LQzXMAgHZA97UFGgY1g4N8P8krYVxa8mlE+8csumd5dWu73f3\ne/1Lp9fjCPDZiCW5pPsi9vZIAIs1qbov7PmSU19SGGPDq42T6D+gdLgWr9y1WUmJ4d/LFfsYwYVC\nYkyxmK5+itQzux4upfR5kJYATqt7Y1Qah2knD/d6A7M1zgNBPmQGYYVZ+ulr+ox0c5znGwuOGdhP\nLvpGcRpDwjsWVwrv87CT7Z6eqVWnIdeceuH8BW7E9aTr6Huf1Yfy4ztKV+1NNn48odtBk+HOq1LL\n3COJWrVGQ/0o6eO44I3iIagSEB9ZVC3QJ3qijk21qExYRlzCm/TOrXv1a17+kXsmwgmhnAbuzjFO\nbT5c4Be2xtR8iFywporaw4nuZPStlZw0D5n8Vmz+HAhNdR8UBpnheZR0ZfbiqOmVQ2J+YkIt5uZU\nWrzsty+wHrkNQHsdmFLPpcNyoGjFF0lpqqxyFprLp5SxVcLng3py3BZ72MXHOCIcB/BPrCnSQHxs\niknNRTD5hhlhy1A35J2Lv2kgHWLvWHqEPUUUY891UpLX2vO+79nyFaqdynsJVofZMr2GBjSNy5rQ\nWVhk4Kfxs2J+c7YSjpo48PlDmI/m8Rb6490exYUspONILFuKaNt230dko9imu0jggv2H7Lbg+YsE\n/9z4P8uP8j3udcIiTdGVs3T7g+3vU+GA2z8oDdIIEKmIwJpxDb+H8swcLbRhImcrgGVYdFEzLWe0\nNISL08oAXMapIbi5eAWSBpAD7KDAsRpMvQhRmvdlTVYAuvLfkucT+OnDfWwVbENHixCFzht8WzCM\nweBnZ1QVWjEXSZvHlkg2i2zUE1zsMy+MG06Qf8H/GQNWmUSDPNgYC1zwcKYAYvA72cRvdHNakehg\nPGiP9f4Ub9g2dM4k6lCNJ6XwEm+xBjscs7K+LpOphNlpaeF1drYupJFtbiSWq88nF7aTdlAtaIdj\ntpdQISYRNGvEArILd+gMz0ArW3MbQ13rxqDowl264IId1Oj28sbSX6vNQh9djWoq1zsWPDzVOBHH\nEtpPxqEnwwmiRrIq1xuOA2HMJpDK1JAHI+StYONYgmI/fTGq/PesRsBqqCioeVLHU08r5Bkv/CCO\nN3/W3guXhDL1xG7Yugc/taEZqvCN7FKL32U8Khf0NI+ytJwLDv7bvE244jeLVFBZURBaDyJDJGk+\nAI5ac4m7lM1YcgzKq6bE7M5LxjzLXq0UZvjS/JXrVD1LJ24kf6BLMBJfzvH2oNhDLkUK+0c09I7j\nUDFK+0P4brfcxIdYGio9PxnayIk2tHTqzew7Roq2TtUs+nlxGIet+nDiYNIe9Y+M1k7e07JmvFwR\ntBFcOin3Mgy5R1ucVcjK5Vyv4Vz88jLYwPWpcxx6C1fnkdLLK5L39E7s8vURuTvy7Oi2QkHSiGMr\nYRy1iENqu2p2dV1NRdWqEfJRTsheFDSvepNES5Y4iqZZna12a/RIqhYj68E0q6hOTZzTDKdUyznu\n/DSlrKIiuRTSAa56rLV7DgNvwzUnuxFsKkaNo9WS7V8bIw+kG7k1Uk+87G0nJ8u6LrUSSYNZJZ6b\nBlGh1Pm7KUpiS9wyBZD8ukb7SzAVSXiRtzAdicwq+hkMHCwPSFRaF7W3NWOshqZ84trOpI01HEsg\nbSSmY+Hyq46sc3HneTF1vDaf/TX1BOusWC2tc5vWKOX7opVEMxza3tNd9SvvAWSEqF4wJ75YTo07\nwrHFUm/JKRY1bFUrXAWMtSxgA31wFtiwd5GYwDJ7cQP+l5vq0VteRl4ZTKK0QtrBJCXPtRMiFM6f\nKsaNFK14arb0mPr+JutFd6+AD72RWSevScBZ3ehzt2Ul8sg8kBSdFSa1Lqpwy8rzyYAaK+gH+TRl\nEa8H7JPf+W7NnvnjJYqjPhKy1jCq79WKkfvzyBzCZ+aRK7o+kjaBen4W929EVASFpF9ku5Ot+f8D\ngO87xvOZPpPG51UtnS6u7hmLGmSikOFTLN3gGwjNx2IlWsXKeFlY9ZAi8L3R+fRd/csP7EUVMjqY\nrXElfY7pXL2/wKwPkGIIOAWPKpFYG03Aq3sP2s1PLM25ZYCIjr4HDJtKFyY7r8lGMxaJw1ACgIhV\nA9fxKiKhMznHAq+kTC61XlDlj9C5fDB73EJP0rDsqEFpSLl6RbvX1UG/snBEAt0gTELayfi7RnP4\nnp3eh20repeRgnMbnrkHysy6rrB6Zm72pWuP5M54O7HHYiwUwjLiu+tbDkWZ5PAxKBA2YKgtsHUj\nTK17YmS7KwQdxH1GodYru9cLXeBb6vaJNufjRmWVQlaQFW5cVPE1oW3OQRDOEZIyadkN9nIHMBUo\nMyAQDIE4r8iTENdAnDpSEFE1E+bdUJVaaY4dSSDCQZeX6rKiXx7TD+8WldFfN9S/o0NAv7UDM5TP\nfllYRVaA/vQQPK6WOllWJclZLbIWkQno/zognHBiaehvoGBUfcnej/zP3Pj4kXj+ktJh15NO9YFQ\nWdha6IkZiv6fzWk1WAtQelTsBOUxwbYF1hvzbjldGQEOd2HhFPLQmXYOp9jAWODFJdOd9YWYrPZb\nCJcKrsty0zYDvL6rF129wAtEHVVJXlxi+w+hlX19V8ZHYGm2gheEGUu1q1ysh7BuUbXAqVNKbcqy\n24w0vxtHe+8oMlncgAs8Mf9MYd96Y1Ny7i6dXXzFbDOwe5tpQkGJ4D8vaoLJUtgTk3xEs3mb4nxN\nBkcWA/ykCDXAh2Xixt4zXhgt5o087vm10s3OQ6Os81Di5iecwhAp2oDTV8lZ6LYtSS5CTgtOo26y\nXoB/3/NWGlwhsKjsgSwAn6qT3xe9LHnIe26IWaRAFoQKXDGvIIQNjcaflgcHpL8Z26IcPuJAwwwH\naD5Y85uAYVikHGxLCakui+wcOYroRrVtop5c0FXpVMWYGn7aQTUfEq8PdZD8RL2SLrhKMTz1PmxU\nmcQLcZ9i72G3Vv0XWVTZDb0VQj2j8Tk6udH0WCk7hl1mI8JPkK+97OQK6H6ntvwNnceeF3nOj5tD\nB/JMgpSUKjfiYZcI/KwYWG51m4V6Ssso/xfQdwBtlqYQZOvDOkaBEwziUd5hL6S7q9BNDjPsOnHf\n+yEi2GrbkvtSun9WVTM/dzYrTCNSyc63/P07E+MOsUNl6811z0jTq5dehRMxtzd5hBFQJQMdRH0g\nUv80bxgqeEzmKN/pq+lBGadsGGYA6W8pTsuPIdd59Qfc4Yf1IVRXfHaUKmqnRMqS+r2p0faonrI2\n/BpNt7+H7WRjvOSowlTnx1it6v9Ng+dC1ospZSY4Z/Hl5gt4rxo+coKrwOzpqyu3cKTCD81oZA3J\nKTRin6e52BVze98zg4aGYZ4nSOcqPrU020NA0g5Kttg0BmAgZfY0HmdW7lXiPimH1S1M8spNc6aR\n/yi9I1KyYDehA3tqd7y8Ea8Kp4010lEBWG9d7rJr7oISVmS8SLX0d8isVcJ1vn1Of6GMVa562Bga\n2E8+MFIaNxFXRo+V5DQ33AcNJnm4pSMgPP1M7SnjuTnsy4loiy97AsM+lwV0m0FMzOLtWMorMU1g\nRFwCF0xp+kOeryyZDtuaylzpTQhIN1sFVc+bzF6zHIXUSSqE1unJDJINhFQjzBCChhpegqAE4gvM\n6Dgib2SjPXReIBYE4jbzfJY+lGUQHhAYd3uNGD0+rFUIqdLMMSfQ1q+0UZvNKQrag1hv11/wHb20\nlJb6+/QS4CMkqjStvNMgNg3D0d/5iXJDF6xolTxXKhbzZxi9p/9gNbmqQD2S/d/SKyu7p2yQbLPz\nkKpRhNZ/kSvzA+JOMwYo8WUnOj4F+FU/GO3zfPa41sRH5EuMG4PWqcDVeaMhiuzNiilNQJx93HEw\nNmP79Mrr9MopnzVd/kJhg4+wm9J727rwLfeb4NAZH2tP6e/0E/OdO1EWkqYYWlYJ6IT6sGSb97fd\nW93wqJXagOW0ExOrhkvnOH3sYG8FESDf9dlVQVV41gPBP6zvxxzlXmKmmlBHeAeYLLUccMFUuTYF\ns1Q+iXuFGRQ/yaXP36/7ySSylb/h2LXLR94mq02hewZ3Y0WUhOFdbEpaFFJrvyV2JZ7tS95liB3l\nGiADS5jxqpNuew88q1p8NKYZj5lWuLLv4q1DAK+Ht0HnD7ewiJK2WWNSX0CRxCjOOoCd3HCoF2Pf\nzit3muBO48RKbLoWVDoamvhFMpVGLvURHQwxVWkJccUUUWeVzRB/9Z/REG9rHxJ0NTPXYF/CdWn/\nLBr5kqdmQN9yhT1BCezYsZ0JKRlBBmEYeweh8nQ7Tkd9NNTnoK6unyujr7czrYtCtTs8AewPPaoI\nLf82vJQ6gQ2KxcP4GtWYeu5dU/YRGqm78kiuKzc9pJKK8hdp1fEvzIogrg+umgLKSXpw+RYczzPB\nqVVHVDg/EuWZmgLJnPZ9wKnwNKIJSmhdt+6BxodTOjKboikOB3ASbGXFzhNcTAQY9Ev08q9tsICl\nQCdMRXvT4eUeU0AMEBcMIhyG3dK1SpE44gIBa9Fwxw9gpCt73mE5W/KtOf0CmtVXBVNDaqAqqSQB\nR/Qb7rADXDlYoWu+swIZpbFpYDOCkMWX2J/C6yOHlYX7pskthWy3kPCZbUMJnzOAS6AmNgF+X1nY\nS6dQQQZNMDwRc2LfkinNb4nVXJYx26YbhbJPsFkbNbdRrCMklsYObOxJHRw0NRaiEIEmKfgVEgTu\nX9VwH4nALiFOsJ+CyDukvthbuUbJ4widRtzU+ty0kbU9WakgHVjoKCsMqzggxy2TkUnVQ778bTbo\n3nT1QWg95VItdpLHuiKDuDyi3mgBzJLiRGm0AL+7lTjpcWKiU81HGORt4XSvrHG/rOJLsBnD/mFL\nnYj9P5y/gYhm6b5uQVBSKij33HFlNjfPTE87F486SxaokBnu8UsfmC5mokcl5fpt5vlJryiYCoUv\nggh1WaeJKLAXyhRA9IoncSt/wEMeZDb9h9nXxKcCyXaQ7P/LboXM9IhLk4T5kXvaX/Xcl0HX+ioT\n6tUi7Yp8Ph4291vdH6Pp6tANkv4ddztwthB2j4h/WH03hheenGK554dgf77BdiGvtvaDcmId64CE\nYCa25NFD0ulZqnIHuRdaSQsewKfwRh2VzbRiwFuLz4LX+bqPXbUDqhwvXe7lB5YhtboY0NrLN3lu\noU4sXxn/QMoZHvTnS3OJOaAvJb4sYaV66xeYoOGwWiD3/7GAMmpJKpoTAiK/1WQcIjaML3AoIriB\n7HDEW3jPMnmTXVsjf7TVA+1Kppg3QSqceA+9vWaI4CXBsiSyzyMum8oisEM73VUsaLGSmVuQLjO/\niYdukwnAz+BrF7uxo5qiKBUdayQ7iPZbfs30Aki9UJIWkKqvEMKcGHomfLPZ2M2S9RcEymiGy/iC\nIdbI+j8qBxTM5jHkijItpOOR0IZnoXoNqeNpWqQLWwLzPtD21sxRnh4/obAfbGdlQLkEJK0yFyXO\ni8psAm8ymnZPHaFyjpo/NDqx4fiojBhiUqixcJZ54qgMpRKCHAUajziOpk4hNinIConhNnJQ5HSH\nTi8IvC2yIPLZFx6Xm2bo1eOv0RSMDYOHpN6rxLcTeeKg6n1gaXe7youxYAoC2SatUKryQjt2S9Cf\nSIGNaM6M1niqAI73QteUBnTInTncXjHuX6+Uv3M6koC9+tAbXi8A83lPTODfe60mPOt7u5FAMAwk\nmmX7RawS1tnzP/jyPlxgtyWU7n0GcetryiPPGPsihaeT3SgxHL31bf2ihOthHmmZVlT4NFQwUzoy\nin6Q5GW+HKIB5q0iCp+wBFKiN4WrIXMcBmxizcmPDZIhsfiB9VUWV2dM3wseMoQK4prd85aAaqri\nPw8M1LxkvJlQY/J258aWMlWouBFHmCcg22qznSr8RTC38CoOLRFqjBzxVBg3W0Z8zpUesDFW0ivQ\n7m4W/FAks4g3Aq1eQL48IdJrobAOWC8GbaGhk/GsqonKxoAZS+TP0XZ5Vdzz4ngoQq0io4v6MXfN\npIxg26OdXrWSrS3f+OFZeyFmqntTJGAsuMNUsuSTKoXSoNPqYDLed0xATLPO56xcDTTa6hGJdaGs\nkPbds2MH5V8K0Aclb16F8Ugx2phE/msfxiJHp7GVatskeUnFy9gvU2TvQQ9k9bnTivzHzQ0hZwTf\n1s3qCExJrekK9B4U93V1gothvgNsbbGhembw/Fzg2qLA+rWZAzEPKsnkemGYhqAGtGGbZswdmPWV\nMURBJdqJqOdNXzvuzgoIizN1NK3zrpC78wA/yi8LJbO8mYnHWHcOgNiwKLDo0UPyRxcQD9cyyNmN\nOwr0BjYQguCHqMuMkNbDKO0zNdPklpW0rtiG7YTfGytf13TUG9n8Hv6x+OSamPXt/2t7kt0Axzki\nUMDH1+iIhge2oefEDr0zi5RuO0U+oeGsEWydyjCYN1t4RRjEsGiaM2R6Pba2YjGs752Yty51D6xt\nKrSC3cvd1P0qBWqSN7SPdkp7YmUICivzvSipViguTAHuyP1PKmGTiBeiYnp9iwQYqoC6MNbgWAtp\n4X3SboNoZAxtBPAkzlZ1L8fMdm40baBYJTGzhssoPkZB1bqQ91DrXs+hyPy9l2TJVUprRsss4CLZ\nbWcV7sW3GPKGtMzxpwjK/orA2DZ8P1J7P0/0oUmLIn3PxThSbqNTf6+HelbLDROi9UfMjAlffbCT\nVk45Wfp05Fh0fvxhnpAQGJniZVg5jp+2xTLsY/d6I4Tpy+74EqHO4bb/ISqUnqu1JNSlGBmMURUB\nsDJGS95vTQizLSAOFP1Oh7QgPXE02+TLSP9C3ZenXBYbrE3KbRbzFfHH5Ehzo+YOlgxuhjdhtAHH\nRMajIwX/dyMgX3z13ucPCT2snurAVjXXb7TcgtSy9AWZ9PkgyPVw43pjvGq/cds3tME3FzQnc1Xz\nX7aNFY6Ou4IC7oWcbrp96sQBw5R7xGnZXbzEoMar0903fxJZuDbKKt+oxteGUVhppu636JZ/a6uV\ndJKl+l9xp7Nji98meR8I1zMr8f8ez/YZxVPkxyHsP7bPXbrag4w6nSxfVCuSCV4ha8ee1uOIT9dk\n0SuvF1u3LSzlqXQtwdCwpZzij5tw4klNdk9NshnVRIaaQMO3ZTYBo+JCos2dLRO9Fl+wMa2WzJjS\nzbQX3yDQgdUa0+gTa2qKSJvsEAxaBVvnMNpKFdki+/fQ9xVM1OiDtxfrDODa4XeAdb1e00+1y1u4\n9OP07fq+Y8BaEkGEwDJpFIiTEUqaslqAJcTdOVQ8V4tw0I4DJVrbm1RDfhl0BeiWCsREr/l2skEc\nf48+u36Hu/MA+Zg0LAvKtaqHhVmzPnt6Uatr+T56W887UPGaPVvPbemn6KoGiUOlvLHXdap7eaRU\n0cGzxhXVNbCrbV8a/0wibc5N2r2Fwh5Hi36BMzmDJDQyHSNxxij31GGAThadBSMB0rLUeBOf6D+V\nglUY0DmtROXiYivMInG9Rtx3H2DuHlis/Q7tD3WuNPqbmQgNs2kDQwFOpyik/TGacKoJ61+mSDBX\npgz448DI8+RqyG3HgltsGjcxrrcu1+qLfPYNQg0mXeEW4ZZWSBbl5P1BGE1SQzhOnk24rS+OjEjx\nC8LCjwqs97I71Zqubkx8Gpw3F7KgjFeuSAp6JvGxw/HB1ciagLmRjKaNQTFP60B168Ai5CCEUeP/\n1Leq9B3Dca+/Vn0vl/tkhEhTJ1hSRWnKT3gnrhAhIsavRfXzBxC923yMUXGKff4FhiKF1iYE+xeo\njSsSVhHCeWN481AT3BM/DOtUi/s3PsiHvnliL+eo8VghedMGgPjfBm+z8L9AOUimDldBTgI2cIL2\ns12Ba7OMgKTXWVkB7toSDE8YsyB0VTn4e2ORaQ6/HFz7McivzPJ3YRmLQHPDqEC8/kR1p52LfWol\nwxnT4s+CMmnKyNPS5UwWX6g9t0glgcxq/rw77TBx6f/eu5T/4fRWgRqtzuWgUbkJ/oPf4kUgOnjF\n05PWT3x274wbPjuC00LJQ79laOk3DObUWRfFG6HTdVgFJ6S8GeTYrDNA1NxnTauTt3L8VtnMODEd\nwUzmPGE78hTFz4cxChtdXlnjhXnj26FHLNx9I1jOV8ZW4/PciSwa5I7taDmdbg/KNSoQpNFemVpK\nIb1HxtT/uRxTEB3X3ZaxjcBaHQwqC96IkB3Im6XxBbK9XuswUR1zs+15eqv+mVXMFYK8gyrwGiB1\nL8X4eY2tDW925d32EzH3xDa/NvPBu5MhJRu0Yzvi+elBjgtVAXkSO1qEx+9dyvL1OUavbNyhWZUP\n7ByDuLUVox/7p6JFpZQ4rUniOaGS2r5KB7OMYU/S0T0oxiQ6tE2fUsySkLAdv3eFoHUBpgamNLSL\nAluMCoZzNBQlztq/RmnilB0T1Lf9Hct00NpxL52B9sDzSgg01+2PUCCk0SUFq46gerwU++rqrPu5\nIyy+/DV6B033vSceJqFBQKlMaokdT38mmDKtuRjdKrTyr2iWe4djNEnB2+8iXKMQhv5igb0NCxmE\nutoRDM7+xZQ8y3/hek7IFg1QWKI2Fvl+Xqyqxr9+gnCCXQIEJUmIb4x8yLgFaNFa6DKwpbP7Zhyv\npG06A3WmmRxYHf3NATuVt69fxwhseVm4plhEgImEibQC8k/0qDc2CqqKmqjtrO4UWOBUwm0tFd4n\nsVkyx/LKyT3zN7CsPsb8HiEM+qXuGcKuovRQdiro0qOZixQrqnEncZcWufsAmYYZfXBfRMFK0P5T\nXXBEp2JbKgYKZyd7OmTbEjvKVwrgE2/2jMybpmE9csPuFy2CtNvEY1uI+cdZmIuaSP62isp+HKkR\nhJrtqprqDLXqbT8Dsny6Q3OzGYX+68x16u/RZ0uEBhW/mkRwPrJ5lIynA5AYTk6WbkoUxkj15or7\nmwEYWFCcV6YBHBoSWTp0WF5CR/roF9Wj7nDwVH1e1gxT6XfAHf+RhZxGGXRaFG0N3+j/kIZ6gzuV\nhDQRVO9nCr5mW1Yr/mmCqQZ6t9A8fxKQb15bsb+bmjOPb47/FZvu/EcJ8pSxHr9ZOU3fTTYu9yBS\nRoE/gRA0pKlfVpPFnZ1YMC/fVPa+d+pvdeT/IlPW23KlaL6+InGgThRaqgYURm5rCGCDNlt/+UP4\nZ3PwKKDKzqPWnjdnB9wgxiauiwu2yyTY/GQX+q7tIC3t+2u27SXxDMlrGEZNvx8YXS9uOAsdFder\n9A1avSzrJpH4fewEYiKe7cDym6Tb6SNttCQ77U3lHoC7EKUFa1PKur7Gz8f73ISipm8aobRSQY4G\nZF7OQ2NaE7sGMUfTco9785Yy3yYucfCQP0RW9oYw5v4rjuXdbI/J8hpA0A9MLOjNQZ+e2IIEoN2g\nK5tr7wF2Ns477xW/Y0r34bJJVKSINqdnqN24+IfK0nE7gaxFMYNi6MzjneUPKYTUune/5vZkBGC0\nV8WsEICilCtMNBusdMqthZCN6EHiamqjCp0R2DZfx7GgBpiZ4YjCU37fbPagnWnjEbXybJ/H4Z17\nRnsHA6LYUpTpHCrxRT9qnxLYoxJ3uGW67jUCLIME1vmMwNRelF+CFjJZ9DZBsIPCy2NL+vj6qm0H\nrVMT57+O87ktprAnp0ukpK6hp2VeyBNty33XGjqIBMpUYl826kO54f5oSsOyP616hUrhiAOXJbRK\nGAvGInDfx3cUyivJuhhZr8mXcMSvOW8W5Wj0nS4UtjVZLTt0L/WwGARQBGTdWbnJhx/PfV5208AP\n7iuqVr/2wKxu8hEneJthv5tqMjORu+uuJm0mcc8wildT4I+rOTc0fjMAAlg4eQqGKZctnft1mLcO\nUw7IoyDVgQnoDr98lbPUQ3tUq0/UU+HolcEU2vYWeq0B6wI2kIsLhpNZEi31Osemq4j9dwxXftc8\n7l4hvMddJKhMUbUozB3HVERTx5FzOGCW9I2XfRPUWu6RRxOZVmEzh4FXESdPtlkXze8rWhzcGN+7\nIqiq/HAVDSQrDT96tfpvj7OrnymA1i4vBwGWSTJ9g7TnCzqrIYc1F6XBqna+dwfCGsjGfH/IkU3W\nK+oB35prfPyaEdcTWJPe27/VGvYtWIW5iLGOqsvM166Oq37TYuiDA/T+8gv5H2I3XdyXOkRB2FFm\nMfMTaNVmTDgUolQg5jq4u18g2qF2Fiiw2whAORvQJ+tvcdQWA2z9tS0fCwT5Jwu/GKhHdpvI3Lic\nGhnCiQ75Ko6HMtZfqbBtlAqHKZ7/yisCoF7S163fnWCFNCgIqHfXo/fC5CzCCHs8Ne+jDeMHc4Io\nA0sRvAUTrVZgkOqMyfsFR+4kbyumcVKOupQn0azaXEVcR2WkwKSftSOKEnxjS/0nTAm0M6V8jjAR\nALVCI6zH/8pMCE6TJXzEKRRWvnf+XCiboujqlCWYj4OdVGtzrUJn0dwekXHTxjGilNVVV9hIRWRC\nRWP7eolLF0IR+8AatCAea2zPZxo80k3tqDd0r5ighZDFiRLOQG2l03B4rX8JgB9pIbyW8e+RgY7r\nTlTsRH3eujzGEjQOZgRcVkOOywcG+3gCo4kGIaQv0EOUEdjUD2+gqzPgHHJb6llIbjqZ8zLJc9LR\nKcEZN8bmlbnGUjquOO6HfqOsWAKvXwMKZ+93G8kJcJvSgn/aMekZJNAutYJ0cWQ4GpN9u002U9bT\nnTpvcQFkrcwn9nFwtTLJh3ScoGv1t7QHkdDYpkSicOulTWxbMHiaAwsT4ZxrpGik9yRbbQ7OXelI\no/00+31jPLgSAUGumVBqjI+nAW0pVgYyCw8twc2E3nmHagELbkFZncRTPgKvWNL1Vf9o8/6v14TV\nnOtaEk8KAAcxxYAG3CyxD4nY5YVIJ2RErWJ3m80/yT9FMzgmPx54oarrj6gSOMK+jIhIhwu1ABfx\nPVpPXLxfbKYHunLjBbiCc7GGet4MYKJzcSunKmVB0Aoxzt+DUHsv1gralxrOCjVOhg5brQmbR0n7\np3U0ZyhOJXymXu1dp0H4X0GZ+QnYuNQpsWpXV/lPVKXwdDeTdubQO6zN3hltWgKlnhRi358fyUiG\n306jBKYmUUjfT1BviqvlvlKNVjBuq3KBcsVcQe7IrmVKsndoZ3JYd6HzsAnMonb5sWSN4aNhmr/H\nGbF0sB8A/JDZ4H4bH0vnDzfQ7rRcRUY/JkjTZrgYs8SUKVbOUmobsBQLZhAYPL5pH8f10aOFPRPE\nrF3g/xZphfZRWcCEDZcZUfaJMtPtn/IvBBcGwQzF6ffK+/0umvSRiCM4tqDWsYj8rWpGdZjkTYnT\ncrHCOuNkzPhgWnh5TKHQUgL/MbM1IIxeY9AySbK+sq5mKXOJ+LHC9FofIf7xnSuXFptyDT+IFoTB\nR4VoxAs6WW7Q/AH/hfeH9F91EvPeVZiiVggg71uPodGOyWDBArvr5GsbsMm+LU6iZARrdjYx3hyE\nmvCzs+8orHWVw6q95LaIBraCn4lOf4XvLoBAVJPvfpkS+2t+auPeZmT1HKpIKiMhLZ3PQjKHjsuu\nuo4cPQYW5LLXHoHKhvPyos8FgyjM3nqLow2D7HlFsP4azYS/iCCJRe+7ftXsNU6yejC025iEI1u3\n8lMiHF2h7HO88FtMcV5i3RwzYw9euxNj86XfuLlUdbcosfFS2kFX7fVPkRs2PZ4pzTaNGZxfCjmB\nBnaHTmXAu9jQg7kadyP3t91vDTRslNM/ky9M1VeztB5Jf0pTOU4HaY+WPPh2bUXs8rN2aEtTsWbQ\nnqCsEgSBBA0OEm6SYaZXqQfuVAMYkugTqAzsGvz7CQKtf8Ks9iCh2LERFI1uWXQa8CG2ikV/uM2e\n/SRiZsM0gCLIeIG1XaKdKxvy4w8hAQvrfPmNqOWNpH24xXHet3dlpYKXSZM6UlYh+h6s0q8N96Jk\nXyRTsz1H8IUy2/zknvgtiJMOsV5K3okOxOzC/s/aSsmoEnwblouf1kYX7pdFgW4PIklqEwehoQg5\nBV6Q1+mtyrMs3j5rPu9gk0Lkev9VZHwMM/U/S2iS/5YNT2GFRaHGIuZLrrJSwupjSa0B6ySmFQbY\nC6jUwYT/x5cxIDRrxUotTf2vgZhmz9bM5wru98LOH9I6Bjfar7mItae69MJXNJLhkm01Kxnzpln+\ngt0jteVoxFgqhrzGkudZng7AFyNjrGq3+nEP+rPqmVv2zEgk4zsnVB9mbUs+wgKdh2vtlJXL04i2\nBrW/HJkqtE9iok1444Z7W1toU4vUCMVE5qj/+FIdZxUKLMjfjIgaf75cqLHdAviI+DjnpT1toJ0t\nPAwFpBDFyae4n1R2zHsZ9xRCMgOKaavc2zmOnI46egj0CkHTvXyc1Y0T6sThxzEUK4OSpz7yOpC/\n1TeADbC6ljwS69e00fAZx/fOhw4Nyq/t16XySribfZh1qTt0DhHcpop0BJ9TxiuhPLebfsuOD0hq\nMaXx70wgd2hiBA2Q7S07RUqL0kqR1B2Pn7ZgyO2gWAqw69G4IFEyu/OySfG3b8akQDePwH39Y2ze\nr2W7jx4B7YT2w+gGf5e3kpG3WL3K3Lr/XB9OG+PR076RS8P21ZUe+xT2oKQABW1e+F57oMnNcxsh\nLijXIlaFTbJZLzkekd45FSv8b5n4F2N3C/dXDFY7eipUZaM1zhjOwP24++AtASo5ltG+QHQdLYqf\nt6yluk8Wd4PvDzQfNkJ0MpwKJSoLnQ2YBXnVSFREmAh8pRvrPcegdFCNMWK/3WPkGMWcYsv79h9Z\nmRgD9INwT7jy6zdL1iwH2VvELvpf+PfG27JVSOzz2JXcf/D3BmR+rduarJueJQmOmZU1gH8uSdEP\nqt2dvTf+NmSpzyPJ2WxdNGCyF0HXGtQRQWQFioPGPo8RyIUopLFJn7+ACXrhBGM4EMmD8LU2kPc+\nWQL8/XBtkPjGzxjZTu0PMEgIP8DxMn9bkdx63ObUhX6GFSxEb5nx9ans/TkekZ2IHUEhQnSq+GtU\nD8T9Fulcs9YAvC+EDuqQcLE4GLhYaJftSdGT9IlWACdkKMsTuY+3/hWxV8hAWTFbzuqpzxpTsNde\nMrpSi8+FxuNngM0JD0MBRWkWtM5+tqVbTMxH4Q1JUTksB2tSWJRj5a85DKy3MK3WsD+KAcOivrl4\nZqLWPI2X+lLRqVM3apF0H+PvWr/CHHGG/1QNWmpxWH7qyNd9KIopxVV4Gr30+odaaDuVcT8L/dBY\nQn0U+NJMsmt8YRlvkA5JRycNAtUzPDXK6WKUt8b1yG3AVBu0Sp76JWd1riwlQAr1uX6uWaaJ3TwE\n3jR/mx02g/BwBhKA3CyHGbnploFqjUhc7Jv/zYy0Lntxi6JLQRd/ZP1iA1rmVLhhrsW/1hjYeavE\nqIKRc5s/p+H5qNLM1z6bAEkS92zcOc+NTE4xQV9EWigfeCPPgCSqCwzk8NKMQJqU3nj1gI3WZr1p\ngc5mX2TjfPfsoeyOj1O8Tj7duZ7IPXKuQT2wGWRXNHF7ZEomHE/LxvCIQl4YRmvJ/7b1kD0J6BaE\nAkVp/cFWVtqdFCwt67/DB7Yvd/RINsSg0g2kVAVK2rvembF7foVB9hKKNiGE6MzklrgP0mYW5yOO\nWaDrRv44Sr4DHfzQ93bMByVuVL20JhfvkZEDOqThk5Mv4N1HMtIMnP8/dVxanIWjSpbZkP8NXyEA\nY48q1hu5m502sDmmkRuZk6X9A+KnqESmBRseNQsgT3jzzuy5+mwrr958SdAnc5jNMlwcyniKIl1A\n/MbL8/AuIHhufEtENy3sT7M61GBxwYIpsWwq/bPnbxqvDOuO02b8g+JorqVmLpJNQYX/V39NO0KF\ngJjkRj+1I3eHJvfz6OeHGzoZZrh0iNWMesSsAdxBFTJMiVGvYvviyGsWTb3LFswQLbpCpVkwjpId\nQPgWH20UsUimpaA6HLw4oOV8IQUDd1/YKSrbnwAMlZEwq5o4wvdxtJNYv5SB7Jd6PsRXqwa19uQR\nm566SG+5a51aAewZuCqht/t19JlMJa/EpDHHnD/TTKGYLKzHE2+C/WzU5dpLG2qTNnLrNI+F3A2A\nPOMbhJfaVZmO8cPUYltWaDBrTzbExdof6n98H7q44MI4cNkQH1kf4gmOb14hRgTE3/ZWfNeFmS2Q\nRdCdad/IfHArooFAgJd54VkFIXROMsNoTxFaoJZbJFQKMaRzCdchndZjDLdJeGV6cbm6GBg5DLEV\nAgagf35EwJuNos5dENL++o3IWGt+4pThppZm07eFX2If5Mlt9S6uKyGFTvidPj5eQoTvRAZ/NWpE\nhAzhjymRK4LiZ6MeTskZCPvH9KgNw3m7dxmAJ1pfoUR4lUhQ++Ji0OSuQQ+spHKfH4hKR4RBwfPs\nTHVNa1vClLJ/pdWleVmv52Df1Exw6LK8Bw4RHBidwJxYO0MaeNQbMY08GX2/ZbX2+ivB8mMEW3X3\nVm7D+RDOCuToQvz6c8kusAebDrvgXmhr0nobGmooWaSiXXeK0OlvFkGpXu9cVPD7O0YXVouwSjWV\nSkHucZua5rrYrHSNFbJeQsFaSXVuaGwbuYlfUpVHyicajeWaciB83nioYaGFf6ay91eqZd3Hpxqj\nDQuYsdkwptAHKwFiO+3O5U2Tn+mVGU+YEj/wLAzn8XIN/DERXEUe5CsJV06mTmpFq5us40bh3cql\nyseSsWxFdvz1PAaa2ZXakuBp7pES9PVxCxPrRqqDeIPk4WAgoFvKow9bNePaICX8CQrybJpqBvtl\nHwV6VJ2pwwrRNiz43yxhYb+/QsBDQ/HS13/PSg1BB5T+AiEgWEY/ENe7tK9p4BgWLq9b418k+RW7\nch9CL+MBSVI8QzIV55wvGVC/ivw+8jgEiB4CgIEy5KFtvQ73JEijbYfJ09mzzDeTlrN5XJHUJ19V\nUFe9ed7r4a2tH+8DWYWuE48AB85N1Dpxk94ojLvo6rgl69/fPOZ+eqYwcJhaq13JyJqSqXXqc9wm\nQfGzSg2YXHFcgAfS4QyRTFMW2EnqC3VdnzawyzDouYoIn60cb+CVjzRX5Y8l82X4mNb+94UKKKCK\n0JQwj3iJDRExIi7MTlM8WJVbXWE0nJLUTJ49DmWQXDpFRRlDIHaqu4NZQc+DAoThbKkcSWSrQ8ef\nT61T/A2jKCwAMGCukz8hQbDJHbllqNB1wg5WQ1nIF5d5LkNS3cbTtmet3qwNqgSGMOGqYaOiLCnZ\nMhFZ7HMEwtUEVSGvwhEPPjB2qpeYKELohXT6TZVRLxh3HVMiwoVTppsm/R1mX4LV0RrWCPe4iLVO\n3F3XTVUzFly6ir7n8oezl0ooXEXup2/nLNU4f+DcYsWdv8VSeTBSbDM7S46z/RD7CxUJlnTxBEyj\neY0UXrK715AbXD7ZszR2RpeGXAvAlukEsW1T9bzt4VHAanLHrbYHe+P2MiOIVmVTc5QdTn9FUd6s\nP6df5r1vU8D4g+NzKYfsLvx8IZt2NgWTvCQw0pUiK+gM4GdBVPCBZHGPM386mqztKxDqMO8fzso0\ncay+DHdFAAH29IDhcxQt4/IkKIUsdl+W0CSQhchxySGb5taxqn50dRLGvl8/bRgctqRlQqoBsEF+\nSHLQbgCIQmdugUXF3SlpCZYrPJ/nUP8BjkZ+kFf8AeZ4erRToD+bV9HS3hwrZPLWBTh3svD+rkgn\nr0hheWaNAhYGkgBO0PKP4YFaQYi5PIef2FMwSFbKejGTz4XbxhJsq3EvJy/kXADFp3kWLEG8byBf\naRgUMw7VrZQyJ4MhGfgnDbLxIpmu3nj5AaDqDq1d16DTX1y9oOkrkuEK8hWUPS2w2JllzJNoIu8r\nH9xL5kP1Yk2+rYNLm89xzeWe3atZ3+FsYo7uPD0hnhi5W49HS+Pj7buQ5lbLwEzhIcyvFGoPme5k\n3N1SysF+ncMkCmRtY8jg36rws9qz0bdYxBFYBKdra0E0vosx4n6fvUE+KFrJdymZMSGCyvUu6iDY\nPXagxEDb898FcZttUwbyGmhKQg95s0ZfPDvw+6XEniPME3iUw9lukbL5DPF6WVgO6ykthTpp5H6x\nw8KDW8t231ROH5qX2+eWF3hygB3Q/Rs1TNa23F4IGzwn4kcat8wd/YEvAb4s3Yxn7PisSOQ2yOYE\npUz7yWkhDY8yOIMhtlm9ncqDfmXLGExwXhZg3dYvQ1sTSKtUMqaP4kmsiqTBXCNF1ZqBVthQD+Ji\nxmI7OZjT7PM8/6HiiZcCPWT6iVYnskl8IZv28wnht5ELWc8H1I9JLX77vM6zpMW6k4n7Exfj4tgv\n0Mq0xiS+K6ZLthUqV9POWb+OUCV4AYRm3Z0rjypDnNqlqco5FfHLIh70adeNeYyM3xcB8R/3HWoB\nVpjTXvDrDuEts8nIhhoir3QLuJk5dWrjCoMdYm20Mhpy70ZjU25lcdZRmxpTCl1TddoMcCXrsZvr\n5zp3REdao5iq+ElwFECjGQp9les6/Tb26noaM6B19ER4pDuCG/hFjBfWgLEj+5J0+NuX0hqQgR6v\nJYBOX1KvTAsUFG2cREEOmhFUrs2fXCOCkP3Mjo5f1gtIS/F37UMo7cq5nUDccgDCzIbqG6XoQQ3n\nUXmV/P5iL+Ps92+o3HtUWca5teAUpmP/8GaM9Xiy+gKSeXxtZV7P7pxis4sCcbmLZm0uVuPQMqWz\nd8idXmIesj+pd+E6neMQJ9WcZQhApkl7CK1O1w1jar6eZoH/kDDw/qRMgZ9utMqIHuTzOfHyILzz\nNEmxE6m9t3Maz4nS1JFWM8gAJKyMs5AGUU3HOAvsxxzwXbUPTNaUCHubHIhq10zpYF3bX3soSTca\nOS5RK5iUNoiR9Sy32o7HhyHEhK0XNiSIQB6bUht1n5qJRxqoPAiiANcXwISxICV3VugMa8dDe6Bq\ne5/TpwaydFZscBesZTR5eUNMW85HKWKi0jguevOC3RhUeG4mnHYgiCFJCqRxiGkT2HtoH7tA2stG\nmQVQ4840L9JzzgQ/eKN9SdEQqSwLpRIDHOTv6OBF2fsqHl4tiInObhpu+yt20VrrhTCpmofoaSc1\nD3uLe3/itPXAT7cnwlZenkDwVetT1YktDDorJ5ybRVqMOSc7IjpGI/wtssVsZwKLSKzy8iNub7El\n5Mcgn+iBJ1+7DNBxrrr7cjTIK8OScJiioF+teUd3wNigMarfUaW0XkmmcXYUdfc553qhuVya5hto\n/ycuC05DwqzdaoJXarKOAGP5GQYozwepN4YRKHnJML8pENmlNrtEUrV1GXiaKRaY7vTxJJjKh3zL\njpdU1bXBdBYt2yDAtxYFUhA8bmi36T4FTqQmjHbzwSoGlrzQK1Q/RxWXN7eWc6SgqiBepjarby7I\ndAMEe1YxBnP6GNawNiLK6aBzyjBQ5pLfrwmN+YRyZc5Ikcx6SuO4pMGdReE0l0UTiMlcfL9k3/ZB\nM9VmMMN7INRwpz3w7sekPZVKFS87Xp5wSGvW56uN3dKCxNn9kl0bmP2YLaeLN3lGgjdsif0XVLH8\nITI08+5RAL8C/fk9CLFSMCO5nin9XQH91xWYN7vFLYNjocpONkUxYHbdoniwPX0KyTqZeKDgOG/u\nxxSxw9SGCy91ws2xx+43XufwKwUFuMknPJjNOO39e7ckGuG9FleHUkN5U22EUFsOg2My417Uo7Bu\nKDbv0fVX1ssrWAzS3sAsYJuDdeV9Pg4xxXPsQVURf7aiz2Y1Qss18ZcmrK0sYLxkR71oCF+M2WKb\n6xL5nslinbALdI7uXI5bMlUSp1BL+6K10JExOW0zfDzrwPOHDhwMPoMEzVLOZkvrZoB1DdbqOdmI\nc/nCs3UWm8+JDIpyCDhT3Mpg8PzRdaUF4d3xFiRpp0dDWgt2hjh324b6yd8M6dTcJTZ7kZXfD0Xh\ncDl1b1h+Ly/5n5cPZpWZmSAuvkXU/OzLFLPpVD6S+vxNdv5/MLce/EHFNGCul25x+RhyOhHTSHkA\nYn5ABpVzIl8tcx3POgpres6QOtLV02yZOh4OaJWJdvXu3RcOk/SAbA4RgYCGcwiSBR86MI68ZWlM\nuZvZYp/80QwcwS7Ay70hr955TAOivhKIU1FwdyvRiBnf5lQegIIZ7YbIYydsqvQYnRWsmB9kMGaQ\n1oOzcJu2e3k4V+Nlwj2W9LB5Y9bvfvjlEyZ6xQtNFz4fOoDacMM1o8bSLIXxeSdZcuFSZQfk1jKa\nN0x1vRN5fNtYqLsjYCLNrkJOeccM3kGeQ5rGvxfoXpkiidCSz+/GrNXAvWJdurxawN1njJfzgFxR\n1rXQpDObWuN2EfLdw8aJG7AfUxG37E7eohQ2vXzNwMP5e5hrU5SD7Sh55S1Kmd8Lpz6Bz/Bb3/Ku\nQu1jzneDrqbEQtQ5rTO3wd84RMrr/HkB0aU9cwOgJ+fua7IGmPTgZLNxCO9v0aiU7RUen1nLTqJA\nMx5hgwOIZL44PPvPuh/kOsvn7MkKagkxHMRDkRRPIFUFK4i2FQTC28bnucMVmfxgVl0PejmmzFBD\n7Oa4x12ZHEQzsadKd+t0KWsn2ZfPbIW4KWoPent50K6JAAWo/5psk1z2ZML+2z5zO+SW4Id6YUDY\nRWk+0TLpgtzNPciFdvxeCtZltH4q+I2hKMtVW3Gu651I29LzndbKKkQOCqbdGZCfNxx7Wp6ttRYM\nyVz6yjeM/63pu2DfxvyHThgmOp6PUGMJE6aldBr/JaPYgv39WnEH8yui65RyTENSW/OgMACcM5CE\nKxgXlfC/aKcXroTUYljib/XdQOPlecjSjDOteUEDNXNVJfmoAvTxk5IffXk59+EoySDIM/Lancf9\nEQTfIh084+S1fF7XlCTsrTeVwu1wq1gxe81zmXYpYFadzCM7FmjOfob5c/ZbuXNSAVe97OhePHvv\nguPCW7X2C78FkWlWe9Vl+0aqgP3GRrpdwn5CVu222y4BnlfLCIvG1+aCFhKPJOnPXuAomhz8wWrm\nUvBFlv+cUeJ0esgI4s06bc/DXqoEWFasIIbC0/lkjpDqLJZ7JoDisrRpI0QAL+FmpAz+5Ui5FRy3\nlglZ3JTIexfAeXaA+cFFskfiGUn6RksPF6+hw/YQU9zn56j1fkfgrjRSVzvy3CeFU/cpKmS/Ut8A\nAs2BG4yOoBAFgsC8KcFDlByjKgY69LMYirGsKMA92gIZHitn7Glk1/y2KRaJe+ERGhdsaB/dADJo\n9DQJA6dlghjFY0c2jAhTnyKWwAz5ee6OkH/BNDYef5FxTH9gBfabitzW74ZMsVLpAnEzwiGG3ji2\nAF4Yc/GC/SZsqpY1TS5lAajTUwqTrV4iBeQOpdbPbzXURKhBZmjPzfqVoS3GOUiUbOOpzWUF5xK2\noik2fDUGWR70m8Mh2KT+2izte8SNtABHTQ5mdVs4S/x1ADX3uBIdhjUHG9nazO17Nkx/1TnkxdQo\nypN+w4rqpxBQrkYciRAZPC10DzORNnWqnlBs1PBEY/ITFBNVXbnnEcet9CSLvVDl83Ox9nCRV/4W\n22KC30vL+1E/RLKoSiYu4jwxYHpEyzlTgwZyyCLPg/0PmENVdG7XhkfzrBGE7uZQtVVFyArOvxi1\nbKxVNyowqaZE39ZpRZyHnFQuMcxGXpCRibqH2OLv8vDv77LGYOncORep+a0/57t2Mfd82zTa/J02\n1CjOuNEfb05PTwL43OcfzWwhNYtPYsmJL/XU2b4kYj/+qPwauER6NLiD9clVZ8vYuzEMetxafEIk\n9xftVVOSB4BiAsFuEwo1eMcoX0QN6dwDesiG/sHHHyOSoQYOA7T1nK5F/9YQ0VUzggP+ZcUSi45W\nOGGeBOhScFk31pmrLwMlRoCbD3gnw4/Dl0mXKvlPGc0FIgXVuAbf4591TT90I5LsF6p9ubAjODbn\ncKOG7/EyMqKSk8Mn2ThuDdowvo2DkofZgMA/SDuY3PY0BtHw6z+/V363Gzp0rfuEENfDtVcs4ig5\nfrQxyApHMea9LnvYJnN3kK6hmPuYNvxwtzehzXhQ23wJao7OW6zGjfnKBFy0uwm93SbD2N8nS1y5\ngtSINwGTU9hvZRaW+kTlepsex6u8W1oJpV1Zj6arpzWgMup/0KElZT2MpNEpu8oEkaC0rTg9ezgo\n25mmxHAIJjlTPDl0uRuc+VE/kobYjkxeNd9TIxSUTFwZzcRtM5qBmVDodDj4kMJGBzeVYMUKKwWx\n3UNzcUSAojpZzmj+gK+NXoh7Q7g+wofR4OOXegvJvQS6V66+xwfT9vScN+thRPdae3+B56xY3f3h\nsSXZ9MEYkihxaS8oF5UkRE23YGvPMrntpHVPuzSdHIESkrX/K/uPPGYBw6iZyvi8r50LQF6P4GfQ\nBMG6IEt7s+NBXKyyesj6eFRf00Fqqp6mzREs9t8D6M+rKrXbS0xlzJVydZEHjMWaBn+pRG650Udc\ng+S2JuGmSx7G7Vp1QzGj+j8r8V1Y7nbC8KcuhKxP2AlhvtIDA/JBit9Q8DZIiBTBOE9BqnGML2AI\npVasjKA3ImsHQfw0VP5Ycbfpec3ML3uGnaFWhoFIsQJstmhDnTp5APGdTszhomdYkqI02l9Axa04\nz2ULxPH9yeOqqd6LIKMKxhcJG761q0D0qXgEOKWv91S+lnDX2Zc2VDYY2uMpPqMKra6sDxRz8sPA\nG7ujs57VM684ffvo7EEywUgqsewB07sqiG5M1TiaoMJ9R9z2XZ+8OyAMq/4EurvwQJPvAXhmOBQM\nU0EUWxLSnhcpHlY/WQK+Z42QrMcwdh4Qan4HwrNSo7aWQ8dBB2zWXyDFIknmLQnAT0Fw2NSp5X4L\nkh1ufB5EuNVrXPIJRXMazV5f7XZvtwMSRmW1ckpD1LID0U6n16n1zAbZODFKO4JVYrxpskn59dO6\nLHON7Meh7LzCQt4YDG13npEt4Fs3wNHbyqBeZeqqVP1BbZOofa4Zo3Odbo40pX+EG4UqwQHkJpuo\nnYMybO1sH68R9+7JxHfpXMPwqe1gLoeIkMQxFx56tQIO/KVCyGlPRiAoCtUu2S22ByDQMGGRMHhw\n9dogmmegIyGq7SKMR9BeZXtAj8bW9LKqxiyvY/NG7rbb1euj+wMYZ098UFJetehiFn1cxEKeQIoN\noFJSwegWMN3pp91aiNsutUbBZVrdl0vPdIqKjdfAKkNyINJ5gBWNCq33UazyK7Y2PTGZURZ8tebU\nHJh0EFYIJ43MCHWjgO1SiAbXTn+1+zXRHqRhBytUJVVT7+lxrf+ElHyQIbeufEY/d4n4kbBjF0sK\ncYdlSRij2HtqNxc2fhiTq1ciXycup8jsWTfAN94QYmqIZacCl003THyi4ySWXD9sIfXkmInApMpV\nSyiXKBvP4vBiCFKAT804aNt5PTSaAvIeiEiqP24w9TdMK8e1yw3i8r1iIh7NRS+WMTVQzaq08hWS\nW0GHPkDpre8VSwiGibnmfP3gqqlJPj1ttP3JKoh1bUj3ocg7K71a40Cpf0HeYnOnXMYnK1NXLyyC\nNC0aKGzIFTqpu6sJzVQV13LvQ2lG7pcVZZjZIhDau/gSi+v2QYxg5zwJu6uaQAw7D5Xs1EjWSezV\nQvUYebmD/DMCpWqb5QHWPzxqxjfX/wWwIcqDrOS3xEQgLHXwbOlDphvQ9RKVbNi2YNwQXVWWXq9x\nThTWcmEmscu6s+uSI3+1AVYJ+OaK1RaJ2oIlxRfdnvkPbRWHacbyHeT2X/AnD6MgZ1sg3bdPQaY6\nvEN2ycB6Hso8L/Z1DeRH/i/8q+ci5NnOjJsp/Ksyzjgt9aqbz3y/d7/fPHSSSGzx3EGS/HKEo0AC\nR9dR+n1cLYc7Jq2M5OaGMD2pq+lYctH4ZbilmhSuWU1R6vCj46C8T6Qhm8KW+a9X2Uujlnxm43ca\nK5B9m79jMvpJV8XqqCmJSCdmJc53Yq/ElwmCHNtYIbfEvJhbliw32Vq/ZdHfwI5iLyU3lqIRMrn0\ntp4hNobRM1kTj5DkAcWGEmIAwKxb6Wa4ffpZV9q1LAL7T7LHzoMX+jDvuLkCpGMshqoTke+dO4vS\np3YwMYUFewXgBANcHWSXxb/UnhIQG3PnZpgSivUdTjbppFzjPgEgaz05135Fwr0FZ5PpWfjHpLrZ\nKldwjM9/C1/v3WdJFpXkfGLFzRYPT5MpQl18eUqCeU/DTseLj0JeTbQfiUubTIsdDxNN6GvhGWB5\nHHgiQ7SFijxL1x+93fVRtETMfyU6Oaxp36yyeGKVOpfwnKzQVkznusvV0xH6D2J4fnKnkBn0p1lb\n1TPnD56KxK2t5SIjtRD547n0ZJNKG1SR4vw9haQZwWTS9e4oHuao63Hd2appG93xNXtXVBu4QCHs\nxJ9c5Qch5JXrklPY3WH+ZWLmau29jbjUoBj7VbdjSbY+uVWGFvyp9cC9thjogBC5h8II7CUEGFAl\nV51QOO6ma3HigRCniJCtD7R7H2BOHvABLz7D6XyZiQ14wUa1lXOJlR/fIPaAXsCFVfLgXy7SwYna\nfvyVHurXx0dtGB9nl1aIkPrCjZcJd+kAlrFU5g663QY1rsQ8Xcmv78drnlYN6qmfKmZmixwtJngz\nHpZD0cQhYs9U16nc9BqwKdzDIiG4fL+4N97L9z741tAf+w2iCfnpt0LqMPgqZ3PgOcS867OMci7G\nMd/ooVJS8GhEvGa1oGnAnZVP2XIPYxrIasey8zV2iGVmcQNiR8lJ7sWSouawePwxqEHmuwcM/56d\nSI+ZF/0k0hMEsRRCB5x1FYnax7dog1CVZO1MX7oKKCrDQf6Veq76TQ7K7IrxM4kBkMxDy6xzHsXD\nmELCU4JEush7IHdGn8LwQ04gpZ7eSq1KFxrbZG4rqb5gKyMJv4n8LhkDkJKxk9s3iUBtVIWTAPvp\nsgzu6LGZI09+hJFjS59AXJ8yZsbBvhfcyaMPW46gSwMiShiowrAJh3pbb+gBxAe3tvjgXBjE1CyU\nb/JQJ2X9ysiKndggsM09KND3fzoiol3AfetfAiBsUwo7Pa4JwucloU1L6y0b/cZIIzadsjE0PEN7\nzxXsilEL/YTEQutxk9aEziuk2iQVWyPF20HPwP1ZnuJk9sgNppDhXih7W9em08RrC1Bkz0Ur0JYS\n7OfgcozE77VaYuAFSdv08X6aNRh3Zi+wT1ORJTRXKp1JlIGj0b39Nu2ZdfH4fCPB5B/DauWYemGb\nKt6Cq1yoEk5IYPQWBZW+d7ETjK1nNYKekdw6ufLvZFxtuNtmYl2vrpUitdKM+dnLJPhHTfPOmnt6\nPtW3ccwGcElxjvnaTwq3+bnazFIgm0nsV3EKCF5PWzeh3fIcGebP2ESWeftXh+cjHX8Sgigng3a0\nKgBCXTgbYdkbjKNzZdUYw5icXEtVg0fuGbNazVl4G4m8w++02OB0IYSJYJ7MGvAbw1hOg5KE4h62\nlgAcYbNWd47ojrejZ24oCbsFkSZ96A81y8uNJspmDuT4Z1/7x2xLlL4ApRpwhoZe3x4n9vypZJj3\ngerI4kWp6l26cR2xCQo19LKSEOql2lw6T7JNfPx/N/xmEJDVRFq7D6zPktNGxFYwylVF4Vm2tudk\n5RnzhijvYh0iqhwIXyBhT1afLA2uXlAN5gC6HHJ2OH8THWMkY3kF/szJqtXyFAaSxfS51Gz1fO9q\nvraNtTYxu3Jmsk9xZLuMmZHslNcU3ifFuLaR0xOWT/L6TNi3y5m4cKjB9d/iTYi2WmenNy8yr/Y+\n7mqPEI6KyxgfusKU9H9Ul1dl1e7dzMIk6GCzUOwiIuyds0jBQaAsMou26mwm83MIvUdstAeuT8ZF\nCL0xMhdQkwYp1+dfU//DAf3fMnWrwmjDFiUZavj95KICEqhcrWokby9pNazQ1T0doA5BzNiSsIyl\nmxE4oTDZSQQpVZl0XGLnSYT0zfwP7wGGPGIjnVdPw+i4JYIR8wbmvz9PevSxf0SsSMEBBUg/6Wd7\nMgzZ/+2P+tJDMGe6/gbk7e1YsGAvbupaQHvQEP5g94+E/+VHW3Y7vtkOyvO9bmTEpZFR2yp+YVOn\nBsIIgi5+OQgrxptkxc3KuYKjISEt0IwnR2I8Mq1WpnOp5Nuv13/bvLvUqK+NLt0VFpG/uwvUL5No\nqmlTMUDLqmtlR7VlSYEswIJIPLs+jaysU16lS9JhHo+gMVfuyjpSiiRqLZmvTRWHcPllec/Pp5RV\nyd2RIslzwqiDpvACMVsVDRJOZo62Dc+lInIQdB6dZ9ga6SvDSgt5nMp14nw7mp7w2S8Bg+iimo/f\nRfu/NDU6IhD+wAtNp3aiKyKhFIYryCnJr9Td8zeMa+PLHfbtIVRczWEfhd/lvrlntnCyqJFRXqoa\ncy5vT0kNQ4Me1IJU0C79ZJnZ9LR2LDitiQdxWXstR0si14Rco9wThrlF3cmQXILyjzWyPIYvdXTM\nZRJJyizPPR3MqPDXnewb9ZD/Kaho0qfyQYEldXHTYh+xU8saQ9/srEpAbA6891mUn0LqcUQWUUdn\n953rkkdmpbTL+ZnCu+9Xuq+l0cNFKGphiScq7KR+RKSS5VboVy7KJUZy6zCM1g9+ZQOWCt3lPkB0\nZ69UfgTU0HSZ3v2ysA7WSXceND7Rmy3nuVaB9Z3mBi1+vV14fKym0tQc/hDFs9RcPEIh8svaTSnD\nXN8ZKIaFz0a5wbRNfH5GoSbq2u5x+FB4eS6Ek4ysmf4c7phrxnrdNCncsTcoJJwAtbuEntRYpfSj\nWFy4H4CB7Owyq2VnasK8RXFuAN0kKhokxCRZY9f3RgTs0k7b7Gf0QyBHby+DVdnPA1fLC85mr2Kj\nCXltML8pzgH4XDV6PuZPJkpB4NuPlHA8MTtlO9pG052POnbc7mmX3inl7GC962uIapsoSFxaZ9NP\nHDXkMw7YQVdQcs6JLRtlJ5DmRbrK17+Qr2yLuvkTmV7InAaa/PAAa22xnaIMGNZ/fp6FqCbELqC9\nFbGWj4SnezOWw21KIbVGA4qfKDJhi5xA4s9KEGrVZjRkBvvZNinLkZWvn/Ja+7Lq7dEv8oxFIZJC\nFnHicb4Q3UIdfQ8g+q7CUw8spJbk4q04pzRxpdV9qAmrf9lnEOE6z9mSxHBLwP3x+3T5s0dKsbsr\nZ6qpIpOyWS1cPXTVna1Z2U8hwXQnA3LJ/DwjT+ZthHnWrwlmrVQ19AQdAQBe9msKqW38gyBNW+Ib\nVA/7VwhOLUtG5i60z5UzOtrfUag+qBYrH1QdsLxD50sTFPQ2BjGUobax+HCgt8VP8QZ/xtTqPfba\nnw5tCv5lOTZMs5+6pzgNVE7vWfnu9Oj1B4hP8DwS0Rx5XgVRXR6jDEQtaUZpTmLgMJu3RhDfB3IY\np4NdC2VOfoJ1zZMLbDJoG4SD1DvnHyr5pTbAsO2/C2yj1l7zb2yYCxRfnY8Xdo9ATHjHAloEPfTw\nmc5m0yx7WbSj1GM4Wl2bwKgBaZW7neayjXkCkHg9rQBusFltTYGrX+uHzeIwPL4LeYpPLdR7TlpQ\nwgWTnryWd8RrxnbyldaSbF9+AnXCk4plu3NdwA36PHOv/Gn7BmuPvMCW6ajC4GFOo720Zrm2mqb0\nzZTNzitAoDyftuNweip03Sauq60/fE/6yMkgj8PUaI5+O7lvwZTAmwXDJiLzb2GtKZKdwswc0zgC\nUW/sDsWJTa8SI+kA8t+luAb1Q5t2SmMLHq4ADSOWR3IDq0BtovCjXsVsf8f1ThSRErt6aHW7H0YA\nvVV0eDW2HQvlnLsLEk0xwA5owbqdMdLzGMKLE8CzB85MmZ0F7FDuumY/OBUz6wP3gOafSfl+C7oK\nTojb6gALfllNCRV5/+ndGR4/sVWNH7FQ7X807fpMOwHcr6FIV4zdFDzDem3X1JYUYSuHVzYN64XE\no269Qqanp1ARLNu+41s2jLT1l870trPvqQjlf6Sxm3LYNJCTu0OgBhlxC3kvIJRLKpxwAUrFkj1A\nlWYhm1Igls0sMthTXPqT9pu0ezm2sHXO/aKny82Wz2kgfrAC9YAltb7GQGHklLxxsBRI/8wTN8Y3\nHhomzPdj9JwRNbXtnExORRDok/Cw0WtzrQPb10FmZDfT5TpyeUPKZb/U/nuZhyeht6IfpGwURXJz\njDuSOMapDuKz8L0vg58XkSUuaP4y49lNo8Ln4Jh6JfyGyAr9l1CYgjmamEC9nRXxMgt8Lc8WJXso\njJloOOcdepITx4UAnSIzEPVQUP5FMm/yE1RaohC97ZyST/WE57MSfyAYR21BJQYxr00norkeHubU\nDjOLD2mEw5+oMy8AnJ6bTDFUmTPDsr1+AhUUlxdF7p5Q5SGQjHABGggNFI0vR0Oky+bjrvS7G8Mp\nvsAK4y2WEAxL8TkbKX149ulHNFPoKs1ov+I8XqWcEHuQ9ZpgTksPLLVLBZlqN4ouDvR+vcyBV3cT\naZJLLETY/TUTsUhKMxUrN18Qacm88V1DpZc4vfhi72I+xUVARAcjyowX3f96m8zNFnahw6l2/fMZ\nQIY4JFPrnV7JtcMiFoZ1O6dQGjJsFUAs+HawAlaihdv+VvwfMvlxTOwv3HZJqor3vpSxUX9woHPa\nyphGLCpX0afwqqInMySISF5KstVhyvd1NOkWdXnSsIU4qSbhpWsiEDbiPL+sHtcHMFZI2bkwL2aG\n+VY9fZWFpATVOy4p9qaIh44r8YrPQxwYY2CYCCVQigCTBmUaAgrCyxRrJ37aKVYkGseVGx2qFFrg\nMUnCcOPMUNOuKtHhwPv31P69tokS+xJQf/RW6kwxre885CsAZ7WlNER4e1Juf/+6aXBh79ccAGjg\nNzAS8Dmzqw8q52ppNzPI8VKIDX4FBbHNaV8QpLWqDH+YDcijnhnZxt4AOQGZVLVefeY2hsM/tUhn\nvGT2mguAJagm3fDVebUt2imF42+yW6LsPHRYFEIjUdBdV7QpMwg3Glln3GVb3tQFXkqUEtZzy8Ot\nx5woA0p3w6p4YmExTCrFsi3rpn3Rf9m7jHhepeLWaVPnTPThEB6FTR5nKceRtNPMG3viJ3ur/ux3\ntj6Ee6GQLqbLGlljrpi95vZ8JTL5guWnF4WF5oHPG+5w0YVj0gNcmkv4TCWXNmRjA8pK+aiwnQR+\nkM8yX0aX6QRXqzxDg3Kpg3c6I6juPhSz4tzlqPtZkZbqcJFWuxBid9XdR6obMcha6wlzV2nWNFGU\njtuJiwflhtk50sXZKnFMMOdZMXNAPV3R4xnpxLFAl6DW831RDmerfcGtIgEj03mg5xNPtOPQQoj1\nrt7p+AA73ifEXkM3iZG4QUSu2j1r06LUekDHGFd7lqYitoq4xuyeNBgDY/9Ya9YiNoZmVpUJ+B+S\nmo5mjl3d/bq8UPjOtYEoUcpS4VLTelRdHblr6qjw47vBDMU0PfeTFcUpcjqktTpE63RVngK69m+U\noAP7tTb8z0nGjFTK9iGhVq3N/lr4R0XIr5BDxj/fFSsn52/5wD9jnmr0Sg9siy6JaWJ+pkL+IsOZ\nt9KmoJqFdckWM5NtgZYH2zS+bZel9AgkDBR/2K4654RzpcARdZg3NDcFKsiVs7PXbD87C2vyXSko\nmkxbcytbFDWRZUeaGWOlJT7Vw19Afil+STDAEzO2PZX5oHOQ256eDcQm5WHzagqMlVsGx74+v/jM\n0+HdhjRS/rWQYQib3BGR8UC3GdQ2Z1r3KKRdcr4NxaSEpmBH1ISgx0see4Jaq3aFJ52puNT+1XMk\nv83gb3zlPZhuTb6cLKS/FOKEknSn4gbuz+hkwqA1QPiFMKAdOPPxz7eFtaM6y/1laq5ka2W1WNxQ\nNqj6I+dMxNJq1DtrSCNz/NBsdemOt/BXaHqK4PpKFjscV4sJKFb9VNyfe24LQJ9ShsrrNaVscYPi\nZF3x7vSST0y6OUIiAA7kxULWehIhVPamV75uMhF+ZYd8J242TIZrtaYUxQEEOCAZ3qdjZOgdciwp\n9WGQq0xm/OaY7WIPnsvThNIy1b+KJJcfYjPZRa/R44HMBt1K+UQAiOuNvjzXgdzd9wgygHeKUlDS\nHWd8LVMgVBb2JCPRM68jBX5hjIE2St7hZ7kBye7OsMIMxMwUGvkgu9eGqB7XAWaImrJ2KBphj+JX\nLuj3+oM9qCIEpW1GwTSv7yE3YWzyal9rGqKxfV6EkEFdSAGFZmbzJy1l/x6Zqsj4bOrHUnIxu+pe\nYpf232vzSP7Kyb4PfJp3Ocvfc5Qg0uRHYBxsfrt1akLSmiluKJQp6vJOk5ZRW6ctbxbxJeHpG/MY\nwC4v04cegyiwXm994isvb2P1VU1//HlPSyO42coIWl6qlIVGlYJA4EkmOTkwF4083goNqDOk+ha6\nRXMVZ9qTl3hB52q7lkHtRmVmC9mbwElAV71vYInJRGauyapkqDgv+XIis/EPx6nnrgDY2jwcstyl\nXO0I+sPJog6HARxyQd3MijFMT+llguLsb2b/CQXc29+t0LLRoqT8oILEi85vJFc2mPFU6hlB3lfi\nJLvw6zwp7fWvExCjBRX/mMD+OZeZwN7Eqi4i6amQgZV6sHKUBFRXeWKOO7jZEAEepznSG4aCepEz\n4oR6WLLpUBPys8zZRzmJiCb4I7/H0omFDLM2XoX+rCDiBom5fViyOX5See99+Sg8HZd3TY7D0a8q\neiaxlycKQNro4CJm3ChKDBSSar1+rNX9A1ZSDITwxxaco8fWIibEoZZKureyqlNnmnwkq7AArMdi\n1CHYSqWgPpzRxxyhH/Wf99N8+BsOLEBC+frcsvo4HxOfgdug8hfc6AGYGlasgdQ9dGo1yUNBuwvU\nCG0vcMkeiUHeWu1GHm5zl+4bzse1/Bwg/WDoHuADYHcCuYF4CORq9kK2b7Mrg7JUu5+pbA74JzQv\nh1k9fu50c2zWaAt90/9gicAkkHpo5HxSe4/ckJT4Fm1V6mzSDyqSTN3CGqTu6cRmEAmlGROGwTqA\nFaS5+/6A3VgbHNKAsu9A733AI2krScUOk9OnPWuYr8a7T4YaZXpVOHu3G/+5uejjeuJ1No0VusBg\noiihjPArPfrpUZcMx/grCdIAI98PNTEM4rpXckrbvLOXP+rvDKW4dkyI1IQoFmvBUU8j/V69Cz1+\nywA//JySuq0qc76LWN4WzXPE5CXAvSaCrM61T6BAMiIcsTQu9fDF9Bx+qzMl95MFK7DhDtkJ8JbL\nEK1oMAl3cenAK96NZPw7kjr3ts+Dvy17TND2pF7/kvkTKTCmua+Lp7wcFbzIU6mkjR2YdcXA3VdS\n0ih1cpqKUnF1gXR2f9miTooP9f8RHJYpqxN5YwmjNTmrY+EWOKuYTbkdtpMOAHMEvxZZmSme1Zvt\nfzAPkrchEIep58mgDJnBPtHafq98Ctkhv7+J9L9uIRg+YCpJ33yBbZeQAHM+ZYhptTRISXP7eK5u\nIPB++bF8inaSFsQJrAMBKbrgESqvjgIJ5QHBvX+FnSmPBE8MCWd05X/azqT/TqpRdU6OK+vjwFOg\nuz3idkqlrSR0jpHF07cO1MKCdJFsOFjWOa6ajXYqiaPzRSQtnGnPm8R23w+ZGLsSiNp1JOC5we6q\nzBxngL9my8ev3UiRSMRqZytwlhBx53+Ty0taL0spcvYxcw5Fz1/86rbGppYC7tbKN16JBUZD+9Tm\ne1iEANzFjLJkI42/nL7fWjbDmK2Dxp72rVdEyNl8I1DePVULpkrgrRN1l6+RZtbucDPIPDNkaW6G\nm+1pDEzzNCIV/4T4stmiz+nVhARv7OsOY5MfrVQzOdPnbdGaxcsaEJlt4we8tQbbFWJCApvAjiGI\ny5JeeKvwU7EZyUBuW1GI/YMnyiQj6zs+W5HfWsOjqig7ltF0dduw7Z7NmitElQzlhoxngo38iTM8\nPYn0WV5ED5/4IFrfYd7AsZBO0h0hfMz/bRCC9MR6vAL2KGK3g2PAIDV9y5zY3WvqsppxP6SFzFEo\nWmMDM+LdqGdqXXXivQtqySITbieUGfHglAm94EfceMORdFLKA1r1D0/vmgaYwNAZfXrH4G+zVASR\nSnkRAOoisBHrEjlUvGw1ttsmfIJgo9etLIoXYx97IqshN8AcOYwIIOlgwkfHqEMTm6xt16Fcocrm\nrDl6wXZpqm8CwNsg+KCnUeKfznrH+/CyOE1Zc1CxlbbuhjDI1xN5EEd7ad4D+SHwfb6jGR1okvRa\nyBjvCezO1nz//TpH6dopXxvjvVgJSlSnhIqR/jrPmBw8xvoFM42UuZiHYYeR4g5fBKiJE8ldukNP\nv/9EG5AnDXsROBGjQ6Q+r9dignXmw73O6dZIkbW59O+WfsKFUm7CJ51Vw4Nl0mJ6YJ8ipB0Zyuj3\nnUrtgs0Ayw7DOocl5gB5SzSKNTuH2s2BuKcFpEQvhq6BWqv9YRqGgwrdDAPWIodCHfYuBLuQIxYY\ni8FQ/vhV15bhcwXKVvwUqeqAX3zz9uuHLlDVC7bzUfDooqELzoBSJHQeNd+VU7ZzMuNz9UghvE1U\nM6Nnr/G9x5vM/XlsZcMVBRYAhoaK6t2Lar3AXGpG4n/x1qShUuXhia/P9aX09IAqzSQVF+WB1BQ7\nd/rj98YWZT7EvurlrhfbIa/KwVFwYEBWcr5RVluchYFsQp2d7vFo1JuXccnXQDSzufqoIBl7uybF\nW13+Faqp9QmT9QdQv5bBqTfLzSQamE1kZp+RYumUmD8n/4avDsQJDvMcN2MYXYoQvTsSAiPWvKaj\n29MCdjww+x5kVLe0MnlD+ZjAFXqtRO2umHNtONeWy4dvDVmkMoRkMYPLmhOc1koqkB3Fof/ASnqg\nbvQ05p27HAqSwxXJ9cpnILEkIGs4Fqu9MrFyfh2Qg1At45infwYaiwYLBUkwnN+BNRb6uHnObCAD\n5DfpTfhE/oxFaEYTHWTdR58Q8ij/0Bj+SkAYP7D0kA8mO2mJUb/q953cfIflh+TH0/eB4wB0kQ+N\nw6DHrZLP81xO3fhgRqNJ2aCiYyWPXowsv2cNj1XVILLx2Rv7YYoaReFhphPqwYpMq/0COQ7WmNil\nlbPq4oKhd1oc8NSCRJiFAXqsGWW5XAdB00XTPj1D88MaC4DuNmF45neChdyUgG3IxBVwslsWq9be\nks/XgyJlsHCVtn7HFXf5bgzJaEno0AgzsUYj7U8rAGwXz2JteB3mhk/OtD2VayOV/VYP8DzhkfOo\n9yF9zZ4YMnIp9nypAZwHWmp+3TlEKWDmMObd+KZc1N2iK8/Z8Cd4Tj471oyU7rGsoRM6Xw4a4gu4\nLmOzAjEBtLrHdguze+SDWqABcjYGQvbD5qul1/Wj3cxGnSP0utrFVqsTEUEPc4gtoOWl0DGNtFdV\nabthdOXQWe4f0DGZGLgUWD0Oy8IpiZNSUb32lk62UkKU4UwD930N4Q2vLgXPnfNxICLkGObQ54d6\nlegvK+spO+w5Ige74SmsGsAVKtk79QJ/xT497S3cydX5wK9BhE/OXDIY/5dqidPAgAYbp+Tq5xEH\n0nu1RAUQohkE4qysg2zdI0ifQP/dlr2EG7ClZT7nL11Xa9HQhthYOxgmPUjT08d67fXMU2vbgaAi\n7aEs9TcIJvMfHh75zvP19j3IlaG9HQmU6VjBzT+T/QHLD9EW7RisQ/PFuUZnXE8w1vOcGleq4dUd\n+V0NMMrRHRralJbkD0tF5GLYk+xbe0TsPEtT5GzWN/mGtURDobz8kvXLrJfoKYwKo1p6bis7fls3\nLqERQkJ7TWCvHrwNjKJaLBtG2jKQryFYLm2yqBt0GXaPakbjRFMwwP09/FY7xzADDlkKermTwwdy\nCT5b9FuyQaCGpyf2LE+SYQlydWgUjzhFh53KGtKqa8zqLTxeYaIAl8SC0wuOqddSLTjXmtQmL4vj\n/yYdXZs663Zci9OWAi6uVd6JSGmEO+4Ej36tu+jbt3rOPiRy1kKmxWtiQ16XPIfEVYPei9LgJDz/\nRGFp9X96fNW62CLEX0MzSYqUoIBuZTLwe41xfne7oUQofMOYhEZNAWyQvsp+anrfQdA13UiB775z\n0mZn+Gs/6rl0T4k6YGsi7f++K0hQe+AkGZ64uqv69V3N0AWG80q0EeACGxgMkOmS9vUPT05hdEOW\n6aYXleYB7VIVxb5eW8YJlSvi0yHfYxwqiZCsuY+EpIzmhp9JYJuAcGTjVEVlPiq0UfEpqCW8maN5\nD1AqpVfj56S6dRIhmwcml1BGcFctdWajtW1h4KP/z+xGrX7JjHz1rTJLxueNcMk5vIBp4fzKQDm1\nPpkhm0J64hazVewhW8JS+qRMyDJLbS0Fxc5fUAUGNoBGGmPIDQIaWxMTTeMxv8hHPoZfnklhkEVn\nPfmTRfAVkhZbjsPqdnkCw2GCDH1Kk6lfZiDK7gaQ9uvnPVLR8OxIezmhI5LyE8m4wMscE7HW280U\nkpQ+GoKJB2Qt6DIN6MPD362MFgM2HDXeAcwqgcNSmMEw7JZtdDlnad78+9Jy4mw1PQUqVNcndYju\nyCl0jdBaXMTyGgYumyjV6wMrTmyHM9LXufsNWQSwLifMUsj77fbE9mW0Vxx5NLPkb2Ghm4EbE1TZ\n0dhcwSwLpTtLmEceV5pYMFI8ixvBKPGCXBEJukvcGuJ405iW+Ce9IdlfgYRjwdOCB8gqQjwnwF6P\nlclJtgw4x9eMozYQ0ZjIp3TCl5VCIa/fRbr5zFCvbtgYMnSoDjZzclAW8tkeCxhvWRfGUdx8GaMK\nzkW2Q/bl+mnOZujNaxpnUUf3lUloFIDKZpzWYvpyx40tpDLkoF0DO3KfO5F8ukg5N8Oki0rOqkTy\n+DIUjTbOKhjWWYIDfslMxCjftG0mtBscJkahe42V98YzVeVDWjHfW4Gh0ncpij/t1ZSDRuMsH38P\nEDv/P2Hx06kugZp3hM+W08yljOk5WqPgyoGggaqFy8qfR3sX06r4X9lwa5yVB2qUc20hGWSo9Rb3\npL5bN5rA43E1YZGjIcCDW8j14nJgPoOm2jOsIrh6hAbXXFV0p8+yqMUtZCFLRKqsBvsMX40iV8wX\n0Ytl4fuC/y+/IYDivJ/q6/HlpCNCAUlV43z+DikonGNt/Qjo1zIe/43dP8WAV5Wh/nluCIY1qlPA\nHesbcgYhSX0EZQsu0pZ+Jpc+0dPHBT+kLn33S+0JKVdZk0cg0AOjxY0anXb+Qh1XvCUrg5YvWQi7\n/F/hYyBAvYGvIgZZSB6I/+e2Lff8B+NXqyqBoMgWQ6UDheyEBugC+/nmAuVpUJGLBjdOD15qsmcw\nZmMFL/+jNBRQPzonRJyWTYghJ7s371ooL5OBHBrs6786qZJNr3AtgHjhUEVWWE2vzXDbIz8ZKC+N\nVRPhWXLzwKvI399MCAI0a7g7Nn99SYaDp93V7d4P3qg8l1JP5S5/qbgWhdu8+YDIf3kPvjVeyg4G\nen/GgBTA4w/OrQtbXwGe3HxIq2Ofm983yqufejihpl1J4wqIuFp6xa3hg14RhTpxkqlJz9lsMBb6\nDCK+OELmAWdodgCHFcAL/GrMaybUWeADTABMT+1iaKT5VTNElo6xZ/QpsATnbwD3uNH0+fQfAHkl\n4ofTVprxFzhcxoAn1FoXEd+XJ2KQNklAd/CGP+cUusMNxDxc43ylxXKtxr+rimDKFWDee8X3HR2Y\njBBYnX+WtSUunb7zazQkF3CB+kcTp0n/Dj3JLC5PwLqJweZ/KwxzttoZOGxlF7StFyYqpMDTdu9+\nl5/V+qq8rVEYkEA9+iPrN/nEk6PXbKczi2rfDzSrgnl0fO6EfoqO89faCE6n4pqx5p0rFMdK47v8\nFDuJP61TuQ9VqwgoR8s1nYfkj+6XBF8RXCoSb88BLXy+3NcJXTKFis/DpKeCZR2GXho68GF97+WM\nR+nysGoF8gESXMJcw/flxDGWv8sZQIeesr/66T5pw8KRtxH4BlOf2mG6m5jM1mmnoA4tsIMOsGQY\nnVAoJoBm7xb2LX/bUrqpJWQcuElI6PIjjIPX8eEblNVa4Nk9ZBGdKe5TQi8tmXz8p/i/H+V8W+c+\nXPjk6ZgPRbzz2eo1gl5wMWl2FVK7QBjDodLaXeQRE4cHEmGRpa66n5af2t7KT4zJy/iyoNFI07Ra\nzcIBJOxbGiu+PDDHza10YJnDpXUJ8Nh4IGms0pq3FOihz2OJc1kHVYFpYXDih4tspY7BLVuXRMn6\n0Ihwda8gCcCYZSU29DYSCAJWgosNh/2tKEqJ3cFpIcjAzk1lglCQj0iuh0g6+84CXaJiwKbb1sDh\nLGyA+asQqzJhfYaDwzIi/r8a8mx0nPZR5Dz6WRFa2UYVXfx+XcoRTnyAIye/Re3cJ1XXPyjdNQBP\nTcoAUNPubCb2rgDyc+yIqDC5QMT0k8E/dqjkR3nL2tStazRfo4Phv0XW69ii++JR6rFDn3RhDC5i\noMO1Qr1ltagCCjV2cTrZNKforQfut9+XSNNxlEPk1rUhUI+TTZxsInHX9U9jbh4QfGvNN/OzVpT0\nYJAh2/FpPm+Iupav+Il+hcJlE6hTi2qL6mpcj3bP52U2WKvgfi4VTweV/rPngMQ98mec0psh9FyZ\nn7pPkM+rlkk5dJm6PvNL8qhv5gm2ajEM4JwgWV/1yZjt55av+xzrh5QfeQldPItDoVTvkjPAxuvE\nfnF7kWOuBbx0hohiPgmAaKE8WbbSJkjGm0N+tjO7zzcbSs1eDliDjRKoEBGy8AEfaxUNr/a8Lpcv\n4t8eBBqVvOjy/c1o4vl4upmz0aRNae4QPd5TfHIvhpCsXlvoaCEoAlfLdSce1UcrPfFRSTkI8WJv\nQqtN8CEQHKs5yW6MJ/949NVihq7JF/fn8EJwUkWPG6Q3ogZcxbpQXd+XvBHP+oERyIIZSSYxDG62\nrEy00ZO/g3IwMkaSYK/8fg6ZX/s58VdXCz13ZabWP/Yz/Wistr0FwKLWMqYnJCYB9/dmysrmKY9W\n71Ca8FBh4ylAnnLT4wt6TZhdZHSzDRfXc9jHs8YIUv/U45wa6DFcvqlad0IRH6PsibWxSQOG0UVo\nYm0DTwm7626OKtxQJD5Obv+vQmwwIJHkSSabX8wBLAHkjyUt7zRx1+xUMR80FjbnhZj/5hxPtzm+\nJ2I/p8p4HC0L7etNyDeV33oI/9dpUJgMbKHO7b2e8x52rEn/145s2r7CSHgT0VYoM3NFP19VzO+a\n/atjeOWIMmQWl/eT4+3CbOFfljuhaIlJ5ilx8polvw5NrCkUDdajExBC9LnnVjKJs2hIXj8FI3Rq\n4co+dzLfwtSS0Lky8p0ABhMWjbYGn6kVl4vnuOlJTt2VGsd++aECryWuDGMkGFHnC9MNifuz8L58\nFJkJrredXpqgc00Ua90BBcqsu77H1nRc/SK/pbOXPwzzaCTgg89xhMrWUlUcd+eMuAQdDclp+2tB\nrgXFWLcqNKZMKL8f3F02V5yJr1isBuHSMyO1hU9WBfVCc1Kqxk0ZFXQmQA5J7j0/dli79XqQM37g\nTT9x7Cg4HRECCeMPNa/Gu+vknLhBETebp9QZF0D4DGJ95Tc4yVDj/32M2xHUGVWEwk06GuNW6NLB\nFNxmUrwGwPmB5OTl2qmmu9eBwIL3epF0dVPKnlKuJP1HY1UAIqjJC2Z7h0oiziXBVYmtyzP7b1On\nqepKGPAcsr6VPxBuB28juJDHYexZbyaJyAfG/WzYfrBkp45NoOgoPwB+ZWaQI0kekz4hD9eakyPL\nTSHlHpAPlRfcbP1x8OoVdwAdgV4DfutYZevSyG/BtroB5WduoXh2hI+hTvpkBSBi83yWDqEO/rm1\nGayLkOZlXYtb0iDuK/wWJ+KzDmB/3iiRu5qsaBfACBtNnhDF1oRYOBuEXLe7hQFC5BGcfI+KeruI\ngIf5wPv6HZItMsmXnbp2V7kjgTUIAq1tmJBMbDW1NBB8VBEG6mGPOwl3f//1GYFBwt6ckoA3h/UX\nIpI3SaB9JpGlAstTkgd00cBHjQzdDwzX+PfUOxzPfpcA3f6K7/T+es8aGxM4sFB0ihF5YSaVdFMz\nzbTSgS5sMn1Mk78CmsWb4JgTha39Y6NSu8TYHP6nSqZzkF6qBQvX9B9N2z6zK9cA46Xz95lyCOLC\nfV2wdRFS8zcYMxudWwIq7IcosOkenckR6dpZyZ6oJf3+KcxmpFNhcqoTXcf+i43+5MrVvBJ9yOqY\n/R0WAJIImMjXgxY4Oryf4LE+4iRn3KqsvWVKKRvgntJT0jvdZezYjywIuwnmcHoxWJGL06eOXGFM\nbXsRCN1nCMfdNh8G+kPsN+LzOuTkubNMSYzV+JsarBo9KGUdyoe/POrewcrFCcFsTQ/U65ItttLq\nETzoWOwdLiEhFdCq1WPFU23n9V+88CM43ehddt+wb+c6CJemE8aj+x8rcxwzPr/0W/n+6PxFkfED\n8Q1KVJ2Zlv+9HcTl7Pxt/7VQczFUs9aY+dsSGRVh/WCUVEc8sx1lNRAmtizDclo9V9NscYgNq29+\nowvnwG62p+jIs4WI22Nlly+/LFoN8BblsFAtgTm+WAKb2iZmC0jMDQjyGwnG7NvUw4fQz81rKTVG\nkGgitr0CJcrw5uLHbI/GwUsihQda//XiFKUrV0qjqpzLwYsYP4JzfOh7HcbXSgSsBYyfFQDbciKA\nent6pvvXHo0y2yPaKeleCO/tDsDUEQDMp49hzAUC42VBJSjLfFkaS3+JhXlH2x33j8qUnMDQjRso\nDIsXyitA6TAmD1umNDsJvbtalvU50451Ah+B57YPNOcqLCA5ZKcaoCHj0Nb7HPGWMUq+6ObhVomH\npz9tT6FG2yWQfsXIDUyc1QZpfcWaHqF78/2dG1N+P6wpeHGoeh4YbdmABgyKZ1CQZO4hrAbHF0PU\nlaG99ZTk5TdAMSxriD1JzqxUwTe1bS9jlFfpocAeqH7m0NepPOnIelh9W3hCZvVWX+EXNI/CsxV4\n/j6cU0Yo/zIorY+it4JOTgKIbakATAJEK8GOn6EcNgD19P1e6oT/hW0MmpNJppZFwx4MqSbVqiht\n0pMqom2Pn7pr4Yz5EWcjpqD6B5Bdp8eS1PkK8ZR6C7msek6s72FUbO8cfPd0GzT7FU4uulXt72Wm\n41I/wkgXHpiFS1Eyw00ypyeUSN/hqonAxpsrO5mw7AKCIKAyWzsPbBgVN3yBVYXr+XsIPctZ4DCd\nKyWyt443UNFLiJvbOGoFHdeeF+opRmEuszdOZlh8meIIp/sugewJUTTL6AuXnvcEjFJFNAsbruKk\nMcsn7eba+upUlHs2qtSrE+hGtnyNsvxl5fma7Tjd0hb9fw27hIVX7WPwwuHKWQ6ok2Dn5pkPNeT9\noSs5N2JAbcCjh65tm4jzJCfYgBzfNOx1IFPVdxhjH6f9owKxWhcsfaS+lGd98aI/q0lXp4oP6GMx\nPt1S63a14RHVvuQC+j9yp3M1kr8WZPrJxitUHCqygVoVia9fPnsYw3E8IaPlt2a3frU5+RetfNm8\n+4WjqbXj2Fca5eubTLWor4LZwyiE4myd6idB0NvXOUBgDS3Xhx9PjehTrs/udoCSq7ztmqVqMGUU\npGOZp4IyELIZGsytu1XhqtbObewRGX5lTnMkvLv9z6DV85CkeJZJoRkN+/iSQ49iVifuYTRS5XYS\nvcz85QT7MZGj8tr0zBEaEvEmgqsVFPA5Q7k9K6Ew7hwzWrzAY+en5CFYI4UVv/6qwL1KRsPey5+Y\nhfGIYpsjn3i9NrYX8hfRZcsQwRgT48vqR8wKqliRckiGJkx8KaVZLWtId3KaR9eiGyOlDc06jD5n\nSWjZdLMT+IYf0vWnuOtayM9KItkinBjsyc4P5VmYAW8J8ZHf9lIGyes+RdusbfXGU1/31qnroW7U\nAamtnHQhdJG/z1NGw2oFwLaWGEmA51tuTJDhKf5mGwM04hKNu77QT4I4ckg3qBScc4gqgUn0g5Ux\nurDG7Ur7U+d/dThpgD+dbKa3V6T2DNq0evFdbYF8IHE/BiGEFuKtOPOUlpp52dsTUgScuBXExGxF\n47B3vNejtEUNTA10d+RMbGC3/e8+RKxhPvv8NCqP8vQkIbRiKzaUHyic5kErUgcL6POyQOm9Vb47\naHNAWVwqn3F05aQs4Sx1anRqp8rFNdsKBaqfSakqtWOhLuThf0ydi81QyCbexZ9AhFe023LzfhrR\nVFs7UdVRn1TPmPEsa6K+F09D6UOkWMv25iC+OdK0O2tkckM6C4HbkK6EBdIgnuqxtqCmARAqFmAW\nB7iaRtTnMnsrTDcDcx/vTAoWUgDzstyu7HXrxksqy2S25G9GUU6xCJbuatvBo3rwrIpQtVlZvA7w\nHJCp3GIFtwBJ21JxlAP10qWmlPN2kPmVQny/+l+VSbQ3Pz2y1IssvClE6fMbtlHkkxJ6pco3HmUZ\nWQ+pJsneicWG4QAR0vmmulHBv0/ZGTmIU7fV35OGRgetElzEH8hYgsyTutvJY0yLOngUbrQt8pid\nNEsq2uG0cJ8IHWIgtatrkQjYQkt+FCXP5iDSH/CgYk8zrYEvLOQGLSvOsPBdQOXnIHGy66nAgqPE\nKJ3w6a8DGOAQ7gGZg6Ok3JHPkTH48ijihLhTJUqxw5vcDpFlrZ1tMifMnkol96Jbjcd/yPa9Kog5\nTq5o6t/P0VWJD16mFeKy/emtmUFwEbEAvP3Qo5ZJlgwmdsWWsIe8dho1CWcPMpzTbcYLgKKIdXDD\nI5GPp9Lq25JOE51UC3pwy0cPLEPLUwedRwjSRZliRwHJ7GabH/Py6MnvbYgdKdwb8QX+Cye2ow6n\nYz+icNff9IkGR03OWAhrvOvWo1ZuKVOfaCRezb+4DMGp40VarH0PTbfBBXYefFZoDD2pgnC8HZPI\nNRVIc8b4itS06zQZ7NXyFCALQdIAA7F760EWbUAuggYSAA6mZ3LRh0wZZK9f4Gb2T1jN/jpo2g6W\nbxCW3jjmNQayDb85OuNACq6bwcDrriNzg8rcjU8hmzc9b+c1ydyvDIwHo2a80rrDsO6O2zL4mD3f\naLgkcKcPfqHZZUYtcXUo7Z5Cpxck6bX/Rb4rIcgy/w89oCWZmS8pT4SE96/RC71OFesKfr2v7wxc\npWCynLFzK9mST5QAQa8yoMmaVaIRmZmuCbZiXbilPwVUD9tS3weefAZXp/F9ooLmPH9Z8s+qpptE\nfN9rbeVYYnhaPXT6ZgDJzB2LITJNIG6Xpp0sBSUknnaU7WyJaMvzJaf11sGL6fi4D62N7f9buWHK\nDi0nr7i9FDCa8+aMnMBX8tHHRG1Twrlq6RCqOtF2o5b4Cj52lYDScWxaApvVWFx3qFrNaR8xeEnx\n8RBM7hZcMVBPMmy9D0wAyJGN2dFIa1Y2k4qerEDdUZiWVRuLB0s4z4BeEiXk0D839nIbfu9u1gYI\nwJ492i7yt4chmWKH2b4QV/n8DdHlg6Oi/gcQ80bnBhDhZqwglvQ5FmGkK8ojIaaeRni9pPj5cC7W\nTFKU74gU4SIkkwzrXDnCT7ycVnwvs/2t7xm9m+/h8YG1o5aT8qK5oHDloD1DiltTw79R3ijTFWB5\nzVisJi5QjhwzgOdS0MK2OFNSp3KTANsk92ZeKR8GNWy2ce9mKgNXP+pbaMVqx5IORiO3pJi4Efwl\nWO/6Ht7F3m11Bv570laVHLj32aDiUfioLLyyVEJ6H6Sk41fHCx8Mzc22RzFHPL/Mz6n5GOCPiewA\nG5HNzKtDfvp74EB4vG4mKUS8S7r/5K8cvoJbgU3O5AtgCmsjiqfJXq3sUNsYkDypwZL5G3sgx07b\nIxpIAk7akkuwYCXEGq+aCaehBrGfpEPRtVBDmLojIacybB64UfI/lccxKbpaK8tqL+yPvyqJExS8\nQt04BsPvx5DkBgMZAcb5suBN1n8YR1Na+XoWinwNOiY/aKstFZsavFyyKFv182V+W3UKQaflb6dQ\nkA+lzs00+vTGcwJggLuZcwYMLLhT34oSk7rvwDXbUGEU3W81ORiP7QvGynP6vvAr+n9MiU2ja93H\nvlSl+/DItpYUgH8r2bwXBYqSGa2YVlK2Dew63q02FSeVQaMIkSIHV2UGKDlmYzNFY2oCyRVGf1ce\nP+BxOCp4UF/sFKDgwB+f7jcqQS4GrZ8f4U3tDeMhENYSJ+voJdL+3cUj6D6ogDaFTxV7B31bufLy\ntNiCso30Qe7SRVl2Jg7SZmbgMz3PTqDxhJBaZGQfT6ql5Zj4Ql8kU5u2Mf47wMFEE7OtsEEhbaXp\nb2Bl3YsgbE/23hUdGRcu84rXAZSIE0nZxVU0UGmRXha3921qulcRz+FfT15Fw4KBfGuqNrtQeBzM\n7ZS9abLNID+g/h7HCVRm2nYqjVWsDkmpDF7vyKNN4OGvNu3BjcxJk9EWIMjHOPobGDCrgTPbNttB\nVQwgSAzYkJhmbxG3Vf2l/yEExW9SX8XjE4o4/McR16rXHuUmSgb6M9UnVBjv/hJIvJniWSe2VIJs\n8NO6VF66QK/bzBiWQQz2YaWmw/C3f4TfSEWtcMHdSC3p5xreu7Toeos89KymaPCFezGj7w77m8ok\n4NQeJFaf9qMi0tmjcUeL01okKmEdWLSKLyPPmwys0M0D4xZ1xNtYH8cn5M5TCN9G8zdT1XXzqfg5\nLKnGpyXCAC7XiDAx3h+iEC7SXIqskZIWywIsX2jXwTbDagy5DYLJ5h7MZvNqJfUyA5KlABiBR+Pe\n12XYpznDyUk7nvO9tJ1YPNBwXIEeN2sz2Sdqk8dc/Z/g8bAtGgy79+75dTLr14aLWeVf3dacx8yf\nrkGUTM3zrvN1KT2RmVC8KEy5lUXyMknug95RH3IinA9Pjbx3ArIcVaqnaS0F6FNtyluz6ZeSsGor\nrLJuTyNR8nX1CSbCjiRsh2fmXWm/bu9KdGVHy3Cp/W9INiWr27kqk8tPxPivzQdU8azHRRNI2s0S\nEli28RgSc1eYOxkzLpncPh+vNpM7cfu/XCbjcKckIjC6Hb1v5Av6A9cpMwgxlit2Zylg/qfF5zaT\nwhsAZeiRQ/YCAxKGFeYXetdpMwe6Ehmw+Z7OAtZHqmEk2jSZbBGISlJ2gBQ/py1ZOSYk79wZslGg\nioZPHFBS41dWYTNYwzheXlnsNoOqjfeHvjfHvdzpaF5MBQLq1ydsfbdSe7RjLXjV2uWFs9DMHZ0s\n6qbK6XtVthXgd2ihoZhSNka+Gr8DsP1eCxXNf3KZLc1//RHP3FkKBt6qOihvAvDpLgn+H8zqtSt3\n0sMmMIanYf9UERIfPVcyLeT40jQA7SzUn0qAZ3+0cOWIA3qBjZok+1EIwVrjDnt7/cDVO7I4NceE\nFcWWxAlnHicBPfCC0zGQ7oGun/BZVsQzJRmGOXP8AFXshfcv4UA6LmnEHFF0dz9C/vyLgHkgGvbl\nVCEw4TF0lOTk3d2l85rgq5sCbGS9CrAzpQ0aWq2BjC8dYLr7SAnmpbRm74s35ZsSYNF9VujBUgPe\nUT1ucgStIaWTA1+LvX4K9wdKrd93jIrfhLuXN67awT3/yacqt3epSjamXbv9nAA/P63jc08BzIEa\n0kNPKDRtn/C9H2s/6trtntLsxDfMPfAxLuMx8u1nSBYpktK6crpgLnLRRMp2pK6Y+kxr1jcEU9ah\nQFkMYrcGNu0dk7pOHv5HvfUekoOYlh1iW5273sgSwisE+cE00+D4ujx91M4R2YVVfU4ggD+lyL8C\na1oHcuArluZcUAZJ5eCTgXllW30U99fe3saKPKLt0Y4wLacLhtasNOQyH7DJnPzvJkEPexyKmVbg\nPK3xssRrSBfU4EFbTLUInnyQZKL6CMSfcHpLmnqF+CieVLd7K23yB72KZqJDQfcSTH8B+7e+T/Cm\nHldre35iMiAhYomBodNQVcHbhkYBV5NNGhQzI9w9e6CMwpv/MOZSt2V7D1PbWTtLcNytmER0SaAq\naGRpmbM8SahotJPG5kBgyfg7pBewhl5XG8MTS/BI4wMTgAHtdtVag2TK9xXBA84k38sB7hDYJlQX\nr7ScVEbtpsSXQN1ZZjVtIJ/aCvQWLHd6RKc0HD96b02KQ4EZMEpnY/3IJ6UOO7Lo34as5prqQCHP\n9ZXuOUPCCkdNGznyUPh4W9PDb4n5pqgVYwcwkzlJWKhrjsIALQn8f2g4GQA7ihS18DhZjythaFIi\n6y02RsIFx8KbtOZIpYE8E8SiWY85uSEUFyATOdy/MqKB/1p/qILqyp/ioZuhMG2A+LjE9GOOYtvJ\ng0zpLbmYWQbwj3CU6n0fsGxxEhgwWbwR24ri6JdSlrxRtB9JUs4CKGinOZ46F5NzFD8W/zHAZCtA\nJdNZ0+wVNp+EqQcmPSeYV41b57IrxHYV6BPA1mwD7dZE+troEmn60So1fvXi3SqGmO/998FEJ2CJ\nyhUI9KNy4xHw5s5QsrBnozbsrDhgDs+1EM0N7lMgoGo5xP2QwOXhj57mJD3ahhAm74r7LR6E/y9U\nnrQSZkUIiHhAsSFZZk6MZI4fcMj1fZhGmruRa1V1Z+igMNfdbBtfRpPgfmsGUB76tPhWFwWdrGax\nwTCasGh71mLSKDkWHVCSmRnuy08pvu0UAz2qTbmdrTaAPjEyyD9ua222PwbPcxm4i/+qFdrUwhkY\nw+PpZw/7SrIE6fWvzKmIHCIJ/B6XekmsjVVuyesGQyv068NBHR7OwdZSKeuGGstu1oo8SX4F1bY+\nzyUIFsDD4kdMX95ipCxD0QQdyYqNfOnZd5NvG4n4r+KitSzo+DowBrcAZFmFmzf1zMR+9PyPFKEU\noZcsYr/fzs89QnQ/HtUA4iD2M/kWGcmmJHqM6V85CJZ7DM2PLuh0bxmwW6qPFqQs3UcXzZnJluZa\nQfC/slGomuiY4sPMmwa0oAv9FRBf0D+hJNO57VuRpbU7NugUJdvehxnZAMeZFjnTgv20OrjZXQmO\ngUufIeOgcXXGgjcBpsfEPlsP149+IQq5kwIQq52y5I9IiR+PcQuUOXvolahqGU24WuOz1Xb9cpWB\nhE/27isA92zPj8yw6dkmvWrrbBIIDojxM/nsYVWc2Cqc7Nr/eEX8Rols+EdiLqMFTq+LjkX3F4QB\nq8tgQNslKT023TgjX22P7IYzqlByN0ih+WNPmEMQfKWOUqnCJOLsCDjJmUJMQ2qBNAQW8xnHQ4mX\nNnPC91h2XhEFRMNwtBDOGLZ6V2qQBlcavanajwMRJyZEumbe6/Pk6SwxhB7Wd5H6p8PM9LAZYncI\nnzTjZ71qyQZZJmtKS6sMFbiZdU/hTDavmtjVL5dd2Z+Hs0zSJwOSBKaGRYXLeMM8CKc1WwtjBTSM\nHsBCrdoCIF8ScvSy1XyILuHyTP7lgNIXYMAHwr1O0dppXkdPS6qxBu//XCzv4ejJP1Ua6LFyWfHU\naAE+LRKlPInoHavKHHyLsJCfKLZdrwBHYU72xpcA5Yu9NtRmqZt+lEh6zd2HoJZNXgqT2UjtOjBc\nqCUTKP2SAGyJ138MH5gzVWb079H8ociCufL9ExyUmGOsgZw4O58Jjh8X2rXpLp1B9CKW9KcDwZ1H\nCw765xjFPqWqZYQCYqPGRkqqvXsxYMMlb5ShBmtXocEYRNCIPwIFJgAtMO05M9I3GFZAqLJMh4VC\nOaZmMmAiHEScg3eaCeQ6z7xoXD2223s98rjgqmxwufPmXxt1DLzVukFgBrr37S2uxSvgTELnncDH\n55WhqGoBN6rYjXUJPfPu2H3YZE2CrEd6gQ8EREZyo1K9EGieMhnt8dZTeLlHVfdYvLWo2fa3CNrn\n4Bs+d1X1dyQvzOj77oU7sFZw6nnj9Ti8teEH5JTGKzAUisNvzVUbLcwQZtJIdSX4FjSsyIetJpV9\nGVmjptSmJRCSDLPnDjGK/uSMQoZ5nu7WYrtzm3dPosbdJRDdnNkpNN/x3WDF7CFH6nTmrwf0fJbl\nFt0lcBW55tEttelTMCo1zzdCW44/vxw62CYpteqLDLAPTizgOWaODROg5CaSEVxpf9k/3y+XIpVm\nHXQzo7lJ3fxdkLIp4zNiYqhrBSQjZiuJtGaST6koKK2t6KDPRJH8nqK96E/45iLVvZsGPF4StNz5\nipX2V4lcKlfFGQ3sFKFEo9JvcGCBxzpsukdImd9uOxH9Y1/Y329lt9LeF1yhjrBC6/rHWCgnKKUq\nDBCGRMPNyaxnPlHTbf3eIvYWdWHvhH7Q9RObVEzOOk4zv6AY7Vaa1oMi3eKIzMq+c9vKVNJlfMZd\nKTdqSV+Xkdu29FhjLcVq96+fGUsVhQ10+ZosworTEjSxYLyxwhOUmaRsHFwtlWDhdBMqMlqRXepI\nfRiHpMDL0uY7sBt46jLC62lAfrJv1CMnqYENis9NI5ELVp5ZdSIj5/U4KGphAl/4qr8aqicxUbbX\nMOT8JUoF0acUaZlkKhKjTEIO/EerWF4vQcNc1B7JeObEEGgtWcLkTQQSfnWpmAtkqr+s7L2/739I\nFQ8HPCNLrW7ybSe0Mdjst4x6RLrIfWSCkSzooNB/DsrqkMGUJ2iHQ8YidA+KeCkbxmSRuuYpFVio\n4CWr1HCV6JreZzKmDkzxWi0fVWxvOz+HzvplzcUgSXYVU9QQM6kgSQo7kTqKMcZqlUyF4JrTn+eq\nPnqjsJtUpLsqzNntvcCTXz2OFESF2npRo7Zggo77/yQvTbImQuEX5apguUf+pQQAkSEulcEIDfMM\nDtIBr8wvjsQXaCgCCPCIIx7lYaxrnrlIngzPyB2kcfD5wmNumnBy+TQTSaKdjhd/FspVNh+Og/AT\nNftN/Tn+OSWuY9agoSM9MMoUvcpfZZ34wN6o30u1UZXarugPBUkw79AY+0zqrONNyvVf8Zxk+rZw\n5gahuGiXWi/l9eUneDxZkaeRyClMQcKQLFg+aBDyOGGT1slBJmpWn/rMt9VgBrVgozKdCe8wPfqZ\nT00JIYOtEBZ9A3O+Ek6hqMfALCDgWUGvZzPp0N2if8k9Fi4q5h0o0pywfCSaTnIfe3nO5eQdCBnk\npmghUdYqyDyT0JV2i9siD+vTaY1FCMKRXz9b+Rpd6o8sQ0Pc2TAQs0KzCP74YkOmvYIZoy7xmJyk\nXsRAZTC2O++TPJQxA5AwMRC1iVAUMc09NHl3NdtQFjTTio+A6NqrOpUU7Sxp3P4eRdjkgICitk4l\nAtBm/ysO4ly8OdO9cLAFDY2Isa1rD4KI7R5hR0g2DgJaYY2YqDayLs9PBc0RlK2WrPNV/AL4Inkk\ngtXQnZAC1j1uEpPqQ/t7sjmYW+Pyrm+fKLEQFxGgiNfJySCE5cpWykw4UTdZCAX3H82Za65vJgyf\nP/dOMYYWntN28jEtjQvSwWuvfaUBJOUQ+cK75stunTSf/NxwqJrsbUfmkfD00wS0guGRCuLk56nJ\nzn2INXMo41XzCVVR6RqFekfY4eNOWXqywGkT0lHLWNctt8iXPYgTnOFJsg9+G/IuWdHNtEpwzAmN\nrZCSX6LYAikOFLzCKcWRYnpjgUfpl6kCihMXVbVf2ujuq+/VYWNl5G5mUGmeICtYjdJXKZby8yKL\npikRkUeWraVnTehup0JLwezbF2qi0YfP9LzA7iYBrd+xhcI+GfyTZTrLhi90Mn7/T9MaiBM1tb9r\n5Nq0jsJMr38bCm+pEgKQwXI5wysdhyHPw8P44uEcfAuRc23NZdhCuAiAYgI1qZkYgL1z3cJCRbI2\nw9E8fR4RdzSiviJ3hNLqANjjX6hwpPmDSMMcoungEcubTLWhyjo74KF+cdhkBP6jXYbeGON8Bp+p\nLiJES0SAQsRwjoiF464NiJsdv+OjDxUuvtL1DqFU8nP8uZi4Ru59AyKtTWxAKhT5P5Mn/sSypIXf\noeEpgFXbLhO9KSKdbOU8STs8Fgg8J0bgOn4iGb0QKhpSemPGkrYli9eskdyS6ml1f8pz2HMvpajI\nRSxVvM2RZ8Gvb2iVMte5btDsLRaMh1RRmBsiuWEHVsLZUTXlP2FgWEIf2RYQ0ietVEbR2F0sit2Q\nKMjxvX/bCP2EgYO0rU7wYvdGO8//8EOvOZ339Z6p82etmPrsbYdbBp/IBealfJdp4EaBjj2xYR51\n2jGUXs+RRmA4g1zElAe5oI95yE+XoltiYaSzBrW7atJKbBL+cwr75f1x06yMASld55KivP7JmtnQ\nEJqRsON1fKxj0z/FdCJEcaMme0MnDtSFRe6L1CBiy3IXsCuu+qWRcz3BZL2JWE62HO2nw+xrAfpc\nx5DJNOL6ADZdcaO72cW7EfJBK14sPFO/7K0oweKk/JYDVhrVU1XFRSMJ0uv9kBzbDKi3Cj0BSSEX\nkXRVgntkgQvR0l1gHzEDX7O/bMOf8HlH7m8NM2wfPIEM83UdVZgxgt7ZKW3AOGnn2HxDEwq0feG8\nG/mPZ7BCiye7laLtOlhTl2btjxTWkVsN0jRmc1or+MOcWG4BHRkuZnG/Y9ye0xq0aDcXag2Ob079\nbWU2GBXFEEk1iuEuH/UfRP44Ix6jW3uuONGlNpS7I4oIGgtN1rCgal/mwEu6Js0xoKQbqgvDSkoX\ns/XA9MfFTI+U+p0tz126iFORr9v1x2Pc6l2XQjnJKP1eTb3BiHHeiIWN7CvbB9mSCPukms7Uv4oX\nLiyLKca0jXvR79r177AyD6rA0fIYLQCyox4WjIVi3N7nbrzrKuB7rSXCblhhILx780NlnJ/23657\nUjm7S12XoWgyXLIaNSjJqixWKbvAYS2X0DasYhqUHGfJIjrxOcP89JqX3Jol4YN11qadSeDQMU77\nwrRaBuzLek9LLRQ260FIA9RzldkEeuwydL2gaVK29YSJtuqpZwX2GVga/aciWMpUmjCrSEB4XYbS\nbEbrbPhnIBgWq1v0DrPxC6ebY81gEDzCNE5ADdwjp6WSVFAJDvNP+Dd9aKCIXJSOvRtfp4+IzhwA\nYrNLRbKYyaU1Q5fsRsCG3Mf+vVON9TZLSuwGRN9DVRbWrjff0yVeMTpxGbMR4q4bDgPpfBoCoivh\niS05izmlrihuyTmKQE8/of8lrv6bF/q74v/CF1TW9QPgfx4emGfXaPxgPFBbWjDfGaIROinhZAj1\n43wSXHLl/7nyq+XryhJ6NM0T6NyjvrkubLUfV8uOA5gLrmPNvEcAHJB9kr1BUnsJzJbQLMBBcQF8\n4mqne8nTFLzHscHk4/k5sGlVv9e2Ly7e1R3ublGdeXrwKeDuaUca9Pl4Qn/dVFxDyslU6w4caQLv\n1Z4jGFvWxyFyR6C3qbQ4eygNFecuO5zLIu7dpX6GRBpUttHt0otv8g0J7N/oHJ152I8YR96iLe6r\n3ZitFGgFMV5EwVjJdv0vkSSXtzggTGOtiw8cs7eif/8Aj3YI/NHvf6iWIaVldfIwbi2cWTn8DwR3\n3tiWpCA6PUlCf48K63izIbhsCe8we6tIn96MLaHTndYG+E+GIt8YO0jC8zvnNoeYrem+8JB9EQi7\nDnauMuArpSxC4aB1C1JIzq451WY2mi+PPXq0bcpFgiDC2u0rzf8gxDMna4+tsH0L4M0C6umaJbo6\npEvKFot0MRXMtRaEILYx3xg0RkAuI3psoO2sCPKt/wNIMMqDxp9/MAkFg9dorZK8806oYJaMmz8W\nWiAFclwEbwBwXS4RaamRu61JS6tSj6jvi9EaDNd9b384qMzyjuFIrToNLmufh6QmrPfeKKNXldfS\nYwPqFwfSEeLr7Gkc0GdxLTwwYrUoQt3nus0EmYyuBjyVtKvq1NtCoulN2ePvUrat0O4CZGF5tHHE\nIgxJrXW721QXAQ3WYro9QdKs+LsvqqGOw+zYKDcpHJUYTHRJmBbLMIEf61Uld2ZW9g8FN42s+coA\nkOwVZ9lGwQtsy51jmYoh7/sNQN/8xGp7uZZgyRtxJ7xV77c46yPQuvfcvxwcThqaNfTtlKZFfNL3\n6HlDEBMz+IN59or0joYupUf5NOWsJPervC0y6yn4SfCz9hfuIlACnxiM9a9SvNpmXTqqb8I/0Wrt\nQHscvZHEAL62tan4KdBBlRYl95I8RbMUJqgoG+qqz5jm1Lz0HF0lgoTJdOzVHnYmL/IKdn3A/VgF\n5sk9f4v41dtaDKbbrkFR3dt6cp2RxWaa5jnsvesDGUpYvyAVPsZmCW1oZlzyDH4W2OIRnu3FCEYf\nUEgGjrsxL87uJHf+uy9Grlt8jdSJfSc9cqgevSp4GWTAv1b/tLpmSqCp9NZ4GfoQVCpggA46+at3\nkdEiL9FIV0Jgk372O7yndQthi+XYQyqPpHpEgAIeNXErF3F/e+Z16r4QeHybO6hcNVHjjm91HFkw\nfSgQtjjwJ7jXsXsjnqQihcAiKM+xs2EQGwavOKwDnavazGY8yIdKDa6QQmBmY0LUizwJiI03uPFk\ncgizcW8qlZA5l0keb+NQQdZnQgXCC90q/LPqxZxEfdOjqz3qk4kSqxVfM+2Kp7Q5OZ0YDInx8EUv\nbJRfoKpGuIxvBCcau2KsQKIdFo8S5sdF4OvLkS9BBdBXA92g1Vq69YXDET6WvOzUN38iUIke4yma\nSYhakJ9M4mjP0Hvih/qzecOXTXdU4mAKNXvPr4ZFtOG5dbuGiAWPoUzzcQrbSSKIK4fLj4YLF7fi\neVxlKLcsklWB5bisyaqe7xo9Tq7rC70z1g+hLisUjzGl12o7N6nSiLq6q01chboI9fzpEMy1ibi7\nz5sTiAweMEAHAUeTTY+49DPyR+DYVWW0in6N9bfZSdZTlMOAqDA+c5+bcedMRBVmxE88cWe5GnEj\nTCP5oBcMG/j4EziGzXWEfU//mtXjZOAwbxIp9r88Dnzg/KCuC5vGuBH/Y213xP/vtIq3SF9P0MHV\nsuUaSFxiYm3b4+ktRk0t1dME9DrZWtwPMdUyhcqsX5B2Bhvzph/Erg5ucm+j9gTNZYNGkspL4LId\nOiKgEv8ybZTB79WxACDbDvmFhwgcBEnBcjWWUzJS4Q50tzELcFmEpzuke3AsUY6ftvKd6pvituat\nFcdOZyq6bsXGkDc23vPqB56OiCbxICCXv1uC+YofbDnLz5LGxEdD06251MXJJVQKHq+ml9UA2XeW\nO+hG/BZ3BTDS8cDnGzM4WHn1oabSS1EyxvVjgnUaMVQ72psXohe9P7dJXP4wbKCuhqM2GG5/3juy\nFxZOrS3dZ5NbluzHt4UXNrLz+6wSff6kY7CChLA5BDmV226Ed0aSSozWACSBqB2MPQr7JVoLjd8Z\np4sAbBfWzrQ2gU6Gpy0oHnGg2wJsKrLLnSdX6aM7rIZJXap0GljMSh2VhkJe6qTTTTMJVwoSr8Lu\ndwvOo4uPaGTiBKwrfq37+Xin1qp7qBDevyXGoVrrY151xzBqwBP5T2/V+67s99sbA6QWXVIBmDEl\n7+BG5o39NDRXr1iQjfJAahdk2oGJQ0KtFA+8d7uzWj2aRKz7LkJJR/VPuW868gZKHUKwIfp1XTIK\nIor2qe6mmsl9p5NiFCKC80QcoAXt9hv7QymNGXvXQTxBOA6Ok9Ff7JwarH16GBoGYSvcvMDvnRVY\nrXVblUOivpcOD7lQ6yFkxszzU4PiXFRaX5y0i3g9j1ZNB9Z4BBi3/lKyfP9Zko/2aoQhZY/Fz2FG\nfXbaMjXn0AXjBUY1l2zTHlvZdpajgHasVFB7ijhnTBINtoLOtKV9nOQKQZdBcfQu+fL0xlvIdDTh\nI3EPKPXBPzsnrOYwiL8uveBtb1ZF5Q9sQV/mMVG3O2alvUySX5S8HNM7U2YXV+IGDmBkjDvnFb9v\nL4wDF8/BKuzQVBHsiu4OTYc1+ZuD3uHBRnDNDOcWn7CVvrmY+VjnAsfttMK1iu38YcUAaxq31jKh\nUiRgsJxt+1R2CMEQ4ACr71vvzDIoJS1lmJzVCQ7TGb9ERyYHxiYEkqRLVl23AjUblPL3YCPfDloq\nX6aYucIztTHXdK2ugTDUdSlZVPZF7jXmcboRC8fXknIqcn4IyeIdtFkxS+I9gm5Q4M4icWlmq2cy\nwlyfKhr9df2kwO5/D8vcZFpmlpGNhTMm9JY1yNupH2L88nmWeOhrnGZoDykp/AzUl6IPpW8JLE0m\nHCoML35Esi0HZDMLcFQuuSNGIDJbw+k4Rqa/ay/80acMbhxmMJlHQ65Gy5wl/3HHRd16x72Se9f7\nmzU2qm2nH9kwBWPrePSCxFWC8036iYMnoSwQHJTv3B3fIaGV614wg+mPscuXVyxGWQRJz9+uk4cr\nOq7mCZ928ntmnDXxxd3QiT6S/4UJOFo8VXr5FVq9w6nA4d7FjIzXkQCBXfeEMsqCj9qe5Ff5jew4\nZYy3BJr6jKHFYp4srjuTTGYDyMxw8yvoY6AsseZZK3+ySN/W2ButKrxJsFcD/KPKNIO3XjKgNX0/\nd8b0txzsc7qiWlZuehIcYknkXD3DVgpjNoY0YzSu2RtUhym3/9yMRAt/1154d9tXLpKeoVjFUvqf\n6X9RLCOoI+A310Paa4y5VZf3PbOTXtHzNTU0MHUiqhiR6Y9L7dYgULnVJ8a94UcjiQV+6dJ2vZCR\nmm1Kim0xlYFmBicl4gN40g+WCKiqipzcFaybqqkT7kFw2ZfN/KqogK/s/dVWFrOa8XB8b9FyA1cc\neuCOJkwOZ1hl5iCII4gSolRiSaz3/bOk2ijAXQdgAn3Yf9agcdUr0DQYxAbxni2S3M7/4Q6btNLq\nHAVeRLdxNvP4wEWvfFubnH8VY6SuWkpD/u6SRAqMHwosoi8x/a3XoTVF96e/QiLu3xtvNeKt0dpd\nrR+xtoZPw8JHrx4mj+BCeWteVFl4OI9DrKmP9+S9AgR7oTO0Q8rnQoPyQ9rb73Ws4v/yFV+LxoRS\nA5v1KmcvcWcDVvwulWxiRhkEn+6jG7a2rO1bzsPjLu0Ld8KI0nwCVgVOsrkX05gp9frULmU22AOF\nUrS1MXDh+gbkXtArJfTeVvk7i8Yhm0H2yj03Q50n2Uyg6Q7ZfTv8Z4wNwqKfS8AdKEM5TcuFn1Uu\nIArJW88TxrNCZe4puWv+OjvrzOv7p/Nq2yy1LsKHcXVq2lN3oBO3QUjZ+hJi742XZvcC3MrHTURL\ng6u0mHtjZ/mxdXjB0Pewkn4uIKKeBrX2xa237ml7QwCM5kwcWQ3LSuyQHWY6Co0HPPZ2HN5nOjZp\neanWuIA9fm//es9j5woVVqeTjum/Inh2ifOz8/bikKyYB9BpOsOPYg9c7hd5Q+FIVJYsYVhNeZV7\nqKATDXu3Y9mcgoNgWPvIQyedqAED4NsHjwiLc78TMgMUK0/PqG/r8dK1nnbW8m5k9taiY4cIiIG/\nv0RrwvaL1v2q9WBNujg9Rnb50Y08cnRQS3OVccpG3dTqE8IEElAlc9wTBumFV+zU2QdILaDR5bBD\ntUruqxhP/WQK/X9yFnbMYowabiBVCe2ArIRG/fPDmNrG7li6Thjo18l1+rvSjcgWTaVvqJlIxHo6\nh/FcVrBidpXnJVYQi14V2vWkYX5Jz+x0v7G56QbFcxisLdvgK0JiGbZzKn4iGeUo9aWNu00Y6Ii1\nIowvYzxlKoRCO5gqVUYx4+EZ+N4x5Eg/zqfTN5R/KqIeqaKAKRrk1xWqiWTkew2LLWexMsNUUIq7\ngxHyej6K2Zb+vDIMF10QsDut6wg7dkLcz783OcuWVhFPzP1yJpjCsGY4WXaH/GY8YHYTQAunnLAy\nddjXqS55fySsmtuWTygFrhk0dT17CRoTGtMqE9iA4I3xJgztth/al2eZu+UbQcq11tDNCJ3wW9+V\nBhlZ1kKuspf1rPriHQ14YwziChCVkwOzeeiQ6qMFDxQyol+ePAhENNNrDNSamjNBr/LiTH1K9Em2\n4Me7s6iHQjTLHx8tdgb3ApPoDWSYQzZTtTF6pRNezqJ9WVc7kCjuglC6XpBLL13S7wZ9ui9klrdR\nB8ioYjprX8v/DIslTfn1dCAIeSuRJm/+em9oFy6k58Cue9XEkjIuBml5dtZGxga7vxEwh+OIQUZt\njVvoSMQOOymRCeaL62FrqjfJtatPx1i4c2YLvNF8lOtO9iZV/FARU0IAjq6k/i1OgdstmdpK4ipb\nwbXLs9G3MRTlTNlyVldMb8SirIB/ydNFQnExlL9U1yTB0uQmItSKZMj2dYoUzTsxQzwUMTPakE1T\nXZP9qYj0Rs7ZQjrXBfChI1MkYaB+BqHMdquszr2mUc54Mb/tltYV7RYSIwKbShap9AjiDdC/w5l7\nTxsV179FV4bvctzZxfBZ1ddAYP4/J3OM0aRIUZMU3YGdNh48UQwiyvBi7dKGR6KCXXabWJTKUImQ\nZX+Of8BmXRpC6+lAZ0rL90x3W3PD45hBgHoptW/Onmb3mYaHr59XXkCtYoT1YeOOGEx+2DBi3fQ8\nrIeNzGtThBkjqLtb7q7ZUvbmAzJg27uQN+rsDkr9urTc4tEhAe1M7EX3V/XSXv30uwYpyYeshzv2\nhZfAVnOwVo+IpxR9wEk6Qg/eKI4e6P/O+997xGplDZ2oVR7sVz7sjUJPw3vjuaBUx4Knhe5kZwuh\n8xeZ1PHflbnGhtOPI5nnAqT7YHey42e38HM5tafAJrV879nUa6tp1THXEkvrxJ5ks6n9OUxLDgzN\nZWCup9P/5uAtpSTZchACms+0+9RYgX7DVclZcWSv9JT/VOi8SDiTtxHDhXCVc4bYLg6vndx4rs18\nwpZpdsxOOwXsfx0Mfj2l8vXiGjNBDvcMsrqMXv/0RYCzNCJ4COCOV99GtVioN8FxW4vINB10sxHn\nZGjiaGk3TQceS0xZY8k7Tihsq9VMZxe93R1qsNT13MMXvS0aWRHE4HccH8wv6/KeUS1tsoiPsQxR\n1uIo706+Ekc8SOjr9am2kjccBe48+kJPzw95aAPqBgGUiaBpD/5dVGkmGI4+i8ADGmzxizXe5c8u\n4QIaU6h2p2Xtb+0Pkx1fj3yBZXpU1AlJSzbhGv8r28+mZhNxmILsJn9FQkXnTcDJwdeej7qFSCeP\nYIz01CLczE/frGRRiripbR9l2415AjGVElrSas00OTtic6qRz2xtJ8unoLEu1FgSii60uLzxQBFG\nEosjhpObWQI84ZdkgSuSogL1b999OMXdV3zI5seOhUbueJ9c6yTHsLoc0HLeX9EwnJC82yCGmHi8\nHhycZNjYhfqRM8q5Wknk0Yr+aVSuNTvByoTNKNQ2aJlREcL8VLFqPfKId/oPGYoCqy9fQfYN7fK6\nnAv5nPp7E2vxJtiVlrQDT0LNZDDRMD2jsXeAZA7pmtYCYW7ua44bvbxT4wP1PrGWmi+Hog2Lxfe5\nJONquyQ67FVCmWzA7nBX77SyOsH4PvBCc4LSHZr1CacUEjtPrsGlVpTnIJ6H8jGx0xhQB/Kbw94X\n37/jrUGlES00uBhXm2ys73wOIH7st6+rrVfufyOuXK1JNhBqncDOLYb0WlJDrPAbswuH4OfqBXVH\npsGzx94NpQ141rpw97Q2rWcX+RQ9Bzd1ToK+s8SuOaTblKccnuEpiSioAuJ2yXWzohaTtlYFDNCl\n6tQrG2jKuEXt5v8VE1F1CionFpCSITir7XhLxiU0FjbO/Bht08p8wjsrzUzFAGR+PngH5z+B2Eib\nKg3AOyd5+E1XKCTuZT3mXXf5aXxLRsfJcuh6FGwAQjAdeSO8eJ5EFx565gTRndmsVkSPOTzixJbG\nlEi4gLPJ4fA0L0eBjdk/JgGQr3vMnPnL3av03+VtzG8yssG410AacQfN/PLJZkDsTs3rqJ98IiI0\nvoBMUiX+oZTn1jmrjqn80T8c5NzjXThnSgjjsVaH/VRqpwGtaBwiylisqz51Jaub+GP/s8H7eVHv\nKcjYZLiIiaSmwIjfz4TUSMagWWHxk167G9YXTPFCh8ErpkEk84ex3gaTW0Y8XBQ2uYeKA8nPQwhP\nYMyZ2RzT/COFu/1bEqaxTzO3CsZxyTHiQe1WN+MIX1H/HBeHzXUaORile5PDMe0zOjvuD7CdivZZ\nvbP+aldBgTinZqP10Ha5unwuX+r0kPKCzYjqnDOpST0YuahJQI74pYsm5valRUZwcqL0b8TYjn/F\nVRY2RNlcOY4kLd9PWhXUcy5JDbXgYYFzpbV1ZkloHIB1as6RiVx+wmf0xi51LQykZuQKhhXwSCo1\n+jTCiWWEKKG5Yr3TMYOBSuPHdOPJZiqQN0L8op3gfTpOcM5NfzH/XKCRmh/HHBduiyTaWOPN2avm\nm7vFQU+ESN5tsgoOicxHRsvX7DbPInlWNFVQUUH2YzJFpm0RsgtSonbbzBjcpUlo9QdKNcEhkP7T\njdJAqruynhiAQh41tkYsjlzMqec/sOibthHvCxYu6Hve9a8Qqa3J8hBv+2HGr+2mMapEUZbQYErG\nswV1MmVWtBiCDeTIA76WnpqG6eBFJ7adD8swLhcXyevpjT1OHGmYogiLT8Xp1nTPkdPKs4thhrkB\n6X80V4YO8tNS8ttMOqd0b90ty3qAqTDp4eX8MxGCW9rgASU+UONyke3P4aU7nPSJaK/RHQF48uFe\n79DMDEsTV/GSdRg6iKaUWGHLDqpzi3of03iuyAWaD6gQf7kC4J143U7zcVBjn1AfvZ+CVJevvQHr\nCmWd/wAus6X+xS8haML8p4WciFrrGkxsANK+NSEiClWdKUAt9wP8G1OWhuWZ944cw2EFX+Adfvsj\n2It8zS7FYH6F/7/Qkc3zko2IMOm8K6IYc+sVSQN0grXvwdbGIbMhsdmNjfjQbDzIVDJmlyAuZllU\nFopJPaWGeig8EK5d3jEyVSwL3cgBkXEnbqUgtShARXop6af9V1C++2128qQXLaTPko6FCqxnLwML\naFA5MmxLeGBcumJO/HNLR+uUQUchv0czhBrsfNXm7EIwswrw6ia3NfYOm4nn3UhNHvdOUQ1xB/vP\nBatNtacj6mIXcUdysMCw5rVA0ceLJQ7MBXgqGwwywpQ8O4JZEKwGn61xTZhYRA2iuCdseABci1xZ\nJyyYVAH42nyvdDQgiWypk8FGj6E+/gABwM44i1bergzougOPNi9XRMhYWpHuv5FZESQkM5IataJq\nVgl0A9wfzOz8L9OmxBoxO0cu6KgJZHbIOk84MIhrSjFYHmbiIXJueYovK0PrLGc+DrW9DrdgBo+r\n57hMgOpQ0EfsmT4DNGdhH4yfHbFd4vcaHsA+8rXvQPrV/GcwTU++qr0vx7V3wkiv1h+zIehHdkgW\ntgmS5ELx+bsxwkx62mp7rAxCYRdAnsEVxSYgSnRNIl0KdkbsqrH37iX5tczNpMTRkZjgkBwn7TC9\nXyLZdt8VfxHpFTbswQot+dI5S8NZJTJWtGmz3RCs7G7tIcUYfeNk182cElUu/qGtRHuC+yrTHrBs\nQOTbOZ5ZJJM6/AFJ8QF4v+9b7200yXRrd57k/st8NUZCwqJ+YerR2vXwOb3It/+mP0UDAyvL0Iek\n5L0MmHBAXs+gUrsQRpqeQCL4C8uKxSCbPgqQsGFSYg+PYPpbVeV1/TKOqTcue3G5bxiKTk0BcTlO\nnSX9fznwiUcvxF7qj9BkESePF/IbD7+6Z+XFei6lIctrZSPli4lcIvF1sWQlSpYMG9/5I4Vh80aD\nnaYCO9m7/buVYQdXySpphW54zq2mV5AzIy6RZp/o5WikQLuiu6P+OEzn87NApt8fNLSk9h0npvGL\n/wJ9APzsJ9iogYgcF8myOSp96+9JjB7x4bt83rR1lba8OfWsuWIYN5IHi/SeD2aKQ62ZvVEE5qDZ\nYnjGlnGFKn3YwCJS122RQJtqNigQX4NQhhuPTCXODWE0irKOvMiegNManMSm2hZzkzjUNsDsHj1Z\nRKuXgrLBWlwtKSxG5iz8YK9PZ7ZSzTRAzb2wj0e3acNPRTTavqmrapItV3cB4zrOGSjBH9ta05cy\nMKibuwXZYsYD/UxhsXTq0+8fMda4RimsNBW6+F9VBC6rhGwfLbPqscFOu3vSnHN5lPnlEJgBb8nG\n7SQa+Ol9skdYo8uvsVHwl94TKG+IsILMy0B78/3dmXIj3C/EraH6IjGbzXJYADrzL8mVPH2khih4\nvURehk9F7oQlbRqAAAHySMUTTIz9tpxhz9aqkqEjdj7xaYdnJ0REvhM+TlbLFhqnVKvxq2Wbj14I\nd2QyDE8HLpcbk3o8/UxaMspPBsjyXJaichX21VQwetlYQzEsFwY0C8kYjJBCqsN367/JKcExnkHR\nYC5ApbnXsXp2zIC/+whRaWHbSYG5M37sOHJqG7b+4E+rF9Y2fQxC9MTMjziry+ykpZ9cuMvOOLn9\n9xcYUj8zgG4oqDduibaaGlx4Vc9QjPgETcbANWO/CtLlTtj9YqiJsQYHiQkFIXzYdEvhCya1SAZK\nY8qwY/w0QMkcVtRG2J+VbplsdEOzcaHt/o6z21dkuPRuL/zpcc5R/Bau7/fLKnhQ8QfGw5pZT/0c\n3GsETbwIA9PM69uJVwlHc1smT+Wy6qcf3mByshczP5dNwJqfev8K+0/UCepFdrvx9VG1Z5LhL5+L\n1HGoqow+ue3lo6ifpXVDUDqOXQMSDSGdhyNdGqjrhrOyotlv9InWFDL91mkTWjBV+JpbZr1+LK9Y\niRkjCOYsIwt3R11+cskiDZDT//nedp/LemS3Np8GhDhifOA0yW9sUTg6Zf0MHlAPnlqW/3vEo4Gx\nwVv4QZKNqpmBPad2UAu2IC4hdG2nQvkBIRcfeZmqzT4JB7DS2d/aZ1ljrCfTtj1j/4B3rexYG4o3\nioPl9jgeQjcue2Y14nNt1e+jiKzpdUeyu1bfjY3NeTOcyO3ARjeFC3vi1Nua8e3lGVeeWA0eRFNE\nzocOwPqOv2JLI2uU8jfmIPrJk0Eym/LqAAXOvKPkm1X/RcKnAiwDqcHLf1eNl/6bj3TBSRfibgvQ\nHgnW0/fGHc1ZZ+JCo4lONxokgnlanY8ZbUkjL7krk0zNwBXWOPUG7MRJCZWh7oQ+PZ1Q5uipQeWN\nuqziqlLRf3MfsTlJEyEfoJYCs4X0itrq1XXyYJe2DncGcZNcfs/c9cJKU5AGb8a+pohF9/pZMrVg\nv5wpz1VFiR5oZu7vfGDO+fB4iaBQUdL+j0cTp7ft84NASHO+vyfAnMx1S19RTFr9qqqH3iAT0BbZ\nwYWcQnDQ4LxtGqpQPqjbM4D6P8ISKCIjM7IqfjTblLBKBY9RhLS+G3p0b7OZt1+n5JQ+obQ4qN5j\njEFZPVtbzTpNVH6geb/4wMGZt8MND+iTgaalYom8dbif9R4afoXtcUIqE0Bq0zdROnQsCYAItaxJ\nPlEeuMtxP0LMOO03szxz/WAbd5FgB4kkte2bXWJSV7osWzaUyPT7tjBZHZUsavsDZ/7BbPrba1Bp\nL9hfjvGmxswF342rOnqMp77WlSR2hTaaPE179bcja+H0H1Y+W9amkwLI32VfeNOTdyb5K6Xr5Ura\nV4QQchn5ixSILxvblqH18tnsr+50sVMal5YEc/RAaE25dSMxRPvB9ENRnpNlB+08xJNqzCw8byRS\nLi/VpoMgVP+t/U/S8+Nsjc0zLLw0HltDB/f97XMKm2O437enewaJrbWgXJ5tZe3C1NpC3CJO8xCh\nHmClAFnTx+O9OqkwZF2oi7F0S66zKChyMZpj79y1CQJjb9H9s9ZUjo6d7HWYMZyhyVu3oQ5DnYdn\nsitWmCA+AUwQnN7yAmnyFHjbMbpnHbwFb/4Lm+T5vLF9TT90Abn4+96CVx7fmoDDG7DTkgcaFsZF\nmOFVn10hY9E8cYpdmJAg+rUihkxfoglskKNDMmig2I5PDSgDzDbWORPoLOAzkEu4bl5cGWDnKvy2\nTzsta17M0VKO9CNdgq5Jc/hJOPujIgvM2TOjCyoLldszxe3ZVuVtNBmWHVCNWW4aN1q9uhs8oVe8\n1BQJ532WgC+lEDDtWAl6rcQsw4FhU1a4I5TM2QcjVFkJ3xlIQS24P4LQdQtOPIzbj3Z8FSzwuurH\nlDI21nkLDSvi2BRquwGDYur39j8qA3wjivhOEr5q51jFdty1+G7ViWkiUo63CfEDwPRHHP/39Jxa\n+zIe784UjHzPwmZondvLxVFTVEaHFCbLP7W4Zb5fLQnRqGZ/7ntRFS38VyeCVEYzqNeKXQ9b4HgR\nQnIbLwalYpWgfym8HLs5gUi4taR8z6P+GVFaVCVUri4y946Hp5MwM1fMC3hndh5yR8W0LD9Dj5wL\n5GRjTKz9LfhdjLgIhmI13fdWOK60QKVq9mUmOjo4bf2gfs34YLYqzb2K5vuo8RNAuKixM8BVJTrg\nXJUg7g5A3QVIk2P08Wyj98v+GiA0AapiD7debjI9Djg5nYAKvfrQxw3Od3U2MpZVVGkSrSpyYPUz\nIh3ebQg00mhqyTpDlWh76GLB2IDvjTKJ6U0RRf470yRvY2YWc3QRIAeC/UrDlvU7MDZR32pXNAYU\nfsiMqy0gLh1myasxPE3QennDR1ELf+061vAxI0Zky//5ofkTZqijM46EjTC2DRpHnu7SB1Cpdamg\n7ZokWmL64rufo/XkydF9CAnXoSPLsfuOnpEQeZntcj6Sb2h5saa/L9LYNEl9qYD1tcloqDOMn07/\nY6g5eB8ZrZ8oPZBy6QVcqxfcVfv8B/wl9hRj0y166pqV56cUGV2F9Puib5coDgXcVZjovq573bBb\n63Vb6W2o7QeWGl3N7+L45dvAP2thgC9NwB3q4fcN1GgyYRnWNs8h15vikvRyfhf79FfqettQUOTF\nvwC74ZcrtgXE4KA5MU6v2qlgwaeYjDLBQzVSklI3SP9p6jdwTPweAg71abmlLXL6YMQUH9/o162O\nGdLyya9AMOtw/a29/Bz0SAbZJploeWa2CiakzVY3KuhaIrTZmYlhPN73rKcutqThO1ESHlIcZAvG\nAmkCfn/8qdH9GEszPSnsdRxT8IZfSy4p8L6gIzB5ZP6G/HLXiX2ZNL5Wrt03pHAN7Al0Nv9Slc4/\n08UtFtXIBiEiZRNrJPif1kPMyU6eAVGL3fh0P+tnMdy+MHHb7VWq8SFiZ4D7w1qm0RNovEQBjD90\nFCk/OrTOkiKuUwlBaoYjJTveVyCpwYtWWdThK8kbctO7TqBlShcqkkBtNa017NVv8s+0tAlf7xpM\nyh5RTJQISTFRvA2Fiv1bHg5k8g5utO1ygqNp0UU0KQ4UFkdT7/qM2Py6x1WtkUqC5+TQTOz2zMSq\nok4VJJPXPqfKExT6rWwFLLN/kDsgETVrCUhwGlS6l6re3gpbB+Gj/D5WMNjLqR2/WEXdgCGQPH3F\n8wrlHuP/pMg1obwrYo7WIQ0XIGNA8u8kcvMYfqSyT+0kZt7csU+dK35SL7aU70Pq4pk5iNzLQ3bW\nctR6U5wzrYF3ZGhADRm5hK5D4cSM73Qv52K5h6mktjk0GLbNMuMKLalzMMNb8TGItqbsQpbF6dj/\nurJ68vkiEm9/WvVlQ+fM1xaGcFaRQ2Y5w4NE7FPgNGuzDWn3ZCpheDr1vSiDa9pHPoJChERPqZAs\nsYcPUHvYcW2EvHPMZtKRoh4P9I3whny9YBqEn8/uuxPObXjL+nI+JN0Ai5TWLfs9DNMwh0GgbugV\njL1Kvj28wUdRCuyr9KYiouCdodWmucYzqt4LojNcZpDlTKjSeKxjr6goAsI2wrkWfeU+z61jyQp2\nSu+E14xahwgWEJxONejV0hf1g5mjFAH9hhJdkbQrKRLgHx9v8xEgi28SIJBt4tZ1Di/LXKQlznIA\nSqBDRVdhOzQsLvBMZcHDAfGW546KwVUTJLFIHUlvHsfLDFluPX6yBUrJK6KugxujmmCK6BXFiTLh\nOup5uASuVKcJq7q+VlFYIKSw7HQL0yEBkc+eiA/YaetTugrFJ6GIhfJ3AUwHKKQ/EUslmYPjlQhS\nbgh4yCvkEyVcBfX6thLbpw/VKJuvDxuHN7EO2gcdnBJlxGPAxueV82Wrb2958HLfLtUJTEaQ2d9j\nkVw3uYz7dds7FamzkxECTZgIPNIocYkB3Y/Kag7X8rIzWG2grcVj5tYvqIOuJmvp1z5y/sU4Vlx2\nwuFFMM4EE4SpteKh4pxata/UH+vrwMiwWhDCJ+V3UDbtpT4Cxo6DVzb2I9acU8cddKDy274Caydt\nV2R9KwS11XVgUx/dsYyGw9fAoIBaSon5lMMNahh9WNausMLWDpKd5+cnzm6kHjbZvIT9pw7Gqfqg\nyQiKxqx1E/T0fWQKW75jNmlbWdUmiIpBrdv+yRnY/qKvJ9mJg/khXQJhomFwxrRbm+UUn/2SvP7u\n0pqgrtWlvFzmXvQTyTjnhZBVv6bZhpniXo1LNmblVe1IsbmCoUcYKF9SFzDDg9gv8kzq/3Tkr62c\np+hHbUjuyIJLqXBKM7211GPADjTxocgiAtColPiIU2hMGX/FT5ZhkBc1+KGTRPXfFw2BbOD08T6T\ncdYognZwkX1W2QXTdO6CYQe5DwKnatL9MEBe6noFcngDa0IU3UAcpggNrSQW0ZumSMbfe9wZWuRJ\nq81YbZs/1pq9+GxQLTTy9dl1607SF8rnwd50dm1JDvzlpiyPwX4dFuwaP/hRvHN4aJF8LsyV+kzO\nEt27GeN+KbotNUYD55JSNJEBMf2KXPgtXX3iv3vzyDbXKwqM03ckJcDHq/HRnVEgPvU1hOccYeJe\nfvJ3vZS3WeNEi7t8GnhgRU19yNETV93OVcf/Mh3jUSv0ZFvcWwQBhKdYMhap8Lri1DQpo3bYM5IL\nHH4gqRcyhJl7J+W+oh1dwXE05qGvpc3lIKEIvf8qevRiI+BCAeKFr7sJxXvNw/la29Z3nfAsxNEz\n0eyEzjn5PALdBmEkoLyXD7VYbhUzsud83jtvlt39vrJUj9vfp+Hq3ROL83UDBPEbxyvhu/Dudpre\nNZAOchDGjG5szCRaKVzmvT+wr8crT7RLFCk3vDVKfWvLg4Wqrf2Rg83FWAYw4OeWJZg0HBEwbmfO\n35V9/EW7q7OWc74dvuFs7CtVpUq9pxgiK9rDf/7n6KVJVsGb6LAgQvCMElmwFVi7+wUEy/beD0Bt\nDifw528QdmEgE7RblFSZnfo0o5fj0P1ntPXLYl3WR+bPTcZHVwu0fe1f4kftyhC/3nKyWzjgJYFl\nlLB5u2U6I9MACV+F/zGZxyKtBVxL2ZWekQlaE2v4FxVbXNek8OD51p14A0rObOiik8Qp+KKlBn1h\nUlV5n85BMrnu7PydiUJ9zaDvTz7qIDsvp3czSzVrAipNVI0lc8xfj4FaWitCvg2LqECJ814PPX5w\nRKMs2By976iQEXXLjua/U9Wntw7oMdSzpTlX2AdVJxY2XBsaPpMTx5FSf4joK4vBJSmrRAVUl6ga\nnQAiLDMTuWewnpSlygd24kIc44v75tNtJZq1XVuZoPybWYgIN2ThUg/MFNT3PvUIBahXxTiQ+HPR\nRydC2aU5EyTPEfuP5aNcOtuqIgpKt14EtUtg0pwH71nrz9MB2kajiwyW5FFq5dqUIOTDIh8+hvs9\n+MdLbw+QuPogVe7MQ2i5fNJyshquaX3qcF3V6hIKOmU0RZXjCLYYFitVphWAxX3KppcYJxLbWXUX\nzrO2kklBS4tusze6JB/LGFUzxrcwEoAtVZxHSYavgeNioo9eBBIFBrukyCD3Q+I+Ftf1WjD5xQFs\nsNLeT1PkhrpIWf4m0YFdWzFJv0ndRXchl45veMBtSQLy/k+3XqCYXhQnoWsXSZj90XoOJxGV2YjJ\n0xYobz77eQfXeym3Bgn68b6ltpIMrztdv4TeQJAwV6oEmcWt+PGbDZqKMP7yVuqCr81GXbURyKkw\nQqvI1f7JQNcRw9X4/7sTKDkGjlfLIIo6ikX8Nicz07guwVd2wqW9lFiPbZgsER+6AoXo6Us4rOHS\nqiYCE5aZf83OGEbNaY08w+yrubUmMsQHH4HvOhqBoe00dCHgNVTq83JEjjVRP0x/UqF3kRJUgGrX\nNAH3bwtfqJq60TAaQoxjw/ftidzUZuT3ecULABRZOAuQcfe7Ercksble+GXciWUD/qn199rHSuzC\nT1ughi2Dr1o4FNRT65Jo/I+VnwvkjTo1287FtC02sPzkWRRuYarJU6dFVePnJ/C8Pfw64WP+riwC\nHZ9MeO6pbJ9RiC4Pf9i4FvExQaqcdRFjgbvKbUnulmky+0Uh+cwpxTpUSWdQ66C2w/dXLO13MdCC\n8I3lp4peZBKDAyakEuWKPnCcmhCFOnEaLE/MyYykrLgO6anIXif/a5oJC4JT96Y50h0+ZIz0Y8/r\nEgOw2b2j+Y6T2lXDWh9lihpNTzcIevdzKmlk6NeTkUMa03eJh4kruBKc027dLblQJcl3/mvJ2L/i\nj6Twk+A69E9/5lXjXCTGdoFy2OgVbddnG2LzZVUpV5cGETfPhvvbYBe7Lvo3b2aXeUjk26/w1oQr\nUV7kthuMHcp2zCLrRMvGf2uT2Chk9fsBIgd8Fgb/F9/LvQd7iI8s6a0y7EBpL5Gvm8vXIbQ/Z1q3\nFSa36ZLSzyqGJ28AeA/yyTMGnFLvWRkHNkwA0Jz42vWsYJb0JlW957XXtL9jwKDKDEoRyTMXbrEe\nXJKWEpJgsf3dXWWt0dkHQGTrbBLqHGbr0X1ZSzjjmIDl08zpoZHSm48aCaprS3qEZMS2ynuQu7O+\nVIdySxU5HyGCNiPJClpAsF9iuJXaEElz0f++Tt2kPaocR2Q8sgFUaSuelTfZavocEq/nHkA2Otwl\n5cUb8JmKIQAh8+Qdb3olrMwWAeAOhDxoW5eQBcQR2TVSdxyMDS8hjipBTxj93oXatSws5JpMLyBd\n4Fzf438cxo0mpTgAnrEyNQWJ8q0MIJaBdSXsbawvDdEzbeyD0geUgYmIbGAbV5gBuxgINbHuY4MV\nwVdNq/KztKtz5QlXRnJ4Nmdn7ieUlfwV1PVaj5AUdpAzTMxzIVnWhhPEky8OkzRVypsCEdXoLLHd\nr5rtbasUIXhBFSckM1l7E0SmSbLzZdVZk3VbarcKVgZETPsxJbNwUbJN0QlPOn3CbDKzJ7hvB80l\nvvSDuPYi3mQSrPN+uxOwltzyGZdtSr3v9b5sWXU64+poAtaboXO+u51YQ/roRd/NW+1f0pc3np+2\n8et2NNpKOEuFKRvVWMRK9mHBFD7HCNU1o2XlqjydtXnywFenZMFdPrCGIq/SoQ8cekArpYiv+V3o\nI/9wM+dtoly6cByBCP4i4fsZTx4oMXZZsEztpyt3PKUG4ngOmFhhHe12BqL3wOk0g++qHCnXQz/L\n+7xFTxFAGxTl6yXk8V0R8WOXmOQQT9Wj/Kn/1GmidS+XTimlfWZ6ixmAIoWDqxm6wjzjaUThu0C8\nH8IdCa0oq8MttkLW5KRTskFiT+DDyzNrho4HKuIl/nPpLFtvTrx3pSh+ePspuw8VvhyuzIbpGfjC\ntPDQntQlrfEUzb7iRn59kGXaQtz27DT97I/184EdWaheAnl2yfJpIdsxl+i11gesA+JOHCAf12Ug\nzCbQOsTwGEPI4CLSiBCRXPoHGfI0i3bna6pFCD/6j4PbQnYA09b6tj+pU0R+2436RzytfFadKt7O\nT6S/hp2F+eZReWUuPL5YPhQ4C+3w+j+IxM67vE+bO49uxYy6ZMKhqX3SnwQ4HnjwN8hVT74OWKmx\no4PxzKfTSdTlU6UbuBl3J7x1yfjjes/EyByPeedwoWOzcgX2M/y9LukQ1UswpUFJU3yj1HTIweME\nFPMTFjMICEsw6TMYjDP4BsNsIYtllSbEy39rKmCCGA8c//bT61L6nDUR+5GrX/rDXTaeH3bbZ3ml\np/NbD1wyNn8xawF8V5R94JRpYck+ihs+GiN/bNxLHzdwS7ZRYVE+R+5yYuoElUJw78dUIRkDGwFF\nnLWTqb9L8LORkNkciGzcMKZw7G5NhW0ln81GPiW/0XhoWUFuaCBhSiIb8q2UeZZMa5AVdfQSQ8nR\nWb/3c6A9a8YCuFhCDYN7/HX0VswtzYjDaWFnxYJyi5B8DPAJvHEA/ZjPdwXVIFJUpKBveZzVWYeZ\nsz4vK9wlfXtrBOdTmzTOWyaUUBJu6Tyy5Rnn8jB8FbQuoP6kxgMHPke/He2NofroF4bfljykkWRX\n3tPkrnkJG18O1LjzIBD5zV1HFBPJeXnphwly7YLBHGFZHi3Ni+n2NhOCstvjD5FMn64Bkb5+1yI5\nvvdMyxUfCBjWde+pC0nG1o0QEXZVf8Qc1kTh+G82H7p/j//HmnRZfC+I3D4V7ZrLA23EBQPeRBDz\nzon9KJALkETrdlhaN1XJnjAUP3ZQXiN704/QsCLmxIVw5C9hO9ntMcw9TAUfzo8TY+Pu5ZhvQvNg\nzT0Aw01AgbUgWjr2d0rbukanhWZl7progCtkNGSZhEQqlToQsP3kV3p34Rn1/qMc3LGH5HMZiYkz\ng6bxKb2JQva4quLVYMyt/VmF8TppxOIWTj7xaVrNtf57Cmg/vna2/GnRuyBibQYr598acO74PzaZ\nH1DG748uSflp+EEvlPp7mtSDdAIhqib/3guCntZS3lCXmsBFMNbUpeq1u/97xJkLveDtWjr0KRvL\ni8p+SFMGldUs4Ap0TDmx2iz5uRWAJOhgCmCmg/b4cXcXnJs2cXh07ChEGuxj7I0QWgSlSYTIkRVb\ndvFI+lB9cBepAwdRgYQ8lsJsE2V/lr/CTmCe7P/93qAaLqG3IHx1KdyvVl3NX56YuRcgLADp3jgP\nTQP4DJn38LCfKjpspTBbYvTWnVJUlcUZ6uOextoZRvb9BDZ0Ufn7eG8aOLU+tE4tUTRuMx1jqjnO\nZUMvSHANpmBPTgTIAxKnnZvKPM9/ZfJrqNB0hbgd+86oRQ13hblkl2A7IwkaB9BGUS6G7oe4gquv\nM/Qz1wNVfNFEXvsP95PQIf7ckTYQG4tY4AhJbucnCQWbE6YNo6Ggp3XnUV14UpXtNIeyyC1WIrlE\nN/cgc9Ee96uLJWZfTxCHiRWQZqK7Z7eL0HMsPuIp0rMqVT9KUpATGC+ng1qPb/jZ7AY5ZFQ/M+n6\nX0wsSK1LI3UeXgN24x41tkvnQzy8+SLNJSojBYZkU+wS3u5jkzEgi8qVKXPydMhwm8oEL02uMVkq\nUTiNoBdiN22jh37QjCLXY7bL6XtEX7bUX3rE1iDLABT6csaVk8Th51QyMf9CEIQmZk15ppGIn1Hm\n0wK7JR7HRlD2iH9lbz7djzrxRQh15ZAz/ozoepIJ73ez6W8jfObAFS1Syo/wzZx9HNaqt8H/UpJY\nt3ajVOP3z+ml15s0Qolmlz0OQzAIAf2T+z/QONjb1ywg+972zOgiEMk0Bzp2ZepNFZd3anzVuUU+\n14iE7fcNex6INsWiQiShscPlDiz0gFgNoE1avWUBAKGM8XTGnPlGI6vJEHJvsLURnZ+B8SqcMjxy\nzh+7K8sG7BYvjVqZnlKU7DeoBPXbg8TXqCC/LnUvecrmGv7SNkQ/A7PIgEfO2irm25vUFLOf49e2\nza8hc7qq8M7BslfomMnTbEit1+095a06BP0Z4nPA6eXzhmSkATxC1CkfgkGBa1PoAZVgyc6Kmk+s\npgZ4GDZiyHJspjJ7nVRvklRLM5MgrgAV2yzG0UWJJeAweLYeNBUoSRj9Pqf9e4nIdRwAzz0SnBee\nDyn+R6Umu7l/3cwz+H54r46j9MvdCCysX26elPNNduIRxvM/6b5XX5PzPNUw299WAXCV/IX+pOvu\nqoKwM2UNAow8KgXY6PhZBKNaDi8UPwd5qG879athtSAsXa80D54y1kpUsha9c+YaCtsKWZRaNE8B\nM8boYBKv2WvSvy0uh5lqVqmcJCTofSS+wG+82UZ0LYD96kyFES+lp5SI7/crTZsrHXLkR4k/2PCA\naejciKUqNLtTPOkzdzzgVNhoYbnhPvLLkpw92JWx/fcjqxTnDV8kkEwKEB3Yi4DBFxcQOQyebj1i\nT04TFgiUBbtDberJcIki+30/Ne1Rx5dKSrzKgLGh8g5hx6wXgEi8k0NtvXfmJrpWqSSTerNt/p0s\nFMWUm1QteIGSQuuXuJQxeDxurgpQV+cFEdHrUMz22hQDXYpP5QV0DJ7UmqGeA0ISeYkv3wXeFh6N\nmhaKBwiWIu7BogU5BeGE+QX2UbPyVDEJJLHe0HEadhGksfAv8AxgfYuDEsK1j9pKCXmClsM5JEEC\nmadWd1esyTDXHmV13PSgMe99ZwrXYpNcMlx86MROCXvGA0a5H1kynvNoP3SQx53IXovJE4ZyZpVh\npc2fqhypa3w2nhwEpLsB7PwsMsijqjL0H68qu98X0mbz8f71eHeDHXtZjmS8BRlToidp5wGU+WYu\nKNJPsdyc+g5pG5gA16eLyuoXcull3aqxhi7eYUarq9pKSmQkVcteW08jStXaYu/ja0WIuxhPFBSc\nKaYPeOL+nKuUYgAOyyneub+RXcIgyl2mSLOFXnVrAur3MG9bmqgVSqhibPDQX0s7fUa8aF2/jzBb\n28vnt8cJwsKKBlGViK6XnJ/DUITd/cVEThJOZyN9Yi3zi5ob0Hei5pJnwluYiAc3koSvkN17wiE2\n/U7gFZaAWy7cPfWgPw9zllAtnEZCTotg7uGuu24qsTEOexsRU1sntBsIgq6a0ZnERUpXAsaKLQEV\nTIVwlZoMXhAqojtJk0bOWVz3fTv+FOqmkHk20wrE8Pb7c+C+KXv01AIejP1lsYnjtx8QbeuArfVL\nwrU5vO7sEnKPPc7jLcUwM7I/f/2DEoMFMNxAVMvyv4DH+VTyo0qLSUMNsy0B06vIPy1fmbXqkxoS\nZEP1krcsr1JmMXKnS/XHkbq5gOXbFXHV70tcJ3YAcplfKToQiuoiKxbdIL11jWs1p1mvm9UX8bu+\nANtwfczchM8GXJXHrKl+NOYfdSXQcfjlCtASemiw4DrTu6SqFE5SX242Eutt0uwiZv6+dO9cKDPD\nQGenXqHzKT+KxW5z2JoIfJ12ztes8bmC7HpvbahLaF9crYU6el3F0HNiyjoHatQJlyM02zfJZ2Is\n+iBY/ghGTL7YRpi6qLlABO2xzVvYwMXukXstQ+/Jg5sBa9olDPFQ1xtxGHGS8OgPPK95PPEBy76v\nIJKh+HkJEKK7yooGdlr3sdO6gdOloFZV3R2ElFlym94m6xiifD9nJSWjcTaPwLkcCdKb6DLklfQE\nlNQ4QNtKyVs9Dxy89wecxY4li7WJT+yvdXUt9C8/kUd+mI2WDcrYsLtOvul1aNTygBtgd1REVsh8\nPIUG/IswP5Q3YFSx/kXm7frkWCZlH5wcPtDeT5ODmKdfUueH8i/lcWvwa1a/+DgYX+O1rEVS/nnt\nDpPmLwJppJUeh8eIianlUQkYxodnOvkg18FNnn3FwK9G8ytvELOOtB17d/EDeBeGUBerx4M+674l\naKv1P26zSR0RFPIFqJZMccPgPDuV3x0/A8Xmy4oi6skvd+x/N4ky+Fx9xnYYD32ws/SoWFvoD23O\nn2T8HRDHLhsALH7Cq4QLx0BP31QYjIr/C9PF+xQ7j4FqqPnNnZiimf6wY4JxQNJMKRTkiA2fVgFH\niZv6n4DAZhSD8L8eUu031kX6f03eIUFFsB/+TnXSXLkMutg/liy4S9M2FmXD6CJsI5SvekFSNdWU\n3bgNOWVWtr8UNyaGC5UIQj+rQ8HHHLav13wnP3c+u7dOty43VJoe2yuhUGcHupcz39IjW4ssg+yJ\np7JyWXJTGWrwBPDo/bKIwHpSfhZ6hwirjC0JdJRKk9YVZs2ZNWsh2ZWezFCgPDQLq7qOsm8uRiXn\nuzX1c7xYnaNA2xlcPK0zVHOEqp+GD0OVvlL3XwMglb8USXrKIzoeu1m1Z9fc5TTEEJKqqzOMl2m8\nUF26EOz0LL+CoC3DfJ+4rzGTYdcMT8Xx2EDc7+ayBk6WUygS97Q7rtCX7RSZgqE9ucAU7q2vqACx\nnFCNHrb2Zt0igLShqdYyt+1P7VjGFeo4OiUP4xyvcxR8xmwG9VuTRyuZYetNwD2m5TWAtpBy7Y99\n4d/Ip01u9csh7qVzoKOyUmUNINFgRt7GXf4FNhNWeDCZK3MPgp9ruvbJ+878aXyxRLYBJCUs6/pT\n0n5y9JB28lXWigfr5NsaRA0c4n+XYSIOKJT7NLC9BwT2wFv38SmwY/+ePYCdOXk107GKBxTzHE23\nIHCOZY0yEqxeKOk1I3lxaIzqHUqtBxJ5hyDqm4W7mmn3NBLBvxwmuiZQYPUxondua2L2znpldJ+u\nJD1cl6AI7GEDATL78MgCiMP1Tz+frfuQA1FW6ihoUQwAsgA+WK0hh46RLXwQx7zo7MeMOfZqNZCd\naHzaNz8uXa/GuobIHwyh8SCLqAQ7z4DuyWT5HA8w5SZnwcTOG/1CaVxAeDHm5x0ZuQ3ac96XCAzA\nnVd8gJ1GOeqhmakBUwylKzdR/s7V9gL1m7FRqJs3mQ+qDxv2mRwggdO3CeJO+MrZkoQLacJSS2T6\nMXwpUHXvfjuR1+rI9qVDt6VBSIRTxzuCN3Yx8oi8KdOjEG5LQw+5sR+z4C5C+ygMAleKXBzUyHzf\nEZTFkik53SDlx3wktcEv+s0BjQTxdd5WKf/LdToT5c3/HVkUIil87drTGVyINIGnY3yvY0Pymnp4\nGVS2ZMgWZa+jjJVpOdR4cyPZSW/lC5RgTE/tgBFkHSRzG4wL3j61/YFgxTAnN6Sabnsaj4UegQ+c\n/6YvACclRdTYoyIpOhSdW1sUO2HGbBAJYPhjtL8HVRv/BbjdzxnZIoq+73Fviw7BAqBfHjT5FEDg\nss0yUlUvrJr/ARIRLvh2cy7dXI4iTWpVfQJOnAX3Ma4wQhr32dbaycAobfYUPt99W3jj/+ulm7pl\nv2LSJ5GRTWV4FXM8PS1gMWkR+PuNFJEl1meSFUXj8YE3QGo8J+ZdS6ZPfXBjFyaX0og909uMFv5Y\nSxAWsLbImUxcy8qN12JUrO4Xt7BFH57cTfvqL9EeyyyoJ7RcHY2AIl2I6mYLmVUA2mCOfZE1kWS6\nfxTYX2C1oHZfy9A1WpZyp0OKhrIKT4Z+QtupnnZ+L5KWdZc3vLsmyUZbPilp6eb/lDNBBy3rsRQm\nVmfc1Qxd27tSjG5NvZKcRQUqijx1Tub/aa82asR+cqM+8ksV0LQ+HAi+m1ATZpMVvU3WOhiOTVbX\n3K1aFwHErtbMEQZJc8sf5pgCGfYJ40xhum+FTxZHWYdCNajj0xiv+Na+s1Iw2IfNg1nGWTZHw5IO\nymhadsdLTX0MYPdjEjNSxmQRRM4S1ivs/Na3BUMOf4Zemo2jgkWOhWNHtL4nNU9yPNaMcp7F/hzl\n8XVg556HMrefgW94Ghq10vJmhDxQ+BnEjLCLydNE3YPcO+XC6sk6Yli8F/LVeRa7RFm5aU8zQDwa\neIGdy7iKYTAZjnS8Eevuy4/G43F5WZL8LDMkt2Z368//1dAc/8fKsLwEWpjebWvC9okA6kkTr5Cv\nLsOnb/JzW/ZfdeeayvEd3LofgoXxSnn2ssFrSK6XL2xVxnsf1uiO09cJeU2POA0mJAREg/WgJkb8\nYa8DbBIkeiaQacWkn2eb5uJ8RBTvPV9PcF4ni4xjznIik+p6nUZF0Nk/sDUmPcW/G/fLegCfxojx\nXc7VLOpocKnashCXjTHsx6/EBNls9gCiYTCL8Cmt+L5u1Oa8OEiEvhTnk5M8bZ2U0/wmhcO9kOwu\nBMI5EcNxmkS0RyO6D+q9KoZ1ZUaYpq/W5uhfQO1TKZI3cXD2HCFktVWi2agenHbIlFD0FqS1wGh3\nV/4mEX8rSkjMVKvl5aifD6iViF+53H+9hbFRJXM0VP8gJyR1LUBjvbw5H51dq3Zln+h42MB64eRX\neDffD5ZvhoeXu9OBgGRcPVNAFi7zyTMDacVl9PcdW75UHSrrwnjlGzWWM4WM9TVlhov6ZPpubqxj\n02zVM8AXMrRiPLeWsNsR8ATpWoueKDeX5rSxLMyV4ugQW1X/iJTdTrNNmXMKqK13jimWaut0Ondf\nmYySqyW9gAw250wtiRKBpyWTZihsa2b0lViMoMXEjWCJbIxg8DbHiyYMCtxs3r45TdvE+bqcvFyh\n9/s2JST9ogCyl8kHA4A4RLLIclwhSUxw8Yib9TGEHCDdcuGXnw/fkgnZoHOOuLdtjnHpKuJUM+6l\nx+8DdIk72Vfi4zlUfDh6z/wzaPCSoZYnq1kS86J89l8pyQtD2Tkyyd80bd2j40U5w05Gy3ud+TKN\n+tiHrSck98ZkEljZoGKtt1J52RtLT/J2/ejhGHhmIM2BJ5yinXLUVOJgvgmKIPEOKDznYnbT0hKD\nyV5s6YrYfeoC7kY36EHy7EJ97d2dUU9FNeOWKfOvErs3ztQRygwZOm6POQ2VH9dFLr1apSpDTXON\nw+O2MoELp51bwRQRAN0TtvRGhP8p/HTnE/m00uujf66tUAPLI+CBwQn3W7KU8CriBtUhRREelZbS\nHHLF2DBFDBt/Mg+X9Mpkwv+RZZdalYMRb0QexWs7KAZi1tVF5BhS2UqtQ7/otJBd3+0uXPNrhilZ\nLsPiJjyZiKcAPEhym2PVmoEKeXpq/L+5Qbtp1EzZ8IuRITE1zZGRycOZ0fKzm15zp7NqHGNbyU36\nj0VBbM3FmCDytPYm+GVqhWePhc0NmtI1mXyW1tqEu6RZxq3kr++BSAVby6cb2NjrbJDfaYj33CCA\nP5t+JmO6K8ZSNuycUpFeH2nKtaZSK0O3T1c5WqTqBvO7NuCS0iesB+ExQuqzB9FkNQaFYpC5DfGc\ntnXqCoIByGX90KyT5WP1+KQjqFI+eFWA3YGpftZ9Z38cox0U7/bXAdma6YJOLqpyXxIsNRHUVQBf\nMkwK18KWy2Nb0f/XjvJiy5VARnHamb5vxTfN9mG3iDNIfRVwRe8z1jwtZ9tg1zBe+9XpZ4ooGIBz\nqRDfo8Gy9pofiRhi9DXJ5iRqj2Vzfns9Kxqwd93nogUum3OkHpU8LD3snP7sag7PLcPPW0gqCI8Y\nEF1uOKbVhsoOzYQ4+VYZ2kZJam1FtQ9Vc5bP+uDcAE/1UAS99zMJbB9T8/2avlgOUyhtRiI4EOix\n1/XvR/nqPEPjbSdu8qmadV6uzjApBpoh7BlXoL9dNoINLNspC7avciPuHtDPHkqI8c6HhDM+2dHT\n1ERyxDg8KNwfgS0mrnD+hILuDycrXt3L1+aeq3XcP1avt5VfgUK5CMZ8He3T9ImbF3RGPJtaCbYI\naJTIzwMCHRUGvVe6tBk4BvVg1jByri0jTJdOBe8GA9GR48ye8y6bc5UBvmYXlPnFI/bKHSwTTXy7\n8eDStaWBczgoleVHjIbGKF+S1BrxhlwmLJ4ga04szAMXo+A63ZHVSgUcyFklDMuQVcCvlBh882YU\niO6r+q0PvnLKQRcjCsEafbMucAOh7UwBdNc1pApTcUIlDf6XRCJYjq28h/wgMOCe1TNwm+OmMkAR\nXKllXtAvNufng44tkegp4jXaNW7h7pOXejPtTFJOEXGMDEQFMJIIufgJM1xnDYa7v5WqO2YQg1D7\n4Rk9qjpEX93CJ82kIeqC6Kp6QYC2Em7paZg3OJtHL733F5doyyaKsHR4pjUU/2LzeHcm8v32M9nS\nNYQPuasco81lH6PATQl2ks7vsDnwVB8XDUv/8oUWE/plEFjiOG9iqOMSDqIEzr0YtA3QaILJ0vIa\nTb2iZnnJNzz8DYpuZMfSVXWHEmUMyxx/nBOoCks1BGbEKU1uWn/L5vb+kKEVTmaB8Pl+IxXFH3s0\nzPqxEyLlKD/HbXjTZvY7sB5nR7i3Au6eIvNBla5KgZLmE1fq/aSExjxzphSF/FkI9BYSyT347D3G\nA5L2FLfONhmwm6+nNf7cC0STCHMY8PLiFJ5S+HNIvld5Q6taIYE/FsszyoHmdErK1YCzz1oP+dQx\nE4iewyd1ycaBcCgHZxeJTLxLzrVF5ITuxizh5qBw+JWVHESjd+zNM5CfYzzPLhsTeXeqcBH5Oy5q\nxrjJedz9HaizUsnNQbtLLjyRDe/1ztVNjlZEjNxjT3QxZFl4lS76jM3OgRzMW5itz9mSarfdrMbD\nP3I/yThsRQXmBoeO5YVOYmnbuzm+4ewJqr5z9nxi6pjOJs4+BbZuiqDI3iHnOGoO8LrLvT0ja5FS\npUvph4m18bZc1abISgEQu7EL56Dpm55GGtJD4etmY3xFeoOFjNeOyRlQA6ioOUabNbr/PTzgkL3q\neT2TTCSHCCMtBY+ce4J6yVr211KaU2JOo2Wi1pUZq7dGg0ByhvWVjnitbBvrOWhLG/y+BWOParLe\nir/7VI2u0KTVvkTtub+fSSahNEyyZDDy3GyGkUhwxgDbSjBiEuPXNgXIKLkiaW6sVdi4jv1/piZb\ndlRk0Ne1wgZADzDBj4o6FB4+Nx0OcZqLlEM1O+456AtrWKT4SESLxglOtT4x7vSW35djc2e5fbiy\n7e0VlL4So9lBHyu8yWZP9EbODhimF6EAnc1Q4+ZXJy0e8kU/P0VPyOq/iuexUprb/uZFGnu0SPlC\naFrIXCqX8/kl5liKPMlYh8iJkL4seK11BWPai8o2ngT312QhbUgVgb6ore+/exZzqF515/0scd2E\ns4VYrRGAbCDGJw1hzjT79LrGmI2z1u3/UC2xWeeTVQlLuvU34QlbsfSybwCTPl8zwQfQvv4SXJcr\nSYsFktANhMd8f38c6+M54dUwEvQMX6o32L0DBZppWyG5txbAAipioNEcwPQ6QWfMvtxgWN1EJjMP\nmuH0O/t/XtGHWingHs6ir8Sox5MvcaNHfAr8/OpT4xKmFc1EKXcW1kifZVkZTMvkRa+qkFqGzSoa\nfDfdmKqasWc7BJjidnMFgoAyTXCZ9zgpTgGz4KTMZpsUYPuPAoC++bShrwWQIuiWhADIOyMUqD6q\nqCNSRlGNkJTJLUcNLuxaOJntluR6urOi7VDpkNkTZWtf6GLif4lslwpVpw5hRYhO/PN0I+21Adyg\n9JLfGff7bT8jdRtlIwijD/Fn1UW64G83M5vdN/uB05VildRiBELI+s4dgrkzlbmO7PxbsoCqfGW9\nU34ah3u1PWN0tYqlUtG/AoLCwQmHgnq77ZLbQYYJpAcm7kWJX9rQicGRRAj4Wsg0BCRFP19fhvbZ\n+vSQuOKh2bSD23jZwhTA+V6XdgPV9I/Q01jm2CHnCWYZSUUT2sKwoQDdEUqaeKrix79e9vO8i2rg\ndewRNi7+SMoOGgwtFA2DA2Au2gpBGh+/HCuoAiG+N1Drpdpkkvdi4NvwELZGIS2Q4GMALra4zQY+\na3FZ+Z7yWVNLt+iWtjVK5pD5RZBzvdFna52rtWQs7O4jHVZxv4pHforHPTQjpub5lqdqmJxgHovk\n8TDCaYq9dyMsxr2I52CpKKc2+bSWHOXbwESDwtNYRPb1C7zhLa86/oXnglZuABLJ/jPMl4MrbDGY\nz+JGcGLGHhw8JchxzuAy20if6Cp6/k7FhXdYAC062tKNtcalOJYxQRdM3vfRVFH6iFR3YYgr1WPP\ng1Pvnq8aLRAP28ISslj/Q6bAlU4GYl0RZGHG2s6THjOMKFIArwuDZFa/+AaffNb/hxP3Ty88vWGK\n3Xa0wfu/xUzTuUrREPH/NhqlXbkD6CZ0IuUq/L2EOdGcLeRlCQDjTXu5dgxsaUaJ2fX4PUp375Q8\nDFmPws1P+w1AqtvlWu0NtGZW3aH4Y3byzcfnhK5GkSPUnmke6C77YbtKiP1EBfMmBMu7iY5iTq8v\njy+QByWCYdhFUGTiN9T35eNSj/XNIf2kHiJmQc2pt3zwLhVzWi82H2+1zMmU/sdJNE1Jahupnd/b\nsoJB1fSJGx7cshIEmQ2OgqE36zoV6ubU5imaD6vWpTAKzGQ8tg/TYsMG6Z6RAD1vJfd3B+0fgq5C\n3oboQG9YTb0GIEHSHflrhq8onVKDlkR5moX1W3NlBlc7a/dTcgp1oe5RWVY5gh1G7H2UxYL0FZdw\nURruaSlgOZETwaJRx/+JyZX9Aw+B7SvDUdMYQYmP/wmx7nFXA9wvPPdohXgsM7FOJkIKZg0ZVqbz\n+hc5ZfseInjvFkTALyOK/Xr/QHn6W8w+4u3vI/ON5mZTnP6X0FpUp4ziopXhBIBmlUmW9OBqstzJ\ny7l4khEG7tLkdcjcCHCeGxXaIuBptl9bT9SL/tR79SgnbLItuaWItIQy0efvhGnsvQgOxqLDPqFN\n5MshhLylB37dmmfkRntZNJy2l80nnDbAcmCL3shtD8HIEO9LySIyYIkzHQNIdOZ54SvD1K3G1Ei5\nf720yCqNFfiz/yDFkBuGwKJpPY+70rDys7VJ76DifHFy9Bgh+jAnQEL9laONUh47g8416OljmApo\nQvr12S8DvFLoYMbqCj4N7GH1+vAjf4CFcSgk7bfTXE+5U7vSZeTuTSryfdBUkbbVzkq8gQBswQOC\nMvZgXSGeWWNRjgmuBUN6nd0wC9Cpt9j7y8r0WqCe2MP6I8+Li693+ldc8cPeiEVPyFCgKwc11UrV\nkAgIr/8vhgQD7FZNNO55E5NJ0yWem3oCAd3rnteamBl4MPZZKyBEnKSTjflagSbZDpIAnMVClr+w\nREhsNzNJ1UftaFGTynO8CDqZTc6yFG6Vx4KwNkvw5WaLPScrwj+SEZYS2LRFHn3l+ho9d0fofY3+\nzXEre/e5l+nk1HTNUfIQ40tDzCdVi9/5qhKBFPj6s2uTq8IcvjWWAREolAW4oY2qVo9JCzC+P5ig\nnZ1Pc7nZyPOPfHvmQWLQFegpV1PgvYXnYFqkAW6aponv0cyK3asbXB5qSnSmqforoDo/Ko1WtbiI\nyBvMvM+4YS6hTu/Pkzt5wOw0hJzuD6WYe9XpxER/PrOKiBmG14LUYooCerRe3aF082TzvGAL+QpQ\ngTsqOQhB5SYex+70IcLISO0EPWNTqbY/HLM/Ogotmv3Wf9/Y1cq/huOAB+VNUiGGxzccHOtHnqh+\nDxqE5qudZTYZk3KOCJn12A9kY/7iNsd0FGYQbNw/Yb17BkxiQxHA8czLgcvX+JW7c8fGa7FKK/zn\nhCqZBs70Nj/q5lgKxPhcOVdihlGhajJtM7MscVmlWJCg60YWIdb9UM2risFylFoZ3ROQKOvL3zal\nR4I4o9AFc+9FXffmvK43aBBYxF//f1Vdd0pYUVGhB0gbFO8EhGaMUPR+CyhqYpAh3A0QkyEwISuv\nNGtGAl4jJRt0AiOOKamkreYqY7fAVX4svGuwSf0Ecyq2QdNOmVRGn67RiN45Iaqg9QJ5YkyKqC37\naVOdvYR76lV1lPD7UMrFDZgdZr9ge3EMjcyNm8W5pefzXkhYl8iT+3qyigKs51zYz3HyPrJJSxQG\nBWIDGoN283P9HgV8+MatnlWplGJn7GZd8X4N2KovgGEshojwu5whw+IMNO6uaD5sqgEOokueu46t\nsAmfbFlEFxiL4I9sMljy7TbhFYpQoOociVJDgS9mrFsYWp0O/SWmXVpG295CtBTCrgCyMaUTrRnP\n+wQh7NSeXwJloSDOLh8Q9GZL69ppHeHuuEKrMJnnQOcnt4AvQ9fbz2PRFOaB11VSj9y3iXKIq14K\nfexMNNxdsbYiGzs+P4KRivPfNZGK1g9XvdPRkCZ+7W3NrxGJJL6yIMDL1iIigCNtSEKhN2c0G76p\nEkLfLGBVPFEmdyc7GKWUo9h6m5pt2baTgpvCSjGTKgLJeHNe6TLlkinaqOEGXVbj7NS/9c5gTVN4\nrTC2tD4RrKGaGYBwP1LeQBcluo+nzqjIXbcneHFo60ateVSNgXbzOjZVHqE9j0QuGfpYz2gp/PQg\nDhMXH6F+wNU6u2MPr2NGBNw23W7xpcZ62B9hO3e02tw4E8mVN9IndBRRkHym1z+0DPf6apuIZJ8l\nK4xA10Ltr1ClHu90MhQeJ1zzUkgfIaDHEetAMJLv5/Zvc+9Uw19i8WUmYZjpQe1lUGgm52sJEtGW\nLF4+iMCIHNXGCraRsoKpsOznekSdeMXhq9VOrGwB9LIDrnVlHluexR/orCadc2teRTRvXb/yBt/5\nwCbOEa6/dY/J7+3vIPcgFyKWK+1jx4Bg5tCMAop/v1C4I36wRiNRKH3fKlXUJ6exyySNfCeSM2mh\n1zWAftW02p/kRfJT3SnOcRz6/3H5c51vCtEMWmsa2XY/SjkIjPjT/145x8nAEopaeWOl0VJcDld5\nHXQxbaBOkXDexPUvg32GJkVGb2TZMwTuTu0U2hOBdRJ0SQW1epSCWqNSgtOfF7nTZk3M6dJUnxNv\npA2uWRGbhJj9IrvkOSkXHEsuhMCIsqiE2OtIl3SjnufZAfVk5giK/WoUzdgncNzStW7u32IG6CR0\nYEIMhekU8zzMHtqgOvfVMf4+MgUPWEkOY2eV6j5HwyRqfXLJLhRUbp6jKhmPeXMkUkVM+yYtXAO0\nEsUQxfeDHFckadq12faJMHFtNoR9VC9hIApFMML4fYEHkTs1DM4LAA4z3/uViEa9FPd+AmerQ/kb\nNJhjSSDdbYL24PbprdDxqPz/6PSkqqv48nSflBQjnbBoeg32gI7a/y69RJ2WGYsoKn8yPeQwcckC\nX9a6YKXnIru8L0XcvK2vrstvm6F8jhQFj1GnvuUi4L9moqrUTu5I+cDyovrjnPpINs1j976phG6l\nVNIgAsFCAtsANUS7sUrPtjhcRUbgSxvp8G3isss6F/s7hznCgIewc3lTb01Kzj8iahWo0djb0JI+\nkxPgl1EVlfkPekeoYTLRV3z+3zhLVARNdDgBjodwtgO2XeLPq29S8wZKKv8aPwUw9wicU3Vv31b/\n4xE41s+Tef/RE+ReAwEIYdVcPXJzUim2fD5q2+SzZUxFEn3yYxsbIWbbAa9mPJPkrkGklI71xQxO\nobCDxI5BYlXqz6vclfSbjIM0UEfgHl3v+t6TkMpz7OvmY7SF1x7bjEfKCOH3u+cATB7FrsU7zbIi\nMfGXBYl1yDocixIarcVsmpZ25RyllRynUtMotBhXOWNnty5KEhRx0GXpUHqE+6eSoZqTG+ahT3m4\nk9/tDuxzc72LlBnDPMgpTROT3XXKVmCHFsADf2hR0ME6Q0WETbZEJbtsSIonZR2bbdUC3QnY2NXv\nHnyVwA3TqtCnUDHW/vnLvm/zBKIYDRvXQXo6eWhzM7T3A/KW7stsbMDwaWqkDXIfUNp+OsT8GUnI\nVCgeJ12JEcGAtiax1aG3KDsV/1/cOjOck4WwZq/wm0SiyFvkrSVHHFqyphvaD1N6jitKP95aFKCK\n2YYQhyfjrlVMvqLyz8bCSL0GOen+cvRkOtWYZSAG2x9gW02AjdgwVHvsOd0S3OgC6HGUehRUweqn\nrpLN58QUsIX6oDEkF6ger/c2C8qbXkFsOei6mGAXJqGhYKpT9CK6XWTYdyZVY4adCuOj7n5+f6Jh\nlAisGId5SLN7Sir7719DdGxelIf3/tMXaasbKl2gzZOsvL2tuVP8GcsPVDoX7dS5SyopVl2OxBZ8\nizVgNXByJzmvAtAYZAS1gMjFBGgHu1IDvncYiCHRxijDO4M6+OCH+HQQ/yAO3+wSLdD82T6GR7KW\nShdrvj3xJSsYZhFZ3qxVtrJbabY5pploAVT6XpETTUanUEQk1EFMw6md31O3TgpqP/kzqWnJ9I0a\nMCgx3x14hGo5ZPNu1ygL64ZCWuey1uni9gBnoqDBPgirZ5ejSoFpnZ3F2c95R3EoddBsuykdzfHy\nl8p7HrIi+GTB393BEV2WFiXNTlvpXhq1ghbyjGt9h9bj3WoZrf+9lztTCK/6F9+j9BjnF/PgtMzK\nOEPRRv3KvpLP9WGQ97q5zg+TE/eqfCkZASA1/B1qsqy9exFvvFGQiwk/QzmqnreJHd0DsripcPAl\nD1M+zwESnQLl4b85hMdkoW+1q3/GMLhJdNIe8IVXkpNZW4W5DoLvvo3tl58S3VANn3FYwn3WB9Ht\nnvgVdm7DPWAyWfXdVCJpKYnCq5SpIkRwv3pxdPUlfnbH5hQeyTBFkIBmDO3T7Qc8LjIYsUQbivwQ\nt3euzokVK+BMpJa97/3WMrYCSlhoJwtBLRiIXLm8wAxXqgCu9FvKQbaNV3D8VosoPHXBpeJDzRi/\nvZNP9CClGA8d5dYKnbqDS0Y0jp005RrHrd0QrtWZz5opTtgS+6CRyTcl/tHoceISfGfXO77ykLQB\nl9SYVgY8WGta04XVuRInk6Tx+U0PL4eqTP1YjRBnoGF62fdDeeNCDdpUVG9zy0cI7eMJtIb/SLVG\nfrrPVl13U5juBkxhMmblkI923n+xtwUmXXRDzTTIexRdJYJPY7ud9ETeK5DLjt/tDLXmQbmI1hjB\n9nCIlBPTSHkBMNmFdflv8paNSXtSe9VtDaB8yZQPHIMlL9QJeWeEKjhO04IVorW1wvzPa/Lk96mT\nOwDgqbRXbROApn8T+Xya/qAaHKOhyq/F6x5X42oAT1jFoLYJDFdRrgZqEtZTe7u8CLbO2P2pMfBi\nLN0iTCaoZffDxziodYmN3NwJFCZlnqKrAxyM9oEcLjGDNzFCQHwQuR9uG1GW7dGhHT9JMoufYLpC\n99M5X/9PHuX7jnYI5anhglG3YC/g/KdgX6aVLAsP7uqQ3qj6GZaQ8jMbOJJzfyUNRM6w1NAagrMJ\n7N991tesXsFHnWTZlhytU8vIExY1KwPlRS7HwGOu05XpnMrfhCRasA7Ft3tIxVpaNLwsnUVRTl/3\n44bSAkaGPS019Uq7Dqaqn3G7imQ80KqZYkNlk6fTr86TguOQqefqQDMEoW1TAVoSek/4ICTTznPE\nLMQ1SZjbQk+FYLh4QAve3qlcT4cwkayOzC3TWazqmNcAaFt0ODUcLujDztZ49EiPAPD7IR6Hi898\nP1tREWLGr4QQwVAueTez9GLsHzI+YyWU4zYKEvXVv7C312ZFdNI7rMnUS3V3LV9VEzVMWWAQLX41\n9jhObjy1bG2Z84fYf9LN/vSEbVx5/PHQL+r8SY+MA7PhrtRTgpFP//Ov374oqoVDvajCt8EOl0ZN\nRVdnf4oAFlpTltow+Nl3YEE6gaSIFpS+hcjXM9bdZpwd0PTY5gVt2gKg5Vc7s3V8I7Yd8ELMZjfe\nhEdHpfhpe8Fqn4NkG/FR9pgKAr0egqEuBnnuIybpp1gERo1VulZyKbHJqr4dDf0rpOv8EsaLKQL3\nwHXUYRZI9OSA0/+X4jtvQsxnSyuHF1ceHfAX5BWG+yLAu0dLq88x2epAK11el4HJwoPcR8IUzYdv\nP2oZVUTQNIxi68JJptNG0yFL2KFRwaIg1fT+JPbggrYRCApCDVzdJN7yEwH40njlUPVmx83b5qAQ\nv8Tzt8dt77QfesA+TmCUtOLkR14m+IHDaOKJjlLf6o9lYkkK8HYj8M+Y1uFSptaESiLOBFhD0YPA\nFAmhsklFkZ9subSValUPa9tMQE0lka2GGfRY+Ok4cupDCf8R3tvOVg5ZojaXQoBkiiecsWEAW1r6\nNCY7v5YZQ09rsEDl7fdsgIJ5dAGswyB6iZQUsqobja7mwoHxKPny/8wRE8m/z1REj+FNHCL6lnHP\nou1kpcYBABtC9+Hkrh4FdQEkyiqSnjejDFzdjUyHZ820jNrv8e/hYoeRJD/6TGfpHD2dt2tdq5Uh\npgyxG9vNWd4keam/tjCnzKekOxWgy/YNCQGw+0iKK30vqD4jwTmWU/6AWc4sKNesKN404IkISAni\nL5ckYrDGNe03UcNoKq7nf3J8jPFuIlX1asoCnYdi5Fk+ZEYkJh2eVklls67EpzoNm2U/CBx3X0cw\nrGBnRaayGk3SKSog8PAPXPlXd5vxATRmQw6JGHe9dc/GcoNbIb01D5eCFJjUXwRE1MWffv/yy3A/\ns77Fj5L4idjX4wkv2PMBJAvOmFg3V9hu1xtR7ycvdLrdda+PfFY5GWsN7dovCLCsOEiP3TS0j4G4\n4aUYzzU82ILrymYxBWLsq8/7ERdnvWKmQkWqS/rTuSsXr76Ess0FFHXNMw95cXuaK6kOyWv80tXF\nUbMzZxtIitLUgsmz0NuzBdRYoxCMI1JWQPrbefRkPgACHafJsSeQ0ui6Y/1tL4/CVEXNU1DMQHWT\nuE2aLERpW71K4Gn+70VPvUW/XHxoxlq7vACAMBv5O8+7eBe++2RT0jsGJ2ETvGrK/JnkwuIy4BEy\nhPBj3h6TIocrXvRPjEZMIfZfmwSNCg5sUFLVx8Viw33DBTEq5CCzO6CWiey+pcxvNmTT79Mcjli6\niKfi+5uT1y7Pa+JTIiqGqJjIqvy+nG6x79ls+qVeiQiSh9VPUC/xKpVT0v7umN84u58g2LvwvnjT\nXKNHjOPT0bgTxdJsDRzeKmsoOsnFdvrxqvPwukTRRpCW/QpH+0GvhW6r7l9en78PkGWRUVgPln78\nwhCiZURp1LYqzb8st+QqmomVuzP/PPKHCK87u0o9uwyl5sAZIiHmLMwRO4/bNq1A7ZIOk8ZtEt47\nwhpuHuc/GIodBf9WWdvqnJiiMFVpv1a/Q7Ugx2CjP0k8oKoTt75UYoF4zZhDydezmFUeJSaG8eNM\nJ4ztUuzowglatJ3MzDQzy9VC9JgoqeBiEL6BgWnP8vSdYuFNCtmZhK0Rhp8fGxc+ZoX9T1hUnIsY\nZJGPPON/AR3kknYsLo1xLmOzDsCXh77JKm5eOsdx0kYG2aR/1/vWyog+TyjMzIVGXDtiUsNEQRVx\nw6t703L/78gcypvYhjot6Is8U39LIAhtKQ6zMAOjyGg8dw5L+CzMtj8ydNPYn719iqe1s6PDAYRW\n6XJz3gflV1/LznhTx9OzdQHPAkpSXgWfPS3W4jN9NayqvnfWQWByv0cN19Wa7K14YQcC6jQhIL38\nQosR6oIdThCaz4I/CmVuIQFxhVrwIVdNmZM4bmdJzU1QtG+KsiOzTf1rT9dQG4VgUcm2ldWcfWnG\nBMcll0PL0ghJYlUWWU2lqcQprz/r68xDRWBlg3r3jnTXJKwXu/bUpUFK6aCOGsXnKNnvGgGetswD\nxOdll/xU1ELbyRVdZ6oZiVbiCi7d51wByB9G9Qkg8wuj9rPUtF2b4hO0H57AaTP39fMJttSicrMa\nfxFv3EmWDqz9NAPIUWKpN9JZttmLw+SwpjiMsE7Ozczm7hxe7eZxHtwCwTZsbOrmEHbj7GLF0yp8\nw+5sDdEBGLVvEUxYXOkX7hf8hyobvvTf1pbDzO9+ch0S6Kn8ljRc9WPj9rKrMIjStaX/Rj8Cu6i8\n9RvHW/ABsCyjSVw54+fiB3LUQtaDGiswnYCbbZibaPn7hyeiq+OP2JNmE9beafZGvb4foPftXrBu\nxrKQanx941JUl4+Ln9Gj3qxsys1eUe+udB/Ro+7a8x/iCkISlDIWyAgoSPaDICzgIke6MLKbVrqb\npINUJZpKBYD3EWAN0nWN1eVm7e+qdteSQ0/SF5Jmb8pjTClbQQH1kM9Ahqx/HT3hJAr5K22IQ0Yf\nVfxnVxr5gDpTzecTxqpperwIxD/qBJC6iDO3bjj7CNDWHIWxTARMT5mGyE8de6+Hc8HWwCgvl83M\nDOEAnQY4UMUsMQvw5Xr87pCOHCUkunLO0Kz3U13y8SOArTTyOB6ObQ+K6q+iKwb9KjHY/hKWtNpi\nUy5xAwnDlv2vEbfIrjOEcy1zhCUQelxksuiQg5dOyxUq5FLRXP4sPo4lLtVJThF8sVmISy8X112+\nyi4lDwZXVxZQ9teIwzrh/8tGFYTzYT4mgSGVkJ7qRdAjAja3nYuNo2tWpngZNAQj4w6f2FhY+vCE\nhocTnzpTAB629kHMsVamTON32xCdyzQzDfJgIr+Ku1qzOws8g5VQg7gaWrrK8pFFjy0TNgdBgqUz\neqHjJtfI2+tnydOpgRWHDq2PyoB5J10BvIAW24kWXML4/4vUoF+tIKEGB99rferYDgS/I/nSk/7G\nnzYOwGuc0w2Wit3e9eJ7pI4LYcNx3b2Uq5eIz5DLhBtd9JDvd0aQK/EMTZS9rxOcOP9jG9Wed80O\nREdsP5IupA2vrptwSgqaRoSHpjvrSXQ+6OQ+TLT5GZV2KJl+wPx7I55BU7BBJ6coExZRI8HHMagW\nyKYvRUwhuzaflIUf0wlLmBShlZZZIoOkdrVp4z4mrHJR4XqlFo2kkhVwOLT7TW5zR65EunX1DcYT\nTTvXxHsyvewSiG0uACmb0kJSaTGyNDGuCXvap+xPxcbBA2gKLakrW0GOuS5duEi3d6WZqYp6KYwr\nTPSIxWZcI+w4HYqe9TyILkd9ajHmHlMs+dXsAMVXhDo6507nmqbWg/d7QcANU56vbz7+Autpnv31\nhbZ+4cVq3+pOvT5g1DSaLT54i8GzDMz2AhGiMPqVfZP75joOCJ6eUJ2HpXCCcMPJ4wIj0QADgVz/\nh62UUv28v0aK7teYzWwqk0eUit6TCZXR6VGrSTguFxu4tR2s9c6eMatvdXd/8QJukq6iPxqgRCE1\nXUun4dNXqp/l5hxGXGe94RriRGIyFJ2573QXCxckAaX2FCbxG/oiuMpS76LTxWF5700DY6E/aaPV\nPzOBSP8hfAvUl3FqevWFHgxMumv6SE0/HpMs+u+of1q/pAa8Ug7D5HdjOHIt6SV7n3UgyTLmDuYD\n1rMFW7GvhYLzo7/dLcGWQss0Tn6Tv62zVWKMbRahJFCo4u+A5Ij2C7pW2zgG+Vjb9oQjZZ4BAszv\ngIeSfUY1kZbzBMFclCM1+5pTM1GqDl24UsQ1axKDCb6ZwBR3I3//9Trg0MkX+bimfMsDY/4OzONJ\nimQqCtkPObv4ZSiYNgiBasTJQfZwPBtooFEgnjKks3FojWNtVAWt1Geoz9szk/zCfL7IuX6JRf+e\nYDC2EMb13LRiVeRh9RstC+IxMbR8JTt2+waJaV9el2TSY1+IqY5dE2ps+mFBeVBJ7YNCzcpmARsu\nVYSLJzpCn+oeLEYH+sUIXAbF8WzYHBH+6JxdmlsdGIsmY7ZpzWGNXgg76sE06d1HT+07oMuNpPms\nHAmJ6Rndh1E4Ul+gc66uBOup+pKubPiMiAnPBfhPDzhkEsF92ePYdd83pBCaOWX+czjs376MUhGz\nyrcG9grpBR3aBpUT9VgNJYFBZrATDHRkERzuRjj0MoWdKpBh3SnoUtSApX/G+43Nvz9f5S2aaogM\ngZ0WxvPGkuORWFUtkP+B8zDbKk7keCmQNgTm1Mgnb0Fnjr0NJIy33+Jldv9E1DULHbuDR17+mzJO\nCjxHdkk0aBq4G+c71XOSFUgiVV8Hj1C1g0BXfQChFgvFWcW3rTQQEGoaD0Ra5hYnyetykawrht+0\nCl4ZaqyEbEiBITKNhY9FNVu+kzv3L1AKrre6Dq62S4C5A30Bper8eKvoj6ob9vlltX0Sv3+2gvo7\n4dRk7tQQUHNcNC07jWXVE3xrL5Vq9f3QkJrgjgvNxLcZX09NdDle3RoeOKbRGbIQiJUltI1+a/DO\nrAbsh+IZv5nEdZwlvnPgEHoJ7KZR4iLUQWfa1L4LJ5Wkt0NbLozuzd7qa99jjX3ax2L4Gd2mVK4p\nsISCHUeOXmrQIO8V9BTJgnFVkcwmF47KjAIaSwvRWF4x21tlmM8FfixfYxSRJcXJn8OcQfO3B5As\nfyJIb9/ee0fg44i2xw/De+Lqkj/NNo1jINJyc4HLLneQwZ5Q3Ve+BbHhaUiL5YH/QzF0uNqk70Hy\nPU7bv8SCIfMN2M+B+tZea7AKyzdOXPySDnk6IGb3aIDK1dhm1VF6xMqrsmkdUWvoPSScp96IFFiE\njGsf/JR6fq8eNI0NNWUZx4RJfulny/+ulRNLVUO0Fzx1V3DYqgC1OaPkuuNijsaGTXIcwXcqvNKO\nI68XDIfRl0BQzRREDg0mAfinoD2AUWSvSWO6ksQlf5IB9DZMD0QNNM/k1b+9Pap3hI5MnkL3KEfV\n9sSHxfGFMio5AhzbhZNltYwd6H3KmtmkKWABu7F6KZIKGBMEunSiMdleOOa5UCtyZpTNyiURg5ic\nO87fo3mBD9sdiNMIUAFJcInFTM8vuWEUXlKPlFLr4GMCsizjMqPLnSHE/5XNE9DksXkIs8PDVRTb\nF7JMPnBwiVekpNxtRNjc1eRn7c4JnPcNCExPEvrChF47o8L0pqg4VH88SKPT4o1L5CXsSNPD8lv3\nMgLvMr29JmSrq9BI0PpRdlvtwBUhH0qHHFaust1vbACDPzevH9Y6MWpzH8nIYoznircuZxFTKAqG\nUEuHHPrcbaklZBf4UWLrHOzbUBOia9XNefhLvp/POG3hvUhxkXUQztOf0QVkXHY4MbIcngYV8SQg\npeoyKG7EYyjo0VaGohyvQ+ujHm2EqwmEVa0NV+1jgV2nsfo2Mt/AO1zytGuBT6H9zgKoQ6rugbry\nqyerF00/E3Eq3yEa+HstfOR2PrA8Yn3RpDTI2ymuR3O6RJRk68/8t7AVWqt07rrt8H05GyZ8PHAX\nq+D1gZcoMISbbJK0Tz2r55u3P2KE538iLJWg3wB3EEh8LNm/EA4HROTdD10YfrLv3qgfH59B+DhJ\n7JeR2sWVXaPQLVwpNmFFyHLZJgg9mRBZ9PshV9Msks9UYBwYCFDMeBMYj/5+8sCjFT1Ve6VjpApG\nvOmTa7Lo0D1vM2en5xLZt5Tc/pOljwPAxDyVW9A7zR6z7ek0oVJGI2ZShKBr/Xr5zuXrGG3jOQfm\nw0gfU3gSHee5QVkZMNAoGqOwkQfNtLr9kIMwAK1oRtiZX/XTNGjC9zUesU4Dpme9EZ8tNCW+FuO/\nxBrzWBdDstLC6KS6CoFlpPdYif0QB5J08YLj3MCb5znq76mdjYtju+EkSVE1fm9s1eKzmvejUGgQ\nZYNKk/UVRC2SX3yYcNGKyEeFRGFfTSUyq6MtwMGZ59yhESiCNFW6q62TcO4J7mRW4suzjVn6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Sk9lBC4sR2erfDSjUi6qJZmChBzCeRawMu7wxItvx10AkNFMBF1v5ExWyVJkN1u/C1POE3pGuj\nSF9/n9Hd8/t3/iOU0ERGuRm60iFO7SlUi93/VByIlIcpMN5sTHG3HNLDcDqznxmFHVXRF9p0oyR1\ngOEcbCQgaaRfi7m0xuMrOeOy2Z6BuEvqqCwaokBfQJtdh/co7cqnl0kl15xslsbVll/nP3rIjFmf\nFXw8R7crtJdgam3o54p2CW8ChhGghKw1GWG355ZcxfdfjTXclWSzo3VGebzqGeV3nts3P6YbJXPw\naOr6jQX96NYh3by+TQEhwP7Dh3FhiNOOUexnnGVXSoQhzhN5yzOcLzgZKnmnOD5K09AmWygfggs5\nhn7Zkth80aiL9COTEsq+2aUlu091oYBqjtjmjrhE/ZkU+kZbMvYEIetC2hnkYUEB6qRVuKKLpXVE\nGKmp90JWx6CtzXPkDVN/AtgmiGohafg04cZwcH011dpib+rz9sAuQ6GxngRm/+6MRYeuuSzyPLlF\nnoINkU7FT8nX7v3YuVOHhkb+RcE//HLBmG5w2DLW3XSws+14sJB2oEPXiLCl8CFIr+fOrrHO+0T7\nTlmbX4iV/OqtP2fAs3jLgZZ2L1gu7T7GyykToN31bleGfzHbOn0mLEmau+AhLcSTZRBUl7j7jsfC\nZzCCQrw3IGgfi93EgilbXYFeqgQkZnP5exHpPqHj0D3AacsqywaeZrCYLnPY6W86TvGpfM7eUACJ\nyVy64Npj+JWxq0bSe7ia/UDKpmgXCsn717qGLpZTi4zGaJpBuN2uqCTXnWG+l/3seAf3gg9dCtsw\nTUaSZh3tmoxa9SVkeoQevcznKL0Lpdxm5xCv+pF4R6Di+ar9GwtI57fKh+zGU22jeKCS105lPaZJ\nK+B+pJcOEEGKQQr8cslTZjOcC/pYCJpAHqaJZUKd2fibBpiqHxpo5XB7JyG6+z8TvSIVkIqQ5bSa\nOYrcqgilxoLy/PU/nl+gbexAbwngBoPrXLeO//wyIjNkrxdXf+pLtiJ1YHdikjyjEk7c/yJHV74e\nN7E3Hf7oW4LSgmohyJ4ZIHQjwjtS76pZeg0JB2tOzEuPXPh6ydtH4WrJALhEQIg8clfKxdTzV90T\nQ36ykIVUFuKoGt1MLL0ZdAws2ZFfAC0E9HRAime1typb5HvdmD+KoO/LPjKHuWUatB4g88tnX5SQ\nn4hGXnCT33zMCnmfk98SU23SzHxU4XRlt7O5ZYHzgGEcHj57KpGQ2YogcdRIuFAcH3lulxbsPIv0\nNSD8wwXwHeRgX47RlUcWjsS6BO7zrmlYhkNhl7QzDqSpiDPxZSJI5V2HOsC8OAppeG64CgwLFxkS\nU7UVfgiG6kXKQbq9qIFVBbNRqFeZWAdHoz0T1ArCrXjaNVJ52j7HmqMlySo1RGRePl0jWkbPX43j\n0Q3Uh8/Ya3NeVWPGaaonNQQSzYkO1/CMqr78kAdWq7pT/fy2lYuERzCPQ4dhvV+zibac/vRGQodT\ndp+zO/QzkmkUzq0RjpZYI/NJL8y9g7bcPcvpMHN1IVuPh1wDm1nTu2WZuUAmFj+fDbISGnOVTkiU\nlhIDvtlZr9U/xwJt9Bm+lIakOx+o4gfngLhNC2rBt3K2q5gxIYYNLMo8MlEhNeYsFGwoiHf+r/YJ\nxvU7Iuakb+a6fQK6t/hpBEK/CahDO5IMVpv8dc/Ifz7buBy8FNlSquO9RdPeLC4z3QbSRimENFd3\nIc3hWkxOXJAYBdVGdn5+OuheNKv9jJtlN26G7N/RmiZDbw4MvzhuALsQTUMgFB+1l2i3evL+Q2dk\nNEKUc/RT10TxINl69zrqXAUTxzo8crQFx3flrc/AhKn/PrqpG8CGstuMX1JD55NoySSRsU4LDBxN\nkeqJjiHdqxN9UmdbmNw+/k1qfpvbZe208Arhqq7yLQuh4vciUc/DtaxzZk5iDx2k6neWb4pfg8Fc\nDnr5pW6Yi5voXDYgC8nUly9K/nEKFUMijQaJ8bIpv/DJqPRXOEjL24z5zrxW+qw5W9+5Pq+HqJUh\ngsXohfqs3jT7Hc5OuRe0+qTWfZn4LnGWj2KbdiALvUkjymRPl9lKTcKftKAfUVq0/w0k74fVsNDW\ntQ0Qja7CvINDig42KLRzsNuIRcaQA6xmsfovmZ656kMhs8hlq+wme5lJgio/VGUmt4kC7NOxnjGC\niT+HrxEeg2FRxN0vlIQXZxRpea4vP4PYVyg/MgvLalxhmElG6wBjcR0XqQ3xtkJZyuoLf7SmhAes\nrnW5YbTzCmd6K2dVB6t62t7v4Dx8IgIxFfcTpRX5h7KOSsyOFj7DCAgKaA02f14ZmEKKK1QVbkXR\nYXxEZkmd0ulVxoq4YgQYEqoCfxSptg5vNvQFC+VlOph4oGVJY5CHmagVVzZg6h3kY+VuhItYA2BJ\n+tw+hRhv+Td5whXh7r8d0+Xv1ldQPaJMoq17PJhpwS+F0uTx8YeqlP3DKa+wH6O+08FXYJK9evAH\n9Dg2og8V3H2v9CENuCCs/uuqnF+qiXgRsNTEa3J9JWSKnB3U66lQRFvUksue7BdrvN+dijiVi8dg\nhk+dy50JUaPd4b+ryT3gzO288fO0s1deTpTAcCjEpn1x7XFcu5AKj9eVAM8tULfaKQJYxxy0gabS\nw3tKQ7/HpfT5VJZHrUuY0m37OPnIVMvfI1hPVFlWWi9vZPgIUXrS/lpStO5jG+hlfjZRqVqpqoT9\nZ4A0R/vb8YrdhHeYk4FazR/MgyHc9IDg9Sgy67u/lui8XssZCqa1JaqCn6DYhk60BDCCry+hkojd\nVJYGbrVWxbhFrwCA9o5e88bj8M05v1DTwKRcKKW7OP8il+4EV9TjYgIfu1/3YSGGFYNVhOUw2ATA\ncujI4R82MRTEirVvceviCmyPwX7vVRFBwDVABbFRrUgolc1cEr0XAxiTOyyO7mGRNl5DhGDO74Lw\nWIwLJdO8eAJlOTeSritjGm5d1dGuyoLNc6qHHrVe2VdhkEeAV1NWrAvB41Sbat2kV8P5iCQjMMn9\ngAn8D3Uej/ILNuHfQQP7YFQ4w+fx5vijkBfh/IUy/fEC89wiykwAR4QCeQ2bkpbZ3BSno7pP0grB\nYfz5gQI8Pe+bdUXmex0OuVUgpGJUEEqvKoQsBaHqn+McELJV/y5uhaEo2rw1CqoL3zSYimDOtIPn\nafTAuTtoaC2JO0TONvqYoSoBN+/sqPTkUqWrh7NWYj0onMhoOH+IISuU4Ci0K2INk5k/uLfUK700\nSQ00UwZSywOT+OB9/5+vzrU7GlkxgjshS6e0Z4HMWfXBt8vNap1KFhSPhpXEj4iwidph7Y65Pj4i\nVHqOvLHV2ZThzERRd5mHv2GgbPZr//H3ECiOhahbXUfLjffyTUS6WqM+seKG6JjcW24mefEGErfI\nQjPFsc6NYePW9ATxiL6Bt35ZVu6a9pKMcNJrbYC1+X9z56qh3pCZDGox+ElJE1j9/jjBX9GKh+PT\nj9K8rNcO6CDJdPDH37WZKynJxtf6HmeUTmW9zpNzKHRVAq4A9fsmws4a9YJl5Li0pJEizXQRi5/a\nzaqNpKqmayWrir7R06vKElR1De1Buwi9488grEU522XNbmABTaStkvoN3ERBIOaTbStsVuWW/SOY\nZrgg1iyslqqQ8HWv6x+DAdj6/pKZ3AvEgj4R+Oy11GtL2zMVgdGCC/yQxoheDk5fm0S8wx35kKTB\nRecjKAC7/ZPybfjnTAJ/QA56BxTFqrUhaJfe0lfdBEQdIIAeKWSjOJAhgfI0Zc/LClkQbbamGyO+\na9sRdbEMUMxSgSD39APuWRYF1nF6XCk23OwS3BNDzs3opTyCL07PzvErn4zx0fgIGBy8pKNajPn+\nBSAHEWlUZlPK8SUXmIhwT/uOmaFThNtlH8AFTLgIDdb3A+0APTlGXWjNyJWJoE2b6h97tmX9ttis\n4w3BKc50BE60XFveMu5jOuTe0yzO2LMZ0Duq1uw+w9Q0gMX2pDEHhepX6AulcbnfFu9ASU4ko6nF\n1b1nsHBhiRFVM4TmaoLl9lxA34gWKPWYj+NWiRZ701Cl0VCYy7SLL6lVjmnilcAAk6QHqdUy4F5u\n0daJ21cjmtoS8r3YbQVCy0mktyhx498qncI6l8R8qubXiVTYOP3fsBmmbhmOxZwzdsbiGD61J9lt\noMU1BQpJGIto8cJ7f1mohh9pA4xJh7dgpIVYa2HA3YlZqI35N23JiEDreGQ5DoPn0yLBtdkfQb+y\nzCFUMnGoHcV3uHM2wRSJ5Vj53wq8Hjd7Vb3IiHW5ckfHoA23Rz8f+3Lyh7Thm6xzF5lBM2M9B5SV\nZcSLhMX3AhvQTw1afc+8jC/qS4rGffXzl0BIcZeUQjESgVFrrD/FL947HZGbQ0YZkqmAMqawqFDe\n6waggTnCYtqS8VOanBIPayyEisCB/L8KjFeqxk6Y1GP3mhh09QgGWbB+SBVtNKgjSziaa2mQnlkD\niIc6ljWpy/hSbCUJDxBIo3hPMKT5ZZwvuJAdQ2d5sLAELg+ChdIR/wAIxlHqNYIWb4WL87UjChvq\nT1TGokfzIvxxk7um9IqBg+2h24s+a1NeAQIFOIg8ftB21hmW8zIku5iFgPQojzxabrcd8xbQKjGI\nptgJQDqqNbWlKyuQ4ke/vZQJlzohT2ZVWzCU1yqMY7aR3eN+V+MbqC9kvnWxNmhVaABC9c2oyBNQ\nVqRhJ/9DEmezz+QMRiRdmjtqV9jf0+7GFdT/Ocd213bkQhpDP0rRHmjiqADUVxLQSTd4/i+mZxwv\nJ7Vy21PQsjbdAWDutjCbArCrEwZvPlKjS2uWuqj1M9wTeAZ4ktNUcq3+Noq9JEWIs2yIwTH51qx4\nN+uvcQ3yF6WPuZF65DCd4s3Cww2ZqwJaCuHYtE4X3mxMFhlu60YQYZxjfX3tU5KK0ngPBWP30zSK\nVfVrpV1MdYHTtLpwWEed0N21c30iN2irGuB2c3lIRqlKPw6CkAderOIVnCLUirgJ4O/hPfvekgcS\nSK+mGHQ9nTMXtaKjpC37lQ4ZkIC4dai4Rc9KvI/tF4hlZ/aS46HIb6/l7jnJ7uA5qq56ELj+1Umh\n44s1jfakzO2rY+bcoIWJ6YkYN6MNK70HDhXCZ2k8hVbqmr+lfSKFMyVNX4CaxiQ/BDjOzsrDGR+T\nSUNA8Kaq2x7Erz4wEZcZsoqayOI8RExufw3bLy4er3nq2eF5luIrEQtL9OTzSj5pZdbvbV2Vh6nt\nNk6tTVZB5jmkKg90x9VrBDrXVr/VBQP3H/2VmnWWiS2xgLAgJEilLpaWVLPg8AaMcioZio+g2BZl\nUfPiU7zTyBg1fcqGHnlvpK+F7sNROM13UGG045JJNaj7MD5L9uJ/9Zwse24ytj9T82aDw1yxLnco\nN2pm8eRghqOtoQxK5LQBKAg5KHmU4AEB3Q+ADsDXMJRegYw7e8EROyyUJViBYZY7eyifk5dPUH6l\npDGCz6upYb8NqEKKso710ZUNx9j3uHelMzl7IOGyRCUDjPhKRR43pQLcxrs+aq6xaTLVDK1DBO4w\nzd7KeYyAvDSKawn3ev7RhYnYgt540s3wzdvsL/dpTIvMZH+3ucJc5XZBr6YQJx/BzbQ/g461iseo\ndx7oxGW7UDrb0q52Kmu2s4WZBeujsfuAwdmEa6NNACeTGaYh2akSXgOihW+u5yVqMqo7VMY/FiNi\nwnRlyyP7w3RiVNjdCazVBBn0/vXOGXsOHOuNlfqpFt216kqfmkISDICxJprjxFM5FyCl4diqR68S\nwEgT/BFgdFisZA5gpcPyOzpD1HgBsn0qV+b2axxxh7gFS9KLDGbrlnpSeK6vQc88vg1TgVGTuQw+\nP1Nc6hENGomIwHK6xhikrM82PDY94Je1jf6Bope2PVi1b0AKJzZdV+Ysz8V+OlBXtBhtmzR9Tgn+\nbhV7XPfiOUNsWIppzMCxGT0WYUEiub5qze/L93yLJ7Wbt51CeFjYxoFNJIFl4qQf2/DEniuEBcAG\nKpQ8mZUYCmTezG9CpxZuUV8Wvrd2gld9bY3X1nN3cLJhT05og1SfG1W5xRE5aVgnoCwwN67MyArt\n6UfpdydUKZsPZD/9k+KapRurr1QnUyLxghcBC+7z8XUEYfu4HOsIPmF3urhtmFJJjx7AFdh8hbA0\n+SaMgKQmopv0BJ7/wwcbvUScFzAdqzhz41gtimJrwe63QIn0rMjIfflDDxFIikTvstuqi07V4yMG\n4SDMRTm2LbUFtcArgdw9tcqlpdd7W3sjAbIM8iv0F5wx3148zRprBZhJrHfivAV/xjJ2+LufAqos\n5S0OVFaYBg3m5x+y8CVbCaCVKHzLKMVYWTBbeQkhIDTlXqA6JHwAyDp5cXUr8ycXVywc+icctTzi\nZ8s3tc5SMBh6NcDkAq58vhGeyPynIVQUUKmASCIHdRQCtKuEa+62RBH0LUDT3lgU5YKS71I7JOa6\nVzhgfDSo0I/ymuRBrjIjgmCAxQR5EdFeTVQ2FUF9K9q8E6Pu1xqaBAnXitDsHi7AfKt4nwazFy2+\nlV+KQhjCb37/yiiJmaLiGBm4gk61DNvHCwIagD8uwgAfyCaB8J39CiC9HvP4n8cPMTVpAY3CqZsZ\nQ03Brwe+jPZFlwXtSXrs7CTN2hhnSszE9trmzMRrCrAyh/wJfEXjBk32m5OmE2yeJjfuUsqxO34X\ndp/1hsLYJhibGPXj7fg/gfrs17lPvf1wTNMFQfiasPWgVWiZppYr3fZeSwAn/wsSpgpcDXEL681q\nPMbVNwPA1I0AtUZoOqUHlUFwqTRH7ORUW5qfg049prDrnWrM/kyB+EGBZgVDLylsocOmSuBWoAWx\nDKmR1fG4BQPfJHmwtpZqhqnQbrJlbvOytKAWOvFkmrwJ3xBboezoeAKsWhuLgdAD8esYMnJZJTGP\ndrFL1HW9VD+gIL6Sx6r/BB7Q6FV+1gYDg3CHvbiAX3VCzqER5ZEeSqTuln1M3KZjARC2tQpqMoAm\nimX3U5yW9yaMx4hZx7Nl/SgvwZl9FeWkqEsxRQMFCs8P5/t2x2F1nW2Uds4wde7YvVEtF0KG7v8t\ngXRlhTs5pWQPge7hlJV25U9yRI/xMfuQ+jRHTqdO7DtyckIa3B96SaQesN1lOHOw2/3K3TOqqAmQ\nQKrO2UchTIObxuguvPQ2LDzELiu9BCrc144QV9oIb2LeP+/6PhV4yhX/PhgHlHf8LrUY7dGphYrO\n46OpkuzXAeA3rTM5lhsvYtDsCobJMo3BVIi8QYUe8a96R+zaXb4L51DqQPIH7akl3JHCVpuMtVsh\nBgUfiqJg6ohENx2fG5kJCE58DRRMJmv/24OJK3PrpN8izU3X2T+QIM4qJXGC2+9apctI1f8s/DCT\nJKgKzCHsvZ7oy6D3ienrEjOY+rmat6jf9Ug0jDnvj043V2yq87XFJIPWZXX5ZjYiqcFMyA6xhH+K\nPxOCS/f0cNYj6k2mX7yAuq7WLxsAksT8yMi2EdJI05An9wmz3szbOtyXyXqHCI0KGkPM7c32DloT\n2Ngy3x9X/TBT1O1UPwdc+nU3b4vU+1Ol6G1v5OLqvgJ/hupDBek5/lrobBl3GukzP2NaCUNIJfvW\nIxbaEF71igxQmaXjIHvFg6vvFWfisvOBjrxnqiZkoKEg2OaUlL/2jzvzAISHoidAX9mFotn0groJ\nR0CrCzGLy5eOF6I6/kqTpvTrGEtszSF39LItTfCx1DXDVXx56SaQ/huc2ICqXjsqK2CmCvA28TLd\noCP5NJVVspa3FugvKGNNfw63rUdSwZovP0B0nzfXg5+f1zFiu+UpV6x11CFyv9aK+rpgalbsOlD3\n1Op9kPU/58Tb/LAohiGHc9yoRZZv17hQ0iT/+wHX61dkd2TjK7Tg6wL5SgYgudQvQMW5sCE22o/0\n3WbL9N8x1YNrZqNqwdLUniQzWUWmNf9PqH46EEO0ARk2zRSdVnvvgSKaJ08V5r1+6KG0A9MA/OeA\nUzWYCjQXloytc2XtZxZHnsf74EL7uqN6Zd5t/tAuAUoXNOYudyXx5INsebKtlQWTHsu6foHkWKvb\nPL1K40+Q4IoUX7CGeTatxxcu05Zw0her5lB6TNfLro7rM9IAnyilBC6PmgEk59ct+jTAwZuHkPE6\np7p0G0EH183ch9OXcgCcXzzCOqdnjzFe67Pt5J5/uDqNtaDPZR8g9fmLvM6GDfL1KRq1ownySqRx\nmR59EiJkX5qksuE1jnISWXRH71wsslPlEHBeE6gn79mYt0tf3zU4MSgkAcZ2zlvvbm28UZC5/nW3\n30BIcYnKLOUEKqgfe+EcnCgjO8URoCNLb6xCctH1LpIYJ47yqXCnSP3QOJ944aDQ9O87LOhsie84\nLiENVu5N3HHuYbCH+TSbvrAObXaMdpEGB2sQ+n3N/+SvOYs/Zn/9c/WvFn2rwZoNPQaz3FWbKk0p\nwwtO7pfvchvbnmET5q/Bw4fKozjhwR3fRIm6KJ2xObMxVNPXUSHxuQq/gv2OFKc73zmNOK34bEk6\n6B4UK/PWNdHCfAzLQMLHKjSxjbWtgDeEHYLWG7echPpaR8YrqJNLBvP/+l24bIQQz0LjKmBDzsL2\nVvFjIwxOah4NjCYVhPY+Oup7VoMEzpOv8z80T6Nx7dcqy/lbPQ4hD3YbzX6H8w33RY94FRDUtRls\nnyVIVkUk5+LhvhgP/GBWjbgdHGZvUv7+5E9tmN9RfQoxd3nFx1LxCoHh8cmlae2al21JRQqY0xev\nmbAl9KSqIn4v7KURa6a2n4ULzBQvHstvaD8mLMCf+FktM+B5nIQhZznqb1wJVMBAzkLA2v1rMnXG\n6PnjwuB9/btpYm5m28W6bZDpFrNzdERnIA2+eM5AianRkoZGxcxafHZM5HkM/LvEm2l5I3+pDAKS\nWWncf4sG6U7D31mVrZaMZ8xSvpsLX+UNICV/EXRBySecDRSSkbr/Z8Xa1R5KAi2OJXBI2Mt+fEuf\nkqKFzog2ynOCNEufk23wlYwVh16qmYKNmKtVp4IRvgt73fqxys4pbY12s+pVMK8e3gWcoQudDA1U\nuntuMyvLw/9o2q/dh1p4AVlTOX7t+79pHmIGUIw1PHHRBvbaW+2bsTRMAWaGg5Og3A6KKzDIghd+\npafkv3nMaQG4Ky4yCcjRXMMGCxBj3mOtWIwXKNdp1+I6lZq1eUFrulXVKvw34c9nflsnYyN0gldH\nCR7638itHkKQ6CPJ3umrc0xJDQvck8u1k2PkOpuYEqpI6G6L8bACKQFFCQEaYOxy3nFHWJuu5z/O\n8QHIh5tkGbfbrUubftJTJTvw3DV4HQ1lx1ls+9+FBSjMioWat23Q1BSQGRBlwT1pqF2YeNY5AelA\nl/sjIdvAKnzv3p93sd3TdOZAkKsC2qhDdJDPkwpvwvBu/hwQDT3o1H4uK5zdlMuP0PP2Napkt/oJ\nWmZJWuDzutARGAcCIP9dEPJpLAjnPmDggEwmglDL23Sz+QxtMkiul9NQBePmHdtU1ec/q97Stotd\n3jGdBFSJbcKLXiKuMwbkKXFlN8SSnMlvNYczPN/unIL5eQumVK75Q0jRoSntCs+Xmws0TCXLOAgV\nnzfnT1h738P88zAiQI1zxI2Iry0cCBUoVhXweuD1WHnn1Y7+kOK3utvwWMs4Ow26uL6N5pyplJqX\nXalSw6afdMMWF4tsDwgjtd3OUKn6PHwSdbaJWA+PgL7Nx79Nruyon/z1od8d8gBxB7WJEIvT/UzC\nAZgybnt1vAVvS0oTmzmeCl8RYhKNLvRmAfgc1TCOQac0Cpp2bkE0LYX3mpltsVdBrgGf6JVIIDt1\n8T60D51dlidkGiBgWtWwgH+IPEgUj1lnZyummxf+aVWmoONz40MbMkx5ESxxkC5S3kmqIGWAWynr\n0MTObQvu3F72RLqIwv+TVGSkXo3Pn4VlUfnDH6Fe9yYcvjd98r9kgKH53bhmymE7z+eu6AzVdcIZ\naE10nyukAjrAPIWy3V4/W3cPM/Z5kX149yY5McFvQMNUHBcNVBwVpIshuiTyuBf4d0N3qZ95Iokq\n+pci1lev+8XDDpbknOXb9lMyRWqzh2+2Ba0xdXwjRv927PFfEsxwi3PLBEaP/DjNHjjkCoSYfTAA\nYbeC9Pen3baHUIj0g+SdvJxB2Z0DXRg8CGoy1ocZdrXed9qaZbr5pGxl+huSmzcoL3t+pZSllAEm\nkncxkJLnCiobSnQLyHBYtoRJo4dcNBZiRF1XbmwXavWoL6SDYJzM9dLUxhJzOwE2I4WQ69oU9t+j\nn9aUC2O+/J7HWIRKd6FCc1mlAyVxDC8J4+NLfjKpQDAuYJ0VEcReyfRXt8L94aZxCmfc6hUV6ZAQ\nS4Q9mHiAB4NXuqefBfv+zdmK0N2neKpuYzkpO7yjwZVLk0D13cqV9QCcPEGYjGX3757Mh0aVXNmr\n5ZiGf1tQTVcbVDtl/zth2ZcBLCwqHTZlLvUH4ZdcH0euicZTG2+f5Vokhu383+pE8/kr9DVrXOQq\nAwzGBR5dR4xUHrlZvh6+Gd2JJgY1sJxjybJifRVe/ecIR1OlUZBXfuM/6KyELvgjqiy9VytHpjiz\n+0UhEAxMXPBK/y1WnFh69IOzL5zhbKPVG0W+9Yttt0uA2XF7Pf6yeWh6jqevICv4e2CBP66rf6v+\nu6u1xRgyXyJtkKvkusPxtKcdHtweNGnNAKwukkYQFYNfjzlyoGQxnj5a5N6RtEL/JBJIOx74+JAI\npl0y/e905ZlXWYVEwdgPgwrjxYmJBC36KJSmbNaVpctbWLU8ew0IfBxeTtMAFuXbZPDANXwG+0H+\n/0pAODKz9A9r515HNFQ8eN7lafW2CYjvTam6tfc83FJHKE6OvyDWx34Yjp4rfa4F87RXte27flyK\nW29iegbCV1Nt9oiGJ4aeGDdsb6ChcJD65wHFlUMKgu04ZYUf8o4rRYYEOfuBCNBCS7Hdn5H1pqFT\njhNOM8EN6qivzeF86EvsfBk5ivRDJxORl810JDrkOa/165Tad2EbH/AcRyKXnm4zWpfQLtIkztKc\nSWwEW1NIMUTbK/0WqhQyGBL2W3l2gyK9McSlfeCd/lyS0N9MK0Y7G/GFRqBYqT/Id0GAOMQ5jdG6\nbD4De0pgvmbQcj8NAX8iItEEM7V6+ZaqYkBbTmYTKd9y4XegwyBDYgOSDOeUdw6/8bIg8fz0GXop\nJND7Q9fF10RsKYvZy4PMJSG11YBKzZfBqErhzjRePLrb+EoukU3j8aDrP72OjTt7jsk/MwePc3Tf\nvdPEGfSYs/ItnIbOEj9o/j1Qv8jq309mjCtGUqiKsZTf/TWdfGv4zT2R5V8kLd6bQ4ny1JwiqwTK\nxjNlciYkzhA085p3oNtQChXS9qWQVGAxdQZTUxi6pWRdDgrszKOJ5cMsUJKnDf0KgxqWRlaaJFoH\nUpZupgz7Tt53XdV/5mnWYO7YSaJF+vkxlgx+OAqTYFsIsHpsH9w0gQRAHnLCqKjhHPwBt850U0lP\n5LAMragAyShdJL5c2SIt+pFHzMRX+c11DLuxw7s3zWQ3kAhE45SEQxepGzn81mckZ4Oxuq9wS5uL\n7LAfjMLuD0ewrVWj6peLaXObMb3YvqUunfKynUx4fi4NSGaMNa5LDBNUMFD4nVZEi9JOVx2P+wAq\nd0PzYMsmIjHLy2++Z/5LyD4hLDDtqQ2okeOyT4+pxHisgTDlu7Jy3dY9z6v7s0UkqpdTk6QYSdvs\n2CSvQ2trnl992tD195u/fT4K0J0LU4m8G1w/hVusFp5GJeZ4hZ84Jv+VguUGG/O+h3V2hRVSsFxl\n8iSniHNLjYa2L3GXCxXpmPsaqwxn1DS2PeHkIKF8QkmRODBdVIFoM3KUGks7ao4ayQJXWQ+qjnlo\nv7KyVGk2UK3py1v98LD7HeKMOhVXDtBtPP/GQeO0BY7J2OU4sB1UtDLq4xv3+2oDUYy8yXzhUf3M\nWx1halGd7qUo9NrpLGcXKuQzQfDYFqPLBH0mxIS0dY1izaci2ctWa1PO0Myn0/E88gWT9VNLsB2o\nnL4Pnul56fUUKp6YL0nmEk1QIaFumKQNVFbIwmzQiCAHqSZ718dm1uX2uGiYZa2hUUnMQQAPe2JO\n49luIFvkEBWKZM1dtn4qQsnK6Vlw+yJVcF0Ayz/dWYhtSk+IGa3ooecJ+MO9wMNvsxIrh6jU703/\nWOX7IcZ7CHeL3Ts1XINKMCmyplQ14dUfu1wYP3gxVzRtBP53f7seASFFy0qr709FgYDrxX+ea663\n/geHKQVT7YDndj2/j43Wb+Ue8isQzcEvMoRoOUG5Yx64nIKL3epvL+MAwQgOsCe+cYtJwCL9i7iX\n+NnrjVANDoPC+f5oPdvso5TxHduyPY8vAFdiw8s8TBuGi15Su4iOzs2l+OJIqKM4unN/G+SkfIds\nZBnd5OHzQWBNMeX2eV2cLp6eKVjcOU8hN1nLx9Mn1ih9IPGcH1rzRbSXNRRK/5Eiymh78CeTKjOX\nw0MMdfdFov69cL4Arlf7INbHl/FtLrUsbwWCEoEHNr/g4F0De6AOovKKrZK5BCjXZq5raksOLUXh\nIV523NhFDKfKIex3umjRchNjXzBcudoIFyCWTASnTF1NJCy5jKOgROCbxMyJdDcDY4obeulSBxCV\nTM1zODyKeP30ySFmSB6Muazs6mme+x5mgY5Vj+MmD942DsPEevJ8QZI8fVrXBAnFkCTK8iBushJY\nYetKY+yqUxLvgA88R7HuNx6h/srA1FALTy2LiWGhLsb5wTgMbx4Gp+nKHDhFSGdXiHiDF6xRQ209\nXVds47X/xgaP6cZGHOjzNbmuAG1AZoz9OAx8kvUmDyf3bvtGQ1nWORjlVaF6TSSgcX3aPOJOXM2n\nHKaKHAv+N6m6NtDqb/2epuH5qtB8kbMOAUoYOOQX0/QzKFuMXl/+OtUscFpamMQ5hslpP+jEIIub\nq4kmZgeblO3zWWzccArM5QpSZ+LO7AmlvD3AihbX49aW+lbHeBv13RxHEZ8T3Rr9xuNWiriodYbK\nJ+cmriWdsYDYDlvPPd06a8oPQabc9BPxcB0pAiFTVy6KA86oGuJmh/v3NpiEa0dX4h5efo3zOEs8\noKZvNmiakf0egAfWE/bep8axuEUh0Z3+rISu21mxbQzQY16B825l8hdBCa8/JxokYGWcmSB/Dlqz\nKHByuamXP6pfW0NxqGKzeMr59M7k/EW85qeC4kHf4Om/rmDHZMrDOsFgxL+Wn0H7l5NlGsQvN/4F\nDMluIEtqP5piwzj4ihbAX3Fdz9OgfcHItCuXr/YjVGatOUkJZr1TYxZxsHo1oiwujDNsFVLpPzTy\nhkdjsg8JT22mn9vkb8Cr/kJNCCXuP6x/mgtXQ19Rya8OmWmdLFe/0uZTZGEoOyLUslyeXF1mHF1K\nkEmEubqjhu6Eo6JJn5C00TUvDinVeJTc3ACmLYyr69o7MBtjhvt4vPWCwY/X0p8LaU6cj+254w+v\nUSJqWiIwtq/zNYZD2c5WDy0PYncOIMJ87eXdFrr68pj4S2FXp/n7yXDIjG/V08uCFPhZdy0/hnZv\nhIqvL3kiQOPenbuPlB+oJeJHi5ZzMx8BjwYErwYdzzoQOmB5HlGvX6yMx8TucITgAQodILxA5xGO\nzAgHOYDBJEdS/VH8C3iJKqGv1JT64pYvfTckGV9jO6cDVXo3T+cRKHZEMh3w8IYb/0P44O/P1+pP\nOfa+Hk1/nUKZvAeEfAYGAM5lMC0kuDD8weMkmOqHOnTvZMqBQpB3foMo4kbwQB1iV3D4MvvcMnVo\npo72dkE0p1l3EMaLZvR74u/inCCAj5QmnQEor74mHxQFV7f3J/pACOdZF/VncchdPl/PfrtuU8dC\nSaQnK93mFTrlikmp96UJk9AAVrD0laBUeIa615GTmq6tjyA2Fgok5zAyy+GW6cPcwnaABaCuLsqW\nK510SnqYQa0cDSLF6ULpHUSsxghuU9Wv6mYnYGh238Jumj0SKFWUbGH0z7/wiPK4OsBrErrmKMjg\nbj4Zb75AK7idc1kfKiFN+eoISvxvsf8TPi7+JAxYpJNf6/XOewzWK1QmBTznEKwChpdLGyAc4vdI\nYbL9X+4jR2+YfiT3o7ncIh9+J9hq3bleD9bJTsvEfRmw7B+yoHi/tIYeRx+LGKdRZIUHmq+l+M8w\n5oiGhJ2ACUI53CsjdPNscRUigSENzcsCspEZVIfeSJ7AzK2dLOAqfdV+E/Rnen9cDfWaBa2jO+ad\n6+GEvfeVvJCgd0b4jSBfhUinfR/X9SZt/mEL+OYAYAAA9mR1aNMZAgTfgAFQUeENg8ke131onSlI\n8IdFFrvMWOMGUaO9lUkdra0hWhSoZ1AERqofqns/NeVpj338YwwJCeqSEwLGSfM3UUUUw7XlpNi6\nnTN3UTNYE09+KciA2073BsPf+8OLmqcB+K/k5eY7UdyJO2PMp+QO4OYfi74yVu8yM6qGbTbHEKd0\nt2K1+Aiyl8GGe08sa18u0Yg1ncL0G2JYxfrjbhTijdWVK5/uardGMPdV31HcGMDRq/SMy1yuzoSY\n2BH1khHOErQzq7/JDK+WyLh9AxVMoGyvagtRE0WmGM9oF/pJDTz9sa5w/cMrIGnIW9iBD6dR4RsK\nLv6rdrB5R0JdSSuonLusEQGT0HlGjhO/p9hJFvCDt7SzhUvK02D+89RCtNIGOzI54S2arCNiIPde\nzLCFR2qcqf1bVQ+aT7SWMdlAWsxFXcL5H6nO6mi7BmeZY4Y2g/DbsCcFOAVLWfGQF228oEQCgRTp\nH3P3xovSmv05OMiYQpUjzk7PDalSTRSFMMx/SipC1n/X2tSkOi3CWzJlVAhGylicqAtWKAEp7DnI\n/3NGtT1vIfgerwao1Nv4VqnWI61j67pN5BJ9g8GjOU7kpI6QqmYsYCPoZOVh43OxY/0mS5y89eze\n44SnZ9s38EyuABAx7VkGNqwCQqoTabqb5HQ01Yxnwz+sU0EUPZkw9Wm57GpySHY+gscKRHS3KfT/\nRFymajp8ZgQVfmdMlHu3PjItmYqlgK3cTwuf76Prd7Nz6QcysJPHsSqECgeEv42f/9/1ZYfJzwpr\np2zy9WktqFY9eGUfMgvuxIXdaOCfd8QVLsBcknUvUKp2RYAyrpSajPlDGitPQu+FVQXcNTc1pJRu\nOk3JoTCG5BhNJT1CfEcWVwW801PmrgQ759xc3DMzES89tcbxh/3a9bIuBt/7NYfha3twbN31Yrai\nTWDqU/rDhjw5onVMl+B2KhzmqnMDcN3z/getTtJbTAdD83ElqONn0fhXSe2woxQ29uJQ0ar6VDZL\nrxQmSwMqp8EYiEUEjCh9S3AF1nHfV37CJlm3Eia19G6Bh+6Fxsuxw+iTMp+/9VazjpqFMGEOfgKU\nNx0v9mRfQ3OPJHEHtqhayQhkhkjkTfloswTzJi6aWoPC8nqVmNoEPguhP0+oikpAXYxRX0Qcexxh\n9GQCdbcCxnibb5Tl4qAhunPBL2FgW/l3Kcz8kKARyCZc8y7nUCE0WGKQmmkoP0CykM9fwAsYJmJG\nVpswNsnis0YKwWV8WayYkh5ab/9cEhJ4MEdRx3rob2Ks4CRuWMP28PSFl7yeUUBNGVYRH37wtrta\nK4TSNBl028qp+PmuwY/xGeHQt+0vRhZgh3GDTtaJ1VeMzogxkXhxCvKEkSRtmroXyLckd1VLf/1o\nsDkssIx+1MuBpH9M9xxMyuPHsXPRvEq21SssltgDrQZ0ptt26xP/oYsZH9y78ryy9ZfVfuqNSfCK\n+JIQoYCIBATnYM3e5Bz1SXciMijiGTe/ZIOJUquCgx+gROdDeVOaZvHkJb+8A20CyAaTZXkX8QLg\nTpxt/+sE4vDzbJxGk+7UYk2wEKQKjYjd6RmfdC76ZxB6/dkHFqWQdudecWQKc2znc+saeTgdkA7f\n3glfvItWKKTcCNSv8Vc3t20IqsqMflMFtqgQYaBg72IJ1Hdejq/AtyqNQl4LMNuZgubFjptUEEy6\ng+bcRkAi9NGkIZZsLUjCR6+LZ5XJdqU+uixqo44ac5IDAIh5F6J3Yt0oyMXq3xbnFLgJwyNC1fEN\nuttW1H1b3S3nOUe8HyezDOPJiXOgdQ0ocS92CwpOCRLxb/JyKzJGDGCuFMKg3fYyYpkstjooFr8v\nKYvjoIuHCgUpcxJYt6cV2vxUtoL0+qknC2PpdTNA1H6Vu1tFO3uHlKBqVPanwL7Xuy7l46Lekzri\nR+0I2cbzwrVKlhv60Y1ViWjrox0G/30fW1c+MH7QzEtUdGey5vQ+Sl1tGAId1G50YnVbZNPfiAfS\nC0JjM3ooNkCmXAuzMg1Fy0eE1SqF/BjcfHqcnxqSTfV9ISZlXyW4CrmW6OGCqlz3/xLCcK6G6WUd\nHzsOdZg4TlHtvt1UdB8P/75ysMEX4QrOjZh+KG+KDRum2DvYaxrSTMGopR17RSb8L3i2wwLDEn3H\n0KyNVcHfpHewgNP6g5S6xvmLjcmDcdqIIwbfJf+lLxZKKXZM8IY9KJjoL4lC3Kbam/lFF8pbDmiv\noXmzmsyrq/LOrUxnnf+Wwa10yKa9XRvbHpQJzfTg67bojmtfdEmhDMfQVx7QhvDoHMeayorzBHo8\nDHl5aKRTztEtOuKOObTtwQVRjb+lVgOHqGurc4ew1dN3uH5nLxrs/WeKXeqoDRPeC/W77xaNZbKF\njXF/XAWwCM3XfkNQPKyoYabrowA7SZyW88RI95L8u7dKgWbuyaZRzqkfOVCc1H2SL/Kp8KASk1MV\nKAcX1E4/1fmLdv8Rt4HwQfT/55IKRNAnzGk4AkXe7z8o/w19YGhAQ3MoJ4ixzL0E53u1ebH8Xjt0\npsuOh2fTOzUO1jSxIU/I2FF+tBPe940jYW4YZl1/hoy225DK+9YkL0sZXTBmsnr2MVE9dUPJAkDP\n5OdBsD01oGeCVFmQ/PqJNpuQWZRKlVcnvCCrBjQsPCTf0XMXqiXDC1UJ/RhFum+mIS/Pq5Bw6Fef\n6ykW8thKlNtTiQQQFUL9j63BuqgHVtx3b2ceaLcEYVoba1OBNvTq+fwHsIr1jGHovSvQBWIyMt75\nxbpU3tFUPlGA2dj6tpyIaI3pCMEeBlRGagf9kx1weygvhbR/L8cJUcah/ooZ6zHtwakwP/RxSDcc\n2fpvhAIINljDKdmFjdQ5VlCEasBO4OvW4KpMrGr0PWfCCCAhQCYeXrh4nG/ODq2i840KHT1/93Ms\nEYBdeZpl2UKpa1HP6rLg/3WHVqrhOmcWG7B3vd9+x/SLi5IFFAXel4YncELo8a4rH84fafrD2QBR\nyIgkl115GU/9Pcx5IBxJVq7sZwZgSSbhWaBqRo68ZQ5RyVN9v8Naeib6y+0+Pd3j9/JZTluTv7Xo\n8jd7KkUk/lREk/3L8e1XLRmJlGkRVfucbSbU3KzmpKTVPRd/0tg//bJonROFFJ+2rfSVvph3lZQz\nLaSQ5LkNFPHPR5t4DxfoOtTD5SX8Jt6tV6deU9zwXWNnqnJz2C+St4jmeEjuq2B8n/DOvu6u159p\nFoJwzCSKclw0E8QP1pcnpGwjKsM08DXQHtoHqML9o7MHbKiSltO/NbKTiICcDs4v84MT588VBxoi\nk3LxuFora3Uap3TSuBB0X/TKeaxZXvMqSEBbPuj3Et/5Gk5NAisRq5lGwXr55TnvevgyemhBHIAy\nLLm2fy4zNlBkiHhEOSawbstG4pu1TAqss90uXZV8BVkJ3ykw5Qgv7ibCpwZlC3IvD+wOtvxgo9jt\n3ZcuT3HzAqat8/oUwenL9/2yiEeY4BmbKZzHE/Wx2GlPA2215daKRUzUZ8uE9idBqP+cCOSSeKri\nzEacBxPitTMZvwpaCKE6ABDNUFOCuUOzg6UDSEoSPnhbg2pZIbAVCHWc+cCUvUlmcp7q7Ijt5RFg\nWp9MUQjdhrJseoMqCtKMe7Gkz1rjXWPKsQJJjaYN8dfH7JpMago2ZP3WS0lR9QnyaGNgOspv3i5g\nra4SUv9LjRMRUKV55MOc/9lVJDCphsGZLuyo0+IuWaqxfMsWYsfkSf7UfMUvEZmqSAKjOJk1KAGu\nopx02LKnDCP+25X7o4d1dL9FNLtfQW+kIXVEL2q+maRPdaZYuz3vT9DkwbxQRE2tzRPp6QTxHaD4\nYm/M68C71i+mNBO87vgT6kwZ4L7BhSzZniHNYHCyma1EfyxaKJZhhl1s3GiZdC5zPnPUZXzfKB9I\n04Fnxyk1L2Tahpl67ASmCD6kIs4eaBPv2wEtDXVoKuTdjP1j56MNv3SYo4xPJPbIfGNNiUw/doYc\ncC9Za1roGm1n7RoaVvpFY90OkHezMONxGCSdtiWiAKvbaMm1+9q4oyZHv7QAVaTLUippXGmyWGJ5\nEHdRqibjJr8/NrOQKHECOJwEpuvqwCGI2j1hE2PQx74MbB3VSl0rfZeB7U8nxXoilFCMXgsjOOeX\nS81taKbnv9BVgfAEzKlv3aoekRctrPbVsERHqlDtJSqgSgLXpwqkA+RzgACJZ5fCXZc6NYcNiucO\ny6YiB1zyDbNaXDne5k4TPco09TpnU2kA4C9vLQAvMxMdiwJEgiL0LoPDmOcn7uDJU35pKot7RPoO\nvAYJr4sEq8OYcqwYapTvIwtyiAYX2CxZuvL7hGFLGbISUD2wjHlMDnE3nTuKfg5b7BfINOYAhlEG\nQGe+EQRlpJVE7eVPX944A236yl34C3CupV4SwB1vmhnwPY+FbKZzdjMB/n9M91wG8vu46Ma2AzZH\noIc+5A6BQgbjLTJx8bEjSH+aWdCqNasQ1NnTalHr+lVNsjV9s76w681M78fpxdjdit4H6MLT/rNp\nCfk0Re3EU0lSJXqMZCe/xHLVKORhFcGGmhSGp5CycfGA29+bMIlM1tS+mXpS63JX3V4TXVvdL6C0\n7mJVWpxrvjV39ejdGx/MgbzNTcC70kBq2xUMC3qjpH0Pw0NtPvWwwP7TcLtDombBG3R3lxCwqQDG\nyYEx8zG+b0G2/79L+UEzFWbBcWftMjFt6AEFwaLbLidBzZCbcsvVhg1caVp4fzdScVNhNrAuEiTk\nkHkovbjvNTiveBXh4aAfJVKpNdA3Jmd/GGCAXY6ugiy30XrnjtAbAYkrupRTaF+j4JA0CPlHkgLi\nBiAxRpEiBjnRpb9VdCyEwQAsVre+oIPrgNiY3xgvO2WvRlxt5t/i03rRVHt/8qnYdTPpTM4NTnKC\nkbmEFhb6BPw9XnOpsxhkpLRrKzJTyVcWq54KNJ6orRhuWVzGipXnj19mf7LqQf2DvTxoKj0WP7uo\n+SVWwsf4VC503dwIJZntxTiDoOTvfotgiD2H19Q2EEzirxY5ZL73ijIMMK8mdMloerXK38ZWlcEC\n7qThd2j6oYfcDcVpES/RZttUFY6k7nPecP3eSVvGbqZo3hhzeJUICW/4hpsjOpEpTi7ysYJOl9zL\nYIR4YkQduTGhvsAib72r5YvxslVlowoHvRgu3VJf4h5VJQHFQ1NVjJ8fQoQZmHjQbX5lmIaNrPiv\n+QdIHBljLCfKKTivv/9s7qfgn/2Vd9sMryImvbS3FYQBHqd48GpVY1YuV+iTlcJvGJVR2d3c4E7L\nbLxqwdQ7koVQi7X6ZN4IWKyfM6vMO5mo0rNkWJvGrMdVR+jgfpMoNtoRIfE9/nbS8Iu5zDQcVqV+\nrENwlCHPwH70zXIsPZJMyFJ3WCetXdkf6s0JR6LTHRQwh5P3SaLObmQqZMXMDp//xWS6ClvGwm+B\nQ52VdS9H88zNQN7dPUKJNhnNtp4H9qNpAS0TM6Kgb1gLGLt3nDEa9YqYN6lQ47IQMdnjnxIv4pYM\n6TvG2FlXBMX3dFzHojLvChRkaXUBY6GQA5Nd3yVOInOBa5qik2sw9EVV7LHwBKm74s/Xuu6QBdi9\nP+vzOdy4YwgiEuFHVM6Hew3RKSH0FMKVyh2WIvqleQk4zei3u2Dx9YQhW6oAzIbnD1TN4dc4cxqN\nMDAvf05VjPVMGGjYFCRx97BaBXD2M6QeSBaXwS8vf0QDr3hBOXH0DHOut7uGUuIJMHRXKgOWduzH\nVmphLU+N0T32/mF/wzPOOFsU0ZBBEwGLQUKePIUsDh7wVfNozrljxRh7EI7jXJ5LAi7nxiOV/OzX\n7ar6oRWuG60ndvkdU8+5kc08XdmFjDbWtPGUJQFz8k1W8boYgd0L3a53mYfxmNdMpbKgfp2uR71O\nuxiW9fK5yvV2+nkLdNg9P5uEySCsDchyyHuRVNU0oT8CBA6YGujjSp5uySo4iZqwiAK3RZYVgwLI\nbl3UXV3z3O9k6/Zbj65XmkT8R7HO/Cum3Gmnxf2EyhmmyVFypiVUv3/zj5AdxCeKLLqNFsVRkI1I\nph19doF+DwZfyssKyd+TlK4UIfmrDGLIMg7iiSnMOvE6xQWKrHaSEm1hWrQj+S3Z6yTqq67KngLs\nsIFyiwiNiCw0tdrFhJJynLTnM/m4kofZLR7pyoXd6hyGg/qxl8xwhE5DQde+cBjYJAs7T/00P2/k\nNuWb1dEG3FrDar4OWf49MonfnZlrNVW6mraS1flY6WTA6eMYwtUZdR2nzARLxg9wLzYivoD6eP2Z\nvNsD1R9V/oTU1Onf9a6vFrL3tfA5TEr/QP6DYstdnPpXO6zF1DbZceFDfEpZldAvORakaGlGb/lj\n24TmEoWfJDRZjU6ISC25dRsOUG5L2csCMGxcIblKkemxDWI1gXsy0M4s/rakvoUHdWB6I5i69cVg\naRZOQGTQQIRBc7tMmx4qmE0CgYcl/ip1mBW65a3Q8AFcXGXLDyOpxCVeBCAsZW8KcP6tuPJuHS9h\nzugWFNCx7T7I5dDSMrz5ZYsPAbnqeWkgdam9RLg2hh2mzws8tvsztuBKjzU2ylQXkZpwU14W7RXK\nfw8+wkhRIDizhl3TtErAqn2/04RNudD7Xqmwz/hH4ag0oVWYy6WSASYuc5Dd74amGK7Ujjl61UBQ\n6bxsHf0fEYSYUg0jYN1gdwhZmd3+vIyENXainrZ7+0EoxtCLkuTXxitkCd7J2rkqRwEa5m0tGxHK\nTVFrx2uT7uUajpiPfSRRTsj7LliTFiddOgH3tMAqk0DTvEnbHafGdWM5ZS/js1ZvDFf1EzSAenH/\n0LHPx+FFDFLJ/4DkfrdjyYXcensJWyIlTrf41lqnzGTH9E+nOGCbxDPztFV6xQuRmfuucs779Wja\nEG4Rigd7maiHD5kqPVcOy+yG3u4Vb1/2OLnDfT6hhYQKCtW9yHBQMEG7+gXe/0LXc+QHf/fV4Iw/\ndeRnq2DRu7ysA4oESxLh58S6jMXmycuSOv1VDwrFiK9g7beWyCeP3XoU53Xh7hl0dITHzWtT7khT\n3No8aTFSdvArzuT34SFu8SjcJ+ojo3uNTb6i7X/7X47YoUfj2A5OR9Mhr5UrUAnYP8UX+MwEdyDb\n6brWgY0Q9tTdLWL3kSXJ/p1BOYdRua5EulgJhqyNOROokEnO8NM64u0tstyuCoXomDeUeTGShQx7\n9M7AAq5emN3xXWf65qQCOIiNRB0Uni3RLuW40J+MrmOeBSQzWt9fk47nUaMvKOCKSbj7FvRK9T3g\n3xVvCib7fR1cvomWgSytdURJen0euAze2ORmZgOlmJmdjqEbMKmHfNINfBKJXgtmvB0461fBYCQU\nZJ7nTHRvXpEYxP0C0quZ30RSteXdAEn/jYn4OSPCfWTuZ/lq0hDU1Mm2wHw6JDUtPVCZ459hwGow\n539OUidHrJUvPH8Ei7St+Vt40xRrzodnnz6SatqT5cPJz8gXdsFPbQJ9a0YfZIDdebGtH/DXIu/n\n5bqc+Vjr3pDSaEyesZO86ICVkTB/ZejHvpAjrolcgvPCyk07ya4a8kekuFlnCQIHWv2znmw3qcmj\nwSMzdcIz7eqFVuDbM0nxPixkWvDvI+A1zc1q5LwDeq4XfRtdswipW85oZucHugcgBfJ0ofK+SOUW\nWJHdmtRuzue0XjKcOkme06s1JOnLxUDxRFuZB56BkZshwkRpmOyMGEGmooYessOmSRATBuP4z/bg\np9aG1uaQN0HXwdTdb8aLtJjvRELu6LZIVZgxNkvJOph3+1PF+eb5B9EXWzDV3iKFObQzfDlF7ZES\naOVHpbDI3UMaVvvU1NKTDLyYPccD3nxMnd9RNSw/Lb+WaLlCyv2jmi4xJZL/pitm2323tYvCDg8p\nk/60ekxCN/AFcy5gIJ93hETzXXTFDeIRgagAXJlb0uQDOb3oELp2uSV2jcx115JBgXdV3LxmWDVE\npGPaw0yqZU2XgtxNLFn+8Zl/c2GxkAQyZRdTAAGlUpgOcMMuy37/GOsoYK9IpJ4aOIwBPSHEeb2T\nyZdRUhGwj3RLaL12Cavy6aVuFmAAf5S4dLyXIhXackVGq9IMfeWck6ezO7e6UsW1/FtkvAq2jhR5\nm3RzEdauBBIf1KqNADyegub/sEtjXdy5I4MoMY5yijV1I7HoSHuAYKQRSomsIGyZNWHIyjvKkDKS\nfF56WFuNq+Z3ChMZ5YexK11CGkHlLawKgZuBXxgUSGQC9pm0HbCLYdxskcREEIgcj1C8x1bvHfpu\nMAXwjkFIRzT0oE9iy9dudKke4psUdhn//YbqYBTWE+xrr9KoIqjwpjNgSF+/R4vMq/8bcTZ1dyYF\nB5cAYe04vtW+5dK97fALCyPQ1jeqLivq/i+nJuWn5CpafGEoAZ0ZZuo4SPweL7VvFDN4XrmO9Xel\nx62HaVCEU7BSjt9GtAxdn0Sr7KJACzb5HaBJfx+xgbKytM9wiNZuSv1bDdL3L/J3z2Tlm6tRxGc1\n6dAPQxEvvRvj2J/BUB9QWg62G/fiYi108frNqk8vrHugymJixDmkV90sSunyOTILegLfnfnB0EXM\n1V28jOiuxpU/Ni93COuEtEMqaxZSZtK2qHW583A/GdKyM8Fpsm0EdNFDYcjApEBETiVOOSX/YdZf\nUgfzHXkgIMHTkhX7vMXYio3oGJnRjK8wgjqFiQF2J+1QnnQn+i/ZAnvAl7IyexCG9t9Oguufkee3\nZAWM1LyFhNUFJQZC5sBPITBtzdc6qN7viu2TPmsiYRofiuP87Ut2qZDbt6LWIyUhZHJqSZirhc1f\nAPHxsOdJIevHcmYqFG7Vb+WoL3loX4nKiYJtEQK91bXEUc3sKmdmaTZr2UrqznpHrEDuOZLFi+Jz\nytweaLN2h5yrSGX/4OqMnFn0UpstlWcoOUBEqn4icb+j/skez69wf6iJQ+yX4TAJ8l8G7SS/en7z\nvs/fzx7A2IZMl3ZChpUNEkOnwDzXCVQF1l9pEwHrN6Cf3tjAVvLohrJkAHNvN8SAL6tL6Q4x2PmQ\nfZ5IZ05g4lyLaTyB5uPM9K2h0JyxqcA9fUnBsVH293yOhxOw4stHAmIyEz4zsHEdQNZ4mkwdYNuk\nepgNxu+ovT3///fheI+YkNjLBb7wMHZMVmgiPCkpMvbgEJy+VkGeSbrR0oeNTyJKRuCxvQOY43vl\nAj4Oxz/OjPNZt5alGPgedyi/EaCQh6uAmORPgL0oMLC8F57iy4p+9I362ZOUXe5R7dGFx8ZK8q10\nTiQrEHNDTpfbsiBmjvD/DITQEMoF1uEFRapgmFFmlfy9OY8RR2xBhlhubnLlgggNyO1VBZWbHsCF\n1UoqQjfqNQguvIgw7wvahPOqTyGqg5N+aQ5Wx17yTYTHSOVTIHMHNAg5X2xsYZf4Kdp4NSsEUvrA\nS83BPil1aKWD42bToiTmmLPuUlJ84CepdBv5uCmkRU9cEpif/6gUIM5Rp5VefRTnWIMumfbcPKsS\nEYqLENrwRkO7i5W54VU28UcDoHQEKGRQ9VoyLIiHIq6itGvpJagZkV5fyo3Goide1+ClTNuntkWs\nhu83hnpUuHX9B6GJa9w6tSdW9+Vudhh4oL3EhkkoO2aODEs1UbXlaUCT181gGJ7wSrUEt4mbdZEW\nv1cD3JahYbhL4oiH3yPAmoEYgLHOd+MqMSmygObJv/cUEdBDXTFQtKxLsqFxKioAOxL0ZPqsLI5z\nU86eByBDGsGVq2sHPKvjdZp0dq//ofw0Lunv47V7oRXz3ELuEUZ0l7Kzq3uVf7iucu9QJJxQsI2k\ncXgmTqeoSL2UXjnC5M++tJg9PEbhoUq/q9apI9MtmaxZ94lmQNLXdKdBo+2/zcnW4a42sEA2ClPW\nNHh3+wWXNdgV5BZp+PmYHosVTTLtDXkCHOXNPqI6I+WpE1WYU41fe/g8YxeBU6xFlnnOsJK1710t\n9PkaUKObmA/4AU9wGrtGQ93fR/yeKpgsuRlmg/tdmlh0LyXdkRWH/MnE/R1kIsIy8lWAMf/JXLnZ\nV2gVo7SvZwBfmBP9D5e/6QOfmSzFj5tE1mvLZFuVkYJnIerAJdXvVUOPqekncwabsTeALlARkW28\n6JaA778bU/w7tqQeNIhRneMWffu1RMTULex5xGjii4whQgsHb9khPHvVAlqeeMeLsMne34NYNX+1\n+pEWF0gT2oyQ+nJmuT7h+NSEumvN4qHS80KtIbKJ9HdYNWTFiVqlcF8E7nAUYENFYePz5vo2tw7d\nq150DdWobLRM1AXUImRZq6d8+xeVFTZFqp53YOxce53UKw3xsDCmC9ZyRGK+OEbsO3J7yZzEDWgR\niKWIgVW1yE5OL4Wx1GH1b4Q5ky0MKddh+5XP7ltosSz1yf0y17I1snIi2EMsc5QD9YqiNxa4w5L2\nnOvAeBfTiM7w7QExnyV8Sw9/B6iKSOQi3Ow646xhvXayuEvVFLpSvBo98gEKHH/6rlXl+KnT6VP/\nobiMzPEknYDcV/fVMDspHNoZZt37v4/jLufSsnR27bQjuFBTuf38EitHVPVKTRHqbomt9UqwQBIH\n/qAeQn7s+IjpQoPgve5HtiDHZjjPBYsf5xCCoGjaNcgPquwDBSw8oC4Li67kjvjvdNBvvm17PWhP\nvO9+XZywwHaVqeDxwZbpr0i0f4D5A6COB4LLS1P2p6YIsv2is4BhVhXwyR1hexAF4zfbpechx9Rc\nzymxssu0kJDqoeVkoDNgoCPWx3T0qBww4KK6L7mq6z2QjJx/o2e2s9Z/yRRlLXkNygr+y043iKry\nOmCuAqYskGn/PyHgQV4/yNrmDfFGCGxxO3LyE6/ZHqeux+TSbT/jEP5fbFaGcNuHJc8gFUvHHr/d\n7uGVTprdFimdUTFtVDPYfRdmUEHogT8Emk8nuArWcXaqeK1gYsCdNAaaSUAriEe0HQVuE6R/yKOM\nx2WNIEtVeyRq7Q8fVCjE36kU2nDmLwOV95+RW32g7/b7FdhQJgPAqHxj2ZovbQIhFbniPFQzE5JA\niykNoG9zNl6QN+rbCysDhF9wKuNzqv3ZoehD24cbISFmgwxJjHQx8UArJ3rOGw96B9fPLi3c+Ruc\n4u45kET7LHA2dVbBovJfYoY1+JIsKaxz4WIbqMj/qadud7qZ6ZNKd9uEfaFFZe4bd/N7yEZL2Hv2\nq1RNLWabUxFJppwgtvXiafzDYF6qXM461Huj3WRPR0y+rP5X2yEgyVhq7k2oPLw+UFtpdvoj3SMt\ncqE5DmSCXnwqXHjVqdWxWrtS3MooaxbwrbHp0y+RrMMKPt94XvZbovLRhgxvDgNCFKGrEtEOTBvs\nxWf4pwip//MaeoBKzRF7im/JtcvlJvhyITC6vp6xkXvuU1GN0v+mFTpSI1xlmY/Ro69Jkt4WvkeC\nUCFgksGFPtk+uYaPicdY6eCZqKStYHBjSp4ZYyTtRUW6hMML7Su1ABsR4COx717BLmlhIcV94g5V\nVrHMkRBJjKdgZ3MceE0Ze9xC8C13V1Gdr1h7MCuYins7sjMHg/pAnQ0JBQTSFOXMQjTP350fjvkd\nJw0P0XmpOW/dtxVtD8I5uzFD2Fcgx3SBd25hVjTNfLuxj1xaf+AcL4HS3elR7/zoO5teh6L8znZJ\nZxS15HK8oewOr1gawHA9qxdQtfk28lMTEuCENpkoBamIyS3ZaFdxOgPVu25qKA6shIqUeiomNatV\nixrDHyR34T8mTcyOPH/Hq+wJIBPXRtaSR7G9R39IZj4lxYpPFLUG7utvmlp122CMsPeaPbN7OI3s\nMp8R6qyb3OWOsAm1NUGUWogof/1/9ncNMZ2GwA09VVWsK+IOWkyKAgcWSn3g9AttjfpiaDrFXa8C\nUZvCdmPsHV7EKw/6HzD7VGuXxUEI5Qv4e3R+J+6c3N/rk/NWHJ5Ppi5y1gg9lO/ywk9YOrCTJihN\n84EiyU5MTr3ERsvIy2ueULQWlCeKvsn5iBr1/de6OEG0VbtNSYxp3i+7sOhkWIHcT1QsyaLUgPPP\nU17oN+f30I9lhBbytalBKHXPby6aRCFjxbaPrv45ADDzfRQf+0/VpHyslIHS+F862S4WvNdi5pvH\ninY6SkA/gqMMgwVesKzXSjIeannhZ/KN9JWQBdI7c2ndKqJeQE3tP0eFd3PcznMFCPkvQOMMyfNk\nym7v2trsS5q16F5ZRI/alxfP1dUFvw3l3OMoEs3LK2JzgEqbM9d7FjwCdOzZlOsSokpkkylQyMY0\nWQ+lZKjnvScYszxGJhq8DksTYNAGtm3EWTtCQsQaGEbehVYYfTQgNAG+lGti6oggryaFL/H0Eb52\nD9KeIr8gtQ0xdY8XveXIprA1ULpOkWR5B/FHmOcW5n7acuEfUcnE68LU+RQzqKwjbPsIvCCkk0SI\nLwTdXD/DR8G6hofdVcIZQ7z3uNwX4K3kYsIYewelidBlPvgiN0JPGphKEuPRdy3MMa2RhwKYz8Jr\n3AN0i5UiXu2jfzdWeiPVGZuwigsM5JF7DflekQIoh/OjqBBMulWj77cNpNW9dOWCHBsvzRQ5aX4Q\nLnuSQqcFS25REHFlV1TJiwtTXBqO8AEHSkUOGmv9GFf22nPldNQIPXoyBRsL/T7BgZJZq+ry2dNe\nqfTMg6PjATTfeszWF9Zz38PDdTX7AT6f3YOyg0o2ktG5g3u5SQAGknCL0lUN/p8RYuBeOZOCgzob\ncEXSCVbuT1Rmcuhr/3OfV+dN4nYHD28HrMzi6fmmFVQ8unFFYKWbBQptFTGv9qoVNHWrBTuMA7Oz\nLLgD5TjuWAH382+VphFWROYJeM2NTxryRpRbWFQEVixLiE09X61HYHTSOwCFTerWVhkAE3olxmE9\nkvvmSUOXKLiDUeB6/QSqeTFRkrMcphmcHqOoR3jnKfLSA3TDDbd7zsFIApHHxQjcOfMM3ZY9op1g\n+zr5vS4KtZmEQIzWxNdDtt9Ttk/8bFJLVQiS1lKjXYzmAq3QVghuJL80xcXfo9tr1eaTLvk5DctP\ngcKMUr2i8o4/P4jPLYngZBn1MaPIgALYbni06z7cU3v//NGP7k8w+z6saVNhbcsmVNwSOw5GniI1\nxoqaj/38ySE+3PqbER5ytyi1kExAZ5ZnjvEZQtPRoXYSJIf1hCCocakGJtHjimfnXkyC1tl2JZwy\n7ogQkvdAo03ujmxIKAR8Vooodz12D/Mf/0iH9u9tpZKm5OYnF6Axc1Hy52p7sspOjsgj4nuYOmWW\nj4FdaIiwqhDdVSE841aIguS38HH6VcOEcKk6fDXiD/wBw3LbTR8xaY/g+B8Yk7SYhBBOe0uz22LJ\n3y9I4eA2YW0CXIWZBOrDFAWPGaM/bF8/yKiZf0tA98bSheGUbZSaRUP/ctz1bhQ9OpkALijxT384\nLJBRwyTcjRjPCwQPWIP1ZO4uglEzkOTojMoz/3qIY9i2ifl5k3NaHEv91fn0bnSzvwyGLfrHMwDU\nOhzqavdQtW3kwC1Butx7J+8gA53983PUmpykM4Onzx3dp26m7CYElsKEdrZ263aCIQYwwX4piu4k\nsUTMQy0tznTDpJUw8iEyWKAbUwZVBLdioJuL77tvGqHXGvWK6gOOcXGHD+2a36086sin+TQ67PWr\ncRHbMcoNLWZrRuvppov6yHUITSlLqCf34PvLifUZUqygH1uM49DJQA7M9cAePkC30OyKv7fE/lit\nugvcX1vPL4u2afZaoHQASwvpyu6h2jClPkBCujXKUcT/hyHG6l2FnRQrNPT9exzPbznLTeTV98uN\n4apxh5a8DrTe9KpdH4BzYLuyXSrA53C3flrAzRHfakRM61IwhIH4gDi8Knv1WVkP2GVKtlQvGGoo\nQpHPyE741/DcixBA1eNDMWmw16l9jQghyN+9HEC9bNWlg1LLZXC1UnWP2ugAb0+WHjujmrgJ183Q\nhD8fvLdlkfRg/MT+1D3i0GGeV4dmYjn1RpYWGiaBpx21BWE11fDzO2Xw+hGcm1IIrX/KszMXOh+e\nZqPcb+YL269OJObh4daBfsmqSHsnKS2zGmgVs9J6kcZdFglb2N21RyUOo8y7wcAnvjUPPWJwZx9w\nRc5h2+rSdqBDnTageW3pLB2BZiFHEsQq7uMXOJK8RMj9ogX29OURw1cDrdBe7eYnwh1jm4ZtbbfU\nUzWl90pMa7wyDwfXQlGwuai+i+m6J42LXcrQHHexH0svJnzB9Wq/ITk+9HoJePUSALtWKLbix0iB\nbqVnvkDxSoe7bJaqRZScCq3GqUs1u2u4wOYETob8gcdeXK3LKXMcyXVAhpC92r8jroraAllbjIy8\n7OH8o/DFwQzhB2xMP0W4b5N0vUr/ScV9Ds1aPcUs3cQtYem7kfAcXkTqJPJctevyj2EyM6D9xnxd\nw+pY8SoXYgKYsA7OorOUVqqNpZ9byxe8kSK5FmFlDYKysVqBZkzol00klvDbn7Z1izCSSVUQRA9B\nXaRwW28NvE0Ohq5+uUUrEmRfGEnWHk62dLWDthf/r+cCikirQleYEGYINh3cCAxshlf8JtE6I0m0\n62lCvDWVexsgtdFWDJ3sfoUS32AFwIljxPtqiOhfRFAr8kUlvGaVK/buxOqlK42VdEhi2/gPz2Zh\nqrJZI9td618nOVdk/AoUvt0Ds7Gf9RDX2L4jdj6rBwQlhIS0aAl0tzI159FMSgOAztlv0IE7pkwN\n2FWvqlQjcC+PJi/1L8IcYRyveIvYwlVscXiPps085TTl9d+nZdcAhfTroBFdRJ/CCx6ppsagA/kB\n+WdXC5RJ+qxCzZrPc3738Zm3qSa2XBI6mr4jW5rDAFaHrkNSr7z4OMVpWT99hVWYUBDEYLHfsU7o\nZzb2uo3B9SZ9tEOqPkd9zT/q++R3Qxs0GTr3pflCuUKtPHcSdck0WOC/tx+eIILIYKjFBpWFxnxv\nWJW0FJlj1aGJCMjt/u7UPiozVKgJIM5Ut35Kk0bQN/h3Q5LOklendb06mfD1AMduW2HIBe2twcc9\nEQ2H49EP7ZkmfLbmq7y09OcWqsqEIFbRDCFr0yi2fJlj7gk2x0UVCqKsqd8ldscMnB9JDCSIWZF8\nhOtRlU5k4OXjLUw4gJ6laZ+yUOGMGUJrYYyobfbnnwrCh9p54tRwDOmA2Jo5/65khyYdnuL6+3+n\nyYAbIJ0DcGN1NLGTAh4bP4nDK3ovf/sliQgVuHEPOooXCRyxgU2yIzl1GVvsAlQih3KylJkS/ytc\nmkBfu/dp27RjHD3KPVU8Mb2wg2NNbXe7YADs5/RWMn3BNSCmV+0yTKtqqHqaARomx8P66Nl9jkBE\nlws/STkYrtORg+M2qwp7DIKbhr8LGRfRXHzXtN1Q6V1kaNmF4MX276wnrJ5k1irAtYYdi4i9blOo\n0l4aiDkh73BHh5GHnAbdacv/3d0UewZr0wCHNjWrm/F5iVzsw8Yq86zBpjqUHzqWfhrsaqjW0o74\n2prpnl8oAzMmgHEsWz2jg3P1ZkGW9kKDRe0wIAfEN8kuJngqOpe06tUqkvtj3d5kzGrNrTPBd1l3\nHLg1KWxl+CBMhJeevgutd0/R7wW5wnCq9HXpNZ3DKXHSY0grrQSfh81PoPEtN4l62/BZZRjkUpD5\nSYlQW4k8Vwd/OvkjVBkas3jQAW6i7Xdv6PIrCy1ESCIykEjH2hg9cjr72yX7uDS5ky3pEJcOc7LV\n+3yvbXJd9NN8hzszKPwwhDRb+HpKJxmXEnOBwzAV7w8f6vY0hLoDHg/uDjN80xIUtg/hkqwmyZ9x\n1XbncqI5cRl9ATW6YdSsK969QA3KClKbDHZd4mNwxDJaQVOLswiZiZa129lbYVgwLcv8c2juaQOR\nnBpSHlhJbWgVlqelPSVrSkYXsPm49lTUJ0KZ3FwgEmM2QA+yEXAPa320QUXJIStq1Ui3mKfKsIsU\n2x/4TcXFxDGUlMIzfV4ERLnjn2r3u/PSWJqOA7VoI+yM+iaJdkWJWJkVj5MuqwsF6xQU3+Srp2Go\n+3YibWE5LVqjXu6Wih11kYs1qmzL5A8+KLYsJY2HJCH5S36r1vWJJ69gSDT5jkxo3i3oxmpPlxy3\nMWjMhe3ImkCQhskOMSCHyG/4XJjqwBS2CqrExi9inb1vNmy2eNwJnSOZFmpXA5tI7gcBmI8wiIvs\nf0oflpQbAVw8OEcJ2onYNx9S6QmQE7Ae/LMm9xAYGUegxLX3kVU6PE3V2vQw4N8r5CB7prGh8vwp\nvzNO+xRO8n3yrsouaZFg4XcRFs8xaoECsnpDEpULzP9jpVK+AmQHCvS1ikxAi5Ie5FG3q2R39ZHK\nyvV+PKK1YBZNe/ihqPjP/MCx3DE512hbiHP8Or62Nylc6Lkeg0DtBm9+Zke2/Tc4feWKFZujAuCX\nHLQDQJ4AnWOmuunX8P0mR56J65o+d9nNyEgMJK/jIDpaxCQ7M7JjarfLI6yW1IPXoEEGOcu9p6Dl\nh9Xf2YyIDDnn7ELHXxNweZ6OWdK3a0wEr8YmFRQh2X75I01GDsmjLjQ1feL/c/z/+C3cGhBZF6mq\nasCsoYR0s0y7nXLis+3n29Icc5FyW5j4K6+AmkLH4foPlWzOsdD6SO85mXdwHsfuDKkuINhAKVuf\njybNwV4Kx/cj+0VAthVKtq+6TIEiyzR9iTGEuJjazevBNBF2x65ZWwqCODpe4/VIk70aJmNirXZU\nNTg/FK8pivk4ShbWwyUGvrcNanVWFEeLofZd4aQtQ3UCxlK98K3wx6x4u1RoEG3g1oXd3/fGRE8T\nwObrN7Mynf7tQ5t0S+do1U7KzNDkvGpg6u0cN9u79kcjuFyA8U4+449+Cu5QNgby2wojSrVra6A3\nEY4578Mi4UnkrpVSUEWyBfTHiN36bjJjKXh6pzEX+zHB1Otwc4RwtsfD7fzae1Tj0ZqIpijqdXGi\nAF5JESD2bQJlAsC3fil2xsqh7wmP147eTLgHDlb8cx8ttX7uyO1+sRfpgKvgZohDzjZ5xKdx6niQ\nTO9cbfTOng4K7yMtoWKtu6Z8R5b/o5HiaZSEPs2YgYZFIJLP7hF0S8aPhnAfZUAWrXXvS7iipMup\nREeRHXNmnDoifMJgpFOEqkdhYZjyAUvItPGD8ebqd39e1+MKOQY9QLfEcELZ4RN7bWdaag1+FLWX\n7CSCr90duL0tb4PKIqjTq9fuBUkoQFxpapdzi+SQ1bdq2lpylu2I1OFfFf4pRyJw3S3gt4jnzsi2\ny6foA45816Mvad52CF6ScpVmNxjI+enuER/jTykcCaEg3Mzh1oUKVZKayxNwgdNrI3iu1SYsyfDC\n9A4R4MmIvl+AWbKvDHYXoeaA2NVTwgF9IZ3GG32svG/d0K+JDyf3V2KD7DdDbAy8z5vME6zcCoIv\n3QzmEQca4fpa9C94MLvRfvf7G3kt4BMEdK9m4SILLKXUB+slgULzIykSEBREaMfawt6y53AHm19L\nnZLKTABcwRlCgW/XmqYErgqE2e4goJ2DseJpr8hNfr8xosGmfXbayKyV9jujd0jc3N1bUXcsm/QF\nkG0ftOvrKBKV9MV4tizKA/LKzQkcRGF1is9JD3fLVkqzA5VkkLMmW38TCqoMQ/71ANClChU3WWtN\njzYLNVBqcz+GTmynIdl04Zw1yb/3s7MdyGZo1AG1oQ3OFnRUa3fF7vp1SjXY7lBnvE6nHZGQNZfj\n7X35A9QWp77J+xbbn+GdIO/W6WgakHFHL9Qy6puzHPmq52YiERxq9AdP0ZELNGQUB31qStkp202N\nVHy5Q5L1lfjHGIHMP9LFYSJa0rsgHLwbVDNkUgQ2Jc80D8iJU7jBv9eeraL+2uTyDxgStTSEaVCb\nL2pLmM4P+a8/pudIvyl4UQvROA6yb4my1fyXj4Tx/V1nmkoXN3K7koQlLCLQpHqKecVjI3dnhS9I\nk7SdGoAB70Tvit9Njsl7Wryh+JajDvuwqF7mXatbbQSkuu/2ht1jQY7Y7umVEY6FvcMOs+Ajzuei\nYiPc3Fl+9/cicsGkx0q4vDa/rTLNZwdYkrHeIgm9/9utLESWWlzdSPHeKIe1R+yk1h3Q65mkV+5G\nTMNSyArsFe1y5vjMQ2KOh8ij3Y+ZqOfmqyPf9H8zvTnFRxFpebMOV21zIJAkahD1dx1Hp3+EYTLD\nvGBPdcC6Ut+59gn/BCgzt06984lFmV86mJP+P6ljkneT5Bem+mnWWHnwC8HDvZxx6oiLphc5xsnT\nuzrDZUr2gH0OaKYOGZUZbR6rI4JphW3ueNqW1U0eIpDEURjQn1BKhQma3AYCYn6Vygbw8r8/zulC\nj6bA9ryLquL4BDfzSUdvdOcpkcef9sDBHVtuXEERcOQKE7pxU+BWx1wxQZLFZsJvLCOU5WFjEzNf\n3xI6GRH4rJV9UXwkp9IXd5Zrk/1QnDu4clJyhK2qcdg101UE0dX4XYEgFCBLWuE3pY6ks7U4AN+3\nTw1bm3Dl2z1HR3k5v03VSPyaYAmHGxe2GaRL5oOJIoHpWrPFo6hSK6s5quLVXiKTfg7EBenMJWxK\nACGAMrAb8RC3OxdtaUKceEYMTOOOYUnoyh/hoQIkDvEwHpGWXi1fj8Rm8+0zMf106qgHO6m14ZnD\nNO/TurIYKR6v9oBxRR7jJoWUYrhSNr2J0xWkKZY47LnkPMrOIWVKr+i/fDP731CJ3FrZC997ZAXR\nMk6+5PhkUdX473ij9wzjhGKa8HONxTW97PDjcti1GBehL40aqGJrQbsGO/eSbxve9XC+ACxMkG1h\neHMqzsVjaae4H6yn37zJIv9Z9QuRKrWQ8FG67j53YJUc1oaR4anzsXWRe4sbGI453ewdIVPQXZxs\nG0O/e8Dj8Z5qaryvDTWHbGRRHBmvd7oJfX88ab5mZvO/b8xy+bGkxzPHVDx8C0cyDxvWuxQHvr1W\nmHADFBfOyin7N+/HiTksz43+aWh70QnFw+CkE1OUe0nG+15xh0k8LujfQ2hen9p1uA4QHwcvwMxe\nK6roextXt56looqksSAssb9GCmKCy70yVZqb8wdlEz7KuhMO53EQOL45BSotNJjk8wDJ9awBlhAI\nHEmH2Hd8SnSXQYcks4esZyPxRDCGAKznTvvurbYb61K/C6BDLzLcccITaHg2syhbX+ArI1PfZq5g\njWYB4iIpE1E1OaKHREKsPxGGdzo8hXAivzXfYhXalhKIKp7FLjj3HRHHbuHROla16ThnTg1prc+o\ndiQj3VqQoXjTgpXMRFxzx2QSnEVAUAHCBE7xX5/BkiYXbgzViLKuhORdud9vk6GJOD6EXAztjRJb\n8L+JZgyRPZi1h2laFk+J3FQ2Swxi4oxAvyWSc6dQTsUGYaj1AyNhpjMpAkojkD089lsSvR9/Tloe\n09UwYuuxBCclZq+Cvq95oRMEZyNR5LAczDjvJRgW3spMU//a7sn4GUNyasMFgydNHZtfw2K4cbYj\n0un2+Syqh7J9LOuvGhjkkuBmT+aFU3K2gwvODHhSm6M4LJxJrIwbU3BqQtC5hdCmuuRdFGS8SfQw\nFR5acBdZQfaTO7U7n2430DhRVMLQp80ephNJ55BtkQlQhKqrzjUN/x54nh+piJjqNQ6oBIfYWcvr\n0T5+jRo3R5v4UsgW3GPNbHrZHNs1tpnBTjLzmTYxuyOlPqmmWbkWN6SaDyJhnIxpQmK5A5qFqs6C\nL+27HrqkfW8optY2/QBRvgk57w4tjUKDdRVD3Ysvtb45NsXWPgUoY7cyr8IrCBlMaluyga144EHE\ngmZLOtG7aqQv+TyXqtg5SAPRut4kY/Mi3iaqW/u15fzV/Y5RfOmkcAPtwR7RgrGE57fTs0cCk1sd\nx7QhcSSTxpGJZhKmZV1bXPeX/LA7ZCGR/N9kx6G8dU2E2PjFnuohINrdniQbNitFJGSyiQcS0tQf\nTnwnjCpenlnw+voTL8SHr6BHgnNJ6V/r+IxMZ51pZXh5xa8TildOLnRfxKERrAH2vVbGSEnSFvCv\nQHTe8gckoPvCVTMDzcMQbbW6wZMtrqucFBdFaB0bphMx46n5UrYTdlmb64IBVQoxjSutIJL5sP7F\nlgEGS5cxL2qffa2ct7VvxEgKC/nHmrwmwByXu4pgFH0Mt/cI5t6YzLIfwAfXkLS55qTQzTD6Cza1\n68E2Wi/5+bBNOqX/2EKDTNDMcfP32GMPE6xol3/wCuQ6HJ/ayFFf4q8dVfktUP6enciQfMIkEUeT\n70GdejZbvzyxuJIhsCymAcMK2PP+wXIY3fNBkhLg03ONZyldxeMj+X24KUQCmQMX2SwCTQYN8Xzr\ni/zO44CU6sMrshHXLFYy0mI/PCbrWsX3sgPXVkncjX94K4RPapz290o2dhZJfblcnW3EExHFsEFW\nkmiBPcdj1FJncDw4zCk/30Lg1Gicsnnoqs9KBr1JYfIcIsliQJpqJePTT0atMRQFPIgh4ZyLv1H6\nVlsix2InQ+E+FcMvCLAjHjwSIJkSPEOCB+byVknODy86t61i3AihWwg//zpS4cDOJgeNaJMQyaGJ\nc2LFYP5d+Gm6/fa0icmad1GzDdX3/hS5Td52aD0AmkL+X+dpvZZNjLakPobeWj/TQ81CIHssomGK\nIN0lZi663RMWnHqxxi3+d7QcwwDWzmWudm0mPsiAmwXT+fJUeJBl7YosTD+C16X5SLeV3YR5WxZu\nyVDKqV6iqu5gwmeuMQyNge3ZYd9ZgZB/UfNAOx1nuo0YXEV0hiy334Ci8krJkyW5u2g8sonPKSpA\n/ZTGWgrs0esOajR53p2CR4j/MGZrR7MpoXLkRlPPbQs5Io9defXKyh3PbldIL5GJvNRQpjEb/fKl\n0PgJE0D1n6r7f78Q0q2iC4Jt5Tf3qoGZBYs5OUzbQKtczPvZdKmM6DRQ2EsZyUaF9Te5tG9/xbjV\ngoYdRWnbRL0raYjaSWON+2VYDeyEYdZBV323UX05T7gYjP9FrWvUfbu0CjaDlbvw4r2yKURq4reO\nFLqrXqHRj82saV8rsKjqMz+DKRckcgzs3I2ZhjaLgxoatmKApx3rOgg0Z/hX64UqqMHlJhEwcjNT\nGileia2mUz2ijwIUswrBj+FEf4hndCNXH6wcztdsIBIShzmHJqy5L2xdVPHXMS8ldzpWMQRQlAnL\n6EwZret2rYSHR7of2CemYCf2+hCnetPCgAbzbRUNeXh8DPNrBHE2blwPCoUS8dg1iJHc5P68h23g\nFjKiQ26rPEd0OzmZE4xZq9RmKj9n0iDLz3mZFMADVz6RtlvuiKQP0RmTOgAjSQPr40I1f2XDLMnU\nz9Fo4eEBegAZxzFBz4+q5gASWXC0aogh26xHPd6clgdni2MrIWlL9O86KEdsbTdCyrXs08qx5v8q\nDQIKSYEu5hIUv9z0MT45LkplwtSTEGPDdU/TKW/9Y1GDrC0wUDqXYUj0lsKD0OtJjDD38a+N0JST\nFR0C09kuCAYwMY6nlHM0Y9vQ48FkJxI5pN2EOGKgx5XXnHLixZWZEzfbZ4HkM7+9mVhudWrvgZ48\n9+gwR1yk6NIaKelWrV+TgELuw7L2UEz4Lu0r4/zHj4u5hfzM7+gcNwpbp1Khb7QV7BKljT0OIqQ1\nIBIoWgMwc0PxUvjoKcIAZXBnmCDw6+Ao46gFi694s+13fJq6L7GQJKyWFoplnrAWxBSnjiZZFWm1\n+bWGOF0wdTTDpEPK0grFOkJSxGaJnAxLvRI4sMSIK3rkfNdQiYvb5Qt3sqAEkk85JNXlrOJwdhtj\nhtuJIPmBKqrnP9MQM10dSZdEu+lylOTbYrQvYVBdYgUzYREdw6E1mL0DCxuMThE/sU2Dpz3XwwJy\nlZnOCn9VMH7baKzZfBuXD+42652kLf5EabcnDCVqqZN/TEtDFcMD95CBrqRKb8SxdSS1RVYpfyFf\nM51kqvSQZL9hGFGVVEIfSJcvBzyt+Uxd41+ISQkKCKdl6kAge054hr5AbYJ/uHsy5OkSIw+ZvfU0\nQU7Q48wDqHeRhMF4pt4zYtQGpW+eLZsfekojvBHiMCRYWT40t+ZuXXauSCCgcpXPpn+kyF35zi09\nmRoXbdR1aA9h+qaysIRaLSg8vHKukbIoNXBOWh+5WxFcRttWxGyChcBDpHB9hxpGMJLKMpA44D5R\nz5ws0PNWWFHfmnP5yrElUL0kJXvvpCgV5zZtbOiFlq+Ohq7kxJj8U414TTntSOmQFBNYiCAHChjP\n2wmE8q/WGaOnllHFzuENYuDQo3jOgyLsxnlW5vHrcG4cXZqaEqOHWx5EnzPrOfDQqvmoXzf1sev5\nzi6R+w7Jq9Fi4V8zyh2/i/JpejCjmDwPAwgqm9X7UXglLoYRkHLP8MD8cDXBGK+a09S99bsTcVXd\n7G22AMPegHhl5N41amjbdHq0PVU7WJmhWgaReebFzV/ZtOF4XIdO0Z+Jlll7WVl4i1PcGjhLOVB1\nnEGEvxd/tb06pb9IEtEoMZZMh1JB75eSd3DL/XaAh7IxwTQWNGVeG9A41N7v/Nm/02YsBOInttuE\nBHwjECiorS3FlsmhHRACpHsitW/e7mISXcn1BmlTJd1z08Xfse3m4m+YXBAPMXYh9lt8foIYJ5GK\nbBOkQe6uK909XPKsPb9QeVYHyUYSkzFHn4pK+c/hKbfFiCMhxSbJN3t90EopRGWvvkCWxehV11H9\nSVq7PsI+NZ1rg39R+fTqARlz0eoQ1kpUQ9ld/FLsGqnVDLzfsc6Ni5nAwCMVcl3OGJhPcbDowMrR\nyqTS+jFtPR+9RLwgqGdijF5hG0nfxGfO7eQBep4MOo8z4Ib9QGlcdrv2K1S2GgfnVxw2+XbqlDBI\n3A/XOFqYEp6B7tGA1NDfH+qCdsaHGujhP6qD+69bPrwtFAQZEdVaLpTEtXFUOHKFQzY8Cwybryti\nnqEKuWUAi92Qq4Z/+iCQQnxBKQ7+FvA1HsP9fIykgKOQ4RuUEp8i8XdypGQI3glEsXgEo0qDdtlh\n+aF58i6rBWwe5ZAOyOKqCafxiFFMgU0lSzoxljfSTYN+N3sS6RVJh4xspacIhELAnhTbYjnignI/\nBe8XEA7yCBVWaQnrG/nZkj9DQYxaHWtYWaTYkxw0CMQAJT5Fr2xpaopa6oJcyNlKxdO6ts7vj33L\nQ2BhXQ9OZQLUxN6HisvFhlNGBl7E3EuJA9pKBPQ4TGEh+gBIV/IWoAPeCLRGoOrebtXxFimQXnZO\nlBn09ytjCHA1qxaZvoFAJM9bi3bI5T/JEIURiBN9ECrxVxd1raJO8g5BnbjcGbLReR28vR7Hfdio\nvfVgQY7OSdPt8B2spJCL2nIfoSswtaf/sN4UVIZVPsCGuPsdSnFq9+NVtYxAeAAj558FfPA/prpY\nT4vXKNwp5TB4nV6orJOUulEGIt639jpm3OWevcxkcmlaN+qCk2Rk5GjShiE5/JRUZraau1dxaTXE\n02mDqOXbB2d9A9XmJclSE/MhkYZGp1KUEznwjMuXXANv3fxXS1QtaNFCo56sb8/GkBK6haC6jU0U\nGKe/tgj+hnaHaGAIyxvNpp63ujeIKxA/ueukfHa0oR3ZVNuCF+BQnyjtx8OA1PUA1UWXCTKcTga2\nGpBucEP67k6wMzgm/hzSsTFmWZ4ic6QKlwRO19RtzILavOo3LlgWZ0I2LAxfbH8GO5HV4dnlCvKg\nbHwSsa/vSSR46JbiqiXzn6LPeO0ruV+yHW7uuUB3LUvVDoUtQeLcDSn6h4nBEnlKAGtk1KBwlyjM\nhvTRtzOSCCzmqd7f+3LbU288mTMyB/teuXl8G3m/6eQ7MZVk+OFtCeVp0hvr7yAKHkV2OYTIJ3Rx\npqYE7oE8b0xbKwLsNNE0V3/uBApEn8l6iUZKbdW3CGTMdXti40qQB6X10HzjfGeVBZ8CO5SnPudH\nJOwMCTHX92e+UTSgpXHoCk2rV4DEl4zNQDJAbqKCJnkqmr6y+jmZdWXxxoXpLVROv3g6WYKt2sOq\n0sIkRfiWREAymh/F7cs7pb02nChja7+yt4ykaZeHbEa02sUqywAmY/34gU5+1L4CmtLMyzaYqxYO\nGuy9NlpiUkfZwqLa06k6w417m3UWmna34Ih+wg9KYxGBFpQw1pQicSLjyrhP5H11rTNNsnegLO98\nFJgIWQsFkQofdzwETkWGXjL85yS5gTvtQZF9YfCBK3I5bpP8f0kO827jVCH2rmBtQLA4o3yfOEr9\nyMW5/PtwNomzsn7WraLHwBhMBdY5Vp+BBa7vonxObMP1YF9Nj91Z85aalPv/4BLjNydehX3+bX0Y\nR4olY6jNL+4+gE/eFPpGkVosYyQBM/VWuA9uu8z0CSJjRsMgLpx4dmIb0zV3bNiWFDW77F1uxrcA\nm96yz8vd9Z2qEObCh5YwTNNqM7pMVYC/yWUVwWCWzfC12g8N+abBXl04R/Q2xdYMbImXw8bOWftS\na2+XEdkQXAL4JnMgg2gnXlO+P1u1lBY5jZ3pdUopHtIpX6bmFIfZIIFBgUf7MXpGaa0Pa+pWi+wh\nw5W4nuPPBAvDVNOJwj5CQoRGkgmvoRl6uGT+XtD/sV0ob7eDcnwSZCEwl/0gNPbtLs9rpg+kJBnq\nhcfIPxwvJLFF4P3oit0C+110iUZUe9c7IqwMO+rBv2yTNohjiPpwd96OH67V40QSk3UuNRBtY926\nvS7Kj9RQNboNoXtOwWkJigvbCGI4zc2PPXhzpyZcnzjo7db2NIcl2iUCSdtXd/tm79P7p2kE/HIh\nXj0Sr/6PrZNmmAJhgzl7khzXoxxeqBZZOA3AqSvps4dVQ6wjNkuAervUcTPN0ltz7998PPVzNW96\ngxDrwH2lYBJWUYAk0GWsVc5akM9zzzG0CKMBXtqmF2jcuIsVhRZC57DZKvecXqRFi2O0J0mvlMqB\nrn+CmpAterh2vjcelO83imvbM0SP1lDovAAcztrNXyk4z1Jdg4l5l2dBUJ6k58GAojZsRoKYaSby\nYtd4SMZUBA6UFjUiU5AkUjtlcib5jY6H0V7RAdIlMH3wEl79JtjAM1IB3fKFFC7oBZ6nUzeZ3tPz\n5ETkXAdb0ABUS8qVb2JZzkbAHYObFQR0+sAT0Hk3MQSYqPNyForXTjh2QtvcbTVisZfomj4dSkGH\n++ldwN+b9hLENpSOybTdlEzV7LZpDZtiOHnR2DnyX22/GvTS/KLDTgi+VC9xf3R9yQ8y2dlNuEag\nA1uckEmWu4u6AfsbQiYIGEQQwhL2GMJ87z3jlVVdbcKkv4qwzGkAVWJVS4467Y8IoKGpVkiIDxd0\nQ13OuIdxSHnBJ/XlOCBszlaoD4TefTCuXEqdF4baglhymuX9oIiYMWXszZSt5Gwd3D0XJ2FnJb4r\nMkPv/xHoAuRgP0VCKNgvAsUlm2dfD8dt5otkZ1w6lO1pZX3Pe2DUulazUoAHQy44x99sH0dws9Y+\n/REhKNwe07g7ytbMPpts80cNvO3LudB1cgm0+wU/ldaHGlDO8ag4iYICB3H9zhNLldkrSmgD3I8n\nwj/fhyZmNl002gbX1R1b36eOBeuGrKGtFgvhdl1H3eXo26/lnvzQAKqXNSCpq6YuzR2UbsHt5vwO\n0B8y1nzI7TQ85ZCxgFgfiWx+8/ITvAeUbi1Mh6qn2Pq16Wd6jBQGQnb+BqhdayYXa2ysTyvq8Hql\nAlaxm2zO/BNllr+jd1I1YZl+CpxBgXb+qCmn79nyzrFAhQ++PAwaNWmZOB1NFZReUON1giSV4OpM\natCF1/PqTNkfzHnx3wmfy9Omyz9dWPB8F85IUHpIkYKJZ2SaHv4m1E5RLi83cWnzPDADTniATRtw\nIFuGodaEAC3EsDsq/OMu7nh3eG9lxEmg7Hg9EahDVr2MM6giWJCpFPLNAnZ+ven+y8AYgwh31Cmz\nvKrpqaOT2mdtREi8QGPT5qKsggt7NOd7ffy3+8KyrwxTz30KyU+Pe1hxLr3FCn96OwzSu6ZH3hyg\niMNBVBCMq8ANK33BPVayi8PFfNkAdNCtxA3JKSdM1PnuGrqOi6R1eF/hGn447OpFPhGT0vRlyMDs\nKYLVcJmFCQVCSt9zlH99wnrBpyzylt+znRnHJb0eyNKqk8BTwIAWIlZ089eLQXRS78hlpnuTNkcP\nvYhBcMe0zm/1AEpqqznJ4bXtAUjNkc126tHT0e0CldGdD4ZXWCLqdACFHf/1rWaabY5+xFzY1Tjc\noJInLzAcv4r5JflelDLQ7QJHl96QD3bG+axNrRe8etVupQKeyssdUja7/JVcRFi1GsoYjGkZnV9R\nFGiARl0X6PLVR4nxhEfhf4r2iXgIlQM478l7mQdXxsxrYzK4VCQVmbpBOmalGGV3dnHQ3VaOyjGX\n42eOt0I2EaRmUZMHAFE7wCXVNlhlYjTL98bzQ9C/Ji5Iu92mxtAIQsZIiwBGD7gW5yHjkDuHTLJa\nuVqRAwVQKWEFUmyQelU3Na2yizo4iw/N1FfHLF27A/vYktN/EBVFHfzQ6ERJMgmhFqususEFqtVA\nPTwkM4XEI7deLcIkF6IvpAZgudHq/1X0Z7gnc3p1i4/jgtkZoAf97dTZ3eek6+6HBqE9uKdmWr92\nSyZJCXJvul6YT2LsN8HuSGuRGwlIM03PH2zZZpQ5pBo3S/nHKeFB41uM2rSdn39oS46ksS09zg/e\n6c5XvOq4dPlEEdhbx5lLZztcZsGuNa97AOjev0oPuR7FY9Nd/zeGePiFxHSW8KGdwFKkmniIyDf7\nUBw4eGMj055F8UA5PIRF+gtzR915wCMb4DWSm+Rrc3iIEqHs3wYUjTHbyrkHMOU7AbC09oPXKTbr\nX39eJKEC6h6CVh9szAvTBniL4qLIfiiaKnBsRYHUcXT6NF2HS6SkRhEFpW2S6UPM99OAWqTiYkkM\nwZFTXdXoiT/hVgnK3UOG+pFnIn1hAqEVPAxOH29BJTo46GmGNs+JBv2DbcGRGSjPbz0UjsEMpbNo\nJ/Q75LE3bt6K/65KRPQOQIwmxLVhiaQdLqG2r3Wn8JKWm+LdB0+U6vEuywBH9b6i8P1izNXJR8Au\nbKsp3aZJ5v8miQ7wVhE4lvtv5C6AicCHAerRr9kSDPWv7dL1KiXf65vOFAWkN9HRsY1VdD4InQnR\nTX7YUAef+X2ok5ekw7eEGgjHL7jKoXzP9MN/JEMtq84iMBOi9FHa4q071W+sKPoxcwDZRaN+4xyx\n16Z+gvKq3MbuU3BCtDIeP71sZdc3r5yhh4PTNy8d/70jeiZ7q4wph6l/CX6IGklwk/C/VDROlQKA\nkgnjeyIdxiMvYK4HUskmxVu32t/VviyxUqGlXAvOv1LqdOb+F/uFiF8hAj4byv/2SFz76JVLf3Kv\nrKI3Ea71/JRg+ia8pu6U3ebhCsywjzgWiIlknCNbG9Vl5XebFzqMRfW5PGNVwNQZnmWTgwavINim\n0p9ve9DyishpL4bgkY/MElhJ7CtnFRCRbF4uUR2pxLTWZqwjryBfGg5cdOqWc+jcEJsz1G1UoDL9\nmiKFC7XMzeCHLcFJl6u4hvGhH8YS/nCmcHYa6TbRN3vAkOjm9Dv5YZ3dptgOduzMGuUbKbbktVSn\nwo6hTwjd4pAXL/fnBmhNeoq/OQvcXmry4vHcG3/3kunTur3bHRywXIwzcDJDY0kNxG/V0U65Fgln\not+rcTxp/89VVfbEc/8aRH7N7rc4Sct7P6+mR+Vc22ZcfuEolNJrjMeWW4okjWdmfnJlmlXy7tVd\nQyqI7vCzb119pshOX2L24LmlmpUYxgqRnJvN0YRpHdFSBu3LJdij0gZp7ORITxU6WTP1Y43Ll3pp\npqTyHsanc4aKtfUkiZDTv7E2U80Dhru3M6E8I81cb96RGPVX4YWKd5+G4IWroadMRHlAFQf2v7gb\n19/733XRLfnAqsMcca6Bsr2rBVk6SkJz+FG7qVoRdSPnNpplzJsWMOWXUA0khPBUzx30tgic6q7L\nSH5NlUrUv6xOWCWTLayC3RcTk1yKp7bbttXH7WJYgeaSLK3s9c0To24fHRpap8cc2I+5FlyFlXA8\nsx24yjap5KEOn8u17aB6jQfZefJPnKzIP7Jq7aiLkufm7S2tmPmR1LWE06pwfWB38dpUkRpHFpWs\nKUJzQlIbsHrGO9NCIxh4TEuFIpSQG6N0uOYMQz31DgtL8EVMMI1OpktcwQJqU/7rCIXhbb4BhW7G\nbN5ix+OF+YI1CY6ZPeJqRTN23mQ0fuRdrrK5ZLvSl1wlTHNT9sd/Wr+rWptx2QIsyx/b3MTzXkYG\nRFBpCeIjzf2dTbEoI7lC1NvemAAFpLCbFOSF3vr5BGMWB0ly6h4MbsBq585J9ZCJWmr9DdyOHaqg\nh3g1d7sOXs1OIaaKxL1dD0xxqdezLMdVgmjJhXBLY7bD2XpEz9u2mVcCtdNX2aZT6TES6BaSjDcL\nD71fl5eFcfLcKQ4Dm5cJOkri3BcT+LMCtOelNAAMXoestW89lb6cn7u0QSKHMtpqIcqpOvEue3y3\npPGw+GJqfqJ+E6dZVSCnBa4c8FbIqDHFIaDl0gYRt0MZ7W5FvorfhuOMRP/m0PZFNAjDGAHGTJti\nTpXX4DusTTSyUp/SjpteOETK6gNr7XyvR5naZGe11ZyidmW4M0+hQCF4Ml8GQ3P/Ko/xc6CfUjFU\n1hrO4Y/YumoZdwr9J3LjtP/S6gEOTtT9Z9r203xsfagYkIEyFojbzz/QgKZy/hzuSwCzpUUS7GLZ\nrjLIP6i3MJQvBkHApihMKtXWUJf9Mllm3ml79Hd3px1EyxAifyJSUBx9rxvVwucqsO2HQBn+IZ/b\nl56Abhwc/wfR+KY/qZzs3xyy9NB88i4fo+bveV90TMHKT8/FSXjtjKYrTMSjdICvV7/YayHSIM39\nO0huk+X1aZP/JVtIdtppV5vV//SEnqL8CZJIXxSJOVkO/dEE76O2cjvzqETl9lEnmHGD/+n0oiET\nYvNqDZhEHfwkbFCdyb7/P+nDnk5qI0ZRpZVbquxK9DUzY3ZYQ5KcHN17X2hBY7ue70tLCbOzZU5s\nvCAGCYPYLPbqCvyIjLBC1wWZmyCEdPTEbDFYAiB9AtuGwcIBzKxHCtfN8b5LU0jVpQJohMHJmJCY\n5vRyQx/1f0Dv8HNOIFZ2NTmfVxQFWPHWXmy48qhchfPOkFAHs0eeY+f7hjdGjpcNVVwFhOrRaluN\naBsphhdzJ6RUgzVuN9MfcMOFiXIvhywFI9zlFMOjoynI9lt3jZyaKJ5s+WR/cTzDja9wCwmoanEW\nk2jSJjwQOMDVI25uwO92suegNMpCqCBb7wM+1bF30I/8O/ICPVZtx4lTpXvQAe8RqcW5U/fOPn07\nEgl3DPPF/qs659Jm+Kvs7TX0k6bG0Zhvzd+JV83nOjv8tMfvLB+NHrXpJysEyxIGiDBfG1W3bldA\nPe13O8V6RrmWoarZlR8lv+IfjOvQn9SKffYABK+U84AexxcxA6p5zLS2SkVTMe2xVXlVrsoIxBdt\nrUHNU9lsib8BIeegB4T2/7dqKoARVmsO20DNuj+m1evDRlDoECpu2Kt9hh0+uBAP2CE9Oerd5e0o\nEUtY5vBN7NXIr4zeVlzz1/W9pFKAhml4VnUp7rA2RdnxRSrBo5gZFFDiersm/lfTNiWXLtOEIssM\npppg+6NzNHYe2QPqJrQecFFbF6ViHfVY7uEGs80wBlZo8DBO5VLNP5z8pTgeghoRMn38EJSLy5h3\nv9WuwuqBORNacXkRFFjO4qsVrHMrJH6O0I8YkSGlNjHNoooMQziPOeKw+1OwtE2CjdwpSqWHtyP3\njQH0V1ckRbj9FDQPBu7ivbQOynLrJiSnGljdQW/V1PlED6QcT1XOdnUX+6FWvkGAt6yfdYr8+0Rd\nFNuWVUTKCaOjShBj2Q2chWUOyhOien60EloJsazGSU7EBHDC5AF0JT8teSKQZoGEM/lyWfhVHUZ0\nxOMQSWLCQo+BQDEWngCss4mqKS7+OozTaDR6MpUIZwSb5qAglOsSUkpR+I0dLhv0xsxaCtfQHlJw\nduv/fDVawyXW1RX+n/KypbAZOnNL5Po15gd4vPbddwzrO0K4wz5CZ/2PyJKoPxQ7Mq0Xr5p1/LFJ\nkCdXJ1X+Rr49KXycHRY9ufrbwhg/4GIfrt5xtytF9nRZBr2SH6/XnjxJoeCkBALtsegVoirNk8Bz\nW5tgzT1TTcn8aCw1A2P9/h5HUtrag9Zm8xOz1Dj3Q5LUv32IhDtfCXGRmopcnZiRLL7NG44ifaRX\nVHJmlznozGJD4GpG56APGlneUmDSX2nB6vz8SgL1CRoBpiF6a5qz985Zd6Mnvc5w3FJlgW+msF4l\n78aGB27abjSHo2AVssRWK8inbOKzbPH6eFlDCNp8LfnPWmyFI72xbSDT4DQu4pEMDudRlQUFuOie\nW6b4mf3Gmy5Vai7faJsH33gc+qDRDrnU9KzvWNuLrakkDIcN66nXaXbfLoB9kQpvmKCarJu7vrvZ\n2pxZ3NDgd/UtdtS3TxvDWWcDBWp3Vhv2zqeNiReA1vNZOLJY4MtQbAXfnUgojUsZAHODHKEbmrgS\noKaaSpChYvF4sKAjyws6jPvWfKakh+xYPo41nhBH6ixyMpNlbigyE2xKs9+N+2BavI/w2xPhrDFl\nW48sXrVlwfkQzzGTpSWUxXCHGLwlnHhGjNncVuvLRyvqd/PxQB7VnOWNevK7Kd7dtPHSGAtbcuo8\nhLfXszuk8finXELf9L6Orbv3uOWALRDZLo9eNmurt2gGy/01qPNeia+O9hgrc8Fjhf6qp0/fWOGi\nESGHBVaPDo5wtNBvYBv+740md+wJJYFJDEkmieenQjy86sVUTAl20+QTeLrcZPSZK/wqB+I7+RW9\nUC1Va1kkpGctjlcb+ILdMPOhYWGSKUUbQ36l3IuY2AP+s0hs15dNQRJn8pNj/PYhIOjkhLathCHz\nqt7xXO1xeUgetO4OZzZQpf3kj1eJ51rFI8dbAqBDRVYuniGkYjSI1iu0OoNYV+6V+KaUFcvt8uUC\n4mw2qALBl+8EReEk52xIme4FtLPzUDCNO/UGM+wRdiWtj9790fPUxeyn2acP4VB6VnC6PUdUnpr0\n9CtRVOq9ZTAgWonY/BvvJhAjCewpt0aPICmdxcPicJpTV4jFQfRA5QWAYxt1QsaYc45jmfD+TKYt\nKP1D62YsgpfeB442GySAEV01KNif2cytc6BJmlvxTnQbRoKJ5Y9Bk56yVWfXbYxpEgCStB7WAae6\nr4df/NBUQSUIb3B7PcdmZwxkhTFsCC5ly1f1/jTPPftUNi6dpbPQpe1ME6DLK4hiYYT50I+IJF6c\njXTudq6CtchzeAqtjxSwGBxW1uR9Y5WcGRaHtGvUrKDUzAD3ycCtXg7mSFuP8W3cahtd0POAGmCX\nv4dAn2DePQm6d68O2nGGYJKpewwrPwxpc5BALkWp4+q4EB3zn2VBJtAA1zoDTJ88QcFWmp64y3aR\nHSyI9IADRGokppHaL6crCBaV3zk34nBTv86rxwWO8MTp8EQdTx0wRAda8ROgixK0jw5A5H7eAtGN\nF4Gyf5BBPs5Zh22TCBStErj4Qaj4H/941jHkGdYXcy6Bva6BIRym4ocUqB62AJnOekqkM0QmZZcE\nOBWDvAJFqD67BYdt42uQ/8ZEIev5hFRpO+bfizUMMyMeMmD73VKtMd9sYWgUEys1Yc3YtuCUKc1t\nQM4jtNzYvMPQvt1FeqkUIftdOzqYRMBZZwMDq4jvM/GJd8dvT+jNdM37qLsAqb5gNpbKHGg6AHbi\n9wXjDvG7eLq8Sdl9WlIZqkOBSmBt7Ikqni43GqiEzZmpMsXEuKIq+jZrGMHP5WvJETcDP0oigKUF\nmLLQGmWeD7tqs3fme8NY/7FUfZGeZEsWx83Fgyz/+eXqg2TXnltiNlwoQOZ8XD3XQomEWaQYJeod\nbgFXnETaenyAeaKPOxrQ7DQ801YjoNhWEAMrodY7mw4C76RtigV9mJOp5H2CWe5qexapH29b0e4z\n1hR1S3F1JGMzs/c2t5KqmkPFyUNmVp7UHOnQXnfSRGFY4m1+QSnq8DWPPZOEXk1/oaC32xQa6niJ\n2L9awWVbagCBIUsw+sd4aDe0tLIxvixhOacoLP8pac+Vj/D+62TLLzpSCNL6guLv8R24mM6pnqy0\nOMZmVPsfJviMKiCJl7SWIqf2iW62AbpMspNY3rB3qZpzVxj3Nj22gw7osU6rcNJSgIhVdSYI/C+t\n4Nf/2vtGtoP/MVxvuUyxWDRAiN68StckJnKtuDVrH6C7wRHe8JY4FhsB96DC3Xfy6tFZhQAOU8gF\nb15TsLIc6BNCpypM9RPUDvkq+lN8cdB24dfrkjbXjgnDILaTiqndu6DoPYuSvg6u8MWCIvufsJZi\nivqIvUnTbrUkppsOPTGM0p/CA0Fgz5z71kvtU85/YsmUFDPb9a/R8uNeUPIO4jBmUBmwcBPzdzOs\nqAa2DX5ym5NNdAc0aP9Jtxg1ZluqZDX7rwUAOfRX1scMLQviqC/fQkOeJ3CZqm3uFa3L0U4MAzRc\nAfeZyh9Nuf8D47MOXqdkrbQzYrxdScYrYWrh86i6C/VKFUenUuRPZ4lr/BEdvcusoPjgpFAAuWRz\n1xyF7u3nBQfGC4ADRP0Hs3F0M+yD1gF4dGcR2HrJmSCRA28O6MUiWiClPir0WbZEScOEgAoN63jo\nFmmjYDF37OxLVvjFYK3tl2vXn54EGi6/axVXsLJl/VOI/AWexGvw1rN3T5VWT5XM1qd+gOpnn+7N\nwD1SwPXHPLh7j+5eg1S1ZX/KotYy8RNYvurSBebw+wz4qOULZac+CCyXeAeBGu+FN7AtvxssbiVQ\nrCKph1+FyCmDovyzYOBISlLf3Y/lLXoVgc78AAd6WpWwbgikCqEGXEI6TD63zDo7xmZ7ESswnQvD\nBoGL7aEWOI54uF6WiWTwbHUiTG8vqOt3mJElJBoZ6Vt15yMA+NNufk+97CZzhRaazP6FHR+ei9Cx\nUYF/9FsiAPWbDrcp8zR8KJx102dpnQEQuacf/F4UAN+BAcXXWqpIpGW+Ub/BMzC9YjdYxz7T0Iy/\nL2Uif4aMu1dg6NWxkQ0KkP1i2hOPXwCTa4OACNN8xjw5nFMBn4aLccOJMSVyGmrJOUAIYmkatpYh\n7yPpACYm+zvqE8Y3oRNRULHUYTtBsWsTyZcN140JH3irGD3wYxI0dsQeBODJr48uvkregqGqED5F\nVbKU9YRiloXD+YtT9VOuntIgAFNBr+HtxZQSn3rNndoAWL1oHNepPS5zEcAjZvhUmHiUZyOS0LQn\n/CJh6MJy9laPHF0mZautMDvNJx9KOjTSLNF2Uxsv/5q3tBlD1ZOC5Eavnt/69vWZVR3vXuzuVL+m\nLMytdc/WWqvP3KtNbrO0X4vMY/gtyfFI1tZNrq38zy6tfQGCHpmlBa3WowS73ohuVjXI7zwGGmo6\nWPkXtaT4fEKX3FWnftNtP2T6orcMpiwMUmStj+mdNUCmCqLdatiPg4M9RiIv/PY8ljZVp+Ih7nVL\nDMxLEGkeZVCkPoAw2PdQnUuEgtSxUZ+6t1H9xQZ7W7Pl4C9u9WUbDt9fBqR/9KjfZe9JX4o5IVMC\nQm1NUwOjweWZazpIIFy0l+xycctMut7wuDUxMpy1iCPb6PHsMp8oUxB4J6uba5+rRCUbbdexkJHQ\nq90OB05P9IyiUMJicnNHgXy5g2IBDUgBpOTvLBjsDWtl3geugjCAgDdGsXRtWN6yRWKoMLxmAHt2\ncnEaP4IcP3gJ6e1dqZfYoPlnCgh2gwZLQeubJmJAG57UBdWjF4oQkitQnXQGeJ6I57a100BMM3re\nC3PFW8YOWeVTDaQUL2UQ6jkwudXNN34EJ428uy5VAT1gbsOvEN7nU6RLJw/9ZWMvNp8lbgj+hvof\nx2dSk4wBxIxFkMF2qe5499xnKGybMGYUdL20LNaCPOKSyb7ZsEFlpRvxxro+ybE8A/BXHAWiVAh1\nBkVyS2gpzq8ObRTbjIIK5py8gKspCuZ7frHA+NuLcEwnwseT3h56PDBrbTgIMV3F+5ZsnBBvmyBc\nqbEA1U/uTs9y8x0NAYVcCnzVxmNpPBRpYN2ggd0J2lPaWjX1emf7nhfz+3THzUb7lhI/CLWCT/7S\nSOuu3DXh8S/xzzwE91ubBbnIP7FOkO3t1VdawWX9Via62OuQdBinFaQhN4GnvZYZqkN7z5LR3XHO\nIewGOtXeIONPkrDZMHB76tJ9EsKnVMKRS3ymDVtbKmKMxIB8xKYyxnzHAR287dc3uy0jEJKjyjG+\nvQDkfRAo8OH2v06Trh+dWqCDJdI5GXQQt5mYA/UCXKzFQEqKdbPkdlIWgkixLQgRTYDZXCrn3GPr\nBM9CQldJfrvRjYuzlFE+JcIArrsZRdqSYRTt4q7lbNUcRlaicOcYl5NrnsISId/BwViI/GkG76gR\n7lpBD9og1Yrxxi0YG2xLxnYvnbo9eqRXfyYDnOpdUzr8pdBTXq9jxrqMCJ1hLdNKIUT5JM4GqnGy\n/J+I6W4beKrF5G4Ac6hCraQPrNY8PM0u7xQEfVZQEhF4qGXtkAS4z9vtmthof8cZD+AzoDp1iV0v\nmsOr1wO/Aa3Tx5UAHesvTB8DgUsN7n6dTarXWNB1Ls1/OE2MvOI089rRYOeiF5QROsxgNLKBRtlT\nKsfsJS63PHG6pSioeyVvyf0J/EWvOSBP+hD0NaKkkO/trQtkhrLs3/eoBMwvL0msVizEtxwd1grw\n1zERaJ+C1l2Lg/DN8v5H8LZ9PrMzKTSDEG4w0Cw3l3CTCsRRENusFIG8tNV1hycZtRHOV3/M8767\nJnw8qeQgNDzWEHEcQqn82ZFvCPcbEqkgg/HLLL5FYA/bGOqgPbL6SveAImvQqIo7++WAu0Lo7bZ5\na8Z2ra3BgBV97qXuKI0c0ygwE9rQN36b/MUCkyKLmzEqqv915yFFfF4bx979rUWxCQ+JdGafQxXz\n20osVCRrtDY93TP0tnjYTIpkMQB+b6CGWh04n6LpxtkQzb9vivtvREotOSWtYPFXDFW4aHV24/BP\neWICCqIpM9A04cfbG8OoOwsXIV3nJrZZUlClP6ZOEZz1+f1CMI92jH26gQttIkO2/Mzj3wJZ5nrj\nwNeumfiOFBWUaxiMpifBzl5ReSuRdAmq622di1Tw9VdWgxR3OkURNoP786dMtNWAsFljMDuWiiSI\nv8ghW/MNqglcYUOyeT3GmcZIIXx8nhCreKEgjs230Qq/fJ2VyPse9LxaszSxeRhvQEqhVNP4/noh\nAEdUCp3lTVjsTud0/H6jNptRdbeAX1aUNCNg0z34F4kh2FnzaoEU1W3pXF6fuPaoe7NDZbRnQwKA\nfW/u50bJ5iuB/6ancOqnnSXzt1jgP0hz4y+/TFxxZ9c9c07ylV73MdEVGgSddIi93mHggFfmXfAx\nP710mwbKgI654bBWNrcpwJ/T0Xd7rp4UIzXFtc0RQb6zONy4PzwxwFOhP4yOJYd+cQQEjDoizkQi\nSQbeAEugQMI8h73lvjErnt4PcJ6Cpvvqqjh+fq+YEXHRnAQXhws9dJZXnwMOFBoGqruo6ppDlk/g\n2Vlvk6EUlHrnbeT47P9cW5HOJYNqccFeyvgd4jSo35heQUQtRTXPHkJyknjnlCP275gM4Zuw0y2z\nJoHO3D5vCTeN9oP2KqT6C8ZnaX+SDuxnrcicCszzJHzhGiCOl8Cq+mWiCq3WNbkEZGfBEN1aOr8w\nToQEZN1QmdlpHl1L/vcEsLj7feS6Ha8tVX43ZcYwwGPfBMQSzjR78zbv3UhVKM+a1TMK7rreDYpu\nCwwmN9V9tO0VsXyoQyTcIKD9FizRYvukmPj4ftb61yr/NJqqKNN8iP8cE15lIDxmRDDYttQS67iJ\n91B1LHInnpwZ3BojJjx+ron8xoFtTWTeJetrOUy2+2PfraJJbfllc4AuiPI3uN3y4aIEaLLMSqa/\nc/SsrMwD20t11vMilbidr5MVvrNU0CqvlG0VdBWUm+vXMHyfZ27rDgIENte5gtGeiZCBKO4CdA7k\n1rRqzliSNHHegYS8OVldO9waBKIZccxG2ZPBSaY67uXiBEYDbYJgTk7PGV2IMbQc+ybfavi/Sp5p\ng0cUSjWgC2vg0kXom/s91LD/4gtnWm59RxwZYxzKNzrbqLcN4PJw2stMkU14AGLoykovv5yuKDTa\ncZGLV/R1nIoFNW8P8dom1tYfsp7ZYzZPeXTeefwWQET+96MaNtLlCWqm0ZqFppMKVzFTGtX81HfX\n7LJVb7CQKMYZ+VvvMvulMXG0G0yw2vuLh1nc96XLeJVIDPPJzwY9U2Bjs6Dtl5nVcJIlPDhK+oW3\nnkRQpEEQyHDoRzoL76qGQtNch1bHIxaN4Ua4a8m4I4re/VyOrI8girJvJWru8VtfHnf+bf438aDl\nsT1JcKIsWKSVCXTLJXV6zNWlocTTZP4elRIeJOdYu3fdED2fRlCx5Kn0uzWaZWMgVRHn43Z8kcm/\nnIqbFKi5T9Boujdc+yZCtrfROvjzffSTZQaYHTKDnN8xuaKJr8JzcPJUINxs/+oOsaWDgH6Sm+29\nkM3FBdhojA5oCR0qZWJ1CyeZNNLXh3hhjg1EiQpqFAX8sjc1VY9ojA0dZf6jLtaFNu1YnNqSlLoc\nZj1Wv9ycLD5JHw0qZtEmM+q4hxCy9+V4dxbJ2o8Buc1vD8VJmNeAPuHMnUbemOF4QImhPjYLjIoh\nVGLSVjnoDKxOxGBlPh4OuYW5pgH7/0Jianq9MjuRAaknTwAqXQn0IoVB1h9ZRi0o4fWzHcTp7wrX\nPaPXk4PUTIWl0/yLbs6MB98MxQyx2A0eV73Y6zNkQkEFKEJ/nAnZeLUo6shqlms46YRKKI+6nEjl\n6EFw9rRsN9bnlrc9RSfTBtWiCBIwhWKhbMJaZR0jfGiFQPBp2Wv2UgQjQeNsavuweBz7cEkCM4oG\n1MtcAh53zv+cvsdR+51hrd3EYc9EMz2zBKrb7lO0tXx1awxarg5NTjyrfGW/4SP75wCOklIPrade\n4l8Us0yiuyxYlpwLngx6O60qUGJg+o6n8QJO/S7LfNZSLhl9Mo5eu1WYlDfkdPhahifpbb36WxHB\nPffQxKPCCoKDjvObWZ/VTq2x49A+a17LohJwFkMtFiCkGwiJY7qT3UYbTVyUWOPqU8E+lqXPFg5I\nSQc9oj+sAOA99l5ULkZUM9eJ//9Xjvst3CYhlIMGc2E2ol7IPvm6w8EQNBf8hm9el79OR8DSKK8s\n8/R5hbZNl4gO1+FBVZ5TdcFoUrNZvf8bpxtIDEk5C50s5dcLzDA/a8hGRnZdguWGbM27Wd4rxmqq\nutcFcgXVjEe9Y562kiCvSGX0aMieUlhDM7cHw7QeD93yisunwewgTxQzEKX9/4hQWIKVbAbty7qf\nOMYqVpkpL3eltQncbWUDE5kBTX1JSjNqsgOjgOCFneX4ly65gch6qF0M0dCjmxNklnM6vtY5Pnky\nRFamwi+9i8vvLo0p49NBUvp2Kot4rNrT3WvfTQmDHusseTsrPQ9EetXS5MLKvCTP4fNGQGKH1uEM\nAEZZAnjDP/slY5Yf8V3J2O7mwxOEE48MkUIuabtO9A4yhS8dZg1Na9WBoRolNjBJ3A9+N11Bk2Ep\nqe5CjTQEbMjDry08y4zHGoXP+TkkTKebWSly+iwqyEnLgUli7Elwo3zsZwnY5XBMnhCza3FPBwzZ\noLSU27vTWWaebDw/edLOxfiuZMpRHH+bV7MNvK543Tp3TTwbFzxzbmqDihXlMkDjiWGRPYTa0AVT\nb1gwKaEycgMRDpufJVQkV0emN/k16zfOGYU2+MUuXqEQPslAtq/GKSA83LEo5Sw7k9zRi+vtYV3D\ni5Lg552O0lt0M5wnPf9PFFOtyWnn1illJFiqARj5oFkRcCJqgmHWIEwYOBqaGYXCsKdhDzoh3XAz\nfVfVpvxtJfPdTRbUZWf3uuRgvcuRtHK/1qy5i9zRRqQX4TM31ZLu48R4caIP1CPdiuNfRuxDO7Al\nsXjn4UV3LBgfiE8e9TIYVmeCFnh90mACVE/TEgspPPZS/vgwzSLNtLGYinQRblNeDo3W8O5xgqt5\nr0fj4CLuabzFE0JCwP4md1f8CRppr5Ty5r/5JAYese6sJUWnxDzfDZb6j/O7w3TngVoZ0fmQinJY\ndYDa7/RbFsGptssdcGd4+N7LttL8phm8DpnRzPFYbG55+iIT06PvRW0c2qqRzDa8EbKCLFcNf/GB\n86nIcOHdgw1SAUUAZw959CeWZdQNVr0evLOLwjEU0i4Zu3ppImMTxYVplwyheLUBn3xRTaEjpFz9\nHw4yv/rylAuMqVdPrdKvvMCM1ENokGyR9oCAynRKMRqffjvNCzdH9QSeNJMGHaA8Nqey90W77Dup\n9vmfQ8BZ/f0hu3/KaRFcTO/dZhKR0UBdocx7lhHHu4j2tNZNnxJiRW+qH8xHj7l8uoNxjIv30Z8f\nPV6ZpyjrJCu//Sxp4g6ZSp//ZCDv0uhO8/V8vt3AtBMc0l43vBYPTJyocfOnVonkFRaQdbcxCuog\nZ5Q1ZtVC49AMC52WxbsMFkx8lSq89Bd/NXdDcgHECvfKKMXVIR6ng/tZQIZZTRWQ6/eAHT/wR+0s\nYeNdIrpeMTEuVO41+2Sq6WNztzm794MLRmQfMYNiQa5d2ukWM8qn5XhmAx/CNFUYx6MyI1pWMSka\nbQhogMB/D9JP8+GCbSrQixRTvDpY6z7owEos1zVDK+hoFfIZ8BVzL5yy3al5e3AQwHK6wc8/ONee\n6ZwmlSvF+w894D/pkcM/Lxdo38j3WhzeiZ3W3Wohvf8zSFTo8BtxVs3hZXIGWSCz8nxQrZt6c7Jh\ny7M92ikFvE0F00BO8L3KNVA6qncFOtZXNwj5iYkR0QhEXkZcrNgZcDgOjFSAV1NOla3tg5PQEVI5\n0+rXA5rPhJ5a7z71yuviMGWW55zTKQOWg0r7A2c/1yjIwckNC8lWPBs95LX79aTCVqH+TobH5qdi\nPwgBsgj3laCcIH9Rg0zk+dWFl5M6TCCv2K1vtl/8HR4hl9aDJ3BqJ3i8vYBItIl+J66G/JU3GX3b\nvXLXFaV6qenOf5chGB4DcL4EYZFxGow4laXhkDR+CBwYvq42LphsDPm/PQ+OfNfj5RCQ5ELLXoO+\nWzJKtgiBG3YSUUTxfjMOXXUT1SHbvwgwkRddQN+R5fMn+681RSBz4Gt/10I5b4UZdWkg8nWVnLHR\nYQxueWqTOquwbT7f7wcioRA+M8rAtqTngpZAcUVDzvxbHnxoKW+Hmhw1ZitNbZLf2Gmc/mFRsNAt\noX8Xb0FfeCQWxGPBF8oJE07t6gRy8NRNaOqlqsBefXuNf4+iMo2mXM25L1XZZMMtYp78yz7Vdsc4\nw/OLZXgcMS3sIwg9A7f0Yhvn2IHC/DcKRouIOKPfwideHZYu4FqaXc6AQJKD6Z+wqkog7s/Sm5BO\nJ8Co80LEzuUUX6CNA3I2vmaBT5e0eacBfnOKodS3XtInHwbfqbCVjHO9pbCGxsz2wyKdBlueTVjm\no+h0Cwbbg0DpFstLxeLJwPLOan0shA0koibcUaT8duCkhjuZYuf8l6JWAj8/+38BBXF67hzijbyw\nF0ZYZZYr4YK7KEpItgVFYEGjZEBIJD+xUSIT8PMDL9n7Vhk2uaoEM4hVhVhh+kVsU2v+n/j3E4AQ\nvBhCxO077AcMleIocLJdxdVW\n`pragma protect end_protected\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/ipstatic/hdl/fifo_generator_v13_1_rfs.vhd", "content": "`protect begin_protected\n`protect version = 1\n`protect encrypt_agent = \"XILINX\"\n`protect encrypt_agent_info = \"Xilinx Encryption Tool 2015\"\n`protect key_keyowner = \"Cadence Design Systems.\", key_keyname = \"cds_rsa_key\", key_method = \"rsa\"\n`protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 64)\n`protect key_block\nicwBRV97stUfR2Mn0wfPioI0eY3zGZJF4gSa++nlQlMi8xdqEhl343ha2TeCedqJlXwUNOMTshjg\nNWAZ0CnPtg==\n\n`protect key_keyowner = \"Mentor Graphics Corporation\", key_keyname = \"MGC-VERIF-SIM-RSA-1\", key_method = \"rsa\"\n`protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`protect key_block\nKdJiATwLz7apgDVo1m61iNvEkKe0M4UdBpI9Yd5Ge670sdg1t/Nie7/y7x7SOpFtKcG79N3mDoiw\nbP4Lo28OJmNglVRWiKdTRUXoQr1KC8IPt4mFyf8RW+0wysmhFnEJpQp5SwugZAg4ZiK4FJrJlEZp\naSpgrgqxILRzspwvJ28=\n\n`protect key_keyowner = \"Synopsys\", key_keyname = \"SNPS-VCS-RSA-1\", key_method = \"rsa\"\n`protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 128)\n`protect key_block\nSEJEAo+4DoRBD70Ek1O2LvfMayFQjSsQ6O1GJG8EOchOxWL4gH+izXdYttq1qTGn/KE0kJRFDUcX\nA+ZQ8kqk+Eda70AyokFzsXsNSPHzlbWGhztR1gvMy+dW963rNBnhXvIDRr9xQxdB0S9wFcz7sOOD\nN1RSFCm4eWHHRbqFsdE=\n\n`protect key_keyowner = \"Aldec\", key_keyname = \"ALDEC15_001\", key_method = \"rsa\"\n`protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`protect key_block\nHw6LuFnFxQVdpUVS2z8t5Yf01nLm9evFIzBt0PsoeSy3+WLcOytdKrEuHuwtqg6ihJly/jHVrfAl\nTVavmgD4k59+ZTPqwkyYVYZr8LuzM7Fv3Zsc5/au2o+APxXDon/zrWg5zDCqJ+yGISpVFOGA0MAT\n1rg2BXFph8wATddw8zNlEp6bqZO8wbVr8W+qZoEQF6sr6GzqUaybeo6b1Z3w1X7NKUdCSPPuX4db\nQRR5bHztRnOdGS2ZkX/0nKkoQdRgAGHSPbGl9d/YRB45phWabAM6E0g7GJRxyuqw+AKvG85eSMKN\nV6SyOVpBvhsf3QR2XAMBRIjaI2XLG0cVK3U5SA==\n\n`protect key_keyowner = \"ATRENTA\", key_keyname = \"ATR-SG-2015-RSA-3\", key_method = \"rsa\"\n`protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`protect key_block\nf1rsayuAPFUtBwuAa6sFvNELSdf5C/KR4epVKFI5FedDC7MXninDZvVIr8Ro+3EmB5CE52O3Cses\nOzyWKYv6YZZKdPiFqafxQGdjnlqjoxI1gThSKKHQBU1hBfjbwsxmpQK42hqhWzSCpeRTJcjV1jcg\naVPLy5PWglGMv00FiULQXmmn5GFwuKdr+Bnk+e2BuHMI4hipT8VA3cn5wgWr03pZFoefI8cpN+oG\nu9Ot12GyURIz66i6gWxGmq24zuJUslhyvcG/IxJB/b9eaSe9bwz573Uy7K+hKZAT043fQL8TW7Ov\nmXUYJTHcnse0uXeW3bie9BUo6EE7Y9TB47lk3w==\n\n`protect key_keyowner = \"Xilinx\", key_keyname = \"xilinx_2016_05\", key_method = \"rsa\"\n`protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 256)\n`protect key_block\nu0nDmA3YrWcfEk4185AhUszcR/nwHQHMMcbB6zFWjm8trTpyEdJp71iK4ywXp2oQ1lMSKg28ST8Y\nGUH/HaXAvnJIVIf9lm4LECEiUiGW8afQ0cwQ7j8ujiLlWTcu0tDGOvezlUc2E0EMkmYd/yAwxLcX\nQCiYzQrF83xIvL6pPU5XdJbaD7dD4CFOpFEQRnzHYTDxHZHUu7AGIhYCSDrXQ5OQ6te9Q4sUdPJS\n/KiTKe33AZgktXIhotf5HgtgK/xiCoCoxnSbz6PwQCkJfuQJUXFVua3fEYo6DkxeRwgmhGEr+1Nx\nRBmwCvu87h7nHZQ60sX5T9NikshAxtWacHhtGQ==\n\n`protect data_method = \"AES128-CBC\"\n`protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 1050704)\n`protect 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dbo2hsnuRovXrzW57yn/tbseIV3e62tsjB9E4zcChDFCTDtvnuFhEB6zS9dBCu4T9KoSCCzG\nSMkoEU3+pHp1yCVHKaednVfkPBhUoLRIHQrxMPn3xGvc1PVcjYUwHW9yORjsBkeCTpNi2xfJLwHm\n5GM1AOd2GIb78W/JbapRoARZVQnDKn/kPBIbsSpFjwIooVyaCuLDHguDzjLuVhxvLqrVIUnuNTbq\n28/T3RznQvV4gaPHwVqlvZ0qGnV6hcoPAv6OaLiOGaniflQ8mSkDkxS2g2/OEsfQAED+iixKd44T\n0w1vpvwA+d9u53+d9ynQFS1BWdvXetjBJkOm4GJA78ACkKnHdZn8TKFCaqF7zfriytl+5kPY34sd\nqvlGmUXIbJ+QLkZ1DKL2sgEFAtVEWbkdTZYsWoG/WITUVtCAo/q1sJMbEd0wh650LVUSyyaAMKLg\nadvi0ZLa/WqU+O708OdaNCXkOrfSQW5kt6Te0JoW9B8RzlUM6kB3EW29EbKy3iH2EC5CjYWE+2iG\noPRg+1f83wDKr15i330n5qRVgoeISvcVJdp32B0xSOPdOIJE6iDoqbI75ZaUA8ZeUw11ELsB/56K\nXgMxITLs8jS7RQnJzx9OTqlDBaDWkIRyZC3BPtOep+4ziXPUQOLDVbHKuBghSl/KEzBA4lZb9qtl\nKUi74Rakj6oXtgVx0DS6l2RpjYRO8NOmCbMeXjAyTovhWO9G8ToHUbE6TGy0dGCRl1AMNBJ6ahe3\nFnXxavSvZWjgsEMTp/2OT7hnlgDr3k1n8j9HWY+T+niyOoqMJ8gZbpqXCBGHkdcu01H/DdadRwu+\nZlswQX43LleKEP5SD7Skl0nnVMZ0eoeEhSVofmnXYuaB5rq/P3vTpynSJhMxn/jdH/7Ff0pZH+CA\nciZN8frJa+BfqrRdZa/wmuBjQI487VEvNDZgQGnRv61fPxwtPJK2JhElzxydj+w9eizbe5BZBeNR\nZKSlZcku670BD8zK/RE5CZ7OiPCGR1vmcWdSzU6t6qKc6EKPyzv5fxSUSp2Oqmf8C+h+HH8N5L6N\n5PHR/DxxCfxrvPgHyiW/zwkz/UlRCvLE7y2GSq3Lp/LbKD3NlUckpW9/0HD21NubQf/p61T4hP0L\nV9W/bl8MYh6GrQaMwVn80VaZyPS79ipL8KrnWB6OsCUHgKi7FHi95j3bfLxOl52ZFlPtqUje0Bu5\nMIhrdwaX7ghmkAQJQ57R+EHU/FPq281572DqooThsCDMCqTsnIhJG2BQpgn7sHyiNLKVsdzx+LT6\nVpLfI7Hhq7zPhvC4fGwzIyatU1rx9dhks12VwHeD9K9X6HKaASolLm/3A0Ha5gAoOuN/yNjQymTw\nwf7WJiHD1a+FOKa3j4o7kRrSN1jaVaZoNkmjKZ0+KZzzqWv4dNRaHSEWwu6MRqFWvLTz6uESz9tN\nwTxLMkLI8D6wnX0DYrk+fIECVUa/DywuJ1kx6ASPsl3pEZKQBTjtdaakh7gD77Qjs8N3jF6MtIEz\njbZVR8w0F89bCXjqkT7fupApVS/t8XlT5jI5JMpKaJi73TMXMc+Hy7UUSnu9+Qrk2BK849yXssiV\n9+kiOsG96Al2jeewO4CDhxUFhwi+zcF76nJJ7nqiVyErkNRXMxlUo4YXKEeIx6ojqC/ExG9MPEKe\nIlwksIDGGieAUgS6XsUpznRwagwTv9S3q8c0jU00uCJW5dPAu38xpNM2Ytv/tzkUFZdNVp7zscfM\nbjzcl3Z1F2ycnr1fjSDP5mW67P/SXOFsndvZPm/Pebj7ICeNjrwnSnFYXAWqcCPo3SgCAjsjx22x\nxCAVe+p6bABh00KjUASrOCwOKAYPz5ErB87zgyHsXaDHBumUAlLCDNGzEZhBewzq7exonY6kheEu\nY4BfWPMHLAa2Aotlh8df8K9bLlPwgR2DorZRB1PPAl4ydc4wAnQ0J9sx1uqP6mNKTrimMUjxzgFd\nDcHrnGWuW3nPKftTsqq2nxo0IQnUo+47lfRk3hLn1q3g7pgq+ESMKCwVW7c7JYIjJm/SllvH1Kq3\nzVBunzcQBk0GiLUpM/iZBqElJqBw1if96/DI0RYq9RWoIb1qVn4z3IyOKYYSihqM11omax7d5VGR\ndhCXtP0bq+hNoDmOpQgF8GF3KfPCCC1tuHhjDMsSjHkaYAKNGdXKXKV6hvF2HHSzTuwYwsruAbHu\nJD2Ax6iSU8wSSK1ihQ7UtaV2CyybYvbQKhTYmxRdXoQhLk4yp+ojgGAuvelKiAoCRG7bzTJOSfCW\nT+adOboVJaTARlfwEUj2P8H0GvNiuCqE0csZdYENdQxln/AN0q/8GEaKyi07S7mUlGBUaGI6R9Y6\nlXrX45yTsFxyq0tmVzWEfNA/CQyCz5qhRTNRrIAjMAwy+2ZYJiSsL0iLPYrJjB6iVA4l4iJ+vO0N\ntv0YB0dy5Bx183Rxo2VmVlVtDZb8N0ffH5h+qLF0XSaYkY9DbvtN2UJDiCVYMJ6XWiun8wAxhlHi\ndsCDFIruXwOprdH4Jak1IJjOn8mj2zI6296IwTGgsLHls3fMTAyAmRYZU2AOjY6sadKR7EAe5aj6\nm6sxNuATHPrCVdkgclbv7SKo6/pjzbqZwvH9F2wTm9Vq8M80OXaroYfFU9KFcfr5H+L4hoAw3EZm\n9SoauTtoMZC9qppHCxSIT7qwJVV+pFS0FgHGfJ3hEupyhycCYj/OyqA2+V8If0Fypg+uPyAc6Z9u\nBq3b5UROmDfRn3dJCheECYmLBZObHRY+UmOKGDfsZTpK/TgzLClJz/ZZzTtpuHbAONltLoqnsvMZ\nwLrQaopQ6PpFwa/IXuK/SLA9a+IHrlM8xGic86bWPE9Txgg6ArcgjxC0EigqWROTU4oKU9KuYdWq\nXZXInI+0FOh6BKUs+CxqUJr8YhiYAoSfJxQ4BdvREPi8WxZCGMIBiElXy1wo4681tVLprg5c1h+/\neCyCSgXuca+1+pQ7rtU0vr7nyvC6P+wpzPc7sNnivqS2U2hMn5+CPO1R2MK2vPaQPd6VWMbEw2Lg\n8SHKks3HBT1i7+TPEn24dIOK8ujvuXJS35YiUFJoo6XqhZA5ozg1iTQ/NH6NoYZmNm5NXyLpjdJQ\nJ1PPgfzwo0ZuvBuvX2+1TmRWcmA9bCkKZnbhIwikEkcId6UZmHgbWTp3hns8jRclj20eG45s2suL\nMzaizZCR5vWdx5xo5jerQUBzH2R3WGsB8tK5X/VTYFYcQc3pax5PqjkMwiV6pSJi9tovtb6ksCWG\nJujZkN2rhdE7NsfGbiJmpVAFi6VgiGGqQfUfaYuD10fvmPAGucg8oO0OqeTJEzFVwXYvzBNrr+y1\nZwQaZPsLZhxY/El7MsR2s7Dk7FMFhNi10/sySDeCE9CY6z3Xs6ZWBJGBoiI++djSfOGZ2iiDyG+f\nHneWIhadE8LlstDBmyXD8Z0VyUEw1N91XddE1YkjS9JGXkXLxOwUwKZGgdc3N9HVZNZ8Jf4WZ9Wg\npyUFXsA3EPMV5QYCvktLvVtqP1b+8p3QgnutVrN9oNPDPi/7xf8WnYtOYu4UKaaFjYg1hzFQmODC\nOrLeXmQptB7jxX6FovJtXZ6kazuCrOJyDsxb7wv+Krz8nMfayDBfxKY/8QrZ5QgPBmwisrxfXYOJ\ns6XOHONL7cv21caBqJgO7PCvFdcf/wJAaOzQuTcfa9Y6lk32T4wh25TGTA4Cf7xBHlHWClodMSlj\n1CY9C+/NsmnCFmfxe+j/ga2pNx3gnqYaqkrIfRTa0VA9mwAL3R3NMNHxfpnKSS1dj6xJtnGsJ+EP\n5Z4WZPut84KIom4E6JHPb3i3a3gE7SFJMj+HMHtvxnwOsIq5wB6p2eRMOIFwd2CRBQ5N0De/Y8t3\ndUiwDVTRbLLh2gwHCyUgf8/j3wK9Wknk3VqFuYy8xsHg89YlqC7LsmORoaCbD2/j1xycAFDEKcP1\nT560qPTlSPDWSRpzPjaRhtoaJl1I32WYFegUi0OncN5W6xG/Tl2YT5BIUKdDipDWq4Z/0xWumOev\ndk6DdRNzDZdjgMCml0MmXbVUAxgZGUCO1OCU7qm+wEtrk2xd+d+DxiX5jCtK7DtSQlGfBpRGQ2x+\nxMf8NwvkKCSmd8cxRRA0nTeI/kbrvVy6/6wXsxWzJ29rohZZ0OpN8U35Iic20T9KGR1tPDHVPDNl\npsjO/zQLocTTjAGkOlgwB+g9eED/ML6YhbBdhGk3AMQmW5uOvHc1Js2Evrm0lBGQH2s7wo7Ky8hq\ndyPfq8n8ZTFOi+SBZvNhDgBW9CMV/JwPtQrY96+zTZfhG0bqNI1UXOMiCsQw4DoxSxIVUgZC6cMI\n3/1U1rxL6Lz47mrWoSbS9TnAb3l5wEoHA8feRneJd5i6EMtBJMxMqyjRHwfZnppX6S8k/XNO4k/W\nLp4hDZX35MOnr9d6OU+IbciLlK9OH3w8csKIgBOu+oGq+1TMZKEjJs++CbJ50CJElMPvCYvAvTgn\n/4kjQHgPXqUHhqjeV65htHEK85MINA0i2ZMVNk3hAL2d2IZSfz5KU3xKc6sXoghg5KhjsjMSaL1a\nwzAYrPqtR8UgvQomQZvJH1L2Wiqc0/+ubCWvhcs4syDb9b1hqtCKMfjS/SweWjfh9OcfFi1FNCbC\nVHokV0RnkgxLUHxfv+kekN23nPcPEVKF1RDtagJ3xQimiGVbO9mOT050CFG+0iuh32vG1PCdDd7F\nZ/NUfliGOwmHLRUsHyAzmctvXpJzmb2uW6WwIX949kjmanmprzLtj9y9r0nEmbd3/impeRUBeo0q\nI6HSaSYmSgk+3PBfzaC2AWQsJ/wrnrL8mzJgEMt3F3l8Zh6rJP9QIJHFWFYK+KC9zZk5ao221WDf\ndtMA7XxvZydVfrJ8s4B6AljKKcyrYIJrgT7wwlnFlC357FWzamcinAmwUhXqVR6vIhCyzvBiBXuX\nDaAMDFYVAuBZijOd2t8587kiwQrWV5Gi9wEbcWP26erKENfR7eeHgcf7SKtRqILrtBqoCAP0e91q\npdoRJGPp3ShwJUyLcBhbSUOH8OrVLaNRmGTsDWOQ03rZXfhC6GhYCflDrkQ9+N9Y7NJ/l81QL7b+\n1s5e8n8lOsY6zgu3AFhh1Is0IM3f9JNslWeSYW+gPdYUF3sxCIhzESFwuOn95V01k3WGZCLLjFjr\nfY2vfJn2axAbky3xI77PBAztZOpnAFvpSVES0trJU/ivOaI254tfe5ZVhP6+JiC0RLnT6VmtGWuH\n1/qtFEJikNc26bB5694NDnXwBOl7Er3RnXpeiO3ofXZzM98x/8VEKGEQ+qRX8+FKyg69Q0Pta9zc\ndXwH6sRfmBHhhjCd+JAirQrsiqSGTABI2OI5yr+s26iQ8z0AVyLDKslF44LqaUTBMeIMJjQjy4z0\npd8OWPHdIe2+NaCeBG4xmjltakVz3N0FO84ZMSpa039A3oXRdhIRSwMo7sMWuDFs8Add9VW2AOa/\nRwQy1FYNxq4AN944MtjYBrBvtPKL+sXxoa8prnlZX2FsYFoEmJ2v6P9l7iscP93/df5xeeFhTS1U\n2yA6fsRtWh/A+SVbrIbAUuJGQLj6zrxlMzwvT6Tx3sQzH6edcEsU++U2BOJcE1aIC8jIzjXuv3aH\ncFFt9zyjvx1O5gwTQZE/KSivrTA1sUhYky/ZHbCdGpiNaAgjVlCZHcKTC78MNpEEwF9tQA8p2ks9\nu6Hjx9o+dw9+2b7s6KxYvv9MiAQ7+qhg5fORkdLm7UDgrQgMixAuBVYHjtWnMrmPzHKFPA6mLqOq\n73nza35wKLlaG3fgff/b5KHUtk8bWW736WadHdd3KTS7qZt/QVBhgQM6oEqE7yHnW4sAhmp4KUUc\nSC+5Byhm7fLySlWL4GYecYbMOHyeWX5BMPh05ON2d9u6shmrE7PP5qcLQ1A2SaVkvzw69CkwbeV0\nil+AxuHpjFKG/qMGauQYbs8bhfNWK2JF1r5RchC7v89BVtGFwqIHyVaQ3jZrA3yKMckVnJu7Lxoi\ncgMC08iJJm2ZioJ8QyGpO4eMekMzulRx4uRi9ekEuMg2tGEbclkBBq1u2zmbiCSd+P/3rOK9YjEr\nQZwu5LyssY+/3oMWIalsTYZFIpaDIeNS8A5t1Jo68Yiavi7pcEPX1lklwAT3XzLTHOX0IWG9jDuQ\nxHq+h6YOOessX6dXfRCQ+T/D5+Qj2Z9TkF91m73EL+qY3FjeDLB+4dJBtVXsz/KnNE4rtJuWbKRr\n2xHH0v7FtBOp1frGRFQ2jrDDgLjuP6JiHVD/f42buoZh9KXrFSZxvQcxxbvrU+JTAbuU1Q0mKr+L\n6UjNlKNGg1EDT1RjJDT2KNsxzthey1A97cnCMF6TpWD9sOGabI+ng8r/LVFUNer49CfBhWQP4VCo\nrX3id+BzIcExS1EDJUZbqcABEstWg1OaaYwjgVbS8UWrgWIHk0E0UTR4xuxH9zO3eQWJZpt7HHRj\nCTPASRvok/+u+Kru2RChkO2t3cSHlHgXiydft8Z9lkwQ0qpomiaUFjyrBSZn3npnpT5YiwIQvXNR\n+my4LkVBoOoBTLdYvoSEgQFUjiHCssG+8iStE/mKCpvksvAb3fdUzYRphoL8upc82BH5aZRMuYHz\n8Q8dLedd6md8AnW3esZ/PqCBd/5yowz2l0agnI0ULX6b5Ke/Pc/JOGJ465lImfnqbA0afc7laAtY\ngAk9Cs8edE8pmlMSErkMqITKWNEIAfc9+qD+flwASsaGYGRwPlAtaonqIqu52JsO9ieFVkKMzqr2\neptcOtf+AJetEE2XdI4BxOJfsdC/Ah1TQO0ATarRckIJGzxhYWm1uNGcH5oTAk4Htkwmcx243F8g\n8LVAjkPjBTR7Il0LZyXWn1ED7SioseKyJLj/jb8oScq633Xq+SV3wrk3GSP4ao+USdq1DkWvS7xs\nnMBN+H6P6d+oImx7vUeZZAXEyPX/wUShuuauNQfc7lf4b6S9gBJ9MtcuQtyVrCJNswHLT56KDGr5\nJPTe2vJLAbD8XT1FkpHBIRgU0uDTY8/LjmfUhpBQdxvuuSLhgnIpR3P7P6TMt7BifzNALhHp5KYb\nPiplpjUJ0mIaDkqLhWg/MAdy1NXy585iaoV3ADtAov5+ddCbm38lmwCbnCspHccqYdgZ+gaYfU18\noKpecoUe1gTUaDhEARd7X2Sr8Mg1xJS4IKalf88JDujCmi1SgeEv5RtTiZRT983EwJYTM9aQOuED\nAj1wZ7NRSJtn/JB0ZHrTIuVw3SucZ7BQAmIInu1rr+uJQiRLOkU2pc1U2K+DFMX51vYXmot2kluR\nMm40J2o8/0JYgosaOrRjKc5beuEjCUUOdY/gtRobsdTTh5FuepSIgcbxTVOM3CGLLLcBZlcy6GME\ngIt/iBIxSmcDZF6vxRVIeOUsHC/HZN8n7GmqjzMvoVkZIKzeNl5GxXCJAsDqH8Es4lyJnCjG3z6F\nU4PuKv+mLVMMGxiZd8EE2bAFobD/16wj4fCV6hUFORv/AAZZlSsJ64YJlKKu7E7f/F1l7/+1Al9Q\ndG5z/fLmCs60QOKHuFM2SlQ1Zclm4tbQZegIP+PQbA8mRvnQ0GvwPiJW+CokhWvDec9bpJ6dl6iu\nItNRKiQjI/7PAgg+cmqiEEk5aS6SScNio8cCIisHnASqjqAEjtC7MprMr3wOfwpeRqhnR0GbXF58\nOCOwnLRIXwy4Yve2F54JhuACwATR4vnGGsJ1milbXw6WakVl05iW+gSt5OQLydmReQUaEGaOWx0a\nkE73FYZ3c8ImXhEdfWPagIVPQzbK2p8TYxhPcTIdt9sOMqLCoa0WzijHbunhHoBgh2Ei2/Toagb6\nnFqWaicv1BPbpH91vHan3iNmUBnQO0sJnUl0uTam7vLKXB5sLi/Qj5HzEtxn+2FPdnFvj3surADX\nBvD6o9iSnKQBdi8T5FAmbpXKFhYZTP1CvaehllWS4L/uPQeZ/X2OByMVbDs3EPr7PSsabJFV+MA9\naLOjistEOhi3ph/DlIT8WXuDCRBkrj4B+q02TMsogHhKEGF4EJRK3N0VzMThb4bu1OKPOnDCkIlX\nNYo8or1do6ZaRGwzfL+R/6gwY9+FXwjwc4zUGQcPsZYKT0a1jrRN/xPJMN2RX6lTMvuFRjQvdLJS\noeuFfAfEViRSuPZiUqzjHeNpWAto4oHJza3ITY74mgOI2vc2dAuJ9eTtOorH+q5IAB5Y3jQL+ZB7\nWL0wyzjHnLpK8e7Xxa33hVHWZkpdxJvDZUL7XpPU1VXgPRGWo3mvvZMf71ru2cnSuancEBF0FhWu\njPluWk5S9f81DCf13e4R8FG9ldyNdGgA/OscEqfMLqsVIrMLH/CkxpHT7apqDR/4NVV7Q7ne2puU\nItohSGFylsCjnc92zxZd9WmCVromTKGuz2Ot+4fx3OLG8xo4AXdZs92u1Sm2APeQuNTYKuTQtfc5\nLawUcfVqiB6WAZ8NydJ6/J4j6pGsWP6EsNFFIcM2aT3zlFW2jVce8071i/Oht1CyXuoXN9ctdCOk\nwrD6ISpVtoDYcxwHrc7YYCxrK+MVlFm8DK9/L5oZ0Y0mpYw3AgHKDwQQBdEqhT+GQtNvJdOUCGtn\npWLCotPtovVqAuKsplk693XM0GOpaleFzSwb/5L/Otunvih9VY+WeWaqoElFeX2TCXwd7o5Gn0xq\n6hgqjGYXsrTzfVVBPwahrVo7kgiXUo8eR5bjAmTUWrQeHVvm3pm3V1BeodHSq/IvWv3BoXOLMIAM\n+iJMl0fIYnLLa3WAcbNSdQ/xafT9JCcSp6F0ziYIR7QmBmy9QA66JbX4oT8a45B9EQNUyWbpuYCm\nigmSOVWW47wCEuzW23A8hOWRQ75P/OzSH7wJskqaarI+7jCo4hEYjcLYLn0Fb1gDHmUc3erB5kil\nqYLISJeMgD/bVKo5tGyQ60upGEh7nskTSQanPvt5iE05D912Q2WRUIolIsbElIQ+7fFr7d+JlR10\nqtFcEpUJx52Ick+pwAhKfP3SIZBoQ9d3knp0KBTafvSu0JLJEKW4V9o5HTCXN8sxpeyS2FEhcmHs\n2DRKZBpz9Mqc85U1BDVccXPLbCmgfsDThxUuPeAtU02AB+nF4C2nuaFFKqa5KvI+fU1M+vHsgD1E\nMK6y6WmL7WXsQOdpqfgd6RlT9SPUW4mdNzsGJrWzvnD6VbTKh9iqW+JwqK4+JIJPgWHRfYZQb4FE\n1k4WUjfPiZDWO1JurMA7ti8KWIGJ1atsf6Q9019+vVFYvdINt7gJ4UJ1noKxhybC9OQ4lZ7nLoSU\nXEjViGruCMmSD8f9ffpG0iY5f1jcKQUfMBNP1xROsGrxr0pE7x+LB29nxGUuWpAunl6FtdfbAkuW\n+NvB9kzDReAAPfhmJZdnJNixlqBZtRl9PRpPi8TxqngZ4y1AbZ+1AK9PHM3E07C216yDsVQI5Cmr\nOnmnbZFqJdKa023HetomhEY+SBGXiSP0lg593/mONWCuaJ6b9GCjcHTR0XBlaRRy84z/kTZnVE+j\nHUqTpYYjQD6QdOV/wuUT/WyOgF+wiqda/Hzcr4e4JzJTv/p3gTxAJAAYwKJQyqY8k1aUum1hNYzl\n83UzD9ZZd7Oec71grRSJyTGUcYVHS5veE2xs/jFlM86e7Q+mIUFQeT+jNkaUCY1PN6POuFkovLlZ\ncRm5L8yrdbqREJtsT7XKsXweui5t1dKDxH3KSuXQscdQ0BkblMUQlW8FxcYS1tGSweWWLrJE/Znz\n+PSz1CyITrJAB2M3M7BWjD4Tg9tT0ScorsiI55q2xlel2k3m+OZdVD6D0AgoKDKuA2EBY08miZZ0\ntHbekCTqfihF2mZdrTup8GTQsPiIVa/8y1yi48SIHH+JMbric7nR6Hu16C/GVAB5+RlpEkxB+Zbk\ntSjFaVv8dE0BEfitshLr7Zv029g8NC+ad03YvvFg0VvcmxnerGCz1koC2mxSQUjz6eF9PD9D9iVY\nd6dYskiaPpkvYp/uW8H4PkIrGL12Gd8wQCZvvDxQHFEIc9p6RghhIe1yQEEo0od/OED3mb9BvhOr\ndESihuxEfVBHLN5I5eDSYy+HcMpkyI33IzHvF2JMzPC1mk4ZpqzgDVJdage91f9EiDaAu7KCfnWO\nOU0qZ2mFzBWWVqOs/pm76kL0LUcrNevN2c3FaoS0zAUQoPO5QCNZsxCvEamjBXkY7VJbV2JeOl26\nDkSExDZ1/lvHuq8GdmDSoOvB3j/NmVCfOxuWYX4SfNWUJko8vuPjKjXgXqNDGm/2pWkR0CdKil1I\nKVkp0kEdu9WatmdEmjh3hA8BAJlKANJggcDLzPySiqtT3ihjNddPtt6Rdnut7wm24D02TKth0ui6\nCP1rmpdIq5QasaB1jODKXt3RaQyJhrGCYrKbdt2XVYwoYcp76cqqAPVd1vwCkSJP+302pwM2EQqK\nMIJBG4p2OGeo5kuxEJaRjm9gF2flIlOA3+ZuAR8Uo75kjizj/ZynBzMcS807Iy3LYsUxINlTN6N5\nNj9l8e9yMPqy3WBMSOzPVFzynN6Ac3Q2lYRvtDOWUB/LLi4cm//FgDwy/bfKZJBLyu+p4YD4QPnv\n9OAO/MWKImgqoYt8zxInroEif1FK3+2T2+ZVHgCT8bwHHg3JUb7/ISn1IGs7qW4Oq8/Y7N1g7Nqi\nAyh/pgUl2kyRViy7tAOUSpucnjkfAp2Y7FMTk/K8ft+AbtMOtLSVfOsvmevGHBrvg/9pMYYCpV77\nxssDotVw1ujCoKac90N1h/dGZ1U29Iyg8/Bdqhu6CBOCFBZnjOg/ChSPoZKfcKRoxGSFsBX1Dczj\nU3WmXsQ+ZqaIJrJjY94nUbzOshveJHZlSXriaG6DueUyGrwj0zYVOTTzq35/ninUJZluw2/QKWxn\ntiCy7fi7VJm0pi4LifRkbjTw81zKvjgCsnEuuS7kx/DlckXM7BinYvuAUTHwYa7WCyeXxc7Eqo5D\nny4gF/s7IraTac82xvUA/3ab5ZWYwmRYZDcDqNjOJ0JL/Q+lfcNrbqGuW/BdvpBdBqggbolMpRpO\n010sFxXSE0V4ykFJU2vrJ0RqWDM/1hNubBumt7SvlFuwZThYwCuLf2BRw7DC8Z4oT7PIK9P+hpSz\n9ZhYIFiK57sSyZX3NvHJNr4TesEdgn0dEjif1jfS+5Jt0iNdtBGpdyEmvP1KnUEJhZzI+3yetgj3\n80z/QXKipwrlZixWH3fCzbjKbVTzkhnSTeQjMfpeyefYGPQQ8qSBmlaEmnPwcx1b9k5FyDaKpEw1\n9gQLM/VaokyaIbmiYe/u9d4oPIh9z3lzrE/39Ut5P+7hIttqe0QPQA6rvVytc5IDmqN/LgpoxQ9e\nFlpn4MJ6i83Vz0M7G7oUgBw6TMIvbcOodMmfcoXsP0klqmUECk2TbCRC/F2PTWGZTS8OMXrd6plZ\nPeEKm5CcOdDGDit9WAyGxu+dbLVJM3zAshRUGYrrBWyv3zi6exnaFTPQwlkLmLl/fk/0x/zpIUUe\nSQKtx5dJ6nnnRCMgGnthy74W3TgjoHPZOotf34HFpZL7M3/dPOqQyQjYAD0W6mqX/InxJkiIfwxY\naVdadPKG0TmjJzXlIKB+lTkx/vsSh+4Jjy1x9FXxHxINETSmbSgWV4Q9JqDVOC/xo8N9PGve+HIY\nLh3s3mf0JQY1v6xHwmKOJUDYk6nWYe+bAWxGO5dHfM/K9u6Dt3nWEuzNURQfWuNDb7i+ic93/n9W\nNVT4pRYKHYVnD424IBiq6ynvKWu2r3pvW/kmPLZ4o1BCNLcATFkhQC4gCDFdKs+tVr7ysa46fGLD\nG89cI+U2U2WzXf8WzenhbOWScdynEcn6YbuK0IZhRetMf/Ms3yP68gknDyWsNEH4KnReY4GZVijP\neRanpSYbVgF6cy4VEJBi4oHcRpPJYgByIceNCUL5mXyFqpAGsV/rEbQN8VhzKAIn8+uplUMiQ78D\nrWz8IZOxu5pJxMo1UfIDIoLh9o0hJ0pndHB4nV+jtsis+lopyGJrbfOkXB7ClwWSp9m6q8+QrbaA\nQkEf3bt1JjyZRbcVHOcIOSJFzrR9vYU5tyM6tQPKs7+dMfZY41KRRW+x/7w5hROYhr01TYK2ZNKr\nX8+t2fUMRQ8EglrABKzKgYRMkSyjE2I6VI87z4RKomtXcRPNZpyW0M2oPzxmzzaUiWY3OzUeTwJk\nKuEd9rfI6xDol+skUhtd+Ihnxxn6tkn5QqMs/ixt2baPT7hQNk2Y6MNbe9+LKeOIjT91IMruwAHd\nCK7EtmRSYfnl12q7DE49eM0H2gbAtlIgzDxOI0NY/NVtYzho4OdJuNCuit2wP/r9oyxzGBdhXk1e\n37ZrXbCu2uE8aU6E5n6zBkCuFfD7q5jEGM/0CrBpn5E+/XBLEHm/6h0Tq6vlf/HSoLBbY5ujUotr\niB5+e332o3LD/dMsSieX3mXYHO1hdZSF+mq1lzbTT1+XO2BgorLJzBZTSStrbFQY6eYVFwHKdLp6\nkrTkHdOEydfJBzI9yYQXgHum75VE0syP2n4qxCbPmpINIzkHucaJ84V55pDQkF9sQo/ymOKQZ6He\nkUF37MWg4NqtTsJfatUvUC0T5VGvsMarXGvCcneAmbpAjzJ/GBl8D3IAOa//9SvFMUd43ueHesYn\nw7bL/jBm+/rnl1SVD17cK/fZJr/kmlHhZETVrMtIUc8DwEUk/CNKOYUtE9YzAQ8ryR8JA6ao55hD\n7LDI2KyvzyUkzW7yXCzNCaCML8G40qHJpcd4iYZV2MRm5F3dMChoXLpCYuhh2fUjCQ99JqZE/isH\nIiuqs6acHc/JjJsNjNSbXizre9i7XIN+jS85GTd2TIkj3F+1WoOnWHsUeBjeCVTNkwfQ8XwIvIwz\nhYKj4OymxMhm2M2q69Q/RRkEMq2/ZpAZPJRraoZEytEeULX2cFk90UR/BNM2UfBVA79DYCeeK/Vg\n0vP5rN4EdeMqcYy/yS9mprBLQFBb1C3rs7j2gPnaAG6rncawQ03pb90ThpYAC6x0qVm/cAtxwTsG\nLLggGeo0JvdGogkhEilN2QUIzRqlAqBjjU3X2mlkQXU/yq+W7u4+ttZJ/+zUX0wfTGx6kZzMB0ij\nHKPzggeIIeKgoD0Zf3GpkM+lGTCTduqRH+29oF7KynpVPXxXt0+oMe2+bOUp6SMBQBH4HQrvUf9w\ntu2Sw5PpRWEL75EwYWwCi7be4r9VeSwXGjIV4k3nAYq3O905QRX39WdzQfSLRDQuRdEZM8RWqboE\nGm4Hc2KOaouFpzpZjC9WVfPZzTHnA7PvCB5Oz/9x68pG4KV8xZOzxkNtrr77tHDtO5GNBdv+Lfeh\nDscHFl4+ZboOLwbRpJ2hqhzTHwh3tLdLvvjrUPkQd+cOXGbXreovaDLUos7q+/bUtHrg5+JDywl9\nCINwktlK6d8RmL0L3doCXmKx4BSnLL9uXBkv0OhM+3zIorpl/x553gczzcPXNA43wyZLIQLQW8uA\nqVtsVt/G2b7jOyJj3ozVAHgPNHK92aa9pIwB0vZHks+XuVDUq+MgCKo4nV7eCh2CkpR4ZhxTKsb9\ncjmNWSN9dio2LV8k+OZGrRbnFilfOK7JoRuDVncrSu/HGlTEcvz7SFCNFAPqexlt6W4puyulRf9U\nYowvXrS+n9jibpkigmqbKoQZg0qcHl0FgJ0aO8/bWrwsnjyHtS79fZG+D/IJpGfOY0xToL2kbKST\nX14A9/Ln60Rr212k75E77TJFaQFmuRBLINrg7MHdn0Bo38DDYeFkidXCr7X6PGa2MBBlFkGuyoSk\nHcN63ze33aba/JOYiZydip6wulQeXNiXTtX9agUAegvQn3FaxNdkJgMnsnY8YyCLOcMikhL87+Nb\nhoK7WIITLBwFaZydOfYdNl9G/jRNlWayKtsP+2ZKN7hWxUlzzOw9BLBKWuBAUnpJ0x3Bbh3A1yH3\n6xnb1CD39Zqbs4OwdZCwYeVXZjwS3ebfRlk/+KLkt7IxkZofTqGD2CkZr9MB4LqDKH8f8IAJCjKi\nFt8Wyw+7xOwk611zGhPdVm3rY9B32vBP7eP92SvKGfPdukc5X6Zm2Rx0NnTSmO7Lt9DhJbuS2qU6\nFEnrOcpA9l1snCeYi5a0U+UgMZV3gZyGbp6CDoFdn6DOgNpRZ0KdCGyae6l5OOeIhDan2RpAPIsQ\nncFL28OFdtdpFihptzrtmTnWjceyHWUXJ/2g9BxS6W/KhiogxtZwi2EUgDtkjqxPxdIurc2MJm+U\nnL0i47PfnCz1HXUahm94wrFJUCtVJarZgcr4K/iqYy9oMXsA+mDffABkltARO54/C+a1wq/nJ3Si\nJtOuUA9A7AP8R7HVlxvV01m3+NYyerqhVZTh72rs+VOOC2Wv72NvOBshJKKRQ2XQozTuqTQF2iwq\nk1zy1k2aut/fwwgp65IOHIJweaB8Ri8+VxcLdrvaPpEI7g5RKpTsRaHEgnT2VVcoWnqAOQWsiDNG\n83DEKruArImqTRqKjQQZ+mkMJcz/P9ZscPcMX0qgmcpSMa4EcbFwzsuEKtfHfOe+TKGBkuQCD6kS\nDwO4WAtbrFou1OAZ7twWbZIJm7dhLuRfRM9jIgBz+uudrWFjY3eLnSrdtiqlAGLh+0LlcVOOMpmS\nqjcNHEx7SyTBiFZwmsbhHyFyJ5WPcYKtWvn2fIZzRTYxb2kFNgijussq//aw0mLCTi+b2mKGTXcD\nCQjZVAXbGEvKGOK6jKMmJ85cAuZ72FzISBlmm+e3QUzb1g8VpIAgvvT7RJYwtAy+Z2eaGZ2MMWBD\n6z3uBijv4a14RcLqLPRhdlXPzk6RF4EosqVX2otzqokVTP8Swr3pRrAjcrCougeIfN7yvzCqag4j\neWJvClKfO2l4Voo6yvgha3FqNifwhbXeAs0r1fBJ5kbULK7NqlXTQRmRVy2Ec/0Ewgc4GpjhKdSE\nX5VbZ+MeXVUoMgZ0WUZ3LIV0xF+LcphTFiCgTlVWD9GolYbNl5fwLToO9BZsN4eSMITJ/a9m2P1I\nZgUkrrl84J/K71WCMhsQkRnoQ7dgOegS4MsOFY9gcyVUkMQ5j1wAbyOm93UZ/oGNKRexDRel8B1U\nGTJGkbGIDijLy/9dHzMCMWY2y8eLo4JFCc/aG7uol5GJa8bPJWmWdP7RxPzK/QRsTl3S3fFkhR5v\n9JGcct/AJIVs3GvO1sFib+Rci6P0AG4v5dNIu6cLPR4W5wMGWv1x6+G+wv4554ioRfeGf/QgHEaY\nViOH1ECFayT/S7MIhKpW3fyXLturxDTIBs3AQxLLL+W6Ghk/GeBfv/9zciRp5XLddg8KNzAPYjlv\nU6+VdLUFNE2cB4Sq2ZFCKD43/ncZW42NMfpG1HLA4bdG2vLDvUoOPoEraaML5HpVMNs2ubZ86TmY\nFa2SbU2Cht0MRRbCqT7pbOhw0O7xvxNKOM9E1pLm8xABNTLojgKfqaQZKIEQU/4WC7yIV/IHjfaD\nFQiECT9pKnehE3dgjPCNZKans0rFLGtwAXzkGLgdStUmuyZV0AFCxv+Ff4oH6h73VIZr0Ppg7jxU\njucTsO3C0VOMEzo8ZkE6Lit+2i3w0ojaGhxgM8S4ixm5xowGDVpA5qwmn92PSiGKMHpLRR6+b4ff\nazB8sGH3TLtSsKXVppZqsNq9aFDnCSI+8JvsGF+VphkwnlgTY6OigsgBm1HduVAA1TqdYToBjlT7\nAR0s2K2vAwegudCMplOssyVCQ3pCguSMjUHwMU6LeLuIg0EwrPcJ0C2SSYvcABjE3SrhuN4N/nMu\n9P4zrfR+5BgC2FSBO3zeuBNbvF/DRT3Ncqy4C4DIGxTjnZSOo87u+vLBG8SVfGTcZxv6pWvI1+Zw\nBK0uhaMTx+q3vL5iVypLpCfQsY3wGNoFXOgdheZy7fNLa79IPMxwDRVnRbe0/Oyg1ymAxgkNpTQ7\ndPhwPzFLImKtjNSH7jubTL2NRH0h1FbFf+69GPLbGZr8qSBQpX6E3lxDthEQydWYcvl7IHtQs86k\nks41CivlSTl5TiEoknpQPFaDRP4pXwmpDKEPQ/vC7TvDmixlsocst2ZlyEKtnXDN00FIakvB2Hss\nFn6g/VHHfIaQFg+jZ3MS3Ggi+kR4hDfcezprZB2dtH42iBlESWlsU3ix152ClRApw7idwAOIl4KM\n4X6Yqhwz6LIW4MJeAKBWyMjLIeU2WV50m3Pb78Sem72+BWTxCr3mOJai1I8u8fcs6NJL3H6TgHoE\nmDbAkUZ3sK7xTkgnn1+QvR6I1IJgnm80X8yuQJIaPMiEZ+EkhaMQQgKGTeB0hg00pb8roRVn7nPi\nL3JCIQVvM35kb8wfvp/U6VY5s70EOGm0SMI3gev4y6RIdt9R4Do60DjuseiO3fboumSWC3okiMfk\nDfazpK/q7pmLZjbNN3Qg15kStgyUN4/j74e4zaViZWm7kGinAmxN0ZRdiIk5vMFpcqWmZvV/mEHR\n8N98TorfAtdIdWk6Sk2Yno+tccPPD8Q5+YIEIpy+W2UlpGOCZ2e5LRnkj857NXOPmztuA4lffwBP\nGws9hXIE10IktghXkhsR5u1Y5bqCklTce3HooFgf6eF0+ZURvcTt4NGthp/uQXHVfmUnBHM3xGK4\nukDiUSDCYVL1eXKIabdjIJ/5oHe496N81smck84b4sdLv1MtMarAjBHXZuBlfEvZkEmYb2A9X/Zr\nrKp+FT0hq4NP8/8qBGASFTX5AVr2e9iCuvpp6r0z2NuWrkEjHeBLOO+2KEWs9O1CzVWGyfq2OClf\noUiEJWhIBfk5BzzTtty4AuhbVjFVQPmMyqqODT9s38OwsawHx+PLn8Vcr2lyHgHz2GTiNG/OGbos\nMhR6Iw9umeOIppoO5wLbSOaq7+mDfqsipgqLaZflfxOAG4nlXqPpTpzHd8Qd2EKzakPRdWwysIp1\n6wZZI++vYdmDR4kJ813ca84HZiwaeIfa1R3zTPnnBdMvin3ZPCrOp83e5BdxByxbJQqNuHvCrsY9\nItaG0I+h4/oNk3JtyDBDVUX0vdXR2AyoIjD1oq1ZovFVfgz0vXNftTGQgUVNMLcxBwatmPvESFpU\ntc4cnyI/fSxzXvZOdvHsLYhw5iBUvLfZDCIM/dgAJSZoAIKv1XxeL6ZrgT/7mnquct1p07Y835au\n2ADrpO94JdU3D4VOGEQOYfYwvws6ob2RZgdsOxwwbzwJ6gv5FKWKNaVGcQu6ExHZKXMV5AEz5odL\n8NTXLSkWtjM8pLE2wik+DAwmcVX93tx5YL3FBEoDKIpHuVb+77lfd9emPBuw0zvSWSzS5vGNil1S\nUikdGrJodX2Jc53Aoxfa8u2NVHHL2vkPzogGykYVMW/vK95POEbPoX1qsqdjNGJ5P46/tbMQnra5\nbygezHWqYnTT1lX1BLvqBWkBLY45EQHDeeX8PGwLYEOiG2AnNs0DFro3LGym5mszVXnWZCT0U4lr\nLaLkuF1j9oKBQzbt5VbNgtu32q7n1XV9xJYV+3GsYe9Nb8VbeoY9ZQ85XTcaPRkb06/UV5uX09BR\nlMXth8IQgAnKBmYnexdjDxBiB2AALcXsPNfU33ZWu69B77HhxZvbUSDgVXG0PtvUVRkl/8ZL1YDV\nUfW/bffYKy0rYErndcPleVPw+KEljc1xmtVkxzw5eXyEUmcRktnLxybvUcLIZldR4faiTWyIw6Ib\nH/IHh0FzQKPcspEQIQmqLw3LiUpIJbvmRlR9ffp5nvK8I7a22OyNTwI5wTyAoXNQRkx7k0Lf8nNw\nZ8mbe3+DWttxBujczK+YpPVbH+spMH4evGvLVwqmzpgGgDP/0boRHaz6nHullf0Nq6Bk8tinRD9p\n2h2byQjRwECiriLNRTo/sAzU1cCswA0RmEnv0L03X40EDu+rK0G2wqkfQ9xsfjvY5rlPRMcMxPko\n/QpnTa4myYTktQousAz2Ls/EDTkf5MKzqK+pNuMIXRdVwavXmO5tTSf8uYV+kGAXx0+imaKVJ9+G\n0hFk2BzFcLulEVbTZZJCqsoDK/1aH7xMfS1OyO+/4wJ7SfRSWMoT0w7uFWG6uOpCC1IjjE7iyVL0\nWrl538hhWbGFNQLiZKkaB28LYOLx3vL47EUBiOrjQ1URCBmmjPg26TtoiypBOCeluCDSo3IBVCCi\nO1D7kYQHJcMGxq07aAX9mtkEHowNIb6T3noluCg0455/9qppxHQXcMUccJkQAQ4o91peYWzQTetN\nquyO6Dws2qUmYLWHMuiTf8Nml2btncWqE/M8EBrfq4pRXGtgyvvcH2/BiNu/UBAlWQR3KMZIpx7E\nCusEgy/NEl5g86YJd3jq7V7qpV8ah1H/G2GzNQd48CoUnNFvI8Um66gE1t8jFynksxAiX13LHi9f\nfTtarHb1+YjzIK5RExnlQWL1S9jzVVhYBcnjKP0ZePZYLgl1e10rHwskInKs18R0vgqwFGYCa7Qz\nFx0HxuitgvjuULGohFlSsy1B2uluyAf3rZq/GoHDJD8ZX4jbteSTTXRwNl51LcWCcwzPI97YMb24\naD/f2yu3tVhjjRRDCUNonn9tdloA8keB16o9apNmeY2Q2NDcRq+Xf9kYk5J15mzbl+I5ZWbPUwX9\nwhZFbSqAGaUYYW51F2O2xEtYMi0/1mGSGGskxrhZap1EeXJa6ti0JNgllLTEqBu3Ggg7ez4M8BUr\nEWdQBqTwZHp4rxxnacwfLDoex3SNPCG1s79iddJz/Z1t5+nNEVXYX9QHXaJwry909LNYoDU2lgoY\nhiBka4xWmB0BBAX5Oofdl7YhBbnCnbQLAqiGKbCOaXyuJdLzJAgpOdYawx6ECQ7al+bo+orKddBa\naTlXe2lHOpiCZOamirT+eqjoMBgKDBRS6nmoP8XZSr+FYgwy/Qxg0Aca8s9+t5gNrNZa6POG5yPQ\nIos0Kc6P9ppeT4G2EJyFmJ8oUhHS1Q9niK0n/vcaf6+7gloxQZLjsL4BsvegAbBGnXfxPT/m1SiF\nU3onil/KmNhtQFRmxr2FWwqN/q8BJoqyLMS6dO1sPYA8YmuLaJvo6hpmCtUcO/P+kBHV405YAoVo\nbuNrqChEqDUnEfMpoqL+INHsHPxydtEPWc6F1bCiaTj7Cc2OqZVLwSDMYQG+1h23ob4oHeRipNKq\nes1F7P9lkVQw1kpX5qZekoiUmS9/9CT960leEs0Dwa39zQllvB7u+mQVMM7JD2p9mX+xz7lXgeY6\npHHoJ4Mv/fJz7XCM6iu0eAD4lTAZ5617P1zO868Er69YnWB8Ag/3VV0Fu1dmE6Q8aRawBdHwk4YC\nhctMUMRiYmKcviDxvC0HF4JXV74u5ZCYBoVFmuLEaoTqNZMVjQ+bLf0hPmstiqRtk3mIs0GF7VA5\nQChJn0b8iLYg051O650ieJJzX2MQCv6ArTkfIeDnWWZFDRWzrJB2xrO8FNCn1+P89DtYlE4ixktO\nfpdl5H+j+MvZHP4FusiTFRTEKANE8X100Qgq7dvWfgX+d4qVY6ixImfAdoEm/xKBqUK8Y3e9rnu3\nCxkbfGZzjcfoZIeUOzwmzhCeY53jBQ91px8tc0T2se3swhQ8Hganmf3T327cxBg4hcsZNI79Nd3H\nQ5at4YjXlPWYTvH7O79st1/jqDGQAxlThDFv2OeNvvQ18IYNghnyhUQdkxy89vBg01Vh3ACrchD2\nnIDSUKVbFI6WxuhYwXjrdfvlFeQc3aPvWil45zXNoFMLJGE0B2GpHUTVu3bitPWrtPK3lIyeBlFv\nxyDLYE1Xm/hA5MSYNy1fy+pb12OEsXpog5XcjJr9hEdF3725PBdM/wvhcNkipSpFc46g6i0tGQ6k\nuK5525xKV9y71O6VEzns1jRuQxcXobF/4HPTZX0PlkK4wa+Pd8uPmvCGmfXN2stox5HsDT9DEpy8\n80UgNGskuFYSblZv6HK+CN44AfMdce6c5GYg9cJ3waIioQe3loQOhhe6JKS+ZUdV3C6fI3fL6Etq\nJNTXZbRY91qmoqwpy93Cvb6kvXEmZPDKlbMcSgBxD7VYRZXkw50cppIZPyp66alCLEhiz/AxokWT\nau2SYfya+v53BggARwQ7Zz8yFsA6HQf1Nv3JTL4tow0WY9cz+MCmNGotj8l+8HHQW0tVVIeTLbnF\nFzBugbTMxmL06qUHfbqZ2XWVTvHfABs6qFbpRuQJY1gRteVYLKnNBOqcTlHXaMlOVhfmTR2OCt2c\nAJUX/gQUXeZnDI3lAUR+vcVePwK031ujf1EC4EQ8s2YH1AlfG05rUfGR7b7Q135A6THbMoJhG/Nn\nQOpk/IrgtlQLCdBnknwtjJkzo5i9ZsQGMBRCX1ODbTPH7qTsuvZgTu26dxoKdoQj974qOwTh7uP0\nPqRP2qZkSWshqd1nJcFlMfCWEcna/ytrP3n1XO0a4dHNBv7Qr8MGBifpBI7dDYOppgJP/oA5BbBm\n8Uc2uv3aaU1bPFVsGX9C2W0I5BflvE8MkTZXhQOYJRErugcCfuHSyjWCAgKRklzDG5BShH5qaxuF\n/0XzTdZDHR2IDd+Mwx3Q4CwXPhmx2gvtMRS1b1LG25OFqIZun4zkzmzXyHoW0qvT7iywHDdhbMbt\ngzI/Xo7OpC6emNkM/RmBlU66EOOKAuwQHCUD9//8rp0/Y/tNgsh2NPNCszP4WuB0Fw4jtLEcJacm\nJE148VXJwSF95/v5lDScxeOcHbYzTLLGOpQgqhLFtqXJZG9wZKmgqkqg/1pJKf7FTT3dT6OupUNu\n4YVo5V4RPzc/fRVKjR1SjWdDLNLYluIggcvil89De007gpSbvR70Qfnh1LULhjaasEj8Q26hvKH9\nOBdyCxSrDpdX7DZ0aTy+WuSZ4kYSrXIB+mjA4Pq3w3/0x+fcVe7mroMLS+ig20PF7uNxtFp0deyK\nl7owVoLcD3DfMOC2md2dcNVvqgN5iux69r2wcIYaml3W80YooOftOI4nIy9v3Rum7BaTr9yJOLto\n1DM8mKFDfctZVaT9K27kzwt6PydvOWpvrzHbGIZ4ubxrMpda81rFcdyVe+/QWxB+nOOiQ3ybI0mx\nYZETntmVUg5ekjNf0pMvqVBHtn1mBRttTKkbYmiteIj2i2JBs/4mT5knLEFBS5gwMtUTkMM3ql2+\nZXpf4tefd8GyyM7trvwd7wBTrBLOb09OQdA9ow9+cNQicYGU7gwhRT0Zhop1bxr9t7yVMcq2UEQw\nmPnSTjUqy/fVSdG4a9vt6jfrI+x5lfToF2WAvBMCsS+gGfZAD/Hoy1J3SO2JB2CiLyLFfsok8HzO\nEtaHgycSksMf+NOSZ0lZtyJOt8iwyfXmdSSG6+UFTdEHPaP5Z/fQ2O4RXDAoQEbc18fNDk4Qt6IG\nAGk/nAE9OA6McN0hxrc/pEm3TNLMfEVa0lvGSapkWMzHLxegWIJM1ETcoouVET9Kj0LWocpcnhw2\nDTalKjunpxeE6ViIqCN2XbSpViP6qT5oP937WEbB1TgZOKFljPMTOb9Z4GvhxFpCKzRPXzyCt46d\ngUHdYgNpEnqp4EKJhN9le2dC0pn5BcLxpwAL7SAEuedvjW2M63Y1CzG5xDxnCzC02wDTbZjKfTpO\nrrzZjjAM0imeDX6LwMtBITXScaohIggMAxXHJkBovkTcQTqjNbScYF5eQ+2xCFglj+Q5uQiwqc7q\nhbAc9W+ZyZm0OugxZQSyTvfDuHrG1USBj3zDfh4g1tVA8jX1l5KCOK8CDAJQYY8GKJxGPhikV6/B\nokvQqqlS6xOrzm9+79bw9YSdQnd0kl+5YHWdEy7AaWbcT5emrkS/bMv8Ky3YbEgwT1uv7QIWhJhM\n9ZV4wuL9uwuNOVSnO675CvQoevDOcIEtLpWy+06sGLGKXCMULmgM9nCKXk+ByxEbIsl4xMj7nivA\nW6YvdQFYnyLhn576H7ZnCnlO8qXyySQDbAULrdV21J254XUopgA3oVn15NmBJWgLFTNr9ncvh4A8\nmZEbxXJd9ProGd/AZ852YPfsIwK/Hhv/DwSrSJXjyix5BwZvYdkbPr/quzsLz865pgmKV199JLyZ\nMmMs8BHQSEvM/QxtHOTfPmJ6sqPLPtpNOPOJjiftUDtLJcV98CDg8tBNAhrkIhDwZfbSSoUu/q69\nAfFBGQbM14dXA3xlWereH40VPLfXlJKM20YUkEkJIUZfdaK+Tk3FWDBWuE9XGBjb5YReY0N5MgL0\nmLoCtTdm7gt8sgG9WoiER7784a/uP0oiio5La1Eli6LlNxAJHOVZ+67hXwz3Oeb+y3WIAstsID/S\nKSSP8zZPKxhCJ/CmEYwYgkeWs/MmEdmCN1qgYW6bZxxmWpD3xzkQXP/g4DL23m2TRp9jRLCSVp9E\nsVSazq8bJNMI8PakaqIo0fEGItSYeNtA1pHSA3iRq2deHHjXwxdI8elwB11IF8WGNa8c7scbxybD\n4xPD8HrXmexZ6PnE2ukzndgcycOe9XqTcUEwTsc3iom+wvFH7pIROiAlm3bYHFI9G98LQ93i/dnQ\n+ixRaqzuCThkDBIX7dGPdViieJvN58pd9GQvuf43xq5OM9qTDz/3mKMWAhjJpVU9QyoDMbJBLqQz\nfzB1L4AXZidd/3P8AZ5GID7cpy+IEjlkpGpiX+tgr2OEivwzUeLPlkTMRxrWZ/Fk8+G8qbb+MN23\n3yu5GGWfhdLvg9wJwOQoNDQ53Bd1o2EOOSXfV3bWjoBvlwwHr+HQx3tv50f4vsA1ociye6BpKWCl\npe2qgdPbVIHtLtiZ8fyEPMT0/zRIB6pbagJFQ6L8+IZhSlXle6EU5pQbzpYToIgNXAeRMMncF8c4\nF/24QwN+3Is+Fb1G5GKa7Ik5MaG2TrdDucH45PbV3adc1lk1lztb2yKM0zlZ/zkD4XgSBGrTzaqB\nwpNWsAnzWH29cvzuXcfS84U8hk29vR90IPtQVyX+w1FKeK00+S7J1SfFQD43FVpvoyh5stp5u0+d\nHLtHxTKCcgoPObAnWzUbTCWhU2y/zKhmQA3HRD/judrYxyGe6g+4nr+QT6KqrzrkmlNFhQXVSsZS\nSRbvouWdwIpwPTZ6IDBCKhT4yRqeREp0UY1m1QS8Ch2/mTnAAYZo8vMDAOGlyjDQE8LW56sKFfYu\nqLAlMQSe+teaKbMrx/oiAB/DFE+1nApiB5tW7LKGnFXxF1Tmij3w3FzK313WtHTUhKoDAZyjka3E\nVeckrhvVCQGd3NrvKWi15FvKD+LpphdNMIUVx4WttkwY1TKSEqv+u6j33YrRQnKMEJr63AFEJESx\n3XBD/xe9FSbykSCiHHyb+53gXm4K10G3jXee7hPWEl1jjqmZrlxgR3l9M+iPQEes2/amB8JjXE7u\nO9RFXDwB1hhUy2hfeJX/vA8kDrgijUonmpXvwaZdFPRlkAMeL3b3ucaCpWqzasSXbYiV3C7aU9yb\n9G/BXsjkTNmOw/8zBz+qeLJggsH/x2qirnYGbZ2fDOwj8xKDL3VewpuwKkXuEZQMb5TiCoJH4VfE\nu/UZWfSDmTSHIIhHqEuK2RQfPHbWOXW79nBnda+keXuPVBsJ6upts7AbD+zdvCE19Ngbmi3hQwv6\nxnz3JIHxt1r0xW6fpsBN3mG+Bb1MZn5MNkqgHYyC8CNLbBRSeL6bM75kCFOntNiC9svxagRDN6+Q\nk1cekBpKdp1gily9VU+5kMV7P03YXvRu8RL7q2Ei4EWHj4XLKwXMexRhI9IJDTdh7uGYFb05whRj\n1TMBzJex88OuL004tpivgXRL+WNykzLOhxIeEBHPUrcvj7ggVOcZ+TN5WD+RUBkStKGMh39JxcQe\nRg9RfR4GBZKUYY4P6zfytoIYs3ie19eP1Davdz0DvecduHAA9YNcHykB2Y06KRnVje6X0EZZnURX\nzlwlwTay1ICsMAb4/RJiYcjNYSHTgTxSJeEAUOkB+5jDQx8AnpLcGgsjrGsF1R3buOLZfpL78tQ/\nV/jn0rjPGka1G+y9JqjpZqB8Eg1OnM/2S62wp4cgC/fjeLtECNtjfRHg/OFPkbrh1W9zyoWHNXv9\n4IQdcj5iNuZ1aqolMg815867bLoTHCiIJPX3k9FSjcxqT0Xktn1SV6qAIdGrtdbotfgqs3yUpn1k\neNgbKwZ25rL5I2GwgNzI8frnWbs7fTCDIQLGjokD85N5q0JvosXqML/lBJe6HucNw7TnBS75P6nO\nmW5cL+taQuoeCpiLzhS/AHzMP9tgellBGmTJ/5JirKdXrpFuos7MyYFmMcZM7zGH2+CxFcXcjwzj\n1cqNYLDSwpUFpKGV3Fihj5BYM2l0gU0WyHwV9DHZvwzXD79EX0lakHNL+Qu8C+Ces9A0CqAFT7aE\n/GtAQIDlz36z/6IscCmfF7fHZDgkUUx2/9CWN0P4O1JHpDvKVYCa258u0kC3l7K/dq+oOb3DcfQX\nGXPRBuzMyB4hCrx0pCCdnqYN1JOzROKx3lTsnYQSjm8I5iMJBd6+gFkRYGoYbtJhE2yFvIw6IxPG\nnKx55a7uW4frQ6zl6TvkaE2FYb3rjwVoujLroMHoE7bnMTrbCraluALQcUJ6nPjW8wQFhVCYNyuh\nRUYUZIFAFZ+5vd6jRQhKBaw1Z6Y0CcC+Oc5ZH59ESEC92ASgwWpsHVqcCGpHfeb+gEWWzZRVd19E\ngPsqaYnX/jJzIraVQ+lNSfG8l2RiK++zYN2E4WgDyDKnWESDNd+RT1GKEehP2ixszSlYduicFd2F\nUhG+eoKqfhNy5Mn4dXK2Dm0SZHI7pXA6rL6G8jP4NRaZlGbmfo+yGOA6DV0HwWCzvQt2LgZlFv86\njdzZVjCxurSGYoM+8bJHrOj6ch9vmBfvVTM8T9tjup7iuj5aLbPRfzMGMvrmbMvm+ejHkhVUw2p7\nlDb6nQS92WxNLXvrUDLL1B8uDncAjvRsZLwBB+EFkDSmJG8IH9kTbhiiHmY8UrOreZJKfZKyofkb\nrmPlSqsvRllFenC8BCJm8JdfQcPY1gT8RiKb129BNfNcPDc4DifFtiJ3G1SPhQLNhExz6+s8vqs+\n6YSej5qswoh/RZUlizPz7DJrwuA6v/sTiAMWZVcVw+Owbju7DLVv7htQvlc7P3K+Dp8NOagczfTV\nQpziDIbcovCjsjWBkhPis/Uirzc3mTZOTLrcQcPFv5etrX895hmXD9DGNy5Ka4UBWN+E8aDhoI/V\nEGgOqbpGpEeKsdhcL+A1hnbvECuXGLGnyAYlM8pIE0olorKJ2zaegvpA5qf6gdyQyDTG+HSfTBPf\nNVNAevlTzX9HSfEFR8x+/8VXia8PCU65mg4uBZYTgjobMcykStjfgaYUgeEbgSGvcg2pnc4lE4mS\nNs31+NfVUiSuZhqNDUq/1SyMLLfV+K4lYHbaPen18Td40mKlnY4uX/y8773mvJeNkSWAxlJsyZCM\ncT/9lQvcjAJIFRQQAALG9fEmPPbjUJg92m96BQMYxvi/p2JGCWMWomgOwHQYTw32Ko0FXwaVjePK\nETCRU00kcaneUr9zfVA2ZREdWZHfIAOu0MO3smSdXf8UZZaQVnD9ahpc4I1E/0bgoe9we03IN69w\n+riTeF/I2prIB/q0GTpCXrDiBWm/ZK7emuot2FrPR5pHOPx8u8oKg3JhBq/uoN9wERV0ebHcK74F\nxYyLiK0ACOeSFq8i6NJ0b7Z4i7JLPg40M0xYUJOVCnEMmVPBELcO7wT+LMsTnnJcS+WhOkpGCM3F\nUCRYyQ1zIP2EuQuHHWgnVhNw6rnt1YWXB2UoSroV+BKDfCqn2TBUr7jDlh8ZzQGu7yoTd/nsLJDw\nBcQVj13xV8dlSdkBQnCpteCe+vvvcj6etKIw3Fr9utyk1BZiigckv2FFduCpUVR0ebGTVahxsGEB\nHrVUbwmOiOKHV0S4D2M+jdIesnzmodJVdllS6mMy3o89dO66nVR2074aW+ah7HMPPY/5AsmBzAux\nbIl/C40GaCZSDfwpXoVdtgYw4alqo9AOsjFqSMm4LyoyuiY5CzeuWear1wKLzNMmq/bIrtvZJwDY\ne4yFUBrRZd3ku9HqWmPnTPmzPbrcB11eN7K+yGW6c2XBWOHwRsYXKAZzPrjrMOiWJ9cWL8EXvA/y\nDelbhZM17oB3GiVk3+I/SaBPV4WEkH6o7t5AhK4X24VAeWDUPCBbVkkbrG4F4WlRU4J5ad/Uibcg\n97SNAS6LjJmTH/L4c4qKni4q3PX2arZgNUqeE7+FvS+ThxssTLFVdqpavwd3Y7dDh6QZGpg0AfVI\n8NUjDSWHRbl1SYQlacUS/t14CYiwumwCORpX/6HHAhYKyivegfMVVr/ojqgDCYZlTBF/WOmsEeIn\nYAGja7Vzc8fBu80TMAK9/ZuzkyWVOUDzveK8Tdalcna1joUf44mfmZgwXcVQUthqp7T1pw3gcc4E\npkn89wmwWxAYI2a3RTY3uIbB0yvUtC0+uJTJOzLXy4kv+7m3RYDkQEL3MsQcaxd0b9fkYmMYX359\nrpElccPLP5hIyIKBr3P1DsfMJx0brPMTC6hmwJFympb3aei7ztHMN0/VJcOkHcWdjHUUyUmgqzO8\nOQiWnKW9yWsWbZ7zqrqGz5Mh97A9jYs/RkMhmp5rY9HtZf1m5MseVAKVBfXGQGZ1MpJzW/KuvBDl\nkVblFLCW31ZoWXNz2rTZkEGqn8N7UmrvJO4jIDhnWb7LeDnfLXQSCQ8ZAtt7sP3+sQOSPgpbXVuz\nXhK0HBZeS5IAlNAgpGjI0MpnZ72g93XciVNrV392tFFmJKiHidY7DSvNxc3JhcFXNrJnOoQzTCtg\ne8Re43UcrY1QLXjHgcZ434EGZ04zmquAn4PUFpvMhloiqq5NpaItu9HiHCZvyV/Iuv96cOjgRc5J\nk5A96ewTsrYOZZhW2TwwLRg6pe4/nllTfl9BVkcPPaLgMpxMP/jmHqDN4K4oiCbdgAUn8fB6u6KJ\nGfgDVsLfKpfKOsdwP4xe9waA9gV10p55bCtd39TWBH8Xhsxcp1xhHqoXMIQvr1I3gGvh6e4v3XBT\nFIGhZRhY1kxhyDncLKeWlWvwqtUvb25Gb2zAcaK3BDf+DYN7fXvmFRKzqLPjamWjJrcBQPhW1cqI\nC8WL63SaZL0wdycTwA6+pCTazmEPmjEQtR9QptJ+wMIFro41Zqbx+ZAr81l8Na6Q9sCIx1Ux2yW2\nT/zqCh3ZVTxUUFjF0GqlnkdNfsJLoXIlCswZ4lw9G0HhyISewMRqn3gX7BK+I/IH0LkHquatNDyV\nBYwPcofesjoG3hxrlvLLsbXs9y6SsGAXz9ofUGYCJSepTIHhJEgAOPQk/2YpC+olZubJfo/w2YYU\nL0gSL5uAHzBQ9TICaxmSB4xUEF8NfuJMZ7xc89NG4L2PkOObah3JLcacOXOR2bJWN9kquWQs6Mww\nNZtfUkbjXuC+pgRi+IT935odDASg7z/E2Pnf/sca0evYMj7UfHnlyqkx2oOv8zqZW6IERY8OwxsI\nWdf5BeHxE7Y3sp83EHMKs7sigeAQSrr6YIqFyq1iAQvDTkU/UmorZdcaGeR+beDNflnnZ+n6dssy\nI2SyEYTA/WgwyMn367sqXOQZhPacsMBjFmIr6Ay8lAsuwmyX/y29PWyhFpshLIjxAEgiPJwboKTo\nhi166pp6gUvLZsmg+38bRlEgdXx73TbfQx9+WmX/d62q2GL/IbRiWInBHxDFqkAoIFALSwWYH3SL\nF1kwsCNZ0zhUqufjsersZYzllwsr7OC9KO/l6cAenF5qIZ8ehep1HMBT18o9+V4QsPcVJYFGVc7o\n9S/Wpq+U+kesBpNxK4UHq1WaNsgj7lz4dPItnGO3riHuUkj0oxFd7Ix5q3GoheVkd7gr6avZ3P41\nqAUFvi/mV9efvtvUiR3GLiXE3UwuElCTpomrepeprwHVHlpyfDVp1G85HNbvp6aP01EpO99PljqK\nLLHBsclxIzaML3H33jHcSq0tcpxFMyKQfFajsnoA3UViWHbdDnfYCJpF5nt8GL9l9U7QOoo9IaaH\nD01LPUc/Ht1y4N9cisul4DeSSxO0vKqlS6pl2tiyR+tEgIZnSI7HwhWMfNHZWJWhrpp4/EeREYC1\nEJlSVHlccf8zeRp/AYwROG3YKvqZoDwEl0pT6QEoGln2QHRwbJnEibqy1CZFmM3chp/G1qjvWQQy\nsgnm4cCUI3LbwT9oFzPHm7Sv/9AOy/HRZfwgkDQf1sZaOOJBYLjfH/rvphGiYO/dAxkM6psaCG2k\nXzEToIHRm6deYUOb4NKFusW94QmkAaoM1jf/20Vkw1+t/0h8BfkPxIxbgc8pMCx+lgYUdYSvTnh7\n5LG8BeITLbYWrHUBE+ydH3X9zkgKaquIPRXqLeAmG8M4hDBtVICqcCKgmQKXPY5bLzNW2FUEEVcD\nTZag5fuqcxlvkoTgtBTeu7XAsNI655+1gisWdJ0QzIQjQI6VSycuF2zwDFm3ktD6Q//AMufHVYUk\nlB3MBLeKQndLzM7ShXVaVEOSKRtvAXiAVoZf/Bwtv6AdbeHc5lxDoptz5ySzNGNSqh85iqCtg4J9\nhyuag2/MPLPeIMZbhG66ImT+BrRUZKZaTFcGfjXJAKM0kLqxm1ohClMApk8IDFLedvPo2N9sWGtd\nWqBcPqsfp5GXj/4dJQRpK89dxXlGEHG1Glzd2Apn3FKpGF6rbxOpDZpB9vjhtXxCssolf2D4UcIb\nUED2pYIv+M9CgWqOzVkWDM45hPrXMQwi1Sy6u6jj+YyXroreZoxw/BpjmGWFAdTlV4c+UBGLD1/Y\njgUXQNhhQYxD8WT38zPJ5V9clEfV/TwpJhywScOtbkYYpUHqHTF9XXb1zk7QggwYQ0BJlqJ15LbV\nBPxB0Y/NzflZ4dxDs4pIyXDGAWYIhMPCQjRQXXMZMRp00PmgukbWxCRqBjhQB+7ucyUmFUSipcDd\n0Iaf+X1awiqWX6W6tnDAj6K3lTrzLBaU8k3wXY4LlLhMXSmiw+RTBqLnjGztFWAZB9gi1WM7soSV\nTXnP3FMgETbJ9GUrN5nPajQMGK2JuSHWhFVCx1FiYyVM1Cl6sPiWGMYOaw5a3CDdfARHdC81ADh3\nl9394vIQZumCDg9DEfy/Cx8BXzUHDgJAHKI3vx2cp0gWwDlBUofRRczrg8QzxYbhnYxuNXUjclcC\nV6rLK4+zv4EclXCnay8JUT6XOygYtkoJ6uE4hkj5/rlZ2w+yf8kTPqN30U2xJhjrQfh4qeI0R/Mv\nx7ZvN8Gr5UT4Pe99KnXcTiLWxg0uWiKMn85G8cd/WQ3qFQIt3DWhvI44p4+qkgk4HLaS+2wuheBF\nmYqMbk0qgd3ie7RIx3HIna6RqNwk0aMXez7WuwAEPPgGLGd4hzAO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v/Zx+gK8rHq27dQP\nRfvPUQ+GB6wCz3gBCRVN2+A9z6W90X/rYTdg6Dp/QeY/372BPSG81fVid16g0kRgYrZjuu47qGOi\nDCD1QuAPqTVhLdA2Oo3KPxXswKEwsuGT5WeKSVg66RhtgqawuoRjw2RTw37j8z2KzgXOFRTyUf+o\njcQHnzwosYBy2NPbCMDQcHFvWvcPStwm+aPud0H+/kAeJCqrBHmvMAHULjJjOFaiBo5zsUGaqX+o\nQLR/66fzyeolGCltN9htjkY2D/F7vNWvwvnjnNTIe6TVm/w0nbhRJVaI6bYPr62lOBnO6dKyw3hD\ndbAb6mEG53YgLbIbYrqExhe3o9J5YabbLT/H0XVUya9VjVdJJiDeR2fQf2qHlk/57uLAY1ly/fb7\niqnXHIEvONdwusRRa192WRBixKsDLlx2Wx7Z+pDhti/Wm5wAcx9DVVNlPXwpt3eM9Oh1xbg5q4oo\niMFFxj6CgCJQD62gJKqgvYswHEmSj30fDa+kPrQyQonuEbNpE4GM0d3eJxAW5jzbKvAcnuWCSBH0\nphyIzm0kjyE3UXTqi0i/mUvvKLDmPMyJVucVi4p1jX0f+eyEKRVmgV54LwD5nh7IeWTifFRXTaQN\n/S3306y451cAJ7beM2xndbIVr+5v1dMI+POsLzfLeVIhJGk+uq7zwicsZS50MiHBH/OTgtV3sDqq\nrPKmzuTcXRaIvdi7gycJ3sigbuEJflXlOLI/HRH8YmykrtKjwGuDJtekztb66XRVg5Xos4B0MhSO\nvzm7VrOpWWlKsCMiFgljLvL3dm5fPdoc6NeSV1+JDEo/ZzxBK/KsOED7WAAgDbo11eaqIZIMUPFv\nC4IZQTGQqqpDBqI1Lq7EDFotccKNZvkbntHL3jveinl76LgLrY2nch02TALxgcdrLJ0yMhNO/sRL\nPeDtKmjd/s2XyO8CSn4DkgzPddNUesN4Cv85viwAOckd96x20N6xVR5M+eVDcAeRYNhPYdWRMsDe\nisb8g2sKeetHq6+gqFQ8CUfhW4iVEJKSzc5FH+KlpREgAu6FLfC8AJ89zjo6apJhlS+OKZy/5AE2\nRs6x7vI7QUU3jQ55TSjDtlokk+REwxt0194IJtVj3WpdXWtkPfBd19oG2nO7KeHgZvhjM38WGNrY\nQt7/rd4UYEddJbk03BidZQpTnRoTxO6iuzeekLgIfTZEujxWl8D+oZEfdIYq/s6p9ALNnJeUvS+F\noSD99M5YHM5szY2afpegZMkBaUAox+R8HnwS15REVMnd5QmLNrdIsbhpDtFK8pOpzBk6eGZyx+Ic\nplbeMG3UaAUnvDAKV17UXLmMt0/EcXzMchxJqXyx279hoONfsdowL7xKbXCk6kUYXaetZMtt2pdZ\nIXnjvmjbk/3IzXXpBiNe4oavfjaaCnaYvvFGK6P5ZRKI6K9kFexI8+1iae3WFfAC9IATVvTVSSRl\nDD4oS3UUJ/BnMwcYrBVBLyNrA67hAl5dI/i614e8Aiw+NcBpTKpfNMXzbk80fl+X7GNM/MuH+ofJ\nc0yIUHIbuZrbPkrgGft5VNJvPXiGT03p/yCWfZNXHrNSNa2f7y6FRP1DEGkNdKGkNqb95cafIPte\n7rOC3qcIWFBSLlZ4bhECkfzkdxXf8E7HkJsmDLJUqswZVI5hjTbs8bIyzl4uAN5H1A3w3i4lGkwZ\n4MaeK8XN7WhV5enKHZDYgTzlwPkc/0G7r34R5v8t5iav4sP7GVNqrdpr1jFa6EHZt3+KQ78TEUni\n6v7/vAaaYUaHo7scWDtgQeaRAbIs5dMMm4I1WJIogsaRZ6D72bARTEYb4LULVjPNSwd6XSTCADnz\nhE89VVAmwpBzvx1VJdAMID/UgB2LvgF8OSAAzq/8W9heID9ht+e69ij1YOoZSWS7zqRmtSPmAQ1o\ngbo3W6n2Y/+m+r/jGeGJ8SDjHtQRNcNxrL96wsxL2YvYn8lvnjd+/ET5XKcFeSFS7uioWN2cgNyO\nMtqSZbINSXDD4JKaU69AcJhtnamTv4nHHQszTXI/P0qD7Zw7HDuQ+Yhxy8Bb6deOtWHrZWkJVVMc\nutzmy5GXJpNJqYyhRR5WqHl6MOgRvdApBQRalhQhNbt7oVO6NcPhux2bPVVVu1PJ6IRxhnxldUN+\nbZidnazc0YaS2D2Hb716A9lK0wq0iAEU8wCalQzjj/w/a1RSf908QWnmSPVb810ULUzm6ptl5dAn\nx2+r7lm+mVtNBThPSw62kgscVI9Di+qJFp4qoTMNL10ZnBV4/HoLLYQSx676sSSWGO7BN9x77yaA\ntvOTim6Er+SFeYmAYX4dcZCy7bsDTJAfs4iaTWEr0UE/Xr6wOibivD2ZxgYjE4aeZ86OxZBIuqgM\n/BHmvcBxXeMU/lPpcoY/rrES04u0rKfyBdYWQRT4TPS6uJHWhbVde9Syllbo/xDTjb3/chY7ifgj\nlsdUWFp7aXr4esdbFEUtuJAAdrCssu3GnSNwEftr8dujZ8fgut5vGl7s64tG0ZJTevph77fn9dwF\nxKUvzzFvCILge8O+Y8al4/pC9mSsSup9Y8ZZTfCKqXZqtW9oiSkHhsDU5lT8ZXGEdWr7xFysTdq7\n5lMBQ4zJojmPLLUqsqgdJB+6lUWenggKx26ybdsrBjzeiNuGoXrypXzh5vzsxP1ycMX1JCU9ON69\nty2rKi2rwGj+q6xgPWnmBLs9bTownWFg7gIc5LO/ZgKBEY5j3xVlW1DaJ4JSVgKf3oy7fsPwC77e\njFXz0ZakuSRv1vpCW9d6gZge5lsWDsJIBU+aWcjRfo7/WlEJxXQpDeQ8qskzHHkehOXEW6jz95Xg\nIN/mdJEXWl/PedUt5VyfQKQd6/nTRtMgRuVYGW/dvkX1iZTduuos7hVi/0JM3RXkY9yoLoOtR4Dr\nwahHhz1AIkFOgtvWEZYK3l6plpHlgi7eGMcX6iwYgbDtUHQ6pMv1FnMrzcWsYwTmvN62QVxmQ6gL\nxqFBa+Oh7NRkFZPwfTlcOCsTU1CNKxPEEv2iD/2DB0tucWcjEcavSHTy5jjfCMpT1L+W8bGhkHsj\nJRc4G2K7leDHxfI1ij6baKw2JTK4anGS7Q2TcB0K2IyFWxRoCyMZP+lPnH8BRiLGg/K+/hxUKsox\nb7ddVqLtcTZ4KkXSAKRDYVhrRNmdSsegptePk1iNSzb3cZfoGrzvu/NaRIR+TSzzMDlKvc3Jo9ft\n/B27rvxsEjqpqduEZ4WDm3g40rf4QtAaJ9jUc9HgVynrsHd3O0lLLyDfMChnwR2oVFT8OT7R/mGR\nmcGt45jisgwp0yN/CM+PbKcxIZ8P6vN8DgZoJuIC/8h8NZe0rNW0ejW9nYr5AcycsheaWKnxHRi1\nqUazFAYVIuPaF6isO0ECGvSUUeq4LhASArp20woUAkjqQEhjUXYC31cxVkH4pAXM+4X5YJDcsyPR\nu6SONK9vHXgvh1lrKEGmDoqGYxMBwIlXaWgSOhRHMSzMpZEoXbUlKbeXLMnF8P9wx55zA0U/Ln4/\nvkDPNtsvhsf2VgXxWEk1pCm7XaqQohMu3NBYHoubV3pTFdUWZQ6HBbfqWK2y9qDbJddShglbRfGZ\nT/mSKhwYfQsp3tg5gH34xYNfCZl4fRrG+dAaJ81ZRNowXdUqwRydqmZH8fKPoimSlwD/PTvrOFtz\n9u7/ktOsLCb7yPmjtp0V0XIlGYaG64S94v8gGg+0wIWPvIpmXJ8A2pCDvwjIkiN9j7t3IzGB9SaW\nsgRQNS2ICCvJ1zS06b4vTmxEytTZPyP770n7uU2HEZXE2x3GLViLnFxVq+js35bixsFGPak78p+b\ntrqfmlMUi1guE9LQUAP+1cG/sLPWkaCj0BvCl7zoAJF7Os8zD/lbmyGTdPYb69RBXg4zuQ2eFDx/\ncjY2LUg3sLWyV6VKNjAdtMo7/CPtFL71ZB8hEcF3ATWajMmqIE7ln3IHcbUstDBMOOApNvEUwfhK\n5nOsh7P0AKWkAGY+r+h8waJ8/Vq8TmkdEc0rlhVgd6/7qU9NHMitIpNWG/U6wwKIlpWtG6R+Emff\nBGY8N6xNG4mHR1TL2CK73Y0tkwzlO1yGdSVaDGEBcjoFe/GXb08XrXORHtQnjZ7nLWYIqDIPsoPT\nhdxdMl+TpFz+dA7RYvmRGQP0OBsEiika3jR0IQXvg26ZQOdYYqXIXMQrQGDa48O1NPlTgJpjX7Rg\n/WIHpEEOzAM3sti435y+ZRyO1CHyLLxKsV40/TSQn2tUJpZITvk5bqMQgXifdWmsb0P6aeuT3Brj\nMvP0Dus2NfX/qmGWZr2AeVadF7XuYV+K+1NThraR+Dt14/kEnbsO5AT6CRLRAGfymPYGnMJFPnWT\nqCjlsRIenemVs4G3vIXmp1sfjr6Gfun9e2GELFovfxZ0l20ztcOVqTU/B6Jq0WCQyFP91uyL7RR6\nq0qrRCAmgwiGk+OF5828W7FLYUfZN29tSlLj9cJlar1wKAFcTs1uExw606bomrhSE/LxoXemGgZ1\nHaHHuwdksN81EI6aC/mt+kHjg6E7cfKf+ysQfwZWSXCR0wIplJp0mLUPZ6tzwHpJ1IyK/Euk0Rb7\nyUDCJC5+JjyJ1XG17zoVFa5NMObDUhNxPidKqyEYM59S5CCHDG88yMgpnlB17cg7ziu8dB4nRZ/V\n/2aQF98cCcwM3XsAZAgzTr/EQOwwfgWlZJxEohqWqCV3zdXiWUHdooQXJqikeyJPUpXNpnSDitv5\njM35SBH5/j9Ilaansn0kvcGqog8s/2GPBZ86uEmqvqRldffxmKRU0pVkBHqYtRWWInYKG2EETVeP\n54OErUCvshl9Ms+C8xwLygF1Xuc89aH7Z2RmFh7LkTipqlFxpq/M2sHVOyiPrrUKn1Lo/P5/tgKC\nHkiXUWcOZSvOUrNRdqpiM8vBLt1FH+e6Fe08j77liro8Jk88/r1u3JHk8EVeYt7ry1mAwRfqdBMo\nLonollB982dKaKQaoo9fxYjJEZae1Kkbvkd/H1mCvUo+MryxjUICVAsrk7jd2wi1C/ebQoChOb65\nkMzNu1F9iZnJedQhA1kA0hpyKl3TTYZNM9TetHj76dHjBF/SmOyA/eLPtm79rUQ9261XLEEQRFD5\n/d0cfl4NEe6Kyclu91mHfoWdeZtsqJNf2FBeYsn8CCGgT6tbIMlQtSN6FX6wBuLX2JxrLtiQ4/jO\n7S6/h1JM44i4ns/F++HYqQ8yIvrMbnYQ68U1CNN1FfPQONKV5XHBd+rIVoMpKS8KfJy0VjCSLjWz\ng6lwb17nciz9aDojqCcT0iHO5VD7lTwGmRdK6DV41EPJ89fbOg2/swc8YU6ycuwbdfWALDDvfgyn\ncs0m4QkLld6eDpxECvyTWlW/6XAC2BvwOPwUCG0IRPsxwQZ0RX1fbcx39pKMRNkZXuPX6pz8aiQ9\n3/DwQ7htObm8kwW7bl9iiF9i2uew3AKiUm7NNbz5+XGwaQ+ibJRZI+KsYV7GWXIf7v16aRWHWycL\nrV2/iYDERvoubykYI/s30qT+SF9r50PH4dKkqMG8hmteH4/grRqkyVa4PFoSECpF1cGcALHXCVwg\nImAmAJHkwNAUNMR7DNoktzkMjlzGW1+Hx5LvOkxLNo7jr4zkYStWnTPI5QkWE1IxFW8ENisAaBfJ\nEsbOeOiAAcs6fU6S3dLf4qUaWilxI5e/SBIP2LpWn7rbLltiPVpGY7orFO2/FPV5wkzRqdL1DNV/\nkXKZhLGITVhw+dXrfbihaW3m8g5XGQf392zF6FolBU/3Usn59q8LW6e1xBW6q52zO8I4R5qiZ74g\nS0Lbfq8E4mcoHXYm2/9Zyb+bf6wLUwYHQcaOt/H60B87N7gz2jvwSPXoxEz+nudwtLPdSCMJUMNh\n5XMN59tTU/HfPD3a4nm8C1D0m45+QYb/5PsSBPWn7ACngXlouEtyk3TN8Afi2xgLoe17qlTVkWQQ\nAjC2rLLCKPYPuiB7s+WoYCOJ5izrOWNEx+nu9QMKXjy/RjCqCpq8VULXG1XcacHHWNhjfr2E9rrb\nwZypicVgVxg/0Kq+Pcvg1v0Y6AK9LuI3W1nvBBXxDQ1BqB2/K7bD8+l3xCnIyjq9tlCNtE3SXkte\naCJVJBlxRgifw7EfyRPQtlEJ38lcZdMiV+xlVWRjPpbK4QNzcb+Osc4QlXMMc7Q8NrN3wp9Okb3U\nuM3l3GWwtYbREhs1Pbmx7uUs/PUvdrxBMgFUmQhXk5fnug2i9kHXa3gXZ7keScbnpMfVEKbhOc9+\ng75gylxATVB/0Wtj/0kqVO9esMQ8SGy4h4LbZi4GdW74uh9oUuNMdI8WHoaOMBi2uvDZnWMlCvoy\nkvFkrHMx3KZRkdvHRgpYg8BgblsAFs37pEIyOjxOBHclR6Z1PtlnK7umTH5np3Hytd1XoSq7SA2c\ncZv5Jz8OyiRBjuL6ePIQgp8GBQQTovx6TYdGoMRnKKfsdR9zKTFbsHEgQaiRHGfFNMtnxEfhIQVv\n8NS2BnpVQ66CMGYM+tVLccJVtw52ZNZLWRQ3hazdc1+O6sbvNTfruE9YVeX+T+7wEr9wx1xHsjDm\noolvdH26FaZ0leX7yE5B59blZEJAI1wxkbXYZsjszg7MMjszJbglIfUZBb/QXaRSWwItNvAMPde3\nxhekhHVKCqQUi3Ym48viEMBBvfn8fdnPbCNUIyQ6AufJIpe+cKy62QSuESK6qU++RE1rxnp0NAZF\nMTIHDjkp3p8i+poB7oGe3PbRtyQovbB3earKY66oCfAqVt7VKh3yoRRxV8MuOZfjY9XWoNr+CaR+\nMdd3DO+0ZN7LuxgXl1tOHI8fL9OUu1ma+2hQpwSrNTrreR6lAFMKQXxjeWaZHfP1fro7Ug+1+ysD\nEAjIzPy7yC0mO2w7B3AWel5yXwz5jwfMAeaEGonpcNCx+v4Q4BcTZ7WOGccqjNcZmnDWpozmISCY\nhaOheGr+9XzYZvA0uAlcKm0mPXjTY6/z9pyve8ZtkLHq5T61ZMlVd8Og6ZYC7ClTve+IooOEyChU\nUtM1NraWAn72PFEK7ioKI4Q2gxJMHXWWOYOdjO3wtrByDs5fg7CZtZNhiwOp/tAsrxKN1GbhJ+2n\nPmq/lXc3BOlOEAnE5D8v//OjZEEA/o8OjNG9Yiyn/eh1oe9W5Cdp9kP2sqOtYF3h+3xShQerX15+\nngP7FQMCHXCSPbXJzd+7lSKMgIm9WqJu4ai0BS5CKoCGxS7mEClW65BwOSGenJQGFqahqfghX2bE\nsbWHE6Dq4H+Skxb78b+4j9f0aRowC7uwhFa2oz+8Pf7jvkG9CbAopwqCbl3ulCZkKp57REmnRROR\nwhaGzqRZ7BmSLWJqZAzltk0aqkodjanOx/hqasqOL3e1CpGoxeMEjxPFCh4dNqMmyx+nAwoFdT+m\nUbpUwP6Y5mpfKZ23uqjJo8cSQjeB0OIpDFvI3j35aO+uxHRKFDUIJbqedAIMcc0bz3ub+UZ9UB8/\nk3sw7v2Bb5WKZNjqzgDpwYgAnn9kTC0/J1auilmsxQLZWSqpHQ6xgmtvDUVNyAHI94QhvoxcKkt1\nvoQQ7SyylEo9YtIvY+TRrUcSxzB4AI2UuPGqcwkvPkFFw9V+IjOKLBBoyRggCntN+uV8R/Sw6/Ud\n0PXKz+11Trf7bfSxL2eXMVnKH28CfLfrqlTgUqf6WJtnJWdJ1S1nspfXnp6XL3jb+zWJjZ2AxO4s\nGLyKgAsASCj3ykPbEiVrjYezkqTCMP+Oi/EsHf9LpY0yCn2QIlxslDsj5uAPK4XQNyjt8Nv0T3ye\n9fVbPJUfzEe+uTlmWAyzVhnvUPIboWSA+psTi7shtHVVD4l/AmcScKTOZCiR8iPGrKrfAZ7sBbxd\nQEo9y89UheTuvcPzZy9LtAIxkaWwmYKhsWOWTUOXB9VIsNO+zeLhz0hu+LtLx54+59SVmE+fPYpH\nOQQexdWZ4UqOk3Tv2a3GKgfCsWqA0JFw/a1zlK54SiMqHWgJeuAZRqgwkXkaJU8dX9wtne13B6In\nXEkvcy1QbqmiGws8JVZryr2a1IfzlBxqEi5oPWliP57h/wHFzfw2h/+ki1ddr70i5lVQcaHlzM8F\nFSXR8XURkBNYH9yDxSCtyqXkbYh71OutjcCDJnktVini/0VvhESABKvykU6fV0sZNiW70Ax+Eqf4\nyD/ZAdzyFF6YPE70xg1z+qLfrdupDIZrQWXxyNNHX8jXxcwviFmNG/aoW2GF9dIVNydsZjyk5Vlo\nPtwUIPmHUgs1j7d5hC7H4IPWeCAZKc62W9D9K5Kt3BzFx5mAw45nm9DmY3sdphYF2vUEh+u5Y9zb\nKKgQYmYp+0jjkgDbNQsOqmcqcF5hz2FepjwIQ0Ht8+m0lEjD4wJC1OJ/VkC8p/mMotz8jBYbtClg\n8cm5vyvP0GKjIcZtFbP6CtvWOxAJxDe+wwt2bdxok98Eapvd+oyQIxwZxEi+u+oWXIbqlswWEXxz\nqriJY3EAMM5dUOWFu0gIxZjnfPIt4sv9ENmKfu2dshufefQpg2ZwdMmJF3Lx+txwGqUo3ncalbT3\nqU0/KxXycIXP25MLy2dTZcop4UxDsUqkNVW5ikOl1SlkktN6ac7U54n63x2pCbdIh2tuguHrAWGV\n1UWR93wPRnDKWisINo8ZGhgVssqSbJ0WDmocScbKFa7r1AwLxhZ/EqJjpxeMrOscn4omMRmsEzwD\nwrT4xHB05jfCMawCsVt5yzLZyY5Ff/vq0RVvoqyd4MomKDuTzpmEACKsfaScuuKp42dJE+ySsOWn\ncv/0vAeLvFwTIDBxQXOhLKAuOqTSaBmJpeNhnvAkrCyqnXjP2VtS2n/XXT770gxWwHh4dayqxw6t\nBU8o++ah7OmjwxgZK3OAfC0gmk7OI3CWEhd1kK+8R+kN+8/kbA6e+otnnJl8k4YBsWE2hN2pizvY\nVVa0hZUHfUV4c30D1LSjQRIhfFSwUXLO9FojlZfKxdGGZbCIYwQn+XJAL57fLhvR6g1PvVa2SAcd\nzAkiWmYm4wMgJRovs7cFBfE4kLsXVSgMnw2yvCnfvD4dbXs7aMoAlJfbYK1v9MfGiJ+EcJXuQMro\nedYze2XuIpd1WEwdc4U7wFIL+tX7xc0okPm3sBtMOUPxNKabwD3fyod0Yyf+s6H7JH4qWpxWxLep\nMkUXIzqXCOo5jUat2wQiXFt5wfx7qFxb2Z7J1j9g52sdeeus+d2Pds/8CfPuenlpZadQvX8Fd6G3\nia5T01CrYd1676qIRclrrcjoBiIvMTf8HDqPRXSNNJdlodE6u+yJCYcVxVvdSV0dDX6+l3PfOKGu\nwpxPCB9bozQ4xAD3sGbkPhmOPJUeB8un7QYtuzthH0t0GQTgywetmep6lVV84/LRyyb1DsCYbksD\nhfNABdjWf4Ws9S9VvrG+gtPAgqq3By/37Zy0E0XOtiSpfTgOscNejbabLmWN2E7kt0mi4BGKljuX\n+uHrPjK6u9BYCko4Zl8o1eBx+sK7+o6JbhKIntN0oDfLd6ixsd7NO5ZbWfippB8aaJQinhlbjBrh\nTpStOxQQyuoOOKUS2ZFWaC1SGEi3V6HoqHxYVy1Yh8fKBLv6SBhc+eJnvUxbAYKiONrba39XvPqT\n0KhTaJuR+/IJBkOjldEnOP+aRDwJyH2PD/JA+fhp3CWRm8G6Ed2eKYDr1sxffPoe0fGSeqUvItoN\nlbf5d+4VCEpPQYCBry8R+jLxkJCENj87mIVZSEOb97X2o8Cki1rEsxawZ5ja6jqntu0bqldM1y0K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9i4jwSmM3mR5OgbYfEvpqNW3/BuhHOfgDPAFKFixjYWJMt065eAWPNFlDFP04n\nS0doeptIEmaOzmF1LSigXugAMw+1ehfJ4mSPrpdWxrYFQZjEQxxOgq2B53An7BWwmg4koxHOZf0v\nYUWLd7YTIQmXmHTMUTHSlBwrZiZH6sFzvyXWC3m+jS/CyFY7RVq/nPENltECw3p0IBUggS8Q+14P\n0MwblAkjAdRMw/Y8YYZ4f08HiBdpXx3C+2H5UqDHP3GOx8je981kN0ZzB7l8nGjIcEOkPzRuhkKI\nH+kk7YCpbtKT5XVD1U6kbEAYZ/K+kyRbr3NSCgAAO6iL3YjEcWhMxNFWWrAK0nnDMiFHuNodsMRQ\nNGBCBS8OCpiCCtpzvZlfW/B9+6yCrZYbWmjc4i/5HdKR1eVfrhQ6CLB4f9PjVEnkhsLSGaLOj51G\nVQqbfqs8DIX1G2vLRvhLwBOWb5+DSKxIQwCJRjUdsWXbMEU7gU0YMLLz5vuf2/+DpZpzYvOYGEQf\n6+FqfV8g/F95yQhJpc9DLVMHObVGlgTd5qoLgcjFh7F/RO1M0iHC+wp9lvPjDhUwFCbUQTazW51O\nnAznZOt3uNq5jR//FM/y7gJXpK0qPjIm0WgcRqTkDNRGFvV7iMiiR4c546LzgyIisUG5AWq1Zl5I\ncPY3MZMerJEUOx0M0MuGnBNydhpFzijG165Sn3GYDMjM4um/jNMrHsMu4vvQistzQKHkKW1Z4NEB\n8f7vbpARSpos3oWGxYLXH/NOm7ohcUN1oZTIjfXaCdmDlKcyqOuEajKEJS6lo5iD4VGYX442tMDZ\nB3p6YL6Uo/W41ruy734EUsHHrR8J/qnetuSteJl/XYyNsqH+RDmxn6aIz530/diIO5YbvpVhTM9K\noIuY/UxvGhBXGR1VYKXvsMNTNMXPLkBPQl4rFGUWz3/0UfE+Udyud9+GQhm451RFFrNjRnCBrBE9\nKrXhvUlVm4GKiytWQf6bvQwDDYY91Y66vaIDbACx/DqeLAbIqfSJZc5vleP3cTOvw+S9MQvF4sJj\nGcAjvDZyeMtbHNTXbnWVMWguYI4IYfM+Z2e1l3LlmaDUH93ikTNMEb24jkoJjsiak7Fj5150nvIB\njPM8IjJtlGZ2+wiVC9AM1YeM563IpM2DXJeYHAqnw1JPhiN3BglDhenB3Ul3ifDJcY41a54RAZGn\nGB14FcfUUvoTpdcx2MnmnLKmrqeW9lVpJ4LGRdK/ib8j5fK2qDdXSF2KGrOay4aDEMhH2kruIBCC\n3cTqmcNGVwSIcpZKM0t0SPCvlZ8nUY5W4f5Y+U8hhTX1DIWFX3Y+M71i6kxi7/7E2wgqXyNHFJxT\nOtdGYGO+P88RP2Bq3r7SNL+NsEFfIpBiikltfz0j8pdnwifdK1/nK4MLAqT1AIUdz6CNBCkUL9An\n060z7r1FzJDcGvTUQluYlf6LYPadhfMXeSthHdi6ei+Iw9cSMBzHjHh7YaMqzC5QwD8/sPD4Xt2E\nXOz2Xy10kSuFEo9IbvjrhFfDzOea4sHIRFkkI6TXIOUZSr1bx5ZEswHgK6AVyXuhAAG8gmZPrKjM\n1EX+QNHlwNRj5w8rsE5uL/mNgnkem6SX0wzeGn49mTTDVsabGmNe/gFtG6JPOUkAwOQFIRhlZ4p/\n6N9YTvK3ZkemcL5LD/8VohWbCdIN8kDwZYx5QU3SxqDgyE3NrBX2ZlpXcwYRS1Rz1GC9nju3UHwy\n7k2pjp53EFHGyy5QTf7bQSbrBMp5eUeeIW+3opGU/xYwSH1sYAqLVSRDJMOffGoj2vAKTgE7wtSC\n8igG4kRnc0c1mgNfNFMWNr/ZfcR3bMfBuTg+4xjOvvPjpfEOPTf+f0jlyLWBxiEeyXOGiINgi7VR\nxgBNb10D3Ghfs+MQZjy6OQUOUNkGsv/cCIZchllDXUXkUhnkZSDLcnVWcmJSRHA6Xpj4RSaqArwT\nNbDIv3u2vScew88/CTYSXX6pxScZP4F+cgZljso4G95jAv4KZWzUd6scuGQKHIPQ+QhwtfZlWbu4\noaH97Pj8p+DE6AEjNMmcy6JnX3tzvlZdnlfAINIsCH8t0zb8DNzexwLdRkbChC0XC9rJJeUTyxT9\n+HPsMobHxkqekH5nLRPkOtFYF5rNIYzutSMgMqN9h1m/DHcma1dfrDaNtnZofu1bbFTvlHAm4IB/\nm3zBMIqXBQe8cqrXeQO07CwGT4+hzwCRdn7AtaRHpdF2NQf5c0YqNmeIC3bT+cYtNIkPA3axpZI8\n+2iNH/PrN9QVI0uffOYVQWX1zUnOMCaR927nRgqtqnd1jj7lax1rFZ3J3VfF5Q8zoSsLEdQ9mo2h\nQ9Cs7ImIETb1UCMfRHcayhpwXv8VpWvZ0NEg4UegAwhE2WlqtxfcuNKtYUrOEgtF2un3bPR8/Z+a\nIUhqfsX8oYXiT3rnTzunuPpPie2jHJIl+PWvQfDtzEgpxxHPUJMZgRROVWGats2/PbzokzLmbwfJ\nkEgGaWATf7DGeFYBPU8H29EwMFIv51+uhrmS/F+YNLMf1bjg5fQbrYrNz3N85G7So/uHWM5QWFxh\n6ODP9UlA9IgxMvUA4oDoa6QwH0D5FFEdiU8mh6e3cS8SpumXGk2YgksPJ71yhMNm/VnGH9zngHDO\n9XtHYyKflJTx0x4aEaytGqo3pRZVg2GewVbUozY0fq5RWLIN2s8ExL4ParMobfC8hX5xyx7qxjXD\ncaaeYH20LIQk9vrZQ+zZwMW0pNasfRCV2ZkYMAn/5afZ4HXc9t7kZeAKCJlzxIXZAic3matvqsAs\nff0VFE5PEo8DJJtCbs3UCdu5CozhODfd6g5INcraHXDEQmFmUjXknWEXjrouNDIu8DrF5Z0m3p2Z\neRTlhb3XLBXqqjHahdIIm/ykc87TLzhQs3L29CpTNoNuRQ2/Mrif35ftx7wToaXAmbF3OUH7BFZu\nh7DeyGdc9XoYsbpL4qaU2hcJ5eHXeWR2YsOTB97Y3C64ArTJxOJI4+YYhpC1r7aGY+zc339Zx6cm\nIVE55QQN7oSDM7ayJgAwlgwbdkxexevx6NKFxq7f6KpAuOeL4rF1Dzt+lG8SAaS/iLgBYKnRm4/m\nJcdYY9+x0UyS2/S2viCBMjGiuIqgZf0kU/eoS7gva78kSkl1mhzZpu27sMirMpFYmHP09iAcsAFg\nd1hMKbJjRFbsAvXBgcYfrHvA3vhOxl04QKoruUc3RW50yPuUfd1g+nDdEQvNE9I4kmTxlPSzQVyX\n/btPRjw6LXahFRbcqGNa27hti81x3XXzw9TE6IsfdhmCbAc+rr4aU2I90OabXUQC7P/gTIRUYrsV\nvxMeEpqcexXlKGOzbDGGCOmW8xxcZIcHDMqvx7cAzBazELqLdYA4OctBvIaAO3H4G9vIdfbSLnlL\nUqMsM3H7m/zGzcYIU+FFubFw9NT8ihmvKaw32XcGrH/mgd5U72xcMtnOTpNIqAYRjA5SttGrHGBh\n3wqnGH1XxR7AeiJyoiIn1eZ/bqNE5FQCwJOmNVixkT46jdj1oJ6OIdKnnWuKRW6CZtCMtaJL6Lws\nX9JPiUDdoQOVlNPWLnd3xphGvlUaQbechaSCt1LPvWRhmrthohLpieckza57dYOVuJ4/zPLpWX9a\nlYNREc0VG5PmeqWoFUb8uH4dFK+nM/OKITmaydEJKEdkQEOqJcsryqvT68fYSlxqoYsRl2uZk88S\nn3x+jlyNOAiQ9GmokMJS7WG4PJONHneAozFSI6GB48E8S7lv5sPJehzdyH+U03mUJD3h2vjT5Ymd\nQEt5v1Lqtj9Udx1gY0VgtdHXBUs3ukQDeJ5UjlgLfs1fnSQGB8ldRPX4WIxDaH/MYuPtGW/JMgPp\noR0XmucOiQFsdpkNz6Xnkz/fiihtUEZluDJquH8XopKSTLWzJS1CAkJ3D+w/QOXZOqQ+wM54r71Y\nRqzpEFfjRil6DN/iUhiNboSnZTwddLU/O7bd80C8X/XCJexHxuNf3/gtmoW2AkVIdESKx0kNjdds\nJLKdBQL8SsDtk0kJGe3L04o7sbKYn40XKvl6BOw7k+O80zKA1p34hE2K6zYJfjDEHltw6WazR1yY\njd4+lbz/2BBKqk6XdhI7R1IL+00z8LcQAY1E2EH8Jnd8NacmjZEkpGyrV/+5DWurbDZK1xXlb2s3\nzODIEo/9RlaoZksR6fpMB84N1faLyBCjd4zCERDUvOjm8/zzswZHLZg0cRB/d0o+17diijU265LH\nT33lHfYo819/c9Nx3trg0PP0dsCmSMfRoiIdpBpf+3xrSol5c5h7xKwEmYcoqmWgS0I43NcxIDHd\nG3eUbolTPxNFhl/3di2x7BOibPa731AYU3blSsG5tVEm6A1stMhTCPhxSTfp1Bih6iaUoOevz9NO\nuBcJcU51R0gyo2eVKBwLReA4Do+nNuQXbki06UYn30xp+mtvaPDrpkYvsF0Id2uNdJ479Igj7yR3\namramfyXHQVBnxJiWOX9S9EZQCOWtmDS3AEEKJCt0P0oQaSGiQI6VLtj237M6KO1MaJZ2w4pcnij\nlctO9wfxenMMTPV7+0qcRPGYXaavZ+kHLG4141TY7kxHox8k6i8jJe1JYIuH4H/Pj1ajPb0X3N8I\nOkVc3n0Ds79A3NocyJ0/Kyfbdwb9Ma67LRH/iFzH4Tbq8I7xQEAGsc9X2u/iUWYy9ismggF85Lqn\n+mXpRaEu/wtgXBR9gtet6PvBO7FgLChPLONWCLB9B+4svmZYlWx/k8mxr4vACTWd6/k1H7PB1PTV\nIbkvp6rUQjIjLDo9I4ZuQFmeN14x32O9v6EOzO5+orPeBC1cNoNI9OHEv9jaVZTvjbtdxXhVxxrm\ne9mP2JGq5wRmL0lv3od8M2fxmaOW5eL1r2sOgZ8bPWipohhsc9qszrorz/j3+Ewx/U2or7MoWFZY\nO0IEnR588twSQHtnDJ2l1xLqs1phfrzOhycC6CexWxhEt3S+v2BhEn1LeS6eBeXKvGQv023DLXnI\ndY28NI4aWFvD5rxlEiRLmNMPyev63jEFdqQC3gEsUMl+N3O7zmGXqYOVuBeIuvdeUzkoIIDtkXDI\nFrDdQPl6L/Xsjau6EthbanuSioIHRMERiYRHb4x4mfl3cJ9AsBSSy4km2CFgcwO9i7FGA6HRHKL0\nMJrgOTT6cFmEVrWvmdGBxYK/gXuzkwljLxhvX6LgEkvbyEgxtHb6Eqi8baAFJ4zbkd6FTeY/ULE8\nyB4XGEMtQY8dn4vL8gIor2zuXYfjpY5Que9wtBagr1F3pKsO040QoWSSt8OF9M8fhkBBw0XqQDt1\nQqu8f8QOdEqKWL2tad0YhkY/F+Kjit7Gfz+3k9nXy08ODTRLp0WSaE6NtBwJdTdUMgNd20YYe2bW\nKuMb2RiYfgssVoKa08Oo6v2eUXLsOXwGV4kg3UeSWUeBssCP6MuykUuEHQd3lE/qq8TOBLWMnBxL\n0wP4oWjgfQ17XHs7XMjZgsWoR01ZCseThHdQPYklzXLzYm7pVeBXoWnOQb5vHG9ZKcCmd1fGDUrb\nEvr1L2VxyWh/u7GbxViD2/OXD3iLtBpUmZVr+vEAHx4Hwm4B55T0IdTEWXeQl+xcQTJ1x8NH2DVU\nNsdaQSU8rxIZ7W1L/koQJQ/DcvCffRJr5ETIz+P7K/mg5reVYcUX1ahBRSTaatENLY+psmxk7D2u\noJdec5di7HWyk08gG5cJYSczlP2WcnzUUwDmyqhmNpT6qjBiAFPmbnwgjCgjHK2RVWBmdfsVFfER\nQSo+IK4XTEdYyGB2yMQIFCr5RTrbKMOyZT18QKwQ7x6uQhJce+rQCvKNt5nHZeuAekVj0y1IKbIE\nsnWmVSpplt+/ca4KJ4JpMn053iH66WpS7yF1rCsB3w/QzNc3T30xr/OWq1H2ZenC251y4cRsIHka\nfIqix1UHe3vtwEJ5c8GRFnHMl+94aoleCrX8b+LTgAIgD7s4Zr9lVZz+WLS1KCoNjp7JYkfjk6yt\n3JAoCk3jAh9mo601K4owpkjsU8AUVH5gHTN8BK0aMtfypWKPoMdizzc9MQUlIHm/k/TdjU5xYtEo\nR5csyUCPqf5EZyhMhWFDn3hUVz/zvHI/WSEspVT+Il/B2P/bp+7O/K0htfH+nRc9y7qhEwsWXb0M\nzLE0AdY0oFoPvjEAAuAlglZi/JLHFtLrVJnc6nN3EHmhmYOLcGvqLogruwVWazX952sQ7+n5IeTQ\nV8ylq7jVm7QmalVyrN4zGULxCLQe58x/V+uD6Fdk8dWhU0iZndCtRh7M3TkrlnxOT6rgZxsNCOlg\nknr/tmKsouai++MMl0/V7G6XD/NfXAYr/bsZhNC87YEurpiE09J0MsruweccJM6kr+SSrvH3d7Un\n+Biob09J5vxwV4kBLCY1UyQa0RI72RQPTkNvMl9ZCDRZTjMnKNJ8h+gi5T43W3dfljcMqUrkM/Fq\nieirE5YCNwnbf0Q7zqSj0pBBI2fqYUKvCgidaIFTYBjCyQHJTDVfwlJkive9XOyEZ7fmwE471ayj\nF90Fi4CsGh+fJGgi3y1F3yqMMwYey6uNQYHjbFV2taAdPCczWbIu1R4Oo1AVQsMAWnnGvp/OHLTM\nVrWUJOjHlu1y/BZIBohdwSyDIma6n35CooIGq7lIaxfRz6kxbYvjg4LHftSfp+XiV0ugp51nhtTQ\nxIImMynZ+Xu4Lo2U9aN5RbxjbjgtfYVkcYE0NhKRmEtC72pnLOtIWPHbXx1+Gedf7TPy1pkiFcEs\nvlNSsjXN4gHKFWwXOVQzwcus/gIOB2Gqui1xVOgoIr5H8gAqmwuGOyECiz7pnNjGuYGO3x7D7moY\ne39rBdzxncw4dRxeBYKFQ2nu2bu1vNIUg6XMDGvHwXpbmC/YWMtMc5n+KGxx/EnU03UP7TYOyQdW\n1LmLzWbIyCWrQv7dIpVOJH22orzT0J4ine1BxowVwV+vJNllM8GckUATjl3nVK6BMTFNaqHP4V8N\nPpmW9YTjxuG9gvocWE7Pd/X6pyyoV+kckTqKJl41MhIkQ1nhc7T7JEAD7Gnk0GMbI5MidqzEwpDl\nBFJzZdDQHaQMx5o4hrvuZMlIZb3hi+ArQKx2XSJZOBb7M1oF67k+Yn4r0CBQBCjBvKrNGK4Sz+iT\nUu6SwXhGt22N2yKAkBX15lEtrw1RdwloNU9bCiS7tm5jd2r89Ek5Zx5jM1MAH8DdbMhFZeXK4fiA\nk/OHpux2R9b41YEQXZmB8cCbq+M7MvCBsEPq5f5ybLU817LxzKuSAcJauenvwW7Z3c1zQblU6drj\nKtvkg7ExqfLtOhK+FMVuZZRzwBk/UEG9mFcrHEtpSVZwUnrhkw4lvbKKy+H1TI7sVefU2q9mPt8l\nboVvkL0D+j4wS6bsQeTBPiQyTzSDn1heLO50F/U/5Ha5piGgFE+56Vf6ot0PUCHD/3zq7NrBjeov\ntV3DbR/63Q+LQodf1AL8TQHDp/dtJY6oncgdyqNyg9IQ0BDzY5jhKGRyPZy0p+sHWeqmlfwoDgsz\neH5MAj0PUWyf4jxD3x7lcMD//s5zZsjYWwvUgWSeS/iDfc5Img0AZEDEdz66mLZi/Mi5uNi5NXuu\nkJSo/C+YBcPGUjZtqzj/TFC23Ij/1H9pZBDOGmJlD/ZXN0G8fx4S/fQ+l0A1pMCX6LEFSIRZQQ48\nzqL7Lk//tKqlBi2E+kY/CcH7yl8axFRLOZuG4UJU2R+G+KKqag0ZrGcyc8NkwBztfmn8t9PkD5ZK\nMYx+oN9ZS+LiHy32D4OfhmVUaWpY1Gu3Ex5NvwuCqDLdMWyFrvghbzXahJk2+fyej0OZVHLmCULg\nTVaOS9Ciq59ovdkoFmJGpNEdZCs0cLoDzJYvSTxu6Sk1oQaW6xjaK89VgKvTLxXPXpxrihV1fJqq\neSHm4sogN7jG+GzLKjYZ58NMihkQE1XOER/eaGw8l62tWkzJKxPsolqmk9HL0uKq/9+s1J22S9co\n9057FWtCu0jTGPHYc+0pGfAGSmRQRxv8WRMUraapvMO9BVOaYxpt8NBGHt2I3lwuPLLiCpS0DOcQ\n5MYnEiEw8cF0Wtf6wMMFKsumCrzfIlOYycD0IhyUpM/ZxZGE+hmWIr3CDifOMcYiGqCPcCOxpOb9\n3VJFYCJolSjKCmxUPhc4WJF1NykBq1vvDDfsRMJDmuxO2RWWhNJn27mR0693mFj7tVn2ZeZ337B0\nYIwEYO/HzTIAb+Z7uEl41pTUr2ix6/IP8pkfBow1TiTyz9xd7xpQPzoVV79qWeTNYO+RmNtQV5F0\nQHZ2+0qH452M1CtTKYi9UUSgmI3c73Vku+Cba4mQDhKWQhkPJzMu7AY93rr1TEAKyjxR4cJMMwnP\n8pZAggpg6beBT0ZGSxCt/VyidObgHGpM/szcd4IpIiDZroJ8uemsL83Amz4fnsSUm2bn2nEpxtrv\nXLpmQUPTGn9eARM1a3e0wvpBpMbbmoyyy3LtVUPcUrEf7gq5X6QekHvqwbPCED2uLSv/rqv0CnrJ\n9UjZwqwcqeGThpZMb89kntjqXxMWxjNqDVfeQVyNVNJWfKppx2uNvvQ8eNRAZRAcaIJ3NomD9uZp\nauJey/X0CmY1qjbXvZ6BHdMcsPBpEabVuP90GaxyNOHNX/rFTYulYWQOoxmQBoCAnDMde3MC0EGt\nX1DUbgRr99WQFPXUSTFhNZhrvFvIMc5Y8BjCrhBhLsowUgbHoeKZR7vOWyFqIF1RvPYyaXj5V7cs\noZKev2pOyuVza826LODpTT+/yhZUxHVNGF/Yv0Iil2VEK6uZYih2GOpM21rMaWHIBMx3+2FGUEoR\nz9p7JoVDOXla1Za3yp/hj0t+f7Ao0fcKox9yrzrVLn4MhMvbl03r0Fl6zBHaI2oeQNzbUnL1+ULf\nNOU5kk8kqwcnEsVsQuLIfbc6MI/YKkqthDMBBwHzQU6xK3d9IfT13BTzEQbxGe5rM1EontzgAYy0\nxOXMBI/W3OsMvUhRt9kDn/fM2LoEGbT3EsBrMC66JuxMi/sU+LSJdEoZmFELzQQ7m4i9sBfw3aPT\nAQKQhn3Xy+IuyjZoIiVSb+eNWECwe8w7/cqMI8FoZ1sglQ9Y2Gfht4TM4C5U63WLMqfuoQ455WDg\nY/QtgijPzhnblGqPubTVn4eMBU2iGTcI6k7lbhFkwwyR20r0tQ4M4gRp6xUuy/DI+9GNWVA9Qdmc\nKLONVBY3L4M9/5kRbfxDLyJdjy5ui3ho70x0/foKgcP/60WDy0LsdK4Jmssc80z4E58g/oZCKkGU\n7bXsFVPQvB2HAkqljjI1wONuk754RsUeSQSGihgojkM1QzMdVer0ViIuBxCO12KmdGGKMa8rxFBx\njbyJFnyiP9eTcuAU5TOmKU/e9xYvEkqXXF0UBj28lGp/Svg4dtgGwXspJf9GaAsm0ifloHeSdedX\nUg9ub8aU/ulGpIKQOtOwaKbxnZkOGeQfEWXHw4pdEeSd/m6RwIsSxCFaehWSGsDCIGABAre6c86p\npjumYaQHHirxadAu+TndTErJt2GBRQva7SQ7DiJtec9QifynneCMSswRPBPhMyqA1OipQH2Lrw61\nwm5GUXKK+pnJDKwBceA+r3IGBjTK0nuK4kNBKXom7RgwImr7Pm1kn+SsOWQ3jE51UKF39tfwwBHA\n7gAGW8kAD28Ew0A3JZUUAXZ93Vzej+vc4dn+FdLjOWfn6b977fiylrHGMAQWHGtLX4gP6ahV8OJ4\n1SUyGVk+DOIjEa7k0RLH2xO7w8ZPzg/u7PL5hvr27QibOn9FR4eagUVMRDThIl9HkU0H6FJ+U1KA\nn/WLGeRbDSrpfQk24xXSAV1jCtpACSeD//Ln7BghiwB6CNE0r8fttUm9Nx4AeK1m90lMfKXixjpn\nmtrhz2//rr04K96a6ggJTdfD0ZJi/2ItEUhBJiXm8Wkb/HH/NcAJuWWFUnS2NyZSmTM8RdJEn0rF\n73HSIGgtb+GOLbBlN/UQFFp8KNhHIGoSGYDFMqdZQ+fkZqkG+MITwDRpzgNi0Z9b3VgJ6Z5MedHP\nOAywNMMDeI9umLKIjnEU5lepjo0MhMoebDh27AE5HiraLzmGxLhTlJR7qG4BKhm0CutKFtoZoqZT\nVtv60CDh3Mv1vyzXUL7CpovSzrWkruxDilx3QgmQXWDIn1FnrWd19vtDIDdM0od1J4LaqEvpsKRq\neVM1p1lh7oWpZoEtYQJo488oRqtljeCGeCtfy5LdnZbdM8tY+Y2WiZhAmLItYbOznrEVpeWmyJ8M\ns5hTU9/bsm9b1Ofbos05QAilZ7b/dMH/a0Se+B6eC1ZYeuQm0uBhg8kGlrjy4lDA/kKMTPrLtCjI\nsWkmyJubarilJXBQQsO+U7TW/rs1jIpgGeUTbWJIt3Fj8MiLJzsK6PjuVRKuilSJor692nPYyAyp\nDE6gx/Gm84WRciQa/gvI0lOi2Q3h17wW3pWicWHG+Jnpu8siG8lnE6B7PNwy+WnQulaqbPwzPhRq\nyydJDu45qaH4kZ4cXE/BwgsHfZ06s7RJogVCjyGV0/DT7wLpJfiAZr+tV6qFnFWmJIWG5PlYwVHT\nP9zPiemHWZjB76BsdS7GSCiMP5ONSaVvz8wopFfjTkk2Xzz0irkG8uwh7NKBlNC0qnr58eGGt2YB\nvn6LZIFdOqopPO5crXSDACguMfcHCs+3PGe5sat2ONBx1PpUb4Eo/FBEZTXi9PKAdxsAtxfM5kmZ\nNAhEiPrMnFtlrB1AsW02PVTrFx4RPucBxyq5W3pFP5BeRbnjhU4V1Nfj7sNqOogUvUw95PGXmBDZ\nFGdnQN3YTpJMLdxzjl8dxf/MCKouNjVHAwdg2l3QzV1rX6TQfdr4YmSCnZaM7XCExP82V4QllfNP\nJNGLehTXlCdano5ePQ94mpjo+NHUrpo4i+cWJ0fHAhxi+SFShg19cFXFas7UvL3vJDAvKvkf9zGF\nY943EvagpAue8mGj/frSRG1WUMfLQLqVtthkHV1nhhN/U8Yub04/KhGOI7qI3SeFjgKae5WR6UHF\niYUZ7ieXmvCsBJXPH7pqviYUS8336bz0iLxyoQj95Jhij2vqPjYsRGpj55Bf/uz3aB0QqWl6Fzn9\nLHKwbg/LXFdlmNXE+JTxdB0Y9DkuPzUpfouTDw6Inf9mES+F7/WOKxp0RXRPSjTHleP1jED/6lV7\nrtglS/FpZNrMIIiJVNBku+MAPoS1B38oJ8Bufgmm3YgAuMZHDQ7svhAIPX1d3FqtOs400Eklg3Q+\nGFhIyzp55W+3McQ2CyqJnIcxbW9s2fcwiIjdSWORCqp8BLwgrzyANs1KIhVuSNQSwcOBCNWuotB6\nIoW5AqjhfVXDuHh/NQ7F7Zpt3/8naV42FHZzW0QM/E2mPEEnDErPHritTg5n+0YEU0ksWLK55paA\nLEBlDQzJUGRhK05sM921PKR7cF0lo6YJKS0WueyY4kpEI6k76+1qc/OzAIASLsoFxIIoe47cK6/b\nYl5DbgCKw8pGG70ux/U4a3Uev6+1RTDQ4cCMjnvNcBspuQU4ayET8GzlmOAUT6FASKsyxyKjcowv\nFUX0kVBOjEIeVOQ29HXKvXwdC2JXPeG0esDR8yMeiLScmyumWjZ61acRT7wK9uLg4Z2Mv0OcwN2E\nEoyN43GE1Osm8tCGdgO47SOrGdQHBO4QkFH/uF3XVlGxyQg3Eg4H8LnuOe3sbCfQavtV9eAjA7du\nQINAfCBMVuxd/oooDl0WIpt9uBlHOf7gw2Zm3cA8l56P0TIOorfGtkzIfuHj9sSAI6RA3ryC5D8q\nHjuJ0I/lTXAH1z2P1JimZNFZ0DCIjz1ZNqQYme2XELZr8iW2s0wDznsZeYuyFvcUpw52oU3VmpFq\nUbT9un5kh50EaruBx/W0sDVaw2PFFkMEiq/E8EPCncvvmEFwMvXBA28HGlPsskJOy5/f0SVEdCJq\n2EDonV+F8ZQ7QP1xix9xwDfOsTMt9Q/5P72nLaRBhVWWwclbot2eQDTpVfKPxz3NCGAZ+VTWasol\n9qEB43W7zUj+VZi6QwAK97urJtyxLL3YlH3How9wKBhmVrZlk/jN033gAlzL+H2/s+d5X8/cWuuc\nNV8/wMUA3mO3XTRL7B0Yw9qGLuhi4UmGv/a1Oxy3dE5dc2C4XSmHAvwjqxEJD9E4WwiqEaW+mui1\nBgUPc8N1pk3BYOpdwUNmsg74dHPbKVN2TJlv7rJNdCMNlEGi7YdpC2NRAM2vkE+YaLFXcA47AvPb\nFzltxjZr7TgrMjN9fS/9dg5/nAkPh5IR4Y2tUmC0ovh8J67UqS/qeByRQ8Ao8Udd0LRDcP1MZb54\nc27I72PHCsiz/RlJ4FMXHh0/4VGvXWF63GTo38tWxRo/rG+tnxSKHf4fzQI4l60RqThWWIocvMHC\nGoBGDsLT1bKcwuBcFdbT5jZtriAETutHcyih+oJ4/6x+9adyt96ZPA5iNxFyiqipuq1xABHL4iH+\nAg0PHIek/UrUtP92F70fyk3G+xaLcWrVUqbMLJp+66h9EtjQZ2Uo5ZnWVnLt7Dmf9uBuEpzW09S9\nX+A1c7rU0ZTjiEJOXPug5sTxKn/PnNnzIcbWsZG8ZY5jcrBVl93KnH4Elo+pbizTqBfMSJw6OCl7\nAZs4aBFTwmOdpC0PtEhlm4yWCOClaBlCIETuvuwl2s/iPCm+07nRkacPOEHPkehsNFuNujxR00dw\n/kMNh1w/JntuvVetTvIFAgy1BuPL8ojFR/kaOONNBfP41dIEmTCNVBkl9/Pukvhs/T77L0SxtcaL\nt2foKu77GJYdCjqDR3dxNROZKJagAC2rDzqgjv5XYy9Re9XG56yg475hGJiCSvtVLxEL2Lw6xRNL\nc/57V3a8jNiLLt1UuycCJCgIeccaz9RnL9lxxCX62Mdr17cKrgfVwYmNqZAq4lGTTCSlRSzuAvZz\nU0S7lhCh32Cww5T+zNAtDUV4jH5Lj+zuThn164ZHE75gdiTISnjBJg63+UsJ2Heut1McI7462yWW\nxGIqPR361DfERxqxDPdSgnzov3ug4URzWMWxcEHxW+RWfUMCGlRH3ryZu4cCBT3tbwEeTiYiQO3f\n9xqKunPe0aoAeG2XTiqzTB57KgaEmKxLAaHELmhBtyYDr0ProVrDnKTfWdpnigPurS0PqGjn6QTd\nUFMoXPiFhkXnI1/jSaFZ3qQeg5uCpR3Drr9eZVzvm6zvt9J3aJsRsE/9Ipv7pCj1chmNwYVasFfn\nyYwZXsMxq3NFXpTTT8ufKrOqFtIPsa0fShr3j5dt0bJz76uyMBLFMsSE9YmM11GxdnnJbk5wvcnz\nsFugk067dHQG9mrGMXjaPQ/kDyclCShrz+RAyqj3FIjqHW8OQOcokqJStnIqbEzuPf6cQCPpag9t\nrECWDI6JPgE+cW1McMx49yTLzUPdNSJSbrsev84V4RbDKGXD+oKMEv2NLZksOTPw+swqMIrFtAxW\n6f1QWYJl3+/VLlk3/Bi1S8ZSzrzSly80giRq8/9/XlEfrVmFY7pZIg/EYBFFFOP6QyewfCWOVym2\nJUHzbXDEwhhubUlAeaxDyKo916t8nxUQRuPY00y9pcsJa/l/DJ+QO/cjOD3aOchfj8cAiAehdM5Z\nah4RyOHt63ii7V4E03dxcKA1z5Bi33dB4y3yFiidBEkCwpp6OjaDITpnqIjahia47X0Uoe5oHjLd\nL9SWeTRUaamk/6Kcs8D7rXHqKhWXJ7D/A9srqlgnpkj8m7YWd/uhBD5CSTPXsVUPfn1T+WRZbL0b\nT1oBO9Qs6gGgaIx97fuzJ1HXAKFx6i+9TjGxw3qn4zRAuUhUK/TKEpVVVCQW20JpnQtcBrbx72XR\n9g8m2xPunrdlBu1f1B0Rp+PJR1smibINbO4anY1EKfR1RzwgKahfxrCWIc+LT/6UJxiiwYLnq8jO\ntYAFwLY+K4UxPhdOHuyR1ewp/d6dmcBw0PsRPT9bVA36+SQKloRy3UlZ+YvmdBTuqzVC+xDxqX25\nvueVwsuLRsa2vAUGjfYF7d9CK+79iNBEZ9Bn/Jtpxvx4f2uLqDDxbTY//zLzvBaPSHSbbHUw7HXD\nruKBnhyf2cXA8OivEd7TEqo4AXoolm3U6EkYo/NUxXEo+6h+I7OzElRa/dceQj8jPrlRFW0rwIAz\n7mOL5N8w/58Cq3+EKHmI7fngCjeHXEMxSzC1al2ACZddNARb2feIyIUXHVzh8IAZploMD4BgU0Eh\naq1SpMRq+NVKSTVX4lzx6Oc3z+Jufqs0TYi8dPz87vxShA8XEQlXxVFkBvxl1i1ih1T7n9YoTa0V\n5N84OwcmMLVK295IHB2PWCBkYcPj78jHJFxrxOhnIL3rElMCZf84PDCUEFG6YGHxd782crFfJ39J\nHsX8mhO+oaWesylLOiEjAzLYbBG0OkMlDNSs8xQwW0s7MY3d5HCtPw+vyNKppLeTfbxqxMCVyq0d\nN2FAp24SPXzrN+qZ/o1ep1/mpb4OBFCpXVwvnMXnypB8IV2rgZor6huW5feAxn3XdtltIlRXC56l\nkMLa3EWGph9xx0la4/5i7IRaOGpkmYmoyfaMgPLx6wjdz7B9/6txTuhp2hofCoVq0EuDPvDKFIcv\n4c9tBwxmVd7xEeKOBuS3Q43ogfx4YAhR7toyCbmrnQpig0KRG984SkZ9DxjGzqdqz/rS2DcfixP8\neRTgSICVe5gH3bHqslZXh0TbdH+NhLB5Y2JZ4I2x+hd22s4CaCY9ppTaa7t0twEtREhhnbsw/5qI\ne0qK4JxRrOqzbn3lAiCEdtWNLl4Fu3eLey25qjhUmOtplXFQjF+9Mw//ADeViMN+QYC9ktVgQInw\nrvwi7WVHtWQWPa0NcnJ0kExAZKXg8sd8ebPR0RceMB1+VCyxTyiVwreiTjw+lgz6byuChK6UnoYu\nnge1SiAO7MYo+iUgsKcaYl43cJXiwy+FlF3p/RO49KGM2lHCi/8E2/b7L0v5TO7FAEvwnjNQ/BfP\nGZRiFnboeDq9eIWGUnjyfpF2vqHXHgFYPbSEHr61QjvUnIVZaOGbm7pUuUnfkUbFmRgU09ptJOhQ\nEfao+09byX90E3rTtfRw4tpVpWuuSafhpKteQWsPnyLJjUASot9UAYOtxN6GK8Nj83AfwP+tLoNv\nkoAkNMbsJKd4egJ27/W+d9LLBBI4wpg3eiRxGlFeuX6KEYHFAuqa+sQ/DEZ3OacoxW0NTW8LLYah\ngPk2z9VMr53NNcgRDQpARNoEdN7ozzN83dFso1kWfKRLpRe4YA+N5/s7WlNPRgTRoUUnRSx+o5Bs\nM4s6/fVh5NdeZQBYrq2Ym2mxZNaIiuChPoCWBPi4V2NQFAVgIj6t9ivPnvSJrvxg+oQlfGdtr2Eg\n/dHKn3fMtU3jTScnlWYjEgyDMTQsw0ql/DTj4l8+N3dYDVzuM0K//pG1MniZbHxoewh7qPJSxkqE\nVhm8ZgLnqUxDcdLsW67oM5aiqKLkjALYlOmUHIG6sPsKyxxbwzTnclLQ3nHX5YcdEAL/KjoauTmA\nV4CXDH4Y5puuyjAB8bsUzzItea8uJ4haAyYZLIegMJu+Ej7LuXypubwQ+ZQ8OnUB+yKn78pHBv6L\nSJiWdhKnywBoTVEdkuvVp/ILU330H21owBY8EAUzmdqgZnJFrMxKr8+kj3GBukmZUyix2VM4DMrG\nPkPYSdacOOsNZRIInIYT4WKnvHddVz4LKeuYTJQGMDELzS8+i0yTi7BuO6TttFPh/EhV98IAxs84\nlzVl867GZgM71cTtn5K5fKoRxYx3YGgBTk4t3A26d/3xIsUfcXPZ2kEMaEn/WjPX0xmmAG7Gv4eM\nV1DoPYFgRRTdn+U011x9ufZrKOOOc+WA/LlQSPJbVjOHNmct8D6+6scCNnhL/i5wTLKAbkxA2gOt\n/KdssuRCkHdJiB/bZXQucy3GDTR6TuuYAxCq1K97K3lEV+MVSSI/7KsDU53fZwd3xn+2liNSnihd\nGY5wr5kbB5Cr4Z+5s/Ezv+6xqcdQXbehHU+qidwxEeZL4kl3wmQi6t3Vcs064LalqtSkDsbeTJVm\n0yY7+GWeb9toG11zibx9WLM7JkSbjmWlKF+BPerQUYUmfFF13v66YG4tSt6U4LtfeZ1smTPOsSLK\nhU3VM9hyLHnLq7C+dB9M0ekSWo1tOa+Ya3LIpSKMy7/PoJmf+axyjL8HLTRMDYN5chvtMLY9wU04\nKcCr3bObfLJOEIDh7/V2aF5bmcXc+DgNqyMcQwM5XNBQgxCmHGLXAxPbZCjUw5aeEuTp+wW6q1Hq\nd1HigSuKMdDTa6fBINnIiWadtbwZww9zx3Ju2kZ6MBlGOI3FnCp+bUJX8mB3SQc6r6eSvNSt5BX+\nAPCsdEODF9K66M/f9987F5hKLiu3ndfg64kKLzK5sgrVT2U3yuEyOEvKA4etHOwoMSRJj2Yt7vNv\nG63JnCVWlSzEmLOd7fiWACtIGMBIwR7rN3lw0iCTDRtDfiKdXuf7aKQPFXRQvyN2Lalpyy/6jzyG\nCwA3vi8zbUnbryWm3vxHb5Doz+oUOkOUAqXi5cEt2gQLW7VroyC5j/OqJzDJQGcCf0bTuOZOfrzv\nDFoBnJwrN+zvyd3xZDoLMRbExhZ654RhnMqXUZgcrcjgKaxv+btLFGSNuoCFiyl8xykaMLc4FuKJ\nS+T16OV8e8SOHRLanE+HS7gfdZHklddd7Pr/ia8y8+GaLYtTyitQLNIz50MI74yyyyYRhxdgRY3b\nZ5pQV/7PsU2k2ideWz81yItBGRDTZ3bXVTDy3YzHrvUWRc3ysOjL/FrvVtcDXR395kWQ6erIMz1/\nAmLX0dD7/9FHwUwogDqsqwqcWBbDlBZb7pYSM24YmWrNodSlTvHmIjAqvnZJKxtqG19fTYBgKBJq\nXwSBrdEa0H4/gEz5E4v6ldUs4iT/MPIAHGY9KgEDOetE+0SUBG83QF2m76Z5Bhvc7aa8kHXX9zYQ\nafCWGumgYmgZTdAvFpyf+wDRBeETA7HzJfcshlmbVI7E7H0uX704njt3uk2zpVluuRDwPFPuipJz\nxMCJ3+6hVNWZYMyPaW5z+lVCofdm1NLe9y0kgBUcwL5QZlJz+45u9YjSIdYFjFwUcgy2GyOup+cS\nl6hwj84zdNVm9I1L//snXzSLMWVIusZYAUc2c2dH03zXPnI2cZQQiqv8KRgLNsXsTOve+Aztt5Ch\nXaktEwPUtnNrErdB2ss1WgqHYESR2l5OVeje47FNe7BMMGmHbQ0iKxeubYV2j+eVkNvLY+MEV4UC\nYytqRAIic5vQTxw6/saIDnpkcL36Xr3qQAHkYaQasdqJawpakeMSGzsSt3nVqB+Z93IBtYDo5MHg\nNOtte4IQARIP9ogidP2LDwqptlqdvG2afwApcPovoEZa/xCjshehI2JGVghoYU9pRLdEsSELjdpJ\nIAS9ULYRLV0R3ebh06gIJhzpKAzK72wjRdMBvY2x1dvCMmnuolkc3vwZ7WCioI5h66812DxlQa9k\nJ7t0OCsRCu2NKgQyp7iCB9/bZzjHZiUbHBXoqpPZsw0kJstnKdDCTJdX7GB4IhxhmhkoRddhfZ4Z\nbOi4RXSND1OyFmb4PX9YAgQlT3fiNlbgdfoUepeNWQOkzlS4KUrQi1xMke9aiG+8DgpuIzzX1RO0\n2s2LKfBBEy+189dL9Amn2AlFemzJFiD8IVWoHFEvIjEO2RfpjqHGcdlyor3ddN6UzrSEkoqhUGmV\nrujJnMACUbtZjEDnX3DF0QftEVeh4igAlsTposWJNTh2Qlwok0360P6T6Gi2SATE4S5/N8mWO18U\nyMVuyui2y6Imb0pxtSWJli1DjF3m73okQ+qTwgSITM/Sfud2IslI/Xh/bHK2ZORgQ81J3rNX39ev\nPML48BXHubxMU9wIb2N0G5KboS/DbB3OItzaM102tb2HyLdQEYntezHJvXBHy78xSptD47qwQQVr\n0wBowdpkm2FMhMXvkC4EbEKpuKsnM4SE1LnQMeDdmPRF/3Okafgm1R1NoK5afc0i99RUB/7UYjYz\nd26lGnZVYj2zT2QulbXtIBQqOpprbWMODjOm3zDnUeIn6OoYyAjAWpPYMwrVlOGc89bmp4M9C7ME\nYFnh/Z6kGq+3y/qS8drWcSflttpHXItLKlsuK5XK5MXptzWVgAmJ2YGOV+S3p2LkIDSI0Ir+OvdW\nXHlcF6W/BLCmSwRUM1z1ofPjkMMf2+pLk0FAdy5RaF70HqdEgZyEMevMdmKWl52VyCvA7MdD5g01\nH9FeTGd2yrDa8nL2mA1sJVmMuuILqtlPxgyEpgKfWHbXAWNC5GALdzRgSDapHRKzyR7NkW4tH4bJ\nfqDYYRW7Dfe2BL7ZVwvGxaL+yzNTP/J/d51moC4zxc8Ejyqz/0hJLrCUxc9xuHbzfLHKgE8Gwlos\ndDMJvOHiT22sewPTaPM0q7qDnHjymF/UAJst9lQmspwGG9HdNXNDqyVHA+L2SfkUtXct23ghejHL\n0iGi6ejuC0yvc37KlltPogxSCLxIE+rgHBAkKBm60QLLzl0M1tiTVpIHVBUbNFuXbw32a+TSN4D7\n8+xokpHD37o7mgv5VaNIkAKfqAaR2yKAIFxVbN0cBm5nYZViC8GB0Ook+T3o+C+NsTxKgdT6rYez\nj6n/b7MWvorVJKs+JbhUbv9IxJsWCV1Q78xshjZPJxXPLYTQRAy/HyAMI90u/sFgSjoZpgYYa/FA\nZzwmB+kOjFLLqRQCf2DRzcmN/O0rGYLqDwA2dx6AYLpL9mPsJqBMc5DKNsFDiUgQ7H20M6l6whOj\n9VUCT6BD9LgANuMJ/m2X4rHcxSBdhbX0wbUM2CYkf2sx38xYShvWNsJoWXVRO7FuesIHeGuCvzxy\nUp2wr3g14sdeUjMM8iSeO01A4N0vanXmzDETtcQiKdJPRoIvgwK+SwMfUFL1uq71fS7ES0ehR+Nw\nQZVSJgf+k0dLfMgf8CHOvCDRHOwz063+xoYzqUA1iaKECjPPsYfxVu/MQUnQKSLhCHCdS4syVYpZ\nXepZ3V7MYHNOzVq5S8HjCXuHf17oQ1D2dN8XUxjZZe8bc3jhIAJ3avOYSd7vGeQ08E+BtQ7qQ3eK\nXYCW0PwHm7JcbKjlNW4TRjt5zEWdYR0/QTpVqqiA/CpUUkmKtrnbnTopLbp3UKweJS1RjGPsANLx\nbqiS7yNB60BYoJPcnQAwgAo62LuwOsM1XuP35Bj9toprVzOnpkoC/7PyhMCrfv+Y6WZ2sZuHhI0u\ndY6oAHRSh6Bz23UvB1FHoC3MF/bYCJIjPTz4Z5W1NH6gef9BcB56/P4/Lh7jVIxk7rfTKINATPXj\n2Tfa61nUfcEVIECxojLHMt5frtsQsTChaC16PD1LtZQVjyOLoDeik7ZWhEl5Vnvd8TZk5Tma00av\nu1fT8FenDHwPOveBWxem466q+61Hc21AOs0PU4MqXGxsdZQQOq3DegRfAcipf8qfz+nw4PZ4w0Y2\nagAZlLRAsfHJbRgtdhf75yx1GZNKrsG/y5OCjfz89pKBscqenRIeDB9MszH8KmRnUL6+ffAhuOXG\ntD5K2JzXmCuA0L4CKnQa+jwNt/W5qCDhk2FlJkmVe7dffftLJnVwHKMnJWf+MB7n2Bi/ShBtfZYy\nGiOF1MQrj+vlmRdv7PhaKAho6bCaxmsEtLspmEBPVXqaKpoM79CCmrcQFkoACCQucFaoZbjAgmwb\nzfXLzGbscnGobZKflMBZyrYhex+ma2/TXGczEPHZx03ApQE8UobzYE0aGGC06aNiHz4s4oDaeFf+\nBs4LeYg92SisKcDOgdyaZK//faZAy9DztRPsXBm8tNZP+wuSKQlHyy6daiMJPsbx5vUwFmRd/IEH\njXlsabr6HXvMqDjP4TjraB+S88d91JakLAkTzJh0v0p/ppO+T3qr13x+EN9vWejeuUdFpUeQrKED\nzn7F/NV/tyb2MGr/zoOKjzUIj8bAZtZNwObYcMJIin1lksPdD7zFKhqROp76Z9gthjWntU0d4Hu6\nSnZn/jtFw5w+0w52MEE1cM61Pfy0u6aVhn0mN8azkp3oPuGL5F+FKMlNWjoh2bW6NtJDAUtgjbr2\nAkaz+CgjQazJM+fDN1Od+yJjUeRq2rY7uXMETKRaJhHa06+pMfMJm4YKo4wAELKReeJ59XDF6oOF\no/lrDOYFU7fLfBM58jEx3Onj6l7Cqr8TBtLdL7BIpgr0Xex4EJ7SIFPHu5NIkhJXC1H13izTM+vx\nS2gDlGJ1mXsHUllp5V97ZAdAfodxEVoANpdGY8HV0it9ThxPh6IieSTiLjZOb2PN2lJEkL6gdYZ5\nJwMiigW7mWO5O0vegAYsCXnZyD1uiLJE9IEY/ycgegRu/yFSjSpLSl/CG1w4zJFFlvL/kuHY89kc\nh7XdcTGAUDX1MYV+aOWZtGN4YOJoYRNqjZipiepa2eDyOXohPwgKG8vCR2WH3avGAsoamNAry+nv\nzBGFW99eld/q7liFn7PaoV/tWXuiSCvla+ljelse2crwVYuqA9i668n9rJCHdQSgu+hotTS/uXuo\nxMMm2Yh9IkMqsABPmLaqJ0U3jhEUuTvFPBybzyK+ryXlKvFz6poTWqbm4dZwE4jYf9Iy16DE7XhU\n7pk2kbYVwtNaqnrd28NoSfQ1QWDxlMxX8aDJVls76jlBqz4/kbtuTczpqxm2OYQ1mYzuzoYCIPwM\ndZrmh4nsxpwAotxIhAxc7MMlZwp3FxWrsQG/oARu1xhzwpx6ASKOGV/5i5VR7VnUI7FZUI+M0xv2\nyluqiMtOMtF8HALMF4LvjqTy8ZOzW8LGJlnYCa2TA83Lb89dA7GMZmNxOhuL209w40Ob9t1u6Juu\nW+cykxQdCTYEPIdzi+jXREi7LsPC8qR0PIZo8adGhNla8Vgl33nDuTC6Sx+JCq9eUoAGvHdem7m+\nkwNANUJZojzv/c22iXS03Xv3r+pOc9Pa/pItWtPipodIOhbQIqhCWtt5KkF85kL4Vd9sbX9IhF4C\nIW+L9VFRj2qOJZ73JqWu8Bk1F4nJR2+InI8ktozYFpzp/gA9sr1cKTw1sUAmlFMKBKfydGFz63BE\nj+BJfd5jIjZSj/FhnTa5lytAaZZBFRcO01keQxGyZ/0o70/byWzGi2UdyOjCQt8BlW2FuA4z+RK4\n7IpRqP7YpoGswnJAaLrGGQMvVMV7PR68tCVSevAd4d56XuYMj/6HAvS0mjKWiALNN2/45HrhbxBZ\nOVUON9v8BN34GQGCegQnPqtCz0xHrBDnSm0h/koYb2CX5oMrY+hZ4X9mnLYLEPmap6bkgxKJpwvY\nO/XaCVw2FHUtfkvKhTMT4A4qU4OFRDDpcd01YSrk7yp1ePHIlX4GzKuchsSsZMl1ZJhatDCllPYi\nzpdPK+Hk1sSoyeqeJhyB7idWkaMB+cez8PIkJdWkV2oofFPMst8+q39Y4hWoMEdr0MsPdym96HYG\nrNsDj75fkj+I28FvuKdve38lTd0zRgM0wdZE4lP8v920uXbgJQ9Dn09A0zqI2h/5aYADGmFr3v/8\nxieDnavaV9WHA2mSIAGRnjvvf1KMOhOwupSnxH3/ttHmyRyQcrKr/lMZBXOYG5z/PQJ9QhkYgXOa\nxBtsk2IbvG1GGkYm51hNufN7B3ICVqM9pV4+oB71Qcll5rd2YaJ4v/syueyeWF6lw9lVNGE1XBbD\nZQRoOsWXU9d/IB9+KpAQPSkrFqR6MQANsryjz2WQ2nGgW+IyMfy5coE5FvFf4zWh6KMpv0aiwrM2\nZTuTkE+vTB3cE2Tip/1PdbBOB4qcpVT9yDEOI+4A2q4V+Jbwi2Ux41mU8uf9Mgwz0uuaZxo3jXcE\nu2cO7HJ0RrSQeg9Hv+KkOYcrY/E9T1DVZwm8BTbJVqXt9+bULNP9wXirCgAvx9dqqZ3ecDFMg9Jh\n41aUlDADHfu83YeMqMTLhH8f28f07BF7ph6j8b177LTOg7TFJHZe9ueD81QZ8k7dGDUHn5JMr9e/\nrwAvOy2es7XPw7rTq+7HRrhkWjhLTgqHvqpDBTqQbHTC6JXK69l3oe+CkpgleUoNwYhBuJ5CRdkS\nLf31oohTHa/i9LeczOSc9JPi//ntNKmhybI1247S6sFyyykEKtAvdZOmJoiIXTV0XjKBVEEAiZsZ\nELaNu1xIin4pvINiMh+v/bb4uiBgqvrXozgpD6vZdYOBjb98b53Sc6XCrDww5gDFd8qxXmEXy16o\nMGjNaRlaVSuuK8DGHewXmhFNBm8HCRXEGONFqGmN3FMk86bxtAVuCdnfNDwqqpYWtj9nOsW32ZTc\nubK3vRgfMTOrccrMrFKB8zMInBagFWOUrEQB3NAkm5thAbhChWeG+ni4pZSIFVYev7AanPyyfC9p\nzDAl6KPudg+v6cvjHfCNikIjtYFo8OzXI9khlVZR6/pSNNdw0XqzfkqVjlMQeYO7U347NuFA4Pv7\n5D4eslD/0KsstBJuEYqCjOvm4+lQUWpM/r6bXk4vIS8E03PPzA5yLlbUIi7vM2GeSdKM18sYkuta\noL0BzJsRVhcL5U7R+gf4fK7xumTyWaZt/d2YsDxbUVs8qG3tFlycFB17lNyxmBTxHZS7hzLYqmYu\nNC+hdNkkinbb2aubXwrqSSgXD70BTn1K9eglYL+h535HhQmICKMzYw/cCuOH+me1nFY+QktzL6H/\noGenNRxYq8WUbIMQPI65iOuMbJurmA0t+6vdM/N3Qzom6EPTV5f0zM4l3iwURgooFMdWnR89JegX\nZWR2UKl6a+eLokP6p/R6zeGyPamrvl9MRg9Q/DVN/P/YpLUakgEAgZfj2toDiw9p4/ej9+j7jnnb\ndAh76rKLDe4AWjxCcpG0owzd/gdmmiBEw82z1Veqs+7kGU8lvlP4XLCTPz9CImVnybdz851r19Og\nO7gv1FbPGE1hwyRqMPwjJWOtS2AU3MlmFsfTyAT1xl6ITiuYOQAVbc27EOCCIaMnnZPv+czVtf/q\no5P/ce0ZDqwiQtBm0nDblzRQcTNgWVEFP8jveQVWIbQ30qnpD2DgMWWl5B6PqpBboaGj8JyQqaPE\nSAMY5KTB3O6/dFnxDgIiQVDsebvNG5+GYovF+4GsAwhnE6YlpIR9UEBf3YDwnXqjC9XsppRafBPP\nYAXSpUs4heluoR3mi1Hu8VFggkVetdqEPzpqX91VBNt/UlzBcKcxemo5v3mXKdxcVUYSs4BQ740j\nTUlits1POv08EC7EUv4MmNbYVsMZ9eUs9HtBbRVXxSB8kcDf4X7En+WdoqPUwxxEQhSK9VYfPP4S\nueMnHtSSzxcyvc43oARcgm1dQzHWPRpkq+QjN9pHFW2qFnjBdxtLXQRZjVeKURXCX8fqGr66UzBd\nOXyBDsM/KyQ6m8rdna7ReLwC3OLso239d/U52mJ94jt2l1KIcZuXmzQ3fvKTyt0uGSVM2Cx9JPqP\nSmCt1ChHFSG8tFrif9tO+Pyt5VEm0kgzItcVK9qxO45PKcryWYSTTJfpdfLdjPrdzXQAXg5Rxu4C\nHwtJLD+KeThrAtIlF66B/jjLQiOUJte/gDjrpKs0aE1gNRX4EU9zJjuQsKLb6COUdEUdaNkD4smJ\n+WZxTimJLG4j5esUnhxI7dT1ab/4Z+jo/He/zUqSn11a/pf42zi2Mm/IWsslOU5uV6odemDOYXaU\ndFWceXMzaUtHmpf2f92iRCqt4ZyrRsczeT/b60vtajpOi7Et1Yroyc/iZblZ9+A977VczD9Gja6r\n177Qxyj5gr3lsxjva86fdnklxfPSr3VQjUWekFZjAxpD16c+0q9EZl6/LwEaz5yrq20ZenSZePii\nrUNPKhx5VNfl78ooEAYyBhuaNu1JlQOI9TNjG/oQFocQe/3JmyRPQwpx/GeFeESDKNBcFo2TEHOQ\n8Xh0ls1/9uYX5QLAm2GRwYcQ05VcUIDoMX6i4PsJJtilP7jrpBIjryFtSLWgTMDZZiW2/KsOjAC/\ncp74O6hZOqTraFKSwnoDjhd7l+DjWAfGyJw16WXd//uLH9EKEapobA6lslr2O/L4ZFP88gygE2xh\nP29btM09GkoDBPVJdv9SNjsJqyD52uGhdmUKZ/wlCx5AGuIdaET04iq1Q2F6+IWUeSLv6E8jVwxl\nubvKS7bEQ5fbxucR2Gp25+4aXJ8qZn9KY30fzCEfBithLVGHmTIffN2Tp2rNvXgd97bZmh60udOp\ngjaW7o3RNy3nSI4lTFWRTyrL+Lm7AXziobrqz4faUlLr4kFCb+N1QKKqQyjzx5E+cVBX5YacNXUZ\neDyhijfI3KgIrCOU2oJ8eH2qESrE6W+oHQ8GbaL9eliBcYehtInhxO5iLfeQJ8JRstjtCcwPnNVL\nlbAIYjd4busbJt3ewv3c6JBY4lINj7/KCP2uz6rhwOYBOZZL82kTc5w1gorL6w06kqho+FejLbCB\nj0RhiAy9h0+AgUW6Gt7ufLA+lAWRechLl5J/uuuP3L+ehtijh2OHj8I1pZ6Q5/FMb7pyvcf5uDJe\nv/IMfpte06TsQyQQPHUhU5nZjBYTHm8IUvfN4jXgKTsbCl4W851s4AE+4LmWZdDv8F0u5WcO3LHm\nXQhMZ4N/l59O/WiTeZziMAE6nreB+tltJqWV35cmnJms78+O2WwFSSLTkX1oCj1v0wma2Dhts2PP\ndDd7ekORt8lBM1Z4EJG1Mb64U4MlH+Yn6KryYxmBOqRJD6gfmnZ1q0ce7sIR5d8iHL0DPccrWKRu\n1aaYlvFah5Pg2NV7t4pf6MFHSd3nhRGcKjz2o04+2wamGLSH8EhrJPDe10ZCBCZRb5Yg0Ugn7DEi\nY7czBQJzOsFjtwoTuon0a5IviulpO7zr85LIKSqocJcuJLU8fYUA4EU5dQhhpwRTtsduS3Y1OCEd\nsnCuDW2snZgDdiIyhhqmC3iO8+5Djtg7rlovAwaiGp/u0PzsG+OveBSu5xKZ7QcYZR4/46akD669\nA+e+oO1lKlGXYKKEPstlU31QyUb1oxL9rVgI0gRRvjZTNOETHKNAUuR32aiytqTKlxosF3xZxmOT\n8NhTb5UQpskIqZD672nc3nCxPTKbyea4xVK0pWPLe4NXfm2FKH3KKpPyy5tdqMy6hHoJYV2fUA2f\n58VvQDYNtMRxWjJgLgGFzlZcgs5efaHc+G+1rCDcmN6zCiMmdYgi8BsgpTt/rYEzmIe2QlyKKPHO\n0AiGGAtoGqlR3Ugj65iRHTpGISPQ68qJ3IsDOfBuKB7lfs41SIv9u0nH4UEpHaD7kqp/63g2Yo3N\nWAO4wuQ7suqD4FQdAUBEdR7cEBYRpoX4SuM7wRswmfPifOXoxz870z2iKrNZWxKNqyDAujnnPhM1\nm0bFL5QMSrx0tcU0qFFGAxfuzPrVYr0U2a9tvYAkUm6p9+Y895EpMLazqu1c28F4ySYQ9bAEK/ms\nL0OFc3LMP9q7DTJyAhaJU+pnbXhJos8z5bRlfPvtWydpDCB3lH08DPgMkoEiBG7KVicy0D1Y60Yn\nimup1Z7MNeBxOiy1FYo/dUUVpcLsOWnYNvKeCofFP2QuxCpItrNyH90IRCOQbjUthJ41ZN40XtNu\nECpb3VM8e4mnsuy+VUP7MRi8qs4w86gEc8QZXpptaik2A5vWsCzldLNsJ+7FH1Q3Zj41WDiksD8f\n+2S/y9zfeQ/Oc27M4QqJ5qaCD03Et8H9509/colKbbrmzlLpJFvnaZs2zE/QIeBjKQdFEbaX1o/7\n6981V0D8nlCN6oR2TMG//ACfDwTeLCnO+mBf4kFnfyukzPklOEVsVKvOpNQIiwqjaI/TJbkjAx82\nlo9izycdz9FIIlRtiS/m53Nls4MckBlrtW9YGpV5+01h8riZVtvFZ30zX5Rpr93wk0og9Q5BcP0x\nup33LiOcX7STs5VoeKp6jHchA36Ms0mHDumUDyr65sdu7yBGpt7v9s2PJHNMrOdbynVc4/kzS9CI\ndgdKjbEsNA1J1C+iyNJgqtwOVowNNsXM+DwE7udP8blVhZaJG3uwZk7nGbCvt/ttNJoFQnqq9kDd\n8u4s1U+yfcUV6L/HIP6x6ufA6bc2+0g7/REbbn12h7JonT8vQxPBnmPZ5VMN4oDaUP2DDJsB8tEf\noVqNgh4brEk4NHuR2TL2WJplqLptBY4ogMvyCKAjE/x42AGQ2ljJ1d9YA5O9Pw4lg6ZJ0lxoqXoN\nFrGEiJ7QI5Wh2Rb/yRyDRUHkNf6LWI/Wsy/zh2TKQTiDS1PE4YmCMxl8nRL26x2StsgEnDoycqfi\nMk8bMnMP0MQ1F+aFHQEN+FVPLaxU0d3ohTp7mEwhoO6hrDW0xWxtX+4TIUnbikYQ/GpZucoYuO0D\nNUR/dAkfVOdW33cSxJOt7s/Q5+aJZpm0HnnWIDqBkRQ2kDkuNoaN4GWeEGKxnMXYqL2AcruLHTC+\ndzYwvzGoT0TqEV14BGlI5CoasozgBomy6kts7vQRAaoQkdy+PyB05dHsvtuA022+jn0n0ziz8xS+\nTb9pBgufu/iCUO+5mW1DQVdBp6B2o2DhaojldjHzf9HTzq4ypGgkW9a4ArhJaWqKcePyHPJ+Ps1/\n56LWHIxljAh9691uqx1BnFxIrAgNO2cQw5qODp/lf7bdtxNPMk+R/J318+0A7Q9knIQ3CmnQeXvg\nkOlUU1Jv64EVPrZosrbafQSD975t0N/njZwP4qqtsfvX7FmdNW7zV2bDseXXqKRT+igxn58sdxUL\nBzQkhHbmw5FhuvhQs6WRi+k/q/p0cYfBBsSmFCWB22KC1LxBNQ5I/NGItwIdRGgY5SOspWqheDc2\nfqNOaTV76YPyVwpd/d2BuNJW+ccSM8fxf0EOtTU1rSY6RrSF6cX8zDkl3X97GJ5APx9SaEFgV4Oo\n4e/x7+2EpapDXK6ya47Ru/T+RzbR9mLlGzT3F0NPnh+RziyCWNpB3WXBzCUbPXW1ib6IVy46dp/O\nrqT8FuKZ85hZbHVVmI015nw2DJ1oD01djrTOqfRdezC2hxVEh6uj5gUjwam7dei0iHjELPVWgF95\n9l1DuhWPGcw/aGAVBwJUFcLoc+gJxLf17CwxKpvSRgozOQT1Z6ySOxPcCcL6v2akwhG54lYM6W3f\nxcy0P1MAHbCugJAhO322mYH9QwOFxwLmty1kP1Zwxfa/hqA81CIm1eYuMDf9L4p1m4vpbRLbywUs\nTc696yyWH/K1BdQYivxSU8Q/7SrJwttfP15/FXIvnaed1vlyBCmp6go46bO5Inbv3oRYrFMiQ3O3\nqgu3aq09q2HfQuP3l8DBRa70FESJ6jCg/MZLL1hLnUHBFFsNF8Yh1hrnoNsllGTVlahlWxZr2k/I\nTgZ6CfuvG2GB92ANNI0YcGwhFsXSlbYoY9EU7wlsSQ/9D60zlgtImJ5fX194FLRgPvR+gtVJ510i\ntiiLI9fv0QLuJbz32OmMiG+P+9j4PR7mdysDLQ+8cjZuQUB6es3Swnj8/60HJhSp0uZam0WHu45J\nj/PE6OlPIa0sYt/UJWKCZ0YIBCmOfPeTWqkNzLfX3ADtxn/G8dD56elmL2SEvSQJuLqFtbhp3CWR\n3ES4LRYWebjDhARg9dHhfKcYjH+YufUM5YVmtEFm/WCifC3FQNDqD0DPPkNZ4YBZwJs6V+ZDy7JN\ninJmiVVOhYg+jzvRDH372SidIMnmNcMt7NqvnRz4NzscuvDOxyU8ztJeGMAYiHhuHuEEwz9zuy98\nlDwyjpJqSqZGrBCmAPQ1poPK6gnIH3S6jayq0TzNCuQpxYesLLGWPaXumkbejmAM4zrPdH5KPmeS\nUZov/TlkzBUf3F6jmLU++8z2YSXvle57rYO2F6JKAxppjUh8VrpV91B58/yUmp44jQFKoG3vC1s/\nHwdxA6KRC2lkzD4USVOA1viEx+gYXS4YfUkUzT11ghcq4kMS3Z3TQeMM8pt5dTqZX4P+fniN9FAs\nDMgFElu3f2WxcUURRSgQ/mUcx5Sx/mAVUuxTVqCaQzxXnkfTmWvJYNY2PtQr61n6Yhqv9011Hqkb\nvjTxQCVHMkDImHBRqkFMkAbn8RtXPxtqwoOFEfWQC+xMp0diQgvbvm6kIjx9rW3PfxY4h/V7VMH5\nAVaG0/1Oi0YmfRSyM2IfVOefyy9xR7tzmyYfUIPN29U2xo3hR2NK+13oBNVbx/RTnZGHR2tWtywA\nTeJarEo/WiBFi9O0xHXWjryVeFyfFyuP45m0HIDNdeC82ORm05TbJnl9hR7QWsWNOS6G+oEK/Fig\nbZQB7fBavBN2sHIiAW/IX7p3PRxzxrbb9Nnj+WRBYhjwks9U6aKmkpkqu4nc/NC69tlzdedf3sI6\nVE1Aj7V4+PwDwapXEsZcRiDKx0RYmUA3uyRb1ztKODN7GMwCc20a3GOJpZ/YOvawDzFvOsY30kKU\nPq0aT6OHXcj9qkguhdBdp28ecBlnlgqHrosc5s55RmzQq6OoPZDZUEvUhu7Vzl+Uce2lbXaWDsNT\nHtWslDSns4oTaLRO0ZVVqiSnxtNQkf1TWIIMX2hdWVPibX3pp4vH4DnE8LfA0GHNHAdL4oEFNXKw\nSLnmPgdXXByAtaVBMpRc2qPloZnfw//nvfWOno/HWHVVQp1lw/eDRZYgSs8Q0nsikPEsPUJLwuiv\nhPDuEaSYQe6uqcDgzqlXv7fyp6cXMVZE1VpCAJT4mIFIAFXLvkPu7d5Z81fUfbUXjHePG5WfWg9a\nOO2ePK/8D1vSkrxHcgOJ/lJIq4IfzHtY2U4mPI089998Iyqk5a/6SgDTPlMTsqpng+QalISPpmXU\nt7mYphlAkVXOIuEAahSt+W7HkQhaim/ZOy7CvLIHbfiC7T4l29MWRCqizwWY10fG3fQsvfh1qBoI\n1WshenEk0zVvyAIyNz09aFVlnz7KttsMNY0wxRuGkT/99ZEBYxfmMltt+K2DAEMy4l0ZQdKwyGcM\nxkDW+vjOwBJ3Hfi7Edaod9DSUD0OR7tI6ERU0oCannJGaZNpIR9fCR5m7Q0ryDLXGS7+XdyQJSTO\nwUVAI6i/ggoF7KPyxv/AOeHDxfW7DTZOw0eUb/OGfq06aWcnhk+SxSDQ+fUVRNlIw0DMX3OZ/+7a\no3qYB+wyQAQDE2kpjnNSd4HifsAqI0cbhwh9+EbXpvrIZ6G1zZ1fnHUWPyynWc+vLUhualnE8lBf\n4ahH0rPzJOgqyZhfeS6r2bPsKp+obZsr/3k2qtzXvyUp4PCZo1sJ0UVOvTA/GbU5RizU0Ef8QZ2h\nVAF/fgmU1U/vb2hT1rbwwIm6gLk7fEzLfJprYf1Zq+Yg5GtMudCqy4YMxkrN+7lfcGPoU04o3nwK\nhge/8VoqHkTED828P6cEMCPBwjbcCVAggg/JPTDfLk3+V+OBjAjjGLBmgjkmJqOa10jp9y+++hcd\n01Tcw96/OCNlPAy05XYGxQx88YULtlzAc8eM/zwf3T8u5G53TiSfjDoNekvA+282+SXCeUCw7hDq\no4flFFMkwQipVnZijpm45FCl0j8ZvzaKegMscQXv6F7Oreq3O369aQxNlZc3xKk4NT66hoAyD7tq\nrspDaaL0irSvsGIKEfgzhwSUf8UQohvEJtLLDp6lDkAdTBGLspVrjtUFlpCYBqEzJFNXsZzbjH1P\n0SxfZtiw2ZHHFi11xsUgQlDEvfDuOqOwgtUP6HZMEQkf6IlF/iakFbd3dcpWE7gSR5oJuNi/6S/o\n0bXsYnPORuoXWmPXP0WW85UIQnaMo/6uXDcUh61ubJjJlT3pBGT9mteiMGrG0VknKDauy1of4fPt\nl9I82BSF9K6uOYGTya60IjyjPobRujBv7m8l+QmKskat7w78gTq7m6YkImL60vL3mkH3NvBZv+cv\nA57vduc6oxpjvxsFLAOQYOw8YQik/bCjxHG9o0ZCQkYzegZNf6KnRXdqz2Nn+iuBPvLRIDZDZmHJ\n2ngrRGFv+A4Ve2TXi1oOp3OuUDOCgN9izjMOrAkRIDvXrOFp99CL9adcw9cqvI/FvSTf4XgVSP/u\nGDGZSLTHXcxgl7cfDYZzY2C240SJ0lK5pyJR2P3hXNtmNSZqyqz6zLWOjhFIAyr1vSkPBwJ+912F\nqZlXISln6ZqCFcddJ5YiJNnS7q3R0KETANewP1lFA9emS37EQzg1vqciSvATi5Qj+O2P6EBQHAqn\nMoBV6Akg1qosHoo0e4mYywv8zvVENh/g7E2m15W0p/53Fnn9YO2fF/iol0JrUJQ75uh2TVTx8WP+\nx0nDihv9K8R93AijYXmSzWzoXxx8f9FzZIOUxe2QqHJygE2WWnoOgJkgrdjV88BtxbZcCkeji9kz\nO9O8h43vM2iwvuhEoUgPC3R/bTFXdxjIw4UTvcuSFOknvmEoBvqQz3jTbQYHu/FCiYj33/24dSYy\nBoZ4fSQzphQcLAyw3jqtFRNn6jZ+ile/zEd7fS9NwolmjYvSJJhr9sjdxSxzzm00vvIDkp8yA08B\n8LXZHGPXOwQxBLPuOtXnAGSHjpE/mfEHus95hy3OvlXPCsLaEiCXbBwQVcgooTVklx2QxmXoOvvR\na8/mQxhk7GfABEIpmrnM++3/qQ7UPx7YDAhl033YyYGPoBg2ObIc6yHgbRMeVLVyWVnxjWZRlEIg\n0WhxpWo8oMX6fues4eGLgBLNOWPc6johVlx/obG+CVdcWfTPwFyw/e0YxRAbvP1J7lGaEywS2BBT\nBf00IWG23Rkq+QOofV2jbH4jI7TeDg/ANu9Th2WF1Cfx3YsB1Mm6G1BTUoSdv4hmpSGktzV3TInz\nZMkp5rKbR1VD4wQUn6a9qRsocuMc2/LW1VGqj6wHV6Y9fw9Sn8+obKavHUlio16XOpFuwN0MxCWg\nXkuts3SN83LaRFPL0ScFCsyVFzbeaRpYzWZsigDElIH8R+1vQvB92vIyq0/a+oAAu/x2geCltLHv\nY6kVTq80VTQ1ZdtfA6U/PGpblJOYr3XyD9KtGZpZS4RfEN74TxMOv+63xenCJqx7iTDpDLmcqHuF\n91f5CTHOLC0cp9hAR7vPtuly2fu/Ivy8Ey2qxYmyDbbQRmaiukpj77r8yd5M5VrdyFLljIbfog2O\nJC9W/HzrhadfBmQAO1ML8SC+VF8pDj/CGiYVv1GnMH6km09t35QoMtFmUmx8zPjk14H04OPleNXr\n2FrWcLRdSf+2tI00r3oYYVGQc/f0qquwBxsp5D+hz6SNbH3VpN0jsTipsuuNUbRH9HVY86b1tuv0\nyZT/CMe5IZkcb0Cb2xPJ05S0UXmVB2B8SZwMxTOOJ1q+ePrjWEjwLVphPwdADl3d6NqS4Nj5tbNm\nv2gkvivhJv7NmhDlHiSKn+Z1L6eNvhRCql8LstxsaybhUB1MtYI7rA59ZZ25y7oR1+Jr6vIDkzEj\nrlnzk5rMwGj/7myMuwxzu3t/ge1LsS7I3oiwykkFVoEfb3WiRn55QvMm1zp1LxhIHvboe8khIjgQ\nd6qlnY87YkaTH07nD2dRipDn1qWlNr3sjIyHbEIAJ6/KA/X6RJ8s5befMBHDYqNmSaUJQUvo1i1N\n9yWETXihAXy4zPSYCrHxfWVGL4+FhMR6idgtDvHHQwbh0dFDvEzlkfZsL93pUHWV76vZ2UNIRxtw\nLAzqd5vk5j7w9o6sL4kfiXQ2XmYDVFli8/6xD20uXkYEDPbODsKGNIz+9pI3Betv+Qh9ccFijgIg\nM/jKXB/GuGfbbTdMnLIX7AKQdlEM8T//VMOOGLjO/i6SXYcRDT0DgMkpUqnc8NlFtP4N2azXdEy1\ntUzXwoyFcg7j5TXspDjdQJ16dIWOh9Fnetiuka866sYu3tnPWmVM889cJn0qWQ1bzyN07DRzVM38\nKN+rC8ixmsFdTnRa5IvPIc9FxO5MBsAEwaJPaknBo/J8DgDaaJum0u1L8r4akmirJdbiBLg6gK+9\nzRbT61hqbm4aZnQL05pdhuE0FkpV6Qy1GtYrhtpfmcZxMD5sRZpr0SQBDv7opvEMLpQWq8MnFOY4\nFk7oMTCbJCgoCMkaaiXX6NprW3UiqeAKxbUxVLZhsFq4pdv9jzAqcXYHMQZEtg3gCMK+mTOc9T9N\nEnQgHSp0Mu16/Llo6ixULBQq0+NkrOWWfd/dKOCB0PeTIWv1glpn7R6NgNczQEPbxwc2tUGRNPDu\nMoQtLoSM11mXMcaAFo4DzWTnpGtmF+RCcI4mOzJCeR02Ew9Wds7bfov/OHBZJRQmmwXTQclcldSM\nhV+XdTPV2bwlUDPQI7cOT9lKOGIEMX+DFk+xhJGCIsJmmBWN/6TVdZjh/oH22fvn6KsRthuTuehJ\nlbC3K51XUybAEFWsd0y0wFSTkS8WOib4OEz2jU9nhsBwF7CMHPh2PJeXHCQisFU9Crbv93RAfn7F\n9c2PyLf7kh8Ch3X1SPCpjUm9FhlcVfTIlcO7A5FPqjmTe5VjVHOJPIgbGwLzLe+qxZ2l2nBMEjFf\nSUAZGU65uvNMqs45FywNc1PtjAlx735RXhL6mT2bI45LoB7rNWgO4kieeRsx6/RpBBRCyWk31IfI\nqrlxpUIHWjaDOX+4GlI3vpKhd1cAbJzX+JJJpOooCioZsdXFFWlYOb9ACf7GQ6kUx7liKJhxUgzE\nI2tZ2NkUCBKyCg0ORQlzlVqtxZyZ8ltAjCOciFowEYx+Sx/J4TYX01Jfd3MPJMd1Anzgkv6bs3KA\nC5UW6Grpg22uIkFR8P1SIYYqEfPRIU6zF254NeXiKoep2iArrCtPGs5QL1GQ+ZdhWolpLJ3YnzZT\nKiw2hmpljaiRsemY5bsw+1eD5Mf8sxxMRD59pMX4GCmXlr3EiOHsxxBVBcH0onBb5VGCnXMjXGLI\nHRw1NywSGL0vWQHwcSC5Kv5O+JhxmkA4ov8gCD1F655Yf6s+/nkKJkUaClQx5u874m5XIgowv45C\niZeqp/rBswcUD0zdouG3RS+rmkVhHFagARxwuX5R4C4Boo9IztvutcfPPRfqDFoMy0AoHCwKRZrq\nvex9V8dml5YbxKf1x/lxIoacQT+qGvFyKgYVbIotzBY1ydD8clT7Xf+R4iUQ2tJeIdIcJOR6SQrZ\nbRijVUGUOM39tTWrxHpiEsQahu1McGWVCJLjGX/I30xIO4MN6NbvsFDcMfJ1TNI4VFxodUXw2O/2\n7a2mV8ZoPoj1ggiFTMvy5dwZkWbazTwbluy3oByx2qbHjL44db1emNz/kdisOowLj6kr58i0wHI2\nrMYvkBEp8y3ADhsuMOLtcqf79ZkpNQO4m433HxRWppn2AbgP3Gy5sUztwpWwRuvjU5pZDe20lYXV\n1gCQBxkhIFZ972/ZFwEmxvd/EcXb6vvM5HVwooJ90A/0DRDMF2/OQ2a1s81NCmJ9/jKYqTzctY7T\nXbp4k22xLkNcBl7Lz4xk93fBKa7LNpfFFZB3IZ1T890rkzFS39s7/GovMkNhnblq8AmQpw15IkmK\nqHFmg5FQr3qkjLj7PolYMHTxMe3XowIONVm5qoJEh4Cz1hzk9M7j15gIecYWDWtoFNaNLeBHc5ML\n1genBmA1pIaKRUnMq1xQUVfHYSTbpcKIDmwjIzwQBbnJBS3AFegYbT6nBBZc98e4qC2fCRQA8fmy\n3pUTiZV01Ggh4Ei70LQZp3zN9lwB/K/GbtpnCF+UHVY/P0ivdiOlofG33ynJjvWr0eOQYWfGqNVA\nN5Ou1VSwtcylUWHTZ04rNU3WYKY8aYViCXpmC9F18lFv0C3chV96AiP/gtPpKyAeq9pcAyYNHczQ\n1koAd6I06qc3CYDmhxD0Xm3AvusRpMP5e9AjNBTjuPDKYk7CLO3/k49JsgN4F800hYyEXzxDvxgA\noZpQBOSfUJk98oQ/06RqD/GekQlTeGvE2UKGYYK1MN8OYqh+cliXniLLyFEkkOgqt/ddaMARVvng\nC/m+Zv3AXA36hC9/05QmPaDNAC9RtmhGq3aCYdq8Mak6sNrpJDrLP1GK0SscS0aklVnn7EHHYHBi\nDhiwKMV+S4krbhzcACa91fQ5+CZQgH5iccg0bgHVstuUzVbZGOd6mkVRQE+apDIiNNmVE2Kcz4Xs\nxd2Rc92AzlKCnGs0PNB12I+vku3kuWu6uM9N+1JOLEGyJUB10BZHa1PTL9a2gg8tlHa9EQ0b8quR\nTom1QtY6VyxKxZVA06GeBdztTVF6CiZJSSDHrcIKluW45L/sIUJi7KRxmoUl2wioiVEYRI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knJ7OdK4bexmuRF3iOA8AjJK6TmU6wa/tKhPbgu9LZaroURgRr+QGUOZH26nTt71xs1tQfaviPR8\nwxkDO598EEccepBfvxylJzDXc+xug40IqbGDN45GQgj62ezQYCM3dTfRPrWmgfQAK9yMJ0F0uJm5\nwotNkPHwcHlTg0HKFQdOkipFIptdWEAo1DpTSqmprv+nvQKQe3LI1/9U6Tn2om5rSLgyG1ZVpfoP\nhltd8cDlRFmIluWQtVxPBL5Odnb5lHryRnT0qj1tihrNMBZg7upm1/wc7d04mO5LT+/SqF0My/lX\nlB7vyxXt/8F3pDeI0mMNcfJGIseNmEGlfdmTBwUR4rYan5P7HtTYEiVmVUSiqRgJdk+BVd0lVH8n\nl+6kIrAIyc6VFVjx2wp+D0qSEzIglZ16ozmY/sAztQy2PutL5ry2rZsQPcxPCmz+wOezihE1UMhW\nJ7kfZXyN2rPslVYbB8F/W5GbAezoGjqD96fhhjsVR6fPDSDqDcR8c120xt9dvZiTm3bhhAkmhNM2\ntu3TxhtY/69sR1WjFJOq+rqaj4ih8pcd2ajUm0wvAjUXSdrDgQqsOvGli1vUcHIIQ4PE/vUagIBf\nG4LknLesHHb5rE6b4PeGlqYWmFCcu1QnwQpiVL4ex3Jtx1i/8kaKGQGnrXyUTlzXKs7YFcKEWax9\nyCUdyupbVBqFDSBVKsdTO37jGPrxK3FtKWQzlXej2vJ3bPr3h9FSvUHGpS+hupTNpakvwcqKqg1y\nx8V+yo1rBXF/fXr4w3FyzrTmERwPQBDALRVVJbYk/xBo6pugOxF0uwrvhcmvrX6Y9U/tTZwWVNP0\nTd+/TVp2NiTwSbWkbHMN6qLHzmRy7ZAaV/Xzcq3Rmqzf26p2cPGHcfXrWVOvFyy3bbKtapROI/ez\nrdJll5NlXWxUEBA61wA02lEOlnHWbPTz741z7VpEui5yh0D+njqzRtlUwMJnYPm4EiGTgYTgyqsX\nQc0CPQ2j1LE88HoFa3pCWPJJ1stEzqffFgxUR0lixjbmjCRBOvadE8j/XPSiBK4Lc621AVIiHTPG\nOxvQDKYp/+i5vR51xKgzZZMgI/3CebCj/ubbyskWYxDB1udhEIhXC1Y3+Wkl52dFRs9RvaX7iarN\nzDW8kPs54sqU/DNPs5BRhERXH5kl2AuyZH4HoPOu1yC/vNZ/ufbROujjLd06UpLMapFJ7N95xp8d\nSrXYvG+L4njnqpLFhMxWd6pZCUNl/TNDHxd9muv5/5Mr8BaWtmlh6vwLMlA+tV9hBJqZtsa8I1Cd\nKRwUTLAnh7Sfp1CZ1pL3CMcbr1bUMi+rJ+JZS2/opCpy7i6049eybJVWu79Do8UfsfkpoX3hFJOM\n1IDV/MGX9bLPpTgzKHuj1n4MlkXeBH0XWe9xfYEKtB+GkxB63QnXzKxrTJzaCcUw1Y3ZL4VaUkMz\n+d0gt1FWJa9/5nIfvBmlLYjkY7ClqIWzzesQBxyjEz7CXd14wr8w1LEpGgzDc5mhcKNH7QpD4r4o\n/3fyIPeQBDMOtICf6PHBW1qi/qcphnPdYX0l9vv8H6RYamFBeKcdoY9zctM28GOZjPyoxd/sEAZZ\nCh2TVU6BJpl0irTF0Go13QommbGgKQ6kXwONWOEe7lJ4Vkt1AmDe4oOA1QtPREK6H1koF48xO06Q\n8hzueMkpyyfsbhMHmqEc6wPNU6x9rIBR/63QJyDe/AEcB5kC+FmdqAAbYj3uHorKp8YbKW1gSVJC\n250s7TFUSoXigIcwKMKh7cOv4blOftJcSYovbLGs5JJrflpVk0c6kmR68f7hJsLkjue7ZzArwjXF\nUcMJYF5oVN2lR1a5kLuqKoNMhiTVAORA0GZ7wfayfYodbj/Rn0RNQxkzD2oWLkhfWBpd7MfmqiAT\nJ6y3CDb4Jsl3lRuCdVqa2ffbJl2embCjbEOgKYF1n2g4hqdGjhck9fpa1pMjI4FRcQwE+ree7LbX\nVj7yBXY9As0Ij4tpVtHYuYQ1sAEsuGyBD7PJlzEV+6ofUnFemyqNL6Fqr/QrGcszKTkgMqgg2Qz5\n4KBnLaQWd/Jx2fw6aqb/MuLJwdO5fQCUwnDAO/n8kRvPANRNHLTZRJr54JiwtAGuyzB524SoD56S\nqFDafagTUDmIE0vfX8BXYB6GUs/Bh3B38r1rDDUJlOdeLQtcXDcxFStqJSzyXXWCjCt9sL2lNgrt\n3zwGhCfewfILIr8uxjFftnWCGMj2GHVD3AllIxUXDOK2Gn/s45QvQ/vaWsZdNX1GX7MuxFBBEqxp\nVyqc8e3gMpMc3GV8nCZOhkEv0Ts50wvbk/Q63X7ZgwQLcAI3ghb0Nz28dCx6MbdCvm5YMuv0MFKQ\nUVpjjRNVvqSfjphp+I0j//ULfMpOvDm+eLoIfhDM9jsoTIxBQje5qHdRBdhcKW2617GKVEqgqzeR\nNdnFuXV/nWqQLxJ/jZJkbp4N9Bo+zZHrTZ3fuADzrksTLGmvkE7sffaZgKdeaKtDAJIBXE/TU9WJ\nx8FdMVwKyiHFqCo5hkUEQfgDvKDOAJZ5YYobcNlqDTGmku5ergFUMOuD0JhuufCceUt6gs/8oAwP\nPRd/6gDlSji4UjwrmQM0RdO0rGQMzlOq3MvMyocOsLyh41yPaVGWvdcf8mNc+LLJolH44mwmV33l\nEitWWx2OvBqQ62o+rYcOA2M0+VhcoC1PgSoc8BIuqTvkecw+qXvTnWcbfhqp+WQbL7BdjY7szr3e\nGSGL8UR+owT6Ii7Z0zqMQHxyLKyiLwzS1fgD5w/t1tsNPqqAiVPzODhN2dZDuayttcl8c46yU4z8\nTRDleIxOV7v0omujQO1KyRMWfpAv/KTTJzV63/4nWGbobacV+UlIj88J8GSuTUePY0pWBCWoxeC9\nN+wJyUejWJUt5iplAyR3nD+nx2JbZkrCv7r+uB0xo6H4tEd7zF+INfr/qG4xITCYNhnZ4AQG3yr2\nwRj2bgm7hKsKjAwsP3GT1/EZAQyG1ykV5Arkt+/n9vFfRmmTNiXYudbIK0tvsjY7zi8PUQ9sMnwD\nY10Ib9gNtItxe6p2YSSHyHDnzCEpatjFNU+7FxmzY9FXSAAG53OT196QL3Spmcr5kEzvVx7cd4OW\nmOy9fRBBjuEqGtIfdzGP2I0SqCVVyPzRtNaqFcNgrYf3+FJ6ixaIDJ853j1qqd7CUoSoaxCYSEqt\nbehAO53LSKc7wq+DwcAEDWGdwWrtTB5WdMc4DrNMavnnJKPJec3qgdcE/WeeeHhXXHxlQbVEJIH7\nzgh+5Y7Wo0RYUJkj2NCCpRs20sWgW6s28jCOWw9jkKCh1i2EF3MWBN4XDqnXpd+QNNGgUeJzzfLF\n4Ik5MUL+bNTYvcsjK9iwuXITsuK3+7RJBDpSmdOvQIkMxI7JxlZdF1N+u6a3Bi7rjtavqCiHV4is\nRWX0sJfldq4nA/w7qq+4ox3JBxliRM8jTCwhE/37lUzo+ccWAlUXAXH2OykmtqE5dZ508AbaQqCt\nIiAftyIN+afjkAoARZcIVSXJXMn5aNADtRpb9Nb84iNt90QnUfKXJfJHAKewiuWz38PMi0V4wrs4\nClM9Q/WpXock4IW7YDR/KZtgtkHTrSNI89RitYNDtLoDXyGpgroTS5VXD1bHkLO9cihNAeZ4o6fp\nOfhXifuqT2Gr+imGvqrlkpDv5VfTg2k4Qu73MhR1nx/HwBgAfB6SBQE+e8d9cThZ0gD23sJltf8U\nmliduPyOPY4Kdn5mI0sBukyzkM9j1A1oKowFKN+4CK7mM7hwCu9q/kuy0ZlzPCYv5R/uBQ5uR8F6\njZKqm0domaTJTzX4d+yb8e4177gPLa271BK5GDFanZoTqg3w5kJlntT/iq2CmGEX8bv5P7JE3H7M\nPZ9gB/O8qQX+reQ1WrYitUMgzLTEr+/G3vt9RNSUv0KPmy4X/45DveT7mIgozAqunJTSQES+iz27\nGFi+ySPMIN0Lx/45BCfZ9ROhf/WL8aTAHfiWv97Rk1i/x2d5x6R8hdcF6qu8Tcq8lOhA4U947JJ9\nwhMexKKSGvf3Ot5hkMybpjVHV3l8EvNXb5U2km9wfHrq0pAo2xD8cWyVdvV7hRGamAvhiRQUFHVM\nTNoTkijTF0XeIdMgnXnHPd3YQqE44Vdco5W8iGVLRsMAEm0iX4OWrlC7PRD4nUsRt5cMaofB4XSi\nGDDyX8urEeGTNQAh8vK0EqMieQAcpRWUDhKKBfhJbmJV6Tt9xPA+jR3PJFDoK3wFnD6o0DyYyFFq\n4jHIv2M/VoWXO8grejmMz16V+i3CDiXrNecwYer5V4b2pYmwdZpMtlIa+O5wBgCL0+LmlPkcn2lg\nBCtnWglkzqnndumS64SPDH136popE3LEIbg+nVgRvfP/EfyWFRm86cxxXezUI0ie9TmMMDj3Vkcm\nrVICVj32IirCKbqS0Sa+OoOKtt0x7ZzxeK6fdB9eO39yYxkvnnRxshIiCDZBQ+L//goaPg6E7o2k\nI8wY7OTJ4GAEU3LDN+DUwdgWIDt1Gm8rKz4j5WOAFYqr8xazyvYXdukPhYVVRxyxlx/bdEfs7ZsC\nOTeBZSpOcwWrmeEyXsEgZ873rvpRMZvM0Dx2MqqMIhozoPWvw1jQZF6rreEH8L1eSN3ukyGZQpe1\nCtBix0g5cXUI/KNEzFYC228md5Uzmu6FKQ3QiRq1bOO7+oH6I5mDLcxYVqPMwG1PIOCGtEvBfvn6\nXM4JxmhSBKqEOqT8rw09BpwdFdl7xo/KyItBCP1Au2+SShE6w5LF0hD4s2O6ivN21VDD/Ag3LAmf\nREGV5kSN8OhBQ6C5q3EtSu19Axyet9FcYMHJYsT3ddOUpiI1C49jSo0eBwD9BaNiE9LuBwhld6Tk\nPfG93ECqSgbeD54MbmynK5hh28QOaKMAfyhN7d+vqDoYuxMFKIa+o7YWxPKZOyQUn0nS7F/3MKNU\nvmDKipGdjnztH5jkpWGTSfdoaCX+IQLzGj3LxmY6KRYioXYi9XirIKz/pGGanRl9y96Y9oUitaJG\nkVasKb0+NoahzA/aC7Q4gnnXrAjkalR7P7NhAPeq0LqIro5dDephamRE5NFmPu9Oln+Q7q2U4AKd\nIRs7EWCR5cf4WI94hNTBc8ZSbtQhJqjiQNgGopIVV7Zy7XtlmHqo0S16KncAmSwxex+Gdgy8xX0+\noO/HLAtMF29SmwLwhvibLOOaUIv7hzbA/nFYZaEM0aQgeKkqijx6nq4t7qH76hCPZEHgGNvUaNmb\nJcZrNlehyfcGM0pemDtjAHpAVtrcxcFQgvAeO/cHh4QgYabtGwI6xHFSqASFcGyd4XKe/v8SapRq\nhzemwDWU4zfaiRjbSlMrTSQTab7bevyyNdrtw+ZK8xR6YovZ+2MRoAPEfJubWQzp6gKUWvieWHy3\nijUbqZkUws8uwRYj4CYTnw4h+Er6DcOjTywQB6mghjBZhxCkdtU9DzspDgpXKmfCaH5AGlA8Ytta\nwLjGUSgJym8vxs2oFN8775fKrdMAxF0RzCrqy3V8X+rb90nV8lIKAbjPT6a/3TygARB4qpivj6NS\nllirXVAXciECztjYlOByxk2GEk44iA+PdYJBMxUeY0LeAE8Mj4ubHH4L7Y26ffwCPr2EY1Nz0S4S\nd33gIRLwmF1bBtjFT5/nLBYYM8IsYHHLqNw+VDiJOBQZN2K44hQGfTV+uPXfBlpyREADBJr3dcmo\njR2AqiL4Y9LnKbxww0Vv4kb1V2I+dpIHBapRrp6Z5hq4wy3jt83PPrnjdZBhKQeF++ZGCqfYQ05N\nB/jkgqEebVGQpgkI7+1g5DkusTrh/QNp5XHkiXIt/f1jUsqY7G0a4loa+vYWu7yAKi7Gfycf4txD\nmpsgM/kEx1p+iu3jRUN99rGJfAIUrjuMk2ewscXaTWRvHGa39GMx1Wz9X5BIOYZjIormcZ31Q4Ix\nOPRN9E7nZVv3BV50BPgas9oX4m0a1NsvfIFIJoJREIJzabH7uBbyfo7iWdtXE3aZB8pGEbcHJ4/S\nQ/b+DoaqTeihkf5VAVAq+D5DJtVy8/3zbOUdF/12RGCgO7Mx2d/Bp8n60XXdQWTdpJ6UZ9xMb6/C\nswf0WgXhDc3S2sViQqgIH9zPJGrj7TmJdx9OqD0RASfJjuBbMtkdKRiT6nN7XD2QhTgekZvUde1D\nYZYzZ1QSU6F9k5YUJwYDcDIkTK8a9RT0SopBS+1YwkYOEGinQ1bGU16zX07tO3Pt3YdsKCdzkGbZ\nbDtEYo6e7496s34kBy46l9Lb/FsU7xAGLUQCCp4DxpRCu+cJczidl/azSdMERTYNEivtAwzybC5i\nKRS/MxOcT1IxZr7qdajSDSXBk38CsgXGVL76n+VtpfkbL4u+IBAyNZcyPsjUGBA47ZA05WYfqHD/\nthZ8eOTFmVjqi8yqnSt6RM8UoHp46w1U2OnEqCYxSWnp+/arbKsL89q+OOtqcQPvyj98t8l5QtIQ\nui3JaYejOOTBRpF4ZhI8b5PJZuEqo9ILkQqgc0isqwhBKGRWpRawhoAGomZ3PeneVXRT0BfE03+T\n9KfhJvWZrPO4aK3jv921fIehLqlursTQ1mBWtAhdi3EumyikKRGXDBAyI2XMaYS9rL1mY3Ox+IzG\nZyRC8r34FHbEFCDztA1RknmOo9iGP/mL3De4rM4uUnOqNybkc6BdTLyJKv13Y6PPyJc3ibIgmdpV\nRld6xGE8CckCk3ITldXhODzIhmrnofmSo84evJzqEIQurrKJ7FYeMXjEptRAjXBhhh6AbwQimAS0\nkFNUS6UKNTfrer+1MCU1BBdAYmA0E0ceL+6ecVjst2eC3yDmVREEF7VXpmcK7joqQQJy7EWErNXW\nKwdjfwK+jtdKMiqL9FsvCvV0Ws5MB02zUGeVq6fr3QHYSDBR0+JcToNod2TWNiVTVxwRiLtgxGc5\nzg9o2TxVf1QFe2ai7Cn14er/ngaOgxMDEpo0FiFvO7jFq7jQDvwdu3dC8LMNYJICYe/MpFWdrWNZ\nWp2j4sz26pdVaMGtMOTtCzRfAxRgF5ExAf/sW+Rio1RtDQ2zoXKoGCfh9mBcufaQcTTTt3d+0YyQ\nXUnFPnzItU8XGOu0SDUAGHfNRFuNKpWH7AqBzoq3iGRuaIm/ph9fLTFF4qJ/N5kzsPTSpQDARMNc\ng7AkJVOlVMqJHVdiq73H/7piZbRhC8DgvB58Tuj/fr3VxwKNYBa7WndJfBa4PMrF5wF0nQ6EaK3H\n4w7BwIs17aHxHsM4Z8z2ZjmntDTTBepfWnQQC7Zno1c2LL8sgYwyLdmbdejapddrXSRqj8lAXnkl\nuEfWIn5/GXK4wiOUqG6kOermYNgtwgRkNhvekpKxOZWqJ6jxYoS0nBnqzePQdTuYn4WTsamTOJnd\n4803LTstxJUAQPeTW+gnIzxJ+aooOzY/f/h+e8LPOJ+WgM+xkKWD2RdiJ579Bkkuy/AjUDrfBEqe\nfA96MoXBAEj6Cm0L6q+zvuR0nQTaCelQG6c7BbMWA81jFsE7iiK0oxN29hrWG3Uo2cXa/eaaGDk8\nsaAZunyxYZ22f5gDYRJCxmTsV3JAophBhBJ1mwyEPK5aeQ22TF7kLUWRL8rTpBFGpuUkRS6XmyYJ\n+FPrcwZ99IOie7Pbz2LjKHsBlHW0aYsy/0pvfNWjmTpYEtWKhaV9plC3yAjVg8i056B00u5gETzK\n6xI+PxsmHpaeN4KMxkUS/TOvU8fEHTeZbUqrUybg6E0TMC4kBBRfVp+5n10uaRLXf+gL+0rLIuWw\nzNjNvDa7LMYHnEjEp1YKajUkOPOsvKj7Mo+Wd77wKCOEOfhcREmz4clxqUVRNATf1Mi2yQTaTTJK\nwFxLmzMaDAJUlm3Nr7MkPW1XXHTS05X6og7J8LUSzQU/XqEuDx/ES264TiWE3gjfaN3yHUmUevTw\nmkZ5s3UEicB1GQS9iQhDupJFd9YlzkvzA0ffdvJGG+hQB4mzM7iHV+Lp/lGgr6CXMRZkDbkXP75v\nRFqoLttkDhEHwKH0JZTQxETP2gHyHYAxMwi+QzEjqkeY53SXOpxRHemulUTPrc5+3EO5xHvioKVR\nk965wCoq00Y6LiWzK9SJ9CYLrTqsAZxJTBqjrNEzelymKKFIF+kU1L/fiakTw1g6xDZ7EO7o7IkZ\n9iNjyjYlKQKcD/F7HLil4/Anf/9v9H8nsychqdQH8g3F/abR0TZGQEuHWMdrl5yJG6FbjN9kmdIQ\n07ZijWh9GVcPatbzZ7v0//Vl4XaXIKH0Q8F1K2atzrVuDH++7skt/O7JPYSdDPSex8fGOpfIwD+d\nGob/bPAUVVpksHL7+F015J/bFhH+B6S3/MPs0cy2P+WGDhIqiadOnuqpPz6KFnRAIPJSOPvl3VG8\niduPUWdw6UniMWSWAB6TMVpi8sS6LF8LS5kAlrMEMh2B+cio3y8yiMAqDfbFftIYFuGwDoAE4XGw\niST7NUVZlXqdbLdE81Axhtt2cQPqfeZtbXbbDp2WtBhAtBkaggNbjNMVV7HgsJLP96ef4nUIQHhk\nxgt3Y4UtTGl68V5mA9okf8kMStPbuwtt9CbTagFbzRiZIhtemMDl8/7bsd/qsCga0rhnQ72q5loG\nGgMgixCu0FwFI+tjs89+vFYykyklfr4415LAl3nnQVwarxTnvlDJsdKgHPJ0cWMPf/F5ga/XOh4n\n5Ap9eYEtoY+noOwa6pu1lnL3dZyV54jAx74weytTyOkbmvL61zI84JvqBzntvuzD5T74+NUFgvdW\nJJSrIG7AfgTUad2C23bkCYdS4QzDrKb8IGvnMM9v1WyXRTEXvjat2Kk8OnPeE8IvlwazWho6hLQD\nWTMDVvsYR3KXRxO6hsIzoGpMP+w1YSnlGyKT5/vOpAZBRdI4onvuaHgp9m3pXXW9jISzNlS37ktj\nbRAuzNukOf2Xfc8XpDvSUTAjdrkYKCofzXCdHnKOh9cAB1k5OZuqEjscbP4GdPXHrfX5h2DYlHBQ\noHuRqJFV2RX2EgSmk6vpEinQoTaQBONdWV6aNNmCCqWVn3FM4NJ6UoKYdduWSzSKM3SjzCpUb51Y\ngalYLRgP5Jpklf+ZDr3RzdD/DtB2vGZcxQWueKWc5ekbAwMwYLo5HiEAmJfjM+scgM24uWKciMd1\nYYlVddFINbnsWJl0ABvofhnZ1bohiNUjSc1V9Ie8T5a9Sgx9u1VvkeKuLUV8STwD7rUV01or0HpS\nw2WSAs9pdIn18TTL2fGvfRmVV56BNcNrTWYxvOHjCnlKwiasarmHzoFwVD9POKgOgpoLYmjIkwmy\nyO/+282o0T3esSa5VjQHSYdsl2wfb8DJC9OjBrBtIJlmrezA8iXFFE2t8JcxUj9YHs4eGIuwVwlq\nv6yTA8EGw1xr8qsdxe/XjOANT/+weNBfNP1O/YmYfXOz8IQEmzPSX1VjQQE0RusS75LaJ5oOV1qP\nJFdVjlyawwfLIr6YduddwgWxkOMqWbN22WXKdFBnkhN6f4qSKIdrlhyBWueYfGL2Nl2hEzpAtlSR\nn1hyp58VZFaYketP3cvN/rRyFQX4OlMDmpvkuhIi0BLqQqmZL0mZ/bvdDmrPHZ1cbUXjufxOmvMU\nX2h834ME5PSJU7Vdqs3/ieJpKWB8zguWt9IUTGVcsIflJsnvcwj7VDXNG2/zHqDgF2SQq1lFeoXH\nFOiy3Grs+kss5x3nd4FksMCzqn5/WqAnk9dGAe2ttSRdXLLRlEDuEijcLZ6tZmpLuW3XyCL5YiO9\nVDQBDIXxUwHegxI+RGc5BBddcPuaNry7e845xBbV/zwK0FUvnBU4vQ8RFNbbRC0QKNJekyyg9tzk\nXAX/Gs06Bc8R8f0GXG8JUypHjnGNW0dntgPGcjCp+kKyot/n4nTBpG1/klj6lxDqoUnPfVt3V03n\nriSV/54K6112cWe+0ltKsocKLsZPHq/ediOdPdFN9gAa9Iw/tb+8/EWlxCuHjCJxH80JntX50Jza\nJVS4wAX00Z1MhHm/rU2z3jpYzQclf341hkMi5BqqTouM5qPrdu3WOzVeraXRLFUnEdR0PwlhddEv\nVSwGTAW49iLKuCtC/8POCsMnBnQ51bI6X05oTYwAx7V0jZZbusYvPYxED59G7UcPNOObxr18ZUkb\nPsypZD9OCe4Mc1bQywKJ9gR09y3RZTowstYnCBRDnEzn+4WWxmNJxn68O+zSf8voLl5XSqeEtWLY\nOXSspRdzAVjUSshk8evSDYjMHiXXgL9YeBAA2dlClia7sBD6LoNy307XC3wkPpwXUzVja9qs0GUy\n/lYL9AhnT9ChldMNn5axheOlgPa/k2WsDSkoy9St9alH9momRJeihGfgwumXTxnPQT/vgXfHmpJF\n+Qoul9gCD84t+bR9a75gHS8Rjtxqf5Lc+2BBc86Oufj7CZpRPCCwLReoGg9vO1d79PaQShDN56BW\n/dhN5Nv/0SdfXppb2BKisLslRn/rb2JrDfPLQr0NiWDS1AKYDlaTiGHyXEOQPmtigLOzgcf52fKL\npCA/y29ZNPLVv0uVjMpc1lW7rJb21jVuvJh22a4kKjQtH43MZOefYIWCPexchBjO8ugzUNM4+OwF\ngQ1SUkeFTvpp2BJlLxc+VEpry3c2gkGJl7TBHpXb8w/5HPCrSMuZnGIH0OypNM4ZENBF5WcyPWau\n31kIdopEzpLop3jAPkEkSxLdxuhtYsOJ2fWdNWFjyjimlRRffujCFOuhRestLtXBjrUHrvD+KT0c\nPT+0fZrIu4aFJ81vhIRYo21O5IHu16Wiy6PXuSEsLwMwx62OAG9SjOtCe6GrALWVLZbn9fg7RUen\nKS9xY4DOS2whXZ3E6FF/kReKEa8iUdqZ9lPlwOW1jEfMuRntWoFYdsTfrBrdBXsDKY11K9ijsUzJ\noSAn9hLPU8n2xQ+TswA4SDZo2wKdGqXXfhdCQRN2x/2wP6PgnF0/xRngfuHD6z6g0mWMSp9uTYJm\nb0jE3MCXbXnu2QYpq2IPqJZybKsqp6KmylEZ0SmAJ/chkpyTkDx5Skpdei7BfkIYvWPyx1Yg38Po\nTqfMtrYCdImzm8EYUO7lEG2xuNi2r9ez50adhfEIqdzix+s9sqWO78OWDogI47yDYKelMC7XJEP3\n7Dqgzn4GToCFkM6H6nqKg4y+N4bDqn/9m2CjJtC8+x0ekRQ77XcEJtwUrafdWggssRUqcZp3Fvx3\n4ew6bTxhghgnEgGd7sN1K+bBc4oSc5EvhtHIXdGXei7MHMPJ0EnU//KiAn8i9NaYpDgUe0OjFTPJ\n4+M/wv8po2jL+C1H0pR5GOV32D2tQwXXctdP+b7YmEwWomlCFhoOpSjnNT2umt5Gu2cCMsh3foc6\nnGqPlxXbxBO3kTMcgLzKbc1eVgi6Py6DQ7T2tMKzvjvgjRokEalRcOg2WRdh37nvssrlv7HdZllP\niSdcN1o3bAT7tMqYcTbGA7frxm2n3HH+E9ByhQN4BAJhK3/bsqjMe0w0TTC9hB/16tjGkPnIgS3S\neo8Nc8cxBM+Soc7RxCdYVdy2vm8z7LsqgvOj50fmQLEGbnO7YoRiKAUqvIJMIG5auWSoKjsiS7bp\nyJ42kgp8jOaqf6iCIh6DhSpLXux/WxtR8R0nJVj2BUMgtWj2a+jIdQqNn5Z7TTdvEAhn5jfZfO6S\nGT5b5puIQ5om3/xEIZFrZYTOqXcO4OobuaiHedDq+/SPShf2diPjqF3wz2xDUovGYm4csl7s6Oqw\nosJkPk2S/CZFUfNQ7DtqWEquk7B2txE9usuirlyQ1wkxaAJ5wHL7B5SgXn9yaUv43Qw6Q1wfg3S3\nQX4hnrPgQAy/u5rZhgLmo9PwYVGl80FEHndkesPJvdeOAaRIDxASWHj5BsAZbVANH++YHRZ4+YZr\nLBCOTuWTo8bV/JqfeHEsAssONlrXhJzuNkJY8xiI6wulsSbzQmh7XBU1rO9PXKq5GptaMCV8aJMr\niYMUQ/R3fTk8O/+DpwuklmBxNWFbWBL1KAS9MLPDsWhSp/yDC1pDCzeyrMVlr4Z4zq+Yg9wS5Ncv\n/x0i9CPYJ9ALtMXEgyR748kh9Rj0TUWV2sPK3E/OnAzo3r+hM31r8H/tpvj7LC3lNlhxJ/vEkmd6\ny1g04o6u1XKuSE2sHPWOgK8I+AwqDx3Gs5BiMCfwh6cvQd68vMDiIIbl3991YTdOtKPXJlyuj+yV\n3YUD1XyUo5Da7kWwCdEvpoM7IX8Se7L+KXDFjKhQGb5bJ1SxfyljOmuaSnQ4NDFPSu/9qDr5FbZf\nnEl0Qzihz29ITRKYxoxhXhGm5JO/DpmEpw5i4GgDJxrZyrvru7u5f4a+wigU5Mu4T2cpWumcSto8\ndNw7yzRn8npbYzqcF0C4YmIo/iY1vk5nL/P1XSTiJTWnPRJ+fg/wnrm1V64MAxEyU+aHS5cPArZp\ncBe7BSLPvhko85Wf6hSJ/EDNwXHwIv76IUKfmeoTcza++X0VbvnJFvisstWiqxE8PBAYQYUG3Fix\ndeulyVxxCUY+qMp4r6aWi224LJrjeUD7rXAJSJbTcESYhwzaQdQtIXh5a/bp+IZYdQGoMQ/OIsNo\nNHUZkT5xDYKvOYBGQOU/nclPovh/vqVHYq1cX/9GQaFHJaZuQUTQ6clRH6RUe90C9mmn5m8iDqsX\nqt1nw7pXtIjgEKX8Y132VZOmmagqgNcf7VSvkxuycZi0dONaO1MB6WnmxAUO9rH8Dhf57Tr02rse\nGE1RxqXYiNxIruBewXGhWdz+vI8BsVH2v8fbJPd18M26OGq5g3G7hFnb1bP8CtJJj/bQ3948U6hE\nP2SdmWlesH+XuARCnN+EJCMe9+PMfCeoFbhf1g+hK41jlfeLt38/RrCTKvGwt2kwYO+7fvZKZO7i\nTwIDksTluOAKi1WZuHqYHWOaOQYlyF+QLaSjYV4YLX+tKnJ+K9ulJ7h5g1g+69gp8dWFPtkQJYS7\n6q7TJ5kXCUg6mKH/+quoH/fC75hK/umzNpVBPlyJop8CFu7nGpQg5M3EJYyWpa6GF7vh2H8JGXWK\ndgmEFznzumt5FAVGjevzem0VFI8PN7fJxmhi6L+/uyFrqUi7AiEFU7g0a1ykY+lYd5S0hfWcJtu/\n5OQ/nUQJLOs+1WPfuDcs3Z0Z7wYE+hZjfHDb363lOHO14yZvJsG5wDIY05pKV3abSe84K/OHl+/I\nBU8tsezAnmdhVD3VdDA1Sv4N/X3SL5RKJEf+zk5MvbAv4F0+8BM3Nvu/k7R56Cyj9HR/wZ/1K1NC\ngcbtbshwyQ53lj3P8MBiI/ef1w0GZ0wdvO/AOol2lWNM7CmTskg3LppbJrn0FWeWEc1uyKK2zVal\nWmUf/GsoM0zxcBtzroVkJo5eRtbJcvyzr58uLYMbF1sBpgIIg3CKLUhwITeFSZK5+wDUnwGAgdx8\n3nNG1GEy8t7K+slIceukWZzzA6wpXyDIGIYVd5LUEorbelg0weeUGTWcHi5MXcLCTCenKQ5dLxuA\n7fm/RE4BsjESxkfcbkkWEjgBQZDIX47uNsfv8Kxt9yE+Fpf9Y/agdqnHRk9xO+bb++aph/R1zh6E\n+J2BegCYK1v7eVfyV+0elskgnjsFI212W4F95hdk+3ewabS0hENGnhrOhOfAVCAEfZq1BaiqAVaV\nhQ8UFlp9itlqb7En36S59H9d6qH8d4B+cNUrLhC7nrMnpb6GRhtNBqhyc6awct0X/2I3Vxa28J5I\ng/OZ/bR6n80i1+tt+A8olmD6hTP3Qt9T5uFENCq4Jt5y8Mp2+7HLORVDkB1XDwiIQffIL9hTEt/S\nPq1ZrGzJlk5shMFH5YQUrhGbSkCKVQhQYrlqEN7Z5XGsucwP3KC16LFoYHCZzQE8gGdhyqiJyYQr\n0/LsIQvFc3W+dSf/rpoIQIfBCe/OZ53UFXkBPIrCLm134AdQn1dUUPo3o68bv2dx5FSILiGvdd/2\nX/EeU6FSuN7xgUBWwrSqHEgnItOQA2fRVL+FiBjP/KUrWUm0QcaehnsHhfRuedaXH7/8SRL9v4qJ\nqeSGfL2teHqfhwdiEu57YNuLrNl2E3faneWVvBsxIuoXMR0tr9mnOcRZt8GIkuArD+JDweycj280\nFgXNcwLSIuEvjqpvKhBCjFNi6eHXDcodgGC1wXwJaxjN/04MJqwn61zS5xJOdNurTNKqc5yFlJba\niG+Rn7FToIS88PEa5hV/4HTZ45RaRDGBcPaVzSJo5pzZY35c1w+cy3Kw30dzi5Ztm9JNIVmXpJdK\nZbCcmD8Ne40WtXqDD86xt7pMWGqrn6QfATRPWb4QOqWdxj1KG3iR/j00F37v9Nn0TCeI6V/s/5fT\n6RTkNWHqz4pWxtHBAwzcHvjQJ9DXMCi8G/JblIlaOF5b5t652GWP0zKRtlJugXjKbJPQja6HMaOI\nngya+iYaaZCVUqBVoK5gYZ9QPX1KNT6Cq2gGD6ETloH/Sc+/2blmrGjNCqju6puw3ZzYuWUM0ZoS\nXtGJ4PzL4SRL3QgItHxp+J8txn2Ero7eEjKR/yesxZ7pbSCIbap7y1vRDe5abVV/+6TZQFQoL3z0\nFvfw6vr2m54uTPDR5jjZq7x1E5Ni8CETEv4nM14idDFFWBeHLQDfn7AdbpzjIFBqqfzxaBiIceRf\no8L+HKxegoaRKyrckb9UE17SS02XauW1u2n7pSp10DnLwt4p9wjUjz4nP2jCF+VHt1hhrF2ZYq6T\nYBmzLxdMyT5kf3TGoAdzyxfCTr1cDuX+IQgndmHDhCj0hV1zZTCicAZGNDt/eiHg1q1HSVzweLgH\nmF/42jpL0Guj7if4UyIXG6m+VGBxtcryK0JcYSdcTqdph5c9Upf0Jd/wHQ3sG4Bzk7yKes3F3br1\nQYkDatkVUfz+LprUWVHIN5ChMGpctw9LntlYLr6GqynNoJCxvHQRXvazcdauZSSlUNyffA/qA4Vq\nwuLvaeumH94x7DUlD3rU0cvKX8uDtGq/xBCkYZEylCa1ISOoQETVCMWxuOqLVD3HzuSaZcv354J5\n1YZ2IC6NUnaR1JB626tbw88NQQ9Cc870iQHmj33yys1E21naXnuL5okk0BYUAC1vw3JYuevNRCNN\nwgd7BlfpMf30MLmH0nq/ujPtqkPnMubD4aU6EB1aobM3/I2qgqTCV4CFpOIoYPfvIopM6fPHdIbN\n9G48SejygVN3fL+jShFRq7YxVf/bLtxTdhoCDfDdvIPfi9Z/hNPJmlp18CpN3v37+3LDxwhFn+MM\nCsJk6KydZjRW9hCyNX8OahWnNlxI30N0TVrP5X2awmGTdoAj3VRnqqga6scWhuyMzJbf/M+xg9WX\nBHbGZJhc88xdt4x1VyZHiQGLUTg2xWTrTRE7arbUJ1DZ7iUvzG4rIWxY9PoWBGq9k5g40VzKmo+S\nF4e/5niTLRtSxzQBJo6SNOSoMP1vdGDUqtAaOzz3etBJfuji6NAx/CwGfb3BFARgHi3wi8sdr9+X\nTVzq87JM40mvt5zHIqFa0NvjIOxy4YBsvkEZQBT46e6aivUJPmn7u8EYch6MmnM9ss5l6ALKf3eo\n4Ul24v2oGOcdX+9GesW51mryEzGFszBgVOMovBYGqfHqCfb6kF81ZTyXALs+mLHp0iZFX2QJGBVQ\nxC2pmIFsoa0pxiNdM7yeFf/fNxPJPPQfe6WNrr5kMVfI5Rmitf7qiLwl6g/bbT5aq3NbsQKw5kjO\nz4gawY1jPNCZ5yJwCaKjLlfHNsAxoEOR4ZHANwBM06qBVcwf7DQ7UTy1+UDF+khhn7ChBjTS7k6X\n8fEtJc/hmTcOjgXLVBYVeGLwzYb6+ATcCQTZY0IboSgbzrDYF8hmV6u2zqKG8a6iD0BE4880OG2a\nxzswTErcc5Fqh7v9529uIwtTlgECVsw+2ESMwunxY/SdAWmvUS0KyjgXufmtInGxWFf00NG9l/TF\nyzJ09rg3zt7HTfl5dDWz0CNkkEUN4rxoAOz83PFtRZpXOMsd6PalIzSmiPsNOWRruI+Vdz5wnacT\n21Fx4Ku/ObDrVXrX+JwgKL0+jS8xcDo4QDuXRl40sTvAxsZEBFKKwHWYm8CVOyeuZ7GWWphw6/7s\nDJiFv1Jj+os51ZhVPW0NwE3qY+pOaCJg690SeAZtTuGqiPI9zMPeTHFAlXXBzVxLiCPw+HY0bdT1\nDFLWaMpnZC6HxGAay1/V/9uMV2CkqjKavYHZ/IeO7f4i/PH20hLcm65aVXwqVRtzPWfnpadACoTl\n/YND48+WRYpG6bKg6kquGPYPO5542KKedZL7zKPV96/wWN3iRekBY0T3fIsziA/niy6DvemnwEnm\nuWfe4Eg5+ht2G4hJv0zzXAPCk9/saWdut768boY/boA8bJD3iao3UqEU0CKASuYVMj/2PX5v3wyb\nvMVU6OqUyh5Fv3BgbhS0ka65NGxyrHLYdQuICH8Wf8pGQFwrvxyPgTaFZW1crAKYELq9tz8mR16A\ntSW/gdeef3x0yMlhTUri+zFU5D4cgacJ17TgliGqxKls9vFjV350fB8IIxuva60Pb3mBcFSsWqMN\nd/DGXtVcRcBzNUjC0ejbbVkprYPZ8LD/7WcpQq+Y/5+0TiBtGx2R+OulGFL/zltT8zT7SdQWBBQo\nlB7baB+V9JISBsb5i8yVNe3IkIr0gwdvaa8Oa+Locm5ATwJu4JlYgKYnnVDrOYod57DBKd1OlT0m\n3Tvjscp3SS4hGeshIlqE7OtzhzqSHWdPNL+c8Ync75AvTvAVvG2/oeYWGQ4NdBW0Ed6q72t3VMgt\nFhOO7ozVu0i83MQEwlxOlEeAY4eUXv1WtzMwR5n4f31+O8/aKna+RgFLE3RFU18J/GEC8okUx92k\nrixM/f0Bqeb80zXcVj0gdGJ28GTzO6oMKSWcvndyrgs88mq5227OZsMdGVaHeFy3aImlCZmkYOX6\nhJPcj8wFjAfuF87LvzCren6dQn0QC8z4DWZ0dDyqoRmNCEgCV4rtKvwrMWjefOP9VOurOGpasd3f\n6zFibawwcX+4HuyIvu7slAarLtT8BpO+U70r9HmIR5x7h8Fneergz2ANaKjcpb/JPYZHrXaELlpj\nyM01prx99tbKdjVdFVANuhG1FRzrd82GGLVkgKsqrAl7JYy9aQxfPUb44QDz5JwjbNN/0ks2Ax7u\noOVRkwZTrlzF8vd68LQYUscLKVGbECaWsH4EAXOiDnQXQeIVSDbLRKqq8709I4yMnzoez9IEJ3pM\noQXPrr3xbScBhIawQif832cb8qU258kvXmg/EFhEkVqMMBc6tQmmrBat7wvb80JostlMwLaG75sW\nrSf94nSLnWMz+pCkDXek8GgpLKNKxoobv6hSlB23XvLB7CumzayqQlfixEdQTwiUnOZkpc+4DQV3\ngH+txQwdRYKkHa2qM1lKDWtE+g6VnOLElRqlTRWDcV0lng+4QHoJgZ7ZjbV4NHs97eVoOhhRsxa8\nWDzRcQu5Qwmv1tKLMRT4oojOYOjqF6SuoZSdDZIAg2gsoUzXETHXOD4MZ/wMOf9qqYEuaLbRbjya\n7Nn0o8M+L8iEqAy1yKxs7lVv8EstxyH8TJHQUXwRF/OtXp9g/HwuqsNBc7RsbIK8Abt3nyb8dw3K\nIsGsaOEeDObH/5bD51XbJB/i8GJwFG+ItXGvsj/ktHNMOT7K8jtHyik9AdJn0op1rsuEvcx5qlYQ\nG+PrvI4ZEwIcSgmYwhe+0IXlQaK1JBWpc3C1Vl+2485KA1gs8xg8fXYz2sjET4nYd4gJw0EdSo5h\nvKQeiOQWRqLgQA/Fqh/1dp9jcDS+MRUlsGOtU7QLS8JiMigefGZhdIK1XGT38HchT9FlJJC1353l\nMgoylrnNA9kqaQJQbQ2jpYe8/M7Yg/DWbX6ctLEfDO8yj8yZf8+ywrKymLw863v+DNBZUf+EKAKv\nnT9AC83ErWNir2HMNy4ZheHMTpl5IMLUQOesYCNAPhvrv+tqtabZNTMDgOTqkrZfPI8iiiZYagt8\nnW6DKKMItOkoU/Rj3Gl6tBN2t22eCw7tunTH6vReJOtXyaQzmUCnlLgH8qCgVeR1P3AmpRhzQJE7\nnOTWPGTvMl8ON7kIQA9n0aTFiMwvK3k7o+bxehT4ttlTitNrFeCuwgNGIjCV/uKSnaEki+EXV1NZ\nnJB7c1D3/Dd428muf4hu7M/9eJU+VkgYktluomuh1dB3QK8zuugivE8ltOeG2WtSTpBVNUUDJ3vl\nL6Eujzro2z7+e1N7aLqEJOPIATu1kj5U6hgKcb33rVpKPmVRBblN5qGKCPbTKNoH7A68sbERROMG\n/l/zlQlZiZbVPmpzG4PaYSnwd4hG6szG1nQDJdyeZR5Pd/vjDqf6msZK+83B5ynp6uIgSay5m1Td\nSFTyJi0pmmlFbHmCySxFQPo7ifdzQrGaioTLk8+AcD/xHe0KQeSkHYboAvA0EvR6EiXx5+hHciu7\n42RbMABx5lEwZFCYBrZ5GY0QveGE2+NPwRpZSIiQhB2O22OriaIUg7jp4CRvsKa4OBq2paZmn0Ll\nfzTKnmEdDS5IneDm4Dt+7Vj9z3jiql9N/s+Tv9BwYvwOnhFA62DJVlFxMKxak9uAJ75p/kzw1Gpn\nAbMmIySTSuKZ3fyfI5jIfTcW+CCAFdNHwNYx1veZHiwtD9jlbuZmPDWUPPoaI+y5MJStsaEJUlxw\nvYVaGSPRG5Y5ozKsceBprFjDfX2/Nd1wmHdePi4qVWuvSljv7v3sugT5vUmVAEbfU62FqpuYlEnj\nSFuDuExaiRgCJxWaNfg5gn5KQ8s7uyd1wRHenB7xzebiHmp3bPnbDGDNWWMeMc9R6eDTax+BEclF\ngOfcNE2MB5eoqbJuoWH310JU892h6FmJ0K30Rmn11EqCY/jwaKVmZGELpZxOCcMBme/wobKQWTN1\n8di3YKeYCB5ypJQLqF+Pb6VIKbwLuDkNGnYWAns2V41xRltYdcfKBiy94xeEG/IBRdpzuS68O8NH\n7P/6hahyBzgnBPaEG5Rs5cKGukDNmM6gkq5jfbd7V8Wc5EtXMvI16qvKinTa6HqnYc7tQl9bGWUF\nj6d+efWOTKXKc2GNzBqJAkhosZEoxP4IwT8iSwUUkLv5vIUjXPXlz0ny62eGTJlDSIaRG+wdm9pE\nlwTf081AOOYTV8TissJfBNms55U7nZauC+LacnW4ZIlA3Thnh4FmMEJwwV+RlX9sQc71hRsOKDtk\nFhLj7TxC39BtrfAIwuQcL33PWIwVlhX5i+rABaXQb1CMUYEET9/SBf/tS3n0K86NMw/JPImyVd6F\nvbAJU6dLGwAeZK3bph9P59W8EBlIgmgPeeJPb/Tux7FNHGpOAqH8+/PAXLuz3F7/cvBxQXsDO9Xp\n07Dn6qbrNEP7RgsFbJzeOOh+oM5Q8WJEEuIp7n0zaW2jq9bdaL2lO9QEe6u0zF0OzShLSnQ0/a8q\nI/SEbnYawSLWSuSrhCbGoRxz8vJ0Nn8z5KqZRdfaCew9kk97HoU5ItR2TjW0C2dQJp98KAmcPEDN\nS7Tbl4S7ZauhGW2dRP4kEwY0AzdJgGLCqDvfYILQ+l6ZRIfGPd05Umm/RiFcSw4cNrxghJpI7fc3\nYKAY9GJ8J0dag6T8cpcUGntIYIu2rIIhSJvcsRgZ7wPXSwxM3RncCGX9rhwdvww8taumueAhpvuF\n373xbX7oTpfrVq0w/CJajiX5hG/kgPOWgxzCOp/j4YHiwPVa4BDdyD+KBiBo6lxeqhyvYJyROaq5\ndi6oG1/pEIV9u0kymziTQSz6k8/gPNmdHXItioBzx4pwatpLMrEallK858fQvycbp3HZ00gUitFf\nHMIq6U7JHoQgS3iLURBPHj+fkLEMJ5WGgyGQIWOf6I40LdIWmo8zbTeK8dBAo3mwl9fGMkDswG+U\nxOPLdvEQZtAJ/0P0xjZUKPS7xhhgOj5+EHOaR27lXaPwMbVdCqM22WJfq/h3LNGHkNMka+TH9haN\nCDIDpHhPDXJpHSfuvro9zR5gKMYODuO4YkgiSsFw8nlXexl1piaFVJ9hqVm2z/n8/L7bZeP8Eg5g\nfg/rFVg1diwMbC+bfZDMm3b6EoCm4EpNQ1lIB3CLdHQgqSLBtG0BCuQkObNNiEDcgbGhBOj9wCPJ\nLcZcQnsJf1PBQd3I/fN9Xiyxa2kYhoLNe/oZb/XWV8+WiD4/1eNx+ttibr1nSYLevPAvnVbPFF2j\nLNOQ0QQziqfOPPlGdO1RyUr7wbXr8B6E1nNMCx4IXRQDyAxjtRAUcp3n/03FNvveZtp+jeI9TdHI\noNvvEPV6jKjPEwbOCccfl6W7rnJjaHPgY8Rj0VJZgG7lwBufCR2twNMKm1xOdpaPIug3HBSzU+g/\ne++pP+GmqEu07sCchj01YNczT8ERB3uIgkmx8wGW25VtCiuNkgpN+orPDbf6/YmHbUvdUk8xORf8\n3rdUsPqaX1sfcpKimPUC2ZDzk+lqO2OCG61nivL3qZiEhvMxWOdikAtk/Ccyko99hjCMfECi0mFV\nGmFkm998w5fKOUjZ/Qv+G+aOXKtAaPlNHOR/A2b7p1cUWoOCEiK44qrfPk1h9jQ+7x74P09vxmZs\nZwYoC0OY5tmZ78beG1NG0AqbCQtcLySXpa4zZMvUnDIw8C4VkC7k5CN4Gzook+aoSdKOf2HEOO08\n5j57GIz0YdhDcRneH019DgH27to7fIwvC7tN+LBLuD4G3gjSZ6o0Fqrj0XiTtryb33neg4CII85h\nrj1c7DadE3YWQ3nBDC1OPrZVaGHQtg49Yb3OugLcP37HNunYAP4hIvtVy4kJ7/vbCTBxRzD/Trhb\nnZBxYYzEv9UjrSNU6Nc51ch5WeH2uoUHimuHd5/3BvaWeUiHKEJJl9QMdIjWt05k/e/C2uS1P2/0\nvz/MBP/tAcLQ/51akOn9Aj0HoJRFX8PYbMA26pXqmxeUGbTCFf7BXeRNZ3fWw5sMmSRUVpLBMp/J\nMKAD5FDb0+kNNtk/ooaUsg4Y5knddZjxNzimUB7U36/535x+v1wATvJjbJcIP72z046fdD3cQPIz\nIWegMZreCGp6nCBoejnKvxnlcn9uKiD+grRUbL4kFgbIcXbKx/WR8zzm1GQAV+/RNxFHas1NWhp/\nfB3SQ0F1uUgjpIXMF9ax0UZclYKk93T7q791tm0Ck1fFYDmvtp+v3NENgBtbn26StOtJXQJzTA6u\nZb1WlHXidJRUnvEzteziLetjHvK2uoOyRdnnbVQaG07WaRxrtnz0DjId9KhIX52FFuvFFL1nIFbI\nNcc10ubRUWzZohtRCVMTRB3tSQwpDirj6oc8czAzr5wgy16OQ6VSGIyndB0KFNbwEvVFZXZXlWre\n0S94zds15TGWWte2DoIioPiXXqU+t8ZZ1BPV8uGfBr0B/7GT9hLGlbYSyLuAuPJEIOIcoUkXc1rA\n0Oydf1t4r20cW1jayhuDCAqD47jnDJ5iB8WVGIF74OniqXveRFyzjNFzT96RscVLBZynV4FDEqit\ng1G9F00nOMQm10YOdt1uBviIRz4YCKh9RffIYjY8xvNnhgILckpMR+fTu9/rO7/11AbSs8d6jKCp\nJ3olfpa7NuOQNCYJ9yZhqUmj0L8kHRKZAOwxuso7rCQhSmcN4loOCkFdwmfXQ5Rk2owhozfCqtqv\neT+gtMKxdTYzucBlJfMywNBrn9oAL3mgeqbJ6RTwrrrp5T3TRak4rSaOuTfuz1l4Pzp7oxhBR6Eg\nTa5jKEGIBdjUNuYZDT67O7DLT/EIXTaFpIVKKjRlGG++IV8r90VEIy0z/7die2v+/9oNvAxTQrKP\neq2sWXoaNoptxfX9tX+SzjT4Vqv8MdSbihYxd10nsr2wHNIvPQAyI6+yd+sqMay62ll2yhqPfPp3\nV52uyH7vx+l+xHtSrvqlOORjbw8+fwhviYgol3UQ1SK3v1y9cf9WHcP4WhCYxbAHLXajZbVdeNT3\nHVFcG0l9T0XjtoLyvbj1Zz0Ga9SyQMMBis3lNQnIHBncLmr5jikO7v63IHOmuZGjeBvynpadA4o1\nvi8QOmKviWmkD2QnKGW0zddogHqiKGpK3WTtgZp1IkEGGXh55c/McqcIV6EN4wMQIbo2bup57T+v\nJNFRhO3xf12w6qRv+Xw93cfFMxmBS2nFtC3vf+u6dsxxvZ+0ug+yTKWzr5dKUPFzWvWEp464Hfgl\nPct4QgH+uAEzHv0CXheYX/aa/IfL/trJHFr3xxqrii6W192d5shTNsOvrzWdHHkkWldvjVhhkGTV\noKvcLW9qV5TVfZpG+rYk9ceEXfXiBuOQeXkZtiqqi+KCmgg0oY30867tDN9aFkloqWOGf+L+M/g6\n4ofAkf8WuigH8UclnvXSWFA8RRFgFM6/ZjbyqJBexAykAGxEYkBXohcWLazbXtlWP7FYvm0nAB8u\n9VxujQwya+httrYr0I5La11/b7sqZndhkJnv562toTV6EK2F0OcQOz2DDK+ZKScI5ikKxHXOfl4o\nPHqHM2Sd+QpEJ2xo4d8Bp2ICi4WEmv+y5DFQq9HXjSWda100EGSCwmULI+yeer7f/ODkAURKrZFM\namuAFfxemdKP5Anxv3dmy38xJMLFj+v/L/rXMLRYMqqmlQDlLxqjprL/qPowSXNwvz1o3hA4Z/p2\n1p+VGVTim1dUClT4b5xIYhiB2NQU6kMKfDOGzE51K206SGhErMWQNPp1jaL/Q0QyQFCBOlpIgLCg\nsE+bhpaoyM++4a2de1YOTkrvpTjjzG7QBkGEMgB+BDbHv/nDUEjPXXWav9aPTo5PU9FTbN0+iaPx\nPKXzkWSDemwopPI30qw11hQy3UiTbixi7/79hmmj/HoIojuUGoQD0FGlRTZPBk4RCxHD+TspVcLH\na+lOaPAnBz9XGziIZ2MkQDol/qlxBrO8BpUZSk1QuChWgpEnyUyMZ+BHcah7m69ZcSewCybsZx2w\nwm6kAtQ7IJ3s7yDDEbGrDgqdJMzAtfyiDpvEuOArQFr0xiJqOj8q5M5J0gxMYWdFqS+MCKStl26A\nbDQ30c1XvH7hXf46pquNFVtzUihqZF+OuPkXsNFSrsG/swcj0/uVncHnBzotWtjhjMlNW3oueFXI\nHyKsb/6YrUFtNvdHMwAZnM0tMbQLO0flKpXd0WhcHut006PjsE69nKlR6huwCW/OHJxo9n4EwTIf\nSPEWWAxojDW+R1sElasGYn9ZFtByApZ/3+AF9CS92g91TzrxfTaoVBjhbsXNG9hFlghaqRv68WH2\n98wXtwSpFeYQP/wsYUYmWrkli7vZ7j2r4W1gbpX00ME3nsCuqDtkyWCrZ0Gbk1NJaBcz73sBMGfx\nMyEzSLR1l2X0m48PtK3/ON8PKcAeiJLeYe2hi0Xq29dFkpzyw8Myf9NZgKNxdaY05RHMepUq15az\nbv7PmJqCI/O/hmFfWJCh/9m0UCNdzgvg+t5c6A+qrY7xR6bcuBul+In8h84nOKrpkH9qS/vX3IsO\nAZUJZdAo+uduGOO5D7GlwEtaUaPEvwuLLCb0rnr2fvpMszk2rovYyl74l4pzDB5HHgwsoSAbZlKs\ntIuBOJG/RexqPORty9+xT+FVaFFvjoE2e3HDsfncFomOlE0e0eslxfkA3aEciYQd4ev8XHUSN99r\nMrzXQ5pzXYtiX7yoW7IWEYQlhiTYlQ/zwBxsaw0ACQ7CuHjYZW4Zqe889gPOg1mPOmiu40gxTmvD\n1u6+xj6fCqqI2rwgoO0uLeQzR2STGYRufz1FrZOp/NmyE7PyZH5sMnOM5EliPC/4b20PqYIya52D\niCS+Y9Y6F7tYiFrkRCmvqzCt8awINuS+lsz62NgVEcAWnb+cUdee9EtWnE1gqjp3Ii5/nudxDBZS\nW0eIyMzFanLrizrdJrPmkcr8LSNBUXJOgXqJMbshJ+yvRUncf28pnDJpWO3+2pa/vkV/E6R/1qiu\npgjJP5vViWWOYI9A4G8CqnwGXRJsn5ApLiRJesSEkCs8IaNGFBykKeUXgHbhK1eC5qUbRH1O2YR5\n0uAVcY7gTDld1gn3c54nuGFDVy7CH/e9ZP0pHMYlIlGH5MuD2ZfNynkiy1zzbC8LnERyEJNwlsh8\nRLcl76TkzGVLzCEZysHWGxr6BEFsMca6x7ifKXCxPM9LI+CRWxBVtUED3Aw2dYTEqCsVG+02Z+8D\n85k0Ap2dTBQGRSor9jNzBxCE9psIiZQAu0QD1JqZuqz2Iu9dLwy/yE57e9Fpx8NdAVkp8tM6WYFF\nARE895oW70jJ95tA6y6qedRqI5QYv/xlfTGDQB9CpNUIz9STkG+BDTBmpb+S3CBLY/RtE6OYv/0a\nXiAxiiAkGqEC82+/gFnTXY+npCvK8nLqJlcnt0PG1Dcqxm6ND7KeYO2t8tr7nYEbUNQX90h/k3c2\nq1lzTtSkmenZLauwEvZimLC59hSCHzNCAM/dLva7FiGHbCU4g/UgFSnSidS0OzoxmDFZyiCixO7k\ntXiHq0Lpa5y1QkKfLMeuh6xHijEux69gzz60zvSlOGbWYQe4QrIjyFTRdmwPYnIyU8Oe4fWVBvIp\n8vcVDMSqULuzZuHe3RKphFqR+ttmSczIBuqnGE33vaUHT2x59nCYRlMn3QtqkOkS5q6wmYSTE9Wm\n6zdpmcaNnHjkBurzqGUeyZp36JqJlpBryycBMWAyZei9lX/+rigGqb47epuyTKc64RRX4f/8wgV9\nOaNxVkh/aAggvMdW+K0po1kSIcnvDOPGHfoXHiNXCoHE9j9NOhNYVdyO/ZY3wbZCE/EhisCYAxjN\ns6PXLwsn191R+irNNV1z0WiJTXSeIGoZx18IYLZPuLh8luXIWjEJz2XWcpeHFkn0Ap/waOsN7dYm\nY4PbOvFPFG6mlBYS0krs+5gz0AjAYDds/BYsUp9tSy1KVlVX1he6T0EsJkbf+JJE0DQj9yJd5iWz\nnxTzZYGnQ1kaj3n0ip7ecp0UQmSc8DEi4TwLGsXfd+WnBeZ6c3MzkfDF9DHUoIUuV5HAxQvK2OJ7\nqoaVkq8QkCMF0w8b6oL+a3Fjz7D0G5GCSA5HDwSOVGMUUtg30bMvB/JhIZrVDXTMALOVYybIU5wq\n2pIOeZ2Ih2j1DTzNWWWUBUZyoghXLXHW6UnPc1XVzB7X8dJdvy1FGT+pH8x88AQBTdlVbUCXE4EP\ni1Us8krNUum+o7mTCgc1ea+9jt2TXTCMOsRTocOf3dmmreXkE6E+2GfauYbvxNjZi08AX8ZrzF+a\nqK15h7bkwCpUDCPBYHiIffb3b42Jdebhl4uAKmvxFo0ZL/OS9ZHjP1mURtKPunK3GBeuKsY4VmEa\nKbE6FkGkDCE9gBZC1PxLIcSar/NDGe+63TYW1unEfJE5pyBPJdPWmIb2FGD+s9JdnZCdXvlMVFbQ\n1zjaWRjuPvvC7FnhtHz8PKX+hClD83vOPRkeR+W3nZKrbmXMJ2OoAXQxwjBucDujkyTFgnMXzJjE\nfcnGCU7e6ntQ2JRFR/VQbhG+OYvxUBfJ4TPPClaDh6Bz8jd8qFeXIiJGpUlm9UVZ4K8cTJuNXKN/\nK2SRNGF6W3Boyg7lzrZTB664Qj8c8g6kH2CvtMmHFnDezY5DRS/sEa31A6daKG28+TOpmMWd3CtJ\n6bLA/3e0Gx7nXZN3QKkGfk0d7P6Q1wAnKgD3wWWxu2CbBT+QYxJgcUwfRr583dT2sQJx7EAO8Xfd\n4OBjW0cuQKK3XKX4Axoo5gOfgqiQTA+0MCWsOzsxMmAiMg7M1snW7q+wiYLOzZKnbC09XBZmDA3k\nHz/h23l0poTkcEC0cxoBa4/ssq2RzB7MXnz3PLyYFOPSzs2l1p7jddekip3S6Erq5LTlmyYbLNDO\nUtsya8tZzvpM3nJr0fWKfresGKMn+gio8CVRtc2fxQ0PpYI6WJspDKk56fHtOepT3dnjSEignOG7\nERFS48js6nixaLRtx1hDlZyLDu++2z8kZ20FwC31Qh3OPw9pJBiAh9/yYlEhpfgVdGtFSRLmi0Dp\nrh0ZJBzEOMD0JAirrDT/7cd+osneKIhgj+n3tZ/ZSk3qSXKnYb/8KobKNCDwrArHGKLuclN6w3zz\nk59kyrbQMvoO3Nbc42JEAwz6Tnvi+HFp+B+TPOTsYSBl2Ett5L926l+vb3yTt9kWBFluep36HO51\nmHxHIcd6FrRr06lMToS4D6kaqnJt2j1EbVt+jdSK8dDf1AF5dJcXH650KI0hai6aQyoTIkMBNrhI\n/c0AqfPQCedRo3WsXr9rG4/jSqDkyV5wRLySW0BwB6iPtoLqQUgJGNMboapSG98gKYrSa33kxm4Z\n6HkO+K3xT+op6dIr6FfNdEndfEMGmwNsUyx4zrA0RA2vT8y7K9yN0ex489fd8zpxnObs/3Ga1xKH\nhsKJW1Lopmq2YuJ+6ZWcn9Dgh5BN9b55rn97Si7MqQhKj2rFja/g99TsvPMCvC8NBJEigQFaQyD2\naqCGe6BV8F8AtD8VUKlztHRDaSuNXpaoKYlQVvkhv2g/sIVu7JxXWzeTGVNRDiwWU2ZK/WainKwV\n4y3BQ+cAZBPHvrhnrFiApLa1UTsMgmmmoKbMd7RyZzTsrj3z+aDDLUG9nDjXTJ22Fhn/+k7FNAAW\nSLzhyOwcfPeQe2JVJWnL21whJwcRfU2yKUfRyGhEMyTmzcXxCTAPxpI2sp1Xrfm/0tbXX0ThQLk5\nehkkDs8efRYmvJqazMZVmC6gjSpEerYVh6ujNebuz7/W14h/2JtXQLvR4d1MyACayrV5RGPjILM1\nSA0q0CsS8GcRc6xl4jMsfCriiwJdXS/3AyvoY2/UILC1WrImY1YdYOUff7g489qGZBMdn1WgGmZS\nDKRRpHbsAecEpb40lUL07eYUlBqkzaJz/wv6wuiZpH7q2EZrd+r5BToCVHNGe6MxwdS/8vS+TBGW\n+8CjoNI61ODb2x+rt/94+olRvr7GVfxOpULYWy3iR+oBdAPK7Wg55n75A8i/Muv8ndv59Us1/TWu\nE045HeZ5WMbVrd1m3IH2yRm4KLoZnEl65v709sQWHgj0DN/OCcH2amv+KDdUQAZWyiK3UKezjhd5\nOqpf2rtBqLtSyGyjEk6I2v3lldGbMmuvoGTPPMOQSKOx9lDBr9m4ELZVODc31py5C4v2ybc6R/J7\n1BGKzQ6CC0cYOdZXTw+ij6bUOAezEMUuhtLDOnPx3xG4PdeQOPOE+/h5aYV/x1fYQl4biZbhfKao\n1nBunvNu8Ut5QZmb7sUZJlMif+P8KtA8LQsgdRLgWcLKcnGT/hJOrCs4qIhyl2EA5zvQ7piDCe+q\nfTjdh1E7GAQGMNn2/E/Jb4HALDTClPV5Pfb+b6WVc9r6+IjvxAgrDy8J3OB7OxjjfwXa9hiGXk98\nx5s6SdvBZzIW8koUQAjUGcH2GeLc66H5WI3kJ8FUGvP225z5rhTRCr2RscH+mHNi4kMlnyNUjCAi\nIIiv/JxrMNr5RO3eHqUwSXrZ4I1ZpC1FLyjA6AeuQpaZpTiB2ieH2ZHDl+91Yd/4AQc4YX/3i/xI\nP9+EDmGAIIhJwWCQSs2ZeiSFwa/iRzGh1v3nfyMAC7186eIQusBdpILzOMLuAcwe2nC4DNYWS7Fq\nHZaX3924aw6A/ycocgytiYCcWmN14gEZl65oz7UzGwcCIiyQJyIWSLvYqr954oiDbmvoHRwAFOeP\nZpk3KYDqZF83pr4s2I/CqNOl63ichdNTQYJd+HEWJXsv/+f0p1UErNzsqQdc4GCoaNgrCBRwbjUd\nwq5hRGeYa8xE4tIm7BUHgZVPVd9H5qklXJgXv0LcnbnAJtvxOKyQFju+hmujksl7LCRehXDTP6kU\naetcaZ1vDWG2b5EnrsALT7YUy14mI1ub+jxqF5uuSyDKvXx0Za5lyomLfOiZktJ7JHWn9jFZPCA7\n/K4GgSFq36lUkfX+kotiUEzC16UTZXyP2ib4cL1Vd0LGANGdTWZGj6Soy6N82P0IirJy0qdtjlHA\ngWkj1beCsnBd2JHDlx4xDeBHmy5B/9I1yIcIyKrnkP6T43O+O+2gvEHyn2glg3bjM2i6EPpKVWJ/\n8X8E5vBW7YfsLCkU2ewIZYNAcX37yjOCgAlSX3n4VUo7rymZWxRodfVSWJEG3Il7NjNHrkV24GfZ\nUO6bY1d/VKVnL9ic3d3792JI85nqXDj//+Z9tb2KN4J2iyvK22BoJgEURQJ8qg6rwuv758jKjCHw\nh3JrAemH0knoqtUwkNDfrdTCJRD4k2rYTNFkVTdDWyY75vxUJQ06jNf886rCpEp2dYjbSTVT+1OC\nhGDC0v8XGKgbeZXiQ33IN2QRN9IwO1r+f5Qe0bG0aUPlYB1SU1LZVDiAd52ZytE/poiIxTbu7/fS\nacWqOGc9OEfE3FVmjkoh+19uTyvaudcaJy+RnqBTmh/vImBwAA4ABXz4o6Z0RZ77OAZ9bkVFA7Eh\nEGGBtPMscsb2hTVkomYILlssIv9SnV7R6bQcTQAVx4PHRlSahgmRF89lCvAt15aIj1GYGuNhTief\nyPf3JloN11hhN+p7i+7U3BGAcdaE1JWHAL0wjLCweyspLciMC82soZhVIGjinMkFNPMitMazbKii\nXGcvLowfK3d2h47GW8Y7nvDC6+N73trzkunY9nAfHorApS3sqoMtKqSAi3zM8D11BEiG3V2SuWRI\nQOiTLKfodPtC+R7adU93EhypU4cKxq+MGQ/Lu8tRZnPo3unFBT/iGDzM5JrHZbalHuGgkVqShiwS\nmwDUxBcomoVkodtXDyK6WvlO2WR0C8WaFLvaf45mJcPEzs7PLX+C0ear8t7hOrbIrV4PLN2sCfI+\nuMzICq6uSXC19gYUfHw+kiCfNZ43KPPJdcVuiLVEAHL0nOCZ0TLuSXzt6hmWyAJifW9vRyD0z7Ee\nR7UMZMfma433PmgyfkaBV5JNHbfjAmntHyB8wXRLLBe/9xk6Gpwdrwd1XnGmsqKY3/xwGDXVOfXw\nQpJrD82zyQhk2+/esvh7iKox+pySAdEST/kE9Fk0dJrbeONg3XxR8RW0FnZp3Hu7q9TJSEFD7Mi8\nK3xn8JXpXwSSvEKNOUX4kDNeUy4f3uLAg8Uiwp5jHLRbOp3iWg9T89EwDpMBfyIDHJSIzlqvAr1V\nR7G7S9qZYB+0UsY5I2Ry4bwNS/QoDNvQxhl6edlKAZIKXTnaBQtV7wgDpumCeUubswgEznqMUsCh\ncvwE+nCGOqVHvHEmAiMgaauMglgJoAIuCLB2hzNHoGCB2YtiyJbxjyucWpLgJIQV1HxlYLzkJjwr\nfjZqURwU/OBgRIzMB2+lcW5U6QrR4vgLQrNUJ/QlMvDaaRFTSdWYw1uR95HaHR8Lk3PlKKJ+LiTX\ne4Xipb+98ksqqqJLZl1ePo+ipy0QEo5ByX3bIkSctN6LMyo7Pwrl4rLalK/m7hyAfx1GIjSbZKPw\n2gdVeC3PLF6qy5DgW9C0grWYyyjTvH4SQynGP4C0DqAjqgq0AF/2UhVZ+FaKk32R6gE8nl4pzf3Z\nIP/bQIthPQSrC+j29eptQXIrLzOtqjYmxl+g2d9s68CixeJ+rfYkGGMYTbIUcid+Cqw8wIF6YZL6\nnlOigweW38eyeRgquHQ1N+9tzvzR6DGlb4dCKUfjftrcUBSz8npgJnCiS11PfKHo05kRaNKf+Uu3\nLapCnHsKWRe9mljjjEVa1LzuqH3pVfUmFAX7fMswjU0wRJlwoIsqlZ+HRwIpyqc2muAe6xa85mSZ\nCGqcSYhBEGqMzcXZ8QD3SvbfyBjMD217ze1Q9XygllYLgMXFGrf+u0U8K+482r6Yryv/evISC5L+\nQZUCPhpAa+G4XlF7Y8PMPZ6id5a9+AUYdVV1Q3Uo3QfDRTD3Rz+N4BSO9PxTHAF5s5ksbQcNovMt\nG/tT0gghOKeOEuPodmObJNVcCJrcJx5AXQL6thuCBIeNPf0y0isjHwxpdbuecj8twS2uAySO0hfE\nhIcwbKn/ujO10Sp6Aw0AB2OdQQCZaKWrQwBkrvxO4xlGvawjW06nnBA50wJU0FAMjo1WEO4prr6L\nTTgzneCZPvGtI3oFp26mO9NpMUVm5janjuyntP6LZpdSHNEICV8MEWf93tSSpFL8KDmU/O2OzEb9\nsNeLX7tgFvEX66gVIetuov7yQ/wgCpff7m1qcL0YGarGbURYMAyamHsPiArS76tOUtLrPZDk0lCt\n/8C31dJeIhVN7TzvYc4kw/wTAetUlD88yDym/Sy85WwTPVOioGB3EMm3Ea7G9jRsHlr+NMgpdseH\nnImn28Tz2qE3+oCmhqWF7YJk32pLeTax4gj/ejUO4SNT36nfq9enLyvz9+i35thH89DnevapJX4e\n2cVpfsTSMCI/9p8VvsmYHkytEHH5g0bi4soOnYwINrdmcRl0kfAJ3B9OCOq67P6ze6zoCyY8m9tE\newrqtywSoXE5IXoouY/7MK6hN3tXttp+cSoKpPCxlSU79wPpvwOhi1gcIeIcuIRtt3Pv5LxtkOfB\n/tl8a0iwfqpOHvwCQxuQS3uXCQ7Wyig+XFdTtBUNULwUgxCAjeUSfQ9uA7sQbfBfwFfActODl9Sa\n4J9v+8MOMafmyS755vgC8FHNp5RYKwhn89HhXtYTnFXcQATyUQGdzkAzMn2GIFKr9utp+Va9T0pT\nuZZc5yNb4ZPGdBe4U5YmpA5SvJ9hvmTJK+P6Eu38TP03My6YNuSyOFY+j7JkRqjF77BJLMks3RuG\n5J6gt4em6DUj1M8bn6wT+MiGresB81wAcrIAHAzJ5Dx3X79jSVGB/UJMN0/Ceo04m8WkcgepS5UU\njmYrIfwjs5oO/if4TVKf8mkXTCtE041zSb5D2jX8yLFp/cNRkPwgt/eK2eDXO4OTy5tG6t09loEd\nIQE5bas4DecbQW5fa6BEfSQXmaLhOKO17pMb9mtJvod40kw55Af80vbtv9NwSDhsOtX2bc7aCJ0O\nkM7aZNpvBWD9SThU9UvhVDZeQ2V4sowclMh3dadyIZULr3uTs9RF437OX9grWjLGR1VRys8bA1sk\n1ZUk02S+TqoEaC06Tqn9M7bZ94zkg3Y18zERz1P0kXXVlNrX4266Fa/boznv2kaXuANKxh3jZ2rI\n63ejnauAUcv33BpuwjTt+uyJXVGxoYVv7VfGhOVfUUj3r7hdiDZprGlN4HQDwzbJCc4PtXOh12ne\nPbG2K/7LGVSP9wYTNldnQpkSRkOXZFfWjKMTiR8XU8gLc7hkTfpuFhy62AMhGhUnpbaLKR/CATnM\nVYPy51Q1N/u4HeWdX8ECIfLn634lVy2W+O7r5A6xv0EqP5TUa0G4JJNf3aK5dsuU83JtmHnvccRw\naKotK7jDIBm/rAsutsSmsx/VUf/XG2UhN5g7yF283L/eb03AKmkTkWJGB3tDAfe/4gBmb2TQOs1k\ncRZOqB10CCCiqdH+Kj+Us2nEMEfaTNHcI6f09LPNE+LxfQO+GWlMqNqdAPlp3Nm6x3OqDZN6iKn3\nVuFcPqNCvfkow4kGKQfkudY8uV7XvMTQMPOZHgm2/nCNKgMQ3IcYtURMBPfV9WKCnv1t3v63brPW\n8hfG33NYrVhPsHa2VpMHCegvPQ8UNm4sMZT2031TAwqylHgDm6b92BdSFVlC3NPH0PZNbyfhFvOZ\nYRqr2h6QfM6OkjngX7t6clqCvhu4JXNk6eLrtsLsd1h9AKDn58ly4enw0g2mAC34JGn8pScrQNkK\nbOjf9mhX0mgRBDFd49zbX8GaMUsiqLT3xcguZpkoJlP8W4bjnzer+NmPZWLKUM0fH268OgsmWsBZ\nOAWUKO+pSjkww7+o57J+zVJMXcEwBC0+cH74Nr7xxwfD9OZ1rMtCYTSvMFsZ2A4q4gXwBYiHB8QL\nZcDoHHwRaCf3VzvhsW59puF40zfIM4q3rx1tsNOysxKBfbhWR8iwCJtSt/8+aiXnc5FJFDPFyWnV\nUM9vS/nHB63gFFRZ3NjmWolOUxCnkpnts98595wwNHn2hRPISxmdvxYi9Pk88VRLgWZei0QDx78Y\nV9onlshnGZDl/1CRVQThZ9Y9p28I6dCCOGXG3qTAleTuPQ5tMTjLAABAXVOyHXr/uUS0fSMvUTf0\nlZwBEOW47zZZGi2hSw6rh/F08vVGx6ZuRH4ohEihTrZaSuJWG+X0Xg7FScc27CJI9WLMd1yKD0gw\niW4YHfdyOfym1+OUFlhHQUp1l7zitnrXmanDphZR3aeFd4alWZfasQkaFqgh0wJNKUu/j95RkklR\nE52854dD3WmfJqfneZhXn26/OO1qCi79mkxfSrPnar3n/PbUd+a8Dqa4kF0Y5ZvMvMHyJ4oBSgaf\nHxFy1/qSQ/pdSdzlTva0ucTPkJ8viJZNu7/76dePd9qIeYNngSk48Eh8374pSx2ohteeLqyXsOFS\n9NOTJvtra++ecRX2LWW9aGFIrtZhbv0tZuMMyWvOBdGWOsfriyP8GG5aOSJcUAKoImcKE9k/86N9\nWUNuSzqmUyAjemWXiZ5DzpuewEQtmfZXFh+esID3mcTL+sTfEt7nRDHop1fr89O8HIBoeWzZxnba\nZlqftjt8n0BBX9pA0S41CuufgJXjGOw48YeGq6WsjvH+IrMiGERKziSgNAM+uQzeLtZK9NFBhRHK\nNixOyFv9mYyjDZ+cd7TMSLaUqUoC14u26jngb0JDpctTcCoSvszjhTQORlHDHifXRP0fyv8jb6y1\nt7vwth+4oNgZmHcZD7hBjt/M4c5Bog/xjd/abGCQF3IZrlhJYY06bXtEcIXNKYbZo/Fe/Pg14Pp6\n21sDnlmjjUr78ZGs59d7SYNNxNdJ1tel9vQ0Tt6kmeFpg8aIh4KsqhhITOoNGXHHhapwCiiUmqV3\nM4BCetdWm9dAfT7V6b+Rh/GysyguxD4O1nzj6TU3LgYk/4nIBM240spxMj4LCvhpmc79nE4s2na7\nOQWWPR+vU9tm6LHLCxcxTqAWPNmLL7j2RUFfCxB5Xz3lnpf3Y9/HiC9cNpoGVrRfpt32EiKEjrvv\nAj6HBq0repJxfPHJTDcAExIgAFJO0eUX7vBp3cuDb7poHyWBIYJ2EffSNdQyZEfHWMkipBVRlZ36\nDAqxVnS4k4n3XScu46ZUFg/CKrAwtcMg7pzaSJRpt9IT0yNKbVqJafaRjpUyy2wUqRGKl/EfRDsm\nruQI3nXCW8h5jY+j/lmh0/JCn62raoX0+9DrCUUgr5NlNjua0mRrFHFOh17oZRDM4kJ/twyY+aPj\nC/xsXnhJ4nwthgMMeox+K7AJNG6IimcT6nDpGVw9eermUCPu7X27IOAV9oJqoMwdbGh/GSpVzfXU\nwAHfFsmLIX0SPEpNuCL8ApRT8JfWM0iU7uPnHCqyohXnLAD6d6lSao2rtZ3ZAmHv4HA1NUjZfns4\nN7Z65kDxOrdR/U5gKtGz4lPe9E9zmXXFVq3NyOpLYZWXyVKacLUKpLxT27/ObBz/noMb9LaCYjFh\nOSwFDyV1oy/n/CosEJdF4OzGvqfWQOMwcq+zHyC5G3GRhzRUn7OnqBK4XdXzduOagRakuU+TklEe\ntZm/z5poVxsvhaPT8l7Iu24yJa2ZtW2fT1TFbEdtFx1Hcp6BqJOq5b5/ithO8rRmWHYcTTlhF6G8\nwUido2D9AuzCgKJz1dgywn6pM1F2AP5w3Xf2Aj3SzPZEYM2fYr2JvJ9TPMZMAWeAqqQg2NNknjof\n7n4x552ZzUduqKVhOPz+ReDD7AjcE33290TR+XctqYeIXo3j211BoDVLiBKsx4l52Hwqk36O/7aD\nwijmWwh3U33NlcnjMseaRQZqT4O8za+qTDyG/FXwYM08UlnK8Me3oaFuQMi4rj07LJO4mlx+xOCg\nfWsV+760Z2Rol/6/ISKFcZk1Oe99AbkZGCpYtaymXd+bPADziAOtTmqbz12Ma5jDxsFQEGFVcyHO\nDLl2rmUVmLRnTlksr/AEwsTLLsnuPJKv57ih3XsKmNR9xXJ58rAzZBgTI3JcDTRYufAHSz6FVb5e\n/6yONnJP5ebIt2FbDUaN4c6fNAq+msLjv02NSI+d814N8BLerjv2yEzxKyNWtUOPfjqngej9B10q\n57pd+zR3WCPeb/vjNFfXA5+F6cbGl3VZOn/JhE0O7taJNO+u1lrOQ+aNRH24LOs+iQZD8osr6ICM\n7Nuh+9aOriVXwt7DgjCwoUr1rNSrhu6KMm5Dt3C8g4e0Uj6Nn95Boo4x7jb+M70RroMDWYWoWfDm\nIrhFsoaBwJdRv56fYbF4NANQ6GM4nD3+lpe3gDBzmuCzzlf3UWhO3Q6siP8HfD50jM9QGlbldcNJ\nM4zA+VscY4rl/cKnKPXVSXCmjyzsonc6TKMN63/6fE2NiHArBt6ezijc/q00nk/QLFJzwcr6C7qa\neeFhyzYZN2QNaf+bu+ksAoU+JBEfl+hmWmvc6l3SX09YmnTLhdMuRtZ7s1jNJi9MDIFiOMjO5I1Y\nPLsn+TxfFnVbk767xzw0iRVFak1ilyZt4PnIJ/8r/P+6Cs2nSnHrhzzcH9UmL2ZN91auJQ2kolyJ\n1lFSg1PZBVmp9Ws2/pxEZ7nn64plJGdEg989AlZEyskMBd6gDNwHhXpYDkU0QKj37UPA4PEGdLR9\nJBPdtrGrvoxQGVqsW5O7r5C1wXVMNM1ZhS3UU5kvg2kH6j/OcD7WAxc/qSPtLde/mxJmpA2GM0er\nVcDXrr3bXXm8V8e6ShmMuwPjG77qPnSZmMG2ozuCAHN7JiE386euznIDr2p1zWxP+Vnt+zgDgRiO\nUWQ3rI8PvWbM6lzE83OcJrZBaa0vl/m8Uey2kjeFePxrT6gtzwgZG7loFCG1Eo5DsqRbeozt9lz6\n/qO+/o3FJvYtUuNPdayRlcJ1nuE/gwnetqeGvfFesuvfUJZz00ZFeZHnCbvgwTShhp/pW1DfeGsR\nDplVnrRTN5IsiUr28erKyO76VYEimgKPpBBIGw1hgtDn2+6B7GNdCZQECg2lq4+u3Qv/4M8zg4fj\n3K9DuwuCcNchuLHNPxdgaeLKNLFQuqVvFn7kthuLsqEykk2qUC0tWue+M68eYX6w5SIbvmf79xka\nSrN/wwm5d7r1iHKoc9AaYcu1pVyXqAj+h1pEwgiylWKKrSjPxGZArsYCljwak9mB9+OSnom1jGT4\nfWI2bovZAUusWoRx65R/PsR8qrsnuVaECemQLqnSxS2Bk+cqhFJXttPKIO01aJJfN+HM/e+7xVq2\nPZYbwj4LlmIIttSCagKbDWKqAMsfrHrh/AAH/540mhdsip20xdOs0p6nPi/aY7OmQvqVNiPATKG4\nbSNCTgDR2zkyEtsxchzjo0748+OzYm3WK7ky2TFpDEfv6Foaqx4YXUlSPM7wl6I+jFD6KRl0RLHU\n1ZkP6ClYuhPHxX3styuDCOGSao9eHCduG3PpAEbwLrFo5+zJo1j8C7jGQu+zHJsPcW+V31WKHA/D\nuqKOWNOMwWseEd6LHBKuNoy9u/dk5XYfZzN36RKLyTJKriRie+MnrsQTHiUvXTEnFb1rKEXxds/B\nlViG2nNsdLnqT2/LdCsUIYolztxm599EFd+R68XK+CST4oOYttBNgq5OOTvYyBUXcondPTirpPi+\nJupaAktjmcUC/tMTybBu0nbqJPYX9+qnlMuYMB2Gv7RYrL1Di76BI+V0qeWkpR47OaPh6imuHadH\nhmHQSZPlbxya56k4kxlbUzi3AsVAmdbJ/TfI5OkIAbYN+lrpzhlpdOYKnE0oRajBwiqY9N8BsUVw\nq/FL9tShYLDqnHgVNdDOG2aTlzELBIX1esT5Q2Aro9VRUfezgxiNkGbOd+Ggaiqm3t159BhIwTzE\nAtuib/PDjFZspqweFD21go8z2RZC7JFH9gnvQdaYJt6lF2G8+5LfogABjh3gFWKqhxATUi3ZWyoI\ntJwnbHRn33D3LWDPItLFX5ihyB/63AKorp2rk4ZEp0kSJ7H9NV4E5Ya3GalnKeGKQHxioNnJSSfe\n4iUULytCxDKBVjpaVwQvVkSE/fVGo1KirFYjFc01cz31npEaNSkj9z4FU9XnngVr5Xgjx8zcHfYx\nz+7eNn/zkHhq0WVHeDoLv4finStswl+UhLH7K3g0nJnifBck9wk8S/gQQ5j2enI2MeHAln7qhyrh\nQFChbMTejaG05GqV9fPVL7tL7plwECAsxutFCC/gkn1teo6F3z8pu02Q9Bl/258xSA1u3JOkS8G0\ncqAcmqy/tZqO7BnXsJBimI+UbkdQOupqjaV8pXywJPn8b+9VtfZpVatG3HaBpy1IBk+VdkAxfPVy\nXe6MYkXYBsaab5CQJRf65Sisnn4PoustKJWXj673MHw7UVUqmzHcpk/GRJ/0NEms3qHsBvx9PYnA\nyalsZjGlkTlUdpV/WzhDx/8fTgAzNxyJWIkSqTDsl1dcuxGpuyFgq8zIaqSi4DPBw+iAwBd71Za6\nJrmxBu/SPwQVhZir/LwrSDuQMUuhMAaTi741mozlTUvZAWbIINCX7bGQG3cvCzwTHQmHWPC9sFHB\nj7ehCwz3iZk6IdegD8yWjMxtWKVBsPYb+PWsnQ3weUsc0satRcnk2vcq4xDCWsTyHROXIuU7H6SD\ndfTD2yxw2MLIOJTdAGl+cZJjNYv0vylQQfA5u5UxXeobjxQWS0pfc5Z9rwvCkyYB8j9jS6aK8ha9\nUupZtl0kuA8dVjiU1+StvA5SfNRp93p2KOnGb3u9G+Nepp9IT5E68sjf4SZXni3HDIltQ90MVrb8\nZinB4wNMQBKtaPRvF5smTbocApyvO6yuyudyxzCKe5ckSRIcAxKDxdHW5svdr1dApgAVyXZ0F8Zx\nIarlATMMHI5BFo0u7E3bVFIj4Amfl62NLqmVEBq/3a20lyoHCfAnYSmIRYdXqpmKkNCMRbZcM14N\nFwDVbfYGJ2TMdtsd4eNZS567uxSRGB0xgjK0320539oHqKZGrrmCfEVssPYxEkUEqwiOVC2h7zvW\nDnHlVaQd8mP2RM5nWt0C/AINHmsbYI4wnn+/Vk2H8LRlToF3nZmRK3mBWph8HviCe1Dc14s1ZCR+\nCnLnNcI94fnHZonb39lYi+qLDQf0YXzei3LQ6MS4yFR6HaMwagx3JocY4jF0Uv6msVWiUfWsy/TL\nAdLJpkF2KaU0BJ7+7BidxBNeWWjlsvn9pqb/3BrK4XEC8/jAG1ymACJWcQOK9WQGCvzgW+sCOSQ/\nMkb8xtcIvEHN/Dtr1lZXlsZ83L4vZICGcVEmbmp52Ahw8gKJWJlPrMNdocksJZt1021zSzxs2jYJ\nw6CfzZVXg7QKDPopi1A05s8fJJnm6Rs93E7/VW7wNGUkg3C5pPVjuHlA6pWVKrQg952/1LZQOpYp\nuQnlCm8VYiJWhpRRpYGiPYZ6rVL6fGTorFmZVuFr7O3WnyrNEcnEIt8XG7ztSEWt3h8uNWlmttpG\n+qJ4liaOLbhbMboeZw+TtrlYm6NTq2jeneXbU17FFaoEx06jeuR5DqsL2zhh9P6kyoeloqeQNrkr\nj36ZuxHSsSlbAxy8B5+00LBKJ1WpEbp69g+HN9Sau5P7fTxKDtz+vBMyY2NSuqWgAqaXVEMhVH2g\nc4+u/FZg1HHji5cMYk2MIUWytu7K72gwb0QUQtnaiiJpl616pUKi/RT132yuc6R5jbLVO0Y9BFU0\n66ru+VkvulEf+oxaGBRN9tIV/oLP6tJAhPZ/iGlSl/lt0JQFI4G1oi4fzqjKKR8oAnRk12JH3HtP\nEP0338HNFVM2oPu1zw32zdrCxna1rvJwBBtVN8LVAnxOuZJ6kUFw3//Oq+JJev6V+j9L+Ii3rB+O\nGx57F35T8Pz1QG3rz3jf95D3PPo6MzJTDBt4ljvWrOvbM+8InC9vYy09vFn9Htpn4ZeA2wbGOhvN\nPVPJUs+5WygbB07B+quRVcDXDebrNEPBzsC+Wp4OyONgtMu7PwITFahmmt1DDf6MaKqQ05kFHlbt\n1U5nSm9oVRW6wPRd9NhVYY+GzZwYb7oYieHXTBi771KGYMrX5idKaGGdVekbn7jmHx9p3RvVYaJl\n8E1AGtJsMKUU6ZCEQzmtVBSFnE7MSR3wM6ns3S1liylG0hnEJOmi8wtk1jg6yeO2NaD1yJjQp2+C\nIZjvyLRWKvCONVSXZzM0BWdAk9cyMUu6iCL/u+xL6MYXwWUdV7HZ92H+7rX8XkNj+qmeXlOMy1kB\n82ClwtsT2HfXfQ8nVFK260Lh5q8//DjNEb3jVlW/Dr5U9RYtn2Z26xu+OvKDRq3nu+Dg4TCdLYvP\n0YgID9lEsHldodV9BX4MfBSdyH6ztU7RysPPNaEQtRqiNjS5TDidfqewqRbTAc3VwyJOhkqjWgWI\n3+r15bvWCpq0usvFEKiwURvTM2V+5s5/pVjJEeiCNB2QpPIqacGBG3ovU5nXfmF2N5r1Tz4giddI\nVxuKnZYQstyAWfT+oHCa7UXXIpK93SwTHfsOXiQU7mT/Ezljgqymqxw8Nwu8LwUXf3H9XaeRYyVQ\nch6JHg/DW0lIxShP1Doc0ylf11kWCT9AYN8neFtEcOo9PGG9lpLouuJ6dguwrA0HijlPgTTmb3Qb\nDx4p0j8mIeOTfG6Cw6xY6bANqTD3VmYqfhudfeNfv0vuiyHrexPc7glQIV8sPtvnFMyioliyZHgy\nzv0fzxlFQRSuY+7Ns+pupMeS8sFfuxTqgOSeLYEV3Vl+zc7xkFlBlb7hm/ASSdWAXcK/Le5EewMr\nR6mSYX1oFiTI4m/68okKl4HOxof1f5ON8rjOs2RVK0mmDY6hk1XXuNQF30YcxSUDjbiFwiHuOKfv\nItVFEFYeCgh9SlmDPyUY6VJUsRWHCTw1Fy+qjYx7qUXaSOQ/ct+Gy1FVU4WLNdYaOuRPBFMARQK6\n6Q3G4jIUhPqzOFyJE0r0IsGySaoOlC7+rDcvdYn0CkHzyLDFi8y0nMsCpwWwIF7SuOgzSlj/qe4S\np1Jt2G44WmuP+FvuckbXElEdgIGL/4CYdmshQeaD4mS05hHNZEnYpAPeOWj0OHUS48jXuI6fSGKF\nNWKGONCIC3BodCC/9uxOmIMwTKTDxWoeyXT0xXEooTFQnzLkH4Zsa0mgS9rOOtqQpS76ZcTM6ELu\ndBY2R+xCC37SzsmmZnqjqURvlFHQWhfXxMixExPFhGf7HQoEOEcR8ZWtsrH11Oa8h5gkMK34hY61\n+RP2JAKaaOnavbRuPfcnAp3SiO0nZjAyRYx4AHxiIGzjMbDvOVNcq8sia5G7iIDh4oyGB3tgrRMx\nofieNpUWRE/m6OlzZioDrl/D0QAqbLOLIu3tGYoCnv08uO+h4k+zfQMRj2FqpfGhRDDB+qPE3W0/\nrQ787fr0YOk9OqEAjSFMUg4vrqF8MJDJAGfOYHt9quvdA9N9jcY2Rvo/qFa/ugzUe7trkqXc3EFt\nCt4CMkDK9nADiQ5lgipT2slZgentOnvEY7nVqMCzTbwkRQJxnc5xJLA/TCH/vcbxn9GEa1MVILC+\n2s/jRaydL0ujdZrx7AcKBrSl2jFOXH9kCcbk+a6YSfWXSC2/U9F+ACqt9I9/LR+pFVZpw44cNwI0\nU8gI//SOEqgd3H/2IwFqPaNFW7GeSzV+hGspd07T07f/4i6N7XUtABywu4X5skMnVPG9LRgQpija\n7vQYvV+nWGbcaQPlg9F+2mr+/qUGOpnZFS9fSwBhnPYsswvPoHAGoOQthwR7l9GYw2Z2yp55Twr/\nrtCyZ4XCdNMb9FjTN8nSxmGIXksdd8sWsa0rALvtBQByboNde8FpWAJ1W60nXPf9h7kfdg3kJeZi\neiRlIZp77JWhatE5gt4v4gRXqIbJfd8CU6cqBSY3pPeQH84AVEDgCYV2ZG4rHWvXMRnceKZD22uB\nKTIQWk6eqSYHKnryTrUo3DlxrOQWc33Z74Tl3KZUxxUJFe5HXUv2kHDjxHnYFgbIHkjiQYX+m7/K\nVas0QJuo8NEcrlUdVZ68LtfhxRaid2zKn8ksbQ8DdOyxkclcVTR5DXtJEBRUb+GG2V8fzd55TaiE\nLCoDOpWjAd1FNnu+GmQ5/IlfT2rluO3xd6WsS95GxPbhCosP17BzsNUdC4ptGPG55XZmtELAfhbO\nbfqzZGLWATJ9r6ETNAGL3jXGDE8D31ukyyLXLTHWX5WrnrzUraIKmDzcl9Ub1+RHzF2oSCPhHAl6\n8wjsQyda6yAKZgfim6YoYySbYRMa8FAVJ1bYwLKtQgPFpa4HLVRzExrtqbD9We4+mq/badP3EoGr\ncZCfUS3mgDYQijWetj24HDkO2bTmP9mDf4p115nhSy1dvQ5cDBfM1gspjtPiEngiIfNQFBR0/paz\nB/42bGcXnTa3y6aLnxLPBOP6E+VfdBtWaHjHJiLP9QE8of/vd/R4j4HjGevQ5/B74IqXgnrybrsk\nblNUYQkqXUMJ+WEN/PBbr+Pgb4uSqAG2fo39r/d8ZTdqkqovqQAyEwYKJjGmgRzJcsqrm9X0ABVd\njpzKTvLcBi0EEkmAut/Q9WKctX2wvWiKdGpinRUs6FU4cx4FR4rek+lUJLzP4pjgKmAmuTYGAyfz\nATQdfFE7J1N5ddp66v/v3xr6oS2UTuB3gL+rZ7/hGaswxZQDNatuoahpnta3DyQOrev9bcnrqL9t\n0Z1/j4QAjmU4SySJFh+9h9X8biliHVnzIr/KLld3WNoCWyG2x2jH05BlpWYOikoCTKmIjdW9oaXG\nqEvD/J7cEfwPrrRsjJmGW4fMfatPwOZJGe6kn5YzUhzOpVW9x8o7mpGPHmP3LgcYMQX18Lqps78v\nyq3fiG5lltk2/2uxRTGoIfoOHzumhrnyWcnxxn7C7E2u4qpAiXKw1hrpAnqqpff8Yax2Ok/wCo3K\nG1oJ3QwKAGZZATJz+kSpszMZW3k1Ga+1t+sv8Qh8yhKlo7ktbushcKloRGFzaioyvCjDooLKagPC\n4EtpYcwHQ6hQ0wmdEzeFEPs7jAtOkQq6WNKo8LbHVxVotCcP6G9xY/rIXzv20ltR9Z7sWUOHGbdW\nLkeHWtCdZ8Nvi7kSE2tETmj+mRn1XmlUgX6iRUo/U0AJfzNC4V3pjX2LWrPAzQkcyidlmG35UyrZ\nCdjzhrP2QzOv62830wPBb7gOlHvdqW0B9yKtx/kKBTyLX9UX9ghKygy5vekwCznrN7lHRW84HNCy\nlPiQHMB4kB9vYYtSQga4bGzgTQRRZzxlhVipOg1QK17Mb0KVBlhJnc5kJ5atXYNZJAp3OuveB9Kv\naBzoHV9u0OWgR4NbuRfYlsJJPOMYi+/cNCYEvJnHkKbsWfK+pXVXqa4leORIajLCuFvlYwUS0Boj\nTn2xD9yMNGPmEY6uE6syk4xSEa+ykmiYLfAYwUS3XgN/EkMmHWANk/N6zxlB+SJUimQJpsRtujtB\nm0dm744KjkL198yuQS97XyUyGlxxjdym4YZKsQ1OcjFM3L1m/oPIGQbpoPjlZKuisKrKjnztWBAT\ngsTOW1m//lLr2k0R2j+QP/FwlKD5iJBZgZqlEWKudmP5EOqwu7irDTqenpAl61FEHsiVGfOh8HMf\nkmH1gOW0IpATVzw0jhdvFuk1PDEvq0GH1L5iahBC1pI6mkswkisyZyDhQMIP2XlnFUKs4B633LbY\n5pC2ydXx/ZSgcofWSmNmfdGjtzs1MnLgF3ezTXIDsNg9kEOhLrXPorL+pw3M3rAmpATtPTehNr0T\n8lfEllMfVR4YSTG+Oi3CLikmHItY2h/G/rZ/Uq3Qr2HHowA88LvI7DUDUb/d0r6XFBV/LbaTEIiA\nCQoXQd6cNxEAE1ux5Zf9vem+YGerHtdYvCl0e9MOIfJ+DT3YoM6FfXQJ99nzdgC1dbMkUVhQNc0l\np9qouJo7Yr1UTAtUHXJMU7pVsX0VAKUHRKxA2zUE4mnvgh3/PyVXyreugwSJT7HZOcOblxmBlsSY\nD38Gtv30pLv0QYgH5XzW0kxxORrK5KT8OFqCeYyJvY73LlYi1Z/6jsnE9+eaATKi9GYyVCa1tWuS\nUshuRZmCbHlUHTwcoE0myRzKf9YkI7EHBO5UJ96ukYL4jK2NbN0zVSWTU1GI9C5WNOavXyLJ43ra\nADOHRKpg24MG95hBPj1xRPflkfr5WDOSNtZMnumS9ddZKpr/FAGRdffWkR84aOGTXsfm8/DBhmVk\n/2tyTROxW6Qqe1BWRNNHh9AvYMRur6MH9Gn66Tu/CdkrZtE3WwTMFTpcHtN6pfc3938x40nojTnb\nqNd8STyPwM9HN7/O+x2Gx+882mhsJ1FaPSgxb4OI8vgxowbtzK3M/guZQQ8XNQJEfElM12m6/sZx\nzZ08j0iMr1pkFz4TC0TihgFMFPIOdLbDXtSztKJAeFLMQYjzyMBp2irBclv7ysbjo0thwsA0iaQr\n9vwUywOrS5I8kMRsIX1jaVPCj5QkuiuUQdZdu8AcF6Fy9wiyT9YV5V4KxHyA9O5RlFVe0EZ/5Ozu\nYBJdfIxs8ML1u6nMrVBuPcstQV/vcbM8RFXv7b6+MxOc6iim44oOHGuZIX4CpMGmCOXaxTdJDSxd\nPldfjy8vjUHtiXEpD3vWBs3Rr6rfBOeHRTT6xp4/GHNLd+SxPONiQi87csW6lPqu+k/aw4/utFrm\nfkVIZMHzxLcpdrYxXIAiUJArn4nJtYMkiABxZiseAHUMB6REB0L3pl+TbfemtPKG8SsuR27w708Z\nfGdMDwL3NdT7jVjQT5HHPtgXF5ZzQyrbBLPUYCnLzsjlXypVb1XKwEjlGKkwYKjozGrz+0wPijoF\n8kIk7GHIK4AOS1KaDHb2hRuiBthRDCk9qTx8sctSefM4ofDdxfd42czegO87jOY59jHopWETEEF1\n3x151SCQr8w5+Ib3jU3sRGwGkQNrRn7WwGu7LhGKIEx35Pt0rPNBVysxkyrbsgkm+nk/SV6R5JAk\nwmWUosjAYigOUndnGRYmCOrj2et2cS7BEMife0+bI69eAS8zQ8wVzJx1K5KARM235qyVi/DJFZ1g\nhHmdgkbm7+5m3XbjKerZIuCc/nLeSml2JndMqLh5faHnQaVBRxTJ0+r5woHxmr/zfF/aQ07QErvJ\nlukogv3pky1Na1wdu8QPaUAsEq0r1dnydp/ow+cwm8xJOlrxBRG4xoxfKS9qaW2h+TW/CQbIgMrq\nkbICRAl8jS7BtqjTIsTrEdOCey9FPEXNYERRQAjn/cNzbZ9ILhnrWHKKoa4q42gmdUcuUjFICh5O\nHgpr4wY0Wf1KOiAOCI2oyjuGxzwe0eLtJsY9P/rA6Q9TRix7Q4Km9PXaR//iJYXflWu0lDbLFZ8W\nqUme1hmVCEpGTJMANnxAuNCmL97QyWsM4hWKlaMQBiVPHvNvizUxKCZGaGWKjOOmvPZd1D9hIvHT\nda6KxtX0VKMAtzyLgBdQsP57GW6RndPiUzcxxWx7t/3qW7OJyTyOT/INHICKQLpmv9LP8XNhlzfW\nxMnbIgRqztGJrcK3lTjOHk673SXvxY9fxr/KBW3Gw2wQmlt14LMKps+gb7Xhdj63pP/+LfnRkePS\nWXaqtn20eljSt904np+3jL/JgTdp60MDx9JERZazb4KcRDqeSgY/nzQIMLxnkn9V6GB8V1Xxb0lA\nLT9eM4g5u11f9donBe4lK7N4OiOSG+QiQP2gJWW8POhgADBd5B4awxY+W+O/uPnBDA9G6u+Z3g8l\n3VFeEAquDoSu26POkSpA7wXHFWMItpcp4ClGlQ5TVjt98eL66vQiVFGjp41mlKW8uSEX0Czoj+d2\nnm4LGTR2+ggb9HqG4t0ZHXN5qQL7fei9sxEBeug5Y5ptU05CXcuH6+94BgdXKU3FMB9rlcTQcug4\nflVMXdcCixWHr8l+FR+LHNaEnA7nQwO87Q3FNq7epGSGxGRM89WZZ1qXB19wXrgjobeeWjJ6slGI\nks5dhPM/P+yvSElGWhLsdiPrqUD+qbRsMkPw1tTvrkOmnF1EB9x9XdVwX8rNIytUIjSNZG/uQGPc\nobr0xnJrneqDI5cqpW1fO91ZgsP/WO1XJfvoPkZUhPh8JVL+DsFm3xq+rG/jP1jKte0AbvFw3lCu\n6a9GboBIFe9ZX/FhDg/u1aKnIlcuoK1zL3TNB86FQdIDdkUpT95mZGstnh8q3uZgKPxJeNbEE+zu\nVbEfKA8ASQExNXsDeRfkoUXCeroHSNIcFKS7jiq/T6lDLJE6khzoOH2erjy1hFsJYH2eyJarjHNP\n7mTNmMKPgd5Q/1CkzU6kk7yBmxg+RX6zhQf1qHf0r2enfArH7efp7OBsvkU2UKCglKQftTfr4XcM\nbjAy2QqaUdiKfCwKtTjFWvMj78kRgq89xlc6NZRi0LpgCxMEk0JkMCdiNVeU8K0e4L2x9KPQ9rpW\nZyfpofS8Ff/bhSHbqLyByCZPiRmKrgD0FPA9098BprY2fJs+yDShttloZedRXFwj4CagcA9k6/fq\nQeaiqp+Vg/E7iTel49NTxRWB1zLiX0FJn44TILwWjqvfWEextPSBNxOfobDk1r5cS9DNRJhii9vE\nmeDzDQgWDU+8dDfs8zih9ypACW5UGzGHCY7v3STkJ3A0qGMkAjlYSRCmXJyOKt+eIFcdtVLWgHAN\nnL6ZghgptdrR+Dsxz+sYe/LRUI/3gDuQl7ehyKFR9QinGTOxk6PgxvNB6SsJi3r3xd5h99Hk2Flx\nkZZyltVT3++Ob/0LiPZc/b77wa2WUX05oU43nVZDPqqHmQFj3UXoD4ch/AyAutEh0eKXmSjsUY0f\nLbgn5/zxgi43zyuUMyBQp5ViveAH0LkUBdT0ZRBYUr5uWCk5bZ26o8m44svk5phHNqNi6Dpgwv/v\nhxMFK9mLKfEol5i++cymDRcHCvjpiQWY9daCdZijtulP3evuAmya0pHsKCuJHZ6dVuFG6Bh9ylej\nyLKuZv7h11/xYLW/YPE/LjL1jmlMOoAIys/oW6tmVjMJ6YTJbyjFBYmJdYAWxMt60MGJ72/WzX4C\nG/HpseLIVQz5RHvfjKvcN3U4gVO1oas5kXVH5h+bn5axfn1xSEfygULD0hG+ODDrA58cZghotgbg\n28/GTPvAUp0EaCMTQ2ERxkElg++bN+rKIl8K0slpnTZHxqFRP8yYiSmNTYxA3bTTIwaWHobRhjOC\nnnsevXp4DRGUFhhwKaEwkuXAUKKsN9jfoYO60YnwBIHkPdnLMOKE1X5S0TmxvksP95uhiZye1Vi6\n/6KiJ4eLXH7g6zy5uV9WxD1u/u4lji99tskRyKwUbhK3mkFwRF4sW9SIzoQHDT8YPOZ/Ns1Ab1Hd\n8icEmy45yLPL46uZj3p1CUBOSNvwPDWw1Q0B3KWZKsZ8c9r5oC2xjjO4ZGIS0ksyWB0OwJx55SFD\n3vKi6UwO4BnjolyTPRfoFzgUQC0IuxSu57xuDFZrdI7oM5rV1XQBEJux0OqGNME4+2R8dxHfCW17\nqe4+oxEg9s8vdqM3oSGVCo3VVWHgzEedhhOd+JccHi4ioiyP/EIyUytTwKMKY80zls0OljyOMLoU\nBx3RsuIxSXG61Bhhn0rhsvFy6LnGuYC/DohVcw+gCr25zaUjYBe1tAJjqbp7tEksYk3r7gQoONTb\nsrHhNWpTeJ1nLFFa5bO14MrfS1uwfewdHUKRs8YKEGYkkj7rsOLF8Rwzda+Bu9VC5bYDSGNfBCqX\nHdcuSmtnQAGcHv+lfPQjMvF8rOL0WRL2mqIXNkGhzehkyDPT0Euv0VbU8VcQpLBx/FRTI/6Cxdmn\nozlfWH0UjEqnJSKMGZDax591NZ1bus/w3Vpf+k3/eVHc3rnmMYczdKhxTnosw1Txbb0uPK6RFphf\nJ7MpP2Km9RcHicqGzDXRfa/cxADloPmplp8/U2nrF5QMilP6uIjswp4OVzft2YI1qwA3Bk67X6Vx\nOGZWYp1HBlEnYUHhM4vCf4/NqTWLcZX79C5Z3E71NtCcauX58kq9fcpeIijcbc1G7z9SFEVsVIqW\nqbqqllNkvhSBkWIw8A2WQ8YbcN3TblzHb11ScbnEHMlAym5Vt3yIMywIRzM2Hj/VHDJEu4SAj1jL\neka6zoMQfPR/vEi2qDYq1QqutmAjVmoJOo90IZUtPEXGyEe/eayJH1Q9eDvUh3YEkywP7Hh9Gwou\n7CAMgNncIapjC7bDcB6jQv7imTtcQeazr4o7YrFQnekhPT9PZWbhzVlbEN79eNkkPn7bPUV0zqyZ\nSuT9B9A3Qcr33dt2sEKHK5ReF5gzboDKJ6qQx6AIhmiwuwzWlpocy+/YmogwifVD7ieVpYn5EltH\nDREUP5lwoYo97Wb7z2JFWa+zMJvaYoyr6tcu5tAPG7TC0+dYKNAqlLAWHIdddsnGuUxtwXHBfe6r\nnrATvgMeMTMgqaTgI7tqMCuIcifybHyfBsFKexkev4HAsN6hoAEORJsej13HTvjChRV2Vt2VRTAR\naUOTTNOxKgQ937tRRssxp9cVMopdxjj4DcRtSeExUUwD/x9+04qR5XTpyXca0V6W4e6Mtvn0ePJj\nxQZIybNLuyrRj7hiL/ASMciwaD4GEpy28gZ5qTHofbyap8cjcNwfVO7ijhLAP1l1NsIlkbAEuBK/\nw5KPGnvkABIuRDSLJR1KFYS2soAmPlIk/omNrfjNG5KcwFLYd7Em3gXq3U6ambrtA1Z+FlcC4V73\nQlw3D4/tLtKnCRR3vRsTwcNbRo6TqcRviK5spYs8XXJOqZVpw2rWMTPcyGrjQO0KjRp9P6RQVZIp\npevBhIIH0ToNefUyfdyrLBUvUUzzV+Sq6wcT7ESL1wu9eCVEHNtFFlaF5faQWSrSwXzQUuqVRxlQ\nXSiMEtglKXzqZAV3ItxnGk/jR9I58lsnjDdVxhimaP/pqf3tVU5//5v0tAq5yMfBQ4d1eaWKi5Z9\nmWxt8mqmOQY09oWYiUR6sXPFx3V+IT86Wg+9IfOVsPuo7HX1616503nEJ/S/o+BFIIZ4bUyQaIsT\nWttSq7FUXQZHQQPpb8cWhcNrcnyjRFzIlao5BQrQx6LfWxhWEIKKrw4+oxg6GtjSSL1EqSAKry1v\nh4nmXHVKXkj0EhUOkmRcLdsrC54d3Zm2WwMgrBXbXTCu09N8JxIvyCoOpG/ffXBCQ/xVtl9q1DVA\n4zWvQnAijXtN3L6gO2tji31/wP4kx3BQALmBkBrdNnkpsmMUSFTCKomCosZ/C+IkXTBp1P3TYs0h\n8L8TNvvXZ13k7RkN6OPtWWQ7vXhuwz934O6lMo/HsH5vedpzd2O7UHjMtaDHPvc7O3NZmCZ8/3Jf\nayayf7t0mOP6I1pths0Mn1GOSQ0Bq9FPlINxQCClh8YxqEp+5d9TOZ2YFBVDZ6FB11VfIPrHJr36\nFvoVBKhrIypS4LDN6YpS80rrOskwAsg/yoB238QT7LshjAPxGzwvIyABW423EDH64MBIp6cCSEDN\nSRCv2FMKmGgUjfWVC2G4IAuTl/VJPsMMAa3k+q61LFupvjZEhPqdzRAycwzWHrrZmrrhZVDma3xX\nYZdOJlnvZ0UAUghDHLrFaO/hRIJJqXnuzoBRiWsXlM1cx7ApBKsGC5F2X3vdfVEPlwz/kJCCDUJu\nuKPH82wkpQme3p9lqFm2aEHyKnoNRzScfkpy2jt7O4N58E9ogQHC7ZmLUYpI1NvvnmeKqFPlkBK2\n1n1cvaDNgj5YpUpzCCIVzAeWJwmV8QGzG9yjinvbTUWy/CUtjrEt9ZlyG2mNWfIKcje1U5jyaX1o\nfrsVy3cSex2TaJH9XZYNTooa+smWITcV+9ffZ9wtgtL8yeb8A/6G9Ca85lJcbdXBo5tWM6AVl8d0\nl4G98A7C9XbIN3R2m/1WELmozGCvF5QxK4gyIqt3ueCX9ZvnIS751ere/ja1jEefdiT2hKvxyYB5\nbM7AfWu5ieslyK7IsEkGPbRNYNA/QFSnjO+IQn2LOCKl8R3VFR2WXw8Rm+Mn6yZi9KUhdLQgOVyg\nZOjrRWPbiigSGTXOS4EC7d++PWAvW+ZmI3sljf2cM3pXPf8D76O2vcyuIh4YRDAc5mO+2DfvpNzL\nnI19HtpVgoeZWVD3SibxGgigPhRtHNQijE5NEuPOLQ/xxw9asvhWNJrkh674GgBrinh6Ja4uFm3o\nWHFHisXQ3yqPAg+UGfUiQ1I53yuSkGzqbKT9gYgefWWjPeAlns0rXAcDCjsnSpA796rtArbF523E\nBmAtdwXZdEGl1x+oqw4ckrx+xhduYG4gutVuAtnqJF7dboIpNGl9vHVFCTtarEK8Q4Oq9hXJM3kC\nnFhwWWwlQrKZnCvwhlMW4PNW+/dVObOX/LHLA3PjVFnRS25kDcF/yvBbm888qP/mygfxQNyFu5zR\n8cdPkk+1YshJeQ1RWzS4wHe59WMfCDsGilkWZCx1J1AfMoFwU3CRLzziw4xc0Zw3sV4WVE4w1ny8\ndObK0v3tTDdlRkDrmU8PO+FX/CxFuh0qOvDGLa4LVQfcmaEHycPVW+ooNengqPTJjjY2RIu+fOP0\nQ33P9MLVQbdVp+hKG7cKqpsJE92KtCiej10CUM5u0hPzuiMOIpyqUNvcJITry0aybv8KBrz+0/mz\nuVoi57JRUSnnO3v1bTDMqlG88Plo8HYEbKpOdacCtkBhYK6dRMDXr/qRrQ9dbGx8lFbsj3qQek+o\nEScTdG1WKASNWKF494kNSMHq/bzUR2k6EKEmtbuR/tQ2zn9ecnBtNAvfEj6S0LTaiKylfG/gucEW\nOIDALrrAJ+VLN0j5fCw+7FGlxcYZvkm586T/RLDVzOR4qYv8LAjB14DTnmrXlClYS3IhuQZZpLS5\nh545uo+hPkSvFdXGetnvh8XeSkW0tfWI70m3x1PeuzpVzhkfxZZVOzQWyp6rgFcmpSgEPkaUtu6u\nuGO4ojrGG5mV/XmDrfl7voUHByXf+M1bS8aytAgrfNxYx1F3beYd9W9E12FPDzvcxXPDjv8p3RcK\nnZsOBDZOw7/z64rG9Nlzx4cHRtl9EZaiHlq88a13jADE//kQR4p+H9+Y1q13gUtAoVbO/ejajyTN\nt72FMMyz3iQFURH4VHa8g2A1g3+cWKCr5hFC+pfkuCgyWvjowVHCt2MWnBMY7CVA/u60FCKkkKkI\ndXttjn3QcDqH/7tX1tJtMIyseY6Up0NdtsmW+SGAWg8dkfPdHdH6Z7efwRD94JhFHrBStLeIQMnM\njqRYE9LmT+L5FUk6s71H1b2HWnfhzriMvbc4Fc2JgG5G66ogoSTzPlSjgN+L5PZZ5BF0onOc+s2V\nlG+QnEQ5ppERvQ72tCNRbvms5XpB19KTBMrgd/ijqk+//m9IvYChjEEITH+VkFqCA77pwGZyV6R9\n4E9Z8uMjClIB/ZnJDjMQ93hPeLIcB4MW1CbExBiVCole2ejZRSIoFULNA532P4Q9/AxcoLJ2tssH\n3iDFv9e8PBcmAex661NKJN0D+uynkef3n/m0+fXSdUKc+sCMOkQU5L/eInBAbuVYYfAyv2e5VDpu\nokbzKope4GNxj1BDoI/trTuKmblTLVQne9tAK+eIg3prYUJ8l2nugP0f+NwR5KyEiIyXQ8qwGxYo\nb3wiu7WZOEAW3EnRH3gcFSeXagiCoZSbEtdZML/kLmakcQa9NzUgeT8rcr3mon5bBvlROIFUcwLv\nVqkBChJXc2wNHEwl/ME386wFmH6IC0W4Ndy3NW2WXxqRYJYSODv4pN+0yypKHCb3FR0C4NW2fIc5\nq000kSIw29HyOPXN4jjwMs2m9SJWtxO0wJsYTu5JEU+FgGwcnB1mQjA5t5Nr9+06IkToEHWcoF59\nvXhp4wRhksXkODVS1W5zNqakYaPzRgFLky+6nR6yDQW9OcfRkVRDBvBagnQqtYoWCaUc+D3hY5Lh\n6Mw9WkGBSNQ2i1g8XghFau5362HBKc4V9pwOd81xEwYLkiLNwPm52sNIgf3rwaV2h+c56WsseNPt\nLLF6MC7qKLmH6a08kzW7T2uxP/BkfIgNF/Fwpo7hjI+0nwOYXEOoxV1OHllU6OqEPuHaZsyiWF7m\n81B4x3R8CU5LAvN7JwgQzOsLJfQO4l37DO8PFFTuxhOHimJLMdJiuKN3LKhl2vlUp7+zWEQyRy5Z\njrcDqczEb1+KAf72t0yQSlgehndUyOVX0h12zAPqdo/DUlK0jjQNGFzxwTnxtdE3pMjVgZaxWaA0\nMRM3gfJ9T+ghd+qQ8qn+c88iWTuLORTN/GCq4HqKaWaFxaaiJHsO8fjAqrs8IOgoJZRHjwZ1sJmk\nGgLtg0OSKNM7CyqomOnBKxc4CGWvAsRsgRuowMPzSBnEUWWQ8/QFUt6a42Pj1KzgS7rfScX4DdW5\nVOMUnOSNNWckfQG39VNN4ncnv41b1vDG5LjSO68z4w5Pj64t+Ymn7eHjxpczjmXHPOs62cY8T/86\nDtVFMoG7hb2OaSYJ4Duu+zuQ/xVaqKyb3W2j/P739shoWI0DEs1CnF8c6fzgCdQ8JjFRi457b6ix\nOps+P7ywu12aLm2rvxBPtp+oVDT3kvktUvZiNg/QH9QNAI112iIkx2HSYC9O5y/jAXrLD4iIAmss\nCmaxspQIbQiUOENSgULaIbLUxtMJnU8DFT2DseYjTnV0dDkgmKvrX3zTWdY+d2a6O9MnF4dYRNDe\nC1KKCC93V9D9oky0Xhn5zOewW64UCuOUcHIa155HSs8TPv6T471BHF+Hqj6fY93rF+cjzZC9TJAR\nnqIVqHk0gQm/O16EO3cY7myN1n1WUKSwEPHbGRB0RTdwZu2XKXOlCtdOBjBBSdZq+82LcZn0ClaF\nY5NGGp6iZti2yUZF2w9+6LftSiJMJeaUGMR0xAYk6EFXn5iz7Nw69SNzFx7xaO8ozWhuMtdfBevN\n9QODiFMO+teV4+rz0raHNYbo8PlHWNuxKas5Z6keDuOQunM7xzuV9srkIBL5prhvyfFO6+EDtO0j\nciPEjdayOABY8NCdAjQqtw2zSMgbbL1z1OnfqmLCZISZmS5pRZpITsgzP3iHQKnS8pbIVyImcHx8\nQ2N8x/3KsSiI2SUoWrtaV+T0MQISMqA6F+QbjSyuc5W3UFC3fy8JVizb1mYd8NRshMu2wRLViEN7\n/SKWIqsDSE5Jr1YAFpy4aC+OcgZ5OMMdlw0FFy/K/IIGNfQ4X5XLiFouaIzxVfSQhwSS7rhIc8Ck\nCO8AIpTTPvTJKLvf9GelYcqg3l30xyEwQKTL0eJIZXoIx2OUuHnVsrY9MlP9hJTlVJfrLcNFaGKM\nS1feYvr268PmSe0tEwF83EXzBoxxQfzDv21j6VdB/8PVy0w3GcVxT0k74UEoVETjQKZCbQfcKwiO\n27TpE6kShO7bV24u23nfbZ4L5ProV8KNRkLCfbKAiAhmwWXT7esfZErlRgIDmEGrZ52PpMJIi5j6\nNMhflopVraTWya4ua+D6LpNBbsNSAoxY5CK5+qKvVuHVnOJeY5m4JbblGj7o3g3vVjrJ35AGp0Q2\nGQW49YulewMbqbp8Tf3yc45IRFrzKW9G61hj5/ftEjb+OpM0HWr4XOKQ/Difb2u31y/BbsrEVMNg\nfl8jXL9zh+um6/ZDQTpoDsg+zFYaJiHQew3idfONLHndHFZ0gs/Io520SVqlXhuvUf5jJv+j2lUQ\nWnTZUDqUJsa+4QPaISLH2u+nf12zYDdR8hzO4uL92kXwpjfh6Fd0O9LHwTF1u7jyX7/eF8G1f5e6\n1/CHuGSfeHkF2r7rIMCkpYGi/2GV4VwXqYpL1b77XQPB71tDH2S7eRBQd9QucrTKKWTIcE9XnC3V\nX7Ti/x3yXmfdwJIVv273PgxyoDS6Dmb4q3dbNfo35GZvUuj05YM8tREYB6Dlzn0TbQbWBSdBwp8W\n9GvVEuYAhG8XM5qxx4D40tlZcPZDNwUeE3U9LARc16j67Wf4UX/KkRWrdApAu81VPnQEk3TZADzW\nJyYtAOjkxW1XSwXeD/MF2zJXP8pmSsU7n+PFX2+KfXyG0IaMjsz+vlPV6o7RtiUO+FuwET3OjmaL\nXYgFjJZQggkgjAIkMIsbL0ObvTlzsiFlIAIHVmo939toXeB+rPh6y4/MdBblMVbArDRrebbk09gu\nZl5c+nQT76gOv6Cc/oUMoiyuLupraZKNTzX3Y3qtixsHcPbv8eXmQQVDsuXsZBA4JJhlg8mlM9li\nq7XeAtfGqfG8r+pLSSd8gYSlVMT4qbcp9AjFv8R9fJoi07hPSqgL68XGKr42kO0jXy1kJqanI6vS\nk3dFVyHjwQ+48Zn2E1kwaB1grkLdgqG7kN4k1kP7pdC+9HQvNcTgMWLoKhvQRFDaIfzDXEeqZ3TU\ng5lzg6l9Hx28wD1tDy6ToBhmzrqOBq6fNHhwQUzPt91xboNJr4UrUTLafr2YTToqLtLdL8EA0iCk\nZF0CSKFqbQ/fg2dE3LaJ7HW1yz15ZTeZ1zpRNVP0DzwhDRFA1HdTNg0HUlG8O1yKx1rNlEwymyQo\n2VNbrQkq6M4QASEL6YY+fl0Hs7iYo2ihc9/QeP0LnCOBXEDJOkPoK6HClH2NE/4Y4DWBL6bODCY3\nx+U9wy9JdyQCahPnAbvKkozUbHXijmgI4PQrYKnyursnrwLr60Yw7HhoZbZ0p6MhOwCi5JrZB5hh\nSW5ISrQFF+Uqz6/BpHQQuPOzNFua0blkK3TavhxUJKoEfAYbA+zIoKqXqV7wHBcXeWhvubvqqwet\nTzPwYW/3nYCSWD8ck0jb46dHFk5ueShYOuVP6/lp0rCTdfoVexfctezamcpVSOjg70nJWHvYTWwe\nmF5sEy3Xr59Ueg59zYsegjqFCNb/9SUaJdvYiPipo2JzhJQa6HZxo0wGbHyR/p49vaYl/mU+/kXl\nJYiAYugZes0CVvBa8Gvw9Y4cChXUbl99uNSw8rRfR0LQCCnDglHMW+nU+LPppQpRy8o6RsHBWnAT\n0KGulfy+Re4gb01K0jHbHc1APWAnPk+gfldt26i9OF+TEVoxY63cTL6HotA44DcjhtsoHIUBxSmH\nrXM/jVm+bWaB5AKS/0z5uvMoagEWkBsApaTynVu7sY+1aJ09XCEWsB8MihhMudIJVweb7+5E4ir/\nxi4LP3GByKf4vfq7LmUNjfkqJn9Tjy7jMw9V6474bMxiwgtIW5EYSm4QDgrWnODo+t7VmMImb9ua\nsbmafsZIuuYvC19AIquaIAS/NnS8bS+TmOTxjfAq9qVsjulvl/HZP00+E+zp47FAWti46xJSCMni\nNQ1qE2kqZ+wIIU92u6W07URSepLxk4lpd8ksnZh12b5ErBpFi67PqTx59WUqkn6+CRKosqethNEm\n2d7018vOwz8cFKS7rcjZretK97H0g/eIbS1C4zKkSUIGNni4hfS9q9PVHxSv/G/zK9x2TVb6MIbm\nCigdvZ5JClFleHJ3wBulN/s751livn4ypjrV3TLv/1s6lPnDHFL4NQAOYFhZZUDmB9NZ98S7x7Wo\nljNMOLwCrkFU75M1BJGXHth0y4fPGJL5vEo9EzJEuVC4AQizv1PI1X8iqNAegh08wLNz3ocMrY0v\nfG2333u9QyvzsDrDHLkoKjWiWqKf247b8/RBOTGZZDo7bvvEI21gVz3w0qn8/ERBzG0K0K03Oyht\nz5zdjkMQQ+wLxYO430seNjRG3hOGqB5qyYivVXqG1+WXPj/qVKsQXQTZojrd/i54tuJQWTWSczPW\ndd9f8sPKtpaqSXPqydEjNft/8fxuI0uTPml0rRRwLBC+FEVHRjlkYWq0x+Uk5K444jvcL0Y2FQIP\npp60fPoR2prTClv1jCd1YcyFJuYtq+b6DLy3ngmUbtx9HOossZiBRSoYeXIbFaqd1NGRrvrhiS6C\nMInT+xdfQeBbNhgH1sxxO8LXrviWCvdZKiGjgJpmKXSGLq2XE5y8JPDRz4qsdt4NplGupXGdm3vA\nNepsDoxkQtQVsbiDuWznnbVZ6WdoX3E/CKDC93oJWib0eBndW9EnNwgtQ3xafoCipUDXKudnC1gs\niGZjQAtPxwSGUbpN7pmC3j1PQJ45bJtPc73gNTtgCADoLEUdsjU6tqHqY3gronLQtsvY1+0SbGU9\nZraQLQCZ0Y9eTMTNyX5QUx+cSU4AZC4giWgk4ZtkN8BSxUBp0YuWWjNxygx9xXwns3m8CoE8C8/0\nE4X96O0eHtAuzuw1Gg2KFOHYI8TdJtCnWmiAtaOEC2KhqoV8U8Ark8A/Z7Rca5xKdk/k5jwqPQ3T\nvueELC+eJDWwWZO0lUkD1HOTDv+iISE6fKn4j6hr4jJeKBtPo02tWqj5/sja/cfFBwViSzzKPIKy\n2vYbw5GwothPLNpqOtomHbDSY8py04kmy5hCSoPaCBtB/OTa3HbrSJxiWJUpCe++5BZe1uPotLW5\neRfl0z8YyMK6pCjEuE6ROuwF+Kq/joZUI44KxyGX+gEl1IDTD3L4tP/aqqLn0/HV2uc4ZAOCBGW/\nfEE4tumfJ+pTuocy3Wkb6GaBY8MHjklAoEaCn2+hN3pD1ta5WRqJe6E+sx8ndY4jU0dZjTPyjQpw\nU+nL3oyMRzEUajmiAthmmQdNRX8DyQa0BGXiHrhNh4Y2/1W276snrQuqrxYKOZLNCO7U9mjRVQk2\nu96alb6i5HnVOAeQXIzCSzZlGDXrzZYlpxZPdm4C0OX2Yyn6Huz2rwph4oPewgrErX1/Pkz4gX2S\nW8dMjTs1g0A48cFHRsuDLHWsUEZA3AKfXUhfWM1nBINKJDaFVOc8kgAt3KAmXc07GjO37Gk0qtDv\nwTsaHg4mE+vpZr1djvm7gZT9eaD2EZSZlYcRKlkvDS3c9ZYreIqSbHZfIksfXS+TUQnLGCl+TeV5\nCzRe60FsS5PFsB+b+kPiTTN9Msfrx4sqV4JiTXF75TGmX3bvG08iJNxwmA+g0hlODNQfbjtJfbeh\nZNTScuM2nb90CsAlIrlT3qASepHvmfeKrXjcGIoiJSEx4QJHrzN7AFFRgazVBH+qA9TopSeLsg9O\nTjvtqiiK6RxGDMT5K6z5alD4Qze8gDsNw4e7F7lsQ9I2rnr/z6o9QRpEvLDcWaLweSTMxhhwY5h8\nSepTuemrl5JtzKmFxezJxEPfYzy8tUuN+17FVZCpoyW9IU5SeK757zwia2zDwIHPBWhWseHRFl49\nygCXeFn7CzxkMqFuvuIPzIisvNsqiDCGNOikSHjn0xfp0k7W6fgeQGf0r8uUKFEnjCqzmdrCyZvP\n+HjvWf7++nEoponqdtUXALpV0nw4O7+lwYy7g5GTIxmh9C5pLriOb5MIFrK2F1jFM4xm0JFjpU0C\nRFbUJeOGvL4xVrE5wl3RjsQF2oqbnblx8dPVkEx/VpJQZ5/G8D6bEhHmgzdXMlGcvdSjdyfvV8b4\neG9bdtLLjeDmwblRUKR+v3UqVDpg2qZ25N4afdZLsaAYwKfD7LFd+ldNZ/fHsYf1IGypxHrmmde4\nNs2Ykqdphqj+/ceZRVSnCGJeCHs+yJxez8541U1WbfMhrap7g6LBPauUY1ArqyMHlVJcllA7F1Uq\n5fx+ySHM17oKhX4J7j2NFWeAZ4am3rXYqf4/AXwO8FGZrMOaX6Ws2pLeCsJiQZCiXdvSySQGdxkw\nDlVV3cPuexKyWQ6JByEKwBskjPFNq7cHKLgHEDMELsk0PyOIayn7fvGKjGWBfeCvhTck+t7ERR4z\nzkox5oxf3zKWuJusRnD5G4nHqtdkDOzHcNIW4AVLOnTPGvMIqlnRw340lozn+yvoj2IboGcZluDz\nKzzU5AeBJy9iJEshaLdXnckDCkElVR4WPqc5LeIoYOR/Ilmv6Szl904pYsmbmrdMfI4Fk9HCPAn4\np6Fzg2iee6pruaMn2qxX/rSHn9hlwSEmTxK3NCWiXznsh8XkwuVG+LnIuvwg+aAt7dK85ziJFwFY\nqS9qTzqbIM/rC08J3KYXBKpWeKWbqntqqGTCgIJcBpbEsLzr0sASR1VVzwnvtUof0KWWN3KKtHQG\ntezmzLe7qmSXtDNvDjmLnc4AHbg+FTyTSJ06b1Dap9aOpACMjoleTr4ehQ3bEZh4RkvBtJ5oOWNs\nnQWnWrI6h6wkNx4wbdV9cCqmewkz57Zf9qp8//be9h+TCybn2faxFiw0zPnb7MNIeIyJRqmYx3AH\nJatxPE+WoDzrDfTjF9YVXvVwsUgUIbKw5jIv6P69rOfjF1fT7C+HNWcIeufBRVatYOQY7KXiB904\nTxbWEhPGReiQSnsbfzmt0YWw0YOknO/KhCwUCZeCGyZS75FM5jWUfh2uVFosmcQ1dUPgIqKnTvTh\nH4Jn8/BPTZpqqFm/2IIvUZ3Xn4ioRG6TrbsWwUiJWcaHixavfFHloml9fF5Zph4M+BJfk7f265T3\nguCwikoZQCYOYWkzFWOEza9LxUn38iEwfoDZWFtwYSuXJF3KEBGNMxeXwkGlkrDoemXMdqCBNtbq\nQ2deOZDi3L8iXgsRB2QaQo477N8IJY1L4HEl3NvS3qca4MSRtUvztUjoIh9M6XnzDGlq2T0qsC/x\nR74pLWlQ4gCG6k/WkqWOgA3oBa8L5m8AtBTI5T/CvwCAoMa2s2iMylXuvKOkymkl0+b9gQt9QfOA\naIe4Ep5opX+6YWYlH+pR0O+BW6OnzSiBH5Dx80hETOAj8yHEayCGmx2TIjanemMSqiCMKLqbyksI\n8qLFXuFiomuk2fdDz+tgaiRYinqMvMnDoR5yNMSGrS1c//3ztemlegMfCgYFgS4R5cZFf3mYFYla\naYdZSQan5887kwhEu7Y/DWgxS4WE8/9FjJSYr09PYCkUCZ+jAguPCASpjKmGiB88+hgozAPbAxzY\nG+v+lKSXDtt5QUDJuEdugV/AI4sJnjqGqNdOVHtGThdQnCtTCDWh0D7Vl6dDZjulG0PvBQ2PoD+c\nopzHh/HhbVJGHYwW/S7VXxou1xWWHo83kYcVPUGglN2uRqR4I0h30oIxDXOkgLgWRfj9ABPyZhPP\nmDVxkkb8B4pmEELnyRVKS9ele+FFfq6E+3QvihaSXwkmdhwn+OwypX1iJIZNGEzHOjWpU3MV7VK6\nkifTQ/oo+TTDYwTdI45sk03BMgQf5fzLWQo4jOsRA4ue3e28dDeVrGIUK5M8mxgKufF6zNTmbmNl\no7344SlbqB20IplUbG5TwPansKVOzocKJ0vAELffgX0WxLnXy6E0R1SaccIem4xAXcr02DMzw3KZ\nc8L/P+0T9UJpI3GEHuBR0A7NSLiqRm8uTcOz9LnCUgb1necGXABf1WZs5pmyJmeGLYuzQKOfR2t8\n9oSlmJT8mhF9I6fHXAC6btcKJEb5I4y1/7ModtTzUlHrQvMd3SVyZK8EEnUAxAAsSV7g808RJ3zB\n6RBioA9c+yBmKuzHHohfYE4a8XlpJ4bifK3AVHMNtxBmV1NI3m/VLL+n69I3iV5YR976GUloNbQi\n/3j9DTfhbZoMW+/7vE0M0zNumI+T7WmsBEvXDDSJqIBqhfEpClTfN8zGX2IvYz8gVa6uBJ1kZqX9\nE1bgn0Q8h3lTtM2GkjoSMtrKsNpabYFtQEtcdhbDQXZ8DcN/hc9d4C1cS12u1pDC/BMxslblIwmJ\nTUGedFAVLoAUgbgPKkOx78Ij+rCchcq6sPABEiCLa9p/0i88ZOYjfDJxJV6rafRTFHQh2ISwhTVr\nN3yAM4k5dvcHXmtvU6cLZNk9iAxhsBSo3v/suz3aoc6ds/RLVqW53vnIXC3Su/eBpnKm71Fz49BH\nCYVzEThDhKOOXKNKTlN6r4OkdZn4QULVo2xBc/ByagYE48n3kqaFnEILD/aun6kvogEVscwOtoQY\n2wlHEy1OBzA6MbdOY1wl3orFykVq7OSaZWo86yQ91GyA6JAImlZePlqgnkA68yBOWMRX5XrmROX/\nMwvxsD1CT4UFy+r4ehKLBG8tqvdK3HyKuCGd3CGkFHLnnfF3KDMELwmGhngI5ds7Fb5BhL24eFCp\n6Uum1dS1SoWV6jGoK2CKBMHjEZArKzCXgxxuXPNI0rwksr/m4RtbCWRrdQB+9k9YLMSaRhbR23/0\nHgAoMk2+mH0egNddxMo+PmCvSOdAI9UGzpwUWVbGOrAoTdOF0fqN1v9S4Kvb9IcHnB4WHtmcjrdI\nxg3ngdjxQ6ghcMIRiZOSK8l4vPKbrEkvdlPZ5mwtwm3Y12TLLWkjxBlW8v7lymgnHkT6KeNC4esX\nNQUdXvDLnrKaAEthb4vFvbjYra644V0dSVUbKhxselBZaEPFOMUCJBio1D3srsHuYAWVe3xLiYyq\nLZZrjjTkBHnqeOgW4J4QYDMReHcppKDvdPszKhUMHKBayMYYpBSK6Flu07pL5yX0YlKzvv6Orf1H\n5ZrNocCephakwqrvWF6nsZCBFaXmAnL8+e+CeJJoEQ7EHRRU0tizS9BFcUFDnCNc+LfFtz65r7WZ\nQcEYuYfgCTZC2iJoxM2fX1evjyulQaxRkstmRcamXrHoOXXoRtpe67VlaNq+dQ5rJ6XQ+feQ03aq\nS0BVsGIYqehptI8Yx5mFzJHLWrN2P2UAyxuW03xFjWJgOPSowCbnJ2HSiUPDkJOEuuJMRFmVi8fh\nB9CfIU4LrOBtoHHAxlwi5V4Oiuq+DsxCypOA4PJb4wQpAenVoAQySKTLeV3GQcb0AUCc/GwPjq/E\nDVoppw6O0KPqHSSH9ADV1b0d6SZiUQpbB0wNHJzW6sKWxf6488Q5SIdlSmJ+k1cS/pp0KS9S8zUN\nLpD71SB7akZbW8bSP2h+lVfsPGx+U1+ExzkMz8uI9AiF9hyT+fo7l3FhHd6zwlOyNv/jOMph4vxW\nJC03nttjT2QpWRqDMsc38U52cjZZhwN5bCnmFeg3BWViIqv8D0briWMOP1f9yt0RHAibBekNmsZ2\nGUoXc3FqqkrBgfC50KfMR6xN/x6FL5AlWa893DOd8yt8+EYENwh2AeKkNFwo9lETkR2+ZxuGy6zJ\ndjzo5s4Lo8PRy4LwtNRVJx4OSqQitkG/o0MMA7IBYUl61nNwIsr+kr+wGjXcFKo33pNSxDx7P8QG\nNEA/LfYIFCuMtNLpZUptc2upf/G4YT7kKV//QyTdqJYeDuWfF6UggOufdv9nDggPSsLou1Hbv96s\nu/IfzZDWFKAbfkJLLDPvJLLsIMz455eM2TD0AWjn1AwUkixANXDfuEj2DFnsx+w+/MKkQCG9Z2+a\n8O1lIBRI9/wmmYK5sYLT4lh5J2vNv+g5wAlHAkSWeSPJ/lmo49DHJQJVAR7hzoZaUnmsYArpuCgu\nx04WUUFnDwuaNie6Nj+WWw/U20E1wEUNM1mML21TnhQPHESYU7RyJLgPNTd0/5DrikhHZBekyr6a\nBKTuPZsZkha1M1wLsdFG1l4evtlf0Gk62+VmbJLMnQyhf/hQkYLP7lu2PfTs5aoqch0oq6efSrLY\nVxmbutIsMu+P35n9bE7p62FN4ue+V+vASZupFL0EIB5FNMM/1kV+x43/Wnfw2PJKKBNHs4Xp5Fo9\n9/5NtQUyz+EI+AmiOXvkgVZ6O81X7RVo8PniLr2wy6Kf9+vfHgmw6kQHl+1aK9/8RrstIlqK58kP\nfylzOeo5xXE2KzG9qdiBaNL7Vtsf6EIWb+cn5sdjS+dWhNnSwxYJ0g0I0p46naOtRAX848yTodFB\nF6HdmvBK1zrVCkJMica3tUJ/igHCB4d47pRlY+6GoF93YQ7weTcKFuTmgNU/UWJaWw/DQJn0CNkj\nzCH42Aktj//zRlwzUTsL0k3ZQuQGssxsOMtpq660qs9FbmTYC7Pj9jBayB8WXhFulcKtJYTPcDT7\nssVNENGIIksI8eA9IJWqAPH/fVznxUAFJThEZ/Q7Q2cwJRW2Uroaeu1HEXx2e0A19/vviryXAfPF\nGqV2dTxbBTZszRKNHzailDbhmk7GFSCYGwKlX7All+VvIX8Va9yzgyWRakOO2wr52XbysrYXp5us\njRBZaEwjtAvYtgfiSxPyTIg53r/XLWhTyeSGIA2WmicWrN54aWba862XHwPO0+P63nbpAjj002jK\nP1xBJhVM0FhrqHIkZbHEKRmnxSoDPvXP3+/K41Nz4aw4XAcDQHUmauNkKUaPuoSDSGeRdTepLnpL\nqLOs+HAWHuRKhHy/6NK8FiDdqobPcKv0RPrIy4TUMuCk/a7Ta80PWwYWQZQ29fk5enOajs5NOBut\nxkTTFDB6CdNfReHSJAAu6c+d99OMM4cVblYwlt593n/S6C4LEVkiF3us+DIqUfLXgRDtogRUQQE6\nrLhu5ueO6CfUO6sM1HNR7dPwaNXmgGkMY+0fU3poyLVlnDjyJZbMYUaetZ//kp0XmKt64y526256\n4OMZla1GRsUSAnk5tbcG9udSu+8tLG7bPW73gHBj5/o6E6VXIkO07VddBH6c8Q/Vj4fHhNq7OVzL\nZ5kV1PKX83WzqTh0qS3Hu+fQ4ERDbHm3fsA1B9odlNJlqxU7qBSan45L/XpzMiPcXLILMZYpCul9\nc6xkqubsOE04qXlY9v8b7bYu1fPgulacjPMSxY5iK0UwBa+TZri0U+KnhOldjJN7EhN21JHjbVM5\ns7dPyOE2AhH9xacUjtkncAfQ5UN0Du+7S96CdecU2A2Rr6Pk8crTww1ZsLYP80zVNYtENZ7VMTRm\n4vFxbxU0kCxUBUEfj/7pAMyXRAb61S7C1bIiUcIhkqPOIqfxuI7oQLYIAK856AOjfrHDXPUFeQBv\nLLH6C0TsIh6gKC+HRkyaiwoPnm/Jf3ElqzXvy7flAhO35BabwPR/aqyDKFMpkWvfuPd+Rpa/GOVD\nmgbFfNYLaYSkPwSiMkSkpi4G6+jhsd3bNO/y6ycTBAepgwMEgeT5rH9imvBwfsy56DGoLSDKCER6\nNoKCKGmbPjbkdQx5vnHhVVUVilAZ7wnl4Oi/9eYf2Rv0I7ccBiNRWgBhuTTeXGobyD7wnlY+5SbP\nFu3MzZz2ij0z0m+VNVIog1KcU+sakXox/4v+51odedr3c4APVvOKwOD1hvIvefgmQ2H5b7tCFvmW\naHK2AoztPRWm37Wde10lw07TAcccRC2qQxpLVLz3CNSqrNvXvk3N73JzUKpfjrnrxO3y0OKIGsnm\nPL/N/bcvOtq8SoQghSkRwQ8FmoWQV9qK5mHwbWB1REzjaY7H4hhX34cHuSeFk/K0ZwSBkSdyjkkH\n1gm/DDLyI0pe399dBH6Jm01u1PQxFloE5IRe/eehgA/2ec4McrE1wNeTyFAXu/MkHq6EUNxxi+x6\nSe7JLYtj24A3XUtLB13zhaet7yX8zqRhUCRw0wUhZM5U60s2/Lplut0iRZ1artg175UvLaMUE3gX\nGgZG0jklMLJ5mOwv3GEwbaLbS4gfcE1ItERnT2iP2jCxMZojDajqonB9K8sTSDBpp+aghE+zj8EZ\n8wMv6nNd2vYlgtrYrhEdJ4eCOjbXVziibNbovoTbl+BPSmu0wekBhaJVT2DibzaRgqSI3hQBEUeF\nvdHw2Rz5hB8Qwx7izHwq66rTSorxFDC/DugWgLmdlLr6CKwT4872+BQ4MHV5A8UPoLF+FGQ13u2G\n7D9/ZTqi4UQ1BriIYXiGenAvW5o6mtumh0WAQMaQYAJ2gdn58yPwM4zJ99NvgXzeu1vozPN31EFB\nS13cx7gPeEiT4+u2zmgaok5RJBG9TyJzyXEMyZauRsyLM0cpEzkQ1yXsIp26gEK1clDsm7q/9J7/\nKZnK6ASzAYtAR5hHNng2S4IDf8RmIyriGn4Fy1OmGhVoIvuGtDqZWFUCxkfvadXacB3hD/HmMqik\n3Vx6M98tW70euIqN5p2hA6YGaTcNwwqOlkRFf2Rz9hvvDbSu1bEy3B6A/p92hN2emc3aiMW2ygYJ\n8qPmlhv2SVT0DlnNKgyzFIs1+Bj1yItqePmsoELWQVdHRQGSzb8qd9LRFbW7U9fKZ34tnGfARPyK\nwWv2zOR6kCi1JGF62YLNWfr/6CcB6m3okv3I/5yKmDFyVhM4mRTCEDcQo4zAu7PE7sFvYz3pfoeJ\n1e/hbBXNQ8tlsoIld8JvjagWjIheFFCzK0aHzpV2g8OOb213zmw8kNrzhDHWaPa+pjQC0xn9InkN\n2okdy8asOpBbr/dtQcy+11wSnOJxFzwRzbtM+DD38UQ9i4iQ1L8KH9KFW+p6uCavW9tCkWn4qpfT\nfaZo07yEWyuo4ayn6Ni1XFrqNc3i6W3g9Mpfk/ZnEKrch68jscOcWwlGjUJA7OaDNWxHVheyRrdr\nGyxN/r/uNkxf63lc2i8rGNO0NTjGnyOkq5ecjclrzVAL0GBu7x2Rte/u2GCXB6i1B2C6ZW/CxW7q\nxIHaoEQZCj9nDyVsp7o3oOVGeBYScI680baRC/a8PVreq8xwPvWj2ZNwGzkkJnECYQ0IDwzKsXgT\n6Z/JQnDUTYbJBAyHWB3nss6UYL4Hb//FsBNjWLGGwibHWwxXXX7Jtf41udjima2JGJTLH79TSn3r\nMVDh/48IrkgBSTaexJjlMEWX4sasj1Q2m7Ub4mOmi34cKiCNF7aK/cV8sjNLhMGJKXomqM0pzDGh\ngKHmcXPCXRocZVEBI0kNIaJr5yHVZk57HSVsfr4T6A8EMqCXsMZfZRyGbA6VWjeRppvp1R1xrh51\nxhmNpkc6gxXZdxPq6l7u2DK4kinUFI45XuvEEz7l1jiV11q3Jy3Rj9Iea3L1N6oNBxyhv7LmmvYi\nZkw9aOuBwMBy9YI8O//yukHrzTuTRF/WEiDR/KZB58O0oiqQo/kSursC8aLBsTvBQmztnYvWcGIv\nFDULfaU8K0qB/q1FAhmNe+7C/cSpZ+LSCYEORYR+uEfT9uCRclGVa6+EuF1/DX7SJRznk/Lf446v\nPSzpA39sirtcJVmOGEEnP63TstjLCtCdI7Rqz2DFoZgRdj7vmhfLqX5vg3/urO1Ako6RZo8dbjky\nOPAcdGnL7YP7cZFIvrFvYkX/oVHNgHcN7HCnP4H6o6t2NvN0teXSR43lW/b+7kWLHaxHItVjxjrc\npUezudhRGIeveK8/RfdfEG7cI7yvh4TMRbAIKnJ3QXT4CfmfQycUkL+Fjy/oLOkkUkCe0iUblQDv\nNpE8QwIGC5LR7ykQ7ndSqCdXCXt8uYQ0vU2KKRiF2Q90D0YpqfFUndqfVBanpfEkJcdPnWbK+Hf9\nnL3Em8JC7UXmlVgBmKjZdctJ9ncYydjNcg4Uw3CZMkMI4FJ/9kWpOMBKQ0xBTrfKnYLPcpVOnMf/\nJQbKWteZDXl7gsTCuQylYjyxtYiCO179CBKSojvUWPlj9H8ySOnveYbr70ZiBwvhBCb7U1Vp5FgN\nQsFmn69hARzV9LV15XCV0AfpmUdKiO1FbKo/yEogOQccXEGjjpuKKDaD1vd9OvAkoQtT0KDVeq1r\nryUvmfLigMbGvMQnXjsk8TWkYvEziAF/GVnR4ccTI7FjCi8nWwjIDOPdSBmEjFORRo3WbIiIR8Yx\n2C0SmrIoYWK69Xr25NcLMbY1kRTS6AtlzazTMh619fJSkw3mYUTEUJa09cvvaf5jNY8LAUs5s86y\nLkyWr1Gj9TCLFu48Ub+tf3ty1mp/vZMMypc1ipM3SpsYfN/r5AZzX05qm48Y9bAx0LryhPgE5W6y\nkrSHZ8WItXXPHGIDzV/45oVP8aF+lRdqUhyVH88gFhe7PzXPdM7ppBpmyqxE5DzDPMdMnO2nrs61\nid7bGwHiYbVuI+kGnvVdq3ZOusAwvogzhC9oD20WJz6ovQZCAqZwDH4P8UWTQJ5YRl0fiz0ojmsc\nXkfQ1Uou0cbWQ9KjuWfcicfy5RHaichR8ucyyoBGUw5iCdKY5A0TYBfMw5/J8Kim78TqQ7ofcQeG\nMr5RA5QjG9ONQ6ZOQG4f5hjpZH8pp6dJwwrUXOsPt/R6lJgiG+YKXR6F3uKAMvtpTVYIYWLokgET\nlqeYZ5t+hd10qE5Sily3MIubkGQWC/lbWihtvKAGspkFgmwJyIPtmKrRQzEgtUn/t3QYnRmALBqb\nrq2YyQeHQ1WFSgcRI83dJqrHy7wR1uWScaUzHHMHfnjQnuN25u3hWz8vsw9r5OXIJZcCpR2L/cKH\nZBnE9TZ+P+jJ4XSWdRXuSEzRN4AoSFbWW1NQY740CfTwSM68M5AEkRGsGlVHO+auJShmzdUbWPQW\nDZeeEw5C3INrUNnosiR7CbAyBoPY0I9WVfXs+dAR7GIsBzHK+BiGnub1hvgsWTqNGouvjQHRXIvU\n/Wdynq321k/Qjt4iRyy3t3TW9xxaI8lqJHLZHVIt4ymQgIkA7Xt7Qt76Zj1unuNw8qX4DrOQFZym\n4eswFSsikZX+cTjQ8vQbFHZRWAYO/RzTqQB3KyeNZTJaBk1RtYqfos7pFRb2x0KPWuzVXuGUn3ru\nb59njv7Mr/jAgdOKPCsgveZY5clTdCujI75SIvx3kprWefN9KOe650TEvbV00snvEJw70Huam4/P\n8eg/ELq+LXXwBJoprLG6kENosZ2sYs1A7cOcUfjjZeJ+4vMCyJDDKnbd0pR5jWy0RFCaUk3nlawf\njEeaXbb/TEYUuqLHCy6TOeKD26YiKYT0qz6q0Q6mYhqFTRphjr22WCCxW4npfcfCD8UpRWiI61Ir\nNHkGvUqBvS4zBA0dWuyFEdjWgUy9Mm3OSZbWZHI/Qk5r9SQpwWMjY5y09CFnfBQC5sRL7Cy3VYnU\nYYg1A3Qify3sEx/CtWjpfTtJjP1nYTNrG4skeyQ8TT5mLqW3sfU8d6sIO//V3gdI0jhnjKmhlx9e\nWx7wMglZoKuIzkr86BVAeB2FQ1NuU63/FMXcw9DyQ6RDwY/UGmocBbwZSkscYB03x5Q1E6me6Ky8\nU3fyS18P/vRpA25ppswXgVulU48BZk+vHKX3EeFiPpaCXxsiH98EQs7c1W6YfckD3aRcoUz/qAjl\nJLxGnp4jgznDiCXokEmpysrxMOX6aOoDXOyD6tPWWp7MpO1TTC2Y7xUx49nehZ+KuLTxm7ggBuW1\nOYD8B4rOyGh1O3mp6TJwY0gATMUaeGwTl2WrYTW2Ilx8feJ/m4wp7YM0KHNj/GufQshpfHuDnFoz\nN3HVAcgLJqsu3lr9CnrdPy2uRR+YaEPs7q+RbkwsABftQ9clXj5ktXvpVaQt1fc8SAhbhawRByyW\nLQkO+QuuS5maFnqv4h/hc7V6jRsMmz0vIJYcPRwNIo3wK4+Uihdgt0AWfBXT9NyJhT5qM7t0PDG0\nhrrobCQtCGzoVEYlw5shN/IAzMUbC1jGcKHs1Wwi2Q+ieqxnE7tWBhf+PGGIC0HHgQ4pGE6d7sEr\nPSpVnBauw4ElYClsTUHf1iWIhiFpz3Na3asBupvSZ38XNisttjxRTE8Xx3BlhwT2IGBfYSbiW6cn\nMc7sr55EUMbbaaMGdqYPXesFogGrlyZ+UqbySfFAPQyz75zGkRoaXsWFLz6iqD1RXBv8wrJp2yaT\nlQsaLIZ41uVaMHGlXUlawpA5xV9wEIdF8o4LlwGX1RCUMAKwD6UshZX242Ry8feVKyaPvDNT67oS\n1MplKvakVMEHzFQPDE560bemzItxKC/ZzCRmoexBeU3z+Hi17QsHyu41aBY0JO9edGOJgi7pa2+y\nya4dfxPoGwIeaZWwzAQ/8uMkVUYmMnib5rYR4vlwf3nt39zFn9qQQh0UFikd745td6CkOC5CbFlY\nNDUljPKwUh/d47pJBjuOsbrFhmU4V/XS/FHeqlMwZPYTdgiDA5C0/KzhlZS1fkXgBQCeQOcTIy9t\n6S4zxgyJVhBujrV2yTNGrQYZCpPxImNsLH2n65CCf+KxvqzigbC0TyCd2Lw4HTdqoHOFLmZ5TdYq\nKX+hFl0XXeDstz0bK5aT0Uej85yYcWeJMvJCuOAFF4oUGnh/IDEhZOs6jjXSH1CQ0lscOtSbw1Gm\nWt4Nq0vZiBe1pziqsv04xc9O0sMrYadPqd3CwiA/ZBcjprAwI6Mx7nC0wFeuJo4w22Jv4Aq5aGK3\nhCr3bF8AhyJnNjmaqhE0YtPtSDTIHkMuIHnnjgz26RH4f7fPLP4KdKC0SpWj9V2wq/Si8siH8V9+\n7XWItz344Eg42YLih557hGuBAfEZg+IlP5mSQG1eyTIagzZNLoKH2LqhaAl18O68A19azHUNJGYo\n8bqxagNFiKY9z6F5XUPC2Szb6YpbqRJI8ESK5nZu7j6By87vLdb2Wl9+/xsyAEcibOc+2AOIejS4\nfKalOJ3GKB2C/IfD0WI9MtaDJMkscCaqGnZjj3KFoasy15BMxD8HDczyKClRAQWNSWeMymJ9U3Ie\nXJpEuJI49raHwjS+jA4xYzkFgeMiHOZ3JgJiPsmkUYKwZibmCW62PMETf6gg/D+kDSP0aCzn8LIH\nIU5izVqD3Flsn3apVPtU92mZGK5E8jtXzy19fVXTaEV4IsOYtMKtNPKVYB1WIYRezMLjHRMGlNM0\nyQ5xFuoXgXZawCz0a6gnpCqL1lcjVPFaBNw38xQgK6CHX8ZjWsjQCjmvemqWTcVhUuqU05qM/nwq\nHHUJ+OU4WLVYfsJEyMIp/4TStNfzYvAHhT2J/2PmtH4NAFpBkAlFzXBFnXStfRqkNg4jnOJE1wwx\nY6j9eMctoMvOqpA5Di00NCDLsIwBC+D4KnbO62pvFWfUMq0gjeeFS6ZjhqvZeALgViW6b9o4DlVI\n9mBn0FT/mDgrGZaxnwhUJxzOC2M3S18e3liq4ZTuM+Awkd9pKecILweYwSzRISC0kgrKpwkMo/UW\nPJB5PXHEh6WK3l6UoNRbA4xo8hVF7LMXkzpTXsS4tkkReo4jAajbFKlNNV2PgqwvbYJJyDhlrmW+\n+vaxS16F3GsVBYyxiXWm+wXGYH7zTUJ4IdgJPFBzzKtx0Rrs8r+EGkMdeTlb6VeKFIIBnKAykIjA\nbMv2bt8/m+0qz8tPfsFouxvyciTz1/PKcUcKNBWFhP5Bm8029GHNREIfnYCK/WFhhz7ne3FjmAUh\nlR2dBtN5k4HvqmBSWjPCQlUu9OMSagO/xQo55hbUhjFnWrH5q5Nx6lIQrpflk/KuD/2GTkbylDkW\n594yZ0EqKP78k7HpMeyvSX/CvyGFn6w7i+AxuXh5B9OjZj3P8L1nTzT7qZ39n+QIFvcjr1x5l/iW\ns/s8RsQN4BCdixoR1xtd9kZCXwM1b3nBx5C6hI38vjiwETm7j0ZutumyXqa4Hnqv9NzvmLKMPMTw\nVnGngUIkJOGzqAdRXIuzKTmLdIoPsOqUqpmTfHqyLABF8eb3YPL+takp5Qv5eN1E0VOXgae4RiPt\nGwPvlhMvq5PqX3uAOnE2vK0Jtn6jhO/KuEJN0IvDU8m2J1yjVh69ZKwEJCJMaB0Bwl76UvgAoLwN\njS4Ka1wMrYl3O+McaWK6FI10hST4tuyeigunmrQJc7I1mnWKCWwcBlWcpVGo0jcr1kZYQ2iTaSNq\nrLRDZGDqG0ol6yCO0H1z5NxWVtBPH5yGiFO1Ri+SDilT9D7eQ33ThNrQD03niWbK6+jjk1QuRVLv\nD/ke4Z9dqc5hK0oVTjFCD0I+2GbNRXbQKaDRmYhHADTo4d2h5kOGjci/mVlyXAJTo0zuUlnymUIb\ntDb97KLMlZA2CaDchzlmsbIdLGxAmSrcK5LHVbj6yZGPB4tASKDSZQlQNn9fTWGKLfK8eNQQTEFn\nvyUqWwljFzjVVzk6MLcJLr+bwab5hIyWkHLDJCJYBrKpr3WmlIcOsO6WGnFFicNwap06npMc4mEV\nM6uB2nepjmIAYwcncCkuJER06oWtHNE7Z9aZyY2n/H7j4gaRIIaQEjLvIVEuGQA6I7U0GZHEoz9N\nlplxmQV5nR8TdVqTGegeBt2U7Nw437Xidug9AloUs+Gg+ZEQPFS3bnr3UONthVgWyhSYU+EVj7v5\nTYNad7OAyGNe3/XlarZpK49slsV4gvANtoiVW4xDbpTcxkIL/cYl3Yk4e9xPssIy9gzd71W8ZIa1\nSML7pFA/A4/sJAcaPT3vn69NxpUob42bH6m93rNRKs7RT2xZSEkJWQNqy0aG+Ok8koKiX7RE+FGR\nva24oeFR6f9adkAZuuMrHm/UIJfx5i76c1XSvp/oDXnrX1M24Y9j93RecqdTdiQk49hqoZ36D11/\nHf3D6/o0aiYpf/iFE3ELL5ejWQdtGIrtU5OiwbqVKiQ9Slo4v1tyz4S41bWoNEmfOih+yoiztE28\nocimoOEqxhEtbGbijqS/liZABg2KL80AzOhHKYx6Ubh9jaTfPIpqxjrXXqnYmcBVqMiNUOuSVbkv\ni3s7C/Lpg4PasuvGUBrZ5H0wHEajjSXFTC3uIqxQpvKhvta5GNaizQEF4sP1SVcvt+5K7GfisVUo\nctd7MdhVRuip/Dzp0MUzfWK3jmV+wzlBCSpYNtpIvckV9y9qDCtLs7S/vlAmR0tK8kc/jlJeUb53\nFt+ldQjJ6jVAIDSxH/OJRByXV21WgLAGpT92FoxKve7ifGeRQXW2HiqJ6ak7dEdgfOGPkUSaaB1p\nA2kMeL3ycbBUvtGcWzM3mqqJS951LSvFUNPCnQg546aOh22uKyUnS+onGS/4rCW3EQgzFH/xjkV0\n0jQ1coMVDFDJgHTzksiS1REJtluadzeYN5ZzccRKvfA2fOANWO/MeHMcn/evT4S0dimNyN7nGkiL\n4zOmqtplrpb65bTcYFQ17/yiRhhqw3G+ltnS2+a394x/ucnWR0RInfBchpUjr1DycmfTABhmeGvP\n1B6aMmVPWX3ro83gz3kPa5sTbZVyJBHPzfuI2ljjQTWFq60lR9VtvMZOtgtZWRT7iMV3oBUORHGQ\nIYxIuZk8alsz7gfoI0Vd7M2LDsLchQdoqOYw4a/ttCoMLAcDR4PG9YgBmbouxOFBTgcNBTJeX/m8\nWvi6TWc0X1Rc5Tr/UYRawf58hIWk0akUc5/iguHWPW9Pwh+1K1uUozgo+hy6lr9gKenGZv+4Hfze\nsRlunCkdIH2Bog1LDN+AYKA4mqDByC+JOfGfdkEyyxSRdhLgfH59Ro+iq60NBVALnUrFMQ/PHOIe\nH5swpu7JviOUqQm33VwiCNko6EBLSTB70r3MnnOz1cOllnjB7Di9hEPvnOCBIH9awwYVg8Nl8nz9\n2/Mh7RLchV7VTj+w1HpQ4eYY1SaRaunHaXm2g2+bFXkPjiukqhS3K1oVhkiC7I4zdRGqvVcltSRp\nUadtOpkvcda9y0XjBcUYdVL2l9dtWAB9zfW2nCeXbo4mkv4zcseb1Us7vhdFzmhYbLNjVTgveVaz\nBEuYFq8/0mg+b6SbBMcWUdqle4Oeq5Mtm/9g5RCM29nNZ+gbo39Drnaq5YjRqWM1SxuUoSD2w9i2\nBH1SP6hAjGoe3k1eQ6NgyMZvERcoHtVAl2Lb+5gOMi04ZzD3HiXm261Yq+ZkpO+d/eoG8bNQw1K4\nfz6WCHG136AqXxU9BGq1fpLqEJkrRCUIJnYPanKQZ3iO1B11sorvP2zuc35MISJIw+uUyn344Lx3\nyCwng6Mv+etOjBopZULmi27S35iQ7z59F8wItKs040Ky5Bm8wUcbNFh42WoJ3vRNh1QzQmAL7qeB\nCeL6U4rQF22Ts6SlWOd+OPdpFxY0Al50g/Uacd8JfZ1G/u1KzBgookPC5bkgdQDrPeKH6iIyxJBE\neK+oTpcIZZoP17vjgcPUk62QfJvB7vcZpnByVrCyFGUsLrXVz3XIKZ1aKXOX13PV8i2EBtJAnQ70\n9rZigFSPfTKghKH3fBCjUasS9tKONsqcqHTrrSVJL/9u84fGhkFA2AMmoEDWuEQ260eyZRwPB7IZ\nW1O1LqD2m7xPcMGLX5fNuSZmeFPSq3t35PI1VJ+/EjsOyHsPPyyqBJrYNXLiXRAjmwBPCuYpyYrB\nr+Fwq9ThYXdRCeeXdzA3rGebNwjDeY3Z1794yPpikK44Qpgmpjo1MI0619GVrXnxRX6ITTcC2JKh\nztufb/FbIv0mobL07IaozWKrQgW1bRef6L5TBB/h+9cMkvwqnPTDRatqo8sJAdXyHzPSvMl5rS3M\neq1Lt6DzAzhLJrbpQ1ehxscsZLH1YpDtxZMZ/CPhR5Q7x5CramFFyt4HNlo+xQgba78Tp7bp4Jne\n/xDfbBiA64kOfT/kREDx6hunBqOzev8tJpMZGHN24BdlWte594W4c42RMAzsVzmmlMANuYc+nJBx\nnQRhGuKM7vqH7cddW8u+8WnCghPCMdTFuYJWtQzwEyGAow0McF69xeQ0WWJZaNnsy34i6isVOJY9\n5S3ZK06GzPZmaKNIo54Yx9zVc61ANhNUCirXchCkI7tVsur0mq/wDIZxd7uVy3RpgGchmfRavl31\nGG5ZEYPL2jcFLW/2SZwDy3uXIhEDIuMfsRiXn58D+2Sck1ejKimctn65m2n1TrFx3lCj/IWrh0RN\nPSurqYQCzp3cT+ZRUB4XAt7ij+89JdynQY98gE6S5AsnG1IDQlGnvKDhd/P/LaLYs9JPJLP44hSd\nNMdICqBtDak10fv+cO/TTRpo/lK1fq21/j1UUFLHy/Nd4e00g6v0+C7bJat5070IKLHxgQWOnupk\nCHNFsGoDoF1DFLIJi3ltz+bXTDmSXlvHVCbjHQ46+QFoZ+Ricb1dJLMvH5x0ZOPq9MyhPnSlWGlt\nxMNae73sp0ewyTBb9u9Ok6q8oymJFF+4cvqRD1+0O/RVWjLrU8Z113G+xG0BBNRRuRdqxkLNfxjT\nVCPC4cdDzLyKKMzmfJDIGwV2BssiJYgJ8AlNhRTgUISsRDcXyE/Pl4eTHKoMzOk9ICWW6kjIn9ct\niNT4W4e1VIMzNfMsmXDXEUFWX9j6PHpc3aL37D787EE0L2RnJFKqQxy2RwyhIYks6lfsxaTXKo2y\n4qdVuZNZXMDFSYCq/4+KxjlEzqjreopwe+HdG0MOYFUHa5rUShVTTj4RdYqjnqGRWxWaxcRJ2lCl\nSEnSw6HDUGR1HT7/ZZrnjwvWQbkEFB9Zw1k5+bNHMM6RUskULN248yXUGFKc4QV/Q7TCpIAIEwN1\n3UxLEP8x5zJEgkU1tD2QU+x+yfq0gfSytlhqdMuaOdcd9aWhV/jJW5PDN0XFZ5YpbbFzOvVvhKiH\n7hL1h65UGOOehtFVNhX5ZljLrFWu+J2P71uB8tOnQ1gazSUlSo1a9PObVGo6kj7dZ94MI9LpGWJU\nTWfpg+P8CBeeB8ShslSQ4/KEnpIJxaSIO0z3vpRGHB4HFSENpoYbnAsf9jcFWQ24roc7xPpK7YAL\nh2kW+M8eVt9nywYzj9h9qlVxFQDNu+wNlWvsStpcVfLVJ/2Ep+KqXoHkuJTMn43c99/VFo9yKg0D\nX956SkRbttAeqSijW4d5+bV3CxsdBn9ZuwgoLo94vCGQj2Wq1teGy5IYaASs1yd/paE6AwvZIBBQ\n23ch61bP4ugWiKrWG8uk1vcFuAOowDn1QjrmAtQPqX89C8mRNnstGdqQ6izAku9VQktbuyipUvk2\ndg4gmM1ZnUxeJ/aaM3weT7aIpjF5x9ISnqRPxa72i+Ni9NPRW9q7x0nIaHU7sOtfx2QhuQImC3Cb\naM7aLt4WcSkRCYiFURS93mVtNXJJZX/OF/M5a3AAJkOC2yyl1iyoHoUPzemjwKOd8bk2gkfpRZi8\n4gC0QYCYM3GjL2/r7sG0TgJPj4jxqpzAdia53+LqHd7VLVBgnZuWwWjF+35O690BEosHJGPqTDGT\n9Tahp4qT6gNQoGG3WRRXhEFHcmreAHdZsu09dzz+fZvqbeOpT6e6nJhygcEKXbSJreq8aKzgXZ6z\n8BS9HX4Penia7qMCKwYXurvSfuO/kJ+RsOHgiUzqD3npXKwpy9khXXqYHboUHdXzIcHXrNLo8r3u\nR53xLvbWkJbCfESnwUXDbpFhUwhg82Eh60BkOh3LWWKsaHJG455cznRht0ku5uQvrgMH972hWcCx\nQakS/D7uagQJFdfmHM9mYGXA0V4OJF1v/ijYP2WDWepDQoelrWmg7rEZTi2AYgIxFpFfvT4ytVEQ\niahn1B+cEPOsmyN5zw+nU2bhTGxMx0HFSh4bd3/FZZ/aZqKykXIiOwO56V/35ZGXCzxJ9fhtm17I\nI8JfPG0lPa9fAAlGU4sD/HuQcLO+G9arNeQ35MdvPis8yzXQbRLxdYQPWQ97o/X6c0ebwn8hE4Z+\nxVmZeygfX7iOP8M0gonWhHOIAuckNjYiWcwpVevHYvonSlUf4665MZnYhJ9pmm/N6H9pQK/XR2mz\nbrn7fw62fglsxvdY9IYgpkWkVUB+w7nsXAf+kVRGSnP7dYAIkFzPseTcfYlg0azVAMYct+dblt0M\nVA+OzvoDU/yyZVe/O6WDlfg+CY3rcPVNlO4N4SMnK3UvajK1E9ka+z6LuoJxjcvB0YCUpyP5xQCb\nFCtpOmBXMnG7QqG004taz4g0KQ3/a8H5yizI75HtlLZHyDxAL6HQM1l7IVvQuXW7PcilFfxw0qom\n1UF+IgoAQjbXmwAgQfzsKkLu+iw5bGjCrrxhgbKMp2E+jt+UmNzij8D/0Lg0jZZaV29hmR8wJtk2\n+hP7q9xn/1Wq5piKVWmlAkJAYHkoezTpWtRkB3fC7V1WKIWaE75mkClzxWJZ+YgwnfUlMiCL5ax6\nrGFX5IMzQvcQ6UVtt+MR32isLoOGslWqIvtsc+/3dlUZQEbSmKK4hdytznMVyvxmFBlAr6/7eaB1\naTDm2pYP5vMVVvmM0QQVgECbqrVWD6UrW+fIKpNQCQcZ7/vwZzOLXkrjy4LRvgo8ywj6U973X8td\n3UZ5uJ5bvxPNWBje9Szv/by9Dbx94g3PDzbjK4xGsTm5lWi3mW4GkmRyZVySoTSckVYV8uSHJG2X\nCEDNTmCLDh9raJ2MX/NqlvBgw35vvzSpGkZyVFrU4yo5owUqEq9i7YDGPBW4PVLe+scllKHJDaNL\nkpEumb3IEpH6IMp0rr0ZwGm4ZkIK9XbUeu54fW/ks3psH5fhd6EENV4zu4pP5Oz10LbnuCtTxntL\n4EQI0nMGx2wzIT0MyiTEgsXhqU6EhuaAsIQ9dCgqIsOvt69JAOr0+RBCOnLN/hvmZ8q1quPQaYQ7\nOTmNc3z+bYpQHE/vGyIznObEqSiTT0XtujtGrN8Sw6bEDt7wQEdS7HW+HPCdIf+7OOn3v+b47Igl\nBqdPS4XlMYCoC8X6l/QTeRcrc5sELAMk6gPl0ZtHYqqSx6Gta1O/aRwcMvtNosr2XzIqA18VgsfQ\nTuI2WSVzCfVAm0ZgC6W9DBfG7G02Bg0snLEOpxSH7Nu5v5S4/a0oykPXDAf215alejFu+vUsuYar\nVgfSrk9OEV8pCOf+VzgLCwsg0VeMVFg+6ZfQT4tC1/W1U7qh1/xKmD/CnV4H5LkdZgPdj74auY+Z\n/jndrLn5Ob/csWgECWb0zYoRQI8zjCxYK0OlNDtrC58Eax6U70azuzPeYSDEMCXBwEe97LkkhriW\nHnHMlBdIL1eiWuVdevC6ajPdwmMoQ1La7+SHqsMB3ECZupjxl3JfFvib831nceb99m6JWWiXlu8E\n8deUV55axrDLNbPx4V/eMQG2tWXPs0KS5k0zpzGOH18/IHxLRLmIaYhxCZw4q7JOnqfO1xOUj/pb\nCCR08yf5RaEVITEOT+ujiYOENydkEXF7qtFEv99E8fZlZ7XK6P2BHINLAHBjpV9/pcEytS6ScOEt\nt8WEzp2N+WNqd/GfDXMKc132fr+6h+G9aE9dh/cGQ07gkREhfzD95JXaaTqwKGkpy5UEOlWdHx1k\nG8JnUgL+gUz0CCM7D3m50QRcboAKgj8oO8O4kgeGiloOneM+xkbGCoY7mLbzT2vJLgr401g7oE5G\ng/MtfsiZ/lxIZHHp7FAzuziB0q2tzZItJ1DMmHJEm75HpMG4VkCGTCwBxeLyz9G/3OWtpo1fMyJR\nVw7VY28M1sZtA7tKi4gbnMEgDtcverge/nmy7dnNEU33bN9lnOArF0ZNYRbw6c2usWYGx3MXiN2y\neNyOx9gA9tQ+cLMQCLETcuEeHYm1XGdPdRaxcWybyJdtCrKGljUG/P7Q0MCeZSCr0Fv0ksEx9pQE\nkxJP07wl7wGKUsa/L6vx4zgDZmFWn2oZCAxXdbQzTqlng0AX7D/NQJYQt62IctW54+wGKArPox0F\njcd26ciPhSh5i7SxsjE0dQ/ryqqKj8HvNFtT3pkiHtCw9b1NeMabod6gOXiCC9sUJDRZKNvY3RPi\nUI/A8ya0ySt2Nu7Cucb4+xTTGWBCP+y9I6LlhgLfuYB2Gl6HluwJcSM9Cdr7fpxtdFaNt8n9mRE1\nXtyLdtEuw3dOfJ/IsRbTNqe9+hkzYlO0J4+XIpGL8HO0VzSm/zo4YtHjNUmWNPUXFmCU+eksJthd\nwk5mE/GjcOzYQtiFDnKXRbj1k74nIYh+MCNDhV/iOf4zMIlobirmtHezYTBlA8hFApMTpyNN9wB6\n9YswTrbeJMNKrIZLz1Cs5vuzJ6as7XeOzd85mZOHPSKyDGHVx1euEpc09mRvu/eTpU3nb5zlWewF\nEfs4AgYtTqEiUhfDEKV/teaySYGSnpAJQKzE46RToP5VWEb/9MwsuA/C4KJacaNucG+OPsn358Vy\nwjLoQw8rF4VzYcHzBQ4/J3SJR8jeExtTxoarCl9CD9tjV+cHM4rlf5OIu2fsWg3sHUzegpgCO2xf\nvCkKrxSNRc6QzXLnMjLoijxTezY+nZ7QIBBMnf0FyxyeFpu9zlWYiEXsClwhY1sNbwlmDTQN+ZCf\nwk+mYvKIarcgPceOi6B2kEH+PcXQorAEm87PozNuflw3mnN+jTa8688Vb/TBO5lOWyYTAkstS9MI\nDxcK3zTUag73KobejNjyllc/F9KskHxWe3SxnTqrGnSexOVQFTa95zqT9rmjAy6JXE0iGx2x0z3U\nsyq9geKYTWAyGUEaE8raXliwNKskf54gcwCluZO0RIVZrS0JkD23Q9uz8kNkTwBfWwhY3vsugLo0\niN8rcRY1EWsdyqgaF0Uv/8mnIDgRbKzs8KDsdbBzmLAiunM5MFKCbLFZhGVGt5HPIjcOLAVoqZnB\nMRYQvdCZT3+wjEMAW339Cr1qfkwqkcrmN4KRXON3nx0cglU1/qFo61Na7YgjceXn7yBc6gZKGS/L\n8sgkGdqBSsDeSblpnhtADssU/Y59zUGAffU/Hyx889W0Io3d0tFblMykbVHntoaNR2YqMcRNASVy\nI3UrR1QSh4c8b3DfQIDJfEbKi9hM16nqDUPrhyL7/b+vWhx7gJPhScoJbaZo9KeNuuH0Dm0fDlUK\nrW+tnvUzOau74t5JDPVrdMfaSvsiOyY8tHQli/eHoN0bIOH9WR1Pzs/H990dUIx5U0tKBKUmG6w0\nIIB2kUAhRKLT7yLzeixqVysKHGe9YqGRfxrjrUDd9JAsf0gxX9k03847NtOb3VMQ6/w8TcvotBva\ny5J+n2tLNoczlgTCKA8rbFPG1okYGa9IBS1Ob5eiWehcJQSF5owlIYM3ExZ9awQmotF8TPi+aSwV\nN4pbqMW7EQOH55U/CXIyDA9vbfPkrG0nBGcTfkjjDknwqcrsjopnhkRR4lqzQMi3+Z7bNn131b3f\nMxx1S39+0VoiGaXirWHNdJPtykHz4Qypk4Y+kNEYKW/qiBr1vTUhEPDLuUangdD3zk8cCoDxW77C\ngptZGpFyPVqq6FnjwqeSYfpC5V3zAHSdeSx517Ru/9M41W5I8JaQSpJXvxMLjYbzhvv33WayPIbL\na1RrW46a/Hsq0u/jX0AVyk4XJhI9b1lUuE16YeBi9IYX9tLy9NXFcA+xc5WNLHheY2s/EnzFzRoe\nWH7dteVHJvMQuxaeOGpaJ7B1WBuA8/INURiagHhfTLp02OTRj5c0/8Eh+YpiLIPBrxHzSztBdhOh\nhbFEuKV3Gskgg3HFWMjxP0oJaEXDNVSH3hnJ1ETtNdI+6XJk5oKQVv4p5Febi55JHamaUeZ5nhOR\nl1F6Fl1s1WtDuqHXVZXTz32eFJA233T6uRRbTZvQBfBOwtZSz13Q9PWyVSOXEDhn8qhE0TQJsk0z\nZq2HL5mVZdLp1JuCy3+gtSjo6xNQoBd8plXfwih+ZZxrRBpad3VvaxmQzeLteZlXgiBgUau0zdlX\n02aj3zlE8oxxcC8NEb3Wref/m57EBhlYogTHOTBHxcqZfDtnLnFndpn9Q1coyk/DFUruvw2pq4M7\nrpYeeT8SLLeZXIn5EgRNqNFs9174+VSOfQXJ9xKIgAxRvkD+e/CYIiVrc/zZQzlgbnkALLT4XRos\n4DewLrIljT3gB+o+yRFJK+Ar/jI4Frh+6/5xBeheuXxMR0EX9FMVOCnp0tJmu5Rn3705dBkjAN8d\nZw4X17tJdHy8OkJQtuqTV63cbn48z+6F8idbsBSAMJJIVojcaLbLlfuaHiorepZo6EJ2PYdgeqxX\npMnusz9egLIwXMQGooLVsw5t8as0qJMGT1IkYuUYIdtkiNiXJe2U7BPnhpZZZegZdvkZp5CTpZ07\nt3pGAYoGBw9byMG3ZGDTMYzjD2pnTT8Ny/INUaZPzZXrRj9KEhpY/JURRSL+ElmlSq3ubS6s6ZGQ\nNVCHmWEWsa1SjariC4IZ0+5UIOjm3Xiru9rvJ0lW+6HolUVrrAITnbNnGbGpfaq2qbC0sQwVDhYK\nFY1lMQDyHTLaJofJcW3S6odn5iE7tp0uLGFLfIM7VZxs0n/rGfIOcDCon6cf7dA8w1pGDs/NH1IQ\n9jbsorMLfiof6Yq3ZIKFQ4goPsvgJMhBi2lCqb0IIxjcSbvJDpGZA8c4mzbmJJSJHxLr3jXxZx7L\nng/VujOYxK6N4MIbbpgbgvJ6tuHqxviH3zek5NPGF+uYoZF678pGRIM6p+3JS+nsAatrflJEWPBp\nn9rwA3mLDZYQJVibZwKtC0sWCbLMS8Borqa9LHRYRS2NHjoxmYmUsrINl8WRbRw411+wKO9CZrSF\nOMJdIGzprhXuLXhq7lCs5LhM1gGJeEM8ogKtkEBhCJgpYWFyFXHJIrW3wP9PJCDo8en2QosBj/DZ\ngJ0D0YihAOxtgx4TP0OeRTEZFzBgnJd7/4X9YPbv9po6UTCkHoQu8b2Wf15EipcYPsf0TrycQahB\ntjepnLzC3NsA/GRcmm/+gEaj3m9Cif6rfNoiM/9JbD/70mV1cnQaeJtPThWkkdooF7I7NkOByx7F\n6GsMNbZRDuMq+rdJBh/d7vkFfFgDNC0pf9HVvAvl8ia30ruCTd8aFIB+ZQIcwaylzR3xpVQQRGrN\npAF70I2BR2B3XuV0Qq9lown2sHEJhINlcQBViZCWMz6yj6FboSy/92dD+x6OAtjor2106NcAn0C0\nb/wjHswKPydmqI7/zxHr2CtJVLG3c0ZFvuNnrJTmjmrueDKB5qck931/1u1xLQ8ZOYxq11n12ZZf\nJHOuUzgu8qUEmPp+rXYt5Kpf1ayjVCK8PTlAu7V17sw2GbXzdaLvj8FGjd6oPrs6J/3heBSqI3OL\niHm67LmijSFDUfoUNvg0AfJPh2wGPK4e7onephI2bSPrwPfqqsfce6+Ldb7i8PHNvzJw8s6TJ7GM\n0gXPQxCCPSCUvLfrfkc8Fmz5HSpP2+CfXtA1UzLWRMeP8o3mum1VpboZYs/vcaw6VSbMO2Ga72+q\nolvHzFtQDxWgIxXe7r+OinJ9cUFTJWSCNrRYHfK9xfWetlHTpQFwLtfj41jJYcTXgV7mXmh6DSjT\nEr7qO1II11hKLSkm2atA6QYZTN4IgYzRIF7p62fx84qeUqcKxCEDhZ+yeb3GIvmrKpAysJO+ydLb\nQx3rAnZcdLdO4SLgd0ZmTa/O9IgkFNgD1XIb4JPtYIGT2l5VJo2t7TP/XVbj4i9NWwAjtmTOcjV6\nzs3T9g3dcE0yyC716Lt3Hsq9JBjdAXwxbCet0Xbx3iGO2yJO1VUtvg04hAWoX8RO3bQ+iD+pSLw/\npWCTPG9c0pi+63j2xrFCqDpJOMGEnPsycq9FmyJqgOLVC8nu0JdeS4Q9hP7CbT5e42rg0szmYgef\n642TaSLliIAvBpusD82VyAxvnqqUjrPbXuyd4ErKmYvMROk5xuJkUzVr4XBfYm2yB6zV5CHxBBL+\nXpwBtOIOkqJ1+OP7zV9H/fFjLI7Fs7zC7QgmZoZ34vEUf0Y9NXlxAVrD0MF6++ABxofMbSS+bddS\nFsj79Zuhxhy88Z6Y/YsUi69XhBA50i83XSNFEcUHgfHYlCj/ZQWdZD3eC8oAK0Y8HNrkIHKcgs9+\ngHJn9Flpt88c3Ks7TQ33tTyublf6Hm9eI219Yy7wx+vRUrfiiNoZfYZIkulq25CUfVk7DWWyqC5Q\nKbmIKDVyygGPYZ0NR3qCvGekhs+1tuTNF5GY1KJgc+wu6BS/JBJzmdnM7E+k0eunHq7AB/XTcaB1\nW+JeWdndMO2jzKHfldQ83zV/G7DJ2J4/AhXr88QHjXYRgdip0dRhS1bn+qZMiouZzUTwp/notAtf\nEm0BOPL7NWrcdZlESg1kPMXRGwaxppljeW2/oIr4DixShDCvS+I0UKKL+/PDxxfLICFEtSS10qqR\nWImI0KoI3P9qV+OUC+2/8XGvyP5u9KENXLmBC12DmP+qcYesI9MCobJIFv0r2afKry9QIFEgjuxF\n3HYjuGWPn6s7t0rq6nYqdItwBKHV4oJyH98Wv0kkmpz3LzFr+9zOuZMraF17eltVQx1Ov4TTm0Yz\n5LiowUy4bt2OXg6CklOZyV1Dlx8fn77YqgcTfYbAbv0tLfDtqNwLW1t8nAd0a9B1ljHK1/iXW/Kl\nZ5DrtFafl4wh0rB1JQcJaAFoSzQgmJx7fUo/MAi7xFCZOgJVG5YXrMHqMPtnlpkq1M/tltBXZD6l\nSZM12Fex+yH7ji5Fbnho61cibEt6eGiuTE//NBE9u6bo2n62eHj1C9zLbME1j6Dqa4RM0JEhOAiv\nC3iEVcS2grrgWfJBlL/O5UDobVylh+PHVzNltlefOpdSjVdVt8IE1QLh4fn7YMbm00nhgFSWfVs/\njr3teqxSqo7bAcXMhyR8VLGqTqePkeAq9XPhR6IseJJu3jqX8uW4sQHoFOXHnoO+iFgDR91oXPMO\nYn6Mezh8PcwqvS/8Pm1v9eqY6RK5GmxdJPXyWTxs/48z6tp/jiJKLonmMivSOIKr6O6dLf1caQe9\nhjxOwUfK48BKHvV2wkZccRcJh6AWweU7gcZVTN7CKpB207nFZcqGza7aBOUIaW63hYqhPmK1g2jK\nswb0Tvve4d80TWLrOI8gM7jtk3x92NNnQma67trl0v7ryzRklkoCJedSIFs9A5eGHdGnXPJVr2UY\n+NrOlnyQURAqhVZEzAy4PhGJfz/JCe25MA5lCO5RsmPjmkpyWnkmapIOvez4cVk5LsfPLyj2D4yV\nTq+qaepnzgHZCGYmQRnvimw3/MIunuoDRPwxKh/OfgT52CiTcYifjriEHUIxPgN5WoMjRz6OON5L\nh4aluij3HiNAYPMYGtt8WIq76SQzhQieHhyJpdB5inV08pNjpdEvEh3FTPZes/7sta6wd3R/d7sV\n8d97+7VXM5xYmxZ8uv9T+aWx10vsWkCPj/j+QInr2UwS15g0ByyJR87shJK7sPxiJe/Ny25rH5ip\nbQPDmZWFjIN8wQl3GEKfGS0NMNiFMXtGh+/Lahhb1R+atvMpx35xt9Ir2jt+Dvpa+m+p1cWxFNA/\nX78010xb/b70OrRDILcv9tKjZGVNukcEIkzOOkB56xniJVLzeCNcIUkEZphRk+xJr7tsyCQNOois\nNcelzWkB8s9Lu4F47Zeg9siIi7kMuB9yeE6y9Z5A8VlHPCCfCDVjQU6gear5GRj1BujCsW2sVm3n\nNrJ0kwyrvqlwGsFcjDH53AJZtI9brX9WszygMvdqLyJ41rcJvF2JooxJW7qVTVQJksY5l+t4SCmy\nzUUeSV1Tb6pLejD672jYLtKz7QhT+qALyI1nkI0r1IPFCO9mxb1/WsfP81m/8H0wdOvk0QEK3R4Z\nHDqds9UkGa9qsYG+QuigKU3laCE7EmrzVLaEn8gJgFr+rUiocxS/Z+9HJHyifPRqXp7nszMOlFqX\nXN4Z74P6fyu0KExSqNwyLQkKOwCyt/x34a63Prne5794wFTXSLLymV/kWELpmKCcH3d65CUs77Si\nCFjCERlk2a0t7+EXB8cjjJvEJjwGG49qm7bHzZo01nD2j7vabnhfgbl4ZJx9okzpVhwQGGQ30/Bh\nSrO2hEEMRA4iENBV2/dXUbT7E87CwLdIJrnvLl2TG4BvvJzNCHf2HcT2ae/ZQvsE2GsU6+6Xu5Jy\nSMiDZmmYmdZjlz4O+yYefXz9q3gmVbdE4YeScjME5BKEqftt4FhZ7IGhRe/cn88uFTToVybza1g2\nFFIEiPopyYoMXgsjQ7msceRWRdOujgD4mtpCfTxIMR1MFCSv4pmI2DN9zMgvZikTjHlbK1zoz3/I\nMujfi22HRM9ukzNt1zNWuPTLihYFoDLQOpXZQaUOBb15LKLg9pwDlmD9tIfO67VDgBTbaTfhyCQb\nVLc23IAjaBRE2B3EN6T4J6IMM9jASmS2qdePs6RoDtYqndVAiqRqVZ18DaT3X16qBX5xl6Qy8tQQ\nj0Tv2xeuyoywbXVrUpYAPzkB+nDHnPRV+CJhoRbBeIHDVhU3ZJWSgG5qQTj6Ivb7YIE5uCPtSh1M\nmIRe2nLYU3//jf97SjBUHhYFTc7vgAdb5WNcePekUNCCcgw1Ri8nkmNNBHfm7l16J9EGe2SMMgfd\n2+r5cxKn71vlXBj+McdlfO/61QKpvlddmV7QL/i8KvbUQ9CMYYbAAmkGntHwt3DqwmFCX74LfHjz\noEovMNUqgZkbLpPoF3T1u2dIw7Xbe9X9I4BQnINK6TVRrlxHzYf3HI7QF6ysoNwdPYVXNT+Y9Khe\nWn9vD89MU6voWk0vCRiKWqmmXSpY8Ql20Ir6b7g49jXbtndHLjdGogei2c+hmpY1JB210++RmokQ\nWoOqwuwR6zhxr8O2wvac3ziMIlK1ZxpW0yVu0xiKwUfJ0uecv5VrmHagL/C4Nvj6rRQmTvp2/h4u\nCNKeszX5WM8y3cbA2mAv9/wFTKpL263pdrDYCYFc/Sy6eKc+KUQoPCq0fsFVAH3MDKruTLAPTYBH\nRpItNd5RP00IIF+DiH+GrfuTH7CoCCQB5Tie8V6aboOdWy7dFfLaf4hq3V9ifgtpEd8L9nvikb1S\ncjXHqmOvDhVxe3AsMyZHukeBZ1RLjgnjXNgqA5TsCw2yNCTPoFYubyfpl8wW2v7Hn0viFQSWtu6V\nPzFISg8eSCd0mjuvQaoWezaIRnF3/2OM0PMfUSVoj6EW5ufnrwLg1ouu9PDsm4Ycc8jE/Ne1yuij\nrHa1MGhV+8DTncjUWUG7cFGKe38rtfGToyxJlHrJlLEMH0ZMZLb3zg9EkiP5LtNrFTnSMUDlKlCv\nVyCWrA+rat2GGpjZNsw69obmHEiXAAg+gknvxnfzadN9YYfI+wxsPyaXTdByfsC8dLF9joL89555\na9+kD3tQNb8DRxFqRQ21OGMY+NfYOZVMxx1Jg9rWCgKtUEW/2FmwnmkWcL/LfNLnx+9Y1k9Mm7+/\nP7hEbQGIwnbVpcqzEj2ZShCFuSjB8QCxhYiwz4k9fUYGctg6Ttlm5DSRKWDI6xDjpBTN5sXWzcCB\n02CiQR8VX8J3/jCvItABS3oJsqR0RlJV4pvb7Ja16dYzivoVteIb+QKuvLlJXz1GHhZAmSvMKYkM\nHM7h//W72sbHLlfNgevEepMVNI4yyHIJq109zaNl3I9ZfBXaj6botto+BKEPQuTx5psb6a9ZjeIy\n4B7M5k2e8aJXatYa14fZTua+ZsIFNEDvF4vWoIMsE3n9oGJ7CCf2g3h0o92mKTKC+XY3h554XEQc\nr7tb3AWXHBavDgR+cuUrxg8eX0NWcb0zDjK0y0Xc6RS77xjKp261STQAsdlAFwG/gNcRc5G5IatR\nQB4vKw/4moyCfiz0WB1iqu7CPtkgMDeupYGyM6Fk51YaTdWprLVr39Qwiks73b1kl70JRFt97R95\nMm26con1cLbTcTrMTFCCamwOK5zEJsYT/n6NZ0yPV66314eAhThjID2cED2ZwnLecsOo6+MBx5+T\nHaBGKl4z8gRubtIFdS5FXvKvexCle2TVZaJl6ntcSCqVgKMKNH3jq2E7vfgdsEsoT5XPWKkG0Ecq\nnAbz/7OG0aPDvPvBRY8UoD9UV11bF+7LkLFNz+/ct8uZQQROGMDEZfMYcQ6vMWHqmtPkyZZExbTs\nvgY0e1HwFbYpkrFMMMKfdUpbp6jOk4WPm6t9aMzMeTuUAkpu2wmwCWqPIhNmxERRjOaTzhy8+XqK\nfsAx7F6y6co87ij6vUEDLboOjdbPlR035JG337Vfb2DwXDf/DLcnamfaP4MdA4YDzRwmxO1nv1zW\nsUoakJ02ukqZteBIlEKMM9OwcmBUAtNWz/GZiX9YcIDVMlyDDsLZqyWbz6cI5hWiX0ktsVtrbPdX\ntj4xGR+mkRS39/Fa9DGyt706LTrZaE0C5gfeNrH4qVyk0Nt2GMK0A/xBk72dqW33Y2WzIK3gOmth\nyCCUcW9ALtt5lmlxtwXvwZ1NpFezEgahy6BdoAYvc0biGltii9a4HJpprYUUOaQOzkak57yvhxhE\ng27pc5fxK+54IxCKEupOOuHEOEpXRAqA6Ye3SDW2JLGX8SQpB9Q0/4FS/ovKT1OjSuw6LCH+57Ns\ng6MPpVrKQTHydZJiSAJHqV1OTkIx87v91Kxq1nkazboWJx8gQEnW2HqSBdA6ypCT5LFu2578d2Y2\nOJj1qngQ9YoifynECgLiBBhCCAGEcTXpNoPJXFLw8jPHdfX8MX3PggGj8TO2fC8kYSmvXVMtR6Fy\njXOgwjNC/Kv6BvWtkKRg5HRmBicml0aqT3b9IrwB61u0mA7HWuIrzmyOoJDZmyTLLRG/Q5KaXUIQ\ncupK6XeMhtnyH/l0t1fjw16jTFrW55XlVEfOB/rLcbNKXwvLHimRgxQueB6Cj7dK3WjTEBTzEy/v\nNO/I/JKByAeoNXbNLVaHS8hAy7jfBWf8lWEc+bH8bHsnN7DuUpFFWJtqPto/CkIPunY23UWwu7/m\nURQxGEmAVkRGfodsE9exBhrkHSlm2wZG1gnGKnwpSy0ScePWsk5BDbgQOtEQfN2H4ti4V5xHo9HQ\nGkYOSHvtcTxMiQeivy+h7KxkkMoSu6KR5uQpLMlho+Kp94jTmpnh/DXaBbLfNAVoIi/ziyKUZqSQ\notebspzvqH4R2FFgSRiJ5CNiCEifvSUp2YxMrJz78q/EHI7+jfTofnYJrTnsyl2VsmEBvQeUjGZg\njJW3uOVyBiF6H1VpB0hkIQGsQKw79t0o6RV+RNw7efHcI1ere3g96Yh7i3Znsz3YNZeqYckzzk2/\n5wAST6LmeMv8EoprKavSiDqtYUXE7cWO8M1ggdoYJJSm/CxShXtTV+2/lBLjauO3QvWrSxYiMeag\n0V99C2AXZBU9Cv6nuQL8FdnwcKdlxIfaaVM9GSat74tKkCH2P+IM8p69QXksxz6S2AwTSHKN02HZ\nJsODgRCW/zoGUZDleUXSGNd8Jvr4PS7S7LYQQltrQZw6Z6btUySSmIftZaFQjtjlB1InIjEJNPaD\nXdC9gAE6D4IJCE76z1Ov624RzZ27xuodVAMtVFZIl30xQYXe7YvmqTPl4yzIuF1LXUWvjZwoVtgX\n5cYFcpcAybwS6VhuY86YaOhZTRhvM2377KxAL95DXyuxYa9VWri9OBkfV74Z9pcK+3049KRgeTOU\nrBsVaOppQwhGqtyq8DUJQOsqHYIzbGdJtnYWyz2Z87BbOOScLOYD7tTf8f9LiAj6YCLsH1bcuvXV\neiClrm5QFIgESs10ESwBAZTdll5wao7X621pcspnrJpi7uFtXEFf211AACHB4iH49SHJjwqELf1+\nLuY/1KE2VgyIXwuJviA4HxcM8iirw7NB6+IoJiyTIiNqI5FSqN8Zen/frIMffZakb+8K77CZdFU3\nffvx6YIqFSCZtP1TGr/jhzU3rGZRoLrxqcI5vJsWSgBiO7T53xwodneCq+F7LfRRCv/yqjqLawDa\nKaQyjf96Fl0t6Z1Arv6lCpMCfwCCkKT3yzDaJWETahshtRYEP4ClCvSnLDEAx+/Gcq6ZZ5KzxHGm\nIODFpbjtpVO8nuugKM69LZAW1xwqOp0cLUm5mahyh5zVvddreGwgvTJlPHY5SdYLGUhLGzWqK2zA\nKCnVYTiXJkJ9Gt4TA4RrUHwcPS/Mtx5wrsEUTXrAWHHr1Rpja1Z94D9Y1RIQo3tsDxrz+qMrrh+x\nNZLQUv4wUjViIUNHyp04+t7BB4W5xJmVOyZRkOyz2/0gnKRLLmWVCpdMdR4SmfohoR4FWuSRl3Zx\njO/Z/YKPvQ+En238qw5JYgIz2ZWzOGt2yD9snASPlF37k/kxN2H0PIt7ZfGmhxdoVW38jvPCW/Dx\ncoqefOs+cGu4qeAw1mZbo7EJqkSNJZNJgbgVZ3jDBTj8W+CYD0cStMKO9pVEbeTtLBaaJFVs6nhd\nmJ3WW+C0f4oYGwyclWI7TThf/w1rWltHChY5hFVvMLPmfHCEMN38Si/KqFGy/lnyhKR7c4S+AzLa\nX3GIQuda+rAjHj5T7cJxAXdit6g9myfkDSrDs/xht1StYRIxIqv3daqo1jf4vVb03ZIi7jxGpzuT\nY8OwZ1KO5odcLmhZKJPtl6pgzE0ypedajhy1dstn66P0ckzuuCWrOmlVmwF7QYPWBSwJMmuS/yJi\nnQzjsJpecUkuRoDCOMc4qcrykgfB1r7+Ag7xuijrfMHFpzJJbhttBQJ/NIGkTdaFi/i+ZtajMqGl\nmfIRC+zABPNNKkRFJYPPEB5DOkfEsLskoNw11/+2+rfCS7gABLxUvTPwy3a1W7ztjsTO77GGIaLV\n6RawROGrhYYOR0x52snM7fWpi8fIrvLLj6B2w8FELweirwZrJS1YTzb2TbZ+ZB40UXa/sHzLk/gz\nP5CCyIEij7i+xk31PntVJZtkRFaODDue9rFIBwinxB9MiUD5fmgC1CGiRzW0SBFX2cKGBB6lUCAS\nYU7suoUBX/3OK31hkUJyxoZjXz5wUGI+RsvCxtfJjV4Kq5yNp5e9putWYkvO8+sIhw7HhmNkUIoy\nYvdxXTIvzePfoW1OBKWL1FRjuKHArAqmF2vkvb6f7ruEyqkRseOaRbYc9uqrnE7ZDlexLYVfk5/X\nQ0zIcsL0o1LXcIg2Y5NuT3LAPt1y8YaTWgDaoXzY8m/DJZ+moabCvIXj7ULQZH63PglUZ1EL1k2x\nDHreYvc4PNCJ7C/taT5f1vuo7fchVchFZmRup8ESGQJOxHrSf7m8UDxXQJQA5evZsTg8PSsgRbpt\n9ZLbdPO2LAoJASpG1H38Q+HC9gVmpaMLc67QjkB6uYMm1AJe8gJH8FJhNNLXpAfWq6cMaZDK+bHX\npPQuKp8Vld1Px+SSHIo8fAzkfiOnX2dOOA8qx2ywqn8PKrQw8Bdg7Tm4VjBQE4lLapfICN4pwWf3\ngz9ykoiq0of87kXMra2hH347VTTHl1luAd0fCB5/TZboF8ZGq8lT+IOr1EE3sV9Z88000qCzR1HM\nwhmb61fOBALm91f6aDuLcSdgbJJDvPyMyLYEibNkUxKFQLU1iHzUzOigqeVy4CiEK8bag1yg3Pde\nMtIJZG8KS6mbghGqCMpqotATZNjCPMSPwFTZ0pHU4P2GV4qSA2E2yRXxtKWPYoOtF9BWoQ+ZnWhn\nSrWVlFRYhSVxEBkO/UZXlRr6qVuW7qeIDywp8k1In7JgfVOGjNRtALph4sNoOdACGVBhcJF2jiF2\n8tZlYGZBB0UDNEDv2vTUkqYfR/2XZN356VE8t6gUgU3c2s0IJ6EsmCymaJcv0M81/xH+0Oh2zAgI\nitZwtvhTZh5cSgZsPMIrEKIMIw7WquSGur8oL3cHvVGfvfKUD6+2n+ycoBXB+ct3Xox6szqRKCAh\nNfnsMaN1+OmQYUMIEujXYukpjNqeamnTGJAX5tSqtWJ28G7KK6kxlMkKZke19XYPiEjk7/3M/pg9\nsW/qyPdugQjUAJGom074DjaEkDj/SnjUaaUKKF7NLh5URedtOZZPB+bdRgCmnT48kNSLqKIAP9LN\nAPwaXkpkPoGXk5ythwfEhWEyjU9kQ5OnhWd67oqLPVCkSzTCwr+UCgA8yr0nWHbf0tGA42pJxlRM\npv8nK+8Nk8XuDdXi3EHAU0PNFwj6DkO3GYb8vFMhmXEKIIO54+1ko/M0DxCrLNrRjdsosac+eTHv\nUEdGFqWOPcQ5h+XoOOTPSd5as8jqbbFT/9O5iuXbPnDqFkX0hVyNW8SiBByS3KU/y1YmxteMDv05\nN+3czE2F2l+/rhltdPdeAQx+nR/Ajd/qP+L5PLYajt/pG0C24RgUpUHW+EJ+p5JqFllQOy+DraoW\nxkN4VXZxfFMI3SImpy/fC7At3Lw8f0m3LMdeBEEw/HzYSAdinpZE66VKeFE6LXow9iEfNe4Sfkc1\nLC/Oo+aNSuKGzp0f3JnyVREbBNPfCpJuFcKkPcnbYYY9sP3wM5h8ECLOHVPlp2FnARZbn3p+eoLc\nW3mNgYfPZqK/RylVO70FtYFyY/x88ZJG7ZhFeNjFJ+emuZ38DdsED91elkims6nr4x6FxLgJNpUf\njfV2OJc17mUodNKeoX4umvy4Zaj0Cc4aYl/gSRIy6gKsawHhH09ilZu5tcf2JfYllB8Oqaunpahs\n0LWFkmeux4Yaaj8dG0y+9jwpYtgLV6YpyJMYjKMnxXx685/8kn6/xP1C4WFsis+JRTb1JUzoryv5\no8PPiub9XTpteu9bHBVvW+goGb386+tZRAbR5bn4nxRJQA3UYRE/gQOz+3Q6r/Mu6mFDHBoByWoS\nFs+J+lQBL/9rqHLF2etqN4HZnJjR8q5dwa/r6NY8yiLa/WtxugR5daEUDiZ+0RmEUgSODLlu8tTA\nPsbY0P8RkHqV9gFPSTG29EjcRKKMiy8nOE+s/om9TnuplklqmqJRj9GF/HxDxIESOw2+fTPWekts\nSimPSrj6ni0+y97afTajVNfkJYgdHQS96PYYcJE1P7RNgW9X7TiKocm/JmyHoz7wIH4ymTEHNzKq\n0pWWu9TrgeudC924D/97D4ypdVuagNhq2le/3Tvh5V3td4fS87BiP6JjvqzpeiB0Su79/cenQCrh\n+ox8Jvo08T6T1hjZDPzEN3w2F2l80141vEcmeCan1YxIgx70WR0PNT1hJ5tDgI0Cxzv5sRmdnKhG\nGH4eo4QT9t3H9B40FKzFHSVaaOoyI1otZS04IpC0kuyYxJJMlnO1DH8WLG0rmXHwvROV6M1dlmbN\n4Jy9jGY/AfjUpAsQm8b/DwdATlU8+XwLecVR4pAg9YKLzaFs5APydnTeaUw8mZSoKaKc4QveUUvP\nePznEA0DZs5/0gYV8g+44+jNmBbkfQOnNzYdZVYN59MNnj8lX7R2Yp/ZlBTSeCnvwP8edl9aHkRw\nset3BX/087kpIuxv9wt+4CFiPScV2rg9YY/yh6qBd2zoCxvMp3qW0tXW7NVdsDpv/AQ5k+peWBPB\n8Pv4G+cXtTlSnL7MmhC/+1wEs5+l6M9i6lDbFCXkKPMIW1fvRtz21hNm8beeAXt3+9yEU4oQ4TbN\nVq63Skw/AhNYmvz9jvB1E9KZTrbfIJzmwbAUlaL3OU3vjg57PlRM/m1aHmLfykH899HrDAf47Ct/\nFXtifGJ34KrT2ChRFXdmtYDmFacYYeK9kpmSiA1dVFF1g2oK+RNUagM/k98TlkxP8c44ViwDxoOX\nf04HcZTqzljHMtYVXxgEyIP3PLn7r/E5r3TEoHqR5FHjUUDfk2YCLC22ECYuWe+K3t3Nie2z+Y0Z\n0/9KqNyD0ZL0nzzL1oWa1uWZIIhZ0nmE7nTCOwkIS7uLvC7GBvqFXevvOAwKW2FXGjZcZ6Zk3SD6\ndIlEXq8I3TRjWKoWMwVb9U6XOnumE9aSLPGcCUTIvt2W/7r9SYDQ2LOANypftmQymsggetdbgUh1\nfbM/P0BdjmE/tMronAs7p+25gRRuud92/la9n6bLvCshcDC7G6T4whQGCvVUGuIoPefxxxPkWgAb\n3+F2f+fvbsuBQqZYXiA/FoOrAG5GMos5CzH6hWUxsRcnJMQjekLD70UCuZXCXVO93g8ajWQgsSzi\necZhu11po9vBc7ddSA6fS0+QQpIoTa/IW4zAjMnRUXYHZhUjuv+J2oFwFQUOq95yPeNH9QTijJ3s\ndnIm8y6OfwyI4RHC9oKltv/7SG0DFMpoDvTSz1iYSPDIqI3TR5twLx5dVrUhf7o/M5KWgXe9kBQn\nl+4QwsXsmPs82w0ym8+n15/qEVhubu63uwPK7lVrIiTSm5JwtMuYaaOfxX/31HdQS69vQShXXd7P\nCq10Loze8CFCKbZZb4+48qTX8Z/VyzQlTU+EUZAXOslfh/udV0cUkstNNRJIuXbf9jQVPQfnKDAI\nVZTmIIu0HndZs9QCtQnZHxG5DSGBLuwJCPxWO/bUeFBGNjW7oU1aC03MwAN2zWjdATddo0Jdsefc\n/rxCarqySYyzoLugFLBA19kDqKnVBRwpaBWXkBnthvW6osrG8vzxGNznIJ2UFr/O6TvMq0hbG0oa\nfeYlf8EcdRP8N74RqgI/9HUaIuk0jdMDgwERiuuG3q1EkHnbbsbBOtgsZl/JW37XrgUs5peXB5Qr\nKSvYuTy2KfNtB3skEtxLuU0S26+rzkYuAuSFW15tmODLKGAimVqb3T1Hd1IoCY6nh1/FHDM+Ab1V\nROYhrEFvkQJ08XYV3eUtOtholIRzTBi8SP1Q+msAlVMFr2TcJ3u+LQqNpko0FycWUP/QUA7esOx3\nAuQHcBalzH3DdxU9dbBukL7h/evPs1sfKSfy//TAf2bxwDSDJgVCYP6U/kqn0pkW/uO2AqLo8UHX\nGGjW+9azqbPvEbzD9oRbSfNuub4gqlRLeho8Td9XErOxwohvfD77Grbf4j4DfXOVzKqKGGUKf2zh\ntonMKyVvPOlx0ePboTy2kPdj0CiCUUicOMKF6dAlNAhG27QzsAx0ALXMCsJ3l0zOGmPXNY2kplPL\nPe0GRPjl/d6v3oXByInXD0O/ET9GlcNujgxqtDngXsLopaQcQmOO7ZMaVb/9EBhzlcbZIMMZhnIx\ncIPCZVeZyR7ZVPkuKhsSeKcdoDf6AfGgoVS4J8+q0Led2nhe9yhVUYlLDCziqJHtKElls0JKLj3t\nU1RmkeSOZNxwNPWJs21HUAcVBVxK1rZYfW2I3px7fe8lGbpyBCoF9wCBgiz7LUbBBQ/3XbGxZrJS\nKKxlTUxvpn2CdOeHfOkzpMm9eBmwx68YBzfctvRLEu1k+CmjPc+NsSXQOvMIu7sAXPpegFlV/WuM\nV2XjXWvWYYup3AVNgQ1N+mk3XCYD3mXYXzRwldNy2zhSQiqOpPtC8YO/BM+nGAz1peK5hSwVFJbI\nkwaa4WKzEkq1/XzdW9/2ZKW0vP2BrWTfVRZNjMUUIdZwRd7A9lQSfIUqqxOEC+AFg/NDGEvqOHp6\nRL2cqvQezYXEgyq3aliXs1E0wEg3VljJ6GvmJV8dPZ+zdaIA6BHnqbF8lKvdIbU36FZztsCrBwk1\nYSB2tiN93AcpyYvUqA4GCzjG6BSaIviIDhaWXCAhCDM1G9M8jU33F4glxti9pO+2JkJouViCLhY7\nGvmBk+sfzN/N1wd05I78LCDS19xHFnABeA6D/pIGnMzeRHFiRDnujaXIIuVPlBWHbC08ETTgFsmx\n1ETQi0Lui9dpM/p1wAZsldfhK9btlw+uk0Q5CSKWNYEJvwrC4jf2p+iDJako6Xa0cw7NFQbidL4+\nmqKmqz6juuhgq2QSgUH8Yt9YVouPHDQ2XDqjc8JYXerZfzcD34oBE04POxoQmaywap1Iy81bpn0g\nkIdUIhgNs+78JAF9BybHyJdON33Y06q0Fga7k+nve9W1SFYC3CKuMlUMnHLga+rnv37jcDZrgZ5j\nuiMxrCdoh7UvJsjldh7OW9emjm8pRfZgmJ51btk+w57wizPI8fPEjuVb1f5q1GBCozWjDuK+9Vg8\nnjlZEn2jZB3GPyt86XZXConSpiI50HC4G8hG9Zqkb0u1NgneQK0Yxc+sZdGV3Muo7UZpsHV3kiOl\nKjHY7nAo2koOeeH+JdTMkrlNGTIpsRWk4nBVY4WtxA8qWz7qLStLt+cc3Lsrxfs5o8742OJEufEx\ncufyynQHANTvlZh2mmCAZd3D5lOIJJ3qM846iKEvAFv8LE/tVyBaBeQe1yzZNJlfpdt5KKWGS4im\n5pK9trwi15ZVkdsXgQuowItLnIXZ7Xh6iU0WGhmMtAjILqK7sgHIXT3b8Fm1+6dt69pklBIv4GlI\n+SU93YZznqFIGSmdmDBHHzlBPoBtgHzZ0poYxv93zWUhXI6IbPXq+L0q0apWr+wb6RHAekZqPstd\n2+2I6uxqFcaA4m0nT5GfUV+TVschJd5pSJpfMWlkGO1CSNt28Sv7szbpZOhpeQYfzzNZeDDZzqiT\n02f/gDHK3IUe5y85H7s3i/IxoDHp5eLR6aTwk1Mq+y2Nz96zfOVybH+mT7mzk81XvBnecDx2bdMa\n8iHg5vYgnl8qWt45/8gGszE6qPi94eF2PfWTh3rwMd1fVCo7TBqiyW331uhH7/FawUEnOYN7xb/o\nUFnh0LLyo/AHOH7weKKCbylO+6Z2W2v3TpmIauYXnJqY4jCU7P+3enhzfkpcAQr/uhibfGkHUH7/\nAgoIzrc33MCbzfxmkBhqNT53dV2dCFe0WUJO0Z3D1HOLaMqSVzWbpHjh+8HWlrgGB9vxdJLK2St6\nJ/Juw0W5cdZVuYotcImuzsDElv1z9qHg8veXTbw8kLO8h9eYMg5P1Gtzfn4Lj9uOK1yV5SiY5+Ji\nEBppx0C1ruAteeEeGnj/wZB08m5eCwAz2VH1rmDYU0mXeVGHRZcHHnIU9Gu0Brd22uroekrgyHs7\nn7fZi0UXVpw3vRBOC/ZCnptgfqBEMWIYMyr2mwH7pA/zksbWliUYlcht0TlnpcjNQaLNQ9UZtqrg\nor34ZMHBkTjdDR/UoaRmD5QWObmDrF05y6RQ23WxQ3ADkooe+e4w6gacx3Er2I3lqEYSfg7Ak4Io\nlonfWFiuSV8ecfP5CyLZYzx3bAD/Vd1wLJrv6gXdw63Dr78+A/RERJfkdkfZgmj8wR1bbUxaWLPY\ne3uUuDhOIJLpCNjgl01OPG8p41PghcywgJrzDdQr9Br85uZFZZ5iPfbRQTAz0jvbPhcbcO5umd8r\nPPIgPEUpArTEz8agjucYXawtHD/5zbGjESnN15TkzSASFmfYnYA7kBcsrAYYE+lWESKvVT4KbRxW\nDB7YtrkWOw5hh1hv66hRavyGKmVWm/HG0JWq5rOxb3iUAf6fQe5sZ6N05svRpLClTXqmtv082GM3\nhwYM9GKX7uVBPOup8pmAPB7/MrUzuX5PQA5ndbo1j1mCPX2vjwXVQMXgQilvbhRP1d/5qXzuuCWl\n+XincXGuu2VY0f6wxGfhBCGWaDf+CHmMBcz9CZ1feMmwBQTnmx2Et/APVsO7Qq3oqKyynlcft/QI\n6P+qdQPeDf8b3YfsuliJIxqW4Z7bsiE+pp+Apz/hiUCO/NUEIYFa1Vzartq17aj170g/Su+qLjO0\n0bsxBoGkX0q5/CKC7LowK09ZFZ6iFQ8Xh08USIIvidmXy4+QwLuap9tVzFBgdGy/URuEhhLbYygp\n3mUmQ3FC41Yc51P3KfWNbCc8w3xHOun0WGRRGgoPO2Aqef6GHzCBr3WvwXLQZRPRFrfSxaqNZuN8\nV2hK+R94DtXmEIAmlGOHTzlKbdHs3MRMovKqpPmy/v1bqsrH9jXbmAo38gWzDp3EO/6VVxGSNqun\nMXwQH0mFkr/k0c6OlkAbkzX9LjS8Ana/SPoDUSVXYDBGJbpKRWBegu/G54klOS6ikMOyxR66PjDu\nfzRR3Hj105sdiUWFpNMX61RlBJwlckGaqn9rHYLicGCV9SmX08F84v/AO+RewY1BgVfohEoDrPat\ngQOAC3sIvu6rxibupIfg8F6O91QFujpNqCPWr0N7k/FINh2e1vpQwMM5L3SQBjkiGscN46TByZbh\n/YAuY+iiAfOeH37HmGtZ5eHgJHDZjuVOr6LzmhYogMcBANqu3tGDxNLyCOQ+ld65tetsOU2T9nrT\n2u/Dh5YOmAnjp7JRaPr9A4bkazRIsczE12WjFmm5LNajUXQEpBotnuxe05rliC3Ha1E6Jyb4GWPm\nejV23cIeYLy7DNyBb8OshW8i464vzuchAps7Ykxw2NGrZ7JMvwrnXHWUNeHuATioOZlGjcid8mzl\nf3j0M+92l4y8yjmQVj8D7RqPovbWCOcwJBpUmkStzq380IQqsW/MbPDKzPBDOIO2AEo8LjR190dc\nj6J+E/RaolJKu1OdgLmCViwA3VVtfgFuz5UfzfmhFrK7FyKSR1rZU9564h2Z3+GidmZGumZYLsG3\nriuB9kSXI5muaCpXiPOfvpt1ZmNvhwFv5POQiN4wXhfhargEsQFnU8vVZ/CuYm9X8GKTFPmrZ/rG\np2wIqbfuzM7eH4QlOKXh6/5I/HxIA+bjraZa+EU0nHyY+yMQ5HvWuEcXP155mRfmDT/dd5NIn3yO\nFvWiccY8Q65G+UGW7YjlyxbFdoxUIl4AV+Pw+Io1IOcJWrN/dZ/fC9eYDPrti57RdkIEHF9W1L1H\nx5l5Hhn5JSRqI0n7KbbVg210McQv4ML2CF1GwboVU+BGxK7KBLtaT5Hw9xtxqXRt3s1h2sFHcyGQ\n8KCp1WjWpeB3kEB6LiJRi1JJpDFSSqHPusIjnOaOPCup3JcsZWJRpK1PYoRziUXLJPaFHhrsDkme\nf8ky1iTNUvuQtQPjOLbzspkRKWa/Z87NX/eRibPVpHuk0v0r600p8vGPWembRJgkn8Few2Jdj3Cu\nTqwfkzjOibPW3vbOmJRJjj6JvQ2xN1/B6OeA+wXW6Cv984IaxrG3OqIq7C/8i+I89ZVPa0JGVO2A\nAGdVJtsJcHvWzYb6ElCKuL1i1SB+88VTRJQnULqCAcdotI/9TxyIQRTQ7BRSytD35875kGUQm2kq\nQqTRnoEMeumz2rlzjpu+iLj1KXOiYj6PIGtKdbvBSvnmSBP2oj3ZNP8trdEwpiBnoWnEHcEYai6A\npbSmqkQ8UAFXWLn+JtHKKgaNeyEM6jntYC5ShlFlbTvybE7gsX+m/xaUp59pgF7Sl5uD2j45yVEW\ne76QBXfiApw36RfNz1ugFiDVJR7WCDJ+D4h0Mll5YxOkPIW8qksVJjCeEHbpp/byZeezHbp4bXv4\nN9V40DAOvoaaNPFXzVfGkdteTJDvvkX2rHoWYZh1jREgrFJOl6erDD1ZZ3wWmO2zMbkL2bUCDuHu\nEqP6mcRDUhc0HMixRq7pPl7CsUX36xv8+0coqTb0SWFRm8O4tQKTyBKNrzMb9pE+iJ45UuenhVpa\nIjdLt2P5YGoKauYpIp8BFMgVnmTBe4XxhxTcrZptofHTDhKCINkuIhiu/Nl91f0OG22W+lkjXbwv\nmI8dFADbqtFlHXpcu6v5Th2L2LMS5YLb2Gk10VEtYhnozGNClaRNx40l3sBU/OTOMLISEsNaqdF5\nD1+n4XB7Fh7hOfbjocozF2hZTERDFATA1khKILrQ3ReYAqevBOY6V4dvmnl6wA6UG6F/ZmDGOocu\npzR7bFVets5w9lBkctBtByykhU8ll1gC1HYwPxA4VvJcgRQ4lPV9akZLbnkRLgaCFXyxcxyc11/4\n08BM6KJWDO8EwBnhJtX8sscefVYz+0qka+il1xyQV/qyO7NX3Xj50rqzPoqVMBUlAIG/M1oUZ8yb\n6lYkQk+3VvbSoxOlk+8OM0usz2WUrPMCHtAcwnOIJc3zVnXBATzDgJnEJxzNJJZCLYQ+sMDTy6UG\noL2MkXS3rGyyd/qklEvx3se2B2fBwHI9xCAlVhteGfWiZTmw51liynOnr24tnT/bs5BdF4NudWDE\n28D8jKEXDocnzoR27HhtrhlIFAGx6C4Muc+dP/dtcSOrn91cCj3QWypr3h/GDrOzUzR899b3Dfwp\nH9MDb4TsjGZIT4DYRNS6NPJzivXxCdSipDjQxFtoo/bVH7/AYlbF1++V3m3T8WAYpVRPt2/6f/gB\nscxsHe/NCo1berJXGt9ETJVjMNdYGpcOZXZYtN2zzb0cD0zrSV21JpkSQ99GCv3WxusC7KhdEq7N\nBZYn9iwKZC9Y9yHVR+L7DRjNEIFutE8zrb7/HdGrBI/Ae1blICx6Bz4vfyKsjxCgLKEjF++1mRaC\nSjDpZJZNc/ZlHMLXDpWvLcafLto3kiGgT3+FqQt/nEEuJz9Ex/mvQI7xy8TYnHl/BMVceuovyBoJ\nR969r7zFegQHN/w/fo8YxQ+iupVh62kKxshZ2ZPdr/iBrjTMyX/2ruKDM5KScbeX2aBSEqR3N83T\nfUiArAhvlMr1RFllKFU3RlYRPOevTQpZvvR3RNSS/FhKIuWvP9NTTocdqtCil7BYLGD582zLzkyp\nPDoFSVvz8uFtyWu1qLQMq5tZpjI8LMGe1Z6uvg1tY7zQmodhfJNN2ykEMRYcqFW3ejIaN+5Vmvk0\nMv81hOwMsrZRDgi6o4pxrJ4U5L45GFjX+9gqKzbtSShcddcowcLd5T4husCXeIn9PPFoC2M4ALnr\nEwV2VVLQ/CmP1Qz0g2jwTvgYqqW256h5E3ODjfqMEL5OcSQFrIAO75OsZoF6Jdb8iDdsbKH0eKZW\nJCzGAHmtD/qsLJpKgA7GZPXzhcMVGIcSBOpzv5/mIsk39PsG+KeXkvI3BDfV5jaz2YBH/p8//K2D\n+rwz0RUrwW2o4htyOfoCTFpshLyiJv5HIGoe75l19iHnZSO+xZ8GvOKEW85ME+UKQ0FdM6EUMUs8\nkMep/cE30IfRv57NOpuZB40r5eAoZCCPXjUqjvxbQYNQscscrHfJvvRW9VkgM5/iTGC9SL6zcdMS\n2YxwV7SnwRapEha5puQQcgKPyVqUxTn1LZFG+KYGES29I9pHLZqrkCYVQJSnj+CGN5AeXA0drUkk\n0KH6TfziJeZltVyO/gcebrO9FagKil5GKS4pOaCg6KaiPohhIha8jiJXkDqlxNvbTTgGgLYYuFOc\nO0/i6US+flZL7LFNY4MIRbZ5i1uV9ntU0PpCWrYMXI7JQ+LJuy7C/skLIVbZaefMuc2a2WJfjszq\nmyXOl5vAM0bkYQMzIhVD5XBMb6KwQ83VMs6hjrVDF1qco2Mo3S5GmY8q886/3IE+4hU7wFIrhwJd\nL0IDnQ//vh5lEdhDiWGccHqFsZotTwR9xJgFZuHLNA3RABVJGQtZNnE813rkxtW7+FmR4C9HUORu\nnxc1dTKHRCKP1rGwZ3nc36SwUEYR0OA80KrxQI7w3RJj9Z81hfAw+P6WpTLxiCgjEGz6PhD0bk04\n/68oTkyjaopI0kh7eACS1U3ugCskmLPhjiX4rdj8qqDyf0IMfPZhO0726yIjdo3qM97PRpecGG6Z\nx/GAX1GjgATL/waiSSvObU6YUD5w+6BpIaariWcueVoO2bEgjRbWmUWMkvGNEgvVr4tTEwU6kufc\ntA0nnfx6Ue5sZ9mIvjcQHEXnCiY/aavJEPrXxhX5mFWfNGaT+48yaNPYMR7Jz4kDWP8oRDCXWtor\n/MfPlseIG5L08OyICisYDVL5AtDr1kJX9BUrd1PeSV+0zX/Q6479zUtL+ZKTcPtZxIJO9nGMzTFH\nDU4Lgog6tJeQuDXF4PSY6aKUU+OOpRQCHPT2tIbkY6zL+1B6RbkTqY2oG2BK9fnFVL0+cpQkLcKv\nrZhCfvlsiDcrpgGSZtgt2aScukEk5wRr2ULFXgmhoxn/9uOPyd7RohDHH7q2FKJr/YRlfR8xbkn8\nbPcYK/bmasx/72mbew9FtW7R0qowV6o7msUMFOMxw+EGlO9nvCRjr5XV95WQ2ybniPMDI1HkWbAT\nWjbVqGkciU7fh9Cl14KQ6GLqjaSLGrtPgiGfdw6l6yr88siIYrKxWN/BY9NfbEeOw+kibS7SBu1S\n/ZKtPf18NI7vm2Ef9KlgvL2QlClbNciJnvz363ujQULV5ZKqW2zKb5h7AuLgR6GKoJFdKCUcS7Gg\nT3E58Y8qErEb2VgetUN45sLtuatXQBMmUOTZfYN35SACnARvBxDrrQsRZXhqeJWrKKN8fz1dbhLc\nZhSsletSlNsuk66EOaTvyCRSklH5ftN+18rDfE9ywFxoQSNYPys9vlzLr4qisqTp1UzsxFOAfu/z\nTK+A/k398o1h+oR5rrVPtX+YJ6bSIGmp6UDVUpHvoVX+3gWClfOpZjzgIDPccuOlwIde2oq+wGBl\nCoKbScPVroNpva2kxgd3LpUlxKDERYQDtSZ9l/hzISys8EmUF+LYL7qYAtbeEtqIKieCgrihyoyn\n0czrwNeWzSqepl1NupxC7+BY/jqq6nxQglk5UcuE3kFnBsxrO4w45Ib9YxVsRPjMkTc4tAG03Ab4\n0TDrRTe3TQgF8nru5mtq+kCIf2rK4LxfaD0lRzTi1ky4bwMbRjbrLzkNM12MA0vr3srMlLt2xHDP\ncIvOY7hn2VlvrEaFYMlaiKb+QTHapXebXXhYs2tuf9dC+KK1ZNL1A5Toht5rfflNB0RIL9wpkuyY\nl6NXg1rX5DMrcpGxhYav7TvTHjC8g648CBr0vAGc5zlqx03VZpoMiejLFqSQp73NBxNDZJ7h0kXe\ntKOZbwmKqkNmuZDOChpBgItJ3+9z+WC8FmMpfoPKo1V2fEXMS5e9dRVN/rZbIeSFp1cAtxa8jogV\nISVu5OGk0r67Zx9ybVrP5oik8eegLXlsVhk4l7ltsY3Nz3sp1o/GS9NXRlbYY5g77/bnRpnumIGq\nxsqt7BVO4171sdBqknAkyE0KchQcMQNjHc5kzgl42fBO66o0KttMKykAFwHEsETf2ho7OpkKp1BG\n5hxM+yFJXnfz2kvNETznt5L/su1t6f6guMjZOMvi7M9GXb5a6HS+9RGxJcCINA5dBH7jZT662rp4\n3MIspl7SEFuzvKyKjtvlJYDOHuElk7L2BGFCVOOwBLK376R6MqrJE6wMt0gDUzYBUjXp7qKl8N3h\n/jtgb6BcDVtKQxc8EuUenOSTHpttFqlowB5o//0Up4i35jjXu8nMSXW/S/+QErBbOqT7lgXAKbTg\nAfDGPGDMimIiqyIBGWgdyTO/mVQxjyGiOb4wwgP5g06pbU+1EsWW9lRpT3SKnxm+sN46MMiY59+L\nUxRtmBPwIGseG/IbtQKnethWAjFL7bdsQYu5pFR7izlmGPmR5mU+wLYDvAGt8NKKBG+ccjzl72ZF\nx83VO9EHw5rzYE3RUgdLQE/NGsvIgK+e+r2h6Qv1qq8Fq+Vf73Qj4tOFQfDGWAJCydz/pSLyEMGN\nnIKnewLJGmetxtM0uvZkYppt4sgOMgO1QzW1eTsLCG5rBVwg+59pBsAo2ZlSZSdYQeyRr3zvqwwc\ntMY7qt6TTPOzpEB52aMk8XK6WHrx8R+KXbuN659pR/brpeZZK9H9NbznQ1LxDFflpS+B91AkQSEE\nGsTucA3X99zVV/9FBdCPtNjttPKOM+y3d8W/wCb4TCnvnVGUr49RKOCwXIOLNwmeEblhHlWlZAop\neGw0N0twxDY98g/62bmR0lb7w68+Sij1kbGkWSA/9DE+ZkNVsDE+Yep4SV7JebyyW2wHLdTGImnK\nf6EC9hIMjU3sNtWn8OZfYRlZSUU+8Qbq9UaMMlQkxLShaki3KrfNc4DP9xjX04KBRgJE2k1Ekewt\nn6bk+4AkfhPaSYr1+V5pPH1yU1ev4gnm4NOjtbnHkCv7MadW2m+LlLnQuYcR6UCJMHiAKVijUmVP\nhMoBKgZC3qb/emFutPQhCkcEO9C+XfeC5moJdr1WLu8+7aKn1SLw8z+2jEiPX8XKrQe12kLC90wI\nFYU2lUhy3YF0gf+1f/0SbJet+1c0ONxITXXeFxUtIZpXIETmxjthjiGhpSLPzxt/mTzS48HUr09l\nbqCVKuiD7ptz8EZtHP1+5yEX5PBUJHJvQ/yRrQyWBx9xw7R6zMJYJyVkqZLFv3q6jrR5BEDz4nBK\n5XtV5RGJ+F+ZbHVHw10moOFP92cRHFCU2qS+kO7849WduK2W+AuS3paKpxqZ+euflkV17FCtCpiP\nNJFMjpb5l6heyoWIzLUZK8uWxsFoldEUOEfBUPWwuOoesaHVRskq1ltXSOalWCxFq0mwI/br8EAl\nb/CMj9UnOS7niORKECP4PwULrVag2kkrxnvxNJdSdYdHWrwUXZzLe/7eal7HJTRhZ/mUCQL5dz85\noU5x9aXCe4S13cTBZIkYvbSct4fU72pyH/LI1539H2csPHFD8BuCdQO2eywau6n9oBv7P8qvn4s7\n8zDW8FlnUn7DpIjNfVtQ18MFPUr6yeImUD3HdanR5kA/qdRbi6I7xM/Gqgr4BuKsaLO/o02lxRmC\nmrGCT8Gt71LsLbTlMwIV6xwQfNQPt/Yz3dbb1PGh6sPo83McHlZFNweMWLXYp+Kkq9UqqzFU+7NV\nHIsd+a1Ky3onD4C+IVHWvBZfHa3Saa9yczPPGlvJvc+76MWptLCpByHTiO0cYhsgCZ4sCTfkbteP\n1Fuo9ChowkoPW1Zbt6NyWbmvI5UJCrmBnlWT5R8olLLLX2haGb2IvJfrwDH4BfJDpdN9E+uh3EF0\n4NdL3EH8WFlOiLv/PSY8v/HF6EigvhRn9H/1uMukUrD+SBuIJJNluO2f4wRSpC0o+cXbck1rMww6\nurRl3tH8DGpqLZkHIIm+fxEC9V0UzRcZcCuyYAtTRgik/rRwy7CxAtEJ22eKIe8odiVbNdVhjpL5\nq4tKfwCcdpvtyNFBZPq3vmwRFbdUvkJwXYIxTd5Ai/N5/NntM5snkrG8z0O3RXtcKzJoxp0o5Aik\nyPwlpaQXnmPDcJ6NF8Y5tBJrYLtdZEwv8gUI7ozhq/V/3R2XtzyTt+mIF5610mgK873tV8BkNkRk\njo/RXE44C1y9redy+pMCWfWs7T4H5FMeodmLICYCCZL2Hm5NqnX2RAo6WB394+H03WDgv4ojOZyi\n4nClu/RnHGbZd0IKJAKLzBYEap9MjBzZujR6Co7h44KZKUwhBYZRS3Kvf7WMqmZmBDhdNw4wjrVA\nSFTOBmFf/u2C1RaFYyAK87ObRK+yT8f4lL+IBmVNnFiIlP7zKGW8+hpwHiY2ZwPVKEnsNcqeNtfb\ngva5ggVomnPakHh2tmXK/KnAKysq8Q2GR2hzLC5i+BWsyVcNG7q2rhY4CKp3HazcVKf0jbV+Lmqg\ndaaUFA3Pz68UkKIGO68W1GZ7bvw+D2CaLnFdSn2umS236q6rN6y+RWtAnqCLJOxhAFAKErjoai38\n/E7A8EjVOjI66J0RVe5WnmZMB392AoFQKARv1ikg5pxF1smM+Q9tRaXP9/XJ+1AenFbiJwDaBBUx\nmjA+mXm9k6RUHavk/hN2Iea42m7GptEstA9fHhC3XlXsuOv05QBEFpzsmnAjoCYymr4yIh5vWAYf\nb2anMtVHlE25amfwij78rgFCuTU97t+LsdctQhK6feyME6vnN7roxf5qZKvcYyAdm7fTB5vyOBZO\nv6u1nrxYub5IVVTi9CtFLI0ZDX92hsE2J/XesvEsMqXGQf21Q+LYr4B17k5o5y0PkrsmH3H2Yn2d\n/dYilTCWC1suGgwVYK0NocAQSnaPL7yk3yHXjTJfek+4LmHs72D2Vid8x2cNwHo5YbwdeSvd1pJ/\nGcrNqL7yEg2z5HkI3dvE1c0k8O8eVB+x7+X+ugha+h0xloWNqj5BaxniQ861WZ4WbOlEQOougto/\nyim6JGIV9Hxj3rbxGfSciFWTsH1+fGsnEWkuIYf0r71cO7KQ3l6VqF4JYmwV7mJ90waZ9CNSDaeg\nSCnJLlhthWFHGuPAEkc5GrG74BHzDLYo/okSN3CSK7+H1E0jOwS/8tMzbt19pBYuCxukbF3vr/6F\nrzgNDo7t5piVNCWtN644XdtPSBtel1Ou3wP0e/jYJgbL8WZmjd8P2KyTqThJgOPGTtXMYeLD0UAo\nKyEjOMyVzRmOSgaIta34CdYfLxiVpY7VKxxWpzj0pkpJv3v0/zXhBRsV6GiC8zhKMXFrjb2zs5ly\nw3z8pNGaiQyTNGgzuON5XkzMLpBpHpfASqM8Jx0VbEqiN4YCb/4BRZgeKfRSR3vh04glOFdnIm5x\n5N/rWiSnwT2GIhpx+f1GnuhRsB9LOx/pclwy4XoTEzUvQ6w1YcNB7BcKXYmVE6jv1b7ELmFa+qPE\n9DoN09Eie6dijmFnFuq4GLyzrqNVf29QdXu0xvZIoOFHCNH9QqGA/cBIG+0em0mlFaVYWVZfmy8Z\nYepMLHVSTE/nIp7D2UALtcUp/3mOfE6rIVRC1PXgn+Jm8bUPu8/sz9wl4ZJcAKZuy8feONdw0HEZ\niRCMYrEUZrZ4YRuQS7TAvKoRpCxOWEmc+4cCr+oAAMOjw5trPkgcZn4ETNGM1KDA7cJJj3btex+x\nSKSRURMzANe/lg8ylzgciWCkN1t6xJ+sZSViocQPyY/kiN8CT7VZnzXak6xVkie4xepBnJdOHdpd\nfC5cR4yOSkxQfI2YNF80XojFZ607J42KZEq3mkfsIVhOCoN1uOMxSm8PBEIzUd7WO7XxwPpgJ0eb\nX2+IB77zvShs/t8FVdGv2xVQqeQutDBz2LRtBTy0qtC4PHXf3CyLwdi/loL4CNI3yGNrNz9v4yvz\nMxWCNcZL7XxH5nQWOvANid+1ThkFqy63v5+giKa5A2nDg5nthPoYQ3/PXq/lAPhNfjErBBUHU1WF\npP/Dp66lh5I1Eny9chToPCg2zNBFqN+kr/h1tOV1Wbz4RDmON9XyYGYeQzvjDJv9cvO2uJ9u+vgU\nGWQbW4sGqZm1Z3kiz7wNifHD6H1vVd9Xb3LtbJ1AUBHlBZRSA4WQlcJBtWdkAUZwCREv6i2k49/+\nGQqn6mnoowUPGBND9eF3nnMIN7ohmzcChUX+YsdTvIGYUqP4xINm7vaSy9j75chCC5EYpTtHfWKi\n0rLBt/93bFvT7uUWM11BU/hN21CHzG6K+p8F1GCS3KJg6YxcurScnigST3RjL2R3RvtUjewmWWoW\nS2XYcTRI+zbTP3oDE+kgoM6VfNLuPw/O8qK0osMZhftP1qZe94/OSC9eGvDiXqjhyb1jH44xom9o\nnoNmRwZ1HiWcepqWExe78isIHBi+HZDSG5FW+jxonFI3ztUfQBgBREon/XUy7U607yzXzH2mvbnD\nQBZVsDIBefrF5tjlIE4w27B7OyrQZZy52fqcGjywMKACpXCz0P5r20eyxSYCvRmazbF+tXqAXFuh\nqCSM50tK0T+A7vK/OFoovcS5Z2yTG0x6R5XPJI+73zYhc/PcAv6Jru3hFwdAZiMg48L0Lb+OAj7K\neKu7TkAv0RvEARzfjOR4/AjxVbd3rFGZPIO730Tfm8hCK4wo2UJiYwzyhDjySgg6dkYf4kirU8cn\naQMeDZPj4oQDLUgcP6IObaFf34kTRmWxkvd8sLUZMnJcmudrx/eOMsB3nZS1U5UwP4XVumagAQvu\n1BWN/F2W+jGdXSMOANIv5yGLOEoYWf+gfX8pAJibWCGTvJuecom+bFfek7t8P5utlg1KuXQGaZhB\nVuRa51PI70pJMPbxjmFf8gc6R8CH9Ebwdp8w1DLf8AIZmA2z3rcry60ej2iYgJpiGLNncR5BGAqC\nHFOj1xR28Ao8H/kX0EaDa+1Ayd0JmFaO0DP2WlR+xgRh3o7szisgu2B3Pa+2X3ci8FX13RH2Huf4\nzosOaO9LzXzviKWU0BKII1D2nWEwZVKaN/ctQPWhxU3MA95e4ol2i00cAtZ7/Vi+CUu8z6d+jTx1\nLXoBosuWlyFgdFvpspNE13CHB/VlSpg0NXnGtzuWmJG7iXBgjsBDdkjthzttKRKZ7OV31NJ6CaGD\nc+iXUCsboBonJ3yraMpy6NhnkVivgmlXBCW6+X17zw7VSpjQ4ZXiojwjWqL62gVqQXEducyySxGJ\nYQyhJYBRooZL962bAyvg31Q+3pKLW57/DwFOzT4ngv/o7BvlIoWJ1BMOVkb8xCJ+SnVXW+0WkAVo\nRNtt6ASuai8kk+p51sn5WOyNBWpid32qZKUWIDZrLw0ONKrbN6oOdXHyZkBR3kAEZOuMBcsFtQ4f\n5sbF6f76MoDIj3mcsv8Gy7RwUBWk/zkztrUXDiDAvMUJWC78WnYlEoGAFZNhlumfI0i4ZBK/oeBI\nkbZ+iKdYRqGxCUaf/EjE1PPmP94gFBMXY0gtCSEJP2QB59Ja5ZtPZwe8HX4DlyVZZQpSbF+XjTBr\n32nMFQKb2DuGi2oi2FyZ4pSJoEI0dBSML8RPx6JmBFhKH383seSa9UP5pkHxUw9I5tczS8+89T2u\nOSxwHnRNxblVyX/HxQ+avvpXhJBAYUUQim10JKMRhBgkvLl6tytZpNsYdyaqAJxbxOMbwo9MTzAA\nGI6i5MXF5r681dHmi5nFqshhL6v83k2Rllpx+Gu+WTfM3Mte1r3QfgYqfEGFqTmMB3kpxNPinLEN\nZSn5tcTIKjGxV1TxCosN3Y/6uBzyHsBDX2ykDb64Fr32kdfrXkt5M2/ovaqK8Pqqnq6rdQpf5Xs2\n1dXVgqtvKN6IcbAuf6IigT216tQ3+sqBBqR+rUKPFAlUvVJI3nIvUFfuH/HLX7rOxfwqai29Xda0\nF3yBpw1YMPd1SsW3IDaXQwEVxt/Rd3vCDKP9a3XVWL9b6E8Bj2mY/MldxjMOZYkibs3x+XfD4n8+\n6DB3K8NmGIRlRxEXijyHQX57YBEv77RzB/v5lNIScAe05VfB5btj1Cx2dt6lWOksoenmMwKIX1S7\n4rMLSahPLhE6HEHEfn2htbPtowWCe9UCRzOtCIx93LoPhDSESkprGq7OYd2XN+3h8lO9tVGeBNSZ\ndIVNvlrYlRMwi3+oUixy03z7DR6M5ctHezXQC5dRD4ZOKnrk6J5wGgQ8MRsOcBaAnXB5q2sYWyp2\n5FBwXZ6oMbBTaGgM16Jir6JXP6j/YH5UFXIGDQ++gam7VOJLL6Liyng/BSKAGK4Vqh0IwSDid1xu\nIva3ZhGULvHa/gtbjd3lM1K+E94SueLf8+bUFzR/nJD5C/q8oS0Gzg/JLvllf3d36wv++TKcDtgK\nHiF/EmsGxRpY0GFiee9yKmQ1gQaKWeqrPs8qmf8RYKXmk7XNbPznrtkX2UdfEJymQqvGLHhzOWoQ\nM8MBOgXP5UTKTsBc8oUEvrt5ljW0w7BdaUy5fseCONxnW3TOwj2My7VtoVx813Ajq97+ALmpVkGu\nPUdqMbsTWIPQj3qz5vyWyasMht908i8sNrVoBZloRj5rqqN+HQS54dO7OXCg8qL0ygbbdIm5rsLZ\nEMl4zbysF17IvuKAW5/7td1g/0R20Db8aPDU5J3NIVi7BdL5I3SauZEGjjqmkcmjP8OobRzY6hYR\n5FwU2j+b4RVAXXUW44eMRSQuxlyHgOCcZAwtg2aYI3HewouHcn9CpqMLaHlBzOepuM3KWbd3nOk4\n/EZcskxjtobhrVdIRP9y/jZagh84zg1oIvSK4TbI0GmceZBKOj6P46sooGj5Xdc+ThGQn5QVdEpt\nBzrvF35ggy5x0oF/sajaOq17LZNCIwC1PBY3IjWk4uvy40zIy2OjFQn3C/N/rMLTNeFjq23rRscs\n8HntGS2sA95T5o4QQo5En84hIVJ41UjjJt9oy6eqRA3lLa7Yx/AiDGadSVTr6qMKAY6nXMNAnwB5\nXGWn9uQR0gzGt3FFt83MHGJix36DqRdEIbenD7EfgPK2GJEj0+qPzPkZ72MmuqsUVdanzDM5016X\n6xqgjGXl02HCX4kKcznQ1cmS7ylwNnZqa5j3wV5tmx19Pk8zJFzELisjiu3n1kz7+UvFuAPQOCjp\nGmeXJm6joeT4WPAo18UbiBEbGF4o/EvFwfCIdznIX0SdldTtcAV6qUVXeHijTeNGFmTkewOqMidb\nx2O4jq/XaRnSsuaUAl7wIPyW7dbvMLQx8Y5VzXsdLQmu7v2/6IORNvZYeFSnfH2m9i3kljoVzj2q\nbq1WRiAyBn4TFZLtN8VMa8NeH5PpxIN+zcRu8OWrJDC1ayM/1ZLP9OX3wgbW7mkDCzBjb4+hp4CZ\nC0MrBD8DQEfUZuh26gnwXy/72HgbZGYSkl5Ms3N8pQhxd3aBGQYnHBDH2AP+KPt3Ye3HN8KasIiQ\nowzfr0+yF7BKvasieqtHh2nOFaYAARWjwdMip5kDv8yUxhDkW5lkeOX+uxkIq9pYVYT2HpRMlHZY\n/esnshJ0LPccvu1E/6qOoNnduzGxewRrkKBSdYCIbQhXwM4nVJ2anty3ull69B0654PCKIljU9aW\ngvZegAGRV/Nei9bQcZmkCwmEEcaMFpL1Pbqa10c4eFqpK5lNvq12z/A+xNJiGrk1SoVNqWJc1N7x\n8856hPR36UYTRWLI+3uEF1k9C9bXvWDUbw1RwS99TxHJ4GoFEsOBrKoA6+BlXYDZrKJQVsH0h+PF\n2+pO+fvYsHm/bWNEWBCWsV3fKLoCTvgKMAYZJrdQ1AUQhNlNQslYbjfiTtRjUs4g6TJ4rvAoQcQk\nIB5iRzrWwBDcBHt+qYbMYaTel0mI/Vvc6vcH+fkAhEVOxuPNdPkRpss6nl4iKmxLL/KaGBQJp4z1\n6o6p18jI8HwKPQ3XeuqUce2xUP4QDr+QdFtz49VVdFQ8BBiTezR4Qh4hr0195/6zmjiVk9hmFHga\nunORzSl2qNO9+TPdE81CdSxqMz9C8UG4XGRM7IBcKE74PQL6nF25PMp8k9uiwQa28SoSNBMFSJpr\nMFwd92Uwxll8wkE+dJv5tDz2TOuA4WwoAVXevNQfy+fhtmf2YCgruBHS6P7PxyFpgvTnm+FUV1BG\n4lmbvexk4bgG63juZn0BhOUevlEsQf0VjnZdQrFzzO5oLidf9PmUDp+I+lD74M0KXu4ddYEJ36D+\nbERO8NxWJcrLN9fxb6I4jA1SIqbpC85nMO8ENmZtct/5SC99RE0i0RO0aUk+R9GUsYpmkNcM5zhI\neQYRLZupKp6ZGjM7a3Z4i+haMprvBNSGHO40kd2XhPWsFpYPnx0oBi8T82SuxzaM6yYyLtzu9eMv\nzxHiFCnfdZKHsCHVW0teJrE9hfMk8f8ZAaKCCcc3v55KWTJ5dTKu2jeuuxtenoAUKe5gOZzZy2WC\nEEFEnnvxmWwYCiTJ+fHAkGCwSGbalwyWyro/QMUjGnrW34oM6w4WqQNzGsF8cixaW0ob04wckbYQ\n7CPfeSBf3mI6hXlFocL/4oB/oJlTILY9Iy4UM+b+MtXT29ulaxBXaBKn1ATr2SqjH/YdPtxNW7Bz\nk4RYdnM6L72NL2Y7Kazq1CBcRfpPiy3EFG1plwMPN4SaDUDIyhspJ3p+ZM9ZDgFHottRfweIHULx\npghTPmOcdi3I5+lxUHtVRGjfGDzWP7iMcmfuXcxae+mphwaRUnDLSJYnqd7g2NtAcAocgt09dbXC\nWXWGSiWJ7SmpoIkh0C/lknfwbJZKt55d7goVscCEQqk0r3RASleFMo4lPBZuvLTeaZfGNcICrmsk\nIONEn5nSFyrdemyKf6tp8YqR6lxq5Qpw+nhuOI+9nUGia+G5pPmcDRdVguFQmC5gL+XrAfOtRnL3\ncCHC78cQqz+HUalavqmh4fQKNNKotRLMy50Yaaryazje+C3eEqKbOarNiZ53y/sT6NZWoo6SlghX\nlljRvmMl6cocs+g4EMtvjKPFedEWI+KxjcwPu1DBOeM1njTLgCX8jZBiWXWbiAcOUtX/5BQcSY8O\nu+xPZVkkWmp4dPdU7Rrl4O9TH1KugQBDUhUic87q2q5JIDgu3i9zIqh5XQ8m9wgVuebLN8jI7+VM\nTRNC66+XD7ve8sd2SxVAUSh/j2LjqJQ8/NQ8lBopnu3/yA2JIHaZFC0BQSfKSJ4DrWuDFw3qwY5w\nxTAvZalPwShLo3kob36PLE2urWVnFotkmBe8skC/BLKp2QyzrVIInLForghN7iROrYeXLwtFBsnP\n1IFAeb6+02Zh0xhWFEf4UGxtBfvg7hmhAB8zQ85mYyBxXPhwmo6JOaqNlJoPHPg7bLt7S8WUp4HF\nEd9D1Z6d1Oju8zavMIy6jx50J1RVQrylEVCKjZtvY/A/Ogb69iDnXxx8JsLXbZnPmn0gd/R2UECg\n4987lpLqBMJVL7rhyu4vbCKY+/oQSZS1rtlyXx6sMeORy/6Jdyr+zxrRIiM8SPnVscaohzgycBhD\nITSsNwwGF1p8pRbBs5mMmai1HVIvU+qxQRn4WUSpMiKQQ3YYP6WK32thr7fXHQygOaUFTGWC/2id\nh899L5jDduBdhZ+RxP2YM97cLhVJ77rkgQlZqlxv/suQiwF99nHEjGGRcAm+A/M8k2d+Y+QIkdg4\nNb7K4LUl89cLAWcNxFXWt69MJt2pbQzkn30PQg74FlY5202SHymW5kRPqpgND+Nkuy3V8bE2RZvK\nt91H65NTZLWzihIsfdPWE6uNIiOKBwpyNgikI5ckKNUzGS3JMZL1WNwgKUJBBL75lc5Mmy5Lt9JM\nYdifP05wDhy/b+cFNGAl5HetH84myXjBQXg7JkR84rOXIohwhg1KCNTUDR1PzdteUbDXvhQ1nOYg\njBPfalkfK1n5UAPWvvGlEsBdXlAxVUe3CznqqDN09n82KBCt1wxQvTmvduzrZxJ+3XYLtSFdBV3/\nMXolTLPJZ/kTMHqwEEsnvJilGUkQKQ8kADFXqG2TCVEJxbHiA9+nqBm+g8Llp+EwK0wB0qMW++yH\ncOkBkS/d7ynq0eRQn1PeNUrDy7ECP7kSfBgkQ+MfcLzc+H/caBwiq5/yHEpR+E3jBA/NX2/pXl6b\nXl3bAfdF6VBbrmObp0VrwoU36v3E8Lal9N4g+Vn75ueo2uDM5Z1CUubBqycT7uCuggQJu6vgPu7f\ncJxVmue+ZRC2KNbXKZvk9j82Uoigeyz+MPtOyqaWI35m1YEFP/xbVzrwYtqijz6Tl1zRwUB/HQ1v\nJzRSTb1DP4G2P+sTTXwRestO4W7FqXKS1XiH59/m2AYHDPpVZBhZ9k7n7ltQS+Y1Jd1wodQMupR3\nuIMT2S7JyYz1Paf+tda9MrOLT5HEkwXDk+qi5//AgLu9dvxKjFZs6+O2w+wuW4hOSI0OLPYCxiNl\nke9eChqWXPEpofTSyWrRbsA1e326rfixHqSgwLEAuqPpbGtawnUgcisUQlvl3rMDVXqVKAlzjBp3\n+MOdDnBjXIg3aWWCFaN00YkxkBqicuqS04uBt+uook7NgKnDtHoHYpkkyDKaKcjYlnm0LyXsFJd/\nKuLoreWA672hgvRLNNWlbgSkvfxrBg9vBF2VBy4fCItp1O4KCRfm0+AZvJYP5G7LLLO+uRIcFuRo\nKuCRyVUpPVat59YJGci2ftMuk6NogWT9YxtT5vWfnqG/R1h/wH3Isew7MM4+s8GpnWy93GNzbtRq\n8eya5KzeTZ6xUDco1yFlrQyTO4PjQOMbYVTF7zCYgrt593guoMUIZd0A7lryLLIzn2XmoiGuFiaU\n21IKSzA6JRdXixUfPLj3LKX+ZD1ly1MjP7X1peBqvEotrLWW/OCdyu925Cn9u2UMVPZ4W3uvcES/\nZSmah97sImyzU+onh0qVx/RmK+3DWcQOyY/U3PPjoZKyyONVytiW5gIAyC0cKituJavPEb5gUHLk\n26SQVMKN024sjPMtxjAQbOeTqGSJYD3xT43H9ygbmaJeET1XHsh3G9RTAq5Bwe/np8MbysP+Y1Lf\nAcKnZWRnp0BAtHk7vPMaWdniee2k5Xcn/dEqJhnJg6lukbKbCR8H/3J0YJpXdeb3Gf/7RVFabCXa\nEBhtnnt6BgpODqzdT3lrrBDCCLTq5Tqv2Ap2dy1jWnKYUwgErUHPjB50IY2ADYMu0QWA6+X8Wuei\nz2eR78oR6W9lF7yCRCvtjmQwxuBjL2thTQOKwVcr7eYzTRvY1b2BxGj5yTMx/y+SwK0w9p6HqByw\nEUi+pO08NS2VZZrHRhebFMs6l+hcZTAwlJbHemx35JI9M7vtATcEMhVgsnQI2mHNFX9NdSxwTBsU\nkFSgSbYAJ314DEkbDaIhqiI3Ea0DEhvhDt/m5sShVEXh8fNRbsOhTc5XxvNTAJlQH/eyk8riqsn0\n0tv8zhnqkO0gRAXOtJt4C63g2rIXq2epWYcldvjHySk0F2hpKssOU6pZtlX/ToRbO4ApOXPAnO7F\nMRCLuyr9Vkkpp4JGI0mhlPIfIXp5gDI2jF0L2EUy4hTaZKrXVw8b12ZPY60aQwekhVkd2XV7fmYB\n8n2zCMWVaLtkm1ugv/0zxqKs0gLJ+PvizCPH6gRqf3iQfcBRx9OgO+tYzMvzaEU8zoavEJGZ9hHO\nOOikHZ4nXSVs4YFaJoKz8NTDVh4vxdgK3sFHVaZMYoqF3y3Lr0Q50LN3YJzTfzP04rM4+hEJgJot\n+6ZN7kAeejmEoFdb6l8k5VQ1PCJOmcFpGC+i49Z1K9TD7drB+tQ09u/BOTscOEiNsy5PmmVDFJvV\nkOmuNanKx/J7Xwp483vOb3LMc0Cta8Q4deV78K5u3+2aF7wwAlRejhqdfABQdvp6pGoG2g8bExP4\nZtFKetgU9WGsxTOFNcn90dVU1aKnmqwdig6snQBQ0LLxVAe6a6MNnSrlrvAZw/77FxSHeq+Mv0I8\nzMv2fWN08x1JUeEwOiyEUQqgRj44Ua6rgPNqjbuzE6IBB4XyG9mZfz04nuI3XROcJSwuO5gDLhXD\nYXBi4NkgNAmbUmxWpTV+XgKSx9wt+p0BDnAIZNz3YH+Xyt+0UKm41GgZOHPWvoj0oQBN+/n9Uv50\nzsYQlhAyC5xlnDbzRNVu3hXytwgpuPMgmUi+XbI6iRaOrkGjEljdowc/1sVWAod6INCkmudarkI4\nNUKTou/dui7lB6qOWVgPVJBfEFzZ3iT6oU2tZodjtqD4pxk1i6irDTdBPT4BJtWGeqtYzfl/o/u0\nAjI0d+qA45DsfLlidNmEoopuF4OstS/hjCCu9my0432BqgiIM38wiIfOdXVraes0oMv3IO/7Zz5b\nzw5updfgDiXvH1vHmwkgt9U24cCOa3oLNKme2ZQ1TQolLcgpYutFwPwyM4OlC8G5A30dpfjXCeAU\nLlKPjCg5aYu2HPArkyFNzLJGrQOBtP5vXc5+tpVvGVt4AnC/1TN5z42PQpFK4ywFJyFhob3Dwgjd\nOCdtY/9UXHoZWrxIJ1I1L0rK1Y6Ilqh+/skRItP6i+KJcRFd0NNy4I/Bdy/869l19Slto/ShmNbz\n7yjhC4zNXHCx3wzMwffd7D05IoGt8so4y9dEgUEG2dxf4WTgwFCJF1IytfZikhAGSCrSeTMEdB2O\nwZ3m83q6CPLWLly0yJTdu65fgDL8JbC4nNyI0jD2Uu4rTi+ShnGtGqdVKiFGbRJivsGE8akSIAwK\n1uofsayXmaRgsg8ndQfWKGwK4N+yGevC3TC8i6CxzSNj9wlzgTQ43Kc6Sh36WXAEbgNLw6IJmWdb\njIvnlBtq6Cg8B1wcA+PISNcUXuZ6611CKTF22DVC5m8lCBp7v6vyf3YuEaqisKUrPZgRF36cJfuv\nNCJsbEs1YoNqP8ehsZdFFrJzBsTZ7AE3P4o1A5wb9lX2Ux+DiyNJB2BNYkKGNyOnt2SBDCetA6XZ\nq2tVGLV2Z0SE5ZwGkdN+CTgyE6JNIPgyXN3BHn0xj4omdQ6FpwF7wnrwUaMFFTOPAGtcNChcbf9S\n/525Nr0x/h3/ToCdDGoo/7Gv+4d4mTXDQ+vKXXz35DOz312FJxtBU+1hliKtFpkaJukxR48u8A0c\nIYTZeW3lb+jhgHQ3Udo58MII2TORoZjsZZ+awo3A/787vJ4S+eUCl/vuUnNBHcoAySnWEfCHRgx1\niBkMK6r8Bz0QcNqbS0c9YjKy5PfS5qFEvb63qBtOjnB9ccnZ8gzFirkyPAyR8cH6PD1WT4sxz/CD\nvAgTDLd4B26NUzLlem0ytE8gm5q3W1aJ6oPPGoQXDmSFf5uQ8ycaIWjUXlcrPOfB5xPqzaY2eJEN\nBjcZYwRzey3nJYhrgFywc1C3AO259fpoeUVIv7mc8KS0yWI4zm9bypdpMC5VsoDKpSgS3sYcQXqy\nZLBqar/68QZqMxjk/xl058/fLjm0cAauc0PQORAqajeHETflu6aNnkafuZiIQ4KljwkFhnniq+tc\nMqU1mo6dCNSUaGuaDg79KCro+iTAahBzw5sjcc5NCFrILZ3Tq4INWz/2huLRCivD72se85UIKeC1\n7hGlPtd1tddMZ/WZL8BqCuWR4axSuLrgfkfVCrf/pFVDNZ/U4KRxyHtyEk4TV3U04vFNd7yAKUJI\nDi+0+/+O9ICXX//Y0u8ssSkYUcxsIZzHpAKSk1MsEZNLtcSLgCuMm8faa5htzhQ0YzIG7fNCvCec\nsNlSqROUpNa/sgx8gNMG61fXovyvvmOmX9c+1O+xALQ0JxnPxAMx2GbDuwxSxMK2z37cgDM8EOoB\nwub7R+XJWB4siC4tII5MLq/CaiF1G/U21SNQYN34mRYC4skcUndD4BW5QOzud/iV1RrCO0rjRFDF\nk1vdaomXzv9fw7X2hsBSoOCqqxEVE7MZkJztZR6h3I3ljT8wFTTVpLGlvKpBfu+FugRycYwV3K19\n83J+kFnxtlF9uhXok+mqif+sWzbwAiIRNkcTuoUCjA3Dve/dErZTUOAPf2+NF6oMRJV1Atd89fRn\nkoZEGtTrqHVpJPZgpKtI4EIn3mhKD53lRm/95U+AvTgfziQV0oR8yLYmfXrTI993DBlDG24wVdS+\ndww0JiU29TFugxQHkYnoj4xlQg1h0bgTK7ck4V1XXZzA+uZ7gfgw0d9VYSZGJSz5zgNtxZSMK3DX\niFFvqThmTn3oCz7O1rANrjo0FY6odQ9xDHevIHBKZy6Ibu1A8wpUN2Z2TI4yL/IhYYE3YOlthg1A\niU04wawXtdqaI8TK+Fozun/pWAvRFB/lt9/EL7ZqpavSdhMRS20RF72cbqXF9YPM6+TEqiCyW16Y\nYDEow/zhbG5kbXLbl7dxQCTOVaG53GBHFpt+a1W1AsWkfEE1dr+Vj797hXJ44fU4ERXCQ1JRrMLX\nHftVR7R2dIcqrAMyXVikLRl5zYGn/LtEwPRxL0jUMLTW6ziMAcextqBSBrywwRDvEK5td6XrQca2\nQ/CUPvMk4/uPQDSD+eGZ7B8SJztRgJsYqHGAW9lecPiUW2Xc6fGMcOJQihLovV78IzChaGngPBvF\nm+cunjdGbznvBAcdTOVro67Jf3LlGMjdezZHcZuMlMTQdYWICbc+eIcJ6b/prx3h4E+2kcJxZ9Wl\n21Na3d3dTr6Zk9EftCEOmEBNZThgto3+8kW8qH+2P8PKuk0/q8SZZF7VApy9KbmR4f80ydmBGZi5\nO6QGRN/B9jx5ValopV3MEIOAJVaNwCbYt8LNu/xL75m32+Bb7pdgvCEzhsdK+eAbLg9P/tWPnxgR\nuUXRNIL2CoVJCMqqxjgyKXKG0x06Ul99Levck/zxMO6JWLaFWlFIgqyOJC5LbgQAEfZgScAibA4x\nR5qZ0VZA0OI9CNvQSEYWY8f1z44VOJKOCryPIiULREI0ooGs5TT/Tax70JGUjEmS3+3MIKF422X/\n4XbDsbw8Izo9BChjSSOvJ8DYeBE6tqBwIIEqdKm48DpmQ0FkfnRcQm7xRCcTxvYAljPTnkOyEgMF\ndFEQgfdfn1eGf2ktn5G0vHIQicOCzYmf9A2UNuG7QZ5OyFFUC2Mhl+mzIEISnwaE3tFDNYRMvY24\nzwi/TUvM5EaW3DDJx1von4wjhWzoTqJJNnTEpPjv5NBt7g4iEPwm/CTmSRA8Bnxw35VPYLnobvSf\nMff5Ucu6Z5N4Jke0ZObD0MyjjsB34F5tfPTP5N7n/SUrqPsFLtYfbRyOEJb1NyMRaO0SUINc1kvW\ne4Ahs6cw1f74GmthnZ/CV4vc+DoL7cfCNiJIyCakl6G6o4HjbL29rEukBvfa9sa4O17Oknod5eoL\nD+RoKyk2O1zyVaFWi9pwov/X8LuHMBY+0s8r57kshwXeZT+gMQMfvigOHKBYZ1FMX/hp+JvmAgtY\nGrFXBOf+e7asCnAhwEeFcbPpotLJC/2TTkS7cAZqNQswsn7e6yTYBdfhAjf7atMdRg8W/lbMu8b2\n9tdq7P6xRoED6AJw9E0vBZJqv2TYumENqntKoRyhc1GDkSxEZ5iKpXYf5rBbrvQwwkyMUSb2w5zw\noKMdLjc5o6OsjlFBBU72aTgJSlPm+7yENAnZHBXHJWxpho70vSSkAEsZFgoqQZWXImzvVRPZxmME\nXnNQl6qyJrXkymnFWcgvZknPS/DNm0retXg824GaEP5MU57aa66AE5mE6QWTu8K9GdKselEry6p+\ntKVBaGHJysWgIoOfr3GddVITB2bwAzwrZYyH6RfNCwCpdHtI0AR0r5eYL7mztpvyXqKheI5QlHK0\nSp30EqEWII+hh/PAdlKxcbfgyhPaMxSrCXSzLlP1fIskfjTDOFTRgl4qBFrxx8azbVAhL0L9mTsr\n0BbJklAlxP9LHu8VHafBNjqbzng/a7sN5AvsXm+VDBVH8PsM4alU22YkyUzGh55nHMDxxv8GG8I1\n01gl3hFPiBs9jzzgrOd9DYGLv9OsLghd7Dv6ViY6TauLRttPr0SHMWg86TLFdKzdbfduWOjQBbc3\ndSS3AdSTyjovj0rWPzQiGTm2aZPZ92iZTRZ2ZOTngJAtd+QFOvSGpCd6BwhG83NqND4vV2WE3w72\nrtsXbzzTBor3Nme+cwlE4k3WeWGx/3QRuSIySLv7Hfp3tpU1GGcK2oyLWh5cOuaJbdIyeQkzqJV5\nGoRsJnvKbbVyJiUVXNSVwU1G8QVetRHctI7jaUydTMuBvEalVVvn/YFMOeLlKO13t6Ma9/gyDTSM\nKrb5XS69QN1p18p9ii8cCNo13LIX5K9sUYk13mIxlCDRlcvCdfwlOP1iilyej6oXh/rdcW87jDoa\ndgIm1mBp1w+U+7lqPqJ9UNO5JNsnmOimW59ukJoEzWciDuaJBi90GPC/FFoqplBSqh/5EIG0W02C\nSC2VXhlVsm4ZpRW+xMKjU+aS8Onltqgy05qiJzWFTCgt/i4VSRiGXI5Ri6NiA5O+lGT4uiX7c4CV\nicGJBVFwcZSHYsAjaKpgLF3l9aJxQwA2o9/gddjWFsKaVD+FiaYUo/sRduRSQccasWod/M/UjCju\ndWP8xH/7qrt52M17y1tx5Xqu4UuBjhVC/mBr57LBS17UBd5lMbwNb0SP0dY5YMER4lOPx2gmzlLR\nQZUUF9oWt+ssRKHjb93n+RqRDCLCuCzTuQ59VUtTdPtnWcorklJ7ddaagAhXf1mWVuMZPq9+/Ds8\njzx5JAUdqcybIQkQOpzLDzZ57I7gIkJNVOQyZnsug3qdlCFqaFuDgMSLnbg4F8CNpMfEp5O3YsMY\nJ6jL85g9V028y4tRUiQS8ediMuFLlcxQJecW0ScDPEQU2loGW7SpS50j64PdoszrT67TXf4afwWu\nVo/o28ZEkTZli9UsrSLsA2qZEoaabVKoCBQ1Vrc1VpS1xcbkSM0EmPGYyKT6nIR8f25k2TkiDEqv\nt/lbPz76ZHaZl9qiZUYQqh/C59Y0D0g+RS4QJBk19RaNmlwTfWA50ZJL2Kshu0uGvGusU6CN7NP/\nAVx4wgC8x8RwFaiWSrBLkC4NVBXVhUHgiR8UVT8Nm95d/8VCVi+4OkTyuM7JhSThBNHtUqulC/6x\nQ9vuPEgew2We0zVxYAeVafbrBzXY8M3TQ/0/1yT0n8egFHjkUSFsI1Zw6WnDSbV37sOydlOMcWSL\neQQWddCxfQ0dutv76DqdkHXbw/cm9sSIoTPNTxOESJE0wcjjoUV9bBe4C0SJXRDrJzgbWrkHj6C8\nwD1rQqMBBIfrDcYpC0r6fw2R8Y49dvI6AbjvTw0hFfAZc2EI5OqEC5QxjhGaBEPkzbRueIXQFMn+\n7Gei0dVJcnl/aQ6NFVL7Sf+k2PFX1E5bj/8tpJalUAyIGMVu4aWJZX69Igi1fE2x5cmLCgXLKnPR\nFaUIO4Pb8MjGG7nfXGM5w46z/+8nB/FCRoIxl7mC7L8XfOXOaCT02JQpLYKTtki8LDRqEpR27lOY\noYLD1ge8NZ7yndpmyTlkIum26tiBYWjwC0+71/e5ZASzIKinxaqRwjJCMBXHp/pzqvqG664L9QP5\nJKaxHYs713Oeb+PxegPlr1WLhV0RI3YOZ1KewLTgrb871ieH8NRJ2ogKYAtYgKOndUY+P6TFR0zx\nOTrLjuYUOgbONvm0eLCx2mt8WLB8KxiBsKNKJ24pIb5laxiPRV5vZWy+ArLQha09Jhbo3bGDjrTq\naM7ceU2FZa1FbPXI0ffVuNMbi2BufFeGNqnH1fVoDgFzJqp8e6J4Lh2ywOMsptV2NtQXpJYSuJOc\nyaqxwqz8+F3OzTh6P4ZTX+ZR6uDHhOkUi2LJHmac4FdQZCTOzIgLpgsGGDlBEIBEyiCxn2jC0+Wt\nZteY+6MMx2xJe8oVK9UQ9VifIvQzO3NMchcOWW3gcG5ZowtWYa/vd8ttGeCkyVuGbZUSYDG8ztbE\npgQM/TEKxDBrZ810ON/tbm4uExkoz49FkJnMhVQc/QYIpkPJN5rAsUyV1KHx1ltGq2MuCJMEhfRu\nWnV9QHyekXVteXel5PMob9q/8OJfOyedL5X1EvGUJRsteE/ECO8856YAhvRmjg+iRuGEYW08IlJk\nQmZQrG/Bz5fnzuaAPmJDcDTeS1M6i4qN8tCFYrWRE+DA4fm7kJKbgFAHFBRRXnVy8HbM4JqghktK\nXxIrWeD0ydBhg5AxHM6a9tKsqiS8DOEhxJMRw3Va8X1SmCSNPYtfBobE62ploPkxCgEfXuvUNL0Y\nTcyrNV5Kho9N5C0AhkMbThy7/H2+xiD8wHxkG2+iBHZ0lv2/s7KOdNV37j+6S5lBB2o0mvWRh6lw\n0pd52l31LzYlB6FjbUJ7eH9UEgSbg4txtoEJ9xo5CDddvYUB38Mam/Hn86DNGJVRkdFHvhann2dQ\nyyoC8Puz9R5PojkbMNu2ZHMocjDgsOWoFOyyYU16QnKj3r4jKf5C/OgMd2Qu2v7HmTcJBid+tOvi\nYPtYOu+69a4JcuARkld67/B1sMzXj4mxI30ORLTFk0rAiBrtl+DYPJ4E6hez3vFp4uECbweCsdPU\nghIUBJDYERp7pkYy1NV2eNHVFDd3e7/YWJu1+zHzmi0K2Ea4niJx14dFaBOSKVdlTWMH8dvj1gMP\nGmOut7HbibcvCgn8b0/JcHX3e5HvxN8IXxHqgY3Wxf628ZBDbMw1yiyeFXcUft2OBXk6plxhERHV\n6rdPV+22NfOvCbRyH9/QpnOYkDX9QcTqLPyG28uFiyymSE5GYAi4IsBZQNtkAiK8uc/Ipio3YMK4\nlv6DjuxGUbg73f69W7rzIPenjYUoDq0rVSfAxbGTeH11ILUoekN+iEpdtZKdr889RUCxBxwDGivR\nQncG0WZyBUP2MsBfuE8aDYogNiWm8XJOkos3Sq6FT4gvskVSd4/gpA/Kk9bsawnUipEN06f8X21F\nlIzA5RAitX4+FeGloLRjeAQtR+GQqqndtgAQr0N/tj1plVtY7f5xKx1oRRoU+2RkZpUML7kacWa5\njgRrhn9bl+qwqc23cjOE+qu0AjlTX/iWykdNrFl/anoOF7LxUpfb4+VsaQh6KfAgM4d+YjVmL3YI\nyJ15VfNLdrj3ujdVVKcvEGfnVVXluY+a3izF+6GejWDYrih/8VV3F1Nl36XFqhMtHOY2+blDSjOd\nw1X2KYmus3DPxLQfCRI1bjy49NBDpOyitNEORPXskLiyLVI2Szviac1hdx0cW4aAS1h9itFIeiQX\nCDZNLlUIc+QX7mR/NatJm72WrMdJIL4LAvMlDIHXN285ExGSDvyzPC7P4c2kofv6E4mOy6ZdTEtV\n4JX8Ar3SOmpl8AWF7Y3Nd62l/y5bH/4pYTx9dXCDIacggTNvzagFeEk9ifUusNwcG3tFGjZVxDeT\nKTA7Ei736ivSGgHmlRl2ywwDdvnuwKnoU2WQRaOkqtvyf3zZyNItIN8mA8OFqnmMum8GurOMuYnZ\n2U68PYAmvjt9zvjUKSrgSe9SvZtoKqi96LFfqSCOmMbc12yEH3QGobj6KybNUj0S1mMmmQ0VXmxY\nOZTPSd5YxhbPw6uqOAI0scXCm6OwLsVCoU3CvlzGyi/EM6WAl6C+Yv/Gu9ah1qkQF3u5P4hiknTs\nRObtC5npKv9JVkvPrwYP1dZIRbjKCly3C9g+zT3MQde/QhavYiba0Q+jFhKJTatqyHeCe1NSQPho\nCjOL3Qw2lq6GbL2GMXHeEVGwKiAICnWNlFI4hQ5FPrbq67T11hOBrAPwc+bC3UFExPMzy5+TQjG/\nNfFW7yxBALvHM+JJgthptkELQ44JrpXq1AIC7Zbz9NewZod6y5MYV17j49qB7GWtP8ywkc9hSP2q\ndjQwK2JKMRUkk3xP9BHPfgdR9HuGJkdU4yRSuLMWyI5ALvkANzOAxGDznb9qUFVMRMEzjUNbMiDg\n4xi7ec4dujfB2mkJTfTRC7rwpqSyd5VOsLl7DcP2SUa+d/l+/Vo20Vp7TbiPvWocorPWxrIE6fR1\nALh66YqRE7Npl1TRTZ4+P4UvnjX5j0KjIKrwVYzwI35OXYVdHhliwKL1+lBBfWbV7B3d8uLtEulT\nHuRYyZStHW4adNz0OfPyIfmyCE2AUYP/v5R6V03tL7lbjO9mgSR8CVxhk9Ucl7HAhCrgzY8mf7U0\nq6N0JF0tiHu+eR+aiiS7n8JXgzDkqrOiBgxvc3FPzME32HKQsJLobt4vNbSUKJbWOAy2FQxbomcL\nb9nL/MI/N9q99oiINPo1c8eRiST7sQBwFeCzgTl7rOqKaUeXZyp51FGDGxRRG7oVDQ4gXIWtlZZB\n40Vl2z7kh8YYiRkpHuG+JoHWiDBKznu0cubCXiRii9/2WjI1+WtYkaJk00bqzAv8e2pOHjhh9c9F\nBiMyPU0szlEI9JHjyGXsAjWnBl3I5PIbZ644Dy6EiQIOQO1DjD+YKCCrwuO8yAiYXP7/0kNEKql4\nf5TJmqDmbLamd3O7G6M/z5pk9u0DqojtrzP6GbSwR3CK/etQrbn43xd0gSjUeaT/uAdg86hQgdrj\njs9/gYZmo7F5GP991GXUr1lDSngQDpGo1XozIjxfoibSB4Y2xNHTC1Edk5aHEXAiS62Xpux1xqX7\nOLD3TEpM9IcmmLXyQsLGHyGPiBYzBJfmIuBB1w9L9oh1c76Kcu8j0BzN9OCtaqzDP5Zi+DSSCbnJ\nVsMDldG4DY7Cv+xzrAQ8P7726JXCdkaXrokRFYQl6nPgs6QBkXGuT7Qq/JKjZwoEGJlaXOZshrJ3\n6QK0mMHyzNw/dq/ICgGCbzMUXnW9OztIv28kWMVuelKNL5IN2Pc78X7MC5GrBpLCVwbiCV+UHlkU\n7e/QhjO8hL5/MqUN0ZYQbpHm7IEaUl50xOFMa8ypoqijMWRLkRHa96jkl1ziAbCrn6sICxeIku5M\nojFr9PRKPe2C92SBufeZCq5eu0I4EpbIE79mBHxrlrHJDGTyK3U25GXztdxAzKgfJfjI2K7FJsxB\nqrExrwbSxNQi5HjY+BHBv+N6V3opwrB2TOxDktNCMMW5FY5VDDktpHUgSQUbajuKlZlD0ait48UT\nk5+qx2Cii/eQ3u5cAz8WMCJFeFQVA+QgBd626ofrqlvrje2fFHM3x+E6EjygeyYMu7t2P6Iu9/z3\n/1H4HjCwWSObvEtv7zLCrfwAX325DbdcbSaB5Rcu2/5n8wvuL58g3FvxlQxGCr48LOpCOT+Ovrw3\nTuZIwX9VOFUjxsYgsJe1i6dH8S0kuzLodk43dYCAhfwobZm1Y/4t+bj9IDsmG+TFza6AfSf6v3O5\n3+yWqWQ5A6NwEeY1g/O5F+RzMj/GugYFsNawdEKAX02+COYAI0Cjp9y5QXjYVg2xF/SUgCZ8FWVU\nYYQa1IFkTWiH4/NUmAKYNDwA782jbLqBlOV3OeMAFcrRW+//CdFFYzJzXhHvzoWAAHYWpWMS+Ngc\nzgT3hu5sP2DIsaw74xZYujaRYN+HhgcXvXjrD5ADtYQGyyiq88hKU2IfCtmbD6Y1AfqoihYXTbZ5\n83225bZQ/VliBwj+9D8fkZYdcfSEafSIs0ziS+v/+pb5dTSe7nnyROlwIv3k3ff8FB0+J5CK0tIv\nsvWhEVJwQ0c9pkSlWiIdCddWxthgzV8nhg1M4ZWkm2l894FcMari8V1Cf6uVuQdyEudKHZP9g7kW\n9btefI5oQiOzFCjiv/bNOWdrk/F2/z5AN4Bqk8nsF2dXzNBesn031xCE24Frswx7k+CezgyUBXyf\nr59UzAamw6zZAx89Z0D453CWTR2ie7Ynui3kpxNHkUHeVKJmVVSMpM+T9U88TvXvOVqHgVnxnPOc\n4bwdk/O2isiz+BzXZrRjAGvZ5nBPSyO/hKWgLVakfsTk41zSz2NENdBVbxVEIbyFPZZm5zcyt3Yj\nRZT5YYHg9N+NaEzPCyIKwNqxJCceL+abvhjLgMVfaEBatfBzKjCadSp2ZDY7uHFs/k+UpsaDqPdo\nVwP2lSeKPonjiodG2pqka92DKgs0fDNqn+fu/LhxTSQUffLMJ3TQ7MYEV2fh9+Nt2Y/N74TBom6n\nNjUKeyxH6SL6RPrRxLxhip5VEFk86q3e78Ee4pNZe/lPzXGCMwq8JudbwGup5hCgAhX8Mi5y2VDx\niKErFERzFh2FXRzzcYnSkyRVmhW781SOCOsSnZ6xYIkmOO+rxAsfrp6jvlQoWIzSVlT8KUAKsDzH\nBbcVh80Cvtz3PBUaPAQJzFCh7IFVds5/W3N1icQ7h2ioMJL1ea/p+OTRGLePlUVJiN8Ym6jGc9Zn\njbgTpGbXtel8hsOXpuQLArwhoVwe4RNnFDREW7FdtE4y/L9MrgDfAPfA2io+BIo3u2jim/g0YLbU\njtfF7F9GXBTiqsvzny7YnTJKT1yYdCGxFO4GYZrNQusPsLju9G8zwXSX/8M5RIG5A/QWq2euD3Mz\nIAAnSvGMcutA3pEK2MSs2v3MFJaGfNIAYzTyX4gAUtzZ4eAO/kz7uPZ9diQUA3RI+x5q0q2Qg6SP\nwWjxOdtltiXF2JSGYVp9E5eSZ/Fqs4q8wLJ93y04Agdd0MZiEjVbxwbXdRdsObLE8qD2EN6I7L0j\nrXffmhTLFIm6L2rTh1Iy+5QNyNVBL7ixhCaWK4mU5WtBb0pc7WhnnTF37kTvkcRNBSPnMR/aGLl2\nYcU+uTFhl7pAkzjCDC4mahil00nXj4e7C3SOvcj5HGmo5QeIjjY1BfMB67SDFB0OmX27Ji/tlpTE\npaoK6DLLOGBf+CquHFKbtIit2hgRYL+TOISj16hqL+huGwR+zI6F0aCA4BVhC6bKP9XrNMZQalE6\nXc/cqItNaSMvytOq2s+fVbH8sLJcAJ+kNxJobMnx+ktxAHS/20BYMu336MzPvyLzGHZ/rIEb2NRw\nljaLnyuVsmGz4cgQwhPjtVr76tptWPV0AxgnblzHQ9b1MNDyhBn6gYQlL3/BMqhY7AZvj4nGf43+\njlPJPdqmV81QSqoKJayKDjV2uX+Ax6MOGy2pCELIbrACnGVtRgWC2gjBWaIsOG1inrs3kVNPHAvb\nBCe58cHD6qFNE7jn+PY0vkWBr1mJMBBzxvGghQYoTBC3uiTKcCAwtB+jnbFd8cXwIoXRXhlWRapY\nDLlcyCd4Rjok2vx8iSyMwFhSfArEdYuPQS3ef32ZdmQd/22nZ0Db4a/tqKtngwzmReEQPiJ0p4+U\nCYAVIyr2kKyphduRJ32Jyzw4n74ICzKjALiedye4oVfaw2ytTu4P7ay4Y4S9fOSEXxKZnI/7DmrZ\npvGHp66l030EcgFln5xofoHXeOCBGeqLkNO0WdbvsaYJEcI28KzhHuMAGGW+LzJHeDndRhIzqRue\nmiHvMzljVAeqn/M/o57NWa9QfuNDcXCLKihonfh+AGRLMEfqydPylI7d9Xe/bcHiu/W68xM/ISdL\nDm20CNHhqAEBCzCSm2AWkdksmuIkM2NOf9xajftGTPdcwqL3MObw1svKQj271rv4kXhiiQn3AkHx\n4skz8nMU/JMCB6vHj9FtwyLT9S3DcwFkRH4ce8qEcAxtl4APJbWkuFEpnwEt12E/kX0xljw/JMuq\nXWn7oPSbRmQ4Plxb3Pm6dMXo6aAbNxLhShrYRozo7v6lPxrAfad+ldUk4hU74+GMY0Os7r1Uwy4P\nDmhW8Tk/VwehriRQLZli5nFBD4od0J5OrZlcK6DYXaTt7gMnSqrL2ZVuiAEpYN+JCTFOeIAJv7Id\npz1TU9ioTPdgwjAiVKKDmdSLO4+GWRoql6XV+EL/IiauWTSmJM98bK/uCKepci5j9v8awVOjC6W7\nHt3eHxrDEftHeTmU0A635T+VBrph5v7zuhWG2t5impOOU8HFJLNeba8FJZ7Z7+xp4wK1Cp9PDY7T\nO6wblMVu1uCwLKLDPSEF7OFD8MWWQr1IT6EDEUhhT1XZpwG1MeOfdKuHgpDRi28tCb48DOI+lBgb\nhKXhSsODVeQN/xqARSA1SrmfdL2+ygHR+ON9Sq1EvgmMNL053zxXTdqE+Oqdb3+8aa5gad+DrIau\niqRknSpUvT0sxf5h9oTon5LDTFmzP+FMgUZQ3U76+88nrhPYSRpucFzqjpJ/TMEC91N3Q81VUV9L\nSUp7G2M39aIjjTSME5xLMFDmTMrUgjAj1+b5SAL/ehGdUwvLTTJ3yrd3OaAFQBLaRkWFKnZAnx9z\nQWmn2gm+q/eZgSuq6s8zSB1MZMpYCEgHv337coDHkeIV60BNcOKoBGMxbRS9rB5zJcgZ+Xn8VMB9\nowlzOzl60K1Lqd7vLOqtxMlXA2lfIKsgk2MHupcuGUahbQcrCOSmahVeY3gLV/fDR3F0KUUmU94Q\nwwayuDCIgDfeUm8829DwWBWOO9OCJOlJKpkdI8iP0BFtGqr2T8gsvPlC7lsoOZJyXtuOiSDjJPRI\nsiJAY7TaVDNm0GI4swHi9bJ6Y1eatfwhEr7qi1E1MBNxGFM97vwuPhymrjEp0EKPy4yDnWZ+UoWz\nKitkqV6/94l8AhXHDFKuFXyO0g0wkE8PVy218WON9kQikx/71SC3n/9JS9i2eJwwS/DsB9JTkA6d\n4l9Jc3eCntywyR9yjJy0LT8Frg5tKV78HRJl1FZxbFA2jnI8HkBllrzdQpwQ42pYpl5iyp2Tk5pU\n6/LkrDZIVYDIQHEgD8ngcmIjTsbRSIHLWEYIBPOg6fQLaYtkKi4xtRi7v/zc7CQYOcoJqTGE3L2q\n8QXLMhFp/aKPdXbm4PO+pYy2zzXMp+F9Go1LTzOe1yfHYjoUyXwPZZa65XbCnK8CvPYxmG8w/46l\nHlVaBFRPjR2rg2P2hgZHMSwpbgPRiSCPnlLqXoj8W0yPPp7OFkut3ywF06gWn7ZZJGJmlLoS4plX\n/fY9POjTZngL6gQ7J0Y6TcPebd8F+z+6J/K0BDiOhYyHjYQjlRydUkL3X2sAm2c36Yu+wJ6Y4cvg\nowCF6xHvg5P/jM3i8HZ82kLT2J1QzBbGnjqD+VQ2xtfo9bFBp0DcccL+8wdcIwWtn4jwIpy/MwpI\nf1KTLizQXGv1p+VVqKs9rE7pqJpoosClZRgi29U8xHxRzifx9NN+5tMpvLS0v1uLqiIDjR2d+7jx\nk/BCBHUCz9EMW3XVSRiTwXP/5rYPKLJIT6bK1ilM0oFC3fxeNyE7BIuqTCmz6qjbuVw+H9bKsTJD\n3MM2aTR20h7yLEeycCB01K9kOxi3ggGW8kid64T8dv3I7aijwDy10QcrRNuN7QH21R7e1wz+SZmA\nplHmP8jvPwNV11Ug061JofXhDILrkkCk3Fffb24/bJQFz2+WoICPAHb8Rdc6j5OIjtlnqEm3hHUS\ngDrv8FK7eYfuCVS3o/0keeo4CVmRX7OVddDN8zmtvZIHiaLKOR/rNbeniHlJlVp4e5ezduHhvNAW\nwTNa9Kx/DEPbyUcryVGM5XZeVxrAPx+hCd3pdvadCUfa0hAbBXZdZ3w+55qyUNaCM90xp6iAk0Ja\ng2Y9TDTzp5i7xQ0W2pcKYfEmRkrJ7UMURwXgq+xZ+V/lBC5dTRBCErTf5BXFHyjeV4zZ1HfLHs7a\nd7FA9hcXKhEEZkupdVsx3sT6qXOFb5FSx7AfPX+rcnVHjA2lUNIDxkICNZBIv59S0usV7iVDUNP0\nzM6iDoJrBzR4wqcgqTsMoHuIHURkCdmdX++u/4YBbRKNygry/A5EEmnNnjrgH7z/JyLuW7Kvrbrt\nvxT8NcqPS+n0S0NGYvnPxS/1nSNVMV4ZCliyeYjP3GbyxaQOdkp/PgURCLWFOvakMJFzNo9SNtez\n5MSRuq6j+mNgbHVbt/bUTPHg+b9EK3xvC9qW2YC0m95ypBGtFPAI3uAaf/YHK4XlZ1LMsSiafpa6\n2OAODJ2/n5rxwEJFQx+fZmqMi4ViZGDx1KHEYZjOub/RaByqgg7Ev5qwUTqn/0mFSi/sPsOoIbSr\niLowOZKJM7Tdznu8cg2lriQXjlTrX8X6vHbQryQLIdgKukaxcmR4vPzm40YvwCpb/zF84CvfjxAi\nQwgpWFdmKQO9nqLpt1PIYUHQ1lI/paRW1Pv64huLmRJwAPga6v1bAhfenUm21wgateAZwGmHSuXJ\naXY8in4cfhL6UC9WfnQ+EzKP+IGFnQnuoDyfN3vvcrTxmOFlq6YEEjiT2+O3oQ/TqeZ1OzR1RjOt\nopBvlHjWHl/QsGD+E/xK5g8HZI+DVDoYvsRYRO4EODaEmV5AtXkRbWDyyX4/E4ol0NlATZmvSugt\nc2UYzsQmRMB+tnV6eCKnTVeUCm+rSOoTaoRMnZnnxK2ujRrLi697whRTqD4zjmyT4PygEqQ43egu\nZdOPZjYMVmE9V5dmMf6L/zCNrq1e4Edbry8UCaqsu2dnSPezPqreO7mt7Y+ELFsNUa308pfgrKkD\nL9YF2dcyDbDwFM+fdkth/YUqozZEqxLDTHmYZkMdAyPQGgXGOesXK9KVIgivkzyvFVq1RsrqZZGZ\nA74X8yj+H/fujq4+4KWoGwEO0y9eSVVIQ4HVqbYss/3++Dv7mGfsqoF4LcLCvX6BZNbykCobIhq5\nDruV3N+qBl3kv9D3cCM73R7OgirMK7OmNLhsqUSQd1/LsPCo7p53dCFNJ1jJ6+faQE5aRmjZPOvx\nc7QxWNwFGih+s8he/0HtZOln9sESK8elRUrLccWrdAuq9hUWy7npcShylUHzoLRzFpkwFbQYVL1B\n8l35tvr4huh84lT9rEA/s9gu1dORh2jVkkbbF/uMF6wMOOuuBd2bzT3s1LZu2WrKgxISLRi0T6Xk\nredOhf3kLBQqRCFKR6xC7SURUbe3UZhGQ/q8ZucIIXu1MN5UxEzfsGGkCH96NBVUNpd/TtZqP+0J\n6k8SMvyorsi3Ow3yJ5vrdnHL+twPuU+U6ixjr1JNLYIfR2/8re9Y5rujge9LXQbL+iDadXCTTYzU\n8aeXFoDdBKgmR1R/N2nfzG6DCKWdiv+Kf25yd0xvTttFALqna8j/FG43YdGyew+dettDTQisG+/c\nz9r8PdJKe5xBoe/dC2G2sSD/5wuFMNYhgAG7u0ZMcY7+cy1+GWrtiOWZEyKm6PXS/1GwnpX1f6Zp\nSgGmfNNzJkkXVhW/8SOY2x3xmtWY/fCjjT569G9+h+wDIaYFqwCS/BcLZwVD3uARDhIDG7vxOxvt\nxJn0x0og9PlkwComjKRd1KWTinCHBVX3WOlQeb27AVN6hlYcp91IcgWpp3YdmaA7Ow2a9Zg4RoqS\nk0bSEqkjpseXkO86UBqNHjIY8ISu6pit6Re/XgVJqfFRTmNfmJyMYKk7XtoGeX++ri4C7Y+mQ7jQ\neDcRU9KHXHnCi+Ctn9xk9AerYDA0WkKasvX2xsYf6mV5BDAv2spfV5IPdqBdez+mxnmEidmNP/sv\n+qn+w2jLZszcguFvf1PFP0YYa3083RZ9q9MhCq0S3FTT0SoKGsGhwn6eMNof0P2OHu2axH96PjEs\na4JGCNWAMcp5D3acO8rpliyoL63hiQ51dgjjvLWPmYMRrYz2/XNg4AqAaxm8dL6DnAQmMGTFSBdj\nx7HqdNLTAl2wnCofxPNGL7YSC610V2MNG+2H5GfzSL8bUfaVWQytmAAOQHO7vXKSoS0tPb4QJW/9\nB9xRcSZK4FlSFu3OtSL4cKFF9Xb1yiyS7q+VQEzoHltAsHwfq1Fgo83O/G6YkfCOx8R5kjYIHa8D\nloQ3urmBettClbGUqn19gXlhpOUuLFcCbd3eVU33sWZmZFvH6iL1RHEITovNskYuzJn8eA++XRYD\nieOvLK6RJuoZ0iSKUHEN52Q19+izEFEF79sZunedgsXksTAqShRCv6GMMK8eSDB+wuHyZSekEpxN\nCPoAk0K2L/8AlMd8BdPYDhLKTsGCRJCCx1fMugGsd4woWkYpk9rchqM1yGZWkZXc1ShqYZQWhMM0\nJh/7XGBw+q0B+XlOZ23wv2CKzJM9burb9Bppgq+2y4rNNwgM0ghhGg3AkX266/Npn7iDK2p+Jr0r\nK/zgcA2YcuEMKdOVfonfL/dPoSrr92SboPrakFyrQbBLT4pO2yMIrtcfjlc3f5zIqYQwlR57pY3/\nc/9c6NcyRZJIf59CTBa1F/I72sHhoNuao5LCUQ0slEzpva21H/Y6LhRPrMqTMGnyXtKId6phbNWK\n/VtoLUILWlDv67alhlL9vBYTgKCv8F/OKtbohzCBzwbkes7vqMhCuMMpfnn0hndHLeR2J1sTC9mS\nQAXOQYtjosca1XK9HQGLVIEXwbBMPeouTusz/qXsJXjAJEJ9tDPtYEtVmDjN27Vu9nqDkJIfkklI\nNA43l+Uu1oDR4FkuBMY5WtKxsia2amydg+jFN3HJ8EnRxqiseoWMKFnNsoWfbaPA4Js26x1SwC0+\n8wDNWlPwzanC+IYbldSBzDUWmq4TbgudQUqjFYkoTrISuB+mLL7DHTWMJiW+Ml2+zAOgDIl9/YgE\nMkCp38EzOa0VGgWZ/GxooceNxDB247AtewJEWEifvOcX4S3Pwrrnf0P5MG3cVjjQnJJHa6Lt92DL\nPWghtV87ZMg5hqZliiYtkjbtDsaR9Y0h1QNdME7lKdzJ8l2bVqqkKH31JxT9syNh2h2DK4f+S3Ya\nfL41q2/HZLVe/dqV6bET/qKnTz+EC/DWuQMYPOGU7Zrl70vazM6bYJ3QWZoTyyQAZV5Mi8D8vq1Q\nJ1QzpHDzXvqoM7PtK5cMXTtJ5Tl7R/HOfvwUyF8npeH9PImCSqBQLYWGKu9TTSkYYrJateke0abj\nf688V6P4WWw8itKiBnggM5s/rVpsnE8MewfTdkWHhh5VdbO4tsDHSOHR5N+gVAJzJNhKKwSA0/Se\nZoLMcSJFtwTKyLKTccNwmDdkpEkk8fWq/e34TsDGCuGJ9+aBQQmrJSJMCe73/EtkhnsBuMpF8T8p\nyPpkkUnlcNANKM/YkFP+vLyqTXv27FbqmU2ucq1o3c8T3MmxFixiARnz/TvvCMMkPpGtuVE1knEC\nU2oCWG+meDh/2AeEpTFnLh7kIxHfrjXzETsz/juiUyp5BRv3yKtJ5rfWbOjjb4nUQ6Yrqkm5mRMB\npXOTha15SAkcE2RYNqjhcXkFAHnxwfjuQewiZJ55DyxigSshOJ/ZKHHr8kh/R4zXe7RvkDGcck4R\n3mcaQPXN6l+gJM0AhXnZDdl/3V1XlYt7PGPNTtIeQ4N3C5kscD106kxzbUBECe8xZYUuX8YkfFaH\n4Jtk9rwskmZP5zEthRJhilFsYRrpRPrk+PD7vc9KotrdBaBZOHJS2xpT282ucl/LF3Re69zRBOL2\ngQDq4BYj4XVrgsLc3rF8UrEmNYVvL85qemjEAVWDy8HqDsvFUni54XqbpsPbbPpgjGaQsEamm2vb\nmug0s2q5kbTSxOqBpowQ11Cfqmo0ZMtKtHuFyz5UQRe4h/MV2sP6+QJ3qRA6fxAdWFR6HGwJuEdb\n9OwU6fLtdtjfMlcjoTRJ9LtrVOBax7B738rN8xvLPzfKJfXME9XbRfcZdv9wE54estcqSOUL3yaW\nuEk43dw4QEY40vm7v9fqNzC7ms/yUnXmXY/QW///hYLaTmo5cAigORn0Huzn8G8TBQ9Igo3+rGGP\ngCtEdbbuL8nUALWGK1grJOvAu4sqn8bDZ3v7mlskFty/StvS94tU58JhJApBnY8xfckPy6oXz+Nr\n3jFbI/+48B4dR9ktDOQmFHEsPqs+ag4fADgtJ7olf525qCe24X6XvJI/dcFuub0MiAmyIfrsB2fm\nxcr7ed1HceZ2UyEATHJ7P9ZlW5pJxw5jret2NIQfozYJ/mON8s4H2Kg0ljAH9hO5WD6mi1rvTETz\nOhsQDTSF47Z1Wlc6qBLr0EdecEit9G/LWVuwBnutR6qPQe+ammRwGV4YUldhu6YL9+D2TpLWy+cz\nKRLo8b/WbJi5AC8rpWCOIcxOVKJMJVpy+ZkfZGSXpRpyo49CFectyujUnpnpw2FJgcw9A57zOkfk\nOQ8DL5bF58jSmzO/rgJuzn1OYBmjaTTH9AewQKja/oWp6xcDE9YJpdsEub/CiBoe0Ek3wMfd2wmX\niUyXlUW/z5yptzbL7HmkB9SsJ6doel0aDGzX+M/LfL9KhLDtZNw7xkqVm/il2WHoEmbF5UlzFj6h\nrCNWSwDyXOqkYOs3oxaXSCXmsxyofqUdWWsBFQknRcUpAOZ8+dS+dfEUPfYvInOSoc3SHjSTV05E\nbXIxa11YgaF/+5G56uPuWyjtnJG0BRECnUYH0EKtwAqOOFLzeRqgw3nEav3aDNFudPw8LMeDp3us\nu3072zNVr5jeNuT9KpqpCjDy+6JsWqFRUovH/kVlJnNfIUeCeA47D2syBO+fA88MYE/5jxNw4WD8\nlGJ9QVCuVTisV1SkkDWzs+3dce/VBhr7kEQSosXMVAWbdO9U/vrEfeXXB0c5K1raaUasetgKzg5m\nV87X9UcC9Oq3s/k5zeSUy5KvKMJAbjjZzApw8yLOi4ejMR5YuSa+5R7nGTJVu2ygwvX7EO8E1+ou\nlez4D405CNm2A255pcmTyXYADp2aMZLBQMlefBSVYgaMdowbSkHGQGF39mlAL3y5St1ZkI4TiViW\n1uLRlDnSqSpXldjdkxH8Hi+uZtIJ9EQEHe3AFebe++rwamNazQviYN+R2sNTI2vifwznO8ei7VG/\nXH9uZmvDvcHdNAWZnPyKrOW3yG/2z2C9VVBXVR/aV9maEuuuqH6WVYn6lISBGhGzyxCK9RrrdyUu\nxnRbaQe7Jn2wj4nb4gJzGpJXkm4ed7SdcJkrEpVOCkqO/ZLOrSr0xUWT5Cn16Y0NTQhgOYcyTsE7\nVfmvl7QiZ+pVug5aKSYa2EHoagTLqa2338sbMM0RVvTZUOZeK+oEDL5B8eKOU33vYFPxBadYswjS\nVtTBijPna9VTs1BWoJSuuUPE28KJBnE9jMo6wz9cobz/zilbWRlK46XtO6NhtQ1mP+QMDG3R1Gov\nwJ7wvel7UQIzTLZCVznCA+GZvSzAjHHljHfTvFxfkXiEcnbDRmkedH4LOMnnssMBlpQVWZ2lM7BF\nVui3PTsxMo6dp6qPfxSdmS7nb1MlmyQ7o+8TjZsYgJAyPNzVwdQW0zmoueI+/yYtMSod8UUgtD9c\nS2IneCIRSMTiLTt8/bnjmRvDvLl3MIMjSf0WV2R8dqjrID3Az9cApWf3fwVk5OA48/owx6XR4r4T\np1ftLIsfOsMOIehja/cDAa3N5pn7lZX4DLjR3TT5p02jK7+nEaW3Ho+x9F+ajOSpl300xf8D6C1r\n8fNN283rzzERXkIqeFFg1F8ftFWXIHuDOcTxP6TUT2jnKwyZyHGNN03GjcfyPqN+MltRMQwcIU0P\nVV7Na8LzbjYbSYeENW/di2pDr5wxZVgJl11JpE+qMwsZrb38SqxRytOov2Lga3dj6ef5YFVbNUVi\nPke3+/uqNJ1snR9PwLR1kN4wsYjcAPF8IdXp0vzPpYdEWyB6b6k73aDb93vx2mIjX1pxtOtkMOi4\nzWQXdvcMR5T5vX5QSHYCdCDLv5RCkcXCyYIgeJrk+6r5HZOy6VHqk2e9mLHckmyZc2PF8ZQK/9kI\nHwuNB9qOo77jpR/MKu6OpBr0BIIdfLEI/fTRbmCPilRYRYXrt7XT9Cyg6FUdaWUNarq0CPjslZ2y\n87EJkBW3c6Br/ugc8/bVt0uGl+RbaExVdDBhNc03eqiWSTbgMyREsovnoDgzNGunfwUVbDZruPK4\n871tOJji7sqJaQhOFR32RT/OXnF4LVeZkOeWiHoGJxGEPu8l9YsJBbET92nw0rALhVXpfP69uOps\nFaAxAQtv7wpyKXbqrsfwgMv+dreQPS0ZNcbkKwXkcLih0Qe+UsI07bXd7x/ADyleiUqeOI4erHCX\nbu+qOL9bVKA/VoolPwJjkaw79i8JS7df27csWS3EbY55DxhwQt7SaCMZFkDLOezbe47yPenP1DiP\n5pMm9biXYMd6Kt4Q04rGko1F8dd37YNbkuLIHuz8pEx2qv9StOHOVhqf+focbxAtNwMFeNV51mN2\nCwlQCazDvjAl1gYqdlPGuunNbCwsDcpc+xXzNxuDIqVt5g2oJ2ozkWb/c52hdtMK11/vuEGnDoIs\nx8Q6/1fus/OnT5MrwQQg8w8/lw7r8WSVW2OPpUDeA74jbvye03LEOQVXxyzI4EldB/bX5HBHb5EI\nM7/uqTzBHdaZNjNEl7B03MwS+bCbTzickIjGjXWuP9chEu4H/ORzgR6N+QwGTjPZLRug10pMiznT\nxmCxyLiSCuV6N/Fbl5cP0As4Y3iDi0QdYQGCdMitRbl6FrQsN5ajaEhS9B95QEC9xMWn5gd1bhGV\nwLn7Nj/D7bIefLMUsypbZ/wBzhFV82g8tw02HFb03EeG222+kGTgqQ6zBp/QTmr+uAP8aUZcyXkd\nYNXNFDx9r9jiNq3jsBKypYaSe+O5GSlWpoGy+nXPNURx2eXSlrEry9l0mloylmXlSDj5bCDkI2er\nzX/aXI3laMGMO2ZWRVfmKuebrCLZSq65UhNL8cxg5PoKCQA+m6WPwROUAtH0PsxW+Pz7PYyDichI\n277u7G+zehm5eeB/W3pIxZ5WDN6t2c9dhIDjz2XtTtpyjHngGDoJf3YZ1P58bZkNd0TlKp4k8uc6\nZGa0p+VPp5MnXnz2/zFMqFDACZQZdFf0rpLG1sAwsIlbQGejUCtUxH5KWqM6ntaYKH+9I3gQXlwR\nHprtNzb8ZXxrfaC0TkO7oPF4/aFuz8P37MaQduOb2phbMYYqFcyLnS2OZ7m0Cut7YE18VQneXPK3\nnCDT7hzWN9vgKIPjbUYwQefrgPYDkTF1OirTA3k1N1UxLoM1EC4GegjulGt6QqfVF2VqndPc79Ph\ngVd1A+LXvpEbLzm+/uTmnQsnkv2rGdZ8wsmB9mFg7Y4RfKyi1gBl2GO9KEvbv+WGsl/7TjQwV3+v\neacvb/kjtZcBr8BdSoW9vlCuJNm24r+89L9p2v7AAGEHvXEa/GDroricJR7G97U6OxKUOOUUxFaH\nfBEnyAQOcH8raV/2hrRFR0JFPwWXMCX2yZrExbdREnIH1fziuRsrBtrPup3hn9J7yYcqJra72XlM\ntDkmCBbpHbS5aua6Rs35y81Ih8Z0fsM4KfP7NiefLbhMymDajXT32LpefTnzZ2LxZ7jJNir8rP9v\nmbdhROWbGAsHQOQ0JgvLRIgxtPWqc0irOgpqQkxT2hBXXZqvCJoND5lyeKk619hmc0a/NVyZ331M\nM90tbi1beeQpEturiie4j9LdD3cjYF0bJ7UphIXRq1cP/GAYGj9WNGBxieuikzpVv2//3iyOWYEZ\n3/+N5SOf4LXepS+16xEKMN3lEDLVt6iI39yfBKjrA1673Q5g9F60a7zcMcW+kWGtqh3wvBOi+NyT\nAFYe8BuSHtZa6AfTBdi6FyrUn0PlqsB2ZKQMBTPObw/tEIZANs7W+J+gjCCjrTN4cYMMVCOUZtIa\n+vkCYfxqmzArhAvdW2+dsaXeoUJhtHnvLusS2wx5sN0+PSCuZEI1U4ZK9+8IsOvjyOV0ZNXMveQg\ngAA7QqBp4bAVGgoe9Dl78Xlrnn1g5a0b+1aDpR4bZQ/qphegUBSHbcQzfoCDERG5W8IZiiR+J0jH\niZWXkyjswT4JRTjo0lMsyi5wSIgr8TZPdg0uHSb1L3RCUiavQrdhU1OdqSrOZjc9LYwIL3IIrlHD\n+vrAaC0clSRh4wMZI31yk63hKEfFvtcEHDPSmOrfs/9HeOKrEt4mLaZs1dTd+cfmFCKieR7OFrVZ\nWSAht33eb3EoD9bUNwFirmfXVZD6jEPc1v2eQgjn3jli3Upbw/qgRHeVhMyO9IIMRojWG6VMCrrU\nLzKPFpoJbBSW1+swQ4ND19t5t1Z5axGUX7uIBPHyewtksDOdXGtm9oqp0xDedxMh4L7NIAPoNU/Z\naoooSM4AddR8t+Xk09wXEX1N3ynKrWf37uY+N3+DMQmQXs5PZbXD6yUXpQ5G2QgfFQq0ZCXENoTN\nwYxJ40lvv2oPDlqar/MtGf2oswbXHNVsMKp9YcGobWrpaRiplFF+grBoPJea6/tJZ/lP6Cn9frcI\nneZ0SXyU8hy4By9cYTsSRUgCL6WphI6YO19sqOKvRkchAjC5tr1AU6bmBClJk0HKY/A1kNXfm1uw\n8EeF5sq3wf/ki+wx2bqWZ9lS17LmdFltPtxikgxubDjhhK5M/l8B6EUqxhutLn3QvwmaG0hjDJId\nMcIdfYgXlwua19Eyidq79z9FhCVv/FspWmoRIFACTSgjrwNu/+Z30Df0qfEeusuO4wxxfzcYf3+0\nfre4Hn5Hc2ehGvoVHHEmYccsTMZCp06IcgQYjzpdCW1XE6w9uBa9/blm0HvHaLctgsv16/FUD+qa\nmMpXUWZo/Ut0mNfuJN5YrUhXuP8E+6fwMZNC09NSBqwS4/ZJbdDaSUiBTlWXxTH8CmyINlSpbZWX\nY8bTEb32M+Xqdj0lGVpn//VunsZ0UEqrMhORh1vEbg4WuGSnEC329q5YwsBPf+QB3AK/IsG5B/yB\nMPKYeuZm9a/KWvYSwzMujlK3Nx7357/X00q1XokliRqEQvWcMJr4RXMB6cSLu5B2prXXOGEn1Y2N\nVz09kKMPDS6TuipfjjRyBxnfQ/ZeeQUnkZGsTD2rqSguNPgoH2K6HeZL0nasPbFuCxerpVFOt4Fy\nMY93eMHEtt7SKCWC/YS/YPH5/LOE/wFoXNzYffXWcPKYwfeN85cibF6g4TieiJTxy/Dhsi0Ldd1/\nrIX21uIdnVUocJEiKxfqQ/y1SL+t4rYG/uXpW6tjbCBnB5XbsrtGaE1RFnp5GvW1vaRYn2ZUpal/\nKy7widgJi15YbAIDz2r3fSLbKlKpmPmyBMooJF4vgW8UAksBAk9z4K3epyMTTYfrARtq6RHZJOWv\nnnXsMKUi8Pyu8+MYEUxVdkqYlIU1dTZHc5I7dBBO2+lqEoXLuQ/+/ACDihtN9wDCukOlEPowOsii\nht09B1LgfxCFDxHlvyht7kTxjc53WKieQSUM6+1K+HaIPSxyDJx88PJ2etzweBSJgTXY0rC6BQMv\nAGWsEBGblXxbGPX2YR36+KIG7Cj5td0NYeg4bwulCNaEwXabN56dG3GYLQ/kcPuYU26I4A1cEWOH\nvRREhNEtscGtpATkOKZnF+jkzDHwyxSJnSiTYE41En/S1OSKwsTbIjA16EvBz1KYc3nbUdG3ItVC\nnsZ1X9amw9nu1OfEEWeakyiXaR0sBa9lnrsYuFkkxyssEpK+WNokv+jXX1eRcRXQkUTFiXtQb2QK\nRvw5ZSOR9Y9Tm0svm0s66F2dBQw86Se1Ip0cgcWfwDX/9yk0MbA9WKpbKm6uoP/Amu5JnY0pTFL6\nkoGTZ0fyKtkcMP3nRAGj2JkXYcPwhzzVwuL1jN5o82YYSbujbqOd8pkW+EOGja1lkOXJJ1Q8hAvh\n01OrjGLJczJ9+IpeULvIgqTe5xMKx7nBywxBEss/Qx0UX+95t2DpHjReJkuRFswU4nkIFFsNJImU\n5WvSLyJqHBxT0vS6yzHorBLc1ILyWB/wrx1oaB3wuS/LMZft1518onsu7utP5SoKMMlnYDtCyPcI\nde8LiSDrd8okEhVlA3qcXTpL7ShrZTA4Hvz2ny4cuu9Z3GAKECMPJO3SHaiafaKk8ZVs6Hx+61o2\nVFKidCMXJY3sCiGwTq6+ueuIhjBMB298tKA/2cEH1Zq6exlfnmbZzTlQ0dq+4J/Ok52ZEFu8l0+I\noQprf2AG1cHlIBnZlTExEeFsodc1nGslKEGtOFNH85R0zHLYESenf235HDKCyYGO8a7woLoLYpnf\niwpw4yQd0cjOv0ukM4IcK40MQJn1L4wjlmPxFnXNklmWie1rvmQ0YqdCz30VcfX7BEfxRY2ZXkqH\ntgxdQE2cjpnbU0UkP4ZnyxL2JiYQRpH6gOhDCzGbyo+90s7W0nk5pZCMcHNjqVyWgS48fs2JI5OB\n0NST24KxLkObjJOCC8sYV5d3HAT/dUvfDRx5nmOHMtM6UTkcBEe7lbKo1poCABV65LPy9AaQ7kpA\nBTuYHsLsnGEJs4yaP9K3tRnK+RlEOXbiK9ZW9Jq1tZZC9N1r7ZiGMMCeCgmt+MDYBpM2qRrUzpwZ\n26V8WBPaSajFT2qSkrkINbaBpzVAer2jRklFSl/vsk2B2kDrThLbZRTW1l3n2xUTVZwrDGOFiiSH\nRyBqf9zaz/9smVmc0z2e7IduQH4p0tOFCFAMW9HrrZ6hsw38u6HZbgP1tPhfckr4U1vJRO09GAc2\nESm6g372MQ/F5CVlv64DptgmnpMQR3L7TwoHaOWq819ICLks16Sph2KFudGaHh+AdE1HUtOcuwRY\nf4ILMbLfsLQvE+oopfQqjctmZw8wYLFvQGZKhF6WvzEKmJ4J4oo/G7QMkLOsqFGNHiY4YKNIqWO5\npSU6Ip/6yc7OSrzJaBSAt3of5/vdpEA6wliWGeH1zxEolrEigrihWIn3KG8zzb6faTaLmMPwU/id\n2VcVmsQwRd6ABtxvO955mSRQ1cr5/FMpswrwW/mgA+l6NlVFVV+MuYpgA6Bh7R7+XhOrE07VX4Ge\nJvHF4sUjhkaYvMeLpM7OxfJJ1L/dHRLjdV68VaeKlBlFkpUslXB3JO45LFFvldi4oANLx9rmB4Hd\nmWikzRyWGpJDZpcyVaFTicn4MnMghc+AcPjhEWJ01lfTH/Wd1a80VC5TUIdddcxRqbJN7L5bYCP+\nY9GSr3GE5hFkU/rYo1dqBe4awUfmCUZCnIVo1El/S02ddDLOu0rL1PbBjzvx6y8iaeZMGL3JQH7s\nsM23L5UmakPy4idXpxLvEIUJ7nySvmycatbHeNAIjQtxF+a2LdH/L7jTdvc6kdzhIIoONP8oONys\nkLBZzGGFyqopf4CDOvVA7BH1weh1q2pf7LNSvKU5o+Rew0VdbT8uvKNvwcR9YSOPSTdSvA7HbbVs\nLxoB0S+tPeIj3x2n1dIxsrN7ECLV2z875vsygwi5RLQaF0j0dD7d+4HBvm09POzP9p7PJ0i7gvSH\n2/meaWPIl6m58+Xr4dDg0PsIIkQ25UJatZxKpMB0Br+NujpmCoRp3FOvU+IwDGqbk4aDmzDH984C\n9Y/+f6TVMd0/HKCcGKUehx4wm38fGlSgCfBj0pgeR6A6CwJ4yDdqpFq2f+05I7g4E4oEfYNsTnyd\nWZ17RIsiJGpXWjtTlCuRcnEfxCmNMiRxLYBFnOXKwKzp3v+ZBQcn0BgVvJwK6vrMNvAgWzJBqyAK\n2TZjvXj96HARM58bXUZci3A6vNPUMueHy5BYWKaA5Nme91zLAUy3fHNqjBZq0ru1+TLXsSLCEvcG\n5R8HT5HjC74LZGRwQHXvoeEIa9mIfTbuSikUKEksP2BFs9lYPl3394wYudWyTeV0EVch7FEp+k62\nQyX4hPAWi1YgvQWL7QgUM38NyMf6xZe97QbtJjcnisqODEzVJKrz3gx3HcjXnA4OFut8GYuYPR6F\n936rAxSZMo7GSbdm/vd2cSOLP7YrGaiFe30e1OIrcZYS5H1AXzOush12/Rg0msBhuggqCssbAd9w\n7b1SuzedqsyeVwY9/uNOQTlHqqOiqzrp4GUU4uTK+XFSrXffIWJJ778W4mPA2JGuxymH5sgKqT0v\nxFir40jvQLza20j2OIxsAfv7pcCBkDat8VXBQsXddhdUnJPWhtF1wdFf6TRPVXs8OMja7+s048Jf\nodEN3KgXUlOAxDZUi2ZyV0XYUoFuywfuArOLAW45DVn8ZymEmjqajPUYlTAttHvaePGwDOrycdE5\npxfv/0RY0y44uTeUKrynIubj/iaPjzIv/Y3VfiarNf3hNywr0pqWeZuRlD0fO39z5b7n5AzpRGUr\nTdSEQPJ+zYe3tlBkGU1sRWorY9WUMbnTMTwEvavhpIs71dftKj/lHR/dbZJovp2A764OmTo2PWFQ\navq4atYvaNpK3RyGyhLRFqLzM00Hd0e6G8iqLKMpZrT+E1CvYgZytTbkZfU/ivoTKJqwQG7HuKsd\nqBgE2zQiWZO+QrJrw6bU9VKlQvYE0PlqPOQ2YY1eUKftBx522sOWNwLRBt/+6aahjNlNbhlwnLy6\n17GXCsgGbEqE+WoVaCDXFbbHIvpf5guRwHcw0t5Xjcl/ndGtbaqUSK19JggqsBMTguoBbxHxDI3e\nfnZZ5HwCRt8dQnGLcX4JXBY3+e7PP5BbdL/ZhGcUc+Or5p0wtRSa51DlDYbEA/13vhJd/pU7RD8z\nhM/Jp2j2Mvp+1CRqJnX2X7FewgdEPnZa/SFA8LtypyTcD2YzL0YztGPRBK3yK8Gvk9uCcrPFy+zi\nQkd2Op/SI7HCUFWvXHWgDG9YprY5MobE55jSBQ1bLrQurSUG5SWpzGvA5BnRQX1f4Sa9DgLjNBJm\nlFm1AYSk3Z9lCsQp8NN4/8WC4n0pKORA4MZ+9bo8a2ADVyWcFHmkCZrtxV0JZ3wgVlCWKrk+vODR\niclLLPxuYtI6hWKp7gcz0S49c6Uuv5u/TxYt8S44wTqdDMQU0T7s0z6OQjnX6m95DcfywmHT2BY2\nXJjeYh4ubJ7GqLFY/XCaF3IyK86Yb63293sFUXnrIPiJv+9qtfQzs6W1Zw6dOclHZeCoDw1Ghf8i\nu+/8ZHuSw+NB3t35hB+fQBCJMUxx9AUD5ojFX+OK6o1VUt7Q6Yy2uQ1h69PsaAKYWjXGo0lTPcgS\nD1eMzetPVz3a4qLzdXWgiuhWPTyE5I5S5Dgly6SdyBXDu61bURf7C9lQXcNkeLCiRwr1vHNBgxcd\nIuOGRM10ZQ8dfVC45gSC2K75r9t7EsPHgStBtyTpEyDC18sFfHPTH+Kp07C6cJyXc1HXgy0SV36j\n92YhSnQvp6fLpJjrEdZrreUTRL0v3GgHzHAKp9OIUQZsHCxKq7ftgOcLGQDIMRCuuvSoJX3GdEan\neJnzCYft1/5NVPm18/czet3AyNpQmfNnRNWwkVv/PlSZcytYyYZl/oWMCJ0o5jNYor8Anj0z7wkm\nUOnenhXLNCbWQEjyne8RqRsIUxISCGxdlPqMY50Dv43hTjHGGjwXWu1mu3tme7yGF920gNm0qzAd\nkjHayykFpZ9NAMzSrBKFxuBZmOIy6oBDeGrLWWRirFn3CQKPd+422ue6EuiGJ/rAFeWTir2OIrhN\nW/hQZMTGugxsr9AcGFNkGDeWW36e0h1Y0FjLAsk4Ve7yqdZG0RDeuDGMFkJf0FYhGvchcf2zFvG6\n22hCsCNDMIdU/lDu1CbApgT/HhDTBXSR/vxyUTNI8DSnyTKAYR+i/4BoYCbLOt4H37X42BT1SfJz\nDIvpSm3VBvwCXONEHl1SfFfTHdM+dTeANZGSwpR48+gXtY8W7kB/AqSTLaC4wKD0VK6kKbnXF4Y8\njuWfPN+bWushbSUxApGq3cYqXkpncjQAlb6+Dhorn6QuQuhHeXnmQdOKF72OTq/0Hc2PPdbzABwx\nvLKyvbJKmLNU5MG75Ee1hLYpP3I+Y1kyHQDZoSnUlYBfoT7sCKMN+u10rACQN6GqRyaEnI05Q+Te\ns3y3EwdKvDQP0vxyUuteKGONM7pd1YC9BuIPazmB6x4yOCI0scBYOa9oFBjOhEJn56FUco1wQiia\ndi7dl3QwUhZcyOvFxqeEitRk5rOFXjGGnW84GplR/W6+6ZqV3aK6vc8bUiYUNNtAd3NY/74PJ2xx\ncl0QH+8KiM6lw2SywWk4aYRrzIleOmtwW7yjToBRMz5c9tR9IAQ+jC8LI+tP+/MhTi6nligW/T7W\nxNDZFZZqyH4MrjQGHdi1Xx9MPR3IgZFfAKKu2uGXkogP/+ZbvKxr5U+lyZpmPMnJ41up8ThHKrcL\nCYQm2MDL21gTHXC66DZ490qXRnQ6lE0lUBW6q1nARcol23FXAkswX1fbhsoKeX2BRjew6rPRl0YE\nTorCGrvm5JS2PCK8NVMxih3/bkMWIGMAsc9i/xf6vrCLcVZq2qHoqYAnTXkdap0CZKyHUWqMK36o\nIQAGuyZAvGiagrMLeRL13Bf9oh+jnwY1PJM3ZCqPy2LblCZLktez01LMI7bVX7jQhLLum1Dq02Hq\nFwoVxeiHDtjsKC6LeMSQxufMXaxcdx5LccSwEWrJ5ucbyaj3FwXo7YLe4zM48PNUDs7jKQaSvmbX\nxub/32lxBib61xD5hTh6ftDNsUMl3aqVC5Ev6L/VwQLC+iYpGcyMLDISeHlNlGqqbzU7dawE6TUa\n4txtw8IOy8EtPAPBOvRWAEU6ilJsQdliOfHHCMu27vJppbZ8UQrm1yOpJgAo5Rq6ZELSgHYYQofC\n+X8dlukK8rKgeRFgKCTiaGkPfKNkH7nf0HBEP9LswtiY2p6OYVbNruFdn0CRmhaoU2Yp4Z6jEzXx\nu+ROmiSJTCd5mrHx+7da2+E7wRsE1bWcBtJAO6NiG2wAyyaL4TFrHfOItUEcVbU0OBH3qZEMl7Q7\nfDEM1fmGu08MDy91HFc2ZeGGXfiGK3SYg7YzTO1bBkmibciXcPjf9VshLKof9iwKIYiPt82CbctJ\nI973EfZehF/f/F8WB/cUnNEc6H8gJfCmaEAsnnGZr2H7V/opeGUG2TmR9YC42QLKDJ54kv/E6HME\nNkjv8/weCLW5nTwKwqXbefV5MKiHcJSb/XSRkTAJMOvo8SOp5XYWDj8kj72xLj3vHGcm1F+WNmJY\n6jz+E5EdmAJrMMcpEIPvAwWiqhN2TTbdpSmpOy1OupQca+Eks0P6Sr36LwSSGjE5dBQyDFwYu2Tc\nYamtji3gCOeBw379UK7dc5AAPQKxtiESFkPFDBiOh15JjTbXinF99IQmtzPzVDvf8TV07lmCEODr\neSE6WgNAw7ily39cPhaAYa/qgK4UalqDu0o7MDW9NsGNwEqXB0xJGQCZVft7i6fgo0NEIUZzGGl9\nthjoxeGJbeHboYBFZz+kcxTE1zIcwrgNx+md3rBhAFwmqJcJykMt32y+0rMC3rB9YYCzACu/OI10\n4rkveE3AFZINhaQvN4RwfAd3Xpb7RjjbVFmXlGBSq+OU+ixc+WUfabgzxug+my9MqLz2CWVosPJn\n7YJk7r5WJLod5XXucwc/ajSznwIKExM1XTdKX9P7RTbXZVGIV+5h3/RNTLkTuN3I3CRHoINNX6oV\nbVLJln+tsBlyYuKHztcE3YMeTLeJU95pl++5mDTg7wDFyhEb+9a1KH9K6DmZLn//uWxMdIapi55B\nEWTgW2wmil2jkQur9IXehUdjckfCkoxaCFl8UMEm6zVr7L0aB4zY9tqjFbs54MJf0kxM2MibPgdP\nn+cBddFhclB5DdxEhU1Lo/qaEC0rvj8FRvKJp5BUPHBUv7QRvysfufpvXwQQ/qwdAhZJA50QfYyZ\nxJPxOI4ODSqOxj7ZOSAvROj9HG8xEecwh9E4+VS1MqbrT6xSio2mf0uxJ0Ede27e/6uH7MGS2LPa\nLkONio8sQ0ScNI0R5IrxRt99iGRCO5DpCFpoP6ZO6UAlVRgmA1StmoIroRyhXpMtljl0kEd9bqLC\nblYTiCXL3JGWHXOf4jOAFxcM4a/Hw7tO+bpuIiWiA2cdO8fq/t4Bhx9dCq2G7oNEJTrLyyXauiGh\nVGaKbvRnCytPwULpEOGaC2kZhCAbg8u5hEr5y9jgUna4p6G08qv7E++4PmVCrvBbPFCkfpwUQQTy\nVvk8LImSfG6lN0z4GTKrpVgFTbtaIwLrd+Enljcaodcw914oMZ5j3zfXNaOnLkqO7oyGM0TmnaG9\nNjEaJi/2obhfQ2sClDuNA08VPLyKZAemPATAFB7F3bjsC3LEja59m4dAWVpwFwNyaDneZVRoj1JK\npBVWxoaTo4VZvyveaikkxppjhWxmBaBZ2T7glPA8vDQoGgKS23AjAQ+ogZgFSwFmu333u4BBFT+W\nk0sO+YTptynZ1dtu9ja5fG6rGht0qtfYor8vjKidvCD8ROz9b3QQRwENrvhNZ+U9LyWpyXcWTIPW\nFP3vo50+MXQwXllbXQ/2RSQZNws70N/PNo+AvdJCO/Lvfl7xmSAx04JG0WHOd8PkRggWOXn9QcUo\nB6FxgDeOK6cwPRVSocGV7Nq25h4n2KPw281qJxsF/KVfUiQYJe5Dnz/OXcJ15IaGfntXoepjHc7e\nLSN24FeurD4dtqjHVbqXg7Evkss99PCzBPZyxGOXrGwm0PXfRvW3okVYofI8dJtDLWa1tKn1ZIN3\nxDd6hlNnE7VQAZKUUEWeMK/9w82IBMFcAs8d6AEgFY3s9BCSGBtZ4fYmSFY1Nw6w3Us/MRVUNYel\nqwyVKud2mV8oWMW7rkMvzPs1FzuGimzBYs9TtH/1iDjASr5eb3zbNMuQOj7eHs46Ht84eXtaVok+\nOZPIvnyyY8wgdQIOeWdwdIqaFbcSMjrfVCQzP1rvY6VUZzbYc98TnmUFTrnH+MBB0DVD/8Cf1OzE\nQDCk2LcLzdP9nGvOI9m5NGq1Ozq5xHkGS9yzeJ1XnH6UkhkR+SCxNbw3TrEjxUOO/dWA1XgLTSG6\nQE65WWUiMT72qi+KPOog48jP8IF8KC6S3SoDlDCiu91I5cpMp2sohBsxkvPIWfMeczh2xUJGSaNm\nc8MeS5yehNmNN0mFoT4EfAcNx4Sajga7aSeS8JRw1OThYYZA9+cQDAURxdULzYRHUn6VQBbwDW+7\n2juDLAKyxMpt0+m3q+HgVaW1Lkt6ow1ca2Fx4q3DM2QC0J8z9atsPQ3VHQmGsW9GP19ojy0vcvmL\nSWsT0dNxoNuGZw7XGyl5+g72tTL7O2znu8d1ywoU+4ZPCxxWRsq4UI3oHlQyqWwjMBTAfB8dXqli\nNU3zv2+dWX2ArvY0kjZLGeK6Jo7JzaKFQBECwki3mmhPqBZofTYkESoot5f91MtW2Cw/BecM/8TO\nFbhpAUiGENgihZpQYRf6tmAdOmIZYf4f9mDj8+vtpCZb2g/k2P/mTbND/1Dp8ZT/jdUUnO4LxsD5\nLBGDoNR0avxqEbn/1Sq+DgJvwI3DdpKO+vGr2UvbrZT9Hs43w6jrcvRKvd4d0gtk1c2PHez2gUNn\nLsb+DGthr/T0KwXelWYm87rOY9L/9mtlgP5ZkJj9LXEX/TX3tniB5KW5iEvNsbO13p8E7ZOaMfZc\nGH8srNqKA60SHtuqcuuIUry9l16eAPUk1cTr2KktKT8P1yGxiC27q6nI8U7QzyrzXDdVPl1ZSMkp\nD/s21fV4Nr1lcBd5M3AYEVJJdwiwsimbgv3t6Ypv4lP/Jv34tM/6RN/EZcTApJhO9lSjAjBFfHC+\niZv4mqsQXp+Gf1UTTjYYfslwiu4pd8Rzu9pgh2JLiBOciSPylg5YV+qeBZ7fM6l2P6LBfLRfGBYl\nJevTs7O8G/sqLQXtUvMnWLzwOAxvnp9HxFZ0JBH96ummAqU+PHzxTUvOIV6xPRKlec/HWhCcnJY0\n9TVWMCzKgepp4dr4EF7vt06TVUVigqa0AaYnQ42iOA1IJhwbVVhUUPhkvak3/TJZ2nJdeJxzMm9r\nxEjK5wQ1StDRvvALBFVMEbjeVsvjmrwnXkhKdwg69A+MnRo+36NdxFIe9jfU7XoqpxSIS24I/ppv\nDFvSSyV7/4BRdJvHQMZXYEq3BlwGcsRb662HsRwABVWnSsbEYOwhAvbX8javeU50IohiEsSmbanA\nh6lBCedBKl8p/4Me929LiRa7h4/pwXwqJv+hNO/Bl7C0w6AmB/zEgnRrjNm6lngPVk7nPS1/gmja\njCbhe+oQRo/7+Wmjb5Lr8LAyfc6kxj8k07w2WfDmD1/aqBBVNzdAmAx2q2FWedVFYi5m0o83HuUt\nHuRtqDn5XMxT4oG71+LZ2LkPIFkfBXah1akgR6IhjR+jzcMyg+e5cGVodiGoEoqUjpGsBrsXmmE2\nVpdWTvLYK/OXPraQYSfPO8JwLe4DQJclZN89VNIIwMqBimHy65a9Z9NjviwAV9PbzKCpYII7TvA4\nB6LDGvMnOSbgBgKUCf4RXtqpN1LiclvKwQcAb5ZI8hWvPO15g++ENXyLcumhRoKgt5pKgtxjIBZF\n9fsflmX4z7duanemLvqYXFKfUj/EiFXGv+VFPXZRkLpEUJbTMgwwvUtHMahVc/5ZVK2mu1QfnpdV\np501GxKyIuLpwICvGhITbHzzYhqlPfp3T6+Zn7Lddr2WSUi43f148K6/FAYtkUV6rTSD7AZYe1gk\nbzSOF8C1XbScUKBOFMxuDbc/hJItt701oncWHXPbXq5NqHDKgReAP3Ac/gO7f4aHV7bOPH6N+RLH\naAfAC7JqTDDyXBD9L5C93D3EwhMnzUurW/2CkNQdZdwIe3z2nQqwfxNAOhyFXtGb+LK16aMfT6ll\nobv41quvQJxA1w27vxROkxCrqf8/JLCAR5al2MgZfq7hRSqhHOR5Pk+oyn2VTVuCcrl63gzCM8ra\nN/O1OJokBIyduwmmh1wM0C4jw2YAKkx958FYH3PDxuJ8qusnMn3qRK4Idza94//7+buOP/M/hMZu\nh4rYBu2ZHdAJzlRL5VYX9LFT4BKv7u0Iq3i5BHr51tUGhOE/saH7rJpXjv5P3iqBKo6HghDmRUIO\nfiZ1Gq7e5uOKRkTRe4sguoIuHGDN/2E8mHQJOw0RBJKEp380Z/JZy2Ebdk76HTqPstv3pRRXkoUf\nww94ZglvbQPzhjCpTfASRq3vR1rj/0fAzNlHxFiRmJuMv7aKyF4JRgHF9xx4w8M/hcMD/3BqvoOg\nlKeorVW9coS8Nuoy4pgb5OsF0YP4nCft6omrU/CzPceNyD8h7sf3cgRjsxdVX2BMkrcluZ+N0A62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i9yeETstoD+8hTfbW8z/TQiXa8w8Y0Utxr2yBYSxfd6R5q/UVcZj+2Zann6qAM9F/mDLNh\nk4UkGSNyAZ8aHaLkbSUI4PLeHVSItCY1bZEgS8cc7e6Up4KGRkBL3N+1KOhIfEb0A+V2y3/SY0e1\n4kqqrN+MXHQg9vJ8ELYO5NqStkEfiQbE6qJHBtRG287cltT4aNrNIf2g5gU2UdqjzyaU+G0zGE4W\n6j8TxpM3kCLBD01GYHkr9PruXlzFmmx8hM+k7WoW1pTQut6e8DzTr+smg1fZG29YFCbmlqizFj4y\nTxl8GEp9ncBxMAGZVCHnZ9iCWmudIsUnSTO8LrZKedg6CUwn5HKgoJgbOZ2LP+b9EdUwzz6j2xPV\nrJP2/IkOyeuy64ud00TaNr+51sLaA4s+mY72cBHCqr5U15E230Nx31k7PjkG+/aaVeQKP5EsWUpj\nqgsaLWlK7MpDyErA1NZ/neUPC6NPv0DAXt2ltu4y8EYLdVVenNGMmoj0Z0M5tlVJZPVFcQQBktbT\nfCyx+KKeuTuSMXfUtJ5H+MbAKeomhJrpF3TyoYAA7qVp0191/8AXFiYEt+Ty1oSVgE4ZB+4qLesA\no/sv7HWuIgQS4vxJxytcoZhS9dxPps5GVC7aJYxfR9IiDcR/Bjk8supfnDH680h+cIPfEpvRsHUO\n+9gE8hnxSGe/+uXFQNThSR4Gs1jAz0ZTpiHlQaosvF/QKUYPG64d4D2p/yWsyWrWuTMggwpciSWx\nl8eA8BMIgZUJPkJDRm/snNmtVSG1aa2ltDLxiIrjL23K8nDJKvzEHLnlt4gxuPydlvmX1pZ+vpeH\ncGjI7qs443Kx5J5KfMc9G//wWdS2zbHh4243MkceXisEbQSxcB1mGPCt+HQfMtqc8vilOaXhteza\n7PvSdUKCkNYrWo/NPn5GpklFcqxTfAr7s8JfsIkIedV21ioIPV8XM/M22IqVN2pocJlWGW5HSaP1\nVTrX3Me/8MnZkF518VUNN4S1oAc/sUsxZjjIPyQRa7Wul3K35ZCSbTyyWwdafAwk065zGLzcpU8W\nsuyf7MySykopw6CyF8pbtoNXSyze0z18Wg4wOCtxRjbuG7ofuI/f+JIGaemky6wOD10GfftV44Lf\nUnTFz+L98+wxt6ZG/llzoVtXoyCeYHzvSDBV+zwj3u3c4J4Igorpk8BDNeQYdnUt0TxyVX3/+RwN\nMADWDIlpiuwPSjMw++eINFRUZpISBOZJDGqhIGA2jB4IVzEV6ns95UP2JwsT5VvkEHtdftLjVgA6\nmqFkX/m0N62yapAfPaFW+nGQx9MDY6C/uJb7San6J4SGD53sHsncQBWizfUl76VJYj9i4184vajX\n8IrjNAxXA3oAF3MPv7ZzRlxDlU7kAH1OExb/ATe1xBrvIv6/1elodSSV2LHbPeoP9C8ZQWin5qsW\nbgNUzZhN62/Y2Fm5S+RvVbbb6aT0rx83PDuuuxhKiGZuj99WwKqWNK4DcMlWoImC9kPSof3dsvtZ\nStnDS1VyaJbA5uKaDNsJOeSNIMaAhSJtQc6QAbFP7/SyIh7tQmOYlNSKy9Vhj6WVAPt2MdVxB7Ds\nMykJUiUaEBgDH0qbud++zyDGOOnRonaypGYVwL0Qhkq2KZdEnnoQvI+xou43+vEFYNl2LIMwOcHf\n2GYXdd7raz6MEuJWLziNCpS1qsxw1pa19hmUvmbawtJgv13uA7wMMh80dP/YHe8+vJjsfhtRMyVX\ntKdinqFYtPBHxsTKZf1FImTCp5y3/suJe9aPpT56rbvHMetZnQN3GeI7tQxLhC8ZCT+qt01+eFnQ\nKDRe0A3hs4qm3IpU4GB9G6dHvHGobDfMI/7D6q/06lUJxbNTLj0BkO1jp6z0Zl6+2UANrMN/zZ/W\nxnG+oKN4JdoVXSgkxAYMwylw8Ntpdm/MQstZ2M9pmmWxFN1rt/3qsf542vdM09ErBNXWcMSQGyf0\nsiD+sz87sIEaXKHcirOxaUUGL+Mj45hM5HYDhJymIdb37EATsD6eO6Y2VyDyZvLgozAeVu5/Cy2g\nTjhsMoQbEld1wo08nZ3bsqgoYTFX55esFVZbZZCZSioJQEGI1/PB3XpUOqzCpqDS+UnQiRAJTVQ2\n4EoH0lgwEQ1pKwC+hvQ5ob772JWQFGdTnpZ+cs5RmVBrQi21+TMA4qLwttTPw78FJAgKTkmQmYBZ\nT6vfM3QVM5TQ6TAzAccky7hMmQIKsM2IALKL+8oVAQvdzCsfze2Tbdg6T8eTeXJklAtR0kxigE4m\nmcLHCAxk5J+f9y0ydq5L+togXUfXehyIDhmLr12Y+JZ7XQOo77FngqoZ0FrF8cYmdNCJJlyeYH7B\ndKfobK0vjldtOmeVebL6UcUCvARtYDNfHDXPdplGKkZv0eHkkAgpfCxE3Tb5MTpv4XW4fF/K6wQ+\nqiYibhaWutz1dTYCGFJz/L5alrTXwRVDjDQnQvHvyfAidE4Rkd7NshMKft+RCQjkgBKSjLLgZEtI\nFtMJl0EMgY1kJctUPjMeI2142RNtq2XENCWe0AvBioW1FFk+Wz2WbnNypHhLFjfe7JZEC5txShIL\nOz9CarZ3s+oOWsNsdqfsNURBKCpTZ4jOUoGrruArjDU4wxpY7ObYYeaaoPugG1Q969g3/+d2/m+7\nc518CvzlUP+9DMn2jvRzKlsgOHkrykvnWN9eEF6TRspdegjvxENyHAn6MdsvysuIZ7Zbr5R+UbK0\nDYT2tgVSiwBT2zdlwHvKkwED8tnjchsMt3J1uC4dsTd9KnbymLX52S9njMjhkCBBtOUvIa/D+PX9\n+ltaIK4e0FsVMFSfjyrCzCasohEPpj5ISO8fR+s+t6V/qqRU3N9fo1FkP8ySC2jVza47kC/0O2sm\nJDXEMl6eJ/OD0sDVNBdhj/JGAiPs5JUgMJlQzCnl5wEUzogJ9vtZgNpvkpe8h4TQ4EMS6Fo3geTj\np+Y14iUIkfMsnVyHfmkGwmZL59Uvxi5/0v/I4Ox9c5Zpvpz+ANPf6hv/Q3eVo8jAauhNIhrS28gi\nEJyImruAWsi/SwCQ0mxtZS7U9X81Dmadpl6hP2alAVdRh89SEWdAlI6TB4JZvbrONmBsAXKS8vbW\nPf39Fv37mj4vErkaGDOkcHsX1XOlmVdMxlSj7L+ZKZQor7M9fE3rQCj9ZF4muxbrq1gJrOgcevmy\nJ1l7Dcu/Vo0/xH83pWWjrzT2wdbjmW9IBi/mFRIl9U5m/9QGqB3l/7IzOLxZlVY9ZnxCVVYOrzWS\nS76m5bQ/CE0lis4+Ewm2qCjrxRaPFZWaMONG0QVyUqezEBGU03dhxAqW7U0fxAXvaFHxKMISxgOZ\n00B4cvHxWH/yUp6/MWY6TMGebmzv8OtCeGY+LEWJPyKGAipt1X3ZKLdT8U4cu5b0fKBs5iFBI2XG\nZJdWlsOQRxMsc+k2MgTDxrBbyuU1F6eso3TKLdgPTpm8DUwtSGuubm+BwpqbASVHiPj9B1UDlJ2m\n0TdCDDDcBP9ltrqS2bzigFYVD7FyVeaijnaTMcG6BaAlRbtSvRW8eiD4gG6qQm239hyMZP3UK4SH\nydbNldjSBhlP0Goh91CY31B2lQ6DU4wGM3DJJmIj3U3m68zSxtGy+A1JlPMJ7l/ngSbnoWqbK0/X\nAHDwYBb0/rYmlnFN6+6LXtCXmW6jKH6uBXC48cVLvT62bt75Jjf+k0TR0LN+yqPtOx8UqQYtaXWD\nQiOJSZJ/Jwahl3ITi/ep34rP70Ey4pMpOHvLZYDtuXXRaD/ujk5NAoxaFxO2u4XkaCUkhnUo1uy+\nDCJs0tGN/XfPXuW8/wLdBnuyt5kSqAG0B6umLRHd88S4RagAJLVlSYf4NHSPcOsOYhtO0xWco0Lc\nEra2/vblUfyh20g5aYVHEyBvfV4+BBSEUqxCda4Tjun95yGsU9V7A/+MGLzktyhjMWvva7WEJM5G\n+iWb01HBPvq/1x91gWOBnrt41CGiCorlEswT0h65D7J9sEmMjhRAuPWkKu/SF2Pcoc5DRseljnLj\nETYTRxT76sORC4rXdgP+1WuHROUD5jGjsEmaP8NH5E+dQQAXuiktu+sYc5g7umij/kS19njtuWzx\nKo6lLQsVKo0bLtUAchbM0N4CzXCKsA3P67NvwDxmwDYGLiaaFh3WNP6Zt5CeTnWGpWwBMSYWGWKp\nwFB+FSonEOnp/lqMZtmH3uXLqLqcztHySPcPyZlff7arMzpZ0hWix595gICp1KRKyueN00N6aRQi\nbxw8g8ZptYIcImpy1TVWN0+lcfJc4MytynXPcCcscpWsjAMqTvxFar/h32cWV+QNUKPKZjxmk3z9\nyvLZAuTX244BP9CM2ak8Gfa7u/zPVWEW7bBtLnribJ7iNHU4gcEKiDFj3ng5f/fR3Q6TqiDEMyrP\njC1++tj88uDAjk/CdgV+JcdMnQUNnmxz0Pbn26oxOBIqmn8sWf0sbOIxMdqPZJbjR0fvda67rWPV\nORErxw+22jilaAZT7oIudriBAGFCYnSwR49/ymqZEjVdfmSq604xtPzTbiiWNAj0sm9H75L+C6i/\n1rJ5V8PO0XhsYYMyGd26Had7Hdrcb4rPwWdlP9tE5iutZmqAYExp+iXVJgFPeYqyjb239haCq5jv\nKCF50JoUT4srmWR+GAJye+VOmm1+j6Hpa7jByWszk7vlfdn/j9uZ8AUXXBI3cxFyzCwkidtSjfTH\nGux4KRf/DjNJOk8oaTAoNeVTSXGXlFx8Q7HckSLTETzkusLY56zsZCSDHso5he/CxRYnYu6Yd53r\nbqeie08UMavIg1E0xw3BIqgErdZl8jsUeL4L4bCUceEFY3mgZcP+yAPAWKaqdEzlxrO2Zfv++9fE\nExjo7LO4XSvjTg4dwKvHrnTgFyzS1V622jItmO3VgEcktbPzEPt74PUg0u6SOqQfMF/7hRXYTuTW\nXn1mIYRp4EuvIkpjL8sxLwHePoaA9mNqmcEfN5Dgt55vuXS38QMRAg5Fi9Ll8Set5kyJnz3z70b2\nwhg8lOJwXfVYgfXYpzygqCrIHD3xfwZ+uTMXr5nJO1c3vmgl9sBNobm0K8I6Bap87AXkapqQizWg\n+OQBC0aEl6a19UyfovgjAxX7EDSHUTtvyWNhuSl8RIA1QwRyWN9LI8grTuk0L0ZQBBQ7M/4CvTi+\nHtwCWlZp5U7uuCyXK74k6zU3BRRyTmLYm1IuW7Hm1mspLqBD9XIpqzww8H4ZwynQX+rEBN1K8CPq\nNheUH1ZIBjOTpQL25m+XM+8n6RxDh0WPrTL+CuH70qJcjeA+EkZRkUMhcPnzQKMIrl7h4SvtZDVH\nWZU1FMMSFowjMb4qr2uWFtaOW4mSi/YcLK8z2+gW/XL2nuj4tZMXNOeOUqu36hTK3WmxZOrD7NHR\nBxCvhBWWPHuaB+QZpQv0tC4O1OLiiVV0LwikPoO4GXij+jdN+p84OlxN7yZRQju99Oz/9G7oT/pd\nscnqyNdti+dJZciyWRp6z+VoyRsinReEV5wwU7atDTgqHVRdAZ6Ro6LoW5ItzWJRTIN8k8ohbrd4\nNkMCUMfwKBVkzmLJhpGI3H+N8UNKMUxqQOK1Tfg3xqnUiR3PboovW024b8hiNx9DSiI0MKwOuqjS\nW5Z05V1l/ef7uBZYb+HjqeNih6b4Ci9fkwHqP/lpFjJ25Vs9+8+zSUj3I+HOBRXxSIsPovG9qgBL\nJ+p1DpJHhGm+TPD99680k1HUZzuDThApxzsxHKUT10ZkOiSpizegKLnxUZwKbSk+lIewRSUAzdA+\naz0kRSSptG0/96oCHjmucfvoc6SzKF7caAO5OoIqAzHrxcXQ9fP0zCkhX8/29O+3MRdkpDWlA5f+\nyiS+F6tkZFkOdzjrP9TSdzwAtD/beahQzo+Irs1tSc6kZKwHZPOdzSyscxgAjDTEOM1cIAeyRyi8\nHIbBewYjEkvsjgyoW+MqL4U4BNMcgeDgK0v9+qlOnCk+Tx+MjtYpH4uqsGSAN/fCyvrfl7Fh88Ox\nxAzuEJoJTfJI8CHuN5IsFgknw3QIjNt5X3C+5g7Gf7LDd8vFWiHOOyNbbqpU+eS1+lNNxR2c5kti\nX/tHqHips4nlXiHVsOf/OuyFV4geDbvl9kqi4EW1E6jStgvXOOYenl10Cha+TbPv8G2IkBNmjjga\n2Kgf0Q+5g8Li8rHnV2TSMqRD6pMp6xYrXEYRJo//s6FAz8T8W17RHBdvAIfT5CtXS5UOc9fFWYrf\neXqvqhpPEU2cYAX/jA+AKpHf63vAGEoKFMkFARTpIe0VkM7sWqEL+d50y1BgyLl9KbDhbvwgA5op\n2GkbD9VZceKVmZTnWR6o8Nux1PO2txrP5v/SyOhGUaLLIU7dyiwBMJ7fTuaSIkvbhjfuz4aH9anC\n9yy5OhjyS7X4byt3aVD/5vbOdTCqWFnt9RaEhz70KfpfS+B+3Yapwrh85Pahm0RrEn7l1LOTzIQC\nyWwrUGBBcsmpzztqN/v2Nki7Irik1Bu9VIy6Cy2MGPurICSq7V/VsRpkeESX98g1Mru3/vAi5rFS\nPPNRgNEsgJ5lgIb5eI+uh1MovKdJatjpyu2QshgDXLnXFv65sLGVUUgTfF7sJ30aGdRftr6dBQux\nzVVw8B4r62IUnsXe53n8GiXDQOtoA649hi+EWFJswNeM6HMccvSymbWP/cayMBUh4MA+SzWeCGfd\nX55QKy/WqAaDx2ACumERHe5wPHBizoR3MenKf1EI+xFxU9UlI09TwUpE6ngZPnnHYXO3ib+J5fT7\nU5FnYxnJ1h4gZ+iq4HwNwWHNiIibr+QSv2r6BBvWpsd92v+WUr+1hfICULhQmVFPecdwQxtBYdAw\nT3kH5S6Iptmo+skNhd3VB2PftYvWubZ1sye8RSBVMZYfxLtSVJ15f8HB/YtPXhLV0amp8Sa8iz6Y\nNnYu3llfkj5t5TsQwvcPLExOIPVuSoW/up5IMA9D8Rk3lHEdo32Y8B9/vqYYLbmr0SG14CzDc4qu\nY967Guw+Z9CZZnsszgel+NnaVhwOLGlBf84upBxjxZVcGpLgVsa+vRAaqFsZHzWZnn14stTY9v7j\nq8+8nB6tEG7gA5bILF/QR/IV/fhRA3fk0RkntoAsq1xLT8im8/SZscrlMyduWRz10rGASerQxxcB\n8oCU+VN4dfmLNps7LFi37appFYw8ure65Hf5+czdVrsKy+5BNu9pkjULkQp7YVRZDNyUXvGbtwXy\n0MO9tRcqRJXc75jmzwheFt56hLi7ZIw1FCbpRe+M/g8ctTjPaLnOrBK84nbwwcUMVA7mXfZtw0P7\nZ3x1p3Zh9msVIJVHc6OR/w9naGz360zBslZicSj0HdmfM/+Nh/NbwH8tEbLNWyxq0U6OfmIRpdIK\nrdsrajcnVnV2n3hxKtW0ToNw57MPSBX6FJ5+CaN30Ww+BMOR46iqAl8qQ3MqZYQUYnaLw53kka+6\nvUaRmd4N+xMIrA0MhDSy2/ehpzA+CpVkD8yn3/OGgOLliXAUwpV1o7pDbyZlXPoBqgAWo1fsricG\ntV8oyAsqhVIU/xGp75cCE+0aCn8OKwlRC01ijkZVLDaDjPry+OKMKMU4VShABzVyHUOggaHTkEbK\n0JhoUYvbtpDNMETWDD5g3ysfjC+iHfTd/UVuT5EtTniql8rA2tjmP5/9wvyqcrcw5LLVKIB/qusC\nQn+LsCz2A2x17lvD4LWQ4MiNjecyou2+qgYWJBk+B8akPj0NY+2gPjlkvUsqrAQ2ZEXxBAkwh0VL\nF/eAFc4dBe2CZbl8TYsPpe7KzI+5JZriggvwyDmjx5HaHUjboyypkmjg9naR6Qqc7LsJ5ZzZbFc1\nll72uFZuSNVKIJm5lBBR7xAICAWv2XOXOofDZlxOuffkXLR4bzRQQBtQETDojQDCfB94RjqLLAiB\naCMkLX1EXctsM0yLaU5TUM0flYh6mVdAACd6pyvaYHZpYwTn6Vuqzm3DS6ndKOxtbGecxECr6oEh\nvA9Wcmp9hTT4cYGPjSPGoKvoTPLJDrpu549JAhZRJj9iJqfb2HnT4NYKUjdgPgXJjW0T+ejiUJSy\n/5pc2njO1XKu2pCaBq8DsiRJDpRvsKvs6j1rabWaDVfDLznSyOofiaGg9fDHV3vRNJRjE37gwfAl\nZungs4c5YQ5oAfpNmbg8MA4fYw1Usq97X2MoMpVph8s3URe/kBG74uJOX16IVh12Vml6xv482Na5\nSuMOSLfeFREQzlXCPPosYqtTYG9iNrLsObPQ8Id90DlVTrnQTY6EskbTr1pCyQ1cfEFhiibBbM6k\noMrFqMzOJLssJVd3plr6dDxfCim+pbEQoyoTV+J9+pBLRZUGansccFBfkoaCleyN3gA8pM+Pv577\nY6ONip6u76HKp7yk/83EUOTbJOq+kDyZiKRgp0uKSNRgCbXZbMu3gEOAA7/fvbGCYCTTdAb1HZvZ\nRJgndHGaXbBMH6eZh6j9kRK1jMZ1CeGAb+3wURju/DdIZDl2K+6TOYdGP+x5kFbKrbsWdcXxIipv\n1DLRA9CgYXcQbZ5/f0VBoIL11/5UbGwBn42zCdfhKj7wo6FWDDNpPebKOEnzltTrcCaugumB11Sv\nJhWQveN40JRpfmyt7K6r0XIPtCqvAe8q67crNKXIzf5sQ0oeZDZdFgGyPOdEZMRTCThPX4iLmPz7\nwv7JPuqQ5KOIZJi33O+yz/oXOwbFq86NM4FHtV7xfnMLkIyI8Bj8HVAagBBDihQSUBKW2SoaF8RN\nEmOO3lcENTe+/mpjxHXPNhMyQyKWnS0VlG9RgrZQfFNdsIG8e2mGMRYpuFJFaqxLdTInx69P0pkA\n4oEQMxRpaHPuILbQnoXQRhkh/LIAjorvgn7EHddY4QeZ5TFU4S5OhGn5Bp0eHD73yEjVbT9Db/EV\nGHJcNBpwAlh23BXa/8GVhaeaL/G/L7UfYPvL1Mi5uf/661MPFWb5WQDkRugYwOJPkTp0x/PyKChx\n2nNUOitBW7hnxqYeAv+eF+ybOhwqX3P05FNUDeN+EIqUxAa4ezVQ71lggo1f0BA4DrTfqcPn+OdN\nENPa5TquT5UUVR1riTCW+2kGiPRsnmY3Gb8egLSN8nLDPzk2ELOrzWWIKZPFHeKMzE6wpqlFqWJY\nefc5jy+ewIes4NmoOwJmnV+XB74S4izZMboWZn9YKm5OVxwsPdKd1PHbcs+EJ7k5CjnmxAvo6ZY2\nG5/vA1fKfPpXDpGAY0dNpmDaS9JL6GcJ6/L50VBAmhgo8uMCVvPTPFPuj8OYsa48NsXmxsbffbUT\nkxvioyg/L1tFJVc1k5OjqaoHeXCQZJSAJvwMpa6IyaajUS5rWKWpY6Od3eAsn72V/ckmzOztlVFv\nYT8cR4QWRq1hTTTS+NvBTB6CmJya3wEKVHEcn3ARTloatDp9CY+Jj1DynzdFAaApP0Tfn2zg+F8D\nVh/vwTXVryToIh1FooQHwhFRsy860lv1UY5FHgWYXc4r1XwWDAi1CqmF6G9prIfiwq8KJhfxiB6g\nwNiCyg0Nbn4wsldj6IrTOwJV36Q1jCMwSmeyKWeUzINQe40fe4P66Z41grZmoiWMTWMfq1fA2Hkl\nKt17J3q/NwRcVCuel0FegD2YlzYXNmACQ0x4xNGm+7mz8zkKY9HGERpSZpIYhE9ORdhUzz/ayaUS\ni8cxCDKK/n8+OddrYtQIyOtFeAmMQrk/xBVxkm9WDgBHjfYExL15drCb7/o7m8oDv12Ee8LyXbZz\nyZ/BRsPhdq3OgeRRdKz8KRS9TSr5/zoRXnAN0PgSmb3w6UAGr6SNFyChibK86CRF+yM2cAt0gO1G\n+/tYwEVj6fNe0EtqaHd09D/Ie0yLHIJMAMQQPbrAFntJqrxG1x6rFPiNWA2gg2B65rq1QSKPMClz\nwmhZZoCCbtOE7wj6x0MSgYZz9ZisRZjySzrWRHMwy8P+S/v4+rp4MR3ZqsmJ8fVzKDHvFoyboXsT\nEdF9eKt1qJufZDIfLpBYgjcXiZWcTp/aBgi1NCn+W361JmmWOy4cjlyI0Ci9TORhbcL86eOjc1DF\nCdgqjjj01eCxybRgNRDssKnBU2sQnmrik/HJJsfILSKM5R3NoCvjbBARqrtiuC3k8vl5mcuaG5sA\n6yRj7lg+qzO5X4PTXdqdUpwN8Ow6xuEfpT0d5MNwremnKSczNm7rDn9YpZ9/VCvpLzCklMRhNNzP\nHTEnPha5WWZWkMBADbtYajUYeELnEW4moEhk9ogGrwqR+BPSxlpOL3HCE0U8K1ttuRNo2mIIkJne\nFEv5n12XAnVJyHUX0nzj+hl4sD7WijILEOfKxYYv15+iQAr2nOq5uJ8aSiI0idUobE3ez4/si36r\n4QeI6jjcFwpvABdfvU0IRi1lRegNYGxPvelmlB4A3ExZgoCRM+Ws5R5dZJftsx30inTMjxC+ztP1\nmPQoHG1sJ/dr7KP+Go50V4UHV0xVVIhnMBsQlT9LpTNQmXkO6cVZ6N3YikFEOYvNyJMslO0V+kMK\nQIjD/zEsFcxEOIRbxmF1vXrzJlL1LQgC6M6VkyKc4A5ezz1NvnM2BvMmVDeodEUuLqLmAmRO2Qsj\nFRrPUA5In22kPzSXgAIYIq6c8dp1qS3VEE897DOOIge/whgAeYjS8t0SPhaXKiAnNeIjGx1JlG7D\ntMlRPCGdTcmKM0YdJqpyGJRS5bkrouC2RIww0Xh/F47q5PGYBW64gW4Kl4rihnSPfDX1A5xSMiyv\nOPmjKoviduU/mFjTsTffxjqWkNdcExCT9SiiEWJqTNJtcXE0Rc44wBXZvu29ezDt69FEV3jmYMTq\nYio2XuA33O3HnTL/iw3G7K5zpDPvKghztazI/nc6cxhuuEDRVaAgV0Kv2Lg7P84rB62iAYIcRjWP\nBiVpCV8tndUzecp99vEC8UfAfLvGSc6aOQntrKNHTBAZfzGU9OZBHKMz6kXFWOpkerw686iBsq+R\nmuzKeBClWOlYfhkX4ycyJno4Uv7tsmgA+tDztbn1cwEyBx9NOvvY1CdKpe/JlJJS8noc+2/112Us\nJwVUOZ4aTcm+Uuvpqg/una9X0B9/4a/hn16sitLbY+/oAqkFhuRyXIIRDM0a119sP+INIQiWr5AV\n1fmp2M4uEWBtmIVuytS6Ze2HBpP/+aUDfzbiB5DRxLjtlBP4jkpJ2NwtfywWc5elMUqF6j32Ew1g\n+7UMSZsD5GgEb+VSi4fRgA2Z8K4VezrnEj1ohXEOjOl/41md83DwdKGCTTik/JTyrKCJJXJU/RcK\naPt3v3Q1Wvd+gOGc+P0lpJE/r/xbhFyxzCmZftHlyoxlIzia4+tmlxQKVC6biFh7i8ON5MJByvsh\nezz0Hsb9s2OjYxyauGXULhTROCPgqMENZvc97b25vPHFMEk4pwZcbClyok8jjOuFHbAWv1utfNBj\nBT1FKZSqTLhPLf+eIm7Xx/aTWPwYkiYEHMrXm6+oj+Y5t90y3y2NTzOOgXsQnn13W+Y73mJ6KEZ3\njifMMn2eA4kt29zhRCiGGdE3Hk6LbeWbRAcXIlNqx1rAEnwLYpA+tQlbI6RBUh6w9aVowde0h+hD\ngTS/Lb4IvIs7RByngUERSLCvPQUltcTsmEmL93C7bhSIb0jN0TTbnuggS1wn51Kv1WJTREmcCgJa\nRNw4JjqyHWG+KwIk2AdObXu0RxmnDIGfQboZOILje7jatS2PzE9ba47g/lKG1E+Dve5bYEMzKB9V\nGfXBZ00GOoDFHNdwaRNDELvJFupUJE31qGP3SzmOvPb7XNb8yNixzv0wX7iCfK0W5NuhOKnPk6Dw\nMOYqtzT+CKefjK+ooONntXwgssy0uKgC92NLhYpYjcfyVWy2kP+/kHcrtjOweLuVV08GJGPPovVi\nwTPu3nSLy+CpXOZFXo2b35LGGmw40CYsDir9OIcYPc+4AE1O7HStI3kbg7fo/osgeYL7nvZ6PR71\nRpHUbUP4qLP4POBe5sY/q1FK0cOfPWfIweZ7mcNAfCh/ES8ixGzUMXA7CT5jwcegRBKuCSn55Y5w\nYuYOfDA+5430OROz2lbjMTvO7rG4nYwmL1mV/7d2zBDGA4HOhaWtODK6e0h6H/rh7gnGY6MWH4ib\nnABVx4pngeU49ds1mFGgzVxcKzruXTNHlPQHLx8qG3j8x4qbhNSnzvKdcnJNYM97DqoTJlFF3DK7\n7AUakABcuI5l729JpLA40v8TzNXYxDjFp4GDG9a/hX+9Jnm2fe4oQkibZfha1xtL/aoNGto0OKPo\nRB7B0kVX+JR5FZH5BRdO/obhHFkeeGcs+MbLi6KsAwWZyegKJcobgDUsuxyb25wFmQRF8PIyI26Z\nkxm0AKCp3qptk38HT7H2gePwJ3dVcp+s25oWbAkGjFDamh1oE9LclOClgjnMB+IBCYKdbSKS5BAs\nHlw/e/+9cZKpQyjMDE5xryoy3iWmG/2E8jn41BT5XEUlt8Fv7o0hFtx8Ue8AgpWUl63E8zqT2g5L\nSb1C1jlMS39atJNQJf8UF+rUhpntyzfPCpSOihook7JjweYrZSX0iQtAgEvk73dLdCD1RalOiqQa\nw1XOZ/ixpzMotYZW8jZXfUNYHDVnYwpzAhoHO6yNCc6qys2jHSR8tPRXoXKjW2q71ydUKKhIfpBD\n8O0l4muOhCXGXvQent4GYDey5tD8SLuuBzYAx1ZImztkhcWvV76u6ghMSxhEiQAEQm4oQIGR6jEh\nzhqh+sVB5+onAh6+QFpcBd8A0PhwuSnpHAgJ8vrf5rglBG2XFe77Pw5mfVRXHzlw5WniJ841P5qX\nAY1H91haBTknkYb7fZJ/ghu4WvyrSBHEZRVhcO0HZDdM/a56oc9v1nZRE0TJ9RjV4ty8wm+/KHYZ\nFR7ZHiRsUSmaMd23SwOwIoK+ZF/B8NfQeQCpYfqubsuQAfBQvcRFa5e5kIrMqS1F5gHY60Z4cZw0\nd93bl9JowvZ3JThsOVohwqiiUDbSxlvDpGxwHLMHKRL9rwP5cwIjNycWOnEWMqxQ6TIFWCJvxzgk\nQ+gNaeHYJScT/PNbUZ2LCoQJCSqZFUdy0RyKFaiDJcKw20UGfUd9ou/2amFI5A8AICqDBAZsjkg8\nWf4LfjzxJ6CmfJwrVLGt/eqhtRe98s635zYelp3UwZW/C8TvaLVWqw7wNbfMONeSTLznfu9Hq1qj\nteijHhuEUgdrAnB7fv7Ojnj8GCWjfZsi/CEYginIP+SyrgWxBnYcGd3H93HsAAoMXdoF3txkT49K\nRYR4xtAt1vTSQNQ41qH8KrDoEdJte+CfGooLdHAA4XSxvj/1PJTin4kfbUdzb0oiQCSiclGNaWsi\npFtOV6RPxkd1HNJxTiNRqmHCTmtA7GlbwaoYOXQux9Al2DFbyZBbXU1sGp+f7fvq1Rp5iWV6V43v\nPzL+JLBTxti6A2z3bsebQJIWUW7+ILzQTTuAmJ8a6YcpaymbHAXQ8zijm3UpBWbDUbPnLic+UrbU\nvZEhcuXiFScChAp2TXjnjJfYabQUvPMhF9cxGjkUazUwCZ4p5Gu0v0UKI7ny3TafZp1HkuAL4BjO\nvqwE8SaoAPg8+R1bPKEF4g0hSp/NWjIAW7Yc669kRc+vNiBRQSdtkMnM1m+2iduJ2OW6pr+BA9EQ\ndvfGH1MNqdXrPfKxYDQpw2r1Y5BPXqi5S0QZ+pIL7ls4xVBAj+tfplBhxc5JSa5ylWArJrnn5BQa\ntWjOohexfBpEQWk0Zhd2tZsVFhxSoX3K3VJWOuT6qjEdp/kPBIw4VeUCSjSneuf/tki/H7kbM00x\nTVezfnEoxkqbt8l4cpKfFv90PjeVI1kJit8c0QxrP3jM4rZQHHxytkiV7xjN6ibdEKvjAzXWcY/D\nW9hc/LgPe2B8MZ3P28X86Zm7lkkFN8Gai9s2MgfnY26UohkhDMtl/mhPDBTVjyHzTjfYAeaw6Ds7\nlHPsRy1J5gs+udzksnEJJu619WQQ6LBMjMtFGyA2qcMOqQI2E5FsyDIGLcukKPEa3YymwlJj1I8E\n0qXVjIYHi9R+uKpZB//uKVGglTP+NkvSPCWfyfrwzAlXj55U4WmeO/m5J9Rh7CSCQzOKqTPr9+Gf\n8r3dHjfG2CYF0yZ1HBwHQjq8wUMiDbd13DK+8qXT5HU95pgFpo84N1J09kFdwpaX4nlUk+wPPa2Y\nuvqzHMbCLKyGLz8RYHd1ch5WeZURbxI0FvjhogT2bzz01viGlO7dN8N93YdtXBe8vLCvvtrw6imX\nSnUV0V6ecdrTqBWYjlD3leh2YeL00OYFFb0GAMfj578PWAG7DCOc1oW04kndaSaP5+x0ww8YEPs8\nRhbR6rp5xIu/96/AzULyUlSXoF027nvHHPzmwa3DmLP7fWZJDC5LfyJefDIUzyE8tl2oUWFSwvUw\nl05G/sNF2iX6AnozC4DmH2Y/uUdKsCKj5d6RN6nhr8EO1LN40CXdY7jfnKAP2J3bdVFJHSxtG0Dl\n7kxSQuLn4m5OtvMayQ8ylEpz3F3zcBsetRvDuAtuXxTstNkcmFjHGjk+2leYANbnZrkaaFcENNlY\nq1cDQCY6eUoBULfQ8fNudoXclMerRrh1muHTw5T1PZH4eOxD+qY9Q2G/1tS4QC+1OBvsxwH009La\nnsqjPkTZd40YeSVVAww1UKVV785BhyObefXWchpzZ5eUkazFO6Cl+n+MARNov1DGYA+ngbzfYkrm\ngJ8sOSq5VxTvay0Wqkzh5n2XjYSPNNTujh2AunRqEIQLwq0IArwM+D2jl5h0q/GSxV+d6RJDAJLV\nH3eBTC9ugm0F949PzuIpJ84XLAKxoCaGsTUijNOzKDDrBEzlopl1LG/ZaBfMesYd0Ikto5q0ep9p\n0M9TamfDdTVfS7x0Ok2bjxWmvjo8JrxYZmYGSHwh4HBEVvyEIBssLpWCnYhM7cSliHiRt0BbHY8t\n07tjFUzJJac4ht3qoS+tc4URG7d9FZ38IH40FMO210sUL8hU+0YkIgSA1xGiE26Kf3563idsSa8Y\neuJRfbhRle02O7fZ5tflIGSfgYuZic8JguRagmiIlDCc01PHvm+iox/Y+iGq1gQ3h6WGtr4b7sXj\nw/LPDlJcC/74fzBS9WOvPQm7w6mo+6MuZfnef6xWSoUx6V4bUs/4uXM/w5muFZn+pWZ9Fxf+VeFL\n84fiUqteftld87YHip5RHM3xEp25sWxTbR5tGXlr37emmbgXyq6H5FAwrW5G0jNnlV2kFys9Tadk\nsFFb7THlsgdx/sY7TGmSf+bvN57OJYhW6BBCfwH5bPNbIkrl381HvmpTGuLfKJ5wvGE4Zh4yVX5M\nAAaabnc+D3ZVpon9JG+eeZQmtAcxHZolY3YIBkf+mz/IAPr/W2pCS1x6dLf3odYh7p8IkFgWOZOl\nzyDORJ5gPMur/ELiu0ALVSk/wfpzeRO+XLmNk7m7hDxUH9VdZFvu9UJJMXbE1ak/dDh0wfSgRBnL\n1TJGTypQkTG+zfeJ2ijQzsXfcgQelS9dcgt4rO91JcLPe3ov5HjhRJpCS6T7z7kL+6SMFquCU5+O\n2JyZP6yUhrPBG+D/yvoFtLpbYMLdfAXwAnP4dss9C8uEpIm6WrpSNFb+j8MobxDQjZDnPaC97d9Q\nuSdY1f8VYPPLSuraZO5DNBvzvkRT8dlHbKJsDPeBuULff/eA5wAPeTUt6DLxkURHBPPJJB5BkdXP\n1JbftMQ8pYLS2N7UPxAr/BOo6dgKwlU4mTww+Up3kjXaO6UBfwEFx1U5Bm7OLxnbyV+YAm0w+WkN\nf2bEkMnHCh65+Hrud0h8lSFEd0Iu7ZzbbCP0CTwaaw8/2+VUTVXpBs1ahMQIGhF7EgT4mZl8r0vW\na0pESFSPsMoWh4yzmZRHPjZcB8ZGDh6CTeBAZs6b9gYxn7+9IsvALQ5JdJKDfJMBPD7VfeZhtKQ5\nnCeVD0YZ67H1PkEqTJ4uloOVHeXwYOc6jzajOCHsPqVp3PJYJT8YYmdeuHHK/lxzZP0kObkgxmNc\nJ9am7xmMvIS2J+Vw2Dwt1TDIHcjDMpbwqtKbMKsTgOD/1KNez+Db9P1Tfqzxr3IEgWOiSVvGFZTK\nHwggr975pyJ1XN7R55zb5l/8ZNYpEO+764YPcwYxu4Ku0Bc01/MqEqflH2cm+HFIjhw5qyo6xOp+\nkTlKjp2kLaExUhfgsYkAyl0RnaYh99OCfItXqCCgvUktFKvQEK68NvJyjIhm9V5l9nMFhssfwpsi\nLhTZ1FanOCjU8Slxc3tpsfALx6SrqmNUYxnOXICay9edcaBJ7sAhAR+lwaghj9sRuWbuOZGjZL5G\nxLio4oeGZmH51/Oq46VF41gl6AjvjS8Q5q6U3FbGPjs+0AN7IZJGyuE3hxfMxitOZ3S7O64TIQnh\n6vCQXZyp/4S4uYZG4bh84E8zNYfdSd0zICD0p6fBT74tr44Y5NhYi0W7hkOpzOr3z/RX72f4Dwnj\nduVTOYn/oQT2nqdxyDhp83cADrxUJezNa3Hyayr+vvov6lg6HaMkS+JbGHgN/gJLSlW6AR+uc++Z\nDy7Kz4jqKVhYgQ5QgAi8UYLun5fKja2r5zHPhU8bYNNxVkAGlQSrJQMdAzxK/GSj8tDfQg6kF322\nU5Lbpp6FQoHA+UMyrAzm22/ECJmhgIsgyJ1CZyQrbq4ty87DOlTh2WxL+qZt44JucqLFaQecUzJr\ngFhbQ/g2x8cb1wanawRdYb5LHudjLrKhOk0GCy9NsxSXVZwMN2761AGyuoTKtQGJzd9yuO7LVu4B\nqR39x2DmLaV8kAGMGlgFjEPlDAZcn+kDsIGIfvY79GF+82yKJZGKwl/wBMBxygCGBL29UiK4UY0O\na44zd8R9u70Vv+ZpBLOy3388mx4Dd+vxSAY/guZWrsXofyjQRXjAPAM/CDOk+nnI9KWEMP573DRM\n/VPWmeHjG8iLTQcYll6G9/ISZNN8zU6vsFZMUIR8zb9u170bWmvPlcokkwGMyv62jWqtGjodn6KR\nS26TNT5EpTIyU3kNu2zCCqw3Vz+Xcg7rVcTOPg/QvqJA8rP+Bnbyzm2EdqKjt2XllbCYiUi+hT7O\nqwqt+V2q8zB+mDJS9GF5/M6KiD3VGFFR1DO1G3gCMFMT5lv0vdhdwS+yV90Q2wjR2blQJ6/41t1u\nEPEVwk7LGMCyIcNaDpVPaoRMAErd+Xetg+JVTp6eq4TmOgCWeajpaJmdIQP8zxARgJgyIfUjumlk\n3rXVnBcvUlnBzli/dhee3LfWDVCbWCS/VdqOoniAmSWxrxtMe7EalnKIl3JE21woLFSEM+qMA5ub\nvbJAq37iFvjoCxBCWtXVE41zquRFYVLXoLspPkewBtTARi4LmaV5Da3mKzfMw3CMBcp9lOkC0Fgp\nuTPa1c53VqYv9iBHC5XkMRm0h7pw6NKnQAeDHyNwj6H5g0A0K0wio5azazGh1JHeQBwBKK5I97rq\nLa2ZfiPzXIYF28MkmIhVHOKUEh2Jrjbzqb/N7IJePwqT/mOBWgzOgCvw8C6LZZ/NmClYgijvByR4\nsyBqGoY4kOMacT44LTW+EEPzdyXzbCKR3vx8Vl75e/GkeWHtP3mc2HWk0l8PsxRlSSGvJVBHZhgt\nXv+O6A7ND2/gvSffWA3ADEWGFQ289XNc2+6f9CzQUegOZ25U4UJmP83cYbvPaTdHDB6TbAtAX578\nQuGKaJ4wcRFaBE8UrAs0qUxMvNmljc8xICae7HFIayKx5fkTBGeyxAtIEBgLnMCcwCHHBLAIckl5\n5Utx8Q8hoaOVMlli+u+mTjGB+theT10Yk4BNrmjXs/E4Kat/P06sWd8bn+FUkS8j726qjiJbzdd1\nCY5lbn5JtC6owKTmUU+EwuCgCpBWs9dV+hNsqRfHJs+TOq4/xOkud+qVMG2738F3Wzf5aeQj0ZA1\nqujUxfMAUHklVnDocRMHdDuJ4u27SfwcXt5okS+MHVOqcS2gtQDyUVRb+uVdeZttqOzmO+ul0VYb\nvgalsbQDdyAoB7m+8RSccMMOHbHx0Te1pG/GX+3ysRDgMTMFqPog+4I07kS9Le+FS4BVjWG7dw8Z\nf3shj1CDuiSMwVQ4+cvyJ3E8SqD99cjm708fK4jr+p05SFL5KyOBxFUAQXAJOhngHUZ/4zu/gFMY\nMkBIgJ9KUH1U+Mdg3f1C2V/vhEereU/mmviw7urvjOb4dlX+Nl2fz4jhiPsWmTOVGRXin6dTy74a\n7gVjVq1ym68zqoAvL0YYngjfWaLpVUwsJCDMDj2Sn4Vk/UGchJ8PPObz3b9VmvJeNIurV/mubWfV\ncAFOmMchdjcG2vELDcfHarDwqGL9UCYNyTLWKmIAutogy+EFnkWvy5Xtmzho4Po4vZ78//zVLSYD\nBhiLtmxqhDaaHkmo45x1fbbOzernllo6KMYv93v+HM3kw7/0sizqdhtOjWNW7H14n+EbI1hP8xpf\nujaXp5g9gtrKC0/Hd0K1vnRtHS95pNg9y0xACzUc4aR1mKxz1YzAz+cf8S3aegA/HdBHKGylraBw\nyxDQJ3tm2X7Ro8OJ8KR+uLf3o1f1Lzz4ziNX7NaJTkFW71sJIHg0xqNW0uyyz0zYDVq521b6yip5\n0n7DJRSFBslbMcm6LdDJqzD7Hnvj+qsIKV0Ro9SoFR8mHQCpPKH08U2LLCQ9EWyXGQy/kiDFTwAp\nPlQFGNP/VAvLPX570qYOX1Fh1+S57hFz7tKlyl0C5b5YSZ1HUdcopA4NKEBza5HkdAocaiJMziE4\niBwJbTbrGjHORuLSlkMnGTPWMxOQnamtZz/GuFKHUH1E7Ydi/4BipikUxRjMEVH43m0C9ju5lkne\nHGyMg6SJy/hNG6SBgx8Ef0J79rF5QTJMTxNt67eYjQu9aPtYgKa9/9zfWzcLqIZgjLdaw+ijb2sM\nPi4wqDH6MGdCSO78C78MY5QQ9lKqpbrVubz6Z8otFZXPkxYMKKWKMEcnfCpLUHXXFXrMJIuemgrP\nG4xH7Ca0E1P+Vg3+EYqpPveuJk5avmEQ2ak/RHavM1bdj1KVDiLo9yENLDceSsQeTNu/AyDMEsEc\nL2XoyCU+KQ1nF8vmw/8jKWuI4Nvd+NcgvzQo9vZ20ZR3bZa3bYCgp+B/6VGjiS/94dhOyNr8Ek4/\nCw/D/qXEL43gLnMC8MyoAC9Lj77irXrn8FfUbPlZuFoDGbTUkhBK5ouOwtRZww5JeUrvOGspZL7u\nVmnTsnkUA7PzxxCYJ18TjUPVgmiQIUwCE7YJeLPg54m2A+JrScFhcPHa7ci0KPkWGlJsVUOBFhqv\nof7FNbGulYi6yrYebG+AYd60f19+YBMNrNMJupxgjESo5PPVEtvz7RrXKHdvAKwb1A0vGjvKclg+\nMsN3M1zadU+cFdIzzcNfjztRypG9mBOfaSakN1U6CKBlWYPHRNid4kGvuaKOhTKuEheLsEjlLIp0\nOEZIxWumkhST1ps4MBxlB+uga1wsyOe2sVyoyaDuE3fllOO2MQZe2m7dDpJfpNesNUPmbkF/uovw\npo+/0i3pbGxT8IbDRXeSAw+ryL6ZQTT0ZvkrrY6CdpU+fgiex89462gticVMJ8u4/EkpYEZrflZn\ncrFMmq7WBbfCmIOoyQyech3DcdTGFiU+MM+a2/18gUBEm/686EQ7Ccc3qG2Qa0WZaB+De6uM8dM1\n5U1rGG4lfhwKuBzFtPnxS2Q8avhHOyiHmYyQPPuXQsHsvbPDIwcgPj9YwuDhlmoGYUjWWt/fQmE9\n+G5RScKm+tT4kk6dvmvt3lJ+j+ORLr1BMhUANimuOHiS0ypPNOLsWZGkRi9YPZO+LL4/9Bybz2u2\nWhEMjGT8n/SwklEs01vkQ7L77CPt1Nobp1y+j3yFlbLaVzkGISUciMPWiLcWyT/nWC5IBvb/YQAg\nLYxxja0nwWa3lY8z9hxaHpcL1SAPjni2VzTFR2mIYJL3rQz+sC/k2aWOK9WU9FuOLZ4qpBOYeTdz\ney+tVIUyE2IAgUJsmOIHGArkznlAXRXXbIqkc8sor4igyMtYNAn1J9Bil5HSNaRg7WWKu/YTaARC\nQ6k4QVZadaaj44d2JGHfLe/aY+5PHHefEWKdIwm1QiYwTenAxI5mX18fQpy9sfs4pWlrWwWkxDAy\nZUWs7MHweTSW8fsRelGUV3QVR9MIn5kVyVFWeoA9buBkbfwlqfjveCnsWpTcrKJNIbztDl8quydC\n/CJ9YJ2BOr87Ctx7T8Bp/gdKDr3GgjMUY6RgvaXArPDG9cQihr+5aZkd5F278IXg3iaLwvs8/fNA\nSS95MMtuE0Igv3BJNqfYAOIg4XQ55v8PfUGjARYJYGiZnsY6MdOJfJZ9Mg/CmfdRpKgGkdQN+SVU\n6G1O1SQbieH7b8Bp4IrZ9juOnNrM3qK6TbBe455Br9a/xWq1aWQ7w8fe80Dkoe1GI4lCvEAXV2Dw\nYoLn7BBv2Lyk20CkWER4HvZZgMDHKS58+2S5oYY5HrNCGHcTu+Oyztt2rxdBDScfyCJ1PIE3kgo0\nl1VgEzN7v0XLTuElcv2l3+2u6HoTlCG4gzzdmlqlDpmc2Tu8Az5s0vnzX6tpORxhruVRPK0hPrhv\nc8OaQNDa9Ve6yPF6jaFnIglDsjdMr5RFkdXvjoHOjHVbSs0XokBvU8AYK5qwWjEZO4xGqwXudmUU\n2PxeMtSXRRv0M1idYYdXsbtYBLcMX1Ep8FR5da4SxV0UV+Gq0rnVK+YYg1aC4rdlmv3IZ55V1V42\n82WFibsj3k9qIE+8SdCCbFNEVj6537DRAYRytTSPJfJbQYESi/FY2+TCyH7dJidWffUX+w3t/uUF\nvgw9m0SR72RaA/aYpn8V/2/hI7S95iIZgyNQc6WZrcLK3lTgX5V9ouiB/tWMm5/mWoZBCB9FKsx9\ntwjRYl9C724vivtd7c8gdT0aFYeRQAkzVkzYg+sgwjqVgE8P7g3SdrY02ZlSvEwZm6w9BYMOkDkx\nUpMGGj+z+Cuot+VHHY2jgmgAry5EDfbcWZA/OuQblggYDKzM6IkQyqrutfyykkMGA3p5lbmWWzd0\nWsPTLRrU1m+X/PVLbPWuGZliPRmJR6qnxwZsJ8sDIJUya3nFMtF0jE0JPAVRP8bZcIHP+V8KaSsd\nqxjg/ntX7aa0uQ+Pz5yxBHFIPt8OB9s5afvRIjfNYOgLmZs70hlqjJL4XjLHXHXgN6K55ebgkp12\njyGZ4n8UuNfWoIT/CHjBw1BPSn8ejjeUgUdvkR23A+Zi+qRDNuIhUS5HHL8790fRIZ9UVstX8NXb\nmmrZKskUltKiAAymXrdn/4VXD+3g10AV4obRVm8XG3b/8gM8c0ZL5Jhb0jauOhW1DEyx6BXXEMn+\nXJP34r+yMWvDPggM7uxIn6D9Ytf7gF0e5ysjueyjoZMgv/JgE82M/VB1gLnrzLifOCJg8VOp+B8H\nDhmfczHUEZ/8A37nlq9NnTdv2la3AhzW7NTIqgDp22K/zjm84oSbchOsPJjWmu+3XdK3Si232SJS\n0nkiGvLhgvhWMkZ73ENwT0XYIF7VzTPM1B0L9BmsKjCV3kD+UolbFIVa3BhtYj2AsarzBaXgk2Ma\nLN/qJIzPPfcE6Q3pxLF9rumzV9QEHwLZOEkh19wdZgTiItST3vccEGDKkJF9SJU3eB4OPeDdKKc0\nUbegbJlxwCVovFv3owxCR65AuIHYDHKkd2jiiZ9OaaGbqcBxwbakPMWgf3o4TwsDK6O/2yRxxDze\nfGnMmlMB8MpoBEnkxBGTtIPN2qreznffCnMk/N8tk625BvK9B/ffmudgRBdyqkmXb47TrTZ8CWrV\na6PzfvaI6qOtBbSm/7lHh52y0T2CIt8RG5zqoTx+nPiEtH/iDpQOVvZwDXDpoCQPfmDHR4+qBvQk\nZmoeckLhKNBvdlSoqOl7hzhLMSkTScMUtNoe5oAfoL1xRU1yjmSjFwBumkE/IwCFX6O2ARS84rEX\nxBGO7/+pQ/ha1I5tjjHWsJffNinTDHsNniYawJY6IXyMiHwdHJXc2sTP3EwIa3hI9yMZvUHSsmN2\nawTvf0mUgJri+FDaKGx4RBqH75j+djEn4mc9yUSH2QwX7smWbOuhhKZbgPNW++BspWe47lEPnFLr\nuDaBXXr6CDyRRANxJu3PzbHWecnXrQ6KKnTtvgcgscDbWWtTzz0WIZ4NiTArbDA8apUKxD/Oa+Pt\nG9jITSywOVw1Qk4baIZs1s2XoT4IMsH94BZHnFT0vlAaJYPLE2rve6eyYNRa+wOM1HAqWdLlOVzo\nWDogzgbeGtOWwPpT1dkYGAxRkduyyapNLgHEp4WHhplSonINTrjoeOvJsOOhRVfeW7xiiXlPB1Ny\nJo/Ga/pszHlphiAO+BdjAuiX/MVrivpJT3nciZWnAmGw8E516rrCET1Vn9aUG+Np6alYjwfzLUEe\nHDCW9F4PQH/TqqOWT9ZGqKQ6fVltfEofjOCSMSKQYyPCm1U1Iuz5HUZacvSbxdX8reghTnYYv+NV\nCSsk+1jjz6Z8r74K50u0GfCIzS0bYza/IxLfnk/swHglXucA+80V6fsSuZeo8GFS/lwS4OXcn0xw\nlaRW/ukGo3+kn4130qMzJCCjF5mUpUitVPoDR6+2iTfLRN+GV8X7sIJRvYU8NlnBbd0BoYTTRxtn\nrs5r714PbglbguEbMviYJmT8JwSArSJDhNivyOsPHeHhkh3w7JAQt2g9sEY3/IWLHzIN9ORA75Zw\nTYSzbak/OXWVkv3A96ikQdCXF/2EyjjxaaLFjV3ckaHp/f2yFb/Hk+YAEGxV8Fcodb1yaZHa4mHg\nr7veamj/BLA058HABjinyr+9Dpk/Eggh1o7yPYAfhIc5RiP6ARtwaNQ9e791dfp+9SH5xZUKdeRd\nO3yw5Ce7TiUmUeToTA1JJAd19KDppT2lgZf/Y7bnAPtmYwJOJcXbbM/c+j8VuyVtZ0bnvr/Wg/Jk\nznkToTAUrrdHrNped1T8MBpQUFye3eF7u1YR6hQtP5jT/JAzrO843voNWjC/CSRTlUqfciu/ZBcn\nvy92AHXI/llEELQ5HpgXrPTzXkbJ2x2Pcmc1VZc/H53CXWv9sxliiF9D+KUvXfDKJ68WB98sSVF9\nxN7OxBuuXWtcGlHV6iq5SRYFuDv9UX4e9BPlwaMVsl115to6RiFSCrWZqZ3JLgSa6EgdRGpq9NEC\nrPOi5xb2z1KLzfu6MOgXr/ttZPb3wKqSgUnXNmTZWXKcx0IsopQ+jy4A2hwEutClweXCqSPLHHLl\nEjOW8xbhvi/puWhVvkzNk4IWn6fcRAK4fvxG478OknFVWnfuCfTOzwj/n7RYpLfJUoGvI0L9Dps4\nV1JK2bA6hDETcfldBfTxgodX29Z/QpskiVZkH4HSMwrCEkYN1sCt+AyZchkNnXa1sNdlB0FAwIdU\n5/V9B9tR0XMvDH5rNKfMKWswds/fHPk4W5tlgrWyPVnn7B98pjNfJ6sE9bCJuKbHdNRqnsfNvTvG\nMTkOwFvwr0yTDlsU4PFnrXFthSlZ3cX5Nxto9MX4wDONZFVY4E1a4BeImausIKWva1ikDn3lmzmx\nLJLIgApT5J6UyUOKlqw1x7Myr2fjs/Tj49lkQ0sqSTVl6Hxt1oTPu+Is0oJDDCjLzOvjOLZoLNV7\nm+xyDC9eIrXYKyCh+JP/sVPWKS0CiANwppOO3uzqJuBrtN2rPEXwlWuWzAoMkWg60sw6o9zxXqpS\nHlp4NACqyVMK3Padl7dzzohxiHdx4x0jGzr3FPo+nPQROOtH7vGTMNvnMuJ6HeNXkdqr4zM/7TO9\nxPoKwySr5/U7fDhNUzOZstpnxYDJzWscOWwrkLHVcj2PGCm7yN9CiMKXkGHI/D5G46kjTT5oiHpa\nR2oJrLfEAoe6JzkbWjJwW7eI8wRDI/+Z78eNQ8g3c/Qg7PsCtIyS98X1mBfFMCXkN+oqr4iyljNN\nAtjfzRffxoO/2ELpKfArvI0VI019R14uUHt19IhZSkliEs9ZmkrjwEqfU/nWA6YC28jIqLI2YKKv\nbL6uOpUgRGih3dQQJ20HONR9+1JR59Li/MBYGkzavCjjZTbqSCNz+cqNM/YQerBsUYa6Pd0Z9V5i\nMhCtyd6ArM+OD8kPdjqWHu/7E0r9oSNcxiwpJR6vyj8oe3zeHB7It4Sl7XgAW1viujCrFvbftQpT\nFPLF1Fd0S8CKc6sGbrmREcEgHMnPt9Map/1z84iut+MM3XTYpmTNwKtHEWb52SwWjh8eJvmKrvrm\nKYDbZzJA8r245fV5Qh1py3VHn432mYcYBJadN/e9jbmG3FcfHE+MD9+69fa/FnPeSiRsDtnUyJt4\nOmFkSyWG6enoxJdwB1d0TQ0NMd33cODxw77IZU4Il2QdSwXDWHNtBdclaFBo5FyboFy2NwdKHVfQ\nzhT4I9o6ucgWrJpmEMdyFEfW5oRI2WALS3rIux9eA/G7oN83Cql3lzRAUmSs3b+UJvNdQhavR7L2\n1zOQQVB9Og95SKEpqIQamtRxQBf3ltCbO/CoWhkLtxScG0EcSKB256zOwt5RoVkLNW2Cng/lNK6E\n848dgj/9LzBW2JKXCQ9mq+jf2uAeY4C8sw48GBKKHHKhl+Skpw5XUR/JwRVhyIwmw3gOlxFr8fJC\nMSOdi2OTyXUU5fqH5gI9Kyp0tZlz2e+Op1NeOzBq7Mgz/gbQ8IbLEHmFvMN5aJzjVWnjQ3/z7qyF\nmZudH6msIoayr4WepS4wxjlbpjFE0gRs9jUWOuJvkXEVeQBuYUgpVtihJ2KkTMfUPg8vakr57qWT\nh3+jR56eQTitTMj3v6EKALhJ58O+TvlaZB1iBvfZ4D9xe2Bvj8i16Mc51NnwX/bFuMggrMA2U0K+\nvgdj3h9KnCoyJ8NtOfhc02f9ma4RAodwcKVUoULNkqZpRBIwnathVykc6T5+hBM6bbJxE57SCnEr\nv6g1k5WDHhX1x9wxVfVTTEGv6ClpKCVRGSB2hWhbsh38hDlYMfALSUg4z3D9xZuwYm5zseVMuO+E\nTnDEX++HwxzdK+ODBKPrN4yKOO9/4VP6ZJUJAJx1+qbyRci6FHZfS0TodSYExwutGhbpWaPBfm/C\ntKjvmpVnmvbXXoYrz2TAT5zIr1z5wN6LRhFmFnGTIvki3ws3SVE6eo/fNS2iCCL3MDp3IXDMadB0\ncAgPE+3oG2aX5bflCJ5/hbwaqdziB82ktM/sVbOtgYTJsnVnG7vrlmU3F9RX2BbSIjjS+NrkIG2P\nVzIVyb/L03tTtWjT7klF8VmaYNAJZZ/qSJ3KPrVZcjYR0OOm0xB2DdTW61p8+1VZOSA9G2c6Ru6o\ncIzsHemLIIYMfgBmydf/SNoU+pI9z6ay911Vh5dBg5bEWcf/3SuUIY3Ezckpl3nAA4ZTI6HTQnU6\ncFalPT2ZvKOxJrXex2xnLsSyXy9AB4Eq1jCVVIL01E5F0YV57tI/iOzi/LzhVgsM91t4+XRuiPOR\nANn2oMteqqrO7Z7HYprUNorj2Rt1/XGdA8B7I+ANjvLZAYqSltjeqcBfx4dT2ot+Kcv8WzERu0Gw\nGUvLrztEg4+O+ITZPWYOmRRj9jCCpnIoomh2rf7OJ6lzUlysCe1BvEF4o3iOT6knAVudGAWJfnrm\nccEa/L/ef3m7oNZZI2eIMhenzLYyxo5LnSosmj7CE7EBaOw1EyJML3zfENfDGqN7Tez4lyYZBx1y\ne3utMZyaEOoitocKcGaXUrnDi8lWAUy/0/1v6tyajmcXck20zjqenyxiNED2dtROop9SZ3xuYalS\n5eiUG4PurlyjwjMUhnHTsnqTIHFERtDTpou0xmNcQmI0OfIAuZRSpGuon+cqs/u/NZOViRsWPL+D\n3JHbtvDuBCJIALpEhUGfO+xter9N3d3+QEG/eEzr1xaEzElehcY7NMpYMOvly3JuK7Zaa0bxFJbS\ndibcjQqvBDmFTbgAePgm5ekOP1QQKQ1aAOIMUMmLH43IrWS+Xroupl1OqB/adpb+1+x4QvwVRhnR\nHtZc3r7vc9xVRsjqJSGrpLV90NC3fLbab7FNscAICGuMIsitCEZ96XFbrXaUmplasQJkiRNMhvap\nRHvkDa5lPWHwKm8Qd1UwaQVPMkuGitxP0PEjdV25Dna2+Q5kZVeK9gN33aHxubiHMUd/xtsOQ2A1\nTKbYDDXN5AHyxyAiVoMcWArcvid68PDSc0TtWfKsTSSPDhOschmiQvEOZNLUKfmE0u7lg7pDK/Ip\nerACtwJtO1DKbY5twWd8L4pNWC4xIMAOLQGZT11NVe58s3TEu2391WZsO/zxNJQlmcltjaJC60q2\nXxCxZ9SH4usyr4Wd/NwTjss3l2Cajh3/+B+ptr18f+t/KRMsABNj+LtarDllTI7olPrObDID6cZr\n0qsL9HpcLV1fp0NYUymcn8MoqU+op7JoExTqdjjWn6ZANxMHFw9FzHfKkM/ZCgpPBYK/hjpv+Qit\nftPO+kI6Y9RkcypZRIsOFC/dxS7TYn8dRdM0bWwxFtVrMa4D/kzJK+3XVKWdiKfxwoyiUL2KQmbs\nO8HOqvsEKAS1UNdsDVQ6cIsMJoMfZY4HJoXdFr6t0qGv7S3dq3X9+5cqM8gl6BH9u6PTsAmYQvbh\ndbUZHioVuX129giGyEidSyQWnkVTnjpoaNdV/aBPt8Y6e1Qv3naDXcsBvAI+ERpKs3o9Q6f3OAzA\nCnOmDP9gqhdqFquCq1TgtEInhTMHyrBJn9os4mTNN+SwwC1D+ezPzdwmf/efYf29eW139aMWUlWk\nb1ZaylWXQEAEH1bbjkyPDnnjBW191QI5zi/Rmc/PZbVVpFg1mLYURlH9SMzoZfHg+8Q1EhvLOjOH\nztF4iKZZ+vSFoLxMLp0c45Qych6wpRJLGbUHBaTMSCcUDldI04/axnXVARZZBLBLCigeKH7gzFcd\nVD1lGFEPv3mlxHR/O+3umooaX6+yNS02R6EYct5oW2scLwqr5+TRP9kdqF73RG5rOcnA8xf23auz\nAAy4KXBinL4nt+ndaxmY7qcDPE8DgrP4r8f9jm4H+MSdM0OqCvxvBnWUniXC6WAOBSfoHujEhfzL\nHK5OVrkr8jBSQRy+QIk66RFUsWtunEPSjvzQWiA8h2Y3hk6fq8XV/r0BafleEpfo/31BKoiafi9i\n1SAPWKTsj1zMIAMJsvYIA4WitA3op4XGTcxMvws/9x0TflJL6+CPpTsXwBxbyejviIXzOTR0iKAi\nZvEfW3pOZ6CSrpPRT8ynTKFRCGoKZcnusbaJGhSLUN0R95jPbkC1fPVz37yh/oPmPn+vniQbyxmn\ncqpLYHpcYicAk5E0s/hllW5OUeB6qRn5uvuUX4P/scJ7jF11sS0FQ+Iwnat+a4Al/05kELcCdXVb\nMYJqNN0yQVUSK+SjNSvOMD8QL6pVY0x69QvsY1HoMgsX1lIu0A+eujoDcXVp+A0cAx4NqHEiln2o\nUfsZQt+5+PZT7LWQOop+c7a19KwZh+hWSTqg2UlMhzNpzn8o8EbmM3i7EnqKmY/36BUOsQfioW6j\nxPbIASvRGqcIynA+bhNJkSv2tkl59GK6Pjib/FjifginAGMRvfj5gu08hGEc9bVoqUpwf5ZrJmkH\n9CWFlDyJ2ULDIIDKVAVDXXYp7FP7FoJE9aykHIfPkBsa86+QrN6B15D7bSK6quKGkAj//NAnhLSV\nHNlIXOoi1rZ44ywuuKqOpWOXbLFj6QVo9GBx9jZf3USWF9S5ozJ3CertFYScyBsU0wlVfTWpOc6I\n37vX738S9B/oRyhMi8E2d9kv80nSKpkVBurxbjyewIUyAu4/s091rM5wkCAu2o+p4jeqOT1mwy2U\nFidzBs4kOHE7POr//RLdcjiw5HA9WqcRzvvmaiCZHEw5OQIxR/GvxXOF9Y2V0q6CrMt7YN463Khf\nnAKE4NcVhUkeXSUcR8ndaMEbAByfhxCULbanz1ehj4Fj2y0KV5u2xxM/oijgCDz3fRSCv/4A10Zj\n255HRBO/kVK/lPI6itfpvxsCLJyQ5Lo0UAXTW+NO668tcIJyx4jGdvbA0/FMCqhU1oIaw7GyAqk2\nlIP5BgtAqHd0oACWKNQL08dETwSs/iGJodF8+2SOQbe3DnZgm475lTH13hEE6/RVmy1v9Q4qYFRs\nhmc2ESd2wCbYJnJLb3zyt8d5ATmSYadeNSPSzdhQdZ2EyQgB6f+RL556VpNoFo/ZyuoKg1dZMn+r\nX0lo1rVBKo4HPbABhwuXdAwH5ivNWYml6ou4pLStrHFyLxYaA0mlMc4UsgCN5L3fFABpSMKhpnv5\nD2peuFB/fL/vfrrpwZjJkobafMEAuyAmipRUgg8ktSS/2BuTRg6GGb2pWNJRK8L6V2/W+BMUGmBS\n6fKH1ifNp7oMHAUzhe9PIxMkUxXn5hFxb+1DGw547Io7WVsVb3o2bp8RT3DNT0TwI98rvOS/R0B3\n1WqNdoj+ZkUVLGMmydZ5COQCRbtPBPe0hhPEV1e6usgqAH1cmFoqBmITJG8Bd8fKG6Vc+GJjjVPK\nGdayrnJYTtELqBrDdn+/ToM2wkS84zFwoq0SXj7m9HxoCeJSkeMONqw6WEIDp13U2rzUylAz+bGE\nyP5ypoUwv2E0XJEtlL5sZKxPjLfp8RxAdK8Bh1FKEd0kVA1/yYkEZoGSjHV+8mNE05B5I94YGJwu\necB40iHaw6CeTUlEC3F84xNqixG/6KtMH4UZP1YSVuGXRBiQV9qV++aT/vPFAQcTknfMtTHu8Ief\nG2mLYzNIOQcJRkwpYSqhM1/Mo7maaecBZ+O5nbOuOYExDxvaLWXlo5f9Z2m/bxA4XCOVzVwWJ8PH\n23y3FnVK/BFMgg7/as9y+VUUaPWuBIGAljDuBZwRm0bTw310Z37hdeFNyWiSrfjUk83Zl5Bf1cOW\nTESkpBPvWpkTCP7wEgg8J44nOqUJOTCXbBwLToaLy409Sh1h5ZFb/9QbcRwHFW2Z5o1zkd9W+eEC\nRz99EmQR0Ny1bR70bd40i7/XNL7VEqBLtbPYUItWPqEh8ECgHQG5TN7CajuZB23Ujrz/uDClmwvK\n9DPuqrwTprN9ttG/sieQhWAPkGVHUoYsE+oHT5tqs/6EafvH5KSbCxId6qZ69+PS3V8VBPfoTbSq\nhjNiO5gQ9Xy727Sl1rxU1RStCf37ijlacJ1xCrZLx/LgkZFGhen0ldOYyivqd+Xs6I9FCZafk4k4\n6lunKeY1fYD7GSNP7k6fQE4ZQj+kku7WcImjudx+yxlwMwFe15FW+zTNTMMgUsX3wNRtVYJGDxP4\na7MBZakvuPgR/VXrC3uJCNxp1VuSRRjqj7TfhBQgcFZrm48JvSEUKhlbIJOuWjELwxUk+rmO8viQ\nO0k269ewq2qD6kjlFwZgQ8kSs62WgrFQieCnEEOAqLhT6A9t/gRUn5wIGJJIUbXqVIuFja7ou3YU\nj6yytjL80K0M/3QbejDlxvQ7lL0ZahWVRzPqTOKT0fSTNOkYPuvDpnoJ7G3iF7z1DYhBPYuaD71l\nDZU3TKgpOLIx8QVxXQKyK6AyC2Ci/0ltW9JRymHLc3kzQhuLtJPOtvnlOoPRfJ0YmPVfAUzAW5wc\nyMZaSK1G9bjYiTOgmcxB7zdPrMsWjF/UYq61WY1wwPoR5+1EweRJS0iY9QdeE/lVnexz+7yX1sqF\nEqPlqJ3bknOZMipjxNiISeT8auV40fVmFJgfcdHptFsSSx6FczGGy/G7t74mjVrAuOpslh9DnrFv\nkoTtylricEyNhwcnS4pJ+HJeYhUo9dnImxAx4ydI6WKMp2o9gq43IYTBY82BuyZdsTCytTN/9RU2\nAJ5ZoGaCrQjaeF3nJGy4Jw8O0qAalTr6jC03/ZcC1CPuuYtDcJkx7BFDwqRTazNtI/2v9n8eSTNo\nR00HEMlUDwyYplvvxA5dcxK/CWp/wL75Su2Ilen4Ia8p+sZObcTh8trg3BS0Rys9eBFrxjr+Np6v\nRXlfMYhodMUCiFoMLEscGzndX+Aus8HKE3wZoLh/rubMTVp0gW0nsghDBDD7AARyKkcOV0WlcErg\nKiiIqumaOTVhdUDow043AoijbxQr7gNtMqqC2wGYNdJdkAzGHXMq4fgpZxKXhcvrE/cwuBwukFeh\nVfVkrcO4tfQAsqAU4Q/w8AbPnUyU9hcq8kYymhApv5RtdUM1/F7VjiE5rnMgu+93pk++6N4qShCl\nxMkCTL6bv7R0CqDJqCq9ZQCfIZQ7HAsMxjl75vwoMKuQZ8VXj2aQQPxo10HRmVldtzLoKUVLRj/Z\nXAJ/A+OSFjJF8WfAqvQAl6M2Wpcg3G8HFSL3nYouRx+VM38sclupciV0wmJ1X1fjxaF/Fh/wVClz\nzrjO6OcT3BuzCgpHzooMlStf6/cFVwU95SaP9v+0bGQfUVSUNkspQvJbCZbnvzWYOhgBO4wClhkZ\naL+Ryyii9GCYqmYjneK2K+9lKRDsZpIsysaZc6rgsnO5uD2HXwqEvnooSBiSqZHHok9bSSIexAB8\nkb/hg73z+zVDgVnuspwtobyMgHsFKFqFZ6AqTxVMhUrmZnbdHA6hay56DXJbXaz+VEa+kVeRhIOy\ng/dSsHgmlXWBdWzo6swPXWKTFyo4hHJJrjNSyz6FgJnS7lqei0wxu7x2wdf3LEmwG5hS7IJ/R/SV\nnaG6/JTQeRZ2mKjeGrlsVaoZm3EuTK+nxnzfw6SGKCwdyW/TsBeQEk5uta7HB6/BkaVCiWdFxmzs\n/Y4cUUC/C4eNWhbZh+G69TfvzsWn10nsDNHvSevltZv7L1xUFVgSqN70bzEcjfhbE4I8WpDbkeQk\nzY0bXhKLMz0EBbRsSDfkyZqk5wkwldbtYPjxyYDYBQNKzeEt2lEminNN9KiTPLBWGb6uVhwOUMQ1\nGR/CabdU2+mlha+oL4ZTSnihIU6OTklpQtpgA+r+aLEXYQqdzQBO9uzQDDl256TLcLMnDb/328Wt\nM8jT09u84qKfLJT0lwCmfWpUC7KcIbvh+sjcLlqb9559fnrm2Vuwu2vThHES0ngW4DOBT1mDXAv3\nQr26hUoojovXVKWMUVX/9+XlwaO+VvFFjvH0TdeW6X4x/vqJofzUGZQw/XLoV/0h4yBd8nVFUXrj\n3gSG4WzMqes8kZhCpgvcKPqLZGLel42n9rLwqiwZvSImuiBYNk7VIEzVxbSAN/YngIrwejTKJsJI\nyIPpg+xr7iZspWmlRofjJhhuI2bEpQpBWcDskyXsTj5umB5iFRtUcidkodQMj49YJrzZfPvtcGFQ\nqt3fBh2CcfWsxHPzkH0RaYnmmLg8r6ipE+orqg5lgu+3px9QbwelP7cgByMh3RLf/X81is4fFcF4\nEVl4W4uGidj1QqMc5v3wAAgA22anA9xnuqok5II7rLHaRNXZh9cVSRo8zz0y+bndjziocSxcNoyE\nFpUENrk2500gNADEVQTPqf7W++zjxb2DbWWvMZwRFL06Sf7eN0pQqyG7M8dwv23lX1+6TOQMoc4p\nMembLs6y9RpO6ZwHXHjgUxIa4EWbevuz2ndrCZ+yL1OOKS2EaL9kUxFFMNDFVrgLS61Wt5B25Ds4\nRQ+pBAjCLZ5O1Qy9b2oOe/W24/x6GeGWw8O3DUCdV1/2FXKTtpFOMKINfdDqmd1GpfLM4oTEeM8l\nQbj8ZLzQwpJR2ZWOipQ10ZHGej/6y9LOk/Ar11gT870zm1Cz4nyM+e44aSEJZ2rljL4t8RLIN4In\nj/xiVPpbfaax72+JxjksdlUs9GqJsktZ4g5fyLogPDFFykimg1mZ18fsYs3dhHGxUzHw/Bwvc6pm\nWRvhLKX3eBoVkRg/3M8mnvnnrftZ56Zr34s7reGWcrIkykp1XRdO7nQdhlmYg1iDeB9+OWE7qfhK\n+5ZhG2e5z3Zh/T0fplxlES75sOHpx00PgcW6bjhfGc9zeU98E9SwmsFlXvp5TnRfQZ262L037vse\nO8zB84Iy3cvE4nD7n4oDTMXBiTEL5uoRTFT9S55es2H5liiVPdrjbP0Lu/sGkUebyWGFYH41eTub\nDIc0pMmCTHL59blSgxB8GHVA02QW4tU55uzQ3Hqm8A4vMZtKkW4DsfsVSyp2hmK/j0tdiamU5faj\nxPK1A7nFiIACIOnzpwaD5Bt5WzqzsPWyNBAci2iVXzpTay5YwRKGtXSfkZ8V5EfdRHx8eejGfB/j\nsjNQJVQZ4PKEaA6q8lSxSVnNPb3rjNHI4SBOa58MSdhqypRwu+61qz4I2y35waq36RrvaIIBNKHf\ncTKuVE4MnyarMiY2zbqEwBFUOIKs4EluwjnBKr9h0ADuKztBYvKQbmmHrNOTPtd1LmwtkalEHRtr\nN45LNg5WSN0fVeSmHrrE0ry8KBmLm64LZWcRWyOpErZF1FlEDMMBLt33qRbRj/QJ54ke2TR2J/MT\nCOGquhhfIwk7gmfCDsABjl+/jTjwkq6jYnloSXB9GR2cHWZLQvJdhvEv2uS2jpkL7qWLIkc+R4NU\nty3JQSMaYmGsA1T5HLFtXt/SiAMXSPz7tt9R1yt3UiNJdbhOfKELXSNgw+ir1OOycmiX9ijqdsHw\n1RwF7fTtYhGOLihNHHRpxH8tcWMDllWF7BotqDclJJ1TBXLij+FDJgSce0XtOc/EoeGisSfbYyuM\n4w1h1z4u/KL/U0iw/Jmq2WO/fIBwykyQ85nrXOWiGVpm2MRXwD/E+MjgoDtV/cWFPU0CKbUXg52s\nroDbLTzErmZtaAuaKMBmkaOQ9fLOhYkVbMPS1EEQQsio3+c6VSeKN7YQujfu5fnx90mIdpFTHFRi\nZHMqADNKMGswP3as5iq962F54Envv3lK8UTh4d6F11ptttTlbSnE8VMFwe9PXGMBKbkzoD7jDXP/\nICn1cI2qKW9JO3yBnYxZH1B/h7cIPdBcdJV3TSgRvuVxS43metF/JJ9txVgaBv9Ub9rIEixwsCm6\nd8OJuGQjKZFUQr9Er1jeaaBjHcme2gucLlFQKKYeztAzBpKNjdW/MlrXK0VWW3o6vpy6OI0ABoJB\nFJ9llHal+TzUPIkF17WuO2j64lIjkG1tqDqP/nHxZh4FI3/O2VCAPyatrfZHm0KuyqA4zNeyWZfa\nGBYxyEFp30/5dP9uZ/CgHlmkX0V+xP3xUDeeOGI4jV+3RXgE9aWNjVtdnj3J7IHVMfnKMx7cjOL0\ncTbNkyFFWtwPSsXGNe2mv13VrzcgfC3uW+gGNfm+IAlMG8nLrJeowhJYcA/K+1/ShIGCHhv81okT\nEOpmOmrAYo/NjzP2OA7Xfuf3CHMILTcCYxmirFwY+z68gEfmx/lq/vUofg7EZBnKnUNhwkFWhexY\ndVHJItgIMfq5ljX1tx24TFSAZkDqECXrzVmYnczKQBj6LXp4hvW4t9FHMsENJhah0IwwrKHTZj+J\nN6nOPpWG2UBY+Dkg5g4TtYshEWmyI3PVyz/xqsQsvQeadnxwSrx1RtN4QS2ZdHAoozgOY3JQKctx\n5Sz3YxYUwKJKqYW95Hyms6tZQkLm7d300utCkLnYaraSQ85jry4xHMIJVIsqzdLYDpR3h13OLkZa\nZZW9S+FrbtjC/HSa+ESyxkrmrVdHosomSnKk+j8DLhAYdXwuQ7tHYnhUCtS2/W3r8cSqEqM5PT5d\n06/+kcjIhOYl+Si1db4UrgFm/awSjm/IKmB0J8PxMtI6+kkYX4vMe4sPruoOqaF8S67vuaStIhh3\nPtDae1wGFqF3Zm5SRCZ0HDQp9yS/jnFp3A+K6CnsrlOmvR2rLn88NCUvZCN2KL7xCghyEVL77wd7\nS7tajQz9xlqL73zEhkyeXdrh3riQbTxh4nC10VLLECVnQQgJBZhL/Qzgn1tnbkqoh+w32TeqwJ7V\nGwVRYAHITUBp/4ZI8VEIkDOAKnei26ub6TgFsqUW9cmIfczzIOXmKCtuEfGOljrw6EMKqJ82/pDx\nCgIqszzuzjb1zFav3xDW3lvL68+tQxL5NQpVLy2erZf943O1DAStP/WXzNgogOneuBTF5+OkdMEL\n+ifyA3KFIFZdn0GMPZ3Ivr6XTAzhFwbaHRGGmUvkSuV/+HymBWe7p7wL3oeRHaTIjtbP318XjvRQ\nSSvFvsMENl3g/eLdXhohLZSkSR4/zF4H/oTqkzxiK9JVemrXr2Zqhi9FBpL9DFduiqgLtXoSrVI9\ngBfhayG2T6I0ct864KWAqxSuDvui3XPpv1cwGf5NXsUCmE7FOqDaWWZXqC2KDMOUWRiF8w49GuRt\nH+5QeFuhMGOIhJHfI6gN/Es/SNknk2HDYIZEZUkU9AGY8qQlyuTpBvYkLROwcrMDLeJ7RUJM9VgM\n/R03oHEVszQJ4Inr5MfJ14PxuyzKNi1bQ3vS6Gq0g0WqRXVOGhY7l7qk0gkzvKGePSMtOMwBDm2T\nlPQgVQ/nG4FA4OsY0QwPHUAHLDwUOmrxcp1NtPoymRcK/m6iCLn1mkG7xBacT8gkoIJ43AqfiMaN\nZWJTHrJW9/NMKgn9EDRRKdbOEeEiWU5AlASNo+T/Qno0PQM6b937eSCQKcliWQwrpR/jVOAtUM7L\nuklH1pUnZX8OMHNuQ9d7/gUj7Aamkromtj3OV1HnSoAGcr0yipP2BV7HN3k4suGGoT0V2FgM0uH9\n5BlIw8S7jeahSarzPlaFMQamKYxoQrvUagwqtxmbp6XpYcHE7UFg14uCjl+0zwmGz6WAJcBw12lz\nMblBZdEHZVJMACBoslPp1yHT14cpwTtCo6Hm49yQFkrSsCZsk9rG39S+WD40MJy1vC9u3Bm5RKK9\nqLQWMoLe4xScJeq0O18T1ZxHmWT+gocgK2tqKgGKNFpGKCpLh5Nk4ylPxXh7x267789Z6ICL7gLQ\nq4eT8Whr7bSeXbD0wDchzljDl5toZBuT3kuMxW6qj+sMkpI0Txvk97udT5cO9liwZR+KAWifCcsj\n19rdqyUoyyunr8RtJRAXL7wZ/+GHXfgFB/uuS1+e3DXY68CrFUOTlgpZr6BY/xxfwOsaKNI8Wv9b\njDU6rC9E7uFmK73gHQ/5URIaKLWbfQ7D/UDv6K9WIHE+46Tuc9Fx/nfn+W/F5Yrc7oH7vo3xXktR\n9wXh1w5Zg7hqRBX5Z3rgvkiiBijBIGAB0n3oEfl+f7RQH1MZmhYljIVnQGkUmTbTXjiwiPTagZKS\n/ecv4Lrqx0Gjpp2TRmcCYk0gVJd5nZjwatnUsn9yoIbrqWwWO/HamLprkAawh+pFGrfJzxJIknlo\nKvs0Zzjel4fyT1uze6GrXVdqAybokMw06xTBL7XrKg/7Ik1TaldH8XgXv8qZSFCONBfWqauPdwCT\n2FedG8dNb1Y8Ej6GpOyG8XWB+h0Ps1UDuiN25gQ3ocDXX+0DLwvPziHhoN5/HITyReSPhrZDSbFZ\nzf3BezZiOxc+Tr2Up2KSUaXitaznXxP/EGKcKnzeHzIf8SWbl4eHW9IsO7Nx3QRoUcpFzbGge9kp\nkUO1FpSgX9uTiD7KrDVMWNwLl7WHBjlp29P+1KppS+LksX8OHxPOXxsAeDmyyof6AvjR6nMCJ8zg\nklPHt/t7ZuMHfDoU1wkomRUAF/mppQkgZnixIq1OY2ssAWFNikRr3HwrgOMgnGHvDlDAntM+vy4Z\n5K85vIINtERDgVBhF0E0+oRPP4355pKTHOJw/EEnWhqDFI2Pit/1xSaevbV970HuqEINjHB4R4i/\nuAfpoqSCqnNfXmFpYImK7qqdIGh0iKJGCFtDKB40BStKEDPM8EFbuj5+WkozG+zN4nia8p+f335D\nH5JA+4dHl15KujKPd+yPUWq6as1gfMVn7YCDEsJk+UvUIPImzJI47wViQnJmvxzhI6fOCZk0Cy3y\n00gNAKHO1bZ3LaGXdmWIq89GDul5Ah1YVEUcSQ7ycKmVlaqAUHHQPzrdG8ULUH0SwlPwAFMKfxlU\nRqwPAmceSj28+ahgJ1iAnxIJeZ61F6RbqgjM734SS1GVFZ0QgUi7lZxgker7F/DIktY9wcfT2FXd\ne+SPHkD2ewiWuYWje7ehjtNO3R/6L5EOfl8jt81iOuYBVYmpqM2tclGXK+ubYzLGPtbeOi2AbHO9\n+hhpjwM1vmpY1qaUMUiO9ATGsDb2nfW6CgoUVXeODnVyv7lXaBToCNU7J2uDPNsbm0oBl3i+7J0c\n5jSqXM3IzesUjT2xc+ksmP2/oVoAuvv/Mu5L7/euIOs39s6y0Ce4gPdeXY9bfRT07lB4V37ldw0/\n33lrSChBlmrubw5RviltXXHDR854bfrMDP/laV+vZ2JAMvIdskCXdpKl4XnvGFagYF4zdqkgCQZz\nmujST/c418rMwhJCABHngCRD3BpUNuY+bJ377640D8OCpJG8V8sGQjX1LK3NeNCxqUT8+Z7MtKQU\nN8Ke9GivKOguMESwteqZRVEyxTaZVGeg6aMg2WmYjH6SXpPkxVebvxjhJjtTZfXZEet3cCkitT9P\nJRgkr2rBfWekTJApe2N0ZxWR6jph5z3Yywa1GDYVe5JIWj8j/sBX/A+yV4PDEJlApa/9tr2irJpP\n1KoPuGqo4ZbF3UhA904ft3yjBR1olAUq+Ov44+Vn3PpQ9yoCtInYMhurkt0z/qtmwpbylxsewptV\nw8BTKbEr623VVQNwAkRgTyvwGb0cvOi9y2R6IK8BzTAjAjVchAP1mo1egYehnFFpqoZQqFLVVHjo\n+w4McTYL4LfBM0LEi88jY4sRqzPGB683KfdU7MBB5tyRKfFKgbqqQwXOcv4YRVu53OsqQknA2Jcn\nkpiBaRaaHJG7RZiZhP11CvvPa/4k7juh31JIyJDgPf3tMUGF/dBtzy53YYJyFz4DwuQ9J4T432wy\np527UGyCzn6ltWotdzshxIDthrB2wry5mK8NIesgWgkU1+arVYcRDgF/kKgrzXh+5x0RD3fS/R60\nQEfZOIpM9QiDQzJhk/LHsQKhX4H/rmU4DUGFsXNlwzrjj+DPMNcK92NT6VpyFGA4tV50ubwysLN2\nag+NYj3KmM+6wCoKZxpy6XOKc4PKGsraBpvdWq+/gRWfe924C5oBPvx85VYe8qIma2xpqPFLGBfo\nHuwCe5Dnk97vB2gLZCRdmOBrrRd6SK27YGbeNbjxPOmbM5q4Qu7JLFc8KQhlvv6VZiVmiYI9UJQK\nJIk/sLFqdnerVu4fVKmSt8gqW9r/EnSBoCaTXYffzLcM5+SSTXcw0cbq3LKLnORtowXMzMHsqAuo\n5q2IacsuEjeLBA9Brbd+yoZmwoAG2TL0JuOpUN5HxX0TLosvUfFomQh34wQy7wyUZHedRYelDCfY\n00oODy4VJEQwp86MIICyTNr8WlwarN+5i1ijyyIBp3ixPo+nY3WogVUNV8fWcLXn/y6ZYR5v/E2F\nJrQ0cIsZWXkwDVIpzPqhZ6NdHW9O8+aEI9SGQRpNzEjUtuendNI64AbuyKdMasOMre4ifG8tldiw\nBMU3D9SuQdaq+2OI3QZ1Xn/3oWADAJIdmTcjK7M4fGxseG3Lz114tvXCRGyxQ6xWzrTHqpdcJ4ns\ndRM9KJ+Jdp4E7OJl+gR3dgNHVYB3OiatWu1l6LwRGABiAPk64jjqqyUIlWJ1/VQGYeWdZiq6YkW+\nqrhYlLCv2AnJsNiysvr50gqCJ+oM7LrjVQjuJvcBnWR1H1coUmmUhKfEC3ZNPt9xuHwTYou1Yl+P\n7t/9pzefuACrZvvGImwVt2YLZhKZuyk606XYo8AHAcurEFSCMOKVm+rrCOEPWrRnW8MRHjpXOLT+\n23UBE9DRwRcCve1YvJXf8HOaNSv3aax9CJJ0eAfUV50Xb7X7O1vcL0lZ+nybfLXHMV1qIZ1k14jQ\nDPc8JVf4fnz8dYjSrkXMHV6Ij3HfNMSZnPxoMUTReEVg9Nm0PVc/9cPhB++2lJPakvPhwX0iuUQc\n/nWruxGY2LR8ZsRpD3J7oJpmEX3J5aME6QZNX3hhVHYrpDtrt27O5jrZNrjdWVsMEcyG1QeYC91I\n1QFh93GvPJzx+/hMXo1cIRjbVv4TVLQBGXiKyS2XMsCstrGYttL+SXjdTVXYDLpPNxfw5nsqyxWN\ncVVhxMUnucRLEph2JAzWYNwtZuAkfHaObbmFYdZxgL9q6hP1uBbOpMGHEPbBAvr/9ZhC8JWv6vwS\n6O8+jtjsXHewwsNCGbeQlPZEAdhT5NwSEEk+pHHKzfnHwQb2O15dcKqf6wWLWljgbxo8A6WDKw3y\nlldmHnvU1B1SsVs9z5T3kN4NvyDAwCBUoNQCPS8nMx7pUV7cZixVPTTN05/VwJs8o9HG1qD/bq0m\noLMa9/Vi5Xu0S+8/LjFtNn0RUsiutMzNmbcnwf7lKctTbTEzKL6a6sioWfB71zH9EE6btDijg7l6\nR59xgUbvXKZ+NniA53CMGfFhLwyID5s6GcXKSmn/u7YAA3KsY/M4/9+6iqUAKGyoHhu+n5X+YYsq\nLDfdvqbDWA59tp7dU0Jgz5wanU+Np3+/4ikiLYd5gfZ+BAe9M46FY8oLZbmi0rAGi9IEy6+vr6ST\nHk+t/Z4wTdCVTvhkeErUXyYAbcWKrPLPzpbtfkicShNljV+Xx+bMwyUvRxAWhyI141A9DzcMvmJk\niczruN6CXX6+QteGAcmvfeemUw0dp21SOjlwyYfAd3TtXGCc5jmnluM5GwChiWYPoAV5MAkaT1e1\n11OToYsBz+ioq84eeEvHpa+Aj2idBMCeJwVh0hV4t8HHA9YGdqNG+XJPfoJ3/6/ZYcQxCiW94oej\nuI/Ef5OiFnJPtD5rzU8fzioSqv4H18qvsauGhhoZ2hQbiTDiZg2y/xFPM/sR5aSfpb8mNVjOnMCX\nBzIJJt0Nwa0zWB0b8rjSRQR3cZOK/0vIu2g7h7tct3E8MO4KAzwEV+ZK3So1t9ezGK8tL+aHDSlp\nhabD06Ei7Q9WmWv0YxPZdUopfYGRaqzF5GNSou8TBBGhCEcFVrQvUQk7uczkB7LZKwDpNfQWBab+\n0qYN/kTDGh5XyUE5Dnp5Wt9yck41Zv0Cy2sj09AjJehQ708El/WpWbje+UHRuBI86YQ8VPic4z8W\nXebUELGb1fT/cB5TKBhUZyU1uWhBKgN+OhbV4rlVUj/XMS4jlzgiWuD8Q2jnvPnVxXdHbOhITX+7\nF9p7gPSIS1KedcxQbiuo+G0cFdGFSEjTDaDIN2ir/SP5NMfwj3Ujxs7VsV/J3C3OsAwJezgvsfOu\nFYylLS89fqN0tnC3ZO4wsL0u8sDQEEiDWVbl8WieUagBBrFgbQ3N1vYsuY4AZbRNDlIl3Yf1Jrlk\n9Nlxky6tlP4qZAjdBOeRpU46wJy4CMmKLtTTRYaK+ScPg/WG4Y6kBmGy8ej5BtJ1iAkq0kMj40tJ\nkULAPmzwu9R4QWCem0ofbgi1XouQI3JQTYhiINlWGg7JxLBMMHOjMFVAfLQZQWt/JOlfWseXaczI\n/QlnS3PPyXP5E4vRbCzUPhi1ufYufse1wQcBAXRA2erDXH6l3EHHDPCnZIdNZ+wNBI2g1DcKC1g2\ns+f37iKOYeu+gQ+Pd5McdWlYt5R7kaAJdlJ+WNm3g14QBh+BirVd5uAjfx7XF+qN3ZNETGKLJIiJ\n2rEF6+y427oXxVgYzGniJ69KXOwHHYlcfituTLiAoMYJXODe4B6K91RlTmFvcrYCCr/5ePyB3/Sd\nfoLubmZBWeVAeAnzFfwa7/GcbvxGZqFfFzKA9H1E9kU1FDWFde/uohyBea/WNOxm0H+j10vSW3eS\nSCCXt8aQwixzFCWkL9gbDIArjv+gczLIuIgMEviBrXGcuYA+KgmL+7Y/cs9ZsmzCpwzuFsP0SN2X\nIB0sj2r/PmIa7N25eJS9F+nek+lUlfGuKYTxlFDNxewv4Cpf68PmIvTqZ1uZ/RrkZRN/lol9l/b8\nGtZ9qeibo5AQZbNjVaPc7YDsyrAVQg34xG31CEqr6E9xnFu9ZPIdJRZa/KtxYB1xAHZWFuECIHLJ\npJ0cLHd5GMZHWWfAvG3xk0S31tfs8NgfMZIN2LGCdOVox546cNTDJsPa6rP0Cnxti0vQnIpUJdYM\nwvOtX64ar6qDHQ8MuXg/UirqIj4r9AmJ8SA8BKA/LtZw+hoXs4/+Z1/iJ7cZhm9BoIyJ7OadGR7a\nNYik9Dc4bPFoweVGaYrm0KkcJoDZt31xAKnDqCB3dMqhydVG0aZE6ANt62xQRpc+8C309+/nbfk1\noCQe+oM68V8Bqk1s9oiOJwUdfPhhOYOClKM0PGv9ot5WHQLUMxxcxIHOmkk/A8BcSI90PO0aJSp1\nyb6hOAZno/fm3qoHF7J19SekRnfjCU1FpeFOVPrQWxMSv+I3hGraAW2LbT15L1Tdvu4CIFZIu97k\nPHSyoyQVyj6PJqJb2n+XOzrDT5n+jXU5GGyUiKPyCFnBAt2XhmOxLTFsq7XwCNO40sKuQ38eErq7\n5mhjmfij6mjZ5okkHcMyeOiRT6lmjKEeInKyGae9ZAwqeBjIJwIDYJI/i/0CYNC3VPVRMie40Mv2\n89k0OydLT43HYm3Vg0pR7TIzMWQcqiF9stKlzc80FWkBaCYY+PqK/zXbvNr5DwXBjbndwRWVyCTi\nYUIdoiRUgqFpMaRshV5ypZUhVpaPJRn+mw4y7W6zncdXBcrmym+TSw4s7CXJh15z+1f4KkMoH+Ri\naiLxL/HyFr9ODngPCE7Z66fgEtG7yK9kYhA+OcaCpmGoQF6ZHKyqoWaYUTSNHQS4sG35ZghyJIR4\nIxkG2D8bdaWrxg+NYPVCFdZSnOnb9KU3VRTX0atUdvzAsZvx6p5ERuIbdOjMu4d/MybkV2E7CURJ\nfCNIv20WM4bKkfxKgSVGref/ykL5Yb4+JAbWv2l7LGTaK3WdoyiQRvl/rby7Dia7vC7kDgWUqdr6\nRss4nAq0dmnYAdAigRxHWlrcsXGDQnDJNehhcRAcZzel8bbj5gl+JsO9abqEii/IMmVnno4CYyd1\n3MthMIyY47YDDG7Hsx00znsIsRS2+P9PuHGomkWu7ugM9E5gvQ74O6K8oYYFxFSle14I/B9/Lwd0\nrNXsHoTveHXOW54oM+5PYvgI4cua8E5j71QXXNsszcv7Suio7R8p3PAIjRehqlLLdDYNJUc4yy5V\nyH/5kGi7EVrF/JPdqQqjwCo/oKbGt20X1Sz3je5ebsU4/TqK7zTh7E3byng3V9W7lL8Q65U94P5D\nb6+PRrabrpMdHbiowprPCyOGoseshPSLOmMve/CPiPzacDg38kTX6EvAynHatxTiEzMOH3mWmsYw\n4xoJl4QN5pvP1mCH9gB27G633UBlQ/OvWtmu9fJeMdkeZ3RZABN/hk/nDKvM1L/QuuPRs211ngOM\nC0LKPgJYeULLczTcuR8FUY3/81OLtpK4cf2OaY6Aeed7m0vouXZCdnFpYWuI2aoNo1Wi/K8Oeu9V\nfzcxSY/Jbl3brynxrH9p/dQIhma9QMUDMybMwtTOGD1pzyXrG3U+yJYNWGi7F0C0UmjZPNTLRMag\nfveRyrIDmcgLJ5zRcvdi7yIta5kYxZX8HvNUf66Yea4H9e1xR4eKVgTzms3w8HVxvO99A6+rt6fM\nqCFBYydgtUp2AUAWWBC+LbSV/+YUA5szjftRBoDuf2YQaLk0d69qf7DdFUoj43mct7Epga55bZaN\n9vcGFGcPoz/CRABKztlsIIve5CjGUCc6+HDRS0wt+5RtulDfKbXIdVdnXZXWhKJ9m0YjrF/TBvOW\njAOkEVy0xLLxiwoicA9XnJjm1/UHINQjQ6cVT2vgEAId0Fiw5lugDicYQ5E/5ncxjfA5fZC4epcD\n0K06ZZvBeA/+d2uPF7k8CTE1N1fOXgWQNb5ML+AhGCbvrQaAVhziseZOXtNugKAdo6CROebd3TOc\nbw2RGMTMFXTwawdu1SG6RK4ry9WKchxtjkL1h0K0Av+Ub34U/0oEq1t8XeaNufDNOom09DY5T9Lw\nC1wATZE7M1uWSH7U76RKdS7gKSsMZwjybWBvnRje8nrq3zEpEnxU4nSwiJvSnDTshHnhAgJUmIvx\nHG/n3KDR4giJ/RxGjED1qVEoYK8W1S2W/7t5MelJahikSc8LZXuiUJQGr74PgfECEVBlLtGHh7TF\n5lUMEge2Dia/RfME9pacagKs7pQzOnvTT13ntFPLgb2xPQ06zT6Qcoqt7AHUvOJ2bTe6tUlBTcq6\nat2je2uTwdeK4RSBLWqLF9fctApsFWLqbYrEOQFv/XXzyeSrxJDrJg8qbHXxeQghPs9Gwn/FbeCX\nkp222cAp99y/JTmqAE1KlL79m/W1kIJh4kPsd6AXTHTxKcHlHje5wg4btT86Httya+x2cl2K2BPg\nz1fqIWZ1ZZOWzNRi97Q3kto3zJpiivZzkhjj9e0vdIdxBHAuY56XTIyhQJ0fWmc/T0vWYUUsnI2A\n+CxGlwbwzhzayLlHJqbJm5VnrkON1p+1khJFxDyn0QrfuVxg0laHxsOf+ifvCbA9PrJ85Jn7uDaZ\naGSdq//QCBPFwd39/2OKEQLHA76BviCxaSmzkeajnZz5Y62yE7QkpvuHMeRoWQw5qyC+tPeqbBfI\nsVjln0+WqeYuueZhzSGPsJRRyb017XkC4OQJh1od40mXbUdDXEtcr7Xn2lsp20Pqgy5QRVOJPLGF\ngclwwwzjVU7mTv0LfRQGWeC4uOWs/d0b0sHOi5gifMfLOFLYSv5lX+Ov75fR13kaAzmXDIElWHQQ\nxqvFGLpbQ2Zry7zWXX5aRcYVuHX2QXjbPS0mRGf/cSs4a7lgYJ02n++cz75d9hA9EM4IoxbrBqbN\nnoCQptWMQov2rMF32GU69uxoTI2RZnFlPhlo0uHGO+bdlsPGkiaAymTKHRTcJIh74JHujmDZG+fU\nq1ilvwFrc6o/Ebkh4fd/z/8tuZyfpmOsmAAyZvuhCoVLRS6CZwcZ7MPdVn1W47p+PlQR97YLD0j6\nLolfxV28tPKC8fuYFhNP07UAzny1xWK0H5kMpfxUFi+EEKYbjZkamPtIqT1+RsW/Sh+CwFngVDHF\nRLLY3nKTgjEQlXR1CeA+rg+50ztTM4DpS4s6Ahpw5l/zJ0WPRi+PmP6pfGAFKIKay8bM9+boNmJM\nU8C2TK0zv5QIlzhISZ+MamP7qZlkHzvAB9qaZWYk9IWt/OVuaclD/vlQoh8MweIHeBaqw+gIOja/\nUI2xt5+BhqNYnYzf1SLG/oAl3YqlQeThwLD0eURKz/cC4eCSBXdL96GWLd/viouVAC/WuyNpq1Hb\nrPKsDYY6D5hJtUttx3Oz4oJX8vbiN5S9l+j8GXGg/8uStLptz0OEsRmp6nJkvtaUMS0nQfkazSYs\nIzT9nS54yuKhXn/HRphTXgox1B5340TyPg8yywkx6QQ27Sa4vFQxJtiYXQRH6h580+m5ME7glCM8\nivPT4obHsuASDo3ZjS/vIisESzVnWaURxS96b5qd8ppZnvYHB8i19NYvUdcJlxYoWDqPxazpDbEn\ntYmI3vSYO8VL6d8o6f+T9831TfeFBKngSCgxBD0CNyKw9Kf6Y2nrh73YgiQtCFkkCYPoQVSzLzzO\nCWuri1erwd1TE83IghUhPA6YAq5H6CSBWYhBraNqYalEBxXSI99bwHahtfWYBkbHbXpYbpMBf6QQ\nPzlfvH3xBCJmTLOy2ooKKe+etKEgYiGULNktw4iysaxT9JH6AoX85YeuHswos3GsDvvqT1kV0s8T\nl7yfBN+ivJYI1pryqnR3p5Vnjx1VIBVsU83CTFhuQAt2TGovhzPsiw6U6xFPFlIE1xuhXO3dMn71\nm5D61zkKDBvumL2w7Mk81mg7tiHMu8K+YuxnV1xhxsNpP+jrcA+ooYG0rQTU7dc5OWNoEv1g+l9Y\npTb7swAWCHPKo4E9bZhZZ0v86OrXJDJtYGTyNYBZfutTr8sW59KH6AZptet4ZEONXYeCR3exLJ3+\nkIh0yK84qJu16ZA3rNlPj2sErwjuBAd6hPOTCnWNLlFDY50YV+IZoXXrltdnNKLm3ybMXTyBqdV3\n6zqeAjlQtoR/UyYLli4plxdQi3g03howHfRPyFDrvvMhuTBRBX0AIp4GAjhT3T9JcPlKcAoqGN6s\nKEggUvekyxSK7DkSWJtwecjotdC7cG9YrwFh+Cd08EONuS7IJgLi5fA6KIafumJ6ztghS0/a3wMG\nGpQuB6oCrEv3DwqeetyXjcjy1wAqCE2qK7HbgecNGAosHYS0ab9RzHeGSMtRURJAp6vHh0JTUk1c\nwBIfxsHNLpt1AT5ai0lQzDV8Tlr3UJnPrIjo4MRVlKve1RRg8EmpyguwTRWPhYmki3khV4/XhN8w\npgKDE7ty/gyPhwBHZ3521LQEGDf495sHpX65RlUJqE0EbwLqvsxorRKpguNviyvuOim1e37kEKmV\n18WIS52WwWxlwgnyg21fSAgz//g+1hWCeLx1TVBaz4DieMuPj1F80BLWGiqCV5oCH+wZcK3hNd19\nM2NM2Z04PZSliQ742tIQR4OcdzQcTXGdWpWBGXBffA3fFS1lG/n7a+N2pZvaerm6QjXkgAH6DUpW\nk5qEjClHcKPz4gRwatOAP3C0dddhgiK8SnRcPWo7OHL00Y6NoM5pKJIFes/VAVYjqyQWSVQ7/rcJ\n60/hjoRIQh6VWTRh9iUwDJ3wH+i3NqPTkVqTUA3zqGMb+3SeKOInZdmmQK4S6NaH2yyfS07QcxIr\niOxomZz4Wfd9Ey/CozS/a127yGPUKZIvHQoU+jqRhQOmSg9hVY0/nm9jc8zHZAuTC3uz0zCIPs2x\nS7pRDcEna/eu66PKlhaqZhM18AgzOFHkUh0gMhSFhPPGAczfaGOkA1EoRS4ixaW5fE/BmOBUs3Ml\neaM+B9k9y5XZsHGj4fydNpaWF+ji3kMTBtNyheIw9zqMu7DZswTqf1RinlueBhqdLSt8waab1BH9\n8C4V5iOGguP+5kR+ZJwVD9Xo1rz9f5G929HWUy+oPXUx1iuap+P9BU5NzFkj6XyGglmtTEPFz4UI\nnaxk3ltKVxKbZsc+QPGxaq5zoFcvIauWf7J8ud48xv3lCVPC7naeeANJLKqqbVYZSshcf/brGQCG\nKI/qSTHAIvWAS7w0lfu38XF7y/jzQz+UFAxbp6mMEDrVXpIRgjALbU7Kocdcka6+8LLhOFxGjnuY\npYR6km0eB4oHSGhCxdSmApSW5hSCO32M501iAIgyU9Q3K8VHIWfgmzfyUmw1k7ufCd3r/FyYKC6o\n96K0hBKO6ECspqCgWws/Wkh6IRQRG5c70CoF8Ld6mG6XDas+C+HdUHLlukWFXW7++naxO/4VoUaf\nhJrYwngSnLq/uakZMREdLUwlDB08UJ5lG5ZBPLCCRB+v46gMpFQ1sUYOkiNDwzmsqhLzRl79Bvl1\nPonniwy6Ci/7PUKXpyXxQDSeg3656uJngFNGaWF0IbqQiiF8yXx/8BBRWSR4cisWyjIQNstRBObo\nOvGssQLuHsCqVPFIyD5eKyZNEwRAJuBTkviW6BFNqEdLrzJIq0mngM+hTnoZTMkvX2X430+29oa/\n4vZ7B4mhQMRQ6Q4z1ybB12ATP5nAt2p0POPA/azZj/6xzlSttttW2/1bcO70txdZJbYYcnluOiMV\n0JzVx7nobQoAZHf5sgLqilH38F0TxBTRALidok5m5D+LXV9WQwFup0oD5TP0eifbxlsBiSv3M+KX\ny7+6UVDZ75+J5C8hrt01zrwAYFS5PAG4x9Lv3Ml+ZnD8KlZLre0dkM1OEqOFDQZNSx3fmVkJspxB\nmqVTkKXUWDPk9G0oRGMBw9JQjp9Wg047tjUDu/T39sTvzn+B2AmGAxcAceN5NPomaTzxCvOm285Z\n20Mru7JUj1zHpcdLyhwX1bFKXdsr2AqleH6krQSIjnxoK7ddCIdrfv6/sFEe4r9aJ2BuDciEzaem\nN7kdUn3btQZz7QrlYtuTX93/eLpJuZi2J7rfpqLdXPduy45Irm39AOVyt7V4Vddp7OdTbDD01Dqt\nbDyWKaSlKDZbcvnSWqXlXaDeIPaQNrtDODcMFWHE8n0jgFPrqXh+ZC92lnyCwbyoxYsJ4tUsSgmj\no2DWzvdR/WoBvNAGArp0MRw6nonMgkx+cWGaGsz2mMrkerkmoKovnZJHaIq1GZEEehmi5ex5G/vw\nvPJnJGvBvOreJXTsv7sCVqivteHcMjwhqwoZ7S8qnA8zDw5mzrjnY9Kh0hYR95q8qWEVcPE1EFh2\nKl1JC+6OnlP5eFgC+Mn76TXzmj2FIjSHxx/1JQ3W6n5x8YYMEjgqcNh46cfdZUQJJxhaMyJd8o2A\ner/UeONnLhkNsyUmUlVZ/MCy7zHuL/DWTPppQcAhjeAbxywZalkpMhi4+oUwmXQgJpDNhjszwIoR\nMnbxUDuhh7oK0OPghLmK25tOUmKsL/mcuzvhBIHwDjc1jViliVHe4d8HRR+EPAVX+pKpgQmHSmp9\np73qbkk1evMt1CCClz5xyBMcPjnSdfoC4Ksq+SnvlzYvnFp50tYzcbFT8KK+xLHOPzsG28XJaPgv\nfoDPNDy67w6MVg4CMlZPf9mAw/3d65Mjxps2wfdfKqgNOgnWwTi9gVRMu89LFf6wulp3Ll2aGWtq\nGP9+Bcfo6shwvTeNRmlaMcWNYva4qeJmS2lEJGRsNxM0EkfuVpeFdZdx2mAgkI+QV7ZkLCk1lvn9\nQ8DOkXpj562s2J7+tcaZJBb8SHPhK2IoeflL0fDDrrNA1hedMptm4eH+rJMUd0WVVsgGwM9vJl01\ngXZ24t5zP12F9r1zxXfKpGaOuMgyT/QPJOwwWZUOVUhuivAGJzq//+0r6TgbiauNbW9FnEOVCsCE\nY3Ce4yO53fsqCuRJYQt7aqzx9FvZw8d4VEn+sxQeC/mGHOAvyQnoqDyugiFNoFF8y+QqDf83mqpf\na+e8UORADfp4i7L9xbGwM7rdJAmCMzA6ubyenjb93bXlcqLiileBj30tN8b12/GL8r5g6q+u1HSu\n5R4GdVEJ7wuNs/8cR8njZhXiyuY2E2UTM40I3WElhd3bA4SUTE5zBpJsOQTSSepj9J0vlpeFsIu2\nhWJ+1Lew7w8tsvFjm0xJcM8jwpryxIfa8+OD2bESt1pZDA4nKox6iJvv/VODnQBkaPLXrx5UJ6Fa\np+ohJljQgqizxe2X9OT5JXyU6R6djwGWbJnh8tkaTR1Z8kZbPaWfH6a9QlHy6t8PEo7TUvFn9EnT\npJki8SUsJkqrWqVXcDom0ss78uB99EtAyicm2M9+CJQZqN7LdIeRMm4xhjIX8c6Q5CvMgO5WSfW8\nmjtQCMKC9KZ+Ecf8MLUZVT2S9HWsK3qpPFTmnIFG0wr0hGi/RNrMng416w0mXFLRHbxxIz+XDl9J\nopt+szoR82GrkHG0Wzn7PZKyRLLAeqgTpkpy08jp9WWp1RPRFQGjQspPXdWvgwh07DnQ2okAr/Sb\nEdxsWWS7JsDCN6z4j2h/rjckH62O2zWX18w4oGNj2Y+K926yiwQL+0QzlLsk5rHw57DnOME3s6ue\nZ+PbvpZJAeIilyweYApTK8b88azwKBx5lgnbQ0RaD0Ui5sermdpPUsbyxBD3slGXb61r3Yu3XmfA\nnzlvsKEkw9whL8XWnEYv6F7s1rDbEqpRJPHaYFIq2ikBLRCsIO1ajmLAuVAUjXT5mxmBPyyjxq0e\nUv2J8biyYFY5VpqXb0hF7UyOTGGz28I6flDsZfxERpbDUQIpYKCyaXETaU7pLtmbJ4HVEcGQ4591\n3QbvgQ0ri7UOYt6pOV4nGNC9OolCUaSrqrHxajPvdZ817Pxg21I77JFyO7cTa4lGowroCE4apxvw\n+1jhEr3Aq/mNglY7QkeMy2NLyny1vZAxUyjUK+hoLgB7t54qPDMimXzkkvPs3b1x7ffYhGf+B460\nfd4VUZyGAQ/IuNA8jBENkE55fGFY2QdvveQD4UIQi/8sG3rdohDI0oW4Lh++zG6kgpf5eCMIASq0\nHvgGhpa1kG6S9TPnYA15jXG6dIIkDb3VgRx5lMtuhw57JWcw9FheXk4yxft/Tv6BXaiFhuOO3Wcz\nMvy7RF4xFsI3CQaW1B8rxQ4aYqv+PrzFy9zg92m+ShSqabPXkbARtdxxt9+voo4RL0FvYRrcy8cn\ni48FNUb7scEjPyOu1dxck+fDAJhGoqtqFhws1PGb0FwEVbw1fAX+KWGMCiJg8YNwBvx4ZKT1Itat\nHb1+N3TTii6Wpn2PPDdVGpFSObe4hCEAKHqK6dfZ2e28YM7CPonjPlBIfCwkgnACpGu10PZPrI/+\nNxjjION+x6MDCZKn1CTAIO6rw17shx0kOQVZjFNXYVDLi64PKizMXW3kFX/70QT6Yc8pinVv2hDW\n8+LeoBU5o8x1M82j8jhudCS+HIItV6IErRjCXwzT7x2mxMWGLeM10BtqZPjwl5wcfwlXMhUGIIJm\nhvevcX4fbKj/2MgIyyQ42P5cykxy24GHwFWqeXehnOcRqK/tgLdsgoRUveTF1G/ivjWJYeRtfubf\nt+rQyl/duI22aiW2Cd/aYYtelC+JcW1MczUJCbKGnrx7H3UTm3Of0f2meceDzU/A215RWy8gxbJt\n3oJXy1BcC7F2lMgGKqKiXZvQ7JeZzqQ529v2iDx8MSrMTgxDZsrKo2cQ1rzoth/VOBidV8WFLws1\noQg39BcQDD8yY3tyG3CmLw6MqeCBdB2aokiu3J5tzp91nyKTJLb9B9memSyerftj9YVRMgVa2foF\nNtfAZhD7gUFCOwMcSj0hoKa+JWbU5A0MY8mUaCrmwrREBf6hYjpndiPP09WUxNqWv7EY+M8B/8q8\n/zpGMh0dS8/hvd7axwtPiL2FC0qpTU2Q/clbXhZrZqkmwYjI1Ec1Ms+yYawmZrO3jfAqWwjmjcwK\n70JWyPnyoolFDkeAvtojfuR5XfxU2Oc3B/avDFjNja7PF4HJdTCHNtjqROVDW9Y5vLTb10sxD2hi\noT6bLIri8v1kxVu2c4JJlQUdOJSE7ehlqu7GzImN8EOrIGB98ZJ/MRvhoOez6yMub3PnfDjq0R2i\n6cKER4+aFCxcB/qiV71zJQaCgEueYYrXU0xqMu0ftHjkVmXnexlcbCCqmFdxjYyTjsb4T+ypLagX\nv52kC/DC2AAuhvIq5C7acxmyF8/7zrhUz8WaSoUuF3d7q9f2JE8Nxp8pN4o1sis4GCwZuE3jqhg3\nL05RfzbMMT3/Hrk2SQrJp4pLGL0rK1VUyNv8yFeUMH21e9Z3gONtgvBuqicoUcVwCIDs2YuRTny1\nyiZu30z3tFeY9z+1pmwnNaRVjJsST4FQQ/ymYMCSZ7pqM3Lxc66kRPOL/MhsxxKnRQqb6zRx4Wvc\n0FUZN1tZT63bp1918z4fiIwzAHwUpIc4Yy+B+deHw5K5xegq1s+KVY/DusVB4jVeDb3iRvL/AWaI\npm9XaxCNxo19K8gn8c0rpKyJGRnEdgtXGo2tnZ1RLc4cHGihYz81Fa3iAgFLRRWpGp3xJ8m150p0\nUeMRZhzHraR8ckN+lOXP23RqumL/3Abq7wyXDAADhp/528A7WYltepSCP+qYCa7GeG1KyobuDN/b\nmUrv8GMQmUMN8a2XsM1vHZdJAqyy4lHxJ5aeFR1Wjji6SntPaYEmVP1tEjAKCPSWkCtLCBszNv/8\nm8g1SnBQylo4NFh/qTxTaEEcag041AlLLzGCEjUZHnxUKX0hkTdPrdhU4ojloyUJiIIQRCRogTWY\nphKxQdjzbMyNGnehk+8FhoMgkhWmRGiL0zi+QFE9dO2z3CC3tM7YbttnQMJWXZomhU8NkFIDJZMq\numZXhNT+tkLOH6h6DJ/6kcvcPbRdZvVEYVm/kFFSoFwT2a8L6Zvx1pnAR7UoWPgHhBa5voPyqvdT\nL7EIU/O87ygsKSEwR39Cd6WbNilc7HR6NY7uSwFpDxeGP/4nRw277a0Pu9UYSOcoC5EmNT9zP0Iw\njrVJsLDqnByWHRlCo6hUb2XxAn0DYI+SxhOrTxOvGDZjaLzKei6kFAGHnF9Yatn5AUkXMwypU6Z4\nizS3xjwYZuI5tCEz7PL6Vulpx+O/lkX0XMPByqyxUPCWFsL4mKCa/EwPf7hkhkt9qBECiPzCBWP0\nua9h1jzMxmowRxfH+80fK9GEr6QqrFoJUulz5sFxonM5yMXGyHNBCsAifUwySgVMiNVHNrkcLpQD\nUpiy54Stl+nxjHSzHn30JdIx68nXEeoZqyM0XOBl5S1C8ueaKgkHR+ntXrDZkpdDZi9lk5TgijMw\nS194j3co3EYAZaC7B4WGb+CruqW2SGDSnNDOlrKUBbDbCIdgVvtIPmh/rheqvUzLCYvmOGd6XJQD\nXLR/sag0dlgQZupLW4MWM0Scdu/Cyg7IJpROnLPmMsdP8/FYQWHKDQ8fi7VJlgiJPrHo49tA4x1c\n7JJ7Ae68Y+VoWCPMDxjZonUnZvgjnrcH5UM15VxWkgWc+XjmPoXg1dczHN7BT/nkqJL3StOMeTfc\njVJc9EwctNBmh6IA2Wy61SrSosf9jAcdd6MoFW6AAQ4PrOII2yjtviwbO51DnQ8L13R7IF+1eCbM\nZpMAWT2UDHv1VinTEprQ7pSEt/nMzCn5d9SlapM0r96Psa6zNuoTIYi/P4u8eRZjq0x1wr2Tn7Ms\n7NEvBZRr5jw0ickfpN9NuB30Z5ZnVpTGvgP0aL5HBGFibaT6TNJsVnPMGpLxeM0Ti1/SSI5cWBvd\nmfcogdtB1BI4j9ylr2mFvK6iWcnIm6a7M6VyHvC33wueiX+AcsS7KOsG73U8N1W7tYmukcwe7/ZB\nuMKAx/kpSPANVOO2haSU3dqO1QBIMFSwwhf+xLnKnL3FRWBHrhBIy5Th84dx81KGoT3G1aHQn7zl\nnl+4W2N5Y2HMrYa1jhyj1gJOyhAgbANfipEFx0ZLIIgLcH6P+UGy2vYQhFw9BZicuED3/q2pAx3G\nawmAuBEueEA+f1uzMv5PIFH2FuiC/KG2HNKsZORFZecx4ZZsKKnyOiIfE9Sl3CPC8sRTtJ1sgCtz\ndnaOtAyYwYv15JcoJ+6dxleVZQP7VW6qwH4ApXIoyf6Y8nE3aivx55uvXvlvDdfTD8xwSI3ZGF/Q\ncDEnUBndKxzs5ra1fqdSvi3EWjtd3BP7LT/IQCHA1q0N2N1OSVoLVjoJ0WbjuEu0Hd3nojrXjGmL\n4CnKXLDpeubIVu1H37gYk/hGkXsl6tgVEoe3n2QgKFkWG2adeBxD0dt/BYQHNEIuKxhhAiKlAZ/L\n9A9wFFNHaVB+ygThtqwSMJyvMQ13v1nLaU6PX0CFAZIQt/nCLStisOdc61Bc+OZ/1r6T0X94Duq0\nQXMNI8eao+5OwMfS5bO1LWdj/onWLCZcK2Bqad8AxtM0tjutbpkmg6mSMArt+TVTV8GbX9wUAMe9\nAcjcTqk57lJFND1aIyP9i4xAOU48eBY+mBa9sZ1YOGNn9QBHs1c+I9miQRYxjLYFaYBb6wwVaXW8\nnASjcVNfQDN5gfX3Lcp8NrUW8DZ/s2rJMeZEU7QWRijCEw5G1MBoBkQnptqwVp6tX1/8xDZR2BFR\nY22eFZnrK2HqIUG93n+MbBg0DvufAH6vuPj/6qACUxm/aDmvwune2kHbRDu+2AqWeiHDrVQPFfCg\njFUQ4XH3pZOZtGxaVnV+CkF+lG6+GoWsx/zGDaWRC4yJrNg269hhNDRayv3oqVxpIKsWMAaFGDPU\nl4F7J7W9Csdp1VcLEenxif/aK8Lm8j9YCfRJ4WxvDmftyB9iSfUD9L7v7RHLHHwjNzA0d4PrUIqO\n08Yo2Hj3EQ3NuRZi+y2nvQSQ6L0EkIRhBQT4sOolYL90gV+hsGJZbi9vT8435KRsF4ZZwX96oCSp\njawuwpwo9vOXjbvHBe+SnWyU0rZvwpCdZ8kXVDlXerNkWhHvbtaTxychtiuhHqT0eQ35/8L8OEll\nqxFB+s70XjQSgnMRmgnpn3u7rLv0vd17iUU19AJIghVk97z0C1a1O93B3OTkxnvFkYd1tdHMInCm\nrDrFTD0Yrs/T99qOG6iJAT9rFSVVBaH4wuP87B2R6TC+jN5bxIuvvTln20sPDqBUFLEDwQRxF0vl\ndvlA86CMUUn7UpxOKTD8Ocm3FTpuAiOtCLxS4oDVlHrjwN78W1Y8LWNICTkGl1T09Ynx2niUH7RW\nsti0h+b/mK61vnK3semFbhKJzZpe3QNndhxIqQwkZVpDBEK7/cPoQ3pPUm4gnL5BK+NXaxDDVbSa\n+S/3I8xmC5+pVyv9Wbgch/fhlwceg//tcq2u0kREP2ydxo/MqnGHgallxs9DrlhQFS+gAmtCD+RI\nq/Hb/zHEQabKMcC04rSD+bnX4zjy9s6P23IZs++05Gnp+VShK80KbjUINd6YGuz9/hg/6niw2pC8\nfbD7GFTqvhYRNAziY/pwJc4ZjNXtz1xPM/DRABYIyZnlQcFafyMp9p1o9itIoTWHe3n6QYqnZGW8\nEd2aVQLFewiLuYHhc5jgCch3QJBMQj0LBCHwjMCg569zx64dz0zTEh34VYKcAhQFXbehqV2cOH+u\nVfNX1bPOUnkjHHTMggkjqgPZVCeyOtJ6RpS6VVStBpt7VWaULHgRJxuYhM2GjJLoO/YkR/053TPY\nto0EMnZMZX5yIK2zMk8icbWsJL5dCwnVPtVKhD6TNXR+Df21O47ZeQfr3RCJWms9odYr4U6aU55Y\nDq+nHFWPlJqTb8i4DRPFltOG10Ny1K/+eMQUlu5aPA1axD3CudqYTQVPNgO3dH4OIF0HuWgaKLkE\n2/bnpmFVwqPRkQsCY3qB93ntCRc5B7Qe57CqgE+XiJ1ob+7O2HrDWLVLigKzv5Kr/IOp36LkJ1D6\nOBUm7m+Nd8eXW2VX5puYJ5XLMKiFBmU88nsU5/e3RgRt/xZ5VnwaDV+swrr4k4d6uIblT+W/jdVS\n/rPdqNFpG11q4Yn/KAEPXhjqqi4GGbVY/ovOJ7Oa7SVWRA/+PY9bdtryGVfwlQYmAmUwa0Jy73Q0\nJr1SQ+vUEUenCwjm7SXh/kvnOl1vUSVwAWnnrQQULgBJrETGShei/+0BnCj78pj3NHuW0DtnugE9\niuimXW/RlUrF+OBiX4QVN+ISQtmlt+YZGiqRxxr78Q2feMdkomJCz4LyGQgUcyNvGJopaWGdigFi\nXTm4wi7jgtUIQPrX2V72Ey1Wb8Oj7sc9IxKQBbv4A8V6/5EhljYr7abGQ7WN9ToVBexukpMDvasV\n4a9L8Bw6Ca46io//QaLNl2fy8c69pbE/uIQUJgfxoPz+U1H94dKYaAGdKaKhEq7atZ079ML/nKpc\nvLe8mYDXOcENoQPPY+BFPWAxmYH1QyvY38x65ET4LpYYEOWob/CYPMc69c7tbJU7loLfyMKDQPqK\njWdqGGP6xprnHUUQKvS58G2zJ/EL2e24StrPyOHbmje5YFV0HETui4JCT6SVWi3DWXMPjYrS8spe\nWdBFDixVPZVENT5CieXONiLklYv/NKlHK9swomHOlJYB/LmxoaHfer0/PkGfsj3GieiSmu1QKnwE\nztdg54qRH+oCR6NvFWz+DWiH/OQgZUVEtNYSRNXbCeHWcvwwDti5HIc/BvkV+fSeRL0jB8muNl3R\naeDl0JoabJy+cwDB/4Y1RKPBU5wxKNS/T4N70k8+DuTx64P1tZzO7UeFGxEVZrddLP1/LYNQZH4R\nGHUXMx/PK5QIDCbdMHXMapBmHkmq3q5V6Vi32wN2nvJb5vCLpwGFhTcrNmoTdZGZmfoKRGXHwR4C\nHdH6XWtlHtaENuACA5DkqAIDXw/WbVjsM8lanWql0Qp3psovYHNt+BuS1B3vbMoBSJoie7AbsKL5\nI08UuEPNxBYp8FY6vBAtfvK8vCDcSC5igAeymmvoPd3jS0NnnIoRchYNkdMV0hxfnQub8oQ1si1A\nbvuLjdS58pqJSj5dbsx8IHBYtA7oGij+vQrO0Gbse0ZWD1GBEcxq9lhblCp0+uYuVjIS13zFigWt\nKL2a4ZU455v9tmpQVH1YKHXbTDPa+TZATqDcdzoAl0YAmTh+rHtNifWp/1Cx2kxayO221ZF2Cp8z\nGFfCP3FcEhKqCoiNtAuxtPuQyn+FrC1IuJVPKq893lyi0aEPFiKaSJ0wb8ztyix6nyzBDpaxX7uD\nBe340LLedFfPyZH8EGNHvjzBS7nIMSsKKwOEEI8Zc6/OJuIx6TOMiWh1GLjDpNayvY4Um8BJFpgD\nNO7OF8norgVXGER5z+7SokXcU3Msa2hXdGbajJd5ghW7ZH1X9Obh/s28yIUC5V6xK7GMXI0Fe1qV\ntlLqCq0FPE+MNyIFy6ZzDywDpiXP0yFcJRa3LZgNqjBkb73ecRhC1S15Ug6kH+T+aoydE2BxB379\noKKVto4vel8yi4VaN60LY6CHYJsxPT4U5GzuVJ1IONZJ0juluBZtdoFNdWvO0lQg5bbW2Iow8HrC\n4iksVLZ5atZz+BYc0oVoMpRoPYRa7UAauyY7JuFToZ8NfjEJOSziRAmRgAG61SCdt2EFnFt6m2Id\nsagO1Ts30NW9vEpGqMmMWmj1MqJg3XfhBAECmVh5mWwlSJV4/fGteprCkbXmWZlGFXSEu6YAs9aO\nYmDQbJ8COANaPorQI8k5vStO9tcyupm3P+x7mOLjkUXPYnEPgxbSPrJCapSqW/ZOQ0oLo2n0u7VB\n7I+jn1AUYJra7aJnnpbbCUNZP1Vqj1ynQdoDA7q2I2sw6irns7z4HgnLA22XFc5Lqo8FjMU1X1uR\njGroHOCd9IaMpseixZpW+ciMBkFHwj6itrr48rcRxeaPJGVyNV5v6m9ovdWXlfnje9506+eIi+3z\nXP49qvxeL/4+/uRGlmyrf6FAyVK/uoqwWY9KzeTJz31/KWfiOCXd7O7/+UlDA1nYOPm+Ob4Oh7gD\nyhldsM9iHVCElJfQD8W6XL7fcif82z7EnN7whzZIC2Z9Ga/owOwB/xx7WjS3875lhZZ+sRq+gTVe\n+17M/PN38u788uLxaeTPUggJGSi/6jaNr84aioF6FI3aF31LzXy2JG2DjjilWIWNkuB2aBiTGLVN\n9BbV4aoo9u9XVVn8OwTcoHIeBJXQ2aPi231eXr+E6RL2G31vEgF+izn8YcjsKqS7lMJossLVWgpG\nuu5D/+EtMZyL/txhijR2eos4p/CY/oJqUZDr6YnqEWLDqSCZavqxH3XuZWXHAXUik4QbyAO6sCEw\nOS1G1jSC0t7bRlvEqv2pc4Oxu1TtVlz1vJTab5Prk6fDB2tGflgVexQWoSt/hW1wWe8+dnn0bj9P\nnzZX7gMUy64qg/impRnJ1XIvsuwGpMbiCwPhA+SIvotPW4lhGNv8x67i4/Aew+S9yYHWlD833lK0\nSjKtbyeiTFiN+H3rmjn0jUh91CMHEVt8Z26PsaevJDIMq4JpVYlSGIaM52AXaFtueBjoUJ7QC/x5\nQ9zKfO+yBCc6fOSyZzFvXbwuplNcEvUd6HXMFX0Umea+MdSQYfp0rLjHgqmtclycgoc5ixotgAfN\nLWOsb5Jnla4E7LLAJSYlaEZBSjiu95OMTa4Ol93+g8aFjaLRQzNDJJLe+1ix+UXKbutiQlnO/rZp\nvEOj4jPHWferdMNUpTGnfXHYtrIoulLQ3bDa59WBkX8cA23Qc62j3zQ5GQGkHBAM4n0XoN0OOtVP\nzwIFxgbFhZNLNjsb1BmboBknn86KSlAQ7JcmANasWwrA+FlW0ufLlKyBGvOsz+uZS6QzXhr01jYW\ni05S/tINKXtKsggggy7skVZaIdbluusxnHNfqoiz05Uu7rJ8qMrqIIS0XzEAreF1LCRTd6CmsE6v\nsU9IYaCbbjBwbjoAJk39ZGiiftPUis9n3cyWXkA5UMDZLSXuGB0oHoLTkMgZ+OBCl6W2/Qm9/V9T\nH2lF2mCaEJ5cSdHqfzJDl3c6PMsll6+3mnwV1jvpP/3bfuvVDvofWl0vnOVg7SfUCPNTkdwRF5gw\nDaclspmQ1FgiSnxTXwFW9gBULA0uda3qiqY4is7mTk8SB5w1pWB/xQol3Exb/Eksv5EEhb75nKb3\nYWrHQa3+/sN1elynIDs4pbzMJmfGxXq1Ppph388IqF3zHeWgGPp/WHSBbOwECa4O2aN19bVk50BS\nsA/iIPi7TZe2lshSkdj0IkkgX7eRsewlpXh74UJ6r5EqYfu1OLjr7JWVGelRjswXhYOD4SLyW8eE\nXi/3etxPlJ4XA6KDFgTPrbF95gtbzJqA8LIB1cdF83otxKVKbAtiChQ/6EJS+jEoF0XtHgCaQDNU\nPAAUfmF0Xk9OWbYFNlNqSs11AgqW/pQXwRtdG1cdSHpLOD09ejkSk1HmMZ4Wb5YM3AHUJRwmIeP/\nC5RpL+3CRnJkkvDK+9ZgdP4VE1UQVCDxKSOLeKJYm2Z5OyyYAvYxzo9a47ruSlf2b5aILfSaPEmN\nBneOPQdn3r0hAUy6VYF4MgRv0chYtaJSypyCej5ZrC4/wd5jks3nIpF/cpAI4Tv6SUNn20hdEjTa\n/pJeNMSpeO5k2xj0ZOBKp3sJb7vHuOg74pFSivNaIphMPfkdpzR/gzZ+bEus4G5gifoW3P1ZzGtA\nCLfbwthR6Xjb95XC3ZJ1GN6TzI/ec9J9E9/7BJNs6kuzdkHH5hW40f6C15cV0BmbF5n8kOtp/Tyk\nx/Px/VNoUQCqxtgsfeFU7w7jSLA9bjoEu72AKD8woaN9nmuGPtb2NjQvYseIldpwKaS13Ug3aUDP\nQrCvHp1ofUhuzglE8FRK1v41Pl3gORF8MKRNwD6BTHhBw4OZlM63jHog8Wdf7GaTCmKG2TfaDOuf\nBTi9UczTPTPazXDGbTwBFKH6JN6ZV4vWsvR1ghwJfV9VFKyI+EjaOrjvkhGBbhcl31hG6RGpE0kk\ni5i5o/hOeIF88DLxyENSypMN1xT63lKGa1o5jEKVZmMEE+6wwqIupjeR4RbD+q1Kl2jAdrLtsY74\nBw9/71cEdTw5eWxK+Z9qHp4HlFiJ6sih3QVzm1ONoG0WmCxASjV0SY2W0zkjJ0lx+9L8vkbi2Ibc\nuo/c3TJrPfsOQiCQ6KBVQLZq7y8VWNM33HeTjhgalTWT6W2xrQsjwYA7EDRWgwwKxdefwm9TeLGN\n40L125PgVwaNTJM46D8GUvZn1Thk5lFyKAleeDJF+B5pwUu0MEqwaiNitccph83sQfDbDP3aEw5u\nC4w2oRKagjxODAuJjdOGBtf91diLPJuJ3UrHxRVimy1l/B1IyoBTOYrzkeWIDt7qeNvpPtMYmH06\nrJoZo+bt5dCyXFootiCVopHXewZP+jr5sP33KvwtvP9aMbYoXmE0U9KSs7ElKmaUZfCv62jKCc8k\nQ4zzrJ4sKlQ0imbmlcFeHVY7NpJ9ulwdYxMUxjEwmDfbGb2fiRLv3rwNG9aKdW46u4w7HEjZrHMt\njpMr7/3ia1GvDof+JplIublMxgrGI4M5zbbI/YgrhmBPftJgKaVpLl4OcfmkzHw2KwPt0qhy4jN7\nmdbnfLhzaLTED61uWnw4IkBsPcVZxuIoB32ylSbfUsEcsRaJYEwfzbGE1KltwyEp86C1ql2L2/Ru\n+7HTKsAdLHQS6IvljvmNCellZXbabEyV3cm3PRzvZZ5UZ3K7WL8V0jAmw+3PdgAYlvKLiPtRVoRG\nqyCIsfsEMtawaFdurm1c8fPea7IMQqMyyeYRFMf9EUopXN6rbL9em1YNqk3/ZiOPVYacUn5WI3+P\nPreeMgQvbIX2LeOz0K+SfMLJUe1sNMq7EU69J5WmhEyHfs0zJ0ib54zD2hw5cPnuxEQkNDLKY3TF\n7Lo9dcKJ70BwlFh2+L8XwR0yq++7X+6ZwUQwHFBX3sp693MkJ9OTNY6hQUIYcnF7gB9u3fVqve9H\nQ4MzrRV6wcus3iljeGMsOHsadC0aU3rPwJAYhWzQ5A/TBQwL4wXLN+96YLj7W5Z26YDv/DGt3MAB\n2ptWhVD+BBB4GlX/zMYzsr96C4tsb8uT07yyNliQoI2tPx8+L7Q4IyTmxcU55sCD/aEo7Ybk4caq\nPZwp3TlQO1VetojvvynwHaP5taG+Rr4sb223rNMubw7h7dCUPZwwTTIP6/IfW7bXczf1EI68jzSg\nt7vmRIRnH1MRPRlsBRCLotjl8Fhi7q7dyG2E4uI0mfqFbnKOaODxZdel/iilaHS5te5RhWj3fSpu\n7q6Cp2vfuL8UVg2Uet5BPhPyb3y7HBF3uMamK9Bz6bSI8If9QQ5z1dHPr+qmR9P6AFZbstqq0oc9\nHHpzNStSbJLENszvjcrWCo2809T8oYtPpBW/48KupNMrAfStDL/7YrAHYnpBOP7f+zob2sazsJB7\n3KscUtaTsPZzAJyQ83rginWHHft7Rqlj+Bv9K3QTEIYa2c81V9E/gzhCGXkkMIuFv2sVC/4ouTYA\nxPgyb0RrYfO+HYJJ6ZzUimGBhueum94Of3y67FZXXFMlkkU9QMxmIvjqVEd/3P5+lDGCYRkjJJbw\nvfs3oSAjxNlpAlX8T2b1dmjbqKJq0ErAPQMeftID2DPOQyzxBNH4iYl8iIjcQLl8vMuuhIhbJzxV\nRuOXxSQSVqyGUTOGWkxrCav3a/GXM3drfXhv37LJLA5QJD2gexFA2z9wisQGFY5fBGsswm+Eqgew\nKdyaR4GnASwZV6i1+euSgArHXUbgqTW2d2z8RZZZ94fQXGsBAKJLgtysl6v3mTQPgFrKC/0s3N3N\neXMvwoC4yOoYUG5xhQPQzLT7Uw+qUvh/iv0u0ctCGs90lEZ/q2++z0y0lvQ5uM9I9j+Kv43cL0Po\n5gDCBwwrOKawFQeRMCK30BbZcwV4Jsg1GFF/jp/eBRvGqWJJfKyr+Tav2cuaZ1dk2nveXgDaXmcn\nuPQJnP4bLvPiQ2mX8G9SucGVOqitmLCS3gjmZ5g9lCjcdRm0CsmNcekzOOz23ZbLPPNdA6xhc8hf\nYFQaHSlU+ibUEk27ZADv6qltR0H095wVXjS14t8D3owG+dk6YdIiEKDQAJUd2UJ3vIhj+wlJEJ6v\nbNZT/9LaJHweKIe+PhU73wGfz7zL1UIeUGLKXhpIY9DlKZpoz289QSkZtAu6+Z77xSw7rXwo61IJ\n7XapLbUrqc+7znaYNqKpNyi35vJYzZAyK7eW8jKg2goGacBqXJjX2cUF3nq97aSCxKCtNvEQlFsp\n9s+Wsb2DxgCPF9/CopUT5KWpqbsCfKb+XNunAkVqA6b99gonMi2bbE6LUgPUEJ1+sFc7FwEqlg0c\nvrm0W8d9VDptL2355s38mY49GXH8aMeKYoHYqo3nh75BGFcS5aFOc5imIsGqnvJTvBdjfwW68+Uk\nsNHwxTmE4iPdVLdpMLpnzpyRkIHhDLpjMvx20kPfjPxc62t7+GBZt6zAuMhpO46EocVz2xPcw2Ud\ngk/0No9qYS4safBP4qyQBZrwqs6OV/5H/j7a0H2IJzB760/dB7698iVIxtvsz7Rs6rbs6T+DsQy1\nNC2tvYmfrAHXMZ9qqiw57Mqs32ysJNlG/iRHUPQYrUvAoeHx12meYGQD5R+WTtj87HkkLccEqvo6\nvOU7ltba/fn7gHvoJg9dClnKB4d+GVBD1czlBU9JQ+mJQKbo3N44EhafMKlLrAlJAdxXaOV6kf+2\nREra/Qq+440SgBk0y7KzYsz1TD7f0oGYKQcmyLJCZ2ANcdM/m363QVyuEIflYAmD90hKYypcDvCW\n1rA/6Im0NGixkeKIeg864l29Y4ggXiRnvUjj8p0F/847avHF9TUIJ/OZgXayA9VS3XeyazHAODkW\nAgz0W7bRByqC2PwlBsgB6T/SymB0ulE3JJZ+/PLuXXRf1mx/mMEIZu7fO3k7Kt/RytpisOKDF3FG\nu6c1XtOEp+fC0TaoJGYHN7ZdAQx+0Q0MYpO4r3tS1YF+gVAgnikX/ju2uyvCMytjq3LZZWbbZOv5\nHZrhLO8LQDSgYILFMJ0XPhDbP7diX1Q+EzzSvEw9UcFcDLEYPJaFmEOdQSWZUFTmo/lk5+Q4LDyC\nXSfFMrAyLHUlGBWjWSaUY7rCyGQA35hByyD9BKn+Bom0ijfpHMdE7qWOGZGvYnhZu9RKflJOg2ve\nZC/jBq+tdEb78Ar6+AnIBQmyCva1THmh5QVqa/rpc3cmWpUD7Y+MkAqHKLeWCTK6nKsIE6SdqQf6\nEE8Bkji8gfH0cFd1zCJMOJjCQX+aHX5JtOSM3rdXRQ4+dGCgal4WSr6+znJaNe60hTjeM8rNK0ZW\nqA5+LpzSvGQz02LmrbrUChMz8lYCEqWVbKIgPX3NOvWWNNqSzM2hGGXVCI1tMpN4rZKFURpfRiPj\nW8z1/2o5UFlDAoRQgkLGrOtl0sIlT/UMqZufFF8h4JwxwMGfeHPHSZsrlmWdpOX2B4icrdn/v56I\nZjBvbq8AQJCPfphNTVDeHZNlJz5WC51Z6Pq2t+KvF68tIfUhxcs7i2jXAJ2k+W7q7NpAORTMxxMC\ndbuTrhFWrjf9CxRH7WylcnpK+zTHKBh/IZN1jk2HfX3IoC/OB61gIi89/sh1tnOAiMia/8Bt3zpW\nQYKpIkC2gW+jWLMPiW9hau/2nLX4R3f2pU/mSPymbXs/gol1hQwot61I+hj9nvMpidVHB8UKiuE7\n6AajdYmFHuKb6rMF6RE8U9DbK1u8Kf75mmvWi2EwUNiwwQBHdmSymSKGhVamcQCrpC3pwLwABN39\nse5HTNPFeaR1hnWwB9BE+FQTDOW17JtPG+fjKfCijJ27qn51z5OqR7cp0DAoBd8JTP52haYGakDo\nTTQb6w1QlpSkTy0huULwQjJ4tILDmodfGpS3xtZu1ghUZtxo2L/AwPsSMVRAsc01k6D2aavWC7ie\nFHjD26PRJ+yfgWnMZfbzTaDNJvI9jbxVZfDSQRUnTdW4LyoHYtN4ClTp4HeVu4cZE5OzcDTQy8kf\nws87hKSOvNmSeUoe5m4Yx/6cfN35G+HFW/rxi50H+6QpHr6x8yyWIYqEesIklG2b+JgukZLG7ThD\noldpgMqpLFZZgHo8fmppdAKsojFYiDtzTkWMaMAHvBzkFXC5psoEdYc49CXebYbbnRFkIOM7zVPL\nLu28Qp/H+vtptiP96vIDNJRgY39M3F6nFHzXbEW2JMYcd6HwGdX239dSTartrBv+lQdgSF+vHtlD\n9GPa7VjRIUyPCXLB6fSjGFMLYZeFbv0mRHmeRXtibYeZ5lgqiU/zvWzJIOjIQs0Jvon6tDMpTxAt\nyZWqUQjR/Fo8QmD5gHL0e7nsUAIMSW6yDu5SWFH+Ue34TEiz/llkdvpN/8UTgGPQUaCFwLFRZm54\nH2zo7G82V8T0e7IzcJwAKN7AOfFdCaD3ablRSrzoXBTh6U8xI2jCUGTlKXswnJkxDpxuEn4r2ZPK\n4TchUB5njS28dyYZA3YGyOcILCX06zih6ezC3yEjTjIaMrZyEDBwIZ/ML7B//N9HJall8mhNrOUx\nAOAr3ufn9wjpuUQDiD/a3zJcRdhk8ciDA/YpRLpSkOnKCtI/c8BDWrcegkFLugllGKS/QYjPs6LG\nOC5MaYbgJzfc/ENwW/8AIL9F5zSjK+tcd+iaMlFH/4ZG87Oecy014T8czVOtnlxe2wSsBIV/gq1/\nEzT74beZzp3SSIZEOG2ct1QmTnRPYdTZ7XYnWss1yXmLKXFXVcyNgZ+dECUqzU76RXUj4OVpfU9+\nVID2BSfHQ0UAiTB0jJQVyBDaqDeFJDWTeOhBYYxEhT5S9Ys7TZ02nEHhg53ZiBa9GFa8zRUm3+qT\nT5hdQtNJH2SDMfx2aJqwIQ0g0TrWoi3YdgzkFvo4KcgaCucxru8Q/c/ODlbiKHCz7GoZdHFldiJV\nysmdQGWpnyft1uCKQLTw5A/bGd+yYWJwAxcifuqe3jalobyEu4eF63o/JH+04zylt2RN8G5Zdid0\nFOO4/snpEKFSgOOTdbHiF4REZRxi9+vUDM63uBaSwTTdA8+waxuMRmjUKHQi74jixBhpxDqcIvjA\noETXAEi7XqyiHEhC+I06NC2wW2snKqk3EE8q4vFbgCF12TAktdQpYANK3cum81gfUAsTn/pM/css\nuTYbwNedmInOxiSN2ZP0LJl1aa5dIXuMMuA64I12aQLdVgx1w0Wy7lutN0CHULBvHtkSlsiLU9hB\nTbL4kRSxGoO3gR1MxfYwSV2o8lavkYC1eBqyMej9DCxWDF9cJjMwryP51gzEg2mmnjWvPY01W/OL\nysS7LxH3FUWOJ6NlEwphm3WS7SZUe3IuiquDJUeOxxsxOdhUYZUVc747BC6w74ARWSLAPJEUXO0M\ne7qFtt4TR+CfdcmuFVekcphvArJr4ab6lmsmWK86Oie9wbCCNFb9YK28igT6PVpsR8K3cfzgOFoo\nxTJSQv5/8Z+IO5KevOQURQ8onbj4b0bema7MneMIpsYrDnwUo6+MyJvkJJAr1gSg1lLLyNSUVku5\nPgv+WyC75bcLf8M2P8un7tE8uDM5gnk7WqkkcMeD69bfdi/7+NhSv2eE2SV6Jl489W3qcupMh8Nz\nhavJ5vAl7kWX21cm8gErnmebG5nS4QiW8Kz/DksjhySvT3kfzjJ5UxUgckc/IX2/B0a+lOGWsrF+\nWvi5tKTKNXKr+vR/aQrPzBBSCu3KtDnznSgSLXLPU7uG2lPc44E7gSGsXoxCTGm5Dap4kIFnI5mz\nOi/uzvLTNDdigHGjxxxzc9sSJGQlOK/XcwF9nay2f40LkJZzroLNo4Dt6Di199vYDuZwX42Af2bB\nM9Ou6CcUigMkyu3kG38KRW3ke18JldcUir8MZ1DqsoLJx6Hvho2Jr+gi1r8KStbZ3GQSEKydl8j6\n6xY3TdRSWWy+hb715BQftIYcftKL0MSQmLheoxAfOAJrlnRQ049WVcbJ8mkNSUB58ASeZhIerVeh\nKior8Nxra4Ax1qs1qcU1l0CHUrV3XNparTYrnZHLqiL/1QcYtBHZvGTwZaE8ga2gJa+CXyyG8BQ9\n7beOYjvWv5L8lKCaDtCaelj7nrC5K99ot337rcWmqWDPCyHawG9E8qXx+eA3Vp6aJugP14FmXvvu\niPXHhL3Ef3Loi/nHbyaey38ntQLHMQ75L2GWc544PpbT4CTTtGENpyNpZGP4yePB8Gqa8w0WEVSK\nECd39avXCwSx43WVebMBN55WD57kGCDp3BaxbENTwAXBDa3mwebTIU+sAQxyzbuDdr+9ztWyPyto\ns4UR+p1vo0a9LytAP0JB7yKYxV8KpoOEv3u4hrTIPHO7hrBbi5RG/geot/8rfX8tIOQPa56O6Vxp\nNHe3YxJ91Sprm1rdMArF3ccLeL3zwBBo2BgKr+n46L3l9YUMNeVO0X3o1AMtqNiEaN4PoT+be3jL\nv5gBdeOy5HW4N3igzxtFdW1c3iK9mWu3N4/BaTJW+ISMMoceQDaFViu7nlZQ5XKCNM+uL9ka7/n2\nsqGq28FSnUolcSagmA/Bq/X7ATVfGDrAJLy5wo8Wvpp5syJBSFjF8wJF1eRcgJfW43ArgZtCPDVi\n7V1L9mpCMI5KjS72oQi8CDpiSoJnMynXO1nGPZQRtG3mdejkp8k/IdCUmI8Skvgmy04KLL0f+eLX\nk+fzMTzu3QtdwSDPev0DIyD0hJMNh+U9sTQe7ayO621LablhVmyCtKerYK8y46z3MXM7mtG2Wuse\nV0E1/QG5bx5K22HV/UVRR/giox06aVRLXDhdAU27cJRG7ibCPrMn0FMwcaD6bUbtw7jYsDCH6UtV\n1nYSGZbS3v22IhNIO1zezWzC6wn4VO7DuBH4hbxVrL55P5qbyxQy8sV8w/wQIbPd1t4tD9t29E3/\nofXWcv4o9cRP7SgaX3kwND2PGiqOc5htiZqSBB+mMBKsXly713i/ONEJ956zPQ2ZT5jwUKVtP83e\nGgiIXWpBS3px+2JesmEOaXIFFRqZCEadL+lljFUZlMDty9r9vm84i6fSYQgHnX2q6uwra7M8syWe\nt8r8WXHcVRKxjX9vg5GzjgCvy5J4/jY+WdPpBV0RyeeB7bm41i6zppx4W5vynuvuh4n0p5rNn8w5\nR/+UbUZg7wejttgDMT5SvdV60bNAx/ERz4y/GHdtQflHP6FYWGVvu+P7WNC6Jfr/P63PLfwl5XeN\nvj6fU9BXWcIEhgyzzscIdeXnpH4vH1o9omt6aWTqeQhN38WVgB4YITbzePfJFXADQJrrgVFShM/0\ne8BMKXyMhtQTlOFXb/7CelpuwqclO/CkASePKVKfnXer4lPn1kekM5K92Ko3uwCHnk8gvEtFq7by\nuXP8jsygXZIHBBStAuTQTImMUiAX/sAB8JR2bkXLZcyLiN7qmk5Aen2NHVo3tXM6nc4+VAkyiXxc\nFpEl8OMHuGuKVVJpbn1UJOg5orffAlYSHlC2VB7fLTbe7DiJLLAH5at9B+s7WSb7CyjKmA4Oc3vQ\nS43K4b5Ngnwe0+V/A7PMb09eVuhu4PR6o+3GUqUJ1SWWRWie7atagQ82cuDUm1/SrlUmHEQSy1vD\ntQ6/xD62IcXNBo3VqaUwVn6cbfHRqiB0wmrWvZckaaeC8elN0ypMbC1zR7a64lbWAztMfW/oCcye\niOEtDxcpmjL6pm9Id9H0+6iYDym7DHUyT2xIpNIHgmomQvjM2dGRSMfxDsqq06qG7FLNylNQXKlc\niMDti46+XJKMjHPfTrfYxklZnp+WUzrwMSMb2baTklkdznJgKSTXeMKhnMXJIXsOwyXfBUPdLIeV\nhJ+0/8gAmndDrik6k5XAVkx9cqGTVJ2YlzowvJ5yDNcjX1Iopv9D267zQgELuBWP/Uj6BSFSHtZ5\n5k/W+ghXJ14ZHjYrDl5lwAzKk5cyr8LUoVBzwkgAf73nOEzwSd2g2ozgO2cQlecNtZddVEM4eSiS\na5sPCwmgf0tr2I7e76Zhgi+nGgUHhCxQhfBlyoFNQMmSdsdYuhmtRul+qIhHLDnNgyPngAkirXfA\ndvDJ9p5fS65sgQy0haodPGPndjagoHLfhcMsAzECfn8iudILnzZLSt3x0UVhOPlS45ES9HNg9qA3\nztMPtnMH4Oe9tb2bQq0bn2gGCKnOJCt6GU7Ub2/HNBnGbDEKHRwJYN6aZmzCNh2jPWphOM68LVa5\nVe0sDuPL0kzTExzRY2Ng35+kAS8xPobTh6wkueUGcZtzDbBzaVY7a6cQBOFY8ZUBRtV0YHokNPu7\n62xmy0zTjg7TqYkOnI1eMuElCn3Okl1u/jvceaP455wZ83LUOrqvhp0k5S0YxDaUhdG0NbBxi0E2\nlNSbYOccH5dh6aE3PlnQmd2j3CPRWWr0HMaa5Tz7LXJSHCa3WNsgkyHn9Mg4MNFtFi2JSr5kI3F+\nOspZZDEx64AQiJ6hVtfcYjW7qhMRI1OAsvBqXzPLW54VodW5ROJPXGp1Xui4q9oYSPQgyqfGB8uF\nxsWzQi0YQcJQXqUYs8WRGusIlpqKkDDA3hJ78j5LXjO+lODYEVT+Km5WGS0E/WIQ/6h9Ww9Rl2ez\n5WJp1WQfu7/yDuB4EaabgbmCE4cvCiLM+vL78JHw3857ofyS25rhcgGMfnjy57DIPdYQZKE7Dv0y\nVE6xXSskWwn30d4DHqzJGFcbzBY8XrLWzAUn0pJISH/NUpEt1fpcTF4Q6hrYMZZxAgO4EFMYK2fv\nujNHVr7qv7sSHLPPDG3zC0hjom1tWehg9uMEmxTI6l5zYSxO0fkmGUhXCN8yOhS3nbebILR6lKQY\n8UEKkjac7/NBRSxpCsAc4rsStYKqTdSkxh9zNZEypfA4TlVuWUWtFAs1vErajehGRKvuqa/TDWHu\nIX6PMLko7iDI4vrP39zJJ3RZkzqoWMD9AfA63bGqyKJtZMWrGz8m5Z0HM/5v8QoblUG53EKzGBA6\nMFSpfGbEel5wwGkQt5EVpN6WE77sQoV9GRPmxgo8ncmwEybgF+GZH6NdNDEny2+zwUKOhpFHDk9m\n7OdIx7XPmtpIOQp0sthz4v0YqtHGndLNFIR0CXcQUvU6qY4LIseFJx9jGIw7iLSydHA6i+xd/DY+\nW2RYxmaS+7A/rJw4V9avpKjaqjHY4XYnpO7TdAR6GZ1rpctKq+a/fDbMLdT5hxbJKiVyae3zakP7\npZjk42gllsGv4iKzIA9nGAXDU/vy1A/yTPPHSlMXYlvwZ01gjUGHu5IBjIACYAZWdH8d7G/FGebh\n3ClCDysC9wEejRlulBonzmpk+ye9TqE4LW150x2CZSxiowL38U9fopGjf1tVOVyOnYiwzLE/l2pW\nhQ1LbVOdrmpXyZZTPqjjZ8/JmjPzjVQC5E9G+Pj6dehBQclLe2V/OyP1QuvE3WmQioh/xcLJxUjw\n8YnZDPw7By2/rXh9ppTzAzCUM1Vm6Kb6evdRPv1TcN4vSdgIYjvVPjkcxwzjtS18n0YEKSo3uW7U\nGAXhMXOTscj803tQDOdNYTm+FsY0/yml616+L7OnC2988RjBkOsQzmeWU/wslcqzM1mR87a6zZaN\nArmZXQ8HBNP1h1q/mX91UDd2rfUTyNGo3A62upnsyMMbkypq2SnQ79peg5Xq2N6OvuNlFpzPqH/P\nfcYgAmj8seHVCPS7A5xkBC2OfJ+9X6jT49qh3OvSYVPaCp56M/g5Gv2KU9DlMQWXiHJM4XNHd3CH\nAs8XwxuiuweiB/y/Me71mZzaJo548PDdYkk4s0EYD5cCRzqL24r632SxeaFyPUBUIVGqi4CLmZlb\noE272LQJo9LK6POQPgLCDIYARJpMMFmo5w3hGtSiUYhGqq37B1u4S9VSkIbQ9EBZMe9MrkSkCjmh\nA7cMouY2JOjADc3UXFata2aPTzabYVJ8trTsvit6oUTDoGn1jVM/JdyxTir4xR/XqRE6uNWf9P3a\n8FJ1xLNABE+aNqeylAe6SizhxPGv9ynFK3xHwVTaogAuvqzkMsaXjwc7CaorQvl1RBYWyvW4TMzo\nlJF8d82pI2WzWHI3ehMu+gx/gY/AtkczIFXeVWpbGbwlVIBOUZ+nLZavK/zNVmcPx6lAfDV4lI58\njm59JnUxY09xOrT0ycI0WJWHZ6gJEkxIgiPFg1ij8Do3GOMiTLdgI4TM/LItLW147g+fBNrj+6Zv\n7vp7U7H4LE1DkUvEqiZkAEzt0BN+PosDJVvHp6ZQ4g0sUD2o8ww+FPOc+yXuDaHO7Kw557II/eR2\ns1t1ZeOJGGd0H1DAt9hCkNreDsXHbZ5gH4AWcUHSXNqwpO+B7HnJApxKDIeOQ6+ajk2BrLT5ysd+\nohvSYHKwxPwwv/QFMeRMx6vPKWtcFpPfRsvJvIqUqUy6Hm/ezhb4y3lKM2ILS0Q5SlxME0YilABo\nib84h9fHMK9F7rQor2xNfw0xVm+fzLl/adF6IoT77zJgbufnY50mVb/Imd70OgphJzYleZPvIPO7\nccXdS6y7VjO4b05sPT0l6JAsMapQRYFKzeeoBRVsxTShxhVDWUh5Lx9c4/pqhXLDs9FTXdv1vSnV\nOIsXTNfOqXuMxR0GBdYIUCHMcy+Zr4XFqogqrAT4Mg3TwBWYX7Ry+k+yftYlEWZW9aL4+I/mEiEO\n327Awcshr0LgyY94Ej8IyB+AP2hyzPeNNHrDoqR7i9398TeVPaqSAPL5xoD62LzBp4hgeQJb63nq\n7Yk6y0EshEhMTdtUfjY4C62xz1kEAhVVY8bYo73r9CbOH/OqDARGXUKP9ujH8UZnIelIYmX16DlZ\n1gypUsq8gN8o68nFMqda5aRzTNlI93cgE2nhFuoTtvlxkdW79cUo0mtzTp0HH90bVwfgnvRb4tsy\nPU986mwKAP2RlxSqL8x28IvEY0ztkpw+EtOknOCzq1G8QYRYfm6D803abMsZBFjbYohfjcUlpuj2\nVGp54rlcUuaA4391sEOVFt+vsJfBlc7aNpnr682runSUKEFzRB0s8z43GsQKD3GVjbsPyiLcb6vA\nyL8SZEyOxBBQq9Jd3XONHYIQwGx2rGj5OuCidx8fiVvzvYKnUGKGXuBT1fw5cEzJiANqunCeDrHj\nYIDn1x/yWz4xnGBaix6CkwOQeHQE8/Uwl2t1HIzIWIEBdufHmL96od5+RcirQw4soTAlug02iCfJ\nxuDPuhDZtr0NodO2P444mLB32tzZIL7oyHwYNyD9oTy69NpnVchGzuNfqOUpmAAUlsLr1huijQ0E\nfuTJDPUQtYrEj622KN3Q6k4yV5N7Q1HUkUy7fwbaTI5FZe0tEDLy3Lorhbi0ZbKPVmB/iuqwGOZV\nWtrwbslwPZqNqBFyITk4X6a7BJKL9LcHEx0lo5BnI8z+ACjx1p8RrJS/M6rOGQsdR7pgWhaD+TSr\nzlfPKpKE7zHZYny5DgtFMoY9yHumTGC40wPXzxmzuN9VN5ke0gfb87ZAW3NUlN7e0vsCih0FmTDw\n4P3Uo3WHY4aMNM9kU0T/tdH9dGNbg0yx54EXB6s7lwGR7hX3sSYnIMCIJ2AOXnk8QJ1T/l8cfuNY\n8BadjNe5F+a277uvq4AZ9Afkluut30ybyWOBcFyfkpCLS/dfhSbWhutuxAEoNlCxc+h8SerWvB5/\nEowtgSoGZMEd3Bmu9yFJIh0tCMJc0TCpGmuKDPvMdRb52ZwX0mqD/sfxclLRIPs0eczywyf7i+7e\nKvNp7JPQ3A7vbZtZyN3a0YpmrCjvohQDwVbJhY58y4wxsLiB6/cbbGbXcNh+Z+ljEjKBa5kK+Duy\nuMTIuyvh2LafHK1II6E3hhjg5UE5UMlC/JeWnO6kBOzOtjYYZhE9ctCTnwjkAliEwec7H7+4V7nm\nEqKJWR+BiYGmD05ffO7LY/KlfDFqYcNSS7MgifksJbvDeDJxkt8nJBz5xnBJN5WSF4sejnNxjClU\ntrAc0wUbl20HOhhp5doedFRIDoy0ER4CIgFb1urnUzOzaYV+GStcUuK686x37hhgoPvWm7FdGSiK\nKUdrXWoAb/wm5TRCPwHGKuy6iL62yxYmDGuL+0P189D329palSSrdFz9v4Cc5dfsmAgJwPD0SVod\n6PCEOoPxFic4xQBcFpPYP5kU27imCLz1Q3Y53lyuQllXh+IqfycOEDaFj3mJzoKpmGCpfsmEqmEO\nDIZ/Oqv1R7R47e5CLE4RTzZpPFY0KuEHZ7XsTfQSat/f+X63mstgH+xpaY6ibYIHnQryak4IAX8Q\noOokS4742HLyVnw/Miau54/yzU83dG039wTaCbrkdD4xoz/YVjIPbUs9bw1VPs7PbAsayitHGVCm\n7JvsczkB/J5vnfnwC+U6iEcnClc/kqRq1hxwmSLU+fQ0m/Pg3zkuoxB1/tWZzFkGvAIrC/TQL490\nDNaDFt4iw9a1fPGHdqoYssTNTGMKFPtlFDqdNfwirqQiS+wgt+gLdOpe9jQ/w1zsjW5HFDS8u1cM\nTbXnGu5jixIl/51EE3b0Wr8TU8DnxKQaueY7NNApJTLZUW71/UcGdNMzIzopTCVk8DrPqVQTT8Gc\nepORTgb1c0oQHbE7HmijW/VcKMQ2fBWqk1Q4YiJYcLjQ5krwxEy8l5OKfhfyPO9l4y+P0rt0KDks\nC4CB39pSkSrvKom0uX12SQ8OsOT2d9RVOHOZMydhy+qDx3x2HeOW8qD4Ob+04bZRw0mu67nFneFk\nVPvitVMXFKm6u8+YmDKeIxefY4SQ6zMcaT1cyxSaGjBjLlvJUz/0Qbfd+jZ7U+CsSpZeBujujXaU\njSZv0ZiY+zyMZ9eiPBxeMZgsAVqxK29upNMd54FHmUMeeU1RC4ro+HALQNRFCKnXAgpynkrTVpvq\nNALYeCCrtEcIxCd7sJxk2Y4yuChNrY4gQ0zouAZ1ICr//wkhDH/HGrtq0fEQhn1gE8uHxIT92mJe\nS/7HmcNnU5r361sVcmIZSzRZYaqcoiSBNFoXnE3enYC/K3CnxJwktK1Cg9IZ2oYwcAxbY0XkJWuK\nxDrL5UHuxEdRIYw00OmhmfSXNqkscNozdtXc856aHLTg182Snj3B7ZCiGPNjbABDcJkElYTtzaXs\nUSGDZDDwYRERtGh99lHuVbiL1CtbCXSn99yQMpsCNtukocOJUlSeXDfFp9U2IfU5U6ezlQNSCbHr\nMzW8UenVrSubf0swq9LeIN/e/cl89fIAXwKB5EFpYCn5yxYWF6kwJfYcgfu498D/ShiB7ZSCPnqy\nOe6RBVvgC9LTOAmEKg1BPKdasprgxWUv9g3tTyPPDvjGtizhBOuk8W/7qHuKNpFceY/T00UKi289\nEsa5PTWTheZCFLBEGKH+zTcAVE32f4cKRuBOjZioycqnLmcZX3sSvFIBF9bfBmqGcSx6Zp+Aa+QH\nV5d1cbwc2oUTpLYb2+stoFMTecjzZw3Gud5dp3KvVpggsXGQTyMQep2C2wRYqgPSEZazwxoD2Npy\n0MQKkWbE8KvEV1z9adQth7ytAcOFtzTP4nBZmytXZESxKfEf89YCRXZygqLKguBaCxin8w+EhO4o\nn850vI+v3FAZEHpdektIzOgCLp09p/m5Cxh1YldVk1PiN5s/Hu+dWe2Kaj53dZWnG+dz20WDFxky\niiBpk1zbj6gW6Fi3Bdl9fF4Hi/q55Fnxg3c6X5EYXcPQkThvYBwdBgY24DddA1K9ks/UycPE3JMQ\nfZGjS0i6IHoHqjA316+tOw0dGl4HaP0danxALwEGy0nt/5hRl4uzUjo2zWhoQ62PGpMfuQvUFrnz\nC0N8vRP4ShRsfQC24rWcGCsi7NaFMFD4iGUm172l7uFMXneuS3iVmVjVFd/Z0rb2FGqFsArIhmmZ\nVdrm5aRymkLMCrlljVNf3f05ccrS7gAmHINzt/TP+o2zpiMfS8O6+adpdzhLaDCFHqz8Zqn4Q3Ul\nuoBLLps0/tcITGxOeDwn4uXT9Lu24NI/tOuUZw97lq0LE2Wl//OS4zhMcMkHu601U2vFvGRFX0e4\nCt2LO/zZEf3sDo6l8K9yGt2eLHdSJS/IF1YapY5bxJT/lTZ1pE+IOVyWIV4Q7Dnk3UWmwULkkFcj\nrKYoX4y/wzlVPG7f4RUt0oRsxEsqh9IvAfSK6fuIGrwijviZNiK4+gDiIJhc5ANKY3zBxmqy70qK\nbVbGwptQkgYRr0+2cxxJQr3OQrx5r0bqUsx1o8/79hU8rGwV7+zbR1T9jadJ8x2Khiuja5Vrb807\n3BqZHzLnx5arXm0lSzH0ir4+8D2ed/ikSTARPEpaOQnEmFHtqZG7erYRdoml9hNse7FCojvHSrb2\nDDrkdccCC/0t0Ner7YJhl7rCHlDXor3PHHMP/Kba3nQphD2t6lpvFqHSISM2a5aplGPnV4Mq9abn\nTMRMtsk5mk2SfgJurJhbCK59IL1RPMxH0iPER0fJuf3Z0O9DvKkHiGdcf5lFk9MpFI0JA/53RY4h\nS6XvuP/TLC+u/RDTar6sOXkGqW3L1RyK/vVRZjwBrGwycP5xCh8VTDu4ldwt/OtDihWWfoa0Gz6A\n9VdEGNmNaeo2iB2SXWyTihr7xhQFli5vE6IaeX7Nlw33fgYJtLj3waKnEzRvZdb7rn6RSf8ZJ2ZQ\nVyzKCqOFIkUiOaw2I7Hh6yppz5W12Vn8B+o4rzfYNDF1rKdUmKfk95qjIUQc7MxB9dwwf5Udyaou\ntox0fYSp/k1Vncz2J90mxDg+NNpUZc0PS0xfMvuxZW+6+jjBhMymX6nVwYIzeCluvBn8yfpiD5A0\nVYTJ4UVDf0JhUYDD+Bp++6eXPUvkoVXiUfOHstKiedmJ+5fK7mGQxj2LvicwdOrGjx5FaDTGGPtD\n88X4LXmr/hVbpdDV7PdoIx763sYo66idhU700oM+Bg3zrH11WIE2rjN6KITghtll8X9OGgAWNWu1\nwhDITfiBQLFnulRcAcfJDj4qkO08xB8iGOB9uGIZ35Z4NO+SudVAkWSwQ7FWToiEEAbfqMznPLLb\nBMIoGht6Pi6+2oOHRWpmWDYSmyXsOab7GZ8GjTl+Mm4IFqQ1WVrYOrVYZAUvu0j1oBQTlUjmbR4Q\nkb7NfGh03oJbasIHWL/2vNM+ke9IfBfYlrRU3fuU9jqiFsyOn/GHufFm/e/e5YnQ/JvAWKQMwgQu\n220bbEs/MN6oVMw3ZCFacctZHodhYogtRJCZtqnVVRdkviy7gMVgRAWPyrcb1gCCbD4hK2wpMyU2\n/o10GG8EDN8+Zh6Mbq3hvays+Xpan8pZXL2qy8EQkF+M407omfN7pMz10ADTEE/VClIwoFHEa42b\nlc+pZ7UJyJqR4cULHP3SKCRFJnvyMrZqIaAEKyoUm+udtxXr1OYidNW/Qi9fmCRUgEdN1EwDv+og\nOkULo2JctWIAbzDy/JEqYdR7u7SR7vduUwpgvicuVhimBv/elgbcqj1zKUUPtQAskjNdSxpIusRj\nJjs6zXIO/tdrZHBE4BRFyta8avV23EHlQLNYwXonF4bgrrxjzSLqKHAjudvaCK+KU8aCS3b0+s7O\nyvd18vKEL4GtlpQA+h+qW5s98/S80AFm8rPowYB699yu+PPSWlcx6pXEYfWNPB8cGWn9TrVxjYmC\n2rWd/1UwSyqDMPs1xk8uwxQe0Dg+DstGllIkZj2F93CXS682lwOrXmvQ3krhANxmREBrVhws2ILc\n+LbJ8J7MF3rupMpIkMxqJWQw5fJeg4TrWrGKXf7BFwHzNLG5Q+ozffWSe9RGZjt5hJscSF6VlOAi\ntGB2OW0Q6BPUPJv8ZNc3b0qk22/RbCZr0ajhb0VcbxTM8CaH/4BoeUe4OnGf7bXkJrSoyzTFx+6Z\ntmhgaTO0oZwxnCktVPjxgtsfHCTdsqj7XP0gwiM/E12WG9YdzYRcMn5oR7jMX6jiZ/iUGATJXsLh\nzZOCikq503pGHFd0PUt/TDWF4syB1BwC6eaxtdswbvE+6iEz3/3acG+8WI4yr3/LdILviEyBOYn9\n0kLCeule5QNLoa+uU1IRiPEY1wCKQaOIt1hrW38W6VEFX1qm+Dp0J5rdgS4ew/qvCteZ3LEeQaNV\nDJcHJqPY+kgbIBgZYt32ZuYcPqlREUjivcARgEeQdyCMQ6oqsJo2tjybwSQXixIUH7L+5HiZtmFg\nOR/CLTKZz6lzmJ0xf5ZEDCE/Jiktz1W/Jl1QxEOCH5gotoexvXtaR04yJZcyZaQXbJjBlpbvnHVR\nFrNW/1KUjf8At8EK/RePbfqmeSreQ4YgFKXzU2kDkOQMWYHJaU5eYf9pw6r9XYgpk5TY6RRVU4VK\niEUj9K8wDCR4XW5g/dvywGCMvXmAp+u4X0q+/GQ0ws+HrmEDTlRI09XTD0BhXu0g6p4qRDH7J/Jq\nQH/5tq3cfeojxzELMNFn9u4I1RCoG+df4WgIz5IikNLtmnDIVFH60Oc2s6KljRMrFDt6TayIi3yq\n8bUmbBSPQcTiuePysmVsBqh987OGo+uJiMfIMLH0iQ7Yft6bZYlsF1JvMwSv39rsIkoKxBxdpWLT\nstoW7iSaisKXz4aQydd2eAD72Nyo4H/w+pjLEo72kNkyH0Uid/voKznNOyqJ//3p6Ew7loq4rWxT\nP0ct5+8nWDkpsIW/y9uQWIPsbdwfMOhyKZWSZHXs0IsrzKlT7GHLt3FapodvsVegDVeC3o2DBt14\n+NSlvO2sEtgnbQqopVULzdLOoGrQqW8rf3eyjgGUrhSHvZ3RfAIWwE5H342Vyn2tuzyv23V9AuD7\nsFDlalHrUhtV5uVCAaH4E3zYbKTicN9nnEc6hPuc8yAd+WYGSnbU91PvMAHFeKZ02LKYSmnsrcr/\nbwPMx7PNdQP3w2HEQVvgXIJq2E4ahXwHLWDf2NTp3zZSSHPCjW0jUcxBtXjkSOUj3KtiD4kYwVWf\nb26AwcVqrr1nzKweR1nmhezuJ51AjDw4rrbo+NmnVbCT29xjP/b0o2cHXitgrLYUzhWWWivx9fcL\nOzz4nkceJxRVdznI32mo1rhaCJM58+VjAVhOMDJ8nJ2s91gGInNbVcT05SKdA83uC/8QJqIgx+HC\nbHnHdyzj/jSass7eKSJH4HrMdREzkfwvf2X8iesbrNwGikLQN+WGrh4uy+lsHE5CPAt+2gdYUa7O\nzUT65QP7GCPh4hCbYXb0MTOGYXc8UC3YRgXvNUlC7LZP3MssdMNcOHPohmUGuxXc1FnChT/ecml9\nUjLAba4BGmj7X9gtX31p3Mm6lJs22KUc9kKXNjL6qWmxcx++13PBHGMB8yRZB1lhO9g9rQRnKeWp\nSYagDZT06w38R9ZqsBM4uBPk4PzVIAeOaijEEFCEA65xGRmFyK6qvySEJrOzC0jxmtYlBui0/1An\nBPRLAXXg6wx8A6diJgwtUVmUe8dhmJx9euxpo+P9MY+sd/CK9Zi5/vr7FSCQY+VCrsSsVlANQNNx\nwsxZtYgMcc2jYSBrO+Amru/Jm9cjNPO30WAaIoD7Q7EmkPGoDdQicQijo/lQM4F2bHCqW0kXpoJo\nOJSeazIqpeMibI/B3CYGbwKkZn6klymPfcM2X4koxAa6HTppn7ENQceYaMz9obAVR2Xppo9NQCVv\nd9+xagNtvn3o73+FF+sLTx2NRZUCygTYYWVQMeHRprz55kxaH0WcgWSPuZYm288ZgVpx1hwKNd7L\nHIwZ3L7zDglXc097tQwjcRn2iwwKFKGOLgqIgLiIJG5VTEPW7s+E6do3Pud44/rDmmAAlqyMQGY3\nz8DTFLoTyxlRJgp3v7VExzi24dYB1Y59sVFuacUeKwTiaoaSABt48SQTpkNwTQuqu6awwCv1O6ex\n9yR2eDsd0qacv8DNyrDeeTZGSN8OHwjw8xQvV8QUV7UfqE9bN8F7ggdIDyH8K1SWq2B3VK1YbID1\nmuyVCzTroctNDA31ipA6QSpL0uOuWR7Z68SRllEhF2pMUnrRKgLn04NIUXLjMiK8AcoOz4EGKsHI\nvYlGy2/L7lHpZK9YFIXMTs0EJiC24okwghV7mOI7RMDoP23yMt8aH1XrFqFh5MqN7kuwQv4H3tYE\nW/y/uV9rHaYYYKs58ZorU3xoi12k3vUv6/PF17X97+s5mG9GTvTADBrupbTENHE4pjPn7ZsDU2rf\nivx8BT5TYGOYX72P+ejvE8x3UBjUOhEZixKVFVfFvr/Ea21TMFHwDlNHh+E3UQT8ubcOJL33iCuE\n9rKdAst8kDkcAszlOv80A5u0O1q8pSNGvB0TCFFHuLmEr7qXG3z8LcGs9mXA/ONGT2qPOiE1Ke3Q\nee1ymVx+/0i3S8R4CTtyMBfyenkdQB885KC+CNVShmou27I8/izFMbEVo581dN8ISaM/ij0sBQBC\nPtPeoZK3OOP6jpiNujjPGu4Hs5H/Zi86CGziyn16UKUHewoFq+oSR+KoAjusYsZR4hzT5IfImr8+\nDpk9soJS8MQb6VBtodr0NO4JvadwsiH+rpqUIhIUwRTGLlISXE4e/6CNV+UbS9N9EHDh5iQNAamy\nWk5xmS6d4V8PgFJjYM76KhV19DkVCYPvTQlU0Iid8qPQKchOA/MCy9nG1K0k/nrXMLFzWawRbEov\noUkvd4McRxkLidkIuCCMvV6hiwmDzmO/jhhE8VSNqhVBb4HA1NSjXbd94yFnLDyzlxFCmmyYVwn6\ntwSCfWhdU1J/IVU/ffRhLXlP75hpeUXcQISyKzqFzvIGo99ACLlvAEEsjeD6QJDMBoKxc68zVJQw\nSuEvnETVRL/GizwvQ58ALQMWMZYPSBLlty2aoUOV/JvhyKtbLxX3L2auwMadPhHM7uJ7P+4hHw7H\nGVCtUouDNBk94cXpKdIaqcLO1Tn0maaK87MBxNpZtkXBfdv2p+57UYNdNv/7edWG7Jijadt2eJpg\nPUSiqoi/eCiye9klNdO3IIqb4RKpUmcMu900wzzDnJgBDJ+rro8V99R7zBioNnp4M9H9lKe1EzEE\n+o9qqqoWaBcl+/LsOaMcMPGnMaEtvW09Wo/CvFQzfy+Qi0aFaIMdpiVmKCYJqqpiwlmG7b6noXJm\nkiDvUFAC11GZJZHjOvw/w3wLXN/XkcFZDBQwual9ISTWWLG9l6CO5Xs1tqXzU2WVd9AysP0AJLlj\noEMIvoIuJwuV3hABAmVmArjEc6B2eVzX9Ox+jZuMXOoEMZzJSfT/UlZAxrtCuzC7ATe4H8d18x6U\nBC5Jn/BtnPQzoHPJtw52Wjy2WBn45A8z+0adKKboiEj6r1ZWXz06limDQMotKMocGd+EBmzDUqS5\nZTzElSy6/AXJQ6jvkN7M2iXQwnqi2Ip3RHT4rzWpG5fgt1Rqb3fzwEVBeMowfYbyQGcE6In747iq\nv+b71NMVTeZpmQk3MgKUx0aX/z/oW5UsnDTEx+FJBeNDBEoJhRGuV9b6Ijc2hoBt76RaRhZ4s7r7\nn47w5ftitDZ9t7uSzs2zntxQtIr5cQ6iYbm2gvENRa05EkFogTp5RMFM3quisuszn2ndY7F1L0z8\nnV3uyBePZpQImdFSuJkXmVVA0BIcDmo1JGZDnu2IvHoN5rqBz3qiX02zX9iaiIwErHvTkSm8wAab\n1YKgW+rgVqQFGNj8sbmEmbsDL1+pbWZxUq62vWvkgpkbYSzYLE+dZRHpCTa+vGhafa9zuxUmiBPo\ns7Q1BVG3eVYH7D5pUGVLDSX44CrFsGknp9Q843of+kjfZFhHIbOS5owsV3Y0RH4+zTpL2koZfjy2\nWqlhbc/KqL0Lc9RYZFPKXcknQGVq7Sh9MHWvGl4gCikRIxKS/yEf4mhCIByqswwspEHbqKik0COP\nYPKDjjJVo/efiLnpqZBbgjdwZkUlB/QXFrzU74bsr225vrHavPMTcpKFiZKhencxanCyKmEog4Dh\nBywIP0q7pK3OZEQP/eDppFJ0BnEXY40VTlwinGgeVjNcOeFAD8fc6VnW2Cxe4Qa29b7ceYamkiQP\nIrY2H5QoLgnENbjLDVsdovxnzFPiJdwktsvsCWTAtCllcHr5CplniA6o9ZvNqW+PZvO2/PTiNTDM\n9T1Rh/pb9ZP6QpugJ+K/26WuEevreG1Rq4EywsdUSKsrKv+N0S18kGSiR5AEavRnI294TQG/xzWs\nENIYP2J8SNtUyUz5t75un1erMfm6DguvZBqRVaegwkMB5zpajM7js1xWUeWp9LBdbSra5Rda75lX\nj0cBeEN5ss9A9UAyyPcRXXEbfA2yd5GOT/wJEOJY4gahGdqkZ2KdEHyOp9qdfLzPgbaxBkKMwbY2\nBwDF9vC1loqpLAJ/H4qiforIDAgk5EKFC3tp7PWWIwmq8qlyCdq1fXPlW1arlUDfZvJkMADPebNu\npRDK9AFNjyv9dWZ8ZPjv2dYKSJFI08eQurZz8Dh11Vg30Ziouc+KXGA4RPo1BAN123AfGsL7AIN7\nD+C0X6akbWD/WFg7GNZpEVuynnNJCtbQ2FBiGKbqd37eV1Zgd6y+SWRv7szleAldnLAnN4Uw/v21\nP4pSqJcInYtGJYw6S7FzcnX7FgR+QkfWyrk4uci8mtdCIeVR+XVgnoyATbPr8pbqw2KVNJAwOJOH\ndfSiWlfzZrNfOvVg9VU6FMTgAT/ezYXpHEwkE0aQddspPbRjq926xDWZu+1dparI0BJ283cLNvIj\noTPDHYMW9FLed1wzN8yt2wucwNknVl2Vyqd+Kpqvmm7xrG68e24+A0LJ0i0ehZ8DZ0F07bCm42mD\nKJobOIo5jnZT3N+/U6CMOTe9/MNt88OmvEPkiLJ2H762y+ZwPYjbLcRnuO2QeXGqanRAqx0FND1i\nj9d9W2o9ORk15FuqNiPiJMiWsi1DOLAzYp9LeHOLWIo//SYTb+RFIMEOYorkImiPUKyH2+o7NadA\nC6QXjhB3skg7MxHeMyW9oIRE8kP80p2dSFL8CfAEiR2DJ9ysmjqITXIhoiiBAUALtLYGYujjnm4R\nLGbNjrCcN50/CoDJYGS2NxIjLK78l7EY2JwAK5WMDz6bUA4nADoG+IacPOcVmCBvJVluA2DU72VZ\nWVcRbDmnyZZSBrGo7rtSEwlTIh35zZhR0d2Zky+514B3h/MVRgs3isWSoi1xkMnheZ6vQtQ5G8I1\ngh2aRpK5BHOBQN7fv0QoL5V0c67DRVEj3cX92nze6rbDTCcAl3H78giUwV3MaJOOgRcYg8qMcx51\nS5Cn1SZAfoBeKhDxL2P80ODdo9EKshlgxs3bQwBpJtOeR/9Auk/+5WOpWQ6lfC1qVQ9u3JBBC0Gd\ndFucZXEDP42+cApIdU4/FmyruowB42oD/PKtayFbcYAdJexZ6kB2I6IdNm85tRzPUCyQY/SJGz6G\nxTP/B1d3R6Y19RP1s2q9muU1jBf4GGFFhvkazOrwmtqh1qG5KKR4fMzKXe8BA6jyLfCQEKkm0xNa\nemYtaE23/eRK97Ucl2oHS3YzBYjbLmbm2LeLGv6nkk4YYVt+bxjCutqZMpTF1DWdv0vnGJwpoMU+\nVuLOksSarzQa8HRy8cobtjIjwEkCbd3AF5Mkr0ifWI5RbPG//Jg3RKFF4Y68w13Gp2VnOMqJw8Jg\n8XI/UmW22pUhmVtdgk0NHz25Eti1P16y9eTvdMmJjKqB+fFod8yyWIuF/jWNem65f2cR4Q0aY8o1\nmxfcRAzrE0c1LMcGQqCJsnp2OdgQUdEdJHCzk1rMo439pBQn9CdF/POaOiNpXJNr6YplU5L750zw\n52xyPAQ44KUEKJTB9Eumbhv7g8FdDLQUlNb7I+B2KK4ZDZoBbCEnCh5ZjS56LzlvY0/5gwd+mw6G\ntzPY4sq4tVGGDHQvSjBLPrx76WnklqBLS3P3CrumAl65s0/vPg/wQs+bQ6VrujHWq6KNs8F6NhFn\n+mEEa/67XanK1fUhtd76ZMkAStVVYc6JZ+eJDbgSwQGReM6JXy1FE26VIyccZRRr03/C7wvjYHoy\nM+YHaSKkj0OUXeoZFWuPtKFcBxOABor7NtFYqrjC0RNir9EzMA3ivJJfYQNKFo+1mlR7EmXd9PXy\nQ4hxHKA6FDDNvm9h3xoemrxgW7z5K1BQlhBoQl4IIcNws+HF0JI2Y02oNIx0ClBcV7Y4dH8GmOOk\nX8YEmQ7BrufIi+bFzmlKnKP2pz6ggzQKdi/2Vjjj9mVuMQ8w5MxRIdDVAWHmIz79I4jgyw+t455X\n+VDKcKgi7DNl6ez7P+jRefMpNyCa8Kx2SCJhbe2QEzM2n5Us3mO+kLVk28ZmxqBosesDQ4QekVSi\nFQpALrrK4MsPMPiW9jBS7O+/4sCsyixIhu70zsV/l6lVo0D72c00Aie663UfU3K0SpMCDNUfPaqv\nevL0COxopefuGDbV7C0AKEapp1WIDe4rbGhEG7U+1KqNfsSpPwXGeQY85u7fjN2MqaZBiBL/HW59\n29yEd5tlXLO3EYYqDvacLDJ6YshZgiSnHcS7neeRndPtvF/2P/AVz5U4hLBVXXRtCIpAwitu26Ag\njOz3oL3eyJZ24CHpF4vtp4oC5ctUzBnmUhfHmChjVkhCLPQiNL/+SzduPkRUvRmuwm5aw+IDWNd0\nthRWa+hEsJeGGDuChuK8T3QACCd8XBq1OEFEqVXkq/1rAF2NOfhq9Tctftju/3TQecLAuvdlBHJ8\nQSPLTHQ84yANkeH6dptaleo46/nvPNbWTCNy3PAAOAKt9TxI4zAMSkic+rQ2HSHvoIQHTvXfIh+V\npa4p3khQy8yfIW5KztFBjUQLSony0oQElyaXScjcHDg+pl4EyD6mKSpkMLB7BKSuk+36My0u5ezo\n2bN9rbkDXsb+ZvfjlXr4TPMwA+DWMh0oPjXYFrzGE/4nPD0HW6+s7zS4zgqoPZFwgxFWpZyHcINi\n+RMd4UGQGM4Vh/xMXxRdfLAFBUJuewNu5UpmhEcWbBzjirZ76reixxZSe+1/h9Z7mlDM/DoWtdbn\nWvwf2jiBJbpA0ctJL37VX7DZkz1tgEbqHVBhM1y60x2buMFxnR5EEyRzk7mjh3OdYcmBCi451RRi\nuyVTkm//7MLmlA5JtRulASekX99WxWdfrzn3Usg87r3lU899anMghWRaKn6NPR6qpgREiT0xcGSF\nEullvPMPBQOe2pU0hWCk+5phN0XdhWMkusUCaJiIER2SRc59SHu925CYns0t7QIGk1x2cCkyDPgP\nIO1SHIDEuFzUK+8PDmpr8dAX9I3WEIlrOjon40ccgFR4L6wsH72vOvrV0Z2LO01H+FMsdgk99yjt\n5eKwhCQ6J0emqswtbGePnRI1EwHz8No9RE4N25J5dkfrL5yZJwvXY0fq56S0V8+eJncA9EXo4DRX\n1jZbOhkytWpFACPngwCY9jVmzgSMhgUt0OLxND2NF/9n22zDV35Ed07VatW1KO1C7IwSttLKEBOp\nNjjxLa1WuSHPNP1G7fb1yFNNsc3I9xGVcgtyXIdn5iGEDVQKJ7+HmcKvryHToAPiLJB2BDL9jW5f\nFoixwA6scz7Qh2LzSq2CR2oqi/ywFcYehYmPqETa/od1ZNewRnQUPRNmOA/2n5/suGN4i0bdEwvh\nx1dp7JAfnp5QlL2FQIfCUOgBPFRPd7QThPfNEaYXhrszrpnT2UL+C8uBzJUuvvMtNhsQckHFjZq8\niFOb0A1i+Oq4+fWEMJBfERb/bFz2MQZLoCcni4Zp+n94GSPVjGQ4mrjIG+ZdIjuXOU0Z6k2ILDxk\n+WTQpHMPYsw4GrycsUakWpAInwcElFt7yzhJ1/xwN28aiNjv1Fhm2Slk26jqWmbN0yE41so1uRiM\nYfiRkSk4/N9/vo7vdJn69fwaALfrkq4+flwoNZHDvTEFu4y83tOKkSmkNOUWp9RulK+zb8TiTqb1\nuQjVLLshfpsdwr11hIsLretFueeI2wDSEIQ8faVtAezbNTzjVw+1Y5fhLAlBcve2swC3uhEbhREe\nTmnUw97GJw4mGLo0h5VB2kSBR363mkW640d/qknKFOxovaMhKKCACptjEdkYVV4Ame8y+ERUYI6F\nCRJu3qZr2QUwc/X4AomKctho9i5PvXkoR7CcfTysMQzgKSIXqoZvxd2w/5diDRtOFUFrES1WxUMX\nJJIzr9J4uZ4q36Tud6DroZn0HgNpxPfsppwHQikWBh7GQ2650T0mt4XZOq3HFAeCnIZQmYF487NT\nd7oSWcPzKoyn3UEKV9oKz5z41J0QnTHlcF31Fmn6YYVSIC/z6GUSz4ffKVSFnLqIRbeEz5cp1b3i\nogwr2dRSwu2G01cD45jlHCKWN+vTG/F5liPEOjmP35TrdxBxxH9+KThasyyWfosSfts0QFcD/sBU\nqw37z668rkI7TohDI9MQ8QhFQE/VJ05/rCbToOqkSdO5XCkvj96UoRsJeOSM1DamIy4r1MjJmW6W\nsDeaSY4BXjDjXWKNpLYJLGikMdTevDwmCMIhqxNOXde4rMw97cyFADUgnncZJSqZiRAisiSY6EhX\nm6YP0b9jGAeHMLFZOxky2Uu7THZh+wZysJbTudu4tG4e+zIVHV3u8IURAF0sL83gPbPVxod3YoYH\nByrJpktxVlVXJBf+dpAiVdS8Wt0nV+msANtj7Fyvmt3XR2w6/OHFZLWzVrC66WAMPTgP1/3lR23l\nQ6r5iyRMeWrnJEUCzSASuaHLhhXGKQ5jerlr7pJFtq4p2AxtTk7y3D9Cm5fDLBmiRgD4aASYhVwb\nBh2Kaen9qNQrP+f5O9z5xC7Bnh79PiDzHHrwz56W+8yam3iyZ5rOUj1E5x9f5/LQUrdxH0MYei76\n222OWT2lPEZxZW/v5iq6aHVJCx1qqTdLRXRvRhsTEtEd0e+g1eS6NQJ9g4/L85g2x7LfTmRqbFo5\n4XN8TFM7Uw/RT48thMWbExi/w3sYChcCFXfFaMb0jCDFrzEzXMIvfAyil/94anGjVV5uEnVwlwQf\nyP/aALPOW7/Uta/a67cwNQV7S/9WtHNvxm+UWRgZz4vj4rJ5f63qw2Ix/KtnELImyKCxw7FVa4Ry\nBewYY5qJVHzo19pYdXyLetRZ3RvwKNiKWFVIP75qDFMELbgT5cjc6ZKd8MuRjlJUj8O4Ev98Gm5Z\n02wd8VMZ2K/95xuLk76yoVXdoXs2LTCpW9TRMK4TElb78MZqEA7iZ+OJa6cborYYSXEPsPnI1OAH\nIbS2i+a0loJvDe8HOPQEigetTww/ZrFTiVnYc96EgXwSNh1TkxtU6vP8xSeWbFufZ3QxgZ0cj3c9\ne9dvGnRBsyu1TQCi7LogG982x5D1tgTzdLulG4FLT96UQ3izGLhwmNpoAVheMAcEVLCQVTtpmM5S\n6ZaD6w+jQJ6o47uzQ8lU5K/E614ZDP73TSI1DnE81PYbQPC0uZpH7dMaCZQGojbJfACpvflXBEiX\n+AhYZPV0Yhrv7MmWrALSaFAcjmWtPf9sCqVRKwOnYCaL2RKCPlPNTyu3GJnTb4dwRAkvDnCw4CEC\nn4uZeQC1zZFXfEGxJAmHp0OCvJLirkeqpJzSb90fLKt02Pu5riiibycjF3NaFboGqQ6OCL24CQRF\n5puzbouEw63FAY5/kDR5c259rgh6SkvUjhwgqm6AB6YjK+GJBIeUGW6OqquC4pYqrXApPBn9ponu\nF2Q4NCy2CAKG6s+7yeQocOxmiIbrXZH7lfe/gVEfSWGfbf1yevgFKhm3LEuk7Gf8p97cHb99f7z1\no4YnMWibF5F6MuOfRd6Lkt863CtmmlQDr3abImy5UHwZM8arhprXck44b5XzqpAYQOGEte/XvxOn\nPXkVrNGQKaUh9aK2p3paQVFD6CHykCzGpLH34cZ7vzot5TuX2OduRF4DA9ntoBpyZDaRvZ16zg6T\nnPA93amkuJiRxdriAVmwqkjIU9sQcG5zzhqws2ExywMERMvUhWapq/sAWiBAYkT/uz99creY7ghE\n1Ai4Hueq/yxkQ9P2jgdpJ9yBYkd/vzAab4fvI93faax7W5zqe/vnD6ByfHA8Juf2h4qQzKfS2+TC\nMqD0x4h1Vq0SD5uzygHK6DzRdPZquhK5yJhbAZYt78muNf3ERLWNuZEWWuWF0OGJBepT9v69lv+0\nWE7CFyMobnMxE97lC595ZymqUCI0QX8NhfloAR5wYWeses08frzAHJFccGgMe60OTlWgP7Urjc53\nOuH/KgoGGiD5E+gFa9ntkTM7sbCgRtz+McRRcvd5DFJVobYvL5SQJbMPpiYryEskZJh8pUTXm46A\nVxkXKTSAm+QraxTiF4VKc7s0h5zQXO4Rmce45uk+k5w5ajiQcusA30M08pJpQlG3Q7m8RlEgMdWE\nELP4juT2BDTISrkB4Olxuic5AhXYl3H6Ld6Lm+yhnCLUMlLetwQxulxeZfNPg2/6E/0MtmiNq2QB\n+TEl4KnpPW6hpi9xXbfmX5+y2hkfk4KwGmmpTUa43UhSNaveNuf5EQUJY358Kt2TMe8gx/hOsHVz\n3pieYp2BFKgQ34dmOB5DMp45ZVOEcSx0r/jOZGwfKmZzSFSbi4Qs+Hi5YzLwckw2Zs6Dfqkd46TP\nG+u3V0zEdR1/UQb2YFisvcQaRlnbdFZgB6QV64/p0Ry1g+VoSIHo0hNELncWhpzv5WIw5kt7Dc+X\ny6luye99VTd/BkjaXtmOuHsvZHHIpU0bv5UvDqgQTzE7QZcYgVRT+O25M+LeGuXsZh57/aUh/3Bx\nfHXSLXNZI4GNDfeFbJKrqli5TbWhlUfqo+dELUSXfKEhZD6j5OhB9WI7a9yOi6VUAETZoh+xWgrS\neekZH3MiCyfOfR/8QHJnkHAqu/9LpOOJb+KK3XyHeVC0B9GxewhhPG/RP4o+jf28rf420qJJsqcJ\nq2GX7zrz14pL4FEm12LhKDJnhndW3xh8DrTS8+oZIIo3WBEZslzaTRB20MVPWx3EQg3XHQHIj4Bi\nC4hz9PIdlZYYEHCkINrJtGd0a1TKOr/5m0u/NDstJHOnmfXcQYj7j/1FfTLaBELElA/37o8q/rYe\npQq9sStocvWHbW1wzMR107h7oR/DIDxwilVJDFi0Z/itoywio/J1ZaDMKtpP7pAvqM14kypJ3qeh\nknDyFxA5PkYpcrROKB2F+oFBQf0uQD4gC0hIpEC3CwaI2+0DDftdCpyfsGIRRWVG0OPzddnm6WZz\nLXLTm37u4yYiZeP9Ajo09hEixr1KeSkn7q1PYGO6Zs+p5T1t7K50Mk+mgvgGaaZnOuv+lvvnixVH\nHLV3SCgAyZSND5ugZN3D9wHVySnRcuUydVhmJUBeiIlOOBTIzxtA03pZxMCGrFoWqUPtIQbHMaNE\nvE9k65Nz7LLVt9t+vt79rsydN896eazFEOw0YJEbaiOac+aczHk4rHbdvDA8byQd2BD3KsaTlcjj\n4p7EMiRAXrYFyk5I0+av82U4ZdEvNJjN1H9S9xpAD6CkV7X8cfT3+4xkTa/h3Q0Ca7oueffHOJSm\nCrBNd6b7wBke4rYnkPF/uPW3pbc8lj/aoU3LKov7TsOBQCMSb0KlkQhMCtkcekbYBM04Y2RTTN5Y\nJsixmeiV+nsafZRRplK4xYBA2ugXq7CqM9DZb3eZR54+dX0c86gX2VBhPJvp/9lCuVg+qIBoTQK9\nqeCDGbFIJHJm3fpmrfTHEHXdv08nlL/HnU/RPjF1+gI8yQfQdNC/2gop/YBx7Rjdo2vs399PTx9c\nm5rWb1XM1GdOQ04+zjwtDtUzOZHv9+mKWH0q1Cy8bXrkWXg6j0wpH1K/ZrpIGlHQNfCZdCbj+bCB\n0TGL+OodrJE9O9ydLhddBOQRhxxRSGC92VHq8O4zkD57DedWFbjeIXFmTZ9F/bW7e6bKdiW1BLUu\nxyVWmIxrZS4o5RGrgynForTQb3tDy1paYH/RjP1P9Hcv0DS4DayBuElznx8edHPGDxzxmhNyDVEo\nL26kC8B9KsPrzFO+YWuEOH7btHoM9pF5qJ6oELyzPk2HJisZtWvJvPuRk7/rfGiEGi5eWroD+5+j\nzl8HGQ38CD7E11T2eK++iUHCIZ1QkisFQ8aiIeVaMNPCG0bWYiG4Oj549brzYwGOyo5spJGpC6Ae\nExQ9RHxHJpP5EF5rghDc1PyN5VPPtIjG25Un/ZdxyMn2ZsF8iIx4tFfy2QMqA1FK8ErfDCrv0bkf\nZPM1Qt+mwA8FGNh/42nGtoJNbPjbJaUPTU0AUqGTJ4ch9dwxgk/0N2evfcWYVEMPmODM+A+NH1L5\n2mriLqRRbRto+TCymqRJqTsm5WEDqcB+6pravFrAfCBgIvNDsY85zFXINKQ1d9gvyGIUZGXF0a29\nSa+8c8EQ8afMVxTCTnwZjMvMnm+ix1OFmjpA1Tfcmzz8+001QZLJH9VDxfdVG3qjZ0fCkHNaGARD\nSD0n4oAlcNBq7WSjiTz2ZzdtbOb+ir1W0kMmv62uB+WmZWO02K57a72EKdMMEHKDpLO+CueYLtwX\nEz/ivSbP77hHYh2nICht1yM/AqjrdHvOAwgfVQuNBfJdC4urpx/nsm/z7PMMW2cE1Qu31e5Jznp2\nqvYulivIKLKOJsPeuU46p6NODxQWbk0VNgei8KGy5Hq94S9uvVeMlnuOYm+NR4vrFX98ZAxrOL7D\nTtDIm37SFw16psvsgozxJnseOF+mlbWSk1JqoHMd5kViU2OAgVvBSgDN2hX+xBQELTm7oHdZz0Gm\nSomeVvM6NMOZYrsB7n5BnFy4lz4wA24vd1hFtKsLuWaen8+655A0jLIqe7TqtwBNNuLTXo2YYb3O\nuE0W5BBvjhhrvPZXR7oshjAyKNVi6pt7NlNElDt8xwVH6cvM25EZyYIfJg+i26Jl4Q1b/Fw9twww\nYhGYTKUyaQM2ZUw7SGiyRWaMX7hIrN5Q/RSnN/3k52Q7q57/3LjnDQUdqidqq6/Pex8sSeCCUAaI\nMOG9OR7uh5nuZCdJ/DJckXKj9R2sdQsGERPdH1j1NDvRlXzSkgAdyzv9yr7xSp1prQgONRJ2Sz3d\nzb/iSdVY6rAEbBKy/7Q0bt5NvRqyjdYeAmtF22+htZFw8T41kTWPfGbmovLyixAR8nbDf1XJ9P/R\nz08YB4ETTUg2WWyWFoIrAo/oCET0M7OWpg0mYcz2QLAr3Ggki45JuVQ0I6LzbxFnBjpOXvmZdiYH\nnurQmsKxVw/ql0+K6Nn9v3eFM8OwgPt2lpYGZgg9xAbZNcIUe84YsDvCZ3h0jf5JgrJrPsDEPj6N\nYMy4pWiavLEItwT19JRJhzUm5ikvuDlfAPIS3d/U19mtnMyddEGLHKayfuU8nyrZUKGtTiI9bMGd\nmUX7aPsb3elXEXDL7GfI8ekcCiADtKXdzYm4BcnjoH+I0EJKBxI+Eyb6uKy5ojCgLR20kLTgEkcw\n/IV9ud3EdmnaUMk2ZyONoSeBl0nnqd4QDRhrHTD/BCgZ/3LTjAbjiq6SxHJFo6d7NHA/jPqj5gZj\n2jGwEh6MrAd9zOYepWZpV1Mo6RnhYvXt7GPAUXd+ujG379+h5SxWvO4NEusNO+dPJjOsC4q9UNtC\nfJKjtNa8NpIDmFlAmQAHPfM/THbD264PCFf2kdTGpg5F3SbJY7MvayaWi5a6fLaL5O02sTj939Y2\nBn4vMAzWsR6PsTpRekPYa9Y676z3/FwoLdOFkB8UuOh5hzl+pY11/SZD/x5TAKFOSsJ8ktOZIQYP\njV+a9qef0t3VV6pZquqLUCvJQyR3LaCEZfbVvVLvPTa3oDYgYw7qKkpd2RzaYTYuGRbRGV3fWRTv\nEAY4BMeN71dlpmRELGe/YfAMJ1vbac5MiHUggyZF8GZdkHXkmmqi9KNvTKhDFarLOu3oKFtTT0cr\nzXDxNtVWSeWiffWmuKNyBoBTXJokydaJ2sac744KYrdrBN7ndzz6dDCzC/yzQx2tAuj/aZ4ubrRx\ne4/oXs7OLqu2PeI/ERtapjwryCjNHmAZnQJAKP1Sa2xO/SQaS/xNJzLeliCFq9JlqBqycy89LxRh\n4Fsa3++WiRFKW/u+rBgDwS15N8+W/FCOKoSTGQQBV59v66Io8g1JRw1zt6oq7gQPeYgjLPL158sX\nEV9ZYtWSXq5cDNV9vZy95E/EuOhF392IZTsXLEoFjfuR2dzOBiMKP5mDl2yD9UhBja+QPFH/ctlL\nBmzq1qqb8uLk+SH0qrO92Oe3zxRARz85Jxzt5MAhTd6P/RXPP+9c//RmSffkv8omw4Fh9R3xbhnB\naIkERqcmkerKo5U9gsMEsLrTZlb9tPL+3mYgmhhTm4PjsT8+1fgjC4y+MkPTTt+g6ozu5lhIaMXi\ny8Sn45dnWmvo8RjaqGPLMBm3rqfvvpf7dVscvkx8lrN/uwBzFaOA/8kDwEPDZ5g8540ythrUg/Ka\n11Wcw5mFekbOW+3KChIazlQBjgscyvO8yItBg05dDBZjDTFb354Nvc0KigCzSSNCQaMmuDY1hD1r\nHILJZR7qoJQLclHqqYtejbHeBdfffGSP1N8DRZB00HSO01ZwBuayZHlCdFKH3apAA/d/SlARwTrw\nITk04SvyyHz3L84xUuBGq1yrxOeIlHdRSbvBmNcFITKqdyarku8OarPADkhT2KuEeZRDIQFtxACX\nh/6MPyr9BmwpOwStmr7gsCatvf0VY5/8RxYPxG6X+gXrZ56DbQMVORcIVO5jtq8RkMveI12Q03YX\nnPgRRSyIfsR8+6/PFk3D1pGKuArXAaUukeP9n3iKJgmMjLixAGV4v3yfBEyxmzoH2uSlydJ9wny9\ndL7StEETe+yC5Dxgf9qzo39e1oFmBGyT3kHo9kecp+uimWUEJRMWS+fNyJnsFgahzv4ypMBFbZJ8\nwgRA1D2F1RMStOyMKVQ7ivAhUNFmuAxVC7fqbX4FhjwnAX5EjJF0ooJSb36h2q9L9jxgRqZ08vI7\nxG9Yo5RJjztppP26xKF9HDo6jtJ7foyhknh7ARJedOGw7vkCDtIeQ3+dRpc2tT+My6vFAp7coLZG\n2gqNPROf2VcdLaqpJEeRxaO60XMrs3euPKwLRYO20Uso0KfYIBU68Fu1mmWMxj55TH5JM88YGDU8\nKySaxtwOXrgRJRoXncNdJiLMQSYYX/VloDnK8H00C+VkbeMib3GAQvR7r+LunhfFDTmVCeEm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gYsjwP8gPL6yj69oEnEGfB4YqvnWmYg//Aixh5JuuparFe1tRuJMniZzg9sAMQD0diESPKTmB2\n+hD7t16Jtvfy5Yhq5byPCmJW0VjWg3/v/vmW07AGOquSYuYa9OCFxcuPDu3L9b1FmIoDE4y14tGC\n8aPlrr5gh+mPgkoED7j2UV/4Nu2hwZt01ZyVz5yLWh69hwh4DdcDz8nYn5E6ryQT3V5OkXdKCfnu\nyLMMKEk+II1ddRQOWSm7lB4ueAOV9oud0xvCjUpO+vdwHStlBuE/oOAYhT38blBoSuU0766uFG4A\nRvoROuAoS1wUDv7h3964JczJdfB6VrvtO/rj2ZEffJixMYQYnp1IQ9DBbkPeu81aM7mKrxZukXKW\nKUa7+PPV5GneSCKxvpJRSK9jCUyBGVCXXvlp9Q8Vub79aQUrL39mubMYLeysrLeFlKqf2Tp66j9Z\nXKsWKSRAFVsrOM2EfjzWd2UL3qGC4lI81ygKf2NDpmI6YY4y5OBWysZ7bWhKGJQPVj0xp9pACjFZ\n22FQ+vQPkAtw/aNGv6+ZwkBVbn8MxjwYv2mQTSn4vraMZmqr9ma+IrV4OiFeDXwK2nRcnz5E504O\nHMt60mk26rp7zDyLiJz0FLZ9VWvsc3aMXAoGsinJeFlqsH+jVMQTGbf2ptM50CmyQsBQkWjMYBkM\nhyJCa0bOVxWaMk6kSx8ur1QZFEcfYGF0Vth4W8fI6z571bFOqKzW/qC6CMKHWc+glOgj/yo4QsjZ\nFEs9kpIM9tJpXP1rSS0u3PzQLYhoXOjQQoCVTJHl3ev6nqWhP4rquTKBRpTX4iQ7GmzzguejTvth\n48Pg8mxu/GmqPftbwNl/UigDx/QvYoe8jVuYaHcLrjE7s/729ZXT5fNiIekMsRo1oycSeDgzo4lj\nPsbzoQYKG7xliOLTRV/Gzo/tPDZYPLt/WvcC9HE8pKr22JA+U5kq/Y/V3JZ6VGrFCkPy8SHtpKaW\nw00ZlC4UCecHi9D9YingOaHavRusAwzn87qVag3GPJRHSKTsdoRr16TRB8b4V0CKu3wygK3wsdIz\nANmNe02pP4xOSg0o4TNNIg4iAPELnTgRZxLuKdAz+uMD1lz+wc/2DHc/zCQHDXZzHVzqEGiKnRRH\n36D4c7BQFaZ3RZpCOlyq40/Z+WXG60XON9klmtbgY3S/1V76FW1cHcjCJlEFf12cbW0jW1TSgcNr\nji/2a7/86reIlnjhyCA2DUWcJP0iMXcId7SFglg+bhxc/+ncTKYZaCLIIoZuOAPoNcpImmkFAsD1\nybv90cjFiSybZGuiZJ1aZVo+8Hl7GumeOcyUKvpJ3EJqwizLE/2yFPpXdg11MjW/plNR8TgDD6w2\nkypDvcf2ahZQdNnI6mKeQFIppIeLnDtq0VoVGUybkd3UV5CxZRo+JnXqTc8cABCkuvNcCU53ph9U\nGrbHdzVP2E4JdTgPvmwGSEsYJI0TgA92T8Tc1uSmbAmoFC+txFwb+SL0HqCo7stjtKf09t4h6nFm\nzts8MvhPuf+chrN/0mKhZsoG2SRhxVKKDvO+fEZTwM9/fbYLvJZr10zRUttjmmrabNb1Do0HIKyZ\n2tVj/l+FtW6I4jRO3sbNSlJIDSkdis9VVN/s8nuAerHFDOZPbBC2adJEczsBcfiDyuvJw2vFstLY\nWrYXwWt1Pj2ESlG3VFSPd6r8IY/2vQ9N6zr2qZRvZAyX0tAVtWpCVySXuhR/bYhpMGcc5F4lg13f\nCb9znx5+YjzD2dS5j748nSdDxJdDiRiN7upht8CIej5w7S2eRx5zlr9Z57rBFyl9bNZJbN847tHC\nCehMf/IqxtygA+9CgBktr2O7OsL52X90vB9xNxhoHmJIC1luSq3WMkwE4B9XXfYV0Z1THWCW0Ray\nPLFJJDwXGxZ3iqcpKxKNqUZj22eEguj5EL0c1uj0wj3SjtHhT3QibPJ61XWP86M7cDbhzokDwTuY\niocltkcYCQAiDRbKh6xx90CqbgUJcSrulI5SWNLEt6RvhR5Wrhb1JkhRKgwDe6vJoUftUjH42UPl\nFF/4maor34wCgHb1zUrrtlRhtrm9Jfh5felbIK99FFQeQL232r4Ou3xYsSza92dacOOWg3NBfOZ0\nQ/C2RzCz8OD6kgERxnv3sJ7U8c0tdfnlxBxUrbTxOwDes8SfUqpPT4lOoJbbB1D0DrJeCfi7pGTt\nSTx2HeNC5IMbgOr0kaqBQ+SvzLV5GUBkz2TyhXqHSLnFSZqzzSSKOEnW+1S363p+Jiz6/i3VoIxt\n+nO4KbqTRVgynm2cMzQxp4qZc2qCUfvAc91QFExyAEPdNOLMYvCMogu0Bg6rLV4D0D2bZ3udWdkw\nXcm7ah7k2V3egMEMLiai8Jig6MReBbdv4OfOtXGYS7QAFPHFjNryAr8gU8bduh47ZX4MDN2EOjUI\npL5cBSI0nU2IfI26MieOliYTdabZY80TvMZ0E1GMCqX9rLoIRswVPgVsukrSEWjLd09SFOAtn6c+\n92pEp6eYkPWRz55aDxuCimHwY7phvUpBjznuEH3lpJVBNnLwvKjrkWJBDj/K7IlhwZMzhZ/ld2xb\nCSIcoAQ4EZpANsAadnGno8GZbr0nnQfQcW8qvWG0jKz/OENbFk5mWfrq/2XBPgn5h82+smpdYj4G\nfDmZF1bsTaSP6L9vhYwyHef4cNKo2DNsN7U+7LfGy5IcrRHieUax04nuDAgZCb1N90n+z54XSI9y\nEUG+xHlR3no6b4IkXTm74aPyrWuhNneyY5zZIKt3cLYsPpw1qcRE/eCdKkDWcRZoKb8u8K4BZE0C\npnQrDGMqt5rVHYV/vj72ylwJpg5t9jzRWtCewgt/GLqCFd6vrC9ewnYF1hwaZDyZUeF1hHPBFd5H\ngH2hOuYJhH7yRFOJg0NIu2GV2eLQhOGWuRHl+1tUEPbvZgCLKMXPoV2VEPdYUe5drUwPZ8y/oy+m\n+VVvUG4YHHCXtOTwg5ZnCnk6OdskXXDxG7fpCw5KnJ9thCdoO4MbrS+3iYGO0gF5Bx1G3/mHVuzZ\nUJbJo3bqIJL7dGYmGRN7l9Y26BGaTT+u22fCQEj7+Mwzkfpr08DUgp2sIeBeEQxiWUjonqk4KEdO\nOOb0RhBCCviYx4J2C2h+dcpfXVG4WqM3h8OgD4GfmFbA97XGzTmFhVqxDB6HzMOAM0I4Gn3K3wZP\nm3LIQrXgvPTwXKHPCsmjSO6UCPfrbTD20xVaxnxUXNjdcQgms1d+5iVWlMLkgwnphgfS6anuOy5D\nIb+zf53MrlTY+ri+saYtKhU+k52H1PAbUxbvT0mdWHACVstwPUf7/U3CofWjV6iucLSxv43R+5/s\nvl5uq/IzR8HzA0r5bppslNEEneLVKyUiPEX8b8teq6KvYa+hF/WOkJS8mRXUj7EAzFSHqF+m5t6H\nD5J7P62i1vlXX15/bdkcCh96dkTvGtsV9WXePxBx5LKxXYOfg/4jr3ibgm0ZJDyiLPzdTj+MeKCy\nFrn1DF6fELbgwPVCyb+xpYsxS+GAHWYPwmUKQR0rop+GtAXlo2ClpixdjfAmWqJadUngwqkQXQxP\n1Tp1Fk9NTpXwmqDMnByDxmsUEsrUJH/QwtVW3i8rVkdT/sy63Evun7x/8BCJDuFXgZjj3s8ShqZQ\nVXIrFgtvwu02nhMQH60cCufg8edvSTK1JFq9tWtoW4bjJmchFq0e6YJXf73TW3O4T+GvM5q5PP8R\nMGKJnn3huju/HjMuv3C7WL8u9C9X6hqUfVMT3a3xqUsf9EWTH8TGvkERfYHDWeWOMtSNhunFSpuu\naqxAgVrggeSUiEsXl9sSYf+uaI5hyOz24Shs2LiduRnWOU1xlmtUzUE/8V+AfzELkAtU6CsdXD52\nlkHmsNQQ8xKyR5TblhdWt3g6n1WAQTrScROLVCKRJFXdpsbiNgqimy2GW4mlk9n3cXU+bYUofLb7\nJz0vYEq2ayvBbRbWmcUsxRYeg5aEx8cUmqI0SrDIOsEAnz3H3H5kZ06g/Xnt1ODsxLvyiPzJ6gmM\nq6/TyYR39R57hafPX80IlWVzOeGcgjwetth1aPu8NWPbdrv3W6UO97Ci5fu+MVLV7vIDnkypVUYM\nbWMv7vIyiGvuH8bSDQzJhfeSEfeAIHihru3Hi8i+zPhIDhB4FBf1+uZCVVkf973OQXiuUfDv4ek7\nRXpmXqtU56cv14xn7SqDI9l8UOMi+n3CyJCWXcy9xXhylg/PR1e2O1KG8LmtDoPIYRUd/RRTuiZ5\nHgHxiLY0O5+mBMhFMvkAfD7rP127YjU0f2Cnktj2jUBJVTB6q17ddR7w2PXjQeugZKowP+Z8h5wM\nfuR7M8mrOoNbAwVmzhE1uvLJXJEyPluY0N4Dm20PozqUZaAtGvYXhmfLFz41VUuJJDg4b0/Gld/v\n2cJXcQoQKzpy7p7+beEUp1tH3Zz+lp7Yd4dJnkWXr8w097eDEccwIHpX2tgGuusf4FMCQqML9VKc\nL2DfHdxBfhI9IZP5ALW21+DAYMPnKPQKLQPSKbxLDPx3/RPj0Zl/8oUMvxypzUukMLPdeYacX+k+\ni7W87gzHFoTF9kH5FA68kYRBsd8foml00b4AbUtOlaL5u4qdse9YjZ/nkRaaKgjVMnlOSua97bm5\nocC+8NXJ5wmdpMe54IMRbY22hpyIKjmOgt/glWafX9d5fnbetBgMbhZbMK6JdokX3kVPpzEQgZB+\nlpWcYLiv3WN9zzsmOiYvByt4SyiNKNZ/A1OxzBGnCWngX2qOYQrnMGH3eCp3V/GHZHZdSraX3MW9\nTiR+ZGwM6p50sUw9Nwe58bNmsuFnDj+mZpouM75qfnB++No/e/G9yAd4RycS57itXVg/gxCrnTFE\n6od2haGmrsNZeiP9D7Q7B18KSuqSvpl2zlazY+O15379LoUV1rkz+O8mnNAVKUpb6kZOTdTalmy3\nLtOmCcZJ57EshtTbxNlaRED5qdfvx+gYNTsKcwLjO+nK3Jayoc3iP/jajThfqmW6lEgmWdzSAQyw\nT5eEAxzZL8Qfpa5tyflgweXGCU79O7fbp4hydQhP7Cp0FjinmdQ6XB3EbWXHIRNuYHOWIFDV60cY\nv6R4aPB3MT9VxvFdFuHMWqZ36trXIcuoZB4giyL7UdnQ3o5MvHzKLrig9+k1Nu6o+g8vQxO0BA/2\nESvmvb3lzS4QZRBGQ35YuFcSALEpTkX/I6quQ7Vm4K3pMKrvJ7pLrcTeVJMTvktx4Ts5QXXyXMRf\ng9zyWT7RfcAwb5lqj0wQCG0URL8uf4PC7kM5/IBXYC4aOyGRWVsR8eAEJ5Xrm0rhSFUBfH4PK1zR\nDpwjP6jsOSN13vn64e6T/q47wykgyFU+G135NWBFVlDtLOJid6C6W4WUMd6fy2ZRRCmlEVN3X5O+\nfzsVcF8AhAa/oOY+p/2jLkgdPieHYp2z32uIUwgZ1QJVdkMikK7Vt2TEk/eIbbgQkp0aMrLyq8jZ\nknY2VxA/exnZrsKMMwQJeLuG+SueVaEyBVOw5rf9HLQOXaj9fXEJgIYrMyseX46PDyQfHz8q1USK\nrrD3NWN4DDrC3WgUM6Yp8MF7sLu8zgK50LwdYc9rmrds/BUktRr5RaupMGUE0H5uamMZ1TvW0Whb\nKx2qzGdm8duE3nXxISyWI5u6DZN9uNwolr8d1Dz8bGa/5457tcnC7pWQHL2K3N92iU6jiiwavv2J\nvyr/Z9Wn+4xvXkXbOvDrY+xFC65c5UcoVk13ArY95bVj6s+BdqYbtvaJLrso5j/nfOWfnpRgOInJ\nFhjuJA/Nipi1lym9b4hW/jkT3k4IYDd7lDnv0Y7kjN9Kx07a1JPfP41fLgYAQk8nISauUNofLFOM\nCalw/VAIYz+aHHF3/hwCdnwndDrTUInhe1CQqTlw0FTUs9whk+zxJbidiijBvLtBCWECEkRGNfTO\nyw7n+042Pz+NBaDMRgZHNw5PqCt7XD3eLZa4A49KlMGdir5x2a39touQcc1fVubg0XRwSffMgRSa\ndp8BvenQY96PQnvZ/Ra8F++SyZEDFKmpNaBorOqDSZgJAM9i0GJMyCftT9wuRdhtvM4fV/1y8UVh\n+BT07+HzM7qFUvO+6mPvPHoA/KhTrPwsVktODzIwgfqAmgmYu8EVu++S5ZWWC+NoxEl2w5kNmZto\n0+zQNvRSHqaoeENzGR/8Azp5Nj1VJiAlketTlMEiobNKBqcG/pr2aX8xuNJbfPHy/p7P0XP0PchA\n8VMy/9tWKf2h03LAlaJ7YApwJ+f/MuGwahQnYlrof49+JzPlSS4YV4B39PfGQ6CyrJY0RYR1y2+9\n+CWgkVWWl/czyxZ9dk+34ilfbxRIwuaYfwFNACxMg+hdW0KUah82nRO3Kz9J5gJVD7hLCmYllz/2\nBaQgYl9Lyl4UNmbW2UvRO6e2ywxpenlAOGLTlGTThPpB+WBQqwA61Z+zXdY1vsRa6F7lOM0SY7Tr\nLlBXL2YU5HCLFqsir/HRHGuS9YZnzloORBMxFGUvRsBjCc2oBQOis7mz6ZuCsRRAkQPnlgyVun8z\n+PGRVsVw5Ob9RG4b0cZJ+ZIX1781WbUVc27F4jo20y4nM+HjbnhHEhG30pGbv9Wj9P0DEKd/wUDQ\nC4QgF3ErgKrRFl9JemsbjdXY8WsiLV86cXjxamwVAdy5WPxq5DIoCWnsNxbpUFjNo4+C63xuyayK\nqdTxVycOrrvcdBLr+ycxd2pBaQlLoJBBG60Kp4Ii5rCFXCiZPe5uaMR/VPMDPNrD+DW8F1lPc3Pe\nZRexDQlhLqj/ou6g0Rr1ZPzmirsPgKQKcijW8BBMEUzJ+QjkLzi10V36Bt6HTF7diFj4LHj31bO2\n17o+7bA9t3Sq24acDuzx4nwXflnSEwHtE4GUY5b2K8V3kgMD7+QwodrJVdEE3sydwg4QXM2jpA7t\nDLBEe0jOlmV/13yR8CeGBq38ut/bz3aUQKYMxSIrB/NTy3YubOlaUSg87/3wlFmBypjFaalCb4mA\noJ8R0CPWY2nYmstygbs6FkiKgtZAImzmID28yikA8cEei1aOJTcqAG3TSG7iN+IfQBg0fl4caa/i\nscfHd+NgLPCcHJ4p4IkaMZZLBwGin2brl9cF9RxxvkP8TRisOebPlv8X5AwCw5E7AsrU5jnQkVD6\nT8mClO/+IcYrYCjFOgdvKEJGQGMeP2wsV+8v7EL+A1gHKhIEshZ8nM35m4hM4OTP1YRYzO8XsmiX\n33AIBqR1tzVF0doNkvpSDtJ9GFxznFDE/Z6CSn4krQLkcLt+Q/uBMkQX/3nyHqhdYg1zIYp4L+oO\nvpkJRs7MmpBkjdMaWjxdVn2OU/AMoPAWZcx+zxAoMA9YVB+WaefvqlCdErWAvC7f1BZ8pIMCFHtI\nGOW9anUr4iC8jX+XjdsYhTlBJ/YUKMdFnoMMPLjegcX/ALHgnzO20Ahm/YpP8ox291NmOXLmKN1a\nIjpYe4fnswuLh6hs9pA8oWxt6aDmZ7ZMai0gOdKjDJ4jr9kwXeEvsvkjLRog8IVr07rcksp1PdIq\nvPZNchy0uolhV3JclzCqf10IoXCD2VbpUqD3K8/e1fw2ut1yinaoizN460hflrEzPLuMbgAbcguv\nWgl9ETqi/FRoA47B++bN4tkcpxGCeoNv04I2tzi65BnBfx7gwY7ZLhEjjaPQqPz4MW9pOOiJi4Cl\n9OtQd6knjMw4U27nroerHNcBB7VF17hHgVhLml+2iLVmR06CLxH+MUjGqkxiRM+uN9Q1kcT0CWsA\nwxvRzwp5qX3IAgTKZ1gjY2+l8KFoZ7ZhTuA0qTPjsPA612Pr3J6eU7oWUrtzszQ/hMegmt/tH6p/\npUWOyJxFLGIKwADCOmZpx1mHtE8MIsGxyisue34CAGn/uoSev2RfUFjT0xziIksfdsuUevd8nZLQ\nn2fGWPo5G3MC0AVQRLCWZpVsq5YXeJw1meW9MS52LZqhPrkWScoBNiKdrIKwhayGLRISHUXXxDnz\nTJJf3VqB0Ea+K6dvE5sijo0DbrY8eh+xEfEB8B2OV5yFC3OuKOu+pK1mqhpGHOGtWzZ3NsapYvdY\nT5HhczqfYDkYRJcx1g0Mk/0vSfpXReaYNo4xaH2Emd2NWtANc2hqixSbhVECMLEwHFms+PqnOMNj\nnRfuU9c5E1rs7UnOPFsfj2OMiSin4a55wJtQ/Dx8puiVBRW5VYiIMxIvnqYcQt+ohwu1ix0eMQJc\niDTxdY2iHqkn4kJzjl2PLZMKZxW/oibjt4cVJHy326+TG0plhGa18Ql4jpzaCoC5u470k06Uw5rY\n5LBNjrB3NRdR9Ejve98nVTVPc1j1nM0qEZmSghHrkWfP7IQsD+cjYrIlVwiUBhvY4uFvW7Konh5S\nQYSZ7O5Po1SzAsUs0ndFTJSQ8zeYGTsIhPhZYtFsb3e45qMd4WPNDpx/n2WfePvzbF/0ba9OrYMk\naxULpiPsuGWGI7Ew9s5yIn+DO+TqENMCVD8YqWkQmdoFMNehWtCrACIZ8WsLwVi3N8PuaCPzIbuQ\nZHxoDoucricxobor+sm0RB/AsClVbS6GlnjNjQXFc/QlHS45HP48cDQOa09fWeOc2nkMvqWTpgq8\n/JZrwIUbOypOAYfaU3WElMKd2KV9CIHdUBMyXVDVNSOPEvo+etoFv8sv8dn8pEjH5WjvL8xEn+qB\n9POzO2JwXNP6Yu9q2+b0pPerOPF6rhyjqjvsNuNeOalCJbxxSellw8jk0aDjrTfCs5FbXP5wOv5I\nirSjj7rq3z2CqXn7bv7oTu6gZP+P7UjSA9SNB9E6gY22c5YGMONs1vDqAoS+MZDGOXn0Da2PDrr3\n+H5ndCK4ZYu2C8tzRwFODl4cDrPzvP3vBbdeAIUNWXKHt79evnVi5Pfe5BKG2CrXUk9Le5R1Ono9\nRczxK+h/4QkYG2SSFjw+TqjcXaMdXH8Rf9LwEyvaFjhjZp+B/F7kguBR25XB4C++YbGkEiB9zemz\ntm0rXuxQGpI9GsStxxScKbYHxuEGjJS2NaC37tLZulHXCCnbPkKx0d4FjndheaCNThN3QBP6eMRE\nMnRPP72ww3F++kGuj41OMh/ThSlPbUdpF0iIv+Y2mz9HQYIeWKYA/KozacuZ88A4EwFrzf4ZPNG2\n+rpPFpQd2u2nYP7y4uBPup7ur+vgfdLrkVjEXCiLR0ML49CxXDUdlMCSZVCpD8zDgAlbPy1KFWLl\nDZZCCrrbZpyemu+QoRtuz6eiGR49HZ0cxGmzGdb2i/mPEakVk5Y7jWmY9B2goOjILn4IjBRXXhSD\nBan/da1wItIyxe37GmLPajqMnizDG2j5YSeedWwShkc17Eft6UlubnQQjnRq2M1v3YIAuH5Yvqs2\nHVS2RLBKu+FOGpiTClmb/Qf3RP2FxMaBKzaTvPQZJWhQuiHJQTeEWXAwXQ11RdSYxDfd5phb5AXQ\njKDT1ziXCzi+MsBq0kFwQwhNFtZYpy3Cpi1KwsHKfgD1ZHyeOlnSS/W9pexywITNpmbXJH4dqVOc\n0Ja9ZDCv8qeLDrcVkgQMI+F5IOahalvErsFvgOa5YEv13RK8UeRedxgboU6BUoqBGxsqjvyER6u/\nd4KPXUkpzpUxYi54WyadOAk632QVJbz4LV0r/FJxHweIY+IvXbuU6Zy7CQAZn9R8BS9Q+nMKmBcw\nxTb7bNAKH+ELrqJBCPQ7mIxkUdh1j1vlGIzTB49/rfLWeY5+I3udmevnI4vuFGPMRTLtQkZFiyiK\nD/Ho0Xsewx23MM5t1XzeF+FnzObIOlMBWex0em3eTusyi00ed9FpF4SKrOtGnKagH3J7F4tLILi5\n9lqotHHJS5+lTR7nfaCXXfMRxr1L520zBMgBRcLrMP7VgFjGvvIIvcXIP14RdJJYjIBvi0HSHrdr\ndBlO1Mw5012jCApYDJoRJ0dDnNSknqQXOL3Q95eLZbGUPTwURXM+6cM5THUTT34+qzfwjwXXnYOm\n7b5SImx4PnEwU8uaKc6CbcZF6kox84rzmSPS2Mr4todKW+qIWN7OFPffL2HiV66VF5g7YLjCc7W/\n0dtX7AYUk3e+wXNO/q/p9Upg2joq8BRRNoJo8P5K8fE4qWRFncdGpekApKNq5/a7y+HNc71hd8qm\nlgxbUsx80tO2s+1gBQadJl/ni05q8KovOxwcWQRLMtpMgpcILdCDdDi1zticak4lEAIS32aYxDYE\nV/cEoOYxWX9IXLQcLmI3mXSLBVi37svmfbej+Jf1v8BN/mpLMIVRMd27kSldcR/VkPzoGGwBMMw+\npHw139CbFh5RzoihoAILYOTpOYnoF7mNxoswqzWUFaz+fl8hZQDEtyNnOpbmxkT8IGT2Ct4EKkJ1\nX7r17ABzZ4Amu+rkyf3GFFTz21itEab063HhWvv4UWZxe8ZrpHnRAnNcq/qNWNAl2FWjindtoBLU\n+C/Yjm2MDzBwtYau2BHWhvgxLnLkoJ1pIncOwxraIu4KxCMkmEGwlwIzoQYOW/NhzgrvLdzmSl4n\n3dvLjZ8FPRn54exaeJ7gjRmI/Yue912D/7KvXYZeeIqc7pnPv1V+WTsq/VgnxVYSOtEGGGgINtbu\nojX15BIsPrMSh6qVKRmxcmdOwn0BHjhX4JRc85HiORN5AeH8klXs50pa+fBVDMvrn9BN9x1qnEs5\n+TLXIo+Gy9htaqLUpZO56IIJlPcknama79C2G5mLTHG2nCcw0h+I11v6sbDGKRT+s20fYwr2qLeG\nVESHTbrJe9kKtT5Ji9qLUTjBjF7EHcpd3MWXOclsPqNZnDUlf1vrsL6xPhzkAcQILhsrosZwlmnS\neP/t6VrqlpCpP8zm/nnOsPOilOwH34nQhrgATAHAh7L/WO/2bMH8evTM6ASPJIjwMYcIxPT/HtR6\nu/WGIZfH2n1ULYmjpa6NaVTsWWjA8Fv7J+RKRCS+JEu5sp9AH2CXD9SV2Gfv4SWyQ/d5Lo1fKEie\nJlKFT3WSqt1VfeiG4dt0X0TRcWbYhFfkKolLTaq/cVcl5PbhRMeIFzMkh92FL9gtM+08S648mkth\nPzfqeMrl0gQqvNHurYYB+XYO3hjPhE1Nqpi4xgcy88IIBz2p0dwNk611QzaaCBRqHxgsCOoL+yUb\nkKTyZEOIqngQV9wQkvJLuHv9qXEmF7Oti9dUTim/IYYHWQ55cpB/3TMokF1gdxdKr1CO1vXyBjUB\nQAv+tXSvk6NB2lpYvcG3H6r6jPU9eyxCz6Q9RAFzgjENbk5OhrV+m9fKzGwARU7UW1/rRYM34rLe\n6cwfUPbYQxEZQgHsD7OobVqO3tXr371T7utyTKMVyniqGeFhwf4SMBaAXXirSEcaTU1x04vSJA7M\nlskmJV6CiRcPqokwO6NmIA2PwOFAApNX/PfKl44rJkEd+e7sans4dCHemI7pvy0C9vxkcsVL8aZW\nE9V7JPH+IW8cNuFyWcEVgWzBH2W2NhvOKpMRoyafnEZi3NkcIHmZ5Q6b5kxHKJcpl7NdPPpBJo+n\neYdhNmPgtBcKljPz+Z/xJ5QXA/LwaR2JXOl6icMjczi7DY81sVXQN3JPm0Okr373PEah6PMvsBlV\n4jyNQXydw+Qn1+GTsAZitnv6sQ9z5GuLrePvmo8kfjOe3KqpOyNdRgCY30X6xSvAGOyqdfTG1Vv1\nS68dyAEQ5WYL1jJnoi3I8fO3YOLjA+jXYCNM2bFumtKubdPt1MFqrJfP9udBLrBvGZyzNlBzEXvx\no2wC6FwuISwjgM4UXlJ95VXCJgdUzEx8HpWkCVXpYhXiyePwHNE+2eZvlc+CF91T17hqB0FTSGkC\nixsgG8Bz0MH7N5KrGM0jMHmkjDuS0zF08OvQvjz9sof73nbXbu1ooO2u989+QLC4wk8evwWFRPOT\nB2rUR/PnnLWQQ16xk7HSke69mN2h6gofSV+3hjBoVleM58Vbf50mxhUbTW0ZLRc4u6UveUpKQetr\n/GuaXzI+2qFAW6LcBbYVOBfjZnRleqQqKxgcP4/3ReAn3FIvxHMBYwXKVe8IjgSMbLAwWnuMfqVd\nwAv5XeTjX1FFS+wWQmE2ZuGZnLgWCgt5mDFKVbcuR0x9cHbBgiyV0EpWK0ess4M06hiFjX+Ul7fO\nMnnKbOCAwylZkkINTvxp4858qmoTCepQRhNHyw4EjLgZQD9GG7gD1MSkSx+Ukd6vVnEK+tWMh0PA\ncJYZnNLzHBm922xB0wxJ2UFbTSrS6pfH58DZMX8DC4Uav4IOOE0kulcBaREGsUJLVlUg2bQpC6eq\nMAqpAIseqefUOrZrfsvOZk0sn2Zlk4hCzB2vW5WV0UCJqjqJAkBInrrMaK8Tm7IST2l5GUP4GWqc\nxvrQT/f/DcdFgE48VhRAaKldDp3fP2AotEyEQicPC0hJzq5hARCSa2SlwDCp7pZuw+RssRqk/9CB\nw1DbvksOWD0qumP8cq9LWV18x7glAcF3ffy7a3t6S09NEZqZponjqhMLQsShegqO1DLJR8JjUyvP\ni5W1/qEKph6IFwsMzMFcZhmTsj26wldJWML5YJIua4QHOQLj2KS/irM6pC/UJEpTOLYUwlLBblpl\n+6Vt/1ovZP168kZVhbjz7mO/vWaGdmSirFNH/bndnhP87KL14N7Vo/d3nlELZe4FCtNWWlZwaM7L\n1kd6+aEcrpUlAWmpMQknVhJ1TVCem6448pOC73lJ0O888vvG0jRfLFGF3wjYlxHfpijTU9bhoKoO\nzlFK4RohaXeYx01PuadToiHQkRAgsr/HqtiW0SnqCYPTGbvRjB0VbCqDidonWfSjFUq+oVflF+59\nSp/oZR723+j3Wk2D8akzE9AcAwUhbE+dvGVw4rVVRLSIGL57a6g9wa64azFzeKIQtUFI9M0+R3w9\n4THtkgUczli+Iho+kMcecs2Rdm41AGw48/4yffp9Rrz/JyeiTDwGKI8LCWCn1EfjQ4zjdWd8HwK7\nn818mKMCVB+OaRc9t0Bz12ES0XVKvFDRRiKiuPkIZVTCS3PmBBzyQELIbUOTJXMCii52I++4GzWF\nt02mrYnNCNxJu9QhZzoee/z0SZvOTGI7VNwby8nu5CLBuxOU91S+kDHGCdcUJm7miCQ2Dv+6lqNM\no4evXv6lstZBenHO4P2Fmt+hDmHP3mdWGWfoJNeYWFzqi0mJIc9bAhdWQrNA0P2idbVNPX3xAs7S\nI7XyRcjSOpQu/sPj5KyptTeuXCASswHtDCm+fi2WT+Vj9LC3vTIGYKL3JqdcbXx2DP7s/xTArRsL\n9oIPnGvUlSVyyBJ8+HTHQuzAIbMuxqoBlkc3wiRuAMTfyDjmtnwidt7hTKAVFfmWhnRJ1qimt0s0\nPOKyD45L0Rvh+pbkyaGUzrPTmjQvr38UhbjxBy2qEAlz8nkwiD/zBGe/8P6PKfktS1EAdCKGSifr\n43+8T3LedETyd7CgUCTrMes+DG0csF4pFuo/aXUAaGjKWSIa8difBfZeY87qM4bsx9BxtE5wLDlY\nqZTDkH7gYpNT4X8y8xGp+U1KwPA9UK6xbXGGH2Ps6AHY/rUx+CcNky/NnHGLZnB529uQEepUvVp8\n6G4JAR8KzUlHJJoHuOR8cpIV846LcjYfWrFCFrATV8SQ4ZtRmGlPNFMqy9YKPlW33q/sX/nWNJ3k\n8NHBAvBcWaQcdrclDcxv6rTShV30DAr+T/fuFbk23xUKkwpn/y9rS+o/pDjh4edrv1Mlk7XZ2i7f\nY86fW+Uv/StsBRoehxo4TtgjvFXVeoYVhls/o6yCodvmUfMPnnN52Q+yqmPpLzHJ/rvClEmy5YQ/\nYzRlHuopU1jKg6eYWYwu1XH8+7pwyaQjOieKxZn8W5fZZr7cU5cuoJJYUD0xu0bQqyc9OUi9W+6n\ndWYly+cycKe03UzE90/QM31C8B8Phk5rc8PTpvqPe02xiWyeVqkm9sZxYdkn0NkBlav9wIweV44p\n3FovAVVX6HGqkx/qzcilkGhI7SLIwSrqUQ5C+JxavRBP8HoN1x3UtBdBYS/JGmOh/dLLYDLj9tbJ\nG6f/quuz8P5RH7ZB2zF3yHc0/ImVrThd6yu79XJAAaPoqyRnyoQn0LbQFJSDCe0NahQ4O9uFwDF6\n6aES8hLYqz6Yvp/RiY8Ra8BkgGp3NQ0gMAr8DjL+QXkNRXZjXpWLvV4EvHIqeGCR1R8JROAkOXJd\nNVVpng1Y40l4+IvXcZh2r4pMDHg6CcpyLGprrxonNQoRZD9hPjgUMU+FWAl+SK4R3uHawsEfavO9\ng8vrchco7crzkaAme0UEw+DVI7PVcLzV0h69kB2IwDbCYVk/V0VTXC+0DwturyrieFPh2PrpSXmk\nD+TM1yQD9F+00oFuZzRGU50fgX13qcs6HsArvWYl7TcjiBtJ8/PWQ13sNOYb6opDQAxloLd9Y076\nbKIejub2Sw8V2tvsHZq4cgA9NnmhBtvT5GZw2LLuNlPT+IvHNyL2GMzMEWmVJULFuCyNfU2V08OQ\nsAYdcOp5SVxA0EW4S57Yi6iqn9ksbYF/oaKWSWPqD/MsCTaXtgYhAuy3YeoqX7vMJnL+Y5dPR2H/\nSsEpsudF9FV5IBF1vakwF0rw2mQ2e+7mIj84qEb49nX2bBVwVOHp7s4TYB8KU0EpkMAnv3dUSepK\nHxRVWKtm0A6SKYL5XAkse0JwmkLolWGVttKVaCxRr6UXmMS/FaS+JFvh1oBZJxyHwq+a4I6DxqFI\nRg2YAsOggB/bRhwks61xg7bp0wYBVDzLCqeszZT1b0e3At8UT+ng2RFTYXo+vnEDiePNwueM17a+\njLQP7fgH6gyP2/IDMCddYYQwbJXJzpAKtqC09u1Qo+VI3hRsXKNe+cK5uwUDweUOr2xcFV3mAPOf\n9FOVltoEQF4eilIRgugmxVRxVVAwDZVyPYBUT1Ql1XSPALUIyWEnsOOD+yuTtVO6ZWRiur6URIoF\nxKxnZ3ap06qaQGN/ubJu81d2IW1EXLyu1XiDhhKJr5HGLgMDavFmXI4xV4lcQ6GlVx5ksPldFCbi\np0lW159fGQAdcEjtPxFlLs2oyhdw3KP0R01qD9SvGGDy8so5Ssf32vBn75aZygzXCSzSVbTAu5kw\nCebh32bJGO2mAzLvl9ZKImfvyj4YR8arY77vy7sG6gIIjaYVdFxyqru6kUHA2CLGqnYoFfK7twUc\n8sTFtdElYA6iEkSX2CxygQjxPPXAsIf28bR+bdnIL6A7za3r975TDJ60rVjWdIKjLbZnUGCHWkoc\nAyxrG/QmWC6dvwMBUxpGtWaQGraFbYbVaViNr0bkHfQb/MYrEO826wVN6tpmDhigtrAbaMursSvA\nmZOdZ1RBYpsvDjoPUJsg+/hh9/XIRRRFh4073J8D4WqFPMcwpcYC2H51So6rq+LjrDZXjnJy3Enc\nxEElZTiuHTIfiN/0l0kRb0MWVorzrdwK4WM1xE0fq9bDH/cQLGg/XawlDlXk3AAWtLALHJ0I4muI\nsFdOIqHZ85TC6FNYB2C9a7Feko6ARozkdtf4N6zJvfV+QXlgsMqoj1Ft21B2qKVxPx/ZlZPCM39G\nn8v9yJ2FJKSykDQc7Lo+Et6G5iJrmqzAZ+OtKB9WvBhL+9qHxMLZB4iUIdS/aZ/VI3EjuGkNYLN4\noIFb0kySw+DL1dkbpX9j3cAUOq1ZU1hTDNQWqsjxoUZb9kzUMbKKrGF4q2gaZR3/0BrQ75XlpOJw\nfw5Tx6rEbADLrjawO9zusb9dSFx5wNBynnK4Q26Y5UCS7WAgs8B+jP8SZUyHTejBtMIwt7LOxFG7\nVkWWjJ6s0fHLIn3GGpjtNbE0MD8oUIx3QvCbnbDQ9v094sKlj4exhBZPBCRSEXYM/DghWNLQya1e\nd2NEws4nUn+Wr/qKphpdnsZtDu9w58DZBWtCRyPy6EwXFU/ixyk85igKUGRGevTQKSeNz2Z41NwI\nit0qb16QaZlXAsUKrQnTXrYo7BaTPiO94DOO2WvcbiN7STrwX7x72ayumF88EQSjwNCb8D1ql6IH\nz8QLb6G31H+6GbmBRGGDrxCasdkyDvw0+rE9zlSaUuylg6ieaMa0J233O2BrviMyjMFJ7Mswt+Bp\nprXbHcjEBp9SwF7SPESdwam79fpTSOsKbPoy6krhQEAb3VpwUnLQVLWjo1JTTebf/ubszRCzTdd5\nQaT3FNouv5IDmdyCcE9EvWAH687fiSdysbA+gBsCghcA+kcbbaJGTBDY8kkctrWxlWDVntJPyVW+\nwaXY6FChUtGcnzWO6b3dGOqcwCLC8Q7FMhXDOQhO8LlADWFr7UGfsmWl9yuXhiLnRiemGRfZD2PK\nNOpIrtsEmr154lX/ZrxDFECJF+5SD2J+1bmJfi7IDeyUCjH2ZVJv/mEPXMGemumDlZxFzG+SEvXy\n2k0MvNMncn+Wv6+mUyTr2CnddYs6luNoc0GH2jNn/xtt4ZgCouOlIG44IIYuPAJqIOVuVau2mtF4\n2LuKP41kqwlS1QhaQQVPLOndYRyOoNc2wLaBCaWfwz2czdSDemH3axdIjgVBID1h75ppXkOa/8fF\nVGuRaGs+ozMT1MuEyBieGDRdesNzrX39v283MOOvQeLKcACc0bWMxlrOcHWoiiD/U0x73SLw5aV3\nOWUhwYwADmZkXOVKbkkObApDmlZhtRF6h3XN/Qbz8jBrhU2/nx50Ss7gMbeVJP/Vy8ylGnJ5hi0h\nmBF45grxGIp2TqmnE65WmOOAZb4af82ghPcik60D6RzlFRlK8KeHVvU7EzDG4Vk/DcsLgRfLATx0\nDekFLQ5SPUeaPZGsExDxKsr6YxhAd0slaveFcNEYfDSX5ndVUUQYSnEMOLvUahPkq2bUmPaBBPeu\n6RD/44Bi1MTKL2afAwWLYak4O8Vc6rXFKJeN/NzJcnEAc0EiIXlSwXPY/CMnXDSPrC0Fyb87Vhsj\nVGo8Tlxzh+lgk/EfCuBxMYbMIvbYn1+Fh8YzsUs4ES3uLc9JcRgD1CrtKUn7nIMjC7AutmA2j9v2\n1V1S0JufCN1eSQDZYpuo3Qmm5RPOdVVc+85Hjjo658mv3OOQbRnVtK0RujOODnLcyzXfFF/oE4BZ\nGUaKuMFy1ZBgh0uNP1XWcIhHWhPyMA07bpsAiIZQEwbm9Ryb2EVFjm/xrD/fPjDsNstOCOgWAAiA\ns/eZo4n5FHPDFBo1fXBjQV3nHOBVnGdrIhhd1a1nJ+PiZgIf13ys8djt5TOnl2r7B7WZ+sURz2Fu\n5Us61gPpse53NVbJGUeceXRcD5AtcW2eQpB1nifZv3O87YJj1rt2GoG7tglBlLDL3GPUR/mUJFim\nPM2irI+QvYB+STnHtsRb9Xrv2tH0lTeqYGIS2wWIzd+RCs/jmkSklQ19koHSSW3JOB++ncb0Y2Mb\n1PbgsjQsoGho4Fwwscw7rsr+KXWI8z0nxSGkMIgKTctIaHHCvL0B1+zbWQjLlHKO44mjdpEAIvFO\n5o9yZ5XNbfTtkicRTrIpwM1zRNPv58gLgiV1O0dh+vlRqtzv2mcFYSerTIb7haBPbnS6PXQXGHuT\n7B5lBJR/0z8s4A6wXVopQd9fih1ystbpR3uNbx5kgRx/gNAm3cz3+b7geL0Ifr67DKRC6l56jlis\n6eLpSv4cdHEw1YgqSt51TJd6JivVumBooVuzwHhlNl0DnFDTRNO9GhwjmsIBbzLI0m+UN5r7U8yY\nni4gpBALUKHzjhK7tAyeLfPw6XHGyf5f3ctOZsDJp+kdpwT+nOwZPvm2S6YfTl0c+tzXNn6WLD1/\nLKunfsfoOV3m/oo3fRYCcVth0Sg8LxYXrTfK/ynmS07JnHUSfg/HVjPoX9tT10g20zaMdsPkjHHE\n44+XRJ4WcHOBZeKN555AjmchCXoMfOFj2aLG69kM+6Torb3XcJUXcUv5J4tBCwyL9G8i/B3G+VBK\nHoOjo09fm86jKo45TAOfVXOQP50qWgZ7/DZMeEASAHeD7W1mbHPpZrHQcrJ6mOdWzM7O5XxDvOO7\nqNRl9N4cwVZAPjD/C8fvaqPsu/FO+2Sq5li+Vu0FqAdAZ+P0mpS3+GXw5o/SSpldDgmsRLTVJzWX\nmKyNBh9/7tstrnals4lPBn+Ai8EeVsuZ5K4/S0Y0ZN38dyW6JKYL4iVR+geHnr02DQ+KNstDkB7N\nltRdrPKAHUQT3JhanWZHiVmgMu1qmuNUdvdrS5QTkBdWQO78zyHBS8nsmiTNV3r8XDdASkbRFkht\nZDjc1YzJRWwWlwBEM7rYCY4P764jChkOC/IY53HYNxD032sgvAi+yXD6qI2Hx1k5xuAHSrDOyRcG\nxMYc6mRIrGSrtPbByNVrjXRDAk6Q3Ri31LjtVZc3Ogo4P2K5HBK7w/JKc9iAIAdGnZtwqX4DoG7C\nCjWqktSFaNFcNUOccs1/IyBZzPkM3eh1n6ZnYU7m3N1L2egmM34R9YcOYP2FT0cFerHqtuJ8yW21\nQCkdtON+S+3BhbDPabdyZYfmlnpR6xUVR9YluFfKL9Uf4WYVcijRVvJhw0e62YNh4/hRfEL7VbfB\nEGYxGiNAKPI+9679/o3uaUO7IBf6znASoeDAWTaJnLDZ++MkJQ856L0Bd/xNEVwpZdv4ejH/852c\nla+AgnrlMvdBwq5w0QMwH0h39ilKX7FcGwiXuvZjuoW9D5Wy4cye6Fr2ttNDOoaDcqkyNnZETpw3\n+7MUe2I5sUJMkLdtEjCAqTju5OKQCMoyOKYxHEoyAgW9ekT6JaoAPnN0/R16Zw1k9mkyxdpNKiEf\nCT/mFBnRmy6BYwCOrSXeHXxG0r2w4JOiC52Vj/4MwVE21pQ2Qj9TrTjAlhqb8K6dTCEjGxM8LuRW\nF3uoIkgPZMAnllBL7zDTCIuP7VXRIEePm82p87HJnJCaiZv0Rdcxnp/GMmcsDRXlT3wKSia760uU\n3CkMolLIfbO1WfsbCIclBaw4S0JqXWvtkR2l3m2zAQqVg3v68/6jOH5EX/4PnUimtCWVpA4HoMHI\nizXop/suvt8AC/3qdzgHnpkLZmCpQT9UUHm11kXNPAXWQ1n3y9F9nvRYCQLLOCcEAAcUnQW39csC\nDeJT0NjCptIBwc9eCTCW7fg0zI+ZqEoHLv/B/LBlQCvyLT1l1RjETUVtMRwusIBUdd4jxJ1L0e5G\nIcy8amGZLyz/a9GFIa4DUi0dwM17N1FDzlx7tdbCJdot9bPSwjvIoRI5B+XEIp1sTeIwfJzuynH5\nISEN7UuH/qIU9WppY3GW53oVYMSQ61qZQGr52AsNBEyQGm+eIPcXtVQ5PQno0gzEmxE4t4GwBGRu\nAmLeuWWZPu0gkL8MqsOiaCpPqHsc9Qm7SVjdVQMB1bBa7E0lQ9bOZf7zGCM8FmXyO+bYLHJcWOto\noRYdNgIFvVI54D9MWNV8bib1/OP0Kev0wAo36eTn5lZhEwIZDLHiurZDPuZhktJqZc/S7KC7H3fR\nRCtd7rn0TZDS3R0hQnkStevCkLA5UtC+eodapCkgCPsiR3r96iH+WEDXd4dVpGVQu7Cbj6FPgQ0p\nWv72GaGLkkODg3PYPqatHLTI9sXFKu72MxDXTeiWnzKnKKAHY0H2F2kZyLCM2Vb59kcu4ESEW0r5\nnOJPW0nPhpqUNouIYdZDlNmHTnCbCM/FSGCKqnJzEBPeyXKyLa4AIqjDUT9VXv1bNasacC5RyCZA\nDlpehsdlS98lHLsbhZxxBc3vcYMQ7DSC6oapQpsLB9ncS//IoHy1eYoLsz1GakYUrV892EK3vxKH\naO80dGN8GptnnSsAYFYAmX+MhtB11qXHN4XNzE6AZbHD9dLQxcGUrZ2Eg3cqpEfHPUyfkb2LDrvr\n7cvBRLvLDql/NLFu/YNzfM+K1nA5+QQ3h22j3FRonDGRk7t9arV6hxJPA6wcQqlLtaX50CPNqYp6\npEsj0aUhBKGd3DpdAk9Ndn9GXRceVc5Nht/my8axEBg4BLlTQYEcUJEyoBmobOfQPXbbIWib1+Tq\nAfxAoY3B+WJgPaqJ2aYxq3hllXHID8GMouGzquBHR+D6R6KblWgXCRFYxrNnHobF6mU+hjWFK80f\ngawSNeTL7euSiUs7mcjudCBn8dxl8nwylfGfJ8JNsvETcivju90Se4gY5dvMAB6JYhXLMvrIKQ2G\nAJyW0TRVjPy61RilnBkNGSkRDOmhU6p/We0oHVPIeZlydpXmK7JIlmPW2SGU/5DEn7uxRU0CgVJy\nVbEwEU65yFMgdz1WHHP1JCRSFu2gwFw4ugg4vNWgAFETUp72M4mbVG0fvC9DctDZScWR5YweGG64\nbdIF+v/MwP7vqseeqQMUP6gB2syQK26FRZ64S1V4U7dbrJOBcJsz2BbTpj/JwB9ba93heSK/kVnK\ny3JziZQc1pdg6KwPvwqNDqlKD8juVx9FKrYGfUybxqxka1kiVhhDoddJEJh+UUGNlwpnbrjFPAOJ\n0irqMW7gm9WKXQq98Jlhsn//iKTdyeS5J9Z41H9OGMNcmpHp06eBX2yXtMjQ3jUyscTko9nBsxnu\n8okxGcz+6CQt0pvmGNoLo8+XpNByC0vQmNfHYv2HKPfo9P4m96DFr+NdMavKoECAR7EKZT3AQAV9\nv02Y7ijyQzZVSa6eDD0pdq8HeRALFXKRH9LyEur1Rn2BO2wAmMusMUr3DapTNpznYN9PF+dK0iQp\nbY4SMbCEhm4Y/Hy4CNHj9qcLalFxN4yw0zzULwpR2TKApY/AR4GDp3VNkg5aMukl1QSKPbX3oPVm\nXGEFcemKem+8FmYnBfDBauAw2AkN5pV1gx9XkMKpfELE6UHMgrp2uh8NXHAtwQGonWsf7OX0ebSZ\n6X7qUAzMXlPJkLuFzcyeh7HWSQoX8qQobcW7qd0MNcSrpRSuUnFKBeyPPvT/T2V6ZI6dGWUohJ+M\nfroZMblr8mYOTqkBadmMY8Ig6hgoypX4BCzlp3y2Vxn+nHX0Nefa+YSyEZMNOsiZECXv5BLB3s8i\nUpTU3UPlF78ysWRsP9GqN5+c3QUHHC5/IZW+8Vsxx+M4q0PWPgybn+hNYoqQaCiihTCYHv75NLxY\nFH1rd4hhO3ulI522EpSZXYKuzdcCDsUB1rTs80lsk2iSE72GIMRg5d/Uc/XHAqh5PNnjDfl7ifZl\nSevT7039Ai2G0R9Uz95u3lfuVX1TSs1N+4dBek0l80Iv0nuJ4giKK+OvbB2wwZkCgTogQ+FOTMxS\nkgHecjdgJyPlvZCwHgkh5cn2HW2Gxp5Y+wSlQr/v+nLJfmLB7jbpmVBUQ0GREBc4sSlycymp5aaP\nKIJ1tyzuNebRPOxwFEFLEAa+CxqIqKzaZ/3IQaDlRavaPPKsSP349is1RUctdlvzf8hO1sOp8AzB\nQrY9SBrbuh0R4mjhdM3o9NEHo/ZP67BZiA2tkfCM5oP4SLinIt+asDM5dTRIAfNtEtqKtbb15jGV\nEKpBfDDhTgjIV378FRWymSqmeX8pWbzFDuDyC9veFQ4PdGZ4R3anA38OvDiXWUASx3KJI7/hYjDk\nkalhm6wI/0zWU2QhCkScn0oqmWkkWRjywXzJFZVq1rfTPkN624DPCUSHLgBVNXtS8LW4P4ymHd1z\nJNMQaRZPkazMx5bFsLh8q1cotcFD8RgpXsGfy/ZaBZCtDJhzUupj8MuyyozzZdGpZrXX2KhIad/e\nk8fqdXmxF8B62KCCsWejcofIjWRBlrTY0GO8TJPQHvzT3C1RdGTFQsCgi+FWH+BCzRuW/QWm9dnF\ntmHi++45xtUclTZZBmQSEGFNUVJn4PSuC9SoixryAnhupCwr05qnAbEOM5iKPPt6PgOSyzKWTult\nxw8Ee7OgjHIRAaVgnTyEAYuxEkZpf2qV7EUCmeFMQqdwEp0CE6w6AuClEVZGjbAY5hw24nMmegYX\nEfTreuRMZT+KSUOWjFi/Wr1D91Je0+AYTi0E9qGXtuXS4z59fLtozf75/u453AWqqiUXjY9FoiT1\n5oLin0Gmc1TR0ZKdUHsMQ0OAPqCg5ftuGFjb9d/Jg21vZkrMqbSn3lXajksV2g2ksCPf+8oovqJc\nmFWbVjXHWJqqnz1CRUaMS9pwFBFuer9FDrr9Ytzw+gIHnRJJxNhTy8LzouRS20JOyMc1FLDIHmPO\nl9UXDBCKuMjqOpssGOFSsIPABHQfmrWDyFLzolhgv10ZvJJ2Vs0X+X+Jl8WigCzo3TjGW1QHYP6n\nqZY15OK8fgQYS7ScgsgjLEgPMSAthK6b0ooYEbTS6LtxuTXV/5B1u1e0ByAdbkuca/ullSmEsGns\ntMo3U5mWxLTNTpDc3ClvujYfbm4/JZsPKFkDMCuB5ukP2jj4RJ/AkFb6oo43BwgEv0cnBwg4+JEy\ny3BMVt4uXU+ZWAcTuAV89B8q70S2euqg7MP/jTXQ5Yd8IuekFkFjzMKyM4uuxLO0TtnhWjxJnns9\nkesGvFdeeDWQBe/aTrybnO0ghml4Gl4iwi21UH7LaaeQGeNH4Z0OucLXCqxdcD7sJWqjowi3cQ6+\nbM9IoUj6GRMDW2pjpUI2qjB2/fuTM9FXAxh+D/QKdS2GkoIcpfEBh4bLj3q306R3GIRFiazACmf3\n6DqW/7jow+8L1RN5dP8UplhwAeVDZcROcRNmnFnoS7Mmc/cZOyOMl3zRbijv/RifGuUlIFKU+jz0\nayMarJe+ndObZQKahwy0g0VIrPQDSkyixq5OUTfoWWlhjhSm9QybDxCl1Tji2pDwGDi0aBQgDcdt\n3TQrvk5c3fMyE/Kxi4174prfjhCqTJj9+mNG8A3+dIYrbZxZ6smNt8BTjL2aEAUfOVnFRC+pHy8V\nYD7ODfnaWLxYiiD0Q90SDbn4bSnsKaT44+zQVTR9sdWI61Wk18oyoYrS7CwooxFIeEUSUbT2Oien\nCJ4orUc2ql3I+1VucFqNRkYZ40/+md0N+AWk/Oes8023LKa6RGk4TG+UV/4kM9RTkPTy3vaAWnsh\nKAJWVjZrCjTOzWYSVC+SSo5vTj29KLfbL1Is/Dinlq6VyfJo81c069yv5gyao06d5H69nb1Tnghl\nsFeAmaVID/U7qvZ05dQw+J4QatMXdIdua6U0verRY6GB55akimByKyqKsFIMP8f2bViOjMhZ4cYi\nnvdH1/vMEGwR+eBoBykn12RmIsVhkFcIXvqG/kZrYmhaE4HuoPMVc/+29zDxPFWoip1McbYH4017\nxD4Q1ndC5X2244+dw7YV+i8d3TsPOEnFvyPIx7sPQizgp1N3Nv3L3edDC9AiLty1X4RYyGoIlblV\nmGrLFkrgm5YvDG5DZqDJ14broQQCCGkHQr0whFnjE92ufgu1/fVnDH0ZjzRN+p0w/dgoWMNLgsQS\n6yVm4oETIZ1bx6R9b0MrIrWMNNp4kpnmRKJL2dKUxPZ0gLV3jNMF0N8uIOyPRiOFZ6UG04FAm5Y+\nM3AR+nskJBAe4UlaM8iAI4Jdavprw6Y2ueBfCTd/dy6NNNhSu61oo469rvwdRHIB3N4FJ/KWKXoH\nN8V+BRfgh2zo1ypZhUxOIMpydQB097DtNUZcrd8LXCJiDAmxINljRQFEnZFoJh5/wxAZfmKoztyc\nuNMhdKNP1S6j3dZfThSdiK0TjEypF2lVZQQCuq+wmxJ28alXtsxCBzxQRVNea7TV+D8ZvogY/Aer\nnIakdksFKvE/0xQV21sOnnMYtkDZc454vqmiZBY6y+HV3iORmFIAcl5/FhmlXyq3UbAkfHh+s5oz\n3bQD+376VyF82/zZa+VO9S7/9nr63PoltjMx7GogLGaQcgJXT1zWm6EsBoap6z3uZL1i38wYAY23\naj0I1WJ07D9v3zR1qrpVHLU2J7viya8zo27eHvz1DKcazJ156GnjohD2WRDMmGtNkrGnV/uVs+rj\nbvCWymaPE3UdNX+8GZKQdkpskBM7S5cUqPgBoiER6f9orLMy9YavgVA1LVT7ZTuqm84rK1VpHR32\nrH4ZOBF71F7I0MS/xLv2vsIg0BgPBtAt4goGdH3jtqJ5xHkBkTYRHi3VEEtY/365mm9xS3dh8yPC\nEo2EGV4mRRSR6zOIEvRnBfQbkWe34V5aJk8OUWGqYZn+EPcRjITZ1gHREvAjog0agq/0Qacm/seP\nbxQz6mfbb/8JZvjhTZV4RvL8SF/n+MZ8yVRgIIDq3WUG5Eut0XNA7QbQlhIN+MwzBtfTnl4hb22A\nPX06+NXX72igEavcUNFMYvngt+ddd/xWfxKbWWRNjKWW/OOTcvb+aXT3gmIQud/pBlFwmmV6eIVG\ngcRi0v0ehue6FhvFJaxAhfeEUh1N7SQF4P3Vcm8Uc+s/zVLqyHP1ougXcXYsr0tKCMJATsBH/JPi\n1D5JCCVS7o63e1FP7/1kNK3jfFb2Hudog8+JGUa7sWej5ZuRPDAPPwLdQOCi2oU4U8RkcYBgkhhj\n7437tczs97PQxLZQ9PX9p4aaNh81PG9+CbiBFBJVOTKwzFK4gJlkafCMVkShjUdlpm9VWxGhDkww\n1AMN4P0yEUE84pshJAAyRGSipLLAA/wATcC0Qo3X+4+HDu0d4HHygkYQJROenvvAcJLDAIrtyY7R\nPU/yUFBBVMvIrgB+G16qMZ92EnZvN98h6AkL6/mdicJ8h6q3wox5h7hIshoY2jDLlx/t0JrIkJiW\nqzw1ijDLAq2WuVSyOeLZaRsE2Qse/Hd8LpZ2LosX6WeWYrlx9hZQXftd0vWjwZHYgEeoz0WChW2T\n61QUdU8Ri8T+0b/MgbgMhDfPMAc8ovOR5Bpyod/FLZPW2upx5N/9kkDyrMQVWnLdGRiAy0zGNyy3\nRFwQSKKXxfGv3HVwobb4tpdStkK4ky+SKyOtxNvvb8GkeUNwPktVL2EcN1k8OPxDQpxMlhvSGFLE\nRnRz+g5yOWuq6Hm/mrJkYN2jYDqGWUeO5PZ2nPq10sxsfGRe0OvUSiEEgPzZOXC1FGH1sv2+jeNm\nmOA/KjH6lBOCrN5j5SKaFyqsV4GU/o1S01asoisTjftUOUoRYXlB/tX4RNTqQ4FrYwNcMnaeel6e\nTSd3/B/M4T9H0kfyGy3BQLeiNtKBW1B4+p3OipWBFK09daLFYRzkfPHuqcdLw4hwfrHoM8AKd5W/\ntG6NM/1cR93WDNRURx1sLd2KqRfm6d30UaxYxD8d7CAMFN/Mry8MCUWiHlPUtHZTnG/DPCG6jP3K\nc39o0Bp7rUNqxVYjBmSWmCBCXoZ/T1f9oCdHXoelE1jS03mm7WHGEWr2Jo3xrnLgYU09/nSTeUxi\njH5bxmUVD2oFtEtExMQQzZrtNA0qQrfqNLCm7GvPztsfbkv5XKD7BJ48n4vCUJnyRd3Rg2h310sY\n4BuE/XZTJ7kU2kpE1u8yPZxtrfWndORy1jvECeXFAI2TCppcK2EZ9nuY0dpyWM21DRGcl1X0Hkej\nnOv5IurJSICBWn05Ai8SkHJmyuKKS7z4pa91ijfw7EVeC3kwJYYCYLmM+f7M6cZlPp4WJPnjyqcJ\nwZhOX5tmvTHnEyurJZnWmbk2ir3vQwyhnn3QdEjUy6u5zNQlXSnvJVEMtQYAZUkORFYCH4bi3Djw\nNJegjVw5Hu8GFo+1CmsHLZuqxHCG0yV9c5uM5beAhB1b8577Ld6K8h6JeeyjBei1vrin6M9Ni4uZ\n/38I25xY4FP5q+SPxv98f7GOvuFARncd2fRcMbrCwZGRqjDnVTyt4pfibn/Rsv2S6Cql2muVifYA\nRDlWg0SNd7SDJ4jjCT1LEQHVDh+DcaKdrm/jaJGdt6bjeRy2iBPmf51HIvJc6vJjablK6BnKJohY\nv3870Tzis5iRKyTEf48Df+8DaYAhY/ZvPQyRz050UZhYBMeDGzPInbGSIJK6GMl8QbpmJfNeCjL6\ndY7B3gR+Qq0uoAYKe0M24gxrwayUFLXx4NJ8mVZH4JcPxA/JawX6ATOdc9Jsv6/y7QX2AjOzxRJP\n8+/W0A8P5q+B6y/N38ykWbLBxtfz7p9gkZ40MyxZg6CmB8sr2hsWCh0XxZROkPGEtKiUzJ1EYwfr\nAthXr2/Y7Ybt8iZyL5oeFZ3Fm5KhSyqosLlD3FkcaXKghXsTuhA7KvRfonDwr0ceDgeHsvR+Rk/J\niwL0j9Q/Bj69rOuR9EU+OczYxmFE5s0YWcy8hXOp36LJ7u7pTYb2EavjGcPTv1XHUUCADobhb5Sk\ndkEjzIuZuhm7RvPivWQ5X5HFF278CGHJlCJNeHZoINP4fotAc7FB1W8gBSVQb6/3W03Y6dGQ/vYg\n7mlAluL/9C2DPea6tHa67CV9izaSXnn2kovl2g0N+SjPiwNC72gZhO78NFsUaEl/xHfzr5LIWv71\nP5l3ZywGJyL6jr0YunPtG6qb+fYbi7+TD/0v/zI7Zh20WHQlE80AH+yHSqffjI5HwChj2YxM8XCb\nJaKhzzbiIIsdVJDUY6HBqkLdXpljmiS1xPkfBn2sFVrNU5wsyD3vQ+S0j0Bhevsta5K6/gABJ23n\n8YFX8QWbJ/2hvl1UrD3O2gZUTZa2sMeIOTVs5zDU0a+F0nenD+dZdb6tVxa4jm99PQdkQqYvIuiT\ntWObfRb2Fz66L8/Aj0TmiKyb4nkR9dhh8XsUKXTZQ9GraKEvx7p2kaQxeq+dltguoXAr3wFZojWG\nqFnW1B0z22Rmi3sFRDlcUwYyxte6JXtl+blt/3A6xIhIntRxQzeyec1iACSNDmB6tZA39BfymJ5x\nLiibpUmPEWkwzHU2XR13GcP9uAD2KTXPP8aQWSNoOdhLbw+zJtOA4TIaHFSF9Ht5IkUxjk469VV3\nIntsG89n4yr2dPS5MmRE9KVwVUw0zNi4hkKvEY7XVwwA4qwoSmqsAArBb0azH0Zm31W5TTgf8dw2\ne8g+EPOdNFvA6v0B6+Gxs/JilW3Q6GUcX1WlJuqzyTzh66xMQFMV4wbLM9+OMMEE4/I1XfjDfevq\n+4MREiKnsOxyCXDkuXgghGYbGZJMcFKySbva+gbrYCIykQqBWFUauxGIvAlj3aABnSZu2ICMZBr0\nXdBc00ybLlMzXpMwg4VKBLW2gP742Ib+MQBCsTMur1Ipj23xWDlXyISZeru5aTHQi04awbwW92k3\nI87ty5qQfHJmhEXHplMbLbWcDKB9kGoaOrhCZF5o1F3ZXdpVyrU09VgMHTXrODuGCBSUYSlotOm+\nry+eNg56BitUMxhlDx7kCc604bTwLYx/5qsw5OVBi2Hbl39NZMnIbLMBlhhqt4+pfxh9eI7f5THZ\nhyH1AULYtl2uWe/i2k5JTWCiUihGQIEXwPA8a6f3Fgyh8n/sfUCbfUJAz2cCT8T1Vo+Dt7zn5Cf2\n864PQYlFkPKr6Z3s63+GUqV2qAWh4+ZeU4isUNbJR0jiIOYfpxSxsHnalep85pdMUAjvM7quZwv1\njQYQCseiQov1rdUaOK+OfzP2rVIe3B8smmZLX+3PbSTO6mBK5AjXuvsG/WvB2/nNjJh8vCJuF3ok\nYxX/dwv8qaRpgLu88xeocSi+QSEbnZ8HJJj9Lx3PlA8TGJSaIC8LxeFoa+U3U6ikW/euqLICWuBY\nqnusQTMAvHGaeBCT/WTpKpwPFs1uJV4uCDXKQio+m7zV18UIc6kNDCI3aDzcvApA7VfWtEBxGxBP\nPrmM8/+KavARTEojYbMewi2yIf0Iq1E/3a2R9d9pHOs8ruUfGK2JD+N50SHQY0dpkOuCcYXWnlrX\nD5gMvIO9S/y014SvfmAt4529BB5o3o3ZqCw/8T2CNdxabCzJpneHL0oviWgv0auGrOLQQXVpb9hb\nr6zhe/R/pPyB7JDDRMt2O9lGOpIPmHNyf9KqejPY9HOnnDX99xTaui886xPtDY20a7fT+VvAb+/N\nX4TLiIWyzlZJOm9zSwnVkSk+XAVhSRDAxv+e09GyQh1XjyVkviSMjFDzmnv+udFnl7qr99aimmvY\ngHwClGn6LUn+U0XHAIQlY+js/1dLBlLeqG/QgMKtbAjp3InPQoKzL5wbreShId1n168MjlZxZTAe\n6AoL1D/zgBsRahwvU7aB7FN773aZf1rAU7tJvEtWR5Bz6tF/oQLLRPKQpI0YKm3iTgIWpGtdDAs1\nvf/9qkqz4tDSf8/U2dhC/KXWn1zwizoetIJQYEAAwxUXwhCa4WB6DMFldc+6wGfG6eEeFXuL5f5E\nqoTAqmip+DO+1zv4rYMx+yPsfKgJF6WaLKN10h0KCx+Zb7NXp7SFURkl85RWVZwg7V/sJsg/8nbA\nG0H0M9TYq853mTwolxIFiwBlA/dV3AGOSWPasXX/iiu/B4BP2tJ2IRZYIPMAsp30ccweK+1ufn9D\nESLGxbdNuFMeKBDX6FYJdB7R85/hZ0eb48tNlbRHb1sXs8AJdUm+uKQtH1tg+Xb51CDF1B8zX40d\nk45qWzRT1ewV5rsxxw/NowgHpyto0sAd3N/FacAc71Lzadoj0dcComYxxIMELJFAR2Wq1/c59hAJ\nm/5tgh9IAcgF2oN6Z1I3Tbk2Khc9RNidZ4tMxWczj+sfnaKkthy+LaZy966KPke9L6zi6g/phVQd\nH9cROHv+tqT60UDpJTQCWNvunuGb+duoLcr1DFFmBMuqL55M/Tp+uiTPX6C4Sllw//OGBdvFltcV\nuaYNvNLPbC2mr8QRt87HJV9dnLayYOjMP+vPccBPvNPERj8rOSmUAsDPKpa9DOZTz3Z/ZevIgSmO\nzl6cTGARfTi/kqjxQuNjAVXQZ+V4vK2LKK0mL6+uiZMX6dDpz3K5tXDqKGrl2VHh5FYalkgY7Yq3\nxaNg2zAmTu7EVnXKCji/eBkMGs9dhigqbzX2SJ1s8zdu5kOIurWTozaylgmCJg/8A6ewEva1ry69\nqeEOXJTKRL0ULCXyWoAJVmioNzAi/8JN8zx2C9sTrX6VkMM+Evo4pcCSdtjVGQM2SGD/1aBv4I3z\n0Ny3VtAGSWVPQnvZ8taPByo/n96XXWFzAUak6mqQBfNcoLDVIB9LYnwlVq8tkTa3lfbfsJgeqe8X\n+fM7d167d8i2/DEhl/FsevXKhMlieTmhBHOvPAvzkYd4o4ncaL0srtsl260THCDeGK9TVufAnyJQ\nQn2xxADnH3a6bA8qoSk6RJZ4rooVURW1eRR8Iyn3nR4rI9dMWNYryASd+tdVrWkz/918Rt5aOXzl\nd3mDEUlb2sQYf5aLMTkqr/1RSYPssbBxAfZNKvTgg6hiMv1+BD0auWzlHxcoB/JoeAIvOdZws4hm\nzOUVzcYRq3Au9w4Zle13Uan9XHtoCswNYixUOmXJ9V2v8J+X/WdDlq1huCZzhtZRdMZkUbicsZnJ\n29YMHs4FBrkxksI05PZC0qYLStBKn3GtcdqM+a02poB6COdDf7IGj9UPoMx88zvJWP4fA6MoOBiT\nE2GE7m45kUgwpinWluB0CrQlX7wWOkc2j42jrFzGeWvmPactbIddAx+paBBKBbQiV0nA1oLQd0QQ\nwMSnTMXw275YgvG25zg/DBX1tpiEHByXINF8nBqh8ut3hRh1ayGouwA043SLrFHsFwoyjGob1+P2\n2zzfkUu8lKah/G/bD/YIdMPBYZeEHGD595q2E7x2TgzcP/KnjK9So6qGCwYhTw00AniNxlPCMV99\nWNqcvSKU6yu1PnkknVG1OCdIHBZNpnm56jeA0xp2nuiC/DWn5qYCdhGnQ20o7y+qALHOYeKufwQE\nKeRkKByoIpXVSgl9QMIySkoDIyGmXIZc4bfmTL2luMfCr4UFJ5/gUIHDy0+8lBAgTi5wcOqb85U2\n/Qv3KaOEjwmq2+zyV7JC5gZDIPafmyg+ZusJbzC3fJ5jegad3n1kdx/px1MSSNn1TYOMjA6RiDiV\nt7Do1p8VvJCyD+GLZ7AjDrFzaBm648BA28QYey/zaUwi3CYCr4PZZlBpglO0qEItEsptztCctaoI\nSn04n9mUkSLIqVy1rcYAEIByEr3dBF8316nwhQmFYSl6rPlWctvs98OyRhehRnx8n84g9mzlWoPH\nuaFZq4sE7CK9XqOpTced+I0oXHFHZGOaHSNBtaZYuJSysicURuPE6P03f8O64cam65K8Eouk8ptG\nkEERny2tfMG8QD6M64wvuwi+sJgOp/Ojt548oCgFhy/HItP1w5FYeYv1PWOpzv+GMfOKhUgoPQ3M\nhrkEiR1ltitbKI9RzuwnBXA+JDpkKvfF1Zanh4WXN67FvW2HLrGtAW3hkMxIva8F9iWe1lD/Oy1Z\nso4YJWefUPsstCiFu2RzzJxiZoG2xWWFyCFjik15/uw0JtZMmBNODSWx1c+l5Nx0nit2QV2b4Jjd\n17To84FrxH7nXkTpQRcSwP0oZcqgOgh1m/baWL7rf41FeqSteK28gOdgxzfppqTFg4TncvS+Zxpc\npauc8T/Za2oxP6rZKQw78NFxNumIrJA00EmXRzeEHLVHXvL39emtrkrX5s2g1RfAfgI+ysUTNb0k\neVavJNrBs8kj6/srwH1FEDt+myMG934uGNqrgw9KjYqvQ5jVlI9U1TsPII89ZKZEjdecR7LzWvrO\nYRVi58tOBmDLs/+PG4R1VjZIJwKH0yZZnNR0hp8ZdrWRe/JJYuy3Wn0v259rvlZJwCBrTdxZGwL/\nuGemZVrFwuK7Ip9rnj35XCN94pQZsErqe23fCTItrb5lSL/jbGm4Q15kfgH61RruuTNXUOG5OvOJ\niiEIvHHLzz3WUSEyLaRZ/3XiaxgC2y5stu3uN+13MdwudwLqyh++S3tAs1tftuzd+BbR5bIJSHzD\nok6svUxa75H60Tr1M6v8yILerpdLgBGqDeeMqdNaBZSLZsGx5eMuA42cnpurAHxj2Y9NQAR+yTL9\n9MNOKwl+sYiPNl9y+0WGuSqWsMm4W/640yZfIOsVRqkEHyeth1Kk36EF+26L2doww0GYD436E8ta\njFvE02tkMthIhlrhxvQQD/vF6nrqfsbJwjJ37XNIYTMJ5Gd+P4xabQfM70epdsBi0K+sgIkTs1Bj\nyM0sE7zw39fvZZXsuqq/QITF5t3TPZxZIhqH0j2KGRJ3QzPBetbZXbGwvWv3bRaCPfoWsQcRegUe\nLMuNhOtLBTBaSKfQ6YhzK6IXFc9eTQJJ2yremFcCUmSXPZ4DQ7kZdU32mVtx6o7+q+sORC5mYYzV\npsIkzEvSeerbKz5FZq3Ydn39vffxeyjuBOC/YfMuOQjJauOkaFz390Vl7RpXiBiH/T4Ugq65iMl6\nmpJJ+d9HhfZfpiKeTS7MTFkVCL9v6JNKsq/Q+f83oZIMJrMMz2hGfP5wJxF5KtAN8a7nzgAiU11H\nW+ktgaxp/yMSZX3mzc1Zu5mfEGIiQ3Ok0sEc4f7H81QZA9fYNry+KC7KAzDqDt/axyajw4s4IreT\nBHFtOQyR7r9kz9ctQlyFZ1r7haaDX59d0KMRGlkvwEqbl6WWKfykxKR/WBOfXMUfJMvoAKuLAbwr\n6h+wVhmnewmmJbqeS/duL8dX+J9RSUs4KfigkRWfjiKM9NZxNcLILI7YPtifqruGRVvb2jm73b98\n0WVXo72xw68dBsDvHPalVlqfBcIIidd+s0IOXklSEbnoWys5zAhSQ6Bs+kLu3BBynMP32oub41Qu\nuXqbRRPgF6Mi6ZSeplx5thCHU+SodfSPlu9FVkWxr5XAMp9/OZXwdCmDl6vcMwek+I9SRBEDfi4J\n9X166oYgHWNk5tzUf/n1h54vjISq3V+evbV5oWm/4PVGsIqJtzgmDvicf8gII176DgIg49JFls4z\no05OzrTc2NMkOMLak3Wm0D2lJss3GgQGJ6dIZlVGLvzh9L9Ynqd3RcBKEUd34937W6/aQzvPykRH\notvtNSSSS79hPOiIqWANkzzhT9eVPNVbUVdrkJVf+juOZHk4JjYtzVQIV6lCFNZo7/bIZjZJsEYr\n2jqvPiL+N+fslqdyE0h08WgjNr8aEWAXAilN8XZf8BUz8CTATh+uS3f/ReGqL7/ZxtWFIwn/q2qW\nxCOtGBQ8pmigx8WA6/gA9m24xwNXAdbXVrTG0zMO5TtKrPjnCf5Bb8X4fuJUbl/SgatwCra08q9v\nadCGGt0P3C/tOLsZ3OmAAtZsOh1stVcJXz1E+i+NJpITp+01fw1/Z0cU2Y0VNOnozKuMUvZhHBFb\n2rBWzaA8cBikqrts2Kwe9OxBrwuSK1mInbokAF89xRwq7a/sfIubkXNr+9qWvGoJThTgDlJH9Pdo\nnTQl+8jnS0qugdortQLrvrH1qe4sIzNRCOQ0ObFK8tJX3D7qGVOj63m+bDj14hez7INqKjoIcEpd\nhwyT3Ts2U22P/on3whcApzGjwbo8k1JTIXJTvjKTWhDbFYWx25gl1qOzsjyYM0dY8/wOkgBq9hLA\ndbt1KhoTJ6qIsimVocXWGHrM0LzBfST5KJ55VOSBSnFOK9k/J3j7hbiUsfRCHtHgtpBd7192I/eI\nwHwOMFmNPfy6OQjEl3ApSEHkTy4g+sOfz+/BpyYL65C9kFSajvOJr8aIe6K7kyDDRVdRkj0V9Ykj\nVo/sun8VN2nXxWmAwEll1SRQKMKap5edkm9cdlD0NOJx7pM7WrNS6LuJldweoQozU1wtuYO7vLF3\nyWBzmhgq2Ek+U5pzaQjsTrN9/+pvMFi956qzOceCIeK7fAfXcJW1dV/Uu9zZ9EVO/jK9ftIDTvae\nKbGB5SJb8eBZLacX9/dbbxjc9nc3Y1TfkPNrMEf1paelLAlNjbcA9wGv4Anf6lm2wYCVAU95QEt2\nESmxJu1Fe2k2igdBBDhuTN5h3s2Z9XobwN9CwFNqa7vH3m8HwbMQumFDGR34R/LK6+o2r+Hx9MWs\ntKhuCJDuYjWe/Th803JceVIX7ch6/NLu76DmyrT1Rja+Hn1Yhaax3ychQW0vttyW26h5DbiZpIXf\n6unycRkIJJGKchItntOu+YlFVyl/qt48D0L9b6FQ3WEYTQnw/S/t/oMeM+oFtNFrDZmktbr9FtnW\nvLXEJ2d8zQ9UIUjjwnJbxgNAyhpnZ0af4uWO2++KBj7VwylYK+f/WOXsyBE7zOY1nDPeZ0/i3Qte\nFSq4ne+lOzSbdPZG9tLU6EvTIc43/KchEyjJvqqfD7kaihrRW/zJoXUuTQ9iVPwTlEtlZTNQ9tZQ\nUPt6TqlhjT/Z922UDJoReC86CaBflkSHb34hz4VZv20N7rLA+T7qpxKtXGZ4bBn8fP/E7g27x4vn\njSm+fd9RU96tVUXLHoZxOHHp/pJKiLg8mkdpVC2ZLYhcEL9vaEPb+W7eRJP0q+hKWc1xusgPmhr8\nFnEs1PWzU1WTK8vhlGNxMG8o1zpxq5sdyLk8LSlu3TpNcw8km/zjlByLjg8a/nRqNWU8+Xx3nqOM\nMs+ifaXltnwVshjJQdI1f23+qmTXsSOGGFIGUGWFxyFGOylN+4RqoohPFO6BZibIHKSApTBCFDHF\nOWG32Mx/HAGizhmrWF77P5Hks93Dv5mNrVMpu9Z9WEPtgdodd3JxZdX4Hiyob7u6iuIL02mLSGyN\nlVO/q8wWYwld9qLxNSl8K6+pRjCTqmAFyprgzX4K5jXQzr5J4aBtiAnZetCEQ2W2z37g1PrXzskN\nx65MUWv5yn20FIWMDpscCzlLDfwboa7UARTignZ5LxkMxkWmwcwg5Z9akeVuvLv7AQk6OTy1YbBX\ntr+gsPimqJO0hg1dqoA5AWjsXqxfXU8lAADMgoBR0Pw5akF3nY2CJJmVKFNY7r4eLRnLMxrI1LDv\nowtWg0K/M3aEku2r9BuCDTj10M0NzU5axxDrKtRS6PTx4SXDjsowtUBfbF8ShAp0frQxewGR32cY\nSqw6KWrkGNI6FIX++PGREPvvPaUf3lk0hJIIa7hS4WsrAQC8S2RAvLKVSHm8V5L3mW1H4ke1Rsw+\ngyQjSq0q5lPawofY8NT9oQ6v6D6r1K/7yphrfvesRoeH7uDlCl0Iot5AsS+wFQ2t4RC7plY67uri\nfangHLWj0Ez3vvvVWmtJRGjsxCS0qZsfuAEvk5t65A36YyTALSajh6NEx3MMNwKq/7LjRv+UvgeO\nC65DmVZl57ukOTf7q8JLEmz+EjbsVSbj7gJLR9i43Rm56OeVAXRokoeYewK5OuSB5/VumytVDxQI\nm2j+tWJ4ztrkIx8bVwI8WlSl0XSASIWLD0qf4PbgKHeuQERuAyNiu2u+jTN871Y0Nc8wMAptZdj+\nHbHfr1zZhSOFS6WRPFFK+skWAMXz8QOPrU5t2eWrrvDZ8apcbRq9p4E5grn3hBYLi4F/Y+mEi1N+\nXDG1P+a7S4auKl67MJPdG4IeK16+JZbbi7llcvm1ZbH2ZvUkEzaMwSmIvCgR0GLH8M6CbUABeogH\nbEpQvrdlmt/iCU7kovU6KX5jNlHhqRBgl076r+lJ2QxhzzHba7dt/2cg98Eg0O12iDjKycewvljN\nmuTxeGP7kmy345VJmGb1SAOAzwLRMH0583+ympxhg4TncTKHv20Ng9moU/9wKyDjhSn8+hE6oZu4\n4J3Fqq79BP/5ZNV6m1Xng5FiCpDGKmZzbizOt5rmvbYxOnLetprqjOfoe/mE7PZPue5YsLWOWZ6y\nJEA5yRSnuyKSc2XjEehWuux83adoxpaEXVztTfzABZEBJI0ON2VO1dVenazistw12f5TQ7tBYwRm\nbkke5IpwXN4/WvA4NlvSK5JSRXuOzGLsiRjbsKlnQNNSI6e++fIt0A26VTBrnRSWD4ZrOcFq/Izu\nGZu3wB0YSwZE3w0txYkJnw3smQHnFRmgEp7Y3E4400MUvadfWGOLFm41AKu76zF+imCAsUf30zBq\nbsyDakOduHMxi2UCKQ77ZRidHdgR1zAYpyUVfavJvRR3cLWP635Br+7EJILwBOmtAW9c1tGajrOz\nlN1SuPcIZpSB8Vk16kkfjCBtP3rFrbftNrKNaxhgjhoGVpyYB3t9appddTDS2vsHywtbaepg02w2\npcEQeI+q0yXRzrFBB97QKlfiFRKcIuYuBtiadRTFmZAuSc2P7cnGKvhG7zyPey3T+7Hwv7h3YwXC\nhpPkS8eJWENx81MntFwdRzqmoFdYoT0koUoUSB8YW53L1RbHAVzxsiPzyX1WHDsSEZo10QOZi/7d\nRYHZ7RqMY4IgNPbWcp1onz4YXXi2B+gzu6rUKFFCsZgBRk7KLMJ2F7GLhBtZm0DaeeHaS3c44eDB\nzi/GSXbv6Fm0Fo487xPOGzjFIK6BJYeFBvGebK8OwBo+yzFh8eUEUk9oLyUHdcC2X+biP+7ZkqZO\nStcvHAKJ0HCzGoQYAm11jSQM2L7dPE3AC9x96UHqqZwsw0UjZntRZEDW6cCbmpZ6WShL7Iw3Qrhm\nCy/HT8PqrGvzIEn3PFrLLXkx72jnzKaNQa91uQNWSTyYrptZcwtKKgr5YEl2YFYgV2t/FSmUrIwm\nVEV7o4rCUdq+G1T6eyenskL6SbBtoJZkr5gVg6Sh8Y3Z958cQAku20YkhwIZ6DxEwl0k7yKVLOi+\nDv/m8NDVGBi/sZqqfAl+CIQ2h5bPZXPtmhrOtYRc/yNReRQwI8lku9+DIGfQJEbrBxhJCaStShQL\nNOAj3id97NRTZzX2rcD6CzqsFp+LuPm/B2pLnPXuwXboCzyFAbVfiwmnqeysoOqWiH7tw1Lczvr+\nnUbQmUpxDuusoSJXPuJPVGhn2MHFxN6ay3B4Iqy9KW0/FyZr6amW5sslsGqRt9JH7kQR7dC1cGWc\nP705SBbrWeuIllbLnJxNqZZM2R990rWDrJP0334fdJXmC5mA9bsnvaA21b9EzLMkwqMaIsckcWJY\nw4r8Z/2i4+lqAvAFYBbtU8V9SSZjiu8F0qfX9bw9CM9ofZy7gRfOftSglwFWR1SEW3cCVUTqPhDv\njorfs/I/tmHOOzXqlry0JP0jAoMZc1TKfDJwxUUcTe/sfk6Srdni/PyeETFl3CYM/tJuTY78tqcC\n9WLCk3S3Xx7Yv5RadC6LGIG13ObLgtUGyPeblBXrh9l3adUMiIo7yayqpo4Zr8YXd7XoowFogs3x\n18L+xOtyxyhki5E9j/+RQb+ZET/7AaV9TkcWE4azx1srTyAT5eKbXFXscxI3Tqhe/WdpSPpoQdxL\n4kRDJwmr4ERFFTjfKtuWhkTAoX9zbC2oh+BaXtY4+0BwIWeV4NOom87rmAcDT5fb/7G/UtFTc5sX\niPE2aIdrWDjyB6Tm+SgWwdjUp+iClgG6LHunrEMWONzYLYiLyqVLhJZeGFE/aTtfYHqPV/tLCv5z\ndUy1pPcVIS15w5GYxcnGWYrvb3EW+aV1UbWm3XQFpCtAjNU+zAapUGAzEqBId3/aYD+ncGwfNYpC\nldOezxVD2b8E3Pr9WMm6u60T+lzix7HAjVyJ7qmtnN1s6S1jht9urz1UPEG9h4cT6kxHlwVdOFwn\nyYEKOwEE/qOEBofRUEgXYj3Fy+uCOttXCpXyU+o+oOE1nba8sXJ8ogK2KS2y5SxQtK8DBgUgchz8\nXQ1TcP256crKBoDY+oGisKlTcN77n/JpIaBqiFAaV58wLVrSgK9Q9OQHoDz0YZCkd7GrFOJLat/9\nRD6bwu/KSEdwZFiCeeUPc37nJqU/MiV8wcGhreaDCW+f/3TbpGWcgJ0LN0Epb8daC5b/g7fuy2v8\nkrwzARAimxqimUhCinB1n+IBDUWf5qOK0jtv2GT4kDeFpzWF7Fjd00TmypKLuTooYHfKHddyqJjG\nRgD02PXgzUI/mp+EMY0uxRy+us5iAdW3qHX8tiZ5J8f3ri9ywMttJWoKKJ2JHQqzYN6W6O5Li8pa\n/5M3wLC0Cz56a2D9Wu1bykp1/mEv4PK00HvXT5HN7OUYDt3Bz5SCYnUYBruOw642H1qSCwbKZ5PH\njXH7ti81IGlOdHdWfuiMZI5PnpiJ82ygPcDT8PPjrATMl/mupdSN1J1zKoykRrFeUyAXN8ZVJxns\nrzeWm22b6mRwGup03D4xg/9O6xJ/Vum8Xyys0vJ7iHvQlZkW4nI+pGdQsjXhdU3Hvn5ZY0fDbkT5\ntnHk/SEwfZ2TRNUwWY+zkp1JAUlk+5+iO8uTpaDC9IQSElM+c4K6cQcoYaNpbsUdQries75a/ii5\ny6az3XHVjS3s6ea+4eYtPCSdn7syya9O705AQv/9GOFZCVS8bGsB/lo8QmxTJ5jSbvaH82XUF3fR\nKG5HC1JdUUfavcy96Dwwh1wcaPBJCrRiQpBKtx8P0HdyC8U4Iy78HYCQMIobHpjpV8Yd0mTnp5X7\nDq3++jTqky9rp+hhtFPYLBp27pSZtADfwD8ZEOE7LyWkDIqAx5WJLUTdvrZvVQUzp8g4l3G9UJTU\njoDiF7Pfelg/QepqcKH+fSvogeW7+i/CvehhUi3I0AZG6Bs8dAA17NCjlwAcUNZ9RvdU1sz5ZkNQ\nBRi5SmtXNmAou8b8JsU+ljV1QXRKQN1AHg0JnwyS5pdrmoDluBm8oA/QCvMdfR8OyQJW02DinUqU\n1WECyVdBqgfWyJTlKVfVCeBBzefDm2AaGDpjCC+bJ8YKc3+n/MulJh7yoXEuZG6+1PrgXWjnQQU7\nV150538ypPHcnjVVWBn1ylt27wzo9mPc+bC0jHFKQ8NUFFBFNGQVPibQqc1YP0knN66hW6syHlpL\nHc/I1tBaw718We5QMNd2RknnWo5Ic2X+BRHV/9GWry405gsVQ3gHi4u6ha43Tvq++KdH+J4aVhAM\nHMMEV3BbHjTxgqJ2JmU/2bYiTrEzm8PG8pg1baZUyg/c8b+8GSPmspaTDslJE8fkeDP9xxIvL/5Y\n2WlcrKpl7dGNeUX9RtQSfKoycTOWK4zZwzK7EJzOjXyDaDFDTnaquPUjYBLFEOWw2x7Qil7KHlbn\nmNiOw833KqgyeYDz5C+oOA0E+wiXLfalFcxz49kBGB5i0rc4XvOSJFFgiazEcjuaUFfWnlB8HRJi\nB3PWZnyDt03E9nBugA4a9BEvSoCgDLszWA8B2TxBNJIDwps5OjIZMMQR1mdbRX9vh6ldg+n1pbtC\nBVN9yxXWQdInB1fnb+iyt8DOjXmzgimJTyqzQ4lF0x7wja1IQACkJauRaIyECOALLvVC9MYmuhte\nbv4opZOb0yc4wsz5+7cLDY07/05Dgp6REtAWK+5C9dF/LpIXXSHi05/f51H15xfrt6jJ5eRYlEXo\n6ht/zFiB9qt/crcX9KBrVTOk3rAoKOwVm1QmfDv50IuVJcfFIHFDW0RU/4KTsny34SocDFB3bnHS\n12p7DV/O3idoDOCYPeQ2hq82wXPDNT9o8kQ/UoSsqur4bLJ6S7OYIObTKxXBUboBAn5YCLbKTEO8\n44vzKPa6l4ZhsYkF7r6jcNhJZ2E1ii1ECFe2OD1Up52xYEk4IK3hF2FinG9W0bPe5iz63dVPlCnA\n1sbi8r2bMepk4tkiEFOAftkP8owEnctzIgi2mY3cnhkF4EyZaRzCZ8Mwa8hinj4fX5K5HbCxVeA1\nrWa8ENjEms1PviQRX4fjqPBvQIR1cw43lFC6CmmEK1CXUkoMpLQFdBWkytmJ5ITh+LLM7+GE6gOx\nCNjuuyrKUG39ow7OfzkLXMhgFLWcZOOuTXetAg6NqclKqVvnk6XVANUntHXWoQKZtJZV7F2/kVeM\nc07rDcE8xGQtsuqc9aek36KLkXKdTLRgwzWlACknKSUZXOQdK3LUYdIM15/SujBQ0VRa8fVEIoZ3\nY+k+YPUomMJSPzwbL7eVL9UK3Xsd+HVNW2V5EfCtg+4KAPCPp18aO6jCXCu844EDZyLNVbB/DT6o\nJrBHMCZMe1RB6qHVxcGV6dIc9qL6D/MEBIzuMXF8/oL3iq6hldwgpEM3FkSUHlLjGNu75x6NlB4f\nBiQWfNPzYTdUXDEL2VzPw4dzkwGYCQyRvEGu0sbaHYIkByG4Io4GFfnWtdEXLh8EnW5qzFrEQk3x\nEei1zDnaLbdGaJ1IEfoqFkUlKrDp5+njooneK5y8MCt/8jnSljR+drWwSwSADWha+iCy3BlKoNPv\nbQRvVELQufzAe3vfmjjb8PQ7E1BNe1MWXQp5PVdYdGbauxPNubilT6FCn/WFjbkhH3yzFly6Xzp1\nS05BgHAWemCsnQks481SHTB0bY9FPzUwFvEwbypXK5DlpnNxArAmnB6RVDSIZZfQvud2SgLA8rI5\nIhaDPwR7wQ2s2TZa9/vvqnl2SNLPAy/fNPxaqy+yN8AsYeshHonLst0d0GIZ/JtVub24xJ9mUHZA\nsIX3DXswa/frmvWKpgMbSPMGpfSToW4Y/0k79UdPnV11W8zzMWs+D+HssBPXsbiPkhupwEWs2NG0\n4hLYgoPMoi0BLloYyFjSHwwSf00T/uqnWbpDrnqfVaC43fAgjnzGK5PEfmLZbzQuZKRINEahlVEy\nUSDkeR0GxrQoMoG+NypL8wvulJ1ysYXRXHPRfQ2Obw9Ofoi78ZRwd0wT2Ezlw93AoAk2U8dMvh/Y\n1sBFACXkWb2Cd+LjmDTuuo0+BGILrA/Czg91pQjyvJNhljlIwOYY33m5KBeoxKAhiFCpaWzpS1jP\n16rjatUUNvQczxTvKNwsZF1zUZ5FYm63RSyzu7GHJ/YFmC/j9eBUfBf0J+8od0D/HHviNDdUBGia\n73n8N05vo9241XzdfuWdTaHwPoZbCrLFD0yxTMFTRqDq91Z8KxavQ+vMwID2hPoQPXzTr/ocCQ6m\nNN3Qvv7kgVTlzoDveZZXf488rE95FICUSv1CrAbjG6rhVClqPi3fMrQc2aleNBozkwhaRyR0sGPx\nqPvRoFFRfnVA+8hopbXZkhDL13aZ8+jZs1EWZN2A9KB2YoeR/GyjZWYm67y+XYhrZk6UKqwCSKwe\nvXzjipWKK+9uOVcQV1V6tUetrotCVGdsT3vEwiI7AIN32hx4OTkp0CmogNyT7BUau0j2SB3vDjZ0\nPUVCOgmRRIbdSEh+HJA4nkwlmW7QMp5lpJMRUAgWYcsstSxpCPQw6vQrd/kj4yflngTtmVEQnq/U\npIc1qS26zEwxel87kL+Nwz+fv9tU6GyT2Ar7tWMWFwHr9xC6B5rUUT4S1w//RHpP/N0o+4LAX9zR\nq0LC6sbUOz6YsSKp6Z9a17xWl6SggV4KuVq6oPsso95+oycR4MOen7632XIm4aj6p47NBQjfi9Gv\nT163iv8mwB3oCxkH/fkorN8nsxlBVrBSkV/XT3syNECJLix8/lfYdz9lExa1MmQYvbgIhAOQlBeb\nWKgUuY1R/lBgodNGj8zJ5FihgOsG54tWK7Rbuq5qViK+Ng7AN6me8PT+O/3uzWiE1tC3hc0MK0df\nmw70qnnbiaD10fa2KL9lYmBd+Rhx5LuDH6wPLf+xhXJnFMDbxIk1NJvMUumUDQxdQKvc/+hFY7eS\n6BJmEnTksUTChxeHIjhdxmf2KkRixjc/yH4m13BnLKh1FzEPwBNg9nNeBB8AMMJPRk8AhRQepw6w\nVFqmNDX2VAjk14mIlZ1XoOeQ/xu0N0Sy31/OThBmzjQoSeiI8pWFmnLwoi5fUbI4f9vPJvDYgVW4\nVfnANKSD42Syeuy1kkmbc/4uHRfcTrZ0HGvCgo2PHRsw9Pqw27lB9I2fbbDAe65bb8g4uBYzHkFP\nljG9XBG/EeF5eUVH6C9+rw53JBPTHJrDUm6TRPPCz5p4d3Tlxjn7xptCtg3Y1kvhkzzHkvoH0DaX\nMpsCd1MFZQbIpgVt+4z9HzaEH61Cs6dwMpEO2M/fqXS4miVbyJ/2Jn7jOWlWBQBRAhsypDvHTE7e\nu+Ps2xsknYnvEdSEa8Trrv8aiUC2mu6sl945J2JdmrpOobkEPbrXX0K5RJ6fZ+5tr0jONMKQwjFk\ng8u62bXx6hFFZ2AI+hDv262EFYl9Q6vZhGiWa/9j/Fe50+rQnkc3UVgtbjExpa5hzbz4an+CY8iO\n5xeh9mzXlG+gby+6wWvpMYyORDDpPWKc4f5XTxY3HoPIT3WzbvebQ4nlvN10laefPz77Ib5fvons\nvROcaHGIuD+7tSB9WoLD67aDm025FnNsNB4n90HcurG1EpXcjfYHP5BYBOyWJ64xl0ndKUJWTAnG\njyCtIBuA2OzHmrusDmtGyJ9sKr/iILTq+eVSoj6Y3xU7LzQOQ34lmy7Bv7EJsTN3w+3O+iU7uHxr\nmR4wJPHNx7mUanq6+LAwS47fflwAuvE4qvZdbM9nnWkoGHRAXD1qrkpn6fzl5y+mguLAGmYH7xNw\npJw5JX0yC8xCuaLwXu6Ko+QDDdHd5TZOe2BIkh1rquVqev1ixhAuUYiVFqbjC/UCjUjDc33GjVFB\nkk/crACodODFH00fXrlbdHy6JvRMLQIK6PZL7C7KKg3U8fF4PCUToAW4ra3pqs+Sk37iVhTZYr6x\nkSWLgDUUbk9gvdtgjr/6KuXWudQp592EyvxxLCyhat1Ei5mKVgn5oqtODGccWj2UWNIXMm+f6HZX\neR/WniZzsZwS59N8DfTZU8PlGmYFi42NQmQu68v0J6Al58HF+JoqkkCufrEWzerw3J5LHxdL8puD\nR0Ya80wYryXQcPkPo8B7AFh6qKxnaXSJUwIhty/abydQPgQ1gogSg5/ztjNzJ7ildvcciqrP3ykE\nRCLCtA6bb5DT4JariJvjUc8RDvpNZ4UmPoTAbgwYb9/LeFCyENtEHJB9fvAE4YbxTkhmQmRmYPo0\n93qZ2/k/mNQ0FvGFsWOABFpP5kUYyfs/K07ZzZ+fOpoCO30LMzXoXvj6DPoJbeb4L+eoHBxytMkb\nRF5jW1qt2wywteUfsLpbEjtEeNLEg1wEZZl+z3tRFAGNzH+SXyh2w9mOcCoBESQ5zInlPMhSOlXs\nycFq1ZF693x5lKd3UeU4zWrzkgut8KVDklVt6oSjNNrSzH4nJaUxNtsdIFKdWCK9VvCzBl18Z61B\ngYcxuzodzd9o4bfGeIDTrOP6MjX6NVM6pTtDOjAoKdIOq1MlfjZaqTUUrBFDDn5GRCSde7H7l0Ue\nL68SNkdvimq7R0kC8EnUCnp3YTbGBQBf90GeZygBdlcuLmHBdkVGYXigp7IXvzBtK2NDrWvBmpfH\nEJ1yE4qBLT72aCKLh0/O499CDz6Bia8mtMZFFXZZFV26nTip0rtkykgCgJ7zM105BNB1ScJrydJc\ndvkgoMs0jPE9OLEi+uUZ3Y1JxFZB0CZf4kHVG1LcDm57k8aduAqz2a/25M4QYrr3KVAxQvkQn6m6\nG2OU36buDKae7oNDgpEnIQ4AMU8umrrDx6F+kv7ZpvWcw2c9O4FKBa4CHyFVKR1Uv29mwq8xxmO3\ntwHg9nc2/8jPM0ycWSpyGU3WU7jE3vR/7QjvezkJtL2oFZlKxKSISWh/nQdQKza/WH02yaLU4LTQ\nP3pzcJOAQW4B+fTelsKrPsyvlCF++yK6Zi1pIVR2ywNF/v+DGRkvKGFdOgtAOZZ7KQOG0THVrJw5\n0/VAH/2I9jwwAEzVm/WGOORVLAGByV8NoDwUQdSLlqRDtVkNKV4Y8B6KYPY7NrhoVt1cTOHT1Pnx\nsyJ8gExdwCsV7O9pRNrbhl5O45Kr6ArWFyLgTRz5tA0cq80701gzTdetWqwSf3L9uEUTiPGqMvzZ\n5Q+7DN60i7gPs01Ap1ukf+6pRg0KGXOiG5w0nx3y8wuu6zyhL6EBkacMI7N/EEJtMSV0IpQxvgsw\nznP5DtxGAhHeBej5GuHKAh1wItZwAAvBrwp9f6WL5a4QQIm0Fy1X3yG1xCAiqq0Zu99Go96WsYfc\nO5rmZBuWYgUCvoBZN7W3o8wiHkGBQZj+n/6tNNfVWBADHdYy+r2NAgd9H9jx0ddi/4hzr/jinM2X\noI5keN0e4HDeIeBJNrHRg0kwXu+6e5//xJSY/hiMAKkT/RlQBhtFmQ4GQBBUJ7ZOjBySQ6gtRfwK\nTU2e2nNRVH6zO95jX8ux/eJEYoY6xFGfFe6oQ4lb3ZdLN57NxTY7DZUlfiSnRieyv2U44pJ1uKVS\n6Hu9baBwHtwWExh2GHWzVURT7IJYl6A5csBO3DBM/Trypv6YK9XiDBFgswGuN/H8Q1kc/oIaConH\ndsP4ldtSVZ5+OGOfhY7/yqVQnzH0gkHrmCkjiT+C0BqwL6xyun2EoVcmiFAf7RPBqfg/mTUNMU5R\nFF9BfRxJUuU3KvtyGbGs9EjatT1rqPxEr/FywTa9i5hhpk8A8coqJ91d3GXgja86vd77G3kERIZE\n70n54xfdFDV75vwL9yr3SVygfNJ0jzJ94CEfSZDRcOUDoTJhP1Bb/ynqYf1jsgMfUKzxkqvwrdBH\nSaD2uWotsRAdNWQUXsLOaaWuZF/qRs9bf5uOpsA69OkJ+hVcK03ZgNmYSbb/6e5bNF0D9hSoAyO5\nN2BZytU2324OMkIfLnedCxZ9/mb31iIMC07ERIxQf1x+g0ANhlQKTQV/HnYJJdlTOttvlMh1Y7fA\nO6KCM4nwGzcZ1X97bGUIlxRWdI+I974nXPZ54NheODbnC7bTCUZ+3NV6HwOlEK58dZOQhHHx8Ceo\nVeCA4AW7S4nsM1MHHnt7vyMbOJS6KCEUpA1BFwzBDI8HBxJlDSu1u5ConLlS5U0D1Icg7gKcEmnc\nswAiS/nhKcv43EqlPc44Li+UD28N62icvpUC+PYB7TdljFWwn7jIkGOKGLdmS7HfKJ7J+8U0jfSd\nZkmtIZ2R7M1K27g0kGHEodC4ZZj4q0EDcyF5J8KyhxclrMKNWy6VjCbxcqyMmvKOLIEWd27Mk/Wt\n+shkdp3ViGtA1r0Pzh1fmwblVBaJX6fDor2hHnWeP7cd8WAvTOn+BMriYNB46EgO29NCfaVgkWX1\nD78RAiyaM68acV+WAWileuPthONL6Km0L+GrtLunYOUvLIfk0WfYgkLEB34IV6FP2ujt6PYBcuCt\nMhYTWPBr45oHAL/ZN0p3GNfz0l71kWiquGkGhFe3eqXNYDwSymNw0pPBuc+RnpIndP8GcXOb4nPP\naphOUpVUF7tm7mx/pZJax/Ahp55Aunk6lricXoghWknJc8oqJuXsnmifFjo+1kH+nI7V0dVNMMTI\nIbhqhGQUE9bT3+/22Jn/fktaSMteMcogEBEbP/cO9o9i/P8Ihvv3NAwvUp29anafSP/saDBX9C1/\nF7Igtwc20k6HqtKmwmpADUwhYGKEx0UuIf5uE0UgHxuay0FUKY6WDSHAa2bEHGNAPfeW3DD/6mlb\nK+ljxuALtCCfwIrA3xInlmdQPnqUKnpjG4/R0dW7PuDLYxOTwKUQVPuL9E42yINZTRmD9qZmuwS7\nWuP8o+FIi+1tU43BFhsaeTRLdMeyM2v74D7AI1oooP+kuzXXiB9a5aZjv/2RbT2CcxBOoqIjqnjQ\nfUkicNfkzJjqignzeN1El1f/hkqYQ8ACKysvSSIU+28NjHGSVMpuSszBwidtDJNOT7EBgzdrrf75\nCO2T2h1/Tf45jG+hbuOF9W//wGf0O/lDNdxBut58LqTH1DqHU+KVKq2NOe4CR702VCzzZVymjLEa\nUrrqjqTAg9MwDHqwO0CuppXclw21oZqXW8hJWhy4siw68utuYWK5DuKA2QX7EtRqBr/dF8Q/eJYw\nxuYKhdOVjc9E6RW7xp2CG8WxX8/fD/l7bFS4AsOVEcnXWS4aLBK6LVzjQ2QYe7fobYGd09f1fiMq\nKGXMJ5NBrOAnteUxvy//37Eo0QloyygrsC2iuD1j5nwEd1cu8O3N6onNwr+jSb959Y3FDj6uA4jx\n08Wz/BRtjcqsXhYYhpCy7aBydKuhFQAVPQItnc0A3NG/HdiP9ofuQ7/4KgGPclTssAWDMqDcXkyH\nyXRg2EzajopFurE76rzU4Zge3NMNg+pyXjRmyQnxurZDzitlv6hH14a/0uEg0ULgCcPlfxF4pqd1\n4pJfnwj2Yhl2KhOSOoQPXZNt/iQ+XGFiUyyGhvQ2bjFsgmY9Gf7nP35nID8MOR8+NPCsY2xXNvdl\nnNx8iTAgH12HJOXzbKW1bpZZ9Kf43xoNLyXMNu36/WF1M4LdvTQ75Ih8HI3UmDBSribV8iCjEcuF\njfSduzHwaSE6EhWOHt58XJhsaPvzZZDcq8s8WCGHHeIU4KkNRnG8zdQjACo8DNAMkd5kzdhaLlwr\nRqNafGTFqIa2RchYwLJtLKgyTDgNaLcQdqtIWhWOw4yTxdHKBCFpJXGeFOUZr7WSrxFe6Y3U6C3m\nYa8khYq/eHHqC3+ezIV8UG/sNma7ZQsy5ZiXtW0zdgotquv3HdcwoP0C8je5VkCkwsrnufRbMyki\noqW0+VdEXROZWxy4aJFzHq0dlO5+vfynHER0fkvzR7arcnkCEft5isbwRL8dQq6+j04G657v7do0\n2E9zpGUykT83ZErNRCeKleuRyDipVBRmtNvWqpvitI0+mogoBfALJesjQ0XHl4pQWoVjRer+STlb\n/C3Dn9j6RSpMXeOQMxV8EdmIh+RCi9efe9S2vplrWCZNdTsVwAM0sHG0hebahbiIYaBgHLDhCer4\njD1uNz9DUn7sJB5iMv3YUHA5OaTPjAxaITZCHXHYouDYN95Gzz+fMN7Ca3mSLtT3AH9ujw/QONu1\nCYSRdbihjq+aahtFvrk1C/TAa/B0NKrm6nMn6KyOf28OswBDP+mORRhrVeTywGTWcPVhOQ2kiMbJ\nk4WYQNOXEebM81S7G4JgfxIF8c7izLL3LSs3fsN5Ys9GY/UM4zMVmZhEEgTiOB8uM/7sUam1jb/H\nWaxwy7MgPyFAFy7Jy1FT9FawkEKrM3l7VziN0n2GdrWBtlsmTnIkFR7N8oPQs1MPllyDftrwty5f\n8r7u6DzInw07/e9ZqsRguGSLML4TbunJMqU1Si+Z+ATBxHYErlnEMQSh8oeYXno/fpuyzXrSG0kc\n9G4yXpiqMKsECETEZs9eACc8ZDAkPllCJl1leArM+pFytzz4Yt7FQuvtKAJ47JYDdgISVpWPzRKU\n7nn4Kekcz0hyp/UeWmU6YWo1+KP5i6DdvuTxpqlLPL2NaaPZLu326gIfpc/xxbB1IE8Jjo+acaf8\nvky3pfBsZG6xNTNbWfKDjcIdh+rfQZ1dEXxjMIuu1iVy3WjB7dMLXcTQhdgJLeTkCZlYuYTl+zzo\nSSxkuxggWXdEBaE20VLTNGlTLrev/8EHJPb0qDqWpL0szStio+Uy9Y1l71wWcOw3G08Xb5jho2vZ\nVb8i6ZzyFlQ1HM8Pxo8UoMLtghRUC4SvmOCuDJuQczJg5X2RViByhKxQEiT9X37G/QqFMpindMYo\nXCDfSUcaHEObBeWKyBFa897SCAisq10HV+tVzLM5Lvj001cvGjqgjLdt0nOZ0cH3MC3uyZMxYF65\nyxpcDWZypIA6ZKQeTKwvQgpKWGZEqIZ0Zm5t6mBWYP4O0Ti2VM14HS8yrmiuWYBnhrqU+6MGjosm\ni0nouU7SuvIWEAPb8xaQPBntEqZ5j2Q1gnkypyNsKsw16qvzUKhyGLEWbd2pMJII0VSJMbAsIfBI\nD1jdAxFex6EaWJzQukPnuKkQrQCU7ZjM1uKE/4BlztJlPAuCHIZLEVdJlk5hhToa/2HEDmHrQxJa\nlycfaoNCvg1UHyyDIEi0n47vRvKhqPaYdEkahWA0KS/wzlnvNI8/kEZzwKUyFAtCy349M1g15l7g\nb656vZESvlS9CWbI2HBsdwSRniiBJHQlb/vqqs/0+bG+tLG5HnIpKkpYimbhLJtmO1Oi16LZ7eIl\noyGL3J3FkIjXDCFMICkFZ7DaRUtC8j/3bdti5dEtvcEQV+ZNuQE4KPeHnGdpD2mphLGQU/mwRymT\nJGrYVvpVy/gOY82gAYs6elziaR8U/s+sOLE2pvct+P//ztgi/L8aX88uTu1JE0dcMrL2pR693uYe\nKWoBQLtR3OqjIIG9kwfrWXfxIYnuAgP4oAvRYkmw4Ut5BNQJTigNydNzZgFxmB8mJQOnG2CIRLrp\nLpo0dkUGGY/FLive4rexTrDVaolK6IvjqyL5hHpI3oBygrXqTaYT39KeU73tVsCYVydHYtb0CeMi\nreT4LnVNB3llfwwdOzuIKcQQwJ3CQMf84l0U3jx5SEznA5CUf6eAhkcZS1SyxLW0+DqnXZGnU026\n5kHbhGYVjAOvAEMKfDJcJ+nHgE91MsqC4gq7ImdwjKGe3SaCpXiEL08GjP+MOvczIECgSiKNTW2O\nIQhg0qSxkDzMLwAOVA0MxUT+f0yz2PM2borx6BzyJFt7/xbzLgRv/NwIMvVLjhgBL31e1bIjnMVU\nPns6ekjZQzvc4oRoUFAbL5zUGMdge9yaEtd7L2tRrgf5KqZB8Ff7spcsg9PQyZFYU7A0KC/u6hEL\nUYOsJ3CPrRo1kDxtUNn6ILix7boX9UoUDGgLADq4q3oPIg3u7yq3qUYShWej5HTR+QI1QijuMbCX\nZuE1haMM9LX2XkB4+hFL/104Ke992EDoPdAcB0zmUPuk+lDwZF/Zzl6xEZML9psXC82GsX4DWBK3\n55GrEZpvChJgrP+zYol0kruvTOQVFcuQyrHZTUNV7p91Toygdb+r6/N3PZCB93JAKIGVuXfQMaKg\nfPHta20sd88kGIixHlf1Nfh0mC5ga4/jjTp3D8/LRS8hkHqfG2U0MMvF3CTcOEpxXBIo7qY/ZLLl\nAdgqRWcM4ARfkrGHZ3cbm9O4gmXausb3jPNtVm0u3nz2ycuOaV3nOCqa6xThMRZ3xf206OkUW3WI\nGhKqZdrl/tb+8MtJhgx+fTSTIxEu/+f7h6dFfFw9aWikKGiMTUVxxwoWbT6OFqeJ+muF1AfD0xhy\ny3wOEJ2uQyGl6/4z5+3pj5lGOoEHaRX9XTl3J5PWHUmKOMEESaAXlJxG8WDSFEupRIDSA6Y/NMmn\nSkrjfWNslCM8hHmRzINmlnDRGX/RBbtSQ2J7lNlmt2m2O848pDTeTffdY7hbq7q4Y1I8bkCYlkG/\nB7SVfrLuCdL8mhjw7YYC2+oFgrOnPbvIp0MuVKV+d7k2qciVjoC6dMLNThMDeU0p6ibhF0iVQnsG\nbADIp26fJLr2DTsKeQ6hUFxRWO032Jz3Gqo2AVco/nWNdxXZ5bHEm93G6nrvniYVeaj1Qrf7pTwy\n8JP8PW+mt98Dc8toQPqfSbq+8HOqEOpGxO0WXlXIcndB58eZ30HCi5IZbCaxVZ9zmHfEz3YLOhJl\nv7AbxYkT/y6Kp2oFLyceTspEde9xquKHXZCGBQqvElXT5lduMhDch7qDdFiUa50gEb/HJinbWiN3\nHYTAo3rWZifyzux2kAXwBVydt8AOrzRO3dO1zfA0lK7z7ymkvy6rHCHjnR9hl5Ev1yrFG3UsWd34\n64jrhcEZheZef7vYJTtji3EW2kipnsaffA938uqz4LD7gGzAS6kLgWkVqdeydkpnLjtXXMP4LLCW\nItOPSKSoxWdxoNPUSWySo0PKcCWdYS5sIS1GkP+6a2+CR7KQeyzv0AylGkIPuGuFrb2bpU7jt9fL\n5xJ9oqZtOWeu8VTi48cbSY7PouRXGolcGrnMaHOrO3JJf9S9UhxXCAbU+dSbcf8zLIpVRnaTK6MU\nAv+5ElKd5uGSixaKsnxYWD4GDctrqVaKWe4oZRxJOQZ3k5EX7gy8ksInw/0HDKXBxXdajq1SK+Ix\nfW3sa8N+Kf7p7efbF1H8gvQqnO+ob3xF5MPEhp1Ph9D8XXvdkSQyTMMVqnkg9wQsFFQuBlkxF+sj\nrDoqY+LXcqVCoF9R6gVP6BnwPcmrgM7CXvYeFFsYg19O8B4Kwpp7a6+CWjnxp4HnG8KsdXwrxBj7\niVUrNTeFapxu9HM3mqN2igSYyHD56KtTlE08UOeQXFyHrd0Oq5kLgCJkVyCD4bIDddnxXfHZ8HDa\nsKBSphe4P+yXxNrluFMuZ2LkN02Oo5tkwjU5onFV9agsTHn8XgDkKYl0OQ81CfZEumu3gfuKpy7F\nGlm+GlzlQGF7ZLoCWacpxdsjvlvZnxtgyIYLo/zEHhjgSIOi11UAx9cuKFd4ENq0ZQP5NPCQiDRA\nssPyjeHTlaNLLi5u9LjoW3C0VCwd4aUO4NkVSbTI9fTugglMvCeDVfUe2bhlyDFkpwiwJ7lTaxEx\nAxJZNMChvB7IfGezf8VCwXTnuuyZ9QIP7pU+PENZl3LAwx3NuM67fD3rs77McNqSAZB7kBMoBnae\n+rQLxhR+vptVVPf3m9UTVivmxL5xUQlcT+WPwwZMkir5/mrfBebtv4HN4FNY+5ZbFrgIS0WNGudp\nfI44+39CZKLcEFLzkTdAuq/bwJgZKMhhRTn8jTkjmxbt5yolHRWUcQvTieYMc3gEPUKcHgiNVx6y\nfTYTrk6nHUYTjfWTRfpVxkr/lqqwHwzHKiO3ewV6tOhutiTQghuXYOv/S5m2K91HInowNH6S0yXh\nrI8drzxzRi8Vhqw5O93oNqOSVmz41rrTI+F0U2Ng4szoRZYu61LWBx+Ppzabar6OBLOuRDLYROSU\n+f3tKxC1Ad2cR1V5ntskIxr8I2IlMGUlVV/g805HxxQfCqNaCIMv/CUqQbaq3eHXv4Du83dTu8F9\naG28YJ49k71Tkqjvdx9S+Dk0VibGwLh2tc5szi8tTEyOwEqim3Ef21QEigHt4VzmabcybCmfO41e\n2oAzkczk4p9ZSLO/7/HK/dS1MLFQ1aT37ByO8bithM8LsD1jtEE+guYL+5xzXQX2goXGCUOra6Mf\niuJ/irSy1tsNyH5WK4JM5KeziTw6Jk8pcqnezD91zNLch5P9UNkKGSn4UJA79q3eM2vEezEkUnqH\nk0uEvWBaDC6LCkTr4C4fZDRy3GZ1ZuX4EmgejVXACYSEs5uJhF8K1HzFCR4aaVBF+QliH3bz/Pl7\nAXt+Evt9eKNAYWMdSjdAScnxKHuvbOsPCkBqSgjeG6//ckXsMxfFoaXhBYkOytWwkmj5Jwb7MfER\nrHndqP3ZhdxiIaWW/4XZKF6FoiaN7a0atdvcZtXzn+wK6LN5eVfJPRqS9U3xAInSod2fZWV6IxZv\nDYkMEka8B2kBmR1wP5aYxp7naCHsyVceDASXvxL6nQtmiyWziLnhmF2pYq9dPz88Hzi0tHSDpwyA\nSdwO16LuvrQvKOStyZyOHhKgTMHeSfy+zClq9uyqihFJ49BDMVyoftp9FEWexBY3lcd8MrMcbakL\no0X7m8yMNZ1Xt+tTMLGQXPNLpN8sHw5WAHLl5haacqWo6LAtj1z2TbuE+sdMpW9SfJu/Pfk+EZER\n3XdW/OVCQLpiAb5kkDwb8UDt+ar5a0BnokqzibyeUOm8tBpuZgZDBS61oxgr3GLTUZHh4pXtpg/M\nt9Mh/pUE1Tn8w+3+7HhE3yX786Xg12TXhMI8slBSbnAJJi+90hmtlXSUiOdpdVe45T0k1MNCVMSm\nf6OWMx44KKvAhNeU6Z59JqEPLAmhpeuj8FsraDdHwioX2Tg6UoeY/duENB49H3WnF0QMQrATfLH/\nadN/tj5qQhp6iSvVnOfnV2D0bpeboc2TP1BkoJAO5Q+qPb+NkPzBOwSFXvusBli3p1Ljd/kKR+Ce\nRAUGO9GDJUrRRdmKmSZCRYpgwT56l/eCvLBI7HF9r6d0FzcEt78yXBjLSuSUygmoxcqOfSaLDhZr\nmP9CMtS+TuVxE7v+cNHSWs2MFhd7/+isiD5rJhr6wwwpBo/ySfNo49q4qPFGz9D4HV9Rx2vbqw9b\nxycBlverRX83+p4I0ZT7cD/g0X1R4quPhuGN+FrHwxQXnxF7yiANWDjnRtgca3qUAXZt/zF4GzC5\nRnjbWJFR4lckg90wInQ+PcdiIoud4MVicDuDq4r1TAVkeBZi9AgPMcTb3y985DhTh000aJedrtyP\n6ERtjPTARcBvAOjX7LbNTMkRfTmZczke3k01q06x7HjXKNPhoj4IJND5jI/6M3Fv5zPVNMT6RmKJ\nzoKBsADO3c3LEOr3b81l0wXPgeiUHRORVnC45nkBWaQmhcgmWgb91nD38Y4D1p0nSrzoEJJnv+k4\nx3IdC51MNHAXhfECzq2QfmOxm5U6g7oPfoBKPLciQ/UA597kMVzkpLiawJ0wiOINMgoT14D/e5cL\nJRV9RJ2Ww9/C6gqlr2T2BRxYjlHI07JIHysmqQ+pDAIPg4W7dI+kThrLadRpKtxxoIlrBDWP2R6O\nVLsZx6yEEOzpu+V+rsu/apdFc4ZM2x013z8agnuNODJFRr3fYMtguYEvEhfWeWL380X/L0D4NC69\nesM13FxBJbmPzxvf/DZp2Ea4niZH4loEfZtqAHf/jydN6g2PxcbW89w3/cZH59A6JAjbABN1pV21\n6URWmGG3/qarEUDMJgf3ax1+hitWdTaCaFGaFi9odBl9O9cp3dmzxBXzyHaVs6JMl9hP/C0P4sd+\n1QgFpiswJDGzuYrW/fjMArJqgGiCyUeNIfd0pbGUWncbuh4QKiSfG9HJ9ad1NWpbRZbszk/DggT3\nco6K6pez3pJc+LDGEDilTfHZ5RoS3JMTpYOYVh2sONi83TvH3sZDLSBNxEnDhvzu/GUmzEoRHVtH\nibm3vx61CPZGfkJeLF2lxe4VxmkXbBfOVuIVCU78sl7v0Rwc5jL98VGScM5lTYQJegKGQFwzs4Im\neDaO5T1kiA7ovAjXQvrZj0xhpFUHJugP3EodD7DYrZoZ9c+JDbuCVcyf8ogg1pUHu0d0eMY8Cgba\nf/5fAg7cKZHU7/lQ/2E5JILI3EqQ3IPC11LnscLVnT/siQ5RGW0EXvBC9k9zIVPDYARM861xj6mY\ncdeFFrzgmROXVWSwhaEEifeKhX+QnmBEFBVn1gGeEH8FGurBp1Ns85cbirgar30Odljgue+PXFm+\neOJCljB/meqPefOXvl4XfADMvMZfmuja/0GrpDPnDlfUWnuHJ0+Z2iFQgs0QRp1p0ETHgQmIEFXi\nvBpJAsVmGpsaDlWP4lMe3in80xpDk/QDGMG6VvTqKLCZKjk5ohtSARqn4iPhkubd/9kMYV9E8Htb\noG1xpnuJkQYF+yOHxCMaOE+1rz8htQovtwi3m7NjoRkD0xfuu6pCraSQjNxOvwTNPqsT893fsQOo\nF/xE1VF76Yhfzw1yK/WNrupuk6mF+OmDxSMOZ08RCoL4rpbRzsT3mhkKFQhzXeg+YIEjq1C7Uty0\nTr0fhD9THHL/HroTcjkqwFuc8z6jO41/jvs1Dal45XlzaFla4qaAzL06Xs3SoX5XWTQm9ozGpnXt\nHoJa2QhreoD1XXI99+8dw3ksOXdL2sq1aPGJhdjW//ALFfxH6PWtLMnb9ShRr019SIFyorH9U2kA\n2D+4FlQ3AcTpnQTliw60ZsfMa2mZM4NL1cOQLdrKcB6zkv2PoDGm4ECnI6u87KlSSoMS2YTtLanw\nTV7GSgh95Et2Q40o+seMl7nMbMbC3EhPGCjut+MhFB8ViPQbFOrmadlg96wPwgWP0Yr0j7NGQro5\npCNh7di5Mp5/N3z7PohEZ25UQkZO0RXipU7kSPUxjgF6/N/A9sX3H2dOuaIKPuE1XEJJvVDB6Y0w\n5H7kC/phMgGu7CTGO68x5xBKAVIFXJJTfb5k+/Ir2Gi7G8KdhhEejfihtYVmvCOZ6pyXLPrqxvTi\ndQ0BPyOBY/3qLlvB28I2cLZoyQ3xx+827K8g5AyrNVZYE+A3UlbM4TOocySupv11TDCWr4Hh+ST5\n3Crd/kDhUocJoUeXRay1IlQz15PP4ug4KUuyxf/LEEIQvaFXkE8Gs5K1lIyCZwy/+nRfes5L5w5n\nN7OebpbaXTw1o7XBy4Fjw7vWK6DffdQW44lh7TO6PqC4CtFBqmJvbX3asePUDRGkbuFnw0g/0JYj\nInRFwgxm3MaNcAZL8+4IBtY+Qi0fLMhjNeoNJErpZNsq7zJc3fqyKi5e+scTV0Ufv8cDrXXm6CjG\nMkOPHnCSqn8Cp8678yrHqwrMM3aCQMJGUlMa++p6hBJC71XNFb0DjewDQtVLdlZG3MSqrdw9dR7p\nK9t7mk1L+t1rvV0bI1L7iLWmaYM6P/ofBkUk6Q1xgkNc/xI7xWZm0b2uruape/PA2H96lSGrhkLY\nvGKZ7V0X4K9KEame9qvcbX+plnZdbZk0cy69NgiTQWLSiBsLcIIMQpZH0atqwPoiRLpURqbTfnII\nc/rUlexEH/TEj7O3eF+BGzfzWYMWsVTkEkF7hvnJTAzlkD+wxPytHpON4ePN+9u+tPDBsiqXXBi6\nCPpfTDwLvl9OacwdA8c8HAguoKO19oGjlxvcYhNI5uRIkXxFWK8yKjS5nAdthGtS4F3VgHsMUFWK\nRFT69v9G8grnxUwO5yZ4umOhcwOdy+yRC8baFYZnShBGpNx84cqPkDs32bD1Ph8hjlzcu5BIuUVi\nrEf72XYeQUpgoeQzwVDGnkqVXRzX3QDHSPTcOAj+zHJkn/oi0ClssH7E7C/BKDW8UZq9U48tw4kq\nl/0W85XK7mZDGBvJCrIbgiCPLDTSH/ODv8t5n0P/39khdwI8N0tcP51CgQ5JKF3ZPCM0iP5opCVx\n+ndi70MS3MuXPABankCW+25XAy3PFccoU5R9yIIWZ+EnfDlog4p//aLtHfLIeRHMG9j/OPoGbiAu\nqFPcV7gduXlL14oEDYJ/ybfVHdz+YRst+ioYwhhcya8632LYnOBXHrVae36S3ophH6k6WBIyu7kF\nsGKhdJwoa06RtDHH1g63GJmzDJJ3GB2anhjGp2skhm4KGQzpcHxzHsEIpRGfEZ9TBdOyX1f8tCaO\nJPmb9jEC7KNWGWr0FkrXP4k4rJabMmXt9Z0Www+HQKbVmZlV7T/QcoMDBySNALomgMQcJ0a0gIXQ\nJYqrtlx1TubH9OtROzhzNSTG4H6GTDwzbapClAb3p2lPUq4vu6g2GpNjOfHaxT5c3u58TycwX+rH\nHQwXxt0Gi4AEvjj0Vi4aIk5o/kCUq1OC5HjBnr/Ya805rCtkB0yDa9q7oblVwCa+t8aiew/X1DLu\n3zSQaF/9aGEcpE4cn0rGhvTwEsrc0pyJLBZmemieynfUAV+iCyiJqNllOiff6gVtWjXq255UEhBR\nFbzuvEFT5pVEpgWjRmwYOkhczi+x47m4HdElyYWcE30ADVV/lyLRhAdAxyHuqNrG4+F6y/aeuLu9\nC+KGDOGGawEag1cehNK5GJIEkfnl0iit3Xglwp5BRE9R7H6RZ79xiyvJFk6zy75TzqaFdjn2yYLa\n6XGJK/2kh9rDGxjk5v/4hP/O5cf/BcAIOO6Dczl27moFGFJf98GxBS4LNu+6KDnFxrX5MDIFNWbp\npOv4hV8YVZafGiW9NJSrJIU2BPqwlB47NP1rBHh5nRn4BOPNKK9Z5kiUaWatT0DINS9WyfVknmtT\n/JtpZKEETWBZi9pZudLmcxTNNLBPo/o7nN8Qt5e8id3qHKiZP089w7/2JkNhMsKV+CrpAXBmHg2q\nQQeNIBp5Op8BkubaC2LobuSdM4Xh99WEgsN5GaSCZ4IU1dJJLuGOD9Li+2vjWnBN6zXV1dphbBmp\nnpg5F9xz9RZiINtOibbd5naqGoyAa7s8hKG+kCufePVEyJiqGnxLZmAHfzYuzI74OwlnKnc+BV6G\nfPCjmZe2OBtOybiU09KMDKe3S3xCtZrKitaawB9Nwb+MprSGHMCGIxGGaL8AS6EP9ki0RI0+DtMS\n/bvDMpkiV+VbfImIBpCE8Yygw+UsucNsv89LjxIcQbXKpq8iZA+QlEVFPbKjnRzKm32Ar4LyZ9FT\nCMyyy17VoDloLH3kUL/xKr16OahwK5oHAhyjg7dH5V7aUmT7ibVNM12arIiZLuDXaJ/OyoSU/BsS\nx9yqYUuRDTBfZfPCulv1OGeL0jGLhlIaEa8bWtIG9KgKG3AKeS62SX61RIQik7xq5U9YN3V5yyWB\nIH2ay/mTn672PBSS/woHMxIcMEeAEqnNPhK3QxOeDCKWsK6hH0TgPbTru5aWpBnRpT58U5AjQLbT\nQgXEN4UdQUaEccFxWqn7Lwnwxj1WgpCwgWi/4n45O6WiDt7yPqtabqXKxYHJy/wKnkeH4DKp9RG/\nd4TiPxwg+TaAJKC8RNxKon/doexaCtCEtKzkEpRN7MZU+ijTulVq3Gni2jNi9E5cwCCyXYewRsrR\ngpBvcAcbdABWjhTl02d/kv013/LmIAe7n2Sw59GKQa+d8aSnGP7nsDviJTOxiewFoEVaz/7Hp4oV\nyPrHgu+bYrJIYmSJjNE/j5uP+mRMLfzApDTIjnjpPfz7TkYAc3FYrZklEVamT/gkrbvy4Y60JG4u\nL/5a/uwSR+irXizjUoQoCB3j13wLilXvDOZn7TTvLZyroxAhcERNsIb7l75Lkk9/WLQiH+2vIFBJ\nGt1VRCnQxq3Jw2EP6KdI4UOIKsNoY4LGc+WEW8aYYt+pJ/wt0VB7Ij0wUSNz6Rk/WIMRVqHMCW7F\nufIz7ZJ52bUOPqnJq9Lhld8UqzmEsg7RcWJmdmM9T9P5V/6KJwgzykBuXKFJeSDy/bGtrd5XUdRO\npk0zQ/Sq/t9Nrkl6M02F7FBMfxPXB+TL3wneYN1XZI0C/pq1Bx3/LzmEKvqhkGlYgeqNRDWehcs7\nSSJRI3MS+VsSQw5sGRGy2F3GGYSIUd7bUeXzd0Zmqp/XHzn+uhzhF5GbW8oyt9fUczLpDBYLseWS\nXBSlxIZHGbB4YrWPHMYhAd2ed/DAtntVc7+W+0se07XkTGAH4cL6whdEp7mA6/4+A/RvnBSdQF04\nZlWD0zUMHPW+NXcgPqFA4a+x6nG1KWZb1sIRbsrdeyVSlS9VUgUjotN2dyuIehngW2gZ4yPriEgW\n1IT+1zXrL9u9qh6tfCca740RMC08sP1GQ8a61KKTHag6ubK3ABZFjeq3UYBOM5evv00B/sPRG6ez\n1/1ZasmRybOk4dywL3wLOTIBKI3uv8LfNqsoLuto2dgramO4MiTzggwvmsN9FYy3K6jdE02D4Gim\n6vSDMdi/Rf7/GX37O+dxQ3lp7KB9yaVl0Nbwc8LrUJ88XqGwz7VIqcFLDaokEIg5un9T6pyBMcRq\nbM6QNWae3KywCq4zBZm1luMHeB8/4/1v0HthvnRo4lw3OAr6Dw5v5a0S8sse/qqcj0j61GFzOmL+\nbRNknCq+TO/Dt/YBgdqI/y2EYjPivjAbafV2oSkCLwkvyDnpYNLn/b4cS40oI7LbD9SVSU38BHPR\nRxeLoyCzx0ckZ3nMi3PwAixgYvW4jEbM68ru+YcU1qKzm2mX1as6D1F3DNAJ9rwZ9B7seKQz/twj\nw0HCxkcRwoaUCnxUIXPgbyjtJ7ZS0fZLJuwqKnZ50NSMggtuVMSH7C7KMw34pRIQgzHCSy1KrYar\n7O902WvmajXIIh8v8tdzJjX5l3KStSnO2vKimvJFzrsIwzbDwmoX6G/J4olgx/IMnjExauLzoRlK\nGEoHJ1UioORoYVNWwnF+fLW8pmwtV6+AjKHwePScWiNq4XLijTUU/IY9LX+FXX7YhmBkYxDXtZYd\nUp/QsSwPOdpueksYrHSOkXjsQa1S4a3W4+lFV2yFyhf9O6UenoHXouBtF+iQzaqvGJa2X0Vv23NH\nTktCarVFUwUFsuW/8NB/RyClkYapJ57zpX84vmqvc4mV1MEIzBrp9ppm2jaLG3FFhkg+PYiGhQim\nGQDQBd9i/fPo4ZjzT3bIjwQNnjp6nBrKYvnurv5ibt0DL9xwb1o5mfVKLGbR4/PGjyTVkxBYwOds\n1dNeZ3ciB8rQKqeY5vjZhJUdbDcFOJH6OQtVlSY/SUtdLyG2CGKR2yif9uIvnHGfphx6FRQt+JDf\nDC/BlR0fy1bB1zcJ9z+UO91hWlMfOuX5qAbVz9RcpA6RpVKzkTkNpTLUdd6UYkwGtcQXWtkSluAp\nSVanCUM9X8qiMMEciveAOvsbk/s5wCb41YmRcJWmsbwimIXE4pY2aa4vKLEbF2xvyhFs4xGr4EXZ\nM5XAhKHcfA6yl5aYIffX9gG7eLJ1Q8yhsfvOvzQHTyogMZ7rlONudqptdvhogDh2qYjFUIYylh5B\nmGeiuxapF6ZqM3EThqfQY3MKxF+xFsXZjkGDmDs6qrKxqbI9IjIMuIpfMOuyVqec2SV57WmFhtpJ\nIs/Da6QsQqSECZ3Z6AcE/OiOamf2Bc/lgf0xLyi+nN3LA4vRtO/T5A6mrmtxFrMEhSW6Gr9PTvG8\nb3zMW9rG274zFX1zWu+Xg4Q1qnQu5Rx6iwDH+/PUoS3Dim3WbbuBvt6JcMFuBGSf/R8q7JAO6tjE\ntaAOJxxJznzoPUydm13DF13dueadtT4ilQ6xY8F/wJTwO3AyVjzjGIkANbvuQdri6qYb9bhzsXQS\n51nNPpsMDgKa434BE8vfXDehh7f7NoLNjxS4sHMf+c7dm1LjGXyaIubPqKtnFeToP0GZ7ZVVsaXJ\nWXSDvMRRridIAHR3UGPIWmTXd/U0ulzP1rIBPhHAtdCEbLmkDv8tOH9XNUHmHobPzOf+9GbBRNLO\nb5vkR7XEArgZMkGs2kR+VcBhqyIhwNsCXu1tU922i1UthOSSCho9Clo+4vaCM8KVW7Xa6TAeocBO\nPPg4qZrgVg+T7wILNAHovNTBgNPK9lLNEluJkNjpObf8mgiwbU7pfi4TZcKp6bj9if5JG2g2UrMU\noi0YlcC7S+F9kBbLr+/TqyKlNTsHNVU92ahohst8yFCokjfoTDKxcfg82QSg/wEVggyw1QZqu29v\n71ALXyi82qdtFCIgVTSsNEI/Bhhr6SJPYd9Zcx7ITPPRqutrJqfqKoV5qhBsIy/uMu1yXhpHD3OJ\nYkmD5IHq+B8xH6eidiY+siY8LXJ/AGlf9sBoSSv6rW3NBEceZVtfoTZ/aA3GaP5nqBBGLqD8pYou\nlsyXVxd/fG6f3PlDsmen7KTGDduNaCHVQqB5TMHI7br4j/vHDUBlN6eO7KVJzfErnfn808GonxfS\n2wTq4D+BpDufYnlPnM7WEQ5eSRDShRp7XWyicI1p4BgGQK8lW/w7zQ5vpRxj4/Qa1O0fLmBXpOL1\nrJo2KQrWcnK3F5r4rjUFfhHwJajAwCGwTyOq3434GtrZGLLkwaq0BTRHYENWpBbfk0y8V6ico7ij\nXKsvxPpd2T0K4kwRLcHIhypYSUIJcKQgF4TBW87Ha0nm5E3JUst8Etr++Fu8wmv+nuAJKcbx/WwY\nGIoFICZ4yjKlTAb7XQhq/IrvsQN4DiX1x97xmAff9TqRi2OvZlH7p75ADzAeYNtnAsxrr4SzddB7\nFiHbfqTRSXzcisQezjDMGkmYvPxwtx67iJrs/S+/0LrBocZ9Sx42LMLS5bLVYY0B+NA8nLh7JFU2\nvQUkdOp5DkrhzkhjYkLzWat5KSpVfFlBKcwM51XkYS8p+mS8GN9TNrSSHuPzbUKASv6qKXruCrvC\nLj5isZqgDmm5W7pTBs31FgJJv4eoV1h9mn8dnUprX2U7m6lEMGBmYC0IuoWWm2um8KjMpzNYGOyS\nua6xQLqK4yQTWMlsmh3GP75Ngg60GVaWXTufmY43nTZUjg3pg8ZLSyMEacYxeoYSrBUZjU/Iesx+\ntQ3JfqI+JOeRkiy8cyMcA6AFYhm7Oro6dSoxH+uAf6m/Zd03ySSYtKeWm7+jT8vr22EgSvx+/CrG\nU0SIxlFYT8c5xWpTPJuv9I/0isqgT52qwJ0UEJhC2YljJmJEZ+NCOC2Ns8VfVLjN1HKQ2McHXY3M\n7y9SKvaF0Hwsv94XJGrq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bk1TaKvjjN89rXBSMPnAwg2IzQD/DuX456zZr40hx89P0m3S\nx7Zb3DWAujN9toSodqWkyY6r9lz5XWYNeh8tZYgSaKNTWcnu7SgjKGmBvfWI3LR14Cj6xEJqFTBb\nylcSoAY/+yKoGSXJacZbKV7NBeBi0RoR8JQfFDwFThhdEgTTzKIV4ipyw9d8OUT9A5WNV+yUwbfG\nw29G34lRt0uQYDXOMo48c6eKMpoFdplgEAd7JYGPwpKSHv3wMQmuBd+v4+YsGCLKSNvbLlU16pL0\ndmZ6a/o07WBlgeI96XKgec0SBzKXyBhQsDALMMos69OQlplKduhcNVZpZSSVJzyMBZysu6xByMhY\n+dsR+VRN0pC7DtDYMJxYLn4MYB4qj0HRikYcd4mZzGMAKiSfS1UNldshK/AEjiTUt6Hbvdv8MUNv\nVprCDnr4Aw2Kwp8jYNOHRaBt4R8WZRxgdU1iwL75G1ibCSuRllWq7OLMA6AU7Pcf5mrf6jdyPQ5M\nM8mCKp87Kb8DPGdGMvqxGo5TBYwH+TAVhI5/vb3ktEyfrlY5TLn0Fv6yTP48pI2IYnIimIg272S4\nK54vszHp4efpyu2q9bTTTmbKU1hqYQ/Rpi1hRT3ljWYzfByj0z+rT/z5lKr7Iif2Jy2vTroDZsmv\nf6/kzEp1WPZuNCcgfBtQ4ZQN0ZYW+tyji9Niybsc9VFcMq/YnLA0u9UCEAgxdYaY0XYMvV1gC3iF\nDlPTOLN6wQKjwaorzp1HT2RUf+nZi06yNuaTNG3Zv+hFPGpt32okb1hOpL78cyqxDmA3O474Wmre\n0F5Fm3vo7E41byX86fAAvkCVxPg3PXQOwFHRV98q7KoYF6K/Wlh+29lFwhQ0na1JgP2/VfYzsA5v\nCmKoBMznbBdqSM0sD9YvirCTq72Wg4iQdkNoB+8ppoN/SfatXaAq+PPf0/QNSyLrraxDcH5BRGbH\nYe/BReXRdn4HYdJwQxrH+0wDPZWpnV8EzATx58IJUrGjfYy0aY20DGPCb4pDBlR8Ie7qlHdo0D0Y\n+34je0cSPN1+2Y+NtCe4w45NJ8RczeGhZQvtd1vd+IiKjQ72gqA3QX6Cf4AQ4n5Zh5la7+QItp0o\nFndof2gZIJrSlG9Hl6BN1KDrPFbmZeQGBUvh10/H1SaQ21FBbGtmPEcDzoAgITjHfif8+UcEph6Y\nbJe1NXFKkDrbEDIZeCXDBAO9Sau6yE09U01iwGvbRD5VpYHWzR4Ns+0OXB8HnYMFKIAiG42N6jzL\npw2OEwcr9fKmwknfsGWScd3xUeHxLEz2asJUYdfDKpf2uVx2FF8MQkbQavlgIiFKshSMR21DwtHg\ntZ1Tr9DWqjp0KYZz6A3fDautXDTJQ+Ya1GqHQfL7n993WVrjXG3MKFCdrSrjTgMvFHRmYRaKMqAh\n6up4wrm8LiMEtNccsvW0NwYCoRIL5GWeUZyRDsX0R2xm3ZuRN4vtWscAZDGIKtr0NO/SLnm2RqK1\nRGexppXHEzLd2j5oCWAp7lffMU5aSJzadOWJ+Ati+JzGHxzadO6lA5BKMo4VErkvpdAPb11Hp8Tc\nxDrhRHBYbivhllHxvfcDtnDoyyudV39OserGvfgMip+CEUtbLeSFsFXHX6iFSaLRpi9c8ZdQnJmw\n6MUkuShGkbdZh0IB2OXDCKt4PhS65KNP494259Y4kWbYWcAMmMvL8qsInP8/sCjfedg7V0XwTVCw\n/ZrKBLHrRVDxkXQt0bHo6l5/m15z3ozwV1PgWL27yCR1IKsbfOCvqNLMC9gb0Pez17BrYhTvsqTI\ndMw+Ir4rH8+bj03uKM+8+G2J7OyKFz0qjh2B7VCCBQGqKRfH3MXFGINFyWSnpJzkKEOmxhIkJCTm\n+mPE2+g5MWNblSLQ2wH2x+mYpqMkcOyV675feRTpbAOOg0Xs5RaEAApW2gUTrBNAJX588uQ31zOb\n6hRzogV30vDb5r+dx+dmNyhNlix45DSC/F2yars6+dclEjZM6k4Of01FWSdp+feFVstuPQYO8R2y\n84obAtSF+soKqD59At4F6HIAe/l1VAivy8v2GjYrnmKMyXwDnjkR0pYErwdIJN3PxaF7c5GZPT80\nOE3DrOTylsHkNGL7+/8R1t6dy1sXbRdk784aQJV4Exd+ZPcfds4fotXg/MvXiX+tNkC6DJ8xTkDa\n+PjvlUFDR0tLvxVna5H7PR2RJ3SxslCL0tzOhFPBY3/FeA+7whhotJEzWVWTek4wB0ubu/tY1uGc\nSxwW2clsaxbGT5ZfRWqKH47smkV84LoYBCCKR7+XI/+FC4NnYLIekvPHwZnVerCXqAaalLodEfah\nN0ISUDnufmLX/x2doYj08V98tjMBeed5quzHCb/vqAIS8XF0uUPceD714r0vRTExS2hB9ThwtpDV\ncASkoGbzOZeizN8upRv8IEs84oBAv1VtYQNuCQT73w5oyy8OexljtwcQoZiwNZhMGRqKrREYCo6M\nAbiLB9PViTWYb3v78dKqwH02EcJR8e4aa7aog5rDOFOPkxlZ148JeuAyT+CMgnf57LBehoheemdC\nrQg3wx+LCRUmg43fsaBZHSvMb0hwM4JlOpcOodHJ+NxLejXfBFyJA8kqQk2tR7upL/nd5IPF3rpE\nzuDmaJuMzZDNo6Qp/hB6N+Nshr2aat6yXJUJXroj7Ca/BC5djocOrFCWZgEowPGsjMe1I/wijIJ6\nTrAYIACg/GzxySwYdX9dWYm+1dFq1MTB42Mg+ljWvyZonRkVWpEkBuU++yPBc32dWYHbCSqRMI3B\nPJ/i7yy0iE/1wqqebk6WyA4L8OcIXLDB461EnD5PJIipGFZ638y4JnrLVnpIqDRI6wamWqHi7M8N\nUWiHo7R8cXxJXK5GO4rAMHq+kMCLCyNqatOr3qJK/MmbgS4Sndb/+piI34OHvEzqPQTXqsOUuaRU\n2Mh+rxvrptTEIQWqvLwz7xCpyDdFF1Dxf6DesgxbkHWaFcOE6ssCm3vVuQOYgcUly1YUrT4cHpCx\naq9n86qf5RWpEvGLnVqAX2fR5w1eHjIwIxITbE1NFShUV64UgneZkeWcr5QCYZBH4uFMnsbHImCZ\nYv/cRAFoFP9pJ5EFnx9+BkjHASr0RPwRkjgRmidQCQmprPe93JEab5VapqOvmajabnF7h2YPVklL\nENCPcNKAE+Z0P40D0CxxwejIspuE2qNtQdZQhCaFe1TEakwd5uhEE8NlD935zS65aTWd5n1dASF1\nZCKMUZ0jJMdlFXtMMp0H4k97PA5GOhxkCONOuo7H6MJdZbqVso6Jwp1UZU16thgmDHb86GDzAsL6\nmypsxRXgpp409TADA2/wxnoATqPY1HBasZ9TUffimi2gZLxv5PBZ5RvVtUY91UFxEAzpFrtnaj0y\nc9EOiytze77ue+iYr823hunqzgwubVS/qi+pyJXgWGH+Q22njDs8rs/Ur4YbsS1dP34Q3EWVWyvQ\n1nywyeiqafVzLUD8kxCPpmn+qrUbD7omPGdV8OXJnEsGaojounsAzGMiPVVMtcM4U5gwSmFW7BVc\nzDyJYwti37MWwDzKgHmzI84KGAXcnXvVctJZGzJtgiazjRXRZs0A1n/pS2THvpOWFBgESGji7HTD\nChyYRcL2x1+2kI3CAC/AwNyTcOo12WgMEwVrU2IiP9DKFwnJa+qP9R0P0OJ+2r6YJklX7Ij2yQ6q\nMUwQFmeP2SIjT2QDw/mdhzHtz52yoJCc0/ChGtfcb2fyPPvnp8cmOJq6vwZgK7swtY1aUbsw8iK0\nlMMNN216zdyECxtSigTmVCRTcbFpykuaLYK/4SJi1QAJD3UEVkHHxdIXnvFLKyszyUvIjGPWK5Yp\niRoa+NDNMHgN5kQimuYNzpW73qhFY5tVEay4xFemMA+3hRpzb6E9881Kzj1f+M/Ho4nLTqQAIylU\nBfTh36SctpKKw5gC+KfRfYrH9jrDUPWW3hbdw0KiBTy4myxmF5audyXF9csV4eTrwRvXhvuInmHM\nQsBVTf8lwtCFkn0HBm9eAGSwWlQdofxZgcYFarBiddKqWq8i3XcOzlfZEPmRk/EOuIc1NZxmTwds\nSvNweFx6gNxD/j81DXBy0lGItxO6MKLwjsAA++5RZduz0kkKqdQ3kTwmEFk71Nkr0F3ouECPBify\n2xrPLtil5xQKp66STCeYQIcLYPFDslh3IWskpXoZcPduHPB3n0dTi3RTrDTjRAfX/kSXNap7HPxd\nvqFeyXv/Hmvp4YhtqzJQF08Y+qaUJ7CM3nNyhrFXITlM4I9g8+YGAeI5GPAVWdsFnOoQE2d59o2m\nbQFdJV/s3rsaFcT+g2icQOf2XTzPEEHDIA7+mgJbKZzW4ozdCMAHxDjKRHdD+Y/BudoUfa1fbZWF\nBEE0JXWAhtoDTyrkkqdh50uXqCLzW5H3GAHo4Dgmu56cM9M7sgA8Iz1KbKF0TBU6qixT4I+J3EPe\nAxBCkgvtEj/VT+NWHvESk0QbHXMaOCuvEIjQLMSsliEYupv4oRauuJKbUexG1LHto53Ox/1B+i44\nptUmgmwJqrRZiChOnCz6x4B8OKDit9t0FU0AufLcffKtDOr8ua80A5UgmId6hcJstw3H8JOHfE9W\ndQ99Yd2JvTazCR79NhavxbqhS4TXmwAMLGf7m5XXCfBC0Spb01Wh2RgM36sZLB0K30hYFFJe45ve\nMDXiiFSye+lPHCL4xYXAEedtIjaYb0IiLLIv3hDJpxaMCk/K40dVTnqPzbLZzRjaIgLoXYWtq5S6\nUdn4itg6+X5joGTzdTtfrQ1a0mEvJ49StP9KWicVZIpGxUEI6hYwI71QbyKpVDH1lN8Zz+uWmo4D\nlMoTs6Ena2UM04EMMgqIsqUrf+cabng1VDxfyN+YO52/4uEviC+BcH7lUx00Xaf7U8ckOiX4K5Eu\n8i6M0zWe9lR+osUx7WZic39wK8FPkjwF1P31O1RvNd6wO9xF2u2kOGSdO+M3Io7QzFpIR5eYy7SG\n5XNwB+TjJlxvMOZh3ytHtzQialmN+1fV01vAC5Oti8f9nsjkMrHGixTN2AIz562iYFNVkNRlpDgc\np1D270irx2ff6jn900HmixLrWEeWgPLQswOi+kM5VKW3sSKsGIFUUEywaqF+UDv3jyNhDBaWNM9e\nSSJ6QzmYRLkTHE/9ny5KJ+czMLPypd2r72zjKLOmiG+OsaMyY0EcFsyMeZI6d74NKf3T3KaOHjf9\n+fIH8qSyy8JQqna6I4JlqzZkPWJfRe20qAhU86Q465bLrJM2epI8GXCvaG+riTRNZl5guplswZ9S\nOMPgRuY8zfUdWWt+zt+8ZiPz1P9WeB3jd68lWSvZYjekmXM7kWYL8gntyKNDNPe5bxwmhajiXLyB\nxeC1eWK3HuDqDtXN+xqpvAbV1B5kQNhVE99B1T2/pYpXQXnA1jCAhU+w/l6ri2PktgdzoSCjIbr3\n4b5FIdE5SSICVxLLlmndnbq/QLDPE8Jpd0ALpjltS9EjgGTQTKa9I2TGQFAtz9gQj1P5mfH06L1U\nFlKK5bNuxFAIq4tA38o4deENWJ7ytJTId/+8uTqjRW7R7oRblUOYloCjz73sAHQM5/MoEUOGzzOo\nETxJEIZuOYZUXjtsmOm4fjrOl7BBwHtZN2v5yicBT2/THR9dBYtRb+rCmzkm0tuYDlUVN2zeSjF3\nfXRccUSmxjzrBdNux0UmrTX6tEf8n46UmEPoiE6EZx2Rw6vrB2ke8aO9z3V3CydgWPZCpTUjINI4\nFi5e/SktUIaLgPVb28L/7vgcUS3ANnTtIdqC/gcp7qM4GbieIc/LszLtaboIWknosJcq/oxXyW8n\nKHl4U8XQTqlKQbby42BNMvVyXojAZ6Xir6dzewvAqCTTF/TAugrUCkozNOb8zzdDFCZ/uBSAjS8Y\nDuZIGsblgMsHyLj2QuxQXUE/+BPoKONCvf5UZhb9FbGTiu2YTTGeHL61pU1CSsnVXD6uweDwvs0Z\ndFF+MiAmNUk8WKb0tvfD1oyuwb/r7bB1wEKpOyE3DWJ18BSL6FUk0RRSNvijghtZMMojEO1v0iT7\naiboeFqY60r0635YaLTDky1tTP9OtbXq7SAaaYYucIXpd9i2oBDr7uVxnXHLPSurcrOEpYNMDa1T\ns7U89sWTLV5sRmLMZUTZg9wIl0F/u2KSUjHIajKMyHa0Rdr5uZ1Yz1BVK/fR8SHQVf9CUn1CZYjx\nviEVbXd2o2BOW3VGx7kyY5Bz3naQgvumbnHcuxkZnU0zS/jKdvNj/qTXd+cXrDAQlXWVxcHBXV3Q\nVlrwyhhUNLEnaL42cHFpfmjQ0x8PWhd+XEo5XmqNVpzWDl9YJHSv7E+eDbp6xwaFBcY+zlF+doES\n/9I6E6fhFPC5a3l7pouqUy9lWUz49dC1ShV5nelvJ+cX7JN4B/nZx0ENY5DLq25gUyVLzEtO2/zC\n9spc85+0edadhrXfmiDE2OKyhNmFhVGJ9ZyoZAohTbvdQ3Hsu/Z8wELv6beEPLg+rfy56k7kTPV+\n2F2NRh+Zlt2GbcZ7+Z606r6GaY/J0p/m9krHZ+3RHG8I/5gwHPlf6GvpoxtwKHL2apAUX/c1grXr\nhSbRQpYT4wFrUeUP3q9GnyM7m6ZpRS60RL3Hwokx5YvazCD0oak2JNGIwEAv2DOvJDTpAjs2Vm3t\nW57jr4CUTJB6GiTOoECxm+iGQ+TTpjdQVBy3KmQaePCzY8Nl/mUaAhhSqhbsCxwSD87Xw1ROz/T8\nSS2AZLEl80QUa6+6JZ7qZ+Aav/JL4yDqld1oy9blERu4I1YBxaZp7fu5Kv0tc00tzlQphkCciR0w\nz0umOLpdPTUFQhBS01g/FH2Q4sOmP1SppQISGLSzXsCjKnrQ89u11qS0wcVUfcWm/UUC7Esg8b35\npR8RkWOx2WUIJPtoqSWpoiw5Sxnx2LndF22wxt4aV0sAIDuwiDDYreOMdVSGaQDdxEQUcl4/iJKT\nAH7W1PognhZMySlrtT/GtEAZXnVVCsF336PhMg132oRZc3okjbhfZkH9nHVKMPu0l1ziE5TIRsb3\nO32GFGREnMzi7R42Ajs4w6f17KFlaf/8sF2wPgc39+ZNpN5TmbHKnbu7CsfKPDTh+UPud+bx6y3+\nRgrwSdSF4t4QsBY+YnBK6x4W3rgNeJijRF27/M78ayfUXDB00dA8M8owZpbc7dPrtozAFroODbu5\n0IM8/qO+FHS0pFFIdAHxFvOPLfxd8pQFN2ruWG3/NSNHgF8Bsb9XSGoE3SeXspl1Y+HBm+3bLIh9\nKuOxJrHdc4fjbBxQ5TRF6AKD67Y3TOML01jO9bRZeuUMGDvHXys4eUaRUZkytCMbhWoFecfSz7ep\nJODc+ADTu0jWAfjGOZYGhHBRD6PZreGPsHyJSZkMRKcTCgqw6ExH5+4nQmoV4JAywlkmptXwVt87\nmTsV6hPEcAQp/Qn2/OxT5yY0a3riJ+1eH2tneW0ml/66P/hjDDXXBirHIRd4rX2IudX3Dv2Ryssf\nicUe5zOpJRkz4QguqnrQ7Tu46XsRooaxzDZKZp5aKdBfIVFtHFp5DpKsYsG1L5CLjCJm2ieIoD0c\nBqd5pqLJJf0t3opTF38oHeRFlg/xFBBD/oxtw+8Dxr2p7d90Hj+NbShnlrklnTQ/ZiqaTkUCEq0i\nW+bW51PLZ3psl1adwgT0uiaZvC2ZR9fxoOqSmNApEmIjJHzQUjIWE6+SyeiQAVFM5jTi/H2WThyt\nvTFybDH+QCcxTTYIPrYLXKpDx1ji4vyIeiWJkaUJrs4VUb8Y/DwrDnszUUN0ney/Eu12sMoQyn4X\nw2JIPfK3KynfJaIS6qm42iWBmcj6H6AO5t7yTBK/xyTaXnqTD+uZ8gLDusG2w/zcUgOumlq0XTzA\npAHoRSGZIzO67LCDu/4BpqBvdutOsMmRfnInt2A6uQkT6po1o20XTTS6p3rxKb1kOaiAaQQsg0+t\nKNNngbNxUOtkOBNmb5BUKNoABL1xUwmHGP0IPN5Uu5Gb7QlL95/GWEJfSu63WyfWcPAI811/QuMM\nh1Wg6h+t0LklrRdczvZocGty8q2+LMWlvt11X3Ap5ixURfQqtA6/gOaltYwGJwYXFN3MVNfltPdi\nVJbkNePASXv1Vp11CyAZj9laCZJgTWw3zMsKWyex7TjiK7XimcCnNYTfeRRLDiUXRE+v35H9V2E1\n79UULQbHI5R0+2sjQAQG0o2If7Fdza3eOZb29fPUa5M5AESUXcxCQ1yxOGxI56i3Zj4jGRC59iYQ\ngYaMdsKmLyfjuxK9pEXrf53/uWLbw8eyLo+FDICX87QVWmByLOe0A/fJvtyKKVKfWu1815ix6r7D\nFRoJPTlf/Tar3euAv4dYCKeXaFbnhHOQS+5u85+2Bax1gMybhq6kIgl/+2lV+ve/fueV8mV1W3PY\nYBm/hrAY69WDdYwSa3gq2oDzED62FJTOgdax78fusW7sbp7UqTxCi9N+YnYcbJPQjV5V5W2VI2JV\nKqLsOYfjJLGEQ3asUwW0DxzOKBrGKE0G0u/x+PGXofU4QWOk5BD9X/lvFfj3Xnnjtxu9vHu1jqqc\n9Pih2q8Ovj5gMYECUuTDcFKWeS1FLVXE5Ofb/QSKL1y7vXvMG8kxAiqWhXZJIRc6CLHhKoMkqSwP\nWxbH37s8MvJiFKl2TjED4b7U2Zn71zdU5kTAKdlcorilCoSuZKIxiMH9QHJWf0avayBA8WcManYe\nwv0tuSqbngjFzWnRx6Uef/hKh0NPJTflbiQnUKeRHtZLHZTlqp+PPBONrypSf3RXg7HyToYPBryd\nmKywa8Y+n9H67jPdKt7T62WKT0mve32ADJpCfwLp64eUsnpvwL3ETpV+MJiB2/eiJeEHjzxvNXod\n29CglPGFLoRmtw6FyIkcR/iylAMPy3KhxdnzaPBxFVEiqFddk3ljmb9xRlS1dlBkkGxJD7kZnAYz\nU3NWRSHUN5LoLkn2g6c9d8Ufj2p1jjqV5EfwrW/ibPDkQVXPyUG+DJ5gGZLEdLTgdA4y109IjPql\nQXx65CouywrHBvS1r7i+L6w7Lb/BfppYhWMzStz+079zNrzhn/QK627fDoa986HrXRYspTsfQZhb\nboDPRPGurvr1KdOKpSOrOf4rS/lWe9LWWYK1Ebn9Kiz2iJhqLKGZvfYjn/tw3wAIgKQzLLyb0zjy\nasbKAgqLvRq3gyKLMNyWC50rS0ACdiH/yGh5RTQ/asa03ROXiHRbHk1ry49i7D/rX423p1ZAX6KV\n45U1uabK0h9c86xguZjVQWKB8pJn4mIYGM6hursUIdRC+K34+fBWz9pSJiqXsdJy8vtDwYjjkou3\n86yfAnSPIbopzwJ/9XcIor2d04ujRLoLB8vukW+rCMf8dHzTbZIsL/yOL9814ORjtIo4qyeoImGl\n3gRTt/5l/6+h/X08718SK8oEOhOZ3neyTUro0P516UovveelSDQ2egxf5pi1DVJh+KFYM/30c6UA\n+SBO17WMH39ApOBc/GO0px8iaPaKaaXi3OUox2CnsTTzO1ueksY9s7HTzc31MdXdcI3gM19Z8VWF\nfpEy+Astbk0m1HExb2lQTe+SmjcFODU8AxkjaORtbnD9jSFXGm/2KmBC9lHkoDQYg4nJtywqzDcd\nR7G0YLaZiymt3+IMXrErJCPkGuH4KeDU/4NZEkNqOFIi+jORTVeH923Np+Tg9G4sAXBPIKIfH2Nt\nfJacyWoiiTaRAFcVj+uxbr2TZSiD3Ee9Siam2bj8wmdgrATqgXUI7XjIekYBBvP/ATcJw/xOEraz\nopsyP3jELjWAHPeKWsea3iLd8poM2NpH5bf2teNr10pqmimN7tfzlVHsb/Nux3KhYvz8RmbLJxjL\nfrXnsxOfRAVyJjySuiK+867nG5aBEC8wCWtDx2ffhJ7iOYpSlCD/fw+BsG1llJ5k3dm60LdotAl/\nAdcH1IklN2V7M3TPKIMNOTSkP6/8+XDjBK/npUof/bCmMpFb6rvJENdsWGGG47zCcNjHRp/cdKMo\nArm0wK/+3mbh2Pz0ooqt0sj49di0v8Q5Ikg52XgXUaeYwZibo2aH7LPFzfcrDOCLofqD/QXtFzoZ\nHisRwK+q3bcL2VjidVymyJRoHCeDGv/z0hTUmxJuvtwj52GEzsoUolSYODscwcoUOQoSfo0xuEGb\n5V9wu0S1gu9kBzeOrk9b8rkbC3ZY8jCECrRkGKtVQQSA2W/HTR67Krwrf1CRlaV0dXVTdNFcsBU6\n4ql0Q/hHTINsJ6ptGZOmY2yCefq+BJdLt8IKMF1WgToHxGAysjJG4V9J+zVV6gRKXCa7upsuUtxw\nfUCFWYJwWUog9XFNxbBhcpTEbokf0lraRsbtKZ9JHOROTQYrpR4+5ONlkqD7mKDv29BBmRoBS8Pn\nn5d9w2iSz2iVf0xx3lo9QF7L4tukY0xTjxr+KjJ+TVdxuNfMi+R9vN30bx6jjVTgbSt2/4v1Eh4D\nW1+/R7w+5u2uXLdRtp2Y0ABG25OVDIKTDkmMOa8o2W3Lnlf4KpG9HuhzXMi8Fd+NLda44zxN45vo\nmLQ//VcGAl4+s/so/8kmUahbNTeCJQlgQ11ppW0vvBfYNFpHDXkg5+tgbzXDWXElK6DJTBddqW1+\n+CnSTZ/70rFamqVkxDMoQyhQgYskiYHUiQoHQ1j2h1ZaRls3ys7TWzqlM/qeKliQFOco6ngWJ/qA\n/EZUAb4VHBWyCbtU8oAw8IyO7+aAonAk3f4KLdZUdTsStJEG011gR33XbNPtVS8urMGNxprPVWQe\nRobZ46TDzQYAzfnIPxmEQ7MlprhywJlm9X5hkIUhb/wFYJYQd08xNsuslvTO+5iGWUG/T9ftO3VD\njJyDZVjmY7wWxnVJ7PrTmD6xtnc12xICgqGuk3hZdRe2RCqo4/2xGoEwOXI0JC3I+D7OKdrTgyoD\nIHzYokEesrHFdqIyBEStERBMXEXf7SB81JAiC+0tsbBvsTgWiN33/eB9PicsOIMRO6jqp9AtzA0y\nqnj6rplLiy8sSaK08xfLglV52AzFNdkt8OdOv7hpj9cjYClXlXz9zBCWhuIILfuqWqS4Hjr9WFu5\nBs7SKRpOsRja6404MleogbmPpLmHwJrEgQjRNP09PSF0j0adER+T9hR1ubG4+yuSBC9eAX9t9712\nLPzkNcxkQIPC3Gs/LoRZB0txw9uEiwMsem/a+OxgqjNZKTUn76sfQYPCR0aR5r/kxP1ZW3UJRKvW\nG5BDP3lBH2brNdnRnlCPbtd0ryjqYFe2UPiQAvlAk5T9rN/JTeAv3poKr5zbNz1d/pabLDcIYmXK\nSmoVB3SGpHX76qtggPf7PdVCmnVbyE2h1yMcujz7E3wfmDrocaGOf9KagAPXhaFzgXPg3C/mld3S\nJakGRUEc4qJf0vgaldtRoxDzFLrIz7rzx0OV+80Tey2JLmkXXKA31qbiHtDLKp3iyhD8Xbz4LFnI\nCK9TYedRwtHyGV9NL6fe0mekwElEziQ0y9L/PF3+iQ+daqBPTk0ZOWPSrDzfxvZsxXW2STLiwm4c\n6aeEHMLGvHL+XtD47+pC7cYlF0C0cHr0yf6SKeLYE9FxLOU29BtmVECjeuieQVgjA8pQCZDgYMXS\nDf/P0ywLevMo/6njrhJxs1G7YrDIVQpMX36Zi8iTNJe3F2Y0Wk4I3MOo2OH1BGLxffPG/X/5TP3R\nz8lpNxbNN7xJ0Sq9SHsGoJrrfRKL5w44WmWwPHx4WRPI+YkUN9q3AMyO7GalQ14kCfyEC2aksnku\n2v9qyXaJL6YWEYQQUAG0x+6oaT4I7JBK/SQU6r7uGHHgYXunHaJNR2mH2rNyY2m5HWzHNjoCEHzb\nJf1wS6gixMsic8CeO9yeq6OjVhSEUbATzIZ49MF3ga5EEhV1OLGuxTA/0XCcow1PISMCKuvep3iK\ngaNsfBzV2Kwa8ghrsXs/TFp6KazQyjE4DdeiPhGuolvbWppbce4kEAVF6VfmF4RVuG3Ch2jES2Zj\n+TRteV407mcN+eVbLATf2i21K+0oq+JjPFD+/lTFeu9PZDq8cFov/YaD6h+Jb7IvpFdL5IFH0kb1\n/hZv9wpV2tdiG7L6uM7LnJXgw3J/sNRoQbQgu9iRRjozKXBr9ignZ/ipNlS2w9/8rE++LNP/TGnI\nSTIlDbWQ6oVMZ5nmGVLp5t6ofeFgbdIVsdqpvumNWiNczd8zAeVoq9RGtYJiyKCHzzfDVC2qnwWC\n7MjQLCaSCl7HWipqG0vjI6gPyQFQKSH9zRwN4nmRcHsgDHD3u9dZoBk7CPbh5R4oMYsuOf/zBTTW\nvg1wktyGV4XH4gz9IajViDZTpLfAGgQGeB4CvVBSFvDKGLktk9b/N/wtkklofhS71EbjNIknb6AZ\nxs+JRvq5bhGQEeqv9TagYKmakT9DPmZ9323RYgf3QyFU9BrdAnDtqQBaZhQ0pch+ZY/xJC55d1WV\nw3ah2eoDoetVcgT83URvR2xSrCV+WVqQ77IuTl2CcAk2bXRs2Dqw1Zw9+hrai0b9Jy5UpGhChhI8\nnD7w9WqRHB36I2oQbxVGR0buJn9LRddWr5namXuot9nbcu+vhB1J7pPidpcTX5hmlAftgmTv91te\n5bMTi7Ste3AHt3EuTsOpigZpXZzmsTJF1E35U0yVdiGKPe9ZSzrENezZgSQTJGiJH3hVLVKL5OIu\nUzYs8kGe3zG2rhNOPPPii5KUFv2dzE3YghV3SDwjgTx5I158uUYFp616pAstjSIOiToN3KUA8sk2\noNBe4nDDlyDRHmkf7dpVTW/0FeWfnmb78ziqdONfeayWOGp3L/HKzH61V3gRFoFYH/fuAe2zSczb\nOPcKOpCt10gTX58R1X6TJ+MCyV8yEMBU4OXFxqrXvGVTkrOA/oCiryvuq6gmJzHreVK6aND9F1fi\ngvZ9PVa7nEWbd6RO782eoArI6l2PXA7T5OZyWsDPQKUevB72BGSfny0FO5XtdVYjBUnKgDJTQGJI\nvpI2M6qFc3/EihceUkodcqLxT/qsk2BWDyDYepZZbPmUPQAX6N5ZQ2ddGyetJU7WCLCHOukMz2eF\npTQQo26dkQpU38IBXga8OBsBo66P0bWlPJQWnjUImeLnsD69Tov+eLs0cI+nf3x+HnP6CA8pYgMo\n9a27UFL4vOU4hKexVD3Ca5Qy4lnzbh+HzXsl0ssAgKp5lViiPW6W063PJSZzjRelmRvHMKv889qD\nZyhW3xCM60Fc5SbjyWYRpABKk03hJGo4p5W3k6n0c5p/QksBOIxZEmc3uHd4+KyVmsaBEeSPUIrP\nItYY4u4JZhs0qNLq7o1W8SKBiCe1aEtlA2aCFgt+0US2urY91M8TUHgW7mkgzME695Y+KHfkYFdb\nfYdfq5tkUvJoFEwNHmV+P3HfAxEmPTQwPJioq3t+a641Sl0vXGnfbzY7qHZ7sIRu+Hst4kYp8VRB\nLPCQzaBEESoiAG3byTmydnYQf3FZ+te+vh7p/u3+MZuDWRZln9eIyEiISnk195NQe/b/GWXz5vyP\nMC3rhfMccoTMKqjCUkKdsk4xCdU5EjSGuYcXbxEuTGzBX5hvSkdGg2OiWnShzR41VFKbUqQDIU0T\nqjwPWG7OfJIbdc2paCZ5WDtfuOgpkbFCQb/ArrwL7aAtpsLMYRwxRGJb56g0r4XyF845NyYZuzRe\nbscEkkTpiweva2k1T3cmsdw9xQ2lMGlc9Coe3P2MRzZRPP3SNDDl7Pz9Jq4UPw+d//0+2BxFqbj4\n2YxNYE7Jncc1ZWncgvBJp1sqvdVK3/09KnTsqis3TeLFS/iDJQcVYkirm4eYD8cNy3lgpmZSnaxl\n7pJnRFU2r5TG0QvC1MRsU0oehrKjj/mGNUVlOeejdT6o3LL2lW0aEAprhNjskvqrwPmkYo9Y5Y+O\n3WuWib4xqsw48VGLjeOAMoTmwAjqQKjIuUoZN+q9Ojb1Z7ZTROzrMHpUJ+xFc3CTGN12JzCt9cr+\npOovm2cbhLuuFvoGnDV/YzI0HIYog/aN94xzieSIaSxRpIZYvehBirx8yrELSLUjPWHP7Sji7gpB\ny2fCNQ1lhkpgZfUB3KkQH8fvvSRiuqYGVVCSzFB6IlJlWs+EaeLPMIU6b0LDON+1LEZDhYYQ3JDw\nXNU9U1ecuvJVr6Q8xQgx6ly2JMsAsGN8NR8KQjL0eq26V8ogpva/5ApzhNA+fUPfsKrlIHtAtTAb\nrIe6iJrcUqLVuhD6B5G6/hfLZ8TiNnAmBLJVK1UjyttOEIayig4ffyLi6fPhTwtQdchCqi0vyUlZ\nnDe8Ivqgc4LqcsqFdAn4kJHuxHSO/6pxO4zzYizcY/his5hIkDF0cek+F2oYF+6z2QvN9lq0nb35\ntcl/U9kSfqbZax/Nc5Z1BQyaHoCQTAlI9FeWyD51yK4WfbTErIewC/gemZHpdX4bZWS/Duwc1eoU\ndTpWuUuTmXnEcd/7DItgZdBmds5vmYXEDk5EXExBBHQo6BK9d2xEry04yOPbpZ/LJO8IfLE9Bh4O\njKgmwkIraV1CbWo3E2ItDFkAaF0r8+4cIircsS4dUFkBHZRCEE4/2axsND1M2f0HRuLIKlRt4Sk5\nIMhCWmKA3NiC/jf4iHXn57aBR5nsXGIgUjo6x3foyHWWRDkXRDJgFwoI4x0qyvdUbkdZ+cmOLqxx\nJ3QEeefBzsJ8btyjO93yqjWNZBBwN1Xes4EUGpUbeC6YtQDvmUUo6Y5Uva5B7pxk54qscChv/wGF\nqFNy9qinJMCk/tkxDo2i+QUeRiKjSnkoTrjqiiEWcBMaA37M8qLxbMoqEjl9N2QcLBJQUaK0Uh0J\ngATZ36LN0tGgaDUY8yF0eLzFK8lWc+AHclj1D4ZH9SOLtJz80pBJyAjThj7BpLfkmYjuqMt4YRO8\nhYEKoy8IVzr4CguNIY/Q7fJ9mC64B3N5JfC+/FcXPufu+HRaFVq6AZEV3b8VviPw7gF9ci7nWMUy\nzzKQE/pXN4fiRoqX0RwGKUdmHNGaHfXiexsouKR2jn6tWbKLCLNunIWZU97uK3gL5pn8IjAB2sd9\nymyMuXTWUEz9tyOHziA8o19hnvXbiQXbyu+nUA23ylyj0F/NMQcmYUyYbT6470sPp3YQ3AJunsha\n6+SCUjQIOvCVP0HAHatGeZKoiy7EITcANqgg4sAltsxhDo3qBORdWtKUvi0RUp4j3GrZFmOysFGb\n3F4h/m9CF+y/c5jslczW5aOr5Fslu0F53KuHf95kl96KqvzNlx2rS3D+Be2xJB5V7ZsJ+rVtT8P3\nP4KWaTmMr27UmNsiO7RiUI63B+Zn1qTw00cdYnO8dtpoozzNpMg267QQPbzPFyJ7u/JC61PKKzoz\nGzMcdjlscN6Us6Z8iq3EVTAqiLgydDP2PSPaTfREVg6BndvsF/E5juCVkDSzlR0JPYlRwTVweqlm\nRqezqf9Wh7Z8tQreE/ndFobG//fM+yxhY19i/YkaBac4s01UZEVl7v91N2VgJZ4Jliu2jJ1+XFtx\nZ2hc/KCYEK+uw0DMascUaP7PNVZIpD9fAKJFRDz18+uE1EMdnkQQvcrstkp8wFJNTHN91gnSxkJF\nZdEeZAZgo0eQ0PatTqmK0FU2ru8z+4nu9ns5Vrmh49AJnRBhWXhcMT8EL+L8vCp7mokpXLQV0cBb\nCTpCLgPvJ4fqD1kZpt9V6HjQcteT/pSdkSn9KNYKd74PsjF+knxOFd0M104G9bgJddPR6Fr/WbvZ\nz46tsuzabK2H5T5fwzhN5sAMSMUmhDhe5+AIFkeEMz059Zu+Y/q+/l9ruYjKOwkUOtbhNfXNNdt7\nkc3oWcgG3gG/FFQ8UCnI3+AuCH+7XA3lQ1GVBSsaOuoOC99AHU/T+v3rQ1ivKuQbMGXlp1aOAs2r\nsu37NAhwVFmr325Mkol2Qbmg5nIDQyS7sqRQpWXyRjTXD6iQNbCXs3hNXQ0kCUSQi0xXw4zZ/HVr\nAUZnZcdr2uJMLHIfYZdptfu4ea71cBscVduO9BgMRH5LWb/y1kbKHCV7KzBEhxcHbjQbatdwvBy9\n3kpTyHVkgFdwRIpSDA/1sYdAPuXVktpJB6BleF5CGKA3w1363Ef0VgFLxVxtMrzHi0nj8M67g4bc\nR7e/8pN5TPH/QAfLD6WhCi/xrnda/V2lKg6KSuj55wNgCF5zxfMeH1cnD+IF/CdrxA58RN003u2G\ny18cZUfnbM8ujtrA+Yc/bkNIaIJG6NL+G+L9LIA9MIu6mobCru3OTqFU3ZO4elpalbbOo2vZ7jBH\nuJtNTDTFkPYkKrj6/0i7Gzxw8Qpv4UpDorjnMHZIXdpSWIf+rSei0HaDD2P44FSFL2IxbZQHEO2Y\nCPpKkyssWyLs+IMNZnu98pa6rE/gmgFzIzKtpHu+Jeul4e2EvbIEUS5EwDFYMaM9cebruvZhjkRD\nCfUodJtR6WoFM8crE/9+TiXZ/OB0JBJdashc9npmfbdzdOXmoCVFpiQaSEU0pyagSKG2GfeCmbJ1\nf8Jq7CEcZwNzksd4JJWBzYbBND0r1MIhGcOlhD0XSpzVCsimpUtdtBVTfm2hjFcwX5WWIryhpZko\n8e1hOgnk5PpHRVxJkMWwADBTUdj4COPZReGzb35lWg6dQqTMEHMPxnV+nHKo5I9QNj5d+JXsZXCk\nZgCu1Ro9nHgaEg23MwZPxEDJ8RWGbfmKCtHNXGFyZJNwbM27PijpC7SNfLUM/AnG2i6YQGy8zEyu\nm1HstuTsopNTcmVUYU/my8nsEk0cu6iEkdByPsPcMTHQUDKZ2zD5pXQXAEatUuuXXkjXNbRNwuh8\ntQuX0Q1msGVJADCXjMGa2B212LmzUVZBr5wyKTL2pb7u6Yz1DQ4/KlCHSMlpfzxNavZ1R9tdP1rM\nfHoRfEFQGmgeuIV49TS3tCHJp1aFiVy/4ouAuARiXFTKEv0nQ+nkoAznnb9trnYX46Wr+TqfipmV\nY22Sbj6xOBQ8ThUzefGv/XPbC7ADKe44IJMOD95WcP2Lf7Ic0GBWOWcVhx7WKoxy+IdlHn98Faan\nyw2H2ILAC04YqzI9fL6+zTcmQVI7UZsbtzKPXNpn9rG58tEw7RwhPrhi2SRLe8GD2p9ZCEI9HEF5\nttPRLB8aGL2ckh3ZRFr0dzRTAH/+IOQKvZOyE29UeJz/bzq5yPaN7dFGBEvAmIxIxZH4RGRX4ARy\nNefgkV2uRSTOgqg9qd8lNCOvWEZOz+GHwfHw8dO2sdlI0vcuErnibVGNo10NnTzc7/zs4xo222hE\nAr7ENhZc3twtokLwzjoq9f1D5hh3p5ck36WXWNDSqUT1Fi31pkR5eJlOU89Dh0WifrUu2AfShLyd\nxRcZQGSe+E4PQZ3eKLIbHvw8sc/R6KXskrrkCZAgeVYxCzDOH1YcFgjNG0leAE4yYS5RsFAEkwVa\nttYmbnWOUvy/rXsDkdnRM4Ccl9qNTYqQUMxAAr+icN4GQzombw+bD0opIaAE7qGptMRTP4FW61+R\ns5SKGgKwpnl5lj6e8fDw4g6i3MOUhVLW5QOQ/INQAcdBQqLHdLtSusEF+X8zUX+8IiT10qGTyai+\n7HbmuxYNVrhWimChoI0PfSFfUM6k6xs3FeZsIazdOeHQjpds+0cNMYSx32kM5jZlbT9RUuRd+o+q\nXBdzGEzQN10fwuADR0Nmp30M54KcpneR4Kgg407gjLGnIGQK2yOvt698WBfS99Bo1aeTGc/W4kCt\nfE6shQS7ZswQWGitHr+Jjtb5uxjXrrL7ABV7xLa+/LTEYnhPYq22x/4SL2m9uPE3BDVbo85aM1Tp\nDdNIN4YRmwAceKS/UOkwsfZ0h7cmQQdllVqqZjUWC258mrvp9Cm7kCZJomEmARUOJdeDfhzvZ0dE\n/ejdYXbl+hB2zPLyJbCEUIYnDZDfbjv9cFUQ0il2IcIxQ0Utu9/uTS1GJOuiCcd1u2bwbXQ4MgAf\ndplCubXqcyVqBHuC1XJ02sOUYB90q0ejGAo5zktrqYKri6ZNV9SxSPgbBZD3v+2zCSHieSv/mmIU\npdBSHyb+A/WhvohlZwy8Yd/9Vc1QvJed+F3N/UxYFeLlOdGcHRM9KJZIDXEvgPJPtXZc1m/eh+ni\nC8Xyjv8/Q3HXBV2tX+Wqp+5ViyBsBJ9QpSZd/TYx5gX/5KQEPtGc97wdsOdAPj8I86ATfcLECPqe\nQ3IfOMDcD+ZWecHRld2n5ILnnXGnbhqkgSQPJKItqPwXOdMskV+RhzuhOR2IIi7irY9VE8udqkPE\nSnGCDGyyhfGanB0WnY3NAVjgct+NioJtSMrDpl5BSbNThu/nmtVNWLj/KfQjZ/PX5Y9hPUUIsuYV\njvEpTtWFsR7saf8JMD+FAVI7Ngevng6E23JcAYZkakYAkGjfWc5y4Ingk6gsbKbh61XcHK7Q9sDW\ntIW7I2RDVQ6R8EEiKKgH1BuleGsTeFpccXS1RIZzMffuGbxR7wbY8Hug+c8LSpp0uCblDhuyVurA\nB5CjshhIbKirOrtjUVuUR5GTlRyE5S24jfwl2t6GRzIq5Fz6MXkJap5ZSEo3NSLS62oVJ5rdy5An\n4dHuDVpoqNGqvzdv6LH/MMniuoeX7dDir875I7HBMzkq8UkHGos1bRROG6lqHnXGBl3qS0igZzhk\nDSzDCQLDDKWrT2HcOx5eD/cKNtQZC954HWvaCGaDHWyZKZESZqGBzGLhor0RUGwKXCjdW2t8A3P+\nCieN03kwvCd6jYkhdL3IHNTH+4VRSKRMwT+0/mbJIzUmsoScC8+YOlEd6i7sEh3V0YcY/8Q/y1hc\nJesWiY3duxFutYDCO0tVLpCzLWQmjAzYqhgEERkE2r8jeJBP+nNd3kU/p6ee5t7NJ3D9EKLes7+l\nAOaQ8DCX38OtnGsy4xoWI8+fH0wI1/6N3/TcrsdlVXotAQ0Ls5PNjFpwSqgD7pllJBTwaXSfO9D6\nifxUfBA0FizUhDS4VRejgZ8xBWgpkq7C8p0j7FOGIHl3IQrCo0kAlYnSZdMf4l4mx2hph6XkzmgW\nQG8yv2GSZll03v8nZ0QSmItD/7T90fxTnmSdtYxrQqMdaYSmuSyAmv36mXjFCNCzVZnBJas7+I5F\nx5im8aadjhG7/2IPcAV4ZDpGPUGMGS1Yvx6B8eTwWns60fA4JDFVzvfvJyn2lIFp9PacMFTR3huM\n0Sau3HXq+7LH8/druoFGoe0QrRyP43b4LJZygcRyItNILVtBZ1B0FT/BUFleQYWSBWR4ilPpq9Ko\nxWDoayUTV+F0MEK2yadJbaknqvyCXJuTZdHuM4wALI1Xzfiisytevrf31WgKliFB6k8++nk/Bpoj\nwlM7BkpDR/fu1Ca00b70hESIaqEmTX5Ddnn7UHPHy6Dkc0l5Q9uAnfRlQTUUeeVtHNF7IcSuOd3S\nApJDKA/TeiDsznJBDJsT9RSWz1k1XcFwoemvLiapd7k6q+hCUSq9TKjnNb3HbV3XJf9XGni89a95\nxVkigIWqu/ZSauc7xN2BjharWJAgxKNjCOXm/R+yWprIjexsfJzh2aeXuXPipXDCxZaauQ2IDutQ\nAhh1U5IBYrwNkxOihbHtl9g8Hwk2D8UXH6g008HqdpkAhDZXwZbWf8qFcNOuGwBGkTx6bl1waE2E\n3nekRX1KmkOgw4cGxCFs/E3Ycn2rhmXqapQnw5Gqcx/B7CUZTrAL1iXVIktJMWlwagyfUSsEFPCu\nIT7hQ5arXX6bX1LocI+EQLytGo0KZPa12o1l3xlFSYY030zmmj7VEK8tLIVkY5JOLTR2Q2ZiVDzn\nDqztaZc7hAXld+tn9OEYRhwN26Ew+W6sY33dZdNCma+/96shVHhGptW9Ynqu7xO177sIwJ0QzwBK\nRzJs8tbIDHoXeBhm4Zbos+cXmWa7HuB56Nn5tDZQHQh502Uzh/ejGk3ahUcEvNGVcc94BV9OBqa2\nwpONdDqHZ22Qjy+/7mk4xGa3UnyykcInOgOL3yxP+sZIw0XdCDgIZ20D5uzKIKPX0K8xc/+j3tWz\nPlUtlqJ8UpGLEtOWntzGStVPpqbqkXqHQ4BMZ0JFgYYgOX+a/zH4chEQqG/o6+nJx+OlxSmX484M\nY9IV9QenUPxGtFQ7pktMKsWG9H+eLy2WA5DhN7emVxGFLo15ObLgxqpaUVnT2ndqGI6+YOOwTNhi\nbxm8gqBFL4KSJ+1KquVgxhAWfptNnkIRs2/cWHDyqjCWCz7IbzWGJ8VePDV/LPkZi6qmwDnDIuHu\nTrN06Nq//aAhNVsU31INk3NMVzioYTdaWlUTs++X2Rh0x9449sr8bD9Mz+fQoK8+bn6c5oZyDEeC\nVGGYewItgy+4Ko3olqjZmDLI9lrzX5rTvNRjx0Ne93MS4KU3/hCoklFbHlUvt8kr9eR2AFjMxlY2\nyq7AcqCw7yMVzdHeztynQITONwJ4q31cAkacJTlUFKPhjpdGQFsfFRrfG9Xuflu6sIAcWHOm5Kjv\nldHvnoo1ynQR/mdXIgJLGyYZnkGF2PkqSbGA2EzokFdO7YBpVnFjWl0a46xjxoufwC2ZsabmxXF2\nzKDHDMVLrsV9n9uRcEK5ENopSeFPca+fve8hkWcU9h/yDZx2CIEFRWRFWxG9/a46Ao7WztngXsjc\nhb41hQ0GcSp/g+QGo8pj97EpwfnJgVnJxDsAE72tYCT9hF4uYI04KD/WY0BRxFLJQEtuoU3NtBcd\nAN9dmwOiKWcCGdcGWi/DyG9Y24UKnT0qiAoleckhLOhynUNLzlhP4IPkUvzUnmNRrptrf78WWguA\nMJyzbD0unFdGXCrlTXUWlQu76jUaEzn6bY4L7X4Tv3FW9tifgCQZC+eglGyIK9g3N6EgR6fWxAX8\nlSI/YrXk8KyKwPwCt82hA9N3+BafCrSeAPI0ATw04CLtq0nYfvDxiYSC480Du55FKEnlFvVq1Tx5\n7Q5WRlvetaqqw9iBKg56soPzY31oTLtUTaMWev4KErREELbpHFAC080AJwiGUiaJMOFWXMrBWilA\nsdgZEcX7cbw+11FiOkd4upa8AaZP79GVb1n+lMKWdWANf5W3zyaeDu09LfgLE1vzEMKeoiP1y66F\nyHTZAvoX+CR3bGUumfLyU9pxX73f55HZJuGhgBuB8MEpmmusMpUDd5I718Q9yzOP43aeAqbNJQkK\nBMCEqj80Z8SLElBxvaJx4eD0FpaqPMwY2pRfZef1SI7XxlxcqPfY0DGJwiqEjGWsiGK0PGsks+gZ\ndka7ml21c675yFjFr7mTuBxYwYw1nBplVD9Dt4vsROEQ5oa+fkNR9RtRhcCzeTdTvvV4l0L8+CV5\nOiwt+CR9GJolVojf5PjbL41GCrjRiTSs6kj+i3/IeqiIQ8R6rgqAzKkj1Rh0tsgGf070v0fHg9hi\ndgRYhGGGBxxYUH0YLbwvx2QMH1Mf7odYSG92Dy0JqGI2g5jPwCTLoePpLW5vERBih3mJ8lne+glM\nRn/PYR66g33tWiPpzL57RqnzY+fhvF2C8I5CPCLdxSJ49eiksDIStAzxuS47QodWSI2pnQ+EmsSx\n1P3P2jYmCsUT/M0rb0xolmZCNichkg5hdyUyjK7He048lUCKebUnCF9Nsc4FiDb6fL4y72yVsFtI\n6sM9GRAozWA2/mtvp8VLOtsYaGp822fEZqjmK0/jWKpguY/XEsUQmeA/zOGHv4MdggNBCNupqFej\nl8NLPeTTsteKq67ck6NDqSirPdinNzfY10DKKdUncOTx8Sv4L4vmrxewWBcfy8DdafRTHIzQdaXT\nICDChEAuApPfSHPgWlw0DhXggxA3KFCCUL53hf8JaKcUzmkLxOsxSqAvwKCSYi5thZJufk9cVojg\nPdUfJAgOHpyEhYEvrSCh5C6jJJqE9mNxMIKrFxxaqrVzBiyZtxQzcLvj4wsn6xsyX7H1cN8WLhMU\nRVQ62/mZzXg/bB8EmgsAcaT2tGXCvW1Mqp3/TXAdeBRLmF5AOVQJJpWfFhbFN1Mj3L+WWwVw0jHO\n2aPeTyfSQjtjKFMs3dB0tvq8s7/FytDNhoAOgbtCIIip75Oe0DKUaEtYftX+Tc0q5JdIqvn0Bq4B\n4q8s5tnowmpdJAJCoRDYn4KbrRgQBAr/FiB5pYZmu+a+CbGjclNUj48lhiyV/sg5L1PKqw4tS/lB\nyryIzUC8HFl/BBy2p5/GemPyQENS+81n3YjadXFjYHK3iPxHM6pJQMKV7W9c0T6nUl3i2YmRrOWb\nW/aNsin5s5gYXTdnsHdWbKhvdjc+Hb84yOltR+zGYlqbxuvhZ+0SeZJ9LaBpDXtFKLOeTlZF9V+V\nC7lk2AgZv+xBbGRXttlphfdz76HxKJOmHpSLEFfhTo9kPPLFDfGXYz+spctYb2Fg6qovdJlc8f8v\n3aDlwd/Gmslzz5PrjBZhETDir0iDSmZ5aT9vMzHCP4pS7/kp0dTltCIdzViSPG/xRMivg0kGSFnl\ncuXNKWqkhePN/Pc781AfvGVJYrPpi2OZpZ65PFIhFvaBAFvY7Ue6GBABbP2COyY1Fbj7cUENkyEb\nez+XQkvnUkduUkFXArWACtj00723XYA3UGSrC/RDnLHjLl5hB92lTjSN/S+l715ZYctd3fUTlfRT\n3ixDKyzOXjr6x6VLJYec2oqOqwH9rPpl99GBCdzDA+X6gnlvJ/cMOPi5bEF45HNzVJtzmzwXtPKp\nacEmHIL3eHEF83yfrb1yYpMlG2uV+b+/hNmxFMsR+BiwzSjQyp2+m9BeV7fP1P4PwD+sLRMM6SsG\nOdaEVsOz3OfguzIcCY0p8vKe7WbQqSvxx1tO6FdRlJCPyPqnQCwFFiEvKYJrtyPNNWXaS5/++JwM\nEVF2HVQ83/wWqt/zkBwLJ+ht+ulppSQhvEQ59fl7Kf+yNQ7HXbHI+VM8XF5e4AGHXtmtMAAgSzwX\nHkJEXvgk4M6NP27UOXa3qXDBAaxynSd4Hhxo8set9ph/lAg0GaPOAoKzmDKDFmmxySJMfe10NSh2\n4NYSiorAHdZ8lq2Hmm8oKFiyttdVmKAIk1AliTsEhJ4yxcKEBftG7eaZ2kvISlPXtZLRtaPfeEMK\nRFcT4pCGzti0TdSLhD4fbfeWsxI226JQzvC89/1EMveu1yT7BtVPzKQnEFjZoRa13lml6W69ADgR\nl9NlziksRbCZKJDCLKwRrZt7bnIDcWzij3kzlCaek6mZul0kWXRe2xAHv/zyMcUH3ctWSNTo5/Xw\negxyp2HMS9hQ73kngBOrmR3Zhhm4M6rAWUv/Hmd+kf4xYv4ea60v9i4LQ5k/rDCqfbmZ8DfdgYYa\nVrvdPlL8htOWYTQQHw7Js2MneUtVLQHIt9BrC3E1OakORAEs5s/XIQnHNJl6ApuQf4SiQ5eCXkrm\nFyh5HRpbljUGLzrVx3LneWYLVL2yIxajr9rZUGr2dNZY5mgFLDOtUuHQDU3z2FKqVzOseLf4LhqD\njz8YJeMqcUfxBxRXC/zh8Si+JWHODRXJfZghaO+fZr/aDScvUEX9NjBQkpov2mA1jFw00n9Nj4VM\nwnKA2H66hhqZKop1etNZ9K9w7zjQzI81NpILyQo4rkDt/kG5diU5g1gUscI1J/yMAiwvmupMQn+/\n8jauU6TYSsHTCDYk9gu0tzqOYOQcSSkVNYpFDyN/FxKMfB8Ryyiy/ALDvZFqCKAh2BfCWr24P9HX\nmiLmDKTqcltDEs9e94XbZ5uh7ufQhQ4ueHzJFdeuI+VOMrgenTmJTdBEBu7FmURrbKmzz5xD20L3\nzdqTuo0HRIHah7BI8p5ratdv+0e4vaEVihGHiZUOCrx59OsC0jEr/pKTdpL52gytko5zAaU6SR0s\n8QmsfA49LI6pc5qyPgxFf/RnbuIPWNz5ypYUHXwyiRP5Rx0MiXT6dmwuLYpVUyeWToCMlvPHzTWB\n/4HdPbPFXgpixW7yb3MMpuug1Gf60Zt9YP/BlJ+X+6RHvi6Jix5CNiuAjyIuOmS2WmlY0ekfDVyP\nghWSM7waf63elCIyFHdqwwbUOqohw2sejYJUOhBgD2kbo3j9Aciss85pNDhK5pCTHERNl5saGATW\nR1EW9/+p1xwv5j06wQmirADaE9CO3heZ9GnAMt0EcRAV8FCg3baIDPxdep1JV6edbbB61wwtWj7x\nNvFA1qAJERd48Dvb6CRtNYmOpEWsQi/Kvo1KB0bEgC3E5hjmLhHzozHaZMLUB/7QKlalMFFGTvJj\nnPTDTvFIkQBwcvMxXEfvtpkYhpFKBRmWH708IkIVsCu3FmtyyA6Y+GlIn2mBuV2w0Yft+u3EP/o4\nh48MuZKXYjtHZzTUBosn54IEJptYjay+f84Ec+U4ZDGcRUSi+/IYx2P7ftA1D2H2INI8UJtWZ4H7\nKoTzJ1a3mFRRu9xa5NTXuSGItxJoAV1cLNKOmX0dHKhnFQqENkw4GLXLzm437Jxg0USO4v9ps/ld\nTRO89kjkH3TVvU8iORGG4QWZNw63jcw7S169sAjOyRCeFTIIyjthWJEASPIKLsiIlOd+lNbCvLYx\niRuKr8G4FL5bCXdlcyv+mhEYBlG+V2Z4tFocXMjyhj8z4ntyu9wqRiGDmtmt5dyKmQVqymoup73T\nywpyuppy4lASZuFX3JI3+oa1/Ibpu/7+7YBp+x/HeVofWC7Xp6V8SPry7Y7QIe6ibTaD9Sblg+ao\nd3WIT7m8BNWvrV7MCzzEinc5A2oSg8H336vg8rjAJnA50MHNpU8hzFvvttsM7ETauKEyP1EiI81T\nqicm9qbqUUi003Teb1bNvy8u6yHNHW96/r3TBeW/7yIR9ILb1qN4QYYha+vRFLzRn7mW4xjvWYaK\nzAQTmum8e98U9wKswmHuvfTtMF9kgbyYx5kmvYOQ3fySRwe5f+9fvYVSGetwKbpljH5qLcQmo4uD\nz9ZgJljvkONTckNZxfo6f8QxnKnVp4x+im3kSpae/ySLOblIoobJVTlyf5XjVmXZjoFZvLo3XLBo\nl70tE635Kf65mKPgWEYeTjzPcZ/C4tjDi2fST6UfuW72clt+9BBagoiAtOuSPkf5CKaqdWawokXR\nNQlwbsUv7MXC2gdeE+Mab2UDJ8v35d+Yn2/HNENQvE6rEJbAKGQUk1BrTFTzpGc8BEa/BourCWl5\n3c88R9rKm/j+G5aaBn4cBF5fDBLTHjP5AcW/PmHqEh9OJJL4dHiDCfGPsObLCDayfjBR9jbFVMxn\nII+Pebd6ZCtSNPvHoiFggOlx8qk0ksbxUmVt6mX3G+e8xJIV8nTfqMichuo+2Yd6tMcBz1phSWdy\nxK4gJ6Tq31dWXYf4cyVI9DwIMDCnJVqgzhdhp0lXRM3MDzG1UGh99w+/qiFdmcsi//EiOWV7WyfI\nnMHFtki/Gcggk0zZWd0YkaMXz/PutSet0W9gNwgH24zasbJsPyzWgfjunVW944KY9ZPDLYUq96st\nCgNp2ewMxwCvkhhfRnmBriWmv0BDQXjm21YdcbXmCCOsI6cQElmLcIEXqNCQOYy0BXfx4ykvwo/d\nX9JLmWVVLFAHziwS9e4KTyfthNQvxTb2suTfCX4uVajNtrIweiClFNDgVPCOa/Agq8mUh0sd6iN/\nw6G/975WHg3U3JJWPNASLRYIOlMJ9iii5gi2jPWbu4/gsL+306cNYICgLe/V9dVwULgo58wivY3v\nPOVCNQIclFNvqYsKClWjUsSjg0i+jNJ0caBFdpyfxw6GkT/TT5RX82yD70P2t/rN3MZg1Q/ys97P\npO8aoiGxB09AX+t4BdEIpv1brqDNLYZwRNnvUfCd6glyns7i57kV8D2eOBBwm0HEoW0Ohe9wNe3y\nFHhuVMW7TX3WY7YVM9FrXWKmuDpcvG6xuMKTsIvhd6xgYxa8ELdMRKuVqiLS4TsT4g0b1KuXKJ8x\nQ9ysYSklX85zRTCsLR2xQqa63hseFgq4ljQtmK3WkE287Z7Psdq9YYicVm74cHO67cghZwDHcQom\nFMEMrv6qweyJUvQCvklzdvga5t3Rzqja+lZI34uaPo4xK3py470EIxDj5GBFMNDJCwbK9LrGCKd6\ngO8y/Up0ubxEU2a0Gf5Elm/ZHlR79ZQ44+MrjFxVNoTz1zexeSCem6bk0RGmG7xaWWj67TWyilE3\n/Z+33mQbXgU+md2f3PMPgz3z0uIQ3QIV87Ln9YdMh/CyA4DTcEzq/1hW1fAvZ064LXzYgbPkCT/A\nsiCluBbZJtWFIWNdh+M491FSc5gUKQCENleCYOo+vaIkbF9OayuOY9vu0Z8Prksr6ZxX6xnpF98R\n+PjstBPHqvQ6vMOls44qNc3p6xjtLY9n8BuXkVuff+fe6TsjthTuztvNWSuVAEw+N45oCxYDS5sM\n8u8IN6lQNKatlBRAZ0fGAcXqjf4wBoz5fMwLT+Fe20xRBf22/4zbUEXzjguVXxSxgb7MtT6pgElx\n96WpvQfMMBN/KwTKifv6+za4XKimorpdwoy2PZeBPS/YQSctE1x2FNR6pyYsSkc3lHMIwfZTza2S\nRkPbXBfoNEoGqsmLLOMXlVrx+kWe3EbR9zDKXtmZ6LPRPSyIJ2zW5BC9rb5uK8LBvNjz40u95ISe\nr2uLrGu6eojyhUr+zBR9zlmZLHW7QHEOgHQ5+mT9YS5sOcm8+d5proAIx+ucTzw6IZ2Al7I9wMlD\ni0B5wp0TBdO7bPIoKuNAqteR7clT59vGGUTkhg8rmDXbK/srNdW5Ndt5Q4lXlgrR0PkR1P4+wVk9\nB6F88amkRpaXNfKFfqr81gdDQLxvVgL97aCnZh9ZkWFVxhqeBWLXxdJL084N2mmgfOrd5xsuVA8Q\npJwq+zLitMDAggOIhgitq6JkiRx5NoXJMGZobPObDH6vbBi371ViRvJqUnpSnNw8WMMyF/2FH2Yh\ne98rUW6cInoWl8NWoUNtZsY2QHATd1nPY5QEKohNFnqmBNsxhKYS5pyIcxEd7EIyDsyPp/X/JhpR\nwVknRKb+eo7DiVet4dUjcuOiPrreB0CC2CQexQDQsW6ghw1fuhTdtKXQKfzw/i3AMeZUzIPa9lpc\n70zSXtrs1HW/bIIGp+2fy4zxHpXTH1suoaBcJmAGJheDfBzcAcwfBjM2NO+INTba4uq+4aB8V/An\nf7Z3IK/5nQRXK29PG30rCQ0kQFv0m4ae8jEDQUFqFsc+sttw6jSQ/lU9fsywCUW38bNn7nEMT8cA\nLt+n8m9R7ckK5nsoNyz+oOC4al1YuPSpKanKbpPJA2KbZ/A7KgcCZDE4xP8XvJWJWvYJyeVazcEC\nmnod+KC1EuUsRXQ5ZuuAzKsm1qmsoU0RY4jM6/M+s2Jf+EzpMc8vn7oy26+86kMj/4RU5wuqqWdD\nQKke6sj5yC0vTj0GGzr2xokgNocEvd6L19fGxa/EGghbF0emiTxbzfr13JzCWQTQyYdOwz7DEVOD\nD8bhoIsal//U1mZAcBJ7EyXpDlkvN+20p8HPJt6nU4BABFVrqo6uSotl4dH3+Wf4R//QPwbRwZbl\nHUnH9E+9T37kIvThTmg5XqGI/iD63BwL64ny+0hRhULtrtdiNPY5HEMGtsHzTyrVaAwb0rIGKL75\nGDzr/1hPh3ncg4xoe3mHtuarfFD9Jk1yfvBxsMe/F+XCbZmnMOn5Cm8GpgoTsTyKF882MZyy2hHs\nH2BeC1YnaNnUw94OcoDp0fQZUzD14lYEmZfpknZKCFuvCXCk6iSr5KRY68edKiXgja/t07xXCHo7\n7NGI+xU2VbIK08bkcZbC/JwV7O0fFIjOAoRI5AJ0bjhPrZlTdVlQ8tdjLBtq3xAXqFkc3HEq98RH\n1jrx/vXkRVGaVAy5gBNtM+DXfQ0KCrbKe6dFbJ6nenryAPgX4OPJUyljGzHM0tU922Er7hiPT8Qn\nh6F9eCalhhnbeFUv+HBNN8JdeO2r4aAz3xSe5l4+VA7MUoapqsN3jZ/nwuA/mer5cSs4GO/s4XNS\nR86yqMj6h4rVkt2Pz0hYz1xqQsvyTQocks1wQ73IU36/sDavqfo82rggMHKv2hg0Y41QV4xbySD8\nnpm6ht2eUZ7RXzE1+5GQ/4h/QPP5g5kuT8K2BBqQsxMaz33tbISZAU3pfsnNIqiegjjNOvW8SxKf\nP62gkQkUU84d7zFuIhDXbOuSCwc8fp3i4stWEVHcLkBbR4owYT6qN1PBjNOmyxHNsx7XEkl2hLNN\neiM8MT7UHTHhdbilzk3QlHot5tR7jzWCpbhJeuFmwdk9UVMJplZKd9TpmUIYYWq4+2//vQt0L4hA\nQK/yB28HF+J8gpkc0JB3uZCX70LtR9XAZfx6VdFLSr5lVG0figI7R8TEhUNosR44O5gE34JbKizI\naOXkcDjCj/wYx6uFPeqmdOgctuhvgYLxbBa5w6xRBshGIEOb0S8Uc6KEXlZ9KhvffdjBlle3yq/A\nVNkGVl3gjjPVZs3vbt4IpYqHhfaClG4BxqpzJqXIQFgIbUYdOPThGQvLYV3Gns3/THijKkKy4te+\nB4LHRoD/PrQ4xiZ+/1aaaaEa+1X9/DZLIQXvAyf7gXBAdphNTfnxDPVQvLtaHDiSlr0Tch5rjm/3\npQif4zwXuJ51rhnwxFuswm0YMI5dMCmjzJdH8E5Amc9mFPd9S8rjn8pAdj5hyKWpv5sDaRabhmFT\nQn2ORL8nHL1zAofrZcfPsCsx9L6qSskAqg6NCc1xhJ43TPvZVFSDIkvc7iYwO+3QIyFrS/HoWFeA\njMQxNHa4GQYi3A/3scVAGDjGRaNm/9w3C8WNZqTwu/dmwD4uD079tvKaqNEXwU6d50sQ1RULWXEC\n25MYoD6YKIC8u8jGKrtLygsahGz27WJOe4GGoDoR8HtmXcmKUnhGjH4aJ5UujiwwiR+cvd+ak4KT\ncYUAMByfx0np7H6DlVmo27c3XcslerniGS+2fm4TVbjgKK72qXfKBov5+slCv2rDZKM24qoWQymr\nyY+Xn22rVMZW7wkgUIak+9nrGZvjYFG7QTrLfzbN+9BrVfLgzQLRwIQTA14tzmwUVrR+A63SH+CS\nlXKx7TdGiBLx2B+JlfX4fdqHHZFPEQjU9RevYhwYBnOnh9CMff2+9pgpefw1hzH//ui2TgJBwvWq\nzCifVp1psK8X44zUPxT7VgHJrzwkT5Nl5Nmn8PAhrE5OME+stRPuAii54CW2fFV12XJkGWy1D/dt\nhm6UUiXxuAt9Ra4CkH+HnOyMcsRnXytJr4RRBY3vbkwc4Dg4GeG3cSVQiV+zDcdXpjm+Tx/dIbLH\nkTr+qJoHUoHJBkWHARCBtHmjXuhF4lxQQEn8fM4snXyoIzty589kkwR1gBp59RhJmRXlGMTahewC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lu4XBq0YKxIZkidY7K7qtZ40QWCJID5AlEyG49M1RVsHLfLHSlavnWfxYGuzt1cxkIVKmQ\nKUNIHIgzUzFQNXYzmIC4JiNg9AQz7sIMFkcF3ktHmhV9BPsQH3+ogA+RUs4uWogc5I2Edz6LfF/8\nMktB3SF9wYBh5NtUHSdMUloWXGJs95NBFIczD4xDieHIm50gwneeCiuN1Sm6FjY0e41KLIu1ePF3\nG3DOZsOz26i+A487AkKSSZz7uHiwfvOjYYwQDdtr//iFbHG7AkXl0SJF3EyWK5r2ahLK/BzgkJqL\nbG8vmsqJepmjcq5oyEFJlFFcFTz/azm5pcsfpYpdTVeohMChjezUDLZGLTIccinBxjP8rBrFso1H\nK4GCwnfXJjaUPs1OZwcZBe5t1ak8L65X9YGzAImbNFoLOXGM6VNOfW2U/R4sdawHSKfCra8y5Vdq\njWFvXRVG+uaOFEonwlKkLK7QBL9+1V0ntO2+/FZgldnHOGFCHJkC75mpK/nMx73CtZAYB4c6We3P\nkfMYpj3Oyi2THS+0JTlR7FqS9iKosT76OK9nVvmQNCFukkgUhtL/Qi39N3N9eoM71VxCX/Tvcq+h\nRHhJJ5rzZD24h/W6ipHyx19xY7Bg3M5YM2ZzoUkgsHd1WwqvRSUqpnDacWmoxlxr0w72SxXkWaET\nA0zszdMk052Qdh90RYANLRnSSVBpioooL/9JyK5g+PsLNxRaJzqG6S5NgrCVrN+wkEAzMrcOzos6\n/SGpzCHg+WjId1X9dE3M5OEyayKGQi4VYI4FWBg12tgoSh6SJt6fySxy/n3+EwOaxSmngowbg8t/\nOQ3BZXxSrdEVgp7oa86qg8QykWFSFzkwfswnemnjhPCaFJaEPQJfU3nnYCaM3f2W1xsfDnb2Q044\naBixnoEXe4lHsvpiAaJKYSXik4g6EmVx+ZR7HGDX/xq7j+MLMQgXUM4be2B667HvpkjXiLHa8Ju5\nYetSPjmsxTaHeBbeYWJgMXRcAO9qXfR2ck5pwq9zA5CBE8fqpPueOUpiPttmiD5oWa823c758dVT\nWgzr8hFYPe4Xs7P4qpQZp94SpBffifboWKKr8EC1Eh/hNqbPcF1CXo6N/3zffDW9r/J0bSZJ8EUN\nbENwXkL1R1qah7XXcutZlQRa1zk22GgUVs+wd1Ml3y7wZIBSwjbJI90gYB+zdo8s4WAnpDcgNMqC\nAtdmBfRd8Kl2IjH2fISVWarISyBtpGaXZPvs21c5p/Ac1NLROPGO1qAvPTXFnwAZRWY/pBubbuf3\nJn3waRqsNgWHqH8TNRsNROE53FEbq+JIa9739dNJb4mRGYAzNagfoOwwRWfhVJih8KpTjVzWkiik\nZnPGHcXO4Gx7tGVi5KrKW/tKruWeAvxEYJhMQyhf3RRWyaEzEt/fIT+xiODswA1Zrc+iF4VOMArp\nVF44ltdudsjmcVYLv4z4DELRju4xpS2ydF1Px8FNrtffu5t9kwX5BYzVbHcY7A4xG1FbQB0F0XuM\nOTaG3AqT1GIn7VjQXzcy1OqkhEW5zcLgtlUvtncNovijtdC7LIUx5wHmKqx+RW2r4RZUIneYf0WN\nqJhEmaNMX/Z2WLjGgJYOU+1+VrNSQv9dlQIEfkdYtzG+gd+GhhY7FtulnqpzNOuup8UCmlNdzWbv\nGSjVJFNcABudcFPTUFeHhzjkFSvUQu9iFhgO7PORHs6OyS++WBNkO4wOOj/4ofUOKrLG94W+H7r5\nlGVWBv5ZXR53bbbrhQ4Y7I9GR11+JHisAB3mwhamkwBHYOGyBu8Zcemhluf7w9GN7mxTd6OK0yef\nrV3yJ5U0qho3BxhtEmmNAQIKKslJiYBMsoOtPwwQWaM8eB39KykWNfHyJA9NfM3Rc5sbKAtC7sLM\ntdiNVoULatrfsE99UfA1WNXdm7PB3PTsC9j7MbWH0o1roWsGpmwzXIRCVreVttl1nj01WacXciSM\nKNpQsM+MzA5G8ZqdEge8KWPCcOsmpylAnts0U0La95CzYn/Sfa0QKSG9RuFgdacOSwZI6htYHE4h\nC3wZ2t4IFX2EW8OiPCGXut77ZvpJjt5KroZZmxpp4kbmW/bNObZPa89b4ftOdASxccl5pvW1p1N8\nJfw1DkEUe5TrUYRWn/1pE14AD/plPJg0jrzZfwzmli7ww2ATPu0ispP5WaYQAoBe/mpLa8YANLlJ\ni7ovrIGfYPnEHFzWqlXsdkgV/sfC4l6BlXi8t/tuQMctpuvgQglmEwGInqhNm19iLeWfbmhzFLjF\naRiDUeUih+RV/A9CLWUFLPhTNFbi7r+ssHaanN2zJkT0kJVjAvf9pnNZ0vlCqnu77d52UIGfaCB7\n6m7zTD3/L79LlOeKe9WzgHcqJ4AGoZzaxi0+ICdpFzC9yvFmXuixxAw3z3tkk+rvHTD7Ah4b9He8\n6TWaA0ZfSrFGuEP/upmI8aPB3u+B3BJ8bjogDYTT+eZA+FzJ9RZy6i/pMnsAGnNSAaXAFMOMK7WJ\n3cqi9EjQP/SAi1xG+qipstpMPptnXv9w/x40U53fT2UdcQHRmln13Dhzwu6RPF1+y+yjPlyuoIBt\ncWVMn/8nHQ2NdOKt5MEY9MHB7XfsEoWgRC8lmSMTpMKKBx/VpWhblhOEwK6PfwbYVPJJDNyckeE9\nhseJFe9FQLLF8ikRYRmY/pK0jbHQmoHC/wcp401OQ/FlDot8QtpsBcTHm896eZymOjRGwGzUSNYc\nt3df0iLn1D4JaYA+U7mYGXwnPvfVVEAiSNhWkCc6yGPG0NPAHuvXSX0ot7TsNd/Zmof17Z5p5XfB\nyq55wXjHLZfsKZnkkVIOgwvWqM0lJ8ZEdSSC0s4xomovc3BLYkIceLVhLVeYYUCvlRSDA0hqs50g\ng3OxoTjH7uS7zzE/N8/GbUF3S25RJG5ymavStg5mBvZkWG01j5L00buJK/RzpK9gXOvKs7o+50PU\nl4TFR4fLkb0/OgQmJMEXWbnLIkcRoyM4rCHuJ15aikBFV/mm27SmhIeNWtZy39yW06GPcKR0b4Sg\njUrvz15fuyrDBglHG26/03OZzvC4s0TFGOQbhlJyj+HwUBDJEuv46+VPKNPCuF1cfkbcZ3UMHdlr\nD1vzYb6WUjzeBo+UxhHE+7NPsh8NsM0el0cIydlxQMQT9vI7s8hrgOlvl9l3xpVfyWaCVRJlcUXW\nFc6PiANvDOAWUKxwcsmKKG2leZ4Ddqq29GmVKUBREGoLhMNgV4Mwjj2xm4D0cxO7sYFjs6yhCi4t\nh7E0UUIZ3X6KCYeEKzEFjxjzDbaRCfgdH0pyzLKZAyAbmEkac49Vo7k4dQrWrdTJWU3UsjHCQBrF\nJCLTqfweMPIA4h58hETb15f07ENqJkDLsX8lBRa7eFEGd6muvzXumeS7sNawg37By9KdGFtEZuN9\nYTsdTlkyQPWhozVWKFT1cPE5y/LBPCLajtKCuTt0RM55f3UBQMJthPIaf6FSe50HxT5KPEEAHn3X\nUyANB+yOS+6A4QlKhLTV7XBOVYGg8GU8FhyiLPizKJUMrpUKFibXfLNikXFWb0INOXWW2pRw3TLP\nTTIbpGvz93UdS1ABLnPfaIEbeqF1eS+mNA0Q0n/IlMNd1fzev8Ap86G2zlRA5Vjus/ix2wHkCm23\nfl/gG/Smx4QUtnB2Co097JKrg92A3lJoNv76aZ7qvNmlDbd7jZMalrdbGo+I//yyEKnlUOanV0dq\nRrhLo6Q47Aq4EBCihuNGpOqXcWcisDnFGNJZwn9wlpBegwzaDXZ9z+L1d5jZB8FTxAOrmATaI4j9\na5uykoDJr9AlRm60vmlLlykYXLlorkz5yb+eQrJMG+I0zqg2Np53TFZJlcrLYxBUA6oBJBmt7gdz\nKEut7UI4xsiwQne4DHtWkYDSUln9yFZeqOzE6uzfJi0D6dAgSBuFj1+Tx8gUOLNJxIq9v6UB1t3W\nNjMCc/1ISQAE1IUo3LSbweIaB6kEG1lUf8Zc0ABjKqE4UtxqC/scvuXyduFrritRXVYOgKbPhTi2\nxKx50pqiroVhmdJnQnY1DqlypfHbJxypAJOH348QEbhgDe9w0nNTufH5jNvjLLUtvNy0+abvPA1t\nbbzB6484B/cTTx7A8T7x/+An5NcJolHCC85cBAbVKYGqnrIcjGkYmxRHDkvFJeN902Emy4c7FxSD\nvMeIikrjb+jweGivkQGbfpnqZoU1wb2RgRQGdTaNWQi8rGRJJIVi9AtGgeTFQWD+7uC60DvE0fAU\nDjZhrNnn+MdmZyqxf84316r+rcjedHHrFKPtKrBZwaYprPEeUQ0R0aovx/i9BlTmWswe60OkbMRT\nl4A2scVK/2oz6l8US3cF2YT3OUhdQr+3vjJOrGu4u9BQ4HDB/O90Rm8R3Gy7DYg/AxC4O03+85Pb\n1KLKRjUzSS6eD76L+HGAOeDB/p1EKpXY2qS1gKI/CDMRkJlTI7F/UG4ssDpakSw4FiWHMRZuuujG\nPl+RHKASDPQjv+ZEWgtxzQzKdpXBF65uZ0dnsveqBkUvrm7oUOB9bDudlhNS5SIB11G1+HlTirD7\n6AX2VE+kXulYor0qw9HqVCAXny+Ir3oMZnwM9yA8CdmFhA5V9iMVypwMITdZPdoHIHfaPt/pM2pR\nY9q1UpTrUPVZoQWED7kj9oWd5TPk984Hwaa7/2GcfYn2FuL8qhhija0ZLMmkzM9lkEnXfoZSKri1\nOUG47Q0mWwuInn6sjwgi707LHfE9J7wS0G6VtHpav8y8Bd1Nk0Ihyj8gueA12zGx0ILf/AW18Ro6\n12Wc50gFAfXRz3eIJ7s2U2Ut/W2q7Wf3Ff+QelUOY32lG0kZztHAbEFHPoh49aZkObSc6JoGFxIB\nx2Rg/ORwqVT0XCtOVoM8+wyWYoTtweluA2GqLFfULAbbNdLsR+4pu+8rYhAMsK9WsuP8UvMlp9Dx\nTvFKdosUknuoU+QfBFHqsZ05M08ADON2sZ5W29UPM7gz8kZG1prs7dDQ490e3J/IBxW1GILMV2TQ\ngo0uJW1eMwTI+2bLwrPowswEUz2zzajgJxPrXYosHKX2S4fQRFJopKQfi7NHBPJLsX5xLRDRSsPu\n4zXvZg1FmaAaBYa+jXI71br9e+aOP7hzFW9Vl1BNC2UxaboaVSI78v+4dblyOpS3q6Gxis9rnEww\nxPJqsZgN6ZC7a088tjgddPEDqNblN7hF3c2KYGr4m0M1BZmcQtOlKhSIhubJJ+OQaOKk1PpY8fJN\nUHW7Vx3ANeR27tCoz41p2rk7BO0rK5kG5dpQm8uabskAnzYl62nyjMgZJQ8d27LQdlHov3B42tQD\n8nbmc5JcShATNzPwhkLvCYCTAk/ijmi2p1TwpsnuvWNIhM8gwOrWuSJcVnfRYCSmQOXZZYMgXDEB\n2EDx9vYc4iVNl7GWOs7DPLgL3j/dSJ+ZVeHCEfhjKXn9QUylkxVfjykq6zaDONITXWEG3W7UpI5f\nYEgLJS2Ts4WeXP3JAwrNs448mjqgJfqr1idNpf28WdxSqShtx0kRfixs7douX/2e6v8B/UWQIhV7\nUkmMg/rMYRgbc+1Wbju5bVqdmUeBW/EY9zEKzm9bZcJn8vqe2cyZAgNIoYuXijIb0QcExv1nNCU5\neooIOCnPyBsaZt+2x1zNvEp0EOw8NimfFGORuplYrwbY6Im1daUEmWf8VqdK2SJ3iHd75pWocjZj\nQNBMhalvj73F1vuDf/R3pgUeDNvJC42X4A0kTZjVt9Jwx3PW9rK+3UvbY2ITkWWjwk+I9qU6ms9n\n3dkp3CInQRDjuFsk/vRrB3ZNukV7QqtWupFT6OVJiCTRfDeVJUEEBG/77oAlGIk+6b+nfpHT3t0P\nbRqAOjXvTskV+dpKSMkQlKxiQobDWlppyhhfh9iVw6hd08owmOXDhYoaeleUOzfJ41YzoGyISLfk\nv+5/ndi/m6q9rclA16ycS5IZHlciZQkQFmgibctAAgkFuQhfweiKNKM0/LxEOFjWe7rYe2iGt7hd\nIVkU9o9ZqEEgdw5wC1Zpl4Tq9tnorJ35yajt0STkYSVixIw8Z/9hEz9oEvqTx3mTqgFW6E7LVIe4\n/TktEKa3EmWN3RiYultbVEsBjEjfgZMRJafSiitLrM5GQumAANpq/MNU5m9MJv783NgfOp+feOP6\nswXn6uXMoNhvQ2crlnG7jf/qV3Pu7OSuBsWMxsxpT3lsiuSljwJxt/LXLASpg8AQBcbNd+3p73qX\nDy5rMZXdzct7RZCy/sBQgrynWPgy96KBWuT7ayerZOaaoFLokOU/KLyzCcXMBPpyYdOoA4XWB+x+\nfqNsLx0Lidr9ozKAdaGBe077E/NlEeQj8rA5H0h1aNqEarCe34wgFHEFXDCAQitIidhj8wLRkvGB\nw5U4U47Am8DL+VNdhmhzvi8z/g4Y0d3uxd7NLUrafbCngdKRizlcX0FZB99yzCORiLkRx0ct0Sme\nMagYNOQAiAIOQ1w1ILiwz3FcCRzm+C/P+e3za+wbvqNNxiSgqAw9dwkxDtP5aGynFDn+MvyWdpX5\nbBhfSRSjOB6NlhcLeIvG/J8SLVkAoARIHiSVeSo0AdrnNDuHI4AmLZZ8hcIAkjHYJbCbh1VK0HAG\nNm3x4PBY5MHG1aLkENIysYJwXfQDGle89WtMYJdgdJEeyB20Ix9dtTB8VuQa/PzKLOlJ+uMJHXjl\nsB+jYMTVKeZIq69Zti9jkCOeCxCgAp4/bTWyHvNSizt+AKH3+4k6vaDZGWr1FdTL7vdicpJ4QKMF\n1EmRn7lf+Wt+jiVSCJhvZff8g96bTpxSd6aVAUbyotlYwPPoZsa6asAM+E0n+/dcepewj1qQTjBc\nOA9URZiczKi+VFkMyb2aYSDwV+pLSHqQQFggX2hR3+bpIXIZ0GAIF4SnNMbYCERPnibjpJqFeIhY\ngnFrJXnRUl+J6nT+Joi7Y9cbWD+Q0yFX/gZsZKu9o94n10GcrqBp5eWLO9ZXFjGzyRY2DCUJKcHE\nhfbVSE3kF2M3c7BV6Fwrc5bhXfkVXdSwkkv3oVMPjoHR6cp686LYcTAqlJmKLo7EXEyK50SNxyC2\nzEyvSoySvWUprAs9eYjHUpc3xhEGHxnfiiwxbyxr2xgDloVDSQFSoMQTwspBCikgyxmVC+QOA+zO\nQCenpP+WMOIwPsHIg9eF7tk/Eq4O5WVYRG6yiQw+tzIFqZwPjM83Y4ZBSDBQg+4SVGBLJUn2AmXE\n+xuAmiIKeR/mTYBLQPS4P7er1nQzbj71mWHFzSLAriZ1n7jEsbBqs6EUnofpdvTjdEifmIrOJMRp\nJXHNRfrRKOdUBEGxq2PJUm/vpVVWQDmY53a7qDtDYSeF9AbMGTzOKNNwckUjRUQIqIMcVoq0pWCn\nuV+Ylhp2Aw16+Ez4Pnlu6BYFwCM8PnpTPDIdMlbHcQHa1yFbtI6DP4zcox2k01hy6jtH2OZJ/ITH\nQwJhrIc2RCnkJzsgHpkXnurAW7tL6aGOmfp4NdfSGVxnpJC2wupE2jzviJPcz795gZn8iVJmxj2t\nl2W3DDBdWAIqX9xjD5E3EKCDluDJhioEhAjsVxmbzLg4ckXsA9tqlQH96qv0nN9gTXGUciPbesc6\nP+rgj4GYagFufJXZqwlJvj3/CZwxiUw/YPYwMQDJ5jhfXWFy9II0WE51mBBER7nbrh6o/MAnUzpc\nZ19kNlen97Agrtrh4L4AziTGQRhLmABEt7O+xq0H9qp+pWAqBfuIViU+Io1dUsj2yhUOr+Y0gUT0\nhwYUWBxWjicaVMPeb4nK2e8mOtSb9hHXaMvHRHVlCf6MiVE9OWFZpcdVAQ9L0TWy62EAGjo//fEj\nSUJpr9lofCgt9PDipn7Ac5zUrZsql8jmlCXQRGSqD3dN0q1LUti1b8+sIUS6eFwlmV3WmQPngqWg\nynbXbZKNm+o23EzMPFwrFrnde0cu+4yBJL6RSFNCgs6iH6ux7tUYFrFfkhd8ygChBk7sizADBJsb\nzaNt0y5mHal+wZSuej0guo1V6lTEeym6xgtzkw+1+2hGI4SQyhFcFj/6bjnvrGE0MXMuV0bOR4Fo\nuuL4ffCWRC5TQok6daL4iewOrAiIqdtuKoHodENc++AHHc0AwQpibvNGruLqb3xlPTXJ5ip/ncxg\nmZP+bA2NyhJpl2Ek3kOaJ5PyvrOPqon+vMIEDRdQyaEV5aZZrob4XM4lDvyNJcYrRAEgqZ6zwPcR\nAucL8TLUZkiAU9uUruSKLzKBPqS4jVBncCjh0js8ym7RLsjCNFJP0fhxR0UquV+TWeXnPeDaoJhI\nTI1S1SOcJZIwQY6QbyYi6423eFy1GAMQv5QqzoP7/JMv9vi3TxkciCBp/Mjk/RBsH2m/xLZ0fudx\nDXCv4eXveOzaoFy1+xudfHP9KFlrpN94ZQBGJnWB+Cyq2fZPLGs0vmbDPR9iZb4setIkGg+WB3hI\n03mNUZZdJnuw0iLG8fH3xDf3HitQ6yCpo4VNpkth5rA9lSUFku+Bt4m6nhH5H78M4yEhMtcf9CNF\noLO2JdAHuHv5qCQqnm9ozMPD/0E8CxxmfV6ndl9bzK1TCXEfTOg02JEjisWtuaZW1R3jKDewVLRN\nVJDUcFwfRCWLn6npL5mAEOn+LB0wTGRexikZRJjDILQ5GIYew7Ddr4D/vV0Rv0o0m/+kcKP5JJMf\nGdcRNNYWaSPF4ghLSmmSZdgNI0heuOPEBVBzMmmVtYiwGdbmrvkUdBuk0elyQ0VGd1hNwcPTbI+h\nq1L/YMitHOa/QK+mElKFGeL4c9VRq6oJu3LjMDgYbzVx+QByCVRS63HfcvQOy+nOU8n7/UYWTzIm\nLX1UKLHDbCYgt8DemfsXBXKv4Lx7EEdIdYBrlOR1X7JhaF2Q59QePfCvczdJ924aaOnBIlvX5eFO\nz8K8/5MEK0dMEwtRksyffLAUR+KUzzrkij5DHxZhp4hk2n4yZOXZX4MwOFGqVLNrL8HTlUNUTs6Z\n6zJ/pu8O19KBKYAvpu1ZMIn/zhkfJCAgvaRT+k2Rf3giEZ70JoSKjGsjaaXC/SmJAqfM0FAtXbNq\nlketDLqnunLuODL8M+kOGnHLIzNK5CuNL9R1fwt710CoNdPKlCNf9PCnS9XVn+zNam5hS0kCblse\nRWAjkiqMvCec2ZxvUaCV5eg6itH428NrilLTlguSQ/H1Dam1RmM3mQKZ3ExuxdeE/oqqxn/qgjs4\nrI8XGKEHtGSIUH5kJsLrWuZyGx8br0IowpXhCN7wyz+enJUSImODbSD1UhbJPZb9U7+jcWHNp2dU\ni5vXPNSjL/pr/nqoxokUhe3uGihPTWxeCQKWPZYSPfIgpNKQcvTe9wje0pYVT776kHzneIhr9TO+\nOoedYbTL8yrf3IBWpCuOQq6/i3wJzLhhZk1hutaPMLBupKfDYoNPxKFQykiPYqqlEk+XtY2MDGIr\nw0FANjMOAEE/TYOFi8FDzh3LXSdUKP+1IG8559tvECxAs8JTdxnh/QLM07mxKroybR8xttSGXE7O\nd2tTdYJ/78tB2i2MVfRhAq6VEdBkWXnZhh3dFLUq7YB3Qvq2Ryhxm3hXTDCYX690foxsyev8hP0L\nYsqBkXwEKcjGk9VuLQ9I3+jFowW8zPMlkvGM1PMi9e+WxPsv3aLEWwwy7lFqG6i7IOrtq+1RIO6Q\nhFnkakHfblEVaYRHRfMy7J1Tlbj9n6osDkU0xpqm1MU4ZaZA852DP9dZGDDzEZJR1ikIvHnK/dxv\nx+nN5VWffSSjeb4YEqjNj5h+6pqC6QptxmoXSA1oWyvQGIyh+1Egj5uPQtg1uEOxA6mQfP7SjoVC\n8iQyWZAOB8AeoAE1/pmW/jkWqPFyfBbm0tAYpGgj9J+5dPo8/eq7UNuv/9PJQ/vxCebs+mKBtSsS\ncZkq6cSR+paD6Pcecqvd7KJMJTtokgyu+MwWjxVo4MWIbwvRp4ZA1o0QHv+QK+satXmLcw9Wnw88\nPkbejuGaJy2yyidpHl3mHtfTL2XgfouOX/2afoPAp+l5ya/4vlhQhUa8qP6NY40zfeDW1jtRlkET\nMtiLOE2azZPf43C4pUFppHNAXrVI9sylmkV90/3gsYAlCsSwBdIyDezJFpl7ELxUQ0Y7qhFUoi22\n8XWIJtMypCfZmstmZlFGwJVF2n0+YwpihXDCprIbeKfcMMdMqe1oPPADpowSnoj0oiHtdsJLka/L\nVs+FJ2nQQJZLWRFzEpeuaEpZwWdhJ98bJyzOSDt3+g4P4+mpG2AAB55XCLFE8K/t0A9KnVSPJSAk\ng+4vrVjt9ILQoiZxFBgv0+oLl+V2yNwGLRUcdkyeFUF/MlDekKx4Nd9hsonkfJcHeMXg5jH8BeM7\nFCmQD0+qaGigWADfgCYwaFWwOV0thfXp7mTTRpI7D6dXUjZBMi+hREZPGYe5TdaGDehohdQXnbEM\n7gsm0T2WlzeaSLqC919c5nnwvqhSJ9hO2yt/5Co+YokC5en5JulHL3sMJGwN8138Och+GLx1S463\n6W+6b9cAv+5KfA8Rqvvz4jW/at25HOfw+3DY9BBNvT8JYdBp3JpH2CWkIGYqVpSpY6ULQE9hKqJA\nRcM3WJmshroIk/QYEo0lg9AyEeXkk0H3J7iV+9SGkoJ7NRRlFpPBX74kPTlvpI9WwoKx652S3T7j\ntTEXENHezTIkBQYqJNfyqLfJNEQOMCyfr48Sc7WbStZaror5dSNnwujjwjZGRUGlWRsABJiWKAPE\n3WIpk9BniMMhmSvFnjOdrIFwj4KAYqH8fN7vg0LpuFki1wYdiSidyL1CaUbkqNMskYD4ShWF7ILy\n1RvwJp9GPGJqLuFgYSAvIX8x/l2I20O0/oM+Ynf4FJqCW82uQqPNiL9l2lDkccyro0tcs0HpeX68\nNMX+z4hCfpBp1fyziWMyR3a4YN2BfoPEa5jDQXt72saLSyalFzA/lMNdgOlKjwGhuwdt5XuU5MEL\neN5yKbUP8OZDpuZ5NvHROzZVtWx2HlU2k6lsNeZw0YN3IrQSfsaMk7nOs4nv3qd2JX4afyVycESt\n0klW3DIlSlPwR24iVyehKj3q/dsFJ9CYM57RTTZFmxby9hCcLzr/D3MJoteSVUmd/rDYnQYhGW70\n+FS6yboGktvlvNy3sqUpjoL7lgIdOKVtfBxDkJnFKqrLFO5w+TM91R84AfJSDfz2168J8/kCuZFI\nna9xY17Zecnt1SfpxmBPuB2QBS67ZjWLTTyIRkcME9TlIl5g5uuQH4U1oJIB0I963255bZhLv87H\nGG4oO9Pn1/TMSlU47oZI1RH28xogFkTLf8T8739OiSdnBNyVfCCbuvqoCBeG4z7VhCij+dh4xrEA\nzeHBfpdz6bUFqizN/Ug5ARm6obZ7sAh1BU3X5hdq6HbBuwJUGVtSAA59Xrivl6byY/x5SMeXxQVU\n7CnhcR2YCE970V89yn7GzxWa8krSniiPgnh7fdv+8PIw338/XQhJGPakJ+5JP6cTy4689BQNqtUq\nSwKsLpkDbRq2pJKLQa9XwnJLcWoBGG8oYn7GIplju/Z38WeNkWR80vVU42iBPXUu1Ttr7WezS1A9\nhEwv5QCll5fRrL+lBUxJDTTxjfKeGSAdviLuuB+lCvQwJJvyCiEFsQxO9h7Yh15vQOlbTD/shUYU\nQ6w+L7j6veCFho9NAETtr1SRdLleWyg003FNEr/GTK3XlEFbnauJ1eQshC4dkqI7PWLja1LaSP52\nwCAwwV0g2o34KTosxxADk/iyX02gIvP6kNtfkeLbbacbYuSGQ3t4D3Oirwuol1+bosZ1PtsMLio6\ng8q+YYGgu4JeNvPQmipBEPQpuIod0mNDlPLuiMWFDm0Fl//SXcyAVA+HWBBu/BzrLPd9q/NNm1Ff\nrnJM7mRzAnOwgZ/Kzjo1fJndYV9FmAG3S/lWAZkPk/YHrtoQwn3fGjV91Dex4FiR5tkBvaPeBIuz\nKnrnBo/PjPruhqMelm7Sv0W2SpPaCJUwiqjs5Qs7cOLlHQRvrY4biTjdVj8w2W+PMCIiQ0tKvlOW\nIJ6Xm+/6ngfwchbGy/rvYGpRtz+7pvNt9iCjAuF8vaRbB+wFW+JttQmSgFnUSkNX7fNPIv21EwnD\ncMqSRYJdU+hyegZW9QV+pkScIgxqfKWuba1TcHCgYEwupupfyW0VL+BTtF8mQPNbdHRVWk+w4Um8\nz6cCbv9JxpxLAImeWqpLPGxMCqT1NNOkAQcYG+5rBXjD98qsiKe9Rlzj2zPOpRcRYLAww7yKQOfJ\ntdhMOpCtcMdLxxfqja3KK4Gw3IutAPql4rqVIH45g2paABGYel4WFb5FnoI3vUYSnD48J41bR0XA\nX/PEeTE+JwCS8QEpxH9Rl/ZTlMEPaxcTzp8Ji6XHgdZwTU062sBHS5dgGcD/No4x4x16IR8q6NP4\nxSJfGXv2H0/nP9Eq5nMD1pABbAn80wYb7vQhik/F1ildjb8pUnGw9DXcK8uqMIulFpJkQ6jcGfjd\nxJhwlPyKp+VFZqN0UxZVlG4qvlmSszoX79Sg0z3qiYqRXJiktky9/Fnuj/44AinYhqSjMOEvYcNQ\nShvTDatiM2g0QomOv6DU23uAajr1lBzRGvHtgcen98urbPMkhTegRIOBRAAI9ir0iNpn0dyRS6d5\nBRbwUzO5utKBll+TJFC7JCIXsNjsvi3grBanFIxkBLdY4aHsKlDQm4McLJnvgbbMn5Xyz6wJ+nt8\nkr9CPzr6GIaACfnN/30wkNT0gIhutNTV+dvk8E7Hfzkw8um2YtULw84sE8uJMYBliuFaxDaVh7L/\nveIunq0pRSZstBY9Ib/BMpFhCJnsb9KiAvBwglL2+oPKbkVY7Y0MaeLbMt07KbFwjUMpzNPJECKP\nxoF0RvJEUSqBzfI2dnSSPdfTGe1gd+/A6tySoLbd9Riolc7yEIIOK6qfHj/XWVLJAtBXuAOGIChM\nCPdpIptD1tzsIc92ZXOfHo69RZPA26zyp12I0jgGmwImuJyoILZFqUY9Iq7mcb5F+55OBWG0zSGS\nYG2+LcxAA+Tkubww/2emkbfgMLvBGuFaGoPog1CAn2dNWF67+CM5Wi64tHpv+Z35PSsnKZw+0Kf+\n9DTFFtj86O9RX4FZCwvDpMBboqnBkeDQ5swb35pQ8pE17cCxP7OBZiN7oVL+Q3OnsR4UCGelwon4\nPRk/+h0q2T/pL/rkmVPILR0TZsb8lLRKs0VbyOtqMejJWB35a/EqG42duQymrd29dFS10V9fIQtD\nP9906IyKtf2sKnzhXHCsjzwfJ7sDw735RgBtdzyg+oaY45DeclC0+jyGOFNtXx3Riup6Ur7BrGtD\nF1e+2nSBaq0DxNz7RzIk15aeoQ0Vezi7mzn9zz42Gva6BQLbedxVMDl5uFhqTgsiThhhoLPaqyIr\nTfgkQDaiNPBnWP/lWl4Ji6CNI0qPZYjzjX4bqLw4LWlAEa/9SUd6U14+fFElodyQKIrU2o7i7f1D\n+CTKiBFo48g62+eMXs1P/E2tZJyf5bgkpLIJqL4Ql7Tn6bNzGylgYDo0ro2iY0x+X2HQCbDd4Ssd\ncXK74J4P9H0tBY4TgKaZxbaXih1xVs92QyaGQDxqMTajUqCBGvYgq2dX3FuhMxpqnwRqQcE3wvu5\nxP7a0bwfpGULQ2OBB5e0sZVcVCpDJRiymKf1joJUqFc+oKHo/QpBOiSPMWFkwKXR+ErUVuEX+heW\nxs46gECKHHsjoA83aSWGLRv1N43JlB2+QTrN9QZcPDEGvYs5SRQThaI9zes9QV8XOSLMARcCdunD\n4JkkbpmKKpJpLGdJvVrv6lAIDpEmkDM39bdIaq1C2eKame8WO8Ca2if/303GiyUosS+g6sWb3Nrd\nBvU95Qu4+jiOQokv4FbIUpJv1XIm9RsKYAs/0UM1M7wdo2Y97fdjHQN2EFmro0rykwz1kXGDXsz5\nDQ+q1fewUbPW8OuKJu4GF++axs+LMODNs7J66tB/a58+LyBRkuL+kRXHt1WtYzDc8K62mZnTS9ua\nrrYsraqa85WUQxpbm1qeUaJfDD2cGrrBO3XLScBmS2pPUTowJd526nGnBFI0vcPurbVO0mb+Lz1e\nC/19hwQn4kqjG6PNJ2/6j++q8FvnzQHQeACvSNVbRuOdB762JNQz0nfx9LPcpdJ4a+ymJitcvOtG\nGQiCWRUagAMWXzxsXvZ7GSCm5CvFYbVzcPGlFcnRnGDIT/Mat0nANpgoKKMzlM/3cKJJiRa0DhVW\nQijukAHfgrIevCwMFXklwMYpfJz8u1867OdNNAtdudYFMw8qOk6Z66EUb0p2numtCZV1pBqlQcNr\nM2ZeIZDxJRYhzjYvQFQXBliQGeOG7TgrvgYzxZvYy6u+qb8jts2pPXG78slY5s5D4W+xNstFqSc4\n62b8bFZl9qQQv4jcCcwz/FYHheanCZdUpzGlNAvZ4y4qIe9D3sy/cL8ShgvSHlsx44KKzSXo4vvQ\ng87gasH8SBnXfUx3cxgYnCJzWg6+sv02yXBQ901d823PZt+Zu47dhO5wHkInt5j+R/nmIZn35Psc\nduXRuDMd/7pBUViVdnfvIsyOMzBypIYT+1hI1BKsvSuIRNnD8mfaC9MXshM3zUfpoz2jK4gQWYaA\n10CF+ldXxU3mFNsBJvo/HomxWYUUQDK8TvBMlPZopMQ8QbEBlMix5y7NiKJBKNDbBCeKEtzuUNQJ\nWBCKL/h38pDno3fWwlf+7rbc4vZrengU6T+0cnEEBP6LBt4EN1sAQUUKySEMu+Bpx1ShZAnuV13c\n4sFrn4/t8um4G2DGcW5XZ5RRdXGedHZC9QgmDRxmTzJTx8V+X0peWhwP9UsJV/mEWpzkQUTAqLnS\nXpLyNPvNXjquDedk5LBzdBQ18RkfKkTa8RgBy0BnUxQdw/DyTev37WhOnaiAY6Z96zzzXmJOStgO\n6+4wqPAzlqvoKVRehB02LeFS7OrM8a9VJcX0NuSzhHS2pYNhbr6WNJjZCrQruNKgSqMHNPfbUIhg\nFD4R9KkYXRUVp3yB4zF59c5oxHtBbzx8E9qbbx5ThcXv9BGQAzece+CIscBaaHD87lsCg9FaMNZm\nt4xgZr288ifqQXs968rIEJeuraDU047hWUi+f/sU66KcqkE5wOuOWHiuXwq5SoIVHhExi4DxynU4\nahcDxNV3K3HzGlr7wvXbvvEwRzVi4+AKHRShI4rGusJDcCFtEwnhloCkvnr3NwvW1A1MgNYmO7Cf\n3c4NpMCZdvRiXMM4oUycR9qLcz9GUchYO3NVXx4RIp8yZKOpW/Ol8ZM5zEokQNK4JnweOmBVOFM3\n+2w+GHmBCMLyPyqcDaBc/HlWTHUEQDGJxzt4n0KsUaMCgesuN5t6xvj0L2EpyvRGdANmqgwGmqLa\nCc8fS/sxcqgxtIInIl38HZRACxYcavsWrpImIMAlkx1VMaVa4VPaiXM/KMrXWO9C3nZTCg8xN87v\n1Jh1Ealbk5T8MveL1e0EGvWCp5JS3PD4fGalgC4+HHW4wFeHRAKgM7cqj5gDxCDzue22EJK1Ds7k\nGBXcyP54IoxzwElTL6SU1TpcoXrfikrzLeuw5QsHb7khZQTGLypdSO3f4jKQXfw0RRVigTLqCfap\nAj294bB7eIR3/zEwPOi+5S4aQSvmO5pPRqT7lKc7Khv0sY6Td7I+sH8arHOTQNR5YqOPdc5x8C+4\nTrUZVzeEbnf9Rv12qCEHVL2UAlphxaKDtPcSLsq90DqhetmG/4Q1GseizOM67HFGHmVODtnQcl6H\nZpCa503v5AU1AL2wmF7vwIDbmReIKFA5GwyhWyT/6zB7Kjd1/2wq0FMnDBgxt+wuIc+N8ay0T9wS\nm3xspDc/RXBJT2WNv5Uk4YbDs08AP7cmCtOld2zzLwHJ7MQZCr1iHnldVOceLlGMvn53CRDn1ORB\nzoK0sfYLb1YGRyaxTUOvcxuemIUkDNdCD56+0MolpsVdFbrEWVlR4ioK2QEM8YBDNg1A56+SYGuG\nEWWor2uozVbdYbebKkKYTFiaAYVn4QJfQP7Zs0N+3NlBnSC+RBX61PsIzp2zJk8xUTDeeh5JePYi\nsPwbVofowKcsnVWbXs1MlTho9A/C0+Yzke7lBM+BgKmqrd+VFUxy24ZQa2ObUdvqYb4qAY7aW8hC\n/SkmVD+sYgSY9Xd5zKIuYKxphokuC2ScjC1Hc0Njxdt1rFxp4jSH/nDzbzrdMF2AhIx1+8t33kka\niPBTOFnI37mXrwLd6+irQHw5W2Sb0PkTBP4tLjYwrTPMjhUEON8FFkjfMDlUiNFGTAP2rs7EiKfp\nO3tO7CX98zu6EPckrjI2dR3yoP+XP+jOMXW5nNrOJhuBUDSyqgEoH1ze1OrfF5kqbk5t6V/kJjCq\nedLjbzJeQzW5o0jj8gA9ykT7ZHF0bcuuarycZdo8byADR+MR/4zzjEZu/+h3c0gGdVpcVJqHLmA+\nX4gpk0744y92AyR3Sia+PBsbsULxltiWrhhXsims8CFfMpdlm8/NRWcI9soRVfec429PEMwKOo0x\nPHYe7dWIXv6dJu/H/3Ky24C7/8+rvcOWBRAyGrX4jmhsYfgTjHW5QW12QtxGeG0tnwLnXSCj/lgy\nCy8Ey1AmizMOloQzTEwtQCYejz2MhJnW0dtyslLX/XO9zFarUBFfh/9hZbEvHmMeo5wuINs8XlU3\nyXBprGpp8RBHt6Vaz+lObCfPq39Xwo6LQtWFZnIwCBStEf0mSIMDW650J8M5x4ruyj8BKmslFeRx\nD7RXz3SI4Uzvqsc6g18xZ5brYoOCMBHNg8tqaE3sh+h9p8nBY/BXJRsemCkJzUK7cjuwHmIsfiz5\nSgHhaFkn74UrH/JJeTTmhTAa5KcjM2+9gUFdXB+owTWRZgFwCLuh4ea21xX6fb/V4OK3IPSCvWPE\nTYOrZEiU90x+ETXbyptAPtDVH1ehBiTZMkrL0U0FpE3B2KTiLwFGY6PgisVOfPLPSKd8KtMpaN4J\nuSVKfVxK+N9QS+/64u5wKQXCjZAWipRdZ+YubjeFg5uCnrO3tvPr0RIDv1+IUTW8ZNWYu4jigO95\n+HcIFTVzSHoIQLlAsgRWt+rSOFHZNrUPO3D1e9n7fx0rHBdnXHzO97hvZG7t6b6Df1NdhFKGRFSm\nTK8eaJWFzHddxrOMXOgBA2KvZ1uiBZ8Etylm3pfNTwFZyAqX7+B+pAZDtu57qF+PLSMxnlfPoy9S\nw7Q+VJFe3w82MXgygs6QxXA5lhh5l7fDyy+7y1YYBo0z+jK/X5RO4bLrCzMUZFaoVyvvSy3KsXAK\nyrQlQ7mDvvXkX2X7J+2D3aq5kat6Z5I3tWKVyTwsKMx26ESA6/Mce60xqSoNEpCm+VRIZ/vZJs/4\n8Tyz2JE9Kiqo1vF57kSVwHie2FnfyzyA/Ee7NXIaVoKL/jYeSrc78AB0oJ+VgVEsWDRad8VrNC9H\n+NgkQWSKAlpJX4n8NUrtmoyZPcGAM3+F3Hw47Pa6fmsPBOiNSGAuQIkfXWdwMkXxkhiHYBNHIDKI\nuXShGfSnKfxpgQSoY/DfKhDazeI0lnhN6QLCPkmMVj4+7xRSRrwD6jao+6yif82Z7KlT+eiOwocE\nekPclVnUbJUIqiZyjKGM8S9kKcRSlajnnc5XUWCedmssiodAvMTiPf/HN5bHAKg50Iqh1+js+gF6\n0mbyGayd/l2mLWCCFMr+IDK4qkolDg17q9vt0gvF4DBMgcWpPlFoqWluXXWu8uHoFGG310TlT+3v\nvq3Bx51v5vmAX0Bg81Irl93iYpyUArM7ujxSwpCBr82whk1/wZrBdAy4pGRH2XZBLYxIVGIKBBb7\nDPvv5tDe8jkQSih8svdb3aURXhHIsTHL4He0FJoMiGLo1czySOa1ZZRHm8ZuperE9cEkL1rish8l\nZS+6zCCw2oN/YyJqdlYfVsBLuAPsnPrkHy/8VScJdenquasq4u03lJEYmLfNpyGMAHuNJPr6cVxc\n8Dtf6BrG4asJ3EAGGfknmvV1CctAIs2JcphnRo8uRQuNuv0YuiGxe34G2BfuZZseJOonSux1r8vS\nv0CZCB5VNwrM62B404EFnsQWx68mPEw3rFvgkT985qNvnIqTDuCSOKsCSPBFd63tdnO5xFneA1O8\n//j/yxnxFvarT+izRdfqLXwO9Lh0pdM9cp7CLNjznaD0Zfi3MN87/0p+fYgXqRlJbDKbH4LBNva4\n6TmAhhtPs9c/3FfPuqDdTYkdqWlwiROD+t1pQmXyh5hgdFybtDZ/wso2lmvCxC2tOwhAZFM3Ypbw\nHYRBxqp0a767tYEKyIhbUUVceuAucc81GoUPO8zJ/J5hpQ4ATdWXP7e53d+xzvvzAR0dSFPX8fzc\noNoQ6EL9OasnfuHx+mxN0uIyhp5qgTJRAQEmxCdsecHVaJM6HG7OmQZEYTNqiMu5t7jn1o5za3dM\nvRdMDrj/sXbvI2w5FKgSVQWvZ+3JQIYN5nHeBZozNn7csNEV3rle3v5nKidwr79cPxF7CchyKsbi\nKk14Y43DgroyR2OViSQID6cgNMpVlXJhDZqoc3oKVdclt53XkabU38IPcx6pmOP0+AmbA7bTEGyB\np62oVUCarlRBk6rGWiiOU9k6Rl1ePR5gVtvqBeZFPiI4tEqG4xykLzaVNZbYuQ6jVQaWuI1mF+ET\nf0qoJd4jKFxQ7ofUxZI3ZrY0GEub09St1UEYZ9dP61SJr6jByNG1fqcYUvrbJuOGKyyd1nu+m8J0\nHE6yTD3gwSbRO7rNGmtKBkf74XPpkec90p9BBppcpFQ0Wq1egKvwiK4ig/OgJAsKqzyFZj4Wjku3\nHel9l0ZmFLm/cYb8UuuRB1Dgaq2XXRsjT2O2X6XKlq+GyD5kW3WtYl8/9fqHfudFPny4WmRDYDqY\nlSW4tuYvNzETBH3ZHI6zbvPG9MwkFYO8qvHn3qVW328apdSW+DYQT9+bVUAYYNEVeGMZiA6q0RFo\nzXlsph7IgJ/1IqYFGKsVtgh0DM29dtAjJvHs012sGAHciYE42K5S69y1v+ByneTqw/LHBeq6NJ3U\n9dpv/9lj4HtF8Ipay1aeETf+G7lFsXCALGQdP/TQ84nq2re24mVh3vswgz8EK+wDlkqCuh3EBtEx\nknmEhOjGGW/rklpCoLu7qcSlIZz1etSkXLo8x5o4wLR0Xal2Qij9Cpt5BkcCjDZAOnSjq5/c7km2\nQ7n7JNFk7pzNGbPDCU2HMzniZiA7u9eMGNGuZQy3g+Ypv2qT+hf8U3MqXXAed+OWHaMGzPyMpyLW\ndyfpbMv9Gx4eANcvtwVm5SaDsxiexlB/yGG9ZH9bzTi0qiPkZ1XyMbFAAGpLeJFcd2mACnidEEGo\nSpxGs76F5uLZM0ghD73yTBSEewvqAICkD4eN3NgRxVbyXzqcZU4cR8skcjgeuUCZXzHodXclW1a1\nedRnzzy5dHBJV4bEOfHMqeKpH59zbe7xPy9KARd+MsRfEWGaNfa8o+eYHZgGOHjCtN7icnRxDF2t\n7fdyQJysWhZz4MA0DGdDNNVyTFDK2JxSBrQO2VqXWsfgCrqeZ1k3Cu5hzy+LIT6hMYpQ0JJSCVBX\nsS4GDbsuAmd59WYh5SRks8r8lnRS0tlsvPQQmev6XhMBfXXslmB2NNtsp12XPeZ2K6kch3MzMfW9\n9srknmwyp8S6EcfHq4n8fw1vGIBKlQHF66utqfiFjEWASjjrdBl23pAK6UqxkIdUj2lvqU8FX1nb\nKppCnc4chs9cQxJ371lLP4J095Zca5d0Y16nsblqxTjfUcJ/VhNPtoVOcaekaNPFdecJsEDR4rEQ\nqE2UThQDMVuyQ+lAjerd6+Hr6PDY/DnOFecU+MEUWEHuZqw6xLe54AhgFbnnFu/GWefxZIgWTSiB\nAFGCRthfWni+4ycQF68p7frv3V3VzMC9gKLB5YrHAhFPO2hgNvpIKsc/kVHwxqT+Frg7UX/s90+R\nMl4SSQoI/DXsTsq7qb1YtmM1Ztb07rh5VfLusux5xpznF3WVb+RhN4/+Hq3rh6gjC9qtQOGP/YLg\nJmrcNh+3Wo5gpJkhJFSIUEJQAY3wEBnsLLYy7WXklNlbSSe/zoSksHG7ZHRSgaZjDbNRhnTJ64cz\nIyPfE6DCfzDHckPp5hNer25VGoS7jq4z4nzPk+JBZ2QzwBwjhWH4EsqfSWGbOL6/k3XQjI9B0ru2\nPJ7crkvmxjrGlm1QX9iSdgIjsu/sOjzS7M6XXAeDSX7O9womP5poCjItaX3dvzLd20aBjj9+Zc45\nUkNpte/Bw5n+O8qkNT3XRaz2lUBIbFTIFTbLqODWEv5leaaCJ0ROKWy7sa4kFi7J65+PNCbVhhtr\nE3XG4hirbACbFlafDhkfCAToCMWgyBG4uxKL4NYukw6t/Srmb4OVYLCNJJ33mcBTa9akf8mMGeYm\nvvCl9h6+EoTvK/jZOG+nrClag00ZtXOSdmSTVa6fG1vrbO895nq+B4shS0BBsgwX5ivUYQhIr7UC\n35UQpvm4lWZfwRuoelOp9Qxwyk5gxh27MOj5UkvnAlQZQ8Zfy6TCCxSlHfa6o8+2HVCHhoY8yKWE\nkCQ0PTOIyZVKZ8KwsGr4c/+HpTXEoq1U+CGYMZlHN/nWicMeQBED0oVhh0+Tmhoq455FfQTl5Flp\nk5OvB+g1qzebOB6lkeNBEQC2MgWJgB0Yj3kkwm2bqcnA8uGELAHkN9SQlg9Y8qbyilaC8g6Tevnp\nTlF8C1lxL5enxgLyhgpVf+95oNd9H6M4LGzrySRODl1YyBqfMERLm4xBoFknOyZqCyHvZ5tOnhLO\nPHQ1qbalxm89OaKDnVR960xYlvj4cCMJyDX4qAQN3NDMSW5057sDdhbrAgPQKhFvA88ITjYOaX8Q\nmgPNaIy+01and49iMCEvtLqz6a2T0krKLzlpya7cbvosr6bLd/YbH58P3zTlJa4Ktmor43Y4MFLt\nECmeuVJjeAwqrPXQ7/9l7C9tQ/bNTFtOVb6j7qqVejPxHyLBpAfMB2JGiuHMfyjlOAQFCoPLWYX8\n8q7mamNlKjy54Lb8bEIzprMNQfKXWKb7wk0kljOOOUIAXdngfYch5gam1V9rxhyJpcU3F4t7ywDU\n+8IPVEjUuhYXEUht/IiuLU+JFNSkz5AXptKrwRKnd/WxT8XpcfogIRgAYIEcW+v3ccejVReT+FAt\nIPAtlJcSZUP7Wph+D/ReiZmXWueh+E25RcReE5B7hma2pAW20eVL+FlPGvI32zlUodo7gnO9MMot\neqtKw8O6uACGJEpyf0xHjsdUB0zMLk4WNZN7Yt3chV2jUZYxxZHSAKP3U5S7u5u77kpCUD2z+SXI\n4wIh6vRlvAXaGTCHAjDA6N2fKVUyrO3JuLd3Gln5HSNUlF85X9H+WUIDc38DIOau9EbEKpcLAQeE\nnukJpkjGknfdhZLoEtC0TZ4hsSt6q8Mk49tEd5NY5AObtSNLHgyCDoRLH3JG1yv6tFmMvlir6cbi\nXPFoj5DSVL+4geiLkpeovSo5/MLq3lxMPZZm1kE7DM3SxaLLjT2oyciDaZQkFDHTeJBK/hAFr3s0\nTFYTQtTwXu/L8zZbm5jnObcBwtcZg5ZmbiNCfj/s9NejFScUQjR8/8M96pi8gBI1CAPqiCvBOuME\nP6W97ZSYMJ1sA5omTQZfHP+kDsOF7cGXVi/aNjza9xlmYEf/3WCXOPtj7G8ZvFGonlTvt47cxZNV\nrTQjWEnQqjC1yFOIRcGEpvbUs/9rO0/mpmKSA4c/KDgtSUT8mEzjc1tjJSQTGLGUaBPKs6mc+0bQ\nAm1vqWby16SY971I303KW3kCSp+hG7fQJ5zzrkKmPrEU6tQcnKeVgsYnQgUdV6SaL+Z9Zj5r46TG\ndlk3fvhf6ZDSun4r6hkxORbCdIzRWP4FSvDvXWR+BlV6b5ACKMTbG7nk8gLuyraTmMzE0QQUVvb5\n8+xS6FM9c/2d0OaGsW95TQWTmEMDmu9SXcSVguCBHAq6FQ+K4ZQ28m/9J7KWqIFlbECO6Zh8c8SN\nO93IRokvZvrh59bZcNDAzia9tBI1YVyT+pgJ890dnUDePSANaTdENXhERZlAfjdClccRJkANuYK3\nlF1WNQlTSpNu6CRo2/Lr0UQ0x2a6z3KrFdgAQC3DHaIEaECLfnlpqFi2KylBqI2rlTUgaoFP3KUw\nZIwcbjvchMNsxaxNZfLCYN8wqsm2BzOAKzC6C2z4wjOhItfGG6B4y6gjR1noZ4tBk+oGTzV5dcvu\nnDRcJ6vgxjmfk3pu2aW7pXXziasMHyc6peAOppTMgrwx0StxTqmcPAuUn476bhAeL0NmiO1CT8PE\nbLQrB1cRQ9b3fvAmYu+yntwAV4sM+0eA84I78uPv7p2s46qSX38LeweBZNWQR5818YUCfk6UQdvV\nwEoj9/3lpeSajHg13r7KARNK68POXVjbrcigCdXR0Sh86w09A7cyLNxaQiShmDhOd7XR6xbR+WzX\n9EDdVU0dfLGfkD/zW9pxnGlF+e064rvKwPPcHNH/GXdICaqO2MBDplc0PLLGLQxlamyZKJJbaDmh\nt/rywkTOzCda4qDCOIFf21RmqY5W1rabYKmxAoTlJLimyg02TVjP/tlh/NsxA0rnpFkjryJIhv+h\nANGiaTYXlzy5ZnwaE1dnPfumlUxaY/nT9/Yssbmt881Aq4w4q1ZnNj2dj0SmSwDbEsD4i9PNXIL9\nM2CNHeU4wew64GLWt/ptDiiK4yZ9aHqMw87eEsJQ69L3epH0gwuocHxQUZ7tnjXB5s/D7gIyb/Ym\nX6RQSrMtTjlZ6u/22DpzCZP8nkmYFaKbSxbml/YfPO6dse5LMXfrgPy7jXNWOmIENTiL1f6LjiOQ\nQASeR7NRnNNVJJkP0v2yWg5jQV5KTFnzQ0BOI8qLtUaVWFETEWj1YzuNl7KBFJYhemi4g9ohbI7V\n92yHGIqpJ0nXqAQjlFo1Psoy7NkrgoRrXezuZUwu6rbkFydyjrVEKOut4z2KVJgY4S4wpoSuziq+\nbkuj/zwbTXlxUbOkOkOIvWJh5OVrCuIG0Gzff/oUI6+3mlaxh3gpxDHj2CyxbjZwovZWtGBbGg9h\neCa0l5/waOh3wjNgxFSzAY/pwKNSbfSMRZ1DpZEC+KzdIHFZeYTWgB90qffz4FQAW9OpPXWKA36y\nOfMTKSbsO6QDnP+m36Tc4oKLdvhN3NE/dm1cMUkPpF3GHI/2D1AKSYLCGouuSnZ00TPahEoiCqGZ\n386k8VjO+/oU5tc7DOYNxXL8OvDg5mmTz89xboN1B4Bgk6k2EEtIsTrz84znGvJVfiBKkxaGff+K\nYyXt20FM3szTM2pNxNgfg5itQghSc1/YNTOukpHlmqSBs4QBzZIzNcv9XWZi397IpfYv7itUDMeZ\nX8cYAxzTChE38/tbaHSuB8J94Hbi8eslhByHGZjw5GI+jEMXdXQ57CTxMXCU7Gy/o9Cox+wFd/99\nuq5HGxrh8zrVsO6fIij/ggaZw+sbBejUva5lZIwUSIB5gJ4jYqQpRxUlZKMqSLsrA0sMOIUJMq4k\n7cktMeajqrkkidhU7KBe0OQq/AVcrOndZM1K1PNqEwQqxNHTHxzq4jKcvOKUI+WgSvAifQc2KhA/\nyx2mFUzsxmPK1BfgDCGLk+f2VQBza0d0LEHSPjCfRvpsCwQvT+O4JlUq1W0NdUzlGT0TU17ZAsr6\nWcRkAqebkukSxW2zvdYTCtEhiOV46NIMLo8x1sQX7fEjvkRbaVDH4h8zd/n9cz1u+RGiU1J8KXZe\nCoXAgLVhC7cEDCETgvreUUbHbvlzCPkMGqkdIG0blvo/nQvVtrp/7Uo3aNKTlMlnBFd70RDKajeZ\nOsrxi6C4lT+pLv3FtyF6c5S9sBOvG+usOEaKG8T56z7DvVuUG2L4dAX7UkmUIFMy8P5V5M/+iDjY\nPu/tnTcSMQchPh8V1gqYLJzodvpWgGIOFW6S/YkwD3cG7Mn8AuFpZR/5HVMrQjdRrWUrq9/dOTBm\nOGh1FyR/mf1+aStk/TQudeqfb5ajLFKCGnKNZShVKXD0mSpPVkiGw9tvp8+UU7yTX8aqSlWfTNOZ\n8E5lYEXI59ARyzjIwPvMOX7I0xQMVwXtkoC7PxaJfGogKJkID8zvYx6/t9Jl5+e7DKRxM4d/Oe7C\nj73ed0BG9SZQbTzdJhZ6cne785f84wm68LO2ueDXe9coqefVyLKAFLtt278YDVETnIXHyJzgIaxm\nr4VuVSCmBqSK7zsARUDynJQRVBdNjIUv4/0EvPGKw1W5VU685eM2oGBGdy+5G0jM5jNkbnhkHur+\nbS7XYflMKlAKYJ+I459FSiyem/HK934IndUEblIyhuDLGZWqpSDy86+cRJrGJgVYUd13zskANrDS\nwIOZTxjTSS/rrT1kTWcz5aFkILA+nmAN7bGb+UCCKJKjPg3LFRh5icqCnD1RrtDyOGKQ6cKVWNjf\nLUpeWm4ocGLZ8DuwgsflxjWAy+eWnPwixmBX4B9lww1xo+tKnP4yx24mHYW7gteiHNVPWUhzxks2\njj3CbXCColXTKz9WaE6fPsJXdPCkW3/z1xBNq3uig67KogwvXIj5VDdRk5Z6IvIkVMTTCch2O0yr\nwJsrdneru41AaO4t47oce51sj3KZs4Nc8EEm5bsFJWkcsMdgW5cj3q6I0/fhdVDmJs+9VaGgthh9\nxZGHYCDvY1RG79DHNDhRaEFB2sZCRKf0PgVS50JDW33RsHmXrNHWDhq3DCDdWP6SBxt5Nj1Wh05S\nrbXJsQG+IWsAJj5i2UE0/Ff/S+6hx54lCk5dZGuIHMSVYM/uF58pbA03o6VPA06svrVmF8AiGV73\nVcBROhtEOxlWSm2wr/EZnvEsRxxk6BETaov4h2hvydiZu5aHpxORZQTdcNVC+Z85l6IGYzz1fsZC\nSkjOSybXNE8+l89LjpBNKnBqjhaGFSYqXpf6LcIvGLfgNtFUBZqss7InBinj7Vwn0gJpbipyriaC\nTajOswhxQpr+auQ0YDvU0YAtA3rzG4dejQ7KIuNMrsFVSFb0Qf7OJrDnpdbhF5PtgRFh4mJ2PYpy\nFyshJy+6aUzPY0036KMBUeCE5zln9vTJnhf/9dX9KzCUc2ijypeJS3IOrAf+WU88pQYApjmb4BYf\nkr6zqp24d4NGOb//VKh8fPUeJ3CAbaBJTQ7+rmRpGtjMi+CdkUDP13AqM/OHBFIc6CqU5ZBZSHtS\nZBp3fdjRWEy9/QAFYOgIMgVId4exHhHXFwIdeO+4zOdBMPyk0XEKtWxb4BFWvoG6VqFRoNJbmIK5\nc/e/sO/YovlVN26lA2bObRE23T18Rnn1qbL8rjx9xe/+a7ZIAWswsMJDM3ZYT164YPFZYhEg9c22\neAxrUYiLlLN3+KpmNtPDcX38NO9fVlrfFa2zPguXUuXj0yOutsozy0AsjYQ+LtwaO8obfY+h6NLe\nP8LjCza+RNWds33weJoav+JxEwEKi2XWJQFo4tC+qZ9ruv02nnhtGfQu3MQ+bKuq9AFYVFoQoIvt\n2nHY9Q+RQgLiJ8qNrME0xZu5wQ2wVjUY3M8MlIC8SyycBmBNwX9saoTn32I8NYt7hIqc0vlzmpHN\nOkRJBrkhiEX8WPUc0MxrGo7lrKkuukUa9nQO06yAUUv/y72EIzYcA1jozdXV8DMUV5nx6fzjcknQ\nTy8EQ55e8VMQ2sJxTLPsRtKgJLnHGTUXfoeCeSrGIcZncBN5WYFWR0gnuZwoavjjqjd9abDcA0Yo\np+qPzARBL6pYfW4iu3WfnS0DTYtOAPrMmyFVu3GoG4H+QJdlVW7LSFpAul/fULIGhBU2joCGOJj+\nypbZRNeMsUp319/kt6ERxhmkKcaJhk87KZUA5X7mU7WkvUgOWf3bAq3uIfldSIxsQk6gdG0Ed5p/\n3fcfS68j8OIaJFzeC9pprAC1xNBSf/nuMsz163Ipof+CkY0CIzlA4yO+QysV64FIbZVvu47L7Kv7\n9tGCJ5Q/Nx9J0i3CEW8Y/md4gb9sYzvv6/EROGqQi2BznJBfSSSRfkDovht+P36T3LWs9iR8KNE9\nXZfwo7T4RIgvEB72BgVmHv6MLtmZwkN02SUqtn9xsGRYQmNOCJbxJIHnfgsWfT1fojFjzDdbbGlj\nwZgduK2ueqESdHcn2U0P22ohhrAC0KI/fXJHdEhLVUMqjIWHZsVKJ5zes+CmsbjBPDgOq/Ftr7eP\nwgHD48d6FhJVlF5FpUswiNAU56R2FGneJ/X/NkpZeBsDflsXDf5ToPZD8TRSanguMXSx9Z1zt6aS\nNeXaJWfuNt86DHFy8+jHczOz8FyIjiw3kPqLMbsSV+l3YHCtEy5kA4I4dcmD2hHcDIPENqv8EUa4\nI6YmkIt4BTQaOw5oCE/f8WAW7ggmS8kxhrKhPeVOaGxdb+libYK/uVcl9hJSZlB5cs9i2coWZoFa\ntW/xVRaqs06UC93wVuZWf9BUKlwz9Z6TREc1yGjEKsVWNclALQx1Buoln5JZwImR0oDtm3OTFlZE\nFYQ7xab7Mb1SdloXuqYaet9s5DzQfOM3iRYAJFTfoH/gqhy4mk22mifU7jKxQpAiLuemycIRAG+f\n7jSR90n7JFt8cVi9K7sU1+YQwKPKmKnN+IoyzpWpEDv4tZaVeqLt/L2fYDXbRo6r/hxC9c2h0V/G\nMT/JTJASEpaeyrJFmpTFYBkG+0A3Sqc1ZWjEk0CN9KpIMoA/H5mdR+gb0WHCfwg3QFe+lS1M7wNg\nMFdKvmlCeNe32r4ClNVyMldD62uYPYJgiTOM4G4pAsr7jdTn50hnFjuETF47W98vVvrYR8/Z59kW\nkke1vBxC87ftKir3S9j8fID8vqVhUckxOZNylkvzVf/Dh5VG1Ruapvm4RYG/H+LfXy6NKUPmGfeb\nIdM5H0MJdAN1UPeD3OVJ1npMnF72rIGlZPk8tWillgdNMq+CodxXk0TJbxgXwNsTGsTPiM1V0O/W\ncpLkrna6Hy2KbaLt0aCq/3pbFbwqGKDC1x3HELpBbFzFMRmBF5ZcQE802IopdXbuISfK3lPQ4c0s\nuEGVj5FT59qOzBPCQT4SwMFHVC6JmV5uV6nkAU85C7kTMsRa1FmNNHbvPWyI8KskofZsvjZLa2OY\noBQLDG5W0BNvcNL4LF8EZvk6uwVkTU2iNXDF4DV5P/Fa3SdJW4tuo+96qK886tVU+YJkOeH8JX7P\nf/GHjV2caoIv0B9eEGUTLkIgTelc8anxZwaGZSinAFA6zoXOXDaQcj3WHVb1IyRWLlFHpwnbXUsK\nWE84yAezekkVc/pH+7y49iQiGuqHwLiZGj3bHuHCkpmkgjggI7/dsfVSnrXn5SS5cqT7ekEUKe+1\nOmq+5NChcyHS04571mgnyVx0wxAiJ5X7wt4Nyxo+qqTfOdYtly4CXnpQMXcSi+fA84PxrSmxGIJD\n45ObahoXXvAfsXDScbThoPdWAWSZk3ZcUKyP6sZgf124UQMehc7S6dYMQPp3GtbpqBQtZ07frUTb\nDblc4GNuq7t0DrJQ51/zcXKWhx1VzsRWL1fFjzxHZwtrsXryM8CGn7SUPPrU7XamMEuR32sP3EIM\n78modxSBokKcoYRDiSIDAWM1S4Ubgb34lSyEfEM26c8rC9nboxZqkMGj8Fvh3uOHGEpHxuSKJp50\nNILBvf2/vNRhh7ZGRipOEFoq154Ys8JyNu5VQCRZn9cRP/Tlu5Q5l5TNOdmsHxeSYPdOC2X1eErB\n+TnIyNKhycAMmwBj5/gQIM/SVSBqvs6BHD0m8sQH91sY83zqWeX7r2DfiHXCcZtBzBYMKsrc5M2p\nmWHPfo85t9EJrQiLIyjLf3dWs8QO5JN2ka42TwQ/DVZFGspof4+hB0AsCofNblX+GJuCyyWT1cd0\nGDZXpjy/I44ZRlJ7S2r2ByTGJdIg1uYFhhnOxTcEdsp4zT2ZNSZJL4ZVrvPC1lH/7TV5wg7r94Na\nzISmJYjnVpdiArC1Dw/fc/SSzHQQ7sLBiRPZvJR/I8SuzfqBI17Nkd7r7210QcGnbAmSMqHvchv0\ntwIOr7EehCgGJwPAhgBCrYBUOQu8SFZh8suk37d0EQfizbyGFhgJNqg8RjrkdiJp2qraudLSspM8\nDzA10CWQsy6+1MrpwW80Zz8R1TASXXHhs+LwbY88b89TT+0s5LnRc2qSuCzOLPLGfkIZbj0+BCMD\njmPUWb3SbHdP9BEPLvtbRLQvjd8EBjra3FjASI77t0cKad1xFM/eQxJA8s/8z7A0du8TdVcKqAi7\ngFI1+ECHQmUQnUcP5+X67uyPbUpUMJ5NKrmVikHxTgdtdXcQqikFWmwBPFOed1s6ZhPqbav3T2k5\n4ZLVqUC77KqK+f67yNQX1He1QkWnx4G8tIDaL5TsVpxpVKy5nt3FfsMf2LFxMzMRv5ne8J3qcG/M\nmHPEZNDikLWlkgnd1U7b61qbAkSScIqYEYG3NS5unixnlexo1NuB4mOE+51OinizXrb5SLlOPHt+\nyd4sQP1JIB+3bRYisfUkekJKiH7lrcrV46iBrOD/qg3xBKq1O72ODMZZdrsbZ8n7wZQ+Vr/P2UCT\nEeUCGoAHdDqnTm1zrgWEYAZC3Z2y/YXwUiuugTzQw9YKAoSq9lmNDIivaJKRz1WIMBGp6wptyxzK\nj+KzERa6ygZBBorxb33N9NxEeEnqmc5jnfGw8Wj1RGz3qcCFXadl7N5syQGWpA9l+SbJG4QowG1n\nY9ddIKJ4N4bRt+B4VcULyJyYBU/lSSutrzQY5zg+nOSYtCl4RzPb0/PB7MKVgKEmYSUtm/QsxPZh\n1BxY/R9JkshJxPIMXX25+qJh7kJrxVzUN6VLGLhlGwnkCkMjW7o6dNgWFuFX2opA1Na6jlU9S86x\n5/q1Vf+x6XF/6hlRa8Tp3wzuKF/V2R4ch7V7KOpGSmyGVWTeJd5rKKQNbUmSqNs9bQ4ELSjy8Dmc\nMtnhNdqwjoSiM+2IW4sAdD9OtzHEfVcqGrcw8wKEhorwKvwwKcXLIXy17xT44abV3v65SydAPZlf\nwFTGvwTiYG0SwilQKfxFsSMjV9a30ee4HGAQIdDsg8B4WMZgVUwSGwI2QYB3EY14I4r1juZGk6OW\nW+zwrM0L0cdA2vmBa1s+uZsE3xiw8UgD/jxRfk7Ane89zfDz6rjifJOKHFggZU1usbAdqZOSnj4E\nmow1w5gsdadRf2LCNythTQxQrJkX6MdG0aRnvZIJYuWnSbfnBhBnnx4WnDRh458jlLx1sqXL5UgE\nkjyJgxt4YdnmmIj40V55sLCcG1+TjK0B+zRPlf7/vdJY9SkyuyC7ShBsronP8x0jWIbDZKAviy3W\nFnyufZ6a4ujRAe38SPVe9MODbjEQIe6Zz5ayD0LVAn/xPeSNFbOfJ9E++M2/cJjmBJWO+Fb3Qaa7\n+eovVEzDis4zvoewu1j5WXq1pTWz0H4FFer8Bz3OSWjDvxt+yIYxYe/iINpAhcToBUJURD3wtxJC\n0wIOBRHp6PIFB83W9AHNVGriXCT0sk60AIaAAilpgY73OdApjIvjzHPF0S5M0bOC8Bt92fzI5jbZ\n7Y7IcuHal/hnB+/rIkrAhK7roeX1OM83v94q2j+2PAm2Wio1PWqk3OL83AqLAu2vYDb9W+Xw28+U\nMb28P4rYvSk4OQquVxCC2ytajsEZivaYLkOjnUWfXpdGQwWA//2vE0Khh7dRQ5UXnojVYcdi8sug\n0lM74Av18/PpY3rTcYIfJWuJFmYpd6i2I7bI8qPU++eGQE5byBEPKyWGpHfOch9Kc0NQW2uUYqS5\nHcmElE6r1FBwpB69/Zu+wcjNkaWekgoZM1LL+u/yrczeFq8hjcYP3hA6ant4/+Y9txHt+Jb7KLkS\nAzqzeCB676Ibj9NrnpseiyBFJCN6tuNwW1LeyPXeUtuoDJI98+l+M8hyDmn4zmLtBqXJ5lcde0y5\nEpQWcntTJ9D+c8jYAJv958TUkdKdy/N5Fi22i/MeZpgQs/Eil3MDcKJHdQ1ntQciGCs5D373w0E8\nE+KFtfO1/w2/ydTUeao70LQ+VzPCbSSh/Jw0QYwgDK9wR4ef3ozEwIhO/MZOAXZIs/b5n/+q6b8Q\nd+LeHMmhBwaUi/tEuswgOyIYPu2AHsYlshUjzg6t1AFDLuNb18vhluBKnBOzK1gqaUYj/SHCvPpG\nGpp86FsH2OXG//ktB+4gS2QCV/7aWsV9asRRb2/RSxw8rV50jmWKSRGfRCs9lQDecxXLDWteedXf\nOmvZA8rDzdwcIKTXJ6qeA5jIgfZlifKO8llSUjfVkp/yPzilf2P/BWx+vCKw622Qho49J7HJ7Wc4\nIdgdcIrz+0gHEHNhbtfR77Z7QAKsQusj4gt0eir3mcIXDRe0lHP1chH46M5Be338TViuvKunHg0K\nAq2ZgSR6Cc/Ju2XCmwXSSywgG+3MXtV7tIFqyBhU3ZJaDOI/RCr6u/OQXLxZ3m9ykvfDUXt+UgHa\nuSrMhX7MphHcOFcpUknIg1zUsuuHFYK6gSatv8jZs8NXA1ciJ3Zu4Gv2XU/6OwzCY2houD8SRUQX\nAMkh+H/9e3+IFgiq+tq5xX4I17TKBfw6eYrdyPPLRays5A3GEQQxUuFfEWqd0b77uVpd80Nd3iPy\nzO0wu4PfdczzXS8ZGu982P0bGAU/0Lz0i2hLIwshXOG7TBY4bY55i6QCeRb6jjg5qrBweXllHgGl\neirZ2wvmdhtVuKDqLHgI3WecWfU5tupCPsdNoVPm7KucSOBI30ej4g5JpHV1si2WLAybKU1l4yM/\nsMSDqv4eUlSy2YLtdyli5sKlX9JFBOdHyyrG0huk9E/8zBcuCHcpZNF4QoEKKZkmsFxL+EHzIv4n\nLBrgYJIr6O84mWg2dSjlndl5YVMz03e5bMFwVCMxRTAROVB0AexcFTz2hSrXAh7Ty3yJA/BbRCtb\nHOyhIqBqODoqB2JanSVeUZdIBDU6xOgq9H3gy07A5bCnB3T1118aHlkujIuo7nQaGTlR/b39Ners\nRh+cRrTSMn6oDP005AWsiM6oo1DMdq6sdQpHCG1q9RRdpS+WKFqDwmJ/Y4Zponn/AWknz6WKDAFt\no9uV9TM+2rgkv0bU8vUKgP46uGkx9bVCS9z4rvAP1khWvRMHEe/wnYyAwTufSRETlQYw/Es//h5O\nVIQJPnKoc7tUGWjTTb0Z0jQXsP2xRaZODGkw3doJu/MckL+uxWmJenuAJ/9X3ZPm8tq1BtZ/dyE6\nE5ohRxgk/zMBEnMLeAAY7VK7k5nKvRpgbjm7+BZDpCTXM/Ocr5yXV2I7keT0WprtcTK04LfjkwOy\nuJiQ3xKZzV7Znvl8XiZhr7w+vD3OB0Hl68pOP7SxpGjEPszLr4GlE01c6Y1S+eapwJpd1CV5QOu3\nIh11EvWafzDJU8yYdRdHHWUt795Ehc5WsaTuKC9gwxE0wjtROc5KbzTWaRKtc0QZvqyo5X3y9FUz\nQmD+0N8xr0Satmp98SEf2hJZZ+KIDJfuWrhU3T1WGKQySg6LpJ6GY1rR+lIlv0Jxc/QE3sqClxKy\nTIF6U9AWNBjoZt0Qz2hmjeOW48AOOZp08wztDnQgNdW4kzIY8qtZVWr06mNej3vHg1Fw3YsqRWQt\nlzRTp15YV1v2ffb55NkEp8mTts5ETXNFoEePWwMyw+NkpaWuT5ugBbivRHPu1cgPLtlWe3FXletS\nos4YogI+uWiOO4kuzrei3LP7W0DNMdKdh823VUVxxeyKJFKD1s3pm2TihaFIUE4wQrR43iO4vu3+\nZh3wsRhJmMgC62KE5hIXisKzxmi6cPL/+o5IKSJz7WvlVBZhD+w8mwyDxqbdg6NJnDdQrYcgsR/B\nCdHGecjmmmwkitvMVhfFgZDtPsJUm+9BvAOYOGwlCkQpfkEyx6Xvewj0SOqr63FflrMJIG6098BD\nyEXBKNvTLkz2r5B7WJGRD7g/o038ZiKp4HPe0fU3hZNsfKpHyTpEikkjU0E9VjsHnL/4IUsOX1OV\nvjaM9Lv7wxkfOfy1P0GlB6jg3dK2JJLtFyRHstK9wJ6bSBQpJBjTb1I2fxZDidFPa8iofsgeZ/Es\nUrZ8CJHnlE+jrsqErvyI3HhkEWc/upLYjISzW4Gps3OlU2qYcX4nWiys3lqUSague91wbJiNaSOS\naggUn5ihiT6pKGgcxpAPPJX/1ligkhMDKlMtHSVM18bOOHqbrIG9eVeYSQYCkjP6NOcvMkhHFz1H\ngy0c8LeBqhzp5d7EilGQsYbCb/NFx0QTazohAt2U9O91IEz7cpiB6sfTf7kBEcajwJINJB5drmca\nNuPZcPbUU0pdh3L7Ydc6NQhQ1AJgmhRUfU07Ici+6g7mPCBVlUzrOHaiwSbQJNtJILC7EKzMbZSa\n8HIvjlV3bLUdbFvZl9MONLE25vvJotRo4ojn9tI9HZ49qJb5sBpOtknzj7C//Gcn3bmGjsm8Ahyh\nQNgN2LZ3I6hmtsnOG+CovBDfLldEjr2/UtJesn7WVvfd1aDh+hQ4fYmukEfx/lBIQevXNiKA6qmo\nL1B9TvqfsgnAXyLWk039kPyNMgc/jg8lxYSQcX9ZnWqy8RBvzzoQ5d9fLF9m4rPNAMiNWvsKsPo7\nipOz3hpU3td+8XIisWO3VsplajsKoI0s+lRkI+Jx4mkRPoANECgorOaK99xCBN1kT9y+puktXymE\nireYUglNGbQVJ5jvhJXT8m+9X4tMQCYExHviQxhvROHIksEax89oXiTW1P9IAlliT6d4X6FXuTXt\nj9ITtSRWEsgkCiDuxptE5Yaq+w6bb9RHvsFnb6t7HAN8lBqkhnhgr17L02qeJWnPMOB9fP+dcoyM\nob3PjOFG0AvH+LPOOusZhuQqUufvWyC4vdQSIo7yGQKQOQYVu+Q2E+LG9ZFuNxIP/o5r6bUuXBv6\nTG8mYe/SSkddTFpuZ/W32ee/bhfWKkJxHo9SDFrdi3BZDk7yTbnRk+QdnUyqAODGXeR3pxBBhOlP\nNKutyhPK0yfPmRvtMkdmYrpKMiu4Ysisswni2f4Fgdrb5X7xCjKVbSB+KrTstYOEi+UqZT1/hfYO\n91/owLR4UcjK5++RNDSnAK+nDL3nBqDUT4bg90JHwZ5UYDGSz1DceyiDMPgRyZetAXGFnjNwV4oF\n9SuNkQny+MSsQo8OyCzZge0Kkwqfj1N24Tzr9PpMCi+wpRKRtmAYItWZ/6jDbUlOycK2dMeYigPJ\nNtdn01zNP86ajGxP42DPeyw/duIkkksiX8rMKa7JWBBsXu8YAo5ZbajBVzN4BsTioX5lMSDx31uE\nbP5qLtWLvWe1Os7XhA7FxAtfvB4Hc6aSZLpVLl9sw54/mpbawWWr2CUrJQH2QIawAxeWf2oa1LwP\nDPUzb3SK7sEcqiHaKMohWAbzhGhSdtvZ6uNtYIdijdK2c3zXZJ5l8E6Zbpa9ze7V4mYiOxDGpyaj\nUETkNyVltJ99FgIUOxobxWdZBhKd+91PN+CIFbwRG0/5sh2C6q07FqA7y6J+KIaypSOGR+Bfkhm4\nR4pmcmVAMrkwWuSu5FM5ftqeE75rrnPQ6kgUHt9BPUmB6cEQu0grd41FDXQdzS9L6rt9BV12I/W4\ntyD2xP3R7pAtbG87ccq0W1V5XkWnlY/JnJR6osxmsUyDUUwar7VYSQO0NYqoYsVkWCsf+hdSrtiF\n5z0HcfhprkKxUGVnvKuJjc0olP75v+LUqdmqgQjmgeti3pjYgxyAlHJvC08soSzyU2UM+lfmXyE4\nW94jUix1iO+xyLJHyQBetDegGnyiBCzjyKc6hmK7ZqC/i08s/N94z1K9OHRPF8DiAAOkaPyKJOLZ\nPxj4p9Pp3KJbNR2OWHqZgl5S0kffsG2hrUJBsbS0EkXNqbNiaKu6s31mpA0dzGQTOwmvvw8sDxa2\n6mMirBkNLjn0uFyY9MGk/cYEcL50qZGCn9oS5UAMTvEAXZwtNFtsISnHUCKKjBvsFD3AI7XCCusD\nSiFFRhbrXFIAcscD6GwKtjm72xW+NBMZBo4JEMDZN/3gNvt6ijV66YzWoqhtuu4o30rDg2tJtJPi\nETotuEYJlxei9N6j8YLIx1mA2NIc4wtIUNXtoUeYXcKTML8f66r68RK2Aa15NaXzOk8B1v9YOiNN\n9at8qkRNwvnB5XE61DaeXPSWZE3/69Vgyna7LP3sVeBYsFJRawcis+JUiFoQlNhml0WolyAKo+DM\nbLmO2woWlD2fidljUZtbDcvER6ej9FXHURkRLM79cbvyJUa1cmDfVUJA6aVA67GbkyPIbr+sF5Ry\nwawRFG7wOCX1onfGZP4K54unlGh/MVpd5bTUJOqb5Gefs49uKmkm8VNy/Wmt4THdnjXt82t3bNTG\n4kZj4LX01kcXNCLlLotK7zHtaGk3YCvX8Yv/gapROMDmGKlm6S+tc3ocURlWYFqzq5j+77nJ6zRu\nOkkp2Bxsc2aCX/w1gq+HOAHwiOOtzcrWJiSYfjd3eyozXShI4YQLh0hZsB7Bnc7kVwAMghIX/Ovr\nb5vS+jJn0NU2RHB3f8BgugTlG+7LslZB2qlcxjxPgZ8+u1M0c9NxXfMjOv4as2N4d+NuQsoY5Z0n\nSUQwW88yAJLKKIGsaNuifYutwr96t2anudOBxFhzcRfSwUy9zFhtxS5O7Xuqbnl4BIJBCmD8RXy/\nNiRuIzAtwrhjVjVJ5QqENu7U0557OQRQIUeTFHro7nX9apRqfZ3h5iDs6Zn7DUN/jnbp7KO9Qa8X\nvQ5aj3RIDZl6p4bZvWrmomRxMUvr1TQeiFP87/iUhVgXfnV4iltzNK0FyVb+TreATt+2NGKzKtaw\noz40xCg0gaVALu+S3OhvATTwxtbZfpyFAii6pq+I77TMoTngF4NIhGSd/igcBkW8Vlq0jgmEC+Y6\nKY9wDDlZGgfc3oJmaZZup/PoHBxQSekwjdQZ49JZuZ/1ZfMenW9ojpIJtviFirAMMfgVyHNnUTKH\nDqcmSBtkQOPZHEQXIfu4gXKrKORqacRNV3iQ2LCA5SY3jV0OzbQY14i/Uax4PQwfpccBUSCrSdPS\ng5fJKRsIKlN/s/NPv4a9v87CjfmkKuFi8LN2DHt/H05rlOAmWUy1i/zE49BgbgmQfN+hyPAu2xOP\nn8CRaWtMDKEuRkE+p74vKk2jpn4tzoL3hLXnnbx755SqxaQ7NHi2s46Q85Xxn4tIUr83pwKkzOyh\nABxEBw5wxiTCY8DcZ8tXERHE9MFEErXzJCx0nJl906k29jQkvZy8lFaMqvJpRAa+IrhGINxsCgmv\nEFCxJyzLmIXcQU74GZFVq6Ff5PMZwMZ5zv6Sc/BtgjXuinTW16PG6kvQt9kRRIvRJlhU+UkUT4lx\nKAKS0BGWGeeJvj2l3pMxQDdDW38JEdo31S4f3+nO5khzTbRvC18uR3gliKELql99hVJW8Ughax9c\nZGk2OjCbk3ltjSOvDPWAJ05RSePyNe8EDucZDE8mHqsoXayXuMecJiy4qCxfaDSCZTDLidH6LFnL\nedyWJFIX+mVbb4eVr5//PembRQaXZy9zS+ND9SIxs/GYO+dOK9xNx/YPceGAHpCwckYKmm/MKBkG\nW0Ct5G+fFTyG+bjFT7wrvm3NPl3dy5CdRTfTSqd7vo+1wDKR9/zap4A+YMPoKXLLrrpZ2ok1NP5b\nVkX/k3BcSC5njQnTH9fvzP5On46+/trfuEtR/Lrp5qSCQb6l91v8g9ZDejjBpVOXzTRexrZ/8Zhu\niyh7sFt2Ge5FP7UXPm+uH7a60B9ix1lt+4ayMkF4PomdVxIw371QRqLbv4DRKRWoLkbZ6rS+CWeM\nylf1mWnABLs5Oo2V0TttT8fmxJdEhtXbsivuQqioyxEr02IhROX3otGitKBHr5AbmQnH/F6vtZzi\nCaqP8RXzmszm0Yuz1U5PwdbTHSJkS9tZVIH61OFh55bzOdQvHCUIHMf/pW222U7rt6pgBXuglCd6\nmUT9olxfc7wbXnpK0NuBpUt04dycPN+XAVxLmJsojwcGWYLJhzi+IsmWPzDqLINHka37ucbA7DXk\nrsVY97N0D3mhUT5MBPDbGs8L3GzsxB0qrXV8IVeHdygkKPAdftspIBhx0UQ2oo9dKVRnjEH2jXQ+\nuGz/88NXJfsJ5fJcrJp7wQe/BVWDlDzDtnZiBrpF+qM2H6mimFzAiNTEPC/mneBbkAkynwfbRUVG\nhZM7j4IWoj+BLG4SL/+IqxHltiXdVkDW77R/xwd6/loUroeXPe0wSQgnFQVEyyjMfnBCPG59enWH\nvoej0Sz1XRLU5enuDs/Kurs2Nxg7aua/Y1KNx98ZChwJP95YQTByf/JuUoFA8cndeWI9TWWkhfDv\niu1T5U5blsLUZUrHvo7+j4uaLeHpi1jvPdF3KdBRNC7n5PrCzHx+5NePvuKm3XKClBPXDHk/tPKZ\nNvnFHM5RecZo6erZFDEM0DvcKg06CGh5+uRGDbnYBRDsuxva55wQoNOPRIthT1BvpCAxsfx8ly5s\nYZWsxz65JkC9O0YaWVhkz5d42kG90QH0aQL9Q5bnXKveGd2mnLB0BuhJz4M52MkCClhP2NCpG7+R\n4f5lELJrWgZ0RebHt2zhPzv/Ts0GhBkErKIon4/gI3MfkIwmrsnq7+ScCwAfQ5UFLaApSWxbQqK0\nm0wBkT6mJIHt5ogNU+0NldNcW5oLppBJoUxi/xWeugchpg8sIq1xywzFMc56GxVpSDAA2V6Pyoxg\nr/P1CMILvU62EfqAOE8j8sBhtUiMSZTYnSPnxf/B9iyyUPLpk41jNrlWFJpqyJPkRmtoJRmuJdmt\nwRDGzcMQa5eeWdsX9diGqMlW7g3EXXvO0PzJPivxLZ7XyY4O2omKCe+mSmComsM+PpHwq050UsbF\nqZ8JWgyzEA0vi/V6u0NGXzubORuYUya1xaOcpWbAx2UYYcdMWoIxoo016o4cc56hG84lIzc9yA/8\nDDrpS3wfm1Q5oLJW+OWQFC3WodkY1P9nfbvUJn2vil/D9VLWV6s6MzD+R9ZiWwoctgdo22CllTtE\n+K3Sc/fk9NCdu7Zqgrm8u5brtTOQBPfKMEazrov6maCdYicLPhxSAkwinrjntd9mUSEh/3vKiptm\nE342O/cbk7cPCkvvBtA/n2XgsE9uFCfCVSAG44U9ZJdEOmeycEmzJeC+mjP037MwyVDclm2TdSZo\nutvwFRGDOmR/c4lxAD3FgTNEwL/z6nWz/kHNmim/7fWVNVi2NcqJbQ3tCDDXDQwQQaNZSPmSueb2\ndFrFZWtW2pF9mz5wIGA1AV4Dwjh2/tXQa2C+JiR5XqjMO/2+8d/G7+7fXGLrcE2jbeXhuwOyqxRk\nOPTTIHDcTUdHcatvkmVRzANjCp0vu9PVjkSFncRAA2qEKp3xc1RPBU9U5C8SqW7KYIgmdNhkc4dZ\nFU2fYnR8I+TYo+D/wdo2eQdBJjUystmHMCXmcNgeh6tPYwdI3dw6k8YwiCTFuMd5Kmoowdb9kWWh\n4TEamHDfaCjpdNsR32vJqPa5aLFkopu0qgI1yqbiNlccxiArJdPsTVrq32Tu37oPEU9F3xbDSht2\nODneJZ/O4uroTze3rtf1HGcTsIkFI8ZmGHGjnhH/c2FY17nk9zg+AGjMYmQ5zdJMbbfFiYPLeOo+\nz6eUlGioPMhhZjlpOJptCe37owgRiiyXqQ9ubMVaYIqixhm3waw/k9fEFwadDw7DrRtzY/4Ybh8B\nLSGwctw9PfhRRSrer4W0FqBrqqj3XcY9Gl9upH11oZ6PFmXxtavCnnJE9hhngNOEyaPKKDo08d77\nJ9Pe+lmd8wWBX+Pmc+4le7lH5YgQeAJngDbF2CaQqrlkgkhWvO4hY39Xr/IqnTcDv7jGOGB2I19K\nCQZ1+56pBn1JIGdlNeIsk5S5ED7ZjTxtSEieiFUptFNkpKDa1S9JUgC2AQO2uSciv8d5wyBlSWJe\nGKYAPBPnWGAJiAAmOv8Me8/LN2OOPi+muqaJHMbgVQU+0i4gM3L9bObRNLjVb/42G45N4HjSeKhM\no40Dbjf/0d7Sny0suxswV+sw0IeHR9annz/7C1DFGfv3kecQVYzNOEeA/Vf4o3X6a7s+9+6LasdD\nAXYGbGaNWlphE9I5621gN57Zr3+5pT/bhtouHAw0nzicuiPeljRbleIj0QjN4b5EtlXtc4lmqoXb\nru9NU+BmquaUzu/2AzDZoGjcF0/zie8SPoN5CPVT4AGfzndABDMgR7CuHUon8ZxnCvDh5JsifNWb\noRy9Cymd8skBrxTrDD55Me4vTEFASBkvA0V8vRLaFu1BlHSGgxetgGA11LJDmct2VsoBmAHbzz2t\n7WM68CxPeHc5ilB+qpAzupL8KPLnKoGTqgpCBeXRIxyxrH9bQiNk5B+9QE4suB8Uvfv1bz1P511b\nDzu82uh+5uTgnBkUCsmAozKZNaEVKFBNfesBM1w3i/n333lbVTHrYxDSROJAQwGYCoZZTZd3dT8q\nzmdGp6CwEHGwyv/vCJYG9PfSTHQwy6w9JZsP8xdReyr62//LGj76tj3Sr9RhcDM4KgjeTY+2YhCb\nSTlWGVjyHSyuaQMpE7AxZkBRQ8SxcRViooxkCaOWwWYFUT+W1Qudndmb4l4d751sDxK6WRpZe7Fj\nComjRrzWRG0ku/u+tbwF5VZNqelCTGqEfpHra7NgUU1VFi6zSmzhyxmKHrKAXqmo4fvbhZ0rwJsb\nZSubAtME80Zf02jrjQbxqWkw5GuVRIOxBxt/dhpOUKwgiMdGzWGa489MRfb3smzzwaUzzuK1eY9+\nBCo9u01okTfI5LwpR586WITkmcJVIJRTl/P1kuVlCko+8dBoB9O2DpvHqIVCk0jB7df/azkgDlYF\nhJ7GUkBOhJ5hckKAqCPc1KYVqVhLJ7hrudqNLwolBLvDZAt6TMTkefjhNfv/ef3S2TvpohPYym3q\nbTYOOMNqr9VfKFNpqJ3fevpZoHc5rpaysuQdmdD5GRBZkFiiYJpEnZbt2q/NZVEzDEDrqk2MbCJs\nlpysFTF/G+sC//AwRvHqxZjQVtJa+Ygj/KDr4nCwz+rKjoc+DaqHRG2GIWHI47Q5rkX7Tl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zVyAb5rrb/RHo5LzjeWCG0BhnJsCAjrlLPgvKwkKEEG3cRUoPrgzwqic+9EDNgJtlJO7Jrv3tEF6\nrWFU4gZsILxLtMpa+EW/xKOQI3kdt/9zl/cz292NiJvV/vbbq0mkhR/y9C3uISl48M4IiOjy8nQh\n0fob+3bidpNzxf6bbB1jg28XJ/7RheCSWeodNiyVw7Tsdb6TVmoczPB2nUxjBJNsUV7rL3uTE474\n7zrz9ooEl/52tJV9xgn0VKUy1JDHef2OhYPSAjm/HqmBURez/fkUfLQgJhRf1D8BdwY5z8onGhzl\nwMgzPw1y5Owboao0mSf6VqcRUEm8FSD2p/iscbBcpdSwCnJEtjVBQbHAomIiom5iCx8+9ZkPtHZK\n4sX8exFr0A/spmEjJuFzIbo8Jl69JANjj0Nh6cD4k+YTsxe9lxYrGZyPWEwfT4jeT7zE6GyZG7IP\nR+Zvtiz7Qoua01yPvoZ/JP/r4IXHu5PlZpRotJIMN4uGYe4vWWActVrG/lwK19Dzg+Qx6zbGCdPR\n+M9QxomMVvOhMzWdh0hQ6OVh8qn4t8oM0ZrCK8H51JLEP9vDjXT1j/nNf92ZFh1BWiQxHkh4+lqC\nV4eMeGwhthNeGaQ+6vTaYdUvw55kAR+JP7oeVh5Xgz6+Ov53Ng5MD0FdJKlhkidfsRa5F7jSy6oT\nfa8hQJTqCJhAHZQll5V1eZRwltxESzFgPtVX7HkqCXL77gU+hIaI9aL3N3bW7VdhJsudRvBV+cHK\nkqg/tgzavcZ4E9p0IeYcgoF0YX7dpJx3KnXJ/Yf6MwCEomjmV9+5my3xIrBuGskVGroFCd3Vehpa\nDQuuwxmGD+ZeSGQkBsOCH/yks00E35gN2RKjAQo6dHJrbyGIjbijl+VP5L9TmhXmLdCEGjFPoj6E\nmXNotu/6jhOzCj2TOC7Ra3PSA50WNugTpKTVkmZmN3p2HZwVBNuHqmsPKBJ1d+t3EhwlH9iIjlju\nCivX/+Pvwem/0RqiZELpYQ7lr4wk7aYBvr2Cos0va2ku4CwNKbEhKeAYkVJTgHKGuOtJdiSW8euS\ntKEljVqDcuP0gOE0esc0BwLcJB7nROKs1tHMioK5Nh7z9DUjUx0TcfKAANkkImg2Tx8PqpmagwC9\naANzk5gOwbbT98kPrS0B7xXJWEJFv5WKsb5st4yoJNI7aalZXXhGsoJqLictxT3eBUheHMSo3v7u\nd2VzOM5kwUKKMKrWch7weKiZ8TRMX3Yy9HpzS+ExAoinCE0a74DJaqCx/K89cpwQKW4XitvJ8laL\n7yw4kC/Aifgv/JGSqEXPTyv7mihxU8LMCmb40SO2bErdH/Lu9uO01ON79PW9veBi863bxOxS2tUt\nUzLDSlMpz6IBIOglIlAAX9bAQLkHuCzgXcWFUiUAYP2Chzlei/WlQpAkyEzSOK2TNn3B4s2CI+68\nz5MV8d2v4AcW/ZgOf5DI8CaxTXYWEBTEdOO/usI9NEjFIujZ3CVMucKOqy+uBZhdbnxfQ0c70Q1I\nK+4clCIlMVQ1P7xUdsUcwGedDQxjJIYRSl5D4yV4bSR5bAqZH4Y4wu4Z5hlb48eXD7Z0AJ8Q8qjP\nzc9z52qQ49qX1V5JHL11IbvEifDIaXDh0vXweXANP7OcxRIIMHL5onNFW/ZqcB5PPOEbHeVSvbBw\nipHATdV806XNoqYtFh/J2yH3gJIjdw0qh63gTjfwIumNnnubWumxGhu4MUHI3yA/Fg+XifKreTbg\niVmQnb5wJx0K8NpsDvK84cdlcLmTn8o+MvVlh5oW8B6my31dHJIRfwdfcw6+JMtoGR5QdGRTACG2\n9MrHJU9dFa2H9cIIMBWU6GYWi8uesrcSW1LzW97j3BhHwcGsFYbi9hUgIQ94HNx0eCn9zgUWh41r\nnrIxFp9zV9ZtUYc0F+8YZfIioVXwUmNBT/YspbCjtxlDibUAPqZ1rvBgXlsEYEp4TMe+pcZwL7ZY\nwjHLLdW119Jz1a/TN75uPJbgYe7YqqEzLBO//uUqjrC8c3ewwX0OFnbKbu9i/YMnMtaPVbon7YSp\na+7m8fOoK7ecR91f7G8rXuBQinj3sXXnbA1feqVoPqEapar2TRNPnh/jkROZSpWvxIRi5iizs25Q\nmqaBxFHD9D7vny5sTLr0Fta50RKsUK5cPxotPAGv1U9bfhssAKDkU89/UPcVrH95lpmZh31y7KSh\nyIk92vzJJScJjDxuFXnbhNsXjdBstVVoEPR0WThvNcvm/DsmBULWn5lBcwMrCet9gpcQrA8h4MoF\nZKl8i7fkLnZOIpkdhiuqI5X96IVu5Ie5jVx6/pe+9lhrhsOz1R4C4p8WhSsz8kcVW6bnNTTcC+5l\nwPYdCJmdiDyyhVB7+idzhWgSepuLzveCvt8eLqPscGU+iuKBTS8msvyE3cbi7AHzA0D/e39aWRBu\nEdXp7N+iwT8xR/shfH67oViBGhwT0fVeyzl8z1ix+LpC2TUCS/yCUcddhe1Gs8WUs+jJLWfIcEwH\nwl7GSv5faemlnjU1Id7/v8gySG1Qy4uvLt9pFjbt9MMdH9OmLS6ZugCMBOS331tHC5NEdJrZ3ZJ3\nOCVAY+w+U+l3ueGsHvlf3z22SfFsRPSE2ke58FD49urZ05RKkjXtTldaMXBQP9hAVlz0HVcbXX0H\nApiP/5fWXn5XPgcOaMpMWpqYVF1UrAL6mfZxMKQUeLpXnyWh9Ba/KmQRF3Hgbcjs44AmpQXkhS1N\nBz1CyDqE4vyfyKdBKX1H+OU+gqSRvy4ZKGDjYXVHzgZZzqW2Mq3G+LSNC2U9iD2nVlvZztHI9C8N\n7+JOeeQ0OJNorkedxplm3cXrwMqWPGlesqu2W6ZUqNMvL9F5NblP/JX5+jUDOE8R7SVXTw/tTOy7\nHga7m8JYZ33gP/2024M8g0uBKcKPHPTmw+OcNnT90KtrVMUmKZormQtX6CR1qzSgyCVl1egEC0I5\nUwrjQGQ+l5/c+F+cbtjKvsEVlpVBczoF4+FstU2017O+85olHa+/vxMpRF48k2JjYV2iiY7aupht\nb5YQ0BZkf7eYj1De+vfztYtyOF2mTc/bV0NKo6n3iSlECiLvDJg/yEIsqkPkJhBJzBdSyi/Hk6BR\nRibPvIzEWft8DpOvqv9hJv2B3YuRUHzazBLwWSxjUVilLHg1EYqAWPE0/SPolch7MiOTQTHEbSun\nZrx8zlh/BvJfPzhCk2W2wk571aVKSfTLa5Xg8S6b6T+Dal3fwI9pZ32gnWXTBlZLM460FL27F+nK\nifbWQwbQRSnI68+vgIa0KC3Xg5AloKlZUWC6dR3GN99QFqi/vcWMoYxZnlztQZM/GzdqX/BJJinm\nbiSGwMebfJM1I6hTfxqDsBn8W2jcoHd10qK8poRaQF9CUUQwRnW4C/PInClzTFq3rmk7bGaQKS5u\nawl5waiQKgNqQcWnh8Yonbs6pYu5zFnwjpHzIeiWm3H5WTskP061wPrTY9moFEdvEF74783hKGGS\nwFMxxXhzEPPV0fah4Z5jI3wwawvau/4kBuyNFM+/BYp3pGg3CmzZ1c43ZvvTKVw4Qxp8xeHEjCfd\nLKuPLKw5+/1BxpwSs3xKRXcfpJ3LS1tA3O0X5g7qldaJwB6GkwvS8E4NRRuTgSkJxzqTBWzG8+HC\n8rm8kakRSRoE2xngh4O8C6f3nfBzZvW209aoUHhlmPRKrI4EGy50wD8x0zm5UPsH1Nn7SG5FNBp+\nWMq1ck2/yCEYPbYqRiYlc85tIFB1H5sY3n8c3zX5wv9KyY7rw0vlVzXz2Rc/CEcjEAFdh4s/L36B\n/9bqcM08gClxXeVGCswMMkbE4GnSRyPhlv+CLcyvpnZFV41nQQx5jBpfw9mj+lA9KUXY97TelwwS\n49FQFqVIQb3ZaRoquRmTwhcCSeN+u6CiyFz8p6RtGDAU+qI5kbieQeJWGkDwOL15Bj7JF9KYaYPw\nhQe6ameSDMR5I2SwfShu39AmM3+lHoOSgERwQHIbVR6o3sTBSFm+hAINyC6DCdRHM1xnQ8XhcCPF\n6VL90h+WqngaC9BnuL5+yqCSrIQLWuAj8k1IBuAp4QTFE5UTEGWfQ/h50tyftJwDevSlEl5Volqf\n6Yb2Scp8121bssvfqr5bTa3MM5E3fQGFNzKLnAZHhGFCNVBr/QY2CYEMZQWyC8Ay8yHqAvxmEC3M\n3j739HgHkCrogx/IiRXWmPS7rCBiNV5XfdmPbWU3PaWOdFDcighKXZ3W4K3S1lgjJeA9GfIsqzD+\nwipIfTPanEvM/QnKS2yhX8tdFD/AC7BoBpYoWi70Mfuc10BfK4/TmnPy1Bo2XGQwNBxO3H0ysqK7\nhizQaW9cMW6ZW99gpoCCaalN3aEO+r1dqOnenvg5Os7V2EWGEh03suZs1WSJT4lLJ+dDBfUWX+dt\nQLn6cXtH651BzU/AKit1zvjRODXxM+6O2UijNGy4KyG8lqWmCUKzKquxqOy4IgVZ4D7Y+FfaN3qD\nTpb60xVDFAkVf+wqtHKUKXzOp4wOswXI0gC6YvVcSpbf8Tu0117V8sE5CzoISgwmA9qWoQ4HBX/l\nNFjFxV+tQsjwPS5KW2stKt0PnCsEKgqZDtjAfAmOOw4pVYEEtR94SMsZ2AZollW3o44u7fP7DdAX\nayaIWt7ikUuJY94vKjA1+yTGYK/pIA0vIIQsRSH+6bsGiGPukBmZelLV3agOod/pnDFN7tS9o/yP\nRLT2vB40tSkjqUDEbaASAA9QFquwgsGa0+tQT4etkWjpYxbPMVRQIDVdpTvqipGodjUKkjxOw7rU\nG7ipgL6N5wcsGlF2tFXcugVl42i9iiukUlHu+hxFV0yULD8HaJfYnXupdxoxzBtjxOreQjIFKDcw\nn05j61Xo9a1AbRfHfBsSS95Wg0tddyFfdrkA3s+gEyJ+x9ck2j9xyaEEYYKfTUUnQClqQlJafWNR\nAC4rYH4mpOxmhcg4/XmJ5sshrZ6tStOyEX2T/ou9KavgiZfsecbHNVvP+q9FqsBBNofTNJVdoGgM\nR5i53OhlYTqz2ZLCkuNNzlYdMjHb/2lBL/ktD/Zzt8n+RPrHR6GwOGjYSzxROCSmYAvoSk6Rj9RW\ndRCNKLgfOc4rCXvqSOk0VyK66OlgaexQXvDjBcX3yIMtG0bKfZOKzKA3IjNW1hJ18A5o55eVLUsg\nwMvYaVfR1myvkbCtN6ymtfDgRXfTiulpXB7CcfvdzSRVtIrb9Q2pA35Nu7MoeMKDA1bbUgo0Fbdy\njqmbgf0fpPZzBhtmkdhKrb8AMd2Ba143ZTiBSPKeS5AtOfh7lmVKIkGmfFz6KCZXxQFqN917kT+W\nLIktfeZ6Ny7jBvr1ksTeoS+zoAcYwe2HgpwyBgfoj/fLInG1bxLgLjhJmlhAAREkxOTmOv/dKN6M\nLgD+aUvS7J6AYc7E1ltaR5qVgAiFbrblLocDoYodPQ0JsYwfzR/r4qx+rNyAyUy+Mf90xJxKrv6y\ncrKTbMWfsM6shqfAPf+C35bcZc/4K+3zcKKCl4VuQ4FB8A6uBilokVJvhEYkvLMMPMBIMoVLh0kR\nrIbcTbbev8l7FqHwTzBl3I7GM2ysGB8LGxSwDd90G4JlFj3jdC7Zc7Sz/8GAITs2+XqXrelXcdJH\nTAk2isZ3APlPM0dFS26mBlamSZLASyFTb6CJ4DGJ627aMoJ2O3gZYPjcBEXScdJsyZztzmxAMe2G\nc3qTqakUonYaiaHISOXUPjI3ckZyxZyVqydL5rEB4q6+LcA3DuRHFKBhkkKscm5QM18UFCaqD7Q5\n/ZgKHmjUyYYORLaJ35dZ1vycj8g1XgILU9t/dOEL528FoVXkwH+Km6sjmarh9OwHBU3PO4DeqRvr\nbW4L8KKjwC6sEISdMxo8TCKLHi7rqrUO4sdUW+5qPqUg2WWEZudfNW53jOJlrtLAWZLHa4RYh1Zt\nnrE+e01Vgw4Ab9pfTPTEI+q907Z1e7kgG7uqs2dZNbEweH7jWtLA/nPyoGKrmT5auz7+wQLbcwDN\nsGN062Dsa7UGRr2nb9RtIaLtRWCRKuKBZ93VhGQzjWLIi6MuRGN9za0ZF48xkbgdVHGSjg0veSXU\nMV3UdjYyX41mNBku90U+TiGoUwdCm065jsYMqHcJBg6oglVRdVY79aFEkOuRNVJEHxLlEAu1H+a5\nsqOJzvwDMdtIeu/yNT87tYb19FQf6vITgWAUuBu2cLis+XBNN7oxRk3secoJyx0NvuCSrh4TBuCy\nohe18xeJQ65APaklScoIZRuKfbCsgzPIMXBFrZxmjxxgLVDmwaJnDcqMjfZU9h531tHaGKd7Xnhq\nJZlbFm1MtjBJQYyubii3MWNlFBcuQdKHo9lwlug5EmDxcN/HaRtxDxmd04yc3JbqW7/WQFqSNT+5\nrI2b3g3pIwLdJiamVNO1Gg6++syMVvOYcSrH2DuD0wsLQq0UesRX7QeKV3xBoydNwM+wLFtHNc0N\nPteT0WbM/ZCYk/Ql3KZmXgl9GW3fVz0ap/QCjoCC3NjSoNkpXIO0WT4s5+YTtxSwn23PXDwfATqL\nYD57/Ff+4qRzHZ7GdXWoPrpkZoD+/GAS6XvFBuA4BiZX05I0AkbTlgYCGreGpHKTvBa6aQ1YsYYu\nMExHjMeSU88WDHHoEiRCJx9wHP4uvZEDAjf9f+J7w5vNsPozTfvHjYhn59IstCi6OA1Zd2KnCt/J\nb9QNN/yvTAUGg9lGYNgZHOTabUf9iP/o+HcrRhuKZZtF+SMqpXaZvlvcoD+OHE3cj6kVqyNeMXcR\n6VCphi2FOZUMy0WlWd5kot44E7NQS1X4gLKxjrwd+zb6hHoEZ3gFb/I7uF0Hi6BB4LpAdqgabnF6\njGVrmrLAof3i+xkSUuRvMidENdTVUyoT7iFxvIDgR7H7VdtdbWrELto4v0Sbk2/wPYsTWAM45M+f\naQszzpL3CIdZJL9aKH5Sr5WV3hoBELJMeyXD/ApSiqioiz/ZoAfIGU4FsPdLeEhDV9gLezQINL3P\nxiDuqxuH/uNRJgjfWSwk8hAbRjvwVHvMrVWJgV8aLwVloTpPMckqTRbUywmnRDSBTHEEjs6QyS3I\nB5zfW9C7YRiAULMGyZiQsOBDJygXpXiMNRgNWnl2d32HqhPZJcdI1Yf4udzuE32HN9IvGWJe/p/V\nvUfzV0qPMpvT1xiUaiOswyljuaSZToL9sEiKo9ivAShhI9QjnLZexZ9TBD5mqM+aBrj8U/gR6Fof\nt2iv+yX2OikDzKgC2ZaBm3y8kuCyXNyRtmVQAsDTqS0XwUcrpvAYCQbPs8zpMJK7+O2BLDp8uY44\n80NzQ5ttdN8UQO/oj1wilgWCxQwjWRtaAoI/gHuhbwdj2r83hMY3+wtWKhr3fkcN7ae3WNGDFnSa\nHaT2kd0oGLKcQId8jfp+bVjINXvPGaevnOYkwRJuKhBI+3d2pYmbdnxn9ybRO1KhQNrGY95pIH0Z\nW1+Up8HZGVisQ35zI2k2+B3YkQNPQjiFZ5zMNld0KT+Ach1xkaIry4b9Mz/vfnqeu+ELNliw/3be\nzlnviHUHGDXw0V3SdBPx6FkrtUghHi+8UX2sgST/QDDfd5REryDuxy6ZwaVQ3ioYnR+CG8Wxpcqm\nKwtfMAFNa9RC07YNfSMGDT2yX3rJcao8NhdXBJwkj6qWYWlHm7vnOYyaxzzF+pdaK3LHohGbQ7u9\nsM82EdDVJdnn8M5Vo5pCGqBarCLFrYNi0edPtcU+Sc0gEDWDFkPqAsB+NHk0hhWBdH0lI4RxV06g\nm/5vttZwDIP2Nq1Fhxu//ZIqH0uMmVOiZzLm5VU11jnaf7TkQgKnHGyxnb2D1kqbA9HlJIsr0n+g\n+dRpFgnBwQHqi6woBYqM4r4YLJxQVKJ8oMHGo+jjexwI6CVwidgr7RbJ7Bmd1GK/1osDlPMe1JD+\nXAO3FPtl+s6Ql7u5t4+mWwbgugSx5obXJRt6gPzLiqBrxZ4h61TLGf86Nt4xZmTo7Y3f4vgWyqx+\nIOmIGjyfIGFCPSTRps9Jc68S16sMTWuheaBbPwJ2/ndX4BSCPIRBSy62d6kubKiviyOs21BUpdnO\ngX9MLRWTsbd4439WyvGxFp4xtVd/nukJP8z0qJ4BOMyhMo5QcuNzHlYuVWevDhWwYw6nuYJpr+VF\nryHOXAXOoqIx5rvRnRaOev4S+NkrQSdTyArOvR2Lbg/TRiaTSNHJdkd4ozGrYXTNKN7adNR2NQYT\nPdZiS9f5b1j51W6kNrE+yiR2JlllSYqsHlsEKdyj0uyhuYEtdYwWPLNPGgrYZDX3mr/kzhpzb37I\n5nVI7ijrE3AfpbUs/GMEO9zqEPPaGXrmThL7lPb0LXHbcDcKJ3vFAuswHhn23Jkjk29EAkspZGkh\nlUhDC6FIjEJ2vg10nHW8K+U7J/5UJJquYCD1m0tmECv7BjbLSDIagEG9a0QP+K5HEjT0JZaBRphP\nitaQZqx/9bt4PTl2GDL6xwd9PzM8AzUT85IQnKBV5GveqsrI97XrkYs0Stnf+lt7kE5joy/1xpyt\nb9a4MsYVQU4HqmibOCcWk0TGUFTYT0TyAJ6BW+Dfv8y5VEgvbZzOf29TWc7yKwuMwf1/gppQWpdZ\nZwhBDfS/5U+YLPJ0amZqPMHTqcbvZesoElf42YH58KJK0ketT0IkiCWgT6zyBsmsgfDnm071yPBw\nJCj4lFyLqH1pox65/TT1nYVMv3pQq/spQR1CO2HQ23sMTl/s5wxzLJrT5Ur7lAwNBaj9s+nmQcs+\npew4wVNpv6U+BRpHjmKQw2pJRElM29KCzlRRD4q7v8L+TEs1L1xFrgweOLSGYGwHuovRlySPjdsr\ncaq4AaGnz04WtPke7KJ4qfOoixI7tBHIxXlk2UY0txWHwLsEF7tJ8KGWDDKUrrPGJDjpOjcAJPnW\ns/knjjKkk5cMz7W/FR58NWnW8ippnKbkOqYBUswWe+xpHhkAZgEEsznP6TIyT9blH4gWWRZza3dy\nIr3E4B3VKt+vcQaB76UMe0DJUiMbIPXfeeU6S/s8rnFbEhvFeuy/h6eRIBbGrcevliuo96PlK4T/\nHpY8Dbb7thzKl/48lQsxJTJqw9mXeITQ9u1CAa2/lNoyFEXYOT6QDXIoKfVi5GsnASi5qifn17n5\nKqcLboERX4vQX60/mnjVZjpToFZvgDpQmNY9jaDT2ehIY4HA2SR5NKG9pKQe6kHG2jyKoIeNLRP0\nR8LwRXSdr6YP9BxA0ZjvmY4H1ots62d77LMlTdW/TkdBHlvTozPbj7uJPKTh8YsaGBMRP7MFmCNv\nr4IFqtw1k2jUNnNq0/bcPKmQz4zgqGCVchVWKIVSFjz7YVQR6zLrCqJ3X29c9wwUp8lZa3wTRyUG\nzo1s14YclrmBhcFMBvpjbLdtEHwZ50LSwNZZzOEFDEopxVGSSclAMCtriTuuMNE/CjIoMEhDHJZf\nMH17i8lQw99g4jbe2EAFYkgZhStgVOV8fDUlbJokd2cUeTIRCJHGHedL2AEDbsKmm89HN3QSW0DQ\ndp2YjTT9Szwgl5kdowkC2c3NUbhzyijbTzapgJDCwpVElyIn+oN8uNB+IqL2W8lFlRf22vgDJSHn\njGwevZPM5SVg+tn/wqwFZBzmPdTKoJasHdBOCIAmtj1AqStGA9bWGXdSlSxsJ5E92rO6yefafWAX\nU2aRhayR47prO/aWbC8B0ZrFW9H9D8voCtzMzCaSIW1DMEa/m5TACRmLco1g+7BU7b4a+bZZ5OPo\nJDBGdbdMoAsZMb8MlgKHQrP8XQYJtr+zPTJRw8nhRRP0+hyjB4dZlN8RQS8Izbde1m6r9soS2sw3\n5bwpgdpJm0Sjd3PRPejGlbhlgIbsNx3OUGcb0Y21pbagdYskAb4nJNYhF+XA7wjOeGSZQjs1GyoI\nyhXLlp7BqRCqYwWXGzkEf88v2RtoJDKyKbCO5/N1oLakiHP8+rpbmS9T0uHFwLaWXZMSn1fKJBek\nK8X4ocf19vFm4UCPlSXd9bY1iqFTLolEpYO2AyUJnK8UJcDCQocx3fYvg/3aHsgDS0nRRsz2X+Lu\nTGPrVr7xeTN/abnlEQg0XDQSpNaKoHVGiOgZBEGhTmXBmTnRubVfe6dduoKEls5Zens5crLVriSb\nYhrFx3cnYxlyrwJMfj6+n8zyEErqEeLCA04D3qvOaEaBwHCe/Rk8b+X0uzLohxz4oqC2IuMmgzHX\nyT7woDg1fjeqkxDrzYRhtSptj2/EyICb9tdDXoOQ824GyXiPCsUlOcFeEgPR4uqd5x11XXcl71Pe\nxCclr6CNFdflPdhFPdfBeZvmL5CielLvc3a6I0lXzM7tzZJTR5znGi6JcajdIE7KVXgepHsyErK9\nnUmTlF1oWR1JKxSsybK5Lp7rFT10LrXisNCqvNb8FGR4DKMUFW2fwRcnE2rkdFMzmpkp2a3WBNFO\nL0b7u6wz08zhpcU+P9LESJDuYmH8KeTf//O/AzZMTKKZu/ApghlpBY3EWFuR1mi1qM6uDc7MKgLR\n+U4ILlc2/Ew3BjMg/gQPwFMSDNpf4MgynF7IlW3KmqIx9Rq3nEyL4NyxanSLN2MWgFkbaAgWL3Tz\nb9FzSc+oveXmH42hUj1S6yNnj/E+CVfC8CuC4NbnFAYzqpVPytCCa2u4qtGOnEGMoDsKS30pKONo\nhBoxJ4wXEBlb7hgF0mgyHT53FhFZT7I/RsWI+atSNdG51F1t0M9b3lCs2TxCBnshWj2tYechcMd7\nMjQZZGfEhLTLOxrOAQsc1/WrKKIT2EvHnWc0dRgwp4ekwjPE/TgNep8CRbDytRU2qtTYoncPc2RC\nu21e1CZISi6Ysil91Sh85vn8UHmXFN62psBzoucgi2v7jGIMWctsFEn37mQ22KWIPCvXDFPbXPto\n15R9VyNBhvrVv3iODlDbpjubwm+pZ8XFQTP+yNR2v2BV+RUhcOh8ehztNT9zulIy5+qBqsNOgxLs\nOGwyzmPxPj/ImJDnUIBnwhEfq0P3fkWHGRpzEXTyyRtQVF5tEOWx4k3fFQu81iMls9UEnxlFIxb4\nbrgwnWKrXpsO065gvSsros68274v5XrvC/9SyvhrgdYgdz56yhlN8zHDYsMIcSuLgOAvQlNG+GUq\ntpycSf7tS37ffDe/24NTKtKWhBYJbhf11hxwpngFGW9GVbx5NsXi1MnJ82XSNTru/vV6eVI+pOF9\nr6Vg1Jc8CqpXEgqBAB0yhuMx55TTletF8hUgpJ1zRIfWBdQmcsvwqk6jl7yJz7Y/ZW/QFhw1Bmcg\nNgtxvqkg+EQpJJ0xVPA0zvAp7VKnLV0XfHe39CwsedQHZfcGY9mIUuXBHEdPvMLvb/hzHc+gmXI1\n8ERF75Hfx4SQ4CQGhcuYJNDvRVMv9IPWcaZ1GrICdXu2405jGj5ZSjkFHJd1OMzIzEVmXk7kHWqF\n3iY82v6fcRwcsk1nCfRgSMaUai9pZbQIiwqi2Vsc6kNfRv6JZBYqRrI63PsmipZUWkCfN8VYxcTe\ncf856PLcTmmZsjm4fX8+hUfDvcmGHLjPYxCYm2oGxLA0A/TZcDL9eiXgeIjDDOyR8QxA7/0j3UUD\ns2mM3tZslTRXExWkI+IORkG/864hVRbEEVI+Kw3BNn4k9kJXSRuwM5A+YsEpSM9eGl4ttMESMJYl\nLoY1FGyMCXcUCmnUcBT+t+89NWuBfeitTIQqXQjOY6bvW2vOceFgew43Bt7ekIjoPlwso27Ihd5B\ngDnsAFGFEZWRNZlkc2aZ+7uXAXQoenElIe7JfJOQKFF7hAq1kWk8UJ21dbWPArIHr5LjUPOvoRrR\nB+YoYYe6eGhYdp64MuaRZVxbgV4oQgYv9t8wW9dEKNauGNh8Klf/z8gbJgO9Xfe/dOw2X/HfDhnj\nnyvujGZKa/WY8BI576CyVWUhf1eVcLblVRZhQtsVkDUog0tq8bZugBsOtkfNJpSGdQkA7YZYmLrS\n8qiVU3FAGf8wFxhUy5+Guy9OJq7GpZScvVdOJX2vYgXrBXwAYEVINau8wT7iivhIiUY+bf08R+lq\na0+yz7sxf1IhAc0xUJRjTmBNAjNIu7zzEwtOCZ8DNZXcjr4FXpbjszVccdoKK6mlODzEKqWqQyb/\nf+ysdNgMN1PNeqh+BKefZ3YocjW8RHoNDOPOgPE1XDGcIDjNKh4rUg3GUf4rGkyl9Y5xqEsWxiRV\nigpDpnunIldWywPhCbMmTFxYpzaXX8bSi9HQsY1UMZR84nnKnvISF2mA/ZHbhQvJpr0mLZIRwzEB\n0WBbmey1V87u8LL3Si4ge+I5t2knrmkko4ogKV/sLxAt5yDupK9LewVtSxownb9YTrYq/+YE8VEs\nM47whLOfZ706zyq/yrxukV4NZeOuOsQIPFq0zEneOcNqTHT7ffkSYicsnsRl3kMd72gPD48gUPru\nU7oV/eGpqcGePdOBK/techfx+eeEZL00Aq5Rb4C+MoezhhU/txKeAIgMKb9zMoAyqZyK9jlwZe5R\n3T4t6oy592qK31fVl0L0taNZiEsb9gXzRhSVeKP81XYD5wcC51dDpkYlDzV2JbIPD6O+DKWNNh9a\nH8JN7MVr4NcyPYjh5UZG1GKJiTXJmVc+ZWJPjFoTqs9JcsIhaEBuMRFtCyxUYsuR/XkGH6oRSKzf\nDq7+ZD8zbFQ5gC7Zn6S6cXFR+c+YOEFw+Y6HrA1GxJaC1zztZyRe2fru6v1n9Tzt4b6kpKzhDvW2\nlj8fFcUrU6OY41FGg119MmfaSKE2OU+apavHQn6ZIwNc3iWvFVJagPGTtAYAVUBhzPCA7yk9YnES\nEpOsklGo4MrXK0V/A56fcod5TTCcZAZzDs3hnqWd2N6UCqC0bifPYN6hu2uQe1mIEl3QMwjVxndZ\nhGIhvWosk4Qa/3climQcyWDbpCcPMRj4nF5DZo/VCZzoQApkJINEB9Iq09OidsLurgqAYcFnEGOI\nK/PPHSqlHFaRn6qpbwXuSZgM70wGnaAKuUo9e6RLvzY/qtl92miyY5MLsy5ZZAGiTHMsZMXhMnos\n7FICC6jXOSn/rL++08+HToK4L7iIDR/o4KP1xwcVbk1VlxSmQsVroSQYO/tenanZBB2iL58YgiDW\nC/IBfToxS764rwb2FiQPhARu4CxXJhe9QfmK2i77T6ymi3eA0CpzobAQebV30a/sfF/tKToYzvAN\nZstLqOdNKvQJ3attP/5IZ0ZAMcmVq8VKV8SY1MOAEi3/fqFF1QkQkmdysxpk/wCqPQsMdbDlJxBf\nZN5+T2V4YDCL+UQUTDphk9cH7TxW1XcDk9+DeClBiYauISR7OzCsF0R1ZTv3slwIwAbKcHY1rJcZ\n1zvq0HBF+qJ5rNRKLy3bsBQVEySMFPuQUOHs1Art7fURZ6TFFWATbR2DqF9lNoxlyg9UCWuZCoI+\nqR3QjHZ/hmpR1Njvzt+tKRnuBcIEl3yK+JGJYZ/I2LmPp7J61ZDEq3I5aOJo8+XlayE4oBMR55Hw\npBiwC68T9rkjwBmZ2x9CTgixkdpqQHlPrWIk3YZpOuw9MHG4khq0oJBdsg4EODJJxzTfIiqdx66J\nJCqAgMki77TryUZNzHE6e1Z+ZenGCHUA1tRo+9jbcCd2inUaWLpMeuyYXaPVSjkxXZbvPTymmruj\nu5Jaa41aT9Y6RJT9WiV1X2CzNud745MWpuHqpAB67R+RIC0Zf3rEJWdUDXWRetAmzaeTLd5Mz7sG\nZuE4XENSb9mpCN3ZsxUgVHMenXv2OxCxgJoDjIyC2ajA2vAhLPeA8hFCtgCXDCqW3waPnzU0n3ec\niby66TIvEfzJdmEpJwRd21C2OdMFWmQ1YsC6m6eB6IEWu430dYN+X0xv5gUj4xSrN8rciV4vzWGx\nPeUu/Dy4YtiNQot6KAd7GgOBRMoyusxi1zWPRoae3QZwQJM488+JefhWuy6KV779GR+V/ocfmRdM\nhAzbq4BmmOTVtf2x4vAzOw6LhgKv681FKyC2I5VWllqLiC9jtFjlFj63ePctjvhFU8geSEt3D4N7\nx4KJEa9QfmBHWN/T8JouSpIuWAIDfhCbNR+eCQgoTM3ltiZLcXik5IE58QqjBhF9x4T657hwsp9C\n3DRhjWq/BIvPJIuWAnf1ZvFJyZ9EyfUq9h2SVB08A9d1mjwzXJt6JgVEaFckBXCU9FO1KjT2dA4E\n96bCY7FT1aGAeO+zvXq8LJEDR7EvKX74YSahRwERCq8wmOyHsXV1WTwPzpdv4VG80oJDcw92SVE4\nIy+0pUtKta6ievdSRbwN5E0Dx6s5dEnBX6TXhwhippy1t1VFF+ctI6/j5wJyicW/nXcnYlbHioTS\n3DLN2gOHlhizSu3JCrqaybPYHfOUuvU0CQSpSC9zrZyaZoG8yPgHAXy4MeIq3mlCveAXscGGcY7B\nNOW0O7sFyNB8Zecs0/78auMYnjeci9+fODMfPORLirWFI7N6JBK1e8bzE+CpY1xHZ7nkwxoH+sDj\nfCtMTHIsU2I7QzjzhLE6G7lphv/11UyE8/dtvMWcSXQI/+6zNT1r04xmDMY9z8US01Dybm3mLKE3\nVd+WlllQSOwi0+Q7xUy3Tj97mmuC4nhrJN6rY9GI6jGzjZX8mkkSYz4OQqB92s8jjUvSidPkwnUo\nk5eAKXg7TKq47WgZlknohQxPylSMUKcfxmVCKhZb0iV42XtZDu34d5xXauxHaOAopg6CmQJQIrD3\najDzGVlngpkfJvrsEeH5Y9Uaah5+QeeE6AfsM1fgr9R5Mr2x2xmnewBuEDT0ekl8vZspsEudDpiD\nHNhrXhTgbJPPDjkdUsI1yMWtWaWLpgOxF+M9sSTufIbAbx+5t+YtBLe0MF7C9iBWJanKyqJUpdyT\nYiAzrWQeKaLOEkt2tXhpw4UQ2AeGVVR1+QhiGYE+uqwet8aHwcZnXMh4j2m7YI9DCfoMfudcoeQv\nipwCLR8KK1HHMEntf0EQm69lex73AQGQvL0LSeIpz8CbUaLTPVSYN7N3G3H8EfLAWj/R2zxnJW9S\nzAq2cEEs1gDV+6TRIQEXNzfpwOlCm/mMW111EejtGD+0x/xjxuANm+WjLmOYa8LpOFhfSyDgccjN\nwcD7wBHW0C+Yvn1nFMt9FLBaHtVPR4anRjJMl5eocqxVRUv8qf192gvdQNOoreVrp0TfTc4a5GdB\nXc9ffxxQOI878F+QIoRv48CnFs+DiRR7Ed+cXL0x3kUocbb3YETDdoXOApYdTJ7Gir2SVm8uc8xh\nDTcSIIJH4WUvQg+R73d+B5O7rBU2yaHAVua67HJ9fHro+oGG99Frvw7CI9aZ+m06LHP402gtMfUy\nsD3bJEcUUgEF+1fAeJOWPyXVLKBdlsPqfo9/mckFTTNeQJFy4cYG/6r1P7dc06wVI9/WfMa6+4WF\nyybVtnkrn1sizzf/TwAkWjcQhaOUEz/5VUwjHx0gJ+fdVrQ0JC+4h++JMPwm6A+GbgpwhJ5yAgqL\nDv4YQ2ZFNZyD5zD98GThfvtdJ0mSuvQa+aZAWnKPbnpPQsLVIPLLKIwMf9R02OnvV5G5LVOdtQbp\nv0QB+5vKGo8wMoRQ1Wx08YeDjhkJem4XA8q/KLUKq81GfcqKeEe4ZDNMO/SpgqxNo4ZhXbuRrl8A\nXxyCL4+Qe4/TEz/1dnv8qNux2KMHbL2rOK8TenqJ3MQDWQixrXWQ2rxgOyB5lIC1+u0UYKqzuLyM\nV/mQxC8DTsoT/SBM6k0u/gdlErMo9nJaW0uMyD05ApH2DlhAwqg7Nj5wn3iXGvilYBFGT8c7CPFl\nngNCa5os+Za8jIvU0k2KHuR0EoBbJ/Bdm8Ov+RhcITVub8D7ZS0aXImLZN0yFvxGohMTT4Z3S3GB\nnVhi35jwZ2v8fPRVNGc+VIMxepmlfksDx+6hL87auUDb666LGb2rIn0OcZy7+bDbnlcRCte3v6HU\nKpTM5H4wHX4bzindTZx4zXA1aDqLsgD1XOR6Op92YX2xXzixO9YPOWwQK/2YRGXiWFomdZ2OTyAw\ndu7pKvJUeKO6e1dZdTGY3+4J8jdyg4jF8ptDfphZ+i3zgXqdxRpiuKD0U33Vi1POXaMWfSvdnWZq\nYi3rkhPMNJsTqAEKLATdhoXDhM2j0YKgm5Hxhg37QfGfxNgTo5Opb6t7MZ2Sw/JWXaKe7IIwc+dK\nYkr6zawMDEvusvD40C39HEkawA3YVafSkjFfYL1Q4buFEuklkX7AnCInFRLMPK4u6m4gDNTgElDX\nxEl+i7bCqlJvV28ddr7HQbZKVm3poAjNYVZEXx6QfztCTQbdfKTIp0dlKbaks5zwQz1Gni9B7fcy\nrJARUsu0zcCDsopVkknuQJKJTM+MVyyNNmm85cMAcFX5ttgcd8XjM8mvX1mYyFqKh4Evpuz8LIkM\njzk8i4014o5FeSkjM/fdoUaNizFcYaUkkigsfnWGq3Vin9P3em8irgwNsWxkX7vKAeMj90ChdA2o\n+gBWBblTHSJr/zicy6QuIoS44jkYLdLCEbqH7YAP8ckl8bG4dnPEFJq3Kk2lTMKjP9sGVsM0a8RM\n5w/G7Eo5vwqkntKfFEaKxn1qmNwQJLyaZZC9eeOZps+6V3km/aqqCyBDsOyx1Ga9IeJJgXoVv418\nU03O+cqcOGYQ8RzETWB3NJ30AmuBQOnofRQ8wY7+U7VVWiPqnUUdwpM9sv08wWJyQG0/bI3t/D5H\n5Mc+5rAFzRmDFRbZitf4uLA68uTH4XF0qN6VdxXEZyrWRdxDpC+sNMzQznJDFopJnmkYWUdvgF82\nolwRRGh+FFDkWiM9mIhrPbU/Wk0Pb5DOd4SRmH7kMcKCWnYsUMeTl0Nl+97NYsfHGqbL9snOIn5q\nsSJGSU/qjWcBtXJ+S781/k3q0zXlVUiwuxjL/vHWLVyB7hINy/CxphBQn88DcrRaeX41eKrJbHz+\nM75s61M1rFMCP272XvoFl1cNUloOhToAl7V2Gh21y4bKjm77Njx+/e6kTlA7arutyxvpHahae8RU\nx3p/0BCfzhxVIbHfiQuM2n/43bNZMopYzgoSRPeFXvQefQRZQzoR+mzmgOLHXiHkrLF3xM3NON4u\n/3XAE6IkODJ8ACC5CI84v7DZ5XMkzeb4zlUF4AxIYMtrklLd1u6/IA8dsRts50qPFgZrtAw0I50s\nQ99S0jP2ByaE6FgzAeR//+wX9DzcwtPYEBdOKTIoVHW8bAqnAy4aeozjXO39VNXpPfeHmswbPOE5\nLUBm0PiryyT/hCLbUHTQgXQF8QT+wFA48naObHYV0zn9XzjMQlmDKBxkFKCwWNfLX25vumDCLb4s\nQIIkRGOpfGuxQfxIJDzOJS68uejgYf2BjUgj0fsh/Rh0a4xrP51fhkYK0Cu1kOnyIJHNYYGSTyCS\nZnQ8icjEfOw4G0UtGS6bWbd7w0r5fVB1Qrj9eQmNtaLKTw5ld09AAQ0eqDeg17fMQ/uLpk4nsLfY\nDW3W7RL7/R7sfTVFge9ajr07Hv25rOdHy7vd559bxF0belPAe8d2hQLz0xAVR8YTBkeeomvQi6Un\nICjGaLp6lpiD6gV6UKO5cW7nhyV9PmvbvFl3x9y5jWFEDjb6fMchfq8Tg7m3dyW6u0H5Ptuf0hjg\noeXofDqwcdE/g9NoTl9IdmNP980ZRv7A5ar5+Pu0nCxTz4RfADPJDvFXo5glGSpe1knG5bljRIDS\nPOUzy2S82bN5filSisJqDyhCzDJnWf9XufduuiXtDtlOGXKJ7DLJ8eoiwcvXA3Xpj9GdkVCIN0m4\ns7omABFWmOR2fMkYrF7QlRgLV9KVP/8l1gCSE+F2892Mya284pCryxh9RaSf6+NG03EnI3NlpwEq\nGrfb9uQazDkNyLpQD3c96BaNemGunFv8xlzgqNt1eErOTNaNC6NGO9pDfEscMLHtt9ZxwgIAeivt\nppMQKSMPygmUF/WB+llSE0wtYSCBO5frX4nMxEV+JSYEX1k3xVnr7C1F4J2jh+rJY5rD1fIBueP+\ngn2G4VapCotbdcG3khRLe64aifrt7ZSb10N6qCVgeyzosjxDjqpXxRrUeBhnt/qHUNgfOGhXsCSL\nLvo2D9fVF1Y+FjK+Qkvn/RgKuyPLn/hMrwkwO79NeON1smCWen2IIGopzryhqmK+yZldJ1snL85E\n5z72U4rNin4LG89NiHzyIvhPkBM8yc0zbshtwTyuEJe6frVFOi3Tjm+oqLKofonIJmzCZ7P5xA0E\nowYDeHLb/XfXThNZ6H6p8sNH+hyQXTUqp8lf06WXcaakfm/itBDxyKKhV6XRORmMP6rsdWFcep/p\n1gO9wauEQOgijEj2QevmpPx5HeHHfPhKte0dw/sDdX/ZYofs8T29WjADOn1rMER0xx8B34Fz0tMv\nc4ndJ7QD9IQ/nlEvKyeBpcKAoGxbHD2kVSqeLXtI2WzyQf0VKj8NkZQLH1XuSx3nBLtiBCOwW0Lc\nFFdkyflJs/oNV2nIPQg7Bdd0oV5L49sarSS0qs90P5bP6FFC4Ic7VXLRiGH6kIQHgQsP+6GZnhpo\nm6n5jwJecJ/3+QvA36LDMOWrhOVq7Pv1+0d/zxC09JL5vF+ULdWHW+JzSJq5qpk2h/QV+mFKe1jK\nniLI7eSkGa94WM+uC9RPQuLX/EZuDN4yabWeVTwMwAB920NNAf1g+KIks5suSLdByn1UM/Vyqe/Z\nY3ZU2V5r53Ql93tZWXG/shrOWtj2E0uVKkTNajtY6fRAbWzS7qlIGve3T0dAJvwDHpvHdD9v1e9g\nTUk7Xf3UQowejchdXyjYJjhmD3pwrOSemqPqDGCcgIcIgXkuFgNS9BReKpU5oRgHOF3y5/5kny2+\nZF7+0C/V8QCdvvfUxncnb4RQTgiGrdinSeyadnfDpczhsM1jW9MAvAuVyiiZvGvtaPPPi5tWuJES\nO8Zph69f0rwiX2cNRK3TXy2DJ8jYoFrIUFhuW+L9jWZX6snBBTu1gymrTjVQGzcw5pXPN0a/qm6y\nBOQB+WjpvKGkr/av0W22Q6EHlAAKjpX28TyMtRjWMt4xggOqTJ3a5YM4yk4jIlLElYH2upJW3Q8/\nR8YBygj5ueQ/MvayaG82kClhT8qRwgwrNE/Z/nlEkMlMc5CwxvC/Hfi1MUmHbW2uKEn2l/xVYiCt\nKlOaN1AmPTgSLbfPWhoGof4tCeI9vGWKzaJ8qqnh++yrsC3mATqzP4HtynOX5KqubFj4VebdFWPa\nC+Z3CJQR/1FPocjyqE1BnJl/hxnnVHP1PJ79XVq5yZeq7GB7EVR/FxHRgy1bv9eHVvfAlgSf44Q3\nJbO28f+mpzdy9vCG0dtDZvjlhY6QN6pjXY4hsORYLVP8n3AXVrm9EjZlLLRNAJEq8hs/JgC7/ehn\nmlCQOR2vXAGQVAxUlfrWSt46htdEA74bsXt+vBUPU+rJW/YV4UUG+0hZopVNrspdoKZ/CuyBu90S\ntjbKwilbBal2ZWkapUPV6ZJtkhBs1SrSlEji7ta0l1kQzCr0AlOsb2uohFxb+CFkpgy4QYQ6liNQ\nnWoBQ2FgwiJ+mD6Iup4KpmhS4PXov2uGClEHR9UAHitq1Q1FSQmMT4uoplRM5PkyPDeUKK7KZqyE\nsBmnt2zqOZlkm4VdXb4dClWax/WW6Tm23BQTedEN4I6biS0w1H33zAA9uvVN9POkq10vLBE8G/+b\n8H/Qb2kGSvOTRCdBsp3qxa9GMGRA8LQq0XIKNGEzX4CPAqn4Jq/Prdzychh5itroNzTAe+jbwQRT\n5faqEbnyEoTeKd81LmMcbjR1nNVxZ5TqFibeGLp9MP4G5gYeys4cHcy2PkL6S3zS2sFKl++0Bc8n\nbcCLGs7yNeSajxY2HE5wY89pjbTNBawTuJiS7qkx8THXw6g6JD056+95UQn+OoxJjZY8IwGSJEXf\ngt9B85cJGOP9bOyJCwdXZ07sn3q0ase/YWufjx4lh1tWE0/Wgjc483ePCEGWw1S/IaUz4XvkSWMd\nYcL/nXsDnBG53NYLgT/eJSkmxCCKu9npb3hQ8e/afrBNpKctpc23ROZ1vknolvlzeek2K61jnoKe\nwlq/7U0bXVP2Y7oizJBFUDP5ePUV4yDTE+0d/aEK1XvhG0a7ao2bCmrBzRaxNtNam5Z1nDH+Bc9P\naHm0Tk0w1Ll9LuglbZsvOZ9DSaRn81NcHxikPNnOvV+t3bbBfE61GTbBjgl03zclfXqSeTWocW/N\n69nrYlNdv1x7/J5/NDHtFtZyyCjck9KZiXHSxk6DsEJ5VuyQmGd1fWv9n8msIfWEh0xRaImEmufW\nKVf45sbaaokKf4wBq8fzfy3tdBXajg3rgp5CR0+fwmxUSe6gYVSV4YWUN1xYrz6JUW+mY4Q8BZsD\nPhJbSQ3DP1Bt+5zC3kmtZjKiwv3bSkEWJjXizTIQ7AfHeES7GmgrnWHoVdF+1A++Hh4GeHPOp4/5\nhIpshsZ8V8FZyKSO2Ka9bEk+kPZFXo0fOrt9ZxeslBjVgVwleijmZyIdKhpikXCsbKyEVCkySYE1\ngtQhz8Mx/F60YCKioVWIxCrIXywYW6wW376FABfgRQoaU30ueccURVcKOHT82sBzClCzZDhCi1cF\nnV50irSFb6RruNNjIubBH706vcm2Ri48zWuHFcHL4/60H4Bo1ttXVrJQtmLr9dDmNW+pdWrUxnwh\n4zbTmJ5v7ZfNdcKu56QnI0V8N+4hBxJ+egYKVTy5iQIts0NqxDkbQFve7Fzf9XBeRSY4X2+QU/3e\nQWpO/GRW1wNsatSNCuafqJ/dthM70/bTDMSpS2yRedSEBfavTuR2FrLyjWhnSOKmYXV+Sqz5ipDW\nElJbMEvKrCVb3dYhzx82mWy5FhJzK4xzv9vJEFeExiH4dZaJEbfWT66PTGLRNWGQotN4Zc+mL8ZN\nFhV0Km92kZ/X7+oeOGTGEiKLM9M5NlFxmZxdcSkvpIQPKqnQtzP96dgqHMGxDqLlQwfJdpfVb7jL\nS25WpQJWY49NFXcLdHLQEpB5y+WcdgR9ROyyF2I/MQ0JI6JeRjsTVFskW8WRQ+IPEiPGoUL0cv9v\nJna3G0uuw3JTmoPvbiKEJTbWvrUwVmFhE7NVif2Ilr9Mr7g+RWvdErH03syNDgE3HGfuHxyzY+34\n+tsYjXa6L6lSQ23riuc+dNuPYi6OMeIy6TXqsmyx6RoO27NnhYS9aFUZSXEHNbk7oy5gaoRAUJso\nLyzTX9SDKJWaezhvD88iPc7H1hNnmt0+3GQnaRoNjFeT6HL/5MLMGUnwKtA/QSx48LPK8v8al2o4\ndb9vBWWnBd5BfCgQ4hmMy/wEYmHG+6qTo2juyw8L2VlTa3AWfCmr5cy2ii7zTSEWCT5nk/Ua46ui\n7bp6oZLTsRAoKW/5fYvCbNsmWaoykwF7zJQKJhecla+yoKLE6BagX1nIFBBlfm2PPx7lKTShHHbY\ntJb+i8NAwE5Nb33KyAmSH62+7ooC7beykPeF7ymPd0irOApfCbG1N8K5cxv2SaH90HleXrwtmDAm\nLBnGw3rYLrM+Wb0ziFL8Kx5rjw7OnsKQjA+lkt7o69OTU8s+nL4jJSEDBQZ+eWoSAr4tNJXSX7Yt\n975xW6vaLFzNOEmHep/Uvikw7s+ji7w30z/IZ6nTLI0CoNKSvsjA7AUhX5pVV22ko5/ZppYPSeV4\nbazW4Doq1b2HVfANfPDsBK2tOMJfWW+4E2cpcHPrkQ58V7BzZboqB1z+/dPQhJodvm/sYzk8tKCu\ncrv+YEoqnDcqGuUY1WW7gn20wfsVMYlunO2KpN7ydolbV4D0n8PUbbYJrxOJ5i/Z7JIlXvkoRG2u\n+f+Y3JXoY8mqhBk7XFGTlr2f3s7Xx9t3IjUN5oaAv1ob5/7iRX7kZKEV30GrnV7Lz+6F/Mpv0wj+\nxXx4mZmIn9s3NtqSWqnuYK2FALrrBuSIyIaHlcACfE0u5bZh32G2yHMUHgZzG6CRgW4rU2DcN7u0\n1mAYkwUm/zeHCWME2q/Ao2mRPCJ6ui9ymKJfMdCloN4zs17azrLRq1o4myoUgxAykK+fZ78rGMUe\nNrZ+5+DSKxiqGwkEkhXFMISyyOnyj/692j5Il4MbxQmB5zcgzAnLe6/b9rfXhqVqfSgMDV4p9bst\nLptte6wQOf9Ehfcq8b1N+I4Cg9vRuYPfMVCm24OUWDGoxrhz9RYD5ferxXsiySEcLnIkucmSRX21\nj3jbVgY0IaxBKz5YIbAv3vWhjcQCqha7N+lE44wzxL04bNcImIaDgsVwsH9SwrvQa1448LqK2CEe\nyUgJGw1n3gArqPIy5tzLY0H1QokAKQI7Ge7KjtTp0BsczGRKxmCnw5c8ydA7b+VqfULfgqviNi9N\nuIJKuhBIVz/pGLphqlz9RF+V1bPJJfvpTeh1TNXf0mCLbDCjxM0ESjx10GI0liV/zrhWxXpQXquj\nTdynLGG3tNfWbC5Ri/nIt5mHBIdpwfo9OZpiwCw6JDHu5zGrVVV7GDPq/C9SwTHrurohmWEjakz5\nIugUsW93QBmeBJT4DiWeWSiPLy2dbaqcoSDJv3latk67ay1kUDF01FXez01n8NsBH0H2rS8t1yxa\nDz79HFD35p65x9kGrJ+gJFyTen7qGA8K4JIpDtwuMzYPJG4a3KpYDLU/IaWwImySEGoPxPHOARff\n/3//N5vOzRxdTe0wa+qDk5IM3PlPFqGYpL51nL7JzBhddSKZjqf4P1mwki/8Kww7iKhKQ719BOS2\npylp8sU3xcXfTF6H9tWuM1LSNwKVoqog8Qnka+TCPwSPdJI5flDd35Ge15uiB9dgM/av+LaTIvoJ\nU9MlZLrmssAJiCDp+LRsdQ5WHKqOM50uslvrEX9IrewmvLV47UcaRnRkt4F5VeMZcbv87cbRN47Q\nCRPs//Gj74Jh1S0vr6kv//hqSmuQh+yKPC3gNEaiIWzDtAouyu8S7obpl9c/alERA5s3U5oQuVDq\ntkja1pbygFkQNG205TxWJupQoahTfQbuXeqOd3JZlfZ3B8hQFOVSVZPBUom+bVKxB+ocyaMoXUPY\nxghsu35k19GpWyC/gyNnyNRRnb9p9ymx7JKimwKOBKZ8ZgtVvxhzdKKsEO95VweEKYzFCiWzMNAa\ncgStuhkYFqs3xCam/fY364/OSgQsWs8IhfgyVFITk0Gk9o7z9NbmKaBEhvJBUSLpF2JISyyjTWTK\nJ0QJnx7NbJ6LecMCEzM5A/uisLcgf/zTs5hVePpTfxCOAgRhZVsxrrnGPWtQTEm6q3dtIGLq/oyc\nUhyW2zX/JHniT6VsAWuPjOqiTVfCqlHPiHXxXmyLVZPzeyo6qN6/vpRldBCPuc2NDpQid6nR8War\n0UK/tTHVVa5p3pSwwk01n6DC9C3V3pOe3s2DBfnMHPz8dAr/6CkhkDJ8dF0YezxVEvSxl8//ZPIX\nM+4mOw1b9dQrdgSIc3qQbR2QV84Jhkz6d5XNAlDy6DL+mpJ2WABxpYRiddTJigTakNAG1vVCI1QA\nL7U0UmeLCAzNdqoXyKh6jbbEVT5ZzPS47eVj6ISVbWLSqMe0KUjTm3NuIoRV1/tH4aIP/xiv1dRH\n9+r6gjYNIL1+a2XmOXi/4npbwtmxSFNfOeEo9Ctz69wm6yZxX9zKSeYb80NhH4yhCHA6M/NsRaqI\nGHcRWvjPmsDNlD7kj8Uytmpm/gTkeNb3ptvGfh9ZdiXjSIK7QgysCVqvBsEa0KgP+i2l+/CzVi1M\nF0eYgVBV3tv+W27OyUcFfR/sexSHWCxRthjJenyHivCm96MuQ6RpRO+6Bd3Ia0fnkKlAxQevZ7IV\nL1iemrZ9dMUt4r6vaDfxGY3VVBxHH58C3iQ6RsRAVjLFbmwV+/0ZcdyqJZaP4RuJPcEA19qxaN0a\nwllGWOF0z8jF4NJS+eMo5jSo+8YGrlAwk8bgtCtUjxWMIflX+8I3cRJ+wsbnbmpxdSIqY2zPMmo0\nTVdeJ0CEHtNNkFIr/xwy8NeA+77bH9s/A+RvUtVetMOK7Kl0nECCMCXdetK0xTQic46MXqZ1k1Gl\nyGd0wuS9x7PZEkDZll8Z+D0jI63F8RD4Uo/iWSW937QsKn6hyKLlAHoVe/sGsTnVB2aLzumfoMWy\nF5yq1iRVmaqmcvGjeHtmWorWFjax2cUU/7DbyAt+gxnFb/IKmQyerpXL96ldyzdJuymdb8+qTVX6\nf2xhJYVQefa+gVxQojL0jux8yiZVmkzF7IcIKFCNO2lFtMlyabVYRG51HonrUSzVsqBr9zzC/DEo\nxN0dKQbzmsLzRGeUOOpUF3B+p066QzhKlhsqSEXgSk4G4uLIAE8LtIqFhz2t/Ss9kK+O7l7Hy5Er\nasMwCjZuU30M5Qg3U8qCqa87YzdAwVbxwM3h3y2+Aw4mdrg98UzDr6PzbLkOY1FCHGwmRvOaCqyY\nJTkiK48KNaMRNKq4iF4e2oxHcfhrO3o0AuLo9x6ipqp9b7iN7yHNIho+1nBqyicgxnxxyGRYlFZD\nDUqHzKcKWto9uO2H2pvP8vbj7UIo3zHHp0CJC7/CSoNpyY8/oa8UuwKpdryO1LmVoh0OpyT0ud1X\n75+l+fWPZWwCsteTL8NSc1VjYX3NbvoECXkCB+MOJvHmnwvhU+b71NqBWF2UAvKKXa4GXpkx2Kd+\nD/YhHleJakVB2KAvv6ol0S+kBNxQ4T4yrk6M/l+Vfk0Nf33jWXH6AJmdiSujeSPSAFOqI9JaokF3\nXTrLdmz23OEm0JWncnt2l5LMA5meQfYhrv2dTrYYWXRXQmg9hOdUPi3SsrT3F3ZUlxQJA5FkbuoS\nR0OrMW7qYcmSxrHXCYrHK2Yg0Y+5vgSJS7GW2jriPfbd8UR43puFKKJVNjGF1TShfo+P6poWVE3H\nHi8NzamEx9yb6LQdI+VSMH94TjIVMy64RfIX3fCuJjWFvqsdZqMJdcNkAjTc1WBDCcrv/3QiqDqd\n4Ode5SHq+tCRUtCUFyukx1qqXkttSOJjkzGl4dal7hDYMRREf3b5Lr+pUoJvc4fOQXKAIO+o84yw\n8fsShsKJNnuhJpJKCJNgPLZPLEL9nh2F+qyEonoN3cvPZMkNrKdHLFnubKnLUxA7Klc1acAVqD5N\nk7PYsjCzfJNsRVSuDhJqOHuWRaQGcOSaVOxUG3ZzhswKYtsF/iBM3i57rvFWVCWO80AM2AD3T7J5\ndiNVCQFwNUVJnGZWHbignGdFNfKArffVDU9pbqKXU1QPJftsOCIwzjEJiShEYxD8NRTdp/1Py3Fc\nYYsaCJqon22GGVkeu63Yuf5wXt6ZXMzzU6D1aLLccUbkoURYDd8n4ld7a4QOnlakngszm0haVWSF\n9e+MCDHpg5Aba03rf6wWPKbUOHJPmzj5UuAFUtPiZhXOy9p5wYfCGWD9FOrtI2ZDZMXTtr5Gx/zR\nzUGM23qG0DiqvGTZHRgU7M4gJUgQT3aWGc07kHKv8iYgOKrv9z8VdltpS922vRF+PBbI783+WYF5\nfGNH8zeh18p/5AOnClMjldWuRy2tt0jg+KqoHexrFTAGlIHmQ0HLNpmxE/igDsYAcs4yVZAcNfKG\ni29qT2b/VxDM0/xxCEHvmZauIdwjCHMq1/L2TKOTm7zRbTdz1jJIIBTj2G043Kkl/9WBv8Qr1MN1\nmkO7J1tVQoZKiwZgnbiF1ddfA2BXxvaoSiXDyqs/SWx1W8Xq0YL3CwMXHbLFNfmK96xaJ7hIVy7h\nAAs4ZnJic/cBEZvdSj2pUZEnz7xbIhFEnrCFPJExNlXoialEllDDEAu8l/MzlDakfd2CxqLbYfv8\nIPJxHtwV/RA5PsKRRffMrBygnzYXZblv8A9KFSHifkBXwjV7GDzs/lGGFxd+wZucwLAAPoclyv4m\njGi51wf+kpZY9feV1Auuj0wmzUN1mv3klVP0FQTGUx5QPYTK39kH2SloAP9UNk0wdotY02o/zonM\nCvr622w76daEQZurrx1gHg09wDkokwPelsq3brA8dK3PXr3owxTfaLsDpb0cu+Z8WS545ra53LrZ\njWMM0QWk8VMrzHXHrssFZ1+/8YsIvXmpiEpNJr0Wk4UYiu1/HKjxMi/OQfE96JPzQnH9bJKXKX+z\nqcxAIQKaw+nAnHt7KwAfFDg+SSBXCbvZARPXzsXB6Ygp4TtUpt6ZHD9w64asSmGo3ryy4N7rrymi\nDR6mTsYiQd65NKs9n3uh5LVBenHepZSvBcCA7cpGwUtZm1Iew0GaPBxo03ThxN/LG1R+Zu6s5hxd\n9sXcrXI8yzJKbnIk7BoFanWuV/Z5pJULZv6XAj9c1uxKme9M9j5m889GmFu1z97JHPcUMo7odUkB\nrnUAlKbMtlE0ysDSzIkum9hN7Cj3DyH7dkw0We87hENufmAvzGPRhVxIiigzVfU65SxLUlRHsQgf\n9DD1/qlL4VbO5mljOecMvtixVJ5oYeXOWfb4JI9FhOUphhWlJF800H/4JPEfO1IQibrCaJLwyZHh\nOR06yZzSi1zMWmRjzXipuRKoeOmpCJgnQ2n8jq1c3907cK0JnRFYszkun0PjvysFy2A+O7mfZc+j\nCN4YhSIxAIDJIwGgLF6zglVNNr785I+YIWCpySJB2ypLs32vE8uqMqQaNJRisZO2IAWo1wSioZDc\nJRnFxNu9mmzH2wMJEE+oDJTQbIOwT/gmfQE6+kmR3jZjMYBx09hwXPH97KMR5LYxX5ipHLOc815s\n3Vynivs5XzfvxNXXzrJEZzC6YMkWubKqQWFKMw7o55dcJK+25s5MD4nE11m9wEHkcbs0L92bGLT6\nGB0zGhiFnscytBGgW/VOMsgQZ4vJLkWvllVc6j2vWq/uD8AI5ZA86xKCiMcMYWWdpGdZD+LzIRVN\nJ6vJ08IIM0var+ezW8r3AlhyGKBxpe8DUTrf7tkTWpRlMD1+fGRwBFxFWciqiD9nqGKGrSuJ7LPE\nhPP8K5R1IOkArigFro0kaIkQn1WPr9zqw/NkNcvVUyEIiYEmUC0HhFrJ3fSp7iLoq0o4pDmbdjT2\n4g/GD7piuHmaq0k/ytFvG5u0FSxvsCM2hJD+aOagWXWD7niooa+3sNiQJXMbTzaj1Ai55jhz3ftj\nK+YJpZdjXgd1+2aCLMhsfIDn/DFLBmpUvLqPJNY7F4TDgMst9P7LWASLs2xKy6atZtYFDJWakJfI\nBK2nDTozSv05nqYZC0O0c+vtppoG2e+kcDhFpkxEf5W5XrD/KtrJBsT9MVp8eayTSbCRm9zvlfwe\na9Gqt3vbgUjnusHc3e3QH6bUpVb6fBKDe2GVCpLY3r0s9gEjcYXdD5QRuuRCi29EinnebLOKYYuG\nlOmkaTfJF4CPLc1NUvH+NuH85zLa6+bYW1fO0ZqWMyNQq/htAohWnoBm7L0MAPlWnEaU8BAzRfFs\n4u7p5AwxQB8cP+r0RFYm9ykhZRyeiIB8+BGN9+nV4nL/Q6ItbBEpxdMmDeknqot+EQNNaegMx44G\nVlxQ/Y+MGncLL7HJNEsrV/l0e5hawrDFkCnpfX4vQy2tZdjk7K3tD3Q8F7OdfIqcm2MY2wTIhuM+\npKoKhISvCDyl+Hmyk+REguz+/bkNMq351iyhcjqFa78+qwxnYK3Wa5V7UlLHLqdKSq1vkNViAvXz\n5BREIO5cGkzboDEzgNHq/LIgJwYL3z8q7juqHhCwY8VPDDH9YBc1COFANOg54izuyOLs+9e4CgyV\nJ0n9Rd3+MV4J9BeaFeekLH0oIM++AGDFbJsFO0lkABn4wGadOmQRXaWBFSwr7hhD3l03CXa/SDuJ\nmGOE8dlsH5uXXAWXkjJ1O6E+feujxPvCGDSWX9+flBSL1FY8eZPC6gbtX+migw3YJKB0JM7m+o3z\nHfIAtU0M2ZB0fqS0MSCGbOoH3jt9m6QeeRZj1HYrnjkoE3hiR6t9kJbWW685Whpr2MUlYBpYy9we\nJwN3RRRGEmD2lDi9zqhf7M4P6lSL8pLLQR7gMdZsElgiY1g4tOb8L2aqW/MNzh7WTHdWl59EMBpN\nKwCEAgr6va1sudi7I0ARuduJu0vpeMaWnX61kc6MMeoQOpxL/V5vHP5ljsfsFKdr0PdK6q3cC5XP\nwVqvKkGxgzsiEjGPHrHgcYX5raTsgprhjzAFbjdUOGpB+UBIY6GcVxidvFt6bDPoHS4K5byW6tNo\n96ZHMuZti3mAvRZ/TRaUA/HjfrlqxWLJ4oEtsgtfHKItOnXNnCJ7+DXr4X8mjnAOKe1AUh0rqUFK\nMhJPC0ZufguQY1xzctP8+Dj2BVWmh+d5VO7Y6tyJ5X1BMdS/okdSbLk3EetrQNBfNkBVngWhQSAP\ndENUptOx1LTI151aEvHKmuee2c2fjdFq8EWBmVW0z3OJBBl/uD+9H5Zx9RDC1okkSk6950n5nfVg\n2Q+Zoldy9swfDwuCupUBslYjcWzXxo8Dur0ZBGh+g/u+2ViqtsBOovFEzm8EcGMVT+J4yAAgujOf\nd+Xkb+QtwHoU1YrzDMHYSvnSmog8DHKpFL+sruDonMzV+uH/nxENlFciNx963Wt1RKxSibOECmJQ\nKDgqhUYGxHSkdJD9Run9nbdKF+wEklrSmgj8whhD3BQo8WUmwsmAqqXEvChNA6q1pR9Y9pfXKL03\nPXmVkkBXvplawSoGszs0bCVfkh/UjdWdlMNnwV+Dp5Mq5eyFYF0agn4uXO6URD0Ji2R3K8L1LjRJ\nRV16cK0STNAggAfLDh7t70e40G/B3Q+hef7R/NGVAH8C7Tv+GnHQpGReogXMF0UdjTtusMdCzRNd\nRumGbVJdsCY4s1G9vBZ6trhIkwGyieFBM+H08IOG994fVo8jQIYNLdHUMAgDFGa6T4W6G4bjXpZ8\nsFQ3fyU2c7YclsK+ZaBpDWd3K6nzyYmLWDfn0UAu1sYTXs0vpXycfj61o5zX0BAll36QmsskncF3\ne7GVhmvk4va18GYc4qLPLsnLL2x6oQwl/tcVNyfCOMfAAX0ghE94SY5kr1lDDEHhGKROriVkZoHB\n5qqzqlWsZlRmHFyj7QKlS5rD3bf8D2i40etdYtylaJxJ6shlxLdUIt1AMOsRSClCTqpmguuA5TA5\ndhVjdXFe65h5xxxKP90ysGX91NPzM2dz1kEbomNsGDgGPfviMgqt46JyLF3Pw4XhxsezvGUfkOwX\nO1aqMII1z5EnaYiFcaeRGRNqwt0mMTE12Bo/PD1ZAZel/8T9T1lkR+rUdPrMznuWb2DFR5mep+er\nlpbgq4NCfZL2n++R6WrlqkKHIevsMuHjfqGazs043gJ1IDwFIxaEO3izWNRzfnDYLgM4j17fN6UT\n+VWO+f+kb6K0BlLLxcNFgVTIQxBESCXKRUMJpufiQGrwEZrBCNSdl1j2/MjeaRrCt8NptFoERf4q\nB7JYHjr+BdGEO7A7YDJQEZTs/JpQqkwexQ5Ukt7BEktwr/mHGMtqSIIxeNIWYnate3VprVr/zv4K\nqaDgDK7de9IsiCsql2NrH9KNbxN6nQ+RmvvzvqPFYZtxB0hnHbC8Tlal/R31cMG5ew1naayPhTxm\ni9EtTaCGqMH5en6PxIg5Z0dUaSPGCZeQp+RWdk7CrC/2zehWMnyFoq3IpeFztMLjLStFVCB7/49x\ndVv4v0v+wOC5rFFZ1sRc1vc/ZX3CysUMuGyS3ni2xy6xGQo/w/xaUp288FTmgQI/cuOOp9ZSIa51\nb0GdyEXvdT6EFOZTBIHU+bVrBndZD9XQClS5+HXoho+L+wVPIVN8KNmujMl4a6HdvAKYsAVKf/2O\n2YsQE9EtL+qs3rqxPavDxnQISJEwPv3fVvph2vsEU3nNJByvM+Rua/IV38FFYeoaa8jCDkVYkzRI\n72dvyQxuc5idMKDNY25KcNTypKFUbOeT01eKtpldT0Hd4UvxGOgbxXwNp9Yth+NLLSEylkVZ7lp6\nGrinW4x1pp2rxDcjW+blb8hqS8R8ScuCMT18G4VZlVcEVUA78P1jgDA3iXHuIEZBd/N78BEcJcIB\nXtDr/7zZsPGIEFtGoIgM1gqOOwiL1bxAkU2PI+A1MI2X3CA7mjMCUiJbiOzaD9n0uTb61ZeyC+cI\n4QSk59lri3qiduypevO72NcaBDWfqY6lMOGxWsM+cC+6D8uSmu+ajNBdNB151I5BUYhLXjvRglYF\nu3ZYrVVZxpMV8YhtAFs2duXogDt8fm2mei3oCZk6uootD5MWMDdwgXj63zUyengw8iQkHuSoBMHd\nI3jE+yu45gscaBmefkAHOD2lF9X30a9Nvl1D94jhwjxOcDFilnBfoNXed2gPjiRxGWN++1EfVk8a\nul68oK9/UEDQen+m9E1bxDQqx585yZWmnTnb0un9LjCrQkPkPb/OH7fJT0slJs8WKXeKmnczPFLp\na+R2LahIl/VoO7R0ARjJHaSwDfudifo2WnpM1GWQfdNQ82ipLgEZy87ybSQi4Qwhy81Cm8eggxYI\nQIg8FKj9dyXCT6E7BLPO8OaA5aIQEocoZh0hBBTCoUckGEYVIq3eg7m4TzXpBo57TXMjBbjTjp2u\n4mGD1ZRGPB9j+ONr23Xo03lMRLJxzBUXTneo4sTn1ckf73zSaDLOilG5jlJIyzHQXDZTlXhIbAfJ\nh6bBEGvBuiATdmZct1LxWHqU57uEFsnv+W6WpFG+N1AFrp2T+9BLh0gro3TK9T0LQjL3FiZYTQsc\nyzVzgYiiGB1L7g6T9e2UXqgz77xVJU73PbFsGVmxRej3rsmffHKt+m96FdScEXx5K7oCkxUF2hQ5\nm1nkRLBnqvbbYxTCOYTGVnwELjH4M/ZyBVVD932RDey5nRoyj5EwbKPLCGOoR+NEQIHm+XqSvYlz\n0EatXZLQvnwLRtG/eZCRSrmYSr2XT5AkhpwznWpZ+cMnsXaYZPQUsUsOMsGU32yJsUs1wFlgB5q6\n3OaCJobyUPNAOfUwejNx18FzYtFqotaPiYatbdg1vzTw0UVaD0L+MKFK8DICMuR2yUzGWPj2VG9L\nU6LwsV3BRUXDVjHpyGzw+fteEfmr0OfXESBo9Pn4ZOFRqCvcifiFEoV93gs/DXzBFr/7iRXlC++C\nzgb7YIdfZAC4EbJ2ZLfqVcXUq+CHHrOW4F+yuKgNwL6oMdaN5wYiS5ASb5xPsland10evWsQrOaU\niOlluna3zO1FfSrvo7z8KQHarjdFpXIe5rrn/d9spewxbhuIM0s3yJ9Du/IO2K2mchlFGHsZy978\nJXAtNFtlB4ietZc2MKOVwrVhWXLTdfxFEUI9JWiClJsmdvdqQJLG/1johgGAs7tauDkqmwTAlhz9\nAQjt9uR3voLsZIj3ghJ27FJSpWM0Y4mrkGcEJjGb3FZ7Km6CbZPA+wYbvjduwPHAiSIDt75M2/Ge\ngQ/KbhZti/+TvZCzacG2TwwKX/UCY6xqr2zHUu+gSiU0pYljbw18H7sCBJlemftKhq9GFPMZANUQ\nRo62hrkXLCAYWhCv3sHBD2ikJl2JEatYZlMI8wx1LZwP22Em2R4yGIHvuqSSn4XhxqiB6mq5Bmx1\nGATXwZRMiAAJ5tEgInj766EvQbt7AFB4sbvzhivF+if/SqfE2bcOpBNvecARXSG7KPAy8TFdaQQp\nbsnH/5lFxgQXZdQe9n8xIRG9AlABP4mr/H2Hx6ml8yJ43/y9+XXtzGLqbCH2Q0t0v/TywumIRTE3\nanmj5wxEuVL7LlNHF/VYhbNxX5GseizD9/YIb/FD7Z6Y4Wam8mR05ZPCoPqf7UXIPK5/Rr0C+mk1\nGDMUpkTMC0M7rT/RMmt7PwtGbxSLtMmlO7qy6bF1ufAh29C8VUdE/HH5Gf6Z1EUqs1IO8mdruR5e\nWl9tVTBriWfIfjrB5d4gdCrv7WgUnq0bcHjh4vN20+a7c7gYMUbGlw0zuxQzNkWDFEoZpyFXQEat\nqky3wKgVwUR0sVr7J5UgVpTcGgphM+DENAHET3HlSWyaBwOG2S56/eXlGVFBNGurO/pM9l8WqTyU\n7yaFVFTvlJyEAn2XOvQghG+2rcZ5eHTl9CjRxRKSgUXkYSahUpMkAta89tXMpesXip3SH3pPbBMR\nQzXLvBakdVqS3NXZHab8lSUKeuIMWYHRJz8Fq6qevi1GquUH6jZiCXa377cdSbzmFmi/kJoF2Pk7\nipoi19rLeLeqf08vw1a4s/P+d+0JETnpouTd+EKA+8/hutAdlB9ueZx9Bax0n7p2YlGJ1tfXP3d8\nGXWPOjLbPmbq3VEjVlbOy0I8jwOc/TvN2QThr/xBCQfSQGLN3Ug8RVj/Bttf2huHamMEcz6vtbIi\nxea2gAc+7XmHkJt3hsrJL77JtQtxhVScN/r66qeX11qoTYlHONnDI6LlGYrk0RHAgduZhFnAK/Pu\nrZ03uAE9qOJa3izbx9RGpqvuRS2y06/lH9FaCaqC9A2RJdFHw5cJAeHEd10fO8xyVkhFbIrFP23Q\nLIJjNQB7JpymuP95WefAgEPYsFFK6nXixoJiqR2124yqBMQuMeu/OlLeOv+3mpGvDcH66dJDndQS\n+VWu1wGRdAviEUIyxZNn4LL/fUvxx0/8bCKJ5sRdM6Mtz/IVtnKzgteqYTIIZ6yWFAz18+fbByjx\nLS9lDr+NkjffAaoxrKTyDxmH5Y/gsmMa9mNrHgyqrzVvALzxW1P/VtdMSxLJuozgkDbyfdYUxpQG\nqZP1U/oocxPHA7REoqYGrI92LddLQ89kxYRa0Km0yPtDhAnrjBnxRdSUvYKkfsRyyxWwAw3oDu49\nh8JVujRAU7p/DPgDtK7k/VgIlTW4C3MNZrTyHyt+T9vrxE/woXkbKmbvYb8zCd01WdWIpQ0CKD3b\nzv5OxmWAszfBJrRclK7wvb9DMg97lW7cFJs/qSreaG1/+NbjtDOgrXTdXfmqjfi2XSS+Rk7OGdoz\nmWKaXfMliaV4H3sdJjKeXCHgWtAyy+3Xgcq4D/Rx8wiytAYkez+A2RmF3SMay4ZEO0GpqmfV6JKy\nGz4jDbUmPIqTvDodix5f31b37bmk6D2J7IYRHmdRJ1D/xy3NUmgzf66LHdpy0zCFhvxKHGbdneRh\nZwe7TjsgBDeEzGCErdXgoN3IICi9M3EfTVwcpoDSjmz6lqp5RIeojZAFd76hjWep9J+h3tbiWXTM\nvyf6ytQ885mJ1EMUVPWyK7lMxiczQKGtJrJ8ms9IyulBQtvvFk1agKF33rtNd6lZPISS9fljYzni\ndqy7LEUKwKzgX0u05b/hwLt/5b5LFw/Y1sKXwO30AvE48+9YY4YfW9dNIH/mqlyRsKho15wXKJZI\nkJtRK68D2uR+/peAanaDO2ESJRxtp/lJEkCZDvJcwbcCKGyGt+c29AFWONfHjEN4O0iP3TukBoW8\nesz69niZL9hFp9aXGfUEBDQtK3pKJWK4WYCYamsD2W8nMLa7DkLRUABIJ8ZrROpX2Q3kvdSDCtV4\nKA8h0QMaA5ng1l2+2+NcBYPspOXZBOLdCGFnnYKBC4Z2DaOiAFPGteTSl1NBZcIyqI+rSCwIXR+G\nCb6tjk7qgRHL521vUJEsNcc18HoUZGK25G+gYOz4nJTMWPCzHU+8n5QgPWBNpHvQqDIVESFnsebk\n1isg8JsJXZ1y5QO36B1IL8aiVCXUxl97Q7dD01SyWkKtGBeVO+7Ij5B5FgBHkbAPcRTXlVO4VWfs\nHy2MpaqRRSpXiH9jtdwBoB6uSWCe7P8GUzYbfni9chJqYDMLiJYnbNeErt+I5UM5FfJQMvBiaaSW\nYpaAZapakraWAGOwR7wWgFhLdRaxs167FtX5XQ+/y7v20hEkW6TXtmkxw8G7i21VNWnvgd7/Ljxx\nKeLcCaH0fkZmWiujC2Ey7f2jYIvy86nQZJC/lndFegG5SuBDAAaKClYD0oM/vWxww0ygHSnF4bCB\ntdYGvdVw/6oGeIMsCZtSKxhLgg059swPTbBFWHWRP4sRzJdSUYEv0mbLrrvUFENOnkuGUabRbq0D\n2QTZ1q2GOMLvUT4mhlfn9Rn9RQktWdys2w+BjSKELUHuDN+bd8lkvj8qxa3upgUzTWnfCM4vWISH\nuKPE7hWl9XGYScZE0F18oPW9WxgHUN63bnh1Ow61ur8taq9IDo7idydgaDWVmrGH/BVqYqm5xsbI\ndMUJVYvPAonwsM32Qq/m+GWUXkpXwHtEDfngMlOA/honPpYnfy/LKXJ+T3EYLCPfLKopFJHegYbQ\nwX4KMBO/dmV2VhOs2Q582MDVXfTCzJzWgS2/4jS5NJYjhTp2tfyUyWcJV/NHOsR7/6UYshRArySd\nE7LqoRP0NfEDsSQMTOJjSrIHS7OlL+uZz6bExhCP7g0hQ7xXOvU57Gzk5N8JcSGPofjYsa5Kk2JX\ncO5/FOgzt//FdVteIGg7aVEPai8dyXMGIdvHTpVV46Ax4EHYCPWisqmqNZL4POTJK2I3FFIxlWtM\nj+lnLFQLr1SoTbUafXIPD37dJDL6JukphXYHe8ANJV/nmTEg3U496wmFKK2VvOxeZObWZ3ymZTky\nxy8JrPVARlLcjYcKt/SVoRuGKOEbuaA/MY5kJyGcf5IdBM5iULOknMyoPfQgOstsLCp14XWlOMws\nLDo01HedJPGoHjbRV0sWz1zo5U77PFhojEZmj/hnNTLS99ON0vNxyXSdk5bMhG3CTuSw79yeP42P\ntW5LnRpGNE4XeLnc2AbbpZCl3TkQXECrLi7KiIgISgcC+hYJPEVp5nOl3oQZS/GgVzien2b5/VSO\n69+/FUPJTI3ykmboFB1hb1OgCyEw3V0UdnHAvDHv6TU28/NYcB7+h/1n2Fcbj/34BQpmFQEW/RML\nENkDPbCGsvnXnHeCcV1ya8VgqZ3j2WjHr15N+5M/rpSUqFyvYEgfCBMRgLBG9V4YYK7iyFLWSfkN\nUq+dUcBSR40/DIcmpJ0LSK98VzNCEtg58XQ+7PNSZymqGcRb/UTb+I6WOhrwv9479nJFwQ7prPtb\n/QNhGb/PGFoZNjV5rcvhF/HrBGPjsD1+2rG3OT0LISoObKj5nIMzM3Csrv/HYilP/Qz8wZJDITmr\n9yfjPf+759sR4P2+o91I5ywc+5ZTpQUv3nx4dKiVGsGNxRYhV5oc30KMhY9gKy0rOkYQz36XoVvW\n//5xS+QBp/CWc3R+6fo9WK1Tzpzd8qoQ8D6eQlrEhPfN94/G2ELbp1Ba9ZwFlX62JeIXnraowcWO\nPTPVluFi4Wv9MLs4vIEoB6ARi7tVuW8jJ85hciYzj+rHOZXFHV8MhuEeDeEP/jcXFWBEK1vsgSEz\nDE9ly03WdOBp9vn4JYHnZCSjE0PbIpiOBX2spvAjOZzlsYSeKLL96jIJnlh63FHMWZ12xmwzlgT/\nEPQl2xMvthj/9zwy6EbjXrN0E27uovM9DNP7uqExbREOmd9HfILLgF6SVpljkpwbI6n0S1yckOnP\nX9zPkZEPM54+vkVa2pqAWJJgZT2f066Ivn7FeYYOgffoLzuNtC3424pZmfUvHc37gaB+2Me721zN\nrfMOQ7jdY2kOgxVlXdIu/iHBP6if0y5l4pQ7OFCAKimCMAROXByyz+SIIUL5s6VLzYSBD2gI3EO5\nrSVzndNRN5Fwhtz3NhcRkq734yNtqQqnIsWtGs75IW0HVFyyE6xiyGKA+CWpoIMzHTVWeziShxtL\nih/oK1/eUWy23EWjkljMaVMisHaxQSuhHDW/G5mAvFQ6SgKqFcyCL4G2A01PRDFloxts4iKcw0lG\nKXEuZfvS+WzIEKw901pRUzN7OSbWCwG0qEha//ZntigII3WtkS1/lY6YPM4YC21VPGywzS31pQP4\nMkBHft5sMydNgy4T2ryrhk9Jef/92B6RbggUOTOo8ln5EtzpjY9BcJwb8uDMmXkMvTkzcRPjI2XL\nrmjXevy++/96FWzcpJJq3JC0UVHpzZj/DNgvInzfBCjigfTIjz55GPDtpKhsj/dzI7pOvSr42NJH\n5vA/rdZ7ZylXaVxHP+W6zaPJqfPmY1XRsAdC2TPCrkzFvqTnDoS8ub+SAPb4T7abMJIxLzPtwP2D\nIzwSdgh3vxOrus2+TEev7P2NUjOXXxaqwH96qXXVThYMmaIYzQ+ZFNdSLSH9nY/askGofqnmi+6r\nUbZY2dZsI6naTFvpjkbw6Pprphm/EN/aQLJZHsRIkzk4vBf33ym5Qdhx1acvTg05Fz9KnSEnNPE0\nIbFqTRwBaQ6RIOqtoY0vOntXV5lUQxFEk+jJZ8l0SYr3SYcNzxx1MuecstYBNnjSFH22fV2J/rvu\nuJ3P35tWsxGiC7MJoq6q0fgQY7RPAutbwiOuhojk3uEhyiwXO4HJ+seq9Y3Cg+/YS1Bdf26TEVc5\nqSvI7FVuSHeEDNcSG4m/VAlm3Zr05mLxBhbaJjb4o/RWisFVm7oCJflbZkEF4frlzJdREllyBM+L\n0HtEkptzb8FYa14xCQ/OSAv+SQe/v/RS3ALKD2FFCWzZZpkl29yZyX8fUjxTBVQyBepgx6Fa+wMC\nLIXctJGwZnat00xppz28IdvPN+ksMxdGrKqFAbxVoAmDaKVF3q+JPCpy8YLoGEQEryaBSy8OlBBE\naYe+naNiUt7IM2N/vAF0PXcIF1Bm0bHdxh8NghZtdK6D4fV0n5Mkp0lLNi9JIaD33kjFts/zmct7\n+Y4nrqUCYKxLfoNfTNNPWWB6pJtF3DymTNKHRLLJ7kzTQKqwjPBqMDy3u9mk6MkzTPtAou29Q1/2\nfcas7bw9mN4UNjAqNQptyopMw9CdBObykvG/0fIMjFeOhg4/IfC2WRKwEP6dxMmFnlg0j41yTxl0\nw8JPh0Rn3nZB8UpbiPskP9E6wh1FwGESF+36LvGy3dTxZeJvfp90mWsI7bEomsVH/el5YRzve7kk\nUaiuGW+C+wKQIgBMPtWv/EsH2NNrNmTfx/cpCNgRFX7OCMZ/GWuQ35PxO3TmxHu9eaJeVVxq8t0M\nG5lQp6gQpV264x2vK52jtM3GDrfJyKKWhIqHs8LvZXKPxeL4J6aXHLfuXJL3XoXv5w1H8rm3BbiR\nWZPVGjJlM0QOK6mZzPLbCfCDhTZIEppqozsfJeKkRwQXfYwnnGrG6lPa5qHQhMZnRztzM2+PhuVh\nc8oa/y7oi2RnJEUJ3SR6Qhg5++UXXREUGE02UtTlBvYWxIgyWLUwF2LrAosmnA56HegLFDyrIGss\nQpiaRMtwzLeMx6Kfm5RdtEEwv2GlBhr1xUsDoulX+Od1Jc/jyM0us/LwkS4lbpwZ9WaiRWtfuXks\njoSm3pNuQY5q0JuOv4zp5YKMoDJZA+dn0lF4U3NXLa7/p+8h41XfMV4ymOjs25yMr6pA/i2uP9Bo\nq/AOriH//ZU555JKotS+CK+RXQZw90TgsmxCteIP4aPl3c+87MfX7UQqZSZyRk1WaHHht2sUOyDR\nSuVC0t8vsZ+EpI2pn411TpnuiIYJNJETgaB9lOl/1lu9etUMNwMfIQhfQcKpns3rNByw8R5wdmxn\npNDi0jzT4a20nU+g1ep4C+OneaIDrV80DU4ebY/QdX2SxT3XBTGnV8n53Tmlg/WjoxrlOuPnLGaA\nTtiCZf0t+FXe+CIEYVlgME29KMhZQH6F798bgy67Pn70DjUj4l4hPIftlgLW1LjQcTHTX4cjTHuO\nOWCbVuZXKgrYtu7/WH8MhS09444Ybzu4Avfj0kjNaAJfylCIc1SKYbs8y0S9bxBOG+ffxptKJaPS\nCuf4/pA5WDMIA2lyoWzSiof91z/HDz4EePj/HVH4ceCUw8Af1tmRJVHHnKNM1PvImHssSO9wmlz2\nBglGKrlVp62ps4KINPRJ5w46YvyCo/9D/QmF7OYM9Gr8n7/A16an1SXyTJNkW6JNvXSNCfVCdpIZ\n3CbHrDeD8LjS5O1N5xlf1KS4JmQoTK+w8ChiQmowzrz+kSeLHfIx/fK4q/jc5ojW9Zx8wFInv3qS\nYa7Wxvmsgf7RCcRn37Kz8+PCUfUG+Y9EZJ9RuS3QCM3w4ugFARJ9bLaQV4Fg6B3Qt4SWA+BEu5OP\nAxvewU8kvLeyEdDn7p/O5hxzZa5d5G0EudzYlbyCaZvgkSqg9JTbN6ay2q6tpFtxbyX0bJXTHp/e\neALOGo7zGcB0jXlGCykkVM8L+mSnXzpI07i3D8prDRy2fbmdhubEgFiBqjnn4P7F3LHFuV2mBmb5\nGpLRJgPIINGJ/LpQuqXsKv2fxgdzd3ID5EaFl+2emau8L7xMywZRUOC2yVkdo13cLFTD0f8Zrnfa\nvW6cIKt42UYhjFdqp3wxAhzz7CNDwlIN8be7n/Xv8V5bX8wpsJeToQHK9rMuviUVaVNNR44lMvMZ\nkL4iDpDcW1AAtPdPqbpbmPYXb/QUOLCbBpiumvsL1e31VPqeuNdk8gIJB28PRGLxdEukzEtkCH2O\nyz+ewR3LuQ+KrtBu8/0y4t3DqS8j0yb3T+Ms//6OhjFT/HBw63+NY1MXnP0YZjOfxWUaegHUF9j9\n9aZKAwOapPP68UvnKmTtCY5XXypq2uwB8P1LjtbDjDbEnjdRd9utabc1SbkAdnOaHA2S1QC5WcCA\nTmLXujbCSd8IVggLyZvZlRcnMWCJShiBdW+c0TyHuADPA0UfQnkOafeWvmL8a5H6Rg5wh3/Oc6Pc\n8SYZHzXavHS8Lw9INJfg+ftPNNycT+R9wtR3NoFaqlnOff38HJrrohY4jthIfmgTuR8M+7rFj34J\nRqx+L7a/qPyOzNTPmVtCxZaGo16MwEMhyWFR5SS5lc7wIuW33SavfuZqIjW2cniB5/yeKXaUKyEQ\ngfCa9AF+JXBqakUJvuRdrd0ezKdWQZ47/2E2z8CtzCQBAiT+FrP2kjuOSjQhJ2b9iLwdw+Z/CbAU\n/g1yw98Htumxbtq4/ICl90g6auYX6Ykav6RgNzVSCeU4jtbodd16P8ryCTP629QClYbUcUIoKtK6\nDX2L08X9TXDZEtloRgjX4H5TR+Y031PfBvo/+L6tkGRAwQ8Nfzdq8o0VaPaFmLpprZZtcgEfqzyP\nA7l40/3ZyQ6V0CLuTWE6rUl6ILc916OZ0FOw5YXL9czUOUi0v5u6pjG168tAjTtIvzbjXgIdVfKn\nNONjLp2cU5nswqagKTX9HYb3+6Y5O01Zt0uQQVYGznh95QcglmAtjiAqd8LbH30+/sRX9JUxbzEL\nrLxmFcqLErqdLzpjemuVUXt+iK3u8dfFVCNmVTazSd4yKkxtkPiE1HMO5AgO+6MfuJJRSRKHEzc4\nXQTEhocLaX7EQzOk1s2m83wJQvlgkmvFWM5UU/cInYY57GmZVIm8JpoOCVAKPQFORIsmiN7N7xzJ\ngmIkI9342CUfPdvhHjelUzPTHRB2XJokU1njQQY6569rJzqxW8qIt+xrU0qV51AM69AKiUC/111o\nj7ejFf8gY068jJeOKuKJIeMKkgH6ZlkmIC9TODmQ0iQIPsVudO2lokWdtFrJBsJ+/MWwL7SvgJUZ\nkNACImXLFUtQR0k+v3gAwbOWB+b/yc6scEHoeDyHn9Cpd7/tM/yd7ENL2ut3AtH2eVzMtGd+SOcf\n2yGP5h3oAhFdWJDl8tkjhxJjeLICUMSRzQhyapJeF06L8edeJVik0mqTwWhwkWfkxywAnRjVoGjp\n7xvlViqdRvLScEXhx4/1wotngjlsFgYshu9rhJ67H0gYZTvbyAAg3tfBBFZLejawWuvOhr5AgKa5\nF7soGA9rC0Snwe1vhNOtRjyzQd8AQtDGqrz7+qrz51Kbeo+7XXdpO8SzfJiEOD9wCPh5uSY1aism\nilNSrCYJNbZOHPobK4OyEGwT0qZ8XSqKmCjs9voopjq60erAc/2v09u8g5k9gbJlE8zu6dJ6UpBx\nzIE99nBf5UDIWJ80r7mXco3hB0Fhu+iUK3vh1N2WsPRmboH8Ri8AN7PA/RtVlri1fK1OfW+8mJZO\nP6LHO3mEbiarCnyIYrYaIHxZ87VcmSnOaCN+O7YKqJPRHTHLl63z6MOb/cZda1ptS+hQqEwh0nRb\ngByoEgNdfytRYnr/Z+GAv0r0yhzWY3U1yUnK9L0RH+/ZZ1q3E+1GM25FZWZMIJbTCPAyiU7nptMn\nNGaCDHYtQMTNOw6IR3XEYr0BDXo8oJ3iR6hYac3YPWL8zxYkNjTOhhSi3QYLlhANQ3nXbK1/KOFf\n1k7ODbc1MuVQ+Ex0prlOMP167zncTqYGSF+9fEd/CtW2pJ8PfmfjnT9rmiZ1cbZQ5kYPnGMHFP2X\nLxyo6+bTLRz6WccqDDeGPHTbxtWnFpbamqm9wGmdy5IzwwYvhvFZG/B2nCcpA0T4eS8rL8iPkmYC\nvlT3rNqr28xYwLeGzx7GNKXFo17uGa3unjZxjhOMUpeLvr8FHzb4FVtOmyTxtL/s4zAleeycQZoX\n0kHzfC+02wjm2QL1lYt8ACBfj+BaJCGpaHPU2dHx0epBuK1FCEr/14s4AaPdcvzhDrBR5Aen20q3\n9M2sODJ0MSkCtObK0FTiYZ9hCT5OXZyx35UIg9+qisZNQ62srp3NR8W3LFtiH5dM2I4m42ivVD2t\nkSVxcWBJCK/KAtyt19PUSNnRBI9TLJbQNrEQMx5/ZF+G9Zpd9xbcDP9EDpA+LEJfZ8GE+5UQaMMS\nzfeaUsyNeMjpe5oINV2e7FL3YKeq9GpWMRckthwTVaEi6TRFJmMf8TAwbb/fdq7IptesVtsegHA0\nCaAWxaVMM00llrbXluvR5gnjDS4Bglt7dGI0Q7/EtMJKG2qC+y0vasawjdY2IVtr5E4M0ng/y2mO\nSFkcfwfBG7/eZ/ZFY4t53Lzp5/SK/XgsaIpwJt7l8nFdDURADz5No64pRa4CcHHoYk/vEAjb24Xb\nGXbtDepzWAzgXhmqDvRqDesH0SeBKz7ZJORpEESSn9AqrjplFVrhn8/+5vEt/riNxS+64YYEKn6C\n29uzoWjg10CbTMVOIP9lyjp823rInGINAb7rw3YWVGJZtC86eV/q0d9nkApnkpJVrOp+3a+l0lsN\nrhX7JHkIrZZy0P1hqHEjsfOx3e1062qK73JGp3RX60YWF5rqpFfUutiRzIb+/k+DxygF5cI7hQxx\nI59K63WeXJ+uHFA2vBv/CZmXWmrHT6e3EfLE2LgcMwu4JBvFaYx917vZ8n5idEVsnsKpAL2CP6ft\n05I7DNqxILGJX5M6HpOquL8xZpo2nIP8VxDPnKSWGO6/DoZ9EJzWIbeG/vbyCkDeKhUNJODgV5Lu\nC+64XDnsM5e0uLO4mQ2oyG22kDyEj/lszvNPAqDUbowmFJuW7dC6WzfWTzwQ9Fp1UWze2jR7+HhC\nQTx7zhJVydupwxP7297v3kW5kYo2+HQkIC01GFV9O+iFSLH6Sj/N0aP22v4W1iKfzy0w6hefyVXx\nXan3l7xX4Vccatdkg03wonvl8yQOZy9/GWWHVheotZwm+enGfkiBGDofBs4Mh94sSCHJqGQ4KtjC\nKoC0Fhv8e3rCw2ZZukQiQEZCIxOHN1kO38GKVFZVg5SYPmvVzyvvUm20JPZMkI0TsItiGjljQEaH\nzAb5dMQbZpoDFSwelOiTeV1VvbLlXr7Qcwl9TkcudtPQOvj5kDLs0HcQ8l9ebZRsN8yrv3l6ieFc\nzzKSiXeq648bplDjYCq06Gc0FwhRAdVxIa/fKMDykRZqyTmsY/7B5E3auKFSTY/y3CvNg6puu5UD\nR31smT3TEgWsIvgr++X4TCFRMO92lTEaIVOBwpC+jeOkTeJ/V8B89Nzh08FnWo7EnmUdtwOtLNHC\nAmSSXz0ZO8VbGROBNoTyie3Dfzaq+VEXjpBybXrUW8rl9uej8aOLylqgRa257DCDkTpsEQ8mlT7I\neDswuDBlU0vIV2y+AOfij3c4tYcAOEvbAs9Oter3S4RBUnIDnTyjWnDLwjqhOS52fPWehkj7IWFO\ndtMgyUf7ARIaz+mowoFWeuQN1EnmavLS8nxhk5ii2Tz2hXma4JLfET5brWvvnZH2yOv3g5LXCJKv\ntX4/AQ3QuD9Kb3Xu1VmAfc8ZjNYJVBmFzvlGMkYJnNR4UKnNjLHWxQHr5Sn8oh/EknOIyFezvxuF\nzL/xhBHG0Z5c9H5HhBoJOh6BLEAQXbF3cGr3DZQwMlT9XawwP1emU4RVlir3LJNMBe6HEvXD4pi6\nBVy+YMtOP1ew1u/MDvJ5MrobTGwKVxFQLvYPPFPylEBG8YRgWdmaEDnzEEbIxaEdjtzavRvJlmGa\nYCEnIliyImCZWo3F6jBFz2tyJsX3fATJYEGriJkSjXfxA0thRAjsBQdJeuvefJhIC9/gx8yV3Tus\n5FM9p4/3tKj2TbGrFk593EVyN2OZNJip1c/yJBxQ1OBkvcf4UYvnWTgywe59yrpLjYCOUmvXTSXD\ngUwaakiukPuYgjayJR8cfg2Io3FdzYZm5MGNHzXzOjj0Ngbu5cKWkYz9FBBdGRBE8o5E/9o8+jKu\nVniZV5gp0rmyljOJEk78GvaYch+JZEBqlKLWaacIGOaYZkFVgHtcnQoRPxKZQix6dEtdK3jH6opU\n+pNzo+5GyyDII63oGHK7iSJbA/UitYosylortu15uY8VcKad5UJWGD4a2b2J/CA8z6iqO39smuR9\niUMluR5QfckLQmW/imAbEiV9gTtmX9/EkNiCu3X6TViTF4IqrElQXOT2PkAkbSmeZUOyxF1Zccyr\nE7d3WkYH+4U6jOGvz5byYqNpXRhpiBsZIC42nioCdN43EhpVzNn7eO3xLEzkxGiZSPQZljK8ZqbX\nSxXbUyXtkn8KrRliy5UFY2GIW+ngAu7hvBGojv9RHJACmVoED8q/mZHbjwbAWel9CimZhEPDfjeF\nBsG97zMT0ti+4aKacDcXqKnx1SN02brSsJvlZgA8vR/CRTFEA/cnXjNyb1G/NRQUz1NI3xxx07tw\nbr3z8PxnXpQbBJdEctvu9py3AxvrwRkgJIB3hQVV6rJ6YHXkvp2DSVyWonHhPRytkIGCsXFlq5YS\nBqRDjRUtBJxIpavNi17tF4bZe/maiCJOLTpncbybLkAzmsNLRY3WsZSVMTn4Zyy6FEc5eP5ONWVS\n6Cj9Pu96XC7qFfi3EbUw/ICVK/kATH4iJyiLtMsStNRO70pxGcsAvjWxlFanbW3PIxuk5UygZq0/\ni2Ndi/jIKQMoq7U8H37bwjLsKz+DEEciXnEpsvERC37/PWY7vwHHv3ayxhHrLHez9/x59kBVBYI1\nLLre0EZnYrxt6WHrtOz9fMHgRVGkxGXyJsu3lrpz4tn+oTO4wlPgEVceRZqHve6V3+Yiq5x1zbhQ\n0oFGjS0G8vvcCIk4FfoB6MKiAnyrRdg+cpzZDf6iY+yzoHwWKTF6XtZjBgTfM/S9szoJPPYo00k8\nJA7kCMQaQncpDDxyscPFf0IpjetUKPE4Eh3uBNlpCdrHOFdqsDWKt+MoJfkdgSZMhj4o1LoDiyj/\neDPBvNWUZoU4nXIlUNwx6gxgpz45m4/vjap45oZ5rwr4jRPjwXREoIgqxlOrK+bqNbBtEsxW9URY\nz+/sDs0KebQGPS/Zq8eg0qoxMyIGk5qoz6wKdElUG6HKKuUpVzE5dQW0pAH22cActHhB5kkq/gtk\nsdlaRdqYoS86oX0LylvOWgvM79M4y/Rcf830ErbtUD5LTtgce0U1fJMv/uKNe2zC2DhJ0MFUVuO8\nkMYgTjjlwJHnH6VHNMwjiaz0LfifEw2OiXXOzPiyieUrCKHwMC67/M5GUJJ2rAyEhZGIL4j/sdzy\nqylbQflN3xltbkEN0Mp6o+o20lKF33sROVhGrvpvV8XzjBZEX5Ch40yCKz0btxBs3+hEyuN7sbZn\nV3xFpMhWqMk7vPpiq6uSynRzE52SeMYtjA2SGNzLkCLT0VmbrN4yuG5AlGZoMrE9nYAq7OZ1lLLn\naE8tqAWBmBu/5sDKq8xBGOZ4XFB4NDGYtGAa5sPhnYtjtMGtu/FmpzfA69VvnPGYOBPvtKi56Kd5\nvsqigggERsXqoNJ+JhbqnNgjvKk9AueQh0Gtk/ZwyeYTk5kwnBqfdBxG8TwApZCURtrobr25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uMIA/tOTHAWWQiZhyo0ClZhhskdXUiODaCtolR9aSaklAElTpCRy5aaNEE7E1CQBDAyGLRCP+z\nRKKOUX3kfo0QMMHx1ZSbnU+5sFNjOW6H7KeNqwttbEFIxJs8NhJnQDmbGZVGNSK7TmQ2XdlPcmPJ\n91051MSVrVr+psSzSGhuptsA3xY711YJ1GaTPYEw1jMySf1+hOSjbIO1297LvBXgd308MzHty2qa\nnHg9MhAmLB9wzzGr3ZO1hKFy7rlxX+5QEP160aNWvyJmXkuchQDQBJFo6mstWwYsR4Ck/QUfmPD7\nGfWaSn6iIgR1XqICt2v/Oi2B2/uKUV+ZGwr480Yh9hqmetHnE424TIG9VlE3Y/Ji0ScBvPJkPidA\nYsVZoWikmMxQonwRoCEUMcsS1ws6hyzqiwxPzXEg20it9eNI4UEUTEKKchKu+HqJLD29MNCeGpqE\ngLQa3ctGzUy2i0hYyVwC/LhXPOJ6q7TncLHUY1HWwJFOUOWAeayd7PVZPYRNY5nfnXcZ/iXJY3oH\nLDUexq6/uc+J5vpSthCve1tDE9KkoALxRcI600S0SzLER+ulfD5LaTz+ZYostLyXMFDYa7bOgMjG\n4sbpUixiT/zTv86z35lT1td9NFqusgotfeWIm/MqpOXJWNfqOaXNSttxpotqxBmln6/z62e63Rng\nOQA/8uHe9ysvWKP6kzPEvYd3Ma0mnuRpPDXE4JVnkHY7uwIo44PEpHoTM+3yKulbunnwnMY7Usgm\nGBCaYtrrDigB2xqFlWuG9g1N1D5heo61FT5LM9lRKN0LGbxjFQF2IeQU3qAmuvicGpaltTUWUOA7\nrRkSLXxj9lHAb/FEdl7ReuYVOmPr8c5w95FJRt51DDxYBbbvNh4q6w3lGwG7PZNONbeQi4CwdvjV\nFH62Wa4bNT25787dO1n19WFiB/qvSKo4B7KdM5q7tconrlSslxzK6PFWKgBmOB4cnXCIGKBQF+sE\n7icdywf0ILWGOLqJK3WW7VYjgIwO3IDHwwC9yVXNwbSGYrQgoEHQN0RTGQU6Y7FUr+xycdauE8zA\nVEefTDt8mLC+trMR8ntQh5xOcktCFZ9Yy8q52joCBAXBdXAkcBoGrHSToFC26m6skNnhwkmnvmAn\nHwB8pfakr8uRLGxcI0ZQYgCWEVJ22Uyrxc20emMtciOdSJ3Js8hzYhrwr3LbK5IB0xBnEqrO8z9z\nAtOMoc4g7sEoIfFz1+HMalosy3Z+kYEgiLY58r6sKCuvH+KpRg9FCHxxkm2jfPZrjwcYN4PcAmFv\nm+tYZ+2Znc0hqPnOzkNV5SvFZDPZjDTnNZ6KjLcpq63tvBWJi2Hm/9eKiJnenMuOoKAAgKhTW832\nCzzq3FdB58a77u4GtTuXuAl5mtdyj7TbrSnRxJd/O171R/fuQ+tt5qsj4xOe4eX29SF/xM79jj9c\naQJ04xUJY7tkNBCci8uX7qCavPTiH4SWDQdm6jUHvvqbZGuVj+8ykeD4EfwWnKJWCEXGiVXEl4oJ\nICVQ3OHETIMYlobMopsHWClEt1P2KNJORbh0X5nYJXWmre0wwrrGMo66BFl/7a3TwGHm/Lu1bEYu\n0lcPoamRWBAi30Zh7vSvyps0phXHujA/+qLXBtLqq+6+WEpoXPxa4aK7QiaUX20MIC28g3PC8EwB\ntcbQR6jiQruE3M406DFbNi59yteZsXDkraS+AeKBmhUpDUIjhQS8U68GiWzmSgYY9Tefg6gnazsN\nTNWUKcU279BkmKsmvTuWlCdycIl6ZJZ6oPYClZotrLCqgPVSN9J7FTJojl1hVCpoPQeluTsokG1A\nMUhw89iMrg89yvbzB+aX0dhm1t2SVUX+47j6FeCucxuZYVlYwYjhPR0ww6rg+4YItepeSnyRFGi0\nXNxieCFYTBXWuCWIqFuQgPFXj5c27urFZZBTKdH7+kWk3KP6VW5pXdK4sUPGLrjZJeRiefIntfwd\naHf4RnxdN2GUl+EWGJZCKpGDCTUDdSZXxTfd2d3PlCEi147mmitftLqUB4nlGP+P/i5po2gPPg2u\n0S8S652ROauEtRr0/hNs2qNe0eB67NxpuY3hoBHy/3L4s8tCAU4j8XpGisI5bY5NoIjR9QOlwtBw\n1Ek8kyIxgkYc2Llib/+PewMYWaDz8qZt2IXaXPlSf2//r4yV5057o/WIpA1O8ImGO1XMWjpRKai3\n60pVMKy1BrenPYT5o5LWj8V3To+gZVHvoHTes598u4+LcMij6GB9V5P8YkYMmjVQhHI8sBe8bHBE\n3xpAXxkzwSqcUOBWkVTWE7m8zhcPJClK6huqWeLJ+OounVJTBzXshvKTOELwmpj/Xf/d11Qumndf\nbrGPMh+Bw1spEshhb2WMFgG293Fx7nBsKSyCPA5JEb8HlUPLlsreAL7aur2lIHVn5QM8DyHB2I+m\nHEH155gqQv0jQuC28c2EUmIJRk+ApRRSS8yrbDw/MCTgV1UO+/l5SeQa54YcsP1DHgz1T0kOqmpW\nqmlBMpuH7FpKuzdg0n5watA7ORW7rr8usiu9BhewWJkpgu/Rn0PdEPzlB2ORU5CMBC0cEpYYPOMw\ncZ9bZBweq6dwjueddS03xynggTci0PUb0GjgQGHJk7nia6ATkat5I6izkbZUU7ryl5GxTZE/wk3e\nwi7iGIsoUWCq4diG9lvSK8YkrZ8ALs2nJxU8rtD9Jy8MjfdtgKoXhJAiOsP+zVzW84EldHTiSvrP\nkEq9RifpYK0gzk8q+hRuteSUD/jmKom3/SpJfXpLFiGa8tXC6EGQFr9wp8DoVCE5oRqBNqP9Ib2e\n200XaACYVgyOYf9Abt/CuB6IVj1t+gOT4ARHJicSfqZs2CmmthfNLpATsJatF+pTUmUR+ALiCfqB\nWJAzm0bthN/LNBv2BsWKl74V2PAc4hp8vyt5O3HQGmX1jHAtsSZx8zHyLFC/D4lDA2b9IAxpKqSr\nSy5237IJlkCCztpaYESh8aYU9s7RpdO2hlMDk9A/CvgvLB0YgXsW2Xa33PQ4S0u0nEVW0yr8gdF8\nGyKBz4Ev6ZXsYVclDtSePjLWF8/8GBymW6c2J7vccioQhmxFtzZ2waXAxXw1PSW4x1FHEvEEEvjZ\nVNvA2XJ83wlYRgX35Ks5NUyUsbSznm+h2kFbx4v/MDICw8qwctc6oMlgsBwVCEh+/dM8YNrXhYxb\nZT6y0TohnHAfMZQip0hguQBZ40tplCiucDttFgVO/HFcL14dLFQ6PevuKsmEp96V7WXI8LBWB4zy\nu4vIQoHKOAWK7mUWFvXZUKMoIJy3xRS88UWhB72cv+6Buf5UkdRpImqs1VfS5ZG994B10tdXtn+B\nxW4kPlzevjuIPFhhHkJ1SHuhBHhbZ3X4cgRq12ME2x3bYSOkebIGj9MUkU6lDew39CJjzM+Cweh1\nv7qfuEYKXdb4oOxJMjlUzl46INnFYm6c4kw1EN7quFicY26inYyHI2H3olYmZapSLn6I3qscnzTr\nclbsLXnSxptTXfJz+aMyYbEOxmGdlrGstVwXUTT7ZFidNKYVPs9flDdSdnlhgSpfO0eItxX/E0qS\nMaep6aM8UT6hNgJ2J9tQIpJn4zkWCULtLaeS5tKfv63BbondfKraasK9RUDiF5T/89ZXcctaACrQ\n3SVBQKHeKDBxOWeaz/n0DArscsYao1GQQOj5iTvLtEoYI7qz07rp+nzog5tBcpMjw/hYbb7JAhXg\nQbxh1dCzPZvkvloZQnoxhPPlbRJnnt8OsoKrgPLQuHamudufdt3cVoqHjRNS9IBEQu4HvpNsQCeX\nV2SlrLtculPYoV/KD1TZ3btA8+JSpCFMPDdNjjBFHJrZDxiHLAjYVMmkpHkqW99FU3+uDBb2+l8/\nMOzUTN46/IPIa5v8rsiCj1wxXrgi+xjJ5dVwR96Jcflo3FYtSqa+hBfLE2R+nh9FRZ/HFaZFhFkV\nD0pNlL0c3m+fmI2w2gDgY6rXQ4uudvnnHxX4aTALpmZNEyN872NDDiu3MQ6bWASB5rKOXqTxu2/O\nOL09Y8f3vBjyNfKYcIsYo3JgnGrrHHYdt1TVc2TD+37vEUulp+6wVBzKOfWEJOiF/whd278uKuRb\nuaBsjPGXfbUzPROo86US1g60MpnD7eIwG2zQukz1x2F1/1+StZ76y4rJChRCy03ahoLl4qUOJ0sp\nrY3WQm8K1w70snVsAgBvyRR64+HuN1eK4q8r+v5jG87SSIcOozEqVMMSm8MB9U8Gw8bqsi1GC4hK\nkOOKsHANNO24q5GLyPfOBqw+WJmKhDBJXeomKHtBdoh1M81r4Ib0Uf+dITH9JvVdrWT5ewp/xU7a\nBVnOpxnWmQvRq+SwnxbsfNNqDJEkSlbFW+CSS9/mQl08xKX/ajdoK3td87efUtzRE3rVKLjHP+w1\noonLu8OzNRQVYId7rKkHrUNt+ubPhsfzrgOoLapjFBWCjhGRJbtkfnBr1AOWiOG4SwulgE7Pgliy\nVn5/Xd/eCs47rEHYxBrXsRzktxbKEuBB71slgBbru4iGVYM0rTl8whEyANUiFIUN4TGmqqT0E0jp\n54Fz8oONaBJskX+l+78qtufITtM76zcbsUivX7wtz+QcgbmQd1I4gQonP4JLUleLGOywGtCEM7/x\ncwUaFxf0zCVJ7ZxERcQfFH/lOgxHrfHByyMKsy42Yt3yr585a8dDDkNkAKlRA+j5OFDGIgW+IHJh\nx5QD3uSODbXw9tEzHgUreR/3eN2ONwirJpAcBCRuW0i7/DiSpBQRNQ6PvpBNGCFyz3UfT4neLZYr\nQZ2xKHfXrmYzlTjp3JimPnaVPkLuVbJcIZUK9qa+KmoYX3JM3TlMJ7Wnqd7BX/ZIzHvb7WDKT9Zn\n3tuNSES1QojsiGjNZ8/gXXHlG6uXHdOKiqQ8vaCEUEKKx6cHrvVsafytO9vyxqs6ARN4xBj2j0rO\n57A+6CX3+JDqnUFSB5Roiuf8OPAf1iuGxu31Lsjyu4SVvIf2Kq0a2x8MKxp7g2zbVmkyEdOo6w5V\nS/YOBTkyZbQKqFdXRx/cy2NTqpEUac+2hhmQRodpvN9E2NQLdUcWyrPHz2thI2cONNv5WRrBzLkA\ndb0oSrRSd/ES/2wgTuGF88E1RUf7ebWNg/JIFiscpgaMgV9SYVWxNKzLE7MBWuDy0KggalLkQd/T\nF/rGbo7JrFpwbZhVduq2m0Nf/PVdAarWLxNHEO1GwHIGXXv9/j1caTBTlmFR0tOenkhFrvd4KZ+M\n55XpPNtf8x1i1KacbHvR/sbvjNACtPdo8Ru0Q5N5foJqtzByprv+yewakXZI37ABH98Zn8YEX63C\nGHu07DlNtyCNOnibeJ3WMiSnkByFhVcjHqHYn67gQhOj+dkAu+ALQBj6zu3AAyZWqTR/0g8477fD\nITwsBr9NE/LtnuSosPrsyopoSGyDDFwZBB/6rJoNtOXldYXgeqhtgk84UFdbFIRS+hDF62I8WqFa\nc8pRNcBBT1oKFxyCDbiGD0e5cEgfgcUCWJvBTTzhbzUBzCA3LGpfuwFOiyPW9L5gZQi2J4Ba/eUu\n4GxxjAqFkcigbybWwBIob8H/A8ec4OgGKFQvsidhhP39qbgZ5Ig2zOMkoTn71T+dN/sFJDXJgiwN\nWIUv3fgGfpYxxS8rl3zzduZ0Q8DBj7dJc7mZ+/x+pwbfDrWGOLGHbBy8YF4y/jQSymz5bdfjM3wJ\n0MilAxsicrIb3gBiym2TYbCvsJqLO7crHiN4Zl+82l8ddXkGUDkGDyP+qExklaEudp6byzg+BB5w\ni7BPHbzqiiqPWrpjO7Pv2tsbVrRJL1psOdMUZFDq4m8hPPxqpdb1zt+60N+uIb33UfjVr5s/TPC3\n1Kq9TRBAoVnmh1ZkJoIwS9+tgVgubPSWLPwhAJIX/fCtXSKPNJgnjppq2bR1CsjuHoO9AFVFns1W\nZJlF4K+u3exYll062gDXFJ7jK99c0TU1IIM8Xo6v3bHMcKCd3P9OufL23s5Up4LWnd32xpeYk3Qw\n29hL8Shm9Z8gXAK+IQdEgzcB9DiSP81RN3ySOypMF+YYdHCYlh9E0YdaenQfR92aCsgVgKAX9Rhl\n6Wbyck0OY2GpgqZ8ffeBu0DYywszT+MFcdnjQ9S6UV6Ark9/07qmXo+UeXXHwud887WPgUSsbK4E\ntRzorAeLOQ8PsNVVYDw6rODbfW2TH5aZ6l6DjVCV6vSDxt/EbaDF4qaZGD9nq4nCb+K1dBLtXRjW\n0LTSZTst7CfyRsn5YSH09lwXHr+6w4ONaE1Ys3zNBkUEYIirAflszbwBMZwAXnqOgrCLGnZFf48k\n2tIjrwVyHhyy7RmwjXNfWfoQl7/lhDucFGUQI6ulfOWnOKnwxHrr8wHWLD414mdjRy6gfLbQ4kY5\nz+/X32TvjGl3h6h2VOUdtqFtva1CStxeuoGHd9aAabYsNeUPLS0WJGelJMcV3VeGC2dVwxIxCIbI\nvpAg6YTn/sR65nmodfgkyHuaZQD7mufd7s4F9FbfEVzMzZCmMOHSUAbDd4H/xpuE3WdBo1PxBC/H\nl0qN+lbzfBBTS2ViI6NHlviL0azYeikFHNllMZbCMffQ/AYDu0hZ76OokwOccGkmvhhj3kemtsSr\nz/RPDV0EAE15NDOBXw30uZ9TpVO2WGaLM9DPlpYWuc3KcGeMNPuy75xcwVnTEmmKRUrYyDhycRik\nZ0eEfVRaeqpRZbkw0SXV7hUgYJjv00nXENJX2QvIVSzKFI/9iZKsoHCCE+tRARWI0Xftd9uOJpFl\ndA6ntwysUS/4xiNPqMpuCw83BnAhBEOq0MDY+Vrrew5HniZKXdDdAliUwNZl2laq5w0IjVEz2cQa\nqxVseE7EFjQBhCbCSkGx+qHA5Fc8jJ14tzgbhvu/JMs0ypymXK8LPRq8sTjamNumaRZE75n2jdDl\nZFJo3Ojj5QBMehgrhO/Tl9rEXRE/pPEDVOHsSV8y/vrKv0cP516WnKwQGvYVePQw04k+ECtYawlW\nWYaM6KS/Bgw34HJEVxc4wDW0d04cn2Ijl1XfwId/PD5RyW47wmLZ87PwHmP7cbpCeWnkwvDbG7MY\nAxgxuMMi3GkNXr+TZP3QGoJdCqdJLyYQGuLqLPR0F+4K8nqJoVsNTQv8fsRUiAWS4MKCY7Lt0HaG\nZ5HOjanWjrShne7kbDuIznrtry2kzTrnhg+SgVEnwE6oqzaN3+eEZBr5F8a3iLlT9AQh2v6HIF4x\nGT5YxlBmAnJ9MA/lzi4E+ziAoX0VjXGbGJZ/FDCYt/goAXM/qYqhpn637q/FJs1/EfAUtvxZIzju\nVvsXIwVFjByjW5kj2ghpUex3I2VNZPcbWT5/+QUw4ZGuvahVit8gF7U/0XIryB3uyXGHUwiBu39H\n4FMPjGHDBFMukNkWIskJnD2U7zzIzPTPoYfwEHNGoMMZZdYISuOkAS9DzmmVg8TbPnwN7uXSOm1S\nEUaVrE5KWxoV8RHOgMotZf1xdasvOybQvkOd9bwmXvvzgOPjGGTaoGmeSIf0QdS81w2698wc6RLf\nWeGxhSYE3XMRyWm3dXf9CBHVEF0IAJQF0geLFpLvZ4rd2ZAOUDgA5sChfFdMsavaL4U1YNVUJTpn\ndjw1TvbOjqmrlW5aOwEolst9lwOMUVv/VFHOeuQWErrRIEARtQbXFRJZRU60XE+9WdrDqaF7KXBi\nBP1Al+GjJzfbB/LSsAvA2C/8sYZBr5XRtrKehvk7k7EXIy0b25fXasek+QSg4pO915LvL/KO70zy\nC0cXc0xrCE2YTqvVTvNaazgzNpGdAVJ41J8LgNqhEu6uTGZfEvJWgNN4YTNmOXETWC4TsJL3bLp0\nRue8aqWT+u4QiASKOw+JjXHyrDhhHuCM4xHw9py8EBoeRDewSuQ4c8uZ8oM4KoqM2P/uU6GwUpf9\nkapbAyV3VJEbUzc/MsIQBzKrvshUk/GacJbikihMXcdCJpYJWAOQDzY8esAN/XOFaj2nAf5l0+FD\nOKY7D6htR2OIaUTvTH0UXRWmpUv+0QBugRYkbqvf6/O2I0XtD19z6ejT/6YlrTSJMBEa0Fxg7W04\nsKF4ZAc7o4DAKL6ZfLm2Vb/rVlMBKPX5mqTFs/x8PQvwhM1gRBTa9nsWmhvHb9IAFSGiTDHDZ6J6\naHdjByX4WI3PjOSQtFqG5oUvooN9t1ivOnhPTrxaDNyPy2r+01PPpc5cIGz5pz0kglvx7EqC3Opl\noEyJEy5e8KieZ7O0zQ1Li8mZNJwMijsKsqWXT+EL512vLNkrQ0nJOL6/HbUJeKN2+j73yAQ0/uzK\nj9Spod4DzWi8q9ntb3Lf2zhvlYTWFDaJCai4aKu84O7RK1A4NGZYWYlWfu1tmKPebl2u5XQBOMb4\nDTdvwEKBacCwgWD5KVXvX0DzvCf6UTw6JIYIRX3Jij733M8SiAjgnEIecXxWRCDyVcRmNi0FajCR\nBmx3CGUUrngdXXWO3gyoQaVXD7Dcl8z1TslzcoNWa6pgnFBfMdFOrdOnL6zBdgqFTVMkyp8pC2og\nDe+B3t1H9GOGkE4jyH44aPkiO+kGHuxnxvxfaR8z+6AeQAp4svI21f9kCckxO144jgThd1cIY5fh\na1LdGSs7sgbZhphNGcabKGHGoQHU3fEwNwUwy6lPN4z+xOXNVHuz6SQIKFB5LqtfQYc0A/sLfu/Y\n5IixDn9Zc0OSOgwOriqKOCtnswNu8JvYkrtqM5hh1F7NEzsZj66cv+hQbA4pnUYAvk8EqV7cDC/P\ng60TKs0f5bDccPoux6WJ5voGl9PyiEwDSR2OSvmHvN3dTcSxB3m1FEdQzn/9b9mw65VHm3QIklQb\neqc+xESK+nfbDBcZclBbYTTyBU4K6xlLjIqDLdtg86/3Ug3b4aHbMX3eIGW8iiL0JBF9lCMOSb7c\nT0P28C09K1JmX0nOx3jlMuGbGyp+2ezu5fKwmrdzI5DYs8kLqU7qNAQxaRETts6uRZV5l1D7xNVO\nYbhbWGI2vNzuDrUPxEuSpTn48mBWSvWfWo6Sz51FcwAAxrDru2KdoyaF+kXcF5Hpsv86LF0A3daf\nuFudztDMp3uEBl0oqVM3bWse57ekqlQ2009hWnqpNT/ijUSJzMONumBHx58NXduBfDI93nKKq1wI\nww8NqEesuqa4fkX653m9RP281KoxVD0Hk3ehH5unkS6iMPNTn7jRRgHhG0F/kC73RNbvNX9lLgPi\nRFx7RYm4XLnGSEXhE3wS+EJXqfGmdW70Qc6BmTVQdy3Kk5l/LVrjZCw2HUtJZCtD5v+yu6VaBzPc\n7chp6HugsBuO5kuer9/Q6OoAYIFDrv7d6kP19+SBOWVBfwUfMgshQwKom1LjQfgOlqKDkAwSbvK4\nCVeH/aYDsF9gNSrQxOXLf8pFpw3ktn0ac6MnoyDTBEc77xg2sICLPH2jWpXfITVK4I/3XYxGKtHu\nxEVdOSRbGkwiSlVJ782KP8ev1dlJ8YtMXeuSzF+sxSFL9ArmhFPeWN0uJbjeR6aGhl7TAJ0p7Mzb\nwk84KQYRciw2xrczxOsSqlyFdUNFg7oN415a//YZmLXamjs+5i1G5n7hZxPV94hNjQXGBUdowfJa\nZZ32/XJ9KNhp1ibz6OGogh8cD8j39G1zR+IONU5me22Nip6HXUmFr0OUwAZrhMf4kfXxI8qhG43e\njj5c7XKLVJR1gdNMfB9Dt5RhihWxBdf/fZo97lQXBFUIIErpl/M6duG8A2Jlnsz3bRyRe3U7wJF0\n3Y0mOlVRzuhpduPHKSHKkIlCPgRnUWD01DQ8syDTRZb64tAl4i3yTgdUDWiCOzvGrghhoj2XHzjl\nePRaM/xKS0J3otSDO5Rc2HAIq+GFJhKFHN7l6wA8drOCjk4SfA0QPMY+Bq4apQzg56rKCzFeqnhQ\nheiFc3zSoCCVTHWB94OS1x+OdaMcjHkA4yhupHA1MnSd0Pdxd9uAWX15H/L/S82PbvK7UQNDdbE4\nRyNHyoQN+dWkzsKrwPqzEPY114eGi+mwOYJnpt5kRnF/0jICfu68+g68ICs7MBp3mr2G/nm5JQ47\nqkGlXiGvPIGz+FkZAOfDx7VxigEdJcDZr60s8pnW5gL05kTwiHL/gwFQT7QOYGDy/PUgRAtozEQE\nY3vyXR7rJgeEUm8nXYrLMGYl3pBfv8vTj5sVkvEGQIjQzr04eMNQB7TnC4VIu+/7VeUmNua4aSSV\n+JYnGf3mWQyPIlEomjwfJ2uDp+uRZTYSQ1ym1fkzrvH1WWtzTNLEBXwGXT7TqN5NiwMfpOIpNbhU\nVER5NKXPbT0u+GbNZ9dAeYfoQWuR18F91QOaycTMT0qt+z+D/WMnPnlqoDCt4k8xMiHVGr+RmgT1\n9jSoyrZ0lNanMt/HMdBcV0wIJO/LOBjCSBn/S9K6/NqAuopvOQlMeYxcSMcZ426kiurffrfvjk4S\n/zjR72UXdCuLl5V0CPz+XlKdQESj3cVREkpCU243Q7BmfpWxrO0F88mI3tNpDnHfpQJPqpRrh+z9\ncky8nXgkJoOF64Q4dz14zZl5Y/CNO37KFOnjsRvLoxebFmYQNQyMQDwzmR+ufzFYs3uo0f8fRWZe\nH56Z0C72xygqEq876EoTO7oeSyCfjlJYIlE84soE7GxArjxQx/oHf0OGP/hipuSJd4yTtXn61nKh\nqieraJd3VrzjzE9FiQGB7J1Kl5We6nsJlumlB80SHhBZ2RUt79lvNmjAn2re8jISFGGbTdMOD5uV\nCZGmD+kQXxh193IohbFxJE1A3J0Q3VLLiRMUUW06ubik5MjgyiypV60TVsaNSPh4vHkxjonf8hIO\nKJawX2EAwtKvLJg3lAUq9JuDC3Ce7bZzHzdslJYn+C7m8PRyKbdFKDAYVRvTMjRPera4ScGviXkr\nfMk1Xw0311GsIU7JFD+OwKoAu8bCp8gpJgHo8dgBC53YCwv5tQqC0x+dIqr5eYUOAWXwTpIskPPX\n9RfiVAQhht1SnaCPAxQb5qjlrqCQJsCqEoUOGn8ryn9svzXQSLswfsNEakpjXbRRd9EsUQ4VMtXi\nNq/vXuXgrThF8GbScWyytl8Umfo+wEJ2Ct6nKVGZaoX0ftoKZbKz3tjr0gSqy/GmdbeWfS5Vl8w3\n6ccrUNpFQgD7DUckzkBdegDEbjwmczpuNm9lkzQzGEy5bA0swXLeAm2ziJxvsjfk9elOhCU2Oeup\n/FrpBC0pcneGWrqsIMbXXCEsC8K9TYT9GN/PWa8k8W0K5U5u/aQ44N8hQ3/8sbjf32cPyCOKf52l\nppuiUNX/27mWGDY817omkXo+7KW0VLp/bJrvCjrDGbrHnuyy75moZWtW/ub9uLGkhiBLf0WmWtX7\nwFxePxWgOEmOxV0EQHgoAQXosdayDCJUytGEe1k00w6/mY1Hpx9aUtZfcFRodPxX91fUQc9Bk/my\ntMqzn9vKgbrVoyZ3XOd9Xq2CRTeBWl3zNpYaK8pAxPZ1mT1iOTg+2bL1F8FbHOOKOX8o5eME1zSk\nuEKzZQF5WLF9E9ZHlHIC9zLqiMEZdjY5KCBLX4Ve0KHvTb8jRZnzL77oKHHdUP5tFm0LSouIShBm\nA01ZGI+ktHCjduC+8WFTjapkxsrhkMxDhVqX5utX1EAZU9zX+VtqdHhjqML59CZNSOsHKU6XPYr/\nMflEe3Eo7GUZE61yRso4V0srwlXovxeEg5fwMCdhf96x6QJsHxJSEyJZZlngW01m1CeGbLe4VtjB\ntEeKA5UF0fZQSW3tqa23rwOVfe3781EK+pm/Hyr2KDRyWCE/jCAaBjNL2baJabJtguqoe6HTAn+T\n7jMhtDaD3uymKcPETwgdwQ9+7xXs/8SdapY7BfAfbimA2jdXKKWfd5qJUpu7+GOmEgCoRbN4VWHW\nzgl9ZGLfClI91wZIUWByZNlCjbP17Lc9Ocx9kppJW183WQKAlgtTYXzWsUttUFzTxNXFiIey+qKq\nUrA3mvYd0d0ih35Ah9psnG9O2Klc6PNM+M6FULdbYVz1rdu5xd5P2N3QolyWrpLToPzGEnXa7RN4\n3GotzK5V/Cx/Zk6v84gG/17XPyIicQY5Mi4FSiptggDnm3y8R4LA/auo+Y0A6vVy6RVHpeQa+/Py\nH6ikYdNeOsYE7fthbVoxupIfDZIP/lYa3uO+JFcpfpzJ0hvKZjNH6lmRD4cWFFrrIw2sOK5+jKs5\nx/E6AFoIxifjVQmoX5jwbSwqZwgF2jp1f0Hnk24ObIX7LknAdH7sncbTU+NnFr/3AX4Hc6Mu8UUq\nwClNJaRreMOS1br7w1h1A6v6jtyWvUgGyjF29xkes2B4EBH6tQ/lvwHHGVpim+ySIdG/eEiHRrz0\nPjVWddKyTaps75251wM2Uc9M0jOoC8lyhGfZjQp3Wk/X48vTo3uAr2NzLfryIkoZOBROygnmdfAQ\nniM3OdMhXx4hJkjUuO+gPjffyiecJ0CFQmLSl/Dh7rrM8ba/fDhTAggsD/IA8EBKrd6757fxT7qz\n6v3B5jJQUU2Ko84PvLlsthcHiGbOV+1zGFPhiTg+89QQJWBR3Ygiq2FTnNFZo5/U7qdK3vcCZlTK\nHeVN4nVinRnMiKbcB6u2P4UiYsBCGqSXjym0bWoF8kfaHc55dP/vzTQIduYkff5bSIfx0Ua60a+c\nqgZDM4C0If2Ezi0Wrnzw2aSpZ5JwBtFKIS4Wie1716OhmGlqfllSzeT6ZiQgA0b+HwdEde/6f9lb\nFP3ju1PvUhT+GBD+eE2fvKEL4dpG2TxCRN3bfIyUgezyHsldDRxx+mZKjs0nitI5HAnhHeRUL3SR\n2XcutgKpgga+5J+j/KrlVJDmmZyi7kDeeFIHeeEESGiz2RllUjQNypAQetSgmhHOuQe+cBftI5o5\neOLnYfpm+vZ2YzYR6dBaxWsQEtYphpPOsdJMrVR/pZzQ2VIknOSXHHSoI3Q8xWSBv7FNscADtoES\n/10kWYrRhpgcuswjTMp9f6GteBxa50UPyA0g/ps/TNRZwm8Fvk7cANRLkjyT7OUZ89g7Vaw189DO\npZrB7nNNXhfixG2fgFYnSQHK7wGHHlsU8+sRyQyZpk/Y/A7p0vcihR8p7I0fVPqZC14iNL/3ppJF\nmzFSxPmxcLX8gZY9riEC8ttOFnxZ5sNEKqr9JDsUnw1dHmp6breYXGS6U6nPQALklon5/4QRB+pU\nmmZkpHT+XWalFdIe2BStO31Tax43lP3fvHFU2b4BtN6PQmQtIu1M9CfXXheYvhrcdEI6x4+bQDWN\n4k2Ic+7CijvBj4T1tKr786Lnz8ujobXdFeTiOMULQ0KvkZYBPZx6uzfMZI+6xuqjLZ7f9FiUtNyY\ntg15wHSkBY/j9uYFp1LYUvQyVDQO3WGlfvo9AFQNxLv7dK+DCy7xkz1iMZpovc5ZoWFF4u4dYrr8\nL4QnjwY0gY72XJq/vS1Cyzr22GYI/wQGxgMJwrbS5t81ivpECooCR0qIf3lSDmourSU2M6kTgvxw\nPJcdLBpEe4aC9TjoLI492kWvi+sKrl6Y/p2d/i3YQD9P5zaQXk+ysxx+rkmF3TCkVIDg4ibTZDg0\nqS68ogILuNuenxhC2k98zkZRSQgtNhpYLao0RGAhVvcanF7B4kXTjWMZotw7euQtH+nnpv5dhwnS\nOBVuZ/5EBY08iRUEb0Xpc/5cBPdAgmkzkVc5p6/nVRBPuXGSrWnPI06GTun1lRm6S629h3fg9+Mk\n08YWUj05DXviVnI77HIpL3TeYAUExUtNccaFARx0lIjFXLZdsOK5II7Ftzaty4Bloe9gl3D/JnUh\nhSlf8nSI4pS2TF6psSeEvxg3FIdRZnc/V893TH1L+uwAnw/qPW+/GAiVFzJlmRUhtZt9zI3Lm2K4\nFaGE5XVunRIU7XCyHw00uPyU9wJDJ16vh0eHYQWn9pYXjpD4ctJ6ftdFC+NjZmT/G1PutgVarce4\nVYcJYC9eWkhIrn1RE2O9ZzYgNBiEsHt1BdNxExrO9vur24lr8xB9M56DNzNxNOndB+egmltRdcWF\nBaVCn9MBD+YOTdPGgcsZhJ6T7XwRfMYuy1gYu1AjOb70pVrM3TqhtN1UHmUoknGBguwT/l2mxRfv\nDe2nfCOpszzxkCDa19KPiuIviLate59j6i3FsZ8GiikRazYdJPaPDuNu6YDc2c2GRshEx+a+g9vs\n5sLmUhpPIIc5XFoO93qzScZ9QhWw2d11JPtwNLRc32VW7BCeibQWavWhRhrMPc+N6xtw5v5ha/W0\nmHSwQtndTOnQpK3Nw3FpdbLzVn5EnF/zRwCfVKLKWXPyTWv0B/OSTG/Ces7BY31K/YsgbqDIbdmq\n24WFUaK3mnB0/3N/2Rbe2PZu16Ui+2aAlZlvvP7YcAuSbA9nXRCbwP3zDihVE2VINCIcZOskm1uY\nGIPagER5z3Kosclt6BoSXg9Ue7RsLUySSvHtLHFoKJJhRX+sbk9TgKAJdWcOxs2PRMVZzxhU6D8l\ngUQ1PSeGDPSvir3BzyNRroKb8dyUb0BKqCjKYcbS7GGzcoDgmeIgM7Q3ogCtugMZSIoLVd11n+Ow\nkpyhgAqO1PIhRhizx1suGzUJ5IJrZxabdp/7pQ66BDXaT9LRT1uXJwqsytk1YUs9whpowmXcRgeS\n9pokSVrvI0vxAGb/u9n6ZhMLECLP9xiAGwSgIrftb6NaCmVJERqNArwu099R7pcRsZN0Uh+zgtpX\nBmqx+vTcPkRbs9swSqONbKfgZVbRjG5VwoTq3r3WWuc15LIPuTbAwqaflz13tEY8kEGSJdvSu+Tl\n5g1qxEKTKBdFgY/WNqdRUWEcaR9U8La36lJS9jJxQPBqPWfbeiRqzhjYD+U9IYGb8ynqeRiLwZBz\nAvxSgD13+2CuNd0Yzib5UDJvvm6gYVdOXVGwH7rtK1NfdAlJ9a0z+BavsLU5wNCftzhgJyM0kFxP\nEGACyDNu8DC7+I7MlZHzoRkahJ1UpbAUMyALY553Qosn/q77L4wQhwjDxzgyFLiWN6M2Yj5c+utk\nFPKatRFsv/P4cAgVwXXH0wI0x0wUASeYPVpi2FSdvtoXNI3SiG4laRU1rg8Np29H1prh5qdhwsoa\nfkzrciEa6yTzFopGuUIj8Ap1IC6SG9gAhBtztGgT4nwxeKOkmq2FjYeK07+/XIBbLsLaRhnkS1+I\nyo1bKlVKKuxoRPv35kaDfFkJdLYpcXMykjcGI4w8+i/OgvwT+Dny1kepScGVKB1BKAgRUx+GtjUN\n58Rd08wjEXJ4PseATetz9PvmdtlDa9v0k908Dfn67v6sCPtgWJz8Yrzw/DmNi7rqcNTekmq7vgSV\nnb93K9bG3mDIGDKqBaU7M6i6BBn2BAD3sQX94aS+bGvV4g9D2F5Y+/y4LFGEjNaZLZ84cfp3V4Hk\njrpEm0JnTxcPM+dz+APQJiK33awOb9e58nLN/MHD9UR+KBWvAWuaQB1x3k+Yz9WDrie71Mxe2GTK\noKZmGAL2MFjLFITsF80XCVBAXQIYTQ/6kPbp0o3sZU2bHHxZZpfJutNXaK7q10kp22rWBeeCybU6\nQH3JlLC4bPZmzbDQ9uY2Bji21cISZRZwE1hnAJUFaSlp1ese4fHDZ4+o55hCDt/AFe7dUESboKk8\ny/9YXr+9jwm4yR6lFVt24hj2QmoGfD/o5gKpPky1FJwMLU3PzO37fV3jdY7KVHPVBO99vnfQDewo\nMtD/t+6Wbngyyqk215dzD15BdNQURNF7qq4d8V5+CMpuQ87SsQpW+OCPljPaCbKNeSsauBd2pM2g\nIbVLU61s9kLfi7X2khAnp5xi2VUAwylQMSg5we/jDfEA/Y8BcCovdmhmnPrmKDwj9kBrDH79r56q\nSTyOhhFBQwbB0+SYX2aHf6r5VWctw/H70MxwoGh6DV4HZbA7HIQVIszO4bGnF+OssnWrH9Y9Fn0E\nEiwT13ysHDZhB/gqlwvo82oYGQTxPdZzjsDoC6V5kEW8cHh6rdHE8SP3TbTBnHXP0zBIWiMn8tfM\nbzebsGuKOWZiNRFX2/+69MnEa2F0XpuF/oqZ+5io8t4xm4uTO3izauJaGPvirV31foxjiWynJJB9\nLTr8tN7BqRQeHXGMJistq9BCobJkXkkuJh/wXCT3vJuyUd+ie/gchAXXDLMvmkf/dnFngX4round\nl6CAPn7iYThjYicm8+Uy92bwRz36q0h1C4fFqOYr/v2//hw5L3LdKxpVh2BUflYcX0pkkhXVYrch\nLXGvREqA+Ao+hgNMrFB5JPs9OfnjLqhMhNVd4sU++E7zpBtAFNci3aM+J1V/skjqCDL72mzsV0ad\naaYgnbgeIIf4AanLrimI5CdK0E3+pg54uvsPDKH5Jt+7n5IB4JgtRo7icDnsp9NA5vHYdFEA36Tv\npQ7x9MtHTf7aRGnGvbQ9bqJXWi+umaHt/7exR9bi6/GbpRn804ROX2tDfu8RQq1eZD0QQzLU9zBz\nY2SwVpAAW5hTYxTIXVSbRl68V/dZYBm/ojWYiT918Dg4R6FXPfoayjrtIvDMbUJ5QH8RT0frZnXu\njeN3jo60ZU2EchdfvV+XGPhXYNW68ixWlh0j/1aDLHke3J2YIU7JYUUlScx/C6edoWl3gWpnZ+gd\n8UdMAfSyE8NLt5Tqas97iGJY2ISAN32Ik4vz3U7sht851uWI8PW5YPya60oe7K6o9kH9W8u2oQ4I\ndwh/MH4bm0Hah2ctniowT7Ws2mmV6NhxnBM047lZE0hI7Fj7HnWScpzMihhL2Ml3BLsvzrjyzhUZ\nNqu9JLm/DNq1QAG3TKNTQFhHsdUgy7pVxf3U/1hmjGXQCvJTOLv9lSvdfavmtP3wkEV7ni+aRphZ\nehDVli6QrLz0aGSNDSsGz6OOM88LmMwZZ+Vog2AhLdh0fpg1Lsr1V46FPeBGYFsjsgGacjqvGWgL\np4c4eHg5kg+tknyw2IeYxz3hpTnPWnaadd/agk/BwtWRwIAK77SOHBltii/WaNkvt84ag6xXR+NU\n+zUY9Yybn08GtmJ8Ruua8YGsp2IMqLRTaJq1RQER8r8cxAIiP2xLpf42RM8WV3QFF8XWRTbtgRLf\nC79Mjp6KZr9d69uQUKqWAtJK7JPij66T8sxLAlqT7sdFaKi/lnxUdJldcALMV3vpsnS4xFUN5ZnQ\nhDiWWNwTUUcVcU7R5i9mvwbX5k6U0Lhw9v/o2M+mkIWSKSsmvzl4QJe8Av4ksG8jd/LGR5ahvl8d\nXC5bMoBGF3CScSzDkIoDI1qFJEVHl/zSCVdK4Ud3AT0eyiAcfUl5GxLmzFj9Fk+bvjlVQz6c8AxW\nSc0yP9fxJi7q0PfrBzgfpTI8g9uJ4vb3pHHU9ZGVcL0Jyrc8wpjpCPXhRa8C9A/pt7igaN9yTTt3\n6c8rmjojI152TYaZSaVhN/TeEgGnAJ7pAIb7qTpDKNCH7VuWHKLy8v88BJUXGKGI1OsdLmiwXhQu\n36OiWS3MnAcaFk2VGGEeuWwcO90cj6asHGUYgwejLmYWUgSyNU/EwDZfF/vdfya6nzMimh2JPbGr\nVjLuoINGZ78is3HSGz1ngg3Y8XFBo6IREFdgLpP6IiYrkc+wHigBY6JZbrutnrPETU76h+6Kz6oS\nV9Z3QR4EYPP2C8PPoq9x2NxLJ7AZ8w/PagMH9MLB5pZkAPgQ1YBDf8+UIVHBUDLi84kcGBap3FQQ\nR6058Ow8KQ3M+XLPituNFGkYfc/najj96Fdmpq26nUrE7oFsT6H94m7V9wiVPJcM4f+lsTSOzQbJ\nm5KdT/j/Uderj1TLTXibVPQch7j27DcZjhTqfDWpLLc6yRa8HcgwrMIUx7pizA/MPH0ytyoo6C54\nqVhnIy8oLhTG9bG6EtqeA+u8n20LZiVkDtjapypBmky9qCrvXAXDI9ammpl43TqjgEo/Ncpr2MvW\nctZ+mYv9RaUYKGK1SCEFWNl86q3dIqqBaEMfiz3a29wrHWlnp9U3Kd+7JSX9YO44BdCZhfNWutsS\nSvXy9NXDw5Azw+Mpa8A9oQO08jvkBKSvGjkFKTUo9yVuvcOHYieRtKdwK4sc4pkuuQzW7KjwOnoH\nUyDNsok9itUVl4mD/7foF44ZpSbUXknlkFvmxXgkgk7+zyaRM1fcL5jhEfJkvrniW5R0ShStROpF\nbajNnm5vJ4uvnTb3670QxEyRjJINRlMSwxSk0ka2GsW7wDLqsqA1ftm6HYDgBgq7RlAvpWmTwR3n\nO07zK4AC4UYxVunhe1YAg5Wql6MJhXZ1vi575t0xQ1i70JUv+72DpKrIAviK/eOs8x8KA3e9iKXD\n9QjBUVFx9v/ka2HoDIuVDe3AsxtpcbUP2wjL43oVhlrDm0BlxWbWfdBjcpFo4utDAF8+vE266YkW\nRgQ/QThPKODeC2i/ER10h3FjI17bDOHS2lN43g7iB1SxfbQBrnU2Gk+iPCqUlJkdVyv2eJeSRlmE\nQJsWVlHkwBbmo2E8Qid+RajCHaGT+0agCWNsjvjysjNZ8c6KD5QscBPQISDp6GmQJDQXW4TMMOxG\n1qtk6yjq8TFDbELHsv0l3/EusL87ETIVS6D9QH4Rq4LQl8G4Bd/mYBPdHGvJ0T3dGkvmqiVM+xs5\nT4ZgZeLAfJiz+uH9p2e8bh1Qp0OImsaEXUlayHbbFdI3icbK5BygCQmxM1+F9Ws8StznnCMhx/GY\n/NUvwZVyJ+Boi3tVQtqG3fPrtAk/7MOkKbNNa8D05r++znndw8J31b0VyavNsFBgZqCwtLIDyvCk\nVsk5TeyG4QSBlKZjjOa/GyUkPUVZn2JyWvSCS3pNLALl+lbKJpjXeJWbz538kMO4IPnZBJE3jrtt\nKQmIm8oeuD68es26UkOSRTtJ355FuEjRYjA6n/NGXzQg9TapGZtLDtKiJkhLxLe21qJ7YgtV9dI+\nFh7E0INmjmL2l96xjIssBMX3TkGeOmRSzblnNJjahD9NNdwbu+S/YIimQKaKlIcve2110m9aTZzO\nyyx2Bhas6zQSUiGkBSWs4Wll7vI+zfy4Wz01CBgfDjgWx1/7gsaE7szynvBXOS3ncEZpTXC9657M\nphLYlOujQ371mFdXeNzI3vj1yaqNfyzUE6dYfl+ujaBHZixxdQ8Nk7QQzUChkJ07rK/SMTeqY1v+\nLIZcUj3+VzuPOveg7wvt/W5DWg5mv4ffL1rlmzQxiIeGybqbulD9FZNE+18RTEak+alvuakFVG8C\n6/ffUFs3jzDnHtkY2HgzcMV/0f7CioAbEJ+xu3ZOAkOSITmN2t8Mnv/H/2ayKt/RuplcUGeWUNxL\n7ABdYZLMoGEX2hEIYB+SEf3WOmmuZ3a+swW9PFHSO/IgTIbGK9kTvGLh9o7iy8YRpq4xK+eVgEEc\nHpbDqSmX9BCNyGqENd3JEvsZIeSDmkZlQzs0d79F1dK97DeMWVQnUL5298SSoW90SsbBRizwIBO4\n/eL4wrLWqVe97QWI/xZ3bVffrACWiU7OuxW1ta7+PtHvnRzYtk6iQv9VQNuYA2DFXvzpOhOqebZb\nJn/cXVgFX7BgG0bVAt32xf8sRlQFjeJFGKaw298xk1LipCkiDgQCSOuGc9RHFpT8tZpy/mvlYWid\n/+DKtof/7TCLZWiMl1Y1LurP3n7jRlzxQW5P5rqg4u1EbmcyaxSy6pbGBzAckNL95CIRSo+3yEqk\nKLbgM96lsSllPW9zUJDUg74uWwuFi0sJ/ZcODlnfN6F/yaWHuTJJQNWG7PXgidWSK4bLTtPro1le\nx1aqI6fYoBoWstnqfjB+wByNnpxI4wE0Grc3lZieszKXDjkNNw8hPYmdK9oIZImhg6M3ljQDvENS\nGd9Nf66sfWKfK6A+wCmpojjypBjJs0UPwE7JmEvbwRbzpa8KSmRGLiwSlQAZSLXO++jn8D9T7hBa\n9lFE14agMHKjNbpakJMWyDdlnfBhqU0VjHAUV+eOKIj6Dugkk6PeJk33a2V7NiyxlHc93ZYqOT7t\nm92mCaGH4KUEluH1C06+Bl24zV4vYBZSGXuQuC+PjRGmz8dNd4i1SxMc3tNcxbdBnwY40o+yACR0\nWz9bMNBKUQqBFCbMneX4TYHj0qJbSUqj9sVFVaxEAD2YZQ7P/vzxZCZ5lB7Q806HDYBmNHPHj4ut\nNAYaolLnEo85x7ajBsdSRXxtM+V+OWlEqVHCM8ONUXgIO2x1sqgb6dkUaLwo5XJfkzIancnhgBum\nx2xPNLCHeD56jkZZpE1LKEYMG4I82RIshIYXtSiPXrdTQDD1QwV7spNbEoyS81QskeiG9ih7xoMY\nBJ4d8AjqD0Mfh0aPY5287apuQZgEWbQh6jIuja/LMot+1LavqRHGd/HXJPg9blPN4LvLkwYxWPN4\nfgqQRoMQ4qonLNO+Jmrrp73PhsvKvO/hc9vCH7Xm3vQ5/z0S2923aUmOVij7WNv+eRiaeGusOmV4\nHFmlPzCwNuuhJHEv/zVxchIihCooEd4VbGv1l46pdk4pwScFOxeB2rTDuK5Ho8Gd26D++njUxEbY\nNnIzpy1Ex+rxI8OKwywqFVYnHFpnpjNnb4DWtsdlCBfBqDQ2P0N+w101RGSx/CuNyTlYvRp6txMN\n/QohXP+ZGZNO6mNcC5rbIL2BI9u1QPnkZOM644ELXIaeZ4oIFJJ/92iCvc4Xl+5gi56OycEULF/z\nLcfN2Vvcr6eIiDPGKRMzVFa4L5+ulEgXA+m+bD0WqcJoGckodW2tNpUSS5jJfwYSrQZ8MMZDsYx5\nYpZX2DLdlQ3slkpLPIq86cfpYNluI4f0QWYvC1v9JnczGjsICuE2dq4Ig9Clx/TzBiy1FJ/dMbw0\n4LfY+VTzMRx4x1SHX2tnG3APMaZRQlkD7+XtFZCVEcc74Vx5YRwFYL2RpiXffUAX6KZHDdaloOGH\n2WOYFAtCejEjXIYgakVT7bJ7x9gbVwozH0xWNzABMsIv/DwMJYKtgAvTYKOPJ/PTCAZIu9/OriKp\nYXECVIPs3iDco7ANsqAqHaHJWQghgT9ud316oFtUZfmMqc3+ktkX2ZKbSCD+5goXx8UpWGSokCk8\ndP7JNrzZLR+FDfSr0LwyX7FPxnC3a58ttFBxpsiuDLK2pwCxKJZQ9qetQYjmpTBrI05WkWtK66lg\nBYyt5BqqjcFkxaWxWP+eRvYz4fu3cjJqE5qn/YOJNnSQowQHZIzGt0LmBGeHirSTkzWseQZTNKm3\nmb3uduel9VgWkN/86JOLintIToos0EQx/V1sV/zxqRpcKw2wI7bQxGngzpET78dDdrU3KUc56Wsi\nlV7PNgDKkfd8qhSkZ5SOjQQHpTXNdukQVzygW5DaiFp0YtBGaM0uyrDNoJUUYmThKEL3z3OY9zMw\nC8Sl8UkNEk84rXpx89zajMfY2f4oaocGbDu4tEkT9Rw8J7MDVr4kIeUH/JdPeRTw0JSkrtL4nZ24\nSaJq7wxkfJEEbREeNXolIh5Ezx3P9VHi3gpjMIIrXIO/lLRn5/DheKy7WQ0WniTUlDDDKmLE5HjB\nWiv7W5Cd5GcHi0XVF4UsRoYtEVUCgt47M9fBRIX8pz/R1WJvBlAoxpC1B+VB//lKAK1OiwsEVpd8\n09sF2mkVCZhcDfG1xW2gxsxu2g6qytHEoQ6PNOEOQkJeUyjRFNM2ojP6JKDqkV+sqUYW+3OAxom1\nWMmDk7ZOQ829buTYUdT1olxH1u03DfIzR+f+bWRUr5zX8ifuLNpKN4G0EShTX3xB5s2tIc6rdQVd\nleWTfpWY0/pjq3fUC2RQxvHyoDODYZAzFHuAQ8PNo2ahXtMYH2wygvAP7r5euvoa7YY821RGXTG8\ne9IET0pCaqiWonWiYNLzakJ+GNLG676c/XbVHPykBJ9c31UPYHR/ZOw8061V148eD2x6J17OjB20\n1zZaI9Hx4YWsGgE7ZvPj9aeF3flfgSbdNwa+ab7ki4ukmHgWu4IF5uqTYngVGultsUapgxpXvUGT\nXwnRSebYNF87FLcLK3eO89QVbIRfrZydULFDiO0QaVb+dWd2LBxrsA6MbZQUHBANr8HrmM6482uu\nrcGLnDcqO0UXyiLbsqixCSfDZpaSvOm2mu9Y92A37jHusF5RPljcR5Vk6FyMv4YOC8kzWCkOACVU\nya0qcWwDqGMvKQxH7fxpPYokuG6kiSIYrjRCSNW5VJLo1AQH34vNdYsc4mV6yeg/lzZ7jO4VBjyt\nLood4mnEtNmGFjaq5O6wsplvQG3ACa+3h8sy5e7GWNzKkz5pTKlCmIX7KKcx8CMjzG7DuavX+FGQ\nq5N+SaHoAY0JTa7kKd7g/QLCb9aVpwFPSdEvtCGsLQG3bjV3xZebiFnTY79bbglF4V58FzvjkVn5\n5eT2psn9UvYJSBntc2zbHAaRD4eNtrETfVfq85L/+6VDIgNESx9xIP4lX20MhXmh2Yk+/FT912Ps\nuKqCmPWR7+6uBfqKBVYuo+fjC6WyZVYh2bJlr3m8LdFFkB+3LNgvSY6Xp+LheC4oPRp38+UUVZKk\nRVcFIlf8qJrPrIO92aLxstHiYf2aPYzAQWnSL4516jW3jMujGtQPjHZj6q1vOvXm0l6muCiJaUYl\nr+IjK4P1auQ+9gnD5C0D6WoMDMOwLpofqI23ZTIoTLKiNcS5OgucJCaHo7JSrm/xyOrVL4usVBav\nXzN12EV7bnA2v7rxSqmVE4NISbZ32fR0yr9J7nQqAHxS7sq8Bnf05jXOl8MJTOm47LYaYv2UR7pR\nE++nywBwg2Q23L2G5oWffuRTCLW7mKrOwzCUolLAFX/3hA0FqZ2sS0ffYoJdhvvGiKpZk+y2w+H1\n4natcswu80qyyS2E6zW3LmNV5r7wTt4GoASvQ4c5FWWO+hyW7kqOb2KJFgx703vkilNiBIRteS/P\nGRoeV42u8Abc0Dl2OjqIaPn02jk3TUqTj25+c+H9BLTK2cOLFonuFzsTG0++qqm2aJZYogz3O1PQ\nVzM8ldye36mGOFJl5hrrl19Rp9V+skpAHizARs482yUbjZyjb3mS1jKWeFEQfMDV2Vkh2XIpf9SX\n1QaM2GawkloVqzdnwAgnyyEsV0avZmX25m/oN1c2dbbxPvy0xIO+hOL+ketsQgV0xQLNGXiKX8t0\niJiGDrmzYGEeN3in5gjOpumiRMm3ZpeX/oI98muwrSSHICAW5YN9Bikf9MOTdDx2f11xMIjfNlgb\nFH8JAgVOy0lN5rdWYxFf/LI1M4PhMeKvy/Cqoj5K6Yixjmk3el1Of0f1X7V2mLLHo6WzTtRw3l4J\ndsDAFh7Aci+JYeDwgJR0O3e6MncBGYMe6X9RihtcAdwOsQ2Eh7AzXH0pjRE33/NFDc9C4Jy5F8Ma\nPcm6EXFRgyPEcps+IuK9AR3Yt2IfVJc0DUV5ZC4wHruaBePc29NO2GD+dkYAG/vZEYqHbdMwoEZY\nZ62yUK4fS+C1krqqrC3GoIEXzqD1k1DrH2wnT20Qj7pFiamMai9frmQUF67bMLcJrVKq67Af/wyR\n7hUEh1OnTHTbCQXRqMiUVo0SKlPrgZx+uBCdoXh/p1HwI1ugcU8fqdT6Yf1Vrq048JK/iO7wNxLg\nY9z3P9FEZx9GgCaGU/WkrvmxraKnq2KsohoKWGrmwsl/sHPAM/uGAimzpXRk6F7zPFznseYBOXA9\nHPSaNDBkMw4fO2TkB4VpMZlibujpqU5a7RvdJNza1WQ+r+eGArmg5kCr7MG/tNnyQIVGKEnY+tXl\nNQXhVQ5B3AQ4Kefl1olTTIwns/l8U8lkM/yT9SKe1tQQV5bD/NNrLMkPlSLJ1pTo2IlnxvQBTvae\ntrY6bMR9/SV2QWAUR5GMI8+TQ4EDdilIpbMXyQygdgS12Evl8Qvz7utsVL7FrERUGjn9/iu2jCb8\nUbX/lF0hGXz70bZ2sP51ie58AaHKNhwKb00Wy4LdJBOnqGluTf5vs3sIw+TmraPgUOCQq1t25Nmg\nF6+5ZF+X6aijhw6dmqftBNCrnQ4a6vIgiIe4SJOr2v/i0QiqansOdvImyrgmTTEF2faoQ0y00Iam\nQg0sjp5ARPyiFwCDu2Sf4cab9MlQZYkzGOgYD7wMbe55D1jWBexaCDDzELJ90WOvmt6g+J5y4qdR\nspPFNHlLRnBdyztpcnFS2aznLQlmK+GwufrbDTLikIE82M4jV98TcbolF63SXTL7Y49Q9/MAw4/a\nUdmMQCJ9o+vlirrGmAtX4Lm+kyXa35KzoQlUmoljpeNt1FswWXmng4FwvWZWV/yQQcrn4EE+Wqb+\nl8u0jzWswzhUiJPnyO86tftbC4avqJDs0L5QH2ntNTP6xmQDaP6Z4SBEfqrMgVE/spV1ASv7IT7V\nsIak06dlTKt4Lu7Wnz7Wpkd+Px9JT6bmsZ6++eENeZdgCZviWFdMtfztUysrQ7oafMQbI/kfvTBq\n5Aj3RKnovbVsJ6qAAx4KSb0JI8MeYJwC/VqyREdmJgvEeYyzdACSaHMn8/iYayBwLpmaJ5oknc+T\n+vL0htw0bB+iHVYeCEV0PkteDt5axUkPheCJpH7KsVSCUZkQpuke0ekdlDvVcAGXtLmqE8Dzqj0z\n+oqBNrJ1kXAQ/t+iZfq7DBru+kzNf7reKRiPvz4lxYPgcQnSVo5Em414CreDt8cBSgI9CFXN1CAP\nY6rsz+KN06+O5V5LUbm8WbFBjXcv+Mb2JMEtURLOi6iZr7cC/1GF++nFBGDpN6vgIlsb22mQnmNl\nHgWCbTN4tykGW+T09x7b8vQxrxgtIVGH0tYd8cDgv5E9pTe2yMu0tCf60XVc0HxKvcc3CMQpWINg\nmzV8LKiNWT0o1vTkBybWlqo51XefJYdsCsSY7yDKSo8NiysjRYM9fz7nnfcOMWSZaKSe/WPvIPCx\ntRqn0vTdtmu1Vj7v/nEf/hEaZLLW5vRXHfEMX7wSugGP1YnYvra6yrEY4+1Q0wCh9u3t6ZLQPjcA\neCIUf5m2gJEUdMrL/OLpLU7Ed8UacznautH+XHIrW18Lv1M4c1BhXalc62n8DU3+zIrXp5zmlmIs\nivj6MNb3zZe/zx8DSCS+gu5PfJTXBNvkqLoRxUw9ofvhg3PsVK8ykJizZsnWb3r2eelEs2SEWLmw\n/zBLXvZ+HIi2ZN2X3hHKjIrBdxWPOEu8LuwZ09Yzt2AYYWrMaVaZTsNQ376xobjiequAB+zY5dEr\n8u47fi/3v8ixsdprDf0OU66xJt2wMBrGqKUjoqozv7peosWo0DQVPGBJFNp6fpRv7RUUjW0gHe35\nAJppJljpDiL8xC5u18fSKnVTbvet4pP/nO87CbtsWtIcvdEisDHqGOZWLwe5/sGg9JrlPqLH11G7\nQ6cu9MbWJq3PwBan5cVB7CUbweM1fIIY9An4eyk8jzh+UWsBXF8LdpaXquXm7vmhzjZBslhVix0x\nja5SQEgXAKWw1nBErCa9JBsORQXrDj3Coe8VP3F46EZooG7yjvYAxRVlmhJ6pN5HxfrQIeP6s+BZ\nMAAHu1fqqIBlSxxjrBNp3iTwNLwOxfU0dsoEBO3rb4PcanAa173qM6gEiT2XTqIjdqnkVDu9DF19\nuwhLc21E6h7Mj3ievFLUH5N21vgA2JEQbF5Rmd5FRMEutK1UUk8kv08fsViGE4CJtysaWI5te0zt\nmlojl/hIN+HfCjScgF2Hw5Sf7SoLZwtshyCAMwJ+0Q+JgiQ1pedpgB66JHwTWqVSGPDW0EpjsWmL\nG3QZ3Khr34Klx6BNvNHNwVF4iRPMxCv6iOfZFEk7NdMWihTXKW/kp280o+N5DQ9i4DObTYeN9zZD\nb1X2qgNiddKwaVBVM2YBdqfK1DJATqQXCvBzv34xdevOSjypfUqTT/Dv25WKsnA3n1PvUOWCxue4\nY0lmo5Af1B9chpSzrcsMmO2kIo8MUcwANOG9O0gs3nG8Ob5NznTOpjDqZISzLXxNE9D+I98n9zKW\n+vAESTYgYq0xwiG934O+JI7S4duepTJRVdUC3U4xpZJQExI0SARx+IL9PI2lFUq9dJQJvoBhsLsq\nNRdcvUruSJBEo3VvJ20NicGAF3HX437sCbWptY4YUQAdqMywbVAswe0bshGYolzD28uCtG9DJLJp\nl/mDYFisqRP9xBTCMjoY222Phv1lgZmuvztHcCPDnQjToT4qpUm17QddzeePyO1uD3K5BD1pjS6s\nzWEgAnwG09cUuTrkoAm7hcYSRHGutUDQwC/uFsmCzEJCc3UXvK7xN+zVA0tI+eFEhtex40NQUb8v\nMJOGJbYmrsoRygsuksOjx7ogwxV3ZHb92Kqx+BiZzDLqMWu+OTOw4HvnMN6CJyXhcaK72nj+ULJb\nuLKnd/XlSz2WMf6uzSHIBcnSkJThqyl3hYV0pPzZoX6mfrRdUv92RX2+xvIgjKJ1Pe/BXKRJEo1j\nObr3ar3qnpfAP0eWwDJTLaMWVNWHplOGctf1WJPElmPTSxaS18zBANh/KuQDPhCfwKMZ9/x8jpBb\nwUWnY9KmrqYOcLSChmOdXpaxiJo8VBSqS810yQ5y+TzLgHKEbXvZ7ziHGVeYxnGn7khsClILyIXU\nReg80cKpWBL/RnUdU0ZMf+p36xuAeX7hGQpIOMTTeliktDhlhsqET8GWUcFv6IB4w6hShjndqMZ9\nmpt45zlEZk22KrBdoLRuiKqXFtuEprWD0R+r7gusGe/6gZOO+4QCXPeQTnF/MK+Ff2X7A1S9SLhx\nYdmLnRYsqxjlvONX16aDL0cqjdquxtTxUmY/3EX6t/OKkqUtai0sa0T/Qvd91FUgrQkPXiVpdFmQ\n1OZWIcilBIb03y7L5zk+tgAVz29tpq7vAbXgrrYdgQ8rsZ3uf/B+ulDzeDW4TWjdGetVeDJiIXM4\nTwMQgeZL/ueQusoceF664LA8UQEMehrwVvc6e791vDhwY138Vz2XYR2WiSq/MHGQf6K6taJxKLkT\n7elLKEzO6xfTy0SWcdaZ+WfkiZ5DvxAXi6kR9kPiH3OsQ5kMkT18ZIUND44ZqBFNRzhud8aztJAK\nK4XKHCZpupYsVwwdRVxcPHzbcYSoCkOAs9HWfIFYCoDS4hkFAsa0QFsIkLcvTDki9gAN4vfaEE1J\n008D70ovFzAPYK+Wwl/OlygdI0FieUfTmI5A2gqIGSweic0DQHDtRaCLr5Z4IFVIcdFKBmyT/mwP\nok53n90L8eBuTzYZLLd7SK16sORYI5+D4bYNkj0EdRXuR5wQXUK51j6hdgD+w9xy4gwnX3/RJpmP\nHWV61E81UQm8yI4mYktXePmxdMvLWIT/CIopAe0ZCBTlpH5MXdGpFA8SMf3cqSkx//QdPv/FTiZ5\n2LVqb6MUea2/c/UqsWUUFkBQDrXcoarjVPTclWl9cfscRW1knQ9RTTD4nF5bP4xrY7kn0Pot8IyQ\nLArVls75FhntjeCqlagoRV34LuywGuWS6DxOdJZUa3j0mAm0zAX3frIGEIaHdMc+va1FSI6Qx/2t\nnVjSlb94jFNz6sb3BwMw4v+lBZtSEP43b8E6ZZpzpUIHfsX6SIT+IhZS4Rl8EWME3RfMp+unYaZi\nGQFpmRHyq7O4aJ2ZOjGhPJJFhNSoAMQudboLVvtpEtrYdAk8Im56fw5FLxFdX3OkKNY5Vux57HT/\ndNfR6ys8OC1gabxjhtM9gJC2X+O0DBFOl4IaWkztxqXJFGHHKqcqKLEQw1vZkJ2d1ThfSnMsaElW\n08j8GehdqQyeub3BMQ3nsSnnDKhuRhDAte+N1I5jF6TeXhyuoJJgrR9ITXZWzB3MvjIVTOEZ6OAs\nx40GvyxHRImrUxZKHotc6QxRdfLw8ehkx/jZGiPQKb7FVso5xjuZhBI9vFzzZCSvshK5jeiawmIZ\no5DSCM3CJ0CUOpZgoFz0Q6rHOlJ/bDEhpoiCFrUEM71f0A4f4I05IVsbmoSJEwQL/exYyGkkP0XG\n7DIdGx+Ufm9Vxawzj+Un7gj8n8PBiLpwKL9IYnBxTGEKF7KGA9+0zVnhdBfcjbJMzlUcx8svwCS/\nFyX0Lj0K/jq66tt6suwzyTa4UjteZkk/MeadPFfH0WynvhTUcuBrcDCJCuMi+lz6zZoBF30jm5sg\nDlzRe4lrpIhotCQHFdh9Aez7qNYICr0GOIObF7FcsKrYcGkjIhPfMz6eaY1dJfWOESOmmPCNP+al\n4c3sVuF3pKY4fkwCrZXEFXcz2emDp7PsTwuQo/TbF3APvtFLRpE9RewtUfrS3mNoot2hYcYEXXOg\neft9nKzHUlAjF7GgUxDvFETa3qD8l6RXfRm8xN3S+zuCpFrddpF8hBIELAobyQpozxI9v5aGLlUJ\npErtFdh7JgE7VxhF0k/jCWdgATDTWS6Br1gUTWe3oTaXY+lcSBibgeZeLdblmFNWmMfVTk7lRg9g\noF/SB7fBMICmhRLQHdHwNqmvq8808W9WgdWPsib24sF89hEOZe3pfISu6wowexd/MWXJ7RUt/LzP\ntxV3uYuLRdib7gjs1jui6xLuNjFD8AGep6EB3ewa+xOzreCuopfNOuGwzd+zfyfuiKMdnOgqRQe0\nw0Md+ylDsyups6wkZC3J4IEJnHvkXKYepfIh17U1hGePs6kL9fZmbltJrbjMibCy62JPFuIPzeQG\nfMAyEbLcwv4UStCaQ/DP004NG/za4XpDRKdvWPiwweZBu4NreDpdm+cLhZ7kggk7G6u9cP0au1kE\nsFGsz/SCiTV9NOkdPR7TEfjB8HBrUjY96W0cfnQkQBvk9waf3SHNx0rt4KNFesQyQw2YIE7H7ikh\ncQeuis51JYOlGDZVy2bSwEc6HTF3p8vQpoM+ONVIVVX0S0oPryuRKaas7ztwJ6nCm1IY3u6FqxSB\n8I7SoixlAnCE9NthfRSyzR75AVgXxW7jFMJ0thsAw9hZoI14sA5t6BIuUZVpkxIVaEqAFLvDWm9P\n0QxqapGi8ZHAqG7cl975BKmW9t/BYInk5C9kU0cNW4FtuvBCD3ZIOw/mIYnLMC0A0SxCKuCGYuvM\nH17p4jBr8eZW9q6/pQ3qiS5aD59tDmLQKUKBAkeBYzXLsEqMf04BxerFKO9EbzPRErLLvZWv8tpz\nePyBgNYAuHfMaTG6qyjHb1X0dRJAjkNxWEL9DpLNY8Pgb5BMOc+U415edKUiEqWXrv4cfcuwICFm\n5gWRoS93YWpUTmMs7Z3KDz5D1wc+EYLuuvqnHbOaNq58UiaXmmnh9uxr+EfOrxv4Wgi8MvQ7+Dkg\nKLyk8RnNluBnNWgMrNIKUsH3kkoZH8vdqXI2MQiOEtbachiD8Vs2ipooWD25K+3bHgrAA5b4VHu4\nW2YGrEBAdFCVwWmAMVQ2mgZdPeAFasQ2fP/pHv8NlvrSvmU69FUPZoIbz/a52Kw6DaZSCAGwPpHH\nE8aDB4xoePNDXZEG1kxsZ+W+cXEr3w3LSe7kCcO7vBuXvsl8yafxsbhZsLDGj2UALTIo32kyMuo2\nZPAo9Qy5idAb1QXVRRUnoM6GKxHReB0DjCATrHYdQHC/j7qviBDH67XlByKyXK8h+tN3V7la45ad\nygOTTvcZSHuCtbejEA/ixk/LI7zN4Fpp4v+DkjmoHc9ByzxmBfwGULHNAC5dyeLF/wnUPxG/OFaU\n6ERmdLqz/F/E5l+Wv75FczUHJy1ST519wSglHLINUBqUJ2SwMoe2zb/++b1GE/5Tu/83nChvu1mw\n6BSAgmBhLnDBQ3En6mtwF1TlTJKvV+7Sejq3Hcgn9wxLCZxT/OIM8Fj50Jj8wU0p21Zl/ObOkawG\ncRXR0aSxQgtybtuWvUtzseeR879OipquNIbjTTD6hGfR3Rj40lfcji5Nx3gS92UyJsq4EIYtcwsO\nPUUHw8LkyUeIV5aKdl+pEgShRfZjB0zPNeOG3qVS0R5fq+qMatyUJ1snYA9FptRz5vXMZZpcVj6E\nZ/Hxfhtvslv661E4iAClJCuKbV/uq8OdXb37JqBhwFY6Bk9TL+Z+PDPh+pDmNw2x/jXNAWS2Km1/\nAc3DtLY0GlMjJPwvkcRMamFYEBNQfs2+H4YmRzVgPZcY1gS73C7+Fs/NSWphnedRw7+XCYx2f+IM\nqBHWdxCShf55gaIz6GxQ3kUPF1XEUK+Xim6LliBGZ2DwRPiUjZyZa3fwhbLmiMiruZyy+MH73dVX\nEbzay56fqyGeVYalLgVvPOacBJrVSg6haICcxlY1JJkJ99DXmwW1IwlCE0t3+/3J1cIlFsIcMiUm\nJbLAZ60oi/1QK4e6FK9esawYVEBFOL9q0MxJBLI9e6/rHVom1vOAPuMM38MimHq1pHgsT2hPXsEn\nAATx0/DqGl44WwWgB8imt1pIRVmm11f+RN+TO/4xMUHJepFNxPsaGdZEiHkjqT1U9oMhobqD6BjP\nUHmumCOqzIXCOy2c7R3GWN01ydo4b9/skKg76bGtFwblg+PpkYvA8o98I0RJmuRdQrpA+dR/OrOr\n5TJGTxahFyJmLFY/q/PsmofvHcDrICuil+BIt/10C5ELa3dRCIOiNEP5zbg2EaHXGtEz+Ip96X0e\nJm1RlVoLCSJmTDVRkUjkW80O+WQVKFMObbJmcvgXFypNjOcnOxwWuJW2Kbp3VpSSScZCHI53OTEZ\nz6aBV7y38F67XeX6MDUNQkaQKy7V6zh6M1wk/RakbIxUCyPfrnDAN+lZVCFYl5pN3FOcKlADp8x8\nqEqjr6s/ba5KJipSpRIx8ae2/hFVFW18ORpMCZD550nqpZqz3+J+JM5aCc3xkU+f8Ll9eTQEsiBQ\nAKE0J5kPJXDjnRedH8jUgZjmdbm8TgmuzxbE7IR7lJ/dvOZPoOGi+w9u+dnVPM53h1A/Va1FiIoI\n2ZhaDQOW4gTn5/p16TxzF/UGcY076HYuM+CG9nx9YsNsg2H7aDni/4r/IKuTxPgXf9AKwIZNqww+\nknJQ2Gt73MekLhgljQnvJXeisdCmwGqosfo0ZHg2POnO7HbAD2YTnijAFs36uCWRHcv4mI39KsKI\nGhuGCb0Wj/6KP+ehEzO8rA0puOeeiUm9mmYBNbRmlO1nTtyknZ76Q/08sEgKT2WdI8pdq1vVbWQI\naxnFlE/WOH/ZY4iracV9C6NDF4edNWOlaYRgxYbj3d6QeKNQuo8ELKpuMh/2UxYHizv/8oz3rO2V\nAinhDNDGbaNrsdBG71PHTx6Nmknvl7PoPV0Nrpld/KFXKf0iDxFrtoVw185J8JAhpQmKmrvGrWsu\nnMKOyec4LCz2XHB9ByZ1ugH5cQPwuwgmB5Pf15SOT/z65k0rW/jlwM41sRjjTqMVHySPu1+fzmBv\nL8bUTLvxNPl4Wo28N/tD9nOwYzjBbQets+FCaVW487pVCBD3UAHnY/wehnDumBr/ZJKZRW4PqGwW\n1jeutEuqpzioYWszrxo3vwXqhML8HBUYvClsrLBBbGmMGKeFB8Hxm2T3V+q8q/Iy97XyXIUMvtFk\nZTTJMbfU/3ycu0c77dMib1v7PfZxvTdbLyxgsjI1cBxIuCGy1ZDeobI5tx3uD5eamHsPE4oSGpQA\nvcw/69dvjtaiiBzwa1fd85N1xDanzrG+DumgYYUJxFPBfVObAjwcG0ChBLnpR9T40i3zFPEDZR4a\nVQvPP/1Sv1mwwZgyjXF+XB+8aZDPt25zjUpB/DDXgaY8UBECPc/KIBDkidbbpEPdISPBd8Le52HK\nsJYxx4xO5DvHfmvlMeZncAfWjwgIXNy67buY7y5quEgYftDlW6hzAGDOhBmhhWI2ntX8aNkDcdPf\njoOhcpNQvWBzyRrmQUIGniyApf04phMPec3+EJDCf5Xw3oJlsNj7bQe7ot+tC6KkJSYMVgqhguqp\nM2TBiFhEq7MiAz5PMLSNuaYgjUALtkvdNPGCRilOuA5oiuYqKDrLtSh0gLgqY+6hpEVxmfZjAvN+\nBt80KZFmD08FNTDiemXhBZ5zjxnOKj+rA3xri0dcaWV+CEKc6gPaztmWaSqlKg/2B2OhwEoBVDfX\nKaCBNdpgRzvbGOa4HNJx++8odivBRDX+MA/jsK5k1f9kjbFxQFOVjadq1qQx87MuekgsHXdeCHS3\nqLDxQLyUhG7MqIBr008/L7bXdGwMYNN/GV4zhgwaR5b1/1qsRLWqpYWQ0L2wtZRLgjytQDOU/v6k\nsOgzoe0Ahy/uCb2fELwoUe2k0MjyoopZVujqCfUwptIkdSDigNv2OmMEC48LEdy35Ho3q4SkgcEE\nwiJYT7xkHLIoiTpq/4jMXVVdIwpqcZ065Xfhb5OCcYTzKfwZPuXXmr2JCUIVxtBBRz1RJ14N5fKn\n6t8qM0ltTJnQhCvXboRfpy80XTXLY9uDdymSNEglZBfxREAfa2GWMXi4g5vm9PmJs7wRc8G8oBcf\nyRIECoo8n+6wgikCZRioUu+WmxiHyMEBHKTa1jnQFjY1A44a3GkQ6IVMFMJLgfZukJtJ538vyiH0\ndZkO2hmPHeOZQJGRV3UnXw5hn6nmM94nbwMceufN9ArYPYVSavIEInRgmNW+VClM/YNT43hDCkKm\nwMcHBQJZADbmM298ZTW3r/0IbLqXMINjjG9ge7e1ONxccksxMO4RSILgJwej+7RZsCK78EUQngSc\nigPUDABlHTMWBi1Abxh0KI1klVX6DMnwVFCjADnQbnWMV2ELnoU7ENJjuQc3BJh5US8MT4yvH73h\n3r4X/Zmc5rRNzvMBUN015rB1bMDCvhxzUGAD6i2fMYrLMetlWR6vgtCUzn+yhmHdmywouz5nmfDk\nh67lqxMeUjmQudKtWcY5EafE+q3vf8bmqAeNGCtPqp+V5WhhAdXNAJG6sW+snXBHcxLLJqnVjDDa\nfHuerlMV5Oak60MHJk2uW3hDtHhb8yl5ly/7ue0+UYTe8z0aoaaxNImptQz+l9POAAm5sIm9FPyF\nEy95RQsB2JrlPgmWL1RjtvEJM/xOAZN8xC1Rqpc0MGgjevjibV/fAjTVcD8RUwQccKdUJH3XznWp\nD7H8/xEJUK8VasinN6FWEurI/h3p4uOqC9Xnmj2J58xaSqu/MOgW84WZwnVuIcGELRtGX2TtX5P7\nWBcW8HswFxniqfNjxIXa0BXzVbs1rz86JeZhkHFcfuZkj6KCOGNK/9BteDw/1mIieKssPue4QjKo\nv/dkRmfH2RU4CaKBfsPmBiA2SqcHzy20zYTJVzL0a3P29n2yO+RzXXeLE90AJW+IuTolj+QpoI6u\nWkpkT9FpnkftkQ7iFYsM2Nr6/xvVxAuvJHAvfqjCvEPJ872miaMOcHp+Hl/mcqjfEvimSJ3I6FOQ\nUyJvhrvhyK/q5ufMfEhpRUMjL6xp9en8krXd2mOONrjFWQmdeRdgdjo5E1TkhTNrVghWm6qRl2Kx\n4GmLPvBgwSACsyOWV3KDowHS4sjsJmHPPmo6/0IUZAPyhkVgEYut6jQQbb4vF4JeQTSkbKtn2OU6\n3I7PzCEOPVC7uMclv8kqHXiUWghlfqXxpGgM+FrixFP+uzzWJKKVjHkgKLyo78MpSM4ZyYxmXLtZ\nfTqA5wynL/a+/Q88sVhHo8IuK8yEYniIQLE3lgViP4DD4TIriznEvG9D7qU+7nNSOpdZHuxlhqtZ\ndlAe1PlDf09GPI7AfXibZvKujHCAHXnaVEuCq9vxlfgmClyyI/UE3KYvWBGLU0tBdxe4ho04rKZL\n8EES4CfTYMzbTzomyB1qC6F9XrPq8pBQiR7GAj/3SXG0Kl7VAKekF784JcvP5KWSuhA82zY1F9jt\n95HvJgnQnutuowBo1KY0HRetgtiy6UOwF57rrtcS835dU8/frrFBUutm6l6iNUHofmqZzgwYrTuj\nIpI0WNc5juxySFygUZDefMrQqGtzvZemTmjGCTLG96fORF6MFtfRfmsmkqDx7l6CRoMVl7GSuOwS\npNS7e2DtvX2HCpJGrwtZzQZvlUs3U8B4F40FyOHA+WfTUojuTzvr/TPMe0WdZx8UZ3RYW3Ndpgbr\nQ992G3TLx+kcT6EaBR8cyFYjIMXE1E5Y9SczCQpWthdrE6vJZ9bmHWl6gXcGO960t8a+Bbr1hTpR\n2FZhV4/mvyx2pizTEnsseqK3iUJxJizfFdeGj8HYsosKb78W/XofV7SgxbY0jWb2PyJsKlNFGThh\nBluNs8hLwpalgZeDPw38bBGCq2YX7wz1Ss1V60FKrQMBK1CDfDkqPIX4WFKwjo+bbgsJJMiVNumF\nR9XmuBhdVcldzlinF4F8tWUr6W9Q9wao8Sh7vxaAgR+7Cvvox3URq5hrBUVHknH3DQjgg9MZms4j\na9DVA08CfWXR85gHEuazxtGhmXt7kyZ55DQWhv83BS8Fs2iPeGgxAfXrA7R1O9eOQ6+9AO7juIsa\nnpT+gGw2QRlDpS5zi8/3z/Xr3tOEUfKfhJZodM4gh7sLKbp8gOmXanNHL+7jqzr0AKapuBbl/IZt\noYVGCqpwWSv2gmrErJG8cS1mz1WpsMmL0U6204gC2DBRaIG2pMIEJXVCqrNPTvhnfBz2Waeg/SAp\nkC7oIAW/dmUcoDc+ShR4+MCDUX+EfYPEdN1DAepCkQA269gzrW8a+th2Cpiy8CtD0lQv+S4ZMVNh\ndP2BZNdBJJV4SjXrKbb2q8vx1vArrYAtz+/MPkqhKI+dkeWrgV1QBTuO8Le0P5vky6OPypMetse2\nrZx1hFXRAbnZmosPh6U1hkLX5o0Am/yLV/RspONgjCrg30vnbgcoISFZLbUuNNdKCALGKcPaT0e8\n4MRH3nHZlnnev+yaXvzt/2JDgULBse4Q2WLZxFf/sTM+8dcFqATkUq5ere4+dWN2mG1K4s7znzEn\nHEem7Z7cHDArnjBEuqZW0uXPk68esptZzCQKqn0me9Vu/o+dw9mlYd54UDT93KacWNCl/YmD2rAP\nTZTKP9tCnTBf6R+XCnIpDECP56/d7Jd12yHLiF3D2xyZQ/EPeT6co75YJbSrK5VUItUUJJsJwkgY\ngVUTolrHZwg5/5Oel0Jz7GQpjuE7uux9G2wLRZAZuTFD5jDgcUVZi+ZalzNw8c3ngcPhtLa/wWwz\nDIY0wGEHNJG9hNtdTT0+fjrp8yxmWEMvA4qtIWFG14ZVxpmGzg1kcobfsdCq2GNsTrwf1b726Pa5\nJhpTbg3A2kNMDcpPKUVNWxpK37CkhiHyMpASEVFNOV5Z+3ap18afmyX0b/HZYmarVzOyM8fF7YZ7\nxcZeNYuyqXzBLGDOFbIXy01ME644K3b/mYUYyUO+ufh7FGxwZdsmHT0dnKLT0E8OAcF0cbcOtm13\neD2qd4bHhWcdzJJM6n2pFTU0iGDqPas+I5SDM2Yn5EVqYiRASc/+cToemlgJN0NySjkEi9Y2aUsa\nE2xdebSwWRNQU0s9qKC2mQB60/7mZHrTAQvqkPC2igMocT7zUVLxMXLWDqkpXEpZIr3Hxfv9p0OZ\njNhczSdHY+AyTvZgTzrS/MtnAd/IGGCT+2UviNO/g2Yo3xtFXkKGFaitgsnuGfus/n0l1dHo4wqf\nQu/DgZc6agO9JUrgsaR2g9N+aMUJ/4etvZId3bDk1RSO/OKEBffLMu+WBtq7vnwT259ZNxyfcyTx\nxf/5K/TE9pn+JYRM/J7MGd1RTw3nlANHx1EoLDPTGUSJee19Z/w5XDtkbiJ5K4AwddAFfJw2lBoS\n9WGIGY1gpBTwCeNUhi4hKPq9rHpEm9AoeK1scldIocLxkM+y4a/2HAx3d0LVaEnr5tpsCmvKeQtF\nt7wVS0sllgtDrF2pIPA81QDRfcPZaOeLm4zYhyeHFPTGJLSw792mW5nB6GR7EXkphw0BCCVuV/5n\npYu6PVc4F2BnoVZPT54H8rWxcE0HbrwTx8oqhHdaww5Y37npMjwbiCcSDdjiHiwH0ogwxGa0nuzx\ncToCT7z3qzWBXxNdqjZHd0GoZceLF1PT8+1CSV0/rjhsSrHXln+PLMmSZA62lpBq+x1FgHOdRU8m\nqOS/Juwq75psqOvcjBJaax2JuFoaL89AhFhfeBMgeb+Nyk0oMr9MZJ6pWLfQ0/lMdWzwP3cfpJKZ\nqH9t4eAmE2cAUKGmMCudbxG9umZZPZaPrP5B5yImcm/xOMv4nS3d7AVYnwVP0ja9/s4Y+irZVjnk\n/Jk1RiRTMUlhsk5vESdBw91kjdkBQT+4PMQj6Cv6ysB0V5Ub7YcLFPIfoEq23mQnZ8G1HNBEnalV\nnEkMQzdTUiaeT4Y4zBqSyuz5p5zBK7ugxDD20ng0STGdPLplNV1geLNsoqnj9lO7nqT6Sg4GTRq/\nUYQcWJWLq3eqxSsV18p7hTAmjzHCDbsxtslFXULwXZd8NP1LmhEMGKsWNB+6csDN3peCoIkJi6kZ\n9phUpbztcMhdOUmVre2jBuK+K8A9YEuaqDi6SvJsAaKaNmFrn0RxhsXpmDXobcKXmbj/6y9mbH6+\nNXBclgRznUCG492QMWlA9Kb+ZNn8FAzAxKnnXyvD9glGw+nhGNWEkjYRHQBq/RP5pMk3rlPByQ3M\nyhmfu8e74OtqY/MrCy+mPeZohQX74OQ4UjvgK24EE7et9QFiY5NkVPqieTUD8q3cXjimQ8++GbLL\nyJlyQ1Sg+VdFbTenE/W4K6P3/Om7JQW0cn7QZ+lEtPXgDGWibIwALJ8z9wYvumLEQW2SNHnvelO1\ngzPKpYARvKc5OXxSm1+QMXtSHykUpqk0gP+z0kc6ikCLHbZ5Cm3LbWCLD1vvI2qndgYv3/LoJ91V\n95iVroVZh2Ici/seNcEDtMa69UUN/FwrgU0gLY1ssJJF0mSYIb5OIt1fHGIBJtX5WdyhMjtlN8NQ\nBA4+tSFG53IrtexpsVf8K22DihyHSVkc/lR4gNVGk0b4Jz5ARipndW/2DyBAGnCsNVtz6XgxRh9N\n5pjGZB8bhVts+jBJsno4yMuhLH6IanSqlPchlefxZwdSpZ6jZwaLgSIJrC4U/RfT/aW2CGRzxj/+\nZpZFaol0+U1pAq+EXMqJgYdjhqkaaOHaPkglTL6GwjXmFXzMl+nt/DGHWugnmlQ7ShA9y1xn/AOo\nEb4PFNKnyr/MXSZktu2z90J6eYYoFNoeaKV5kkX5jcuyVFM3DkzJrPTsWRnqo6nVUgcZxe+vpaZz\nJDFp4BP2Tpw4WTWp5YU9oK/nBMJ9hrPqiDBuuTGphaaGAyyaGfyltug8RwzgGOHjl7qGVr/nWyX5\nxMNiD915ZraYz3f3F3IKJMGbBLX41Tq3UBjKoPJ6PSHcFsZBAdj3T2GYSVesAIcBEk1NdE/OiIA/\nqCq4YgUOnZRrXjqQ584rgDgmclc2Te5KxxFw5UlCz+/GhKK5n0d3ZRWvtTBFiSjTa7xzljKi9z78\n6M/DtLmy3jJaN7CpaEamdm15CAKlRAMyf1sff1116mPPin8/IfuYDYtPgesHHgTpI5NPPacTYTDT\nr06pOZKOCCMzDOu/T97fl4w7G/7s9HCpNV1V5CM9bhtGAmIj+VxVNG/S+7SHZQlPK6lh5AzOO+h0\nwCCl4JODMMlqrAdc8E+T/A8jdAlHAZC9AU4uLWtQMW/Wg0Od5hjLQDDNb4Pn9BzbrL8+R8CZ19E1\nDzRoMQqRohIXHzoxopATjX2oVVam2O2SJ7H+8TDxGS3OOshTUp/U7I7x/EJGy37f2k8D18MgHNoa\nElC7M7ukDKcZXbMAjdlqL5oq2+uT+Tq2mNaiYUyatLe4XErqc8/zk0LhdZbyUz+jS3rDS7bzqU91\nludtj+zgTDE73134Ed0joeZk66BHzEi6Kq8LQp3N/pQ72sOnSFkslLkU0M8cIviPH9NzKs8ku0Gu\nZAqsNbbu3C9mUm/5UJ9T/zQHvQJW+0EQNxeI9k/pZmx0aYCxE2cuxCTv3pNOrO6ukXXnGy0QKTnC\ndxbDiCM2DesZm9RpfzP25QGsJGd5s/d/9WkFLYiuBp0GhBQ6S0t8KpQtwdyyM6VFG1hrdFDP/gf9\nzPm54w6X2VGdy/S4mNIqrSh64gd2BIZC0tmowcp4+b90jm/AoD1tqdDc9mdremJmn8OCoQaAmGL5\nh9VWv5ZALG4NGrpNLY2Xr0xH2z7qr6/SMWu0/EucFBfOJPNdAQ1L9EYBEDu86NTTVoGRadhQxpdX\nXcbZQuciACJkweBQi2b6r8yAhHktyUX3jVbakQ3HcsygWyYHrV/LG5gt83MjxX/yHkd31chBJ/sP\nXExG6YOi3RGyT0li22U/9VWPVdFLLBI44a7JJleeniJs1U40CxX/oGtRxCtPoqQkPeWBhFJgVeRk\nWFP+JXzNqc9RrAppOyeyEIEiDpwE4fVF5iA9PkfT/sZcjm6rLizeD7pAAUc+ADs/QlwILsR+7pay\nM7VkteUqf4VJiE/s2rxJ3fi6WMlifPmIq/o8JS+r0RVQZ2IOuH03OCqlctAmijqjIa97kBr52DF9\nev+tZI96WxtuPqS/ao1pBBKbJhK1Vv4vn/521V7ulMq9P6J0fgyRW8GqzwB4KnOMHf6Y2KfqdoeG\nMNFhU/Kx5KpbigohRldm9ja8x0O42d246BPCh2Vx3nOr/dMf4KhfBTT9srRcbKxKZD4VAvXWMAhW\nrjgCPAo7dW0YibotzDv1ieNNTJOVWLcG/FJpiMZeWbMEH7OHnQkzaFhnLIa+F5vig+0tkCSk2Pyl\nIryMEln8w5Jc3wxxhn3iywHpVHGF7OUnFqqp5UN+3vN/E79N4BSSaKvpOY8ESNfYMRgmAHbzuygH\nrtuiro92xlXncZ5SDgpdVAfwHPISvMyR8hrCRhxtmolCiFYZOC8/1Sxfd+jjwbVFEWzOwLdnt6Jp\nWMyE01e+9dZf8OUmt/YrHNhwxkWlhu6J9bBFEqG/cR+RnKA464/TGgkhzXJb0BRcGfR8MkRDGfAT\nKrkPaOvoQzcwvxqPYqeC13LaQHfEMzKC8CBt9ne5Amx7mGufuXjG0c2DtabwvMhSAfdShV3VFOqn\nC0X+eOP61A6eo4xTgFA+rp9AQvuVOXHuLjTZ1mgzmFwTH1dFzdWb3hIOkSWaNuESCtG6BMY4Per9\nHXHYHZ7K0AprGRojJtaHfL88ieA3fNgbX69MPwnjIYBDVKRsy9QDPaJ8mL8usV66Z91iNjutqxE1\nkM2Q3Ux+uNvTBM9HJozBpPDXVCOrdn7XzphmHAIAizR2nYD1o+RyVeu06ZtzBbSbXA5kFdXwChld\n6MZgCZ/9TDGi4J0L8JBPuXPbV1EywC7cVy62YUYphEIuv9VY5QVobOU6h5RISZHghvu9HXWJHmxd\noR8Kup7jOd9pS/bRC1Cr/geWpTzL1yT3Rz7IGSP0TKQ1qeAn6y14WIab4hh4mTjhPyrNEoHhXYJj\nzo3yvrh5w+PhqXimWgEg/Xgnn62suonmaVIsFU6sJNxQFXNMm5c4UfWt+bAyTSD6J4pF771Mkdln\nAY47QM6j0SvNguuF9eGRmisK5XLk01tzUyGo6B25lj5dz034IIrguEeB7FT0DNcN2gdLKkTSN9j8\nb3Ic7ibJ0CyAGvrX7sKNP/T9sdNl2iIQqMyUwBaTvLhXhfsSiGr8mhJsyyAa9D5jEloNw17VnwOw\nV8fYYLvuXF4Wc/jsTr7iwnB++cK5U+wtW9Nzi2su0GQeS08wEEJfmBJ7nACOU+nJ8LsjsflCxcxF\nPAO/edKCOaPlzz+Ej+rCOyI3Yzb+ROlrPChtPumt4QcGSJj+ELk1EAj92S4aNsyZ3dnFAHc+CidG\nL4cFW4bXtgwyZN6F38qMqb6UPEb89UKTI8VWALzXze1CyS+pmYOkdIn4BLQpGCe7loNltcRFcy/9\nZku2RFMJf/hjO9CsNuAueY2d4j0ywRAZvR5X96JbITk0Pd+WFXpdriir8CiSEnVSnF9bysY2gibE\nZO1eT6pHQAPVSIPatOYjzxKGpyrs1rDK+vWVIDm7r4Gfel4mVF6mLBZlxMP3Pf/fWZbj0rvGTVAZ\nB+mRmX1JPNL5wj0ZI66SnM9mcgnpeVtP9o9NEVxUOk2kAUMTWpmyJKA+NA9fikXzqEXORw7OQk1g\nN0U1uaaM+s4ZEAlWOPaHSLJXNnUGRG0obwP2BVzJKSLtTzpFoPJEDCt2jg2JeqVxf5TCULnDeV6o\np2Hu2miUd+8Xd2s9EfJxK9DUrIJRylY/YQxUuHrPJILBx2700Gq+PyOa+9d20+2w1nGWY8UJcL9y\n+KUmP++qdSAQczHtC1uXihX4GbaOkT8ZSiC2KYxPLpEvJ2Ufp16g7eu/2POSmSuFqBjTPpR6jaV8\nbFUPCXHyM8Tt9CXxGeXaLobYyElgtkPeV1dJZbii7NjBrC1WDMpdiy5CQUKHbw02uWOwXXQiWyle\niuI3e3nXGt2TQGN6wgvRuNTYWGQ9YV/I9NBMaXaZkjAp2JY0NF0CpDB7+gYnA+TyBVMH6KeI4+bO\nMwHzvI85aM37iuDsV9xTRp26XK8GQsZ05vZumiNs2ttC1xqG2NqGqydEEKuam8xFgaxHVUUrghfK\n3b2h5knpAipQxLEirBrMe32uZlK/+9YCMJvSDk+KWryeiM1dDcJpVAgxN3dtkNm5GGFUcq2fkGmp\nV0Ffkp5gT8B9cFAs1rFrGO6FrkWVXVtrmBh4pFzZPOsLLPbBhypAGA8w3o4R+9MvdcFOTmlte6x5\nxlwkh4hfRLmQytRlxRV5At4L5yJc8U0XvBoc2dm0fTj7jLhYOUIKSRUpquZbEX1nOXwk5A8pThvo\nidqE+ffkgHYA9lEjJC9NFscHlqgSViLhAEiNHTEQ3SgYT+kb8UhsEyRnubNiI0R+NJzQJYY1LSix\nOCtqQZWfMuCLVgIvymfsr5m6/rL9qPn3dvFLscCPkRew6WJLdBRJ5KQbX+FjZpc9VogZDnFo/pqm\nFN7Io6D1Iro9uFQj2+W86NcsT4nrrY7vsxGGktpwVxBNYRUIFsqaiNDyavt8AtaqHHn9DL4FizZS\nZIXZ9hiaEDw0N6dFI9Ln8nsxcIHDmaHxq9b6esF3OTqoKFBasekvDhIvd/oi803OaBPi72NkR0Eo\nhwvnfaHvuUWY/AODB+am5nLDiyFdTM06PeWhXezvFDUPcIHCqPKMnbozNv3b3QDi3NNcKczsVMvs\nI3TwXIpTz5lKiJRb1OjoeXJxql0vvybDfJYv2Wx629LiErWwTj1WfYquJN/YupGeKDwZu/4HqAC8\nIyVM1TgLBopG5p4pKrHNxVi14XT/O7AjY+UKFjOA39ahRHfxc7vwZYcPMgOFUUD+CYof7YVbkpU+\npNijpT3QsaiUiDXICgWkTA7ZBHfloPHzru9W1lfYrhnpUgslXdWrK2vqG0VlZv1jXa9feCfW5iRO\naz07crc7EoxYLWMACioS5SsoZkqJ8b6qZ9IXYxBSax+bZSOwz+mf+gPGLvYPiOovkqc4upmPXLt5\nwv/yY8JdhHfvh4ccIpwt55drfDLHFjkLcD8Nh8Kq7XIwaFd0kJ1NroyYMdULs5BDs9k26qxz76yp\ncs/bVze/YRX9tCcpL8q63ckrCW47oU5X/d1OESi7qRi6TvbCLzs7H3C/tTqePxABg2/2TQZrf8b8\n6ZZB3FWNz1VD5eUbOCHWCIfynOmDTV+wPudt1xFb2/ZBqZq1lguil3Tvs7QsdcL9tKmUMTIzxLcm\nKs6rJR99TL/DdhZ9PGxppcT/LYNF41/KWrYyI59zu3IzwKfYx1KBIuylt436AgdnI/nY2R3PjyuU\nr1E1hIPAQSQTWUdycoHg4C4T5XvUrnAFNHZRa84JUK2SlQsxs5eGDwvfqrR/BxhiY5opt5QwMJRY\nMin5gEDo9TBe5Q1SSXlT4n33LzZCysn6UGbavkrwaFqO4lNqkhSCLmz/N0Lj0sN7HahHjAShsCf5\nWDyKGxj8+ga8N+gNO9Y1XsQno4kQsqn3SpVy4J/lQ3baQ7zjfkr3XuhvC4KVZBY+29/JXkdd2XL/\nYmf+q+Xwk3wGXe3R7d6PnSH/OTP9OuYNvzhihP6CaxFH40LY9pkbMgC8zPNATHVb2TtM7nuxcY5P\nx3/1GXwpUKxOYTS1QQeDlfaqXw1LY1jdi2Y3ykOLkdcyJq6SdFzerZf4dXIhpJY+3PnOni5EDeVH\nYukVvGhz0uYl0D6VuqRQz7IFaZgTSbdwKScJWWyKuwzukqPYQlk6mdC2wyeQtzZXKbmXjKNDaGdq\n0K5UBAYIBE2lzZ3POpzKCzD1L1TiSfZUpgAl0+KwFFkjjwBg03zsMdZK9fesGgi11Ukh7wfDS233\nQ5N6O3UPa609Q99FE/EFoJ0l3mGMsXMmEGSw3pazoQcWzrzJgarz9Liuhe2SQ0G2JSHx41KrqPMa\nqoj58VPsBXTR5yTgXXI76FoeRRJf9XoNA2hdpnhW0LdRSnec5wsoOZIpo2ajlVbZ1/OAL2xl8Vo6\nZzv0s9XjYRCL85I4RK5uL8Jfrk0e4C+RetSBhxJCrQb94dCkeTxHH0RRDf4eaG8p6Av+90glVPj9\nT2FS2I7sDVCFf5IcoOuFNRxHFuI5D6bVnDcmRzlj0YAxKJb4CJQYD8GHe3eftgd5WTN0a1Kmwdf9\noSkn+i0zzCHpZ6ezWJw/BmzDkyAytLEDWimi6ktx3xPC276tt2/d83dHPLsPtyxhpzxh7txr9Fl1\n3oXAP754yFMBme9D9QtU9daBrvRIZFGF8IUjg+lYM+hEZI7++Aa5LX+hhv6AVb2QEeh0vKWS0iEO\nQH0PFXDxTCFQ3p3XW6UCdXg8xdfFOMYWImz6edBxH0butcFamG0beRr9JGWZ5YFRwGAhMGwGSS3e\n6cxHU+BxRixJXL+uvvHY1fd7x8qClVS9UiJG6qZe2mxzmaW0OBdmciTX8AQAGFem5CWuVZVplPku\njNv1/Wpexajd7FxlBfCyy51WHq6CtSCCoh6aR33mqkaLHIkIRhvnV9a2KrKWWG2m7FjVPs52xqYi\nAqP5W2H0WH8mMi8k33EOGqta6wnsXd+YFnuHZOaNM9o3otZ7mV9LZtYpzeyFdqijuE6agaNJZTjm\nPZW8Pfys40m7aKOEFzv2mk5jVB5QsoqtkX+HUljEQncTdfLDt4q9y8Ue983dmZbhYSy3VNw6zl5F\nNnOoKZgi4nVBE16egRR+5Gjr3+yT5ackU7KfB7j2NsMGms9OLt0KWpvKWdDy2mztvOG/RNN8eLNw\niRu/G8d3nn9wuhubgpBGcVC5kMmhv4ksIQYn4T2Y1mVAwRXjCV74m5bu30e+rj2hkouj5FZsajiN\nzGmKhPK7nhsA7zrlgN6YYhY6Gq6VM6JfaXx/dviZR6aJWSl8TijdWMu6An3yKtT7HtzOjMt9bSJX\nzmGPwnpIAR1BpJkmqD5jKe7Njk5DHvP7Rk4AduNqoe/1zQDZMCJM/JpTGNqgEfHWitZkO8mNHM++\nLFD3iFgcZmooAxeVn9IcBdJL2kah0xTlDXMsFUSY9iXJW6LekFTZpdRWLlFY4rmo/dAlk5qG1oxv\n/1NGy1G/lRl741VOMQeUoyH5ClULTo9ABy2lE5EmK5FlwPj9iYclKHjo5aIzjTrHzzmcZH8ozRcb\n3pOm8WYrsCy4dM7jiSS8Cw4Swk/8avzpR6/h+iSw2kGlksN6QMexxhSQkcTpBfyxcsAkXEmSY6Rs\n6GrEo8Gy+NjA3lXeqcT0Y2XlIBCLTyfzZNuH4a1tEdkDPTQjbzQDMkVllphIApCcSH96m8eQx9t0\ngH2HIYZbf+racca8M+/LSdVld8wthMbrtFOqipK5FPE/i4oPdVAEg9fDlk6WsGjT0ACwta8EhzbV\n8sn87shBy97YIG+Y83+77F9M3K+EN0xVZb9z/AXbyoE8FExfFMfc3bfAtpiVFuOH0Bkd7dp1L8hU\nAMjjioR2VJV3vR8xU1IWWjOKNNVSu/aI3L3LzgsB19KHkGtIgDqcUA6ILpWhDBF5pB3UwxaOPgBo\n3pamXp3UYttKRkAk2ExD7B8Gu0zF1pqcKIyC/BSP89zzy433VM893ISYjRC/V6KJXr/cDSCi/vPE\nzusyPZrnaZg3Dr92IvihNJvPWmpytJPt41NZkYM5DlQ0jcIbAaaNELs2TQa4VE8Ma5aDUTmlT8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/3murI/ReXrrFPez1ufwtiJu8MlsSIt6ugK9W6vfSVT6XxsprsgR+4+7cBKBUGfC7+loOpXr\nzAnLRbz7JKi8iwLC6kOT0RUt7EYzIDthES9PIw22bL6ejqSkm5NtHCB5bCkv1mtteSuy5oNpaX96\n5mEuztBs1fMvrK95EH5pEMQ4BsvDOtvBc7xE1OzAf2PoBOFgSxb38m4n9JzSgP9w2c3mqLpkKyUK\ny9Wr+Cd+vqnMJ9npc5pCr6i5RHVHa8Q1p906iOw6dgt3A0T8gJINLuLA181BVOR4zGc9QLHBibf2\nJX7emn0h9txIxa8gsMyPQL77dPqyP6hDqzYUXI/iWMOv630oofXMo2wRirmxhPUnaB07dwYyibXx\n8xdi6RZWtrm89XxJNYNjNVZQuJBo2RM8ZnIGhIHHtC4eGZ8YoiNILNPx6TZVa4HrJWsRb/VB4KLP\n2+kT3C7TPACGxCwVBRBqBj0QXfeCkGX7g/d+5tjG11cw0y34JsVt3dZsVtuEefSy8fGtO9TPLgzI\nuKE7ZvRGY5lqPP2NS43m9NwmWfh/2ttLSz+WX7C7WgjFPl+ioQqdYPEyHzeWtsnNLfsBVEpAUhPn\nWV4D5iehOTj8rcsskKKbNHV+PlIioGB6sIK6XV2U/QKtWi6v6TsK+Py5DRvqZ2y5BgPoKK1HK6R1\nXrbw9OQl1jtxsqgB6pcRPlmlwmL3d4Mh3cXGSZkDAEvadntJGEy14Qsp4jyhqGuUsPuXEe02FHAb\ngRGRtiMQD+phGvopgNM8SMBxtm8M0gPcTIZmryDcycD7ZImYwa3WGPmBv3ItqZUnNUML13XTp8Ha\nWIe8iW9klmqHBBiCAXVBs8kbm2ixRr7A2LtmQu4UqRHLKOZVlwXLBYnZzuBmg0KVGD5O12hy4HJe\nW2ulEldTX2ANhfG97XJXmJgpKj5Oly2NkVV2IJ/r7x90re9cqbbnHL2+Jui0PEYtU04g1+lsyD8O\n77/aEOPQNUX97sin683kgT+VDAj1+q8jL8oYA9g3UbXIe3qfrgV+IPaRO93mdcjU+q2AMQ69RYv3\nG/5JelLYPJORphtedP9CcZM/XJSqCMFerFiYVbsE5XBBRzbWfb1+9dggdhKhrqSF4ujBU5U/lETS\ntZJ6oCGlroXGG++PqNAOZRWNybdPvKqLMwnLXl88hIU6rIh3kg5Q9MCCksgApVb90h9a4dY2I9tB\nHgC66doHP6LGBikqE7DqhBUyGTHsQ3QFfvlXPpTdHwDNkl/XwioLiP416KzUTsJu0VvWiK9ZC8wE\nvBnQsguUHWNSFYGZxMPlhyeLrqWNMPe+Ebm32vr7mH7BtiFLH8iskmaT+BiLQ2cfd/CwvRbm5JPB\nIrKWXwRRJGTPDReXHFcw/E5NYZIOP1OCetKBKFWowM96lSKBUhA90zKOZ2XqCzyV+G+b9ylDd2h3\n9xl7v90MElueKl7UF/NbejgNMH4WHjC5yfjoEUw3QUc0x32BUOKXudVFRugW9S7gm5/I3y+I9GpH\nYj38EOZBJ+XbbLcStx4kxveEjnf72RoITPeXY+QhoFcXvr+ySnonADHu0YWKUE0J59nOMe5AfTAh\nEgBf0oOulgR1TGMZZJxXAW2VLurx1YsrWxzNXw03lmO8Nrd7GIDKYUFixEbYNRf3YCf0p0cC+SoX\ngS6zRpVclBfeql1m6D/Dp7vjCKW+U6JBtEe2JSpJdkhl4oWeewaQbyJDKjdnfd9RVIItb2Ykv3Nc\nFUqqcoVARYBYXmgJqllnMEItmfFXHHNB8ggJUhUsvgJlfHpCYWzg+bE+empxt+3aU0k5VCNl7gyr\ngbWJ/vYOLRU2bK2Q4zXXzI2vuFyDcNB1wRPQpASQ4M3dV0HTVHZVRgucOeJiBn0DZAjlNCkOaEib\n3/zBpbIkdjaNNU4U/f+aqUe76ew2oyqqUANYkV2s/Ew1/UeYs4STiGmTywv7lH0vzfWqJ3Mesokp\nlkODAum3Sezc8ipi5U2IWYCXfYh4CTIkmgqEpi4eWLEChp3kqfzgvR+eLWfBFmpCEnytrpZEMwkA\nEBuLiT2sK7jh6VHhZ3h0QBzHjRtPNq9zW70Gf8Cq+vYUeH47OAi+tGNBwPo+4DxFJxUXixTRmZnh\n00/HO/kmz+wVD87DrZ++Edu7cpjLxCJ4fLpOMhvvW9D0sIy/AC0hMu7n0Hlb4gdtaurzYVIpKCo1\nJv/ZEgF+lDIjHGmUa93D0q9GVr60v/CXLtTgLeGN2ATHKRepjdje6nOlW4/d++06zUgVxMWBEajL\nnyuWA3uuISZhn6Or8//1DhJ8d8M+fOqPveCgRAPZ2wGUb1YrgI/8sEj3p1M1dISDtB83AO9TP9Ix\nZYO1kq5CB369nu0zMOBGeYSdIGuLGX+jm4Ndm71sVhUzY6HFaqZx4ui+d6uV9W435xfUyyPSqqZw\n9dYNDG+RAmfpGqYT7z47+mHPzi+eF72RAe3RSy7mDgS/8HSjI6z285qZeIXmPA0lgoztBJGa5m4P\n5ucPKHjmJ1frbygXQqtpUg/RHYrfuIz3DeOwXoRk95sfNslwnechfIz8k4KbnoFTOYV55ybEmdSG\nHb9PHf+dRB4OLY3c4bNxj9PV9swFb+LElrZvtkvrlYAZYlD0/Ncl2ZnPrNpiiFmgPc1Bg9mM7uTH\nYmvPBbH+BbM8i+ULazvWPcN25fwn9/FXyRwJIrxQ0mgPf0luKAb++nNs1L5DTpk4pIKcr4zX3gJZ\n5j/V48eDV2Tu0ti31z7vAeSO5WN1pqkC0nJSzYGWjacTuQSwbGtX9NsR/iFB7JwWG7pX4uui8NmK\nF12WgpGbwUk7LofhigM+NIGob/oJ143bX3gfOLGBjLgFB4QSRvo4QDybFmth5EUxi6dcVprkA82a\nvl1UvMX6LiH8pAhBoA9CsjLFM65cZ8oOIAX7vCF9hDsuUsYIzn2dsrihdCOAxSVUAA2gsSGDuSCo\nBP3gD5gYe1ziFs2XzxSKN8ae9e9zgRMzV/ROozbQZB07MWyIqH+vC/j05r2PXqSIW5zxLlzG4Ump\nSJcsYVTiwNf3T0rx88ynZlYYZda5hG+E43wLR9P9H9RZsKFlPDuhoXwi0OYtVXgr4/HG0spanwAz\nhkuWEY8OeUxU4VIBPnFhcRneDEa3CCrfqZRpigFiuwi0CCUfy9jQJgfjOdIAX5fqZCfQVBgmzAIp\naTGFtJRdeEKTMoX9ghu0Ojba+i6fc+vLF3CVQ6Poyynob36IYfeSjys6fzUHebxcCUFfOs0SzMFS\nOSlH3dghQMlW9MjRK/uO6zOQUbER0grnU6WH6Y23bni/L2SAfs+Ad1/8FdEqMXIK7Im1P65IJfHF\n28Wx+UzDNocsw3tp2fz+EyBGT1aHv3Pha/sVwqsnvOAaXNsA9DyjRKmgTXQNyqLq4GZ0YA9pmlfg\nfcRvh8fEl6ztNejdHkHAZCw+eh38lmKrHtamcA1aNTH5GayDFcO3ljwOfcY7cGsBZm2shCY8C+ZT\nO2pjCwxboSbKkGoc7eFfYnuRrDOIeRISCA0ZN407uZzE+gh9MSNcmrlk3w1WnWZEqLazaJRP/69c\nlSmEVcD/DLeeTmw4df5a8M91UOTQXOIV9/64f8jJRpys1gbUN52EgE2PIz6iD9i1QfsVR4KGuHsa\niL8cqq7Efs/tLWcf6UPGCsOW9yQBNQwIT8ChxUfqNVoGzaLGXKqOgcIcvI72PD+i5f8ldBVuE/JD\nqwJJP53V9JL+RsIDSM3XInkwWh28dj8CkyB78PekmyUIFmg8eBex7YLqxpv5meVbVR4rqhunXD6z\n96Z+izcUoaJtVjsPenuX85w7fWRuujJTc7XZ/Q3VtjHp64DKaEBCFCh/sy0naai1GeLoZZ9j3Mw6\nT8aXh9Mq8ZEeAPinGpaIpwc4VJHG40iYKATASsvLP/Rf7xLEO4/9BHEdO1yoyLG9UDAnZNUMOSG6\nf+JI9R62Zt2Y8LR69isscg82Z90JTkBN5ppVr2uaI7OnvFPFlysxifmeZZZrJ9OqoqT8lrc79OZl\nE0r6O1L1L51MzcewyovOBhocJz++Ys96TM63FcvH9lmSiSHa3kjr4ldskQuaaqmsrlJto51/tWMs\n5G0/JPtE8zWb2nf+1WF2zFTYAfMhI59FiPljN1d8Km54hZfa2/I9d1ib724YIyr8FGolfSueL05/\nOsWJs0TykJFI5v6k8V7z0anTVTj/AEnGIY68qAqOLGFIfu7T8T5/hlVM2pMTQ/Wzp4s3dIVMl1tP\noQsgFOBeXKhF0FlytM2SFJnc1UlEYbXwMYI6AMKZBr2BKF4PUgplvl+GcRgqRs8iXFeA7tTK6IXY\nuTcgpFJ9uJwo5n9vbabAIHcMv2Qos7oZZJiFVVwjRX61E8pQn1mXysGsC87lzig9SBxXnGVHDBvO\nwuJdS6Eyp8woO8YMNoVhKh2okMz+MTcTUwsNMmr4Z0CRZistrcaruXba2AKZCepIkW3jBJakyqgz\nS5CpPM5OhFKIlh3lLvVlrBHqQkoqjvPUf5MAUIgSTgiIHym09fgnvTBM9F3sW9E+y6cVOl+Wwvld\nTj2540WSPEgAtTCnxPEOOtrZwL6hdSEjL4FFrSQfXiMsLP4SqRXnz4kddBC85cPJ96NfEdIpCyRV\nTmqQlqpjb9uZgpJxMRRqHYeve6SoFR1N1gqgVaJ5gkWrclhLxGdK7M+MmwywDJaGmi3H2vqsmWOK\nk9N6vwEpRqODZXCrpApWC/Ing3b9FCn1B/agQDE9iCtulBM/ZjDhpOzxHLb13LxcKKIyjYVBH1AR\npwP7FFkKrAqgnHjiPQCFVyRN24DggfYa46J9rHnNX4n0yKfLLJdKuUi7LvzQXmB/1phCB8wmA+IN\nGPqH/UYUQ7wK9w7bvt/j/6AupZa3f8ZMVanmXW4Aglg8txVey6h5xxoJr6Mx+JzYNoX21T4Q9I2p\nap2GhtatWVUj8tOoDZcckBLsWt7EKdiqnxTn3f9LOZVEUW99eQt8sWM9yDizBRuUSC0uCBITaWA1\nHiCZW4nwxa1GUE1tpTaH+WRXQZ5CffL7NZYB97oADNqZ1br9/PfYzHqWI1Gxlgz92pu5WO1UCVV2\ng5VBKrxx+qcixi1C3n2vLkJiY19W0vAva8UoyIO9MbM9qTEKfRU3hbOFYxi9GBDIWQPoMmze9xg9\n3nb/PGDqCHCJgvst8LY9CocuErSkbvRPGT+H0kzsgda/L/rggB4kr0ooUvSOmcH5qQ0gJIVZg6Ru\nbQnualAfLxxjsNQ/6PQN562VLH3s9E0IIGJx17n6fi/AvkOlKgF1WQ834hrdckLTZkK5/okBDaHw\nacT8JU0RCK45qgR8kDx5Q1w3S0jytUhMvdlUs0/2qnBFUktGopZ6YdEBLGualbOCpffiEAwCCvXI\n0YO9sPcD4J+vqVOFhWQ0HpuiI+9gHoJqWuYQQZR2BVuFHNYcMD2fuTO3855j3oIIck9UVS+19Ve3\nFXhqWgNqDx1GD8KQqR22R9EX/R5hhltnK2qpeLy0XZ5rTXfEwTBtMfenSNspG+Dx1/5A9lZespLM\nHGpUtiQQ34wk7pDLbxTzNxgkYQztIYiydFtUYIjph7kRPXaN4zoDElWLRpyrG5GgvC2sQ9etjgd0\nxFDXb5IWd9NAISr+t3X+UHC3/v/n4YxUp34+WJu3ISAHQeuBIPk1qB9PG75A3tS271EfZID644fM\noMSQZy4Y9kBdw+9/x8WOutRuZMUeJ11hAs/9rZq9EOONjMb9Er8Tr+U7BZ9WsCOp7ZC09ED/x3U8\nbGCCHeJET4jA2m/+g2bcOOdetHUHNBi4DWLSw/C13/FBRBHfoQiW5OBH/MUycelZ8s2S+9a69scA\npG+nSWZCQ1MVSQPf01xfEkS/GffzJ1OsIKSljC2RyHRAmwwUKYtLCSaO1doaujsYf2uYyLTU6cMR\ntfF9vN5qCQ46pkUgGowtzmIN6lTFR/BFE9WvRLMpaCIcnvEzV2X6985V7IjF40IdVSNmy7Pm1La1\nsJ84kgWQg+mYmHc9iXppDdM6CgeaDsoPasWPysNk0YlPSUpnYd+Op6AMldR3nw8TPqLpOfrcmkho\nbFo4y42I3O2pgUHZrZLJXmBb6YI2KLVCk6eiwa7dPaTVW/xRBVyWgz0rveG9mlRCRv4QqqowL9au\nFDfwlIxJOHIzOGBaWQVoEd/E/p0bcENUbhc/6otJ9Zh7b40zZ9gk2rsiwv68Esb9t8R5MF3ZGjDJ\nE/3gXN4mh5LmL3a8iQD1n+TCkFkoI2n9VUq7CSCqt8pMYgtgDUl+CCZ60KGRa86LqFKfqedTh04s\nKOikpfa5Qe+ZGr7T0TqrfM/+aRXrL2eyJGOZH5k7d+A23eoXSIkwJpSCvOE9Z3s9lt0YikD6WLXv\n4/JV8MzLigUJKsx4by2zA40GKDJ6EI42JSCHiPd3yzZlm1dmPkGx1EHyT1JOsokUYfqffikd5Ywe\nTF2bOCsyHHlUv3cNPtD5fScIIqku2LiCpsz/JXsdlIIwlkJ4DdMe1z2pSUBBhHkCfQ3nUpCOmfwA\n9uHt4WlrEAHbozfQdYNMEKdA8zbIJaLFDKyzZBQBiK+9KyoNHFWryazcRPQAcw15v0AUOArQGxAB\n4qbvH/Jl4Y8FfSa3ok+9yXkQkz4IRlQxrLtJSraTNxqryK/8ZekELagvccIQ966F4Yv84y0crBpo\nqD4vbpkLmncHspAaEZ8J9P8JUI0+rFZtNQdQoh4gglRXlRJBIQ16TqgAGaBYeB62rQj/H9+FDK01\nv+6l4mBeGTNPXr8sDNY2l7DoXq0BJa2PSvbnGX7AsgXsap3B9i7etb0QkrYcuXIY9h91Oi2D1dqy\nOzk7POUVBQKvC/9m2aHQPzxeKMF9ZaFg96U27+z/TW3PCoFHg0rUKGo28UILQQdCAE39JjWtgi9x\nVFDL8HGDaaEnXFk5g2Ujvj733h5gofMQ1ZptWuyQNdDlo3jiLS5dNgnK2s6kBRpOpAxbihrKZkQN\nSpse2hf+la3nSIAxgQ22kk/VStea0/etDWrjYDWjFLVHViNdgP4MJ3272JxckobcyxTPdB32pxDs\nPOJRW3FHgX0YFCGE14V5AJH4vjEQ0AUIa+OOE60ixicnf+PwHlINqnkdjxHwcZFSzW5PU539oN/Z\n1QC2G5trYoJVR73Xi4LGfwwLz/CITIAF5v5U+esWF0H1YVKqL05/pltVvVfjkMFUNEryTuihYpH3\nUcncU+Dy0zVitO3bB1EtjT7wChzZrevxNo5OXX1Y/W20jIzSL56K8qcMb/JE7aei4guX2TW2oLOl\nLuPGTXblgRMZEWw/a3l6/jauWyLAX3eEcv3CLj3P8c/ErtK8LJ84FeiID+o9sLjmaNq7YrReUxH1\nsNCJ9PgcfqDcngh8g4OnYVcAKsDdRTx0TTiPfC8FowiYEu1pJVk+4EsQSzDPZ+KKxxcP7okSNSiw\nVs7/0aVgSxN4rVpJdQVGrKmlmd6vIlNKI7RBHbtJ9RC4xAQbKLjov1Ayu333MBRmHfG1pKceckig\nsm+mqxPEKOFvBRJd4+qgypp8I2JX52bOushtsXgMHyp0GgGpQjLHX5ryXv6FG6nf8BGIO4uIHW2X\n4Or0ZkdF2R3xLqZHlpBnXywIhUbMTIsmcGR4v18YmAb9saIuc5F+6sCr1aiC3rEY8ywB9Fy6f5HP\nALOQn5p4VDsIByNor2lkknDoTahJgqOXz3VeEA2wd8shSWPG9+vuZQGvFo1q/ip4ljMIz3OStx3t\n7b3B9UE/OBQMIXVCy9LZWRhm9OsONe0MHjdR6GrG2DUZQ63ovpmG8TByLtWeoiN+wMzxvjkeAK0u\nSsTzYiC6tbHlSQEV2v8tRAb5Q5++LzKSKlqEA0JRxMghsoUhDRckOQOADfD3gQOyH7LyoIjEtD4R\nhgT8UXwMcLDax9juGoxVGcrT2WWKBREKC1FjwDnR9MoUufQuf/+qiLH0Oygz0ULNYlTKwHvzLDb6\nSmn6WNFovS8Hvl5A2xT1HwqCq3XqHX9+DOxD3J5LaZzntD0HpnLMEUjQDKXoJZ/9PcKDhZyoMDbF\njB+lcYUKAiNA3J4fsuoWEs44maR1FHIi5Yof1ouo5sbnKyJkZK25D0efOZnEtLjlq80YDyWo3Kd0\nIhmlDbXidsFC7Z7mRz9H6/o6jzFrbU3xIheR93hx98x0fMCrYvESfD0xz6N3J0TyQvV2AzVfJWNM\nuYZiEZh0vX3KduQQr42S97NvCcffX+rYxde6ud3IfYBhfJbeH5hCGQ4AAdmcestkWhYJaXfu4WYp\nBV547aPeyVc7cxss9cDgAhvWVvt+Jn9wWhl5VrEKXRSS3MYKmxU1Kon8xnmd0hvIMgShQR1P5vdN\n4nudqCz6vOW5C/TstzB4bIurjQdCmVOPQvinwWYHWh0imfT5Vqxd95WtaSfRJ+lOe648BQd3f3C4\nUKUFca0KciEu2axMSQjoOarCFpv3eIdhZ/IwgJFY5X25EaUqu+YZ5R0kjYmXv2M3U5Kqiv+J9HKR\nF5khE/vSOLnJpC23DdKqHWALjKFECLPRbwLvy2ffQHy/aNwb+yOpayU07McPLi9ygqt3Q7yDRkog\nvP3pohkeG/zLpi9KYeTZdBMSMIpsIv2d0qDeknRofb6+mGyTetJ+0oc+XVJfjHrVzrw+vXMREaJS\nyJsd69/o2gQnISWrz5wsuiHOP0xLQVRsxXlFbT702e1oLh1tmdWXUwiMoU6ycY/3YHZZW19XTKse\n9otGaJqSZ9XAgbHFV/tfVs18WAmpIVRnGA4kcE9Dfqmd8GUl3Qn+iVSKSjo2IFIn/Y8XFT5zXsZN\nQYCgUZDtCxa6VpQ54IUK9vJ6It/5J2LpNBEDl/sZRvW43POonisONQNF3pVm2zAFRGo18JU3HxWO\nRcQXkoJc0HVD2QDDHsjiwKew9cz9sUjLlPFUeF8zsUjI3m3kdk9kXVoBz88FA3ngFp1Pj8bewSjd\nERI4Wbu6+pdBWVXF9Lg3+fkuFlaci4i+jLIQhjlM5VzKYukmpMYG6jVQIjISV3p9kKx8fh9LnYQI\nJ+sWeN3DvWSNdtqsHVzBVRis8zFDpu4bEzuBkPpwVZ8ol66B86Gsq3z/HO5N4Atsl+2FJD4uvmyY\nhjGVnTGoAMIJpYzZ8AbVR9TvQwN4LugMtUVCKtGql5Lw3uYo/P8+K6dcMRXFGF/V3i6qnp0ndqZe\npMhyadbcLnVBgkMtfknUM8/XxDQD9nuU6FRUaNOPzThL90ft8BclgXJgXBhjdwxFR8ztl3gxO3Lv\nzOZByFIaUSFPu2mk+qBpx8YBquCN3djpGp2dhUFAa9Ri5ccV/fQAFwAo8UPKTjHkKFc7y0d/BHsh\no1795Ye7PNExMZ2ip75d6AItSgRYH34wcvoG7M0XFNy6LDttZU6uY618lvbdIgvQ4tXb0SuWLNnu\nElkT7mFxDwcnSnQJtG5NzflTd8fvpug8B/0V8Ur5bpsOOW1iej10RIMQD34qJoGsW1X96FkSVTgd\ntjsYUOkaoDR0dMK/o2RWkBWEe49Ve+bHe9lRNgLfMyf3wp1xWK3Pdbr1ZtRkLquacfom2gXJ92Qh\n3c1/QVukbNhUmpVXmfVsMXbjTjEToasxVOhhQBgjx1k5NDu2FNf233bAhN2BDFSYw6+tKnfBjcvL\nvUoIGW0iWNrLA72Evi5Ksnw8P3wbG4I8xH/nIpeB2j4Kk5DJc4S2U5jTumr8xyVJKPmhgI86SsAT\nzkudLqaYIzzMtC313pFL+91gdevuq8XVvbpK580PDXc40E2Rw+cngez3fj45vBxmtIwZSCPu/vgm\nzHjsmGJ5PDvKZrAQC2m9VjzU9j2l9/ykBCmehn/UQEJmc+oNNwyEgPn/7LeLYkB/2DTpSGsygbx/\nBcXcFZRva386sRthkwIoGbP2LPyBLSJuKphwcdLw5dbLfpCsPIXCpKfbTXmZ43Uw26u1gQTcqNJZ\nfttUPsrczXuQVkrJWvRK+V4DSDzHpWiEZ7x9FVtUxr0qDjEnw9cm2kFKfjOdGfLRgF30tci2XeCA\nUIqSW+qYKBwymt+cGt1OMhF8xhr0r49UnqrZulzu3x4rAwgNUzlDUFwRRo3z18sa/VoU6gCC2TSw\nb6eoCErhsz9TqcF3qlyd9RRPeGq6xTtn9lNV1LoAFXmZJep+jSs38tqWXKKZhq0PngGy4UfWXZ/Q\n8M6ZVGJwValsUEVlw/XK9HdD/8/4QcOvGcD6WWmeN89L07gzQ/8z2H0BqrEDNYN6SpXrVuuy/q1h\nDjfriLncU0gzMMJQVj1qVNFUiHm03cf87VvVZw5VII+Obw7spL7OVin44lf73bFwaZmZjP48M64b\nGn3Vz7cC/tcPrLmwhArgCCjR7r7pUwzqrRdDhY0wRXg8AWWb3ZNjLsskSDXWTes6dRjT+7xHQp9S\nPmmvs1FGrDXhBvhYX3quzAo75TyhXToBCDYmpT7Gd88SKMvSVKwkc0qWZznXb1j7f/V21Xhh6qyH\nWi3h+oSlsCMprYv3kEEPHQk+R2TrWPEvJ6TXv2xd7GO31/Te4BVBSDrpXAuEU2Sy3ev3TMn6e8dH\nQtia7N+F05Ot4wCo+iJdJI8b0mGt1cFnXD1F16yD5ZCrH7vWoFy+siTRr77gQi+GqqCOZ/2f/nkZ\nIZYINAcJTiUNmnBiaWhC6qkVbwU5ZFEK7sVVqCr2oU5JgOTs3kWgSBi5vFTGd4IJhQZ0UTl2dTIH\nCVjKAx7zODxDVFvF8GsGM8YY8fFhU2+QUihjyCKN9XHQM9cL/hfmkucoD6T16B6Bd5zEN4ROsMFK\nBsovKm0zKA9j6ufcpbzxvyVOzP9Hn6EYH8EN2o4C9f0SQHkVjywNGyLkVIbjoCi7ZKwc2V53ppEs\n0AMqqaDYRa0esDHcYQRE+fykZVewk0TC/M4Cmzt2p2zLrbwsOBpDzGDbuTNeYwuov82MTzFVKYhh\nIITpIpM3wW36GY8M1YDhZPKlL/l2NUaEnro8JJ05jSceqWlm2sGc3V+AhLEFxYsuLI/Kj+LFU2n1\nwxNwhQFEv2FpJabWZU78RskLdPp80euPDkk5d8Zt6CfDvvAgPnRIIEoBzPSIZ655PME0SUszDVl2\nZDKurEXv8fPABpsOqULM9TcWQkCG+qlFaYbivrjoV+hr6GGhpVSPcHlfWOCGBsm/TBDTb4NtgQdj\nAPZrYTQH9jAs56bFaSe+yqVgI+I/zWm6764XDatmqQ0VB1J/DoniND533CH8hxTVeLdDv6BjXTzV\n5a5XY2C/VA8HjnDEdhDfR8q/Qwr8tlF6oN67/l4ba/4Q6iWcmPR8EdOSbnNxHCPtDW2FYRqjOpAE\nMssBn2rW3LxtY2NayIdQn1reI7gxBmDwaX6VW3/jPh8XBx32dzHihbuT9DWu1jacQ7mr3GOI5YYH\nQ1YSFbZvtr7sRfLY6YyLZ2zRJt7J3E/HraJSqRih3tPolABqms7DklCgL4gEJLVZ149iGjNed06h\n6Fn7B9gJ3UiMCLDx5+AaY3tWIzqABQbUe+qAfujhKKMqLGUfM+dmpqyh7z7FyQ2/DEO/fITUJkPB\nWCr4ejbXzSQfusnRVc3xWE+vXtmy0Ed9uVjIc1hVwHmFuJFNHahSiWOraqd1LESh+SR5MT6sSzsk\nvsA4wFqJbNU8T02riC5BD+kFkWNXbpz1oC5WfADgx0fPNFoUxBCXGITM/ydVpmiOGHgBkVKAJTae\nAC1ef2azng4ZKyEG2kjEzLsc11Tm/53G/Q+VxvV0HKv6v9B8PIwLxGazT6iCfJXAyt6zwn4hAteV\n39d86N+nZ65Epz181dhJN4hEhp3aGRGXYJhVcPXV6XDHTDscShleKJkgzp58MYYBEsEbFi+oFdzi\n+K3bSNZ2KsG6XyXRAEXRSsnnHdvyGqR3oNnH/QIUNOUfX3ioimZ812aXAigoopffpbdHV5RM9yDF\nbMTJohZdkZVPr3rEBasZb1zrxi7W3Rb/M6VKfuNqfVqBomAzQGJb3BYgSYoh8BC/br0F42DDyAw6\nPMef5G1HkxiAYF/CF14YhJi3iiBhH5TaByTirzfYz7ZS1vkK4ULoxoQ4KFJc9wJ3y5HvTN+EtfW+\nRQad/pay8FB8M5QyCiwIKggof2hCWw2UOdeOOcwq+SvzCY9As/wm9HVFbNoy08EoprLxB8CeyDGD\njQ+BVlyjAVEy67vVVbLjL0XX/4tYcBFasQ3z7/R+wsip0y8xvMqDSy1Rccq+cLBgW+x85cEOMlM4\ngrcl5wVvrGQ1bNdbzhOx5/jtL83GJ3PwBEOiYP7imLak/uSix0yhn2ZjITcoS4H6caziztXIBlV3\nbPLruEEXnSHpYAGldQzDoijuP0FJh5b/xi0En6tz+q0DdKEd7M3TllwMm7w5vHzpiC76lH6yAZT9\nMzEW/KrYlJoCBxZI9VjCqm/vnz6cuDQUW07zJxwuJJwwpft3VuwvlSojRyn4g7EN4I7yz0kgf5Jh\nMX8ushYupJNxFhiua8EWIYT8oX4EjVLUI1iwnEHnXBLWcLrSGngB/87vfFaqKosYLFjml3t3ABeH\n347oMKgXAbokitX7QWgOU7dtFjW2UdiC3NxsQnrd7Jt+7v/Z1piNfZqkcDbL+NfMroFZ4KkMf2oh\n3jdOKo6gOlNDrKs4Fh0lqP91CB+HrEEpMITt9wKs6IoKkTMn9KY/Qwq8KHFcInzYSZZkSKedE0i7\nsYj7i/ujCeHsKn59aKuoKbOBg8Y+X27mWIX91Q913J6ldQFeKklGgrYsXQic3NA2I+4XniOvLrhn\n9Z0FuiRAKABhs4fS2L8pnEukyB7g1sFt6vDBQpcqX53W3ue6QckjZJQjLHXKOIls9KmrKHaJxZs8\nZfMZKaM+YFO+ukKDebRYo3sK7SadXzOoS67KjuAJETT40H28WYUMiVZBwxZWMMnZ/jgsY1F3aZMn\nRDYSZLXOJd/h2uR3JoT+VGdvZ1+VQT+TWxHtTMAhq7YreAhIoXeutLU+aFQKGdDp7gBoCSW2Gxor\nOl2NYSa1qaZrZUXxfiJpR5NyQ+vQcy5guUPxWCGbJooCyw47NO8GJkitlfGblTz8FMupKqi+piDO\nmjbM0keIWzL/+hIdtJt13yEUff1w/qX63bcYVxV6pVM8hnOaU4h/Fc1lL6moPqattoQJdULcnnp7\nG5FjzFPqyMvU2ZZ75nEmIyNSSMjFunVEmiZPI7wKo/HEStPO6pp4VXGilwQyYgGXiUQq4++JsDRB\nNyowNCD+On5fxFfrovAonNLd/fCulWl2hKt+ovPRLb0Y+N9jN84KwPSyt9pHvKzjKHZJCGrJCFwP\nxGDACWHT1zNhRXnAr3s6qqk6H+AHNqqg0J2PMKMd4KsEQxAIh8Y2ULppkXXsbcnSEHOZzMD8xZfa\n3Zc/U7jAfBo8WiNyBJs6579nJHoVPFmOwKcLdvMkzGNNmx8ViaGxR7OAi9r9+Iv8dXW59koO7/Zf\n5LFtgC9ETLWzYqFSU/2Tqj3r3cHBxAYHUmefkCBZdKtr713Pq+D31LZVr1vgA0yxZfTl54IsYMqo\nE+jL6Gm2ptM5CrFvz44a/Od5Wn9fv/IwtJOskXEmGSKwDwh5OxrCieG3sA9Ue44WmvmOa9rRNUlz\nuzt1jJEYf6m1Z90ZB8qhun79jbM+8yGnTunK++FooOfDGCx/W+LPYNbPdrXFqWajKwgLSupyoWjr\nDZo/Peg5su9f2Q1p81prZbfXtnswvnhlTY0lfj5cx5HqCEodVcq0dVgKBz2jBFCjobgEUJlL3G6k\n10gYZaX503bp+IXtynP342T+abR0b6C/2sJTMtOvgmTay///YANtIULczYCojJGqVqQlEPPcuiL2\ndPLqbGJCuluyziTd95zs4iyaoPyBI+AD2UJ9P8nnIIouyIAhe/0rPDVIAv0GAbbfvy2UoM4LB7gx\n04bHEp/AtH38g1R586xUIZy91yeqrNB0gY10SQAtCPoMuLqkvsBXVN89hT/w5rulZy6sQanoYELZ\nb/POBVxSLUaKyXXobhjGbGlTfeG8NGzl4KOEfBfbnucnZ2A+QToODYyn+ZNcaPuUbFPmDHsoSxEG\nbQxaMROay61twNek7qFo/3vkXExFR4ut4u4Yf+WdhTERzdW6NSrY5UzeUcij2MggnOxRBHe9nRzi\nidw5LhgA295N4W2K7RZKWl+06qr9RYOyRhVSZGzthNlrkJbz2D1hLILGZFWWjDWhiRc/xXwXa+AY\nxMef/UPq8khDD/6EtMkFHahrZ/7/u09FhznpI9z5SWkTxaOctk5NcXN5+CrGx24gxAN49oGmM4Yy\nbr9txNLL461ejCFkOiTgdAsDserllSaWFGXFt/l36U1fYTCQhIDzeAjpF1ZTtUCySvvWKe301gaM\nGLqNnc7HfOzI7Uysuz+M0dQLPJ3itKwdc5j5j6LJlZNAN3Zg3Vi8leTJfeuO5P1gFR3c4fiVfRK8\nBPEHz9XwiSIQO4Bz3m7AOcrEnGadXfYPttA6STDvowHki0ceEZ87ANzQwIo6w+UGM78bUQG51tgz\nqCqbLnNvFsSNPHHUN51jjFFxIHeYsYpx77X6aqFE+qiR4Gf163L4ui5d4ACY5JN9k+M5+TVLytzw\n4wXewmPkNLObqA8yQeW5hrmNeoK4Z/z6epC+ZDn8R8RWTZzwo+K2KwPBIeI/P6rHgPOrRpSE7UZc\n4UVZ0aMIkFFEZfvMGYIcGkUelSlUOT/Qs7OpLP4GLPLQI0S+ROhakO7ne45FObXJ7jX8dFK2x6tb\ngJWXem0C8ju4DdqB0p8fbruy99cDOgNfFsYcOvhscIFnORE7dzc449ql69hhx5qbdHQMXWiwFMrE\nyNqBo8kmwu28q/cyUn8LTCuhrzoCwqvx/HCKq1a7+WMWx6f7cVBjqqpUI9om3g7uW//zPXzs44RR\nKVfUZ1yioeJTsSjIZxfKP87FdAO8jN9mV8ZiIibw+CKXbXm7IL/Kzc2oYidk7Z0Tx0/ucJ0qyJ7+\nlL/FC+NETxYJNOscSSEfheDrIuQbhuMI/ldVm4RIoSR0CPeo/jSzfwn44qml20/rvtZa65SJ3bnf\n53LKImqR/SlPTmb7ZL6PABQg0eg0RZyvi83s+5K49DosOXEedN8LWDCf0uRbg7ZXGd48XRwcRaaK\nSBuLCiKvc9TUiwJiRM5X+rGn+LCz9of2BeiFTchsYDjju6MVLFprj3EDHmurKDEn46iQxMXt1mja\nxc9jg6D6Gj83QJoYzkkLU0vxrB3+2857VfAGGk1yCYd3kuyrHP0LmlbVv1puYsYV/lN8m+ju0V8u\nwamhFLMDX2oxk4kE/rPtdBI0dlI1oJmWm/DiYsLvgpoUSc0k1jWrSOjjYFNYgwm3Buc26tgAjkXf\ncUJzeL82tQ5V35DjQqwxfSki2xWpVQBw3Dm3clMDqywAMCOzWwEITgWnVfam5wcwmtxjjUecopbw\nW1HO6ptTQtrIApi+jQGeF68tjAnoHcIrQQY/WToiO+RGyM75b+Hlsuo6VZElhPU60UhDp3lZcvLP\nNQOxkMyPlSuvg0AONBS1uw8UP9OPoMrdjilYe6ffPBz/dXLZywfBdBFJmXZZRXqbePST91K5k70w\nHUs+pd0PP+6uV/Q6YOmOmSUDjejy6HA7Fscl205n7JzfoWrrsZWnuOPsrqaS3uJ/ux0W4LkuTYTp\np1K4skdVCYRC+4+B2qx7k7JRY8nGdcUeWJaYPbWXCgJU/2onMrMhFlwMuxJqJ61HLiIJoGDpAGvj\n8TjzLgnaOOO8/OXJvK8QKhLZs9mejC0DTriVq15kgZcQRuZ5jnSTvq8euSd8LE+i153vpEe5+U9O\nJot7t9WMDMnHMOwxCRYf4+BPaz/jKyX5Ek2yIxdeNfpNYG7z7Io+Ha0XYRmfZLvbCyqtYjF0ZL46\n5gzGtVIHzio3R8HhzsLVAK5TQ2rRkNEMHw7/9XSvQkpYfm8Qn41f7H40uK1Sk5RYSrF0Ii1bD7q4\nzV7TvJ50EitpUY+vk1rOWnsHKBklu1FnQQJ7SN8Lxzu4ZF94TPLbyjPQ99BajMataIGiHyOeLoPF\nLujSuC5Iy4wrRUgZSL0QYAOAuw7IeOceoKrm5JAIoYDale7+J4yhyI34FUWdbfpf5TCrfRU5AN1H\nfIqHzkKQ+7AeqXwjM8rJSG52iLVjBrm9WP0iFAIrNkcKH6Gi4FkmDeHu1M/a/jiRvqG5Lt2qPiFu\nvYlKSD3/WBE7Z7Av5K1yQHJxMZeJ1jxaaHbTeBkn77mVOPmOA78Ua2UaWiHDBf6kHYRgk3UESo05\niVBabpSqOSOE8aUbdeHlS+wPJENKVscKPet0AbYzspHj+7KpchRxoHFTsujNh7BTAOqJCfxMmnLo\nwcdBy3RH7cBXl1N9/elA8Ks6ygMWYPjMOevGGacYatN5QJol/DKTu2zOH9BcpKy0Uebn+cPwqJeD\nAOLBYyIBPnyxx0+oAhUBG6bmjbZ/U0GRAuCM+Wy5R82VjnFRv50NPq/zYIGxgNhAf2ojqR8KfW42\n6AbcqQRsDin56I8jLI385GJ1OeFak6dkUXMAgW3Xn9QmVV83F6YEwWGH+z/lUAJN23SSOQm6TVto\nrmzUPCwu10a909NFGnSy0VjxqZ4N+E6TJoWtVMKB2F/1VzpKlv/qY0EE/CNMuI4MDNYUkLXVhHRb\nDsWoOM25epR3HIcZbZWvPlyxtWMcQX2JXCJgzOXLHiqn0wXa9QfE9gBVQeFcCcfr/u+LnydTCsrb\nMSLA8OabjiTkSVihw4DuLNOIdwlhA6w1idUD0WykgfOfFAdrbi2DLPNCTHAVpbXRf+2vZP8n7J8g\nuLi1y/kyqzRmJZuNhNSZxqM+aaGBMX/CopxQwkkjB6Evv8CL/PffqoFqQ3TJhG4t7R4FLiZMMNNc\nkTa7PQtQfwCG1zv/NLksv4vm0bNG+7/8krKvTDF6mEvrxDk2kd7DHH93RpEhCRl5lwPZpWub1sMH\n5FjA+a3FLllfm14ZZZenSm2H2Bjkg1Nfq9vE6wHlqKy6tENeIzn5/svgmBRWwok5d0wKlgjxcaOv\nCiOBgdrLVc1EtW/vqj2cEODBuVcnKLD595X+cMgLEw6alyL7nxSsYND23OxzhF1UoH/Fz1il0iiz\nJJyKFsMJnNVEeEbTcNH+nZturhHuFFd/77nEwspCb2Mf0PkATE1iZrncHbLh/uV36+ZDP1LChlSb\nf/xIVHouXsZztG13do5rdW/OBlNBhOOcYAOykAI3QOYHjDZ/jBi+71UGyJdZfOi5ci5Ioh+kYnrU\nxxmN+fIjimUMAimb+dCkqpqMLagluv5WsZMHW2MX1m8Chjnt/lS7m658KNUMT7RxOwaVyNgeJCQC\nkRop/Ipom/1RJ9P3U3lVuKP7a1wMMoCNrki2ZCykVVU820fbuP+pTFnCQAlGL7S0cpk4dG6D91AW\nOTBMFfuSdwlMb+yQMjR/SoZlssEo94I4blNWl/9ZetxCjRy9AjVH7+T52XARuRZCBmasj2ZqPhxe\nRLX41Udh3hmWsdCjGh8zcvmfi5XWYPFoqzTVo0NvXWVrXsPZM5Uzi+IsxmKUVDq7au6iTAWg0cYf\nylT1vUxFUE1i9Rxylqz5jvo/BlL2fPp9+5UAJhVxssa/SScyMlKEkKHbuqW9tCmoaQWfopvpT+Ph\nkLFX2TALqTicvPQ7tA4lfXK+XFDBLmJIGXonKTzzwpuWBrToM7qj+iAgE24W4Y5llcAJQ65RXQqL\nDKPM45dkiSZGAoeEJJ7mVnheMC8Yr4cqQXuDTrJiGkppd/pmLcyjpNKGiQALw6IZteH7Zp3uud5o\nhMC+gKOC7nZwdnI8g2Yeo+3za7SWFWiCn3yO6EiLSLKTR7MfsWTpwWkmy4kEpUb+SxTMwbg+EigU\n1NqBtDSh4qYIqEMY0xWNuwDueknAGK5SZfSBfx3vHEz+LfkzHCxTpRawYyoQPZna30mk3X+y+RY+\nftH4kOh2urVcHISaixoOYIcPsHyu2R1npM/2VLsZXdvZ6K5pkqLmMiLc32EfujNkR6N3HSct1I69\nx3kTBduQPNmTrVZfp7qB+51Szimj/IfXAks/IBwzGvg4e2FqobJOtbAkkwyUI8SGHWqVXBWA5KaK\n4H7qZ3S9Wrf0WnZ97kS+PwWviqI/oE6zjwf1/LqaOMBLTjbZ1/egwk58SmgIxee2W972Ek1jM4A3\nqLWp8TYf/cYYDwfNIbeeoif64ApwhyLPGrUYreomZjM04DDfVwSNjAn3dKjKovCfTAsCKXSxps06\n7dCxEGzFuDjLaf/31SvAf07iFmXod/x3RMlXoXyqvAje0lP22mCzyJYnRAmGxr+ykqF0S+5xVauC\nvNWaECA1pQZYOS1t6r+/iVogz040lXyttN4uVXKWn1vuNzQbFuO9jX6nstjuHQAeAaHyFoqBOVT1\n5t2blnVosld5VegP0x/bFNAIlPBJNNDV/nBhDd8/jn7GcHblC53o4CSsD5ZfO/I1/na9swtHcWny\nTCcNJ7BFLwd6Sse+ED85++hWedJEyK04++F+uimCJ2aERnbp3PMwG1l1ByqvRHL/p4zRm9q4bxOe\nq9Tcl4a+PQFpkXzukVZPftr81/z6njWl26MX5R0CsAxqVAaFhXYhwwtXZ5/cM0vjRKvBE1MedSK7\n+5iFvI5S74jZmpMzkDuuqTg4KQI/dxaovhv6a+hJEky2en0f/OGBbAt4cHGfH40bDyT0sbzDuBXP\nT/RHWrfFzEdJc4voSIcz1ImkS3g1xTbekd3+T1pnR/ILU24UWkaK9JTsOaVE4jeQpqIlV1SCOOVK\n/Xt8cBIp1jC4ld1N/oO7lpLfoyXwYv24NyfFdE9oW/A0zdciRoHihhho1M//a0JWzl0WcEnxhbr6\nYKyIoUXpOJnFbc5GMGQZXmC4VwkUinIKey9qC62KCDDpvFuNdoFgQhc3tQ3aKZFM2kl1ezWP5k7N\nACZT/wWRKPVm1cG8Cjr7el6kGQnPRzByYtWnrsM1vMS1F60Pegwc8gbM02mK0smi72XBpLZJgX0m\npJTHajzoQN5vot0mrp/LwBx1bYnxs+ovV9iamJ70pc/7KOitZIGXgpiktumy3Suex5sGJ9HCl8lI\nOcoWf+aBl/D/mrJAYDxNLvWY2n8asUTGTwrGle//teyVoxD1Ora6yVJh9ftoIdlh28qXKMukdZ1M\nTy8uW7SkOB8595c0BjZKwU1doY4UEsMxIF1LiBAzPCW6K6qU0kMx1Eo+plus6ZkrOjbCkC+EB201\npxzzhTwcs7tgaIFD7E/Dbl29RMP0/ze5JOS+ePob7U7TmsmFCnGfC6VpB4GIFk3nEZvru3TudDFl\nA7cyCtdREabc1LD5o1fJImqAXsUdszaVYDDYLg93pLB7878eO0my6RKLsDi35dz5a74ux5aWL9ot\n7/cSZhwyoQjunhT8Q0+6AC0PKeNbV3RLttcCFclbkzwXs4k89lBWRmzigfKI2KO5PyPuKxe+8znl\n8tFVWEnkVrzbvcLXA0Eg1pY4F0gnupajD/Co9K3RIwbM4uUu3Q2BVmvP4TXm1gbgSfxCfbcpEx19\n4zKTjrFh7Ns0hFjcnlWCflmonXNks4diOTlY+U4cFyP++19W/6BO5HSznq6qfgGBQnYEoCPJU7gH\neOpmhziLwHr5t2zNBkTgnpe28hQI7FzFiNbHWUH6XQDMHAK6Q+RKbqzAellKUdmTU7PKBe8Ia+m2\nhS4dqH7t2WACNw6qTprw/sZAw1nU2uYUwtzlyTaS/6PbN+G/f0KlLL7pXDThyYAJfvjCTt9UAGqa\nZH24BnvwUSH1UsKZ9zwHO8Cjpp8+J/sZxsh3dNefSxStM4+pxa6aO/q9AOJ5tb9eicZD68ZFaNjO\nxRWD4kAYJOl2fxHvBCitUOi/aPyI2+V2tgsC6rod7ashhUhRQth+imV9pAYGx89+FJb+5pH3p0cP\noKs5d8j47DO2vE7hC7Tut721DVbMCa5AaFIOeZ9Cw+KHIZl+mbnyha3oj22Op50mf6b4grWanTwf\nmYMQ0SkkwBDX4soBXkNDSUf6iBXB1M+R8iqWNTX1rVcrZ7JpHsSK+9itPJ9yqct0hFTaZTcsZGlA\nzsJJJyvVt3Bt5cKyjOejSMiq9EooKOKDqYmU1FNa8gJMSEQGqEaMqvCeLfnEp/YyXJUhQ7hLciv/\nB6+LzbXGq2VnUa+fW7rTPriQWBr5QAfu9C+BOfhmicVkNMWYc+kPzePQ7TIwRKCwXxIz6Ogg86Jw\n6pBLT3bqxwGI2FexCrjIMmHa0uwRSbkJTqYFHAi+YRQPMLV6u6mXSooz3Ej6wxFPEsvqJSAPutAq\n5l+L0gik29MlemGtVUsv20OXn9wEtnFWlHRyB4BAJyEpbE0A7Vmd6MS8CbwF6/0dMwYvYvTTgGN+\nP8Ha+VA3Phy3hTY+JETDIl8qNMK/71JJYm6woxpqSpXLiAUgSs/OnrBHJpoaMsA8dy9dDFgU0aB0\nKvDbx5V1N3STcEDbgW0G7qBrHv7Hyy5YkjB9I+uEUv0W/3WzjxVxBPwKc3dsiSAREsESLCupoRv+\nR1XS67nMz25wp253r/Fo6ZVcZeo+7iACMY9XTpJcS2aT4BSxWb7jdT+4zBxN/XRFlSBf6mry7y8G\nbHrpSs4zLM/iXBXn/J/0K9pr9v6GI0nedHcMXIGW4AoWrB/3I1jsILYtibPWpJSpbz9YqgYjZW1G\nTLl040dobZ1K7VWUxbIPq6ipz8lpgGDuGMdZDOCQxQKfnkhMl3+CTa3zKM5vNB8aGqfTuAKt0AHt\nMjJHSyzDUfcOTeS6s6HYu/7YiUOrAmsB7/hDUh0BP3J0c4Fq3xno+AYtyReZVT2xQNHsaZ8GIEKA\nnqXge8BuG5RtkklkhguVrd3Z1nld19mao82GYxem+Frenb3wgWF3oVh/nSFC5hO1OArjlJH1lD1w\nifq+9POF8giLzU5ALcT5PhtsG+vcwACcDj1wqcaODeqb6ud6rlYHhf08eExHtXlp9sVuEkdqW2SD\njhyN+X5LxKCEX+1Mj19CAPLv4pkvjvxoHdIwpUFX2eCQwgn50MbUCr3976VqXIVp744mDOcrf4wp\nps8B5RsHcK5IoDqkT+yi1KLoA99yeCgsJFoS80FgKcj/x7iRCHdFqHTRuASCGi3p5nWGK1Ft3FhP\nQi1U9/W8Azbwx32lguENkw9eqb1GIcx9aixFAJYoJBIH5U7NMr+uHticdZStAwljkReZ72H58ySp\nppPdUk6mt/Ur7tox9ZP945JK1XGkSvX9TftVLbx89WZeGT97t45c8z7pl/vqzcqNaUkcnNHeNkwu\nBmOOuFf9v1RnX344BInHYfy0LGannHPVbK/MOE6eZ/bH+hLiWCdgKoNxMGKNFTvcdggAIogB5mZg\nWU7ikTNUqEAypS4GY7wf8hs1hLBIamTF1hamMK9ixIxg+UFnXCXhTSkBVQ4zAM7CaongIMebCTbc\nm2IzxOhlcw+baH2I+hjwidBlLjlRbUmoQgBqAdrfgF1SGvOA946fdLs0Vm40BWw4y7BMySZ1twnq\n2QtJ2Q5pkxqZCHjn0vpxJ/CG90KbAF3imcRpKgmjmjAWQ0HcbjaRB4xZvCCU2msO8/JiqsSdi796\nxfpDYOoKCRlwX4hY/sqGymxM5hwsOoMR/ViCKC8jlrJjYn0xKp0RoKb2HTF4KKpfseELXHdrkQ3Q\nHdE/2Cv3vxcZug4OqNt0vENUG6L67opzQivmydTyGEO+0FIg/3Q9NeIzaOBLhixCvYUD/4lscY6f\nblggR82JAZ1CjC42+LgoY4mUDUgV83eV5QQn45secr1sAp5Nlieqrh5+Dxw1hreQg1uGaZuuY163\n6e5JcS740UxUyT0soXkE6VT9ae9i+GrkR/lR5wtgFwVF/dfUR/h9kYOBrE5Apxw9/n9urX+14qQT\nWWjoj7r5r+ebLaRdDm/g7H5AB8V6jw/8AEyBqfI5V4tEshQsOmmcJAZrwUWojq7Z0J6ngQ0cDDw/\nV8eOP8ENWD+Eqsa2qz2ukpGrhYOj5258QcqYizxntW9IOdOgpLlPrVbjDSlOLlRKio7Q81RBKQ4Z\nUgmHOOH0knDEWM3o6HBPnWoXNrNA1cJlLwR569hwIlDXs1gy8MCSMVBzHkQbUaOjwYisFrOzxR0a\nS/tVEv9W0JqjX1BssI0L/TxekFNd/5hnlZ1JXNarEjzcTMLtlkcSIOcxVs2KoB+wOK3YveHq/uzV\n3903VsYbHjv+wTWi8sbwhyz2gdj5eTNZ1DtTRRb/QHvOeJpX5RO3IbWrnCZdoqNYg1p8uS6KpA/O\ngGqUrdoiCcLqwhLqvz6DZ+N1mUM+b+EbRtWIqtsBaDlpZQ6JRbei9Uzczpd3EHoiwMmuK2v31Rpf\nRNaERCT170YOlvCfqnYYKjpRUKnK8xZPpcze9AV2m+cq20R7+wIbxJX4L1/obfl4Q0bnopDgugqq\n6BJ0KFLcwV4JFL90CQH0okCDfDDFFneQf8W5wz+AeVBWpaMAV2NsKtmVjSZsavvU0MpnGxdc/YMh\n7nHXQDOGFmJEon24fkOgxN/4E3RmdoxkdSdCzyncnxV+RgVZnXR5lUa1iWWPoTAw/JgA8Ylxkg9h\n1n3VtiKHMIIRviROoG9FNQqclMtZC/V/GWoodAyMvQMCKe2meiZh8c5HsuxPOOkS5GLIQdlDjjbG\nl4Qh3he1TvlDXetQnOPK5Eu8W8WJYAhxEfN14wCGrL+Z2QtT30Yef/cvKkTSmcAbXgQdEbNprta3\n6dalL1GGiCAoI/rwwMF6z5KXLGgQ0EBbyiEcnefBpJ6ACT3oygRTnre8yKtMxJBMcTHHl7jaqFZC\nOwTDWb7bRVsDODmwFNrTTNk3eyWbO2XruoQClKEAv2ojXCr09tLsybCIuBGA27I3Q/TU+st7ZWu3\nQqZqLeYyDotc8tGpzwJCQO7Edak+xjO4Lrq8L4BcBX6uoVqEK24NChDz2hqrYkXesiRuQeEzyPpA\nUFVOzoFtzxWpv9bbefTe/mMt1vfaXUE9yj3+mHxhKo89OJ60nmSi6Ub86TspFPxkyGbQih9JjY+9\np6gAwVN/G7nA0lgc2wOsMlmhRdUjow9dBM0zVWdCcjKuu5vWckckmjuYpUjz8VKLuKtxeQ+n7mAs\npOYKx26zLp1dVUbfJd4D5E5qJrU7T5wlWJT0FOTx0XWIW8fvZml2rkn2Lffn+kGaIogHVE59oMM7\njBIh6nR8Op32mK0SnoNLm6Vjh7oBcpt32bAz5oXkD9yxtn6yeCGTyktpl+137ZYgOl5BQNqJjoks\n0SAzvKXSk/LCDOGRoom2vo8kvDd/+5okkjWreRNjU4MAMD92Ppoi7hTox6jfoYPbYUytjg4PzsyQ\no9C0+hxoD2YvDQyM0D5H63xC4R8YumnNc5avK7mz2WmlUsVkwFEnPJ92AUZVlGCgHKspJ1RMWVCc\nL6qojKjPCGcR314Mg+8bA2uuHOwSscBTT3rmzjEdjxHjQsPh+jIdbrwLyowT316Wj6s4BUCuIxCr\nSDdguaE0tdYZsGPyc8BXwBiXUSJII01qCqE/YODPMRiopm7Or077YFbgIVNtLqQAEt3iFYpDPviG\nloiH19H7tSg7Oa5yg75LUicWPtazlYIvrTqgYCBs1kpxe60PaUwJAZK60utY5X5sOlBknN7OCE21\n1FB715D1VSMxmzLyy2fFpTEOz6ecfQnZ0Wjv/izYkJqpfeF3603JkhKrRQpjipLHngVq2eeMkr/e\n584AyoES5Z5GhDibQ3RCHy94ALEXjQR2qKtKohXB1ulpd+Q2v6tzqMxZ3rFGdPHDUiLNTFRNw5GL\nEUXb1hQ25yYn6hZ34hjzFli5OU9bxAqqXJ5YJ9yewLTElBzOVsHI66+UG9ozdPVEvFlzVsGCKh7e\n5dVD6y+PYfvDfEF5tGimXdmXAq3PuqmvXXIjxW5zKfyZHGAYhAgFsw+yPuFovmLzRauYvQfx6Dvc\ntSW0m5Itf8NezBoKZaHgTZt8e6q5OUTo+ygk+3ArK8TVbpjKhlaxl5qBOTg/kbI49txLKnPEa74y\nUY/qzdXVC/JP3hY50Aze0Xs3vVIrb9Vq4nn4ArxlwM+jjyBlUAOLSeodWPUiYHKwTo6X+HyLXLy7\ncxmXvaYkmYJROTPEde/VqGce4ShkSLdbe3jciE3fhtGC0+aItqkk8AwOulr9fBRCO8qOT2iyLndR\n2TlI3tzekDFnI+rdouHxOcd3WnwlX4Kfpm770aHkC7dB/u4iXbJvU0HumG2K6LxbjOehEJue7neT\nazsclNR1X3rqokGfsaPMS2k4Cuaam91GLFtokjULTzBLw0LffO0+tIxpI1iYW44kKjJK7C7y6KmU\n3r2TLTUn/Tc5ucLn0KSaOcp+LCUdQ0GhCdwK2y3LJgFg8nUU2ckyEclAyv+oYqGaiLGV5stCeBb9\nIweMYnf14r3uQJhSOs4SuPEPT7iUDo8Xi6pMcN2JUcB3ZX5XXSfdKGp8gSuQ9oFdSQk0RAMTL8Je\nvhwEkqfgtZM8MzVHwXdvs4db3uirZq32s1NPX09LAio2MrwKfYlOlrLNV4Z6KyDWz50JSssj3EZZ\nqfm41P4RkDa9ZibXT7svjo9QurMcc2vYCsk71oO3i3natkud6ZwJEeoilnz1C3MriWxV6VHKBPJZ\nGSfUr88urC7Oq/n7yWRCRq4XZzhYHFKzb3cs2xPSRytm6BhtSsLOjcjdb8P7b03VDEa/k+AYHb6c\n3O4uZgL6h58vcj3edmBDgLuNcL8oQZcd8CO+0OP7fEIjEGlwcZ+6bzhId+o0hC4WUuoNpL+tyiPj\nX6uzRCAH2YRkwDZtY4eu5HewQO2YvWz7/3FUmItPrUuQKB/jWM3qPunUTt1mGca+qDd4vfjjeSh2\nKlgmtKMvaqVh/cCO/+h/gL7A9VIp9PZhMY2iyADO93VqJN19l4mXMqEGCoAllLvaC7eK4xPpUmAL\nDj1Z0fp2XuHEB0NtOyYP30PE3UK6v14onzmhTxp7GnTY6sXOPCrrSlChmu/wmW9UV3z8hWhmDYFv\nf8JgSidDsIkIOAS4qcSWekRn2hCuWw3sQzZj1Mgy8cXUl3Fx47GcamuqcOWbuIN1LyHQQhDO2r4M\nYUdPpJBBWgB9r21svnnWIEpxuoH62skNcDc+5Z3TdJ7vYCe0Y6EFDMC4KdaAh42gKnlhwMt+S1Zl\nB/+NzHq+MH1gRUpjNNgMdbZo0x8mquOclYm8uEPCxXo5REKVOYwjmH0Z/vKhdQgUYMojvXqEBkmU\nThjTIogzWzVvMkk8OY4kXXda9wKgyQs1dk/Mq50hCVIuOmZ3m7wy41cWXEt2qurkedpVQniTOiS3\n2ydu6ceHG7KnRM3CZquFCWSAH2Ba0AMEmy7gpjg2eARewDcc8XI6+P3POaVP2jKbCRBgAakSPrym\nVVe5zGXmHkRoHRrAFgIdhB96JnOyfXsYo+JrGM2J3pAckFS6GyKmipLoBak7BUCL35zIfARhQBVK\nknXO3OPst/ss5A5Q8jloyI3p2AoME1/WU3kNW6iWFQtjsL9924BSYIxjhbvJ3jLEz/wkE3md7rpb\nS4PwXEoLUvylrLI4aR0Du4TrT7xOUUTWhVBByiRxVXK1qP9l2QavZ40tW4KDYP7eXesojGAhujrt\nNi/FihDs6mKkrH/AOMHRG6RW7rm72IsR0OdgX8/A0ePKOZnxvrZ1QIWSVOAJRVx5n0ntwXPyLvW5\n/OkrY3zEOhDnG1PS1lfGG4SWudcsffj2G/Z2xjM+z2jmEwhdsaeSbyg0wSrXE4UClb4Ozyi8yMQZ\nYxBQcI+dEgz/ABKBLCMudOLmIjPqO0ZnOu2DSSj5HxZR32RHJZVMyUByUXzGJksXkO+9q8V1mSuS\niCVkmbCBTRHZL3D8lkT0WqqANEXzwNVy0BzGv+wjOi1jeWnFs3RFggzfpTJFNloXMpzZ6K47Suxj\nNdtWFYbK8YrikLOfNqxYOrCDr0zESSDNAGGL34KuB3CJOqFRgJTi5rKqVNWWqFzeu16xFnvVJLnz\nG5LuWuIiDSfcs9XQ+49k9lz+0CdfJ4T2AUwdUolIzI155TM4bW/pvMlw2CMWWMOchm9knlZqG+bv\ndc9+tD/9oebQf4FtPukL7SQf+ZP8HLM8C5BJApEg2G80c4GeyLVwYZx4NuFgjirxkOwUKafjBrC3\nu5v43Hk5ozfWoxBp9SHz5sYmiKtGSUrwOcAE4s35rnYbl5JtHFOuvYyOyt9WzqUCoVSsnxkChzO1\n3dAL22jB5KFctev3cr/9pin2TmKqTa6MQEOurv0mqr3XqnLcU+glQqOlF3OFZ0pcldA25htb53Vs\nqwOCI5ltOigQJJHZXW//gKlRe5mcm3s9TnoBL44YIf1PoX2zz92Q5XeYnXvXRS/G19nG7nH+NCR5\ncf1brWaGvJO6N+tFquk7mpMQArGF0etn5fRSF2tJAmxA40P70Vb0qp+KJfv2KmzYGPza/QYz+eO6\nfTNZTN8orHenyTt9n+KdmO+l85yxNpnWi0mNMF4yGcWikPjJnNV2OJiOPDBN0JH4b7RMOQHTkKzW\n5cQHRWAeQSdBOahCDqmtS+Ofl+GRS8GxtmDxUnYsWx7doFkRLl7ygvaq4Mh20uz+Zrea3tSnjbaE\n1Aj6t2m7WnMXFZsCxaHX9JdZjuzDuJxn2LU4wzNdYZstjaPO6WOwv8aWndU11t1hij/1yyJhJCiV\nJDl2/JasCiu2FLBh9uuSXacHhq4GfRjG/itHLmtxs9jrYDE2tsBbvSKHQg+MnWqaU187qLt/Bn9y\nM9sK/lp+Ow90uwBWjTabFoktTOg87v66ezJkJCkdgEwFwRbqvRbbS+0b6IjWLRYW4ggW5aU7Z5G0\nybAP982F5Pn+fUj5gPpQ4MxAOt5eipoDdaff0JRcH3bvTurrjeXKhOE6baoNr64BaeZ6TItwn3iE\nWlujwQGiRsrgpWoMSnU/edQ7uPyoMGuC7O+E818FK+Eit1MdCkHX11BUbn7ehDIc1qoNhl4oETLu\nLetmYi/htDmWDeuWg4YmvOER2OuO9YSEdYk4Q07dLl2T+L0XsvESzMfCZpux435rUaDWcWHCWqmA\nL5VZ0KYs13Wt7K1+ZAv4THOlM/nCst1TS0Z8cRVItoVdU8uU0b71uo9JQptbXFt8Z1UBfjeEGnmD\nHMiMeN56vqWuFzkzCHvbHCmrc3eBsIy2Gnjlr5iAEFNgA2jsf63WQWvsaKNBTfINOFFJpvjTr+t1\nquBKQ1NJHDvJ7/2sfDRduk+gFJGN1C4hdKdZcQIVxlbfPVLDCboM6gi0eFwLzqq6XhLGEsuz2KEA\nuc6TKHVOlgPW6+m/n3AZNXEfG9HN0yANBdi85SrUiuNoP9MubJQklxvGi1iPM2CciPHMkuIlQsyA\nvZVqJDFBbzzjIAcf7MKTtiaDbx7F5PlEg+imJqFTaF6I2oxNQW1VHbaqVihAGnsBWXaeLOmiKVqd\nbg47F8mKAH/xHy6+cjlUajEvKHHadWRj0eoW+bYLQ39J3D5It4B4GxcY8NOudtFwahjZpdK90so7\nuYqcjwjhCviHUQWp8gG9vo4R5CSFLc4aBbYTHE4TUPHqOkzGMXYfZJ5fqZWV/aY6j9hVs/WNk2S+\nfHWH4P6HKN4YE7oKi7pe7bRLr1Q7yGdB9ckyjobUMlgXJy6cPTEyLmdBZdlhPvh2O19FCv+Rx0vv\nSYwP8m2n4b3HnPBikEYA7ISrjDGUl4nLk98YGDaSGjw9qlKDw/5e5W4JUCSsjlrk/cmJE35eJRCb\nLKwTAEFI2wcg17o8vuG8qaAnAjxPIYGlVOc9qLS0e7mqVPa/mR65vsHdl4cGBtg7HvnIKH3RFzYG\nZVclK1wVXJcdnbuJKwbk7rPNzB06utuDdz84QPcMsbLNR1gQ0FccuM+rqT2guaRDrxO57M4lXpWe\nigBziRSrwyVnmgJ3vQCUfWAFQ3DZr0u/Bp4SHZbQJ5wFgBPV+xJUKnm3P2AYee7+Ag4EhqfIDF7t\n7qMf1OpUI2u9fKF/If/JNYAKQbPmOBQ8brvUak90tZBzGveOBVe8+P+Xv+0zMmgw5ueiba5r6f/d\n16+UX65a53KlWDGiz/Df9UarDN2n1X1F4juWK0mWc3vNKXNJ7cGflUW/kamwRrqF9KdvMINmozFX\nKdHCC2D3WqSffDu9mWhd8SQ8r5O78UOP75hPqL6yEBTLeGZ86i49PRl4E4VRMt0I8+ClFrNkIODv\nvFRsm7kyHLy6u+vI1Wm7dLKZI/sqyUhHbrR4OJsVob7FtreHSvLuz4ZcGKmRfhQpxdQAqHchasga\n7fzI62HuZymf8Scw2nEP3zL9Pl//EzHqq9+tSjS2Hn/YTeTIY+om+sd4plY6YB9CEg3MY6boegrN\nKDxm8fCFmuxO7wFacr3WyX1h4GLWrbdwssJqvq4iX6iYvsbOky94ZSNLatLhwe4HyJ1R/w169Lrd\n6Nj6TB+qkgLNMRx8+CoKrjb3Mv53r30MZMM5DSi8dsuFnrb0K5nmrbxjESUymOHjWk95VsNfpEht\nwcyTGe7i+AgnqgcfOV92v/WY9sFt8jpOO5ut54sRh9uqDLgBQ1xYgbmckiMhCLEpnVosEOqfcDAE\n6h0QhjJkYmtiInOQD0jUfjlwff50DnvpxxAWZHET0HYxDS8j+5E41mGekhtivagn8RltgXMuQEoo\nanjZVw+prqIioJIKRLMhKZDae4X+VitKbsRcvIpU2h/3hOs48ii3C9sokqM2rqpT6sV7SQDwH1QS\n4HNRGVK0EYdEu0LGNxo16onxozZMswFkN3PEaK/Fi5KjbdZDAsG7ZTATFIlqTeapegQ/Pnk7ZSk1\n3+kneixW/cVA37J13DRQ5R83bxbeBYrbjXkAWuw9AsebtiER3HxA4zNJVkIhcRDPZvmevEcokevq\nAeSpYqchDIyCLgijOe62uEmvZyj4+uiFzVg64sPxpc8uAdf/hVMFj/Px/xKYoQDiAfVfdcgQz+U2\nA/vVtjPaBrxPfBCtJPd8AgYw+MXUE72gExXk7Dg26rz+MHabE52lIiOK12cnuDFKit7ZkLgtD5+Q\nyYQGTM/Pj4m/S7RxG/LY26jlA9FgLLNEssKYENb8Tz/r/pW2sxqqlccL2Tyr1Oo3BwmEsxWY+yFH\n3gLjnJKUm/JLRjVxe6JKG+s0d0QMMyf+ikWqWM+jmDRm0T0CD4JntogZfFfNH85QscgwSLaiRUMj\niMn9aJ24MXR4K3KsrsYF5C6mpviEhwYU0dSaeyDHHpREzzn+WzE6UEnl+S3jQ6zkobjZC49uEfLt\nb0wjc2GAkNZxIhf+mEIOISukoMq3ja3nXO/9QrYmDRHyW/i4k6aPunZOg3yb4mNLJd5FqS2fFPAS\nB05SilXUnBt5Azt4+CaW9DdOsXEc46XM0OwOk8ZvmHAKXaJUD0hqV5bCMIXSse+jbKrv2f2fSKjp\nMYgvn7nCHNiosPhu5IH54NTsX8onChAyCZqeQslpm31SVMQixMqEt2sjMfLMiPNiLjzEyO+Eb5fP\nsqM/XK+EJS8fftezBNVi2WHAVNrf1hBYDqw/vXq9B2sBP7HJfOCmtMBTX0I9jyyIc+uSsW3DghTB\nx3NrhJU1Z0CIefGmZZvxH4m0NuZ96HHrPZ053RQgMmpR4g8x2RXmydEVHavV1QNs2u+fw/rrKF1V\nABiURNW0pdOTCFLlDn7uXGp+i7PKLi1efdPqDQYxTRaXVPuJLiW+sF+gghzCecEhgsmBrXNeBeKv\n7vbiBMZ2G/tjeE9BskqBNxAOObEHR7O6y7zNeoXUu5d4ERJ0JAnfDs3PSXhLf8KZQ/PfGnuAiJpS\ncWY/PQboMsadQufRckwbw3yG4I4QNwM52L/F9++34CWrjruviEsa9QCRpAvIBfuemzGpwwMouK4O\nUAn9R+G/4hBO4KYHm7jTS7e0Ss/6zq4ubmQZVn5mAdA63v52snY+AHHt1MY1dbqsnHZf8sAi22Oo\nTPJ8RB2ZWgX8YrWaInIvyjpoxwoAi4mtYhhTIv6epRccCXd98FE0MVZ+/4JM1b/jEx14MircPk/Z\nVkm1FxGB1FA/PFcdGp/6tWKbvZNzhveEnwsxahBpwoImEbSP9MYf+DcjOGPuccJKphzD1hvjvDGS\nIt91fuTy8RKxhLeCG7Cz7y35p3WAFfzTAyiC4mFh0jRusDQnlOgc/RKbTzS8OcOwT8ckieFoWPD7\n8knkuZ1n0H1PfM2+scEgE82Uy62+Mbr+pDn8TGD5vvzXg7aKO/FXwwPGOoRbuadJ7EG9pxpmqWDJ\nVyeYP9JArvFk05KYDZqyW544xMjsmtxeGKR6hGrhuh6tkzh608w2GZ2H3caU8AN4dDETDWguYuQL\nywqv7KP3DeWY6T5K53Jb076nXjgwAP7Ia/J8kNQWbk2O4mkDiaC6emokKtLBOkC1pyAFQo1il/60\nATkCVvyqO432auAPfucq1wqw9Pi9xl4FXO5FTtHg2la1Bsffg5YdmMkv4tD3RJJWdxT04m6JprmF\nYphcskHenjaB4sx44R+M3fJb55dfp+a89TxL6s1rsT60Z5RJ3rkHm2pYc4zuUV30OCJzuLKH2sbX\nzMxDEA/l6JlxQfjEIgVv6yYQUbcTnMXkEkZ7jvUpJrvojwxzEn97eDh+WcHWajoC6HcgI2DzA/Rc\nawkS3Ni/YwfQh61WQmVQUwaY13B1OViGEBSZdYdMv8heINOteDihZkAWCZ5o7b+WNKaDT3haRXoz\nG0O7rat1pZtNtLNUYEy7BDb0Hr7txsliP47SOMOdZ/To4FgXyKf048YbZ4YjpA/NxnwhmUbvCAme\nPoyJk+EC0+PtpSlevnHYjnCQ3/ErggIPFR9EZs/LB6jNvNnqQpqr6zHvk/3bWmbFPadt2ra8y8Ne\nxAVUFL+g/QApKLXGR6msVJqobUgOLUrIlSbJijYTyiJP427ZQzYqKQCaIwY5xmPl02sCIxpmJ510\nmugVZPD5u0eHTUAl9zGuwRqsnWOMzacKvz1PSFGwASdGWZ9NJ0qBT7foAHbqPI7S4oc3MgLB4TQf\nVHMFkxThvd2LSzAX0HS34QafsJphKGXvJ+UvXlID1I7uLbty2hdaARuXPndySZIDHxrdQEMwx8E9\n7HaNa/fYq5xdceqBR4koAPSyO2LWN5M32tyfaYAgitRp6D3OOFelUobC5Qh3rFVP+T4ixIzIhO2C\nRYNIzuRzixJOUH6DKWPTatxQdWiIhiuCCe6c60+G96a4tCj4YWPlheToeo1PWHG46fj6M7vWYexl\nBMUWiY4d20AuMyo/kbWf7r7uYC7Ifdolhi/L1sqfUaLOx0eDWyfgqylgMcXncI7jLwp5+ONLDsRB\nlbqMNVOKD56441EwBXdir7IzEgXruYQmZHDB7ct6coaQqYgSgZgjwQtdhBim0Oz+9pu6ej2syBHw\ndgnLSL4DFAm7/v7e7k50ek0zBBHcjGAbHBxzAIkNASMscIKIyVL7BFSIbYT3FgJiH3atIyKZwsP6\nFeugOU2+rZS1wVNMZnrmHA0cvCEoEUk4GSqNBM3EUMxK9WVi3v7OaoGeUPEe8Zl1jp368/9YWEzk\nM5IDlkPExJ9SAwMEZ42Q4BmVufJvIcD2DN3nnOx6B3/eFSCSOeXMBQ4dcNWEMDoL2KraHYJ4LB3o\nUimuuwTaeGW5u2gbMb513KITOcNmVrpc/EanLWN0zwXPrj9V1EEO0HMm0K5bBH5ApKtOaK7uonwg\nSR/9tK4+OqJS6ClXFIeDuo+5fCF94XORZo2yYKgsUbxPcG129lqoFNO7thILU/mnrZsRnbyGFlpd\nKCmDsUgSGBIwoXRgVeTrN9JSDtD05gXQ3vIp9W1uwcPIxd1v/NhIUWeSn1LvfBX0lIyu+46LLRRE\ndOLH8fB2JInUHzDPmXHoDU44440Tjj1fugKGIaMdbMvAK6uPjCoVnZjmYtbMjd7byTNMGpQ/7uCk\n9+xaujmvMC54Ggrz7osoBYb0Rju0k08heg9/DGMIq1FWpyzMbvMcO1GZMTXulcIHkAOVoiovC51P\nZMZd+MsPJg3QKcF/nl/7FGdt3MCY377jsc8h0ZHtAxqz6/wgp5RzwB0xWqzXp3szGFOkaPhLUIvH\nF/h/8V/nHwUZlTfwPssDG5inLvF4+JJfDB+MojNefH5Fyy0DdPQDXy+sydMkoapqG1W7jQYZmwJY\nq+cxVFoz3MyT7Tlv2HPB0AhztNN3tPjAHQ5O50xvMUCromnRNCwglbUhfYg7W6rrCm9Fr6x6dDBB\nEI8tmcCO5YjUgNc7Dao8WBr0oBagHORtguUixyEkeeY2yqktcxN+M/TPiBryaW9rBRqPSE4j9qvc\ntzhMN57brYH1rB1IRFTW7efxXwd4HUSkD7Go+5MV5Ha0e4PMzoLX2bl4R4bXsagaFHxdbmLsKueb\ncLUWVn92S7yzdkVOx700suHGnNTNygc2xp5Q3+f8fbOl+RaPCaI8e/HYOPdESiiIZyVFExjZSYtU\nO+obWMBB1n602uODewAxp4LF6iVW5c3763SfnpKOdn2tyWIs74KApVN4eNBmxFS62eejWg/O8NPt\nq2mR3P9Wrbwv2Jk4soISbVtirNZ+bIEVUZEqRKgdm8zmIQsZi70U/ZGx5lUc4NaBErxT8QU85eQL\npSLsxqFZZcmgg+dVH/0egdEgqavQsVmmQngIJc6sa3sZHj2GZs9oVBdzRn7JySHmhWbVJk8uqnhh\n1tqpkMwkAwfIovwBreJF/t+ijuu+hs65rx52slzNtpHsMj1lXfcMAfMjTVkUh7ufADb6oJm7MnA6\nUMa+Bn6o2Gq4pZKTQ7WwB+l+jc6M4/29S2Hqe4gu1t0vnD+mDnP8smzlGP9/Rr8kXsJXbJDO5/z1\ndK/P0Prf6W2+H9uXVQK+5w9tRFb2AKcnEYBSptvvpcrB08fpAowJPsRlQlRtGEXW3/RdskH3doIG\nZyJ9g9rRxXk0G4TPqUZrRH52FqQ2DhzgSwDqgEQpKPnXudnLe7svUI6b+5MwpieN7IZwftM/ncEG\nHwO5AfzWBdGrI8j3fSCvoYMh8dFCOXS+NOvW38mU1l22NLsKVk1el3MjQs12BMLHtGA+bl2C3Uxb\nj+iSAUUCax22FrRCq1ptPXLcyVKFYSFnjOokRT3NCU+tY89sGjnetQAbfe+ynV2K+JZep95pcHOv\nMdQJUcDZrGAXk0pP19B1Bd67mi1WYqGUryMTYfQHx+rXoV0pXlijvlcyXkK5z4i07S7ADWnXsc2f\nK5S9TT5PjWoFeA2yyc0X0Ili6gzM5ofnuuzsvtY9Tfr1tqwVFPLG8iCxTJ6v0aJtdUKsf5A4IXWz\npcyiYUSDgDW0z7s5gEhJJzwitZjM0Knpt8OMezr8vhHPJ5xKImQ3+mrcw53/2ncFcXjnR/DpduUf\nxLjPFdwvsWBufdzftmk+O9qnuFxhb7msfcrsBvBiAy51eM/la70C7HupFhHuL+IlvqlL7PpjLsxt\ngqBktAx+Gpnpz3zK9fEN86O4q7xdUXMKtfQmiNIMudDyINJ4O9zH5h6MM5f1rfzkmt9gWnmXGjPT\nFWasD6dgLQqqK+BVBdU+4w1b1DYYZLx1pt4KBLuJrPNNn7oFF73ef6+rYWzL/x6oWQ5Yf70j6JKu\n7JyhxZCq4pFwW/hvBRXcXmKYhcAqLo2S9lSX79JiM1hPkRL1l8Y2ltbsaIJbFeMIb5uw3egZgGPq\nP9Y+hLrSoq/G5IWdA4G5MB0vJcVsU5hZy1igaspRxpLL85oKf4prkGvMJu4ORjYuJ3/C3Bd0RzeW\nBnXwDbH24TYneN0aKM+xLqZ6c6qwwXppRMsssd5x/VcRRCaJqD55/dNPtsvY4Vho4mY6IF2Poqd5\nNXh4ypBi4C4Q+ZNPK9deLm/8Zp4q3aTKvQU5RrfD3DpdjVy6HfvbFsqk0hnRXHqjv/zeviGqwchj\nAHtZplMK3Da6OCyJLPc11SV3U7fpnDwfNfww2Ub1mTxwV8RFlk/cf0HkQ3k22XVZjpmRoBwwMEQL\nwskacMod7ny04a79wSLZcexNrzLLmIX8Tvlc4cY8buNrrgJSSi49saEJ4tLStW74H2gQ3cv/JTXR\nuOXv0BpTffTZgaSShm95QJ2UCWnlT0uCFajs4gD+xZ820L39IO0mNQqUkezs6XSEj96B8dEKRLtK\nSHEFHruNTGn5bHkuJ29JAk3afjcb6WpkbZSbrusD5TEItXE/qw9OTXDCM6x56GjXicLGHxlznnTa\nxiWZgrcvnPszb1D5rEoyHCYF7di/Tod1OKDQp4de5w7QmeQXi7G2K7Dnv7RcSf2uZf0ab27vWJut\nq/DuDWTkoXZ9XwJ+cTByGrV6VHd4H/kmz2kqLSXu3fLguceXiagRGx1JnW9R2fm1s9hfF9/MrIVj\nUkraJ8y4ihBGdQ++U8Miqg/jf1OqqPjkUnIEEYB1x4bZ7TknVJcnC14iNQXKJ2TTjlqAuv02rGU7\ndUAnIjRVSw6jJgweTOasTuzrL94Z8VUbqrggvA3Ico85FdYWGVZj+b75l0m+Ql/wXS5LrdCbLdKe\nftjsz6/gWRi1yHeaiTSu+yLgvDhbaqvIQ64tdenKZgdx7tRxvdHmjuchDEoCfw88PICJfDjW/XqT\nrxU/AxP7BkKEUFKFY4jkFNr6lmVGw7KT52Vj/yyA+j3ca2C1+EQojizobl/UagpEoCmL4AfWBI2z\n0494YwpD6sHZZLRsSZQBQJB7M4z598fCs4CVC9aiULeWTOzWhXyTPqyW0vKRumgO9hwFrfCqaa+i\nYfGZHnMwrOhDwV93dKvJkdN6Twam6nMVAot0BolI8ShWwCXZ1wdVxazOBbA/xQ2xsavBxuMIRNbQ\nBy0EIHLXdtFulppkbE7b5y9S1qU45ADor1Co+hChDJMlaNcdQfaRxQD3eWg/F2GnXYg5CldqwvwS\nMQTkpj8h0SSz8amZPqiFcXSfQPrJkpHZUi4wyE+3TdjoQ4HQL87Fir7r6+tZrE9P3GrRbKoFAssu\nLbE4htWrucuWacX+XszAD2sI/TtFVHjOnI2altV2XSKMvfSZ3OJYf5iPtL0oHGN/QllxQ8HsHCuH\nCMBLBbRP2xoxxk1EVxj/G2W740CKKJdHJkufZpOHfHIkQpnLcaYknVv4M1xG84P/F+TJ4/2MzRgz\nCjlrHvs8WYpVVIElkGQn8ruYsK9cmTvm6RlAxaFTGBUE8X9qy9eoZCEH9jfuHNleHb16mzjH5kIM\n3jyrxbpAYxnC0sO2pR47dsXz/zs2vnSL+QoaDvuu+c+UoounaD+OCulESmPlaORe4mUU9FlZoniV\n1zc9a5h7RbR6hdwpavszyV3YLnrp2MP/+0mp8cAKL3uOI0mdswVjmascffEF2T6ba8Isq/Tljgrj\nqnaCZ7rQFCIzDrbOLvdfHDC1CZoLz0RtGWSJ+i8DltwUGugvSrjxrF7xFOJCNPyO+V5hK/6FnKR1\nRDqnkI6KTrViI8I8nj05z4cHCTFnywQ+C3RhzHSQtKHrHwi4spVkMGVzV92mQ/zS28kF1XkX5HoB\nJ+ZtWQIr9dPuMS9NFb9JfQST78R8hhG80dP7tAn+ZUDBCzOOykPVW94Sw7ARtg7xcZ09hVHQQ/Eu\nnDNecINOG07ECp8DJNtkzg8e/uKU7+yz20hk3bZPC2lnapHUd9ZCDipVCid3Pj9P3VeOBOZUbcNt\njWQsBZ0AwcXP5r/0dFWjsMy4ejDpcUhDw2LeLtz65lF71U/8Tffg+NaTTW4NtWnBWoNMUrIy8M90\nT99vzL0pC0k8nEkgVz8GtExyvLgoujZk0VkXDo6QF0phUw7vwvY9+rX4eBnUyDf6gMikm314Gfjd\nO7hb7X/voxFjMkEtKXKUc8tRLvnguumuLRJ9oy4B9nsFfnoBlLY57RR3a/ll8b8w9YQjM78J6W7s\nyOzeSBkHeCnWuaO5eVyEm20DgMMjKtOf1939EMmYwQsKwO2VD//fGDFdqnGq2rF1hBsmUl1YRKPr\nFISmFmLgNZUnJpKESipSJqGF8y48WCCscb8NSePK3ZIrK+Gc5aquFHAi1SxKIvnqYnIPuCEpZZ8c\nJ9dTfuumorXG2Z/iUdqdYcGTvYJFzQ/P3uSkgC9bLPzkm35uJ0Nk0Q5PYZggqDRxXK8fd8p03fah\n6PwDz6wX5K/5sJoqFThvZgYgI9dpwL5KwG9SlDUJclSSGMmrjf1YgDapUjE3Gncim5fYr+5MUKqz\nUikJ8MiYB7eSX+rBLYxVtEZNakYI2dXRLfnaUXVI12121ZbtzYvEyb4hED3/RQyQqTjEAVFRuhp+\nIMmH27H5nT7lA7Pr1di9c5cOX/MhZNTeV/SWrsjGMEhbpUHKezy6rX5oBZySjhpz5tph3yLQ5EsN\noLp+1J+eZkrMJKmpGcv1J953jjDE3sVY0+m4bKwqZLFUKBhV6SiFu0RaujZo7V2oiuMbPkear+de\nkZ1uMN8lU50L0/sacHcNoHw8S21j85MMCAEbKBVKdJLkKKpfks3OmFw6IJN71hoOK4/nc4uJM80q\nia1IcdaPc4Pd9jS0QyVNrAPhLu5fF2M/0rhGGNd7kSoF8EYOahSV84H36bN2OJ+JUv/J61picdyy\nabfj27Rm8Af+7/66UcPi5hDdvz9wxuLx14OnQy22/zkCkNoSQyvzuJGt+XO6D0fNJLqmazDd1e6h\nYR0OaOch+tWM7KqXHe+eh4oAaQ1QnUAob1SLGzV4DUcg6jJvnAeKVYs6ZOG89ZCY9RcjI18MQFBq\nGtgNhnwE8vzFRBuAqzHN3YTDo2GRtPZ7mAOb8zwPywBiFvHyX2tir3bFsqrFq1Z5DXBvbFBZ77iJ\n6MCjiFfsejVauDYmGmQeUZDezgJpqO0CKaWQ+2mAUmKo4qtfEg798nHyeV6UwmPfQvtiI+SEykVq\nVRyAyiheJJBatjxb/SmShGfcWuhf7frRzxTKfXU57x6UrypZApCDklzH9V3pnEEAa0T8GDknoLby\nyG4HmlT2hKPlElyywMQD/OVtli0f+/7R6jRu1eu9OjUXiMnYDi1oXdDQ64QngKqKzgjGo7oi1nHn\nQsW/8Ph6M/42b2PRaNv42bDkD6BQIVxm2zC5n3IHPV2mnkJD60FruIRGtLg+ZgahbROFIT2nKscL\nEc37OuCX818Ajjog9l3DBEDOeMmwjYqZIeTE1dTrKTALJTXnLOKw76R0YM74Wms/D5C2q43AquUh\nSo3LlXNFPKV94lvnlfB0QXaN3z2/E5Sr1EiWLujg5tMKMoxysSLLmHZXEKhdKABm4mJs18UhOFJh\nf+CFZ1j/IIte6UgDRr1Gu9TF0/cEDDJ7h3UtYAlD7xEati9rBG7/JgLjuGXe0nFfKWS7rlbk9Vze\nGOKUzTOZ7XK1Amc2uU0wRx1L+y0nD0Iwgc3eZYjtVDEufKNhe/eM39cIhaCcjMNLEoqinIEVogbe\nfek6qouDY8u2Jb3NKaRLsW7ZTgi9/LNA29x/ONC124B1kVISIIsvTsnRD7WSrgBnZ/BQo837VtWf\nHf2U8rHxbnfvzZyIzHa0iH6dQLGuRsyFRZR4t1AmMNqeKpmt5a1pJ4f+5KAgwlOGK0qDSiYQMgl/\ncI6ZYTUdDXUWNMHAs4UNEHY/CNUTfPORyYTf89y9/PymH7L4K0EGqxRxHaJrOnLwwzj9azZ7MH/D\nz20/NhfYJbE9/zWMkyBVNfMTGTQ9rU6d91frCkXKwV4TQ9Wztbrzg5ATAV53ecHvkkcKzcAMu8eX\n7wwhZ8NgyU2jWOQKZptXlkQglmwZ0OloGM6bm2hzlG1dTzIjEcXFTzP2/Ls/cSGr1yE5XAVHPNEi\n20D6axUSPIrFkuxO6h7JBV/VQA0fE0Z3n5ruR7XreuwbFGeTqlE6x3+sn620FJ6wk5GMHfWpdW1f\n6olWrLobLpnp7WJ22lkofJ1I2env0AGhnHVZxDfpveBW6TIeK7si8ExVr/irVX9xwRhcEpiZa7SU\nFk4arO9DQQjoY5Pwsocrvbo8SOmsbXkpcFSqbnmEZHYKYIHmf50S1IKs7YPZCGUUyZ1uAh5hQ821\nLmauY9+xQk2w4Vexe3Pda6anx04ZKpByfmHaVKp0St5QPkc46aSsHOEUnHA/p1HRhQPFoDFJJ1xz\n+auXu8o7bbz9tE4qWASXT5rJ40B4I2mgkRPIxum2iNxo2GHKyDlf0gn0hK9g0WKFyLFfnYt7ja79\nAKhpPlIhAh04doOZz5NApdD5bgAYNbKIhQpoWQUAUoQSYRzr/2PvebRgwI+r4bMgpY7049csGkNV\nLGKgsYh0QcoJrSRKId4Hw5D+vaxOPGX4/LJWzfk2+bl0qMYaB53Xn3UfLSGmgy4XdHzLD84wqVkO\nTaULoifZ8nVq1fWpPCIdJTyGd+He1b0RV6xdYjU9rkWBVrDq26JKQlNtGn8SenvuiRf8/irsL+z5\nyeR8DtTAoSnJc4GJ0gmNBK0kZ5iclQWw9/hg7ZUAPGOOUuskN7+Gh9La2sXo9df5OQ1NNVk0nGwH\nCVyXwxCUkJjeMUjPM01r8Q+7iWUOu3fK+VWXg7pDqxlamdUCfOm93gT0dlqwSCgf1XtUIVU8DvTd\nmjGvPVY2TsdEbjbCQlNSF51gs8FdUpXl7IJskIK0B3yxvJVyuX9+M6JeiJT+rXqZ5yOLK3qdw29b\nlCd2EFpWEwtQ86ILWzIDxHICNEiKkBv4JxlAffK+o9oYT8NaQemWeHe/tNxpGRae4CBzYe+Tf3v5\nmuLYy/diTrXUrgENBLz8yvgtpLn9T/odcq8mKtxI265AHE2a3sB6cYwN71V/DB12rdHtyWXxpMoD\nXJcV3LZrqiyBOK7/uWIhRYyoq4yNYMp53mJw1P5kSL1wLTBUNgWd3Gm+Lsg112MrAH6LQPMviyP7\nhaPt6zNSAZXwxKp4Fpmf8GUkyri/GxY5p17gCeAaiu08uVG88b2k8qBtDdjMzehykIfdUOqYmN6G\nYbww259H52PviooegckivJya+Y8hsr0Xtu2LizWy68dSn9W9jJSx1BEunMqpg0GOUuWtv9E2jNjB\nQJc1+x/98FrA+U6bjJ3AqfIVfGRpedxEI3Yu5KC1y3rGCF2PeFPTNxg8n25aKVlkkBv9FBIJm0UY\nHEvl50m+XsJrXrnFgYaXUAOdkrSj8vYpureSd1RjlFfHj5qlhLOUS3AlXtl6kLt16+4NAGwMgExS\nmYrOWpTp+TQ7OncpqMMEt9ENBIEKaywdSZiSBMLDFF8gAAJct/N757EgeDLo+1phm494VP2e4P8M\nxm6HNXGlYBG9SP6bz9J1RN4YSM2dl7ZRp9IPTeEUzfTVCh0KdIKpCbSSZ9BrEtHAED529PUHGQu2\nU68nMyPsD4+yuOzTM05keeRpTcgDjTTM6+5woA15SY4FOULStkFb55AtZkxhOY41t/+NOmKm1LR0\nsABvsB8NI6uPwJ6T+Hw10nJ6Zx52I2sFlps90Wq7Ae12lWi/3fkCviuX+CBqJckRYga3SA6nZbMx\n663dhxZTgbx1ldNKMApnpzJwMiGYpulIAH+wF2kDXKaVjBUM+ujeRfib5NMFd1cNx9rWc/Rlr9k1\nFFXs2t62T0maXcMEql2oMsE5jZVFFzh7lriz28Q1atNE1JkUjx6M00gg2WSan45AZt10Vl2hY7HJ\nE3Xzm6f1Fsd0uZf+lr1WdB76lv/e9cV0rGyA4C8fgWCKPrbtKRpGRA1KMI5yGPRf/FMSKayBHdbq\nNBg0dGd+hb8+KMElyPGJ0iXz++RzQOh+9kQy9eucaUjp6CLPdOcPjgqFN4pDcvu2jxZMYkd9bJqo\nL2yepgo2utGKxVkgshM+6QbDPMBK2By5uv9yqac/XpIlkSvD3r5gVdzWaUYkBOfKEZYy59Zr6Ydo\nzE2n/d9lFF1FUCtU82rUJEiJQ/fw3gv4SlJDDc1R23QphpH54qglBz/rK2wEEmB9TgKVsyvQebG/\nN+SQrnZ3bZSM9rQf6icIePVNHNVPSyp2omzgR1tW7YM+TNQucH6f8uSCnhwxm7VDbnwttLF5b+QS\nIKdHFELA+skdHuoyr1A2xJpdbeAkPb6fFpCAcze8cHI7kcPRps0ew6LA0Yngrv7KvM0FKb3Z7ZuX\nUv06ymeYm66szrJRY99IUR77Eqtb2tzSxZUhwCCXVOpFMTFx14uVAoicyL8ZMHQ0OpILH7Umdrgi\nEktLATkALA/uIEpb6S/DHrc3t8T9pyxv1M6vaKHUvlTbqAG/umG3f/j0aR2z1gmYS9j2UJVlGzEv\nVYdaKrIjqlWzy6/kol2oHqGE/iiqMvOuFGPsltokWb0qG36DAtsTMYhs4BNYKv+wuooONx/nqSYg\nTqX06b6VFmWpu26hba2zRlW4TT8tS0FOIJVA2VOW7egE8D30RPkZ2FCY3sKOY1iFuFsaLO49/cuI\nNNPqcIVOkVqUsiXHX94IQOd3KuQwAei4NEA3WZji6pogwlbP1IPcljTB93q+/1hDnnEZ+XT7vVuk\npvfe2sddPcnxe9E77OhQRY2AJ1NWqR0qm7PoZLdWPun8WAAEWuj+JfutebboFIhuVi5q43jWF6xl\nweiQUWhN8Dsn11CLR2WY7/jkLqa5BpSC/iVxnh/VDPNilFyn1s+sFadC6iAShfXsGbpF7eBiLGgf\nGoXEC5iFpg3agRq36F9eQ6LvlX9A9OcXZq0L3ndEiMsc6LADwdIeoMR73JsMTfo6A1RUqJv+RXEA\nOhgNUABx9aYtzKguTxgNYJweCmnslAmqkWPhOICRPWwcqd99W7Np2zIY9eTv4j8RX8zpybiy8GSD\nHNRDeqBgZwd4xJ7kCFyv3OGKP5d6zAsvAHkOGQaSg4b6Dxau/UiPP0WyXCCdG5Xvb8IFFwCW8RmV\nb1xG0v00HS0+S6NnWO3y42HilafaVUbiqd9ql/mCwAvLJQBRjN1bFZVUZ0tyX6aM27CCsgmYRpJ9\n9BoIo3m/1kTWluCPvF6/LmhDVsdTc+2RlYI7rRs+LpZ2z28G+hwwS3KeZ1SggOsdTrIaFx3qS1qO\nE2cntyt9rp1fIz6ybcIkDhCKxhO0/W6P+t5QkJu1MyrhUcD30ss+FzBufSmZ+rD95sHxu5aik9Di\n/Ib4LcgYEfmAM8VBvG60W73MQgTAtOsFxZ/q8JQpOPjpFCkmZ0QSeTng0A/c9qGJSGp0WwexaaSA\nX1/h+8GyAVOq05XrdAnF/IZbn5Sq2J80qwjEpZSben+oRgDmIGF9Yexf4iLxTe3UKoiz10lhAERt\n3amuQMQslVv8gpwAb1lcWBl7K5vym6AWX+Hib/QxXBTcSeIpsD4rdN1buqv6fKBUIyS7OOZqX5T8\n89pPTxyoKXIHxyZenKdg9deFy95N/ut0E8YsFcxzrKjAk1Eyofct3GmJ1rT/zL/DHDR9SsBKxnuR\n8Tb6a/ywto8HnV+ScgJY5wI5KwNqPTEfSHAeyuI66yQJppLBcZDGgtITuIwtv6wvkCsrDVl1jg1/\njMFh1Ss5e6Rz8OgxXmkRq7fWiBnMRHnq6Fykl4SgwQWEQ/JirTO+D2bPmYLAWkkAeBCjJ/VJWIGC\ng/HPGMt+XTVdFpNsmJvuLCQGdG+cqt9e2RE+KdXv+6CFhFs89jpGWzX4434waBKdFLPLW1yW4Ojb\nJ9vxkagvQIejbl9HWKZR1t0phhGsPGPpeRZD6I2wF8bmMwNaO4sV/WPuNOoY8IFy89PLScPqY8TT\nQPxHGmESH32+Gy8gocaCoTny15ltluhendcPTM/9Bi95nFp58RTAIDdDHZNj/VvnzJk+mcNmwhct\nXweVORnh4TJrFSbH0gXXMuf0FeQ5WXLu41nWQxD9eH5rHy5butPJKco2hDOBGaVHRDjl9nkhsfKL\n12tFtSXD8a+d0lDkIla2aS/uuDcnkzJtVy0DdQk+6fpeMv47C7jFZtdUPyDf/NfILuwGi/oYwm0r\nqjuwa7FvexeITIl+oE3AHZ54i+ZJJjkWUmPc1xNFZJ7RMHnn3mixlrqWHcUrIFDkd5iRiLT0SkvT\nbPf/ss3HmGUyGbRUoqA5Vb+HN09Rq1GLq6j49YS3dnCcc5xadGFgCQQFnyKGBvd62t306TRrXAU0\n9ATgWB5/rc9xmU7B67xUNqrv0Dz4DoJ5rY2M+7pSvKKUlz/6sJXqTjLC6oLN+kQ40Sw016Cm6K1z\nAYFqFonmOUJUTJvfaBvAr4mjwr0JIhk6+QEXxNNAyDDX5Ofs6lenkx2Et5EQMRbO7B+4vOm7Ggpo\nlRB1nzl6VngRmOAnT51X5d80wvxubRbHT+SV7MNXTjdjU6qW2Nm7R+kric7WWl95Mt8i8xY8OFA2\nUepRD0OpwDrHa8n0qMp8tD7C0SbMWNV+DrCZ/BK+brOsXzGZ8PlRddLs+ixZCOPdXbdUFHfu1Qx9\nDV2NRWjp6zy2nvBLXArWWoDgj0w+M1L7r+LCTt+p2fsCBfxNedpbzffu46bgmAoOVXx+9Y4wiyth\nSs01FDEKGjxLgMDlZAkLdkEsBOsP1m3HhxVzI7V4XF5G8wJG5eLdz0cCUQT+xo7kyfOYsAFQh1h9\nSufzBp7OyL+uWE7I2RLPyHsukAduOsh1DXYh0DCtmOMC8tg5b592iyiZUmUoRwEpnn4qF3jD6r4L\ncNilSEZnoEwslQaLUin6oxw6jW8wfOPq2xqO96lPXYN0TiqxV3pJRneWv/+R3WKq7uNF1pRAwWTx\nrCwUuSeOIjYB3CaPvv9ZmUM9CdeQIXmfMC5v8TXaPXqHwkFYSoJvv1G7Ra5/UqrAqbZswstwKkFL\nkSG58gZ+fo0EMgp9yfUAFMgUNea+wnrnX+ft2ojX5bfNwSReApjMTEDZjdUor7ZMC2UlZPKBRRYL\nVIC3fFo3g9j6wPHOZj1ojbRaoMhexn9OcGCHyxHqz5nalzKaExk13kDPyMDNYPzynF+9OL5zRKZF\n8glWhlJN1M6BQLwvKc4Sz4pvQ61kNH241Kw3yMVuRy0por5UAgx0wc5K4gQ4GlO1mMgANW3G9NAy\nSpy9M7S2sDjZpVMnAZh4PumM/9ha94hoiny5jWgQ9qP/IvrKhqDNABqyVLcccuCd37GcvCnV/+Hi\nnfrX9PTxgfKsO3DiD226GpqyDIDqQcRV4R04rn7ZZQdg1cOd2fLcMlbE0iZmbfL2WoiVgfB9ppCX\nGtbBMHfFYy+CUTrBmDg6y84sWQe60+/Y+w5i5WyOZvyxwz1EHq2BJEemTXVQduQ1U2olXVS/meno\niYf4oVDLxcxlqrSQC7Zs8Sj2ctEdOKMZEh6kbximfeMoFRkP77rnr1/NjrmE6f9YaA2Z2OG6cmDa\nSG58TGCCj900UcB824ROEL02agh5cprJbjd+XW0q/lWpS02reGeXt4TmMF40VYTXmjjJafgaAL1D\nV1ymRJ8N3W7B+rsVyu6DM3B/UgQO4RU1CCiQh8faA8/QKKx/n+hEE1xM++o7QuYT2SUXTuT2IjL2\nbPvJtEv1dEV/A6J3oyzkN1/S90TbgHra83X/dD+uFhs42dSYQoloQgVHpJacnaeRe9hQNRZF+eZC\noEbfx5zy20Tt3rh0QAqSwxVX9yu/FLD+dnQbfc1fCM4AGACgHgGB2cZsj/6AFOyjgfvF0lUaixHU\nXQBS+oA81NytiIAaAIRVUZpMEUpVAsbQvjbQBqhOYbjEhFYowKyanYe/cGT6jqM3RvbGQ1Lyn7nl\nag6qPJbsj8Sg4BstHb45Bt7PEBAf5pLIk3zHoENeR/POCu+0NUAjNJn570jGWxc1JXpCltRPsm8H\naoYU+uooq+p1GnZ7fXUhsc1eW5wKhn9psXqMeWhmCiEtrCHfggzneBZtrc1j3zhotKPQEQt+BbfX\nlFyf1jyks2H84P+e2XsgAW6bVVgQqiS3mdoVn7bfJBx4jJzgcOrxm0WolFVJUZ48Uc/tjNfO4T2r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2ub10BJTdrUPjcf3k07LdMoChwY66caAGv6mcrK4tDCSIBSH8zk+GU4xHzIw8tbagliCH5\nnamt/cPO2jlkzTBOEgRSniQ7nddFIcOa83J5KgeblcVjN4VOXYCXu0gZ3HJMidgPLGh+C+CFg51Y\na/ixmJ77Yye05HaxFodniXNJ3rru0loO1xvTORyEENpde8005p/7QlmvWsmuApH/PpvaMUKBuurg\nFZYc20fdytV1Doe3r04fZu6JI9rwG00CUrSBibFpnR6Cm5/moidcSFRSXyl43K5wBORcD1Ll03O1\n1jUGh9T/vmVE9bEDoPsoMTNCze6qMTmMOQnV/0zTetFTD8JcZHR/X40VX6ZQn9KvGPa48xfGg2D0\n1ZQjmKRYt3dJCbazWe9mMN96fJ36tGVULCqTqxkSjcByAqkGV2ayCD6dymuVqiCsqhE+68GLZ64S\nXpDgpzJ83P0Pqq6xltyXu7iMsyKW6rdkH3aFbGFSfsUG+OC6oOwHA2QyrlXtw/VUc9w+PaADqtyA\nnOUtO7/kVlVfUM6iaeErB5AsmVXOXC7XvpmmuQufJD1FLXCbuhZ0f9PfL0/d7DYh8GY/+eU/bgJ+\nGNo4Wl+XfOGd54rO27qIJhagvRY5BOi59q3m40CaijD6HzmBPxxlzBPA5DgXA9tX6CMcDVMwMY4q\nJkn1QgE4jt450sEJOuTNu9gClz6lQZkFU8o8CyI9plvqI2/aij3CLcvVZn6bAQb6dWrV1x3gwxBT\nZo+CqTkf6IdYdzhus5YvENDuU8Ktw/kVz9VcRg+cipZ54vltr/RJzJQxeS5V8pjFORZSZR4R7LhM\nGqn4FJhNi2T/wM1yo+v+iQrdevBkDGwn/Hkyi2KHvQdN5YddVyba23A6NTMgzJym2UV7ZUWF/yTi\nXAhblKxS38SDpGKMXx9Mfov4lUDbVUWEsa8+dslCPvwg+sfQXIXk1L/By0zYf8Sq8oPuPPex67F5\noo58shk6a/HU1n+x4/768P0zziCzhL6UmrleiDPDoC9ktql9yKYLsGuBvfilGLDq7WHSjd3jI4wC\nX7yewipXW1dhkzlZgOUJ+v+Ap3V2N5lShVkpZQGvYxPYknS3GXq0az8f5P3ZEgw/9tykrMnY8rSe\nP47tSSHTgAV8FtDFp0JoVGxkLjm0QhrWkCM4C8uRxVaR8ALnINYyoqLQJq0u4Ep8+MjwC6lc+u/i\nqdvbImKx+EJIzkrvjz82uDVZTC6uy+7lV0NrdHrJUinppSEa/Tv9aik4p14tBEL7WLTR3Id+Iw0M\nmAWYTLnCrXDewU24xxMx+72KvBXmeJyAXQoinEDovNFKGp8ZSM4D3uOTn8emrH1pywsrsyBEI3Jm\nu8y/czvv8pZ0uYbtm4T4mleU012ELAGt4snPB5zP3Yt+u5V5+UN3oKgiHyqRQHMNYIR6U1WGBo2f\nneNS7ac1lfauhei5r8aG5IWmXWDagc9tc2ufOcsyfNYHmP2YG7irZZzaDHbk7OF7cQbpZ8R2E0Jo\nQb0KuBxNEj9lyHhM2zK+wvp5mmThrDgnRFaW34fgKg5+8dvNvY9u+8ajHVaQ5p17A/gQZycPmx6W\nCnLK0X/7c2PcOW4dlO01tWQxmkisM67eZ+4Jw0txYwS810y9KPIE+GzvPddynvu5+krL9w58J013\nY4VW4eb/tMneMaSaOutn86s2maIKt6f/gxbhT93TZPYSjf7U5vgGSmg3EX2kFalFAtNVzN3EyZVE\nOT0xXxoBf8iPNnNaggzSy/xoVjU/y7Y4rBUzLTVq4hDJRygeQPoN9C9hI+k6ldLGmGwv2edAUoXo\nygGVQVDcrk2iobjVTZJpQJgUy4aIM8g3YrHvxYziHa5ljiMtQhDikEsdJPBMk5hpnsl6USmqP8Ad\nXdqjRTthsuCA4TvrncuICjPovowuYhgCt576ZKKAlEDztZQoipglO1cB7HV7WJIjsbFPQfjDwgAi\nLrdtv74xdk8NcVf61tr3ImmaIa25jpT+JeiFETq/+h6dkf5w824oXl3l/5k8FuYgIxYHuVmf95H0\n9spJULVuWF+tmlQX85Tj6zuxJeH9XypJAinJ84ok7Y3g0C9QfTHTrl1z94oa+bYbqykkSotMmPRW\nfSJbR8/htSOm1oU3ipSOYsPW62IHZ7TTng9zQj+oqJDx5L8fwxC6SWnbRr2u/s4VauC/p7dpE5+h\nOcYme19QD7qZRBeIEmU+GOcYxmAsFT3tjXGjx+FnFl1V/i8r2YzXZXPO4qfkyr2QXn7VRjeU7WE/\nogPElYcYy3XREmC0X0oseulhYgpZEZH2VHHDdGKqpssJWU5k3isGiynD+TtCCUolYgXETkQ3OmK2\nOb34hnSiVt89TFhLoAh8IbEuTG+rBCowNO4IOpO3K8EgQJU2psVpK96syIDs+lbmGJwvnIiH8OUU\neSmLDOP65PtX+WhJ+R9EsoxbRMv9CnkkaVEiazn704B6+2iuZEt+1PKIHkGlwbWG1RxU9o7zuo9V\nZorjNfhXyZk3xA1N2TrdMOpeUgyUpz2fPxNd/VX90yWWDemuLr2t1ZXLHNgPea/fvzYd46rdn9mx\neZZgFWPUE8FDrgmQU9sMn2JOCFqeXaAI9ru3Ure6046gdxslPsMeF7JpZF+4aez/kZOmhJHxCts6\nvzw8RHQS14qTXkucroTYQChRLibvgBTH2jeBflojLPknCgnA1Qw0qGko0znYgas/W1H7jTLBCZOf\nKtUK8k361b4koh8W/XWUi5vmtr10aHMa9EmbV/wrIX7Gjuc6VsHx/IgeMA2OB5P5wcRF39tv7v0C\nYrhGUJIqaU6l9Ol194mV9zk+NilatFMpqq9EvGaE50zrWK8hIdd4ao1f0MwwIR+A+9Sh912JStoF\nxXlUuLa0yeIMsaM3CXzQJG5356PppcS5D5TGwjb5yMCmBoLMc3cGkXDisY5S+eGKMdssc9RmgkiD\nFKLqTo/qtYsrdbCrdb5qiFzD82ldXwRjP0sqTA6Ul0gzwz/oe4+OUkliqg6SJzS0XndZ6nEsGJRD\n7fw9XqswwNBZ2fmuAzdF0B/1XVUWiA6C/OWgMFv1vFPxXoXRUQg5ymwofyecQEXHQVSFn4M09Otp\nwXS76jURDiZ9Hc7m4k8QqmLQ40kbRLbwolRW10+ZrKZSRa8ukjIj6XXQDrkGhMgdeePXETYzmTM0\n75UXF63jnQYJ0W/UZyqWpcBZrkD7DEzGqezVh8N1PEF2/C+gmm5Viy0KcNJJrwtkGWCCSG+tAH0d\nh0adDk85HgbevrJxhiOky/P+Y7HdH+ZNK4k/x9k3S1vCWlF/q63/KnW6c0mjlkosU0ixGm8E/JIR\n5oCO8BxrZlVcdmLQ635kztk/eighutm3DBepuY3F0ye0ULzXMVmqrwj85xCYEm3RbLOJZbQegi+F\nirsWcC/JVl3fnuwGrg5I4YBq1dH2zWXhA7lOC4dxgTAu/JyGMRp4A+ej49Sq5XqTdKpxpdMRRHZ6\nCTstCON/6IPnQcQqxmrkf0rJDr18Y8TnE0upctxIn4E0gevAyMRxsQYA75zMdirKWejVy7AwnH8A\njFgQ2lRqcr/4KmghywsjnA4movNMSuqILzFRrdDRZL0I1iab81SDIBYqcUYfktJN9V8RnnAUl3l/\n3hBgJQ85EFzPBR4pTNNIreFH2hRYmUNF4Jm6nTEpMAIoroPvWn/lrqrNZ+YTjihWR/U+8QtTOONS\ncMO5rFhv5o1NZAjo4JCgQd+kWcFadzc7wsvvOZo3aflvs7NDrWcB4EY58YxPHwO6aRCGnC2q96fY\nZjV/UMTqjLphuYGIP8idKsFSvgg4JhwOBwTERLDOE+sncK9HPJiJwnALVyDzGUx4ECTbJe6hMlKz\n+1UXwQEt1CByl0aj5ggN1P04q9Rx4e9M+hhCpppTLntntbCG6I7u/OtK6rDPz+Qdu/31y2t+ypEs\nzFZ85UusIL11VcY+o7DytUARXwg3zWgtv1wzNatklPo9CSlXZRfhsY+zqVuGWey+xoh4KsiJXbUQ\nMH7R+BgcSENdr/h1Bi2Pq58MsFC2N6znenfP8lmH8K6pBadVLgO5tJzuwBC3uz+UchZBTZIWI6HV\nafKBgq70pnKr5dAQHbWvRHrYbWjWRgWYsshN3l+FWVRLRFD7ytIxMl29EuJfKkyut/AtkgUB5h0J\nx69bq5YbxyEsBVjhRClsewPdJF1oo7mFdIoAUgmGyc0bsNkivkdIqY6QmUXFJ2QV6Mc+bO/55zWj\nCvIf2CLNTaB3f2CgtUGic+re2A12X76uElscZ5eZvMGIRYir5pfQoiGAYNCGTRl4f1PwHiBI6mFr\nqdjb2adjrQNa5WDIDYa2UT/2BX4qCCivtCNOP7/jMnyjgxlL9lfTb9zlKqd30JvftPDRRHL1/2z7\nGoC+HBtdpym2eDmmjxHnHpsOaCgg4IaiHBy+aVwy2bo+f+0vRidiweWuBmdb//62eo6zYpYMiW0C\nZzbNpoGKuEIk7/7Hi0xESTgnMstA/sk8/34f3zxL15rZIW330L+dde7HI3hHaZ7fkMdWpaZgVhJc\nLrMCkqqPel7y2pQsEFGmvHk/zOPEXpTZr9RMWILuc0j5OrF8rRLdl5iYpp9ZGplOzvFJrLWj/75r\neO/o0DUs31oomZg7WtxlvQHs7CzG2tfwwpDHOn0OMrJ2gMWOfGjEMHZ/ZaGRDZ1O/IvVOaWPS6N9\nkmuU93j2hCyePSl7fv5Ift3sNjPM9nmM4rhiDeO3kElHlA8bBETyUOl8Tih+N1lfM3/GbPGuXk3d\nRf182SC4LahYnpWhH+ya+HJIbr6PF1jRAyuyklosoA0E2wRA3vygyuwm+NCvmwg62wnAZU5kaqcP\nelIKACtjd7IRcimmua0uiKtGeSn1wlHrxSqH4qj8/C5SbsAGtFAsMbRELZ2fnHO1aWnCxVubj2kM\n/ovahk1VfGvcEuuBn7FLTqd2c+KahkKHI0k3xmc+fJQ0dlXC58Fi1I/5Nx1duz16rFXuKcFwLowQ\nakg2kR1ihV6W7JYrMkTt/4dd4VEN/zcQHc3Py8X+pKaJvzK3xGeompmwPBpFocSEyr7yYMtBQUYH\nJe4Ouiyjvum++Z9cxkRehVHBTTpstu1SFluxcSd/ZY2Ghq+GyFPmqmH8PvTh8JfgI7lzoK3N8SuV\nsIF7rCMSL7vx1NnEn1rFN4Gk2ra5xFfNi3LpybwZPH0wY9USRBWuR/PrR1mm38Z2QNimz4ZGUAeF\nmcIxCTP1X3LAsu4biq7Tqs162kjhRsneAwHv89HIWyXaGuMyCECt2T2hhGKAoy+sSnNCvzjR9cVe\neiakOT7mH4vQp42zeO5XNmVZJQqSzFka4EjWxSwiSyKlpsxssYk6iFfvndC94AshO8kM/WmJQTnz\njT2ARPbuoPlRyCLhgj5JlhhzFJKUb2SUOR7a49qk/t+kVK9xswR+c60hYaBV5dIBxSZguzt3LzTO\nRXmTqnAJpHh5SZq4OP0wxpnH6DcpJ0ORefbUj/r5BiEgmqj+qgyWRyFRxaocuRmSqCixXxeT7Wxq\nXirtrs7DAZzxx6gDCIGghT76uzFYiGr5sUkfTH6Zad0hhYY/l7GP+g2+mHEDywFOGNN+3xRw9q/E\nsb3yE/lkdA7s9wtd9U1Wf0Vs03q4/j3bKQgLD96Do9aKdI+GR//NdRUVurNffeMgx7yQSMUg4aOh\nbFUBUeMgWEIdHbLZlxUIaHVZf8+wvmOsn/2NKWvgii4pfZ7/Y/0z33eC0cFeaEzmTInXQkUqDpCL\nkgNFH8uOXXlMvVOJuwn7NCP+p0lzwU4jQuFRCJUSvFHTflKE8BrO8giz0dL6U+/J9HGBmzB89p27\nw/Bs/X0rzKb9Ey/eaVgYDxRLI2MknlY8ctw80V7g+654wZvHuymEXKwu6QkBV1G7Pg40I5tzHepf\ncsdahl++Czvw31I++2/lnHsmr0rZe1ZGUpLvmg5YOi/iBIQWe6wwrJvxk8qtsvOL+IWrwvVXnhdm\nYTDVfFLYN/IaozY9CMmi0Lmnd+JsNCu/2OnD4CnomnWCl2H7jixsdNOxfRS5lOc7pu1Dai884gh4\nBEBMiYaR/mOmwYvWRm0s5CjnRRPb7HfXmvCwgItEjlKRqn1+6zy73FBNjv/vpT0l4VLCl7fbNr+m\n0nsgcrEpJs5tBzR7RH4a18SErXWYute1eyPErSI6nq7GBJvIGNWiHK5ve4ZdYUQvN2qBl5CXlVZP\nBuFtdqN+xwfxZwM9xHdqJX4ado5+zf6GVDxIRNeBwaKpH2ofTKesPORY8n1AbnSGDIwdxMR7ic3b\nOrQ0rCtbL6ZIqRjJam1EMe3lPDn4EeM/LiBB8vKSERbk/Z24UB43iAwYI380jJVxsQs7V+QoRmLH\nNbDTCEcxX6dyiBtrB2t6YCEHMEjsXfOSYseKYA2+NwqrxgtiZlplhGf9YuChnVJQLwzbm/UqIJUt\ny15QNvE7zgPMsLnGMCcHd4O1JIDACaOC+HTeXtJiKIOk6W8c0FtKEaNxVY8cGBBa4vec2/oW9PVe\n+IHcI17nJNBP3rvlYPoCIFlqPGsf4ErefQtDoHOSFfzCf67UVQtV/C3DAiEYv9j4EOv/imn1Q3/e\nRYK3mSvW6iAczMTGoX0uMziQScAdWVk8k41wv9xYDdlnfQ71LpqHTjs35Fv8nTvXblbKCJLX2AXX\ngDBwmnbHSc/NnVQpznPBJfHty/dlgjadUnTIETNNHzfz2Mi6uziQ1o98l5uZEiiYCvaeer0T5/9i\nCY14dGagymKnNo9dPBOCvmMklswLCJpii3JqCRIWPXDQvw1J+01nND60fcDv57LlVIw0l19q8C7b\ne6mXc06a2ou2tMtnFw7hditQTEfs5VXdv6uXSmDmFPacMYtklu1mKsc1F/vb17q7iKKlAE1A1+Fc\nSyZh8M78o5vDD38WyTFbJHu1Me4sx/a5a3MUWq3GjT0vmzhQNK5nYwfmF7NQaM7OLDtXEGtbPRG4\nbTUMgXOUYft09RfOHH/EV8C+aXirpUj67IuMgsHB5NGUFBsO8+EjWFVA+2p12M8+uI/YJAFcb8fW\nRECqxLkyxLyD48LFBG7V+/1byLRs7lDtZe1VDe9rQFC3tDF9TNL0iyT46QeAoF+/VvmYEdGQQZXI\nuZjd+ZB++QR/3x/V8nvffzUAM3CWNj2MEeIWJi1vZTaaDo/la6qGsKd0ppw/uHGXSxv+YPInQsVg\nmDWFJ3rd3LN3tOkiMJz9n5F9rMGSnA8rFPbwjm+HQDonchdGPvn5+HZpMmhKqmK9J2zBJiJ2Lx7P\nEo0/ccGr8uwHCeHaXcDPUW2U3GP6e4ym+X0c0oVjC26Are7Rg3VxTLwTgso214W/0QUGQvhKSR3q\ntLeAw/qLNRMkXyU06AkJngzDB9eya9oV3gru7BaZfDZpxcHIErRma/ZULO/GHYHNLSNUqFJOFVuO\nZwYFkUfeKoNc/0D6MA6T1/SghHAEmxzbiCyMDTWkPAvqM+e3VEScT/PwwrR85yfu1K6nIr6wvdCV\nEelx39YEhyAGabP46VOvnshrEYiG/STk3/g4HUSsPiePMzl5Xky80H7CeYbNrx94mI0KoSVtXaQ5\nK+qBKv4PUZ8IdnEoRD6bzbhrXgC8okTwO7MnJIu7DmjVhF/Cmc2mqJISwA1P7vVgPzXrRMA3Yx/6\nwwxA2bU+Vn3ZezLWPTyDlaKwBcvVXWiK6x4zxI7DnMbHZVEAcnV1Zjld70+f9g3+7EOYW6R11+6S\n93i0xSiojR9UqDApHio46hYXlHB0A0VRp0ajAxsWEeUf3k8ZwPHkgWqzx6p1NHDsVEGG38n9YoD0\nxgicBlDx504r/BhRaMKkeLx87ZNPd2J27b+VuU8FFfM+9PgLy4nvnraOXq0YBpzdqx+UhgFNzXT7\n1dH6x7MgsqNfWsfXQEK/OJ1V4iUT9yxEfR8TH+amuPfJzhebd8RlRbLzgy5zmyGyknHgHFUgGVGi\nIC/E6XE1N/5MVC5OLQy6r0PhvnTImkt9biXULxdMXkD7Qjg1IaExzYoGev/cfyfdSZOFqEqbmqVs\nuGtBre+C4pwyGdwIsnIT0jFKIXW0uFJi+jrgzp4K/nEgqKGwyk9OhCsrfA3QM24ctI7yUK10cdVO\nKzKRfYc0Y05TttJy7KtfkcDRp+3Lp61fKM+CxA3HzCJZLnhDXPG848XvXKyIuxyeoPJzix5cWziO\nA9nNdHk+UEW/MKQXiApjOsSDJu1K0xWhzdyG4M+xhSkTKwtlyKBohpMvU5aw9kS41mGfBFVYuzsC\nJ7PkKfTAIKg/rOtu/KoYkg002sHK+QTd6xUkJniM8+/S2Pf59InZ8Iex/2PnR3f4up/4/f4Yzr7u\n/cQFNYRIoedwDXzBcUo+YDWx43l+t/FvsHWDpIAiSkTyDaVZYjkKk5tzIBSAmFQ1PUX2Aw1uijIy\nTmSbVvcC/GSeVGsRijWQdIoPQVgW8TabObAF8/Iq6GyLnUAEkEoNxSmqDtkXr0mMXBnVfPlgrdQa\ncSUhPP3e0JSB0LL2R/Le93n4NeDOUZ7iwAM0uJLs8wzwzOHbBp8p4KZ/lOxUBj8g3jKHC3fc7ktw\nm1kECcIiLDHX5IpoAh0fl4CJwb3ABtYddz13AflejZX2m79zqUqIkddpCwYsL5wwObXH7H6ozCEn\naRCSyrLf8hf4p3wIzSG+pdhRQrB7YflCWIF9AMj5iP5TGKeeMDPS1XZfsu4Yfc9ACvkYxqW9FpRn\njd78IL3XJC8FqfAW5Hz0a5pAetvYhU8y5Iu3aexC/iQiTFfo5eKbvIzMtWYh21dNISizbA0ubJni\nE1NYvVrUgi4HNPeDf9ayM2MZQhpg8a4BF9GNGa19VlhKzEgCAKmbuGvbpgbhPF0+HWEtNIJSbn7+\nMJatbjpZmSNkDspbQPDzxXenVKkJNwmYnv+GrC0l8efYpc3iI3pDdbr54NpwjILUPl65BwxuSUJ5\nNEIBRbCRo0jpDpuFfqNv4h1COVm6AHzVnIlUmguVoOepmL47dfcWC1a6q7XcGPFjF0zrqvrqddG1\nSUUqdx6a07zDzaWXYNDJ/qDytDrFfRYXMM/1aMsYGO9QpQExOxoo1lGMFnnbg07nyUPAFerPFZch\n/eJzBkTnfLK6M7N1CYAcSyC+KJKvLUExwiUEKHT1EdvRY6t6DPL121niWRnPcwJa+Y+iw50o32Ql\nwq6nhkGsKjKKtbAvvMoiEVA2QGzj2tT8aZFVkMIUb/QvQ8wo7/0BGgJ6ICnLKfW7RntrbEXX0Es+\nSYK009eHPpHIoC+ZyahCO4OP/HtLmDo3YPINqV1lWwZpdIqOqFgtA2q2c/wSqS69lw9f8TrAB/Nx\n51uOZXDt6+2dc2VnhB8Z0VURV06IaHDI4bIrXxyjIu9brJ5fU+U3aUpWHdw3X7/A9TfyIg6XnheA\npgSykH8iignsSH8sllebTbuIPgbJb7N4Vqo8ilSxbLB0n6QaMpX7VpaTlRMg9z9hzqwYTxYHJxnl\n9C9pRzzomQze7rSkDAn+qE8b0RjhM7cyh+RsfMe6tRBp9BpNgmMqYF6s3/JmrCu42AZdpuVXrcCG\nkCq2YqPsG4FlrHQHuvN6aezotodm/DRyIovMtY9EV95/aIbr38sV3M9m8aMTKNbCj8dhCTVKpC5g\nVoL/4t6rws/+bjKU3xX2O3W0e5MDZdrEclornvMQecW6WdZdBB2Z2FFV5AJjUnihthBX2OngELRI\nzLvLKg74A/geYtme0cyWjCJ2JxsjK4n+CDDUeQD2wZ5KPx2yvAyhiW1GVCZRhCGcKyPiFj68iXML\ns5KoYXf9cU/yfSBkHWLhf7S9J67OH8DMRSmMS+2FWRNMDZZza8QHWgSEaFZgiIehdrK0Ukrwt29K\nf7Oyr0dsDzEJIyGko5ZwP3kq2QPpke9XFtySba4ufL6phIY2Z9to9nAvzpx1KhlUXb2acELZIOg+\npjatn0262ptc2+9QF+l/O5iegSTmLBk7ldAE8Abl451Q1lla+cjDqE3PaEF0i0LvV37FPMo3d043\nCws9S9hlFmuIz5q+/VCCYbFNbs0oS/zwmEkalms9VRhcpFB+EV3+kFg7jB42EhKVPNbA8lcCC100\nYfwYj8AbGtU4KR/wpcdARZ5hHfMeLLUg2ZnNdPxlsYHrqXRgl8UQGoce1YjG8am4BP4DNyD0hm3y\nqL09we2czazgK38khazoVbyv6bwdpzbHZuNDA/fAfW7Y18LCF0OTGNOXsCHdLC/CxZAxMMMPb3ci\ngAzv1Y07zjtCkIV9/AD2IoWEot+AK6zBclH+LwPpIOtWBdc1QS5g2+GmyZCLpbwJDBIQGyJfm3pk\ne6Ac4QUMLh43UT6w12/bgtI9Fvc0OAltvwkGkBI7du8wUY/bX2jMtck/JNpUCYtdabbeGetHWbhI\nu5FFw+yTkKldqiQluVKPfyE1+K5Ig18pINO+Or41W3yyDcX/eiWMDgL3tsNShLVi8iCiBBzJmM6Q\nHtN5JIBZ/TGu5eFnQK7SB85baWNV5Hqh74Ns5lC3TLnFLfwz2As/OfgdAVnrtsmt2x7bJHeY9+wp\n4ZUIVnR2aioImUZ1EM9NEemrPbzYj75f6k1o7hY0KKvaGsJ9zNEJ0MUrcLXUEoAOfzfOzycZQ3Dy\nYRMGgfwwWAa47vpNPxU/Jk1tMgrRlRqvFSicjlK3O7+Zt/x03bWF4JVGsUfKc+9MV1tDe4nJeyQ8\nUJ71FbeM7xTLS0Sx+pMgn8rZ9OCiNN+l/Ofyes3yyBch3jid2Q4AA27+GDyaxH/MGkngRM/e+4S6\nUqhLAOkjaw9KF2OLQk535HnkOGTBcbnBtfIFrRH10gUAgKvV9ITvCLgEoVbz4ibEvdOVAReHSHrt\nMHAq4VMXXd2bQgio3GYKg1jXwW3V7rAd2yycJi2ovTuoEp2/O+4Rm10S7wAlLhbwZAqLjnFiYPBt\ntg+zCH5tDU8ICdVgcJ1dYdpwcNTF6IUYoS/80AQvfUkJ+NDEe6K9/sX+OBuJk1f3TKWrxjACNnKQ\ne2EV0EZobRxdxCX03rxQhuNIT00RiT+CrroG0lk4nOCvvJuQ+BsPevxO8WGn4JkHXLucBMYqt2CC\n3ND99oe3jP5kbTMRM67aQgPD6Wqz988Zc4AXV4cIiLTHAE3i5XyBAtSkqgBM7PuqjfV0XLsHLqbn\n3Kt1eLUWvnpp4qjAVP6wB+iGTGNa/6z1zLxjhepj5uMTh8i8DDQEpDbb6pqCaq4Bl5pcucR2jKkL\nAjZZXjRzuegqs44psw+iikAOLN1jX/d+s5GCPITcnJ+8GI46uu7hM1GF7LVIKGbyrzsSt6KYnsXn\nxUBfx/i3XwclaQ64GDF7LIRu2lrvHlNXo88DfmPoNB/AZR0GjSDC79VxxrT13P+a7Lfi7kEV8mV1\n2cwiTdtjbS074rGT3tacTD2vQxdO+nKGPGpRDKV2fARKJXY1xHQP0NSP4X8GTKfj5A1qpW+hQ7eZ\n9Qx4/IDPYPU4UDrOuUDGyEtU1aoOTiUzZUdVCFPNK0nG0puFoPn4xOLIXQGHNkFG9/oR23OCioXB\ngQFpWfLjaZoolhd73ICq3RH0GoB3a+MjpIlAuv7iEql6gtsYoPITu8Olz6QA89F9ol7KEctnVyvI\nxZ4OBM6GgKpfRUTLmZYiWOGzXAr8Hond0yxhVhZwjhMxnaJttpCGqiCbOCTcCfChmqIOOk+6Tjng\nxJireKXcr7gxVXoNZg0RCneKrgtBuYGag0o8MZgzITZ8/1lJuxWvXx/5NpaRkG5x8+VavVlnxOav\nG0q9oo5ESwoUgvf9KmAeotkvUAKE8REn9q+JCnmjdooxbBJaXNX5ScBzMFnkrSsJq3OFUYGUsHTv\nHb5H9ilCWvQ1FEBxWz94w4RoC4SKfcFq7hXERbnkCFz47BnL01jJTSHFzJGx8JbgVzyXVdS1+eUt\nSZdviBFXqZeHOsfdPwinrrC24Ey6iXxzHKOExn23eGMo3JbypGb2nsHMv5S4HQINwFbZqNsRW32g\nmZYi8ueQmHldYtOiAqpKK4NaUXbp5Ba6aA4LQErGAwJkazgS1EBuGLCc9Z8pFtleC4mwSVTS5+op\nsyHNdr95V4FXBgDm37HH8tVcc/9fYm6qN+YtszBv7hN8nAvXvwDuc1oSVltE8nnvPTIsKF2J3eTx\nJ6s91b38tdlgOad1hyWx85GzcWsirI14UczEAz72WOhcLgnyq8WVinwieqfRLOkQ8A21PCACXuJS\nckRScz55M0z3c6gKZu3uO0qjvk7woWbfKYU1VdAMlA/Eh8Afv77xW9BQ7oENEeBX35PDDhHIBveJ\nJXJKh/l+We+Ke/TLGuewc5NG27XOYH+mdyoOk/ImFoo8uZDw5pobhSjXUp7W9x1JqDId5rx6EX7y\ngbvdQyp/Lg9pVbaiXk/z8zBBIM29B5Qg1Feqo0YFVlgmPBioOmL0wRy3kW+7R8vBPU0DYdSBMgH3\njT0QXF1egNON6WrUm25RBjGDZKCqhi9fipxcKRMH7tHxj6eVXPEkolsF8V5Zj5oZ55EGXO5TZwdm\nZfonanZYHBZKophKRSUY0PV45a4gsZugJdMw1DqOX4gljKtZITP3K6cSdp0r02DE3fTMLAq97KDq\nAaRHjlcpm66xTf0+Wt6VJ4zFOz86ziszPzO8SxLdKk7bTf2KxC2F01yM37KPYgXyadcv/E2C3S0+\n32MGy5ZrMopS7FVDs5ODjvM/Cp+zabSC8BNUaBaenyB9kWY+actuk5zKMTSoBpmHQqJncCjiIgWS\nrtaMvlmwRUrb3pYlGIuheZYph09FR62khlEXcvMccS9hsfPb/syM2D+5GVoPn5Al0uo25tAPzXfg\nxMq9Oyk3o+JfDZkVsnIKvlX2wwcFpTSrpefw2D+4Fk5GEYq8pN9pzxWpZxV2sq7Aviu/VyGoq7+f\nWrwjL+aH4motwECFGLJN64iRgGQOg4/K65NSRvALZOmsPpjTKwBpkB9sVpK1/c9GCqLjCxniM0J2\nrwj4vUWJuZyXuxO9S/zcLc1c4uqz/kBJ4BEAlLYkDuwvTPFKcCZIBti2BHwwO9R4uRSyeQpa3RqZ\nyz6sKvfLzxuvaMcMtXCY0h5Sxu+sA2iNBM9Sqvd3K0nyvv45ebGpk1eGYAxntN+wpqoKo3gjGj9S\n9x53jL6rZky4qEDjQbD912tQi2vhSqM2GR3nzHvhfi83j2gHxHgI+2igsVo+8a4KJryeSUG+FXRY\nh+4ZupELED/WVkzq2yMp/2+5qGeRibklPRWplY86cSu1PWyQE962Ia5ekOQeqYSI1kodU3sir36E\nNGq0agl944W8ZhcaZOo45yZ98+5zeUKVMJsMUTTtOFJT4zeT6iKwEGZvTHVVwrBUIkylgXjWoDE0\n4CIOdeoNrf9hhJw0iRnX8TMDIasZyJ8keuX2hWb2VLKPGngXPJZSGaDkCS/Pd/9c+Vnj48VxZo1Q\nWMCIhfBrdwlrpnN/r71UIopSxHKjAoGKvs+ie1a4RIHFq1rV2oKL10ryZSXYnEqcQkjU6Rk/Km9A\nvTe5EY2ArgXAeollC2l2e/qby/FR9y/rPPrJx+3ghDEYN9vaNhJm7IDLlqPpOtIaB/v5rJpbmSs3\nRgFzIr17Bxou81Z8tZM5QqsdzEhPAQSOpDiZrdZLdKsZzKXQ/rzpY5CYSpTx4fsj/xT+8vAqizEY\nv8at9psQu6JICgXWN8YmRLPW8SgWpJDTKzUudj+sGPnWTxtE94T/yDv9kynvvIomn/wjOUQCLdFH\nJX24rdxjgacbmkfbx42Vv4DmOj3/L8Ebl3IRrWiqLucurlHx2oOmYIsgO6D818AldfLlStrUpoZ9\nVrETbT+GrdP12oRjMRqocKjL3U4KDooek82i5YvXhN0ebLMuwg7AeRf0wfy9MSBhvhaNXoBWiNxI\nqQQktCPqD2uHf4nWzvPyrwVxSWbplRYraWQ6q8wzbh5hrux/9JzjNNtVQmfwmCU6jBVw/UOm8x+g\nuPVV9yYBKeWPaOXHEUOw9xrdKA9hLimpOCL3DA6NajGJnwuLSWXtDx0wzPZL61+Df3MOcWxFRmXV\nNQZPNXIef5BahzUGKLyGq+bnoUuUxAHcY1YU5ftMKv5fGQGUvbWIriRfhMEwqVCRohdB8+zDWb+1\n7IsUm/2Uv48xV8myuzrL4TU5fc/ozYHXRxt6AGi0NFQ2FlNsKH34xB1FATbAJUpUaYFn0z2YG71S\nUB/WA+xzSz7Z+QOmlqteA7J4nGiuT+BZi0/W4Ad19dGuaWFut1LRASoXU3wXNSkCQf+KbghbadN8\nP4nggmXkzcGWaqXu2IekPg5VtMkGJVqTZn5s05QplDpuyTPARLrN1cr8FJeEWNQarGMrXPDQ/bTm\n+EURI8dUoi9RXctpU4PIb1mNqkocfsR6THICtHqXWm/qd3unxcQN1Qi/cHB5eupC/Kj/X18Sag3e\n+rVzXCuoQiuZH8Uusbxs9kqC18uZVHSfn/nVB/8p0CMIk2eoN+7UQMeKCYpOpnfobkvkdkHcL8eU\nIBNwBUtkJ1pNTxC54VbllF03VVnpOPj92utxR3+IyR/jFDUhCRxOX/YB7ixu9XC9Xm0i8tmWs8Dk\nt8cPfu53Oen1RhAVHQD+vddfuyjCu31ZFVXNAeFlyrIdgtXsAaQTYEyAmCyBrBewTBwZT8o5c/YZ\nf+RfiMnvBM3fKaoaKTXMeIJFtmEjFtaaeXZmPVgNlnPzxVhcStp6w4pOnv2wP6P4YpnR0iR6rc9o\nx5xZgcr6Vs2mdwECwUgx0PtsMC3wdU5aL2Fqol0sOyVtJn7l2bld9IPdoGM7MkjZXKVc1uQSofv5\nX8pNV3nwBVYlYNPwt4AyWvFwD7L50YBX6f03lJQFR5zip62FIxdi3/Hca27h5TSlM8bEGFRNDxSu\n9fDbs67HMJouIheTBXXTIDM4Fa7nZ10zaJBMwSULvHs+ERx8yNc6wer0iUVJlimpFG/Gk51Ms10d\n0BW4HXzjFdCcCqupQBleiS+sK/llZJb05vpOS7lSoT36ITHXG2CglaacvqXcZDWa3/931L2bQhay\nJUBpNHDlxQa8eO9bGpiWMPCQKY80jF/kH9WZsE9CwsbugWCrPlN2GuKGQEdpczLPFk3TRmZOjPCb\njim0ZJLHP6FdBujUqBcAwOellLDaf5vCYeHLb2SVuKmHFVjNJGWZtvTRGE4OHwB7pONfQmsx4CVX\nk5lA2AIzj3FYnzk7ikk0a3cK84zAQ1ah+oXGn/bQS9mfz8qL+c5wVHQMjZdeEQTznwq6YqxXiRL0\nNB/+MuwLmdPPIaSfaErE1E7hKovsnE2NMdf/LKW0C+nCGu0bToVlcOmdGs7MSRJwymBGXxaHJBpe\nJl69wGXb94PjbHld3zuWwuakUxBgiR/Nmi2WhvgzAN9od+TciJmhneKCRBpoMWZSnIGmdT4LqO0g\nK1nMZhJZeGOq8cPVKmBUoSQAXXHzCme1rc8hRJz4K6/CpaZiwg3vDPd0R9C9xvd3D8e761GLTV2W\nuxtIB8+1GE3wOpqHQ1Va1yaDU8AFE/OguN4/Tlh87kwqars0MTRxDF9q0INMAAzpve8Kr9NwDumY\nozv/1SHV+BbBDNvfaCpmjO7pma0GXzjozdcXC1iZ+0o7FitM5D+0FNukvHuHBLMLWN/qgWQHbH2a\n+7Ip0LIUkrH41tnb9aqrO0XxWoaXhnuZXY6gP844p/5njrwhY31T8ROsMOfV3WVZvMzxuwm1K35L\nSdEWzbHYcZnRjPvSK5KPIMgjsAydqNbj/UyH/5y9FxvNmZ+6X03K5sItrhmO+3Fx7V82nNjrL5+y\n0X9mqlSb5NQj/h/GpydH8+eUyLi9Nq+6tW59STJXr4rA5yZyGAUMzKGjvUU2bjAI2N7+cKr8Dirb\nw+7P/XxiER8Mz/Kq7vWffO58BK4ofWnIb6vo/xZCh+vSTID6L0rF7U0C1cPyiFxjTleRyByi1MSk\nM2poYRuqcJ7PGtvaV2JUi2NdxH/qP42kK881hHgZlUhZnb694X7mNeUjVopB2x6PB4f8VQlc/p+y\n8mamyoGPcEFXTl7UB3Etd/wEOGcxeCmBNEYNfLywgkjwiJw6NjqfcZu8D3oFd+Dn7RIT7nzZFVIZ\nHv6X7nrc8H1C7OK2k1D5qX9v+nxo5qH/p3Un/ryZM0ZqlG2I1SYPbWtVcN6tDqF722oHoRjF/cb6\nnMem36o8KOcAQ2srDMdrSsUip29yp6AzVhoF2mPfeehf+dl/Oawk8+YGUzPHz/mzUgXOJvTkavsU\naPX9n39sfBAz4R1KBww6Wc/NlKTLR06bMmbH0lk8ym5JPPH9+D/sSt2emdOtU9Mr3vC63ksqnLHp\nSJ4n9UMy+DRApvca71/qBdDbai7BscwynsfqAcmQDXNCphgdUSGZ+TyfhxQwly+Zeg/0CUty7c0J\nt+fpzAz2fjcScBJSNwVWimT7TYkjuRPEs17xn4lQjMU+sywBQ9tNrpSs0XCCJ6SoB2JajQ8X0xxg\nL6XCvwoyNzWhK1AIlQAcqn+ZRZt22H6yYCoznILiBZImOxDCAANKiJ1Zecu6I/vqKh/BoVDvfpKU\nr4RULHkNwNWt+TP7kjSp5JaYot88yk800SR+Cg2zheqkKGNR2JBZ6/dYXr3YJa3E6oPkKXGMyRDG\nkJHR/OwRQD4rxhoY+hH0wA9DzVQHz391WZlxoh1FyYcpV5jsu2hvI4XzWpFl0tA2K2s4uU/x+wez\n2zIKXh8RKJOwuv3w3acMIyFqeUFTgqJrbCCljvaMvjhshAofF9C11wSylphDyzDmE1Auo6tk5HWN\nc7w77UcTMG6cMK4e3RVpVHZ9seJg8TMOwXE9XTEjWKip/kZ1dQLVn0li+SqtNHDxprWjdsKkr1uz\nCM6uvSUeFTF3dAOuz+A8L6y/eTUotVq3B3bbpYrScs/XaWQrnXwBOqbLjj0n/qYJ8zXSt25SQV24\nJT+9VxmBlxs3gAqtWfbkMOSZdgST+prZ4LP2+ojprhjuorQRM1mqaYq2jKxLuRzpOgkK2Le2heQk\nsLUMvKG9KuZkz8x0CLch3t3VIw2MLyWbm0/RE3rB6AXBDpSILXSVY7qFRGdxvVbeFhxUxOfCInvR\ntIR3WTIK7LPT0Jvm7eNtQp3g4wuqTHHVv+N3G7rseY2OqBhtNMpZxgqgkyVkuWQg+GtpKvnGk0af\neFs7Ac7MlGpjTaS4GXjvL3pCZMETVcFJSSd9EO4uX3QfTs4PA2hCJhDq81GGmax+uMJ/KgsLYVgn\n5C40oDBGd5ucoJfjr/ia/dqvJLlkPLjEKm4UsSNbRanf3yEi9ZG2riSoR1JR14cLafiJRzHjDt5u\naejfTraQCR8PMf3+L0VvssJ2QhLqx9OdGrQAhAQxU4cUvYNNOq7ok2YFDDdIrGEYX7/iEGlOdTuP\n8x91cEa2GZ53+7ZlYbcWvgSOdGT6zqUYomiiHLHShyrKPyyRKcx+Lb7QJRyELuxXderyZRjQzLHU\nKz5BZ1liWEY1FTXQhWi/yPmNa+C9enz67ghszmadpwNbhdW/2Eq5XagNAZ+biKjfiqHdUEmFe6e7\nvPQ+gwwcH/Rryzo5/GBFxw19AFqLHNl3upW9U7E3vQEqyqTrAj2jqNS0ie5amaTzAeeq8GlAAhyT\n4Q68l+Kgli8s/DruaTRRbq+COVBUl1ypz9aALsdCm+AAEu8r2Zm8B001gG8SGF5MtYNdpCEmKLD0\nTLWJoREDFIMd3VG9P30XttOvNw7ACmezwBL9kIg2B5J7AfFWlDtzzctAYWXJ9ziYHrmGrftRhtUY\nf+UAkKKkitpiOqc6tym0SWgfVjUo0PICfLbL3dw7gk9lpTBd2KEUmwvw1n2qq4MfX7Rk6GNf9c6n\n9SYqpIYH3yHFxVcQNXtqCyDkTeOOcJwnSzBgIkQ2pYZeTa3XblE/lNLuwQEW/Eflz6ngjYvAQl1H\nqbaEhKVgw5gMaKHItw6ssoZF2LR4nNb7AYZMe+0uQnquLrblQDVeEFsa0wU5kIZMPEzIC2wAhblL\nwOlafjQ0qtiJGaTrEf5675Y+k/uHE66uoDsqAPh/UzjBkfLnbADu9HXfXRo1Qq3zmY7MgIYQWXf5\nanTXt5OAHzR8qFm+wMC+6YdFeexacOrCf7J1ZGqLKUYAwq3okf1LsE+c92OCzbL8Tmo9GAlBjRwc\nC+zNzEu7q+//gpMh3IQ/c7mZK9jIUW+97WfY0BF7wpeO/bRQK/LNr6fgp6R9YyyH7PZgCR4xKNwq\nV7mEoikdV7iqwHo9n2sT69TzIXWaeBE9vDocrGJqLVWnxGog8fGb3Hhi1kkXjNWa4eP83E9FkWXQ\nWbK89/CyZcCDehKkfEw7Toc8zsKSn2auTY9W5dgyKrBbd8dgVqMJy8eFklT+gArEQ6+FurOIi3YH\nmMN27F/jcOMPGb1rKABJspBh1Jk+r0nbwUiVbdNLZbUCWcziZ0nZN0Ke1RNVH8s+0QhiaWZkbBne\nDc5HfTQy9nhzeXqzOEDtFsXxThY1FvQzRhot0TZbEaGKMxEelqn98my87UCRCgMwVY0CpkL67yKI\nh7oaFBkAqM4Fn0+mk1KpfMyU/XVuXorT8I592Hw1o6zDyGVVVXu8lEY+nkznUx/u5+mey5S7gkU+\nC2Wl+4E+QschjpFvIx8NQUGt0kbRTjmfzoh2Nt23sbcFadhWo+wQKn42iSujS5blPcipWKakkeCk\nqMrpjvcOsfSwnW19BGFJgyIPTT0EI+F9CzTlNOba39uMDSqys9o+hbyb6C5bgutSZLOXMd+lpZRJ\nZtagyr3nIckutoN9jqDtTTDzVXRNfj/vcZGEcWu3vyqFvIE06doi37dr0afGHlDqNJk8LlGxaC94\nqJcxkmGRzL5nURskmFb0Xp7M3WyjbJOxhxqZ+JYoJaRLizwrq0yHz/kDdbKjJMysU0XXDp1nTfwA\nAzH7PfGlKjwMPbVcAeM3OOqpRZZziz2fcpNyw+7rAAbXm/Con11fc3B68ahO0CUxmFqW9klw91X0\nehLt9RCmpxw7BChHUlP+D7TH9G7aBhWka5w7J3nOQM19oHAFLLYQkeRmHkkFOCE1V/Faum0rpTgH\n7twvoPL3X6PhwFuqdWz/XlVwFn3JvCE0WF5h97cV2CdcPRakqs3qNv29Ud472F+Gm7ViKYBSR+9D\nqwqKf1KMUd5c5vTBUJc2dwAjN1CB2POC3wy10zCiroPctQ9ki6Y7//cYk8/puTy6D3g8plWCBbdM\nz3qVtxOYHFTI64Zqv/vIVEz4ZBOVoRYbyx02pH5hnBvisdn2AXn88CkJpGIirvJDPdhLpjtphNwJ\nu0uYgRUW4v+oLFAIYFRn5HaaMxdX5gtjQptZfSUHixkkEO+1JXcgFEzNx/LO8I3gVqXTgSVHQVHL\nC98nZn3mp9r9dukcm7Jge0agNaEFqGecoVTrDh/40akXXpxANsd9pT7pyLqOm+BawFUVsXWvHi9g\naowIxOq/0uSrLwi70qsrx+vJuz1+xyMnSYpy30ft0oWDex7j9xHKProYlRnRv73QoAV/DxcnWIF1\nRBNRIpvMpXaANY3YzGBdH/OG9QK/I0OcRc3/M/qCyTwqh+HS0DRcp+Qx+B7sju4OVf6op5ciP+SD\nJHleQdqZPgI3m2ahmZWLhe42+T068LT9tnaXHgtuYB4I+a2pzMjMzOJtDjU6G3rIaP+4jHqEGaXb\noqU/QHQrjRr37R6w6uJ//uGvviZQ66TmW3gHmniRBfBvd0ibx2Irlk3NZ5eo2MbSGYKTNeqtlHmR\n1s55OmAmXCjVCdtCkokeOj4YY0Z7Jf4koOu7tjPoc0g22BZQLHSP4kqTd+tF/rFNsMv3+9/yF7sL\nqMEN7qVUOrc8t7A0851dUYVApDS1oeBDvMglv7vQq5cJXCIWTk/86F/yRyc9Ke6sRvCglvmoJ0jv\nequqKtlTHLCuOJq4Z9qPgutgU/5x8E2O3HgaT979n+Sb+IiuET84GBunnK605+1JfB53J0zhFHi1\nJ3mey2smWZyHkpXlnSwMC65s6jwLfOVilP49OSHmV3O+uEN0AYvMis870I0wh5HizY45J+XXlFYz\nELfRm4Ea9nIQSQkviwJQ/uC/CKKZE9sX4iIdhU5+BiXVEPT/lgS3CBy1baU4SMZ7+SaXNemi6zzz\nqMqupY05BJvfTIPVIO8aExb+fxq7ToPdPEG1QKFocQgwOslx/hSzUc6bR/FQZ/za/XYowQRrD8zv\nx+onow8nCSb30ryTNIhRoqv183eXolZbf8KLfUOK/YwlpteNOzlQ3VdZEflQvbt4s788N0lMV5QQ\nqwyWyEUJVru2ShDGOZHTkn25SvQty92LbTIS54vkU15sFbPCbntdf/cCigr/EuTjdRNIpTmIyagK\nJLpbRqkaB4Efc78NPcDJamChicRs+Sdek5UbYLPmQBPUE/snEltGnH47uYp/OaEUtu69GNj9jtyD\nF9NS2lHUMa8slvCG24e15oi66gkpWLDk0I90s1nWpkkVJJzM6kOq/av6GbdDfNWOCT6emtPiuy7t\nFpiKRPuLmJ8SR57vTRSJiKc+VY5QlXfN8d8qlyZ5khFAtuL7jvkaXm0fm2NptJRJVo4+KIjlefIt\n5tRioY7eY2xFpnowPJO9b0qzfwA0eX7qJntACMahgPwIAIA8MmNqW8TDGNYxs+uPMOIbrbQqLIpH\nJC1qExOfnxej1eKNHGX0UbA1wpU77/GmTykAISihgBCB4H4KBp1DiyMd7uZeclyTe+bgiLDEz3H1\nQxfyLuCKInSVZ8VPUOm/NxHZcfPziw2elqZaG4qocWA2MxY9O8AhtE0izX0AOb4KUvqf2PRRrp2+\n+VTB4RL1ypVJ9ikd9OBTvIHYlLH/905ebXIC+i1VXqFpWWt38OkSpj/fYPocn0ASu4/2bZZQm7bc\n0USW4l9rx6+d3WU4ex0WHFmf/ae8FEDGaVF6vNv/yM88rxv4TzOqnrdt2kpRslZIHEigGgMtUDOt\nKKXmsoECwDhveO+PVys+nsgXOYHoitjt3516es3HFS6FxlUH8WplTsgX0uPPZ9KtEAqPOtya7mtg\nR4t6p4pkSpDB5wY2E/dZZN3Ye91gSg+finke214DH6DlU3yPTOixQTtsbd40kbHlKxaiyK3iPyH5\n/Qt5GYC8SXdRX45XcQD4PA20iLLctTEJsgohh70ZCbWMTDDSoQgnLAj94p8e91/7yuT3PBCBrETX\nKhQXskXzKmi8q+/GRXVXMw8IFTMFgnRgfdw5A2JKhbp85Hzxejr+U8rfQIvg0rv1zdNdq3cYTmDM\nIzOrBm3dl5RoMU1rwsHzKelRVKQr632MgFl9CAJdlmkbLszAKkSUHyJJcl1st46oY7GrkrI6VPwm\nObwLoyrECdKkKFczQ6Ahtuj6DmVcLQgz9JR7xIfTCiMwmPYC/TVS+xoMbk9xc7KvpRPmiK62/pbH\nIn8ejo3P+EAknE6NQXRrg6zTGskuUgs5jJlpBXFWl1RB/YThfNX16yA7xUxHcsZTqggcQguZoihC\nNzK23WCcFOs1X1wJKbTSepMEKA5Tn8a04YkvFN0oDeVi8Wagui6BPkXoElYI7KhdlrRNnJEe+K4C\nmWuqCoi1OXYJy5ddbbrGBPaS8V9T5uEUhUsuwXY9oVCfL804qhAeRinUkLWzIinPOLk5n5x5JrVP\nZ8okZPnW13mwyX7XaRXUNj62dMoNLFPCWc8/UXUR8LPbtdU/cfRSOj6NrFPCq4xcg9G/njsgJA3K\n08cNspEYKmsLaNJdTU9nKABOVnEOKX9HKlY88RcvrgcAxfrMidg/3Ps0Zr8WPoK0ajTiBz973R3o\nC13XQUZpXa3N6jw1msPPOnO5RxjJbjpzQ3uoUt5VhBrUapwKXlaNCdAMZ2JpCx1pv0Vq7/uOFVT0\nOBmXzWx+UfNdQpB++InVLO4FrCLxqT8LE8yfiFDXTkj50ku2ZNVHZgh0Ac4Ses/r4BCGXKCCy+tJ\noUBkIaV3y3+82pgdpj7dHPi1DyPafFfu0Kc6BZwAHt4t8KNk3wDejh/hLs/uv/C77YK4Nb5L0AWr\nHnkds7pieFdS0esjLgYrecbn82ZEGZ1AheY8HIX7lwLwsZWsWE9jkg7hbgWDG0pPur3cWFd8ZWQr\nTiZJtijb2FHDwdf6Zsmv43X3w2sfOkg8deoClEBGE9rvUdqPaiocZD9Oc6hAGOpI8xlZgIGuBelp\no5SWeGzoYJmHCknn0kuadiRacqwnRB3VE1/SJ491ZLMOZu/MaUf377wd/SU0etI32vJ8feRawxKt\nj++9EURxtvDGLtmE9Tj/SIklU1tAaadPWLYLckf0YF1sKgmoDKVWPQoHYYim1qNL0W+XO44PABOy\nyMQQqoxKLP94ZJzbnlemCjjYJ8GoVQePZg2kh7m8UOPBE64P+iLphk2v7F3lYfzPFfPWZTvy0IPY\nzv0+a5E5nnCkD32GHgy/cMrYr8759sprdwtWri08LDYSjO8mfZpAgD5G5ownFZbII6eFNhlks2wJ\nXLmVC4wK2IE7kdKE1vVO3EF7pIA63cqGvSAB+HYbsca/XkaVzVsZ1j9rMymY9jM8DqycqT7Cm2Sj\nGllbPM9GOIjvwXekmW9AplvGT9ikMwzV72KlRWgGbyufSLvOfzXefWUE9S256rfFw0QOFyS7EvKk\n/uDYptVqTfLysYpp7IPTNBZWFr/jwQrfGDmOf4jlfmHm0E25e2BVeUg9oR/WaaXpQ21fJ4NkNSpr\nUk71jEfPfYmIxgBTVSwk6aiohULZwT800pe5GgCxJg6St2irxr6gnMtZT5rqXdJvIv5SDTnL5IlJ\nVe+nLDmq8uTlVFi243FbJvaE2ktFiudAj77X+5njmWJMjFR37EgInG4HkG5QGu56pkB/KFJx2ySu\n1NREkpFNGFVC9TqKoqi95arlXIdYSfm73u/XZeJfy3CIZRRKiYsL6/Qgf5G/JpyDun5iqBnBO/9v\nre8qmKI8/YxtJ4MbQeGnm+SMLWT7zao7BwrjXrTOQ5In4gn9hdN8TpEHZdWPGBuUjHeGQCb+Y5O8\n5rZqHliQVmjIHjR+BfXIEtG649djQPyBZ9JEEt2x030TUR6+rGTvURTdvknaJE7t/4QK5e7Cen+r\ndC5KvZEQFTTYGPB1mOxWIWYcOaN6NoL7k/sDtNtX2Gx3hLl96FrKYOUluXxWJZVhq3aTNCD1yaaq\nvYUknS7HRbZoQ8puuGEADuLXCdCggibAHZkQoQz9DjNKedJgpKJ4MkcfVoOfrv67HuXr4A98oBUI\nPDEAXq9sElW2RuyxpXCCxTBn24wYLwQ6P1n1OG1GpBBOEapSC9/5mmQaawTy6b+EVpBj0pRkeUQw\nvb/iZvAdDjyY2pmOo2hbbJfp3P0VpX3MlgLMerJg9J7vTg+EaqVZz5CZ3h01tF/ol6/RhKiQhWoE\nnSEDNn9qEBaNY7wq78bI26+cyIS9U7auIwQ4beGm6i14In2ZpBH9Q1ZbSlybU5gKPFkfPaD2pMbc\n4QqauXDd9AtvZ4QImEXzUf0w+dAsqDgbksXyJXLhHJm+J3UjxCPq6Vo7pRMs4jy8v46aaTgkU+9U\nz3hsIUP/AnGYAzL8sdiGLTYGVpfcj696k8kxvPblPl+4vrt/1B0s9NrDKWePT7920FI/+OFP331T\nfTVLF5uj5wIQhizcVjKU7FJURK/TDAhBxsoazIslKLOjpbWSVnD0PgiQsLrtYmjxWWOa3Gzkt8RK\niQDZf2LzSFbiR4VHK47CrJQCGrbb/CLu3wEevljPAGw5eLfjmxgrCgWHbhTNQBRxe8xZglphu3pB\nDEfMYiBsoWVIytbZgjHG+h6nEzxFVks3g84tu67+5Fdbz4EXqui31TdCBLz6cCuySTtmKzFwJW2g\no9MJaAjdxYYsVIRXRpq5adE9RVumR6wyjpFfQEvIdNHvpHlVRGjNBGzxlI/F99faIvW2mnmk3y/r\nkiQezCL7/vFl8We2eJJJX6iXuYpjy9jeDm09cQLINu9Ni8vWF8NJvFKnCmjr4f51TB1QVOu0DLtS\nTQOkSfFTCJWGc94XHdlmowpWh+97n5Ip3J/avRivcnS4rb/mAJha/st6uQcQg65P9OdYFKGazvxu\n4doggqM31Sc9woH3MJX0V1ArOPUZAu9VmJogazTMNZkEaU43Fr92l9bJHu3a0gzd00gDcN8Ai3ZC\nwOw5f02kfYMbXXyMIAHtUsLaX8t5ZRI+ztxfey4wMagkipEEYo28ISRLJFZcTT7BDRRizsvRsGdD\nDyxRwVY7/l25OE/MasPJMlFACcGdsL1v/1NWdSonZhukx1LVMLJVn0BxIfeebEuEeIhSWQknwWaX\nBV7gH5lW2tF+hL38znVJHEPLmNFWtVIQ/JpbZ1Ea0YAarwiZeeXI7qUk5kJVesAOuXk2sfpIM3vX\n5t2cpZr4VOQaHdvOjFD11Dr4IH7Pxu7mhvkIpkwdMKoWjdPXQYRwFY5vzqdQ8SijViTXD4M0ETLp\nkq9MuK8zwli28jPNdBoFDvq0y8bDdaUI+vYCVlVCBy1kKOfLNfHiQ97Wyi/Uax6rwh6MjdGkJ74C\nKSp4IMt1vNoO9fkgNjYD4nhM7cPpboSk9nNKKi/j29AsFgXu+dgvtbUL/dE7+JNp0hzFKPilt7OQ\nWlFy5rArrL6dI8tOw/Bn+31OWzBcwMiqV3UIZcljCNAkAyfDkAos7fSZNpS1VYeowCQXAddoNOVO\ns1UU6Nc0lp1GcHqD+YLLCAaliX6scmSjbchuFNyjnGTykhv71mngPTaImOp+0OnPiSKxMhLJSAID\n/9ZNeTIYGDB7JImtSplQ8lpb1mMbtElc8zbqPQ1MLulr9VvENIOZVnZaUim+RbTwEZy29fp1GAye\nqtts90Cbq+STzFSwyB/K/mIW3gvOJMcVNYbhdEzPyuXKgUw3y8dXfeDp42ZGLN2pjK+T2+xAkPMy\nnfZdXtLM9pjRSkJ4oLg3OknJHelRxAyrPSKtssfj0RhkgXQpFkcnt5ybExf0tCoX+ORRUXLoHaSk\neUZERXtwOcqMZPud336YF8sSHpiqChZq95K2jfBYsrNYIoXQ3k6LftnMeHWbAy8nZM5FmyFRC/o4\npDv1SMha/ha0a8F1tbGxVVvlc9GzVfDj2fDw8om7CN3qN5B9krfhYXDUe+rvoDFlZRSDXUhoB2Pw\nzt6TfQ+Jt7svUbC/t+/KqBnNZVnrPnDcpfXtx274e26ma3c/xKqoPqRNmQkHebbrB6gOqJZfzZzd\nJcPulSBsMAcNrte+IjjG/0PJeEaaT4jlAfhoXo2MKkTjvZ9w4ufU6tSS6y8e/JEfzKoDJZAAEYCj\nQMfSBFHSuk9bemiaVwScU5TI+IlLopFBeTMvUGxmF8/NPX99d5byq440XlIwnSO1+6UTboZQJ6z1\ncefLrhpUxsjGsJmfuX3HXFPZiHE/6iwLSxNUVew+sxJS8oZxHjgiVvD9Rwnt2xca6ivMAoXeinaO\nAll3DXsO7SLo3e3NWA+E8pmTO83ENDyENc5V0viE9vWh32rKwdoJrOe3R2ODk6t0AAeUL/iVa5ov\nOZ6fWXsPqOYp8NWLPZD+I93IeLIXl1/3LHmgkOYq5g8WouWbPlsQ1QzjsYoBCQxsF5vIfGILc+UV\nH3s3tjzYRIIOQLaopEQS2XZZ6qC7PCVIF2qHaX67SmcGJgA2SCTVx1Nk59z8IFB0Ia1s5MFnSK37\nmXb7aJFSrmG8xMgkQ7cEjoBIpDUKneOzXMm3uMpa9QuNlnDcHai9BzWrBF4VeWYzhgj5jMzAkiy7\nUomh7au4tb3UwpkNwNk+39Ux0Qh/XaJmwtuJeNrRCaZBTSXuzBwUrxE/zOKCzE0GIiT++ro+pwsV\n758X6/CwOQyYBWOZWhi5gcWUMCDfqMqbwQQikP0om+y7kKmqDhtjgYFBvDku0HSqZE1sBwo/39DN\neAywwx9wz4Z5Xk3F/4N/QvRbzdyeJxiS3uVJo1KXztmmpTalHStgQ7lEx4jtQKEYFq4EOeXPnsWK\nqPCKHhQORcms+RJr8OOMlo5CBHs76ZfItnwxSJGwqtbeAE8hHeE0m10VrvVfKA8z9taIN+6hFcOv\nTYRZjig+bwJ94FJVN53oRI7mD89m+TOgb1mJBN6nm5Lmb4GnNBHVfk4CJ9sV4KSNUqtwvN/ax620\nkezUzoHec8EIqipCoSPYgzoF7Xz14By2TV0aB5twkl4oYuYQI8NTrDjT2yya5O4JqM3A9t57MBTR\n+i3CjwGRw5atDzg9vbgJGAh+6VjFAviTmVmJyj5scxtyvSBp/hoyuJaj6gRa//Jt/vB0YcRa8umR\nR0XJqmFQCFN1UB/dWlMZylpR/aqr3qen0OF1yNzZuFf1mgbs+NYkW5a99+dZM3JinXu5vAyWmAlC\nQcA3Xlifd0XutK5tiLHstNiXetBfu/icW4Bvb8nEZMLYRbfBOcKR+mNPSkK2PCGvZJV/x8emgFlU\nZDBSQSJB5PyI2HZy6XgWEyzVHVKntvbfFiQxvPNGs/aNGFNqw1Xm7fD5+MwDFOY7UvwzJaxX6tL7\nw47a1OfTfsCPLTC9vrA2VfBiYHtZXXNUbIJaX6+uHKUf3Rs7hPdzQM3Yo+L5Piy7F6Ns8Z/nJQ3P\nufWIcBCnT4u8GLTAGVf3N3ZYtrcErfZoL3Gp0rMMK7d9IGVA5VXX+JFeYez6gx+MaHFVdbGs4ASQ\nVw11YLC4zmn2GiTkCRXIphozLS1DJsS9fgGuyWzrdIOJM7Xw+8sDcGVZI+vJOUv9NmPMSvvElx5r\nvnaZK6+NpLYt30wYIvp0m+qeLqZwKQzADILctIXgWaNZ7NWdEXYPH/zyeyMIclRiERPwMdcdkI4w\nl6U405h3IOfOjbLKQX8p7tZHgH6X7866kL9OQjipTr3TcwZzoGA11DTcGLkaX7Ee4s210Fxwq64r\nox+CSMXjn0eflsBmh/0eTYahny5p5qQoQtu+ntWvzJh0dOyo21rVA5lk31ZWZLwg2aK2jkAIlUzY\nz3ex/hoo2LArSYhT3DxN3D9MFKBwXmGSF0z/GnPfeIshqyIpfNvhDZQoy1vV/R3SrMLotbDMIPeQ\nMYAi/Q4LADryAx6uxV8eZMNBa8+bECDnygtCv9q2dM2vYWhFlgJunDVJkcwOd5s9+f8Mz/o8J3JG\nvoLamUN9Dzd6utFFWB2AeSxRj/LGWDP/Dt6qxyMjZNXGaWVnzEBwDAqMOW4dXK8uY/2rlm3LydfR\njIL27/4XxzN81wYu1LwU4YIO8UBoeQWTsF1TaJ7XEE6FiD9ON8GCzyghxpW7ss1sbkKOWRXhgsPI\ntwhHp7FtkvSUz0l6SSwgnO+QBTtflystA6Yt3Kat8tgVj2c4n/iFA3AuOqd6ZXlyzpm4ZONaExwk\n+y5/1EilwFoKY1FPmjWNY847f0zRJm/sRrfvgVXlEFSAkEY8Ab3AJI3g/doZaF8gwqReq24Wt+m+\nt+G64J1DUh6GsELw4hCLTrNSH7XtpvDTEDw2y7X1c17+ooH14WIfWExWSPJvVqbOSU8H3Kn5gARn\nmQOqZOTSvRcVUwKdb/h4yUdGQMS1zErnI8SSZSxQVJcCxxVktqy06iN/wWXMI72fn9ez7xG/T3fN\neI75grIEWsjCgkLru7EdSAMZa4/v/XHI8dsBRDZH/bxEh6rhV8cSKrWMEQA3xOfgeV2ntcKB/rnP\nc2pc7QMiGF9NjCaYho+h2MuVhnrQb5GgW/g7eJN4fK5G3kyBX+6pTVMlUqkt7Il0RJExyU15EfJ5\np4NebZH6TLSItwuVIDtcxXcrc06DHo4lxACgk1ObwfPFXU1OypeVx9rsu1rNpjoUw5zDLMh0xFaY\nUi+zYdg2dVC7N7Ny4X2XGUQQDYkrWiZzxxmoNQdSy2PbDdzvMK4qg8n9Ofz8auoam4aRh36G7FDt\nRLfz/XjuKOyAW22++HYdjGl8KlO5gTK+lk+BDJoonYSBGQ17rq6zsRRApaKXLCoCPRyj7+jrNH3N\nJ4I8fEGZXi9La/5eJULrVK93FgbEjVLGVMby3AZ8qhPD7lfRM3I0xWxrUvYxM4xJQfGF6/5Sch25\nJ4cYiBSLWLzpA1Me1IM7xd6Im9dMraMwxhDb0EMKigaHd8kiQjzKKk4YLwVfVRAUHoHLvBBZw+Pf\n+siQVQEJIZhBfnfeVuKrKVO/UAn/fHkvBh9QvBV9XMgMDX1e6qXS9cr04LriAVwp2ZVwreYL28Bl\nAa7PFwfJZ+17uprrSNAg2hpV7CFiaHVk6aZ3T9rEYTOR/5Sqp9d43O2VEr3ziibiRwJuI0MssW6T\nBIKwUXlUQuymtYAfvt3SX2zDH6B5vTabaYhftqYItgRIS0x3MpFFdmai+Q9Ke4ycSJjXwFH1UQdB\n3VYD51Bf5Fkiii5LRu5nOWo9SN69b/G7dpgDLmKMkJks11pBfAlTK07QQnpb+ivSyvDpdLVRjA13\nUqYoAS7ZiNDJIYGJd0LpGZJit+GsdD8mbGTPqgT9+yhMSv34YY8Z/4texN793JHc9b7v/eZQSqSo\nbMZQ3+ncIuVk1JECl4WM5kRF999VI8WR0T3bfs9RCZ2feL00nNJ72Sfppc+cVWYPGINGA2Vc2kJU\nXCVdsCTjrKmmTNZ1sILGdZfQwM/OD1YVZb27cOFlZAEIagc9Jpf0Xz/Q+WPmx744OZQ6nHhBHggI\nhYbmMFMCSQtTQY+1zhqsQMkM8bwf7a8/YWS09w1pcmsGiaG7bhu03MqzQOKowQ25tPRCxXNWfpK4\n1HqXwtm6+4N6EPwJgbU48YHzQPRHN1MPmFcGIVx1xyxg5pW6OZTxuTcHTneCIQhoNDnbIxqrLpLI\nq2lopLr+pwl7j7408GIeinqe3Q19bGpCvoRKC1XS7DdxBjnN98ZUGKViRKI/uJXv4/UmtI4ZsEf8\nYBaS1d0pCmRNBdD1N8g2r5a7DZMCxcdZxkJkjRqywxrDHyTmbyDEvue1B4Cgy82sKke4vXs26b81\nGGKeG38RToNiQdmL/E22pWK+3Rc0MZiYsIjcB0cU8BRtWWbHmiBU+wj+ZkthkY2tNhuaaQJk9qV8\n/uxDP5nuBRHkNqJe7WJQEF64a6PcuQ1FHoZo+gZAslXcne+Syh7EttFDF+2nfVWuxAtc57bjV3b1\nBC7Vbm877Jw4v2+JU95E22OmtylGJThZQvQ481q73MfJG6Zet199bV2zIy9he+JGjyixmMSMXbJt\nSZT9nPDehGnACZ3CcG9bpSN+hr3RuOgStHP+ShjyilhsQIlhL+Ah2n7T6qpeLG8rnWimoLqXEt1a\nf91R1D9qe4q3ZBFfvkC4xCOAM+82vZZYLJgEOgy/epi4Nvwzr24VLydiJ6V1VcI9CQQYRGmHjnU6\nJqlM1PBpQoej3oTt7CbycEmeqWhj7f9pCONY3MY03UwSbTSgOw8Vkg7Fd5rmBrS8sK2LzjChrZMP\nYJPoYx9S5tzGnzLMa3heW7/xJbvOrtM6a4uMwtSNIResSJYafdgaEkEr8yXkCBj7la5ic1Zuivl0\nq+UG25iQxtq+q7FS04OjkkPAVBCxDN8vUfbBmAySYOTIUuaGeFfyyN2YHZEWhOQ084EUmAutjqEC\nftCzaA/KruK4NpFyFj6QLYXyUEfVxg1dqd/NoIQzrk4v/Gbi2krnPjmmtDoJl/esKoKoVEKEP7T7\n2WK2ny8CYKVCiaAUuuqbGqJfxrF7RZ7bV6dAEDwnjw4HPgGDUgmI7tUJh+NWUqOsioGLbQU9nPUq\naorD6kmAFbnDB6cXyR1+amTIm58CUK2xU3ox69nbN20IS+awjS/13sPotJR0uUExaVTPzWOySobU\nwvZ8RkZF5r+Uf/it4BB0Fmzo3Fw1+/VhWTIx8UWDwuK8g4gx/IBPBy+F+zj14a81ERjrPDzdttAt\nr27gZyU4wIzjvGosA4xdazsAMpo4gQrFKp4mvFDdLxeNhyvAaY6bYUGxjbHopu37gGQXVTcaHtlR\nD70yh/GqYbQTV8B7bYW9urnzZf+CsAm0H2/uT6UPnmSGbqo/4PanLv2MwT+WnxKt+55E+Hd+RJEQ\nRoaITP6/pQSj+OhuNyleC6C6WfnG9gG+KZ3knt3vKYqEwETP/710F68O7aO3wx65kUz3GvO5BHRs\njAvcILfzQ51eBCt5L59RdCh5p+sqULo0nnbQ62MfskVeqD75CPb5aWeFegA/GPZ2DK4IzDJ93khG\neCx0C0udLktGUxhTTENdhr6+EI9M+qqOHGi+w2s7k3YAFMhEg2gZkH1pQ/Lti5S6/fSJkIGprUZF\nMSY0HF8zIJzNdP+nPg5Ep5oPqQINoYf91wv3lnKJhDvkgus5U/6u2AW6t5ajMQSO66+CpQ9go4z9\nAAaLz6Vvg3WGEbsURBsBHYlxriFZMvd4AFCRuJLVL2ALAwE9n2JnafW7ABCoXU1zeDM89SA/pYdX\n6UNDkixcteIKsCLr1ow5IY+0keqzj17rQffRqnRoynHwNHmAe5L3w/YQjV2Fcsvie6HMJCzU7eif\n8rIGb9A5+xIbH9wGKzYf6C0qMkQJPtR57qGn8FPh5ew8D0yV58vs134882GB1R0TsgchGuhAB4hS\nF02ARP6g1+HAxfkEtuydedbFTI3VDYcQu3siU22+k/bGJSwakwCDAYDcd9Igw7o0+Je2EAxOUzWj\nWj85/t1CezXwV6obqw0My0MiOwOq7b47gOZPPm7U0ofgWuPtjF5IoP8tI+zl5KUniZhUiyAHWkbY\nhpQJHKY3g5rG4nCHfyQsUXpbsl6A7PZrK2xS0AWNgaAvylsBY3pO72VKlcyiHE08eVHJgRXV5EoN\nRpmAyh1Q/0JJtSoq89dyvLtuRSprN8z/IbSMDF7PlUXNTg+itYj8l7FeNR/MJg9WhSTBfbXJfFoA\nn7GO5LiygaLPEthau2bjm6QKxiGwURpk2cXoaboeFIJ9LdIB/CmNXCJcHt6Ei8av5Vael6RTzLB7\n+VHihmz7rm7fFxYJvjc+7wZGuz7IBRnyRh8iuSIsbV66EEef4/a+ySADgOvrGkk+SdSnoNdrKxhy\nYpeExPq7qdyH9xHU17t4ExgsnKM4fpNRlYhthYrhM/66fPmPW2BFDM5y+Slfqw/I/Ee0nNdf/Jza\nSm4naF4uvuOrC/NBr8Ds5zMYPMzPrjv3n0cLQD5VUf5rsDbS5vAEmIbfFvwvrll2sjTANP/CIS02\n3hID4NEJn4AlObA2USUa+ZGzd6M+FOAMruWWbgOPESmKKGFvqxU83lp6SlJ6/UZWYfaB/hyk6lXe\nexPtlo1YSu33NzrvyeBF+duJsj0TCHrSN6/t6sWaC0oUU6lN+uTmKtaMg7fINFO11SdFwQ0CYK6Z\nEy0/KjIK+R9r2KbfLausSmH2pdD9heLun30ptvC8SEyGABTlJWufcwPuiR400HxAOs15EZeFoPnD\nBNRO9+bsjfV8fdgAvKPS6/chTSYn376GW/3AELRomNaCxWHeK73tlHCh0KzI6BBxaSVMKv6Bbdt2\nN+EHfUsw0rmjQSGzMgcOsGvGJSobOkD8sx3pbOYFiQnlqtdvQ1wUpSwBu2TXcT0G0h9NASl6oLJh\nVt9zZXZrTpCnEMAuyCyzqIsOldqBdNQZWc/BW+gsv0g70/VTg1pKT8lMFJ5EyOKefXP9r6coFxUu\nWWdV1Fjh8bBO8SCSqJw3BTmemen7zig+6//BgDqE3fsJJR0gxpm2CB7Rwj6Ttp0cy6ibWWnxFm4M\n748QcGaEPa7ogqdL6miZnYBX5FXdzsHc9d3io/hzqZjSF2aD2ftrMgFMuxWOYsem8HnV5RZ7JF6+\nyy4yT50MHAXRkz3DrB5sDemO1st8nuETwAxb1n0pZiK7+QP83TXKSdRDpSR0zyyP6ZxNlPc12cpz\nh1GsbUptAsO+lJgv/8p2Wx6lyqWJbQmQnM8VbHJR8WzjNf67o2n17koAlspf8B1dB9zB3rkDE+Py\nydC2RAzbrCPV9S0W1bKz3oWjve7SS6jlIWGqHqg89FIw1iKHRD9W6zDyc+P8/ankkPQZj27BqmeG\ngHbSfa07EBu//h2MJIMbt+Vex5KmhZDcsf2GZm+TN/M2Ko+sZPhLOLHeEEzOhGkTVbz17f2xpV4Z\npyQL12V/KOkUjLU2r+yPXTcjUhlBd1jKWH21IYQwxxW9ud1bdd+vQqKQRhIR0HO6cqT1yLV571VW\nkSjshxEKVMllcLTNju+Y32R3N7k/QoFwx/h05bvkyJSJ6ifz5qxqrQwudWGJojoIgAJAHaGBazyd\nHmN6JZCtmUqxM63ZGY1xE9mrHXJ5/nqwQeupIE11Yg9T8gqRXbfYgfZkrGAqGKf+GZd1R9cEYPs+\n9QNpQMCOr+GUhABocmLLme8Z4DcJONv794XdlNQcXjPNKd+xKhACy6yZSkVLfLUV3WtzCcz2yXEm\ndAQkvfYQ4Wt/jaxNP2VGr7ttjWbMfrdBSOvEkFiF6BYQfT65WbK3q2Z3dg4vPcSMC7WsICul88zS\noMG31z9R0CzIPrAQYgEdw2YaqaSiWB30X0QJeBVNoTK/RYJlGU16rEUxAnGO74fKrv1w7LfQYzTs\nbbsZG88RVv//Om5hxtqL/3larQCgAnPgRM76qZBDVJ/P6CnCuv1tOE2wzHky4gdXIxOHb2znj0NK\nCYTyoZdfZQD/ZhVNBBJYSrpmIT7SUdA3/nXQdN7PV16gC+Yvksr+2oFQyxq3zMQhMvq1b8s+YtEx\nfqrJWTvAec/OHlqx4yH3k+Wt+q1bz0wJpup4mhr0ZXcoqrHDVg7c+6mrlqL3EQTSY8Vr+pLNHRlp\nuHciI8k5DLLPALx1S1MJ3Ev5UAfze8pkPxTO/t0XXeapVvOkfrjWvY6vZJ5S2bkPi0zl7by+qv1l\ntDgtnFQ6Xgsp0F9dRnrxSfJUF+k28Esxst9AqW/m/PsQaZwk2Y4QaO3aWRUiv1F5C9JCskFfC+Vr\nTVORPpYwse45Qkwkw7lJYrV2MOJAFWG7YgQxy+y2jH3quP/OkYtViM9OObMPvZGW78YB4weMkSSY\nlpjVEZrDnOIIzDg0mztttctDxF3+S5ne8/bp+VrQZ02nA37Ut9kOwcDgDSPD0WA7xrQd2Zyv3RY8\nVtYcg8HwNw9U5PlP8G+ma3ZPOQ/khPyjrCMFGDNa0uaFsImohSpQ7AwrDHlBcb/R/Ovqghe3ZWzP\nter+g9jQirvFw93a9GywN90QPpAdjE/piOh1QRXpqs8oybJ465K7SfCKlZvzy/xi2mpOsUy4JX4a\nXkLehwTrm8PKr5xPTdY+W3VVl0jTkBpk3Od8YXyWaG1Wuyb7zFpvamTjuNQV0HjEYKbOcCoLUQ7R\nE/TadwVsATgcA/RT9Olp7duLLQPCtHW2JV+yLhPbw2e1y7UkHxp43y/qVt4Depb88qDKeW3n/nBL\nBcn5yJK6gcghN6VT7OZsGkppHDqr26I6dy8y0Wsi4MsWEY8EeogpzxiCdbU/4CbxIj+LBvzZJGbN\nyj+tJ10fUzxe8G69h0KccWc8MbSQPHIgNE1LyeQlumT+LJKXxamdfzArioWr1MurY2i2Gjb2mp4h\nq3AMnSPQzlzyZK6aZ6z/5kszTB1ivRcW1dVJmiJfaNhb20oXHlFWZJo6fzM8No/0xoT1jJhLwR89\nTT+OXqDfidwADFTILv0IGfRvBmFxpWmJ4dU2u7D6xTOUJxnPQr1UrFuzVauMmJH1+NfjRTsG7K23\nN4Pb5NwC+RMlHfduwDCKdnmlxXSHg7rbJabfv1d1jr+Az2i+B/WSCRpJHLHgaf0fPQ8AsTFr+J9j\nhfWy4ASP+3a4G/hDgQxfnHA6piZ3buA97bmsZHnMvym9t1mz/33VY1FCWVuQb2Qg7BCoVa/cK8CX\nucxzYdF/uXw3NHLxjWYCYjf6ebU79Gze6hq2eGllDNbnDgzxfPggO7mvd1IuXPqoBxCX/ChIwOZc\n0uiOHpydwcrrDEWRLJRXLwxWAWpyEghYWoAor4TAYmLWCFzaW8f+1gZf9jBFquKNPOyI4MW92CTM\nymcivIS394HuzYY6JDqSfzQhdu7PbwmBugTllXKZ+d+3Bv9X3DMaamt5BpbigikqxLoypNVblEZU\nx9pl0Px61udOIYyHJBDFBdx2UfZTfnxRVW9yfPt/s20FuLtm1+Y0UKD6jxhRlxDXqwxp5FYFL+nQ\n95wPV5GCJc//r1Jetgh4eSqrwLjCI8E7YOwTNSTXWDPiAkCcbUaoBWtfHplxQ/VX3Y/B8X8laRXp\np2MKQn3/mg7g9VIRXQmCvZA6egTHNnjA6cOcf25bu5jxNYG9wQlBVGyQqDqCu/324SkCtuojxVft\naI6tH5gWfSGTdfwLqM+btxekK7ByTkY8zZHOs8SN3qorm/TyGf/gwJaG4egiiE8CC6jNbU5rBSZ6\nwHwTb32iBq2A1Rv0ikhwgBAVIHoMMBjC3FGhtm7pymyYzh+PbR6sN165exVLWOpTJBtVybw20aye\nSGs5Q+e/t/Y8E0RNJt8DYEW2+mj3tMwlYOPX11onHjajlTSEq3D3PdqJymjEzBt6oKBoCZLYWbKq\n6mChEdgI/B+OzULWBPt1W81dtLoGu1YUFXkGrGRE4tFIMH1rDmW9xiue4YwYCEhYqQZjPYq6DP/J\ndl8gv7KCHfoHPh36Lut0K75hy+RX2PAIXlaf+gmAg2Lba57FCphPVmCekYR/YN8ZH3NFAbABN9Jr\nMwKu+nKVSsUYzI5+Xiaekpo0fgItaC2q7DydDbi2FlphSH2Ir/0IuvT/IoulAP6VsqVGd7Tj1TrZ\nSIH4MmwmWhsSNBPR8U2bxeRawhHHV2+jhe9zF9UzR+ALXLEI/6BXTgorK+YTSpOOZ3sZdZrSbzKE\nc8kxhvwTyonY1iCPqu2KndmGNCTz7H+zLv7GWxjKRKoVbPCPd8PWiTaGdz/9LbldjV7PmeRgi1zj\nWZlMkMTwuydZuuyOQbgQf/32AnYc29M4GnqbrK0ULEBeWfrSya/pLGCyQhMqtLB3TOcC+jvHMB2Z\nLCV8pFYq1HExfQCHmAmtWlY1ZiTiklM6q8JrjZ6a8kkmxXyp2Gw4VGcfCT98UBFpe4YTQZbbS0Jp\nVE4DAPhxGeTm6INH5Zdu+fyiXap+SpCNX9idd3vi66D4GbJuu/xvzZXvtoKkSw58jMAUasbDPeZS\nMiJMMet3jlLnyWTk2Je445ru6xwY39zyIwnX+lFB6uJTtaWXdtsxn3XXkw83vDjkHqffJuEbROKp\nwhThNQCyAeYPxKlHKrwCKEnbipcmBw2klLcNjL2FSmOW8yPkWmAfnU45jqlA5MaJgYpeTIzMAW85\njOlV26StI/nMX/EBdRi3RY3lVEBwovey4AD1Qqo/dsMFkAaABeFKc0pisu2UShkxZL+vXoZHlBEh\naiQfxw8uRhweDgkAIwoBHcy22cwj5PzBmrddXnR4/SNhw86Wa6Y4eP+VumB2gQuFE9vMC3KekDGp\nwbh2Z/SGbdCZeZ8+zZwYKKXGLk3cPH4qmQQnvJ4tLOwOZtR7R5zY9pVyriSmccXaltTDHxRpen47\nbGSC0sciXE3xzVCc1Zyg/uClk3HliIl3lXdOZ8N9OozPou+gAip+sMzoqv+N1XrEnUFAQY5QWAyA\ns7Hi37BspkWPpfFXiggnz2uPam5s4bvzxpEIrzCWqrww5XiZrJ3e4dNBK8LW0wgVDi26ZPIDtjoZ\na1xyLljhWmSSAO1Zc9OvFnT26FcM7sr0BCzg/l/8waR7SuQVRrjOiIhxsjeIr4CqjlMxzjESMODE\nehGYIYDFCOtJIAvH6wV5vdQlRm2bRdkAW9E+TspICKollFpeKBt6PwFwplYcz4nkHIs2cmZVFVF2\njU4mkpnfdc6i0urg/tJiPljaJjLQF177zZ3Lp5SOC21e53JzA1tupeHb6TBIRtnUQA5kpy9eQ3+9\nT6oXXN1Gddx+6uK4Q5vlykNod7t0eEYs+4xXL2SG8r5mlyhjPMqQjliT8gmBm6cCdcjjogBGpxG7\ns0UYarjha//ZU51l2k/nM/BR7hr/nPC5LE/+1TVJpYSBLbo+v7uvis6axNjcY3LFQk0t3Isa8ZAF\nZNUZxyhDLdMpbLlm0ny3Fa903x3+wMrrfQbh3stFOB5mwCDbmLPXSzUnI29Gqqju90ft3rc/3vPQ\nw7M4d3VyQfuOhMjTFu5CulZVYgpQj9TlfMwl54qY7d6eAVCl7cO9HEGJbHp7ofSxS8FIcXJjuYw+\nhC2joSQP4MJdCFM/epkpqEUaKm/z5WjyyroqymSmEsGeqH5G+lz6PgjFa8SEMdXGJKWt0hyQ3W35\nJSj/mAbDAJoFAc4DGqYNloReaYNO+zhDjG2/sIaHZft37xSSBBmkp0bFedqb8p+xYb0Mev9ysGJN\nPZvalxW4gqnlqG7QMp9eFwLGnBzgX5OrvHfK08sw91M+OP/+l5U6RF/rXqkcHhXDg2Lr2JjdF6FZ\nu6I6VD41uDIKAuRaSJphNlNiFRG9ABoDP2bD/2+/ySoOmP1JXPamfQgfmT15my3ymi+mrmhpqpA6\nS/O+TskdNiTsohRiMAWeSjlgMQLQNHXrQdxF/Xq+lVbglh0xwAnmE9iz+iLORQb8kglg3RafqLio\noyngV2glLKiC60rpZL8J/hKwoElCd3B+4k7pTNAvC8txBx+8IyOhYSOXo7PJkKUZU5aKHFiXUOvK\nyh+zgdOw/ksZyLAIyiT02JN0tHVGBOdiB0soM8NOHiTr9dTZ0SvvQn41ZYU17sFOBNFufGjpFXwA\n5C5jO8djcqfN4bse9rv7TWvPwiZe9N78sws8Zbu0hWkoHaWBk3hqt4HVWHOAfBvnkm+c+v5chFtY\nsxiEFRX4c45chtv9HJYKS06RzIaieOXbKdd0ZuebH71w+tOJFi0tYRNth3iu6QAYxjkoW1gZi+lM\noQtT9af7P2rkWCJsjMSBnI+3wwVipKgw2s9u0sJegBwlI43T4imnq/uP2Sr0m00Wfl1sFNJOD4HD\nY9c9ruyZs0SL9VeONJQ02oiI6/jtJT/gfODb+bR8oTIRzP5f12Aaa4QUOQbIdLs2SCIJcxkFM7sP\nsJK6OTcRzP41LSRpLRfp7vDFsI1IIkGfKxia4RT3hyA+RBZ/bHLmKmwtwGSfwXkvcM+aBQsCwCzD\nl+d2/XQe9skce34RD6WhcWIPIbhkVV3kM0hGfpmyn5PpFitT3wem3iXqvOI3rtJ+0Bi2+cLOWGFf\nBZxATHqHoDCQYLXpi+7v2wjNj5/QAlsljArOQJrejucxEJW71PGai3ZoGZULX8ZTyE1WKzMGitSi\nBYfh0+l54+vvbBorjXfREXiYK7MSpOASrvf4CMpUe1zdbwkhKad3a8CMtvWQKvGYVpmdYDhCRLsH\n0LvOWfx4J1aqGh6fYjHJFI8Or5w8EOySZTSoS8RBcI+2PWSIhPN6DmGBut2vrSGpTuX96Ak7dFgl\nK/TgwwrXdW/+Nz3mA/mqPEANGyrip7R/3DNqCfoILICFzT8NI4Npudyx+BBMSX8h/BtArXWIRPnS\nZXLsokkwJpr+/EoxpDnHG0vchlpOGfQd1L09R0t+IBwlFUJQsKszgbcUgWfObhnCKwXCp2OBV5SG\neatlA5dt1QJj0pqL9UkfNjjuRVhpqrB+ixJPEXeixuIhyL3q46PEQahMP4wHkctSXtfaaJXXynjP\nMT/a0ydj08t49x8QUpQNqcKxK51KMn8hWN45OdrIPqkbX5d+vptAstjQOncghBsxRVZzzNAJ+0Ap\nZeMUJJQuLAG1C7hIBAN2Wkeapo66us02atabsfuxTZjDgmmphTOwZOwpURzEKQC+2o5QXGrbA0QR\nN7bSvUUDWTlPwtZN8zqiw3VGkebtcWC/pSqwrTy2ElgRI6MlUmITcBk/621uj37i2sTg9nxXS9Ir\nKxPA9lSOQEiSOk9VgepII4JqWOUDkVrdfg4vjsipj1wLvltYZAF5Dvq4oRa1KhPgS6wdfFlXRlD+\nn1k1arn/k4F/JbRb9QAHa8ZEC07cK1uAr9EPmyTkRfNNiqtQ/Yubq6fp6eFLjvAI4pBWBcqZHPmu\nhdh1afdR7buxOfPm5ZGqkpZFxwx/LST9RDmK5MvDxCckQVWTFoFSBwKiLtYX2Q4dN4CC6qRQkxr+\nsLWLl9+gPjXFHS6Q8QBJCgzP9gI+A3zWlXzOqk0Z4p6KGPhi6eju9urYVUnSeKxUzCkEug++jLVc\nLvU9BOrrTUk9DNdezdS5edOO14nO4Mz6eBvZEN+zacRMeQi+iHwnGNQg/KlsOlELdtocRy6b4wmS\nzRQPUGL06NuI7eIGaLwQBqhSjcXsYQOwrYJbFmUgRL/XQaVddsq+bfqy/mR+go648EBO8GzJKFpo\nCJ1t+9fhv9V2EhlIqdYHn6iEo3B0Q8fk/5PPGBMZ5G44eNZohgyOnheXH6FjhyWLBxZ8sC/vLN4G\n+0g3bhgqZ+dGTVcrmXtJlWGT0N1XMgjxEg9kxNzANefeghVl2Sz4+c4QkpWvAOxptnN+OF3QsBsB\nQ1RMsuRcykpbzNJ0c82rZxYUeWi3cwJesbq0LtiI1hU9CQkNDfRFoMLrjx+14cGc+mATJVvX8f7d\n8DFcSiGyvlw0ut6arBIgSyW+4X6Ag9DAO92w5zdzahPezPxzqp2tXXT3ox4wqkhXUMefx9jMZcts\nx9D3nlihpgC0ni3IZCqC+cA29kd61Keb68Uxe0+FiO756Jcao+plg7ou71NzU4Rug96qrOthOw3Z\nlS4ge9MKWEz3yZ0DFVH8TFBQ9WZBL1rG85+tJ61vWenjmjlCqlqYOCS5Z3NIYaFq3jmTjs4DTWLM\ntxq/2IV4f6XKeWwSnLqH3DHWWvRrilFZe11NzudtLbZyfh0ymNbGTQ85enpN6rtfz2GQcooZtNxI\nurDOFMSj716fz8DydmIo43XY0R+THUIKLqkyOyp+R4gPCMH5NfSMmBx3N3S+6N6sY/2xcgudN55y\n7pTo7jjxsN18dlPrxdCAdFrh0b88FD1NsNyIEg1vuLuTK7A2Vw1Ztkf05Ikev+JNAjf3umHMX6sK\nsR6wvrBO5hRo91MoiTBcMR3msJYYF7sFvYQQxS4CBB5LJSkhwhgvZhlzvVTLAYrkZ+DC8C9dlV7/\nrXyAgAHRkuX/vHC2QRA/BVaoOLrNylbfVrf5gz6hKpMIsLnivIQkYVPuOGtHFctwPUzhOeLfXX/M\nOgUYsAxj1nu9FiDon0NrWfwJwulqjNqV3IdrFRcofMo71LwTa7z+jihj6v5gz5WBJ4Pq6OiPZzUK\nQMah6i2mVEvbPgWYlLWQQ/R584he4VrKhoDG5+NB9Wb05y0QMDQgG1bF/JAqLanOyRHE9VFECEF0\nsFBJmknlVKScQX5eYmcKYehCQ5WgqYWFPVQu37H61ouElVU6JSoTaRYa85f2gz6XT/DZ53tGwT10\nbKN+uahzKDYlHtkdd18RuwqWn3aA3RO8CLhsa0xkQ1eohqKPnsOJGW9miD7dCqdofQEftaoba6MI\nxrE9bcLIbpavXGJCc2BnJXxQoz5C3e1EqPM+t033Kx5byh14Sb+A62Q1lrw6K2Pti5HnZKv55UCm\ns/yd6V00V3oPuz7MllBRA2oFmpuUC/g+XCtHjAM4ucPz5Kodrcz7gPJ8tSgocypZcRaREh9tQJav\nvvOqUZy0lyfDz6qVO/6YaY2PfuLzRTxhhgGvQWNa4Sl+JElZMDXM0MJvW7aqJmFptpnYdKSFh0il\nmlwMVeu9eZlDHQmfK4Kuc7ssy6rUGFgY+Hz7Ez1iGKH6bL7XT/XI1gMNzN6PwtqeXLwAx3Jclm9X\nY84u2aQXsBX8dsk9oSH9xCuXPjKn8vX+Z543dfc744xHkV/EjnW/Ga8UxlcJXBX7NO03qJGPKFfI\nvEmrtC+Fz+XX90SO88JZD+JlDJI9QZvdDwG4hueOsafoSZFbXn8Rn21CaRZRjegEtW3XR7wtRbSD\nRM+X8TtyEfat3/VOzH/hW7ZvMZ11q17v0qJvCpq/N1Q2XF50cnVuARCyzp431Zd3nTF6Q/Ar1hA2\nM1q/EmaKRBeW1LPn/ZVIWcrclqr9KdRixQ50eU6O0Y8fvsFSNQQBamr4z1M2T68aTjgpmEHKojCQ\nHpm5nMWpHbDym73h9jg1TT+2Z/vEORhfZoyMG9Rub6FxSlKL+FejsoLBbqyTKpNlR4JmVeSxwF3g\noSm8RXE2tRQDi70kEm6wthsfgQfJWUQZSRGJzod4JYVnHEdiLATXyH0ArbgQpABHazjEBbYA3tF8\nb9baq27ckE5zLnYTwBf+bW+PISIy0AHAA0joEJJQxSvPnuIXuoyMJOqjEN5XoHVioKmAXWtCgMGj\nRNk6OwFZUYYMshBuAnOdHUEo325KKKsNCYW+q7G7UpPubiLnACKyKBrcloCMn/pRMA2M/dJxwFPd\nbp8nxqhMym1AlqRsLVtuS7TH7vNrvoaDL7dB/K4sz4owOHKn/RgRB15uzK/z9yZ4VsW7LD5MvcX9\nyZQmwqcNbJ8pcsqvC0cKy7AuEvjEL+cMAMP6ECNYE8gCs25cFvBJR3L7TqMZkxoQPEIMTXctPKJW\nV/XuQwq7eEi01V4kyh/6LmOapx59tzafqStPyNeCqrxFbMCzhDON1r5XpmDQ/0W8URKmiQSfc3MB\nJWn1dsDkaml2N8UG6/2g1bKMBVp7OLgc2j51p/r92FgJGR0Rx4XqVpl8hCaLPBNKaLjEM+1T70Yt\nbAEfbUJMQpcy7s9OqWu63x6BUOAKwlNRnguTZSnlW49BunzfBqrc7WDgA1hsKtDU11XTcqGYDk6b\n2PPRafJJNYJnT7d0dKOeMlpcUgPcByqnI0VRWnG3eWTsjn7vg/iZ7vAkm58ZPw9JJ6mVffcOv3Yl\nZc3MamIFIHvsPwdn98YG2uiswzRpqDSW7EahlKD7f2fYyvNSpUfzzMKbE8pcbw/yR6Ok3eBF36+3\nIosb4XdpG7fNuGFsyXz7bCA62afMFNKHT3VrnkS9t9xdNpiy8oxnTjRhT41p5+MnR8wPsP/2jglu\n7yXgAfhF82tq0OCNusauUEfEv3yCX91JjLm/UfPNQ1apBKEEvT9uscty8Tm9RGYrhgiof3sAAYFy\ntP+G+MvJq9AP+gP8dxRKRltwBSJezPF/nI8o2NV4cDunrxO/E9YZSRKUFmb9OLt1jQHfOjssOtU2\nrPwLyxmIFwAE1E9TlARHdNwBoWZB4tvwuEbMbTqXmuHnZ1oc/05nTWws2j+6jh+94bL/g7UXO4iJ\nGdv1Kd//rzzWJe4s+aZezcOH2ck/yHeYRCoSPXv/ud/aR/Lpam+qKFnYfE2H8VEIxJB+OrBG0DEU\nyIcERrzs6AO5u4z9xzXcHuI8tbiiPmOLLhoZs23QBy0F9YxvcmxVGQJCqL6VMiz8uwFGFiJlKcdh\nhL0kzwlajPkFzao1FG5tcSf8tcxOhx1EcDEHRRL9qbNPvKJt6QAfjfaVmTDqHuZnp2biuaeujmUq\niHb/CpJv31pzXv9G4BVE0L/JKoEQnZhoeUUGzZlI+P6JO3FWBS8aB/86Ckq/x57l7y2AfNwsB79+\nhibZ8gpnlD1GU900keRtbphpWnTCmmPID3T69Nib2+tESbqT/dPrdcDUEnalsu9oLUct5v88E5Cg\nPLgNK26s66JvvezRmvwe1kLNE78qK86sjLlAiaaA/YLDBaNR++9WIDQlvWTzw6iEcE1Rige5B9dk\nAD0rNl7IzDqq27Rqg+jLJw6HDQtNSkCUHnOgqcdIv1uXrA3XdE4dAJEZXIKJMkcdiB0ufimNfGY+\nQbaFGL3zBk5WUxtyCtUHzB4r995czyAUQzyIWKNBStRqzMvT+AOk3rYPuKi0LDm+VUokF0M97YYP\nbLcUN6NfZRQmRWI53mmYSCioc51WcTNpn1i37EMhnk/VRUnYqUMTIK3KrXNsC149wZ+R0QnLVRCK\nI0i5EddlWmzFSx8VMAy+TifC2sxiV9ZSl106YAocDtoHHMY0skbGUpygo1sWcyhHD30ghL9seb+H\nJ46QOFpPRK+v64f2f3Q38V0e0mHlZmVjurYFCGuSw0U4xR8CZ5giMpfPEfK+IY4QjW7oIYbSsAJS\nps7PT6DsNde3tZGVuKquYCljw6ypclHz/kgx0n/cTBe2tybtR4mvI2f8C+rryrau2uu6HVYLq7bM\n3QxlkpN1TWd8nMjpoKplhICWmUyilkrNoOB6p6ebFvjubL0BP2wR+zJheHvq4VnQMPrYs1wA7DJ1\nQrhUkwD8grBLnNlqsvGUQXTybPp5+jQec9rq60xfcEi/dTfuJ+eoGXGWmi2YUpgd4gGS++kup++C\ntli5C9PSi5yXIhJzRUUly6PciaqK1YSgw0ryuSGPB86NukPZa1jj9t4ZXLkfqtEDpdmtCLdux9qa\ndY3us3TaAanXr85R9rWyBS37+Rw0/LG+O2poPsmDi44Ij9plONyWC67gpK0fq5ETa/s2bRP2Ml+I\n1Qylxte1tpLy9I4HLdV5y74e/5dI93qZ94Bu1y+BRkx3YM3u8+nlH9g/MrtVSjBYfG8uf4T8Cdx0\nVM5NsAVKpB+IuajVqBV006GwdnUxObPnroVhQDQ0MHeKoGffVK3G+7n8VeYGWmVcgeYuSn0FgtsX\nNzr9oXK++b7Bdya8nE9KR7McbPD+lDBfYlDEICr15oPFiqSPUi79+kC51J31qsFAJEECmcRjfb8J\ngJGgqYh8jUbVuHnAbjPBIgK08Wb2zssFUKpSQeuk5SDdcWeLjluxC9obOoMfXhFK4bE0AQNDI0ld\nKDv7gK572ReMCpVScvuIjffB/XNJoxBUV5OHQNboCDDfZc40L8qqUAJ4bsILrdev/V6NjDQFxdqO\n5ZZhEbWCli3q6jwp2w6p4cCAZjgi+UBH769OcYHjTZDq6LhMzdn5mFOALs3qpfACUT1V9UisNRKf\ngMLpNDaJCAf5i1EgioI5EDGcN8WpMpted4u2TdNQaJ/yyLJD6vzDHbX6Nveso/jKDMOmcgNiJpz3\nznfq6+pgosBa8WB0P23syF/lpZe9Qi7aJxWOHxJiOH2f2KGwtlxnKYfS7WsK4lh4vfl6M5+rzpsi\nEbMl42cnXkzVyyitpAkDVS4E8qDM5sUFHrZwTwMxtBwMSAtWE+VcvmQi2P7mfCb0P1xswdRu8xyz\nRe7OgNQn6BTdEiqZ5y+0ag0u0J4f3TfFV0A5Bby2pVDi3Skq59npBP31/74ec2bJpIH1Cd1DA22L\nlWeW/99j7dmkjQhjHwedSBBqcdvgNB20m/Ui6aSyRAzgZ0cFB+CEOqKN6wgET6waMrvJBGROeI+M\nG+n8RFsg8I7rINlZXvG5ut+stJ/BJfOIiuvdMOT0IOflkUM6W2XNfqSXogrOTO+GomGaVBXAIbMs\nFavHuxuS4lyIYdV+BwanieO6G4RXZmmTQyY4KI75XKDoY99pnHixitJ3sIJ0l1EhUdomn3baEMTm\n4iGpG5rYWO8Rq9L+0iXxmD67XMrEM5FZgC0f3lKyAZToLSddxb1hAh5WC0uwhhXEAzxuv+UYMasI\nLsjNYTXhSUqYp7g4Y+UD+lFDPeVfNDpU6hglE1sVKuBdMiUbmUgWK+mbPjiLuq0M4onNQeewvKV5\nSSZc7OTEKPTlD/5vmJl88HL7PB9l7kz4czRSfKgTOFP1c/hQdP/FizJLCeeidty/r2QUSfVOfbe4\ntH+QFOZGMulsGocDtjCEwaU7E3cd3kjhsOkuSr0PGL2l8YbbZKGcqW78gITzbDdrhxR8uFA3hKvy\nndOSa7/wQ6UkAMxUPy3ZwU4wMTiXxAuHqmm91h8PAxfO31mTuRZNV5nCQ4iB9uXYOCncQr0mCOw8\n9AhkhohCZb5SRSmiKkRzYT6XP9xXOCA6MyNRrD3vBU4v+gZObBaFrVEXUHTdhh4NXULXKPAn/1bz\n60Jd/Vy7upe4y9ZeUE0QGf6Ey8r2Ta/swKxLQ5FeQs0nFQSrITxmBB3IRhH7KdGcIr3kKIeYZehM\npjOquEsyrQzfLov3bzPk6z+EAXkTMMDRNfH2fHQYAElHEeh9W6zpXELwLeWB2V1ZTszYyYMQND6D\n79/deHH+AXg0bWfMBjXa8+huTJCSrtlg53lGoK7G7XRzeGI5Hhq5GMc+kuqoSgNA8+dv9YKHOivA\nX8YSNx5H/okDcIYuhYaK6qbrdfazDnmRn/nG2eQs4i7ITlJg/VIHHz3aFfaNrbsfL7I3SXrccCk5\nYdjJvHZg5n+arZ5oXVc8IyZYg0lpcBftMJ/iR+9qIPENh8Jo6rmZo5wOljJ3gASJnvpJdRYKq75C\nzrV2/mpB203FNdK8dFznUZEFW/MzH2LsCwYcOv/JYcl2dx60tuDjTFDHug5ydQ+xNwEZ/Yv3tIw8\nZKhbszWfMMdTM6wElRAEKhmWQY3OimdZZhNEwY7oBE/pMqLENYm9Xx4zUM8sOeibvPUc7l8LpAYp\nozkPY74/FrctHCEnJjNO6Y5/kmgtt6IQK2XPz8yDHp6RhsWLdcFQTnWZ8XDAgI23N/j1J8oOQv77\n+bYIFDx0dTwSzJYgE6K/XE1YfM7UHhf9LUTACqqrjFAW8lSGJPBp0tAJ/iGOq0CVpmgQcCLpgbu1\nBUlGiyGyBzo3pLh+EvM7yrRyjYGZWh3SUmnX4RLW2unCP6rp59lkAdXS5PJvCT6HCXgu/Hw4Diya\nFMiT7KQzI1jUWjhg2Xeytn9e5IXLF66VhNftNsLGrNM4LjDlq+zi6CAkHZgS7tHADwbx7pdcNGR3\n3fMCiMim5c4R6NB+nkXwx5yNK/zv3tazGgcCq6wfrWaC6ojZLdOtzx9bpuH4uYaSWED4n8ahxcce\nV8nN78AEPpqbmW7206MRME+xiVL/tb5DunvCP3KygIkOfa89itUzg6q3zZYgeAZ2FwMYRUgjzg2n\nxZX452p55brEM4RNijonrDVM5Cl0ZBrWBvHjxrt/M6RgowJwxiqMsbTaBdPe11yYSVISYA7tM69v\nK8k9KHUhjlIBebw57UWU535Kxl2wN35nDFOt08jvz0/sM2gUsnY4avn8LgHpzsMWFTVBDsY+w+wC\nIr6fzNcuHAiZlkEBNy6DC0Pdaq0uyT6AgjqrTujQaLzM7LOEWpULTWT3m9tAmdLGd54JSvsSv5A0\nL3FK5muL1klbevxFzILLeM5aZyRYehW3SqjUZCUUjZWwNJNUQt5PSp0FXViScm1pMeX8cj4iJga5\nvxECeXli9yLOesJAwO/3fcQL32DwcBfA//rSOqBJSdMG3vAByIokRkbKis/Kmsc8FJLYoHXHQQc4\nGN0/hK8g1i17H0UFyn1XKy3ZsobywHlDn0SWlXBQH5lXny7DOvgVJy4JKH2LVSdasNE+UBjlJSWD\nkq7yiU0CTyDaBYe8zlU6Evj0/hDFASMOi33aBLr7oab3E368IRyKTwNrojH9ljhBtBS14E8/wfh5\nBlYDoEGg2QaIzNEoJI2oTtDgM1i7BIXmCLwmuX3eDxdfgIpXiN5+QGiJB7iV+WSTyp1jG21NOwqu\ngT9BXa6k3wnmMBYYA+ZSOPx/cG78yJ7ponj+lYvckOuBQUIc92BosN1873LJSrtyYx6k+/UHIpQ6\nrM7v9VjAKttdS669Q6lcB8+FIcG2b6P5YvFZygpftLw4Ph2DFgTpyn75b4j7mwAwjZ+rJKz5L2vL\n2vD49bAMNlagIgp+Qv4BsoI+svk4E0l/AaKTrCxMVgJD3ewlqhDmk8cP9zOU+B9432VITgLABlHY\nPbsK7Bh37SRi9BRMrOpI3iekl7tmw7SgxqI2etghzbnZNGsHQ6Z6Y5qJz5nuKe+b+qH7zdEBJaHH\nr/zZHWU5u3oD/DzhcOoqyFQ60N1ZbLUQA2VeTQ6f7pbnoriSNO3IA1ktkaztS6msEVwfl2XT6tEP\nUGsJf/Wn8ZROjmVije7ApIedX3lhD3Fpt4e/5ecRsjtGmful22GbhMC6tJGLBCSXNt9d10EwkDnF\nGNpYytA5ZRA3XDciQPJb/YL9/7/hQrqDMXkXZNmzJfih3Xfv8xHpDqciL/80e2NdPjiJNiK9YPiJ\nUgw2/1+sQRL5nSHWHJX9nn3xwpcrocB5YQAJSlJTT9dD3o7CSSSYeP9jPBkGAld5y44Gcyy/zhJX\nQtp4wqrQMOQcYQXwKvkgVBeIgHAz9+YPy1rf0lAQN8aCCG1Dhog8Nno8g1x0826pnlf6TM+n4RlX\n98kHXqK/7lWwUhMmIZ32R/6rbTwPIDaj4Hs7KPpA97yMoPKZD+qAaoktLytEp/qVtCU0wDK7KCo3\nXObyktMliD58zdwZpObTfGZf7xyB29+kt4cRbxv1zvpJAQOnY86Hx9H277d5jz90qWZor8o3+Edn\nRmbCOdb/uvqFi5HXj74AFMO8lYV+0J+4VLNYvEc9QYdLslZ5RhXOb4P18G0Q6HE1rx78T4LFJ9L7\n1LdWaSajF9V02rSZMFUxoI/QVV0YAm1Gg4eFzjXroXNSBCjqtkWVMPHTwNb+tbk4oOmfu4G1z4n1\nv2w0mlczHBR77xpQmadEzv4OzrMHfZZMNR2tvk3zvoFhoVDRfbvrjKs0XmOyxbkHZOlWIeK7cg/M\nBTUDtCEPto13YbewB1R41TrtdYK23uiDaecMgfccZMtzU4jWqK7UZwFvWlrtm8yyfT+8U17EuciS\nm7EKO3bfyCs8m72/yJdgyFlTjqENsd5wMBsZG0MJ9m4OZSfYb60cCKutTLFvGQcwvLZg1W+v7YcW\nCJLau4vz1EinsF/Gkwt4lkV6mfYlWGQL1BmkRWTfzGbV6GcGbLrdWCpa5+EcWrmeBr2ZXYe38qCF\n1UkV2WormABdGSfKUOChbI/9fqj/lc7glhuEH2u+y0GVE+ZSqRSHXZYo81vxG0gW+alWu9r7iWGl\nl1h+8bTP+p63HTmKKF1Hvf1ZhY0QA04G/v9Zr3/ya1No2KumxModpkHOqdjor8wbwkXavg6xoS45\n/cNWyEUq/RldMV7fukci3JewPYCvzVIC4Vc0FzSgSwdCUgYX9mzneVqJ3YMZ9fqtwJ5WHadjunGt\nKjls4T7ocTPmqmjeLc9e294DF14GxsOs2vCqrPz4pC1S8y875U/S9TcIWrDI7RzDXyXeKCziEUDA\nXfV6lZa+y0j+uy9EYhni7mt8ZjHSA4WVvyjaPiaiN3WMEFvGS9xtKiAnpVgCKfEPWdQ+uE7/X7Vj\n0WEegh0zTrpqnlVsJTAKxesFFmBBSW7/Yz4a1BxNhlbuu5M7Jz2n2up18eZfzlfoUyD7jyWOuh5Y\ndHfWs1lEU87j2l4i39CkiYW39usWtPd6eOvF3A+jweg41s8eiPYrBe8befj+C9HoH4KDnHZ2DauX\nBpGRnn5HntSbDhfOVl1Cz33ZBPymmaflYaA5rZSvs5IsZeKSZd1fa0KMx1m1fXvIm3NEwOK5I+fl\nT7b7VGO4nDzjqf2rvUdWzaGqHR7BGOaCGK5tvXVLjRIwYc2hza8pmHFZdHiPXmnF8FhHeVLs2VA3\n/TEVDIkl3LksE9zgngpnKIh7Zndaxtfn6uZ/bRPUJmQsihU1W7LtQkD+zV41WIWgZVIPdqt3cBqV\nTZu8sDkC73csVmgk5ebyR6LU9C234/F433I20cX55+P+vN+Kj1oIT27iCSf2Wx6bRc40FB6+yOQ6\n/lRMD1hkfS1hVHAGx28hdCFz1G5q+20XvJtq0m48Aj/lW/qsb/bmHJEawyfHVD7KSJr8dOb+h6fD\nP7xD6nuaYwzzT4RugcxI0V9GNn8D+xI9BawkvsTznb3KguDPQP47vLMDpnxDeb8SR1gidRkzEiCK\nF3+XKVE9Fhfk58HNH9ZlsYRLIfbZeyy0iW2vw3U5Is0wktVNbMq1JtSGVEve4naigZlQB7/EeLbd\nPGW80Kbufr+16LDHCTmzkHuf9yF+3Sq5dra84HTG6oj3UqwXgqynqPRfXHU3eCNBAQQThCno8I8l\nlOT2p39YzeP8kNx8SG94YDMIO/SAvvo6lcXwjIGYy3UX3r3oZjINuzo8XbFlFw+XHn0tUIkDQGWx\nEM5Uwasz5Eq09gwQ43t3TV68SeVq7G6CVApNF5AvAf2xl7CAGHkZzT3YrL7Ex6ob5h53tTjg0oQe\n12r+HRnLV+YFxo+nIf1bxusXchhRg8u0KggmkKZyvval5o5Iy1ld7P+4gFysMPJPmHR8QjH9Yo19\nmngkPvNm4jJGxDxoLNo0gCXj/SipBKO0esPZF1N3tiw1hPWbUR1V4W4cDXtRqFm8qbfxkiq8q/yF\nny3TFwSl4uMkT5SzEFGz0BUkJ74LN7g3uo3MfdSwb34e2ieCup7qGzhj342KhlItkmL+KVRWefFY\n05HohXPE94v1LgsBrxHRvfbDPy2tR+R7nHkFRgs6eQEtERUy6ZhtBFU339Z/tD6qw0qgodie1/Vo\njEdegMjBe8HSZYnh6QsfwLH47wRCtXbmXzmG+wH8BlJxUSRsxpOzQRRd65Mc/irq1KVWgRPRyTRG\nIDY5Io087FkoLLplKwRFeerH8jN7Th6jvMGN5pKcZ92xqQY1KDBwBIn49JyM+McElg2zcQUFzlGY\n5UKiIJkS+lhcdnF8DYTYd+mn/2+1m9iOqXDTBdG7+NpRecN34wlSSgKJtRfp82S5Iyk2dwlJ+m+B\nfRxOMXiayppv0lYhUy7cjAzr/0Q0YsJW+hQS7l6SFSqT61FK4lyEZa7TxmFQhQV2ynL7VyXuWom7\nXPBu3xnR2KKghVO9SbYDxjVAwV7IQ4rcCCRYBdAp/VRfXyilEtrA44mWI731VF42zZrIWJUruf92\nqdXl7KHSDgxFtLeNXWVM1thwU+dmLZcDiW+pcVCUHvvl9vlGdK7QsJn/ISa256+2qgc8veDoq9P+\n35OvOUdIvHXAQXVA1WADaGep9xyFGUY+NfWc7i/3ypRtzb10ILBymngRkDXqTAHKOs8+hm0+zTqR\n9B97uF3PMgy+L6d/M1F97ZUVCz0A/nszHGWjdDb7x+h2WwHXDlYzhs4U78uMtNnNeRL7D5ftGWyp\nlp5ypkqJJuUSAMxZr5nisSMcEMqdp8jydcc3+SOJGjm/7W+T65WEAWRWyyoh3u84nVaKHb6b4UTS\nvszRb7eSF02cqiYDMRODp2odBRTauUlmIkJC9I1oNVtuS86HTjkaaTwaOORXCFCOqnkpnGreS6r/\nyQdZXBaByqDr8CbY9t1lrkSDn0VBFIP9kbjzHuD0MNFs/y5wBASFN2YCmLDsJ+rHOSX8KINAoPCc\nfKtDOa/aG4djPzmlA/cPZ/XXHNHxZjAI3QuBSdFOOksIHEWqnms/BWYFCtAY5q5FJinfq00P+teH\nof/7uSyevEL/aUXKfqkMTyYN6VZMXVCuatqOy+kv3pHI8C+LQwoz4v8FOucsKB2swSoLIOE+fDdK\nrWZ3hPR8mr2gJ2P+21vsmRBnO0ZBRZ9Qxo3jjgSptKk/71GjeB13IHKVldMhXu+/GLQBQn5ZfrMO\n8I0T0kU3nNxolxoENhPewq3fSJWCAj7QbOsJdvIKsT9/YgUurd/YwxwPG804etnHCxhoSmjQXzCg\nWe7O3Y21Xf56m+Wiftt7rNOuaD9Z/iwkj5BXbJvCJX+FQn0e1WNh7DV4grocX/K9Vg0AiRV9Q70g\nk1+h/YjI0820dcTRkhoLvu45O9yx686EGRQ313C9L5R8tU5SGmpIZjFuoUKX9S1Cw/EvwcMUsYep\nL8c5d2Fe8X7yOAYCgcRescDDosoPElqfwxPkGiTSL5NVlHoVi7C6Nabmm5N3wXbDSabeH/J4Zuno\n/iRu+6sgXHjqNLWKUwqgXMTcsBH79oEPmOXhrrlzUgWS0W1OKwc3C4myaKlJ7+oTsko+pUBZiY5i\n+hQfAWEHDLT8afArvBokZBWcn7JKBligmoWLutr69hTlLojHPVAA6YGP2wYb8p+3WM+DTpHkbRwQ\nUcRhWYKzo6B/c3bUgK7QVVSjlBNryFGKtkOqj5ugix7w+wi+KGoi4szcqVaLSXBZ65+DD8nAVBAh\nRLN388NLqLKHQ9PJCeQNG5H+6xA8bVwiW2bNH7vaU1mLWq7xfoC+IxGqMOo8XSehYXnbcqKzX138\nh4k+3r12CIqysgaq22xo0ELy+jSLvbgUD5ysQTJ+3P9YeD6shJlsZTv23+FahrpULLmiZG5I1Kje\n++ch2v8dosILT223PKtMmW1PBgGJyVehkDKt/4Wh7k43V1x1auuDkX3tL1ZyaUt4P8F27aN7t7SE\nFgK7ZY38o4HmE1YsL6v2AflaK+h4OFcgI/kmKSjJrmDGI2uSJTvUOx41GQNKZdhM2TWnyz3aZDXN\nus+afOp9Wj1AqYHENJgYqjMaEIf7go19ey5JegRSC87Jyvibl1XNbWnf4/WHHkxmC6hwt6vIv13r\nMxIEqvF8rXInBj6V/kNUxqGPJDikpbd2R8iXhhxw5d0VMSGMdn9J7EBz3F07jErn+3fXVtqE3oNV\nBBpzuj0urUPJgLb/JeE9wvTZn2X/pvgAKlH0p3w6ic2MajfUdzo++eV4W4N/sMABgA05q0w5xLDn\n1NlQ/T0UZQzyA/5K7fWzHQhnivpS4T40pf1BiNmeDp9Ihca7UYoHP4bRn6mBstVnwyxMxT7eUrrj\nvf6stJmkI6DoG/hQq3imZQQovIWnrYgYyh80B12Opu07uuFQvvmKu3kbbJDZRmgwFFhemNh+Ayfb\nVbQgPoHvUhjujdOk3ctM19HwK1evx+mjp/Fn+sGdNR+5JNZX3ofyxBPvNtVtabe+1h76+/LvNcnX\nQeD8bnXAzhlHafHvr/Ib7T+psqmErHB3cTgWYH++LgoqWShHiKivQTpfkyNxwGN0o7sRc4Ol5f5k\nMHZKBud58Ngk6fi3kLnYueAptdWkBDizEm64+K8WN5ozQVTt6qW99S0ztM47Qc5ndYGIor7C/0tP\nz85sZBhEViHwBMws3TUKovAed833oz7j8nrfhKASDSdWTRU1a44ku/8MtVMNo/rMzEhzCetSPZVi\nDXjkhI6DSEmPKisvI/kMlPuVWEIySh9wIjVliMHgl5ZQUqcqaEMMaqQ9wemAJhzIz5q+0a3dAC3O\nKLSubfnFDctP+0+HQPmjgP1RFgkz/KPZzM6j6LaxIRbbdkayYxCbMho6erlCBRcvvzwkvIP4M8J+\nZ0CoFvjY9CC1QC0G0FbZkQJVGVZ0NsZhFFvgXuD80MikH9uM+XK0X+6NLTJbdnjwjyK6cSZSwDHX\no+hsWQMaNtQwiKxl6UnTyi5DrSqHmyEOhta1y3TKb71QwxiNjUzjhmIkXu24F9aKHbu/6yQhYfBb\nzjsu/oDZhNzontJ9Gr54NeCsNZ3cZ0B2VMR9FAIHZGZdHSNg6IDuJtHnlzlJPpvuPqyX0QmOagfu\nPSzkno/hpSCty0IZ2vqIEo8mJqmj0g+314oH6HDj5yDLW3lu8xilRroBOmMo4Nch6FrRJQjP4I0I\ngsP8X2/dX57TXfAz7xWvRT1/jtttd/qICqHTyIBQUpRvu6SW51TNTPV4rfh65gQP6ie7w522heXl\nSsZDqgf0bFmD72BMk2vpQkSsyxOjEzx/C3d6XKu7KUrW7r16Giuh4aR3iDB9XcIz4cZBDsdjBg0f\nylW/Q9wivCDDqE35fRicgI1Piw2Mj1y+nKqNaRx/uwX5TgHC2/2xVrdtVJ4wlB6gTmSBC1N2t+1x\noSdInpzMNRQNWYd22nwQGqGwoAX3f3RO5bvTslKWkypfwzNbfJywCE6gqrIyaoYVlT9vmf5JEs8i\n9E2HOIXNvBpSFKzF/wEVTRxii96noRaCFIBA19117CYXNzI8J4Br3p8u12mRUnDrWA3QeHjQDKWD\nQ3hXvZnJ7zhU2kReOWvJYzuauOF+/4JU1X6Tb7/QWP3rKANjwo2neIKFEGzbq2Ag61JbAUciTeou\ny7IVhpKbB6K18IXZvxqi6xSFzcUW7AeWsvhU93u3cyjDE7I1ffa3xsOpwWeMNRBUtvQoUSiQrI8O\nmcgwbWuGIDZRvVpS09dKU6KwX5kSXqPiZhKMeeuEZvXIpieTcWOPyfHK540934yq4Ge2gYgMC5I3\n1KMqKOiBHYbodCwVuknUb32Qf51Rpe0SArDngP9ARWBwmkzvDBv1LLT3eQayEDIwP6FttoTkdQ9o\nD4W1ukBFIk2zk9g6QGWahhC91TFx/EdeKp3nLfslkw6XDaVGaVRPh3bgYl6v5AtpWRGY1DyCY+E2\n+lcxWqjqcjjrUTJrDJXDI8sG4k76DD5Xc1sq/jwObWw/kaIQnJ6M9FQERozNrvtpkGGc32kmSraU\n0zqFb/vvEU35asTtjG6CwoO3wV2fkufOLFXJ3RxfvNTV8E2eQFp7WFcsN2xxTAwQfaDqwAGSj9gO\n8UsfsuG42/ImQzOAdrBgWru7L0302lfFeOhTrn+W//IBlYxrc1mCNAiY8tCdjT2upUYYmuCvHW0z\nZO1yKZPVmPutRQ6WttitACSllXctjHkgwvNZkpklcnOM1kzpRTH93p+jFkg+p8w2tFaHgnyuRZyt\nP1OfbsHgXxYlc0kVAqvFDwYYOT4njXNT8B9fewWo09kBC989k/R+QTdw8IIWlabMCKlsyfKNXJv5\nt8106qcZRNvb47OImoor7COMykPn/ZFqs2KTcQpNVpY8WfXhChEKi0PIQX91t7ZWGV8pb8AGN+s5\nINWB6Js+yBtWplsoo6Oy54kJXyjq+w/XZzvnrhQjKQkBovq9TC7HR+jVJnr5VmT1rjq4CqeFy9SO\n6th7S5MhWPqjH1pQnrpFgUva5gW2eY0MuE4v3cyhs2UyEr9Ewc4QCV2za3sbqgW+9yr7L5tNEFKZ\n4+por4r++Ju8hZC3mLBZTGlDEPbOvkaycjj+XhfnwEQKOyjDS4WPsQyPRIpN/0rzv29spYO+isUN\ncId0tEo0QabA3ItTRPZID9vS6kcG2RElxnlXNRKwx9G4CTVwqs10haHFGJoxVOY6qhLLcCe+dTk2\nZjvUfGxyTSvpxTc4zkZSaCGCu5B30kGPUqO9osmUVKT2Mg5/jKgN/jBeqaZMP3DHB3x0nP0j9mPU\ncvlohUObqgdmBoSdr+OhBLucS4uLUBmcQSWYPLPQH/p4aKJXLd5IJZxR83b/y8vbfLfKtcLgbE0Q\ngaQjFesltE2BpH8mabtDCV5tseaKA8CguDUAi9ef5kTbY9bywdeTQ8bABbmD/Z2Ca8UXhKHufvRY\n5kCjWaWUX3HzrzZ8peV/rDo9Y/BVxQuktrvyrI/SuYAUQ+n30SeSkmkvS/IvfB+qXyxNJO4NsPfI\nKpM6ptOk9y6OjD1SeQJTh5Eltax1bxM/9FxnZzAlyVNb6bZkzcYSW9fARR+Vqipx81yYFbort2vt\nbv42mTbNtY7i/3ICKaoJ6ZgHKcEtKuyO4yY/e5H9ZqYc74DFEo1dTPnMweQx3mrGgrHcU08EyY/W\niJiG9Jdr4FEiecWWtXtez+ZR2e8s0blimWzvMQUMytZXjJP2S3DrqmnIKS7yqAz/jRL7cdBVi9gd\nNZxIHtNU7lNlTIN7TD9XLq+XXlIt8xyKaW/ciSxq8pvN0TVr+Llhqs6zNNVlX7Oe3G+EKHVTakYu\n1vdaxK84a4CivCy+umkLqJ2RGP/84lFl2lPT9oaTRnltabuyM1YJgHHM/oT6kj39U6jm/GF+03zI\n22ur/ywXansKwOC92FAhWnnjvAFJ9OgVps9KqHQgupgQOWuZ8LK9KA7UFW0B6XEJENmJUTFtS1xt\nsaAHBG2hSPKgZ9+T/3Sbtb9UyNhsHDshoWQJq0AhgLYUslvmreL+f/nRkjvKZhiKjezB601GxCsS\ndIp3VbkSxKgyFL3ixquR2tOiMa2hXwVjUtDr7s6kh3gNFD5jmYYkZQ8nofWlj1vmm+drTJpfjt9b\nfCa6+4BRAvux4GX6Xt6bfRV64ottdpLDNaKW1/rcU2fhY9wHJQVoSrMUvpV6K3pJIDugYneyFe51\nFYgSzRVV2URw/r7zuwb5mAWz2g48MHStPC/EviOcCsGKHDP8Rrwy6iq92DfEMaDXm4+LMSwFavvK\ngfXQwn+HEkE0HpRdp2Lla4IbEQW4EuqpzhMVJPhFhXl18Rzl/6uMPBuSEgr+yPzikSABfvLIT1LH\nDZnC2F8YszGzgNZSilhW2P7Ni54F4TXJVe3v1nwI4XdYPkHmToWZ9Epb4UrtK+P+X/RnVNDE+Frp\nAtb2oC4obxPgNLYUFVB72LP27IlXQZe2HGD7zvzVObYDTFbga08d47bknibGoQOVmLuT+9EoL7GP\nl9YzTbdJLK6nc+PTZtAst3kiATXi5Q7OobSK4U0nIl6psoj1c5V7jxBp+sA3jP0/Vyle/hTw4k4J\nFy2jzlLOzh5B/DGtvRD2Ati7bV89gbtlDBJRuI/rEe2aCBCahHiLdKrN+l4jAm/hclNVtVklV8vd\n+/4YzULkgKb8Q6YSPezqxs5e63rxeeAeoijl42bXi8DoDU4AFRyrbirkP2jePvmAL5HY35W0tt4E\nPNoMVJl5pru7Q3XewWrtJxnrLSfUuSHSkCtanQ51E0pBgaAAfxW1mv85gLkvpjuxS+sAMOLH9HRB\no0URE+2WoEP8RhDQVzRKosX0V2z5kQ+p3k3DG5pT65cWODsSr+akb+osXDTgh+5Ry9sVHNipopv0\nXwGD576FFwuzaULS3b1y3Ga6/Xtf0ZLAboJFMl68a9UkiloohJIL+AIVAyNsQ9zFFoNFLE/ZL5wt\nijtZK2g0ZNY8nzArH4DrHz1b7RSYPnRCYz4IyDIVY0hFmLQCxp/uPP/qwziOJ0TBm+0nSzZPv54l\n+VmkVST9ZxCNADAdF6fWr1IpPLIkbxRvcahFH4liVKhw+w9oOd3cMf91Rvd5FQFrgYylIHqjHYAN\n6J1SdbHeKQL/RTea6itcKgpL89HURwOvR4y1DEu0N/xEScm+eVHQJDAeFKFiWM4CqpQFKqIxBma4\nvxzxLHwzzQwCoVbvLS+Y6paQ7MluTqjETGqBAZxfeayNSNGJ6J5JtW2Nm7R/5Nl0e1VNc/ciIw9E\ncgGmXM9qDJCW/lKs105xQrUPK6MhGvOJkSLW4nQ5KdS3wb9eTltpSSAsfquzZobHf93Rgfmgn/Uf\nOtoqosnbZzaeVM6pycDWHN5F9ZXS5JXyGfRjWxr8DPAi18Q6UpUrcbaLdTR2H4ZqyId1cbx58njd\nVk1q+pNHGKav28ggpSSCzc46glTgSD93xXjeyX/I5QCmL5PQnuNhubvLBoBmuf0W5HlCfUPkkxjC\nWvYdkj9qEzzFLCLKhGKrErU9FcgJ+GJELp4Vd3xMkC5uLCQYyZcStB7wJytf0cQV/BhPoQr2eHDj\nJ7whR+zL7GsiQSMgliyPFRdAo+2NHiZzn1ITO9x+0PP0KjtUIhRKvEJrAvjIyo9Hp3z716Q9Cjos\nUmuUlEqUVa9cC6bdn5oDSiaH/NUztwJo82hCFSVZU8fUEZxRsOQ42rl8IgPLK+QHEb3X/rnY23BQ\ngl5W5FUMnDMXScOmdMBX+plTD0wQmQHvyxC+H+ag/hewiUsQ438zTfS38+WPbEu7a0rDx4ZQGHLq\n5v6SO2hAqMcTqgbSkytAKwF4U1bGdrI1um1wqjDDpZhILTseoizE+LHWiBtASNqytgIB2HI4fCfM\n/z/SkScQA/r3J2+z1Ph8nFFVD3QyxvdgwceWj73Y2Ye8l7WvZbbwsD509WzuWPcGeNXazHvJEDsr\nr6fHrhR/UFIdPNCZTb1Y9ubbHHiOLRc3HFQE3sL8lZmBU+ouHZIY05Z1qs4i7evZQ30/hAvIYXeh\ntfjKbSDrcoGl8sV+YghoCcSeh9XudyIjLJ61x+BUL8bxDQFO7rQqEJQWJDEJURIDsxpLpWg9R5mg\nZ5miRp/IsA646d/AzND16Gc+GGz7cUVA+b2aU2aNgUgvIxCWdS/gMTk1VzyqByOLwWZpaPWxAB2z\nQVyL1XDEGFuewBn6oFKYsBHA8GjXE/iBjC8lJSXSkic1G0nQM2PxS3yPv3+Ol6T37pRof3RTm4CI\nkdv1BVxCropaMkVQWQIUB/2R53Oym8KoMzAla+meYTivObhSH0mH82TNjzXJK5cJdQRGaBIP6DFh\ncmufFea4ewYXDOkMwWo62c1IfPfNiklE9LTtnD96sXQvB+PPIXqJ9XrKy1bdflfNkT+rMj1WIXs/\n7ap7HBK/qoszV/qr2Z4cqKDl4CToYn9qeG4GZRzZwF1OFibzY/+VohQTmpJoVzGvrk9SLFRFdR8m\nBCy1XrkULOYzXP9UDF4AonLtWCZV8xq1B+cmjg+rF2LX7SFm7ow7CbXC9sDDFh0RefvT4KMkM3ro\nUdeESCDPIkoZYlwUUUEaMtp+NCEg535w2YJYrGYkCH62beRG6fNoMsg7ulIvZjkScI/IBlbT2OWh\ni/vRisuEHqMBJHKHNzIvdurIXXtFVhLNFKTSJ1NcWsPzHLtQTRrU1kLK0vtsus0ry62xAi4m2r1b\nGCYM5bJ7QC05U/R5GsXbMsQBKCrZsWJtaOmjaAGvnG7q3haUYDjb4QJnSlTZCusLplimipS8G7DX\n+dj1yZzXHpgKmgDWi0iVkakGjLiUo7OeGRmAtNLnyffP9OS2ToOdOUx4VwKskftk2PtITNfi6Fex\nwm7olZDy5cgncOxZutb/bR0jyhFadgrw/1K8MM55TIdtYkE0sGYHzx/iKq0adtdfOx23CcClZyZ4\n4gGxyINbMBHlNOTufxuq45RzPzqYZH0ZRzYzQOyDNXqugHWrMiCja5lWPsZ9xioLw0YFyqVFGVlm\nlqvd+nKplRyl+5oc3+yC2ugsbGpNGWLE7a38QAuwFPYiefThyyeNS9tryzomncSBMbKr6grmcZ9b\nqLZpGHBjDvkmgG9el1aLyDZof39Io8MAucjO5pc9ceeQJbpa5LxCkwZWpVkCVvSvwJTURtMX8gJT\nNsjVUiopBqU93AesgTAsFC0HLvPgOCyPk9aQo1XaW3HLBWmwK0d4Tj6MKxGwcnOfUt8Mm51rn4cZ\nbyJ1+6AkNuG6KSi66kEyCwtrrT+FvaNm6o0TAEsTonyiFkF2SgCljY4EDEcv2uqMI7vvQN5Om+FF\nwca9VBV2kt2J0MRqG1iraV3bFieoiZRaJpRUm3ppW93fGImQOky0QGbj9A7S3xtYIPORZyyL68Na\nYtzW1HiWTzeVDVytx1wIOmWKXC0dCbJsoKWfBzI3rErNHo2iwTaptybPZloDn3OnSi2wwc2Fpnm4\nsHTZrBvLHda2IZDzgZZwhnHqjGfopta9TpNvupO+VSDNeupiMpmdwg4+FxJn/6F0fghXBoa8JqjH\n7KWweAkI7bi+GxwZrdEI/GE+WaKSdqBKnOuwdYXg0KfnbpnRLIsc1wA8jEwsF7DlwzuT3AniJ6jD\nKNfY+SYHu3AOd6WN5h26eCfs7mSBIZfCyRO5Vx9XJ2Ef0joKA7AqoZlBCbenH4no+yd9xTUGcuCh\nATJ+Aq1b8NuUoHdFSFcwv7gam4HAPinb2uJvkTgBVrZUX7haA2GjTSDsR21NiqbkNsn2GKEAEy5W\n1/p2oPNxc83oQHK7U4d07LM88f1LUMjzmhnvPrq19CgZndb2cOibZ8bDOLt2tiTHNxkFibSmBtlo\nuGUGVFkpLJrmhA44CYyw9PSuYAb7LQFcP7PvAgxyrogTSagnQaI67tilZv6Bh4CPz4tmEBPzBiP1\nhec6JCbc4kXL3zKY3AtFjmlJYbODCu41XZEh//rUr+NsrFI2KgKaNyYJ8zydQkt0V5XKSfPxmmoo\n92g1V+lhizz63D1mwn3IbsHaMwTqESgyvfTDx7YMQu0wm4Xhq6LPEsp5+zm6/zoKIUCM7ZMhNmSd\nL9mmLj66zvvsN2AfI2iqZQDlbv8mUxWg4C0WPe9Y5ppPGIfdtGMe8mHzL+8B1fugkMbYYac+elbJ\n0T0FYQKuvW6TCLqc0GWXCMY3fNPsPGPLv8HdYSB0Hzj9YRSObGHfJywgsd6Ve6NncTgw9+IiWgOY\n/nqY5vSFlQ98kiOg5RjIDFu33g587IrD0yaeKRb109BEvDIiITvpGbNtxK8ZCPZ2cr/quxu6O99u\nisVfKSFvKW/bWU+3oZcdFhqk/BX/N2E8PqTUMZAbL6J9W59HKHIxx690AKE9QJVfUUkLhPCsgo4e\njUwyuWlGP1uJQ78tQjnfoC2BHlc9hh91ctNyc8GX573+dDceWP1nmbGYodI6AmCifNa4PQUuHWkn\nuym9+i+qF0xtN/xxjkPz0pJ24t6KUyvIjsmi88ThuZu3sovcgvYaza6MX5biqJeaVmYLq5BYooUw\nUbXozqOKghZujYg2EPf/4ukrRZWeyXpuVZ+Lhl8DVUGeHGz7zIFl8ut8mELbSj0SnwzUbBpLDRPK\n5B/PIJ7muudEyaByfK/+ea2MqlQ8Zn8476s0DuNAkjSoi0eDtgp4NI78wOCxoYOryNveqRmJv2Ee\nU99qy4bKdGIa/TbpAd3Eue/AFXtvKgdGjCJ67yD8Zc8uO9njIc9if9qKk+PGgufS1RU2YkTqR8Sh\nH7qZzcQaRPU1ictQS6guBEPjSRABUhMEEXweMZilnnWMEXPNXCSPMeO+yq70mSbqP6Scfz1QeAiT\njvWUPmpV2iP6Cvn8bIUXz8/PyUtH3lzHp1KDS39vs1hLIEhVbUmjbGYUQ2SZac0vTBKwdjhTFkhY\nRU4WQGwqhS0loDmug39oi9OUeO5yGGJbCM08+jOPqCDWlXI3qeAQ+MC4Pv3mUN1UGAlc7yPR+g2n\nMxj55S/F8P9EH5nKHB6JB5r7yQvZA5mRdcR7fcGqLursbRbdiR0e/LpXo+HLtBitlkOVH9LBJcsB\nzZAwMgiVsBcERf9fdirH1N+egi2RCCA24JVfEaED1iD7b6azRKnmzOUYx2bqhNG41vyV8hqiws17\nYwWUYPLLYrg/f0xvyMnzSsIk8UXog/rOmEp44hVGExVO10jKCnSs5ijkfx3GcAxQBglH0PNOs5ZT\nAXXyBeWN4FdYWkGr1cq++bR2PANKQxDX6tL1d9bNbz/ZrjRhw4UENT0Qrdgwv8IQTj4YtXeJjCHd\nzTVaH3LdVHBo1hqHGXTQ7hi4u4XRGtdB8L0EcMAUSCWEWDnY/TDax8ZVCgGSeYLF99C8gP8ZPesO\nPHLSqPoUmoihSqMkc4uH2J/XnElj7j7664L0JTVZG+BLaoRFIM9Q2NblwCllgH7Cpt/2pTnOc+cJ\n4f5hfIJUf4Qe5+nBMCjngq0iWsGJ0ZImOdRKQr9wkC88Fg/PIUzgwlI1LdNPNLDN4IQoTvTrK7ty\nm6Q5WT7yyFmdYCzgmlsxEQiBh0feW+HCwzG2UGif0fBzhAOGkYUilQ21Tb7tYe9CxlJsTbhZAQPo\nj0yiKZsdExg+l+iJ+/pnxz70viAGtXr8ct6mDibxjntNJDJhQTcIS3guD3XOL46fkyB2P/RBR+Ig\nMMOA22rPh6QsL4wcTzUp2/qs9QgjU8XGit3k/cjULbozcGUjIAI+kw0SBGK7YSFuwPqX8wL9DB3g\nkp3+ZQZYrrV+HA4SSlZFyBGx7FULmltpGyeb+cXtK4tzMW3n4MyJ9MGKPlQa3tFsGos94j2aQbOC\nVNiisdehWq3FIc7qA1UbBn345KmXJV1naKK6uvT/+Vdt+RHZJ+kLER0nKwqOvW+AfKxxDGl9yMyY\nyitekychJg9OUSERx4PpcqzrdqytEBhqDbdgYJRuXc5zccOoHVepxPPaQbJSDBc3StcDKwpiK++D\nCV3XBj6YwZFtzwdrJGlf0ZsO8Z2oJXYP/8yPy2Ni8Pu7Xhq3jJiq48ha7Vt5Hru6jPDydEIyXfRe\nKL1msdEF3joQlrzwBebaYMCN8JyR9RwzpsbSbfUA6U5EPZwGFmd8gDJA3j30A/HdYzouU0tW5BH0\nfmPAFW8pwrMt6lwpvFhUZ0v/R0N73Bs73vwFZTKfaAcdtDzUYS/sTkqZFE5eLCCNYeB/NlOHC40l\nQytRym/ovBUNU+BxqtzncLMomEtrW4mMmepiwiI5T5RS4Ujl+3R6w9+T9/QMLMaickQKkWZwqVTG\nzSiejc2L+VSZxnelvZveRjSe4M7rjdlSlzf77IIp/zi5EqlwzWyS4KnV6+fbRTllgyMLEjWBWO98\n4ozQvLL8DLQJNRJlj84SJ9FJa8moqTwzge/qbn986Tzyyw5p5+wpVjhXS/ap2FqXxTZ/mzNyVubZ\nTGLWkcn9HVl77bcCPuJ74n+9jh73LnNpp6UK3WfUF/2gjZjWdbC2uYf8g1zH72b8OgZ9W5Jpgh41\nR7hQH1sAz62gtgLAMJsRLUo7QfeA9u5YP/1Lb6qCR+l6VABUAbyjjjSBcYzvU5tI8nr7zdN5AuDL\neGz5pzj9MoxcfAsUQynu38xFer5Jz2+CjhAqRswjwB0kKiCLNTd6ucQ592iarUJ27REXpdyUoaPo\n/t8w690+9dwVjYpdk1OE+bexL02BrW6/EcOKO6yd20yFuz4qftuhCIYZASOhJ48tkdekoHM9llzg\nvDJio/cMnFApp6TgqI8tYdPnr4kOCKGWdtos2611qV1z+ZU1ql1qj3+ezNxoav9Mhsxl/CSbSWQy\nWTKJEIojDsNHVgkQU/n8D7i6kJTvyq1Kq7L+dAeQ6ofWJ6wFk3qcv+XqgBMdo88sSXVDzLPSLiaR\nVh+G2FC/LOAy+17nmFG38WwOHMR9S/fEHFfQwsGIBemFCb30mHxC/EClOP4jl1A8aBB8HQEBLgOw\nkgRPsIs/AXH4y3wNV7aS4R/CLsptZjJDvMrmye7iPunYEIThhtX9R2i3IO1UylRV9LFhIbMGvNCb\nKCi2WFJQhjpYStldgn6ngJIh9LHTCm6f719P4p6lbE1S+5Tg1V+fauzcEW3pNMQzCGacc+pytsMO\nSRYl0QOfUZ2fjRVNLTq6eyYhXDvSNzCUApnBD3XFBfs5xT71eI0PWGQ/Q6nlmPYNZLQZP1ryR8v3\nTUXIgkqzKiYHnzuMxwH7FYOyS8D2zDelV7ATLzCOZ0P1R+YcfBENrC7m4FdEcGLt7VhNN9CBgdo0\nfySrKsq1GYeuaHo1I4jEqHdxJhXBXxFLBPqtRTFs0O9mMuSakftrcfTIvxv7eVv+eWM6vDx1PCiF\nZa+ukRpHxHZo0id6LyWm27zaySHMRA3rBeQNr1iXdm4vO9iEepDN51Z9U/DMfagonUaB9rb94XQE\nWYacV0uGIHi79uUuoDwJxuD3MKYsqqL4x5rPBezKzeYz0c5+Cq8mhilybhKR57tf5oUBNaPDYx3n\n4cowhYUY4eI9GYo3tCikmRiTgBUIcLv0C6HoU4cXx+ukC1rJSVn4NBtYv1TWg4vNpju7wccHZKEA\nntfjhOScPi4sBMQGx0WaaK5NgJmQPqYE9agwkFWMmuEhj+jH9faXBJW0eDiVG6P4f/ia8ITpmeDn\n/3boMAcSwsn/3qxmudNX8G/CcDhnNA9aIytvTdRkWsV5CJoQAPI4PfF4UZytEz8srOcKzIVUTdjH\nzRkLDwnfCpDNqNMJOTSreVMAdAI80BszqQ73by56H+zaCOEBG5mkaFqnpLtZgKcAcwlKZ1MkeHwx\ntxLc8pshaJFKE4/xs6wEUY5YwpA9zbugheDJ2XAhUMIBSHHOxITCFVsWRWuV11GpfWm8hcBUs5vT\nnEvvhDvwxImK5r/j/pxwskU3jR4RxPvuXGmgiA3CtuDOSFMtMs0LTBGRC3sksh3i1FrQG9ouZ1fm\ng2ettdabjhyFeuq0TUcTWlJO4RC++9pq/ZPk6PppQH3oRfDG/FEssc6ymJwbCV7mHPAGx/XOo215\nM43rfv1qR0U+bCPVLhLR0RSNLVgG66MPscDNt/Uxi1Ce9cMEymcVAjoLYZYJLx7eJ0QjMFWkS7iw\nPdcdPQ3ceW4tDuS1Y4mH0t7mCQCtqb0H/pzSCEGOnBI9ogiKNOs65gVfNwzI5DcLutxIHSHO+IE1\nE4kZdhpEeJB1a+635ISUJoNctRtvlAA/Y7T39gvPs5IZ7VJSHXoJc/jgyDciin/nEUpQKZKt4t3+\nnxJ2C6DX7F7fFgJD64EVBF/QkTS7NBocGgR0WPJHbeGf4UVfCSGlJL9ZLZwKk+M+vUZZxYetQceG\n7kfiFM4t9ND/5ts8jN7Cz9YYVQrNjmgbep5gcHBpX/qrhtxrComuAWVresrCqJvd5pmNK53TVQOX\nC9tC8752KyIL0nLy1rEneJcmTXlew21YFoN0A5sr3Tc2mEMIHQ+PJVCr/SozlTjwyLwAtAdibm3n\nlXSfkMpOVKE5tH0kO1TE+/g7HCgtkDxLym0uxytdkvDOUqV7K26XqcPM/Fj6kk+b2Qs+UZdFDXaG\nvORMgXJbdC8DIo2u1dDFgUWShK8To15zNayvmBbYMsXh7CCxq+RmXIADZuwEK2FVzvs8b8wkutSc\n60SOv88L+dxQ5uBx4e7mzGg5jnpd2hpMcXJUZBW+Fatwh2Z+PHgvuoQnCox2zkU6zgImd2X5UMqY\nn8U0ZbJSgPFOo/wUIEflLOv2fZQl5U9VbZghbd3gB/pkRsZCTYiwSDgclZNGAlJwdTxmI6JoMdSw\n61j3ORlHbhe9nQiI20GjE0gRqkVUfM8g8OvzJvZvQmOcmHbYF4ZUW1DGgOLRLvcuOtj34i4dilfl\ng/R/qUns4ykV4NmHh0heNsvsTlvBVWSA5MVw5VVQxHfoog4Ue4LYbt7seLh9/wcq5bvcN3n61NJo\nSIvR32Pzca+Wa//UUAQtKzf6iIf7HWaoGBkkeFLB8Fza744ycGqk67tdE47zfzsPLcCUQhjK9fkT\ne52LphxCFnRodjr4Ih99TfW1NtRBUWjwAgy4/owzI/3NfydL9lt7npRzYSBS/l+tHyV4RuUFfr0q\nrebK8aSknASJQH9BdP9JlX+liLjO0vnRn0FESRAuMJ/0Q2NyU4v80m0B4Th8j3ZVB8poGeOhOu4k\nE1UsPjkqI1WeZxVzNjIzjWR2QMIBYs5e9u9ojY+mi8CVwtP3PA5VM1qJLa1NfRRZBECwX9O2CJrS\nFVipuLfJzsI5TuSh3Z1Tnn7pnLmdAcmUYlWVdIe6hI6v1/1YIM1KjNtlq2/PgMCmVMNwtHRMGLQ8\ny59xpAM+8pJO7ccrm7UYGqmIXQX0v6WC4OBALEX3Xa1p+qz10OJOxqnGrmdO9MyGPSutZ7JKbkc/\nClODY9t7LTs70e6w9Z3xI8KiHvqYLkNIVqCTsuHLH1PhHehSrJf+heHHn/WR6vPBq70Vx87CJ64A\nTKxXnWKRMn7jwc95+uDUF3kv6ERFTrUdF/9EKMOzs2lc5MzTgjkRQQtrhs6bgtX4mC8ks9hjrDoO\nyxVxAtGwpdarXXxxvfL65mjYyVcpfCMZ2FAFZlCXltvyULj2Z/xpuufYGURU+gJJN/sPhrJdkLCN\nz4s0sG38kvvj6kNcXb1ALpAEAIv4fnupN96tKB59RIaWzulnb+eVOvycfSmAWEd6e3hDpGNndCjX\nGhbcPOlXyN8DPwlwf7eXGZI2JEOt7MQwzozj7rH2FQgV9SwbIbsarbK709HMPpB4kT1IawL4QHbj\n01nHY0yEFmnRkxNDu9JI9Cco0atBnhgv8TTaffprtfoA+CW6/Iq53FV6GCfGJGiXRiQa+0GdN7bB\nPTw4/kuBnmi0yfnT2l1EQg2gryKfpmjvhBfdSugHZcHkTMW3OA/VpCm7p3nFBdPo92/RO1rrN9sV\nNWMLvA7lupZ8uOGsFXlcmag0pTIRvm6x9kfdluW9QN8/OzIR6d8u1i53Z31g8US+CPWcPgEtCxJx\nNyxbp9lv4x35r14HGp/KUzm6Sy11N9p/Mo26Gu+awKz/LaZCYsQqTJDXdZ5rHJTiyQrVYMRBzLD3\nnZGew//FV6EGIdaHfIdNaM1790czdD3q2aBOvzzWHvZaKGpiG30wr63ZC5YEuQThvV67YXSISUKg\nULFCYLgdf0rytzln8uZ7hLn8A65et2XzN9Wr5uhd838a3fYRVG86TaI0HbN1hcqQAkWvXg4VWiyW\nrF0V/R6JbFMWAK6OMMD8vTcV74+plfHtIOAoc1GLWFbYhywTjWFmz0LN/9plSFJ8NiWYmDYQhHI2\ngA7szwUUOlarAZl6nykcTU4o5PA40mswZ1OhjhjF7lYQMyQVku/eI8O+MGA5ml7NSkOb0OmFvMDE\nwdYY/E99AUooqh29C+hi4ADzUWQ9QrtFncUkwjR7gRd+YPpdCif4YFA8uFbzA50pOkkxQ3RLfJXn\nlrHFGQ3TnoJwbmah3uyUhE/P94I45Oxr0p7pTAvlMo5wffrd3vHYOOdUBaftTUDQwWHK189TBO4i\nlqeWEXkqdATaXZZ+hVA7us77QkJpnnPgM/qUxL1s+oOFiDQngQrjrIa3fZcdRt23XletfJJKCIFY\n15yzHJfCDnf3juyk6xnSY95rgKkjnFM4G1PTnmwfI13JMZQ4tGVShCdoiv6LY1DfYifzBU8ja8P6\nQOSIK4OMFlSAfGSrWitr4mybtbFkttf0Inz4Gkn3eAur7VhYpTQ7ZZH1M9dyodmQvJ7mMMRB8EiL\noblxZFoLska9Y2vESd3NT30eRulyISZe3tQoNmMj8i1frs2nTkno6OBjSF5KNCkKrTEfxquGcODT\nS4udZ5v78t85u8xXSc140hDpKdLvzWCay/9d2Xhy3hnit8Hwhv5hunPWyx65bhKJu57BeLPCxUTH\n33B27H8o/nagRRJGTUpCcW1b5gvdaQk1ywkagTEAqzNdd/KJ/ntLFGY++IEvYmP/dRzZmDVmKzqY\ng9boBuZF/T6Vo913o5TrKQwQ4kI/vkOXVt7kP+ZlGcq9hzgO+ldZWPKxXHrWOpLk/D9g98EeUWSf\nsaphjcT7ws2uwsFiEF6me2SG9a/nLO5bJIp7JnDryHZIHkz9a5/QfGN4HkAjECF5yhyOUJgtaKck\ndnURVBxY0QtoaBZS71UZR6k3ADO7qpny4MIP5i4X9FbLYQgqQeP0kmX7ks0BlC06Uvsk9Q0o+ZH1\neqLoMTxrm/OGtARAIpTeQEikyv4Nm4HQau1eEtupAEj5avNU4xAfAdgSFVk0XPyGq3gq92PQhZ5n\nKH8dwNaa0OWUFRvU3NrGq7x8k0fDlwC/cqvkbEqAt3qRC8Y4tW4w1bgxQQ4c2ymrtzFyBqA3Tie0\nqqY18KZ8aBbmM/7VspeK/IVKLUG7GDaryUzTXjCFtKyVhs7k40i+usycc4Cnb19kAKIYoYAqV6Ve\njKsGrJdiRZzR3dCbOAUdQSJbRsH/gHHFI/ZCCzz9UiNoXGojmu0VKYLuw3nUk25vZMTIYskaY0sF\n+fP3uBM3kUmoYJPQUChptP+cOTyQ4TRGuU7OITevxucSLcbmlEY+LvxnoNiGQBFkEy64Mh88YAzY\nnIBM1ekpBssVLaDobsrOfKPDodUoGZIkB4r2WLJrDxJ4/SCIRXbuoRISgwwWeJy4Rj3tjq49utzz\nke8ggEpY0JZja4LxYiAN1c9AwRbenEopDiZa91kbwa8/FryVKdJWb0jygimRMDTiPeSk+csJuMKY\n/ycjbLY+33V6qkzZNw3BSlvk+LMVllO9SpyHaWrm/haSqGCK64Nucu60tvdJK9dYEM9dOyWHbfrY\n/s13PJkRv2KjiQ1HL4yR1azm7aUI19VtJDG7cFldYg6ANouzY+Aii1is4XwN7hynlpwGQjXSDzJ4\nqp1kpsUoSHOXHNMm0+eHDxgAX/9Bd/Zkr/2Y3F8WvkkvB8E0yf70v4ZozNf0dV0N4mfgiW7utZDf\nVZ7TCcDvEZ86F8SHv0WjFb34SWQiK7j1kAXGgFri5DqXRgfpaH9tY/yuldy9XW74axbC7aFKwjmL\nQQJMscjNQa1q5kvtUwnKGpjb63Jm8P8a5Uvi7FurWMX5VWLPJylJhQ/UV8HwunoW92rBFRIZtb6X\nKj349yRYdVWOzWJQRoDjXl97EbFK1zagXylJFDnuPDkN459QFuWPMTHO3Hb3B4UsDFQwa4wm7IQQ\n8tt8+LeMGdqy5vO/u5n4iERuyFuWNSayoqThSJ6IIyfCEbkVff6U8HwqC7aUHAGy9qJ4fbIf2ass\nYhSXl+hU1tx2/YTiU3Wq7aBG46mBXN0IA/QTygxn+LOW8GhkrOoqNrxCseGw3Fg0kSNoN/GrsLbz\nUNh9PhK+RWyUxBw1//j4ZrRZURT5IzdjuhSJL1UNk6QcDnt0HiER10lATsMtq4JHStj5p5q08WM3\nwUydBYbaaYf+PNPYQZ5ZYuRrBRN6IRkBcLmKBTrpqPGs/Y+qNBvryTsb8wnuTvKc01KhOxXdvSaB\ngOMOL1/Ptel0RsJhXHPjhsekmCxI16DVy0SsltIxBNfncpepmCaXowCaQ+QBaSa2CZyJMMcmA9L3\n1dFsyrOy5E1T2FB8cZKKdRf+yBk3/cEuiBpwnwzp2l7ylWvxDwuE+EOlvya21+x3lpgVMGa1+49Q\nsAzCDgQtIIpr/wOoRZddYMLgJg+8zKxxHuH2cg1ta913b2g3Cu2MBqsvd4xx0EikYWKJK35f8Otx\nbEPPcjY5MdShpEMnBm/+rKUj9x7bxvYMpWrneZiBXI5FtMdHTN8+V3GjZIO576G1yEMRTVwh7skO\nMil0d1Sls+QnarBBAbjMoa83fGXFs+RueoUWpy+mGCcfq/exBEjqR1e58vrIMvw5RzygflBR5Q7r\njOSadoohAsmZVXjxbensFBPI9ecl13vLWAPLooW28Lj/+sPZgjZvkXPzdjrmYvj/XRcIQOihUWWh\n2xGTKu9FxqtSvfCV3ixEIs3OCTxTI5894eL9xofipA0lV/VVcyUZ/Xehvhi5+X/aXezyCUsIxAMP\nW9Pmq+oeFSlRobPLMNpmOcXQ8fltsN60c6a/XVt3DZW4eZjFkgpdDQg9ymhquXCOPCGjRkezR9q4\nct+s5Ly9NPCgwniLXq3RSUjyweQJxzR5x64gPFi93Gjsvsbs1EGDjP1Jr8H+3QGCpasPK2Joccjp\nSmFquQIeARjLUtb5FKwYzQpeBFu8JhFXbSqRhQjwMznCg1S14QrfJV5quOFyS6FO4sHjtKr2AcY/\nDURlC7bk8wtA3nH355Pu7L8066j8YHeiArKOHBK8iRKqSSoyuQLVR+mQBd4NER10Z+CNbiLHwQwH\nnGS/F8Z8xP+wkOLjarLnGuCW4/YyOmmGCiGSYvAo2dQ7d5wf36vwRtfRLaFzfVChx/FUloTqZGEK\nFRx99yNTT8S+XmrdHD+H1UwfT9JOx57Iaq4MXuiYWNZ9T3q+QOc2CnGyjldGl9jb+4ay1p1zMAtK\nfCjEm7pShTqB0CfBBfzXo67YWRQkeTxA+7MPYhYZ5iwDfix0mN+XMVOwGi5SNIeEaYcSkyihmFEv\nV43/f6CLR7I/eJLCmqwaS+AUrN2DNM6zGGBCDIUH5oCogF/cJJSDw/elVMRFCEy/uL8XJz+YEJ63\nLv5k63iQntTBg9Z9woN3LC6hKGA3VZAX3PKsr7lHEd8V/G2ewOYvIS8yqvFwswOHtNOyUt3SRcL+\nyeh6zPvk0o+5vSqXuJgidrlBCDawoOsUDeQAoEMWwfdtd8jx4rDAz0i/mO4N5LlQkNkJQGli1+TH\nktjBeXggoZiXQnkBCDYPPVyS7KwNs4S+zFOmNTlVy+mZ5cLbNvJ+z4zHfskwzxpKS/SSD29kb7i9\nFQevoB1lo7wsrjQpbbpZ+SkQgM18VCRD57jhZwdy9nMdp23w480qatJLxbBDDvRaOX82J13tQFI4\n7VRqj3Fd7SacFXuJViEAtNkrDvCDZOJOBNiSRcWwGcxHCmrSeRVcvF7kck4Uj+1QcaSaD6VFdWGh\nkiusxILPjYAaxud6iT+r+VfcNC9LVgM9tm+tjrrCeyI1i7++XgdCX9vfFda+vvGSvj4O46FfHJhZ\na9XsroCX2V74l419mEgrv/3Vo+FKoA+3ArJonPms/VyiKApQbPX1sVygif0hVcQyHMYL1YPoE/EA\nSw8m0OUL5B/ZVznrkEHrrnvE4VXfapKZ7X8d4o2dHgiRZ742WrCKFFSn5wpiFc41GjD2VWITMxIN\nkJZVkftvPgqdmVhitaoNlpIqD+9b28CVSUGXmjuPUx6P0r4dNeStPsprKC3k73MmtkO9HeA1CprL\nKCh90sRP8LPNz7Uu9FgIoLvX6U/jJBnN2SrIKJGVQLa5js+sZ3S620bEDwtdwfrAI54mfGbObGDo\ntzhShbJfJFxbL/zAcdLDITz8bNIdIbqbvdU2/rice+tHB9yb/hd49NPc9SJEvN9qsfk6GkuU5unB\neu+F9uPTS11IPv5dHxUZ8Az8po65tUUk6DJtR7iRjmI3e75z+XtiK0Euv1tZFnX4plYnYN2jkpVV\nd/AAMmn9Vvbj7RpmxW1WQ5Br1wHtv1N/kPsc2bynCA/0MBbdMd1JAcbLveTBHqoLb2UAmruX/HoY\nQ0p3hUsr1P82ok8XELPHDcfW8EFsPdkga/OCMOA5/Z4wEXHenAbp+QMsE48cVgKSEA1/wVw5mBuh\nzMShjQ39R2PULy1htExU55rCJXUpi7OO8dF7/G8ynXfcnFYmydwBsq2EEz9TXZuIBjtEINELR/MY\nHTyUkou99K8bWoc49bkeF4SpjEhVdfghSHH/aWsVH27glK00rXgwyw1gFmcOvn6jvS1839Qz3FGa\nMrr7vPjad87knw8aWek/YzNNnSByAEg5d/FMopYt2lLhmSGzhl31JlWM4jKOpaRCYYTOdbOyhoW+\nsAAD2sRf64C5BOcavaYnH5yQOlq9BfmIqUW7eZpJcEOSXoNWgWlb7o9tE9estDZCQGnn5SoVTJvp\nyfMB5YyPbHVdWuoT0WqNuU+IS5LzaT+m4Gos+RbVlQFY2ofkq1fgsY89jgVZUE5crhlekgLAjrOT\ncRmKa6jwbQTgjehYT//v48AFvnxflr+MwOYSA/lG40G7ipcoZbSohnqzgXB9e4+sBMrYx2LoS9Vs\nS96mVbCcTAEtcV3blR14N+yDu2mzbd23859GMsSTcKwn+EHVTtoC+EmXaNisJH+wev4qe8f0Wtkm\nc5YAzQvJpQLGbbe+pFDo+wFS/bDBaSBHVJt4lvFEcaNzAH/fMGtV2hI1yNNfYothZ4Puwm6DIczh\nwDdeqMfo8mgGk87RbEre8Lo8pi4YBclt9+3HXEIctRNq0l4ePx9JKNTzwuAx1z95h+1KrPKE8evt\nkb6HX5mcFN7EKZQNrpQxXC3JNJ/JGlhr4Lxwz738uK/jU+c7FNVDbskSW+UOLlW8uorgK0xMGppJ\n4EXUOKkZbIfFsONSyAvxRjNoL5xliW/rsqa43UFSwFxEm6uq/HiMlFx3nzeJcK44EfwHHDUGwdhz\nQNjFci6i8gW0zeezsiP2lTL9DRTCC6qeewC5crCwnCeRtTCC3fe+e+J18y1bdRZVEfCMWGfhviqP\n07ZHvS2UphPfYSITLs9xUFWq7JxSgoBe4RtynXXaLCUZX54/SubeoC6cGY+27j/Ftb0ybpiAp7K9\nHgaBIEULAvqE14PVncjqP7hEWR4GliyKNMDIjg7PrzRYUloOVFeLEZ1DRGv/Rk4uVfjZVLpveT2M\nsiRzKZ9xvUz2m5hx8bq7c7WpCutqCJPzZU5ye7hiL2E1ANpVYOCy4CivNiXe7zfyNmQKNm57bXF4\nxicCBhLv3d89NReSII3Bll+cvjqthCn/6sts7UrdSbV0TN3K9PnTMdoULge8abiKuoVxwv74KkV3\nOR5ajRRxAUN0kqT2Y1+OPtCDANgPjIasAkjjSx5+RgPMu5JbjGplWf6pDftkX7kLyoPSj1w/h2Y2\nrnQgCYIffXroVcqSpwo2qSoEwVtHESnICLgFWluUz7GGWWFSPsXzbQA5cOaTgn2dRKZEaLhYinEo\n4b2Ujq6+h6aty2Gadu8wEFCfqCFo1Sx6VgFg3sXB0x/fbznfqjPOdKTqBsgRZv+yoJo/JqK9h3x7\n1NpZn94AKnbXHbBrtVrK6PfEDCWoCheY3aXk9hs2qQec7uBabc5UfER57tJJTYMIFsAXO8N1MBPD\nPmFtyuRsBiGWF1gS73DOhmLQVANgBaOqBtS77AnnP1xXYmLveUHZModUN6D5ZtU5UbQVcMVW8QsL\ncbFNqNvIb1zSpRrKSCnxcUa5ctFgmAOOeWsnFKmnbxEOLzQkOkpU5FFeYAqvi8iwv5SYtGXi+WTj\nBOiAxtuUqm3bFvM6CxuDAovUazLGjH8xQp2rxwJaIn2kx8hoYiypnS+aBcN+gJGSTMyaxVvq2pCx\nXZXP511k0TvMG5Ahn7yOQsz8yNTW7dPNsrrc8Wqysq+PpBcX06JplSvb/gxjiZjpH588ii4PIe/N\nGevFQEh/vPZTeoEU+1uxnEcsHfJkP1s1loOArmY0EiYljFq/U8Rak98FdgV71luhJLLT/ER+3wV2\nwTW4Ych92Ho+A0IdKpJ3z4TaTrP9P2xHd+SpbktUssGOUFIXDP80YWWG0A5a4JMgEaD0J2HiiVA0\nX1zJ3dWLUmCybTcLieuPCqKqyPgBpjohU7tgMDcHdABOk3Nq/PyUidbMDq6zMLxyXpk6CQ/RkNxw\nGK3FviYlN5981qHPMnFOi5icuuJNOuZBURUdpINQGYtxzSSXsWMaQofzKG9awxLqTFDdm66RnskE\nA8/8JjPPqmXLl3AIvcr8tV7tDRpj/s3rYoTgUl4NHV3YmwZsO2S36wlFYN8rcypK9O3AfjCOkl+f\nOT5CYbQfykNBLWSKaeCdVveh0kS0LIuBaJxoN/bU/S/JPprxWOXyyB058LoocNsSBLK3QClSpRSQ\nT8Yp7GzLe95Va6y1LHdC+B2j6DzuvrcCD40hbCRNjeftgE2GJxOxAWY8Oge9PfAKBYi+TG0UORfx\n7gzZXnjpzchgTDa3Sf5DVo6/+KH0z4eHcnxMDV/E0nSxgNd4cvsBDB/RomlKNtMGPZMPbTxJctSY\nZyzUdO/fVFJbO0imgVsHm3MCRuttZzdS7S3G8glBdVC7naR0BU3wijicc7l8PVjdJFEriUU/X1eJ\nAcmuH1f/ke2cXCp/einDRqVTs/40JAsrkxWkyiY8L6v+K9//7Ep/F9RlYNGGie2msrX+vQjPgYG6\nmo6ufc0MuesYc/B5KCS7LxLFe4k9iKSz5/gTpFm8m5g7GqhOOBo6qWOs2Opjrn4WtyO98EEvZiS2\nLRX0oXZ25QcX9PoIpuKWBaSlxTvHWoO6oYD6U+gNFnscyk23E6c/fPZW+dH48J3mrq6T4/Voz1c2\nV/ldrD1VTBozokdJiTClB+Bznw9hzAZ9Dnz5v5EuyWyt3W6l95fj6s03CLmi7hG4IWQ1f7FmWnI0\n/B8tPaQA48UC1gG4yFj3+tktSW6ajQz0TO+6ET70NL8cRoWVLmFNidHjGlvBHJXNdsvywQSyaZ1P\nKfHZTTwD6uuxDCWs6dhBs3bnEMhXB7hV8rSbLbEtq5WRbfOndqXv1UoPr9IzYJURHusQV7vfNTJT\nurRyLj1GJs+LALD1N8aKRccoU82zgtyOQwmSToExdRGyC+0mQCG/In4ZGcjed0nJEYY/ljMYM2XO\nlcasEYGaz9ODGah2fPn/48Re/ft2zyX0jF3wpq3CGXOed4KR+O53K53cF52IcXDbm7MVSsvB9s52\nJoLfeIdGL6XNhL/SiVt+FmHsISPf3ZY7TdsAjjLd7W3EUUnPd24U37FNitflPpEg1iOl/CTkqyXh\nOiY7g3+d/FRCvKDFN+nf1rG5vfz2YvIh92sS/ulY8HTwgMZYqZzwniZ83Aafa5aaBXdVorzFJf8g\nE9cufv8KAD3HW97tlUpbHLY5yEQfnv5KtZshVpvgXWJUL7+vTCxnyLxKGATo5pZM+rrwc6vAM8O9\n7s7xogpvyslj8n559qBE/DurfOgBRLHVolz1z3v4jDfIkqnT57tGJiWNNcFYpumCzdaesNQ8I7yK\nmzJb7OA/RitijMbMOBCKIjAeiW6XRNR5ZDmArKAixj8m1HUq9/WY/8Zzm1heASYhTIaUKAh31IeI\nfNnXFq871dVuO0cxPYzxIRT/HT446hAt5DlFJ3sBsqHM+r7MrdT2zS+ivN/xMhR4J3mtGo18qG27\nqyF0IRXbTxQeHzGT8zFWMf8rNqgCVsZyml1Dl3nLUvilZLer58AKRUbvXoeMTb/gbIHOZqDbjuu9\nPz92lUt1yWtkljPrYdt67mHDCrfXwSkr8VRRxjQpG+9ZPSdsVtPo2hxVtug28l9JBCxJAcZBBP4s\nPhBtE4orkdzg7HwYOXdOI2Sg2OuIXghd1z0N0SJ93duL7efKwPGAXzAd3/h6pvygnkrz2eZLYlLH\nIHAsDJlBmUczgrxvKmgRzT8AiK/1Z1EU0xnkkyGk/ElhvHS5v1a0OpfFnhRbraIQ+TMqA3/uhkVM\nCpXQO3mq53VV8LX8ymDGti3XtwrQb3zvJ8Xag7SiIX3h4KFVOhpUqQGgPfEYEnfguJ2oLY2OOED6\n8OXuNwg+Q4Inf3Vwx7CTsz9dbTiigp4U/ipnJBSKy64ErNfMbjtoKibjjAX/bxPzSx/7Z/P5fhoH\nHnBC/T77OhJSgyBtJy8gYPoCxhmdJI8zKzzWaApcDAVljrhPMWbff0P3Djvl3RyQUtfTc5+6WB8p\n9RmqM+mRROHSLCV267FIl6ob7Zt9a6AZGiwS8LBCUIaazYF6ZZTa9nxEgl1gnnWeuJpUgB+CnrBw\nkaceIaJ9UN4psPxyFTFs0diFF7dcz09nsHF61HXQ5FWjFQ5GXZ7MZLBeqTGOmDRGFPEGHHkya2tY\nQIexINAj13AXpFLz8Kw7fTA7z1JGtMdL7jYdyDNorL2kj47G8GuSdrRYtTzbldxQM/96Cx5BRX+t\nzx+poCouHD87CwI9xuOW25OsxKXsr0qSG0QlKR6tuxqLc2G/TrNinmqv2MY5CxBCVA8nbnX6RUHU\n7RHO/vLlwxecgkyoImRjChuxUYaJk4KH3KfdalkexLxJlLrz0EALfG5GXz+MRcRyhU+hCP0jX9g2\nN0RR37u/dauTfhS87jU+sMrw93qJhLwcoz/xvYyJGmbTEkutm46u7T60FtzUNQYu+sMQoqCsPk6s\nqfqrv/be7cJL/b2JtEjW4Q3aaw7ytFD0Uh4+Fe3ALAUc3RfO4dvInOhxKkEBtrJik6E12rHDWUj6\njK7EIxhhQq69blPKeIhiWiniAMWCioJGu/diqQDh2tGooXkLR0aRJ9neO5ubqXIBsCHBs4JRHtbp\nFPFgV2i/9AhRAK0tnHBeh7X8Vu5C4OM2A/Sy8G/ZQjI2bZ0qOoW70/uNeKOZgrSJmadpnJMfiUUN\n5e6PLR2bhhIdi3caMrTvhupwGPFvbHTM1aW/egicbR9c6rrD/F97M8w/sqs80sa9j3Y7i3d6bNQo\nnAwtx9+hJGSut+RCg7iC2df0xxcKvUJ6Ty1tq8l/kUqIfl4W9m8saG4ffUKOWuWpA/S1Zdqp1lLA\nc0R6NNb7ogCF4Gi2TLQ6D7vvunSU5UNcXJsHbReW4Ff8HF+JBNMNLg7Q7X94pn6Jy0Nyuunulh6v\ndywt36J+KvBDT0G/8DjNGAU/E3z/WPRmdiqonyUS/+H6fZXGncY6j806RU7eiUtWw/7h3P2YX6Ec\nnYNFlw5mg79evSHimbRt4nQjOcK49upquVJyg15X9V+lXvD7jLUE181+NlT8FCkuyGMS8PsNTL9+\ntwwVC4+hXdVOMUijGSvURVDN5Xa1xvid+ZU/0cCrkYd0cLPCQov158Rh/4u75UfVDbfljEOl0697\nh2kc9IOUnmeFnKs0Dl0Lts+a1dd28R5kO1cXnCH5PwCnHmqKJefAEEmiVXifyuYRVcaif7AP1tUg\n+uii6H64woAmB4WHAnft1yBCdRL4NzzSz4kw3c2LvUOrEcajKRfRXLAOtAmbubqgZdTf9YPAchWY\n81LpXsCkkmXspQn2UaUY5aXjUpyKQJ0NcbdU1mCeXawAR1r+dA+NMGc8v0J7vBzuciJcl7KjLszA\nFyoe4YZMXLyfAku8fe3rYZD9wGnCzawDHCXp7qkuSnh7unnlFyQc7KnmogtYOS5nyBqSFkqOGPun\nCFUKknoOWmlXFdShcmG2MAdaJ6isjlQK7oioFtjlnv39jJAvuJ9H4L1jNHoCYbTf69xuUsKXbg/8\nlzGgVYw/1ZZqoPnXNdg02c1coEYjcUcYAN4kZUIxOQKB0L2dTqCn8o8dp2KXqrb2mywFuy4GWJBE\nlLUGNT9O8hRShQHF+rhIS19SmGH28OwerPtbDew9QTbcWFOfZJdvs97k7sHn/75rB0ii3H5iOOvd\nBJUGD05jwsVSDpZt8eLetDSRAug6hNlbta6QZbh8p5Xhyt11p+Z4V3JT67iW7Qog+vS05RE43csH\n1u0fM+pO52IIL1ftY7M16HquaprH+1yMAoEBNLlwWxe2D/lxq9INNwvkT6Esc6B0L8mRVViMn7vm\n1AU/NB+0Ml/YFNtZn0gteO3ujkGedY/fgGO2Phf95bssBcO9m5L66TzgMrg9H9qrWtn3saykhLr7\nODMSqVyhCHABncgOPPBv5IDbdRna07ZpsnPOKYf9gk6aVn+eKDbnKCEdmo8t2npp4Y48x+6LjGdj\naELEqqO0l9nXDc5V37IooxCS1DYuVhtBAxhdzx5ry39frz7296X/EpGUbCUPZwixEu+MvSF0IPZ1\nsem8S4LeWSdtgGcLKVIWuQ+hVKre7XSkUzy4QACN1obkWUekdj506hCGdLZsi1G2kCDY66EYuvB6\n1VV55ridr1p702fZF5JPPYdKG3K4Kbg2ZN9iqDWFQ+RTtyAkMGlH6g7j5rDdrMzP+80IcmUGQzI8\nm0mFlacuoDIWLZ9hBarnmyg+KkUT78RFYKrAMMmNB/u1IVzguPCdYZnOTqPUnCFYL8CJSc3jxpO5\n13lqAjxQ2xvg/Ms6cw4y08sDnOq59Z3hWJpBwKz0v+zoGg6K0YxYoX9vp4f4a/6kXcHCKbIe/DdX\nn2iMQttYYulEcCQUhj0zFpBmdtA9kMPmzHcI6ADmmFIQU/243QHmnZhF26qImq1zT/K54RoXu+MX\n39rHxSnBQX67bgby7ViV4h/ILYuq5TGinxG26FvMTgXSqp+c7XMNiaLwOVb6VXZg7WcAvGx3nwbn\nPEXUKP/ikBw7d5aW0wORt+u8Z8Ppj608wL8t9QLJqvt2I8cmyO/UILRjRS5fodih5xPrqNif8U1v\nfh+NJmodpqvGR3fg3EIsoYboyQolFz57BIMDLVAlyvizA88VIOjw9s/vsOE/xJDQKZkpEhC93UUE\nguBGFknUvZYFi+WIxtdiO+lGfI0x+T+FsnjiM9kkbfNZ0scFWTiV3/w/CAxU+U0PkaLj+tq7SxsS\nJLaCeqrD36EEHqYrorEcFrxEl/r5PaFIk46I8d/h6vna2qQQVyrrRauSaj+kZkT5gDdqVCJq9yME\nsq4IwZVpkqMtYZ7lY67P4MsiOhm4MW8MO1moKLbzeOCQRTDzjaX/3UjivBqL1JjVlUHOr9eqAnYc\nPIV8apfpmgiGhDiatLbJSrStslFn8YNHa6nMwPVXXOJ7ykShCY6ZSV/30h0qAAyFZHlcxA0XzyVO\n9MJq4paPKCYc8TnfmQWlT+goVHY1QM9xc57vtMB/Lu8p7z055OPPfmFuXpSaqF0999TKaVmT9uXK\n3WZZ09TzdpMzY7/7DZRREa3aKh8i2TWfjm/gCg4uhTRn3XVdzfJBqTPd3XBQiinzjl80gyX9DFdk\nFk+SBujjD2ucPKCRxOvOV/HVTVT2LbtNfvWBzNd9LmLfrZiBkTMIf4ZsYfe4SKF7SGdTAx7iYMtM\nmUD7JEIsdZGSB2qIdBKdM2xGK+WaA0Wz0d/Sni336yQcAHSLnfuqowfnpYGq/of0iuH59QH8maQ9\nrpJgyhBbs9uCjUr97WJnGYT5/Opdc0TtdmIjBGCSpAmMgnWfulfF/NYP2Tyqlt2aC7jrdRkZy0H6\n+mZ8t8BT5Mj6BeW/s4FogJRoAL+sadom8yQv++O4X8mH2pQzseWOjSOB+qEE7FWZOIIJanWYVSWr\nSj4WSnAeQobpPIjbruX37YrgQ4PquyF9fJ3oybIL34fd8oo6gTbLM/ly37LLo6EL5Sy/u+D9aUB5\ny6JCj4r4UlHiKADJ0GuGFpy1MSd028vBHQhqU1PEf6a3jgkF5yTXX/r+PezT7c5LzJs2aAsjo1GN\nZrGgQTblJdZSKoPLNiyivShFr5bJizA0c9XkdawtcCiy4XYKLaI2c8kckU4ZK6HyEZG8QE19aYYQ\nQfYLrXCCtNE1/7u3KPJTVrj/0rsXkp4irfgb0bYP3hzRrh48Y4LwqLKBOAIMN4IoZIos+aKkqeXv\nuKPkYXKkT3zS28E1iol1iu582aPB5mp4DKi8AH3zs5xhW3vgemddTJ2ACjhJ/8C6EUdRSKnW46dI\nFDcxPrni2jtKFvfa133otigBXQyKOVLCJwop86Ca1IIYEe0SbwZyJukHVTWn48RMJDI6Z1nDnxdK\nsgUVDwGAicPVJegSB2flxgvBCfDwAVehQhvWAcMdIWUzlgN19gsetrrlJBYXXkhgQ6icp3hpbhV6\nVTiE8tW4QokHpUnfgXB4RJ2YshBDeKKK49iOYF5vNl14dl01s9vjCZ3QVTAL0kM2IVAczvUOpFjj\n5u7Ya3dNjqoZTzE0DzbuBAv/FEffjCnxpeKMWvk1AcFJESeJp0fTXNXF/4kQSVqdZ/FeNK5PJDmH\nv/r/Y8RXsMBy0zx817qHot+B+1mABUfxJrVn3SX3QFSvccmCZOT0oHF4zQGhntly6yQAqpWiCVGq\nvL8uqDL7xxRMIIRLR1zQsZLiQ2b/9ePBfO6WDmEYHFBV1laz/0mr4urW9gk3hzYBhtEUrv0EFa+J\nkOl9MIXA7t5+86rBa9hzyt5L5EiyK8fa/hCs+rWFjcfL6QkQgUDwHlJbHiwGD1NK10BqxjNzVU+y\n9R3DT08IlBTID51PLqu9zInvTKhzfTxseyiCRbSehS6Vvhc2JMA9hvt0RMmLDBjJ29gncnlHYs1T\nzBacH2anVRlm3v+Vis5ZCGq+x8UJ1qzxTCO/1x3OJ7dBxgFesIKwg2OHlJHwvp6qhi6cckGidghU\nv1eQTlNx11qd3qdVwCkuZ2b4P8ACJfPv9CJOP+JpG1L9GoUDa54gVSCyAiAkc9IK0Eszg2/wckCY\nLj/zsGAR+8nWWTknWd1jVp3UZsZ+IeuyGZuZXv31/jzPw/ZgJJTWIDaFQ/xDDWkyLfY0GwLharP9\nM9N6UKcLcepuPgTvX31WUwQNa3RTExt4F+m/Y6148ZBBr+wAOIyrs3hf9+j+HXS+RSZjlmMEYzrj\nkGP6PdRlnbWTAkEf9rkOWcxSqveocNato9V0HZ06LGPz/1QAjCjWJlJE1fRB2EoJrpR/BlT9HUNd\npazsJNIDlBPJF27e4f+NUJHu72jI8tnBoeKcFAD69zAbl0wJG+a+CyvZRmeHQABlelbahYMJWv/L\nSz1OFzUmLwN2PB9kTuUHAVsnU/pQLoJUIilQWe2bNDfJxNLkeLcWqrx0Q4AFgrKrHLfqwjRl1Ndv\nuQBGxgcRnZyYyST4EIvUIsS8abA5EAgbZY3oa0ZQma3i86FXszbLhp7le7QfD+1BxcXcKhEDjRTy\n5aAbBceaAHaYbzO+k45zyp15dr/3h2t1qT8pokX2kokvff8BmqBFZUO42cAMnvpvfsd4b+zhL9x+\nhqd8VCsfOBve1rJAK+mIb2oOMF5B2+6ghlSRhqIiMJEpPCVERS3QLqkIsQb26vjHtSHy1GzDpyIP\nYV0D74/K+MFXqAsleGxQZmQ5W3V+SR+vf0KHjQG6xwO9y1Azw/FeM0B3fYs1YzPGa3djmvnG7I6e\nfWXG2jgD4JEEPYPwTW0i9hhp3KIhUZpFIj5jsnkqe1+LRns9UyUKPHRQ5IyvMJO0q6bechC2FcyA\nPM5aXM5rIquPXuuNdR5d7Vx6Ur46R54TSl+mP0tHz4Rcxx2NybTS5cXPIMH2n7cg9Qj6iI4AN1on\n3skWsduFH+E/hm6LGXfoclFzKHXAqjbCAyfCnCwXTI+b1qNQjR1oUh8Cv/RDAUc1Ioni2HuDmhL5\nVnlC5bsA7tIl1e0T/Klih2g7bK1Rr7cUp8k6UcNKhvPdJzD2Ghgv1xJR6nEXRcpF7jXCUWVqhqia\nvgz4zpT51lQcZ6fCu2nKZU0K2WOCtmCiIOWRSUrY8aj0qn/3CpxEdxaYg+Hzp8S1AWcPQtyA+vWe\nPjYhTLyNjx6zA+1J0QakA6+Q4c+frNLGbpjUwltHVp4gAwf+kl47gNczeyVZpR1nnNw/8BObdUfQ\n8vtNKnBNnyKwphfraAmuMuiWlesaWu0NGMvpfGJ57fkAHJvuCHYwD/+Z5fFTcXqiACX6y56qs0V2\nxAhW1ellwEan9N9ME/cZJKmmGa0EX8BuFM/9TA3buorS2+EwR3P1cgoJBfaDRViQcj1/fmc+tAPM\ngJDY9VhIZRiQNqb1QX7+BWnYkZ96OWJ3vWRfPIhKnUWbdYkaIq9ekGnCA9QGhicIB9+gUF72iSZG\neQ/uetQNa1Kg6y3Lxq//Vv727oG3jd0I32uA93bGoVaUw098+PCyr/HGIk2FwTeDoo3T+13pJZZi\nSx9KjgQ9Xbjav1qUjjJVf7NZB+3ExX2wIQSlFUgzoMqeNaONIiL0X/pTSW8VDkYGO3AOe++rHwTr\nOFzyEUlbIhV1Dwtb6eRy3zul0i28KzCtpKPB5uD7xjKrEuTetIdYx03Tr41GQA0VLlhg+HnXoA8Z\njNpli/n3DTbB/Q0pHBxciGRghVzgeCIihnKwigWOMm1NQMrVfE5tk3mkVvkfj4naXn0UD8cSi8Kx\nU417m5B1MDTa0TaR6AoHng/wHX+j5tVavkyWlSykOjtgSRI3LNLSDxVFgVrgYI2yeEiOgOqwIATA\nK4lL58KbMhQ0jrrE9EC9WSl2TaCbfyB2fuBta9lU2qv9OxG1m5n2hoLjjqFmkGTkHCI2V73sqACk\n8btzQ4INRW7nl0KKVOrLR09XZDdzBT/bfvOJTzQonqx5CGZP/H8R14NXrZbfqMD2W5eI1bNh6YRw\nFDGVZ6VdnXZHEYcCvqrUjwdaCxmA7ykwZteG8Ikf/i4Run4/Vt15sTHllrH6mcyHo1hw0/Snwpuo\npuj8/K5io909dLPh327DkgL0928nJpJvCGGLImUXW768SImd//aB9S/CjV9LDRm78eo6u9TZvkUR\nllmQcEcM70VHI4tx+kUpknSooNldVsDKYVNFZTijNl15WLukXRGwesR1GRn0Y8r6fOu57McsrZua\nEtqtgHcwRxwLnCadSY/x0EFD33qCW+b5ufhkeTOj0TZimt5st3iglEvfiaNWKxCxBUvE3xhue1G1\nnJtS6MGTQYBNjUJgTjO+16Es9FkZbYbtd1AomxAH8/xQPz7Qa5fvSLcI6JFZVu5qQLabnbvF0Yyb\nxWuDcDnkX+IctVH4F6z0qKU7qsKdxKJp+Fj372LknKep8y6InjfQWwiSpmJa7wjsCbreHNRZlBER\nNEA/u+XTCZxsxAlMxSF8Q8N6I8mLv8HqDnwlDwsoNX2WOOId9SwwPLN3ymU5dT4HV2ASBXhrKFFg\n5wSR2MtDnF50cbqiU9CWNELpwgPP4v5NzCg0t+ND8aWXBhSElrTwtZOg+w87Vw2pXLJUNxrdGXs1\nQhB/6OIpCOjMLQqIEaXBc+4onBU5RNEyj+HYq4OMVF2Gy+Cw1vr6SxWHtnLlDE3Ec2Z6NQW8qkF6\nUnbRTzr586tfAkukgwl9ZkCC+w58mB+AtMNU2jh0QqoF0WI34xuWZu+TvIk7TRZyYzFYWIFyRLDi\nHHM3rVsPnxLg/6OklkrO3otCTI0CkRXWUZF4Q6Sg/PrbajbqaY/JkA4Y+t+icE/qDzy1t619lx5r\n+RccSWEiV66XocWWuAQvDsvo6Ody04y30TPjqlOrvbH1WouoYDzrCFL/USrLQFRb8pIzwCuxMkF0\ntyMXx8VXIuf/TYROi1UGKrhMAXHthMs6Ja9bhgObYBGlrKjVzBS21+D5278TxC5lQVt/O1yzWdMp\nhIzEbP4rMhGAqfEWC7Ha3m7KBoMSumkWNk28xsT5i5R/Rc2ztDtWR7kSkckQ2+qmSPv1cu4TwEwe\nsV4wspVXj1jcq4PCUdCrlsQ0Z7w1xnNqXbHCSdpVtPZlWycvMn2zbw4O1veTxH7pIAyfi3MCzSo5\n8WRI01TNTc3k580m+gSKk143ctURn1GxLN4VR+LmEiV9s4tfP0qYPKw1YMsK3hyHfhsSGZB6+wKi\nxcEgy00Des6feodPZQtJ+3Gnrau3olJMXAH/GPW4ZEqUKIpdDeXus8ac1a8CDoAOnHFqU698SGoc\nYggSotWj76SjwbYD/ui9frHfvH65LnkfEGbC4NUZRItuu5UIg5dwm9MWVyXXM83/Q0p5tLcijjta\nGsx2vMsBHNwrxSI3vCSg683ByZeWUFIIb4g9zckmSbKPdmGHmUyobLFBeYd+m1Q1keoDPn3JQUcr\nPfpsXodTSp7VkLGXJNOVyJruRPt5lrC1AfIsdUZP0PWR+IdVSYzVmHA0kxA06F10qadvKWkrDdwE\nVz5JVO6SWVu2XfHsLXz3ujo8RxqHJ6vvCjLBft0C1ExxdepwZXuiqd5UEbGcM30On80fcIgL9umR\nJihB13OF2tRAzpAlhOaVkEBr0Z59Acx2e3D+EY/G6rZc+XAhDsfO1N3R4X5i1ZC5frRmHD5kU1n/\nOyPaMCFV/bDcjjKK9AWgb9IJ1NfOWQHAS7bw56qA7P0YmgrPFqVe0Vt2bhjWKEzV2NbEc5tz2P3x\nSqc9Pe2gZ8BWXEfMo70IV7qPjZfmBiLrRrU0S5xk+utiBmZx45liblJCTX+XZ63BMZkJRVfRYPXu\nxJx5YN9z0Iz9/i1jk4NQygR2SKQ37XNCKHwCib6g5o36noJ7WJiF323TjuazTJ8DqNmoNnQoIl62\nYXhuEYpYqJQZkL9yOZzImESLveUEtZP92fQ+GRphjpAZhgB0keqkYldp6UOWMgvJ5fCSMrS/TrE/\nXBchBSV1Vu2dSCYyxPQEaaWLlvl91/XMz7nlrX09anp8VdF7EHf4Z/pyJ+/7nNcMIpnqhCyEx82S\nhXdKdkiees0of6KeEe7jnjtwSd7XZ3s6RhFkt9e+TRSuprNz1FtIP795jfe0K8lKFSdSe1bNYJM3\ndu6andT9MugdnE/5qzCq5WLRRfdpGaXpoPSYAEnXx7UbOln9XzLB70OWo9AUKNjCokznzdTF1iUv\n/FMc6ouVf7ymZg4sy0fYsSAuVpNLNCmHxj9nsznYd22VEX+G2QLwyoTjQ1a5MdQHgzBm6bCV1OV3\nBIDiTMY5nE2vZMAVBk2VJ9SHjJOPT9ri+ncMLHZpMgwWg9522tVDG4ZBfNBvkkYS8QaLvfTPCdw8\n9PUpy2PJch9Sd3bbR/gIAf0RAIJ3qSIvp2MZBatX0NlEb1f46IX7X3yD0U4iw0bYblyYGqDBvyIM\nItVpkZ7oVznGcwYk7yEnQthE5k1kXaXIHU5PyUBOA0xwlykpHrfT9fE5xuGDHxDoC7LJL6xFLVIb\nP/wdQELRDME2lSPNQs+J+ZdDtyTA1o3/bWA5Y82wWzsk8ukcGP0OBZT76eNxfJ5+kkOGqnWaS7z0\naOlkrnNDmAr3XWRR2akT8nAf40k/KNAOKTCHaSXiIZWbBCrBVI/j0PiSl9J5NFk3zPpkmYbsBJN3\nYRE23wid1QHRQVt4LKVDCkPDIl8kOXu6IggI5rYP0tuYIBH72CzprgAjey3IaUROEUHHlLFn2DQT\nwJFgwBPSfpH3g9z8FPmMn32unaPbhmnazHEMkGXYgsT6pUEpkoaOMK3/tbkYXGiyQOOiVlirgMkG\nsomqTJqv28e7pk/mXA/G+e0EHDfXSWlYfmOv9+o2s9l+qZ9ZQRnjW6FeIt1o2Th9n2gBVoeLsSp6\nxJrLHiuE9qcn6YuUMVL0yJMepyPFc0jNnbpYpj5OazH7UwSuKiUcI9qxCaiFiNtYitddawCXrsxR\nV7uXMaHt2nsqAAyE7JL+zahUEqZa+GzBdZP+4dJJ79rVXRAmYtfPbW6H4h5Jyw/XIcjRNOkV3r5F\nSnDPGlpcVqOwurwsyCgLGur62oMJwacQIyz1cEuKl0AstpO8s+yXh/20sDXu2SGBur+vU9ImZzt2\ndR6gFtCn8quKOgKgB+eU8yJhrYpQvCE22wiVaZt/G0+RxuneBVDEWbJqtZ8AC1h22z9RHTrrMpfb\njZOHnHsmlXNod6NjD+yHltbceWnnwj4Qw/iRXi0anyPuxk6hBMYJ4KP1gefGe8869mT+1mBK4ThL\nydUfjJDm1HlmTVfQmwsTVOT0YwKtK3xzT1dkr3EZDRh19KXRKfJJmbQNt/J70r8Ix8b8zcmw7LN7\nsKN8SHqtSXLiNX28Xuw6u1jbfjOjC5vXjdh76edkmF61s9kmuwrRfOVW0ODSx0nm3W8SzrVHYcQR\nOfOHAy+1mFF/S/oi6XJxTmVb55cqPCvrzBITLLZ0hNa6oaBUL0hCmGtxAS4NVgURwz4J/pH3z8z/\nVs0cUtypoyrSeQr93+k/Dt/9JLd4yyT8oMLxNre5QhFNCf3uX8OQhipO9ilFZ4hucxbkyEyHMf0x\nzZa7p1bH/L0Pqd8W7ITVUWXJ17V4G/PMihYDXBSegDt91S53ioOweNENt0337jnD61urjrv8xiki\ngF1pmSrJH38xa9iTJxMft+Q8pci3zHHnFYjCRvT7k/FZ1ddX6FdelGep8QlANjH7yOuwgilSzuQJ\n02u4B2QkJ5+lz5BM4vGGmTYFs5WFTcF+WCGGjnt/18iPjg1bINA10Jp0q2xvsSDVrtP8/o9dW7ZE\nTPW6fA4SAzwa17fUTMJhC2CLzqgNjgEBBPjXaqV+8ZP560/41vWD6IX1r+7hDRsFKDUw6ykxcAbn\nByBjPf10pQeaUF6XgEg/FsJFZ1rLjdw9TRXNb5BR9qf6nuZHu4iMYnqXt5jDZQSaeqlrHL/ep5kv\n/7MrkJJRNZYgmFMBw/3WG3TmhBJuysiKWaIJRiyU9QOgWTcmwifIJ6i0N474JerMehkPhRjJniHS\n73G3QNC2khvgrAbYBqebxZqRqL3K5xE/6v4ZfDsPjP5+hkBiqMXyvhdSQ9q2Okz4uglzxnKBTh7n\n0wCuK52BdjgOVZpg6acbRrSOrtcxiewKEZagMDeL+hTZuCEtw4zOO+H2VJRcqsccEdSkXTcM6oxp\nkqqYF6LUDjfw5Z1C0YdBm1pbNsMCyx4NIzURZTa8OAdc9oPsdiBMm2e0JyVMRPTwlsyONz2vGFI4\nKohQbTi6Y9Re0D27PFjn06jyDWO0XhA8ejyyXhuN+LqT7MwjYeW/NsunUMigCZHD5F0+pwhvw5Vv\nLwQEUCOaqhHMET1wqXIaIn7n8JsnDE+M5Nul+m5qarAsr74Y4s5xXVezfo1K/SuRHSZVuSKRoWW3\nBwCORopvE/dGxygTWfmj4sf9WQ3TZUlalKGTcZ5JpklySxmbAx7yiv8HCoeYotCP+NTWld8hv4QA\napsa21g859eatCX8EEy8EtdsKuaV7035XDYrvyEv27hwOcnqwCbaN6ypf08TTysHcMLse6zW823X\nHDvnGPvYSEgOPm/NrIIzWNmNJrFEqbhqQNnwf2UUF0jZG1WqT1AmuHtoOiyy1Lr1lyvn3nWfFFiZ\n6ut7C+jsniU4tr16qGl6QsaiB7WjoxGyzopIAtOio5uWN2pKzvoTKyXxVu0WvKftOVOml4poIjh6\nxrFr5umyX+0HkeXcJgwxkuvFtaXexlN5CbN2peJbCukmxGJjZW5UqjwRZ0MmaIWWXzsJfAMsEqa6\n9Tj5JHqEOLAImpJ9Nrs/K8YXl80tXg0uZXe1eCeVuwiDJxUNd+kiijbaUxF7ge0HNTQoPIzqENYM\ntMBhQ+U6WUTT2PIa625LrCkrJWqJBjbnY/97cEC5DvGXbdtCaJJFv43R4eQgkqD9WkhsQ+lDjM06\n0E+E4OzuTR5JBmgP8GJsxT7dIaPBG8sgzoM98vCGk5d4wFmRIGvYQESXHWQ28jFuf1RXbp7MS1WY\n7fgT3yKiSEwvTw5KKeBud9gIfp+rN2jvA3AKyYo2HkGyauml+Y3bXnKwJ1EfAWpOu7AmtJIKSEyi\nJ1QFtpfrFKkXY02sZOCPZ9vOPuUDPUsp0tfI6bhnPHUYo3zv19nNV60vUaUyVSbsjwpqLzBZ7Ea3\nD03v8v2wmGyvIoAoAqXffJTGSjHIr9S6ZgSvEkvA+j85jb1d3G4XIfIuPsHIRxCf05H01ONAFh+O\nT2uSLCc+1amn3KcwbV3Z1az9p4P/8TEArbk42dc+RjwmJU6QDwukQ++l88IUGzb+RBYnjBG0y8P2\nFWqDnJQOjaD1ohEmHIOq+8r4IVvrsKQDbnKLU/saEM6MWEvNGYIHR4aSj63teVJ3gkRAfFFyuxoG\ncjPzCTuIdpGouhNAvBUFjTGmZidCuPdI0MAM0v8YxNSjHPd6qj7EJzQrjnUdKYGTLQi/Dwuqf2ZC\n65kP43zbVZ3YT+261YmknVjXxZIsJtp/oBwwdVyo04joN5iudXDlDjS51A3e2KdvvsCvJFzkHuyL\nLxmnY5qKHxj0Sms67WLTzFpVNPYtoHvNXPoxJ71ZaYk5ytTBvNGQWvr1dUiU/A1fbepRNcVzii7x\n1o47OdW0DKOaGriJM9dfmHirvA9dg0IBOO4/pqwHmNnzCxQkeWKCAuHNzSWajwPZZWJCN7F3VOoh\nIHgM7wuzzvUr9lwQYg97kvgdTWhaowajLqVn3oezPOE6vK+/YPtssGyrXqM6fprm9c/jlSD5B9cG\nYcy3VSo0ikn/No7OZPEyDLS/3lbyW5McSpUfRBRdF+L32G70OhnNn4KuT+8XmBLQOb5Ai6yM0Gac\n/AUzIrTqsvf9wrH41J8GU2mWYHovwmQG6fl9ybJ1SlUWYAIfoYvSInanHVBY8o47hwk1+EQ5ldfc\nIl++9rVvvSigewU5jHg181+rFthOBRfZfxHlYlRPjy0M84La7kKau5HIM4u1GwZT+aq84MAtfDpY\nbwuZoiYEJ3/xwmSouP2aIHSlf+sBQesjhwDg0ZDFARG5bJD1/M09+yGsRG+XePqSNm9LZX5Yw/Q0\n+mg9EvwvFWw/fP4fYujGp2SVh8xHSPQAsAOhzqDsQIAawWMu7d0wQdMLUXf7A5HQmU1fEQRkue74\nZupsYVwXiBGqicTDKmAUgJompGhOWH0Y8vxvfwe0ATp3U8VaEXvQrnk229Hv1htmNg/PPU5G8Afe\nNv6JvKNcJChlWh0B/fJ9dVaUAcP5gOIi08Bf9aD34hqOquJ+mXabVNfxMa42Bqdu4Qs1RW+mPvMr\n/tVu03E0VZgE+jFfw6S43Ds9h9kVCWxEPDTIV48AC2t709yscwUAW7Zi4w/C9cnVSoi16das8Xue\ncmkm4ysMr8t4dlZHDZmmnn0gOUQ6rbolIhLeBOHDqzDoakuDj7+Hw1K8lilZnOTbfYI5MQEfUIGS\ne3aiAKxZ1Dsg6/PmIJzyeLhH7agdLbQ7gFJRP7cn+qX9owGwzsCKGqCbnnq98E6cgKUuZh1ExkRx\nF0vubdv/m/heKK4lYmBkUowBx0/Ivehi/EMakB4IRRyrssKHwZmQWew717wSlDCvort38rFzAxA/\n/w0aV+OofIsfcZU3OVVqU6mgR16xn5JkcHPlOYi7Rpj3rHgsyXQM8q5P+wWV/78uQ9Bhb2iLLvv0\nPasgHNi7U5IOGFPdMRDR6cWg+GW6d3Ve++byqLESNEzuEo4gGaGQe7JwgD87lowx5Cw6OAOOqvhF\ne0t/H6bbeHWSUl+PJbIcG4BSCpZ2NzlqstYvN5gNLPbw1bvCpPBuOVGEFmwuTqhwVugomV3fXmAV\njSC5SWhEgr0fwTIqPEzfJcNarobCr2WzJy0Zv9BYgKRB0VknAatuELGMlSEO/t1C4yRRZ/dCSHQ0\nnLGsSNP8qCd0QCMH5NFKN+TriQlcUnd7D/bRXd1bk/GlDddbAldQzy0AA61FxnjPA8WLe5GGvjcj\nmP5Jg5rdM9EA9A4CgOihGtC/tN6U/EBHd79+T6nvhC9BPzjKt9Q++eHozRrslwoowcm+wcVdSibX\n3THLpflOzzEAb8UadrVzx+8EEW7W/L689l9dkFOFOR4O2EJ8Z0Xszgu6WC2SALnunePchWl3xvaY\nx97HzPQfKlC68PnszBXnhB8ow8NZsGfZfqESDgJibyXXytytvjkTbtN9DnuHs4my0wh2/xuFy3M2\nK5PWt8P08LsJWrYBcw3Q38JsvqxV6xvmAs1unZ6UbnkOs6xAGgGTsYPqQflvnqvSpUtVyd+m1TSm\nSVel3DevYdXcasCRwzTuE0r9el12JtJPbwDXprz9h8uU1+Z8S2+dS/zhoOrUCAHebQ41DaaQAoNi\n1MUJdNPunTisgh5TNMnHXvyhIdx1p/GJ42+iBxngXB8ua25tmjpwgwAti/GBJQaE13EFrSwd5l/v\n3LSVrUopTa2P9Co7UVc7eq+naAhhc+yEI60UnKOhssU7dfBgHmsn7+QTjIIxm4+DvdsG0jsIxxTY\n2gjZ/sUmSm661FRUteTU+/HN0HXhRxQ5KfVo8r4OnrVvnjVzqYEjUrdYbsV5cgIFBR2+c1i4V5Ah\nFvV1jsRByxmWNsophUVuV9F/oFPIb/rR7Slbe0TJ8/NJ1hswLczVw9KTwaMUjvXhrtxbdw8Q2izO\nqcbLYUEtOXyUWCzzgcFng61S0qZx7qrZebBjrJUeF+7OHJI8wxb+9VizvmO6v3Il78y6pxlQibTy\nFV/Fj4qjoVnNO+eKZlktQ1WUlgrXuIVWW78hhz1jQ7Wc+vzZRoxcd7ni0Qo9k1gA5je+YiorexVq\nnKkjN9+IWtTtdM5GCFkRCqfxhZFYfVabetXnVZe0JqC/YSKkvWGNM0P8OtwtBex6D+yb2oTKZFJr\n4UvZcJF4zy992KHSObDGOFLe6TbM+q84jJDfdR0LCYvkqPjLD2dX0iyMMUKIz0cGhhx+y+aRUmn2\nAmIq+TXL4fOfuX8KzjmmpNyDGupXk4/e65R58DmMtSKXpoOvgl4RWAJBkIXtvtvnd7CgG0rs7Kxc\nEO6wAOCuimIZ/EBsIonnmez6jLLX9o4VnCzDL7ufB0rLkEm1+JVaUpWS0Togyd0pMS8apS7aAOsD\ncAkDEGsoCtisRdBq2vxmOHrqZQkm9VZcKYk1GMoWBg61+n9QqTf2rnAwYX0ptUewxfYun0nfr0Ax\nacLx3mqDHViWEn7jx1Dr2YGGWHUfIBhwC7IXzRaqVdH5rm5zMqmENOmzqwldldoX7akaYHsIHX32\nplXrJz8dHX48A4CzVyrW7moqxdXd0piB3uNbhGBsQFBWBUaL3+uZy2jWig7Wpuhkm9Vieag2/wkN\nAIiPXAoXeumGIY2+jGkUHijq0Gl+VLVEFE5vsTcPiQu19rNnbs7sUeJvFDounp3ckFO9ezQSjasF\n2NaztrjFvbXlt8GJa8aUnuXqJPINk8iLesKx+ek611XbeCfW6H2hiKrNibpJK8W0HMOq852hKpao\nRCjFQ2HO2LigTBw4WUo4lEKrvjg0/tdP3S/JlCkenjhHhFbefwGrtz+YzbR2HSj4ovk+Lo4UhuOk\n14R1UwYU6a+8R1OkPPweGBuFuQPesGf0J886SB+NB4hKiNG//R6VbL+mZELbZ26G/MZBQijsjqXL\nkAWxpf5uX7br0cNtb83YyoD8kh37dyuJQZIR5M9jgrSzcQ4SbgL9TftjTFLDJbxBGCKZIFWk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3dNg1HRaSZw24s1VzDv+TM9RkXcEsDt1f+fNFIrRD0JEVYbnRihOKVc+IgDbpDmJF2MjuuZ6AK\n5PS0xXkMEl7pUqjW6cmQDuGwR6IEgBvP8GNG+Lo0QxhuKOOj4WeRT+7d+FREmk0ul0mVSMKINQOh\npCGudW85Jy8IGhKIFTB2EOBJWZf2bDjaAuAf+XFBXKGMBQBMqfd5ubWmtmxY7v4WbrZfz8tUi8PA\nU1A6paJAttNAZhu2fUeqgv9uGjT0DkECh4x1uoO4+pLRlqhbd98iq2KG1cXhw4XiapswmuZ/Gz79\n8I7I/6e43WOp7pwOMIcqcFKUN/A+hKe5RKjcDO81itLiI9EOzXMjNI19pPllE+DUTFWom2AbmNS8\nndsrxCWURQSaqu0GYqcUEngYphUtdcaRFSteButto94qAKloa/vv4ndseoWaYYFup9UEiyvGYkOg\nnrwgc/dmOJxDP/a8OI/Yvfjx49rqbh5L9t/z6gu2heEnOazrM2gWalzujIKYXoPfAFt7y4O3NZDT\nKVJMXfX5H0NCdq4PpKc40geUnxJ3uM1tJUfSVWqstJjNqb3CxP8lSrSfr4wo/Z3bC7XwV+JCN/Il\nLk7ZCwAj5dNTNIJjRcMARymK60Ke4E/M/Yr2SPu/TVjZq0jbpGb60lPujsSSgAGbdl04DP467w8z\nqfN7nljSqvltu7weqoV63vhniUGtibmkNUfDyBym3+Yh2xYOSFFV6E1vsqplfJApmBZcjxCms1Lm\n6rA90kx/m3ZBY8My87jHCRtTYOQjzBTWpOYwR9mcx6EJX3Ar1p1V5qWVpZGLHPbdt9iUNfR5xprI\nIGLudx941EB0KpkZJ4az5jezLXs2FiMwpd2aKgOvbAT8hYza7MjWUUpyAiuPUDytTiJmF28Fuhdc\ns/QKXg8pOau8mgLLrboakOQWGTCNBnGBGNl3w08DcLgLnV8nyzBFYff0SK9VAOZ/L+M+zV43HQQb\nt+23Ch7SoNRM+wRJBwLaRMT8aMh9eTs/j0dhdZiKFrmsBKwd/5MAixrqnrWBuhIMYYEH2e8Svssz\nZdppsdAqEKy9lcS4zYoFB5jxMqbUhLhWii6QeeccTUSPqLOdjwB+p5q07ECHk6c6I5MWX9dw2TLr\nAg7G3pJYBJtSNIVPWZrtlFMCidB/2njerfLweELc6WVBy4Du2TLWnkxCAnQvyNyT6UTS+W8HbSCM\nTVKjG/IS8k9EPr1ZFJMaKl02CKfD4x59vueDox6bObqNMwoYIgN7y8I2la39vPa66oZkALdysu/W\nPbd0hItkGoRc9GT9g97M0ced86cAB1VrIbFzM2HynMm+onTI4IyPsSr6NmmKFhV9SYVnhJhHSA7T\nRBsF8qVcTbWxz8KwULvjD4EMnnFOOmhoquyOXqfRXJH5SDInjMxMdF3WGS7gvFzws/8SMru5drdk\n7tIMgb9zhs5EZjKfYikfB3qLtvEyseRi+VeoJ2IDl2p3JdVK7IgNWpcA6K8VM9fGlExuc62QcV8h\nd/F9bKGIdV+dvrJ0qoTzkyNU/o/nlSTiXm1j2sWgO1uFJ7hi2KC5a6X/KTElibZY0unnH7mv1Ffv\n3TF38iyxymspuVBLXCiFMMkE72liihcR8KBDJtmBVC0FfAYACYmZUsdKsSDZdwrMe857eKcCFYD3\nKzGy3M+ArC/zu2I5TkJ5JPFRs2q0N4g43iXABz6hmr6WrrP3z0owx+aWXbyrUNOwLbxn0RcTPIwh\nNWpEGPITHdp+bR7sbYCfV27NnNtXpxYkhvlePpgfw2o7KIRUAyd2Wj7Y7sBsjd3UGgVwd3xetaYY\niz+zDpx3expCsB84I/bvPwKzxVuS1t30S1jVvYvWx/obWbjvVO1munsZIJCvRa0wLYlamoBhQQU4\n6rAWbYZ+ByjeolI0p4n1otyzU9T7+hpVI//VsgPPwA3D9Mvz4zBvLNB4xlevgQhe+8MaER2ciZ01\n9M7Itw2Vr1p52i881WAeEUByk16SAYuq9FDeTl9+zWarxDlDD6kdtrSbSnQ+lXwnRXUsPOYd6axe\nvrf6S/if9ERf3nuM92UzU3SbJfDWg75Pqg/Et8lNG3om1ojO1wH52NI6ZWbkyd8SwQ5rdrA19Qom\n8EqTuZX1rHVPvpHG8NgztjukVei4wFyoyUr5D5DHWBeUdewUjNbLJMOsUw4A0cOUcpyzJ8mhaISO\nvGcELfCq4m/aOU+JK0znNTcZWOnxSRULrhSpRIxNsbmgxGRR72pKmP/1NBaUgYp94pJ+KSmm9/5h\nU9vYeK/TuoC9QBmtTinaA4z/JEyrm4C9EpTloPUfw239K3Pr5tJxO6rr9uHtnWnJ2a74OPztbJqv\nbKj/6UsyVYZmwS6jjOPoeO23IStKDabOi3DGIXd2DWtnhKixnN6TMEs4VndSIs7/rpdPo2H5IYKn\nxJaVDVPmQFmPiYMlhn7y6Lpuhd7tqJYW/rBGR4ktjzzIqnD0COUhoOGlNo1SVXpunCYg6KBjm85u\njeBagwJe/o8AkNPxmT65+5jjl7Bq5tkrCFJudBqohpZPlwoBwsbvkL5EW4hmdyIVwrwjkJy2xeIE\nN83ziZlWrni0zBc/K8upHsEznSQI9gUoq/dEUiCaWKTXssiZP0TULHsswmKI4CHtcsY4OpjvFHdP\nxgim25ZHrZEMHAx6mu7wZc7wkLDFahqhPTRGW6Y2vSZL0+VCZrH9npkY3PWJLGp6CG9V0FbwdOV9\nTpSgDsKAJbMkddrP10EycxtmTLjGbQ86TYYno6d/glRONMOJyF+J8FdxtSBxP3qxuuEFqOAWJjgy\neUxDcusgzqQsMzLlZgEkp4RHpo0XtNzKDxd356ztKK7B4/bl+9D4oL08bxaIki+SG2Sfrn8potic\nvYMTfpw/dGE/JJDXTSxKO5wo+hoSW0kZFUWyjDN6FhZS86PYyqM7ZiqITieZmJTDh6Jd4XPcLxMX\nLA5xjDZnd+cs5k8WG3vtAszC0I13kAWac3TViAx6T50efFcYmhWaeVmHLM3vMvjA8ZdK8Ls8yVTC\nFxnVOTgtZzDYsOqPO4A24Vu9Bn3Abe+kpSYHf1s3lDpv84eHNW856ydSlaJgXlxzDxJpUA2nQwBM\nQU9lC8j4bY8CTvngASCxpbUx41zS064kzacuqmfAWKkrEl5x3bBTVBF7pu7IM8RH4NcezYlkWtx8\nZRiIjvjxyFUzJTCQCN9lzVquT1+fN7CkDbUPoObi8OMlAG7HSXBJp4Pi+futlSJjgKd67eR66ugG\nWrXKZSdLgd9WYC7XvHZxZTFhHLVpKBPAb6Fn811hJUb/Kb2QmW1T8ok+E66OpxrDUaPbLrH7iI/g\nei2rp1c/+sqx7S7lm4wDeF0YrE2+exYELYPR++y7k8DO7H8psud86L0AZjCfcG3jAfaFcbUz0z2x\nbzNr5fVDHC8c9Dq4GcZjtPGTppGa4C+L06fzifF4RVe9jOe5XDwJb49sZKvg7vyZoFfNEqAv1ne6\nGWwSFQ/z3ap1Y2yBa87A8/B3dOuxyH8Nq8wFefubTolrYnbRk3uQiOVfpJ48l3xtsqE5LmPrMy8v\nea0laPm0H1zPff83q7onetUOoZUXxTyZlv3ZiROuGAe5Utyk+72prc18td3JjdT3Tb9kt6U6Seqg\nbiCLVKs9bigjtUecG/mCGv2SSrZCGKS8oCG8elnSVwGUEo5YxgAXqw0+GGwiFgFAahBjOBUhtKwS\njRdIwoOuPRh78HBRa+CM0Q+MNmJ5PD8dFNG6mPLkD3p7FkS0ToZ8B6rJqTOynK16ECMkQRHUpecG\nxygy+svulziu1D7urUGCuPzgrkJ+zXntkouO6FQrL9XNpt9btNpbX0BQDvizNdUimwNfrpIDky59\nLI3xwiwcL+75UCKxmFVxWT/ABeoLm1hp08w61EW7P1PKve/jtbThm/N+rNjB8Pn4gNPKazFfUukg\nP8oJdYaYO8E9T6I6Uru17hNQhxfx3QCqwFTuVNTT0wUn3kNcuPOHzoWDaMJXvUkLBFtwAvHT6RZS\nwmi9Jy56OvB7Yn62TTLL4Ywd/qSIATWIBzJ9jLcPOgEcUlswYWf3LD9XKx06rq/Q73Z/62q+layo\nQAQxy0Pe2vY3CcbRF4QbWsSZUm30ltJeFJjDvVsw5uumbvSxD1PIF5nw+lN/ZQurGcEdWULtq3uH\nt9tr0/LvBXLMcuO8gxGFdbou2vCmfIBWvt+ra/6LD8aKiLQPjhf2WtZICEC57ws1vIoVcY2mSWdG\nOqBU4Es4QcCX9/0wYG32LFW8U/kFoiomqwdbYt3Hh4N0BTb0y3j++npPhyUP7jx53iDzoKHe3txQ\nauFt5xvIssXA0+eTjIUTeHj3i7jQ0iFI+WohwPNmvMHRL5f95kYLGcngFBjoMFTHf2X8ABZnM6zg\nV63pgRSCq59gy0PhMDXLnUBafuMw4ytwpJ1YxsRwCh3KY3JCNJSdjfObH9BeReexqS1bOYwukGJu\nE2Y9NDCGC3oyrcKWuviy9eObwywmM6TccNRTr9V0cvWCA8J8ZyBqRPNNHE02AmtcgZkmDzQsMYng\nPOREPGA0X4HDcR27bCNh/7l14hJsxt9jDhDGJPUTYBcdDCsaGgzXAoV8Rsh3Vyp1txb7XW0JVRWl\nnOWXs6M4Q0g9TCNHGYrBujFHVWOM9ZQF3G+9s+1hKJFjvS8p7I+GSNJaJNiwwkSsaNCbu2r0tOsi\nrxn3JwB4pwmtoEW5V1krUeiGOStWalwlatzHdDO9hPRchV7W6iJZQznfVRozQZrx0BXYx1Dg00Kq\nEmoWLQtRdC6uXUmT0x3gPrXvHDAPkYF+DoB1gmomY/d/+kqZRrur6U2fdSvqBJXmF6wEmClKnJTC\ni8UbV0alujEV3kwemFHA2di1YYr3s5NRN/UYUNpVlHZ6F6As36URZQWXY5N1Ln6J4yv9zgysSaC+\n+6jcvxs9fWMqI9TX9MYait29t2ic0ZBvsFqzlAMP/G9prQJ9hvZ2mAdM8pGKkGzUXngeX3d5sSaz\n0jjfDrb0lGjGwMRXISp5hf3nmc704yQJMRmevY0Q2kpbWAHq1pDx60Cn+Ev7g5awoQ5HT+mxCWpX\nC4ngcm8RrQvCjNgpasSXz0LzVg2In2gjMrIo1Dd2UsfzJu5Q6j37BDZTWoU1/M+524BnZcfh2hYs\nYZXEpVY/qJzTwF4rSKzbIDBDhZ7nYALGnLYo4UIKRRMQOXAMxxmZ+FoRdIbwbYFlssWFWizHn5+Y\nNPY+4e/3Y0VUD2KIv/ddyQ/yz6AT90e39aioWgbBFu3rmIaSlzLcRT004AvsGNZF7CyXMnR41VJV\nIKz3IXZ3DoptSvTYtLyQHWd8FBBdA+Rh9crzcAW22IFOTn3/NjxYHneDG4H2BVpkKIMCO+sTw4qe\ndSS5/RSrobxtIfzsQro19J92g9Br9Xa1DTImMOuyzTKor3u1E3+ECq2sRrtcYDSAD538wUq5adFa\ncySpm8KK3wTmX0iReDbCyGbLotsWu4Df8Mssamxjr/AI69BfeESmgE19rJMgMB+fM4mHsbPM2axX\ngGxSkLh6Nm6uL6rrYP4SK19lznJ+RkOX5Hyp5rvbw9DfZugmNrBIwn9VENevJEa9PY1i6aR49CYX\n4AuuK0ZmXkXMIizsZZmyBRbeTJTW3/ZUGkBF1LH7nLdATDWc9K8Qzm4ml1xz9/VZW+mZm0tT+8vq\ndHCuB6jfrkt3HUeV7gy7a0F17NCVLTuFdMm/GqHw6PnJ5EDKkYIarta4hFpR1h6Pkkamt+mI4j7L\nMJbDfk7iZha12Nm+Mq8TVl9Q0ibVCgjAuBOtnpi9gxbFIZBjIxvc37hMxX2tVv05bU+b3gnxCpUQ\nN0ofQlrm5XzWZbm3fhWVvJXoqJLSbLq3kkFyXdWNlqrDniy/JzEoqnfwNQTNNAib9Kez/is4jMK+\nIKJ4kalAYa5xw+eu/yk42g17zvQSSWwsWR6XEdJOUVVU3NUjVEqnivzeyTfow5lNvnF1yX0WqHqj\n8julRnJFxv6bVyb0KOi2sBwykTjeE/d4zXx5W9youTx9K/EyONn+RNujHAR0Ds/MD1BY1R59T7YA\njtNNu7cRpe0G98zURap2vs+UEqlsrpLM66OGnoq3B7I+un4x6Vp6nSlz3oztYNvY4oAsC+IVDria\nvfpAH3LIRiITAZCj9seiOyZ9UeWWb2zewAWkJpJzrwVC2H6QHoKZH7N0SgRqsr4tDia2D0NneTDG\nYffJ+XtDmo1hsSGrd9hZEzpFLsw76ywkoas53gE2GyyZw0QzWzUhhq+5h0ded4khNmKIEtOxEzYK\nux1Zv1m/IIECn7Jmamcc7iq4LDZMomzMX3jbUiGoBMPkGWMmkfZ5pDyW6vYG8JjB6s8sFCHr7kX3\nzQNC4l2Olp0jV/WA8I/bLTIHUDaCtApHi82t1feCr/uS5CZeEAJIgRSCYivSxQJiZh9JPj+wSycZ\nqIjEbl4Ebn4oJao/VcqMHiNAV8g1GiYEruwCZ3VbW38nTuRBBvf/C83HI9OraCj90rrAVa/M0feW\nsEhE0bpSl+fXjtkRh4PI56rodGvUqWbT2p7XpdjuwbucjtxJ9Lp8OVdCPWPcBRpei8ERLVBwBBSG\nPiuKD5VylhhmXjH7to8BSg+5fyIux02JyGnYsLmo39x474+TRwBfi3fJ2j2mlF8QZ7RSElZ2db3T\nd/+fq526ExD7STCAKKC9gCfGJ160DGUir0k+duM4/t/lVdSkek19/KG2nxkzMyUio+U2jlM759l9\nvo1L/mN7/0SoN2QzAB48rt0Zm3/kHLXi57udAkadp2fpjVoTayJ61wxXD0gb3bLxg3nKUMS9G03L\nQ8HOMdHTUCwl67itpadBLDEqjObs9SCxWklNazqPMxmdj4hLJNrDbJ7HxL/D4ctkMREUZ28yQaMY\nUUyTNPpI8Wl3hA3nbnxXpAhzsNAV/lPJtYM13Mm4KqWg6+da32Ll8RYz2iHbmVz+27D0uUGixQYQ\nLojBMZAq5+k+09EgJ1G/J1/P46kPJdImea04SI1abdV9gQCUtdyjHpLIkxwGiXXTzAQUVlD00Ryd\n2+g+lGy3mkbSKf7ithrukeIwolmytbL0pshW/bqQqin0czWBY5QXXQ96RwEudpLa3Gr9EQcSyRM8\nxXzr3hIRy9+MoZKW2JERnUxVXUyyvaWrawxjk2WUCeYG21QVzzE5z/tt1yoFXANiBjTYLo5NfK9n\nRwFpPzHdzjrMAsD67rM7H0lftRduVkBXJf/WC05XpxbNRuPoRoA6KbDIhYY4QOG0NGWrm+ewXbCw\n1b0e1TZzzuwO2alKaDSYO3fkfttAlrRxMZtaYe1+XQgQbpIBX8a9fd6YradbARvr9mc9vaTemF7t\nU/Ts8Xtd9yVRNDxvGCISudkA2hzpvX3HACYEcbkzDvkLnSBHOLup5JZ8Nj0QjApW6pSRl7sebCMc\n9H45kk/p1Uv9BvEWmHyJMteYGjT5x+44Uk4gMx5GX/EN3rQ4BgNoFDCGKB7vddHuoc7NXMdRaIiv\nk7S/6Gf1zvzCgGAHJT1XjEcElkYHE4t4AL6vWE8PlJPa2Y0YUhSfaFPJe5KxDdJXV23XYeAOZhqZ\nGBcjOxyr5yuy26ODLPaWj17it4dmZaRlwNPRUPh3y0EEmvFlcFy0PMjiVH6cYd88zR9llhv/V5jL\nauNiZNTUvgxW1lf56ymiPafDc/46KXrVZtMYHapBkAm2/4k1TJ98M6JjPZibqmKuLsdhgBJGinRE\n7i8BLxFXxgjU1h2cprdlZq0Q+z6jfrZwYUTBRNv+3KTS8M8P/mvPF211uhm9t0lNSAhf1p3QEXV3\nCKK/a5beUKpgxUB7gliS2yD1RSxUr7klpActxJf/4sZTF31ZQBkv7+UvJoGENiOdqGgmZywEVI23\nrvEKVolw4OrLvxdDir6IUiDapqVB8Mit9A+usSvm9THfPARxfpQx3YOpSY207eUM7k1Mgbqtm4jL\npgsl1w2g5Cz4121A1qTtuOu2Ck9xMKtTAtmXlbnSIw3fnMHo5j8H+H4tLZjA4lSmRhz9Xq4KVXYf\nMrB3W/eTiimWI8aH5/9aouub3S0UNc4IteWx1ydcUiHakt203fdEJQlBnka3ijqRCUOdpRlPlbjW\nk2LZ3Gr7IpFBOh+PQH2y9yr3M+aFvcdDNuVhB9kk/fQfncv5O5No1hSMmWUTGqgbVUFrYUGYcyix\nDTJf/4Z1rXA8/9fbDEyKIZX2gMP6P/j+zV+D3oVUXaa0Qm/OyFKdOJjDZ5sfjBA3PMhBZyp+cMSt\niUSAYinduurUIW22ewAUOwD6716jT8QnJ1OxhtRdaynRPpGma9yHVK/HplM4pumx8sX1oeRvcfef\noI1dPU1x1mHcuKjg7vA5LjOuRE4+SUh7DoBZO/Ap5Nx1/sJqjTufAqHuAMymOu7ZlJt94KMdkQM7\nOMhv/rdQQxXgndDyua5ViHquIwr0oRiT+iBNP+oDQ3h+lkNlfuTlbef31ZtJC4cKxKxwCjG7m2J9\nDKqMokpCDJ08zy3gX7mWbPojQNpv4lurIMEvLCU+1+1lyi5kn+i0abqFoLagZjzr26JUt4e0w9sA\n6l0ynFUsn2WFwC2aC2OOIhJSQQxxR2wBVGKShlg/lX53YdoEmxI+qWg2lIWW9AbfOQtySlkdZ+/I\n+3vNTW+xNIUJT7ufOUuQgjEAPEXlhs7DwTZarmh1Dw1pC6ZMIK6MPFMg7Qw+t2udyT+C3ApFsbse\njHOOPHTzMxAJKzSa+U7UyY6t+ICGBozMbWG3aerak0FlIbFHPu6yeGnVGt7/kPEYY55wlsps1dBk\nfYMmI5HD5tvQJvvvS9UlDGKw1eZ1cUsgnShIW9MRrEmPiUoCSm6o2qMstB4sKxuUR5xU+F7jbgvA\nTC1yjEI6wMYShufROJYAOmZMPbDX1qjj7rz4W6iKOEiYnJRhTmCfopMgdh0gEAWcbtXH6GiRcvtY\nhBMDxJnwNzlzKGoOpNoQ6m4RqmXoHsxjpeDaVmG2uULTsESew68SE/s17Px5ONLhpPSdUktwqS7R\nYYvdoQk6O+MmQdXq/n6qUlbopfw0FVsDm/8V4/fKnwwKV6ArpnvLxMuDJdX7rftjFP9MYC3EucOR\nrkx1sKk2kxVS7NRx+ogglmzT38WoMW0MYMdPhO0uKA6Q9RwRSM4Bdpw6a46omNjPMh1AUNhB7fv3\nK3hVahKSKZUMnVpoa2vKFFLGxq8jltidOftde5Rlnum0hbhpMLUfRTVqnJVCkdhM2/yhR4zFVbAW\n9ymmhB8XsMkRbwU4fEuy1llAHFQEtcxKI+/kci8v8WsuIGuuo+GpfnVMon/wz9k7kkVyD+zoiHRF\n/MBWghC1YJub4PaIMldPDmLOrBakqIWizthL6QZ/U/6UZiHitYuz/aD19pimxQTjnLVDedn5aM3W\ni1yEutEENmRnIPAtOZ7FGjqc6zbVBgbrVw1dKRrV/8dM4FhbudYzQbQ8bx24XVaTvJlSap61iaSO\nmf8xzyi4sjLOUlWYkkodd1HReJi1Z0mxurCiDtUmbhHuu30+ed9nVMEGhpct5vqDlmCyQnEd9ZeW\nCZRq6xa3c76pEKAUpbOL5do3ZV9csm6smXOoWXl7PM6/vyjcSTXxfksxIvhVqew0Y6Mrq99mU5L4\nnS1IcwLN0SCDMNUU9a86C4XNYJg8X2Xv6M61hjZOSi+zXEBHkWw2XhQnZjzZ8IyRHM/MkX99Qwnv\n1gzfC3Yzl/cbGGwx5G0ccquS+AnvI1dVFJjd+HwdI7sCm154xKjZAI6X5raH8WiRIt+czbB9FpZM\nydTLBx5YQINQKnqoWvypLwsz2IUuW3SQUvop3d7j6pYIMUzhTzVG6Cybc2NBmSyTjLxONBxotPbF\niwwTmeMUoBgfqr844MN+s5N72aXdIPScXeeZliYS/aANbPkHfKnczZuZ222tWdrFZPl2PXphKLgx\nZrXaeNDyvXipwFt+jRcojrFoxm4Hw0irpQJIynoGrjwAHGxdJm5ee6acANWcUid1wR5XhAV5J652\nRHd/J1Hwp3MF0ZGb6bzCVHLxvPU3LZmveSf1q19XGvOpCulR90x5fTol3H+hwQR6Ho+Si15dNovj\nPAGAOD/KYyvIgE58/2e2lmrzMdo9XzkxqBEXRilgg6+DLwvrdP2yDl/6KvxYT3YaWv3WWRQCiIrb\nZ7sggbf4P67DIJ/LrMTjxocKidaEKw8qzt9T6CLCn5h9JjrK1gERufV8NCnj9amSpJGwU2K7AM5u\nh87UKR6C6p/Jh8L7r79XdnDNUOfmMk0wP516O/U6Q/oyBtvqPzxGzNB1FsvpeOihwYasWj+fGLMY\nFGFNzD+13tSLcmvglBXJ1ChC6Uith/azf0utRE01E8lULUl1wN+8VRBggMxPnPqOAeoLgfnX9OK6\nB/gPHvHyxasMo+z0oo7JDEdfOtXQPdbAXInYCcKmPMxd5oLL9lBq4y48sMj0nhBl8uu2KvOIvsDp\nbRizLcl0aNazChfYMiUchoB7vygFoIP+d9kqZRL/INMMqJ7GpEQeiak27DfPf2UgDetRzpCAkIZC\n/N3j/E8Ls09rDV1RcNSafKpqeBm5fghFI2Bx9A/5/w2Zfy3sRE+VUBP1KQQToKofT6SLMIjz28B6\nk8eufJl4UjbRYtKPzglJn16gQvoyHiMJxExfXAVtrI7+0c1jLzs3qaHs6Ee2M022y6YzJ+oUCBBK\nTkMy4fOoMzk6msoFsuPeaVme6ZLWyNKPHbyntkEjs8vM6BFUpH1ul6vxC+PqSMc4S2VXXUNARiyf\nXXpj0Xz9FvQOXJWatu1dRNjDRfU1h7kJssAyVZqRinGyvcHWXrnha1x+s6Pt3FlV7BOVAGjnBV1Q\nLHHwW19dR/HbZIpzDufnV5vbeZpCOqS4C57zY+rjrLBk0p7LdHiBOnTX6xyKIfvuzmn6vpoLC9gr\ntC14LGFd92+xcPhOCjor1SISx44rCFMGcCnRSqnP2DZnro7YpW74OgGekI6G9gWzSVBsUFpZx9Wy\nbAGs/rwXysjyhy7TWQjT7cM1ecB8IzvPopbR8cfOp15G3VxBiyiYwimqRt/vmgdHkncaCbgIEVsl\neog1yL0/XZKYzMRj5hTi0J0QGBBH8nq0ys9ihzk0XlN77kP0e9ktHaLZ87jum002P2BBeOAucU4/\nGoULRZHI3s44dFjEFuANrMGgk03VHhilw/6jw/4MP5guhrq77uV6rVxdUpwElLTjQf3c6pAOa8tG\nnN1zpA7vyR8jVZkkU6Ld6spP6ivdbzLPLjc3ctLQXcRuGw9rIyGTKUMRYFQBf4YPCHYTfvrWwxes\nHxiUYqv5vI3ASVpDdBqIIhPAMyRrBiwhu/nsU2RR7rx6h/PRdvsulQOuMzqf5Dvi3iOwNUsB8Nh5\n8HEj5KKZQ8T2bcXtDiLX4hZR9d9xJhb6Nkbv0SgmIyi1wL+e5FJZ2TrIGnnsFw/LYjpthBB6JjaA\nYiLjhRtLzbJtNlhi2NKpQlP2hD4MNvEI6G24mKALN9R6v4UqcCdRFmwjcAY0mEVrIdBQFBh1lCQq\nPM/pbfUmkZF3dcBOcR/BUAi9tUiwXnNLW5Zuyeo0aS0gmIxXQ5v7M1RWiZzjBZ1wmbx0wRq4TuS7\np8qfXnuA+r/msugDwfUkti7vw8jQnxEPdZvvnCcYrI7/c8qcN1O96A2cPS2U7fER2tEKbEo79cfg\nH1KMwATBdsIp9vYb6OL2IP2EkwfSHbKc0mRgnoRFB4pGWdoZAT/ak5SgdzGmIs5w8ZKGWzTkUfF2\noMlTrw9Y1JhVw3bkOz0VidW+0RNqZP8Z7akQM7CNdKP39lQXCpJ4f83JWWQrlbS1XotjNYPPqB3l\nCkGjVpO8C5wjo4qt8aW7TzYDtBtrvOayrLkzYffCVgzcg1efXX6taSDi636sLTVDwiR62ZG2gciR\nf4hc6q4wV2uBsWqk/gSe2rnSk1RO0nBSQMcwsqGbwQajKj2wTmaAj3pSE3KW3kQZhZdZ55yJpmXk\ngkPLWCThOeiVta3BXetPsesHr91HGWBC8gdt3y9S/qrE8ZZq1Q0FiIGStAhcuTUz29oKAiKurtRQ\nj6dfWdCphb8ut/P9SyCYpsJ4P7CrTXuKLaPSgxxLvhi0kzY8Vp+HLJ4kLxEK+1ctcvKUhaoe4wf4\n+ET/yZm5JhTS6zk/+7eEEoXrui4UXsNwd5Uhr+hiW+VESBdDELek5MWTZ7NykXT9cM5pcXckZSt8\nAgVLbsBqcg2K2e/Mxtk/1ZKjv8ZWW5WhZpQeyaR+KYCcbOOXlMPSGFaVUGjpHZ2VWIqcDRxef4tm\nSE0bKusPi6kDHDl4jwFBvIBUWjza2htdvdUt9T3AM4NkhtEh8yL/LtRAziqAlpulQwjNK6Dwu82A\nZLF4BxBvYmV+lYJ2H54lOxJureiQU97R9uYbzzy0ExjnzrvBVRR2XWBaFgaqmMDicPmcVBCic7e8\nTiX1Tq4l6RRyA8Ny97T+/RAY5xem06RQGBM/lZlGH3ytBdsQBBI3CMT95+JmCnwnUP8rmHkVahJQ\nu9PAcr4osTpofkVCmoaCIEzZvkUxTwKG2DFy9yCl3BZZQ6lgyrd23anj4eJbwKMtnlMI8d2IBFsG\nAkmoADWiwumAm13YFyOXIbG6xt+H+TZXzWefZ/97NObABoamZKk5EsvbXMkY/TpEzsULMkEXc7Cy\nY5RSsYnfG0xdPsVDz8Y2nVhga/brtnYsADcY2zWObCMbcMnoOoSr4i46nZCMUshfe92PmW6n0yRM\nEIE4u5ieX9QqWlpomAnXUX6Wjs06DMTCbnvp2YZSKtMW1KgfN44cWMROC3jNcT4mZU96G1hXSwbi\n2TSeMJ/Au1CZJkjLMaO0ivhOdgDb184IFCgSyr9Z36fvVk7+wkjxGz73XpF0RHrhzMv6p9k6psWQ\n4xaPsztWsiDlpwLltnBfNn7NPqWI/PWTifadxSO7DS2Tn3icIn4V+GhN/lqghhRvbDH/gRFfpQbC\nQbgVjmCTsD6Xt26OFJHY+kQ6RlgYsTIosPSj8m0e6Ow7bW9MbtOZT0OW21VAdM5ct8dHeDxmsDDZ\n+wMoUC5qYAeYjjj42fNJPFwHPo+4J+B8ThRCoLXjGshKU6GUXTVMGfFozPAAVeNsjh1XqFnFEWKk\nT8tacNR3HxPWYqQ8cfTEKx2kJG3Bq9WY7wqu4UCPt04AaifHQCvxk04uSk6N0mKIG4rEchruHK6t\nV9qNmfeR0m84kuZAp8lzh14WxmelTKVR46TQ6422+czrDeQywzfrTNjS0R35S2yv6nYRsfhUWR2o\nLJKgR7um1MTchkdgigMmcDShsadmp3eIO2NrY/wntyT5fAnh1ckENH/XgeLXclZbi/f5uujrwuGQ\nUaIif00qNEIy+hhXNE1qDufs5z9PiDgYK7Dj0wDUC5uOPMAyiPGMLmiqQVCna8lReYpPIjUlBT8N\nbA7Ja3O9lBRQIKklVj9ogRL6eFvyKXOLvHcmZ6AwdAxezxg934dRTF6eKrglQpmbjIssnnM6RdHP\nNehWmgIwDPZ9JrTK+ghRqOcfa/Igyh+yXVKB0YDwxQQgK8s+obeNKwCkmWIaM5wJZEDJ0Qq0KZkQ\nq8HaSbewB/GCoueREo3wdZk6yxrrtXDWRslp8P4kvqC/dVUDZhdIabGL54t8rNO7L59SBIqgIun1\nr0F96wlerJ/L785otgrmoKKsRuZpP+z/1zAIsGLtDMCQMurVx6o9xN5fFrvEPI1jDwt78dVPukQN\nfEITiU2J2vHhjbU91juiDNjXbhFAIC4rlsmXs+1vgl7YEvKMZSXC783tgOFUbhyZ2rpzfTvKrxuU\nywc6ljHc8RI8im0S8KPfvHxIxSVmV5jXvES9F1SPZWAYcxp4IEfUKNJsG4wUtAQIHoxydPZ09RrU\nbDWcl/5Bg/wgNMf+qKIrVFI+ob3u8BnbsOcRVdwtcNB2hwU/z739v6vSZ0136u7Noim+MEESC261\nx0pe/DpFRvFewi3DlaPjDY667WTUbO3ZH2noWE2kZzgt3g4nA64c0M4uFe0sZoZsjs7PGKEePZ2r\nKwZRnVDSFxDWRmgsrqWkttS4w2VPX8NePlhQHClQXG31ch6dLXegOtCYv3FFKTEQ+kJ4Frk1I5vj\ngjfdlhaOs5hrux569pn0ygotKRT1O/fDMUFZyXON2gcJkZWFmLzklIpu+cosewze03mhSNCwmvtL\nSX9pvcuzETGccIZUKEuyPxSvgawDV6iRUSMo0Uqs6kyF+yNM5QmJhZ8AQzs9FrwLJmH9zqjmFwkZ\nRfbMVBRy7b45jrGOhjFev2d7IKLCymMu8rmatjinJzzxrmVegf5bCUUJeoRSglGw609kOV2veMX3\nN1qdZUP9bbIzN2Mhij55ESaGdZdx+unXD7/TgS4N685Q4OgBM38r+GabLt2D/EIPX/Wt5Oaa3iFc\nNGob/s5vwei/cdQIIJm81rvnxAtutStzdX2DYwUrXmR2d9E1InflKdJCdIfQ9C1tnp6tjGWENpKs\nbkGZWTqx+bWLqGPHUJtJcMpxP3Ot4Fy2uC7dPVgmxTGgZ3J8lsohCtCkBL/QUVvADzkmXufWK+aj\n0VtzaqT4a8PSMyjNHe8vlxRuXoS4ZXJrAF+DovMSjHFyNpVyXRB7D2aLw1xQhyzovRZ/7An694oV\nSNn4QjvXk5HMUhV76nFaK590csZ0fhYHxxLuRnwaycBaboNRtv7WBhSQMIww1tFuzO8PIWcKsvow\nDdMRAjKx3Tys++hKm7PA5bT6uULz5eu1/2rbEoFz3WjjCVFqCWzdUgrs34rC91uFNfYlePrsThEk\nfH4TRZtusbUXGCV9JdaA0G97HRTP/FvGXu2QxM2PAkAoWolnWZubo/KXtNkzPq11gEdVoU/DrELb\noTby0ybT+PI70yinfhVMJPVWOFNK6f8BCLGo5iqzyKmESj2N4nWi3yU0F2ycrP7hLGdnZr08vgH8\nMr/qPyrTcAQPrKVJ76HKwlu0mYAz/J2tfTUmR77sBxqw52GZY/yAf9GAJyahNNK/v6y3fMXTSMQS\noDwF1sZwoYlUw5XMv3ItmvYwpg82O1VS48FXanE/FmUCIT2fbYFggo0j2pE9zQSpDdARVAsJ9+Sp\nwM3lKelqMxWCocBL6cV8H5zLcC5fY36OE5SHK8CndqKjoTuMRsZPiV6inmXw4ZjA+JPn5sr1Vxak\nbaUxrpR+QWOg4XNy5zwiW3CIm0ag9Cld6tcoZ/WjS6Yxwt/qCQ763dcJcEUgjSvSYsGqmvJMazfr\nX2Q6VXcdv7BdLZ8Hv/fP6IXhtksEZ3wg/L7Be7+dz80ppiCLZMsGnVhFIpBJvQYiQhuKbF20ipFc\nKpl8rXjjNXEF2617XjaBzLN3RO5fkfyu6B/wuUrpE1V6qabnBeVY/aUBq4uRC4EZa/xFPik+iCRG\nOGmEGj/MrgN4dOJRbdOzhg6NsNQdn4TsxXjx+647q/FhsbWJIq1OQfkpdqEuXD4U7Qu5TAyjseDL\nmdQiAjntQWidwxL/xXylarrC61yYeSShINlYc356wMVRI2DHtVLlsY6H/5I1M/hMmoObRAmivxf3\nD5CV1GiyiaYCkbQLC44mhpvbbdKbtEYvSmKyX/ryc0buaN6R3G8JdVjxIDh01yY+dpkaO+T4WzdE\nFmUswe2ZE2SafOnmpT0CIRt2e9amdhLv4LfPXRScnb8ft2dkauOxKKT8zqxJgbFa9hM020+Pgbua\nvteqnlY4WoACfihnDfm01TBZZWFOAoghjaAKDAFhIFUR1SXS9+T1B4Gqa8cVatjLDfLksAKFuMz4\nvo4uZJARXMZmrLKdDfHdrb2iCkw2OhW4pSmkSin0gbaWTwtOXFBKVVMByYDkC54zvaVlOoNNhL3t\ninYEm5wg7mDx3Ix6dl/iW1X4wn/y5iSKoyvFKyrVtAZ5++b4T6aedoRpTjU2hRIgQi1YviM4zY2W\nA8Q/gTOLsEzSJCbJB3lisZMFO8r5UQBMR/0rTuyGZMNJ+Zxgc4qG0I6cU+htSDqfdy3Y6elw2SAm\n6KzQGn8deRJQX2cR6UOdofxlQo9drJXYET/rXElQy5HALUn0eLeHKtRUzgo6U+ubzS9bUr1eMqLy\nNU40dyJF+IL4InjOLPMFmUS2IbUkaZDvtPhSvn7IfWts29VTVxH6ulnBUraRv62zfjhNEb7e8aK0\n/ddjarRVuFjqGUPnjBTYCXdDZi5VC6fo1a02gYKuYeU1lJkMAUZzSzQT9B28eHeTOBHxIHGUdGio\nP0EgAdxZK/S7CNiRhpHRB0tZkGG+LWz87YNtOXtUkIpe/3hhSzVmDh0iXrucIT6WvHamW9Y5jvtQ\nKV0abIfX/HIV0cqjG4iCCeBiiHc3dWsEqRLOR8s+J9/S9lgYnQnmt16t1iYb7/wBgQ3/8NCwg8s+\nGf1i+tuSR5vdIzXqfDb1fglA5uOwGiSvocMg8gQZYO8737QnCoycjCtTXLwcxGwH8eLkYO2x4dIr\n5rRfga2Wo3568XzyacITtJW/eVWk0IxCBiImaDe9lyK3ZU3GhKrbEGKX8y1uAGMH9uuwsPklOEmB\nbaDsoehKRGTdqD+V4//v3HZKcMqaQe4JLCrm1W0dJfM9gpbPiX426FkhMoFHrFsB8gAxjPWb9PZU\nQMCW5nSmr7qr2c4hNKtPA9Xbf8Vj52aBkY5OB0/cn8o8xrAA3BcUdbBiWjQ+Bs5DQYUw0tcGjSB6\nVbcPpBClkdMweOc647ynp0Awft13C7dnetDPT8xaG4HPklo+DBUCMcUslz1e6vH5JItQ0lIabQLB\nDMG406e+QKlKgWUNnTTTfgRw7SOlH8txynxee9utlnd7wQ8b9t0/z4F+zr5wBDvOUYUIAJiYYmr9\nmRu7I1G8Q8qGDAQ82eLtGW8JDjpLYp5LYxpGFH6IvlVYizIZ4IwtZ7LMkdSyu8Xe1V/4x++S2xKP\njQ9ujEudRqmEd1CbTdhYuUR6Q8/POSGLjbDj37hgCnu0ZXj1NCMMve2/mASxsH3s39AtACJjkkjI\nu7JHrEdZaa7LJeK+5JwuQxdZpvSOtH3fDgCQmWgJ9lbS3I2WfyrKK3SyVOsZU+O4rgfC4nVoFqAU\n5FYSoILjunuyQfNtVwkFhp44g04LHJrCDCYSZMnuuLlOiFDiP+trQ1jRLU86G2JEOQdICMslhViw\nuJ0irsLMNoLqlWGmIVPC4e/sKLV7HUCrMu+KDGrWjim9cp7u43yevOIN6/mDdisL8nzC6cRm2wt4\nAYcapHNB5k0U6ObddlaAByEYrLV0gyqFxHFZ+dIPI8GRq2G1v/aY/dYM8y6JFqa+Se4IrL7Cdkrq\nQ3YFtwncikJ6sfekz4+zHYysnA3R1vz5NPl3n58VvehNbBQ2aXTvZuvL3T559JFyeFGeKhxvlflM\nTljoPTevIpBGfW7Szu82hn4WuQTLgHUjFzxaXWghEfVRIZWRbdI6B6rU2YCbXiX6wRW/+iOs1lQS\n9YCHqUDTlSed10xjxQaizJAgtQG2rKN5ADLASztRAh3KF6bRPMIKp9SmylpQ/fjNblpnQMcUara4\nvQwDNX6mrYtXgujlMOuhBRznO48tAlCsxa7LeYIzo9k7tt1Mx3ndy6H271CldY36mm8l/Df6AKrQ\nhsznWZk6yZcHephA0vaF6hukxw8sD48xVAzF5mFDoZhnEVrkHRz8A0b77sbq6IAUUZoihqPDEg9u\ngMrplXsm94easb8odcysfLsRo7g4mEonT4D9RwqnQrXt9ysiJ/ftWZchs4XNBXgwxz9YfttlqTG7\nYe9pJYp4BPr2G3fu4ruZYswQPHg9RNaLomeE2tiNsQg989cQKz/uERR0BE6Yo3Lyp6cHUbKcQTfQ\nQiko3kgFY6Cx+815T6JsE1g1KN2CInNsCfI1lvwWB7/hne2knmm9WD8LmePzmbyr6rHYjZPz7AJM\n4k2NY5NDX+4+8CcE0vvacB3FrLj91I6PphHlFjqfzcxUXKUW0wt/FX2mjE6gCMOCReuq5p5mUmfC\nEeySycR6AydYxbIAplLuyGeciUpIyjcbI2pm/tW7rfiZDS1IbZa3gpDAdZpGqTHRJLA8kAbacCuv\nMr2mXcYXWZOCVGijeKscpRwVQXSxHSecMrehWtmI2CyimiYftX8ZutDjBZbOrjr1nhkRsux2RUh0\npWQ3i4W8GZhocFGc3GpqX+RROgS0eIgU7vqhEyoPe3JA00MDmWKl+ZhU/ryBmmeM8Ds70T3CjptT\nKXjFhHrTyggkJjGje+ZQyv5pP2eWSZyMRRgZjAKqaw+tVeraxozc91YCxDYhfKKRMKwbSOfg1NKr\nedDAJh3RJsyPoIWljwlYWWgBa7SN8vSVKCTfjWyW53DNjBr9foywBaJukH8KqTlzlzMzDAemdfWA\nye0fPdO5Oi/hxoIyMFMEdBbSwfYJq96ks0oMrqNhkXUbYEEHYU8+kMweTxFRB0wwpIDPeXimFXNQ\nsgo86ZsPk8ATgqhoXCCVkwXIZ7ZJzQCIEqYbbAeWTy7NRuwa7x3onxtoBwifFyLaW39KM5tsCGQ2\n8AvsFW/EEIDMJbwl0BF6nmBPLx2AVCOMPwhO0Fq8kruQYckcHfPhqVlHR8PtB5/gIyXiFfQ6S2pw\nYssYlicQa1Vd2/3NwbNx6tsXRGlt0UeMdFenc7XSdH8JfI5i1mJ92EuKs/6cw1RHGp3R87MEoC/K\nsMPNJYYP8buKAcl3pFAFzdPNmlTGAE4h0CDtOl6NkXJpHUKG8Vic0PHwnS0vsNNPpl8OF8JqYjPc\n1yAFQEDd3qWrViu8OwhnuFsMQhpDpg58kg5fUI0UsakuNDFWxxhgUm+sXgEB/2C4zySSLeG9KMNo\nNz5ign8gDh66L13JCOBVwQvGLpF7h+jWl1bKv1rlKd1mNEzqMP2PrUHJbneDRHvH/x0jrsdlyrUz\nVVbAQG+pRYclja9/4KpR7CZO8ViWy7QWSciRR6Uatoqm+RS4TMfFdk/MecWCcX9IrzL74FujuZ4p\nv2Q1ik8VixTSKngzymezs4qGYUr7PdwGDGZQGa7axmj285L1/pEJE8j+uys4wSfiMsK+JwPxoXLD\n/PiIdmBhmmpPpHk9Blr2fw5RV3g+OJC/ZGUqSzkiKMJfEIizDj0pyqUNhGtDpWZza7aYmu9qXrN+\nSQyKKEOjmuFwbTTai8JweyQGBJB388CBMHpqEV1oQp7ymaOXdSpN43QFWnBg2kRe+pwukApRxT7d\nCCrfvUya0REF2Ff9qLvKFRHmd20wuI5BTu0LmueOCIUFhe3hEIKVEauycHEeup6RmTnuHqi7ItZq\nO+EJUfiFZTEokEYWYHBMZjn5WgxXWKZJvPGtdqRcJqj8pFELYLoYvJ2bmA+MDmklz5fu3/aTjZA8\nu/6Oz1JazktNOjyL99tkKQnH/3/v2j5kbEVHfV4JubG+OEzf03qhB5wvztzNMRRWFWNLgLW4ec//\nI8ks4J9GyRsi/nwnZbT2cUYc0isXR8hs42++/9tHw4S7WA0ORXqRLM4APZtjPKo/uKYx3yls2usF\npxKPBOIVy8I3Ab3ZqAbrBQeSSrZ/Y+ioZMcsDZQGs2xab9r7TTTAxUj17zFOXw3GXnT2c7M83Gxw\nSnPEt27Vd5LS/CXygfwAjELs0NxyzuoQdkueBoO4twz8XpOxI0X8awQo09ikq2p2aUamVCLZLHGE\nDGSC7Wpcxj3mGYEnP8cDiTbJLDl1Pkor2CqNyW4aHNAeyHh/3ZJi8vPcamGPt2lYumXUZ01Rb3hV\nFJiGd+PZfO5PWDrGmRDe9uuYPyCwWeGXrzBHqreXm1bL+N9Ke8DNTQd4H6rPub2UKnScoc5xmAGr\nkHwDTRtV9sYNl0QGQLFr0CDFJLR/pWB2gRYT/4Wytf925BvdnIy3dH5k5K90G9E88YHu/dc27qow\nJNUkop6mCQnpwOdJdtr0d/D0vIOGu6apynP+Pp8HWrUDd4onSfwLvlZ6dIX3ihf0zz2pA0KQ30/M\naWjcN1cEillzlpLsgrjFwg3kIsHTWn/UZgqhpVCAMQGVrFLohIgfH4uPFQbO3ilbBMiM3bGGIED0\nDh0J/1z8+6SBNKkBubOW6lPazdrkWXj5/1dDEF+CigWMtEkjmLLQqMWh0dTef9tKIXIEbjICNcT+\n19Y8+3lXhsLJKOstL/pe+RbAQhdbiTFux3luDX+5zSpRBxdvEBC/Zenr/Dwh2exHgt1kcWjcHy3G\n/rVRlOq7KBMjAsLFyisdQljNiz0aDOJ1bN6Zs2FEv4udjIGVRivbY8bEB3Kgl9puqUTrwrJEBw7G\ngyHDjy3XlQoeeuQnZabL1IYig7shYFs5N2n/11JchG37EyvMm6B1yB+0NdMc5vlNoZ0c1IdTbOBc\nVJKxNCHSG0R7JvTu0v8GuemxDwEryO5pYxW9l89xgbjXIwMdPF8EJ4xHjkQM6RQ86RAlkZLtZLxV\ncZ1+USWlxFQRFOSUlt9ydFhj4Rl43r4C3zGLOiP//f0gw0qQAHeiwNka2/FQSqTi+nbA2J5oUzSM\nX/0jgMy/IEOLtqyfk8TBa/agSgY4oC7wMHM4mE51++vWN1E4KB28Oj9ywOXX10GhstWCJSkNbNAf\nZwxuYiaR8ke7Eg5A4hYEkY2CdYTNJ6Q61ysOvU718QxjOTud6thc93haEtqkcLDfjMb3n4+339KO\nLLIi6cH0ElxcgOX4/LisI8Wa2w5r5u3D0vZGkcwVrPCi5JbKxCOZyeGh12CUd+V/nrTtAanpTgoC\njcvP6bVF+Qa4cXPMALhcu7Llhqn6LC2pfVDNyPlYrc/5u9VSC/eksWW33zowAQnG2iiUC4iQxuYc\ntVzDJ2B4FxD0UQVk4ZIBfvWmUPInEab5nTRqlodWGpMndJ/PiTO6DaRROR/Do1RBXLJ3+N1bELu/\nmmjPn89XlyI7gLtkhkWCL+lV6PEr7qmNcAS7JRfvBWKiX2SgUWn5Z4taKbU4iw+fFgmVIW+RpYeP\nEherNU215MPZWnvP5wJWrKPNe6xV/HFf+lLuvJYn1Y2n0sD/OL9uCnKYTL9gpWZQi6mlHFTLTG1U\n37ewu849D6eiFZGnESorVhqZ85FWNy106ZK6sOK4eVhzb3D7FvQbD/B5iYHXfJeJo3pUzOJAyBda\nZNVBzjYNqFHPCKF/WhS6b4WfLhEwPYst7vRon3Pbv9jURUquxR3s2B1yXcKgjfJ6FDprEVUwIVaj\n602Q/m2DDdBdWbEg2S5ERM0RUi/jkghj/ajeIz+oLjllOGHpLCFJG3mxISjAUVv31e7QPseZNN8N\n9RQfhyRPX1ihdjl3/LhGHXfqQUsiZY82BXYcapWMUaE6cI9nCGI8TugoA5yM1bbCf172VQat63co\nMrrarDtcEAqjbxvKkfY//E7gfNqwQWKKJKOUfG0S5/qJU7GRR/XlnntFY8IAJGvVXJloUPtQOT/b\nhlFAAopReZQHfzyaJ8bPGZwwgc6/tnukububtEwEfh8iyLbQTc3Q9ByWGjIHnEzU6shbH1eI6EoV\ndLkmL0cSdCn9UuzgFvTvWhqiu0CUNgeFffBMLEUU1QT/uo0UcrIK13aUXxmTud47FHYQdLbjNStw\nRpOmzEFgOn9x9tjgEXIjPdQgVgfvUiJ9daJx2RiUqySYzmbatwMdjkm24rSNHehFzeQ7QDoeBMyK\n3AzlP3PfeXjk09bc9tCcwU10bvyRWnJld282SzqLfu4LeA0EqqeB+lTNAufHdoB3un1hh14MROx3\nHi03IISJ94LA1TQ6J+3BmTt2uVILNi3NXsZjPOYbgdOxTp+LoS5mJlbaPdeMCgMoCYGalckXCaZ9\nsHbicEUnXmRywf21pum9ykeco4yZqUYaVETdw27XFOdQGVz9hXM5M/dN4/5jClKGpVDfaCnMw0r9\n5gAf90CZwWktU2KIFjRn3MA4zP7YgaBHJWv+meQow0H8wClrmhsmgRXqlQjQSY38g78UJPURo2nX\n4zr+33UAjUEvGmRPlmCuFrXRPAmA/SKAT+EAUMi8iDXIf+fzZvl/GNRPR3ZtCF47x0De49XCtWXa\nDGBFA7MnI1sKU8pAHZC4oOCR9I7Mf/rU4c+y+3qzGmK4xPnyEESjPe6WFwOAuik9RtX4X/AUT6EV\nGwjOCe5x1MmMzB1Z2nrRBWeBP9OamP7CgWtoZhzCUjLpoYTdaTcki82lBl+7/UFYg6Yq4TsUeZ5F\nE2+9m8WEyyxJXjYFdvFWaPuEgXKRv7M3C0WDfzOZqW1XA/t7gbN+6BPUZp/JicINHpGKdOC6jc7h\nye1CUzvgDo4kFJCg4VXFMqjyS52GMYr+9cIde7nxSQ6ZzsJOA55AWAujeDFQsnpPj6uuGFUj1rNX\ni77c8LLKRgahOoQgnQUK69ctzC7jQ0ostv+jwFn5SrxVI7rl7SmHKlCX67R7oAMB7y6PxsKlAzPJ\nw49L1qm7DMPbgMAop+j5yGLL6xtx1K8nT9L+tqyTO5JbIKyzvFEYPNVLXibJjElLq9+E10ohTdCi\nNqMJ7hI62YT6EElnea92oPqe1WLlrfr5DROZP5PLQGtO1WfHO4byI6xq0L1WOLr+U2Up1wSSSHKT\nwrlahSD2XVWR26KMwBu5ZyIMFDAV6vyRQWaOi2aXEnqWEfHPZR67DlPgttFQdXcYaKdea4VV6wlb\nEA2H9ZGVIgyNmcAAnxBXNsCoswEOFDarYNjX6XJy6MeCjX4U3D6uE7202orf7sZAZ1vpD/p0jsaU\nPaxlxIR/Z2wayKyX1+iyv+db/hQc741I10W5tdOE6wzz6k/zb1gSOUIKhwTlh0Un7j3u8MUA+QmA\n6qmUpew+pmYyQ3R1t5XRcIN15yrwg+ZhiMYV7z6BFMl0FBocRceOG4mW+Q852kNLwW1i+JS8PhQb\n8LJlaWGRcIBpdd0lhxSdrdaI5srHFEUpaIRakOY/zSVqcZfu3+lDAqOQiraUpn38FVXp+GgxY/NJ\nDRuSUvlsKjfAgN5wcMCvFMP00VH+0KbIzsrOXIPFrZRA1DLHKQ2HXz+jcJn7P5JssmAoEEDCLIpW\ne+ve4Hp7x2blognoZ9OZi8MOcp/azCE/bl2gu/f5cAA7M5k2L1NDOv4aZQoeaMUZh5NKoLNz7xW3\nYvOJYth7n6RKPd8BUW+X+YVDxRnLlhL5drOP7Hg2svOcTbe0F27N6ujM9zdSYAg05OLWJ/3QtXXW\n6YO6v+FQ3kE/agjZ2Ej/weBwVD+vUHYkucesyq9BIE970NR8RpF9/Aac7/Da8Kyb+Lj9Qz7A1LlK\nFgmzpo/QMRzf3Pkosss5Q3aGxfgO48xpXmOeQ69ipxnNEzQy6IcHYBcmNiWPDLbNpS4eoEGsMdEw\nRkxO+8JYPuIg/m7mEq9RM27EYvrysMZxH+quXCgLavWo3FE7gY/XSlhdoQGgWYxIRuWjGBmTIwdL\nciHT/0H1zD/y+CNeiJg9iVyyAvqWDUhFYDr+LyKlsGVKe4YEHetLw9bFxq7skrThwo0Y7snpQ1Fh\nIHRk7pKdzcse/Zq/EKjs6Wl4BqAr9nCsEN52Ct2amdAAGl+MZy4xjyks+7rAkZlM/6COnq6xqJ8Z\nE2q2Yd4hT5I+k/SAmlG8LgtyNbe8w5ACP6+hXCIUCW65ntlg6V4JsvP/mi/G9UIBxPrWSogjL7dp\nTE5MaOgXk2A3uNxNwo1KASYAEfVKQgY4eZwz35xfXoncy7adHw+EXy3msmqsVx8kskDvTvoS/a65\n/Tmf1U5MB9AzwFY77W/qnAEreauKFZvckDuDo+5Sfmx3cdkDVrp9NflHNSwVHpIR1j8R4sMyLUcT\n0AbEonq4AoSDnYhBRy1x8/biGR32WxG8iBknSRLM9DbSayASjDsI+lJ6YHDNpkl+hQP7vu2U6G2r\n6au/VHqjkQUPb/ZtC4XZ9xxH1n8Zug12mokmDgHpDLGILnpzvns5ENcEmks6OPfwMeOMsJUZZ8V8\nfskaYuQQZECEhK6C6yVEEv7r/V7Dm2HGUgaq1eCx44gJNz/bC/I43DEdj3XcyWGh9vzaA9hYPoxk\nEawR7wZKPviBGkP/vZXKFHO+eateQi2a9Lv7hcnWt8YLNB01no+qXKNrZ3kJhH9R22XwWo8Lno5W\nHYotcXVdYco2KVX0+27wTSzjAaTkNUGCH5KwzqCtyo1CEDQbiw2jxg1jXtoQrydtHK6n94aqL8Jx\nLWDa55ASQvS19ytHHkS1lsqJEcJbXsYTEC/mZTxZDNoDJAeQo9dJPQD2y5vo0cG5zyKpgjNDR0x1\nnTGLU7aKBLGFs3bKW+K6vMxGU0KH0k4MVLpg2BPHfB0EqxQ45IbJFB7YjQ1enuKXzCHadhYNi6mO\n39tXU4DAef/VybYV/N72hkyKBJHKAUx34vhIaTmQmlAOxRAFC72TPBjNZsvw0TRs3eDz2ZVeXsig\nE5a1SAoFCOJ7GjqtfzjtQkmTU2hvvXZZob7USQiUXw1CMuiQ3ifmzGTXhzEZQO312pWVMARMYSlp\n8tZaOmMoG1ZAnYOoM+3/CeEWIz7eMfpBTBiv2W490sQMLArzC5jPbfW5Xu2EekCXsihZs2DsplCT\nUSj6tkN66Q2aJZ8zUSvOsF+EGK/RVyPiqZWsryzYgRVO2i8WnTqBJXk2jou5tC8RX8/BPnt0UtF8\nkj0FSg6c8p4yIOtSbe69GsmdYp++6PzjcnkErWFQsyczEZrUYqG8hS07mx/1ZBBlkq/Rxq6LwoFa\n++t2vIPrj3FpCVFE/kq71QQQfEdEdBveCb/XnjzyKs3xTkD+omZMFj23tQKm0M4b5R9Sam8siSg2\nVEWfyAjA0Gbub+kl98HJg/pi+fYNnjG+uIEi+gU9Xeqlm5TfXHL6j/uovjWigW9YUKF1oIe8cert\n4Id44AreiIaiju1CYrWKzoF1KEVHz0pLJls1M7r6HZBUdovrEoE5YiFKAUD0NlEvarCWpQ/p94X3\nU+DLjN4FI+jISqQxmTr8M5dYffeJd4vAEPOzW2r2or2pUkYpZ3Ua+YKh1UzpeiGut2dFBODRlKum\nN+YEp1/7p9PpR8cOVNWtHEGoOwphpVafzOyFBV4WFmznik9DlNjWstvNFgWjG7thTwlj+5Eq+Nnv\nLTmKZbU1vUiFRXyVJG6artkdxQq4Sy418IX7V8J4H2/VFggpOIiqgtjifmYYR/yK5oC4U8pitIkD\n69TgQDa7yzhbrC1DwRSWu6zXzk7qbGJE0qq7OMNqxUE0rj/xAQT5JyPDeZeTmERW4ouZhzYJ/ty/\nIBBrxYRXyS5IUr4xzo9fun/98gK/BA1W73mD+ZxCe4KNXdAk4C156dsTipIQgxzl5BYyxGaeLaQE\nYEkcSyVtfPL+2j8/ZvgmTYsxIA4xJOjUvjELTfI6fcif0K2kl9ni163Yksuz72vH3Pu0yZcyDPzu\nKtLpRr7ku8hMBhgRcX3U7yM+mu6j8fqZpeQ7XOvad7s8+Wgb5Nxx0rgW5mgQhKq/Gp9FNOm1C/wy\njNpTBRdAKELTLDObBaCuWbGuvoSefnpcEjHoVmTWUzZHoX1PeTLU6W++D57jptBI0/K75aAUCnMG\nxrPiQdUAr+oNSSiKc+uXDfZ1yQVELkZUehfmv6OIkf9gQQe5ouOHGiy2vG+aO2JrjjUt/u5c+Ud5\nla2ZdITdVqbxjo6YWQfXV91HOoQO49/JxZWtE6Mea3+1u+1N6UFnZImCtZZIeBUJ//nd+ABpM02s\n5ZMsR6hULhSeo+4sSP4C83gwsZH+TK5KCxwZSErRT3GGiVb6L7LiSlb38P++ra+k3tzReQKCI9st\ngV+5CNqsrIabg7oCYuvhAkqPoTJ9WVI7ayKstwVk6c7YLs0UcRLpqQEMtzxeId1M99VJjKWluqfL\nwpik281HVrt+l1eOmmk9+ngBTS1PR9qEq3FEuPGdmgjLv+xOl2OncAj2gwDos44bqkFHETj5gPqm\nIisK4zbf31Saxl/Q+/uF01QcDJMdSRSY9bJ5PMnD11iBPyKhQZ/JszB5mg5mnC7Di9uOJi+rGvaK\niZC3UKj/Bsa7fPYWBTrf9+cmvc/XyG8va/+DS7wP0q28LdtUA2jhbeMgtedBNh87ZN3eoc3KWH9H\ntTUFnkFZieHxyfkU49WMWoo29u+lUdUkmZPxfD014ULyCXU21ODr3owmgAE/SWDnhNtp8kUI8BaJ\nrfgOf6RE47XLDd+zvBGCpoDV/+cKgrrLBpngV8s7bQLS+o3N2DgbJ0IvUxG1EeporB0t11tD4X0c\nKh4OEuzGYpTF6K1SEZ+y+q52aYNMY8CFSqNLMVSV1Ng5UsO+2a/xpwwsz3U2FpDzoowNg+h7AklG\nf4xhuv784TUfA/X9txVnwJ/BRKTc5EPPzGCKAvlP52e39CluB1ODKX6n2mDymIXsWFyzs5JEbKBd\niPXm+1gp+307r3bf5RDtYcKp6cp4oxzP/37ReM6PkBq6D/KMqnklnitQmI+ObzPf6I+hDlQ9pF/R\nFIyirUbnpxwe5kP6vOK5f0WOgS1plZX+GuiYQgzVdaife2b1hBDcM7o7aN/GBZUZhM7r7RsWu8Om\nqtoxQDxzHY56SeDVusvnIm96lD5n9prPT00M9Pl4Xa2pq3cy4iPv6BXbvx4JOo+Zs4kBmAomeKAD\nqg2a8tODaGYyKs54WxQjgg2N2cCPfrvMY8hA1ZdXQnvVaQH9uKTh5bdVC0/Il7/WqU1AGGAoETu9\ncdtLrfbRbmCFa4Ib5uD3F+vOZFEVWh1ruMKMBThysPgCaBmBvS9Nll2JDETTW+gRO0M9OrK3LV5m\npUBEe1unjhuv1Ha7T7nKfAS7EvcTQWzw5WDHbHp8MvDGJLlEnd83kRSVYp3weeD3rdayGfQmAYLP\n9QvUM3gaJTibe+xJqGCUYfXRAbrLXn3EMQjLNFRktFBL/8vv28WHGdyNoGMqCa6dBY0MbBKsqNZ5\n0PkdkG8DO2TNQWeb+FJHm8Vsz8r7hWLr47qRAuChikZNspeEBbN/QOBj2MkMyhIYr4MAS98FJc3Q\nPUC7EapbthuXIpXKRCsHI5qVisirkente1mukVh3jxSsIZIrIW4qZcZ/kzhrvIOfnB1oDMhB16tk\nk52QTYaxY4lmLduZs93VP759103/xyzz4FlRsAKw/3hjSHMriVZKEP3ojXkIxjW9YZJum3l383vx\ndafQyQslcokMomo5g7yqwm7zzhtX4qtvBfU9Dou/GOL073IXsYvD64mKPx2DUNbVh7agP++E+cu4\nLn71oKZ+5Y3/u6+PJqWIbT7U5bqJfljaXR0LN8zcec0HBt/gd7gYDjGjTqJ0/3/8AfztjKLqeL4I\nXNmLhpfXhznVu7KSQR7LAp0sB5xFKIdlQ9PcuV9x5m9/GfCffpQ92X4UoGBbvyxKWPUsQDTjdKFk\nnLaZbyEZHaD/6q0FuF5PITsbGZW00Vj2+HXe6lcgPhvNM+i9GCY/UbOFenznO2cudo0bjPSUjXDi\nbPjxNYuSOXSEzF2gfMqdkb03MDIpGO9fK2kFYe5thgdvjHBkBhYCq+wiTF55KOtGE3G2La80+A/z\nZvNAihFVPmn2rtTE/e6+JdqaZ8DG+dgR7F/tq8/jUAjY3prDeXAO0b8LH3rZr07FM5vWU6+uf1XW\nHryl1deAhlsyWAzv6QRml1uGpNeZiY32Ddj2DaEHIBXH4wRuKxVNnmf7Ebj+yriQECte0E9Lf3dY\nnJhCBjYHwkzunWd8dA4TgPRqLaHQQrM5bYy9vQswGTYnG4a+Ja97UaJLBdpz9BbYadXm7QJHnPk4\n8LhkkJmXZJdD3KPxMHAao5SUGcTakc+5KEAJbxWBae4h/bEOPtZDwpSl0gTa23tHn33dIHosaCIk\n0fQP287XelnXqKLzFdKrvPSxCEynH/Venza5sqB22bZT69qiUeFLQLQI0khK4xxuUxkTcfEFloAP\niVR3zIc+qNsX0F0g3+A3aRnBCRfcArsaYc4Hn/cTsFKNNNRpiSTwqNO6eyGNl6UQ7ld597wPAMfd\nLQmu4+M9jObGi8l3cd6Bbn61N5XLQz3hAVNRZUu8MhSlc5RT08OPUm5Twr+rmbO92qHq4UnFblnL\nxvEjThbgOf8vg+9GAcUavEC3dnmEL1vZSCzLHxYbCJZAKqLK0YyNSWAjPWo0s8W76jPkdDJnZ2Sb\nRev5MRfCOEFZtq6sYo8/7regYEmYMQyliFB7ScEG2h9wo3HOoLu5l4JD9BPZiY4khuPSB0sVT+gJ\n8yqcpLNJBw/KEShxKMoUmln/A7W0cyM+4vSKoVNDgExjioCJHdYM4EL4dorD1FhAObeiGvJVuR8U\nhw7M0UasFUJW2UH1xFqTcDv1Tw5Jkm9dDVkTiqiSDjJHBtoIaN5HBNKEcNvx4eAgCxEmNUiMkDZ3\nOzQ0JhBRcveBK4Z+bgiJT5AJxP4HxpaSQTwV0iffFtnKp9SSwtUJJmAu19pfvMf7jntj1TTk5cjw\nZq2mOZpq2EtPFycwkWuNWtFFa7EUJL4+iP76bub4nYOC4TMsQO8vouAVN/0wLc/JT6Yaf7Fdv86M\nC+81Y+0PUTLGcGGgddAQPo5kVb/simBDuc5u/yUgH1DX4MiE+LKeV7Rp48hvNOIZWgkDYsNfxLCb\nCk0R2655Y/fVsOhAfMWqGq8Ihs2kWAJflEhiajSTSWlSSkdET6Olgewe/gRH9VWkWGRuDws8iL0g\ntfBsJ9MwK4/wfdZ7llZRXAw54dkUN/YNfoS2729VU8QNB7FgTKIJkcsEudlKWW1NAfqxvoAS5L5G\nRg8ELLo7n2EDxTdrA+INgCQEpEPjTUP/ig7BWEqwll1SWmXZn4acb6Wh6pUPUkW4unUNROnS37bt\nJ62upU1Iu1z+XnFHIqAVm6bLLiLsIxmRry4NOR853RdtpX08neCQWbN9XS8guObMkMbrO+h4yh3Z\nNvztHfmy8mr0RqIy7W6ZTNB/dzclFTCzIWr/GKaW6dJo8g94mPrKJf4EY1N/5SgBIthHytBaxHkl\nsRpkEMntVpxiWBoixwgfRdTLfAYPRZ5Jy0x8IyMZxl2//bhqsZGJBYiQy1KLtxB6eW+sRT+SCNh8\n58e9P8nmYBXaEkKYt7qGqMgV1+hcHb0o1m0cD8gT2tJCMOvSRPjufNkR4JuW47wwk4S08HcUg0lO\nNVmCaY42UDmLwNrSMLn7CdkBA2cCxhy8zqqHL39SCJQmVaE0QWBnP4w/GPsc68r0gs+yU9KDt6MY\ncDGxjzqNrnhh2JRje06oxO2t5I1RyhbHGODhk5QL9reyKBEqxuEBi4LQZXLxSMz48owzB+/idq1+\n+Y05VzNv0dAcWMeGoZ5MTPCv4kJf8qD538SeRF619Y6x/91cgXXxt/5J07rmm5tCkRZoLlTFY35l\ndaXq3RD+5s/vk9Zno9eAqoINlL856PbtelFgwi2uoVbc0tZsOPDWbkeEFerm7Tkurq4+wFPcZiZa\n1dAltNh5YYZ7CTKRO2chvRW/mCXdmZBlmhWsdJs24U9ESWNmiCEUxY1XSPJvFUBcMtUIZQN4gWZo\n53oQZpc79jb2+DDcrtxqdX2NYeUElMH+L4IoY00ZWJdgSlOkHXvEuYACrR20b6PI5WRVPmqWHM1W\nak2+ciBOoh5/IxuaT34iigFXKkrIfM/gXetY2oX0OSnq8zfXFN0v4rY5j2upY1gt1C0pRbGyueKi\nzKJTixnWzBme8Kfp1LtxL8H5zswwhQ59+SSApV/tU4GWe7rbTd4H8ODRhZI7vQZgdO7FTKrkfXdx\nKpQM93oX37ihWN449RsoaY8TDA2VycLmQFYNYap7KOrQ25OLU50bV4GNtorunYq8Qm7KN80792rN\n3JxkcxlQ5njxcj9wfPEF7bq4dccYI3a1+YnPnCKDTpS8nceHwa242gbqezhZCn/malyRF7yDrGkp\nlwnKGOwz5F/e311cemwK6tgNj2wrLK3lm/eAot0XNC10DBcfElt2KsYBAPwooWypCGm02CTzLzPz\n4tLZ2Qqjf3MdczGExjG22nO2aF9Fp4liY3KNficRSVAA8ewU4EuqeE/NvWssg5kOhMC2T4UZmv7I\nUaqmfvLyIkkLIjWWhj4QeVjqBe3RwqMBdPw03Yl0NU6D+6QenqtBZ5ti7G3+hZBW9i0s5cnP0ktF\nzrwvM4JEYC0pTwkgzCQpVUw0Gl6sJbjxxHu64YE+FJRtp/EuMIgn/DYfEA2bHxS7OrbzUHpgXN6X\nTwBSVu+JooNoSAH7mOdPbluInRT7TFK5hQYnyd39m9DRo0QmdJKY1e9IBVDnT5GvlIrli7W90Lnj\n7w7qXz0P6FDGZVtLFNkyuSpN/gyRi1SJNpUGgq7qhqzansn12FnUmhUmhGQRA1zaM6EQ1q0hS0AR\n5IvPxNIuehgfl+G6Lx4+Z2QxODnhNBtwepOJ4kIhnMwgvEb4ZXO2AbX5S71RXCZe4XhPzD4yxYQ4\nCE75GmgpnbGd26rCet180fkao6Oif2YVTI+8FUDBJgIO3tsMQpFjUn6OzbrOnLjm6wCcFNKpJUgC\n6Irj7rzEnl8L9a4TJ5G1GJhVz/4fRSTBNl61vKshTiM1WmENBHINTzPZAIWD5wxFhDzSqovmfSPy\nhX8t2atF5TMXaiyaHaKDSdYNsOciDowx/iSJnoapuqCX3tDW6DMLgayZxY5E50Ex5Ij6Rr/4nYgL\nrh/JOVahRmkM2ni4NWeWrbbcQ+2dpeHIp/dIRPyy+SJbx8um+Q69eBmro3bvvGvoIGhCuNCf9B3/\nzT21sh7V19Fj1h1yhDapLXFPZ3PMrVtk4DwhLZPWhd/yZgqU9YRRHVQDwsJQPXEIdxWf1rB9Rq2w\n55/pJojbeAUvWTA4GZBrNR6jpW2bM07A+Qpl/RVPcqDgX/MsF0r6Jo/Yzh6x7C83pf86g4L8mlTO\ne5xelFXPjoYwTPXQG8AljFkKNBUUgARsyyQP3gpIGRgv1ZRkQNQ6nQQe9Fz1c6oe08gSEz3Ntc3n\nzLBemdys/3IplkPP7aDewX7f3VtHb10XlK5ilZXA8oCq7wRk5D6oyRQLIJ96Mm7tbCfmFmGyjQsS\nfyQqtvZ3iRPV/ktcp9wsDgZiW8hSBPbuHm5RkvXEyaZ5Kr3/8PA2l7UidDEpyMmn4JnPERjEiRuH\nyroC+d573FnGjW8eBTukq+YDz1wSCnvY1TUVoD8YSTyHKYUCYw1lj5BsG+7jezPGQWOu8MNYnDaN\nKcydlAVYD4Lt7n0g4dmv7X5ynb6leM2BqJaUFOy8GiYpn1SDHLNPHSdPlX/4mHC9/eFJ53lGrnSk\nEpBSgtST3GuYHyfVbfj3DuM+1IWVjN2sPUmTNTzSTJ8UhdvDGyuE1IcsvLSMzeUIgvijxK0ZxtuD\njuuVl+Nb9/HDE9xACpTdX2fjk52MTsa2kS03U9E5yxITOgji3kBgFaruGQuZfN51FsLkHdq/Apfz\n307aDUxI3q3Pi6Q6H6d7dSOUw4WA1QrAsiyaeMZQZEBRITt3k1x5il+fB+wX5OvL9ERzC1smI6+m\nf3yZOzke+rMtz0eQBi84ET9fC0E/OuJmhQaFE78FKhE9uEJ5JHLBQ88w2umcT90TslmZy9etOsNn\n0JwQ5YmdJg1T3zsOmZ/unvbnXcAUicO2LnVW96qKTJpTFKsw57b0s5Oa3GyJ5EgwMcGq/nDxOt5q\ndL16jRH5CTmC/mNQUZlIlWjIujDC8anzWJ05H398tTfzjgHARCnWiYp37xib+Lb6dN/SC98JapUw\nYYNzkOwqJrH8owlW06vZpNJYDNSzvXg/BnK7Tn3QnDEGOeXTJP46BWY7UFqoQjb7M3JbzKGnONA1\nj3doz3Smz9+wd98WGoL56l44B/5SLtt+FbMzIzhcXLFWALpRaZvkGPmAzqWLgCHTURtPec0NNtS4\naeRVahN0LxQmpQwffGdJs8D2rEnNk4zXZxlYM58vtbXWl3zbJ/wDmKT6KMZyQHM7YNhxCkEy8OZq\nTPMYHcs5vOsAGwMXw7rGdRpqkkYa1befbTb+fVwH/dAb9T6E/9lI75wT2ztLplrh7JS40XlkrLI0\n6eTzpWJ9xLvhNs9N9uC3qX8Rwc3kkiRqQABnbrFU1BYwliYM9R0GC04iJmkRsltHswQrsG4GGCDA\npKJiRJFwlR4djwIq6N9CWblyJ7aEprxi7a/mG48UGMPa+UOyaRT/uD8jvTMiCh7B8HUsUEaPuymT\nVG/COtF3uNOpr1pg1BYh9w1GUND24aLZJIPDtihG9/QaS/LyYu60y6upevfQTCtSAXdiebLEVYNq\nTwks1ZEk/PXWqIqfyZtsMPayU70KmL810r8IUtUUKiMDPFYZ6O9obtLppg8VI4N/n0hIG7rE8TSD\nO3tMZDghFNaHh8RDm0izsCTDi+eYby/OkFyNoJOdzDyGahp5UrkQZgcGsFNwA9dIM2wlKT4sLc3S\n4CsLG2MZKkiPD2aDBAQXaeag09vkS6es0ANUREnZL9cPPnJgms5uvGRGHPifUU0eA6GYlmw8cVcY\n+4dQLRnKQaFR8wWPfLl4s1DLayP/bfiOlxzgR8RgunRVaq0EM+41lYoj1WOs0Z3lstqtVwBiA239\nNJ7xQamXu12bWvtgfibas0xlI0qorEgHbl4QCx2dM6b6i9czB4TL8GpCMRSFcBdq/1nMqyDBHMtZ\nYJK9t3Ldc59JyklzQfhq85slJTFRU/V9KQauR4dHH1Df/J4HLFODVsVWpQG9lu8WAAmycw3A/jx6\njS1gSa3JY2Z4hQIPEl+Iokbs7fn+6ihYor3CBalvSOL7sUhtjZ6wBQYP+S06R698/fBNw7/7PkX7\nOicPRJAzrBxguEzWV/3p2KPcIPSOmRsvd0oG1p7JBPNZbblSWP0etWok2ZmKrv8xE9+JB8BFIJUn\neQe2UaSg4OnJ/oAEYKbafOTl2DhRT/rIRSLeOtz3CMPSe5jdRNLMPP1LLZ7ZQCucap0D33eDvwll\n9oGO6dJAwdK/621eWEA6Wcry6aCR73qz3EA/3/7yANk/NMAqk+P2TsK0OIyWr2wDtUuX7Dma1bL2\nz4MlieKCb3uzviG8hgzSZVDPABHyCR/wUKDKcr6SL7EkUOT5AvEACB/SsVFcDxOXqD9AA4mclJzr\nxDyobYcgpMUDorU1988V6bxLGZTOdtSc8VndqtsF1abNJRQCC/sH1S0bTQcfkbQ+WhESC12EeTAK\n84QlxLA6N9LQ8qHZi7DC+5/TkiRPznVypDCEGa86XOLYdKNwx36FQQaMjCR9ThkLMsJvAZgjXjjI\nPKR+D4FciKzDTcPbVSoPSUZ5hRoienKgQ9pkTVtW/ujiP5A/8fDa6Ntra4Kj/y83gf3+mtQCV61f\nsun3LAMV/EtYqNvJTyp72zyDdzM3QZkqnvidjtg1cCr5rsOj0AsisjvF1L5Aa6VMPYopEh/y9TT7\nMJ2r1GIgOINyqHp05En7F7KrYkA82v6qgJt3dbPgkL7MMQl5GgEP7cI9HfcjowzIgJQAXEYLNlSX\nBiDfynxC6bwOYOMyCSMckgvTx1zkHsY7DoXtxasJ0K0JKoLAKeqrDQgYuxzqftB7eKvUneGCQQfP\nFCmM7gIbx7AZTNupc+b45Oi3s5x/mkVAvKg1wx+dRtQlBKiQ0I96aK8uAWlAeATM8WkUBMOYp5+s\nK92tOO9CsSzMBkn+H3qfFLZ8fbH1DjCb74h8OqLaSAgSqVEJFfazvw/4aHEnl0bClPEG0uGkxJa+\n5sO6BHNmXeZCILdKQzuA79leROxpY8NxZiQ+XJ1P4S0pxuY4EfLcyJH4X9Lloa9XmsMpeSOvuwp5\nDDlIUo9/X6QwHXYnYaDZXuIUVdjkFjY8rs2qqYQJKSxF+H+rDDWMc8jysfNPuxE4zz/hsiDY0pYI\n462MBkMa1N1BCWAp3ePifJxKChywCN29XGtbznsZGkoTxS3TT4q0UGt+u9dR14NoGNVoWRJZ6iV7\nAVGuiTj8wgxNkwJsWYNZ0Ut/Wv1CtvAy/ZN67lFq4PtR5oSfL58yb9iJHZhvC8n8mWVlNnfiCSMt\nHRK2mj4+4vPH9z0J3NWkJyLUm4YLHNasWkSVzRrrXLyxR0dmC6E9ezZThgW3eNCLYOhffAsbd4Z2\nsItp4fMhyAqUA6jx1FzWBOg3XwANKcTZVwySvs7dewDzTKP8x0XdCF7nbIH6h841b7vt7bU0o/4j\nnJ9PA9WQ6wUuWIksirYw3O+0MFfEuOmoKBh71jysHZ2HBmF5ABY3mCdYZ6vko5y8Ko9KJCMxoyEs\nXqR39uV84J937CYMqtmvI6EMtZEyUEq7LsSwJ6o8RCKB935R0vCeAU7el9AbbtsCf3KK1mRuupXL\nwuuA1FfOmGuoKgkaQMDFuOF4K8BUfvFYMaoQnpII286RWLU0CsaEIBR36R3Hratl63Qu0RdCwIax\nY2warvQh/QFKIiEQOkj908HRWeV9rc4TmAYKDQELqh60rXaE7iEw+z8JHPHwx/Tdlza60Xh9N7A1\nfDhARuY2oeslpVdCZAp7hJFQV0IQIFPjDweVvA8dL5hVAzKqgH29kfjDa9bHpu/ku8sjHmXAyvts\nHmS++nonwMtpMD4mQuDRBEZKeWltXAlAh9ZjHihm6p7+ZrV/BRgVNwgb4M5LCogRoftcvK4xP/QB\nvD4oFo41HWh4JQTa8WqkzydPhaLkCDwMnHXSWGNrjzRkL1Dlz8Ged/st+2YbDgPOJ3U+jGf7a+c4\nl5qMBTd7LUdkL+qX2o1Fw/lhTI06ABhFBeiGDnEclUj0tE0JeAXMJYCaNF9QmT8K6JaYcCqgK2Yp\nz4QNLeND9UeeUIcRFT4SqaC0rJF10fgAQYekTbcAJFQFylAuoq07i9r2YPrHuGtkqoSY+O0asOFw\n6vaLxCczPGUXi/TvvzusQGS4hZCG2iRwjB+CCCtuYiXiC4g3qDfouzfXYhatQxrobO9R+sKhx1md\nk5dbgp3lXETsVy2UFQHDzxg+e7zmvqY9BowrLIT0gYW0mRWn4TYKVPHYjsJlbAHFGhF3MvBVI2XW\n2gQH0tzk5EaExYi+gSVfVGSxbfhGsUkOZvDByfmPrM+GyvDbgWsERAowddFCIcekTx45m3SnnZd7\n6wOT/cobtnSMWJST8N61VydkVmVJGthSRkavlOyak8GCP4tWKU/Gj4Hznv44cVEnXRj1oPvMPrso\n/gOvMScrotCyA22U0XhEE7srha2HmKDYfhXZflDlAJMxWwzCMN94GxNbXmIc4ysRRnM4YgtZ3NiH\nh33DXV3rYZaJEVqXzlhy5NFoFy8G3DMfl0e1Wh0SnzHN6kml9bRCYHsYWNVkI327X/YuimZeeCru\n05eKUW0lBY9oTyDdW0cus/5havfKLjD3V5Rd9E8uEdxDLnzFA6L7/5PHu2/FL7GdfCzC11cpWFHf\n/aDIkQPbQbkdTs0CfldXVPQzYaq/L/iojzQsLnl6mnThIlYpqNtNMB0PabH+P3kNRtPKTz2/BqQK\nY4iCif+Lf4s2iTtj/XJRz0yoizyU9zBrjdf44oM0Om+Trw99z4nR6yjB32Rj/xxDg8foVYMyNLZ3\nwzMzmTxWvTEebBnirJShGHxEvsiw/FFm7Le9agPoOSEfoOwNKhY0lJBIbr14zQlmkdu3vK2MhYoy\ncacyHvq4IQ6IyxI7OEjC2zaISws6Axv0w8mcHJLLk8V/OVkSsanPTfFIlOs4eGllZWk984UeqXR6\nIsSXyWPa7CAWKeaqMthBlVOmMnFLQHWA9bVoJ6LgyrBaPOGMF8UFvQY3NbYB7PDC1degHZDhQqcg\nDsY9N9EhfYe6C623sc3vwp3sQQgEdNewHOwRr0w+ohoNQ5xWESka8M4MhswPamnteB72s33EDjry\nNvc/zc4vFAJvEIl7AbZJlP/vOQ4dl/7Ajs41JvbGOY+hTUDy457pl9wezi93tPAMKfhoHm7h8aAG\nRaLImsKRh1zoba36G17CDRLh238WzHZ8UN0/gsfwO2ZU6oWX/gDTWFXRGVEkpSC8qh3fPz955ywD\nXNTXGwHGSpxA3FKzr5iz4aeEGKiqlyZCvVAUwef+w41oSNcBqc9+jTNsACkgU24ptsoeBzanZYC2\nCFmoR+FCKludhZqlyVCyvOccQiwD31PIvKzFrDTaNxfZZ9R3uRyTcn+wula2DPGS3D/e1jEMn2w3\n4u641lwxi++otHsTYvqPWfe9yyE3kZrz63bN8fYHu4rpghwmAHfAwckfOpdZIkJZA5QNRnO2ZWYR\nZ7f4TPwIQyOCr2y9dW75vNtjpbmDMBASsJZkgG/C7LZPLR+A28y2MttbW8Hvn5xCgSi8eJbZpSHp\nQzq7oxj5dSD8+hAbQfAk01/RTA1agbyMQOOr2QZsYupnLvXr+VpHdCe4YWN449NWVxlFsEznmnlD\nqUeJQhuY/87ESzss0tgkbmyVsNHFGAjFtKfClVo82ZjApGC+hPbZt8VW4FhZ7rCll0AtNCkG9I3W\nnNOLhV7tn6nOYN8fBFUgCGxGtF5Ln1hEsMV9DzxGo94KuXkK1aP54Oc6E5ikLmpUK8vmo0ZJBw3m\nNRIwOrTFPN1w+j4LTYPg1CqzW7KSRR2+0jepb4aQTZKEWI3ncihl16dp7xcDHE/u/nkV4FHG8Qcm\niAv76jzJHMm+t7xqZWPX9A1YK9VWu2jfBjCGn3yGPywGicmzXw3ygo7tupw4GMZwzPaNEEdpMamI\nb3V3twR9QYRFR3Lak8u8h47uApjtBkByvBXnnDHzewAu/JhfLliCryGHZ7gxfsMuN03eCG+CxIqn\nR7V6mSEaNwl6dzgc2OCQWqNmNC5/YWEQDHU3HoySVpGMJ/FYhUchX4y1Z1q0/Ux2KofPv0JjKvBV\nSKJI+qIZcljFk0sa+iWvNBCNPVeNFJ/VjOpQOijUwbyceeTCu7QCbHsC9D2vW3x/1Hk9epXJBBJO\nYz71iETabfK6JK4FzOxKTe6v2vPszmmXKtcxMYAH72IIb3dZJs/73rJRf02bpHKo/Vw1u4mnpYLt\n+zOdlHnFbUAbAcnxHKaOvlVxTH1OmrU7PxfdsuHGETN+Ydae6XBwkshu8Kv1JsUM76rAUfGgZ9Lh\nJliYMe/YlTfkSs7usqMgGmT6eu7oSfy/0j3HAz0vt7kahJQdzTZQ5u8pOzzK0Ngt25MwqzyfcUmg\nyvmwiloQDf0GuMjR8k/+Ei/UHQkMdhaPV0qrNjJgDHXTRUL3erWMBAu9pagbIAL6bsOfAP0GUg6w\n1FRzwsJgwilJAXINDNqnYPPVAFmmVXVDqwQYYP3MvFB3r3+JBef1PbKA28yi+WjTHJiJzZ0bFoRK\nCVmEEix0oMx4R8gKYrmBnUVk0o4k3tV6MY1UiHW4iy/SSFQm9M/txo/tTpyMv7iQuxGtsdoDmytc\n6nJ1JQdLfgBdnrgiUVj6et8kO5DqLBZUgV9AzB+M0qj//nq7mXrVOD//uXz1+/lKTO7ZdkirAZic\nJk0TwXjsfzLm3mD+CUkZztKYhXd4brt/MG9jrLWSVX2IT0gyTZBeK5qsDjb58TyLXIYxWqRhjncO\nG57r3HOTpoecojkx1h3W10wz0zPvxzQBhDJQxFdt++Sw/tVNMUY+nitSBfGNn03rxQjhr0SIUjZj\n1fZCDEbsClHvNUYcPkjvXMHP2EHBXTcOuZOMPKh1kHfqSM98Q7aBOZQ5pUyAOdILHX82oy1uyNNh\nt4AaXOx9v/zXFyyvw0Gpp74K2QPt4fNfIDIneq1dItuzDP/2SCdHr8tW5FtQqmLsFu+Erbm4EX8z\n97HJyCEuI64mFGj3DSaTIj1+pEM9Uo9u1/VRlsbWmc8oE6DuBdRuG//aJ9bGn1gsSmRn+wnctsqx\niCVSigvlzK0b0g+vfSjgjoBhpjHR0E7AUc5Yx8qYDlkvDUvClZMIWMZahaRs+Lvt4MKs0/4vDdXM\nhX1q2y3S/+atmsj/HJAxy0spmkOd4Gq6lCVN7k8lOl1kFO0xnI8yawwBVnV+UGWNo2ZpI8kR3VpI\nEkFufTB8ypY9Fh+Ng0yCG2OsJ65N0PXPn1w6t07igwj8Y2cN7evbCvD1jrQiK1+7oMqNSEcb9Xcv\nnWY86+0sCSxsGOgpQzNd2ePcGUgaEpHtsHPfKpSMP4jh5pLBbbeq3oirYL/25HoqQHsWcMz5T3yv\nefCP31Q+DPy6325vnvZufthULr/o+Ll7BMzNEJ7+N6pLaiNcLnRwHg45EGBXWs48LUjXrS1dcb6Y\nj/0zCDbLudVZ1lI++bqStMrmXIUWBsN6erDMSBvevl2CwIPEzMRSGZfF9H4NxnHdmcNZ44xaO9SY\nZhdI4zfGNNXxLh4bat54TRnreQwmKtIlTfjHZRP3QF0k7lr7A1sxOszsSf/lJb+JhCSrMcOu/QX8\n/48xQUJvqMHBUC3DUy5Vfz/WA4X1Oa32L4Sz0hPrDm/hdJWWm+DPX24QmAXTfWCqeNdaJqWZgL5S\nlmdMj9m3wcytX0ShmfxMd1IL3Up6pMWVDNxqz9AENNPC+E9j03PpuL5sH6ZkPxj9zoSnTyENk6OQ\npq7mc1jf89aMfnP28gEZ+07hQCWcNxBnxMdLJT8TWCSOJ9WqFnQYHL4vbffOgl/rpqkKHgrPrF7Q\nVQZrQJ0pKDZ3sFlHpoAcSSiWgIIeEGC1xmX9Q6wtrXtPqVyQylDszK5CHF0WCYRT2tLii2EyVARU\nc/GXeEtT5GOKPbUph7NGxdGqlhAX1Le1B0eZ3vCjlPky1VK4Q/lN/t0Q2IlTJUy2Pz9/PebVg9yk\nFJcCJ+V6w42ApxnJknl5SGqPd7+rWA3bCwuMDZ+t6dXSdSdUEoakwe6EtFJGpmX623oBheGaHcee\nY1UezZNcEPhepP/10rRt3BfOWB3VuY3WqMdKMOGEKv7YaucQr7f4CeA3plyiRqdKEHNjO01517Hd\nAIIs5YpGr5EqdKvTHOub2Wj13PofdKdPoNQIOiAqG3mJCNGMKymPk1NmYg/7XofjWW4+TNKNBnLh\nZ3GqUqdmPFSn05AVf4vDLCxUhC++WCQ1qEOjEVjnwEMgGs4ZDgfBLRF+GncCL24Bny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UA\nhYJq9hCqlCFC6+AKW5oDLHobAvPL3l+GCB1axpeio1Ku1wP+CjT9p9/IAZr6X9o6tpsVz3CNpdzQ\nADw7db9x/SmpfHd7onukpz+oM2C6956dfAPgSNi9++3A5vZvskyivbKhEaYRLMgEkzPp0UQuypEo\nSavgpu2eB3ttnSh+AkF92kWG/SzTq5DSCTvStite2CcDr1t2fSEzhrnQSKYcOPjEhjYI88qsZm0h\nisC24wl6YdJovWhKjZy8Nd23WHlODJdmnIg/ZdSGAjFo6d1XaxouQBEW2rQOJFVynH7T6vJKQVdW\nnN6VMrlHOLxvLoos3DhH/ga+NLwU2XX8tYwsD4VOvqCnrS0UPTW+H3WXM/UJ7gJStxVuDuCStbRq\niR3huUsKhybiLKiQ/hH5nOnbwUgtAMdcYndoWifxPq8royRc1Zt1TeyquC7rDPhx6exE2InAWdPW\nZuuE6Tn/HBbdU5F91p9uf4MREmHwbnA/bItbfnaie464DG9bncUjZTNfaB9ULa6B3XOS7Y0yRzXN\nsxkLzfXa/Ce+t4zjsXBXgrJWJ4azmhUp77KJtRmJjf2PXkIriBN48Ja2Rv8oWSrexuA6XbxDuBLG\nopw/y58LxK1BIBII3gHDP43N4fbJ1A1Dko1hqoZP9oSVkKTqbYlv/L8k2zOqmwxXYwFhhva4pYZh\novR4OrHBozGWY1b2NT80C8p/xcebFgIJENKOGKUQcuiZ6NNl278iZSTt3iTlOH1zqXuFH34pX5PF\njEFgkB/c1ixBedpbWngKBFlzOAv8SkKwjhqWjF2EZ4/bnEHaGlBcFkiDfQl+T9e64MgOEI87KRxg\navvNTV+X64W+e/tpoYC+vtE4EoQ5yqEiYM6QrPU6UACL9nua9pxmK5MXBwMojNUwR77xCTIDpZPT\ntoE4/fh16vl/h6ZWCEHX0esO2WGQG3kNtgG7rim1jat1utZWaSp/V+BZQubI6V0mS8V4cQvQGkg1\nJlJj6CSCVdxuXiLok6HcuHQmmrUReMAH+7nANXeFPenhQKGAYuJxLRbJxAoRmTO8WvRgSG86GRyO\neFMBNRTB1vphIvyLn+OTZ+aAT2b+crV934w9LxMQktcDqCkUw+MDiIVi1180wk95zNvATcdOa/a+\nOF16tK+Sq8ABul5Ec7RYnsqdXlJbrnGYo/OuSqjYM9P5gmU75oJu1UII5DjChwLq10/Ei9uPSmlT\nWPGGkCAC8QAqlaQT2Fm20UK39mIGdiNNlcXnXRsB6w/AbgERYLufjBgq0Ho7LYCzQkW1NXO4L3pb\nbRnnr9zqXbKiLDa4dCtoYnhiULBgpgwy7RsK2MakoEpE1jjdNCiCFirjk3/mjGmBwLlBF1Aqw/tv\nO5Zv6riG9fVzryl1z3du5R3Sz4Bskd9n3OcSguMYNLl0xkQlMPVzqp7Kd81rPeZJyBjMBinAbvlh\nXWXhKla6TnMg25tGmlfJqmDhkUNMdmXkGap87JFezq2ptFjUA2tk2VOlxeXuIpmw83M+GIpZfgu1\nlruO3VWcMKtPCQx136bpCYiEothiNdlf2nb4uU9NwzXnEOUb6kaTXfNQtQJU0ak5szI1kYYQPySP\nXUE9sm5lpdj+WO3pqICz8/y5r1b5rF1HpZWe7Ok3O/mFDeJZVrWYS2rP1OVzlpgGIomCMOI1sqEt\nd8gBJKeyFpqFR4m/nIG7xRwJ6eIxjRMCGb26gp9HggndpnSdoUcRXLudQqx+Nw79Z4iyixPqKx+1\nvmhmfi1eCy2c63AIr4IhCOuT/Qv6RGwFBIRzBpmmELU1cHFtFW2v5Y9D2pEE1qvR7kbkahcqUfsQ\nucQXygcNLdEfARmU5B1QEcaR+LURoaNzuFO2CNAXaNW0DykHdxddTCJtqeFAfiiOPqtfh3aPpPdn\n3ooAxAVhNxN23eKsTtSXNoPIdlXHLJne4C4E8y0uOdvnyM5tQ4+m2xVuD30OXEx+oQhq6ot28M8H\nm0IjD7eOsMf5l2pugm//MUmIAwrxw4DjFUigund8C9/2vSH95uLldGUpS6FNuW5HAAwtK9xP2ISl\nqe3UbpDf0m0Os1bxOl4/tgvqdZaTRZqvC/7qNwdafdxIThcQhqD0O9bX6/YCpZ3Dr1ISj+kqxRc8\nsSG2EmRvywAvGI0ztZiYC65aiWhFHX2ldWHxfp/QMECRrwnt0wPAoj1uW2KiaJoO32Ro3sTvZxLB\n2sKHyoVe7dhFz2w0yUJOxu0y15PWEiFe0ut4LItMUrpEsHubp+m6biUMMQViHZLdLrlAkfuKqoqs\nkk5nhEbmY2gMx8tsnAdHtGL9EddYFX1FyrAuAPFVQP4cVYKtWGJ8G4/NDJXhgxis4C2lj+m4e0YN\ndFcs/audKBtQxpoTiRJJfDtwQdruwXbZuRT1dGEU7aAabZLsmw9nyLwcF4WsZt8NnAg3aMrprL/x\nUrMghjPnn0rvcbXB27tu69J7pdN/vEPGF1MGYw3cTk3UJ6wJpp6y4+xHTu6B4ztR2UeJtsFQNbeL\nwfsGdjN/pKZoeTGGaNsm+YoZWIWPk+AiNJLIhWdfG3qMHZsDcVusz9Kk3gNioa/uoAHckOZl+4rm\n2Q4lCtq/R15eWzGmUjp9VV1q1s3tWx3e80GDUqaUFaGl5xYF1ivzoexNIWs+ktSrjAStp8fgvIhM\nmaWdg3fIaNF/WswtUJY051MKICS4CiHAS4BZO2vokHdi8L8+UVatBrRt0kmzkwYLmyz3npoaF2+1\n0IYuE/0Ij4U0+Te0J8hok6lP3iBu1MUHIv+TOQ9rxapNX+Fnx9R+OXVbH6r/SbrJDgqTstJYUnxF\nFY36l1DMs2m0nSK3iHTD3zHn8DIN3Hmk0zVoPsgmLxCawi325D90gL6HBFE8Sp9cNxKL5BUG/ES6\ndvkkpVJ6/UXcZiFUzZUd0KSvoIiyHci4ZZNepTxGH1L+57RrgK3OOIjG8CPJs10haEW/4x6UoSte\nUXMXdtb4qn7aDxAYAJNiPCEa+/bIWlFNAjrGAmZ/h/7v+nULWQ79O3KQlLf+TvawSkRSg6Wa5I0w\nVpuTymoBVc5avI4ZxQuM+2RJcmyxDeC85/8qn+tstqzsrkh8MOWsgLPZVBXkkQo61guzZ1b7Lexz\nyiL9MN+ELGob4Wr5n4eZfwYhINH5Q7KoSd9FO/DKvjOKWFbfvZ1oBCvBH36KHcFT1uXdBsDz0ba8\nxLPA9bv5jc2oWDTxgeBocaseuKOQsCm45xpf+AbSRg4lnew9OaDgwPvTd6Fg+bH0fUxhmCUWCG0p\neAFjh1CDluyrFPJQMxqlfavg50k09T+6x6jy1rvk+AO4hmGhApkbivwXpyrJgT5a3MQXj+KLxLAE\nDGxJgwfK39GDVxP+jAbMuiUog0sNN5E9GEKoIMu2BVOD5O0+eOT2+63uwSJEK3DxXbrKGzNpiy69\nzTa0Fx381RDO5Mgsd3j2VeQ9l3Zrr6tcizJPyjXny598dtBdhDZyrUOsrTtF/UxR1GMFOhaFar9y\ngeF7zDkUEEK6mH0FallqUOIsYIAbOpoWh/0q7rDyj66aOK7S0AEl7MV04kZkzW71GV89zbOi75cf\nU+41V/PSLEOHFqKnt+oqLOHL2lHIneZO4cOQJQ5T4DA5x9+kUA0xl3iNWxN6CeWwB8wBAu07Lqb8\nXzqYOnArNXl5xt9sbcRsKPDz9W/dWLAbbm5A7DTJJ0mlI5vmh4yI2pE/LIEqehkNQ0Gu6XklliNw\nsM79Mcq2xty8IxvIN/viUZ5icoMQ+j5pO9T3ANdlheMCe65+UZscAuPFtUN+ucupvNXHYnaRNMcH\nwS9lDfWEce7z2xdLlxai53L+goJngc5iq5Bz3qgJp91alMSIvvt3KCkS9GLdjpHnCFjzGXev8czm\n08jPNujHifmap317OJPqwQ2UhQ+kjPXkVXFFEEAh+wqK9s0mzsqj9pfsaWCcbe/iDCpiGLrXMt+i\nt+ucU6LdZpdhvn8k4U8HJF+NRoKJKj6xfzor8q+zUipNRR894lWuXbzCI93VnpwNCCKaf1RdwYw0\nv5Xn7Hp1iWAB+CGeHRvZpXvm0p62libMvsCwapNALICce4TrZKg9HWmop6075lYK5kOA17tnkYk9\n+ygmrDLXY79Nzf/9UDqo/t6wTLuAW/y6ldPmIaO0wAOny7FdTF4HQsBu9v4cZ3MGXJfxmFJ5cLNC\nIdt6nV4L6hmejHqV0g/Rfmj8hGuVJxp58DlKbcyt9BB+harc2WPXNXCB8Zdqrma9DDeFiRzK3hrA\n04khO9MgM9zlZTiOPj7Ht5/dZigvcEF+WO/rhKb3Sb7fubXUT2ZPRXR9y1Sj86Sl4GbJ06Vb6Mo+\ns5qYqXZa0Xh1ot4hpHYJgue5P5cawezTwdH3ObeZtoX2RpLjoxJ2EmsC/VxztwK92m5sFdWIv/UJ\nNMHgP0gPEpFF/UKT/HPa09lv1NK6+g1m84AauGw0NGhYUGMPFKU9RWdvg7aZsWJ2jdRhNYOI5FGZ\nfjekURIARz+wdeTZziyT5WE8RD3TW0jGWsObgpuMWbfdTyqZY57KfQd65G/Gt6+YrU8zuPBMVs1A\nyYOLkW/NbY74gV3B5Piaf3NuA8R65MYcYYjCWp0oCrY4SDskBgj9C/43/dZzeAdeEo9mo/cMkSXL\nAK+W+cuKh55rW1ccF88p3eDm9V9v3G1/O/mbc7s3xECD7BRZBb3l74wEf7HopI4lZ43OwA9NzybZ\nG7NPaE5D8BO2ZlGZyu6bRkTMC/rjwMDaVpC4TeO/KaPJOZxkAaVvG+hSPkfEFSJVWVb45tg4XsGY\nufXx4nXlmKekmBJdSy6tHqM5iuTcJ9ovPv0eg9FztmR4OgD4LYpkXNrx5ExxbSr4Ktvpb6Reuzn6\nct5hVng789AwlvL8FQyKLC153/GhzN/klFegw3td5y6aZfV9QjZdJKMK5zkSpXLwcUssSg0u9piP\ncIq916MZ75Z7hJ99iNUqq1S3M+NNIDjzNCJmxM/3dyzGwak3uiKlatZCAPYMDU5MsDqO2+RQMxU8\npd3kqw9C6VrAMglxCr6AYc54L4vdJvUAWCseumb4YJSg2lV+hchwu6o91Up4JvNfYpRosQW7YJed\ni2renAF8vyOCjOmnARw49sSdRkGqBgU6zhhNOKfrKY+HTx4ifnpFWDGRaPEnJSEJcTovEJ+ZJs7N\nSWSrsNjpnFDCaGweMMExxX1O58lTf+UJlnHakz7snSil083uWgWFI5vYS6lUcIfPexkcTtQ4lD1X\nMZpj5WeJ6a0k4KjTmqE6jBuAjRyETRkkXpvxoRnBXUC+EJv0t8+9qvjOlJ0jykshBqTXHOWm9reE\nrHcD4dUg9Um7p/qBjOaKPh7R5BretSgQ7OhYX/bvx56rwnnRAR1W3hJfwSSTckWe1ZLw+WPKaxWQ\nNr53iukv/ITkYQgpOjCA8DsCa8fJZxjDf67OLSA3HCQt+uMt7WmgJ82d45LMwozGiT7Ltaavlz3B\nWEpX0nqX/lZaRkm5V9GDX0mt9tCMmWET2hnzmi/MpPg9YXoJpRHhWKlFKinohCIDGGcUR/FLvMX+\n5ePBzGvb3NALoKsM6DzkJyBOt06geXnItmDI4ouvs0B5OqiZ4iUOyfs86vQetRiYP1+gWpn5+SIt\n371/H4Yp5NNdngDc0UvUOuc2RwKO5HAdCldXhtZb2ILBRjixKF6rx472l6SsHeoJbWX3sVREKmKd\nUmkqvCuqbACFf1P4vYsMJgqO4EvklGMP8JmFZIwv5MhpimH3nSk5K8zdTwOk6Y79HwdwhlIyVUP0\nVqzROg1nIGligoF7nUtk7CRY9m8Sh5HeZu3JQn2WbyAH356f6LmZ17yGqi8Wg4tEK80Sm2M7BKTt\no7t07J1eCUoXlmpsS64tjZayk5SApS2NueUDprJaW/1mz6rEyeSnK+BaSIytqpptz9rJVyGiP7QS\nGznr/FTZ7mYSMjweeIcfGw6IVXe7XdntWJNSly/BbC6VdXUqx7MHsl7BhE7ZwuHfDoIg2NJWh4L4\nHEWuwioeNS+ttLS5POUmoJE6Y1fDBB8J2i+GyLKR2cU78c9GDxqEPMfqc3qGSnH44Qasz1Q2FDxc\nCRf1I/wGh/rRCuMdNO6hu7xRaKW0Mt28Mel1h2EIN1qlYFKuLNDyo1saiBuPYQfA+Gu0KOeVm+35\n+XsWMBtELja6JR3GemgKQ42kirXNKlQUV+R7LgOyDVrMM6rZuB1Auzo5SIOfs/bBe6cxm0SFsDlH\nN0DqSy6bBgdWnVgSBx3oPR1Odyu6kf4KonTwWy4GG6FioIXPBgn/XKr7I7haqSKuor5FQRFFgEDa\nMsH3UCVoBguUjJ+WLsUWlwp9DoQmrFHmT3YzZH6QJYeo7veTY6jtHB2Y0TDN1WsqRg/laSspMwsN\nbjMygPBm1/yeeJ5dsxbBzX2hbefQJNk+RHltUrG0bWoWGik0+1L18D62/ASrlfI5hlb4/jFmIXfe\nwNRWuotl4O18z5J7DrnRSTTp47reGy7y70nUozHEWxvLwWGChgRaUMot1w91yx1EpCS2CR9PYsMR\n2CR7JGKoKyygE5Law2bOTTgrnqzFGuWp6Ejxe/FtppJbWBSR+J4L+klUC4BvIPHOc1X9zZNbVI25\n/aiXy/pIWc0c2TsCmbF0HBORGQEK3XNahld6mFEoRzL3J41WNaUzmaLcWOd2wDlk2s0Vk8fK0+nK\nU0QJPHn+FJOrEqX3WqLJDDc0wKEbRsuMbcbPMJsPIxi8z+kWr9+50n4rySBzVHMUIltp9MHqRqgs\nb8oKDhxvYYhWrzViwBpDoodhrxADWBFqAqvIQQzxT7w6z4RXUpLVahg5P3ErlzOrYb4dDxGjjy9V\nGP9wpVq3aC5nvNIhdgIKtxP69a3Nem7N3Pr27Uvs7M1A8WciLofaTYFn8mbd0IP0VbJnJE+wGJKh\nLgBqjw8UZz8rV3fx/VbtLEiTQR6GTHSuNrmB0wHcF7j+z5jGt2tX7N4bd8MUQcStPy/XQDXF6d98\nS4TMJQvjrmI4Ey/MInMwdc2KutASjKbnDFWiNFIyO/fpAc5l8qOyYh8KzlhM6HjaR270B6HtQv63\nqmjzj6cPad+W9SgQMIMTodkEpjjwVAIQercxilSqNgV6g2q2mx8Q3OMjCGJzJPDPUtK5l2k58lTd\ndhKPCIzVoc6ODQxhl665nEEkV592kiMnHZeqlco9id9004nLKYGDPjoVGFSBxrHB77AQivEUYTux\nyKfTdpitTzXMxX9k2TN2b13tZx3qhgCHYgF5oYlMT1LYvguH4MjZcxEWueJ8QUMl3GeKU8i0xkpP\nYujhJX65GQUvRS+B2gMmBMIgKi4q/mG6RE8Qz3Zovrjga+0w3lemVNNxFgOeAno4ERHwP19Mcn0g\nMqTRsjGlIO1ynw3Y06OBxgzYOs36o7gxtqPfObij1MzDS5E+B0TQYzRNkXyXuzq3em8T/g5yb+Na\nvd12Xb6HZUVRoZfWableu4M/Rd+IOK6wrzRWagnVslV5OEvDuVvM9QZQGh1s02IZHt0a8Azhq/t2\nLJHv3J21nCJVtcHdIL9yX2T847QJpnv0I1ZXbhEvGsbBD+cF3vIAk62b66WyHcX59gy6/LETBWZt\nBibhP0YtZo7eMILG8+KR35ofURKKLM+iITmCTX7IKj3UlccuyHFcduT+iWMQ1xdKia64qZ3tKOGI\nKcZfSfOBPyzwFQsNYIwbNE+oEriENopZkC0fQJxwwag67HKrB489XvJbFnw6H8s+qVwZF64rMXB/\ntE/c5vgAu6JcsKdpIurSJrWD+aZ187ALVOv4X5/ZKmkz1xRjiwKfPMEmTdtu/6tFd1JKa/Cy6NBW\niX5SQape1a7cmr+dqjSHkkkmZjttn9joaMR1xKQq9n5A6uL64kltTfiD8hFlW4++jtTByXVFhpqP\n4DDGaVtJXDf68O2GXQNwKJ2VmDPxuGssbEV3YhQzRPUMOoTc8BfCVBitclJaU7x5zgQiS4nLNjQq\nLymqnEVvgY1cMKI6vqKQ9wv26I5SXJK2f8WQhgk50T4Y4ZbDaFXu+YG753jBkmef/7RquevxTi4Y\nXjWFnWobKC1BtPdCVviPLjJaQpELE8w6mlyOjoIfpXAnVdXJk3Vt4ftLbiGuFQaTMhd10ZFU1S8B\nk+pNkCLWIlRM5XDZGPBV8rfBDbM0NfgHnS6i1IF+bAqQC/MRsOBcm3BnpiD6g8C7oXmBMLSuYI8K\nta6GluQXRKI8CCAzkOyiQk7X4vd1utISPjidlqMex6YOaw+4MUpNmygbnG5MI1jji0VXp+hCpaJ0\nA6ISC7tbZ8racyudquk78qiqKDLShRU1WOLrayxxJWBRUZz5+FlaFYymol6pHWR1num13pj6Y5Rt\n7NYCBJrUI+LoIF20XvoMT56ZJgv/ffYv5D9mGndKmGpGd3rXNwY/7ez1u5n4nMD1HDMWycKE9cBv\nQ9WqF5VYS4sbUqHTSJMQTjeKF5TydWeCesX6LFciUFTmISvihQXseGgHUnzfmVcvaqA46p1L0pNn\nBuA/p9eDPrS4a4BlpquiOMACExY/wqnQgNJM4NI4c4ajrvgCquPBOyqYIUL8R3hUfdFn0eMPApyo\nQYEgriG7uiNgDneNeqHm2MBUZERyTjc+mtrNfP2+T5Id3bqaCF+4MFOYrXgf3f1hxtQbIjO+4lpb\nu/MYWxo5OVCljFciJTlhe7kzyjFkWsjAc7ci3wTb9T4p7/JJIDfBZbrZuxcWa/g7s3V1uAW8nO9v\nGyw7U3XrOSBjbevMgeLxxaTOee8YwbUHXIuPk+sBFXKUe2sD8NlExITWsXN8ZYxQYhhvBLyBZf7D\nlbGDmpm1hKJ76UrwYi5xp0bCk1JcB03niFA76JFO8RkazF6fzfDTVWMiHsKQcbjma7oRBQzTgahw\nXu542b4DMTU1l4+LuyOn8VsX0UNUGbuQ3oCp3uS7lYkRxr0yHtfgX0IhyTexbDFcQdQPZuFBAzx3\nSg/HclgDWkiWvISAi/qa108dZPgBqZp2z6ULVRWkkgUyowWb80U6AZTFPXJQQwrVNSXBxV9l2l33\ngv/MZuT1Q8qmnBPDTPIfw0FazN/DcT5ysYLc8fPPqkHAaovArLrtro/+/yWDGaLBxy5BxYVR/ifz\nEF1H33SP7mZi7EJWnTpGnzXOFiq2HJ357AdwkHt/hrcWsLSEmVGGd20KmqMUG0z2OlUDZlRzsqZ6\ntOB35focElDu9OyoQez6Vhy9RLL+ZidlI9EeaHOPTpzPTmGKbOebsTD/DEeYT1V+sIryenl764zV\nGTp3Bakzu00bvzuPIgqLsjHzlIsUer0QTEtxj6HKY6RiSzXsIo/iDAmsGdz5ao6FYcXaKWoyjbC+\nHi2hKlGjqQoCAxODOn/pnm1uyUE6SMGLue4O6re/DlRW9BnteMf0fpy326p+qtkg3RAP7J3/WAeT\nQ6JnRerKcUcR74Lk1Xwnfd5agpGm6jLhkK4msWObdAYXfPJB+IYbqxmvTjNnSwV0f7V8xUeoqsNm\ncDG2Q68Jlc2pUrsC3owG2hBG/CsDZZIGmcUwQaZsgV9WrAFszliwDyL25MpPa1FKXP9uOXcVMcCO\nHigBTqvA1WRDzKeCl0ED9K+MlTQtSKemak9ZIOsf6MPcogOO/H5DH6CRnAI4gY9ad3/BzATVoImK\nd8oThoFqxElfsclBF+DtJ3GiFOcr1SUC/7ya2/AASmUCPk8XY9i6yDlPDR2LNxZ0jPD4cO5REWIp\ny6OGz0oEd6noFOrbFTi/NXeshAjcjcSw0d4H/M6s6MXICWYmQ/KrHyP3FndEL7jQ4QSD7It4SPwy\nPJyrwf1GOwkbS+NWHxYnCuz8FNEqhhiMYWDv79aAxjYBhX+4pc8RAQd5LIhwF4HEZUFsApa+hV54\nOYIxKjUFxHzLUZeKHLlipGulyszjBE+G2TQ1c3Lvz3BdRV14KCxH1a6k9BUxVzNoUu/nQutgJwT7\nxEeAkbaIB1m3cNzLvu61/BXk9LJu40icVdYLJo7ryp/agt69HdOLT8BOfKFe2ivlqQSwzB9MrUOM\n+YHUdTkgBftuBUSj2BwufoCvGv2xln8JZB4JKAAH7fWXxHyb4QKyOTEuMzbbBha5RMBhyRm5+L43\nYBXsu8LOvF91tiXR7SRgDsAXhQg0c5tuny9irl+G26RRjgdr6dTj9nldfP6XlAYGzQk2wZjsjhVu\nF56gqDCojdIl7hVHlLA3wI3MANS4oIHbF7UcOHJzbYwiYTELDJ8e311KtvlGts1i0tXXjWXao+WC\nd9sqCPw+XWAu/sXs9dsuyHp7bq3tTJMuu8+rc+FOt/RqxknVkt4EInWnD8i0TTIDgMB2v4qk9yqx\njgvctzsC6TvBw61+X5LZXCIElFHHMarbMMFC1fMq2m5Ot3yO+7c2LVfJ9KqIdHqEgSNDhJVE6d9d\nDLwBYVp2jNyw0Gp5+zMi+M95s7rubNTQhLjFE1HQ+I9hP4R8v5QOxRYpihf4RdLNXfPifr8/e8RD\nCVMEHm/e7GhG/JVf0zvM3CyJx3w3XbMObIlp0MKg+fafZfYyzyVA3PDlH/bAJvePuN1BuftV3naA\nsqSbMxfotCMpqdyb/PD3jkoTrsQZC/ytFbqnZGDM19hiqXw35DlI0+sQRLnIg+v53uXheu+8k9no\nISV8V6kobv13F16AxJr/aOjWbtJ3/PIJkS0uBWH8ikedW7z6Jvw4HJNx4Asmj8EWbcN/SiSBmXqY\nrFKAypY7hJz6Ln5TUdEHO8OyQR1TnRNUnLO8rIchxgdezgEvLi6/I9VonCscCaklOaAENTQ1GWre\nsIz/oopndRGj7GixVUsZQM5xq3BRm0AhNfFv/bOqUhxGqsfzxM/Gdby+akrH2K1o8z4DNgRU/oe2\nEOf3+QQ2ZUW82cwlT0XTjeqarYgXe5x88pQPPA7p4Tt8ddo79A9lJecpnbO5lex3ATqjlB8rVwvx\nmbqSBuixjJYXDcZ72/H+GGJkhcZN2qd8xL5jtU7sX61JG0UReEL+HE+jIk4CVQ0o6ar01KoXZGbi\nV6Orb7jLe5f7oCYhw/WKFjRiKQfv9HCyP+A+ZjfBFZh8lpeVwIsY5MPbUzScTepPW5sjcs8B46E6\nJGxHgEEN9XLyXlTGIt5cGC+5V/28HAmWMz+LrNfLR9AwjdCG5ArbAl48Y7AazMASP1e+HEgbMV+/\ndS5F6bGVOYkmudRqWtMY3zT61dkpEC7i9Q2HGvkhbUIfHn6BLTv41BeVrN7qqEudMDFGtgy/xsno\nW9+zyf0w6QCkTj3R6JhkpBrrniWTmK94WoAUvlzssPOK1Gw28+wVgYyqd55kQoa5V1rX22wAdU6C\nf7w5KGDV48NUA5oT5ixhPviJd9vqpsc577I6uol74wxELCNMZuZWJBA8WU9WLcsdRTTSY2qvqdl3\nwx5d4R2adtCGUvdlfwisZikBKiFufmSuMpHeyJvVjJ6GQHVe0JmyTzNoxcsF9KsMzUUxsZMnb+JR\nSNJmK4whxLkwlPD+KUW2WxYIsVskU8kKSqTISTgkPYBGfN7lzoLUj4NxXg7yJ+KR09P5wJhbbEVj\nO0Hbc0kaQDfbYQedq8WQaghwe1NWYVoS23lJGJVnxByWpLWbja+VZKNdn6S0M/+qZRbSLBFJjbtR\nTQ8GWPZ1uf5SdQcXJOywXjAV1RH3lqbgTFcjb0z43sXC3sc2fIOaYJ0mIqNAXjIdsursVkDq6EF/\ncZ/4xeaLuMnr7ROhVBLHB5Av3Kb8YmvyyXx9I+U29vs9Sd8C15zp63MjdWRRgCKeQHO/ON2kmKz7\nPjdngmrIx3XlgzwMzRtH1SHpckQrYRSC9fZocpG7CYoVWBLrhuNreBuT1uayg2QhLbzcrpAn8IIZ\nD625zuFk80iCGHolv7JQ9Q47Lf2xM/0actjD+Lejd0fvpe3K3305o4vHlpA0oNVMfi5mfVBNkuBv\n1LhoUn2Izh12qq5wkjXImknk6HNIKG13zg1KWmMi9/SzIdYSqpw+PiQHWqB2xp4LKZKbHZm8jQaL\nVU2ew9fJwKdv12pP2TTH36dat11SmwpKPbnie04We+YNEnWYrVXgT//1YzTvf8ZVJlcJIMBUiE7f\nNK+AR01l7rDJhVa8aXzXXLHzE8JBH1DXEoUCOax4D+g0TXRFy/9fnB0XakPeqV+DBuknh7YiXvnI\nnJ+JbCpbf//kCTrA38UMl3oUVehrDTGQVr3nNpmOCEWiw1GaQwhjFtaoWodh2hn/4nx1DZ+GSWpB\nqx5FqvB/nrYbx07zmy3pEDBb3bAGNvyOEzhfPyQ7niSCknaCbkWx/hglo+q7hInzGDoxEYrudYHY\nx1sma3Chv3Rf7n7JqkWvxuYJuxgwkFsRvf9pgFfRm37/PPiOZmgX6AWeqNQgPDnzOmwTSa/iGRMC\nD90AXuvTkab1fhrUWukC4SKX3RN1MGdPOkvyg3TZc+UD4XvX2+TjtymOCK3Rla5c+LmmoOO9nNfu\nqkiPL/ijts+OuD1QPNEa+DqvipJVCSdkEB9EAnrYwIqsOgArow6uWORqACRcXal9HAibljQNNy4m\nYHS/hty1Jgp9nitIpff5M5BxyONUCMtKHsCods90vWC2JRX8fVmlgzqNrVwiroDTl2+KJWSFqR9k\n39iQC0ffBUaRDBV0agffw0C3pQfXpk2FbOC8ghEEB+i3mEh1H07fOO+bdZjajwikwiYo7tZh6m6x\n89gVZznKthcfGVy+ycjspGTC3iM3qjQy+6HL/hexwyLUMQCdQ/1RC0Kk0QzTno93BUIai/Y5KVfj\nuvO7eygpCmXepkt8BtJfF5liTFjUiNpmDya50u0kzEC/6yilFH8PnUk2VmR6TF12iRhniUm4c7Ut\ndg8vKpCQaVbaQ6O1BHn3ShRSvVGYEZsdCOevp5OTp42O54JbMUGGzBkpy5yekGGkQRKqBvTBOJos\n2gct9J7QB6wPwDNHYAjvYIEbZs5TxVLHOSu4LZDljpMzloCvk7AuqqqEO34UuFgvpJ+bee4u8Fma\noJHzV1+VpUzkNsY/1QmUmfsZP5GW45dKF0Y1I6w9lweRVJW3MUwB70c7f563beke106RnBfPwvXi\nrwxyELguOqNOmzHAhy6AjcwQnEyTJ4qjuAkwHhoPNHcziQL20Chqb+sSOj+/Xj7hOLCH7x8/Qvej\nSJINQ+K+tVibRXOIMnQVuf4PJlDKTugCGPDYjJUs8IeCtku2qt0esYG5YBUfdibJ2B941cW6lKZV\nvhfbKt/fqhVg+AZicR/lCwjdZHIIubLtz1mX0A/v7msBQLirtPrgb20ZKkp1OitMjFveE2nLyx02\n6i0NY24T1QQB+hc68+DjpNUW1a2KspWlJg+1Et5GRkzB4tATfMVS+01zykYHjEBdoj6loGx5sxXi\n10+yQp+BEAgyQYLaT8gG4gQHn0Qi0w27KdnRR7AHqelPB9Jt9NZdZYR3N694kbO0HbwRf44k18Ll\nsBkscBmrJuwOJVav7WPDIoL1i3LeGVLZ6+iHeDngdfVIlqD+sRWF4yFLSf4drApx4hlFsoUgH/sf\nKvfmCoFbBRGchTTnPev705pd+5ZiSEtVZepFiEZYfR80CqldyV5rxqZe2GR/Rm6EXmwpOM+ivm+K\n7zGMkhQ2xNa2VUFG3ZmTxBX7POmzdkjN5bvo/Ath10P8l43kCMNovELPrqVYw9pLBmyiXlgkrE7o\n5eSYahXUOyI9lfzCTnswzXyX5E2VeMWScxJ6h93Tvx4d1v0r78bCz8iIKkFSoi/vfLft8wSx9M0b\n2hnTmGVIaM4y+nyk/W53iv7oFvbZCjzbFw307iuURIAYp7NH6NRpYlot/iHz2W+6/vglM2Kincvq\nsuyEfw5cyD2ovVcbq2vd8fdvv7E7qJVAY9zhF9OJOByzpj47G3lvQZLYXsGh7XP21zvX5eRTLxG/\nq7nTCqYp0HTCPYXhI3nzkk5w7UVh5KPhXbjNlHurjqd97ANErMRlGIPcq44fxREvDtUFxmIjVMH9\nsefhQBlQjm2RGCqC3l2pACnFxbHE9PlGpYA6wcOPzjYQceJN45w7NIaBaBJDmPpQ7YbwJsyvw5/s\ncG2xtTtx+lcSFKPrvWHz8sLOxFGw71IOhTjgzrBisXcgpHlAIdM4PhCwCgmYwKtHUci0F0ia9uQs\nfLuuRooHQwFsunApKaF5ZtUtB+OpnDfPu9DFSJp7NLZAshwk4lbKuEQHCe5CQQ8AaKP8L4itOUIC\nh9aE6JBeGuvsUgy40PSdly5jxGyfawE9O/Kt/qU46dn4KbBdU9x/IbwpbwF0Y4qlMd2Qy0VGotIO\nkCuvte82Kie2410tXrZNHzabrg/ZljUDyhSITOLI+FfzX+s0n8610xuclgV2rGmKdR/4rD4ON5Ij\nnvq0ycqmiSiMTJnGom7ro4IvzKtHiWqS9a9H1eEl193KHtJ4obfX1F76B2T+8kfOJeXtZTNBh4N1\nIhBVkUA1g++71ru5UcKOOJ4VYg4OZK1/4vurIq0xMUQ3ETVPSCGtKJakrWdflEOtRXDvqBbo2C8i\nPskuGlXg8SczJ6it/qNWwcV1rWd3jJsxUMrIs6qYmE/RWmiO35z9CHOZKWhGMCuOxadv3ROUvXx3\nAD/Cagbu745HyO8IF903u327/Mn/h/ByFSvaeKxntyXf8Twp4PvDhFObEgmM8KlkSLXzGjSp/849\nMVTIK+4ENRqk5TG1QbvelseP9Z26fUs5woWlB5WPfNex6G1uSyBt0HGTxkMTldvLj2uniyRfbc0s\nfeLifprh7NAQXGPpu7jlwKIzX/jPkp32BjoyNZXy7zLDNOMk58fHtjAbO+mNnYm58bdP7BE/Rg3G\ntBtoNqDmXZTltld6K81O33oawp/TPmWQxG58OJJvzi2favxPGSNHELw1GnN81UKv97eKNic+ZZoP\nvqmTk3aUG8HzUR0O2bslwtnYYU1Y+EGJBIbr9c9aA8Pu6A0FIHfHuZMqow7kTkTO+XjZAcXgo6gQ\ns1ZwiBi699JWVuABJP7gYICodx159b7TPpGXCuaIarqtEp+QLqWDfT5h1RnNbu6JbrA3Zz/kl64r\nVT9h9uQQDX4iJ4FMFXi8Plmziflnxw1B/62MHvMBPte8i/DNKGFycq4bY8KsdF0Uv3kZt0wfZGke\nPA17RgyGVlWXDHyTGc99dL8FN6f6qG8BbmPZrnaUDZMTnrcn6d/JxS56EfpPksh6U9vc8ZIm6SID\nNLNGvxQa6JD/Y5VbViS7828SljuW2MIVUGv0mo5JmLnPrco+jdrdUKuX1qbPE+/CpMgtCiSR7Z3N\n2Hco9fzPn+ri1rYe0ZT8eEwz9+dQnkoB6vZVaaIk7QYSoPKpc/0zRZhHzvKBx888lFBwToeC4axz\nPiISXdptKuyZqJ+piJ+oMabTyWiZiZSU8ObVTF+yyXT8jgkFFGFFTXgbP+KmPmz5NPkeOvXJpCGj\nixfGXbPu84oAHI7/3JGQ6gIwatx91GbNIQILKKpXOBe1BREd9edOZz8pnTN3o8sSaqM1/Y9YdDyB\n08eTek/GXqjRKQvlc0w4mIkP4N3EcPUiuaFg5FaborWYw6DGdkhiWmeJkmlQYuGBtMy+E6j/60U+\nEPhn0JxV7+LffLIPFKpkw3eMyLcNIfx62Uw2BSM30bte1Uv5PA8uYXgszJh+isKO8qboZF8V6YBg\ntKVdgUnY04KFwQBBYhyTHAwQlxUXY02nQ6+ZjKF1BPG7wjCzgswI53QOh4OTx7p18/BNHdBjR7uq\nq7jic8T1DUYubz4nBlrP5p0KWJyliSO/4sAaLsh0x6np+ui08h2spGaXqzxKkvkAq97w8OIIuLqF\n2g3JxV15DO9jK7ITG9f95N0xyd8NESJ5nEVaE07xMwnS4PY0qQPE4UzAgUJCgRiKWKrfIWPWkDmG\ngPmOfB8Tbiat1Nxz/2/cRfjNhJu0518rmnH/GwerBYSTyuYOnc0tVozUgv75F3hqfA6mLGru5tWR\nq9SNt88PI8clxdI9AfS6SNNk0jmsa8LGZfGMFn9w1LHv79a/2o0YfUYyRcV3e/GUrK51Ra3EOge1\nM7jh0evHsRfkeH6idYjBFXGgblkg+k2zgFkglJBbAdzbvra3roJRBAH8xLPHTvRUO3+eYzfL7hLQ\nQowNaOSZgFYEVJSV1PbfZxunEEnz/Wl5SBWlZCs/2Nl+RadpB3uvFYEyR+DXAqqQx6+sqvzCFQ+4\nvHqegPRHfgDHYLvbCUJSWSbwW6keWUHAojbmZAL+D+iURQT1isfmgnecrFrxlEeTfPm9ipgoAIwq\nJ77Xwq585ohSvdrGt7LWJLFBcVlHPhWHEmUA/c9vBKkBo4FwMVkVcQB82eyRieiiJ7cTT21QPU85\nk7Nfg5OBw8Ge+r7Im8gAVMj6bGSZnsGeAVsvKzK/DpUrXeb+lzCMNTMIwhP3lksPXdhqWZYCEoIh\n8t8iZL5hf0WuRivHTf3aYapBdLjkRP9+DMqCVk/YZE+7BpIEW8E+GwgjS9mEHm5g5v410OyjDCgt\n8FJK0rrHL2TR/wdGa3biPubE44EkyhvTxcirViqF9L/fWJNftSB7ruQwONGziX67NPKoojYuVHr/\nSew9mbO8I+qRnf22cQmaKufd9XhMTfBAJZwvSoSl5wWHCjvzxBqSQKPf5XBn15a6W88q9ur9OGp4\nFdPNA2Mhf6Zbx+xYFzVclseOkKUHDl0aKfBrbEhVRBZ0AFszjBuwQcA2ZGxtjbN7Uh4ZpzNqmeT0\n1N2x3r1PVoLSZ3oA8A0U891yqyGKgnOBwsQ0b/nF8/L5U4My340qPxn06NFw97Zvvtw+Poh/vZoN\nBonhsnsjRBLBKJijtEOSG4BPm1W+QhpFmsw1AZU/i9LNa5eOI4HHofmieOjLZlYrt+yNS0scnma3\npmoeCz0gRvaucUljgpangeDmfDUho2R9C76VCu1HdYFs2Q71bImlXo7k78MHuy8k1p4AVef6djDx\n4nJxAUH6NOv1WNNunS3zm2PjDIZTBTVWUExNipOMVYX0b0v9Co71b5R7+cPPTigVZyCQed7AFQy2\n1NXEpEKnNxyRq1gq+hNlGxYxjJVCzZTqxsRacHSkwItgk46Fig6s3tbcxmazS+mKZa4I9yimDONx\nvzklN6c/MEdpnmY3+6lELMkZAFlAuyoU5VRchBhE4ctCsQNrKs490WNBCHbcmg1pk3ytWqM4UTpY\n5Wvz/rw5ByPkRyUc1RNOLYE9Xa3LDqjrvDt25UXB9ojQzyeJYPTTnvCIXSUCJz1oqTQkv+iiEFRf\nN9bvnkn6e8mtpUJrlHqqlStHxVjocIW1hb8qdMj7Ok/fzsORlHBDa5NTGLpt1Qqbh1INYVVzOZw/\n+CsXROZkVR8sW35f95LhPDpCZUQWUpeREoT9TV/FC2rNQIaCDnexp5X7wGR3c5w4mJLVk0lbRgR1\nJ4Ib7Yi7Ystgw8Zl8tfj3hKff74TVC0sGvXQoYbvmjpnf6Kvl4iwzSdVi1KzvjzxHbZD9sVX2rgb\n8njOYweGvhHbXNsqjfg2dbIxJRhLJY9dg4Nm1nj1ch8cH5oGXSZm1tqGHrY7ssbvyd+HQbHoj2Ih\nCDOjpyyGYaN99HCaueTIUknYv1Sd5WK3/AjlxS/XfMXM0cS5+MICuQNMls0DXYEC3ctGrErvpJwK\nE25lPnQlMqDK8geZY5XlWWU+JFJwz88+ZV9XHmRRmd53W3ERHylSt2R46PfcOWYeQEsGYejTCV7/\nH7jteEhOyir495FSOuyNyolh+maOCXZeD994tBvp/dxoEwE1qCtvYz2yB3gOdoZs9X+IdO58b2+p\n+QSBhYbQatbLa9GoPepWh2hJ/miw4QNNg/VkSsh3voFdF+xkXWRwfe2nwQQnV3/s236/WvgMySzv\ns28Vb6x1fRQVuONC4lpY5kyJFE4lrvVmP+DUmDiFs2w//cTw3CgHpE822uVOIsrQoYtkJ/SyiRUm\niTMi97/SIK1K6XGKkI/LBcoLgablpDKLazvbUYnHx29gjs3uFAA5sar14O3pjgmmvngDp9YIKfQc\nZdO9y77BKkxFzY7BVkNZMv72O5d1b0zlig0lC5zaT+9GtJi+I0E52LDMhP080CH+avkX/GFpdDIP\nSLTM1W3HUg0tFaZqwLGvWWyLXIJBG1Bbc356mqS5gWvcZ0BtCpzj2epiRhZppX03DDki6VJWOIdz\nQySjoyd22GHnRlJLK1gKRIjtBmfoBQujvvtNNIjtNhpwgaP5kHuxJDmJqjKtmRWd7tErWdMtVK6r\nu9iBl9BjEboCX36Cs8tpNjhHNLlTbfDcB8/Z19cLQKzXMIQTGYeg5kqvoASq5x6SNyYQhVpK8f9P\ne90lM9Km6SZArkgxF0Ymw/LqwI34SmtDLaGX43KDa4KCLr4m2TFgOYbWMsQdjr20HS84W+m+/aCK\nBulTdfVSfa9+yxAcnyhIS3z+NCKe6Mp1w0NM1iwyGryQUtFQaWwPvhozqFJxjW/JMRjwVQKQPQPW\nMWwMdJgidewmgFH5yS3ygWktIFoxJvM3T3qrExqZ43d2uc63752zmAswjihlp8KLnrZ1lN4tkwd/\nv6cplOeRvRn76P11JIOqvdoFeHMXx9YHmfzPxPt/vjsZAHyumqH9fXV0hadvka77wEY/qx00Ob3j\nfJfTGe2p8FURdRo52huT6LVBHWG4ydtMrCX93U0OHS5HVr9+J39vDMWr5WTQjNW6d8UNnxa79A1N\nT2Aiu1P7hJG7jseuTxF9QWyfuYupQcgL0s5bpK0pKdN/Q2kAc4cLNQ2wpeDmhT+rrKOrx5w+XKJ7\nETNMG86ZYvKnKSZAcMHudwpLJP+oW50XN4zOsqz4d9QDiZ2daXvbfKzkUjbxbPHR79dcJ0abnyUH\nbMWAj8m5GUkgYavDcTKPejnkUps/mhJxMZMmAbOd1ha09qqpsVH46DlXT/8M19SPOYdnZZd+84St\nh5wDIacEuqZ1AMION7PEB2rKrWbmPMZRJ6p8XswSME87Kr2UQ+Dvu6JkYFC4Hmb9jAN/VhWcVNgK\nAe59JN/cWwRuOQmmT3FNuAUPL81vIgUBpKn5KmW7wVt9xJhYbbdMkchHAApvv9l3F+vdPkWoM3Vx\nkzKfW9g0BKqD+US8y6QbAX3NQ4KF31O29oTAXgMnQ3vnXyVGr+nEKtu1lfRN/VUwaxOW+ACiYkmk\n3iuPyr2C8l3+4EJD4gt0s1lwZ9I9peuMI7PzCYFcvC1JLZ/987jbOeeQIrcAcCifjEYnTlxgD9IW\nxTEwoJWJfS8WseqpxIBug228dSFTYcJRh+cKtLOvM7Qy/ZFfImsPnL5kX3mUdlPn4L5HDzs3wmLr\npE803eF1oEtxWanMeiQq9khdea0FXn/qR95zjzyJHjgv8SN2hT49ZOn1e5UQNLxJqM+feUDK7v9h\n57VTi7G0Dwq8Junor6gyQQkoOdhQXbDgkfDFg6HC72k7JaMpr5eJ+29MD08t2mhS3aRn+0jDzZuE\n3quRKI1S6YDMWlOGZrZV7Z5QSoVABttrUIA/b+Dmyx044T7lcu3+BiynUd66Jsh4CE2sM3WkCtoF\nKoTg3EX62ZnpTdLlndD6nZwwV/HQO0cOJCnIegebfzERvJYaImuEQvCVg4traYY79eecnGhI820/\nntBVeftcdyUizo7SfFgcvBwZ5H2fKTn3oQEG4S1iNbpNa6jivNlpSOOhmt+2Iu6jyOhpEbTzHD5/\naCCSRnyTo2INBLRsW/EhEtXKirRrPG64Mjwbxy8CtnsntP2Ua/HCCma+OWpAbqa9PqmRtbE4z+Z4\nQvOCxcbz9jh6RNlm/TeZ5aEaYpKZ+lOpUY9BnfZKtQG3DyKYp9YHlQuGDDYqg05NvO1S4pLUAjGv\npSkHtFkYRQUDOyAdQ26syxHqN73WuRu9nJR4r6+IWwHJihpgRRo4v3mMwbEuRbUQsSUJqTrPKcVm\nZ+0KWVUnZe85HvRpUDhvQ9KMLm9YC6eMNiBJbNaeCRIF7r4xXCS+iz4Ceexr49zE8GpoUh1af430\n//xSq1StxBfI42YtzeHJHGGZFaEHuQZbiLMQss5BEYqmMSY3/lSSLEzWcYJXdgXMIlQpdiJ3c7V4\nOVMTi4ICoykMbaxD2GwdLzTJSMpqoihMUzaSrRz0rcR901JwCYgItZMacxoTT3PldUiIoDQCCHyD\nOXZeOlAGm3h81UFNZOItWppwSbjNqia5R93JXN4qof0ysjFdRRmEby5SoLJkrsLEoDOygfRZ9/FN\nS2xqQ18iWZz6gELs9NFfMx73pYIT622iUc3+Ufy3QrwQPKbHjY68VqVCvVHP+M315LRUmWdmP2K4\n9Oe7nPqu8cR+QgulZP3Bxvt4u4Q9HkxmT8O/uunskHgSSkxyWb/HiP2PVMdJm1+A1DSPh/Zg5YBr\nBlUMOWCtF1lSMD8Ixz9PlTNCi9qIRP/62h30oKiwa8xWrfwRUpNgQYXYUxipx8L2r7WsHTjuOh0X\nI/7RJsHXPCj1bHc9zEly9r5l+mKP82fj71mGiUiWvOp5k64fG6KCLhOGlKuORljyLCKkfq0o/GLY\nlbNMMXUl7Q++RGnL2e3X3YZ/Ye21Y51Yne+Y0VUFBJ+6eVhro26GwfMFgaO+LoOphtLjaOrhXKEq\nZrhX8/BQ2Tc/NLZELBCJB7GrnSqTpRHT4emc5qrUr91u0PQvbcbDT/Wa0knghH7ltT6t3UmGfOyl\nJKKJsD1PpaMi9CUvNXB39o2WZamgGmLt4xZZIb0TQ87CjD0iO3iCFchP367SliTaqClgMx2hix5D\nZwWjFXygHiDalQ5WB84IG3BaLnUl3FnhcImcKJ9WKnfeNKppCy6wNhuzG0IfGH2dVH9puWQXwHUb\ndun5wI7GhuUtkBlpkuQmh1tg7QdvWh4FOlzwkRHc7x4HeIoWIt36OJSemI2JaR8b75nTKdMlm2Gz\n62DqkC8lCXswqzjuLOmtffEHJiOwhxqGqeHaqUpYBI4wIkyZ7elo0XuwAHKS0Jc04Pj0u9RT+2hS\nvUFWD4My1q1NKK+Gy/Mj0eeMDvNRXV7hxL2f9aSeBVEmUhwoM1XRXBbPxu/L5icAqoXPc7U4Wqen\nfsKIW55iP0MHn9P4ERuXe4uRdyuJEgIAswLLSz1YtaQb5qeteDA0jGUOAhBwjjen4PrmN9KmmIM+\nw38VOeE4WxwjrNZeOUknWLHRciOqPBGErU12weMBBLMlBU9qwFxz8cLuPSnMVD9nt8ZFOqWfsErA\nX26BMah8bPrp6beG22EYJ+sd+dGH0VJa6biY7IiIjG1xyGP43qyuhbE8ARUWSQZ0lWMTE2tnSOjF\nJHlV11+jQ44aZqiRvk0aTb3tMGmv7oy69KCd368llaeyTiAptihXhmp/fwEEzokx7KW2cYwvAJ24\nEtH0gbUhpxb5zMCmAoxP+H/xJMlH0hcRMRKuVXtRx8N4nVClVvR9U9o7MeErkUkt06RsNF0HJJGu\nM9KsQ9ZjJFehXV5+bCg1ekoS4S3tqxROWH3Q+NVPdzXLuExr/YAf614c93pX5xU61UHn/178X+7H\nv/CLuJfelvx+8EzGtGdPKFOhXs2o88H8o8+xC7LnF9GZijMjW9+x5sE8jwc4GccqVpO8pXDi2FBO\nrugepGlRtteVrmIlFQfPwJZURl1nINcW/tbjTGGus80O+HKPQ+Qpt4rLGj8KbQRF7oMh8OL4+qYb\njPY2kEtDf/u794jn+WkwrLpCma7FciZZKeW6ihPhfBPnQpEn1NuhPwf5IAryqAzXHr+TynUaL2Cj\n7lUmSrhX9shILx58+m+82H2JR0SsO1yx23IUm2tiYeO2HBwPkF+OSbsbzaObwjpIu26ofQmFeDAe\nphWMp0+AYd2IfH30lMwGHODM/0+cqCF0OaRJXiAN88/B498jEkPUb4d4NkcgAt4+J8jHZIcVMRno\nfzdV+i+rex8onXuUh8PmS/lv143CHW13qwVy0lClI0aPKBGFGrxA4DFd4CkGwNy3188XP+vcKZa2\ndKl1J9rc+ohMjRcFx0Q6yKpzqKtbgy/9grCDNwrhdY4jUyEBlSeBUFy7/hM617eFtvvI5o1XKzgL\ne3yHn+lU/RDDnJf2qgcXHyQkpHOKGRo+jy43Quzk2w9Cx8N1z5dv97wJntNiI13RRrcvnebvrKDM\nNhBZnCC1XVOMwCU7vfed/8zSfGwL6olVlJYUeWMG/0mS/k9F7qaRtPQ8zn396aHLFBrnK1YnIRuh\nGAWokTHJ1e0S3/Gn11WhAzxutYXD+j0vk7JVpjNLKT5NZMnl80Ud0bKAc8AJ6HbxptV+7BkCt4WK\n5gqwq04vPlBxpNL+GmOy6SRqpekqr8YfEf8gzZzU0ubCOGwMt6JJHD+hUuwKlMQ2YDlAxPb+2rj4\nrE13umqRhZ/xhaXblyyiiIgJa4YhCekc05/z1UI0lDxO8cYFUSVRx5c7O49kXMX1AFIGNyC2C7kd\noxjoPyLOsaBCrisfs8L/nbl7OCK/cGlJAdksd2VctBIFdAzMug8WMSfBYwbO/D+ZG/cAFeIUxS4+\nFRrLWYowxkihskBIj0Od68y1UII6uldPyS1W7+E+7Z09fEOuc7YSXDRolcPM2ysa2f0qnBHM0zYJ\nQDzLPCHvDZY+/WoERX0fDVhDUL5MFyDRzy1tqLv45y8Xrvp1KpsY7lsgoU5h9mXR1+vYKaCkpUSO\nU/ldfkj9FtqzFh7o/CfCAy4H+tCefEGVqH5KWa8xb+qYzs6YC6c+MDJAGubkYzqmEAR2wYTuy6Es\naFiStiBeRYRLKOxgdIoVi4QiNrmtx4KBipJ890YgYkNqpUecqOsP7pOXISjY045EG05vtO5b6MF+\nTbLmpDKkuO3g/BZYrXUSrfFIGY0ZYze4wisl7/noJdDL3OBAgsu4PH2FshmJSVOQH0OmpKfMgWpm\nULsZ5aWH4yvhgypiKUnWmFuBoElnac4OjbC6mUYUKLoQo6O8bDLSa9s4Q01EOw5+kuLF8TB2Ake9\nEA11vo3nAfDYPPhrHUKlerheT+c+3mvcrhNJEHvzIRarkh8gA/JkmwGVvduPpwBfYuYc2lsMmjhF\nIbRrLYIQNTlIIdd2jlBTuvP090WCFdSEtzGoBFTBM5QW6hVr0+tjr3hCDwnYT0RjA/svybkySmG9\nEMBAMXw9nrajF39HE5nB/Jqkpkc3aGoq9aMRbwtYQNCcFAxt3Rb5DVpdgvNN/Dmic/HfpAQODAdA\n+BzpIjCkQ7TlN46tj1XV+4Ayov5ZYtftoKm+RaApkA8udNzwUSALK/9AL3DkyoaMIODMuaDy4Ewt\nDt7A+ZdNBujyoxhW4r3Va+tDGbtmPRwjDqiNfiNR8LW5ihmbQxGWDhgDJVHPj6chxBrfqLWeJos4\nCnED1f26jRThfw4aigPcMzULHf1EtJmOoenL7VlQglvwKPuVNqCgfc835Y62OPgE1gl+OfjAUyTB\nJHljcG8XwuJ1GSYN/jzZ1gXQqcfRRmlnymoQkKukmb87E7tXqTU8oNBpKbdJIq4NuIRJAbYLVNtR\nrjtg7OXWTqHtJcF5CFNS4MxlJCXUaEmuDA4q7M8/Bd75px1euAqaSLBzZlt7DVJtRubW0qVgigD0\nOvjbXbXe0sNf/lTpN8yG2zXTMXB7TEo7zCBWrwfV7Bm8+DeAyi0xByHh3/hZqNpGHgseFl5s8fPv\nwiyqaWBvnO6KrW5NtOQsk8+MhkZI20iswMgGXvkP0Cz1xZfL7CmLT40OooXtCNKonZCCgUUTdfZJ\nYtRIobqBBjT5M5rLDxRxfUef9XwR8ZpLJCcGde8Z1AUuCVbyzswg4VY1/26KDo4ByWnt+mDyoWEs\nK1O7U4kPRsiKE8l9MjF+Wqi4+fC1A4bt3SHrUJWRIS/J8CWJNfPNe4RrzQ559og7931jshCrPfuO\ngEDElasTAwuFznONfrATrr5wEER6pQptEiPci1W/O+v3XFw2Xa0Pckk67Ru16cgwKxvO3iJCuyVq\nDKYfWBHVYabShvYuHK0kHaQwsqVHxoFJVYi79AzwSeWXyx9wFd7hOPpnE1qEaZK8qiibupBvqMYJ\nn23oUNdM26/JyqCI7MB5UlvYsAbHUQUQ0ZmfPQjyCydzXlM0X4J+FVOwv4lOAQcjSNSCDqCJp61a\n2812BDFl4e625drMNBfwOAS4A7zmFKaJ3M5GhQPwI+fqLHy6KSX97GRDZJ//Pc6tXjdZbxhx7cjh\ns23zVDIffeZ8PH1IiCr5Nen1NKHwZJpUY030Lsh30NFAofuHHOeE9kPhjByEuq9EA+t3vlSsdc4a\npeg2xorYsDUPH5EfHvRfqm6AwEE+mjspS8HN2kM4zQ13BBQ+KgY6qIiUkhHV9RW14gUfw65PXDCd\nvV0xEgPwP4a/U75D5p6ALLcS5iwxxU5uBtjsW8wr/TMAXQtDffqiR+KL9a65w6bvtbbjSlBWX1aT\nhRzXYZDnQqMlaH90GphQkYLWpiA3bl9pxZCkpNm5I990S30H2DmM5ucT04w30AaIZlonucE7R1+6\n4mSUoTI1Md40o68lPWOFQ81ITJUFe5GrMut1wKWIK15Af3cF5KSlTmfCsD31Jp/1PZecRiMz+Va2\nnTWEJREuWkqLs0Kc/Rkx3IDKCxJwG/3heudYDR6z2Nv90zUS3wDVMSXKGL+30TlO3JziKuavSFEi\nSsAVwDBa8s65qpP3o5p+5HWhNcCTiZ2tJfKW5DV/2WawzRqOx4T46maSX092P5NRPEnyf9lOaxGc\n9MSXUHqzQrgZsLMK3SQdGD+4c5eDRRkhEAy+Wp6HAjN9kUF7CG0wKUi1/7EQJmBTxstGfXY1fDYN\n4B5PTFCegHH1kfN3MvTr6kwRk4JX4Jc+hjjvUJ5U26M5xlx3Wiu6v1nqdDX3KrH9W8dqj9L1Wb78\nvTZMydX8ZD5MRC2ojxvdMbvwQJxErvRC7mss4dHkaNVu4fJL6Q7p0BmNH65fNj7c/htSMdu/mRu2\nj/7D/MJNCKfMiSzzVUurqIfbT5EmN8jj7ULda6Bo5iLHA1vyYTqRTV4PVb7ghz+/nFOYY6W4PjP3\nkzUZofRVJLgKK6dyfcro47+mUBt+x6T5+GMe+4s7gjDsnEdE+KOsonMwmIhQrIt4l9egXcY1tUYz\n+d6y9wavVzdHxHGLGLkXOsFJcHTUxa8FIjVjW2btrzH2d9BGuSfvuCZ7zSQDFuGCHJ7IvAjzw1n/\nYIrTGGIGmXXGA0mQkf9HU9LSFcaN5ecHAIkW/dSpSDPhBAI0qf6JbJ3TV/9k+yH3FnooSUR8sUFZ\n49oJYVbNnyQsL1h8wigE46jroqXC157uoqlSpc6RZrWCbTOqmh3paisSmE48rdkYdZ4bzCS7n64a\nDE/V8uVPekoChvA0+dSxwzK1qRvaZXMUymhqSuksFAP1XagbAswCjo9iytghIZHWgD0Bwo+bCQ2q\nuU7daybYeNf492/hsgtUMA/gM24d5tjuzDWhIXQsfxh8xkTX51sgAyoYjZwc1loZ3k+xa9u9zmch\nDBP3eGVqJEjxMKAFvl1HI1mQFB49od6QO8fAc9bMvtGiebHLkKwT+lhoHcvo6Xdh4GzSKA0MUES8\nuln2bRViD55EFdB6IEGQTxMSmtrMq3BZQ5JQZFwMZvfgv+oTiLFYm0L+S1zZWvzB5uCrqp3ff9YM\nIRq/z24O3ThZiRQ5xAbXdi2Ba6fHy+Xt6lgzc0bCrpeLBse6BrszDf5N2kXFR9BRbekz19YSdZKP\nbxE7Ftw4Lovtdxg64WQKokkv1ZN94OXtVSvAXXqrrtxnkRGY9dycxB4HEkpfo4rSC3sIeOtC/QqD\nlGAd01VPiwtTUei7eSXvMnHqIsdVEXMdwjQl9hnq3o2lFo4w1bbvJsG8uAGRJd/pEOKTz6ZqbVdj\nOLwpl82nxrdqEnq+n+lle4YkKebctAoeoFgDvljxUHHOhPMIwpbi7Qk7PNoLfSsZRiE3jkx5tH9q\nzl1LDq7YQ8+CrXCOVNmUwY9qdDe0xoi+qxmbzcGb2uuZYVaF/49NDf8OaCbLS9/R9AkGuasdy+32\nhxpBjDDV+b4QkPe2cunGyL5/w1ReDIamXNccuZC11ihsx8OOGCDFip08fBBm2TFLuWSPHbiVbZ7f\n5y/sqABEO7qGPtuvw0G1Og/WN87XPCO6mchATGmAApun/kdLIVWmUwT1kD4TJFjHzaTpN/VGz4ms\n/LQfeS/CJoymbbr5orq/NTESVz9xPk4X6ropTiO+Rk/ec6k2B9AA7TFJpt/GEOXWEINlLNE0y3ht\nqmmpGTJIZukZGddsZAcRlNj02O52J79ytSPEcmfdxAk51/eY+/Pd8+49YVj94/NM1uS5MYvVlOSb\n0VeUkFsWKpI2POkb05wdS+gLwP6fIoFm7Cy76MVFLvkDqkEmNUaWA90mMvrBhoIZkoNhdox0jKdt\nRFgeqwBt8bRHJApkdWwiMjkCiby/ZgIChsnsKiYRewWZe3roM0d6GcUZOwhwz1+rVc+VdGkH6cxG\nkDlYOyW399haC87Mu5AsJCbxASRP42693h3ZTZoeltoeduv49yWYz9iuiAH+Y5i5HMsWXE6EyTyb\nw/2CueBf6+y6hYh5Z6BhARbLiQeApAGttfmK/2GihKKftdJ/s48wDnzhWBuDeYhdKpi9IEyOFBYM\nwWee7jrF7PrpnNsLdDcPjrQ3eZlNyxxZmWYpP0UmnJzRfoNfd2cXi8UueHuR7FcUYVUILGjt69RY\nPtp11jkv6Cl1QzR+c8a+/zc3w7HtbcGcfm56Md5y9PSiIhWcUCbByV+2wt++i29owpwaEyjz7f45\nIV6Zu49X0587Fe64IjsNU3q/LmThqB2l5kyFXNsZuerfq+gzF7AIf+k+8AsqwsSPq7QjkQhBwTLY\nx9W5qa1oDWtHlyEuiDYZQQyxYLy0Ce/ywS9APzcLrDJ575aVQjWMX8Z54i2gnyDhOeKfDrtzymgj\n18WwqQBWfNYM90wAFOUrhC6LvSNOymi9ZvAWmyut/lH8kwYHq7s9NVh+Lf/guiR8NmMQRmjHiZPz\nfmxOS3aRQkU93UqbnhmbAS0b6AXpJkmGP6j6TSlCpbiAbLYmVv/L9q6d7C2yIrBZyO+XP0RF9XZB\ng41/sMmLTJuYXx8G1VMuUq8ylvSwmCTdQ/WK+eDipsUlrbqom4LZB8yAta35RR6T2ggKmckKvtMS\novcj8RBOqITIqjTTgBS1QZuQkhaKnpSwVC2l0wGTa0zC6qdQ+45XHnfKPbZ1PPGRfkl04DIRrk73\nK0CrqtParirOybPEF+benS/JXXyBWAsbXXzqoVbZfv7bWhQhEGQConkESVqniyPW3g7iq7MVwrAW\nCov/U11WHQuxvNoAP0xlNnXWaVCgg5uFlHR02WsusBcUzHhula3cMGbXzspwtuyW1Rn1kZgS7SX+\nMnouLei/a52cZ6OaEJomzPq9lEMOH20uKSUbZjj4PFBlEXhJoxYjyVKhXTWeHxGt6FyeTMA9hwoS\nOZyBLBP5NoZzlMQ5p7dnHIT3zZg1JEv9/gHNI6fTt/P3xHQzuHqrhKJU27AO3jhHHSwtwL415+7Z\ngMwGnp0vBOFJPdqzZcs2RccJdEEBAzE+1Oh1S0BsWHsq7bRTaZl16zU9euhxnXSb7q1JoTwBIYu0\nNHAGUFt5TL0s8bsOPDrrAh3ifBn1HTHB+fP1AI2j0dmfH6Lt+ofXDDHKbXH0Ez7N/nhQp1r+D0qW\n+Iqd3iZZEl5nvadgpt8MgTRiw2NWaO9zDe1A4kOgfkDlRZWXk1o/sxsuqTg4iW3BP6YMsIdFB/6k\ngYhRZAIvJGJfcswRjEoizVzZrgf/QEaUk+EQzEwF3udBULzBUcQcHZyIvukNV7Kym2pistN0KPle\nr7s9Vg/mCPLgMGAAH0j9rrKjZXrVRSgmtwcWi5TdBahqv0T2iDXOGg2mPBcDT/nMxNGD1GYExAJC\nEGByQLHx7M7DqFM+A2xDmoRDYSW5HZ5q0fYgxRKK9Q+7SZf13giWH+hf2Y40wcQF0AYpIh5Cpe7Q\noSl/VUTAkze/wY0Rm4f1E17i/jEGGkPEwNudQR0+TWPejvk7yNn8YGsblBD87kYpfWHH67z88AQ5\nmbbb9haqkAOCYbS6mUenEs3L0oroWUSTebtYIehAJ1KaK87/T2uPLY1rU6ui4Y7VxUJ/H31jU6pF\nW3UoFVEfQXnPQQHBzNX3VDlBLSZS+NFbFf8UH6rx5Yq+leQ7+/Xk37L24k7rdT++mXYsGABuUm/n\nGInC9W61pafx9O0FVLFBlWKZQLLtmozfr0d4JnuqM0jzd78anX1WJ1R0lPanj9Y6un6CIcbZY5Kd\nTm5h2I0KZQdC54H5pJL1wNZAr2XEYXF/NTlhbk+ptuIidkVNEGq/0BxKlAeOhjUYcLsDDROZOwEx\nwEoFlv7Xok7jlLekhC++AMpVAd9q0AcCBPGpw05TAnooeZuXTDVUyKih72bIu9Lp2/XvQ153rNZC\ndCnU66N1QdnyRRDfuxf/3lJjH8awDq3EVLA5KsJPjw/xCg/0opovvDLtHqN36djXM0Er9fl0Rubz\n6DLrwdd1kOc9EUabarGL0FOBtmAuH2jyu7gskTy7XmLijJNNckrQ/EqM3XkRpm75BKuxwrEp9Hxu\nvpMrMHkJSTeOdHg2dgrWI/hClNuu8N3VZRqpEMweIIcJVMhQCZTwLSjCyrJ3fQGXESRSSvf9HTvV\nHUQ+TA932r9vTqn/Y/CPLne35SzGzDd6FGQA5xmwMqTeIArXQ6h/6xagrwZCgVNdAtvv9ZGI8YYC\n0MG1vhrNWwqiE+zGMLvmVRue89aBNY2LkDZrHtfgUhgjLlBPrAI6qcsiu4AFecPMtyB1asP1rzaM\nH1NPuW9NSy3mbII00m0iAG92kNnjMMbFEk2tHxUJxszB+sg5zGf7urCOPBu6Q1DnhsP4+Md8xB2E\nK7js6E62Qa8dN+/mmYwQTnhldxGwL9ZuX4p/TC23HhByiDG39Fqpllpn5rmBsVSPSaBpI90Dt8TC\n5IuCyDCLN37y2DG/+MAJ5daZuBANknm/r6lXwORzoBgjT0QjTx+XTfBCQyOHPR/OYlcN9KQRZyF4\nQB450JzxzAOgNcfyZQ+uo64U9p7vsdyHAIwsAgi4sRbTssZhysh/IR5JVcIdb/SN1fuhGtlNFd2B\ng/10iRaoukpGOcdhCeA6nl9Lwqd4INg5T7VmGU1K0/RCUpVWVc4B8FjfMphDyMCjoWPhL7v5fpJZ\niF+9RBSRXg88aovkC4Hw0TThKAoY5D/j6RDmLdP6QKsw/MduQ2lU8RS1KyFvefRlhXma1UsLXGAc\nZFy0R2CTEKiO51EvdO9oM8iBJV0Ls1td4kI5rP65IAAvRxhu5vRF/kayL1eaAOaFTksha+6PnSXJ\nqr82ilVaHmnsco+/wX62IntW6mYDF2Al76kTQ0n6gTY461nTKH3uassVmVbUGPNRk2UgfxLUunNS\no73mmo0yRRCLnfsht6OQvv/ug6PGnJ7JG1QT5fNI9s0C4tau1lNV8a5wK0dg+PoSZA62kouWwdbZ\nhUEoJYtOPv6C0mLuDUn7CHcYfTj9OS1eEUN+KkTiNX/MOSu3HOZa2/fCtbIg1AIAesywT/BK0+Op\n+zKBp6D6qrT8sYd5PVB8ZXUCbiIajkNUIEA9tREYe5Y97IYmxHDOeogbmWDXkZlRdVhMJslXcnww\nrgRmLTDhkPXMD2I/6CxC1r9W31vemvYK8cE07wwmCPWtm4slB4E4n9PChxB3NbHUGELOYBzb6/jW\ndo21YNu6AfUOuBL4HwmwT4KAV3IqnSaymSn/mUMckIw7wdIFrHFukb+ssFA1HIs3BCSOpylJ8jnl\nCddGxSU35IA3j/bzWuCgbRL38pgbw+MW2A+FEVKp/xO2XVv2KwNPvc0+OfgxwriWkCLGZz/urdTn\nKUAI0ruaCp0UohgwYbCUN20lq1ELQp2Nb+3Z63np9sa0BHlEdytnDc1fKwCEZaPneYXn+yDiCn+R\nuOA+y4KHlcreosOynzRA4CS0UgQ/uiBips8SqwSkMQCmc0mB3Qkg1aE23TSVuKpwsehrFibIy+Sq\n1ZVSifEmsCvULOKWwf6NhLX2Q0Nkh0IuSpH1m21AYmRrsx2oCTHL/vTwt2VRvXwu4BjPN4rldg8e\n3TIYnVzmpXH0GAa4o7MzAZmnT8eqU0APzB0A2lhuk+Zhvm9YkBopIOa0ySt2IR4WFaljAU9gZhWd\npbvUXxp9G/RVUc2GieFoW0LsH5dtFHmB74ZlzegGvz0vRJ+M/Vs3woVFte3lkeBnDSyMepSJD6D/\nXBwEfk48Zf/ciqebGht88JMU8ipEXunXYbLNKmAYtwt0B2AnKZtOH/4Xl5q833fvOCSE+XhC6aNY\nbFV/IDxUrLrikMf+nf0akO7yyVZ9oyILKrYfVYFnTXw6NrMts+B6aIWVm2ua5NxF+lC2P6pzhyTz\nhWf1ZeDeDu88brp2iWKEmEocimVCg7NxJR/kO/5ek0/rvxYykKWtYH0lCiQiIQUtlrTvzpCYuNUJ\nZo2RwlgNnrX6MUzem48mJE3KGycd26DmqUfd2vZfcuOwRWvR5yNK4z8RNOqTolI4aGUhNLbtlJTC\nojdPHMJ2v51H6/bQ5Y7/14nsUrCcbv/G4fOYKyxvH2TFZyMDAp1lT/bYpwMlIe+qSMO0fuuITKyO\nD74Sap5DehfdnIBhePhxjWAG06z/H+8n1N3AUv51n6pto9ed9uxtwJ26VFAv/3XKvqk1DfC/kwpR\nSo+C9mCqO7uE54VeasQTe+/2w7DPTrqUjn/HKuzY1kxloPSdjhd3gp697rcOnDnbjqU/QQA3OlFn\n/SCQfe8KGSFU5e6HJoV4sk/8XRNjEGSwBUUkylShIqaWOeLkC0g7+Dn09O2mIhPOVjxTWxKw3z7Q\nfejlSn34ZPse81cuiJXLu6jv4AK7YLF7dTVN5RskNzUngkeGIOR2HOlEQzbRxDTX8ReIMKtAhWv+\n4+zEN3HSOa1OGfrOGv45/pO/o7Yk5Vae42b+fVk2FdP/tmCLBANR9wQm/FOkTSsce8+YCEaQYLC3\n8gsYxWbDPuhKSF78vHtzHiJtG+krJkTYEwiQZ5mN+UaOAxK5G1qwEHreuIgVktCHM6J6fUfZ1SMf\nNm3hV1MYex/jS5MtsCYshplaryr6+5osaSD/JPgCglmyFtoNtHn5N5mgKM8Z6WcjoQKCTTTzCtjl\nKJ2CIP55xD6Xre8YL3AUg8fa0W7qav+DxBexGMlK/nO6ODfNBGTZIkJ9IlzroquWfz6ycPQo6zqg\nisNknrW2hv36TtU4903XWgMFRK91i47XuW4PpTg8NTuVkEehMT9KBOeyXJ1Ac66pA5topD/0M21h\nsrDNiB2ahJPMxdtdDyKTE9Dtm7GmnbhuTwo1JvJd7U5qLSU+nEI2o2CgBAe/42FOwqZ8QZKk/i5/\nWdkEG0+/MKxqNrxUfci0uyx+n7ufuc1McS3r3DM05kgrArtYw1hd6e+cbT1Qh+fZc+a3KsAeMHoE\nle4WHg4LJZZ9qxsEsYnuvusZ/CWBM1hFHffpV8s6dG22MS/ZnbwG22ZCDhBTMeUB7KxVzUY8B+kg\nWn+uUdAVJ/oskBZF77+ehZgjToUbpHhDPeux3W2x63vVcB1xmMNrqmw45FPOBNLyjsFQmlYkLK0F\npx7FXPztGXoLB8OrKm1MIiGfl4wnOU4DuDD6ZXh39UOiADc+TUJZgY6YVyBA/F2fDJNOnlMrhaJz\nJWXUJ5Fe2o2e6swKQaHPBLq/3BYtGzzK/LFy1qQ4wBjMMolQcbUhSOVTG4YGnTMLXXbpie/Edltz\nmN/cK5wZRfPBEHTBob+P7DyXCR9XFlPyONYpUP9OMhYo0HKTwv222Al3iO8hcRyvh+wCG8QHK/+W\nLlhcjUf3LANKFJd85C0uR1YArXXKLbeaOrK9uRdtpXgqHEDOAzbvy2imrILYGderj/x4xe/YM/eM\n8v/yVhIy7qUJtIuEpAbMjvgfRapG4mc4iz49YiI14DraKZnfs27HfirW+xQU7jVc0zYDoFZoZRZv\nwEKL4gwKzDtjIfgslHVPe4nWwVKCK93uQSvniZFAiL8t4JDpekmIVieJNYX18qD6C3GvSJ3cGknA\n2FgAZf/YXbiB4beI7eSoy2F7i5QMgI8fLup28hpq/aa3IzUU3Jmn3gQl+zsXWYgl+lVCMNYGI54y\nO2jcuPWaHX5zcwI66LypodPvTNvwe+4802WWwMBgWbju89QdGA23bJ7t9SKwGQXQl0zRKDwKcXIB\nRVcuvmY7Vcn4RkZEuhgGIT4BztdDzzzki3B+wA25mC50pGje7VnLiYbN4Gr1FBsBB1DHRPziY68e\nWCOeWrI6k7//qhLAur9fMA8A0GIKTQuhhtBjsjRn5ZlfzqQL79TqhSB14tQOMFUqqVijwEzp8mwp\n4eaPCmv3o1wXHzfXX+NGBM9/9XAxZq4BwZCNc/Td5/IseiKUvaEnUQ+dqVUtkFnQXJVyEihtQusv\nCxdIRlLRXOe8q37l3tGHqZ//Y7a6q9V31E6E9C/3h8BZeHaI0r0UF76O7Ss0eVjnIWP1KcwZZ316\n0CHiu7Bw3ZtMXFL0+ZBORD1ZdgUygy+01MR/aNhXLR3yH5awNJ239iO/y0g9JQHcjOi+BcI1bP9b\nqUsnriFy2TVFPB5iyIpLgyu+KCJt+c/xZh8UtC+kGUoDTItCgWS3hSXM0fpKpA7PPD04usriWCGc\nVuDNrPkimu6qrUNJn43r+2P517JmFzsLY1ZqCqfudtuS5WVXvBGWhogzStvUNhKYJo5PL2eKTuFg\nspeQWfXghrQWjbLaq+LM572IsiZ8WHILm9sH1hnGgLT7RAkIL0cXb7ipI6QxHJQY30ROtxQq6yXy\nJ3aTpT7T+S28y/ejkPDUGQ9HnTtDKLGBVcEIYUmX92GkjvUKcknx0+A+r77ATMftrvofhKPjaTSR\nttZJhnjG+86aul7iQTGam/rzee8XbbPKNn9DKbszHDlIJ7y2qAVK2n3Y177iksGlNlvPFgkl897b\ncQ2XEUGUUKjkbxGhikw0Om294KWELAIlrW7QEN3wztlMk3LcHbOIZ8A6HTZpK7wi+GYUapvee1Cw\nK/LTuahc+kmQaS0M39f7kSFXY11XilrMTUVoCHGI2HA9lOxFUr4s88FY4vJcLqmP+NkLxme6/EdZ\nYoFn+pz+TNuOub8MYSR8mWSw93WErLujpfctLkvREvdZHGwnUZgXFUHi8jmlq9uZqDYx+F7QlptC\n9yB3LyDkuqML+YqodLjQ/eTk6lGK7QELcW2w1CBBtHSQ/W79Dsq7+Onu0GzlCVZZSqaeklIRn07z\nYuOP/fIGIV5GsEJLMtC8hVlvy5+ReTPdMTHSDZtFFPbBe5ohsKt+YdG8G7p/ORWOaQgKkbyen0QF\ncKmXyGWdeepHMJABI+gd0o369/VLd6nOAQO3dUVf8qsV99IGnWwBW9XWQ/eEOAhoNpuzSVBCXtqw\nQR1OeIW50x5ZTB7KVxuUH/udqM1+hXjy+9/SIb7C6/2ei4QUMtXXed5YoIFQhHmuRZrM7sk0IJmG\nY5+Av4VJM8eA8GCviVcfgFObUuIX7OLEMGcX13P6c7hTm/o0rynxWVfAMUaTLLF9sP0kr9G3onF9\nblrQV4zn2YjQVi0pTlQUfQEDDEMczaEYFv4OKqn8xHuVK9lMf8PSSl0ifD2+DCPqIGtJzbazEdme\nokNx0K+pttqvJz/6af8LJ7JP8CSeFgQI8fOt1+5QIROk7bdaOPfvLaA02xRPG2aNUke9nfeItESy\nBkQ0SWviW3/WsIxUXByN96eV3JENaR8L6onrgKkvojUo6z5r7SZ/4VGKy3Bf3GahBLdcXQu4vx2s\n3cX0U8+l+VyCljiunxxItGhLglsTBEKkev7ZdZumeJlskFoCaoKV6gSPhC1UgbKLGAFOIgiUZU9P\nDK35TBFMg6xCBKtM8xX4ylAzuwBtaGAkNu8tEy5n4U0o9j7FbaCKnuDxqfbIH8soyuoZzaikexZp\n4eukz8CEbzRhqswT7pGLOSA8ws9ZDI/MNhKJhbGEDo5qPgr28srH/5KGDjByYuXH3Z88xARoor/g\n/JwyWranct/jhbBSj7tC50xdZcGUGX2sMt12+l8T425HkpcQ7KcD6VEF1ivPOKUHewOY09gbGCFB\nXr5PnofwW4/3LdOYya0NJDWEq5LAK5O6dK1lismfOMPt40DCN4Qg/Q2QUGAjnMdSVjr22gaF5zjO\nYBPgHmSfz+pxkLTrZk/Mdcy9cNx2qUlNQsXKq3bKfCU4pld1XvTGTlAtf+jePCB8fp8SUNz7/H76\nCsZlXk7hMNskyUSDD1UUNQff6d4cnrnP+k22jgubCa9oB6fWskUiZmtaQcRNS1QuIEKktJzSWD+s\nApcBxcooULNDql+S3vxFzDHcfaJqUlNku5STGORH8ceJJFFke4dTfVjm1ZlGkMphNaYqe4T+TXgx\nvcSp0nfK0zdtLtbThY5uhGcKnRAtDMXmw20VKkuyXGt2h7PdK6GKQIQitXT12d/E6TBeOBt5dJQP\ntRcwNHWMk9ETwgVMmORS8jvxM6l2mIgQk2EYf/TKRD92ZXdPjk5Wt1ZUaKmGLQF/oXfrje468HDL\ncE9VN/RePFTRCGG7u8bZf5oXiLM8weVEfnA9ysjK6F734nxW2YPbO63lHCXrN26lPfmHMEuaoqhX\npBfOhMPpV11Pkhm3u/GXSLlhp8r+gqTmHC/HXCBiQ+9peT3gt9eYIo0ISYd4bJ7hiPN9H+OginVh\n2YHMs2GMjoGbwr8SJe6d5pk39PkNUSEoeCygCowuBW2yJH77BERTnVnEh1p3khTrbPFLyFEPWYNz\n8z8zOF9bpXwf3PhRbrpEhI42F8nNXWIzCP4/n+067i0iFnwn3RqOhLkMwSdPRwnkT0qmAz56lc6t\nvK1AHkp0GHjWD6dvJimKDxzViwVOWmiX4MNV+qXby0+edxB5amWzWUQtnTFKji98c7ZA2Dn/WyE9\njacIEsC71tccXSuXK2kaaiG/xhAao+pXmkIsqcOQjYnR18d8Gq1BXJMiC8rfgiTsICmVJL28Cxov\nk96W2Af5wQbV16bP6m5RZ16svROjaIgbj1cobw7OZeA3DysrJwvuvSFqZLHDDKUNxXUX5iwoitfb\nOeYcBMPt2knBreWv5mTNoX/Z+DHZpyjrPPkGcIkFWBZAzrBMVhbulb9L8sDaIGMOapWndlaiIcmn\nYQ+Dw9oaT2Cvl9xJJfHGs6Q2N7MzvrrKOMe0dFI3oP0TFELguce10nr3nWRPmWAMB3kioikRoCU6\nX2CvmSgXmVFosgFrDSVPgAilTsbubqnr4LHY6+Spa/xfT0bDNd7NRNQuPiy4sXztA0WoiBuFkI4s\nY1sLp/y0tKmjpsLWhtAFyvwWjATEmjic/RNldEcF434cI8xoNCyUgYhVoIcYXQn75cqBT3cE/PhC\n056HeYJErz9C26BvZcH7zgpeu+tiZ0vK8Lv2HnHqpWou6NY8yTM9d6ba9l59b2kiWAOGDddQZXIE\noZOznb9oY065Asopa+vlqSu5hpoxHi2nmDsj+PuonlfbqI0b2QVF5sw4Bn0Lvo+/nrP9bZsYg9Eo\n/QMH0u9qArUDhqiiENrrTcZ+5Yulsdwmy4Tw3MU81Jg1ogVP4+COO5JizobUiXLULxarruH6yP+N\nKrKLK6x4s2hdMKkPHUJ/ZR6ZxtyQyNDinniDhtuVfdaC/UXPSHSK0uG0z/jh/mcygaIKnz8R/kBT\nCEA5jKTLz4KkmszR8mdQeI+LKp+84oR18DgaGZKQc9oNADqzjQk/AzIVUe1tmnlwvbs4yKRRs9RO\nKAd2tN4Oh/zEEuREQQ1Idbpl00+ZKd7Zk6jK0k7j+1ELdpP/NYxukYvgcCEb92xL0eOmkbHu6ZNa\nX6JV/plvcC68kxRSQqSDmPyz0ZNIjyKDs8h8zUT6I03kgYPaKHCQd2SXfASEATbq0AOKeOAyKlBJ\nl6bMbZUtlR9O2xLTEmsA+SfFhVXK89uLOcTd9eEK+kw8UHNeRacOhtoAorh3tZbtS+2ul7E0PBDv\nkfl6fE7k5MIC8n6YrT9A6HN2pBerQDr+0kAYIRgyjck0h7RkQJqs6GCKpySnxfqzJXpcnQ3TI6ou\nEfGGPuikkq4VgmvUP08znJr2eMU2w7zHBdt6CAFoR6mIjpW3ZP5n1KzK3ccWkuiyRdTnVT6/Wdtv\n5u+ZLIwcP3gQNGsl6EUaSN+TcKp4VY02uVyDs6AW5N9entY0KCATBj/YLkykGIk43kWc4feV7enI\nipDyCVQ1h7q7Lt6i6VWBrTezMxmxP0YpDyE3vHFSk77JvC0oRB+JkJT/p5ge7TqdKhVWAqGi2OtI\ndm7zNGKwmLKzl7F8b2y4HKf2ULlvouRsM8mPxabShXJT7JCEZY0pT97hg+HNwOjDJ5a+MKjczUmf\nICjlxO1BjdIlJWrWjOtG/7ue6iuqYe09a+2pLmHSw7h2UWYpb6Qw8Iq6qY3oDDGI7RsLQtqCUGUB\ncGf2XpUeT9MIg2EmZuWh78aYTNaSw4PSE1aYI/bYF3hw0k4AO+BhdXaEixZQMHYp/kAOmwaasLJ4\n4H0MiGdR7u8g3arh4Ck8V37TBwUgeZL567P1qIG4MGw8ElnN+GXqi9qUZs3o01Lsm7LuGui6NCxn\nBa903yZiySBFXcMkYhRDozsFfZYFr9A8T2z2UhQb/M45rzBCfNm7xodoGsgvY7OC1O8LGfMbEUQF\n3DL0JQoPoFS9nBeEaYHqS8WOkQUoa7QiqoF9rNluK0VMjlQWj9msXlenmKWNH4H8o2c16YXv3ptu\nDtt1nHJrz1kkdXEZpOjeu9DNl+HBkQJxihwg9JMvS+oVV6WXkg0++JPHSHWzT3j5/VdXL3zkkPxF\nI3unUfx70MW2xNAz1URpTz9Pq87anu/JZf1Ha8tpME+7Ehl8WHbP6yp3qRcxGRmzs74YEdE4yCSf\np0r3m7kQ5SxODHRRwKIR1gX+VGjC7t6mL0tzxc9PQxKsZaxoyX82BJrkpxQ6cTsDjKBZMJpeFovB\nDngbt59FjjmtoY8rrW8R6u0ypA/+tIr/iDG3j0pszHkXjWEV1vtJEWdsRIUR7JIzrnPUETWbz5QK\nOZ0YjrOgyfqqPDfYXDYghgqee0xDiOiJyYWVEodhZecR2boqj6Tg0ZQYc4fLkT5QfV7heUMDq7/i\nSSmZZN+bRctzQTuWy51OR1ni2yBsaI/7dFh5BXSxOsqOn4rEXiyLu82F3YUQgB+fcJJePt/nPSua\nfY8F6L2vvWFHFuOqaNy76r5E89kOdpW8lsnpJida6kdqPktFnE9r+HewXNj9xsAO62mSTqFvqlK1\nNUOCx9lFubqnD61bbS4lu1h6ti5yG3NlrUXOQ3ajBC0rQWBtSzaGei1q5z1q/7JtbglFoKCy8jjK\nCjG373VT7g/z9SwI10Rc1tZd5szTDxWGPeyJTytCPjIV8K2bBt7Frnhy8b7yWLaMkIHgQqYIcJrL\n3+qNnLEk+/UUFmueoNMb8GQMpZJG+msX2Ishw7FN+DlLdG2z6moM2qrZsWiAd1HJlap+IpL4FScm\nW/Mrup1J78gdXoTTp/EmE26Z6LDhEeNeqkFSjA7uEHU8u4XLmOElMMkbvbaFJrovTfAy9TXu5DOI\ny8H/EOXXuo0WPs0Yt5crdHbMSqZ5AvcYmRH1883VB6zD8VF9b0b257Jf2T1K6MGoiHkr9DLuYoDG\nMjQvokr1mzJAkhu8VXvMGMwAPZnBDSCZKKdpfJ9m4hKDsXj/vcCwshxCUPA9t2Fzbxs2pWyXcSsa\nab+FEgbPaXFkUR1puctXnTGVCVGjWmpv6rAk+ZAFwZ2R1eVjoV75FRMcQp6vXBbdUIl41vnrbNSt\nXrpz9VmD8FPmLYirOlrUQ86Q0dpULnDtuAKJpFZZ/bLE9/wOj34gqLofMTpv83BKPFOZVqxw2EDK\nt9jbECCDi3XbQIlvrxbMfJyPRJk4eZF7xh11dj+ZHNbKQ0U12y8MIDDjGa3SSts8PmBcRICtbNyE\nVGwdwbs36fY/vxZ+DD7J2GdNbNQUnxNgs1yIxVnuRcyKjGdOutsgZJpuT/F3D9tAe7hfG6cmDzbc\n3rhlcCgzlCfUqQ0oHVOVh2AWC0fzEsrJlQN9mH1wRXRS8eWbFOu6iAxV5WpnQNGt7PA2ulftpEPy\nP2TBcZxanNEgaa8RJRZ6VXO5TF/x3/Q8N8uHsRqF5TaG/gUooxYIa3zLIrAGr3SBz3zPl1mPbEJK\n/ixROEbwa/JiFuAHw3CVthXiERZxuQ6ckr98goYJyZwhhk2hbJsxXE509izF62gsjHMifsoIxnpe\njk28Vv6GX8Ao3py1YzdQyQgFp410mH7uwB0VVBiU6cijB6KEYqAzraRH6YSATENQHRD1E3Va7jrH\nJgDMIciIp8dsDZWlzavYPwFZEms/VfwRAf6D4lfdLqE8MAkbnAyBf79owUbtFnr5nTpUeol42kRl\noPFoj8ahXyAelE152CoVHHhQNUxN2bCfUStvouGOcCWpx2nEU0/ZktvrlHNscqdJlTnMcjbdtCVu\nPyZ+9EzCTNPPB4/A+S4lE9cw+AW5anw4d8YwvKBk0OGyq8ocrao1wQ4AlSt4Bf4ZYgh8bkxjvrjw\nvK3DZ7x0aeKIhfNHO1Li/+V0feZz2Vf6R7PaTKKU4wqMZPln3ZiZLzJ6BY7hErtaOl+n6mgfnb1T\ndo7FMX38OpxX3cgXyStMYZDFSNfcUUeyaqGHVgRH1RuS6cBogg8MYbCOOHcVxCumV/9PWqNLUlPt\neQyjOovy3OZ7ocTWQNIyzoJeRDhxVIF97mK6S1hXC5iZ3bvFrK8jyQ5rJ3qgjDRl3N+7/micfdjq\nWC+wIFIEzKO1RGTWerdRUo1LqK9cZYgnvfrQgA8mHm0JFiLro4Fn5Nsw+D9UGu4JBsMZabz6V4vp\n6DzSqGOjbAlkrzh62dAHRye5Pf87FATGJRY/cvu1MXVWIeZYc17WipY1d4uibU88EdK0zpBxpfl1\n8hSKRWRGQMBsknouJtFDsVGJCls8jtFxVUGsdHxuoDfRuW3yh3yMmMyoLOoNl07p/EIDQY3T5zn5\nbCncYfhGc78oREbdp9ESs1zFcbbdsL2M6XO6jle7Szv+1Fo7g5xPqEsnJRxgEQRKeI62hR4UVhgq\nze4DGYzdnMDYJdVemdQq53ONzTD3pq42G4tbkxSbMpbVScRB1cBmQA4zNcRLaJzXveee6E5iJsjy\nkMj5IMigLM+KJeQKhLEvORaQAMr2NjWHw5lcd995FcaggfrwunVflTS6X6lLGw+GFQlm998soP4r\nVGQqmKUQ9tnjgFk29C8JFSeJZhx9AM/JM2lhk5G2x4idadC8+LMJnXmrz9G8qMujFnGVY65PQZVd\niFQhTtHzEcqXiewwKRHdJTn55o+lro6dNxzqFtAd8CZb5LjOuAhWZNcR4D+cp7baK6d5vnP02e+W\nTJXeNbRxv/GRdjCYtnW6gThaO6JB87QK+lCY0bA/jNCO2ROISQUFN3kXSezO6OHywHg3QWUDb6Ns\nvgbQxjCgMNVrkhyDm1cdpCufz2jWjbPtMJfxkDiMW8P2PxeiQKhVE9yLcxwOwOSAwTUDZSFzWF2f\nDB2Yc+AE8pB5qFeILaah52SACaIheL/Vi+VZI4XaOo6tK/yr1PPQRF3jhthwv249xtT+uBFWgsZE\nCDLUP+wB+q3sqex2Rw18Ys5MrQDxVwloXX+MHnSK+RdXD2GG/2tmqSwFQn6cXWKOqoFARY4h6Fio\nebD5pK3ljzGdhISBQ1RQQVm0EEFE467SxvJekNpyzNLdwBcEQUGZir2Zj2/Yoo4/HMENjIZ9kzMU\nq3j4GXv9Pks7nPtAK7O8VzByMVKHjP/1W3CgnWn1xHbxaaU2uvVLhc3N93DIQApxUp0QiHBLVdDE\nt07LKRwe//A0k7oOmCdYp9CGi6SJaj/eJ8EQEtPa+rsFlCbCN+CLvBrQdrGuq/zbDJMJTo8pVbgz\nF1jnw6zmQawEry1d70tkeu8yWuSQXz1s1OazCqbS9h1nG7I0+VUqwLOsTq8ueRRSUblJBD2ATgiy\n3HdKZYRZ4ROY+xE7M4BWK4+LDYqUStcbo0PwSnf34gXiBL6TSHF9Tk5Fd+pRz4Adz3wGEdg1tqyY\nXbwQz4zVaIo0dRIghMepHFvbmciaOUVs14Ed8rNPvRfLifIrqUfooK4a6eKhgurbaJrx7HxkYHij\nyISKMKarC8YvOhvAkfagTfGPc42txpuuQQrNXyV72jkrrieXEJfsQnoMAyr+VTgEA9VoD3q9/ngk\nhdMWBM0a4vsZEviGfGhJNhHqUO67kB+BcRYvhLOvJAMIu1FJL4YLjf9vWkUJ1NXD7XokDzn0NLDM\n5uFDmaTLy6mtFmNpt5tGkCwnKoutRNWLIQkCH8/nDGkBXZvfY7WuhOyjrhYpzPgd1cFZWnVISdgj\nQLQSrSkvZIxaZA44IjwmQADXO7KGoiLpi9h4S1EG/HDTZSKU2lbqkmkzsOAHReCMvC0k2CFM+EMC\nfiqy/B7Sye6OP8FItpdH71F7cx259zSkG+t0H2vt4NCxGEVV/jxur8Y/zFzL8ZMxutxmtJ/rkDBE\n4fyYyoS9174HiMrzA7AuJhby9M2rE/E9nApIwSRSVVH6PXBHko7rfT6o7CygaVNSgLfg5jIaMjEA\n4z0QdBds7H3ViaYgFLjbZsU/ZPd2mnsi6br9HrqRsCGyXCgBw5VKcWe6IkKFYjnMac1CYPYN118D\nQ53iTrP+1NGfc3Giaqy0qaNfWEc2N2KMig/A3/30DYsxkx1jPOOAW8ZZ01SdX6NBK0i2IRnIuDqf\n+IVlkaoMJ6u1b9ZqflC6PYoaSQ7f4ps6T5ap2pGKlF5CvPvTFQqCjQZTYTCAIrGKKu4JxSHO9iAB\n4ydmsX40yxaIb+cyRHg98/gVDbgobmou4udaoXaD0Npi+tnsZJ4SsVIrABe04qXRzikhL9Xu4Y/R\nWjbLzNgX9Fgv6bs/KMOM8LZf0TJRAfq5lLKtoJilzgLd4Q8JaTT8oEG2x3kWsp7RZzl9dMWZ60lW\n81EG9qBS35wV9JHcLFs8NiMUUlPpCeBn3hIV4vpjJ02FVlroUMO5u4vXj2CFb6jtVCA8R8HKFHgR\nnPJHrLswkCuQ4KfJHv1VnAV3Wd4/i/29jrdKvZwghRho8A7XiI2/6CL002Xd7GgOGynbr6UT8gkh\nIrVGmS8rcJwBcG8ZnnZMoCeA49YVERs4DU34t23lXPbAtQr8VZNv0mrn5QPiFytVxDQdijc3Kyw6\nhim/HhMWlqVv7/LByvVQoYWC/rZcBagAeH+WBSt7H0hSExe/Cl6l9O6gm/Gm8ZC2lfXDQlx1yX3n\nUsJKldrxhKDH5/AH6lTlxSnt/9VEpesPYNtgYw/evG3quBx+yQnap+8tx7z/wlS1sz/D1Vy6rXRh\nRGLaaHBCRi98uXPe2RN81li6z01je5t5131422KPqgmGcwugV396rtBR0shNAP7UvpKi1uKth7Co\n5xJBYX4t7+NgFa2Tbdn/ZbAiAsjRXENkP6unVElvoL4rW/nuKPRzIjFDOAb9NWqbpLct57vAUH8l\nOXpiJ8jguRdPbGfo53HMOk6ygtRDaGixfDgBqJjDls4Bu2y/5n4hFWNIPPHQG1l9KAMm2XOaU5rO\nasts3hq/yjpPBp9C2I86rQXXWvjqinB91smUt/67kxvjbi5YrlTh7ALr8eZfffRY/HaGUijXvPFQ\noFhIe8rrXpMwPAD9XpH3YxZ4lRrtT44X96whpV1S1V2J/E/mt7kdHBbXDcwTBWNO+kvEI7XtVdht\n5iBH2yFUXk6I+QYl4JjOQ72rsE3X0g+5rPLh9EZTv9F5bqQAo2sOfLNZ1w/8MQlOp8ers0FEy1Zi\nAZPDRjP+KEgDvJPPPXKBZPQ4MGd2z0vlmimIaDEvDJxWl5RnYJizPSCJpsS/RHl8EIb4Xb8UOFb5\nZtNwcCRm06cQzxvAdcg/1g0Xm2VUF1WnSHT+QUMbS+WcS/S6TtCMIixaQW9G3nAOmXlMQR6/dneQ\nwLpcYuyWAzBJDBB4CO/dLVy+kVfVMGhy6VP2Sv1XDovVXTobhreaXn6yjCPJcxX5pFutSiEN8lbU\nfzNM8mD/QM4b0+rvhnGeoAj3/fPFYu8DmbM3vKoc+r5D7fXjuxehQ8FLoYLq8EakH56bgoJ3YOtD\nRZdckWkxu9xrxlASRJ3FIFue0m8j+zW2haGSgkNGcP1V1/rkHNWGFeqx7KG7jPLAcmeQHLZ1Zqci\nUDewcSdfjzQgV9HKNH5gVnW8uiKj2OmIw2kvwbKpMzEXxlD4ZAipv0WqRlw3q8o00+gBEA3YOR2B\nFOHYXWXUenHAiUk0wkdNTCKAnL88PG0RtSjIobbqYL7rEz2qrZcg8NHZxq29V+EHPa0NUC2WOhYH\nvKFlBiCtoKJ4Z2Z+DfgIToatXhGPgCUwS2zEaIPuWxlFYqxhIEYnijkwiONlMicXx3CZFDNWHmHA\nDPj2iuYglHg1aobk8G9E9WUuYr09TcnLj2YExbDnLLg/PzYC1BpdSatPNWO43VlnHEtgZlA4N7ao\nPo1dXyUvFqrnK2gVEt3jJYJ/bwED2HkmzM+kaQ61gHQQz3pEC/JpeHsTJ3YcN/ZWpl+SqQddAFQe\n6MZXnK5tAsNbKZeJKWzJ4piTjpNo5QLTaucsi8BQUX+DSP0Sv8GOB+9vicdOYmr1h6RBxRJjrSst\nxfCBT3USmkBUBvRNABlsH2I6Kkrvu2Tcb2r3+Zs0PsTgPdpVSUMVRUstNb6vGidNiDyj9qyxNit9\nPAyxcJyDjljB6po5iQdiSIGR1nMK6r4kkg66eW+g9W9jLP4CAnXEvVb/owaKWdO9S6tHaCsGIQT1\nlHuQtjeYoZRebAu0iWLQbLFKi2H2+sD2AN2FOQEJCfwqikknbaGFivKB+YcqnaQDnyt9DA4S8ILo\nWvG9KXXJYfDgJPNe3qYf1wkrR+kCRWBODDffl8lCm4aFctl5J6Rfo39fsL+Gcok7WtEX0LiNYF7P\n7cvWOgBF+CintQUd4QnQiOS3olO2B2c/ev928p2w7Bw2IhHsPAeSbMDCQMaTtDM3K5PwHPip7Vi9\n6Ut7NMiAxafS2PV37UaTvEoYmsF8vomPd20pvDRzm+OAE7yKH+PhmF2DAg5sZ3eWZpDLCVbnVXM5\nNRDAcWpwrpY4lP4R8Bk/V+kgLzxvl2qzx2jY7jcH10+y870D4eyo9KZTI/ilrtAnVwLbjd8Bevoq\nZATR4xEzV6JdWx6Ra95270mddqkz4aY8l7LZjr8uyi7jPaGPhLEDbC5fF24TAlLTmlVzPLy1BVO4\nzTPDpZRIjhNwdzAkUO9bMvZ+k00U+4Y1NOjk00OxBOR3sfr1PK8skD8rv1JNkQl6vqa1ew+7y/gm\nVtdNFdKX5GeBRYNbLjPU1CXpHRGrk4hVJv/xfjF71nvvNd/RRXA2M4i/b/J0z7cr7iD2Llnj89pc\nCR0Bf0yiJi/k5Bps8F+u3cfHdmMgTPdy6RL5jwsAsWvSvHinpvmIIVrYvM+ywUXfYWX4pKHSk+sA\nu4OMmjChoG2ECI1AWdKZwJxkzqzg2NJMpsyi1HpuZ7axFrg1UDIbXIzfv2w+fs8J/gJaVczCOO67\nGhS0ef2Z3YR02shNRrOnSK0BrbxebNI5Y8GfxX++2qqO+scJ0TluteU0Af4EUg/hKKbHpeFsn0vG\nPiJYrjWCQbmIUPZduXHUjWIHnvnKW7kX9x/hJDVyaU1mBIMifUgSjb/Hc0XhPwo71iWe25JhMuHr\nwvQ+asdpICLbZct1r5XxiOrF1D3iM66AaPoAmu4Wrdkqdiz6o9vCPwaSZmDDEShxFnGb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lxAsMfUqDQ3BHARN/piTCg2cS/7TE+AfFg6w0FtU+VWZnQ1rBUAdGz9f8uPwhfRgzQgZ7S\npods+0vJGX5FO+PA+ASBzOWFXsMEz50W8D6Dr07UNhNVguQRdjVIKc1GOnkjGOnwu3tNWbsgmVKM\nI5RSCT++iZcsrijA8L3MN++vp0U6DyeBPrB1YLCuUXfhkOVdGGOlshtv2Fh1HieMJXDFVL4096U8\nMzKw6X+BJpWOWYPTG04XfeDNGcDRg2KOKIzVZjmtPRbQeoT1OM/ZDBm1TVn+ERHgPsbqhjTaaPQ4\nJU6WsUmGMvcEloWlQrUanfKzS63A5D9MFGJ58pDhOo7hutbaYdbQzgw/I43oP8L98IcurXyP0aKE\nrr+5vgiT5YLrMb6imm40b0N/RFn0ah11txF8c61VOmaQXc1gKb5YxUfDx4j5IeBwUfIWIwnyB/zI\nZPNvBhjJm5M97osJYZh9RAQMthbB+GKy9JsZG3j2/C+wyk3ytWCTd2JDxf7vG6OlBJ/s/Z4MZGQ1\nrH1bywW9DJlvI9XkLArSkzpWLZwQDeIIchl2BmZDNbQPvstO7UkHgYHUEdRnpxJlOupBShtbwbhD\nYgvHdyAqZpgDc9K9K1oLJvQ0HQa+JOSmRe0vJJqeILW27SAvS9lT869uuK/9BauJ2Fiiyj5rnMeh\nSPNE60RbyQidUi9RaEkpVcqqpb0WjhD2aAyzfJGMItQZo+7vNrkOBguRZ+hTLzPrbN5CdiFZJQGW\n4JuHRUOcVJuIQo/PDx9Ho7VIAwh6PCmeZ60ESo1Rx268sZ7na2arfmJVerKbQlqKMPPoOotxTsAx\nuvihYc3oUtHnnBVvBfcjp3bwGzq3buj5jvJ+NykgvKqT2TeaUQUgAquqTO3xKhhRW5OhinrbeX63\nv0IKvfN32Hoft6KnWHNKAnaWa8fl8rOIynyWhCoG389qg6mwVg/G7s8xq8kow0TQQtejApr/p8JU\n2RuQw1ISr3ndAOgSHLhTjT3OJFkjM4BKs5NBNjMR1lGLcnLQRxLV7Gj2rXUdMDjFMYqVLTmanORP\nf6EFb5wn+tQuTXQEG/frOEJygtgIdO/5Qr5tHodCByi3HkDJs+6+8lEC1zxvb1Z21m9s6FDSskEO\nRhovHSCpwil8bAY5m3evaa/bFNczRp8z1lJwgFHA3L1dRbc5a0iTqvoWjZiFaVdqqdzK3Hpgz2Ke\nEf41a0HGrjHJI+HMCM77uQL3kdj38ozU7VTm3cDvJ8ewLf9VhJbs45i5ZesZOmizbfAyqtL+DqYY\nM6gSuuGkJpSwqbiDZBb3tzj6HyLlDiKZvaWB5MPirryViP63kvkDr9xz+R15HOVRr1tbMYxjKXVf\nzTirqA5XnyfL3rr4+Y08ElHxgoCt51OfvCXoUDKFjOhqTwRL8c0i0bgBcbuxTbCDmaKpTKRdBEj+\nIOXSY3ZlCYh1hThF3pGyPV8zeUf/dXxlpN0qvYgmuwZcKV5+cvK6cxcg3d/sjJMzigvFybFP4Aa1\nQwkovvYOMTQm3cHaHxzSkxC0DUyc5+TB3YqbmZpiGgaMP/9J5a5XnqnEZi+pSi3cl54c70EqJhfS\naqFzPU3LQn9JKqjMMzz6czqcbC651Xd28X+e/iXdR/NE+JCmAWZqpOWF+ralDOSQb8CqkkWoSPy7\nVfSSjvgQubDI09EvQY+4OV0F+110Ymu7lwd36lwuZyV/TDxIZKoY1cPtbqgsRIKZ6Rc/zFw8cC7F\nDgqJ9CM0vIcaj0FUWc4dKuizHdhtYqt8mS1aBM6azJ6/NxdCONfEBqOkNST5iEgvEgMdSAOjSWxl\nqxPlf4u0d9bViVWD6HqFrusReFsUB2v0mUHpHlflphXgeLrPoCkNNlwxok+x4wPH+0lQRaTDRB4Z\nXvi5xO74pYwyDM798nxZwoYmi5Va3teev5XxvHg0CIbWyZBZcaZjijDkGaBxHSpEAgsHBmXfjO8q\nVtWSsXVELOpADbopVhS1++5BwEbG2w8x+eTfIJto+QULfhIPcKubq1QVX6t1bseyQiJv6I8JcHgM\nNzoyFmdtg6CFWI7yJJPZMQ4zmsT3TwG4PiTGpIGSE1ou2rYzh05v7IPFMs0s25JUxKCZ0+sXK+Fk\nOJlgFHWkGd5k1bdRwyN84seRb9mhyQdUEWzSEMt5kB6R9DlOtFjdOzMk8Trvu7NcQXRPVNLthtVC\ncF40RDqi2khZX9AOvM1PnAED9vsE62zb1lO8ucKxJv3YiYYkGrIwbYIToF4VhGJnTdA8KXkNNQeU\nemHWP/TL4ougaU8fum7xb8+wIDMW2PfZJ4WxtfpUglnUG7lcLycmURObyGNBMQDdeLRFqVOApIxY\neqCk0xDw/ruwp1r4TWpgpRIslLTciw4c9wEmcLIEE6D6OB8MRkBtq3jylSjhR4Q9S85ZDjir7LFm\nn2pyww95/nrigK1H5gCD9iJIoLYWbaVVwWy/9H3eVTmDx/AXOXtQ98fiTlxSpJ/hIgjbhST7dyh2\ndb1Nf7o0BcO08zBi9gsmtc496fwOejr2+YanCquICVmncHrIA3yNSQeGxPjSA4YM9hiLIIFCr9ym\ncQHK4bH4gzl2Q/q3l/O+lS6ozWXebW6ZjcgSQtCYR8QWYb3TDjDFBlSAtUtuHyOOSFe7VWOqIrmM\nXRClN+E3ewiRz5pwjSVz3gK7FU/HXA1FxBAKHVTIS1rmgNwJS9FgOVP7YRiu96nGNeGSgZkWIeP1\nowhKi5lJQZ5o+XeBPDIIqgUeeErx/feW0KnKilwJl8g7n6U4wUqZlf3YO3QwXLldMhVcZak8vi3e\nRK0ZCc+qzVF6ebztNCaENzx6/KnWxh61ZmP2XTKkqjvU6rjZ0MPibtOklCPX/Sw/z93/Rasr2g/i\nYdx/XsBxtvIIIiB0uWnbTq44doYA2lufNadwR/i1aCeiSv6y5n8TIxLiyu3j9MaVwHl0sYOg8Hip\ncwffpj9NffeapTyl4pRWgNllIp2+T0iZBRZ55j7/2rEVmgnzHCFbri1J2HGnilanotMC4XwUopsH\nHIuy73Nj/zBFlkicu97/wosbRX8jN4nhGAtNhonTB4FzfdvqDAaF6lrE6lIx3nEkzbg05+Cn9Jhk\n6ZepjXo/ShZU0/U9LOCwfRXxmelX7K1mbrgTyy2Kchf5jhg0GxZkTL2XhZ6/raGBNONXha/uDsba\n1ooUrAnxI1WtuOqSs+gUtWDmGjEtfxAcUuHiD1zp5TTWNHU//ph/N9vu34eQtp5WklL3YGVb5FLR\n4KqS38oRgwNmhCXy/876ZCX4IviGtvmDyWkhEetRsl/F8a2XrGkOiJYvT0NbqQTJeuQPI0ZcaCuD\nIZRI77vwoZLGIj6ZerUEs4fJMKLU5L6waVzVbsebNN/leCEofs3xugjzVh0snSiqnlZ2gvSbkDA6\npklmGLETI5hvPrQnwg9O7TYeJkNrmBnDS7c1VQNut+ico6wvKVehlL6LT6lvEQRIAdjLlixwAtR4\nfWyMns83DWT0Ti+hok5EfaPWdh5W9yK0HzYkP15QZQt6d4Iw/uQ8/FQ0rZ4In6IZJIwkfPHcMCSs\nYYpmprhFk67XDcgZifzbZiaXS7SRae1GQ2Ok+wjPp1m62YZt7Jz/5bpFr08fF2WtlBmDtrr+eLRy\nj++FMTZ5QHj/p1bdirTkjiT8VWhM5Q9eonLQNHfszRU9nNdGBosGeaBUpvIYu1ZW2Zb81falB6VY\npvcqjBSLR1PSE8JtI+iURyV4tbWzYOPZzQIqJR1olsqem4gjJOUf565oEFmlnxFx+gjeYa21prV9\nHzClhvE7kcU+igXV5Q/4/iUhDk+pRouRo6k76u7OCD9O7FqrByIY+rQz1QAZ1PqKHqrMzd41KfgE\nDhu71TmoA1czZz+OYmEsd7TTM5FkyeMciTu2FcA7y0q4X8s6g6it8w1JcBv0Vfka1ur05oWI3rWU\nVqYyL9mNIEZChINC1lLVbhgNlNDQ6fkgjTS67eZIYpx5CUClhvjSqZL8Ou3xN63/PEje5i7sSsWq\nH3Pmgl8vpMOYfqNm9Y1MGljEW49UehL7L+xGkAeEQKruxzrUcVSrAhsnSYJSabPSeUSvYyGR0W0a\n51HHp52t30HkllKXTeSgrtVRCqOtgkJwCe0xGEDXtccpTnBvJ/J9Uz2Rg/UQOLMeb39jQQDx1X33\nkr3QXqKADdtLfKGWhWyxkjRKSTXD6WM4OeBcO2p720vw0KwDZlyU+QJDwFqXzq8Gojcpld2XQ6KK\neODvBpPJmezBhKySrrn54ZxyNKltcOLug7a5UKPaIyPOIZP8O1H22VbKHMxeBGdQw7E25xUxkuKG\nrlhGKcrsQqwRBIfesJDUYA3FeKEbZFe1BLfxNeorb2lqZ3ROyaBMQ61nXLKcq0fuKPCjY7Nr5es3\nbHLZFcNtwIBEsBKxDw34Qg64LpBHr9RgJ3YrAzFNmrD43HCqo0aSh7k/FqmsOVBhzQJV9C+b+tX8\n7qVUo2ZNzMX4S7YMfo1LsH9vlsodIGmHd/z8dyX0CMIkjLZ+WCeBFGjI8ujSlhiOyIqo8Avt0enl\nV5W4/ArecUWjj4I/4QDc/MVq88ZT2beUeHKY5+0Zg5k26BjU0CAva/5tK84g1aXY+/BDneKCZxA5\ntLQmdr3qpKaZL7TD+ONVxg3ihC5w8KEjhM0VMu5YLDLtrIIYJgJEOi4Sazp2Ypj16h3Ul5QXJWME\n8gL0t7jsHjySILUJVqUtcpVDOZW5fKukk9EN48x+eqh29d1exI0AnEv72PyeKeAd/2lx/D7/Fjmi\nWsbpK/4q+xpvXjqNNWWt29yWfJUBFfGcRqXYSXt1+IJIbmA0fgXworgkfqj/4pwxDWXBDaBff4iz\nI9zto4scZmN3L29UTQxlHU9u2yVphZkhslm/m0skBGI3Hc7x/Q5OV8hPooIMzIWNaGRQLsl6LQpf\nq7mjXOD5lhVUAGjYeianIWH5ogwDCaZKsoYdMceAGsiNouWyXFQWgONu35Eyrwvpi9C7dM1J1o+p\nctSA668wZmZNXcXEkAqWs6QL+UrYll19cDvKXbK2bxv0NW3DNibLF3bRxhZZgQ+WxUN736DPcptL\nVMN843plFoDjwO7D4FqNm5GshEbmyp2UxgJhXZJrBHJ+sKlR+ihuLfLMl4+WGRRgiAiULMJ8m6us\ntk1sj6diM+pzo/nZRLJWad0GAu5sFn3rJpQO1ZyJgOc6w99TPauBMpLLRNvdQWEZrUubmsArA4MR\nJuXYefsXAQ6x0ZEvZlvBaxU2RgXhqwzU2Bajbs6qjbZ+i545mi6qPumDlH0GHKRxXacfpYdpQkZB\nZPj3C6plE9OGBQ42GBje29ye+41et5JlZnRhX7HsWLjjV5XFaZuK69nsjIoEyFoBlGtSD7ZuGPDa\ngu5arHq1jYq19I3w+Gxahe6D2vrFYm488vXc86gJuzShhPa2ny6ydmwXPI8ovVMqo6veC5+9K8ah\njwic7V/qzpHCHlNLSjcgdBojYH8ycGSpAQJjxpSM4bNHbhbVw6JMWG6RHLgLJk2/aXhIsD+xJ5mL\nAiSkrzBPj1lYI2Ar67d4jqG0z5m2z+B4fEjKqfIET5L94ITGx/mYkbl1eNDhgTsqYWAKPUAlk53O\n7Xv+fKgsk6qyMEPVqM0Mdoqn0iMjIJv7amzpL/hk+gA3w1Q8jX2CSsatDlDmL75ItuALKXalgBk3\nVOonpv5zkkdB7T7cdApmmsR8ipqZk7ETaJ0rDuTbkhmHmnxtLtzZ/Ds0bxuEToOGVpDSxWnjp+wF\nXLT1mq+eKGr5u2joNXx0t9+XcgPiCLtDqPPnHlRg8+q/rgqcDNi3GA6zimcpWvTsVF6FPSf0o1Jf\nH514yG+sWZqeRc9XHreiiwLugad/lzLaYtgknIrOzzdWWiZSRC17D8N9SbpBpOwh0dcEopR/BZSn\nsxIOcaln1UtVL2h/2dvfzZFewlsu9n27HDf7hy3gK3hOtHAYv4wwwxnGXaQcVhY1w8DpubzQSp2c\nxroU/cEBRGRi/JA1/I3eRe1gobfzhzPgfNXHT55tXgjHoYG0mZOyQnr/gvOUISp6BwnesWt0akQV\n18rdGPzWUkmiivF3+QATUWBF25hLX3X8eB6/bkyC/xdRVApFTfp/dm1uddtHpl4HifyF7OrVwO2P\nx/iOE4Gzfw5edj/gEHOJbIEkU8KhKzyamhzYyKDLQcH5yIk259NKFCHDXdU69mPBy4R/jCMcJcRl\nwvaTeFXWyZXx5U+Yifz2mXqzbRspYR5PibE15pcxbheItfUOIfjX82sN0AnsRzBsge0duA/xFM+2\naotpuIeRkey9oD5bSAF/nbLLg4suiFLF0ViggXLQCrqTh/9ppx0R/6tigF+Ep+pzo2IybWrBKjiV\nydEGHtK0A1FPXVebAHbikh1TI07ob9kUPNaWE+eN8GxeIjevVxXNpwsox8tkJfszf8p/XuuvIB9I\nwRjPXxDjVcHyQcDaA+3P94/Hy3SYlDrKkkJpPSxaTTBkOl4sH0sJY8400j8OWrBpCQRxm4ipESGK\nzJMG0C56qMsjGfEEQBURNVizt7YqfF6YvjL/kuEirgEwyQaIzlDNize0kHmB+0oRPjKsCWhq8IhA\nK1UThrOgewNQRLbWMwLsTNbpIfHFGFPMxaiK59qeolKsIqnp3gX3RCf1R7B8YXRaageFklC3djld\nPVxdfsUFLSgX8AiBJZ2sn6noeQfJyKe9n1JGQ7P3IPuv467U2ONpdKdYR9e56oRVywGcXUbALKNc\nLbGPzDR4WtDh/an6Pt0pP3yFeAkSRb6dBGrchzK82m26vD+u1bBbt6Jq6mZYgh3Rsa4AWCPRD1cX\nz+NMzKXMNfR7x8fnFZT3Gra/2Lhbgt2J15+dSix5hw3aluaGGj0w/BL7iCdle6A5V63XO11DmQyH\niGYPppFU4k4lwAqO8lZcl692aLcQIrVjwV+EBnSnfXEtODsVeMwqERJ9UcbFVXETOKxefJNuFdEi\nY/dcg/lYlLN4VrdzEUif1Imxec0GwEn0n/ZXPA+1SZJyCRGHY4is5VBHJuAN2+hc8D9B+vK49tB5\nzX0WElBpOjWyQ8ZLsnqHzShOMe9RVXSguXxc3ic+C/m3vwVydO9WWdMp5npQKW4WarcHUS1BqVuv\nzHlhwYB/L10Q7aU2urronTiKDG4LxfK6fRG3R4ZcDsOvmPLb7mpDG5ZtBRPn1aq601okcFFvVhR8\ndgqftQwujamEfGM7zDuSprs2yuncBNeEdAgxKwR6TX/CGOrYD7bO8kjJSl0hgIZ5n7QHk3Y4O1p8\nM/DJXJcxJEkrwvde6iPmK5pqxanW0MmsYWsp/kbnfGq5B+kCzx4Fcmq6VBG+w6wqRnRRKBZrL0HV\ni+0T6wF3bHHlCFKe6zYhUQdczcICT48Fj3bxneuO1w1qPzQ4tT0FOzKkaNZ/bwzbStv49X4Wamrp\nVHuHKnBg2YHJ3DIeNGeFRCqMW6QPIbUEDrkcXpmdk/SpeEJyWvmuQBZgVDTMnfiqwTkXmHs31e/2\n47P66kJTN0hiZVlkxRdktkzrBtds/LAfYvnA0bHwafLy39qnL+aYtCPzvcRpW8Ju3AsU6LXQ3cY0\nRJKdwzE5HnXtCF36Ku2xsXhae2uiItn3kGdpwtzU75mnrZ7y95wJqZZm66gluuUSy4i/HxgrheGr\nf5P1cBiqdAzYZXiTsaf1XdJW3kLyxPYV9uS+lwUzYbqu80h6QORqyQ3QqmTuJ0t1ZkdNBtzdo5i8\nRMMn2bljN4N9GWeTF0RsABSnzRg33PWObX1cjTZOwm4K0rDoirraFBJtwocp8RqtoIUN3WUgP7QA\nGBY0nqQjejIj6pISmpQg8JmtUjTR2vPVpOom8qtq0XUcwteWFNLTYFNjor5W8qmdrS/+ScajP0ca\n67y7QNQ1LsryoWqQjYo8L/q4AlCxPiP+yWLyVg86K42UdusMYhm8+NRZcPdTKmiOIVmrrKlMZqSp\nQkjFkFgI82SKghF8JHPY38GwcFSwXB/cmh7Gu5qFfquVjaw1R56zMEMaHmt84JDPYDHQPv4WBtwR\nokYqmYo9OvMmJ7CSbeBzWXipirFn+cfEMT1ysAdlI7VKbes5fBjETJpk/SFs+Mv7gDnMvUItSdy1\nOb3JZ2c2mAUVX7uwyvv/01AtrayFgQNhwmiAiidVgiQ7azd9FE3ysY/mNjyl+vgpL2r4nQYp7Y7V\n05etZy3W+0XyZAdsWFvCHHkLbTsnWlBPAC0A7foAYfD2R6+jm74EZFJJh/4MN4oAKv/oVV2xgnn7\n6iGKwdpbCJB/s7fUXRWCYl1dIqlpQ8mkZFPD9vg/kav6+glVwyTIH7iSablJm0AtbolfHuAckais\nyGP0i52CUjXP+g1BpCI/h5PLn3UwkkFQLSOxTOu4hYuOlPdhQsO4tHh3BVD3E+cukOakYs6zslDg\nTBm02zG8/NtczpcOGti916MUZkToQzCHpeoF4UMUDvGYfsUl4uZV4NLYdRnxG0nWtgnO9HMlXaTg\njLKZtQqfr4b8o+JHGyctydwXkVQohk3HKoMWVDeGpTHqjjle2WlPtDzvzgi59SZ4OznQZvBhjNuL\nBXSxD49NrKf6CK6VJd+NNwziAt+WzJoUTjhj29Fo+gys7o/sPHy7k4lqQ41i+HfrkfipxqIsr7zL\n5Ek04iZAm7mikMJWX2CiLLrLysQf6HBNXA4ItoZHQmXIqswGkvmu6JTExVVUixfD0LbCoAmIuUYt\niyIJ5oQg+9qmjhpm2o8Xax52qEoZtpzS3djre0PGvT9b4nwJWtxiHNBLlhZ4yx07kWf7zVdhHvgW\nW4qiEexcQ+cGq/pxEoySFl+DePkf1rVu2xYPzoFRT/S4fw6/NIBoez92teyR/dSIrqZSo2pW2as6\n4uDTDbuFvNUdiEI/vqbBwZW/g7K3Dp0cLPIclQw81yz6h6/r7x9Vgko4Sb9vsx5pr561zpwqNvxI\nMU8Aw2nR1C1HQmnaL7VCorljamFBj9ge23QqaYKqPUetnluMvuhNRVBvgVD89eClv/2lvmXYKKcQ\nr/eYFLqrReYuzgVq170UkKMV5g6RVvr/GsgTakMJHAJMyeo0FFMh3kzC5yKYpe8aJkZ0DiOedByC\nl+wDSe+DKkHj0laHud3zwSgIYpogmhuON6jaZr3vgCRlukxPkSVgKS+1K3dGZ10lw40IW3N9JMcb\nmMEoIbAb/xe0M5/lrsQuTqFx9eRWLFZ2gfdUybdpAO4qTjcFqNx975d0pPJqEOX7u7I9WzWFEQDx\n/IGjd/lqyPmuRjne9+bviLEiyD24Ra/lcesxnKS2oSUtzjINYMKK/7pt8/zcKmTehrwxXipgZgsC\nLvvMQ8i7R3PZ2E+9RhFrYq/3wIGzjUenRAS9CMnCLvVJ/kPZL1OFKMa5hWkIb5N9tNVy3McvW5oC\n+/5+NJZEyB+ne7iLntrnMTJlYE83StWyl/F5FmY+RlZUzGn5ibdrTUvUqxwJDNDL7farONbJnVID\naONsVYj6y3pnAWmXOfe0mi4fAI1sGPrW7Nv6wTfQ5mbggggGAgGrYCR+nQxxC7Nd3nDDOWse4kat\n+EvXJm0cZWgSC+QZcUCNG0RNvdWNXZSP4Ci6XonXwRffQDWuBf9FhjqXlMmiG6vPuPOTqKV43JOy\nMigYR0yhnISAK/L///pl94T+OjnC8u3VNqHYyZv3LVI8xvLRPvuOxOpbBNLLSIaCdvRjTN3FlXTs\n5VG6VRtXb6KLSZubScN3h8AVgB064uFGE5nD8OqOfMblMFAND0AC/dLMCUR06RrxoIZnxCE7GFuz\nhPZeNcleOrdWNEo4bb+XJcgNEJ4kWcV1wHfCOGGTVunOqCoTQK1AScx5xkJyExA/nGFsiT6Cabjg\nZqKveVXiKesdpkJ+cR5IQqSQTnyfE8IQsRx+qxtgMyM3eQjoxRNyqmssVgEcQu5rNjE7w86K4A9H\n+O9jJtwh2DPHlyiJyCyFv7AUNIs4sDK6Lhmff1SLLkiybQNh5kCZbg32Hpro1bVba1WOOvQwFObO\nyZgdtAdnWE+2HJp1O4nt4NGcCq5BtDNTpszFABgVU0astr5CkiNZ0YYYfaNJznT1R8zd8PUo+mS/\ncHfi6o0bmRa2wf4EHdm8NWSXNEaLPWVrBW2VZNvD5T/iVdrU2pL7rS3pVKEQGxzWozgaoA7AlXKt\nFsQDHqtg5b2jGOv7BQ1cG74mH5TgSjt9mwUBLhQGRwb51uN6T60gdvT8T0T1ZOC7p63ri0TdGYLW\noqJ1jrITAZheO6ILL+qmVZwOc0FKwks067inzGUxfzw1gb1Qhpas+BC3/42MFeV47x1UEYhZyL+S\n2TMS18Jhgn7kRw8ZcOjGWkIhRHPkWZurr/uPgiiYnQ/AIdsmyF5hVKPqSdg7yzjo8DzQdr7w9TNc\n2L3C5fmSLP10yAJVJyRwEHH/P2KC0kb1ByKuwTC0r72k9Tt+N/nCjWePeo8VLFy/mC7CuyrGBK1Z\nuRFc7OQlgSiii4ws9yuIM3snLKhBLPEukZQdxjC3hmO6J1GrlKIG3h+c03qbjS+6+P7YMlBgdVcx\nmYS4cNNm5SCp4UCqtDSFFnoO8mJKYtcsSrZ/DeNLdnGSm9hMqQyBpY4U8YYUEEFLTS2cZNSX9U2x\njmVtgqnfIoPrT9C8oLgpMRRKIA1lMufcBv1k1IwpIR74sghnXutXezfvtj0s9cFfzSWHOYBfq3pm\nY5cW2RCZWWIi1m3zC304wOlWZlVaT9iJateOTRlX7FnilLmajr6ivluKOtuTZMRBEHj3qpfNWPdJ\nhpGDeC+OitpNdVLiTeNkXYzwTdQ2HweFD0+A8DPZp9G5EyLXHcMujf5Gc9XRZa8cDBCZr33XLAO7\n/qVXLoorX1OJSHjNfGSzaRL39h7rKK26bX8RGR1n3L0Bxm6UCcDxpnEvghQxQk9VpDsIFao9EB7i\nWoVWt+R8EabLW5cMlVbkk2lV9uj1So6I9UbgUathU7eZUTwB0ozu1Ghg3wMQ/I5Yok8vvyBYgWr8\nLjZALLapnbpc7x+jlW5AyPzmFL62mgNRHTDnkCO8h2+tzqbAVP3jxa07Gh3/uvivlqqOgn0V6VIU\nX7S/7sLAA9rDdM/qPHRvo7DvaQWxqoQ0WJgHCpi3daDs+An5TEIIuY4cXyt2SJbH8DXm/7rUvAIz\nOJeXqI1dAbVZHPZsyK+jRql6b7IoTjFeUq4Qb2dY9IzzrE7/SP8/BOE9GS28XGFrop9evMiAMFU4\nrk5lyhgPdFZ1qNJCPcsJElkY7An3EgFrec3maJB27adwg9ACtAR1E+E6cvmEafPzT5gNkL7wVvcQ\ncfZKEmT3GTUfeQno4DLf+9oObko8h3tTjco76gmVUZt1uyClu36GZO9j9TsA9Fr7uU1uPN+O80wi\ndml3wyEJFT0V6zeks2w/fhFcgKJuHSQ7TPo9EiykbZxjm+BAErP3+Bqamfn2ITGfL4Fi4fInJcJm\nwRfLVV6JaEUrVnIyaPD12I5sTfxlzF4Q5Tt3DH52q7x6RdznXO7M7XRyBwSyEYi3l8mPdoP8Urw9\npCg8sVqRlDg3YRNvLcd0d+8cGrISUJaQoNUtcJpb9K6BaTmzN8Yfi25Hi41Jg59oRx64uk+2TNmN\nRmoMQVc/DVkqCdyOXf/nFEMvpQmUNvKnI7tKiEA8BtH5qlO1HWDxMke+bk+8GLjNmeL46eh9a8HY\njbuS+yIoiRNW3LInEFsPuqap1xWzDJKgt2x6ueM15kowojGD0ucf/t2tW42sYr2i8BrT4Zt6OHBm\nR12apxmb1N0swDj0lPjudKdacmCwzJdwyI65B66nY7WJCt36FckIONt3MX3IKD897g4wZlvcWB+j\naeZ7EQKOeVpqG6WwAG/lH22iCgbhqiD70i0xXD6f3LG2Puhl1j6EiJX90CKzvHIofaJpGLKrSJ3E\n2C+DLu/IcWaeuW1xxRUKALiu020Oq4/d/XQ2PLyGPmk9ORXqOvYVN2M5OrVn09A2NGhPLorJhPMJ\nhBoFwxmOYYm6rFtPBIQx8Xu7I3iJ/uEPcBKrudzGVJcfnY9RHivmfzzWyyQcz9V4Sndam5dWmhEa\nKJvM0gAl/Y3wlD+fRzP0dZtKo2Vgsqwl3myNrl9nhWm8QXfMPFKZdyrjeqNoOmXV9lO3wrop/br1\nb0ZRFkFV35lM37MCjkMwCmX8ZjgqO8mHsnWAIxYsEZe779mwW/093lDPqeEEoXwtBmF5AqpBNpyd\nqFi5TV/SDqMn+sGcqVnlQbbazm+IJe+BDK6UcjmNpEO+/bZXJNM1U7wQMU9ADx2gaelXrIrl3/7V\nsitzK6FW1gJi63QYFLMen4CfGqXg3PdsSie2KT4w6UJ/rAcEoKDawN+cNNewDu/R1VDdhUZgoZce\nfFWeOAdltlXDcQOoX+e+2YbMlUVgz/Dzh6BRwcfl7mBdjv5w1cbaDUo1U9MSnu0XhObkrgEsw9di\nBOaB4tGwWiMCbGHF0Frufo+s5Nh3Tnu6WO0+RYHs2G5+Sw8HjtM3zRhl8iUU85y/I30hBnFBuu76\ndXBiT8rTeD/dQcL9RkGtr+0AmS4vjF5AyUB+B6/Diu7GAd4WGA1kxSU3eWoqcZ/3kp6r/ILbkKqa\nVHqAYK+fUVDd8aCxCCmJ8kuWTY9c92nLbVM8DyO/QUymE54Vk3omaHzltkl1EAtgm3CG32Hb3tQ2\ny7snkcCZQ3+mJ6bwMlVT16XcJndlmw1wwBvk+nOO5WvcBRmiCH7Z8laptIRXm7PB1EeBFk9d7AD+\nu/6oZKvmK12+dIgrSt6R10a2I54hqCjSCa2fQyg5xX9xxxZVJsVJOcpvdRANCrV6cfN8CDoMOi+S\no91ExBD3V4Qly1Z3e2bJSLjeFiTuUvY3up1fKI7UDrkjQVpJckULgdi/9kedcPNlcWKFtJM+10aQ\n2FG1PjDsaNWiLaezZyoKa2egTqhwyiuCdSE34+GsB+RA1hPmDn9L8BbEwOhpUjewRLLDhbcnCyxV\nAVJ+t3nYKDuk6MVXgFta19l9sZP1BqXAX5TNARED0wupDE1jhG/45G+/xAIMj2uZdoWzKdapQnXc\nmNqERVR+KtqFeX091ZmHS577EWqseat7Vf/8xAIbaByCy/SqISjwh9gv9j/gHkUb+Wh6yxCQX1Nq\nFpbuaZ1Geii06xD4IWpF4FK2aXNAXCEiJGvISqChjQ9dOGhLnPx/CfQ2oWI04LMJ9m8IkUjdkieg\n4AErg4wI8eV7LRr6dp68QBAKW6Rw4OKkDAXUy/AGPrP3i5+0BWSykboA6ZJGEMw0z5zUkHGWK6k8\nD+EO2u6I9QWM6f1JXSMeXtA86EirmTqEctI9Nixd9wWSgycCzhs9cj6cRi2NvyVlmWRJkjLIABJ6\npM0EjZTofQhJFpFCoU6p5HvPzg6n90MZtmDOf5KiSdVkXzukQTMCUHBUYJKR413lsMrklnRdWcKr\n+YjWc8jJ1ofSC1Cz+l8raE55YTKJ5+VqlMxMPTUsq/6CG2/ycahGIQQ5AHkvzPN0Rq5Ozdr9gk7O\nagEAc4TmiYrh+TnlLlupACmqpeIZb9h/g1SOTDjw7VOVC1rhK53jIcxNN8rhVrRqa2cwImliB0XX\n5LZz4/8jSUKpRkYa8t/0y1wOgG0Itm7pTFdzmmkZ+zALXfjn1upXMo5tCRADMmq9DSLCICK3z4oY\nWfz7fWUgNTzz0wrGyTrnDS+yiJBNuqDN4E519BigMT97fgtYJ4cL/TZKAWA1tU4uPP4L79bOp0VI\nlJoQnRiNmLZAsSBPBrBtms6z8abCNnSfx5KkX+I/5gbVYg11LciA7MiJSS/f4RgxsjYbm2zi9PQS\nfj7mDCCngfttI4jNAqjIaRzG0jyuyQiE5BEAwJs6ypvrcwG3oDGRIkop4puDni8ANHmTbzf+ETBv\nzTuFssptVdLAHiP+9Q2MUJw6vbgZh3NhrGaus0Mw8cdI2ClYeiAOB1Qg+ufbmNn/Oq9ohepmwgjv\n5zPAFfsw+CNwfEZLR7eVo905z2MDiJ1LXFpm780NUHVoCDl2TRNzDDkcOw6RTImCKzKmZBQwQNNj\nJIUdZd1BpE8FGj0TNnz9ftg3+hukCVZE4CnWH9vRltKLz/rmOWwht2SvKRacgOZ0pU7/dilbkh+L\nAmvjawb/JmYi1g+/YyodSHrQYkvOPZbH7Zmo05Favn4/9HNAaupZQL/gbxOYbn/3tdPdIe5jG5pZ\nWJSxbyeKDvyWQiaCtuE5EF6yK+jSiAXJXmmo6jVg1oddQQanFCBFmsRioGFuHx8e+LLXP0xXwOV4\nJXv/0bwc3S+lo4RhTVAssKwasDeF4oI0CTNW14CYjeISpViotNBzNIAvoMDkZeyBD0xmevfhZWss\n5XcG3rV+Mikhnyrl5jG8D6me1O8vmfijXANv0qZyBrbfDq1os6NcbXWX0hEuetcW8a5laRUqynU6\nDHWD4ZKv7ht3nF+/p6rf6VmWEM9hLxKHIldebT4s2yKeB2/DFiu1fzW+xWtNq2W0bsbsDltDBjN3\nN1WMFKvOcUwXvRxGfoAfx/4hndypb9V8KVN8UsaF5cn7JEYYM4QS9NRAlqxi0lI9GhtEhEQyr9zp\nu6RIJXbbhCsbZOzVyXrxJRx/105pVE2WWZ9UGTiUPdsjALtK+Ogdz7d3GOrk8/RjaeppiBGLkxvM\n3KYc0lhEAtJwpCPO1b1eGi1ed4rZCJqeOH6Yc5++c2RlGibC9m54EGPPa3ThOTNw+DGZNF1QEBxs\nAO1t5kOR723wKu8wcRBvp2+nI+OGnbJ2BAvL1jbde9Vtf2wrfAw75eY6W+zg3sX0J7Fa4v10d7If\njETx7EAt22f3d3hg28zQdMqQZ6P5PeO9mkyL8qnU7P5U6GUoFjDJC+EiurzM0P7iBjiY2CqpSMAn\nRulFbmGl7myfgb4Gjvv3zvWxPvBPrgJzqL8TOczw8deyXjtNYO8FD9SaNPl3VUHtlJnG1kH5soZf\nzdHnBzcCeGv0Kf+BprUgGucxIOUipmYrGWO6Qf/fDkh/I6zrTHvxL4vcq1qgIKQBCDagFplCZrrR\nDlOsAgiFeCxPQ9dzbpZDV26j4JFytSQ0StFs/OVeoa7C2i3HuGYZAg/ja1atk/hF2Um+oUH6kRm6\njcxz4YosoM6YkzUimshnR96+PuxV7yTFW4sHi0EQ1Jb3MJRoH9s5FMEBSXZNi7H149J7Ay/HhlTe\n7okPeocTydkJfoBS7wvo9H3vLu67gVH1pHbXMmVwINhbQep+8Hncc6DbMTbnTGhMjW5cPdV+ESYo\nSibC3dOmf7ihCD9phenjK+O1g+Edjt5RomE/J4VtVptHWtPj5yfHkDudy3YCWlCR/vJRMTDw0Rsi\nLSpyVm8awgZ6/EoUCPgXafnS8ynzZiDkBeMYxLiuIt80gzrzfMa2+QLT8Hhr1lOJ82+0XGHl08yQ\nMv+6EVVOVF8Umbj9R8rzdqQxVYujXvSBnZBYxJFWD3niKYdIptrIGqyFWUt8VKV5W9XDqiJBeL3a\nOX7Ui9OGFORhDH7/9SDtwvNxMqzSZzHkjBC/k+lEJ/zlMVPNLbGUvodoJ3sANufXiwlM1ETSpkLE\nDHs0MtL0rBc2dZh9vuoiMIwz7ODaeGKlm4KbqDnBX5g6pUCJDkcdH14+7RM4EKAT8KIW3RGmcMKc\n2WQtE41F+xQK6vRRfmarexRlT8LOpmal+HTmVS5Ceq0SXQB0D+K6xENKBBq2DqmCLf84zDY7aES1\nXFVDbAh9f4WssPSrahbPmojUf95tKQ2bzjz6b9H/UhInKHqusIqugBV5VZZZMNLNrGpQamG4Nk5M\nhSz4lNvulTcI3k3Cmbe/yUaU8wPhqMg1bUHAPSagGh2BWnn/zm20U8xDJdRm3h8dFe51Nj6YRQB5\no1B4faB1T7lLIUxgcRLDbf9ebW2Y/moGObrCeMFF5N4wslUpfNuLF22NQeH0Hb0sLbuV/E5bdKwU\n5CB9zBOTi3pny8TKMPodGzIiRH/MAh3Mx9FPrU2XyBdQauMS5SIwp7BMH85sRcUTsDd8mYKRvhLq\naDzwauBYdoUH2AfOwXLkraKRHVoLEVi/1mienwA7mvnfSJr8KLPC01UVrVmtKltsCr8xHwcMU0/C\ndoNE3mP+/8BWyzEdlF0HycSGKKHPXWQ6Ww/xR+wSIOBw3D6xqLuwonO4aNBAR/C0c4pYDqxszWFK\n2PV518gQrYOxZ+qSn/2esYxmc9yMYH/TfLbWYU3ZYvGf0keEQx8i3QmwMkhwf6XGhH5oqwHt3GtQ\ncAumrWVsM//cT9Ig7ufBdnn9cYX+oEZZVn0Ps+oZsu6OeYC49BT65DZIP/RpjRSPhFq044SwzO71\npJdrT8G/pnAGJouN1uSx3g/oXeGxL2mRsKjfLaXQxmgsAU3epk3YNNYkSLLmvLfsaNuHpOksKoX6\nL33F0vlUQCS6JsXdPGy877Z2C0B/fNmCDyfzeJveX+hfaat3xL6XvVjztquMWz4yAqQvBzBeOibn\nVpxQtUgxzv0UyXLiCgzgII1C7LdMVxkps9FVzXq27sSNNEcueoyUcCe+J/8ZgPjxKOOx9hCowaY1\nGyowS+d6GSa8wuWFkPw8uBInJhcMoXrhccPc7ueI8GIwRYGJ0fdxHvOdpWQMK1a3nSo+abX/q5CV\nWPSYBHgS8X4t3Ih7KiXlDGvKLbcpOwJ8YJdq3E+m4X8Ym555mXZnTYUIJFucgaB36ee89zDlDnPS\nb0jAujPjYKUD/OnXIQvGqQTLjT6vxB8W8DyTVeWuM6W93Z30Y28od1cvgfEuaijvEQ35FFNIX7Ph\n21ogSRvsSpmmRzyoHd6ZUFD93RnFvbw9Aoz3aAY2FHTn8J6QW6/tbYAZuUVNcm+OTQhtU9Kt9BjS\nTb4jxsjyjKqN7N9CCDw39knHKNiiRCYzU+MI6bMQZW/b8dsKexQJtAZHOZd8+h4DbDQdWzNR3vaY\n2WVITIYI/ZgK41bPeRS6otR6EiJHVPkmwlVFGaqwMUh4W/OPZOtfh+O0yexiUoaPrVh9DXJMzhIj\nieM0M360MGcD2waMMhKLE9DsdCprOmr8RJJtBtFIIpJjWIw7+OiGooTpNm5uAFnU7mgoQKVFQx0D\nHjbgwHf7aK4cdkO3F0XZMukgoVLlNd8LECJgli/AiZ59FVUqZRp14tWcsOeuRL5fVsdMIPK3vSaC\nIUsNaT5s7UZAp/+Its6p868haFNBudfeDxuC74U6WBivLVnSfFNXlytAD51ThAL+bHtX1POgZCpN\ncloDTyx+KcTAZGcl+5EvE9F8rpmuMdRNltDvHLlfRZSdalVSxBwAN6zbB+cKOXjUxBnNttxUMphQ\nQUbjcztGxq8P+CA6LJ7o2KDJ+ed1FEu2EVmD25jJ3fXpczdt8SJ+O4XnYzMYNydURd9uoaQgOFo4\neteMHB3osHrdUSNtdghFSowdStkwZsVqLE5HUrexJ1zGJwcJTi+PMcZ50wN0IAWlKL/bB7oTLl32\nOzdFLRh6UFULjSTkXEuO0cuGJBuLQfwDcA5pJLALyaMn05PsZikhWhQNOeCjrFHQMnLStG9D3I83\nbG2S3j2Xnqff3x8fqCLiqRArlQamXK6hxd6mnRNUuwP36CSKAwp8hZpUVVa0Sok4DOzbHJXzFHGB\n4GJ5r2P4H9P0xU1Kt9CpokoA/Llzvm/yMdD20Ocdonoz+duMVGFS8z183IKZ60Lkojs8LF4I77hL\n4n9vW002AMBAe4+MC7+CO3r6PiGH6frkS1hsrcnmeS5MwJMzT2BMgA+hM4ZTR8OJll8Y5HagnqeD\n0sVQGYjAcJv34Q8VNTr6uZB5VhCW2IwOstou3uYz63JxWvNiqa+iE9vP6fxXeBHid/Sit5nOQd4a\nf9CMLXR8JJKRog6rX65sjHFevLKlda8C1oi8AWItGEDEzjYQO1QgoIQuDnOSE6BxJW8nn8Bz2J/M\nb7gqbasXvwe0kfEhXVoE9TAmNcVRtNivDSCRSVhx6NwKB0rtcofM5EhwGQ3Yxq9ebNa5jRmpgrnI\n1utCvOBNZ+rsBuSju0rIbpCNPEiMLzNUhqTpRy4Lic3A8VxNngov6k5UI0FbU/1BFTAbmGPIiApi\nF5foNrLy3KIYGgOgLACLpld6Vew15nuPT3juZjZ+gGBX13k4ljNQgskcVXNPH7UyWSML2yEB2J6r\nysov6FeytHr9Yw8Z4+Y6zLIMz0f/eTzwph6Ud8OmSsYe3RUWq6lmJoHS50b7mQgsgc2Amuy2Y+AK\noSnBHOqzsfXKi7bdpWFTZSbcovhbyaYdPbhlceHDq5t/ywp8ZIjK8ATGm+JO9wjrGsiV4iTmJ1DO\nJYsMenwCAWTZ9/H+fwEEosCEmPxPm16n4ZUqdVb06GiDjXLKY9jWRBS8iEqEc1FoBx79zqRvBYGJ\nwShNw9uSkq93e/8HVjbhr9RPpbm4RaJScO11oBDAMUeDdB6+XQJY1Mru2Cbzf14L0wP3zBfHtO2Q\nB6rqOGvQYkTJ5/Pivr+AQsUD2N9wgJWQ9UYd1BFoMnXy6ukpvoJBRXXieVLvm5akm7/d4yeQLv7P\n6IOy3U3hCtaF5Fqp6b6lfKT/9NdwvbRryLtfo4M+SbrkNPlFwXmv6wg0J+Z2lzfHPnPXPuQrDWF6\nANXPdYhPgCJfZJUYXp1MZbrPxmPofXuSbC+pv8hXHetVcIpnX+BwTibxMA6zFHBbij/TK5R7JvW2\nKoLg0f5cptbW0Hf+Dz7Rm6pRwzpMkWb1/f+j+qW4uHsmlA4fpPqPem9iJaCQuTAHjBMizeiXmcHy\nfakho9mMyC9bQJ/HRw9MLh8Ye0OL55Z5uW7KUxAzpvhaf+gG4FBjPVkmWCKWCXsXd15YxE5z+7K4\nRszuiuBHJRRrmHVQTbjfHquXcCk63oLNIDNXlw9qNZmdLjkQpIyQ5e6LJjmpAbbJNvK7xIb6hx77\ny7ZeLKGwIxICtyuBmxW1+E7tzjR/U0Kb8gJX962rafr6DXmsQ0grK0i9DEbmPFZGA2wbmVVvAh1Z\n5ClhWMVus/57QYrbCAoDK/qWTpyC7aKvWZ+BoUPLBYtEBPVGUnKIrLEv+Gd5wJSkFanTp6TM3Zyx\nKrGH+kaVroYU6BGO2QkkVtFRIdOzI03MP9hnGp+rktgCguhCAqlKNA/avLortIuhIqLcK5WVyF+e\nlBMsB9TDyNCQcreWjvtBkxtZSUbpkHaU4aC8dduAOSYEcXZI1bhnw0gfWDRsiBhtOkIJ8KAIRDk4\naKKO4mrq5Xfon9TxEeb6tfByxLYaBGzeFnvvE5+VBRbAyRROqYjfJ1GoZuX5ey2wwRw3NM+dURTo\nbdsKw+3umHz1ZQz02J3u/ValJ3zvY6ZmFmMeD5KVm/XDOLLR3co58S+hfL/UuKMOZ/6meu//04GM\nk3LU5B/vzOCHfR4tiVIfSjouiY/b6baqXxpe0Fs9cqboe/8HkYNVMatRsFcTArH1wzuaJqRadQID\n3DF8tNJwD5ygPYOvxkR6m7pnQEcsq9KH3HiPEC22ykhButyiVI7KDDDZZYCaAT/Y1pg15CFsIogM\nhN7822YNTc5jMelM4Xl+/SU0JiqtPERNTlnn3aSxkAXDMcztW3ErZX3FmtAJwEXQJf4rmbJ2HBlw\nR2o78J8xnAt8kXDJgYrMksdUPO5k66KjkdHDouICKQlQgIkdpUUQOafWgElkvJvsIq6XJQFBHQd4\n2r0dPrr49qc9xmjI5h1lZ5H5il0wARp0l8ACnP7Eum8AfEyw9MBdzMK95kbonUFoRoDqUcOuFIHL\nptT1thsmnzNV1joHeJntctCVTrEtlNzY32NpHfjx1u+PgqSBDvpTB85wffQ9DcPUoWhyTbSx4M9G\nuCyWRiIWt4HpOzkCGqi4/o36WYOV/cQlmVTb2wz7aD0ZNTjoQ6vwAm4SoJ+JVaCtz8S8VWt6OExY\n8upJqv0pCUFVf77gzsEaXIulugTbHQeElB20ksQxSX7QB3yau023MUJ4v78FS9xLvY+XirveLWuE\nLtVb+bBq8sHCnPl56VOit7bX+DbgeP71muQRs4zb5DfnTzU1MC1KGxmwDzAzxQwknaxHT0j5IJWu\nUiM1rE3SIWMwR9Ix2ViUmy0yfHeKULHpThFpZUfsSEpPTtNGsX1gUsD71m6ezPuGW6zkZ2Dl3xt+\nNQhFML1ZS6D+tPokG6jSMyyDvWbKz3KZlFSQkfNchl39zdglU3un3pVKUDhmzGweopThSrOehDdl\neRFf1VALu+Yzzd7eGwgp3ZbJYkm3+lvAbmABvFxh4hava2/6x+QYwJMJmI401gjRxAMCHyl2d55h\nk9qaBlWvqQQiU3N5Vt058IAh3VEFD56Jq4S7u2hBPi/hJCl6ABqiD+JIVXSz8yMiutvTZVA9z4MF\nZIibscQgYvR7JvtBMD1HgP1bF4/YC9afnGa6eCp3YLGUhGdohsunxLDwbFgzQ5+TzbKYOyFqwUf5\nxv0eA+34p4hskvE20KkAW4OCHuwsaiB70okLcolbqAqouaEdMAv+OyPj2KmycZ4SeahvXXcRdibG\ns8A9fJnvoKh2ApnhD040YSZeFbwS3Vsz/t4jbcYcsQRF/n3ZopO2oeHw9al4YYWww9j0w9pRMv6a\nKX4/qPSmcKktnq/+58UyKfcbugUCptEvY0YYW3ZWc8+EpbZm7lwym701heK5jV3X5CrBeLEt9n6j\nUP5ZDjt2aKpmF7mmGqTfQ2Uggo+QyERjWnihDhW8/MAZiumycun1AzI9dO0NWQghoHcdIHevbS4D\nldMg7c8gCQ+lGFfC0C+PiLjiO7cY9U7bAB365Qo3dUegVa92OU/VqZGLbtWWKe+TFsBOSY7OTnhB\nCVd8vPcJzgEOy17ZvIbMT7VQfvq0zMIMFYhKf/jzUQBvR3vBeApi+IT/4pad2SyGnLZLBkXLB6wC\npHe6WMntLJXpoGZuLez3pWPfpQ+H0TvTyrfMdp3Ml6su/xbr07zwKW/wNa7uRErgitIwFIvgAOr1\n+ePrjYM39lUF0Bv/KKLCqNmSWklXbClnFcHme2lnA//IqAFrB3kFcZUELZcr/xE5QoPQxuYlBXKz\nkvppkdLcrzhHi5wpXVARx6dkLltuayySotXvTXBgEmtZlJ8eOz4k/oycVqA9uZ8/FZYpgzs6QV58\nZ3tDfHKrel5f58ZdIOuAP9lA4GOAQpNvH7pyDkCm1DWQtztz/4xWzJL3JlSm9BOgIraLGeZ59HrW\nIN+IeeFYjTLK0uUNETMAXAq1OAPGGqA6/z7/x07f6+jzxdx7IvqT9o5tNC+yDwTxaj/ROGGlSHcw\nN379kNzgtQxq1bs3OT+cKDDysI0hYGDxWuriy1J1BmGZBxHqON1mtpQkgK8MQn7gY9LlXwimWip2\n7GCkebY3WqLcfw8KHeqjhCPNmdJnlhubau+t6SPBUIFfDZE654S7EhgO5KWP5fRhw/xj2OAnqnhq\nJ5+fstfvIbIKsWfx7eK/kRg1Nm0xkiitP9o1BprvITsEO0sWXUZ/IbQCM3eK2BYikdwfF3I96AtJ\nUQJgp0mTqS6HvWJwIJ2izJPIOZYuQhQXJ6GLxZ4fb5xhB3c73ad21rX2OzgkJhs5nNNZ5SWILSB0\nonv6pWxHnwaQP3o1ltFRC6Rd+1VvabzuAFH9GAwg7WQYEyvbBMU/mJixaqGG9T0a2PteoLQJ+NS/\n591MEUYyL+J8Foq7cicxoN3XBmxpTe3UZgjMLy8aEQbKdUqDLdt9Guu9QqAtQ0mmnkEg/PVhhvPF\nL/KdiCzBUC02wGt1wB8rvxXPnR/dImylVQ+HBTsGWFMLGquDxx/SLvIJpesmrB6xV1neWAhO0hvZ\nDGsRZdjB9P/ARSAO1X3TtoPsZiyOrePkqFTCYAKVMvAnJbQ9xOh9U9Dee/FRIJ6GGW0Ae3vQOs1r\n5fSktdyexi1J16qb4+oShIDPYdJkkim7BgN4exex0/3ptwKJgA+Mi+LyIz+v8RFrFFtJdVihV36O\n37KLXJuroTptxZzoRnQZLkN3QSPSAbYksaa+dcAb89Pm2tY1sOuwll14yWJ2acYPs+0+HIFIvC+W\nNe+2KOvT76weAiX57Ww+WAVw6jokrOnvRLY4FjHZylpSN1CpbjGVA7ZlbqA+r5FFzT9WrK0arhiN\nAGJSdAIzlnit25CfK8YNqyOFi23gd9UzBQyzt6woR0oyOEpRnynYvwkPOyYhGPMP8h58UCbpfxkh\nTz9u0G5lPpca34p1d14g1fno4+3SM54Cpxt79gHayxyadsCOIf/f4tR16rH7g/Mja4xMbrH8CK5N\n0JXrEaUyJY/wlzLo/M73+yqbI8Ftdz5GSOv+4nlUPIX6S3vRRJp5aWxYT8YKjINtMKDFAzg/3eo0\n6nFonK6FKXQwt2tBKsaqpV7P7DCme/tgIsMHKX4zJGyk9zSxyEzojDOsgvcojainzbFULNS7bWsa\n8Dx9cMnAEeyXb3hnFjuc4vZN10JPY04cRweOi85mB5R5fe9YsexBRkZ9S8NACcsBaoi7py8JVQVE\ngMzU3gw6mc9qK07UJX6MUqFYzvrysAmcgzL6kJi0pW+tWlulp/lZT/splRsPur51AW+0+JrUhwaY\nsLjevE+9r/L3zGnICpoVgGxoVdIBcBOMjz15dcdQUq9uPQRyrwx/ATXUx/2Bs2ArRIa5soWeEXv3\nkQI7Pm2xEt2QkIQ9lh9hWzF4cATlh7RiK7RR673Ny5kavIw059aZp4RZe7Qi+C/ELlrLLpz/0l8K\ny0G2lv+Sn7udl2wsXpour9KQRyRXl/rrESOxOl9L3tQvDC+2gPBOL3G4SvcAd6UTX+3bGRTc1Gxw\neLgnCWbzaQPUs79e8S9xsmbWNpbraM7AuWzbM0bQVk/H11oI6kzmSANZBQG1OFNLuJMeUlNaulam\nLXd33j5GNyUanCzkEdDQ2ohsHr8NZ7AB8NZH0nYITiYoOS74ePy8F3oitU0YPZ8LkSLYTFpxHCsV\nxr0jUVSyv8OnQPI0kc4FmxykN8KBpedjD9M18Li6JBii7nYM0r7Mcikd/awe0VZI1+5dNbQT20Vc\n+iNXyCgLAxN3Uu00Dl53oQsaXNO+AG5tLGQorfQIhJ8I0mFtZ62gyquIc91uNQG0rgZm6gIWJpZH\nXsm7tQMwRkIBE07IMb5kKKgnLp2OeaJXDtVSKyZKHbh5n+Alu3nlW99jwp3v4iKNoqAE9Tvm8KbD\n8H22c/sUWrbahfcwp5AZ6g0dSqQGUNpiM0MgzCFlfgWO5pxkkPdrNtXSj1vuMrcy/AYjFKJrxZVP\nuZQUOGqroArhGT4KQXKvZgK3g1iX5BqdbPeffuWGgTYyNEQ9QiVXp65So4gZJxDCHZZI9SshCbSt\nsdj0FRzDbNbH6pSpAd31Rz5QqcvEgiAm+k/TcYeiWOsDCOD2XgL4VDQctgkc4+EbpiC8HS2zgpW5\nvU4Nty2BBUkKm7OT30GHjYc+INJsvlDgLHmG0Q54CS3h0Iwfij/kNBPpP80ivIuLdY2kr0DErcGN\niFCuTwDd7W7c2rfwqZj3RDOqdWNI/K2pcVCYbvXeyxrMKlG2dyLFCVDApi6zHJ41bV91EMqkGQl9\njvXg23fPhxQkH78783aIBmHHoLp/JfFg8eaJUdYc9MoAERoktHgsfCiiIn3el5vPjGUnRSUbE3eK\nQY9xXE8RBu37NVaV0LgKTTiVw8IiAIyJJNGt3PIEhdQsFXJ6sFS5IrZkMiJQPBSH2CRsQj3vAyr+\nih7Ouv8OzoisYOyDbjMls5M4yEqWZNPm/VHwV28hvDvs/QUoxT9UbhXrg6X3LciZ7gzo1YVoBBk6\n5A2FfAtZTNO7IBdMtibVws0Zue2YJIblbdV3Noa1jGbTbCwD7c1q4FU9jLB2+CjWMWS8Zv7/3pBY\nsAt7jbN0tpN8RkdOoao/+HBAZDjVSSW/J3NDcm+39j/KGTaRLGoUIlV3otu9hzB7gjSLm4xn0lja\n0MM9gwIh6SPgyEtkgU/3qe8NLE1xzuMs9xp1j3A7ukcSStVbV1os8o85tGsyfEJHnVU8NXJDi69X\nD9xdlsCQLFfyHa6/dPhDO2oPhu7RfBYSbhRRSjB2KxRu3h9+PT0H5L2H7Me2DRo04qOPQF5nTN6k\nvgDI+9CVgVUG00pHF6SoUtmhuCN9cWDzA1ZsjWrsp0pivHXtmu8VN1vUV9/R/gnIm6aAwNeXvPFV\nvSc4g8Jafw9GdWavOXo81FfKQf/VuYbckvqBdV0d2rWua6qmK901mKSOH2KdOKeWK6Hr88VCuWaq\nz2SqCofXE9JWGsOdY+hKBtvrYMGFaLtLfG/RJ0ZFBmUMu9woz3l6M7RYuwE7iZqmqOmLjiu0hfao\nF4/BDycexqOgdCiJiSmC8luTFHJAti5nZbly8iwmBhxeo6nDEMfUd4kK3pXBksxH6PvYnwmmFumP\n0lFYj62IxGpq7ak3CY8gWENaTY2Wkt1vNuefToui+PS1KqWmSSm2wxHhl/gnz+QLcl0VssAQ8HGX\ndBXGMoJ0nvIfi/yqV2UCJlnZRhdP/WrV5rt7L6kkcORz2Bjf6r9q39kwlNdHxqzUD+WhbTqY5Wym\nGJxQUlspvfqit7U5AYhhXKYKXUKE+vjvBsnNyOqS0OyayaAm0byJwum7PLRmxhms3NrdbzxKyVqU\nlgHZzF86GbsD4ckG/t5r42Q9+OPWiQ7zZD14EDWTkbL/V23Sbm3Pcc2xo920dLlXg3XitXPx4J/f\n1x4sn1S4DuUTK91HRIgjbi2q0a7w+SiGC4Ti04cwH5FI1ey7/eq6ZwAeWPlg8AC4wdgyTnsZM/DG\nK4ftUDTzT62xoT84lkgWlk2FuPdy1A1Bp9JXyKmGPRxIZ8IzhinuVcCFqawWwQH0i4MwvqZy1UvZ\nCTqACmn0iT/Ie2EVLQloby5d+z1D2RPeNBXmDGlq6wClYkxeKfHxSVxJ26r3UaBPRrX4jHWdT5Nj\nmh80ndsovyfMg2OQNp8gdDx8eTw7v7ulqeDvqy38IFGICfelactxtDzUz0IP6XpMOiJ8+DR2Wbn/\nZG01Sdt4P5W6jeu28+IpkTf0Ywa4czQ/kQLRQF33f7F6OTlIhTTiUbe/CVXLjKWzZW74f8ZwFMsT\nlGQeRXqci6Zv2AdorpWhBrzcOZEKJX0CJ+eKcYGqAYdKqevLBCQUJyenfryjMVfKv1ZUMvy/N9t6\n08vuQm/qhyJ5SUTe9vJuaq9VZ7Dys/I/9SyL4Kbw5TUeJpihABiOqU8Xi2xCSOcuZCwRiJaKjyQV\nAnQYp4HYDfr2lI4nPa4ACbGjar8WPvQ/oHvQBP5EpYlpIz1owWTIphZpNxUH6KInJxYNhHC++ptw\nCKSZY8mOyhdOvIW2LaZVDCLa3vDQ1Vdafo5wo3NzkJO6C4c9wp5J6umHMD/QDx0CrPYJld9exX46\npX81IaI0sm+0msSQuSuL7ww1J+FXVwdYAH1zD9dwH2wzC5pyU3aJDdgPOstj2SNrlNCQdkVh3hRy\npmR9zYwtwW9wrQWPBhgttYh4lrAyitbh250hTThIBtoVWpBra8tJrFDDjZnXQIhNBzTNdo0WExYy\nfcCrdHUUG+/1uYjrG5igstWlc6LjC8t8SjZ/JXQIMT3F7Ln7KlH8odRowKaffR3adtFggsrIrIHB\nrobSmwMvUT7DKrRmt3wSVkYuK49LW8FoDumjbAGud2PglOhp+fRxcKsxEj2cxNFaszaoG1V7J5VG\n5P/UJliaZrnbllmOh9sbphZ7+WG6t0yKcu+M8KSh9K6Wm55d4VgNtLB08RAE+wVkks26aTuqaHSJ\nJaGOQ04uiGYaCf2UEZq6MBQ4G5kAwdexIW1jeI2IZaU8+U2GN4IC8G9sIckULwo3yEoDqaH5wQr3\n9xPMCFFO+HahrEftoUM2nbARz6AR2frgbpkFmDv6Otj8+hEuhGG1g7/6QyIBmCFUGwD2e4cHzMcu\nUBSMeDg6FipqrAioSi5i78HqZpAluiD3hHP4yOjb1jYihJTrD/TE3iS25lTByLEN78T4TxE1zcco\n/ORiGLzFzRSwhoEO/BVnkAINq5MyTbWsKjy46zcnJ14Ie0dw9NFyLrio/eWXR2qIfBVdRPpb8Urb\nFc92B9cAURMmFisJIJs9unjc9sxVUyQqOXfb0irgMVRBFJhzqZuPhDARHLEwDGxvmm5ICRqd/A92\n+uHPbpGpOwizMIA2kRhAVVIxOELf95z1tC1fmHc87Qi8qObG58h4JS57aiKBbZTtXTsdx65lm/rL\nGox0kLPF+nlHHUeOefHQDiqA/3u8U76botdLk+grhj8oxbqrkteOqhFIHOdJeidY1eaFcAI90qAO\ntjDxcK12xdW/h9+odT79OC/3oz3YYWwQaP5QEPq8FZqfWoC70BqtzpFbHWRfY/nBbT94VvpOL2d2\n9RiVg2jme7WRYqxoyVFIfit+sOFX3xrkMsTjM9vsWXGP/x4ywS1Sxlamy9WpSb5yTZHJDM2CXHoX\n9Bw/I5XqlMc7KGjGfA9PAMb28O7T3+qm5XaCc7xauf3E5CPblE+GMe146iZ9TL6QZrVNJGwl3KFr\nC+CLBKtzxyuoWnjQLdSt/J6tF81Zv30VnkSBOBHWglh9wiCS5D9x8hkrVPM1AQqrcfdULwFnHK9r\nRQTYE4M1zIYfdLwBHdztqyOOZBmTpVdCKrYmwxtOn2S1stX+F2+KLVTEttxUpI2wNcJFuzKwdK+U\nmHOhHeDTfx9gXjBbPt+eJ2GoPr7stkc5smg3BsdvwFm9t8ZyXKgdj8Gc75DLVLmqOFI2qbC4BxMm\noU8AP2pS1i6VIhlf9yN1lsxiVslTxrvbMt8pmqquCOdNb6jfY3VqM96AvyAHvDgy6mtqMS9sQ4K7\n9RkI+KE7VcdU2EMVOl1dFxPIUbRn2FpLPdeDrQgr3gt6N33KJG8f+Rb87nGKNm2F9aOb0Pzu63ih\nn00ERxkOBQAuj0ZCFeH8Y820Y6k/ALkQUMctfQdkXy84DMZXqduO5vP5n17wBC7gzFdZeEPqO8w4\nPSIfkWbMwyiNXPD2EVtAmuuG7Hc3OP7RdDULnEO2QydNncIWQqnBfutHJvfZTS32v1/cG2x6Lj+V\nWt6q8O00/Lqyqtd99GdQ3lgLzjLQcENaT9goC5NCuM+DppnyW8WgQ66WAXSCbXCB7whRpfTBZg57\n7Ci98Mp2VmoXSM/ZNID32X4nNPu2LqEu16K1CNILhdt+e6mIPXWK1vVZ9BlFe0TpUobYXgCxLMg0\nSU6BsaLaM4B3R25WRMJUCyqszTG5378wTZHNELMy8B7cyfSLKN7XiwcFfrQg/UxD9OPGGNbmiCQe\nK1XlUm3PVwQzTLWffMSATlX9/Z9cQe1bR5j/eWABHNAD8DIsgafL9uhrjPBztBjOXaGBjYsFX1Zf\nEK/PsEaT/aGWt+aMtKFQnVo3xzSo1sL1wwSlMxwpRvrGHjvE2iUrJ6305zqaAXRiHejT5E/OwIDm\nys24YGp2gpzjKsMSfcSf785IPkGbmruvZKQtDYiIhGrFFCM0Mel5QrfyhDbukroo2a75mL8KnY+N\nuYCQyBrAAtioazBlzd2fkkQAT6ovy6zm+skHErZ99hZHAicwcdJSHhHDdzRXoRUU7u8orNFWps20\nh2SvrYu/UEWQZu5wf5FI9TahUx9rB3hQpikuGWbeEs4UA2ZIE1XyOxbk+oMvzgvb2r7VNMsEdOv/\ngn21Wlpz4xNLzaCy65/qfd+rmLa6DlPK3F5T/jtZebtGS4eWE4mG6JjmYy1p/zTHyZMZm1e0iCR3\nh78UtSZLFHDtEfqP52ZtV9r4kmcrtMyxCFxXO0MXFim5XigFfl0xa59ntelwDxk2r33iM+apCWaG\nsvjCPFrq6ICXHTPKMPzgPu4152eEdPPjvysZ3STkctChlBRC/vf40whf9HrrECW20umEPngy2zXD\nh9Bk8sR7/jcFB9hCD93wKyORxtffQP1P86seWrnlS2ovHvdy4MlXUx+xDxl+4HAocyebPSH7HUZz\n8BW/p2H+hfQ3WMh1QrtyQ/gpB3qWsHovt8MlW/RDjE/boMYpvOpIhRjgNfEEvVWWYFetGPEtV8EK\n8IbuJKnKTyPJCpDfF1bfTm2dD4+PnFveQbwvXe9S/b0oXYaHcmgPkWGiSfCDeQFgpJwPnQRUEmyb\nPA0sMPA0eZp9xsrwJoXzgdtaDp65cb/lD9rnWczWwmd0vdKcn8CYF1Ztcaq3ENWqGitQxLByw3z1\nMw2Jv/zKu5z0RdbAlJsvpwjOY2zr9A45etik33MzcNph86DOAny9VDKNLqR8R4PgHPQ8XZ3Jh070\nEeWrxw6Yy/TPfZjgHc0Uy9W31PzUDWzrHNCV4D7TDrsjVgqqQYmKDnP8f9BEFbW/62Ir0+yJ1jSO\nUoAgfnPQ+ghWY0so5PNV8m8+bAQWpinSitVGNcgRkorGKa7h5KAmBlqakrH2AKzg6qneQLm8imFq\n2bPUWWXqIPsxySApa0JswLYInPNGGQ0Gk4kjMZSplUngGPLExJOwu8wSOpTS37cxCagvm3Mp4Hmd\n34wZGW0RkolR8dZErRNlBIvJYN61Gxsii7V/9AT0ZMYB4EbYSiAonB0VOiKPbNf1HhlE6bO5e7od\n80QQd18dLfvuv95reOM+i3mJyN8m678a5SFxfkPKCLhkE2ZPpqvfvCh2BP43bd4eiaP9h6Et9p7l\n4C0aKdxXLBPgAXgX1z3Un0iL1b9Z0UpWcSa0dXRqUtkznyJv+OHzrQSIaHPbuIy6UiWbvTvt+Gaj\nmw4GrugKsmOJzMJw+tlohL2x+dD72f63n4i7txnx5GG/z9xLxO5saLNFHX5FKPqSnEX5paZPZMl7\nLylkgVhDcA3fmTMJQfm2p3GUwIHM/5w+UzeC1vunF0BS70WawxArXX3gu3//OVLFYT57Ku8lxGKS\nIFRuF5Wwu5kqoMA/x+zqkiMUxFGogWh/BxaDQPiBXFk53Efn6qXqrJxFfBb+0HxJDUyGziMAPfX9\nOCHOkclXq/NKu9cyNlXcbZxLfnaoqvtH5LQ6v195nNIt0OG1Ka0HgpEw1wIpjbA84k3B0AHUgYc3\nfku9utvycmmlQ9OHQn8q4HCKhopMmJr3iQLXIYIY8tjyan8UUH4aqm7yzeICDPolmujT9agEGxXj\nziTLOVBWQIxRwg4hkoPkdgM12+CcUZqkBBJ+lF2auLS5uxKnIGbDKcmOjipJ3Iyi1nL+IlC8K4+i\nfu9ePIXs5V1PIx8Ju2zNGNh0eRdtoLi956moZ2ltja6DoUn9AxvGenA7FSU4UIIaAiw3q+vKWT7Y\n4HOSrqr9qOYr9fCW6Atw+4CjgNn6JYvgS6qHboZ9fdeg/c0/8Vo3QO/AZ8yVaGXDNj5WdOOEEbPV\nt2gVsPqPbeT4Scs30V4J5cGhOGNjfM/IvTtJxs6dZVu8b7D6lnm8Xr8+s7W484/TnR47gASTbJUl\nVwVRrQFlpfnkJ/3B7lpCYqqKQ7zymit3vMFw3Sk149Dpo/6ILkDV2KHjouMGiK0oK4VXeTJ0RjCj\nE/QFtpqEfVGs+mRymcAJa4e27YbEZR3ymEx+4Q6KGvKwZxPOyR2Xc3OJN6ZcisuZdngX37gMPEKx\nTUzKI1Qyl8mcDz5cMEdq+6E7dYR/+EXsb9/0bBxGYxO4KCS86hd8ke0Jb4myBg8JVEfWfbUMQ8d8\nerriLfOZyKYVEaxLvTCn0FpT0xReuhKh478duFmIdysYXoDLn9FFPBuQY6YLYTRBnNMr7FwIqzdO\nV0v4KswGylpyo1MqkSH1gcaOdtV3YHxncjPmOYpY6pDQ0jhONKSOhie/VsqUtRfMocI4QB/L7L1W\neW7zt9BrHHp2bSpzJDKmyz1TF7f6ez4BLFwFATmn29DrQXXkIJVEZ59RwJjhYdxnWrXpyInryyOv\ntiqxDsecFJ4FLQ2wnhSXuJStF+uFgaMm57JMP8n1ksz3nSjQa2Of3QerEcFt+e5KcepdZ8WuTj7l\nc4hIB9JMfzeUftH+EbClpGwN6I+vfiRVO9aFH2JZxDEGOBVzVP6dmOsHiPDNb/Ah28r0bOH1r2zG\n8uPDPvj63mcfurdeCNDk9t1Lx/ki3sLwTygnky+u20Jfjv//7rf/y/QjCbXy50m2X5OlsPRjvfDN\n0usv8zL4uWCkRkK1CwuLMZaKXS9cdPXUZ8pGEvvCQoif6Gh8WpVZSNZiJUHjAI2hWUjj8zT5G4ph\nlsGTapmdiUtPgTqGo1IYj5vSLlX/n4ghFIIf9vk61mL4slzoSAuknOoEwifT38TDPeqjKw8hvn0Q\n5w23IDnvdByiMXt7oNAP1lj7CPxeQHKoQwVW/lQKxhOam9EyDAzfRctp78qtaWWUQaSDxqoux1Lv\n0dHEd0o9NbUN4wsKzK4gaKxlt8Nwy8dx0IytqxM4woPLDeQBnFVA2S4BOY0wsF+yaWwUxoxOdx5P\n3tqdIDua60nnlwbnCHL0h4fQaKHFeBlehLABWC0qf0q/SPiFxfPT3FcIKtWgjhfvu6Vzo/C4/8y2\nB6BOpuseaDxPxU6HDs4np7N1qUw0ymAy5UpCrmzhHM4TyorSvhQxSOe2G6vRnG9dA/A1OaX11iuH\nKErwvPEdGUm1lOrO6bEAwf4de9Ons6Es5eHbpPo2wiAR7+Jq+WQp+sB15UgCHu38nkktwfF2t1Q9\nR65V9mpfKWNk0bSgjAzqQBT7WpauZyvI62H9+shuuK7Uz0ZYLosqb7USLzeFk0xQSl40WN7tJqNb\nmjxjIjEAGZoJGF7Mllaw+fNFLjGPZS4NqCuNB2k7VOOqBa1/YgzcfG8Dnw+HedUgLKB0IQ2psrV7\nEkW1v8IhdcjnMkxctGsZsYscaMXk1VZdhtIS6I2AGXFmWpHeZh1howHSJUqDEpVVQqvL6JSxy9A+\nyUxfVG9iE9K95FyQJWdkVB4tgWgPGxWXNCE71lGPHNhlK8Sqa1oTVIWSGhOIVPAscJugNvyyzz3H\nS4FL39yKgvBgPJIescvnpeGwXhWy6YS92TadY+jsAMrB58A2z9vfcFDOB9iNm0IkG3YQS2wcK2dm\ni0eUmU/3yE3EeLUB5NULFGXzGJ2G/DmXC/X8LdaoeNw/MXWiYT/6klvBt8SQ+EnD+xJwlQQfDLjZ\nHv+lsouZ9kM/nLpJbIcVaUeM6ydq5TGskEIAuuMrIdLX6JNmD3sq5pf5INcFXZDUKPQA1jpJh/kE\nhvnseQ+cOdFHUOd1NEuzPkLj1/BsAoyHkWlovYOVMkr3O9Ldt37E42HyCzp19LGKpKyMZcDkSyvz\n/6BjZIpk0eGi2bTcVIGkgWwwLn3aVydAnaG2ftPtTqOLdH8LHvCoh8pp9lLLfQvA68RW2SNdLQiY\nDqzieKry0fS1Oj1D6bpuAYquFlyv7H1T+5azLsxa3hEfNBQIKNFS6+m1OJ6gLff7TpjI7eapziS8\nf6JM8plL/EGkLhW2f81ieKXtwLcETAJh4lfhFym3NgqkudfOkdXHOx1OyJLdux/cO6LqmH7Mt92p\nM+kFrI+Dh6fEsMa2F7RVmG7NPeP1t0McDO+elM0w8kcqGsZSfJSF1jpn2pEUgylmRMEId6qpI7UG\nT82+M5jFuRrAeAeedEuz29lO8jMT/dqUX2QubBVRocUdl4+blN8adt+Fj6iX7pvMAdau56vgcTza\nWyW3WQFWlAupIBuOt3Ot0UJa24Na0AyDBKEII1lX5OsfsWBsvqqxMrSWLCZdQQKuOHX1pMdPKUy3\nyFcaS13rROkxADv3njnT28p6xk33dmcK1UamdIY1tKmzaB+SsMF63viKTlWu60p3DJtZT415EZjo\nHD7CP20zWWAmkGUv8e9UXxcfRFAHf3rki/Tfh7TFj4bmYeh/HJelJyHZiV+KnOQ9LDGTyI7zD6Vd\n0DuANeThE8SGntTjELnv3He46L/uMY6CBrsqPdSOyS+t2ev+WX1NKWePy37T7yLEv1PatVinkwVG\nr5ert8Y8AtMc99lbj6kJwsl6+EQSx2gA1TyCqP/0qgvDlGVhLE3gaLiTVThb65I7g2CR9LjhRvXR\nWGSbfgcQLV7ha+AZQLflwCZyOjjuUbT+WTHChlg07kipeBTtIeflgiJRWRQ5Kd1AqpExnthryNiN\nzTPvJ1f7Y4C+cylbMOH7vD0ZI5yVlNaFSBSqfNt4SK8WxIZaPPMQ1s/YHfRnQ92+Dd2NHedHSnhY\nI1MDD9lxmwyLPWBnfExZfUpc7zT50Ip/mArbeTjoUEeCkM5VaAN26Xa3uSrbDCnsDcak5s1NmCbu\nOdMcMI5dzDIhXFdd7PEk8PKke/HGEWWiHPwU+kIyMrP3En7v+eTzK4rPF1cX4znmcmnQYAnlZRbl\nUh5cISEB2EE7wm2d0XRahQJ5YrdWiD3Zc0VJ/2taXsCpaCFOuLKnSq0bEXqorh38dojZyels6IPl\nOhJaXyNUqVpj7WWRUAB2VSEAVCLgPLzto5UPkj0YTWpzfNvcT/MtMdWSfzkck2MappPw56mGCCXY\nSbCNhK/eBwqG5/btc0CyjB5Ybe8HD4KiO8tmKFzcXYl58IiKOgKME9vR86o5KhT3BdJX1Rm6emhQ\nVeZ2m7POe1pNblbyI7qH8PN022tFd6DMdhuBTv9PNnDo1vVmcGZ4kTxYTONIHIveQdB8GXnKkF18\nyBqKqsWP9HDCZ0eTymA00dwpY98DgqwQ7fIq6+SXJ76m/HN34LwW9SSRDWdrWydp0kdJHtouNEEc\nctvMBGMBmw/9SGe1DEefZSbK36SuxnlSkOzy5jIkFTxSmY+39/GCtH+GgbIIODwq2qWq8Yp7W8ws\n1FfcfFa2vYzkUm0YxSYHypXBgkhsW6gAWCkrJYUKVPsMx8rTud5RAKtGUfhmE4IX6qXGM418POra\nJpyUnOmrBMQCKfxE7x07pVcMIM1f+3HGDb+J5Nsr1ZK3xh45hsi12N2JIGhd38DwRm/1wb1XUfWn\n6AKMAcsfagxtkjOYgwvMlrrIev9BF7jRDSaHIc73j+T+SOGyvy3P40AaFCUEPEqxxrMnf48UC62w\nD1yqe/FetXrHweyEKdqjEvGdFH1tni4rRoSBO99SXxfO/D2OSbXw3c1KA+HWItb8QzpoMg08TA+S\nfKMCxOP+y76Xj8iE5s+en4//D4gSLypdyLWWfdeF2o3CCfv0UWTwtrdTkel5jgOeoJAS38p1Y4g3\nTxzI6TfPQ2uworNoX7ZZZ+lQq6AxtMmGK/d+JcKY/8/Z4b+xvPa+TbH8nGa8JrONLEF+vSC1dSRp\nLfuhOGvAmxgvOzjNUxp48NJzhaiAifANsrwlxGrlqRVe7HVeQ596lueAS5CaulYTT4ftnz9bc/XU\n1i8VXddv7PVrOlOGWTGYbxofF3w+MfFwlWATTVtEHOijSZCYeyKs+flVxUGglTGIFKrOKjYmZZgv\nZ2d50S/YNldLkZjGw87zk6TXFQMJoGueUcMBMmL1yzyjPjb7+oUit4lmxGhYy4I9JpmZjEjvLrQE\nPQDqvUmTfkSuARbVMMPn3IE2sObWzrfVYiwJ3lADknxcYnm5fD1/70FBng98QsMr8GYlXvX490rA\nt8lgsK5et5bXI7YLyfGsqSFbw8TWvnlWYldugwvmaYUk16TEIOIyk+7x7Gfdk90q76BDmPsEbZ0P\n/FUIamWNyOe3LyL7RMbNFl8yq24yxIwvn98FsUwAvTf4gNtK7MhllDkvUJQCZFjKTTB623qVQoow\nJjyZ911BiX7L1wD4V/F6BW75znMEAxghzSZPJ2Qcd1hjDdJxTh0bmqChRu995w54ke1UpQcuGmxX\ndx9z1AXbHY3FJh/MAHyqqaa5ZX8vVgVf8xFG5APxNcAZFADQI6/J1sfOdXTYA+9iYDgDRFSx9mI+\n5vuvlI31P5hMZThvseQjaleiNOMaqIrlx0fr1aG1V3AO/Z4kCpwaZDnEsSS5VbRADKZpL2G3LlNV\nVM3iheQfNY2kIlqItio4gtJISXoehougD4v5W2Q0s+yIlgW72fl5ne/00EHIv6XwU9swHuk6iRQ+\nahcMubv+hbrEZkkYm9riNg1HQrFaZelWxe/0pIfpnYoZTby/nSdV3izRpVbGwOc0yCyi/RNEmxrh\n/6bDnJq1d8iv60Wy6kl0+kCB/uX1Kh+Lr2+uXaICyxJPytLERB8BWLAiEteGvc9Ebw1VVr+zUuMp\nMp+lbD8ViZcmv1P1TiCJdNjEJE3J4rGHP+TZejmBU6oX1IYHOh0nUU4S163+vfq84XPvK2E9LN7q\nulJTyFBdJvMW1DmI20V/uVhBX0voO4fnjjWlx850i2cRlyACJO639a8N15xp121cTrAAkI6jsTKT\nXiZWcA2w6coPO42ryTsdGpeioMXwljN2K2SnT+epk0xQwuztM8JPkXJFey8Djv+A6iJLKJvSb5Hw\n+YGqKmFcMEtClWLnUv+NUw8eDER/3TOoAWcPmJyqBKd2E0/oKbJxv3WOWBUxIJkdBZRg9pMeOQNj\nVB1Qc2kZFm55KjZ05sEAFbp1K1X/kLAhJl+fnAaplTRiJdQ4QlwLVFN2K3VTzKW0TIW4oLaCNjW7\nrJW7yergm+hP1Kv4IUfrOTuPHdZdDgbK9JHCpqS98Le7VJfSCmIDPT/XYfzp7QzVfBW6C+IC5qC/\nATCcgssVli/NtNXuUpYv4c41XcVDmCFvCcFx6dPpu4Gk9Ku+pYBy9RKPu4tnud/qoo8L9EcWD3Hu\nZrPSRjLaKNa1Bh5j7MoTfYNWoHR7XmTWrnxh/ayjcTxFzIW/1r+QrvoLXjnIoALjWY1W+Dr0FWuT\nVfFL5cic4wWOHZsfe5m+6A7tvBDIRbbYwEgqhgIuvg86xVzAjqeFZTkryOvHfyRThMM3AMULsTy2\n538eegadyQNObzCz/7YepSdjAzszFGdpuMHI0LrSiqXvi8byVmN8eXDkTs5TczBrGRi/hiq0ycUr\nlfU9xRd2aW17yN+1ILET/N/V8HqXN3+XfvE6L173kj05Y+9Rhf1Ydrj1tnW1lJQI1bhaFQZWvpVa\nVg8f/kzRsN34hiyUdoqEUonO3xzEgKC0bQC440tXATm/xwPYWA0NHND3Ue24lymSozwWp6yg5T3Z\nero1gbmurq0E3zCJJulJ/hM87PFMtap6Mgwhkz6dWKSQXT9AbPOf390vVmgu528PB8zEk5WJDjJD\n9irEfNT03ROjbhy+yl4mfEcknMe3SJDNZzUe1+TejoxmLCeoYCdr+Api7wYTD3pzxAwfM7kNw6AL\nw+na06W5sNh8tjyUHmHHVM9quNNMSsBx6rFga9B5hQy3YYXODvGLHtC3YNw7X9j2AgeVxsxpez/F\n5af2eEr3GCb4SaUb0belNdeVYyVieAm/yoWf+JGpXK9OxcEyfBI07znIdiRpNsjFdvxBMfVHln80\n09pUQ13syUqlGBd9pVTyukO0z7NQgwNrAnVkI9LTzebehN9Btvv7drfUf1AklCKPGDOdkvuXTKAm\nZOZ2dogpjPpKj4DKJI9cNmpC3Tc7zbTHcWS/xbAs7j5UdNcFuSw0bi0/cQwDZW+uz1XQ1Cd5iA+6\nsrVxK2EKf/69tv4E9okAcoykBijspu6O3YB8RYM/nUfkONAhWtS3iKJ7Dm+TVvA2ep9xv9oUwW3R\n2YbJjZ8YmKcU6B0W8YmCxHkKlTczDP09ohNnTDf5opznp0PLgAZi67/4b21+We0RFVgdNwYqz/1W\ne6nvWChKH8NlExgaEUczRDWCCt/ZWbYcMyFVfuwW1Gqy648nj+YhRR68PJSkNdEJxh2HITcGPvIk\nNA4x/ADAzxxCrat/MQLesE/k6yBMBBT2vDWzL5gGyADMDefwMZ1irBNt9MDJuSXYNLN6MCAbmtmH\nnxPJoTxVWvS/qre7nk294ObSzWYFRq2ChTjMrA5ihWhL3JfGGoFB6s5TnNkOQMLb3X0JOllmOawL\nQuBQgJHCcc/aMiViWs41oQvrPLUBflKszz4sa10QHV6K3JvVov+H1tovHK95NWIPwEEA2g2daXIu\nRlPmYT7wcMZ7mYlAJ0MNCdQLlLOjZ9zzmqK3CV2rSDunygzcXpIy3ALs6C70t47flE7eQpHaYefd\nZqvHfp6PsrmbYCOsy1UIpQWZwahG3UX1DzzgKE+OSTcWhrj26EK8K9KloNZkA8vKWaWc4zPzJnCs\n+zvcDAqCseWnjHnT5rPQHVHR7MDUy0tkF5Sm69AeSyqFanWJ16TcOBVMLSi34n9UVg6m6iw0LSyk\nFpTkwSth24PRoRS/vd9UFoXcccYd/73cZwnpE+LyR0E0HSpqM/vfC5br607w9ZfIljxMshvXhZUg\n1sMuLy3nDObAGKQaZPy1/KhzS2fEW3qKtdiht66iuWFE68r19Ucbnu8ol4rqAG9GWEHZGI62EJds\nmOYpjzCzUt7CBdZj/hOvj1bnMYUhZn5GnDK+AWTFAqDm6Zya5j/+ptGPf5urM/qME0xObFELdBaQ\nsfvdmSImvz9IL96BU3AVTZKh4tPP7XxY8/T0hoVI7sN5CADDzU58FjqEIw0WaG97wh+w3UJmkfbP\nW4vB5ZXdk/mekbvNL9txvoGKwyjK9WSLIn9ZBDWdocBy3+qfAYwPb0br6KBh1DDH0EYb7wdTBxih\nrzv8h7onpTYPzNsd+3GPE3HtGaPcXVRIRVV34G6nsSQRHUKH/UzfABeRam7FF5qzxQoI9fwskCBV\nnBOjvePjmLiDw5x/H52MC2eGNCdM/xzWFk2fgiIP3uoluIcqwaBzkQ/zDLld7IsnTHACoMs5OKye\nFn0vb885+PCViBvzvy1z71Eo07/xEeMp55qyIDsMlvCWRPglgKZnDGK/12bX1KNMAdfXSCwKsnKH\npJB7plGq7++++ezRCvm2GwlrgZGclVEZZNaz3DD/X6WSjWB/DeL1p7jvTIoJuOra1hc5BIq+Ha0s\nYhiZUe2Ed+alrzwbt8Tp3stchDuq+E8zs5/7uqW5eDTFVAFgIO3f5kBwZiIF8UsFsMDq8coAQ/5M\nZCPZs8CWzBX+jlCTGSgkYgA+Z9THR97uQ42rBi79bQAQ4RGaJ5Qmrm5hKkNEzBmWjSeDzW/oCaIU\nYgSfo955XI2qoxK2fabDOQcBFQwFV51ifgISM9qGjbP6jA4n0UJOoDS4WJY6rigaO/va6lDPCdLt\ndQOaafMaxr2Pi2rF9AcDWQ9XPPTg5iearbjKDh5dN6VODV8tYBFYobYOllkHIqyDfOXmRqZCCXyY\nyujWoTMTgOokHEh4z2eU0U0GEprw8YYATAZPUoSLp9vqSw89ACbkBrVdPE7ozF/FvYiJfuSD4+gN\noEyrGsflENpeDJHIK/pepo8mpdAjvawRjO0YcSxrtme9Oh6BnV80X4CCZ45IsNteTgFF6Gry7ZzH\nJ0Bhp0gzHV/GOTOxs/9C1r359h2QIoc/L37YGJhrqC60OuvBFe4BTD/jdVodjZ6hKMFn8oS/m739\nIHAl7w/EG9/YSjSHgE/LIlEWZfLcO6Qc4Ebh6wg692YYMiq0krjCT0GbK7D9sMpZ/R5NNw5lDm1X\nSSK4w4HVdD5/8VGkzVR9fTTgE9sRQ8vJjIPdriWl/ZeCtD0t29qSSF1rsU4am2XWWnmTiSC/09Zg\naRIEZlI5SgtTW6AQYevzxBKbTsADMJe3JTxBr2fEkQDVswhhRY4ugdq61PdS7lYKyLvh6cka9ZRX\nGc4n4qfYAUf/4Z6qqiRiVEM/A5eplfKwXqxSOyzVReZ5E8TfjamUQlpmssEWLZPUqCy53yagq/tQ\n/ktCNuPMG9IAMZkPlwiuTTTjUKY26Wya0S8PZcxqTfktAv9kFeKkD7yyWAV1co3kKjljw+V3oCrQ\n/ZWwr/iOxANA5wCk1Mjrele/yOxWz/XHqzf0/F823+IoqiIvRNvSeaJmPp5VMuhULa0f8LhOBkm4\nC56hEd0GtGdDOodtel71eF3lNHjJhk5JnfYUqf34JBZV/dI/VVT3L2p93P26xZ51SiOKuHjUTFxg\ns24MghjgPrcPOhyBTOwRNQbbU8A+EbRpniV3VkOAZEatdz+xO77RYF5JTWLBhWVu7xZ3Xa3UJ0r1\ncEg3AdMd7Q9dhAZJ4CgUhwHQqQ+n19kGfgGD3ovG+Y3F+zh1f7LstLp4/r0SSrDHl+UvFPnpNMs0\nTiIIzUwh4SvK/XzSkHu7AAKhlzMT8OA02a9OMoL892aeHosFIaA7/cc9n334/5v7RnrrJleXrCgP\nTLiWimtC0YAD6hAJK0RcpXrYzL29OlXiVQtMRo7moNAovLFsjjznFs1Xwtix+2Ax3Nfuwfi4aamL\n+GAbV55tsF4EotQUJFgA0MalTX3GHvT+hIhvAN0nzGIawC7opt6saDzVjlEBjgBCoilHRpj4JcIH\nTFVgST2d/cxnGZ9XhznkGisGFhimRS46KvTJQF1n9M99ETT0UKi2izy1E90qTbzp+R7b3YPI/olB\nT2xqReYmuFG4l/axIMUz0KpKh07Ku8liaGo7JTniQCE0gZU3cdUaI4Y7QMUT/E6KKlhVjjEFM28j\nRqKf00yHm69Ksz7cZ//FvTWsRIIylCrox6rlIaytgFV+/0JDYMFHGEdJW33C6Qvb7pGbw6i5VNIh\ndSRqFGBzbdBBUUmgmrUCjCd6WGVPH4FV143IQQG1yAWW3OjuE2AdFz0J/EWce21Jj7xNmmhKxiJu\niayoYSaEUf0cmR5bpVvTaKpu0jYaQpqRanIKx24sLJnuf//WhHtBN/14eWjhrHTvYZ+1xc597YS+\nGmQwinNqVPL0ZvzvJwupfJU99NbvxOwRQQlqIPodiCYsjw7nciH8TvnJkvwVc5k/7kSA47EbP5hr\nWyRkX8NA2Rhh/AMciYu79c+zwj/UrRXoNUBDEJ3SdDLXawGPzb2wRDdRT5g4ezP2R6wj/jovQGGu\nw2jETyqqy3KCwd8fO7RMfH5Ub4/MK8jgbTGONdLC0Eckqjq0abLnsgu3B/yk3zDJTrV+BKQ2CkB4\nl3fOrJRycHtKCXrQQxuVylPJ8LnQcOQgO1jLXdq2lLn2cNFHVorxK1BDh3RIdVhhoZE5Ej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MVHZaokw3Oz1yOotIec40sNq/N93q1AyMMQsV3rKJyxNzG4VEhQIr5snco+0TB3WkK/ufKUkF3sP\nmwKLZl2HV892Tx1r/d0KxzDnX9C+piJM9gQqZiaXP/tO4RaaAq2ELZIsB+Qsg2ZRskcieUFu0io0\nac4EzWKmqj21fVctXVPPPIMcIUOUhqzJtnoxAzUkGdq3ZJigLTnxvoEe5cz8wqQ4g74d97WaVHv/\n2qhMtilt0n4+lPuk7H/XOtcz9PEqFgOL+trtFhb8c1gM/8cUX0KNfAQDG1YiPXwA3qig7euPeByv\nIH1vDcdfyO/w3nvIB+q6+VEsLgi5zxzKMqpMwA9jPhdFE6XuZNVjD3QLSZNET+eonQbexqUXsOt0\n56nJyAfuCihEQt6Hjij/OinBjLfMoQx9ygeAouQ6NVLvWudbCReNJDfrjAd1oWw8xl+zrw1SwnQ3\nV6PvPCGe8Gn9TDfLBOt45FoGje62jaCUF1aNToZV6bdtyPo49/apRCAPjuq3NHPmwug3kp/mPdex\n5BQohwTNNbvy1VTOlB7cDlpYWUdVNy4pY4oQDBQ5ShPncwLA8DtQFap3NZEGi0SXpmXWsyaUvVG+\nhvGPg2m9DtQ6Nw7i+I6lyuXK9uClb/SS/wcOe+T7tL8KehsrXyRuSMPZhS7dSGKTgFJxWu/uiFsz\nY1Uc9FYCjAvg1qt7V4liJACwBtmuRJUwAmxqevEYxNHuJF6LIyeLbnP3x9FE4GhPQsJxfjnotKwl\n8Z7t0Ql5D0SNjQwwIHCABQUno6/FyTJjR9Kv8TRCnuQiLRHZFFBcjPstRyDQMksxEB0X1Npx/7zK\nQRL9veFDhojYYbVAb3i64itiojyEeerSiUOQuyMKAK2AO/V+auEDP0V3TCPTXHzlbC7JpuRwhKg4\nvT3B4OLNAeVtWrdNacQhjpyE7f58S7UsjSFOehdv5z4Xf68APFAzqHG9sX7oJeGZa7a5LMVlZXRE\nVQR7qg5R+KvE0+G3FSrgynMuoZJOF6LHOXDmQkZJppxIuoByrMP8NWwT6SCK/BEkx9AWUDnf963w\nSF3vRzq6Ue7d8yrZ+tL2rUFY1WQ7xuNKQGXvF2BYixu9kUgNJmNsBLsozVR3L7LwieJgNBXxtGAv\nkUpjWHNIvlGP7j6n1GW5zYEXFWP8j/cWXt/WaIx8hH+bLEk2hQWsIr1/LcMdqxSkk0aaQrt1ianV\n8lO2WGX0JT7JL7ANBzVgkFe1clhCots4xyHF0rbtbmlm2nHNaVomMFOhRbNr8nwStmSbYIxR+8L4\nK9eSBf1mVyCxTbH3w17MmLgUGDM+rkUwWZQZlcSCQL+uEepV1HzBPZEk2QEi51us5Tq+fb5rakTX\nDuLD18V+elBSMdZNfASQcur/Yo/+Cig+eclO/NMGvB3e/56XNKY17ab3yaMjxNJQFXypNP5w+3f6\nJhHBVj/7+ILXACxBnQOzJFh38IwOn/q8779xd3/2L8qu+OwbSZk9uOQpCay0ALZQmZ59mzlYTsH+\niB9MaZmsKi+eEkEOMfCIf4TNrmEZidAyPjqXDd7CTezWaezgHYMPEb6Hhp3ThBn+wCTC/U5WaqUm\nyCZmuC0LFpXATJjumjhjx7jGz4eCBXLv1zxUS+lujpxBsK8CVpH0uyrejCLz2C+e6UAT4GpQ8JWm\nZQseNRqayt0SV2UYGjNrHHXNuf5mmb3rj7YnUXSotmCDp18OeAwA+tDMbIf9Kdd64+9jvERNIxrb\neZKQI3093jjzrJyYewHDvQPo6K1fmppiJkRmuLDG+vUrkic/yS1VumXrYsXcOzhIPeKfwQ+cqQRk\nZtxLer/FzUdwZoV9I5gPEhJiYsSMejOgopEq7otl1notZAPNNQQci7NMQKYp9ACpOQUcgXk8fIre\njPrRANWnNGI+Vy/NyfuBoFo9MQHu/nV3RkVl7uscSZ0mqDxUTr3JvLNY3Kp09h4XXgZuRrfsPH7Q\nrebgmTeEo8fA08nvLyWriIo284UCieVCk2z9RuVRX/jmDl3YJiIgl7obY8VwXWzZC0Oqsy+iFZIt\n/ansoEenq2q6BzRLn9VGHzefKoWxcYFjJ73D+G19Dw/wZOLX1D/uMNvKpvdZxFbhP264wxKg8JDQ\nBUhWYDeDw+s6k/OGwdhBaPJAYG4t4J4XcnU2tYKodOTdAg7ulTDCqvNACzXkC/qUgejqyXHXly0/\nqyA3xkLSM92Y7k/2FtF7/pJJizi7zyPwAdT2Hj8uAk2xvJPTj+6lpv6islkEanuubhXEFYV+hzon\nZbTWI2XCCCcEkUr7wy/eh+YFi1EPRy7WXbjZ+zAHDi/nnDa2t4FZBy4AzqhSaK4l3XJTzjLB+ywp\nAYPwkBu2GAzg7F+sYy9yDer8DHr3MvxC8vrN+ajm9nOZWk2I7zbhE/aBLjPZYBt+/3wF6k2vfniP\n6rAyDo8jFP5C7ldXdhbQ3JOpkeLn9OqnJ8DnzblM7UZQRoPkEJ26mHFJobwNYb/VF0rCjsRf25Ob\nB/t+ANNf+zh/KOuBoMQyB7setTmAnJsO6zs8gOjreqPMJMZeg8ZREhVyYIXdYZDL09KAiSDqdGhA\n+2iRaJY5ADbLTxFOlfxlkDVz8gekUPocoKVZPF2yNdekjMwlHEZ6RTyY0RYqlWVPa2+z9vIOraJx\nwdeV9tST/ezBMpfqaS4ATtLYFEVVa+WvcfDYFHdCvsRyV5af/xiTGG18erBOboIL8mTM/obc17fQ\n8qQVWSJR5RvL/0UKrP2iB+RCYiYY4OdDq2DY6OHc6sf/RfrGxigYOqHrzu2Y+N8SyFWGATa8QTgW\nOjsJbCzTj4zfhwbbe4pUjClbCi5AmFFthmgvSfhSii+uE209EQCfGCG9MMFCSocM8r5eUdZkfPIw\nYhUzpkzf4T0NP/wOVKBk44tO0szvDWpbeF/+JpYZnjbbiqhn0UKsP52zb0bgsvTP5No6/nEH4Als\nfpq5clb8zZ+LvZw0JBO1KHD2GEwGfwDyxzvLMCNR5KclM3hXbIjtFAwy9L52wMoJZhrF42iuUxIe\nbzbOle9UqZK0p14VcmfCnA265zI8mOiCMti8eqGJpz6jZIqOgLKbDc550Pi+XmuTBY99Xn5X+P6X\nPJb3aaNTRh3zdD2D5WwzA4yGWRO+y+7qzsx48i5RRlF1pZ14vIp9KXkqZZQRCR/PT1rmN7cPMzsi\nH60DHuSgKQZiNh3v+hCZbzy4YmxLrKPP+NXMB6i6PO8G+GlVrw0gn8PXuTIFhHHAx/h9S208iOdi\nMhjThnfO2EYywQK+wMP9HW1jDHWGsbZVdEqDtGy+m9OYUkyS1szxKUgBR5coPH47o/mRECUgkWm8\nPOz/q53Va3DR+AIZ5JaGztHURm+Q5y7GMR68HOlC/SBfA2/Yxu/rWuJMO8uHmWj+I1KXX1Sc6Bv0\nJYtfljppip1ot37+uIs14beffCy7AunLTCwYkIKcQ9dyuYtcY47GlD9V0HcaFvYvxBPtRxWGFi5n\nvR3N1DwWW18J8FkKFtPtvJqVxGaLPf0Meu0x7CCgFgbhrayqTuIXL/LaGJkpqt5W/4a2UTMFoh3H\ncjYkmiofiwQvhrwUcvcuubhcckl4vIpYd5YmSgkZOkqOwK1m4ZlMj2qw3dyBoa4yHcjiWqlDGRvs\nF8HQGUsYGLkOFtrGUApoQX8av9NuBftrSSmSOKLzD2l3jDKZY61rw08hM1szKj4zrYhvQ0Br2ts+\ncRIQsmlptUK+sr7xhCnHCX6SFdAV71lYVEEh02gCDXuWDl4IVzWtNd3QCuO3XP7JmHhsT2CIBDEc\nES4SyvauV4EiBVJ6U5Qe7gvvvLYd9GC6/itMWG2kXUJmocIRTKpIeRpJf3nH7p8KwMqYszh2/kI1\n8y7YPiCT8tUpzokNZm7UgmjNzTm+0MbEPHq12LxCc10z5DSnlHe1tE2hQj1MbOio+WxbwkL27kze\nivUHWJd9e06HXWPWTaMYkjK/pEe84MTKmTM+pyayw3G7/K/Ysu82rClRCsViM+wCNJhJM+CkVz7p\nzU0QPE4Cg6DmDRucaJqElk9xk7JNPXCbBHFZsLmn9SBg9tZcMmOPT7ajN/Xtn49mB/gO8k1c5us0\nMAoLLlV6cdBmbRv4DoQ/UeJrF7dnTI3AhucFy3rX3ooalZGmLaJ7y+VU0Sz/xbIYwjiS9IF8cdUX\noD3kUMFSouu+4KmkD3RD+1Lz5eMlbGwyvW/IxacYdmQxACsQlPprh2P0AaIPXzE2qT9NT/mHyvad\nWcdvd88YXgvIMOgrHNHGTf1858liJmD5zvos/oyRo4KB80dQln1/Lk/o3HqYzzuuHme3pa7AnrdK\n3p3nwuc7xjuz2Z6i/8VYzw18BBL/vMCPKw87Y++Q1Pz+V15RGFDdRCwAiZ2zbAlLApdlO+5kTY2C\nWDXG87uCEXRuHgCbNjt5sSa96R/TBmehbz/9DSFWqxmjutCPlI1w1FaAJkOfjzDzP/k/E3aO74kU\nKAGSCbugrNDrXkovFPej+QgwWvJI9XYiInlBl6Ot1f4lyhWq/bAw/SmrGPVH1bARcxBR8m6kvNGN\nGKV7wLb29w1hZUfXR2H2Pkltim0owP3+eANnHmb09xZr8zNAm6/oxBG4wC66TbHvOgX9LZN2f4c/\n60v1/LYV/S9CnCplhSYzLeXfArKPEJ+rLewcfPyEmDhqziaVPPxkwGDaIxrfPu52k3lxDp+Em+8k\n1MUYhm5Rw+jnPSI6Mvuk0K8z68Kl3ad01QEf+6rFX/hxexAfhSzObbd1Cj75XpGj/SLrZOc1/U1C\nxEgoCNnYyra5BpsWjY+ZuHF4rjnmMj58iOusJVyyZHsoOp7CREummyIj/KNgt+yti8+/+TC6BKDX\nTi7hrgwG8VSqFwrE+v1XXsnnr37PuSTyMJDoLMCAcvKh7b4/uPBkVnzRpXjvgpLzm0Rnry4BU0Mv\nN3wpNcWBoU76YdaICcvzaiUWmzvtq0DaWpQGGWSVHEWLUEsPIiqloTkWP35D5mH7n95T0SVShxZW\nJRfu6SKk81rUjfYQGtRgXZpyaM98Z+s0ntv62lFOIa8N/6ee7n0/aXLx1ju3RE7d1o0Bg756+7Ug\nDspoZosRo+TIvkr7CChMkoD09lzVW3ptet7S0lJM/geEoDdUY0RLig3MglhvA5uotCU7rwZIksKM\n/Xc1YKZ/Qah9zRekwDpW+gqc9hieyS72EheVSxG3LPr8cWQWJ5VcccvwRJ3fTGPI4nENGxxpx15G\nNEg6wYGzUPJ71JAU5P1YWJzA7I04d3lEFUBwOwFbhP8OBpT56C+G3mIvi0vM4eqMrmcZo34b5O1o\nw/7L9Xg68Y4E2iS34WzfWzWGezLVSPRq1kMrsvvwe8/CYidExpGUo116nSQieR5OsvckNKROSMxP\n251nGuTKsvPV/dDJNG1TfbOR8ZEwrgDTyPPv40Jhcp5GSCpdYyOWHwVE8OYLtl5TPKtsIdZXoUl6\nu5LNJmZVk0cPS/WKD3Is3Ra9LX4R++oVX5ljUe42i/q8TjWJAn5hPZBqIl5yWBl2yC3FoYvZ3sbe\nycIi9QL9heknyYrm9mCXSQaFTVSrKzzqwBozgyXYH1+KCgU3OVyZWO15f5HmS9mdY26YHbk1kKx+\n9+CUJ8R7hG4NCLCCm+DKJFY20VTFSqCW9IbK+Z9GqWRBvj3HydHjAj946+im3z2soJW/zEk2eJ9D\nLWXOiZ6YijZtQSG2yM2ZpOHMQeHp/Oqi5NIs+7Fz52WaLFY/n4EDxKUHWQ4qea+Ialb+XeVB/AEP\nZ/Y1YxZMAGeUaaAfn9bhHAZ1wjG5/xUNwt8XxiB6vVknVlM0CdpOnU3h7XpYVNmG3EbpnpP1mVYk\nZPMinwwx5eEd6KShyxhJWloCFPv5vJyiQ/TCcbrhdccLjvbS4x7h6iDIWtUjbhm3huTBYfVptX9x\ndAdiY3FqPEj7QWp+XV5cmPgX6RIwxhfuB8xCIFF/1VKjQ5rYMAVGbBo8lLuoRYZ4jRjkm3brY1Oi\nx8Ucl4Y+Z4gZS4a/EaPW0Xl1uSTUNoGSp8uu/rkjXXZ3lLGZ2gqI7wex7vtmyDTDF2jSxruflj6J\naTS+Xu9S64A7tsrHlgmPFLx1NPKk5pdfgDr89s0TDVKd4wv9WYB/6faLbuFZWY+luCpNsgn2Xlvs\nzjTz9WPY+aPbGzB5peIj+YT+2PDGL/2KEmlAx7dxNQ9G2AsH3YYUJg57CLS2mSTDCSySaLFP7g+Y\ney7mt6Jb38eBQBij0zL+rKix0UVWANFGswTZm8h2fRH8fRanR92Cv5bAHQhCuHn30kPbJGW6HtiC\n/wbklbEVW+imRYxoQKVin7lxVgYELeZui0EpEQr84TFVGabw4/9fKnQyrLm5iQkxCOV1QvVTMTx/\nnW+E6vlmIa5LQodycZxF5oubpZl4kBBu6poLdljOqU5/4HETd4bf2tnI2DsV7C3JqXbEXbQVHdur\nTY0wUcZFKE1bWd8ZvpKVh8L1P2HexhskDjpzfq+2vStSAkiOf0y3XEJler7fxGfmorZOllm5+g9c\n99dCDUCmf0mwo+k0RP5cW/exXOlaSuL8nUb4/XOxG8VnN6pSpGSsL1jYCL7OWOEHiGVAeUSYiN5A\nN8/cI0aWtc+HYU5DmmmV5ZqqIU0nFslvAFIyRZpuNFRfYdZuT7ZGkcA53Jnu7rm1EWhSa7zQUH8G\nlJ5za7LK6ZOyIdsJDaFdU/kLxrd959gmqGBpAg0xHF7mueGWZP4tJeZjWZX9KONLzGgNk29b8B1b\nRObH46V7smLfbd9I0taQOeLKuB9o/LbPTLDEeCo/fry4M2EQGVR4h1+QdqD7aFBCeFklEj5ATKJc\nZGlIBGLNB56iuT9wGr6FpN7yRzCS2Yo+AoM1GOwX7j5H++Bl6CY7JdsCoVsT0cnhO4U0ZEIiDoOI\nXXBZioI5R3RPAvfKRWe8iRf7Z8hlpTmA2nlS0qLrSPokpTxf5KxVXvotfFP7osiL+LfUyw8bCsBI\nlt1tCEjL215yl0J/x4PHYoIimtjpg7/Y01fKb89e9mwMjXVo5SHjQCOmB5f4O+jz+cG3fa0/oVDJ\nbI94MQONzFKThuOLDaEVONFdqsgFef9ofmjPnAuqBCYOZiOl/0P2fABkZkpi2oijaukA+6125i14\npil8WQheeE0Uqjv2whInE7Mq7ac3A3mw8gqUJrBQMafbdUxWsXuDucFtkgF9Sx/Muge9PLDr3fRU\nfDm5hUqRvXXHaFSINIn4fiGjBP0LnHo27wTed7+8L6okL6jM3liq+6jWhzDc0OrYodM0zEVg3gzr\nOtMCkJnSl7EN5hb24/SoGiZwqTc+QyLwsBcUhFUrsawR2tYb5D1YsgMixDgykDqWXJJyN9+UrIQR\nGwXBj+glZ5qSFQafezrc+qiAQ9hO70ve6l7CyeddEFJ5kgHtdmuHNraWxF44g5aZ1tw7BXVkOo2K\nSlZrdkPAJGjjJkJJ5LSk4RzriDg6p4pqwSgwZ7Fy+7iQSlNyDG8XInhAkvr9yYakwaiKQp3FiOKG\nZ6105sc7SN8rvj3+JIZowcxEIYbDINHwuXn1/5sToZud7TcQa4BjSqD79mubpZn30kdeAhARAStY\ne6tBCEWxTUpYI4qs0NM2OMbha9wtuU0YOBSzk8w2o+l2yCj8kMqDsKWO+3OlmTMjoEE+JpqnfU6u\ntrlQ2zwzn25uc74Js6N5WA7I7XOThOgxPTdd2a39K4HTcScwSDvQ9O69Q/o4W/6QOpLldYjtSC+K\nXqv2pyThiPG9ihuDqgJi5dDxC4CHy0zmxRhdW9gPCv8cUJ1e8YeCnNPHzBQKRNHnq4s23k4XTQd4\nBipWM4swYal6CR4kjb3ViLm3d/kytfL8V+/UShRQ+SG8NyfZR+c6PDP8iJqnqyepliwB+q29fG2y\nqJEhQnpMd+bnoe7KKSukuzq0h2bnKwX718Qnb2519yzDGENGLO3NODshD7dNEPfwXqqzsN9p2Q3t\nbkodxGEURZgR6A4qefbtLxIVihASXGLMUpTi1hkvm8+fl2M2mfaxdkXNhSHl55IVya5HivAfw12i\nITCcq/FOdet4Ba67V8bAKPaaGH7A9skNN1proVIQe3SIi3NdF4gz2hSyLWG8GH5gLzI7p/2dA1WX\nCZ/tOO4SaF6b7bNVUGN+cKoiJVIaY71digT1Gu4dARzimBOwPJiAFAmFvyTc40oD/Nh4DDCufHRN\ni1SIHaJplNXz5SCT1CJYyIC7nMcVpkKrFnka14Kjq4f0ESKWR8vTmm834GNCC34hk0zoxlYlZAip\nRMhcxJ1WznRvyMdpWeIvZintnb5CfOzYZYAtfZsPx/6wrjOy5hgifOw9kWqY8dNpxmZyOu0+ikrC\n9xhIXuRuGinBylMk7/wDSEtHv0JA6JRrWElHPRtGgx8J7ByC8Ala37Exan/H8hDomEqRvN4ckgYx\nQqr0e4+jFzT3rXZme8ptR4NtGSS3Zlfp/TNdcht39Jf71QTUONxtBIWM2taK8ky/NobGjuQ2go0h\nHIoy/XNWSarUTny/P+Bp8g7eLKVxA5OoxLxT5feZC6BRLnj/JhyYzSAvPasqUbnnZzPkH2jorhnO\nhKQp2AIvEI5VGe43H/s/VMilto01hok+fsiT5PkYBTsQTXsESDjU7/Y5ItR5liKZfYRG7OopFgkv\nqG3Rz1DFZ3y8sw6vfIsf/UNURmJu1njSHU8pFoVixEdx2YjxfFoWyy3rbIBKKlVbmYnuo5FpkhjE\n1xVN2NlEYxvPoDnuGCP4tttzazru982YjO527TV9guvWfNgf122Lt9spQn4PTY4bsiGAZTcnpnDW\nUOygCs7YywjW8oc6j6gpBnR7n3NO75c3mq8Ct05OV+AhVYOYBKQyZXfVmaTwGYCz3gg6ruqCuIM8\nStAJaKZ575hJvQ/LnkLd5UuN0ZRwap0KdW0S7oR1arEfW7I8DRAJmXg5FrkX5GeYMKlBas76iNXU\npNPr9azb6O86hh5knOwyWYaUAvTZqA+2e8sOutu52lZKmjiY6bFvOr8th9a6+dRoQygoIA7JJQQJ\n3mBQ8qwZJpKlQD1/6O41f0/g/8ir/EGtekGQ3DqGevsBV18s4FUUILzfBemrnYw8ZOalZiDcv4gN\nI3n8xx3AMxiubHo/6vrcCbzpPrK0fVMJiQHclOY2UiTUm/jq8TNsF3li5tD4sqE6866Zu6TDWQ+w\nEXO3XIDQow66EJbByVoyt2461V1GqobAov5zJoGZSNpMo/tt3DF4n+oX0zBF04Ok0T+C0+6bDoKA\ntbmKzNVeqKFsz4GPWGKlI34vNbwLK5Eib9esu5u8GjUL1A+At2eKTKNqVEbYTpWjpg5PbnSVRbY+\nYuyKkUwOzhUNrae25NTGJygG2DT7Qc9oEKVL0bTs+DDdkoOIc7tHUanuzeA0Rj+bYvL28OgHuH38\n6NtmcI1WqHZfvjzepbGIqWjzOEX8uiKIoMm4mzA7+YPO1CaanYnNzzFd1KAhps+m14ReYVWdUuHH\naGlvfbmwdMinI5p9gDAXIlbyHhHxW2FMtCu5Zha/2YRr3i6quGyYjqAGrwajB+z4phsLdssiZ97q\nOB9B2KOmtHLkg9QX962VLl2ip/kL9PjG8t9Man1PnJVLE3KN7sGBTJltBs40vWqA8sj1cIgafa04\not1fRsYFFQ2g1BnSdgrqMBGDVZSbR2g7vDJKhv3cw5W/kWMVybGFnb7napFnlWbFmc0cLzsJzbmq\nCEofqLiuPdOlsTE7stVmVnWs4Ssw9bkJC5G4wQF+5QPhB9Koc0R4k7IKLX3BZx+RS1uR56ji1E9g\n8w2bnWAlxfUKv3Kh79JoKqxgqmn2zehgU5QXu43SzGIucmEFvodzaINjv/WQJze0mBoPMJGV3wHr\nMjTQfOGnVpX1Cnb8xBwIPlyZloqtYQiwpKiX3Rj36YKOdiQe13UBYO7PaX9I/g2sBZlHeSLABa6O\neZ2lPEWIP8/xL2irhwc9/YzJnlWtv2oR2Ic2MlLWXOWlfO9dZ5vP5vmHDyyFMOTgm9O5/WWWAsHw\n75PPwFTnB8tqoWqgf6+tL2l2YKl4VqwUPgk1dvFObmc+2uiXfaA4IHcexnJjYLs0Kjrj6D9Urom/\nqqim2n5RjuhHYSI35ODCk/AdeQIJ2Z7ygKtRi2u4G+QbIoCfbqUiSAaeeHaMOWbSGh747UA+RHnq\n1jXlA7iGMlLfARyZko29LaqQHvlFc0SZjb+hqpUvv1O8kxmkh4vxcbkKRd3hCbeIvTPUo1rzwc4p\n48sYSH62EV7MAkmS7w/sRZzyImFdowttYfkbiwVkBdPx85j1voxkasGb33w7qYz4AkZCcbFSWyjz\nSF3k2vdbgI2UBm0R4/MYllheZFNhcrI9gH5IZF4svfEX1vBd7QUCEFTmfDCtAJFmjFSzl3eBxW+A\nz/5VxTBPnmGF4UV4fn/DOv+Cmr9qUwj/vKEAgf1e3ZoIMh3irjDOVSUGQk7c5SOCPrVYH8c+RZ8A\nzDKDzgdurmYvEaWm9rBoYeCdsz+m9Mzk0qptb4cX28RjESdvangJRxpVapgSr9L1zneTIJk7utY+\n6DNFV3vSsHBJFP0V402Uaz5LW1Gus54roxthzyPDjIUw7To6n97vbugclNyvZ7pJciXZU8hnTGtP\nF2whtA36lJ6+TyF6/LiLmXHIGHiZez2ANbhHWjmhAbOs+lcGRGAEIC8YSQmj8Mdikn7l2EQ+T5uk\n0EadHXDKYXSqQeDc58MiPFVxI5gP3MKONMeui3vGZLjcJX/l1llkz7RgRSDQ2DxjGJIRpWn0xPkV\n/1iySzK/HLpiGszwNDWpU+j3vhuF7wOdbH8jRZYP3eEOtdj7Waa7eT/ZpyqgOYV8dKVgecnBhTTs\nCUFxuZ/Eg81OZyg4G/l1kzvr0GZ1vEpYRb1zbcj1wPKYoHKHp+rMUwibwRYdr4K7dc3ywk7lFKqD\np+ZerEtIlbl9/tGmzUCqkRI0dAWp07NPYJ/YB4vW7hK6es/uiDH0VYPtDWu4A8KSiB+eauByeo2E\nOJ4bmgWUlDINhsTgx4e7Tq2oQy2RYVLE7h9yuf95JsRVcc3EHNCVTZ1q1jw1lWzLWHkcnT284KHN\nWZJG87dbR1RXmbnIG8RfiKhUq25X+K4fEWmV+PIffVE5bl43CGMoRp8kZp7+Qn19mt9YQQBYmXmN\n+8vUdRHNDpuK9er1B+pwZ1dG+pDRDbwhC2muURtCx4sObw+EsdTfB4PyJAUfbNMsRkpcT0BAGKLD\nNecOVtQdwaLBKT9L0tvp2/IIAbZZCEO+vxk5cuAeHuufQncspTVu/rEU8zyMYJ+AOeG+UCNHqE2C\nazs6JcJnjoLyqjABoGSQ3sdF33bHWWyBQjIowFV2iYibN+cYYnoyuBORo3e7mjzix2+KCtYWSw4+\neVE7VkLlw9GocFZe22M1ZtIT7vi6GN/5JZUAiyU3x0bde+t6XGoPaQPM0ZxW6ds6dBR+0KgvZeVe\nz4mYo1Mf1OvEBTo7QeuCSkwEXLUSyWYjpdxmrRURPSU628Pc2UFA9OwKRL3UhfyRAeM4Owa5n8FU\n9htQ5A2c81lh8HcOO8wqMqjR9K+DMFoOl4M1L9jeCrXsMfoBPB8a9kK2BJbXyQozrcBG2y7yR/9P\nY7mfAkCySunHf8xRGdjQv7W5DOE7pcZ9+YB7FdO+uftBiapBz6t7NFqctAAyLBLJpCFlXF5+ZQze\n0R2nVkxeobtemM6vRx82cRPY8oStzo5AGxj2hLUEs2G1PpFN8wP0KjzVKM88tBL1HrqHTBi/4Rri\n2JGkMWHBSv1AQIKkfXg8Exydf+SQxQvdNkcASkU3RSjjnyqrZBZXxD1eOHvz2B3ymBh0vJYg1arF\niG0JimOP48W/QnspHb6JKWbJp9PhMv8sH013n8Bs7swZW8FO7GJG6bmTfupz/0hYMhWVElzcT74g\nNXMslhZkAKAL4f7UkF3dPvGZGgNFkq/oeIxc5O//95UJX9JiEpRWCl0+8E0xHrjRB6u+Vwr7/0dP\nD57l0gq7jyRTXIXPoN16H2YrJlSi8P3VZDTwdb5cQARGF/MszusXuZWEMRj/GU5eyJB2F65+T8ic\n2GpUuNNPKCpk2ZlgCiKwPuMQQcWhL1MSB/teq1xs9J/GcY18MhHUX5KfCaryFWoY6R2IhX0bcWIc\nAPgcyM5YEwjT0xA1Q2HRvBVfvCSJ9yrd4fkUFoA5kYcNvp7OQVa94/YGZDpY5gO2GoP4mu/rG41m\nK0EdJeFdUOLjoep38cm5A0ZzuAioM0cjDGvnyRVW4VrCHi9hTifXkcuwRWOXXS3mrimo0yqECWU1\n2oM+J9Z7Lj/r0htlM+qj7Td2B+M2cHEDLFwtF+c9LaiNn7staTcAXKHlxj1uzDjpySmCW96ALGzG\nrshIENozI9rc7V7iNn4yJ0C/A7j7SbkmsYIiZeX9ZVewvP4ZHdtCPQY4PfSmmjDYvyv4Q3MlotWJ\nKjEl0EArJ3VUqFIutKvmjfokVmWG4g6eIp7Kb+l+GVkDeLWbyGN4MY+Cj1la/J4fY0GmpCZhoLz/\n7iyYq2EexFHowvb7gy5tW84vzeJtUnrvYcttCYMX5a/khythilJBiRLdgl9xgAF6vvL0090mJv3q\nFc6PAaND2bnFtZo1ABZwnuaGd46vaSi4P3PBdJS1Mzejlub8kI4ewYVfLnlj+d16blVu3mCbfjiL\nFo0W78lmtd/clIwgMGnT/rmMCyE53U0K0gR0PxqmqSO+H2ePehwy823ku6v20KtWeYEAJTSsV3jI\nP6w4AKzOzjWlLmnS5+PkX46pu13kxMKxXCNkn+wSMZXUJy+rzOX2QH58E7lRJ1ftGLMmnvj8XUKH\nJbtPWk4VGq6A+avaKHURhkP3ENlP9N1Xn6NsB+AW+GvQG1kb/Bx2hk/JGQpcFJxkBTqmDkp076aG\nT9Za/Bv5YIoe5KBRdPmCVCnRZPF7sKwlKMkE8jT23gzxQPOYVzgmtxmjo35GzyK2WAMioO6EQ74M\n1YW7zAXtbiBRVLMRPJFdpnikHmPPQYBGfvLRPvkMgIvuR9/4H6cOWIRVQ4wuzmvmAzg3db6Cr5xs\nbCw4aUuEPZrYmCCuQxCbL/hqOtfE5yR+4dpZKNSWbA7tvY+I1pAAL3u+OnU+fKFnqrApkvv7CbvA\nu6X5z1hsn5iE3YcaE1tcI7meSGopG08kT+D9Ad2ZMjJ5oglsr3dmyhFxfGkXXLHxX8Ey6L4HN4kT\nuJ0nVUIKFT68LhRW3E8kjycPQ8kMNeaoLrrp2Ygr0hgiQrPuU/uJ8mAcZXOzpeIsNQius8h7ZQyI\nT3AKDZicQxHOaGo0lCMTEdJAlRHK2gX/2j7bVKjg+S9/484nSzUveYVzo6uqLYb5pQGV4ccc/YAf\njPL04BMsyVaNoOhmdDc+kySq2VOwqbvMuYWKE0XilgVqOFyMzy7nNxUndNu9s5H85KGL9TvW4tvy\nTpmfq2ZhECI6FHlI1DKbAJ4D68/FdaC49MJclqHcWoSqU4L0vADVksPF3kJ9EPcsCvhB4zDnUPHV\naAi9xmG98ZEI9faoKatwC0t0U7maVsXaxlOCDj9FPjrKr/lCI6zQVXmAWVCbGPK4aeb+ogV45/3a\niEmcq00gMUFv87SpfW1xEtaMRiFiRG+yMv0iQymvAEXItfF/4mhapribVGJc4/DAvBGYgZF2Gd76\ngHsSSWGyUN4WCL8wZqpSa5A0MQdDr9iPfBjlI2Zu9Z5MNNabhzanVU28BpjqWLtblkYuX53iJwmS\nixxcoq37hb4VOTnqIOZuVziGAJKPwc41SsUQMFuXHkcEy38cUpRZ5DaFEWMSJrpJvQLjbghMW5Ha\naNRMqmSCmPYjO7qNSzz5Ut6rxYA23noGrz4P3fEM3zPlfb1WnFk7Zs973BPKnENprTkJdZPLiWDR\nRBsim4WFcg/gNb0S+W3K7zXAxpZY3lsazt8QIrohoPBBodYOZz6w16omqJC78SJK8DqUAAU7Ulgm\nj7pHdJT0QgbRn5sLg9FwNFbNNeTZELV02yLyqSorgVZOB/+cgoI3gVOJheFY4GGM5wHJ+2pB32o/\nri73f09TEOl6NmH8nCe6aH6ucMbdTXiyYJ3RmMIblkXapaBgGb3I0PrQnkg1dnZN1scV15KZX7c8\njoTgKS+d6gVd5dqqsxrjtcZ1NIwppzDOHZMj2qFEXERm+K4yDzm5jibBkE5aDyPpwpCWO+gSS1PH\nah5ts+62nRKKsmg5wpAUz79xXJLhHPlFRiY4qZEfX4WZ4gK/BPCVqO3oXeWJ2HZrVyl7liXi8Z0A\n/rFpo3Xg68MoSNPJYXZF85nk76sm5xhBAh6N45y1WZzTFifQD/btoW9RhDqgEkmDEpDDcw0II2t8\nn+Zz2AwJ4qTDv45xD897lOEDCisz0/w1sS4P5P+/+A4wgUGteaT9oCzzK2Lp0l/vITCgehgqKSnm\nTO+VWXQbCmtuoxyjBK/WT7v/veEd/fwyoFOi1ZDT/2dqxZAk5mRraVyoZyzDVr2goRhLp6bkg2v+\nyruvcf8IvjAVFLWebkOPYooUPZ2ogpNwl2hNsc90NuTynd+nnWbEp6v8kJKkB/jZbI7wuzwLJCyH\nHL4/oPvIqa2uLwJBdvdgfQQlG5IsQqQ0H2YLaQ+e5tIzETWlR2KBfqG2GEIlpl53k7CZsVUmbWa/\noqiQBQodVsjiTwPaU+6DcDC7LlHrPzm+jOZo21aWavgkhvs3FgTqaW/W73EGKYZi19Ui/j/FILvB\n5rADBAU4LesIn7XIbzmIKyZcbLUyaWPDW4bpvAsXhrRinsNPzTsjW9bj3pwLM8DlXADN+N91gdOl\nbrZoy6c390xjYk5PdZ7bCCNUYXHhV0R7gH4mm0Bx3FDIcFnsFsJS5BqPfcn82jrf4v800y4PnZZS\noMNQGsLFP7wpctLHuXR7pgqEigRH9tHhz/OtXbZvNPqSFdJmSCmLC/S+Fi6Kng4umEufmr7JMN/C\ncZzAaso7/deIGA8G6TRwTUA0xdJAtNIwFh9mCtCgk7/VN4hqKhXKq+2J7+GDKKhkMnWNaFvBW8bX\nsu/QDoLTtkrAbk19ZWem0dTSVBUf9kJpmX5m3nByXC0EQ70MHO3uuEUT2L8aT5m8hpVEZzd9GBcw\nts9cNTPzPj0Ci1VC5s9tiH4WPJJ0jQBm3bernRbXl+MAGGKwIhY8gkS1W5pcYf6FnlbSaBIHgUzK\nIgFNhUjMLuz+eJYkiRh1E4AOmR2V1O83YSBtFxcB76JaG7VwTJFwn22Qpz5JRVT7V2x94koHtsqD\nMT4jZ6UpIgQizpob6FlOvnhWldFF3G4Ta/zVfTcb6xiiMjKOG7jd5f165n00bBy/SShGL5pPtLOU\n/9935rMxzvWijApcjLFPiSXjUiBsk9IunhH8U1ceXFC4td/nxBOgRLK9lsZeOcpTf5e79856Pi+U\nVyyqR6k7oLWoNApbyXlYR+pjJvk9JWtriZt0l5A/2fdavV57uJCjcyaCFfbTgincfDDSw98LBPWd\nLBI4oDvA0whqKw2rcEc7EOJZ+ZUVD3DjgsrezK8KzcEJIkrF/PjaM+WqwApFSDa27JDwfDGiOqbE\n72fduKxwil7bXwVMvGMtCz8JXB5dU4mQ1S7x0/6YPFhn4lsJnA+A3Sgw8jc8QlD1UiIiEjSvAWPV\nJfZekOkntReGYcnbhFE1FZ+DAvBc1qGSPPAoNkddNZgg9P6NEO9aTIEsTJFED04TdQ2TdTcE31aO\nwnC0f7roRWM40kgtVwS82X790C9h5htVDG1/qchXyYJ8OCdAYXJiFKTaav9eQPB0GKBTAAcz0acH\neYJhJYsM/ZTkZIdVRAiB9HzxbtzSies/3KqVFLCXFWjoncwrRE77UPwGIEdCevGoC6uh8oAXeARI\nOJ7FyguR4hsUH2jMIh9oOgzbTSEPEGeyNzaxv4mGRD3UVZs2uEKicikBQ/An+DoHOj7vXcx9jFHm\nYpDDRjWgn4lof0eLEliyGUUYt8vAEX+GZkazSorri5gk2wYWCPEJ7jyAX7rPIEJzHliIlMJ/M2GO\nMf05cxU9TYuEFfLV+Fi1Jhd8lHWxRf/s4ju8UZJIhyrXqe5+Tz0NGroZ45hV4QO4ojOim7ENujQq\n/6cMAu//7vhVOp12OhwbbSpqt+ELHbZ6+XrQ6N/9w3mI4Fip++AH19SCRRKkVcqPnk5PvnUC9xsH\nNDX8uremF3hkjUweqEIhTZFgNBnN929O4wMPD2uJ2X1Sf0Ozf5IQCs8oCnAkWt64oA8ete5JUEPa\nw3f20YD0UQrsed028qXKfGSpeJ2/dwJ4B8aRmSBKmZC2t425qiM2sPVMA8JOw/2ML691jesBxPwC\n9S6FIQt4jzC483VUtgmMmZo9tC4IXLWdhmqmO+Od1OPg3fLjM2OARafMrYF7mt7J3ltsvQNPyheS\nCQB1GwWpo/ndYAfp02gU62oCMLA6QgiBfDvkaw7MUzZfZVMF2+l2jUVy3ZnAgbDPsyXq33NA9kQ8\nn5Iovlmsbh4bS5IBBJ3H4tm4JPrNAPxdKHjAV8wfv6fBdzwgmhZVqg1IDCBttV/3rcGVh2fSd69f\nJLW26VJOMP4CbqCfWuz7J39+yHTVtwTiv5fJgKkXsCFaF9fvbratixc5ibZkMOlSljIyCoO/Twvk\nV9iLmjmc2xn6zMSLec+myVXZnvLNcueiWCzbDg6ctYV+LixqhYI40svmK/XypC3UIC9D9zXW4BG/\n11wx3THkzCiooUFnzL1/W02nzgEN5J9hGU06HCO1If1uJFBWTQltG3iKDlwq+1/XsFRkAACo8Qo2\nGI50RfEBxSc3Zfyy33vdvYG7bgRCIq3fDcGoem7FSBFJbFaPVfOCp0zJ4gi83I5/jgFieRepxlIn\nNd5hT2IltoyxMcwKXodfrRwd8QYGitHR/T3zgDQmNO+RXvZMw7aOTF5M/n+kg4qtHQ1N/jAh2D1H\nXWtH15WAidfz33rmzICUP/JOCTb66B2K8d/rxmrnqk9fviMrYPlKb0Ltqm7jFWyL+Y6ZVpziuIP8\nKFyzC43KLXouAF8oAnr+ZCnu89E1Xsc4tzJ6sB5wjsdMrgazah2i2w3/Y7odGWwO8sqpM504XJkg\nN1wmCjNyG0P3Ihax9MnqPccyAetizEMpEQ5DVHhpj199W0wxxJpuiTgR1emi/gPdwFYM9JK3E/1N\nhAUJkVoOsBgFdAQM7H/UMEjtnpZsdMd5tS4Hydg8BPfv+x1rRbl4ILqc3CFxsikC4Mvy4mM4+qSd\nQVeW8W0wOrkAHtWPYj0m8mTr2AqiMtbWDQTxI12zrvc+H4W2Ob7a6YBx5WmC+WVp8GigjkObm4iU\nH2pFZdb+LwrVVdKz03ILh2LbKQIozXyCsx9rbuDt6c8JQobPAW+hjcoB848pSCJqRygC7mMWR/Ch\nJQUQEyda0qpMIUp+isNX1v8KlaUxs3c5mBM++3I2qpMT+TpvUH7CKzlWJMBzohDNbr+lMnxx5xDM\nd0GuHlnDWNYO6fZVw1eJw4B6Hw6RfN3jUYtQypkv30tYqcvwXdm9n/13uC4kUuF5Ia0RgmMJ9CSe\nKUxZ84TCvTX0P5HxULN99taAOrDYmWXP99HzpDrPqFo4wxCnIVWZNlCLWQCxpE9ftR1LYDgUrSjK\n1OVLpIZHDEUjtE9jTnc4KSf8ts5Ls/32v7nkZFeiSi+rgbz/Whnerhj4IEXx1resz9wPqCKXXkro\naXYUmYpL0HJvmpIBzNI/dbfk7edWEbi/DJDPfAfFidDpd6wkcF1QPh8TNhC7m1WOpBWD7TDhOjM9\npYJValwOGkfK5nUGH6nqz5TO/D9dADRilKULOYmjx/PrWLDsm3ZFPO9cSTiEP4PU1HIZSbIfUD/P\ndX6hkNgKsWtkE+hrMXRvwj3F8eMwij+ZCdi6MP0Tfmyzs6J72A3sQx2dvnoruigyHX+HYF2/GGL9\n585jy7txBGnxWbzELN+OsoCLB4Tseir2vKcjrgu8pXaeAiAOaSgcSpB3l2TzjayQEBxIfW4yEaTR\nMO92NRgnGAqZ1PBOatDFmiviQldVDYnRs5DwGanGjscyvX5tDI3zGny4BXAxvzHA+JMrjcnpiv47\nBQs4qqY/s+5O3S6slgdg69C+IVTQ6V/G8+VctFQVgRm49zCW4ku7JZ4TUahGuk1IP802bSUY9aIi\nF407+DidkrDRKOZt/swszw66TvklY/iHWHkSC5uq/cUSBgwjHD/BirbuplrhS8b4qOrpkcTXDzbb\nM1x7Oj1/BnAOWV2B9EVW5J3RgbNd5mTaD22NSKtM8LrR0+25QJUL8rnMMP7/6RRgGgfy0Ywjqj7e\nfzxQgC/2npkEaTPO4beZexD/EF4sMkR4mWl5mmX8Oao2dmRisznMYalaKQcUCPTxQAhPbcN4ahGC\nXkE/km1cyD5r4yTkPSPpM9hUs5RIKng+AbLOsiV+uCnAgRxkSykaBqbvRKlaWzUlbiuAEBHXA684\nhNCmAPojQZHXwckXyLMQuQR1PNpvrAIjAN+GEKZt36CYbwukQnqcJ7ZI8j6hSdZJQ+FU0L7AVXSA\nlpiEFdmmAazO0ZXVktrFvomGhbLM1Cbml/5tW9049zUeYdcMgoUZZ2eN76MzsAUHElfIJZVmArGf\nSNJG1G74QlndZSvH6j9oWDzBBI63r2mZCmPPQrqVm49fYf1C5WVChW1v/JDCBKZzR7Z1IP4YJP62\niA/PEybDOi2CTX7GDI8l98ir1BboJFtYj65+zSn23lzmNmYsOerFjfqjz6+StMdDpPt+R6d2iSYn\nWdx+eiNC8ZzIdy0uPDLBAtr7l1L9X7wSnag0mnQMO/11OeoeWcryeK/gLUuKlfe8Wc7TF/KDuzbn\nuAp6jKdr00Cq3d+U8dR+OdVGuZZ6gJ5+RdR3ut68239cJ38oeEPtfNyFTW92JX1EQZwGg0i4rOqc\nyAvGWAO7lFvnmaSF+7E9zdUZB59uVe4kJ5Otbtzpo/GwinnrKEjRZbhk40wR7NuZp9qtKU2C8eJO\nXNyF2G+Uu51fvRl1Z7gtc6RZJue8Q5VC9AlDRogBYXMq+DtUtma5VfBcRtnMXXl7MilEn6QBFHiu\nFFtwNGghIjL7W2Jw4eo+G0LrkoWH4kq+S/I2uSaGH7AF8wGqE6S8oTJOagLQOq5K9uEoKp5T9UQs\n4ivcFjb9EcTGTRiEdIrw+N7evPq1fhion7GoBsmqwKjojK8P41MN99CsDeEzTMQjnotpI7nemBlA\nKYdUlaHmWyW1KOb6U8v8+7ehju31dZ4zOWrDx/Xf+X6CXTz6h7IBTmwHInRPaVuVQdBy07anRCEl\nSaEtGmy6vbPGGbkg7nvCmizgn3DfPPgIbtin1PIatM+fdpaX1pXOtRLiFl8EyjpxZZ5V2k5JrCqo\nDFi114Xhy+/H2/N3rey77/5eUDgIjuNegdfOlognyyG1rRO1w0tcztljZ553oXebdUb1CEfHTRW1\njBruJWtNOVphnAs/7fUaAXCB1nQBFwfRi3OGwMIVBRiEZhEab6arYrFM4/8iv9vXonlE/HsuZ94N\ngEzvvHoNf/GBbi02A+/AgdIuz9ePZjEZadlDwUeGA3BDVJZnYNHDdIpyNbLV2SjvnftFlYiSBbRY\n8RzCx8az6e/bf8RUeD2GxKOXo2PxtP7qJtnoGp4p5mkqU1SHDApxurIMSZ1Jeyu5iFbokDZof231\n2S0ScMpBbpLMtqBTaNwoVLoyCz75IMbeuiuxGcxjNewLlMHNMMLvl7QEgFS3B/POD+/3QNN4fkYv\nBbMKUMbyMiKzBFtKA8WFu+XrfCORzs/kIJQRUrHlRm+BjULoKbtHEpqnYuUpAJeYkl4U2+qRUmHo\n9FIqnQolkBk3jQVleR/hYe5hi8BIWYLCwkd9GgopJeU5UbrT0taKROR8shXnW0YQQMpty+hvDzo4\nY+8BSo8wh/c4iL4apMWgRwfixZBon0kX/kU9AMaccqDF1K8bU1TnYmQ83V/NOV7m4MnSIx1xEPtm\nMRVAbzSaXzW9jyD8emWLrsEoUupf32FfzcV0MNKSeLMXttmrzSXYp/Tag6nblC/RvuY5Q07mnCBM\n7rD69JraW1oGtEwf/S9U4rl0xt6Mm+5c4WiIUhm2DFPqQlLZXBDbs1ZxG6M8SHd9d1k0IDz08B7L\n4j/ENWXqaWZkm8KEKvnpRLt66/eUI8nV8+26t55sZLVODXUi33DF2OlJcpYqq4KiOCcuovNi5Y90\n+063cf9shTGT6uMe1tioMZPYHZCplMsoqLc8rnbob1QwswobA3DMRRrWvVCXMq388bXsIZ0cKFei\nkjbM6WbjjUtRRo0u40zEDUfESBzOGzA83+g1IV9Lc9yorja19/APtlrcJWmhHv5Bgqe4LwWvffCM\n76Q6GgvDdgVuRX1nnyvK2o0wNSsJ7x7PAFS4mMTrCMrtLfIsoN1YhCjJzMKjhfpmomSHNRyim0zI\nUgl+UsdcPfFhjWeIIuC2waD2OLWuPlPyJM/PX06UMmRTVLz+l2WyEuMgpCGDtkuGCvegq3a2Tk0T\n3Je/QTHX2YoJrT3vTgrlEdFNr8z/3z/3qVy/qOrLac5H7Wkw4s5mAFlvPHoZkKGn91YmqY5jMFQk\nzFZ4XmNBDavKTqqB8BzuNIQnCExoPVJgtQvPQSgdFQady2Uyb4cBo1ksaNM/ktPDt9kjOrWHZgYn\n/Lu5tGkbnfuwt7gmu7r8RUtXbYylSBJLfdQIX9GRCrNuJ/ToWB27dGEaTHP1giQe4gU2qANeNewu\ncNUlF15ILIlqohCS5yy0GgZxB882iZEyI4eEWvKGNLLDe3mz8ku1WjnYsTRVAsbRgpsm3Qrn5KMQ\nnRSaT+9k4Fl7HVgXjMREsRtsLr8p45muAVvtB8256QYKj0RLsiF2H2kKhvwte/n1jamJceSGv8YF\ngoDSRwtGABbTq05YJiYh/nlmdMLh72X1ToCb24Nd2G/lMnP8DTwrbMoNsHjML+7nOC+APYpIc0X8\n3OJ8xC0zPaGEPxiMwFnM9zBFbsBzjX6SF7YbdY6EhZiSynaB2XNlHKGxATXMwTvAItPHt2Muy48k\nvmGvXGHpXuB1u2qVoSLGD+tP047mwg2vv5YhfimrsSYqD4MBJlNHjQO/QEFv4DWwfWbt21odURPN\nOfa9op1PLpTegkfkCfq+3/HjbYHYJhTgjmazY3W+4nTCRuLZvU9NrJeOa4MGP46EPIieoQ1vFZgG\nmwHRgiaVCzizoZzLqPFL0kpLoReZnSZ+pA3PukCfxV6CZvlLmCyDO1I+uRhmL9dP5yhDHLw5E2+1\n51AkIfhPFqzcnuVNrSt/cmhG7aunz5jiR4hseLdSnJ5IompgVERYnxT20kxUPwOIEevFBzq/88Ml\n3Q294OMIYXiLp2Uk0COoRPUGYdhaZfoeCB6VqfHIACttCoydkdqSI44ar0pwyOMdBQjTBQBmRW71\n4senx6dyyAo410kPdZVuzLoWEM9rDZrRVz+xybNiybtFZYlir6/DBJyVQ9BT9d4wGewgBeYUXkfe\n9Zw/tQPcIYU6Kx3YV3cur13CM9enlrw6CRWhAawc1l2CBchPAs311at3itvi2v1ICRZOwDtSESbz\nsAX3fCtzbFA8aQSV+dkZH+spj+N61DeVT8jvAr2bRfjrcTauPTb/Sb7lkiX0HYDlIZQBYc+b7PSs\nZuBLlBRR7Ut1/I10i5Gz3EcAvcJMZ7Mj2VH+uylgjN3ve65qq674WiNb6KdGHxer9ldOy2M+EdoU\nqMjN7+Xhf5iIxHgKQZcaHnBn6d2tT0ZED032JvJQaKtnty+IiKoQLQtiTMXfAmurfoCzwo121LgC\nmmy2CqVg+urGH2z7S/O6aEHIrEyKBtkxHXnyftRI2+tcy0b7jsJIgdzsnd/+yaFqQI2PQFzgZdc0\nNTy8DGhgMhoy4uc9CqBX1QY/dwgMwQTVW1APCSrTzp386LJOrIhFZBv1cIV3vhdxeKPNIpY4F3xT\npTYmzftk8476L4tcJ0hoG6+Y4xy1BhY1djSexV4ot5kDpNZHBfQZcrN6O42fRYWEDcpw84f5WnUq\nWcaCF8fzPC0VY9QU2ZNWfNzOI2/EQMCkCbJ3HM4AeWImzOFB8EmNCbTzEwaY7oVHvM94sYyb5m3s\nDmlhiJeDRXIxxTblYL6jRZuSj1rPM2v8yDCODZ+crW/wtkuyV33kQUoWMgCPad5oc5tPFX5mmzjn\nr8jPtblt8aG1mNsyaxyrME1Ohfn7gcuUcQRbYWk9cKAqI4HGwx8pke3zl6ZGxGwNiQ4cEOmnpIW3\nmqBQcvRnRuwc4WLBnL2XmUWv/DmNefwmrHTVDpHi2AcjOl/dvB+5ZeyaqnUMhaCPt3jvD60CIK1R\nJbuC36Kllrz+uY7zKBjM0K+1jx205hEdGrpw6TiVNwR1qgYO/NRZiGF6Oy93e8upMS6cOp24br+z\nCxF0Xu+/6m6AEZoZBd+FUcKyHc/cjZCli8ZU7sYEhugE/ujn1tBYnoH3S9isTiqQZScAKWVrHzLX\n5oAZ6SGAcjwTKVIpuXM0rDtEFrO0JHR1Nwl4mfA+jJNzZ4nEA1RQOK+4cruOvoliOTTavRnUU3Vl\nsjfmoal5FCRVpzfPHHfCfcQIxEJGL8+83zbkyMkAl4a8FNUQHjgmvV3VanJ0xXOfwCZu67hNQO2J\nJBzumgQSR35wXMBxtn7i7ZD7pTFgpfSBHQBCEpkxg7iC7v5E2m7Zp2T8gjzBeG0W+VlaDM30z+vC\n22NLO+LTxfxeoPUkSO1063CcahxYz4FMmx3DSjij44lKun8cDPwa2J/XkayhcwT4phFsRMN7BYU7\n89Cmgdlf7a2ZfXG3Vcjtn2yfkekq/Tj+S+0xSXVqzS0H5NyKqQZqcJmmVX+6m/v882NFPHTGiFnQ\nz+Ptb+7dqpb9v57+GXCVTJa9jif6xonW0h0TDncy08p8fKDaMEsZGox4C3cQgmjciORwhSnKo7Ae\nVgC//kXJMtD+hSzikbneLDIvyu4Swzss7/QCjz8uvbECTmjkKki8ECnmm7xc+85JOC+ePO88UA0C\nCN0REzsdyw5Az35bBlZPvsMbgjEupPZdGWA9symkYjVDDlg8Oh6ar85qtpw2jMuBdW9FMY1r0LTw\nPt+lhtRxhTSzyK20ZkQ5vJs3bW5K4K+2sbfm8ANUb9czXOlIROQc+LqnaaRg+qKS+mroKghIlAY2\n5Jgz5tp9g17+q7iho1UviUkZiuNGe3nXMKV1TGc/zRP9cqCDuuzYfQPPyUEZkYwm65yNnNQY7zSl\nx5GLMEdLp0+hjSVUGeDgJ9BzfRd16vQhdzMuhAKKu+IjszJt1oTCdK2D93Z47IDDr7eZK2FIsiV7\nJirVJ68XHnZvbnl6+dFX8VV0/OvnPIjLHX3b1e7REXSWp/ThiPq3EzJIlnneYKIj9HCL+f4FOGg4\nxzYP8/v3EN19409X9ralTFqcyJ4d2gKLEMUiLuUrYxUqFheHVhpM9ayGex3/w1lQ4oU2Svuldn98\nA9s1Tphlcs0oApEZ60xHzKL0eCYs387MjW4Yl2xYGSxp8aZNqp5YBw2jtY79v8eMaixp1eokMAk8\naVUIOn+vXXiMeaa7Y9y4tSHDl6u5zCdxisOa61nTZt5W94E1Qr0SY4EFlln3cRZjnd8aOHS5epcf\ndBRasSAV7v/vrAuXRAm1m3ugIuJ8NghA4wtyyF4wZcfoPkxNJtTKSTOLnT/NOe1rrnSJzZBp54tF\nbrTF3zmUTwUff2wYl9BfUhNiXZX21OA0D6B4fT4X1Q/mEPdreqghbS6Pm6+sg969DLpPejfcA+1R\npJzbw8FHO7R9I8qfaIthtR1X3Y8uoFQz9EuffvzMRPTnWc++LsHDHEgnD88tAONFblFQV2k5CN1T\nVR6DeBhaHAKyHIrTOYUVs86vBJ5HbPTy3piEF6sbaqPE/A4eGKWghhDuw01LOqkUxDySUC7kukWl\nj1bfPmfPMtUZpWxRcj5L44BwaaZlAVwAr5I4La+/VtiHyM500u4wi4yvRSC6IQtZsIZ76JrNxgIz\nFU3qTzhv6b/i87xAxHcvLIiogoD5ktvrrIzoWhFao6yPhottrgeq0CWRfpdHuh204GDOuaZVqMc2\nQW7jVzv+rzZnpRS8xFVv9y0NSYwh1nqGfZMVRnZIZK1yrS1bQczNxzTBMOGg8DWxjP1oJYk4IPOD\n6AQhwhb8SGqOW+SyBNSrQOKCmAA+9NvyxdSWUNRmPAk3OSwNHo4zyrWPFqTDqU+ZuDPm5UnQExIo\n0PbY7uJPUS817ZgnsCMr94SS1kHhLr3R2K2i4fTo1r5nmecZrjnYaVVrMf8/AHeSIoKuik/Qu9bb\n3QfnDdgXUfag8FBETF+G1kZmUsCpD7yFJYIM9tfIm6YnVmJZiFQEYFoI+94U828foxVCQcF5UmIp\n2Zhphv2Kms/OhiRIX1soi5lITF2jnOKJ0gmqoNSz04nwBUNXnVOU5X8X2A2aEXd/qDxx9u/HdTFG\n+ytyrIaHUBE4xjiBUlV5E7fXKsIL8XhBoJbUvM2pqMFw5ZRsZnIhaXJygCllQvWVGwkp4Jb3kU0j\n+xC8yWpnSBlrzbSsMAVl1086DAt5vqHY/bQ4nfT7GRxCLossoa8DrtE6/6HL2/PE9wvkE3frQHa1\n8wEvEzuGj8YvH9CCm16u96wTxS+SdmQ8ZEfkTHypl5+3U7W70z0VqpWGygY5z+1N0YXo882CtyIq\nXNBff5M/Y/jTFYfeGMBlWx5d7HHkB4f4NPoGyAOCi2wqzeonY3NUKm5VjvF6zNSE1yMvn5rvlzok\nsvkMQd31M+2LBZnV8B/5kwEz9oBQqlGc4tlq9H3JW0Xd23z6A45CM1+MNF3Hizig4HhxzwTo1qg6\n+8okHM06hyXT+MZa9XjUgN1aS4LI+q795K559JepfRvw2dJgjNMGtBDWqmcLsScGxlAtZR8ZEyQB\n89sSLDyYUkSnBotvzQFlGsQUeZI0n4QGQ7XluwcIKwGohyQNMB9BB6ypRgy00SPUpoz7zjZ+v/3/\nz7gbQiIrIji1m0h9Xl48LT/wwM7VnKO3ykx/0YlE5EqRUm4JeH5r4/HDsMMrXSieeJ4dGpzQ0nM+\nF3tQItpTewQdJ/Gp1u8Xe/WiPaEj50AZbGNwuF4EpCQqns+b1speSRHsonPhw0pjIavLNDpENPLz\nhvpSLyfbNc4e1ftKxEN+BAsEprTORUAjFeprCLO0UaO2H5X3eotBox6j9WIeHpA52vwtKt2acM42\nOrIkPeDXyL/xvrjdFTlvaH6joPH53v5564fUqoZP+9/ByZu89O6FVZMi0p75voRX1SBK5fF7y5uK\nuF21rkdvwWwtRxxlWKH7X/ukjUuRJIMqZVCqUhowQJyYnozF47VIRdIrusP93bDbLJLqg5MpIJo9\nluX9pH2n2WOXecG0RoWNKaVGVIwXx774C8SDFZvgWc3wEri5+6WICGuAyQGz8/Hiidtf58lvpOgZ\nOdQXAPbZmI5vFrmkO+Djl74Ts3XM1jS0oAqW9SS/zSJMIewdkshqXSgydeE0Ob6p5O1n3a2iH1TY\nYZGBHeE2hbcX4c8ra85n3uRos4qFcMVdIBh6cTHgmjOGsSwk9wuaoAP4ksUeBISSihPpgoeql+z1\nfQt8gS1paDacSdQRN0WjY01TRPVKtzUyAkoiYK/IG+RgOUPEy6WVjMvZ2dQE4jXUU5+9lp0kF4ou\n2ioZwtP/PPb3yXzIwFFiyaF1vooPgHU++ObHevHJNBkbHukGelb8y+7aszFQPPZkLvBd1UGWAnbE\nE71bb1zEK16e+Y7Cwpz8jHrNfzVhRPT897TEaE9zVw5WKGbpCHv9MPai2PLu2NxSTdPbU9h4ZSJy\neQRVMz3iogzV/ESLOFdRjO4lW80fY2eh6zSA76cveRkWSOf76LfWIZ8ZqgcsThnzlj9kLCmcwuZ2\ng0HjkMhpfTk/vA5xJewrpaANNZ39AcVidqwPpGgUUx3e5jwXx23S14FmlCNXvb4lO2se87jOOxdf\nv4jX0KoY0IfqF1mP95J7y6XuiTqiumsNdOijc/XsObQkV9lNKaxRcqoUoHzBHIZ9bdHxY84ndQ6I\nZZL5wksXiWOFIJRkQJnn4lZEPgm39wGazOjofSb75QIAVlAg0zjJqpOdXqZ2e4v/qez2k2M72o4C\nITZ7nT1Mr3RQCRXtbg3semrh9MHV4t3QNEFrVkup/LxH7SaW2iFYeJ3xzLFbqg4EukRgA1PnqtcA\n7W7yY+EivjdczHSSU9cQPpbUTtKM7U8sj0XTuMsdhq+M1uq987jIkaxDCjHUcT1DNaf5FIXaR6d4\nuSGNbEll9nEWni6+UtSOktAWutvA5dXB+T9B/b5VKDUojBrS/NKmImBozWDp9XDfODfN7ZHI5SoS\nTyydsS+M+6pDvSxM/dm230905bElleMITg2LtVE291aRHotAEw2yWMRoZba0XoBikPQy9Oca1/py\nGj/E1TEgE/gaLPtPI9+C++VpYSnU19mce0dxYD7AkEoqobzdeQaxo7F/rOrhRli4bi1ZAWwwa4l1\nef2cv/RX1ZqbSb9vVuZ5jFdgP3J4rElkO6rqSWNVtGwFrtVvMYSpu7kmZeGDB+kd24rem5d3+yeU\nh5uGrENRWuKS1ke7TGcKl7o+nDCwFqyo+5EJoKW4EGZXnsVGJ4/C1fZDiLg/x5bE4I0+C/hn7prY\ndwqxXorsSLiGnY1zXkVCpnqJ0NXlxGQ7wQBNhGNMmFo9MiXdBWKncPQEgEwIt336hKoPtU9HetpV\na9ffoXEg1BubL0y6pefPEuNm2LZ7+QOL7uZkfwmnax8ZmaD8VlbWsNePeZRvMK4MKlQrKHJTiQiq\nKm10N75RwA8E/Rj/g/E/4kwzjYX4F6lWKSNyGicy8clI9XZzJdNO61ZmM3W7M1uJg7Dz2Etxdohb\nbd5FhKkiXhQTjhpuPSP7C/oh4KsIzFrLj7weX3Nqsnezh7mYtnLjNCfylfhssPQjWc+I/ThWF0OK\nrdjm7J852mmEnGcZD1uK8qkB0JEjAGgtkkiue828UMb0IkuB85wfgpRpkS2x0yo9iRNZ+NVMpKjF\nA9H8RhMewv5ZFApJL6AVs9IGDM+DgCkL5Ds9qRelBnDUhSUwJHKVNLSRl85BXnhBQ1Q4RJY6KIj0\n9U8E3kb7j8eRno9bszbq2sgN5DUdO4ypS9LDKO12G0FcHozhDOXoWyFuNLyjiM/5m97BmurLnKs8\nh8LN2FET/w3ImdlfriDq5aBMLOKhO02Y6dLMG/pTvBqNtPvF2nzJndOoOksmz8hLTT7nz+/AFpje\n0btwDZ6w9ad7sm5IcdSSXk5hQ0fDt/FxQsQCcN1rHi4VseMyDyEe3ZZGHHBRFFBmxsbU+p7uBX4c\nTPoy9KdfWyK0xJEipY6BlazhlPYc3jcFo/jKJesXeb2MSyh84A58mKpMniPOWZK0Wudr62aGIVVP\nUcd1D6JPPy24bac3eKWvJQ/nDS97t5apPVmRpTQT+pqsoLHGy8I8SPrji3co1sFKTW/p4pJLoalw\nJqJNPZLlYyZBQyAdgIPeTeVwbOYxaEWBZf8fv+LDyua4AMr28eQ13ZkOY4ysChpWeY3kroje5q0u\nL8rL0n8r6KH39Ac/m6ir/v8HFew7a/UXb0lMUlGXHCKKwgOCG+nxK9+zZaEugg7UtDUeVTl7yqPf\nT3Hjd2Ymmf8PqCWl+3UBvVle79UGZKAV2qXhVR62Os9H1n8J9Q5Ssq5J/Z7H/77jjjvijFj5e70P\numc0Pllj6imxDUbI73RHUsyNfYz2qNsnjvc/iJKam3/eHiyLGhRtRgOEbr7H+7389HbZHENxjqEV\nJZvAo6CF0kp/MoL9wZFb7/AQ8La5Ajp7dUg7NBb8aFLYIvQv/LrmS+YXl+rkWZmmfu7oLlW0/pOW\n58kc9o4UZwD2N408SXggleIAgMU87JofPn+uWHCCQhF9VijdKMswhG+K5cy7zpuA6vFqGyNxwcHW\nik3mvU6Sb/gR86jxULfqaooMLpPOPNyVK/OM7/5ly4fii/lAqCFDyf4XRH+Q/t1fNyWJ7Dn1PlPU\ndNkZoRzDhSwAE62BvmOwkpOq+iQnUSF+j6rI4fFbz2pn0psncJri0lyEkWsLeIfwsKpWjOGQsP8G\nF9rXB9GFaTZqmUI5FPkbJYkBwAY2qFW1/PND+nmh9E7HRVCy7GJ5FTO4EogV4SJd5rRq+rkiI9Z1\n8LyoF0vRqJ8/h9YdwyVRSetQyN7XveV2ERnbyavRKo5z+rtHpFyzX+kSpoOLK9ObdeeTJdNjxk16\nzR/Kzt+p5yuFFwmqhqlAUlD8DsX0/J6W4i24Sva77VeVrf2rLgwoVwp25F44hy4QNq0svGMrD8m0\nus78Sg52/EuY2PevehEJelNckSdGeB+lM7mytPYOOGg/flNT1NI84nm97BDmGBhFW3FYI+U5KeXv\nK1xWHj/nwCGAWoXWEmSo2wILxK+bff+gADV3yh5mRYmJqGw7PXpC5TwsISHectsBYBKkVH74x7P8\n3N9HYl6UABux+o95iDBhD+2Psb/Kfr3dCsmq7GATe/P2SmBxQbXVvC6VBfhk2ASOJJVMlyKVnxLt\n7wi+5Z5dxSkiuV+PlTu6ZWq1KInBlOjDYnWav4l9cQO55AhCOYJeFQpvMZ7cnR13/JIUCnx8XcST\ns7ZI8leVcXUHOmKBzzma4+1wY/xKiIbA/v/JK2BPkdaEcYFc+GdrVJTXGWPjj7QzC2mk6ZDYLxe4\n3g3xJUMdENDqgirjKxHwYKIE4Fz91yDsX1mfdmhs8kqVKwolzP4WzWZBhIX9T2MwwP5vOuqlch9Z\nF/hUH4iyFTddNsqaP1XcdYE8//u2gO5jvnbMlUno1RrJsy4QHaDkvAtmNXOoEsx7Jto2u3W9Nb3P\n0svl8j31OzGJz8WgODqtxwqXPyCfeSgvfh1oD+uam312r2kILD5AMKa4Zyx8RyHh+N2yXpqiXgaY\nHZDcmf4MDPlPBQBiubt9EKhXGeVHkYw1m+RK9IqSAlbtYa6ibYosoHY67TGKjQtofBfZjfSM8nss\nPRv7UHvzk8Cx8RkguQltcOByLDexDyfBIfJhHxB0RflI7WewltNiZBx1Xm9D/1czDC26mn4lbthM\nmJ7yhkQ+34lWS6tNWI9qzfhTTJt8b/iYGCBrv2HzJ2qoG08MBD1dukuYJ5tcMiuXnYWXu5YNNFbn\nD6bKjeWQrqodfNqahw48yWlJrCDI6x1tHmtZHvxmI00ZsgBJqtcGj4IK9RTgI/UTA+Txz4uj/jUR\nvTb95I4tbdd0hgXQimuHKe9utSOK4zNfTk1ESXVLe3X4Sg3WzjUhgHWbn4Wbf35rCvHidL9Dz1JT\nngnwACTwkGyT2oEOA4rIlDbomucNTrbGQb8T3z8S1tdwpWUbi59tDgQ8WZreRYTtkGS8CaTiZ5GW\nU4wauNfeR/hUdhlxKkhG6TtqV8YOEm+bw0kCYKfQ8ymwjIK922G3rF5p8wIzhroSW7EOsP9KZkaO\n1X7mAJ0ZZNQ1lVxzP4bqEueH9vszRkELWc901KjR6uLP4oI/wG20XtlOP1XKaZeW+E1O4OkUtnH9\nycoyGZsCWY03F1BIyNFA1MnVKofuiPV2Nzgquy3O5oNv3izaR2YbwGmcdaf63Da6JyrKsZVSwohg\nZbQylWsrpj553JZyQpITgAFXvLpqPmZVDkFs1v3a0w+cnDTnh0YNMAGUCOJUuq67UcIu02x3jl2/\n6k7hrZf+bPtxx43rrkbCIFfXcV0SJIZ0LI7/XDCBg5Z79W9XCU7By+r+OoPJaBrvvT9ATZExuzPb\n3lCc/0dn0AiS5nArmFhVCBKuIunusY7ANSyhJ52qD3rFDgsE7RqipVrEuqWxcNTI+nfns4QDuyBh\nS7BsTcyUmzNeeZDKKGj9ci8K5C0icmjfpWSLY9jKhJWFZ6eE4fdFqmFOPvYPoHYZD2EO6lSHl/y5\nWPv4vTgjlbi6zN44VDh/IVdHznuOq0C6FVGdeLSbZRDBM+UWds99do1GswG/9sdGqBa1NATItfWH\nN9m9tV/QFzgy5WkeEx4PZL7wJ5Rs8Rf4kM1aljBMNGBavIk+tkCGotRf2oR11EwKkPEDe9Ji1Cey\nJoxoMu7AgOUbYnV13618hfSJjrFqnoeoR8q/Tcl6iKYDDCyIoi6sXeCCFRqLyOuYyUFozF6bAMSh\n0PnKq8NcGb+k9+t86wUp2riVj4ZomonaskFABB5nQ/h+TCf27BdwIGOg/qtZFZVcgn5QvcClY/Sr\nzeQdSrL8gwZfwH2DlXXLFvpXOlNhGGRv4W2GSBQLkUDV2gdWIjo17Q6Yyq1UEdgm2UKNlzzttDPm\nrlqyUBxVqe17QpvXRqTnrrC6SxcMl2ddGhU7k9H6P8GrCvnkUyhdVtanOiriHO2Ilgut3lL3ynVT\nNOARNFgTDfHwbiQ1k2HgMp9WZ4X63gmH8PB43IHAcHZP2EyvHU3cZXKL6UIkB+wO64dksqW9BYdZ\nii2uDp6B36lG8YxsUK9gDP7SExSjhXQIRp2W71/RzgOpAwjtRcnuosZET6q8nEHEL+P9KUnQIXEV\nephtri7X5zgQeBUwGmCbPkDHyTB5sIEKvV3jTGVhzQWPZxCdO164T9ODuc6/Bix16uRFdYISFbH3\n6We+Y1lVyNmd6jHh4wFfbsEsh63Fj/kfe0oqrC97bWRizI0kntKqzTTEqCidBDvwT29MM7+6OigU\nDyiMR9c+MSsubcjFKhVgblCkaurzI0evM41NkGBq4Y5IAiv86mZrQq65qcbcWXYYIpM05nPjiDf2\n7F/jhM59Hl9aIfLEL4UUR/CfPvon+HSNSEwVg7O3T2LucqalPC6AzOjB91NixKsvdBv5tHbtdTOq\n2FM9wGxpQ34LamsW6i2cDCHWGIcFrfhx4G359UARlR0JMbpM2BNyL0pUF62WVwRnxM+5NreECT5e\ndoQD8100+XWJ46sFLOIv7l0sy5QsW0JaRR67MAqEl2mDPLJmqspEf5x+uEzlSvMAU2RApzFCIJQG\n/H2bIn8MyLTQGvBw7kpTP/MA5niWBBhO3NW7Y3hI+jTllwTU+hAveiFORdBaLpB4n9RrHLiNnV+c\nsOetq9iqz0KaUzNmE3IeLXV9zqURXdey5/xnQfeyEDy5DBEOOkGAAyO8m6MCfHJNnM77m/Z0c+SI\n8y5XvZDB4alTqAEy+hDxSJ7r4zN2q2sUUh3I6UBRt59nR4BbH5akaXAWFgEmTot/SnvsYr+R/Loi\noIe2FARH09teADW2RlLlHTUXa8V7OwqkEEubabWuZn7aaXDMpJfHXWeSJkqfn7iopl8CZYNC0aaj\nNML2g+kKtJhdyu+hC00MnGoqMLYa80nuyD9Jx2qntgq7T6MRXZT6r+ceu7RHWKIb/xBzsO4Vh+Bv\n0mAC/FUF3J4c0VyeYZ1QiSmoAOfOwOF4JaigJ7QtXdhrwXoAv7itpU5gFQs6Bfdh3hhBiFmvTFh+\nhiAgDgl7zsDhqoEKagt5yZl/8JWocN2qm5SsXNADL/EL0yED+J8JLAxEmbETWWXVdzapfaIIL7DB\nA0rXQOFzGnTdAA52jY4guaD07V7xe5EkB4722/uUY47t5FcnJ4+ikis/jtzxgEU3fDjvxCR0mDfT\nrBlo0IO7ScNt1OahFsv3ri8iYmSYUtnYGoUDHsgdOEqh96AZa1Ngc1BWJtSYYVEf90LGtCg4wuBK\nWQOnwrdMgexGl3qJJKXT1T15X0oPVFtyrlJYVO26kVPQv3+VbXVNUWEgzbLywn+N9EVsau7SfcyM\nSSHZaAY+XLbt8rkIQs2sOGTl0SQLp+ToO58d+cNIV4GlcZ4ehbOljKh6ldb80v0GC+MhnI4uDUAo\nEMWY0bWwTXzdE+RxuhVOFR8W9s5Rq/2GOzuRAtN/ELMi4ebYveVCNYCFpfjlsq89mBARCHFHFD4d\n5cNoMXELS2zOeunthrqYsFKOuavkTUnufdVc9Pm4beRauyoZDX7+uhM40+V60edzFGFw4FyTL3/x\nq86+4AwlyNAWgEd7UFz92LNu52cm6ShJuC3r57r88Tl0PhZFp4wbZi6MPPmhVhBvb5nl/hxM4pv3\nZtHYLiJ70hroNYHjQ8YrofaiimNeQxvzb+4mVAXy2ifHDlBhzTr7XwQmRyApW/eULggQ6ZZhm9fg\n39w7QnckzOqemBDDDC3elygR2HN7/u6VNljE4HpzGJmG+zCH6rgQccNQLmKdncEODumv9n7YLpTg\n2IC1AbGX7zoZfnOEjiJR7J51u4KHjEci0Fr66x17PnRXqbGjjN0HJZV51AxMy71HnTbjFjbj67pG\nhImYvb45ZGjyE8XoJXDH+uoqAoxAEJHg/nDSjMkOpE8+lz9iBMJW/FCwrpgqokeLGlgYFpLQj1xU\n5MyATQb+KuSm7OTXf6uasw/HQi2H7UQb1BMCsrVjvALNgNOl6P7Z7N7gx2NerLlw3kexjA4rAI7P\n6jWyrdRvugxRdoU5eCMFmlp/Rs6fjENOLn1IGoCg7YcEW9wHwdhVjG7xBIwiOF0b2F4FF2SXUj34\nxjKy09iTCrDrvAklFU7Na2goyGheALNc5BRb6xR2lb378Il71bBY2ddvzHH6q14xcTpKS3WBRaUr\nEvPO7Ov7+Xf1PCDocIkr+tOFp9Mz/0i8FS8v/gaCQYH2YgVfKTc8fEGeZRJs5XPDnkP670I4nI6H\nBx4FLOByYXdDKWGzFX0q/eoWMCBiv0JEJqO2rBK93MGAJoacf2GwXJ+cErdBkUQE9teMz8CESUx8\nwhF21qTWvbgF1JoKddYjwR6NlO/BfaFUL1dtYcCjBgNR1jQlOgGxIa5yV+vnjnfIB4pTOO17oMyk\nkOP2I/UZB5FC/BYPBTF+pzQ7Ancav5p6lMdzrHD6/qiSjALu6g0AGXN7CV5vX0sTjS4/asm3aPzK\nEof4eKQnYeaLzksQGQNkRTZosc5AMYpfsAEmkrNgXAbWTPBwMjzgC8xJICfl6TVWAC2lKlFeyu2b\n1avcWmgYRvjOlnVMDZGpy7+B4jF7CN8NL4kAf4hokNa2vB4efCld8D86JtyEvwWL+RQhBwrg4ANr\n3vZEsUCqikhoU4TGUDLH81cBbsnNOSorJqp+twWiAVySFTg6jvRU/ZOK9j+djwzcSYBHTepeSi+m\nJ+FIb8cmeTiBtXXNb3YXynOn0BG9ngQR/Su9n1/vbDjfMlbsHbEwpyb8oEPc3xVr4zTn2jVG+uAn\nFGt5K8As57NV0JeTw3eY4A64hC0vuEN4waaji8O9nsLhgm5xZvCb/pJgAPdROz2lPkBk0KFMw3nE\nizAknlU+1Fu81ilL8rRGVoUAZ9lLb2ftDjyGrLo8hescMh3Y+7mEriHsFaDVCB0NB1cDqzLDV7Ac\nj8oxqFxDOA3nOO+UdOjNLYffIdHYIaZ+61EBoi/nG6wwWZQDl7un3h9HRz36GEBeoNBQcsFk9WpO\n6H7cXIa/vxF+4/uciwgmL8UXVUbtPmJh3A0Sp93O4rfoeP73hUPnEmMIzEGbCJUTbMZkVExZJfBl\ncj7A09QcsIXmx5jkfbOs0rdIHBjmwJeDDDR2y1ScJnBOvk7qwex/TRY2NwWXBY2TbzlsPhYghDaK\nyOfbK2J9nr35B+JAnBmkJ8gxo9i8F/E1NdKbIc0PwQ0oryVAMgiI++D2mPZPHxglaWg9muYSJn+f\nxeNUBPv9VGbAS/L+5vvZwTpEHA09DAcgiQ1JQNHaqFCYCUQqVRZjLABLMjlTe/fCeFVkADPGK/sX\nC/oEjt0g+SS+n9uc2pCMkM1g5yyHGwdYaHPRfdgHGH8nDg6Hetia4R5ZD/W2PnuDzEYe68MsXIgC\n0oVxTy0FOduD3w/g0/kbFZt80uBIud0uRYxLo6iU2KsPWJsIdRSSUFbT1E3vmvYC1cIDpQQXGavT\nvNtwcfAvkkq9w5d0A0B8g9j2QR2iyIrLIawl1HqGQ9cBf1gIwFgmQ80xhz8J3D8teAIbj8gcMM0r\nrqi4Af8N0t79uUUVTRfnpAr6kqeqmDF+7szi6wL9+5aV8vH955xsM69tcmZCsqCuvZn4rAhNxgEO\nMLa0p0q2cez/mAm67Vs9b0QESY3zXllsMKa/h+TCyYjksR0fwa2Xd8juYE1dAUpLqUZVDW/cw6lC\nd/Hj5zeElyHmPlmZryvnido28qnd5tlldNhMfRdL7bQLcMICqWJ+V+hlWYWj0VTjSX6MwIONPOHf\nXq8MTlPDX8+O6tQ5li4T1HVLBQFZZXsAFHUzam/DcY/bEo6NBkJlmimrpf3DJ8ZDub5Dlagfg66h\nNmV6nnykl+NXtXyBRm0S8vSIV71U9mfxXZLQFEhTQVzOpkq/u6rAvYU+MM5GLvuEX4o61PyBa8pz\nLATVXOZuqabnwz9ivKFekOiHrwk+vWPKg9NUDY/wbU6QhQILIErb/hhq0VF6rSHdnYvLZW5GYW21\nHjshk8C1fGtdOVlAc3i3vs2KtafdFqvOvpBpG2MnGOFIrM1/M7gvbwdRya5yVaQILNYXJm1M2n11\nAoB/HyVMXMsptZYEMGf15+Kbbw0tYTIrS+DmvZR9PA1ttQJSOkYaZjLx2gPJDBWPvJYRQRzVuBHH\nphZys10a/XCbD4rFHBDADK+XruGal0dQ17hcJCwuhExRMCcxHPLib6pz8l9hgH80mWW79wscPPg9\nyr0d9Vw/O+5PY7Idvwf9LwD2Ug+tf5xhubmuVStXeRFnK9xrMaE2RM6PlGRnm/Sa7vcrGj3Ubwsx\nUI04+GHobX0ikhHq9MbnfBRkTnsX6VJr2qdjU9rlpkb/4XdeQ9uTFmLy8+MUyA5iYDra0XdORrE0\ns/yjIc24fE2YChxPrX4EVWv4YHTMsUbtxhzCQ97LqWULNsCorfHkOxnJlzlVUch/77sD0XqUsxc+\nIrYLdPkSIVOOdshlvvd1otJHa1Wxupm0OQTRwolFH1GdqfZJZ9+g7gjQUe6aIFgUUKcGcHqIUKrA\nyEz4JLJ0J49Qkd7z98KK0VEQXwP1SRBevgbVdrdWTlEuZKz9aJPtPAlORcHmXk5DsnFIPapw/6IT\nGNFRbuZUCtQCvbw1i8hIMHHARZ5K3pDG7PzAFW4Rc35mePrZ9gzNt4gEsdbA2O6LmolnMrweIEH+\npG5phk1Zmuj2/sZ2nNeAfFPD+pCGbjiDCIakEpW355krUkQVWyIivMt3CKTfg//W6WHLNxihYtaV\nKMVcBWoWS1P8qynZZdp55UVbxNHQrXZUzSwPxMY44MmAOMze/I23SkWNycRl9f9ZTeXZNOdPLtXF\nolS0mfhNi4Opv8S4rwPsGxbfIaIR23qQC5IOEMOTG/CM4otHO7XJksdxAALo+1s1XlsyeOdoW5mB\nmlyv51lk/EcmadK+r+vVQOYFpHb7uSG9mfR2wBj3pjnbo6fDcJ0MwtNJRAgq5glIsufS/8mAdFIo\nyYzhPNToRCKkK0aeU5WAGthLlpuYNlApF7OE407DawwmAhVzILy8+/2DtRw9MbGRUodzqFuhZ+4c\nzgRURet6dBc14sdJnzPB+Q7sJ6Hg3QG7L2R4DXoxJh7J2YvRtcP3yAQ6XnvT6InA2w18dWxWa54W\nLEQL0TxqK2h1n3VHSda+Ho03diR2swQ2gtI2TeffkSG6+kZ9p1sxigpt4rbonIarxQBZ3hbXCSf8\n/irXZ6eqNwWS40yhbP0JEwEymCGGUcxYmfCcni9ejamWoSpwbg2kWttd3eEESfttsB9h3FIw03JC\ne3NnXS0Tf6Ziy1+5eIDSg2qorKxtEYLlBYa5Sa6VGqeGpAYLkfiFutRC55S01rZD7wypMCiAzUva\nrW6wx8ewltTphGPmHdvQg1FsSUkF65XFE+n4daHMa8e7Zd4LQ/lJ/+djthxmdDI61Fp88j/xwpMi\n2W/tt+zMirEVO+wz+8mzpyk3sPSXZzlnH2Nb2N6bgTNuAxXdhiH6MZ6xEfbTgmJvNS+MgHoiGGI/\nN3bKqMhLkdvsBR3FGb1HY/JbF1lGgl2lnLJYBh1Wwp8DTX9c12+Z1DFtPFuEwlcKnf4tC1O39+Pu\n7sIkiV7mzW3ve9Eri+JxrKs4Vt7DX3c6U9nZze2lWu06BxiTCYUvw6mRk04VXnDTc1Ihriol23Ui\nzq7vhwVhtl6Vuzuf4e0aQ9R83wjJXKqJgBYHcQPuRx9Y08sFq92dvfMDJWyjRhFEKsc5L0DFT6ug\nDBQw6Hoe08XEVra3QYYoeeCZctc6hRBg8qslGy75HAgbjlK6RS8WUOmcuNW0WVKbdrgupPeVCNWT\nIt2BKLITwI92K08rk+YOK0JrPGbNsa55/Kxc+/+EU8fPo0n6oq8no2HQIWhK/dVEf/wDDF7eW9XA\n9B2xsWjLPgMLCtRU1ac3txk8G5O0pa9MTqkuANSZeud4ajZVyCnM8R4VmMp0V6oAgz+T8qhsKARh\nEcj3F1WODNZsPzaTloyuPCmx96tk6GFUSxU/X9Yfn6P7tfzIGPPcWqa7VxD8pYsMUEr6gdjS189m\nmmnsatEX1krtU0GFOYC8YNnAswxrhWwTmXIljha/KmW4QjqhZM+QehkZefxWv6JMeMdS6TeC2wXS\nRnKWnybww7uAMYK3HalVcE5cxphd7EDb/hYtOdCLZ3uocPnOwDALiMj3umr8oyQPiC+3j2V4WtBn\nw8hBVTOqNBP8S1oH+BUIti6XvpW2+gxsZMn9ljOtbN5lhcwCUwnqymZ5wRagLtKoU0RaR4xiRg58\nEQZNqK1lDbC8NSGUsjjfQ6wQ7uoih7jYXZ7S41f5JFYKhhnhBjB1IJZ9h5pAUhIag94hrv1TO3el\nvj+bWG8fxBSLMtIOtj2myJQ0JIUEvH6j/rSPTVTjGAhF5pBOgLoEeeAA/qWZFMqtHuQkxwVY3xqg\n2Yxl9+z0pKBsc8mFNiK01Tgklh1RNytoIH/XHmpd91hjEIOQ2Ott07qPZflDsmDX9bG9Z8TYN1HO\n5FiJ+/Pd+7a5J5RcvBG0OrUcRK4GBTkU3dR81MwQzXpRBfkwm8i3Imqakkyd2jjq3Qy7mBD6MBaj\n9BW4z9VgEZRJh6DaLoanQvzv9ydWS8UeWqQSnEuq9ZvazUvs673Ae1CXWNWGNNGfECMDpvz/KMpx\n1zBP0ewP6USpfkWybZ7er8oHK1lH0H3X5ksg15Li0sVM+s08WPn1oJ1LWyNFsVpJ8/TwDlSRy4/y\nxdKgUOZobTqENvo4tzI3PCk0k9wMRkSzZw4RSCapgK2T21DQC5VPv343OH2IczRYWIEbyLJzZXy3\n+iJ1c5zGJxQl7U7StpqhRbGcJyYwzSW20hFF87UECCPpyqq3pYYAkF/QJmTTVPAGHOS6ASinhGbn\np+jw3vwqo3GgokOnTY89Lr5PrwN9HuP0MYNor7onPMd7BateKQO0UC0jZDc0NqxRO+TUL0WFbsjh\nk59bW/XPlz4H2GFWax3w7vwhKwKW4Weru1TrIp3lZTVIE5PZjpEN6CjrAIBRwZNYXrZVvq91wxO4\njGoJzZXbC89zIs7CfEPuBDlXaNB2mxJn1hBpII0xHNuhrwoTShQhAGD6Pm7GI93qG69MQl8rY24b\n00/Q0fZLABUdx7htO1Qc+buziu1KGHjCazArb6eBlDtJa6cNJ2cxMhzQLWla4wuWzfw/v2FIBkh/\nnt8WdZcq+5dnw//2q+nrLqUp9U3CRy6FVnc4hcfw/Dno9IALnpkeCREqQtF2s29xjYPw9i5LZdzS\nKAklu7wMR8/wgw52t6f+bVcym9jW8IJ9EsTNgOWXaP3HMp8YqGm0iBlhgdKDBmwbMK2W2teN5Sx3\nCis3XLVHlxxh91ojo1eCDtD4wECKLKNCjhtebFLTIHIAgwxy2mFzOee9ihQ1/qHy7LuvhUb6TthO\nYy5SF4FVk8BdYd9l44t7Rq0J6KCnG8Q0eXg8GYNhys662VR+U4doGhEWhV0So+Y7dbS14j/jvqMs\nQLYqGQbheXIWGQc/bIW+HkvVT8EYr16eBspOcYYvwXTibku1pZugw0ShrFmtOopjive+JXIMB/UT\nRTjvvhRcEZt+o3XS0Jo6vyQLe2aN7OyEo8C5NzBhXh2QmmNRiFzLzus/whlxFfSX4oFB6fxxRb04\nBLJUuFaymwZF8Izr7qLtudfPkjRUeM70txmX6zWtemXBNHsvzY/1Op4yaldrin9zWE/Q/VpjTvoh\niUdgMDzJZdgkzbx5bgjGeA91TFZuG/sdGJu0TZbkuzAH2El+5jjB8EoosEGEZk1AX07aji4Thu59\nY3kVgmlqhfud78rlKmriXho++NASb/XisT/lbl0M7cbD52LQJIB8JOZiVBrNpdUFSsIHxa9UlG+l\nUP1ROGIdscdqN/LrcbGCWLKljzceYZ/OwTq6FcAAsyvQjm9cjydbS33jSIVy4O3dNF4BlPsmcJPz\nVltk0rYe1kAbTneekaZ5WXHKfeKCcuadlTrDMdD8rr0kxc+x8YZraK/V3EetnZiu/fOOGenurU3E\nm1JXUuOezqHWZCnwSehlmU+3/elpVX717pddBYPFNi62si9nx4myZwNfSg1qSFBJu9nF9rwkMYUs\nmQv4/H+NMhwOZH9iuNXLpxKxikCHVg620mbGobOppQ09T79z5blqAqRnFR5rYY0NGoVG7hqacuuY\nhvhb9qwNihgDdU3eo5Pw0s7wwU7oY0WdMAVyQAHrGeRcTu2/sy8nk2h+UmKmuknXfmOiQqtqrFOk\nXiv7uNxXkp6LySPdxZeACRuXxMDMvFdLwcRVLzs8HOIrm3E09LL6oWRAhHJSWaDgyK5dBQ5HJlQl\n797EEIxoWukulG4olcMPYKGOEGP2tPiH9xjQxOH3xs1HdBEz4/+Oat5qnDbOFMeiOToZgfT3f6dV\nVxRSubTfD6fxBp8b1RZ9Frw8XUyxMUTvFwyh2FE7jt1yb60Rkm29MOYS9HjQVrMPvlLfzy2exxh2\nKX6fdHoMIENV2n4YGxzgHLvTfRmOG7Bj0rdgmdwZCY/Rf4SEV0chjT/enTu7lVXGyqQLd8JGXTRL\nEZTpWV8tKsdlWB0O5Y/cSOJtEXReCJLW05KErTeOkkgCmMcy1KhBX1pJaMB0IvPqX2OZ+ECAd1O1\nrAOq1gZkTHcxF1D7sTTm0ZXQ0TWWBlWemkWZ0zmGwLOBFAW4CEVhioQn1iGwYwU3uttl3P3+MlLf\nYJU5KOQ+rai4Sreht+dxEfEaSsLRY9noPuJ3ep9rKptjJY2szmp/DSwyIKMXAseyn/YprPJb3f9m\nDa278gQqNZOSGnrR8h8+Mbcqby49hcxPtW78o1PPTwWIIDY2lx0qbueTBrMUoMQm/l8f8tuO4GxX\npXZ+8VrmXy93UGS7GolrS6gAw6dO3zrpevbYiA+328tfyST1KUgQmiiUzEy29c3xakVnRNtxpuST\n5eWjGEqq1BOpblwRZ5k0EzfaiWQPvjwaBfyeWVuMvY5kgwLycMZ+WX11+1uqI7tTYr8m/8B68nP+\nRiLF/HEfwuHzHEvLol4AG+j63DDAMHvFtDJlsUPn+N3H2riRgAZWVD6N8mtea0sbst4XUCV1nDQe\nkQPmUtWVHRl0LeXOb6NQa7s4Fce7t2BjbrcPMApDKyfikpyBgL8JFMdnPO0jQVslgq40X/RKgZhb\nTcPCuoy377mKijnxSJgq1Gyefl0bLGkVacOwbj94+Mywdxgp6f67TlcG49MZxXLDZKk+2wR5uYNe\npJiN+5wgawJfghAs2RufxK3OINkOTLKY5oXW4KAjzvxJV+M2TCRPRZaMaqISTKPciKSzITevY5Er\nZtcpqtbbhaJZGd4dkYsvOA7zos5UIPH7sp+ehS4mpyBUbsiSP0v6od9Pwf6a5bv5KlV7jDOpMm+E\nJ+jhsybN9omTNRGa7zN0cBbi0Dt9QiQHBS8T4tiPvrGb124AoNLqQw3uqhSVpXxg8nsGwNd/cTH5\nWwyCI4AT1OGlwVFfTVJZTR+J5GGySnuNIgeoCngoL6eFLOlFxLebCbbqYM1PRORKVIkpcu7BumV3\nNtc41QqqSZZGy0CtwuZTGDzuq90fPV/HO3qyx/4z+hwZR1Zr2H2VRBPkZwZVBJUVJf8pY8E8lqyb\ncqordsbTDJX7lA4+rp+rtTShqs8ciLybnGQQsOJ/3jfj4JRkbn3EH/3l6QHVplXxOm0scq2CLsA2\nzLUE3lIDDbBxg1blXwop8XMIapppiqR0/G5rzK1Ap/kI3PqimAp7aay4sEDQKAiasfAAVpZVdILB\nS2yHJx0faWHDMC9qetdTjiMxIv26ca6gy+uts1XsjpFmd57wFUa7NWDxx7caD81M5wdHs94UIt9+\n1sYM6JDe1hkH9YyXH6dxlwtSO0fzo0cLVVZyGm9tOzBoUk/xsl4BJWSbnD/KXr9oEzSEPDoU/OBA\nnIF86LoIE9qGet5pc2Uz6bXWe/KivStfFRazXNTEMUGXdVR3ASclNlF6QgXTa/V9gpC8+JsEMG5n\nnGReWfx5Go/dan4+3lTe2jCC1SslHQLBNZr0QZlkaYC+kyQ5ApQ2ZRB1kw3ttATk9V+XPeEzepD0\n4MOwMM7jD7VCHHx77+pUydfoJvaHWu6HH+kDkAIXdoLwk08LRqpJVkB7jxXy0fHBb4GuVZNDkwry\nF3tNp9cym4wOsX9zxfxJuQZFlPECNQzXbwx6e/K40mc9ko9IPy5WjjQjI+QCQnxtbStYrSULaRZU\nAfwwXZyMoiUq9WeV7p2S5pBwHiTLwXlSPMGbP1LwhLsD8BYSY2PZcGU/X6TuTjh7vgbbhqtzBaAV\nrMKkj9xqow0ePc7vsU4jdZddJLE0qR/4+KTfmzAjSMmzkfSJBaerBIKsA0h25CvM2mTL+K08cVD5\nlEUv180Mtfn/8j7OqSYFdAegPpnhjqk+hU87xjlzr1InFE3VY71tUp4AwytjWJvfgWMWLaAzxpW3\notIzODK5Nnk335k3vPNS1s7NUTp5fjxVTXOqpI+lmmTACdLxFAzr+++3GtTX7K2Hd8PgDG9Mhu9T\nNkSvkNqbWo3AjOr9RfpaTAtFQCwujnRmaJRY1GydfUIjDfvx2n1D1EcOuE3LhMajP1pDVdzU2RbW\nxorUbtMWdg27aQMrnVEWpwKp1XySgJnTnEDyOFY0kMAfImwFWyfOhoV8eTAGhHpI23i8qyl5MLtI\ntzOuyUc7AxiXXXwQQ9S78SLp9m8oH+CSc6JA70JNhcKLPTuV6YCc5+p0ROAzcUZFzBFwgeG+g4h9\nsde99Wdbga0n1TiIo5lvvwI7fO1G8ErzmJHPX6vwLpm9b9fFqVHcD+U3jSeZBoleJVopDqRSrFrv\n/CxnmmvkGL/lW4dthHxKmL7DpNay2rQ3nY1wxCW4thTQiED3B4hcl40BZLJvlZFz57JcGORQxTE+\ng1TLinbheSYGhF2E7H+DNT1FLCP014Cklo19B0kmagEzFcAp+cjnMVMz/fBpl+DRTBYgvNZ6xA1g\nKsnPWBE0enF9ZPCaya/VUXlz9yQuBKTkoVpwhnuOiUfEf4b/oVAPLzOBPthTouLRrA0z5/9GvrkY\nZP9eI/sqVlbqrZCDNTro1KnxDX8lhJpHy2bTZK89StMKP2nYK9tcG5dlK+RpnKbu/HLSkRutflsn\ne81gP4tqDIm5GqDKzYCX4ugfRhNeO02/JYCAPwb9EpiR89lS/t8oWlQxP2cR1YjygQAyweWLHfHK\ndpeXB1Vszs/MkwDF+R3B6lc48KuSIfBoAFOygpDeU+nJr0Lki9VV9pgQvKcigeqwSTZlQxNuHbLa\n21bKImPwxTfRZf2IR3blZkx4tNoYsMzpsMNk4WTV808F8MP4D6pPWrDcEf7FaHJd5RnkJfmz6Y9C\nLFHKlZngPbW1oxB7itJkk4iDJIYb3ZKBqM8gei6rpfT/fXvwuWZrqD0XJWU2PE4/TWgrYKkh1qsF\nTvDC+NSGKVS2e4QUFJR5B05IK8fs63vb9b89PJJNAC7vxjYvVzf2DeYKPByyyl8JXPEadCwqB7JN\nllPUyUrfRB0SiUd3ulQPhsGd6RhUHOeaSxk0tqA7KzDHHbd5LP2Ug5ITYkmtDbFXZhMTl4l7rEep\nKPAVYNbb26K9YiesstXGTbYiMpofmSgQQm2/EKxClFp4VPuf1xMz/Ym0kzZPjSyYe72ZkWV8rrKE\njLfQz9jRN4TIkcz/XgKi5yizX92l49YsOQXkV5vx8Mv4JMv2FwdTcP76LtHh+hbYrlvN/kXNGY1x\nwwAwhCaQe0dbiKaTFAwk4iZxNGX+oq9Bl6fxz9ZAiVM3RjT4M6ZrDTM97DyKhcoIU81fMSo8VVV8\nJiDCjWBCzlj8cgnNDtYAmvN6PRlrPWERmwBJxL0az7BffYoejpuA0TUbCYjti1yIU86oSNBQ3A1F\nk9H4pU0fLY9A1QXueIczXw44dYf9gsUH0N6mrmljLOBgG5mHtaYLXWO8rDfoaFH/PZLhIMN7MWdz\nCHlY+2g36qqttwT97SnKq93z8Tqxy6lucsfGmALDhcBXh1asiVUjmLcoYAc1jkjChcfm+NfW25Ma\nu3qelRfbaakkyVNDqSg363lOPx0D95DCqTh4zuYdiGpfg+H7xqGi0CBOitF4fWGdfv2qCYkELVPn\nO/VQ0yK/0dZemhb6yppNQjWeGwVxXDc0z7FUqj2uKvnwHngPJmHT1dIt146MSOAY+VevYYa9icMl\nka0n1drJqFR7fqT/TPePu9Rlq+xbFIUtwARMp6bd44YbLam7w+KPCybkhII+yII6g7eWYDntpBNx\n24EbgWASVve2MYT4i5JbWCVSQKoXNhQOhpHHvNGdlS1kDQLwHfpAh75lC3VGXDlZnV3OTPgkn128\nMKVIs2haxPdWY8pP2wXqy5MV0kb8dvaeoAtBSWcf/GsfaZqhajglz4kSxH/0r6cLlG/sChzb1Bb8\nitpDR6CDTP8jqGHSjRbTQX0y6BhUZhWwspjfken2GqqYITXrgOV4PAm/h3rRwJIFrfOPLCzEx5qS\nkiyk5v2AAxrkGBL9MdZGclGO1SMuFvfltn1zPoTKax1MbQpW0Hs2Si5MFfKCAkKeLuJo6DSvAPlZ\nztYHmnm4qsKlEieqy3AIze6buSIdR/DZNKU1zdZaOcDBxDRd8bB4roHlq2EYa+93jXoL7/5K2Sum\n6eF7XY2e6vL41zCvhdRJMSrXop6N7yXhGbSve+JcCZiWrAx5AOM2U3d8VSSx78T9119lWhljQoZ+\nia6Y4p1HtiKRwjqEt1HbhqyrloixlqWuxwzj67l6oP/P9DTNN2epk15sZ9kKNUGNrwqENGYzfPO4\nQq2NIiKFFOfLx5xWuFo8BYl0AKcL90bEG3YvnT7dzflu+8xQYeR31Xjmw7ufjZqYca0DUw4/c/vs\nDuOabaw/hM+tLxgV0x5kFBHK9MB/JGIcrIo1b0pcgV5OpCnB+uDof2+INND+qzEBDbniVhnD/h4o\naJPoLERJUo7p+Rh4nXzGZIJmHg9sqTvbA60aBQBpODcRCEr4XZsxSFva+UBZO+TI1V3lZBIkcp5D\nrpIIH5tROxc7g6L1wZOJNCicck2RnOdSLNwWFm8fXKrX51IjcOKfnzJ/BGigJLCf4NyQAi6zdqdG\nGNlsze9guyu6VgVlNgu0zJNQ/6FprwZpPrsUa6ilJXuYYRxas7KxXk7BRHHKT4bgFqUMDx7d/mxH\nzcZG9xdfrPPI3MkALGiXhIqgVyfVWA9+O7UvieBj14vuufpbxqXWEu82wEsZpeafyXTLioYdmyte\n5TqUNixrDHULifNOcptXtg9Q3+FFwriB2U0Ho1L1QqkpLBRVYkV3AXhw44Lb4zydjJzOs2nqfA+T\nupM0fKVRfQ91xUyHqrAkhGwwRzaDTff0jXiNmpUPtoUULmovVOR4zVwOcgmMZYpMOkHfyehjF2S3\nMWx+k3j9xHjK1g9DtiUc7zAeeWxdma9x+dR867wQU7O5qydWLJt4n3vWp3ZdeW66clYmBWQz9uok\nKhwmvn5ME7OkL+YTDquTae2acyFkyOw9mQJdQWTS4fj/PJId2eNgHsXIBqgJS1kpr+uecSbNlHiN\nR1QsRgewhQuH9pVAMKXpZ9JkMJizAyc5NLgYwDZ1hATjiOQtKAmYl4+ICTOMYKhUctfXFiV0peb2\n3nmR33ujZ0l8P3l6tjTQkyNQsC6jnUqEnFJVjjrMVKGySTPWF8HHmKDH4mDgZrmryjvM3ssMcOeo\nsa6tJQgilhsB9KP8OAUAhBdLFXPoUY0UzmMt3M6ZesUyMWUGTbvv4Wc/frxCJ4AWYxtiF90Y2h9B\nnkZ9sPxau3vIoCZKp4/ikcyIL5/AHV06ohcglzu/2DVCpL4dOnOmsc7ztApcRSzQaJDTwXpXlThO\nW0dgIvf+c5dzuxVRUsCQbhr1ax9qGYig2zbtrZTcPBUbljMM9KFVgFqyBKd+6M+y+BIhAc6zKaA/\nsZKmBxl4BTGieAZxpF+hyRcksv+CvyVPoRb2dZy0Z+ryB9X4YrauIsxt+I40qtRKHaB+mu5fEBCf\ns7unbuKP+hwPR4ZckQkTytUDPo0crwwXHhoKpbkx/UtRFnZws0/CQMI2uE7FKfuFSIY0kE5qd7nH\njR7h5lp45V4zSKSkdfWqBXke8Bi6mRkIxyNfgCDyNwFC5328TjRQ2vMl3AbrEYkG3CYedmNcbXT7\nhRM/MAdH41/1+NTQN+a6ezu5IW3VALwfrwL3c8EVlcKj8d2bDpopo57U7msKSLypalyPLZP/8e89\nE39PdwYDEX6A4GR9kEId1zZk0TbVQokKATEEYw3kdZroJgNT6b6ExlD+KydETiSWTjhJnbEhTpHu\nRW5edGXBZoVY8c6Mshdk+M5f62Iie6OCC5dqwwv5auACOb6y6REw/7n6/4efTuZ/+apm/P0ctgzD\n/BrZGHUbszQCqfOfsC/xEFl5Yx7IaEjcAISlZ5u+2JAlfMBuOhzr+WkhYHTprsA+GEGElqS+dCbb\nUoLHGJJS/ojVDs5H4QcigeKZyw2CTbpayXYWz8M5HA+bwCmqBDqK8Rje4MdKKaXr+qkecMcV1yO4\nPXT9rOCvFzlGZNa3wSTNaxqMgX66GveGLTWu3iB6y3Ugx2Mjts7PRBwv2JrRVHYyA7iOQ0mt389g\nryLwnI9P1rx060KH+IonYqaCGnahCzMkhI7gq8jUSKWXhZzf9X5XuzF0a2HPqjYhPeTo/TepkJSH\nB1tZnqPB8RXaD1UlblEwqQJ5F8UtRZ58RUY8PL5qBOliTPBHjrinsuETX4C9f6hfaP8pufupZFKT\nhTU7xAltupPQMzNWNDRXqdn6HA9sxkgdHtssl2BwQ/5YEzHR+wDuEecQS3NOrthXORx6aHKVDdY5\nvlYgmuhxWD6e1LB7jumzcOZ//Q26LCYGB8Clex9pj766aQJGPs5HuPYC5Ur6eDgbN4cKpQlwiubx\nlzOp7PKmBEwZ5miV6DZ96qkcoDnf/a/8SnOUdnLjHeNF6ZozyBLGnCGQkgjL+fjHzk2uix3D8wOz\nnycE491Drn+kEDfhvSPWIVKAJg2UyDC67kSST3DjVXJYV5vbkxjc9xQ44aI8jEAJRK97Drc0eMMz\nmopbyqtb+UzV0NGq5Aaaog9TsF3AMHmT2VqQNqn4cRBCBgmXpA7WwmWf4jcUBx5tiIKL8xYsvXXt\nco60qDtCKsv6EPE2jtfZDDDfAKBe5WDsNUTiQmEKYfBTO5OBtTYUZ5iUhEQo7Ck+mvuqpzRjHoUB\n5dv/fP4yoTPEo0V/ganaF4iP+Nk2zbgrQIZ4+wIb9iEnJzbWvFesFqWO1f8AOECf63bkyUiAWKEB\nzjSgjUwOr8cxXWsY9xKLmPyppusCo741DWcjazZ1GIaq8yxadALSRCk79EKyCwAlG2hDTAyjTjvM\n8ULcy99s0WF65bmuUjUenWAEzOR03FaskzgdHBAmX9yiNEcEFXmsl7Hwh+81k/NSrJxWTwaPbojS\nGVvqbhiurBTaQ4n0avvc0Qbz1WUMneHLIt8/6thxFzrLRfYtHJmtSd7YkXpTBJDshOvPmNYZ3XTY\nb3D1jULeyTWu9C66SnpZuLcEfeu7fxG2l9ZfdxsjeTsTFF2eK1gPnDwLDOloXi3rzaWnn2DiYxJ5\nFtd8sHxrXaDYaMMezpoY6S9gEeQXi8y77IKxXe/bzxkz5kCE7MBmm3TTRaX76avUFxWebc/5w6xh\nzueEbbYcBE9BuYKWR/jO0jk8kSXSlv8hxljvKoT3xgX1g19r6fJVNxgpFWYw5MhzB3baJ1N9YcQg\nLa6j57l0zNH2EtjvFiMirLxY64q31PxCN4UekvbCh9i5I4V0SfXriIRAuUsu1CdJR9WVMpdptNDj\nolr1M1QlcrXPoH1yq8XlLD1ohBIU0tlgRlX7g3WDvrnp7tIYf1tmexoO0WuDQDPOhRqEZPX2jbM1\nDmrGJOYcTZIecoHJtcd7fkgKVmk882bl2E+DJWUf7a1mxWfAoqfNXhT0JCs7kFuqgXHANqpSOpXf\nWSkkzZVdImzPCp3ErHWaT2IcctwZzNpL6S5EYsxCaQldDfaEiPNmLrbdzotdQ6wJLNGZmOMsqLSq\nCD1TQp2g5izcdC2dvimBX8c+0S86po2qot65eZNeACF1VQGG8jGPeaSU6OzTgQeLQfEt7d+Lr5Nz\nhOqxaOvq3k/VgrrB2GBUc9GHhleIQ88Z4Gfl24epIwd4BLHVrQIGT6A4b6tpgUpP/expGK+iLj3K\nyRy98mssBgblR8ek3HYAyM27A/8Nl/1cVfoZ99X9dBKnEH1HG6muYxcg7lXW8ppZrApjDz3hx050\nAAuQRyvPXFN4U9M3hTa74XH8Pvp7WQaf9zfMcRp5S/kPEpYzVfx7OFjVkBYkBNUuU/6vbvViGxIe\n4W8GxynCWJCDXT2w412kn4YseXUdCvwAditnuwZ35LkQf/LL6QxumflnsKnaOEHs8MgzobzCGWmH\nqO8Xv7iNsRmlLpfybxOp0X4dnc3u5tBRhiw3IYyTyjr9p7689AOHyhG7TIxZlNIwIwry++E0jqhY\noN7B/QHhRk1iswwAMDafF6V7CzNwl14Cz1sz9KinqaElkgBJYLkTtgI/grEHeDhoBIKmnEflxFV/\ndypGEyW82V3JuW+T149skzf+QEIwWrEXTNVm0837+1K5rmLKkK/iARW7L3Pp08j0CzoI6rCBcqU4\njtHqgd6M+qYyU7E7jn56htwDoC3erg0CNtdLFLnhxiQN/OqdP7LtwlO/mv8F4pEhlUjmjLHeWFvG\neBBWlQAKprbOWyppNrIW4bXXjQrRLPczOR6Tg9y8jPJB6XK7uW32Cc50EGsRqQpNKybMdwPtNYVE\nQmrgi0yuWT6IWPC7SvT6p2nNkeO1Sk9JWZEi7bqZLxrf/cS771zrbSysEM6f256G5EqghCyf2mfb\nvZViMvuntkDF4DIJqhGVV3CMo78JEkaswrdF3cL9AF2B96v2/+B/XKIvNV305DBmeRw/kPU67QP2\nwjk9VVkiSmdX22mw4il2VbirTZuy5k9xtZ5LNyLGG5i5bfQ1a+K2G1n5Fy0N0XLvRUGDE0qjR+0G\nzsFtAV28p6UTDVpr4/HXWr8EgcHX6olpJ+83GLBpwmH2o1VboT9sPL3XqP+lleCLF28fiOLyk5NB\n4VYfVGEqskWxXPQg8TVqhkYlCZy+1sv7/wwQOKKtFRPCbQmYXwP8SRkqW/MSNao5BhKIr+RTk0x+\nS77ZoUTB4ljXQR9Skh2gWSEpbt3YcvIW/vt6xAg/FeEgAVISjymW1sIAcWzZE7MR+5cPmNWgjWAh\n2fXz2rgMMJBPd5LGkrJhhgTWM1CRAT8jnHOU82H/dAiF7uyAlfkPgrSJTMQ9OuUp6lYC+pIOnfBr\nPbwQ31pTPwnfa+6rsiyEbiI1uU82hP1VlcqnM7yDE6pC0PYwcKxj2+xmi5vfJmBCgDE4QHcNpVft\nxdSIhejaUqDIoP4kn3TURP56+TIsYcAXNEqFnqg/P1tCWmqyTkuj2j3JSN4d24uxQQsgSG0wsVxy\nVAXlwWO8tg6jdUa+4ZQdQphPeTnsysXI4LoZsahz7M4lCJjuUj3zjqAkOC2wG0Q5RTLAztgFqcQ0\nv+7PUG1nXSp2AdpxiFEa2W93PMDOEynQgPtDkL28S/0TifCzyJq/A4fM5hyYkrQHvkE3IyiGpDe6\nZChOkSFvXs2WJOQ9pYmTbnEAmlQrSzJM+6ka9hN+438zNfcC4/zUhU/UzeyV8oSog2TFKd8gUHG6\ncMjXeKoHfsbjJJWixF7QOxsMScctRXaqjU17gQe5H1IW41IB64ojvjdJXSc/UwjEpjdoxv5AYx3t\n882j/JT/m5xm1LRt9SWIFDZdrO+s8qXEQhDWYsVPGGG07RwD3IJv6wgKVqZ/dBvOHWLTxVz8f191\nwn0DGU1EbRj+zSlCcuGgQdHWMLRw+BsLyXmyJTtFlqhHGqZKE/TkrOkQQa540LQbewKkBCOJxtMA\nDDEAzhbyQCggwE0Ci9FsgDWvabn6iMOSBnz5v9w2O/UdtLdVhhwhjL3Ny7Kn7x0oIojuDFmkUCBT\nHH07qAwn7COk/sSSiCXxj0sDxMyVE1M88SHscXr9LOybT+xv+8NbUn318A+IiB8RyU3EdmWZhGce\nDigop7E7iBY4exCvrJVLlVHBo4trExGR9B06jnMDzdqUeYLGerwxtz2bT0CrZpQi/fTN35yRGi/3\njntLtLMuxlRlxeFyFLsuUN6W1ccA8sUhcol06OaehaD5Xpjv7crhN6yi34wyOAP5N4bFaxK6SQNR\n6fmo9SFiDy/NSk48u9hlWdbQrhO5n/0yRPSvoQGOJfw5Hm3z6lCoUOJ5P29ubGWxmGgGo9sBltFV\nJMbsyR+BN/ezeBjlgB0Tm3qmmefhO46Mq0vLKtQrEphsrbGKo1hCmjmGODxvBF/jSZlSqlhK5S02\ndZbo9mwmXI9f3hyT7tr+rR3VlcSsiZMK4cl2tRfV25gqWj65BcSEVAOtB6wrGrQ5mZyob6Xgo6Te\nqnKLxEy/a6fNFqjBkqOzh50J+RWLLv284to5uJydwOWZr5Hjh7duBfJZ58FNZEvGmftn+HpWFcYE\nS1YeffmDFjodwN2ESM3AO9nQw51637CZMCQkLt7vVNnnaUQSona/LsL2EYzboLB2+dYt4rMjqbh1\nymELapYeBTXb4n2ho+9CvJNwUeeM46918OH/hKpZtbR1Xz1vLIQSgcsDL+ZdyK/nxKQuMl0LgceY\nNpeH46A61XsjFSxW4IWTXqa09VhwyJ4bA0QrR8j6nIhVUjkjtoFoM0Ec35JagyRuHNg1XZJarmx4\nUU4AbfOEM/0R0bLi41NdZHFYoIX/dklKJgrM6bCoJl13jca00QrOgKfhhSgi0RRPK+wF3BPmAc5A\nItYRVP6CzN6iOSieJ6g3Oeykvb0n5Yb6rV/rj9DUv/+945hLSqpDGiyiaDKdq5LmNo3tZnqmVWDT\n6XFv7lmIOTMhiAw3DQt/g2SC40dPSwLrLmkjn/JZflIRkZ9v188WGn/AJUYOsEuvGKT0/LyPThG2\nIYMzDoE8BGAZAIxCERWU7wTrSU75d6V4jeG/i4NqIOnw/yS27HOxImf5IOhMtAR3A7jdP635C4+b\nARMmkNppu0A3h+QN+x+kjWl8gQxt7aOTOWyAuuSgzIyz9XfdZoV8/JSSnO12wjOuHVM5yWk9mbmX\njiWelU1ToSoH7aofsyoGDMBsMou0EYliSJsP62yLgQd8nl8eDOB19QsOJuieroe27U/gQeJ9pP4O\nQInGOKz73iDhGkW1srOZ9H47qUdhuJms6rcWoIYeCcxLz0IrCvdzUP9+aLq4YKIE0T7qv8m9NUs/\nUCshHedRBTWETl8CQhvGleuodNDZWhyQk90idN+0D/2PRQomnYnumwyn/rcZNSybs6c9NtG6IQ7P\ncaVArqK2W8qv/vyFthvCPQ13jPdOrVs/qWZdB6Np1//UDyXQ17uRsWR4r9G+ZUWEAB2gUI+3agSa\nBgndFuY5rUwCll9amFLEM+3L+aUdaxYwQTW23R4eaNgB8oYbm8CZQbVpCHejlmPl8hC5+we2PF0w\nnCRSkRzkXHtTmX2gaBeMkyDocgBF4QgATW0u8tmSSIF2eQLD0kVEQGJKoZI22F/QyMBGK0JnO+0+\noLO0s6VOWOK/2UOX4a7NV27IUAQa7xOvoOL5AOYjO10+TFUrQLVi4tHMOwQSR1TZKc/WdX4HV72N\nCFEuVMjhkTUXaDKdko+VZdbX96HTHyqh6EWzGlX2r1O5j9QFfNx4tGradyDbp2y909d0eB77DShG\n6Zdqz5p93ZDAysXEdixNAIN+6mFa2QOZUMfqNCzu73V3HOcy0tmazi0EPNSLTbC6s9omEORt+egC\nCmiVv1rcf/rew+MWykBUuMeoJBXEDD8tmCr0fiemP3UYyxJtn2fDKmzTNri8aOF1h8QU70aXqfmD\nsJuoiXZPB7lo6sv2I2ISw6SNdIfFwC/UHXblSIrj1ZwwxoyxTICcFZdeW8dn7SrYCpzDG/2wZGZl\nciUGqa6e2aihPSrUXpY0VwVdNTvUDS04q6POLN7Ue4BpbR0heKMVPkZi1rGq2/+eeZot11/ljCWa\nbGKl7nBvyk7KQ+Pov2BMNgOJdLK8Hd1ZaPzJBG2KM4L3M3qnwS2Tf1OKNXs8pHVJwGDmY8JCOQBL\n+VJIGqwCo4s2pFz68fIULK0DMGhiISGMKO/a4jHh+ZJuZjkB1fAUKrtVqN8kLT1ZXLqLdQsOyjDX\n5i34qzEKCo4X6c3hk0HjJJYnDi9hS7It8kPr39Bf9vCPTVB7OLqRiNSDGUGj/hi2B46V5e3V4ELS\nvcSo8Qwleb1rn0eNoDJdJrodGlwywYOI7qvJ9bCGb7ud0y8Q0VSXdLipUCxdsiAVcaOHS9FPKYWM\nBhV2lWBDhUz3grqiAxF52abpyTX+1B0bbYQqUmaFloTnNhxqo3pTZFaV8t6bvAgsYO1ntelZ/Cfn\nUggFVAE8wg0pgnhRA2IvwhUtr0xsku3QZj70BsZYpkUo1jMU2aGaLsSy9+u5PRlg77D0wgm4nTSj\n5pK3s4nXNpfFc9Kuy/zWh7hnsUQxhM1wN1+W6mbXkgFYEmUMb7qXDIEXr+Tcp4oMqFpV64bsruev\nsjflkziJvQY0b1USsXO/3AZMEcls3JduxxXBUoejvkRfr8+8+TDYptCEOtyvMNveumIOWmOaEbyg\nhipQN7ncBF3GHFaCWq/632+mMP6zTe7Zjy36+w4+9Dwpqc5+Zxn2dbhL5a8hQV+l8ddozAfNHDOT\nK4IG2l6U3ZXl+OBnz1HvJ9rdHvsvyZxcyHsxqSpfKa+EPoo0+LLG4tGHzGleb5n+epWI4PwnQUi/\nNKZThaNrPZmSHyRA5XI/G9EKE2M8WlT3cTFMZQdmuKRjuGa7eI0rT9z5kPNqOr3zmckXjrSTv8hJ\nbq+X8DBDamMomoaBKHv9ol/QWlElNF/zkZD+9MzO/kebOIetU0PYAxGnCrhfGaODW2xtMu7Jmquz\na2LS3y3zll4rT3xuJ7iJCdxxyw3Us5OAn2r04aUhMDhbR0VEMZdb+MN1w2XLoE3zS5b3csufr1O5\noA3QXYIlXNuZPlJZAlajR82AbXii8Q8lxeKPWnDMOuZunF27JkN0izIHSgTPHuAd2U9YFHntiD+f\nICM1/z4MfHwSppKp6jywiKKZlsFGO1g2E8mC85IiSxmwy0ZBkWm32H+iKd+WWzt7AwMFJugWq9/l\n/vR6GJhiyxTxnkigjhIVZos6Q0W1RgDwjXUa+pJ/7GfVyfl3+xsD0Z3r+ZfcDL6N3ZsBtCOzCO8R\nfQbIiEJ+dqUjgT6wl4ItaWttcO5jMKZ6LXg6EPhMAVOZo5LD2tFN6V79hrGorhNZ+aV1a+hCu0YP\n3jLqL9Rsime+Eo8U1B26abhKZ5vlPygaFBXHwZXelKE/OV7YHWZbtXMeoYoqfYNtCZm8zeIrbZlq\nWvBN/sH6UoD/fP3b0WkrYWnl7BeVukq3/md3wsvv6lzJXy3Uqwznoq9TNRWZNg/JDvDrXUMESCHl\nqHa3w+/eUAMN6/h9hVXaW600NZ+k36DQ0lXQgRqAdM0Ks6KJ+5r86rhbtKkprFSBxhP1eSEYc9JV\nBonyi/DM0Znue/ux6RZy2ecoVYPQHA3nxOatTKg31NgmUYF4nWI0mx/DVAUBSq6N5MobxHvPrRHW\nNu9p4d6VVP86gZe5fOUkmqT+Z6JJi1SWpxB5wiGmWg7lDQbW1UQ+OESmOvMnm5SyVjQ+3irEiYWo\ncg7fjJ2ox0EcuGjVDFNjufpoQxErTdYmLptSHBNooKKrMswNud2oBN2tf8Q80fg2u0gk0tEkEzMJ\nVeS1VJmt+I2Dcf7kLLdMr1cJ+RqHca5kEVeMQGafzH3AuO+ui9PxkcIFMu+JI8oGSslgVLVdOpqX\nMllTm8CB7+U80sDBYjQO5SoXTLvoiwHaAmv1WhewQEXb22PRjtFGOJbPeWwd4EyXm/Yc6O8FuTlT\nXxlWja3RhQYiAVB/Nq94RhlX8lLhlR40vRF/djAl2Af2E+j29zip16FNxv9tMNEpeUFwlEA4wTjn\nmD+/xsVQH8S1tfLCgdzcE5gSyp9ld/tSegO5QcO15qE3MVd650JkZF+u4kPmyIxUKqTK/37UNrzM\ncxH16pvuTSRzKgElVevgSGN36z1QYO0K7Sj+9C2nJqV0KAN5hEeMGKmL+tq9lWGpIfVIANOUa3tQ\nfIhjfRHd13w2LC812WfzKT3187ughEGi7uA3qHG4ZR6KV9DDnIkXGD4Kor/xI47QjdX2YTK7ZyL3\n3BPQaTyjE71BD8jEP2BaLt/gjx6R7FrEacmZG7Fi6VBxtokvJfZzZa5x+nX+zUBzQ8+V8qhjbjd2\nHM/+Dej0j6WH4haArroKlsZ9D4Bs1RuHEStsSYzFzdWfgo/DOGH6lYdMaLcZVHo0bI99hGzoaGeU\nYDtT73g0NMzkO5scFBkOgx+tdsgOiuoyCQOf+I2KL+2bByFlVx2Q4e1iITNoKPz65SnoOXLwEP45\nWzSWO8fvAsN6JfalM/jVT3k6I5SXyhVuo1QDYrJdMJZ1NqVsk45myY53HQSODjwO20uMBdsrFdV+\nQrMIfcusNY6B+ktjjxvqRb6ev2CWrsLACyKlD8l5nNgiV9ybLoqjwmJhnGMvo5buhDNUDq3uqxKR\nNID3sZ8CgO26dEbhXcNZLb6duxi0L5Bp70VzhHxjfhrIeVjSh3kyupbnmRM2PJ7MGTTotpJZa23u\nXnE5z8/TKRR2DAM1C/LrPpTNJbMRWhxJ87l17zSEudi6GTft0iV1bNEpRmaCJiFi+L/a8xerFaJ9\nuUx/mjnNUQVUVMzlnBoMz92YlmWli/os6WxDdTRUHcFvwS7k5EZAWXOpYKUGzTFo8r5fRRANi8hM\nM6h/twoRRch8IIn+4z5amA7CcB6Yga1H1wSLXT4pXvE8lGnpcVF0c3/LMERcPuQb+2U5P0987p57\nxDWf32M49PsatUF4UpTfVfXRRK5dYMVqNv3Cpr2+y4a9EHkGJR2fo7JauucsR2ZLRqIFtRN3oMZn\nOomn9Pgs0nJb8Z1C8Cac4oJaKIn4QlOR2+f+ITW5CnBDwCd2y13fPUFBjY0n69ADT5ZkJc6xdFoR\nl2v2kOkQZNVxONf1p5OKQFQptHw4eaQQqkTD4GNCXLn4c1Nbz+szDozOaHYpiXDeA83CWalj2KzC\nQSAOU1kUTc5rUEHlEgILVrAwMIDqe8PpRCwbAORTPn/N3WiNuVDoKB/bf44LEQcRereHs4pnD7u7\nIK5MgDGzJBBu0id8gagU6HaSxNRXrK0RNwBn5MW8ByqKZo95TNjg896z2w5ORbNzFVykhF5R+byx\n1rgbkjwwhKxd1JJRFpZ6mciAM9wLexN/pssDlFDfcdebU6kneiXUBRNnlbmZg08ck9fl426eowao\naM1dKEng5z9uu+5GiVdouC3Rz4LMJZWxDguh/RTz+F8u0Izz/had00gvZvWQ2Suu9gk2VbbDb4iW\n0zyWH4h9c5rnvTW2e+85tjRLqkFcof6hW0sfzGEywMtBxJBoWPHbewyZi/ZJf21C7+gKCvIwOlVV\nf1IEqzIAJ+Q9qXB2vrzKwB6ABUrLbBvMwLNekoY2hE6TSqt5rxKo31cRDeb1UjMq+DqFtwouk1uk\n/3Ud+rNjMxRQberpnGIxc4YF+e3Gl0XURU2jHw9WXXI4EAtRCEKjrh8ikiHcGfCCRZMc38qtEwq9\ngz30uQdCrAPkA++FtXf78dQ1u0/GghLrKjIs38daE14wR0eZskvq/Dv+5H7u85KwlimW7T2rR75f\n/dNci0sOWxF+MtW/0f+me4bSFFKZLUOaQjcdepVVy8Y3Q4g94cQtVvJU5RA1QeZgY4AfzfPQYte2\nD3ltN6Ohoi0QDtev6zxR0LjdrW1v6r1s2YdwFOpVBtdS8B4IAg9GmfOE8CmKPUBq9NzEgmixILqJ\nYlpYguPkmmwGCWmRNyVlYedd6fmFcuq3dCdM/2rpHJUGJVYHcMaq86AemexOvdkf6460jEdWid4y\n01GhbdHJKX6vu0s1qZnza9S+HwbrSmFGaB5yRkmOs5UXJLB7FTXosq6XL2/SeMETfZ/DTXEHAoSQ\nskT5DJIVBiUS0PME/v6Aro6Gx/abqsOwr+F8aDklfSjISH3IcUS7hfDGq9uKyrTsFCqDlsas4CIC\n+hKV1E3bfcsPdb+VDrKV+lWI25jZCeg8ynsxR8RJEoW6wCUEKjJ23+hR+f5UKappk6Lu/GAqYLag\nM6r3x6WPyESL7FmP/++zuXBNo+i7mlC4j978zckvCktLJ2SGSu0Ll3zzB3fsA0UoG0CcB8pPlKZ2\n7ojfaFzX4cB/x5fj2IyOUqH3brPIF6Q4+EpwwK2thbVnrYomEJOCBY8ojn1wkSYXAQQQ1Sb1JPVu\ny0M6nXwBsqASPXAJ86ZBcSrlzofwMcW4Zo0khp54VtV30P9Z7wgw8qCg8HEROliVx90i5He4X2rw\n8006LGG1n3q4wvF85bXcIKi4gVaoA8I4tkDiqA6xteR9pAg2fg4Vtil1hBRCaGtaH8KETKT5nQ6Q\nhw2e5KfbY+/84ngDBOxiaq6z3B/sO5WNGo9vnWb/BLLG7/bPvIenbU9qswF1LnWWL76nOSitZA0l\ndmJpYDEX9BPcvMKkEp3HXmpw4Gx9bxg5jFYU5QoR8PsPRS7fCvuQmFNtIu7cC+bYwPR6xoLe4exq\nsF5cs786OOUyVlx3g79SvtHwVOYtgUcA3lCwtFUsi7MszsIeFBnagsQXG9DKd0pIQchHfKQIBWqM\nl/arORCAxBQ4MG03S+hiYIei2R+D93Gc+5omAwB48P2uQ6AzlPdzFyshykqMnaoHdt2w4aI+oIUA\nIdTI2DvU5xVLNmD5J5L2A1gtgjrsgLtrdTnhBHqRiY2+RXkBHvV7TJtJwpKpCv/TTUpuxpgras3H\nFwhOgl4sWl6QLmQyM+P/CMUaryZRjyuQDsASrjTvf2WKd5oydo05sionU7zs0Hy+aMz4y09ixM7G\nauMaHKqB1JD6OgnHeLX+SJqmusQpKpAKc8J2yuCrkg7/ZzwAVNd7K6SRN4V57hlPIFxlQ6aBWF+U\nXFvpgns4pSFKL42+AekiXpMMvOiyk5aT2Z9gJlg7tWTMLFlRmU3LlGx9/32Q4Xp5CitlXG7hF4zU\nICetxESgE3R4/Cf1X1Qm97v4K+kD/3ecek6y3KV+LaPLu3EwVP2hIT3FlOUJX3uGKI1Utk+zweKU\nUJDbovc8RPX/Q03bxCebFugxpWnp+LJKYoOfGaUET4b8D2OGWWHCGYYZAQGRc6P7oPupgAAdjmPs\n8TGLJFV2e6ZLRSqUtqUOdUdxsCxIAHN5YauwLDqRexVp6JTy6JdrZ72Lp8cAcDeZFJ3XwNl42LL/\nJad0RSgvObQ3wkJCCO74Stghumdkjzh02BppR31cN2ukfwuadKF73jPKzdCxpmtvwMaFScVHonLt\n/B/wnw3kRbn4KcnzrSvzzvMd1uTLOOuqLY6RaR5vwIhxoP3PEVkN3HCq89e0Wdw75yQWfZy8MC7v\n8MPwaUNtoN6O7BnXBNU6UrEsfLtNn9zAihxG6s9B96yLD7cTL70O0QW03ED7Jyk98T4gGn+RayF5\nHh903tgu8D/vB2pYBHbf+sr8iSm257xVVOcdTVqO3ESa9NTttrUHgmCYoDC/BohYh9b25ZiXO8en\nY+A7yNCuIxZeoF1Pzc8hBcgiorPdS6eSIrl22rNq3+VcN0e0XzZ1hArrLwKu7HYXaTDGIwur8Bwa\n/Qn9qRz9cj8ZNbXOGG+aqgRNxYPKdzDgtGw4pZSdvpBmwcdFrdki7tMxZjYKK2C29+6orZZFXfU/\ngfKNz4ZgiTM2PHPNfQCZ+4i9ibiiq3EQXFWC7v8z/cD3zElKWazRDoUtu9yKNDPj7WAt0QnWsddu\nzUq5g2VCfVbxSydLgZkw/1Ml8C/xi4qLGYpYsGs39v7wvOlvliZ2fiYyeq+A6p3RHKZFC2gSwsCv\nBPw8csCm/mSKMDvycpaEAfEl7K7N4XwEg2+vicRywIaQuJuBKZ9oQ301ysoXtxg3WCuEFyMYFH4T\naZKfZQ2JmjpTaaVZ7nb8rzgphn59GZgeoV3ykgfXP13z7zKo0kZioBLNOgOi9Sv6IO/lLNh1hP8Z\nFOP0sJ59AQD1pBCoBrFBBCbxUeUzWN2oiIFVfeRODcnFMeEPs2cDqAY4/S1WeqaE3wCLaZmz7sk8\n2Lyk92hYTS6c80t1WSeZlfXmhqJiI7TUav9WYFYUk4O0qDHIbnB6T9BwBy853XSd0YbUgo0JEek2\nARO7a6U6wGxB/YTp0TnWv5EUwV0CBrSwx2HOarRGLB4LvaJ77RwnKbVk2uy7kPZF4EhVBBHjHs5y\n5ZLr2kO0qHfwWxFQ0IsMAyRD4t+2aI/hBGubp9jKXlvcNUmopJcubWsSkR/1ZhcC+EuuLsdmTrJG\npW8wP8LSwXdqUc4QSCof3x6F63BqRiO8JUm981AHIm6sbIMmnLw3aIcDSrmOHXJQUP0pnOCqMovw\nVZilbM5hgAuY67hAgZ0imQ7s4RYMm8RNXjueo41/aHJDftt3WZ7elvoBtTrCmGYZjpcgUpEmnfip\nMBOl/757ptX5LMuRJPesb0FCQWGERLKLe1vI2O2Ri36oImP00Bk3TqH7sFiMk8FImHKUL0AjC2Nk\nDg/fikIyDsrjOjLGXxZKh7yng7gskFCxm0G/2q+iShvMRjH2VKARZn90Ol3yhjJgb+S7jg7q/jkr\nrUl4w+4jnUhzJIuL1XPYm61Ec0UFYhK3H+t9rVNEtj3+i8D/7FCoI6B9iGcsHtdrAxq2n9JxO0FQ\nNoZFin4PRgfiD/Gi+XyrWD2MryqicfkQFXZxLktsicU60QlMvuPf6UHzL8u55ki0xm+4zuvsqmNI\nBQlJ8gzpk0DMMcdIHsNje1+xQvTSC2hxTjzORL2mcJHkkcoGEsfUxMtBBNN54cEU2Gk1bmUpoeyW\notxUBfGMhQLMAZOs5nqgQa1XkrGH+M6oGGfr7kiGfGrys5t1It4lJ2GC0v9REjwCG4h2uxBEy6sa\nGBcLaXzdDbuRkMdTzgubZsBzSao4rUs/3Oh7mH4S27/J/hCmxX5gN5bw68uMN0FHYKubwJQzt9Bg\nincHtXNK3vLsShRwXW9RtFudRMsp9PkaW7It+MM7se/oOdGGrFh+LsEX3T8mV1JsPHvIk6oxfbxa\nYCtvo/APpvX0NFto5KZfV/G8OlFF+bhnG+5n3mmnrqgh1TWiJEzY+p3IUCau3oZbm+tOA/YS1VZk\n+obZGjfdEE/N7yXQJBTV16q494TIiSKS219L8dfj8aaPTJhWMbdHJwkio7kydnSwm2cIDTopOYWE\nTZiO5x47SFeljfKKVdDX5thtRL94lNhTEWZePxyAV6P2UvgOTPJogoz91MBkmluvFo/9jlLfE9B1\nECNhEakWFzlrlDbREftfHIJasSjuRSVZW8uoNLutH01TG3PzCaE4QWBheC4/YEAC/5/ZmeY7OXZc\nmucS50ywKQrYPGbKjrt7QiNiEV5Ox4L0MxdbfP4TheZKPlUjytowQVn7nIhNWWcnUiKZSV4alZ9o\nVOW8yyc4iES26whtJPg0GCCp8aBYCV5depNHyFm8vrb9q9Q9EpewaJb/zkDXbGaxROHVPjmrLcEH\nkOnObCUpca3uQ/EC0OlvHdFP1Vp59jVP08+mFhKrwAkImWeqKR6yPjKlDZW8k8Ftuoq52ie5FCy6\nordEUxZx36TN+TCDsSxSJ3lhLLLVVuzBuIzqEuhprgnnydV2HUe7CA40RuuruwAIYkaExvML8hLp\nV5cINcBA3v4mfj/o6udXIC9pH/ju08K1xQr7shh+aEjqEsB4nzfUI3z8faF8pzte0Dcw/w+eOoi1\n/rA9od8RZp2OVzlvzUOe+JtYEaEi5gtEs+7vNkbj3X517OnlwtW77nPoTDNwcY2wBw5AVTRihdT3\nun3IAgsvvSQjt91hUIcan9OsIJRtkSP0f8xNLxUTF0Ac3jmFfEM35of7IqQoQAnOI66XMLAKR8XS\n7lg+EETN47BDaAn91oCAYb/kl2vGmSBScXGdCTNr/3/iT/0qDluJaEB1oB2xWKPugm0oG/fj/UzO\nJCeiKvdSw86t66i5LjJ8PhrutyUjF+/9rQpsb4DisVQMWR4gZy6iqxNVbfje/FpppsWYtWSj/bls\n/gitTFIUoCoOj0sKlBAa4IFsZpt6zMIds6e1o2s9IiDPq5Fz/90RYDkvAw14APEcaynppVPbrGTF\nDj7p27ceKijMiroctyfFJd8qk4Ga498IZVno2oX3HJR2krX/AowDPawtRzd+7L2isAaO8qv30Qnf\nEtOWyt7rNEr+8bbx1lWz9qsH3OWCGKPgTuodMPIPIt2pRSRd7tJrJAVagFoPkh/+3m+pbviOqRny\ns5dC2Hb9b2N2hac7cQZpUzgLkBk5zJ4zCjNUC21T2Svtvnqps1OEQowb7QXRZ0XVWzuk3RAJZiNg\n62QcsZv5s2gyFdvPE6vQTL1yO2TZnKJHOI16tflAdhjp4UzIRu4d+7GUtRu+P5QcLbh7PevyBCUh\neI6FSWyyjemmoRGqkmETpth+JG0l+ZOIQ1A26n9DGinD0HY0Ogcv59Cl2lwIvq8uCxlFTnJhDIF3\nDVCNcGfiGgWDLnM4r8as7R92eW/VUrggBwBy5mGaiaOZla3jD+29sNGkWLhLeZ/cwJsfO4PttzRC\nTDcxSYREF7L65RJMv01K7eY217hkvYaFKbnPUQms3MprYoBK1GbIgRJCpJAZHZ0SyFgvRMi7vDUU\nCPxkv7EagulDt2PxiTWifk3eNZW+nl2Gv7IZmwy+yd+szIyy+w+qHN1maK0QP8FJjJcTBIV5Fj/u\nrSVBBDSImv4y7AsuXJfJaSm9ZMxLn4YwBeRKOTLmLCORjMwrJgRFNzrQGjcCf8YO1mnrqG5ZTspP\nXEwRVUCmaiC3XboTj8Jxs+dPoCpp9jFX95BP58Cdp5EsNL+6Yk44QLbLNmCAT1e7dME+eAgAzVTy\nkTG1dGUaon4muP78mjkgXPAcSXWTpoVzLlaovwRGna/v8nthUEo2Ng43dxRRxmUIC6KJH4qrAvOy\nHpJ0Nlx0kzQ+Ea66yA3qfmAj5v5BWIf9yJKEPRApCbi3IBTY0+9gWBH4t+8eMfP16ilIfbvrqvSm\nW21WRTI/IQyE8cZ2NSDg/fOCqVaC24RRer6Nj81m/A+LIFGHQKGwVDNJv4L2r0YyQMVRhm6qEIIK\n7LSJu2O1wAKK/+ucRRAaHzUY2NJh7pdvPk1s0i6p4gaa3IwwPMoUK9MK/1vpt74y4U0f6h3mlXaP\neD/o+VllRlDNuG6VMsrf60KNaeVHp3jK/yw67RDRlD5vIIVMUMJqdAL+6KlBjz2MenyMo1xklHUX\n6Iit2VsMdc4Q9xYSujEnpIc9UzKryhg3KRwRTcA4zwdZtgSX4W6TPutjpCoqH8fqh6CoFXN4lwtV\nBJo94GM/WyqYhzgH4kyEYvFIZGpQVCxYnnPhl4xyEVoo07CIS6VGB2WE+sDLZ/mUC1Mq9ps/LKbd\nIWwwS/it2z7l8opzBXH5USRc8YDqinYORaq1NiqgU3z0NTR9AfNhncq0QWSrn6rd9CXFs6xoo7gb\nVjavZx4R7LBmINm7XzYdl36BYA0DsKd6H9j12ZDdwya6d0rTIUiv5rFH6n4A89+Lzm8TTn+QsO4j\n9lGbCBREWXpnJIVR/cWQtE3rFMwa8Wc3YEF8Cfda1dZ6famOfQyJA1EpWks+bUTHujqkudh2YMtS\n0DkY2CjdzJEudHISX3PLJLEDvY1rWRpfHRC2BVdTy9a3JYLNqBJnKdN0p1Hp4nbKR0C77HXAHBxw\nQezMSguKlNgd+wHqo6Dv5IhW4LT4gTgN0wjEqqcx/6fyA9ibOeilvkQ9x/vU0S5TM3ddwOsM93Fv\nmb2OgG9L9JIm1HkuEPC1CptR2xtE2GsAM5P8xtfJo9Yk3en2/0ycRk0PMpuo8y+rAJpwxryHCIJ4\nUTf3FTatsg1ePefwMkPmzeIwOIESoc34u+qae+PJamv8wqJ0cudOj1IKLDmZEB592DI6UuJiPvK1\nFXd21+sXWe0w9cAHePxIZu684O6pBvyMy7127I4U4uUEHg4db1LZ++J+BjYZoWDKu4A9Aj9GGfG2\n8Y2njeWmDGMzi7Y/KTLvmOc8oWkhFi1G/SolFgbRGjIfpDpi7SCyPylT3fgiNq776/RKHkj/c6ni\nG90jXDy7OT8gF7LDekF+aDwVKXPY9nfTDJUoNPF64S4++JW2mb4Cz5jzvm7JK2uDsJh799b/+E3W\nWx1WPvDERt0pZymTfoyCxxNoDjUlRP779mviMmR0CIAkYZtVbOVDMS3RyL2aLzLPkM0csl1LCi4j\nt8MTe2LLeu8P0hzwb1W66cTDurHx/7sh7wT8WAaf8XvxqqkxBiHn3bzCTl6mQp1Y2zuFh8C7TCiM\nXd8WvfNwmzrpQSD8JNac5ItV/iwHeLXRwegpwcO/HmVZLJlCjSg/0sK7/Qyy3UaFxRNeMJjcq3Io\niCCPpJO1WFxYvSg10qfGmiEAxWU6FuS3kwKCtHAGvokY4qxipv1VmvABdpdhkliFMWWwn+OUhbrY\n4pZx91MyYn1/1xu4mTh9h+NQKjc4S629rpPQQSJtAXEn5JzJ0yVGOC6DriZrB2jXLehzS+j1xum8\nHqUu25odjyR4jEEdIZ2Q6uyWVDWWsysPV39Pg4DuvKXwO5Ej0iL+nGnnROzEERMx5+SBmYJvlV7R\n7CBVtQQH7Ew8wp2NUXjt8mJxSsQix+xfwmZK17962r1XewT6WRzrVtKOifNI9pbrX8+/yrQ74Sk7\n/j3NQY792wZ//oz9B5ep4rWgEcu9SheVUrN96TMts/oFmkgtxdidnHlrTIx9aBVSxqrqBSxbxqzN\n6nuaZse//3AmZq7QIhzefPkAxKfh0mgOUawN503NLXXyAyfy2XpEqkpSJMrx7cUbQN+fdizcmsdc\nVIoLCR21X9imiCCX237WUxmAD+ZgUe0TqQ3tI9uNoywfgzUWHEOjstQVHK31qfWbLeSAH67Jqiwp\nisvIv7ucDlVT4+sxk0VC386pB3upFyWosSomljhUsCmwXdQHduk929d7++MS7sXeFgjvrlS96zJh\n0VBJwS7u46ISAZwMY2p2DlQIFBh4+JwIA+eInZj7VIydgwVKxIu4S8ZZF7HDgDBCMkqamWcg0VZo\ntNQvoI9tljO05jzw+NOgWURj2iDSZN6pYthUTbbhDR8FG+S6DrRk5MZK1B5ajqSoxvmHGaI360+A\nNoMfMLJA5a/D0OzTLJ8KiaJnlw9TKdvQVSxW1hF98uT/y14L2padkrO8bAjZRNvr+3WcdHoTW1FU\n6mpsbzQ7MhNWkiM+jGZJxSDC8VzHRGDcZRPqqf+VRWQP5cfJi3wrakhqe16WMeqQsZeLLp3ZxwF4\nnHfAVE2lIlucVyauPgP3kh/6rpqgYlJvAkarfp7qx8EClHr8xFsqTpdRXJbgxD1q1/kMLdt40x6o\nttf9GjbdWORXYbV5tibEvDf24b/kiBkdtVSHZHg2GpD8prK1/BdUE8vfwvDeSJKu8YFE8B2D1Irx\nQ90cZJaUpAj4QW6hM5aVDoXGeQQ3cCbq/oAAJsNRbZsb8FNHsH+zYWxdQ4xCsA9bPcX4AHbD6ZHq\nO/e8ypmdNXpiq0IhsRlxN95bv7i+bw4RbZq3S5yQ2+auIl/f1sP7CrpEmrFN7pLhqgx6ZAyD1rGj\nBHTrWo11EfN+RXm/9R4XGZqIOAa8rv/XypHYpmepG3VjEfXqF6MEMIZXYSdMCRyLM8TYb/Q987+O\nPOs2FeWfHiNpxNitC64ZB+JlngxS/995FINPhCcOMKEK6Jv/jZY6grRGO0+2OXn66WYjONKllX/u\nh22MQLKgc6J8tBlfSx+4cPbByvGpb5XrdpdC6qVU7X9okjZ+hHKYr7La6OMQlh6xyW5XX67m0KgF\nYGHr/CyBdGi5nuM90Ahcaj78b6eQRlTQcAKolWvwwFtfPFYfrv3HomxTjIF7xCd07bOxziQcVWB6\nWqEatPpaEI9WKuqsrWW2BxZmWsPpbed9dFc3ckSUoQunxAFtWiWkeIypyBrH3fNMvcM1WIKBBOOd\nirShMF96oJS8X0CDUrCOhPrSUxf74MLxBzTPXV+MKvFQ9U0pylhrNPVKG9RJlmUesVTWJkrN1eeq\naKH2UYk1slkVvtj4CQJ8DqtFqBy/hsZacP2Quep+apI/IDc6j1hzyVXY8NvROR5gNF3R4Hgs6JGY\nvBwB5USYmwpwDBI6/5YLA+fT0p/SfkxKGk7S+mhYp6vi+EzE1dcEcSqAGjvhjjxdwv+ta89oENPp\nleQA8Eq33QAWhWS59SwwEaUm1CxUSOue0lhhYGJA4djH2+Mliu2pHmnfCAlOgaIFM/pqNRMH2UqW\nxubVhZ987U0vqgqbI+uhLRLqONfSIFz+9beAGCxOnM8X0XSgAF32xZ63SlH5U+j90fWQxbgq8L25\n3JDNdRq/364WSHqFV/V5yKf+tKFvrHc26gqVXeGFKHof/HSAKIb+QiGAKYsZRThWYnTcCPisoZyE\nwbTMM/EVYVKVnsj0yw0rZZ9s8w//GH4hUX6oupcI42gJ2VmXAbM+irClIF9vDEc5TiDjPl4oeo2k\nPysdxEilghEfnCirhCzDExEgezp1eKTUcAwQlvVbXEGZ9IZYP9bPLhgbgdLrU0bmePdR5XKS4NWS\nU5dSGWfGh1FowRVFzPlAANezjTnWH1KENg0kIaqAx5EN5GRQ0MJP+RyTaSjkQqOB0vhawGKOYTV5\n7m9Jk9R2NxXVljdrKyMtBHCxyX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SxR1FkmGcEu3ZLVx3JPLMm06bMUVT/sF3m2H90FAL2\nHA5Z7byQOaYlZYSqhAfVbLQas3K5y/5hCaW5bDPqcGnCbixJ7oXi5XHFdeC1LfDo2AvtRQTbzt1d\n7vGyD2W/ypeBsuQ1DWpFIjqVUMxG+GZOtLsC4Z9k8wcC1Rk2NVHsMp0mzhx8B5BCEfMMnhmCADz3\n3FYrzRAWfERrHswbLjpkXwkF/vRM+irsbtK0BfXnZ3h1NjGzWUYv1ja2HYrBg0wbxr4Qnnph2nhf\nvA5Ha3TfZkZDgapLIk9avlww2u+5tjlz1QewDuFGqD+3rIwj5V0zQBWcaocKdFiMcjYjATRTSK/q\nYGhyrIJwssLorMncPK3frpbQH5ORH0Dyq00OoLvnrXXuT3sfA05iluemWCI74KLaPB7/VtNu193c\nFHN+hSTX5o9fE/3MsyyhbTQQYVRlb1U9OQLIkgLlrk+lgAc619HFtsihbYRouHNTe6HFceDW3Uzt\nrtZQUYbYhlWmqFF43tAG3ZynRkFtPGfHrXk80oTUqtC4dBBF7drS4rdwcIXKzr4pX1lAsWbD+DwY\nDATJqGE3T4iIbZmAvqwwZdaNM8d/CyYFiTXKE43pLLS7TYxL0eSC1WYWn3jKzxhn18ufKrhLD4WF\nI65EbVzfd8yLMCTXbZieqUImqymx1hMsq7p8g2YKjszRo9jXnPKN09PTjCnUtidMuXrXn+ZqVsEH\nOSSJOjKrpjMoy+/QC6iFstw5jLtJP/kT7h9MVkhyMwyt/F9809QICnwMRYPBli25KgpgTL4NyMFK\nGE0Azx+74tXkm65VrgSDmp/wmEi0Z99AiV+OCMq5hT7L42PnyAKZvv1MCqFEcLrlWZas3d81fW5Q\n4p/9EDAioHRy0Bk9kL7K9OJekbTZ4iv0CNk0Qh2RO2kpbA+9vCLtReQQtD99jKsueti/ZZJMegUy\n8aP9xreOSYxtZN18oEu7KcWJrzDR61ji92mV94BS2fehfYnYgexwiA+h6bWjHzXFCecVq4zP2/8U\njym973AsBs86UTWcRB2K7EHcIjFAK8y6BsuTT0ENPmEAOdOtbt8Mmw9x6BNmfDl/n/4ab46XACuC\n040wiVCvBz5zBHo7R79fmZWu1ocOLlVX4D/dgQvjvnKq1AVJP/frI1mQ+7X2HpHLCb9a1PZ97c70\n+dz439ALCcY4J5nkUcrJmw0S5Tf5u2G1pUSbhSMAss8x5QTWU4u+LVb7ekJwNtw4IXPwZWsc2uX6\nLMAmacisCxk5OsTNDyuzpcsi/v2IEHV9NfIXio7uw+0zXbMoYODWCcAkjHAlKeLIxG9L7/kk73MB\niB3EWpFzplhjp8fnAePCS0d/q7bc2OGUiIoCk/QO3ve2xsmQqyj7M1JWlJCkPx2FBljvdcMoIAh8\n9uo3IgB3XAqltK1fEUqlufrAsF6b6bLonZS0MkYu4HIHCK+/yphbtSw/wumnk1rRank0Un7A2aA1\nGDp2e1n+ch05RCntRXNgiiRI6JIaEPf+xz+qNpRqQvgvS2tk0LqPP3vU5yZzef3rmcluJe1yFe3p\nTP7x0Bdqvivv23aTjYM3gCn2baN+r2A2WgnFK6XU548NQpV70srLRxhINf23oogWaESIvj63NUhX\nOlf1myFWM9D2o4DKn8X51YcQ5WPhRQw+LWmsmsZXNOU/YWII3caCgEGGQKZ0lv1uJaQGKG7+TcD7\n54iKOnwo5H5tFHxqQyn0hRmQ4SdawRZm5Bz7wbzvDhEGUBjxmfdivmpMWkHKeitUHVNQ1mlsaYSQ\njig8da6uBA/QAi/Uh7zDdVcq5Jzv1v3LJ7WbCAjiKG8iYj5Ac6h9tQjy1wwGQL3CyoARE6G2X/8s\ncWltXMD6nId47bFCscR0+7RwFAi0jacPt20wXw5frey5rOaS1X1cndooY/4WL7HJVCcfHXiPH04R\n9uraKEfR21KphgSJtqXYaK6G9TxOeC9a7g5bQB22Glf+on6LgHamvqFXwlPqw19sjmqeIVkOy2sO\n3kYW/c94KgvdEYo++J8hWFKE0fOr3GHmNUrASR4RumqXF5Aj8wS5d2eT2irWN6/BA/9VpWCl7cpE\nVAtt1M75KJfmmmVIfCZT1h4T7Jch1XBuBjYszcl/gl1ejhOstcD1hKVuqXx1AMc8RcCW//Pc+mvS\nufc6TyUIH69gob56rrv69lg4ffmA9EWYgWiYUrw0JQ2DxqOZPASHclZCh1t2WP/e8DE/on1SreKT\nvdqkFneWUc3NAvg5sJfutvcytOGUpfG2/Y1snHjOX7cnHWp0T8122sRK56aw2zWeTL0BTHS2Wywt\nSoQZ+fbc2yrwBk8+sAWq8fiLqouVIOQyiYRfNlC0pFd5zOeIrOABFbi6iD8h/H5NYPljyqjaBprP\nf8T8369SocacQEQHCrX38RZbc2ZOemoXMQvE6op3GDNmgWqcv9nJDSjtjWUV98bg+XwBNx6uaZK3\nHoaZDv9LctCsaWkslocCWmv6edUVoFrDgB54sgmjG1fnzbXAIqkXdNfZETRfa0PdG9f0ZpHsYiu0\ndpgicI3sY/BjISL8wodu64wTXw3vAPeLMz2BhmTXmiIarsTq7SHObURUjInzXLY5MRuRagPXIUKC\nnFydHSUPxm/HxnFkSaKGbfpOehM2kh1PJXl1UZYD3KQ/bwIRkCSCvBy9b2S1CdWy0LS6rK+NYFkP\nhViBaTppFVw81zLyCzq9tW9iQwryqkwrLYjAF1UbyB1m27xW0RdWgpI7Y4nAbJB7S1qONcAbV0Bo\nKud5Tsrafc3D8r3nI5D+VspWEh5pbBex6PFDGs0KdeFIwF/QJj5XmkwO7wJgFU63EORhoFEXeIRm\nu5uta4SWeXYh80XWhkzqAdsD7NQ7TB6ofT8yLrmF5V+PxnKRdWYXEmWskCfNzgQDeaG8a465GRMN\nQIV3Y3N4wpEyICslRFwQ+a48zIiYpojqQ7UnuxTZqfpabf6ZfSqDdG0TyBYa8+8P6o2FxdGJuFoC\n7zzi/DFQHDO/RmKGNzXarWp0xhqpXau5tOsTpuRYdDccK9yMAAZEfM4JvYuZLl5UMWcNWVOCETzr\n2AnZbZTjJGCYWsD5s2qMstnljVCSmnghC88TttpMKFevtFCJp7WIOiI7ijwPJ46hTcNv1R0ytwJO\nZm+VEBnUHu1bRh3MIig57UQnD4Z+ueNk38hmf8J08UBaPFRaNHF3T7BEkIgMS3aiQhXjxG04Fhhm\n6q73dw9PAgIXzm5xOYMNPdnnPHVBLzXNdLXbYuWcPBUREjJ8fNn3Ah5uXGcwMX/jKtdOrio8hMFt\niQ8yKhEzvOfwz/WV0Isp442VLbT+y+PAIQiI+Blv/51ActXcYeCxn5VSioFrOQk57TilZRbd4gil\naFtuOTI8gfXlRx9Ima60vBcnaLnAz0g1LVWWrTmVf6Tvqbv6ts3Aw7iE5WFLpx+dNoixSAkVzICX\nDS818VoB9rl/ux/FS//AY/Co3rO+CaVz78nhAfD+mI3GX+sr54q63q5X5NmdQQcQkb9AN190yqes\nxTQbDthL/R0cfFAJDDXD7UuAjRGPcCxCVLcm8Tk0SYB64JQWGYW1EnfYHh2J6hMN9wBNrfBDkfkl\nl9I4QTlbxcKKhNYGeKECHAPg0DuiPk9BN2CNC3U+1R+OlSSBiOiLCVwuL7Hty/gK3VAPDqml37kR\nNk3vqXy7Yy84wZVn3zsXBnL/j9oWntlNSfM/uxB2/4soms+wUO+nvKLEtZU6Vw2f6kdp795sIZe8\nujYmfpnNSQ4IqircgZq70XL/GkPH87a6nMphtcM584h9KdCg4Sn63e+Ta5qQJuTkKTNk6wgE24ra\nFO+SYENlpR4byiHg2mDP2WfXe9sfUXvc+Epq6sg/jjBeZeVa4BXFaXgUrD8LkvYWxfk7O8FmOz5d\n2xZFyzamk7bShznzKb+vkMgZRtURYx+yGGoABxeLiu+c0X1dVYBsLbNdkMSas5zHJLSj1C2etM/W\nIpeWqGBTBUwIwtfp2q3ieRLp0D1YELJOCEqgUHwhDyZaeYSSWdC02dinwXzmihceDKsUHSvcl0Xz\nnuqEJCGVhVwLc8HDnEDfgkOcXoZ5ak7c5qkYbIlvTiXekIVh7JzZ9zUb2G6pxWRT9FatLr11+pLe\nN6n+W2C/whEfKe3b2RKE/fM11c01LX5+BsVk5+NbC9F1DE6H2wIxmKEDNWTqXhGb9yC2g6EQ45Yx\nReL7tX3uW0w1F/hAdxIofiQ8hbguSnDdjzOVTMsNM9whDZZBhrSWFdrOWTcE4Qw/spxbW98axk/H\n2lqVN+BBzZO5ShzmiYKOyop/mZ671hGQdngGxnaVMdUieJ35mWW/lQovarr/qm4GGCd0L0j9PDtz\nEZ+RBSwrLrlPQO5Dhsp+lWAm+6FCvLqhUPYhyJPGUYTt60oLO5ouPEczwCUqAMN7M/W07Gv5wtcj\n0t4N/VOrx8gzvntDizECpVAHwpTkkj78lBF5i2JHtEPTXU5fP/Ks0a2s5ONv6NyIMVQulNd6nLYw\n/QbghYOrzfmrzJ2lZ7ACl4/UO4kxqq77A9uPV8Cq6zh5fdmG86Pt8Jr0E/FyUjqN1q+yuEK2C7NX\n2lLTNtpvwz4axJBcWyZc+u42lAqa0keHcq6WmpEOoaHX9QiAlQ7ZQBe7J786lZ+z/FuEsAH1u7hN\nNqW06zR6YpkIP5wQF8qxmoyn16sfxk9EDdUYWL6BffVHOdd+ZzEU2M73Qlq/KO/URi1uT2KoFDVv\n4aIU6Z7UsOpAC3zbt0AvTOde91Ul3fcZGHynZa6FwUotKizfbc5q+1ZX6M41BwYu7f+JQdd8Fz6Z\n4de09UdqffhzwCNLPtyB87nIwKtiAI1z6T38Tphmz28XCY6sm/OfikfJ8Ux3gR8ESyJ+ZVi6EBC5\nZKzrcSlXWlYe5GpCLEUyUW4SKFMl7jUQ3xlm6m8B6N8gfYkEBSeTWGVrftBdx7+CuCFTV1atRppf\nTJfsXnjwVMQkDT+l/YntjNoqfTb0Xl4y8tdgrFjqC0sGEtUmf8YxSVIk7mn82I14fdluOcjtCuF7\ncaJVEARZW0Z0lkEbb9Yb4RJBaagzpRZuG14XFncgS9WhOFXQHJdMqsA3+1uLM+7tNLmA5L8xa9Ym\nG5vb3KRuhbSPWE5ylASOftuQuKmf5HoU+HliuKUC1K2wvhVp12Q3x3szmhTbTr86hPzB9TKo14rj\nl6MvpBxwaGdyttGmWTC+QOAAO4NSglzfICUuS9KamcUWK3ARCmMebEbc4wKJiGbj14uCyBVFxcfs\nAW4PqMnoVf3ktxTgvZEkUG2wDPE/Ln5jGOhCsWFQFXFYWv3U0bG2q2NOOuMYWpGxYvTHR781z7Uo\nhyD0YvPLAT1wGv1DTaH+HBBwfHiIa7nV06ZK+qYFGVkRcmghQr9eNSlFnTRJSh4Tusb3GP0ZcwBM\nbwwdQZ+3OrVUJBClgaze4jf1XHIfhOh2287ZrmY3+2iigZhHglyLE4o/qLgW5diiXFgfFsPOlo2L\niJAq5N+l3y7r0lKfA7b+lc6wUvE4CkoK67EAXRji0gQm/NgT5Ouxwrx8fO6kpjR3b8hPZU4pxOnL\nKCw3GTEOXORt6bISNrFvNsPoNlAwyHTSYRFy7sTBdnQoIeIua7+XymlNAdhOBIiyBAwu4tkwSPB7\nYlW9eJFCbxXv2j1MJJfjQAwtXbvTZARetnCRc91U1vNpUWhrubFy4l27G9NzXcKgjAm4mNHDNKs6\nUq3j+TjQIWVwRt8C2wqklTGbH03zKbnVXf8zdMEvOjQPX5sDrHBQb5rJIyDI3iLwOco5tpS8rRRf\nn833FP6HtoMWcKLvsB777CDtdFce66jrG2EkxkJxtdoCmvzrMd9fwHkGRcdSLIGJuLRj6O75i/TD\naXVOPvEGQyR/E3YXiieiipKPqzT7OVXGYbTgASDFLXYTGM/EIbNPJEZlBGyjizhBDARZnMbFVCjw\nSkouTtW1FKRA+95i5d9x1W+J37ClVndMb70cKAHs/noaToYaIB/oOCVYx8datUFkKw7SrCtNtzGH\nLkD8p14x7mvfcu9lARRpUE52BX1MkaIWlZXHqiuFwlOOPKPakSD1wuKho93g2zo5KboPqtcPvxyk\nfAsOfkk2m7xRmal73sGz7pRA+RYFheDiHUsZx7W0v6M2FrHglwI1sfOS5OOlVX+/NEbzAiYChJFZ\neRkila1QBjaNtfI7LUvk71NITPr7zBioQqUO0GfXj59t4KUpm6mG6gDDHWNCgO4RGNRriKkpvNaL\nHySLvUzDz6NtFsNJvcLLkWBwEmGY5vONDYPpqh+pLIlcRr6udgFAZ2xKsM0DYEIWt1XhZKC4L+6P\nd/JguqW4nnuTk8RcUSsK9LiAQKJhYWBE/7CzxkrSc4YiH+posmQXWsu1UhuTtKiOFgqrefV7Cck/\nx8ejezWVRQS6YX9+qBQ+WB3n/7tr6qbkj09A7+11AUkFDRDvSiog2TVPoDd8Ws/sQvuDI+5l/hbQ\n8bOOZp95IeQHiUFO9DUDmtC/SNOpUCg6rf82HUPZ1ZwJXPsF9A3kVJLNr4lDPR7dWxzp1dSgU6L6\nGvUnP2YRq+H0FFfnMudvGGQLGrlxyrKQt3TwhuXu4gZ2NjJ/EPl69Ob8ypvgB1ikYnnONlGf5uSv\nMws+Z1anRapXRAO7ks5+ol5Z1eFMvnmtgIwEV6JHyXv687mMAOk1t1ou4+t8rtOm35PAk4gIgwCy\nVrqqJ+iYo6tOb6/ko72j0TUFaLsx/XMw2fxU+ACXckutiEz3Aa39zVIlCmA6La3FC4peMsJJ0LGq\nqJwbpg/y1/YRzHXLVRC+0TcVq9borlgDnb9q2QXEOVA3BOYVMPS75e+EqkhOCcJVm6w7jMxhNXvZ\n6J+EbndD+zTzYaFZBoStcmM0EMpf9H0C1PQHh5xZ6p65JfNl8/lJYliAcVaVoXXM+Jw9dVLolbuf\ndtzQU8vzzwVf5caZXFUSdkBNn4+cQ5KqSlD/Y50OxLK7Dn1Ey3qBp02CVgv5PiYsNyTaxWI5K9s6\nFsj14h3/9AeeUzNBjqIYihx+v+P+Xz5Sd36adxkVUhRdNrFurw/aE91Y+mBQoTjWD2pTkOBLJgB/\n+JctyT6qcUDiVK2WMBu+yQurGdtpzw/kLD6EhBZIUq2frbWpdxYJfBrUIvi7jDhIGlK+IxQ5EQ+r\n/BYncxXmBaJHGuEQfBxpZkbQPnHz9gu5SM/xu41Ux7bjEAZ8qXZ7eQDq/H/i5THMZEFgxU+XvLIC\n06fC3PeeNjbIbrAtGR/pPNuBYvnEFhQopy2JkqSvnrF8Rgg90FGt3qF/OtnSy9OXcWti3tjd/D23\n2blqfxDMdSkE4hlL9+bRB/JwbwW7BJFEDBYMRF17LEAo29MjkgMX2aiB2G2WSXIQ9zUiO6+HvTtX\nN+PGk0/DiwcmqoBWdAncxLLyaYM3ZUfgwjN+hk/yfIKpxJZ28g7QBKp1Hpx41hKdYsnblEnU9qsy\n03fRwAh/SxC/Ihqp0tCHQqJbIVVUIACkmL6Gc1BR2LzY7dZZMYfWPXGSUfcQqtOUxfCIlw+HJVj4\naBa26EvVyNgOO0aqy7+dQlOpEawHlS7cTsbTmx3XXOZ2lD0v97QXgUOb9zmAKTi41lpXbDsHkYFN\nDmGhD1vtf0f21lxml55i9yWq7hVOTg7R9xGr5yXcmh6K9lZR0vDDwz26lnbWoBltkLOkQUjXW9jh\nsY3lWhmp0fhaG3mt3GP1wegVyjO5qG7I+V+VRj3/hLKgZL84I42QVlYGHEtT0uS053uEsADOX6NH\nb6OBdCNKLSrsad245nV6E27rzUDGR9wuHmBD/HH219kfOt+ZJO0AQA0DjUQbzE+/GylpVHEmfMff\nSkM8X4kLqOJmFhx7vpDy8IsnXd3sw4Dcf2AupRPHgtN/IAn0kjadIcSOz+NIAAn+bqXCTwcrBtxz\naxKJOqsMjkN6bGcaHfvdMIZNx+JAMI5goUPxFZh9NXhX0SYfKj5eL0Mx0eq5g3wECtyYfSoIsQ9C\nWpzbXw79lqT0VHYizX1AeRAXhIr8bl8KAuWLmDs13EtqfD4Jdfrq5+IykP4f8JATT5YNq5GbazRh\nnVv8A08GN9g2FZoUZQ77yI38l2h/oDnNUPdx8r8mcYr6fpow7A93IMIw/ndeitDIMkJL1P9ZAzuG\nYQdV0mXyNt+CJVhN44jOHtt7yhxKliV8+wFK+0A1SSRkquIYylTnq2L/gRydYRf27etWmAk80aLX\nsgQm5HpO5qKaVX/TYdAL6wOyjof02IXNTs5jKIwz9AIo6VTaT4ayhYuoRSfTtjRW9/zgMcBBo8xO\n2mubWKWOrGEkRcV/nio16vTZ3wdhDDNarzqi9Mg81fkJ08OVTYqGb/kBzjBB7VDmDqypcaXt6G4O\nIFZX6B56o2NGXfrp+nSLI/Sd1C6SHmjtUonRHSO5E3b0JdjNg4NHHuTp3vI4C/6tRu8vf6ILPoqX\nBddoFjEwlERhNsqvqHMt6R+x79AdpPqlaLXTIyIsFQesUXnBVHBjQ7F4RfODJGfBJHb9WtWJwGFz\nbByf0DERNoUIIt00ky1bPTgkfx/DN16uNV3bXXhK+79mLmQiShEpmuJBFgRwiMIa92KlA7CPKNcM\nmAScAxv+ueFxbetUwJtVJPugybWpBXkgHB6clWPT8hs0b1id2ciM9iQlR54nxoKfIu9vpIAusrzD\nWkqDUbTz7dhO0B4vftRp5/ge9T6p1NG7GJWNYCG4XkR0haN6EtHpc2A2+5BqEVu0rsdpXgrCcoma\nN5lMDhBRFZ7p2oypB5rSIy+Ukjy+qXtDQYT9iZc7iJx4kZnfLy9q6kWvnZSISI0SKS8YQcKaJdTS\nVZq70U8BFM3tze6p1cDXBPiSSBLobz0oLCYvOHrBVD9Thzd/CdgM0EOm0Vnos7qaAgxExKpWSrY0\nEPWRRRQ8A2+wXu6l7slo+2F4UmdKUQnFvF1U1ok86NzWjOL5iO696dmr044e7eRKAWGNCXArDrNS\n3KoUY28NdPIDjgRWdSygG0CByn/r+d50MCC9N3O/TrQzl0EipX4djpzi261PevPL55h8di4ImJ/u\nG2pbhwKV+lWTx4bsYtzuaPCnsvHMkIEtgBlVSfLwQufUnxsFnHVp/zNsVUC+0113jKErUdndnJgA\nqNk35H7PuPiuD8TNEFrW7le4AWKxYgC/Hva6SWFrxJsYmwuXhdzwXZJDcz91egcd8hIX+YJZIJti\nQMhb8Zriqll/H0p7t+fxiNvfqciyhMqyYRCscfhA73wvGff+qPlYIbw81aKj0MYb+jcnwYrDEEFk\nX5LeSzAm9l65ix+hpUmoZbpUH2MUFd9uh9+3z7YYJvHyl0HkdgqE/eSu8U3OTn1OlmHGPWXk0rA1\nWNDUWQ938o9U3/pF8yrhGcDsz2j1nB/5j9vAq6aDVwUMmDflaa/MICkX49t3oUy+xfZJwJz8UtWq\n3IeqiMrUD9bnQxlKBeKhstBgkjTo4sodyUqjD3AS8qfzB9iDhmSi7xrnznhCggoRua/6mP0eXPVD\nsmr7pwBCmfdUUCuMZAPyuwQmYD3KX1Pz1T7K+14IfspDg58oHt763eH2Ct8J8tGU0cdZyQJl4d6C\n2FPTDoGxiCooqvaDOqq3lOpPKmoj5/n9Zpt6W211Lw0zMnq8njmwf14H18QRi3kbXROKyXwn3bDz\nSwN0OMzNb82jRQZFNHQ/lmZUqS5oU0vJPs03n/tdxBfbLrEq8t8H1hw9SvNzhS6+MaGGNiwGYYF5\n23mGHRejPBcYNiHqFPZUyZG+SFR5c9GR/SMOuXJz85reHAmkapNov+O5+066tPtlKWhGg9UU/Fpn\nLR0hDH6SyLYXud5/yDd6RYoSZh5PE2GRlyr9Ul99Vb0H+xLwvHvFEsR511ax6g//88UMP2JELrZ1\nsr5U7FR0YTafXkZLcnN30dBIAxqFNGgmIVGaQq/lkqXpVdM7bSXmipgF3mSo2X6v/6d7ftl/1Mfu\nRs6az6QpbhOfcAZObEA+j3HsqGXpSr+3K/l+nGLLn2zH19P/N2EBSBAXFzrTzZ691D8pMw12u3XP\noeoxVeL62QO2VjKL9IASpZTN/BYV9UzBZ4SImC7Y0QmcvIMVqg63rHQw3PfeVXYf9PA1NN6Uge9U\nEk5OkXp3vyi2ZI6wL4kTnB3vZUWJ5TMP5sCzq3B9wrgarhYUtoKbVZmhwV7TWs+wJD02/TJybKGX\n9S3YiD0kc36Ew+HxZ2bnNnWYiUPvruCoeFifo6/0cocMt/a0EdB6B0zpdmtZQ6l7soGul5zeu3+q\nnGsMYj6ceJA+BPCab9+Q9rWuUO56cj8psjhRV7N8SSeSMpWXsIwQ8kCd+8BU4tuZ/Y+GO15OYUuF\nYUMSOLCD522seAn8pTvt7SAFrIhjb9A7zTPO9GDOydmaQrleEQY2lMqHAiOSholXwY8qDSHb/nRN\nzdSCmlmJHUkauiVz6HvaktdNfHSIIrUivFCjKJFitUE4EWebx+GWZmA9gMvubMNVT4R9FCfgRXQU\nDH+GXH0Fb2Pm67PFvTM9xtKhiUwnwM+Xs5Poey2xwUNulT9pmq2OjFjd+SHde6LBKZP9rPD2/nw2\nY9v77nOUbq2AXbbD5f0Fu3bG+OQjwoMDG3TZApfYMwsCiHT+poX6PkNDwEn5uQKt3yx1oXTnXKQL\nwrXV2fuZWt1D5tds5chTfjgjh0GEdWzrdFygXw3DOQVIlUFMuq2xqXMwAzYBtcUNbYRfJloH7HIb\n/kbfc5P7Hbxe04meih/n2TowMhVHQlTwOzKIStKdzz+GOWXTP8xVUVFbQOjQlNxrvsguM9uApSp8\nn0FsJolhVdLykd1R/zPlGRAo8XIp73J47EPTppZUICAitH2cDLpLSrrE7xilKOx6RRC60Ub8bNUF\nOYJ5COkSocybeSb3n+Jer8Wyc0aIqYilgX3aHEJWfdcyszFYpkW/4xb8tZ2+OW6LODF1MaTmOeTB\n3FskXEbj/WX/qMGMTXn+2RQ/C5YawHwB9KuVJTV37m5aaejAOFyhO17RqFflVsE7Ybz7RO8WU/z8\ns+5h4fsFlcov5H+hOLDgY7/JAKvxwGVebSia5tAuqvGqxcjbnEfYRlphlK5FtEYrGSUeZC0clf3Z\n3JKrZCdx2/+uvDB1ZmIN4MV6jMyceH85lTSwgwUZfGlda11aGvz+PsH/b8oQSptcWcOsKGhYH0c3\nywFhFN42eBR5DFdX6r2ehj7j18GB6mC4BxMhh7rTIAhYrO9DPEfg7xvMJqq44Cc3a7eEx+JdLbeR\nyo+PYhtBrlWX0Woz/Kfc6OrzzWlB1MX2UtsPwUrlrBMpFFDT9qVxOb3T+u1FdimT1UgtctZKCJIB\njOtYteIXN1vPKffPvHaUPgesYijwybkbWyK0kSaebCqRb5BJ/0GUlNc/PnjP2OIT7X4HRhxJAX9q\nHjQTRiofjPpS2ChT1ExBAZKEeEu2QQWia5Hd415oJSO1yefF5G34J2auuVMndmC29/v4rLlyCI0a\nY2IDI71xA7CQU7y1+k118LZqjk/1j8zOKboUbJZhY1KeR8lwGXeFyEc/qw0txuZgXqJDQGdOzh8i\n5CqyNuCboyKmh12llhK3t1uBDZmWIY1lyhJX2SB3nLEQr+DSrX88i6AZ7oxAKrJpu/FCxNHxoiFv\nQH6W2M6WcTtdGItnDXRGwFJuNlFCiRycO39+fTAegO0s9mND5RUbcoatN2L4RaQazU2bcijtkMIG\n3qAGJ0HqrqtvOb5ueFN35UuaDt/7Sqx4c+CBMyEz60J6h0simbdV/4oFEnnZaEE91BKT05fIL0eC\n2y/iTBVFZvzDv2NcgNcyScWvdeHRkxwLQEDIm7uQEuAgY2kv+EDj6IJequCYUlOqvfNCq5U564dA\nuCKQUnfT0wsG/PqVH0ErhCq2kWpxwDGiNYmlqxoCWgNmc+5u8iWVFubaToS7irXZb6q5qFaNmLH2\nuG7JvbVjduLj7514J5uV+XmMjbE6/v2o66en8g5adEiX5n5tN5VDpMruzTGT2cpwZ5P5HlTeN6Vz\nePQc+iWpTpBGpQJgwFqpLhcM9NXsLHRIXHAYyLtaCNVhHdiCa7a4jrtr6mQXkmv19BAa/yhvB5Yr\nnvOsuR8g/8NO5Od/I6C2CB93IZLZwExQ/V5WDKHMNioJShJp3Y2wRGa7QdnQPC+FLOI+8cb2RX43\nOFDDlmTAz5QOJtAWO8yw+izq0Ac9W+K1ckqawjCKoYTukaAkXsJ9WjhctQ91IDcE2M09sbNtlmjK\nL322FXXVFDpq9hb7PldGiXrYDskmxAFugC2mYEKis9quuRt0ZPMBT7KwFb+ELHh0+R3j9Aj4Y4Cn\nUOJNb/rljY8CaJTkknOnAD21jGMQXa3KJdvx4gtHIKOctvgBO9++cpz3EpK5iLOdMeqzpEyuqD/k\nfXtxRJBlyOWcFolXLta8QctH/eJFGK9juIfwdjWJhz/fdfoDImVBRsz8BwLywMaMeZTHbAQudhxK\ntZ1C/6tYYdF9gUACD2dFOQBGez85VtN9wuKKtV3H/OdRq592T+4Y0Fm+QFrb0xo7BEZPGd/zQaAP\nXnYsdqB/JmwuYBloOC3plCFmh5rn9juBSX6QK1m0dy+GbFgd4P1HbhCuNNBro26tERj2aQSAOeSw\nNY9kiUKZDV7zfaeVx8T6DiCRWi3S49SJ8kr4XgiyNfge2HkFAlanbN0zJvNix0mhtqF7Q0uWmPW0\nGWxpfXA1emM1A8KUcG6GHx72PFOkXtH819jLpoIj+u377c6araPO62E8Syov0+a6IqhRHefJ9EOk\n5h565kgYNuDKqllz+eGT3mO3teqIna4BjhxTNnrAKckrDZbHFOwEWDx4s6aZ5mJPGwGljUYf/Ljw\ndZAT/MpHYFwt2z86+1xqNTw3+a7vARg1Sm3GJf6n8CSoay+rzQhH8bNOfXhZrSJWGR8c3SncN9DY\n/vahcXYj5A1cDWSUQR7T3/d8Uo+gJCNy0JzkWZRDnJp3HJlk16fwGLv9l88U8Muu4/hqrUynncvo\ncRLpPgmPmUwl86Fhq1YqZ0rVmYAVtlJ84dbReyuV6SoH5hsrEWjp+yYmmnHBvUa0dVBEbrT3wnHD\nNuituIh6YLHAAm04HoXkTmQC8G7AftlwQ7gU7nibbc1GyV+zPhDvFJXcgsdUh44jrLqp6zy6D1/E\nXbFJvhgSecytsdVAg1SWVRZFU8+/XwRY17w32XQ+08HVD+4kfi3utRUq6MHJNXUY/H/e+MRSF0N6\n3wZHntDNzGBW0Z+IKEp9UovyLMVTcgEXKS6NjkBAhek4RHuVZ6gujvPUmm+JNtVptzQFMKgB11tS\nvCI2LBxPqKxWYL4/5sllmYFSkcFLFG3x3MQbkHJgwLf3AALk81vMh0cIsINeGwpQCe0xRaIDJPkN\nFGLLv7BpiN3PKbWJFYZrdu7wkb5genB7aMc7nAf5bh1w68PphfTd25cxE5iVS209jF1uSokNqS0d\n1aTOajPHeTaq3TabE2ZMK10OT3dON3/dn8m1hSWdQEFHpLzg7c/FcCrhN0EOaMihFf59hvD4C+N0\n3PYrvpInoC6SmbCWKOGk4L3fqajr6NGIDsYI5TMvasUHpOS3/feCHJaKuqLVcrnc83uN6Lo7I55f\neVxjdm+dluwzy3jXYYcEv+V8iEqIP5KCqwcGCImitpdD+3C3NvlMECipZmcdd9RfGAUhb4Imn4IV\nr0M2kE7/24Ow5NKPD76683oH9iFHxd83c4c8OeW9Ed/ML5FLQjkWtvd9MzYUXFfBlEnmvV6+cX/x\nqqJ+PQpAQuMOa6sZGrfDHxf2cZptGwgEm1YDVve8io0j3ryN1/oFTQgs2q51oRxOpLjdo/FPGVhS\nBjCrHam7lvctqQYLr2ZgaDG5j2DPynG0BORg3q7XlQmgtxo8s2+fZoFwsnkWM24i1NFpjEYjMDHE\nxhnw6W/OVkA8LTyT5syDdHRKblIZbB7Ym7EAtL8izZ6sLgnA6R6vnKfZHh4S/u2O6vTnJ+xEs318\nPxP3M2gYSFBu1EXbLHy2k5Mr1EkjaBVpJcCf8XAke4kOppM5RsBlrkYkrN/hSb2ziZmJ616AlG5H\nsSiWEoW+WN01rxbuZ1fNSRW7Ibrwzfm4MKWstbfuxO9/a6QsGN2kMkGOy1s19IX3D7mElBfXKacE\nNHCujUtYHAJThjs98Cu8+7LK1nCQPXOUdGJku/Lom+5X/Mjx3rtTkZdCOJnaRqeduuQSua9OxWAk\nEcswnj5Fe26VvXXaNkb2qoMAcx85NknOpSt8TcEi8QqUVF0MOS2HkKNS0SeX3vMT6HacyHPyqrIZ\n6LSSGEU3ixsaScmVleZizeJYB1AeiTTixJbBFppAiS0khYlt7CJasWOnuYhM8G2cqC9LwrNDCMrv\nW8zma0jSLSlKUHxw80rraC0moy4p0HVDc62vhbi1iSlh1GUTZMVfN+YYzdRaV5LoDdAIy5iBjI3q\nED2Dnjmm2asgs1ntgscze89sf+BLqUhtIEFXP21v0i5ivdbdkg0SPMD+buN9m8eGTjX+KQWs7jAU\nGN6zAGu8DEeYfSaYef7zXUr5VgHNsayZwY6HryW2TKpURrQpgfdWxTqC65+MT9kpbczVzXSWP0dV\nLQ+W6XDjvGZxrsiZjKc9fGGQ5kj7WHop7l/OVQ8srVYAjlOCo5IPQtmihvfpkFbAFyBeo5sImHrZ\n0A/0m1NY2PqWSwdXLY+HqZE2kLVlZfmlFI8fN/KzXTd2dNYJ2wIy58AtOkkhPWqFsgrsQjesP5DO\nYXXVOE1JhjM2cyiGNksdjrqAyNVQ1BkAblc1moKccGGDUiK4YhU8QRXF3o5QJXtAV8Xc2p/sMI/5\nw+GeCFzUX5RMe7Iyzk7tlk2H6B//Lubx8Ul/egI0dVxJ0eBAlfZCOntEsT+UyxZA+MUOsyufk7ap\npSc7sNqyPz0THTvQFx4+zb1y4vKVpomijWhspiTW0EqaB1XG1Sp7THy3TkFOUCn/eepwSfMDDYpk\narTDKqTNMQ6WTqeQMudyrMSG6kg3IsOiZULs6058JGtswGTolRHwJYJ9sDGLRbhDts3zWwj0TR6a\nGV831ts5W/w36fGkTc8a4EXY2IihfRjntPo4QSmUPB8J3TccEB2qoFUoFDXL1J9TSwDtC3AmfcVt\ndBlOGpx8zxWsyDeeEUkswRkuJ/G/LnBJuh2cJsetJb7tLYv8Jw2Zj1r4pzILF2k/gxsVLzk5VWN4\noMTkHVOFGLFJ74vmqDWT53VCziQx58pzWfnS2gFQAPbTBZtykZ38FkcbLRBBPzDsBMnFrwIyCHfw\nn0vxIZxSaFSueW8JS6UK8X/aLHic+uloqnf88MFfFIk459xcEpSTdcGZsjGzk4a6WG77GhS8tQMq\nDGB69Ct7I2KkK+W8GEsX/26lTw6Hxgha1LC55XMRwwzq7DZnZZ3L2Ch0fVK05nMpq14QA54UY1l2\nOY9I4w1PUf2MfM3qC6A/mBb8yqMcB69XWSB8UeWzFh1/Yey3hRRdGpoyxfLlc1lkq5IS31VbWqQ6\n9sg5KKI6OPKB0UGDARwkdgJ5SJCyz/5XEBPwadmtjoLybp10R+SlhtUFAZE/9EyiwImx4TH/NcGd\nzkwLQ3tT0x5giyPk+l/inVodjOao5swi4HTTaS9VRY5UCI43zTTQeTPTYvJRpMwbIoM6640WKhtJ\ntw0Gw3rcy0gWsiFIU2V7Pu77Mc/7l21pB+S+X/AYWBDIUzVvcV4I6NZEvnOgFhK0Tsb5yUoQQtPW\ni6Sz2tCyiWgTHC8GXy+gyj5ukdx0v5diV/XftHyTOk0OZdHUoljNxXqusz4oxMWv6q9dQjC33Et+\nUtRoMnbjmQuMmPLnkS88WewASprdJ6OWKU3s1zREmWXB9Xi7RhWjEQwshVkAwNEWNS5wlbeicJDP\nl8EfRY5xEIQtmKVWGId2lhylwYR5pdcM5j3DPXCGGwhDALxErFWsy0oaWCVakjZw2l6pHTv705Zh\nNWK2fFi6JyQMJAEShwIny+QrlPELruZl7OYJahYRJO7GUJzRmvW6KCzqitg0Wl4/d93S4PtH7LKG\nkrxEfotAEphMsRWOi4oCtNTbEmZfHXjxpPd6fQXPfoCXTBRaoVvBWsTjvh9ewPIi48pcL0nYzmmB\n3/sWDTSNVJKIN/UOdwybsaKMHVUptamgg71Qv1+f1INn6ACCRQGrW5sRxlccy3J6AsLRtQ1eOz/b\nqBnTdf8muMOGwKoud1G3mRZ3YulfFQVcQSHp8JMZhm9DjQAbUAcjLhlXclyAIAyS7EH+E3NEoIjX\njg4SsQTxb7wRAX/Jp5pFt1sD4nKY4pbnnidsWIUFA2BFXlSgO6nbG/AnKrnWha2fEFYZ2LQpyP4Z\nmC67sPhM6X0tNBW3R10MFN2Nv+HK+/VItouVtjjmo7mGyyS+9V2kJTdGUUXwdNoOpDTEt7OkCj9V\nJMzAPKN9f8YxTCR0hPxWJMrlToSzR+bc1JnYfdIPX+Poxg2J4L4wIIpZWmoTBfrrSL2IeefSxnWA\nnm05fIKdtf9wUDAJsIFrpBJh311qfBO3wQjgSgRQHdXyF8P6JZ48D4Q562o2rKiSE2VyWY2el1sV\n1mLsRkDLoZhunPuSn89YesZPw8vxo6xiuDvZZZJ57olIKXSIUkqLOkCsqP7EZgo0lz89ujmanbi1\nh4EcQmNVFL89pevw/6bbzfuTbe0/FAuXeeu5L6bzc5N1rUNCt1pDa00sIWKwuSA6J7y/b/NzSbvP\n44WGpzO43Y+q2PnR1QhgIhz/FFA4Ivyt3QvYWoNypWTDgvY9emLN5fyH/4LDA2vCFVWmm5oyHq84\nZZ2v02g7cEjl1pg29Y4H/0loI0ze2RWRrnZ1xLrAPK2T5bC8Efu0y3WH4cteMn50Dp1bCPieyKHx\nd2XXoYjw0e9pdvJh9wrONk7pjVoKUhrJpJn8ZyoJBSG5I9wAZ507cYfIIOV+ycP4fKExoNqa8Du8\nXWMFTchsLLMTXTuHndM9GCQ6soxE8LWbe5AaimPI0cu1Cb0ow+LIFKv8SQg9s/qw6dN4fxP53BUb\nbt3vwsBaDGdTToOo3iE7QLlrdXX/CluECSmfp1C3UMIE93uOAa6HuVIFAVf0ueCnWRs+AdLE42j8\neJjBgfQoLJ9s/hMbz5kp5KCSPKJ23OLGepYDYB83uC8ftAoJaq7ANXAaQgYa78/AGiitTWkOOHTh\nZVctjMgHuLGpUDB5Y/QggFaZsOdMtEQxXKpeXL0CnBs8rZsenkIFcbb3D7pqW3dm3KRtrMwQ4URZ\nvfZV7vCNSdUthZJi6lC92rmALJFGaQR2sDdy98RfwTLXkKDFljg9NS5ZWXfD5ppYUS0q0lu4KlB3\nGRaosIjmagaKKcy1KBwUEZ+VG+CVVok+SyplGmZtzHQ1iT5IGLEWt3vKogAOrho7Dw4kuhI+XjkT\n76lwszu5l/vbAAhU0IY+cLiNXrlyapTj7xAqhuwIhXUbIerFxZv8RVijskBcij8C6QsfiOqzXmi9\nJnEEXqmLhsyzu54/ZArJKDAgHV2zWm2VO7v3SZkXEnTNni7hhJigcjO55JxEJKD5L4UQJLN/psAH\n6bcxC7xLjfdkjEukxIJZtbmNjxqzAXyDIP9V0k/ubHmlZeo1o0qJR1N0OKPEoCGKZYq4Y6/yAML5\nvTF8pmEiNG6gyIBfKzJbRbeV9HytQml89lpP1pDSYYw8TQR+uCTgS++H9J+rLh8o1hNZlVkLe5ap\nZBUUgHaHXCYIJFXD/dN2SRmBkTdDVt2faIMdSv8py0TRm0IzbfCsmNidl+qJdFMZHTaXzIW6U9QQ\nzuZWk667jox7e30zg7eNpRy7ANbwoEHItS37wzr7EE+NdgSLnH8IJBen0f4BXJFCdWob6WYDYxNB\nCQ5eqEIwz6WA4Z7ic/Ad9R8e68w8KMmfktkkWDksZ5l3L/plD1Un046+zPaKXP67fZXLLRhHlxQX\nNNrWG70duuKmjjK9zyg1kCBHw1P7KEatl8OPETBAxT8NXN6GJ0GLOU2Q2HaiYvXFhOCdIKNY1EB9\nXBPk+gm3IvXaU3XapL+Fjc7P216k8f/FveMjKyISIi7JwuM4pci25AJJcJG7aT/d3h82uJnRUYpG\nFBKxKuPUQHOyN53j6eVPgxhDVldnZfW79ON5zXiqIlOn1yeJR/zE8MdxboXXEiAtGyvFtA7m8neB\n9YRoCtzrxxoZAuwIkt+4UCLh5/6hVbwELtlmB/jS03IEnJmnf0rA3t0yZVVpEbJ12Oe6zSblJooC\ncG773vq6myHHFxWW4ZQcJqxyElVGjSfIP0YO2FwD9hYTZZZ2mNDzrrK7TUcXK9kyy+5srmBQnG0v\nj4R0omdCo0uuIB8hgJALS2TuIWcNoo1VFrCSXG/CWTWNz7aPg9i02ZlwfwQVO4+p3jkraeloGjrS\ndXtC1et81VbAvWDFbc9hzfdVBWWJb+WId2mA7fS6nu5aMecYhTh41oSY/11R+v6HNe0+47MXe6io\nQOUqHSFmTrlOeAeOrUCtoeta/VlYS1axjTPOK1zjUd/Sq2lgbehDDK7+uMlg/obIOmm7sFYpykAy\nSiP00ka3yLORonJB/Q+hJ6ILufEc5CVdYeDJ05rsICWX6VO+28BT4X4tzaOcyja52CjcXfizE/yV\nWf0hJsGV4n8GJoZyRwMrv/6qp3K/nIHY1nkA3nJuwNhHp2XeZDVVg8X6W17UKedppi+XczhXIsDP\nsCemq/DgPlVQ1C3eHNC/MzmkwoSm1myg03WsASTUmkui+AfxQJBkeEGp+ZfTkFh1jzu0eQMXQ+js\nRzA4dNmbBrJhXrpW02SU0OvnO2UsyhOaCN6mHoqKrgU8CXRD4k4Mt2YnAyRIWpvCwUSlc88NSQxD\n6ZU88FWtbGm2ovEWY31C0MX7/3w1zw/RqnYX79cQhtFs1KxymVi0U8BUzAHjRMFBW/JY/kiymOY0\n9wWNariVfQ/m6bWEQDoCz9WE5tv/jewa/IiMA8MNncTIre+MaEbCXh/bYNl/rMuatX9SfaElQ9ip\n+4lrOOnQ7VHsuEVgsjQ2ZfsQS9uwFzaS7IQRFIZXHuoIY/GqPKju5yFLN7jh/S9voUno90wUWn+x\nFd8GTv0fZRxkkwhzjE4UXvkddcVgmqWG7MfKOLT9al35oIyj+PLNsAFYc4MysIUr569IEhtR2pc/\nCx+Z9VgsWBKALam3vPEYVVFNktsYwpNDO2hu9cAkeiOmGiQKSkyktuSXSmcOgL22NyRJyfbrxZz5\nUW7zGrSi30jVtsYHbATWp4DXnNtYkDuWyZP53JC1Npi5bdmBV+b0vC6ic4vLVKdXN/e/fjlnSlWg\nbbrGrmWsxptzsoOqLoZlCdaU0eGLbBtJpT9+vtNBRKO3dkXaWeHQgTY0BnCJAmhCm87QwrWy0hFp\nSum55ddSBd8n7RBFrBNj+Un9xJmOjUMpytXcLkC2JN1I6ZK68/KSjamAoCtFTm/TEtX7Pc2NdszN\nmtFCa0UmWkk5GLjnjRSegbQuuMBZeFFqQr3Ugcju6cN4wnCYCJ7/8kv54Xy40rS/8FtMRT+0Pn4w\n9phSxGLxAIYOnKEInqvvp36NFEUCSkjU/Z/xtJjPs108rCEaoG2VHK8gDvmMpIhPBL4st99AuKnA\n3381JxFS3INiVZ0JP7+uFy16k0k5HYgVZo9R0U8kfGdl65nDdcgvXqahlUxC0ygAsOivSWYjpoNS\nPR8JTXFMbOjj5ZVIZQ1XvhLepKxfOiGBCGcucGiUNnoRa3EmIuIUFFx/8Wby/M+S76geMBpEPWCJ\nU8we/UW4Rel7kNi2kFMFH21sCOiinr+CHR+2uVr2EQh1G0D2wWZuHnMdSDmJZsH38AFXmvtlCFgD\naam3O29I3i1WjNAoiXBF4t1RfjlKDOsIQ9z6YkMf9o7YKmDglDAMrbXqnp09pfvWu+UCr7w1xvur\n4Esk2pfgd91aKAuKM/lzNXuQtHiQCMeXJX1jSv04xOjCyJtFvwl9Li8Y4xQpg0tgCO9vWOyPbgSJ\n6UfRi4jlr6eQxOSigeGgg9Jy/pdi172nEQ/6TwyzC0YLOggYs9pkl49OIEbivm2R3aNGvytMh1dt\n8OcvfNm1Y4+5jhYk9zMilWrdDtTcTeMG/rcH5unLhM/7JYEPSus7eD7JErYqGfYhi/G651Jsdt4X\n6JM2IgGB60LxFsCdBeb+JcE2xYDYqVsPt4igQgQCVxR86D4Y3SDzHmQKK49/UkCs4qzINEO0+EYY\nvw15hiJF+ouA4Rtak4vNRVnh73AeKzBO2qMAnwvdojzuZzBGvTv8tzFWJ7/sw0fA9BxXj8CkpUax\nWjEPvfV2Y70pRojzscv0pa4tfOCOrLgR9gVsZqQKn1WQ34T3Pan6/FA2posLSlUVY3udPZeCNwEe\notGlnUKwNA1vf3uGn0xmCuFRWQGPHVF8wSa33UPCJwY4qlAyxVTeOcd59m/BHFvfgPZuqEWurF8D\ngt8fqA3vMa1B6sByTk4CxNLzuNo5ee29kCMNxrDAbmRWhEuVhNBjZTYvgpksp96QnH18sTHBYwJq\n//CD+dtmVpaTRWVWOtFcyFnkcXNdGZl+12J1z8QUzAJFnokSbAIJ4kPYXL/NRK8nFU4Uq+9Tc3ap\nYiweyUOpSGix2K0n0CAU3kdG2GmnMxlRgIc8ItNh9cvScQgN+/J5c1mN0XyZU7OaHCZYO9dPptKs\nepPfkx3LNl3xDS/Q0sc7FXvpcOY0OtJGEdoyf8n6pY/McMduWJQbrcQGXxrzZchbfHANXlK6bOQS\nG9rHyAIpmNcBUnpV40saSxo1ZA1orBUOtO4kWdKCbSmAQlFFEo5dIXy3JZ+eQ2rTmOQWjInJU8uu\nhfAXfUCTmoOeBmANojFLPp11RDFycPfHDN5rdO3ox/fOnI4uTcBtPgWDKDb83k7mu3ilmvZLKVj2\nyhSXygqVNNMxXtQGNrZylRDfI0VvqtRyM4uDcHArXAoIbp5qUPr4dQl9qsgcPU8nSpN38TO9ZZBq\nT/eVxWA5fhqJgnpF3869v13frwFTKsKbUsYV61nkGAZFZn3+kllwpgBJuSFlvWm4J+nakUEamhSJ\nMGuzQqTMbzJ7Txi/3kYAg7iiUbfqgQJvMV/DCKWUPTEWujcj11gtBqEEL20s3g1AvO8VdpqSkMvN\nSpM3taKCuu8NMLfH7lfSCPA9TGjGNwTMgottE5YR2GKQsZNak5l7+qteY9TnvBMiLIgqo7HhKVto\nL/p6LgYR8WTe17DYJffSehhryA6T3FTIyWFPpUle0ZuWIar00AlBMpinkNsjxUP7bu2jyw9NPeS8\nggbvkZL0gnQhVnH3Y5p36LbPnvNf4l2X+7ihF9V73C/gm/iFk6AlJJDlddIHgWDU2vCM+Vn1rguU\nrjige1w2ny8Mfp3fei5ENLBEP/eDFQ2pCwZGnsT3KF//sdwNz63mdTaUoD0zLMfZln6UlBN3Wd4E\nsynZ+AR/w79/Fxjy+oF+92IXZuX1baWuLp0mW0ED6s1Tjw3WAlw0ul0LWAjde/tc5K3reKN9rgz7\njIFluBcSIZBYmTEBgrZwp0iCn4StnxfuQjgFu0tDLNue8Bsnsk+xA5i0am6DYrLMcu3Un8loGI6F\nGNxRH6+2lsCbBl9Zw8kIjyox6DBj53LR4FY/ltDxZO/UO2r4R5j1+pwYrxYUqCh/Bl7TxHJbaG56\n2lh4KH5lLMYt2fE47ggJMCBK8JlsvsfttLzUNqvbnUuFMBK7i4VFPBvfK7jrDWbv/ufvPzyTzr3+\nvqiujVyTbBwecurQdyXNNXPbnaa0s1wDs2KwWtfM4zf9XaHukgszJFl5V7dr4QgobrLl8mYa7ivS\n2yakGpGPjFeUdIUbGc/+JuH3HCAZP9WgE5/Px/2C1w6RqU2QCRwtpS3OfaUUWoiDrkGP5MRzpzve\na4NirhHWNGhJlWhss3YvQ/+ads2Z6VMMsyo48dRnYwv0H2M5Dds7XNOyLW/MiafMGAz6TwzwQhR6\nPILSbkS3n/+hbBucgaaFDuJAdc5YjPlGp+L1G3RJkN6VOVsBbPJaQrFPyiub9VUAk/ljqCWCCDEb\nVNyqqvpedIoJ0Nqqa/hjmgOUzRCVVySTa/9yAyywZT/oOAq1fp3rbWRWQJqOuQdcC1Vrdk6alEDB\n5JvQRxuJSDm6oJdNbBjiUYDhpi/4D+/9jtcJrz5gGl6s8VPCulgKOkro276gbZGLSKIbAFhbMCde\nHoy3u5Q+vuh2KhHUR/32OqZ6d2deIYJI4jGiiC9fKeOOyvy1/rZ1c7PiFep2VRMXZKlMpORux5Uc\nAb8wvta6hrToLh5wM48SqjrhCXGANDC04SrvcRM3dQ2RKU0p9BOx02uHPRUJv5gO3KGStjMzOQje\n4JxBQYd5BYa7J8duwQh+cwq0R+OrWGmiTFdITB6hsDCnZFaQieoA/r30mG94PnIIRU6hu4cFdwt1\nJH5sISNKxXAKJB5rnZnI/kMpHM2TAPDlLG2+7unR/tsX2DZSrFHRI5I7MElYHqSuf/cLpHSbw+T+\nOdULS74le8dYep31QEU7vQU6pdpuCAhPO0zbO7J+SgXJ2Zlv9wAjADrwgvqtZt5cheGxhQjFh+Oe\n14ksLurZAAyT8iHgSF7u95UlCs5j52o6QOZeWerORtpot6OVQ1C5sOdgsYwzwOKcnTFoFF6vfOaq\ndzsfQ4q1N0ZouTYJyxfQeQ40kEH6OuM+tveBnaQBWhtTvMvlpkCCmvIzZciSL9YfqD+hjWw5pEal\nnm8QFu3yKOMZH8Jwfan6x13ItxEudp9c6uZry1TvYL9BLupGlFByi6wXP3VO8GQzjLZ/XEVW3bss\nXQ1NTICEyy8EqRwrZj+NQtKIJdSVduugA8aVx09NHoW6AnMcl1oI1heerw46wIdUhOxMbkmckyoH\nJGqsE7om6ThyQE7Z11TT67V85Kdy/YzsPnNdbWm4v2Rzlj83sqgtjJYebKPPsE2GVwzLMieW3YG7\nQeQdeo3h4XeNsTrzD84Yb2HCYhAcf8p+ageUhvj7iPu2S7Igw83XZ250lFZzl+EHAD1Ri5J7X6tG\ndJfwa6y2eR2gjgIhlx75iYS5q5ZfmAlw85BhE+LACGzrPl0J3lV4NRRSV3qyrbQCuh9FI02eQkKW\n+HvpU8bC8BVfIAJF5ccNGBWuqFMgWX4VTLb7+WuUpbDQluuldWsZqb/R+6hSJcJDkHkVQkEV5Z76\nGeHlI1l9hygndQRcUiVrg8yF5Th6e39cSmhnIK96zbtJ358NHjRrBFX0dallZTDp9BRGCwDNM814\nt0LxQ69QmI6CgcjjWElvHWCNDtf579hqduVkVYVrLPPRQm6mrUZqcCIv60F64JYYok2eYPTfeJnh\nnJm8UyZi4mHkRK6oQ8uhoUe32HXNxou5iY44a7vytKysMlrhoKAt6vFPdqV/LpihHgsAwSDdIuUh\n9TTmETHOlQ6xmIvWFApfxoUbzT5TS6Wek6nLomAES2lpSc8joIvEoHbyqA5zZiuyyc4R+DXdsd/i\n+2dnyVo6YDd5JwlvvIB3vknBT1zxe+F9arG912M+iOZr+AjQJNnsCv0GLV2XV+Y78Ess//xfT9en\nOBVRAYYlJ3LPUd0TzS8mumxslmnsJ0oO0t59+HvBn4quosYYRhqh7grIQGSKxrZBtvv3Z3ev7Jx0\n3GOMoPkGeTnGBeeLTF1ImgxB2TnsJTIveJNF5C5Uiw/y1sbvJAKqu/qLRNr8ZTT/zpfYDRuhPg8r\nc42NMIiCDpSELQZFCp2QqJmg/gNgnW++z3W6Stic+o65Td09AyQeLt4xkdnkLQnr129W9Ge0u0Rc\npAMm6S1QsBUzR3tQmIRO86fmxs5ELYG3RwhdFaM6OG1I60mct9XfVF5StI7GcWAjy8Ecd06qimZd\nnz1gS4zEwfkKkYCeCbiNsm1S0AJLpa6g4ZHdigMjFhLYLhZyjVDOwdb1Ebz7I1y8vKbcBDxHiGit\nkf+k8G25rlNKGZCaD9kFinnh8FcPE3Z5mSyefAAJQzv3O5CsAmuGmixPeoje8/Wd454HHYvBFzmG\nH8Q8fmYixeWA8zOmyfUdwipBCTxjiH1FQVxszAJ/JF/F+tzMsJOD/wTsYQoORGHEvrskivSdD76q\naSORvw1NYAgMkoqr2+tKyQZoCRPNaiHcyGuHU7wI4oI6sD/mvNsTmTfGwy3u+vP1b6OkgBOBT0Vz\n5Jx6VpU8/XBj2c3RykIBfmc3ejjQpAaXAk+4TsrO3HIm1ub/YOaxcwizPUZ0YOVS0/yhfBk0l0Mj\nTNqr1/xcbjIfs7VezSoluVRVX6HuJFk4erI0yyu4m3Sce5/6lspK+z2XFNp6b/flNNsL5c1zixII\npEBCsdA5HvNBujIkgM0qAFGgindB5PvIab1Dincbcf75GGappRdqUGLB5ef59S2/OWAkwdSw+hyv\nOzX5NljJYDmUGdz/6HY2nXDeOMF3E1ByDSDzDmlOFM70t3EUHi9k6vHlopQcMSOcj6T40CJ8Cn9L\nmgJ1oXmAn684xPmsCzeK5bOTE8+kXWrtfBl1hDtsmYoO8Fv/VUd9EKPK8U1HLadrJQbUS8gb9f5P\nqZCG+NxvILzcdRSFt9HHH9kreqKAVWlDlH9q/hLV9CZGSHvwULke+/rOo/Upe5B+f9bQ6eaiIMDD\nwRcpHBarm4/l0SzEyaxiSfZ/wjEvt+9UrMb7Kzkt53zV5Ou8HAY74EXWeOceP/3sPtPbdZhaKyfz\nWWy8cOARN/QZxiIxHcIBmv1eiY4ZCJUtUBLWH6y+nw0ITGjFXF7awS6iprBSOH89gLtoLapNNlcw\n/Wc6/Bx+E2JZDkR6k6DU0hKQnDNa5FAqVi8lNePELKHeiP8dKOihyR8DKug0+Jsqiid6Ay/YwPxu\nrIzNj1T16GWUU4Bi3vszR26+8X3A6QImC3g5I+pV34AB5bz6aJAga1M7wM0iGPd5xaLXgn6o6ZXc\njTtt/Y2mUxHluMk40cBLycXqOkUKlbziZvYk8qq4udn+KF7cP1T4Hj9uzzu0iS5Iv3koS99N9zLJ\nvxFs1BG4QgcRYUIIM7X8+gXdXV0ItQp/85DxnKkd91BcgAUjoz2Yh+IWpwsIBBYMGhoh4iNHtGAe\nLWEcRUsM57PkQjCcUFMFnN+Lv9dbRz+7X2eh6gEs6EH85uLlW1b2+sWarGlLEUFeiCt9hNZCw2IU\nq/c00aHGVDfWM/VH5+eRVq2PYHAKCilssT60/sylVk85XcxJJ14NueIr1LBSEjU9S9t0E8nhWKDf\n2iufB6x+JoNvkh8OcoxNWOtwJUPUoUCb/QRpWiUluZo0MjPSpWRaU9Is/HPMcRYmFids9OU5RSnp\nVjneZ0KBfPj7khOmNGB8TpMeKk6gukuCoTAXlGBUe/GVXsWeYS2auRA0JouAObPv8un1CgHH3llI\nMTiKJlXbq429wbZyfSZUFigv+qkpkOiZ0WJxZLOYxKKa8e7V61pzqmJRzaHXdBmXJG9JtprffZVi\nJDlMJgrUkqJkgp0oUZzNQGrYOa5l+BAgABc3INDNUZRPM2R65zdoA3QS2cU+xTpLifRaGWrmRlqD\nYyiHekwamXah3wYj76v6EqTdj/DJHunX4ea3tLDCVe6ZXPspz/YS0UkYUNC4T2exIhYkc4LKArdb\nsBoov5PBFdEDHFFPk/ZR0B6rAGF/iK/z7g9Sn6u5FXS8d0BpaUGI9e3M+l3OjWE8u4FFV1PHBjsz\njGElCL/58kYSDPALRg5kLQUY4exmk6Lx/F97nHWSyi+d1M5WSKErupG0u6VP1nNRc3P/O6LJhn65\nGRtRjh+/uwuxNleBuBzWT6aRJaYIHjWg8iIowlfq1DEXD9ohwjTKTpNV2YKiDDgmua6StErhqn2w\nLUYSe3duFTlkPNgAjJ9P39D2xO2UyChFohXMnyWl61mZf60eJNAS+Yjo7YVLhYRePwWboAn/Fck3\n70nIKD3meeFN/mA2lYBHCPw+s/qbsJ+BJE5WsAe6bFSQzDhH7NW9IvOijzVY15NPvkkwpX0Simum\nzjI2FCcEReXNeoP6OcsZQc1nb6jZwkkcUui1BsEYzeHZTrGfQZJaMMd3tVfqEKLha24cWZLMn6Dt\nAKwG0UmkzpGzSXs245PTsQKkOHWeLHTDm0CATA8T6fAljIXG8qZQ6msht0v6DTJMzqRqUVx5x/Sb\ngJI4Lw/Df/Bb/Ig4UFw1ttNotDq/kCN+ooeaOcxcBLWDMXB3k1MBr91Rx+uj51caAKRSCB+SkAeq\nR7bczy33/G7kM201U159QuP6T8gwYRJwAT5Tz1v+0IdbaY+lTZlF9s9fKagndGdMlDF0A2rKzUuU\nwN1G3aRXsd1pS2/YuQFMA1n2PodrVdriaN+j8N7KRDf1y5PKm00cVxyZD25c0qXS7gQQnN1e/Iav\ntR6qNYYsU4IIU/gXdP5ZM5HObfC+ZINP4Gj9ILmJ3ziKsXM+ol8rvM5e/ugNWqa2DaxQVAsjR5/X\n4ek1vF+aHjvSxlsuL2dCcIsSmEyuWyZyaUGegSLZVWiRkeouLXjmnL0mWOrByW2CJvkPtISTnxgb\nTcRE5R073ty01v6XcI5X6yHaxps+rXRB9MSRc/DAvEmjcPEoA4crC3Uaz6yNDWnOic4IuMdojps6\nyseU7cgUS5ZG0zXuv/0qOLnr8A0U49ex8KzkEqZbpwQlyBOKL84OJRI/WZ17vpQA0lw/vrE7xRKQ\nUu5boz4XnUm5+zXiSNCz78kPyc78a0MMHh6kkWiNQQHO85UQYfwUO7SaxnUaUDe5FlduwLJEUONS\nAx5Xj9wyhzUBR4x4iHzChJOU/87dcUoq8Q6tPEZ15vIRQWJJexnWQBEC6pVjr9VzT/0e9sXKPfqH\nrK5nZt7Vjw0l1zE3Vl+bFiLJDSGd7sOvPJgd3xmZioAXczBpCw19171SeNIZuGMLVw4One95IYTv\n9YlaWSTJRlbGIjfyYlFZ1QxzCqAXyldSEY0GJofzyDBXiPE+SYQStysooTWyDyTYgyDZ0tob4gQg\nGhWiLSd8EVRkECTcWpV0vJDVejxiJKtxznGrfjJgNIcnvzK3mkSSbKcWXxZghhnGKJGPF9kE7Rpe\nuo/4KDX1vELTbhI6O8Eq9Hl6eQWRNHGysxfHcZmeaqTw4WcmCaVAgpXrLvUlNttuZ7JRMXkn52B2\nk71VRYBqtP4q2PUyAwaPmU7rNJE9doHbERpGz6kfOrJEiIBmNgAHTp8HdNzhZUksk6CTJ2R2Dmb6\n1h4axQ3+z9EuanJ5Zi24TUVbkLlqdDJKMuRhTkElKQoOdeaTfmgzvhYnudG6xXb5TDIitdW8pVar\nwJMDCmyTo41jXPZWA4C8bZyXlyX5ZEzfKBlPfrjnMU0hqiA0cPyvD47fhCFnhDA9cMgm4mjcGPy+\nrPd0ElicWXLOj/9ZWw/rsWCM7XCKikLaE6KW7QPwA+XNghvezpYnfLIfb6UVJQkYB+alrSuPY2cQ\nuMXUFQcE8wpdLGykdx30B83vm7Bl6Q0WOyjhE3WCpFDjk6TPls/CacSiLkCHwkE79jy/UBd01Mqg\nqmTPVad+/XFbo8P+z0JEmVi7ag4+TQxeJira+6hTqCkkl+2qZT638CnYTZvbhJJMjB7Zn/Qv03Yt\ntjCa9Ci5weCVknPnhO64dkCjrQSXpiwwiQRc7gRRv7lnjBvqQ2NBfGDjGRr4ZTleGyHi3wjs68jG\nG/dzVuqDBPsSMmdY8KtZR+txSxY0jjs61HH7OJG4otzigbQvms/c6HdjppQfZLC+Osg4hBem+yDt\nlceONkAmkK+GiTaH6+zl3EUaCmmPQPohwP0pf3/KfGUF2hL3nj3MlzPe9UqElS+sj+0/4YUe2QQL\nZs5lG8qqWOQxgE9pmYDNEY18t5k2H47odPi6RaFzkGS81bBUXbdMDhhOob2hM6Vgme1m8tTPzRCV\nCVv855HRa8B+MkMbLsvUIQ73ZX12T8aW2jTWlVbdkRJuc9uXC7boXe5ioYNwbuImOBuprveh1idO\nYvfMYcwoYkVTDBQJ0bRa8SVRu8jIz9C7Tk+4cgrCx5wSTQ5DTApXqwLsj73cJSPjGwQy05ok05+E\nNs1LHhQTLZU9C11bpgZvSXGKa1Kyitl4AAZyaK0kaU2fx/tLcw6O/cnJ+BLuvF7j9CgK47MbmBTN\nmdzP0i5T5zwQennRED7Pc1soXf9pfOWNqj9kIbN927reFyIx1/zQfdypSHGnvpLxIilCa/3G44hd\nMHUb1D8xjhiS/FLtSWplR1pBILFxz8oGBC1txEDlulzkOKlfbThS2NYZWQNhghbRpfs/qgPx3pXW\nL1kwjN6hWOr7pM3hivBBvrRLl5zEjWMukADfwgwoifCCA5GHxihBqDrpihdzC3OexJ0WOzrywWEg\nHSqd9H4miKB2Cq/cxomNnRTZJ6Y9XNQgOISi+A1H+Si2GEGDFYUCkP6b/J+x4q02nUU8Gm/GlLcf\nz9aABQ5J241y1RnIvu5Rk0GLolhJOjP2YDtGnaQwB9hJcavWfv2VwvgTh2WdW80iT6WsFsRLosS1\nmtSziuQosUgWf3n3mpy3sgZyH75235uP+7nSf6e0iLwbyKO3t5lrVZAMiV+chQqV5nGFqEPqxbC9\nnDf8GaS5cN660GhErlukpjblO5D8TFvjsS21hVyJpi2IfiqO16RQlkWAgzU+DqinrbiONRdFtG+5\nsDttkMG3gxACFYDiogW4e9wy9HpX1J+3WBGzE/qMEuzVuE2WAqzoQObaDFAlgQ9yi6WsktBR/oRH\n5XcNln+lkbJclxry6KrJ9iHRoKM4ueXFfsz7u4+j2awLwykl3efojfKHPo4IM2ElyE+goe/BA2nt\n9mvUFyavLetlqE7Z305uj/gg3gPyXdfzvhCEVsd2BVaA5rchICJO337DOzCxHOU+gt+XWEp74n0d\niEc9lb774T6D5DBSKQJbmw/uiKZH1vUa36dA+89Osm74NSWvoH1/4J7nJM+0dFmTo5PHYvNI8rn1\nEjXlzN8RZOOuYCKFq3DLMqtXOcGMAHGDTo0YtqhjOtoiYP08M3TS5JJl+vZAT/CW1nXth4EU1YWx\nAtSxkQ8mqTOJPmiLHQ5J7ih438nin7NKXmTRDfBYH1iJFezaVRI4VRw7qGMdEY9YCa1QMY+a21c3\n61nhA6AZaUOScDudLwVuDxntC0HDboJJHDPP/pAffLYmhm7c9Vcz+I9G9tm4CsVYCFc4QujIzPoe\nPBxJsMVlEYYQPWORFucluAa60Hfps/G/v0CVpnUB12dYL9/FLvLXr5qxsI6cPBtB9Ldj0b+vrROh\nHfMF8Nmb8XkVZ6LHdx7oYFYQX/GpfGYJ416fwCKaCyZ106Yk1fcSP6nRpm5wgdwVDiCd7v9KUBXS\nPizwIAurDE2uGIC+br1kjk7waxZKys15ej0CfLEMHwgn3z1qVIk6g1+kl4QikgdtPyQoWIWZg1Qp\nwmB0jCQvihUI61ns81z2FUUAsw2ftZo9vWYJcX5lIaaJdWR+S7AOSZBrO+lfZhP0pg4V8gBn0w4R\nWp8oOqXU6PenYv6aDI0au/aoe5/IR9Un718i+mYcX7qfadEQhqwfdWjHKljHpoku+Z0zuXf8jxJ0\npY4QSgpOgkv9aXNsqonSvvJZx5G95uusdAI2lFtoZLaRwdp//FA3cfddd1q9wiPgaXdCGlEs1Wkt\n9vTy4UAtxfiMft9ljF2gdJoFlN6jd1hZsUxaYKspAJx3zlN/Mg2yie9jpp2aXyCm2OUPx9GZ3NGi\n6hJMWyHUFzDaGnnIAlQWFMje736UjYn8BuAMDf34Ydw+FgIk4zcnKsk6+d1oDAABoTXu2v7KrFtz\nQgJI0ChR32ewzeykVM5HdcKaEmNTUveJVQCpVuCJm36xO8DHTS2PQOVpndp+O0t60XPYEDNgScer\nvixMS/PIiec6eyumz2pO6GTILyxslsiUB8ij+CnV7FBfzvhHW7qtxSz8EBsuFH3IvM9k0QcIJOGi\ntQMYgwD9aPX8gND6HPQDwdr1wXCjbFD+sguJ0Ng7v092O0Y9AAFVcuQdvoZzfgh8eFWLf1tA14qt\nt8wkjQqfvs/ue7J4ectaWSQ8GPWOyMFZ9H/oxfI/X2HdNRDbPr+LmELniwbRejAE9J/c8d9qJuQS\noFiIyW6s0iPudMMtZvoeeRFifDpsZ86ej+Y1MK7lt7xy8JV4BnDgiap/mVP3FemT59PcrZtNkhAW\nbZ3AIRShZl4eTpLD9vz6sHjO9ggcYRTCdJX1aKg16HmxJYM53G4sINslLiL4M2Jx/4Vco8VQBtoO\nbcHuFrAXXT1Lngrou8dKDdIONbjBlZ9P4yXUpRhxkSsmjPiV6m6PEn15chY7/q2bMUqq51AWL8el\nbb1w3yHwgv7xdvfo3lpQqL5P27S2YO1s11kRSBh1J+w1Kjp81f3hZviG3V9KmOFlAE4yvE4tNOeS\nz8rOur/4POQsGu+bL38o/6xBHVDWr7XclCy2AenH8/NYEIpvJBb6SigyA5pFXcUNBmODAZQeDRFd\nM+1H59A94F2MOTv3NjloaTIQlPfxFsLARmyZHqXj5Qo8x/uX801wwnzzJ6p1NqTHyZ8ecemesWcG\nvsmRI6+eqGNwQUhTiBc95NxXmsT5R5bkQgTHcO2SIDZOzPUreb/ysgdPSAYjk4WNkeObvUVicejz\nvag7RbRgWqfo4sTu4Hyhxt1wegoQruDkdd1taMYFqCbu6zMMoQ31fgYUebprQ37KU7AwMYpto/tG\nLEbTk2Ml8CWpoQe1bl2W9iPJ5SFoOXOyIBiGv+uCa1CzwLLJG3qDDAvU7d4ezYnGh9XenZ7tMr/C\nP8veMd+CyUYaiVQxLozjmgWvwgeuwpxIZg9lRQNx6a1ohwgGD61em7wmdWBKXktw9Z2ejqkWFriJ\nNtUX8kXHZvJ1/PRsw62yMtekzzfaIAn8k9RhXn39JcR2yLBC5yf91y6TqtxlHORPd+YHyw6wd40+\nwNKYSeRyivztAPk2joYR/cUq6TSR5ThIBu4fMb/3uFotOdOonX0MbKrrdZkp/wL/ovUb3oeRacVJ\nDjo97kFXrwFDe+6wS4uxU6ZQcjx5OwGat8+CqhC98rjFNWDqmChHzWdrzmHZEidn0tsVRe1AnWBq\ni0hzF+ipFyAbOEVstCRKsUN/7dEl/4+XzXArODcznbCiKos5AHGbRb7cf+xDvy7WojhzpuPyx/lN\nN1SjpjLKFNF/f7cn+rNh0ieFtWCl1Usswzu87gKw4zkwzzAFQnDZvCG+C7zTMReLkYp/R+PfkiG7\nd0OrdR6tXTVX7GWpWNkO/dFB9hNeyxjh8iZsXp1Z0LpaQ3m/6TxrzdEHRPeYngR/s4QnoxHQJS0y\neLLUQ9C/D2bwqeB0OFojnwhsoAZqTH6rTCO5cPAF9Yq+ThieZKEAKTXYLPqdAYpz8sPUhT73Wtzk\nhjDAqWjrxtNjMQBTodHKsThbDp+JPozU5696xTqLdssK/dM2UAPCCS+T8Rbc1pmIRa5zaRom0Vmz\nK/rSvfPVb3RF+ou6nUDCV3xesktJn2kDEbxrzWgveuxOCxnRE48iii1q5282AMaTJ0aIpM5+jGHf\nt92WsN1IFCqex3y1qLmEF44KSGz/2Lr8sZHEXQp+/P+WbFFBi4doF6zxKMLJ03eWJFM+7wivqYi7\n2EQtEbVgtGzXQPWFbqcZcLPUXrl4Tui6e0H+808ijNVtiYmbtTxdVvwooRc9cAanqpoNMnDCsVzU\ngjMMnFK9/d1/ymm2bjIVuXxVjn4bsMtCPZaplnMWglFfPmHkbUNqG17e1kl0v7w1R6gwk1nv2DXz\nvBvI/yTrEE1DW+h65J7bSxI5wkZAWYORe+qRO6PVIRQfEst4qGI5kPQh/tForxbRnTN91lASY14i\nGWDfDbi1JorSXJ+b+Sfu0Fok5Hb77RDeOv/gMbvWW5ebwo0kPSe/XdRfesBWUccT18pRBou8UlEk\nSdGwNrjPgi37BK/fWU3HIm6MlnGOM7xzja1N6hDiddCRUSrwmsjVLFsVVvZWg5vAOcrAWeNsHB4U\nyFW7fk6bzVQSspFh2uguUggrRYB+crpHoUcPkotrjljWX320PSJsb8FZHOkPxzwQEq8D3LUvtRul\nAQY403DX50TUGEIFg8q/+Z9gCNYRl0yHvUBWZjPiLnVbJ0CzJ5jPT1nTqzIyrrIFgEYm9EHvkrlp\nAgKkcE2568DlFSAKQ8twuGCE5WgHsg2Rg8ERgnXR64/TBZAmc0tikSjB1PU/rT2SysPoOJZP5vkq\n/S/6kre9fRyav/YOg+m6u1dL5UXsNrdmxz1TDZzfN+Ar2AcjL/FOYzmXYiUMOMNDAinVFDd2Jczo\nVWrvq1JrN3pYbyPDKH9FPL2FtZU+5pNFHSLJ9XFf42t1ITRXJxVy1rsCwP40Xpv/MoFhvV8DmG2s\nhQZVA+JWuT/wnB65CapYeGbIOLXtbeF7cXyYkg/VxD0PMxAlIy+0AWW62aUxrzTJ+bVmphPOdh7M\nBsAv2ZelxbSAHs1I/XgiDcxdQLI6I1t1+I7d95yO1sK3ztCYIovRqhNSjB+tmrZFMvlBCujjB7Bt\nDLGLlOUIV8KZr+1F8DtTRwIk8zjsPrpVovEiGiuyrfhzxzyhWhPHs6+mjVzruDb+vCYn34oWjmkd\n0QDd8Y/K8j202Kupi+QNy2DIuz2Q70itZnDcR0U3vi1lx/Q+67NMkBxbhEw6Y0yj5WTHsnKD8XPC\nyeQ+8VhQZ0kuPDrCGFjwvIBIZ93iNwBAQQWm2YTx/8j4jmk6+WZgy1F0Tu5Wy73NQpkRKYDxXSBW\nD5r6hjtRRuW+42AHNTjvnfbpeZDqbYo9iv4sqnNqUM/XBKgJwvBa/hQ+jmhl8YCYNzWyJmg6pR3t\nbCN5sQsuIdtjJVHwWs4N60Fs3UqaImjt6RG6UMAcgzuRQL5pitjpRLJlhjhXt+2q4EKQLkBM6ER1\nD/L/rYehOTZ+ET2/MkTLzyD3fibiUHTmtIP1sFVElgb8GRIUaGJX3D2ame4GKvfYJmJ4frtjHV2W\nElNZwP+fsBhexTOsPsItjnMdAHjsNMVkg4OLi4KsaiNJ537R7zK0ix+TJUJYHFg4nR0U73HAFI6d\nlWBSKZ1du59yyafjRvkalmQFjwYUw6Vl37ubeeMXUyT0G49mCFmOXLalmgZjQMfdog/7rxh4cL4I\nLYnzldjG4uq8VazmQc7KK3Fwp6nV4i79oSNezXk926TXg9vK3DGWCP6/YHbSGfs/enjw8JXhuXu5\n2n2C2xdIn5vxM9e5/0eu9YHwK2UpR1mlP+ANKcgZwc9sTA7ea9C+Rv1x4yJoLi216Ec/4RzcDYoS\nzGT35WMD4GoP1BWQgDdsyknuKELKYb+mQnJLt3JG4vdGJi5ienFiZy0H6gtyIvZb0h7zn8kaMGie\nIEYb/YVeanbbK2bO0jWtCzsLtzw4CalU4vhwubDqcQfupCWHBFyHyAhWLXSzdO4+4yUYZbOc8apD\nyf2Weamz7vRCFhBQpXsk3A6sp0RtvHAikrSF0O+KyrrK1bG0ZesXzhw/y7nQbeE5BE1dhU26WSuH\nah3yN8tRIIz7ahtEbxkHS0cTXU8jy+cJzBx8KSo8fExdh6zHwKcCmtILjTDqDtdR1848Kj2Fx9qO\nyo/P1JGCwAaDEHDDS5pmcJPzjShzqBwq9uX6CAlrcasm6hx8KZ8QKyFA4ebmHvf0BVHtyB51epBK\nKqODfvttAFGbW+SvqFkVNocg8pdBB1mGcMl0WRbvM81tFvPVPYPOp3N6zdyKRWAr8F8hFpR5mk6N\nIZ5SSVjuiLy9tzUy/vA1N+jUZocYvL20dSnes26Jx0VXZhRuCUa2Yh+Xpfbr4zx0mIZU2ixELK/d\nIkELgvtgHlMjtx9jqiWnagCKJzYyj1fXyx0HWdKDPQXlv05ailX9k6Gm2fVG7jPPMCl24QNzse0p\ntjzZ/mlNZRM/0HZTW0zoHyOFt3Xl+5+0q7sNAUik9iJ/vobRUQIlZRef0DUk2zNx/LvfADGX1pPy\nL1rKHTZJj2RxuM6WLXscJkiiNRiHi/sxE6KFQ7K56FWqsvHucttNIbSXjLZY2ceAUBgFKbyGCbFy\noLLNJ776Jd8Fj5b3r/ps9cnxrU3MixzK1WjATvX+TYConRCRjkdQKHScENAjboMWl/2wMoAnVPbM\nzq/iik/qRp096jOXpUmp1yUv55r1Zt0+3txsyi1qhiI8oNyLwEdxo6NQsdnwJ4ZLqvJnK73R4waS\nNXndpMPyPBFEsZCeY4zeW9B/k7J/FQLAcHaJLwOcRVCWOtwkFrBCNURTCK45rPPJHOgItXtF+mpC\nqiZ2AK1MhtXrQRPDIBiWBIHMDYLjJIj3Bt5DoQBsvnKZ2bhsNXAjwpTU9JDB+WDC+jsZqTocVhJC\nc20aVURUEyrYSGsZmRLqsXMbyRZIgxf6JnMOG+kCHMKuWqzv40ix65ymSSnbec+kxExq9YRuXzDK\ns7K/vCf2lxrhRS/vYrWlz2qtsXhv8BhxQ7DqzN9qCWgV19sv5iWHmave4sAMEWkyfvO7ft1sJDUC\ndha752zAyFT+vIhQ9x4rMsr3o7QMq5+FEEcPnuVPEoUAYkAZb48lzCkhurv47CDS6bboxWy2L6cP\n6PEIZy1nWWGvqWMgy0/QA+izIBX6hb0gpT++r4TCQTvfDh4r7bONrb3D1tsiyK97hMbBRFcAgQFh\n60f/z+waUty87LEztl7X8d6z+KZVtiq86Oy3Olqkr5XKovRSdaOmJwpOKRVEdBJKMxn9xcnplAXJ\nabbtFNxdckLplzedP6zcOZ45SrsSOTA5zpHD48j66FNsyolQJHjBnKdTQJWNKLgUfYJiQiGAYShT\noLZsw0qDA+Etf/O1JU0j6iAbzN8WEKAuVvMFo+s+oUDBHXx+guWcgkFlel3P38Ldl9D5bxhRMJ50\noRyfaUUOSMQ5IPiTNqOdTuzG7RIdImyqphEa7KUlkPd92xetAIiFc1BoPMpeIDqh6gntlRF6cCbU\n+r62AyR84zm1nod2FC/aPhLKdkAbAzcunmu4TeSgM2iM8mviHVBDT/7IqDNPRuOjA8/ohIDmMgVt\nCJwKgNvkzGivbCg6ntJPBwnlSzTX6UZBGMfkMJ50X7oGrDXh6bCzxDVufpWCNa6DrTJYWPUzT0Vw\nCIBxAzqRYCcz+u/YfNnHq5x79838geT/+s0L4ZZ7DZ6awM1Cp0y7/iB42h8qCWnCAkbQWt51CEt9\ngzqh1a0/uXYKDK0OczqXNwPgGXGNDjl7yKs+dr5birHpMzXfTtmziPANm1xA4eaHKdQ8R0N9q+Wy\nABWilfAs+a89v4lL1AMoMy0Tn3hxAMSaDmq/egNM8qNScGeYTmrn1mZ0slrY2+NDuB1RYrjA8oy4\n9xQKVv+KL7T0WW6qqZz2k+VP8tYR3Pceh5vhDTcCwywmdH2qmWYRlzShgZTdO/1p3nPdwLBVqIdn\nP1lq7KE4HKjM4BpAev+QKazrpzUd6f7TfLby8fDe9Z3xEYoRAOsEH04tCiIX4/w+TT9IcWnkSxba\n9yL/YVXjndELx9I2Lfvt/u5IplH3AHLwxY13nL56VIqMsswFldTpY2AABHvX1v821wOO3Ro1PPWV\nC/qqWOfMODiZiMV6bNkh6OI7nT+zaaEDLXPCxTf/5I+zAPNjc6XgCyfcTSiEa2qiPMfmV1FURX2/\nl2tQJI0rk6cmdFvNWttfrzvrz2dXYJQmbLnPAbjNbxyQiTQsTwkmRuBH6zioftkm0KgHxWLJaFFN\n3tlt8OoBrkidK7YDoLdLX26IInNTAD4UmutbPwX0mATGEiBWxKFXo/ALzqJZpcyCLz/kFHjUs2bV\nS1gYdEFCbNissyVlQJr7PHJuI6u/aaKhbutwVIIBedJI/L80J1/syiKy5pkQqAEjhYSFe3NK+Gq7\nAQ1/LjfqxzHCzGD8/Ps4I+CVCmYCdmBuf+xPyBzpaA+vT6ZKIv5tDadIvZx6Uj9hwH5QZFu2fDWY\nVtkl87UZLcobq4DLL8by25ra4hcfsSnTtlqVnP3Ec5+fD1z1lnJplHmbxPiaAQtCW8+T0AoD5YRc\nTiAPY9fQd86Od2xXtNrXpTD8iD5Vtzhmac6ot14Ps1Ho7sx8Q6/yRjaEJqn+J3VBjRBkjmucldSe\nJoCyE+olT0Q5Vtn/rFO9PNogJRvqsa65UIb76Js/P6y7KiDFLqRKK8vnAdL2mhKH0X4MRqOGgwhJ\n4hBW4HL/PneR1DxVn6JLiduyZFOWCZzx29ZSp70klj2alyLtBzotH4c1pHTmmpW+P6+1tqW4KjVb\n2vcfPgWXedKUqoJVo8tCbXndP7Hl1nXCEl37GcoQb9u+Ofz5FoSVeHXJtbvPPs1aQRDQYrUnN5mP\nUlYtEvBxgAezsSdY04AHSngt0PrM/7Eug8ZfgQ/z/HrMJEAUjcObvU9Rmj7sI2Cx0s4W1bYusaXn\nx1GfxsLIiwq7LtjI66WWwMyF7L1EIBfOvf6a1sUbzBdf0FmpEoJyYKPYggFsn+Fze3yMTX8fAz4p\nDHNp48KoIs0KWJUSp6ZoMr2JvYe8CN57IDYgzyQkGyCJ3Z4xJLJObKIPmjk07k1L/iXCP+RV+T5w\ng75OJjjCebPql0Df5u3+JGJd6sb4OGYBq8/s/AtROq8Bqp8+CptKpS83bRunHBVwgQfDxHqdu36Q\ngQxMcSoSbdLoR7dUpjVNLQYDCGhlqHB03TKbsd1O/xS21mHUtZQdlL4XB6AkpJ9O9nyy7CmHCR+Z\n6UKWTA6v5zVLkTTBHhB4Ba/G6zUOqKRjRhbv8aV6XVW1cMF0GcIHbwaF34H8KZ5T1wJHMwSavTZb\nsrJYr5Ay/+TzGTG1gLkckLx6DRRY/wQqsiFOMt3Pqybkillhzy3/NoF4eZ9zgWmqQYzNRQ1D/HsQ\nLIYjToDzCHEfYSQ0ykedJ6Wf086nUIY+RE6CHyBK/B6OlaBIo+MkgFsebcMNIlBXFj018CqwlOxp\nC2I3iRa+8+OA89AZzJfDDKK08Fi0hsYQZxikz4q0wixDG+Uh2JhzVojlLE5Gf3oBGPnxlxPlUjnb\nMEFrLyY3qm7j/0T5dBKChwWl42liQAwCOnYrmPPaX0BBtH+iaHSw6KtMzgUpfUHWwG29sgKxL69G\ncoIff0SP00jKUh8Grp/ltyts+oetwKlt8km3Shb6lSF9sueJ/ZtkfA9DXCXhnElbV+oDz9zlpGa+\n5X/JNSTG7/Go2rlVyM4u+p84fmb8aGbid0ujpwVy08CtkBXA9mc3fyfZTd69D4Lt62OqAFFeetLt\nKn+41Xhc25eWu+5UFIVNNAKy1dCbbRclxDLYAB9RWkKVT9/2lID8hBSpvTGFh8NavBe+k0wgBRS5\nNw9buVTnpmNTqGqYk/mCENIzD9r4SovX8Y1DI3oN6P5jJFnL6nCx7SwPJZV5H+gpdz+8+Yumls7O\nS9o2o/Vt0XyOs4nw2Fp1nAA98/1MGmHYcK4pI89eprc1YysoF7+o4s6IOfXyTyehDVfceho8sClY\nEhG3YVFaV6vddZbHzrklf94Xh6oNuxNg7T2TphhHu5WxNRf8v7jWYmMsXhalGCc83E4srYPcUapF\n+kF8cGlYa7t6Ss7EIXxO5kUWzw7Kgz7wpVFlH9/Z6+UnMlX6wrFxYt23NMULOF4sg6CEGagj0X8s\nkcaOAPqjdkrmFdvCYb4etyB4V9ObG+LPD+B7AJREl4p1D/25Sq/EivRMv2FsCdSzIWgqqjtuTvVq\n3RYBSI/3qfqxO5289sO4Sc0lD1PIQNBb9FWAV7lgpqUaiQYO5EL2s6LIlKrfFx376OtoVvBEO+QE\nAwUdM0E4HHXzjSEcBC9Gy74+6sVI1kRG/W70GFaVBiBEnfAsmkGo5QnSQCpQWMP4Dt9HEls2fwUR\nv2CzqHPFcvtezxiwGx5zBLfDhaz6PHh0jaw3mRuH3K9+XRxVxcumwO9EJP3RWtb4t6ageffVSWHh\n5lSRa3SId5/aaSVB/qSColcximYCnoEWROxWQ758XlSrhI4RTW8gXIQNvg94NB1lit1+sNgOXFFx\nh9tRmfBRBaGhWtGXUEgZgEZeTD8JPpKr8cXqMf2o+fCuOgyrunNTO+ETJ5m+PtY3g4HDto0rk8zH\nWCQ60rbw44evFNa5jYpQhF03M8LAexaTvgkBdPdZTwXmCXhVH/Qkf+Ufu2rdoOhwJw0XxIZVaQhg\nOkBYF+pOLsIYwAxri6OIjQpQzeAaj4koEcmJD/b3YJ2x4UNp0/HSEivgQO3APV4Cbv/ZH31AmdaS\ndYsFSWjVsoBHETT1MYKxT4wG+DSUPwqfiPYJ6viFE0lykIAw9SySTh9cme+nyXnFiMbzNDHsrDZs\nXBBrN5zCPdp3iqxxdcTp921m074Wb/fbAP0L4GgKAb2c+OJWWKyjrL2R1Ec6GgIaGK9C9Jy+fgoX\nXvPMTY0hjriAtaAh8zSuetRJ58yYk6piRywo7YkvsA5qu0jVMgbjwBsrSejHYAVn8ROaD4u+thjT\nMu7iLCnEeud3cnSb7eXruUPRJoS1WFF66rr4XDkanYQw/LtlqvZHBE7gQCYPm0InaTha19/c5Zx6\nvwCc5SjZdyUvGfduKiSvb2t8drv4pHce/NWx2GTtxmjbxO8nxfFbsTdIh8J+mY9vbk/Iv9d/AvkO\n4TWVW4XYGbryrmbwEXTXw3m2yTg66lgX2AOefiTPSrgwtdmZP8rNKt3om8KFE/DKeIJyG0LyTYJO\nMaBlAXsiKyUlIoCxcehiZYLCIXPCd7P9+hOczz+podiuifa/m3vuIxhh+qJSxC2yFeGso+U75Rn6\n+EnWvuyCqAV3ZU60fG9hZVydfhj1bRgyRCRGGI3itEih3a6fa7HRNDBgNozvgD60OFTdR/9OgXp0\nH8Pa+D2MY/WwbJD7YTlh5imZkU8OWw2je6ChT33UkQhVOiTCr+Qc/b73gIbWPZ5mPq+KF3Dp/dwq\na9jc+R62EreeAOXnByGTdg0BRNUsbImuJL0D8fzH9hLl+plsB4kcVfCYr7ooh7oyhyl2WUvmqWH4\noS7Ty6pjD+0R8uBR6u/KC93tAyQDw/5I7IQByqxE1yFirYQD+VSqsZW7HKOmqCdYWdtXnAXNgqgl\n0c/mn4MEdnxQHM9LcJlIn0k4v8K92Eu77YKjgZIko5loHOhrzvD1f+KXRcOMqQG0QGmSkNo9PzGl\n8t8qy6duv9w/cHjUxSYGGTPRpVX6QEEU/62TgM2re4r1m+YLD80Xp1+9o+n0NRySwdcwOc7Fx99G\nv5M3Y0O4Bn22QTFYKBhXLwbd/gvCK7v8KJt6fF+nvssKzUdVoBM1D24ylXyQwYZBpTOl+VgyEj5H\nKtJQ0gP1Ml0vb3YFErhjc5xKI7MeNr8F8QRQR0ZX+woEovQDwpnH6rdOdxW3HyVb+sR3OzprIDFU\nSU005ebPyNPNKJIBx2nIvYzP+urKBR/JDN7O4s3trWui0IH5pC4iwtMYxoNCktHvCE9M5B0VwPMf\n1r9AzTAR7FfbERqAKyFVb7VmTgehZU5I1IgYIjoUZNeZM3QINh6Kf+iJSat07rszmxNhgaCvJ30z\niBhfm4jaOeDuRsoS2v2t+gfFmp+TezZTk/7nKNby+OHVhQ4Iv1va3aofvyhuwjBPE7CqOtMx1UPM\nVgwMf6VGuIi6uIYsIUrXTRBo7rWoz4uNnj4XYcTBMBP/JqJEuPc+Qfur3FVQnWbjoZ4XhWjiFcm7\nVdFKSy53ubQjt2vLFsDRR6XW/v9F/l7PqWXLO5vXQ9nglJvS/9UK9RpSn0iVK+n/PPxkONKP7Kzi\nYDxhl0vOEuM80EBrkhljJLHcrUOAbbFeTAXoIhLLJ0pSDy3jjO97ipXlcs5K/hRKgMsJfIb81dRo\n7H8vu4NGwXUDR492ueXsxSh95sm6wW27aS5HIt3SsPEd6GCzmzYXwsDb4M72Jf94If/Tf7+33Mjb\nSVSwHAKdLqIhcpBOHLvDU25iJcuZbRxVJmgSiaOH3pcJB6M7ixp1CqcLLOVB5sA+jQiYHlx/2DdY\nM9MSTLi49xlh2wRZ/CoWxf+IC3dwtUVgEoWK3WGXgVW/UdfBQRnVSHP3jk/Vtad4QHT6HjzTDa1A\nELUluHUgtcTi85jG6YqmPmYZH6sgxE+qhaEVYIWpocDgFVZjOEHQdNMsQOicsopwvtLmE1mWqI+D\nm8482ZhsBYb5w9PvhizrK/DLM92jMpGV9FR0XMAYG/iyYHcaBRJBrboKaaau9ZwOXZgpeJH5ckC+\nNpNGuOWTGXoYP6M45Kd4XsxmDjJ+KOe4pOG65fEckPZBYVn1ZXFjEONARQeHxi/wuWKEneu+u8Cx\n5oDm1EnffZAQBP0mLIDf54JS0PFSehvaLgj+tvuXfZPe72hmi/ryZu4aw8IHuTw7kYgKBy399fKI\nYotjpUgwtABmV0pnh7zQmDavTTzzgYrlsxVWPG2mG97cP24KMe1OgCAX1aVtM7GANyGdhUgS1YS/\nsX8ngB2C6kJx/E0gkaLP9LlBgq9HzOSDWwJC/X3fTl2N6jXNLQp6ds7WeACXMNCzFN2F+eiYUidw\njP0OlzaH5/dJQB8Bh2UQTFg1TRnWRimRaw52YHJwYs5UdUwmIWDbpDWR45Vbw96kDzFCbaxucZTy\nwlF277dmUBh4G/2ytz2t7ziuYabaOBNhc7Q1n+avv66ooLnJgsDYOfODdxLnDzji296F35mslmD1\nPzgopoiEV4lmdoc5hgCmrskvxxEbS9Uo1JXDAwnN1xPIrdefpZB922ovdXWIWlmipH8GIi8Qyyay\nJHpWlOrCtZezLpziZLP5b31w0W9CXmFN7VXAkg8QRJjElFv8Bwqk/ESJUrJ8+6vX8qyS1peeTqYM\nuqruK6f9ddCZDi+ezzeS1lXYuagX1PppwfnsO2qatDbGqTeMxlH9lnj3S3qo63Dd6nlFlJaVSWei\nAoYqZji320UGbnJcm/7WII0Bt1W2TH94XfEwTolDHPN/i/xPfZZKllK0kSs61C69VteCqzjkEcJd\nNOxmyzqOck04IL4MWsXz8PBKz4jXKVNUPcLUD3XFP8CO/6ZUbt45sGayX0B3t56zeKMdodpCr/Lu\nCSmZUeM0Ab1Cc2+Nz0IyyO2YfF+++UT6AifyTgodm/g2BLgTdKs1017k1259DFYaHqYTMCEoR0zq\nh4+RUZP5eCmjoR3i7VZP/izv4fKkNVsH+f70iM1MvxGxOFFsI9eZyrd3JcftiMlR+hlyXPoIydOp\ncF2FVzoYGFFKbY+nEn42xNx72p/eDRqXedseKp7apHk7f1WIic4TeeLf3hfvSzxRG4Wg/vS+fSx5\nOXDwyDLuEJ5PbptrrU+H6QeOy/nVevr4o0bb3bnrl0+/srBaZ4eC1qG9T6MEzpEHaj6tOaW+nr/G\nvFfV2EH2iVCgngapxBSaa45f9i+WWy1/P7S6J+njGQniS3p2/hfg6FNcO49nWCeTpl4dT/ShBZFn\nzsGaErvpVccylegsjWNMkKVobqmiZxzI465E2VtHRMIOxDmPgaU3EYElf9vDiJ2vOQ+AuCoE+lHV\nvUfTKjOe6dSvcTxtH4g6egIFJZ2WnbwVabgoLctSd1EiSxPmAKzFv5k9m7/yZF5XYmswwQCoHexH\nTFgGpYfEgp0/8oUPQ2r0SvSj46K7kexRoOWY9uFVRZ3UqG0Rp7f63GYzxE0vN4xr9nE60ExSEvSD\nNUX6WETANa1IoPK0LiwIzGv8q4ZIyb0gtBzrNuBpkYWSDfMa9+Ys3u/JFGYHEHiZYAtHo//rkcXU\nhaMI20dm5xIWn5aH2SIhO8SI2Kui5gpcDPDoeDvyeWM7+qze5HJEjjXvXfAhZLoZLsS779HVmZeN\n6XmNY2JN9yuWCMtT88IHU5mI6vcs22v3yzuBQoseG/EIIhqLt4f/RCDEE7Rfw6lbE1TUy6McQ56u\nddV39pt9AYS80fP1SRfAsXopCbVeLCjUPfk7cSidVwOBc9lJO7g/DykRuxSR+Zrju0Y6uhtXQ936\nALWJToaYxU3+DhhBZgjKtZ3oVoCmPXBQmBsQyEtues0ovTKmIV+NozPvoJ5ebUnGw95/CzQJ5L57\n262zJI2+oEOFhQ756V24HvUUz//UjijoMjrPIkjv5667bE5cG3miq71aKmjHLmAMWoMyhWn32o9Q\nFWSs2aM/+wBKN81z4DL/JCJpZFQMpG4v1eih2irrB4/9Lpm9AlZjpAinZC4eRWQiRem5gV2r7iDu\nrDB2bJeWQT3l7jcuwZqrE3Kq4XOw2rGbVQAZaWfW1oyEiuReaZ/0f/0mKOjvOEqFx5QHV/nVo+2m\n4vMtH5pw6qz64YqbKzjc1CvAIsTTa/dBHy0l6ib/sPCEEp2UJ3XYLY0Edq4VqQ6+2n6o9RskT7Ol\nESZ4cvxwkuXBEJb/wzuuPvBGgsdEnPgG+u+vQoRQ1m+nX5AlZHa6FQsOA1kts6h6fPXMXCAt09hC\n5ffbKKBQBG+3rPf0LVZlVS/dHx9zoYfAkYgv370/9/I3sPMZHe4EGLxBlI7P5j8vazRPQk7eyoe8\nUASJqk0vHXGK+KM/ufgHicYdL2wJHtJyI1wScLorko/FbDyzp3SXp8j173/nUh4rb3sVjZ/VANTl\ndvmevOqMurK57FN+wd56CGkxMynBAkpVovOZ3kroCmQZ8ZdX5GLSIheoU/E++S8u5qY/TG1Mn9b5\nceeNVr1SzzujGLJXWy6VHu3MO8TDr8p/CDdH3x3iUuVY5LI9AVrkITGTfAnlt3/d0PsHIvYiro0j\nUq3e++5lOCuhgP+pfNm8piRwOQ7xsigPSAj8LLX9WZxXXOwTHUt4ASQu04qr5o5lasLtoBcVMKc4\n7I97aki6S/B2onxNtERTaIIImyUpD3n1lHxEdpSzqV6ePuP2k1C4d/w0m630o/yvFL28VSgHirVD\nc+fiiigTWV9b+Km3iIyb4ITZY1FgtMSBdf5RWwpFPjYdpoO7JMz4pdn9jLpkGrBSTFRxsk8llyc6\nzYUZ4DHUklDnfFkapjUwoauMWqmC/Ojy+22Xf2C1YKJlXw65mJGplzWyTf5GQwHR/FvsynYJZWhs\nK3aa4KqQ10L6J/wLtYj0gUDWbMVfmq9zYdZf6q1Iks/GKL6KvZO0LnPqKJBsC/TfETMmvnS6/A6z\nzpp4qhzbxj32rksVR1U+hIabRmITf+gPVRN4DJs/w+qnY9UvYg2vNWTLuAhovQUg/huxenZUfVoE\niL6CJwm2bSNaHu/njH3a/VFg78X0dLtzOcE4hvRTMyJUbXJhAbidZeDjwSEhGr79L1IcpF83i+og\nfvWAk6AKXSjIucfa2db+KmrinD/vncFYDPFcmXu3d6lw6KKSMm7R1mrDfbhgGhK/kb/iDJBZuFGO\nMg1cjP7yzdG8vxWEFs+HApcKQ3i9RKJ1mLtAYyo56NlL/rlhQOa4YSUpdeMTYyL9HAZ7WGhkOYDy\njmUZqxz9/ypq1DOd+d12f0ysjFsIOV7IDw4u+guaiHh+V/wwBLWknV0iFsR341ihShw6bVKlv8Vl\nTF3iI00KELql/DhUb0Peo9JPcloMydXRDNtgQfQKeGjPji1vo6cOm7xzKMk7538BrT0alhOchfYJ\nComC8sLB+QifNbGNdczr466kMN5nSABqQbp7gUhUnHxNEH1gImnBa5/yBDyRMDssuTYDmckCKgRb\n8xUclChBWAUQq4i9Ae9rJ5u+aoSjxc2wQib0DPplaOddE28iPJ73QusoMHmPHeLz/vJ3q2l4/EoS\nWU0pZIfcqcStHwYiDNVk2+EAR/BDVOQPYGqO4vPC8qAncQooi7tohBg27AJcZR9jodif6+ZOFjRv\nkGN0HSEMzObzmbDVrCvM/g5vD5a9ycUVAkrzBOFib0eZkh/CwADtq1L2obBgF1M+XXpnhaN8OpNa\n9tP77Zgm8vSj8Lw+iG078mmYCYsxn/qg+FPy6gPnfvZ4yvEEctGzzumz+r1un2epJZHeHKH+PUEY\nNCCF1FVnK1dBmMVLsW1geEORwe+cagpzrapmRB8mUxab0IGm9LaFIHQPCgmvza/I4AdXnBVHPike\ne9gQgPFvgTX0iQ9W32VZVvCqyLQJK9tyjqDu07ibodzyvYzAia0s8m/EVSWxXmps6yKA9HJP0nr9\nYMQWktGbT89FIMK46d7e6dtipOy+JYhIkCDwMHLgwknHhus5INhoBRaR17gi6Km629xxIiniIzlx\nKBA1+wkeRwoG8mzcugiGqOQbtMj6Ik51/9rEw8PSOgppXC/WXPRobwh0GtzRupY+kcBtNQVIRxAH\n8g4lFd6YGYrcmSSEYVZ8GWPEZP/pzuLfgFsOCTnbrozgKiIsMDm2UY1IA6HWkHe1byTNprhO5yov\nqgjtILl4ye0y/5Nr50ij6ovAultl3FjsJbPY7DpKHozi4Em5zJ4BYJhG1lyFI4zCUc0MRhh+mG3k\nUI822j3mN0HktsaMXyd/GeBhBb/bU0Hu3L+qzqIySWJt6VY+1/PZp4gMj6SmDaPTJ5otI7XukmtI\nDIUycVzaaoWxvvfqjhPiWsTpgCXbcIIpthqlJRYS1IOf6GnDifstO9jq/uKZ9RHul0ojKJ6vL9P5\nXy0WVmkaWiZ5VfXTerrwU6oESxU2r5XeTP5oj6VbxO5nUiuRKfxPUQjGp4wTEYvX5DmK95yIYEkw\ndlcMbHxCGdysnVyZOGlWF81VFtY8h3zPmqvIBADAacJimA+2Gb9n20x7UsvwO6stOGnDrWpmqhMs\nv1EJd95D65UAiotHKnv+Kk9n5oRparOHRD/uuxaxm4G6A+4C4rGTczDiWsVVO5N2qQS3HW5Tk98J\n5qrVj10k/0zTNsW5kLEd+SyEYUD3NxKX8NV0BADMDknxkv46O47uMybkcWOe28y2DkAYxf4pAt5t\nOPihcykO/4AodeKpdAqeSSulz+S2EcXg7F66wrO6MCzdOMwNKkBz62mdw2CZCQEMzSaKPinjU3gt\nEC3BDWsKKJpJ+ZlKIHkVhDvZExQ7IbmFbqOAZnRQAPzEvAdzmFx7Q6oEvNCCrj2uqgVUXyuKUOa+\nSZUkgnzz9aZsD0+Ly4zLeilxfQMCOoopoREfkC85S88qh1OP3eAg0qGlwDm9QcDDDGB/tUKyzdJw\n0SVHWAfBkqNjdxo9jHKhsIn/qSXNmFke96zuvJE/exiJlyNrrbmgMxiTFag2PYwrVClAb+RUJzP5\npXa4jPI7Q9hw5hziAoeWJyGIGq+ZwreVpO5JIrAr4kIZQw+74HyMbIwBR1sXJQunl4sQNClnfv4n\nVBv/ybwVnfThYhydsHz/bBx6vVTxkAXDQw8dUPJj2xLfftemmEGgK3pUSrbNsi3Hylu1+RJqjCvZ\ncM8xvZ8Prm/wEzDFf+79sj/dc0nEZ87VkrMzS7ZVwXhWsz+QvezNSlLWXXrbm1lhRpvVMEsOm2A5\nSN6B7hJqlgK+W4x8W8Iu7f9HeyIBVOzv4LDh53kySd20koR6aiODqxaggr+TfeiUyGbpwPSgLV0m\nmNz1OXvvm6hstNaulL+FjkrEPAQ2ErAU9lMBwrZoxETA2Jninewz2AE3iIHGYB/dyXQt+maryng2\nFDsO9Du0J75Fcj+unEa6jctULwMtvZu1xt/azLPAuS7MZl1hi27ardF98qM4inazxj8dCqLbT1s0\ntU8+9qp2dDqUM3PTu+IPIXmMTWwaHnHOlezflkU0eqEKY7BcA3Ra7U8tzBluUsZ/YEPkcXbJ3CLl\n9SlumAs21hAJUMPcS/5GICkN7WMQ0UJakuI9Xs7YjniUNbLVqKTNl4K5/cHu+27CrGS6SBLswVx8\nJNU7g6ehNsiOUC/k+QGzavSfMApXReQluEBTn6Eqta2zwgx5Wnu8bf5DEVGvvIqAOMDAJUla/DyO\n2ILkew96k+kdB6OgirkTujvrhL+dn6TxoaCUXzH3p/fg2LZwXHh0vwDGaHgtBg5e+HqiXR78u4iS\nA+HF2t4QLiWuwzLhf+6JDyABe6r7MJt9UhuGGxK4f1CBY3n1SBu6TVte2+Zr4CphN0/0ODQIJ4+N\n3U/ET5yhNxW1HA+wn2DgYX88O7L9CR8oG+cNtZUUYgBgRwZg5zkY+zOCHpUPMuOx2ZO/yYQ8oOn5\nRgBMF0xgan9jz9IFvJ2pRfaZCDqobaGaaOkf5MlKdb20/NfU1h3ZLmxgYUbuHVLIn9heftX01a0R\nH5YpkmfOTV9YFDBvCp4WUbdgsk0dYwaw6ZxhkB+fxcIDAdvJKjjBpKSbI1cJWDlpNYdmyEuRdyUn\nDdeiJ12JBqZwLI7BG1ShQ1fIes+j6XQpmP5YRo0ZK3o1w/czwRkuSWuyChb4TXrt/BoV8cZvxPZE\nTFFcq7YutkCEnSBpf7rf2pOrKlnKV9xNMWiYbwYeUUkvgbhTBXIq7ObQpaBnn1A5TbCzak6+gmUr\nBD+0SPeCtytj3cO69BNBOH0j4R9shUk8MH0puUdsS7ZwGa56C3ouAUzgV1/tWApOk4LBQ1dc4wMC\ns+sWHw5lHP2I6M7e1JF8nqinJinmJw/dQxgzrz8Zb7aujsf8VXcMcyI412uZOQOePqGtyEFOEHwC\nRHGLafSYAIdgEaNL3YEWLWurqygo6iP2Zk+4JHk6hRDYQXmZ2Us6/NPmSSbIPp58IQpNDiGNkKXh\nX0u/kzorNx1Ws8JVgSlUhbTZw+sCG0lrqqk7EWg3x9Gf6jDIUYB5fhTZPWTUq/sLiugHaYZnjnVE\nwgkbbs+W0Z8EH/iGbS4V9qnoZl7qNe3QR/YA7TgRXPejzygAGyNgx35mW2EAMPPB5JjnIVlNylX8\nKO6+s4ewNDg30h+ASVPszQKM36BB7zN3wGcOcHvy868TFNyIFPHS9X/+LIm/mTRdfbFdTejpC3iV\nmLWnZwd8FmMq3Jhz2+Fin3knUp0JD0rxiANppmUy59IhUsg/Hl668RzTDf6r0GQJZj+0qETPEYax\niIf3YREfcgD+psMJ3gYBCB62CB3JuCyymYtsrtcEU6jEmp2lPPAN7Xq4aJcP6jrWNtwezTttK96J\npdQyQgD4ufN9AabK5ILebqK4MJGWJIFANCMAkNJ4QoE7IJ95BoK3b8UzhqUnJ9/jRbHU2/rBRiDn\nYHqkxyDpJoFsaHoA/2Iqlwe2L/+rBx2W0TSna5XZzs6HAx87v40YVzpsZf1dztSpu39IMDyeCBJh\nFHFclUU6bmdjFS3G0Lvv7ZPFzCMuCFl0Nb2iDTKAnT2lek4cH/LJvkOuzE3niI5yU7h/3yZPTX/T\nzIB9JmuXTaYK26C9Emh3bKePEWGiA0OTaaHBYdUtRzocHwj6jN6wotbm4YNERKHRa/JwMhPmXfyO\nmyI9CjO9qDFiH3CcgmBt/EW1MsKiC9df6PleAHkwQv5o9D12KHxgTOpyW6jNNKAtXrUHMtcTPgUd\nUiQNTg2zozL4x+f2BdJmBsuXsd82JjzUHqhWFmvARsowh7Ov1q+tRj23R/1OSdYLO0PsUvle/Fyr\nfiPjIKIlkUBdQweBr60ZkBXEUSCvv0udj3cpoIbRENT/abJtEy04qt0BXRGfS4w2rSB7FJhDoZ1m\nT0SDOBqPEeUS3TJE/rrqbSHtX1mbwrlaMzWdVFQz/m/ETHcjmIuHH0ASBGA718GcGiAMINS4HWMs\nUvXSnTd/qbZ3TSlWlu1Bq3M4lMe4ZC5w5FoRKGl3SJgMX32/sobtqJ7MsGWhhn+mfopMn/vTp9ex\nuvK9/cWYP0OOh72i/Zk02QTI6lLNYBeTHdnjyGQ0R6xzaaa/BPSHXYBSuAXqVGxWO3G0IhwPoNqG\nH7LAoe18N8wNdVZhQQ4XLstkJTQfEPzWajpD2+kn03IM64klgxjLCacq0F8V0UO1seKu7Yi5Wk8v\n004VTSaRXdT4RzJCgH+4CDlCKplgDEaf0l8p8CtWyqwMxcxan8WKAnJZQsBKwQO9Ryz1DGR37jx2\nM75Kr2Y8vzC1s+7YdjyS6X2N3/qnpWP5k2oFBr0ZvpQC4nKE389aQ+8oeLrV1LNzVzgwoZeTvVy9\nk1UNWroADH21qspftpqA2hMIxfq3kKUVKQV8P0CG6oEpHK1wiEOoNNdPBCKvl5dkqNQ3WpS89GVJ\nhu4mha8kd5202kPT1tDoHsyoA3vvPSvifFERxK0jseY5/ZiC3tJxkGoAAUgWrvmp0LWixoHser5h\nx3J2AKZVj6rTKDx6/mwQ9feu8VKFUIbYvxtZpb5G1y2aabXVAtM4yO9Es5dH61gvh4PMDTYqxFph\n3RwRI87oaVCIbz8o41Iap/UsngJU/QqVX7BrheCz6lEydOa9DAI68nQdSbcbEFLXwFT3Z5RStc25\nTmApdJjybNP5flJ7tRtpi7qxMy9slr+iYZVqFWIVMO6pt8xZX1RchI6XuKTzsn26dd4EHrG21kae\nlxskyV5esa/HdAYu4T6zc2fBybDOtTi5DLdnjs4zq0nVEZvAK/O7hmNuQcXYNh9FbKvJirPJKlh6\nPppx642gHR5Qh+rzibVkWZTf+6gLS24z4Mf4YbXjDJJ47aI+8ok2a3vrVB1wMNVoH9WGgL9lwbLZ\nTXuFMvReOscE4jhEQNF/dsYG7SU5IZmeEJSPSqAMKWyi6xFGV8e/6MAuhOQJSBt4VoJsmnzYx39N\nPcOzLAby+Qd5n9s+R+6kOm00dJdpnDlaHsUnN7owEalVYlmGfVJzJH2WmJx+IssYjPzh0/QMwfo/\ncEhCLHHUHa3VUhJDhxeGlS4TmGaP8gIDHlc/+Y46bA446f4pI2QVafyTjyXjoqrdA8HdeOD0AChV\nxGwBw4itXjGM80P0u4Ta+OOrC1lEPDe2KHbGbxskktKBT6T5Pj1ogygYmTmTEM+r5ZlDhJxid/XK\nJ7xL6XZST0gLowmTmxBummGCAS11HiEtzKvYW6qBceAZSepN2bL9vs6kbPDj3UGRnlApVqrgvjDz\nxqE86xfmqylNh6SY+4pRcjFumWB7Hb/r4mR4ipji0XmSBRR04X8GMBFc6va1NWR5Y774BzUcKvNE\nHYrsHAMw7hTeeGCM8si50H3cQ0JFZtNs5exuzOaI75vxSOvtDORC/g3LFu2TWo7H3LGy479ccEus\nviVdVhTZXaOagx8yRbIDmV7e3IEiCXt/ZVJPPxkt2/1oAMbIsH/AZC7DY9+AjOquwbL2Hfv0D6co\nqLMU6SI6gVg7r4gvB7hhoa7lmS+qSXa0AYaP5WF2sLWDPDLOH+WR3BqvIlJNU0H3s9b1jyr1zogF\nVuufcBKraK/+IlasWz7Zz2u50mW0oECjbzK2KWkuaPsAHBQytX7bPdMfNfGZchKh1bJA4hlBMoDp\nXfJmxVx2n8wbXvliRm/q+DoYpMAemABAYoKdxGQlm5avL32mq48L8dkB3ZYVOApMiOXCF/2rVrUK\nSKZOVufjUktbq+tfN6Wa+pEofGDu5I7ScLgIwXW3pa+rGUPrmKJ2EczjB0mE2QHDWBiffazDjivn\n6PqAoj7ozh4YYmqSSNsBqLHm1uoYAVBvSER+Rmi0mIEu/rU8QZ/mZxnAmCRIx8ELSCsfOJyLtryh\n3B0layR82YtpAmnXLk9WpH+P6JZa55T+O/It2GJftQVkG9xldkWM2qEjHgc1r6mXqGqCsm8YhfQF\n2H8EQZEM0wLp0EJHPdYcqDj/zHOxHwEUqjU1/mCsV7TCKeBCH/x9gbwTUU/cmhnRd6NVjQFKPk8b\nb2pI+oE7RGb8l7162S1Y3b4QCE+/xJN9jH8HB1qn25OlPw5Y7RLlBGY2LWsRsRptWdK19BXqEjQq\njnJtKnUhdRX/NgEFWrpusm+OUZTLGGIkrqhmSt9jsoDOGkk1lYaH3z1trWlsWgf7tkkoCam7uINg\nu1+iT5YQUHQkVLmh8rCgHs5QpvKUBFz5xuVuq4aOMzt8zSJcPYjiCeKVtKHxVnJWL9JtW+IiRzks\nqNfMQbf/GEyfoyFhbO1uwHik4bQur531FBHgPmQeocphfezMPjGRg5aOKi5s+QwRE9J6+Hw0R/7K\nQU8hhgc+ceZz096CHRgfrOQwd1j6lexYDGNLSTHVT7kuWyUzVYc3S7H6HrpLbeSrPBNKctxwk6KH\nm6rB8+4xbhjSAF5zVqpRFYllzQ8JuW2+S2ZeuDB0KRd8InLJcnArE2egq42kGzQTHphpyUXmgJaV\npTMjLVdw9LyF6jFH5irn3YFb9sSsBvyzDc3ck41X4Onu0ZAdXPgjBixbnzGzesObeZzBv6xi3cG/\nex9w4TtFdLqNl4Y93ou5Ee3akX7xPWLoiUXGwn/3LVVuoG22SY+Z1qQPyhV7SG+g2yG/c1oqDzyd\n7lSsaUPxlRdymzdzb4yBKp4a27rC+Ypp4W36eBvQle6xcmguhXa/7PhhbNQ901oaiJr9538PrHd5\nByVsaE/7BaxO6IFg8PoRMhO+NUF4JkeLDnXQ/ppqBCCdHeeRBMQWcAJG+ylUluUjftgLi3NyRVFN\n5NSM0ULDf6ZlBpRKA9YnS5n6OvHElXhrBQ0Cp2p3j3o0XvBRJHi7nUAYQUMeoDE/fukFUc/UTpcr\n+ifOYacYi2dalmQOQ7khw9+xQLkKnQo8tttJJQJFVWfPuIyFPUTnSwK9gaMXtFInJiTfap3nxO/7\nvTtzXKV9EdlNy/fFhbHGyXsFB7cFioYODz5Jf9SKX2KxEp6w45N8IVNqJ/w4B9UUIN+IO457vV0a\nWVWT20FAarK4ePLe1huYPU9q3vvNQd1vmPhVQN+vSO/4wr0oqaI9atQSO2EUfMqKE8WajvkySzPl\nG5gYr4soguIdzoh7brFLws0gFlSCg97RvNP6xc2fFsJAxDCj/jZMiFLyogWMDqTgyM3hgkpklF93\nr27ZaKFrVk1OR4TYc1GBRskttTvLlEWoFJq0JOM3WoFe1pp9frJFKR2XDG8/WevDMktfozvEcv7g\nEIJG/MUbfCdiRcy2ZIrdWry6Zor42LEJndUqY9eeVqfVeUqg3QQsD0C07c+lZbPY6e5GSiHReX5g\nUA4ZDlLJu6pmRM8gPaOKJkALpfFmMNi8cMIZ7DXDeOst/2hXclBRPCNu2H+/pTOb0Z5fxYSyZ0Vx\na6lH01w14tDQkPSED1CaQBW5uch83oFqBNcoLR9yMYYaUxwVJBVTYRhm9eSSTiDHB+Tl+8GScWY+\nzhhVqwr9aTSxEdziTQ6Ge2B4o6us1TMZ/bGIzRbc3mwrhjbCnO4tVISu5k0RLl7a/aTZe+rn6sHU\nLvCc97lNIXNpTLLqHOV3Y50FL00Km+lrL7CgaDxofGRR/hQlMHSJ9mjRWwmBpm38Llr/JvaNywt1\nZrRAajjgF2Vn1ppPX+vyYY4gdOYyD00gep/ZrsUebuwizEbvVLLDnrIE4PMXJqwVhN3Y01YYhbde\nBq9yh2mNoCz10CB3/7djVR3k5DWPd5ZOLF+h5jG1WkftNtY7hOUCtx5V+XF1Mi4qY916g5hLEvuk\n6eQac2eSR2EuVhclY6P+vqTSHipWsE0Hchh2Do8wLQYRMkPazynEyg1Fi6O/5HwzMFgNFmK8fqZ+\nUQvUsnh8IST+kmElMzVCStI1b9HeuzCEcdkWY3FkWC0RAFb2beIoL/45AqGiMR9WNfZuG5boWA9C\n4M2oI1MQnfuzveq43jm3MokWLEqkNcbC/QKbT+nOCibepha9Pk4pF5pG4LJwfrSx3pwx7fZAqbba\n9lRVTKmmgss4czFNGY8BjhqyHyBXss0z0uf42lQwpWVvNYsuz5KsEnEOshvaEyL73pMmQeYQ3hry\nCmpIsO3OB2UTS2xpElpZsLtETXqSp8n3xHPFIHLQf4lk34S94GEaZSNwuEGlNPuZaqtg6x7E1fSa\nXEtmM5yQvbOL5Faumxb/QF5gFnsezH131ftE6AVr1H+ZNWryS6MBKwENQPVXn3ZPdLHS3bKuHoOj\nAvj1G7OQO6O16xolwm44YDitobJq7FLp5KUHUfrej/lxiIQHl6KjIIfkTMhgtO+Kbb9V3TA/vpv+\nxpuxQ26kQiVB/pk50+VQdGtEtlXVKrPGVKb7c1C9npaxynQMjOkFNVZd5vTY1nfxJpGUyZkUU+Qv\ngOA1anrJ+zdRKt1YLy5vY2c+HV6TR8DQKHv1sbcIhkC9LYjIJyM4PJCRs3lRuXaFUnJjCLokz6EX\nAWaEYhUM/pMnlcpKotC7zJqmAsJYzjh6JW4ffRCdhrPTr2imNNDNC66I0u+hlJxAGgD6f4xKuWBF\nWLyhSYvswD6N/Qf7ZiAx9GaXJpXHyr5A+y8NsO3tD1iJ+VzG1X8P7cupDVOe5LFnQ1iWqkUF1nmQ\ni/pZ86+J+FoA8DKR7HGFHA7udfIluhGQxIDoi/lffV85CgO+iW2P0uTNqQbrRB9SSe5no7h7Ltf3\nhPSBFtn+FD/5wCJyyftpSU/z9gYppWaNxilpFX3xOOAukfYfwZXc1DBpfb683QLTSOnuo2IA+Oof\nhDJsRDUPOzKXVoHw5b7UfV3Abo2Mbll/hWXyo7RQEsP3Bfa2umU42hH8qZ3hlGR4hSoGHkIVlHef\nFJgfGQLwhChlmmoRIZOvYiqUoTYLQYVD1D/cKDeVlCbxAnlPI1D3PlrTJlbdDsPNl4ygtnJnUG+0\nH0rhJnlLHzWRlPo635vGvjNOES2cNCur3yS9vUROgRB+efzTuSEr5jKafwKVlL1Uk8xziFNz2pTy\n3D66kgHfrPB4xNnpV8yeUzmQp+DRq1vMVSHjcecmQgMKIebg+p/okYf7tS8RPVbWtHL6XFhbvmL3\nshvWN1WMXylIyjim2DACHWJcE3IoFImNLe9e4SVBrIw7I44AE8o/NRfiUinq8iq1hA5q6pF2Sr4M\ncnKmyiHyF+e0SjcRV+2gwD2fLePi9MUEqx+pajKIu3j2fdqo/BtZs6IZAnYbyLbs4pKJiOwy13Uw\nDi1xB10ssVldkls1CMuu4RFczjU/VMbJaPWQKW/0aSMq8lELEwDGS5eddFHftUqp+nXdWZ5O0Fki\nXhlgvNYJBSjkN9l2hLFIdJjFuUj3Ee2WNSDzUne00QlNb87o/sYFIc1HQOOtDJBdgFWkQDw4Sx2b\nacVvuvs4zIdrOfvTUEHCVJaDaO8dx88/87XttzM9e5rQmo3VtCii5v9KWcqh3gfp4N4JCWo0fPby\nUpcpQ2c7MgRryEAtx0LlsaJ8eSj1EiUZ1zP1QjeL1VXhA50yMJRhcIGbo7iEQXmPayzti0MClxo2\npGZUjJrafrM9OL2fiTlR5NfuzfZOgUA7C1rNLbTF9JP6jn5jkIXw7l/E3FhQ8nmjPRcZolQgIrV1\nbTh4ejSjDA8dZC2FswjRNMjeitmAPEPi2uW++UKOPmyuixSnIG6tY79gua8q9sdf8gdbBD2taRAC\nXRBsvU21h37UjcIEX2JBfa1iIJ85eMPPg4blUE7P3sJa6xbAkPFg3UmuyfKQzHom3d0ykbVtj5mB\n+Xq9kw/sydV+vMfX0lYSwNcUP8mM9j7guG+xqZ64YxTJHHuO3M1wPB+KJ8d1ouYXUMcUj18fhpFf\n3I+z2ehh/HuNqYCBg8XGNLrjZ98XlNGy1G1XCBhVDkGyTOaGs2MiIuCEElrIg6FMXt/e17kxLQo0\nRLfvo9YoD08VF+RS2AzmWM9nYGZP7w57oRPqviADWieWkOXXzcBFgetElrRnMkezMDxYnpUk4kG5\ns7zRMAkHb2Mg2snABG5+YYxyH/pDloBSt8ZEs7P2sMwhLWE1rtXfVBiMltseW0Bp34vjoApjHEWX\nD1i5tzgJ4lFyLGWQWlF1EqK1rev22gu71KhOMRBLveDLbjeNVzK2Kzq7lZVdzSMzcgWqLP984iiL\nIiiVfHdpollSR2oLMQThQPBhCvq7hLHP/Ej/MOjV/9h8Y9x/Q6z6rhIyzhpQ00hTZpsz3suUjj+H\nwxN6MaKay7chu6VuVh/9IFs1cO4B9/di02OL1PCKILPevqc+CxIucY82goyxQSbLlpcW8qWICkj1\npnSVTj58k4tOEhPAxD7+mfn6t/I/C30mM8jDiQ0u1ejZBix5NhpNi9Nx/AxzbJZOWGUTTDuzyBaI\ngsdF9n+fnzhfEsMtR1vMgiehtQsky8gPPevQzcq138EDR7WrdDjCz7HGI612f1MevvcQSZIqTdVP\nPLa7ZikkVTE0nJxRWADRj+MxiutrFRcF6ujX8cVPweFdLJtAkeL9kSBo0X4z6QE1cftEDLknDN1G\nDh3bu3qo+TpOL77J++pBvXaaWx86II7fR78Sjss+IM25imHGRVs2hTetqfhFYcEzpJ6/9QjizRQI\nQxyOJT7+zFdnP5cUIuENx/fsi3N37hBw+py5X+eo9cpcPBcdWXHrIUePTlpFB9TYAXglzKFi0qQ+\neR6u1ciJzNHRQx01fwZ8+JcKyL0QJ+qsJbKntTmC0OnVxpWFlRXiEwoxWI0HgLVlmBxH5FL4T24F\n2vvv+4IlkBaoETQhsrx/dwt4an8HYRaOED4CZTLXMUdKv8GnxzGJYE/iDA4OGIERHS6LQzRZUy7s\nu4sysa3y0wMHSelE8GCR51+lQRQXe227HhfD9mTca0Bakdv7+vvKTB+8pnoMNddMg1fmD0FkmSS8\naJfoDMd/fIsaLbX3MK7qiJZVt/e+WGohLVP3mS0CTNJZFejjP61XlHeUafEwa0g7MWP+POvr4KFE\nEaAGdLQtN+c+xLe+/3qffg0mzoEylcUc4dhZxIPuw7AaVs5fry+X2KrpaMuvv1YT9zJEnmXy/0jd\nekUqbzKeJTuPS0V7ZgH1p3WGPaYEsa2kT1kRZzdSrEFj91oJ3LFTjQa4gI6vbwxwt2HYFaaP98s/\n6RLW9SmJfUO6Em7l6r7m49sFpOa+iEXBoG2RmsRKqGdoshOqtGHGvZ2+vnM2GzBGDVxBPY75JKa4\n4q7zGvRxMeu3CY4XjBXC4KO8LDBHbmgBfnRXosvVPpQSHOUQjbnwZ3bUNHQa3uv665NPkhzZWaV7\nHjGQCxNSOnpPKj/ZD1vQNZtciH+XIE3lHGyliBTne9kLcNhJ2ZVcmcMMzktf/m9BjmuWtShZfwtK\n6BKAigjDfCEbUoXgidtVZyAGdC+yejlD3yWQ4vuzbgbvjX//nz3APVK9U8BSga9SD1Cv3FgtSdkB\nxBE68ZRvwv4M/mOPYEiqpIm7r22gE6auTa9kL7F4qpxgY2Nz6XujnW2kjEl/2gYWN4czGdn7HO1K\nBsHdLFMMhZqiY3AygUmevDy8149f4ynqX7b4drRhV0F8nuFT6fungJm85UGuAe/sGBrGqnKcnwqD\n2raNfMC9WqNa8XFmULfZttjIXRAs2o0zFbrvJzkCbZMmCx6feG5ecRMpSq0zdIZ3MCv3dVw3rNFU\nBGdraqEu0KRC0r7Hm1ECAZM3sd1GUEU61zvOl+oumc2ypAZq4haBH36Y2xK2qQlTguiuib4Bo9BG\n1J2thRw8PBXhcYhOSWjpixl1duLoeZUUGQ7YLh3D40oWbLbHrQzTxDSnLsO35g9Bbt2SmQF7UWwk\nTa4Rqbsqw4NX9Vfi5mFPUURfIPzFrkZImyaqCP7AyqdjRoop5UOgVvQ3xmCd7dO0JkZqDTOL1JNc\n7rWUUnO5QX+8SDLZziTdZz2dz8PfgzjpWnxI0aQb5F4fBC76crmQV6e3dcGGBUwiQTl3CJmkWgmX\noyo+0lR37W4zGshk0iAGmN2GKBWhV4gseIoC+mAZ111kUU5QcZzyjcIo4JRkn7byxVOdLNWCpjeZ\n80xK7E+eRVBnlG05rLeq/nlH+xwme/4UYxPak72WJUgWkTk+ug+h5rBMtJbEkUCdflHpTVfiw2Xo\nJACxlwYaDyGjZy4BrV6Nh/MN6z1HVgwNaKVXc7eVaILy3POCExHD3s9cuBfuMvKVu3H3yxoanLd7\nhGbZMWE04VizaksGTyewhV2cjg7Eq9e+2haHverFanxkedSQzg2zrYRmSHNH1/Ve2Ej5DbTCh90E\nLecReCGEuNdFxqaEC982D8LT9+yduDORCh4nXjQpa4VOEnK6lptGa4NQql/E2i/kXu+RQhB8JmN1\nbq7oGLEUxmct4zSCRuzAjgny3/iibBCmhww775nqpjK1MnO6ZgJhdTDY7A/8A3sa8J4hfBX3qq8Y\nffJIz8UY7Dlraw0TCSZt+34jjpfZ6yjEzFBb8BmMvRUd7PUpd4sY7xeENJjnErTp4mOYru0McZIh\nFIGfsm+v+pFKCCTk+Y1/fbxFr7tzRkbqRFc3gRAAvWzNOJiC1TQOKMIuD2M681Avz+VCpZheuG3Q\n4gx5/ZnLVlUo8+F2HnkKUBlwmqLIMVBDGVB5zdcsM3Ta0osNaEpXal1TmvbjTd1ron8LowiFPN39\nOdLGGcu0xRxF2CpiTMukfGlx1vE6cW8sOw7W0YRiBlwIRYxY+s2tdl7kwMeLW2BoA4CDb13DkbBi\n0ShRbxRXVIxkmdkafh0x1th08NhvNsfEOXIyASHisyDY/aT+Ap6uOxFV88h2zhgm9vY6X6ptfls9\nR8FM4z23UHKy/vKjApeeK08Wbj6J4Tu60Iyuqg5jRWm6XeC8AgETEce4r2nKxY5MtcJbuLlQol6j\nJHPmFNdZS1Gl/6xr2tM9zLSIuMl9L+XxZcFHPdccBwBS24w536Dao4qeyS6fWpdn1+JyTZGzgy4w\n8netJWCafa/Re16bY6AeZJ7QNPCQKONF4rChUHLay7vYSyElW0CzSLC2nkFGF7qT7VHfs2yoadMJ\nxMwSqbJ+lbQzYQU9pzY7wpISa138KoZkiayoa/3fASZ422YGK9Xaqu+07P+Fz/CK518/Zif63u5a\nbxWr6RLozbRRll/VRIHRAeowTuTyT/w4jp3TqKoPHgtDvqpXCBCAIqTTbA1xMtBWdHBlmOqn+nHp\nRDT50P2WT2llXjHdeXdlqESWf2MPuCwmBwQ1gXMRPGFllbZ6NerHotYJf7Kpyw8VzUZYoAY+xTAt\ns12ABZ7uYPVmkOqsTjCPu2/gY51j5TAjEfrkzgnyh0R2tpJCJMfYwmrJBoQApCm+QXPM9nUp1j7h\nmp/bUBRC9fXy0/eTQZ7uRDCNADsxPtF9feIRqfWTcSIDtGrvqqCoQiiznsFRHKJBNAnXbgiyLHS1\nqX7teyZqhucoKcSF6qLrtfeCFpN8OxAasgzlCdXhYQA6zJGhhiLjEOSuqGAwx72dwoWfoFVu0DI+\nNRnxxS0aD5hDSuy/THPObiauSN05qw9KiURqc2k2tk9On/amOKE3CHylA8mFwI7YkBdIeH6DBam1\naQ04oNO0z0uIlivm7olsSQs0olzq94EqqNUrEv0Ynj0WN6Pk7rGxc7BeO07KFy9b9PZQW9Q/H6Pb\nH628EJXXBE+wOw7RQxeN3Vh9Bag96k5x21PKbFOJC/W+joopcKZb+nBG2Bc+369gYif6+prmzPPz\nxV37hW6P+hTBk7juW+5T5DjH53aLWJ4eMhcEkjYgacq3NJbwGCuQG4nebayDEQkGEY+xTqvGTjWi\nQs5MBwCsvg0Rwo1pOigUVvAAc7ALk+cayy/kuakQn685PzkK9PnC7xZfp1qlM2osKdCEtTzLoxxQ\nbDetKAWNCLa0/u2EzwHpQFenTEpZ/NIk9YHRrKMKiA3RV+BkringMdktjnVOH5AdfcpSg+kkbWlB\nxCMnIwaRTzDzJPkFNYFHSzPIkKkdNhFXayEbf/BJ7F5+HocZwodt0DUuzLdjDFmKm4WoblKHx7vT\ny+yejjasnU/x8bTXwaK0/CkFdO+3dkzeIBZheMQbF41LcW6S0C+Uiy75klOqm0Cz0UnE8Dd0LRoy\nplJdF87pdx42eLDKrvnWKA8M3wpvsPH7lXu4XiA8K5Q9ezqTQtNXWO6Z1w/b/SRXrf+INdjL7jlK\nAIEFgk1nTTh0xYxFGUnIyX8V2S0Yh+N5rWNVSj5iSQcAdom893ly1sdW8H296v1avFeoEYRSkSYW\nKa6XDzbhOfmnvucNq8AY/yv9KI4aJmvzjD21E5j7Ha8zQHWgaei67wH/gxCW6Do3TfSevO5vydBd\nBIIwOULhvk/R5vGDSv4rDS6GIzTiGPiLoWF15JxxRtekVpeAIr1+hPhPJF2cl/7W3BWoM9+7RNDp\n3LZExgdPrH+HqgR1H6Ym6KGzDMvYqKFWIA2X7Elf6LA/kcXW2WrnkszwDFpvANqQKcOHXtGHnUXw\nGHXTgPH3wNYZP26X+ee624mxz0VBRWxasVqm1bTXPV9BMutlk7P1gGiAZNOc5/rUEcmZeNQfvxGg\nq2gRydDrHWOb6HwzlcX87WvWlzy0OfI9j94nW27Ds7K2XTl3Rc9vOYifBUtBOnqmOxrNPy5y/ZkY\nI6RMvG0GVfRvnhL0hkn5Ejx6Iarb+epn/hwYi1knDiSEcN0dKGb1vudJVarXADhiJUYcoObeyL5R\nsX6WUTf2EsC+EubhUm7aX5pvHSacDwsmMKNWlJSPA/HEkZhquZBbdpVR92IDHbk+whbLeoUkxNDa\n2vO64pNHJVBrT3rcuS50HTBgMb6ZAojg9BXN8BwmUiIAeX/C9lbhUzYimCIqDxjNeONUJ7ScNeL8\n20QMvAcR1kgLf754SPOu8cUicJzpFH5c3QnJK0zzmKh8KjdbafdNR2rDwklUNJrAge4BFMddR17w\nAWmsJXGMIJTXLKkdAgi5xxhH3J8gwFDkPehH5L3kqy+zTe9hCOGDYnY0BWW5O9cUSBpVrsRHsANT\noWSD168ZPZMXpzNdb1+Xr1HZcmjFsapX51xuf+OElOMCKCdm+YyGuTV7BbDmvueVlemcdYCNX4gb\niV1+8EUIrv2vHUe/WKRp1/9wLyPLK/RmMRfvi8eBsrGvmdV/MMej6wK269UBnoWsP6tdqmlXqEFm\ngaJYVEPJ2BuYs0jIEhYs5SKEHbwMShaP7BUa9fGXTCeI8WlqhdnZa/SX7AAsmQYoeGDHej/y4Vqg\nE6zp+ptK3PhLQwz77z6YpuAMDEbcPFknhAu5nkhyusupEYcv0/pizLPXeSPtdTBCUFcG5Rla4bcW\ngKoMYNOTMuF/MjvLt2s+NwxaEo8g7XcruCRw6ze0uGJaH6W6hLTxGQpE+UTm1zV7UF9N1Fi+wp6S\nHApGCfqmeh4mK/mM0jR0gz5PGkFXGwQcOf1OGf8JhcFzYZasXN8Qa6uTL7v9gbjMcC8QwdT+4SX5\ns35VPsbfXWZp7r997DxQaLnNOhUMmwG9l4FLOlQW5dSZw+PsPeUPcIIYrdwLG2NLWmrpBKF5cZtf\n6L6kQkJx53fzSfHvdB8fx9PD+dUQpyoQ679xeebNO6z5D5byc+W6dHpikebhcXROluITkQAP77mZ\nn3414Fh2DuDMJhXyqssCj6cOR0xAmiOAq13hXYVdO/h3h3U+PqFbtyXg9tRrdxWX9BaBNgv8Dcqs\nDHoEqxyg6SI4YpgvgAycekEj4EdLNfiW93HBTMAFffLTqZvP5REryfUXOI/XUCrxViXGNEGZ0OxT\nNprzR9rkYAk4S6kIyXiP0OpEfCHcU/7Oa5OIGPd6086rUXg2I7YVV/WIe2jEFZR+HQ12QrRXBhSb\nATIQ99ierIx40hPO8V6u5cLrdRoMz+lmm8q/Q1etQwSN5MubW8eDmKU1xkYfsRHzIJpaxLJWRNiY\nuemGsvqZA+M7dNImYV/zKaeipm/c9Gl3WrGSFZgwsg9o487nEl4kCI8YX00Fv730yx/qGq7lzquy\nhhLVFuvZk/1+Mls70zxvZXVFSR85UAuuUcTscOwceMjMquLMm1jbPrXuF2S0E/7kl8EgpVA/4u+r\ni1EWFy6EXxG+c0e40bk1wuBEGGAys6nGEbXM/MYhFdEWzIjtVxRu0FG5OjRukYtIVC9M59gpBPMo\nTKIkuVojMZtk1icMxCqJHkNilrnta+kIzJkXSMr+bL4YOK598ElD2YlveGuYE/YeHuv1zh+gvP6E\nVg+LCm5PH12uw2PGxMhGV13S0OzUctZDO2H1WPI6tlJHU4No4BlbKKN00eLWoCiIn1bZZUO+OVAX\nAm1WsIb+VJuWQzrUu99adkyFSTzNfYPgJ/WmKUNYEE9dfaVR2QtOHRRBjZPYhWvAKkd5H+/2qfUy\nLaKGxiH7UeC2TKHWiUcPnTHfFRNm32eqhD6FrmxpROaxY2zc5KykGHziJWUTOZrW/+RKoNu1vgB2\nsj+SCoAkUDpMXJ7zRfKjkLBhOkUIrwHqZNj/7RKjH8fpYJNpFHYO2AT97tE9C+uEjsSzzoaJgC/I\nUYl05GvBvvh9Cu4k3TpHzgLdOcC2fftwBiZ6msHeXRpvPTDRyos4GHEQekR0zOLsPkuoLtuY7m8w\nVpKDfpUQEFzePuxgMzTBAr9NjbEH/nSNvADRtb2l4355dLu2FnI0lNf4eXJSVXhSnfsiig52bL3H\n8T8GLFzIQTQ4DeHdRPiZCyl9SciusCoM+aGMXjORApA99xsMD6s7jhFs8G2xF2D/ZAegaaS12dOi\n7nNOW5bYu/QQKf4bsdkv6NC2CzJSdGuX60CvQcQn5Jr1dyivIOJaqjD2LPU7piqRSdRQB3b3HnRH\nRteRCiVs0Wwx8KQPtlTUvFbr9Za7+hK1f/ls7Gea1MyuX2AxqaIkpCunaGVTPAHw3aK8G0Z1SSAw\n4sEGqLkOWY0iL9jR02kzrNs5s/U3sPZT4lw/e8vUPbzE9g7AN366J/nPtrYkeTdCN4ZZvUWtgjCP\nV67cnxwwKSKkbPGiJ5YjLFXzIXLSBsgsh1FrwwWmFLd0FQye6MMOEAHbCygIgUGIiLXGZbV3y8fA\nxSg1SZftdbW9ejAPTxGQ+leCErl4mgjK4aYAIcE3lPwNAIWO65/tGq5BFZY4ouxGT0uMNL7pWQhF\nhdz0ejCKh57D3K+JxHenM75jBgCndtsFZYbL41ZJ4rb/sCpeelqnFmUxM7ypx+Mi9L9a0XDVOrbx\no9btnPw4lpLBb9ZVFzLCy5ppM+k7bcoLx9QhkE3lE/9yQftkSGWFOTfPUebN0cysDf+zqtz6Mve6\nCArw8PwX/5hKfx2gysxE9A05EXWctWT60b1bEXNFTFxHTBD1Ko+WqW4WTTlml7MdqQ9ymz2KNwqT\nGLfmYuMwOaidepr0uE2FQHkZeBoY5Y84o/DInzU/oz9QJdwMVR+FQP3PVv2q6EEs0aqxWbPX/zPr\ncKTdeW6/m9rq8bKfd4EwoX3TkAExLMsdBJ2gU/ELHHDX9RGNrZDE+gUotF9LqoBTjRJ9dgyPPyTT\n7xoEvuH6FD/3YbmhKJ+mP+dHcMIzmSCeIhMmvFHDvIcuin7VsuHpThM97viVkTEM2X3mXVmyWPlE\niWUchV24G/xW0geC2l9uBJz9PLHJndwGLIvd0VaYsKPubckqzj5z9KYlKzwNmbD4ndYf1BMliQra\nRD17Hync2x1x0SRT8oOoLx5qiPMu6bCHL02guShu+QD5Wqr+udw5y+HS2kVRFJKidskMgDPv/zv5\nQv8GpCdv3O+B2XsH8ywfdOEwITPN9mRB+CGqduLqXHVBhVymUtrR+zYyEscDS9bwpI0VQvLk7Zvn\nouY19wWYKykM/GhBrNYsLGNgfzkbIYXuTDyEmQtxVLyMNcNXQvif3ruYw4qCRFLvl0XluXXQ9MH8\nkxPtz1/MfnguNlV/h1B4LhYlqxQNtqIeAtUOGJZi+ngNM4WNgpn84ILO+AAOegyDMcl2uWhI9xM9\n1nrvueUJu73B2BC0SCLYZyioMbLfiJIf5Zo477mQ71wGp+mtx9HX8BybRS0ry4Amw3j1kedKr5g4\ndHGDAz6frdJg9n4YT6xyPKhUMsyPsgiOtHF6W3bc16jwppZ4/MLm5F7IMiFccJEHm14RbhGT2Iwl\nNUEBeE7HJolgxD8pPLpi4I33k/uQ2vogJ0A4aSrV8DvhxWi4eerxsuqdMfhvXBzLW4i5tUHcAmjo\nwQhrjL15YG7HrBSaYfImzSnasCEs6ttvlmSieOiRJDYMFh/BUhqn9+6B8Oh50MrN6WvXOnE6wGnm\n9GeWlq/R5XFBVeXKnJvKYxz0tNXkhZQs5e9GFKt0fT6+EZVfmYxGxNUWq61PlbwNDB0X2uqiH92c\nqZlvGaicULWp/4Dz28tLtXmiTdGtReHnqQvxpbDGz3pf3KYDzfSWagDWgRCRQrYdOZgyuQfKcC/p\nOy7ecoMg3yW+7nZXsNu42DT7OGEH6Xe0oJaSkOg3zwjFBISmHAdm8Mqc2NfT2WyPVfenG/qnPZLe\njL2/y9n1L63CuHc2ToGVmlgNSaQGVJyWr1iLHi97i5m8dBdHLharkxmBca6q1o86TikfsJDiwAHK\n2iGZ8rxa4/FG8aEM/kH+HjG0HZ8IrCgbosbAAz5lswmhx1HEKvSjZ9Hd805PQjhdPf+ccfev1UCH\nGEMCWxs3xWuIbzZ85f7bEYchdvHsAUOzIC7LK/gcTy9K/hJr0jL8zpQwW9UpC+NoaY0kPUhzIoME\nZOoOTCeoepsmvQlrUPSL1jEfJKTeOu5DTU/WRe+AiehP0UpHvvFnqv3qM5DSr9/Ry3xhu5i7tYCT\nwcCwI2lXBWW/9jq5gaVyUa86o6yQJ5KSyDTjTT6evfbmGQ/WD1nct4JqMkeDljtwA5LWhpXIBnBg\nu3pIkZ+ykrMc1CNrTTzKq+iYMMah1DLDv0nvmbOrQryFcq+qEC/KTXIcT+1gVF+ke7J1HiC6z+ST\nc9fC5gZv+xbdHAcIlF/nDEmMaiMJ7UGTdp3pc5ozU60dTw7QfgETPWIfDqx+8dLF57NUx4cqBNZU\nOP4l8482z5eTrZItr/y4iHoaNFsOnlHPLAP6JNQi+LpCSt5CAGOYiH4kCdDUnci7NGe/IvNPWsBb\nidDK9dUHLCO4gmRaMTYe5FXUgGWNSFWt+/8GeLRz6pWlDG2XN+q+Sj81Qu4M6/WH0p99QyNl7vYI\nyAURbIeOp867PxI87KLcJKYkCdKTKPZXUD9VvIu9mBrbPgjT69r6YMPEJO1WVHCS+k/7dnfXQvMi\ndkSSYF3x+gdH3CP3JZo+tiWBkJD5cvop+IVh2Zn5R3zxjYqT698Ajft4VjRZCm40KJvdYapuv7HT\nTV7oiKNu/9pnxhMbyQM8ho6sz7KIjw2hukdZMxsn9T1EdGR/5bzjwH1YywolXWaJre5CDfGQGFrU\ns90Z+Fne3ahrv7K1iAPq/wZuD70/Kg5EtGgzXkrSD5fQ+M7eUFYVWo8FA1/HbNDXEKq0IkokD4VO\nlus98Rgu45748Qis23XPASsGOSrG5wlu/i1lOgNeRT8z32cBCRdIgexgH2M8upB9fMBOpPVaDz3M\nC7vwq4HtNoXdSSnaMQ4rkCNL1HCEjWET2k6yGWBErHQCMgbpvTUM19rOB1oFHruoM6eOq5NBLHHH\nP0Ig6I6ad94cMlCp22YMOq3iJCCH0PjK5WO24TDN6Xdvy58O73o2u4aQbHAbCgeUJkgsPeuBtHzt\nMOWpAq/Gcp+N9zQtIkByP8e2GU/+28hRmCPNaALznBu6yvoB2V8ZMjRSYfW81INOY90+HoERTD11\nLnANoQ4TXzLfidzRMc+brvg385FfNUVfjolI8ZeatmQmyniOnvN3i3HZTNAfBjXvnjyF7y+8Ae8C\nWMuhJ3enTO9nY1k3Z76BhoKXEgmzuqD9asLM79CkqG2HAPHcbEWn/99FUU68rYW13IMae85YPLtP\ncnmelTpXqWvzl1faK9Dpr4hwKeCoxITBE19gS36zM3cNfCEmdliLBdXKC+Q9gcCW+PfAS65xf3H1\njIJ3/+g/QJVi55/erT/lGd20Bd/N8a4w8iUY9zzE2RWTNODskvUbSfFVYk+LK5N3DGfUp73yvcTa\nx3WIS2AVWdOQVfACEv9isBDtBqj0QUV9bwrfsUJCgsZ71WDFJr0qnoe/ti01r3a+8i4up3ph35XU\ns3ltt/8ZfDF0oRLWCyG55YbFrQYCvqfTEPDcGBMt+wusDHKxGRbyCGYaWNWQoxKGLDLGuiGl4vDS\nK4XmgfutMP/EX2tRijs0nTiYGL5Az/qfTLiLCBYEmWNZGwQMQtgsPWCxxHekRq4l5+W1wIs1RTaD\nxrZnMEZgQbR/NHE8s+P/n9DWDDiOQPlqGqwl0N9OzIEB4eieopjqmJ2GCwWVSaLZf5G+EDBAQYAf\nPrrYlvBRmtEOSdXF1PazCDVotV2UDonSgsedzkDgbQEiASvuf9yMWBlIV7i203LCxcRz9IA4WcAZ\ndy7o+xe77hRXCSsZc3QaZwRgnsKv3e7giW7gBUX//n6arVHInVm6O7PyzXH0SEq3xYe62fXfXrgw\n5nXUHfP+xMdXVD+V6wuzIBkcsY9550m0jzNWekNM/nmSE6weRNMfHq1gUqUOxg7eAv0wCkISL6Zk\n80MYMP4+SeCYeoys7znXTpGXgvZSUo+f21p6jX0eoSLdlESSEJ2XWwXo0Ou8Wk7sVFSscBPHV+ym\nwBsFriwmAmGelUxMiPiiT3J8Y6QulKFE+IzOlasIuJ2nF5Tcrvbb9NwW1HpQs4b83TzPJoAH1s1j\nQxgKvpGS5a7CunepZJEH7Vd1lCOzBfRQwB4CIEyXjyNgxkBIqAofE9EUTBuxoVjUk/68maFu0pyn\nZJ41ltL8d/ydyriyk3Ux0SHN84BgLhUozwbvQI3MLVZabDx/5fLAreHeXS2oiyxQXG/SptFdnzAK\nqEm7iQSU80D3ikg6snGd/ouViWZIHEq6rj9oqvC3PHfGBUs/Svsqc8mhZxnM450oaCIVeAAqTP5+\nFgQF+fm8JB8qGEF+HzvVOXB0HLRv0zddBs1KJdKkLfbGV089x0HwnNUuCQS6Mgs6/X2JzjWb5s97\nMvTHuDoZOWxapYlJ+HXETwmRPCZFMRglQ+dOe+Ix1L8MLLGb8Zr+mowowENyjIrFoXPc4twYHPP3\nGyIgIAp2RFe6RP8lCO3WD4u5yVqwFc/orb2gGPbVk2i1sfdHgNE+DGT6eHxYnyPXqOBe9u/6wJVf\n7VujUmPzEXm/1vmcfCUfTOgMbN039OHQVMb0VxBkQGsu3qM8EG2iqRewFHyVc9IZdCNkCcHlrxb6\n3+lEXL1rBnxgk8zgek8LKzPlTy7SiBJV8fYBSA7jC09aORj8OuMzleNOkoKNWPjXfllAJ9tQfcg/\nDWahFrR8hKVUZW90ZJa4YIyiUrnz48ZuI/ZUTBRnFEpchOSicPtIijZIXTiqmL1yJ/Y1UTHhGyKI\ndgqMojsNOaB/fL7sFpKXsKMuc9LU6/P+WQRqVewoUPJXYOCS9SI7WqQXnmbwkrgF1MGQZz8weBoZ\nkF5AHXMimYXjVH2j4hv2f+YrCG9c0FLecZSJe0Fcopmvda9NAJ5yK25jXTYdSLa8h2aTcgjzh3mx\nxG79oxlRzL67OI4fSXyd52doJe/qHoDhu1mQ2TUN1XWciHDnCe+668W/j9W6Ps0U5xco1+mw0ZYN\nBYx7JkcT2ET+XS+TQC5YA6dnJVufL33lG1et6OEEJ0Vd/HbV7lZbNXIQp12ERcDnuO7LihpBzdJT\nVLT0SEZZnJVD4G5rWUTtQ1eYc9NusnCfCcLPDZ3c2H4S4bdx7DHYiM9oqqgMt5UCowVxXuTS8MVC\niK+pIFA1pnWl12q1IdkSddoUpI3NbzOfaxx3a4hViWeVPAo7H0cL6FpW83aXTmyER6jhCFQ0Vdqj\nwUFzITBrY0oDIRWVxE2i6MN23eCjcorc2CXY8NC/WTYT23GTkE8z9zuzlMMHtMUDy6+3tqZwLF+w\nWMfbUgndqMHG8sDbPFok1mt4yi7lRcZi8Z7vkq62+JzNFUByE4e+w6lzLHlYLATBaDMMD92VsEJh\nCn/kutmascO4a0T3Xm7zi2SWOYIXeIgeiNb6ZP/Ajsv6/0xGPL6kgB+/B2p/eASWS3f3/3dLFrzb\nZyVfs5PnOaB+X7wsmgqtuyoKVSWHaTtBN7RGEJZkEjZryR8q+yqx59nmREm26cAFIgA1iG+3oQrK\ndy58+uHjkwcQOJIZGph8icCzMgw5F5/UubXWGT6X+2N2MHjcqwpDWsn4f5HJySj9ZwEsRYuVwrUw\nS6Hpnl60Tl8cmuH03Z0ORmmBlhqAIwrGo4ejaGo8CPIdfEVc9iuVrQpZvJqrdPNWbPVm/zATBxIX\nwUma1rqzVnUMPGxmq7VKKUTYenTKN/mb2x/ryF9CY1EgtbC4QFZWGKopZGY2YSnxRL3BdjuTFuEg\n1TZh42sJfBK/qomhpuM59M9Pq6o+7MbnD564MMf/WjhxCCdhPfiv1z7m2ASCQNQn0GQ5qxeOwYcL\n9fcCeA08tY7DklH/alSbKm2fQ48oXw/DNkX/cm98PjQdAUDVP7P1VLs5Z82PygFXj9SJKlDbHFO1\n0GAgJf5wDakV9laut7UDEWg1R8QWEdbV7YbSmJ8ZutR431ucdfqzVjqPFU/Y5n6zuPUOGY45ZVrx\nVnFeB1YX8EK2AinA54643sNZzSOaTM01O4ZCoykzFIWSvcLRiutYpRk6bMPg04Y4Hurctt+olSNH\nR6fnvFM9IBPQaOu1NU7Jrv8ab/Is0IzQ0NYllgJI3lnr6tv6TLK6fEQgbErQQp2DgRqmk3FDOarI\n4LyWJ9t/OgRgg4Pvghm10vXmtIrpiEQOdwgmBSWCgpZCJve+B+kXym5fD5IjNEofsEJ0QwOVCaBv\nSE+vwWavZi6U7jRIlCLb6Q1tIpFT0VBrZ3hyHJM0onGjyKS+CSWh6WyMaudAG4bgpNbHOqL5ch40\nlQF3RqC2gdCk2fOmLItWpzu0FVWJY5oUFJSOlSM93RQWhOSjAaTwd1wN3/iwbqVb49nD+KhfjEkD\nI6XQ/Etwn4WXJv3H+/yaXJu9EKLW56O6zQexSc4KRdJZsKTR0WmPC7IsQqv9hjuOwEEaG7XUd83W\noVXIV1uNWU1hAz36cjEk0xjimDR38cunO+9reN0Bnu2P1AgIFWOrrMPFqPQECoPJaZO9G+NomFp0\nf+lyb+WHDxD0jxkYO4HSTE80PDWc0/dgGhn/EX9nZKzuN5A8JdKkn2Qfp1wyTH+lEuQd9+7K9sSd\nBg8JKKz/nF6d/EhGJQsytj62h4J3Ss3Ybkg+aH4CoYzW3zFRnQuygK3IYfG3eT9qXkzpTNPNBMsW\nl86OSISiM2KLnjxP2Rozgdv5XdiX4YmuGhYq55NxManSZbwVTd6mYk9CWXV23fAi43sCFb3d28Pt\naJFppR8bN9j50ETXdxJoL3d9ysWHYYIWM3bqL2eGFL4RyzwJqbf2gYe4wdX+RDKd7ua45TzsmFvm\nsaUij7MQp0QQw5Tj0f0MKl+NwwxGq4pxKY7cPuoPioQzbmcgaXXd4DXy64a2jVEftLUilrZcRc/9\nwCDCuSKCSEZE1f1lpCHj2PLCZ66JSuicUUQxFy9+yFHxzxXSNo0YmG1ki2qMz3iALMvt6uLD+Awp\nZK8RyfYRleu1tImgxgP6vP7fqFZxsvkwy946Dc4uznNpSk+Xk7CtAdaKT74RfZFDhnKkRHEeBRMn\nmzVyDQusk0V2u3r64O/iUmdMQae7IJ9MNu3sLAn+4HclfT7xah/NOfXU307ErKYExkC3Auoomb4u\n51CqZ9q1ZhO1mKvkqmGqgktgLAGGkJ7XtICuRtTj2jcpeyoK0kAptnYVEj45HH2D4EPbwa6/l1y2\naB8kqJ26P0AGLWvMnxKfOTsb9EU98RA1fn+kEBqSnLA4BqZqBOCfcvdlXtYvYEwVMoyrKmBPxlQZ\nZz+/1/9Md89jVzdeZJ8P/Mshws64jqt2yKi8Y3+ePnnPr7st4I1IK0ztyZgGXEwyFrqkIohTA/7r\nf5xbIjtQQujlu0cs4dg/R4ztO+eZE8Vt6fgMVxQv4IusdV2C09aUTjeQzALdHcbrOw7bhNBA1oTj\nmgI0skj0J/gAEnKXPVMoPPLn5o2+vH6VwY33zrk3gnLcIJSEA2PVPcEymf5NX6nCpP+HeGpNn96Z\nL8npwhAj46izdIwRskKEaYvAr6x83fO7Umlu+9vSt8yc+ST3GIGdx7aFyFsEYp8xHzy+P8I91hes\nA+U0REAwPLa0ZsXXo7YXFck0APQYFS0rcyxnfj9/3JYJ0tGBzGEhpIIz5AdoF7DPSoqTJs/Tjcmn\n6qcG28PEAtyB9JDTwsQf2IdFWurcQl8vIfq6FZTBdT6rbUgbkOODvwY0MNwwN9Kwt2GtGtQlIH8/\n0JXN7KtX6G7FzHA26diqxlPimhTjTAYkGkTlbFIto+vEK6TEuvhiKIk0IdVTqaO8Zt16LClCm4BC\nBaHvD1rYIC+SwOVypE2ljE2sb6oXNOYUkrFCoTZ4RAdUdfVsC2J3shvIHGzsBTnLfhbFccCQXp7K\nsi98dk8KxboqHNnT4fgxcGtgVBmqhPv2RAizSuebGIfqQYN3Zq0kt0fUfh99+cS1IVeJu4/3XzV1\nrFU13ls4ajvRqh99mCSbJLjL+RbFmwoOVlBzkvdOvMwVivYm+cHkS4YpvIgYcWJ8fq1MbR1wzrwO\nb62L7RcVF/6Ku6Jqk4fD/KukBGFGmfGoZH+9utZkx/CX2ve0lUUsJ64HV3gTHGr8Wm5L+O4Jnxeo\nMIgPybG4ec6UE7tSqHdQm+50F5Y3yJQ9yBX+7i7KnZ7qbbF3x3/wagnXMv602w3LQomwhHtg3jr1\nwtGgdC0ng9yFOuC2M5nCYFbi109dQmOojsXXrIqL6kwukhFztAs7wLgwwYA3Ib5dsysbXdV1jcQN\nwZcQtN764fu8ujUT62WKlu4cPcwGe4xxosIw26AgkP2pxob1ASO54BdDE0uhWpGqHDmSUuKVoz+l\nwIBt3ZgodXtA8/BCdzOGHIsFPpiVyQlJJfVJpwsGpSzqh8RPBSRMa2SNRfAoZB+JBUefaOg4//9h\nwwn6b5MunPQL7JjOIzRVPGJ3AOs6ou4tg45SjOfc1DhmBTvaAQvEgwxJGiNqfkiw5uil7UdJWP5j\nZ24DIBqhd64CwVhoRCyLeqZPPZ21sb7T+fsdNH8wTnvo4GMz+wP2vMX7yS4yUIiUsKtYfG77n8zw\nKCs9/vn/rdQbYe6VvxBbi2p7wI35cQpk+ISoo3vMtnV7knqws5jVnuQr1TnNhDX5AHUy/lwoMqo5\nvCqurmQFtwuaB9SkWEU7D/PZquo9kjZmuHLdbXktG8Ph3whpAofqGPd/31kBBNrcBPIFlTgvhnz7\nMJWn9yi/lN9nPATHdZSrT7pduCwLlYw2JYNRonTYUVzPfl8iL24X6bUJwA9HOZ5LHzg53hXIWQdS\nqUOxBkVa3gUKSDWRwswfvr8YYPsfjVBpQPIibXpExNQMykILkRskel9k/LLllZNPP+DmwnOOwEjr\nzKEAhm0S+bI8e1qXx1BUjNy6b86e9gQ8hlSDqKGOVMmxfT6fSg9zzGEcFn2oOb2QEjaLA2O2VxLk\nmTGaE9JUHimmtAdcq5JuCiMYR0EHTyMwrLciKVF42ioAvysvY4CQsfH6iCmp+afnWpW2rsWI72gi\nDkL7AGJGYivQn68VQbmhFJkmJXE1t+UhStvs5+DMjrnY5jbvZvpl1UPpvlt11R3gZBqzpljDdKfw\nh+vJ2tCrSDP7oQOFz37oUp4NSx0dp2AtnerqOVHw4B8XmiJSSB/Flo7XAtL0DV/as6TfS+1p6TjM\nC2Ka+YDkfL/vp56hjnr3I44Rb5vEzhJpDgZ5H5eeVPei5GC5zT1ZFHnDP9LUcq6kVCOK1GReOiiV\nfz4+qGqvYkaoI8eVqwEw43ig8ZeLxJkYpUcDhpgAe+ufNRwsDZMTgSzilYQYFtfcQd6ms42SeXvH\nUnYin2Z8a2RGd+DCX4BGxo/H6Mq0JO7IjtCEs0vI6TW55itOfoTIKn5dHdg9EN+FagwPxUQZZ3qa\nrDodT16jQf5hPG+2YGm6aSfBeLP9dYRQlfnHiu0HiPqX30bkDMq8Tg/XyojbYGB2ZMpyOAGswmNy\n9XUhYk3yw9yZfMe3f1CUzmCbOCxa9LX/PCB7jev9+NGCRiyAFjFvfme8o7FPKGyNDd5OF8A+dMYG\nrDKIg9p/rcNo7i1EY4rK83NepBmswYSE56I6I6AMBzzxDpw9/12wpiTu0fhkiAex3IqhfHvkxWOg\nAxNL9ptaEmfHXHnWNYncLw9XNuJvHndycwDzErsnA4TXagzT5JfoCb4GstfWWSK0lO2mxAd/PIBP\n/YAYxdcAhQS3Myhu7lo8qJx+vCvUSqaxCrbCYf20zog6UWfyhRCTewzNNHv5LJoalyPPDJw/iz/6\n+4BHvPsyKP7IcXj1eVoPV/6xGiSRyMVdDeWBRt57RuSI08dOqDrbGD5jiNOWam2dSC1b4YUdGNTT\nId3SES5GPIGzyXasXPfbO/zMLug5ga8gJszw5jnTH61V/eTpQuw43c1OXoVaLVnLjxlKqwreranX\nTSDHkRh9ppNJ0HbA7RjPU3NqLt7qHqK3w2sqX8sxXdvo+kzM1QJL1i2H6tVG1+/p8vsCyfu4i+UM\ntn8xi0Y/LlhuB6dLkAx6BxDDzHeDw2pfGcJ908pQaZykxM5OFq2r0xRcPPWHgj1pGUfVaR/grRvZ\nRkl9uPdHbfPkvwA3cri54VgEkXB6d/sH7QspsdPWBaGVBJQ34z3J/VJFvjcRqu4G8Tc4AO2hjMOS\nQvdvWuIqqP0mpCZkMjoFhNrcSgGJF+upVV2xWUc3yFB7uqc/zXsDSlhReSKSghuA1FWD+ZLT2gLQ\nGnt74ZRj6RirMUrWj3m+fxsnZUivUZ3PvRWl2oTgBufaVtbHu66e61SPOjfF9bJGyWsV3o1GZdvb\n8gMrdmI5RWD0Yzy6QKinSc6q5H/c5zkEIdzqO3eWu0FxJ7otAcp7SeJbD8F9tqbPxtH/OA4U883f\nytn6rPWanwyiYVX8PVqvL/5TMm1kQ+G6qxE/bc3gHfbFDxr5Bbfm/wXVTzmd0+nM7JWRDOqMNTBK\nojHDT2nw7Ucf9F1A3uAqkeF/QuMxHe22jVrfUvBa1ZURjRjxQeiZmDSsGaiejN0AwcQp3/aH6n+W\nLAjY4yuX1abEgLoSbkY/kPTxRf5zmHDxlVVRrb7rVAo+FXCWX+ePlD6tH1QBpy1fpHNQS4/NDLj+\niiCi9RC+G4W36OjlFVVhzJwjHCI+PBsQ+2De02mM0zNW7xh+ku5r44dGXEVH6OeaQaBre1OTBC9A\nYvw4SyQB0nAthR4E2ij5NF3Ufl1rNLMNh8SAXSRudMjMDeoMUHMmJWHZsEwVpcH6jIbHomBzoPot\nN9NwOdEBN3zxtiVlhwexCfkF+N1WgFvtwHzPMj4JmEbjM7zdHatG72mBXyk6K7z7mkp2qEB2o2xI\nC8ViF3xNKCVQCvia2L2dEDcZ7DM/UYNXCIMpXMV1Um3/khmXEMHfBKFbHGyPgabdPiQt7dRKmuJ2\nfv95FMmV8d9ZE6tDggtkW23f7OU157qYeTYBpQ9thpfS4z5zvXCbFkqN3nuxFHJQM507kLW1Aloq\nsK1trE542nEW3hRJ8lWrJ/CMSZc6mDAQaJ6LqfJZ4q+l8tjTN6DDZ8Xwjsf9bvBm1zpqVbFuVaPL\nKHgvJnb3D9AadvymCZ5T6K+dM1ZSP/hn5pzMhlQtVV2vYkNCweUBXKcVoRzTjZ7foINKwspw9UMy\npIQIfrc1Wjeqf5h2/TRsBMe3SVRpRMgSYhOD0zgyyYLJrhnAej1STyLPTRUiDNjFs+zn7e3vgyQU\nE75CbASLgY6Q5FD6BCQs/yxSwnFfKb69FxFWQAuyz8Mi9I+EL0lnbNQ4WpeQTvB+jRLwVQ4WKMa6\nTFVgrJEFunWEYxOcDwfgjR9nT17o6y1WA1zc43UwW/zOA4+Trzt2aXlz24Zwg4MUqT4fYcbQIWpK\nteTlZQGJaKr8hjdu58zXodkvKjtbBHEuzW4sX4YAMw/oiHGZpjhyQef11aPqqNNAfsNNS9/Shi+p\nCnR/XgcchVliILVrwUM0pCw7cqkijrgjP/jwvZXf4M7YMHBuGwVZ2IjKYXuwJM+gyF1ywOHjb/15\nTXrSn9BnbD3atcmQ3dDyCBh1jNYyZiNab1fA++ZeWVT1lzWh8ZyeINhm9OJRZAh9x6jlWRNzMV1E\n1owvB7kuSJy/JZfKL/J+2+VUfR3NUUNDjH9W2F8sHxLXXY3iRU6E+wpUfBdoqfYJJEIqRD0CVLJS\n8MbfX3871RXyD7q92ps9w4xvY4bJovpxgdfB2QwuhVTuNTtXkLVZ5QhdIy00jdFK1TKHLthvMh0K\nnluUB0MUip1iCtmPPs4QwVWlK+Ksn6COgsj4VLamnAlcMsiDeGZr5+ZCC/kRZJ1NHPb+RkGgdMP+\nCi6n8iHSFz7Ee9ODaMoH1099zQdiAX7jV0KT012vqsOl833UTdDMOLLu70q+X2U0VPIfYLUngxz1\n5/Y/H2S9SHpwPD0BJQwAEL+y75uzTod0IAXE+Z3i3JJCPcfafE9CKZu3CDTSRJG4DoaPxZC52H1k\nUVispJM9lwfj/ww4Inu4lu05AflOPo7Lk4cTk8x4bjzK3oBGTXP3w5KqSeY4cxmoRYGBa9eN3QR9\nMtRJW6qx61yuIoQDijn997FlWthtUxBVazPmx7rEgNUQ4howS7BeHyvrS6tP83+KQEIQLPryKVOp\nh8vr50Ly735LEJkcty7sqrXD15emsOVI+Xrbwht9pQWscBcO07hf+mfdTL4gZpYSjpHjzEIFm9JR\no+r7V/LUPtPllRzgDnbvN1HNC3lzY38NwQJEBr0dSgPmlzjPRwnI5oEK9rrmqOG2XGJzSOdkj3gS\nlpMf0sAwGQ2UtMHlenarUr4AoS4ML+LPz6ycQOXdBfEGzb2s1a6rkbTp7W5jfv7JbeIYsL8HF4Z8\nZmW4B+3Ax0nuSVVTxm3xzChDt0J2dbI6wOGvZOv6RRzGHTkWf5Eq+cPXthqYaF9bZ/SKLWI1zFHC\nyHPPwJXS3FEG8VKRzt5/S/G2PzQgotV/U2EAyTYdgloAS1m51kcPOPwezrQvjBLWv+HEQAppdysO\nwqwjxraZNpC1+8TmkUBpBRuemkyz9Vn8CP3EQF6o0+/+GrUV7JS3ym1P3UvWqkgNo2tZDbVGVwUg\nvSOJvYk0DXag62JCGFlQ+xu72EmVaONvEKLyHTtfAnLHhzDxlWkxlOSz/a7hrZgSwBC8xLyCTatM\nqLmT6aozrz7+3oC8FI7tV5GFYYQ56nbJJZEAD2+M8avw/wmy5LYurnBsxB2G3Mbd/rZdaK9Xt30u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MZ4gye4ahT9vkP6z4TE0+EIDvUzGs1R4NBj904t7uQV1n46DMQVS3RBJDLki48\nJqcgVWUohxjsO+5JEFfilLfh80BnRWZi7uPbAp9tM2Rr3dc8ERAJdhF71skulLrn5EpOk3eT462g\nfSEw5ZIXv9v71wVvdz58UVZifNUYRh1ST07x8uE3dEJHkiWw0jQBfiALa5aPGNqR8TIy+Hwb7bQO\npEGmo3FX6AELCa4YJR1y6UZqFTc6OQBaUKv/jKq2hYV3TbuGWLZzUqTNl6RIdzlhIMDfj1GJG3oq\nuWLZb3+mimZQyHiiCwQNgkYkl2f91hDuO6kgiog7XigIIKiAOBQY/S03W71IPCEq9RKNErIVzZsR\naxh1g6ar71mk8fQifD9JUteTJooPLrM3oZKJN/atjIaKaJToQanw0GoLuf8Lb0sa1mKc71g9oQ0R\ncC/8GtXA8+WcKG0aVmIv93eriVS7sJWikPofQeHYsMJC5l3FdcvWCf7QTb4rY1B+olcg4K480lkT\nH1W+uCS/4RAMI46oJPUxKMtYO9W53VHHNzNtyKAz0wesk846BPZo5H7NfVIpeJchQ51v6+ECBFbv\nKVll6oeQjjmIw8MkbVzncN0EWJUp90eJTOefPqTKrmFID+HchyiaMYYCLhH3baC6KiPlRobqbwH+\ncnGyhtI+kkcprh/DLAK9q0elu9ZPWmqCvC7U3pw5P+fHb3NSRajCz1ZeEwT12Uvv0ULLT5FkUQhW\nMPImNdmXs70vXDyX1I6Pr5cimNmN3s3rZLZXB5rdntqR06t6JoBPojL5dWlyZa41VHwtzZ8Y2rsn\nxmHi2cJZQ4W+zdP/nnCRGUKzecBlAkthlg72QvdFyyhIgMV6I346N7rwW+l27vii4KhMOnoFrlLF\nAJAxLdQhizOxbqJ4eqLs03tmjzk4WKzgT9DHpd5Li+jXEeDfbAkrJPzDp+W6hLoq/YugVnWgAaUe\nN9HRMH9mGz9XccT6NV5V9/1Gq1tyZ58yjRyc54W1tHZp8vffo9L5rOASS6/k3QiIH2PJBd5nTX+7\ndT977Bt7yc5yoVfXHKYG2hALhAFfEFsMIOh60h6T+Zt59gtjhikutnENsILgXioNKUf5RHLcvUsc\n5qkpZ6YQmzIOqkMGtASG24RMMEJHOIooO8OAamN2lMjxKqniv+5lDEkZylFhwnIkVBWyb0j4coff\nk+3lYlsAIs9NP5WblO3MMCuX0b+LqGUG6PJZmOJ0tKFjmzD9p/0/ZuPJDFXH8d4Au922TTXhSXuV\nrOkCX4B1VhOzA90PzdYUUEovlPU4rLlZBO/l9ta962Ga+MBmSsV+0+42Jao4+uebzONsZLUKQdN1\n4Ri9xBdXkApSyEPkjoItbz/IsXDTizn2DAT48ud/FtCENYh3DFAGrPDxbsifYSau49kxhlnj6ZS9\ncHvFxByc0suEIS/bzuVQxzTiGycF8OcsTp/tNk5Pc/83qk+PYREDA00fg5fafppVcgSnFpn+cPcS\n/i4TZwsqgd/ZzZohMnYY+BXj6piCTCNrgWPS1I1BDkFlaVlfysUeIodReQX6JLlnPZdOzhrCDMMW\n87vNKas22rPt2s0J/H2qci+hwT3jxSR705gWJW3c6EGwAddu2GexTC8/N5OBg6DiOUFZqJMjyhn2\nviLOhKXZr33yVxtJgGxrTQNE3u5GASYKy3wuDcFmlyWujpJUt0dLk7eeGr5qLmp0wpXz/h1zgJYl\nK8gtO21GzAgss4N++Cjkqa9W0z+DaLBmlaJrV2o9qwlH0ygasdzLjYnqZGDaRi3QtUmQQYedThJa\naBFxf5hUHTjI2HbhjVOYFufAoDFnOwmRAmOAugvO3AfPENGfOW3RfekTSe3laEjuPASUFWOdJmeP\n3YbOxKrcfKPML3ckQCVYotWQkoWouZ5J7rd/rvv0c0jrbOTOhfUaofrvhKYTF+Ke/mw5yNn0WHcm\nryX7fK9FU+miQUxlT2gyvAmQypM1KcYFYBRI5RJRkNRDyQhimgIAHQQd9jNS8XmfLa+gdHBpiVE3\nzzB7Jk1Yesj+k4BxLLdAXeRpjVA5SIbU6cD0FugQIgaahkSD0fwge7CtLXUEoZCFIKEUyNsv0wcO\nYXDq80yLlJ3KhBP6N3jjXeSEksR2bQf5nHV72p3WMHh/7SIfYjaDiYOVPyBa6jpvTQDR4/51dzWS\n4BuftCtoYoXvZN23g66gkIFyJaaiWSdW74v8OM6UTxjC1EyHzV+yaFY70UuxkYELkPTZZDLipKYY\nD0p5ET40YiX+rCbIV/5hY4MzNzw6uzVfO8nvgG3dHIPNCc/H3Wi60v627YMSf9pCcKZKdxbJqPpL\nL77KRXkJwgmsYJnVzB4mmB+5GNSRALEgCSi3ZBFxQRjPRggyMAZl7Np+kJB5shhCsgTrUTr3/5I6\ncGMXWoBUTwFjYF2IlsvsrFYMNQbzTw50RyWxqsfAiOSyHxlpG3Q/MZIbJ59HgNeT5LQqHMbLH2zM\nMVK1Q1/34QlgxQlLB/OfrARN1G14MQrd6Ov9oUFAhkoMAecOKct5vAVR5404befBrF8hfp85nV+d\nddc9haE2MZr94ChVlagE2HweBLptnmwA/7UNQN5rC6n0c3YQErrKz1LXFtFtyGWz8rc18eX81Ev7\n66dpWVJMRcTk0tIYc+fxMIc90yNR5JByBe3RdiRDTCmABfPiKnJ9iPqNn9QDyiInP+DQDTl92wSG\nOgDy3Ujka8d5NRSzOjPQuqrr81oupKdlVYQXRN/of4JI+BONobdYLiGROOCjZI/GrQ82UmyVDRxe\nnnENqu2Ebxohhix9jZ4MkE3s2TTgESxUAuOr+eAASIrTi1nq2mu+cIlcJ1Ad/xgUbLDiWr6DkAB3\nz0gw7YS4OieCJ3Y4chMl6fQ020zXrr7tyQhuT2bfqxoxqFgVGPrNseKuK7bTHpz6AdrzGwmDGEnN\nnNHwkIMKPsdU3ryyBXiFUCcGpMWADG3fH5dTX1JcYtrpLoNc3fE0CO1Rwm4ZPFARdMLm7s6zTOW9\nqkvAgkmfGoLQWJue1gBn4+GeYT80khqdsr7PI1eDoxZv3M5qbQ6e1yVSd9LwrItY53qLYDbouxdZ\nSf3urV0WelQRgcGqv0wf657n/T/JP3yMmFt2ve9mENxLsIJOdwKfGo1b79RGucQJhyvx7htI3ob5\nA1HHx3CwkaMIpzxrh3RXvHYaQVr8TplRqznWoz2zTwnCGlnMRbT9J7V0IBXoKFYN6qLYJ2AruPQS\nD9gV8yzCF1ZrgZBJ9IChp06EIkx4dqEEx+vzK60zJMH+oTwGCJQXNJeuitLR3ip0FJnzceUoT3y/\nMhTgCwRQ22h7WiJlaLKT14dpbYK0ZPqSNIalP8jlxgaSHra/pbuirJ091F4U0vXJ9olQ+1WS0WVg\nKvxWrKWQlMepdwdrpLsCbn/buvLaaI3GTs8yUVeqedwqZR4/kuaFLGWLDYc+trVvBKVXO6d8jIDZ\nzPZSRjyzkrAq8mR5Iozoeaq3wP0xSnbZu5LX+DgUvtA0kezH9DDb5sYIzElQhcS1vjPzhq7akN/L\nUL0ddOrSEqyTEmvjh46SPvouqip0kf1gq2n4RMl9yT0wZZ1VAnqaxtaHLg9qxTcEy9OI3U+DDQSD\nKF/YIbyIpOwAxLSljY1hJG7h9F/zIIfqaZcxWx2GEWh1NK64p6Kb0hVA7pU1ccC8NqZ+tYUOlMnU\nO1xGWOcTUg5cGsI7eVXc74+IWoYXsVpWHhu5YcE0kpCQ46XvjIdddm5SbEyJth/j0Hoopl+z82R7\nhXD6OJhm9x7bAyUE54LeoA3XUaWKt+Xt2PajqRVrX05cwdnasb2VD+emOZ9k8xvY9cco5esJkEEU\nfvZOJLg9jZjiFGkAjvVwgzdwqYzrIuQODgQ9ufTQEXVfQYViRrwIvz78pAMTiOq45FFZeOm5CTN7\nZs6pIlADFWegYcwNwdWfPApN60y5dfPeeYFLV7g1L4i5JmEcu70UrGFXeznZAeva6UbZ7mZWxMLz\n3wiZwS+Z3l/VwO0b02OlnK9XvnwycJVsVFS0tXVv+dshdbH2HhXKkDvheGDMfGmcOENuo4E+S7vm\nAfAq22ry0CLnNeJdyFCdR1zLYZahdfGbolY4G11B9/nJN9D7dJxfngxnh898ZmISxdI82mw9W0Fr\nxfm+Vsa06ahfoN7H7RF6DZRiQxkQUoRtWUa0ad+Mhhr1csHbk2QwkCuDwqtA2k4uZG9yGy5gcmi6\nvGpZXkEsQO1UrA9e4y+p9ND4kDYAM2ei5HwYIh23OPNq3e8NkKHIKo7GFagH1BXMiCFHdv+Q0b9m\nqNJOasrh4cHAxadv/8qPD6ZzBHM7Mh1lQr3oFJxOvnWHSUQsr8qlWKYLYh9rrnAkUBwNZDJu8O4j\nNzHQqN5+0g/LawpXB5VZ2TwTcxs8+FRN9LeEA2TAYYtmZgeYEqs4RXpDRUmp5lcBhIiRb2hm+7Qz\nT4X/eO6zckqpp+OPmE6tDSTK1m6TsqkohOFb/VE4+bMP15PNak+mF5e4e0J+0TKo3kQjohJkTwde\ngkw1ohosbX6VUIvmjRXreliJQJ3vrc3YTJsKeQZy+9frWpNIWFjz2rU3p5afi5jn23xOczvzwASW\niIXuyMxHsis6olR8yAgQLK8zP8qaYiIoEFqmMauDBqP7nOs6iHs6uOJJpt3tmLXjly1DgJJzRdht\npiHpzES9to4bVZ8VECorme4PoLIO8XUdQVHnYLdXiCLc+sqGVXT6vSWcD09ieETtYTuh9ORXMrQV\n8NAiM1tuemIMxWzRiU+dy95PDMwYsHR5WQjjQGVhb9AB47wFPxrc81oqWbIOIniVMl6Zrqys+PKm\n6OIbiaXvw4cly0GrNas8e2AtUGjKFf/o7jlY8Rfc3ksbNoE7nGBljs5HpItPdsILAKMXLwXaAvzL\nnvKJfr2VoPZUClPgjnNjp1OvYtA6l0gZ5SmTSIigdKBaT5eHwN2wBfqQjtMBCHqcwIx5B9SiJDRZ\nzC8JAfnJhYsAbCFIpGyRNfwyRNjiaeTnSJmA9cnzBg7kUMeLpKcMqt7BMHBznnHuBUkTGDG7IMkM\nTdRMxnzLdpTXaakdmvodiRrUGLGi9mITEFucIc4q0j1A/scRv9Ss/YRqXDWapvqG0KmzEyStLJO2\nl9ML0MGs89ADEYykIRDG4dCGOC07r25W6Xv+v9Jgq42gDQGO3y0v6g9D1u5ItFm42ZQ/tzz3fieY\nEK6aJYJh0gXym69TWnngYNpujroqIXrCmboLdoxvWDC6Xr0SenwYOIT8wWF4vjgXHpd+i8UaepkP\nRzuKsg8OY+Ysq5Z4jgKvbbmfVE2MlKE4AE/8ebGDudWtsbMJmfZlNWy+PppK8uHs3RJB4fPOMkco\noDe9hm59vRGTUlU6sxbYinOhZR83000fG628GSRogrb57iGrTtpiyO6dBmYLgqD7i0hubdr6q6IV\nRaIZk8dYAO4/ca2ihoo965yhRyHXYqIgx2N+ArCGyE2trDLqUWQKo8+o4woGTCPcgJLOll3aj02g\nqppktObHd7SSJWLA9jhq4EWsrZGsHcOCS2AoYkDY36m1tQwW2mnf4m7DXK/cHgT6L64jprHmN7IK\nzesNYv32UWr3g5vGiZX56jHlKYek/Q+ytMGlyS904JwQzlvvompPCyOFh7d+QhzlY/kM2RmsmXrP\nWG70ga7X/TEAfsPAtjZpDyKEOH3ofi+hipMiYYJnD8qJzfCnYgli4DohG+MQDK4bhm5MTjPQd/zk\nFeYDXDq++RuvYBO9QCbKHcYwVoANevVdL77beoVixoa989A0bzarypoy53fwKWuox47QcHWbt7OU\n+QVxn1l5FSAPUVnjPaaNQvWhA1NynO3Kxyp8aUgYFsbqFQ85TaIzm+fSne2chpIuK5L8bIRF/s0m\nxAeYhGnBGMWFNvmkk+HYu5TREsHmcaqxIhNcmm1tJP5dyPaMXwb7DmPD9zfYKMJ1KGZRiwzceQBI\n5dWYPwfRcq3PcKIfXkmqcOyxI9uycVLy14e1+WYBYsqbZV1wwHN7TnaxAKHTxEXRfo/k4k5OG8PG\nZgmzdsJZUWBGyoTAcDm5WGTiJsa/VFmpRDbTf0bNwr0AR4me1VyADbNB8GwNwmdZD6c0WsG7/uhr\n+8mtPcZMahvcu3DvkYsA3JLBe4NpwrmJkJLeWEN4QVBXZDAWFo24whzXp2FwnFHYavb5HbrkC/QY\nFDYJUmz/A/sk+YwNTQ6CceqpNgfF0LOWR0j+rzENe2/rzM6CAluWiuTC+ur8HQlEonf4PlB2Z55R\nctFOZaW2dhbwxJGv3kcqVMhC/XNzI5Vh4qNJ+Y59i04pUh9w9PxJ0Vdm1fTDi4P24bzFwCQVWvlR\nQ4L9El7dJfj/TyOpqANgt2bUT72SOfY/qqRBJgrB2mpaHP39tUq6FmxxRvHFizC1klU6pMGGEsut\n71OFsW5fTujh5P4ET6nLALjs0EjN8iz2cH5ERK7LZvCbo3x68/g+hyj4+nb6+F/ny0PBdDnoBeQB\nSHGijyotdJvJ6uJgd7PAERiy3jDZlDw50UAS6jj35uOZQro4RB9t9iPnX39ZgHvBRSV66L+f50K4\nxoRO5DjypzehQQY+4OP7grPWo2Y/AcO3c744rcCIzjZwsPXOVmNRZqC63/VAimZ41L4zIkXcAGg/\nl/wCmH2BTTGxn3rnxP4bOMLfyNr2oifL0hlSJAXeiszdgj+jP8uoQiErD+IjDL+ToqxITzbAWj5W\nDT4mZ8kb9Q/7SCFNboFvPfVEGZgg7zlLQNGkxIhHmJh+N3qTnpjfjzyEYuft76ek22tSgGv+iVqp\nHEtZFEpbNPzp+K+P15rWV0I7aHdEWJlsQc9b2HuXFXZYeFsE4LIFbnLOoVrMxn/GWL3GF3Js5ipc\nVZhdEsFFFq8VRb+DPBA3zkrelwKJ08SBTC6yTrKxxtEqg19PtHRo+JR1xIaDX/G/0PhbqI5LDPLO\nc+WsIkjElY6tgXhZsHCIOBOrOHFwzN5/KfRe3zr/cc5AECoVy6JzU7dHcr1WBEaeZb20jqCm9Dpc\neKZxShRlQVW8ZYTGccajgYvrhCmBd8bycW9KK9iPID+cHRC89/N9FHb8CUwG08yl7Oo+CiB5Txdo\nz29cluqZC8i1JnF3eWoK02VNPJIMJCslnwk+1GzM73yBkd6Jp/hFb+WS9udtfmSC71kBod1YO+ET\nqBgv47hWi0XKTf+xqzjDLH7JwFhC9rc1UcGfMuMZqgnJDNixoDDEuEWzVVXH4aru+nZSnrR9qTKH\n929PjLPODuMakbM3GIyR9HV6kME5yGV4VEiHyg53DuBDhJ0RHWM4Ys/qcaxQ6UuRDveZJDzyrLOF\nsZiZx0Y1pxmIHeD6m0eXFBFClChI5Ma447jAxcEQ8o/YczBPfZlnYwzrs4/fUpWMXU7aHRMm8tKZ\nEKhVWvmM9Ixq0utXFekiAB89ZXbJazG37ylk1lLkjlLUx9ZXWeovJkQ/6uPMFDHXYfJbrQvib5Go\nQqPQotywpctQTJmlkNO01uHjhuMJzX+2/c3AJB/tSr8IZL3HyzE9OBqoR67M81SqqPomAyPfhfmB\nYei0Sh26KLgK7b64eYaQgYFbknxkL4wXgt8RJCFcorz7Xk0G+L6HBvODls98Jx6mZfgi9puvc9/c\nOeAvKLMI0/dJQJ8GJndihIk2syt2ACBNr2255ndLiSvzJc1WC1qu1TBYeqIMepsKI6GRYVfd7njI\nbvHTsKQjUKEpUpkHsJyQ/k/1J/aKxOD05cnDjBJ9WzYgeyQGCXlACTdKbWi1lAk+5lH+Zz35SUnO\nvTQ4v4PurmCDExFdEpoYbIJ/OUEV0igsCcJsG97mgEQJu8Hw70vqOltA9sahZKinwkecb2zc7e14\nh41JK1DiSr+DAc11vmH6tPYOpup87PdPCWqo6fXDqRaY2EsbhCxTX73WdnWLk7jpMUJqATW1cDpO\ntQEMwnhxr/XNFc0c4IsRMY1KIjDn/frSRPgFpG6pK/DXM1+uf9ckAeddhSjYJg9uQ/62VhllpC3S\nHAEEfkgtms+y5Qbbe2kP+bsBdNNOiqxm5QauwGE0Kf+ifyEM/aSwcOjZaPFj+c8vfO4CMPRH6fOA\n657iqJZFEsuDCbYgJ9PNRPxBaDCgRxFrybjyc7HZ8yiXc2t4fN9HGs1vI1cn+Lr+/JBehJmEukRN\nCdVeDUx2+RlhZZNmMciemEl0DISIx7egnOi7iGU+hbce7//5Gx72VyxWb/tbj7m40oGBMg0E6ILn\nURy2cbToIqcub9j9ErNs4w3qj8209OKU0pCU3AcbSGdw3sTkUmv2EwZ9SeWE5kLe/fGCIInf9wh5\nlo3SPVwpFxtIivTQw5NVvQJ8kN9uTxJoUEh2Q80sEW+O3vKcCy21wc4syamkumnVNzGOsFlssHZK\nIIflyj+nhj22Ufw6pKMamQxjlqYtRcg+s4LByBKF60nPtLKsBmKYxw/D7+t7A88iEY3ih8runzIs\nNP6XAMKr0rJR/8IPL9poD2EewONew4o73usIsyXo81OIhDWktOk8FdibdKHxWnAoY9B8XbJN0Kyo\nc6vZMwJaIzO32i3zhhkMThW4wK0lQwjyEtW+owV4qEwElwRQt27f2KtEC3MegErLMNt+0kf9DzTV\ndyDJ+eaON9JnL9PuumCY/NsLfWHnEzMY4ghG8BlEnQ31jjIiWjGCbkao+I1IsTUWYj10ID8+q83J\nb85+VUCLBoGLEelpwgJJyVSQsa4Mc8qQBep9F/hOJacE1PCvsAWkgRB4/3JP7W2WBNXlA0VMfqjM\n2ZXxB1j7kQ+/iSu1ktxYVfaQ/IdkXPpJQ4NzVCnDtmP7YBCy7dN6+yoBylAMeAMQlcRNJiDZvYyR\nEGK44QZ7Ll5GJZrBTnDxw9EFGRHCQJ1dip6XfZDekBqIABEPHaRpvfQ5m5YYED/ggDL8713ImokL\n5uH1kabXWCdz3m1p5y1cgEVs51Yhvv9AI8AUwh5ynrYVsQ1lqNv8ZIWecilq40VefHj4T3aapWWF\ndnE5XgcjLdWpAhyO6jNQyrf30IMlqIjzS6kQ4YC6nMdjOI8jporAzktoAtU6jsfrCJewc+7bQ15w\n5TOqqo9jdLYe0oEArSdy/uO3xucd1eEax/1nmdLq5s+egSnhR/zXrdAO4AqECiGH3XRWjUm6goTk\nlPN90xzIicO3OYDkfPQz9zUwKns0zGSCYPIUak25k9bbpJzIwY7V5GSP/ewkk5IElBp6ZD/Pwomx\n9F1Tbc3zeOcT666vw2zYwGlMXTXayucLlmbvA92kRgEfZnGAMA/pivM5YV+3+KG/N0+b54tMQv0j\naWVr9zA8EGS2h7skLAfjaqVcdY3e/cYZYwg4ERkAGKIGacIz74Cb5RUel/Sy1dJpL45FI8lpvJ8E\nhzLxvFfuT/coTySlUG2ZvCw/AUITy/hkF1CYfY1HFRj3IHjKgcbgTDvqDGmKR9COnkHuvp4GlqlM\nP2uTH7eVYfWV1tbws63qaaOSlhsNjgJAUz2TLutQxxJ5jvGsgE5bEAh6MLSICxKaPlCeSPvEleAJ\nQU/FQ24az2TQFvVt4RKtL/6HhdxaLlvgNlh3GvcLmZWKr5YXvzNo2asT9tigFL9lRr1tCmPuYC3H\naN2sqKZIp9R3xfsizNZGpojcdnZ7brT9sDoZ6NNEJZV/ID9aFtZhy0vIE3kMbZEvtlq0Uq1Jhe4j\nFtxMe9iW4m7bOqkthCAOBcpQwXKT/C9dzEjEqg0YMwo0xX0R9sMLiegyL4FXBxVQh5NkmcMPP24N\nvnStkopZnC5KcVeWvphq9JYvXeFsaagzP9bjQnSE6AZ8m9S5VQGKQH3UoaTp12co8DJoaEvHzJ+/\ncmSr/kgjTd6ltRTNGGlt7N3TkhPwhWg8wk9DgCllsa7UqQ+T5L+XPH4LV3dw4fi4hP+c8z7uoNr7\nYSYgTsbF4eTjq6QNZzI0n41XUMO5FeUyClcoHts25Yw2SlYF+b7JQgFnu5orEAOOn8IqVesTLfm5\n9DtdKawcRSGAb8XV5ejblrM/Afab0xKYyKzycAPq+dHXvk2QmVRhHSBeyc3subP0P4Ro9SV/FloL\ndZWBR8wSY3XQalN32gX9tx+wcG4EC3qbBf+UoB/6u5GCN+NdtWEio99RSVR1YsUhGCheQMH+g/4o\nRrczOQlTCXR4FYHjEUjRXhVrb7DdRsTV5ZH6nwHszQWXyNtEw4wN/N/E52qxWJTG6kAUqfY0SY1I\nte8TLfXo5vtNL4mJIM4GQmhZ+4zJ8VAgytXLoX7qgQ9mIOeonUYufNKX7uibfcLJFaD0FRMt16LX\nr/zFz1GWiKp1BeqybFddqJgmmI8MOsBSz0cnO+oAwDNgXQ4i6h5ynRIBR0MAfH8WSPwd3np9SIJL\nsezmioC1B8tp0hiYP3BW67Ku/iZFJ9HyRohWnvBO5Jk9pP2NyaKucC1jSrpymQ8iwJfmcBWRB1yW\npgABcAhJbqHNhMpangAPm+r3reBED0uTcuNWQGkMC2euF7MfWCmtKAN2VIQcMpqqp2k8oKzq3iOZ\nKPRwki5nce+rwDbOHY8mN7k8VeBha/eq+CYw/qI9IY0FkQjNsM3l/DV/6QVQQGRfyv8RkyxPUSnZ\nGBOSvX18InmMnT2YG8I8IQ2nSw4sjJUPZ4dM1nYHhzye/lobNhXIG33JakzOs0/BUJgLOCJgmVt/\n8cfMvZgeTeFlaFU8pp3rhTidSqOXpEZ+iZx2nXQkq4HiS7wJn8ALIWSkcleBVr6yX2Dmcv//orcd\n8mpMgtk31Cpvtm0rVTsQwWjOax7vYFvio7Qij0mkAKzqAo24ySCl+a7Sz425USmowfWhW/g6aje1\nckcIcGoqmR1xmTldgejsQmHh9JuykFAm+rUCgOuiqCSe4cwcTXR2CQ/gl3QbqtT862QwqEsatCFI\nHz0YD9/MTQrUrf+jsxLe2vUk/bdrDvdE/42q8nBejPpYPkP2IblbcTO+LdTn22hiX5YOF36B2BKf\nklF3JD3Vwvz7EFPnPHvmhRjA/go3w9q2WBmKM701j6Xz7AohfgPsCTkpuPApU/c4iFLzODCw88kL\nREIggR1AGk3QeBnNZA6fYlNM9KlDTAUPAofRZOMQKsR3gG2/nWYQmOkfqmUo1tpDJufNtNNI0XHJ\np3LA3e8Td78QVtc43Q93tIUPI31TYrXzJiOBUJKFT/lmxvyFBSlR/8s+OTrTWZPGrUAMN8i943au\nS+MWsWS9uL9oSiAgtjk6WNRuKdNjFaTFcdHcTyC9eN0km9TGPSlnPyADqgF2SxyLHJeTl4rfhsTY\nD4QldN8axLGcWYK44r7uze/x6Y7LNqg6N1zToj2PkGehjlzr4v6DFKmaX3hHKnQxgss9BuvePN6b\nWmoFI2a40KV20BqukuVTcdIZnMK4SzmPkFT9RE0PLh0qotG+oQpIV2nghAfCedRu4nrLKu1a4Xj8\nrQsm4/e/rxdDKPXaEbT9QmEKq/07DPfA1K86j+g2zEXqfhBmBBJh/H0hASpDcsIksgr2iP1ZgAqs\n4VZV3YmoPE0xtvbpOw/CFbLCY+B5hJrKAEv45ldLDkOCIDoH1jDiQa4/AH3n2IHsT6rNGhHSo0Ag\nEAhiuEVRn8mnujEH0sXlFe3UdXP/JO7BWUmx5EAEG7/dKS9IvpBFxW7c+QLkLSLFYUAJv2erzxF9\nLQILbqlcnvIC1g0JVbb2+4zCkJbBC6LuHrewHCKHZOIve9C5bj3A5iBODmy/uY4TH//FZnM/MFMY\n/ysSmckQb2yuGGibFGqVr77NDu3vxCtXAUuBu31te3oIPw8N8UZ4cGH2LD+Dm1R4ohZcAJr+QADd\nBxmgtX5AwEKJx4Zkcbg8lQ0Ksf+UUthtBkkr1VWkFlWUkrLFgER1W68YVZEu4xpcHS1hCcjBW5v3\nx9yqqHjCS8H5bGj+dIT/PTHz7oOE9TVB2/NDZDYEQntWl9YOoc/OkgARq5oz4Bn7E0v6OF5LLsnO\nEmyffa+em9O5JrBSSQmR5cEaNgOprrztxhZzWvqd2V3q2PkAGYpvc6L+UDClhqrznHyqTbXEk28U\ngl/NaKbQ1p5QbsHizf+Jd63FYxXzdamOFmpjfQjrDj2j6UQgKrIVZas9XLishR7Gcn4ImXpQWtKH\nkTSQo7h3nW7xHz4VnCXYX34JcCVkkTYpx2cGRvxnCoUql8N1GgT40EOS2JU9VlDW9t6jbpnVYlO5\nFQ4JkD5X47O0MaKpVDbMrfZDBz1kHggr0S0PpXGWmh1jOGaf9TZBfUxSi36xZ4hZdTUPzwHyfUat\nxmFxhC5gDpIAvm+CgMTIXSVQOLCcwv8okEEONmwPOIHtIWCb2wS/4ivYUnX/qPUwQW7bHGIoWDx7\nC2UHc4WtKuDktwCM8j1IRfngTsrjZofBo3CVl1Ju0QPBoOiHY6VZ1Hm0pfRztH2ldHSt3WyBum3S\nskLub62PzIcZ/8m17upKE2njIjiPh/3lGdxdSj9jNs4npJ8uL2W9JAo4unlkam3rJhPAEw5HoWKG\n6REdsAZG5PylQ0kpU9oRbBh+dmRXeMWUmimAYOUCc9QIzxyG6MfpqN5KxJ0lqJ7CE0Wp+1nuwAy/\nPXflZiHRrEw2D3NPOUc/ARaPg6K4GEezAup+HPnb2i8UTTtIeehPM3Doj50ox1JPB6nhU401Zd3p\nQcXjHlwgi7/GftUGw0j+rOUxuDC1cV3AGds06EayYKU2TfxSGM3Y9TygBCz2BsRqfqP88PpCFqAm\n7JiNk+YwJxS+QlA8ZGhTvWG1sD18yGTZ5pmoIGPhfRcUxhoW/a0/sJ/wkUSp7pqaJGfvTtSxU5ec\nQxPtpIHU/LpoICV3Az5JVwibEjmk6OGa999pZ+FmNCHVGQR5NwPqdzk+VSbrby69is5oOFNW2vpK\nnbZepOyvpktJM7pLa+XwqHx9EEqIC2f6DZKi5UboMuLpv/+dObRZ8JjOJHEBoBzXab5QkJFyxnLB\nNlajduFl4dKxVD2iRF50VPtQeAUm+nGO+UmFuP9MPcxvX6++yo/ukWMR8snxPBqPqbdrQvuG6Ppc\nIQT2RctD+e1FkVrBcVOKVRIoE9ihFY9gle3jow3BSeSJwgLk673xJPrZbFPQk6ON7Mbg/Ert5Ajo\nlavtk3SczrNoCguiCm/9i2ojC12x6nopmuUP6OKbij0wL8zf1tqN8MX7b+p21MO/G5zv7MLz6DWV\nJ6gPxWg9UJ47hl+60UVqvKCbl0U45uHW1q+AccJBGzADfYGR6mCcFBcsXjkv2Wx+Gus8OiqFaKCN\n6sDj+MkY+QsF1GcKTRC/LUkQhPuDFQwQ39Ri9q2Mv15mpEivd+I8ydl+5NfiIRpTBoS+uZMux8Fj\n6uyzcqEyajQppiHRwJQTfgG0QDA94vVcrSh51WTwN2iJJ7Nv/E5+rBRzq2uHD6buOGp+XyKxiMf/\nNN1SVcPq9swELF94AWbupHrFR4UrPJPZBMbzOmc1yTxzODr5idGSqLOJkc9MtyuW/d9LkHjcpqJR\nXDigVAx92D222vJXQG8okTPlPe2z092u/TGY7xBTV1RE5ijVSEksqIsdyt08ThpRmJisr77G9xOp\nY334+jHcUV13+Pbj08pzRxEutdHvqJM9ZVd4YZPFYnN4LdPSiZvgvC/Kiv3+UHYG748gI/nZQu5r\nSkwtjTEzQxTt+brBJKz+XuUol67jkF9HlIOlpT8TX8rAeBGy/SeK9MxlKzZwauTob0JEdTfQnFth\ntPpqWq3KNKSqVuo/tD71SIlxt7g6P4CcHuYpWf3u+MUm9GtlJkOzM3cXZsZBpbrskoOHJRDLHIHh\nriBtwsI3FwMhK5e42TL/jSpQkDK8TOITX/jf88633RnQkyqTUuv5R8kWcayIrUfVVSPfDNkjtvE8\n3XIR5Ve+x3ZCXM39O0yBZNn5wvn3NitjtmztOafTBDJi7kEczRGd/kDBcdGbDM4TBMGzJwuD7HTP\n+5TZMgAq0GZkQn7r8BVMS0hs7qnQHMSChcXlVF1jlVV8ArDt6zY72Zym5mWhsbkv2e3e+PF6O0iQ\nKebqywUILRZU9bv5H18p2fXl/Ejo0wztspwTrxV2k01MKLBco1f1vBuO6781PcTZGPDLetSxETcN\nwyahDDoeTCf5oKLKPIIUFNsWsRosW/RINMQgUNjw4cDN3VTarjX8rcWHU/XYRyf4Kl7e7sR4RjT9\ng6Q8w/a1u35c2boRlfR4IpTBnhNlK3KZwTK1joVco+miY5FX8pjStD0O/a2AbbacZ8iMl9Co1EoT\nF+lR3sG7tveS6ej7gl/CXyEM7UiKZFggyTu7HAnc7TytKltwGj2OQkNmfof82uAPfWK05srRyDZ5\nIGNiLecjArla2dWqjy1kxt6EtYFX+PNRQqVNtV6UIO/Wsv6RUPfENga2+6kx4TvgkRhQXP2mn+Jd\ngrH6rfydaZpy3SIBHSadN2ODFYFppdBuoOdvqluuM/ajYFNIEhy8sVcqRcoVXaTsAaNEO72D2r6T\nxorI0ScFcGWTH6ApgpNyY/yJ3vsK+ByZIhcqlcolzk29NlGj/r/KrbU8vTAOgb5Y0KQI3op+CGUm\nJ1PSLajImeCKbaex0+Nf7LKg974bDUUhZ/LDQIGeXspk6z4cYFTTxpMdATtTH4zg5VB3nITd2+Ay\nwTg4mWBhErIjDzwltIJPW0TWDNmeDqs8F7ORR0GuNYlyRLNL2tLnEIedm47lWarFn9G8lVBWg5z/\nz11q3w9fHQgK3b52SLmI2O5jp0l4mg+Bmr77zlse4ee6DMBnTKEO286kQ6O9QIZkx8Cj42PFZDcS\npgtMUlsO7X4t39TywaX4GeqpjbCt8uWsEGBTn6ANYakONiAmR7PYbg3EPDZPfq7Y/+Ub/ZutfBCt\n5NrB35YqXXfY3Ty+cgG5H5HrYNwMzhKtshqY3/+EZAEN8h46cdBU9r6Rw6lcgQw3d7iDMTPrFAAy\n96cI/qJRr9Nu/nX6uA/MxAlzkJPnmOaDKoUuMuGY0x9QWqq7H8rFGMlAylNVtgoX13Ktf9qg6KZB\nOFyN+Ry1LXZujjrlgb9plnV8upnolV9MiFwXACpq1tmQeEtd+esuBFk/fa3b6MQx2IMlijbxufvz\nnZ/so1U1q0A3Pu+PWHnqjDEfF/uzvIqvdZDeMggstseXj/3iMND1iV157nWuymWHIWKB4ZvO/zP9\nS2dnfgD1bg87fMqh23nHKwNRazPvtytrcxvGR7n8cHKHMQZZ3qksU+EPJ70iGKb0obFrzfXAy9x0\nJrLSIzfTnp1e5uYMvvWqLspM3/x3oI+1uL1WFRepKOXOFTm0CttRPZ8cmfZcIAKBV27rsSptf2W2\ndSRh+p5JeW5zxqtojg/+JormH4skHaFKtSbDZNqjq5KoXSVuyleNKghDwef1XxMDPRByDAguyZKO\n0jYbbV1ae5BPcbX3gDPgbEII2kQmFtA/UJ5DfdCDvLOATn6lgdgeklVikzQPDUqP1VlFFyJ6J6I7\n8JoKsWGW574LnCvOWMV794SQ3TqBv8kzBK1yGhf7TkDtEV6kSjIdEYHLMGe+TjL+7AR9yt4oqdsD\nbuiLgIxGW2Nk2z+UtLbkR43FWzmK4OBPj/tcloHSzy60NG8BYdQWMhXcHHe3kqBnci8wrIqRtfmR\nWL66uaX98eTPNgqU1ov+hEByeXtBNNcjzv2CUK1DDdD5fbZlhv3DVTTELHT48fHe0S8uDE1dAbAS\nw1Wh5NMcy469oi+idswgPVB7STOzB3H10GRaOBMjFU140G1LdCcc7HYrDfiKdqwjQy6K3uvBUEQ/\nshAdD1J3fATU4C37PEypC20dq62jP+SZXt11gfZdZJnu7E9IF5ZGCXoLzWqlmtEbFAlQTHNyxixx\nJfmQb2GGJohDwmO56SafJWrffhCy/DDzEUQjFBKEyVoK7DQ3u5Foqh/jzQpZ1zkIDhqGZW9BIog1\nRgWSnvrWkL4j68LOpPpEi66gIz3McMNeiPdvlpluzLSkE/7aTuyS0wr/0ecTcmwz/UnqJLOfU3ZY\nFsdejeFsUMx3GQrZEjLBIoXmp+Iz+odye/LulssiNagL+B4M8iS2xqEFWipJOvRKoF5inAKKAS9S\nytRRyJchX4ncj3mK9ONROkh7K2hQRv4k6Dv0SMnaKSpiRB69Am7FslgQHivhBlypwB8GdruUSXO8\nLm/mwHgvju7IXXaeGjmNYaJutaGhqa6No24CBLzYrInc2cJTl1sxkhlFUWfnamQQcJNSPeG+3la0\nS1kNtYCjPUf2vkH0seXFUgohkjK0iKeWSvEFK4AWYS7NRcvXFVj1dFrFGqmxlofOptQ14hN9qlu1\noUTBAaM+4s/y+q5BrEyw0hc5r+tVfTOEsP3mDhXRbyKqmq1/n3y3bKxRo7SsHrSHvaqYYjwrsJap\nix8F2Gr15sOCR72nX41QSg6nCbRBjTjXTLsluUxdE3SgE5KWl/BUnNTJMqPKBnb1LqdTiAzROUFn\nXqsj4wP3oz7i4KhKxGlCrwrX4hn9EdBAZ1HHtDx/MvSMp7/WzLggcgvjGsPdujAgVFO7jvi4jpnd\nrKQjXIODtL9yy9mea6BPgqJuYM6MzR/L0lNxZ74pcQwaZ8nsW2FW21sJ0GRJ7AzAA+2s4TLYnc7j\nPVZxJhhMC2kqwngObilrLwfdZ0Hwm8YgFNSzzjzkfPohkOuGD+zcSazyld0V9APzlTWzA2/Xxhvv\nth6efSdiStzd6tXyVT3yL0zh7RC2A9OfEgN6uf+ScIVeM8DPulgrBYNT4zWtBnhQy0hNb1Qu89gH\nNsQzgwvgGFczVUF2b5NHMJsThXQMQ3Y0hlyiOEod4sWC0O2HaODF/htR/a4EMvkFlKVJDJe9mZ1m\nC669SZguCAqjQRWM2rPLr6/IrXgVgMuReHqLdu7sZgQLQyRVRkb0oxQQt/B0gu65nq83oqSuTLBs\nvh1EJL2oMDMn+OtgDFZjBdOsglkGKrm8lYrZzQv+SToQ+th12nnJy4RDt2ECan0sGhH/ZWodRiMW\nd24ZoWRHbU2JF7WsuBfDgHFeu+UR/EYrU+HrOpNd2GVJQX1NxBAJ7BstjQlGrJtNh0Y4Bi10DlUI\n6MNEGMDcD82xznguI7CqmYfqTOMOvdwBbGCIHMHs1cjQfxFHRmKeCAEmYAiU95m4obVlGSYx+VZg\ndKSnwzXyZmNCbTuu22MwY0xSpLTjem7eTM6R/usfspXvop5nwczSqIFCgrSpOWUf6KtgB0Mx5rge\nWtzTxZgffSQBn58tpmsMmL1MnKYgKSZI0oi59OT4kod2rcE/CfPdCYjCe+bAqyLMkKe2IPIZ1MXx\n7NyRbAFwd60+tPPSGPsSGSGlcSAq690Yz33JCjZ+mhuhDcNc0nHiV1l41owGtxa1VHvIHgHiexUF\nGWv1JrwSAZ8pjwW5shrXx8ZyXtU+ZseRuMNDYcLA9EztrhAoA3OEdOfGHCa8LGYn31j5pg0U3wBh\n2EQ6S/sjzzL4kG63kMo+3Sginbbmm094YPjKQzMx8EW83AW/+ovkfJwaHY2yvcD39X/zU/FZY730\ne4WIHOa1t2fR6+nDEQ6t9lwNMGZD6X0HNVgfN8N5sCDtmyFfeuiefB+U7vLSM6XQgFWJ7No53XBd\n5olCbqn+QHUlnJK6CK27NQv/LdZEMQJeYT1IIUC+gCjfWR3NI9qf7+sJyS7X3UjmEu27Bc0biG7P\n2Psy7CFEjiXzy/IVjWARYyA8BYLQQNBbV6BK0HyuWChfziETvhptQip2moUzYUDrJneAcayX6NHg\n2G0P+/pgoMWlRRmnk7BVYbHRV4S8Xf+GxFeW6EK4nFlo0yRKERLoDTpjB+qI9s7AEjhm1mAMopWq\nSiT6b3ykbHBM2BE/UcylNjIYA53c/YgylWMuJ2e4eFLjdJhzGhizR+1hL5WDbSFQbabnRjxwbIEo\nol2oXfTtOOlxuTNZz9Bb4159etiVpN1G1VxSBr52o+5s0h//eZu13gf+YEUsxkYZ5fYJQgyytfY8\nwCE/L4Oot1CyEztoIvOygNnqOZ0aySp0Uqbfakg+nWAlLAhcNzrdGYI7JUyNIZT93BhiVuPLm8xC\nRp5zgUHIeJkdE5KsTy9uY8l1gkV0prn1SZxVqvqTz+ocSiMVY2xvFHswa0tcuee/wM7arDnAskGS\n8GnHGdH2qR0J0TOHK1s7lHWTRxO6cFj3uwLWELmMno12M4s4+rz5DWZZV+vkz+z/fZQ2HFTiR7MW\nICtHehE61dwsqginNvt0sLtynmS/s07dSxcka2QUwxffq5t+0caAkR/uRbqkFBruRqE6kCivf02N\nlg0YhF4Bdgudhbn5dx3uQFdtpnNKI0YG8Orx5GjnT8cnT0Rv7GIek9AApWGJjd7dtY9z4izLIWZI\neWqp11vLVPsbK4rNn2R+Zez+M8prD3a9JHt4iRHT9uoyna984Wh6rwJLgUE9Hx1rr0Fc4Xgsm5aL\nH+qpQ7E5IVGY7OXjXeHZdR4gwErxRdK32Z1fEEvEquoSTobu0QXky9pxj9pKY9HA0mxR6kSDWLZ5\nyUGio1aTUqAZnKM0jFwqJya4OAMvbVmgzx++BFtamFZRpX4QT/bhcUZdLXe+kUNezEUdyFqJCRgr\neVo320lhi8lJdxRWaSPWCogMyDOrUCEOAVfO/cViJQqH5or1djzjTlIFlyO3cYjsPyhqxaZ1gplG\nj7obkIH8Zquc7sG+lXjJySmGVOpL5988rnUakIy4i4/2U0AdNvxMUOLQHpVQtatH4N2Rugw8RM18\nYDk+ol26XG09cF4oGzNBSpXXv9APHkfzvt+UK0wABXsp0P6b5pE+bqrW+PdB3w+vpPcK6q+/wR0Y\nQUHlKsq/mVneppOOV8tV/GMkalT17XSUDsmrrFQ8mvSXWU4bGW0fgGFBFAtr5JhqnRUifBqnNTPB\nMaei2DLOmV2aYLBbiL1TN86XVJXQgF7ggFLb3qSaANSnn5z7D35GWdaT/bB6ZXlMnKi2T3NOxBJ7\ndeMz3/gz+gAODfK++98DB+bi34NP6MBNB22S4Q0f436OF902b6abXMj8rVJah3ah5oPoRD/KTICL\n9zODm8zEK37XUjeDOTufY6FoEa8dYl+jyf48+YMnRc78WehlSRB+lhMUgxM2O+8cCFQ8ggiM1Pzn\n+E/xi9Qv2/0xCMeB3O3FDt/6qj79h7PKOffm6Lom3iOTVdZkHxpCrc5eJE8KYPgICQqZXeSFvXxh\nf/RZIW9bHUqYtCdrPkw1G4yw8rr04RPjUe1wBxGYriDSW0aHLDD5iJ8l7SwybTWft11+X/eWC/Wu\nIjvoYhDF7wwJt5XfTq3xEYcTRP+ZJXTN96JhwWExMhrfJar0al2PWiDORpQX+P0zwhcjDHbpwuVI\nCyock3xoz7yYKIoq8fa6ic9cZtFXU9tNdTah9lvQ5DvyqZz9mSXUzwb/RmYxzuwozgoja/YBN7tS\nX4Vb9LIUX1vjHaZ1OxPZVCVIByHE3Xb8hks85fp4Qc42q1IdTZsnkr2Mf+vMB8hm6qm4oEukJ5c3\nJMJJqbSCVwB3Phh8oTwdBiF8tLFblYn2gGdSGbqFpU5LNfvWjYJdwvPqkdVc0ojtpV/GsL3Xbr5X\nU/kqTGsDjTBV2rzmUeMCCXj3SXgWhKqI2xZqTi4WQcFj1jnpcgym/87qNSwSQBVG1xl5AV7GdE0k\nf2G592YRfa+VsJEs1J1iaPkzhb/+OCNxPoDPg76AC/y5n97l4L0+PhFq3geFvYbEiMsvUUfZxCRI\nqeWjYFVPZlrhl13cjql28SuITUrGXa/WpCwZxz/lY5lG0I9pAYkfmIv/mj4Y5picEiLS0m1aly6x\n2iTF5v8cxOOuQM/Znhg/RbAdCS4TXtMRWzH4hvXRu4XokYez5wgY1lugR+K2YRg4467dPo0ERCBa\nrcjhMcnZAx444K4xRdO7IMfIYxQSamSYOl037gJukH/R6fzdbcUZSB9BEjWwzw8TGhCCtNHcGnuV\n3BLt2ltl3ym13DSkR9BX3xwg1kuC7PQs2+fnPE5Z1xtObMEudhVKoL/6SLhLfOvMoVtJhJYtne+5\nXFfo0YeDfAuVDMYUuCiyWb03gtJnArDW4KkUk1Kju9kTF0Owfy+fim4SDjza7Z0ESTMs0IuNSXKp\n0OM2h0k6R8U259a5sgTQqEuG6kcphUSNoawDiravsRD9/leIMO0J8h+CmNkDnUpDHNFP8/cDyeG6\narSYi98nI7PdVLi2Pyrl+CkLbvmwA+Mvds6i+0Yaui6omk34EUvTU5G6CaqIRvjfbRUB28SnCXoj\nLqTsifGufVmN3ZWWCFWjc2YN6AkVlHNJ6Q+9C5MqINLWEbJMQfEYV27EJTwzs9mmLmVS9c2Bz6Yr\nB7Ozm1sN5UgirKSgog9bqQVwwuTXFKNISDkeBBi8N8KhWlt9s2utbDolcmu2twgNk1lzR4W1o6ov\n7OW4s9gZDeS/qaNeXiM3z0d4vD21oBhlWz4ZbpLIHfJA49qHa7NWfVy+8W38UGpau9CYLSZlFPek\nlWM0rTJ3tiORAbvuMffHm3kLq0NihJukwbZ9nylOdR30OYmlgYFZAln+mIqURzoTPrduX5YOrqaE\nc8rBed6lu5Me9EStjLj9WjcKJP305E9fmdFTEpkcGxdM5lqAPEMD6cpvf0DpndZ3YUYWUY6vQa/Y\nAjzYmU1GFVRfIB6G4czZ7u3bhNtalpC6d5AKPrubRvFH3ZMzvbvJfi0CrqYUq7+vWSuUgpzxhumr\nalbGdJ91WbUO0sIzkybYU4hLoebxATqkb3+ftR8aICOHFS/r+K+dAJKsE9lr753hl38utiItXB+K\nTJaDpxzFp0Fexo+nLf87HAmK8NztoQtF6FK8gGjqzvk7MuJ43Ug/+VcMD8YHBqKqus2wZJCw03W+\nkiD6MQT0JrA9ZlhIPCRIru8FnLwRm67mNBShI5U2meMJCnfel8J72tyVQV4MnyJtFGjnn4EhTVYM\nfwmVqVbmjXbPMR10M7GrmYQky2gODMpZGH0pQLYgdMZEtahDHYUgdSTgQOIJFNzrkpQBxLZMtz64\nzgW2B+VmiIGoCC6cJCFEBIR8ZYgzu8hoQ3duxaVrFt+ShCQxHGnMjZO5f8frT7VdYJ3VDcnO1Mcm\nzfyaS27R2Ab+dki5Y0voxHRqdf98XYE0INunOID+ds1le9U8JAW//1816vMWqopRIGj+deKOCB8T\nOFtc4WdD3uNFGd0aiXqtp0OXn5DZ2JStKHa9/6fzPgiHqUtDkzyrkgUupdA9ierTUTkO6Dxq/+hY\n6RLjKJUcsAb3eyRkMVvGmvdgdzhXcYl9Vo8Mui5jlS/hSGevi1rjLSe7eO6uQrXuNM9qTXqdIql7\njJh8ga2G2Bq3rzMVZ6f3ZBtmGw501nKvYPADD3RfGk1oHc/tVI0o/tlEm4ZVRN64fKOU+kUCQm4H\nm4l8uWDe+tvTczWZCTr07FoTc6G3yXeHfmu/LQv1CBMal4XkDqEMTAjG8ZetZTeNBCV4DciDx3gp\nz1fiHzETcw60hDwbkb4mZAKClwXLh+SeTRVa4jYTLHr9V+raQkXp/CAgOyC8O3Y2EPuPVghkiwEB\ntENmTAQYySf2/W2gq1Yuvx6Mvt5xZRRGvRcrLHYXljZGcLNXNOqA4wUVFaZ4yMVkwoEmq6LrRQnI\nh1X0I9s4nP9STPzrhn0zVPXvrNpLD92+R7axEdpFzmYvUuNluv/1c+TTF43OPQDqoLRUhZYYgb0R\nns663uxSS1GqVb7EwPEM+NoLh3YNlK8bW6gFER4VbswSj80rQ01uDazf30onEgPvyxDHZM/OiPui\n3q/eIxsAcUeJjtC/A/Da/4qMLJR/QEEYvyAIw0J6NoYUHJpI6JUCgVzxXSQJvHwGWB0HUESKXXCi\nU5SsfEn4Q6d78Q0q4L8/w5YAp3b7YUJcurpJL3x3LrQRLq2iuo93T04CTnopEnar4WaJdy+TWOxe\n5RJ2SAywxk2JtnK6xQlkoxxGebwnfvKPZOfPxEnHrU/o+3myrxuTlDhrlissPXhy1cQ/5wlQQe7t\nNKQ/LNldhCNsVEJDAxU/Qbfl+65bOk3ACnfmGItvgWBn2xhQgEkLP++CHvNRQmxLWNW0mMjUvGk1\nUGkOTLm+olcAoMnGZ85BinWxawaHLlg32NPk1y8xiDmAtP99awtsMHexWWHCl/UVisO9zyo4aHft\nMjOX/4GGe+m0upqmIk6bTizyPnJvVIEapVUSLijpPzacapRO+8SD1Ti1eaHw167yrkB0fvI1Aa3Z\nusNb/aWhOD0KaWRled8syK5+GvtWG8ojaZEX/HyV+mvifehWGTyiZS0iCaK3vgkfGRTfxjOJNiKe\n7HanDYDQqBm3TcyrXAWuHIl9R9cUvwqm6lpA1qrFbBb86tzT4Q/MrV6S52AvqZI/2NipWUjsjigM\npr+tC4RloteWtXSfFz0rTdEbsZ3irbONILFIYtA/RN3gRF5Uhp40x+hfpmIyfZf5IRvnHIoUKnHh\nTMfdsKD4o2c0G2RBrAb6uEeGT9VfuGgfb5wpMaqqfVLC3uRTJK3lAe845JIlooYJxZtlMRNox+ge\nQJgH2Ae9omJ/+jj06Y269PNN+T/s8Sp5WzzhZ2dES38SYbZFqiRIwHxI5sUxRE8cc9wr+yjAbFAZ\nq99yScVmFKG8tE9l6RksJCvGgLmcIlQvSdptHJYnZKEDlrxSf+Vayy5NsSpPUbsl9annLI9GvSiP\nKRweIqmpQ7eYK8Ca1tVg+/5k1UbQwJysNetFC4DNPSkcM3hDeGJjoApw8Cw7FmGPuM+lSdW5kiWg\ncjuyy5ifQyqA4qANsb+4CKM49oJeDL6NNnGu8RpuUtYn85Pqu5Z7BaH3PWyq+LxPXeTlTigRZu9y\nPIsWCivXn8eKQfuGclZCivkiI1E0TSW8WzRCA+rfbwcfYyX2ve3/20z1Tsf5dgCQfmZPxCgh28sR\nfMYyX/kM9rXyd4KaLmyZDeTm3RKrcEIyibPK04sZtx4gDcGOHUN2pWGB8j+6gzjPisA3JzR0iEiN\nvQWfH/nnx7xtvOvJ27NPPmINSmSo9Xh5qvzNpuUmqPJf7UYjD0wlIUClxEK9tyFPn5e5XA2g3OKz\nOMRWgGjtyMecAFMIDEA+U/EN8t/qksMuvlXnnGgGn2CVGPOBQCD5b6vWoD3XV7dGtPj6pNTPW2Eg\nGIOwqEV9o/VW/wqyudpAxdRTpF8qiR4KmBv5ARcdgv5i5TcULLwjBKCkjbX9Q2x3+I8gfuqiLo1l\nd1IIU4qPQcMShUiC1PckKyBzlI5eeI95nf6CzGU4kvcAYyoGYkfgR7OYfomycYeWqfayyUz9FGB9\n+oZR7tlSsOn1uVCYqiq9JH1LR4NVRpcQjQFHQrMdPIy6lxkKo2G41c5uKJV76fEbRBNs2/to8sIB\n7U9v/vI1LPkghMZ2OR32TEyP8okF1dnafb/oovbewUDEQRsNoQG1ACNB6e8bO6nB/g9a+C1A4/ON\nTkiRcLiAWoIG6DS7CAyGiwciY0/FLyyrbLNqBwBN8I1x+NJn0kUKiOGILCe+YZlMgjSAEL+XA3qT\nGjz0xD25AoE416vIf5LT2MhovIITPxKMIilqVCmXWMpZnTNHh+WzRVNNeGU7EQb8jSRQ+f0liQA+\nmj+kU9npGVF1ZReYrw5Eo2StGhiB2QqGxY2Gqli3J/NHJomp9AScqDglkqpoYb92aFHN23RPvK+b\nxx3fwqg3WO0qhcZKtruvJYeIjVHlx7bshnMwYkWwp6Iygw8cQ9hy6rYDZbd/tQsvkcIaier7+Tyz\nwQHJaKs0Gv8XfgTHEf9gyt59BHn2t+ETTyQgMhXvRdmkwUVEND3eWxrLO38bjW4fc4AKx+GnBedp\noNLMuetW80W7NcQlfE0bI3US37+Fd/vkIhWAX9bd56TJrR3W8DT6HbMwTTJeKXj74yVP+K1rh7lU\nBTDNh8wXcJTKwbzK86+2IO4DsfzT99YGp7iSwErVrdQRYglnrO2gA/k+468xsy8a7QE1bL3ZseJL\nOzOtLl6bNn1SJFfNhruWLsIDSvts6vryW3rS29ip+kmH3IEH77DnP/K4yoMb5g7SkEgswY0vtp8B\n3lOOCOQAzgCOSe7p5XCbs+K+q6uctnIS7cxdBQhctpbDUalpukz+sTQD54ZRmK1QhGSfivXSjH7O\nbaX+2/vPcx2g/iGNEJKieNryWGlVhR36foASl+kkd5bOPAQ9LFSpqc0kP5YGJ3fJN039+fFenMB3\nP9P36gjhizFWm1wd9fqNxnEz7fhkoUkupKxPlQktD6pmUPsFdOkCUnkeetWiZxYq45z7LDwnj2gL\n3saf/XGZAkwuYYCAAdmwLCdVUXWfD6igI9pXTIvxnWQuZYO1MQ5rLQb23KtN7rdhnt0NGf06yCth\n8Jcvld7N18QciItwHZjjx96JdMI1yr1YwwJgFguMu0tMfLWps0OLShZwDqPSqMlKfaSuFN55Kg+t\nRhaNKfOnytEA1OV3UGdqkpQ84hD98Eh+xvWDesBL/ktwweZlQO3HgfAn1hTgUT1aT53EYJqQNGj3\n3w2wg+7c2LYECXHTcmfGGYbY5v+4F5M5duN2qKG3QgXZLP5rIFh3K4GqrswB59MTNjUCy/JweIPm\ngoJZU63pAs/3hFpGxIj4azZO86rnqRtPrEuD82h9thAWNTDdCurvW46fob73JtXeoM6GvIZFIcWe\n/9y+y3avsUYqpYuERJZvYeX5NU7ofYGqunZ/RekTo0j7aprv9T9Dv7SVOCXQD0tPYWg8uPfreEeB\n5xdNCbLqFiZA9/B95Q8kRx4JOU3vKbk4YHiwGDQw+tiXyYsW7Alpg9y1nOY2+wAEA0gyJlRvHKBQ\nGlfxbpdV56bwju4Po98fKR9oY2vXk0vkcakZ3nWYOG71Rv0PXScPFPaAk1HI2X7/m8IfXdNWOoAW\n8wFOLZOjF73MBaVpSn21qmCEIy5QNWX13sP7v76vrLF6/tn/GYNV7xzALx5TEEBTQatydsCyJYSo\n4iORbwOMK70gW+I1y4k+EzKZs/BvuGRhFwNGDLfOvptYxHaT5S4lN6orSE1xrw+czYBhY/wyxwqP\nx/+TZ4eDLKDf7bg+fajRwfhcfDjCSVixpSQ7OEWTF//AMWjcdIBF6LVMUVpkWcWlfSoklza3X9IG\nCi5ETxDWvwIaCODU/1GSJ5N7EHQXuOKpA/EfKvkmS9E3wKBwQ7rB8eb/m/9ZVwc2fflc3FIakaH+\ntdyt8TkrpLfu6fkDWDJ/3UpvDQSPViLOmmo6+Sp6P1yNVypHmbGo1c7A6lortCq2bS5H6s7uTES1\nr3u1NmtPbsFJ6QERydAMhWq+BR5bmkv/GE2OaxUtBhr0XkJnO73oj4MgF7/UsnvRAkPfVX+lWHuB\nNWqgLY7Eh9PlWdG0g4L20GItOizuBYUzIHlz6fDx+T16f5LeNIR9Qg5H2neFVQta8krzsx+PbPZ+\nR4c+fMxgBxmZ/ziLXrHrp0Hk9CilpX+0lXzt1UxUtlqXXxSO+XqDh1JdYmp+Tzd1HFojRu1vqyY8\nmOW3DZ5qdgC9AKW2S+GTXtaBnf6HR/JjJBXYWvvXpGRGVWJjNmZPoqK/b5dtO08jnUaS7NfZL/f0\nhMayPT+zjWsTn3AuvGJdsI731yZ823QEQLcI0PnkQpjFJUI6ffZdrdYMEi1wn+fapw5eME9XT4Bv\npH0dRMY2IFP7UOcuEWBmPJMiSHARY6+Sy33GlwcwZoNYAbi5B/1mAL00nSoQTWm7N0AriYVqhHt0\nNHah2Xv9YCqIDD8+17ZEnDSKPaETwIQu2ohoW2cPJAJP5cWMv00sDY577czzwMmITHvKga/YQeKC\nLF0CtGv0nn4XSGbhl0Q4A3fHaGRW0ua851ZeBhh1qd+QoZVIz00NiEtEv79u844LN1zx2Op7EL6Y\njW03K2rQLT3PaFFX8nEcXRKxSAHwbXki3A+FKXHEldQBnjs2FC76VfawoZ4w8DGMNhHPJtumwOd7\nqEU1IM3DNRWrPYrTDsyOYv7hQ2prjnsrE3SPW1uy9ZkazfDtPXXJYizclMtjAUs0dLDP+DoLSP35\n0WBFWjzsSHpQHmFbg2S8gx97D8iwZwQv3I+Fc7OaxwRYtbwt2RAGFpW1dhJT0O8pwwcLN+QUrgj3\neNrTPeohb8uhGEhNtXezr0A3GXd4lt77A1ryzeErj9pOQqoXj2g05umpNE8xgMGfJYL4UZ8H4zlD\nxvkp5rfTxutqFO8Aonuas3yDuejyHhb7UMQgLtkS/udNw+tDsHs8bWY32afyNFc16WiBk4YFHx4s\nRd6sKpBQgluAen9ltCNL41FRP0ifRBKtBRDA72popEZ6UwcJg7/FHm/wjnzK3ptCQbzKVuT+27UC\nF3633T1G6HlZE8kR1kbaztXmhqsKSJLuLsxD3DwX/fbCSK39JszSHwQSp+Oa4clUkqk26KC7atWp\nQFFNjzPZ9i37HNtKV3cKdFt6VYyCNsDdKCdiEEO4ra1vFN13WSCCHFOrNax01C1a6Cyni8bJMsaw\nAemkMpP0ISVOhdj9wo1TW0D2uJLanZh+DB7s09WSbLOCPCPhW+vQ9NjddUlj8LB63FTu1xAXRSYW\npzPJG3EzUno9ZwDUpuY/V0XlxVNR9J2ziJ5QZd/qwOlE798IN08792jGxtPeuBHDMoux3rTh+VKu\n4goAXQnoPSBqtEuwW2vTqjLJUWccyt34PqVyRfgzUluMGoQ8v9tK+LL58M7pE62aThzRBmNzSiPf\nvFNrHx762bgm0kZR1eBbO5XNO/a2uWIj3lY7tHex0ipeR+hj70HyxuMReFRD39WVWUNMjcL/gmyz\n8X0XIlo98fsGfIKmXh+3L66iJdVb9ibuVlaVYLYgd2S1VPYOzZAaiMiLG9X4gwlTYEw3HFsMhNJX\n8HD1MVaDSXvqftmg/hxOtDw9wpGhFSU6lUotxYy9Vo8u19aLPrkjVrVffyoW5NZcPQAG1SbFLKV9\nvF6JFlfLXgSqXLg1Y3pyOBfwyvQiAMXW1BK7MIm2Tm3tdVce4FVOV7AAzTrGc/dbKZ+bm5PyFfqt\ned6D9yQvlgbSyObjYrRzWLnLT9fyQoJg1AGWr37lyyqBVrvUFykVHmMStwu8pIYGVqeoO11qpCDW\n3z30WEb4kb7xDvGmvgHtzEX/+D8KpfJaIieDfDHxNCDUUCcfmQtFQmqRTFePnqdRIPS00vVJlEu+\nBP3LvHrmTPUM0oCVcwzOeCo1tfAaLmqIK8UQn3JmPEi+Iax5yHCktzanvBNMA5YgzWqhlqr0s2AH\nP10v8Omwj24X6pkwWAIWXiun4TSjX++CpRIyPwoBE0r5rutj6bjuSllUDfOMai/Pn9YchhSxUyfR\nyGyB1auGSH/Vb9Z+YHH4UOYRuf2t0dhfxNnF1LG0cDFIZIOU/18LHPTbJTHRT0Mjrz14m/3ofd7E\nhmcLfY1GeGQSa+xv0d8wfQFr5v0XajOFlkZAgD3yPkPQinQ2AX8L0LoZILetnXsCKwySyQBHI9F3\nomqHEm2oqM8qLB2rYF/x4tP7D5/gM18DIQk6ela2b2ryb3QUaHO/w3adGust0r07S+DeGw8Nr0mM\n7XGwBfZ7ys3mDYnOHPu4JOJu8jfHCglSBgue3yj0BlNZR0nkZmoNcAF2QNht1IkhicpFYIL82SsB\nNyiNpwXbVDmcZHpH3//ac2cfsHWOB/5VczDNdjelwKAQ8d3HEXtTXHgeg0lWOtPq1wzDR9O0bQVJ\nVamn+QnLbgwJcWmdORMNJAcu4zikrNlpE5D/Hw8KCzGtRf2IvLbQ8ngs/fGTUGVswxojfE8A2i0A\nCB8cqi0LZzwb0IiU+Qd6k92LVTJTK4FcndeecpfTVGSw/uSFVC8E67r7nk2p6hwW8tqEZHp6o26D\nsv4asUh9j8ikzuANGslHOZvL5UlR5WqnYZ6tehBf6/Ht8M64q2GoeFf34V4hnCv5XnYAvg3DNNPW\nUx7RZ6nMyYZmyzIBoRUq6r280wJDVauo0KHkfz83pBjSXwtiM6iuZvg19tq81my6AxEhb24FH3mj\nyDPiH5Cc3W5OZygo9JsHAi09iHRa4+mMKEOWZHTolGQX5tH6Hao+V5fBjB1m74BN+6hqOaFGQChM\nzyx6YRz1dw/uPAlV3pLz1ysES2OAyc3Ihte5w6U+ZyQ9sMToMz4g7O4U2B5PikozRubIyX2c0t9x\neSKWk6RhrEBq/cMYllpLAVbzhLwSLtfZbS1kPOBmWzU4Zkiu22MkYVqdXVF7hd+jYRa02pDss6Q8\nO2Rr6+Uqr+YBfg4/XVNRGd7d+iY2IOkLy+LW1ECyGEfOfieLZGfNQtvVLpWI5IoCc9EL+jkh853+\nEBYzQx2LQOU8xR8YBB6II3N74qrS3JXLuwiEttJRf2ufYuaqCcwFxsIXdWE19tJ/OUuHIMoo4I5S\nv62xtIRShr1ompIrLpv70QWTKi/I0y2bDRVDp3SbR2r/RRe4hNuBYZDQeY73Qh0XezEF78ZjQwww\nZJwC886X6oGOdFD6OWAftqd18+NZ9K5KP1YG9d1HR6tjMC7ipRojXK3KOZQLTYiqlDMXqQcv7zxq\nPRG9vg4WG6Lbzqu6EWpIsdmL5WNmExLfTe/raOLb7ZlgH7pQMuaMmtHPghLiY3nyHlUbInfT1K9U\nm+3WAMgbUEYNOxrYvbQtlhYO9J8lEkeJSk8LGuKjPL0ee5Md4FikDm75Y+iXWDnolQe8cXLieYf/\nZ3arE2VK2nxB3kzMF7AmJUPUF8ZgDeNJl+FB7eMcDgxqgzEhYriao9m7w+AXh8lX1HJqIvCweag7\nL9MYStLcfVi8oqbTk9JadHOoQm+S+n8CSynGIVylAQHS12xofzesQmsWh+6Vq/6pCnANFPaNbrUe\nCkUD/fPwDHsJqXRVtWg1p09XAJ0fIEQyKI9Adec/Gg9V8KERDm0MmZ80+JZVOeV+o6JXdZCtf6NT\nCeVHjFOIk4XcAvymadEZ6xAlMIqEUxuHMJPyFp0JS8AJrmbvizEedf6NJ3wQou2R3J5KRWbLxl8G\n+GE7SIJHHKtolGnBWB9ue7nU3nShjfW95QMKCWQ29DVyeMn0XbU45kS3WKifWsTX55n5tIgzHOKZ\n7/AaWThY/G1vNlwym6YqVbcyX2htxvyacdvyQOYULXx3lAJFcxcMLoecV01RPnF2vfd3bZuSmLxP\nGZv/bYd2lU26l1MumD5MIkV09+olXg5pfYDcURagB352fc9r+zbLoxlGHGwzqHB39iaI9gtlj0Gg\n5H+wUEsjG3DS72EV7FghOFtGKf5MplJhAilclj40Y/JWRbaN9EhooAqgaSz/jbypBSKd7lqOKF9+\n4qKWth+0405R4HYpyBc3iUoLmiSkrDQZcTNbYqo9AFBglhP+8nIGw2zX7Uy7IvtQ7NJ+PAu4jPL7\nnlsdVXmL+zBR2kouEZ9nmi2TrwOMQ77BsSkybCVgE1Fi2tCRtYbwJ7WzWJgWaOi2ktFiO0Y0YFf0\nt4HLoD2FGa+od/vJkv3z4hA4h60dWJLfeuZfG7Mvv1gk+xihNx2C6uXpgVkxnuPpN3ZYi6+lrodd\ns35LmY3mCjPEnJARxOf4WeJEIrv/IYs3bgak+AtLCQke5bFmpl1GyuzqTiVQdiPo5sf8ibDlZZ7m\n/vJJFHPXvSEIO5rmrNMdIxesrLKxE8t8WtStzs1VLd+4gjUg7IcPtIZjX2yte/bGyBx+xeo7INXw\n9DUyVVnW5H2+ktvIeWpk5Qg9u5ddpHv04OaRccPD5JzxahxdijMdhvvy+7wPxeTYvFkf7A6qRy1L\n62a4whULqJ9+Pb9B6Jug74yNt7F684MjBj160+kH4l8x5OqKH2afSmwtY21a4+AlgCEpimme1A2T\nXZXS6c7bMouduS795EeOg8xiIC70W/1p1ueO5/Dy1enK6WAfszwiA1m1i4uI3i5a7adqduMAuEvn\nSb2b+SrSZfZli7wKIJIxtXB1yeU6tfa/fCgyw3+ay/VekCAlAggpH4VZjeY6yXwBRxLzQzWjl0Rj\nZWdRfpIcs9S1SxEWZrPje+q2nSGJdn662HyywIsUf3cGUd+GkIyktKRpmqjafsCvubne6A0WJtiO\nyu7UY05faFrNYeAekCyNwmaQvnY2FOdIjxMxKjkj+0NwyXmtrxBnRYONlwc9rDijplLkN3wAcpj8\nZlMFHx4ECIVO1xw52gTFQ8uFKOITErkWc50guHlVDK5upKe77Hv9+EGQELnV7h+x1JkeWI6gQWAL\nNI5/IUVUJvaMBxmYZtCz6gTDVO048mDdo3YMvnoHBMpqmDyrF+OACstTxELyt4szjtka1BI1AOB6\nqQNmTaNWmtcOPUoe3fGzCLDKsv6pfPM6ZwnWVY6hnGsP2GrouGQaZzSt8kY2ivJ3Nw5V0EJcjCKU\nRuUHzdY6CsJpVNRsdq40pw6L+xH6JHZSKxdq/VVfVdv881q/NIJQgXlSf1oIRYwdZg6iIFEWY7RL\nuxc/tpVszworDd6LEWcNZupedQ9UXke/iV4n4g+xZlATJWm/t/TzI275B1tcCDQuFMpgFVZnFyQ9\nizlbpgocX9OzGALaCLcfhsmcur7Np/egw2i/mDzc8E0PotDr9v+KzrY6oGtbyXOFRwx7r40RporR\ngfgDnGnQxtarQgbQRXIKSFK0ffo39jc2iX3Q2nG0rsOAgYK9g6bUKlHEdocHDnBLOCBj5kXkswIq\nDRZEaJFQUo+JA8PjPXb1IpxS4Wls2/YBASVwLl1KLRxfBVrX7t9kEvrtRbEIEfiML/AL9MUod8i/\nOqzwcUbfwKFBAJb38BpxZckmhixDhNbExsWP8yVYbjpqyo4KtyWy7c5IdGhg3Ewgxm1FE2ntKW2M\nDHxzT9AJW8sz28f77+gpiL73UNdYn3GRiJ1/vQQuAzpP/tPrEoXdyytJ2myWqdgJvxBXTS4WfvsE\nNQaLoczWEbWUz3VCy9lg2Af6dhss2AZEnNy6cYu3NF/w17go5fk518WBoW+bEEd7SRWaY5XdtUJn\nNEK0Nbuqn2juhsvmZ+CIo+V+tnBWo4eJQuWR8s6e4TcBAy6WI2eegAgJDIhCuyRYCyifx6MEG+2h\nMN8ELOun6AYxlyrteWWRriffNpiWpMpdH/Yb3Ymvu4hyR2c0/k64Kl4Vu/PM6k6Q5/SoOPXXRcpP\nu4yjJq5dYbaTx0LIIo3ZrjIXpCXVurqMETUhyZYzwygtu4FG6YskvHgmTK7PxdNAP1ZglYFhaJPa\nGcUkt3uu4dzVIlmCvyjeNc8aOl+WsMWVsgSkdBDL+FzWf1RkXDoCkoAdOSxwqHwiVqZimBMOOEz3\nnD7I3E0DSNSFV83XLZS1vClk6iTXu2ZfbG+a5662HbhywwPMcnKOw8m8AsTjsOgqvroOFTPnWUhX\nGJs0s/moNncfE7XM8Afx7kuMSc0DHjjs1t4GBHOORjcMRlQr+G8H/z8T7L9o4161d5wLjQ4ICVsp\nfbja3UHNR1QZDZdXYJLlc+WMgyhyzjrEOpykXGVamRbqnlLZYLFh7eLNqJjnqGzx8xq60hzzZUt7\nj1p4cf4KISLgu7/ntWc8pKPhTEtddeEFF0wKW6UrLC/VOXTUriHKGJrz+NymMB5ZdfCVHkdvx+B/\nZt18jux2acbho/omaPHds4K0oUYF6L0VJXqCT7U5xVfbaX8jPk61GSy+zD35xT718PSGtkUqqRuS\n2jlp9UIVYxVmxXWl8xNmfnS09fE1qRJn4t/hTijDMwlvzSUN6RacGLMcBUo2KJuC42aWqCl7E6zm\nd6W+YIXNfBfhKSl9z1FStT2DulQgQ2En4dx57tQgO1RR6r3+0Q6fTXjLAB+iBFi8WI7dajSiSbeE\nrxqYmJ3BM7qDhJJYQwDfuhjhUt8ZPBh5fsTtaFCe94gcQWR0B7gWdY2TrE9VPCCtTvW96kvQaBXz\nedFCk3H0OypGDFR+zUqP8lfJCbZVp9ExinBhSsLplcxNL8Gec/xsG0xL+kDrIYyBCo+HAYlh9f5V\nqwFem8hW/mvcDFhU/RHcoWy4/+zxyNIiilVHhQv3QN/F/c/5JWs9oo1TNYiYixmGraEh7TfqWJSB\nQF8oTvKdv+1n2Oy7uEXOgEyJykBUJR4hBirKjHdpHfbu2gB3Zl9ng0PugD5do1nBZ+F/zoXTfpl3\nXUAkQEyuZygqGt0FtIok5TZEC2YqJQ5E2V2NWVg6cA/+cvLwS3HRtepw5ci9ZMbSkjPZBis4Ckrd\nBnJW45uTdhDnR0F5/35u8SY8ocCn9IMc6jHyI8VjCgAbX7mbQskp6eaJK02Dq476k30fAu1pHDqq\nAa1aQCJMgj8cv7AfFEadB7Qu5opMNaTYksndIbyM/9ER521nmDrlxPVrtLqg3vFw+9sG1iJ+jrk5\nzQoP5vMf5Dift8Vt7EiFrLJ62lpB34zftHVeV73MJMq55MrWl5NVMUoBTBCiw9JtmVQDbtgS6sp6\neEZe9FPJgne1WAu5nECC5zJ9whJusxDLDX0ZlbtCLRdwAw3AjeAics9avfRj+jrVjSAaUeRA947X\nBxCcYOQREPpFFDdU6+O4nsNI+NiRp2o5Ezss6g5P8xrh9DzWv8NeFP2oqLwV4YL+CAXowE6ys0+0\nMjZv4NLQfs95BW+23ZTSuqjCWSya675KCRGmpZUmyMw1+ELRfkTavVsfBHbKYLKhLBvO5nQQ7BN6\nFd2x6L3o4iLiFlMmSsJU/se4YbjHBy0uWVqSi2Pem+i2yihrWj8FT6Jo4DI1rtrSZxy4xyGIJJId\n6N9LYu1XoD3y5WhtATP/YLLStWzyF4nE3rwF9vgGnp5M7irAWuJJpO8PATY1dlkYqhLsf/YGlVSS\nm8pPWKbGLQEnu8IPvwUKH1Km4bIhKs0vPrAKEHy+ah8mTkGR4LqMOhYfFmrnNQPdsqf9ElErw6c+\nUDOXtiOsxO6dSXqQpcR8A3ZHCJaJlpd9WTDTo9NIX9vdNWZb6xKJR65bgKaAPpbqs96Z+El/9b4S\nQjBze6WIfSINLVjqgTKN9BA8rS3dLa0eXHxioLSXRUiNdsVetXCiPDBU4CFfWYZIS/Oidm7EwjKU\nixYQmrax+/Ch1bljT+zb/eVhVtcMejMC4XpV0LtLMSckbhlxXn6UdmAya8rFCGkRDDuMeQbccFQD\nFPjvzMJulbKo2jZYEwJt07A5VhUw2e07FBolL5Y5MhJeB9wEjXcm5r85tw8dRzf5qU9WVnwWu5FH\nGko+iIRt6XnJxD8G+rL7MAk50rJMFhysdij8bWma7XKkWC2ZnH+3sPuD+pYHJalYJYYAurrr6X09\n5Sw4GAcz9VUMuUYRqmbaKWNZosUlE42Ll9BVNU1d8KOcw6TsxwZir70s4ZdGCSTv0IDtFfW4Ajzc\ncOcQvzfV6GXs7m/O79yiR7wFqW+RfLTuxe0RcJyaZ9nYCPP0iRhcnt684//Svdo8qQRROA98dUlz\nvT39cUMUoVqmYVp6wW5a6iDiRE8krGeVJ+tMU4G0XdqRjsuh3OQhMqLfAS9mv8qEa+ljJLJovTFI\n7akhVHkArTHr6f7C6V/hVJe+JQKwR7qAwnx6ukAfHUw2JVhgzb/8QFMMy811xeZYxwVSoMplMWjT\nAx0HepZOF/QdfhhI/rA6n8RedYzpKaO4jGIgQPy2W3097IvmKf3xHjp3HoJ9lVMnk+bHZHfbA/Lk\n74MuPtx5S6m3BzC9JNlSNP4ilWiR44FYrhDQH3Dm/wf4aAuMr2axMannsKRoBcaI3qdeQbJYqtoT\nygiNlcwqVKsVnL3de6tpMKcMjCBJVUJgZ8MhuP0NcMMVOZRQ3UnXRB2OgAUU3u6JOgVHHJYqSaqd\nFwcT8dUvrYnRThmYzkf+FRkTobw6uwnPg2tdUK3qnXlR3ZkXoeArd0twQV0BCKpsLXQ2+qz2YQxz\nGv9xoTVDRyXvVanqKU47n+QfTxvOPK6Rfn81c01ICnFUDVlsQboIU9q2bnHfxY8IGG+cZjAWdGRv\ngB8FCF4vsLFapVSQlUtd6c+4OYJmG558OkTRC7yNiUvjV1AD4zdiLUmua3LxB7zRsS2A+0NgSGaz\nvIvbaYY56A28EmPHyn5lI/pE1DM0T5vn6olSZV0FRLA7qAKUaaejcJv3zhs1v/Aqvf8cEA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m3RPvAMovAhKCNx8SK/fwu95IaKue0Lcsxfdu7MqEh06FLHy9x8EAbq1h+t+tehmO72myIaKofrb\n8RbMM9yZ0wdI6lD1WDZ0J9TdvXFnIcNJX5n8xterV9Xru76jB1ik1I6vtaylkF6Vr80kTb8ggEK6\nDn4EWZYNzHdV6nPF2950OCt4AWxQ82gWt0iuvyHgNhVqsF4yHrNOH0TbnnMROBilB59yM6KNB5rR\ngwpkA3tNXHpIlUOzv/2mAttHdPn483T3L1fndybYlo5bEsPHCn+3trNTlsTLwC6fUhw4VO+Fg1/S\nRMRiz/T5dN+q81VhAiDxX+XMJ4HRdj7BRO4rYvGByBJedlHoXDybLR/G5EFC9cnPTZdl0yJ8QiGe\nflkOC6jV2z/ztbs8SEFiSGLkI/mMkvejtso0tL16CfV0+soC9azVIgJFcrzoO6FSSz4Q0kZA8Q0w\nfZ8cp92RSAX7ZEds9SSMMVPNmon4Xu4qq5uNhjD0W9ifJIktAPmm5gxbiM9eRfvhz4B7iszYEA3S\nB5n5S9rAc0skWNh6LYGNmrUtaiYLHgoOwZ3ARok6GauMFJphGGa0XEhKWC8480jS+QydP5N05+0D\nFNoEl7r0G3uEJRyfOM9kwLHtwRWN7b52RslTU7v5uJEl8JONu/QVedHG64QjYxSXns9EMIQaUZAI\nYSZQbxDl0cW4g8dF0roI0pmobCDxhMLfu2k9EKbQ25IQ2P7ByDXg/bUIev7vb0iS7pt9jTAcZqVS\n5Kk0B1i2Ox9iA+mWM9YQ1W1ApDbwyjAQKJGCTTuG5R9/UbWjgkjUgPe2fl+eTvB08ZD1B8ShDbVs\ndbi1Jfotmbb9cvNgzBKqGi4KcwZNI7/iffPZwWeTzSa+vUoiyQN6MUBEjp2Slc+IM1+pO2nGNuVP\np8SHjOI5kVE02bMk9HEUF2LgOzllEhbgnVFh8evJMFrVTl1kDUhwTe/4ikzctzUhFCZvOwQFDcMj\n7qe6IHYvoJHNhW1u9kbhqDypd1D0FbRiMYw/mlQ5s7AsDh80BA22oWmJu5vmYKyjH9mfjK+a+diJ\nSRq0X752NPZPXko9D2PKav8MgBE3KYutRbhdI3gZGl5cFWLnW7MBw2TA2X/nqK7PLjCrykN4P2cl\nQ7jNjKGKXvPJcxDBp+A6JlPi8iRZD9jzSz4rtPFONCvB97oxPhygvAxpPvNNlHbOkGJ46jiMXdyD\nEl9ryfBCHpldIDO+XOSW6zAiBOe6hQmNIlL1aL7KJ+8Ozqg0ySK6gAdbdfrHL15f8fmzTVYXasyP\nMxEvRhx5GXGCmLsaIXwvP73x6ePLQx/zc02s4ffD8DxMEwrbLcWsaEnEjRKAIi/316xokanYunSt\nBHvxcI+kYSQOVIrAI2oOiP7t0gij3yIAu36uqZHH6YuSeKyaEieOhFBOdgiEAUdPh/geC2q/8Lut\nHxQqTof3zZf3RWGwAqPF/VKQegcrnQhEMHFozeCXfCL/i8Pj5DIwe7SYWJLL/e8B/Q+/g1W3Jggd\nL92SeDvMBSZiT5WO6+4p3ihSbR7ztRXgDKm+8iDXOwfugLKDcGYSw0P+/PTwDt0iXY+5CKNNhcw/\nk3GjcS5llOdiw3e4WExSfDbNlm70wxJqT1Ami6Owjzg6Q7BI1qb2egE9YXRoK3f3onziugtv8JLW\nClFZD+U2gTx6snhDat9OpDA1BwUQfOp4QBeRXau5OzOARQoR6Ef2k2jIAXWU9JgZIZAGk2TAeb//\nu5gOI8zd8fATXvpwyuB0x2lscMZRYVUybC9+HG15PEgGGU62ezOqv74pTbZtMunGOjVjb6xYlosy\nrcDmO/YPfIbNB8Am5aPuOxgwjXBEzXgH6Kah/AZ+A2iMjddY9xkM8aByI4wxyrYICmiW46epiiTp\nfC/dDylo5KZXJ459IkayQRipkx64NL3veQkVK6n1uu/N4UxXprgnrAb9bxqSKZJJOgXfpdSpW3bd\ngOxnioG+O37jMbjXM1bLnmUZa37os8s0esCEoBINokrjZAm0KtWLeJj4qYy5BXdwPhWFAAPFA6vA\n7QPCTFhy4cFqIjzC0qK9bcxOuerXK2SzmSxzSmze39OSSBadBydDwj8awUybRb7JUP9WreoaO+f1\nUa+QCi1sKLzl9b6bNDAufYgWwDcN9R7rDM60VxFOlfxYhG0OYolT+kvfSlDIVvpowFXXx+KMwJs3\n3tBK5FOIq6bOqQnSL323nJQOqNcBH05G557R/JbqM4UGPWuEBaqKn9jy34H76M/7QYhwXcotmBsK\naZy37XsCLX0DJ/F/THgmJn+2Z0e2UJYdkT93Ep85lH5Q/opcuPvxqj5YS98gCMtzEmg3XPV1jSWQ\nq3D3AHmljPVSEqiAu9XWltkf+dDXLeP+2f96vfOvpu5FaHZSrIqChWRZ1QRCS51BsdlFQyEW3ZO0\nbmaQaj7TgnfQaX39knPFsN+pDkQfYJkHkUqP4v1Q/hAC8e+pwoL9lep7CeJSp6Q0/YgqvXHfFQO7\n/2AnLo6604ArDyFkSe1WC4D2UAyAsek+udbXcxS+kD5iyCA8dWTUbvjTEdartlblmSUGITVGhtWA\nLZnCvygseMdvZjC0n+fkNhKJKiIWw3/pDHr6D8Jn5zRzLmbLS2GuMfoxfrH17TnLbakN+meJM91j\ndRo2Z/51GHZOQ+HRjE2ZohLqy7ALoOR+3fh0fgaej+6I59bC4WRU6h15R99s7Fl9Kvz9u3dJ6RI+\nsCOzSPE3KWt/MymLOj0dCInlhsz9HCiy9mt6gFWJjhRjgzYm7bADSiC5GoU6RYWUyQaOT0r8GdQe\n4WrLrKIfojaJEwzX7OZHpOMVa/CKPtOl3pokmHYlbnNpZCTHsKMdyoBSZLCRPq6Iyy3lNNIPnZqi\n+HiridZuZguwZQ3ccWfzrJBmrYb1n3p40eiaYi8TLA/rXCbkFTaxuzLY9gtTstwPENPpZ+yt7RSg\nAYjHZHwmXGL2f4iUgu+nFEGYyab5ZGWjkU2pSS5lboNnEnEnzRPClcfH4HvSwpPERbZ+lJD3JbDr\njBj/nEk9wyZx0LS9aZsSqBJ9kFSRT0QRPQ4Rh6vsUH2h7BueAeLQKLLLcrwwrvsKKsUfdCXb5Frg\nVCDc1RISBF7x0ZbTuz/DMGiTeOYzTdzD50nX4fC1dElfMSiAqpx8F6Bvm5f5n3pY1tk12C4zUh1A\nVHS5lTaCfzMKVoKzOmeQx3lJUmtro9e60bDC9TkfFX2kM9Ia4ec9n2KdGTNn5FYh+IyXtXhoY5SU\nM9RmcCl3qakwGwWsmYqw32sXUQHO6poD0C8PPXyIaNgqNiVsEcPcYC0m5RgddVAOSoxc1Gy5+DeH\npCl4/O3pFv9qS8NE+rSu0htw4NyMlo39v3pfjsotJIYInBL69HViGM/d4Ly1y0aT/U1AELcBWN8B\nO2dOUBs/2lzmHJaP1C8JbnoH8ilFUocAH76VWT3KzxDy5L8ZqBC7PNhGOM9qTBJY5POLweVtASf6\nfOm3Q8J4X7VfXvjO+irzeb4jUxt7ZwXnk9Zs61q5/r0tDPhGWfGbAv3vg4ufrBge1g0n7LuG0dX7\n5GkJktyzbf2rNJlC2hlwA0F/yxTXdomOhdfOUlbqGlHoOLgABIP1ylusjyMZXLSeWrsBE1FwUwIe\nvazSzva+VTKXywM9maSxDEVMdj7EFGm2ddkG4JL6YAUCMX1aNxdkv9ydDn5HExMZtTzpvVSgQOZ9\nuKhh3hMUAjt3QErPEl8vNvs/+aIqMZuBL3I/HfswNSKo2nNABUQaxyjEfjx6DyVU0EhC6J9RX/h2\nyCbMzj6yFYRmkuSfycN9MMld1E9kZW+sZ8JJShvbOZVcEu//6bPkO4jEUJmQsQaV6X6+hHyV1jZ0\nJMzhc1EKHkDEIgU6ZCG81X+q6chGp4P/ETWS2M168huje7teQlSyyUGdivcI+3ZRXarL4Pl6K4PS\nEXYtwJcbcnal+u+62pjcRebzYS0JzxGAvQsOOg8s+Frn8lL8MLBrjojgGy9QHOrEyZyU9xT372jv\nYmpT69gMlqWR9dtYzjRGC+EuHzghtdldZvCmOb/zzebZMILXEybKz3hKq+tJ6DAoUZdoYclNPHpN\n9Bbo2AkcZQaKc9yqMjoFrUTqVlil/Lm474ty4NeiumDDK4a8m7kmgfn6pVRlH0PQx4Wj4oBbBhqy\nM0hsfF097GeakXGvdJn9FOo1hM+b+jnchxWMdfowKcZPiV5Mi4k/m6i/RdaWZa5iDaSnYtMhIDPz\nWr0Fn94UKVth4qlZ0usI4cpNZVahkN5B5CkWB5TIse4j5qkJrf1f3LC9ZS1Ehj8odgkzjeOfNURo\nSnpWNi5GB0ju05eNR2mBLoTHUg7UDHRo0NMXiAIzZr4RQcPNqjvzuLoRZTSc52I1G+eFBrmMUBm4\nbkzQ/XJu6si5mXPNNYGswLbRlfMmUWXKXHycoAx7F5ig8A1k4uLyBm9wpZRR2464TkIR8PVN9ZOc\nlw5Gi/30PGLWsXtRELG4By5PxR/s249SaLH5tfbRyYUPmpBhZygLx7JWf8ak+qcG0in4mKjZB06B\nRvtWNaltdQ3U4Rf26nCLoArJSkKeaOG72NhjFhQcH/sqWIW0wc92sndel9NBZ73dWDLBihh77YWX\nE7Yjfb1l9u1Obhjrts6bSGtR7pPpitvWT7sDAfJc9QSqz+AEERCLQD2IxORrN8JhJqBqFdGwjkYf\njai1KWaSRrMYE6mvCleF+g1vaQ47enkfgXBzWnzJHPX08qD+AAdymH4Ip+n58QFjkBDyxMweMRXg\n18XjLIGlAlqcBcWDPZlPJhXxRlK2NKaB11HmUp2oWgJuNKXw8yJJ66182N+fys+Pv4gtU2bDbBkn\nA6/ntnonTmg8kgLe9qXIPYpt4r+LisCZPn4XWuxk10QaCIqhCHgs3sprSNKMOUkJLJi1OojEqtiX\nd1N1AR6H72TWTwe/pgr0/O/YwYG9f44LLjdl40oW0EviIVjC87b/cPKfTO1K3YBe3ZfURBiHaaz+\n62xGocL8DXsBIF7048tIInzHFBVgCfPakf2AykT82kq9VQdPolPZRwIs9jAm0crwm+FIohKM/UZB\nJl3EdmjBJbske8KSNLD4fMaV0VdbWMK2JfbRWnqhBczVvO/PrvpCTtV7qyoEgOp0lN5isjGJK9ba\nTkbrAX0E2v4ud/77jYn94i8/4vyT/OFNS65B0zTu7+afWgGSmlInMCkzCtVSXzm249z0EhL2Kh9i\nd2R1Cx8vSMcizme7xJootFLs8mPBIiSXmxyF+FIG22JxFDxOrORaibXNwd7FRow7ajNwx+DjLpt3\nmvOY9maduY3BLQtH5QNXZPeK1WcPJ0E6h3sQzxbK75L7W/oEltstmqkRsUarQDRmOJEJMQ0ikcFX\nwEx331+f2ON2wTZrjpyYV4yHDCjRFdOvQLQa/qk0vugSiOy8pxwVmAI99gSjdMGbs8eA74p0M/jM\ncFrGoNxtnkg+9QrQ5wS4FhUALdsi+WUq7ZAz9vP5EBJJJVW/RvlvEoNcbOwP8DLVb1qRk8K85VMd\n8j1Smgvb/zWRQqWxzTu5tfISVxLt+3Pype4Xn9MEyHrolSko5JN+dGYUAgT3iWwIHmja3P9tYlTV\nJBjhGxhwuiQWlbMFi5sg4ebujnUmfV8VDcXviQGcWcqGvWY6MyTNAL0VnyCqXU4QwyDaOHYFdafg\nJX6eSVi+ygE2oX8z9f2zdHB1sdSiF8/xlyuCw76CU6ujkX4WGRt7tn6BUMLgFSVwiw8J41BFU0rH\nhU1FRZfvN+EkOVYSN/zo6kQCSzMZvlVb+NbmscqUXV17IU0vuxbNlfvYyoPjPT7Z+bCVnMiVvEKt\nw7Lt81Uy++SoC7boQq7UA5bhK2eHANx0EMHPcn2JXEjaV2fG2L1++tGWhDMnBPy30aki9FUFlfmC\nh43BKrvK2k7u6NKcYmhX5uJmTGxzXewo2wkE8eq0LBC2tLJGYNbQ3bAwme6hK5YNSu68OaWALhlv\n61ayufjbDugWJUrrRjzsd3lCOq6kB3yEcqfxcVYsMigmK/1Rmr3vFyP7UJ+OJPiioDcj5t4QujXc\nSsOhUPG4iS6Bn2+cAsdT84IbDpgQRg/grLlv20YGJYwOY5ACcuHWx1FlYIYNcrZyxnAm2b9Af3Rv\nSL8j3h8FVsV8GQoTiBjBB2mniRy8BAjnxIHFynYRl4DNT5S8KdQ6cDRejpOehm9ZYu9JtjUgoI5O\nSZoeYv/1PF2rJJ6IBmr/UEv2+W9vopnD10EabWJayJqiFbV3iA3Y+4nVWctZ8p3nmrOXCfgYsXRA\n7yAq/IvNHTf3O3zCK4Axtr7Fq57utlu8viGi3El/uglGClQ7YWhsCTSolfw2uVeg31WdUDwmaK9b\nZZlPSvSvU5lRUxMRgTvk9VxaZpgNBHGS4FDhkdgVhx1f2wU1qBj9Wzif4uAqwU7gfKzQBawzxIVt\nghlhcKrq4SonsWv90f1jfuKau2Ey3q9oJlCV0sN3QtgeaRfFxVZkXZSiaOYesApg0JX1h4ettWAi\nN99nMygZkgds3xlKMcoO50tNAv6ti5PXaMn473ImFZSJ+tkezKYBJ61OqIOmzl9RNnHu3JHsAJ1v\n/gohqlco4E/wmhpiATcRvZzCVxIEdVaBGLKxuT82+ZPA3H0tttvriiT6qm8yTp8Uyfm40zc418A7\n4eS306QiArUhYRlW0dauDdsWK5GEP5T9Td09pNp/CPUT7S4hfIJLgnj6NOzp6j998mLA3cE8TlNn\n15ZN3q4U8J+GdmMTumzlDPJxvrM0a+sKPBUxOQv636ivicW7UHwRbgk9AotgLbFiMd33R1kbEFRB\nP+9EzItgbKW1DvMnWlef1tn3I8+rrNVN8C6PwESsxfwuBAdSOBpseGR/9z1E9t8FIePs1XUseCSp\nU0+f6b7KJIPAIlPWQEHv+0NMO75fesi/Ubw9VR9gpaCuW9nJQAnBwFvAlRhsNi2GrQmVRxiaasU0\ny8LPEbewp5Ij8XudWj6bFqL6jcdHabZFcR4BG/ipN7qXc8ZFG/a+wRp3B0gAcsZjVcEhVMkZQr9d\nuSvuFmSTjZCuuvLG5hE9rMKgD3H+Zk0qSLwR7J9/pI4ACvlOkLRE54VE2t/1oV6WCVTRzNcuXsqF\nqwkQH+oKXPdAfNS0PK0ZCNDhlsTrWsGT5NtmYIVE4waCKkORgFKsXv60WV+4pM9tXrmBZhmY0csV\nVOXpXj9HDPG4OjyiMIn7G2VQG72P/CAZmgggOWtICsHsy9AqTVOVFHSzEkceRM9IAAblQdDyprQl\nqk0YaT3l2ZtG/JYfqQ1/L546QMAMDL1BGj8NkjZERm2ylk4+ppEUQokdlryBbG1onRzAN1TAO1yp\nkXPY42rvfWg0GkON+15CNMqCgn07Vd7PbJP7hptKp+AVum+RB39144+j5nEOxwCSPizhw/vEbx/8\nuAxkWvj9aFFJdnaw6CNid6Ju2EXGY9FuzwoaHLixIGEQig7fHUZqGohxJ348i2JAQkqtNHGuPBvX\nfyBjBfFJSRCIGJdf1mIcZP48O5yTxbea0EB6Jsrq7s6AyvrPtZcvmYG3uor0WcI3TB9+W8ntbkm+\nleg3Z3xEBcztf4pizgGqdh29cwppwy6JMrY/Fo/+yJqzEY1xXcoF45+/g2uAkIwWZVuxYvqZNE7P\nFWiGDyfpUsGz7Tv4dyq1zPxXNUfjkreEtfeUwIgmNd0QU6kHd+kvxlkV5EaZzbV9dzqQLNhNf+ii\nnNRhFpKEkWONa0edhHpuYmC8R84MritfIJcn9e13VWuZ6pw4x2sKJPW/eLrvX2k7bN3UQ1Rxc1Jx\necgcKyacWmkmGAry+06rSsqX5wwfFORysPF7gbON+h4hTQPkWZkjN+yWQ3khrsBN9eeOy4+L5U86\ng0aIeoQj+e044t8AiUhe+l3sY6KaugErQHyaqBYhBYIu7ciLjc2g/tfyJgc+vC87lEH7LBjRY9E8\ncf9hDrjUc7AcCZ8EIK2JP3yfhuycAR6K18NB+kG2hn3sRJcgsd6NIfbctwdplppHA0MmFKkMh9Mc\n9PC7OLMRMByGKOMA+MM8l9TnX7chVcWqeKZEjx1NRWkWH0EL0FZO0LC6ou2sFGbprmvNcK+n4/4K\nWfcEwrURNfnb6shZkrzb5le7yRDLIL57daPMegszLCneyRVvXtg161tuyuM2jL5+tAe85IxRKzzN\npvtauFaC4L6dk4lUpi8ZfkCAC1xx39m8uozT3KgqCTRupdmzzf/9SanB6i6RFYzRxT3EFZMCD0VP\nwl3NGUW11guLyq9gzrRme8hZ0uOQt0iVNARP6AL7+SGR20MY28jJ1SpLLYzKsr6wquKmsBQhAbJN\nJXtfYCan9n9s8G7hNLjaLlUGF9NzGSX6lbfRlOfvisFPSRR/vT48Rr8fR9QThcdYHROxNtE/KV2Q\nJ5ukcAOvOUk6CAdNSc32LYWIJVK99uufiOoUJPUePc9pz8Rj3LMPPnnmF4Hdd7mFaT0NHPFd/QB/\neCUriqokSVC6NDgiD+cxbIJzQ+6O7pRLdlSWn/VZcIiIsU3OV3o8wKqqzbcartWzfeekz1o8vfOB\nkGD0XlUQpQ0goZ3HQ1QnxpZrch09CFJOVxV6+sVn2pV9y8KykTqQz4jGlx5GsAz7fWyFMF3/+8WT\nDa2qkZGQsZOldQp89vBR3KXAf+blntGDe4czK0gxDSSwIYpVqwOp3LY4weFLGKa+gN8co+jDvkwK\nW14P46abOA8YmkgWb+OnQMFkH+N117Shsh+L4008ajheyy7uRVWTKWHBiZvGetMCmwlkB5UHXak5\nHeSnwWp5Le70zXbgn4IAUMYQYsjTbV+mGHoN0+1jARHdHoiL15Wf6swphtZdtZIhshJiBRrJEsoA\ndUCy5K04gShqwYB5ofbdV6SL4PG/DCp/8BHKNurJf6sBkyfhD++bV9UN4EHK7fXfPeztlJRF0uF0\n4952P4/4onxSmjoyKbUh5ddqGlaWizYlsUT+GF31k2mHCtPGL1NuH0gbarRIwSxerxtvhtamumEq\nQnTYgdlp5tGDMSMIKMK/9KRHp8MLpcEzRmd34qLBe/ALKbSghWZ0qR2GAYTKer36xPvhzjOGsQ1k\nB3BQaiQ5RpWowM8JEgqmA6j2YbK59jJximE8vwljiwGrnC22AnVwKPUKKyA+KYbuduZilliyy1+5\n3ms+xE1E9QO6J3cvAy+mvZZN/YuYtEmP1xTeU4Foqf7JUl8MGiMoPJbc4ZNgGqkTo5ZAy/+GZ5u7\nJMsKIZG4R1atz8A55EYDCoO14sJiAxHbJK6+yeqsBwhb0Q+7K2Cc60fIn8e6FTvpL321dzYKWbqL\nCnDqML1o2gdQrIMsQ/qDffX/Ko0Vvr2ethKaWvAuXkCEH73jt/rEkLHEV6uF0QjDkTy5GBctu455\nqGK7yzBuGe5A7WiAjfZLT4FzdvicOCB7aOPc5311HRpGnTp6Kr5DcA9RKrHRMhbnjYpLQYMv49SZ\nwbQkg8z9qTm44wtQ49tNyNa4hTs3dVdKXs77rMRZWD/2QxVFTHB42Tz2L7BMcGLAxbl/svwyB6G1\n0UtPOvExycYPbjRrinpy8GK7Ws70+8RpQZe+mF1iSjTWYZD+CLGN7xI5dSZtMhJwnJqH7jDg/p5C\n6tmLXESAUGYwjz3ZLV8A45DNSpf4dnXagsPv+ZZAbpkyU+xaTDelUpOe8PkLU0mLPq29e8kBxaVQ\n324vunrLc6dTlptNXYKrfeCCynBu+SUmLRvBFeckNptmd9YgjvODYjnwG1HgX3wZd/hv3+wtRlc5\n01PVRKl5uX0oaATdU9AvTdoBTxOUnltjiTLKa8OGFW0LgHZ6zgZdZeQqgH+NWaZw8NhoEdPCa4qt\nariMf9djLcbDbfb4Pe5/kUIuDnZQ8L5f0vbugJ5Jx83lzP/+TntwCnZh/KRNZWl8fNVjysJd+Aii\nLBC8Dwu3xcMhv6CyD03RrjA/BOV4hHARCmpfACe7cCYood8KnkPqy9hN91NR8vmJHFu9lnPuZbbh\nNY4CP9YJcO/QWLA43dNnQk2oOWMDIERoDjgmoMJ9ZTj2SFFAPMSxDy4i2VHr0zRq2R6GT7uETJni\n5wlDfv6rb+ax/JATc6dq7XLdz0fEb3cv4FlI/042ACY7N32KU8Gu84s1nDzSb6mI8b2xer4JtG67\nYpzbhRXiy3IA9dViYloFMZEAdUTOgD40Ic/GJZmH196U6lIzS4ANKTqu/4CPkzIMlz2yAH4HuLUc\nyQobG4Y6lIDLo/k9yEZLLdyzdXPhMeqI5zGX9w78POIW8nxpMTSIw4ucVpMTqTlvg+kkONCHBDAM\n7JpQwq9I5fEDCcBIHacE/vO6wnTboIBAePOfPJefeyKm/sFBmxpQrrzmzzXX2UyNLCLse0pPV/25\n9yRNwX356hOhDUvmcFqLS3jRhBzc+KGOiWxN8wF0gZCmfAdoiY8l7VuVCT+emfsosb1tRPE0xk9S\nzzseJRBkXYh1UPuONcJlapUuCAqih+ZOjIu6zlauysxFXkSKff9t7uBMzyl89BX77NvGrCY0Ks9y\nY8aGS5sCp3rPAFjpCx83/mZfwly7XNx2ba5oWenOeKZK1vOKhL5M19gNx6CIT102N0jWHynznyNE\n4rJwJ5WNG9TORIWcj3p93EAbT/xWaip5dswaOBeistRlNHnqe3TykxHElbaIu/XR7FRlzBypClIn\njTNCAWeHYl7iy72926piD4FrMyJqJ3hpk71hE8wNRo72Zi1zGwlqqN1j5iSUe47vLrD1jZXWSu60\nIfJdROMe+scaUsQyCl9dvliRCbJ96D2Lw2IdIiLoBFzoTfswMOFq9+zWuMUZVD1iIT3PNZYDXOS3\nME3va2A49Z10JPqJt7ww9ri6Zj0AcDzbNUHXJ2ZhB+CKhR6SyS8hS99hc1Ldr0iCIHF3FxqngZAP\nkggVEoBfEko6h9fV0LAZao+qUuPq73WLP3stUQyVgrCvD3IV4Tpcbt9rS5L1oclizGmNWx4dJDu5\nCGy9wjLk/1RXMIUI4PM79IobuFBIkVNrdNvgSvREcTDI2sA5rm1m0t3XPkJ5coDeTao+5AzHZcB+\nSedsUa7+xVtHxOvlu3XfAyglFRQmEBvjn8TSviDpSWKfXVf7HeTrlNbmx08YIOdjwdezjXxdJEyJ\nsBwTtJ0ynE+OIqAoEE2VKnSSl1+hlGlKosVv+1HX3ShOJdS7hosu2rwUAUOfXSgegPit4BC152GP\nyposbJoNDKuKyGj1qJMInW1S8tYWgyPr+PUbjRASHVTpKGIWKQk3SEC4feWhLr4L5CuVXjVlYeLr\nsw9mxFDEm0nkaYLytgdPCpXfOcS3Dgil4p+QSMXVMAO49Ay+oyar8/PoESioHvpt/rZPtyqM8MuJ\nhEtJeRm+rc4rFHu9fJLAoQ8ahLjhWbdfM/DQoamvQ5KfCnLN/W5svWJuhs2TW8thrKd1uIhy8lB4\nOVNVlair7v9p3oQEk6HOuVxzDTkFtvx2sMyICxwhSLOEZ9dnstPvoJT2TtUaanH1jGeF3mNQ/9GW\nBAj+LoHtm+8nF0mUuVZ4g3ydPkdxAbmx9S3amGAUh1wqZpRO45Ctz8emg2zO+EuVDCqA6KaxOx3+\n0VjE4SXjEHXZWdqsXzWrh9EyNQmAJL6FI+5Ls+tI52q+Xl6U5pd94+nkihh8Kp6dihA8I3y4ebBT\nGOUGaexFjKGTUFoyiuEbGEJwBQR+a1veNwOqhwLBCJC5kHwlxTmVZ11ci4aLZHeymOrD9zoh30Sz\n8xPc/ajRA+hSQFV4D9hdeOqeSrnS2l2/Rn0D8ENAFSsmyis1EDJdgeCHb+PloMzGvYYj+PpV2I5O\nXSQR89bUlXK5dO6F/35bKcBEeP8J35KxOJBtoKPx9WyrdV/CIxtK5w5EjZ8TriaTJGm7IpqvwqC7\nNPz2rL9tfZXT5r9xK5uUMgoIXk2xY9QMcBv/bkmPXq7q0vjUE2BmwAzn/rXMthnxDs4H1poeYt4v\nB3nNkNVf/3Q5kGVo/bRGrnfmKFvnJPEUxPAUtUBzkm2IYqlCS/YfHP2sTdeS7ID3oNDIA5LpaBTp\ndRBiekwpOMW/o+w9trM4nXC+X1ytJRVQ+ctR1HDFv9JuW/O0GxHvmFO2t8GwoFSrTbM4UXsO9hRH\n3wbfQiLKTHXd53wvubhhnQyPc0zErcPPBSu+1gsZJQRrkX/6vy1zBd9HwlN0FWm8UUvbaB37RbfI\nrOTcM0cr9vb1kJxjoIANnBSc9gRPUFy/xCsiBri9S+ALoP0cNc1DKp+mmu2CCyM9yjfLqffpHzfD\n1bXTT9BKV/qBk3CSJY21t/loUK++pgoXQaGc/Hlsqd39QZGbGUl+DStKoVxkGpd6FwpD4IY30GZk\nCl4NhWvBLFIb+0GD7JIeOeZzA9NlpmRojbpNrMeTa7UdgFNjtRVaT/fqlLv5QekRWYPMSbcQw+tP\nXdenoGXHIT1GnU1O4ABxEjvak85Ym2WW1+nYF9jHHm3Q/yEEei22OB3K3aoo2gs7+wGuIxQU7ArI\nc0oXV1q4ZnpmXAIUS7th5FLG3TdFV6eQAaqxpwQWsy2pkkKiwBZZ/D71ffcfMT8QYTyd40w1l7TP\nceK8wAfTWIOYhzSBDsWeXUWAbAxwqnRmJSY/Ky1MAmlbdzajQ71BezaALB9wa7mU9Ljbgs3q/a1Y\nUDo9lI9AhrF6DuixtBvNbif0ajsAD6tRY5H16kAZQcW18xibO8/YVZ3smp3pJoe60IkTe47F+Nol\nJ+o02pvCoIliZXF8/Z41GWhg2ARrDs6d9R+7XgS19GY8BW+JrXpclIXU4rM0UzEqVi2azo+RLKlx\n8c78qHqXNKmAjpezwg/uqzLkhEgld7Rsla70POegkFGAhJvyLmo4L9EI1JJpsSIk8x7XI1MvXOYE\nHuFzq/cfuP2QjhT9bGU6otnCQLhLEAi87YW017ANALhEBfxlaQmjetfl7n2LqJJzLoYKd/SMs37q\ngun+OsXdr2D3RRVFo89c2rr6b5keBuovV5WXYwa3KEVjiCr1CNBCQymZSs2Toz1WoN+nDB1VB2R9\nMEAniTgZRNWrWxJP+KU9mnxFlgdDI7eG7sqFswDE84UZwmI8qIZY5oU0RihPjILStngvaFFYfmW8\nkdvI1rKYceTfan5aCPO5BuRRUprDmbBZ2qodkwsvaF1c+MozPuTvOFTZLmkDxPWQVaIciUM3rCEQ\nz6Tti305QaiVzmoY587WFKz1W+4x3unsBoHV5P/RXp3mWBrNw7wZfRc5urW+gccMV7UfXQerRj1i\nPxTtSaAvOF1NFVAcblw3A/qBdR2y7oDF+hXsKP7SuvTMRlvDccoYuXlSRpTBOH04NT1ez3P3KBAx\nWA61abpOAqp9PaWktJ0hG+QGUwfCNSlCSlmR5UgbncIrqP1T//1Rm9nryWmvvgbZfDXWBpEaRnLj\nxFjIeMl5bV/y9rhvjf8hyAQuKXyvLxM19+ZhOxGx83VXnEczCMhWT9UsySZbUqbtiZDdUgXXq4Vv\n1Q9GY2ns1Bycz9K/pcGfaJbkakP7mDWKyx7UcTx1iIBpvyCqXJiKZWr71VwVUgSaAX0f6EZgMtTJ\nhp3EMEkysVaYCGwxYWj21OcrNMj6Rh9c5Qu39ESQX+DLI+ZVPPFIZrNT/MUB3IPDTtcH6t0CYqOm\nFcgG8hBmhtr3/t4lkjg7G4nywNseiDjbBXNCohWrbozvPmodu9VIooeLHfFVA6hfmMPxiAI6BpHn\nqxxp84f9h0E4MN6uqe6UPscO2mGFjJ1LpExJmBoKHRYK70XqyIs171BZ2QTWSSS04lCaaFyApMcn\nXOiaE5U7IXnYWwxzZcTPyScxX3g2m07bqasXOII+exUO1yIjfhr94ZtPw4f8FfPRUtvQE/4L0eFy\n7jQds6+enIsiXFLxUHzSL/N3JOpEoTX8a1KkNnRrEG5D+IF0TkhqE7Lw9rZDWKxv14vOarGdMW9b\njnwfyglLdOGlv421UZE6tEMom1gremaJv6m8C/m0JarvLKFETW9oMeKca/fS9C1G/b1JP7MSuCem\ne6Gc8cn0DeMpD//XyS8WBGwGeVcnRWc97Kipu1WurPMUjc2sVu1/yDIpVmBMgUL8MoZcFJAX+VnB\nf59pZPsikbcpADqge7GOephs3WjHClsaX4T9lN5G1TRfljjr1YsQyf4oDcS9wYtV6arHfyOm/VA1\nqVWXeP8CX+dI0SQLQGaQI2sQcE7QIRpayZW5cJCUNPkybf48GdA2XzrbITlDm9/9eNbGuiTH+tjL\nXallspBIFBt3cxdbsdk+9iFrxdGT6XG/bShIBNwiASHKGzAbd0MCxhybmqmYgKCIo06yLOVpQLAc\nzOGKz9S84Gq0TKKO8I4/zmLKvemL7syLuP76Oqd+odHayJ0aXh49sUr0hceBA4mY/PvZnhXFY5dk\nsIzCdAWiK5Vv6Kgum7zcUXVXdA8wQ9+Q7PibprallY5U7K3S5fXJn+Km+giq2TCdQBH8ccUzlNId\nyk8zadiHPedSrolCv9XuBGN0Ok87V6e7TbmTn8LGuX46cmOz8pYo9Hbe4QzQzc6hBw7g4LJdGXUb\nKvM3NJz9BJK87IJFujZEIu9bcV+eQ0nSu52LySUMxdq8+uZ5H6OR+wtwj6mBDuDUJND/MlaEMlr3\nkIRgXld8tzSqz1nLyZPULEY+3O/fZ2VDu8T5XI4sjwk2lTH+4X/lCgCl9J1bNWXIZrPLHhMiExY5\nlqomf0TXYrSHg/2qgy3lpjgEzC42MPMnSAha/M+dAu8kkT+kcQ+qKJh8S0wmgfTIJquGJJvTw7Oz\nM7ohZ5QqKovu39O50YXWfbzkTJBqjBPiVBbLKFwOAG7T0M8mnOlDG6ZrIyiFsobngc6dxdI9S1Rk\nMysaJ7JMsok4+LAyzmhF2wGcGVbk/e4eIqTuNuWLM585G1K3VSjItusnuinpD2GVv4Jt3h0iDIfF\nlrigDXm3BKz19JKKzL7lWrIi+XXz7n6mMA8H2rOun7Ogbte88fKe5dbKGBa76f5hVip2vPEZc20B\nE3JVCUtAajtFQKhAyHRXX2vEy9JZAt79qlSDRleyglP/prBeRzhhPsjsqoPnOHXHsmxFNbZ/a3W2\nG85HGdqLdIZ8YauuprpLjt/fU4DlAiZcIim51A8lylLujJvcP7h7WNyFACFKHgwmdHkDSkyu5V0Q\ndwt/R/jwXSkAZBIp+wOGEjYwM2cWg0480CW1+owNSZ8rAoO6/HhxEBfwAw8TEqSspMoHW0Lxe3js\nXNwrr3TrB/gbthx/gG/YFfRHtKznC3KDBDy+V6+HAiRmOSVDW2mj7FpCQEJhqr7qtqwwL1uDCNA0\ns1SZJYdBkgzVopQgJBIrwUkt9MOdFhWd0UlMwEgjmtM8Nj32rqTPowAa3V6QQFfTZmlndoJDkUa4\nd0Vb0NRIxAh68OcyJGSs1YM7WH/o4/DaCKuqrDcC5xX3r+XLTtqhlhB5PPnGnaOJpZCaM0oryZuu\nk/9QyxuPgKkTLen/ejWW9wDc3zbBcXVRHYY4uc9GGCM/vpTZ1ZHypKhBb8Gg0+qsTQ5F8rs82Xea\nDPc+cJZ3S0UeX9tGQW+x0z583gK5Awepl44NfeOEukg+h89Xd1mcESx3MyzZNzZLe9W2h81jRhV+\nP8dWOm6IMmsDm9REL9lf1Ll2KYOS3Xio+ByjQpR1jDvwlUZPI6To3s12zAnuMDufFT0iy7qGb4Cn\n16bC5Tt7Hlxgm5BVJea1b4VjH4Xe7Ju1B4XrjhGexaDDX/j0p7sia2AtAwfVaumWZVo3pmmNMgs3\no4RdyRuJY/+6NFveGGHuN/LEpZ2ZvEN6lMmLIuL9GRTwFjrINtnZuR41YDjG4L7oPBI+j6nBAk/Y\nI9SGVWg38uXGBtWViBl0lZW3zC2rRVz8hUISIIXUB3xQOaUf3xP8/MhOZT9gF/HLObeHGr+oL6of\nOedeNk0O8z00mb9yFIB3DRFyhaudy4N5A83T8mW0ze4lNl61b7mBU2gplmDK8tnTpFKn88aEATYC\nKURQbXzHH8CrgzHwHJ9bpMAHQ7p1oi3YMRFPB/wwODl08yKHDLO8DpkZwNSVx4mHxSiCykP8QjdB\nDqVPRENXcnv3DjMHD1DPHBmzjxc54wPQqHdktYMBsdw/5Dnucuq29wjZPu2lX/SwUJllhCPqf4Km\nn3IX+MuapPWEYp6JdF9rL8ZvH97oh/G+0i0MKmvJ5mOXFiOM7JIznrwt2KDe/ibj46dm6UCrCoP7\nP2Gjkr5PPMdZHxBtSZ69NurCsiKzxiGotliDKQVRGWKE/VjC4d0c55GDU8O32/joKB6Wdruceokx\nQiosV+aoPcLVMRlOX3GnC02EBmlJwgM4SGZUq/C/HjEz1x2scTkWc1TyxL7tIkXJY3dyQX9MGGH6\nwacQH7o8NrT/QJZpGjO1ur3yL59jrP/aqd3KVsmxYDLP1dbjReWfvmzL0rotSrynKP9In06mtG/+\nUbgcQPhewmBs3auWXR3iTOHn7L2oz7BBA9ZlBsV0tvoZgWg8NwGcrzcAdrXREfAwiqNqCxajmh8u\nO6+dMHdMvPPfNBf+Ixs+0RNoY0xdRT+tlkXQwZ0zlhoU+aNMaRvRqEfdmkUpMShyX28QGXRuAsBt\nM06UAxD9KRcHlohhNM0zylYCpqTuFubQdCkEWy15Lc1PiNEY01ig2Bh/oa+XogOD9CAlpqC78KnF\nMGatLL+15qOR74Rq2pkK8y43DLD4cwP6srjAIKqQBOfnU2EyaPCAwoJgwWmusBD8GV+za0oB9Q0F\ncOpptOxrtL1boOvzbBMkzWbEFy1VvIkrmDne4yOX6v9o9x5Z37WT7ilYHkOD5NKfQ9AyOVs+/daZ\nY7W0PHXwMNX3BjWvWLLbqQ/6q9XXi1mN4U/OPa77Bnlz2Qb7ktXlZxMcdzx0h3ojy/D6bcAbLvAz\ngEvwYS96GuLj6Xe/C6T1YbfsqsusA+Tggq5OSraNCM8mVyUfjunlKo7EagYTb8GGo1HU5uTdY25Z\n4EjdU/Y6t4uSbI7GTRit8m0QhtbX7FHpeUtfYUkFLDxJuqgusLXJ0vAxOYsbduZRstOIPTUEQ0ag\n7r5sP/IIxnoJBO8bg+4/D2C5PEELTqzdWot62PINCzEwvEOlOy+hKbjJXua1gJDPG32HPLBUGrd9\nntSdAlQKt3mBILnewanqj3GSWLFDeblxJgpi8JtMiw0QcqvTN4oge2hyDey/wiYNvRtELRxb3MLI\n2gly3js275DeSwao2d+H2k/KZ9mD0iBxJAZiEtZYtJqMj92re3DDJDpr+PLGl5K9YpVAX63BhHZ3\nhS6sUG0XZTJ4FE8Z/EbDdcdjrUmd2erZdytvAAH8eurahP5xKWfgfrPIf9fV4AkGuOq9AnqjFo/O\nkmisEFQycqOJMN/0QnoKZCQUEn/bjqSsZQCo6tkax1V0SQDT4qcPQmnmUm/VGeRUF8LYKo3IQykC\nAgcCeXAA4cuGeOBr+hUsE2r0x4YxF+ZjW7fYGqG77srpbmD5l7eBEGkVGKDynDFg+52dv9rIuvXl\n4OygP2RauT2FhEmaxNJAOg6CgzNTbMKUl0qCcektZ6HW6KCpr2FN2vd0wrr/6OY351Q/2q99khiF\n9VKoxCriR65bEKausAE+iexeS3geSTMTp54P0Tv+akz1dCp5bgxJ9NfD2GkTbSY5PvasPwLjy8h4\nVxWmRhADAgPTmdrhvCw6y0CGoTeyRBfGt3em0WqOmu6OS9gljOtjexDAX3THs7MlB3SjM3pVcmP3\nFrGvzxPqc9emrryGuQrJ9oGzGsLHe0feRiQqc2F/0ECV1eNk8cKd6mUzerjrvADrGbCrpoGd206v\nKbCOW/j+43P3qpwL255l3jkYTuHKQlKuH/gstAY3BcOipooH/PEIyAGfgfuBfelIVTVed3V7olI2\nSEZRLrbEbIjBbLlOTQtZGTLApRVyw+8R8RDuMsXJrOdhoTNdF1DyBskfuqcMsHNGfn4rg/EkI9UH\nnagmAcKIXQvUL3l2KTYgUwim1gYn33tIu+JCtWDTK/1Vz1sRAIgP3k6kptuCmhRZdPbVywon+g6x\n7NzEv/qrTPJEbs5V14+HF+KTsLa5FO1cDu37AL+zTlflStz5XU0+9XCynEiyVEHmDI6v+WohXTlK\nkClA5HpeOi0npY7GBELocYpkYgWjGbS92nYb+dVA5ZfsozwHM2nuIJKUlW98RqhHZ/BBXag30xPC\nCakRcrnjrkRInqxjeIjnC7a6iS3bcpBI00HmLlMQCi7FneD9HFP9R6FHZhgwVNDUCSEcB2ep+Fkv\nP8Yeq3n6RRKv2CpeEQF5RLoKLrCkBnNTQFfYf7T2AHWaI7NN7L1JXJKT3vflHy1aQTrfgiMZy9zH\nIS9nHrWh1ZhvvjsrcBq0oJEAn5ab2gH2Bd659f0BqbLOAC/8L40aLCJ4CskwdS7VlvnimrRvKcms\ngPCK+IHgCbjZBvoxB38INczFT5JmdyMTL6W/IHpuetjkbaS5DAOwpjYFcLeyP9tX2Coly2je0PiB\nehdlLRPG62g0+rMSuV/47qPsCbUZYCviz42KbS0Rr9qSoIqJ6rncMlVnU6PuBF2NUv9GquANsXMY\nKpPJz0RwNZ6lE2sJOeZPnfA5FzKUiFeLdliz8mG2ACcmHc4+Shdc5W3m29P0Rap0cVHsjkncQYE4\nH5EYmJI1WQqgv+ALIFO47eWQcE3hg1M55dXkxWwWor6F7gU+PnG8PlzhRZCDb2UP/GG3/B5Xlnpp\no/hVxMiBlU7ccQWU13i7rIAnEF1T5gQUQp7uN/Wt1/KNI+fMtK633SGfGmJT5SnSpxiDvuf356s9\nHeKlknAwxfHoc+iOyKQfSVEwsRivsuxFHvFO/uUhQLdZtnpQ+WsUqhWDogySWCwDFC19JjqjGCoa\nK6nlCz2x3Q1izcaTpz7/woBI8h1j2Xdsyn0+XSL4opF4Bx7BdkVBOG1UByF+DbvAgZGRJpnKTg/V\n6BpUjQ6QJRAy7BrLKRerUUdzHyKLMpf4tQ8RGOEA9reAS3CUgN04j/gspi31rtU8Rgzhyp+vfzq3\nGsQbyFfSDwWLe/azTphg5uF/b2TIsgX2UcFmUos596z9WlND6VWcbjBtcdK7YlRiG4g1/4Fhqftb\nTGJoOEkjvETgdI6z9MXSug/2nTa1xK1Hm5ivc/HQ8ds2eSReytEf50t2TrAQB8xrRGGZskMYdLCw\ni7yhcxoumlqJYhl+k1iLoUNyJRzzFHNy9PXOBY/uMaxmdjvoPO87mMj6faB0qEJF+3tHaajCT4Yh\nGjOex/hWKWK4NXYPbhPUceJ7G5JKeSwTp3eEMVHGsOJIi6etw/uQ/lkgscczVDqfg6e92odgBN1i\nmxvqwQgpaxJgxLpvvO1esOa/kl2MeXaIxUBcSHF6XgaEXKWC3hv+h22DEpn+jFJUSYqHYPis9H/8\nM9a96VrObEU49isuYOh3jhAW3pOTSU/pOKCxCelPBaGO/p0veKpqhwYCaHdbDVw7+nhV/P1Rjbd0\nPZnmpUa0sdA/JiYd1EyK+heSnJaevOvwaYZnPxdJ4pGnrgbzbDe3+s6mhIl1iemvsvzfvSeJPvG9\ntF2BdFnyTAMwOlrjGep+ws+Nj0gAHcWcmBGt02daBg1jo1wVU4X3I2Qlfwpe1fhs14VyW8ympGBf\nsiGfebzdm0jx8bt6tEB7ZwAg6taPXsP3+ZLEAV5PKJXnF4zCnlaWeyczc96HXdeLyPdOrH5ARv9A\nv03vv3A+bxLMHhR6u7a3JWjKEBfQYWSq492ypx5kO1HWFa+e+tHZ9sqFoJQQBOyXh4d4U6iH3TFh\nipff8OdQpMDR7SyCfrGB5BN5j82p+BZUYSpu1L+K4tQCwarUaKTTW5KkNV56loL9EfaSZmyrIkK2\nUgJ0gpjXddZDUErVmFMQe1l7ZJ+kRZJ37cJ9CYlXfOT+iAT3FacIwZ25K4VtHnHaCVln2KawhaUx\nps0uSml6usvpxtGtbveJ9ISlmgi32gYZNdqUYH0shyaUkYXQ4/LaP9grxwLts2pr9jLpbwd1qCnR\nne/aBk8Xc5qy7v+o8AMJRM3qr1AguoyczetlQAcPoH9ety5wIQhbhp0pRjIn3w3+r9t42lrUA3Bv\nhMlGDK1+5WXdLRQ8dRPZQ+S38+Bapz9t+JzkxFinmSnLxOxnAldd1UmEKK6MaFI7p3fnvQuivKJp\nB5hTgzYiiA1UxVYhSQQ61QIrcs5sxPGJ6LwiaCINNTxmYh9Fpi3YTREqee0T/k4mBB8zmZPkAHrH\naMJ5zfwbrh4YsQLdNhQTHW2SSrE1vyWI6rYyd0dgN7Zav4JCwcqvG1qfctkShB6VHmuJubzqjVDP\nJThkd4gutEHfrjJP4u/5L1QnOhnDvM0zxpK5IiDN6xjV5nETOxqMYsOnq+mxtHe3lwTHcqc2AoEp\nN/I+BWfVXoqUpDRb/8emFGKObNd9eghd2LwycUcaqhf3RwlJ8maR7ZGyVdm0JoQLN/MhkYTkyQKw\ndVc+5MkNcNx5g5/SPL6WXc+wxZ4cUmJPLTFxRiMgb+10K6Yyqb0XMl3VMif8mlKzYnpkZ1IJ43Ri\nF1CLbs5ZcsRcb5crq5K08q+SrbgL/y9xdwR6LdbGuEqM0UJLZM90F4eYrfuUp2n7HGfy3/TYeTNa\nJv3mZ0FzX3mYIkO3bnL7A8MEJ3CXIay0Na2Zr2uw53Gn4ADCcmmHgXwfgu95bZObCkMDa+DlrGkB\no/yV7FF/s4k3KLSN5cKlLAagOqjk6RUkKLaCFCQWd5OlYOO5qwjyRHf5/Xp5AuqkbWNyqbj7ooKe\nlANg2QwNr6l4bsUSx0+lcloNaPGwRPUtJ3o+/xf5QExXbHYheMfPtXUvTQmZrynzvX7R3vCTFyrO\n0ulv7ksdACDYK7CrSOS4Us/k/bQ7p4lJdpAlZFCLtr006VblITBttwzjJPS9N1AIEmTKJaPEM80Y\nfJmeaIrWWfI/USNibFfYGQfEevaMlk/n2ydJ1kjeY89mZEvHOmLLu+3x+web8zQ+/gPJ8KVvWMsR\nc/zIJsgp4KFWWzfywpL3GUQtLdiMQhiZekS1lvMS1ueBJ1tpX7YUxaTobVWx+YUhzcNNRFGY0gKa\n4y+HncdPqZT5z4XZXy7MUPlp8SjxK98v1RQsLNsq9n6ViBy5zrHOEn4TiEs8OB7CPJf84fkfTAF9\nMDCAJRmwlaK84vUIR4BvRKs1cKVH5AsRkSuIqRDKfIl8meeEWbrVBFM7tmubs7CH1+3ceGG3q8+W\nSFZk2uJHDepPnF3rCHBOmoqHPEvB38xZl8tsXrDl8c3jiUymoMbbghIuO47x86BRKw5vK7/iBlzT\n74jFOBZPdCH8RuofG9Hv8IWnpp6AgmfjlUM1H9d/eTWL0OSduTx89FLZfYi2MTcVAfKwxrK1M99N\nHQYMp5oK72wf6hfnMhr8bRrcS6HMT1DzfwKBak2tqqgKUD7naBhJVEn9neNV/Sy4HTof3lydNpbb\nCD47FHSLr+n6V8UWh4k2T5kDwbWSaTQW/sKhcz6wS5I5QMpYpc5v+BgCR0wVeznXsQrSmGG2cNE+\n1ccHjWzeCqoRN+l0Jegqx8JsIO6Ur67NTIJX2i/7S2VQayiIgrXM7yBhgjau2ICzxVr5WxqsT95F\nuyI+CmvXIlJ/2/3ICzGd4PSGLYLoKDJWk2ni7m1mYDBKKTJx7wzHf6notZO285x0fRDxjWoqrVpF\nu9G4Oq0e8xHAr6UhwkOvwwrophf6r1g+i0zx7Yn5Yrd0F3Vx6zWK+4LA+Gke+lDDM7uW+9JUqhQv\n5AalCZOmh3yobbtE2uWRAfV/7x0/Oz6OSqIUSAi31vGlJPfsjLCJgN2AOYgD96vUCgyeIn3EI+Js\n5Av0REAKEeOtqSVP8J3gvmFafYS79pTlyWgOcHSC1UZGUwCucfBfJKBykK5zQLS9oQi+xmiWrw8O\ndLWpRcrP0CGA1FfMaQgDizexDJJ/QQ5ns8KBxi1kcwQkYXJErePgK0xRMb7mUlSgA/k9r8/Mb/5v\nrucm3VTP/8rFh6V/j3n8gqzotK7ukUu3ci5+sN31h73lgIbw5X9CxVvUEVGkZY6cOaZniKUMxcUt\nX7HbNpItwxTM6D4bXZXTIo0YFEEbJYje1zBkgG7mphxV2XbNvDdoyOnbt4zeBgP5+LbKxcxkTDDa\nnNvGnrE5gz9ggtMc70GXYFZs2VuKTqE2YxJ8X+OmnNO00xtQI9oGuZqW83CpfLuKRTqPl8QATDCn\nxnrszSBkfouIeXHKC89yiTRKEkVrA8zsML8EN7LnAD6nJt8kKxBgtPEMfwSrGi4Y5SFi/oThvsJQ\n4aMlcbX3KjCoaKQAXH89vx7NqifsJw8bAbSwU9NObgXKiz+RSingAPtRi1hTP/87rI+O1+Jfb1AO\nbveFrhqgFxw0oTS01GMoXXsfCBuUY2pO/9sk97YuEFWXlX+1+qM+gzOTmbeqPqTiIwsJapKmePC9\ncgGgRaLWb57PVdPINQj5IOrkYByPaUI7nH2LoI6IWGFpPRaIqnooaqsyqfi/ki0PFi2x23Jc1C2G\nEyRNd65ut57NIsN0by6DJYrYWveg0kOblAB1X1l4gfqZPL9nkAinKUZGzkEQmXVu59Wdswd9KUdw\n+W2h9l84KYBpcm7ypBN6bcRZrcR8TG6E+diU08vecroYYCPvqxB1UOMNSlXT1pp1/9D599IP288+\naEZsxlSKanidjBPQlYEOpuf4Uv8/rkuBEBdotZChP7ZJLtsVo/Jze+nsUY7KZej9LoLWl04/fNPR\n+4qONPNYzTafEY4V98vVi1x+WIjmhXRTGxY+ykIXQ0p/4xe5mGnzmMyFRfebqcTTxU2T4E8g0epJ\n+TVglPQ1qFxPiErn1Hd5mV4U61FP4QlatQJN5DEk9ZnsemdE0MWETDSsLnSLICzTd7f0skyOd3xb\ndojj3cxz1A7qr0x31fgODE6uEMQmLcmS4U9GDdZdDISLr0WIn3kg5NZxn3YKajC7bclRBf+wZuus\n+pPa7ncDeVcu2ueAHJhuEhrfOtZPLwahM+FANDKqhAVymt4qA2NR3M9rUzW3/lm8yPfK+pg42Uj7\nrQYgfjSgwh/sIHF77LSIc8cGHcayPoWMoNRgbUTNNvGA7IRRoBSHkg86AnPQDWYowNf2DCaLZFIP\nJ9axATkAsXMTUnr8H8G9gDBULXps7Hsu2sovmcHMueIToEDFk6/KwpUPwCSjyQTIpgy78iStNijh\nem0wP3kTZ+8qAX7mNCLzN+Rfb/UnoAd7qkl7mX5amC7jgxpEMTAc0JFg6nIguuxoBWSA+dI5tQEn\n5xxdGSiuVaUmE8jcVkolyRe/rpl3Jx1lWiTxSOOFyK02xVuGvU+Elgm36UM8+KOcB6HMZ2CIq2xx\nM6ETxyXhhFvomVz1+xDxYBy0edQUCFRqkCy1Bekn+c95A3he6q811N6IgJgPV2K69qGzvUqVPMb+\nSKvXNzcukkdll5LHU9+DHQ8gCJrDrik6pJpUiEOA9UhmjoeYjsQoj7dCm3sTOqHELLemPYZWz3Vz\nUmy15WQTOivQR3y7t2zylhBPzZCK1ai3bDJHhynQ0psdCCbIysr4T9rUwLNtbY0f1GKlRYN+e0WB\nP+XWeJoIxXdIi7TdsW9DXryfWkL2856JY1gJJzMY3DcKsYR0hun1hwhqV2MuUKvQpnzrWwaw+Xy9\nWAptJOM/5vrLqyMvATNBM/nWnRHv4ow0w06C2xsPaygR79kDdZf3A2jM41aHP9jvgFF+Wx6vqjUR\nDkzuLFAET88jmMY6m0lNLvoMON8QhwG6C2dcDaEJMvuVf3uY/I926oIb1jKnmNKJK7n+pHKXB4J1\nKrodHIXDYGesitZToHnljYQIOfJX1JCOCKNDU8W+G0p0E9epoGx0rNifxZV7sku8WXq/HwLH/qHA\nASfTNGD3VgSCzhQTsnqHFeUQxvjO25iDvfJNulDDYvU4DCoATTJD7f+IX+1HYct7MDH9RcRx1ZrW\np8q+C1vXj+Rp8C1aluArwJn3BUo8v+gxaMds1ElimV7KGeexwsm8N/2b3J366f2ec7KAuWc+TuDE\nFqYXEUBMG56uX35TsXOPygZ9ATxZ9oc5mVGZia3YBarCjlbuhPxrexEnW368xzzJg8PzhjjNbHRa\nL/PwyrwwwwpAjSP24OrakCks/SzhCGEHH1BjXoCw9oJ32EX+ssfKgD8DdlHEf7ZssxfBhqZw9oWB\nNWhqZJu+nwdMDeh3NNr7WOyCcPkW6bT1+yCjuGO148MoSa/VVlMAfTgBeFC3prH1K8sJNw/F0VnN\nyDMlrN5BOYfPUMNWMegX9PKdj1ZnkaUGek3jqiY5+3ibx98zF7kIz/XTcaHArUi9PWSPCkknXnAZ\n4RL1qIa+uwOe2uzb9YDUftsVY6lODKeiGtHBxmUNQkfePwm4ZcI7FMvdvPU9YXMvepUaV78lMfdM\nFJZfxJLFqaEhs6gF8zNRhdBGhCgigErz5qdgmBadKzO43Hy6i6tTAlqqeB1smBGWv8DLAr3E1GYP\nxI9U0mve9WU9BbcUhHnNtoEu+cbUmt23wjeMItqPZ51wHY//Xg2X+BlhxnPqjMFYlmERRBKd+qo6\naQpHktNDDxANRcDr1STGx80wjxTTGZ8yfNuAsGKkGdX7Ukz+hfOPmRPbMUpNvZUGCfcfz6Az9E0g\nmv2s+eVODs9CHcW10r2DQpXsuZNRSpCadv2pAc7g4bHmQVe4yiwLmEOrXYdU19lcyPyHmzaMRb1P\nUOaZMdMAz2h1hReDXlQb2GOEwHePfYk5+ny6eyyiNwFb48eS7JsUMLYhgrp2CvMDKHI5ZHjgS1MG\nBxROOj/TXNop/yDVXGS7aw5/lXqNUVujvh/8PQ36Uu9rNFv5WIRWCfUD/Io0BR1Zgdb/8bAwg8Y/\npLKe+4OK245YL4952ayBk/W1YpDYWAGHs89Vig8XNyOtd2iebliXIUXg9HTobeBHRgU0V/3761R8\nuuE1sMqZS9xkMtmCliapg3fhMCREFczbc+9TVRBSMObevMVtNP3SA00xxXR8cEtydrc8nLJ0W1+g\nhbkKhKnrAV0SHR1bj/zUgKTteFvOayD50d8cFUVJMA25sz3Nj+atXLZK2gJ8LSMPknRPl1qpGKE5\npzvmyUBhMK44vB+BA+wDSPqw9mw/a7SmfKw+GAZHwOgIUYEmxbpIdIcoMeXS7InE7eqnAWM9sm50\nBRTtd+wPKXFGC/Oz08cgt1BUfhS2Gixn35BHQOr1YEmkXip167dUkrpxAYtKpjG/ZXcFURjOI5jZ\nPIqeU/COl2a1eRkj3gj6VGMKEfJOjXJD/bojCxqStWc2GZtjO9dURLVzfyRzvVjG1IYM8ReOmuiv\nJc9iUcFuVOGF38RgbHk5sVu7JqkEY3mJBMvncYT13P9kTu5g1f22vl8zpOr8Xqu13LgdikPYvToN\nGTjdsWc5VFPp+usidf/2i/CScLfmMJ615PzA2OxtgISD35Vwzxqb69HEcpditz5nueqwTlVUS7kL\nFDABgk1DSEyh37X3n//9q2Aeka2osaSHKZVXfjiXaLedGQNjv2RVA2xJZb19S/hlsKTr/7FPbRTr\n2cEso2VFxo5c264T8IwwlLgfv3QWlltq/cI2shq45yEbFZCv0kgZJgATvNKO7P3c+3kFjNYFDq1c\n1p5LiEpuR+HiEVGiMSqOUwuF17bjnp9orJXvfpyQpCZDWqa4NjIzRWxLqzf71o1dszSfKJ6RNtbq\nfP3Z4K2m7uULE6yttNSeK15YyxkF6LID74z3O329d/sEh3ztdguQ398ZAAPJVcbfjbVk/8tXa71y\n8tLlCXQ/StxkGg3RE7cLCRlMkSBFABFdefbAQkzwyOfo9wi67jbILIgybuLMdYg9UNr/BeqLGNc2\nJwu0Z1cCMxyvsvZTeUCjl3EKudTSOfDmAcFtDHJx5DHXahzApXO0pKSBtIGNMBA7lJhgypA6QXoi\nOn0tyLHrn9HsVgVeitJPd7vUgLcxm6658oDk8i7VpBcBp97rVXKP2W2vfr4pwcwYglK6hDvCiOOW\n0kkh75zr3CViUN26CrUVHX8Y8qYk/Jzd9IW0VbDZNQ82iljN15Rdnq++k8aABs8HmYsI/nYQ6peZ\na0VwQo6KAwpYTQuT0pbsl81MqlytHcHot1TmXSbIP5a8mJIaxWi+0Vomr8+fzcSvf4MW1/h/Qg9D\nqtmauUGXOBOsMcaL5cGFkW95YH7zSm1DB9bYnng93uNCqdfeZ9VBVC0mIJwKtpzq+VWBryz6jnJ7\nqbdtY7FWupMovComhI9cnbl/mvn/hjnrKwMJ4ASeiTJAIEe6qJCyTC9ZTjaEMe/smuBvgmaLW12M\n5+dwSftWw76OZPH72Lm5eHIzug86I4GKnAecsQVv55Y7csIn4t8HK+7D9QQAb1ZP12FxmRMTXNyK\nkbNzR1IQxhr2KCUyRLZ1ygAy/lcrHLKuljXS671N96GwEPqGs/UCDsZyELKqjnFFOLrR/9cn8UrZ\nzag54CNr8RuzG0iB36e88ZLaMb4MTZdWpaSuVOq/uwip0DGk704sxNqaCjYPUqzQI5G1xySjjB3c\nnPaZdr5gX9LCenaOZycV+npwrf5n9rZidoP3E9JcPIzunMI3V/6LuT9yYARhUdK5CQ9ll5tsBKTu\nSWAvCwMdg7jjGPes1Wuhrj/Re/DJrS5aIbPjMe4Z8AdF58eAzggGudhaBmkZt0TXMQf5/QyixH3z\nODdqqw8LVV540fUKvlw/ohqF1ZOIYa/wGfSjWEnIgA338n9+99ecFSEUA1JWuiDI8UwkKA+BTjvk\nEdnCAAbL7QQ4GsZDOOR4SKVGHbdYnzplSiwjI5fyCNhcg5oCr3r+ri5FeSDr4zFwPA5qWLT+kA8n\nJ/XfcqsBqv3yuvPQphojq/izAn/HyzKoh2vFqxsUlHxmR0eW1ZSOxQyKfRG8SRsXuorguHJcwXVI\no6wz/JXYzl9eHdX4Sk8qhkwe7MNDipqgjlUzaY0jJm4Aq7oeQgGt94/lo183W8yLnoOTv2us0XZ8\nkTvGTJ86vaQj0EXymlG58kxmpzHQM87I3ltjR7rvb4X/yBPhW9d8KTD+r+j5ZRAV/yx/KOJ0YpVJ\nqd1VKVjV8uMm7Y7/aTYNW+GNC91RIBwOnsrRVljE3WfGBYbbBu21+OTLfeU6tDHn3cnuPraskvmD\nOTJ5ZFet/4juDxv9URcKMauiDAIBVCjnd+Hn+LYBDRtY59oJ0y09yWV3N8xZ9TPhdnKYUya5bXWH\nL8sp05RIlxqArLnNDCqQgFnkezjZl5Aic9YV5IcRx94Um2M3HJeoWcjT9VIF7TAD3jBTLexobSuR\n/eg9TajPKm4FXFHwbB0r6CnBjTjkURjMpAWLQ2d6vw6bQrDyacKiRFA21BjtbGdiUTzSSfCdraQU\nQQ2DdV8mYIQJWTqqcu6pF4Cx+c2cOCXQ0flN3lTe/8LyZQOCH905/i+GoTzR7CucnVsm4c8RS2S5\n7oDnk4lB/5sb9Dh1uKUV32DAoW6B5F9Du5olUvnDHGNn57ZaiX6YSdTPAN1nunzvogYeoSr5QE0q\ns1hFf6Nus841JhHQ3hUUoXnWfYk/iZHTJ5YzdGfJQ065OBuyi4EoBUxkeJ3e7LKeOxywOijxlK30\n7E9cy4Dr7sXHEeTcN9bY98KTtA4Sj0SHfbDMB8UeDv5ySiJcdRoO41g1TRS2xarcu3K2hJlnsCl7\nY5WcfP7tbTGvDOJmpyLbwjvA2GcwoBBfBt3Yh1Iqw/lg+jgNNIr+rqnQuzfSB8M2i6RMVb4k/EF2\nZWbLEp9M0Y7y4cq+XvO5SmM/fzFOgw+aLCqUfIa0zR1BP3nvtwyZm+WZB3Yc2OUjxc/kOllY0ONC\nSsX5Np1uofDlAGq8k2gu57EdfDNuEAPfsYqeLsbOUGoUa3rNcf+4lmYL0FxD5DrwrndUlyc21wbl\nwrdPxUWXjiXXvAR/ejNQ6Ok/3vRkvoVh29/n9MdTijO+4dhmzSCOtZQVUc0paDI0zEMexMP6pc48\nvYkZZ7lIO730A69gXlxkyI7wJ9Rh8+/5Hwv/7LtvpEbZ98eit8SGjoFr8WsHklY/w833yFJwbKB9\nRzwnpFPOpb6ntg2cvAa4Q0MQjR1Y7tv+zkg+oQycybay2pZo8VQtqS/IJ8KULjjsHrhxwaAro/3P\noTzKKWECbwKD2qrIIZbo7U+tsqi3+HBQ2DAiGCOA4M0dU0HWbUpDa0f8B4ef0y53Z3U21GE+CD6E\nJ4wxrL9TrdYOfmhRHVzN6+gnNnx22W8cyb4DM9boAqWy1FhJwmClcTSkH7m8rabofZ0ta5l7yD7T\nanmjF1nAS8pnIscndyFXNpf1rvQC3U+sV5qjFrkz0cFPD5dONkQ2myi+fRmoPhvZJmzFcp9Ud+pX\nRQlvjGIxwaBhx19OeT6t5zRdk2eock+AE/X1f6xfeHUp+ucNDPJ8z81I5JBCnL+zLxpOQ1QMwRof\nM6gUzIiK7T/dVGYSoAnGcZvGuzlw7EMKe5+uuS+vMnqw+6yQF7YCLfeSvLhN7ciKCb84z9OWlOvy\nHFoSHtHAXIij574/kZG0pUnoRR6DPqmkqZm9FSG+fZRvv+ux3uOu4I4zH+hRYHLF/OrQ1xqjALSc\nV5Wkkddp+7zu604vWSjWu5dPsIEWWyketILV2NHCZAJZSLh49Xmz5PMfEfzW2Alk//tWk63w1awn\n5Y9fPFLEOITe73un0mce0x6kMekUV8x4im3mrhj0T6A200nyKbPg28A4rEkz9BMLwpa28iudcrn+\n5gLLMdkYeRygEePIYgcshWmHyD2etcgr0wlacT5PeWch2UjVubqFoCiw2GrOi6S37+gywBL0IESZ\nAUgDUq8oEiTpZ/XZueLUOP3dvl5aROpXrgISFkjY90vF9Fl1NgeS45uqXtrmAZQFWG/GQ3ddS0MH\n0l59z4/T57CSCEE4RWqFZZff/ug5K7VrW0CosA8kl+hbJNoJk7bYW93KoKo7ZibawGwvS1YO/i0u\niroPV3zQtyATeqmxiR0NhDVvY4aLqlX0ekuMsA15erTUCVCVp4+aFQWLOkoJXNe7xqzLOCFKfr+W\nYEEG3ZNNfnbglIgT74sz8GKh6pGidmUW+KO5A+3A5CJgcozObzyjvmvFrBHwQgWlL6az99rl6HEZ\nud+9SvjoskXR4ErFCD/t3p5sHfoAFYWnguHh9tL6g6FV+WbVYFoZ+ocxzJXHeJxG51+ZA7sGt7vK\nPR3/ZcMmobdTbvvomm7DkMQGDmwATJqSxmbRcVEivNUXw2jf5UUIIDlw6dr0N3lYYzcomx7LJe22\nr0TuHdbAgTzTwnamne1mLgc/U78lcZX5FngsRY4BLVrMRCDiysVXhhGZIfxZxWyI8/017nv5YkgC\nHz9hsFYM629CoQsf3TuGnKil0AR70zJtUb2eMqQYREXnPyG03pUTphIY2lqbmSws/dGbKmlmmMCY\n8g7C6MFSOC4cGx0X7+qL6yb7ue42+LZG3QH8dARUVlMe6lIC55vxFW+h7gxsFtOaPnyhdatNFwgO\nYEzWVXvYhL9Dt1GYEw+kys4kMERl47Pw+EPvxE+FZ2J5Oy9a+bRsjQWjjMW5QZo0LTjAxiAqpYIu\n23YJWKxzTt86ARE/KUOvbZK/coNDIVGK4SaWsLQB4RwLLTeGk1/IAS49/cfL1fpGwYaKoPSc7gwb\ndFINv1JgxG3yMe6tEyc/Qu3mRJMq4FNId10uwkwHdjdLRZ2R2jSTu5EbDqrHL2h5E5HVQWlEvC0j\nwpLjPGiLKUxgdQG9rfDvAqMpkEffvqTw4UdZ3c/niOYB2Fs05aWI4ChzgZBNZm4EgYTVluHiXfis\nbtLainkK4CC3GXGulcFxDEwQ9t5APiKJ2wm0ZWmzNXB4HI0leK8b28f11usJK+JXXcYQON3D+u//\nt2lh8QejW9YEhyjauIRb2Ryl2QQtP/pNbrya7TX6bS6cMLs/JxDCdZNNew+OwQYkOX+ec4jI31hs\nLEZVq65aE998jmOd8/nODQRSpI/m7SHCsoGrRNuppaNfZG86rGAtrRzv7DmvRo21/I7sD/4J0juL\nIVkXTV6NUY5dQCoFOlZrKPcucYFEp9Gza2UsiLnZPP8NIE52kcsXgqlI0va1f8vC/OqkDSNtfE8H\n56On2995pcY8KcW/8ZukuLW6jXoz/tg4j6juTvMMQ4MJ1HyjE4zzpWHHNM7+wXT1nWxTODy4fjov\nsi7zjbY7U7pcaGHGbHOUJxETMMF/+Nu/vIHy8929UqcdvRaFLsfosterIGtWhaBwDnVChD3zrh2z\nSUc0sVtzVlJ/8d2T8PY+AvDOjNpMbXOM66ALhlfHP8IigQ9bX9RtCf/y9rJh2r3it82pNzITZAUE\nHCoxuYkxhsL2DWYH9KbebLkD2Vmkf5GDqQiOwcS4GJhgIQg3H1cNGPS69b3Oxu6jX9KlTPtW/Cwh\nRL7DoaUYvgWS0AR/rzSw4oybHZRyhpjKlY6VknnBtCnr7c3dDrwJ/99Ei8AHaJVO0N3+Rqi3hnAT\nTGx9VavTS3DVL1FsQILkuZT1b7KgDdp2MXtCRcQuf5qw5TqbY42RY7RWB+7p8yCeXNjILA5XTd2B\nN+8f6blGqbqzl0yR3/zIIa2EqlMPJDKvvXrELIa2zp3ADTK/nuhA4FEsQY65kpNuUGPXyLH0xT67\n34gLEegwXNZXcQ92yKdZDdMwKq2wg/wA6ioTAWC2U8WjIehhloIrbqTCFC4YxmDh4QU8w92B+wXX\nqAX3q7X+M9dc8lJqKuk/P27ZPNoFbLrPk9jd2nMVsRTBb93U0aoVV0iN6TohCvSnnPeaNXF0Kl1V\nXObaLgu9B1ztWjPKcuoUdbr3ynxAdDF/LKB6RJkvn40s6mhyp8ffXQx4lKxLSo+1ZpIRm6v7uv3k\nLvkc+be5TPAmLA16vgEYT8aKmGjBy3aBt37TScLNZa/ZidyWazMSzOkM9nVCj4yQEB9HK/OLauRD\nHW9JTdbb6058rp7efsfjtKPmdYVYBhjzaFoTBxJSL0BMjMl8lEgEI9lsRiYgFoljUQW7NAG886+a\nerhScdfX1SBnP3S3VJmTmTUuyF51J4OfTjjr/s96yt4LARy9iKJT/wdHeQRyTqZQNY+97sE2nAwj\nlp8jVz96hioWj4XUt46SM4u1EKnIO7Nq7AEM7sKLPvH3MVKhjKFpZbAuuFodi4TKm0rqlvVDHWrF\nUgCS6WLxcF1xki5qmPOewJJlw/oW9cUZUbHkpvbaF50/DHzw6umT/0oWAnpzschvu0JB40GYx/I3\n/ionhmznTJ1PZhYkGQzyLtw0ffFJ05XYoh/4f7yFWNHxOzd0E3A4YdwNM3UloPUTB/zQ0SWlAhwF\nOSPJKXKbrkMnAIqSYnE2dxu6sySKA++v2Uw+dUcV/LwQLW0dkm3qycOcPURWiLDjl602pZV11PeK\nqq8FtvERKYtrNsCdnfGlzSmSx9mO2ZwpQcaGah0gE4CLYtJRDi8iFfQnGeujmqT0VZRTI6K3vm+v\nLFEMHAXnLJiQwZpTkk3g6RKF1bUxTzKpw2dC/OWZaDeX2M7UV8L2Y3J8AGU7M09qlnyKOZl4TO+R\nBpM7d4L9W8l2oU2Apg4/rkrL29+bYX8l8QNMxKhq6TYIi3tjWUNyavoZCRKFjWYnA+VogqDDu4bN\nQu7dhi86DujjfXPhIUrkh+zbpfv9F5wDERNxvjRZrp2aZLRyOUiqlPJ9l0ZRI/1IqPYrkKvO445M\ncvfvOupsQDzwSAoL0SpZWDMgEfZJ1IAZE1dVWvuI4M1WNBDOOMkWh+UGUGfiQW9/Uq9RVFWHetxr\n6u+e3jlCYlTMQfUnA74QHnyxO02bJxuhMCxFOSvD7uc7hqxKq97Q9+obCllSOluuqN7piOqyDu6W\nItmtCNk75gIejKveVUm71wvk4kHpQBNnXDqgv+fn3hR48bXDh3KBgioOQ4ztr2Ahfz4ZB2mkidm/\n9uPujRJvDHFIwsTDiAW4KarPBNtOM+Nxwq+RS6ijImvLRqCqwE+BRjeJ76li7l7Eyd5Mh2qI64CT\nt7wyQBur+92iyJD86fsPX/TL/Zr0JbrUK8mlCjHdoDwoPHMObtAyETVzxs0ggjnU+6gxnzm4hg2N\nycwqUAUR1jsx/5qRPLsUrcdvoqwXb8it6Fwese5huT35y0rTnOidYEQH++o7FZ/eScf0HeTFSmt0\ngpLfjaijfIb26OIdpvtEiuGkCLkKy4v9Ah/2wkfVoPFl9pIex8Qh4TIalpDuQG469r/NLJYwzJnc\nzlyO1WJOQD1o37idrTk8FhnwTdn14YU2e6zAz6WDRqiqXrdfXFkkeBbkw5AIoPPi1a+vZllnyqJ2\nBoxQ5WqkRW2RKjdx20l3FGwMxwKoXWtSgCGofHtQ/7ZNvWit/BIvSTxFnnEhoIJIr9Zgxcjhm5Si\nFYGNmcieK1UxklyJuJqZ7Y3Mq3j7rCweJBE98/C0mEFw+5IXh8V0w58ZymvsAahw0uVRq+T+YC7T\niecKpwYh7TeDv8XamERBGIOPZlbtNPzk/RVGQm6dGXsrdkplctDVTf/VBFnWQ+FyeN1IKph8Cnmr\nLXBcd7P0AMhgoribJxTMMS/YljS3i7Ph+Dd4YBRLFheiifmeU2QrmyVMbKm/Y7lXtl+ZYt0KvuJV\npYWy1aD9YGKFd2W8QaY0YROvZI+xfGwA3YOtTCwy8UaGceauRKZ49HOFpnmBQTnY2lMzrRoNSw+b\n2ROzjdZvmhU2wY7301/cpM/lmo+YqQvaaN41pg55+29UF5F6yjb9CGLT4UD+vLHLsk2eSgcZs/tL\nKs0Q0NWow+2m4/4reWhjJtgiz3xu9s6jDi3as4FIfipkPQfdtHNA0BWPEMZi/juObuNzUp00cTLK\nl2458hZ7f3tfD5XSNQERire2/YCZ2jtInoVlCio40AuunQlASwCnOYLbBChbnpqTfK2+FSvvPV3V\n46TTnNFu4Y3RDJMOE9ccr/MW7vHbkySkymG7wHRYh86LnQp2rFsGStklSkXLgrpBjpxjEuWq+nbK\nVIJGsfhDAzR9elnN3GEGVJ7i6i9UliygvmSWULSAMhHo47EcY1fiKXB/kTS3i9VWlyKWY07oAsNA\nxDHh5UrDWIhoDl/h5hrg3DnnMl9+uWazkWoPuf4ZzMYsWXM5YL11bRjB235y9K28rWnerVREfwdU\nZ9US5urDGIBFHI/t540v+jfHaQOgnCZcWJPV7UPQxu9IUJPCw6/PGKeXAZIk0yYS+Beb35BBAjLu\nyYz7iC42RN/RXAun1FJr8B0Sg2fV8YYEUvCeYLYlAI4Q+6o2rplyNAKPfLQA9Oxg/7R9GKOLaK5f\npXl6HpRA8i9wUYtUNJ814ge0q5Tqoq5NeztLPdLSr2czqZ8KHLbuGVNJLYZPp2MCesog0H4iXU6L\nVWaW0xnQP3GBjMILcr/LhgS1Xs+TV7PCjwDCAp9csXlIcGX2gyg7v3l1PiYQ5tNE9qtGyIu4aE06\nTLxhmKt3O6JBNhYFf59saxKJmGs/HIcHx3aH5aHFlrzpzkkXBJrntKkQG30tIt99gh1kV2hPfUHP\nNn4f6kxSQZupAyPp6mk6WJm6Nuvqm/84UNu4MRS0H+PjZv+5ebC7yMC/pWt703wlyoyumcqG3nB5\nsevvqvLmGUM7ePnXHvaxePJHKAZwzNHEnfLmUSGE+4bLiFev3ujYMbpNGAbYuH7zSeGH6qSlzqxv\nlEkwkitsTiakpPEG2OWXVM9LrYFaUWRmUO1QqpRLEZ68rlz8m25qSqJly+7rZ3XrECEo+qktcwtE\nQ+fTI8BU7FZzO4M7hx2dfCU5CaRF8aD1IjDFkXFrSO6xWTAVcVU60XXsAjG9tgQi+v/qXcX+Obil\nncJrVSyOTY4tvwnADlHpjIye+xdwKL0QEW706g/6gJwZJLmlxGZQMoDQ7ApCo4frAlIV+udOWTvD\ngrC4FxO6EDwG2MXYbAosO5+amTS3aU4Trfk2mhZthhbZkL/wjaVddKKhoQZgDKFD9VM4AOLJOXql\nx+hUrIjgEGkuIDhJlUADjOSA0RA2WsM2j0SYR2KwsCNGW378rnMB84WRRSpFQwUiWWppmzXnRQUv\nCmn9dJen1K/YssAmD9aHxvK7Ul0RpaqacvMLMU+eCUzwaESX451522D/VHxNS8jgn/TwUchIpB1x\nW+NWODtKNNGK+b3QY7+eFUcV7tbLhKh97jyAfb1/RC4xL9hiQN+gnxpC7tm3Wuy5BYfFOnwpiOE+\nzc0giqbyi6o747RdgkHySPdjbVWRnKDoskIVi/I/BPiAcmtkC+hhGWZks2PaHWVZ8+YySgTm2tZZ\nuQnzzRHzc9nNi/ZnFE5FCaWaMOjKCp9S4RsDJcy2DOW6wluxxxZt1Pm5SsRb1zNc0O1BmcRSyn2j\nTSMIgfAG0XMrOieV4SY/wXISjP505CJZe/OSwTva7+CU7cGzDqNTxJQJmfOdyESeCot37H5Nbmm6\njCW4yUvlEHEo0+TAF48u7vI8FX7NCS4jmOUan2mp3cydx+NA8FNZr8yK/oPjVVETB3MEO6ZQV7dA\nlnsIRPoYwxQbPfLIujHJ5qhKqJnhygyHDrvCLvWD9kqn7curVbzibNLPDbhqOn3yahoBA09q9uCM\nIrF/ytAmZzKH2Oe1vdpvMTLKcoh/rC3hLEp6UtSMHi/QHdA/r/yY3oBWqAkETr77vD25TSDQi5sV\nUDwMnP2ZC8qU+Y57D0Z7DCGc5fsTFjw6N6plRs88e8Tnr3THdt3cTtiuhK8S8kswnjOZIpxiREuv\nem/w8BY9apCO29TO3bLs42xmrkLem6odVJXT7lSFEgQbnZhPIS4EU15yN6ngc8K5poTsyh7mfMOU\n1PGMa3CgyNRaoLWmZwIjWLuRSbWFiX2+t45Lh3S7V4SzLdDvu8LwZ8gvMu2O+fsLV2kMg021k+6q\n76Dr82dIIxQhqttWKptvHRrwJ+ArlXIwXmdVqn1f73i2UldIrsu3QUNn+jYZoHdmD9kwyuYdQ4j7\nWiQm/ZhYWJMCRblnJ5whXqQvHAhuj+CDAbyoZrOSw6jQqPBL3gyazs7QG4f9FDNoR28LFGXWGhV1\nHces5TtatLql61i7lSyZnq7v9L7ohKeRy7WtOABFCuYw2rXYFWvJLU2tnx3A9+j4/OlH10j0MdNw\n7YGIoGqiq6D+UDG8hxNcaYVW89uJwSOd+0DDN5TOaBdfeHYfx4OL252F7yCKlQ1J2yp63fCAvvKp\nYxUXacWAy8CFhYLKIG5AYAtDy+xqwUJQ0F1288J2Ah4gNdHTb+oj63wRKDnZX+2hutz23PSQyNKR\nAHruzJAYlpycbwvFWlgUcbCxLA30PAdVCp+DrwdSAT9vA/9SYI0zmw2qAFrOQEwyECzHr/9d1qeF\nzegjV11tfI76uPZ+Je5hww2CNk6YZXstvsswshWZxCXF2WyTge0hUUUnf8mjVB22UCzzoIL1rsaw\nmuleP6KvXHlntQVtgr2GukudCYDkuULBtG4G0XOHOfsugbWxYbtKLxFGhh0AjkDSETvm3k6nW3FO\n8U6KSbf8DwP6J9HP4LOKW/GCZUCgRSxU33sYRcqu8aAupr4137RqDNjFCP5CO//DttUAmvEhMOIG\n+6nIwKZZOzXrQ38h9VVHap0xUs+vX9ewjiWlXgpSsoSQmnGc2tEnmXi+guBsMJaR/InDQzn6hpnn\n+tmyFxERGMcEq/qqZEJPwoQKrtIak15L/OTRJRVH2A8pDudljBGchQiYKDnxtUDKEr32xQ2tqXM2\njkn6fVM7TZmRWWM05wAdmCCgro3eMNcOXHxVV5K+0CpRUGtYQpvedUD5TNQeUW+UFUnLR4V3gO+y\n0rfh2C5gg8Ax797gJ3TmKGm6idWbkcgOnMoS/W+fYLJmw1X2rGeLeWMk77MPuyb2NKmnRzA0pkaL\nIaN0SYru+FFyv1gd9VxpBYQhIV4/7SpH/wiSzmjK8EQ1rDyZ3rDHUoE/gwHVUzCIpTJ1K8ARQ4QW\nHKIRy9460VrTt3BAmrUEp5a2KKAbUbEMgqQCDRJijxtAG8i5wbyBD7iv7h/GMpg80XrTVnkb2vhV\nZFnR6yLP7SDy1LhyBybX+MJT9IvAsaeHJnfTcSgfIXsFbORlhnjUF6QriLrOjDw6jov7w2oyeOnz\nrNN2ewxQ8fv9SD5VbAm8mLeTSd7gZ4Q9vLpjTghUIDD1iJWvRTkYyAAqQ80pJvNVSXewluPZC+1q\ngVVS+Q4qtQHfm9AFTxqpUBqEShHi4Nv/eq1LJbd7ZhuAj5jIML1q+FZw6I8Ap3gT1oCHJpRivMBV\ne9nDm0C2EJ9EBiDCTNyVVef6cDizXTTPsUSOdV0+c/PwWFWhndb378YTIM1dgYlb6NrhhyrVizN6\nzp23NqhAi63x1pmFvD3HBypXPUy3Pe+vM6lRdjpeyocejZJ/xDTahs5JiGhnMg/6Rpf+WzlJhPlU\n6zSAXZbFoiY11nBBi5w0Ab0GZjqhOcBAx6nrplzdx9ijavcJ/oKYOpU1jAMMfzh70/Q6DYOQEZLL\nYwVz003ElvO5q5mjir1WJusBEdjRWD6g7yrCj7A43l3iEdW39+4s1t1aoABxovT0QbpLcBH/XHJG\nseCJwaFUWfdJEbloGEd4/ua9H8AsiMT6kuA6CwJ9hYJVT4lSD60MDRPFHPRE9bzBZmap1L/Chjwg\nJZwYImr59oCBYkRC6DJYpinKECBYiR+O5OrJqirzkum65suyC7eB3AfRASnGJjA+vb3Vm4GFQVTV\nHxAKbW8LfUzVd+6m9gBy/XjKL1aBi27NFKFMxY+CBDGh/uFUyZPdGd9VO92DUlnDAQkeR0CefW9x\njXmdAMh7zLLiC3Gl4aHNsZ9LyLFuyrK6XdI/kWJXkwyayKTTIz4JR5g94rRF3QIRAWP9ejTyZ7kQ\nYpLFdzy5miKDK0aNNhj9VeDeAQH35aAvvo5m88oAoAqZMHyc7jKw6GtGTHgg7t8amVlmiC3jDLdw\nyZXAEDt5GFWsr95/Bu0gdbnPFJmV+KlVpuoY2copQaUb/H4g89p+v/Ow60xw4Kn5R0x4Bwzbsr6E\nXz8p65u2uZAjwRbDp9bKywOZ5P3jYp2LdFZL4qdLPgsmYHrTf3NOSeoFKFl9Y/EjcGzmpowgJxOM\nmB0c7vuIUCqYkT88lc4SZhdXjfjAlHK83bOhz8tBFsV34OrNrJraXmClhUFzEaUhowPj4nHQOyRM\nyCmYKvaDvD2gqdVjiRAswqOKQlDg4CfqmMkW1zIWB/LeDBra82mTG/KL8FVvUyy5Yn7t+Hq3d2Ay\nX+9MlAUH/9DxLHJdof47EKScq8UED0uAe6ZZKgdUzqSeyv+BP/koWVax6Q3k6F8H/ctKP9k51moC\nF4HJe/ZgATLeCZV0sPNA2w83Pbe8yCglxay4GoB81wfshQBivrVBpNe35qpigEAUjuvWrTLYLd0X\npi8FVpmHINUuLP/IvSA4Zvco97kSCbAe9bN+W4P4B17a9nno51f0Pj8Bv2jZ3GXZxXdwRdUTxpqb\nyg1ylyrqDnfwVzUt9wPj0LOAhGyTSGgFbhsOgnGi5ue0cFcwGWuajB3ORmGCfiidSlj9x7cuFl2T\nSYTp9tfIbfuTFHtMHmhtIWt/trhjf7r2pX9D2jFeJp5nax9e6xS+C1GUmCOiJsI42CzNhzpWneMN\nJmHHrJVis9FuxR2oGQMLTRbW3uUaDql31H+P/FbaVoyqXCJJSUSJfrdccSOscQx86VQ5z/b5bJzk\ndI1Ct5zLi9KH+cJb0QRC0lLUJl/2JS8ApWZcXJWq6XBpLWkwSMVDOdolV0+4yFbd/IpUYMxSpXsl\naJX6+SwCTZc1BM+id5jS7cOJNjBMC6HN4s7mVZQVrEPttKB+FrJuZ0q4vdQWxkbT3PleSyaOGiDk\nh4PNrofscdL72bzxXuVmRbeGF+P4NXZLRbkJWZzuWfqIFTjlsdaBpdVuXO1h55R1+mCBzyQlinV5\nh0VeKx+wAhhZ1T3hNGJm4SQrCY/1Sj3EYeAxhBLSpwWbZZn9ZcJO2M1KRGgcUnESTlQwPFrKmeoS\nIisTfDMTpcHs+Kn7D2gPSNIl45DTvtRQNJM8xouUEVeb3mgs7pRAyobFedvzmhzNFAAeqjjoJxa3\nKM16Al3wa+VFyin8QCMEV6hSFisMtpJALGTyfRG7ELpdjVI8DZSK6K9SIhsuy9DJNz1ehbpAXY13\n1XtRbfH2m+IoSV6N0p4SslLDug01wj+ttb7lWytlbA9+SQ7ddsSGcGr8RkOd9lBn1LTx7VMuWE11\nBmDPcEaFolACDLCf5dG9vrhOIkbi/QOx59J/ZneSplHdaraptocTjzeepJfcdpMFsJFAguJE2IPQ\nZjzFd/pjbzuZ5E3eHuFNhmOPspL5eBmTcRWbghCa5pT5FNlpF79N63JDJ6vp+iQx5TOKaF9KGxY9\nhS3Hr5aooEbtuCfAS+cpeVMw6cq4bsn/mT7vIr/LBhK21hQLypO3uf0azFysROcZeaUlj7j3UhCq\njEVA9HDtNGwdqE4ZW8cWhhtbvTOkQgd7aD/D2Mw2L6NMPFeY8HEjjBmO4oaiWApuA1PyStOTNnWT\n4SLiJkElOJbBWQjiIh28MCJww6iIFcU25xz40nAVqIAcLa7GTSFNWmmkD+pQPFY5DsyZgtGNh0Se\nYte9XF5ACTgamrO4zh9CO2sh/+Za4mdNAKzGVn/QVAXo/egV5zItFNStKIxX4q9mMAn2P4pawzbT\nWlb//v9xHloaE6C3ggUXs/u1mavDdIxbdmmW1gY6rDMw53wWl0TdPKnMRrGGudoJUCHsoMK7HQRf\nufUi9xI462T/HUKxGvLYv4UDen4FtXypJYHHLc97SqM84cadTdlBQsCGck5MkStTERRM9Lkz+6zd\nGPPGzh3WDX3LL3h2FRg/wiDYN7XhvdgWWu8Kv1Mhk0jqVcgvUy/hC2jCXTNwRbraL4UvcKYN0lTR\nXaS3xF8X0y1Dk7qyO+48xnn3a/wd3PBD1044iTjUWoKvWVNyP07tp9cKS/pu5tbJioaGREj1g0ZH\n2DtKbV7cBqq/qZYcF+za1qynkqXnQSItvUpyM8IIzpWNB+pYpHzFnCC5KITZJuf4T78YIm4aiFsg\nJIFdaUtZaDZOsl/J68M396VjOMoW8Hfeiwmva/0i43pGDo+2Iy4NgazpSBXzUxeqFMDAgpxmICiF\n7HtKcc+fsX3ZT/8+3xy8ttXYoAq0RgxiwDWqL0q/yoA3J1923QBDyVklz/KmRoRpmkeyGLb01Elg\nyRN7TSwgzJAMWIA1fcEDNBnRRLTtZ0AVSPd36/N5JhhsL+VPqUzvYl5LJ4H8rVFpBvJH09qud3WW\noV0waMLca1eccNscuh25wB74VnJ4lhrAW2ma6H0593GXRELhkN1zo/dHVWcJeOxmS/zFW+Ku4Xz0\nr0Dgn836iBSDrwIIiFrICtvhuAj3i5zyBkcTdd801usBufPuV8GxXMzGdW0fArP9SR+/8IepyqB4\n2chDor2L0/Trd6Xalztv6uILpkiY/fgqaB8TWk3wYtbHUAQgmuF0XWO7FnzG+yc1fEEMblIGc0Q1\npWhtiTdFTH6LtyUaena13LU/oSDetchXA6LB6YBklzSEbSdlZOcZgP1IVQ8VFG1Z3Bs8haW/D1b2\nrVzBN52rh75pS9FXyIMxpR+l68kgpycrDmJe383QUj8TD0aV8PW4JGlIrqWaxc6WpNxd5JodeWqh\nwdFBiXmu1z7vnRHdi4v1bWUzaPUsLlkb8UyXExgOYhHQZacXD7btw3uzOcMxkRn2Bggf5HZyr5vH\nCD28pMECfc0Gjkh1kPkhRNSdSB7Acir6BKBKqgIFjEj0+4C1OOlAct3cYV/7iqVlZUL8jeabqCN+\nvseIbtfhJqrtZ8NfSTm07bpV7HQEwcOTRY0B3nsWPCwzKU04TxWtp0ZEBwNRlY6DGzf2sl59rMfz\nwUHoE+Pu+Uc4AL/6eVLdtTWKRfe6jnsUXMCB3XrWIFPvKuvhD9ZKQVR/YhcR7FDAgDHwmaoT3ug5\nqfKs8C/bHhRJGipi6NP9A5hmkdvBk5nDT69grFuCiukZwYF0ToXhDUli0K9ytrmI+W+zkh5N8Rfc\nv5KyUpZc6GjmO6Ck2hPmLBB07cNS77mkI97Tj4MRe1oknobTOubXZpnhu8amIX6SYKB7oiwb1CDH\nGwt4QIDK+YuHNNtUAkfy2NJ39ofrjpVzQ1W3fRwCru22smNUl0wu/GlrH2kH+kKN5XhxAfTlejoM\nLvmdcJTcDb0ghcVqTQbDvc6RqibKvSLDlDXSylR5Ld/Ru0C9oQsCb71xKcxN2BxBVs2gUjCQcBMm\nKyY+j2G2EWd5VJcvDrSLkika+q494F3XnVozFGlHsjFfEph0PIzTFqr059osIE+GbyxWD6hHLVLh\nUr8++dzDKRvdCxXSQwjBnbwNwKdKEENk0vobGSsWdo7v1ppYyVShI5Wlv/9zd0huXZWAA1p8D4bG\n+vOPuQdYgkAl4XPs57iNMfaDZ1wwY24Jiho6PebA8KDv/0ArzczKShMQN6K1tOtSH5iHYSTnlnIi\nQh11WL5R4OUjgGMb/5q6OhOxM1qEMil/Vg8IaxmloqnOYf7wp6QzmfbVhiBRi3JH/xx621LFne9O\nWx/iprSRi4zKefqU4hU9F8dZ1sp5p84l2sW0hGIfpJUmZODwAPAKW2T+ApglDPqmYKnbDpfm3D1R\ngIdi/9CxdRDOJn/QRXBURlAYuGvIvuTstSTUjs71iPJsjCLBAwp1OujwC3gTguSDPaEGxjFnNz4v\nXSMTfTVMnJAvYzS7j6cXwm6464Iypsc+iOo/0S/whd2swP/zKK94guADu8HijwPxFru6C9mY2weF\nw8pXZYAEHhEiQK9Uoe/WaRYPU76e6ap2IrDN5w9738z/b0azWrXq/a/IYV+hl4M9oGYrtpUbpjV8\n6jujfg6F3x359vtfW8dQi+CaHOj+9suA6pOQ3TB12dA1w/4wdf5/tIzA5J/rS4MPeE8N7d8AkQYh\n9GjhEEJIhQE1trDHASxMRao1+uGRKa2sjDppKNaYkHLYP6q7vPQ/bRaHVwkeQBm+YT/5lb+shAu2\nE1ZB3vuEFaEoKE6ekupRwQuRgvBQo/mTwZP90Ix0FhC17acYGyu0WFN8HnUh2TQf5do2/8D7WRyn\nw7kU6+5u7QCCVzvBE2CejlQ8AqMo3GZvsiQ453PP7ZfDecGjme2xY5ivn+tvOUlOB97V/RK4X6/J\n31vh7rtsCPwP9J0cjJsjQSdeX9TrcuBsh5mykNHY3rn2aedCgKyqw3CSfkhQDZAg9gA5F6IMyMH9\nWevyYDTe7wZvmizK9N+QnJRh7213f6k279ObUKUiG3rwwHEIZzfmOY26TD/fQwyNPNw81+GR7pYN\n8ss659T0pEMhn0MRcdAr0GnL4I1+UAgUWAzMWqVEw/4sAW0cbwKel3pY5aGtggcWZfGMcsfwcabs\nw+ue80navY5keteDTMk+XXLGwXJzTd/2WBKOlVxdBDCAfkTttrgl/OtFiH1nOWgK4uCtUo3WG+lU\n6jtMv8LqVFJlWLYkofijVac7hsrk5+LtU418yLzRFOKdMMOJRqQTUSiF0kGZBBew5A62wDYxx7Ko\ny6XZIx+rSW3hLV1Ib2nSU4y9x27/xBo3HEU84ZszPfprXBd9/zcNjCyeo7HLKhk/L8OClp4eMYEt\nBnFis4v00n4oQZHymbXzJSc1jGeLgzwRtn9CiPN9BbQMVYNU8buzIuGyYLtu0i7SPOmHgu0ORYNP\nSQiKSua1U0NNoUBfEocQQ7P50MkaVptvhEYX2NpvG8FsH5NNqz3e0WWqosqJn2tg+SShw1bqdWH8\nU2NEpuLXnCro2LWH7ABg6iPuVu48/CdkQR5lVRMvbMPy1JQmtdIBNGHZua7z7snh+ahwoz872vb4\nDbGBeEX5Ypwi1Q+RqAbRW1FxCchoN4KmBVnm90et7KVmIQ7W+htZvruhQ2/atTeJ2UB5MveY+DqQ\nmyUgO27FJIO2Vu9W1jG3EZB/0O7pqWZEchPCXrFFz/DRkYsZ1aSfnD6XKN/mJ7g7mde1WacPf8Ru\nVnZXwQp3nQCdCcOn0WcuYJcYmgiCr4XPvvqM44BYO3vVVbsWtU1O/RjDxIyDSXd/yiy/uub2QQwD\nePOABdAkH67wc2yEPlr7mwIQyrmcw4iijWKDMtb79JEcE+ByVsh/UhiU7DUjcufaDcJb1EZAs9bl\nFoI8YHqf8HsgUFAFD3/Z2PGGWZ5Oy4knTEdDgq/6HzlWXwblO/gn5TrhNFatGYxdgDGgMBY35pHm\noPTaz/dn/B6fbZjldBlswtSevQXGwmE9mWOenPldnZye5TLkA7u3iB/Agtl4Sfi9IFayrxkSpfe3\nM2xbkAVcyos18/bBxM1MaLez1ySzDHI1Zdp50753amvW1oCagZrNTlhZynBDeNvjEGOeBR2uLdxS\neYSBw5A+mQ+KmO9XyUaTNfxt7YUrbJjCfLsLIyRV7hp4LT3vaOtI4k3CjWS/1oWvYIlI9ezD/xkg\nUnd4SRSyHnGww4IA29PlrjRUqUrK9I6q3qymNq2Iqwth1ZxFHOlU4VYWp/FkHSqFpFAFAKWxiiof\nat4I1dbVAhblKp2XP9z17nWQSGgODjQ6GRyURbbDG4JUDeaDOfZs3lVfagRTxv7Qc9Yi7bW08zOr\ndOV5TX/0IZQirQOACUdiW3tij34idDehRL02M+vNC3KUgfdKuA/Z3/8j6uuOh3cgKhkjiTHZUsVD\n7Qfyj+zCdSLotANkZds8k2lEavAYxgfK5i8zNYA2FwWCQsOFtOQqRzedS4/+7w0LZIinNPeliJQs\n4O+A+YwLCzKT+qQk5pe42Ut6qzJVrIGcw/WuE2THKLw32TCb+9i4bDlKzMN5ilLX+R4XFAZTnPms\ngJdIQhxvBqEJ0IBV+NaInJUyn3WUydqEl4Jl6kjoNbo9XgnjgNRiqzkXk+JJYNBKbGfvWBZ1WwS9\ncG4JKxam/IO9l69f7SOc44YNKBEh4khEWRWmzup6tD0st17M49JA0ii1C3irUm5IxcXA8iLSey59\nvqM1ROyDFlRAuo4NIEKtK1x1s1g6mBPu2leFgVSjStzfIqJcjgZR1R0glUi6pxybx0fxnDSWEOcw\nO7VIQhFoc5Yv7wTWXHKKLZrIdXiCgienW/Hy4qIi61iVSd59Dbv38m6aTBCuCUks+0DHh3YVzFxL\np4NTe7VK3y1bvnCS9tCzZ/aZa2MVg5/fW9GZZDT7xY1X8ptv6wikwC6vy/ifFBVCG0peHLBM2cl0\n8S5EZYfA7pWwdZoweWh3sd5F7TbpkX1vUzTbMkbNml//V8gCVyJ1HjSVvfnl5GQA0Z5/fQAb+GCd\nCCzfCnR7lCw/19l0Y64AmCZNRna4fnKgf+21thlt6s7shDZ/4qTFwLS6Y8VHb9qCLGSHIx0dA25A\nLTkV/a5INIkPsr39lV2Aa5ScFm5dYdX0HQ78tAreJS31Sdhj/OZAPSYhEHEAotNiChrlCIxdCums\nF3EisWUAqDDPNNUR3DN1s2Wr/aYLRUGFvhaA6JGIwYfOVbdPUFZ5CEhwjjpPI9EgPPKFBo1Qx2rV\nGBjAZfwS+/FS3b7FVEO0VW0JgsuJ9w8Wxn3ADnyr26mEfPG6Xo0xXtDCPQFx8Gk/wTVXY0SJTq/u\nkq3+UarnNCfHKE5ha3FoNgGaHOtRk0HT4+xUm6wcoT0cUDG/qFVWp3VxW2hSJrw2HWTcgtxp1tWM\ndvMAklazog1kaJGLIStm2lNgFUPZwP4kwt8kXFI0iJEgYZR98YxdWz5iLqkRZiUDA8AfrwXC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AQy+t0tSPwawTjsQNVFsA98CNzwUPNwx/I7J0NRZQLo+MHb8ItoQZ8POfucU5W/k1uU7LdAEnD\nCph0hs080+H0F9s/W91laK2uFdotdQuLdaUkxNAgBgilBnPQcBfyBZyDMHMSf8aARHu/9iiWr8fZ\nZ7lYymhxCwV4AdBhS2HvvxPMVMu+12aQU7+q0en6jRc1BDEycBYUDwEPc2IeTZxHR8Gc9VoyjX1A\nfNG/kRdIYz1a1gWm8uljnstWpctG23Ceyx9IJLV3XL9A7e5vTdav/Ki8qpm/002QTiLmfBfxfbTV\nxD4cKpVumboXjUfIey4xgDmuQyAA0VuZptNVxFy6QYVWim+aJIlynWL4x3Rm2Tju15gPwSI0lI3x\nqI6npd9yPlFBbgagTJUrdRnKgiw/JqzxVs0Cyu4YW89cwDrp6ZsQgndasySETQAhqJ5vOvWP31oO\n9cguTo7Oe26ep7HPH0Q6CfTCqDbGbLDNfEVejJnQMh+iSD5eADd5CXI54FDsBDCLQlwpxLLdKVat\nTV8YSmIm/ygOCquy8l3+LcsYJYV8laABwRfD1tg6gCPxszLlvfOPEP4r4kaxRRX0MKVfeFhiorZ2\nPRBdiQYS70VHTO+Pcr0qD2gPu3a48Zye4LxyJXNC+19RXQ/7i+rw9SF2wfO7Q0WO0s2uwqUduIxW\nUDyVj4R6WSL9IUFoKRP0t9RyRxekfqI/sAOlIx+TmEnhqFxsObxztMSx9wQyVPH7qJBgv697rRPG\n+ooVq+tEFV4P+yYIUHdyGgOMW48cBEg2ZX3Z0oB3aaN3G9flvIFwuJ151PFqkaK10Xkr/ZPJeATS\nUagNembQwMdoFHg3357unGpBDT/Dgu625boC2b/KzUHwSZvmgusjneN4yjLRNJpMLVrCt1MbOpML\ncxLW9BEqK+vGp35GeVwB9FX337e+UThyEDNp3icrA1PoJemcznPMrf/BS+c1ujFIoG1TlnITYPUY\nzyimlJ77wQFboXScEx5hMDcLkVjahyNJNlWE/rnZ/Heqcn/JtQAAj0Q5X+1xLNf60z5OyGPFAJwv\n2EOd9amykAKWviAQURvoMRGEBXjdNn3Ph3a2BRZWO+1Vxht0E0yOf+ayOvDpTwk6gPCXBnts7ZAe\n2Rxl9cx3fTV7rvfB2RbkZqllYlNlj1ZwI/D6c4PMS+x9LU3t6aA2RJ52G9MRpbMPNbCKT0qiNyDl\nF6m7P0+aolIz8163r85rDUDZHf1J62FBJPwLmgNpsTI32qU1z6FRVIhAc9n+vPwz9PDBw4+VVJxZ\n0o6jRT3GFKHv94z8RHdHtxXjr7VgR89abcREBbg13CgunjF4yfDbgPOn1dPctcdGSYzO3eIxpbT6\nxosMa19ZNra+1t2oFQ/dgkao/UEAaCC4d/8g0Qv7UU3CSBs4a+9gSY4y5A4ag9nGPuGo+re+6rsV\n3zDLr5JN4Y5rh1dTSkMUDrIRbvSAbRndH6LCYnPdJ5O/3aYxdwEgOfoeLSzoPTLUCVriXllAunuP\nzrOXJmsdOAZxiGK85qphrVgC9oZbOGOCRNlNc3kwZOW+kIfOUXJI1q+pFOr4F7dq2vckRwsRHAJW\nqoSwMzkrkcYTUqsniyp2vRk5vE95SklXmddxUBdsyZYjTaYUGtmshxk7tfsghV4Urc+EvYme1GUB\njkiGEUIt0oH4oi6hn3f8tjQU/rSfl/JCEWbg0oIdzr+mLhDEmHt91TgkXSJrYDKYvMBx7uYjjowQ\nSk9Y/cnQ32w0siX1PmXiOe1FK1TduGubeMiGY0dt0SmikG8oGsobhspRVGVO4I9z0u+nwKOMCOor\nZCwbzqVsGzKvFwK0zLnSznffmMWmX7LxFfZCppirA+gMW+qgq0K/BuNT4WZjh+m3waJ4jjxnkYqB\nxcwm/Ycu0YQzB1C70gK3b18iXrLLCHz/O38WDfTMsl9uIsfjW1kQyR83NXUxLnEgGYU2mZE4cXVM\ncfjxfQFwcuHiWwHqBQUcIDThisC8zRMY1gX3eFAtEoWt7G/U4StnzI2imypkrRchjChgJFds+ICN\nxW6Tw5H+fdhqh3pOsUOWjT8h04oaSPPi1jY4dkeSGym0REhlaAqX9dHXeHR6yNMR3DmxnTFpVa+z\nfQMVr6S23rkOG4U6/ikUeZPYkMKvRZMmLXhoGgV2HqLbVmGqVd8pP8UQsvRUsla2G16dgnIfSZ+V\nM/K//E250DPOx8aY7vQozoLNyPAPWQYEvm9Z9KVFMKL4ezFIbiH6hSoXrEJlZdxQvjmu5HCJMEV7\nvxxonhte6KXRn5OhPROxsAlnKCAJQG9p6XfseK76kLSvlbt6hfPNuEEtbkl2jyc1eDdlBFzsTklT\nSSgAau5J5efeMB30+2wkNvMtd8367SGJHUaDVYu1uY+RFOukjyaBZ+QFctWoJg/2+7NW4Z1tnqzX\n+VKDJOthMdFfrvCWhZ35D0wu6aiA0s+Pv22C+6GqMyJZrhsYqJl5YP7lJFK/XMe8qTz+0yXtIVlQ\naq6bsyOe8Y2WiTEb1DCEIafiFlMN/k4c1gpzX0sNhlQyzBHP380aEPiW9Tc80i9ar608ZeMtO3y2\n3yzSuhWmUfBo4IOefv3ETFbACspXtWwIjae5ZcI7etY5ZHZBvboCXadBelGOiio08BJMeXXN/7Mn\nTpip7T9jHSqmhq3mih3V8XpsDaz/kYb6gznaO2go69sjm8xgWAvz9oVCG3HOJAGKbYvLYEcDXdBq\nHDni9Vm5j/SIeaeZo8MiiqvEshTiDfodsNaxXLUG2l2UgExTAx0D22F3s4zXU+xphIzE8lrgiCFB\n+9+xYBrI6WWgpbafD3HSyikd7EorRSkuLUSQGGToOVyZ15ipksEkVq7IeJDlY4uHaIzviQ7tBJxt\nQOtmqwONvfVIwYdHovYcOKEx0yrK7KnJXCJqS/b2ThrBiM1hVxPtK9d9g8JoIUYswu/trp45UpVS\nOSjN0npL50ayZ7iJkZRDX6cfbby2SsjyWQN/iRgFnJG/ugVgEfU8rY/iWW0FJva7DZrihXhxP2er\n+MI5s3MuYalDWXceMycjleogCgUA/UvgntTI6KOCvXsDfCfUpsytxe+S2p54/yMofiCIvwfttNkQ\njrGtb9pn93VmW/sIBKbyJO3jS/2Foh1Tdig6cxWqWTyQf60lAS4MDzVqZr75UmOggr9R4IbYqqwK\nJwlOpoJM9NYDpx/QKwMV5eyf4KiK9agHa8qgMdMtodXoStubIEU0+nklP/ewm1n58p9YZUyXfxHg\n6iX3SJH9cXfUcnxVPL2DfBSe55qlzVWjcdBK3/CFAJmfeTmU2o9kEPrQVRG10hboCkdlx4p0d5W4\ncxF0w/IIOTjsDcwhNRs/+NCDlGm1ioAF2gCBJngAc6hVKeYEJ4RF4ZgqQfAhfu4h2L0my9wKReBa\nWW2lSb94VIdaWVhebuGSV8vDgGFCmzUX6FrFVceu/+hk0Bix20g9CaXCx6iktfBAOKrpLG2AmtzR\nmzxXTJQwW0a2ouvzQ6jwGHX885ot66Kcve+CrpD8epv43jlic/gfq1u8MEJfuecCuQHOh5dCnZJP\nsQKiJ+VsCDYmu3gWnI4pM656e5t/4zZVOM1MbQs6IGHz2NkDf1ugMsniUeBtwMGOSkyPgCG32WzO\nXf8FT9F20hM0zOaERkw81fQRCkFyB6k9S0YeGJXujeJrSy61oRHk92vcIkX37cUa1k2jTIMkk9vA\n5th8+4NRa67w9pLmi1kc7/TvC923bIEP/EcsYDKKmRTzI+9dkabptkZD74hONGgyZwHKkizwqjMa\ndSjFBoOgRP2MWNcIZqpg/JZk+i6JOZ1p69Jv7gZhD8VSBds1GQm4gjIZ2+/KKARpT0EUoDuUicSX\nHpdRFYZNC1tpzo2l8WIapFd/R0+VCY87ISV6ctQDtsvDe8HtPFUIqq1M2qyVmvEadQuUD4aYnOYz\n2+li3ldFYexO0IL3LXRtU1cuZQ9HboQBYglwDCMY4R34vbPswbKr4ghRW/BKZpUpFBHjKnJOuqs0\n7ziBmZwx5hKMqk3yy1bjmcCmCJFnj+auI079FkWoOGCtVhcqaeSXeM0yz8mi9EdHArwdiFXaAYht\nmuhrmCPuhWwawQJ9pXt/r0p/DKH/iQv8NuYOOpsWv1trIMKA+IBPvki+Pf/RaaK4gV3joKagwSC0\nMlow7jhuQ/ggFLxp4hdXw2kATxUgGe8BP3Dw/r2xudc2HjNl1xmuq1Jmf9yk/JeS3mQbY7rO25Eb\nvIMgcs78s9cuODAbDadyk1S7bIvGPt9k35TfDCbTErIziTDt2prwsS65L0votmpgXICRrWN2hEio\nbPrfga9GoA33qBhTWJ6O6qaL6CqZnDqO2u+FGcU5XFhTU9IE3dhkwsXFU5PFmj/YRZsvhLxDtEoB\nlkzOfshJ7EX89xyMrIVu6Q/orTDhRHM4AEBAHioNHImCCGiVZTAlCZn5HW/DhsSp+TJb83hW5QFB\nCFwombJSx1SG0/d3DDQ42BXpdn/Ig8dlakuyUdoj7mDPtzMVFHi/EWUtdzdj9f8vJ+ClMrMjs3Nt\nri5ApbKlzYlK+GcZshMep/h31QGCHb8fg5kbnuZyMHrdHdvj6YHEHwqtj/5D9Dp9DoDb7RU03Tbh\nTskL0t3E5IlfxdJoQ/CVdHzVFTM00ass9KckU9QKeqUX+WKgibE6Wpdzi96FwrZ3q8IrCSGtX1ce\na4NbEAxyBD8318vwfBeAAkKzwsh08U9Bg9SLau3jNa85mTgmErHkQsQfbEhWxBShsSbLazSbR9gV\nmv8JGm3EDyn3DeQ/SvorGxZDstyMwSrlkktNzz8YyMQPZEtNXSLXdF/twtfk9c4me9FFSbgS/r+7\nvdUCJwYJppEPtTv5h2xFA1wsm5D269JY3XFhTBUwwHTLNNYDBOErq36IScblsKmXmDc77/RGVmmP\n+uFBKS6mGdr9HtP/kBd/tsMUJcw6r23J7yyVXqYReConU3lTzImruPkKdGqQxLnILWGJe6QDC97x\nz7laParySFSZ2iAKh0sxhLcZig8FX5Lf8RaewsHMQu9UGrY9xmAFnP7VGLgvwbu95MUVhG8C4y56\nKvAHAlu2d79aqwuBZPhLrzhTSBHh7PUwhWRSu819KwkdTmjKI5mmdpSuOYdsRoihM65imFE+Q52+\nSKXgTVAyx5dDtofKf6rmuz90FDmXsRGSXWAYHk7NTEWh+GDJcG+bhzBmUroTtuUfSTD4VPHtyO6a\nKdVGKZF7txdfEye+Wgajo7WI9yNvvDmjNyu5S5MR2oMCJ6xcGCZzHseDHdMh+YrDDrPIuAlLD0ZY\nMIHiDnqhUFC0kNVMKmRwpxICmJ2xt4dxUSOWadUXuirJjXYVy4eY3XyGbucWjnMcLUZqQK7b6Fgs\nCpTFeJfSIs51829nQoQahrSxfR80tIefYTGsONbpny+WKomfp+7wX+d27aEZBzOLoy5IjdA3U53U\nG+4Boin239WchSxzIg+nYUZMhPyMaP6JgTqt6VnpA0GerICEQQ26q8MAXJjMns9fir4RdrDFzvWf\n77/W32yusbzKS8RU5jGcI0h51Y2wXR8I7nfx4pOt2zr8P1YFstrVVbRRBtUFKn0bnoE8Ki6tzA21\nl0r1AiBhudIBW2N5dj9xUKkV0k97T1UaGWReA3z4FxkXT6G7KouFr0VGWu7XzLsgkNKFHPMj9l4y\nVAlr80TZ5FncdCsdDPZQtLiPsfETZzaqNvNMihQP1J8KhjxnOJibr5AlzG1leoZu0B+OFkWMx2BZ\n0BV/XMG7oSuPb7SP/dwMS606uDI14Rfn+ADA98LXI6B+jZFje0JZx/1NTRWhcgBPoNhwndEks5st\nh8ByMM1HPfll5XsVPoSTJeX2l0GXZNUSS09mJLKG9h6fSAbNisYV99dLufd2LIuSTKNnPmOnZa0R\nIZrBYipntotH9qDBaZ3sPZ32WG3JakHo/UBuTawuvsiL5SUDK2PkeMrhUGxOk1yxbD6gMgaI4RlZ\nyON0ksB19DxXA7dXrZhp88GHXDMR9T7+B83wpQ6MHQAQvh7oLCWxV9RScVU2v04O6x7QSKHhd7bz\ngKoR00XtiYLGA4stabwarPHa0nk+h863kcgpdFZh5PImw+bRyvXsVo3xwlKnSta44acnP9ierP0O\n2fFyAJ9633jBw/CrN2PZz9MoaKaMsH37ZZ84GR1QJwutqaOHu7nqYeoctWAYvwhKP1a5K1mw1z7i\n3oqNiyNhwcI2tQ2x2TRJAOlqxag6QfSLbCz+PdFQ3VwNaSgvJTVTPljYgzs2+JaQlfJeUEndZo9V\n0J/nY1awBcywx1vSXd2DqbTEA/FiG7rfDmu4PnWg8FWLHotJqIzR03Hi6SexImNEm4fswaitdlhU\n5LrAStYZT/6QI09QqvGoJEhNuInpAuCBBAGqlZhObn9dZpPywdJaLtNDIpc3Dnm/nWPO7mRI5J1h\n3q+VH2v1CAJf4m90vgvgRjXNlFHW+TIWY/ebl8YSOSN0dc8Xz4TDJFiSM8MFY1N/RTdyDeUE1LuQ\nqXZp7TKvhe4dJRtB8/p3EJI6gPNwhO8XtYg2U7iysK08Fv3p8YtW7sRKa37rysh8EOuUMR4N2W3S\nCEqiGh5lo4wkZhmf4lbIHRm/Yv/QMcRA09IjLhictuY8cmYUmDZZCLkJkDtFU5Sj68dU7Eg0Y6KK\n71TfofCtocSXXRxyUtyPU0akizOjWCBRHCLWUz8VSAXilJNUeQjski7wXVlDeLrTVAP6ZI67w4FA\nH6wQDIl/2GWcj25a75BDV7m14HqBgPzrqIANXKPwbXGqDgwbtMXcZylFlsP65fva/WPQXLFBzuTd\n1MSyeGwGAxyUNxgoT6Ncp14gfdU/jMsWFsYC62TixZKg3+4mm/3AlO+DofXvIy713bZnbG1735Px\nc4EH5D/60JmzdbeEALpWB0Egs75jjdNDL0xtYhUySMyUy1JuWVOA2tmSFqX3SL66cDLgqK+ogobe\nNIWCbCg2zOJwPtHhTrO7kyxg5MdyB5s2vv8AMS4HzlV6H9onpgIoYnUGaSwS0TquZI30YWJgd58/\nfiSqrZ219yhmkmF7kEn4bJLAks9XpQHKQBz6qNY1tOgs5/fuk2AC8UDbYZGp4bNQaaQZ/MyvA/Lf\nDJ25C8JpcARUGZgZNukFxAsNGpvKx5RiIgC1jVE99ttvH7gRuDleiwryOyz4LoAz1ktDrkHFiWNK\nBmWI09qyUyE5iFg9jUqMCG232eZ9TFUcMdYAwTwnBDT03NTV4yMiPscMrQzPxEiE84G3eyj6Pqam\nGRr1+2LOhKc1PwLeuISyuPyWBKEN8vnhTvA20REPe12U9kEdb00ILX9IyuyeMVhBjqn+kanquhKq\nB5jHScUqi9b/L3bvAjTbj2pchp537BffNUKKKZqhemMzGgsk125h5Z+w5mNimy1LTp/J6LgSPZK0\nniuX3uEZvjzmZTYZo+NTcoZjTtAubskbet53TltsueDyS8XzA8FXdF3s5i7Iy0bq1PbuEMk3YJUY\n88g5kZenx1hqSKq+Qf/7n6LyZ7zCep2lIs7BgtMtU8b8i4x7Ndy+hOLDNLtvJGq2LtLcwKPue3tR\nvm8BkRZR/zDn6i0KFHcVQP4/EBq6lTCYcj78/HoM/VJBgx5r0sjnOxi/BK7erUcQ+xcloU6AodRk\nBu7VWiMbTINtIM2Or35mo20K2ZJGKtxUl7HHf7i2SQu1AlNxi55P4TN+72NWTbW9w9EVBU60GyY5\n5pMQolJm0J03KlPSVuzZjLdRuIE5MubYYTZikpVYsGuRkixhqU8rB6RYODviYfIUHFHMWZbfeSZv\n4cC1//vlPdnS4T5+5pzmK5aEQm6TQsexeFiZd+DB3mqEIhchHA5KQLtHGcehEdrcKsEvmbIHBgf4\n3iVwC/zXtdzt+Hv+aehjIXYM3UpdOfOE6chD2L40KwjCys+D5KHMGqG3Z5g9bJb+iYC+XqqXQtBe\ncC08tqBVxdQKtAB1gLpsiLYXeLhM5GLBl8+mVDmlaY6j5rXXSuPeiAKUMEHiA48N4mO1ztv9TxGC\nOqk4XfZ0yCAEROEZVE8knTdxflLuu9IbOpDxtd50m9LZVIe6KroWApM207SNULj33anCrTHc9oPd\nf/Qhzwm3BWrc3CqWzKh5j910nxwooBXxBILx9zHNQGMWw0wvTgjMINsOm1/SK9yeEh4FtXpjcb8I\nbk3qouSX2o1+uT0MRPBIvZUXWeelSks1/nNkQKYn7Xooe9U7tCpDbHFpXQRSq2XZ5iHPhb25REKK\nwxaeB/jT8Y1ylULf4q+qaHPkVY59I3wLVcZTHdP/Htgm0IwCgLlxD7ryKcKl2SdT6MCwZhuAwE3M\nKBchbKcRwcZanQFaQLkdBR8aPTWLmSfWhQZSZ+Xjf84EnAYqDCkDWHxXE5XCvzRNxjaWJqEQkwL3\n7w9zTAlBHANZzD061iNPKZNwG/hsyRNRwpP8P6Hm4NT1gQkB8ndYJfIVCEhLZwgA08iCgObJojSA\nn0aJ4DhrKtloxogJ9QoH8NDjQBMXFYuQAlgTaoV6TjXp9q4N+ZffWdXKPrwprDmAP2doVneiPieP\njxMPGpFXQU+BnSE6A/nHaQrYM0X8b3yyMNcp72ukcQHp71cyXONhSr2GJwr7GN78HJOHrQoBKctf\nxTgKH19iyVNvMif/max1xKh5NiJKeVuESiuXTVv9MyrpPHdchWQau8IQg7Mzs+VR+qGg5Aff3qJG\ntYvXWv16oGjTDWIa0DXXX54Niq5JPOf32fY/CHF4NMTLygH0jBDsNLkSm75buLXilUNmM1Xhm/kP\naitnhnyTuqme9j2iKVi6qbMyeaCoixmRJTVWVowslRKozr/ZGiCFn2gNt+X14Q1TxSLOtNWB5WOd\nwek3rd4dpvS50fzxMLiUvvtkWPHJnrxIBak43OfymhnLNf5FVdQYAcCiADat7X4/nZ4tecD7edO1\nkUaY3qWDPkz4PEb97CnI8KDBKGriCXmiQTGgqegGI5lZqAV/cwdADC7DpJyOvpTgxPHRmiVZEg4k\nz/66HMAimaRo1lEfNFyMbgXNwnK+4dsMdDDJBD9yR7nx5+YsoWYfA4crM/PFUdlRHvIMRHRdC286\nrxNnyiUajcdLXICOpeRUxTcGYca7PDMYZfH2/lGF5MrRcj8uP9I3o85r7c69cSDjybTFST7KMkkA\nieZUITXkY/zeFwM6bH7i9aeewV/FHHsd3tAK+2ovfurjHcLd8BqywqRkEchDM5X5y0IdUzgF0pw0\nlLLH3Y96A0nbCB7VgFE5L73UGSe+7w41sNSmc4au6YgDqvSe6dUucerLq+51cZzgK88T5Ihpg9oD\nhzcBvA6AyKp0zrbV/wWjTbCusymwLnu0EYvDRyu3se4VAqXkSI2upSMc2nYHuNBVI7nL6mvCeEmm\nbxs/QRkW3Mk7Yf7B0NMjlFxfZHsfbJudOjR1pX7YxWn7rfavOH7DzcGJR9lNmlWM+mt6Z9Ms4QrA\nBkjFKGtLOMVSWpr6P6RRZ+aa4CZOYDMnHHf8v9t30wj3sAwRpuDHNmPbIGiwM42zDSt4reD4RVYf\nIBR0c3o+2AuY6m5WfxNhdvwsFsr2pnVExFUODnrcM+kfmI1GMjnaD+vjcIqGIjoqAihIO6AiM4cr\nqshoDo5pqC4uNEjJZgv0p0w6I4j+B0pn4RorZlVVLnObSlqgnMbCD/691FphKbTRo0mcdniEYRs4\nmQ7/gSH5agAiKROrJkhyKmQ71cK8DlgLz+cIsU668l8um2SmDh5KTuQQLbFOqeP9OsAlii4j3MZD\ngOoxmzgn/ETkx4AJ4qwFpv5szQYfOIfcMyHqbSwtxlkSo93BOdt4t2q7iK4FoxmWyM8MJ0iCwHaZ\n4dskY01PenoDwsRTYf/gVO2tQHTpv9axCz7aRTzTR7HU0L+VAKU8FoAe+V197B8f1pDVFIywHB2x\nzCh3vlPYShnQiJa60jajKqMo7r2wfViqkkFG5rTkCXVmTDhyVP5bUNb2qKXxD4uGiGnoevC0q0v+\ndMhWhCfawsekWdKN2ErYCK9lyKFPkmakLya5+YUnY6EeuEEdC9zbltWgkLuSuOPbq5xgnkC+wdDe\ndVnicTqipmFo+jJIULnskkbt9a91713OLBy+V4yua4igoX9hh2W3bGangL6tfrC4jiC++4mfMXXN\nCmB281CflQIt0T8kjhbVPSuv9GS2MsQBSprVuRmPVYXMzXcDJWABf7AgeqsVg6jzWxyjVsVcVaJ9\neUxA0KGkDo0VFO7gXSEHm9qKEF7ONUNtH8xNQQxrKqIu9pbBYbO8Da9alyESqSULWpKStfRpl8Bs\nrId6LaayZbNuTO4CSrAVRoNj+MMoDIR8DQI25h6JR1oYGW5ZXbgZhmOK1T8gyWKhxBpWFxSU1IqQ\nMokLtkzO7EXdR/dNvS6e9doFkRN6KN9QBM5+reK4VypMZtlA60ncqMHGK+EjDTv8qaAsrtPnTNqf\nGnvBAXSpznDLgcohbLgxECquzOJzhRTMOGjziFYvysHK3PrNZxR7qzl5GMbKRztAYs72XMzPld7P\nEFytvoEr2gyDfPcpGRSjoEk7WjHpTV3mNsah7c9RQ3+RP3QhpFqqCpy6DYhwi0YlvQOnZdRs7DYv\n/WdyDtEN8lh5+CQsqL0jpC1H1inXesVyEY2mLszvLXJQdzo7B9rgIJHXUHGGjgo14zSUgPmgINH/\nXAivwj0K4JKNV8xJo0rzTZ2nEcGVsrZYXpNOklfhSGS886I0jdd20H4STrvCjPPj+4uv4MUjsUjF\nBu681KCFFe3KmRZ2WsBwUKQ7ZutZbqODJVVKemufD6Gbd2DF4q6pTTv/JdPuVICPryRXYuGkXk18\nEDSLN7zYBXKLIbavkWDZDA7auxUcrLrvy/bntRuTHZegeHuWyhJ47g3m56n0IrPukw/aNt1uUOns\nWQ+0oCZjx1I0IyDk5CeHTRQ8hKTaKgjYlbant9UVlTIYvB6RQfhmq653bcKFHJ/J3lTgYhpusxrP\nxS6+pogrFcnYbDoCN6tCin/zvs5ivBX/z5/F+Kq/A0GpXcFJpr8xtDyfL3LE7NeDqTyGpvpKLFnw\nz3wOwE1qPWufhfCnupnUUyEnhOjKuMDTvEV1LU+0s7huAj9asy645T1q3493gigxKaIv2dt0g7/f\nX0FIzQXsfUSPOwe0dXmTJXt2o0t4b9CLNIHhXIAW5axrTvnraIqJpVaMliO+tCd49pJPmWFYZF2Z\nOecR0lovzE8enbA4M3PWjo9jXk7xPGiVbEXbMVFXbebzgD8LYfs6FQSKeuG6Fv7SX0DFkEEFTRh+\nY+8i4OJw+NkkM0sF1EZeGNWteoZkbL9my/6IDRE90Z5xBUjI3LGt6r655F/mijBYa3PQS/lFlknY\nNVvSoQ6iyEbjDBFtBlChrkQwKgyxp/DcpPijuWQI4v3RI5bZQNW2+v08Jc6kXaDFeZ0q1mrE467R\nTovUkmMY8jYvKB4LCDIKxQ9LF+AN46zfOz/BAMl2tL0/vRZVTVuRr58HWwUKfwJI++uYBloat7Ms\nV836BZU8Pg20FOZoG0I23kLm7rpl8quOhRZhxdDeCzikQnqdmT42+FbqrTK7Epfv0Z3ye6cUQlpG\nNB5cRyxfe9DoVhUoAUXwUbEfuYCXWVkv4vV1zdUIETjBjugrlrYK5ECq0bDGVy3g0qlxH4jVJ6Wm\nW2Ha96a/SI8n2BG6y61hQfFCQWiZL9tbOjWewJy3PB9A6Bt7lzSK7bGzYxxyLpSM3UtU+ezU/ArW\nGNjCcWFCvzIjRteKNf/0I4ix9dGwT6NjqstXxLj2WCNfHHccNcYcltUY3J5B6ChamFD5h71c+7ZT\nKbSVJgdYV2NsL8uBbKgotAvX+Jd4dB/4IhxsG+xpjtoBax+3kgVvMMibiB6LwemQSUCTOjlkLlr4\nNdHQIXDlIbOL7KSK9IPWg3mhUEL/VFDPjCf1L5lP1RmQCTUtyYwl2ACn+q959k94NX3QV+428NBb\nDNLFaaa6PhoasoI7HbOf7xfaY3F+NX7bYos20K9RPo5ObyfCwoQCMG8kg2U6DKerHgMY2zNsiw4W\nRZjV0vjV10UiMeafOrKFPemnsHN0TA6ld5xkAyvZOnrrCa1EMo60Gkt6+fQlaBxY7JRANFMYFAwj\nXpqQY8GM6j39UobaNiRW5bg/51Bdqvl+niJFiAjaljUM8uJE96GJy5CBlLr1nkrh/h1LKWv+5HEG\nwesRLsW9MVouJMRJJgYX239bC2lGGbupYAUi+QuLfU/79VcGkkJdBO/YT9eNX4gf+EX5XuO02eZS\nnp16XW+9drG1kD8vPyNqlXFu4evUvVUyiTJqn2IgAI43KtrKEuFB6Q0CEQSqJQtD9WUQLhncJdbS\nSffNaF3UAIcgw2nYTCi/fzkDjEYBxRlCjz8nRQvryhz99KDEQD7xdx+GVEezCnruOMut/ybTIfHF\nCzFnfxAx4bRHq+Q8ntV9P60tt7BhLzub/73+C1VxxUu7b71MfJL1glz6d/NcmfuTcLPNTk2XtXEP\nc/kfujZUwr/FYNMiIesIEfav7oKYn9b3gvNK5MnXYlMe9FcgnZFvV6cdQbNtLnUWDvBCBGDK+nVK\n7ktcIvFLFg/d3iusAbUXSEPplcTrH6qUv3IxfxEY+W6MUCbWNbchh0CRVneVie0P9mBDafW/aBOm\nXIYPNNSaRw+FFAzSH5C4fb65O7vJDiR/Mu4In7FXCkKDGNnz9IUEXnYrDpYtvF5uIJ1Z2OtSLwTG\n0HlfRphov6wohav7X6V3F0KeKsv/FvOwds+UWo9Xj7U0GSvIB+4wburX0YGgyL0upmxTj5J8VJ8z\nelkdMHY6DTN3Ei8OAuYySco0W2kewObHOTiEciEcwlL0whlShH6JzRQ2v+ZgW7w04ZmZPXXwUFCt\n76O7Saoq1BpNA5blkB/7hR3uHApFRQ5OxoOnBBXAix6DDfCAhZdjJtdWGAgfiM9zqaaNKV03vO8i\nUEo8NO8dDObrvWtGU920Z5SfbW/dyh8GtBwFboqQO23Nx07/MWCE+qEU0dPwhBzrv9x6jXg3Y3Sl\n+tAYw4K82E9z7TmFw8mUCrIZdmZHtZ57+B2sWgszBRwt3QhYZhoHU/yRdJgiv4VFflkgGCbs+PDP\npb33bO7AiXhoZ1ors1f8rcNvhs0zIfSiXq+03gYkXbeaftIXB4qc7ILwvheXMUMtaOUB+BXlXqbc\nhFRDC8l2tW9YMF6O2biE/a6AP/rIF5tn6ih6KBlhyvXHa96g7tKEqDB41dhXlFbeX1F8gnPgq/L5\nUXDuRWfmSWIuHi1r5EByIXw1XTYs+bj+cmDmcJoMI0r3rINZk6Wx/vjcdeIXio0LctWMzgnsCa9t\n1zmPqJixSylr4AhsK5ne+wrw2SBIsBSKMawPPp3HrEPGqdPSqINWyH1AuAt4qNfYANmUQQ0h1Uvl\nnX9lYDCxVcBKD4r9BQTH5cewZyvYYYaasT2WIV+J+kcbPAGpoauRNZNMaTMjDJ9Ibwp21V29NoZ+\ngZ3N7b8dvhILWzMZdYQ9r4guDe6wgQ2Y9b1s/t+fsHus/tx/4PrhJyHQ9FJ9XJg1O2mVNk7Y1Lh0\nA+WqpR3ptvx/r8NQP/IJin+Id2v1iTYqCR2HTey7jAfdEr8NoYBxEws0WvTvlv2wvLc6OOtGy0fL\n+zkA48fePjwtC3XNlrZsgks7yCHUQo2AQtPIM+BERlDEY5q4f01JIJCCn/6gJ5FOd8fTJhyzFBLj\njN9G1x9bMz0CdnaOXvlCCTVcgQz64j0sHK+40pcYEg9xO7hNR9mVMEJ0+++A8urwOT8M1r8pv6If\n00pTqRl7t8vmmNmsqTUwEEJTAhtq90+ObU76xnHJF1lghA0FrJ5Ntws09kZcH+ykIgsw8ucNl+KC\n+FoeyyJSqsX4OOvQYILvoVWtZ4I6sZv9O2ZFs0gdDyos0kaUVpGr40tDQS5VX9A66XdTutu0uFVu\nlUNZeFQXg8KSPGmayBCv9df52HCj4v2LeFkGsXdUj+pbmTgGQuJz0KuEJiEylGNwBNO4isDmFmwE\ncMNWcAWfymPChT5f9Bnzng2deP6kRoATIiwGmDztD4weCpWN3V2vLjFfiLDK3oUlC8mDYOSUslHH\nwOdUg5bGv4Lj6aHXGctJEjUMcolj1tTUh2+xePFogUQH566DFvmQHWMGyruI2z3PUNtyz/9mV0cx\ncFMyErPXL48vuDvgL7+MMwA3hYmZCL+psrywmFa87DXYWnGukyRZjtCscLti5r6clsPnl2OAWUSG\nrpx13E1H76q8ZBbl0IcX2CkU4a73MLAsAmntNUshng1kjAKkjk6kZDvY4rCqjNYC3lyWMHkdPgho\neYWN2nqi1I3gd0r9KjbWwz6UkL9mFr7mskhUMECktQXT5rcuEKBz/+fTyIScrT1Cck+YMq5vhfJx\ngvcKE2WJvo4DBXp0VzHEqrmsC+raUb3f0l2h7Bo9dgIQ5zEB/YA+4QbDVdx1Q+fEEA9p2482O5Ip\n6nBN2qAnodRZJx99RncyJ/yuAymzwRe8njpZ+SxDtCDSHeXg4qX4s9Ee5zBDQIwzKwUe44kN86I8\nq9mIpgvg1rF6aoQQwmKeHvdFo2C8J7e9SupywQpv6EnjKhEHsOWaeYUk/f+sMTwZBvEYqoMvUTlu\nhd+MujHJMc2BpWQSJOHmxx3pQGAtA4CTqYXgisk60lzWmDtuxRjREUhMlf++9FFDBRqPPc2JRlFd\nbA8x9iOJZITOf9t44nzC5styqwnCHZC9d+67VKPhZHoEqjTiWtndI/4lvVGMjAChA5DXaQxgUmx+\nC8GB/Yr3//9Ab784KcTLFCFgS6fGVUEF+kdJ36TLZCCZCP9b6dB1VtQLSbfhWli5hvBsdkkpnAIl\n19tdbd5igdKgwvXqyS+c9veM//EGdmxp3KVNhRe9vOmwk5CgjGyxJ0ah10HCXhpseQsRayf58jX4\nmlb/M+hJQcge2+/Zb32ZO4HuH9QCwmN2q2rszTtjBUG3cu9N2lWF54eI1yustuwvSG3/sXM6nX1C\ndVmpvDd+AwMBztDqeSVpRMgpVwtTChe3SjPOPonVaxoVUfNGaBKqz5wzVjRFbEu/tHqypVHx4V+o\n5i3mXCTgiHkPDMqQrk+o3qSBxu+BUvyoXg4yyFJcTLw2oS29J+dud/NmK4PFsVLP/XgojggwoCMe\nROcLkYkU/n+4csqQFRCvMs68+b1EveH45uwaqmpP67PEriPTVyG3ljD0iqG43gXrvymGOENqmAla\nvD7Pf7Ilj2J9Xgg731b9QYgGeXf860iyFvRxj25qr4PoIBbdQ/Bv2vfFN4pYnIVC8z6gDYbub5UG\n4UDCw8ZoDngqXhLKlGWYfLc8Jtah24Dhby+o5sDWHU17tGUAso+yUwvNlY0kLtbreVsRs4iRc1fQ\nJGaJAsH7cbyPxrVgBFKLfthtPtiiHPu7WqT4MjfAw4K+6jK6liHRLwpAYgrzrkf9GQoor7hYQI1R\nr+tO4aWSkf3m2+miCcei/hWqHuzI47PeRFLqRb+yw7oBP6VC/jgSIxWoD4Cqyu2NfJfHnzEg8PgQ\n1Cnppj9IOHhh4wCWtgS4bBWNBUhEvuQIbZSmFIAylxB+xHSOpJECPYUogEh+So3pZBidrPuTxVno\nboK+Ti0W9XPW956kxK9Okt+/A6SWsePaQr20Nflr8f3LNYYpn1iXDo9/UACq0u10BOW6FbsCN4zh\n44aaL+lAkb9geE2ATMvyYPN1QVekUs3S9aj0U5dHMppWCYmjCPDwK/eFywXUDODvnJskVR0mmIGQ\ntQI2FNL9PP6EvAbGNMxdpDNH2l1DDokD/jYYmN9UohfJVXRnjuwZxEs1lhJcwp+JdwmglsRyyd0o\ng1mPxbAILUeWb1pZ0wacm3PumBqXUExtD+WD60gY2or/0cXhfcv5VIE3pxtf5SY3W6FSSS40t8lB\nUCeWjoU11fBBKtCce9S9C6uM/ZM2CDcTVXU3iYzrklOkep8p0umyfGqpnm4YolsRbJhLndU9IuQ3\nvc9iDK+wjXQ5KXixLXQIgPsO7oBGqmj1VqkgU4Bb4ubpHLFrYx12VJCW7xyIdvSbZ5ds74zhH0uy\nyVL+CY6O9PNM0jWJtKaR6y4bPf13Af6Fs2A0XrSz2bVcPgUYwJu0zJ8uwcbBDlB5clv3qsODbymr\n0Ld1X+vf0qiBJ0hCIcnMk+l9wr3BkgnsuvhQgwbxKO2KrdkqYW1raV6LGzhaTlSoHZhDjRjxCFxg\nf5FxmMj+xWQ5SR5V/DL3jcUM56T1sJ1iykHUhc9onH3aVdlDqvEjhfzW4viMVYGvDpZPmAwCri4W\nMH2rk2sHBRFYmEu31SIGOkxauKiRvxa99bgxLyQF5fgOwtX6+Giz886Abr8cV75NesvgtzIt+7m0\ne4cSuAWryXgsmJ56rxIB9lxtiSYuoZr8mkFIc5sJu4IswEOD0TXUbIpw/rE4S9Wedoj+xN1trby0\n9SiSNGua+sP+UBmDSfRymWU2ZsgTbQmdlbfYXXUnickkSeUxajLXRLG4Ibk3qZJsc6935O3HMiVa\nvVjNDHfMFmwxvzwBXtwS8q2CidQIXvTHYv/h5zACjkC13m1FycP0h8dIZpVg18ES2OYPGaKiopMb\nicfhvEPVJSDU4Z4xOwjB8XH5fRYNReHZLMcDqH6YxrWUnnrOf4UWIvyqUGCJuVy83YVr1TvuGoCu\nB/T0n+KlwTQPiCF7agbIcO/QeX6f2aK6zIiwLZmCkTi4pyZgdtcAws7yRDx2Xfed0xO/MXhyX5xd\nNTljdMwHnmG4I5liE1mPY/7Ho8+Aj6TqoFLqrmCeRb4hWxNMjrO02y49vqCczKyQaSasZ7cVh2zY\nkC3k6JSIJUSsi1KSKSGIg24/K7Sz9m7RYja7uBZXSem/7sNUgF59NlrBvX35rmaj7zZJr5Wo8Jyu\n3l4kbha8ZX7vu1X2g3H2P/oRAnbdTDAvz2epzqPpoLeI1METd+fbOm018KZLtKXRNVBDK04eMk/i\nz8CtmfEBn8EmXrkLJq6C9u8MHr08keXfppOibvvkzR/rxWSct3koB+dyz2G19Ek2383UiBbongW8\nFKvm/sKcYDQaXrAiGAsW/5csZP7omZDNgEdiaFpY2IdsaVTZnGV/UPKgGcUmQERA2VaH0JD8EU1l\n8xxwTByaiS5zXaopS2VlGJftZ+eO5ykI8BbAoB1I0zwf8273eARxp9PqaZSEt81n3rJh5+8Is+nh\nTzfc5nSVYTO5WcccG4s/x+4XoY9Jl31FrxYtC/VPA5I3ZnXav/3DbGUhuBn1EzeJAWMH0/oLiaBS\nnrsrTKp4+cC4ilsTgqYivNUdWtto5UgYbeysX0HxxmpY9Vmn80G7+NYN7+d73wKKR0xtp8luo8/c\nAj3QXcodyc6s/b4u19brIYXhA1ZNyQ9omDuEPLtvgIx/lO1mJW4m+HKnaxk+ZUXZaysDxuAHKUCX\nKm/hbPo1RlwLwFoiHJQqsgZ7ddyhzzR6ubcPEkRiFz2gWbfVh3DdtWKS+gnqbNAsMGDRCqhGJZau\n4GBDvl7E1Cp8+MZscPN349lffvPnUIP9ZtHp7vHWDjXfBi7FzFnc1BL8UxaFG8j676glym64Jxqm\n3qyWqzdDCmUgHyY5NvPjI2DLRnmCnNEH2m6/8ZPvaalANQYyQnQXAIAG5osVpfRHthEp3/mVZQ5D\noobaT4pBajb3b8WlkEU7F2bHjHUes+Mk0RwvnNt9VINslqvXyeVGfrRu48Ev46+fEykRoSrsIyn9\nvOqRwAAI2CV790AcpBGXscu5hRZAnUQGgle68M60i0aWoXkIUDK+QUavVrYUdmNE4ukjK2GCDsNJ\nwiUqY2Ge6eI4SfPZkt1oHjDELQA7N46sX7slR61iyfsAerBFLWw898qxzpN5jOSwzqb61D0yKEBc\noGHJjncsHquHE0Nnxeyf/p27iUpNsS5QBV7GirNFsMw1xcl6g24wgp0i511Wg4AXykltpUYLEiGJ\nxLRStCRmoF3fcteOxamLu3783IYYrNKfqSRxwRIy2vCxdXDbutgRadlVFYZJGvhkCArgOKljZzsP\n99zqH1BWxZSR/T+vTM5f2B2m/LcnuUQaivJxhFUXYkP6bg/d1NNbPSfu9AdSAfZ6taWb9auWsRqX\neJERrqVYmEDEOWebBacBTkEqloI0qTbs0pCBmOQ4NiPKg4Df+H/EB+NJcz44OQVRUmA/myDoEPFx\nFjRa0lriZl6Fyebqco/QmBxWNAgBhFPr3fsnXqWYeJoG8KX77pjjyWaHoxVtaze1mFzXeC4wWEi6\n8xG5f6dKHy0k9U0+Wueva2gbdPBcyk0E03JqLwwyBpEZX1QpFi2MplLVR9EWPqPtSRGuPE6XsHbE\ndZpiY1StTYozqcqhtf1gxgYCV5VmJ58wK54v/FEEg0qTFlXHd7FsE98s4EbrLSQaysYnZK0tGdmn\n+0BfsT9ttOXOueEAEph8OvO25Sxb2+D1OCbDxS1LJ6cxXlyv+NpzbxjHig9pVDWlwgdF/kE37u3S\nndCdHZm3Nikjr68Mecp1tWvtJdYbb++5pc/eH0JDEbetqXmxJRWEP+LhYgeVeBYzIsI438tP3l4P\nPGKAh0RcAk6WxLzuEWNnQoZCQjB/G/Zc4bKKfCT6Srj2Mdl3+r5HStpIHMggyDM6hWjMPvhIQX04\ndGT8faO3NMMekcryJhHBH7ZOcWiHTPXD7Azgmpofsxz1kJuut+zQBrhFA6vGwM0Zk4atvzYncjOw\nRrn4ebFVfPq0V2ULHiXFLrvtQI5FEevnRaslzG3/ARbb5gLbvrnFjfPgCBzdoxbJXcnb6FKB4dW8\nAoGlksTX+v2sx2dAimn+BPpOKDpjD4meB8WZGrlHGAiCSM47ggpBARV4esnNbIYqpLLc+YaSYMuN\nQQJNNZtzAcCFFI6QNLnwT9A0ZJo0MvA96eTHUAkDwfxsU1SaQhQRO800cxbaINkbPAW8ucJqolMa\nEyAWF85sRX0/OCWNK2/zCboZEGzBzZicP3OFrpSYKHDQpnaXBC+/2YrzgzzSDEqG8gWEboCP0xBn\n6AacfryifKHYSEa4FpbufIBd00YPSB0+QXvCBKx0HDlyUv7bhWW76lk8kI9RU0PjyrsseQxjA0Gf\nLsTBNSjT6BrPgfFZoLte1keyCNt739BB60mFA6CNJmyKWonp9YHxB63qOrkQToQrWozLU9+sh4mM\nDakyZKwadQgBPg9YC7Y72rdQLH6G/ruDThF6KmIc1ZWiyjHTexbQQ6e04GatLhI0DvPZMrueEe91\n0NmVsLb5ObFfYIUnkguLAGgyGgRN0JXVSPIDRUqnuJdiV2GjzLfvorUG49zjqgPlgyvGl1vvd/DV\n7VQm395mLk8LCJpjVhB7xz0DOFZnYq63UMPDipa2GU7neHQzN63z9U4R4948b27G7gFNCjgqAY8/\nUxCT8XG+0akCaO2q261a4DV2RMhtABt7eL6DTpBoeH3mtUdf6PT3pnrDjultr69ysz919OVNdO3T\nkLzgzCNAD03deOOw4LzPDEbhKUAaRvhuCMM/A558ewhzn649hua8fxW6tw5uW2baIirzFu6u+Lrb\n+zReqjENw+49PAGqzP9N4hp/z38HAW9Yc8iSVkq/2tF725+6coFV0AK1BPsdh4lOTUBhWkr/HmTe\nAPaUNxkX2IT5VUz7DAsYOnQ7AciYAfzl0W0V6R58EJUUQ3xgzSdXh557EI1GafB0Z2eblIRcYXnx\nd6hNYH1HdP0QOCi6uQWF2NU6KYfpbCUlcrJLWzAO/VOZLB7wXQPdBmz3cVBVkAmrS8zDol53FFcE\nqrErsE4shfBrXPMo3hUIZlRdNm9n32Prpst55horcMsPn3N867MNR0FuuEwDjLbClgP0IOWEw5E5\ndnaM8dq3VS8mh98LD+LVA42WFmJlHhOj1z6uq6n6noHv6I7RuDDtl5CNG17mi3alC0HnXkhpkvLh\ndn3/gzXsJKK6thTubRJZzXgNuskeKkRWYDhYTNzMqZrAIQ4e9JoEjxFHMCAeK/Bjb5tXtgYZmZ9O\nOtwmcsgH8fzg9+OmqfijfFJ2LG/CcRCMVqr2ObszJp7MmJ2zH2nTJ2GWRm//GKl0OcgQrbqOgWtl\ncPE+3RIyvTL8uHR8mS8QWmxx2HSUupSQNERk1LiFIvxys+Xujpw8HFjuPwB/CMpGPscgVWynl/R4\n0v4ruRxhFVOfL/C1pqU0mf8T3L9LwICTKvz68U+oiYNaKsbPvop8jb5qpq+taADvJ4jDlRnKf16R\nsFEgE/po+ensiAuwmB6DDNc5Pj6Gch/dYknIAdsmqZGhtLGI02v+3E1FlL8XY+6HAx8AFlIm0W4Y\nfPuAisqsMUT9J38HyJ1MO4P+LxMi9WAeT9Qo8DZDn4VXakFydgWRpv2sxzOt238rB+of6MNADZBg\ng9rjXVUH8St5eNSJi9xdpRCALI5m9ZFyD6mPWfC5ni4VfiO+N1h9ThvmcuKrUc2R1jiXs3Y+6wqp\n/z+J/Fd+WWvfgg0xjzpqVjZYignVo1QgX0BpeAdwCFSklSuRk5/hnksJuL7H1Z7R2U2LSrXogcYo\n2ZgWowig4w2KE6MrNpWM9G4KRCIPdxbXarbf/Hg9gpoNXiHrrJzYH+AaBClc7ld3Pv1LCZRdgf2d\npOoTM7krRBdaVI0e7tVSeSTvgyFQN+qHK0KBtWFdTIxgE8bCAp5zxzpq1cwBjBeaxyIjQGQscsOd\ngsLsctzMhScfYZS+sMT8INz6Yh64APoEj31HSz5ZPq8fSrLb3BJYHa4JdzpTKL+X9q54AK+lo4jq\nAZAVk42GabveZqd1lkdlcx+nlWFcUYvK2PqWnOFH22awfEtYk3cnO3rjprbOl113agd3pkYa7fa5\nX5ZPWRk3LL7apme5qN1gONLK14q24WDjAJM5i7b82ync4JrmKKKnV21b9CVkG7pKZC8Mo9qo8WH6\nXr83W/y0SOGagn2DcAHrlUZlJBHRmWa58aNINiD5bRixGLl1cLGzERHJc+gQykcdDyuLtEr2q7RY\neGOJ/qm88fnCcoamEFLIg169qcSc0uQ7tQcDHXFC6ME272Ef0hQPaQkesWVMLjqOfvBAd0EQjYIu\nV8Y80hSv7DMoO6wbs2UchVLLNbgJaB/a9AkB9o95FSF0tBSSQHInXSet82XlbqLP7sCCxrbNSR8e\nJvQui/yGV1i2zZ+rHTIY+Dv0BEoYdjr6TBcq79SPVyy71kozteKBakBp/VuhGjfDeuCUyBvS/wkZ\nE757+bFy3//pLqznfN0CBTraRO1EuqRWLnWUUijbVJ1o1fV0Mzx9CaJalE11XxI1ZqE9LATOsLQ2\n++jj889XUQtXWoEsFO5Yvndv5WzEk/FuNffONf6nywCjzye9HA3+MFi+tmygXKjYg/Gfl92W8wj4\noM3Cloq1IdCnp/qFs/cyGgodWRds6Dz58CuvCTDPvdND8ST3lWlLaiIYty3y+SpqK4RnQXOWUlMd\nNBdXB4YzsZ4mFouroBnHsE6rvTVQK80PCVc/OJ50hvkPrKJDW7WoQmWzIlI4T9u5VNafs092wDGg\nMcxqaQ/+UyiwnC3v0EtCyrpyGhfIVfDg9frf5xDpEqTJLYuAqP0R9ZC9HKM61U7Nkdj6qfYf/QU7\n7c4zt5jyK8emFJKju1D/aaMAixPhPrf8HFnDx+3FKVGd8s3vzhFKsmlSWVqmbGd8RP3Sg9zAgXHc\n1TwUXoRp/fIJvLHSuaW+I42VL/Qeq8zx+4sZWhcfmoSwhtvZvoT1LIyghFCE/JNDcX4wpv6aDN1m\nThFjxv3b0sf63dDCAe8kSkb6VF+h6tWrI7CYHGe0/pyi2qf+7Zsda+7uWFL9IfrrSIEW4T1+ivKH\n4qxk6SDVX2I/Y49i4mYz3rVrJXHQghGU1qE4kS53arDQdZ0X41fhNcKNWDG3twL9HTsJpYDOISPS\naPYdgJHv7Q6u9ycAzrGM6RBk2CLjTzX5D9L6ccuXCQqFnlanaI/dvbEtW0J1D5t15RWu/HOkcKHu\nFMn0jV47fxC04Z9uN4S6ZN4zSWlolmUWuU22IQYbig8+iR7ktuXhGk/jrGwDZ9eXu/unDrJ6wZOc\nO+ArkeGK3i3dNZCBij7JZFkMGppLVlZl53LJv2+oKyzN5ilc939REqehEkpfvpFdU/0FREvf8O+P\nWqxix6jGoArEuB5WYxGezgQZJ66WzmvNVzke2t3Qu2gEyrElv4Kx5s7iVFwvCwJnY/Rkaaaz5pio\nOwFYUbP/TiHIaTN42vPReH6EZ93DaA+znj8UkNMOd3ftvkShxGFwTtirwNbGW0OltQ5W6uS/gvNs\n/WDfoNqEjjpBEKVoOUeQsngBIhdfQGE+pqCc3Yla9mf9tH4ZTq8Fhv2+YFGgAyG10na5luX8rpxu\nEZS0QFSAmcMpDOyKvMlUfQ2PJrMbVJv1HV8HqVU1KzJx1Hvm3eGe4yqOuZQBRr3rOXOE8gTLlXmG\nOI8rqrmT5jIphj+bL+MmEaQgoiLrI63G41jKrJ/48LKokYCDnLMbezVovXD2yXFjgIMA/0kqjW9U\nZo/XbUr5r0xe0B+VHp4QQ51pllkUX/dS1Cs/BRox+jYztodQGsaKlI2pmv01Mhg8wwa4ciQpzbiv\nt5hftRyBs3QWhwilegr0yfX6Z5J6w3p1WUKzI1a4rIN05ZLWvI32nEHM1GyOinct+1vscujhWtYZ\nTLyEgZGFm7jiW21LdpkmM/1/KKlMaPVw7tTAjHz6ieuX38MxaysDj4jVTqUYVEthY0LhqSwm3XRS\nXRHSyRLnP5z1QMZ7ES5IaX1+npeUAIq+E5AY46X0yBk4Yp5U65OobbR5Vl7U4QeDYj4BdDNe2cZJ\nvKlkk9VIZf+iWdK3WcFgV2tSzJVPoo7rDQeRFHKCqDm85eDuiBmkvJ6qdv+yNSyACXgq++iTNUJb\nPpM4ZM2yNH2zsZK47GIlzj0kZOoYRmJRdCSJ2sqbl6h2n8tXNXQu0N7MFE085tE8tUQeH8IXtfFF\nzyc1Mabf2g0wOpCrBe0izuYAMd2rCVEXv0K8i4OXf1Ds1Y0cmRxDS+sTkV2I0ZdypT9VBVuDtGvk\nxTKaeUUsM2xT38MVMX7gPYS2dOJnMswE/K9Y8WBoUMs2Ph6rNcbRmvQt6qe0lt+mulyGVAK3cJ+S\nBFfD/VYMM2+88PbShdj7kdMFqo3z2NkFm5eAOdXdLjmuouooQlbvs8it73tTltQ1jS/BDuYmp8dD\nPOp3NzW4WBeWh4WqaJh1Rg+k/4ooCg/R6N8gelUt/Lk8IGbkybSoJgBMR4/13e3hSKtBb/iT1BKe\nQe7KJTQBWB03ZfBDYO/5UKWhcUuhos/EQ2RX4yf4DdhVUEZJYXBrrY30cSoGibAMI0QBcuMdnGP6\nHuBtFWMqlvwD1H6O8FjjOi8MDms8TGrk3ZN14YgGs6jTjJ3gYRPExLh24auXHdvvdCxPPWe7F5Hv\nA8OCKem6KlpMj+8Udb44tNuVDLILeR5F+qAnuYKVlwbnWuuiSfxlmkaEPK9tloQj2AIr7h05Yfot\njK4X3pTjDEfz4hJ2yaPplsezxWKzZ+bMAhCbk9Jsh7D94YFvXyT7FXJd3547SzYvazkMNncWGjH2\nBbL6K/FiqADtp9pYaKoRQbKdEg8Fy36ZuOX3861XVxTfEJiBl88Ki3etehg4wgZUwJnnSa70TP9N\nPxr3OolbXdb0MhdcmIGiEGF4zRVt4vdmwHypr+PvwDd0ISJ/AyIMDlQDo9KmGatuMS9OT3Sad4TW\naLNrDTASeke4LePtmEMZDLo6zkItPTXAJmeVGZMqDGy21hgoBCWW4/CDRH5pDmCP622zoJ/kJfdD\nyZRJb7iGin4T1HycZ6XHcSVwkTYXx81cwc4NRwxsZdQ5Ld7NEu2fZuQWRmqqSlbZbGtgL1qJ2iuN\nM4dfSlS/3QV2CQJC/dzAAbyX4b9D2komfl+eHugFRVLUmNBaViCSi8gNndEK0/5PhFH5dboXmIcj\nYWYBcvIoioh6A4vCGcOH+h5K9g/dpjfmdNmCw6hcACMDBDssk0TW2Gnab/bZuLhZpCTWx649mWTM\nt66RBJQnZ6wQUX7KBfEsnWq/dwcBf1mAGQC1jUlmer15Y4CBkFHofvLYrZtvtxJdZi9HQq2FHsHT\nn+dPk9Bqa44T/P1gEt08nyM1S5RvU6TcqZ4fvVACVViUk/zeSrDwkJObyCfXU+L31sJ772rzB+Ic\nR26ODsNpEwRm9mz7zIUW0tKSAl9Y3RCsUNOf28W3eeWB2OIEEDEsXTeuy1eUV/LyQRwCiICbeSqN\nhLSRmkjlwg0AvKDSlcH2xM03/xZTBPxvwkKn6FqaSncK7zAftzbIrkR+a8pOFjinzxuQ9itW6tFy\n6rbqpoTZqfYBtijqAn26zYXWlA+QxW22DdqJE/mqIIpHHoRAv0ZBwkdJN5L2llPu3j4VFgt7aiYX\nBo/k1G4EN0td9f2x1szwGx0hxfHHQgOyDNx+uzUPzNQ6EfiOmt8JOjqvGYxQH4Ov7kK1Mx2QVoWe\nnyKnnpq+zlzW9Rx8uqrWU05/9NLDZv9Mfm1WAegULVlxTmbThLYnwwEVH7mWMs9T0/9Aka7fWQpp\npVmRXziA8AP7qprRo+SmN6mpE2Ykresr3GYNcm/z2802ME4vF8SsVSo4avbrd5+9G1y51/9rm+si\nJd4ldUCUu4cHM2bTY6DLqYgocIzpg5g5XmcLuhuzAWkHfTuJQT9G1zOyjwKNu/nG81w0sQUGt6AY\nC3YvxAqktrcoXlO5H3OnjyUo7T9XnPpRl6cB9nZrptpfcbFuwBka73ROmAAczsSFMWfiwsoKvVV7\naGLTMkb4330M2ZN3ZVpdUx682IxkTOhdcb1X/XgZhY7WfLIKMk2yb7qXQ3RdsS/aDFhqAXpDXO6E\nnvi3iHaystblPxOGRqeI566yOosG7pkKuNPKWTB9MATmaBftW1tooI781UNDTAx0W2S5a+1hczrC\nms7yxhyELgSKHbjuKMgKp886t5pMaR+KMkfIMrDQSdVJgvcH4Zezf7NzPXOMT+gAdTNqPblpsCHB\n7WsDENBA9U7DC64EWpg0V1XXzhk+A318kGKk0lDae4KEmc26Jwt0K+GT230q5nFWJrvc60mzPihR\n3bcx/8cz76GU/T9IZBYIZcxmmf5Bwbhos6L3v6iLQk2hI3gTABpCMEDxaJafZrq5KBWLc4M6jhKu\nzkJdyw1D/DwmKNnWG1AfdCMIPZdFNlSglhTypQcgGLOjduHFjIVHkCzEcoBSPZoSTVfV9fyBDMRZ\n0s2LmWdumDGUlOyvhegbmLSA1BVcZYqQoa5SUQT+mffDQXBHbT0IEhG4g89JvzB/NhmLeYKaHRbB\n2lHg3X3zXeP9ZF0zUnG5fSHeKCO1nQyOE3Wz9Wwchv2y/UY4jdWrbnCLWOm/tkajJnWQEGlOmTLE\nCXlR1+XQPY5pLnaMa5q+g9Y88ToZsGA9LZ6u+QwwG29WG1/vr+8ebBCsOfrROBIxZLQ7B4szZrrj\niTpFGjSeUcLHfpXMYx8G5Iv1nzhv6ra4V5tNzrlPvF8LjzHEQ2nT3aBd5Zv5xQY+uRUm25tg9k8Z\nPFEdWWyWyXmcu1nD5xcbL5bal+VxLQ67hLXh+Id3uzH8jF0RY7Re3CbpGBJeSAwzMLizxcqqUvcT\n6bSrPRMLXITTjdkTbW0LjJyt1GsnqqDJVy8Z49jB0WSOlZnvlzyVYX2u46a02y3FP0Sl/UzijFGZ\nDG6aGJub0RTdOGwJEGwMg4cewMbtB+z7lG4CfhGY307waZEL/rnj8diAiBhfKkFbv8sNlQbKnAuA\nE4VHCdYmbwB/NLuTZ4wUvQckWu2vNcxI+488MzJwO/7FvHMjFYmbulT19/9408L1UizNaOlukHp9\ntUTRNAoFOh1Jzelltu/XAaQkTSzmZA5YJ9aSV/YOnGkBs1LSc7JjSf8crxJ03kx2T1cte2UQhMzV\nZCbNHWou8Fu2pOkMammvKonGjJxSZEVgJSlBaCMDn2d0LBga1+b0CWZnAypmg+3m0FLpNu75gjxb\nxYkfi1u7bfC6P1cV+7aH0fzkoz7wH4DKFNdZPTF42pkhfjDmHBT6Bk5bHvhue4Ahcm51uYZpyu/D\nyWlqRGPFtut9tp8Jlxq8en+xCuX2c9IV+tbSQZj2wrywnLpfOG/Sg/o/2olw8VwF2V0M38Q7s4du\nqOHFxKSqSUc0rKj1anFJ/O92zdYLqjCWWI+7L8p+WPZKc1XHUK5cpKNfslbE3Kbr3DgL4ijMHugT\nbwsXZB6bW7R8XZDPnNcmjJXEEgQ+9Zauvevi3hfB4p6skMvSoypdvhw2LMiKE9LYi22YgKWgeI3q\nuaRtlTBmR66hXLXd0ijmHXOS3a4uJYcUrdDCfMoje7JU3233LzKosz8zpdbvLJjhtAx+8yISRVVo\nYrZmSPAsKJqnfTDx9MU2yquhAJhNvqnhdXyIMmQ3Vgzel+tnhY9l7zqfsx6GmCXnFeCpkQEZsLrq\n+sIVMfknh/NLquTiBWRil+8rLI/E2vQvUVqH/isvKNmdr0UIe6dD3wObcZnESp/dtwTaZwlA6VB3\nkYvk1fsxsbnBV9KcJ7nG0v4T/OS++z4lUporwg6bkEt3JkOEjZYPJal/qMDE0NkILeKX7EyZfl7Q\nqOx/NgdNzu+0ZdDr9mHtcXJS8FOYtvGaWm2HudJ3HY/mQtqKniospPj5RwUkpuXQvlD7GuHlh3Q/\nTnZALYy/tMIGZRtxND4gW9ZghG7EWmav92r4vRLE6qYwzg18e1WxB/D1Y5fJsBcCRfzYrq9ic04d\nPDqJPpXIpCiIR23lLF+N2Q0f782KZz3im7SfmVo8Tk3+IrZsbwo0Kc33unZq+YpWG4EFtqdGxINC\nn8EY3XX0/N1dRc39t8TBkiC2c1pIv3rt8CjxjTrOituRAbOvZe6uGtGjEEZdsW/upkqdNG+dO2HU\n2g/MaRrTPdtltyNL40GsTQwpfZuyQSIpx6OyO8939gBt+ceDIXV8Ua9uEYsvGua+UBmHXWXPQ4N+\n0uPhC+BdFw3nlAxNASltgsrlWXHUfR4MO57LFU/JfXjxRRfi6UERLXNm1F9lBq5cDye7YqKAX+s5\nGdqJMTMPW/FP60mqkH26SB7zbAF6Lbin19LxOU3lGnHmziU9X0eAZ+QHnglLtNWnBnLPpcLuNKQf\nfYUKrRG0qKEeSpsxPnRg9UDV46lu0p36WpMX0YL/X2Pz4f62s+bAgVRrz5v/EqJBVFbhCA5H61Dj\nhVqDCHSKjFlWtums2EQu0MRWNqKmd5yNSrBnmIOPuV2SJWqdf1yNYewSXoold9rvrkaOEsQq9eBP\nz8FxONrPuHZ2/1QAvmZOvoT5Po+rUyFOOt7c407gICr4EHBg8YljSyhpwEb5n4RLVoCuSvrY4bEc\nB7HlzfiQv3/ibdQj/NcbJhOcg3vi0Yig8iMFeYdSks+3Gdqov4ikkq9w9OIiZkNbG59b+oEKVs5T\nPthPWjePsd/T0gLYssifUEi5unS4gcHt3YRaTkhH/XpJbjp98+pNGO9db0cGejzElmW4qKUh8aCW\nID5oqLzng25fYpp4mNIzLuJwX21Uo2MZEyB00VruCZIc4Sgs/qrIX+ChkObQG9zud5+LQfNHgRTd\nwYri4Pehr1eMnir+nnUCBIWyvhLSj12QCu/dacKaDFKd9Qdg95sUnxO5twLIcLh4NkSrNZ4v/+b4\nNZwxevXVsN5jvDKuL2tJut5XdugZVHpH8qpolIFHSj498RoiMsebLrv9fUSOLoFLJe9PtzC06WT1\nb2m+xuCrzYl/9LeWvPMhqfSRwY4Xj/8bwdhXXpNi939Kr/fLGjrCDMfPdc/ZHS3dAvC88mb0knr/\nLm4k+LKR4sK93H8jQfgtt+CaMDZ2yugCn9PCWJf1Q8ITsAayba86Q9sZMJf5hUxpKVawryivtklG\ndlsTIGioK93EblRZoA8nfKNxmvr2IOUk9E7tZRimWtR6e2W6jfopT0rretkwrcxtBLcJVl+oDOUV\ncPemL48O7KySgev6jKgICtAKxXzdGrcxxAOhKvjG91jGPahSnfyCtymiN9GkxIDFCoz5marQJQuS\nTN/K4Os+DbhhLLn++eOFlkqmffFwUVqveMzdtds/KtR3n3EgNdWXCuzaQD5p9j8AKOrN0L6rliU2\niVLkggY56w9nuTgcQCyCk82zhAmiBEuDW0FKjwABCTJ/LHFUYqSeVmuH3Z7+F5GOu5OicRsUr0l0\nfCfFZMdZsUd2iIKIEmVlviOW3s9riXG5XGNdZI4C5tw+em8idba7ovfSoxrxkK5MNyONotEg8FbR\nBMkizl0K7PGAeBo+8uV1AKnK229rVB3+6HPlXMOn6SDCIfGj/IN5q6cHoXMsJz1J6nwtERyiAXfU\nVc1aPD2OONVuNfWz3yJGAmofqTttj7NLAivsO+7WgvlGqDqH9EoWsil34IN/pi8zDIp2wRKGk3fE\nRuKfgCAFJtycvcHWi7mml9dKt1sy97MiPGbOKjstOVyXPE+6PLG0k7e60kMQcT/ozH0w3PKkF18j\nYeR6S+O/Pre83Cw6t8aN6AJaTmuyEu+HyDxvpQuUc/7GpOJh/Ib3kHNscR5Z9hl8ZV3AHHdzCcvg\nH1P0WzKsIDvJz3bxP6cNbU8CznbIVPq98OOIa0BEwjSNLj7F3gmqDgJwpqjE5P6Z7hZtUetxJLU7\n5M1Vj/sYhth2RtZYBrBc5y6kt9VxbPA7QaRxqe6uCAIgDRgPF76BJ1SJFpQLlw1otXlYPrfRGBRS\nikDX0qkTa+PDGVO+fAtz86n6RBrhMdZ0B8AgJ4KItywYJC1Z3Vd/qAElsgdRKyIRXwdngBbjI7Gj\nA6gHVjCY5F72AHNoRnIxboYQFlo4hOzoryBg7J1sTYu/Q7oYDe2nDeCrWrLHaslDgQqpW9kkq7rH\nKLpabfLjJBxEgp+Mwdt37XxDPLPn7BgsDxNmilfvqIncP18DXy0/yiCxrgPwkjgG5MQfc4B016u8\nNgDMknRSZbXzKN+WzsZy/zBUB1sble4qkRutNcC99axWLr+zUiH9ABS1h3QLFmOFbvRthb6EIWx9\nR1Yih3hoqaTJsNB/nL/ECbX9OrMNar8s1/K5Se4l1U1MEsxtX87ZQBLRmvG7w50CjOpKSXjcrFPI\n6pfrl38/4htyYpN3aRdHPN9Yyq4ZU1epTCtjHNvojx2Y3Yjx01X0GwrG0kfsXUNZekaXDSGjcYUe\nfJ+vX3Ljp7DWNFoED8jzfCLBdu3toYfuUrBmuT5flF6xaWc+qYGxCltoRrJqMOMqAkxicFtQGtbv\nAccdwkROiuXVS5JWHEFYpesS5OAxxAsMuTphTltxMY/gznXUyO2Pfr2Mefe9a6laBZXPECN64HYI\nNbhYGYgqrJG5d4XN08ljLJTindjyG3od/doO4gQHr8zn8OEn4T2WwfbiGTmX+kYW4WoYjgzax2Kc\nLAmpOEv4d3jB09x6Pa5lZBpnJ4T7dD6Gwig6s2uy5VQSVApzvsr5EX2unB9wNxvMRIpjbNEVmx1q\no1WKHK5xNV4Lc0qfPNgzxQ0fhAcDM4UFgBdL7vczjjLnW7LejF2yT0pMJiqCYla2hqOVILX03ovn\niU/tGoDC3WCglXKYnlift5KxavBNxFSNVrncy9f/qrNw2E2GgeSRs9GH5E2gvHDaLkmshEvGdxb9\nPr4KO3xvuD+pQA2Z+7DcPXlcbBMUdw56V8wQKbeUjPstcbq9uxUeunr0a7Y2xBoSWG80PHSnsWPn\n5XHJ8DywyebZqQGTev9Dk84qvFBVoNOu96dskaeh70b4ddBIdl/svc5IaWNDQVZly1X4TCECLFP4\n8k2AXOzsJ8zzW25rhN0qizOKGMA26Pcnaee9+VuCNMV5Di1MMqsCXVmLBB4OlwKIEZ4f8pzDCkYF\nfHd8By4L3uNusdvIm5PqTMhknCBdl7I+zrWKvsqCOn6DzZLypPuKwJxyU3JdUAIcFPzvEPyhQgJ7\nLfwsK6J85mej8W9HUanmfKJHB/9f2kbHiPxBxSEpXLsSydAb7Rr4Ue3w/GUxX8PDwYurvAoITZ4J\nrc5Y2vyP7QJzT+MgzR6AsGHM3B2Cbosi5zYmQAhqsrm0x85giVvnWLxat5SkknJOUXmGnz4jfXvC\ntGSP8e7PEAF1B9Vk6yaS07DEk+SojOq+WpM2jJzKjFDgGM1A17fWFm3WeFLCGpszBNU45PDlTzlI\n9vfJFO/3KwmFqD1ZKa795uo63ydtPWQICuoGXhvqwS7GLVS5nvKhbyj5T/QxdWbPcG2xJxmyNsAk\ntjvVaeTcQYVrhX78LkqPtMJBaY5g0DMCEaaqsGaRFDr3f12TMw3Pt0iPTsmJsvvJv63qW9Y9NApZ\nK6aqJDwP2znJy1ImBoY6iFO0s8UgwoDnDSbOsideANEGLC1+H/bTeRsKlObFBv718yItKFVBhoab\nJ2G1gm8b/U6LwCzz9MTCfVAZ9S15tLignu7EbXWdhOtTICfuivbg5M1FuiT20qe3aSjvHlv9Tsiw\nEaGUeyaeUgR02Cy111cKaPCFAOo8XFbBbtlO+mQiKDCiDk639aA0GdNEQQ7rpSPZBLSDjd4HtUH3\ntIC6DafuFAZCrhbMvkQ7j9hHHuaM7UI8dO87MDrGfldecg2RI3jAimmAThZtunbfH6P+ZC3Nf10m\naGvxoUr+LPWY1CoBaL5o0oaIf/mmGXi3y8p0HYbo3fFVCotiu2Z7oc3oEjQhQp1AzKY7PW6bNUt+\ncNdprfn4HHxJmkm969AkxKJPIRVY0Fa3FMTrhYNwB/ZUx1HpUNsQ6x+1zlOMpOE8Hsl9syMgOE90\n7wlNpo36u52V4Yd/mxw5T9uoyE4vVRfzUO2E+5g06xsyLhIlHcTKvFfeggBgflKQPpBX1NEK4TRV\nWtV8SHIZkAUbLNKaaG+QhNmsZLs+uiQXvTsFJvUgHt8Bflxy4O2R8Rf2C9++pcG+GkRxjd8ZLaVq\nyBjIGr9+YgtazfESTq4AcOSBk5yzQDXuW0vlPCxRHy8TrexlBjw3Nvj5J3Rz4btV7HLqwQLYxUY9\nNl/QivtPSm3sE5mU/f4Y1b3hynFuTtOAxo6d9lD+j8JNsOWjUOhs9DqIOlSNWKblrTATHixmCKOA\nbOfjv5m5n2UTnfZWuy5JmtSR3FTJoUTO6Y+do3B1TgNjspMpptCZRWMNuyAu4XBu5XNdamwbWCHA\nSGqykHDzYVkHQ5+12XsYOTnzHdsPbUCyi26JpsVl/jeuNEc8EmOYIpPCqH61DnKNvHLS70m7vL0s\njY07cT83L1R21OhkOnqCjUsx3LDN0v68IUCEq9zwMwvv66Pnr42ior2Y2hezUoBz2CUdWg6IZfEK\neWgZ8eVz/daRxanrtxinEXTVkGxuaTxq1cnABw+SNWBatGxub5E7Lc82M21z+AKJmeNlWLZ95QUD\nASPUdt1+Q8XmkTtU4ZUwPCxu1uJFGHFQQ1jEtlcDL3NuSSF8y/enNTLY19tqimDt7TsFvZcW2IJ0\ngMFBPZvyKOyYydsN7J6gIzPTnHjdgbMmuzxcrrwOdwXh1S6r+lxXeFB6vGpf/7G8v8fYJ3UUMhbb\nsTUzbDgMtHZdOrY7ZdSpyiIaiMvoMsnyOoEADc3ZC+jFLjW2HiwJ5DtLiKRXk8ECnrQYYHIZNwYQ\nX+kktt/q/Bcx/9B4E3lNv7yW97NTpGf+FFpo+ka0sTH/d8uQdgDZip+JcdvXtlXGiIqU+oDUQ/1j\nLcnrR19ZimC/IIVb28yyqBnX+VGdYILa2hG1BOB1ZECmrBahWnHVkG0goA+YWaz5pMylgrR7VNNa\nnGjZdJn8XpfOQVbWyMCW2uHVGaWzyQYjBiP3VuuYfr6stOAjLN11AATUIp/Rod2h7RNZBW6sWeqy\nGr+V6EKXkaPjNaIGx9WuVb2HSvzF5aNj2RJgK1xleTE+yT/ES6Vvtuw2f1dJsnN3AC2f9JrKzjTV\n/OSE1D/t9m0zR4EFf957rtOqkFOmRJhxeMtjHQ1bk36y2nUZhf38BhUSn85usGS0/ypRQyjs5PLq\nemtmaKMR4SV/Yv2ZlcVJtmnVDWBRn9lMSz/6JgZDcNESo+OTwMmyZ9w3eFSjsfEHzUfBQIpwzFqt\nnfOx9TUfzi9mqnktbgcFOaH/c+efMfvDAqBCBgYzz7Cr3SDPrdjnjKsCzKZgxfaLJPLQUnFkBOvf\n2MKRJeb0aQD2TDI81HSYcVkfviUA6pQXVrtD+zZavnTdBccCo5mPHG8XJjiK+O4EAYxzuMCl6ay8\nu44Z2+DsxHYumnA9ywgf6foXSiZt1ao8uRvIPSK6wWqRAI2pAdUhs3/KATSkrz1JpIPvlGfn2DLh\nCEMYOikV08QubmVUWvNTJABaa7Ch9U+v5584zkjo8rtycbONn5G7MlCpAVBKH9EsNJwq370QFQ7L\nGvy1td51LP0DT2XHTjJtN43C3GUChZhDC4KlwRPjDDmTFFmr/b1yQwk3AJlGh2iPEvUnwq+gw61+\nMHKT4Jm/2r//uile+yNG6mTFeoz957Ku4djO3WK7pT0JUlUjDseOq4TLa4stDY+sMd/HyPFQiwP6\nRRM/49kZmjZjpH/KmhWwrJbytu4Jvbx6OsT59k59iKli+a/TPcasGnmZoYS+vQ9UX8SR++F9I5wq\nNOie2LPuL1YQ0f6Tm2SGk7gpO4OAXgbsZIx/pMDMGxPS9puSdPTdj4irXkisP5X186JB2kqbCenQ\nTqWW+PJkcK/QsNyQeLYl+XO+o0U+WPEXp0yzBVV1C3mrVAmBugz6ip7yyHFnL5Nf62Y5uaA0Vozy\nY/DPTPWIYgZkL0A4UaLwXqHOIIpK0dUA02qQL/JfO5Hb9rDcFiYmPWumW5p6bvpahNgFTmJ7N+yx\notlirukw9tny2IYfOOhwI89SjO+RRY+iLNwMTyS0yAfeO+Loi8xeUoYakhWTBgrBHTTP41AQTjNC\neUUgyV3dPnJXq77tij6TKfkd+DiIX/PcHG762yKZX6yXXavUiZbTGVt48t2no/umRLmC1VSFRS5I\n+IY/XFsd5H2REs5kLxX0wHgzS6buLalM2FmpD9/NjfmgWLKsRd6xtehSepIIJo7pqLAiXzycJUBW\neBpcnoTZCAsS3kn2ez/y1Z2w+3n39PcOGQwB1b2FBfkMYBiLRNUTnPgECkxBbE36DVGJZPJ6hGFY\nS0nsPuBDVtKROAQpGQjGd3Y4s1+7fcs1/9JYFIwSs7kTJYXLKhyIuoOuHKu+l/Q0fFNHCdraU7f+\ntgq7TliiBh8Km2eKwcsWBDrSWUAyLpQGxK46LSXXIcYxqOcwE7iTGnkTBH0/72WeuEVTvQ/b52gH\nEzCpJj9r6Z0anZ1vu+w61Ns6qqawP+bu0vlL9X0HCvPs01HnSImyMusDVijCUC7hFV4IhPolPwEd\nOc8IgKHHKwOu1yKMNXnp73u+AAWOxoWYtJE7z4a2rMVmCN27DFtGMxVOFdDkdr3HqJQJnLV1W0j0\nXztJ/edplENb0ElTTuWgGWlrCO46EVOe06Hz94qiX4pWo4Z4VEHjqsSy4tmbtaaxkrwzrpIQGnbC\npY7ZAY1Cu03JWsCBXVMwvu3ZxOTUUaYqRHwpv9jGijiVarDIYAf2JnS5RTZQnqSnPQZrkWga0FQl\nJNyHghmOjc1f1EuZOFN7TicbXmmoRIWor8EZWPgc2HpauFcYq8ZWQu8a87tnAUgJal8/2Y/DR7yo\nqhUFsPXEDa/blKVRCKiywY6qxRJDd6iV+zQysYLs1jFxQ7k1v6gPxuy45xJEQUvhUaNYxLQna6Wt\nOSeOwxf/d/j2uHQsgQ0COUZPOdbocbg9TkyOmGiT/FUEz2fXUQfpPeQg0SCJKo9P7/SyzuX54nbx\nSS8JJxOMtcgV2Sr3gFzb0Wtq+ec+6rEw7QdlVSjDoeigeq4aNc8rhMy96kD8VUWBj5aTNR+5b42a\ntBQhBnymX+pFDQoGdlJR2sMCVcF08U2edGiiwbZyKhj9ISzu5muvfZtWI/v6YJfHxi4MOIh9vYRh\nbtlplhceoOwGZE/RypX+Qvla3it9hgr6yhIMX3RfU8gOhHTKl2zsaKq0+Ql5y3CHPq02r6pWPXvv\niiHjOEi7k7SPOp4v87kDyHOLVSxW/8mK8sH7oLcc2YPqO+iEOtiF8EtIAvwQRx6noMlGxuFwQnhl\ntuHoulwPp+VRFMSXBSIcLr/ALSXHV+qk3XAqYQvCvuLP3XtGWVC9N13FlJt+v2bvZowVg0vkzR2k\nvFgdlkubh38D3gttKNjg2ql6641+FLSgIso39SF3fRKVyvjB5KnXC48JoHU1Ek7+E8QDGFIIzEf9\nWIC9woE/Uz+IVLLxyVWEDyTG0yVaqbqkX6HA5GK8rKl25GQTrRWR0r4soZ+pYeNH72Ymaym2jumY\neS9JfLl9QrY14wbT8Grm/5CtuuvGV4gRJmREscUK8d0bHK1Z5s9C5c2i8wjciuJaXllQGY40UxVf\n/oKpmb8ZpEskAp+GzZFZwsvh8J5fTLM68wFAywTQJpc0U+fvBfbp5tH++I3CIvWmC4lqGR69h5XG\nYlfd3NkLGK2DWj4A2Mp6TlOR7SUC5pKlDzhtnbwJw+vf1TcWRii++D1UhPLn7+eDHLyoLP7ZQJ7A\nN+T8jKIVgtpX92nb1p1NyYjfopkb86bmb60z5+L+LFQpTmHBCyqUoUf08yLisncBzr8br6+KR0W8\n/sy2gb1oyOice7hG7+g3WWqjbtt6IwmAHxN/v6d2L0RsCZopefaU2ZpqVZk6J+RJXCO0q214zocL\naFKhkrA8WHpuiGUp1bJGgpo5KvKlxbGFRXhGEttNwNzxaabcsdB2RiuSp3YzgpaBhjgK6qQzCyPQ\nfIi9Y67k0GHwoFmjG8LV2GzNDCdihIg168hpOIxspyDKFwqI9Zgh19DcBmxutSjY/jl4S2o9PAse\nQbu8J3d3VBAfZYCz8F1jiyMo+mfxAA/9MOL15xsQH/l8SEZIhVSlx6bOyKXV4CwRCLxBsjsXcUZi\nr3z/PTTXXpQTq3Imr0kNYKCmRVzSDpaMXlRdlT6Ewun9FwHg8NWruguKk4foPFYH7icte0878QUi\nDQ2oxzrpy2Rj3gvVJhHbZ/UmKo9Hleao48V/tWdtqrU/vZkX3pPx9hzmZbvfHNu1xwbcRyqQhZtU\nfJr30jD1xs2dNPiVF8WDwb2Fof+r+mt231SK6B80VC2eVjEdfFmZYTgIzHwxgaQnMq3WzF5S9bhY\n0GqNPke72jvD6jTt7yknz0e65b3Wq+QwXjwnOQRbD+mrydoFkBQSe3TpwrPSuPHyZDM+EKvWRXte\n3GNXONrC1Yol7aJiIs84sE7wcET4DQexkFr56hlvSss0SaxqryYqv6vA16SKXYfSiHHVDnQvBfpE\ntisHCpUHiFi+3HyKvT4laMZiDmd2K8YjUJ1ddfkpOcQm8Sfh6GD14b6ixqZtHwmeooY/QKq6wWZQ\nVUQ4HmJ/VKv/IcrukkG2supNR9dFLLgW/ScIHBaqCsyuELZxbXQ/yqeKsoFAj7014juTuq/yHZJ0\nwnEMaqTzh21RTuAz+uAIvAVFnmPteZrbnYqgelwWceYgGnyKDe7Vy58CrBosADOmvRrtT9X+Hkru\nZCHFsuw4rAhzhRRdEZWJKp6T78fzn9KLUep9TbeE+Q8mY1R6hTKS86m5m5J0Ydg03PmG5LrzQPud\nEg0e0+xXGr+hXXQRJqSItM/8vyjWk4qH3qYKRhmIjOl6j9k+FXa+Juk33jFhkRzCCuiG9moL5l4d\noDrMNC2BycDI5mKrGvUPNA+IC6B+OaAW5wu/yeh+UkQvBgxWCI9U1uA1e/3/zHnBbjd1odKjQa4K\nRzqTiOTSZTA2VQs54eYbmnCojk4ubI2sOBsiW/3W699xgr6J624Z9HzLX01Jniej3ytQhF87CIOx\nVQt7HNC9uvCYMT4TOTO6n0FXgh7Aa1qNIU3tNB+N8Vnn27uAjm18HDxtE+Lz6hVYI9PkrV486dhw\nnbgqAtq29EGmPbT3cd5RocymmANsFh9Wvg/iY4tq+uTmNLgS5dNIYPfyXHfs4EEFB15QCdjf+F1k\nQ7009Sw1b/6UDVUPMRxB0Esy7Vm7+d13hyqeLefDM4ZBZ1ErmO6Eri/A9mmsSfzPETEtJSDAUeHL\nWIvLePeQRpz/ZXlDudOtd2KOstb7pmszDXfH1V/8AS74ih/eyuM5ucdKjtyZcgkobjst14SHsmzy\nUUEOBRXXnKZUOrJvvoszZ3AVFrB7wSCvL4TJ/dHRlRYGbxVddu47OkykGf8eCmh62k2dW8myPpJm\nMBQYF30wvebP8RPbQF4pHiZ4oozjwKjHa+bmAxW5E4igTtyrVTUjmV9mxvnwLeowP8Y8qXmkzW1L\nYeyXPIOf3dzo248MaHyTwNI7KcqwnSkJvNvgBLbOvPbPId40oDNSQBV5Bzt7iM/I9ywTZubfgcpY\ne55lUKhP8cKfERBMcVvcSDSFJd3HsZqFnQ1YlzlzI04mt9wCG4a8ghxQFUbkQAf8soaGBW0kfkke\nmGo//elZNw9RgMipxjcJrYz4YaNoxai1uSR4IdsGfCG42qFhFYpS+XyGFodhKZJsV/6faZVasphU\n/PpVyzV9SKYYcwx9NxhRwpu7K3gAngn2TbOt7zbdvxBFk6QdJwRHk4nzbmuciNePAhouPGtdqQau\npEjwwUvDfkHjKwENIMHIRULF7L4C8An3fKhCkm35+qsThwhri5J6mt6nZtluiVokkbIqSIQTIt6b\nU4MM5Uj3TY8Tq1PS8yNrGiz1Esytsa9rJK+hpWdCYksziEMCiXEP5CH9H7WYuWpxx1y8NPHXzL+h\nWlZ7e5e3VtsSmf4pLF9eMJ0ld/guvbpOMkNUyP9AiM3NjIPxKwkfM/X40Ol8pNe3l7U3C6djxuLK\nJdBUaizlNvQi7se56NEdeFikOyWz5zRB5SPAQlsDUq7teyQxehqn/JCjyaINgU3uo2+kh6KxRuJS\n8X/2IxqwXV8OrtMbcxNFoFfp3FIeays4bwlz9kjL6tYVnohzPVAOaD/mePrE/JB2mzIFL6hrhQqj\nmCowvV+/GdSDyQswPQlUzcpsR7Z3U1e5P53eFzcFzURufKxqrjj6lBuJ2h9lh4/sefhchxJz3RId\nCiK1ARiog52CjpsBfOqAz79nMcV8mDLSXpDz4cJmMKa/rKizqm0tjzfzJxd5yRiUOfiV9CDyriHL\nqj3N7ywe+Q0O5M8m9Q9WHEtb8BkiWWQ8pW95IwFJRn/Pj2l1TI55Wwva54gkyM+HWjR2az2PdGdj\n7OCcZiA/5R4qq7q1/IMDolY5SvUQTdsARjRbPatQpSzXPeW+2aqNLnkvh9LLQUMxg6g6qXERnyWC\npkMEcrFg+h34jUo92JJxp/MunmRmwHJR/ffNHh0uVaMKblHctQhcAm4RN+A7kTfDON7SwlcQxAaF\ns0JS/gGuFaisz/dXEmGgwWiPOYQuRMX845EvOoo+8LlWa4faCHmVo6A9Uea1F4/5hql6TLuIaaPv\nxxX4cX96WsVQ74uOrsgyImCFxyonFwradewIoGe1BE5u7UWl6lU7543nm0emglgCH6ckTQpXbhFo\nQ5cOgRGVEkMGvwr1eR7KjTvU0wA9z9IljDUQLOymC7epbUbTCw026P1mHWY+OZP51t7zYNCOs9yX\nMaeYZ8KUEAGLsnxCSEiVI+iNOBXFyHBbeVVhEPf/35Dq2ZRAfQLf5gWffyoHFZ2KngqpyR54EhFZ\notKL+qUXQnjfO5u+bBoHLiG4QVIPJ+Due7lFHJHVZSXscNi96wS9Fa9XJue5yveCSmSREIJ0awTj\nCb+qulmCeMsbNdhf5EUneru89sNz/RF6CjQqG9fYQ2orvjJ0icY+3tReru4g9pzMKLdtd50ds6Uk\ndpsoRNBIZsKtxbDNHqISBam6UTfZDo5IR4jUpwoQ/BhaEs+dD7KiF+MsqhxYKSC2uftR+zZ5XJJV\ncSAjQIi6qZqZsZ/MrUaWBhrh7rVoX5TuMO+jIWTWrW8sCc7F4ME9+JlDlz8+7RqtJbEk/FJxDpZx\nRBn4ZdBA5JX5UFON3mAfCcFjKewc97DfXUtXP0cE9P6npc2txDYVshvjjjJHsMbXK0nbJKBWAHP9\ndOYKgHmgTZr3JXgOaWWmTaNdIMXZ37ekUM8hRbM1fY3X0M0q3L8Lg/L+Dx/2hPP3lx0DDR9ta4UY\nR61i4A6T+88J4o/20lqzkvl4BYZMIuMeYQa5wdBQrfkmfk/7GCdKV8rvCbg77AhslY5DUtdzTmKj\nVXGvpq2yH7B66YUpsB7yIQjO2Ro0FUE9QTWL1wbTkKBdLNDajYo/QkAmUtSZLKAqhhdbWusFhpvM\nlahmkR9rE8cRVmmjHaAFicCvhxURghwTcY7JOCe1WUn+aAA6xl0xBb4GFkv6azjPoCxrJHjtaYZM\nNaZH2Wi/sryzQlVgB07qrnZmytBcXbGdhiIMPgaX2bfhCdIPmxzouhYxgDxWXOZNeWw6E5Bjz20H\ncrj+X50nowxqAdOuZGg2UdQffDsMYW1ZhmRTllzZK3l6XQJvXSmxgNwdt+RAWZ8ZxgEIA7BEjxvL\n592loHf5J5dJw67lDvn8OtITTitL5CCQh8HJhaz/4mVw3g8wnsYVECMCH0DhAomJiLd+65uo36YX\nVaSTjWwh1jo5G4kg6DwD1a0QZeVw9BlScOdvmgNS8L4EmjubGbLWQZjencavxT7yePSReDCARikL\n8o3PvkcBW4rPBNNtc22+jajJqdFssNElnjm8JhyTWmeu1YTiN5+Uh2m2TM6/MC0y2nr8O1tdcDhF\nfN2JNlubc5nz9+XFNxrVGFmqDRfyCTe9GA0b+0PqtjjC5hAqPtgYMPJ0FhowAZW7Q1K8+fnqD49l\nWcU3AdTSMe9AYiMppEGj0ZrdCvGweiYXSetj2JWT2vs76IvS5k8z78kxyWZbLH3T9UC+HHhwB3iK\n32mONb62O3WlVNEV2rnQQ0Ev186woJkdurS0o5eaMCMiWbPHv6Pu0wHl971qxtpGaRpuh4WcZyEX\nxPXT2VjYFWLxIH8EqpR2n2rVZb7ZM4PIwcli+QYRCYscpiYZI3aWn4CRfD9jBwDZ3lceX973QpqK\n/QTr54qxXFhrRDdFBx1fOlZHUAailD0zIW7O6KmauReiCeA483XgrfQ3zbHqUCnXSAdsJ1Fn/HDA\n9QGIIwsUtDPuAqofMjpZSG5tf2FrAl5XOj05N9CV1SFBbVcXcWVbQDSYaHXuI0Ohgh/BJYOo9Wf0\nop9ij1q0DyxE3gj2b9Txo0zhQPpbEqzXJ10xdG/CM57G7L9rzKbbL4FrVJaaD3igO/oBxECS7xRI\n8qivP2cGkZOF/IyIiauGozmkVd7meXK/pSp7dp7BmnM/yP4vONgnccmv+RxSl13Aqo9EV/WMIHax\nrat966a92cYn6eI93Li/hHIi63OoOKbSWK9PwLboB9Q+YbDDCnKv+c8ZqNlj+oT0NPkREaW3yQWK\nZk4IelLm/T98BMOAIX9yhKZA8sKLwTDFRkiNjjN1RTE6aFMCL//Gy7PfdC80wqWnON+qXctwdw1K\ngTukMsQ8VxzogKQ6glEBFNf2MMAvFZVLeClZaGYnoXX2xCvs2yRpTnCy+SCUnHG43zInI2uTr/Ta\no+sVJDu5IhOb7B9hgS3+j2NW5wKFTAhPXrIwID1HSeaDf3w2iBNNFMEEkE9T2JztxcbPqRkKfSn6\ndQQWtXYcRn0fBtAczFEvKkWRyXTP+i0Sq1NNyk79Q9bvKZ1eVTzIK8f6PaKTliuFbWV5IwJvMpZY\n7707DW0qfwRmfwQPRv3cXU5Oa9/Pn+sv1riic2LqOPJgVHG11ARQCjqHAVx7XO89dHycSfIPjhLP\n4t/xkjvaXMiJVIXAzyrDTRhIydB6HSS03vFIYNQb2tOMz2retU6FPWT81xLYq72YWfzB1DoFqXWN\n25cNVmuOI9cHW6Iz2sizHby8m9m7+g+0vDf8UsmF4D/Nfblofw9TmOlbDFkIOkd2SACfEyWwMWOT\nSWJujXliGulCJ0V9fmZWUtUUzbVT6ZOqP/EPSwXjn95QLmsu0LkAUqfDnZs+5Eql1MsqDds5tSSf\nBBEOzq/7Bx+prv/sYPQdT4CL+Ax9ON/T5NuS3j5g6f2DzdOCLNiqLJf17Ofkn7NU1AedcQis0MHu\n23smLret2935z/CT8tiHD1Mf35HzIgtZvD9gCznMphnGXXoPulAY/pNLuI3bZeWu/tgbemNMFr9R\nYZanIfALLTdHKNXOXiBsVZiU2yYT1/+goTbv8MHN8dLpaIsUgjJHI+nkRp5RKM5lFquPHE0zVjlb\nDlqxhC7sAFVwYZMecekYswlHnHOy+hR+JFBxkC1moxBL+Rt7jhZKSB4bQRVXJ6VSgVT0ZTtscGty\nk6xHQZKlFCDof8XTsOJ53eB/iqmCxzSgRqmp01HKGjhsWBOZoL9tHxf7RneZ0vkrBTKBsZF5H5Hz\nZc3Ej1cNJpVTVCb98pLw+ymgWpLHwfhuXDrK+shws+dvPB0cfkZ7ltSZ/X90gFIu5SRR05Mb+XUP\nyum/HIg3kOjbTRRnh5n1VXnejGlqKiXEntl2h5HVyOtOh/owI6qzF4zraFO33/UtWaG6ydd92dML\nBdgOZRRVCfjZ3LqaUR19y3cYlWYTlFmldcPZe4U/A/9+bmhxjdL80M6AGqb5cXuByK7Dee2vAiig\nIORBeOk1mB8ufFyHlVgc+CEmvzL8jS1twE6aHtgy3rmxPSd02UIGlUaz3rQ4KWtd8UJsYTTo7Kqi\n+0EYFgfuqX2y7aCgOW9DF5OIAbeUCw3NrtiVqL/K9d/ESBZ4YzUm88b6WACBoKXpq4THUuZ4jEZ0\npKDGvDmSlgIACZz8ZEFQVi7wqdAzxzJIVw5J1nmfsM+sNoCjySFjsPTEQyEqK9u0bpADrLtEjYzn\nzcMhVSUQDaiM92XG2Do/7bmpSLTYjBRscoiUrJQ5O/Bj6ZWPdMB1skNzCH4OLus1F5rhuEK1S7n5\nvYbTzfCiB30dmKjLyxcd9++OyPjCfLCqqzzt64zZx+FMvYgKuVji1wAcpKxwGC5ko3XHhOdEhRZi\nJ+GNtbprkWKd0S71t7QuBAuE3Wv1pneDolCJbNLgzyUppnLuhm+eDSQk3MYiVEWNpDd0AV6mNIej\n7ECBdDibkGqDhyU3cEHhr5kdp7DNcDSmgIlxdOhH0wQhwoePJ5PlrNXBqqkEU3Rx5V38pVSiJ5vp\ns7OifwLgf3Imqx1cfy86DVBym/yiPhWoxCGt4eV7hTpTsOiMEBnfen6xV0hqRqsmPUzPxcoSgWkI\nNdVSwiuZ1DIbqab8dJbUNEo5rvIOcD4w2kZAv9qGxcxB3F8d2PcExkVs2Iy0mt3gyeuvMWIIBXpL\nPqcMTRilOACZhs8/qAMcveb+KQhM1PuD2cE1cutgJoJx8E4yqjJvihctCSrPj9ScS+s+xnQPBAHU\n31i/ZWZxzBAqnRa+mx0ZJ1JiFjGIp3/6X8qLZVQjQyyv83k2wwffgg0S+X6NnhwrXcfvQFpbucVS\nt/Ne4gUe6yesdSO2O8tl8dloX2NxJeiHkeEpfIkE2URPXV6cML1mL/aJom887RwvLV3SgIc3vltW\nutPRFvsIkKELIQ7NIaawhQQAHorPOozLg2adSS204paokXNkDF11hg0aTyBRN9LnIcO7X4bOuYWZ\n7UoLmZ6d9lQXtu8aFJn9k5FghY1lD3yQhLDmQoL3aqFpeN5zMyqoebI1V/M3xF1FkuevhOPG9/wX\nntB3kPKKuYkR4tWYgPaDhs0bR2aerjLyERU3aoWOgkzDCFha/26Q5PxofMNydGkQ9sR2PiEqT2d6\nMeU0sn06i7Iajs68RNVehv3udXzjN0YRYMkvmf7mmtCypC+DZXpkjLq+j3MY181sQ0SR8JYoYVi8\nq5kMVzHm/Q0DFhId5mK0M9eN2joFAmz41kQb3afJeRQFT/k2SdlqtvsI89vgZ5pRYR6wnYn+MkAU\nvNrZRoOjpPRSjwoYeHAcHEf6BDb1PGhjMN1cSSpwdTwsfGj5f68NVz7wAmQ3FRRhpS6fXSIG8lXJ\nIOqT+a+xbBpaTDDJGcvJ87L8iA0hhu1eKKlxGyYk1JaglxLE6CrRBJrN62axZmpyYeJ671MspDXS\n4UNPvgVHwuhM+dzfatTou+sbZaA7AtdXuRdGePlZmwSnW1CPgOU1CgJrS1xSUsrPRh+uoIjHkPXE\nLlPObISftkbEALo0WV0NxGZSdCJs2YXyMjN58vmodtnKezCiN+s9ltMSfWkkphfErN/Jt19QKLKP\nX9S1ATIro+cppPRGm7U1OJQ2G6VJs24QQo1GvCE0OrlST0kr6GkWJIjqVYkkYqBGTO80b4DXu5zq\nHpNj/xeGFwffwTUGwLudPvAaqrZhvM0/OG5IHNjqKmIKi+wgXHzeeGlEJAghq9TGccTCqsuOEe6T\njZJdHKpyxcjanRrB+0bJEG6dUxv+P+1m24uqlIwUhLNPE4xWi5MUX7vHY/j6RDUjixYbikTZSOLK\n2ddLOE2EJjkqlZStSo3jBIoGkXlSOq4EUCXMVMU4uiG7EUf4DQ0JyZDygVK4paovaNA1Z4Ay2Imb\nHmwZ7tzWOfOv224bOwCAhIX4c1PWEiyKXUUlsFOzyctdKfYKgKGxUV104G7vYaDfZ0sY9PgMu54w\nry7B5z1SDep9Yl3eiu+/Ss+nDk0vnVZ54hmDOMpLnxwb1LTzRdHWjevkRm8BHFa0dmoMPPv2lkyL\n3Pg9UlQnXPtBRe//tIWxlNBwbwcwXNV7Q13lBYQpFr5DHQMUGTSaegO45PmwxDoxBJnxQRU+URtr\nTdHmZm0kllsoZqUnecf1H+ct+atE+WdCSHFv+3/qkK0/ptvALfsCvDB3pSyj2u9XlkMxf98ZL9yx\n3pQZZGeSt96dSHHKoQIhZ6NWx7a1iCba80ZCrupNAagsPRMQ48cvr+e3bcMQaRR6ScT4YtLTUf6k\n6aSLwRP4QDbhE/+9DcvoF5p91wViuocLQ93FK9pHo4dO7ik93+9KUONstRyKqHh1jv/8ygfXlwy2\nBcFCLTAXEOKyZYZ+BkcREkNq2zT/o02amqFx5aIzPuugpHQEPJGGzRTmugXO7bki/UH+N+mkvNIK\ngrhpOT8qJnlyEepT9GX7yemWywxyjpkw4F28TS9qioOJGh+UEMha55Nj1Tm6xRnjZHn5PrqwlBtO\nmJENyEGxADVCShk6upRY5ZY0gD/JqWQYBhtHnxSueL86RrzyzgBx5fpsJdJDdtQOj8CqzbEAikc+\nVych2Mzro65ZAzBCXXesOM5pVekJ2WGXccy5jsHACZhic5fuOJPIInOndppfoAzK9u4XqbtBo2a0\ns/u90zA6z9PROxoZKKz4ZGCpUoBDQpXfk8Ww7Nx4RIZvZn4c3on11T3a+IPyJFxXcjucuhfza6x2\nB1NjdoU/eDsKf4umn5xNVC+RXErYz0TVmkXR8v54wCul3X9+IL/j1RKU4eImi2AAU5NGwTGrY2eZ\n0tyESBojpwMq2dwbF8JGhW+z/7LU1U87+3bAQY3romuYaXC/vxSYVeZM6hvekeQVNLd/7y5EQHWy\nxojzsuSbfCq1kPD4SwDamMY3/6LUPbK0eWfQt1L87LXQh30mrIu6NhhNHiXZ4ZwL+y7AqjJFMWYi\nVWTsBQiOoNte22yN6AK8zrwXNynw7/yq12/LU9sVJhDDvBggvN1mm89PdO7SNyri4V2ezzAYwUcX\nw9HRYR6dwoz2/Mr/2Iqo4ivFbAvQWhHpx09PvSwFIzh0on9T9chw/C1Ukaxxwk+98jKA8ntVw1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l0AxSCuL3D+X9t/vZXVkgpLRygsz07MPlEyXlmX2o66+yAVCaZJHkEi6JxzC1izfQb1bt2TW\nhLRaBM0VeRe3N0bjLp7+f5M913iA9FaXRQYMAiBRjGealh05cwRydiHaLKL4jpQaU1KRm24q3gZu\nfphM1TNaVaolGahM5tjHDTZDMN8rt1I8t5dT2P9z+pBd1CxAlSdKeiv/5jPkZA5oi7H++9sx35Tf\nhIt2FA214YzObXgLeCt62wABpVJwXgSh6JeWuKo/Dnllh5+vVhGwO1Z5NbmB8MWJh0RK/oCHeRhd\nBuLh49x71hTFUI+K6bTqFh6FohaxG4Y2SZLbxCnq2f8DikVqi7hwYMiqdeJ54vw3ivgZs218ozhU\n8oLZ1NF2kmHRo2GSK0jKNUDgHd8y3djCXGwVQwfB7xwzz4a8FXAR5DpfOLvSsE0lmgDXkigUWor9\nzEe1MplErazcVaeb3OSZR4TZ4hWGRIEefs5jUxR62RLAD2WWxGeuBMX8xNeNSSA2FFs2dJpjgK0b\nKL85zudUJbGKPZHradefclWeX53cqVcBx3bM1W9sWrnqvYHlOLJ86GUCfXWBOjdY2qP8X6Nfot8F\nw9+WdEanqBtdLPUPVBcWeHFs2OWi/5FC4H9eodpGnTsm2iAQXX8SIkc08LGwjH8WlYhsOJ8GFtYu\nfZhzskW2m8PdiCtqrZ6A+Io/oYH8jzEFEQTepnlSy1YerpL3nXnD4At1ruoVFQRjgV266opfH1wI\nCVo1jKOw5V64NluInd4ASOUdxWe3VlX0jpeeTD4TQGQcO70MShl4/ArPktDribi0U8rkBMECuJ7q\nTYhTAMSghraF9reVqvhODVdZ0hEw3swEDRSYVTG03bapT0BOc192eERiC00tvDG5dmkksNZGrq4K\nGkBHfpT6gJqt0UT+DTlkKb94SGOLuJSf2tl1h7WZElPr8RxFKtsnTlNBNRnQdaJQv5Amm3Nx23nS\nKXYE2yY3byFrVsUNh1I8Bpo8zS2xbC+dx8JUP1BroZszr7okeDO8frPsQ2qHrW3TSRIpzSnjXFPg\n4rzEuS/Dg+tSxoMayxp42xccRc6LxugPP2LYzikQDYumySQYmNzQs7ZZGMe9qEvkdQpBL85qCckY\nsU2qGiLo1nURzF3hGZyPyg5k+iRyTmpsB6/LowY50LHHsRYIQWIlGChVT/yHZdUROrQIcGKXbCxy\n4nDaJi8f4hKMfreB7ZW3Uiqb+dyw2LMHyVdTrHdlonjX8nzZWQhghmTIPQit3IXZiVzsSsoc7+EJ\nlsjsQ8tFwTy2uZsPKwUDoazkyBLjv+i1tq/a184rHk2nn/ejNTdQR+Rjrz6uxzDYQ4aJQQFKjsxV\nPVwlhsRWM/FRcY9QhZhLSHzbM/oRs1l16EPdgG+mOA5AtzVPTUJAgwxh2uchIOCMwH+Kk6qIzYtU\nHwdXMCQPCikdv+3K8/bVybryijjdsIDvMKDuRHfw5ELSKEms+hF59OwKmrTMyLXs25S2wBqir2wK\ng9FRVXQaXClGv2Y82cTm+LR+LLJ076H8tWe1LNe7u7rbeHyR/W4EaA8FD0KsUEByr8y3YqEPc3Va\n5ckWFFGENC1DsNkRQOFEMPmB+sYbuwmQghUfSiJkytq8YRPcgykHr4ipMpg7ThGiXk5MEDd+45ys\n4Fc6LlDoCM1hnftq+KUiTXhu1vENPPOK7M8IaDIMKRqotGuCZcP6II7ZnTqWapiGV52e0VhbR26v\n/BGcscGwFGkdZom36uh51w8+cB+4CBDC1TKYOEsv2SCUZ1DzYW/F+DAf1LiMrf9eRGzmjdMGDFHO\nMjmDi2fS9Q5lbYS2jlPVfMGXJwnrMprw9itysfUQXVBJhiEJ4XNr4RK4AhdzVJCuNIoFxWnu3On4\nsEWBm62aj2PF8t7whkagilEBEKNgT9ja5Ys80wm/KA+0Q407bV+aalRp487YmOYcsZUhLQwU0mFO\n1KKUfTeEyPUyKK0ehVE/0D2VIB8a12ubCa/rKu2UhB/55eJECpzCQjNjSQlD/4sJ9gFiILmPYgAN\ngWWq+v4jSxqz6LDgj+ZLxC6Bkq9LBlhYbqOM58SreFE21dAm5npIFMn/Z9C4VlXDpJv1Rd+VDyZx\nQII5znAg42u5VxgcXytOpbx+unptH03W2Dl5Xm6v0a7CfASu2K7JwbkpVVyfsAlGLlL70En0gTer\nZplT1nsUILGmK+m3EBNvmC3I/fGzO/ENWHSpbOIAfgrLJlv5vPTAJsjJ9qldnObgf3YiTuKq/JTK\n6dpMOyFDwvjGz2U4zP7cChFl6vqESZ/ZjGlw5C5mdF7ZBYVkjWphABAwarf9IRxKKNgMkuLXunjY\nOAy5l/h/5foMyPaYfL7n2CcwIA9it2/4Ct1JJVq8bQVNFGbQm/BNCqDPkPAcTUPFlh0mO0gpqa+O\nw9qM+iiFh+WzTorI+PUxqOB3t9dEoudBIMNwYA+HhCMborU/3x+cxI1Hr/Lgpo7qgn46TBkfA1l/\nv+83b3BmMyEdO+aoMVaXTjyV2x+13dnyOfA8xrU3SpuYC22ZPNNwvyvU9g9bp68BfdQGP9Ku1WN+\n2zDACuF6pKmsToddLZKu/uoJEnbhl7zctgKjwSxmOaJ2fZlVb5c5PgUrqWDVkSQCSXJGDNTpg0Ll\ndYfkApadPuep0gY7P94xAvviiWo0bktoV+uYSqTLd484lq6T0YQU8I20FVgFYOgdpchcF0KK3rQK\nR/GglU20AshD8RhaO3eX7csKebD0jbsYC2hm9pMMXica+v0h5/JGGLHa5QgxpevfWP2Wp8Nvy7Jv\nm2kZ3XzbWCuYcCYDzoLlurO4GfByqqJ9dZuvH9I2mbWvpwQ+KKvKJ/dihrulKAUpjdnHK8kaMcVA\n04fQ6VpPMPSiKIDvkziQDcWiBrZ7zWbTZDkan5M9sbLr/37RL3lT8vTmXDxr2XWUY4+qHL7t4rQP\nnyUUwp/T/jol/TU8pLKdtXi5hs4wH6HQWHx4K3K8hGDmvs6vq+adInp74xZA4zRJPWZYHRuUCrcn\nQb+z33QTY3YsV1n7DZesk3lqyDlwHCZuVDUBsWxmdNUO+3H3e/RM09SpKUyElFlazVua6SFDRGdW\nm6THHVGup9kmc0SDBch6n+5NuJdleizqjxAUzKAHGw/QfdQ7DL1aWKZd70daLIlxd1wNr2roC5kj\n5MQ4rosj1YR59+tq5pS6uHb0P+6kbDCD428r49yVKplLoywRq/wOzo39IMiN4Oz6Vl9lc/jU9rNe\nPBzpeKwx40J6yLj/uRSulPQIz8REczEF+R4svCKkUW3bwY+m/lDVHchtFsJq2umgjZamRbA89uuu\ndyDiqfBzcmXpuccPwSylYEQhJEEK1wMzHmJLVsLoRp/LKbMUBnVQ32PpoolqHmRocz6tP6kJQGv9\n1C0DHyDhKDbqXjvb8F7niSqnGkAC8kZrRNCM5moxM9sqKXEvtlrMd1SK1MvCd9QTFW1r+Gn3OxwG\nAdFevzhINTuNmPam2bZ66BKnO7ciPBcEiO5d7xg+QZCm2NvpTxBr3hhrJjXKoOTo3HYWdsMxBpTN\nttbIHESe93+PoJSQqF+QZJBWCZWVNt928HSGQpdUPe5rO8uMnbKLZgsLe2A1yN1BaglFncZTWNnG\nP8Sc7+5eEfl9OKjOhjPjyHPVZb8rxzhF3mggEZc6UOr0ZIbrLYXKKt5efDnqWRxLXG2nRoN0UuZy\ne7MlsXwuWsQNDwd52Z/40e6urN3YIrYy+dv0AdHDAYWzQC/TbbVMTXH3BxQfHcfARYSdLdAOABQI\nzyagsHvuwe7S2PWkjGkgTRNra4cHqlRbSBF5ZinWUPAc44ccPKPvRQ3q3KMxs3PhX89L2QkUp0Jy\nA7P+0LDTfz43/QAGYWj5Tkcv9WWCOk1ENsJ8qmaduHvwxBni85XEiS/Hrn/DBXO18Q9kwZL6Qk76\ndidUWAF6w7lSQz1YxRqfXNDfW+Z2OffXDXvhRzL4SUe2u0uXBqb+MATL1/VE1Hzj28Ba5Z8lXrMK\n5wAQLSesoq5TFet/aaBDZM5tJ0pQG913sGUf+7DEaKhkcU+cw1JwqivzBT3ewKQvHP9URqeALfwX\nV5FLE3sqZyqUcrcIGNmLxFkGTkrMy5A8rU0UDyViUhmxPvQQ5H3fXSixWrUtiS1uNUILoDCW7D5v\nDPvelIl4S2cpXMGIasZ4YVNEgqr5lBa9JasG6/wIFA1GkGtldUciC6AyNgvFIEGUWMP9VwmrCKaO\nLxsp4DrcgtAXEI3IpmfgK2J1wxIHUy8xMk+xbzA9FtiFiSaHj9Qp6YqdiYL9obIbBO6yIk4mS5is\n6O7UM+2VSFXgJzSBJB9DUZKecMpXa4n1G3x2JEkV8waVQWIPeR5xBucJ7+pdXVe0QpC30eJ79tTn\nsxJZn3iezt2Hw+DamkJv4XTC/ThM4npbv1EkDXO4D3oWK35g4nQznY56TxEap53kxQ4lzdmKbVbn\nvp8vz/EM9mP4vb8t3F2rNOzsMJzsPpRZrievVXOEvJfXXM5pysryWSKkC1y6ckDFj6TSE5TmM6l2\nbA3RdlgKTwn0uXHQrwRM1EHuW4zKhSxT/L6D/sn6yHiW7Cb4aFHFuYwzQWqhpPcT+UCrKf5PBopG\n2mdOrasqtKbVQUbo2ZuZQ+BJ7g0mjYMIkZOdRkE4BuGPQn88PXZdymPmW4uGawvHEQeWci9/CtrB\nG7WJA6tWkvC0dTfeofn9KgW+Lvkzea4faDFUNBSmWBG1qVhitKoRe0ylkBUMaVbZgIN6ACy6KgOH\nU+ub5D7WkywOT+oxcX+oFGRovRCtCD2FZx+92RvVITSk8rc6xsjC1k6ouAy3s+mlOu9W3ttDJcuW\nimCwNxrbOOTznnnc0m0IEkxYs07zrf6TFPnwNSPhTX6erGjyDbQFzlEtn+k8//wbhETn78mJ0mlh\nbNEUO6qtDi5PvzG4P3erY5InneTuppDhzvzCsP0zNpAfumJl6BDA+MVobb1B4S5QPyeQoPeB3f3O\nioHKh9sJJjnpgQqmloAMYX/B7Sy2OmwcuZ6RD9ZlE2/F7PyDKUrIuuVlVdWDstzpCNlpIuz7JCPp\n4raGXKTp95ZcFo43xLGxMxIXVH9iLMkuANagT+Pe1++Q8PScoVJYvD8HJdSKGHDnA3X9azJw131U\nfIhTJSJpwRTBKKtVtrI242mEkXwqT5RD6+ORNLlsGYsIVtr97pi+MTysu44TGPXpCFCTSr1eSqLu\nbPn+Xzj+1Ft5vr5U6UirB31yYECT+977ruJnXrWv/7dl9nPU22+6nbWyk3ptelI2+gOlCPq6cWgX\n0Zl1tBZaLJIoKu8wHxrAIn/9nUmrZNTGa2Qw0zh4f56VAy2sifi5WLESMlFTri3KMTCU6bLG7L+L\nLHKoxH/7J9niovcQUH6aesGlSAlCMO+BAZJIJYsjIUdgsvFsKSGut/m6x266ci+sSrSLqnylR6O8\nhx8s/NkV0zOvQqqaIC+BgLhLW88d3PjXC5QgRQX8xdt0Ca41PiZLiQ/aI03S0WpaxXKculgGxeGO\nAlLjpjiNHS8XBZIFd+C6+rxdFyM7Pqi2WA+8lpySFV6mz2HuDJn2pnKXGxbzqn16plcNsbiI0KWv\nXZKZvO4S7WXLgy5ESfTA/Lw7sosc8zch/Gxg31IuFXL6GXwaqQteyl5SRO4LV/IOFFblq4+wIeIe\nxXVnCgrnqKCgrwLP6SoTXBkVAXsEv5GyGv29sio8ss/OS9uhOaIYB7isUdxAxih+v+/t6JoorfLE\nT90pxK/qPPHoalmh5SE5y1lRJSOVrAZtUCGv8pdi8KmB8QA66/jnou1tHnjDj9lkWvi/hq9ANajl\nsb8xmMRLM/ik9CBTCIy8+pCnFb0RBG9ApGRujczN4FhP+hygZHdwYkYQvnyvR5zn015XFYY5s4hN\nqGmGSk7BUfuOTRfAq+vq+/4mnDsetBl6ke2XIswSrv7c772hUNW7SpqCjNwOxK6nKvo7UvuiOz+y\nMgnUfjYODqSkVWhvI+VOk/tuCaIfllYVDYEAPoMk0j83MOOAdpl1qzyNevkXLKLACPZrlnVKfhBA\nu5VKiK0mb8XYxLdQlV1C7hRi5VUxGWctltnsXnwgimgW6sDtiBusI5Hi2reN5MzQayFIZpArnCmZ\nNqfdv/wSEA4PzKLayxRwiBWaFH2sv9+CIilHSu2b6BvRZy8cG9sfIDpXySwRGFgasR407/jD2rHq\nLUw5qOxyX5K6+yWC8ZI6a+KGiZQqv2H4tPqCbOca5HmoegaYyaTliYmZITDRAD2UvIGDiGzq93OR\nA0b+qjGXHfm6CfRLEl6t4zmBiewSjMov6Cep+Wfhrva3/zX/XQBn7q9n6xOYaHOBoFyS2WYbj0VI\nZCLRzh+tQGNbF/aP4BO8D6kKjrttLbS/qBb7BsToeBaJ60oKNF7eEpr9eWUFq+tWrtkQRABClNJI\neK3QyXssmEP+y3b7MI3v8k1NDm7Py5uE00TNZQsgStm4E8pUOcVKkcj9rdo/sy3rT+F3C1jajIRW\nLyyZIcXq0zG3JqQUAj2omUBL8rV4BTS4OKQZ8YGkx3LYNYTV9Oc7I5B7Qbu3xtrfBy16gXt/9EQo\n7fH2iU+P1FB2vi9/yEToi5arBb+JXuCeUp0KNHulse0jEMzabEtRS9PUu+Scp82yDN3Q3rtHNgrc\nTOia8+XJ0oRRF0Gd58nJkzC+esUs/EvxkDJze+LQNNf/Op5jfy54HbzyTlO6F3CiNxfMmK1xOKJs\n3VN+OslBOAxaaUhvEd3RHkSMzd5ek0VGLiW0Wv1DpWshaQ8XPrk7tcGhr4jT8EGnRtWFHASHVsFd\nWBuenRUxEA0F4XO8Hh+mNYr0qfpOFzEV8yJTL4F1mQugCNA4HdoQtm7dGvO7hr1cVwreAvRAF7x3\nZ9kNXwxGI/ofYQ99YdtnqwjUzHKoX7QnCteqBroyFsLPfQWxUuVyjvGTNo9xg5unlyx+3PYi5O/b\nacis4O16AS8tf0kvE+oqdcsTGhwljr653iG97q0bNxpmOYDcGNLv9JxtgqrDTB0TAIJiBax5K06S\nyDPADYlKmF7KON/M2mRL1adHCCVh/1UXiS+/esqS4gWNYmI/hU0/QxhSmLZDq+vYkuqiLusHsHYV\nub/iH92EVrArwK94D2KPnJmmubsq6lnVCLLYRTSc68y9CY1fwEnULg9QSUN6ZsEIcA/uofaYtW5C\nT6Yrr92MRlLFZklHvw0f4wgsH/2iy7qcP2UpJpdZKoPz7Wu4/EwoGCHAg9ktNBtr1B+HQR+ACx2X\ntbc/luzxDsUU0TqodPIahTB69NKrwo5KPA6+4qLtjcXgfGGUN9n6Hfw9V1xBbCZZLwDovZ9rk3D/\nkAfIGh2hPc7CWl19CYkQq2gy6Xu3DDhOEVYDM7U2HjYpCrL0Q9lXN/sesGqI4HQHEvwufvMPTSf9\nVGyBcpuXA17lJAPLP8LMzAUVdsqjgsY570a+qauudScLLUi65RqXS15CjIBWAlmjx86gIBq8Oj6Z\niJaz+hegMuLPxJcQD9V4U0ZBY3V24KYGCR8RzneooDAt8s7qW2g6zhPX+ftMBWdLlcgc+8/TZ7Uv\nVmJgn5lTvxMPpqQxaTZwyIJxD5pNNuBF5HdLx3U+pgcwsc1Tq0h2KMzqzjR2swKE7FXHDt3WTSsQ\nAAYfLXj+YdjJNuzTcbwz57LjTEyRVaKyiGodyg5Ww+yun5fSlHbmcuNrSiUVO4uwLAudZkskNpTf\n9lfOaPg+TCwqWznbqH0gXQtRsYQyXdGJKM7WOjtkW16i2dssiLCUSnetuM04SBy9lhHyA3dd5jXF\nQzAiZ4EHFfa8ab38keH1wyDPKxlefE3Svje9IT0ckhcmmrqNfMEhpX8ykSle6OnuFvR0MCf+yXxD\nsZEHy9didO0wY4b/W4LZwAOpo9w2ms6XXN5un1yH4wOgvPmEX0koyB9dVlwhZRKVyW4CB/G/uuXB\nrgDsoRCM/p4Tq9b0AjpFVwyQBy1WT5l6JGAo9jRXeW6oqacjfK23D1iF3by0vOb9K66xnXTW/0Hv\nDBr0+6YWoNP6ZHbcC728xFLTipfgZOBTqnEkoktdgdT3CjrcwehUE6wAaWzrJTFnV5L0eOpMb+mH\nI5DD5FtIPQgI/OWi5BGIEB6KBws0/4Ss30fdhIhzZkF0uDfoaK4VzvC6OP9a28rcEvX2mdvZDwwb\nsHLvwoULGeK4syE8sJ2NqqK0CTvrNgWmct/fvDm670Ub+HHi1F1u2LScFeEy/5o199vM7cvSiMQK\n6+7D8b8q2EUMDHzExG+pjbvIbASQ2Oq5DLDv0qCco1M9kJvVc1l03UDSovAYLKPYSx9nkZFDWjTq\n/8Eod11anNvwTMU51eaIaCxAvrvObLWMDUzEsGIqDmvwdnyo+uj3p5Hd7x0Porx8BAPvEir0tjn2\nHZP0lxGM5zfjyqibJCtbGUe8QUHU02/I9a+1wi/u9uLIyPJtRgwKYchkgSJiib+H8NZwlaqbKtr4\nKLpf8I/tTiLs6xfa+KAHpn63XChS4QKzu3o4bFnzkwqTq4VzKH2KJflCUSEIj4g3/zQVIPBam2e5\nu87LM4gQJHZ69xbQr9+an8sY8QM7l8C0iX5rDc4dAGV4tAVcRZgs3Qt3fZA6bKRUYLn0vVe1xROP\ni/eXVJNpAzLKLwtc+de7dZk9fyrkazU2Oswct00lLWn43Uqg/xzzI4DKL3qKq4kHatvjFLhMkcHD\nXHduL+RUdtyHPYQaUW23787YaSBz04MCHJxFLtDG/gurnLMiw7wOJfHFPCPLZS9fFQ6JSV8rCSqa\nlik36JyDNXXozotiy2L8tlGScrNmDzaYyPk4J/QFqkTktG0gIHTHP+wrnqTQ5Cs+suL9nOkauqoT\nmHSuurf8Kb32wXQu++EjB6mmNCcA1MgwDwqQtU5VZMxuuDDNxSyfcmTVjt/jDSIFzBr3gBtM3VMX\nlEK5rbDfBwUFnkpwEPrI6XRlSNugfs3GP0MfMNsNu/mrd1pBLpgy+ob2DVqmPAc9ntP1Z9/HuJQH\nrN9F2wGUoSLQTIRWkC4f9XZfI2cmfaWwJZfZiFc6aehjlRoAJgWK/poVUm6fZzWeVayXtgrZh2iq\nehukZD8tAD5vp+q9CEwq5J7n6Wfg/pt1I23N7zn9LwvFK7813lY3ffgVS/6DYRxC4YQaF4qwtosP\n1arJkrr7txMkqr7GADGzaByjY5QTnsOhsK41H6y/lfhXcQFP9ZAThT3FJ6lzN/R5Z8BWkJzNo3bE\nFeGJu6WhEh25Y/PRo4uFCaZiBolJifE+cMVoc6SMsrru6ycLJ2q1yQ5C10K7q9At3S++x8U8V0jM\nphzfM7M+dywIHnDa28oBRyl9gnAuegSOrrfydWZ9xUf/WwtTfjxcQAnjtf8R+9WLqg+uvXDQPeRN\n5wR9l4ZY/SyBDTn67RJfH7UA1WE8nI/+b016adi2vO51ruybtBFVw1FNtxacX13hJnBb4RsBkpOS\nrAt7T/p66ttIy9NkCkWuO4wcDIJKpFeph5R5Df4y9JHBK3dCOgp52FFt5ET6DnyD5engVv3Yefe6\nmZHAPp3LjotWFK0flsUaG2kxUJG7hmRvNFCDtW/PBJHsX3UEUPZNywzez27GMP9togsR/LJSmC+t\nYPqvmt44UmTFdzQMYCtkfRPodQ2rJdnQ+5OCX8KX/ptJouYGzrrcyCt7QPdHgjU+gki8ZJcWP75e\noEJXFYOQqHFK1IPKmaOmO777+esIaxSWKQ4lDtwTGwqUFCYjecRI7GolWPgBzI31F14V3v7VzEYa\ntHzX5xAP/vus1iUnW5xBpOi1ZFIEUOZGfgEXlhh+6kaOyIhGJ7rfH+hKsKM8cW2n3RV9iTjkrsVx\nfV482TArpalACSj+tU+sVswHBBwXMZ48+G465wgL7nJE0AUMXn8VFv+UhaPVUZsyVG4aO3P9WBSt\nIDBFGOzjdqSxu2kF5H9+zy8SxsrkAJ3OYUdy6TtswXpBd2DBZjZTRHRjT5tHgInU35UHV520Gwz5\nLRjYc328mXRX7uXYfqS3ykwe2Gmhz1PW5icwvdLeJa2Ja0r8wFMSHqausxDMT93A6/ph5OMmSHh+\nZEwBfiTZx390FvglSO6rPp9hFoDdPXnQRXB6CJnz+iVQv3Svm2e+1MZJ1QCEB9Xxi74qMZXQkqGU\nnxf6itX8hlXde/60HvcPxp4c7+9ZxuSpQAAqvPI1I3tD31o+wWrJcUL+MUq2AFLnyAirBsQ5B+V3\nYG7n6Xg2avC3dTkAS6GlbSwsbqRJX/wBxlgeB2AaRBYeQqj30cjo5SWUxIG8r+IXk28R80XJlDJS\nZiHRyoOv6HFZ/nklZq6i/03WGDGhWbnHZSE9GwivOvVNYdTxgknxh4ybEBlehDi+DY8NRwhmnr4p\n+Sa6WQxl4AlVE3z9Gky7FLARcyz72K6yf9NxjO6lFQljkYoEwpR4XPm+7jNYfahMl6oFV/mUblqg\nyHrwsQU0f5UPw/qb3KtsrBqrCYmcCZDzxwN791kh32Tfvc77U2bng2Gr8IoaMXxOxxMGNRqLCrxK\nQc121F4nzckmVz8jIJoB9a7F7+jMMi7w4gzig8V5+eUdfdPwiLrDSdrH45ps5ijsGDchP+qt4uwp\nO8ydQvvKntV1+Ve9iNsfRNs8puUcnocAi69ULyhisezgPixeVpH6Ws7sb+VPsOtcZV33L7mZXvBI\nSXSgARD1leJMHIhfv6Km0JsHWflcKFgKBj8P8CG9tGpGVZJLeqCdyijlZrlmNrMhuFmExwWfcv+g\nWjVLt0OdPEl499vBgK/wkmAZ37tl+Eyfd37puZrETY2QFYedrJnWsss3Oep+baIBBBRmw+lovtWA\nBzsR2BZC/DujHdUwyjabsP5ynMVvNQwzwDKBJC28D/Y17DCHHc/EhPv9RAhzz9CyzpJXuR5HB8GC\nHQG8aWnWuxRM3uKNyiv7BPXdHYV8poIPbUN4+oieE2X9ISzWbbB7zP65/BcIz/J04245nuPfpzcl\n57/OocJcVavfi5rasbyUWMvZysxbwG6a1HcmBJmCMCNIEt/Shbj8Af+t8ED5fUKRgK+LyJlugOl6\nRzBS65+vJILWU1nIJvYA53e+1bSpHVmQDFT4spiSa7HFGQvvE5C2/QaZttQ42upGCvnBW7tOq817\nfxdyxkh0skmunjAjWCapQM4RVUNrJ+vXo4EvhD846Em986HdOYKAEmlPNtMrFecx6gGT/uAE0WTl\nhJfPHZnHh+9Q7jtqzIZt5Hf6NUslAZXOAe2cbQA6lQ9UGWTD0KIfcVH+Pswk3JmNFvQaLnuA0Sem\nLD55QJW3p1RkbeKA3Dc0ZL4pYdTQ4k7H4ZyNxK8cIbPqlMaeqtgXbsz7OwZpdvOVBgc0Nro744Go\nRIak9IbMNk0raYflZy1yqaFqs0Qy5WFp+5+Z0bnpUHIQa+O23P8ofwUiIzgiNMf0unmG+2nHgruh\nT8Dh0SBVA3XddI5l2m22EE29SO5uzhfIBx6qlLKhyskBJEwPoF+DEwjrk0k9btTWG+p2Nak2UcPQ\n/5UFRRGCxotxuQEwiAkBf7UDq8I1Fkbm5R0nWK0gNYlLOJVpiMzZt5kqHYIYeDq6Cf+bO5kVhNc+\nrYvtZjTmpCRFhmfplrEVSWnpDKVPdS1GbwHWgpEfTV7aDeKuVOzoftBuCYiODLQEfE5oxXbXpC43\nEH0w0tTI3ltI/vNWr/+ewtKpEKklHM2Crr5aS/+dH/rqoTABL9WFveFahIrmOSPB+x5vQ+/QLPir\nSoMmsbecgitQe0/48n3TZQ7GBff507ifDdj1uwovC+KaLEAzfPIK8Kb23oSb2BSQXo8WqWYv2a1X\nEM8Pxv2X+LPKlTRrRLy2HVnrDvVc0hTwFhv5mA4RqQMSkbEpLyLXNYw2wP90f1DXv31yMtKLj+fd\nCWTXFvO/H2BHbV8QwgvjEhgwAcmmMXmoXB0KddTJ1u6lAANTE/r05C/CcbMLpvIO55tv42SsYRme\nyZn7O2QKXojqbRbxtm785+dy80Q9ZGvoB2rgiu329yvNVHm1KwpkifG6yeKC1hMaXb3bMaEH7hFj\nAOxi6AchQpv0bK6nvW4CqBfFOZVGOXudk3H3tmIEwToZql+47rhf4XrrzhVJMOO1ntEKBQJAvtIO\nIV974DK0bJ/NUxDCbLKSmk8W+B9JHZL3QnOf7Ii2XfVCApnJkO9yn1mPYdrVUNDFoXnTwG30Wqcj\n23H1H6JvZF8cDQApf9CQY7/liBM7XD7369HE5qEyM28j4KHobgzuHEcFThDPmHNq2f/OLNMUErkB\n/C0Ptw//28utQ0aGdj7kDYIbE/FBdgWFC9bLbFmcOQDp/2fXA22mJgA8dxUSuKXJMvWXcyhKvQtV\nTC/nu6FkDND2qFdy4yOEc7FIEH6f/50nL17c8rWBdCpF6/FdM6/6L0dKcHpdiFQW3rcyMPNODfXi\nI1/b71wXCuAXaKsOU0C82LcVSalnldxWe0YLPAjY3gXK/d71F3HF+zwCfnyRSjZSQvD2ysaIpQ63\nyMaC6ZrJkVPJLvX0nx04oEHw7F3fX6wlNLCtYFjZi0W1KDN1ej1EdNE+Pz0Kvhqp9UsUE44x8GGq\nc+0pW5gP95ksmz4Px/lTasyaLfIsw/69knaourcbIzmYZgvgdmOahWYLDG5DloTMz9SMZIpxjr+p\nrN5ZeoHP4EUerb1bEPsPvWvUGbOS7JGjmIMq8Dyz3YBoM9r/5+FMqnd5fBfB15AJPbe5xsy18AOZ\nVlDMrNPN4spqnojwoTTamk5HQwMmaZgz1tHrGSUultzdCp3m4xv/4mqM9jIpPiAcyHM6PE4YzWPA\nf/9QS8e+oH9N6C1jtwPEcsuM6uySZHvqtcj7Bm7i4r1nbqGVXZmDx6ywN6YBUzntL1UDczILOue4\nrCxp5cRZTG9b24Y091wo9S4susQSB1IeLX7qESyFbk+Achr3JHkDAt+RlBZ+kexaLrHhOpnzReFM\n5FFW4Jnh/rGJOhZDMLVHE57BoNCuc6+cZVVcmiP6NBvD0oyfE4tUzIqETFdQ1AfpbrD4NUz4uxr4\nxGZKUTY22vdPFuou4q47vN7LkLe7IrPhuLASG7Arcy7mQiUbhHdHHofNeypuj0zRjNhhEDltVFs+\nC1gcbcrUQyq4MTYrLX1RfQVYB3l6hif1Hx7E4hbg0IVLzdyMMBPKd91kiOkpUgLwt+iy0f0nGO8b\n7jqwb0S8t06fHKEhh2ERbbQeLavmIjfSF6XVBZnCgdT9HiNV4ZCHaJ092zUj6/ba+q9J3r2bT+LR\nhOmwQOmXutRvoQY7V1QMlXglNw19Y2/EDLENDsIPicWniafCcEMOrGihH1qHcK/oh1+iPTcGt5w4\nEG7k9+TLj2NlGrMzZFBcPlMNyV/mIkULrPhIJ9Gj3umXhpbsdzH1gyT9VnTZLWM3i0EBn76v9sqG\nGu1t+Ax5eiJcJ2Je91lAUCEeH6RB1sJ177GzmdOujCejfVHjmlLxARUifGnHBu7jH4TX9w8/sWCH\n7/lMLa/aGGjra1j/CaWNftjtFprk/Z/EVT6b778yIKAsYPMHF2JFFZ/ocfHaBBL5cH9QSBijxGus\nZG0SwGAcaUf1pvDaWuXKjZIkY21/4TCWiCsjCD5VzymaodARygAbI4CM+5KkbjpADhJAGDnrr/MH\n8heR6jfOzc3CQDeLREyV1LxHFs0rO2pg1qxBC4JP0vXqgiXIN9IuYfZDxKWDCWilxPAtkk6+MDmT\neqoN6Vmds6BNxVC4eIRdcXer0u6RtupvOunxDKMzMLUWhcdC1w79fcgpzme2yiCKZ8tzvRydxd/m\n1h4tQIlqdU/Ce5e9JtRVaoBvBPhx+RqldsvkxVh03SFJqbrXKd5RyzgKDKe8QIhZ7Dq80Hhq4Nml\nAJx26LVdtM7pQx4tFz+V/4hau4mfAIzr3Oyv9t2FXaWJ/3hRy7AYoVfc+le9ixTV9rajLmu5ZEw+\n6PbQfJEo6RZqrf6ELwu/ooHjIphZLW3mbzt6l3AducA6g17I/k65EQm3NRpbyNvtgsMX6iQPwo3k\noXFo9uag6y0XOc+rwXLltwK8X4g1xj7q06LEdqf2lae9FzqDHgcwn32lSnoGctSaV3MhBPjB6GaQ\nIylTi+rHWI19ENLPPJ+HZopunlryRIMUkmp+7+q/X/g3iFLuEp+8uW2LWErNTM0GFMTc4ZLlsCSE\nUBpp53MPsEEuV2GDDN1Cp2UC4xqMRE97s0nMMQFmjXmL3ucj4sH1asFxh4uPyqbKOwKE4fh7qMF8\n0UIBbxdnRaxu4DJlY0mv4osriqatOawpcn0oGmRAWcVb/TLTDbedFJjDbIDkAvlidtzrENYKYEYS\nj06ZhqXlsSlirVeDwW/P1yDSIfgqYCVPg793RmyE8dJcb2DN9R3l2XkHqgVbU+aRpv/mTsjZEvUD\nkfioWT4l9ncp6ZdwoD2U16BGn7sxCAV5eY56CeBzUwn94UE5wm2ITTLnHIrmvEmAxC3GnE6EdKRH\n3TeAj2nxjpk7BIDIc1rA4n6IjD4cWKjw/3htD/8IbX+yMkqx2ZzHeyv+mJgT9bu28DfzssIWcgMM\n63D9+g7zdTg13zYtFxiSH6V088Kd1XEmV/prfjNyu7VB8MpmQW7RZ1BmFIgjLbiLypeu8LAQGKRC\nYGNyrTpyOgLeU9GVITtBKjUrt2l2ETt9tbwNLd3M/B2dO+7qXWbqWcCZsSLXtVnaBrFQEmrgFWiW\nR2CoVnC1SdRFrm/9arjLOsjZeDnTV/vTdK64uxHRNiwDjWGp9ehr7jh8zEuLOclGCIqKLQAFSVGv\nn40ZcDN66igoB6e1fcxcZxf1sbWZ1zPghqEFPTQXXxid4L2QgOVLDSGEltIAr5UdE/xP9teZT80z\nOYOe4BZBSse33+zLIp+FOplVV0oOY1xTka4aCzPuOsq4JdiuE5queZHst0n/XijRGerDiYvdN8N0\nS11MxF5+TZfBWfxHzK16S55y38MHzpoGONdIdvaAnJo7WwgLoX54zkuJSq/lltyaPscM4A2szGwv\nUHXz49uEojRhLFJ4i99U2LDseDGzC7ZFX4bbeeYIyaiqQfx8jTMqjI84TSQf5vefmJr7pYD8SzlC\nPiBpjBlodUo3CD6jqxYO2bHGJ7redl7IO0Zq/rQZXMzz2eXtK70gVH9EBypenpbAXhRivklywHc1\ngpcPCNsEGMEKtTF26MJw26RyWngci+HId09U0rO8CTtol09q451Nmink8XaQnsMNmRw/h95cEDNd\n+UuGjNhNc+lP5LXv62DTNOtEAH4GMkkOmYpp/1guGD6ugMjqbUF/bFweOHdojQ3br/AySlTl1qLM\nDH0+LOmxVSuf5rAXqjX1w9ty8sNXQD9/Mi1JXm5XsBz9ZO8A/a4h/9/iEkxMmfzp9RQga+5rHmpz\n/2k7HOQM1lnMANqX0ikHp9OuAzCprf6C3qBombGYRDfx00XfmeBuyyycHySpmOcW3RUMsBJoD1et\nRDh1Vm2LBphIaC8xON34ph2BFMXTkrqRR9/qkMxRqULBnwlF0MDVZQVO+b5qwHdq/lv/EFh1xWr1\nYpBbPA06e5nqpG0VEDCZVdmFtRiZEx4BW43DDtVwG+sr6YkK8udnqhaXr0y1Z/nWFsLQoD57Qb6J\ndb6AL2apBtKHzHNzqF8ZmRdjL5VGcAdlBdxNjmdYjOH5XxUsy+dSWRI/O8FWed5L33QAwz1zvcMi\noaTq9RPKQSexvev3YCRTL9r5vUzda4PVYBj7XeZfbMy/Pr3nrWy9NW0ZlGT6sEq6EpmnnhOX0/PJ\nXjAcFnz3ylQ276NXZHvU2gPnBxL9M48T47IAF7Yy5iEqDAPNxCiMCqm/P1K4wtnG6iEVuOxuaJTa\nUY9bFWsh7y253OaZaz9clskM9rkVO/pvkTB4VZnirsqCn84M1qY6AL+hwDxS8NiLOV/NvLYJ/fA+\nifFsD+hIClp9EFbp4Y+sma/gbwO7bdwFFIZ2nLmTk8MMQFX+/Bj+bJq8/alJNiJgECngamFY9qXP\nMd4sTytPI+mHQU9M6qp2ReBQkJ8ktFqGI2E6H97FzIvwYZSGxhvf2gElrp1VN2qCkazuwvPM06aq\nUahWh6pgQGXhizaBl4wM4z0xB34EFhzPsrPD8QESzFWU6nnsADD0dpZNzXeTRqJLBFp431w2rTCD\nkVUssncMSlvwN5G4nhn+itAClyrQ9fvaD76XyGkjqqtIkU6ioUnscAQKLHz2SJQ6s7S6xsHmktEu\nw7eJa8rlQzUktEozQpM3Bk/QPaAnr2zdluvEwZxWsBDJ2Zyd1wbtUHwgMb8rI9GBNrqoZy4gW0Oq\n+aE/BGF2mUmomdCcbYIFK68OaNuDvFQsUg2xFNsr5xjIDtkWCf2MmPS88mssb5rZQi5YWI8BJzUd\nLLZAiBn7M0It1ZOrfHxBsxyWvn3nbGjKnsdGWjOuGqO4PPklvSBMjf0AAXYI8sVkckOeYm9Jv2DK\nCdIK8/VjkIlW+DZPGGCKEb7dMiZvpFHCMCd4HceBvji+L3tDN+xgTaaTFNAKs/zd38ErH8LsGJHm\nO4QWAqw6qDZaXBcPGGwM+Orhlj1Pbgzto6mDXOwQuJJBTQHCgolj2pjWV+F52jUpuzyeHBbwWHxW\nJpJJpPUGr4xWT68r7Id9HEegeIq8XFErCKAq47+9xb7x6xmX/k3+TTBnoPgU8mz1MlmLACOIdmDq\nwIzEcxtqKHhssXIGymBfPERxTHUwLzYzNeBL61ht0BLGXsyZkjqySPQogyyol4K4GEqSjd1JxQNs\nilXF3VdApKOvtTaBCkpnc/cPMo4iZ2NK39peawPUhs86ffMRIgk0zdTTx00Of4/jWOAwpqEb4CqJ\n5XhynJMcyOM4D9WRT4eVEI2WqQtv4sb/9YNSMrgRCvKT81oBy2mPFDYfaBC39s8+WfxK/zgnDwZ6\nPJnV0XaSxwvefkj8yRGhRrqV1mxwrfthglW3PSkLLXnxrwKIyTtRnAF5DZ0TRJRh+i4Vhl69IwrW\nE5aDKeS644mVU8QT4U0PQ96vxXjGO6hnHYOSre6LqacNjcyZDL1ueXrenuwGZ15RZdEBc8yBlBSS\nGkBQspwPDt46PX6LHLYM9rKLtJk/Oj8OJDR6MD9LZO8X43NoIFsYZUx7CxIqLT1uYKV0WXB7HEkD\na6HWFfI7PoFmBjJhOJvjrfxuTVwFPJsviWaRBY7h5nIPaIe0Fe4xHaKCWBUg+cXvqL/yHotrh/Bp\nM6gqytBM/oxoFH9+2oWT3EJIRMxmTbtweWgyTNZmb9CyyBzdyXWYRMPWV9C51YrE1MPk5vKQQPRa\nY1p9jS5xsiNBXaL1YOdnuFiBeengWe2FPvJDBJDDexIBBQ4EWq81tIgRCbyv7faOTM34k2w3pgqk\ngG4UFcOnqxDSXCOxeOrUbPbjcIvs7XdX4m/Ip63BAbvFqsS3kZuDzRPYT7flTS74ZkXMkkehw68A\nu72XawDrwiIaWTgvfrLggTArVmhBfgVvyeuMMXktjLmqMH+ROFQp9Ob2bbHSJcBx7q8gCyKouIag\n+yf/ZBa8tQvNKRaSqM8NBQblux/S2ho06lFDIVSqjKdQuJFwIQPDdb9NueAbNuiQQflhMhOPm8kr\nt7Q2NZb0Yip2VYxLEsFnfSvH/D5XbMTo+aombmRucCdvEEgVftCH6Q6fcPBMF+aye71BAuJpwQt3\n3TI+X7CmvNiA0H86uM7lcrOgbw9pALJeB93nRE93FkRq1w6v+EU99X/lRHWdxJU4c2i/7uYRQwnR\nWV+9lo9y1QS4XWeKDlV1zdIy8Te/z9+Me4UOcOKFiaD4GU1i+RS0B5kR9Y6FsMFP1mQqyJ2PaHV9\nlk8WvDx3oitjUaJt2rZ5Q0/peFnho9n5SaTkcClX9xatPux2X2uYZVEJVTOKcMfWhpdxUQ9/9dbI\nIJA9+oQnVMnrxWtnj1IlDQf772kyYLfwsxi0rEMESruONruxzMjg8UCWod1dkl/VHIvOSErHVxwU\n99VmF5ikpgy5WJCdHHeL3NzlM+uGpd5SkwQjqZvKeDyaH79a5olDQ5JOrsohYiKflUjK64vA4ebB\nXgV3wl1gz3W4wMv4AppJGFPoYE/Hq0E2Vvdk+sUn8MKXdTrPA8EZROpsB9qYYNL7y3NoIAVND+gv\n9LhX/ONzAgmlfwOPYBVzwJFrx0khtmz7/iqSKJ0340k66SZqpuqI4hRbVgk1cphZQfebGts2PGor\nw19RoBiGpEdnmPf5i+1C9UOtQdfL7gUl1lsWC3UEsACdg8MIz7NZK7efUjm9UM79bGQXnYotvC9B\npJwANQG/c7lzPsqZiI087FCLghM0Jeu9SmnJTZJiduUDO5ZPGfmDOavKak+jwDAxra50l62fUNc2\nIDyE85UFIFBkD8nCKoM5Zn5X0yky/g37Xf4/HSmU2/WxZVVMXXSoVceUUpTJVddPq/mbreFbhOMO\nv0WhKfRTl539tiKa9yXHXRxt5v7bJ93aSgscdz5fkUq6BOvO/AJOEATjDkJQn1XWneYV8c6VG6H7\n5EOVCsfe5W6AjkoWdV9UIgHgmPYNhz5Uj8br9rdYT20v21ybMoS9FWNxjWipoIrsh/1mlVzOsPUV\nrDAhFmbWMOwT204SyIWBAWxr36AdIJFENhIiB1scMF+pKZKjhSbHdjJ10H8op8grTKtO1mDO4TAN\ninmTM74I28QKs1TYJowJ9/bKtVy7wWcG76zVw8AGj0Db5WJWeqHiMyABUsDvI0m2zDFEy4Dw95xo\nWfIRXfQ1J/ASdtNKVXMfi/76pqhRE9IT0x+2cKjSJrgTkzp5tAJllsD8p6GOhq3Dq4Qcnmocu0ab\nKhzSLksOZasdNAew/Mcua0FnaYUVxsF7pgp/l4tV6xnBAwDfPkWD1yF1FDbE14g9tqmDE01hX5KC\nVyZv0Rcs5rNuj31y71CK5uDJpHdx+vx1OHFKeaxQlcuO7HcBm+PV1Z8w3sAa5SXd8ihFjA0jIs/6\nSFGuVZfCxfEpzKdBZq2q1ujf9diydWgFquUBm44MsmreTJDAfETvd2eaWIB5dZatdRKT3lVM9jnE\n86QJRhZFtOnmoU2tHSSzH19zrZozqfD9xxeigU1YaRGFpxhTq04If6gJj0Zb/ZOMXcufiQlvpIz8\n9lOoHHeltAtg3gBYqBvdmWXf+tt3OhlpwBXHvi+IDmQxUp0qIR+DQrdxwEp1LCeutas5RWjH4cXE\nt5aKaYd3KpOW32yUpJd++wh/bY7fQR5T0ZfGtjjeKgkOAfwrfFkrkGsHRll0LPmIyAuVmBJuxkj2\nyWj/jKtgD6vhQ8nTo8lYX2pUOPC/D1AWrcQiixbGCmLUliBl7XRPvC7UBx7T2bbxR3mVmbCKYYJc\nFyHqdQYiF2pqNAcBawSAhyvAjJxrLHMemIPejUswrwvMjmCtOYnjOS84xF7iBjlB2UcdH2vEwMVu\ntKuYl6IO6s9ZlO3NbUZxcLkTEn5lT9UvDbApOCxlnY1xYDxqpJz/QOxmasUvJdef9HYGjMmU2mTH\nh0TemEs7YDx6cFKTxd7tOqtLJ3NZZ2bVHzJrV8QPP+z9EUAxuxJnzn1vY5B/RAUSWwDr0Xzn+l6k\niMbQFs6AUWIvjA8P+wYrX9wBySflSDLbZT2Nyo50cys+bWDcOiuKphhWJG+p6ZSItVqKRdVbGGJV\n0nmm6h77i5HL72l2xT+gYapdtpOJ+JuvBIm49JrzgX9wK9IRh2nR7DZeZ8xnQP1at8ZRsshhArDX\nZFs6M8+dppijHTjeC917HL6AbIi7uVOBNj0xhbAJcolceUc1MJv9Vd4ForZxA+ihZLaULBwkj4ni\nq7cnioBGQ6Qc1+ZIGpKtUKmgrLr4UXNtVROPRTJjRvJjOL5Vp3q1+LafPU88gpn75brDSPraDM3+\nuMD4R6AlvmWp75bt8hxfg/wYVow7QlSGjlH1jRfjQeShQG4N0xcOe6NqFAZtzW/VIoGHe29ZFXxy\nPS24yMzjv1O12h8mPGwn9WEzNHGaXBHRCBHe7CQkAlWsehbKP0elgGJGFXne2HDIg06+PpslbI/Y\nF6JpVhLaeNlhOOi3FX/25IqQlWBfPXJAIjgitJvcoSuXGOgMifVvvnm6leOHZrr8sNi3FrRXnRK6\nrcJzFe3PeMm9q4qRUGLj5eeqnY1KHhuHA4B0pno8eXxOj9Ewwnw8YWq1vSz3uAZw+QP8l8w9L4/e\nxSghvwlVlW5+Y0d+Rp8C+PYaXLzZkWHVAuETVcj2DmBQL6fr7aNxhGaYXWgMyYVCcPNC53iPgoph\n6Z7B9k3P1XpFU4Ij+5lrxtcIUU/ym3ywF84rKK6Gs4PUW3u4l46VZsR3OiVJj4jRWaATcfC8TwnW\nJfZ8mM1VU5xM3fMdFkkhZrdFS2GynQmy5VKVBpuw1ZouUnn3wxnKh4xzUTNyTUlqePzoowukncU4\nVAsgG/T/h+qJJ1uI2WlViX9eOaO5+pzR8XF3++a68y6lYNOX6FYf1xvFj+g6i8w/b2ConZCF3FQ1\niCTMyWvG90E3UpYTPyA+/UAX4N5tX+aQ+aanjMnFbaiPQtK4j5d1gaRAn8s5a7qMwzs0eJPNsTJn\n/qwfeQqQslR8wd2FCs+g60mFKpcPhPfiGjqvUkYPMjt/fhDS7oGgE1S7mhTxv3RvtwPWjkBRuv5y\naW4kRU4dvemlCA2iTa1oWl4kjvEttDs9h1dY8ELSypyhL8b92PbcH0CVlOfnqhvCHiwAErzUjiEa\nvy8+0OCfOnCsm1sx9Ajw8+afeboSkPHWRdKIQmE+AJ0pxPMuRqoQxedylh4eTOA1q2CuB06NtWw4\nukhqjDHU0kO2tj3ibuIZ7unCU2GGyEUJ1NMdntHT9dlohRBgT4mD/80HRm9S7N+4YfeOqzLrRaVw\nTc4/0sGNZYqD5oTrp0EpBCGwsjhOXZ77vVm69YM83ibovOQKixi9/hHcvvVU8O1/F5HNbYTFt+gj\n7mlHF88t5CaacYPH5MpGHxgRIvBN06LGIFtY2gTOrZzcVZuGNuOxJDn6tlBLEB8d2XxkuO5H0KWS\n2ImWoSzzAlDLJKtVG19MqgmqF9oxQDK523/9VDsHTSaRNjXcACknWcEcPc1Y+sHg1DX3LhGCSUOd\n+2CgCPL3CEail08kPPYaCm8YXuenTUZm2/mkv1zdWVD82lQlejlnKElGuupPolTYiUQfrQyWUqQD\nTHvf62Hm7CJDSuR9uXSpWxa/KqQXC5HGYcef/vjkWkJbUhCdc8PXYZ0D09HGAV/jcdfMa0FRrk0V\ntpnv1iHtoVSxS0L+Wumx82DxpmFmCflJ66ljTB+Qo9CBLLI+42SSY9U+f15cukSo80ZoYN5dvrEI\nAEMDlr+6BF0VZIMmK2i68EeDCjjnwd5WPoW7i5B5+VjJmcGExdMFVeTy1+KHbzAw2lOv5vssGTAE\nYBQB1Xd11weuUN2Hn4eAxON700TgMuIdjftD/f06xlWUOn4bzqzV2Y9z13j5r4eOs//I/ZUvx1hm\nR6ehQqD3XeCzPjZp1AfOF0qBUkNrvHetw39achS+8M7xOvkN0TGffRq9yakHXpkJUB/JiUOXGuG0\np8cQ5dz+VlS4wRbRVKtkhiLSaNLF5n1LHFx8bTjJHrazgQu0rCa0HAX+HlJbJhkTa1GLQaP3sLTX\nOIHfldwKlo2PBNRRTbsRUA0cKpFCeOcEQgQ/0N06oajufb8WgNzxQDWd9kyLPKodM7kgiNopSDrp\nNhl2rwOWJxvJ91WYME8J6NZ6q0xSjYhDSNVb0EsQHKwBJTbQ5PI5YhEotcqiv56RNRII+ZuNhJx3\ntqxf1Y1TfMPJT28ysJ/Vhx8fqhkGH29C7CL5nxlAVnMckM7srBFn205UJkXqmS6p6kjKtSeYQ8Js\naQk4g399WVYKjRwKCMIoparN7TWtDri1VJO5/BMcv5uo+povY3jAhnKh46gpbvawPCiX5lS4P0Mw\nr7OFOwe6RQku8+Zy3QssYmRWpqgb8+vAivHT70MetaMQlpo8n/wsl2eKNJr+497W+49GUQGb9Nl0\nry2dh8suRIub3sojLrOizvmjYjWGyN5Uq+xjSWbd1lTiEin/4Sc3PlPHYmMGo9X9gzdwm+UzqNNa\njYFPIREDM6d96iVfBQnTMVYC791Uv09d+2DT0KANb4lbsalzWSl33DNWyUE2EIAA2piA9VD5V6N/\nq6eA+HCb/ptA1UtpGf+lIq7xBoBGJuD31xG9PQ2D60L9wT7TxQTUYMK60mWW1k3y5fIQTLiDpTT6\n+kch9Oy/apHjcnTtvChaxldBgLzC4XZhhBwdvlEFpMqUyPs8oxVT7felE09TLb7eMcGmqc8/ZBAN\nZNDu4GSJAsJO0Xk1fCD4G7DSgmaiMrwxujesUwtvQxYr9EgUBgqxUFXI8/o+3Ro7kz8DqRHWuisZ\nf374n0HqJSxy6lPBmSzuGsi7yjrt8f/OqSivXV6yeOQ4kQBEuV4kOHsIgmc/Vs0MX700IY01KtLB\n02y++5d+zgkNjKLFq1z3DWHW8q9CBAJExOop5iVT3u4Fu33oZx6cJ7X3HV5M9IIrcJ0FZHQnIPD9\nRvCfVNfD6WT48GZ2nSDc/1tkf0r4j2XfhFxDsvY7k8W65Iy327RIU7dMbukbM70Zu8zZ65Vs+cOT\n7SIROv9w6ogPGkOlyg7TK1Kj9CnggqABJxO9KrV09vVZmgMINysnaKJr2a3PCOPx66ZcFz2dI43r\n4g6PVxMzZ5Dg2Sa0mXa2yEmDWXyXVA3e7+PPK7VqbYp+2RPuQDvd/uQ44hh1/lDXELU9B3B8VkoG\nYTYM2pXbTznaYBOTQogSaoi8rH2zoGhS0duHB8aSjdZZGlqbjvbJEZZp1M/FoCKRHsowXhaBrxT/\nXSUyRw4ka9psn6iEjoaVObBtDxYrsO3dibN27mAEDN4SLjqFQUdv2vFMRQtcd98ItAPzp2HzLWXz\nbNdKq6nt+nUw1c8tB6PnqL3LMbhfSSSXxOlm4CC4WPE8zYQGJ6k4K4Sv1X6CHM6BEBQjcN8IbaWv\n7N2J/SUMwLjJipNuujHGa1TK5cFHLF0kpAvn1w9Yqzcouz9HmPGXR+j+bXalhtKLZPzppqYo16a3\nUj3VjeKWJAQ3cca0bNnx3A5YakgpucIWJdeSbIS62pIzaKysFrM0AfQml5wJRjpbVnSdUoIQBcTJ\nkyw0np63rJf7lnf4JJlutsVKQ0yFcIthzDGqDDkZb3Tg+8Pq8QkjTyhFILkp9M2ESiVQa/ArmAZ6\npxOcy5A7ejY1FIv9Jqo6Rbgx7rmTK3Y40vp2Yo0iDobSHpZqHmNtU+kuzDMHiTmkRr3iZbGNK1Df\npelcyIOrecxprToZ12nXFAEPO/2/D2aHml72SNgDDL9rcCNjJYbaT2bBqupr2s8ZdD9y4aDdijhX\nEZwOP6oc1WMo+IAce03vHh0qgNhEV+uXo2oLNGZ1O//G277N8uxqWM6kwTeuGXkdv4fWI9yMFzBA\nfWCT4kRuqeCg+cFQltEVX4bgEUY5eOsijrvlLydgBSphsyv/VWxhOC6eDvjLJAN4YV6eHMuDz8Jl\nkirhXKllApYTl1Gfy30p5WbhDueCeodGwjw1VRGv/UFwlL0rK6tON/DHRni+pu9y4iSefYy7+CuT\n0VMLWr4o31qy9noK7FnB4xdCnwtdvAuNOUJ91EPERSXZfVZSR402LR/Lx/ndgo6bFuGJK6+OkGvc\nSgrlbG79in3JBDF87cqaw89Mq2xvC9ldri/wrGTvRulwGNuVkRhnFMAyqN5aW6PN/PpnQ3e3fAvt\nKGi+xJzJqrAZvU67yDyB3Ay39rYP4sWU0k+lgxJi561+FnFXMssVGbTZJG3NcPBjocLkqYKxQmKD\nRqxNRnMSbOv7ym7ORslmAuIr2PoGvnzUVTzoaYQnqYy15etgyd6gMQOx41HTHpjSd/NbPvkwtwh4\n7kTYIisrCC9t4uXoQxNi2uG43pXvgozsdjl/9if2zylmPalPE/2Rh2WtnPpTwby7WfvW8gwHlPhe\neNr7yq4Fxd5Iz0qzJH6f6QjEPou5qnk2OR1KuBZPaIhxktKmWIH8paJyEex0Dc4oGHKEtbrILiMP\nb/qgPfpyEOI0BkFtx9qctv41iQg7leKdL12tdALMXvRio+lYDPOfgTm61j+MA8TTYdbIP+ykmbur\nKkO/4tXIIoWHv7sWWtK3e9dVN40o6D8ofGHs/M4MBEJYRdDqPR37iXDiM4imuXFSr9l761qwK+mS\ncth83SS91Pa8wafTIBH2TfMWn8VwB3xQo+NSrnhXM5aNZHm2hsSMvWHgbQeIZGuZIwcqvMqqrrya\nOKLG2PwYmmQHRtEz2K185+phUsbJyNa9+uQV/gzl2u5IWyjo3+BazRlYufdzxvkUAcEU0p8UCy9z\nEhFOhXdcd/aFUfuRu2heQe446ii043h3PSPNVes0xSyvxBYJR//2AmDY/jFBPSP94eYrA8gumu0t\n3fSp0UO87rc30jbXH/eOK1P4xrbyvC/b723GZFpEh/coF3f5jWxN5AyYOuaofBH2iTdmWeEUFG3F\n9jVmIfkMC6G2PmWtdmw/6wg4rebiCNJj+LivVeNfJe3wJFP2koi/AdAO6FBZuLOdfkeorL5Y2S74\ninyxVjLSOKucyirmshSsHKyOhUm9YHtgDrQBUPedz9U74zFmiwoRjDnie4noQibeyxOefzHk6gso\nZ3vpHgkVxaO2d6GrHSWaJ1AjYH1IFhtTmTTHBQ7nt0hB4PlN2AWVl57IGNhCGfm/e2VqBePJdCdZ\ngwEdlpfPHrnL1EI+IG6Dpjnl3LAJpbRZnOFgX7eO6sgNtAp2dQzDS8EqOu8XEdNH1xJfOIj6GB5r\n6VDBud8OH50Fj1IusOLT8mCIz3tPKL/xSIZ1f9STofRMHQxeiLmJ3hnvERnflKlbMwCOL6qpKPsR\nU0oQ26dtDL8LTpajaJNLn3pQZkcaCE+eEuqQ0pryuMC9dY8mGXVa2tHtxuEN8TdPCs04SO5OyZU/\nNPujl5j6MGze+vfLxcoWQkiG1toSViR58JdfFs9WrzXZoCe0dJ+pg9Svc5zqX8r8f4IgLDRv4muS\nqF6MOzny8YvttjRvV3h2GYwyM6m3RRIvN5btX9aLaRv3/1moexaJlsvlWxd6sca6GUfO3nOXPSUW\nn7MX0AXhbxosqftiuYCg1dZ5YVAHkjYI/S1ypGZkNmhleyWhjHOluxXqGf/ppJz5TWN1SjtdFzeu\nnX/ziZQRa/5N43+sjvj6nsmZy6foC7pMm6BTdH/stmH2CrrMXM4Pe1hlrGL6l2E+Aua3XTQO9UoL\n1azuwiPr17CVPO2XShACYTccXQ42oxdnen1aS/xvD6ozaCpJiYASY3N9FuCCIRKbi4LvbigpZglU\nscJ8wWkZ0IOppAPyjZKOsIWEmphCKvagKBzoDaaujuuzkyHbKL3tzf4zLV3zjkrLdPyrc3iNdigx\npUuVbwN17Etpku3g1aKZ1y8111aEW8m6t2dhbsNyCzU6ACp0+udtakpT7KYMHuOVhtstbGkLeJBw\ng2O+Z/vS88MsCKXWp+IpK9wUTXl2jK6AUkmklC0S1D0eBH+/UCOqnwc5jLT9AVSEEEk+D7KZ99mF\nZ1HIhct0woxMBKjLLJctnvQtG5pDqDhoyXyfCrS5egxdDGJ3wX8SsesUBaRU8VWBQ0fk2l8o7dgF\ndW3bS031D/5SIcP1LpTi5J4lGIfhLUSQQAgNpIVcDBRKTFUF3PU9lxWo8wl0B5fJAaCcsL1yLA1X\nk+L22PaCA5HuZQFn+WDlJnWEGYvVkIZ8nRh2oOqiZ9mJBuyuely6WOmluHf34paJjt+dXCkaQn/V\njT3sQTOWbPEBKzXFouBj+KSqoky9HkHOt9+0IiUl3ILeoSunaXAP6DY6OzWuHMQQDCyOIUzPYM/c\n8bVWQXNJ9o/3gLSGXnAM7IEnQhelQ7oWSdS6F4bzLJ/eBuq7MyRib+mjN9VoyQduEgSibkpgpGPh\nP3GB1pE+IRsrlU+IAxC0NMRw5G8kTagpct+bvs/Jjas69ccLfgp+s7uwtuom6u8pT3KKgnsqX6Tr\ncgUGhkZehG4FfXcJTiMiDkLgIHULacKmGPU1Nr21VuLs72VZkcuwr3TSysOzoaXwMqHntVynJJzA\nwtDyXowIivNiYpPpkynye5TSbmFHVFH4VXWFpVM+pnd35Mt8I6n1ZjPCRSpCSI+BupZuWc+LvPV4\nbuvKXY6A1dhePmIih5wEyQSFGkpOPtY7l0q9XGLi1NSr7he8s/433Z4yospcDKTij57vukTaQr1C\n4iQOYGwZiAgWlsFCK8cFab8LJdT7vODzmgYBbaNQQJCrA5K1MnK0fleAhujgUaYYahzMvUvHzkJ0\nyBZU9YME+wvrnTeUehneoKvMm9VqQs6SK0oAP0dVcvyskI9fOt7z0CsDUIwj2RkKyFyCEKvXmQ4R\n6vep5d7b0xVrNaHYyGylD4//P/1rgt0G2YlCEZr0Zbf/sj4KJ3WMJ02VhbrPeO7GU338pH3g53cM\ndiui3+F69/1J46mSflsML+U4UxNgvFkhbujA/PqbN9OwmglRz9fOjuLP4rBuGbpIiqE2RijAn0zO\nwfCKFZleLDibjUKm4YEkaOotosBsMz5m9/Mjt05RPsHI8fM0pP5sg/6H5W7F4BUBgpnwjxbPwHT1\n2XI+5cZfTlpPS6nCgG1vAWO3CByjzY1O+VEgGuw5HtiZYH0irukNw7hSwF2eLIzk6I1ZoPQ3NbRe\nFC1gkcxcqDUIUU6fQQCy5aRbyfCEfSnwIPdIzZEkjCqNT7tbqwssWYGC5wyh5jJXHO2zvkWKKdyD\n9cJaaugD9dXZ5r7fwmfWQkL9u19RLo7h4+MAIglVg654r1bZssSpZmero7L4HVG3JNsxTchG1Ovq\njNG1NZ4QywwJTpVCJOVxYnwDJa52DPw/Sj/jKDmZYyZJA3QhhoA2cGthdX8zTFxrG0ofbTfz8RrH\nEueBE/uNu4/Yk3Gu9XlkeKy2nQoSmO+sS2xGLNhdSG5RFkYByui/v5O7iUk0nHEXnLJ4Y87RbN0Q\nmyQCkyGjgVR6mNslvixgLapwYQlS7OI8M3sbUy3emhSHn6Buv1f3sHSyjD0PLpTaZQxxHY7GCLO0\nHta5u88kr4xE/Rm9iKKi6WR31JuiOdjgPLJECqXx+nOJqFpLus4z/wlk2Hff1CrSoPVIFh0fKnh5\nEWPSy2Xv0RSO9uBEgfKof91Mozomrm+ICTCY071LdzOSDA9P7EHBDGZODHg0mSWStvjr2+0EuCT9\nUyKdVtJTJiySK6QrIXAfbNi6fvee0Q5zGPTTXEvWarYWRmbXAL8L9fgutzNfVvRB69/jP3GYnDfG\njUbjZBvP+uFfu+vCvAbNrYL2LMhVq+ym4+FwJQHVjo/JyJp0CwqcfqFartC0Ehnl0wRuf6/jZqHr\n+5h7jJ4w/2Hip96/Q8U/Oo+i6sZoUI0Q14+ZPa7cKFL9zq2PQjzZThni3p/AYC4f5452Nx17Vmvs\n1AG1GQBzTWs0lsSHkmarJBIgX4bM73eBgL6xVWt8GNus272WDgkSw3Gp7tAKUceW+HIVc6yVScr0\nq6pn3qCGW7EeC6pU+tiRGdWMoBZFVre73TKHHH51C84hkqSH9Hba9ZFjwzvMp4CEHvCTqePijrRy\nsTqKVUDqnKmto7IfmPLzrx/DJ8hbtAiUCazul9OAas6j9xqTvAVLqUgp8sX8U6szY67sd8hCOlZM\nyDpWGOd6rToZxInX0gi1cc9q/j4MznyIBLblJy5Ic0OqAMh8xz8Ww7xKSEstPfDfaPx2oMbWPHhY\nxvfnjEWlcwqyHBhWvoo3WPsxx2o+O4jAtGI5Ma/rXJzB5zRJbBkHeY8+5Qz159cceXeHp9Nbx3sr\nyTDreWZZiQ5lDtM3PmmJVECyXUnzdusqwjExqbq44MClUOEYDyHik4FZmblzRpOVYuETaXEfVEww\nesEqVmdRddeuuaiAetm172B5Rrjm4CN/lZgFMMFaunFETsQ1x8HF2rEXkTtpsrkgD7AjuRocUtOS\nIWa2sSe02CteurLjqFU3kGnrkbiVYJ3qmy20QIew1wt3lE3erB1fzIChvRyF/rwteXCxbe79yya3\nmBXrJnKDBzpfLccm/XoxweY/V4W8iEghYkF9y0tO7Y4D1npVDFyQ3ydcoPWvrB0Vp4lAJcmQc8it\nR/SKAqC5eHx3dyV2N+YmWlHG6eRSTSuepXazHhbblChVPb7eHhSyEKeIrirorL+3xYLNt7/IGX/Q\n03ox061KZNLvpC+5aGwJABl6btYpKxLgXGcCBRmlyfoknEG69FBbyHycjxhHiO9TzAPdKuC1VuSY\nm0R/zbI/RC1qNzheM4SEWLlpGNdOWfk3EkkOj6I8Z7zN0czfDlqE2jqrWb4xzdwpj+tSSEl9ZW/O\n3BiLJYcJ59qF/u58w078fc8ELw/XotpKx6LgGlpM5cRw+qGoCkwfAK2J2/MHLj/zlgf9GgIdzTNn\n+pjirWAnVwZFrW8WN8GhL5QhRN8Vbc61PbuAg6gak28rJXWMk6mP0dHfwqLflML+JN8lnQn+7jDf\njreHPlatcPtDVDoXVJy5zEZosB62dumztSD1KnDVEwRyY5CjEf9arUt7fl+Pc+VAoamGdc8IQFw0\n4LBX3YmzoJnJw7VYIEeuZmEGe0MINQDUNKK5lWYcPI0l/EpNsPoO6oM19aFiYHWiYIt7LM/cx2ra\n4EMHprpjoK0mHT6hw+FzXUOu/Ge7JS96AD7u2qnHASnLCi9d5aDraMHGuSivNAvpTFmqVhVp0hnl\n25FCXtTWUZqmjmWzZpP4dIv/K5WGHMO4JX+aI8MYSRinQ1HX18uYtpY/WWchDwJMudokyavK1sm9\nEioJFc2zQIMQiPAAclb3elcVK8AoerZJCL3DuS29t1MeJskl5bv7kKYlNbHP0oQoJNrPUQrCne+3\nJNGazI8SUGqCwRsG3vGUhCxYgd58yX8gzw601oz8EBYMhPqfN2IMY3RidnHtwFQaZIdQvzLC00fR\nY6dPQUPY0LHxYDC0jmYVWwAQxKtLNY2Q0LSIkRYSyKvnB+WuVBepXP/Q54MCDh4CsD5CHlCG3B4p\nQnr22AzDvLBZEmC2nt3Y0FDhoDrikrd4tT2lSjs+91akJuOzO4/FhoRzfKLED3bYjdw6I4qX5DqS\npnM9wIJgA9Zoi49UOvjRLA45RP+8/w8LdmO1PNOGC33FCncAPhv8C0ouPvI+sz3hjnQ0g15v31wR\n5oa30G0QNqgnC6a01mDY7UrErraoqsLUdTHtiV7WU3dEUMaaSq/AhyORDVMVNiWx2A1YeSUOmHHo\ns8eSPP1mQVMfscZF3vw97ihpf/7w8EHMU8sXp2fqFNO06yxO2myG0DxFfuUfa8K3FkKLVlqFz+V9\n/XFs3Mctn2tMUlW+Kr5yMR0BvVG16g78cDk7EF0ns63yfJj5R3MwNg0MBKYfUMkkcUdr0I/yr6NC\nKCor7/2VBa23Grvt7h4I5VxqtpxgOc02dGTuAw5mUWTPNH7KhDY+DLRJXaomIjEOK+IUqiHSpq19\n59mL84zffmfu/ICjr3XjhLLjfzqu1lQ5mE8ULLbdOstF8hcCTNN9w16gno8pO+r3bBACtu4zpao6\ntJq9w8tOEaBm+G5xoNSlRNaj6Erj+slP3YF/maRcHzC56EhMbF3c0R57QgRtddeWHgmICQbQf0nY\niO69yTSpH9hQcrn4k6bYUwnrOUIXYflBm7eC7p2oop/avtMnyt2w8GPIjx0UK9unVEfBF+zKjb0z\nvQxCxctLFaccb7HivzUB9b/m+eV0di1PVllM+FI1Yy94XoqOwm3SLFu18qxSLVPVW3EHk/I39Tfq\nKzdqzMudcCankJZ5Q9SXh+FrtDRQkvKQECrT6EbU0Xdx0S4SeChmGu2nhZyaFN5KuEXBrouEsNpU\nnTjeFodVIZ4xfMz5O7xx87a7za/FSi4Gi524Rw/Vk/qGu8f3FqUC3yIbUwpDRy+TVH/i33XQKI/z\nWiijYuznI2ncorbbfPVYp5ihZrUhztDtpsTf6/IbilI05W/rPfFg9Zl91KVI4iGtlGzWlt6dLpqN\nWCf6qawI36r2Z5x+d77SuFb+igfUep2vytFYEwzawv2O6iFrjJQ7nyc47w1P2vodo0ocd7r2mbWc\nLqvdgRDQ9165gke9xyGkR7KW0jhkwLftEU7w8knzEO+nfcLfHJCVJeznhnaVsWBSqlUoeM91f3ZZ\n9T1YhObnRDUXS3tjZ8sAqrIbgMEnlekbCulzQTlMmyCJ6OEWcuR2f3FCITYDWfE/y7ONfOyM4c6k\nAoNVIHwURia0U9cyq9Lk9rVACXRgnO3cIiHnDgA938IRL8ptajdxOZDiPh9I/JpEIYfbzZF1hYjS\n4/DGGSZTOJGYHuzrewC2DFbT7yOpi4yDDMYQsjjQkEADuMRzNtbMom67e/8dG2UjXF5v8bxRFpx6\ntqz7MT7+Dbc7NMD5fFmQFR+DHtgaWr3o0zpuNC7DK7k+8RVBHZg/FT++35X+ex5Ycq+E+OCWjU/G\nAIOCIYIWWK46cNBMb94yJwOBv+9iJmLUXy+FCsJ2dYkLqdP7bhQkxpvbhKFuJyAyJmwti+WZWeOO\nuavp4uNOmySl8+wYrJPAVlGU+EY/yqU7QdDvHsEH9NBK6DH4bkvZiDRGI+bopQHELnulEIeE2rBx\n2Bub9KFoMF9IB0KLtMsayMhal35TDINVcjyRAIoviTr1MnRTDMFfp8IMsb/gl2lX+Mlj1bUeBPph\nIl6l6E/kd/1sTeH7AsbYkBbL3GZsbkFcCUcW5542G/EpZZLH6to5GGiejRloUXHkeLq0UWKmFfLA\niLcVcdDBQZ/bbeYTt9XJcELJNY2lv3k4Sz0WlLyOXjrUXdFF+C1967+3fYIgMuYzJ7Ryp4jKz6iS\nQlVkEDdhFpf1QGXgDmku8TdLNY1+75xJPdnJAKR3k2KvAExpd94WMjAa8BWtIK8GuU9RAMHTH+oL\neQuwQBb+QwAy9hBlZNF2/4Tp6yuHtWAaXeRNvw66UrhBWVnMwHPh9fHmLkH0dmwrncng2PXkX1cZ\nsJW6oBliBks+IAtOZP7UX6p593/vWh3EA+dIeIIPG3uHTKf40JceDP+BC6NaJekufQEVX6VKjayL\ntB0ACXr1/lBe18xG6UsSETMAHm6EXKYsPrrJxoJRjuhMmjCrA/X5GLjOKs2fnnHebKtLDCuE7m2Q\ne5SwmujEqpTpprZmE24toXfcmEqcfTY8NicOEdcKp5S/nurlKXxKG9CNKgJ/d0ue8FSoC9i+2vcQ\nitrGzjwX5+NTch1w6sByIEGL9Eg4OfgblghO2qZaosJUKAixfXw10XWUx+EghLcOcWyYGNHUXAXQ\npMylzEwSZHbfTOrdnX6CTla2ifGH/A8g8Tf7bKwEvS4bhIhVD3cc1s+4iwxMagi6ukxLrLyfdwvo\nNz7FzaFjpspEhM3gaYeCu7hDZrEuc4OrHynZnyKy9XskxIuucinXi37WBpXjfNlofUdwiXKkm8f7\nt5pRZPmAXBdawVpfHmct2ehZpj3SBr48e7m/yAU3LWJ/i8xHb7FYxxZk8WP5RHmEphfy7F5MBkfL\nf/jmZtuXRG/BfhG7Ge/cI80juPoJTDsNDoTxixdb+GuK5uizRFDKopjCSHm3ZQSaIzm1veE0HRmo\nXR3nUFvWjVOmG5DyzvPQ1pfOQl81VVd4MyQqQbwnBFvxPHnnRL40A5j6X6205sN1FmqD4TBjMTiM\n5WwQwEirIuisCFbnHimavL32y4Ma7UvUN2mhZ3HGpKVFiqLpWDHTjZMs2y9MJajAvDGN9VmpryXG\nhmKTg/NjiNkuggpjG8wr/CQgZUQS4iB2vPK4yQyq4lWOT8GvKK1reCZeDBuWms3quACUbiO3WEjr\n9Be/1eEadYUB+bQkNy9yjuuW3MUe5VTbzwXeHL9j1IYZyQsvNTfqMpX60ttYVoXQ0AMkcdUSdYJL\nvjL75kv4Q1UvV9GpPYkqitv+oCPbxUdoN+pAaSc7+exicI1Hw9WbCt5WN4V/QifGHgkw1Y0yuUva\nEXSR+nnP8/O/N+oc2EmERHINmCZAyg7GcbOCHRNtFnkpvUB2o2OdmnVfckiXhzwxUCEMBVOB2lgF\nExxYQfbnjkZhdWaiyY6Xbq2a8IU0gmqE4vzuIyWcrQgCladIKZ+MPvTOYDha4+UQXBi+pPRc0arH\nl2x+ARtWqU7HfqxTPJ7QpALNARzGbJ3Idwghuoc32HnmQoY1zoKsqixgVi9X0pmraYi4827nWaLl\nW0ql4E0juIy9dPAm662qQqXTVEJZhzSKPXgV1zDqlY43GzBIJqtxlqpiUsDjqJ8UNgqgOPGypuVH\nvIkkIltcIuz6hCrnYqA5fWn72yNGVakjJZXHDwn5qieqSxWSTUDrMzIWMBwp12qqLG7EszfAAhOw\nVV8Pog5wQgm8EKd3kBYtfSpV21gcysn9C1FprFpPiSux3ca9PEtJdMUN3suS1ctKqRSxohE7koun\ndeJIO/yf8dnChriFQeYSmYO1DaIvhsAXue72eLGI/UrGPvTg4vJLz1aeyvPQVP/7zsCb88ak0xTL\niiD+LavTeyG1ZFDhO8KOXm+Jlhw2T8X7l0sddNg9RxuzVCwKkx0bT7A3apq63kp5v6HAZoEf7ymr\nGoPmL9tGlF7CXny80TrXK+CCDVIrFTT1U/HLnWCL+o0vblVFz1jG+kx5VI/2N05UBu9jKMkecStO\nM4MkhEZw53uZNqsL042SmzvCUxDXu5X3oIeGP6ntF9GwBY+hXGi6CygWakZc7QvQfWqjAdRmPi3p\nPAUNW8AtZtKsn5YUU/QBJsHLOPnD9uav0LctYdWyMUgQuZRb8fteEsLjpbenl7/DEfLuYo5w6nmW\nxqueh81PDX20J+55jbFvDSS8fjdOqEpzHlAA/ztwFqFpZpMBnkCJ3THbH0FkJehotQ90bdKmgWpk\nJ1V3mK9Kbluuvi9JGLSXT99nwj2KU7D7qJirFsJ+aV0bv9TyJqQ7WcAiDt7/0565Y4nUHHKIEOwu\n7ApyT6mjKm2SJdU3mVNGt4C2WVMyncatje5o1kTQIeBbs+PFPUQyqviaFLiIOSx/1aNQHR7huRsR\n2SUnyiE3UAboCmVF7IQR36rZK41noZ0J7XkIE4oxB0LU0jia6W1WYwQlox/fcUOBrKrfc0sqziuZ\nNTy0n7r5TNWQTvLIrVN8F0vYsPFis0j4u++qiusoQpitzqSX+aGC5toPCVpjpyJtoz2XiPqcb5QL\nXV3Se1WFOHrn7V8+AbhMtUKZU2CT30FEesgztgQeZyWY4bT/H3wcj0/hdjw3R9Owlu9ZeoghCcdh\ndyLexfK/JRc2Se2VDrm5K4oGiZdx0DHPHbdTdfhdso+wOkUarYKQJ59SSnDwkn5QhXGnAnRathPp\npaAKAJ0VNAGxv5zi3xy+EAsbp+A9izXsFdQSefxhhXGQvUkKyRmjPpJ7OeEyoRb6VdSDJT/eRW8w\nTBwTaKDEUTwJdDozKV6t1dAiuddXVRmDanRqJM3Q/WvSBO5EhAtL8/E/iC23nPJuVUa5QbCt9tSy\nwrqhmWBl7UkuKFuLZRm3X+I0iUyOeKyJC96X/5rUfGyU//VPqZaPJOW1Do+jS6SdvXSQiAbRB+V5\n8qxdX4Vs+ruNSUJOhgiSm5SyES/dfmB89YPOphxC0CrJ9FQ1RSYsaMMWTjttqubD1l2wgIrM7z2+\nge1YC576RlTgOqE6z5s2tUrNYShNavvnxPY36YCVrprfhLzz2y8KSJSXyOXGhMLCU2b4UALGZqSF\n/Hd4Sh1TiK5LpPCUyHpxD0c0dNuCMndyDuN9Wm7ol/6Z0yRPYxUFrQkFAugOwSRgO8DN6aiVlfWO\nfA5gmf5fiCp01KoTGJtwZe6njYx2UNAmuZXL1XidO0ocTMWkqgGhnGGnRSDoT5JEcizvvripIQz2\nsbSqfB8ZkrTy/55o2EkA78qEEjt7D6MtAw9ZxhamS8FX3Vgw/i8CzgjNv/pa6PzJU4zaF02iLR7g\nOF1l++OqRMxqiYTShKk3IZS3xtp9gpcXPFzB+/tUXr4DPpvIg0ZiY11sPrTnLdN6pgXdPsKxwNzS\nbFeo7bkm9OwMgoo4HVBjSMDwx0LzupYSpT9e1WZNZgG9MvjHHiyuES3QEBUz+gXY0S5h1sx1K3px\nP0DM9nARePZzxtU7H94OcL7nnbj+X/jA3csUKTZbVHy63mDO9uqZf4dF1ght16BJs6TpRDV3hMW2\nbEbOx0lHYqwW4k0PwM6y03shCIVqphsOEfznJTY94q1JzU0n5VhLLmhpqmsT2OoEScCpzkSdSTMz\n2glZ1TLMGII7koFgH+GmC2HdYjokXCAWpbbuavSkUVwJqzVHfZNvPbpThOkm6tA9mOjs57WbHLxI\n42yJmpF++XQ6V6L44z7+OpQJv7OANZBnXiRp2D5t8DDfkQOoyJFVD7BUHr3f9HAydGqkyOsjYEvc\noC9ppcv06Z6AtYS1POrXuw/m7JdPhmkKkD6/9b4YBZEWOB5bAJm/jnKnqgQpQpvKVmCJMIwq4GIM\nccXB1G/mOYCzA6V4IZ7LwWsSnJLmdaqgoHMhcSONTyUFoIepVP8rtLq8+fkDf2hpREZNO1GUizxy\nrrcNlojF/tXSRr/Gn2Iy7b4quDc6CLYalgq4ybgR4fXCue3tfxyXyzo/eRfiVUfHpE0QqlrZoKgR\nSyvHgSyIMeRVuOD/CzpBZoUgcdzT1aDNGObDnWogvDRZZ2qZfNy8NEsw1ClGT24oDy/YJZRb27J/\nIyf/DhhkTvcOPu/uE9IQRwf6FX00lOW/SpKBHb5Wz5sG2PDwGIW5hF18YLAiMvldYSaSn5Mo6VPK\nzs6aBRNXddmQsGGJMdBUcvuwAbgPd9M/LDft145AajjDH7ylr7bvmsSQVpw9fGKx7/lZg/N0gwAT\nV+McuY7TyLBcVUuNFk3d050zPyL3xHJX3vDHgdqcaETSkgdKxmcR1i65IkP2f/3TriUNZs16yyX3\ntkdU3NidEg0mC54ErJXd8HZ57kla/OG4xpo9R7Ku7KPYoh5ZprmdacqHre1CBsOZpORWLWp8o7gM\ncybDHvAPO563AnBKL1p8BD+Y0eYPWpU+hWuusig59/9wP4jYJXrIgqr0Jvsk8nR+Y+F1Noyg9tV+\nCgF3hNDmfutcBKdClvtl0RTOgDw5Yftfebkid1V2z6hddcNiJ5wcdn0hxwxoYIOaSzhcT4x5h6AV\nUcl+FXCfyAfoq6n1omxkDcN157WsakUn0HgwDjZXuzfwaAasMmnHUtFSECRkxxuiJR9HGlCBwr32\nCTnF99KWxbFz21tv2LRbR4adbKe1L4Tt0tDBTzpM/ebyghpU55+E+K1/v7P9sMA+UCZP7oJMH+7V\nW/p1NQb4jPfYn0BvrHYP52hMeVbNBZAnsmc8TvoFNv+w2mS7WFHp1zTJJjnqapz7NUq17S211Kj+\nkYlQAI6cSyY6quIzZNt6jfxufKXUZ7cbbvQigHU+aRfM/Zk3RflAnBhNGbyd9nUTMH3xSX8mHVjv\n3kVBFxZstdGDMapg32k7G+0rz7mBBoWjONc5ljzDoP8HVAxVf/srjwODN5CzYPxOwPQEwk7k3dTv\notU4znUF7sXlGmUUZuTLZjJtvkPFLZyHwzcPBTE04QCgBurewqqZSQmmZ29G1iSn/Xa5wsM9crM4\nhZvRhmnf5los/MfBY26oiw7heK2MsbF0mflhpG8dVWSu9hm1FfLR90dOQMAqZyOPhgWIKLxWeR+f\nBclDXyecYUqTPXQypVPvrSqBYNORd/50R9yfqh3holHc7t6Q19tcRC1/z+C7efulae4eIZVAymL6\nzXLfujL/wriDoo6eCfM9QwYC2nm4nRQczPzmHP6h3g/qCAH2dIrAUGmU4saTmklA6PhF3OMDnhKC\n1anMP/JuLlPJ7YGkI1sNwbZK/Gso8hfsNYqe6imHY8VybPJ5CfiHZaIB76aZ3+6Duif7FapkxWWE\nDWErcJ3aGID4rZXDYghylf269CTSwLI+rikWlK3VGgWl7Amch710uPurIWOqgRTXL9TB4/zy5q6B\nC3OzZSXGZugdMVSeFkYps3pVFrPmrXnITBhitvJmhKOSf/Qz67gkcPGIjyDpGmuFvuSpf9rAFcAe\nNlDZelQmZZBLlPA30bTfO8mjcstuRIb5SNbm43WzjzgJncSH2XBiQm0dxNrD/vmliuDf52WqmFCm\ndK1bKbPwL2uu+EclbBELEj+OERqeY67RUprz/8hL6vrWQpLegfrWyJX1BcFfv9nxY0wqHKYaQnCN\nzUyFEf5G9AzfYHBchwddvwom58fLGc3EyNfPQWM5hRuq8qi+cIeQtoVQxKNlXCansogqODQTLgSU\n22q7690oNbLIHiQIJ50jwHaPBZetcWHuN6MYJLyoVPLnpnqEn6JhOvahY8wUP0Df98zz5ysIRG6i\nzA5fsybJRMSVGP/CPRxieijwAWVdmRftleqzZydwd0xTIGMwS0PagxqIpWBbHaXg4BfHFtiKLQVC\n7rv2a4ps8nxg+QUdJG+9zlCBV1HWaTWjQvLyJw675uDdIPV+ZFAt/aFtZdllBzGyeS8lGUBG1HUr\nTE1ftP/Y7PPyLgT2E4i/q78VFYnHPWEcwVwO4Gn4/M/m0zUfVSwPaJWdKWvJJmVrfJhjBNBvzien\nvsuHhS1Ebtpykxdo8MIikOy9QqkNnIzIzhKDwhjYgRLmpJ4T/MWmIR2EmXKXaHbiUDnFTSndg/nW\nY5pm9Eb7448Q+gDB+tUmDtM21qPGc34hOfzz1xdvmVkGOZtdIDIYWLJl5ZctFEgNczmQPpWoYfWG\nL4a9pktcqyQCVQHTIWt6zsHl3Kpy7vdEPCc5c5ijt80okjjuDZNlKgVVpxrB8G4oEmVVdurqepYm\nDdtQBDSQ4MWG0Cld1Juib7+6N4P0nfY46mnwjnRF6eOxX0BZC1Ha1h7iZLJN6hIQf+Y+ApYwsL4f\nywNiB/1Uof5mJ3PiGTwKP4vFx+j8EPKWJnCHZMnlNKdsFv4e+p4bJRzMisLZ6KvyEcTXvbYbJn4S\nrLAUAYD9yBq0qpEYBezVTaX8oPAoZK6CpzYs76KdwduJE1TgAPgd0DCOmzUdCiQ4u5IPgNOWVsxD\nX2jWLr4OeD1pbLSBAWljlPJQHxc82FJ8L8VHHwEpTEBDEPZk41dQ1YEqHblCTCGg7H+D8asmxpcg\nz8lctOjwMTNsUohxZGLKrHBydr1Bvz8N/sRxYvqpmGinhjSZPXfpyuDbTZV/jsfC/89+ikKqS+4Y\n1l+UcBtl1BifGY44xDzOOoCFmnJmhV45fUUSlXJtj3fHFpo1JvjPy9wa2ktpdE+OqtvwNIiXw6Ib\n2Czj4ckhYq1NlvniAGvcTuRLjmYXllokgz06EGIQ20uOqIeZ/ueGa2ONBSH17zOe1BhVLqPgrXNS\nrSeF0EwuzhuNg892QYrGzKeiZzQZFfzuQu49XAxtbeRlrkTiON5jwFHwGZT5FkNCVmk/gAVSUs9F\nWztoJFDQuUHybd4HAwlSF6FHru2Ojc1Jrd3c3NdJX6BILzZGQ8KcHv9eywrON71rKUy++/Cor7Ok\nRVjBRrbOUygjueHWOiR7HDTX6/x0NOADBC3/FBpoWx1QBSegHyEkJ3KFpTR0qW2JYAysTeHVpLg7\ntvMUAIa9rrq6gLia5mK1KJCy8v3OJ0yRQ5mk+TACfDQzeGfVSqN1qaqoTAcw/74UgIhEyxlRqrZm\nwbxIXPuWhCkClebyi3HDMHErT17kw+tymoMi+Q/8KFaqz/DcxsjN/EOFKOEBhY+Ozw1Z4gM69VWW\nFoaxAU0jOdgs/34wSZRy8XolOj10ve+fB7cEYy9+AMxG7jgIaOuKPE0SOarj1vpHip5txSg9RV4f\n3vxQNAd2iNc8OzFv2ujy1s40z3WDViXmeAxE92vRF5RUBG7P8ddQ/S/hL9TG/7MRNHsg43+WTK9U\n4/NoH7HREreC0HW9cjTWhGprH0/x8DTs+Sojd0o8hd4XS7AzAk8lH4RO3uGRJjuDA24oJL34ea4D\n5t3uZ9VTy/jG1e/GmZMv5vD0L4ME3EtVzOLm9DwC53A1PgU1WePwEzb52L/dybldr4wSbg/tDL4P\nuzDe5JEdAPr0od5RXhN5G3y8kiLJ3D5HieqmcVY3oYD+ZFc7VMXNpdPyXnAhR7hHOM0+rBJ5L9Fp\n7nWqHt9KwRzTTdIilGbbaGy+1Aml+aOMlYfOaQJldQVLFyNB5nQAJyBWMfJ65VF+9RBV20wPz51B\nd0iLetkqgkjTUdg0DkCdqnRhw1qSgy/KJuKSwVp10EmgH+WivOiJZ4RTxzKfi/jvKoHdJm3Ld2wQ\nJmdm5N2zoXv2WY1B4moJP6Xkr20jPNYN03tzznnaXBk2Zvp1WaKdVsMpei41VYnxmbAkkPPn7uRW\nFVaF4NR9nGN1MF3O+KWEKdsPFTLe3m01ZmhV+sf+3VvvV/RT1nGbJ5spjA5jMxzMHZhYabRplbOn\ngi/vszu0/xUP0YLy4DoGfnmwzjGhmyWXYQwja45GZfjPLXf8ZhgsvztiuO+olNTSzRe0wc374I45\noGMgvj5R1DjiGQE210NsN6haalPZyKX/KSVw4Zr9yY1SqmWXzWhaxt9WGjTyM6uUC9dgmdxZfD8n\nnjnrEL2RYKbBwq+d717mFnxlUlO3j98jJiz7zhhVAc2JGV607yTfqId1T8nyVI55W4QX1S2a/ofy\nB2AVcfSUVwu24ILv/i+31RHALL/WJQbgHGn3bV3w1tqSAXNxVBvBpUSCXoX9FrEQkpznzYCGbODs\nzKCDLLyqaKUGCI/zTzYkaRxtb4oWXN2qAbns6Mc90EBV3T44KpQsi8NZQt8adBzNr1m1Q8ltL1ZI\nzIJPsPTPjzxAFRr3wQ+7EK+6JwVDBhYEBlPKSBmyzkXRIWJhP1LNhvONYA3oLhCcRtAwvSSAtkPe\nU+w4VJMw4S5Q4NPOuuxjZ07eVMwKJzgb5k0vd8+7wV3WhRUe8n6RUV3eKMwGhWJWc+oLq/SuFC5k\nRrIpeqCyAic7XOOSbaBOQwafo6zR5GWxQov+OpVWsq1nSw6yOD7bra3BfCCQxWTS5UquEO4TnMDA\n/BsrRZ/WuQRzekfb7ToQ1UFYCSDD8kiWBZ0hw8kXIka8lS2dMgupylB9dyAVbgG7ym3qRxaxg2wf\nhYxDpdCSWUjeM/11Tfc2J/lZsW59DbuARboozT4oOw7uNxILpB79K+pDBUJENaPQS+kvcy3/pNxo\n4WFcRq+fphR/lPokXN7UWr15zsfvV5NSUGQ1gEoL5z2Xin03HDSSDl04Fuk/ydo6PBVAyQ8rfeTe\nss2T1fuj8qfMnRkQMnByVMxJJSWkZ70HgO1cUvjn4AitvRwMzEiG1QDmSNL0pX+FEgO+91KpqKEG\ngeQy64302tcHzQza+aY8RniTYXjqVvNlKZLrcDJEpkvjDNb6kSCEezt8/xnOchPPrXiQ5q/LB/55\nONFHAxkUAYNsQrYhe5Hvk4qEovu8SG4K/XtztP2Jeob1grC1Q90z7PN7QSTDTA9pOGbERW8AV3Nb\ndAsqrg3cW5IFPx0ZjOwIIRs+XXbPJF5U+igQ1YETDmiRz9swz1GAZg3t52QvPpmfpo/h0dAj8FXh\nMTLTFXa57GktHm3DlVMThj9+wbcfF+lK7D5vYY88oLoNWQ/q9TzIcFMDlBQWs4p0LdC6Ox/PDFX6\nP2mDOWXSi+h65LivpbqrwUcY6A6fN1blNAuaCPGjaCHcnoCCXUsrIMuSoqhktob3nkhLkr+xjgBY\nLu0x+xitB6xevG1wiXL7Iy2+BZyzG+0xCI4CUPI/sOX4HAd5plSVtHoT50KY77WI3rHRXO2v91sq\n487hZAVWAO8FfW3wHabO6SrN/xYTcBsz7GEKHK41oXlynvAgYHDe26LmTFPjfg6FvsmHP2CjCEss\nD2A1yceMbGs5opISULIM8bFURS5pR3EWaYfRZgmjrQE4t8lXmw7fkXeb8Xqt+Ynr6xL2+l7BDRFc\nuoo64nIGdZh+41WN7ocHEm1Ne2rdHxcwb3MHhyVFeCe+sLVF7AQCo5mf+knXVcgp4WnCOlTpOb8O\nCfZlPOI4HALwGmPMpPNRljSu7YNZakLcQvpQ8xbdjcL5A5vj4Sft6rCrg2RizMbx2AgJUrhMDN4S\n2sZV+Vq+qaSJmFM3kn2WgnACP8cQgg193MSOd0qEDfDmAILstz+xMx+7HJBeX+pQ7H7nCNxI+tQb\ndBAV88LUYgseOP30myfCVJkih9EaFOdXosfb5oIKI6qXycgcAPhEjlmDij6VpC57IAfutk2TQltY\nAMNLRDiCAe2UlBPjvUjlnSUT/BsLigR3Q82zco+xEME2gowAJ/2tGhJeIuOF1SbLYXRbICpaOFY8\ncnCLWY2BYLDP7u1y71BwibnZ5Ddic94UqPSTJUqlzytCljWaNlARo4Ak73KDxnFyDJw50nJ0ncWt\nHZbG4AuUoyaoE9HdJRp31+6R6wCfCEJw+Sjn5mnsP2hXiC71u1aG48TzSB6qFEwtQcLcKM3ZcOhK\ntvqnJQs5Bjs7TcFdIn5OkvUzAai4mEs3cSu1MKnOHoccpNZml9SerTH/Oq2GiteYekuVs3NFYP6e\n/2rel3iDJeTcQViEWGEIDu9m+e3yMjG6jqoc9V0jTCWLroGNnRQobOTU/GJaQ5Mo0zeqZRMvbpT5\nfGDLO8bI5UlhI5ELXGkR6NOe5C1vcVf4RHJALLBUMxzBSKiV0zev2BgPjCF/1h/9hiVSOvqmOAA/\nfHIs9PfTHYkMpCxnkHXxoGJZh7lDFJTFWK1Jy/TWhlNZix/usNJOlcxl9SShQhlJoNfYdo6reqee\n1RzMMzsyWUi5Ylkdw77pOZU6coNMOq18WhUvtpNNXfgjfs1w0KcFsFQiUECzecqk+Khv2MnArbjF\nl8KuMd8umFVQq6gpj6mDC6BSftqBlRvBap6m554EgwuEGryQJ8udbt+nqMU7eUMvrC1+V1fvrf08\nqFiEfUBHEJZTQi6IRJtRS25DSA4CLcTCb7T5ezKtMVihEZsRnkZQKcbFmcTitPr7+HqziOaCpxv7\n6c8SIpYok7nIbHSKcwrynzzJR0LusjM4vONC/zWwqsTak2TVdoPEby92+QWcQtEJQnt/yIII2Lv0\nQSre3cgfs0fFt62UEOO8/JAyWGpQVHsOuvzCcndNy3VjZsu0a4GYwKTcVpj839GE7RPxjcE5Fmo5\nrAqNHsvQG+I5KEYfoFlXvesI0bS+SE7oP89H41YGWumHFnWSLHMdOL4mMMwk1TV9j5WZazbBVkIj\nJreFFKIbitZXzwiH0gSvk101PrKM2iA6UuKhXs3sytGLXFETN4CaHZCmuKvDufJRRYgdFVhWk0vj\np7eNpu4vWrDN+Stg4+LshKy6/RonOz5yqwUwN90purCCP+9yJ+AVzdOXPhE0VedY2KxuTDeFyJf5\nZdn9+hb1mGLfPsMKplQ7PBN41zj0vx9/qfldDEYmQKvQsW34Yu9XrMLLRaxkhi045FfyOb4VP1Ul\nl1GNmVpEdvId29xNiP9kLI2Aa3fy7QJMnslVtlpCcAIZnci2JMuZ2Mg8PGrmRbYbWN8s82PCKS2S\nSe6zkMAwmSUTlZfFeS+uEKZWGp4YkoO5F0Vl1EZ+Xx7fcXd82o6Ulcry5TauT1ZBpC+vaWk8/izg\njGY6/sJJEjPoLxAFBmFHIhP/t75qhF/8Jm/PMRbOUVSGNue7tw3cha9ixHRpwBXjUwA1JR0XZB8f\n7MruwIJ1hSKGh7LKtePYw14w6gpULD1EobrhIbsupbZO/eXy8pQQBH/jK1C7YH0DHgUsRyaeTzk3\n8fLqCxnzT7ELzP/PwjtVyPu5lnzP1kHymGKJXjNUUXtT7CBpVZAYYBHwaZt2bja4zN47veaHIMCp\n8mYwm/WKdXW0PaC640Qaa98kz6+gfxuPpvbNlF3eHwE04zhn+16o8jROKU5VxDL4ZMJJ/QHX/mV5\nC7p46q/jilwCE4BBuVo63U9SxBbIVEVmaur6KgT8BRiJYemklaRKH8yhlzjbfU+sjSxD9nvidTAV\nUmj9IGEIhWZiJIma8bSYePEj1yhHzMxSCC6NcdxTIaoLflUqenCKGK7ziYqciElwUWnt8NCnZivP\noAEU+3vAZxZtfqWNiorGVEaDieurZSvdnbqYgzZPeU/ztD/Q4LddVALKDSUqsKrk2WeKohab0Nza\nQc7zBSD7dS1btRUsuLEwJMDCrN04M9HmerjMB1eFkig8+d5drTCcQD6yRxwwtffyxPs9PgWfq7Ab\ng3shXd/BfsGqIuZBbDcTySdsfePCBy8j+NqjUe1BPTToScf0ZdduS6zm0ekULLOvqhXtq4mziXod\n7hC2dyyTkflsqdLVo/DMTxnPjIImEpefrEcwupKtyJqw34D4UAbgk4eSGj2QY+0e2c5AykabrQHC\ncjK20Gh7364M85uwqBQDM87d9FfOOsqgQ2aagc/h8kJf2bYIuXh7oscf4Px9CnB/wn8BqX9zxWjP\n9lOMnXHfVBBgfRV69PmaXRyMXI7LhaqAAhp2nkvZ0PqKvj3aqQtHzJGbe0Sr5KCmDJwhGCW2bZ9R\nzuldt1UjfP7udoW915iGcprT5ckrGNShWeiN3bmPW6IzBOYpnUgIfeyhQTIBQlToSot5ukFUOCln\n+rkVQLnBMn6brH0O+T3jnzpo6bt31B7DZgq7DrdZHb+xLajDSsZth4bC318e1sIhjRbcliiCKOZ+\nLCbgL7cf7NSS6xjBmTu5RKJcgA78fiC8BxYDSLa9pIk887I39A90XhZmQ5VLPOw9mV1zpzwiYO0P\nq3zPMYpvq8I+b1LLOlDaDvgFwBeUnUHDhrM6IOBP/e2gIokSHow5w1mNmSNGid0Inp0LOC6+HcIO\nR60KmUMwJKPsW9WyttLdP+zNhaxn9PY6/rSs5gGYxKvxcDBU/FkAg7gysNg08UCx09QYoBsli7+k\n+IFGUzltRFg+jgKGajOeF786SENA1J3VPAp+6H/tAOh99/XFvwGCydvKKzxzR4HA08BDHYE60gfr\n4QI/kc7MKguvExwO9oXxuS72Q+wS192yMHcVsH/OermwhKlMBKGe9v1ReIEA3vWdYYlKILoqFa+3\nVZTMZNWxyU+wn40utF7Vl6vZnRX9uoXS3srQdAM1DYN4KrsrPNkI6OH0QJQ7BeFO9shZd+7RoXH2\np1PToKGQgqQyetki4Tz4F38QCgtOWKUDmViYu7NvI6bd0EjnUCgzONXT0X7yk6U/2i4xL3Ao42IL\nIyBM8gCNCQu2IqbX82yKRCBoQMdFUG8zYcFDO0F1WwTx6LzAJ5hkO1cdhqN4+PcAO2AgC0LcXAY3\nJ5jy75J9c4ZxSk6XYNHFx2ooznlXloUPczg8cd1aywT76iq9tRgxzpQbTERRdql30e0OMc9naO+3\nDsgV6DZtT490SG/0QZgB1hiGZmyS+z3Shekkc45z0oc/6GGa+ZdtCfJzaELA1uEw7KMhzb6NJjMv\nWSogYImb0Y7OdAI82DCpy5zcj/m9rOp//rlv2UjgZySvGbiIcIko4ZvgGCBUcRo80XikQbOVB+mu\nNjYVGsPtozgBYOYlYorfTjiP6GVVaBNUC5NbV4ZwukkvTO94rAnfpy/ksEZPFZAczgs7aD+Pol8d\nwdFehQz4q2lW/PqQb9tMdMq2x0LrIYFt8dQAxQrkG19Az3CDidn167SQlPCKLUKCAPk4ob6q1Zp5\nXCaMK1UYQJvjyC8prqoa429fZr1zjT5RNCnrTiQRY0akAofiNmzCCXwHD3NH100CNuft6kXQA1EV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7FpYUEQrqMw95EbQanoFo/z9woPf1YGl818RGMWalMfHC3dOv/zN/Tgv5g9QvQ\nqU4JFEzRGOwwMwsP/nt+V4umY2olM+qJGTVNezamrxSalvYNJjMqyJ+nREdWExNc0gud0M+Hh/Qm\nt0nPbTR4h/GoB+mnRzyGYIlLlrgne53+SAotLQyXe7HzNf+xe87GkDcVygdNjgNstw8yNwJFKOnM\nmLG5ezw0RhBoDRST5u4H5IT3khhj8cU7x+Nb758JwFvmpgqxLskMOfDU/RLcu/+YVsBy2gp10+78\nw0thxWRCS3Wii3mblSOBqYlE20FQdtyPnzLKrH5TgYR0RPi4ubdxikIeS0hdRt5+CWTi4oSj0oA5\nRpj+kq2v5RU7+Upd2mql2XBLfDaAwvDoxwwYLKlyXl1A8tFOtl+q+EwyrIbehS6Abxe/GkzBWDG5\n1gGeJTYpxpX0aaYIHY/YFiB1a9XvC6lwYTSdZyNoCMIAUgdR44J9y+G2Dp9Kb2E/gXEwbXolAn3U\nB3YGxlUiX16WdLg5qM1M3DIw3OrkzYyvXW5gylWjWonv5ov8FfXC4j/eMva9EYkVn5bbtK5GB9jl\ncWtnSnYxhv/EdewWaGgGyx1e8KS1lemi0EHCeVUmww1GY7soQYmiGDeLaSg+K7kkpoGbVXTRV3Fx\nGsUm06OwfZEWteUwttcY5LNRuAkI47/hmmxj1xMR6Fr+eVZXn7A4qUAZCqshZTMzyUVtKEy9edpj\n1lRRz+x1+XTZ1Fb9vTobzJiDE2HEgyW4P3A0sfBh2Vn/1aZ+RcKOYtWY35/q32iV9yJzVMzYOmxu\nVxnws1b827EAF4p3fxVVuvQoGhcduGY4wlJBBd6jUnHoVcN5NBkuTXPsXr33KVcw1mO9InhW18qY\nAqI71tZKMQeezGrd1fDzb+UkApHDYXcyTd5r40TSLlZORGFlYo64wkc4rXPhnfZnT8zAf0QIZIgd\nm1YtiNcEKf0y8Fe3oYMbdyG8zRKhD/i4gKwgOZGoAAmDqXjDhY+cvDtQIgxiGqCoSZHwXme3cumr\no6ts5CoopDtcsoi8mpykV0agbNEXaUK0HCzTqvwLMfBy1amkpvmSitrXlyRR8a04hHMmgN4EOBvw\nkQsbBNJjHntLCdoUgA6COq+zP08fvzeUN0BkAthDmpHCPVOqJVx4VNx2rotZjAHtYj8j8zHqW2oh\njhFcLgziUp3VEgnrnwLknRlKc5ZV3MeMGt6UeenUPZOIKPS1uFpY6dMJs+8AOVuL6KNPOwwX7S6+\njWUbpIjujrtRmXbi2St9Z25abqRxb+gOIlFlfIb8KejnCI1Oz1/A6tV/16/F8GaJBySXrlIaOz5K\nc1HykP1KgndWc58H4pFjsxBmKeflPo4l3OYIaSzmGd9SAtnOWO2qhK4n9ek7meElEvQiDzCM4+rX\n/b6c7N9YWiynijDmTFn6ITF2xI69PNjyNkFUOGUzVjxd83l3Y8Sah24d44zeCiAyGNcmEWqXmbso\nQ5gkkqDSOC+f9q+NdYUlQW52GITjU8SK1VomeGpQmX7G92GUWw77IJCyEakPLeY99i3IhV3GaNI+\nQSbNMFyHONKU6Kh09WFpzGWBh9QKy9zqPgSbsn93w/Zht+KPJHHjGiLG2vCC3TGXG3gN65el7I+/\nNNV+OMbYZYlgbZNFI4JgHC2wgJwQPv1T0ECpUvqqywDmXLWHwfv54YrAkNjYohL+cIAh+yA1UzWd\n/GURSS1lPjvDU3qaLzFyh90IKNp6ft30NxO47HgrYFcTFWP+HCVxiZhSLjEfmuMXX58cBqm9DfJ1\n3fuVIJ/znAqwo5am3ktgqnF/2r5UIhOSnS6KsjsTJCVNtVr0sPjm9xgI3nbje/Un80vDj7fTltUB\nBi53Qv+RoWeXh1czwQoInY34D6ZQX5bak5L8cL5I4y578wSUNb0T0fsK1TzEFrSTotYCV+KSnLWM\nw51UiQeVF3OldbPdg75SfHnt3C833fw8y/8nhSPEUrumA5jzRvwrChnauFBs0KgiP7jZM4Jp5fmA\nBvqiWvrBivXWIqmRMaaO1NtVjp70no2mRBBRnDdDF3CRJVKr6yOV9/hnQAGPRJCMdjEGyJpC9+tm\nFxb3+S/hFchPJCmSslvIkLVREAg7wBRF0bU881QJJxPYtLRUSVoM/DTv3bbOshQLijAuwOsn+2BI\nfUIoTm/+hCrEK3j2+3JTJUHT1OL2ZVDJrhrPk57Kjvf7pwivMLMCSB8tlJDoyZZyqMfGO0pUn7rY\nnaHDr5q8iS4wc1z3WlGGX1CPS7lB60HHUjI6zaAW3vWKggvpQ1QlZHJbQ81P2n9Jds7X4YRAjlT7\n3Z6VER787lM2KJwlyvIX7KOeT608e3o/J4YGC3Y8SjJaVCAcTFHW3dVBHDiYr8xF8pyIzFW3Aa5Q\nn9/ssJP7oL4Aa+dFRBx+zOrO7fMHFEj7lPu7jk4EQARQE7XbIgLdHH6QlQ3RyggN0cEhMKZ1jTHo\nYKA0j4iE0J273unX+UjTfta8/HbgQAegd4qExlw8heM+H1i5uReshjdkrenxCVvgnWeN831YDZWN\n3I7v0ZZUOjWy14/p45H8hALMiVCNbnZybRLdGCS2pDVAbjWqscBh74X8CQ7eDZJAAjubao3AWOBQ\ntYydmCV5kItPimALaSQNseAri4X/Jzi71Qt+gE8buadfAdnzNruKTXUk9ycmBeCZkNY5obM4/gEG\nQzGscERSioRsD5v6nXpVji1+BUujBOWVkZQ9y6fMadSbQt1b0exSaJPbWoB8SuN/ZwPdq+SRjMsJ\nk3vR4H1b7KR3BClW0XS7fepTe9ey4NKuM9JOi9R53Zcbe6SHqM7Phgp3VM3GzNWnX0+E3FuU0nBc\nWCOiXAte/IIwTDvyNklB23wUZsw9BHxpmbrSgu0K0M/vTgzVz2hBypX7YlOYM1hJomhYmwcFqHjH\nWKNPe4zmD3InbtYhIZQwcyUNNaBWykL6ewDBIN25rcQt2QxA/2KfeAaQEN22jR9BWWTd8ui6y6km\nGbcRwjjDMLWG4TA+9kWZqaeDdf17PkF04PVHGLFcYwjlfSIzKn9UjuHuQERvNXHdoGq3ejb6vlE3\ndOs/RAFOJ7dVYAiQ2jvzSAxEcGXnkimQSjW9UJfDVlYeh78bvHA2xhM2QrkzQ4liXMGr9+OWWSSs\njiHNMA9shnT3tDL7wa9SWqzUSwZ6oK8xAOQLSYaMfRnw7lPKBV/d0wIzcX5rdXndfjEbxoj8QwB+\npxSkK44uEnyDyxAm1jPcFfVtPMhxH9GO75zRNGHPB3t1mvRiOwAdm07U/WDUYo99Va1jqtW/bKov\n60bLOoIFRm28v6L58WjbcxUjMZ/mXDAqaHJkThdCUIHTmMNdtCWkOPVL6PxlghdxiKkRU508tqgO\nkB2xlLxzDREWciT6orIzp7PVsqYPs+vOHiKOhjOiwo4kuR4+nl6HF9lYctUpyFmeZFE8aZjmFbya\n44/1+eiTjusZYZCxwgEYOrwchrZ5jIs9DspmW5TUO8yDUvbslQkW7A69bJo0XA/NsaLoAwSCtBL+\nCvFJKkTwL8n27h382dFY6LVA7/WOWLXX1dELenDh4zJvsqiHbivEQvzOTpx4wCf4xNO2OnNum/UW\nNWdILMxutKU7x8kqFvF9AvsoF93ld6/6KVk5sMrvf8BP+LzzhN9NVsYDgb++uzd+sXMqPpd9I+ZV\n29/JHfUdHnMEIz1RJr5EfTc02WG6zu5IZgWNu4HfSO4rO1XBhr91blETnx40fIrRBMFWy+kATFtz\njnsD0M8934SGUGzt2sRj2Q7buDvRKUhqyF0SdI0dEoaru7LYkH/tTY+ytrsGPD7aJiLCDu9ewms7\n3nZXPHXyT2dk69FgY+W/rU3jU6XVc+8TxthjNnHGbsmGkm7V/VN094K+s7JIVpkeMC1lPE+J62il\nJU0lQLaGuwE33yCupXtANtXhff8PNKJf6vraa8ARa1kvkLBcGanqMhdQh+3SZFPGproMC00V8B6y\nJ+FMYJm67jpb/Tg9Zvh0VM0eGVaUK7+Y9oDO4K0zF/CdF3aqO2F18fpaq6MrRDE8uuOV1bWxShxu\n9dsyrZmZzxFH29vXbkZWbmYTBeR6QjgBVcbAKN24AzTOGQ0SX0PwbNeXv4Ejk5svIsrdI0Ta7oqD\ngdl7d1H9CfFs/7b6oXjrJdsqm7wTPAT4E1gVrVrzQFhaI2QQOM3WHtGi2ZGhDxDN8nGnb0rsRG/4\nD8E1CqeBpNBl2igv9/FysAI7G2vppQW3+NKOrvyYqs4l+ub7wnC4MaQ6OFix/aBsHbpJYsoq/djJ\naxQuqaT8hios8M3eIHlj5+AGhHIIB3EYeSogNjvYBuXv9waqlYoDaC38UsOPM3Mivyr3itKRLe8M\n83NfnAGz3AfQ7rR6fFUyFHfcccWCRq28u2Y+izKBMJ9opAb2HLZrKO2G3fml3IieQ950W79dT3fi\nPIJMbW2h/SBoLICOSfzWzfmWtgw93xPvuOLIFIfpZyHPrx3xJRnsyXuUgmNUTvj+LD4CGiM9ONIo\ncOmRJ3isGewyBi/hNz24f/nm+q5P9BLxc4u/89Mu2wq2Xgn6/URB5VQooXskR+6q/amMjOkpjcKD\nhAW7aQvOaGK5QwJi36bPqiFUBqqyIp94EeO5IJnKUwznRiVeBckkYfsJmKngm/StddiVAVasnu+x\nh2cvp4ltqZAzn5fUt8a2/sWOh1VtF5yDYQ0OsqgTxv/sEvYTWfMOlQHQIwUpcQ8yjURh4Vu68OaF\nQnXtT45HpXuk6ZyUp8RqerVj9qpRVntUJ6/KT7B9qtYAeTkhZQngziF+9lXw3MYrpEsk+GwPhrz+\nQ4NV0d6b0laA4FNcJZ9lDpwNMQ2hn0SpL4rQMJAr1bRVB9mA219+dY0U/ZrZpFptJflEv7ZEB6xv\n/V9Z1cHAuj9vuuJjdFNu+74hc43bklXzE3Vm0pLdJYuRD59CfcE/Ujf2/darGSOGzENkdBCVd0e8\nLDWiWWIWZnq2GUuISFnlz8uPoNU5hMC35JwJriden/eskNG73orAas9DXhLfPDBaIBP6+oLdYFfA\nQayR9GCKlhbjYEED+2qa/heheRwiu63hIFazMBSS1dWaV4SiGNqegz1dL7AHCNYIsJSDF8PB7REK\nG0mzp5E6dyMJatU9475Mft4v7hFsluhtL33iaUGZJLCFGhZYS1HIRO78VC8CC2HKhC8DeMzlMt37\n1mIQuTV3/IqI29/B/g0HmgIO8n1kFzSXria+TIpaiy2vYIDhQTLlNwnvIcN+4erRTXlWYBxJlcu8\nHBQAfAn5aYaljat+bZbHJuhSJ0rbj8gTrfGsBwGhvlZFFgmiZ0mJZM3OviohqixqDsi7619PI2L7\niyytE9NVg9dn5cpfSFdHYc6dLZo2Fld00f6fFM17RY0uAzsKZe5hYE8Ec7Uf6rXnM46WDmYyRWZy\nWtjFxitIFQ/FTj0WUJt74mWv9U36p9T/L5L4UhAecKfxuI7cifB+4nsaJ3gP2cMCTNzHkFdO1TDJ\nv2uJUDXI1VjAzKovzYqCrqHJPzxwZ4530SwlGUHurLBagHvJ7QzDZjg9HtKgDP+HPiwPsudqN0db\nY/ryi5VGYGGicvZdb6SmNlqlS3h3czrUmf5Q2CyVi90k8f0ety/XJsi4DhtCJ70s24s6F508ZGNB\nJ0ueasp1YJZy6j3FY3BgqhjfhtNBPUPrn3+plUg5mfP7oSqFti6NRglOOiN4rX6v/TBowxu45VjE\nBxs9soojbuxii9TMV8uJYVzQp+Dn8NlGCmQCRKyaxYCjNz/mTJQ2DZpPKtoD8poFH3gH0SdwaNTX\na53KZytV5Pme/nSAIG/isDpZNPoTMn+q70w91QDGiGDNH9i70pkCWZzaLzAhqPt5jZMV0e8Jyg12\n2U0Ci9THdufXwA6IVnI5SxXMBhi/xXuQG7ANoCGX1S5UJ9hhXR/7fzS5sMs8uLHnqE0A8B4k3PjP\naKEq2B8tgyO/IfX89EK/c+BR0lZb43nf0d8JLMmas+29dbMRhCOkprwPkbHDyd/RXTGphM//5rJ+\nlVpk5q7CnCP0sXZGi2qx8rXZqR+lSLQxYJaS8Mv4kb6tdnrIwqzpbcZBqLcvbhi58bG0NyCdOzdG\ntAj833gk42sBUa+AWmY3wAXmgAXJGlYkMeVOLT9C4ZOVB3ZoeeHmc1JpBCWZw+KMleqGvt1wM4TX\n08C/bhVX5C2fK5zak8iz7xTI3FsgFVZDMyvug9nJ+AthaZ2tSz4u5Z2I9zUO1+Quu15mpOA3nxh9\nGHz6MGSYM7MZwK0QLWhBEiOcSFG7CjeMTV5GmEfNq2/1xiyJefHRHN5/ncbdM9jJi5UZ9AmrkT/y\n3bWuGFoT4RYHp8nc79WP1+JlTfABuSeeFe5XCxMIjgaig84YDv8NlP5tpPCWD/3mVh3oVrD6B/pU\nbUzHntw6l+oVRXsp/A98vKnupHziJk84H54cKTkfSwy5kAKRiHuXqCZG4Ja/sd2KUqYk3SNchwq0\n1IhUHa1eDtS4ZKGcFhrGjS6RNkzVhPIQIULSYbIAvCM+uiXNBDWDtKWXN2y7ORJj+wVcRbRKaQhl\nIDlrhZRczmny+BFn97eXrTWhj/wjdJ4wXT2uD275/tF9cjyC8qYjKw+O9JEv9CpPsiYS/+jj4rnM\n6PKlBcXSpEoJfPSHWWiP8qddYlcI7klPrdkbLf0Kc4PMqF0LPQddxfrkZ7FBzwREbjR4lzKzrigx\nWvVn/lS/1nYxbhiYiOVA9BNGh9Uz611i3toheyDmiVvrOhJnBSMyn8DvqhfWKT6AkXo/eEeTXTA9\nqWGRJGfHJmfoZvOQEYXGv7xQxKzsf/8VZIBW7g3w+h/1r07XKDwkBJpxLl5WjDuG8EpIPWYnaKk2\nTmobNDWjxF0QYwtK9qeM21ZBmz6+G6MfKR/p4kFzHgz4WCT04Cige5qafA41hgk3hL/+YRqK6UID\n6q4hAtT3y7cgFcYPWUvFBwf1T6sqxPVygzfZ3m0X90wtcfVfVLW5nplCem818PC2qDeD8VODbEqa\noFZoKStAvRejVMU4qlFlJvpMaHxPw/xF10jjzsjynEzrwvLnemESyjc1igohEcTaznUZ2AWlvAyS\nK653iGNAVH+369M4eVxYZjw63+KINe6exsS1sQ2PfwP1FM/CAms5seqg1G5MmUgryOzQeWORWAFu\ngcE59ShZ5rRBtMXn0r8zDma8wg8rQ/u2jQJqIeOA+QI61RK+dWrDTIl3AyQEYeEZODuX1NE/p3RW\nsOjjnPuaHIUVqIdZ8CYFLe7ShvySpF70wYGJnZe3OkrIAm1KIM0hxVU8+Zfkivwpq1KmtzkP1pza\nFMQc+Z0en7NC5HYefmv+GF5fl86p3mUovJ0F0hY64k4bXUZaIZlh7c6pwotGdMLum3uH96t/SiDk\nPjBEPo5yViIgFfSKsAU05jG3qwNVVUUjVlzp2P/lYR2Boa9O6P40ET6Dn3xGTAOU2MAUQDvPIKoL\nwUB+xIyD28f0CTfACy5nRZEYzOkbpEZRbTWt9+Cg2gO0Rk/GQU1kN4oE2F35ekMUoY5RxdW0vZCh\na/klvI1gusiJ1g88lSFz6zQK2DUJCWFU25r2pmHUQ9m5p0ifkqXpHQzEstnIQPg9GzNd6L+7LpF+\n9WgxMEIfhdj8vnXA5/ENxoFPv6uTi3A0HCug/UG8JUXm2beZpijh+YbtlzPF8T8Rz3mi3b3y9quF\ntjVSYiMqnGxg3ESFWyTN/i2w7b7vNq/uAw8mVyKHIAypNuABMZQZO2T9/miuxtXcHmarLaU/vPrO\nwttc+/kNUPhWBxwRVtsD6zU+tA2TVsau5+eGq39zVX8F0RtgIGP+RBegndiWHkp363N6Mce2tlXL\nCNW5vAKP7/1kIYWy7iqtwEbE0YOP9ZPEHV5+0kVGGczT8WR7RIxxXG83cKskLAxaLLqs8zs+gF0D\nFFYnpt+gK8JH32ZbmEpckQDSbt9+oIwFBcU3kqrTeWEyDnpnWdpMsaQQ46ks+Qjby0t4i0EJkfV0\nGaIlv3Ane6WRzu8A+sEp9XHKl+9GmOhtW7xvoQJDBD2wT7kEj5GfL1N9A3m0/wmkzNXuOFJzi041\n7XR7Ly7ylGRBGPxgt1TqML/Op9U/Hd3C7zf/eQoX2bVy+H5okuFl+KuSdokGs8GsAmU8v4KlijtP\ntiGYWo2iHD40+XL6pWdbv5yl9NSf2HctPKEdfo1nieC4dCnc/UqgdylWiZgh2HdEhAronPH2mE6E\n56/Z9LKGIPmd15tEnnAdNzQkCEhCljy8m+udUxMhrjiID7Sk2X+q89x/cJKOyYefq3gDJ/nnYgNC\nWWA/N4xGGftrPdsFzDPZ7kjIHD1ISu4oB9Kyc5DXAEYplHiZUjrgeobJuIxYxbkYLmgGHVoKEa5x\nZWhLdof4NlqxTJJgdzD10RSosYdKN4+Bn6BmiZWr6Ca1JwQV3JZgeuzyG7DS9jQ23K56VM6z+orb\n4juecP9IgttFifeDMbrgzZbsu2RG7AnMaCgoIWMgZa5WrhGmfWq7aHFd8M04Bb6oZKKdo8iTU51u\noEAI8B7WMf5W3L4xJ4IN52IzykQOyaSaxc7DVkSTkePRNTNEZ0IomW2Aju4hyqtBtVln/NnyyMc4\nmH+oVYmlx66ZyJG7IJbtEapiATycfc2hQjATRZl0YEX8FDacYig93hlySvFGogRhXuvcvhgJXnrj\ne0ysTnThj8KU708y+S6OHXLmueKIvO0sV+yUa+pZIkON+8an5T0bStJLH/MpOy7XQqbdWHtxinOe\nvggbYY/S33/HWxEXxbEQIvRjk3jCPneaCCpL/kA6lg64BgfnKA87gBNcIvQ6SF4HR3DSJG9857Qe\nN/UuwGrL9mpstZrswGX3rrRyADX0FyXwwz0ZO7entAgzJ6P7vQZJ8dYedI3LxVztlgl/ua+Y/dIi\nrwKTRyOFi2J0O8dmizRlWkPvBVF00MekMm7AVtcY3DG1mJvhE/hw/SrMzTDGQ10B8rzGylw1ciIE\nkeh29VkXbJpIR0ZQJE8Y4uzvxIquNb/EGprZ/ZGX50cYTti1fYXZQpUrCJKUjy2/3nARQbN1blY3\nmxS/wkctjiAVTSIFAp5OINrUWxgvYKvaqz8pd1U9Zyi9h3sReSMUCaKPt/fr7BtT80RsFZuu2Ng6\nX70JMfAzRYsMoYUrNeZGBN8bGRTmTpEKz/8w1uOiWZdB/wdwCSjc7nxaEOueOURGog+Y7K7ikCYS\nidoideB7aPPFGTRAZk55MbSH44+lWnH9KvUmK64HOD6IhLhGhUmRZdfdxpWi5g2V1NsQo+wMrhqh\nsqe0fYYj9hI+PuVB9z5SPkyZRPDmPICQu07GXu/K5eFPWGRa5WBFeHuMxv2tV+gLcK6QbytmuYe4\ne17278LhHnaKoWIidf5hTvcAOod16WqwyMZ2rtwFbWpe9SOOOm9GL8HYxQgTMKKeJks9Fro5Uslq\nU4cL4Tzbp0ywpkcLFvm3iXc8Vy5SuxUCmVc4+43cyS4Sod6jJifNOkytbD2AFrqPOjILO2fWh+1G\nla2BbntLoEODscwc4KE5rPowRSCJq8XOZgKVpHfzGaxx5Cyk3WpgL+AaWGmrGH6GQe57CLjUl2Kh\nahbFD4Zp7uB7aK76bb8VhDtgaJ9XhbwJ+/UJCyjhZGJnwcNWxCintfkgY5BjJzM74tbiGU6lRceB\nkyos/Oc1jBivG+oxHO+f5agD5kWfsAMbre7nq5uIYAb9l1dz0rkfv/Guw6P8xQ3cJ76zo7ObuWGP\nysUt4J0KzGvnjVsz09amM+gYyM+zMZ+23/5OAtZsOm6TC7UOR2hNSM9RfGZCYxcq5BjZ0fOiar3V\nKpzpB9XaGUFYHxvIHGVbcrxnCGZ1cc20E02fXf1poBbUgnNGP9eaDRH17NwxkDxfPcusDgY7+qjv\neUHAajFdo5uGYyNsuOUqXZ1g9omnPPUfjRAOFIy+13Ri3L7m+JAXMs4THEoWe/xSF2CkXho/EvBL\nHhXYJnlknmjT8BTuBS5wPFPMwfmEi6D1T+umzwGbNnxdmQMkcbr/f3i8+3sGzDUttCkfG5BGuhrJ\nHoDOnDBWgOkOXZvSxQnt739lii7suUHpqNEKx0VETaKvomhsbFXNOdXF7ELVt7zD0BPNIUeSbGYb\nlCLTJbrLY4R6Qs1AUEpT/22KtwsDV+Op33aahSAY+fBbTqwH5qTTr8f4lYRVfWCeCb6TzWuGNJx/\nX/SMeFUtuxHtgFEIbHSMEHGsKALTgur3xcb/n6p2i1B3NNYvQrmRGBwY/eJN2yne7k6OZBssNJPg\nvSpMMIAEfmLw8dDT/U513rdm2R2LhSVCGHkIEb1j3waPlgm/+FblUc78uPjvqOZh5hko7HmVJ1B4\n6piROfg5pj2OAC/rf9iHWO4bAaC8Va9Dj7rKMCn879OlJdq6IH4vgd9R6cRdrXhSgnIJIvBZqXxk\nX1HazWXsHDfofxaNnrSG29dy4xPjtDUG3r0p364Yb4ptCp0gLbmi9OOiopWmwWb1SACIn1EMgf2a\nH2RD8RaUIhCsV02l2gp9U0m8qQji8i10pFyDLpGc6LuX2YrumERnKMnvvBsPtTA5agfXxF2SoM8F\nFYo7Bbhux0BtQjdjSZmheNj2aYpVCK34ljOuPo+bAOt0ZrIN4h+qYIOjBjg4POJu+P6cEfiX2zdK\nm/1URKcux7ixx33vbGgH4OZTz8g85BH5JhQU6InftfQYej1YR2I/+kIBpMciNYbX6/HAbF+Lt0ps\nxzbPxQjsmnjxvUUfZPVd7kW+q4LFtNrpiyBHJn+r4UPJmxVwFM7lrYQKxT4XZ6J3PI/U3hD4fGtL\nCuO/3sCmmBOQQr5d7GmitEkhJBUDsyobK0TC7jK128mjjbhjFT3e+/5n3Il+UKo+4xVoQdABtGfN\nIYLCeosUBSC8VebxYsIA1MAR7gci0BjTTtv4QpcRopT4D4ZpNR4KQdYbMxsgUnw6gEuVKaLrtJQA\nqZ0ZId/uE7iRfFjLvfQVg84KlhyKyJhi03IM+bhKQS+vtZjdRt9QLxPi66Ym3ZAfQx9HfrkpBv/S\nGhCg/uY5eVgLclyYzQ1o9eZWl0iOsKchqWWmDJOJ2fiemBmEpbvBftSgVY3Zq8squ/B5QFITOBHs\nKl417eu0Qlw/REpXnQr0PP+Y2kfS09nEr8FrZLAfYQl7YihDprFfZE0BJ8FMNAMik79y/7alTgDw\nu7JZbsTQcv7vYZmK1l/Zjk0tfOodz399YbORLadujbsESRAMfiDGbS/xr5OUArXD3U3Q3vCUHVm1\nc1W1m7y+FuD8DgMP2H+HfkaZwtDVQ7TnMmuhVbcqJTY9B/KnwBKHDCm78Ju6JmC7+Er92KJwKqNn\nJoCVnktljhK7CrAWJfo8obMycMMQO7J4qtopcdnbuPnyL2Aqdz4ej6NM7zGx1xbs7Gw1fmuQ4gNS\nuqIwJj+LyQieLBjPImIVP9h7Dr4ZbSRt73ZS4je3vS+QwR1Iv9GctWJacSQmyAAJopSCeDiZtoOU\nWm20kOHO8qvQIZ17FMPBNWHqDpMxmUKVLgYD6XIJYO8DJrThraZAlcflaPfSKrUZrtz39m2jMyCe\n0azm89solF0gTfLfLuYJdat99ReiqDguD5IjLy4Krwll8DZ08UZEgWIjna57CS2vgPZDBQidDXZA\n+cyyA1Jy+1C2Bu0rJscqQnTx6UG8JdFVXN+YpfH84Q5kNNvsnQp3pbbej3c/hsYXWKorcsMPUl6x\nbmoM1uMlSflx4VpA2lhnj/LsZ6Hnvx94RpYYeCYwqoANS70GuGmnbEoUaBaItMjCYOrIqUTfkpnZ\nrdqhH4HMmJyvvol+GhFX1Bt/0rOT6sKWpf+q5LM15Cdw0V2Utj36KEprWf+DNy7YZXVtBZ+iXCGv\ncLkrYK1DADfrNR6skixIVrTzzU6dm3pSDCOVebBu84KhihyDicq87gEIgT+fC9/w5OlfyiImnQGD\nI+hw7Kz/+jRpA/8nVeL19UP0UCYbLefVyQknwWVpVocO0Gz+XBP5rKvGtCIclmDE/RPaSqXp6vYf\ntG7w5a3fTZcJ9CNVWX4of/w/FxTRoTv0Xc5dDk0zFy38nGTIuqWPXrELvh4+xBwMc1R/ALKFf6N6\nnLEFUiXbizVH+u4XC0ARydcv9CwBMWsQZuNqVgrfkoDIJi1u6Obtnjopw/j3UNXCKG94Gs9VA0JA\nDBkJEWoK78GBnY0Vu/Sy5LflXkTZUHIYvZ1GDjr/nDMByHAEz9LzFcOH9QKmbEojwuwksmWOJ0t+\nDS6xeDTqNKxhFWLJoAJJ9YNbd5wkJ3caD/RqeDSL+JVZefrvRk/RWK50J/agiEWj2mC99IJlhAap\n1txRnuiZ1DCHsGB4hnC8taOinJGG2xj/4KKBowRHqdPvh5infCg9Gv3N03HZncsyJcssn8jvxEb7\nPFiNv0EImtv6f9IQylMent9cFKYviNB6k5drxd3W0O0wnHlqbAKrKm1eGgBtENkbBbTZcUalR9sZ\n7qSe3UROTFZB6EVQ3q0lV4/pms9BOV5YKoemIjYPkA3pBbdrIQucpFodcXijEnKHzcTnLUzeL1tN\nKM75WH3CV1RxZ0DE6zC1dYaznMNpav2ifKzzD2Z5jIPp6y2XtJELWi4G5kl0wTpFrTn+DyGJ9Zh7\n+wVijpHvUAbTA3Q/poq/rnC5CtScYMmWOL/HVtAGbn7srj9yeRQ9an8xzFtNlUOQkIUTo7RzmpmB\n8h7Tr3MzmeAR70wyadvQgDKJ9K5j60dX6fgYLFq5Ie3XKrCqWXKhkobkl6r6ZvI6SKiKXa1VVSr3\npbNTSPxN95WbK6X6h9QtqvBT2d8zdCSXa7ap5SblGpQ0m2laVzevwcd6GBzwcyLiM5KwHGmHnMNh\njlMfhHWjk24dGiDF6dzpH9Z8RM96J3sD9oJ8XbAYCaXmHlJv/vXm2gwgLo1X/oCVELtYnC9Jo+EF\n/6FVW03xsAK35APRsQTq3TLVhpsxOZ0y3svjwhcPTYP20koqg8HcGvzgOzRWEM5TiYahMMHa36Hh\n1cFJiQe4s+wz8hkTjoiZAv7hZcwi+4bhcaBWeCuQ5A5HKE4R3Jh91MP2/+rSexg0YALJUy0fnl6f\nXNQ++jfDILsHI2S3ED49Kn95Ak4EYZQnNCQVYQs+INTKFLPasI7GF48W0JpxADM/2sxgjZB/0RqY\nc2Kmaq2xFTCRnToxIc8EBPZUiDFeVabYpqEAVzuTTk0WBnEyvsTXnwJwye9dgBL48uGI0f+MjPrg\nU+pBcrynW94HxSt/3xF88khbtvsynmqIgM4RJEWZ1A/i/0+KcdM6P59AMuf4ZWKktYu7P66aqvvV\npTTYg597nryI9jw5yLZ7pjy5vSz1b7jQvhTTL87E0FzsUcFus98pOoKbtH7RcjBomy1h098/ODux\nj3eieoM99/ZAagxsSy8etz/3bl5e7iyEAxxImYLsDWDlGjbNicKz/JCxqP8qWiv4mQ19s0Eu8AUK\n4ci5ZGJHW5qIe00WHV40oWiKSXV6ySqOzoAJMbjB9DeQTCnqoy6vshJLhC2iiDkE5y+/L3orjwpD\nPo2CvCB52wpaxZ38AjspyO+KilUf27/BMHPq8nQ/9BMQq64/6yPZsp5BDp+zj0QFKO/GntGUTrAG\nIfl4pcAfqvtvCvaYkPaSixFyjehCB7DV9wOFCiaDLn6vY/ogZ1vni3swYRb/TnSe+YjZVJRgB2TU\nh8CQcfC8xkkeXe0xCUDrtWEUo/tympnH3aT8rS/ATffCHX+aTXKFWdsv5ECKtqfER1KHggnRAEU+\nT145dSlQQhMwsnSwhhuzzf6oM5xEVL4hHiRIzuM4L6w73NT0Xr/UQk79LN3mOvzosUWfD67acC7z\nxf0pZKDZf5cz/gKyPKTjuh7XzwCvtp0ikRyV5Nyn3waEJJ4Y5ypnB3Tre+0wB2qzPRQAMNha2iFb\n1PUpNIM4hu80Zpjk4ImAiVR4S9W3BLM9MHsjHvEAlIgFv21CdNfSu1X8qyDkZyMuCcYhOgcOILjy\nEfOWoIaXP2jOj5b8pLkeIKLnDYGiStgooesUh+zQcIJMbIs6qoZC03WD8zMiJWHbs/2guyM3YH5f\ntujna0FUMSM4nT36tn2KUelubANwE/8cnKQnn1ISC0iBpJEm0WJs+hMn0aCWxpPR4Y12q6HB09Rh\nyT2ZUBR5Gx/xMnBdNHoip1rym8nl5s731U5w3f1ed20uNytR9P+XzridurdOwUw6yZrHWCcXZokt\nXzy7Qc+E2ClvatlUrF0lhlNgcsBIkCgP9Zw30jNxk+GT26i+O1ZtnQ0Rdx7CcT6XaEfL/akp0egL\n6s6gIWSPf3inJXyCEXoKoaMUCQWS9aBUWg4QpXsC4a3ofgZjMa8noC2tmB4HKHntOE2bLIIkLIXl\n1FrhwW4yekbPTBkOpeVMldAfkAuTqWeGaK2Li8/JPoiOjW8Oy7mPKzZzeguptOPYJIH1dgmkaF5M\nbvE/zVE/fYfbVwzicl16i1G/lxNUEc35oRHlF2N+fUw4FDolK5YzhmP/RtOON5syyY63Pc43u091\nHMKiSBstdJ1ynSw7uu9ZR80m/9OnmE7RgI9UfEBhnNvuG6aJ+V1ZX0FFsK/IqTn4nqS6qEmham14\nAthIgkUSt820Lyz/+o1EO7Mb6Z6Ekup0sfnO2G0+v3TyDXQGjD+7U6poBRRb7knsQLP8585ZBnbD\nPG5lD2oW7cmiSgRCQF96t37t14EXNnLUlz/wBepd9PxOs2aXff427IcqxyfLsJgwt1/U6RALDXo5\nnbJGrAjmLjnGjyhb4sNj6u3HneEOJkHPZvhprHQqZDSs6d++POHuaqY1dcSN6c9qEnxpYMM9eUB9\npeYC8XMottR/VEAVL5G3BDwg65p244/w+T9ADQe70KNVt1V0pyE24fRWw/gGpxZ8c/yVVBIIPGLM\nrSP1S6wc42qRN83qEWMJdJRb+/pr/mI9DsCSq9MSS0MQ+7RDgKXUra24ELhEf51CsXW9pO8YFERR\nrBvLLWdeMtNwkRmYg9M/8768u3TBpUa+0zCDe/bI/X430IywuOVk8X6kb6XcaWPUP/DZnC2VSY4S\nMkZJW+OJFHBEJLg723jWyh8o4DSU9NOFhiOHsq7Gglb8Oda7Pcy3Jdhuo4eKpDdWrFUBizMJDmqX\nhTT50Q9zQkltPcCG0UAWgZSdNyQGdKHni6y+Atya6F5fw/eqTakuE3t71OktRdmdj64ebnJ/ylzm\n6NDhz8oq03TF0Fcv7q+jg9tPAPOVLhZ2AKFXnPFY2KaLhWFR+YCfbEn7SP8NUPEyExsnL4rTeBEv\nZNfW4JFThBGnGlD4NeM3hNjszojA97Ozxix1O5RPNaMZ79SYQY7VGIhdGM7nAaALynBH2RoM9TYj\nORA1hxe83VG0fcBNcFCzLOTph74smLt8trmcYIOOcz9alW+dBUQ0EESD+hKXhnbwRKqqCLPxW23o\nmfp01Hm80UmgrXZUfcA9E2XVi0Aqe4laNTMtwM/tVYuqkcgaTxyO55Uiv5zEUWc2D1tvK+ge6cKY\n+HdzSgEA7zugP90H7drFpkvsBI5t63p45Vo/7YSXK7a2NWcBWY1aTxR1YWP6I0HkXNvY/0/cK8LW\npQ3QELpS5tcj7752bdYESY3phvakgNNGbQ9OffvqDpq31fUlSZozb5GBiG5FtGynX3xyt5dm/MM1\nkPdyDh66xemOfiH9ZbfUjNByZ6yTqj6eywa58vR7zJ77JzepYVPbE6y1KRMGBj8nuO202Y/1HgNQ\nA2hRsHWQ+t3Ma75Qs4g8u+Qxv5jdizh9RfAQtn8J/uu+xAzI6wL099mKN+DknsPDRlQYlUhbUJXS\nA/K4bXpePcqJEu8GA8ccPnuoAI6kuaMhyE0TGaDw9nvvgCoSG10yHHGHUaUY+2diY+Qn/fAopSCM\nxPiIIikwe0PaVdY7pWtESxOya1RSUvcJU/0XMfZs/4xxL2DxyiicOLDo4BT8FqVAHa4KE/nAnU7z\nqBTOXzd39lh1N3QilKoWXDL1HMBsNSd0mI7rta0RdNgrk/luftCfFHgtw9oNXAka8gUh+rzd7PsG\nRZGO5QWrmEvQ5CLXrGhd/pJ+9BfHGM6LrGHZCRlbFYSzQGW7l6RC4R9/V3C0r9GNeIqLKnbZZm82\nk3SA2oPcTgICdxjy+92fqVGPRbmPTz82oz18YRi6hv/Byo9dYDNzJmRxuxOKeVcM11ZB7eMblz4y\nMy1qZdWf6RdwF7rw8vAOTPlpXfACCLAGCQUm5YssCyboTM94aWYCyMARsDLxrh9zk9IPkvtNHhq2\n3MxpYk5K/R46/67NhoSicRRwfuTXKfaRqY6l4jgGKpbmqnNPJQw7gRc/fIqRCGs0WQr5yTrtdjQs\nehIpgj5PtPy4vEGifVq0GKPnx/ocZIBosvzXiMZPlw4WZeu7ItO5Hm3zfQyqMXvjyCGDUpWxIKCi\niT299UMwQ9Baf6ljJBPtzJFJSsMVoPcK2CoFWENNiiWi+kskMRKLhfofeFyMiKypczNKGvHtf42j\nivjtD96WvizAlDxyMIq6ocpZs8vnLDSSqaDLJ8D75DHQC20VAPDJnmwHVNW3QDGwL3odmQdZ/s3Y\n3o5Rc3CaSuXfLwkZ7GkwE3K+2UlHw8dAL6H5zZcaiVmLvNpILfi847/msw7NpnH06ivKM8CqgkJL\nOOMeGHx3nQDXmmEa5WBpyH5o1bWvcJTBI1xrhxZN3rfxkWL5IHn2aqg05o/4o1+rOImFCtgl8PtF\nYkIHR/eLLbfdXV266aALhj1o58RuT04KlTGKJuHhicFOYarZVxXcfR8a1t4YJJ1Mg6bwYe7SiQF8\nFXUq8IfSxM2vqtlT0LdS0YwXXn25w3ACT3u66ARc/dIWwUzLgCjDzGy/4qxrWtefNUQ8Djrp5kyH\nnqfq+n/Dk1zs+5lJYUClvOu2mvuNsYfVPhxwrhmZDitt99SYkC3xXTFoKct9CojMQ1wSPC8C6Vw3\nsHgobUDI1DrJ/4OJ+9xlSGF/WRfFB6bQAdIF0zO4zpPT0zeAREn0L6EjKgeke42U6hyJsLQaAjTi\nKbn3Fo6hAmTz8xRqfBtEKl1aALppUoqDPcj+IFguZh6P7lvaMZyEVKdK/dH0NF3dO595VeRQ5v25\nVbYTXHvQU759+k56kMzq/rskCFXjvjPlVhYNnKgDDLHQReLuyTCm26/Lhjc88ybVV1cF11Ec50Zk\nKaEajOO4Ax2c9qpIwfXh4dq3OJefmIp1JuA09e+u/lwPztSAyC7djLynkPOIuyCz79hCmnOJTFTY\nmzw6LvpwAziuty45Cl611Z2uSDj6/QewS1VrC94Qo/tHaECuNHHWhstgR0XoIsmAD/j6rgs9SQ0n\nK0vK+UZTRqQsARV9KQnXZj+MjmMwjy5QSTtsZAqrkSKlLlIhtrIMnozlhlpDXVOqOrkI+iKnelZ4\ntBk335sbxWpqQz+Y2RM7FKEv+IyUsxvu35NcrGlyKHLzdwX9O3EepgVKf/1qmDLWfngtIGOxpK4r\nEJlpO6pWmisoBtVkDjnUTdW0CmPPAy0iy5Xqg1M41FXuew5OZTw4MOOaERQPnhNvTZSxZ6XJrfFW\nkm45M5xr1F3uZ10E8kQyisVJ7UU0ln0l08asBBayPbUica/FY9e54IM+lvhNDar1TIJg/9CSAA31\nE164qiWXbkQlw72rsnMvi1fVjkQDtGlNoXB/O/08Jp6k8/jiWZ56rX4J/uogOqVFyw3+DByr6rUh\nPRM/O63tAJCMhA1SV/1rDx6UuhoKYM+6iSOY3wk89SYkcNoLLBOwLLy73N1Dm1Wmn7VGQCrDhmAj\n8Df9utIlPjT0ltCnchEcO0RkcUmjgjsEuBd+19P3QS8E2Iy85KVVFVsY1XUpqAm5P7qEz895h/gz\n/IHtBZV6eIsdlGNgVewOiC333IP4MiZa/9u4k1tGnFTz+Ct4l2CgGteHW+TO8qk/7K0ORZ7XQSb8\n5vrATsBkpNJd9EYO3jMI11kSHdJD3ZJSJF+7W9NZMO827hepEOn0T6Fjgwfg3VC4w9H7+VDh5zAV\nmmaCl55ImUWUt5w1YY+bOMEzC2Dct7MoIM9o4fZH34VQseiClUaNhEIhGVNjrVYuo+7b5CDMBHVN\nm+BMOM02SOuOFebEz5WzM/NitsAxZYCy+GMWxmvZBXZUlTELPbxJgk9x2q7X+1fKi5MZG8DR95sG\n75ifZVZftu3jvvqABYjHQVcQRC0MD6JVdW+RD73aRmB3QlBtatSf8AbvAdk/g4cXq6mva51oUo7i\nv9O4WsbdmwH4jnaaTXB3wZlR7UVh64QnvwuG0tMipemQt+piwPmPuqW+0I1D0CQI3UTk91a0QJZS\nmjwFoGwIWiOvDK5mBkXwt0dtbljs0SfMaSbIJ+czsmWjpM2vkEd1+pEdflrZuLlbEizRoJYiLHcv\nGsP4zWiLKiOg1rKPMJ1a1kOC8yUEnsECodxa9U+dD7Yzg9yQ7Ziw8MxIf3xMu6xJpez9NAd5kBX0\naYoFyjsBaklfUh0j7IThva4phv846FFdGXY5mXSMIvSFhgkzCFwQw9YL6eImytmAGHiIZ26VMWzl\nOoJssJKrZv+8jMG+MThSPr4shPKx4wnRlUL/A841QBTb5LoWfvtjo0DZ64zJ2rY46Y2L8CyhPHM7\nwWRCb1beQK6x3L1IUAxBEDwb/zhHpUJcGUg1zdauanCeFVbPBRYOgtvI09dmLX4Dh5MWaG5sl0WJ\n8ZBxAfROW9GIGcVOO6TPf8qs4eiNR1XVS+x34qZzHVJ083Yz8mDGnM+UWf8bsr5Ra0cp3VLTtAYl\nt0cFVn9G18MQHHcXkWjeWQ5ciQ56hvA0TZJDu1V5yiJD9jVuWydPuxYzWLPAZkPJZrXfKx4iJNFz\nc94Tknxn6izOhCGjglX/dqlp3ZNrDCBHLPebyvUdvTTRA8XzXlVDX2rVGjTYZ0Vomk4wHxOCp6bX\n5OxOB7tGjEY6xdEmBttTIWSMThcXWFJqFzcm8vzWaAkgzAs7BsnH4eRx5gOBEtYWAp7ajXHlut2o\nhRgtZyW0rxERE7rAqdRvrve8etXTsjbmiWsWendDgOA13rKTKSSH7MEotD6yGJUEwUszExQHY+/q\n2EeFPnu8K0wQpyRgUaY6D+5wGncs4IO0fdus5EXw4Xg6yji8eSO4DR6Uf1Y9NNC/VHWYGbIMf2Nf\nfAD6QhpIA0HeECSzlllJkNGIvgDR4RddzGXy/vLXvsttnsucwrRasuwBV9g7iMMYWn7EDI0z2Bny\ns6iDkg3Pm3ZLkU1vUIhvuDwpYq9BNzAAGTwIYPpNSLRIe2Zz+ODSzybgTFpE1cF3NwPxMwgKBA+l\nGhSbxbEerIs201JHIk27mW+/jm5xIQCYfZoBcb0I39+2ne5cI7Kx9/OZr3ZSjIfF+tuH+DWRG9JU\n2pFusGScCQtaPVmWNSoeeqzKN65pXgsGhTC88Wp+h1D1uXSkw1S+0KVIYAxdX21QvSr7inv/Kfmm\nJaaVmVQ85nHp0l4XwiaQdP/qZoWYYUBlZ11jSknJSG3MvRL5fQMJnHASDJ8LuurRGkMvfEF6CfzP\nP4alMjxv9O0ruua9hVhvOCaRdWO+wkG/Mh35l7HJ/LE/C0jxc+ZxNEG32+/pbL38DPSfOMzZMuAj\nL1szzXuXTI9EP3CEz0rIKRvCVkMpN4n/nUGmGHriQuDAVnI6VXKBVC0UNj8Vw/r0fYBXTTCoS7jV\nv8ryJY0401xmn3f+2gGJLOckm73xBzcYHDn/44K5CGYbcbKPHA9cPW3bwEsPn5+45yjt42aSIRRZ\nfQ/V8mdmaqgmirQJY9mJ5rTQBpeQOXRPF8Egrr3slASOlFJw4VCiLZO57/H56ehwQdHxEgmibuUu\neFm8QDp3ObsITQOmTdtjCWKdVLCJjNkd2OPHDuTB50saR1c2aQ+Z7Ky9M+7A9K53Pdn+YEFhpOdC\n3FjGM7imWhKjQwCXygMskbJc4BQi5WqRXoeF5iVsKLQhk0i4rvVDr4KN/tYWhvsKUfiZvhW2LStP\nH8yDzfJI9YCPDzNY9KAw7wN42/6M3Hvs9RHWYmhkceifwrccASWyW+5wxrEZG4RKErn2QZ+byLNf\nETTHTxT3AX5dojhzaIvz5MW0815YtvtvRpYePxnBAp8PH+I0QgGb8SpI3zJhS12lPOf8D2viyUIw\noQqbaGVnYfdCy80e6pZkLRBiXLduUORpXCysdX/yd4In/Y7P4pzvLxzYumiXp18FzNFGFhsEGgfb\nsly/KcuB6iBRN3ELkvphGwppO7RkpCAa4paXdUteckDr0h4eGeHoweX7Au0POgjuW0OW/ASXAo7q\np0fDWqWoVXKvNaKJLxOf3pVQqN63I3CndZWdPlJMLYm9pHUp4RlYDSqpA1Z4P9XBGyPkxqabMFrG\nbrzjtLmYA/KLVFeybtlkp/AfCplx1hXa1desGU+ilCLlFdKjjISDsLEQKh1OaydA3I+wI+80J14M\nqjOlpn36ibZvqKEq1edt5yhYuCCQ+5586JoY5cMwoFIOJWrBNOIQt/5+o9ZVmQNqObnCYAaTSX0t\nKU65+B+3zKtEto+eDCgM73Ji3N/GUij2OQd9NocR5iL2ZGhiNA4CHpUvmzEbSMbK3joU4su1ikM0\nGIWHK7dBZ+ab+R+9OTB8JeKFiIqNnzLoHVsWvTOvN+JJbp8zm6miLqLgv8z4su1BA7E0iLH7BHYq\nX+TOYOI0tgCiN6dvqVKeIktqU6MEpoZzdZvziBG+/hTO0aWOX949mCWu0GvNiZiGxtQTfqXkuB/n\nyMlhIzZQ+v8YFqUiAlz7Hmi14fSXI8YtkleZUArG9m2Mkc7cAk+VCpFBOArwI54SFnVVnzhrV45D\n2Z3hivl7v4kVJgv8raokuVuN+lzu7fjADlMvE7tV0t0yMXxIA61wuzjQRyw0vLPeOrmoKQOKESaq\ntcXnNLCE41X3JWPjTYlqMfsTWbcnCzXvhskQLfV/bKbmzNFNkOUC/D0whVe4qepOHCh1z7faiEU4\nWaRaftBXEZbvjAxgo6uTeqXdf449Kbi7VQtkd7cBYpzsgTWr/8mdA5drn7WINDg2PKqSUjkqc42N\nJlO7H7qCBH47H340VY/24iIjnxkyF2Q+TqJZMLnIleK3WDFvET0j9SvDBZdA4xpG/p+HbvQ5WkRO\nPmGznXxZfNPdBJfDnycaFrp4W9Jc/mVYTxY0vczcNQMADlnEl6BxBOyAYP1sUqS/7a/OI2asQ4lw\nh1my09RTTACtj7v9dM626+vyc9/ZvZYTQnauk315/f4KINJ6KXV9UAXiT5Mx85dNJz9m0+1qlA5O\nHFOry6j5mIe91ju5QytQATcyKG2jF4m/5u8dYjYK4gV20G/OvZkGKuI5kbe3b7EkZ2e5oRUJfuE2\njGg8Y8wvQ2UtClp7BdhYH9BJt8MiPZf/5KJPUwAW59rjTsbteXtmKD3CtiPqX6J+S+NZxUTI6/6s\nbsG58LfSPXtR4oGrKBdiAHTu8lP9/QtQIepAOFncSt8BDjstXVEwE4Q8VDKopU6chlzTvTIxNb/q\nXZI7RvhMrN+hfMH6eFAAwv8qQZGvsMOKJl2uNK4r44vhRvVnA+Um1QsIrvm+XLFrFotxVd6lc6+K\nkG2hkZUqNTzvYq9PycS9KqNRftSCB4TGY8iyJ90cpPoTEwPa4Fr91xjGrEs29GQcMF1Zl/0g1ru/\nXT/uQni4g8kU7TVU05M5IqjY0Yu72g8gb/KuqGxuicq1shw9pvUybdGyYsFaUo+qeE9TvWxYEKaX\nfRGRJ/QGsc8tp9cTCGLss4q+QKmy7/eNhVgxI4SPfhx5odZktS9XIXE0kesBG3lrMdcjTcVGQDOW\nFcAwX1IGJOWZVyTvSxU84+Zk7Q6zxGf5UyGhCrKfh0KJb8LvAaiyRp1pubEtKRPBggCMjfLqGlKg\n6FKQ6QPrpMNztlZyTjxIVV2thIrbBo+vhFNY0rGF65Vvto0v+ItcfUDxWvLws+5hbCm9UhEN9TgQ\nww4D+BZjxUEgf7CAvZDKJu9w1C+hg10xUmosL6z6TY5MklXgZkg4E3MNuYHIrvt+wQPiyF1Yy1nS\nrh7FUOIanxkpM2+SMe4c2OEb11ma3oCntr93KChN4RHjVUbSueVCn2XFN0FMXqV4kD5heqXaSjiw\nNL9hR2WXiBCRl+BirCr+2WyXjTfKIL4lzTQKKXS7VsLmLmRiDhM2ui9unZVMuIYIAPPyFHz26n9H\nRu44wW9mjJrtj8XdID9aTyadpCNNxHo35HdmwzmeU694WAneu8s0d2DXlpVH9Nv91zaJB2Us1iNm\nxs7uuVuzv6YFJqv8v00TwQTMiQh6gfhiZhEKGWEk1IPBRtBrq+sFa70PacuGZTwyxvBEWTgR9zrd\n6HFgIvK5TMTX8Qsmf0Mzep7CVhGA7Z1cRLaWxr0OcsuweGJoijw2vH679doCZmz/cSnANC2AdX3P\n1LztRe8u5Sq74meshY5vpCUXiiU+4pUeF5fqc0jwhcAYGgwJG1YtBsCA3ugWSKE376W/1KMeK5OC\ncxwJ8/s9lGNwfkebSCtqpewSQUb4GWe4btwWD5OUUt2YIblkJFDQmpQapXFZpnBh8JW75mcja6QD\nyxavqriWjaNSPYE0D9QxmMzX0AgzAnRNpvY/d+OakIsqLtd8bu9KwqRePSknEpghmTQ1xzCGVGzD\n9iWmUBQmy3e0Vmx11ALaEjkXtv2zrYgRb4d4e7qUxaMToWHBGzmIb6dEAcTdj6X7o1JtNQP6m6+O\nGDfmz0q5rut9H/kQsfUw2i5mw1Tfmzj/z+yFNiDz+yTMixlkZkwWEF51Dg1JTBBk509A8/SoFP/1\nb5dgNLQHwUt0PnpOh6eom8J/z9oA9PNDLmHU6BG6RF22qus7fX8v1O4SLkD0cPlYaC7TwHeaHzN4\nC5PJoXlDYgD6y/8JSrrMmeXuEcwk9OYha5lGpBqDYaBiGMx825ka2683z/crjwhYUDWZnBE/lloJ\nSqyK9iq4Y/NHDDLKmkUljlFOdfY14O97ZjwnVVTj4mQeNpjzjhbobO7Qnjloqg6wQd1tdBVyRa+G\nqXe1QJH0WRZWFAnMQOABTKiJ0Xp8a5JO1zUP48wIUSi/hn1uSx8C1RCiDb+MgcA8W7WjSPbpYv+R\ntuCR8D64Zp3dQjVhyF05tTSn2TkPFS6fMOBL3bJpGBPGrSRtUNuVb7E1dq3bpc2AEmiS7mylub4A\nYEhxz7Yd+n9F8iI/u7WSzB3W3gkPz0k09Uqq/XLEmdtUDvjcqFXZ1cs6nquDvZc1yvIBphz/659D\nN0DX+nBAP0dmJHgRoZNEYrWZ/A+1J5Mr709yZkFL1cIgboAlhn7O4PVYvJVaBa4DORVXlICKXd+k\nzyhuR4cCcuSLaWPzLFNRbMPrwZ9+xEyYc7OCfW0/iF0wj3U52SMAWi/Bc48NTO2xipyPfgUvKwsQ\njwUWNvbqLA7UbkJonfQDQ00U1F3/3y49zqxzFX2qAb2Yp6WmNjFpsxZRyX/oFtlaZC2LxmkKfdjU\nHjeMFkeq4rGsGIB0yPO3BaY84XWT5MsK76Rz940oHOzpB4GLf78hnJt+Q1MyfWfIwkTQN9C0YcRw\nZn0JoApVZfCp6NuCLlRY/ozqbmsUV9I0RZkm2bbHGdLPz+wlszFvbKCx7+kjoNiaAuuldW9dqcgF\n2CgLxtkvNR5aWiQR+4SlRNYg8wPEyVJe4NODT8kmvEa72mTPCq3nZFmjULIJRZe+V50E0X4t/NOw\n6C6OmILJ83k3cwJGUDHgFTrr2XskFHDsX2Bfiz2Tq2+ClT6c5uQaY2quPtM8PQRiZyZWLKXo+7J6\nQAa5HGTEz168NncSyffFYdygOOqWW67DZHGO/RD6jrB0TY4ZNL4vVv7Ee3bzln0XZns7LPgNZibj\nhaMI0wbXfx8higmTn5mHLdnMEnfR+q8HtzPebF/nR6D2c8rCongdxNpXkPRcbaN5BAFV0WzllUPh\nZX0+2SSYo64XC56hVuAfFK1Z9sTAdcYI3ivuM7HBx+fTTaXAXv6+wel8fKPiELNBRsnF+Mx3/vii\nHZUyscgnz2YRih6AcIYHWqRdSY8pSKVqOrfKs6eq6F0k7e4FiPL1HEIqCSMW9SXxXHRnCy0ki9qY\niRHyWfbQuZAkd6h0YPhHfFRxOicUFdgTz4fzEsm0gJbOExhoeT90SlFJsGAwmz/bz+uSy48X8QuW\nCDpn1sGlV6GHgpicq4Ge848E+CdepibdQ6FEtss177/BOGXR0mr4BGVcBXCOx/7DQaD7TjNhosMo\nlsfFVLvR0yrmfkp3Gs9VNKkCr+1YxUYXqfz2SIxOhvqyZODZKL/m+hfoHYUuqu6g7rOARlycHjE7\nUJCxL5HHie9upR/fyBxxYrECG6tK1nSo002t5UjkAGVob7VDL778D/vALlAl28KPuoydkaxKqo5B\nW3vY5hsRjJuS7DoZlWESPD9CSV6cs+tJvkHVmmM7CQfSN2uc0BX4AQ3HC6RWgUXT44AeDwhDyCWY\nCOU/kPUsSn5npqd1g+K1l9T492sfx+NUCUhM22D+1kmd33COEGp9NsvuyfdJk45ZLurHNlCgrnmH\ngt/bDIYVE4eA81oH1cyJMKD9YfB30jajxzaaQpXgqMwAS/psQbO5jsEY7kQCehInT5dFHipUKxp1\nYbX3Fm3Ms3jvzv2q/Au0KXLcP/l4E/JNdBNr3FsJzuS3dg0/sKfO/veQ8s35xQWKmG7NZ3fXIg+Y\n0tVToy3kdl1FqVAcj3qmtoDiJ3x+IiiNcBiyO8hzT9kPgxyf58T7PMYWOGiWaV4cRKPyHvk8Gbhu\n9f6b5eA8lwPgiZxjcp+1TeY8KnGoPVAtyn54xX9j0XB6y4RvmeKpaY/Zq6JTt02DvYSo/ImcypL/\nT1UFO6lDD6r3kK4+/8Ya+/J/m3xsgPKHKCIYEiqcvxAwz6KIqs7Sujd1AUeKkrpxDpPvwnxZDYqk\n8f6c2y6mMQ0K5jEQ8U1y7jkc8W96oHeAacoMONMu7YN/uDkzJ+CrlbkgYObIrG7HC8mkerEyipD1\ny9RPflyC93+Mdc3OqxqWBweIUHuS2AbzHIopZhzOJblhdwHthLc8LoosvJaDLnUKwIv1QsP71vfj\n92eL2jpLfRC876uogtdP/CORhC6486uUGLdZg7EbkqrFI9cvbdWyVedbrZOWPJRINQLQcGJND+gy\nS4iwrX884YW95sUrKk/fNV/b6qygKQcwsloPJoLZ8GrjF5P4SKuOqiLGD0gGA0ipMGBQ0/5x1DX+\nRz2ckRAo2Qgd3LO6l51TrRnw1DYdPWsNk0Xt5snv/HMV8hgMo2uNR4IqTZ1YWPtaT0+ZbCsLX9pO\nOYEEnwD9otq6/KF1GqKHi+qKVKqbPL/Ah5cQE+gs1J13HPSgRdx22StP8xziv25qHk+KjuMQNdkL\nYCRphIGrX/O48SWGJWLrpBpXZual00EJqg2c4q0els1jOg+vd7vQXa9w9wRO8aa5wQWxm2Rbk5fP\nbpZkc86FGiyZ/Eadxmpidk3TH1NVoioN/NK242VwdCAZiCvd/inNI2aTDNDWufWWMJRXWnrxMD0l\n5CI3yS1Up6qg7FIsyyGt/Zg2RdewshGMsVwcaKLds7INOEzTYsKTGQ5ic2pmyyT6ifA7elNCqZtJ\n8/Hg4J1270BYp+TRzL6Vfyl3jWQ9+/2Er/Uyj1qKeKY9eup0u4KMZ1HAJba7SJ6crspbVoYWlZel\nDpWRZFFpoK2PZjkDVs/FeOpbmRjk9yBWWsXRF2aIIlalnydE4K8doyk5/4ItW/0rfsa18lq7BCAv\nKVs2eUDDvKQGGQB2QOswa924/SbZUKJGdr7FYAkRBbk16YIWC41yaw2u9JWL2oRgRSu5cFCAsyxC\nY6vnBUuUCdWAfSPFsv/tEJ1fw61hGJS3uZBZlNCFfU4UxkVG/eSBF9Wwpa0pWPjSAmbANhKT6J61\nO6X5GhVSNMNENRiJekL+GtUcSKWqzbzU4fkJo+1FFsGE6uGz7ybSirV8G8F4ivjFTxviZ+y6EOPt\n/g7qe/NyfrwGtCy3/cQWwqqmME8VihqwdBMS8Qd5iDqj3RSUrwvSQ2fY53qBxGYVek2z3j9YpnN2\nLFSlT5cQMFbJyh7tNUpcUr9UXMHW1bHxydKJP35IEOlz6qr44onoE1ygoee0aFV2UmHemGwEac6R\nDeKkeQWokBe6fvngf66M6+8U608b5WosbJM4lh/o3XvBdaP0JuwX5PseqH4B7Np6FkwwS4gNbegl\n+qLJh2YJiClqcRDEIzXN3aBQIxVB+HzrzfMAQebR9SrPr+OR4OMcHawgGIUWfT0bKcxuGiddWz/I\necFFcnYwJHsRC5a/uLSv402d8wlJAm5n+29KTDOVzQ4tljZihb1jmxGMA2fB93GUq5Xh/tGC6pHq\nW2x1WH59r332jV0NJkO3D8WueG70dRuhVGcYVRzFhj2wr0Dp3jVqb2oU6k82JL0WR7SoUqwJPS7o\nrzIEKAppleRHG/d6CwsRHs5aeNzyBvNGahoQllHSAzBS2J8V8i0eRqFC+XV+kj+ahTcyIxL2gPZz\npl1xc7JxR2mhfr+MFAl288DR+bMdkTUKYP6MAxzZNEEZSIK6hAg9d1ANgwDo9LJ0Ct4eBiAHJuvE\nWOuIf/Rs+7MM9Nmloi6t/zu0ER0R3gQ8fb+ipLANgJoDTYHMLhyubFNv7Jg+l1Lb3fg66sXq5Dv+\nFE2sH35VbE0S6TNMSq/iQvcw+4Fpn4iIhMznaWOOE439f9o4Jy4HmxxU/vCtBVWSeOI9Q1Lu9Mwv\nWNMLo+2LGQRenXhVEk1g4LM8qnohsT0t1hH+TGD1j5tkwO/aY/q3yDlbGWCkmH+qKjKep7NEeAD0\ne7/PfPaWaBfreDMqd0fKnhW2AYHWAvJEFWn8RqHRndm9E2wvpibjw0uHGV+L3ePV9oG5sTahH08c\nJFfz6e9ok7/Te4XohOV+grWBAYBDDa8kYs5yKFR8aM3TJKLasXsMKWeb1RJjLp0ZvKBYOyS7/WjM\nlYQffhdabZ2opA2UtgBaP9Ahm5u4mRhHfHl66f64yV8Wu9QWjNuCTmSc/G/f2CndRZSyiv/B2Rjb\nwTX9nkh+RtN/G6jzKaw7JT78/PGE5FcY9EBIOcNIQMDwGz8TmRnP6J3JsN71llZEdAy1iZA49IGz\nbRuz4I8RxMgZflDOdJjkH6q5h1/PY6rZozR16AJDBzm2Zz/jrcXVnEOr4H4Y04l88jyHWDo9jsLt\nw4efTv+4xqXkq1NiuPGxmHe8ZIR223qjpZ4EQV92wEnYWmpJINvNBEgPe0ZWgq0FYFwMUYpW8NOw\nEFdAhiJawIwpos4JY3vFIoi2ZPrylijy21qpF+vFIIsZct3fsH/gr60dRDDDTT5KJk6n2JaOuTkT\nhhV2aJ2T7uwsh53IPM6KkrJNOL0kyZOGdkx4K6wyx/Rl97l8PfaaA51sk1O0lkpneu5ZP7+Js0NY\nxFh1wVfxxxOvs+dW2wgXS6KxfysOys0gHMGQV9TV8tqELpTxQ0Lyh3FpFRgGfuCDqaAt7qFLZWmK\nGBuS0X2/3o+P80QCSyVX74F9SwRRxm2qvvq5a57NEYpgN36w47W3ObC1ZQ+mG06/DmQC9LYb7KZt\nurnWvcg9ESdN+j9+nsNL7Of2K2F7Q9+55fzs1Xwg3f6j5CnjJHdaPEIYiOaXg521w8uZU6pnbz+k\nHy/egKBzbOdSW71wEA1jXAxMr4UCctpl8XNAzAXWG0I0RKb1X0u91YgIPLLUTrrL6avyaIztckL2\nPTK839IBJs6PLUH9noaCzhdvgzEqVhJtVrAxSWiahfnlSx8eTSiCCTX35G8o+wi7XaAbkGyS+FnQ\nbKiaq2ap2lUzYdU59rerfb/GdfjImV7fd/XZIr79m15ZIhnXwbHJ3RQvBQoSOGoPMQ1Af5oZ6Hiw\nx/KZRvJ9RNQM2TRP/ypzYqqb+U06HP5WtN7RxW28KmmGXGOjsGZe3zZHDljFK4K0rmC28bqa9e8B\n4j3D98mEFhpguwzJPL1xozwKclHqJ+LtR7KvSsXZyl9JtNL1FX8AJ91JTA2w1KUbSQEfPFkoAaJ7\nlWdT77O0q98ZxXxD69kgOHN8QJD24URDQnP43IW4PDaYLF2lN6xbddikf9O7TNH2YKx97Adbx84+\naohRztAGnj08xh32NkhG1aJaK6X2k43phqve6gE2ww9gd/12V8LGrjrd8EDxop1isvc78QHwG33I\n38hQlttvucfN24NX8zBgj6juJfGeMTMzfOzjIwx9Pj8c2Ahk7583JB4W1M87fOM+h9r/mTuz0XSm\nJatmB2g1VSqgQquBoFMCJMKuXEbP3YoLcv5ZKqIOpUXAs9vr9H57rNLfUWQr8yNQdC9VOvEWWl6g\niN/gdb06A4UkYHDPCwpGW8kI7Bp0F49kImjhBsmyb0nSR5+kAu/Fz8Y1Z/NaZ5nQrwd8VgFAMdHw\nirTT5VQ2GFwe+Ctx9F5TzNN2trVMJAlG0HMFM4kDLnKP4IEFpZAB5EUOgPKGsr95UqqH8h1+4mez\nSb+gRw01NJoLuDTG5CgCnIp1e2RU3vJai/OdYIxa+Ri/UubIzjbYZ29ycB4bsPltnugT+SCxc+Jl\ntGZ2LbFNcEh+QA0q8mOGEp5cbMQmSr/HW6nDi3Y1eKeLghAxZFh5wrKoZTsOmmrQDcQ7CRdxAKnR\n1z8707Rxcu8srOW/rLRBPxgoZ6Of3yC9tIFA3nx9hsiRnzqDjSD/dVm/d7EFF01+hO9gy9GD5Zuz\ngviHU/fwr6oIju10Lq004/xos25lwYHoNwTpjdhNr7MPNod5IS9Bjtg5Reogx9Rm2woJQa4w93hp\nvcdCMu5rSdESw9gzTlLEX801QfYRYDBCMpBfym/ngeB1A8HyGWoH5eiV1Ak0JSfsRCFwipLlrOZa\nnRjEwPSPMq1AIs0vKKfXTqBp9sbWAi9HtoSrdLTtmu5iLgMpUshC1mgZVv+qjPnUZmqOJpcvcER4\nu0DdJQGBKiqta5srMohH3MKejPnzS3IkQ5IjDxRh33jcPwQIHHpdULlE4Nid32URPdqaIvRHHnW/\nVF3NWql++WQZcb8gRd+9SNPY0DC5r337c5/en3kc8C1De5bE+aqG8b+763ZJXGtDtL8XOBmR+Zlm\npHFwwLhq1RccTswr3fVUq4Sd/zP02zgvcn3+nCtQePRdPnTZiK+YLQt7l1fNmCapt4ARbOmI/GmU\nQMSp4An42CJoWJ7aBez8OlxXzQnlI6PvJTDuEuoprO0f9zmhnYZxoJ9vK4uZL3yaOqc5bsl0fh4c\ntVeouZCOUw2e0Kfg+p5WbbLDEUFrJprUJtMTJ+DFA1iY5B+aIAOaSqE0gzRK6PU4KmRDfD6vMreD\nZJjlsPE4cP6oOURVB3Dgav3pPnYqhTHwSWEzHTqI6lk1Ou5mJ+pEWjGAeqmDq8zyz7hyN97Webmk\n20KkXjQs6UsF2RTXH7eIjt/SXotfihB+Eqzdk12fddi0+Ftt8WTEGtGv8RvXmjILG3Ljx0naBaXQ\n6BxEz7HX+wM7cZexnA+6OsRy4sQGAEPNYnOV5Pdl402nZRqyhFN+jAQ3lz+jTasEB9CXYmqvY5l2\nTxvVtVg4uAPNQYrmvxamfMiDm/WGd8C1GjVYaf5VQekBmBi2dNxo/74w8/efj/Dn29B7vHQ+eGvv\nE8qUeBdfLofSaDZ68YHWACw10meXyC4HHKwgniC7frPi6Rn1+gnGJICJecSflxtsxDQkEeAHVWHX\nIaY75z7rbX1AiMnKcOcB85TuB3j1biRmHrTdmdMOqWTxOmgdXVXg5oUqlHd0sMjiR5RKY79V5WKF\npwQtrEwEsVIiYsz1fYPnKHfuw7ACSF8kUtkySGM+V5WEvo72Zf0oH6emd4M1uPAgX0vr+IxfL2qe\nHzDwbQQ8Z48KRh3Doo4L+Ljw4Qm/rAwWyVwWvcRUDis26VqNhfAVgrCZfxpZr5+zAx2HB/Ony6S1\n3S6i/lBJfjQw1cpoYql2ldcZO1B9CSLW5P7LpphkjiOEctiFLh5dz2jIheVUWdkB4OadUr8rYS+6\nZsrg25ASHUd8251NvBQDgNpj1PJS9rcEQWErJdk0oXqBNYVFCoZ4cjEFw1g/1mhE1VYsyi9C9ufo\njdakr7OmPuZ0Pup0UM8qFdkxkRvifvmSbzBJTyr2EK55+qbV7QQND8e3qd7uWHqeTfhxZZTja0RN\nsWnKwoLgkYrUchpVYmwoq36KfY8lxFVvGzLClsHY1qafb4nK0b0/IdvhfPcHJ/UHv1JspPX9XKUR\nNJI9lBS2jIkBL5QaVEOVJBFdowonUYh2n/tWbOp574qipvlviIE9wjtl8MwbkM0A/16g+aPuuLuh\nn03FKP+K0rBHiHh68Q8/I+zq+CofgpL97ctRmkG5NayPi4iZu/RKPyUqg5K45SgUpRnzR+TeYtA8\nCTeli/MSSPeQst+L80oqmTfrpHTLe768c4+oWqQl8AyJLATR4AerMIT6moIfDNeWqECF6pocQojP\nGq05yuCMQYFpZsvkv6EMwguYxfAeUEwQdt6UimKOc6wXHMeZmlcPbEjERbgUF4EpQ394STi5+2w/\nqZYlBUu2nX5ftYJSmGEgOMbddUHnnN7gKXBgxEhyFxGTSnvhkyzbOFcgD0sWLj1CJTYPmZChIHNN\nhHuMDfGC8xLYAnHWQ1tRgHbwi0DRP13uLhGGPHTPQFT/xPARJcOulRoi6lAX4xgwETzHPCJ/N5IH\nEN4taty1lnu9rbG3uMWMKuthn/LiSnOx3iMGufiNTOcY3nJebKDRvEPrgKCkOnUALzVZh9na6CH6\ncCMO6o7g7bdw4Frnqb9ZZRttEFO6Ownm7dvTV2lqTnYrVetZJrLs3naxg1bEmXnRgPUDvqbyvJkb\noIGTy0d979PvjwzSAB97nJ07VtzulF6ZX+SohNVZ2u+0pGYMqGaKh+q6K6/YQUjH6Ndb5j6OEFqK\n+kpFuU6nlMAAxPzCoBm0HOgdagxI98AkhTZcM8YzAaiJZo9dXOwNCa6X8TlLWmqw7uLjAhVH7c+3\ntXE7zlNUj8u6jTyE9D8rMHU1h01kpIH9TChBd8jqYhTYIM2tJgsB52CqHt53+QJeSIPK2t2wlDWu\nffFjSmdDW0+vgpJNqJLjEw8xaNxMSkNzPhqERZEdu17rxADE2p05XV9gObpPB2iky3YMCcPmFDnf\nkY/FAhRlMjtr31GpyCzCiLY2Jr9Xk2KGd3tBWyIsZhgmPGfy1IOyR91GHeMSSO7L9FJAtwpm5jl4\npyyr0dQlc1tOyMG6x4DO4whgEmddk/xGPn9lnxMl1unywAZZd64ShcgCxO54y0KZBaailezifUZB\nDz3c7JWLOak6BC3AxVUfqCysqpuS1EGFZqtNAYDy2RYIpJ5mDsW2RW2jNks2isvr05+0QbNnBH6S\n22/v5aYjucYKjDUKBG5lZiizVOwbAM6qs/l5nFkCSyJZ+R6/+EcARv7khf6AkRPntRHw3KxvtkfN\nQrQW1S5/a0CRlCcpNdp4x1WUM9Z0u9wH+5hcrz1rGOnu31hByiUuO3kIT7HNaVs62xwZj8wVRdRG\nHRPnxSf+NGV72439Jbh2ZA9cNxUFGWA0HFxzbo3bmA/V6xaVb8jPDiAY1aDbNGkFBcvkc17ykNWl\nQbdbOPJNeL8Sbxb2i8xWg411+bsA1LNHwZNbZGX1najrQ8Bez4zrOj4a18ilHksxZs50YocFInUx\n5xHG8V6aImQbMV/uWK3u0c14+GFIDQrmb9Kv4mG20Dq0ZP3itziCdqDS5opiKA+wVKsjtUphF4xy\nrjpSaG4hsajUrs72T5ZQqfmYhg6APtA9x82e13a8ScjnS6y97gw7e5yAusaHutj/KW50jRjAjVzD\n95hPLJZAdhBaR84C5vlzrLyc3bZR9Ur8d0XEyavoWMGfWFWaJSRlMPRnvdCNVRaOoWCMP9gwsoMN\nG7dicgC7+FD0eTcb9i/9HBqNnWzkFdEPBZF46zYA7hYLFHLQF5m1ACe4jSDnOb8IPfxPiUxtOa9w\nEjMFcZisSbjQHD1e3PcnFObYpBLY26/Gchj6HHLf+WTOwb5wjD71f1Re4yTb8/6AAMuSTpbgCb0U\nIROYd3XDOuA4m4ZPb9nVRzBdoiRz7w2NUToA13FFai+Uuvau/HkMs791+9iQeQy3CLfAgn8/eWqY\nyYRvCkqoxk5bfF8mD7YruQl6WB4FQRU7gOCo3IUnB27FfVb4UPDc5Sa8kydRBLvH3LStEGfnoAFG\n9ji4g0pG9zC1RWzABr0jZ5m2K2QY5mG6kpmCp0R9eHb6EDyMCypJHZqHyB+xCJy2tjGAmBgrEUm7\n3y3R9Dr+r5LUQ3fj7HJ29ihrTxKSBMREd+ZXK5WYAYxXUiNCXMe342av4oAiSM8Z+s601vA9ExAy\nM2dNBABaut77AhknjzNr6+B9PMWLKPMBdmpuA9VJnjrC5RfnhG5/kEJ8Gvzy4PzZUgsixHmgBj2v\ngZIxpJqI2+U1+J+G0cqCpJFYNeTzwB+VpN2ERbcZqB5ZvQfinNBT/7ecjWazE1pUO4+a+z3Db2pM\nOQWOwH1FPpwMRxuxM4ImtVG92i/EmJYQTOcOtahFsCFf25bir4iSZB7NDvpG7zY64fwaiDuQsSa/\nWiJZND3QYYISVfFHDCZwwGER38xhtODAc+6yfcoqP40LEMIUPTvKdKbR6r6dHddfFWShjvHm3Dgl\nHqGDGD+gRT1WYIUYCjXac0HjNLz02fCbum+j6K5/Bz3YM3dmGaR80fAxGDe7N6ReLCkN0kmfJWHr\nUWLMLiKt4/aokvwI4v6ZwwIRuk0yD8Rwif33hu+oFrheQ+V8g4lgeakCi8+tOaw2dH/Gu3klLYMg\nhEpK5COhzKMyb/SX0c0oXHegtdxPyy6qZwMwicz2suEOThVnGA6MnuzAC4AhFVc4TZAg3qkiK+l1\nyGNiG7gWU9tzV6vh+h/iREXMKrnxdoAeEBeYKPkYBDoYDTJtjFaLDqeuIciHiwOwPejrzUPUbG5O\nNkiCkmOXbOCg3TIjkIu0sR9+DXVkIJ1dDuWTUadeodIfDIudk+6LrOoy+FczOaoy+Ta1BOmTYQrO\nu7gsIRxrjQDxUmZAa4hWG8kpDYRukx267kVg2AlFCesxUzzj4PqMCNdtjIB27bj0sDwzCfERXmxo\njR5OwkqRejepNjH1CS4VdVOsZrWGl/pPDMxVXKRFXPgzryKuY8KRsbWk9hTHn1e8qvSzSBQxP4ZG\nrkYD4fxncslmiFeG8iYVm/XISF1jtY4pv+/+1vlhUrotfG9giSDg3cq4Y6WH3hvd3V+syYZ6aYfb\ngsB02eCxsF7e974xWl1TCcUO5znCAj6WbPhaIMjhWfayDnh2FH71jE2nbvGQuCdxyfokLjwM9sL+\nrm/pSttDzGXpYAFpcR+otTTMATYFr06kRZmwLFJ+cuaXznb3iW552w1l/ZDw4ibhbpFMgjcLiIie\npl0VC31m0yFScN31zoejARnlGTqlHmaiRvTDC3oYtW5rqQm6lqaO238Jc6waHKK2pOnnevtv89Sj\nIRFPsWZbUQVo8S/xOxtDJVpE4gzgl0tX9BVjwdaNCV8sTlhSrNC2sLLofchYbsLdY+F9Si6KxYCE\noHxf4jSiMPQZM2kzC8KKISDXypwVH32gyqQ21oYPlpnBIgxQxkbEgEU59WC6nubQqcEbaldcp3lW\ny0TEBS1TxfdzWEdfArmoL+draEY+kkPfDvKsoIn2THbQtpCzbDo+PRYholkHAXQOokDvFKM7DLoG\nTZI/aO5Or+2DVqYVNop7iQ2glp2FXTzignGj5butjC8GOTHb+MuTO8eqERlycgH3qbnm8usL4E2o\nXeMFNjASOsjobp1/xHvNbohMDp3QEsDW+Z4HWqqx/aTF9Dhnmi5FVz2oFEu76PoWx9zw0TToztAi\nOML9hOcZS5+lf3m3WXJ7jzCq0wBar4To1hhNkUADvXD7go7jo09HFGgwlYTsmngcaPoO0rHGYeMd\nm1kMMeJap10T2k1j5XEE4/w/psOcGSjpMQlo+conNa4hv3UwHukeZVzpNnEzD1reBorV0stYJrVw\nvZ1JHaXfDXx7QZ1l5DJkcg/XpopQ32OM0DeoKy1vWmCHQnWfQaufAL9uYXUyj//oxvd6ghjdAmjP\nRW6feR7aui0WDpebd8Ql5wuDJ7ycsjyb3K0kGDnt58HWAICTqa/XmKUmcNoiGaaYM8Odvhf1oDfR\nVzF98UoFs7nsDkZydoBhRK+zclw2comqIgMT20St8Hbq1lTllyqRzRdVJIAgbwV5EUNSUgZHu+Rf\nhQgaXwpWrOuI+19ukLVzQ8d+0ZuzwM95ddREqBeNfuw2F2/ujXU3pRzhnoI+gez+ZMZAoftFBH81\nylHrmey5I59uDR6y2wa6o3DEqro387QtAi7Ge/nlj00lqE7LMo/soO9iekq7p3Hh0bFkupRXmIS2\nNB46TCDmL2/MQAel18GZ5w9+R/y5C1x8JgTLRdN2630FDccE2GHbwEBCUjQk+PPZhMdnlZ7Sf3P1\nAmWoI9M9wdHlswhpGV8Pz0rDmCS/sLOZupGKcVgtkARA4DGH3SI3lRADqAAskd2qjG5HwMBb2GaL\nywufCIHNMrsA486ZIx1XdzyRikeOtsujqgG5sRwi5ESgZR3tejg4tngBlUdmGGHA1X+jDzdFnSNG\nWVN7X3Tn5j4RLlMnR1nDRnE4zM4Qdkq8RPZI1eQoJVAT/4GfjI2uVX0HKAI2t6ozOtc4RaZUYqrO\nFyssdIg6bD4BWLuuqVMj/TQj9bwRkuMSEsv2us5u7C/QM30Tj6HwWvUCLEZRbQb9aQj/nzPjxvGd\nggjGfqtD/fPX9PIVdYFD6sTZ7vsZLEWojq4ezP5JMu6yXtGcmFhLQgYJDAatT17r4Ll5VPW1EqOr\ni3UmNt965/TcFYldQa/97VE2dQigy0QQGebET+FiiR4TfexDb4bvB4e2rTbTzyy0m+MJB5AEcEZJ\nC0+EGNd7pQldqJCMwzXuzNkDwIj4kObuvgSeZB7kK4zS6HU8xnA+ByiFHdiVOsMY4AcrAF1S5cJg\ngTSjrxicTUXBiULXFMMrOd26gnAMkUKqAYBCEbGjEMzeM7FixTmo+6gOLPxCknTnwJzxRUWX1BG2\nDx1noNujmmIbR5gy0eT6EdivakNvObL+vKRb5PU+Xv5IsjZb3VfQGqxf9c3BPBwteHlWBAkZjv/G\nbYa9DHMac2A8OGIeG7qAw2ZiYIX98hoFXqgfKc0GG3KJpU67rnnRc/QohMMDHQQaCTRf8uLiUnsi\nYHziVT7c9b1MPLqidDva9NkFHSKpJQQtyQzgeLV0PbSejdHsZk0nOG7aZPlaDGrXPF0/T0/8ddK+\nWmxqbNZfRcsHTfLcrp8eOSu+8kKq55RUvTnWiQRgoqsBw9zjhY1G5aSJ1QescanEe0TCm8enfIZD\novMLveiBACXxixoGmT7pik6xNChQQlp1yrghDHItAzIPXeMm10SjmcRxUxIUfoChPZTLG4VESqd/\nwzcvqzqNvIodNUFF0SPifeWpyUeFduW3q/WsGWEtrsUgBbLePJEdKHln8MeBKqJIDj1nQJTDAMen\nejXPFsgDeO66Qo3vn0EdFBt1Wp590wD86MeUsOYylDTVrxGKB1nuMyUZIGBNouXjBlOFKojR+RpU\n6sDWu2pB9VbPAxBrew5zpEvnF0TWWt3KXlKy3mBZEg8GJRqHmDd1EONj9GcMfOSYyMtQXF4GhoSF\nvC+Bo3yryzsZKuZUX0hCeRidPO7nIoZzZQq6XVBZdM4EMeKvHPKd4CTGAoOPgk0u1Jkncf2PlPyM\nHWRpOxB3VVH+ZzOpw4CNBny0pcuWkYkV4KX6zjVwk2cbxOltJxcL1/Ehdgtj+jGpHUKjggfLMiGK\nSpbsHxD+qo75ivHXmD+cIcl/qc23kHPvI/eESqJfb4idQt5SEx/feyrJAsZaXA1Mp/9PAga7EvZ+\nbUlEfhtW0iHuhvaEYIgxhZeXx8zmfrgM31jHia2aX7tM+JDdeSSs5keK79BCKaYC3BZb3FLvELxI\n1LQ/nrKNFA2CMdyoC3xVdJ0BAZr6WHR2hvYWE1AqrOQ/HO8IQla/S0Finwu+Fk0JFmdeNk1oSpYh\n0FmA/w1hMWh/GKv3KI3JzCrFzkIKUypLq9ncyqzBBzzbm1azVq9BDOIWT31isEYNIvGd3radyVif\nPbNKAJ+YeRuY4jpSzKA6Wh2VZW+3iCBvqYjaS617EnVQNunMWGGRSHf2qiJal5ztmmQNXM+r1NIX\nU71+xrbMFiFKXa2LzN4OrI/hITiPw7HAjbRok6PxenOcyp5DHDAcLFBtjEcJIJ2j/LPGhVEN+s7M\nlVD/H9FA0UIoJAtM527z26AdnQmxfZlD/i/UX4y+79nRS+Q8efancR3SpHbUkN4XBzdkjM8zcCf+\nKvaynpVnthIkBbN7QTkufVrvNtiPOZAw6zTbeIiCrqfYXIyCUWtJ0r5itwKdVoeuoOIy7spBo2Kv\nw2G8bUvIHfxR1U8DAxpvsuh9dKF+FfJCh14LO8LukJL1D1vofZYnKn7G3417pgvOAhHi5Tjb3d3R\nWGu8Ihejm/W1WMCaRs/dWhAo+Ii670rywuIWq04rvuPLOYVUVF6dET6jgaNsx3buYLEVZLxRaGgT\nEYS7yplL4l0TBN3GO/GSrUL/LDQ4Hq9RsplQaiMCVtJ/jQny+eXOcorBhzXTMvz8BQEPJrv5YLvC\nCmZNoPy31varkGKThJ8Nl8vsYod5CnNClgfn8UWLsivqQomXztTQJSFkKQzlwVzOndwgoBoH1STs\n7lkQ7A/z6TB79ac+UDDHHpZpEaIX1uBbvQa/eS07N7jkz2A32gHmHa3ZgKACm23A+6fJ9VipAXOS\nTtQr6/9z7Xxt7P5d1ImVdkBQlBaqxYcaXDQS3Nj2ncIL3CL7t+kQpY0cC+5gGA7UNxfA3ktOIs2c\nVE6EUlDqjHUWymVBQW/PGPDdrn4/I5/Sc/K9VulZ65zQoVkaw5wItiWcHNeDJxVlVivhYGsfl3nK\neHQwIZR7yO8CLdOU+ugykHezgEh2qVaDviMMWq/54PuIX5Q3R5P2dZVBaws8JZeEz/MJ3HbWEPod\nxbXA0gJVAn1GkrUMdm6QTbLj2SV3/iZ4UT394xeTXK4WQUGS2TrKaIa1ebu/7JrmdRLyQKJ/LF6z\nzDtTsGYhE8A/TzHdzyxRFDDEfTbItL0k5Aw6I2g8lc6LG37mP3NjFgz7W8SwsCfr5BjVJW6oz0TJ\nrEwSqxE4LJf99Phuu1j/GH9qGXQ2O4j8QI4Bs4gROqECkWyvkDX3M1PtCD7RBcjpcR0+eNi41oJS\nHwy930WCXyY0gcO/4F4MQZCdK1DgUIpkxAi0lZ62TS06iYE4MIRTjquFw3EPY0dHb8+0Da/2JvxR\nR786dsfT/QDh24c8l20LfaPgrKFsHWHy2oESJlnnl6hEO8PdFKNI1jqTWSHsm9BdKceIBpfSYYZa\n3t7aS8F7+gjiKyEL+DNTlvXmcCXJLiGYUcRk2tueYUhPSolruACiqP5TCwWMcdqDLJupwGdlpQj8\niDi8QwzItXXrTem3PLKhFv/8M/5s5Bwo5CD3LyLuh7ncHuqsFlluUXWtKiFfzbi5k6l2irlWt8AI\nDp1tO6uAq2F3pandDUXRPatu+bult8ZirG8KOnUFyYpy26+PZpNgxboSvNs4+ngzu0uSaZRwE7nA\nmKQmSRjBqWkRRhMbRctLD190Ru5mX1rRfh9c0OAKVl4P0fUMmDgIXFOaEgNqaRLpXbgrni7Uk78U\ne3N52mJFpSLZwr5cX7q1M5z7LRT/b34mxEjVUYmvETHna+d6pw1BFUoqLyHfzSLAFwTyHdRBywxQ\nO18mU0XvLdF5CVYXFu93Dzp8xUVhT1jpILq8au3aNAOsNCHopG1bfeizZosX1dC2/UySf7DBOM1G\niFVXCdkEmSFBM4rT7SBfgghl4EdlkqsACJbmGaDfOLVhnUIg9Fw8x2RXQRrryi9VvYTGxlVn/ItE\ncTbJdRT++da55aE7f6AS+u+zrDsI3nbrucOlbnLkDuBmoisnbOItPnQY3hdLlD72nNi149yd6Pvf\n71zp0Jd5iuqH94fBjrJ/e6gIIAUMeUrC1kAMAGwsPFHQKxPyVqX+WR8nFKBkZCgW2Jfx5Ae601EC\nRuryn3wbbH8JSs7xDoRylKb8R6KuVerYwAjrPlq1XXJnHKijaVFZ7VcBm9a+fzN9wb61LqMRCudC\nCpJdubVrZZDcJ161LPOYNaeZw572HZQr+g8vco5O0Dty6s+k0sxH/G1d/sMeOyoHD4FEE6ZcgbMb\nhJSYDLFXUt0dcdt101h4Dx6gzyiXN+jevoQADG6P9ilG2Lh8OAIfyH5DueI7eQDvyoa6Soy1fiXc\n91eoOmvvu9Zr7jyusSgx/nqsut+UMSUP1S+1PdTXjxDyVRxH41oZSEuLZ1MF5dC43y8+LcTF60Ti\n3rWp1RhvasalZpwJID6cIZ/0iggVX5vh6mcKzpwv9cogdK4TO+18uSNG4RT1EMkQXhzJ0LOBvyxG\n5ixwg14I7mqY/FXZ8WZze3s97d6zbTSMjwtWyv4Nn6nQJX+7Z/GRERvNDxb35+JD0Z7gMbXVoTTA\nLdtZa79FD1CRi3DwcuvRgDgQ/sUUfz5TGWTwHfbDwY18uW9BXFqVvUGdo90KerL4Vw4uJAi9tCbv\nkiPOEWPr8E6/lUxnjo/sRX3lq9p2deWaoh2Zc0tieHlpLIWKL1T9GL4QYheSLlcAAYrtzH3vCr5p\nvGBl9Os+3riS5E8NOf983MCrUE8R8BxE/lFmypMNPGP++c9Ye9bO8MsoNpxgnDOYK1RDCIoOUOKG\n1Z80XD66HBsJZNHCYjyMHHfX4/NPmTBINM8aCEOPjk/Jx552cqMc1+cDJjuggYqC1MrM9A0y3tC+\n/KEPoAbQudnKrETs8HUpG2Z9K1BQQmDGKa1+WB6vdc6iipiLZRXF35TprAG74pLxrznasV0/F3w3\ngSGN0M8QRxQgJZFeMNrkV9F+N45byYHUn/oCOSv3TBl+M4ctdw8b4cy9EJqwmj2yFzupqW5TUJ6N\nxvd8AFRlvuenCVorP+tre2LdeD+cbcZDYf9OlgtU7HLRmTOgkAG9n5RXyEOBOuANMlLCdXlGDI2l\nEsKR68JhFYn22ay/E2+gi7S8NdZeImlDK4hutQweX2GJijDmcwEMejdWQDuHchB4fmj4b1vNUg+e\ngT/k8whmd0qAEs5+lIpOloOpTzSKo93uY4MY9TvC4fPZI4Of9HujhMfQNpbyI7SYObwNz93iA4Vc\nBZNAHoSHHAOF28PZXlnnyArJAyxl72FeAvu03ZAUbZYcnabqMyYzOIe0J/ccCDZFYPXk6f9ytY3p\nUae5mOJP/9Yb1WGDTAeOo/81pZ/Vs30tFypyC9slzdGDDbTMy8v7+qkQSdWFUAyRHIGyS7dhtGiJ\n0TbiT6jBUB9R7rvm1aNN19FiIvH1Eeou/tXIB+Q8YHfuYstp+BL0ix4NJBaSqZ1CVc39sVEoUl0w\nZgRi+vUSLv7c4V26f+fsAA80RgTCTAIr4P8sSy62KLU242voz4djV6JK4NjdTegdAL4qKe4I1uPu\n5Z8co1ttkYRugBVVSk9d1a/M9AiwfHDGYFcCilMhgflUvAmG4N+m7FwxQQ5OS7/0srjI5279E1EF\nG8kc7+aPflFeUvyxlfKFlFEnBm6Fs80pL29WsrK3yYCSXIBdIXdi3Hb5M0uYVO+iV1Vqt8nmwI4t\n1++BVrCXikaukWUrVx9M3Xwn9Gf1IFX5gbMdDII61eQc49PDZT3+pU2EM09eanLoJZMQW3u+XYBs\nNBPTqK5Ey0H71RP+WhPCTYQkaZ0FBePLRLKX56MqwSVi88aIjYGmX6PbNkGUPBDCScupJgKNCdV4\nqnr6o34qo5aK5B9wK93AWynv1cJRqmI3XWNstG3h95y8VPLQNm/yTQgnGW4do4iVdAV7mU9DB9Eh\nUWYLdmBldHjnqzKVSu7r+q2qOFnHZl5SlMnKVa4KF8q6ujAMjRLQIzi5hLEPfQXOa+Ew4cmySVYG\n+xvwtRjeFlT9q75B/mCgijqJPLnNbKJP0p6kaNSKFDrTXvIS1w+3xjq/3iF0yi9d8Qe4lcDpA0q8\nLDy2U/mrrIxCCQ70TXnM+ZWYkkJx8KhbDnQjvTxnemRnvvp5RbO/4yzFO5QH3K+JcuLXDpzfcRvH\nF6Wr3sjaA9TQjVnSLhhPalMk9/eYTNHWauJ99+QP8tuRTqte8938sSdENC2KRTW5n3EKRdZlB6yL\nIlmqhUsF0iAElqs7bJuz+dNJkX4Oj1qLh20MvAx9USlBSGUQFVIUDL+gPgb93S340kCVocOZI6MY\nluwIsl8MTakF+VENmyXVBe3zivxS4ZPtaCQcX7m/gwSN3zLuSGx41Wo8INg3crtFq28OlJzqbxZX\nWZIDNmlCtfof6D4a3QmqqoXyjGdDo15D8caIOHiDMurpcjmbfOseIk0ZE6l+54Bw1cAF5ah67BqU\n9j8MDUVlHWJl50iMFy1dfSdBG3j6q7sAdyr9PjuvzLAT/UFItAn8Dlw8uTYEoXQ/1RsYZ0cO+cBg\nI22YhPZIvqsOaXHnpB63d5tbvP1hos+uI96ciTwu7dxHH7pIb3rIFABshcM8kURWBnBqNgj7RSZu\n4A/NZE/yz8TDoKnQL01SNRKjU0to51wbs5j0weE5xFttOhDAZpwz7HoinfP4/06OWfh20/09q+22\nLWrOoua2OEkJ2t3QNnqO9IJEYoqOUvzF5dmhDvaaOKSG/hQ3uvUHKW9aposs44kfHvhKoHR9Wuit\nzzUBhJGnxrgxolulxG7G3PFYiOquNltf5S9TGvkAFMSYlipIljjdQnza/ISuPy8WLO0oSmivMbNr\nVw5K+BlH5+NsvUOj9aKnTxgiLXY+5U2Teek28/JcZ4RqTXXr3U6YvevLZ55unatrnWG4SFRVjlHH\nHhdb6dS7ChZKx0cy73yWOVxyb7bYMYKmFFcmrLJzh3uWtlzUdQhn1HVRAbgTBaMeB9cW6fKoof6v\nbvjlpA28XX3Z4JfYkCCvyzomuKRJZwjfvXEbqtPDAKjg0esyqVJ889dGNFpFHzZzaz4Dtc2jxhf9\nta0gHGqYsFa7G32VL9dnhEfgUj1Wbprx++rLNUiHSjxJyciiwHVI99g8tH2y87uqx/iUcLNvbWly\nXdlayImb5e1HOUR8Ko5XRlROqCxouKW+G6lxUD98m+8dbAagsKguVe51Am68qMO43KsNOp5qDj7/\nadTpyByayc8q1SO/jSr82/3r+rS7Ax2xuZXzzS/sTjfXzsF3pqRDTPmQKw9cmPXBa26gLz2ZS6uf\ngPeMm1f1xfKhZ5PtXUMB7PzFliqaNZQSLWyOBMp/d5XpsbwjsU+/utq3pZqcPSb92SRCZNNLXU9V\ncWxbkJ9ffdBWbjaJrPJQ4+lNqPA5GTxg9qcOrPODJPa/p/VRHMwoJ5Txkg/hghw/DD9+sJqOMHBh\n0vRTu1pj8PrSgQ6VPT9TVwFARnYClXB8al4m/ech2ZlgCo5OX63oFe0Idh1rTQ2M+UkMBujJW1UU\nKtWRceaasYmkvMdGxrtQXxrQ6J6sMFYvBGCj3ejcxVHUUVh/qGIFfd8i30uA2ou9oesQ0ldT7Nq5\n9tT3iJaOHSmEIUeDScYtwhfUqPTzA0mKW/DJ29y7JEqWXtDgg4s68CDisqH0miYSA+p2Ww6TDJeK\nrz4e/UuqO8DpYI1ksvvo0vhMKkkyDPc9qhSvmThtb54rk6xRQnSN5hIo9q4lkc4GpFi2vndK6dGt\nWQG8rpvdo3aApKgwafor2MnMpyQ97Dqz8tNbsp6jSh6sYLAhiJgHWZuO0mz/K79z6zS36p3A/Oc8\nnfcBdBTkJP3D96M+yc7ZknntYfax0lq8ih572eSe10KcqZKYckldDUlLYEXuEvE5qltWWixGS1n6\nlLUWR5RalFSSUDwLiN1PgRulQf1R2xIiulOP9HuqCVSsRws5FKlTH828erYCwDr3HsB3Y/mRR1Fy\nvFSAD+lS1fmNhK16KWyiKl5GusnK4m4WKZdxyAoojkktsxKmPsHiUIyzgtiJBXt2zV5I3unPz7xy\n6KxTdxnpQaA4FBpKqh8Gv54GgX9oq8fZHiFeRDSkdqeLVtXHpPFFDmpFB6yPPMBF1f4PDZ8cacqa\nLcHioTzAUaZ2dnpWXzDt2mcGWWmi1QzEn4qoOGYT3oa/YlFpuAlzCTPIDR0JrUeuCn20NUFuGszP\nDW//xU7p/LOQJXP6hf8q7QMnXrIU3RmhWH3FZjmqCiQUxUHuwLg+Rjg3+q5hJOKFh0ad/bxRF2oC\nJOAfSXPORj0FTHuTcFB93KOA8ywOdp+ItBikaDQSDieeSKsYLrEo+wiEHYRGwhIIsfG5zTvdiE+Q\nPyRrUq+wgHRkd9roylpKnsKq9LhHTeLPvItyKdsUd9PoJ+0RhCUIPmQBeJ411fSeqmyzoV2EfG9D\n2is19mbUSkD0hYVOUnnza671FjC5kHpflIijBMyak96idgbCRClk3yoslbFcG3Lr7DpLZBbnOVqP\nI+r0kUdoAuVmrV7qDD0Gz0afmomUJlZi1rRhkNWeJchOdZ3A2ypHTe95Z+p3CkM74UBx9hCJLmEx\nLll6f5r8VOujQEiCppQMSnz9erZCRWAcAnJfSeVqf8Wo0UjqcoPO0JdQxsDwjwDpN8VjrTxD+ANV\nshOiefu6SgItO6KRLZRUme9ciuCK62vQPkTJruw8AYLg5WpUAv7+2C8xzzNpspF0JE0DZK8nQxEK\np6pfFcjgUEiwQa3Dlul7i5H/MRpVYvoUs9n66v1cjFEeJEtDuGGnW/BtuAIaHiHbekGvUsgzpbLf\nc3sLEbb3Qhg6+b67cK/GyqR3+b4RY4FX8Askh5YpL08bPDPBTanWJEjxFDIr4hwJLW/XfpdFpy1s\n7rqmVtxWR9g/hdK5fqcTRvsIWmhTOj5kP0xLeVzf5ghYljI4f1ZchGyeSPqd6xNdCqeChAL2U8+b\nP8gzOkhvIqWjzLY6oEQS0JYJCSfeQwx8BpGvZQDMAQ1oNwu6LUjkWJzm0ENH18fX2uaeWOeTsrPW\nDYZ740dyv/tjE36iPmayfFguDUPvjvzT4zpE5BaxuvH0T+NZdPHD8Fe0G13bWrR38uFIHyoEWebf\ngIj+yVWUF8LRDhe2IV6lUPt7hNjxCgOODxT+3o12B1W/8PuCSJb3HfMhPKbZyM8aNNqzkz11EZ7o\nWM1InCbvsNndMFjEZG7duqVgYSkcUv90jyvPT599Rtyr8Euc6NvdbFha1Dz4HRGLsihTulqG7c9D\nbTzZ1Iek2vZhOtQzM6UbAJ/LROmG1EhFR0YPStOAGkA8OBRde56YHG1rq2ZEXf+QrcuHRW+i5qqZ\nEp5AzC/QKwPUF0Ij8SnWxQj8YdRvyo1+BxDjoQqjAF68mVOvBGbYolY9fap2C3oMo4Fdfk1e6Kn3\nYpLFDxFqRPBc7PgCXGOEXjEBBIk9xXn0OosZECP5nnr/dJaT4dVN76Bq2MoF/8Dq88sj6xAogg2n\nkutL5lIa6k9QQ9o3TeibFelcOtw7eFWoWzsiYRYclsml8tcEWLGLXcqbqIvxQMsJolxP2uzMVc5D\ntk4nxZSqgI3K0XxvghA0MDrCDrJT+YmkouoXjaKwZJIRZ+VLJ4q/k0cXf+Blolah9XVJqsOMIibm\nquCI9mo2E/K5Vu4lKvCNx0dJqe6Li/vnkEaa3ZnJJ5Bcd4jgSTl3RgUOiP2ucKfQuGlbcEtivGFO\nO6VhQ2wVIu/AdZq0fpral1wA+AbYHxqf7WOLjlpg+5a9eIU62exV/xgCDqkLstD3iVI2VYjr78XR\noxrwFBqQ3MRwzi03K8vWSnM+QmbVq2zz+Oab08PGmLnrAVhKkfLDKRyiJIF16Pmanq42Em4Stmnd\noyRNskbWegAh6Ujqwjo+pmkZtB0sVClUOW79+WrM9HBioWlS6JHgJOGwGvRfHwwt7VFlcDUKi/RI\nxV+WPNRvHlUk4yIPoCcd9KAA8Wu/QpeQE3LiMcJr0L1DvIURZ+JQfVEk1SiJ6PmD6KALJ8v9EjQv\nflEVY96mMQH6jdLUhmEUyYIQSdYg6VMfddUGrGgXlNDSi6RckaNnS5iY+KklmzI0qZzt1w03/8KQ\nhiJwPvCw/H7HoJBZhv8AhzxpMZ0Toj+RaAdv08WYb2Z8DUHQmftfCzSULydN2w5gHMvmZqJN60Uc\nuzM5Fp7PfqWXR/J1ACFUKUDRAjEPAxIqIN2jxqklxyuszJv+hTo5Yug9eITKixxxIMlRz7IDB8/0\nVMq/pNumVJ8hhLRk+QnwtjcyiM+ukwnZ3rt01QhJJIxVQuedFSSiptuxsLXBSuh/HWvofGbQ663f\nUeM3GlUp289HbP+IsQ04cY9alN64WoQ53lVR+79wQHBan4APZKZQ54snZyTKtf2zaNqC06AbLGKD\nAeVSGMZIS328gwAjNMqj5zWdL5h3mORqpd8tyAx2S8EIjNy+fEWF6hk5e3BYqSQwS0/1VEETchbM\n+TPh1FfB/oD85XZuLmsbG5EO6fIfxX3GE94x5DRyGY6c+L2K2WZA0dfZDOmxTgC6WOZ/LaHe314/\njlOrHJUTWIM9L6Man9dWkvJ0cXZ7mlCSWn8JXIUQAviLVQ9k7zN6ik7UbLGd6FsGKTTR14ms/o4u\nEloPYYd2wm3WUQdy2t6fjrAeBsoG2DTrKiTdsH8PcysOrfXzWDt9oomaMtDtjkZu3TBALDuMRYiS\nrwuk6hcb2daUPopv5vuZaxVVYOUbaBYRIaFRXpw59gLkslpICXecp7Lbj4qA8dJPvP9iWBpW1jZo\nJd7pYqXavDHuxEeagDsRLtwgKp6hW8QWetWbIH4A1fkGFWBvk52JI1poPxT/hfbxwTXOHGnBVRdx\nR6iu0LYxhq8rXzd5IERLJXFrMDZnhOsYqANDyWp4lvtZErWbYua8qZgytHhGKapHsnF5n30uiVQy\n727ztlrgyUj9PJdOxChvnin7hq0anxtFJdC923tGpzUaJCeLH84Zq9XiCuY3PKRCRtGoN6IYEOmN\nUkU97mMi7fQfQFUI3Jr8d6IEQrWSdk9zXJLfUXqH8AaWmKNgBDN4hv/Ogd2h15WkmyIGRwF9nHkS\njKsDsEOncYvSeiT1tKmfSw0La+f+GHSBewFD6CcZDuH6hr5BDP5kQMdAZPsTgUTrWJwpnamYwOID\nNvifIPfeakwkJfDutPQKm5F0N/iS0tLSVtw2c/+K/eevQHzbY/DqB1pjMgQJxjWoSZb/kifztYkG\nt+Ia/0ATKi0f/lMSfbjbBdmRmUC76AGCpyMNy/XvC+M4uboimIrO+b9LEv6hz90lq4o3Apn4M07o\nH3eu9SiGg7W5Gaf4GbQdIE+096Y3yUtkDMWnTtjntZ9VJUjDFCmRQa+z7XsqzNv8HWtUSFK29R6O\no+JBlKipKSzz9BjOZz9U7EfDzb1CFzpFTP9SYM/FH4WFBxCVODLfHpaSu8DhARmRM5nR9+m/OoZJ\nAN8gctB4m6e70nr8b80GOy/yfuG0JLYdPDuYfEuaxiC/ARG4dKfE93VtjigL9MDhUc4LQQsymj2a\nl2kCyF2KxgMh30mpTByz3BkdUnAljlsOCLOJ6sSK3NeFwHlR3lJAd/75YLtZG5mIztfIh5hCXBmG\nEvLzs1TWXPH6+owxlaEmA7NGefOPMAQFGiGl7TACJCJdAs9pL2zBidTfSAlW1sTnafCzepSlbqfF\n2o8H2LRTFF/zfI3I01AATo59B6lIiXDzqISusW2oxw5wSLykY8HFVPvWTOkTDxbYuq5/HK35q9Bh\nahTJCaXW+XP2oWU/gk5qo0v7IFHjXCrSjlrGQmmPDfwFqK+7SExe1zFskOlSxGgUbsljeiSOB5RT\nRx64tVf0/0wiOXomiRsNgC3KD2Tv0S/iZRJzzN+hzAO7hafPLu3tscAZ2EjJVlleeiYhAg5N8Oav\nlAARCTnqLppGXsRQ3V9RSq1MERbVRcXHFHwMQYbZybddxGt8UDboeqQhWtx9rrlRn0v14s0mZ4u+\nc+VEpI2lO+hS6uUe1hMr1JbSeumBNUefYfNVhjb1Wj9TjwLIMfxpv9YHtNPqMfZ7nsOXzWb1xyfs\nR/rZJO3LFcpm/I0dPep0t3DTtYLD9nVurhQwHpyxp4/y0Rtjtj9RBdP+9Ker2f9nkVGBDCW+KpDJ\nQN6DsQrQD/lkfvsgjWU68eaLEsRmHjl2ITTh/7bjHudgT25z4AMJkAJ3S5zTVonhfxrszpX7GN7b\ncwVYLbxnvSA+59S3LDbUZK1E9Fw++5ntyEDHqN5dklGeCiTTmwlp2AO/UY6uD2w+W7s3TeUNCPvd\n5XkD00yhJ71aLPrDDkQ1BF7Es3zAT8jJmbBn1g4XcKcploIZIA68JzQ4/5T27QI+4lS3CoJOqHX/\na9IbpynMdbvRgHcSSgEIxMGwmAcoNa6BCnjuno7sRGVwEloH2qXWd0yOR2qkMXlwBL23m5ySKRk3\nkkC6JC9PJwwZRZ0vHEDYt7+Q/m6S1IlbMA7SjxwyrouREJdckvttAPtKgafS4hl80iRqhchSO1Wx\n7V1vWJKbY35n1m4xXkaGChNnpktdGDKWY2iVUCGbHiCQ84jBZe0BVUaJPm+9DshuISan2bGxS2fS\nbVqobIkX9gXLvkweeC1ezWVIKdkSIQ/9wq8w9mFMLU4lNKFqNpEHKV+TpxRramufik1BIVf6mWYK\nIak9QSocp2N+OnVhu/SgRT0Sbyvd3gaYHaso4wvNYcuG//x1k9LtRm6inelN2BAv5XoVeIPjj8jR\nHo306GlMXUXqLykYSVO760y+8+1hFimV/mk5JFKO3v5k4m3IvCcLwlLsS6XcQFi8O8Uns2Q9Z0Xs\n5qW37PDvzjN6XaTNs+j0yXo8qETX3p682bWMoeMHDeS8bk7uC5x+8ssOnO++74P/DR72ktvJtw6p\nkZsrTy0uvofOvVyeUpBfMdto2OLtOG5QH3dj1nVErfK7aynj4XxJTff+2KdYtei2dQUINBBsVt5Y\n6TqZs9gzgeNdR+Pn//WyVnTAk+dfydkHN3BY1eQ5Aj6hKCXYz0MkHBYelk/UUaJAdi0qdbSIXi5G\naaLPwEZKDJF4tXB7VWgevM8wOBY4eSsYnbWoQuCwbPJdKGZ9CLWPq6GP9jM/R88pJGml2Z7DpIkY\nRxksrae2z2QvyaykgvylUPK2JQZopfYqSAkKjcXVIGzzV7dSHhhzZsfwCEfAw3hha7PlmBznKjfl\n0WIdFx7W8PFbXJXVFnjj8xBsNXLrjv83kximTS2ObFXyaa1WrMbdBiKPtlQzoY/O3jqyWaCBQ5GU\nvvUshgS4x2A6tCO7/IWK/DOWyDmP0UYT3ebzpAUIfaqqVddMzCJg0aLdNvyvVPaKoMpp3IfMCiMm\n1GpWUgkPJ3Gf/IFKRAFhjKrUszOcMJHyJEL0GnXmUkg4CteDqe2sTdoN50u3+FKaaKniycQIpkq8\nbPpLViw11jUltWmMfDBvPF7O5er3Gwlaz617ghJ+pOrnAYRNzztTyI0C8+Fx8V56XlpzNcEYizyr\noNm9qxB+ROQbDdbeZkmaEBxq8Ao+FMPGFNwkBxAmWszuJTL71X0xBVII+2US7ncqe6VX3+Bi1BBs\n2tgjBSCepBVeKNq1GryTbS2i70oM8YtmfS7f/LV4h3RuM3gvaiu7tNhORhsLHKcz9Dej2NmP65A8\nLpXF9alu6nxAZKiERUIbCpYiMYiw1Diwkj+wuoW8RZ2cTNRndLrXyseNO9pEZxiJgv9UuiBx8dSN\n+BH3lul28hMDzNITCh3Hgg4ePw5PDN5maHOyCjaCN1IlUHBQsCUQCUmRoaByfwFwslSnmw32SiTA\npWDXpX3MhXHoKr7xcCymsHvYq7WPUQj1ng3ESvXeLXu0Ne9PeQNIQAhl/IneBTHhOWLzsU/hVtS+\nmZgS04/VOIQvgM9oV394Qkqn59w/qO/s0lbkUfhnXQdehnOPpnOAJ55dfjkXFPONuQTG1S3wsdyc\nZMXsRsoP/TeTR6d7rT6HZuK13xE+cyaXnEfKm0GrXUbrPvHxVhIkQwxhdXxq0aM/hczGHIzZ14OT\ntjHxYmUsZusKU3Wl9WxwlAPuFj05wm66ZCuxNy6WIH+l1bhbV7/S6cyCua3Q79EU8TepEwd3cD1H\nb9cJpsWpwD4h59+v8isrMsKMZhK2tt2PdlY7BjjQ6chGmZpvJRKIG6eJgnxBrCLoRfnYBVjjG9IO\n4CIOIx1K6yVyGjqqlea4W35JTjeC82ENF5vZmpsEqNHuchvpApUoopnq+1QnNWnKtd0N6AwlnlWj\nVBqtpq0sQaYekEnihv+NN1oztV6KgtkA+IdS5onQ8JU6NhYdVnoPhvjqk5ThKYp1Mu0Rh+A11pWx\nKlKkZvdM2iF0kEb6CwxNIj0Ag2eYkA9MMvDY3SnGcCLHSHQmCx0UCk4Y/irS38JmCE8/U2lVvEE9\nr5ViOeHx5c9MA004jd7XdRsmrk5ukYRrVINfTrYbBjrNHviarPNIJyBlGK/hDzSus50oFdDtN4Qk\nEjZIoTXGucCcmkVIXiDJVT1E70HP2b/2ma7pUkjPuoB4iHNbn0Fc3WpSR300Q1oLDzKbG/H8C9pg\nmK0262zVj046zd793mBd104gLZ4inJCDr3TKZri8+sXnfRXd7j0pbWsiMMUieCWTrNVHwEWfZ25k\nXjkbdOFz8Qf0mZEUShCpL6XQDWeqrJHxKO0tzltCkPBtUI7YGljcXO8g0aTU88sEZ//s3fkSyZ7t\nTK07sLvkMt/09/YqxoAoI0MbSH+dCM/jcan/M6/Wimhh0AcQ/hHwLoU6ADb3npU+udDIwP3kY0aS\nXu/lP0hhhNhmIV6swufUwmUKA4XKEggbN4s/udYgwRWoILX2Z3/K6weVDKMlQhSWdZhSKzt3SrZh\n8eaYxOHnLDLHxGlng4a6Y465f41a1b8ovQqc8hL21QiK0DumK8iUCNP6bJB2dv8ZmZ5SUc23fVWO\nozI7b/pqf/g8lr84o+8BhNcaBt7ETInGUmKrW1vE9jAdRqJexLnChIFeuEhkWvFtmgR/6hn75zVk\nWzSxGvobixlpdnkKVEzzLDDzfh2zjbe1WH/jwq2KCtL+LJ2HCQYOTHVvHePJQCTY20mJomlqzxpT\nMU8NejLJJE1PQa2kyUopb4/wzyWiRM/WjnUm9vIC0sxxPTg+CvFl2HXxlHv0gAmAC3oBnbn5duka\nScoYsQjzRqz5Og4CY3/279xHPfTwjHLnClKxVzqD14MMNNunw2wiDJglQtvPzIvqbpHwNRAXYnmu\nA2n3/MHql3Rp15X1HOEnT2/wwGVBfeZRLr6mocJMO0DQvA5Ps8UTCV113KO2x/zcmHOvaKA0kZsm\nOXSrOuIUSw9RoC+bMgL5Jyii25ugyyvIDu+dsRZv1DonCylg7WI8/QS00/8xju4jVYb7ejveODq1\n3NwfXtTMVifjwzUcxxhlT96yMiaxDR6QbUNAxrA74hToOpaCDY3GSDO1FNcAv0OkHpmw2RNhSAZe\nlvoYT1PgwhqSCGIsD+CBA9KhYWnOxc6g9ILRewn+iiFRdIVnjESmZeNEDERYEwS8BbTd6iNiCwe8\neDDIZ3WMqKbRRGEe2RXu1IHMBcYpOTF//EijhhZ5eP8KtpMYK3vKuPcWdAnAamhKbN6+FL+Z58/c\nJZ0H+UVdy+n6bDAQbJ/V2LUKjPxG0R1Mo68ORSxOI6gFkkf7PGN9Wa3xnT5IJtXw/pnW8qaP329g\nuRunYRluZYQ7vLfqapX1zDlJZGRJ+E5LMWUgH8OPYzoS80k5rM/h4Q8xWN2p5LNCd8fMLKneYlZV\nb/r1gLRUwSNQiSYi302AxNzZbn88yKjoAEp5L9hT5a3hbg7mhx49daaMTXP+x9hOwcChHy2kyval\nSveZ9XdmhNqUx8tcDMXMkcQGNfG3QBto1lbRpMSrTnJEtCQxHWLoRyvV4O7AIOqOb2AT5zAFzjhw\nNXxDHoqqkNp+e2Vw+8FxriJ2touRXxQwz7hrzjeahp7d3v9WdO03qz4XRXEjhdGteo3vXVP3WB18\n25ktIXFU1E7qyOSF2F1TsdKmxly61obA4IT6/l6FJ+Ecl+X202sJNig0UI5CXq0t0y2qpfMZJadW\nxWigQBTCm2ONRKcx4VZo+YAGlIJMjLp/Xii6ctwd3f1NUubeS2ODo/sSPgkGft0LT7cNCa5D6OGl\ntqDcrCpPiqcDur8SPUzKqKxJizXjs9FjwM7qWZajkDExAY8a0fAwleV5e5W+PSDN/v4j3WfqMyGO\nAxJ2Dq6b8aRvvgCv5a6/m9lHHFcgqZF0WchQcYlHELkU/+ZNbt/eyazSFmVphlPIsr1ic4njZ5EB\nvHAreM3i8dcSCTXMLAyCOJegOdU/oJIX4ayK3NntYa1BwOuIXFroMN8c7rbxVRBb5tPS+u3V6x3c\nxjK8GLcYkWZmFQCeiA/HMYpAG7YB5ssl9SxootFrUeaTGVIe8t2uRW9WkmS9FyNi9NDSz4MQUbZd\nIdwGf3PwlEq+pEUzpAMvxVDCce4L4b1PDHH3IPuWyfuXceBCMbkmnIsf2bvtVk9w2WObzTfB4T4N\n9dh0V6t5cHhvNbobaqwfVL/V2UBk63BBV1JgpfXW/9t0LA+Nj4WDz1QybUjE4wmpKd1oUBJH7DK+\nJx5k+a0LKIIlPm6LXXu03KQOVf7JvdgHieeFljZjGHeI3RVg1rNN4OQQxG+tSIpdVe2R9FmSnz4W\nnxj+Lae2bQH9GX5YpObavlAX/GgYdOH4xKSVdFg5Pt1Dq0gh1ZEcTgBVhwKI3o5uZ2e00nAXVGwa\nT0lOQW+g0m6+odTXIOsbUQ1hZ3JHxgZeCZ/wtWrVtCEGpYqlO3ZnDPwHqULxcIa3RfRmZqGJEsL5\nZwk46Cvs/2/uIFqXS4EdpHQT/cHH6sWg9qd7K1ntnbtXg3LnPkfY0+a4jD1pZEVX7Rb0aIaLaKwR\nTY+MryJO9FS527KVah1JKkrEIou+98l/WjK6E4vX8x0d4b+0XCby2gXQ++fm7owcvDY4x0A+nypk\niIBhwaHEs4SwgbQUebS/gVhFuUu6+g9tZX2EoMFi2fRPr4Z1hVg+5nJEJLIKT0naRRxKQNo4WFsD\nxUXlvVm3XuOLT4MAVEsj2b8e1iYqyP+CtbX/RaNvGVeEROeAouu/Jd8DNyl91Jh2DeO3d29i0hNz\nCIdpMIFB9C0rVOGv9r291LprbHmW3mPc9lRECnMRv2LID+++tPxTriQvqvahhrGO1fzlayEDDzR+\nPQ1RW4oXRg3GBGvZHYAMz23PRuEWKn7pWClwaI2sS2EuS/usEDBM3098+wDK+8Zkn8sXM9G0ZQWm\nmgK1DU9z6SH9soYfqA1O337omIsebl9O/RLn+7GQK3WrbfPQEKNzd34RV+t/+FSZVVbiTY6I27QN\n5D7ZEkfJ5BKEYHeK13hjMxHKWa9GCkWlQehmzxuxu7dzjnCIGE3/sphZJCcA+q2zaXKvm0z2HveU\n4fwICoAMoxAdKXXqsY/+IhXL1TBu4H71loDdS48SX7lW+rlX8KBHV7Yz5Or/PpI08DFy6yDlRQCM\n6Uuut5wQEwSbMnjyP85+RS/zfGof1pphTI+6Di0xkcWMW4+CXXgJbGhAYD8jVEIwuJN1inWQsI2Y\nE3P1OsrFpDbOYKcQjuYczGJLFF27P9LjRn8n+CW3Njo1EemS6HcLgX2p/r/e74H0OoyKg76G54Iq\nd4kvhwzTE/W4kadMBEVdoJ/pmENUfw1Vx3KzgZzYeZehCSvsaa6xhPvYK2xNdZMOlfwF0bpr0Zxc\nOp1AvRwkC4378ezP0o+yrepV7IuYoA1/ANmnf2GJLUa2q2k4/wDk5RXqqlQge1AYt7yNKgM//a/s\n+eKOV7AMrBxpPZGdhy4+VeHfA2z7Iww+jF90DXmfLuwzPJRpfOtT/76ZCmm9C/iuSmfXkrVe+0I3\nWSqmFL6YsMjKjnaDofD2aRkSKjv4/MFgG5iLj6Op6/xdsmWpyFJILv1dJskFZlG75bk3+xOmPtgw\nf5Gqtmd0Nh59lX4ptmfK5vb7zCv1v6l9cpmomvUx4BdpgJfJZQUVay1Ny5Y0dl6ogwJ8rqN5X1lS\n16fHiWVAmDwAtV0QShVuw7qQLnWZBYb6M8cXoBX5eC7WU8k0WEoK3YBxcBiIBiOqt/+yNWK56PTG\nokcCsETX8sejY5Uiyzh/Zg4s/Akyc7deInRgYASnPD0cydIU9SZSfnVwkAKuU9a+udrJaTww6Fza\n+Xa4gIBNSmsEpn4Z6FNyN+C4Jr7RxmjddrWWcGWeF9Fp/4wEeJbSIMLNTRHgB1AgsC8Gs/IamRNF\nHhIyqVF5GevFZU1TLiqR1A2pljraA7bhQqNJdq8pHF7YccR7j4NsUE7ac12FeQBaUEQbileiqqZO\ndqZk43mGzwKA6deMNt8lhOY94Tz77ZZeCgHF37EmFov/a0rP/7ayogbnJBmYpuNACVqvc6Hump2h\nCmLynro274edn4MbyHaQLek1aWcVO956IYK171U66s6seYPCS8KcASBA4Z8cfLwWWpX1l0brf431\nPoS66CQW9Hb9GPW8jtsUn3GrP51hb/NIeJqfkc84S6c/0X6cRfN8b0avssIfjOi5Jyf0cJ8/+XC3\nfL/zejLZ8JGk4N8hHtso41HnQWkL4ia+CcAqjVM1g4PXyNRn0O1w5A7sNgp1dNMCMqwjrF/AWmdF\nR4DDczmPR/jYpEjHCJk73oxkekw2j1dq6xs0Xuo8tt1ziNUU8I3mt0p38TL1oEoTOCCVD50C+we0\nKEqSoVWCCl7yIOb/PwOxWWcQ6/sBh3q0Hte7bJq/QwwiiVGT3jWTD38i7kqI6/LrbsTWMBr5gCbw\nweknm1LGP6dGltiDJ5OqyESdj9nghBoFtntlIWt5sov0m+ZdYHg6iGYmhhitPBMQa2eZTOXViCC1\n5E4YPNSBanov388NJJhx3segX9p9VspLenuyYG0sykZYRFFSc682ZOLm63m+1NMsUly2jvWDiSvt\n/uQweSE+8TWjPgZcs/xwqR+jJ19cfmJ/TdCfZUgynZVx5WJyfKRkgb7ZYdD6ECyuutAzqKAUAOoe\npilklbNTNtUzhS3QcyZjSdjr9eetGSSSZqSwem7f5/HxW6hIvJIFBPc9feKIpwtfRyu3WREkkJAX\nVOonC82j/DYpN5an9VNcRIRkPdMovZlRnl2KVDIND6YvvlYI/cbPaJ5fua2sCupXfwvH5NSreFMD\nLONvE7s7S3Bf0y3mebCzYsdyHFv6nVDn0geAZ8e6+kwnR0AHgug2UPX2DcJslNlchUprireo5pas\nVGgN7MMd6hEMQdYhFYqQ+C6Chyl7mOSQmkSOkqj/n6zfdSneA6V0l+29gkKPWx86+8p2PWA3M99x\nI5hoA608TeUgoHPNAw5eyKucIXkmilwfCNyKHMuOI9dgKPBgm11uYexBEZA4d73i1Lji8yA3Fzp3\nrj1LfNxiMQLcc1rqH1y29W1zAK1aorfLAWfl2RLz4//mttY6H4Hk6wwUA/X6e4yV7VzGx90l8ZTC\nWjiEN86J04Rwjz2QUzfXu0riQG+lFsSzALJNwr7Dygt0mubyNmnNPB2L6catR8FWOIwh3+3sr2i3\n5bnJ0x5WtLSBWfF98a733aTwMINTB1QWNzaYsN/CH4k61nC4qOshAGDHDFQLSTYwLJ1k0vTUoTm5\n5EKIIBBhIKixH0XLTWDG0lwZKHG/xx3r6pD9WKzNvz6UzFq9RAS+XR5n7yBaunuOd+XAeT8lI7Ik\nh8T1gN8a4ZxzMXulHtm8gxYxJX0S9dvEr5tgcdLEj+2rjN4CBO/Q1Tc768hDTvT7jeuk1/hZX+OK\nBWV0w7ViemDRU9nG8iJcr6Ss5q5s6BEytXAa+YcbSFOkMFtn0a6usCeDTI2y+lXal7HAv0r/jEhP\ns6KzBx+l4oKBtch3t8CvKOrtfzRfLhtjzu+xKyBYwWuAPT+uqrWknbpSFp3sWVwDgbLWQMX9Fv4p\nOeQJg7/xQ95zwnC1wQVfiURnvXNiPOP+55iND1SVeUL4QMDFOhh49z+xwcXGeQkdIVu++Yhavumf\nMenDFslpLb62YCeu2DXA22CG9QKofpbDKA3vhRTM3my7DtAcaQOpaVNW/cRlE5zpSxHVAkT4p423\nUGODYC1YD/z2FAm15tYuhtzyj/bjGtFh8xKQzXM9RMAn1Fn3mc2wGLh5dgLc6WoGen9ayuMlZl/y\nl48vs4z69m1mrK/MFaBg/003u0h5Uz+cafpQcxbnWe5CAJAXH5QoKTBE9ThGgqRnJ4ouaS4fKSch\nKPKaTTCHCVJeMgGnqfw/wC+BjwmWP/+oCqGvMJCgn+BgS3bCE9kPdzuJJZn6O77HKBQ8iiOXrEg0\nJuUW51+Pt4+0LzyzF9mNO4FkD+kRZrQvChi1Wnfcgc+u319luxvFBqIvGl/anRCP2T4ZV/5eoxDW\nXd4+IlelK5dJeruwC/X9cfEP/euzYEJCsjVm990gZP+pFFIfi74TysZMncIyqsshiggXSYdP+JUr\nQyyPLAVQlBY1Xl+CvlBTJ5i8lJjxsUn55ZXfeSBUqedPMyeBJWt7ERF2OhSn5PNZvaggYRVEOUmg\niyGyxdPcFKQAR2aOZ2Hhc2t4Q9V8asMl71rXvjOWfWIA/zRcPiUi/gulEks2N+GtJdg52PP1LWzP\nq/sc2bSPjEClSwAzmsE5ts+p69c6lXZWhDcWstaNwXZQD01Xbo2C5RyerO9ZF/uXx7uuKwk80qm/\n5nQi+sg1rcFAu4bjt/7QIF0V6VmLiNQDgUgiyPbVwaC1fQ1GSFBZCdUBbOSmeE+ZSAl/k9z61xXR\ntwMaU6TyKviY1zNLbcM/o4Y5u9Cl5oaL9uBpCJXlNa+L/VNXYHM5H5EOKjhIotT9GyWoRrSSNDOb\nokk7Rt0jj9dOGQEB+JDuxFTs0opBPoINbDFD4DHJ0MCPMkG/itmcS78cPrZvXXEe053Cauj/by1u\n24ZXReucHvGMzUCVeLcT53pWHE4KYq9tMhuRSgavoGc7mU9K1L4GR5rQm2j0qv9sez+yTBYNHqO+\na0Ue6iEW76u+U4nUfd8Wnex6fDP26/T6rYorK7DAMKIfaye4yCQRxzXhyDJuVnfWYmLrRpcSh8pO\nVe4T5767teNil3W6Ttnwvso3DU1IjBeZJjpDDqWSLBhwGLr9Q7ymos9Yvt04sHjC55zHfyd4mOhU\nJvyRH96+27/vAq1z3GRSYA/OmDDIWx1OdGWFZz/n3HobdGPvipdEfo6AqlXa6ta3t+BxOpiJs4Du\nT2ZtiPjPDr8JVoRQibtyITyXCtBcwyHzVJxDp2HtSEju+QeG2lKhZsMWWsaT5F0KCDyLZv0MfUJ4\nPGh81zsWznO4dpx6nWH601IKGJHIClo/CPyXy+x/O8maQJEM0GF4CvINsQKdoDQVvk4oJVDQvDNJ\ntCBC8Ja4UILusdpNCu8kj7Ji5FNCNfgaF7UoOw7eXIVmGVMfXIQeIAWFQsG1P6v8BmlWNhR3FT02\nglgV/VSNixjpicYpqeISgqVf6s/DDWSkXFhp0SYd0jlNKKBn+IBX9pfwOdL8eFXIp9VoIAVpzaHB\n+tSqeoGoB4LfGT2tswEzjXhau/BKx44wdnfOjhuglPvWyW9yOXo/764DWSKFLPu3uAeDsN7GCwrv\nt0NAIs6FyatfVBPJiaoikoA24ydnhEE7fN12paWyVNXdDknutNjheyYlP7zPRAQrfFEOmtDNb8a1\nJZo2O/GCeZqorpcoPYRqKh98F9knbGRWLUut0+PLIFIh/Wf3SOOOJ4VbDzOfPCHJB1Iq2fhWfF8f\n1TqJKm1+kq0Ni3fhHIdoIuaARwS7wshJVIf7wcItZZV5pIs8PFYtQ2eYFf0v7ARgssZVCVZ2lMuM\n4UMkpTvhgVsB5WJOAXnoxM3qwBXBonTPffvyxFRW+eEKJDRGO3neYY5Mwrqe/QL5eAnBBgqTBg+N\n99AftSLSyFcttqysivxjHSQlt1BsjQgG2YGAPhr5nBHllm/7Huc6rGRYKckYIYDWNBFy1sDsQPu1\nvrgoqPDN26K2HeY/x3tP2xmPHkOxybuXZKfFcR0oIefECq3jjAM9LFBAVZmq+unFd2TghyxzFw36\naWDJ7X1d0e5DYep/+CuFXqCsAaaWfz6JFUwSormCZdzarQwQZpmw5q3XFbUq4uCO5farW+7XI8MT\n3qMfOE8hqpCTw8bl5BsoS48yxuquaMU6EEqNfBM0BAa7rdog+IZ5UzycP+jlS5jlLwPVF6E0TQC0\nDtRAIBfBl3LmNM3Om/ePv4lmZb+0cHLxrgpaFnWuSj1n1BV7rf6dSNq6tK99beg5ilwShHv4mfQU\nFtfa7YAWjs0BjQtM2MGRcawSoQd/fQ4rCAcK0kLsK8IBLEQb2IG7q7RD0Rw6ywKYAkL+r+Fxv29m\n7BPhO4U563F87itZhnYbTkPHH36dWcnxMrqP5mIt+4lgyzBSjNx70pyZyG/D3RFENrrC9aS5cHFU\n80+GNXEhjmpOWVsJZtutWZJuuVrlFjmHdI/GrFD/2cNSWTnQnOFfjZYf1bobHgKVo4FJ01jdS7n9\nHcmRvfPyCqbvC+hXhlDeFpT6FrkIjKzWrZnwinge+u7cogU2reJ3JP1K940SEaMgmV/q3x/L+RjU\n+NHw7klD5EQLjCSae0vxj4/kgFfj44CuZbV9MvFuYrPXsxh0kMY6c880+EXfBphMmSqoeBzi6irn\n8Y4tNMQUx6NLuIcPYrvVj0whepU6YXP2Omed8nrTzbJMTznA2oCd/HrDquqOY+YeP1LDv2B/1LjV\ngQYvDQmpG3/UUd/14v4ftKjIVwxx/bwvmUcKA8GcJ9KhEUByTv+AVDZmYjBkvA1M6kWajiG7E5rk\nM9/PO5wOV/v9AX9OHNTXufnym9CMMN60bjav9joNZ7YZE+ZWRQVAlFaxrihqPropqVxCtlKHzXhN\nXW4s0YawMfjgyGE0mlsAYDdm5axVuA3zFvXU7pfjBgHF4ZameoQCSTIzLm77R1u92L7zbssIVnRW\nxK1rPl0k5S++3eZE2IKl5uwzRBfyOxv5iIPWu54DShGUwAuP4+yk08yJB6f3XNqrSGqXxjr3GE6s\nlvkZBvLrpXYD3iC4VarA8JGmCOwNQGVJdnzwDKO5DOX3diwcaPb/KZ31lA9xUVnsuAvkNlssSued\nGzLlQd2vpIIocYT799cpNeMTd5Nj329IWXN7vaeNDxQnFooEMS4oi0C6NZpRUzBh+Rf3wSO9G26o\ntoBhFmVCKQJg+F1CdH1J0Jn99vcUGKOkgqzxJj4mYSEWfZsDiWJV24fpXFLluvMdI6v9QKx+Lf4/\nnOPcvnfKtXpC4mnLnLNcT942+Q/sdQj3M3/D7Z1TuRvlByUsiYRZ9FGHk309yisGXTjELRdWL8s9\n8LVfoWm2sqAWW+KKYH+dXz+4p2S94RzlFYxEfQLAa6TxZKmBPpQcQyfvd+lkmzS0F9RR7RoMlC4j\nIKjtYjiB3yLEi7P243qo6ms8tADy8qVq0p45TtNzhLzlU0kDNdPJXfmcbL0zXpebZexs80tGrNRU\n7UFUyJaFeYlDe2W5M+BoP9rcA2bdrX/nicjhu1//3HJyA4LM9s7uzggFXbe6Ljkoh1KDizqX6bQC\nlr40wuZ7sWK9Qb48ZH16V6ndZ487AIIhqLLn7NLI4xAoDL4erCbCKKuYBKWWYg98K4MoALubgkoi\nshAFIloQqK3chsrryHF3ZHs4wo4XCRYKHzGogFEfSZexvK2yrdXbYX8TiZr8FzkiNBvt+/SyRpvb\nKUJbLwWeaxmBHCsuDDgNgdmrj999iAIDgwrW6AqHXDnVr4r/I3RJAbgkc50t+w5ndL1vcLB1n4YE\ncKIbEhT0Fnrhn719otvIOZkB6HlqYkg3qRG7z0/VP8/XBQoMeSKw0nTDGfpwXQGVhKBek2YncAm/\nVizdGIzSzgxH/SDqoC0ULJIf6x142fIkgeuYAVu+AzHod6M9dlH0VeRDFDK4Oj8RLc4rFkqaD00r\nfCFf8oOvuPt4Wi0u8+uvZBTdtEYt7KlY/cV9BBLwk4/oGADzUNssnMrq72TvFvGOrmxKZFtjECRk\nHwZPrYjCf+vyLWpCkadm/WeG2EA8VyN7bVli4HYqOsowy6GQzMHp+Dxm1FQDj0IcgHPH+3d98Cf3\nVXj0K5ZbLjsguGFrx5g/rrJYTZm8kxyHZCrP7ATw2Tz2Cnb99FV2dE+0AwrSws0c6/re9YRSOIvV\nu/GrhRHtOxXQ3Z1ZE6IW9+onBZcZnxhqt7WYc5afuZl4GYc05CYrkgjH7t0mNUaaFXC1B1/+Ju6E\nXKBg3/bbEXj1Yk4hM0A6qKVG4yhAWIlRXf+qYR2yfdJJ4vekBYQwRGD+vsaCD3qM+BUx5yA/ewd8\n1JiAJ1CfLscgTjRC+Lt6M8r5RxW1YMc/XTExOG6ZtG6FmYS5f/EPScDKMFW+oeZ0ZbK3dxpK1NtR\neWKQQ6zMLlLOsXqLbVdUiLB17qIPX8z1w4rNCWm1vR15YUT6KUdQCB3EQW/+Ubdp4Y9mi7v/Kd4m\n2C+KF+qbAYcfYSXumLAqaikGFi/0U8DMMMO4u22+aWzlseDLle9gtQydj7/6o00ASHymAvTjbN/L\n/tQMqlCzsPte6DV8va/M8uWBNs5wcY7Ihw9whx8X/QAWo2xzSnb9YS+LhGCK0oy4xdXh+U9y++Qk\n9LobuRJfTG+IJSf/gRqcj2xm/lqnV/8L2ESUSEDiRO4Ti0XYYRAlZj/qzRye+bcXOaB2CBC5tm6y\nZr1A4IFjMCHjLrAl2Evlp8+OGRCQLvCLPtwsaHAYJzIGoVsd29CEHJ1cebLtjcs6ASUYwaGjMIcT\nwI2lYUIMifqFJA/UwjGAiU+PA2rk96KrzdJJWcPqKogZsdbN86/JlQzj1RcfQ//Yd1APeIDUCH/g\nZA74yVtoEtW19vZOd5+vGU/eQdyNVA2U3y3OO+uBfSCbGrw4iX3dvhB4vTVtSoTTHB/nAhFlp94u\nRSx6x6IDW7sPp4AhT/B0sSDWl1wpPXOTKetkl3Tk8U1p1552Ij/O0XAinoSrZVuO2RkXE3Z0CNKe\n8Ljdcl6qRDoWeOin/+S+8vtdxcD8iNT6tGYiIIXKxZqWSDjHAXp7zgatNpndU5TK/2+rBy0zx3Om\n1YSbpfF2+dZ4lGfbOxRu3KbYSViMTKYJS58I4y5f90Vo89B9FhSgWJU/xIQt2qPWBEPEFsKQZIzv\nA6CuS8Z2KhcntdseKIOagg685dDK4us4WcwVO8U1iW18O4K4/iOedIaa8Szrt54U5sXPFWFJPc4q\npWkhpTr0Myc1l8pzUkRj59TWGL2gYaR0tvSDrSwANn7LFL6I8hUGvf0wAwi8tS58Bcy1hbAqHnNV\nJg/XKnjdUiePhe5b0X0bJ1+pA+F8rCQBveL2QBRwF25VitNp05JyB/Vd4su2NxwK9B555uXKDiT9\nCEICmKEi3PclXHVFeWpQnFQafsbhMlOxqSU9RH9CskL/SBwOoDeGP9nPIXzIjMegtaX8XdtV/Ikq\n7Rwayt+fybhxf8zNq/H/Age1WyviF3Ie4FcYGboKIiJzHu5TqospubKIa2nj6w9QpgW4Dx5rkLyu\nR3pF3HU99fL9zTfyzNCYPmX8JPCMlFtKFkyJHHrSAkogunCn7+K4xw6k6EtMjA3cu3E1aJWVAS8N\nONIKWRe2PJeZkzewjDtSVxrBFfBpFa5TZzIOO5yM3XIJPNhYyUCdDbuyrSZkHlaRuN/AqLs4MigW\nBfa+WcYi3sN6c3zPjrTknvGfRKX3moZpyu2YW+LpSFxO/LRMiRGUyIHdNtanEX4kEDxqhVkbvYtC\nr2eZy/ldilTBMJYRFlqn50F626YRqq4k+jKy/y+EkMkuI49Z07+V+FujJChU/dBubI47gHfIV1Ss\nJgywld10lQGh8xCngg4Rnmsfi3CCeLbRqJPXaOylaimoPY/EGKSKHs5dEH0TDGwEWf3aNd87sVoW\nbGLwU10f8orFlkvAwn/JuQPSzjnD9lJVQlrUq728VBEUxwhmfxyCCTPWwISo5LsyP/Eiiu/tt8o5\ndsG5pMEbwki5YMVxtmsOtd7Kn1Twa5FVqGBx7Na4gPycWf/QzuIzmZjXeLfV/qpzCYd8zkhmxX1y\n59JQ//Htcanbs0FfYmJL8N4TFAJRtd4ywPm7tIDuPDyXTmm/TNIdEzB4bbeEAYM3i91p1yyzOMeK\nU0d+PD9WQZOBXzteIFabJVZW+5wI6kda27n1oC7OISHqWzKbBoMxXniH7YM2Hae6KEOmPISdGBX8\ncM20fEkeNrGE2hNkLRQzPl3LVm2gd4DXjIxxM3Q+e1WNaIotnm3b4tI3x7iYnCxY0o2JEaljL5Ga\nmxCkVb/fbgnZ1i9f+KP0siYDQLfNu+YuXKd3FLFP6yXFY6j2+nLolOhZz8L7EMfj74VVVpULLiz7\nf/UgVCHU9iHGvLFDQeQ/r7tahYHKAMLOupV0rUHmRBHeMHp8F2ppYTF7J/btWvBP1Q05uuH01tLq\nGRyA7JMKKrTW75X7IHnNkbbgeA+O2n0wyk7/DRiDKmWMvEcBjkmPzXDv2xdUtDpyDRFv7A8N1eYr\ncZFfHjgzQ+ItSHhoREq4v/Cb/HC73kDcdhrWeAZGefrOSquQGKbi/GnldpfsHXv2p45qfDrKjhVv\nm4Kx/g7v3puw19i5so/kWSZQjOH8YQAC8Y9sKyR1Vs3gkTAd/ssTyXlFucJFaZKv2LUC52yYgjtM\ndxNi3YT+OYU9vMba1GuILg7++YC+aR+KKAjTCHbsONIeTr5xuuDbwj6s8zrr/Sj0p8mkMOpiUnt4\nm8Xod38qHp1s3JCuQia1+WRMb+1JKwpX6kwxa/grwtiDlM3+Ev8PWXZq0rQy1QSTOnJFGbc5HMUS\nk/tpnEBK4r+9r2RQRYSyQsJce2R/9ry1TFksVvJlPIokCTjdGiIu3UU5B52S4E7T5A7RSvgUvVg+\n6fmfvewS5DNjLQ+I6Jz8/B922t3dBdJmYjZ5IQXUnWRJCuXxhGRhj4EofkjBjx5DPlOivP+hRYJF\nlfoPZDgCDJKhIDX2csci61Ik4eWg7q2NMlMfB5p8py7Wrl3yXTLYvFx4OkEjTLwU8bOvM9j2fDkW\nalg8ccp9mWiLfKXCSgpSX4wuIkTsUvlkaBf1AIVabWVdwFtlnTgPhc4xke6Mm3wsot3T/Tmho19l\nibmwEgo05xy3yoPjfN44gFDTJIWqPW5D95mgY+7YAd5jBvtbR27NBMXnOt911P434iB78KsRNd8s\n5Ka/NcBIxXFfFPfj76YrTKimzMk9fHW7+Axvf3EGmUCWhJub/d+NNs/7nQEaMuhrva3DvfDHmriv\nBMF1PassXUtjYDSKvhdHMWT4JXFLiq8tcQZx8GMRrXqFR5m0oIyRTxY8bCpKT2wXW945VGtPEYs6\n8g0uZWHY3Uc1m3LzGVPJJzGNnuaI6wxYhanjY7qfPirZuGkUbnDn8E3gId8sfZ5ecpFtrVf5C0GQ\n7lnUH0T7qwNyWaRQbRgAg/YjvbEBvkz/7dr5+Y+0+KZ3KDcVIHtuVKnAd5qM6SFIWBU5df0SH73V\nZRosEQsqnUL+Bg5H0RiCpimcFthYICOmN27WqxazLPNhZLQvZejcfnqZbFwMtFLyc5fWyjV4qlAB\nsded/0C5lVUG/7YpBJHF9k9ncGp+l/9cR0Ubi0TbSVSpryjORtFw84aFF54HgrCcZ0xOmhc4CyrZ\n44sL1/8Qtarx4Twz+WMO3ihMO5X6/VEv9pOuyucGaFCq+69KsWzd9Cx0Q9QBZf37GMgZdhYTtVSH\niieVQ4HYaD9ZV+2JLDT71xKguzaxiE6IJaxD1/xhvv90JBun5Anoir4Uvl2Uo24rERV4asbtKlu2\n9KUDP9SEm/sBLKo5+IHDNmImpBYo2fdediwsKyULu+6s5il8sj6nGXijOHP5T9zwz1i4P67dzH/p\n+AjUiU98Apw4278O6+kcD6QyI59s7y00z8NV2DCBO8282nBPRNP3B8/XLi3HOcAjF5vL1n9ZNSET\nJLbBu2HNOcqGjEIixehcLYmf/gqZOZc9ovBzwadeIbaudA2CsCKIv7QtkSs3NmW4R6e25hGNwHLB\neuPljM871IfnHvd8bUPc/PLYb7LnHzQCep21gIdiPaGBu/DBgfRdTHXpp3ewoxQCExjN6M1EtL6l\nhsaIIpL60cXykzQAHfHF/BI7qx2DYmqM+7q9DnlRD4p55XAR2mne12Mxh15T68d6YI+a+j/T05x+\nNasw6gBvR93Ydjp+oePT7iIyiJxCvbPtxY8GJE+j43lBLpIs6UnSsWe9a6To3j5DUGVYKjAc3iVU\npqgcFYWj8BNpFvDyxnTbireQ/hLM9nhX9XS9Q7HPmzNtFbK5ypgXGiI9uKO0os5zOK5P5V23J+mD\nAhogqQsiia6voU2bE4TV+MCOsu50LuJDQWONInXj0AzXjkr/6XKXD+3F/JxAQGd+7nB/QF97d5HC\n2eGhk/QTXY0C8FlMkKVQ9rksK0lEwnzpJTHIbcquqEsdV3dkqxgUurReXKjVIu2XcFcMiHIWyBcr\nHgJXkvLYpR4sSEo6DLy4dq0XlygoDn+yrc4Rymzpz/ix3hmODxQEdq3vO3YfNU7dcpptDHeb7X+f\nSpszJdJRSNlf/Y6ZgkEsjO+qaO55vEp0E8aqBMVeIh1+4VUdmKfIdw2in1mhO1mWm47DHeYe2NB8\n1UsBKrzz3NvPpey2NxyhKxT2Ci09wMjc3Y/OyZwGHFpUDemfifYF3+QdkAJmSJKJGLDfDRMcHeY5\nALUG14Ht0owBHNStIhqcKc0bt7WN63wPeAyzHk6I8B/cYP7mYQGeDrhTQEvgTAQezzMwzApIlJNV\npas/HnbbWfFobgfoSs5boPRTZ+dkpoxwNN67tSRGw9IHkqLVISvAu90uM120vOM85Ab8/2mZUpos\n8GKH3V4WbTCMo3jeFeT6Dler/DNdW+Si1AjVSvjW71RHCQq/y9G6oDVOsL4hxogGxTDXpx057Zqv\n+WDNk5IjZ/qg3M5PliqSJTyN5BmWsscHiSLOvAXW1i2exDISUeA0tdMbOBVY22BMnEN0ArFQK+3u\nU4l7Hz92KJgS4rlv2E6EXLcAwagFkw7zPGlYMQkAi2taw1z7Nus2ggjVVWXsO8riwqgwc2q6PYxs\nAVBwO1cSAPm/BgFOEewyAbyrQnb+TBBgnRthbWFQni6g8vMiRjgRmhzrc/McRrfwZdQPWhiBCio+\nm9xxZ6crWqLwAXjlLjAFHdN1RaNyPne7TBMSQWU073R5cJwubRyydOkEumh2dyMt59uMs4ucKlyV\n3DMGIEM3DzVL5otvxzr6lfqNIFvHl9Vk4jDrgBnF+98MrSbkWEmucFD59IBd4CZTmvl2NPtQgx98\nwB8WiwNtSHUHh9MSoQdLkk8guHP4B4GpzXaZ4qPtTA9kavqcQhUpmOkCqaWmf+bWAACbfhmc3ntl\niPsPf65Z/mBFn4I/nO/VMREMLyl58XoyJH1aYqOzKwKNHAQDUtNewoyGvKgB2RS8AMqyHdUsYp5U\no6yMfGH3lwpttUb/vmmo97P4cmnFNet+G5wNr1BjTabicbffoU8ZM7MhEZReYh5QmG2M4NKu7P5d\nYayKynB0lynTEDvVl/t/UQSaMSied1Qkc4cy4g/Vw1QLijSJcLp1vivFUxt2nGGmJGLSD6Jxukm6\nZaoAHtOp3TuOUC1Jn3XKiKUvO3UzhHFcmqiGkjWtXdRuNLRo+C3eZGcyENrr4Ivl4hwjhgAqSG4s\nV7gae1TX24EQW0dpcQwjmt2rVzIm2V/cSuaEUImS4JD2MuVVLZGhfdvUah1YV8YenHCpH0d94Zk7\nyvquPx4IDnj9/wKLO8R0zn/Mon8yenadTSPrPmfjDSjBYsVfBqRBFHzRrn5+PqWF3J8fVAivu2HF\nL9xkH7F2ZIB3aXT0CEwxjSjKsr2nyvu8iZqfVHCuekbzga/QPjSglZW+qDRq1l5TpNoxZAeGTsk+\nR+SkVeOTx0O/PmFQFyWMQYd22GlkytsJL0twpE0JG8G896AOP8WrWpv5kYdABqyUSOyIbTrOBg0x\nApIuo15TodYQGmW6HFUGx7Pss/B5OZT2mNV7e1IV50ixgBpu1QsExUFra0rkEnMTeufWdcnA4dlm\noyrzjCwWRiNoUmprcDLz0EEMr1AlRu1EG3LTuxFGgvDalgvohgIOWUyVFiZ2ysoSW0s5Wl/Ran6h\n2IHnSQxNM+6g7Qzkrj1KuWYIz/MazDfeXgU1HBVguZT72GTH+JggR+icevluj2cQ0Kb36tSaqeSZ\nvcYmPjJbbmxVzPlN4cl98gjeRmQep2MMZetqeHQdpldJUbfYUB2ZskwJWwOxdSrZsXg5pjUmHxmC\nhhkboAsswI3P+6Wfm1z7QPdgl6Pb8X5Z04ivEbnFhMZ4+AF7fLbOpYesNVq1uueWgrNkcr551X0L\nFEHbq1WOp5aPKtBGDOjDeRijzrU/1BYS/bx/ep5tvFpQ3Fy7ZWOP66uJVjnKgfvpmu8DgDVCRf0m\nkSi1E4e2OZg/yrPvWhDQvWhz30VIZR7AFHLAnqcfW5OREd7JnQnSU1Jp00ga0qEskz3wTQSQB4bF\nkIHDbx1Bf750BfdLuLudWalUOiBHi2VRjiR76D2NfZtcMIN1EykJ1vT0N0vNsmnGCDYnfuQZWTS9\nn0+xpkstRx2jn9BCdTNvBsk7CSL/QqaA8X/WloVVXk9BzORKY8+stROzz5P2xS46MgpDeIVSKEgl\n8Wh4FG5KGb/bPxa9r0IL0wSj4uyzcVmfJi2d/uR6l9cMATDSNTu1d90WDVABR2VuJH4c2VkTPzEq\nVEv1qBLzDFNRP1ukPRuzBolT/Ogn7zXmjwlJYi1qvanLI02cAYwJhEHSwC9YS+ZNHRgJeVXviD+d\nuE1xz9PFpF3kMuT04PwjiI4gP8rAAeruMdQrJdhPDVbwHTgEogtSEfTgy0bbMzivkXefyL6AIbvA\n8QElZ7V2f0g2aicNqX4CrmzaH7prnwa/8TsxVDX0Dqv1YSe9EqRKZjyGkbiEt2uhPPLgd97qzjHd\nGxk6bwcVMGEnUAQOGmIxkkaz1o3LXekL8koGoo7tmVd/rY2LXtz8Odhy5n4h1SyHXpWPwOYWtYJt\nxwjohBb6veBvGmxHYUqwqiPQCL1fTYeVyYX34RhQ69quc2HBOpcaoJXcSyo4CKEeF8jREDzSsynn\nlQOvjd1PJUp20zs1Pjt0R2MR/kdhTxnPYawCuC7nQAwNTya5Gqyf40W5/0iy86Ij//xmewXY2bNf\nVX8vFn5x5LJkmP0Dd1lFh0yUFuH+8TPx9tKbiDRnJ8YKxyst+CacZ7ea7xFoIcagiecyfavRJjPg\nKjex2k6D/OFLEw4UFb0mXqKmKNuQX8PDJpO5ouI7Lq8knxWj7j5WDK/zR1GjfeeVNb1w1NSzktCa\nuSdwpbCeOTH/Dv2nZ8GrKD4fdU2cK7qrgov+klbEVAoLVmQ0t/I2g2FT8fCljlq0hWTU2E2tas3U\n5+nULfVbk+rjbSpwxITsZYz0VzgA8cANS5vKW+XHaQSPeAWNjVg0CwpWcgUTGcz7tvUX3bBVPEuj\niAdv78tngefyhC7yb26l2I5rZWDmYD9qxgkQMhfQ56mksWPQSPrke+hdW0ySbwTPjJ/g9l6+gbl5\nLbnaUzzU3V+HB3wC5QLBO5fhOD0r2cFjqzgtcP9Bas0ca7VKJ3EZcH0+mwv4hX2XbIT6QBUVlFrk\nvo3EXd2NcwWYAqLDk/FEyteWA7imk43bNEtvlULJcPyg8Ebhtfj4EgA8JAW7TA+ATADhSYh5sJf0\nodJBCMcADU1rrZHkwRtXuvGmygfcM10mO3nFJnkDurb4sEKlv2QWjD8FEKoXvUNHKImDGwkJa7ea\nRN+wpjPNgItTVugXovrQFineT5kCVpYAyPEFwjXOnYn+uvfsIXUVZlU24JGzN1Og6ACZFHPUlwts\nUaFyi/kpXBbkGCI97PTh0jKKbG9C9xJhsC56dOmB99sazMCGuIQVAOTNClwHS45lZeYvD7UBzY2M\nGEY2El9Ywg3gb5vQSKYSSgrY6AzU1/Z8ciwplvCAkesb87Xfg5ouYLaejmiGYkaMVi5aovfGe+rp\n850sLqLDeAdWf0VWf3tUx81DpPNtpSBcvM7J7YKF92EJEnSqtlgLPEbVawTgldOxXrW0Ros8461n\nj1+E059mRrnzOHTGjaWb/nMSvM3hFZl/Mxs31VVgzGhHBd66QDUeIZYc/7ojQTYf6OnvRc/W3Vj8\nCthO9fqknQ874tmPYKT3snzzT0tUwurNVWdFWOyayxxQD+CnQYqCkb0gq7rO9gvr0YWN70ac+kuw\nPBi0w8mHtytBoFwtmUDaEHCpgTC7tXmHyi6yZjCXBg+NShWy+kUpECuRmUY6jlYTFZ4koKGT0KT+\nj90cg1JOqtzTutjI7d9QslQkVg1OYVfFdZKn8ZBIWqhX6fleGay7lXqB3uzARO49Eg7l/Ff44YKL\nJkGS/0kB/EPW09Xl0PFmgGyPX9V36EZaTlh2l2hbg2rm7YZHK6gG4jle4yOf0u0A81ihv+DbWQ45\n4qpwDeOBhCWc2vKvxJDbxtedvqlMz0YdNXkU7dMNp62xQ+9p4UIZma3VT83RdeqbAOF5k8mkrIzx\ny5se4nOou725TEsxAkh6PzUwZ8deZ8QH+hQ2HZwffjZw6GlsazA+H9/43NDWMjvN9r2Evq55LtcT\n+/LE04OzlHlP8fWPmcBWv1hhuv8vP8KkWGDtyoWcWk44mhyFrpddU92gcwW0IC6+v1o1BlTw/OJx\nTgsWuFG3HKcwQwicUi55QKJIAXG2EzrTSsBQIh+bYDctTZb21+pS+xUiJFpiNY9Kldzouxzo6ktE\nv4tc4XhisimHftupJGIYXgpPCd0IqYgvohpUtSE7lGHJZqw311qzdnXSmQm8nOKoFmWNnSXcn190\nlKRZZEi3XDUGrNlcVSXho9ABrCXcqLUYOe7/k92rt4y4bnYNlQzlXmStNW3QTDmCLk9M/p87PMxb\nI+l8B3+xQQHKfu6W4dS7+QnJYl5mjXxdKtBvS3J7FyoHRblsxmmGqCbMB1/TtlAlOB6nsIXUdMSq\nwMJ7TjN6eGw/WtVSgObZq58Jy30hJ+eTLeL3g8WjioTc0LzoSWNMFl4DLe1MqEYIZwMWicEkVo0U\nVH2qCOXe1vD7gaFd5aSokkdlcbRVBxPTXohWMeThTrNceec2I/pwro6zGL9JFlT3gcWUm6O4u18V\ntkmnYngQQI+YBAkFG+4dZMWtWthY7JhqDgMrufcbRlnbDpD/Xa/AwbVaZeFElhHDRAL66M7Nykfe\nOzW0Pjl0BH+uFreKhJpz74jOSUyK5ApwA2yPG7iXKQwI9GCCD0UsakvgDdx3DDFFpFKZJ2OLJtfF\n5/rUXov3mrWqWX7er6zhmJGXhBRgjYuy+tyjchHrIgJ8x4XLahFw7oK6OIlHaIEfkT6fu3VKe+wo\nYRyTbzOIdGboaUUH2LFZmPfXf/Tz3w8P3syWKdTIequsEuhtiz1saOsxDaaudCjT+mv61zTja1wT\n5fklCMV0AfDwFpNmL8oDGvJUMO8qHACq6Oib2E+2oUPRhNJ5XNRZEWA4LmWesY5HaTZ38qy4pNk6\nsM3dOlXJK680mdRcsnJ8JMZABjEBQoGFhIobk9/3fyVOQACqBQnii0MI9g8X/l2fxmacE9Z7se05\nNJvBEobKrsyU9xR3A5BiI7CR8wYzFV9ajXYD/YHAi+mkPiTPfRalb1eqNEnBOC1BqpAVk809XLTS\nJWHt7uDsYR8tQYqPh6cUuZ96na6y9lmXQv8D/jEBiAhbhsJi4f4ojei3qmmP0hp1bNc/Hp8pcmJu\nG/sfguBWy5ubdobhQO676bkEKfPwjHoIESBPAEP3rvNdYd9oZZMmFnkpYjej/m4cvdMhFqv1auEF\nBa8fLgH5HDTjzyV0bMXLL9yKYo8xcdKIv/LDnVncw5q6vHLVx6xFYptg99WC8LdS77PGND1P2rOa\n64XG5rU5HxoUNro2irx9OQ4Rg2bXTA8bmJ+gFu8GTGtOspR2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vRlfanJJX+V8vL9059DH\nelw38F9aWWV2tN+m2jMGYHze4oZP+TGGQ+8vuAQ+QpZxBDi8ZIeyZ7Q+VoGZVP4Bv5k5kh2VX4s1\nv/4V/gYTk2LlrwIDgHZDEzvtBZnxDzcilq0FoyqdSb9IZni84Ko+MMMnp3YFd6CHfTxUoRgghk8h\n08vUvVZr+f+jD6dQS5kFvN6lC/GIoJW/Xc9nQ1Nm8iQGXCDx6bCHA15IKKqAOEAXmw3a+jMkxNjI\n4PUGyFwa4rq6kRPX3FyoWevP2h99B0FgIX9IS4YZYrjbhxTffB1xloY2gkyyq9pfJcS3hFZ1mDkp\n9FyYwSURZdOXFiUQ9f3DuBpOqpf04L8nXC8M3GzdUwJx5nZ1psrjW36d1a4yBOSefCNQYO7+pwZR\n7rjgorrvh3cHQ3xIaMNureXcU2rH9YUSLftOT3kcYyyLkmTu39tqkHTxGbg8nUmJaafDPt+7NdAS\nTQrStXiP/wIXWlRrG5Ko46jRQZ0OZ1pPb61LoVPlSnTiLvzLG06JXDE93mvaDuK2mDr8GpEATilN\nOUNU1GJJWde097Bnko0cgWY8lvJ1S7gttA8V83iV9jao18XRN5wuQGFOQu8dcCbyOnCLnnQWftFY\nvXhdaokGStCdc3GBfJSL9Ofl9sv4wK8hyQgMTPveOyzdVFhZc7L2F34enT6ZUDhxbXnhxMzXGSDa\niNI81mU3UsW5DtDZW2aKPQAC5IbMVT97FZtD6u2YiZWJGIkz5aC23XFEHgoS78JBYmOhWiM90xVG\nD59G2lbVy1U10i6EY4hYZ/UyJWOtUWinR7xaEGj2HPGkPw4GUgakXwdlGelGrhUGUfJXnSz4TmSL\nnXG3LbvPT7bZPXXks9zrTx+p0OjiQ29bbBF34ZKUlLTb32rdalH/0W1B+CC03ezOoZB2zpIO+o2/\nWlXlpoCZE4J/TWoqzmalVhLJneZIc60BrB4UaQZpjIPLBppP+MhY3EDocCbyB/xQo7ypa2aoq2ai\n8WNbAtuaZxT61LvBmxVAgqorfQOHVTzMYnQiU72l9TcoIfX2s9IYjZl34KvKyy14gpq8NxXvciVI\nYYJjiZjqdk6niLiYvYifPb4/l7iaJcxko5qHa1redE1foVIx3VJqZv8FOx8ehmo+wmdDd9yXCar2\n+67OaG3KUKbodn0zUm2itObEayGQbeKRq+ladI2F85qW966rfr3SJkWfrljV/JSGt9YPL52YKp7O\nqrEJxVYmurhu96ZbOtylgyO5jvWFSsYPB9q7QBMKLCT4o2N39gIK2yS6vrcL11p02rUO79NKocmW\nNFP5KrYxy5+a6FreLipPhWm7aJZ6fNWilzxbvVNjbq9btlqIDxw7bA5bSjfL9ZLI6G38FNaWABQD\nc0Y+YWfwigG6uxKUIIQXonyONYSG8PU9+k7FX2iAy8i5uMmn6vwwp/Zc2IHhPihuetX/kBbHij2h\n27OjZF5LZf3ihcbjHabhbgQnPPaOXbqqqAE/Ept435WQc3g7GUtN+ObCxQVKPiYz8hCr9k3zAR2R\nl+6S2n5sjc7gtdjhcFqnEcEqD5fFRZJ5FpgzMdUDLQ4b8FZXC4Ebrmy8zVpsoz6yX5aqhynydiRU\n+bTS7qSKca0JrVibJuHmlOIOSWkmoqa7wa+55vcRYQP2LMq1rxQbRh5tIv2gWhH8jsET83CN/AI3\nGIDANW2qAPS8XA1JVEmIhuPF7NtKCAr5wYlPPaaZ3QYQoamxBOsqcmg39jtONkQg0B07zlFEL4bs\nsjPUbBNYvucaGWj2skO+N1hBiVPc+XegIDoihwgcTvyGPOqIb2W4FDZDwH4+C1TL4MApEMZw6MqG\nxh6yHeiuoWRCga9NKdMAZ8Cf8TMX64Iq6KnnaArogiSHrZY82x1JIuxS7tesD/vzHH1uSVGLKoxh\njRqTfnFMY71Ze3gpxQ8TqUYCghkeh3nWL1N6STGAL1qHIkOPdW/KQ/w9mREAaxxvIhInwvZoCIl7\n0vWTc/0fdgV/2noqZEA/bVbmF+sA9MYJCGBIff5mc6Q8lo3WICqOz4KbdUQBa6RtEPozcNX2C4Mm\nIMo2Zpgg8fq/YGQ2Mt0H4schOh4mD0acztqKscaNEsM+SL3wSeGKyf2nATW/Yylk5Oz3PmQ//p+Q\n8k2KWf+Kyksk6t/ohdPifLgluEF0mnf2n16G9m+U3A7aeFqoIv3KJY8TBa+muUmve0oRojBfkL/b\nSG+Nk4p7aPtrqusfLUKhAzKVVqZzmquFVYpuZZktond4ZqB6ssjt6qxn7w7G8yK8SRKrxFJmRVC8\nplah/Cf6VlGJSmV4eA3H6DifuBhCX9kGV6Oj4oX96l72p91DYJAivR5to3uI54WbqsrLX/jsB+go\nnQgHILpMSpzbTox21+Y6gY447SZDSyVK3sotIZo7kjbtaBhjSV9zOPZeAd/JnkWqaTaiUAQQaz2n\nBy5EbJR/yMIYjczUTt7Brihod6Fasi9yqXkwjKG7f36keInJ1EirwTYxgHUhwpiVK/AjMbxkccWC\najDPhXRYg9UeCZ8MRtnSaa0d6E5T6N7LFGuC6o1vr4F9cnvrI7xHaYBshuxljcBF9kF6fYF0jhTQ\njo7CzvaoQm+lOwXlLrDi93kblpvtQbpg61K0qkiWpPWfZyGv0xZrkVYnXQE+6IuDMCTo7TbzyoLW\ne9HwxPlseL1FhZItVQLL1eJ89qCDJW5HwGsLkNK2eMZqK6bJKgG8GEKy3l8El5nrOSvdsQIkpt3c\nfIY+yyNilhi0j772t0KcRECfMtFHh5oElkd01TRAm9qfJNXDCedr5xcV5J0Ug11VMe3RUMdWpQ3G\nNw3d4SIDClvqQy+aNNW6ow1LSS7sqxulgMp+dSc2B8gFfZmjyUoUC9SXbN39R3prlM4Y1zcWwVDs\n8To2lGVjdKDSC1xWfNquofQpg0Xtwu6J9tWfTDxCLz1/FhtYlWm89uzVSBSMsbUt7rnY4v5Py4i6\nJRu8vvM8ZpGAeNAQxkzp7x0KoZqhDID59ueLhctOScefVUzy77whcY9QlJe5lTpS88tC0hNh73aW\nRN0XhEt5BYW029l+i9Zt94MSmc12lmp2Vl5MkpQwnCMD4bjUHrFnKqUosO5ntNiNiiEdE/y1xftJ\nTB56mZNNJ7ygzHH9TN8cGUZ0o1m0T4s9SdEihRgzXt2iGHUPBDZp0IW7xvz6cP/2MnfioLAiCoJ8\nleTRTpaUn5pwaZtqzWfwjvvOo176HOKH+YIq0+LJLNVt/m33uSUjC7OkPK2uV2AlxFmkdYL/YoEp\nyMaFArAfa+aWFQJCNkz59xNgZFlJtBYe3ABoIn1Ulx1QgNQtUXMc5rnB4I8QnFrijLy3nxJMIP3z\nhX6ZSdN2w+MW8GHxJPPOrIOSe8KlGN6bgsuyZienpF8DcsNvXO/JxkhXlnB55kgXeCHH3WjkQ2HB\nlpKfYA+SPILfI/6927KRcH26F32jO/tfWiC7O4iWBAJMcy636j0UcCHsEGu02b5lP38PgNtg2SXb\nfEIvOyYEb1I0xfKpB3rTWDX17UDRpPYehCchTO9etz4qQfjhE/E7NuzIIiuN0RyRt2ZSsWVemn7A\n+GBAWClqCkg4EB/6hQO1KKQP/mQSKVcRcCG7EkgIhR7Ugxv6GLUEAnGPnlLJwmS3JY1l0RvaE4GS\ntzMRTiyqXlAziqZgM6KOrvcdEm9qEXd86CVMWuhNQonRiuUElRVyTpN6toG4qM0E9Oq84uSc3h1o\ntHm3qAppfT0d3y1eV9yDl0vGxYK+ynSaCO52R6eIbuqlbpzcrR1IBOxT1hYNev+aaqhS79C+R19z\neehBoGfCSJ/UgiN+XFEz1YU/VuXnZwqS/Xr0NEtIETvngyQMm080TPkKDp+ei8sviyO13hmzdHNb\nkfozpqCA/OHLt7o/HSHtJQTzgonLIkmcwMdQNPSnXhnaaO+1XChY9kBghhJde+n3ra37/CbmhyaH\nrKsT3QrQzN8xt/Ir6Y5wZnJIPNQsHNHuE9TJGKTM76MvWb+OzafU8szA3h7WL3Zz+0X3mKU+X33F\nDpyYD6AhYWWNu12r/xs8hgG4D7Su4S0LzHZ72RJG803DXZgNz9fn5Sv/fvq4ucMnxttm270KOsd2\nRBNr1vStuE1YZ5V5/hoDkkCyBB+6LPW0F7LpBjUNw8zy81Z4EG5kptRGyo7a2yK12KEBzjP5qRqn\nEB2OpAL6BNoLaOOHgWk9IlIG3pLX8O/kpsm9BQ6vu82UX7zRW9z+ydFe/FjnkpBgYQBWOa6wIfHA\ng4gryNybRYnaAluE257lK2MY9Ir37iHNfz1SF7YaP9ZbiyEMfGDaw6WZ0GbCVnXq2ceXUjt+z4Lk\n81u3CMUIxTb4JvIvTip32etIza9tiPrRwfK6yBQMmHSHLgIpGxorJyRJaM6x5SCDaeGO8s4x4F1v\nN6Dn4b2iEVTdLFMWoaVvPU5sensEzg7RKWzuMJVTZpoWTBZstMg/Z0sPVuQGsNIJeNU1O9+yiKFJ\n9Db0IYLZQxXGsug6lyG7bUDrmPwcePWl+zwOUevdTCixoXJF+O/5i0Ce9i4vfF52Cx6y8z2UFdO8\nbl+6rgf/y6lSadcs0Cq46qx7MS6RDFRuZLdypZ5Uzmm4jaiSW458zGfRrS9A63MBhpn8apBm2w8R\n6jA5rlSfUNrnffOn3XCus72Hai6Kpgel5eXUYXJMlfqNss/htwwpjLT6U1xItNCEZTFJYUn2qXis\naiLn/kYEyH53sp/ZOT66hcpRSy+iZJaS08s5kD2MZ2qwdFKCHB318ajaGzXqv11r7JPqah8IB4bJ\nMc4bcYbZJ+21H27eDn33QUN79N1ql8hJO5pZXdyrHOpq3CYcze6ZSItSDoS50oVKAF++D3WhaPx5\nDQ2XsudG/w9HLjNVJ6SPKxsj5qgjR74QtfXzd4TxtLrTi4L5WL5N0tAZytmuGUGlDDgJU1Orp4qz\n800lKqe5s/wjJpXMbI8/wxZCW+tKcZvF2wyGo9wx2YaGPu8mxdIpwk4SIMsQ/QfV3YGiG/WbbJfO\nmnSjeWIc9t8PTPLHLbhWkO72CGE7dOBhjgGqzOy0cqHfdZpSagaRupX+DI76hOoprTXYPNqsulM7\nir1c9LKYRDP/JDzFTnlFt65wK9KeFdFRHzIGs3BaukDtiu/zKlDekFHMRcuyejvIQkR9/U6K7l8X\ns/LNkYqrDAlHfKwMfQjvNh+ejNnqK5TmYM80cJG768WyovnPFP5Cl7YU8f8MQ2ouHnV7ItSV1urn\nUxdrmWLDVWj+wL6L+gbe5lkgASMsFmx4nypFFwyIr/yPDfU8i37jz0MCvfS8K7BC14S1f8Pa2eI+\ngGcfHyxnX5RpvNeCeeLjfE70gPG/K1zkK2UR6kKV4z7z/Z0d14rZpRGEr/KqROFPQ5TRC57SYJhI\nuazYecLNenQHvA/z1dptU5r1KyssNvXPH2UZyzy38ivVUbSTfn/6NPRazj9AlN1sVmUECFKDLWj6\nBAWUYDTVoC7RChaydZmisQxv8WmVD02Q8GREFa1VHMW+ZriBitz4JkYi9HecqS+oRw/yUJe/atuu\n78GvakNdKYLBocX48uyeRxGrxSkIjZnwx5gWrpfU7nIdUq3GKHj5Y/5iNgGVvA1kL08u0je62HA2\nsddIVB1iPuuQ6mZdpaZnwe5no+QzxCg48dYeqyHc6LTDfqprpGhIP99xXKxAmHpirodBvTVHVi6C\n1wjhBD6PMVRSwZiMlyEBg18ic+HzhrDyi/HRsVMVTJE4KV/7q023xyIwEFB32vKEPxref0UPBkjY\nYSnRBl7627vTOvoWobn4HarVheb7YT/msEcDExT/wskrt0SSaqeRWu8n3ONxUZk6PGV87ibgGb3v\nwyWfO2gjBuiFnC0wWgKladTM/4roOnqT8EPEJH5agh7ivp1LYiSd5XO3Tm1HSS7qlSaIXjkQLnp9\nn98HmTlRZZwjhxz7axpBq/YtukfuMioVEH1IJAGdOsU0sKzU41KfdNtp0aR3vHto7TG7CBrKUiYk\nuWm7e5Ml0l54J5+/F5qS9TSJUooIlX8+uCUZDGISEp11IBnt0RfjkEV0m4oB/bF4Y3SgsdbzSpxx\nXPTd084+pFAtszvQ/RYkPcEKTlN0gbxd0Mf93AYLdZNQdZe/c5O8cg9mvyd43kAQRSFt5WkRgdpv\nH3A+cfyop7c7sQUN3eeT/2MGoxh6ax0ZYGCR1O/pVbsI2Xa0V0Lqs13fLIKFoWbA/Evb8whF/XOA\nrfe3VXqc3++RIlGlPCwnPNdKV/9U87p7j0JmnHILXLWZL02P2w7w5ZRJme8S57kXqnGoAXK1bpH1\nlWAadxXnkTvk09ilNl/ZWPM1Zd9B15wa02H3jIpfqFAexxmt1spS7lo2LzX52nhCXiteotDYYSZV\nIutUQoE6OM8lsd6jEPa35rfb1/Xw6gC4WIxHvgm181YDFAKq08sZFzlAkyx+CMhfEDgpH2XaJtwX\nOrPr2gJ3Q5RoS8KrTM+N51HUKkSi7JkxXBWqCC4YwfjBzyY4nCudq9pPhCDfH6tIMdTxCVYHYMOx\n7QRqpKznUkxUdXpcEVCtHxa1T4fCDnIWlRb/Aai0ac++q5WQFWZaNiyJ5KKXVjLNUqyvt9BpO/h5\nmyD2Bc4/cg9VpHDhM4aj3v9VxjVlLnRvXutRhDmwNLYL5ZL7AqVhmsFUhbgqbUNQlCIDTiO787Ic\nce2Od9yVt0W4goqmD++M8OTDfeGTcwnBmD+PctrI5pn8MrzoSnqCJjIVVfowIlpvG4SCLH+lUPmU\nUZHod3YVudCoqoDVjDfyOUKUQiY2REjgF3scgOa1SeXvyuW09KXOpzu0rc6XXPlP6eUmpJoZU8wD\n9DPYuycGuBb5KRaawr+S2VcbEmutFxO80YfP0nx+sNdK0huDNjD3HO1tWhYhv+h/NHYmvKx9qU2G\n3D04QfNr8ABHysRqHHqpYRiqN8ylqcKJgp+Tb/LQ/jEx1yUbipCT+XtVmjJ6bT+zD+1IVi9R49P1\nWPW+wO74fYmjfIsKi3ADB0x4244lhHHHd7GDH4JGbK5ptBabD7ey6UEIol+EChtA3jA7cOFXgh4P\n4RG/BxRy5g5dV07MH+65kr7hpV2k/7IEjaPocEv4dTJCT2YF76wxBj2mg9qeXucKhrKcADFSbm6H\n2wbV3p3HlY6rZopDOdioB8WyqckdNL2dMfIp/VZ77W8rQb+FifG54gXYS7iFK/XfYNW3l/xfbqoa\neDwrnuI6aqoOvBGU25IRznGtAcPLAn4k55A7nH5s/F5RgUc/UMrhESnZJKdperEmogAfAI5v0/ol\nNhCzbyEdvgp9IG8yhiUul7noNViTvqH2eI8rKoOri0DckgguVJyhLUw6LwV/ytHZtFe3UW+KHBMt\nNUNLoGLdymt4zvWvJhdEckURyYgtCGUu8NuTBYKFKfpe6KY/Jw+QbNHkPnvUxO/F/sasqKLjwe9l\ngS0an0hqTkKxwqHyCFtoSc+yaQormAl9svTBD57aSpamyeIpDeLHGTha6oBNgycpjtfyvkQz+08V\nz9+IYkOgO7dTjSQnveCn8hKQkM/LHhPttWZ0hiIOQSEeZXwi0zFPwNKt1OBFLLv4xV5p457A5hkF\n4hsiqVHVHyE5HtrY8Sf9KyJLsvN/zuc55CXXH94WmB1ebu84gpio+bfxqLKUDJXpVmSRqv1lMDZy\nqXVE6EIMTVwdVqJk4raq667ORCP7tgHOykaoletORedpIf4g9HIzN/DdYDYB07PXj9F12leGCg75\ne3WrYqEjz/GU5WSLHpqUH3xw4tYYVVEYszKMQ0nJZ3lrRN6qEFSPl88DEVbY2xiYhCTsjEtGIRCm\nc2P0xvqitB4ytselWy7eHPAX6mqHhMdgcoFL+yuv7r5akmrPSSgrK4qZt0660SoSkb7abuV7NRSk\nDZB1UwdgMdknUFqExSzw0scKDLKxCH7S4x57rAdFMsRNQcCNoF4i1TQu+URHD8hCOXjkSM53EdKa\nsdCnbssTxMUbup+CPXKHq2PlROkamkXlNQ1P+GT5nECY6xVURV+StIG8rR+sP/eYNeOxZOvJxzd8\nsVj6hANmu5Px2BjEQ6rCCeKcws6mxLkiAeH+XVD9x9szKDuVHpnI6ZIFXtAfGUKqJCkgQs8JpRqD\n/Cxp0j8M0bsds+fzK7GnmpUOYiZCNhG9Tce0nGOHXgxBXrcBybLu/0r/ttbls4CdYid8AC1qLiiK\nuk7WDWa0xfRpXxe5yW1hH7F+NCz6WXOwumIo2thv3FkaPFwsuHBV8n2oOZetymIj9S6FSWwLVeqr\n/YclruEwiUOYMrGqKehLBko4myw2FECgmCOVmjTwsRtPzxuD4Z1g4t5PW/aOkt2P4D41nvIly0zp\n3Rg8JvDz2TT+O8k4CDuM2mprJJDENRt8TJekXM26mRGUrOrbKe+Bo4myaIKJdRmWa/1hVTuhddcL\nzVpTYbHbHgZW+8DDfVQAelvENpElw9j7K/sstOtWrxdkxMrPsEf5LuOnhFFreTkiHxUMGPPQJLhZ\nMuDvwior/kCW+1crpr6VeG2XqzXzigmebHHU9YE+Prceqh//WHZq+VvfzJx/S3lY64MgiDffixtW\nfzEMPJnEk6oCX1srksYPGwhht+GZxBsTTX/UlWgy9V2zOsqmPGGSngQO52kdJJ1nd8r/i7BkjGjw\n/2JjkkK2QTkbcA5hOI+2uIPEaXN/H6e0wHGFRqFtKLp8OPzWdnBqYqBpBZ4nk9MwMicTIymbZh4z\nhML3FuYANcVrE4fLZNArRba3pc9exOtZwHpO5woYDmA69mTKggP0RmKdp9L5IXE/4Rgmmed4t2lz\ngudtAXQV7zKGzj5Wm1xUGZ/7q5gDtKi7zNWfN9SHvR8ufTiuV1BLXpPE3Tfe62OBAfYukVoLyJ/D\nryVcPT/9/uhQQQRnzsGbgcmtH7xIUWzfZx30I99hRUkC1yMcY2T04ieY/LvCM53jexNi5C6rPUt1\nMkiQoe0gWwGHhX1GruEE3cUFPFGwzE2KDMpAMVI8yLvPh2h4GzIMKJYe7OwN8am0pfFXTnXpS9De\npWhZxjS25TRQxRu/WAGQ3MuiSdBHuNtaiiwIFSlppxuSz6yYm9i3jeTB2lFyVZwPtcSQHFHKbt5b\nUtuaMtheWcaaP+lAcZ+LoPvtgv4i6RXFroetjfrwwZNI0YdYxg1ZedepiNCjeHk3kLeEUudjKoKD\n33Fi8MVCPcQHaS/rK0TLszsOtPRxibf68unzoEzKdume9UFV3l+vfr00QzzBsbAccmQO8oF2kydA\nnJgY8IhZW3C+0X9IpgWZqPKGcfZF1G9ZZDXb04gGdfYHKjjo7lAOiQpNa/UxcvtIWmXf9TK3jabR\n7kPXeIAtKt5lp6hJPLNnt9YEANDHFRbCb7ku0Op54IGwEawGalbytktviBTJ0OA5v6sqYbY2Sy+y\nWkEr0NhLi9JNNDFLxKq/tYGKzeSD5sP15Wn3QF9D7Fveka8Ah2GH500x7pg+Q7u4cdppdJSttx05\nzhkFXb6S3aI0TIzqanu0mgKSf6dkoSBeYVZPbOrQJp7Q5lCkZe89to0sixPA24mc/3cOuZ14XmtH\nt0tLcDNwa9XWeJP8429B5zWHBJM+/nJMKP4XhKfOYhCMF6Mf2J0kfjxaoGnSzHbWoXC/2anGXkDK\ncVku2HM3AlKRayqGwpUoKtlLG1g2ktZlrezoBPBdS9sEF/nO6SoxNmXzRSDqYFzV8GeoCqqcYRkX\n1kgpBGS4w0ebw0RYpGe9E9jUnOGyumMCTzV0Q9sjUmk1MBI7bdLgXohllHANKU7EaAHQexd6nWLj\nDHRplHc3BjVQ0nRa4z8f6GtThel7Q/EbupHj0DNhEpZV6vun1wP1TwTfsL+90nyFyuDBM7oW8jv2\nRi6tJ5EwOQ/VFipySxDWdQT5ziTfF41065S4YXMUOIBVyp4njrHap8PJFgLc9a1/GXZs7y2MRN/3\nkL0YTsZwHM32rfQVw/Sm/zxkZeFXZwdZPnwBzheUAIZ5jIKzgFZlQDRCabQ9NzqnOxBJQTAICQtD\nEgDdXge3M9tO9YaTD/6Yi9GbTjZ9TKZrd4LIPr2nRl6vUHuC3lHL13htl5urcscVcLLwptyA7FKn\nxKtQamdFBPXzoXYLd+tsluIZlBmKhLbqbK8lOXRlcVo72JZiiI/sp8ozc+tlejlADhsDkhmpqR9X\n9hE3JadnLbjgCGNs2nMjNLy0Wol6gnXoqFxQNoDyiyxMC4jDi7Nb/nF41GGjYkrS91ya/RGnH6SF\nReGiGdlbhw/EzuhP53AqDqfPZVijBQojmzKv4C1ZtoUgAeduDseZSvB/cTq4CiWD7FlS9O7GF+rm\nnFDHAoOUzudJFa2XYn6h00CNjp/Bz5QB7N5RgwdJelE90MBjISrH7nwyGxmgCfGWqvFt03Mx9M/V\nLzX6OiA1TKyq+wLT2fEm9/STEtddPXiwodkjsz2FYcOHUdErJB7hxb3BnMeGn66cjNs2LhO3jqSn\nuPa88QceFdRZdP5UKcwqAgH/I7n8xqHo7iZDqHagKJ0O10gHV3LbKCbFKhwovuTeu9qbWg/VFKB9\n42yL0A1l9ZtWmtugWjHsvlLkUImT72eU73pEQjY9Ia4SCv/bYBi16Un2mGZ7wIsBRTU6KXS+zg5M\nKo7Ig+BErsepLfQrpa17BLe8yT3Wtyi1+1drw7wn0F75m1N9V1iC3ZIBRDpvjgVgL8PDvwrrGJE/\nokEpizQ2JEVuGlM2hFaZkCewE+mUFm40BTGUowvBsb4WefSyUanAOd+7+lF0+yLolEZKtY/7Xdj+\nBr4dezJpTtCjF//+cYqab1qGRSzMHhNKo+euydyUq3fednuJpF7DWgoRn+aCCxRje0tkVK4oMV5p\n8ZeIPQmWM/OFDz4tKMU2KvR4wL6Wg3zMZW07oNIAaDH20FDGgz+ZOhhHgBtla+4MeH+esVsdrYCo\nB8aNTbEITqp6lvfOQ5ou8UR31QKAE6Z94PvfRlZfmGl/ZPibtSJf/sUuUbaHOGvTlfLZylJJ2E/Y\n3YjFTIgl7qK8+h8bS3Iq6K2iH56CXrndYChN7yotMqxKQNyesG8BZ20yoI2wri5oOov96L7U+Cxl\nDI4p5MNeOUbzlEBP+Rvo4mxZHF2Tv7QDZ6cK6Lbx7Hv39T6QVFO0rU4h82F/LtMs81q/jPqWpcDp\nTzMznmV4zWEfm3DUHW2kwiUJHxiyQdx3C3/ICZw8OfUVMXkDVt/HTwjxukbu9082pdGrW8cA10v8\n1YUyjMmvs8JSiw2TzL9/ejW03aK/51P+qvsPlswkZvXGmqqVtRypMZCm2XOwPIEMrcO+IUrdlvUu\n7yJi+1AaViRrgODzC6jXvIyvf991fYsvkfWz2eV6jvDTqOMTFZcW2YC8ybCWDOQYNvze/u5mWKJM\nbCJAqxqKM+C2f4Dvqe+TKDgZejmL0AGMPmUnsDHa2h/Ylyut30W8Niq3F8nla+Et6KkuRMN2svHx\nOjJzil1F7Gi4dHKNinFHrIxM4S18aC54ucVbK5LUV5WuALad7j25AkqJhboL2WfSYIFNsT8yTGtz\ne5YGbE9Ea9GYEKCznqCY/q4jIRCx7ae4TiKAkTnc4CkMCD/SP/luu8a20P+7DeNlIC1Hyq/oJtr3\nOL9w/l0RGLB3aGTfI/A+oz9MTj2TEBTc37D/g3ZFRx1nAn55Y2TVRpywJkGtkrA4UEc+688TiyL0\n6r/5h9fNRNguEvc/Q06IOFhHmL+Sg5p6fCKXuzbhiqCJ1WzYsE+DSclo4+rVDkUBl1JYPFIU877I\nW33uzplvroc9G3u4zmfKavl+SpPp3uTmVeDYs6fB9T3Mc/YdNNhHh5XDb/61DGXuyNLlTIOqYtxb\nODaxMHr8D70NLcF4zbtRzOFq9q3EL9VPIYhyvpYnfuJoxf/BDNPy64sAeKsWFzPQQWxSid0cnZsN\nEr829MEItSZdz5VLS4hhsZp48C7UR3AcoHL6hngM8/4scwXeDKlhPMevqzNYNm1eaqDgoYBCSl3/\n/J3nwzxPjj1C5pxQN4P31uxa9Ejr0S+ITd6D5KOj4dMdX0K6g5ip08Uo6rMtCzlXB6xEpI4YCgYJ\nWgWfthT+oJwhILH3FQI9toz/4ILxU9NBMjL8ZC5jaLE67yg7rJAkaGtANFKyUo3aYXg6lviye+mH\n/KygnPUsKn2v3NIzNQpa4UJbBdp/5BxxWeimbuB7AZ4JgKoZrsezvrleAAzv0gvKs9f/sWHIn6Uh\nt1tQqpy97B0b5xECu4U2QBA9whutZS1CVsMnl2RFVagtKC+Quqca8b0+dOMbXAmI8EkdlQstQvO3\nIv18kL0cGMWLzOiaOlmErFlAyUKIdDJ+rkgqZI6sdZIh47jSZjWk62oaWAc9izjW/Yuzo+f7rfOM\n9WMKTp053BmCEv/7Fcqk9IOLO6/vDCLBUZ8nWd88EJ0iazFKJZ3q5tTzC+G5UGWk95LA96tLvnx1\n1TaHAwgsHEY7BSmgdz7WTi1q00HGFY7DStU4Mo/VzBZhEydId36ibTyrl1fI40ivOw8jMNrjpo+F\n5Gd0Ng9WQR4niI9zoCHvpA/7a0LCu8ZAuymbcJ6bqA8DDSM4ey/5ofB9tJ5TICpgZrCB968Z0kCb\nSsQdOewkMJIcRYOqII4TaLyopakcOuc+vOPAK9MEUhWN6cdmO5PugrM1W+eZn1kQ4AOTDhBF+13e\nrQalaDnId6Q3kAjwazHIzNqrZ/u8Q4/fIQMSwbed4cTaHnw4gLbc4ZuO/n97yJyHujSR2g5pAlgi\nV+1neaz4fBYw0LC4rAUX0oOLvI8gX7OgW456rLsHEmhhPwF4vZuy2cFZgvK12SM65TQUe3+pNS/e\nCcqXrvpUIlOUAmS5z0nhc3/HczYxielEHomU/LlAXzJSz1yBoa8fqBZj5iu0o5WUf/cCtd8dwkz0\n/nuQ+lxvm50UqL18Hq5y+Nq/DpO2mZGPn8sKJYAas8Cb2cEOpughW9pFDcNLsT6O3Wl6kM1BoGeE\nIFeJBOP5GQHTQf8+RvZ58qoAOlIYjCLfqnM20sxtWrXIXxeO8p/22/6surz1S3BhavkV3CQUt0dM\ndhAXuLyFgfokdfeuMZV+Q8UgFgnf/EIlT7bPhkCu5ymeuB2JoLot5XJvm26pMY75osCPteDApcdj\nXZmMqu7A4IrXLKnjLCz9GZuC6y2QdZ6mxfTRXAfgs8957aWDsVbKeyF7R878tXnBd0V0kE9u8Drz\ndicqHnr0bHm1tTV8f4Z1ky3BFlFLIEZIRbDvEA+iOSqcvjsV4LRLC9ZtGaZ67WFMiAU5Pa2l+c5I\nKgTiTODvEM0FWTSTHhCHUc0au43GLIl/TnGEqnSg4t4TzeQp3xktGVMd3PrfEA09sJf7lxvZUg6T\nbpZ2z651I0S7oDLS5DWn4K5OBPNLtY1ri94rMT+qhTrpSBQ7o2Oqpy8UsD07OeBy0poDIz+BgV5W\nl2IjM0VdOnJN33bQzYZ1zBMm9H50kaP3P7TMOzo8+aLga3W/RdCxX5adYqC4evPUbc92c2kdXHs5\n2bi7Y7q3Ynw5p2lFBkNjy9rWflj1H6qH7DJaLtAf2u81sosscQ9wMzzRpaDoefA0TGlfeAdOqTeM\nqXClsjuZuYeibmz+V95WUUAuPCX52AG3yskhpRQ8laGNeafzAgH4VIAm0eCP6tGHPs2/V//TzBCX\n3L54yRuvv7s5n+CobZaSfAk4DevlOdxVZvryLl0mevr+lLGtv9PZt/5WhYOapTpt2KoeY9wPX3jL\n0EJw+/rypRgqTMX0GLMxeKvCYzQDxLHRSdCssTGj2V98h7BBebTGJz/GJ3kjOiGXOlJ/h4YirrfM\nPCo5e7eiYqPS/gOvSuUVWUx2ikbUq3Qc+20SEidSn03sdEdtTpCubMaGaaQ7fHG9iTshX50QDCwP\n4O7eIHjNr7qDyT00uPZADk6C+hyAsDYT0IwVYC/AUng/y6oV3DxoouPZBy35tv9dBU7bgoXfcJCq\n50SZHpch248F9GA5HMhU11F11+tFDKPAYDhubjb0azfoqEnVeQlM5IJ/ke1XBIDpJoD9XhiG3bUJ\nyRpWQczGo3nYQUm5QrP4OCoGryvqfkTP4MejfAc06ca7gvW7cAfzrGvwgzM4P0CqirU9nIVz7g10\nZDttalrppETemJYPf5vOSyGz8ht5OGQ9rOsnqKfkQe7t6LxShy03dHZ6lF7KdJ0wRuyrJA6FPWVt\niq+ARhfAE4xlcUulyefFMm8mQhX+Yip/mXqHAlU3wv2Pmiz0jg8+kJJwOwYg4Ovx+RidmuHf4J69\n3zduhFDTkBzfQbRRBaclp1OU2KNxuwHikwojDZtWE0wqYfVSlmFMU9RPkVyOI4ZtwAVkAZcqdoM+\ng7nowegOxC+sNDyaM0Mr0kSNemQGMEkHMVWWqcy3PddKD/a1E9R8Z+37sOV14Ne2WNoyXaJzIYrq\niCWLkMugc6KZlE79PDw//BZvC4/ob9UI5K2I/sF1yRpzmj7+R0IVVEUYlDMmYZVqb0duUfSs9wnr\n9k/R/rBrTz7Sjn5wVa+IEnuTJJeftqMmr6PYW3/EK3p4TXXgRuGmOzb+u9B1nz12rRi9hlrDNvmK\nPfocXbZlObH1dhjsyX/9+am8QVG/mcYnjxqTzJsjvGY2zfb5E7TxuCYXxUM30+iVMEZc4beh2zHH\n27ZUCSKIrsqdflZEAlBMAkfo6kYC958VpGTfzAHb/V+z37DSoIVzkUMyk4S1pOGL63Kj2e/RB0Gk\nA7s1qnuTIvuEpe9/q1PRnugMDBrxFM5DMNTjyDlXuqIRGdlr6A0D7uxAMLTgSWUdgLVPIAHbzNBU\nUGSOKfwmfbSqmx6MRK3Q74p/r3SP+Jr6/boRGjCYM5kmqOw5aEM79Z1VWmczpP2/nAXOIN4kiaTM\nMIPynRspYSHSt/FawrF1UHOCR9yeKqMd41qrwaaxINJV7hmr8MtcToBXT2cO4raEfZbneAT/5F5c\nWSl7h+lNyQknOfukdDFDnoYMpjPvEmJs/D8OpoAmtNsO8oGnME9US0IPRi4Lb0vWvPK3ciV5UkFu\nP4YKURtazI+iGxo3u9zV/b8vgVb1nZ+sM4NVDKD5FFfuPK8Pg39qo2Nd3+kLH880tao8BzuqKeRJ\nnQyDxtgBt8Jc+Ywzp8EhRA/YYSYPuHIRcz7MAoRs8e258dlYVSPsN4ZHIYrwaWAmhjRA11D1uzTl\nt+ztDCpCRXGnEfIz3U+viMHYT2qWaTzw9odSSSyHdQ2kMaB8LV/+m9tvENucLspWn9ZiWj6a0Sfm\naomdhlGKDTHImftazui7HdM9fBbHqXwuTMeeseULNq1AoyL86OIb4Scwz718PwBPd2k6p9Uw/d+S\nNmDyXm6MLW5gz/GenNVI821fxa2JLheMP9R8Y+4vL7rXR7u4CzPPVE+ZLF3qeWRvUjy/YvIV9vUb\nfoUAs45BOCfgvyPbdbF00eBwPLbs1k/BI7c3OmIWiY9DnrZACQQDKUieEmKfuQNaSl/WgymSYidA\nDMWuKw2RNrW+k8LKN0clrN5mEgAD5z1fw5WzYHW2Ku0CO+AS0qUmTV3ORkasOyDb8YDoG9JTTTRO\nHB7V7xCZkoKICVYxdyhX3CzU1PUx+r1QZJRX5YDjwLBY4QDFvRJjpjilzVH3oOHIR1SFP/2eBnk2\nl+ZGSeRyS8OlaPGNBLUCS7wYW4a3ifZQmwj/biT2rq0qUL77yABC+8pQS4c+lY5M6o0bZTtZFiTY\nhq9oQhx0Tdf29U1hj+hBqTBhwACvSaIaW7dL7bPQHCYWvQhy1eHvOlh6Jjt0ZJmV7qae537dcEQl\nmj4OW5J1Dy1tTG6N4NhUtSmxZaayyOtdi/FK61nO4f9OuloznpneNkw96Y7Ic43V3Z6qvX7nwb6h\nJSyiphPmD2oAifipG67qAlBZsJCbEJTEku8PrBf+0twy/GQfXjTUCa+QPt8NWho4VaJ2OInPI+x/\no2nOcaxiIT0d83EtadswNUwmrbNsREEoC0oXsY4bBodH3X3U1MO9xweNrxbFunCK2NrdFTXSpCQM\nMV1NEq9zFE4E7FuDqpm8jHb27QqX9FRYq9RQSb95xYzzshQ4Eup8jaXwu+H4DtaXTt5D1+Hv2Dyc\nO5S6GmX8MMkxWksZI19lZN4Yb36HE+mKY308CRgTRU5ju40WEgvGTDGpwfw00nGN/l82nL3zJnmp\nCkCYIfMwvy0ZNJvkDwtrgTuCKUmucGdiGn+ACD8HEEPudWwZGeIYbHcHpfWHM74a6p4Md5gdSK0i\nPZmrm9i252KELgGpsS4v8ko8T0afOZIkRPrnJwNkVn3qV1tZu6d/B+1UqtsmVKGEcdqkVZyZDB8N\n/KDGLGX6ET/n2d+0W1metjGaxluHVRb25t66FHVqyVBhRJJKG7OlUH8N6wnd5JLL/gQRt9pc9jL6\n5XRkby42gLih7VUyIGAtvMSDGd0BbZQ/DMsq+srpDBX7BgLa8+Y7yJZjqxykBI9pSpwtQof34F0v\nhBdtDYSOU0qRGBzhhxKWWifPl454sRIQQEeF4z6zed8YVYiItT38xLEbRs8kOXpt8Un6VwdJMtxQ\n+Oly+FasTpEhdkqc7GZ1Q+gTtTt2GCwcfFy9aTcxYrxfjNh8DGq5tZqGpF4oC8C1UwBPeDHZkQtW\nQLxXcX6lrou02xKcP7lBfARWu6Vf88hXPgMhgFjW/66BN/2MXv4htjPLeYVAKH8ka3Z9DGfZYbYC\n4eitQaCYqa5XPXbS2Y6qCrHQHlNenDkXsJKZIqMZIV4ZdrIYx/6SN9pqoKFWyYO3XqqMCn6kCPtd\n8wdRCczj4vEV1P5lJekj0Q9k90Bpt8b7uUbbVK+9AIAqFLr78JygOZW6TI62DUMcFwuQbC7wah/0\nppQ7T5ubJ4khiwwVjUYmKMplPaNJEgW4sk9htmvMDYh6hwiQgUCZxOWj3PGaqdjQiEPrv6ff1Pj2\nm+bDcBcouk36g/rNtkmi1S9ogO4ojFqkbP8e4nSuZgOZQVLaOL4snHS3O5QjTIBW2SCOcmMtkoQj\n2VbaVvBLc5TaBL1IcHAvt9r77CxpZpsHRimMS8mWPAUSwhnVwyCpVJRHJ5daFuDBGhI7nukxtUCs\nCLufKWIWkovAuYtF7zk5ZrBAs6hveTzXfFO2p5KJ7LqxlBdDvLF4J+yF0tIsJyA76eKNrIiUEE3p\n3Z5ukGqCKKrdfJjx77sU2rY0YdfiMj11OEi1z0I+7cmMtd0ZgElq0MDaZI6K+S6YtiFYVUeMa9GV\nJPhb3SJlbJnlp17UNexJbCSgeAK3oc9MgnkfBKuwwbuKFkCj/1/21P0ND5tW2mkhOUWoXqCZC/Pu\nNFx24ywoUkfaFYull+mGV1oVsC1T4GAaI7Hnxt4AtkA7uSakCRYKLBvvH7vteuEq1w6pQKGgOE6X\nRxJIYpCidkiHCl6bEpPZYZoSMCo14wZO98dkMrYgcsksce922NUaUzfUxsN5w51/LEKJJWsBUx6/\nOWMTDSJnosDT4nNBnPoAs2UAS4SB511ZcledUfYMM8Dn1ENGJvB57cciVhgyHCg8Pot7mtLmoq+7\nHb16sXEXtyf8Tlb2QyxYWeivAVLyrVDGCrSZad0lJ+4fTFXv14WpRBitOWaFLtxRXXJPFqilHU2P\ny0kb1HM4da1tWDQ04vpFyTHU+gU+H3yMpGOMfEp0knf3RQ6k/cJpgWqChgYAVfNJNjZ7D95jkcHw\nnbu8snIT6VGtyJAdw3TQTgFYJAg0GvhJ8wxfeh5YcjG9X21RA3RzQxenfa93a95RJIDtingF8M5c\n34UJEgg9TiaXxfl6nBBigVhIHEKMqqTly0z7sQx3SqqAYtMmsKaKn+lp7zR8mlJBtPdgF5/2MQgn\nSr7DFQl9aXYAmYFJ8T3f+jdu32smhfL5+H/GOicGnnDqw9AxATl2HJ2pTc5HJfLl7e5HtdLXv4NG\n8NMgh02MPN9WRsRyJHHEAorr/0EcuM7MQKSBxvhE4AfD+MuFaFBZkHPb1sPcL//OY3iV019EEn8o\n/C1f71HScn/FnXbOg1lTpv9FdAdwxd/uFYSAfHZfnHFPgFsD/FrS8usCajh0ZK4FZayoFruZg06R\nafOnhYtAUIkpC3Y/JNumzAvWXP35Q+vdd1RxClV/pRz2TDEtWj6INlNhO0oZgclHUwA/bEQLRxa0\nH2dFIDAseBIyXjI2GnOZfFscSEZZ41BlVq2LW3p9bhf/nkHHo/mq+rPzol3s4Wsuhs3PU2cdiP7D\njt28F7ycQVsAAlVYLtDMrUxki0aFttXnbT1NYG5MGJA2hySBq0fd3iTpk0WbL0EHZH8D6ZxADKvp\np1I9Q2lFpGk5SFDAeaDBzeiw3CIw1CNV1geTxSQchFCSmAXGlou98StW67V67kZ8x087x7X4ZGWo\nt8Kz0hTmEkzcN1djLUQGDQTONX5XZHiiB6OZj1/tXTwIsDzBG5S3wmTaY1SAZAYB8so9CWeCU8Bu\nR+BfXpVUU1sSmeOG+wX6s5dbD73pq58KDkus+lIF4hBqdWe8kLQblueWSMo87wHB1Odh9dWPAF28\nV44vv5CktIrxf78VV8HU++jdL7DyskLJIY2uRBlZKUpJgGWFgH4zSpY1lUgoYkU2CtQR1eBV1fBu\nhf4Z0C9RNjumfrJrcqAK9mmzuLXDEqOfTzhc1tUYM1O6p3XC4FRooA6jpAtIVALaHDsJAOIGMrcS\nbSdjPLeDBM3E8ZnrQ+6YBPwfs/oNJtQVvM2kPvTLruhVr/dAR+Tg0UtjOoVXNsWC1SVeoFksY+HU\nrbWzucW5zVDFeqRh0tfkBqIQ84pl01+6h/aUw+/1HsTvXMRf4s3PpsNyrmsCqx07D1tkazZn+cN3\n3ZAmI2lP2Ld8jeHVIYC6UZNPHmr85dLJ/9ZpZ2YoOaX4lc8p68cfcgpBsu8pF07tkAz3JJ0X4Up8\nyn1gNGGfZQiBiblxejvteY+GKyjG17boy3l1IjMm/RQIzDfAIAmqR8eQPPmViMBI4zHP4h/qnSlL\nhlDfeOIlv32eGDe8sEskFEMKuguJffcXDOOCD9BUB3y3msb9V3+qHqwcCXr3GUayu9FwughaB+KT\nwO7cAwN4x3z73R41/HpycrDOROoLkKSYj2E1+7IjEexulHq5ZIcr9EIbRrJWgQHiwnmmVzzMcHpm\nE6Q+0Utam6z4JVay76OxGcxDjjO09sAUhNXRNaszJrTM7+c6j4+rP0vWgIbT0dr0CTOdMfttrFr0\n20tjo/sB9qbl8EEctYiMAqCs0YFbTFx9ek7Idh9qAjE5RYI/UnX3y+eZvYICg5BAiu2tu1lKhVfa\nsr/bi8pENcWjf4M12NM1d1c9WDxEqkUeSJ7PybVTAfpc8AJJWrEiCkJdyyMPG16+FSx0py8xFB6F\njjR7KvpL4H3BFIQsSHt4p6GgFXWH5Q7LrMaYivLAwmTcHFRitEJAjChD60ACb8CMAkMK8nbs7TA8\n+H7jOTrTpnFlguSGtuFDWUL1NM6GhFd5xl8nJrh1qUAcvtDNzEPzy9j1EZKa4ktZQMu6UbzfECQL\nZ6qaGkiV2CfAvSaVXT8QeiY2N1bRklvVgStAApxczCbTEnSGkvA9paVHSNYh2SBUBRn4Svt8hVx1\ndG46NX6EbAaiVgDyY6JFrqiEg0ViS4GzJpoyhpS56wH3206pVH1DJbhKGKJhc7K38Py3DT9rEQvo\nikSbZSqBUY5GRR0CLO1W57xA8LlkJ5LzcSiYaPQ17gvCLqvZJ8RkHorlstAFf4Cz6VUB9F5GqiQJ\nHpIfQsOEnvavOZJS13PaXORKXWA3rXUWpn8vduAAhcxilrbj4HwzqHojnCXB3A7dkANrJc3XQLY5\n1KybMjvP9FgmVk0Ra7iC2UCKRL7szFIlPtRfeh5sG61tH+bhGsENiK5xeBOPWowLdXkEkrLGeYhe\npkMb3L1AmPMBmZDTLbX76qf5vLzync9FhRLuwsRYjSeAJuPzuI5ZHHwH2JRYT5/TBlqOXRGDGD6D\ni3Yn7wtF4pkWJj/CKRFPLhFYk/2CCHhoD4QeY4pjfnNsXrYUJgquXuYWcCfdBfxtSbErNsUv7wBC\nrVDe1vrNmTxNaa6K5tL22hM9z8FDr0mdaXgqxwmxaYtjM8dmIXDbeQ24hqlI+WCnI5dgSBH81ZLD\nUkCfqpWE0nodFOIxRfF0Wd/mVadCpB+CL169xS63+ZoQMG+Nd0VYewTZFPteQomUciylUXkAxPD/\ntt+wZCBr6RVpBSyOv/jdiNMsW1HKFpAsysnWDcitpdWbL4xL8sJx2+s1BKvNxtO+f0hbnvvQl5Tu\nDj402LXBC9namvN2djuSJcz6Z3cU8uQ/1aPotLcTgLa8u2TDR53NB/OteMuANFMac7dvC3gkeQF4\n1mah6cTl7XjQx4jBE2gBH+kqUH+pF3rqp6XN/uKUXY58UyU1Ht8oAtk79d48QJFhEUxpj8CwZ2HM\n65Z54RhZ2P+ywQ09Qmcy2p8P0fFvRF+d8yOPeNnrkVp89L80k0hUPmNB9lFeFp7TIzQD/9iDG36Y\noVbpwxJRdOyGEhxV//y2qjM5EnuOeU9rW9uX1rTGFk5RuT8tXiM4YRyh4zeLVqmB6KFc8+97gJtT\nr5GAqiadfeZXhiDkISkNcJZilIt/Gcr46rZBbs07phO4KwYpVWt9Yg3WcEU7ApxTfW15m0Pe415M\nBCCd/ufXIwgJxdfM1iQvGVdTrYYswR83zCJ1050TCrqlRU+5mr9Z5J9+Jt9btW6mgBoPPTgTm18x\ndEEOxB60raZQgccHtP3kt+EzMcWTwk4ZogVKTCDonIXCI31Do2vFnlsErk+7aEWz0EmLpuBUOjWK\nUEibg3ijqfirvJU4YVu+dD1Ixwva7VcjslB1D0NcdXTlN2KX10JPN8QC/JoMcHChvJTc+iYu+cyd\nBkKug7PkHcTUs+ddtyq7bUMFkWgb7unIvkHbj0VWg3zYFsRTqZkUN84Ix/U5gWg04yQtb7qCZAD6\n3ASHMy+hHXDHVnWgXW3aFEYC4p1gSdSI2ZD0AZkTm4Yjx4TCg50wPypeabJts4R2HIg978z3Vzcd\n4colTLrkLQ0Lg4o77fjwscd2wSrDtqg6Ux3qmuOFFUrkCpFM/c9xp7hBpfHz+HivKqv6lRthA6Jh\nJJq0Cnf440ElZFnzLEm6SoMtAA/I3gZ/kXPIknpeqncxtMHRufKZFAPcn3YZC/2MbzJkAhO3gJNP\nXYCkrFIja6WpeVjGqtZpRkzYWGyEyDoQ64Ao9OXdp07DtNXwluLgo1yt+v64BAp4o3HmZfReud34\nh+aD3C+ofIc/kqt+nuhKlnXe8D4VpO427Sxbizo2I0JNtpaBv7B/ivdr6xieZ9YiK1b/qJY0yNW9\nSvBJ1z4neq35bfJA2R1qvUDPSxd0Igxma8uDil3ux3YFs1Eo5l33Rhu0r6ZB/iLB3/q6xbmZ3UW2\nUke0KBIQCZvw9Yh1OTNuUbITxZDfgPOatoVT14i0D2FYTBEaw7PiatIyZiLTGNxePtoaLTBvKlNN\nNWsrF0fZZNrBOm4DylQG0+77yMmLR94ETecWdOz3tv3j3MtBGwUz/76gpHHgL13Wcdg5xEIAKSqa\n/iFlJBR4SEPvFJpBKmSi2HtfBXzCHWgX1cbR0SkMAMAJsnZrnbIP6ZPJteIMbxYH3rf0Gnv3114R\nBjwiFzBcGWt7BKvCzlxzgL/x7wZQTvxEqdBi1zcCM6nq+TcR0e3/GyFwAWI+JSMFS6D7vbhCzYI2\n/4DqhUzTKLAs2o9rryNfdlVrI2w8tMDC98XwRHyIeV7Mr0Pxd9mylYr02N/OQy3ZAVrN2IV5j5KV\nyn+jorU1epq0dwYIaQTOgBez11pGUncrXOQs8VgGF14ZTjlw9er9udqAnmiYMKRt77diRnNUTjS1\nvKhpiiJJcW29v4eaWYrnjh9DS+XytmKNrZGGCGXmzBm4mC38RzTVoPGGCvtwsesOeC33rWJxbMlC\n2W0yjfnRm8yciiENtHKx1DI4eDfwztX2201WBM2dEnx7ZT2xW/3f9PSsNas/eKltiBzcWecaLXzP\nbCpWLB0Opy6pPnAH0CT0Z1umk7j5bkTSDesSa0glhuY73cnj6b/Kob9diXblNMGOGYtC7yO/pOcR\nFqWCYMo8aJMT1ePwoeKHnW2zlTS/0DXwslpMHPgzsNkvJyb1/q8PnkQN/XHFJYQagHChLqiflC4W\nFr0TdJ8/bPksGGRSPgoo4n3LYg80bCF7yWMxONZKxpxXBPFBGUDbUblvBZ8CecSHwguwMRIWkAi/\nl8wGVJRcTm8ggtZnfIYH/XedpofA/YUIa5jjjKN99iF/R5Qb1gfKkgxAQ8Xl6079eGgOvk33tPDc\nMR0WGJoVcaviubEvAJz5LZm+ywCehu+4KmBXtgyA1xhbHqh2jY4EySgqkArKBcmCW8mByX3Lkqb+\nqvBAex2bgXXYXGfG+7v2Ci+WAGc8M831AGuHyQaGNnO1ZUZ7Es8akwtH0sTIzgiCY43fapM1TRZK\nsb0L531gSWw5smMi2d12XSRddhF8DiyMVZO/91IOSC7lfy5S+GfVjzXIDplzSZvHq4+Adq+eTPrO\nSeSDR057JTDE9bBGiaaL/Ap9zsZjm5AMJc1gYfEOmIg/jrDP2V0fTrjDAnbjmQ0wvC9OJuSrwmS0\n6OUI7Rp5/l57i/qW6dys02k+XbugVvyWJ7q03Aua7Gts3hyWDRZLkHRfXhMNS+a6haXcCHhTRtB5\n9trL/anGXmZYDfKJ8XkRFbZK7OQWqnQEvDLXnBCCXJeuAq1ofK1yEhIVFERwJLZ2A4KxZ8utsGRW\nBRwLMh9KpRkrSg0qF0wHSHOqiqbdDrboLQGtP+SVn10jdiRFs5nfu1zJMSH8L7KSWr/zfErXF5vG\n74YQ0ib5DEKy4gJ44Nkf+VtTdxoLKR/ufQzq5HqUXBdLrdkmQNM6DxYf/UV78jkDkyz6NAvoCb0d\nVCJd7LaT/RsYpNnZv2o/kW6MpL2YV7nnq13z7+4gb/ONuqOD6bNngRxdsEKfxuL3Fs6BKAdpfkbr\nz1BiAfJ2CrWONqUKfceTR3R8BiwhyaMay1qYhE7iPfb5X0ZU/mHg68IXWO84hb3HLUbZC6aATtRd\nrDyG72D807wLDxsUAkW6L1NvFxuiNlnjhyGzN0/w+EujbB1JA6aTBLPTrIQauNqRebNRReFuJWkk\ng0LREXQ1p+ge08xA0Im3HWRwA7YO1+1oirfPkYrimmQMuH8TnvMrrBWrdNkPAts0OWARbG56sVid\nrtCjWM2CiYeonoUK9HGNGl22sWKBMH3eyaOpQq2uATsWGy1L6/4R6UEGDOi5cxCHIOBzhh0qdK/C\npJ+nkpADXQDipyeFa8p5tfm6S5sWR7NxLTCNya0gNisqyPGLEySSCpT9hnaiMm2OxUjccwN+VlYt\n+jyRR8IwXdnVOIij1hur7X41K3NmTwnz4JVtmHMch5VnlOzhwlYsByRsuR/n7QC39t0cbXvdOQuy\nDuKsIhavyccbm5IZLriVC71CHL3ddUkf7kKWTLmv9/V06dZFVtwzyeh7zQZLkBCWF/Ikh4UF5qOC\nS42oHjVey1rsXRZIc4rm6IxgKzbjVqkQbDQ9YbTCJDEIsl7vPIwYbog0eH6Yj4AcZkwbHI8s2xVg\n9CrgK14SsJLuMBLR6jRVKy6HdOAuDPaEokOY8hVD1Bap4svMz1kb6fG/GqzLsPQsKuHhWPWz12eX\nTevRCXYheJN1ouNbr1yLD+z0KA8pEsOBcs7/01eHXU6lZtGSpPdzHLvRo1pemElr01zFjDNn4YBB\noilEWwiyw5Zd0iy+RNL3du8O3+3bd5aLYF/uPklPmF0z8n29ncx0baV6TgWFJbENiNoBIcHvF6p+\nRIb18/M3xonmklYV7DzOFK5YcxEBOifuLrlL7xLgSK/ocjwibEipg22FTw+oQuuzEK7UC2dervi1\nyiGk7/I+1YKMR/yX2fgcFndC0jt72RIZoQ1VTGXQy7yeaF8tyholMCogd14WsiaUHqA5XBDX4XTS\nj0vGAl8CY0srSqWD+7PqoDcu68bvd4tCmT8PnggdaRA9VZ0nArpdrueCrJiUDgnb9diGgwCAoCO5\niW/NV3m0IYUujC9YNfbokYwXB8NU0NW5MUntg0RS4sBvIppyE1o/Dc3Wr24xgFoSFI0pi4HSlI/K\n/g308L6CJd9NnuuIMSu/dAdMaGIQPM6aUrHe87k6246cpEyEESmZHRiHTDAHECAn5629iaNOnOqk\ngavw1nr37khBYC/zT3/NnIumAv74f3ojtHS8dGe70gRUBJaoDX4Y4PnxhPeKIChMnTPakeojGt3N\nImJUBhpTD3/GHYX2tOQW9I/aIPw+92v+2et04rdceFmzWS5ntZtOck1gpr+eWs22HgGj9FOUvbED\nLQwz86TgSZeiXsM7QvMBiAlODKY87ukdAlYP/J7f09ZtK8nYpYgI/EdrPIeaQca1woAsZBLhKKDS\nNKq4WSebDlqJHGhabvV2Gd5wWvASXU5RIm/X0jUzgwtNsWrT/5OhD9jBBpN1fjg1Jx71XV683rKK\nlmJDkpBcW7sqJ8Glte/ejSt4ErZ67qVtvfZfNm2Nl/pAUNj9aALxSUXRN5baKcYpzwqmrvIemJDQ\nlGeBP9JGupkaJdXVFuFIz6/xBfkqmsI0/0zqBubjvPNJJoQM1/lQ7b+arPVOwJMWIKaaIciC0/7f\n0eCpAdtUxSL0TUCsPsEDgt9HbdrAL3Ky6TXDlWIgBvruQFE5mGi2uk+bLJw4MOSlF800g86QaQ3Q\n7hQnrXPbt1+NYm/g6b3M8t6LNFsETE2s+7iNtTq3C14GMwwGndPtiONOvdyHKuCGMcmxKuV9+Uxg\n+HfcxjefK+W3/MeFVX6QGbCfnevi3pkOEyv1XAJ0ILDLkWtZVHfQ3AtAj4PUURt+VRsOrljx5Z2A\nuy/ubUcPJcIY+NES/T3A/MceEq8laOgEAuRrW7vmkGBqptO8kjyy4uWpyl74l7680W/9A4CNXLoL\nU0UJndSLPX2rrGIXoJFDP0mrO7Ws3Y4s11Q+yV0nq2Stu3OxEqtBA7Tk/ciAv5xdHNIl7mwOBqL/\nINEX/xSTuGSJdxVgq55OnoD1JdBLZs2crxr8eGcJOZZvVOjz5V11hZNyGX2DhW5TD+KxlO2YDmi8\nSGCjZzTmggItMyCgltYLqBciAwFFdwEWGMHap1VmdvVYd+eThDJnOEqN+V6JTRWyFV6sUqqEoH7T\nc6e6dU+y3d749U+Asm0K601USKAba15J6j7U/OuA4BYjgDK7Z4Opbx/ztRJFT0SwE1FnWvLi2GyW\nBgSf0C1p8qN/oGFYgBIrkHJtq2u2vTTU18ZO1A1EFSdPZha4NbWr/y6b5f0SZiUMpmdE1rjxPm+P\npPlyFEt9dJzIlHQ4a2LLaqOz5vu8tqcg3UxRfvsm6/3ZHcAZZKs5N4ANQWFgqPNE3fPOpv+EpWQp\npRcKmTOf7gKqNbYlvAJf8qTTnL48zcbtUfe9R7TAlfoar6JSi5/uwEWyZ7p4MX1in2f1c5LLOpIx\nV20ynTFqQy5GTAVocnp4j2rlZ0NDRhbCh7+w1HhIhKkMZM36VxMi01TTlPm7mDH0el12HjRunsFy\noFmchWbII/lG3z4ZLM6nDDz7KmdlKRqZsI3exlxFdduk8quR/sdRc4eEO83GIosVtVxTA2r1oP3r\nIKp0LM7yztIjC8vDN+MPn2iuIPIrFLrGURAThFUeSqbJFL3g2+BkOo7bT5/CIEzUtcfpWdSSvYLh\noc2vNwPk09QUsXaTd+rENw57d+AzdW9Pdn0SUq3q6qipoS/3+1HfbLW560hVb9z2LGrgecGOgy3D\nLMx11JATGveEVYSZrR8w1wmKOGuO+L+6UQarriLcqZ3deagK14RyCVa046syoAVPn6mDitBUrkhM\nCo5wRCZdNg/FT8OsKtgJ1wGYhWtb429xlmPcJPzAzM0hqNR+tTV7AwG/vnManXH4lwd/X0RHlwrZ\njs1iAS0ntA5TtzQRzggOPPCGsz9GILdW1SdIn6ibK6Id/97cp945PMYpiZkulKWKC+U53szeQZSj\nnifcFjHSKQKEsLebjNsxprtWsePop0ISWgPnR4w2cDUuZwdwtmOm/9jL2hKsNDqoEMqDRXi4yTyY\nGypGQvWPQ0mSTr+nqeHyY+6J1ky/pcod5N+lEChKI4oPZwaw5rfs59UFs6pmukaD+z4Ba62OInz0\nyEwOQBfR6q+VbmRb07ShGs/mZi9ceiikbH4OIgXLRbrheyjuKXlKEKt0/oidf1Xvpx5IAXU7xRyg\nmaNKz9NVTHNlBb2fSMizkzwKNEgquV5JXrg8cnDvvMDdwGcUeRjyFJBMy5Sp2XT8jN3q2iPmQ1YN\nAV/62jR1+BQgCFiOR10fo35kR9oI3QoIPiUbeNpmhMkbSSVCiy/FmiZRKOROI5SYzoiVOOMGyuMW\nQD+CD2Kch465F0y3738CoE1TJmNdVYm3Ln4NTxK4iuLFIDciHpKd6jGHwcwuQjx2QNxxejkN0WVh\n88FkpQ5snOTIiedz9tfsYVSyteeZPtp+Gwt5krnBZu2Y9X2HDP+LBDT/rj1+IlPFBPPdFB/mpBYi\nQ4Vagq7cdVKu4xFiCLMjR1lI+m2tkx0yIM+POEciGdov1BZty/NiXAkvnpdZcieOwt6MgEusyvj3\nWWZEXXdziCpdkbvcm+Oc/KiojkRT8C1otA8RBguh+X1oV94AGot1Ej7ezyFO9vKNi3uk+QjweP+9\nlAGXJcAvgtinMuLtjSibpPhOpmpwnFGe3B4AQSpMxrTXFMp1hjdawQ88QnIF/vzlDojp3clCjDv+\nK2t3X7KxrjY4oHURfvcC82WRyWXzSrGHIq1fF9TIy4BGCkE4ZDysy+glwx5/qlqGxGVRAJY+xtHD\n0uFrW3EAhnIRfTyHChi4HaAlN0Vn8RfgMNrjun/9CrJ1cR3B4e9FS+2luC3KnSmGqj+Ggh0xQdjf\nO91mJKx/4u3i/hSGxfhJBWv5FJs2OO4+iGJ54L+RQ5J8xA+wFG54J+LM692p/GHcL2O8cTvp4bqN\nYaOrbTv/jE2LInZNXfSBOMCiTKtWy/wXnE0XRL0aYtaeD0A6oVj+ffmKrgftPbZluZ4hp87ngnep\nPNERLfyH65qtfn7a+pDilnNtKjxfCC7DPPXFQGWVu+V15RxtixNtXEKvJHVijIdKNlu5Cxf4341/\nJgxeoLevvK14fCTSa+8CSsYVf8wcYkbafOD9EwTb3G2cmyFcK1t6PxmCyPKdT9aBsk+XKEm8ozrD\nMYx3gHYhhVDpRYwgyKpAp5QEkkBbNh5EbGkUMKbCCGmjixgMfmYQfksp8o4Mm1XS1cMj58dB4Scj\noX4TIcwlr1bBCpRGKvoRPyrW6PkZL0MFXSgWgL52YgLD23N7JrDOcKMzeNh/8BYqaxdv79mQbpBi\nHXQuuFEhibXgaYm6GQsqraAIS3vCGBR4RhIsUdMK40B7TU+N0Hq8y03QKf7sgg6OBgBGsFw3Msbx\n4se04lxhh558XNnPjYwQty77kFrQyqZiAr3gRPJBUdrq/b5qWe9uuR7o+fR0ZhicpZNH27VL3ui7\nvS5qlE0qUJwhzu7xyoQKehpjazzp0IrCNS3MpaQ1oC+HwhuB0nWNRYLy8VhNvTlyDM9pBoqUUBaK\nszOjlVVtxtIqc/e3up1mZjmQ6rpFv7HfMo7hTAG7jbEDesJsAcFdf9AbuFaRvOr4dDYK90a9VZnT\n/0dRhT/85ecpFSlGOhhuWvw+SvPjnt/zku+KfU8HZRVMsjhzLNz78NegLojjy8hkC6dBGMRwBraR\nvLm/PjoNU+n6F1+1qmbtfcwkB38rsILykZW2temDR3QW4ae/9hwxAQsdY63KDgh9nulQ1RRanH8w\n7a15kW+B93Henp8cIJWRukSZhxsdAuT66uKlJ6LOmG+YRk8Ru+gCzNB3bXRX8S7uq1HasAKW8L2z\nquVVxky/3EdxKKQF0KWHwDb9Rq54oNK7oMrfLjCOxOv/f1zttAO2PMhefEh+IPEE6ciD9xfnUj82\nMJuib8EFRXdfZu4OTc05zDI+Y1jzbww7tAygzNrbAQ3Qzlojlrk06QfqkcqNLDuB5/CWmTJxBmMi\nxCNBslwOpv2yudPEqpzmgxoSk3Ge3eEBDWDYH53MmBxPPtkRvumzAn8PKH+TZhEbYUlt7A15Ke52\nqF6y4CsdW/CohNSruVXFt0yBI4rWFVQO/6UpxLg5opMxSMQviiLoXbbhrI+Aw+WJmSNYyKgikZFC\nFM4pVX6lh+kwF3Mz6jFj1GWVG7fhVJmPzKtg9aGbZpZVvhpAeFHZqlsQfIqjxmw0tbno+k4GlYhP\nqqVQvfMNmwdyS6A2oF3FbYXGgugs6E0FVZtH/JbXaCYzJBviqCVu6inwsgWeTpo39evYTHOxizZA\noiaFjD8in7HZK2dcJggPXLSSNh/EbKfcfsCGUlfL2kNkDHMJsvPCu+irNFKbhb3u48Kw5apvl4Da\n2YBAx/qGmjg4WXRcvFQ+SCkd9Bbswb02V3fGgqS1uL2SynIOwKd5IrsQujdfU6Wyx/pP/EL2/mTl\nwNBkfPzcI7CF79KS5Mm1AOTEzKHmXBMHtziMOJVFBwBfK4OFuWi7HMMxip8MEII1Dn+bUHl0eSM4\nWfzhm9wZQ/hu5g6qPSVWN7WViF+9AxYS0c7vx/fT2A9fPYwJX1dzjGarJ+Fsv6k+NUMsvGqgH7yQ\nlQBi3kcGOI1IugGnE9I5WTszrJa89JZ7Xp0acdpJ7OWF6EzzulRq4PlmLyhtkrzKwzXHrqHdjV55\nvIpHXjTay2/FeibBVIKIzsqhya+p5ZemRUPbYq+2zYclkdJ5kKoSZHSTBYv81S9r4Y0ek5iWUpvh\nOiOlhtO2QgX9wEL+2eihPdaP7L8WMqpqMGA6f/34tOpIsaU4RiXpguSMn3NAm8JRVqtHAYGlcmsX\nK2ALMmOgp2zB5gwSroTtF5BcL9RBPfm5rnFSpnblp2+XmIO0WSJjmKD03OCvxfuJmc7Q6mdqwOHG\nupHTxBTlAJ1M8INz2LBNQdi5IePkR/TqRtDWN6xllrPZa9X/5a0Bd5EhwE3xCOg0iUcGd7PJGFKI\nEGxrwmtvFpAAwCg0biDE64NDIa9cEnLhdFQo4Kdg5Oc2Z6eG0NJ0HkSKABcTuXnuFVJLMNAg9qaP\n6VLZ1Fv3neGPwH58I9MqkeLL6ToKN4ztBJGdMZ0TISmYlB0tj2oceSwDtbv+jeS2iooZMDV+9qBS\nTEeJk9C/spdsJC2GbMY85HnNJ0Za/FJg3WlKiRFQj+185YC0R35FZwgOw0X3mMAmZdyp6aT/fysb\ni2/bhBQ0IwBQkrOmP8wgpfRZ/G7tdM2EnxMt7qrMrfXUZAihLceKihT5a3ERFALUUKwQ9m201Kwb\nGGuva7prMboNf/3ppfSqMoBEiE+2MbkQQtp2XxwSf3ESj+ihNZVX655iqOJuYJUoTVTEJ9hbRwA4\nnPFNBTMMEqfYL1fGNEmf5eGfqfKktAcTY5sZOfK9bxjzp8u3pwBErvClbkVHu7gLhwOGiUsShIZO\nqto5C9EJv563yO/P/ayajt3uKD8E4oPJhaLlevLD4x/hGcPMDS1maPeh+pXMEyTaOvbyn2k3APVy\nAwpQ646UckTfRpmPaUcWo6bVKTyz44IHFqa/RnEGei7gz2rnKWpgkCIJMu2AeqwT3wxCZdAepqn1\nrj9epftT+3PcuxyOo2FmlipvmZ5cguoKXGuv496ibaG5vAjEJw5xsn8bO+HrCS8B08J/OsZJW2MA\npepL30731dDIuOsqvAeBC2GImWUdgyG887TlvQN+eTZCTPDssFJkRr5Vf3+HV2xFyRCrJk6pQuNZ\nwtZBoHyE2vO1XLT9fJ2TmjU2Vn2Z2lgML550DL9u+VHpamYY5M1W/vVu24IiTNnl18kpo0WvZa1J\nTCjWUUlyw5emjhI6+0dhlpCu5wk/0PROLNG3H7ZxTBTuPrFOJNUmfJdQjrlm8y+rOLpWovbN+ZRx\nVFiFwY5XSBLhJX86jc1MUWPqnE2jab6yvtX7tbrv3bX+N8wraWTVNS6vvAU6dcKdiECYnRyIZT8a\nxJhZN9fHw4Wyx25sHd+Y1R7SAgexdJyLp8iJ+WEJxUbE7A5xm5zhXGDyAjUeiA65hJxW7lwgX9w9\nn7ig2p0XOxqgRQuJoQRXEuqp5mPZGch0hfW7taDEe3bK5L7pbh8p6ig01hboYkJdkdWTFOkqLmB3\nk7x8VsvE7zBV6S0jurRJ4u11BXD1PmPIPHIVJRnTl35yGwVU8rZwKzISTLb7V/mfgHooncyYYTdG\n/uetP2cpfhJWw9LJj4E9SQR3mxcoKOZxW8NqukwSYtq/d78PxX+6Fn+J2QTbmx6Nq/mhqxGG+KEz\nogCZGYKKbe40WedFzggv7aJlZZMP1eXmKA5JafcYi8k2YuSmbKeC3lrwC0w1gLK79OWTRv0PvtRO\nMEDcOmujDWBaPMxrN6wId/gnrmW7YGTfpytnSo39AkAtvoDZJEh0JeUILU77mqqcsMn8xLinW/v2\nBUx76QSdsWBzu+FU+6TnGBU5vEmODHnqxLjm3ov0ro4pjSGx5g9I3aGKqR1Wp3UmewqBOB3O5swQ\nbXc3cvWN1MV5Mi2h0Ps51zhxUNnBDZYqttRMOoWENAOzYeABYq5z6/j+ijAirU+NDyyuLV63i0mI\nPFTzvJPGKaVro8XN+d2i8lbBdytvLhkJ57oHoONqEnti0OFn17v3OPKUQDnm0bm9eW+em2UePXHT\n6d9tiCnEZF5I2L34+pifAT/4lH8bRhk5CBGi155ph0tLXz/RSZDiskJu8KsGVLIfymDRLUEKDeh/\neG1wU6SUmaf1dQlvarCcD2Sb4xUpZp3khYVfoiUtPtVz3uoU6sqOIdnYTSNd0dds5ytuV7z58qpx\nA3fB0USi/Q4tzstU0KRHHcY8NRPNpUI8eaI/oRlDTpfxnZTzqDOUcLTJm4mbS9r7vIJp8FBfwoQ0\nsAWjBjJVyXiuwhyweEjQgu7PpuohQmtZy8zeN1/pOY5rmi6CSqiae8aDr0FFLa96EPdZqZfIytS4\nYZ8JcYEOinRGdNYbihOSqGcftZC0KR5dnJOXBSsjHdpft24bGMxrw4YPJH0IisZIo4IA6CyINcdK\nhLziSFtxnYcqaxyKp15tw0MVOVkMYzMS4/IjcrArjl2JbBGL+NrBP22nF8ibW+JeTScRJBmWOe/G\nxRvQFc4wVPFni4VUQkooD4SDBvvSkRoWQIcMHsX42WxV6DsjPmxhrMepRZ1zQXnlsAJQuwEfoEOw\nLIUI9+xbgoIOJ2nqkD6gkzXZQvGkcz0Iy48MB5DCDx1iuYmwDAsNaT6+NVtfFbvwHLBk8zGTW8jt\nkvsbqlTb5rIxy0TWZ8yxAxITeRGUAbiA9jLs3iB/tfRmdcCfaLcyV72pN14Glxiu5JHjyTWQK9jg\nP6K9fwJz4oYwTQdllIUbVcQylOXSqKhVFA8Q50DN2luOXrKZG0boyNMZBmef7xFDqenKhJ7B0mD7\nY9rblZIBepoVTWxTSgVE7em8roBrx0jDtHo8PDos+f95y3zIK5u6qiZYNPiMG/g79ZGTiEZkEJeY\n4+/B+bErDHTyqbVaYEyxcPIAisGjLfnKclto7B25fDL2iDPd2jX/uK5fjiIXQEe4KTN+awD9M+gD\nuPZ17/1kShyeR4y/K0C5xBYgE9SkH0ZSGUtMw2hPLz7vCram6U3DpXgFBMFpUtFTiu46xU6OX4D6\n4xqWMfAkhjpxFhwjQPeIsXiPu2yslAPGX7oMrZVrIoERn3zI3BZ20DjFbt8sNjDlczF0NfESiwn/\n5YRhaUrI5vcd6ZOMbpnAOmoaaOfahUx8P9UetIGArgoCNCHPSLuVtXqOdV+ZX2htnJM0jpc6m2d4\ntbXUAJWmKxH9CtnS1AVwdJQ2cwi3RLbrqNdRpd+HErYmnbtj+uaCZV3wdJJGgno00W0f8DixG0MP\n6I+3HqmJyH8ONzRxKp4xaVyXI5ld0La45QZocN8DofJEGc6B2ACS6mzDp3ueyJgISAB2Ntorz/fC\nSYRTojhvxbj0y+4A0cHvKFjGGHRXAb8L/QaxTwnSw+bHNU1k1MgXlVF62LbjibeyEZkxsYsUxJJH\nU7ST2sdEGZnHuKPXBnwi3u45zpjd3WM9JGV5Iww0We9+5A/l1cZ6ygOBE6gx8GqB/ufvjGaWcO6z\nAIeZDVqkdsuV3q0/V600JPz2KOJ1Xxv5bTSPq7/WrFiKFTb6BVOnHKPw0lCMsMhrOJNebjU0KBm4\nLJpj9hSQzMIb+9Bggm/ZGMZ00be80muweGPMWGxqWubHwYOxTKoazjn/XmRpmdoUx3bmBZU2cFMH\n2YlisRGjYy/nre2FlqN/ePjMCVZL99wF65ObFXI7hzjK6YYzhU3RME5UqVmI+O+WMWllcXzfzh8O\nojwuZmRrOjX43HIZF5Iu1nPGfvgWGJixoFwznBU7hheyX8fW5i93VJyK8+SOPKXPwFpXViL+6tmD\n4sZbG9+YV0sOCjmMXAHUflZkoAf5twvbCfjzaEFkYrF11qjCJtkWWZIYvTzxCBBMNwu+8ig19073\n2gWHIAx3nzTpkBODA2VarjD7PFF3ZgJ5YHzPh80W486h/FOGsflK2gXPYVsWe75/ALtaTUU7N0NM\nYlbO/CY3r5lNhJ6C++ZjDG2xl3enRBAh3+xqjCin0/jPe+WoJkRGR0howXs4Md3CXSHNofnzeUDy\nBf3Wgzb44Y+i0xj6HAqYD/v9mSQdALPUQ4zsFa8Ri/t7fx8k3onFQz2PWIw2+YSfr87FCqXeCxdh\nPAevRuqtk9FiMPd5p5rHXzIb2MVzwpodujpmZQxjk+DvjZoGNRmzMLJqCLkn7Y1Ol/xcxru6AjAa\n+WfSraNfGd4m2R7UVgcfJaiV/6K/ItXWN/MuQ4C1CHVKi9QQEN//ylnRniX0pURd3Jg6Xdo2Md4C\nxOrbiRLB/vzdC62APYwoNGGEb5SRHvlPKfIWBWfpi1wFA/SxV74XjpVDQnsUHv6OV+U5zkIBpgl+\nKID0PMwZT3Ah1FdOwphiyKuJr+fYOvFRtUT2IBlmuD5jTsz0GJrmEaB75TqIg8U6IEr+AePyDccR\nk3dFaOvKTqmE8fv0xrx7NJS51JI40ZMTLeSnVjM7BOpuZsnnycs1e0cqD1ALVUejDFlxY8q1IHIZ\nPP/u2xzXOYhdmEpGfeO2qwPy2GCXsYO0Z3yhRj0Rkh36F3/CkVpTNtNHGP7YFKgg7FRC6XQgpfOY\nWQzhA+SN2Ulb85A4ag+Z9ESDf9ITIM2ZEAOODA6PcgizjCLJOqXp0MBF7bY/VcDnhRSM4cnNxHZB\nYqclYGsYAlL1jlZyVHBwrQ3A/Vx4OfEX0aeaJBqLrG1Gv9ZVr0dYkGVKF8S9O5B5aMI+AZxt8NzM\ndgILrzOSx7rBGrjFxtS0iDDPThdGebnGBK6xdSg1Z8FYuOrFlsoNQ7zqruJpqWxyizXu4+d74u3K\nzJiL79ahO+Xaex3rzTKRo/pZrk5Bj7/Ct8x/pE63c/qYvvCThNVwRtfQtEGtUIaSZhSHDojqWeed\n+KNSuuy3+GqxyB2yQicl2cD96NXH1Ji25y3N6nXIISwXcqiKa9JReNkSnZ6svgbnfbs117Bij4Ml\nIOEoZWYKoRk2vHYeUhy87n5Lrytt3L+Ckw0BiKRigIWdGTnMQJFyvD1UcYR6ruXmvS28bs17r/aX\nTX+B3m7cBfH32DdH1K0EtGdbVZJ/MkIuLYPGvH9xM2UWAcKHtCt3j+Korc5y3I3apgV+8B1xB/xF\nkUgQyCuRVfk+pjEET3jnFCKi9X2WfYtUZUwX2zuddSsNaigOtuSDP/gz2ihhJThFqJw7UL1dKKcW\n5eKUspq3zdxRQoXif6sryN9V+1Ff5ydoZZv7gFnIXAaeoA++phDDYMpzRu8ki2i/BynV111f3dep\neQArtwidOo58YA5mqO88Jhzjx16QbPvoToyr2kRiYO4eBpDc9ejssMvXrkaR98Qw1fzcBVDcclpK\nZGv2B2lAev03+WglM4k7IxDXrTl32qu2MjWE1xXY7qf9aB4P6lhD3Vb1NqumBv/mS8RH4l+FFzWW\ndEBYOIkfJaKB5h1ayKYkGBSufcNnsBYsgcBqqxaFZfvx9g+hcXOecZOHlQvFDph2S1ZsE+dWU0Oi\nstSDfY1FM5Uyk+h3SXPXG7VmNWJWLwi7acGcNZGJmhgjvK2fLyg+Ryxh7IsZ6cbm76zZjiHDHjW7\ntUUXEst8+5ueWfZKLiL620WLgcwxtFq21PB7DSHG0WsjDEJ+oU39S+AO/4v+6PXuUobHdaNJzB0+\n1zpYoQfyMtU5YThjImsuLAGjrtu5VgOKtEsJEkhcbXSq87y3+zE69NQNblgaZZze115Fp16SHb02\nXgt16cEH8nFOm13Da90LEy6sBVn08Avfy+9PyfSNQ81ljw6L/QrUM/T+nFDMfOjLgc0wZMU3tFGo\nXuBshG+3vqWrvsIZ1v31XNYPhVQaTI2QBtRGqVFdS+X2j8X04fKcuIIafYw2gLiYA9BgVG8ofeXe\n6bvnPaLIvSW9i9uv1SGtyTmgAWNOyTmDrORI7sst7MSK8bY33rgQF9iCUzbmvGALeMru+CaGJ+wT\nyB7LDFrPYZ4rSzk2IU7KDZhMeWJCqaRl6zPghYb/cfaEQSVLHs+3tybqMQJxEmhq81kAMvyBLUt6\nxISZDRL0nncYg5Hr4K2SXtedZCFyok/lmT47IiJVM9OxIuMeRQ5TtyCrUtUQusbwyIioDM/6uSyL\nvEd4lWUrhQ7n8wciigpWIm4nqGulMTEHoZZ1XJ8Z6mo9F7U/H3plMp9BkVnBq5ENMZngcJ6NYpOq\n6zSPqwnrGktocE5EsEVc6zMweTT0554a+RjGHHf5slmS/XiXtGCaHF3WJ/oohOvESCvXqTqitG44\nc1pXBLv5BQyXinQmTStGOv060y8sIiCAMJ/fa0mjAi+N25yMPeh6DPIYrHtD97Vs2PsGMYG8cnLX\nqCiFIEa9Rvw3v86+7e3dVOB1tL9LB9ZIrXEcDe19HkPCAnBdhNVfI+VRQZC2Egg0sC0xpZJwECx7\n/QVs+G1lRVisFG+lKwxvRmDnGSRdIYWnZRGxL4yO22LQyvCDvqorvucIdQIu1Rnzr/MFo3e3FHLD\nc45TnIkFbqAFYNFkGIO0CBNc2b4Ju99KGZP1SnVKmXxknzpLHf7ga3mlaBWi0VeqHGwXhkQ+d9Ou\nMiCA9sFc4wrNIqOUikYc4rGtsCkCI82Jf6k2IHaZN8FbIiQ3qwr/8fj81P5N+sBVdhGxOcAY6emq\ng1uppFVWp1/gMNwj/cBc9RSikT01Ur9GgI1ZwTo43ojkQ10Kr9wnJ6rVbl/12thRGo8waPfGbtsB\nS91+Zshfbr3fEG1BHcZT92/v2OGWznDhc97ZIHl3uzgPDSiZkJYw8MB0FSsKdVz/2uNaiw0u2Us7\nc0h6dpQ7j/DXBsGRHylN6cGTPUoKUuJhtp/RCygnxRM6gLu/uvNwJmkA9fg/hpV+Bbd+w9a/cO8O\n/NoJSi8NX2KF1xgakydjimaidNfC6DFRZZ5QwXN5DnKhazYnmfPRYHCGwl8m57RjjwxSNbXiFbPl\nHilav/rot1T3cQXEzzoSoiNwSdCXm02P6GRu1C3RpBzrmQFebpvqmr/o9mqXDk+QzhO4yvPtrOuf\nOya9CWgBwio2aFonSv8pjI1kuuFRtlABgH1JqJfUrC5M2l37Ezm9WwcF6OPOw5R5HhCsA9r+TnET\nfQ3hf3/EQN5Qw1Gi9ZU9BizfF3bygPej3ViYpHAO3aaJceiQBo+7fP8xN6fVodPttqPpIhTdeIp0\nbluORm3d5V8wGH6Hm+LQXoCwZzulLx0X6OFov4Fiy2EVXXNudO0BcWBTT9LxJLalY7ct/00EOP47\nHU4I747dXjpme+SrGyz9sOn0KoKCqutJj8t42P3SBcRKBrWlu4FIQJZUwP7SDtxySiOhwlyuCfNQ\nRUmHwaPuPW9Y0UQMBfaN2x/rnSlI3WfdFU1qvbYK0zA/cz70JS+Qesy7q3Trx10vxXo2/eUVjL0K\naAbOnlR5dQ7SJm6moiGm1p8CImjIBWFmqigaiuUTp4/AyzYDW0ujyDvTmWJDW6EIbINxmbnqpw/F\n3LMpDDQ0rRlKAED16+Rd1i7krx8rxtEeUPiT8CrBCggeZ/uSFSQYdcBNdvfhDhO4litKRV+HRkDd\nlQsExCLFQfw5/n8+OMZ/esmp3R7f0iXPOI86IyPh5M8vruW9TZHC2tznnM66Jl7SpMwAFl4U/wiK\nZZvfFpavteSCclDp1apbvzQYMJYurEjKYKTpiOq9u1K6whHt7R86exebYS5s0UY6p9ezAHobpqKT\n+yMQ9Zw5J102SRSzFDkKvOMFFyZmOcMDXsS2lq524/JJuAGULhzUoDLHOI7DtoSuAVd5ofyMq1Cy\ngmDwWhxZ0GAsqAR7rjYxX8AQuvJl+zuS/QF3oSQnaECUX4rvbfjsGOY7jplQ1KrWoR3tQQYIKPgA\nGn+79fodQQkomIcl6WfCuwXnVvsU7DL8bcClQzd2mQZ9vcjXQoacxpEEoRESw/a8oQuAQ/BiuHJZ\n77CZW1SmF4bPolq/ZuLH2UCsY1vQudGbVLeeb8p/A2nGMo+ptrPqmRlqy3Pt9iyv0txfm2AJKALt\nV7DrgTCH94dY1HZnVb0lFjo27mSaIdzm+GjBP16MjblQ6YPt8Fl4sRg8FS9D+7Y+cPfVssWFPuhN\ntJrNFvu0DiVV5X83I5YsY+MCpbuhPib7bb7mPmxi2mGZWEMvOJ+Lcp+RMuGJw4Zdv3iaRR3Qe/w2\nHXYJT/ppecT84FLBr/uHh2ecn5/Mze7OuNMkIwzpfyDjxVUqyQ2MoZpFkzqZcavg3DG/a/xr8flP\nutqmoXr9daieg4vcWD1Gw8KDgeJ2ggeRKfg17+hk/ZnkCE+AX+memni2dq34CGOA1Rk5YHod1aYL\nVF6v3r8Jqjuh2NZGJ5p9NykL5mG2HzEKc5jWQcf9fekaxodFpOEFP76oOiPTIoJ2WVNgmqe36x3k\nMX5/dqQHPDNPplf61Bly7b3i3mUs+tccPG6qDvkn5Gv0ADAC9iYepz55U4KEYwwmTN4IUc5n6tbS\nxWUVatKLiyyDm09ULla8Lc5A8RfWKNcT3B2X7jFFfw92mc0ep4/lr6Z6B94pn/TmIQrTKL4mEUO2\nN/Kfm9VvsHWiDpO94N+r2SROCcv5dfkFwDdG5lG0l2g9g3Q7UQ92ClryqOmOAcme+Oi03Sqwu6bi\nb+bmHjRLBzQVPVtphvW53uWTngHKWMParJ8iqQW7tDZFjVwOJPNvuFxIzAq74BQxWLdgaklcbGee\n2KVuD8Lgf35qfuHUdP548Dsty7DyvAAYsezFGC+2OkABaFZAPjcw15rSdNC9nMs/1kK1ubvdi/Io\npwm62PTQsTVvpAbEC6a+1NckEpc1D1u2KMj/WD4jn922Y/jDGsDgIvbS53ir83CCkWUpt9pc4MzB\npN++AII4kSxC7dSjPtwisVSY7ne5Jf33gbB3Y8A3+p8LYbqVyTExdRJJXDm8CMBRmCqQJAeO03Kd\n2SU2Za8zQ2DQzV2k0i7lALbamna3YidqaMC1pAd0aQJdhIcq8XQwn74sx62EYx07v9UTpNdNV/10\nnIVBBd0/gRKtZYSWMCu8ydrf1SGVySrY2wD+UH5hzKh8gJxYjP4xst6k8R6waENfnaMBl9MER//1\notW8Jjx8ssEb9SzEIMJMwExrscRiKXjnFaR3PvvhIk94s4RJaenpgOPXS3/PmsspnYqMFrutMeex\nHOrOIlnw0yAPoX8E+E+wquULwyvAqSVrwJgBVjKplfx4TT2YWBWKUdG4BmV2EPk2Ht0JZ1l9OkuD\nC3pc2rcOn+Y5BdAQM8WFE9Qf1OgdYqcwMYpcHm4MqIUApF64a8UMPf8cgDntKO6yuJ6yulxMhiai\nwQcdATBXrPfAGLbbvyeXVaB+lyDmMjgMG6OkzfQXJfeeyBsx7PoDNiII6YiDol25UREiJVldqANY\nzKDL+uO80TFTzBQBfl+vB5AG+rvCznsKvcDQHCZlOjtpEUfPQ9AvE9k/3lyGGQquhMUDwvVLKjo2\nOlZdVgEB5tNPIfbUEsIuUE8zJHrK6Rl/2QBdP9jrWXCmz9EyKyDpiHg+p+rDq8z/SuGn1nsygMuT\nJoqqLuIFGXf4O8gj+zcNvS6MNjPgz+1Pfp+QbDoiT6h7lcV9uDdL6EXvq0L6aLagjgMsYWnVb6WK\nLlAEDMvmsPfJFAfG4pP9giZcPeHnvc5aiS8eZLkC9I4IWDSgzFQB7JLOzJdsCLCpvzp1MfOVPIgF\nJtuuYsXhIgYiQSz9vSVb+DDpHHT1laYednu1zRG/qAgrV4vtGzXW5qgisQZceB0dSSUonyMtzUX0\nrULdIXDWvb6+5e47NGBws8Xw9BBkZp0eL2QtYvqeyP/cYhr34TCsK0i9O1lt3M9+ZecT8fHjz9I5\n8nyI1C7D5QCl59XVABKGysfWXIlGwd4eirHm3NtuM1xnnanNKgsCpA0XM130X7bWi+2MauLD0Axb\nBzp2wNyIqJSx+AhTtXqf9xTVks8UbMbyntRdP7Uy2LMWcwzKVUI7WQDcquA05czdZ5hz1CbyS/Tl\nw3ihY4fi7231rTutcEuzW2WyiAEFpOsGqIhqMj5WjY1Tlo9LeeGTZuY3jLquu0UZpM333APlWKPx\ny0So1ifU9UQs2q+/6NNlZtsS+Ipr4EVJxlUDVEIKguFLQEf9XrfHi/efxEoresn/2N6JxrXzE7uE\nA+kLsm/L1DCdLt4dU5kDSoySJmMwa0l22+eKuIAsDwvukMCt0V1xmBHPFQ5RgmIhFgXkTTrPziec\njW4g9lcJPdC2vJ3mXISGjnZcBoCcqq/W1Ek+eMfghGnxrWO93lFBMxhp34bdfh2H+LVL7kGRD2dC\nt/RhuyHVTyOw5GJE+uTebaYIb5Ieu4bp9V+JiU2GBC4kRMbOdt98J4h76UPNa8Q+B9pi+k6dJqgT\nWJmivSgTWBcH1Jl1qG8w46sYdUTralquTsGQavF2xX4jq5+R7DnQkjG5czLM5adqhm+oLjSyrtd+\nGjP86AcVfK8RJKfgHMla8dNbqEK6ib1UNch6tc6jG2eMdNOzdlLjazB1+NtqsLOEV0oPuYjDh8I+\nbwpP3WyTS4E/jIxQXTGps/UqwRKZZrhUJ9d5tY+xXl6Ki5ER7f3j2kto2aeS3j5wFqlEdH0tm72V\noLkAHNgOnrxZFZAqs4RLK7WfFtGQWPz0MTOZucBe2bYV+Rpd8ttSsblU/0sqZNrLdtCTzLmVxNYh\nTp3WIGISNJYdPdTsIMDaNnpzKUdSTgf5WIJOdCcSjXF/nFHjJSFFXgXNaNCg44DZKuqBBJUBlqyR\nk4Gu4STzXgRhWWR1WF4WqBr4S0AAJPVlmXlV3HmqJWvjw9CS5XUzVaHm184hbumyLa3dHxZxXKdv\n9WsX+b4ugxZ+sjgSpJ8VB2hoJLUBOkZmF3lOnLt+Wae4WRvIqCoUvLGXZ7/Cfkm0hsb0zgAiC3cd\nskk7TyIQQxHEioWMZoi4mN1KMp/Ol3VHaInx2Y8vpnnnhNSC6r46sqBiTVV4gGtCFRVwxf6XCWIn\n0UsMz4zZZ34/V2D7EECj8wDyD4ZwBNd0zWLA7v4rE1r2+h9iNFwVEtnToDK8c/YN5AgzXA1s0qfi\nP4/ovfiUkjrpnUR5YPbvHWVjG6jAp89XuWdkbpJSI7RQ6IYjMfewySMynrlDmFyzzuGh45LvVO8B\nYspMQ5lEfCBEi73Q4KS5wNh7h05yA2ihFUCGfCYazapU7zu7OGsi62+ay8jg10Sq6JElVystEoH9\nyz1KzuURow+/NiEQ2Q9avN+k6z3lRy58QhQy8DgHTDEH0ZcGk5cK7lR7B4bXmejYpueccdv+gqn5\n06kxXXNBkaipbQx611mszn+AMn4oLgyLScGc3d0EsKR3fcJrutcY5oUMGWU0YwkVm9KjcPqinl63\niYH/gq4uxEm/KNiJP+0wdtQXWhqTbtfL6J9hJiSKosyAj6hfLxELIYFLMhHFlTMzbhVOaI4+vvoA\nO2q9S8aKjaGXxIx1NaWu5aTFW5P4+R7UHjy9s8Jm6EOOjuq2gWCx+qq1TJPjzmYPGgD721n9vfAO\n/9OsjB9pK/53kBRPt0unVNbShcv6nnsRdUUbITDoA+nzwr/YnXHOO4vg85E1O/XArHtd4h4VWkK7\nCC1uECX0f7WG8rp8aldaqXrunhvHC/XMk659rMiiNf0A1FQCKsFJ7ebFIv4pPWTpw0kbYHHuWUvA\nfRKPWCtgwVf9C7c53Ii7Sn4K/JcXNzvCcZlD1dTjb4JDKbvkOrQPbOENmapZ1PYfDk7Ypg32ccG1\nPJ3PllR8lD9md/Xyk0In1HO7jiH+IrwXkbkT3V6+ELLDK/WP4XkHS9jPNH2a9WhUOxvtkQ1QUxZe\nawHqxlPh7DgEOpHFSyL6tMpHsD/iISEp8AJI4uz0nq2k/IZRXJ7vEhV//VZ4K3BA/S6NaWqbDsX6\nxxSjYj6ugcBiCmQlwseVCiGIpxIKLHB9slP8RAwnk2f+P2AxqfKTQI6j87uBxkLnypRqMlU7lMex\nR2AW4TABrpde1h36ZVwuw2mZzEDW3E1yiE0/MTmt+2vHLlCtIW6XKww96l5yv33Na7YY9cGlDqXI\nA6IFOQLlKGFiLj3YICdgL/uXcl9VhfNW5VLKeEdZ1MPJ8r5sr6cQ0EDx9JI53CYLI82OBBceeCOj\n5GTq479i9isTd8/IcYXxhqNCbke+sp+l9ei91FkDTomT4jKTS4olW5DyOGvuh9mt46ujngotheAG\nCJlWNwbbrQT0ZKRGxb25L63LlgZ9jxsAOe2jYg3T52sNMMI71DRMy3zMlEHybEedGSMhFKnLbAmu\nMQHIL1vSNCvM4uZbeUIpSG/QAz8ztA1w24lfklMA0u8tgMnz9cFSHHoroVxOYDwlEW9Kgsdri406\naBQtSYdz+pQgqjhx9S+PHIXRtk4MDpgWYsKzPjruKJ8RRm8kUX8TcnEzfpNF29HKLCy7hKdfmF8B\n0Yu22vPHc+RNwSPrB1SzBuZ48an+oAGU01kBe8EnF1qDkQROyjBJeIRvqRHzq0v0u3vkoN46f3ox\nH9eLfBv470ONMAKkG9TxweOHA4MboW6MPB2WRUsscofRuO12/us5ITO/z/PcOYSuhiAJWK5Bd6Rc\nau/rH/vMjJvWT+AqvMv0UgeZxQl1kfISZW917CQrY2UgR0aaTTgJXjGirlA8xljZ1szHuJQFZ9mR\nBw931G/iMKWEYF1sUWCpZ4Tk5LcWJrWd55JxCHkR7P9WG5pk4CvKWgtu8M5Qr6yJoJ3Fgm4hCNpk\nmOwrAU6JpXoQ4pgmw7pyG++6XwPwzxaeRAGJIKPN4s1lhVXW+3NSVqcEj/mYSkCYkvOfpieozLuV\nfH01v62gRkcX7o0fwMncNwOm/B/7eL9V/1i8WwW6/JAKN5hTDMnJbApEd1os17MutiWA8p2Ul3B7\n2JN/DQCneZ3e/Iv5NYDbP8Hh5j9k4H2ES/hkokYH7QR4q1WaEMbxfkH9orvpFIh4NkOQHZJ7+UJ5\n/IGuW+Xd3IM+s4paLPnTmonRvyAdNvttJ3eVOgsiDEuLHm/mrW6j4tfvG5qURXiWGNK/g3KmHyVf\nrxr/Ok3amduXTdqOwnW8mAU241BtVd/NPVSrzHNFNpy70p81NNHVH687XFIqmwtW5gNsf7j3Aw3C\nI+RDLzIWKhbu0rynLvZSxbTEs/HQtJHswqs/jBzjqbUxPwxkosjl0HmxK4XFmKwIrICCGF/cAFyJ\n7fQ5XONKD1w9KHaSo9mgtUeQC6HG3DP+IcI/ScFdvPMuKlza/wOKQYRWpNOPxctf6magEnCsO8fs\n+/UOMHCAeEzPqULfggzxpcDDFN3qmTwCXkr17JpFYwpqCivlnf6DWN8YE8cL+XeTOIxMyzbn2LbM\n9oK3Fyd4q6Fv9NyVcceD/6nuWl0HmUn8E5L3OH40Apf1jOttnBQu7tBw/7PhXM+yBNN8Tish881T\nsYC2/+L9cCefE6ZFsR9EC18XiPnn8tc+7gts0wTlTLJzkZ9mYxYB+pvn+P8nGZSRAWk/nWFEkVXa\narKsc82uy3wR10+4LEFG58FROK2UE8ov2rYVci8+WQPIMwiM+Vo+tP/KOdfrJXokOlI5lD7TJhLD\nlrNuezbYcVHhpVIVYPKtKwAoKNfk/EHIim2+zl1jKcVc76A02I/nIXJorvlTjA9JA7kSrUyYXYIB\ntN3rfOu4RC9RJKeZmqqO+wgjM8Ex4cyH7/NyYZ8/UvGssMzzTeMOx3wsy2vRHU/KjjJkDQtgQDK7\nvS5ru87ZD0RB50zI64qnbQOgmxMIw4QNBidnLZ8tk+6yRIKZV4wPQoldTWHinfW2Iqz64SPrQTkZ\nXylwQNy0EAE5dkWjCd+6g0ZPfOxrtjim76uQdgTERw5FxVUoWWDSATxTaueZTDeW07kP0xP2fVDU\nxWwmLI77FfB9Tbw7c+FGq2DUWyDzUSJsGKGPa/9a0MorL3jCVk1FLS6sgN9ul0WG9hkG9Hg73m6X\nghyMcT4HMqLbD8cnHwrd0vfo0WM3E1gisBVTnikiY46WNshMS1y+yKhpl/RTOy5wmjDzvD6F9yqp\nnPAek+BrmrNQmfx98LoyeClfb1fNbw2UsREhML39lOhtY1zPvYXpJ2w56eDDgLXiqWNTuUCUtXui\nAKnby2DKRDFWPH5qHx61gREv5aVRY+/PxQqLvunjnndTUCczyhXhHLBU86WJzUfqu8F27gjvTn9p\nXSqoo8WRKwKrZkFdF5opIXXcDoK1MHGfzKXka4zWhTLglLVpQXygj3TAMATTGsNmGlhd2C3t5aH0\nOld+KoT0JN1j9WQ5kW5tthzXD/dIiG2tkmA85vxIoYHBQTY5lrGdRAW0fz1TmcSuiUZjkUEeH0Il\nouyhitucSn+Z5Jppn9XViRAYBMSBz0TikqBBQ8+4cLkXsYUOL5Ma0IvRwIjF3A17iLicS5fqCIT+\npVyqYNTJzuQ8f/u+M7PXQrZ/Cpbw5vlgm5cSgQ0Qw/u8fHa4IK5riog2L4AHM3iXnXc6qXDJHK1f\n4lkVrme1ziH6783x6NSK0y3Fe2z7V0Y8Gi5KZfaW667kZeRM65ClXlsJeno5P2zOEJfDM+4Gs/g+\nPSH3ATjiIXEtP4SFMFsrCG4dObE4yd6sJ7P2M/HUA3qRCLo3B8roLOhrUCcNmzyEJiNjE0kovmdk\n6s19V+YBNs1Ulc2BXy27YPam22/lYim4oYmUxFh6qT5ScjluT6aOpk0fq2WjZe9LzWu98bGZc1Ih\n0RFK94fYdXbRt1XVQpPLExWjNYxJMk4tNF9bPRlreLdZO0+ZCMpMVUauIoaU1QB8SoMMx3UrvLEI\nWESkG5CxSBasxzuqYy4CqfMb2cAOoMcaOxuXRoxJUkkhjJhr96zsbjm2FC++6DuSG8HNjU0wAE4R\nI0R/FeWvVXosPaV5tvFjjM3xd+tt3t+Yn8UqdHnQIAQGkAN44s83vCwjlbrwkXyZJyHZVyhFUTP3\ny32GdBFfIFUnv5UdatbMaj+RLMLG+igPa+HxlNlfGWtbmivwkpxu8uESh9zqjhRknsxRHwxIOhMY\nh7LuAiakrXs3Q1jAKC4WmbWoFhBjO3PofRqVyM2MnMhPcqiBi1cALzj4Mf2Kg3QI0HnsmkP0dUcE\nwU6Le4HhYLWyHqPFGecOVMQ9yfRUGSeNZLZgpMSy+T6pTIBX6y0gYe/qcWCuBcmZ6HjFLbO/UG/q\nuR1rytu6UIEr87yCjTEBWRYdYhqY3njICdrtKAdvuwyyo7mvkNPf15A70CzISxZ4cWumf9CTvH6o\nz5iKRV++yJUi6dtTi6Go/Fr81bX5V1mh1uYJtqMrckce9B1SQvgAS7bdncca6aYNrIoUPNEq6X6m\nKd/fYY/qf6kIXM6IBLnBPOC27fw5tWMA8CHpL35rYAQOsGE9H7WDefLu3i7iUThtERMCd0G0/h3O\nISrdMPnZ1r5ZWsb8XbNSJmrF5Z9Yv9CsCOBAFva6Q6WE9oaNZQXic+NUcnELc5VT1D4gXzqtOZ7H\nU9fBYwovcNKkcm8WREL/c164UZgDU5MHZ8yPap1k80IG06SIk68n7bf6EFwgqT3oZ+lUQhdeCNnS\nX3TySUnCJZhzg1G+aKWu/LdN33yi7C2D576qYmzM/WVbXso8poJRiyKdjhK9qcKNKwnxt6azZX5B\nCNk7f1aq5O1R0HqkUugOIDRVfeiu0bpCm722BxWx6RsT2AlZYxaTJHcZZLpNJnU3g4qB/NnA3aFE\nYXTAecyjOpT+dOoxETEdVw2n3j3krtB5wCDn1cO8OhJH2k+E7nrSEm/6fx6lJtKuk4LrtcpNh5Jk\nKQU1BiFw/LKsZ+jnQLUrIomTaL8GJndoZCTsPb+nyg+KbHjqqFXtN6NtWSrwRDUKDaFF43mg6Z1+\nBCauy2l0OmfvlaKrjWH4q729pcSsqI22EFzbJQcVhPmp9mWdsXkObtKDIJGVolMcAiB2IeLOAbNA\nVeHis3Aa/u9UfXRQtOm2QEWzgXyQ0Ja3eDcTzjHewY8Tq/W9EQ06er1P7Ggy45rPBsXdS+KYxJhZ\np+WrDulB0q3uAtrQIQJmOLMOCQ6MuQTfR5ZJcpCg6Vk6zZ3N6PLvFsYoblhZkeHiNQddGE2Zla3g\n7gZxiaQa9XudpIljizNjxGc3agrBU5ylWoGbcBrRF5k77ezcGqKdDI9QTmw43oK2YKy++UbYCL69\nBCef5MbHR3vZ7X2soXzfWIV77SILRNlTHCdlfPLj4keWXBSzj2XfPxZ2PnXkbYvWuBos9uxWS1oS\nquY2gRp3hTEv4sgjU3m43cSKcfIPuCdNP70T+R7T5cCMfNSKoLjw4chLJ+URUHnCi5c0xvjY9D3p\nJTBnhZc3OHvagLiHFBYTU5ZbWFcHwBLO458ZupFzObnFVYavJv8OpNbMpYojMN3JE7ZzDP1uMLP6\naBs3j3hY/+4qtAdyJa2WSDMMmZtVTk+9RiAUhjG08egPNc8PaFNjY+2Y2g0mNFuXyg2qeqFTOwJ2\nWEagzXcnHrE5YHR/KC5sMBD/Kbw6LHKmcQt28i8oxyZfNWcq/u5f7T/7rgaxrntjOsS+WWrBOKw8\n+iK1kafjxN5QHXfyi2O1dsHNOMOQz2WqIy/Xw6VR/XXYWCUrdsFUXoHorW4UCrGyb+4hjIjeyCgc\ns0nILhkdX3QZB83p0plOZz9tyOgS/4kgNrB+MJUP2FmZR6Q7bR9ha5rKgtG/ZSZwEI9KmCYA4f25\nTpwrNlm90sWcLmzArkCh9/LiikGn2T1kVVNljN1Y2ER/8Cwqk7scYYpwcRMcn6CdUHMKIf8pdrJS\nSzmhsZbJJ0UNf4Y1zG0DOyipXE8mbzWGoPU+pPxZtj2bpZ07jvrO/JHFcGl611jQKJ0mKMDgP6M8\nFcP0N7zbwhGuB0IlBIqcBs4EvHTLBgTdTaaojjcCvfce2Hay5T6budQPO8heLGunL5/RSat01JMw\n9WBkC9YtCG2Vtl6ptzBvYxLv0Cj6J2zEsMToA42qSS7lONXOedjaeXFQOkP5UrFB/sq2Lx/9jZ1J\nSWNZSHEX9UJ9WHkniDTQg142VtoUiKFOlk8cKAQg/AizhCq+/7Waq3/3LwRljIBhrtqzZNzanp30\nKcpFmjZ28+oBJY5Cj/23AtVn4rF9NOOj84TFtFOxMxn4mL2TAcDtQ6Y9BoRBPt0nUWfNvm1oWbWf\nD/2zyQpwmz34lGUyCw0KinQXjbxgGWswqVGo3pYo7ScUySVQJ6SJ8wsYj2LRbzEJKo2q7FD37TzX\nz9KiTb/l7EsM46llr+R1J1k4Xo16KKbBCPXzkiRpBV4AjMM4IkkBPYoGNU7Wkppwr0PObbWB7Tsh\nJYW4ivi5YV7dI2dcakUmMWgL+YJ+lXqb+Ydt1tBDpwkG6uQV8EkzExcD1fe9FJqP0CzBzcZQjLU+\npPIUaFgXzfet/UmC5Isgm98otRjJ3e8O7czd3WMkHL8piBJCH0OoJbdQKMiOiimkOb0ijL9Ty2SC\n0jdQv2Ua6QBklkBbttQ0VBQETFjQ63Z5SXZbkJIg2FFwUApMN0P79+FmMscYOm5XXPameFt5P2yD\nAwZGQ+rtMZHL0YYZVjBpZLVEeOmoK/meULpXVSpw2RCB1RjFdW8C+FziBqplbIsYNUIFWSvNvCmw\n00+dVB8LVkPn5xM7JzqMnANCBSyjry9I1Jddpa9iAga7xFcssFmu03UzjnW91vaiea+aXONLcpv+\nNce4HTbeNhOFoDwxxm6u+D3MI7GHvNwIDFp87Rf7fetXwYIE8voARSnkN1MzbGCefHUIbxI2kF0f\nDwnA6vGcTyuchZ84CJnJlPNuA2+hYmz1ph5TxtzDGgCUk/kNd1NBrUjt7jzKU7ZYerAYk87HOnQJ\nQOpnJq67j1hQFbO2+5uApDK+vfPncoo0o694cbVKjM2XN5n3NGYIAKoWjJOyQvv6X3NAxGpRvz0q\nN4cPaP251V3Fy4p28z4xBaf2ZBd2OrrAdC3b58C4rPQfgnmLaSm0vcxUZN9RHsJiWrXML6Alo6Nl\nH4DaW1kc/o5xg+KYHULU54avehvXmpWSYSOpVyF0ddvbwAmskZFGsOqWd6g81D7WiwqriSWrSCAA\nSkk+YPYfxlghoWwtQkynZxAr3hUrI567/riG7V79i1UG9/VFL8LeUS4Q+zdcD/+N5M2ufM8V+FYO\nGQ6SpWcnbVtdVDu+qL2s5hzpauwdmV/g0VAB/5gvU4D9WBiiTiHYSwuMFFMmmai+93mNhMstWs4V\ntGfD2P/bC/hEX++ptx/0M37TWgrzAVFGiBrW9oV4ZfA/i1sf4LpVBh6PlEpwDGWHeOU0BMCY92CI\nMLHVOxon+HrRCa61e8KjVE9XxHnmCR1bFZrearnGDBwGSM/xU+BBv27ukgB29xSWIXxBZTOZgHHO\n9dY2BhIs6oBDvV3reBFoJ9MIfgH4bevGyZZjis94JxEEiczhALjK+0lcI251kRpziHBhB6U64Q1O\nT8m0WZDlFiJ0YECVtZ6ZTfAVmWjjkYa8+N6bRBzFjWP8+vxSaFyRBVuDvaHsOx17HiKogLn9n6o2\nSjNUATewKoEDufD3xFbB2DumcIFKXr1lu/NEXNkhSzERbEQQOTCl/Kn449CZ2QfndbpQBeq+AFQv\nFlYD5pMR/4ZT3uPAg63Mo1Y+8rIV59PnPoNyH7MDnnBtynAoc7TW5o8Ot+aWmvR44DG0f/Ljb0jB\nnoMLUp5Pjt+2R6EF2ZA9S7/U15y9jBP+N46JqGgYKapAJ1PJW67KZ4e1d2dhFW+33qz/lFQCZtsu\nqMlG8eX1D6BoFLYS3ngnMJ6EzLB3Xk8XGxU8X2JRuGGYYyxbr7loTzbPJrna6qDPX6JwrNQwDWby\nYQWJ6wOdKxUAcPls2dgv8SrfP0p3IR0+JZpOCM8uELqaMLhFefJLcPp0gRYTslhmKeMD7XTL55Nv\nf83fRYOZpvh9DX2bkAJzvzHdf6Ioo4JPDnhdpOa0B5UwkkWgTBKU86smXnCVgmKucKPMN0ART9iQ\nihx+BVosuKiImtSNDJ7qFVQhIoyOY5Dr5u8wMoQMl6jInIQCdGbHj4VElAdZ20M6sgsjKw9Xiymr\nX2Fo2P5EhSf1MqnZjQG4cceE7q7MM7vjyPCrKF0668XIEusIP9pLqov3cojHyygS2JKLfuHytjvy\n+aq3xHd86h0MF5C94G8qhi7lOCk3+aWm9w2+idn8/5heNpqJYIgwuKc89fOktlolLnCuahoVTJ03\nv+3Cve3ain8Zb5Gyq0JNjhJgGCauxcs+ycN+0pDqCufC4q6s6+QH+3F8BXIvU6yJHfYfWfNP5Dys\ncZG3/X+TO12VutzwyhJoN6Ljap0hAk12oKt067JY3XWvnJKTpp9qBB2OiqCPCr4+JEo7TIJFmFFf\nE0nn2SHSzGCHCCCNdTdeuN3iMhrpIc5ZStECzX/J3lRTXJNMtX0nX2NhIuyE5FrkSojlC0HljbZT\nC4SB9+5vhTetuxonb6hULlaAKV85zmJGFAs1tMUm9kCuuaVxkTHFa3+gMqQpaD2fXqY+X5FCF+uO\nb1puzbgpiioj3/4PN1Bv2BM460Cbop93QiIfJNxiq/wHun3p2ehJBZSsVpVfkuTQ5br5ix+79DIE\n8OHqW4dX0ub6POSoDA7ZtmZDZxTA6QO/O1fT/lPi60MEKUTwnwLfiywyKLMHvH1T3u6nsPoIvaJL\ntOV12Say9y2Bh7/gCjEWEkSlVjZBTgw7wAUqpTgPywYBkk8pngoWVSjiM8Fylr2U2hbQQcwQrFcN\nEXF+v0Hh6d1zxZmIQ07wfAuhPWk2GGM7dNC2WX4Vq9a1Hn0PSsoqXtsF/xJV9YHTbKWk5MA1o0kk\nQYNgF+KpRzMFmRKvhOYTGsOPgEHRaToqiLqBYtHY17somC9HqqmzQWEuVbTDl89eSBltnAQeBZWb\nd/QQ0fuSzr4hwKWNmpvTHc7gH2scKbBrQuujQL+hCPVK1WIfGOs8h9o/sBRyrIrycvezh4T1vPIU\nXlMblAttv85NyWM7bMQIMhj4eZ3PB6INGwgHbEWra8w0u5bj5ra7fzsCWAoaMkSLhENW2Di1oXjp\nunqEJkuwLVS3IadBU74h4OYic7p1JH9C21e4ij/22bBtZcJdeqxHPnEM6YHvTY/Tvy/8j3nnINA0\nyoiRZPiHZlKV0VwumGjtEzMf5QRqlKrT4LRTB8RJ/ghZ8dB7rOsSQtUUs++8kGBzQ9EGd0ItQ64+\nmV8oPrRUEDkQV2+zTrOZR0uF1OziRk7i9e++It+3OyLudpgvjdMvcfLo1Ixt/hnIaTfRQw7MyuDt\nzCH/lRND1xsTHoYTu9o+dknr625OmK7E2ZAPjwhJQvjVZKpnqOhtDaC1VpcKpt0duQSt/rVDFgtr\nB1ryX0k8o1yJVP4eClXy8uncgsXyJrrIgp1GdlZBxZpHUNSMmLdpU/GbMbj1tCMdDYbkWzU9Ywww\nRjTBb596VStUtHiE0qbq7xBR0KY/KMHzE/8wIJ1uQHVX/KyMvmqrop3Xgnfn1QkX8tYYeDIaX2WV\nu5qNGcv0RcJusi0m7Sd+jc0Ah06NfNVSrnA/p2SoCTIojeuU0lDO66Xp8DNIZbT9ylRkP+bLn1Pq\nwWhtM+A/MUkn+8rDsLERw9rxo1O72ul7YJG4yRI8RIopTDO+YBhYaA0GtuGrIqnr64w674psoRnn\nBAIKLo9KTt771Yg1qTjNvfHPbmv7EQ73QHUBwxmlQKHCkcnSabRF7U84NQ7JO9OtYiwHhOVcxnND\npzagvoA7ceGJZpIWVawgyqP7YFCYQRlN69fYGKGUUZF0f8dsi3+BmVKQD96brpC/Au9W6ky1dSRk\nsSOny0QERBH2/KXXMwHfsIN/nsN4YsDbytCgcw4Z9dsiveZcnM6+50GXRSoenStfPkPzn+3XYAoP\nm5bxaE7bO3Vwhi55QKwAMkladFxJBrbPp6KRofWITS2pxD8A5gW4Kkm08FjOF6eFYNSCL8/rlkjx\n39S5Dx93Az5hgSw6xMt8mYmnvsWCglR+tEI3mRTCUenC4/lWBaYUGXV0H33vt1E934kr2lNMkn3L\nXnKFRjKxEitnXT1xpmupGCFWvvPeUyMY2xLQx9l0M/MecOEuBgs6478DjZoDDWI+/jfIVvy6QVh8\nrkqLos2I/BgYAewKgiZC1FHJAs113ZIwtFC6aH7JcMmTGbuZR7ei74Xcs2y1HvMbOv3fl1zjArt/\nrvr2Ds9EVrRQVMUAOu37SA5LxP5X2Dn+1U+SqOoy9ELn5gIvlPV3DClX+GtiaJzLbZFnOfmRzVA1\n91YS1rslLDSEqxOCQkKxNNUvsLRbtrVIhKjT7pw8svP/0njiMuIRAyu9K0C0AZ5Vwk+nW6tfBDPn\nA0nW99CASZkJaMoSrCvIO+UH2kFOyCqHk5AACFSWhKeLXt4LGv+vyIZmOWieWqdcLtCdtIrDUW++\nVZTOR9NC+Hc3z/xkW04z0Gm5uZpG2w1Iz4H8N1Csr8F9wqAGngzBYLwl+aUYsa7EtDKfVHpwa3vF\nCacHfZZ4JwKH3kFpC9sF6sQVAMKdj8pbetgEqh0leIt91l65uza6GQ3flULv1EHkOWP9PHym2bRR\nOiuXRtggTAgfIM6Wj0VeCGb9dnrxOzFGaCNfeM/J9AikZrxtDfBzlOe1fMAS0VGlukBnPfZU5EfQ\nkIgIXMIJ4sGs4tXSqtMD1eLCTiqGsrKGua6yW95gMkujz9TrHN02cZDNMViYyoyzbnBjrDx50uOx\n7BtSLNzpzDtL8qVR8v7jKVVbPu9oYdpjIqOCnrLHkDpQIZgMwwVf3Uv64mc9vAYb3Imi2wfAYoNA\n6QWNKKnr5RSj4bulACfcEsu0BGH7/hgFvyoLMI7+2zT+fTdpwCgLbVGFPNQj4fuqcrfxwi+HEgpX\n7TtdG7cDD6oY1YGdm+CUaMGNPwcSEc/jeUOugRwfYbcijrH3zkg9EMtuq5EMlm+rPp1F7yGqhnbx\nQNCH5FHdVSPgZL6pqX7+9IOv5oFvs51exQv/gsQGa+WlIhNlz/SmSzJa49B6k4o1Jdul14XGCGAs\nDzIz2fja0nTpGAo46BzfoAZGp8WUwEVfY91Y9CZvI6j2Q6aVMC7UNeVkwzz9q1M/7m2G1qrqX425\nNeVTAGpnlKqejy0sjfn2zqsS0mE+8RXscDP6j+4CxhPsVmZEQDqtiYAhmMB+RfVVBOylCsBRv6ow\nzNqlXzUDL31p5lg1KZSTQatdVEKAUKhsFPBi46JCCCz2MC0Dshuhmaz9GpNRIhX6hQv43fxT+k//\nX2HZpFLDbkjelCSsQ3/Vq1nl1Xnhvv+z45aLi6UlEIuDgdATN7bQ3PzFD0dtW9A5raxufaT57ABV\nCy0N0bJln9uFlHrRAwo8oZraS6R45Ov0BtrkCCttFf1AvxEqDdPKCNMjuvuWglM67w6ZIgl6UZea\nV9DuzjT22K4v/GWzMymlX8eTjXnzVjys858VLNfbqhk90Y5VMa5R/pc+8qSvD3cgWS2qsfOlXd9b\nPVSjs587ZWzLf1FuZBZwqJwhL3z1GOkB0Dfh2jS/A3FnZiEXAKrIVLn6w/taKROg4EtSSj6N6pTr\nCzcEFrHaieuwFgM9IkjGbrTWQ3UDh4he60f4fMn3aPquoTmf993uS5RL4RPojtDZKjF9VBeVBmpG\nKAcjdbxtoo95Ri7oj7O2OQzTEA9ZQTS1cMavbalVA7+9pmAyvlU91KFSHBKNT40s9uBikPDk/BBn\nDAJGPmcLQYpo80GWvduaSADO3iMBwQgGxPndGJ6DL2OZhr1nnYJDgZWuVy1BUaDCN8JksExUzr4S\n+LhIlRWK2zUZ6tdypdBEKm9o/pWQBb0l98U7i39vTJLY7DTeHQkabFcDIHv5T9+fGH8BGUWI9jnm\njnuZ5yGWG4jzqxE6EO0vbGM4TLDkr0X8HOLPOOF0ho5vaUKLVl6e70HfpOK2xJ+p0WgEVFmT1UMf\nboZ/1mJ3TJ7bhkWrAcgWl5tGFOlLvEIZ6fec0VgQjAL7GhXZ+VfIVu4VyTOK1dunLCC8hqIL3Lvn\n/T3m9WzhMAuN/XIsbi4jDY5yZbfE3l2OemHPXojNr7uubghwmejFEB8XSwF4ZlX77n8/bm8FrQcE\nyq0YpZLpp72FbNyd8OHByR4m5dNqhRWKc7s50zcorDR5mXUV58WcWWYBVTMFgbOHrFMqadMw10L5\nHaMrAWxG+BIhrgzjMex4QSjiQO/QL0xI9b6PCoyDLIHStAZTpG35qa6rK5sh0TsyEjolFfzMNPLx\n67nI1F+FlE8Bd80c/jTZs1lM6bFLSaogjzTgxI1mzycDk4l37nzz9arC0WyWPj9ehmGOcA+H5Oai\nBz9BUDMEpj2CBzbZzgbltQ8a/uhrzdvMvm9ZEUrd0ZokRzhV0rQum6yWBZ9G+sOJ4HMXxvZvwuG/\nXSGRMrish8zvGiW69VNbehLthEFxX0YnDpojNqIx4WEcbwg4+swSQDxFbIAxigESj4oJsCapZBT4\nKh2YPlBDhPJ/NC0cbWVpmAiEKm1B9bLeVfv+YfQkP05VYK4EGV00Zo3GPPlGNezPG9/mStUTfh8T\nyKT0qY7QrpZXhweJbTUD1HQB/4ei1o8FLgTFRzJkRI4+ehPFf/ILrIOiMttbW9cpXZdnnILsr91x\n/B8BwZdvrhTK/WZsJkaBFfRD7+of9Lj8xNPYhrfoBJ8cgyiEI7lyzvx57E/Cp1JusL9RltfkGmZV\n+in64LS73+ZK5nNaytFUtzWyuRbBGf0Alq1doQqceuzVq2xfltsG3VnhTxQr4iz8QU3G/9oladJc\nVcYozX1z04nr4DGW9cySZTGaOA/ntQXn1TTcVuM1pW80uxArzDjo+vf8eigLN9HSwfDUJSW4oYZ2\ncKwn1ujHYO1E4h95PMH7FXCtVlNvprOfN1Rjf8rgAv/1KVjQG+4/CY85+H5JnBBpZUOor/4mKUqq\n1Ql6fpsUfMEZNd5DTXCQjb7bzIHZtmgQO6lt7GMODI8IWG5NmxDWZZ+Dhan4AhcJi5aF/DXt+nwi\n7yLwfztPYksRAe1y0N5+xdXAX8r0UFUo1VxVCNnw2CowufpFVsfbbMVtXVdPz9pMKmrWWGf7j2Vg\nfi3MgSEC0HqK2mr28cfh5HwgsmNsUmbp2e9FWgWtI6MINQflkbCbhxt3QMb7TWxhPzTREJuEJu2N\naq9BnucGkuvbxQTdw1K1Vmp8WACqJkWLZ/zfgKfutlhxjyzkoFnbVJ6jHOw/dnEu8VIXyOWEIUMj\nk9QR1cr/VBbwQO0ZBLKVkr+G+HflEEpz0lFyW5l0+WNYUT0tAByppYF4bjCVem9A5kDtBnZkzqhX\nYRWreG1yqvPsTNKmHrVdUhAnmqaH5wCp/8lb+hsSmM/q4KXEimNuHOTnKqm0UvJGR8Gif/Z5Pojz\n6NuqOaVOhsMunAgE8me1fbB6x6dpkVKN/cEPTMMBcGpud6AMS5nUR9kf43D73HVxtrO+RNwNyVAO\nsHNvHCofam3BzsAJMaToIopO3+IXTyUZC65ui9cSmBdcQCfJtwQSQeyb4sPRFHXZI0yp8/9YXww3\n88Z05hIZYlsejCDfYQsEBgXteujihH09iUThuO6bzevrPiqBmoqfw3BUPcF0pIBs9QyqcwfCaDZc\nae20oVkX5myqg9ziZnXCCJTHt0ZTPMNZo3grBNkgX/EZgZq3CuVqS9T3TFKrdDAI5QWEpQ5Mhx+D\no235tNBZdsXYXPFFB7NJyVj/GudbWcc6xksWdoexHNt3PiWredY2SiL+xoRm3Rh4BU70q/wyzKsU\nq0ytLE3jZBt9bOGecfKZ9ye2pHT+Recff+D7wyCSTtBvL18v0ncXOkSYpeB4J5Fu9my2DfEBiYao\n2hl1Rym6CsBlMU7f0bKucx381Pn27RsGgkb2lZW7XaCZIpI9Fn0URrSkN5aMCJ2K/R8dXf1fMTJ4\nl0D8PSBLP59BV6pQThYyF+Vga95VIKYNa3IEU8A5OBK583N/2mxmL4YWOuKFwtoDStbbecNyFeun\nNGhxED3oOLdQ8MLcNJRw7FfmFbnNInenXokqJjAeptPTNwJuy1N5t+EXcZRQ/Ds+yezGL0UIWOt6\n/LZ3SqEBT9TDa14f/R4+KfMW2v2xwek6EcylDx4U45sviCxx6RUNnaJyx/T7VigDmmAFWrrwSs6c\njt+lOaknwgius2vqCJ0zyz7IuhpcFxPgOdV/jst47jUy0dFHa+KjDNufiUyiQkvD20kM5EWbTuyr\nzhRI1xQ5HKgRgt3cjKGkiM97jVI5gpNFPlUZ4cQbdpouJ9oEM5pHB1oWKonGTKyYu/p+pp8FYn9U\ndrctPXmxrj+MjzPGRZ7UMtw0IH2EIxJpaUBNS8Rf6ZNosVrvZMW5mHjOHDXzVNZkJpcUZ6Iio4K7\nW7CvIC2gJ/hHMY/jsrQeHGFeIXm9gp6Eo4gCPJTCG+c7jvTICnibreWOZiTJh8iSs6fCUAYonkZF\n+Ai/lyy1jA/NLS9kqIzNYMeur7nzwe1jXqo29+wJ3Ua7dGIGZNj57wIHp/tsTo0OWpHqIKQ86wpU\nN87mMZAF7cBSOs2dxPYTJtd0XY8qpOmt6SRyzBMHfpBjOY8OSYE84CqUp76xCOZdXH4Ulz54bDEL\n9/ROCFzicPoCspHq7d7QjKXUTkesucxqIidmbgMybNUKMc5p1AR+ZE1JY5vtQN9Ncn0IXiVXHzcb\n9SKI9ih087srVnacCzL3GJXVALw2qidMe1e2aO10xBrz7iLtQHGl8QZVKWLfszGnRmt7QwjiJn7q\nfZ5mUMEU1HHtwVtzZd52ubvGoFsIpWWDgPJnKpS4TbkvUf/mgXqdg63I4MKh1ZVFtYN9w/YDCo6g\nAuSVkYD0iSdDFIyday3qwY7r9fGTjPAmQ3muYrj3pDEkLFbk6TC9ET+jtpE3BE1tTAS4lLZyXUgU\nbQOJR53SY30Hmfssc5UsxQ0Aq+zZX8zQ8aWB3BQVpDjZWk2pDHkcWjqxH9ghciynz+xjjaQYxUOo\nak5F3zbfR7GkyIgfR6dhUCFz3oOXWzD+FjrjdrOarUCSl+76JWtRmghDIcln+eciDsEiutLIIemc\nsaGZg+GfBdNNRfeYBIjy0kD7CdbGAKp+eHCvOtZ2JcMN+EDDgiF1rxmzl2t30forWmltfT1AOcx+\nmeW0Ax0HTDmcAdM7A1rIxt2iInFhii4pYZONfO0s01ORqeQMpK4fMXBbBeYYW7MoM2BCS/Dhe+6r\n5+UOHBMT6EaONHk33vk1PQR3WlFybU7fEsp+ejVlo0f1hsFNvYXmv4dXpdy9OKzZdbigD8kYCnfT\nv8Xuo2kX7RZMRiBll57mWA5M3PXPE0p398m8XJO+OncO/yJGjU108p8ppj+7PANICMKppFCRNbdu\n8HKXauFGXJaA4soG4COKfW5nL6AOo0FYr4U6Rl3VCem9WlNg0AN7q2GOrtiuC1RXMZ5VshsfwAp7\n4kN6ZUM3916yNGzJs2aVt/mLYMQTY2YJBootKis7LtQdUIbAcHukGraE7eD3R7YCN0b30N+KXKfb\nrQdq+XD4BzEEJr3CN891Zb2FIWH5iNSV0HmDNjQ2sGotXpX74MyXWR4Nq1Y0dMuNKiyGgTD8iu4l\nl+2HSNaFnJGTyUBsMfUM9Vm5aDZtc2Ut+B+HE6g8moTcROFnIEMUwoWiWot9FFYqK0Yu9YdkPnX1\nABcFY92C+TBQxzdngghuGwyToJJzdZe3wF6m6WZNm08bkBN0reQSBPivNeWU5QEsYJlTbZtJesJ8\nyhTmewwKeaEBwPQuwwblZpGhg2jN18K0WK8renaEA38vGbZ8cmHe77qTh4cbMF9fPztOWwRJM2Eo\nIaR8aVhzGng726QkbEUnuLnJJWwMZ9DYLYKEWUPC+V1eMlJkfvFZLDr70GY8aLtnzJ257HZiByV4\na6GyFz8rOBXBT0rVyTOWV9flQg3ukv7tl0jBlxXJ0RrqkXQNicwATa9C6n+PeScAFfe3p48CTr6w\ngtUKB40U+W8rOxHIvyRz4qYPQJQ51yA8lHTzc1hRhqgp+6+/MUFSrgXz3Ya1S6ws+C11Smojq/2N\nJtPyWqF925DxlUn6XHg1CPm4zEUn8UyY8ENjFvY5L6Jke6XULpQcT9dR6MmG/8uRamIboB9iplqw\n8/Wing437bazVuh4lAR1Ck96P/ofxr1HmCRfEPjISNIs/tByOLHEYs7sudrX3wYA4qe+oj/j4KQ6\nJH9NQGcEoj8WFV0Lsmc9vvPHmqw7KO9xOCRRxSdu79QnOZjKUYWWkB2mqDDBDK5QO3qei9t3YqFL\nV1cW5xUZZ+zWuck5o+3sAdPZAlZvDwWQe4mrUDRkgsaX6Tgti4GG8RvbNgkSPV/gDIKlznnnyUy7\nZW5b0+mWBOq11l6/cMQ40ppVmT0CYozrwD4SHB2pYY/xTZ3gwdBwKI4lkAUpegVKG8IVvS16ez7m\nAlqEVnHP/dmfBLor6yh7unB1oxmb5KAwes+SryBHjk+6BUXR+4oTtXI7E9Zx1E8uEUGL9IBpbck2\nOAOpVWsOwcoe8s4lq4yJIPj9zPLUS6YVfn9KWu84NoOcaSwORLNf4SaV3chbi5apWbhutLVFaHI2\nAWXsw+5M88HBdRJ8KexaY/tLFhS0LYjMiA0Hp+TJkzx5N9xOJMixZ5NTeZzlhvDKidQSI85/e9Id\njBjZvsernYD6T8Q/W6IGKVGgA+QY0nDwAXZb0CZkbr/5+px/xlC31JLCvHvN9Jy5dKzrRjobKFFn\nhXJry1CJrIZ1aF2MF+kIO3BtfVHsRKJVE+0cPimeX8nMaIZ5et/1sEcJbs96Hv1pBw/ZprZqf9Ua\n0XCZNHXDoYpTivM2Gk0jO4d2F3CLow1WgUTBqY9YqE3a1vA2WeNtRWunC2xCYMz473n7AbA7PnFg\n/0xHKL8AG7GXB/mdWGgIEzD1u9MKH7sIP5+OyDNDaxzU3ZXjham0D3S888tVPRSxr7zluvdR7gcB\n3QwKxqfm5dj6mDwgi33EjLBJQqKHNTiomAstQMfcXxpOdnsZIl9KcN5yUiUmdW6bH62AzeLmxDXX\n4Sb8+I7kffNlW0fP+gnh8Yh8hgTC16afQY6PlGCVFcklXAZnZw/1esiqxOFHmBFTnEzX3LdToPAd\nC/jdp/K8j7wS4V3PLvMkHNynjwCgT3k1T8ezulAcq5l9Y9HCz+FHDUUjMnXrKRMbZ2VoOpu+O7eS\n9BAVBxPs1bCzpE4jntiLXWa0wF7Wxf+x50S5qhACY8k8NB1TJTRvS2/nQ+qxCkvcLNoM1lKQsOmx\nnwipdtDL25mm+13qLfvMHsUf40FmhsekJtG1cBJc+yvQ3YxDB1yr8DB8niiRPEbhHnRcjH3ZjMkw\ndV3nJP6eyNAL78d+notVZtMoGZpCKILIGZgFweVKQHSwyqFzYjSBbUoAB2s/jkt4zhmW7eTlmkce\nzT9MFifCSpTF5F3MAq4RTH+Pc4WfY7mognW9myXcrhsaXQFTrvIZ2qDVzbGHiV2Qcb27UyAzKtZL\nqz90YdMlr3D3Uiq8YTjh49aNAoX/vYgOXSWqLgo16JL/USlKpG1jDtLnAlvLH+dlHFNA7Lb5y3Sy\nFZzAe/0v1+EJ2k5ri0R1yPQP3XNIWXp+R+CTW8YtFfr3qs7UWAsRe5MEHQYhGKjRw4dSXaJKd7lT\nRFGXSqhn/WK7x3zybQT4Q0fh8YnRtARX9cjJ9oyl6bswXH/yal9od/kjkFIrEOUtUNAPKeNDsh3G\njqm72R/t5a5lQaX0L2VbOZl6RsbXaF8aEdHr0B+tx3ZqcLXN24Rc3+RkFxbj/MbEukkQYsEh5pkj\nJyNqJAlRDRYacnmaTpghbUyNtwDO3szeQiouYXAeG+/4FHJWw+t6PwaDvYyVJCgud+Ixyjya2USq\n1xAku7IHJG4dKHPOGGnfC8fcJ6C7eULIhR3ShrOMfRmtIMR2Svm8vHwpomjvE2u1YnZSn+2Mmts9\nisM3kvr/p/if+klDKZ2WkDTUcNNqgwHAZKXpSXPg/hdTIsRGWSo67MUhLJ2rqkJB9Z8Q0oTHS1PA\n2NcSjlcaQxT+JMmyGzdOjC2UeabPR+uMqUxm/DiICKOjAUAvSnU39n2IbVR7p7Jd51AeLZN5vj2W\nWihxO0AGjCa/YRLsAcUt+c+xc+28EYrYoKjHMYOxTIEDHVPXU/nBHP2oZwy34w5BlavKymlN17E0\niUvJ0QT97kdN2QUI0Q3MpDQKYhQQhPwiiuk3+Rbu1yhws9lGO7QYJ9VoZviL6858pJXKmEKXjoqK\nO9OnQlYsTOQTOUC0w41jqg9MpAN811M5x98FKsMqKsoCrHpjYTeCINHWc+hSjgS+njuWcCeBTn9I\nFri7WEHIjlX6XdfW+tDwrn97wvDzbMP4ImSmcrvhyi1c+CUfVF3NIiG+eIuKx0OmRkw165JGz62B\nSL0dbWH4ETUZ0PiLleCL1LPqhVgBLcesuUHEoXFhycGcIFgbm3uiXPCLYOTY2V06Ku3Zvf0cZnn0\naJdE2NKan6TdcDbBfbrVbGkI5Z1txRQm9OSU3GNXaeLxxa9mtZdPT2PbI3/MXq11xwXhYBPIQRqd\n/4D9nDtgvAPDvvLD6wyffLr/sbkon3R0OE3nLOW+Txxjbj7lURwvWCczdBy9uMGkbD1gIm3GQ6ih\n5OrdrU8ZsnckEsiLZBeLfKNsRqe3oxkB5JOZzh+R2cJgIKcf0VAdb/oYyywHVEX/WVzKSgo83IdX\nV8HvgttARwCmQGXjGcaHRsa16vFVf9wSZXVLwNmyczWI68+RlselpiMvZxLmbSOZZLdoSaVuUW4H\n66zyMjWUzoutZm3Wg5MlPlxUbPrnJGO/ROurwTaqkP1NNd99uMwbqKdg6tdmA6dwD833d2mRFHvg\n3Z1aFU2rRlpzZlAQy83buIvTWsGhtgbAWJTNFklkwOPieQTGNIal44z4+5XRopv+XEvBtfHjk+G5\nbN1tS3BJz/BInN402OPL/Kvpq/P1OdKZbR20h9v4wjVRfSxqa0X2BxLXM0LJxKUGDF4le5vURdG4\n+s+o+I9T1ftVNrDPSbEVaQbDi6H2GYAMylg4xTFPqMVLSX9bySDI6h2C30JcFTlYW9G9bSIfWei6\nI+munTSCcL3Hz81R1rVmDHcFCfi6jRjncCTMNMV6fokUJxcpdNW1byg3yfYmx5gD4mh57nlDvT5K\nh/q267bKQseGDbwbIDFBymnbnP8mEDMCZTOB2vCPA2dUs6+ftASy/fj4KQX/xeAKM4lp4TqcC9Mc\nxObznRe+E9PZf2M91OswNxeux3XinRCX18iHEVbgXmkIwv9c3QPTIYLTfFGO68xzbrq50xvx0Bfd\nUOSlQaCOa5eQS1UtZ+o4mefgvXXlJQu5DlL+Vu9dReX7B5ArLZnzN1tbUEBZyosxXK/tIx4ndkLM\nBMEqFeUgk2EG2jIwO8fIm9aowrOuUEYkmJirq8adigIzb22FzoX7mPeWVJwjNQoaIANoQXJqSDhy\ncsXbm6QzaV6gChCASESeKKYHwlSwNWKZXandtTpsV/IBxyhmpvjC79wQmhK8vgMYv9/9+3sSQ5N5\nx0iW0J5FzcqZ17juvkNAB0Sl8EjFrTwIF3cWrEnsE+fIPdL6iKkuTFjtHXCYmgw38JVmE20PnD3F\nOf80uiyzXhmEFXVoZQ2QUncyN1SeL36CVVete6df0kBUnk0Yd7DiMjVNuRWdxfJxWkMiKrC0tYpP\nrx6MKRXuHe//aVMnAKvc3GXi+6EIvwoZMEl5LNNJ7J9hT0fvwrR8JGQmudjXpcuhgynAwhhok5mj\nFu6dskkDVA+jzYz96AJf26RH+FGl8c2j4t6IRRvMhUM1ChR/7O4FWWfMjKY81Zfm2RTdqpPFeF/E\nHCg0N2zaY4V6O9RATw9+OANpLNJvaDubMjD2/HS9wKODP/0gavkxdaQg5rv+G4fzG4dRwXGHFng5\nkHRxOBzvknl0f0KnEM1zblFGCcej+WjYHLZyC1rnBP+qJxIFmrhg7RgDzCd59PPc+wwuXqSQP6yM\nZAFF3tQYAyP56T4L7vKAXehWehHDVKkxg+f9hVTnzRufVQpD425k0BE4t9BQNAVenWnMdWyhY/B4\notNH7IZ4Ax3M3IzOCG6gKY6quIFR68TpCztQz80IqnvncjMDOrP3Ob9mEYx3p/ZhhtYBWFJhn4eK\nl+SqvqsS2vFXDMGfNUsF4AN43YqVFJ8LpUnxyQ+DFqCu3YcIw0y3YISB+V+qMsG/a1lSUZL6PODd\ntsPiB6yAg+2lo4UHIEsbaNWmfsascT1SZfbpacT1GIiFyJl/yEz5NrPUu/ftjRBaPsxCXAxCjue/\naSQf6KRVPpcIli0JKmbA8/MLN5fBLaOS+ouIUTGSySa7alZ9Og20gJBvMd6VrfhzDLqbj73zRZzr\nl1xWm37bn4uxTnlNgREBQ4WHUAT402WpT2Ot+L7s4J3+ykPAXta/OuwwlxJe0f27NijwON9NNoRO\nmqDe5lfvw5D73ZypJTGw+1Rz8J6pQOxFrv8vGDWGPckDxCX9svsrs+jqcAtyAwDT/p2DjJChVPvA\nHWkyQCtrBPjrWa/HqIVgHgz56vmL6Opch+UF/wfFTEcVtMqmYjGF+vbsDhBoI2GxKVRudp5xxAXH\nLDDapai+Uk1Arr9/E0n8cT11pAdp2Teqqsre/imG2d/JyOOq05bAfc/SHMf4KIkLwnkZ0VW2jgp/\nMDXwmg/f/jMvPzD8zpdss0KyxMSXRkMNCiZ59KUkwZPofn+JOutVxXcnQ7okytQ82n2o1OcgX1N/\n3j5iGOg/PL9hcFOz18eXkZNMbzl/s1mF5xvdUqp/1bvBP2VVj3VrGfP1ZPXjrDNImV9jkEVI5OJ2\ncW6DFKa6KerFlyJteaci5wauf0PEo/WfTB8HYwujiAf5yIQamfvyw/sxTD+BJq8TF7l5JpoOJ1FY\neGhaqiS6l4but8fB2Ag/iHBwOUj4vur85B1fpl3yCsRvINwXByA4w5KgwLMg5ZTiSu2FQJsB6XwX\nWxSuRldO+DVljTCPr2y4Dq2WxLMRIs8qGly1Yl+rDjCJzvNYaWE47Zt29nYq0kgvFAJhXaaInVU1\nvZkVsqWy9K+wTn1bet10FLC4Ky2IksnfEvYx5q+QdoUPudchyr2tQ2/2BGdoetoCXtvqCeEgxMn0\nQzXzGT6b7O/RU1yac4oF2Zrbua8D4WPcOY+2nmjny9YTX7kCawDnNLsKodfxcbE2We2qmJPkyR4B\nR4cnMZO2I+FlOai3lKBDWMPLV5eg2v4gnly5WAfVuyKCAErZqslYpmXHvPG9wjmP1yjR52CpRuu4\nXh0p2BlPNkLUlje4revMGAS+/nsyQYFoHMXSlVl7LycrfkrDsNZBfZNYDsdUHZtnle+iI+Mz9dKY\ndJXu0+afq48lQVa81pxx27gAksfkzBP3q6Fv/KZjMs2OGhvtaORJ+K1K7CSWPk+ZmaEZ5cvAXbYM\nduevLS1ff0MKIrwtTgnj6gQPZtGxu97ns3bbbWarA9Ef7WnQh+jfPYlvqMFVw6ER3yDGBfhwqCxp\nAt7WT3ipWNVRXvWwZ2suu2CiaUltERJgebulolgepy3Gf//GGjGom1hJKDwJYpNPP4e/qp1sEYMh\n4gNXCAU+7UZyHUgnk6l80RJJUbkbOOtU5wMcV1b4geWkJ39uxN6L6C2gdc82WyrAZb5bcrj2TrjO\n9IxTId7KWVJRh9YcCx4iWB3WWOANYEZ4HBt+m8UPah3kRX2sa6CX7gPoPa7iXHC7s75DkY4SXxR5\nt/MiJC+MMz+ahP1zz4FaZyr4smHz9CwDoykXJu2UxdvnDpoJxXBqCmkG1/4wimqUeWk2Zpud0Gc5\nN9oVGwchVIIhcgzOLr/LexH/reFbAuQ+tfY49MIL2deaJLsUpkAD4l7V3ZahixkjQi+owrFoxA3p\n0qKFjCfWowkc58u1foq9J7NbqN8eN/F1Yzm5Nl1Pm7lcJMGpOc+UPyHtGhwmu/H4DTPac63pWDTM\nuo5bH1gWgcF3B8hB3YnIUG3UXXylgEy/djbUNZs9xnnPFrSIj1tWvmFCbegyUx7AEWzbOvua/Wb2\nYZOkeeiOE79SIRzWpAQd7SI2/jY+z8DpQBlDio0mUa9vUyNO636/68Drnzgss96TBYk52A0Ny71W\nkMWe7u3PIxEkEGW85jYigZPMxt3fULHGHJjqp8rU+3Cor2iuPlka9afnpqwNRNcRhnJ7lMnsHJf+\n72TjZ8VJOhNFS/DMHBFiz34jZikaAAtmSpNyR1S/aV/Cy+IpdsQAM8tUv3bDnV+h0uPYpUiG2EWB\n+PwE1oxOc7E8dtpBQUBuT3TUt4gLm70ATu8f61duOuBx+cKbdmR8NOajjtHcj7hgOt8iPpw7aSF+\n1ic+2fwaAYf1yioUT5dZGgtbeU6kmQXFZwq+lrpkQd5aQB7A7V+m5uqaU/V2itGnHZqVKNHH7cOF\nCalyow/SeUuZEkaAW96a4+yTfIHnP/l1/jcAFu5VvmB3cwJRyY9sQIeVG7ZOkS43jSTNKEywhjID\nM373D0NZ++/Fbd0ilADywsYLOnskV2cRR5C71Gf9yTVjw4gWH60O1eL2eoEkqsHIMSJjmTo01rE5\nJ00Jo5EqEQviJhCMdp6usOHEbvZaZytZgP0h/0HsiGa7noDog5a98Nm4QwCdcNSYgY8Arvn7H78T\nT7mdPsmen2DoKBOb/0QIuR1kpvjM1Ga+PiBSyAtiXhK7ikZviwapiP5WSc4ImdC7fonopg7T2r6w\nYUnVHQbrOIOviffI0m+Gf7AFGlg15IvmGW/AmQdEYSlT9ENhgPq2ZF0A12R9pcjp5Mn74Fdo81v4\nW7w8PolqZ1jS5daiVhggLzJGwM/uRcJQTRPU7RBUp+6c4OWTHXL63P2sT/heE92FI+nKtZW8M1RE\nhstwkXUw2Tma2VMwdi6RyjWzpnVaCK0VXrR7PROvEAmMa0zFvQNhawZ/yiybYHxxNn9oIUrWLcdN\n8KiK09b8fvzq7CbHIDtIJM1N685UJmgeevuG9cNRzgYWPmyTFyQ0G8iZXfS9/iIUR4R97C4yAQCm\npIimndOxdU6TCd0M5nmNSvB3e7X8n514d9POHycc3nM9mPK+QehgU+iZ3MbiBREJsolNOB/bs751\nQ7H8ZuNGMeEmXoYcl4S7yLYd4ecRqaaTfKNGQNpFrRvjLijdEonQk3BthuTHgmWPP6pTxA7U41W8\nLhxzQ4oVlIEQp1zxC3fF79mlv8bR3Mc206PI2skZx6alZGDuBcbtTgz24DcsOngoXYAXLbBUHa0H\nXEDNIEMeFWcYY4UnaOhwlUmkl77rSj59oRXBl4m6aZjJ2I7AbsgCW5hET0THwhqHSkbqGNeTxOBi\ni/kdYb3DjkD6sHYt6egVKu+d+P2B9qFqlLm/pgf5qwpl6Wx8Ymw22B10WjCmDLDKtcRiTwoIArca\nRdHX1MuX50sRV2liwFeKVOyjjYuyre3Dcas2+Au3TSocUDPsvJlp+hD5hjjENOoEeYpZnSzGvcbu\nrNQ5YHkYH4GsR0EpsjvcekxF+Z7EvWqIrMEek5Oy+73BmvtLnk5e9asF3S2HRe7G6OyMIH5qmkLw\nNI/1SOJtDOF08RA99Wh5W3PBNy/26ZAXnOJqsU2i4wZOjvHYeRcsc/Hj3b9KgQJVYsEf3j6fZdj7\nX9MwDHkR+5rR1G7x6J8nQnJzTw8HKmfWce+py27VZnXdEgh+UJUx03OiMfbhhhxHXwqWWJucqdot\n3lRMO6udLBQojtKZN5XS31NHH3m4ub1YMugqt2CWdzdyBcYkf4xc3ClsBctE7ieWYsbzrjiULuYE\nBgJzX1HaBqcbX6Z5a5Hgh93v5Rhrq5jVSVjcMx+4bB5dxquqmqYrzkOX0wmdPHSwWbyVjrEKyS22\nd1n+HM0Gc2uENYUjWEIRcUXgX5mOU6YMVi+a9YdGNxK8mDPzYtU8Tt3VyfzHWoxrgky3pSva5Kon\nJO9gxLRHsY6QqVpwA0VtQC7Ptdt8mCV9h7sXwZWJboisQnFrlrVx2CHbh/Z5I2EnYUt3EqC+3RIU\nftLJVfUO156DBMXdB8juje32MN9a+HOGxU12hgh7SmGErWORy1DCsvPcLC44Bv3bpSJom+QLTNwB\n4988rKGpHCt6XxHB0OUDdaF8uhB/aGv4WzwkZof9NAWeDiHUoiHCATuJiHIqe6C9nxh3Qrd/x7+9\nV8dE3o+oG9Er1nGGZoSWoOlWFzQh7cMLENLh9NmcLSXixKk0kcg7BZ84UJAjo6B4SC+XRznfUf0i\nJAeaUfWH50VeWsZ7paxvUHQel4ag0l+PyxG6LHUdc3sR8EUOy2VwAQkrwLWA0dbScvdrvxBTJ2EH\nj+EHcMTiq/MxkYosvrrV4APYQfTDETijvzF6oU2UXfBUkR755gGIR2bB2ZkllqVdBWj6F1OPXnMj\n5nIhvsC4KmAlp+AIZu5Mm4Fjl5T2Y913oEM9W2dNRWBpZnCpSlJGFTOaKGOwXLsCsDI0ttYnT+VW\nCl/chcDr9lEwvWHnOX2sGdGGqG4sLBNjxwTuFfr8ot1Z2fpgkWhhh0yDXVqWRiSQc3YglSiWRWR6\nFXgLV+Xkjmug7ME+SYGo5zt+JKBhbPDNnUYHkHhSOSnugvfDysKck4HgadP2F+ia2gIQeSLntQCR\n+OjnL7ANhwa4JoUU+110l9FsOuCuvSlTQwqlFtQoJWarsFFQ40lJF1J+UWaJfAiwSqcC5BOmlKsL\n+KZjydkRzATJsNpJLsZC3oI6ENoHTC9tq6Vnult02om829nJxRox7ZHcHrctlkoemhw3+pYEzdXK\neGqzVJgvP7AUBQiy8OH1XShWmkwxhNeuCH7aq+Z0Y/A0qwrXLZPF/+fC4y33xAVl+vMK3R+94GaY\nv2cGxpylmxp/Mk+hDlcxxJWHQXBWwkkAiWm8/oOcdycy0S0hcG9fze4fShTFOP6w7cwkKBqs9pac\nMrZ/g0Q0c/GgFcW15Y3zrHn8Ptjq0x+Z7aps6lPbV0y84kDvNeSUSASG57zCRppDUz9XuuNipgWQ\nJC6db1dN0gbY1dlF5ZOTTmm/XxGnp9XVOgXFvDrvgqbtNM8+deZ5qcqfX/Svth69LWW/O3JB7fyJ\nXmNtdZNyLqVW5eJV/GI3E81KJUxS0umCx6WeTxkrnk33jaLoD8Ek+jA3QQnxxkv/OKW16C4vRfaM\nai4devyXFpOEkzXU75lHv8yOZsNqZl0Xzrv7mTkDjqLWHEPGFvz8t19qP3MoUC1qDhqU0ITvKG0a\nNLrQcH3A8BUOp81mJs3zrhlN0FKK+vxi6TcEBLEuIn/epdoa17gcs2EbWXJvjRxxVO+8lNhEibUL\nBUJDXIQM4ANvzAk8W4Ja3jjizrw/mPqHdm8Le1c4A2B6YozrIdcPaDSDWMlVc0lLXpU3AqQ5AZF6\nzxXltlVGg2SVLtS6EqWU4cYL8EK9eZKDWGgXfrYlKfiDDizYy6xJNc/3RZswqG5Xg/rwwYL9ji4D\n8yZeOu9LfWHPojnwbLcPdo/GBQL9jYrFTW7dXXr1BrHVHAY06LyaDeUgWW8IcWnz82k7L/8pTAYx\nE9o/926vQG7U4rIQTauEwJiHh09dp9+uAoC3eliiDMzW1WGYFXic3gq2QHaSYCDeqiwpQX6k8hxF\n3eBi4NPqj5GvOYtInWEVpIq14GiRnQM5YgZAfgLwDYXLo9TcP9xrMh5SMa8jkCmb6mMOCWrcS7x5\ndkAL69T71vL5GJEGAKnj9IgQzo3T46Rxg/+4366gUNaBNn4RDy6NX2aFJYdvKdtGI2wbVrpnGgKt\n6p+79thTRyFud3oogVHNnsxU3as/IhYnTZQ+dzSWVo037u8x21TEUULIsyuVugQZMA3tSNmvXy34\n5A1rDFD1M9zjyV9vdoWL3Um7sonf+0gJsp/Nqad6HTdbthbchGdqzNpyLNh3rKHNCeB4/Lqema5v\nF635tUh3cR4fFX4ZdWJCsUslQ4/CIT36hQayE4KTkTNmyt5Akfy/XFKRQOGAI2mvpH+S3fGc63yw\nIX4ZnBLAi1pXqzN1OviLYgA4jaCcZL89FqqvXAbU8uEdb3uukW3oAp7zxeJhkKBawDBJo2E1UGAE\nRBw0pxkC5MxhmdwsgsHb1bepDlq9PfK21FLRQwxRjrYiXPe/ut0xFkndk760zu7B5TQaSMUxlNsl\n2KCej/RcxyWROfO9AqSGmITV6TeYfspNHwjIeN6Lf+E6Jp1ZLe2l+s8ab802BRo2YJgQmUgGShLG\ncXdMKYp+B8ad3upsilhnxtLq4aY+i4gkM44fBHe9VWcAJRYDJSp7TpVwkE6Epe86oT8VjkIuGTrR\nTEXn3+oIi15Ie5d14uLNZPGhIZW9RtdUJot877/44quPRp0D9vuieS5p5jhJyntHkqEdst0MZrE4\nmAb8KYCHP1ledznfxy6dHPtirgCrlhgDP0jCkeYEEVXyrWy3u2ul1uVfUlR8pgzskepWziE5Cui6\nrDRDC2H6u31fin7nCTLgzEiOjMh1rLhgX999ONnXa4Rt3Cna2xNVXdB65uHxhNjQh1LjjJJWafRo\nEIiwWpvaLbFdsWEhznBy7HKunbkDFJDvg+aj8E13YXzgzRCSFIBezGB6RSJH7CXB5bo7d5CKuh9v\nAun75YBtqRDhdA+bU73SlsfjyyB6Nddi0qCsir9lT6GB5ck1bl7Bmpg2dWS/jKCdXT5GNkqtIBDP\nTYbQs446811MHxyur6HVrF+mg+S6TbsinwNxnkA5hZOxVRR6rHquTUbJOanZbg2vvMs5zBEZgr9D\n8CCfP+7qDmOrTwdkb5LveM+obgSJXanbTqarX9RofpFLcFEUESGUVul0ZMoRKcvXuvLF6Ycm2o3l\nIxA3OZV684Jc7PbdA2IZu7ZmY5VHxbsEill4fXmhQ0BV5oZg7UCv/IXyodpI0HoTeN7rJ8udQCR0\nzjJjctAMg5VjmGOMzvrYlNvhDudgOAqMoF39tZvj3Nn38OzpfQpjJzIFZrIineFewdfMDVaG3YQe\nSbeUi0kEoMFZRpoOqd74f/s0noX3K8iNNId73A601ZBdAFM+DJZeczXAInIoSNZAivO33A6TYYEW\njbHxvY6FAXMak/vQP1rb3IG6DN3jMprJDQ1tilVpiioH9Y/BJtGZDx0w88dEVQeo2d7Pe+kKM/IH\nz/PqffnJ6twnT89Vy/FJnYEwlmwfuIy3SfJ+xVI1MW16JmnqelozjmoKnWrJe+MKUqaRlqh2n/5p\nj/aNGieWT0apNayFsZrCcTrrf3z443XbcT/TQMTDwNySk495S2Lx/H+Jqx0rSmUhTaqxTlw88wE5\ntkkyjqEBAJ4/NDUyGm3mv/BkCxFpgdleruMUtrqYYj/3NDx3ureWVeSOQpZUVRVy0/MTxs4K62Wf\nSLKH+NQ0TMb5KWVi+Q8QId2v7LhAbKicJHslstIqB3B504XzleNQKwxd9Dx3kRN42oQBuRLAyYSL\naYwcwmMc7Plg8ERmrhzi2eGt1ivri2Mu0rl4Xvwg25kaiODYUVUN5qSGANVUT3kvKoZecxdXMZfM\nICTMVhR5kAxE6S6GwOg7B05vod+sYPvyiZqBN6fg8Y6tg526MhBK/6U0Jq5c57bB7jc0E/allglD\nmujsY56hH0/xrZmeciWFnRctL78QENA+tTE7mUkimkU2cro5d0TQ4mk6gv7ERvY9b+nZCFSUNFkw\nq01AGlUvmi7rcBV1rv3CpFHiWPK2rVjB1hbbAADrCAUsnClmNWQwjgEdNgFlxmm5N7sHMVYYlfTD\nBW+hbxl4pOaLDHEoIb3coHuMz+U0otYwDlYxfDAstdFeIEuwLxyhN+vv/Jq/N/54gF4CzVj9pN0d\not8lbAUm4omqFZUzJ4vt2V72py7FmmP8mtiFPq8JiSsl/W1UdklGIrNOObyNvxj2dfKwVvanKalp\nGEdWfN1Xo3UvdghDg+PRceg7Oi7Ic8tVcBI1uKRkhWw3Xh74hE3IKf5ODqyNWkPoYmeeL7YkP8Zj\nPc0GToIy8ku4JEv4/j/vFZPpjvj7BFMEaDLqrGVviyQs/RF4lBrbxIDoRct0Xe6RxXUG9O9joCW7\n3xPjH0mkzwmq33HisWdOgmnqwQ3lRD+yVct6OT52+jlcauoovTJWrx4L4q7ksbLIgLA7EqqjJMNO\nRQ8uoeirt27vMP8qiB582hQHRaUnw+xcIz8XEQj5ZuGVrJFmj0mn1Xp5exATKJ/4d3dweVJQhk61\ngSMq7ZmCoQBk6NpPBXFhYJUzXz01F6ioKX0Zp+2MxUjjWivdCuqzIpTF/rCGSTRzityuFIYUDpxv\nKsgNg3WOzsFyE26lLqGEmGJ4JH7SAPPHixhX0a8xd0o3n5clGu5muCFITc/kJqHdt/1LWE5EyXEb\nvgGnDboZrWUhF0xSOHtQbXYivFch1j4tvwKkDOoInEAyi0NJUD27Nf4xGpnYITgwmYnSZgkOYVjc\nKTtcpq4JXPqkcpYMGkgqpboXdXd+mTKNm+3A5Jkk1qtr433hFtf1/9Lyei3vCEtfRL2tFrqe1JXH\nLrZPArwLuZ5XyJ4vCz2jF6tsByCp2WWs1HHv279bi51tBo4aiTV3FZ8X+RMkW8U9dUNrQheuDe+s\njEfMTPpCotNnUhFg7Z+tkt8iA7OZJOkyFUTMMW54w+sg2rz2DOA/uJOe3cg5y/DipHnQRKqr+AhS\nxNweZ0RBzT3rqme5vWiU661dJKokf06/Yarn5mGPMVIXZx7HwFtKinO1H8ZqNM4Nd4m50FP89Z5B\nyqkAJcwHq7hzSJezfkgVPi2THe23IrFG2KS88igMzLwlSXc9d0LYb3RG9SN8nTnmeD7t45caCQLq\nAwCYYJ4dU8HFQRhct4sGHGRQj+8tFZ6zpavd7e9c+j3bvzLutfPvY3ttIOG3lcvT+SaYfvkTCauV\nkvAKwazImRnfyZXjXEJVuyiAb3oXNBZCZjZRw0VR/b1KwqU4bKfMEFnBYVB4mfQiomCIJRQ3SQkP\na1CfRhghHYHZ6i0PeN5Ls5EAC6z3zcNI7kbeBYHtxQqn7AGe8vOgsnN9Mcm/FqqlUAuJ1lLO2Akg\nZqbUKnzL1LQv3MTz/TjQ9hMXDAu6gqhpEoP6zdNJYnvIsk23D0TGROqSYcUXwcMuODhxYCUoM/do\nf+QDpO7uB/41FtJEqVW+cD2xzNmPKkOnqDvZl9n6djf0/f9n2eTW+Yh5x9rGRzO24qx39tIWQPWH\nJtAggJAblySD2MEWmdX2pSTe032geIm7nVXqPmKsOJrhR3EUEEU4x9RZ4FLF480nJc0gvLMyjftl\nh+181dzzzEhE1FJiGbGuO+dzIgphjFDcHYSGl2PES3o94liMtr7Rz0j2naHtoBKfc0FNFnyywdT+\nVmUcd4d6I0yhl4Znv4ImTRyBWVzJLZmerTL00y4VKYtdNJtXqA4urwgImCJRJwwAbIFXjIxjqVTI\n8236cKAccubJidpBM99+RYS8WjaIuJqzY/zEGkOMYXjP/zC4BvSd+nqe6cmCTE4gBDXzKw6JPg5D\nwaAbz2d9efUDnHVdyHU0ogMdjyzFeulZh3/4w4od7LEXzanChjg/NTXU8/Rl1FUWg7T6Cof6b915\nfUbvxkAGxg60Ji3ULoqaBYFLPoF1h6PlCChlDeDQQn0n0E+R2mfN5+8rWetMiWciLIkj5F7FofBB\nKMHasWaOk8OmHdc7qViNfRVLWJnIWVfd6Nmc/K2gf8onvNCR+TqPUjoAPh34LsL0bq4m8QGoFUJ8\nFSs4tQ9RY7S1op0YDnvkczVd5eZCEqxcm7eGOfpXzZ6jb6W3vaL+ADsSBl8Mui0ADkX/3mP0XgmC\nYTlEEOvKrXjOnyxSNumrTtYpGCnVV0r/V9TLl43eQXGAwhLtOD+Menf0AupYc8p8i/U2rsElwYse\ndXHOgh4oZUc3UUI3mvXwZIzM2GDe9uq6IqsjpMD3RV9AiPUiN7uPQbGi53zHQaBqJgFM21Q8Ayam\noWLnhJ1op4WQKJd9wuTFvEYRQJHhf/1tRHMP62hrix6DbS/AFnIjeBrenFenYEH8qN5utU7Edtdg\n9fGWA+B6eqRIcfGB184BofpgIae8u8doHc3Mgr2xWJJaCHu0o8hA70CBLOy4Z6ayX0aBFcfDGW96\nvmXQ61YIm7DDr6focblO1ibq+ZHJRKtm+826z93OJ+L+dEgXB3wTE9wWMiN70nE0yJCzG/e0wezT\ne3702kIqJs6cZ82FHAf1IJvZjz1QWUn0Vlbli9jq3CK0U6X7L1g0doY1fX3pUmHQVXFj8YJkoP1h\nUHwNuizOpRxS2TiWGUo83P9AzN/K79tS8Hg+vmANp9YDjzNCzCwnnzDXHGxVnKC1EVycELZDhzRT\n1gi8qKUwSOH3AA/gE2W42j5hSn53Icb74QGDAvKp2Kuv5GpNX+P/7+y5SdLdlnc13LywjMBwV3Lo\n3Unr+dEUp2b4QLeqv5dARgxsi5GWTpWMFnQgU1VgyySr4HN79wGaTBVBu4Vh5ii4QsVB3tQQwI0y\nSktRIR5trfvpL8aoo0rD718OLnId7ljyiOxQNTzPB44YGSaMS7eDxg+NO4mrAaU3e5h4wO71veeC\nltOOEkYGwlpFnCw+S6rYT4iMuVzqktJvilxTBG0P8f/3e6uTmA1LIN9+zCj+Y+y8+2Sg8FXzsyJI\ng/mdl0Ccb176UhlRduBM6/MuKU1ev44Aqd46bQ5u2QRXKKrJ0x+59vm4y9qS9Zvrh+tkHILWulXy\nhZj8J+BJfGmpAo+KXy+jmcAfQDcWJ018kJYEDcweGsffyqcFS+fOvTxNnL/GGQrx8gUN6K8KlbDF\nKW8fYCC4kEiG4NJ9IT4ojlqH0K4BAiRTpk+7Afn7BVI8I2fzLs5G1hW4On6Ki9WhbyRZbIQqjJRT\nX2w8TJybeOmS3t/0Fa2GuvZZqPL+4oXxMfG7idjS85HQFsV64wWabRHBZXYCsSXzqfo7CgBmmrw3\nZ7EK66O0pXn0ovwckEJJ+cTO80TGqsRTDk5AYsjpHBuIg0AKi0a309Z+Mbe1oKEVNmWwyaeGxMws\n2jzInqP6d3PIAJRyCaNLzUfMc73+BxGpEFqwD0AnmGdTMEoiTo4IHvK/BIl3RO0/aw7G77JiXxJh\nwD77240PywsITxz6CrTztzHH0a+H7DvlKcJ1/oyInmD6P7GcWg9LA+munOSjxgP/Tmf7+hEt0wyA\naPHNj5rWJvWe++NZdAViebPEQxMb5P/csj/GxcEcGnZ9WNA9RX+mDboPAxlSwRgMeoBNZ9w2R8ob\n+HSVfzkLdv4xoO4lGqNY3mYO6woBFYNhNI+BRnIoSGtXwh9rOLEXXg9vTi3xX0SqyHCCJprOJe27\n2giuVCa3RzvSkz+og1YPuX8GieoKi5ZQ6kzh3SLVG84/e8wJAvwgJRmXljuKPryT+hm4rJO0EWWe\nrTbCLAotgvRaAqYSCo0UWGUxzDnzZK6NFKZwyeKOgVImwvsaFfU3IJ89PiPdgsO5U0nBrJf7DHDr\nff9DlO/ipWfRzm3sayUzDvS22Bgl0ZIClRAdCrR/nXg2uagCMa/TXoBW4w3AQ/7V4KWYHa70c8Px\nfEBInXaOMLcmXEKKYhhLRORZNR5d/SS+saVPn8RrO4B63P0cBFZR/837/gxf2OZih0K3FJ9sJMoJ\n1ghik0YPAuVthIcXUcNarLm4/ziKxtujMiSA+RzfxOawW5Qh4OOQBGTHY8A7zg+QFwU9cqOSJvBu\n61GKvzmIeijgXb661syOt0AkN7Eq04QNhx/G9j+O2qJZvPqvjMJbWsAdHJLBghyHqZXnrQjEh+qr\nZUCpFh6+KGjlwFRUaeYEnoZFkaRzDRHSl1F6JVrnH2T40SNNS8jH8ljpZAD0DDwZQFrCwbq+g/iH\nOc242psMqZynoTb0vfZZiIFRGZhi/C+/Lz0ZjhuleYotPgnq99+SZIzqZQoQf7+So9g3PSMF5BNV\n9LwKSgH/rKJmyyvZ8Z+ZBBv6vGWBk2DafodcgfxCX+7PI0M+BBvmJxkW3lgO0vMlgXZ3+GKGGPwc\n3CzBvfYWRCM8nvWPkxhzly7ffBkJ7s51MHRuwKqjAX0JbqYspuvZIdA/PM+D8HmwrqZwEzojdGEt\nRLqlRGKCjG0n/Ej+f+QtYfhHCSERIx5JIz0ztxNE3qaDFGO870Fu+O4VGcgEsLMf0Ywqrxv1CjLZ\nIYvdYaPjv9M8nlP7I9Wy5YATVc81Xt5KkQd4/quxSx6s37qJBCNKIFziPgJXVulA2IJ3GkJGIuLO\nRhDs+4qCqKnW8ZtkQKxzN3sEPJA9zY5TCW7BDv2Q8xXLGOXQsnE08QI16LIuyV6iviBn+BoRbSA3\nsesvhCgYY0EKoTRjsgbwjZt3nnV94zupoUMMV4riBi6ArF/YfJe+Ln7SQ3/tYflafq2tDK6qGV2k\nUr9ketsfxcPoKefatmyYUoBp0ajfR/cM2cvYcyfD84ApEhqYj7oaJVH49d5xqg3utCLWMybEHiWs\nHq+yEUpMyCcgqZy5SYqUgrvaxW0+Fd7WhjXum4nizCAoyEd/X5TVwBOCUpmnt7NsSyrUot12Fv41\n10wxiey/RPnAOt8cz7WFD5/WC1ay+n2cp0ZPmjzE5k27a9daY3d+vIQ/uoQJHxWQpqqwK/9z8K/J\nrhBrNPKQ6QBnxIM2Emr//aXCYvYhlzUiUQR1gdlWn+DTMYgSOrPqDgveXzL7FeYrSWFUY16I+4Do\nXiKNuPvub3Nat0D/h3DYyMwdSyFpxf1ZN6I6307c6Bp5JlJtzEaSFnwDkRRSfbYsaOdh01g4HM3s\nff5Wb5SI2CDGTmflBlziWhXqyttX1GMxJm3aynnpLq9wC8TGOIjIickxSZwrl1Uj2PC5UB2RlVpr\nt3EXp6HQWNpVkQrrR8uoqX1fD6CZ+64I/TAf5kdNa75umES8AEnodHp3uXEx1k9eKel7JbugyOj0\npwyLME0AWDNi3y0gc1cTc7Z0mKXpuUzlMYyb+8GiPoJC7+M6416MhrMY53TfyM0DALSGefGN7YRn\n3F9hTjZY+ymZCEbrPRJE+OmuetNg/kik8kzIKVJ9kntm6kUpg0S2tHmUAFVcknJRThIhpwWWwZPV\n13NoEkIGJ5XVILTTkA89Q2DabrhcvRihAr1LMyxlIJKSm32qx+gUYPSDDeuTtW7uvHhDnOHEJSJJ\noxhEVuEXMAm3eZeAVsDWneeHGomgU1bk60XBddn+GWdxrwNR73MGst1mxajwWC4/I+lI9xwSyoQc\nMME/ZgubIispV7V9q0gqpt/AXIfS362+TCPm7uggzZKlllcFzt/Kd5eGXLhIVgymsKQst7ZttXtV\nFnphTgT7l03V0jgF+n+bzwbyTvn7U8MvY/RGXEQmuRCnHICJBmj40yMmSvDjvUcpwaehGfrlfyV9\nH+6KpMEqDiZ6iUX0qMFfFOmIBbONX5b3snCJRuB0zqj5ewg2NQ1e4p1w+XAKjCoBUJFZVpowPnk2\nIw7A9NxUnJpQamzXE6zbWq1yRiToK6JJFK404PzIycnOyYrqQWvCI6bkvP0CCwxLohP3lqMa7b3e\nkM09wuhaIY2cQBuEmc+2wHmLnWpkxKBNiRi/EqHvxOQu6Oimx/Ch8kQ0OOdwzrq1GkvNuUb3A/pb\njLiScBpKBwHQKM4yW4QvYUhYlZjZu0/FvkR68slHsummnn2uO0Lq3sJBKbP8mQXOKoHvNOuWknXV\nNKCjFIrksAt2u3Bw3tM2CM+Z+mPuZCY53udzbMSrc9srm13YjVfCVPl2R6LKiALsG3gy4xPvQTBj\nfvE+SPX4DfiOGSXA4En+FESle5ILFTfSpwbHK24Qa+yh76PzGzWfRlRzDFd2DZtG0JLpDbnWrxLD\nzh+dHtfzg7bE/KUbZ1tFcPh5ZLvtP8Qd3J0z1TLnIxl9RCsnXb4E0gjQBHlY6/Ae8OrjKdY7wYet\naFa/BNqHCe+ZM+JJaWbVfjRSnC+SLXco9np961xUgfiJhLgUeALIyX1qykzkML7z1+fz0dRKWBHc\nyjm8ypB6oWbqoLSPpdFWNsZJFSd/nL1fc41WWND96jiGPojrSBxQbqJe89jTkrEEs2LDjD+aYqqv\n6OznKugVv0G6Gj51OtWat2MizTYn1iWE4TN9AjPAgiETyJId5zgB/icKF6diKYa2R28WC6MXgFOA\nmnn7zEdw3cL1HEGMHy3ihWPjJx3af2XSWasjFPDEMtKygfJqsD7KMnC+f5PMLsro8SbZZVFEc8+O\nqItMbj79FGdKp8sUJRgMw3ptl45xZ9HC+AlrfHsmCeZy1eAo5T4VlnwWIfgrJf97F+QjMZkkcSqG\nN2eMimZmUZlC2hao914d6qhZBj7owCTtN+PMViWjovQTrzRVsSIk2XN8RCXD3dW5YDcTt+JrQoZ6\nfG99ttKpFYnUoawcn2BD1IAu2FmcAMKa5TJ7itnSAcsq1zJsGYoNi2KmYyK4ML7GPLHXFahaSknq\nPkrw1hWj2ii7pvjebzsrUgLdwQOP6jLuYmssgU29ITyYOsRemHNRHGdPesvy6j5folcicqGEW+gy\nnU24IHY6c7hpJD3vH+MwrZcWF7s6jSaNbtd4oXEcsk0NrRg9P47f3oay07OUJOrPDiFqjx3sk9Fx\ntaDjuFvAPURFNSNCIxSq6rtC/botulCWkEvoKN1Lk36riscwu/KxUjexBQJs/y9Lic3R2fCbJQub\nxoeDX9nISLDdtBnQN1lMYUpWAINwi1CTUVaUnd0/8aF2pIZEKLXfflQZnkZ0zTDXSxtN69Ihr7UB\nsQUDVTzArE4MXTidUJpCcNqCRc4TCE4BVQpqKW8aHAgRIf9THxGk+38yIUin6V/zQ4W/PWX3tEQK\naicFbXRDPR/oqW6WucmKvCZZEiYwXwoMTxm/v1vFhQblUa8Tfh+YkhDUDiWsXrVm2lCySLdzkkLf\nMJpkKJXm22LXuYXhK1qehkQD5axucFwNmlfkhHsFcu5dfLY20hOJD1Ks/c4wuZ8J7xXGViR92RQJ\nGyFeXbSU/dLrvWB3JjbXlju44xWwcSZyRO3Y5OZ/UdoZ0v47EqeSa1EmoLizIXgHYbikoK4iHyah\nKAjK4KDOFSkUaOYG0Q9bIHcmyOu6vOMFwepVetzmFF5gI66W4hVq3bnsklD4mVA85LsxPrI6830s\n2Ap7xlhc8aPEuc45oLeTQ/NSy+K9Im3nICC4yqn1WKavQcYBfFUICiQAvJ7Wh2NZkPnSmeQkmz/4\nAWTAXwcbRRiTRooH8Rh6bDoSRzvLCbUOTEJHgZ/h/lsPFkAynUZ4+470tP2PEu7jNygJlZRiRByE\nWnS9y1WX9nBggKZ6qpwzS4HxLheJGH4B8Oald4sJjgIYA9dWbwNFcYumkln4n75fSF6j/2Yk+inl\nSAJPwbn7tcF+BiyG/k3iH8nciYPwZosbBp2QxNBQN1yQaZdCSx8COzsLAu9Gm4ME455CAqt8dwE8\nVA5+9ggBQrkFrW68S6s8cFwy+F+2emyGqnrSttj/BwllJMrVuFaKjb/xB7NBbuJMewmxTZLeYiPM\nD96+Rxa9HmFG7bNBdk1xC+GoWVSLCJnqFM7rsBPpVBcloKk1RBhW6Jxwu3XPC+VAOfS4oSozKEd1\nLUF5qws3/eq7J8cjthfdHcAusnT1b+/RgwRGouys4vjwoUz5PYT1CKiJhNrqgF/DUoSbftHdGS9Y\nhLG+Z0aZehuu9C5nIwklhjCKmZyWs4NN2ssOh2Iy24XQ/VKfPaqvG0KNqKU8Z4zOhFOhRwxAfmv9\neJ/bcmG0MW39A273ake091pKu7n4C0AiHUXtIcL/KvxrECvQGTQlZVE7s4FsSSaNZLdFImAkNUin\nwn/+3JUwcaj1yYrPS8eB5qAqE8Bdox2fpFpyGmxYqatl88Oaz2YLpNHwUl+S4i6Kd+/klZvqIXbk\nhZH2AAWjoRK/4bYHKss8KXw09QENYvNYlqaXYEneKVSUxhdjROnz23YMUmScImXfAkRSvi9n8hTe\nn3PyoWgG1/zVXoFgtj9sYJLszBtBUg8ZCoBRSZ5UlfHW7C4+oASmhYcWLdD74R/vBhZgDDVf8Pa/\npyW4Sz5rlqZIY8xmy1N3h72d5B4KKcmkHEmccnZ1hWNXPRCn0ABw97pcHSolnpJ3xvmbdZ5cLivY\nfYcOKy4uamlcMhjIAdPz82xIAbVczEKzkm+Ybb6ZFSZjf2Kgnnkf16prt01dHHbzNjNI2SZeyWJh\n/MdrXUV7MtIHv3zsQ2gXnR1+/kRN1WiJ5RqxJqNQ2Wp8qZGmcM/tjp2e6gNz2e/9bvOr7EHtoMp6\nfNmGWZod3lKky9wLE1i1hR9beNCKfxrlouudQSl5aa5GteoFFU6tp3fGjcd/hnFijhfDtuHRiTgL\nEE1Yw4NcJ/oSrbSdvwFxmsaBxj7h6Ixc1oTaQx1tJzaknShLFkjDpdvW53s98Ja6q707QkfQcmrg\ndbOu9mK4XMMlU7TCpF6XK+wMvpWoh+lBCx/ALRj+jC2oCSsk7+t9lqyo4pwWhx2nrMhUSwoi1sX7\n+a2VrsV9eUnPvdGGDFy4OLOlr8tJUd1nQNym/uA7MfjzeHFzrKs/KfT1I5o1/rw0Zf/HXxr/vAK4\npMH9IXI7Qfy5FePiNk7NGuTdbBUmNtK7QSjNwQ9Ql9bdhdVI0IIZh9pf+B6cr6PFlDMCmUBigB9l\nBU/nVWZgvfnClZqzBnYquuB9OR66WyWG9fI/6UUb5jSFrGOrVBHm2nWes6yOFBkRS2Q6SA9ykrxn\n3ssQfwoyJLX4bkuFejlgWdIEYgscbKfHZDSLjcUj+MlFEuRB90g+20MpOnpZqXqbf4BR0Ub7wwPd\nVeoyru3p2Y46/bcIj+4bUAhCpbgYYpt8OD2jw9+aZfxMbBobb4LQkWn2BazEzZpppIxvNXb5Yxgk\n+GdnHIVunltC1E/8mrKvkA8LUnV4/2fuWCCRDR6gkbpUSAhi6/cGtGPrqaJA93jIifjtY78WK11O\nlpbuJjrnfvt6fZhrZjWQLNKljzPDyj9eNjxetidK00J9ZYIxs/c4Aare7jv4O/2VgzLdL1eX5Lwq\nj/BfW3tUR+VgXG4ZWvfhJBIY8m/8rgjcK5hOwtpAIzlfluEOJubTF78TwtpRCocJJvW4hHKxMcMl\nEs7J7szjRex9IL2/Fe8tJV0+3ncYCtvU3C4M7H47uUvDjECmSS/4SF4JxIupAv2p0tcWL84QW2/M\nfFhD1eAggA4SRepWcPg4Lye95oNLZ5cFiqjIPK4Xrb1ufHzjJahek2VfnLJZDLLxdi40OG0z8gt6\nE10VcZarQv28bZ/8kJvtQmSUCVnq2Ti4OFKZ1fg+mFsanuC14YaxT3PrGQdMBD2w6pdvMZkLchCP\nHT/rTrtdmAgVAgomTPRK0mBOE+rAz16UiSG2cXPiiJQzHVqzQe6FHITVLttkpcnFTM8cEX1hpjgc\nTtN2UyMp1X3ofyyMEckoPhsYeSjLYlgi11PVPVL9pHl71t3UOZ5qYG2E2lbsnFiPS7Aci1XeMlNJ\ntdGis9RsrWE6soeZjoEGhHARK0e7siLnz4oQADhh4C4piGRNr1Qbye82mf83F+1GSJgvegok4pV3\nHUy4klW2HPck3DiXIwyhZu+67RMgwLkRd6JqMLe/vBfvM8Z2WxWApQ4SVqLAI9j2drOwqZ1EF66C\nNljcfbl64YPrX+0S2zhpU3mnGkolrm6xEPb5z/PjpIVLTBV5WMWn3H+xMsruXBOfbp/fq8VOajPv\nTduunJeq7Ix09jnzGHQoJ4afECzQNuh30bXda+lOFtFKvjmbcWWUzJZA+5FsolFp2/D/9Q8Jjhin\n/GFkKIKIV7Gm2T9xi/MmWSva+GhtBjT+B+ymWfjuxnICqEK+yt+HVWOQ+bBIU10JDigqMuhmHRbt\nr3wtboJQU9Ya3wBmg4LJrb/QXA0ZX7jAvkfM3YFSpkDyQiTMJsr7vTL1JTaS0heg423bNu/WublE\n+VpUKKIQPCCiG5/P0be4eGJ7159uv00rGDOFh1wcQcgLLgRo0G3zYBzwXK4PPSW8dhwNH7APg3c0\ngwVLMYPPB2zj1mdinqoKiTa6HrlKfSJ2KyfzEwGPaAABFA6MmXQasdM02NN5uEWDxgLpE8zafCuh\nZzC79JqOyhVwaEbjCCmxBbkt5xK16INYbXbEOJ5Tl7iRryZHWqQqEB7R2uPTSCEwd/RimgM0eSyn\ngpzsu24X8Tbk227yKe653NopGszGrQ+BJRSZYxcQT8dXyqnOMdQbt6jQXzhV+vTOI68MzNNr0Dwh\n+JxOY0NsbJmQiAWU8moLkKfOb23/1Q2CcPnbO1kegLAPBJCKIDYnKI1/y9Yiu9CjtbxAl7CySH+o\nSYzWyPtpDuOXQAFZtH+vALsuwsrAmLm4jjmW1P6KtOlqGjCesYvC8b/nYoqngYMjtpAcnY7lh9xY\nM+XPIVZP/SNbNWGy2XgtJwcK33r6FjBDdugKc7FdxGyP91aYdOLS9VeCSYcqwjsxveXwZW2bbu/2\nUsX+PsCk3R7jm3xB8bkUN0VtG33KRB7nPHVoA8/NHvt+oIHxHkVNrOyPeVlKP7/Uinx+iZIxpM2a\nkhTM2FZx5RUX9D1AKRZdnJ0ATsMcZyHNLmKmqogtJyyXrFDiUCj1/W+QHcZIq4j6Xh7yoSuholi2\ndx4OHysbi1e0kFjHAzU5AdTSJLjwtjvptsxum7WE+lo5Em0hic2l+N0Eg4I+LUHZaJiROwaDpsTJ\nI0QSwTUiNJJ1bgu0LnLRfdU82qyNyb4vpFelcMbiA/j6AM+naMzQP5zO39OV47ffmFHFytqgkRr4\n6NlalMWtQM+0wX9p+oea9xVP1OuP7xPtM2UkqehSpE6+ccRIRZ34tRuQ5VzbbgHjBzwaCJdDNhw1\n1v1C2TOnyku5Nz11XtdRC19tgHN/p/pdUuSW45JG+faKHL1o/ITfL8vFGEbdDsLB0qobu8a+tjRT\n0ONLsJ6ipR3Vdoiz1bpJm1VkwcQVCA9Js3//vzYD/25rNbNXqjKQFsjMaHoTIUzA7KIFkaCDP43J\nFKt8Ct2HtJbNs3N+7Q88odt31dQqSikEwNAAjPvanb3pXl1uidXLGVwH2I4OUDNSFhwjPU+yYh6O\n1Nge4HIdvRvCuP6eOBXgkN45OpAkpj/xRmtJW9czsOTQmkOJhomM5MoV7oCZJukwt1rguFLYEgEs\na9guTfGXCqS/8UdpRdkF2FfYbL55JZ/BbZu5lN7a/EHAOOjVVrZMfQDhCA/S+Me7I4sdn9M05Drm\nYGBw+YQIEWuFut3BpEEg61V2owttgmKF05G5rPJkO1dA9TzUltzAQutEpJsKN1UxtyPP0U/fmi1X\nzbiybcwrxvbnOO0aJWqXEh9JxxR4pUdIS9sgiOiLFtPZes8k9/C5hDcPwX9iLn07CNxUq+HhpbAY\n/GHNU4t4+XTSgVd+ZH1jtIxEV+ffF4mKpYoymqwaCR6AxvDXm42Q4eIPFWttB60VLdZ4smRzHtQc\nOM+gXNtKekHt9iF+OBmhne/EJQrIN9ThkFBHLnOkcnrUP1rFbdHk9Ih+rRW9xNnqmOpr63chVa4c\nke0/0lCgbQCAh7ToaykaU/+Bol7aGQl+RgFWsZdnk8RPK/5BkXufVNu/g3Rfm/W3ROSxzuAKWQue\n29tz4avnjnSBQxqvvN9UJOCi1okSCfnMu+pwqeXygJvNuXKPfE+IZXkmZea1Fxl6NOoV1VvX9PEN\napHGh9SX7MnxRfxWgTc9F6PzJQFs9sdc2flc7GQW3xNfXqwhnol8xIzwhiENevhgpJCHqFbq4eoK\nGNHCqvqIcLwvy27OJrgg1pto4KA+FtFycpdIroO/zLEi02/M32VtrZySQrLGkDfOp4hXxLG36qx7\nf4WZssWigsi7XM+YjgZ7teTaPuEq7BvmFeSo21cTt+I4rUNS9k3qZVVzP+5spabfA0sJHJRKB/nk\ndtGSZLIJ06zll2Xz3YElYursxOCqYBbF15R67nFDAaXqMAimxgssIjpCTb5/lqgfz67T/AFrklCA\nUAEvUEdnFXH0b/OCGnTnujx49w7NDikIlqVVBlCO75JhQi/kNW8Nj+HQ3w9T9zoIt7F1GNz26i7W\nngPjlfjv3TsfkXGiImD40LUpWjKhdpJJoqf8GT2GmW3tvSBPf2gPrOtFUFr0uKCZTKLJi3hDCm7W\nbRKcs5wj6Dv4ZnevtB1SeT5x1C0ust3z7xNEdwmv6H6UOVvvT03N0j6lud00FX6X31iZbL4gW1Mn\nIhGeZgsIzQRG3aSnLxEfs9nRQjcapQq8/DVH6z/V9ip2hQQltbLj9aH4RssNzFUCv6oZBc1tIG44\nMVjryai0OEEFhfOhd5gddmzNwhbo60J1BYAnaAsfahLagf1gWAxol8w7gNQgfxPQw1JBslsF3FZ0\nNGpKIR8j6TxEWJUveZsVCUqwhgB+PkqZ2watpi7OWnIDuebZSA4fg6FnZj1HVuYGtLpgHFr7M2Tm\n3wfvfNLAKX9cxWpibEnqh0cototqelfnCD7OzGcM1b+wPUg096bBaNlBligQPbxt+ZUL13VTzkJU\nL9jlQ0jLs9exH3LiGxIATCNK7WyGIFIENFgdR09GBieB3iFDWGT5FetPi8OmjcGdozhn7GEOLa/n\n6lfXD5/N9dhE2wCx/0OlXVXFjS5VuEknkicQVNl20aZn1dys1NvMEhR16uDpIugwDULdciAYnLDL\nha2u9+UKvog/e3z5u+A39eyCtwlDUl5fqWd9Rmmih0VTDymAX7fvIqJy2g77ighQA2NvvaOoArun\nXBks3sl96OxF++2agbJHYWMfrl494u5tpc71gUPBNFk6xnUtcLnKpVbxhGGZRAEk6LiRdhgO8XKb\nkWCQfe35vggpG6O+KasuY+cOUvBm0kLOm8Tq1ANHmH9R+O/QmyZsNbDcWByWYxYVNJYXQedh2Hmd\nZFuEHx2/ttx8NF1w9InKjINytYALwN6e0yTA2B475ob6TIcD6ohQVW0G41JCnJ9OfBCS8WUSYb9Z\nIkrNno/LWJ2Z/r+UfFftZHUPj9LSCL5ghp/8/4EcBEgzwbc19Mbnlh6juMC4ZRL3vrMknS5sUmsP\nvgLR3FNfCa2u6nVR1NEG0yofMPmZgljhxYYOXON7I04cFrOMbFZUaaeO9M1Cli8J9YlScxXJoZ1E\nvDy93ZvtqT8osUC7yhUmcu+2pNZwf2HOrsjFTq4pkv8omBaUFTtF2nBWoUqEEiMJ54XACYcU0pob\nBclgJzDJuPy/r4bVLb8t+qiA+65aE5r3M728gjNoZ91i07resz736LpL8tOgXIY87i6AkY0lLlM2\n3pf9D6L1Pna0lLT/RNDL85yhpDvD3hDnSIgfQZtWTl+Xu2/8hbS0Fk+HTMQ725czknvVZcvrNk5K\n6huJY4GFmDvgI40dTu1R7zbW0ixkP/KiEjadLbkuRLrNTHfxvVZvT8za0L5JhRGFzCaRGBK/dzTa\n003iEBOK5pBMDifuhlWkW9WVVPAeQMiO2M8G0P/on+DDzHFh+EPIVHTYiQK24De7/pZqRQElC5B9\nR6hzmjgVxezwUeu/uRcYnE9yaYNjb9hgAhiFFv1/tMVZiA53WpKj2gckbHzyfey7tozPNuU9LNSI\naykwpPP2R92OQ8hIE2h0Z4Q7BLm8HihGWAay+te4q8dkVr/uvZiP04sqj1YUVVGVGIERgztLSjpC\nz1EyxGROsZnu6D8DItN906mzzIrPiQeZqhhACXlEwzULIGI5HK6zXg+e/SFXlwPwHhr9LjE6vzxo\nhxO8oXAY41XMpDKQ/c7PZrrVpQF6Rx6VfxTgmJQYvP/BFqAZPvBk7EFY1IETDTqYkjBM6MSGcXQ2\npntbEOLxrxVAVDROTVW9H/L2Lf8wHqf6Ip9hmevCasFRbdfXiYetdNZA6sITsc+gh8rFoXZNHaNT\n0I0AlIwe57ErUeTRS53zmAJyt5vAuENCr9qFfwsXLgp0OJaYZC8ZEoGIRjYe9CPGpD6fXhJetE1t\nlyO2ytJC/VYG7LJx9D4WGi0O7zEBSf5WZI9m9b7HGfzmj1HqWviN678E+OtgPD7wvcc1CXJT0QUm\nVvOh/S9IIAIov4P6TZjfghqxz+4wiwD/xrDJeOkXsdcfwM8o3P4g//5XMNfr0QJdI9082VSqVN0+\nICIzDCah4KYDwthxAEwPJcc1UAsURJVXVVEVvXVOtYm0Q0eU0h0Mx7IxyfqVN8Vz4NV/KpCqS33z\noDriKyc0U0e42dAi4Apko2BE35AJkikUSphztrwMIo+A7RaO8zmVRBtm1kXrMch6a3c1BczAOr4Q\nRUHNiqdmldexbOFg0zIrTInHMxI3bezd8tXDGQCGZ7T2OfJXnSarlQud5657CJJh5MZqow/Fm11D\nYjIODc+A+CwBcFgbDO/0cJs6N2HZySQBt5aUgI5LdLTMeRARLXGDyEo73Ctw7JIAwvAUoqbqEKWx\nWk+idYpMw8QSXQeoF7av7xtXJwqokXhfgjDwAgBJkwuEKLTM+/816q1dnPslciw+9Ayzhrp5Ll9X\nVv/NwiSUGlqM5s5wwPxPEqxkVaCgWEEv14vwQUAKFf0FbdkaonEguMy6lOUK6TYlvx+c+yrJ2/xJ\n73+/7Z3EPmNBi2Js6nXilYaEDRRCgOTpoIxPcdhaLFNnUITLjo47ddkSyOd3ua7Tw9T4zesBbjEa\n8MtRzIUbJXKwXWH7vPEvoDBHo4cuwZac7XHXa6LGspx2ULEg8NUDDjC6sfWU9GL7SqsDAh8jAh0Z\n3MxXEf6LGYKBsbNTc+mrofGSxSOZW9oxfNtIslGrjUceld2wfyaIQjJjYvM3rjUQx+NCLdsXHvBx\nEbvMABlSpnc6EjMfJYbFRrUyHkVFueUgjy963YW3A2WG2D+q1zmNzZPS5vpaASkTq2Or3pP25O9V\n+7dISHtQ7yV4AbfYAfQnhM5DrBZcOwqVQcR++Sy7+DPijDR09tzR0EvKd2UV+90CkpcLkMp/z7xo\nShC57x7x8Wdzl2fcmXR+Vlb8H9zQTpDAEZRVF4uhti2o1KdYx4SL3Zdg6A7wfPLJZa/VVGumunfR\nemmnJD4DWiZ0nZGZTPj13QgAJNjjFIKPRtYBqZApLILI6GvrJYveNlfsq98t2IUVvABb0n3dyR6i\n/RCgmhYaI1Ljg6V2EheyJlNA6iTt7CEXw+jAh2qAbhAzojsuhc24avWxIGGaNWDpzYQiq6hCW6rX\nCnkKD0I2K3A4/6auTL3o6nryKfFcFdJiqDHx4/xnl7+F9fNyLZ9Wh5eeBETFBPMgQXbxwLZUsjab\nbHfF8BmrSEzDawhNEi1SyTB7D2xzEfLxneVCq6rrhQdlOtyVOVeZ9T6WrzE/8Ba/3ZtLZ+sh5h+q\nhE7kfj9YBhLlVrfjL7mEIp/aiiz//fYw4g6xWbFF33HTw2Phj1p7i5aCy12xmcQ4XwlUTHmfRcdg\ntmxWsPWcaDJNoGhZmXPrImFtPhTpPhPFYIvRGwtG9ec0HZtJbAzDFQ83kR8LxUS8nstPzF+1d/hu\nouL+5B0NBVg3uZEfjQQI2oYuzfKS8KtpqPXD4KWXifM0EqTkuue6bQcC48tyE7RdZlVy8NxYsY0o\nowLt0lqwBNFCLLkfR1q4kDid/05if/oqGwErIwnvWh8pBR09O88zrCzNG4L+qFg1fy/PNHFPqh4Y\nfEnloyioibbNgdfLyCU0DuOV42dQ+ntCCl8/3mJwMLovovZT7S3bZ6og4W6vayGYTdLqo+/6Qkex\nywJtP/hL/mO2mEMpBMDkgZAJTY1FNfCjXntZ6FsBNSu4NQa04aIr4UkE4CXOubSWubAXnI7j/4M6\nm3EMI+I1HYQy5J573N2qvTLlHJFk6Liu3XxaWeIRd23rvWDcsvUCYGg9H6xnSNC2Hwmfl8R2XIOC\nI6S7DjXjIbYuhsvKOzbliZXSlZVCI6GBYdE2yHmfm9qz43BrNA5Yp9bhZkGN4BTXn370WRYb8BU+\nUfNfr0X2Yhk/hV5yJc8K2PH/hfEAYGlZ8GCy3vyeJYdT8wESzMMzbueKCM3Iu1UPgi+tS8dRsC6z\n6pl9zwbiwkcYaevx2wV/z6dHjBLMNzkfAvefUjnT812YH4aRrBLBNzl2/9vJjS8jID0NWocymoHL\nbmjaUHhVv3QuURBLCy/sEAQoVF+kmxfsq9owq6EjNHzGD06u0Ftiz5KPDr27eKg3a32TGg7TVAlG\nB8/mkeo/ewRnZ9Z3xrt8WN2bPfYH1UiBREnJva9y16TDki/zw5BV0q6S59+gOdEw40w0iTjna6rc\n+FgxVHrA35pEZo1OopDsgDJBGVyZQSRA/VPu1muM0RRZpJMQUd6cpmqjCyRBtnHi5tp8y9xU7u8W\n7YG/+m98PlplI8ep3m6Lt0v6Oaj/2qrW5Zax+TyVBkJ3VQTaW1HcY2uPBcah/kbOC5uegdH8fxxI\nN+6DD3UOvhSoh6QaycgbfIy+NdRLiSzNf1dGTsN960woLjV21ujolb1IrwJLeNB32eIaxlhhHQyU\nUenZr4uUQmil3ZaHZOCln4Y5yLlB99g0koK0huCaWy0az7a6IQeI7TLyslxCgVmr8Wjcgu02q1Ot\nUNNFbz2/xQ9D4WMEd5mct3u3n5EBxHtrmxly56BQhs9KVTRh6yoSbwfsna4LVnoE5Zp7klbaO0xs\nBP/STJDdcLdaJVBQ5OA9cuVZ27dOfgry02Qsx3DjzwkT0+vtlZpUvmoV9rAglNdEWREF7tFnHrVH\nIqxpQ7U17wAuEdqvLdFLp87MF5DLfDJp/M8MknjrqhgVaFB3xBLlpZPiCKL3v382X99KnrReyFU0\nWqtsl3wzlMJta9CkbFwjPLo/WEcQCvzku2R6/zzms1AMWcgRCVUmxfMokhe69rNXtMUVMu9lvn0N\naKHIfXKANAY8ESnsPqbGkmuWoDL9ndXXgxSayO8QIFOuzqT0al+lriANdOV8lxXfYI/GJIU/OMj8\nF5FPJNyJGRT7sBhIfUz90ZK+fw7sst4EnitR9zoK246j76y+26J93xias2U5V1JBcF1CfPEPci07\nrBEx1o7cOx+VqnE0JxdgSa213vhfSE5NY3CQBJkiZxVQ++gzLnK4XspVpL8XMaYvy8ZOwhjwqArE\nq6Pd/chGeIoRyWFBgbP4nngD6fjgKbgA9WGcEtrW/pkp65D9zlg039DiNzFhEQWcwR5LWKz5dBTF\nGcCRqyTn1JBz1sjwdVtqRPfCfVaLg7+onnyQsMWq68L5YJ1iyPZibqaiP2K4pMt0BfxZpnZin2PM\nP2DbsHO0JzmaYf0pE4WE4DX+k7CAmG0B004WO7+M5eKmXyQ+DsJjIW7PHHF6KdaDNQlqema16F/r\nGmTKaP2cj6A11elxvD/UQ5MhX4Fkc8Ac6U2k/DeJj2ULANEzzLcQdYJH4BSCcMCQKihEX8p3xo44\n2QICvGeeb1iq54iZrAM6jDwnhdiOyFJ8zrzzy5BYGIcXQP/ZEvRywrbkNGL7ZxC4fnJsD6X1L+MO\nnuhFH7nfGijNGXk/yR3KMfVB/H8978YZtRmoOrrvi3AYKCkrjSWcxDpgJ+ucYujRbgo0Vm/iN/IG\nWDx0dVKrNqX84J7k0FxyXKRO44atfCNCKatgRAqVE+b7u6JvGmlMRQgND8LCgRIln29N+MdD6Dz1\nRHE5yFkTuI8e4d1/2J2ggLW4zEhNp1QSoGPH1B58yp04oYyDFmzmZ4q3eNf46fTCxNjbNbZ70bxv\n2jTsnlQ7VVug1dEXuo025Jier+ZM7Yv9SkFrcIMpqgJV1QV5mLfmtdetR0lOAjPBbGQd9vPssENH\nrvXoyv0/R66BKAHwnRTt2RmluEYF5Yym/U9fL9ukBEMlb6gQS81xdVIvRWb35i1fHcC3TwPWGFQe\ngbr/hUBWtAFbXiyHPE3ebbxBbBWoFx1OPMqeO8yRWJ9qIvwew9QPHpJ4bIsWWtrKVi+ercrUxTT6\nZjX2HkpkuNdLQmSm2rB18z/iQbwSzQf+609yKzX2gJm1q6HVxIkPCER3k6+nxxS9O92fsyp4hhBZ\nzGCc+VEYN2tjDyz2J+e/qTI+c2Yef7xmuTuXHrrm3hMjlKWSoVph71ZKFy7fxLuELfwDje/upjhR\nG+SF6JqK9n+/X64Y8ii3q5OVbF9fDyNiHOFvcSDud42In/X0HNSf0GoDxc1LU/5O0aA7e8j1ewzO\ntmsi5ynxAmFID4FpU6Ws3IDo92uIOzGC0TApklj1yGJjH4eD+nRNC22gtqIgWt9XmXHS1jTrLSo5\nMkhk2mnOKuPIXAr1HTuVpckxtYzBYLdZiEtWSUXr7qaetHp9Ew8mNexknse9zVpO8XH6utUVQCVH\nZwKocYRPjgQkbggqbSLdFe4koDQDEZwxWB4zcqHUsJ1vn9YQIGIstairytIhUP2NSTZDwUNlmkqD\nV/XU9q9ps6tfFsVTUYgZ1AStpI2krYsjLAvNoipSox41dR9hq4REN2JjcFVCXQhJsMxKASJFfmQ5\n4kWjKUc4jmc/ln1q+X2Zc86v6RgFP0aLWe6xzG1pRX3z41FCv3mrHVC/LqVyDUUgYpjPIygJoqQv\nUy95yDyTNYFCtOX0bec68fMdI2WJ4qGGat+hYbWRoKFLu4ShDcgC0AM61QWWr/w49vV3m8SvbvBE\nxsGTyrSI6bbMTVsTg7pGfSdaG8zVpGmTiuqVvsn7p9spuBGC4xjQIfvzBqjBAHAlWlBGN9oEt6+p\n9d+lRCg1gBIMms1zI/aWHyy5XUxvlKZcHBkyY4P+2P3yUvlO10rtbz/jcQsBbGxQ1thkTxBJxbB5\nGye7BTM5HQVNK7mECW3O+OHkjlR8M1YnxbGkJZyUez6aT/2uw8Wt63jAnDXI6i2sxS5z5GXcRt1U\nY8zsZlV82KDqPad4kNAUzq9ujPiXzRdcj9FsGKbT6OBaoFs6Gtvptviy3iPGy6hy0oJDNWVapnf8\ng4OQyvsJFyxnvtRIC4/yLD+pmbx0UxafqPinp9etVcWC9Tm4iXlVWWJyjdXCP0qad1u5uf5QwHDF\nwg8CrYvZcx9Vou07sVwPN78UXIK0bwAoNMZjKARRzeM+okOtdzbQ2tdRcPOanMyTBGkRR4iKTV4P\np2jTu4qK1MusTBxUsnkKbovZyPHfuP17ssEm/DfE6bYMHiHvgbZQ7wY2Xse98LSXzl7mITgzfmlo\nroSo1CNhbSTb3VrLJIIZeyxmGxC1vHASfejzPPvU/ugApBAItE4ipy6orZI5Ulx0pE9m7zazmlrk\ni2kYZXUchhYAvl22XM8uvq+PoCB0snSmDO2lO8EcWudQWKzbaA4ayH6sDEnK343FSB/qQHFR92lr\nSLwFVAO5ezk4pZbrz6twDZzA7Cd39kM9Jjz5ZWxjspupLX6jPol4E6fdKBM9A1LMRqs8L7F1HHdY\nAUIHojeo7QIZuuJLP2BLo1CEQB1nvz+5NTGDQGepNc9oCszaYsTGWd69XLfJ6a0AKgcYtFaDoV6D\n0mVzyWvG1WJJqydJ2Di1fsUtC4YT0xF2LvQgYxcV0IBPPbIdvJ9NpGLE1YVHe0EI3Yeds3sVfrGX\neb+43IwKw6LFVmLcHvaYdR7vONcpk4VDdqNHfYxtNAbqBXOss/idtHM8malXb8GPZEE1OA1dEcJC\n3KtZiS3KUhc5RMZzY6Df2GJxRAWkUksV4j2yRb2q5OaGZJ0pRZMjcSDx1/VP8/d2ho1/KBfN0AL8\nIE8Q5Gc9cewpO0TGsk01Wme+q/tBFGzGsFoE2GepRLCyOjJgP1JrGnzp94+YWPOxXLe3URsY2sI0\nvpy+UnNhIFwRFcp+eIh88NuS/UhyLi2SqFJnrXNBK0jz3FJfB1ij/Q/yW7hHdFrR1Ot29OTSJWTE\npvmN92PB7BbLy23lQFaWULCrAbF7fqvPYyyKOLv0jSaEX6gRNJ8cBNyuNGXXJD3q4Ck3SLuPQoWY\nnNQ3VjoZRq4TTEYYOPkUoa17TcnEi8/mF09kdvWPwFwbT/4KmTqDzq6GywKcRBwid0xfGNrUVJuE\nZrslnDPgUkiUtABXUF7thrS6t8a0gWZdzezaekNcjZxVwcBCaa4wPMF+KZ50bs2WgWwaHNuggiOn\n9zJHvUnEWbTjQqb7sQ47WkfrJ4jeFh6ihzbPIeVisqSDffUjWHE/v5LXv3Qcjlsi8mlDHaGPKhEb\nDb/JXW98qgz1zE5E1dzRpHnS1BLG+4HlkT6WCQFowx3uVhq03RB7WA9MhTEU8kYOewctnrSxD4Dp\n5BnHoQIBd62EHQCLBfDBGrWXtJNQiDG84ErMCbHDHHNxhnx7DQ5yX/DMTVeOTh3yyW1e+c3MSzp0\nqUyJ2m/goH4mdKBjCYfOnx3Y2WnHjYKD6MkNQQcIQ5NMKkMzIvdhlxbVSv2KGbcRRao70kTrw0lT\nQDYURj3Y5AzpymHyGeoIeLqgdWRWs04+P5PAZ7tqxBY9E/JLxCAxEsMKE8QTvyvqHonBfTLObiH/\nbdLTdplmkE7YvKr995eK0tHU8Mn8VUjkXDgP7POweay75dWV2DHRwryS4uqyHSyERORh3TpvzFSY\nzJYeNCoqTmt9RWVJpX7+Phlb9tI/aiXpGwzuOcrmL4CGRRv9bA9Wyg0jJaEO5Fprg4G4yg0P1ra+\nIDitizAXvNfqUs6mPPLT+h699mTYHFou+UXI74YG7iHBSuDDyVVYw2aFIVsJWmFT23RF+hXl+7cp\nsGsFF+53SKJr2L8zqD0S0SvigLqHSjSfGaWzQZdKn9Vqv+2zulLjWnKfmKH5aKpFBpOGwf5Xrn/y\nBz6m82ASeKu3aR6I/zEVr0nj87LDvaQ8PYyMXnMFkemEkOS1YqXrQFeR1X0oqcR1RDuOek2ZZ30x\nmAfkfXtarCM1iJ5hvocmUfti55hWTt8ZkSyKeEurh/Us7DpsUXQSSJ/sDLg0I+56OogFyygo+3S5\nWc0pouwzkSQufdD3KZcbIbO5IE911jkqbMW1/p5EMghAqhyPHTPGloFMxXXfzSN3N+Nw58gZ+9C6\nD3JZWxpTc+lX13BpLyNfjyHDuxQCyecRj8hACmgq/lOKlxiQ7bU4g7RMsCB0N5r5IOqvDMnG3Zc5\nGdJ2HZ4MF2kr5yk7LJq4DXnSnDuX7/7kY+cdxTU7s7tLG/HxfA0t5+I4QYQ2zOru5Ea1S1syfRen\nJnYN7XUr0cqlIVPah7bHfjf9idXLyMiqmLTZ1nvBpXn7L+08DOMLkSVUzWLDlcmE7DK32xakSjxL\nGLxFyRt2VLLy/tWr0lkIZQXCiLHNpS/1o2O8GSCo8wtj8MsdR7CHeVFjrVpxJFHRSpasYCf3sqkK\nMHVNUMwoVZYm/HluXtKKGTMIXV2licwqZgLMAIT38RaDUd+QhW6kTvcJQqfH+9wNQ7HJSIbSDDaV\nG3nJVSfKQlwNpk0pNZbffBlx1wTkK8NnDns9xUI5QEhX0l+dSgvDwfsvwqypaCirxj+soxyku6GR\nb7UC3I1QxKtAkTuYg/L4iEQPGPSOesLCnJmpddAo24S+51PpStAHCbyfH2ue6N20sSA/YMjMeoae\nnKqwQtBBXJDU+1VUoqqVnu2qGHufWU5j1W3RFiH9VUxus6a8gUKBRstoJp8OOnpss2rD3T8IUWNM\n82yyKkB6280nNijNLHegfkPi2Gim7USyFL9VOYoxbYPcWIKio1Crfs37iO3hOQ5N+lSW78emB+Jc\nS3NQFAtahXSpw8QjDt/okwQ/6m3LVs+Z3+O8h5f1USefJPUPtOLJ3KsR6eXuuSQXVjJjzWe5F1/f\nNZ/V7JoLwAg02ZCJoeb3P68v0b3mvd3rTeUh73JNb6UGS9Gpm133fJg3fv7BJ3TvnfaSOJ0LQ2jf\nPHE5OMFsw8mtcZIW5TXoLaC5DgxuYwUwmjYTYTjATyikoNNBu0oXJyEqfSGBoCYmwJqG6WUy9BGM\nlUYsM+shYCXJ/tccqTyKgsxsHKeh9MYrZvQwEDpUtpnA2WoP4MphR2JdNXostOQl6p4rFJA0nfMc\nkVQId9O7uPAAe9gKp79m1i7yoNEbZLozy5C8iV4DiPC6ChTr1skj1gCcmUZ3DONdJZj3JidzzjkR\nMLQQ5KIl2nnU/54Hmxk+C5PpU+Iw37ZyyksSDkhEOhN/14FB/hBjUpMf0YiaHvG9ICHcCDhdNvzE\nj6h1iCyDXO3e5q933uiIXeDmwPzNEhmO1b4Ei5h3R/vfZ8Laz+o6bZ0k99gpIVCbF7FqM14EPbOX\nxo3YkJVJPIr9f4uPHiUS9XYIrhpGfpq9TzYhgltwvST/HIEQW/SjDQkjp4xxL51wOQ206h7qlVSs\n1s98KNkeEIiRi7CRcu87ybGk6jiFmZwdCY9pESU2YT1XhBwvE6374bD1z0djfK4kfK3psMdpH8lM\nEd6P6Mt+LYoAfbx5L2r5DcCqOfYi+4wVpGQIAMNGAALcbQA3ECyfoonvwOdQfzSAgCJixFNcMibd\n3uq1kQPvXR4PT/nAzH7xlTfdRipCNSZBqlQAwMf8V10n9DN4FFrVmPl4CLYxsL9tnzgLo/nQrlMJ\n+LiQgWRevy71xxxJlknzxt/j9R0zkwdVlDr79KWzmqlQDwGWYwyYP470oWGoSxEZ5AbGXQAzYXhb\ndM6UtrCgFFveB8jq55Z2CGsXZYR6uApOqJZNokcn0jVENwcLnFRb3PuMTXpO1zl8kN6CvgNXjSNF\nvXTqCZzau3xqNgIrNOUNdZWGGP5hhjegXqVYb8tTbjLZDMnkSh0GrHDlk6KRAhjAripTP3P/gFXp\ns6W1/EB3wuXhVr9sUc2OLBJKpiXmfyXZsHMXHhU+Tb2UfidyLh7a8EYMsEvRGziSq7H9LlIs27Vz\n0czWC3sxS2zvi34NyRmRLpmqSw6E/OD43rwUp9XDNQj+QpHmOBeYL+SpC9TDq6nTQaG09PAxVP2N\ndxXVDUjSMCaV48XcGbxpRrD0/na53hP2tx5QBavoofg51pDneazYM8S400wkswISouynnmwaZtFP\n6gdX7ABB/OFksuI9d8nC+bhHAfHIkmFOyZ5RA4IlQMWVcMVhZzqZtIBQpnsvdP2SCvIgB74+MzsQ\nqRhwWrZJSdJhty9OF8ERoTeyS7gTUQ7UxGutBpa2JgFEhTqwsNAoCWLj8gmFdFBd3y2ywqzwguOo\ne0qluwe8nd80uwa8oU7YPj1D6PyeOB4z82Nb7+ZeqHwN93ESHEgCJax4D9KM5IO52+QKTJySTRJJ\neTUnJ7oO573FXnjiF/UsW3279Q8Suz9BvKsVGBErykgTgT/gsSfmwUXmMbqMo3CrH5K+Asfz5RqD\n9gl+HxPoI2ICViodY1PHicZudI5S9ZXxtEJPlnUuz0+K9tNjwci4E6KyLuWMAG3vil1wBY+5lvh1\nU/jveMSxDfgSnmw0ZxibOkJ9P8+kF0FZYBHXmgQks1sOVZ/2cOeP7H3hiKuhgwHI+aOwh3WwBNyo\nbz2PKLOGzjXVXkOAvlhfAuwLXpmDZVfLX9EBNDKUaNSnl7vl2/dxk4glmA3pBipJRHnbbqc3WJX2\nax62MsZY6Oswnkslih2iSMzsdn7PZ9t1nBjrL4CPFTNPg9gh/DnwZY03vygdoTEvj0HYmlN+X195\nFFac7F2950I0/1VHC9+hU64cYH8HolI3qLTnoOORqtA6+6IGxVNiCVMceaFQF4C2ygMxH4v6YKl7\nCProsDVsIZPJBN+VBY46N5jYJg6J/Asb8twOKbJ7hr53HNGTZ3MspYQKsmIe9/frDmWbr/GAILVo\nowT0Ho1hLLTJdiAz2fp6f8MJ4NGVYffRyY4K9jzsripYK92bJU1Uh4VFtl51Wyj2+FzVLMVuZV0w\n6hwAckuD00k7xtkSXclYbauoLQiH06T4oIkmbI4eUKg9xxn+PR3FTrouqtsMWpXOZx73xb6e0wpZ\nyuaQQvVMxPM5fl3lx34s95JxrYOPtKK7pm1whY8zEBA8vQ2hvAZfwk3f/L/cA9IDyUCF9ZGRLFz/\n2sh3MCD0Qqn/xUopZeUI29BdfNhbhK9wmJt9ABv8f2SLMGm47IRQVTRhyRmbzbFlp+MOAqAVlR7L\nk1YY8/BasilsKigzfe2K6OeR0hj0p9WimCttrWBCJgvGjkwIfqdYDndYinHFP5r57EnZIE5ZgEIs\nE0yrjKBe9D1/1CoCte8aC4DOIyDvjx00EuLrD6BOz2xT3Ep9Of4o5F56/8joawKyLkNHWvtpPB7X\nCT9oHBsLO+W0lwlREwGpHvPXWVc6QUuKffXaMWMKcUz9d0/tCLSdU/8MvboW5nPOitZwbNLOUKuK\nsGkStHq8WfnM2Y0jm2+gOLv15XKvjb5SFLjiK4L7wj1qHp2En9ghyeHNjNcmk8cbbg5QOiPQE3x1\nS1FszMmHog0ndZgqNhIjpfejW8RGuN0dtJIy6aAN+jJ6ZQQmFeQjBHgnwMqBuUoHR35ekRsHeAzR\nnuLUi2PLz2I8kshPzqqykNqd5UMOedp3Nw4zb3CufsFmPRIppJFns7pJ7LkXWeJQJDJVSgC3482M\na5d8l8oHVMlG0b1uFRZbb87kQjTXavN2T5dSVR9YssNlZ0f5LT7t5UUCfL/Q8Fl00j7KUMwbs6sN\nvUEo7/70nhdw/W489+QwT1F6FJKMdLk9uM1oyVSdhIv0geLPCmZdeyjBQDzhQT9NWZhiDQUi8eGJ\nOY0ekhyWl1xzV7THdeICDBA1mGLtGtc5tZZSwxjv/zGmViBw6VrNtPOZM6mYpLc2WpeehMdTkLoa\n7US6MULfodd6l2Jf0JldUgDdhwxpceIvXGp9HGrEZXauO8VWgLg4I1Bge3MCRfzqOqPj/kBMSdtc\n0TlEMRtN+eDVab2my5F+WBu6/R+koi4fGmTQsoQ1fmc/TRVJNJfBNeACetaBF1oPVtLxvU/brZLZ\nwQITJ7upvXuowvpmWfAd+pl2MCYfIloOyJA+lyyGqMoVw43/0whuG0Rk8xGh1TgIgp1gA9mQ/omn\npZMLqFHyhuIukIlzBvbSVefgXFwDMxXSDAv7NC9c5aZZgvzwx0VzSYCr1HYXl5i4/F2CWfF/KCWF\nCUfQ1FD8PzmKsrbkzRDZhDXZ102nx91PjlADEuTzWCxxs82KV8HbkqTRQ/R0WebGk3rWhss+GlT8\npBLnqW4ktrgoKXGW4+iMNdEIXMCBSV0iDjI/2VOqlk3jc1y+VDmbmZjYHsOSGeYZOSQOyyqnWPAT\nCLMBLn3geEu8dddv+QH8zmjaXkIsUSo8ZcYQT/6eog84Ukz6MTUwwKuTKUcNGhdngu43JlXRPEz9\nSGrjUgndLavfNHLcFui1DwLPWOtNBX2oqywpjduPI3KJAbfI9SQvVYDM3/9TsHwOiiMKvf11NcMk\nW8ALOpfVWieXjVOEWvteoB5sAZveouKBMfN70aUSt4E1DO2Xg2hNptZlpb/o3DVi9P3uPt0Wb+OY\n2nnPeVLqd/V0Mfr3U1bxObJxCifXUO5CbX8Ql/V0R8OO7FK1Bdq4JXwHN9CpX56AZN04sieNvAHD\nH4RwwzZg9ECl6NZenONqxXZN+gjuqi6DqQDSA2ZRs4Q5f+Kg0r43Pjo4VvP0m5AebrwaV6b7V36G\nSvpdknJphWm12EjUMJVY85gdIH775SsGe5B7bTAzgrtpDGp3PsaFBfJFXJBiSxp3Z/CGWEJHJFH9\nUG/ymieLxVo4Tqp53AhS4zH82xhBS2hDrFHHuHqx2NzFMM+wFjmAmrtew7RcWg+KyIDJrgzIv8ET\n+Tuoqj1A44c0JQnngi54sOpwFCQht1Ps78kGMKyBMBjwlx+Zg5tmGepZgzcw0jKm/o5h9LJwmnrA\nTTJu7oSMk2vBv38fJJPLcP/A9xcc4wUyCNs0lpDbRIbPF5X/azu1zGZ5yvjbajC/zZatYaonwEZR\nLjJlUqyeOkS1KtzHTPFRL2deXP048X0bzd83bQlfHCMoOG85lR5lrVTNc/uqcGBmV+kHDixO3FjK\n4iJdv0OfZuWsJIMp1T6l+WUW6QiXlMjQfSiuLAoYLebvDHEqHHXnAT+BLl/vqN8XSuGzhoSVkcFW\nH98/3zqq2kTXV1f7kF6bX4VWVgkZxdO6xOaJRDbDw25mAKEL7nS0tg+Y5pbV2aRADiFeAIByI+Wc\ncvlUvAaw1i9kAtVHWheuI2tjldk92EzZYKRcVqwFJkwj5ohOekiOx0xZXXpwrDQjinjQSFbs0GLD\n8I3SY7Mqh8pNtCtn8diFSGJniJQPILkSY4GXra9dvHjNSjES13FFtOJTpjHS+SxaoPwpnA31Gvj+\n60G3P4uZvIKi9oSat3uYGLjg2myicDziJOWVzB1VT+w+4TPKjIADeYfP6HCHuFNksiKgVO4A95Ed\nj6/8dHzU0eYwOGs2A6c+41jHBNufEe8BLd+Giyc3d4M4J7n28jSPAViRq22K9eEsLWl4VJUKTITM\nyn0KqF2selLtrf1L9al6rNLawMEwWBTEZpDZEI3O66OCRE6iyvUCB8iuvL5cuOIY/yj/mnyxolyI\n6nklPuKSxgh/51BSrO/6JSVRCXawUqyumKlIZRNo+igq/c29OSQdKJZGiw1PEzaYF7uwweUeEjPs\nz7Zu3mDLORcJexZdLE3+erS7GUhHNvCHyKJhAl484bHtvtT7C+Gs4KkC46D2NGRqtKQTR9ESIU3W\nU5jOhFfUo4dV9S1E3pEHej/kQF7/CM/a2X7+RPROndYtdPedT3EgFKDF9kULcKZgegnB90TLSukW\nWcKXrCusVGar//8vzwi18AfpzzozftL/RPS3ouTIzX1Nk4iogxekTKtPBBUxu6RXHz2xMrMa+0vu\ndUGCX9eRQFvcYm8IJEroSY/EgvxvPM6YtTP6s2LZSJ9HYbi3zeBtXspzwqN341yDbf2bw8de44R1\n/urIef2lTwCfYNjpe75wbVBM9IVf8HFSpt5XDBZNRwky9JciyXHOJTIrQSO+AQArLzqSJt83nrXS\n/Ovi75g67QpueVciv8YpQGAy6uHY9/ukjBFfgNv7ddh5+6pvTLd/RexsaBFtjb/pMbpTIPfRZqqt\nLN9Ns6vPlhNEOFlDkePwziXvfON6b/LgLqk/2s6GCyNR6MUidWzbVDtioh+7yeFlEwDWGEf8HYEw\nrbVWTNUDwD3PXssU2Tf06JjHMXn7wPD8I76q3gq40vHWnEJcCbx2xDo6tjGJ2iVphy7JiZZear1f\nscg/G3ZgbQTuPbj7BaltDOhJzKHQjXAmShzSj8nHN9MljN16JJM2TCveYHrXvkQAvhWH8+boUHzF\nTDh1i4oxSR/nfcppsrGtAQ8nbjw9wP6/HnOWv7oSjFO7Xnga2f2VSOVlFz7bXa2/Yr3cBJmU72ag\nW/vFVCQ56cvUanmPrvwPJwWT+ZITz0jnXJm8JzPt5lpzM2uYOjG4ow93vMFLyZ3iCNbQOQcqm3Is\nXKzmmmEvCNY0Yx4/xDlWkjDdO5cETj2qMvTSt8Lr+VvJ/fI/Zx/ARTh+RBkf4YbZ6hbVH9AaV+EU\nDudM9nSHxFQRNRHTxREXqjqifyC+iAz01ThgKfoq6jsYfzdsw0hn0/W2O4wT3XCT7E56Ig1N7AU7\nOVr/UhUQlF0K5wciGd0n+jfxzcbXW8OhSmqUfQa+REAsrukXlN+YaT7IaNb6BJpaUNhDmil0/taX\n1rcTM/QUAywluMEXQMc0+WzZtyg4vp/RM1eqjQULgHOupyiLSV7gKDe65Mv4eYc6xgS//hH/hyNh\nnWxn+QJ/bR+tnUTZeIENBr0ouHQ4sYdSVcM/OZWei79Spqu0b/GwLV4WB9JozNjqyQoF2RJ2zcWm\nd6dFVesWCA2vyzpxbuwGU+PsVx473VTBErMr6TdeljJha7zr0JQH53GN5Q+HVucK4hmXJ6mJM9KF\n9JLWb3OfpnhjHmovBbKBvR0nxRXUivWLXMW5fpTBYoVczZeD9elpgZDG/ByodKp55xxr/8h+yZMP\nH4KplUh3Z45VoBzFdARSh4mh+/xBetTBCdAMG7EExyyZoi4Em8mk4iOrvtJRIZ6Q6iDqDWVo+A8e\nWn5fhW+mFqNgiFNxSMXwKXDKrhandDjRUtCj4QPpQY35H/j6AeahbCbueYNzNjxNdqTpixvKLdwE\nrTK510q2YfBVaPpkauiOBk11fybFhQn4T7OB6nGC+4Dyw/KjvQD3kLk8Y3u2Twm6HZ3K+zzEYz1Z\nuAAtA6Lls5oQ6OJKS2/xeahfUH8LAY4DMxj70oW0KgCjuFh5PDBVsMN5/aw8g3+Y3oxmd3QEgZJd\nyQvsucQXTjprbH/myIYqCBmeVW6eRkRX1EAK6PjnL8ptuNcfuJj9Eelk4X46UZR2bmy/38asOOPo\nBxMqk7/CoNpWIc+y8160Du9KB5wZM92u74S/9Z0+plrlMa/MTftbQUw350kOtPzZHbrMCvVWRsGZ\nViN2LgZufDkClgstKiBlc2c3p1MsHVnDjSG2FGC0yPlr2xnwL6QjC020GLiA3Z6N6AvDZvhDuow3\nwIyfBI2clIJlktBYmTq80Am4uxHla6YszJXLmvmqM4Ncx7QwN5YlBG8H9o9znWQHzTCH3nNABkr+\ntxgPq8457QzB0VAP6PA5oEAkthiGdTvU74hZ1dfEbrnyT1oVd5LDGuutLBh2nE3IKiv58dqtkBAL\nrQD1/bt9zQeGbrYF876LDkhykygGfIkSPhUELGdLX+l0rYAKxw48pZe/hkhkXT3mxNGcKKkZNeJb\ncpGyPTJcHwuWZCkFvBoNJ48Y5JiIvM4GMsRY7wrFSoKkhVu+4OuXT/5KQO++SoDB3ThKnCrTGY8X\nVx7ughEjO8OOunSTW1sXYPF48d0ZRBPgw4ZkBTiCoNoKGfCmvKzNpGQWuaWeZ9WFvbvLy4WC/dDo\n/zsBMqE6OA9VYqRBW4QiS0LpJ4eNoajQQRIl/6wUt8peCxoTzZbTOCTuA45bDYU7sLJaq+NviSvT\nw5yxvgByqEk7cXrD8/G0H5XRNWujsxpRt4BoonSNe9nwQ876qDQvrDLzvrdqM9z6swLnALzX3Otx\nWGeJy/Ff6lSnhwmYdxRu8KVR/7l2/oLBrHfPa5fhwaUmzocijAudHvSCffN2MM/aM+/tGmxccOXJ\nAZKw+kNPqo1grYktt0iV4DqyhKAAfrvw64yLhFdZhFgp/s/24jNan9mWcuhvZDEaN0h+MfQvbEv4\nG1mFmPEC67SgizvirlqyI+SKXYjiBftUbNBt2OnZsQObQC8OTvxD5g0FzZK+7zR6iFq6Z3crV4PS\n59Q2pv2DgOieRvv+Ky6AZ9xZK2EzZ37hoxq2X4hCs4BeQSJXxImHEJDpVbAMlR6jGXdbtZtTJ8Au\nkNmMhJ+r7rI+29xlXZaFWSS5JRqS38Ov0OOOE9gvDUvEvNyWE+VR/btjrWPFtzyIPlPkPBkzBSCh\nYOMeGMqkdz3Dl1IrVgE8/Q3lNpIRTQcycOPWPPSdUEcCIISjz9VoZe0v8RJAiNeujuJHRWcvIoGL\nRc9eL2oKcKEqL3OobVpjptRIsr5Sr379YjTRFBdYK3nca0XrjuMnQ4oJDPq+9CLVawDqd8ciYO2s\nxltJqiWWyVNiqfQK+aUDD73izIG6UJb1x8Lt6Ecw4hzt50mvpD3rmX5Xwfa6pWIegtIV/5ii0AHX\nTpCadHeNDaaAR4tO2Pozibkk94+1HVROFE2NBQL45go1c/qqxIZpNrAGKP5l7dHBJ2mJqOKShsjM\njb5sXQu1DefOA2gLddoIlmFsZ8p1GJLZOg4ZCUTkh16np+gkQKNMRCOSzWmQWzj2bkV4rnIdT8oZ\nFkME9wbItDjvM4U99FTCuZoVCdI7CwG6pHRHZqhPpA4O7jkxcnWZflhmwPawhfLfv3ruhxz5dbIi\naCyS+h79kOIOrT55DT2aLu6SynK2a4qrYan9Qym28pg0At+w3PE9RcMK5+qhaJo2ejMxtrhCL87t\nmiJOOY3rzrDKn7ASE86wpWcqrKsASXMltBGzcfZA/5avCPigIpzjOY1+nsoTxjcXqnB8ww62SGzF\nBoKrb7FmW+GgWPp0Lzc+sIt40+cIL80tNWeKAKq9e3GrbOgsG3E1WmDx7odKFplaUcJxA6DfrkFg\nJWPDyC8XH3zvj717NL9CG3kOonXFRcowYa/yLfjApHdcaGzrdCjGHKd1yPGu4Hk0AS4c2+Kw0tw9\n8v53szPJyiv/nL9eeDlciGuW9RQCPdby+gL+l2X3De7sC+sMNgfb67xJeHc24QiEgAI0xILuFw5E\nFUzYEuVYiL8/Q4M7xm2xZtmSFfs77xOkq8vYUfDct3muH9eELU9Lks4bp58VDa1wHDzH6lWwKSAD\nUlB1cqt/weeRkCAFWDOGOB9sg6pDg5CbwTZyyazeIiQPd0HIFIgcZLqVvpRpG8whdIWWHtwvXOX4\nEVaWpXdSS1m/+sBHWPXjVZ6F4/DXchGkIaJ97lD9SjNfYFdDkkOwHUY7FQArIXQ+BosvRqlBJDOS\nD5GCtmT2K2OHnW702RtggYl2Ci8YqhFxLBmFmiVVEsh0nMksJtBRrOltiuKukwadevmNOhJzUaZQ\nMv5gZ55iYTisZFABB7x1b305Zn+L5i5z+1R7efNP/buqq6HWE3nRfxAP2OPT+e5Hyj18mxQBZ7s+\nyh0DIhWAJmXtkX5UICE2ns2n6bjMuSNCzZu4FmxWC5wN5uAWEARsiDrK79XfgNcWnjnP9oaFzQ/y\n6b+6EQdp+7i31iZ9lV3JSfKSMlhYob0UMMscsN9Px5TrsTA56HgaOLCtg6rKfW5eZP/k04zLp5cV\nMnmnqyC6bpVKrgfz+bX5ygWMdTqJITaTpKqcrAkuRcZQ5Mq7rVREu8FHmD7yq98ssNwHVPy5n95U\nvx4HkLzx3KlEPz6kOSVz/CW4/KCALJJxB0eoXOXwv3IUBja1FGeU9SvLJXpd+yZ9ob/6GISDc9IV\npdCWcw+XxEeet51zqspO9qX/EWpYj8PvoXhKmYe4cPV5bT1ZEqphf09hpVMC3cEW0Za4+5t8v/6E\nsIZuZMbC6Tw89qZEGz3NmMAzDUaeaVcTRn/o+WpnyTKnf4wina14o93K8RmmwrLHWW1GvaOFUA78\nQ1yLu/OShISQlTayo15Vhorb1xgvAO6e4hdVDm7ekn15ukSVpJ7r07O82FDinOiqqfdB3aOXDQqE\nApbeLs/jFhJL0EN/FSpRUHsT+3MnpkzdxgOPPvbhi+qllVlDCCy+N3eIRNTYvqGWJvFmJKida+ue\nzy7cEaGO65oUW33PZgULgTitTmFYWIyCegpEK+XcPpyjKoWEjDQ5Ncuusi+eLMGl556BRDinenKy\nZYn8iYWSiricv0IzPW4Gfmm61HdwQQbXT5uhcbAODwsGmYxZtmH2xuWu3uBdoqoSSD1pkeWZxmjG\n85w/hfiRNGP+I7hBQyU6G14MS56hENMb3Tpb5c2iEn7ivss5H/JFtqIdZp5+6sOKv86Q1stBqwB2\ni/rgl/pfdq5fU2LrMd23MdCAbFJplrCow6mTN3AKTanC4VGlDTlT0yuC+fTke6/52BG6wQQ9WdVZ\nv3ziun6ykreLHVQEBHhpBJY1R1BPTd5wlEXEJE1ohiS3pmCMPVLrVhXIVI8Mw0oRjXwpcZY0/4lI\nk2joIBVIzTwZ7K7Ze6OWrjqlTmnQubrDHsgawcuNUYfg2yGZ0Wv5zgObjU6aszG0CB3rP0RuQ4x5\nBVr6r7kqFdUdE+29L5X9mCX40WaXB5ITrA42ckZXHwnd2pSj4aBtGv0+ji7tgIszzVn064UKzOQd\nNrrrncfdaIfo44FbUDKLch5gppbZMTSKFaMtgVh69H/2Y8mxOITEiYhvgAkRqWHMCjoTTBpB4DR+\nE5SaDnWpMLy+vKR4J5CW5aeYbxZdKRSGfiuCtBy7k0cUySQVGRZZdj3GZGH5+jvI3YGkvIAi7Sc+\nUgFVlasjMv94T4WTPSoc6o0m9Ui8Y/rYQCMMS9DoPXKfbyiW00BQBStbeo+RLO4UEMQkNpuhVtk1\nxES0mbW/PN17HPALDkJVb0kMc5220mu7asDb1p+SwxJhdumU2KV28KPDKaE+ySUq/dY9iLWBlA6z\ndGsi2pTz7x0IFxg28XwMeL0Sw/iijP7fco1DvCW8Wk34/Ne/Tco51E6U1WAebNBu9fd97kER2yMg\nV9iUax8chKnkzb25naCY+FWX1fCz+MZrEckVUZTCPiL2bB3l+gsYt1uku6cHmHBqgA/lEAebEp3M\neeJNBVES+fk99+nXYcnYgrtoaNXMgR5hKeMXsmTY61SqlIUXywqdIVgBWPGTo+ruoFbshb0ltv4K\nqxyL4978/J9Nc+geqPtF9KYTN6fiaWtCntYCgp84bwXL6RBhTZ2SpMKpu4wWk30b3zKzhvNUyuZD\naY3cgTi/FVNuyug3NT9ANZirK0BBLjSIKE5nqtDFaRuzqseGIQRwKK8Gpjr/ft+2Y+uY5c2cN/j3\nWCT6acaOdV3T+kDPJu1qqr3t8SYREj/pERB0FSUZMecFiDN0ZHDOjdfs9hevxvWv4WtRgAyNtfEY\nBNRngFVfEeoCTps4uBTBevJwGvvsVzQmhyIahfehhl566tI5pb5CMeNmpoVGTe8tOvCcfo26Q4LB\nvlROodijwReJfm5s/UjPBXfsXqbMoaHv2cmzZyeb2jXgMbuCa9LBwYXl4/ngKEA1CKDlJssrAwC+\n1Xb3GaXoJ9vAR69ZI91BLbb6ETJqhuKlXjZAdJhP9MFPPy7HXhZ08Knk4O2P0bcJCPoLU4byMo/s\nzFFnYXyZ9ct6SKUOoB4dqQthMD3z6NCtk5Fu/IcTT4DRCv/Q8II3kK1rKbKyqmIjqTOlGuxo/JWL\ngvInnxTJS6S2yS3yxvn3TMO8y01xgmrRxcXGODUNCwxlO4CklVBU+dwyDJsrdiBAPY3qVSOnwxoJ\nEi/7v2HpvIOSH7vXhG+/wfsAnpb/GX/sigN+KwPL3Xzn0uUxWHD+blnjO3qyIotTMJqdWSvSTbyy\nNg1ik++spWCjnQH85fU9TPMKNL/YTU7t+f3pET2oxYCBANIRQbCpHKOSpBcRRm2khlTyEKku0gDq\n3nv/zDIFB21kWDQ/Or+rw278I8Fj4yYRN8nKYUeBrY7kGrhjwYCyhGaLCAeEiK8Gm9VZ4Y7iuPPm\n7ER80bk8A5iuD7d0ane3fy6vEkEmcpmLfBpSPqYVrlekqNPT40bfxMfmqM02S5sXYoOm2AuhrY0W\niRZypEuw7f/riaFz0zHo81niLXBfMeamWj0s0eyGJgzxnL4urdtSL7bZHkHxjxmHx6zuAuW+h1ZX\ndJ5T1+xpIBbWgYEjPoz8I+EkKMPXwiA7FZ+kKZMvLJOR7s6hW38N0rvDftA59QToeXHex5eCKNQf\n9LwRf4dK+3dFM1+oE6t0krxvcKqk1Qo85oAjPvbI+bpmQaKFe8BDcUvVELm8ntqpumqXjvU50WmN\npKg2P9FB+kiK6rX8ovf2CYbzJKSThgRrchgVwgYHQTcmF1rRK9vVjke5UyCzfYs54n8zz4q3Q+7a\nvM2Ol34FJby6bEpHyb82sk3OUuehGsYBVXmtf4zB9V6xmTXCr1eZmAXFyfUoWDUCsFUpgeHXnnlV\nGg5zr8jVpc4pp1ejpRA3aYgX9Veq2bHLErXRntp60oZLhnaySf6GKgJnd6DLNvM8PAXhT19z4rtr\nxCZpzv5iC0FDcpw/PN+xkoObQfEHkhdhGeVY1J2/Pn1QQBmVJtYRIMUCxtiqo/QuLoFsFFqCgrqr\ncErrRRhm7XcsVWE9fzB9zl+b25Dx0pywo9aeQ4DUXJH0XDTAa6qNcSkyEhLgnJKxX9mapcrBTKgu\nIUzOnLDi9Re5S25XvECD7qEgyASzkPU4SORnzsbhqSjml1Y3AoODyVVuK9UBPyYDFw6lL57giXMp\nc6jHyIdKr3y65UZR7C89JPov6niYAh/qWWauh8KJ/Dm+VaSs15B8FCGc0XJt9xADcB8HbovCKM6l\nnhY3aTIPT2uQmKwiPrqLe0pLueH+Xq6Om22Aqh+WtKCQxOYuhdsMKle4eqEvT+pnlKTmSZJF5NOQ\noc9r1eBNzeBHBcGN45GgCI6DHgDNdlw0ZJNHZ3EbG+kVnWhNJ5WMGuSN2mFCWbHyBPTe3SVCB4an\nWWSPd3X2nDX46JQmv9v1cD48nr0ZkzCjCmm0xmtosuze5xao5AZnULXDhIO54CnP1wpMPxAvvMyy\nRMEQsYr0/YjPf+kDAD7HZUiuzvidTzrylyoOeVurjnmvu7nfVA26YHiQi+Zjl7txzYBuG+Xqk8LV\nRK1ZRlSuJJaNk7KeyVzIPgM+TxmicarcSc30pjvxGeBB4PRrM/qhotKM9LBmwzHDk+HXQmhyDGEr\n0zWSI3foaeNutJF/hbpmZoI7uxEZ0cD0GmDb8SIvmjsshILbVmrrYfVGeyrPPD5IDqr7Pr0pxs99\nmOVdfYVxJzk6RCNiv77w1kOVNQOqNcfYIQLeEnEu+RSiF8V1+Yq1Wp22n+sDCxDhElz2Dw7f9Qpv\nOUyRCvfajViEfuJXvgnYrHd2U0DTnMLTL7EZJlg8OgvrQ2AQENEdIlk2Yt9AqQiVBVn7okDIYZTM\ntmo7vYWLRHAU3tWfG43ak/Io3GS7ihBOYwwyCbpXTALZQfTB4eg5EaqhUyzbKlI3OUWbahWjrXUs\nx7vRHclU7aKO7yxqT/4BOc7mkh8XPcDSb6v8Oahe17lyVMg0YyIBMgaOgayEUiP2YMkeUXnRzvkS\nKNGr8brSt/ZTB2p6Tmm7LfBPuNpD6pUnquY+Zh59CfkGMRfBVcArXqN+4OgQL9SyDIsK2kUfsCBa\n0v8Bd7BtkBMp5LTWmC4MpgsO/axdYGNXEghT2kwY2CuW4ME3ucq9O8sJwQlDMIH+u996d/MZ7crq\nw1vEn7uTWekijGHE/XtGvw2nhI3l4Ah2HaH5cVTHRKALOxOc86aBYQQ8LEdqtzymFPO4VVvl4yx+\nuZRw7j+5K6bx+KdhTzug7d+ZaYsolMMzoeszkqtiuywf4FcOPkPfxOcYS+kYtnVmyqR03EMn0Zc1\nt6eseLfWp+tPHx3gtEebaDTk6dFwjA2xw51t5A7PsLANmzsoGd3S9ePKawANV0v7cEH4GCaUOBxY\nM1xZ96UNMlP1rypG0+0sYhexlXt8wEpKEH25M1ZT1GlefMXoSPy4rq9MMHNjIuxtF0N83FSN8l9A\nuS0VQVJHeGDEEYJ8bcsqFn6WhKumarRPnEdeSHv7kwEubCbPPd+mbxImYIrnU8cKBImPE7KiACj6\n2bmv26Qf2hku2R0PWHukIOWNfDuI6sS+FdlI/zxn64DYp8ZLt90maA2Ba2zI7HF6sCvNbnfREMTj\nN7rMwI+xE3V24FLxryRTW9cP4ZAaUHoUjcUfY39s0CWgrurVn+F8TRbYBcPH20cqLnZ77YbW0WC2\n2b7DuUsb+MxLkucq1G3R7QfTcjUr/7GFEuV2ycguSg3DPEa9VRGwtVnD4lEIWixXfHqoQd6PXnd5\nPUCzvkp0BGLmFpok3SFdsiLFok2HroJbe1ZgwECaYIwZtIm5fhjlh9PfcYl6hZTsPP1Ib+H4ZmR7\n+AlgL/G9mCoWpprGPkgNQflABpKUQAjBc+dG+eoOerJK0KoDNtbeE3DLhDWXuaU6ndI3SF4EG5+w\ndOjieeO+LpVxn790FerFFc1NFoIhiao1Ut1fKsEqDrtTSRGIskUevyaLk0gKnRNvLwNIUX1o0uHJ\nB4P8x2I8v9nECyTihsHD8Q1vT8c1UQ5Elxhs7XnuISAvGCXkJmzqal6lxQPooHPJWYW1I7N2kdSx\nSl9nnJpTIn0mK5PRaxmDF7d9UCYSuAlyGYl3RH6gkLAeR+Dm/Q8XWG4lvNOKIQf2Ur5VYor+K63E\nXYCx8XU1a4GKoToC1x+973SMZLVoNG387wMrMXUcNW7XBXenTxvx9qsU9sS1zKKe2Sol7UOmlTMO\nuMpXzyA375AS+oOQ9TJ4y/Tqogvby6rO8LAuJhrUfDDweOHxTnrMTo1GIi1XzyW0Kuobx6/X8KH7\nPr459GqZUpkRMpr0iau5o9i3e5/B+jaf829ZAjyZGLfJUWLE4Xi5o87rMMu1Zpl5qWwhMpSc97Ff\nNg5NxIX7PR95J5Vq4fSm1oECz3KmSwuFk3lzHO0sblLmJrNyiXXJfrgVWLfxrpHmnoCJWHWz9rzq\nOJzb+VTCjrbAESLwZLRWix3D3t7vXPEK5BVS79qUAJV0AvjZj7UrMdxJfj+i+SIy3WQ2RBRVXUyc\nSSfa52HoHyahNXP0ol3mAU4aBGQsyn4VClxg51rYvw9Z1J3EXErvG9EiYeTzDenIigzC8Ht6Efxh\n+x4BjPwWDfdUOs40YpMyyYkVAIH3WeV8OAftvUbfeYVINsltnBtagLsyaXBR+4b1NL36SquUXFbo\naHARThlFAEjCsHfMHGjWzxpfNDNbys32h7W5sXU147eTjJEZW4a48pitmN1M1IyoYaEqx//9xR/W\nIuJ4UqZg4UIeR9IvDICixHS35WLHAq5zOyXjQtdwDc8b4sSpoKBL9rR2tbtXOQDYGGXO9eBviV5y\nsncpPOP6KQWM0yrwrMaeV3w+e3thp8LIfkFnAFGNvdIShY2pH3NGezBQy8/Oecvycuv87pC4Yr8D\nV1hvoOYxevc/Hq0V/kgvW23raQGW9OKCnYB9k8/rcdsOJfwR/gG9w2lvu2d31A2+zJgdluMy7twC\nV5ngAdj2IzIsFEC/gkCZ+jk7z2diq8HuDGRbUkBWRKgWZeIQ6aOJBbvKqno409YMifyx6LE8El0/\nw8iHxkb3eb3lJNKV/+Sk+sY3pOLqfLPyrjWWQtuYfjyEmf8lzo6rZW7mG5gRD5a27Fjar2kSxk8f\nUvBlF+c0gkCCZsIvdeUsdFwtKqg2PbC8a+EhyzGTMrz1afQmE3OD2Dkft8NKEBf91ix1oYj33ISy\nu+Tq3TG2cEMfDH8QYyb+SobCCvX4EIDjIhSHHI0hl2rRCAQYux6JY11EaWjpqNZW3kr1y4Ip0La5\ny3Zr7X1fiqsjzqevGyWZML6rwT/n1uwWZMR9lJVvTvr4x2hsepZgqyQhdonm2zQ6QitaRPnh7rnD\nuATK9IlhbgN+bRzpHG0JI7iKyOfRy7uxrF+LF1fB7a6cTUt6AmGX3vdw82bCkWDpqm715egxbzLb\nkUOyYJ1N6i+717eUDTD6xChDr9NfcUGfhSCbaIWYxwa/86UIQMvwdVSWanTILNOQL9lQSVUlWPkS\n6QRTsDRR5mlSzCulco0KfM6DSOeCpoWJ/2urafm9eM4aTT+a+PRT378QsS0GnxxjSkIhgwzHoh4w\np3+Lkff7emp8jxK0PKRGQhZyrkPBf1rHjE19K/+SgwfPFy1o946ChHtCTnwy8aSDzZWEc8vTLYnt\n+t99k7A4jjum6I7zyAqjkq3yrrko0WnKFRucttwfx0I8HdMhKylJKYnBPDqz09Kh33lPN/ekRT2c\nYXt8BuiLOZeefF/R6It2j/oufb65N+zG+iSq/pnR+ICgeBU6Kck1cz+5CeHFcOC4TDNX7UnKwEgS\nLOJc7hfi9eNyEoRgAcCPNtQZ5vuqFxMv5nFJC0Z4pYQzfQzWE8EDww39Y7BCuTiz8Udpbhdhj3FL\ncoedNa+ebJ+UY299sK+EAbyYNGe/yh1JMa6fwsJNDL8zlT2PURw4aHcoN7UhnVYzWFtl9R8ltt0s\nuI5lZSE17lyVyYJvN5RE9tU/U4bl/l9ZEdsOAIqQn/bbHMrzq1WhHN9Vldx16f6FecRXKNdf+YaR\n8wMVZQ+uVwa5pJAZnsWm1yDt05mNH9ifzMNUFmIA+wiUQqRMhgbNjBHpC7ShGuiD9bLvL+lfeUja\npO/ggqe97Qenu1YbPjhGkYvnk9SRdG37AvPoVMh5+0WNbZHf9N81aeYx966xfwjaWbCM4tYt/C8A\nwxV6WbwYVRGlMhR4mHWjPha9NhwFwTrK4A0jgmFu2aJfNLjy0FFSKfvRE+fKRpq98HQw4kreyHxt\nqWN9bZBuzuLAG1B/E76yxcvZp1M0TResmG1PV9mBZmMBqXHX66e6KuDKaWA133itbtSFQ+ZAJk3A\n1EMdJbPNLiuOq39+mWe8vYtNF8BbgNKaTsbO1uj0TNBu6a9pUsTG+/Qc4xMupQaPzHtQ+efbB1sf\ndLOGjBv53/ngAeALxr3fTr4rDBX/XyZ83j4oHkhndIS/COL0s2kgVo7TA3Co9YyjT8ek8X9twkMH\n5fkccK37N4gjuf+yZGsVfULw339KDRIP9j/30TUmDeL0v0IMGzJrZsuQXI+dEo6D0v7EQeruDTvF\naoHmOzyFEOSKos28/06JB84utDnbmalnwsU5JX+67sedPd3445hCugJieDTGIhFexT8uornzL+O2\nwmvfkbjYHQ6Rm/CgEenI0uU3BIau0XYqKXBSD3ZxuTZ/9aLfpjpK4yklxP9CRza1rtFlleu1AF9W\nVZBrVN/XNjbae9I1qoxQFnDIWRRfGQW2nCd3whHAwyLnQclD1Wk4u9Q0xJWDED+mF5sA8AMb7yLE\nfrreu7K5X8f0pG9Nx6EO+s7uSQyqmBOwrcR5Hxw9X+O7bt1NEEaz0Cmizbx2kvhS5wDo/VA28p8P\nEhHascaJotGWtVdWR4nMsY18b/UjI8zVyl3kel5Py6B3ZNGDLjYr+GmjCZZdeehkyb/krZOqUjhw\nmY9JLRcrkED1OlXm3JwmBu6l5k+FEw8oQhzjMqMi3y9PeG54lwC66PooSwZ01iCDFNIhVvdPpwuB\nP49gxV2IOdRy0GYBZXKSrbNYM7IlJEEoYaPQMgGoxCTgn+Z8qk56mnwDs7bbtPykAQtNzOSmZKyB\nfGddKKtq4sWIs2PCYwDgOIkeY2XwmPHrzTd1JDVHz2G6t0DHXKKK3ZwrcrTAhVTzD1E01u6qVdiC\nW6megz7PiWAr+X83X1D1NLdIi+PHnHrt/lKwTiLiKe6x7pcGSsjqSSkvFu8pHLQ/QZVbv1rTN9dj\nGXyJPqRZdYq33UssJJ1PBBeKOJXqTidRApySgqVldSBhgMwYx4nVI2e4qoOxnn6YqoQ+v5GkTBZF\nuxPchUUXJbOHaIKkAN7OWbtl7cAJr2tAPujnu1hpP2/SyDgU7a6J+HEDkq7ahOjCnToB+hHCBT9e\nksHMDRMtDtDYEprG/PExG4lKODUOqAoM2oEyEh0Tjtzh9p1GFTgCkdWlF3Shx45MC2WHG8p3H5/B\nfIEwHJND2LDvu/EX6CplyoSV70ntRQJg50bY7v8bTd1iYnGXBmubP3xbxbMkeA0kFcgdhVZ9qM1v\n7JDt9pIOycbzjqpI66UynoiFANoWxkZ1mwQu07Qp5WXNYlvjJaE8lg0/e4P4C4ShyP0Qv8/DtEIh\nAg42vx1yJlKKoZHAL1dGV115f9ErqU0hN2A0qwwpLFqT2sD73CKXdzucIHSrCHyp+doYIv92Szct\n2aHDPLhfWyE1//x03E952oJihl6PKq0B/ZcJT0U54mMGckNzMIC/6WRtUBZvlbZ2rtu04B2cOTm6\niOlUo0OAC4bxkpOnSSNjN0uSS6Q6LgEKblx7EVuNlmTpdFWsBSZGzyAqsBhzRPySGPKpjtVyAJR6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end_protected\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/ipstatic/simulation/blk_mem_gen_v8_3.v", "content": "/******************************************************************************\n-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n--\n *****************************************************************************\n *\n * Filename: blk_mem_gen_v8_3_4.v\n *\n * Description:\n * This file is the Verilog behvarial model for the\n * Block Memory Generator Core.\n *\n *****************************************************************************\n * Author: Xilinx\n *\n * History: Jan 11, 2006 Initial revision\n * Jun 11, 2007 Added independent register stages for \n * Port A and Port B (IP1_Jm/v2.5)\n * Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)\n * Mar 13, 2008 Behavioral model optimizations\n * April 07, 2009 : Added support for Spartan-6 and Virtex-6\n * features, including the following:\n * (i) error injection, detection and/or correction\n * (ii) reset priority\n * (iii) special reset behavior\n * \n *****************************************************************************/\n`timescale 1ps/1ps\n\nmodule STATE_LOGIC_v8_3 (O, I0, I1, I2, I3, I4, I5);\n\n parameter INIT = 64'h0000000000000000;\n\n input I0, I1, I2, I3, I4, I5;\n\n output O;\n\n reg O;\n reg tmp;\n\n always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin\n \n tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5;\n\n if ( tmp == 0 || tmp == 1)\n\n O = INIT[{I5, I4, I3, I2, I1, I0}];\n\n end\nendmodule\n\nmodule beh_vlog_muxf7_v8_3 (O, I0, I1, S);\n\n output O;\n reg O;\n\n input I0, I1, S;\n\n\talways @(I0 or I1 or S) \n\t if (S)\n\t\tO = I1;\n\t else\n\t\tO = I0;\nendmodule\n\nmodule beh_vlog_ff_clr_v8_3 (Q, C, CLR, D);\n parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n output Q;\n\n input C, CLR, D;\n\n reg Q;\n\n initial Q= 1'b0;\n\n always @(posedge C )\n if (CLR)\n\tQ<= 1'b0;\n else\n\tQ<= #FLOP_DELAY D;\n\n\nendmodule\n\nmodule beh_vlog_ff_pre_v8_3 (Q, C, D, PRE);\n\n parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n output Q;\n input C, D, PRE;\n\n reg Q;\n\n initial Q= 1'b0;\n\n always @(posedge C )\n if (PRE)\n Q <= 1'b1;\n else\n\t Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule beh_vlog_ff_ce_clr_v8_3 (Q, C, CE, CLR, D);\n\n parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n output Q;\n input C, CE, CLR, D;\n\n reg Q;\n\n initial Q= 1'b0;\n always @(posedge C )\n if (CLR)\n Q <= 1'b0;\n else if (CE)\n\t Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule write_netlist_v8_3\n#(\n parameter\t C_AXI_TYPE = 0\n )\n (\n S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,\n w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,\n S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c \n );\n\n input S_ACLK;\n input S_ARESETN;\n input S_AXI_AWVALID;\n input S_AXI_WVALID;\n input S_AXI_BREADY;\n input w_last_c;\n input bready_timeout_c;\n output aw_ready_r;\n output S_AXI_WREADY;\n output S_AXI_BVALID;\n output S_AXI_WR_EN;\n output addr_en_c;\n output incr_addr_c;\n output bvalid_c;\n //-------------------------------------------------------------------------\n //AXI LITE\n //-------------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm\n wire w_ready_r_7;\n wire w_ready_c;\n wire aw_ready_c;\n wire NlwRenamedSignal_bvalid_c;\n wire NlwRenamedSignal_incr_addr_c;\n wire present_state_FSM_FFd3_13;\n wire present_state_FSM_FFd2_14;\n wire present_state_FSM_FFd1_15;\n wire present_state_FSM_FFd4_16;\n wire present_state_FSM_FFd4_In;\n wire present_state_FSM_FFd3_In;\n wire present_state_FSM_FFd2_In;\n wire present_state_FSM_FFd1_In;\n wire present_state_FSM_FFd4_In1_21;\n wire [0:0] Mmux_aw_ready_c ; \nbegin\n assign\n S_AXI_WREADY = w_ready_r_7,\n S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,\n S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,\n incr_addr_c = NlwRenamedSignal_incr_addr_c,\n bvalid_c = NlwRenamedSignal_bvalid_c;\n\n assign NlwRenamedSignal_incr_addr_c = 1'b0;\n\n beh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n aw_ready_r_2 (\n .C ( S_ACLK), \n .CLR ( S_ARESETN), \n .D ( aw_ready_c), \n .Q ( aw_ready_r)\n );\n beh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n w_ready_r (\n .C ( S_ACLK), \n .CLR ( S_ARESETN), \n .D ( w_ready_c), \n .Q ( w_ready_r_7)\n );\n beh_vlog_ff_pre_v8_3 #(\n .INIT (1'b1))\n present_state_FSM_FFd4 (\n .C ( S_ACLK), \n .D ( present_state_FSM_FFd4_In), \n .PRE ( S_ARESETN), \n .Q ( present_state_FSM_FFd4_16)\n );\n beh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n present_state_FSM_FFd3 (\n .C ( S_ACLK), \n .CLR ( S_ARESETN), \n .D ( present_state_FSM_FFd3_In), \n .Q ( present_state_FSM_FFd3_13)\n );\n beh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n present_state_FSM_FFd2 (\n .C ( S_ACLK), \n .CLR ( S_ARESETN), \n .D ( present_state_FSM_FFd2_In), \n .Q ( present_state_FSM_FFd2_14)\n );\nbeh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n present_state_FSM_FFd1 (\n .C ( S_ACLK), \n .CLR ( S_ARESETN), \n .D ( present_state_FSM_FFd1_In), \n .Q ( present_state_FSM_FFd1_15)\n );\nSTATE_LOGIC_v8_3 #(\n .INIT (64'h0000000055554440))\n present_state_FSM_FFd3_In1 (\n .I0 ( S_AXI_WVALID), \n .I1 ( S_AXI_AWVALID), \n .I2 ( present_state_FSM_FFd2_14), \n .I3 ( present_state_FSM_FFd4_16), \n .I4 ( present_state_FSM_FFd3_13), \n .I5 (1'b0), \n .O ( present_state_FSM_FFd3_In)\n );\nSTATE_LOGIC_v8_3 #(\n .INIT (64'h0000000088880800))\n present_state_FSM_FFd2_In1 (\n .I0 ( S_AXI_AWVALID), \n .I1 ( S_AXI_WVALID), \n .I2 ( bready_timeout_c), \n .I3 ( present_state_FSM_FFd2_14), \n .I4 ( present_state_FSM_FFd4_16), \n .I5 (1'b0), \n .O ( present_state_FSM_FFd2_In)\n );\nSTATE_LOGIC_v8_3 #(\n .INIT (64'h00000000AAAA2000))\n Mmux_addr_en_c_0_1 (\n .I0 ( S_AXI_AWVALID), \n .I1 ( bready_timeout_c), \n .I2 ( present_state_FSM_FFd2_14), \n .I3 ( S_AXI_WVALID), \n .I4 ( present_state_FSM_FFd4_16), \n .I5 (1'b0), \n .O ( addr_en_c)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'hF5F07570F5F05500))\n Mmux_w_ready_c_0_1 (\n .I0 ( S_AXI_WVALID), \n .I1 ( bready_timeout_c), \n .I2 ( S_AXI_AWVALID), \n .I3 ( present_state_FSM_FFd3_13), \n .I4 ( present_state_FSM_FFd4_16), \n .I5 ( present_state_FSM_FFd2_14), \n .O ( w_ready_c)\n );\nSTATE_LOGIC_v8_3 #(\n .INIT (64'h88808880FFFF8880))\n present_state_FSM_FFd1_In1 (\n .I0 ( S_AXI_WVALID), \n .I1 ( bready_timeout_c), \n .I2 ( present_state_FSM_FFd3_13), \n .I3 ( present_state_FSM_FFd2_14), \n .I4 ( present_state_FSM_FFd1_15), \n .I5 ( S_AXI_BREADY), \n .O ( present_state_FSM_FFd1_In)\n );\nSTATE_LOGIC_v8_3 #(\n .INIT (64'h00000000000000A8))\n Mmux_S_AXI_WR_EN_0_1 (\n .I0 ( S_AXI_WVALID), \n .I1 ( present_state_FSM_FFd2_14), \n .I2 ( present_state_FSM_FFd3_13), \n .I3 (1'b0), \n .I4 (1'b0), \n .I5 (1'b0), \n .O ( NlwRenamedSignal_bvalid_c)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h2F0F27072F0F2200))\n present_state_FSM_FFd4_In1 (\n .I0 ( S_AXI_WVALID), \n .I1 ( bready_timeout_c), \n .I2 ( S_AXI_AWVALID), \n .I3 ( present_state_FSM_FFd3_13), \n .I4 ( present_state_FSM_FFd4_16), \n .I5 ( present_state_FSM_FFd2_14), \n .O ( present_state_FSM_FFd4_In1_21)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h00000000000000F8))\n present_state_FSM_FFd4_In2 ( \n .I0 ( present_state_FSM_FFd1_15), \n .I1 ( S_AXI_BREADY), \n .I2 ( present_state_FSM_FFd4_In1_21), \n .I3 (1'b0), \n .I4 (1'b0), \n .I5 (1'b0), \n .O ( present_state_FSM_FFd4_In)\n );\nSTATE_LOGIC_v8_3 #(\n .INIT (64'h7535753575305500))\n Mmux_aw_ready_c_0_1 ( \n .I0 ( S_AXI_AWVALID), \n .I1 ( bready_timeout_c), \n .I2 ( S_AXI_WVALID), \n .I3 ( present_state_FSM_FFd4_16), \n .I4 ( present_state_FSM_FFd3_13), \n .I5 ( present_state_FSM_FFd2_14), \n .O ( Mmux_aw_ready_c[0])\n );\nSTATE_LOGIC_v8_3 #(\n .INIT (64'h00000000000000F8))\n Mmux_aw_ready_c_0_2 (\n .I0 ( present_state_FSM_FFd1_15), \n .I1 ( S_AXI_BREADY), \n .I2 ( Mmux_aw_ready_c[0]), \n .I3 (1'b0), \n .I4 (1'b0), \n .I5 (1'b0), \n .O ( aw_ready_c)\n );\nend \nend \nendgenerate\n\n //---------------------------------------------------------------------\n // AXI FULL\n //---------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm\n wire w_ready_r_8; \n wire w_ready_c; \n wire aw_ready_c; \n wire NlwRenamedSig_OI_bvalid_c; \n wire present_state_FSM_FFd1_16; \n wire present_state_FSM_FFd4_17; \n wire present_state_FSM_FFd3_18; \n wire present_state_FSM_FFd2_19; \n wire present_state_FSM_FFd4_In; \n wire present_state_FSM_FFd3_In; \n wire present_state_FSM_FFd2_In; \n wire present_state_FSM_FFd1_In; \n wire present_state_FSM_FFd2_In1_24; \n wire present_state_FSM_FFd4_In1_25; \n wire N2; \n wire N4; \nbegin\nassign\n S_AXI_WREADY = w_ready_r_8,\n bvalid_c = NlwRenamedSig_OI_bvalid_c,\n S_AXI_BVALID = 1'b0;\n\nbeh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n aw_ready_r_2\n (\n .C ( S_ACLK),\n .CLR ( S_ARESETN),\n .D ( aw_ready_c),\n .Q ( aw_ready_r)\n );\nbeh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n w_ready_r\n (\n .C ( S_ACLK),\n .CLR ( S_ARESETN),\n .D ( w_ready_c),\n .Q ( w_ready_r_8)\n );\n beh_vlog_ff_pre_v8_3 #(\n .INIT (1'b1))\n present_state_FSM_FFd4\n (\n .C ( S_ACLK),\n .D ( present_state_FSM_FFd4_In),\n .PRE ( S_ARESETN),\n .Q ( present_state_FSM_FFd4_17)\n );\nbeh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n present_state_FSM_FFd3\n (\n .C ( S_ACLK),\n .CLR ( S_ARESETN),\n .D ( present_state_FSM_FFd3_In),\n .Q ( present_state_FSM_FFd3_18)\n );\nbeh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n present_state_FSM_FFd2\n (\n .C ( S_ACLK),\n .CLR ( S_ARESETN),\n .D ( present_state_FSM_FFd2_In),\n .Q ( present_state_FSM_FFd2_19)\n );\n beh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n present_state_FSM_FFd1\n (\n .C ( S_ACLK),\n .CLR ( S_ARESETN),\n .D ( present_state_FSM_FFd1_In),\n .Q ( present_state_FSM_FFd1_16)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000000005540))\n present_state_FSM_FFd3_In1\n (\n .I0 ( S_AXI_WVALID),\n .I1 ( present_state_FSM_FFd4_17),\n .I2 ( S_AXI_AWVALID),\n .I3 ( present_state_FSM_FFd3_18),\n .I4 (1'b0),\n .I5 (1'b0),\n .O ( present_state_FSM_FFd3_In)\n );\nSTATE_LOGIC_v8_3 #(\n .INIT (64'hBF3FBB33AF0FAA00))\n Mmux_aw_ready_c_0_2\n (\n .I0 ( S_AXI_BREADY),\n .I1 ( bready_timeout_c),\n .I2 ( S_AXI_AWVALID),\n .I3 ( present_state_FSM_FFd1_16),\n .I4 ( present_state_FSM_FFd4_17),\n .I5 ( NlwRenamedSig_OI_bvalid_c),\n .O ( aw_ready_c)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'hAAAAAAAA20000000))\n Mmux_addr_en_c_0_1\n (\n .I0 ( S_AXI_AWVALID),\n .I1 ( bready_timeout_c),\n .I2 ( present_state_FSM_FFd2_19),\n .I3 ( S_AXI_WVALID),\n .I4 ( w_last_c),\n .I5 ( present_state_FSM_FFd4_17),\n .O ( addr_en_c)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h00000000000000A8))\n Mmux_S_AXI_WR_EN_0_1\n (\n .I0 ( S_AXI_WVALID),\n .I1 ( present_state_FSM_FFd2_19),\n .I2 ( present_state_FSM_FFd3_18),\n .I3 (1'b0),\n .I4 (1'b0),\n .I5 (1'b0),\n .O ( S_AXI_WR_EN)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000000002220))\n Mmux_incr_addr_c_0_1\n (\n .I0 ( S_AXI_WVALID),\n .I1 ( w_last_c),\n .I2 ( present_state_FSM_FFd2_19),\n .I3 ( present_state_FSM_FFd3_18),\n .I4 (1'b0),\n .I5 (1'b0),\n .O ( incr_addr_c)\n );\nSTATE_LOGIC_v8_3 #(\n .INIT (64'h0000000000008880))\n Mmux_aw_ready_c_0_11\n (\n .I0 ( S_AXI_WVALID),\n .I1 ( w_last_c),\n .I2 ( present_state_FSM_FFd2_19),\n .I3 ( present_state_FSM_FFd3_18),\n .I4 (1'b0),\n .I5 (1'b0),\n .O ( NlwRenamedSig_OI_bvalid_c)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h000000000000D5C0))\n present_state_FSM_FFd2_In1\n (\n .I0 ( w_last_c),\n .I1 ( S_AXI_AWVALID),\n .I2 ( present_state_FSM_FFd4_17),\n .I3 ( present_state_FSM_FFd3_18),\n .I4 (1'b0),\n .I5 (1'b0),\n .O ( present_state_FSM_FFd2_In1_24)\n );\nSTATE_LOGIC_v8_3 #(\n .INIT (64'hFFFFAAAA08AAAAAA))\n present_state_FSM_FFd2_In2\n (\n .I0 ( present_state_FSM_FFd2_19),\n .I1 ( S_AXI_AWVALID),\n .I2 ( bready_timeout_c),\n .I3 ( w_last_c),\n .I4 ( S_AXI_WVALID),\n .I5 ( present_state_FSM_FFd2_In1_24),\n .O ( present_state_FSM_FFd2_In)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h00C0004000C00000))\n present_state_FSM_FFd4_In1\n (\n .I0 ( S_AXI_AWVALID),\n .I1 ( w_last_c),\n .I2 ( S_AXI_WVALID),\n .I3 ( bready_timeout_c),\n .I4 ( present_state_FSM_FFd3_18),\n .I5 ( present_state_FSM_FFd2_19),\n .O ( present_state_FSM_FFd4_In1_25)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h00000000FFFF88F8))\n present_state_FSM_FFd4_In2\n (\n .I0 ( present_state_FSM_FFd1_16),\n .I1 ( S_AXI_BREADY),\n .I2 ( present_state_FSM_FFd4_17),\n .I3 ( S_AXI_AWVALID),\n .I4 ( present_state_FSM_FFd4_In1_25),\n .I5 (1'b0),\n .O ( present_state_FSM_FFd4_In)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000000000007))\n Mmux_w_ready_c_0_SW0\n (\n .I0 ( w_last_c),\n .I1 ( S_AXI_WVALID),\n .I2 (1'b0),\n .I3 (1'b0),\n .I4 (1'b0),\n .I5 (1'b0),\n .O ( N2)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'hFABAFABAFAAAF000))\n Mmux_w_ready_c_0_Q\n (\n .I0 ( N2),\n .I1 ( bready_timeout_c),\n .I2 ( S_AXI_AWVALID),\n .I3 ( present_state_FSM_FFd4_17),\n .I4 ( present_state_FSM_FFd3_18),\n .I5 ( present_state_FSM_FFd2_19),\n .O ( w_ready_c)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000000000008))\n Mmux_aw_ready_c_0_11_SW0\n (\n .I0 ( bready_timeout_c),\n .I1 ( S_AXI_WVALID),\n .I2 (1'b0),\n .I3 (1'b0),\n .I4 (1'b0),\n .I5 (1'b0),\n .O ( N4)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h88808880FFFF8880))\n present_state_FSM_FFd1_In1\n (\n .I0 ( w_last_c),\n .I1 ( N4),\n .I2 ( present_state_FSM_FFd2_19),\n .I3 ( present_state_FSM_FFd3_18),\n .I4 ( present_state_FSM_FFd1_16),\n .I5 ( S_AXI_BREADY),\n .O ( present_state_FSM_FFd1_In)\n );\nend\nend\nendgenerate\nendmodule\n\n\nmodule read_netlist_v8_3 #(\n parameter C_AXI_TYPE = 1,\n parameter C_ADDRB_WIDTH = 12\n ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,\n S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,\n S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,\n S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);\n\n input S_AXI_R_LAST_INT;\n input S_ACLK;\n input S_ARESETN;\n input S_AXI_ARVALID;\n input S_AXI_RREADY;\n output S_AXI_INCR_ADDR;\n output S_AXI_ADDR_EN;\n output S_AXI_SINGLE_TRANS;\n output S_AXI_MUX_SEL;\n output S_AXI_R_LAST;\n output S_AXI_ARREADY;\n output S_AXI_RLAST;\n output S_AXI_RVALID;\n output S_AXI_RD_EN;\n input [7:0] S_AXI_ARLEN;\n\n wire present_state_FSM_FFd1_13 ; \n wire present_state_FSM_FFd2_14 ; \n wire gaxi_full_sm_outstanding_read_r_15 ; \n wire gaxi_full_sm_ar_ready_r_16 ; \n wire gaxi_full_sm_r_last_r_17 ; \n wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; \n wire gaxi_full_sm_r_valid_c ; \n wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; \n wire gaxi_full_sm_ar_ready_c ; \n wire gaxi_full_sm_outstanding_read_c ; \n wire NlwRenamedSig_OI_S_AXI_R_LAST ; \n wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; \n wire present_state_FSM_FFd2_In ; \n wire present_state_FSM_FFd1_In ; \n wire Mmux_S_AXI_R_LAST13 ; \n wire N01 ; \n wire N2 ; \n wire Mmux_gaxi_full_sm_ar_ready_c11 ; \n wire N4 ; \n wire N8 ; \n wire N9 ; \n wire N10 ; \n wire N11 ; \n wire N12 ; \n wire N13 ; \n assign\n S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,\n S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,\n S_AXI_RLAST = gaxi_full_sm_r_last_r_17,\n S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;\n\n beh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n gaxi_full_sm_outstanding_read_r (\n .C (S_ACLK),\n .CLR(S_ARESETN),\n .D(gaxi_full_sm_outstanding_read_c),\n .Q(gaxi_full_sm_outstanding_read_r_15)\n );\n beh_vlog_ff_ce_clr_v8_3 #(\n .INIT (1'b0))\n gaxi_full_sm_r_valid_r (\n .C (S_ACLK),\n .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n .CLR (S_ARESETN),\n .D (gaxi_full_sm_r_valid_c),\n .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)\n );\n beh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n gaxi_full_sm_ar_ready_r (\n .C (S_ACLK),\n .CLR (S_ARESETN),\n .D (gaxi_full_sm_ar_ready_c),\n .Q (gaxi_full_sm_ar_ready_r_16)\n );\n beh_vlog_ff_ce_clr_v8_3 #(\n .INIT(1'b0))\n gaxi_full_sm_r_last_r (\n .C (S_ACLK),\n .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n .CLR (S_ARESETN),\n .D (NlwRenamedSig_OI_S_AXI_R_LAST),\n .Q (gaxi_full_sm_r_last_r_17)\n );\n beh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n present_state_FSM_FFd2 (\n .C ( S_ACLK),\n .CLR ( S_ARESETN),\n .D ( present_state_FSM_FFd2_In),\n .Q ( present_state_FSM_FFd2_14)\n );\n beh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n present_state_FSM_FFd1 (\n .C (S_ACLK),\n .CLR (S_ARESETN),\n .D (present_state_FSM_FFd1_In),\n .Q (present_state_FSM_FFd1_13)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h000000000000000B))\n S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (\n .I0 ( S_AXI_RREADY),\n .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I2 (1'b0),\n .I3 (1'b0),\n .I4 (1'b0),\n .I5 (1'b0),\n .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000000000008))\n Mmux_S_AXI_SINGLE_TRANS11 (\n .I0 (S_AXI_ARVALID),\n .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n .I2 (1'b0),\n .I3 (1'b0),\n .I4 (1'b0),\n .I5 (1'b0),\n .O (S_AXI_SINGLE_TRANS)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000000000004))\n Mmux_S_AXI_ADDR_EN11 (\n .I0 (present_state_FSM_FFd1_13),\n .I1 (S_AXI_ARVALID),\n .I2 (1'b0),\n .I3 (1'b0),\n .I4 (1'b0),\n .I5 (1'b0),\n .O (S_AXI_ADDR_EN)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'hECEE2022EEEE2022))\n present_state_FSM_FFd2_In1 (\n .I0 ( S_AXI_ARVALID),\n .I1 ( present_state_FSM_FFd1_13),\n .I2 ( S_AXI_RREADY),\n .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n .I4 ( present_state_FSM_FFd2_14),\n .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .O ( present_state_FSM_FFd2_In)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000044440444))\n Mmux_S_AXI_R_LAST131 (\n .I0 ( present_state_FSM_FFd1_13),\n .I1 ( S_AXI_ARVALID),\n .I2 ( present_state_FSM_FFd2_14),\n .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I4 ( S_AXI_RREADY),\n .I5 (1'b0),\n .O ( Mmux_S_AXI_R_LAST13)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h4000FFFF40004000))\n Mmux_S_AXI_INCR_ADDR11 (\n .I0 ( S_AXI_R_LAST_INT),\n .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n .I2 ( present_state_FSM_FFd2_14),\n .I3 ( present_state_FSM_FFd1_13),\n .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n .I5 ( Mmux_S_AXI_R_LAST13),\n .O ( S_AXI_INCR_ADDR)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h00000000000000FE))\n S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (\n .I0 ( S_AXI_ARLEN[2]),\n .I1 ( S_AXI_ARLEN[1]),\n .I2 ( S_AXI_ARLEN[0]),\n .I3 ( 1'b0),\n .I4 ( 1'b0),\n .I5 ( 1'b0),\n .O ( N01)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000000000001))\n S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (\n .I0 ( S_AXI_ARLEN[7]),\n .I1 ( S_AXI_ARLEN[6]),\n .I2 ( S_AXI_ARLEN[5]),\n .I3 ( S_AXI_ARLEN[4]),\n .I4 ( S_AXI_ARLEN[3]),\n .I5 ( N01),\n .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000000000007))\n Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (\n .I0 ( S_AXI_ARVALID),\n .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n .I2 ( 1'b0),\n .I3 ( 1'b0),\n .I4 ( 1'b0),\n .I5 ( 1'b0),\n .O ( N2)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0020000002200200))\n Mmux_gaxi_full_sm_outstanding_read_c1 (\n .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I1 ( S_AXI_RREADY),\n .I2 ( present_state_FSM_FFd1_13),\n .I3 ( present_state_FSM_FFd2_14),\n .I4 ( gaxi_full_sm_outstanding_read_r_15),\n .I5 ( N2),\n .O ( gaxi_full_sm_outstanding_read_c)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000000004555))\n Mmux_gaxi_full_sm_ar_ready_c12 (\n .I0 ( S_AXI_ARVALID),\n .I1 ( S_AXI_RREADY),\n .I2 ( present_state_FSM_FFd2_14),\n .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I4 ( 1'b0),\n .I5 ( 1'b0),\n .O ( Mmux_gaxi_full_sm_ar_ready_c11)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h00000000000000EF))\n Mmux_S_AXI_R_LAST11_SW0 (\n .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n .I1 ( S_AXI_RREADY),\n .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I3 ( 1'b0),\n .I4 ( 1'b0),\n .I5 ( 1'b0),\n .O ( N4)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'hFCAAFC0A00AA000A))\n Mmux_S_AXI_R_LAST11 (\n .I0 ( S_AXI_ARVALID),\n .I1 ( gaxi_full_sm_outstanding_read_r_15),\n .I2 ( present_state_FSM_FFd2_14),\n .I3 ( present_state_FSM_FFd1_13),\n .I4 ( N4),\n .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n .O ( gaxi_full_sm_r_valid_c)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h00000000AAAAAA08))\n S_AXI_MUX_SEL1 (\n .I0 (present_state_FSM_FFd1_13),\n .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I2 (S_AXI_RREADY),\n .I3 (present_state_FSM_FFd2_14),\n .I4 (gaxi_full_sm_outstanding_read_r_15),\n .I5 (1'b0),\n .O (S_AXI_MUX_SEL)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'hF3F3F755A2A2A200))\n Mmux_S_AXI_RD_EN11 (\n .I0 ( present_state_FSM_FFd1_13),\n .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I2 ( S_AXI_RREADY),\n .I3 ( gaxi_full_sm_outstanding_read_r_15),\n .I4 ( present_state_FSM_FFd2_14),\n .I5 ( S_AXI_ARVALID),\n .O ( S_AXI_RD_EN)\n );\n beh_vlog_muxf7_v8_3 present_state_FSM_FFd1_In3 (\n .I0 ( N8),\n .I1 ( N9),\n .S ( present_state_FSM_FFd1_13),\n .O ( present_state_FSM_FFd1_In)\n );\n\n STATE_LOGIC_v8_3 #(\n .INIT (64'h000000005410F4F0))\n present_state_FSM_FFd1_In3_F (\n .I0 ( S_AXI_RREADY),\n .I1 ( present_state_FSM_FFd2_14),\n .I2 ( S_AXI_ARVALID),\n .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n .I5 ( 1'b0),\n .O ( N8)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000072FF7272))\n present_state_FSM_FFd1_In3_G (\n .I0 ( present_state_FSM_FFd2_14),\n .I1 ( S_AXI_R_LAST_INT),\n .I2 ( gaxi_full_sm_outstanding_read_r_15),\n .I3 ( S_AXI_RREADY),\n .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I5 ( 1'b0),\n .O ( N9)\n );\n beh_vlog_muxf7_v8_3 Mmux_gaxi_full_sm_ar_ready_c14 (\n .I0 ( N10),\n .I1 ( N11),\n .S ( present_state_FSM_FFd1_13),\n .O ( gaxi_full_sm_ar_ready_c)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h00000000FFFF88A8))\n Mmux_gaxi_full_sm_ar_ready_c14_F (\n .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n .I1 ( S_AXI_RREADY),\n .I2 ( present_state_FSM_FFd2_14),\n .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I4 ( Mmux_gaxi_full_sm_ar_ready_c11),\n .I5 ( 1'b0),\n .O ( N10)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h000000008D008D8D))\n Mmux_gaxi_full_sm_ar_ready_c14_G (\n .I0 ( present_state_FSM_FFd2_14),\n .I1 ( S_AXI_R_LAST_INT),\n .I2 ( gaxi_full_sm_outstanding_read_r_15),\n .I3 ( S_AXI_RREADY),\n .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I5 ( 1'b0),\n .O ( N11)\n );\n beh_vlog_muxf7_v8_3 Mmux_S_AXI_R_LAST1 (\n .I0 ( N12),\n .I1 ( N13),\n .S ( present_state_FSM_FFd1_13),\n .O ( NlwRenamedSig_OI_S_AXI_R_LAST)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000088088888))\n Mmux_S_AXI_R_LAST1_F (\n .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n .I1 ( S_AXI_ARVALID),\n .I2 ( present_state_FSM_FFd2_14),\n .I3 ( S_AXI_RREADY),\n .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I5 ( 1'b0),\n .O ( N12)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h00000000E400E4E4))\n Mmux_S_AXI_R_LAST1_G (\n .I0 ( present_state_FSM_FFd2_14),\n .I1 ( gaxi_full_sm_outstanding_read_r_15),\n .I2 ( S_AXI_R_LAST_INT),\n .I3 ( S_AXI_RREADY),\n .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I5 ( 1'b0),\n .O ( N13)\n );\n\nendmodule\n\n\nmodule blk_mem_axi_write_wrapper_beh_v8_3\n # (\n // AXI Interface related parameters start here\n parameter C_INTERFACE_TYPE = 0, // 0: Native Interface; 1: AXI Interface\n parameter C_AXI_TYPE = 0, // 0: AXI Lite; 1: AXI Full;\n parameter C_AXI_SLAVE_TYPE = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;\n parameter C_MEMORY_TYPE = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;\n parameter C_WRITE_DEPTH_A = 0,\n parameter C_AXI_AWADDR_WIDTH = 32,\n parameter C_ADDRA_WIDTH \t = 12,\n parameter C_AXI_WDATA_WIDTH = 32,\n parameter C_HAS_AXI_ID = 0,\n parameter C_AXI_ID_WIDTH = 4,\n // AXI OUTSTANDING WRITES\n parameter C_AXI_OS_WR = 2\n )\n (\n // AXI Global Signals\n input S_ACLK, \n input S_ARESETN,\n // AXI Full/Lite Slave Write Channel (write side)\n input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,\n input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,\n input [8-1:0] S_AXI_AWLEN,\n input [2:0] S_AXI_AWSIZE,\n input [1:0] S_AXI_AWBURST,\n input S_AXI_AWVALID,\n output S_AXI_AWREADY,\n input S_AXI_WVALID,\n output S_AXI_WREADY, \n output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,\n output S_AXI_BVALID,\n input S_AXI_BREADY,\n // Signals for BMG interface\n output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,\n output S_AXI_WR_EN\n );\n\n localparam FLOP_DELAY = 100; // 100 ps\n\n localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:\n ((C_AXI_WDATA_WIDTH==16)?1:\n ((C_AXI_WDATA_WIDTH==32)?2:\n ((C_AXI_WDATA_WIDTH==64)?3:\n ((C_AXI_WDATA_WIDTH==128)?4:\n ((C_AXI_WDATA_WIDTH==256)?5:0))))));\n\n\n\n\n wire bvalid_c ;\n reg bready_timeout_c = 0;\n wire [1:0] bvalid_rd_cnt_c;\n reg bvalid_r \t= 0;\n reg [2:0] bvalid_count_r = 0;\n reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;\n reg [1:0] bvalid_wr_cnt_r = 0;\n reg [1:0] bvalid_rd_cnt_r = 0;\n wire w_last_c ;\n wire addr_en_c ;\n wire incr_addr_c ;\n wire aw_ready_r \t ;\n wire dec_alen_c ;\n reg bvalid_d1_c = 0;\n reg [7:0] awlen_cntr_r = 0;\n reg [7:0] awlen_int = 0;\n reg [1:0] awburst_int = 0;\n\n integer total_bytes = 0;\n integer wrap_boundary = 0;\n integer wrap_base_addr = 0;\n integer num_of_bytes_c = 0;\n integer num_of_bytes_r = 0;\n // Array to store BIDs\n reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;\n wire S_AXI_BVALID_axi_wr_fsm;\n\n //-------------------------------------\n //AXI WRITE FSM COMPONENT INSTANTIATION\n //-------------------------------------\n write_netlist_v8_3 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm\n (\n .S_ACLK(S_ACLK),\n .S_ARESETN(S_ARESETN),\n .S_AXI_AWVALID(S_AXI_AWVALID),\n .aw_ready_r(aw_ready_r),\n .S_AXI_WVALID(S_AXI_WVALID),\n .S_AXI_WREADY(S_AXI_WREADY),\n .S_AXI_BREADY(S_AXI_BREADY),\n .S_AXI_WR_EN(S_AXI_WR_EN),\n .w_last_c(w_last_c),\n .bready_timeout_c(bready_timeout_c),\n .addr_en_c(addr_en_c),\n .incr_addr_c(incr_addr_c),\n .bvalid_c(bvalid_c),\n .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) \n\t ); \n \n \n //Wrap Address boundary calculation \n always@(*) begin\n num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);\n total_bytes = (num_of_bytes_r)*(awlen_int+1);\n wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);\n wrap_boundary = wrap_base_addr+total_bytes;\n end\n \n //-------------------------------------------------------------------------\n // BMG address generation\n //-------------------------------------------------------------------------\n always @(posedge S_ACLK or S_ARESETN) begin\n if (S_ARESETN == 1'b1) begin\n awaddr_reg <= 0;\n\t num_of_bytes_r <= 0;\n\t awburst_int <= 0; \n\t end else begin\n if (addr_en_c == 1'b1) begin\n awaddr_reg <= #FLOP_DELAY S_AXI_AWADDR ;\n\t num_of_bytes_r <= num_of_bytes_c;\n\t awburst_int <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);\n\t end else if (incr_addr_c == 1'b1) begin\n\t if (awburst_int == 2'b10) begin\n\t\tif(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin\n\t\t awaddr_reg <= wrap_base_addr;\n\t\tend else begin\n\t\t awaddr_reg <= awaddr_reg + num_of_bytes_r;\n\t\tend\n\t end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin\n\t\tawaddr_reg <= awaddr_reg + num_of_bytes_r;\n\t end\n end\n end\n end\n \n \n assign S_AXI_AWADDR_OUT = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n\t\t\t \t awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);\n\n //-------------------------------------------------------------------------\n // AXI wlast generation\n //-------------------------------------------------------------------------\n always @(posedge S_ACLK or S_ARESETN) begin\n if (S_ARESETN == 1'b1) begin\n awlen_cntr_r <= 0;\n\t awlen_int <= 0;\n\t end else begin\n if (addr_en_c == 1'b1) begin\n\t awlen_int <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t awlen_cntr_r <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t end else if (dec_alen_c == 1'b1) begin\n awlen_cntr_r <= #FLOP_DELAY awlen_cntr_r - 1 ;\n end\n end\n end\n\n assign w_last_c = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;\n \n assign dec_alen_c = (incr_addr_c | w_last_c);\n\n //-------------------------------------------------------------------------\n // Generation of bvalid counter for outstanding transactions \n //-------------------------------------------------------------------------\n always @(posedge S_ACLK or S_ARESETN) begin\n if (S_ARESETN == 1'b1) begin\n\tbvalid_count_r <= 0;\n\tend else begin\n\t// bvalid_count_r generation\n\tif (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin\n\t bvalid_count_r <= #FLOP_DELAY bvalid_count_r ;\n\t end else if (bvalid_c == 1'b1) begin \n\t bvalid_count_r <= #FLOP_DELAY bvalid_count_r + 1 ;\n\t end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin\n\t bvalid_count_r <= #FLOP_DELAY bvalid_count_r - 1 ;\n\tend\n end\n end\n\n //-------------------------------------------------------------------------\n // Generation of bvalid when BID is used \n //-------------------------------------------------------------------------\n generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n always @(posedge S_ACLK or S_ARESETN) begin\n if (S_ARESETN == 1'b1) begin\n bvalid_r <= 0;\n bvalid_d1_c <= 0;\n\tend else begin\n // Delay the generation o bvalid_r for generation for BID \n bvalid_d1_c <= bvalid_c;\n \n //external bvalid signal generation\n if (bvalid_d1_c == 1'b1) begin\n bvalid_r <= #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n bvalid_r <= #FLOP_DELAY 0 ;\n end\n end\n end\n end\n endgenerate\n \n //-------------------------------------------------------------------------\n // Generation of bvalid when BID is not used \n //-------------------------------------------------------------------------\n generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r\n always @(posedge S_ACLK or S_ARESETN) begin\n if (S_ARESETN == 1'b1) begin\n bvalid_r <= 0;\n\tend else begin\n //external bvalid signal generation\n if (bvalid_c == 1'b1) begin\n bvalid_r <= #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n bvalid_r <= #FLOP_DELAY 0 ;\n end\n end\n end\n end\n endgenerate\n \n //-------------------------------------------------------------------------\n // Generation of Bready timeout\n //-------------------------------------------------------------------------\n always @(bvalid_count_r) begin\n \t// bready_timeout_c generation\n\tif(bvalid_count_r == C_AXI_OS_WR-1) begin\n\t bready_timeout_c <= 1'b1;\n\tend else begin\n\t bready_timeout_c <= 1'b0;\n\tend\n end\n \n //-------------------------------------------------------------------------\n // Generation of BID \n //-------------------------------------------------------------------------\n generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen\n\n always @(posedge S_ACLK or S_ARESETN) begin\n if (S_ARESETN == 1'b1) begin\n bvalid_wr_cnt_r <= 0;\n bvalid_rd_cnt_r <= 0;\n\tend else begin\n // STORE AWID IN AN ARRAY\n if(bvalid_c == 1'b1) begin\n bvalid_wr_cnt_r <= bvalid_wr_cnt_r + 1;\n end\n\t // generate BID FROM AWID ARRAY\n\t bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;\n\t S_AXI_BID <= axi_bid_array[bvalid_rd_cnt_c];\n end \n end\n \n assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;\n \n //-------------------------------------------------------------------------\n // Storing AWID for generation of BID\n //-------------------------------------------------------------------------\n always @(posedge S_ACLK or S_ARESETN) begin\n if(S_ARESETN == 1'b1) begin\n\taxi_bid_array[0] = 0;\n\taxi_bid_array[1] = 0;\n\taxi_bid_array[2] = 0;\n\taxi_bid_array[3] = 0;\n\tend else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin\n\taxi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;\n end\n end\n \n end\n endgenerate\n\n assign S_AXI_BVALID = bvalid_r;\n assign S_AXI_AWREADY = aw_ready_r;\n\n endmodule\n\nmodule blk_mem_axi_read_wrapper_beh_v8_3\n# (\n //// AXI Interface related parameters start here\n parameter C_INTERFACE_TYPE = 0,\n parameter C_AXI_TYPE = 0,\n parameter C_AXI_SLAVE_TYPE = 0,\n parameter C_MEMORY_TYPE = 0,\n parameter C_WRITE_WIDTH_A = 4,\n parameter C_WRITE_DEPTH_A = 32,\n parameter C_ADDRA_WIDTH = 12,\n parameter C_AXI_PIPELINE_STAGES = 0,\n parameter C_AXI_ARADDR_WIDTH = 12,\n parameter C_HAS_AXI_ID = 0,\n parameter C_AXI_ID_WIDTH = 4,\n parameter C_ADDRB_WIDTH = 12\n )\n (\n\n //// AXI Global Signals\n input S_ACLK,\n input S_ARESETN,\n //// AXI Full/Lite Slave Read (Read side)\n input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,\n input [7:0] S_AXI_ARLEN,\n input [2:0] S_AXI_ARSIZE,\n input [1:0] S_AXI_ARBURST,\n input S_AXI_ARVALID,\n output S_AXI_ARREADY,\n output S_AXI_RLAST, \n output S_AXI_RVALID,\n input S_AXI_RREADY,\n input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,\n output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,\n //// AXI Full/Lite Read Address Signals to BRAM\n output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,\n output S_AXI_RD_EN\n );\n\n localparam FLOP_DELAY = 100; // 100 ps\n localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:\n ((C_WRITE_WIDTH_A==16)?1:\n ((C_WRITE_WIDTH_A==32)?2:\n ((C_WRITE_WIDTH_A==64)?3:\n ((C_WRITE_WIDTH_A==128)?4:\n ((C_WRITE_WIDTH_A==256)?5:0))))));\n\n\n\n reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;\n wire addr_en_c; \n wire rd_en_c; \n wire incr_addr_c; \n wire single_trans_c; \n wire dec_alen_c; \n wire mux_sel_c; \n wire r_last_c; \n wire r_last_int_c; \n wire [C_ADDRB_WIDTH-1 : 0] araddr_out; \n\n reg [7:0] arlen_int_r=0; \n reg [7:0] arlen_cntr=8'h01; \n reg [1:0] arburst_int_c=0; \n reg [1:0] arburst_int_r=0; \n reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;\n integer num_of_bytes_c = 0;\n integer total_bytes = 0;\n integer num_of_bytes_r = 0;\n integer wrap_base_addr_r = 0;\n integer wrap_boundary_r = 0;\n\n reg [7:0] arlen_int_c=0; \n integer total_bytes_c = 0;\n integer wrap_base_addr_c = 0;\n integer wrap_boundary_c = 0;\n\n assign dec_alen_c = incr_addr_c | r_last_int_c;\n\n\n read_netlist_v8_3\n #(.C_AXI_TYPE (1),\n .C_ADDRB_WIDTH (C_ADDRB_WIDTH)) \n axi_read_fsm (\n .S_AXI_INCR_ADDR(incr_addr_c),\n .S_AXI_ADDR_EN(addr_en_c),\n .S_AXI_SINGLE_TRANS(single_trans_c),\n .S_AXI_MUX_SEL(mux_sel_c),\n .S_AXI_R_LAST(r_last_c),\n .S_AXI_R_LAST_INT(r_last_int_c),\n\n //// AXI Global Signals\n .S_ACLK(S_ACLK),\n .S_ARESETN(S_ARESETN),\n //// AXI Full/Lite Slave Read (Read side)\n .S_AXI_ARLEN(S_AXI_ARLEN),\n .S_AXI_ARVALID(S_AXI_ARVALID),\n .S_AXI_ARREADY(S_AXI_ARREADY),\n .S_AXI_RLAST(S_AXI_RLAST),\n .S_AXI_RVALID(S_AXI_RVALID),\n .S_AXI_RREADY(S_AXI_RREADY),\n //// AXI Full/Lite Read Address Signals to BRAM\n .S_AXI_RD_EN(rd_en_c)\n );\n\n always@(*) begin\n num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);\n total_bytes = (num_of_bytes_r)*(arlen_int_r+1);\n wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);\n wrap_boundary_r = wrap_base_addr_r+total_bytes;\n\n //////// combinatorial from interface\n arlen_int_c = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);\n total_bytes_c = (num_of_bytes_c)*(arlen_int_c+1);\n wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);\n wrap_boundary_c = wrap_base_addr_c+total_bytes_c;\n \n arburst_int_c = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1); \n end\n\n ////-------------------------------------------------------------------------\n //// BMG address generation\n ////-------------------------------------------------------------------------\n always @(posedge S_ACLK or S_ARESETN) begin\n if (S_ARESETN == 1'b1) begin\n araddr_reg \t<= 0;\n \tarburst_int_r <= 0;\n\tnum_of_bytes_r <= 0;\n end else begin\n if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin\n\t arburst_int_r <= arburst_int_c;\n\t num_of_bytes_r <= num_of_bytes_c;\n\t if (arburst_int_c == 2'b10) begin\n\t\t if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin\n\t\t araddr_reg <= wrap_base_addr_c;\n\t\t end else begin\n\t\t araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t\t end\n\t end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin\n\t\t araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t end\n\n end else if (addr_en_c == 1'b1) begin\n araddr_reg <= S_AXI_ARADDR;\n\t num_of_bytes_r <= num_of_bytes_c;\n\t arburst_int_r <= arburst_int_c;\n\t end else if (incr_addr_c == 1'b1) begin\n\t if (arburst_int_r == 2'b10) begin\n\t \tif(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin\n\t \t araddr_reg <= wrap_base_addr_r;\n\t \tend else begin\n\t \t araddr_reg <= araddr_reg + num_of_bytes_r;\n\t \tend\n\t end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin\n\t\t araddr_reg <= araddr_reg + num_of_bytes_r;\n\t end\n end\n end\n end\n\nassign araddr_out = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);\n \n\n ////-----------------------------------------------------------------------\n //// Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM\n ////-----------------------------------------------------------------------\n always @(posedge S_ACLK or S_ARESETN) begin\n if (S_ARESETN == 1'b1) begin\n arlen_cntr <= 8'h01;\n\t arlen_int_r <= 0;\n\tend else begin\n if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin\n\t arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n arlen_cntr <= S_AXI_ARLEN - 1'b1;\n\t end else if (addr_en_c == 1'b1) begin\n\t arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t arlen_cntr <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t end else if (dec_alen_c == 1'b1) begin\n arlen_cntr <= arlen_cntr - 1'b1 ;\n end\n\t else begin\n\t arlen_cntr <= arlen_cntr;\n\t end\n end\n end\n\n assign r_last_int_c = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;\n\n\n ////------------------------------------------------------------------------\n //// AXI FULL FSM\n //// Mux Selection of ARADDR\n //// ARADDR is driven out from the read fsm based on the mux_sel_c\n //// Based on mux_sel either ARADDR is given out or the latched ARADDR is\n //// given out to BRAM\n ////------------------------------------------------------------------------\n\tassign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;\n \n ////------------------------------------------------------------------------\n //// Assign output signals - AXI FULL FSM\n ////------------------------------------------------------------------------\n assign S_AXI_RD_EN = rd_en_c;\n\n generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n always @(posedge S_ACLK or S_ARESETN) begin\n if (S_ARESETN == 1'b1) begin\n S_AXI_RID <= 0;\n ar_id_r <= 0;\n\tend else begin\n if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin\n S_AXI_RID <= S_AXI_ARID;\n ar_id_r <= S_AXI_ARID;\n end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin\n\t ar_id_r <= S_AXI_ARID;\n end else if (rd_en_c == 1'b1) begin\n S_AXI_RID <= ar_id_r;\n end\n end\n end \n end \n endgenerate \n\nendmodule\n\nmodule blk_mem_axi_regs_fwd_v8_3\n #(parameter C_DATA_WIDTH = 8\n )(\n input ACLK,\n input ARESET,\n input S_VALID,\n output S_READY,\n input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n output M_VALID,\n input M_READY,\n output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n );\n\n reg [C_DATA_WIDTH-1:0] STORAGE_DATA;\n wire S_READY_I;\n reg M_VALID_I;\n reg [1:0] ARESET_D;\n\n //assign local signal to its output signal\n assign S_READY = S_READY_I;\n assign M_VALID = M_VALID_I;\n\n always @(posedge ACLK) begin\n\t ARESET_D <= {ARESET_D[0], ARESET};\n\tend\n \n //Save payload data whenever we have a transaction on the slave side\n always @(posedge ACLK or ARESET) begin\n if (ARESET == 1'b1) begin\n \t STORAGE_DATA <= 0;\n\tend else begin\n\t if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin\n \t STORAGE_DATA <= S_PAYLOAD_DATA;\n \t end\n \tend\n end\n\n always @(posedge ACLK) begin\n M_PAYLOAD_DATA = STORAGE_DATA;\n end\n \n //M_Valid set to high when we have a completed transfer on slave side\n //Is removed on a M_READY except if we have a new transfer on the slave side\n \n always @(posedge ACLK or ARESET_D) begin\n\tif (ARESET_D != 2'b00) begin\n \t M_VALID_I <= 1'b0;\n\tend else begin\n\t if (S_VALID == 1'b1) begin\n\t //Always set M_VALID_I when slave side is valid\n M_VALID_I <= 1'b1;\n\t end else if (M_READY == 1'b1 ) begin\n\t //Clear (or keep) when no slave side is valid but master side is ready\n\t M_VALID_I <= 1'b0;\n\t end\n\tend\n end\n\n //Slave Ready is either when Master side drives M_READY or we have space in our storage data\n assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));\n\n endmodule\n\n//*****************************************************************************\n// Output Register Stage module\n//\n// This module builds the output register stages of the memory. This module is \n// instantiated in the main memory module (blk_mem_gen_v8_3_4) which is\n// declared/implemented further down in this file.\n//*****************************************************************************\nmodule blk_mem_gen_v8_3_4_output_stage\n #(parameter C_FAMILY = \"virtex7\",\n parameter C_XDEVICEFAMILY = \"virtex7\",\n parameter C_RST_TYPE = \"SYNC\",\n parameter C_HAS_RST = 0,\n parameter C_RSTRAM = 0,\n parameter C_RST_PRIORITY = \"CE\",\n parameter C_INIT_VAL = \"0\",\n parameter C_HAS_EN = 0,\n parameter C_HAS_REGCE = 0,\n parameter C_DATA_WIDTH = 32,\n parameter C_ADDRB_WIDTH = 10,\n parameter C_HAS_MEM_OUTPUT_REGS = 0,\n parameter C_USE_SOFTECC = 0,\n parameter C_USE_ECC = 0,\n parameter NUM_STAGES = 1,\n\tparameter C_EN_ECC_PIPE = 0,\n parameter FLOP_DELAY = 100\n )\n (\n input CLK,\n input RST,\n input EN,\n input REGCE,\n input [C_DATA_WIDTH-1:0] DIN_I,\n output reg [C_DATA_WIDTH-1:0] DOUT,\n input SBITERR_IN_I,\n input DBITERR_IN_I,\n output reg SBITERR,\n output reg DBITERR,\n input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN_I,\n input ECCPIPECE, \n output reg [C_ADDRB_WIDTH-1:0] RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n //////////////////////////////////////////////////////////////////////////\n // Generic Definitions\n //////////////////////////////////////////////////////////////////////////\n // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n // options are available - \"spartan3\", \"spartan6\", \n // \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n // C_RST_TYPE : Type of reset - Synchronous or Asynchronous\n // C_HAS_RST : Determines the presence of the RST port\n // C_RSTRAM : Determines if special reset behavior is used\n // C_RST_PRIORITY : Determines the priority between CE and SR\n // C_INIT_VAL : Initialization value\n // C_HAS_EN : Determines the presence of the EN port\n // C_HAS_REGCE : Determines the presence of the REGCE port\n // C_DATA_WIDTH : Memory write/read width\n // C_ADDRB_WIDTH : Width of the ADDRB input port\n // C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output \n // of the RAM primitive\n // C_USE_SOFTECC : Determines if the Soft ECC feature is used or\n // not. Only applicable Spartan-6\n // C_USE_ECC : Determines if the ECC feature is used or\n // not. Only applicable for V5 and V6\n // NUM_STAGES : Determines the number of output stages\n // FLOP_DELAY : Constant delay for register assignments\n //////////////////////////////////////////////////////////////////////////\n // Port Definitions\n //////////////////////////////////////////////////////////////////////////\n // CLK : Clock to synchronize all read and write operations\n // RST : Reset input to reset memory outputs to a user-defined \n // reset state\n // EN : Enable all read and write operations\n // REGCE : Register Clock Enable to control each pipeline output\n // register stages\n // DIN : Data input to the Output stage.\n // DOUT : Final Data output\n // SBITERR_IN : SBITERR input signal to the Output stage.\n // SBITERR : Final SBITERR Output signal.\n // DBITERR_IN : DBITERR input signal to the Output stage.\n // DBITERR : Final DBITERR Output signal.\n // RDADDRECC_IN : RDADDRECC input signal to the Output stage.\n // RDADDRECC : Final RDADDRECC Output signal.\n //////////////////////////////////////////////////////////////////////////\n\n// Fix for CR-509792\n\n localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;\n \n // Declare the pipeline registers \n // (includes mem output reg, mux pipeline stages, and mux output reg)\n reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;\n reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;\n reg [REG_STAGES-1:0] sbiterr_regs;\n reg [REG_STAGES-1:0] dbiterr_regs;\n\n reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL;\n reg [C_DATA_WIDTH-1:0] init_val ;\n\n //*********************************************\n // Wire off optional inputs based on parameters\n //*********************************************\n wire en_i;\n wire regce_i;\n wire rst_i;\n \n // Internal signals\n reg [C_DATA_WIDTH-1:0] DIN;\n reg [C_ADDRB_WIDTH-1:0] RDADDRECC_IN;\n reg SBITERR_IN;\n reg DBITERR_IN;\n\n\n // Internal enable for output registers is tied to user EN or '1' depending\n // on parameters\n assign en_i = (C_HAS_EN==0 || EN);\n\n // Internal register enable for output registers is tied to user REGCE, EN or\n // '1' depending on parameters\n // For V4 ECC, REGCE is always 1\n // Virtex-4 ECC Not Yet Supported\n assign regce_i = ((C_HAS_REGCE==1) && REGCE) ||\n ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));\n \n //Internal SRR is tied to user RST or '0' depending on parameters\n assign rst_i = (C_HAS_RST==1) && RST;\n\n //****************************************************\n // Power on: load up the output registers and latches\n //****************************************************\n initial begin\n if (!($sscanf(init_str, \"%h\", init_val))) begin\n init_val = 0;\n end\n DOUT = init_val;\n RDADDRECC = 0;\n SBITERR = 1'b0;\n DBITERR = 1'b0;\n\tDIN = {(C_DATA_WIDTH){1'b0}};\n RDADDRECC_IN = 0;\n SBITERR_IN = 0;\n\tDBITERR_IN = 0;\n\t// This will be one wider than need, but 0 is an error\n out_regs = {(REG_STAGES+1){init_val}};\n rdaddrecc_regs = 0;\n sbiterr_regs = {(REG_STAGES+1){1'b0}};\n dbiterr_regs = {(REG_STAGES+1){1'b0}};\n end\n\n //***********************************************\n // NUM_STAGES = 0 (No output registers. RAM only)\n //***********************************************\n generate if (NUM_STAGES == 0) begin : zero_stages\n always @* begin\n DOUT = DIN;\n RDADDRECC = RDADDRECC_IN;\n SBITERR = SBITERR_IN;\n DBITERR = DBITERR_IN;\n end\n end\n endgenerate\n\n generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg\n always @* begin\n DIN = DIN_I;\n\t SBITERR_IN = SBITERR_IN_I;\n DBITERR_IN = DBITERR_IN_I;\n RDADDRECC_IN = RDADDRECC_IN_I;\n end\n end\n endgenerate\n\n generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg\n always @(posedge CLK) begin\n if(ECCPIPECE == 1) begin\n\t DIN <= #FLOP_DELAY DIN_I;\n SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;\n DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;\n RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;\n end\n\tend\n end\n endgenerate\n\n\n //***********************************************\n // NUM_STAGES = 1 \n // (Mem Output Reg only or Mux Output Reg only)\n //***********************************************\n\n // Possible valid combinations: \n // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)\n // +-----------------------------------------+\n // | C_RSTRAM_* | Reset Behavior |\n // +----------------+------------------------+\n // | 0 | Normal Behavior |\n // +----------------+------------------------+\n // | 1 | Special Behavior |\n // +----------------+------------------------+\n //\n // Normal = REGCE gates reset, as in the case of all families except S3ADSP.\n // Special = EN gates reset, as in the case of S3ADSP.\n\n generate if (NUM_STAGES == 1 && \n (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != \"spartan3adsp\" && C_XDEVICEFAMILY != \"aspartan3adsp\" )) ||\n C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))\n begin : one_stages_norm\n\n always @(posedge CLK) begin\n if (C_RST_PRIORITY == \"CE\") begin //REGCE has priority\n if (regce_i && rst_i) begin\n DOUT <= #FLOP_DELAY init_val;\n RDADDRECC <= #FLOP_DELAY 0;\n SBITERR <= #FLOP_DELAY 1'b0;\n DBITERR <= #FLOP_DELAY 1'b0;\n end else if (regce_i) begin\n DOUT <= #FLOP_DELAY DIN;\n RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n SBITERR <= #FLOP_DELAY SBITERR_IN;\n DBITERR <= #FLOP_DELAY DBITERR_IN;\n end //Output signal assignments\n end else begin //RST has priority\n if (rst_i) begin\n DOUT <= #FLOP_DELAY init_val;\n RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n SBITERR <= #FLOP_DELAY 1'b0;\n DBITERR <= #FLOP_DELAY 1'b0;\n end else if (regce_i) begin\n DOUT <= #FLOP_DELAY DIN;\n RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n SBITERR <= #FLOP_DELAY SBITERR_IN;\n DBITERR <= #FLOP_DELAY DBITERR_IN;\n end //Output signal assignments\n end //end Priority conditions\n end //end RST Type conditions\n end //end one_stages_norm generate statement\n endgenerate\n\n // Special Reset Behavior for S3ADSP\n generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY ==\"spartan3adsp\" || C_XDEVICEFAMILY ==\"aspartan3adsp\"))\n begin : one_stage_splbhv\n always @(posedge CLK) begin\n if (en_i && rst_i) begin\n DOUT <= #FLOP_DELAY init_val;\n end else if (regce_i && !rst_i) begin\n DOUT <= #FLOP_DELAY DIN;\n end //Output signal assignments\n end //end CLK\n end //end one_stage_splbhv generate statement\n endgenerate\n\n //************************************************************\n // NUM_STAGES > 1 \n // Mem Output Reg + Mux Output Reg\n // or \n // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg\n // or \n // Mux Pipeline Stages (>0) + Mux Output Reg\n //*************************************************************\n generate if (NUM_STAGES > 1) begin : multi_stage\n //Asynchronous Reset\n always @(posedge CLK) begin\n if (C_RST_PRIORITY == \"CE\") begin //REGCE has priority\n if (regce_i && rst_i) begin\n DOUT <= #FLOP_DELAY init_val;\n RDADDRECC <= #FLOP_DELAY 0;\n SBITERR <= #FLOP_DELAY 1'b0;\n DBITERR <= #FLOP_DELAY 1'b0;\n end else if (regce_i) begin\n DOUT <= #FLOP_DELAY\n out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n end //Output signal assignments\n end else begin //RST has priority\n if (rst_i) begin\n DOUT <= #FLOP_DELAY init_val;\n RDADDRECC <= #FLOP_DELAY 0;\n SBITERR <= #FLOP_DELAY 1'b0;\n DBITERR <= #FLOP_DELAY 1'b0;\n end else if (regce_i) begin\n DOUT <= #FLOP_DELAY\n out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n end //Output signal assignments\n end //end Priority conditions\n // Shift the data through the output stages\n if (en_i) begin\n out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;\n rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;\n sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;\n dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;\n end\n end //end CLK\n end //end multi_stage generate statement\n endgenerate\nendmodule\n\nmodule blk_mem_gen_v8_3_4_softecc_output_reg_stage\n #(parameter C_DATA_WIDTH = 32,\n parameter C_ADDRB_WIDTH = 10,\n parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n parameter C_USE_SOFTECC = 0,\n parameter FLOP_DELAY = 100\n )\n (\n input CLK,\n input [C_DATA_WIDTH-1:0] DIN,\n output reg [C_DATA_WIDTH-1:0] DOUT,\n input SBITERR_IN,\n input DBITERR_IN,\n output reg SBITERR,\n output reg DBITERR,\n input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,\n output reg [C_ADDRB_WIDTH-1:0] RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n //////////////////////////////////////////////////////////////////////////\n // Generic Definitions\n //////////////////////////////////////////////////////////////////////////\n // C_DATA_WIDTH : Memory write/read width\n // C_ADDRB_WIDTH : Width of the ADDRB input port\n // C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output \n // of the RAM primitive\n // C_USE_SOFTECC : Determines if the Soft ECC feature is used or\n // not. Only applicable Spartan-6\n // FLOP_DELAY : Constant delay for register assignments\n //////////////////////////////////////////////////////////////////////////\n // Port Definitions\n //////////////////////////////////////////////////////////////////////////\n // CLK : Clock to synchronize all read and write operations\n // DIN : Data input to the Output stage.\n // DOUT : Final Data output\n // SBITERR_IN : SBITERR input signal to the Output stage.\n // SBITERR : Final SBITERR Output signal.\n // DBITERR_IN : DBITERR input signal to the Output stage.\n // DBITERR : Final DBITERR Output signal.\n // RDADDRECC_IN : RDADDRECC input signal to the Output stage.\n // RDADDRECC : Final RDADDRECC Output signal.\n //////////////////////////////////////////////////////////////////////////\n\n reg [C_DATA_WIDTH-1:0] dout_i = 0;\n reg sbiterr_i = 0;\n reg dbiterr_i = 0;\n reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;\n\n //***********************************************\n // NO OUTPUT REGISTERS.\n //***********************************************\n generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage\n always @* begin\n DOUT = DIN;\n RDADDRECC = RDADDRECC_IN;\n SBITERR = SBITERR_IN;\n DBITERR = DBITERR_IN;\n end\n end\n endgenerate\n\n //***********************************************\n // WITH OUTPUT REGISTERS.\n //***********************************************\n generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage\n always @(posedge CLK) begin\n dout_i <= #FLOP_DELAY DIN;\n rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;\n sbiterr_i <= #FLOP_DELAY SBITERR_IN;\n dbiterr_i <= #FLOP_DELAY DBITERR_IN;\n end\n\n always @* begin\n DOUT = dout_i;\n RDADDRECC = rdaddrecc_i;\n SBITERR = sbiterr_i;\n DBITERR = dbiterr_i;\n end //end always\n end //end in_or_out_stage generate statement\n endgenerate\n\nendmodule\n\n\n//*****************************************************************************\n// Main Memory module\n//\n// This module is the top-level behavioral model and this implements the RAM \n//*****************************************************************************\nmodule blk_mem_gen_v8_3_4_mem_module\n #(parameter C_CORENAME = \"blk_mem_gen_v8_3_4\",\n parameter C_FAMILY = \"virtex7\",\n parameter C_XDEVICEFAMILY = \"virtex7\",\n parameter C_MEM_TYPE = 2,\n parameter C_BYTE_SIZE = 9,\n parameter C_USE_BRAM_BLOCK = 0,\n parameter C_ALGORITHM = 1,\n parameter C_PRIM_TYPE = 3,\n parameter C_LOAD_INIT_FILE = 0,\n parameter C_INIT_FILE_NAME = \"\",\n parameter C_INIT_FILE = \"\",\n parameter C_USE_DEFAULT_DATA = 0,\n parameter C_DEFAULT_DATA = \"0\",\n parameter C_RST_TYPE = \"SYNC\",\n parameter C_HAS_RSTA = 0,\n parameter C_RST_PRIORITY_A = \"CE\",\n parameter C_RSTRAM_A = 0,\n parameter C_INITA_VAL = \"0\",\n parameter C_HAS_ENA = 1,\n parameter C_HAS_REGCEA = 0,\n parameter C_USE_BYTE_WEA = 0,\n parameter C_WEA_WIDTH = 1,\n parameter C_WRITE_MODE_A = \"WRITE_FIRST\",\n parameter C_WRITE_WIDTH_A = 32,\n parameter C_READ_WIDTH_A = 32,\n parameter C_WRITE_DEPTH_A = 64,\n parameter C_READ_DEPTH_A = 64,\n parameter C_ADDRA_WIDTH = 5,\n parameter C_HAS_RSTB = 0,\n parameter C_RST_PRIORITY_B = \"CE\",\n parameter C_RSTRAM_B = 0,\n parameter C_INITB_VAL = \"\",\n parameter C_HAS_ENB = 1,\n parameter C_HAS_REGCEB = 0,\n parameter C_USE_BYTE_WEB = 0,\n parameter C_WEB_WIDTH = 1,\n parameter C_WRITE_MODE_B = \"WRITE_FIRST\",\n parameter C_WRITE_WIDTH_B = 32,\n parameter C_READ_WIDTH_B = 32,\n parameter C_WRITE_DEPTH_B = 64,\n parameter C_READ_DEPTH_B = 64,\n parameter C_ADDRB_WIDTH = 5,\n parameter C_HAS_MEM_OUTPUT_REGS_A = 0,\n parameter C_HAS_MEM_OUTPUT_REGS_B = 0,\n parameter C_HAS_MUX_OUTPUT_REGS_A = 0,\n parameter C_HAS_MUX_OUTPUT_REGS_B = 0,\n parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n parameter C_MUX_PIPELINE_STAGES = 0,\n parameter C_USE_SOFTECC = 0,\n parameter C_USE_ECC = 0,\n parameter C_HAS_INJECTERR = 0,\n parameter C_SIM_COLLISION_CHECK = \"NONE\",\n parameter C_COMMON_CLK = 1,\n parameter FLOP_DELAY = 100,\n parameter C_DISABLE_WARN_BHV_COLL = 0,\n\tparameter C_EN_ECC_PIPE = 0,\n parameter C_DISABLE_WARN_BHV_RANGE = 0\n )\n (input CLKA,\n input RSTA,\n input ENA,\n input REGCEA,\n input [C_WEA_WIDTH-1:0] WEA,\n input [C_ADDRA_WIDTH-1:0] ADDRA,\n input [C_WRITE_WIDTH_A-1:0] DINA,\n output [C_READ_WIDTH_A-1:0] DOUTA,\n input CLKB,\n input RSTB,\n input ENB,\n input REGCEB,\n input [C_WEB_WIDTH-1:0] WEB,\n input [C_ADDRB_WIDTH-1:0] ADDRB,\n input [C_WRITE_WIDTH_B-1:0] DINB,\n output [C_READ_WIDTH_B-1:0] DOUTB,\n input INJECTSBITERR,\n input INJECTDBITERR,\n input ECCPIPECE,\n input SLEEP,\n output SBITERR,\n output DBITERR,\n output [C_ADDRB_WIDTH-1:0] RDADDRECC\n );\n//******************************\n// Port and Generic Definitions\n//******************************\n //////////////////////////////////////////////////////////////////////////\n // Generic Definitions\n //////////////////////////////////////////////////////////////////////////\n // C_CORENAME : Instance name of the Block Memory Generator core\n // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n // options are available - \"spartan3\", \"spartan6\", \n // \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n // C_MEM_TYPE : Designates memory type.\n // It can be\n // 0 - Single Port Memory\n // 1 - Simple Dual Port Memory\n // 2 - True Dual Port Memory\n // 3 - Single Port Read Only Memory\n // 4 - Dual Port Read Only Memory\n // C_BYTE_SIZE : Size of a byte (8 or 9 bits)\n // C_ALGORITHM : Designates the algorithm method used\n // for constructing the memory.\n // It can be Fixed_Primitives, Minimum_Area or \n // Low_Power\n // C_PRIM_TYPE : Designates the user selected primitive used to \n // construct the memory.\n //\n // C_LOAD_INIT_FILE : Designates the use of an initialization file to\n // initialize memory contents.\n // C_INIT_FILE_NAME : Memory initialization file name.\n // C_USE_DEFAULT_DATA : Designates whether to fill remaining\n // initialization space with default data\n // C_DEFAULT_DATA : Default value of all memory locations\n // not initialized by the memory\n // initialization file.\n // C_RST_TYPE : Type of reset - Synchronous or Asynchronous\n // C_HAS_RSTA : Determines the presence of the RSTA port\n // C_RST_PRIORITY_A : Determines the priority between CE and SR for \n // Port A.\n // C_RSTRAM_A : Determines if special reset behavior is used for\n // Port A\n // C_INITA_VAL : The initialization value for Port A\n // C_HAS_ENA : Determines the presence of the ENA port\n // C_HAS_REGCEA : Determines the presence of the REGCEA port\n // C_USE_BYTE_WEA : Determines if the Byte Write is used or not.\n // C_WEA_WIDTH : The width of the WEA port\n // C_WRITE_MODE_A : Configurable write mode for Port A. It can be\n // WRITE_FIRST, READ_FIRST or NO_CHANGE.\n // C_WRITE_WIDTH_A : Memory write width for Port A.\n // C_READ_WIDTH_A : Memory read width for Port A.\n // C_WRITE_DEPTH_A : Memory write depth for Port A.\n // C_READ_DEPTH_A : Memory read depth for Port A.\n // C_ADDRA_WIDTH : Width of the ADDRA input port\n // C_HAS_RSTB : Determines the presence of the RSTB port\n // C_RST_PRIORITY_B : Determines the priority between CE and SR for \n // Port B.\n // C_RSTRAM_B : Determines if special reset behavior is used for\n // Port B\n // C_INITB_VAL : The initialization value for Port B\n // C_HAS_ENB : Determines the presence of the ENB port\n // C_HAS_REGCEB : Determines the presence of the REGCEB port\n // C_USE_BYTE_WEB : Determines if the Byte Write is used or not.\n // C_WEB_WIDTH : The width of the WEB port\n // C_WRITE_MODE_B : Configurable write mode for Port B. It can be\n // WRITE_FIRST, READ_FIRST or NO_CHANGE.\n // C_WRITE_WIDTH_B : Memory write width for Port B.\n // C_READ_WIDTH_B : Memory read width for Port B.\n // C_WRITE_DEPTH_B : Memory write depth for Port B.\n // C_READ_DEPTH_B : Memory read depth for Port B.\n // C_ADDRB_WIDTH : Width of the ADDRB input port\n // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n // of the RAM primitive for Port A.\n // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n // of the RAM primitive for Port B.\n // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n // of the MUX for Port A.\n // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n // of the MUX for Port B.\n // C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in \n // between the muxes.\n // C_USE_SOFTECC : Determines if the Soft ECC feature is used or\n // not. Only applicable Spartan-6\n // C_USE_ECC : Determines if the ECC feature is used or\n // not. Only applicable for V5 and V6\n // C_HAS_INJECTERR : Determines if the error injection pins\n // are present or not. If the ECC feature\n // is not used, this value is defaulted to\n // 0, else the following are the allowed \n // values:\n // 0 : No INJECTSBITERR or INJECTDBITERR pins\n // 1 : Only INJECTSBITERR pin exists\n // 2 : Only INJECTDBITERR pin exists\n // 3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n // C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision\n // warnings. It can be \"ALL\", \"NONE\", \n // \"Warnings_Only\" or \"Generate_X_Only\".\n // C_COMMON_CLK : Determins if the core has a single CLK input.\n // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n // warnings\n //////////////////////////////////////////////////////////////////////////\n // Port Definitions\n //////////////////////////////////////////////////////////////////////////\n // CLKA : Clock to synchronize all read and write operations of Port A.\n // RSTA : Reset input to reset memory outputs to a user-defined \n // reset state for Port A.\n // ENA : Enable all read and write operations of Port A.\n // REGCEA : Register Clock Enable to control each pipeline output\n // register stages for Port A.\n // WEA : Write Enable to enable all write operations of Port A.\n // ADDRA : Address of Port A.\n // DINA : Data input of Port A.\n // DOUTA : Data output of Port A.\n // CLKB : Clock to synchronize all read and write operations of Port B.\n // RSTB : Reset input to reset memory outputs to a user-defined \n // reset state for Port B.\n // ENB : Enable all read and write operations of Port B.\n // REGCEB : Register Clock Enable to control each pipeline output\n // register stages for Port B.\n // WEB : Write Enable to enable all write operations of Port B.\n // ADDRB : Address of Port B.\n // DINB : Data input of Port B.\n // DOUTB : Data output of Port B.\n // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n // SBITERR : Output signal indicating that a Single Bit ECC Error has been\n // detected and corrected.\n // DBITERR : Output signal indicating that a Double Bit ECC Error has been\n // detected.\n // RDADDRECC : Read Address Output signal indicating address at which an\n // ECC error has occurred.\n //////////////////////////////////////////////////////////////////////////\n\n\n// Note: C_CORENAME parameter is hard-coded to \"blk_mem_gen_v8_3_4\" and it is\n// only used by this module to print warning messages. It is neither passed \n// down from blk_mem_gen_v8_3_4_xst.v nor present in the instantiation template\n// coregen generates\n \n //***************************************************************************\n // constants for the core behavior\n //***************************************************************************\n // file handles for logging\n //--------------------------------------------------\n localparam ADDRFILE = 32'h8000_0001; //stdout for addr out of range\n localparam COLLFILE = 32'h8000_0001; //stdout for coll detection\n localparam ERRFILE = 32'h8000_0001; //stdout for file I/O errors\n\n // other constants\n //--------------------------------------------------\n localparam COLL_DELAY = 100; // 100 ps\n\n // locally derived parameters to determine memory shape\n //-----------------------------------------------------\n\n localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); \n\n localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?\n C_WRITE_WIDTH_A : C_READ_WIDTH_A;\n localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?\n C_WRITE_WIDTH_B : C_READ_WIDTH_B;\n localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?\n MIN_WIDTH_A : MIN_WIDTH_B;\n\n localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?\n C_WRITE_DEPTH_A : C_READ_DEPTH_A;\n localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?\n C_WRITE_DEPTH_B : C_READ_DEPTH_B;\n localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?\n MAX_DEPTH_A : MAX_DEPTH_B;\n\n\n // locally derived parameters to assist memory access\n //----------------------------------------------------\n // Calculate the width ratios of each port with respect to the narrowest\n // port\n localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;\n localparam READ_WIDTH_RATIO_A = C_READ_WIDTH_A/MIN_WIDTH;\n localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;\n localparam READ_WIDTH_RATIO_B = C_READ_WIDTH_B/MIN_WIDTH;\n\n // To modify the LSBs of the 'wider' data to the actual\n // address value\n //----------------------------------------------------\n localparam WRITE_ADDR_A_DIV = C_WRITE_WIDTH_A/MIN_WIDTH_A;\n localparam READ_ADDR_A_DIV = C_READ_WIDTH_A/MIN_WIDTH_A;\n localparam WRITE_ADDR_B_DIV = C_WRITE_WIDTH_B/MIN_WIDTH_B;\n localparam READ_ADDR_B_DIV = C_READ_WIDTH_B/MIN_WIDTH_B;\n\n // If byte writes aren't being used, make sure BYTE_SIZE is not\n // wider than the memory elements to avoid compilation warnings\n localparam BYTE_SIZE = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;\n\n // The memory\n reg [MIN_WIDTH-1:0] memory [0:MAX_DEPTH-1];\n reg [MIN_WIDTH-1:0] temp_mem_array [0:MAX_DEPTH-1];\n reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;\n // ECC error arrays\n reg sbiterr_arr [0:MAX_DEPTH-1];\n reg dbiterr_arr [0:MAX_DEPTH-1];\n\n reg softecc_sbiterr_arr [0:MAX_DEPTH-1];\n reg softecc_dbiterr_arr [0:MAX_DEPTH-1];\n // Memory output 'latches'\n reg [C_READ_WIDTH_A-1:0] memory_out_a;\n reg [C_READ_WIDTH_B-1:0] memory_out_b;\n\n // ECC error inputs and outputs from output_stage module:\n reg sbiterr_in;\n wire sbiterr_sdp;\n reg dbiterr_in;\n wire dbiterr_sdp;\n\n wire [C_READ_WIDTH_B-1:0] dout_i;\n wire dbiterr_i;\n wire sbiterr_i;\n wire [C_ADDRB_WIDTH-1:0] rdaddrecc_i;\n\n reg [C_ADDRB_WIDTH-1:0] rdaddrecc_in;\n wire [C_ADDRB_WIDTH-1:0] rdaddrecc_sdp;\n\n // Reset values\n reg [C_READ_WIDTH_A-1:0] inita_val;\n reg [C_READ_WIDTH_B-1:0] initb_val;\n\n // Collision detect\n reg is_collision;\n reg is_collision_a, is_collision_delay_a;\n reg is_collision_b, is_collision_delay_b;\n\n // Temporary variables for initialization\n //---------------------------------------\n integer status;\n integer initfile;\n integer meminitfile;\n // data input buffer\n reg [C_WRITE_WIDTH_A-1:0] mif_data;\n reg [C_WRITE_WIDTH_A-1:0] mem_data;\n // string values in hex\n reg [C_READ_WIDTH_A*8-1:0] inita_str = C_INITA_VAL;\n reg [C_READ_WIDTH_B*8-1:0] initb_str = C_INITB_VAL;\n reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA;\n // initialization filename\n reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME;\n reg [1023*8-1:0] mem_init_file_str = C_INIT_FILE;\n\n\n //Constants used to calculate the effective address widths for each of the \n //four ports. \n integer cnt = 1;\n integer write_addr_a_width, read_addr_a_width;\n integer write_addr_b_width, read_addr_b_width;\n\n localparam C_FAMILY_LOCALPARAM = (C_FAMILY==\"zynquplus\"?\"virtex7\":(C_FAMILY==\"kintexuplus\"?\"virtex7\":(C_FAMILY==\"virtexuplus\"?\"virtex7\":(C_FAMILY==\"virtexu\"?\"virtex7\":(C_FAMILY==\"kintexu\" ? \"virtex7\":(C_FAMILY==\"virtex7\" ? \"virtex7\" : (C_FAMILY==\"virtex7l\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7l\" ? \"virtex7\" : (C_FAMILY==\"kintex7\" ? \"virtex7\" : (C_FAMILY==\"kintex7l\" ? \"virtex7\" : (C_FAMILY==\"qkintex7\" ? \"virtex7\" : (C_FAMILY==\"qkintex7l\" ? \"virtex7\" : (C_FAMILY==\"artix7\" ? \"virtex7\" : (C_FAMILY==\"artix7l\" ? \"virtex7\" : (C_FAMILY==\"qartix7\" ? \"virtex7\" : (C_FAMILY==\"qartix7l\" ? \"virtex7\" : (C_FAMILY==\"aartix7\" ? \"virtex7\" : (C_FAMILY==\"zynq\" ? \"virtex7\" : (C_FAMILY==\"azynq\" ? \"virtex7\" : (C_FAMILY==\"qzynq\" ? \"virtex7\" : C_FAMILY)))))))))))))))))))));\n\n // Internal configuration parameters\n //---------------------------------------------\n localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);\n localparam IS_ROM = (C_MEM_TYPE==3 || C_MEM_TYPE==4);\n localparam HAS_A_WRITE = (!IS_ROM);\n localparam HAS_B_WRITE = (C_MEM_TYPE==2);\n localparam HAS_A_READ = (C_MEM_TYPE!=1);\n localparam HAS_B_READ = (!SINGLE_PORT);\n localparam HAS_B_PORT = (HAS_B_READ || HAS_B_WRITE);\n\n // Calculate the mux pipeline register stages for Port A and Port B\n //------------------------------------------------------------------\n localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?\n C_MUX_PIPELINE_STAGES : 0;\n localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?\n C_MUX_PIPELINE_STAGES : 0;\n \n // Calculate total number of register stages in the core\n // -----------------------------------------------------\n localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);\n\n localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);\n\n wire ena_i;\n wire enb_i;\n wire reseta_i;\n wire resetb_i;\n wire [C_WEA_WIDTH-1:0] wea_i;\n wire [C_WEB_WIDTH-1:0] web_i;\n wire rea_i;\n wire reb_i;\n wire rsta_outp_stage;\n wire rstb_outp_stage;\n // ECC SBITERR/DBITERR Outputs\n // The ECC Behavior is modeled by the behavioral models only for Virtex-6.\n // For Virtex-5, these outputs will be tied to 0.\n assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;\n assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;\n assign RDADDRECC = (((C_FAMILY_LOCALPARAM == \"virtex7\") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;\n\n\n // This effectively wires off optional inputs\n assign ena_i = (C_HAS_ENA==0) || ENA;\n assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;\n //assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;\n // To Fix CR855535\n assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;\n assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;\n assign rea_i = (HAS_A_READ) ? ena_i : 'b0;\n assign reb_i = (HAS_B_READ) ? enb_i : 'b0;\n\n // These signals reset the memory latches\n\n assign reseta_i = \n ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||\n (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));\n\n assign resetb_i = \n ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||\n (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));\n\n // Tasks to access the memory\n //---------------------------\n //**************\n // write_a\n //**************\n task write_a\n (input reg [C_ADDRA_WIDTH-1:0] addr,\n input reg [C_WEA_WIDTH-1:0] byte_en,\n input reg [C_WRITE_WIDTH_A-1:0] data,\n input inj_sbiterr,\n input inj_dbiterr);\n reg [C_WRITE_WIDTH_A-1:0] current_contents;\n reg [C_ADDRA_WIDTH-1:0] address;\n integer i;\n begin\n // Shift the address by the ratio\n address = (addr/WRITE_ADDR_A_DIV);\n if (address >= C_WRITE_DEPTH_A) begin\n if (!C_DISABLE_WARN_BHV_RANGE) begin\n $fdisplay(ADDRFILE,\n \"%0s WARNING: Address %0h is outside range for A Write\",\n C_CORENAME, addr);\n end\n\n // valid address\n end else begin\n\n // Combine w/ byte writes\n if (C_USE_BYTE_WEA) begin\n\n // Get the current memory contents\n if (WRITE_WIDTH_RATIO_A == 1) begin\n // Workaround for IUS 5.5 part-select issue\n current_contents = memory[address];\n end else begin\n for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n = memory[address*WRITE_WIDTH_RATIO_A + i];\n end\n end\n\n // Apply incoming bytes\n if (C_WEA_WIDTH == 1) begin\n // Workaround for IUS 5.5 part-select issue\n if (byte_en[0]) begin\n current_contents = data;\n end\n end else begin\n for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin\n if (byte_en[i]) begin\n current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n = data[BYTE_SIZE*i+:BYTE_SIZE];\n end\n end\n end\n\n // No byte-writes, overwrite the whole word\n end else begin\n current_contents = data;\n end\n\n // Insert double bit errors:\n if (C_USE_ECC == 1) begin\n if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n// Modified for Implementing CR_859399 \n current_contents[0] = !(current_contents[30]);\n current_contents[1] = !(current_contents[62]);\n \n /*current_contents[0] = !(current_contents[0]);\n current_contents[1] = !(current_contents[1]);*/\n end\n end\n \n // Insert softecc double bit errors:\n if (C_USE_SOFTECC == 1) begin\n if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];\n doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];\n doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];\n current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];\n end\n end\n \n // Write data to memory\n if (WRITE_WIDTH_RATIO_A == 1) begin\n // Workaround for IUS 5.5 part-select issue\n memory[address*WRITE_WIDTH_RATIO_A] = current_contents;\n end else begin\n for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n memory[address*WRITE_WIDTH_RATIO_A + i]\n = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n end\n end\n\n // Store the address at which error is injected:\n if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n begin\n sbiterr_arr[addr] = 1;\n end else begin\n sbiterr_arr[addr] = 0;\n end\n \n if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n dbiterr_arr[addr] = 1;\n end else begin\n dbiterr_arr[addr] = 0;\n end\n end\n\n // Store the address at which softecc error is injected:\n if (C_USE_SOFTECC == 1) begin\n if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n begin\n softecc_sbiterr_arr[addr] = 1;\n end else begin\n softecc_sbiterr_arr[addr] = 0;\n end\n \n if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n softecc_dbiterr_arr[addr] = 1;\n end else begin\n softecc_dbiterr_arr[addr] = 0;\n end\n end\n\n end\n end\n endtask\n\n //**************\n // write_b\n //**************\n task write_b\n (input reg [C_ADDRB_WIDTH-1:0] addr,\n input reg [C_WEB_WIDTH-1:0] byte_en,\n input reg [C_WRITE_WIDTH_B-1:0] data);\n reg [C_WRITE_WIDTH_B-1:0] current_contents;\n reg [C_ADDRB_WIDTH-1:0] address;\n integer i;\n begin\n // Shift the address by the ratio\n address = (addr/WRITE_ADDR_B_DIV);\n if (address >= C_WRITE_DEPTH_B) begin\n if (!C_DISABLE_WARN_BHV_RANGE) begin\n $fdisplay(ADDRFILE,\n \"%0s WARNING: Address %0h is outside range for B Write\",\n C_CORENAME, addr);\n end\n\n // valid address\n end else begin\n\n // Combine w/ byte writes\n if (C_USE_BYTE_WEB) begin\n\n // Get the current memory contents\n if (WRITE_WIDTH_RATIO_B == 1) begin\n // Workaround for IUS 5.5 part-select issue\n current_contents = memory[address];\n end else begin\n for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n = memory[address*WRITE_WIDTH_RATIO_B + i];\n end\n end\n\n // Apply incoming bytes\n if (C_WEB_WIDTH == 1) begin\n // Workaround for IUS 5.5 part-select issue\n if (byte_en[0]) begin\n current_contents = data;\n end\n end else begin\n for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin\n if (byte_en[i]) begin\n current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n = data[BYTE_SIZE*i+:BYTE_SIZE];\n end\n end\n end\n\n // No byte-writes, overwrite the whole word\n end else begin\n current_contents = data;\n end\n\n // Write data to memory\n if (WRITE_WIDTH_RATIO_B == 1) begin\n // Workaround for IUS 5.5 part-select issue\n memory[address*WRITE_WIDTH_RATIO_B] = current_contents;\n end else begin\n for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n memory[address*WRITE_WIDTH_RATIO_B + i]\n = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n end\n end\n end\n end\n endtask\n\n //**************\n // read_a\n //**************\n task read_a\n (input reg [C_ADDRA_WIDTH-1:0] addr,\n input reg reset);\n reg [C_ADDRA_WIDTH-1:0] address;\n integer i;\n begin\n\n if (reset) begin\n memory_out_a <= #FLOP_DELAY inita_val;\n end else begin\n // Shift the address by the ratio\n address = (addr/READ_ADDR_A_DIV);\n if (address >= C_READ_DEPTH_A) begin\n if (!C_DISABLE_WARN_BHV_RANGE) begin\n $fdisplay(ADDRFILE,\n \"%0s WARNING: Address %0h is outside range for A Read\",\n C_CORENAME, addr);\n end\n memory_out_a <= #FLOP_DELAY 'bX;\n // valid address\n end else begin\n if (READ_WIDTH_RATIO_A==1) begin\n memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];\n end else begin\n // Increment through the 'partial' words in the memory\n for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin\n memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]\n <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];\n end\n end //end READ_WIDTH_RATIO_A==1 loop\n\n end //end valid address loop\n end //end reset-data assignment loops\n end\n endtask\n\n //**************\n // read_b\n //**************\n task read_b\n (input reg [C_ADDRB_WIDTH-1:0] addr,\n input reg reset);\n reg [C_ADDRB_WIDTH-1:0] address;\n integer i;\n begin\n\n if (reset) begin\n memory_out_b <= #FLOP_DELAY initb_val;\n sbiterr_in <= #FLOP_DELAY 1'b0;\n dbiterr_in <= #FLOP_DELAY 1'b0;\n rdaddrecc_in <= #FLOP_DELAY 0;\n end else begin\n // Shift the address\n address = (addr/READ_ADDR_B_DIV);\n if (address >= C_READ_DEPTH_B) begin\n if (!C_DISABLE_WARN_BHV_RANGE) begin\n $fdisplay(ADDRFILE,\n \"%0s WARNING: Address %0h is outside range for B Read\",\n C_CORENAME, addr);\n end\n memory_out_b <= #FLOP_DELAY 'bX;\n sbiterr_in <= #FLOP_DELAY 1'bX;\n dbiterr_in <= #FLOP_DELAY 1'bX;\n rdaddrecc_in <= #FLOP_DELAY 'bX;\n // valid address\n end else begin\n if (READ_WIDTH_RATIO_B==1) begin\n memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];\n end else begin\n // Increment through the 'partial' words in the memory\n for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin\n memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]\n <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];\n end\n end\n\n if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n rdaddrecc_in <= #FLOP_DELAY addr;\n if (sbiterr_arr[addr] == 1) begin\n sbiterr_in <= #FLOP_DELAY 1'b1;\n end else begin\n sbiterr_in <= #FLOP_DELAY 1'b0;\n end\n\n if (dbiterr_arr[addr] == 1) begin\n dbiterr_in <= #FLOP_DELAY 1'b1;\n end else begin\n dbiterr_in <= #FLOP_DELAY 1'b0;\n end\n\n end else if (C_USE_SOFTECC == 1) begin\n rdaddrecc_in <= #FLOP_DELAY addr;\n if (softecc_sbiterr_arr[addr] == 1) begin\n sbiterr_in <= #FLOP_DELAY 1'b1;\n end else begin\n sbiterr_in <= #FLOP_DELAY 1'b0;\n end\n\n if (softecc_dbiterr_arr[addr] == 1) begin\n dbiterr_in <= #FLOP_DELAY 1'b1;\n end else begin\n dbiterr_in <= #FLOP_DELAY 1'b0;\n end\n end else begin\n rdaddrecc_in <= #FLOP_DELAY 0;\n dbiterr_in <= #FLOP_DELAY 1'b0;\n sbiterr_in <= #FLOP_DELAY 1'b0;\n end //end SOFTECC Loop\n end //end Valid address loop\n end //end reset-data assignment loops\n end\n endtask\n\n //**************\n // reset_a\n //**************\n task reset_a (input reg reset);\n begin\n if (reset) memory_out_a <= #FLOP_DELAY inita_val;\n end\n endtask\n\n //**************\n // reset_b\n //**************\n task reset_b (input reg reset);\n begin\n if (reset) memory_out_b <= #FLOP_DELAY initb_val;\n end\n endtask\n\n //**************\n // init_memory\n //**************\n task init_memory;\n integer i, j, addr_step;\n integer status;\n reg [C_WRITE_WIDTH_A-1:0] default_data;\n begin\n default_data = 0;\n\n //Display output message indicating that the behavioral model is being \n //initialized\n if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(\" Block Memory Generator module loading initial data...\");\n\n // Convert the default to hex\n if (C_USE_DEFAULT_DATA) begin\n if (default_data_str == \"\") begin\n $fdisplay(ERRFILE, \"%0s ERROR: C_DEFAULT_DATA is empty!\", C_CORENAME);\n $finish;\n end else begin\n status = $sscanf(default_data_str, \"%h\", default_data);\n if (status == 0) begin\n $fdisplay(ERRFILE, {\"%0s ERROR: Unsuccessful hexadecimal read\",\n \"from C_DEFAULT_DATA: %0s\"},\n C_CORENAME, C_DEFAULT_DATA);\n $finish;\n end\n end\n end\n\n // Step by WRITE_ADDR_A_DIV through the memory via the\n // Port A write interface to hit every location once\n addr_step = WRITE_ADDR_A_DIV;\n\n // 'write' to every location with default (or 0)\n for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);\n end\n\n // Get specialized data from the MIF file\n if (C_LOAD_INIT_FILE) begin\n if (init_file_str == \"\") begin\n $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE_NAME is empty!\",\n C_CORENAME);\n $finish;\n end else begin\n initfile = $fopen(init_file_str, \"r\");\n if (initfile == 0) begin\n $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n \"C_INIT_FILE_NAME: %0s!\"},\n C_CORENAME, init_file_str);\n $finish;\n end else begin\n // loop through the mif file, loading in the data\n for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n status = $fscanf(initfile, \"%b\", mif_data);\n if (status > 0) begin\n write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);\n end\n end\n $fclose(initfile);\n end //initfile\n end //init_file_str\n end //C_LOAD_INIT_FILE\n\n\n if (C_USE_BRAM_BLOCK) begin\n // Get specialized data from the MIF file\n if (C_INIT_FILE != \"NONE\") begin\n if (mem_init_file_str == \"\") begin\n $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE is empty!\",\n C_CORENAME);\n $finish;\n end else begin\n meminitfile = $fopen(mem_init_file_str, \"r\");\n if (meminitfile == 0) begin\n $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n \"C_INIT_FILE: %0s!\"},\n C_CORENAME, mem_init_file_str);\n $finish;\n end else begin\n // loop through the mif file, loading in the data\n $readmemh(mem_init_file_str, memory );\n for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin\n end \n $fclose(meminitfile);\n end //meminitfile\n end //mem_init_file_str\n end //C_INIT_FILE\n end //C_USE_BRAM_BLOCK\n\n //Display output message indicating that the behavioral model is done \n //initializing\n if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) \n $display(\" Block Memory Generator data initialization complete.\");\n end\n endtask\n\n //**************\n // log2roundup\n //**************\n function integer log2roundup (input integer data_value);\n integer width;\n integer cnt;\n begin\n width = 0;\n\n if (data_value > 1) begin\n for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n width = width + 1;\n end //loop\n end //if\n\n log2roundup = width;\n\n end //log2roundup\n endfunction\n\n\n //*******************\n // collision_check\n //*******************\n function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,\n input integer iswrite_a,\n input reg [C_ADDRB_WIDTH-1:0] addr_b,\n input integer iswrite_b);\n reg c_aw_bw, c_aw_br, c_ar_bw;\n integer scaled_addra_to_waddrb_width;\n integer scaled_addrb_to_waddrb_width;\n integer scaled_addra_to_waddra_width;\n integer scaled_addrb_to_waddra_width;\n integer scaled_addra_to_raddrb_width;\n integer scaled_addrb_to_raddrb_width;\n integer scaled_addra_to_raddra_width;\n integer scaled_addrb_to_raddra_width;\n\n\n\n begin\n\n c_aw_bw = 0;\n c_aw_br = 0;\n c_ar_bw = 0;\n\n //If write_addr_b_width is smaller, scale both addresses to that width for \n //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n //scale it down to write_addr_b_width. Once both are scaled to \n //write_addr_b_width, compare.\n scaled_addra_to_waddrb_width = ((addr_a)/\n 2**(C_ADDRA_WIDTH-write_addr_b_width));\n scaled_addrb_to_waddrb_width = ((addr_b)/\n 2**(C_ADDRB_WIDTH-write_addr_b_width));\n\n //If write_addr_a_width is smaller, scale both addresses to that width for \n //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n //scale it down to write_addr_a_width. Once both are scaled to \n //write_addr_a_width, compare.\n scaled_addra_to_waddra_width = ((addr_a)/\n 2**(C_ADDRA_WIDTH-write_addr_a_width));\n scaled_addrb_to_waddra_width = ((addr_b)/\n 2**(C_ADDRB_WIDTH-write_addr_a_width));\n\n //If read_addr_b_width is smaller, scale both addresses to that width for \n //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,\n //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n //scale it down to read_addr_b_width. Once both are scaled to \n //read_addr_b_width, compare.\n scaled_addra_to_raddrb_width = ((addr_a)/\n 2**(C_ADDRA_WIDTH-read_addr_b_width));\n scaled_addrb_to_raddrb_width = ((addr_b)/\n 2**(C_ADDRB_WIDTH-read_addr_b_width));\n\n //If read_addr_a_width is smaller, scale both addresses to that width for \n //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n //scale it down to read_addr_a_width. Once both are scaled to \n //read_addr_a_width, compare.\n scaled_addra_to_raddra_width = ((addr_a)/\n 2**(C_ADDRA_WIDTH-read_addr_a_width));\n scaled_addrb_to_raddra_width = ((addr_b)/\n 2**(C_ADDRB_WIDTH-read_addr_a_width));\n\n //Look for a write-write collision. In order for a write-write\n //collision to exist, both ports must have a write transaction.\n if (iswrite_a && iswrite_b) begin\n if (write_addr_a_width > write_addr_b_width) begin\n if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n c_aw_bw = 1;\n end else begin\n c_aw_bw = 0;\n end\n end else begin\n if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n c_aw_bw = 1;\n end else begin\n c_aw_bw = 0;\n end\n end //width\n end //iswrite_a and iswrite_b\n\n //If the B port is reading (which means it is enabled - so could be\n //a TX_WRITE or TX_READ), then check for a write-read collision).\n //This could happen whether or not a write-write collision exists due\n //to asymmetric write/read ports.\n if (iswrite_a) begin\n if (write_addr_a_width > read_addr_b_width) begin\n if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin\n c_aw_br = 1;\n end else begin\n c_aw_br = 0;\n end\n end else begin\n if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n c_aw_br = 1;\n end else begin\n c_aw_br = 0;\n end\n end //width\n end //iswrite_a\n\n //If the A port is reading (which means it is enabled - so could be\n // a TX_WRITE or TX_READ), then check for a write-read collision).\n //This could happen whether or not a write-write collision exists due\n // to asymmetric write/read ports.\n if (iswrite_b) begin\n if (read_addr_a_width > write_addr_b_width) begin\n if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n c_ar_bw = 1;\n end else begin\n c_ar_bw = 0;\n end\n end else begin\n if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin\n c_ar_bw = 1;\n end else begin\n c_ar_bw = 0;\n end\n end //width\n end //iswrite_b\n\n\n\n collision_check = c_aw_bw | c_aw_br | c_ar_bw;\n\n end\n endfunction\n\n //*******************************\n // power on values\n //*******************************\n initial begin\n // Load up the memory\n init_memory;\n // Load up the output registers and latches\n if ($sscanf(inita_str, \"%h\", inita_val)) begin\n memory_out_a = inita_val;\n end else begin\n memory_out_a = 0;\n end\n if ($sscanf(initb_str, \"%h\", initb_val)) begin\n memory_out_b = initb_val;\n end else begin\n memory_out_b = 0;\n end\n\n sbiterr_in = 1'b0;\n dbiterr_in = 1'b0;\n rdaddrecc_in = 0;\n\n // Determine the effective address widths for each of the 4 ports\n write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);\n read_addr_a_width = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);\n write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);\n read_addr_b_width = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);\n\n $display(\"Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.\");\n\n end\n\n //***************************************************************************\n // These are the main blocks which schedule read and write operations\n // Note that the reset priority feature at the latch stage is only supported\n // for Spartan-6. For other families, the default priority at the latch stage\n // is \"CE\"\n //***************************************************************************\n // Synchronous clocks: schedule port operations with respect to\n // both write operating modes\n generate\n if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n \"WRITE_FIRST\")) begin : com_clk_sched_wf_wf\n always @(posedge CLKA) begin\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n \n if (rea_i) read_a(ADDRA, reseta_i);\n \n //Read B\n if (reb_i) read_b(ADDRB, resetb_i);\n end\n end\n else \n if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n \"WRITE_FIRST\")) begin : com_clk_sched_rf_wf\n always @(posedge CLKA) begin\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n //Read B\n if (reb_i) read_b(ADDRB, resetb_i);\n //Read A\n if (rea_i) read_a(ADDRA, reseta_i);\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n end\n end\n else \n if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n \"READ_FIRST\")) begin : com_clk_sched_wf_rf\n always @(posedge CLKA) begin\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n //Read A\n if (rea_i) read_a(ADDRA, reseta_i);\n //Read B\n if (reb_i) read_b(ADDRB, resetb_i);\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n end\n end\n else \n if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n \"READ_FIRST\")) begin : com_clk_sched_rf_rf\n always @(posedge CLKA) begin\n //Read A\n if (rea_i) read_a(ADDRA, reseta_i);\n //Read B\n if (reb_i) read_b(ADDRB, resetb_i);\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n end\n end\n else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n \"NO_CHANGE\")) begin : com_clk_sched_wf_nc\n always @(posedge CLKA) begin\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n //Read A\n if (rea_i) read_a(ADDRA, reseta_i);\n //Read B\n if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n end\n end\n else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"READ_FIRST\") && (C_WRITE_MODE_B ==\n \"NO_CHANGE\")) begin : com_clk_sched_rf_nc\n always @(posedge CLKA) begin\n //Read A\n if (rea_i) read_a(ADDRA, reseta_i);\n //Read B\n if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n end\n end\n else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n \"WRITE_FIRST\")) begin : com_clk_sched_nc_wf\n always @(posedge CLKA) begin\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n //Read A\n if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n //Read B\n if (reb_i) read_b(ADDRB, resetb_i);\n end\n end\n else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B == \n \"READ_FIRST\")) begin : com_clk_sched_nc_rf\n always @(posedge CLKA) begin\n //Read B\n if (reb_i) read_b(ADDRB, resetb_i);\n //Read A\n if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n end\n end\n else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n \"NO_CHANGE\")) begin : com_clk_sched_nc_nc\n always @(posedge CLKA) begin\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n //Read A\n if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n //Read B\n if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n end\n end\n else if(C_COMMON_CLK) begin: com_clk_sched_default\n always @(posedge CLKA) begin\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n //Read A\n if (rea_i) read_a(ADDRA, reseta_i);\n //Read B\n if (reb_i) read_b(ADDRB, resetb_i);\n end\n end\n endgenerate\n\n // Asynchronous clocks: port operation is independent\n generate\n if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"WRITE_FIRST\")) begin : async_clk_sched_clka_wf\n always @(posedge CLKA) begin\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n //Read A\n if (rea_i) read_a(ADDRA, reseta_i);\n end\n end\n else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"READ_FIRST\")) begin : async_clk_sched_clka_rf\n always @(posedge CLKA) begin\n //Read A\n if (rea_i) read_a(ADDRA, reseta_i);\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n end\n end\n else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"NO_CHANGE\")) begin : async_clk_sched_clka_nc\n always @(posedge CLKA) begin\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n //Read A\n if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n end\n end\n endgenerate\n\n generate \n if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"WRITE_FIRST\")) begin: async_clk_sched_clkb_wf\n always @(posedge CLKB) begin\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n //Read B\n if (reb_i) read_b(ADDRB, resetb_i);\n end\n end\n else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"READ_FIRST\")) begin: async_clk_sched_clkb_rf\n always @(posedge CLKB) begin\n //Read B\n if (reb_i) read_b(ADDRB, resetb_i);\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n end\n end\n else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"NO_CHANGE\")) begin: async_clk_sched_clkb_nc\n always @(posedge CLKB) begin\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n //Read B\n if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n end\n end\n endgenerate\n\n \n //***************************************************************\n // Instantiate the variable depth output register stage module\n //***************************************************************\n // Port A\n \n assign rsta_outp_stage = RSTA & (~SLEEP);\n\n blk_mem_gen_v8_3_4_output_stage\n #(.C_FAMILY (C_FAMILY),\n .C_XDEVICEFAMILY (C_XDEVICEFAMILY),\n .C_RST_TYPE (\"SYNC\"),\n .C_HAS_RST (C_HAS_RSTA),\n .C_RSTRAM (C_RSTRAM_A),\n .C_RST_PRIORITY (C_RST_PRIORITY_A),\n .C_INIT_VAL (C_INITA_VAL),\n .C_HAS_EN (C_HAS_ENA),\n .C_HAS_REGCE (C_HAS_REGCEA),\n .C_DATA_WIDTH (C_READ_WIDTH_A),\n .C_ADDRB_WIDTH (C_ADDRB_WIDTH),\n .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A),\n .C_USE_SOFTECC (C_USE_SOFTECC),\n .C_USE_ECC (C_USE_ECC),\n .NUM_STAGES (NUM_OUTPUT_STAGES_A),\n\t .C_EN_ECC_PIPE (0),\n .FLOP_DELAY (FLOP_DELAY))\n reg_a\n (.CLK (CLKA),\n .RST (rsta_outp_stage),//(RSTA),\n .EN (ENA),\n .REGCE (REGCEA),\n .DIN_I (memory_out_a),\n .DOUT (DOUTA),\n .SBITERR_IN_I (1'b0),\n .DBITERR_IN_I (1'b0),\n .SBITERR (),\n .DBITERR (),\n .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),\n\t\t .ECCPIPECE (1'b0),\n .RDADDRECC ()\n );\n\n assign rstb_outp_stage = RSTB & (~SLEEP);\n\n // Port B \n blk_mem_gen_v8_3_4_output_stage\n #(.C_FAMILY (C_FAMILY),\n .C_XDEVICEFAMILY (C_XDEVICEFAMILY),\n .C_RST_TYPE (\"SYNC\"),\n .C_HAS_RST (C_HAS_RSTB),\n .C_RSTRAM (C_RSTRAM_B),\n .C_RST_PRIORITY (C_RST_PRIORITY_B),\n .C_INIT_VAL (C_INITB_VAL),\n .C_HAS_EN (C_HAS_ENB),\n .C_HAS_REGCE (C_HAS_REGCEB),\n .C_DATA_WIDTH (C_READ_WIDTH_B),\n .C_ADDRB_WIDTH (C_ADDRB_WIDTH),\n .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B),\n .C_USE_SOFTECC (C_USE_SOFTECC),\n .C_USE_ECC (C_USE_ECC),\n .NUM_STAGES (NUM_OUTPUT_STAGES_B),\n .C_EN_ECC_PIPE (C_EN_ECC_PIPE),\n .FLOP_DELAY (FLOP_DELAY))\n reg_b\n (.CLK (CLKB),\n .RST (rstb_outp_stage),//(RSTB),\n .EN (ENB),\n .REGCE (REGCEB),\n .DIN_I (memory_out_b),\n .DOUT (dout_i),\n .SBITERR_IN_I (sbiterr_in),\n .DBITERR_IN_I (dbiterr_in),\n .SBITERR (sbiterr_i),\n .DBITERR (dbiterr_i),\n .RDADDRECC_IN_I (rdaddrecc_in),\n .ECCPIPECE (ECCPIPECE),\n .RDADDRECC (rdaddrecc_i)\n );\n\n //***************************************************************\n // Instantiate the Input and Output register stages\n //***************************************************************\nblk_mem_gen_v8_3_4_softecc_output_reg_stage\n #(.C_DATA_WIDTH (C_READ_WIDTH_B),\n .C_ADDRB_WIDTH (C_ADDRB_WIDTH),\n .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),\n .C_USE_SOFTECC (C_USE_SOFTECC),\n .FLOP_DELAY (FLOP_DELAY))\n has_softecc_output_reg_stage\n (.CLK (CLKB),\n .DIN (dout_i),\n .DOUT (DOUTB),\n .SBITERR_IN (sbiterr_i),\n .DBITERR_IN (dbiterr_i),\n .SBITERR (sbiterr_sdp),\n .DBITERR (dbiterr_sdp),\n .RDADDRECC_IN (rdaddrecc_i),\n .RDADDRECC (rdaddrecc_sdp)\n);\n\n //****************************************************\n // Synchronous collision checks\n //****************************************************\n// CR 780544 : To make verilog model's collison warnings in consistant with\n// vhdl model, the non-blocking assignments are replaced with blocking \n// assignments.\n generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll\n always @(posedge CLKA) begin\n // Possible collision if both are enabled and the addresses match\n if (ena_i && enb_i) begin\n if (wea_i || web_i) begin\n is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);\n end else begin\n is_collision = 0;\n end\n end else begin\n is_collision = 0;\n end\n\n // If the write port is in READ_FIRST mode, there is no collision\n if (C_WRITE_MODE_A==\"READ_FIRST\" && wea_i && !web_i) begin\n is_collision = 0;\n end\n if (C_WRITE_MODE_B==\"READ_FIRST\" && web_i && !wea_i) begin\n is_collision = 0;\n end\n\n // Only flag if one of the accesses is a write\n if (is_collision && (wea_i || web_i)) begin\n $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n C_CORENAME, $time);\n $fwrite(COLLFILE, \"A %0s address: %0h, B %0s address: %0h\\n\",\n wea_i ? \"write\" : \"read\", ADDRA,\n web_i ? \"write\" : \"read\", ADDRB);\n end\n end\n\n //****************************************************\n // Asynchronous collision checks\n //****************************************************\n end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll\n\n // Delay A and B addresses in order to mimic setup/hold times\n wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA;\n wire [0:0] #COLL_DELAY wea_delay = wea_i;\n wire #COLL_DELAY ena_delay = ena_i;\n wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB;\n wire [0:0] #COLL_DELAY web_delay = web_i;\n wire #COLL_DELAY enb_delay = enb_i;\n\n // Do the checks w/rt A\n always @(posedge CLKA) begin\n // Possible collision if both are enabled and the addresses match\n if (ena_i && enb_i) begin\n if (wea_i || web_i) begin\n is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);\n end else begin\n is_collision_a = 0;\n end\n end else begin\n is_collision_a = 0;\n end\n\n if (ena_i && enb_delay) begin\n if(wea_i || web_delay) begin\n is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,\n web_delay);\n end else begin\n is_collision_delay_a = 0;\n end\n end else begin\n is_collision_delay_a = 0;\n end\n\n // Only flag if B access is a write\n if (is_collision_a && web_i) begin\n $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n C_CORENAME, $time);\n $fwrite(COLLFILE, \"A %0s address: %0h, B write address: %0h\\n\",\n wea_i ? \"write\" : \"read\", ADDRA, ADDRB);\n\n end else if (is_collision_delay_a && web_delay) begin\n $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n C_CORENAME, $time);\n $fwrite(COLLFILE, \"A %0s address: %0h, B write address: %0h\\n\",\n wea_i ? \"write\" : \"read\", ADDRA, addrb_delay);\n end\n\n end\n\n // Do the checks w/rt B\n always @(posedge CLKB) begin\n\n // Possible collision if both are enabled and the addresses match\n if (ena_i && enb_i) begin\n if (wea_i || web_i) begin\n is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);\n end else begin\n is_collision_b = 0;\n end\n end else begin\n is_collision_b = 0;\n end\n\n if (ena_delay && enb_i) begin\n if (wea_delay || web_i) begin\n is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,\n web_i);\n end else begin\n is_collision_delay_b = 0;\n end\n end else begin\n is_collision_delay_b = 0;\n end\n\n\n // Only flag if A access is a write\n if (is_collision_b && wea_i) begin\n $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n C_CORENAME, $time);\n $fwrite(COLLFILE, \"A write address: %0h, B %s address: %0h\\n\",\n ADDRA, web_i ? \"write\" : \"read\", ADDRB);\n\n end else if (is_collision_delay_b && wea_delay) begin\n $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n C_CORENAME, $time);\n $fwrite(COLLFILE, \"A write address: %0h, B %s address: %0h\\n\",\n addra_delay, web_i ? \"write\" : \"read\", ADDRB);\n end\n\n end\n end\n endgenerate\n\nendmodule\n//*****************************************************************************\n// Top module wraps Input register and Memory module\n//\n// This module is the top-level behavioral model and this implements the memory \n// module and the input registers\n//*****************************************************************************\nmodule blk_mem_gen_v8_3_4\n #(parameter C_CORENAME = \"blk_mem_gen_v8_3_4\",\n parameter C_FAMILY = \"virtex7\",\n parameter C_XDEVICEFAMILY = \"virtex7\",\n parameter C_ELABORATION_DIR = \"\",\n parameter C_INTERFACE_TYPE = 0,\n parameter C_USE_BRAM_BLOCK = 0,\n parameter C_CTRL_ECC_ALGO = \"NONE\",\n parameter C_ENABLE_32BIT_ADDRESS = 0,\n parameter C_AXI_TYPE = 0,\n parameter C_AXI_SLAVE_TYPE = 0,\n parameter C_HAS_AXI_ID = 0,\n parameter C_AXI_ID_WIDTH = 4,\n parameter C_MEM_TYPE = 2,\n parameter C_BYTE_SIZE = 9,\n parameter C_ALGORITHM = 1,\n parameter C_PRIM_TYPE = 3,\n parameter C_LOAD_INIT_FILE = 0,\n parameter C_INIT_FILE_NAME = \"\",\n parameter C_INIT_FILE = \"\",\n parameter C_USE_DEFAULT_DATA = 0,\n parameter C_DEFAULT_DATA = \"0\",\n //parameter C_RST_TYPE = \"SYNC\",\n parameter C_HAS_RSTA = 0,\n parameter C_RST_PRIORITY_A = \"CE\",\n parameter C_RSTRAM_A = 0,\n parameter C_INITA_VAL = \"0\",\n parameter C_HAS_ENA = 1,\n parameter C_HAS_REGCEA = 0,\n parameter C_USE_BYTE_WEA = 0,\n parameter C_WEA_WIDTH = 1,\n parameter C_WRITE_MODE_A = \"WRITE_FIRST\",\n parameter C_WRITE_WIDTH_A = 32,\n parameter C_READ_WIDTH_A = 32,\n parameter C_WRITE_DEPTH_A = 64,\n parameter C_READ_DEPTH_A = 64,\n parameter C_ADDRA_WIDTH = 5,\n parameter C_HAS_RSTB = 0,\n parameter C_RST_PRIORITY_B = \"CE\",\n parameter C_RSTRAM_B = 0,\n parameter C_INITB_VAL = \"\",\n parameter C_HAS_ENB = 1,\n parameter C_HAS_REGCEB = 0,\n parameter C_USE_BYTE_WEB = 0,\n parameter C_WEB_WIDTH = 1,\n parameter C_WRITE_MODE_B = \"WRITE_FIRST\",\n parameter C_WRITE_WIDTH_B = 32,\n parameter C_READ_WIDTH_B = 32,\n parameter C_WRITE_DEPTH_B = 64,\n parameter C_READ_DEPTH_B = 64,\n parameter C_ADDRB_WIDTH = 5,\n parameter C_HAS_MEM_OUTPUT_REGS_A = 0,\n parameter C_HAS_MEM_OUTPUT_REGS_B = 0,\n parameter C_HAS_MUX_OUTPUT_REGS_A = 0,\n parameter C_HAS_MUX_OUTPUT_REGS_B = 0,\n parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n parameter C_MUX_PIPELINE_STAGES = 0,\n parameter C_USE_SOFTECC = 0,\n parameter C_USE_ECC = 0,\n\tparameter C_EN_ECC_PIPE = 0,\n parameter C_HAS_INJECTERR = 0,\n parameter C_SIM_COLLISION_CHECK = \"NONE\",\n parameter C_COMMON_CLK = 1,\n parameter C_DISABLE_WARN_BHV_COLL = 0,\n\tparameter C_EN_SLEEP_PIN = 0,\n parameter C_USE_URAM = 0,\n parameter C_EN_RDADDRA_CHG = 0,\n parameter C_EN_RDADDRB_CHG = 0,\n parameter C_EN_DEEPSLEEP_PIN = 0,\n parameter C_EN_SHUTDOWN_PIN = 0,\n\tparameter C_EN_SAFETY_CKT = 0,\n\tparameter C_COUNT_36K_BRAM = \"\",\n\tparameter C_COUNT_18K_BRAM = \"\",\n\tparameter C_EST_POWER_SUMMARY = \"\",\n\tparameter C_DISABLE_WARN_BHV_RANGE = 0\n\t\n )\n (input clka,\n input rsta,\n input ena,\n input regcea,\n input [C_WEA_WIDTH-1:0] wea,\n input [C_ADDRA_WIDTH-1:0] addra,\n input [C_WRITE_WIDTH_A-1:0] dina,\n output [C_READ_WIDTH_A-1:0] douta,\n input clkb,\n input rstb,\n input enb,\n input regceb,\n input [C_WEB_WIDTH-1:0] web,\n input [C_ADDRB_WIDTH-1:0] addrb,\n input [C_WRITE_WIDTH_B-1:0] dinb,\n output [C_READ_WIDTH_B-1:0] doutb,\n input injectsbiterr,\n input injectdbiterr,\n output sbiterr,\n output dbiterr,\n output [C_ADDRB_WIDTH-1:0] rdaddrecc,\n input eccpipece,\n input sleep,\n input deepsleep,\n input shutdown,\n output rsta_busy, \n output rstb_busy, \n //AXI BMG Input and Output Port Declarations\n \n //AXI Global Signals\n input s_aclk,\n input s_aresetn,\n \n //AXI Full/lite slave write (write side)\n input [C_AXI_ID_WIDTH-1:0] s_axi_awid,\n input [31:0] s_axi_awaddr,\n input [7:0] s_axi_awlen,\n input [2:0] s_axi_awsize,\n input [1:0] s_axi_awburst,\n input s_axi_awvalid,\n output s_axi_awready,\n input [C_WRITE_WIDTH_A-1:0] s_axi_wdata,\n input [C_WEA_WIDTH-1:0] s_axi_wstrb,\n input s_axi_wlast,\n input s_axi_wvalid,\n output s_axi_wready,\n output [C_AXI_ID_WIDTH-1:0] s_axi_bid,\n output [1:0] s_axi_bresp,\n output s_axi_bvalid,\n input s_axi_bready,\n \n //AXI Full/lite slave read (write side)\n input [C_AXI_ID_WIDTH-1:0] s_axi_arid,\n input [31:0] s_axi_araddr,\n input [7:0] s_axi_arlen,\n input [2:0] s_axi_arsize,\n input [1:0] s_axi_arburst,\n input s_axi_arvalid,\n output s_axi_arready,\n output [C_AXI_ID_WIDTH-1:0] s_axi_rid,\n output [C_WRITE_WIDTH_B-1:0] s_axi_rdata,\n output [1:0] s_axi_rresp,\n output s_axi_rlast,\n output s_axi_rvalid,\n input s_axi_rready,\n \n //AXI Full/lite sideband signals\n input s_axi_injectsbiterr,\n input s_axi_injectdbiterr,\n output s_axi_sbiterr,\n output s_axi_dbiterr,\n output [C_ADDRB_WIDTH-1:0] s_axi_rdaddrecc \n \n );\n//******************************\n// Port and Generic Definitions\n//******************************\n //////////////////////////////////////////////////////////////////////////\n // Generic Definitions\n //////////////////////////////////////////////////////////////////////////\n // C_CORENAME : Instance name of the Block Memory Generator core\n // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n // options are available - \"spartan3\", \"spartan6\", \n // \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n // C_MEM_TYPE : Designates memory type.\n // It can be\n // 0 - Single Port Memory\n // 1 - Simple Dual Port Memory\n // 2 - True Dual Port Memory\n // 3 - Single Port Read Only Memory\n // 4 - Dual Port Read Only Memory\n // C_BYTE_SIZE : Size of a byte (8 or 9 bits)\n // C_ALGORITHM : Designates the algorithm method used\n // for constructing the memory.\n // It can be Fixed_Primitives, Minimum_Area or \n // Low_Power\n // C_PRIM_TYPE : Designates the user selected primitive used to \n // construct the memory.\n //\n // C_LOAD_INIT_FILE : Designates the use of an initialization file to\n // initialize memory contents.\n // C_INIT_FILE_NAME : Memory initialization file name.\n // C_USE_DEFAULT_DATA : Designates whether to fill remaining\n // initialization space with default data\n // C_DEFAULT_DATA : Default value of all memory locations\n // not initialized by the memory\n // initialization file.\n // C_RST_TYPE : Type of reset - Synchronous or Asynchronous\n // C_HAS_RSTA : Determines the presence of the RSTA port\n // C_RST_PRIORITY_A : Determines the priority between CE and SR for \n // Port A.\n // C_RSTRAM_A : Determines if special reset behavior is used for\n // Port A\n // C_INITA_VAL : The initialization value for Port A\n // C_HAS_ENA : Determines the presence of the ENA port\n // C_HAS_REGCEA : Determines the presence of the REGCEA port\n // C_USE_BYTE_WEA : Determines if the Byte Write is used or not.\n // C_WEA_WIDTH : The width of the WEA port\n // C_WRITE_MODE_A : Configurable write mode for Port A. It can be\n // WRITE_FIRST, READ_FIRST or NO_CHANGE.\n // C_WRITE_WIDTH_A : Memory write width for Port A.\n // C_READ_WIDTH_A : Memory read width for Port A.\n // C_WRITE_DEPTH_A : Memory write depth for Port A.\n // C_READ_DEPTH_A : Memory read depth for Port A.\n // C_ADDRA_WIDTH : Width of the ADDRA input port\n // C_HAS_RSTB : Determines the presence of the RSTB port\n // C_RST_PRIORITY_B : Determines the priority between CE and SR for \n // Port B.\n // C_RSTRAM_B : Determines if special reset behavior is used for\n // Port B\n // C_INITB_VAL : The initialization value for Port B\n // C_HAS_ENB : Determines the presence of the ENB port\n // C_HAS_REGCEB : Determines the presence of the REGCEB port\n // C_USE_BYTE_WEB : Determines if the Byte Write is used or not.\n // C_WEB_WIDTH : The width of the WEB port\n // C_WRITE_MODE_B : Configurable write mode for Port B. It can be\n // WRITE_FIRST, READ_FIRST or NO_CHANGE.\n // C_WRITE_WIDTH_B : Memory write width for Port B.\n // C_READ_WIDTH_B : Memory read width for Port B.\n // C_WRITE_DEPTH_B : Memory write depth for Port B.\n // C_READ_DEPTH_B : Memory read depth for Port B.\n // C_ADDRB_WIDTH : Width of the ADDRB input port\n // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n // of the RAM primitive for Port A.\n // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n // of the RAM primitive for Port B.\n // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n // of the MUX for Port A.\n // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n // of the MUX for Port B.\n // C_HAS_SOFTECC_INPUT_REGS_A : \n // C_HAS_SOFTECC_OUTPUT_REGS_B : \n // C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in \n // between the muxes.\n // C_USE_SOFTECC : Determines if the Soft ECC feature is used or\n // not. Only applicable Spartan-6\n // C_USE_ECC : Determines if the ECC feature is used or\n // not. Only applicable for V5 and V6\n // C_HAS_INJECTERR : Determines if the error injection pins\n // are present or not. If the ECC feature\n // is not used, this value is defaulted to\n // 0, else the following are the allowed \n // values:\n // 0 : No INJECTSBITERR or INJECTDBITERR pins\n // 1 : Only INJECTSBITERR pin exists\n // 2 : Only INJECTDBITERR pin exists\n // 3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n // C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision\n // warnings. It can be \"ALL\", \"NONE\", \n // \"Warnings_Only\" or \"Generate_X_Only\".\n // C_COMMON_CLK : Determins if the core has a single CLK input.\n // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n // warnings\n //////////////////////////////////////////////////////////////////////////\n // Port Definitions\n //////////////////////////////////////////////////////////////////////////\n // CLKA : Clock to synchronize all read and write operations of Port A.\n // RSTA : Reset input to reset memory outputs to a user-defined \n // reset state for Port A.\n // ENA : Enable all read and write operations of Port A.\n // REGCEA : Register Clock Enable to control each pipeline output\n // register stages for Port A.\n // WEA : Write Enable to enable all write operations of Port A.\n // ADDRA : Address of Port A.\n // DINA : Data input of Port A.\n // DOUTA : Data output of Port A.\n // CLKB : Clock to synchronize all read and write operations of Port B.\n // RSTB : Reset input to reset memory outputs to a user-defined \n // reset state for Port B.\n // ENB : Enable all read and write operations of Port B.\n // REGCEB : Register Clock Enable to control each pipeline output\n // register stages for Port B.\n // WEB : Write Enable to enable all write operations of Port B.\n // ADDRB : Address of Port B.\n // DINB : Data input of Port B.\n // DOUTB : Data output of Port B.\n // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n // SBITERR : Output signal indicating that a Single Bit ECC Error has been\n // detected and corrected.\n // DBITERR : Output signal indicating that a Double Bit ECC Error has been\n // detected.\n // RDADDRECC : Read Address Output signal indicating address at which an\n // ECC error has occurred.\n //////////////////////////////////////////////////////////////////////////\n\n wire SBITERR;\n wire DBITERR;\n wire S_AXI_AWREADY;\n wire S_AXI_WREADY;\n wire S_AXI_BVALID;\n wire S_AXI_ARREADY;\n wire S_AXI_RLAST;\n wire S_AXI_RVALID;\n wire S_AXI_SBITERR;\n wire S_AXI_DBITERR;\n\n wire [C_WEA_WIDTH-1:0] WEA = wea;\n wire [C_ADDRA_WIDTH-1:0] ADDRA = addra;\n wire [C_WRITE_WIDTH_A-1:0] DINA = dina;\n wire [C_READ_WIDTH_A-1:0] DOUTA;\n wire [C_WEB_WIDTH-1:0] WEB = web;\n wire [C_ADDRB_WIDTH-1:0] ADDRB = addrb;\n wire [C_WRITE_WIDTH_B-1:0] DINB = dinb;\n wire [C_READ_WIDTH_B-1:0] DOUTB;\n wire [C_ADDRB_WIDTH-1:0] RDADDRECC;\n wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID = s_axi_awid;\n wire [31:0] S_AXI_AWADDR = s_axi_awaddr;\n wire [7:0] S_AXI_AWLEN = s_axi_awlen;\n wire [2:0] S_AXI_AWSIZE = s_axi_awsize;\n wire [1:0] S_AXI_AWBURST = s_axi_awburst;\n wire [C_WRITE_WIDTH_A-1:0] S_AXI_WDATA = s_axi_wdata;\n wire [C_WEA_WIDTH-1:0] S_AXI_WSTRB = s_axi_wstrb;\n wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;\n wire [1:0] S_AXI_BRESP;\n wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID = s_axi_arid;\n wire [31:0] S_AXI_ARADDR = s_axi_araddr;\n wire [7:0] S_AXI_ARLEN = s_axi_arlen;\n wire [2:0] S_AXI_ARSIZE = s_axi_arsize;\n wire [1:0] S_AXI_ARBURST = s_axi_arburst;\n wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;\n wire [C_WRITE_WIDTH_B-1:0] S_AXI_RDATA;\n wire [1:0] S_AXI_RRESP;\n wire [C_ADDRB_WIDTH-1:0] S_AXI_RDADDRECC;\n // Added to fix the simulation warning #CR731605\n wire [C_WEB_WIDTH-1:0] WEB_parameterized = 0;\n wire ECCPIPECE;\n wire SLEEP;\n reg RSTA_BUSY = 0;\n reg RSTB_BUSY = 0;\n // Declaration of internal signals to avoid warnings #927399\n wire CLKA;\n wire RSTA;\n wire ENA;\n wire REGCEA;\n wire CLKB;\n wire RSTB;\n wire ENB;\n wire REGCEB;\n wire INJECTSBITERR;\n wire INJECTDBITERR;\n wire S_ACLK;\n wire S_ARESETN;\n wire S_AXI_AWVALID;\n wire S_AXI_WLAST;\n wire S_AXI_WVALID;\n wire S_AXI_BREADY;\n wire S_AXI_ARVALID;\n wire S_AXI_RREADY;\n wire S_AXI_INJECTSBITERR;\n wire S_AXI_INJECTDBITERR;\n\n assign CLKA = clka;\n assign RSTA = rsta;\n assign ENA = ena;\n assign REGCEA = regcea;\n assign CLKB = clkb;\n assign RSTB = rstb;\n assign ENB = enb;\n assign REGCEB = regceb;\n assign INJECTSBITERR = injectsbiterr;\n assign INJECTDBITERR = injectdbiterr;\n assign ECCPIPECE = eccpipece;\n assign SLEEP = sleep;\n assign sbiterr = SBITERR;\n assign dbiterr = DBITERR;\n assign S_ACLK = s_aclk;\n assign S_ARESETN = s_aresetn;\n assign S_AXI_AWVALID = s_axi_awvalid;\n assign s_axi_awready = S_AXI_AWREADY;\n assign S_AXI_WLAST = s_axi_wlast;\n assign S_AXI_WVALID = s_axi_wvalid;\n assign s_axi_wready = S_AXI_WREADY;\n assign s_axi_bvalid = S_AXI_BVALID;\n assign S_AXI_BREADY = s_axi_bready;\n assign S_AXI_ARVALID = s_axi_arvalid;\n assign s_axi_arready = S_AXI_ARREADY;\n assign s_axi_rlast = S_AXI_RLAST;\n assign s_axi_rvalid = S_AXI_RVALID;\n assign S_AXI_RREADY = s_axi_rready;\n assign S_AXI_INJECTSBITERR = s_axi_injectsbiterr;\n assign S_AXI_INJECTDBITERR = s_axi_injectdbiterr;\n assign s_axi_sbiterr = S_AXI_SBITERR;\n assign s_axi_dbiterr = S_AXI_DBITERR;\n\n assign rsta_busy = RSTA_BUSY;\n assign rstb_busy = RSTB_BUSY;\n\n assign doutb = DOUTB;\n assign douta = DOUTA;\n assign rdaddrecc = RDADDRECC;\n assign s_axi_bid = S_AXI_BID;\n assign s_axi_bresp = S_AXI_BRESP;\n assign s_axi_rid = S_AXI_RID;\n assign s_axi_rdata = S_AXI_RDATA;\n assign s_axi_rresp = S_AXI_RRESP;\n assign s_axi_rdaddrecc = S_AXI_RDADDRECC;\n\n localparam FLOP_DELAY = 100; // 100 ps\n\n reg injectsbiterr_in;\n reg injectdbiterr_in;\n reg rsta_in;\n reg ena_in;\n reg regcea_in;\n reg [C_WEA_WIDTH-1:0] wea_in;\n reg [C_ADDRA_WIDTH-1:0] addra_in;\n reg [C_WRITE_WIDTH_A-1:0] dina_in;\n\n wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;\n wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;\n wire s_axi_wr_en_c;\n wire s_axi_rd_en_c;\n wire s_aresetn_a_c;\n wire [7:0] s_axi_arlen_c ;\n\n\n wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;\n wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;\n wire [1:0] s_axi_rresp_c;\n wire s_axi_rlast_c;\n wire s_axi_rvalid_c;\n wire s_axi_rready_c;\n wire regceb_c;\n\n localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;\n wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;\n wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;\n\n// Safety logic related signals\n\n reg [4:0] RSTA_SHFT_REG = 0;\n reg POR_A = 0; \n reg [4:0] RSTB_SHFT_REG = 0;\n reg POR_B = 0;\n \n reg ENA_dly = 0;\n reg ENA_dly_D = 0;\n\n reg ENB_dly = 0;\n reg ENB_dly_D = 0;\n\n wire RSTA_I_SAFE;\n wire RSTB_I_SAFE;\n\n wire ENA_I_SAFE;\n wire ENB_I_SAFE;\n \n reg ram_rstram_a_busy = 0;\n reg ram_rstreg_a_busy = 0;\n reg ram_rstram_b_busy = 0;\n reg ram_rstreg_b_busy = 0;\n\n reg ENA_dly_reg = 0;\n reg ENB_dly_reg = 0;\n \n reg ENA_dly_reg_D = 0;\n reg ENB_dly_reg_D = 0;\n\n //**************\n // log2roundup\n //**************\n function integer log2roundup (input integer data_value);\n integer width;\n integer cnt;\n begin\n width = 0;\n\n if (data_value > 1) begin\n for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n width = width + 1;\n end //loop\n end //if\n\n log2roundup = width;\n\n end //log2roundup\n endfunction\n\n //**************\n // log2int\n //**************\n function integer log2int (input integer data_value);\n integer width;\n integer cnt;\n begin\n width = 0;\n\t\t cnt= data_value;\n\n for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin\n width = width + 1;\n end //loop\n\n log2int = width;\n\n end //log2int\n endfunction\n\n //**************************************************************************\n // FUNCTION : divroundup\n // Returns the ceiling value of the division\n // Data_value - the quantity to be divided, dividend\n // Divisor - the value to divide the data_value by\n //**************************************************************************\n function integer divroundup (input integer data_value,input integer divisor);\n integer div;\n begin\n div = data_value/divisor;\n if ((data_value % divisor) != 0) begin\n div = div+1;\n end //if\n divroundup = div;\n end //if\n endfunction\n\n localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);\n localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);\n localparam C_AXI_ADDR_WIDTH = C_AXI_ADDR_WIDTH_MSB;\n \n //Data Width Number of LSB address bits to be discarded\n //1 to 16 1\n //17 to 32 2\n //33 to 64 3\n //65 to 128 4\n //129 to 256 5\n //257 to 512 6\n //513 to 1024 7\n // The following two constants determine this.\n\n localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));\n localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);\n localparam C_AXI_OS_WR = 2;\n\n //***********************************************\n // INPUT REGISTERS.\n //***********************************************\n generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage\n always @* begin\n injectsbiterr_in = INJECTSBITERR;\n injectdbiterr_in = INJECTDBITERR;\n rsta_in = RSTA;\n ena_in = ENA;\n regcea_in = REGCEA;\n wea_in = WEA;\n addra_in = ADDRA;\n dina_in = DINA;\n end //end always\n end //end no_softecc_input_reg_stage\n endgenerate\n\n generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage\n always @(posedge CLKA) begin\n injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;\n injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;\n rsta_in <= #FLOP_DELAY RSTA;\n ena_in <= #FLOP_DELAY ENA;\n regcea_in <= #FLOP_DELAY REGCEA;\n wea_in <= #FLOP_DELAY WEA;\n addra_in <= #FLOP_DELAY ADDRA;\n dina_in <= #FLOP_DELAY DINA;\n end //end always\n end //end input_reg_stages generate statement\n endgenerate\n\n //**************************************************************************\n // NO SAFETY LOGIC\n //**************************************************************************\n\n generate \n if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN\n assign ENA_I_SAFE = ena_in;\n assign ENB_I_SAFE = ENB;\n assign RSTA_I_SAFE = rsta_in;\n assign RSTB_I_SAFE = RSTB;\n end\n endgenerate\n\n //***************************************************************************\n // SAFETY LOGIC\n // Power-ON Reset Generation\n //***************************************************************************\n generate \n if (C_EN_SAFETY_CKT == 1) begin\n always @(posedge clka) RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;\n always @(posedge clka) POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];\n always @(posedge clkb) RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;\n always @(posedge clkb) POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; \n \n assign RSTA_I_SAFE = rsta_in | POR_A; \n assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);\n end\n endgenerate\n\n //-----------------------------------------------------------------------------\n // -- RSTA/B_BUSY Generation\n //-----------------------------------------------------------------------------\n\n generate \n if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG\n always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;\n always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;\n end\n endgenerate\n \n generate \n if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG\n always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;\n always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;\n end\n endgenerate\n\n generate \n if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY\n always @(*) RSTB_BUSY = 1'b0;\n end\n endgenerate\n\n generate \n if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_NO_REG\n always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;\n always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;\n end\n endgenerate\n \n generate \n if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG \n always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;\n always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;\n end\n endgenerate\n\n //-----------------------------------------------------------------------------\n // -- ENA/ENB Generation\n //-----------------------------------------------------------------------------\n \n generate \n if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG \n always @(posedge clka) begin\n ENA_dly <= #FLOP_DELAY RSTA_I_SAFE;\n ENA_dly_D <= #FLOP_DELAY ENA_dly;\n end\n assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);\n end\n endgenerate\n\n generate \n if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG\n always @(posedge clka) begin\n ENA_dly_reg <= #FLOP_DELAY RSTA_I_SAFE;\n ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;\n end\n assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);\n end\n endgenerate\n\n generate \n if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB\n assign ENB_I_SAFE = 1'b0;\n end\n endgenerate\n\n generate \n if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG\n always @(posedge clkb) begin : PROC_ENB_GEN\n ENB_dly <= #FLOP_DELAY RSTB_I_SAFE;\n ENB_dly_D <= #FLOP_DELAY ENB_dly;\n end\n assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);\n end\n endgenerate\n \n generate \n if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG\n always @(posedge clkb) begin : PROC_ENB_GEN\n ENB_dly_reg <= #FLOP_DELAY RSTB_I_SAFE;\n ENB_dly_reg_D <= #FLOP_DELAY ENB_dly_reg;\n end\n assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);\n end\n endgenerate\n\n generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module\nblk_mem_gen_v8_3_4_mem_module\n #(.C_CORENAME (C_CORENAME),\n .C_FAMILY (C_FAMILY),\n .C_XDEVICEFAMILY (C_XDEVICEFAMILY),\n .C_MEM_TYPE (C_MEM_TYPE),\n .C_BYTE_SIZE (C_BYTE_SIZE),\n .C_ALGORITHM (C_ALGORITHM),\n .C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),\n .C_PRIM_TYPE (C_PRIM_TYPE),\n .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),\n .C_INIT_FILE_NAME (C_INIT_FILE_NAME),\n .C_INIT_FILE (C_INIT_FILE),\n .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),\n .C_DEFAULT_DATA (C_DEFAULT_DATA),\n .C_RST_TYPE (\"SYNC\"),\n .C_HAS_RSTA (C_HAS_RSTA),\n .C_RST_PRIORITY_A (C_RST_PRIORITY_A),\n .C_RSTRAM_A (C_RSTRAM_A),\n .C_INITA_VAL (C_INITA_VAL),\n .C_HAS_ENA (C_HAS_ENA),\n .C_HAS_REGCEA (C_HAS_REGCEA),\n .C_USE_BYTE_WEA (C_USE_BYTE_WEA),\n .C_WEA_WIDTH (C_WEA_WIDTH),\n .C_WRITE_MODE_A (C_WRITE_MODE_A),\n .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),\n .C_READ_WIDTH_A (C_READ_WIDTH_A),\n .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),\n .C_READ_DEPTH_A (C_READ_DEPTH_A),\n .C_ADDRA_WIDTH (C_ADDRA_WIDTH),\n .C_HAS_RSTB (C_HAS_RSTB),\n .C_RST_PRIORITY_B (C_RST_PRIORITY_B),\n .C_RSTRAM_B (C_RSTRAM_B),\n .C_INITB_VAL (C_INITB_VAL),\n .C_HAS_ENB (C_HAS_ENB),\n .C_HAS_REGCEB (C_HAS_REGCEB),\n .C_USE_BYTE_WEB (C_USE_BYTE_WEB),\n .C_WEB_WIDTH (C_WEB_WIDTH),\n .C_WRITE_MODE_B (C_WRITE_MODE_B),\n .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),\n .C_READ_WIDTH_B (C_READ_WIDTH_B),\n .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),\n .C_READ_DEPTH_B (C_READ_DEPTH_B),\n .C_ADDRB_WIDTH (C_ADDRB_WIDTH),\n .C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),\n .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),\n .C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),\n .C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),\n .C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),\n .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),\n .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),\n .C_USE_SOFTECC (C_USE_SOFTECC),\n .C_USE_ECC (C_USE_ECC),\n .C_HAS_INJECTERR (C_HAS_INJECTERR),\n .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),\n .C_COMMON_CLK (C_COMMON_CLK),\n .FLOP_DELAY (FLOP_DELAY),\n .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE (C_EN_ECC_PIPE),\n .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))\n blk_mem_gen_v8_3_4_inst\n (.CLKA (CLKA),\n .RSTA (RSTA_I_SAFE),//(rsta_in),\n .ENA (ENA_I_SAFE),//(ena_in),\n .REGCEA (regcea_in),\n .WEA (wea_in),\n .ADDRA (addra_in),\n .DINA (dina_in),\n .DOUTA (DOUTA),\n .CLKB (CLKB),\n .RSTB (RSTB_I_SAFE),//(RSTB),\n .ENB (ENB_I_SAFE),//(ENB),\n .REGCEB (REGCEB),\n .WEB (WEB),\n .ADDRB (ADDRB),\n .DINB (DINB),\n .DOUTB (DOUTB),\n .INJECTSBITERR (injectsbiterr_in),\n .INJECTDBITERR (injectdbiterr_in),\n .ECCPIPECE (ECCPIPECE),\n .SLEEP (SLEEP),\n .SBITERR (SBITERR),\n .DBITERR (DBITERR),\n .RDADDRECC (RDADDRECC)\n );\n end\n endgenerate\n\n generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module\n\n localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);\n localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);\n\n localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);\n localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);\n // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);\n // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);\n localparam C_MEM_MAP_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_MSB;\n localparam C_MEM_MAP_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_MSB;\n\n // Data Width Number of LSB address bits to be discarded\n // 1 to 16 1\n // 17 to 32 2\n // 33 to 64 3\n // 65 to 128 4\n // 129 to 256 5\n // 257 to 512 6\n // 513 to 1024 7\n // The following two constants determine this.\n\n localparam MEM_MAP_LOWER_BOUND_VAL_A = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));\n localparam MEM_MAP_LOWER_BOUND_VAL_B = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));\n localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;\n localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;\n\n wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;\n wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;\n wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;\n \n assign msb_zero_i = 0;\n assign lsb_zero_i = 0;\n assign RDADDRECC = {msb_zero_i,rdaddrecc_i,lsb_zero_i};\n\nblk_mem_gen_v8_3_4_mem_module\n #(.C_CORENAME (C_CORENAME),\n .C_FAMILY (C_FAMILY),\n .C_XDEVICEFAMILY (C_XDEVICEFAMILY),\n .C_MEM_TYPE (C_MEM_TYPE),\n .C_BYTE_SIZE (C_BYTE_SIZE),\n .C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),\n .C_ALGORITHM (C_ALGORITHM),\n .C_PRIM_TYPE (C_PRIM_TYPE),\n .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),\n .C_INIT_FILE_NAME (C_INIT_FILE_NAME),\n .C_INIT_FILE (C_INIT_FILE),\n .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),\n .C_DEFAULT_DATA (C_DEFAULT_DATA),\n .C_RST_TYPE (\"SYNC\"),\n .C_HAS_RSTA (C_HAS_RSTA),\n .C_RST_PRIORITY_A (C_RST_PRIORITY_A),\n .C_RSTRAM_A (C_RSTRAM_A),\n .C_INITA_VAL (C_INITA_VAL),\n .C_HAS_ENA (C_HAS_ENA),\n .C_HAS_REGCEA (C_HAS_REGCEA),\n .C_USE_BYTE_WEA (C_USE_BYTE_WEA),\n .C_WEA_WIDTH (C_WEA_WIDTH),\n .C_WRITE_MODE_A (C_WRITE_MODE_A),\n .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),\n .C_READ_WIDTH_A (C_READ_WIDTH_A),\n .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),\n .C_READ_DEPTH_A (C_READ_DEPTH_A),\n .C_ADDRA_WIDTH (C_ADDRA_WIDTH_ACTUAL),\n .C_HAS_RSTB (C_HAS_RSTB),\n .C_RST_PRIORITY_B (C_RST_PRIORITY_B),\n .C_RSTRAM_B (C_RSTRAM_B),\n .C_INITB_VAL (C_INITB_VAL),\n .C_HAS_ENB (C_HAS_ENB),\n .C_HAS_REGCEB (C_HAS_REGCEB),\n .C_USE_BYTE_WEB (C_USE_BYTE_WEB),\n .C_WEB_WIDTH (C_WEB_WIDTH),\n .C_WRITE_MODE_B (C_WRITE_MODE_B),\n .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),\n .C_READ_WIDTH_B (C_READ_WIDTH_B),\n .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),\n .C_READ_DEPTH_B (C_READ_DEPTH_B),\n .C_ADDRB_WIDTH (C_ADDRB_WIDTH_ACTUAL),\n .C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),\n .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),\n .C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),\n .C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),\n .C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),\n .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),\n .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),\n .C_USE_SOFTECC (C_USE_SOFTECC),\n .C_USE_ECC (C_USE_ECC),\n .C_HAS_INJECTERR (C_HAS_INJECTERR),\n .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),\n .C_COMMON_CLK (C_COMMON_CLK),\n .FLOP_DELAY (FLOP_DELAY),\n .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE (C_EN_ECC_PIPE),\n .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))\n blk_mem_gen_v8_3_4_inst\n (.CLKA (CLKA),\n .RSTA (RSTA_I_SAFE),//(rsta_in),\n .ENA (ENA_I_SAFE),//(ena_in),\n .REGCEA (regcea_in),\n .WEA (wea_in),\n .ADDRA (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),\n .DINA (dina_in),\n .DOUTA (DOUTA),\n .CLKB (CLKB),\n .RSTB (RSTB_I_SAFE),//(RSTB),\n .ENB (ENB_I_SAFE),//(ENB),\n .REGCEB (REGCEB),\n .WEB (WEB),\n .ADDRB (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),\n .DINB (DINB),\n .DOUTB (DOUTB),\n .INJECTSBITERR (injectsbiterr_in),\n .INJECTDBITERR (injectdbiterr_in),\n .ECCPIPECE (ECCPIPECE),\n .SLEEP (SLEEP),\n .SBITERR (SBITERR),\n .DBITERR (DBITERR),\n .RDADDRECC (rdaddrecc_i)\n );\n end\n endgenerate\n\n generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs\n assign S_AXI_RDATA = s_axi_rdata_c;\n assign S_AXI_RLAST = s_axi_rlast_c;\n assign S_AXI_RVALID = s_axi_rvalid_c;\n assign S_AXI_RID = s_axi_rid_c;\n assign S_AXI_RRESP = s_axi_rresp_c;\n assign s_axi_rready_c = S_AXI_RREADY;\n end\n endgenerate\n\n generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb\n assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;\n end\n endgenerate\n\n generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb\n assign regceb_c = REGCEB;\n end\n endgenerate\n\n generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs\n assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};\n assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n assign S_AXI_RDATA = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];\n assign S_AXI_RRESP = m_axi_payload_c[2:1];\n assign S_AXI_RLAST = m_axi_payload_c[0];\n end\n endgenerate\n\n generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs\n assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};\n assign S_AXI_RDATA = s_axi_rdata_c;\n assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n assign S_AXI_RRESP = m_axi_payload_c[2:1];\n assign S_AXI_RLAST = m_axi_payload_c[0];\n end\n endgenerate\n\n generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd\n\n blk_mem_axi_regs_fwd_v8_3\n #(.C_DATA_WIDTH (C_AXI_PAYLOAD))\n axi_regs_inst (\n .ACLK (S_ACLK), \n .ARESET (s_aresetn_a_c),\n .S_VALID (s_axi_rvalid_c), \n .S_READY (s_axi_rready_c),\n .S_PAYLOAD_DATA (s_axi_payload_c),\n .M_VALID (S_AXI_RVALID),\n .M_READY (S_AXI_RREADY),\n .M_PAYLOAD_DATA (m_axi_payload_c)\n );\n end\n endgenerate\n\n generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module\n\nassign s_aresetn_a_c = !S_ARESETN;\nassign S_AXI_BRESP = 2'b00;\nassign s_axi_rresp_c = 2'b00;\nassign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;\n\n blk_mem_axi_write_wrapper_beh_v8_3\n #(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),\n .C_AXI_TYPE (C_AXI_TYPE),\n .C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),\n .C_MEMORY_TYPE (C_MEM_TYPE),\n .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),\n .C_AXI_AWADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),\n .C_HAS_AXI_ID (C_HAS_AXI_ID),\n .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),\n .C_ADDRA_WIDTH (C_ADDRA_WIDTH),\n .C_AXI_WDATA_WIDTH (C_WRITE_WIDTH_A),\n .C_AXI_OS_WR (C_AXI_OS_WR))\n axi_wr_fsm (\n // AXI Global Signals\n .S_ACLK (S_ACLK),\n .S_ARESETN (s_aresetn_a_c),\n // AXI Full/Lite Slave Write interface\n .S_AXI_AWADDR (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n .S_AXI_AWLEN (S_AXI_AWLEN),\n .S_AXI_AWID (S_AXI_AWID),\n .S_AXI_AWSIZE (S_AXI_AWSIZE),\n .S_AXI_AWBURST (S_AXI_AWBURST),\n .S_AXI_AWVALID (S_AXI_AWVALID),\n .S_AXI_AWREADY (S_AXI_AWREADY),\n .S_AXI_WVALID (S_AXI_WVALID),\n .S_AXI_WREADY (S_AXI_WREADY),\n .S_AXI_BVALID (S_AXI_BVALID),\n .S_AXI_BREADY (S_AXI_BREADY),\n .S_AXI_BID (S_AXI_BID),\n // Signals for BRAM interfac(\n .S_AXI_AWADDR_OUT (s_axi_awaddr_out_c),\n .S_AXI_WR_EN (s_axi_wr_en_c)\n );\n\n blk_mem_axi_read_wrapper_beh_v8_3\n #(.C_INTERFACE_TYPE (C_INTERFACE_TYPE), \n .C_AXI_TYPE\t\t (C_AXI_TYPE), \n .C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE), \n .C_MEMORY_TYPE (C_MEM_TYPE), \n .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), \n .C_ADDRA_WIDTH (C_ADDRA_WIDTH), \n .C_AXI_PIPELINE_STAGES (1), \n .C_AXI_ARADDR_WIDTH\t ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), \n .C_HAS_AXI_ID (C_HAS_AXI_ID), \n .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), \n .C_ADDRB_WIDTH (C_ADDRB_WIDTH)) \n axi_rd_sm(\n //AXI Global Signals\n .S_ACLK (S_ACLK), \n .S_ARESETN (s_aresetn_a_c),\n //AXI Full/Lite Read Side\n .S_AXI_ARADDR (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n .S_AXI_ARLEN (s_axi_arlen_c),\n .S_AXI_ARSIZE (S_AXI_ARSIZE),\n .S_AXI_ARBURST (S_AXI_ARBURST),\n .S_AXI_ARVALID (S_AXI_ARVALID),\n .S_AXI_ARREADY (S_AXI_ARREADY),\n .S_AXI_RLAST (s_axi_rlast_c),\n .S_AXI_RVALID (s_axi_rvalid_c),\n .S_AXI_RREADY (s_axi_rready_c),\n .S_AXI_ARID (S_AXI_ARID),\n .S_AXI_RID (s_axi_rid_c),\n //AXI Full/Lite Read FSM Outputs\n .S_AXI_ARADDR_OUT (s_axi_araddr_out_c),\n .S_AXI_RD_EN (s_axi_rd_en_c)\n );\n\nblk_mem_gen_v8_3_4_mem_module\n #(.C_CORENAME (C_CORENAME),\n .C_FAMILY (C_FAMILY),\n .C_XDEVICEFAMILY (C_XDEVICEFAMILY),\n .C_MEM_TYPE (C_MEM_TYPE),\n .C_BYTE_SIZE (C_BYTE_SIZE),\n .C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),\n .C_ALGORITHM (C_ALGORITHM),\n .C_PRIM_TYPE (C_PRIM_TYPE),\n .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),\n .C_INIT_FILE_NAME (C_INIT_FILE_NAME),\n .C_INIT_FILE (C_INIT_FILE),\n .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),\n .C_DEFAULT_DATA (C_DEFAULT_DATA),\n .C_RST_TYPE (\"SYNC\"),\n .C_HAS_RSTA (C_HAS_RSTA),\n .C_RST_PRIORITY_A (C_RST_PRIORITY_A),\n .C_RSTRAM_A (C_RSTRAM_A),\n .C_INITA_VAL (C_INITA_VAL),\n .C_HAS_ENA (1),\n .C_HAS_REGCEA (C_HAS_REGCEA),\n .C_USE_BYTE_WEA (1),\n .C_WEA_WIDTH (C_WEA_WIDTH),\n .C_WRITE_MODE_A (C_WRITE_MODE_A),\n .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),\n .C_READ_WIDTH_A (C_READ_WIDTH_A),\n .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),\n .C_READ_DEPTH_A (C_READ_DEPTH_A),\n .C_ADDRA_WIDTH (C_ADDRA_WIDTH),\n .C_HAS_RSTB (C_HAS_RSTB),\n .C_RST_PRIORITY_B (C_RST_PRIORITY_B),\n .C_RSTRAM_B (C_RSTRAM_B),\n .C_INITB_VAL (C_INITB_VAL),\n .C_HAS_ENB (1),\n .C_HAS_REGCEB (C_HAS_MEM_OUTPUT_REGS_B),\n .C_USE_BYTE_WEB (1),\n .C_WEB_WIDTH (C_WEB_WIDTH),\n .C_WRITE_MODE_B (C_WRITE_MODE_B),\n .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),\n .C_READ_WIDTH_B (C_READ_WIDTH_B),\n .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),\n .C_READ_DEPTH_B (C_READ_DEPTH_B),\n .C_ADDRB_WIDTH (C_ADDRB_WIDTH),\n .C_HAS_MEM_OUTPUT_REGS_A (0),\n .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),\n .C_HAS_MUX_OUTPUT_REGS_A (0),\n .C_HAS_MUX_OUTPUT_REGS_B (0),\n .C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),\n .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),\n .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),\n .C_USE_SOFTECC (C_USE_SOFTECC),\n .C_USE_ECC (C_USE_ECC),\n .C_HAS_INJECTERR (C_HAS_INJECTERR),\n .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),\n .C_COMMON_CLK (C_COMMON_CLK),\n .FLOP_DELAY (FLOP_DELAY),\n .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),\n\t.C_EN_ECC_PIPE (0),\n .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))\n blk_mem_gen_v8_3_4_inst\n (.CLKA (S_ACLK),\n .RSTA (s_aresetn_a_c),\n .ENA (s_axi_wr_en_c),\n .REGCEA (regcea_in),\n .WEA (S_AXI_WSTRB),\n .ADDRA (s_axi_awaddr_out_c),\n .DINA (S_AXI_WDATA),\n .DOUTA (DOUTA),\n .CLKB (S_ACLK),\n .RSTB (s_aresetn_a_c),\n .ENB (s_axi_rd_en_c),\n .REGCEB (regceb_c),\n .WEB (WEB_parameterized),\n .ADDRB (s_axi_araddr_out_c),\n .DINB (DINB),\n .DOUTB (s_axi_rdata_c),\n .INJECTSBITERR (injectsbiterr_in),\n .INJECTDBITERR (injectdbiterr_in),\n .SBITERR (SBITERR),\n .DBITERR (DBITERR),\n .ECCPIPECE (1'b0),\n .SLEEP (1'b0),\n .RDADDRECC (RDADDRECC)\n );\n end\n endgenerate\nendmodule\n\n\n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/ipstatic/simulation/fifo_generator_vlog_beh.v", "content": "/*\n *******************************************************************************\n *\n * FIFO Generator - Verilog Behavioral Model\n *\n *******************************************************************************\n *\n * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.\n *\n * This file contains confidential and proprietary information\n * of Xilinx, Inc. and is protected under U.S. and\n * international copyright and other intellectual property\n * laws.\n *\n * DISCLAIMER\n * This disclaimer is not a license and does not grant any\n * rights to the materials distributed herewith. Except as\n * otherwise provided in a valid license issued to you by\n * Xilinx, and to the maximum extent permitted by applicable\n * law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n * (2) Xilinx shall not be liable (whether in contract or tort,\n * including negligence, or under any other theory of\n * liability) for any loss or damage of any kind or nature\n * related to, arising under or in connection with these\n * materials, including for any direct, or any indirect,\n * special, incidental, or consequential loss or damage\n * (including loss of data, profits, goodwill, or any type of\n * loss or damage suffered as a result of any action brought\n * by a third party) even if such damage or loss was\n * reasonably foreseeable or Xilinx had been advised of the\n * possibility of the same.\n *\n * CRITICAL APPLICATIONS\n * Xilinx products are not designed or intended to be fail-\n * safe, or for use in any application requiring fail-safe\n * performance, such as life-support or safety devices or\n * systems, Class III medical devices, nuclear facilities,\n * applications related to the deployment of airbags, or any\n * other applications that could lead to death, personal\n * injury, or severe property or environmental damage\n * (individually and collectively, \"Critical\n * Applications\"). Customer assumes the sole risk and\n * liability of any use of Xilinx products in Critical\n * Applications, subject only to applicable laws and\n * regulations governing limitations on product liability.\n *\n * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n * PART OF THIS FILE AT ALL TIMES.\n *\n *******************************************************************************\n *******************************************************************************\n *\n * Filename: fifo_generator_vlog_beh.v\n *\n * Author : Xilinx\n *\n *******************************************************************************\n * Structure:\n * \n * fifo_generator_vlog_beh.v\n * |\n * +-fifo_generator_v13_1_2_bhv_ver_as\n * |\n * +-fifo_generator_v13_1_2_bhv_ver_ss\n * |\n * +-fifo_generator_v13_1_2_bhv_ver_preload0\n * \n *******************************************************************************\n * Description:\n *\n * The Verilog behavioral model for the FIFO Generator.\n *\n * The behavioral model has three parts:\n * - The behavioral model for independent clocks FIFOs (_as)\n * - The behavioral model for common clock FIFOs (_ss)\n * - The \"preload logic\" block which implements First-word Fall-through\n * \n *******************************************************************************\n * Description:\n * The verilog behavioral model for the FIFO generator core.\n *\n *******************************************************************************\n */\n\n`timescale 1ps/1ps\n`ifndef TCQ\n `define TCQ 100\n`endif\n\n\n/*******************************************************************************\n * Declaration of top-level module\n ******************************************************************************/\nmodule fifo_generator_vlog_beh\n #(\n //-----------------------------------------------------------------------\n // Generic Declarations\n //-----------------------------------------------------------------------\n parameter C_COMMON_CLOCK = 0,\n parameter C_COUNT_TYPE = 0,\n parameter C_DATA_COUNT_WIDTH = 2,\n parameter C_DEFAULT_VALUE = \"\",\n parameter C_DIN_WIDTH = 8,\n parameter C_DOUT_RST_VAL = \"\",\n parameter C_DOUT_WIDTH = 8,\n parameter C_ENABLE_RLOCS = 0,\n parameter C_FAMILY = \"\",\n parameter C_FULL_FLAGS_RST_VAL = 1,\n parameter C_HAS_ALMOST_EMPTY = 0,\n parameter C_HAS_ALMOST_FULL = 0,\n parameter C_HAS_BACKUP = 0,\n parameter C_HAS_DATA_COUNT = 0,\n parameter C_HAS_INT_CLK = 0,\n parameter C_HAS_MEMINIT_FILE = 0,\n parameter C_HAS_OVERFLOW = 0,\n parameter C_HAS_RD_DATA_COUNT = 0,\n parameter C_HAS_RD_RST = 0,\n parameter C_HAS_RST = 1,\n parameter C_HAS_SRST = 0,\n parameter C_HAS_UNDERFLOW = 0,\n parameter C_HAS_VALID = 0,\n parameter C_HAS_WR_ACK = 0,\n parameter C_HAS_WR_DATA_COUNT = 0,\n parameter C_HAS_WR_RST = 0,\n parameter C_IMPLEMENTATION_TYPE = 0,\n parameter C_INIT_WR_PNTR_VAL = 0,\n parameter C_MEMORY_TYPE = 1,\n parameter C_MIF_FILE_NAME = \"\",\n parameter C_OPTIMIZATION_MODE = 0,\n parameter C_OVERFLOW_LOW = 0,\n parameter C_EN_SAFETY_CKT = 0,\n parameter C_PRELOAD_LATENCY = 1,\n parameter C_PRELOAD_REGS = 0,\n parameter C_PRIM_FIFO_TYPE = \"4kx4\",\n parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n parameter C_PROG_EMPTY_TYPE = 0,\n parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,\n parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,\n parameter C_PROG_FULL_TYPE = 0,\n parameter C_RD_DATA_COUNT_WIDTH = 2,\n parameter C_RD_DEPTH = 256,\n parameter C_RD_FREQ = 1,\n parameter C_RD_PNTR_WIDTH = 8,\n parameter C_UNDERFLOW_LOW = 0,\n parameter C_USE_DOUT_RST = 0,\n parameter C_USE_ECC = 0,\n parameter C_USE_EMBEDDED_REG = 0,\n parameter C_USE_PIPELINE_REG = 0,\n parameter C_POWER_SAVING_MODE = 0,\n parameter C_USE_FIFO16_FLAGS = 0,\n parameter C_USE_FWFT_DATA_COUNT = 0,\n parameter C_VALID_LOW = 0,\n parameter C_WR_ACK_LOW = 0,\n parameter C_WR_DATA_COUNT_WIDTH = 2,\n parameter C_WR_DEPTH = 256,\n parameter C_WR_FREQ = 1,\n parameter C_WR_PNTR_WIDTH = 8,\n parameter C_WR_RESPONSE_LATENCY = 1,\n parameter C_MSGON_VAL = 1,\n parameter C_ENABLE_RST_SYNC = 1,\n parameter C_ERROR_INJECTION_TYPE = 0,\n parameter C_SYNCHRONIZER_STAGE = 2,\n\n // AXI Interface related parameters start here\n parameter C_INTERFACE_TYPE = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3\n parameter C_AXI_TYPE = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3\n parameter C_HAS_AXI_WR_CHANNEL = 0,\n parameter C_HAS_AXI_RD_CHANNEL = 0,\n parameter C_HAS_SLAVE_CE = 0,\n parameter C_HAS_MASTER_CE = 0,\n parameter C_ADD_NGC_CONSTRAINT = 0,\n parameter C_USE_COMMON_UNDERFLOW = 0,\n parameter C_USE_COMMON_OVERFLOW = 0,\n parameter C_USE_DEFAULT_SETTINGS = 0,\n\n // AXI Full/Lite\n parameter C_AXI_ID_WIDTH = 0,\n parameter C_AXI_ADDR_WIDTH = 0,\n parameter C_AXI_DATA_WIDTH = 0,\n parameter C_AXI_LEN_WIDTH = 8,\n parameter C_AXI_LOCK_WIDTH = 2,\n parameter C_HAS_AXI_ID = 0,\n parameter C_HAS_AXI_AWUSER = 0,\n parameter C_HAS_AXI_WUSER = 0,\n parameter C_HAS_AXI_BUSER = 0,\n parameter C_HAS_AXI_ARUSER = 0,\n parameter C_HAS_AXI_RUSER = 0,\n parameter C_AXI_ARUSER_WIDTH = 0,\n parameter C_AXI_AWUSER_WIDTH = 0,\n parameter C_AXI_WUSER_WIDTH = 0,\n parameter C_AXI_BUSER_WIDTH = 0,\n parameter C_AXI_RUSER_WIDTH = 0,\n\n // AXI Streaming\n parameter C_HAS_AXIS_TDATA = 0,\n parameter C_HAS_AXIS_TID = 0,\n parameter C_HAS_AXIS_TDEST = 0,\n parameter C_HAS_AXIS_TUSER = 0,\n parameter C_HAS_AXIS_TREADY = 0,\n parameter C_HAS_AXIS_TLAST = 0,\n parameter C_HAS_AXIS_TSTRB = 0,\n parameter C_HAS_AXIS_TKEEP = 0,\n parameter C_AXIS_TDATA_WIDTH = 1,\n parameter C_AXIS_TID_WIDTH = 1,\n parameter C_AXIS_TDEST_WIDTH = 1,\n parameter C_AXIS_TUSER_WIDTH = 1,\n parameter C_AXIS_TSTRB_WIDTH = 1,\n parameter C_AXIS_TKEEP_WIDTH = 1,\n\n // AXI Channel Type\n // WACH --> Write Address Channel\n // WDCH --> Write Data Channel\n // WRCH --> Write Response Channel\n // RACH --> Read Address Channel\n // RDCH --> Read Data Channel\n // AXIS --> AXI Streaming\n parameter C_WACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic\n parameter C_WDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n parameter C_WRCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n parameter C_RACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n parameter C_RDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n parameter C_AXIS_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie\n\n // AXI Implementation Type\n // 1 = Common Clock Block RAM FIFO\n // 2 = Common Clock Distributed RAM FIFO\n // 11 = Independent Clock Block RAM FIFO\n // 12 = Independent Clock Distributed RAM FIFO\n parameter C_IMPLEMENTATION_TYPE_WACH = 0,\n parameter C_IMPLEMENTATION_TYPE_WDCH = 0,\n parameter C_IMPLEMENTATION_TYPE_WRCH = 0,\n parameter C_IMPLEMENTATION_TYPE_RACH = 0,\n parameter C_IMPLEMENTATION_TYPE_RDCH = 0,\n parameter C_IMPLEMENTATION_TYPE_AXIS = 0,\n\n // AXI FIFO Type\n // 0 = Data FIFO\n // 1 = Packet FIFO\n // 2 = Low Latency Sync FIFO\n // 3 = Low Latency Async FIFO\n parameter C_APPLICATION_TYPE_WACH = 0,\n parameter C_APPLICATION_TYPE_WDCH = 0,\n parameter C_APPLICATION_TYPE_WRCH = 0,\n parameter C_APPLICATION_TYPE_RACH = 0,\n parameter C_APPLICATION_TYPE_RDCH = 0,\n parameter C_APPLICATION_TYPE_AXIS = 0,\n\n // AXI Built-in FIFO Primitive Type\n // 512x36, 1kx18, 2kx9, 4kx4, etc\n parameter C_PRIM_FIFO_TYPE_WACH = \"512x36\",\n parameter C_PRIM_FIFO_TYPE_WDCH = \"512x36\",\n parameter C_PRIM_FIFO_TYPE_WRCH = \"512x36\",\n parameter C_PRIM_FIFO_TYPE_RACH = \"512x36\",\n parameter C_PRIM_FIFO_TYPE_RDCH = \"512x36\",\n parameter C_PRIM_FIFO_TYPE_AXIS = \"512x36\",\n\n // Enable ECC\n // 0 = ECC disabled\n // 1 = ECC enabled\n parameter C_USE_ECC_WACH = 0,\n parameter C_USE_ECC_WDCH = 0,\n parameter C_USE_ECC_WRCH = 0,\n parameter C_USE_ECC_RACH = 0,\n parameter C_USE_ECC_RDCH = 0,\n parameter C_USE_ECC_AXIS = 0,\n\n // ECC Error Injection Type\n // 0 = No Error Injection\n // 1 = Single Bit Error Injection\n // 2 = Double Bit Error Injection\n // 3 = Single Bit and Double Bit Error Injection\n parameter C_ERROR_INJECTION_TYPE_WACH = 0,\n parameter C_ERROR_INJECTION_TYPE_WDCH = 0,\n parameter C_ERROR_INJECTION_TYPE_WRCH = 0,\n parameter C_ERROR_INJECTION_TYPE_RACH = 0,\n parameter C_ERROR_INJECTION_TYPE_RDCH = 0,\n parameter C_ERROR_INJECTION_TYPE_AXIS = 0,\n\n // Input Data Width\n // Accumulation of all AXI input signal's width\n parameter C_DIN_WIDTH_WACH = 1,\n parameter C_DIN_WIDTH_WDCH = 1,\n parameter C_DIN_WIDTH_WRCH = 1,\n parameter C_DIN_WIDTH_RACH = 1,\n parameter C_DIN_WIDTH_RDCH = 1,\n parameter C_DIN_WIDTH_AXIS = 1,\n\n parameter C_WR_DEPTH_WACH = 16,\n parameter C_WR_DEPTH_WDCH = 16,\n parameter C_WR_DEPTH_WRCH = 16,\n parameter C_WR_DEPTH_RACH = 16,\n parameter C_WR_DEPTH_RDCH = 16,\n parameter C_WR_DEPTH_AXIS = 16,\n\n parameter C_WR_PNTR_WIDTH_WACH = 4,\n parameter C_WR_PNTR_WIDTH_WDCH = 4,\n parameter C_WR_PNTR_WIDTH_WRCH = 4,\n parameter C_WR_PNTR_WIDTH_RACH = 4,\n parameter C_WR_PNTR_WIDTH_RDCH = 4,\n parameter C_WR_PNTR_WIDTH_AXIS = 4,\n\n parameter C_HAS_DATA_COUNTS_WACH = 0,\n parameter C_HAS_DATA_COUNTS_WDCH = 0,\n parameter C_HAS_DATA_COUNTS_WRCH = 0,\n parameter C_HAS_DATA_COUNTS_RACH = 0,\n parameter C_HAS_DATA_COUNTS_RDCH = 0,\n parameter C_HAS_DATA_COUNTS_AXIS = 0,\n\n parameter C_HAS_PROG_FLAGS_WACH = 0,\n parameter C_HAS_PROG_FLAGS_WDCH = 0,\n parameter C_HAS_PROG_FLAGS_WRCH = 0,\n parameter C_HAS_PROG_FLAGS_RACH = 0,\n parameter C_HAS_PROG_FLAGS_RDCH = 0,\n parameter C_HAS_PROG_FLAGS_AXIS = 0,\n\n parameter C_PROG_FULL_TYPE_WACH = 0,\n parameter C_PROG_FULL_TYPE_WDCH = 0,\n parameter C_PROG_FULL_TYPE_WRCH = 0,\n parameter C_PROG_FULL_TYPE_RACH = 0,\n parameter C_PROG_FULL_TYPE_RDCH = 0,\n parameter C_PROG_FULL_TYPE_AXIS = 0,\n\n parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH = 0,\n parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = 0,\n parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = 0,\n parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH = 0,\n parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = 0,\n parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = 0,\n\n parameter C_PROG_EMPTY_TYPE_WACH = 0,\n parameter C_PROG_EMPTY_TYPE_WDCH = 0,\n parameter C_PROG_EMPTY_TYPE_WRCH = 0,\n parameter C_PROG_EMPTY_TYPE_RACH = 0,\n parameter C_PROG_EMPTY_TYPE_RDCH = 0,\n parameter C_PROG_EMPTY_TYPE_AXIS = 0,\n\n parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = 0,\n parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = 0,\n parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = 0,\n parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = 0,\n parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = 0,\n parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = 0,\n\n parameter C_REG_SLICE_MODE_WACH = 0,\n parameter C_REG_SLICE_MODE_WDCH = 0,\n parameter C_REG_SLICE_MODE_WRCH = 0,\n parameter C_REG_SLICE_MODE_RACH = 0,\n parameter C_REG_SLICE_MODE_RDCH = 0,\n parameter C_REG_SLICE_MODE_AXIS = 0\n\n )\n\n (\n //------------------------------------------------------------------------------\n // Input and Output Declarations\n //------------------------------------------------------------------------------\n\n // Conventional FIFO Interface Signals\n input backup,\n input backup_marker,\n input clk,\n input rst,\n input srst,\n input wr_clk,\n input wr_rst,\n input rd_clk,\n input rd_rst,\n input [C_DIN_WIDTH-1:0] din,\n input wr_en,\n input rd_en,\n // Optional inputs\n input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh,\n input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert,\n input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate,\n input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh,\n input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert,\n input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate,\n input int_clk,\n input injectdbiterr,\n input injectsbiterr,\n input sleep,\n\n output [C_DOUT_WIDTH-1:0] dout,\n output full,\n output almost_full,\n output wr_ack,\n output overflow,\n output empty,\n output almost_empty,\n output valid,\n output underflow,\n output [C_DATA_COUNT_WIDTH-1:0] data_count,\n output [C_RD_DATA_COUNT_WIDTH-1:0] rd_data_count,\n output [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count,\n output prog_full,\n output prog_empty,\n output sbiterr,\n output dbiterr,\n output wr_rst_busy,\n output rd_rst_busy,\n\n\n // AXI Global Signal\n input m_aclk,\n input s_aclk,\n input s_aresetn,\n input s_aclk_en,\n input m_aclk_en,\n \n // AXI Full/Lite Slave Write Channel (write side)\n input [C_AXI_ID_WIDTH-1:0] s_axi_awid,\n input [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,\n input [C_AXI_LEN_WIDTH-1:0] s_axi_awlen,\n input [3-1:0] s_axi_awsize,\n input [2-1:0] s_axi_awburst,\n input [C_AXI_LOCK_WIDTH-1:0] s_axi_awlock,\n input [4-1:0] s_axi_awcache,\n input [3-1:0] s_axi_awprot,\n input [4-1:0] s_axi_awqos,\n input [4-1:0] s_axi_awregion,\n input [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,\n input s_axi_awvalid,\n output s_axi_awready,\n input [C_AXI_ID_WIDTH-1:0] s_axi_wid,\n input [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,\n input [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,\n input s_axi_wlast,\n input [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,\n input s_axi_wvalid,\n output s_axi_wready,\n output [C_AXI_ID_WIDTH-1:0] s_axi_bid,\n output [2-1:0] s_axi_bresp,\n output [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,\n output s_axi_bvalid,\n input s_axi_bready,\n \n // AXI Full/Lite Master Write Channel (read side)\n output [C_AXI_ID_WIDTH-1:0] m_axi_awid,\n output [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,\n output [C_AXI_LEN_WIDTH-1:0] m_axi_awlen,\n output [3-1:0] m_axi_awsize,\n output [2-1:0] m_axi_awburst,\n output [C_AXI_LOCK_WIDTH-1:0] m_axi_awlock,\n output [4-1:0] m_axi_awcache,\n output [3-1:0] m_axi_awprot,\n output [4-1:0] m_axi_awqos,\n output [4-1:0] m_axi_awregion,\n output [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,\n output m_axi_awvalid,\n input m_axi_awready,\n output [C_AXI_ID_WIDTH-1:0] m_axi_wid,\n output [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,\n output [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,\n output m_axi_wlast,\n output [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,\n output m_axi_wvalid,\n input m_axi_wready,\n input [C_AXI_ID_WIDTH-1:0] m_axi_bid,\n input [2-1:0] m_axi_bresp,\n input [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,\n input m_axi_bvalid,\n output m_axi_bready,\n \n \n // AXI Full/Lite Slave Read Channel (write side)\n input [C_AXI_ID_WIDTH-1:0] s_axi_arid,\n input [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr, \n input [C_AXI_LEN_WIDTH-1:0] s_axi_arlen,\n input [3-1:0] s_axi_arsize,\n input [2-1:0] s_axi_arburst,\n input [C_AXI_LOCK_WIDTH-1:0] s_axi_arlock,\n input [4-1:0] s_axi_arcache,\n input [3-1:0] s_axi_arprot,\n input [4-1:0] s_axi_arqos,\n input [4-1:0] s_axi_arregion,\n input [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,\n input s_axi_arvalid,\n output s_axi_arready,\n output [C_AXI_ID_WIDTH-1:0] s_axi_rid, \n output [C_AXI_DATA_WIDTH-1:0] s_axi_rdata, \n output [2-1:0] s_axi_rresp,\n output s_axi_rlast,\n output [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,\n output s_axi_rvalid,\n input s_axi_rready,\n \n \n \n // AXI Full/Lite Master Read Channel (read side)\n output [C_AXI_ID_WIDTH-1:0] m_axi_arid, \n output [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr, \n output [C_AXI_LEN_WIDTH-1:0] m_axi_arlen,\n output [3-1:0] m_axi_arsize,\n output [2-1:0] m_axi_arburst,\n output [C_AXI_LOCK_WIDTH-1:0] m_axi_arlock,\n output [4-1:0] m_axi_arcache,\n output [3-1:0] m_axi_arprot,\n output [4-1:0] m_axi_arqos,\n output [4-1:0] m_axi_arregion,\n output [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,\n output m_axi_arvalid,\n input m_axi_arready,\n input [C_AXI_ID_WIDTH-1:0] m_axi_rid, \n input [C_AXI_DATA_WIDTH-1:0] m_axi_rdata, \n input [2-1:0] m_axi_rresp,\n input m_axi_rlast,\n input [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,\n input m_axi_rvalid,\n output m_axi_rready,\n \n \n // AXI Streaming Slave Signals (Write side)\n input s_axis_tvalid,\n output s_axis_tready,\n input [C_AXIS_TDATA_WIDTH-1:0] s_axis_tdata,\n input [C_AXIS_TSTRB_WIDTH-1:0] s_axis_tstrb,\n input [C_AXIS_TKEEP_WIDTH-1:0] s_axis_tkeep,\n input s_axis_tlast,\n input [C_AXIS_TID_WIDTH-1:0] s_axis_tid,\n input [C_AXIS_TDEST_WIDTH-1:0] s_axis_tdest,\n input [C_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,\n \n // AXI Streaming Master Signals (Read side)\n output m_axis_tvalid,\n input m_axis_tready,\n output [C_AXIS_TDATA_WIDTH-1:0] m_axis_tdata,\n output [C_AXIS_TSTRB_WIDTH-1:0] m_axis_tstrb,\n output [C_AXIS_TKEEP_WIDTH-1:0] m_axis_tkeep,\n output m_axis_tlast,\n output [C_AXIS_TID_WIDTH-1:0] m_axis_tid,\n output [C_AXIS_TDEST_WIDTH-1:0] m_axis_tdest,\n output [C_AXIS_TUSER_WIDTH-1:0] m_axis_tuser,\n \n \n \n \n // AXI Full/Lite Write Address Channel signals\n input axi_aw_injectsbiterr,\n input axi_aw_injectdbiterr,\n input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_full_thresh,\n input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_empty_thresh,\n output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_data_count,\n output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_wr_data_count,\n output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_rd_data_count,\n output axi_aw_sbiterr,\n output axi_aw_dbiterr,\n output axi_aw_overflow,\n output axi_aw_underflow,\n output axi_aw_prog_full,\n output axi_aw_prog_empty,\n \n \n // AXI Full/Lite Write Data Channel signals\n input axi_w_injectsbiterr,\n input axi_w_injectdbiterr,\n input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_full_thresh,\n input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_empty_thresh,\n output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_data_count,\n output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_wr_data_count,\n output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_rd_data_count,\n output axi_w_sbiterr,\n output axi_w_dbiterr,\n output axi_w_overflow,\n output axi_w_underflow,\n output axi_w_prog_full,\n output axi_w_prog_empty,\n \n \n // AXI Full/Lite Write Response Channel signals\n input axi_b_injectsbiterr,\n input axi_b_injectdbiterr,\n input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_full_thresh,\n input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_empty_thresh,\n output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_data_count,\n output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_wr_data_count,\n output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_rd_data_count,\n output axi_b_sbiterr,\n output axi_b_dbiterr,\n output axi_b_overflow,\n output axi_b_underflow,\n output axi_b_prog_full,\n output axi_b_prog_empty,\n \n \n \n // AXI Full/Lite Read Address Channel signals\n input axi_ar_injectsbiterr,\n input axi_ar_injectdbiterr,\n input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_full_thresh,\n input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_empty_thresh,\n output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_data_count,\n output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_wr_data_count,\n output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_rd_data_count,\n output axi_ar_sbiterr,\n output axi_ar_dbiterr,\n output axi_ar_overflow,\n output axi_ar_underflow,\n output axi_ar_prog_full,\n output axi_ar_prog_empty,\n\n \n // AXI Full/Lite Read Data Channel Signals\n input axi_r_injectsbiterr,\n input axi_r_injectdbiterr,\n input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_full_thresh,\n input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_empty_thresh,\n output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_data_count,\n output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_wr_data_count,\n output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_rd_data_count,\n output axi_r_sbiterr,\n output axi_r_dbiterr,\n output axi_r_overflow,\n output axi_r_underflow,\n output axi_r_prog_full,\n output axi_r_prog_empty,\n\n \n // AXI Streaming FIFO Related Signals\n input axis_injectsbiterr,\n input axis_injectdbiterr,\n input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_full_thresh,\n input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_empty_thresh,\n output [C_WR_PNTR_WIDTH_AXIS:0] axis_data_count,\n output [C_WR_PNTR_WIDTH_AXIS:0] axis_wr_data_count,\n output [C_WR_PNTR_WIDTH_AXIS:0] axis_rd_data_count,\n output axis_sbiterr,\n output axis_dbiterr,\n output axis_overflow,\n output axis_underflow,\n output axis_prog_full,\n output axis_prog_empty\n\n );\n\n wire BACKUP;\n wire BACKUP_MARKER;\n wire CLK;\n wire RST;\n wire SRST;\n wire WR_CLK;\n wire WR_RST;\n wire RD_CLK;\n wire RD_RST;\n wire [C_DIN_WIDTH-1:0] DIN;\n wire WR_EN;\n wire RD_EN;\n wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;\n wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;\n wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;\n wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;\n wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;\n wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;\n wire INT_CLK;\n wire INJECTDBITERR;\n wire INJECTSBITERR;\n wire SLEEP;\n wire [C_DOUT_WIDTH-1:0] DOUT;\n wire FULL;\n wire ALMOST_FULL;\n wire WR_ACK;\n wire OVERFLOW;\n wire EMPTY;\n wire ALMOST_EMPTY;\n wire VALID;\n wire UNDERFLOW;\n wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT;\n wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT;\n wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT;\n wire PROG_FULL;\n wire PROG_EMPTY;\n wire SBITERR;\n wire DBITERR;\n wire WR_RST_BUSY;\n wire RD_RST_BUSY;\n wire M_ACLK;\n wire S_ACLK;\n wire S_ARESETN;\n wire S_ACLK_EN;\n wire M_ACLK_EN;\n wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID;\n wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR;\n wire [C_AXI_LEN_WIDTH-1:0] S_AXI_AWLEN;\n wire [3-1:0] S_AXI_AWSIZE;\n wire [2-1:0] S_AXI_AWBURST;\n wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_AWLOCK;\n wire [4-1:0] S_AXI_AWCACHE;\n wire [3-1:0] S_AXI_AWPROT;\n wire [4-1:0] S_AXI_AWQOS;\n wire [4-1:0] S_AXI_AWREGION;\n wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER;\n wire S_AXI_AWVALID;\n wire S_AXI_AWREADY;\n wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID;\n wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA;\n wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB;\n wire S_AXI_WLAST;\n wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER;\n wire S_AXI_WVALID;\n wire S_AXI_WREADY;\n wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;\n wire [2-1:0] S_AXI_BRESP;\n wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER;\n wire S_AXI_BVALID;\n wire S_AXI_BREADY;\n wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID;\n wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR;\n wire [C_AXI_LEN_WIDTH-1:0] M_AXI_AWLEN;\n wire [3-1:0] M_AXI_AWSIZE;\n wire [2-1:0] M_AXI_AWBURST;\n wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_AWLOCK;\n wire [4-1:0] M_AXI_AWCACHE;\n wire [3-1:0] M_AXI_AWPROT;\n wire [4-1:0] M_AXI_AWQOS;\n wire [4-1:0] M_AXI_AWREGION;\n wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER;\n wire M_AXI_AWVALID;\n wire M_AXI_AWREADY;\n wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID;\n wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA;\n wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB;\n wire M_AXI_WLAST;\n wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER;\n wire M_AXI_WVALID;\n wire M_AXI_WREADY;\n wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID;\n wire [2-1:0] M_AXI_BRESP;\n wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER;\n wire M_AXI_BVALID;\n wire M_AXI_BREADY;\n wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID;\n wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR; \n wire [C_AXI_LEN_WIDTH-1:0] S_AXI_ARLEN;\n wire [3-1:0] S_AXI_ARSIZE;\n wire [2-1:0] S_AXI_ARBURST;\n wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_ARLOCK;\n wire [4-1:0] S_AXI_ARCACHE;\n wire [3-1:0] S_AXI_ARPROT;\n wire [4-1:0] S_AXI_ARQOS;\n wire [4-1:0] S_AXI_ARREGION;\n wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER;\n wire S_AXI_ARVALID;\n wire S_AXI_ARREADY;\n wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID; \n wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA; \n wire [2-1:0] S_AXI_RRESP;\n wire S_AXI_RLAST;\n wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER;\n wire S_AXI_RVALID;\n wire S_AXI_RREADY;\n wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID; \n wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR; \n wire [C_AXI_LEN_WIDTH-1:0] M_AXI_ARLEN;\n wire [3-1:0] M_AXI_ARSIZE;\n wire [2-1:0] M_AXI_ARBURST;\n wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_ARLOCK;\n wire [4-1:0] M_AXI_ARCACHE;\n wire [3-1:0] M_AXI_ARPROT;\n wire [4-1:0] M_AXI_ARQOS;\n wire [4-1:0] M_AXI_ARREGION;\n wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER;\n wire M_AXI_ARVALID;\n wire M_AXI_ARREADY;\n wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID; \n wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA; \n wire [2-1:0] M_AXI_RRESP;\n wire M_AXI_RLAST;\n wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER;\n wire M_AXI_RVALID;\n wire M_AXI_RREADY;\n wire S_AXIS_TVALID;\n wire S_AXIS_TREADY;\n wire [C_AXIS_TDATA_WIDTH-1:0] S_AXIS_TDATA;\n wire [C_AXIS_TSTRB_WIDTH-1:0] S_AXIS_TSTRB;\n wire [C_AXIS_TKEEP_WIDTH-1:0] S_AXIS_TKEEP;\n wire S_AXIS_TLAST;\n wire [C_AXIS_TID_WIDTH-1:0] S_AXIS_TID;\n wire [C_AXIS_TDEST_WIDTH-1:0] S_AXIS_TDEST;\n wire [C_AXIS_TUSER_WIDTH-1:0] S_AXIS_TUSER;\n wire M_AXIS_TVALID;\n wire M_AXIS_TREADY;\n wire [C_AXIS_TDATA_WIDTH-1:0] M_AXIS_TDATA;\n wire [C_AXIS_TSTRB_WIDTH-1:0] M_AXIS_TSTRB;\n wire [C_AXIS_TKEEP_WIDTH-1:0] M_AXIS_TKEEP;\n wire M_AXIS_TLAST;\n wire [C_AXIS_TID_WIDTH-1:0] M_AXIS_TID;\n wire [C_AXIS_TDEST_WIDTH-1:0] M_AXIS_TDEST;\n wire [C_AXIS_TUSER_WIDTH-1:0] M_AXIS_TUSER;\n wire AXI_AW_INJECTSBITERR;\n wire AXI_AW_INJECTDBITERR;\n wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_FULL_THRESH;\n wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_EMPTY_THRESH;\n wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_DATA_COUNT;\n wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_WR_DATA_COUNT;\n wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_RD_DATA_COUNT;\n wire AXI_AW_SBITERR;\n wire AXI_AW_DBITERR;\n wire AXI_AW_OVERFLOW;\n wire AXI_AW_UNDERFLOW;\n wire AXI_AW_PROG_FULL;\n wire AXI_AW_PROG_EMPTY;\n wire AXI_W_INJECTSBITERR;\n wire AXI_W_INJECTDBITERR;\n wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_FULL_THRESH;\n wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_EMPTY_THRESH;\n wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_DATA_COUNT;\n wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_WR_DATA_COUNT;\n wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_RD_DATA_COUNT;\n wire AXI_W_SBITERR;\n wire AXI_W_DBITERR;\n wire AXI_W_OVERFLOW;\n wire AXI_W_UNDERFLOW;\n wire AXI_W_PROG_FULL;\n wire AXI_W_PROG_EMPTY;\n wire AXI_B_INJECTSBITERR;\n wire AXI_B_INJECTDBITERR;\n wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_FULL_THRESH;\n wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_EMPTY_THRESH;\n wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_DATA_COUNT;\n wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_WR_DATA_COUNT;\n wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_RD_DATA_COUNT;\n wire AXI_B_SBITERR;\n wire AXI_B_DBITERR;\n wire AXI_B_OVERFLOW;\n wire AXI_B_UNDERFLOW;\n wire AXI_B_PROG_FULL;\n wire AXI_B_PROG_EMPTY;\n wire AXI_AR_INJECTSBITERR;\n wire AXI_AR_INJECTDBITERR;\n wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_FULL_THRESH;\n wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_EMPTY_THRESH;\n wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_DATA_COUNT;\n wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_WR_DATA_COUNT;\n wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_RD_DATA_COUNT;\n wire AXI_AR_SBITERR;\n wire AXI_AR_DBITERR;\n wire AXI_AR_OVERFLOW;\n wire AXI_AR_UNDERFLOW;\n wire AXI_AR_PROG_FULL;\n wire AXI_AR_PROG_EMPTY;\n wire AXI_R_INJECTSBITERR;\n wire AXI_R_INJECTDBITERR;\n wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_FULL_THRESH;\n wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_EMPTY_THRESH;\n wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_DATA_COUNT;\n wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_WR_DATA_COUNT;\n wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_RD_DATA_COUNT;\n wire AXI_R_SBITERR;\n wire AXI_R_DBITERR;\n wire AXI_R_OVERFLOW;\n wire AXI_R_UNDERFLOW;\n wire AXI_R_PROG_FULL;\n wire AXI_R_PROG_EMPTY;\n wire AXIS_INJECTSBITERR;\n wire AXIS_INJECTDBITERR;\n wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_FULL_THRESH;\n wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_EMPTY_THRESH;\n wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_DATA_COUNT;\n wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_WR_DATA_COUNT;\n wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_RD_DATA_COUNT;\n wire AXIS_SBITERR;\n wire AXIS_DBITERR;\n wire AXIS_OVERFLOW;\n wire AXIS_UNDERFLOW;\n wire AXIS_PROG_FULL;\n wire AXIS_PROG_EMPTY;\n wire [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count_in;\n wire wr_rst_int;\n wire rd_rst_int;\n wire wr_rst_busy_o;\n wire wr_rst_busy_ntve;\n wire wr_rst_busy_axis;\n wire wr_rst_busy_wach;\n wire wr_rst_busy_wdch;\n wire wr_rst_busy_wrch;\n wire wr_rst_busy_rach;\n wire wr_rst_busy_rdch;\n\n\n\n function integer find_log2;\n input integer int_val;\n integer i,j;\n begin\n i = 1;\n j = 0;\n for (i = 1; i < int_val; i = i*2) begin\n j = j + 1;\n end\n find_log2 = j;\n end\n endfunction\n\n\n\n\n // Conventional FIFO Interface Signals\n assign BACKUP = backup;\n assign BACKUP_MARKER = backup_marker;\n assign CLK = clk;\n assign RST = rst;\n assign SRST = srst;\n assign WR_CLK = wr_clk;\n assign WR_RST = wr_rst;\n assign RD_CLK = rd_clk;\n assign RD_RST = rd_rst;\n assign WR_EN = wr_en;\n assign RD_EN = rd_en;\n assign INT_CLK = int_clk;\n assign INJECTDBITERR = injectdbiterr;\n assign INJECTSBITERR = injectsbiterr;\n assign SLEEP = sleep;\n assign full = FULL;\n assign almost_full = ALMOST_FULL;\n assign wr_ack = WR_ACK;\n assign overflow = OVERFLOW;\n assign empty = EMPTY;\n assign almost_empty = ALMOST_EMPTY;\n assign valid = VALID;\n assign underflow = UNDERFLOW;\n assign prog_full = PROG_FULL;\n assign prog_empty = PROG_EMPTY;\n assign sbiterr = SBITERR;\n assign dbiterr = DBITERR;\n// assign wr_rst_busy = WR_RST_BUSY | wr_rst_busy_o;\n assign wr_rst_busy = wr_rst_busy_o;\n assign rd_rst_busy = RD_RST_BUSY;\n assign M_ACLK = m_aclk;\n assign S_ACLK = s_aclk;\n assign S_ARESETN = s_aresetn;\n assign S_ACLK_EN = s_aclk_en;\n assign M_ACLK_EN = m_aclk_en;\n assign S_AXI_AWVALID = s_axi_awvalid;\n assign s_axi_awready = S_AXI_AWREADY;\n assign S_AXI_WLAST = s_axi_wlast;\n assign S_AXI_WVALID = s_axi_wvalid;\n assign s_axi_wready = S_AXI_WREADY;\n assign s_axi_bvalid = S_AXI_BVALID;\n assign S_AXI_BREADY = s_axi_bready;\n assign m_axi_awvalid = M_AXI_AWVALID;\n assign M_AXI_AWREADY = m_axi_awready;\n assign m_axi_wlast = M_AXI_WLAST;\n assign m_axi_wvalid = M_AXI_WVALID;\n assign M_AXI_WREADY = m_axi_wready;\n assign M_AXI_BVALID = m_axi_bvalid;\n assign m_axi_bready = M_AXI_BREADY;\n assign S_AXI_ARVALID = s_axi_arvalid;\n assign s_axi_arready = S_AXI_ARREADY;\n assign s_axi_rlast = S_AXI_RLAST;\n assign s_axi_rvalid = S_AXI_RVALID;\n assign S_AXI_RREADY = s_axi_rready;\n assign m_axi_arvalid = M_AXI_ARVALID;\n assign M_AXI_ARREADY = m_axi_arready;\n assign M_AXI_RLAST = m_axi_rlast;\n assign M_AXI_RVALID = m_axi_rvalid;\n assign m_axi_rready = M_AXI_RREADY;\n assign S_AXIS_TVALID = s_axis_tvalid;\n assign s_axis_tready = S_AXIS_TREADY;\n assign S_AXIS_TLAST = s_axis_tlast;\n assign m_axis_tvalid = M_AXIS_TVALID;\n assign M_AXIS_TREADY = m_axis_tready;\n assign m_axis_tlast = M_AXIS_TLAST;\n assign AXI_AW_INJECTSBITERR = axi_aw_injectsbiterr;\n assign AXI_AW_INJECTDBITERR = axi_aw_injectdbiterr;\n assign axi_aw_sbiterr = AXI_AW_SBITERR;\n assign axi_aw_dbiterr = AXI_AW_DBITERR;\n assign axi_aw_overflow = AXI_AW_OVERFLOW;\n assign axi_aw_underflow = AXI_AW_UNDERFLOW;\n assign axi_aw_prog_full = AXI_AW_PROG_FULL;\n assign axi_aw_prog_empty = AXI_AW_PROG_EMPTY;\n assign AXI_W_INJECTSBITERR = axi_w_injectsbiterr;\n assign AXI_W_INJECTDBITERR = axi_w_injectdbiterr;\n assign axi_w_sbiterr = AXI_W_SBITERR;\n assign axi_w_dbiterr = AXI_W_DBITERR;\n assign axi_w_overflow = AXI_W_OVERFLOW;\n assign axi_w_underflow = AXI_W_UNDERFLOW;\n assign axi_w_prog_full = AXI_W_PROG_FULL;\n assign axi_w_prog_empty = AXI_W_PROG_EMPTY;\n assign AXI_B_INJECTSBITERR = axi_b_injectsbiterr;\n assign AXI_B_INJECTDBITERR = axi_b_injectdbiterr;\n assign axi_b_sbiterr = AXI_B_SBITERR;\n assign axi_b_dbiterr = AXI_B_DBITERR;\n assign axi_b_overflow = AXI_B_OVERFLOW;\n assign axi_b_underflow = AXI_B_UNDERFLOW;\n assign axi_b_prog_full = AXI_B_PROG_FULL;\n assign axi_b_prog_empty = AXI_B_PROG_EMPTY;\n assign AXI_AR_INJECTSBITERR = axi_ar_injectsbiterr;\n assign AXI_AR_INJECTDBITERR = axi_ar_injectdbiterr;\n assign axi_ar_sbiterr = AXI_AR_SBITERR;\n assign axi_ar_dbiterr = AXI_AR_DBITERR;\n assign axi_ar_overflow = AXI_AR_OVERFLOW;\n assign axi_ar_underflow = AXI_AR_UNDERFLOW;\n assign axi_ar_prog_full = AXI_AR_PROG_FULL;\n assign axi_ar_prog_empty = AXI_AR_PROG_EMPTY;\n assign AXI_R_INJECTSBITERR = axi_r_injectsbiterr;\n assign AXI_R_INJECTDBITERR = axi_r_injectdbiterr;\n assign axi_r_sbiterr = AXI_R_SBITERR;\n assign axi_r_dbiterr = AXI_R_DBITERR;\n assign axi_r_overflow = AXI_R_OVERFLOW;\n assign axi_r_underflow = AXI_R_UNDERFLOW;\n assign axi_r_prog_full = AXI_R_PROG_FULL;\n assign axi_r_prog_empty = AXI_R_PROG_EMPTY;\n assign AXIS_INJECTSBITERR = axis_injectsbiterr;\n assign AXIS_INJECTDBITERR = axis_injectdbiterr;\n assign axis_sbiterr = AXIS_SBITERR;\n assign axis_dbiterr = AXIS_DBITERR;\n assign axis_overflow = AXIS_OVERFLOW;\n assign axis_underflow = AXIS_UNDERFLOW;\n assign axis_prog_full = AXIS_PROG_FULL;\n assign axis_prog_empty = AXIS_PROG_EMPTY;\n\n\n assign DIN = din;\n assign PROG_EMPTY_THRESH = prog_empty_thresh;\n assign PROG_EMPTY_THRESH_ASSERT = prog_empty_thresh_assert;\n assign PROG_EMPTY_THRESH_NEGATE = prog_empty_thresh_negate;\n assign PROG_FULL_THRESH = prog_full_thresh;\n assign PROG_FULL_THRESH_ASSERT = prog_full_thresh_assert;\n assign PROG_FULL_THRESH_NEGATE = prog_full_thresh_negate;\n assign dout = DOUT;\n assign data_count = DATA_COUNT;\n assign rd_data_count = RD_DATA_COUNT;\n assign wr_data_count = WR_DATA_COUNT;\n assign S_AXI_AWID = s_axi_awid;\n assign S_AXI_AWADDR = s_axi_awaddr;\n assign S_AXI_AWLEN = s_axi_awlen;\n assign S_AXI_AWSIZE = s_axi_awsize;\n assign S_AXI_AWBURST = s_axi_awburst;\n assign S_AXI_AWLOCK = s_axi_awlock;\n assign S_AXI_AWCACHE = s_axi_awcache;\n assign S_AXI_AWPROT = s_axi_awprot;\n assign S_AXI_AWQOS = s_axi_awqos;\n assign S_AXI_AWREGION = s_axi_awregion;\n assign S_AXI_AWUSER = s_axi_awuser;\n assign S_AXI_WID = s_axi_wid;\n assign S_AXI_WDATA = s_axi_wdata;\n assign S_AXI_WSTRB = s_axi_wstrb;\n assign S_AXI_WUSER = s_axi_wuser;\n assign s_axi_bid = S_AXI_BID;\n assign s_axi_bresp = S_AXI_BRESP;\n assign s_axi_buser = S_AXI_BUSER;\n assign m_axi_awid = M_AXI_AWID;\n assign m_axi_awaddr = M_AXI_AWADDR;\n assign m_axi_awlen = M_AXI_AWLEN;\n assign m_axi_awsize = M_AXI_AWSIZE;\n assign m_axi_awburst = M_AXI_AWBURST;\n assign m_axi_awlock = M_AXI_AWLOCK;\n assign m_axi_awcache = M_AXI_AWCACHE;\n assign m_axi_awprot = M_AXI_AWPROT;\n assign m_axi_awqos = M_AXI_AWQOS;\n assign m_axi_awregion = M_AXI_AWREGION;\n assign m_axi_awuser = M_AXI_AWUSER;\n assign m_axi_wid = M_AXI_WID;\n assign m_axi_wdata = M_AXI_WDATA;\n assign m_axi_wstrb = M_AXI_WSTRB;\n assign m_axi_wuser = M_AXI_WUSER;\n assign M_AXI_BID = m_axi_bid;\n assign M_AXI_BRESP = m_axi_bresp;\n assign M_AXI_BUSER = m_axi_buser;\n assign S_AXI_ARID = s_axi_arid;\n assign S_AXI_ARADDR = s_axi_araddr; \n assign S_AXI_ARLEN = s_axi_arlen;\n assign S_AXI_ARSIZE = s_axi_arsize;\n assign S_AXI_ARBURST = s_axi_arburst;\n assign S_AXI_ARLOCK = s_axi_arlock;\n assign S_AXI_ARCACHE = s_axi_arcache;\n assign S_AXI_ARPROT = s_axi_arprot;\n assign S_AXI_ARQOS = s_axi_arqos;\n assign S_AXI_ARREGION = s_axi_arregion;\n assign S_AXI_ARUSER = s_axi_aruser;\n assign s_axi_rid = S_AXI_RID;\n assign s_axi_rdata = S_AXI_RDATA;\n assign s_axi_rresp = S_AXI_RRESP;\n assign s_axi_ruser = S_AXI_RUSER;\n assign m_axi_arid = M_AXI_ARID; \n assign m_axi_araddr = M_AXI_ARADDR; \n assign m_axi_arlen = M_AXI_ARLEN;\n assign m_axi_arsize = M_AXI_ARSIZE;\n assign m_axi_arburst = M_AXI_ARBURST;\n assign m_axi_arlock = M_AXI_ARLOCK;\n assign m_axi_arcache = M_AXI_ARCACHE;\n assign m_axi_arprot = M_AXI_ARPROT;\n assign m_axi_arqos = M_AXI_ARQOS;\n assign m_axi_arregion = M_AXI_ARREGION;\n assign m_axi_aruser = M_AXI_ARUSER;\n assign M_AXI_RID = m_axi_rid; \n assign M_AXI_RDATA = m_axi_rdata; \n assign M_AXI_RRESP = m_axi_rresp;\n assign M_AXI_RUSER = m_axi_ruser;\n assign S_AXIS_TDATA = s_axis_tdata;\n assign S_AXIS_TSTRB = s_axis_tstrb;\n assign S_AXIS_TKEEP = s_axis_tkeep;\n assign S_AXIS_TID = s_axis_tid;\n assign S_AXIS_TDEST = s_axis_tdest;\n assign S_AXIS_TUSER = s_axis_tuser;\n assign m_axis_tdata = M_AXIS_TDATA;\n assign m_axis_tstrb = M_AXIS_TSTRB;\n assign m_axis_tkeep = M_AXIS_TKEEP;\n assign m_axis_tid = M_AXIS_TID;\n assign m_axis_tdest = M_AXIS_TDEST;\n assign m_axis_tuser = M_AXIS_TUSER;\n assign AXI_AW_PROG_FULL_THRESH = axi_aw_prog_full_thresh;\n assign AXI_AW_PROG_EMPTY_THRESH = axi_aw_prog_empty_thresh;\n assign axi_aw_data_count = AXI_AW_DATA_COUNT;\n assign axi_aw_wr_data_count = AXI_AW_WR_DATA_COUNT;\n assign axi_aw_rd_data_count = AXI_AW_RD_DATA_COUNT;\n assign AXI_W_PROG_FULL_THRESH = axi_w_prog_full_thresh;\n assign AXI_W_PROG_EMPTY_THRESH = axi_w_prog_empty_thresh;\n assign axi_w_data_count = AXI_W_DATA_COUNT;\n assign axi_w_wr_data_count = AXI_W_WR_DATA_COUNT;\n assign axi_w_rd_data_count = AXI_W_RD_DATA_COUNT;\n assign AXI_B_PROG_FULL_THRESH = axi_b_prog_full_thresh;\n assign AXI_B_PROG_EMPTY_THRESH = axi_b_prog_empty_thresh;\n assign axi_b_data_count = AXI_B_DATA_COUNT;\n assign axi_b_wr_data_count = AXI_B_WR_DATA_COUNT;\n assign axi_b_rd_data_count = AXI_B_RD_DATA_COUNT;\n assign AXI_AR_PROG_FULL_THRESH = axi_ar_prog_full_thresh;\n assign AXI_AR_PROG_EMPTY_THRESH = axi_ar_prog_empty_thresh;\n assign axi_ar_data_count = AXI_AR_DATA_COUNT;\n assign axi_ar_wr_data_count = AXI_AR_WR_DATA_COUNT;\n assign axi_ar_rd_data_count = AXI_AR_RD_DATA_COUNT;\n assign AXI_R_PROG_FULL_THRESH = axi_r_prog_full_thresh;\n assign AXI_R_PROG_EMPTY_THRESH = axi_r_prog_empty_thresh;\n assign axi_r_data_count = AXI_R_DATA_COUNT;\n assign axi_r_wr_data_count = AXI_R_WR_DATA_COUNT;\n assign axi_r_rd_data_count = AXI_R_RD_DATA_COUNT;\n assign AXIS_PROG_FULL_THRESH = axis_prog_full_thresh;\n assign AXIS_PROG_EMPTY_THRESH = axis_prog_empty_thresh;\n assign axis_data_count = AXIS_DATA_COUNT;\n assign axis_wr_data_count = AXIS_WR_DATA_COUNT;\n assign axis_rd_data_count = AXIS_RD_DATA_COUNT;\n\n\n generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo\n\n fifo_generator_v13_1_2_CONV_VER\n #(\n .C_COMMON_CLOCK \t\t(C_COMMON_CLOCK),\n .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n .C_DATA_COUNT_WIDTH\t\t(C_DATA_COUNT_WIDTH),\n .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH),\n .C_DOUT_RST_VAL\t\t\t(C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0),\n .C_DOUT_WIDTH\t\t\t(C_DOUT_WIDTH),\n .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n .C_FAMILY\t\t\t(C_FAMILY),\n .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),\n .C_HAS_ALMOST_EMPTY\t\t(C_HAS_ALMOST_EMPTY),\n .C_HAS_ALMOST_FULL\t\t(C_HAS_ALMOST_FULL),\n .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n .C_HAS_DATA_COUNT\t\t(C_HAS_DATA_COUNT),\n .C_HAS_INT_CLK (C_HAS_INT_CLK),\n .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n .C_HAS_RD_DATA_COUNT\t\t(C_HAS_RD_DATA_COUNT),\n .C_HAS_RD_RST\t\t\t(C_HAS_RD_RST),\n .C_HAS_RST\t\t\t(C_HAS_RST),\n .C_HAS_SRST\t\t\t(C_HAS_SRST),\n .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n .C_HAS_VALID\t\t\t(C_HAS_VALID),\n .C_HAS_WR_ACK\t\t\t(C_HAS_WR_ACK),\n .C_HAS_WR_DATA_COUNT\t\t(C_HAS_WR_DATA_COUNT),\n .C_HAS_WR_RST\t\t\t(C_HAS_WR_RST),\n .C_IMPLEMENTATION_TYPE\t\t(C_IMPLEMENTATION_TYPE),\n .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n .C_MEMORY_TYPE\t\t\t(C_MEMORY_TYPE),\n .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n .C_PRELOAD_LATENCY\t\t(C_PRELOAD_LATENCY),\n .C_PRELOAD_REGS\t\t\t(C_PRELOAD_REGS),\n .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL),\n .C_PROG_EMPTY_THRESH_NEGATE_VAL\t(C_PROG_EMPTY_THRESH_NEGATE_VAL),\n .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE),\n .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL),\n .C_PROG_FULL_THRESH_NEGATE_VAL\t(C_PROG_FULL_THRESH_NEGATE_VAL),\n .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE),\n .C_RD_DATA_COUNT_WIDTH\t\t(C_RD_DATA_COUNT_WIDTH),\n .C_RD_DEPTH\t\t\t(C_RD_DEPTH),\n .C_RD_FREQ\t\t\t(C_RD_FREQ),\n .C_RD_PNTR_WIDTH\t\t(C_RD_PNTR_WIDTH),\n .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n .C_USE_DOUT_RST (C_USE_DOUT_RST),\n .C_USE_ECC (C_USE_ECC),\n .C_USE_EMBEDDED_REG\t\t(C_USE_EMBEDDED_REG),\n .C_EN_SAFETY_CKT\t\t(C_EN_SAFETY_CKT),\n .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n .C_USE_FWFT_DATA_COUNT\t\t(C_USE_FWFT_DATA_COUNT),\n .C_VALID_LOW\t\t\t(C_VALID_LOW),\n .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_DATA_COUNT_WIDTH),\n .C_WR_DEPTH\t\t\t(C_WR_DEPTH),\n .C_WR_FREQ\t\t\t(C_WR_FREQ),\n .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH),\n .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY),\n .C_MSGON_VAL (C_MSGON_VAL),\n .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),\n .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),\n .C_AXI_TYPE (C_AXI_TYPE),\n .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE)\n )\n fifo_generator_v13_1_2_conv_dut\n (\n .BACKUP (BACKUP),\n .BACKUP_MARKER (BACKUP_MARKER),\n .CLK (CLK),\n .RST (RST),\n .SRST (SRST),\n .WR_CLK (WR_CLK),\n .WR_RST (WR_RST),\n .RD_CLK (RD_CLK),\n .RD_RST (RD_RST),\n .DIN (DIN),\n .WR_EN (WR_EN),\n .RD_EN (RD_EN),\n .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH),\n .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),\n .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),\n .PROG_FULL_THRESH (PROG_FULL_THRESH),\n .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT),\n .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE),\n .INT_CLK (INT_CLK),\n .INJECTDBITERR (INJECTDBITERR), \n .INJECTSBITERR (INJECTSBITERR),\n \n .DOUT (DOUT),\n .FULL (FULL),\n .ALMOST_FULL (ALMOST_FULL),\n .WR_ACK (WR_ACK),\n .OVERFLOW (OVERFLOW),\n .EMPTY (EMPTY),\n .ALMOST_EMPTY (ALMOST_EMPTY),\n .VALID (VALID),\n .UNDERFLOW (UNDERFLOW),\n .DATA_COUNT (DATA_COUNT),\n .RD_DATA_COUNT (RD_DATA_COUNT),\n .WR_DATA_COUNT (wr_data_count_in),\n .PROG_FULL (PROG_FULL),\n .PROG_EMPTY (PROG_EMPTY),\n .SBITERR (SBITERR),\n .DBITERR (DBITERR),\n .wr_rst_busy_o (wr_rst_busy_o),\n .wr_rst_busy (wr_rst_busy_i),\n .rd_rst_busy (rd_rst_busy),\n .wr_rst_i_out (wr_rst_int),\n .rd_rst_i_out (rd_rst_int)\n );\n end endgenerate\n\n\n\n localparam IS_8SERIES = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\") ? 1 : 0;\n localparam C_AXI_SIZE_WIDTH = 3;\n localparam C_AXI_BURST_WIDTH = 2;\n localparam C_AXI_CACHE_WIDTH = 4;\n localparam C_AXI_PROT_WIDTH = 3;\n localparam C_AXI_QOS_WIDTH = 4;\n localparam C_AXI_REGION_WIDTH = 4;\n localparam C_AXI_BRESP_WIDTH = 2;\n localparam C_AXI_RRESP_WIDTH = 2;\n\n localparam IS_AXI_STREAMING = C_INTERFACE_TYPE == 1 ? 1 : 0;\n localparam TDATA_OFFSET = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS;\n localparam TSTRB_OFFSET = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET;\n localparam TKEEP_OFFSET = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET;\n localparam TID_OFFSET = C_HAS_AXIS_TID == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET;\n localparam TDEST_OFFSET = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET;\n localparam TUSER_OFFSET = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET;\n localparam LOG_DEPTH_AXIS = find_log2(C_WR_DEPTH_AXIS); \n localparam LOG_WR_DEPTH = find_log2(C_WR_DEPTH); \n\n\n function [LOG_DEPTH_AXIS-1:0] bin2gray;\n input [LOG_DEPTH_AXIS-1:0] x;\n begin\n bin2gray = x ^ (x>>1);\n end\n endfunction\n\n function [LOG_DEPTH_AXIS-1:0] gray2bin;\n input [LOG_DEPTH_AXIS-1:0] x;\n integer i;\n begin\n gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1];\n for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin\n gray2bin[i] = gray2bin[i+1] ^ x[i];\n end\n end\n endfunction\n\nwire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last;\nwire [LOG_WR_DEPTH-1 : 0] w_q [0:C_SYNCHRONIZER_STAGE] ;\nwire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE] ;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt = 0;\nreg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0;\nreg [LOG_WR_DEPTH-1 : 0] r_cnt = 0;\nwire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad;\nwire [LOG_WR_DEPTH : 0] r_inv_pad;\nwire [LOG_WR_DEPTH-1 : 0] d_cnt;\nreg [LOG_WR_DEPTH : 0] d_cnt_pad = 0;\nreg adj_w_cnt_rd_pad_0 = 0;\nreg r_inv_pad_0 = 0;\n\n\n genvar l;\n\n generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage\n fifo_generator_v13_1_2_sync_stage\n #(\n .C_WIDTH (LOG_WR_DEPTH)\n )\n rd_stg_inst\n (\n .RST (rd_rst_int), \n .CLK (RD_CLK), \n .DIN (w_q[l-1]), \n .DOUT (w_q[l])\n );\n end endgenerate // gpkt_cnt_sync_stage\n\n\n\n generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter\n assign wr_eop_ad = WR_EN & !(FULL);\n assign rd_eop_ad = RD_EN & !(EMPTY);\n\n\n always @ (posedge wr_rst_int or posedge WR_CLK)\n begin\n if (wr_rst_int)\n w_cnt <= 1'b0;\n else if (wr_eop_ad)\n w_cnt <= w_cnt + 1;\n end\n\n always @ (posedge wr_rst_int or posedge WR_CLK)\n begin\n if (wr_rst_int)\n w_cnt_gc <= 1'b0;\n else \n w_cnt_gc <= bin2gray(w_cnt);\n end\n\n\n assign w_q[0] = w_cnt_gc;\n assign w_cnt_gc_asreg_last = w_q[C_SYNCHRONIZER_STAGE];\n\n\n\n always @ (posedge rd_rst_int or posedge RD_CLK)\n begin\n if (rd_rst_int)\n w_cnt_rd <= 1'b0;\n else \n w_cnt_rd <= gray2bin(w_cnt_gc_asreg_last);\n end\n\n always @ (posedge rd_rst_int or posedge RD_CLK)\n begin\n if (rd_rst_int)\n r_cnt <= 1'b0;\n else if (rd_eop_ad)\n r_cnt <= r_cnt + 1;\n end\n\n\n // Take the difference of write and read packet count\n // Logic is similar to rd_pe_as\n assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd;\n assign r_inv_pad[LOG_WR_DEPTH : 1] = ~r_cnt;\n assign adj_w_cnt_rd_pad[0] = adj_w_cnt_rd_pad_0;\n assign r_inv_pad[0] = r_inv_pad_0;\n\n\n always @ ( rd_eop_ad )\n begin\n if (!rd_eop_ad) begin\n adj_w_cnt_rd_pad_0 <= 1'b1;\n r_inv_pad_0 <= 1'b1;\n end else begin \n adj_w_cnt_rd_pad_0 <= 1'b0;\n r_inv_pad_0 <= 1'b0;\n end\t\n end\n\n always @ (posedge rd_rst_int or posedge RD_CLK)\n begin\n if (rd_rst_int)\n d_cnt_pad <= 1'b0;\n else \n d_cnt_pad <= adj_w_cnt_rd_pad + r_inv_pad ;\n end\n\n assign d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ;\n assign WR_DATA_COUNT = d_cnt;\n\n end endgenerate // fifo_ic_adapter\n\n generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter\n assign WR_DATA_COUNT = wr_data_count_in;\n\n end endgenerate // fifo_icn_adapter\n\n\n\n wire inverted_reset = ~S_ARESETN;\n wire axi_rs_rst;\n wire [C_DIN_WIDTH_AXIS-1:0] axis_din ;\n wire [C_DIN_WIDTH_AXIS-1:0] axis_dout ;\n wire axis_full ;\n wire axis_almost_full ;\n wire axis_empty ;\n wire axis_s_axis_tready;\n wire axis_m_axis_tvalid;\n wire axis_wr_en ;\n wire axis_rd_en ;\n wire axis_we ;\n wire axis_re ;\n wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc;\n reg axis_pkt_read = 1'b0;\n wire axis_rd_rst;\n wire axis_wr_rst;\n\n generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 ||\n C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst\n reg rst_d1 = 0 ;\n reg rst_d2 = 0 ;\n reg [3:0] axi_rst = 4'h0 ;\n always @ (posedge inverted_reset or posedge S_ACLK) begin\n if (inverted_reset) begin\n rst_d1 <= 1'b1;\n rst_d2 <= 1'b1;\n axi_rst <= 4'hf;\n end else begin\n rst_d1 <= #`TCQ 1'b0;\n rst_d2 <= #`TCQ rst_d1;\n axi_rst <= #`TCQ {axi_rst[2:0],1'b0};\n end\n end\n\n assign axi_rs_rst = axi_rst[3];//rst_d2;\n end endgenerate // gaxi_rs_rst\n\n generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming\n\n // Write protection when almost full or prog_full is high\n assign axis_we = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID : \n (C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID;\n\n // Read protection when almost empty or prog_empty is high\n assign axis_re = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY :\n (C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY;\n assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? axis_we & S_ACLK_EN : axis_we;\n assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re;\n\n fifo_generator_v13_1_2_CONV_VER\n #(\n .C_FAMILY\t\t\t(C_FAMILY),\n .C_COMMON_CLOCK (C_COMMON_CLOCK),\n .C_INTERFACE_TYPE (C_INTERFACE_TYPE),\n .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 :\n (C_IMPLEMENTATION_TYPE_AXIS == 2 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4),\n .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 :\n (C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6),\n .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_AXIS),\n .C_WR_DEPTH\t\t\t(C_WR_DEPTH_AXIS),\n .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS),\n .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_AXIS),\n .C_RD_DEPTH\t\t\t(C_WR_DEPTH_AXIS),\n .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS),\n .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_AXIS),\n .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_AXIS),\n .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_AXIS),\n .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS),\n .C_USE_ECC (C_USE_ECC_AXIS),\n .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_AXIS),\n .C_HAS_ALMOST_EMPTY\t\t(0),\n .C_HAS_ALMOST_FULL\t\t(C_APPLICATION_TYPE_AXIS == 1 ? 1: 0),\n .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n .C_USE_EMBEDDED_REG\t\t(C_USE_EMBEDDED_REG),\n .C_FIFO_TYPE (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS),\n .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),\n\n .C_HAS_WR_RST\t\t\t(0),\n .C_HAS_RD_RST\t\t\t(0),\n .C_HAS_RST\t\t\t(1),\n .C_HAS_SRST\t\t\t(0),\n .C_DOUT_RST_VAL\t\t\t(0),\n\n .C_HAS_VALID\t\t\t(0),\n .C_VALID_LOW\t\t\t(C_VALID_LOW),\n .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n .C_HAS_WR_ACK\t\t\t(0),\n .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),\n .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_AXIS + 1),\n .C_FULL_FLAGS_RST_VAL (1),\n .C_USE_DOUT_RST (0),\n .C_MSGON_VAL (C_MSGON_VAL),\n .C_ENABLE_RST_SYNC (1),\n .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0),\n .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n .C_HAS_INT_CLK (C_HAS_INT_CLK),\n .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n .C_RD_FREQ\t\t\t(C_RD_FREQ),\n .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n .C_WR_FREQ\t\t\t(C_WR_FREQ),\n .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n )\n fifo_generator_v13_1_2_axis_dut\n (\n .CLK (S_ACLK),\n .WR_CLK (S_ACLK),\n .RD_CLK (M_ACLK),\n .RST (inverted_reset),\n .SRST (1'b0),\n .WR_RST (inverted_reset),\n .RD_RST (inverted_reset),\n .WR_EN (axis_wr_en),\n .RD_EN (axis_rd_en),\n .PROG_FULL_THRESH (AXIS_PROG_FULL_THRESH),\n .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n .PROG_EMPTY_THRESH (AXIS_PROG_EMPTY_THRESH),\n .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),\n .INJECTDBITERR (AXIS_INJECTDBITERR), \n .INJECTSBITERR (AXIS_INJECTSBITERR),\n \n .DIN (axis_din),\n .DOUT (axis_dout),\n .FULL (axis_full),\n .EMPTY (axis_empty),\n .ALMOST_FULL (axis_almost_full),\n .PROG_FULL (AXIS_PROG_FULL),\n .ALMOST_EMPTY (),\n .PROG_EMPTY (AXIS_PROG_EMPTY),\n \n .WR_ACK (),\n .OVERFLOW (AXIS_OVERFLOW),\n .VALID (),\n .UNDERFLOW (AXIS_UNDERFLOW),\n .DATA_COUNT (axis_dc),\n .RD_DATA_COUNT (AXIS_RD_DATA_COUNT),\n .WR_DATA_COUNT (AXIS_WR_DATA_COUNT),\n .SBITERR (AXIS_SBITERR),\n .DBITERR (AXIS_DBITERR),\n .wr_rst_busy (wr_rst_busy_axis),\n .rd_rst_busy (rd_rst_busy_axis),\n .wr_rst_i_out (axis_wr_rst),\n .rd_rst_i_out (axis_rd_rst),\n \n .BACKUP (BACKUP),\n .BACKUP_MARKER (BACKUP_MARKER),\n .INT_CLK (INT_CLK)\n );\n\n assign axis_s_axis_tready = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full;\n assign axis_m_axis_tvalid = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read;\n assign S_AXIS_TREADY = axis_s_axis_tready;\n assign M_AXIS_TVALID = axis_m_axis_tvalid;\n\n end endgenerate // axi_streaming\n\n wire axis_wr_eop;\n reg axis_wr_eop_d1 = 1'b0;\n wire axis_rd_eop;\n integer axis_pkt_cnt;\n\n generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc\n assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;\n assign axis_rd_eop = axis_rd_en & axis_dout[0];\n\n always @ (posedge inverted_reset or posedge S_ACLK)\n begin\n if (inverted_reset)\n axis_pkt_read <= 1'b0;\n else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1)\n axis_pkt_read <= 1'b0;\n else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty))\n axis_pkt_read <= 1'b1;\n end\n\n always @ (posedge inverted_reset or posedge S_ACLK)\n begin\n if (inverted_reset)\n axis_wr_eop_d1 <= 1'b0;\n else\n axis_wr_eop_d1 <= axis_wr_eop;\n end\n\n always @ (posedge inverted_reset or posedge S_ACLK)\n begin\n if (inverted_reset)\n axis_pkt_cnt <= 0;\n else if (axis_wr_eop_d1 && ~axis_rd_eop)\n axis_pkt_cnt <= axis_pkt_cnt + 1;\n else if (axis_rd_eop && ~axis_wr_eop_d1)\n axis_pkt_cnt <= axis_pkt_cnt - 1;\n end\n end endgenerate // gaxis_pkt_fifo_cc\n\n\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0;\nwire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last;\nwire axis_rd_has_rst;\nwire [0:C_SYNCHRONIZER_STAGE] axis_af_q ;\nwire [LOG_DEPTH_AXIS-1 : 0] wpkt_q [0:C_SYNCHRONIZER_STAGE] ;\nwire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0;\nwire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE] ;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0;\nreg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0;\nwire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad;\nwire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad;\nwire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt;\nreg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0;\nreg adj_axis_wpkt_cnt_rd_pad_0 = 0;\nreg rpkt_inv_pad_0 = 0;\nwire axis_af_rd ;\n\ngenerate if (C_HAS_RST == 1) begin : rst_blk_has\n assign axis_rd_has_rst = axis_rd_rst;\nend endgenerate //rst_blk_has\n\ngenerate if (C_HAS_RST == 0) begin :rst_blk_no\n assign axis_rd_has_rst = 1'b0;\nend endgenerate //rst_blk_no\n\n genvar i;\n\n generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage\n fifo_generator_v13_1_2_sync_stage\n #(\n .C_WIDTH (LOG_DEPTH_AXIS)\n )\n rd_stg_inst\n (\n .RST (axis_rd_has_rst), \n .CLK (M_ACLK), \n .DIN (wpkt_q[i-1]), \n .DOUT (wpkt_q[i])\n );\n \n fifo_generator_v13_1_2_sync_stage\n #(\n .C_WIDTH (1)\n )\n wr_stg_inst\n (\n .RST (axis_rd_has_rst), \n .CLK (M_ACLK), \n .DIN (axis_af_q[i-1]), \n .DOUT (axis_af_q[i])\n );\n end endgenerate // gpkt_cnt_sync_stage\n\n\n generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic\n assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;\n assign axis_rd_eop = axis_rd_en & axis_dout[0];\n\n always @ (posedge axis_rd_has_rst or posedge M_ACLK)\n begin\n if (axis_rd_has_rst)\n axis_pkt_read <= 1'b0;\n else if (axis_rd_eop && (diff_pkt_cnt == 1))\n axis_pkt_read <= 1'b0;\n else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty))\n axis_pkt_read <= 1'b1;\n end\n\n always @ (posedge axis_wr_rst or posedge S_ACLK)\n begin\n if (axis_wr_rst)\n axis_wpkt_cnt <= 1'b0;\n else if (axis_wr_eop)\n axis_wpkt_cnt <= axis_wpkt_cnt + 1;\n end\n\n always @ (posedge axis_wr_rst or posedge S_ACLK)\n begin\n if (axis_wr_rst)\n axis_wpkt_cnt_gc <= 1'b0;\n else \n axis_wpkt_cnt_gc <= bin2gray(axis_wpkt_cnt);\n end\n\n\n assign wpkt_q[0] = axis_wpkt_cnt_gc;\n assign axis_wpkt_cnt_gc_asreg_last = wpkt_q[C_SYNCHRONIZER_STAGE];\n assign axis_af_q[0] = axis_almost_full;\n //assign axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE];\n assign axis_af_rd = axis_af_q[C_SYNCHRONIZER_STAGE];\n\n\n\n always @ (posedge axis_rd_has_rst or posedge M_ACLK)\n begin\n if (axis_rd_has_rst)\n axis_wpkt_cnt_rd <= 1'b0;\n else \n axis_wpkt_cnt_rd <= gray2bin(axis_wpkt_cnt_gc_asreg_last);\n end\n\n always @ (posedge axis_rd_rst or posedge M_ACLK)\n begin\n if (axis_rd_has_rst)\n axis_rpkt_cnt <= 1'b0;\n else if (axis_rd_eop)\n axis_rpkt_cnt <= axis_rpkt_cnt + 1;\n end\n\n\n // Take the difference of write and read packet count\n // Logic is similar to rd_pe_as\n assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd;\n assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1] = ~axis_rpkt_cnt;\n assign adj_axis_wpkt_cnt_rd_pad[0] = adj_axis_wpkt_cnt_rd_pad_0;\n assign rpkt_inv_pad[0] = rpkt_inv_pad_0;\n\n\n always @ ( axis_rd_eop )\n begin\n if (!axis_rd_eop) begin\n adj_axis_wpkt_cnt_rd_pad_0 <= 1'b1;\n rpkt_inv_pad_0 <= 1'b1;\n end else begin \n adj_axis_wpkt_cnt_rd_pad_0 <= 1'b0;\n rpkt_inv_pad_0 <= 1'b0;\n end\t\n end\n\n always @ (posedge axis_rd_rst or posedge M_ACLK)\n begin\n if (axis_rd_has_rst)\n diff_pkt_cnt_pad <= 1'b0;\n else \n diff_pkt_cnt_pad <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ;\n end\n\n assign diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ;\n\n\n\n\n\n end endgenerate // gaxis_pkt_fifo_ic\n\n\n\n\n // Generate the accurate data count for axi stream packet fifo configuration\n reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0;\n generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt\n always @ (posedge inverted_reset or posedge S_ACLK)\n begin\n if (inverted_reset)\n axis_dc_pkt_fifo <= 0;\n else if (axis_wr_en && (~axis_rd_en))\n axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1;\n else if (~axis_wr_en && axis_rd_en)\n axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1;\n end\n assign AXIS_DATA_COUNT = axis_dc_pkt_fifo;\n end endgenerate // gdc_pkt\n\n generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt\n assign AXIS_DATA_COUNT = 0;\n end endgenerate // gndc_pkt\n\n generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc\n assign AXIS_DATA_COUNT = axis_dc;\n end endgenerate // gdc\n\n // Register Slice for Write Address Channel\n generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice\n assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID;\n assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY;\n\n fifo_generator_v13_1_2_axic_reg_slice\n #(\n .C_FAMILY (C_FAMILY),\n .C_DATA_WIDTH (C_DIN_WIDTH_AXIS),\n .C_REG_CONFIG (C_REG_SLICE_MODE_AXIS)\n )\n axis_reg_slice_inst\n (\n // System Signals\n .ACLK (S_ACLK),\n .ARESET (axi_rs_rst),\n\n // Slave side\n .S_PAYLOAD_DATA (axis_din),\n .S_VALID (axis_wr_en),\n .S_READY (S_AXIS_TREADY),\n\n // Master side\n .M_PAYLOAD_DATA (axis_dout),\n .M_VALID (M_AXIS_TVALID),\n .M_READY (axis_rd_en)\n );\n end endgenerate // gaxis_reg_slice\n\n\n\n generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata\n assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA;\n assign M_AXIS_TDATA = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET];\n end endgenerate\n\n generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb\n assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB;\n assign M_AXIS_TSTRB = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET];\n end endgenerate\n\n generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep\n assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP;\n assign M_AXIS_TKEEP = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET];\n end endgenerate\n\n generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid\n assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID;\n assign M_AXIS_TID = axis_dout[TKEEP_OFFSET-1:TID_OFFSET];\n end endgenerate\n\n generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest\n assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST;\n assign M_AXIS_TDEST = axis_dout[TID_OFFSET-1:TDEST_OFFSET];\n end endgenerate\n\n generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser\n assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER;\n assign M_AXIS_TUSER = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET];\n end endgenerate\n\n generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast\n assign axis_din[0] = S_AXIS_TLAST;\n assign M_AXIS_TLAST = axis_dout[0];\n end endgenerate\n\n //###########################################################################\n // AXI FULL Write Channel (axi_write_channel)\n //###########################################################################\n\n localparam IS_AXI_FULL = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0;\n localparam IS_AXI_LITE = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0;\n\n localparam IS_AXI_FULL_WACH = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n localparam IS_AXI_FULL_WDCH = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n localparam IS_AXI_FULL_WRCH = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n localparam IS_AXI_FULL_RACH = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n localparam IS_AXI_FULL_RDCH = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n\n localparam IS_AXI_LITE_WACH = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n localparam IS_AXI_LITE_WDCH = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n localparam IS_AXI_LITE_WRCH = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;\n localparam IS_AXI_LITE_RACH = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n localparam IS_AXI_LITE_RDCH = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;\n\n localparam IS_WR_ADDR_CH = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0;\n localparam IS_WR_DATA_CH = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0;\n localparam IS_WR_RESP_CH = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0;\n localparam IS_RD_ADDR_CH = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0;\n localparam IS_RD_DATA_CH = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0;\n\n localparam AWID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH;\n localparam AWADDR_OFFSET = AWID_OFFSET - C_AXI_ADDR_WIDTH;\n localparam AWLEN_OFFSET = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET;\n localparam AWSIZE_OFFSET = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET;\n localparam AWBURST_OFFSET = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET;\n localparam AWLOCK_OFFSET = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET;\n localparam AWCACHE_OFFSET = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET;\n localparam AWPROT_OFFSET = AWCACHE_OFFSET - C_AXI_PROT_WIDTH;\n localparam AWQOS_OFFSET = AWPROT_OFFSET - C_AXI_QOS_WIDTH;\n localparam AWREGION_OFFSET = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET;\n localparam AWUSER_OFFSET = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET;\n\n localparam WID_OFFSET = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH;\n localparam WDATA_OFFSET = WID_OFFSET - C_AXI_DATA_WIDTH;\n localparam WSTRB_OFFSET = WDATA_OFFSET - C_AXI_DATA_WIDTH/8;\n localparam WUSER_OFFSET = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET;\n\n localparam BID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH;\n localparam BRESP_OFFSET = BID_OFFSET - C_AXI_BRESP_WIDTH;\n localparam BUSER_OFFSET = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET;\n\n\n wire [C_DIN_WIDTH_WACH-1:0] wach_din ;\n wire [C_DIN_WIDTH_WACH-1:0] wach_dout ;\n wire [C_DIN_WIDTH_WACH-1:0] wach_dout_pkt ;\n wire wach_full ;\n wire wach_almost_full ;\n wire wach_prog_full ;\n wire wach_empty ;\n wire wach_almost_empty ;\n wire wach_prog_empty ;\n wire [C_DIN_WIDTH_WDCH-1:0] wdch_din ;\n wire [C_DIN_WIDTH_WDCH-1:0] wdch_dout ;\n wire wdch_full ;\n wire wdch_almost_full ;\n wire wdch_prog_full ;\n wire wdch_empty ;\n wire wdch_almost_empty ;\n wire wdch_prog_empty ;\n wire [C_DIN_WIDTH_WRCH-1:0] wrch_din ;\n wire [C_DIN_WIDTH_WRCH-1:0] wrch_dout ;\n wire wrch_full ;\n wire wrch_almost_full ;\n wire wrch_prog_full ;\n wire wrch_empty ;\n wire wrch_almost_empty ;\n wire wrch_prog_empty ;\n wire axi_aw_underflow_i;\n wire axi_w_underflow_i ;\n wire axi_b_underflow_i ;\n wire axi_aw_overflow_i ;\n wire axi_w_overflow_i ;\n wire axi_b_overflow_i ;\n wire axi_wr_underflow_i;\n wire axi_wr_overflow_i ;\n wire wach_s_axi_awready;\n wire wach_m_axi_awvalid;\n wire wach_wr_en ;\n wire wach_rd_en ;\n wire wdch_s_axi_wready ;\n wire wdch_m_axi_wvalid ;\n wire wdch_wr_en ;\n wire wdch_rd_en ;\n wire wrch_s_axi_bvalid ;\n wire wrch_m_axi_bready ;\n wire wrch_wr_en ;\n wire wrch_rd_en ;\n wire txn_count_up ;\n wire txn_count_down ;\n wire awvalid_en ;\n wire awvalid_pkt ;\n wire awready_pkt ;\n integer wr_pkt_count ;\n wire wach_we ;\n wire wach_re ;\n wire wdch_we ;\n wire wdch_re ;\n wire wrch_we ;\n wire wrch_re ;\n\n generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel\n // Write protection when almost full or prog_full is high\n assign wach_we = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID;\n\n // Read protection when almost empty or prog_empty is high\n assign wach_re = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ? \n wach_m_axi_awvalid & awready_pkt & awvalid_en : \n (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ? \n M_AXI_AWREADY && wach_m_axi_awvalid :\n (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ? \n awready_pkt & awvalid_en : \n (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ? \n M_AXI_AWREADY : 1'b0;\n assign wach_wr_en = (C_HAS_SLAVE_CE == 1) ? wach_we & S_ACLK_EN : wach_we;\n assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re;\n\n fifo_generator_v13_1_2_CONV_VER\n #(\n .C_FAMILY\t\t\t(C_FAMILY),\n .C_COMMON_CLOCK (C_COMMON_CLOCK),\n .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 :\n (C_IMPLEMENTATION_TYPE_WACH == 2 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4),\n .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 :\n (C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6),\n .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WACH),\n .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WACH),\n .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH),\n .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WACH),\n .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WACH),\n .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH),\n .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WACH),\n .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WACH),\n .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WACH),\n .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH),\n .C_USE_ECC (C_USE_ECC_WACH),\n .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WACH),\n .C_HAS_ALMOST_EMPTY\t\t(0),\n .C_HAS_ALMOST_FULL\t\t(0),\n .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n .C_FIFO_TYPE ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH),\n .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),\n\n .C_HAS_WR_RST\t\t\t(0),\n .C_HAS_RD_RST\t\t\t(0),\n .C_HAS_RST\t\t\t(1),\n .C_HAS_SRST\t\t\t(0),\n .C_DOUT_RST_VAL\t\t\t(0),\n .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0),\n .C_HAS_VALID\t\t\t(0),\n .C_VALID_LOW\t\t\t(C_VALID_LOW),\n .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n .C_HAS_WR_ACK\t\t\t(0),\n .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),\n .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WACH + 1),\n .C_FULL_FLAGS_RST_VAL (1),\n .C_USE_EMBEDDED_REG\t\t(0),\n .C_USE_DOUT_RST (0),\n .C_MSGON_VAL (C_MSGON_VAL),\n .C_ENABLE_RST_SYNC (1),\n .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n .C_HAS_INT_CLK (C_HAS_INT_CLK),\n .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n .C_RD_FREQ\t\t\t(C_RD_FREQ),\n .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n .C_WR_FREQ\t\t\t(C_WR_FREQ),\n .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n )\n fifo_generator_v13_1_2_wach_dut\n (\n .CLK (S_ACLK),\n .WR_CLK (S_ACLK),\n .RD_CLK (M_ACLK),\n .RST (inverted_reset),\n .SRST (1'b0),\n .WR_RST (inverted_reset),\n .RD_RST (inverted_reset),\n .WR_EN (wach_wr_en),\n .RD_EN (wach_rd_en),\n .PROG_FULL_THRESH (AXI_AW_PROG_FULL_THRESH),\n .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n .PROG_EMPTY_THRESH (AXI_AW_PROG_EMPTY_THRESH),\n .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),\n .INJECTDBITERR (AXI_AW_INJECTDBITERR), \n .INJECTSBITERR (AXI_AW_INJECTSBITERR),\n \n .DIN (wach_din),\n .DOUT (wach_dout_pkt),\n .FULL (wach_full),\n .EMPTY (wach_empty),\n .ALMOST_FULL (),\n .PROG_FULL (AXI_AW_PROG_FULL),\n .ALMOST_EMPTY (),\n .PROG_EMPTY (AXI_AW_PROG_EMPTY),\n \n .WR_ACK (),\n .OVERFLOW (axi_aw_overflow_i),\n .VALID (),\n .UNDERFLOW (axi_aw_underflow_i),\n .DATA_COUNT (AXI_AW_DATA_COUNT),\n .RD_DATA_COUNT (AXI_AW_RD_DATA_COUNT),\n .WR_DATA_COUNT (AXI_AW_WR_DATA_COUNT),\n .SBITERR (AXI_AW_SBITERR),\n .DBITERR (AXI_AW_DBITERR),\n .wr_rst_busy (wr_rst_busy_wach),\n .rd_rst_busy (rd_rst_busy_wach),\n .wr_rst_i_out (),\n .rd_rst_i_out (),\n \n .BACKUP (BACKUP),\n .BACKUP_MARKER (BACKUP_MARKER),\n .INT_CLK (INT_CLK)\n );\n\n assign wach_s_axi_awready = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full;\n assign wach_m_axi_awvalid = ~wach_empty;\n assign S_AXI_AWREADY = wach_s_axi_awready;\n\n assign AXI_AW_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0;\n assign AXI_AW_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_aw_overflow_i : 0;\n\n end endgenerate // axi_write_address_channel\n\n // Register Slice for Write Address Channel\n generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice\n\n fifo_generator_v13_1_2_axic_reg_slice\n #(\n .C_FAMILY (C_FAMILY),\n .C_DATA_WIDTH (C_DIN_WIDTH_WACH),\n .C_REG_CONFIG (C_REG_SLICE_MODE_WACH)\n )\n wach_reg_slice_inst\n (\n // System Signals\n .ACLK (S_ACLK),\n .ARESET (axi_rs_rst),\n\n // Slave side\n .S_PAYLOAD_DATA (wach_din),\n .S_VALID (S_AXI_AWVALID),\n .S_READY (S_AXI_AWREADY),\n\n // Master side\n .M_PAYLOAD_DATA (wach_dout),\n .M_VALID (M_AXI_AWVALID),\n .M_READY (M_AXI_AWREADY)\n );\n end endgenerate // gwach_reg_slice\n \n generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr\n\n fifo_generator_v13_1_2_axic_reg_slice\n #(\n .C_FAMILY (C_FAMILY),\n .C_DATA_WIDTH (C_DIN_WIDTH_WACH),\n .C_REG_CONFIG (1)\n )\n wach_pkt_reg_slice_inst\n (\n // System Signals\n .ACLK (S_ACLK),\n .ARESET (inverted_reset),\n\n // Slave side\n .S_PAYLOAD_DATA (wach_dout_pkt),\n .S_VALID (awvalid_pkt),\n .S_READY (awready_pkt),\n\n // Master side\n .M_PAYLOAD_DATA (wach_dout),\n .M_VALID (M_AXI_AWVALID),\n .M_READY (M_AXI_AWREADY)\n );\n\n assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en;\n\n assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0]; \n assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en;\n\n always@(posedge S_ACLK or posedge inverted_reset) begin\n if(inverted_reset == 1) begin\n\twr_pkt_count <= 0;\n end else begin\n\tif(txn_count_up == 1 && txn_count_down == 0) begin\n\t wr_pkt_count <= wr_pkt_count + 1;\n\tend else if(txn_count_up == 0 && txn_count_down == 1) begin\n\t wr_pkt_count <= wr_pkt_count - 1;\n\tend\n end\n end //Always end\n assign awvalid_en = (wr_pkt_count > 0)?1:0;\n end endgenerate\n \n generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr\n assign awvalid_en = 1; \n assign wach_dout = wach_dout_pkt;\n assign M_AXI_AWVALID = wach_m_axi_awvalid;\n end\n endgenerate\n\n\n\n generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel\n // Write protection when almost full or prog_full is high\n assign wdch_we = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID;\n\n // Read protection when almost empty or prog_empty is high\n assign wdch_re = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY;\n assign wdch_wr_en = (C_HAS_SLAVE_CE == 1) ? wdch_we & S_ACLK_EN : wdch_we;\n assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re;\n\n\n fifo_generator_v13_1_2_CONV_VER\n #(\n .C_FAMILY\t\t\t(C_FAMILY),\n .C_COMMON_CLOCK (C_COMMON_CLOCK),\n .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 :\n (C_IMPLEMENTATION_TYPE_WDCH == 2 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4),\n .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 :\n (C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6),\n .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WDCH),\n .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WDCH),\n .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH),\n .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WDCH),\n .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WDCH),\n .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH),\n .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WDCH),\n .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WDCH),\n .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WDCH),\n .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH),\n .C_USE_ECC (C_USE_ECC_WDCH),\n .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WDCH),\n .C_HAS_ALMOST_EMPTY\t\t(0),\n .C_HAS_ALMOST_FULL\t\t(0),\n .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n .C_FIFO_TYPE (C_APPLICATION_TYPE_WDCH),\n .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),\n\n .C_HAS_WR_RST\t\t\t(0),\n .C_HAS_RD_RST\t\t\t(0),\n .C_HAS_RST\t\t\t(1),\n .C_HAS_SRST\t\t\t(0),\n .C_DOUT_RST_VAL\t\t\t(0),\n\n .C_HAS_VALID\t\t\t(0),\n .C_VALID_LOW\t\t\t(C_VALID_LOW),\n .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n .C_HAS_WR_ACK\t\t\t(0),\n .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),\n .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WDCH + 1),\n .C_FULL_FLAGS_RST_VAL (1),\n .C_USE_EMBEDDED_REG\t\t(0),\n .C_USE_DOUT_RST (0),\n .C_MSGON_VAL (C_MSGON_VAL),\n .C_ENABLE_RST_SYNC (1),\n .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0),\n .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n .C_HAS_INT_CLK (C_HAS_INT_CLK),\n .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n .C_RD_FREQ\t\t\t(C_RD_FREQ),\n .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n .C_WR_FREQ\t\t\t(C_WR_FREQ),\n .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n )\n fifo_generator_v13_1_2_wdch_dut\n (\n .CLK (S_ACLK),\n .WR_CLK (S_ACLK),\n .RD_CLK (M_ACLK),\n .RST (inverted_reset),\n .SRST (1'b0),\n .WR_RST (inverted_reset),\n .RD_RST (inverted_reset),\n .WR_EN (wdch_wr_en),\n .RD_EN (wdch_rd_en),\n .PROG_FULL_THRESH (AXI_W_PROG_FULL_THRESH),\n .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n .PROG_EMPTY_THRESH (AXI_W_PROG_EMPTY_THRESH),\n .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),\n .INJECTDBITERR (AXI_W_INJECTDBITERR), \n .INJECTSBITERR (AXI_W_INJECTSBITERR),\n \n .DIN (wdch_din),\n .DOUT (wdch_dout),\n .FULL (wdch_full),\n .EMPTY (wdch_empty),\n .ALMOST_FULL (),\n .PROG_FULL (AXI_W_PROG_FULL),\n .ALMOST_EMPTY (),\n .PROG_EMPTY (AXI_W_PROG_EMPTY),\n \n .WR_ACK (),\n .OVERFLOW (axi_w_overflow_i),\n .VALID (),\n .UNDERFLOW (axi_w_underflow_i),\n .DATA_COUNT (AXI_W_DATA_COUNT),\n .RD_DATA_COUNT (AXI_W_RD_DATA_COUNT),\n .WR_DATA_COUNT (AXI_W_WR_DATA_COUNT),\n .SBITERR (AXI_W_SBITERR),\n .DBITERR (AXI_W_DBITERR),\n .wr_rst_busy (wr_rst_busy_wdch),\n .rd_rst_busy (rd_rst_busy_wdch),\n .wr_rst_i_out (),\n .rd_rst_i_out (),\n \n .BACKUP (BACKUP),\n .BACKUP_MARKER (BACKUP_MARKER),\n .INT_CLK (INT_CLK)\n );\n\n assign wdch_s_axi_wready = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full;\n assign wdch_m_axi_wvalid = ~wdch_empty;\n assign S_AXI_WREADY = wdch_s_axi_wready;\n assign M_AXI_WVALID = wdch_m_axi_wvalid;\n\n assign AXI_W_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i : 0;\n assign AXI_W_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_w_overflow_i : 0;\n\n end endgenerate // axi_write_data_channel\n\n // Register Slice for Write Data Channel\n generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice\n\n fifo_generator_v13_1_2_axic_reg_slice\n #(\n .C_FAMILY (C_FAMILY),\n .C_DATA_WIDTH (C_DIN_WIDTH_WDCH),\n .C_REG_CONFIG (C_REG_SLICE_MODE_WDCH)\n )\n wdch_reg_slice_inst\n (\n // System Signals\n .ACLK (S_ACLK),\n .ARESET (axi_rs_rst),\n\n // Slave side\n .S_PAYLOAD_DATA (wdch_din),\n .S_VALID (S_AXI_WVALID),\n .S_READY (S_AXI_WREADY),\n\n // Master side\n .M_PAYLOAD_DATA (wdch_dout),\n .M_VALID (M_AXI_WVALID),\n .M_READY (M_AXI_WREADY)\n );\n end endgenerate // gwdch_reg_slice\n\n generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel\n // Write protection when almost full or prog_full is high\n assign wrch_we = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID;\n\n // Read protection when almost empty or prog_empty is high\n assign wrch_re = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY;\n assign wrch_wr_en = (C_HAS_MASTER_CE == 1) ? wrch_we & M_ACLK_EN : wrch_we;\n assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re;\n\n fifo_generator_v13_1_2_CONV_VER\n #(\n .C_FAMILY\t\t\t(C_FAMILY),\n .C_COMMON_CLOCK (C_COMMON_CLOCK),\n .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 :\n (C_IMPLEMENTATION_TYPE_WRCH == 2 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4),\n .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 :\n (C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6),\n .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_WRCH),\n .C_WR_DEPTH\t\t\t(C_WR_DEPTH_WRCH),\n .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH),\n .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_WRCH),\n .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n .C_RD_DEPTH\t\t\t(C_WR_DEPTH_WRCH),\n .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH),\n .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_WRCH),\n .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_WRCH),\n .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_WRCH),\n .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH),\n .C_USE_ECC (C_USE_ECC_WRCH),\n .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WRCH),\n .C_HAS_ALMOST_EMPTY\t\t(0),\n .C_HAS_ALMOST_FULL\t\t(0),\n .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n .C_FIFO_TYPE (C_APPLICATION_TYPE_WRCH),\n .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),\n\n .C_HAS_WR_RST\t\t\t(0),\n .C_HAS_RD_RST\t\t\t(0),\n .C_HAS_RST\t\t\t(1),\n .C_HAS_SRST\t\t\t(0),\n .C_DOUT_RST_VAL\t\t\t(0),\n\n .C_HAS_VALID\t\t\t(0),\n .C_VALID_LOW\t\t\t(C_VALID_LOW),\n .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n .C_HAS_WR_ACK\t\t\t(0),\n .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),\n .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_WRCH + 1),\n .C_FULL_FLAGS_RST_VAL (1),\n .C_USE_EMBEDDED_REG\t\t(0),\n .C_USE_DOUT_RST (0),\n .C_MSGON_VAL (C_MSGON_VAL),\n .C_ENABLE_RST_SYNC (1),\n .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0),\n .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n .C_HAS_INT_CLK (C_HAS_INT_CLK),\n .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n .C_RD_FREQ\t\t\t(C_RD_FREQ),\n .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n .C_WR_FREQ\t\t\t(C_WR_FREQ),\n .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n )\n fifo_generator_v13_1_2_wrch_dut\n (\n .CLK (S_ACLK),\n .WR_CLK (M_ACLK),\n .RD_CLK (S_ACLK),\n .RST (inverted_reset),\n .SRST (1'b0),\n .WR_RST (inverted_reset),\n .RD_RST (inverted_reset),\n .WR_EN (wrch_wr_en),\n .RD_EN (wrch_rd_en),\n .PROG_FULL_THRESH (AXI_B_PROG_FULL_THRESH),\n .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n .PROG_EMPTY_THRESH (AXI_B_PROG_EMPTY_THRESH),\n .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),\n .INJECTDBITERR (AXI_B_INJECTDBITERR), \n .INJECTSBITERR (AXI_B_INJECTSBITERR),\n \n .DIN (wrch_din),\n .DOUT (wrch_dout),\n .FULL (wrch_full),\n .EMPTY (wrch_empty),\n .ALMOST_FULL (),\n .ALMOST_EMPTY (),\n .PROG_FULL (AXI_B_PROG_FULL),\n .PROG_EMPTY (AXI_B_PROG_EMPTY),\n \n .WR_ACK (),\n .OVERFLOW (axi_b_overflow_i),\n .VALID (),\n .UNDERFLOW (axi_b_underflow_i),\n .DATA_COUNT (AXI_B_DATA_COUNT),\n .RD_DATA_COUNT (AXI_B_RD_DATA_COUNT),\n .WR_DATA_COUNT (AXI_B_WR_DATA_COUNT),\n .SBITERR (AXI_B_SBITERR),\n .DBITERR (AXI_B_DBITERR),\n .wr_rst_busy (wr_rst_busy_wrch),\n .rd_rst_busy (rd_rst_busy_wrch),\n .wr_rst_i_out (),\n .rd_rst_i_out (),\n \n .BACKUP (BACKUP),\n .BACKUP_MARKER (BACKUP_MARKER),\n .INT_CLK (INT_CLK)\n );\n\n assign wrch_s_axi_bvalid = ~wrch_empty;\n assign wrch_m_axi_bready = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full;\n assign S_AXI_BVALID = wrch_s_axi_bvalid;\n assign M_AXI_BREADY = wrch_m_axi_bready;\n\n assign AXI_B_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i : 0;\n assign AXI_B_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_b_overflow_i : 0;\n end endgenerate // axi_write_resp_channel\n\n // Register Slice for Write Response Channel\n generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice\n\n fifo_generator_v13_1_2_axic_reg_slice\n #(\n .C_FAMILY (C_FAMILY),\n .C_DATA_WIDTH (C_DIN_WIDTH_WRCH),\n .C_REG_CONFIG (C_REG_SLICE_MODE_WRCH)\n )\n wrch_reg_slice_inst\n (\n // System Signals\n .ACLK (S_ACLK),\n .ARESET (axi_rs_rst),\n\n // Slave side\n .S_PAYLOAD_DATA (wrch_din),\n .S_VALID (M_AXI_BVALID),\n .S_READY (M_AXI_BREADY),\n\n // Master side\n .M_PAYLOAD_DATA (wrch_dout),\n .M_VALID (S_AXI_BVALID),\n .M_READY (S_AXI_BREADY)\n );\n end endgenerate // gwrch_reg_slice\n\n\n assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0;\n assign axi_wr_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_aw_overflow_i || axi_w_overflow_i || axi_b_overflow_i) : 0;\n\n generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output\n assign M_AXI_AWADDR = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET]; \n assign M_AXI_AWLEN = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET]; \n assign M_AXI_AWSIZE = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET]; \n assign M_AXI_AWBURST = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET]; \n assign M_AXI_AWLOCK = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET]; \n assign M_AXI_AWCACHE = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET]; \n assign M_AXI_AWPROT = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET]; \n assign M_AXI_AWQOS = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET]; \n assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET] = S_AXI_AWADDR;\n assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET] = S_AXI_AWLEN;\n assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET] = S_AXI_AWSIZE;\n assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST;\n assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK;\n assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE;\n assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT;\n assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET] = S_AXI_AWQOS;\n end endgenerate // axi_wach_output\n\n generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion\n assign M_AXI_AWREGION = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET]; \n end endgenerate // axi_awregion\n\n generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion\n assign M_AXI_AWREGION = 0; \n end endgenerate // naxi_awregion\n\n generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser\n assign M_AXI_AWUSER = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET]; \n end endgenerate // axi_awuser\n\n generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser\n assign M_AXI_AWUSER = 0; \n end endgenerate // naxi_awuser\n\n\n generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid\n assign M_AXI_AWID = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET];\n end endgenerate //axi_awid\n\n generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid\n assign M_AXI_AWID = 0;\n end endgenerate //naxi_awid\n\n generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output\n assign M_AXI_WDATA = wdch_dout[WID_OFFSET-1:WDATA_OFFSET];\n assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];\n assign M_AXI_WLAST = wdch_dout[0];\n assign wdch_din[WID_OFFSET-1:WDATA_OFFSET] = S_AXI_WDATA;\n assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB;\n assign wdch_din[0] = S_AXI_WLAST;\n end endgenerate // axi_wdch_output\n\n generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin\n assign M_AXI_WID = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET];\n end endgenerate\n generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin\n assign M_AXI_WID = 0;\n end endgenerate\n\n generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin\n assign M_AXI_WUSER = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET]; \n end endgenerate\n generate if (C_HAS_AXI_WUSER == 0) begin\n assign M_AXI_WUSER = 0;\n end endgenerate\n\n generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output\n assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET]; \n assign wrch_din[BID_OFFSET-1:BRESP_OFFSET] = M_AXI_BRESP;\n end endgenerate // axi_wrch_output\n\n generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser\n assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET];\n end endgenerate // axi_buser\n\n generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser\n assign S_AXI_BUSER = 0;\n end endgenerate // naxi_buser\n\n generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid\n assign S_AXI_BID = wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET];\n end endgenerate // axi_bid\n \n generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid\n assign S_AXI_BID = 0 ;\n end endgenerate // naxi_bid \n\n\n generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1\n assign wach_din = {S_AXI_AWADDR, S_AXI_AWPROT};\n assign M_AXI_AWADDR = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET]; \n assign M_AXI_AWPROT = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET]; \n end endgenerate // axi_wach_output1\n\n generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1\n assign wdch_din = {S_AXI_WDATA, S_AXI_WSTRB};\n assign M_AXI_WDATA = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET];\n assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];\n end endgenerate // axi_wdch_output1\n\n generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1\n assign wrch_din = M_AXI_BRESP;\n assign S_AXI_BRESP = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET]; \n end endgenerate // axi_wrch_output1\n\n generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1\n assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET] = S_AXI_AWUSER;\n end endgenerate // gwach_din1\n\n generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2\n assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET] = S_AXI_AWID;\n end endgenerate // gwach_din2\n\n generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3\n assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET] = S_AXI_AWREGION;\n end endgenerate // gwach_din3\n\n generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1\n assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER;\n end endgenerate // gwdch_din1\n\n generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2\n assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID;\n end endgenerate // gwdch_din2\n\n generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1\n assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET] = M_AXI_BUSER;\n end endgenerate // gwrch_din1\n\n generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2\n assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET] = M_AXI_BID;\n end endgenerate // gwrch_din2\n\n //end of axi_write_channel\n\n //###########################################################################\n // AXI FULL Read Channel (axi_read_channel)\n //###########################################################################\n wire [C_DIN_WIDTH_RACH-1:0] rach_din ;\n wire [C_DIN_WIDTH_RACH-1:0] rach_dout ;\n wire [C_DIN_WIDTH_RACH-1:0] rach_dout_pkt ;\n wire rach_full ;\n wire rach_almost_full ;\n wire rach_prog_full ;\n wire rach_empty ;\n wire rach_almost_empty ;\n wire rach_prog_empty ;\n wire [C_DIN_WIDTH_RDCH-1:0] rdch_din ;\n wire [C_DIN_WIDTH_RDCH-1:0] rdch_dout ;\n wire rdch_full ;\n wire rdch_almost_full ;\n wire rdch_prog_full ;\n wire rdch_empty ;\n wire rdch_almost_empty ;\n wire rdch_prog_empty ;\n wire axi_ar_underflow_i ;\n wire axi_r_underflow_i ;\n wire axi_ar_overflow_i ;\n wire axi_r_overflow_i ;\n wire axi_rd_underflow_i ;\n wire axi_rd_overflow_i ;\n wire rach_s_axi_arready ;\n wire rach_m_axi_arvalid ;\n wire rach_wr_en ;\n wire rach_rd_en ;\n wire rdch_m_axi_rready ;\n wire rdch_s_axi_rvalid ;\n wire rdch_wr_en ;\n wire rdch_rd_en ;\n wire arvalid_pkt ;\n wire arready_pkt ;\n wire arvalid_en ;\n wire rdch_rd_ok ;\n wire accept_next_pkt ;\n integer rdch_free_space ;\n integer rdch_commited_space ;\n wire rach_we ;\n wire rach_re ;\n wire rdch_we ;\n wire rdch_re ;\n\n localparam ARID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH;\n localparam ARADDR_OFFSET = ARID_OFFSET - C_AXI_ADDR_WIDTH;\n localparam ARLEN_OFFSET = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET;\n localparam ARSIZE_OFFSET = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET;\n localparam ARBURST_OFFSET = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET;\n localparam ARLOCK_OFFSET = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET;\n localparam ARCACHE_OFFSET = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET;\n localparam ARPROT_OFFSET = ARCACHE_OFFSET - C_AXI_PROT_WIDTH;\n localparam ARQOS_OFFSET = ARPROT_OFFSET - C_AXI_QOS_WIDTH;\n localparam ARREGION_OFFSET = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET;\n localparam ARUSER_OFFSET = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET;\n\n localparam RID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH;\n localparam RDATA_OFFSET = RID_OFFSET - C_AXI_DATA_WIDTH;\n localparam RRESP_OFFSET = RDATA_OFFSET - C_AXI_RRESP_WIDTH;\n localparam RUSER_OFFSET = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET;\n\n\n generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel\n\n // Write protection when almost full or prog_full is high\n assign rach_we = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID;\n\n // Read protection when almost empty or prog_empty is high\n// assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en;\n assign rach_re = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ? \n rach_m_axi_arvalid & arready_pkt & arvalid_en : \n (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ? \n M_AXI_ARREADY && rach_m_axi_arvalid :\n (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ? \n arready_pkt & arvalid_en : \n (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ? \n M_AXI_ARREADY : 1'b0;\n assign rach_wr_en = (C_HAS_SLAVE_CE == 1) ? rach_we & S_ACLK_EN : rach_we;\n assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re;\n\n\n fifo_generator_v13_1_2_CONV_VER\n #(\n .C_FAMILY\t\t\t(C_FAMILY),\n .C_COMMON_CLOCK (C_COMMON_CLOCK),\n .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 :\n (C_IMPLEMENTATION_TYPE_RACH == 2 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4),\n .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 :\n (C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6),\n .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_RACH),\n .C_WR_DEPTH\t\t\t(C_WR_DEPTH_RACH),\n .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH),\n .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_RACH),\n .C_RD_DEPTH\t\t\t(C_WR_DEPTH_RACH),\n .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH),\n .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_RACH),\n .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_RACH),\n .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_RACH),\n .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH),\n .C_USE_ECC (C_USE_ECC_RACH),\n .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RACH),\n .C_HAS_ALMOST_EMPTY\t\t(0),\n .C_HAS_ALMOST_FULL\t\t(0),\n .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n .C_FIFO_TYPE ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH),\n .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),\n\n .C_HAS_WR_RST\t\t\t(0),\n .C_HAS_RD_RST\t\t\t(0),\n .C_HAS_RST\t\t\t(1),\n .C_HAS_SRST\t\t\t(0),\n .C_DOUT_RST_VAL\t\t\t(0),\n\n .C_HAS_VALID\t\t\t(0),\n .C_VALID_LOW\t\t\t(C_VALID_LOW),\n .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n .C_HAS_WR_ACK\t\t\t(0),\n .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),\n .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RACH + 1),\n .C_FULL_FLAGS_RST_VAL (1),\n .C_USE_EMBEDDED_REG\t\t(0),\n .C_USE_DOUT_RST (0),\n .C_MSGON_VAL (C_MSGON_VAL),\n .C_ENABLE_RST_SYNC (1),\n .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0),\n .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n .C_HAS_INT_CLK (C_HAS_INT_CLK),\n .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n .C_RD_FREQ\t\t\t(C_RD_FREQ),\n .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n .C_WR_FREQ\t\t\t(C_WR_FREQ),\n .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n )\n fifo_generator_v13_1_2_rach_dut\n (\n .CLK (S_ACLK),\n .WR_CLK (S_ACLK),\n .RD_CLK (M_ACLK),\n .RST (inverted_reset),\n .SRST (1'b0),\n .WR_RST (inverted_reset),\n .RD_RST (inverted_reset),\n .WR_EN (rach_wr_en),\n .RD_EN (rach_rd_en),\n .PROG_FULL_THRESH (AXI_AR_PROG_FULL_THRESH),\n .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n .PROG_EMPTY_THRESH (AXI_AR_PROG_EMPTY_THRESH),\n .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),\n .INJECTDBITERR (AXI_AR_INJECTDBITERR), \n .INJECTSBITERR (AXI_AR_INJECTSBITERR),\n \n .DIN (rach_din),\n .DOUT (rach_dout_pkt),\n .FULL (rach_full),\n .EMPTY (rach_empty),\n .ALMOST_FULL (),\n .ALMOST_EMPTY (),\n .PROG_FULL (AXI_AR_PROG_FULL),\n .PROG_EMPTY (AXI_AR_PROG_EMPTY),\n \n .WR_ACK (),\n .OVERFLOW (axi_ar_overflow_i),\n .VALID (),\n .UNDERFLOW (axi_ar_underflow_i),\n .DATA_COUNT (AXI_AR_DATA_COUNT),\n .RD_DATA_COUNT (AXI_AR_RD_DATA_COUNT),\n .WR_DATA_COUNT (AXI_AR_WR_DATA_COUNT),\n .SBITERR (AXI_AR_SBITERR),\n .DBITERR (AXI_AR_DBITERR),\n .wr_rst_busy (wr_rst_busy_rach),\n .rd_rst_busy (rd_rst_busy_rach),\n .wr_rst_i_out (),\n .rd_rst_i_out (),\n \n .BACKUP (BACKUP),\n .BACKUP_MARKER (BACKUP_MARKER),\n .INT_CLK (INT_CLK)\n );\n\n assign rach_s_axi_arready = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full;\n assign rach_m_axi_arvalid = ~rach_empty;\n assign S_AXI_ARREADY = rach_s_axi_arready;\n\n assign AXI_AR_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0;\n assign AXI_AR_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_ar_overflow_i : 0;\n\n end endgenerate // axi_read_addr_channel\n\n // Register Slice for Read Address Channel\n generate if (C_RACH_TYPE == 1) begin : grach_reg_slice\n\n fifo_generator_v13_1_2_axic_reg_slice\n #(\n .C_FAMILY (C_FAMILY),\n .C_DATA_WIDTH (C_DIN_WIDTH_RACH),\n .C_REG_CONFIG (C_REG_SLICE_MODE_RACH)\n )\n rach_reg_slice_inst\n (\n // System Signals\n .ACLK (S_ACLK),\n .ARESET (axi_rs_rst),\n\n // Slave side\n .S_PAYLOAD_DATA (rach_din),\n .S_VALID (S_AXI_ARVALID),\n .S_READY (S_AXI_ARREADY),\n\n // Master side\n .M_PAYLOAD_DATA (rach_dout),\n .M_VALID (M_AXI_ARVALID),\n .M_READY (M_AXI_ARREADY)\n );\n end endgenerate // grach_reg_slice\n\n // Register Slice for Read Address Channel for MM Packet FIFO\n generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo\n\n fifo_generator_v13_1_2_axic_reg_slice\n #(\n .C_FAMILY (C_FAMILY),\n .C_DATA_WIDTH (C_DIN_WIDTH_RACH),\n .C_REG_CONFIG (1)\n )\n reg_slice_mm_pkt_fifo_inst\n (\n // System Signals\n .ACLK (S_ACLK),\n .ARESET (inverted_reset),\n\n // Slave side\n .S_PAYLOAD_DATA (rach_dout_pkt),\n .S_VALID (arvalid_pkt),\n .S_READY (arready_pkt),\n\n // Master side\n .M_PAYLOAD_DATA (rach_dout),\n .M_VALID (M_AXI_ARVALID),\n .M_READY (M_AXI_ARREADY)\n );\n end endgenerate // grach_reg_slice_mm_pkt_fifo\n\n \n generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid\n assign M_AXI_ARVALID = rach_m_axi_arvalid;\n assign rach_dout = rach_dout_pkt;\n end endgenerate // grach_m_axi_arvalid\n \n \n generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd\n assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en;\n assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en;\n assign accept_next_pkt = rach_m_axi_arvalid && arready_pkt && arvalid_en;\n\n always@(posedge S_ACLK or posedge inverted_reset) begin\n if(inverted_reset) begin\n\trdch_commited_space <= 0;\n end else begin\n\tif(rdch_rd_ok && !accept_next_pkt) begin\n\t rdch_commited_space <= rdch_commited_space-1;\n\tend else if(!rdch_rd_ok && accept_next_pkt) begin\n\t rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1);\n\tend else if(rdch_rd_ok && accept_next_pkt) begin\n\t rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]);\n\tend\n end\n end //Always end\n\n always@(*) begin\n rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1));\n end\n\n assign arvalid_en = (rdch_free_space >= 0)?1:0;\n end\n endgenerate\n \n generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd\n assign arvalid_en = 1; \n end\n endgenerate\n\n generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel\n\n // Write protection when almost full or prog_full is high\n assign rdch_we = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready & M_AXI_RVALID : M_AXI_RVALID;\n\n // Read protection when almost empty or prog_empty is high\n assign rdch_re = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid & S_AXI_RREADY : S_AXI_RREADY;\n assign rdch_wr_en = (C_HAS_MASTER_CE == 1) ? rdch_we & M_ACLK_EN : rdch_we;\n assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re;\n\n fifo_generator_v13_1_2_CONV_VER\n #(\n .C_FAMILY\t\t\t(C_FAMILY),\n .C_COMMON_CLOCK (C_COMMON_CLOCK),\n .C_MEMORY_TYPE\t\t\t((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 :\n (C_IMPLEMENTATION_TYPE_RDCH == 2 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4),\n .C_IMPLEMENTATION_TYPE\t\t((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 :\n (C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6),\n .C_PRELOAD_REGS\t\t\t(1), // always FWFT for AXI\n .C_PRELOAD_LATENCY\t\t(0), // always FWFT for AXI\n .C_DIN_WIDTH\t\t\t(C_DIN_WIDTH_RDCH),\n .C_WR_DEPTH\t\t\t(C_WR_DEPTH_RDCH),\n .C_WR_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH),\n .C_DOUT_WIDTH\t\t\t(C_DIN_WIDTH_RDCH),\n .C_RD_DEPTH\t\t\t(C_WR_DEPTH_RDCH),\n .C_INTERFACE_TYPE \t\t(C_INTERFACE_TYPE),\n .C_RD_PNTR_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH),\n .C_PROG_FULL_TYPE\t\t(C_PROG_FULL_TYPE_RDCH),\n .C_PROG_FULL_THRESH_ASSERT_VAL\t(C_PROG_FULL_THRESH_ASSERT_VAL_RDCH),\n .C_PROG_EMPTY_TYPE\t\t(C_PROG_EMPTY_TYPE_RDCH),\n .C_PROG_EMPTY_THRESH_ASSERT_VAL\t(C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH),\n .C_USE_ECC (C_USE_ECC_RDCH),\n .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RDCH),\n .C_HAS_ALMOST_EMPTY\t\t(0),\n .C_HAS_ALMOST_FULL\t\t(0),\n .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),\n\n .C_FIFO_TYPE (C_APPLICATION_TYPE_RDCH),\n .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),\n\n .C_HAS_WR_RST\t\t\t(0),\n .C_HAS_RD_RST\t\t\t(0),\n .C_HAS_RST\t\t\t(1),\n .C_HAS_SRST\t\t\t(0),\n .C_DOUT_RST_VAL\t\t\t(0),\n\n .C_HAS_VALID\t\t\t(0),\n .C_VALID_LOW\t\t\t(C_VALID_LOW),\n .C_HAS_UNDERFLOW\t\t(C_HAS_UNDERFLOW),\n .C_UNDERFLOW_LOW\t\t(C_UNDERFLOW_LOW),\n .C_HAS_WR_ACK\t\t\t(0),\n .C_WR_ACK_LOW\t\t\t(C_WR_ACK_LOW),\n .C_HAS_OVERFLOW\t\t\t(C_HAS_OVERFLOW),\n .C_OVERFLOW_LOW\t\t\t(C_OVERFLOW_LOW),\n\n .C_HAS_DATA_COUNT\t\t((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n .C_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n .C_HAS_RD_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n .C_RD_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n .C_USE_FWFT_DATA_COUNT\t\t(1), // use extra logic is always true\n .C_HAS_WR_DATA_COUNT\t\t((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),\n .C_WR_DATA_COUNT_WIDTH\t\t(C_WR_PNTR_WIDTH_RDCH + 1),\n .C_FULL_FLAGS_RST_VAL (1),\n .C_USE_EMBEDDED_REG\t\t(0),\n .C_USE_DOUT_RST (0),\n .C_MSGON_VAL (C_MSGON_VAL),\n .C_ENABLE_RST_SYNC (1),\n .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0),\n .C_COUNT_TYPE\t\t\t(C_COUNT_TYPE),\n .C_DEFAULT_VALUE\t\t(C_DEFAULT_VALUE),\n .C_ENABLE_RLOCS\t\t\t(C_ENABLE_RLOCS),\n .C_HAS_BACKUP\t\t\t(C_HAS_BACKUP),\n .C_HAS_INT_CLK (C_HAS_INT_CLK),\n .C_MIF_FILE_NAME\t\t(C_MIF_FILE_NAME),\n .C_HAS_MEMINIT_FILE\t\t(C_HAS_MEMINIT_FILE),\n .C_INIT_WR_PNTR_VAL\t\t(C_INIT_WR_PNTR_VAL),\n .C_OPTIMIZATION_MODE\t\t(C_OPTIMIZATION_MODE),\n .C_PRIM_FIFO_TYPE\t\t(C_PRIM_FIFO_TYPE),\n .C_RD_FREQ\t\t\t(C_RD_FREQ),\n .C_USE_FIFO16_FLAGS\t\t(C_USE_FIFO16_FLAGS),\n .C_WR_FREQ\t\t\t(C_WR_FREQ),\n .C_WR_RESPONSE_LATENCY\t\t(C_WR_RESPONSE_LATENCY)\n )\n fifo_generator_v13_1_2_rdch_dut\n (\n .CLK (S_ACLK),\n .WR_CLK (M_ACLK),\n .RD_CLK (S_ACLK),\n .RST (inverted_reset),\n .SRST (1'b0),\n .WR_RST (inverted_reset),\n .RD_RST (inverted_reset),\n .WR_EN (rdch_wr_en),\n .RD_EN (rdch_rd_en),\n .PROG_FULL_THRESH (AXI_R_PROG_FULL_THRESH),\n .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n .PROG_EMPTY_THRESH (AXI_R_PROG_EMPTY_THRESH),\n .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),\n .INJECTDBITERR (AXI_R_INJECTDBITERR), \n .INJECTSBITERR (AXI_R_INJECTSBITERR),\n \n .DIN (rdch_din),\n .DOUT (rdch_dout),\n .FULL (rdch_full),\n .EMPTY (rdch_empty),\n .ALMOST_FULL (),\n .ALMOST_EMPTY (),\n .PROG_FULL (AXI_R_PROG_FULL),\n .PROG_EMPTY (AXI_R_PROG_EMPTY),\n \n .WR_ACK (),\n .OVERFLOW (axi_r_overflow_i),\n .VALID (),\n .UNDERFLOW (axi_r_underflow_i),\n .DATA_COUNT (AXI_R_DATA_COUNT),\n .RD_DATA_COUNT (AXI_R_RD_DATA_COUNT),\n .WR_DATA_COUNT (AXI_R_WR_DATA_COUNT),\n .SBITERR (AXI_R_SBITERR),\n .DBITERR (AXI_R_DBITERR),\n .wr_rst_busy (wr_rst_busy_rdch),\n .rd_rst_busy (rd_rst_busy_rdch),\n .wr_rst_i_out (),\n .rd_rst_i_out (),\n \n .BACKUP (BACKUP),\n .BACKUP_MARKER (BACKUP_MARKER),\n .INT_CLK (INT_CLK)\n );\n\n assign rdch_s_axi_rvalid = ~rdch_empty;\n assign rdch_m_axi_rready = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full;\n assign S_AXI_RVALID = rdch_s_axi_rvalid;\n assign M_AXI_RREADY = rdch_m_axi_rready;\n\n assign AXI_R_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i : 0;\n assign AXI_R_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_r_overflow_i : 0;\n\n end endgenerate //axi_read_data_channel\n\n // Register Slice for read Data Channel\n generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice\n\n fifo_generator_v13_1_2_axic_reg_slice\n #(\n .C_FAMILY (C_FAMILY),\n .C_DATA_WIDTH (C_DIN_WIDTH_RDCH),\n .C_REG_CONFIG (C_REG_SLICE_MODE_RDCH)\n )\n rdch_reg_slice_inst\n (\n // System Signals\n .ACLK (S_ACLK),\n .ARESET (axi_rs_rst),\n\n // Slave side\n .S_PAYLOAD_DATA (rdch_din),\n .S_VALID (M_AXI_RVALID),\n .S_READY (M_AXI_RREADY),\n\n // Master side\n .M_PAYLOAD_DATA (rdch_dout),\n .M_VALID (S_AXI_RVALID),\n .M_READY (S_AXI_RREADY)\n );\n end endgenerate // grdch_reg_slice\n\n\n assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0;\n assign axi_rd_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_ar_overflow_i || axi_r_overflow_i) : 0;\n\n\n generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output\n assign M_AXI_ARADDR = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET]; \n assign M_AXI_ARLEN = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET]; \n assign M_AXI_ARSIZE = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET]; \n assign M_AXI_ARBURST = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET]; \n assign M_AXI_ARLOCK = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET]; \n assign M_AXI_ARCACHE = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET]; \n assign M_AXI_ARPROT = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET]; \n assign M_AXI_ARQOS = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET]; \n assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET] = S_AXI_ARADDR;\n assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET] = S_AXI_ARLEN;\n assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET] = S_AXI_ARSIZE;\n assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST;\n assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK;\n assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE;\n assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT;\n assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET] = S_AXI_ARQOS;\n end endgenerate // axi_full_rach_output\n\n generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion\n assign M_AXI_ARREGION = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET]; \n end endgenerate // axi_arregion\n\n generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion\n assign M_AXI_ARREGION = 0; \n end endgenerate // naxi_arregion\n\n generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser\n assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET]; \n end endgenerate // axi_aruser\n\n generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser\n assign M_AXI_ARUSER = 0; \n end endgenerate // naxi_aruser\n\n generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid\n assign M_AXI_ARID = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET];\n end endgenerate // axi_arid\n\n generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid\n assign M_AXI_ARID = 0;\n end endgenerate // naxi_arid\n\n generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output\n assign S_AXI_RDATA = rdch_dout[RID_OFFSET-1:RDATA_OFFSET];\n assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];\n assign S_AXI_RLAST = rdch_dout[0];\n assign rdch_din[RID_OFFSET-1:RDATA_OFFSET] = M_AXI_RDATA;\n assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP;\n assign rdch_din[0] = M_AXI_RLAST;\n end endgenerate // axi_full_rdch_output\n \n generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output\n assign S_AXI_RUSER = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET];\n end endgenerate // axi_full_ruser_output\n\n generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output\n assign S_AXI_RUSER = 0;\n end endgenerate // axi_full_nruser_output\n \n generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid\n assign S_AXI_RID = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET];\n end endgenerate // axi_rid\n\n generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid\n assign S_AXI_RID = 0;\n end endgenerate // naxi_rid\n\n generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1\n assign rach_din = {S_AXI_ARADDR, S_AXI_ARPROT};\n assign M_AXI_ARADDR = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET];\n assign M_AXI_ARPROT = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET];\n end endgenerate // axi_lite_rach_output\n\n generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1\n assign rdch_din = {M_AXI_RDATA, M_AXI_RRESP};\n assign S_AXI_RDATA = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET];\n assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];\n end endgenerate // axi_lite_rdch_output\n\n generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1\n assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET] = S_AXI_ARUSER;\n end endgenerate // grach_din1\n\n generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2\n assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET] = S_AXI_ARID;\n end endgenerate // grach_din2\n\n generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin\n assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION;\n end endgenerate\n\n generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1\n assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET] = M_AXI_RUSER;\n end endgenerate // grdch_din1\n\n generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2\n assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID;\n end endgenerate // grdch_din2\n\n //end of axi_read_channel\n\n generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf\n assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) :\n (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i :\n (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0;\n end endgenerate // gaxi_comm_uf\n\n generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of\n assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) :\n (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i :\n (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0;\n end endgenerate // gaxi_comm_of\n \n //-------------------------------------------------------------------------\n //-------------------------------------------------------------------------\n //-------------------------------------------------------------------------\n // Pass Through Logic or Wiring Logic\n //-------------------------------------------------------------------------\n //-------------------------------------------------------------------------\n //-------------------------------------------------------------------------\n \n //-------------------------------------------------------------------------\n // Pass Through Logic for Read Channel\n //-------------------------------------------------------------------------\n\n // Wiring logic for Write Address Channel\n generate if (C_WACH_TYPE == 2) begin : gwach_pass_through\n assign M_AXI_AWID = S_AXI_AWID;\n assign M_AXI_AWADDR = S_AXI_AWADDR;\n assign M_AXI_AWLEN = S_AXI_AWLEN;\n assign M_AXI_AWSIZE = S_AXI_AWSIZE;\n assign M_AXI_AWBURST = S_AXI_AWBURST;\n assign M_AXI_AWLOCK = S_AXI_AWLOCK;\n assign M_AXI_AWCACHE = S_AXI_AWCACHE;\n assign M_AXI_AWPROT = S_AXI_AWPROT;\n assign M_AXI_AWQOS = S_AXI_AWQOS;\n assign M_AXI_AWREGION = S_AXI_AWREGION;\n assign M_AXI_AWUSER = S_AXI_AWUSER;\n assign S_AXI_AWREADY = M_AXI_AWREADY;\n assign M_AXI_AWVALID = S_AXI_AWVALID;\n end endgenerate // gwach_pass_through;\n\n // Wiring logic for Write Data Channel\n generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through\n assign M_AXI_WID = S_AXI_WID;\n assign M_AXI_WDATA = S_AXI_WDATA;\n assign M_AXI_WSTRB = S_AXI_WSTRB;\n assign M_AXI_WLAST = S_AXI_WLAST;\n assign M_AXI_WUSER = S_AXI_WUSER;\n assign S_AXI_WREADY = M_AXI_WREADY;\n assign M_AXI_WVALID = S_AXI_WVALID;\n end endgenerate // gwdch_pass_through;\n\n // Wiring logic for Write Response Channel\n generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through\n assign S_AXI_BID = M_AXI_BID;\n assign S_AXI_BRESP = M_AXI_BRESP;\n assign S_AXI_BUSER = M_AXI_BUSER;\n assign M_AXI_BREADY = S_AXI_BREADY;\n assign S_AXI_BVALID = M_AXI_BVALID;\n end endgenerate // gwrch_pass_through;\n\n //-------------------------------------------------------------------------\n // Pass Through Logic for Read Channel\n //-------------------------------------------------------------------------\n\n // Wiring logic for Read Address Channel\n generate if (C_RACH_TYPE == 2) begin : grach_pass_through\n assign M_AXI_ARID = S_AXI_ARID;\n assign M_AXI_ARADDR = S_AXI_ARADDR;\n assign M_AXI_ARLEN = S_AXI_ARLEN;\n assign M_AXI_ARSIZE = S_AXI_ARSIZE;\n assign M_AXI_ARBURST = S_AXI_ARBURST;\n assign M_AXI_ARLOCK = S_AXI_ARLOCK;\n assign M_AXI_ARCACHE = S_AXI_ARCACHE;\n assign M_AXI_ARPROT = S_AXI_ARPROT;\n assign M_AXI_ARQOS = S_AXI_ARQOS;\n assign M_AXI_ARREGION = S_AXI_ARREGION;\n assign M_AXI_ARUSER = S_AXI_ARUSER;\n assign S_AXI_ARREADY = M_AXI_ARREADY;\n assign M_AXI_ARVALID = S_AXI_ARVALID;\n end endgenerate // grach_pass_through;\n\n // Wiring logic for Read Data Channel \n generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through\n assign S_AXI_RID = M_AXI_RID;\n assign S_AXI_RLAST = M_AXI_RLAST;\n assign S_AXI_RUSER = M_AXI_RUSER;\n assign S_AXI_RDATA = M_AXI_RDATA;\n assign S_AXI_RRESP = M_AXI_RRESP;\n assign S_AXI_RVALID = M_AXI_RVALID;\n assign M_AXI_RREADY = S_AXI_RREADY;\n end endgenerate // grdch_pass_through;\n\n // Wiring logic for AXI Streaming\n generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through\n assign M_AXIS_TDATA = S_AXIS_TDATA;\n assign M_AXIS_TSTRB = S_AXIS_TSTRB;\n assign M_AXIS_TKEEP = S_AXIS_TKEEP;\n assign M_AXIS_TID = S_AXIS_TID;\n assign M_AXIS_TDEST = S_AXIS_TDEST;\n assign M_AXIS_TUSER = S_AXIS_TUSER;\n assign M_AXIS_TLAST = S_AXIS_TLAST;\n assign S_AXIS_TREADY = M_AXIS_TREADY;\n assign M_AXIS_TVALID = S_AXIS_TVALID;\n end endgenerate // gaxis_pass_through;\n\n\nendmodule //fifo_generator_v13_1_2\n\n\n\n/*******************************************************************************\n * Declaration of top-level module for Conventional FIFO\n ******************************************************************************/\nmodule fifo_generator_v13_1_2_CONV_VER\n #(\n parameter C_COMMON_CLOCK = 0,\n parameter C_INTERFACE_TYPE = 0,\n parameter C_EN_SAFETY_CKT = 0,\n parameter C_COUNT_TYPE = 0,\n parameter C_DATA_COUNT_WIDTH = 2,\n parameter C_DEFAULT_VALUE = \"\",\n parameter C_DIN_WIDTH = 8,\n parameter C_DOUT_RST_VAL = \"\",\n parameter C_DOUT_WIDTH = 8,\n parameter C_ENABLE_RLOCS = 0,\n parameter C_FAMILY = \"virtex7\", //Not allowed in Verilog model\n parameter C_FULL_FLAGS_RST_VAL = 1,\n parameter C_HAS_ALMOST_EMPTY = 0,\n parameter C_HAS_ALMOST_FULL = 0,\n parameter C_HAS_BACKUP = 0,\n parameter C_HAS_DATA_COUNT = 0,\n parameter C_HAS_INT_CLK = 0,\n parameter C_HAS_MEMINIT_FILE = 0,\n parameter C_HAS_OVERFLOW = 0,\n parameter C_HAS_RD_DATA_COUNT = 0,\n parameter C_HAS_RD_RST = 0,\n parameter C_HAS_RST = 0,\n parameter C_HAS_SRST = 0,\n parameter C_HAS_UNDERFLOW = 0,\n parameter C_HAS_VALID = 0,\n parameter C_HAS_WR_ACK = 0,\n parameter C_HAS_WR_DATA_COUNT = 0,\n parameter C_HAS_WR_RST = 0,\n parameter C_IMPLEMENTATION_TYPE = 0,\n parameter C_INIT_WR_PNTR_VAL = 0,\n parameter C_MEMORY_TYPE = 1,\n parameter C_MIF_FILE_NAME = \"\",\n parameter C_OPTIMIZATION_MODE = 0,\n parameter C_OVERFLOW_LOW = 0,\n parameter C_PRELOAD_LATENCY = 1,\n parameter C_PRELOAD_REGS = 0,\n parameter C_PRIM_FIFO_TYPE = \"\",\n parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n parameter C_PROG_EMPTY_TYPE = 0,\n parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,\n parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,\n parameter C_PROG_FULL_TYPE = 0,\n parameter C_RD_DATA_COUNT_WIDTH = 2,\n parameter C_RD_DEPTH = 256,\n parameter C_RD_FREQ = 1,\n parameter C_RD_PNTR_WIDTH = 8,\n parameter C_UNDERFLOW_LOW = 0,\n parameter C_USE_DOUT_RST = 0,\n parameter C_USE_ECC = 0,\n parameter C_USE_EMBEDDED_REG = 0,\n parameter C_USE_FIFO16_FLAGS = 0,\n parameter C_USE_FWFT_DATA_COUNT = 0,\n parameter C_VALID_LOW = 0,\n parameter C_WR_ACK_LOW = 0,\n parameter C_WR_DATA_COUNT_WIDTH = 2,\n parameter C_WR_DEPTH = 256,\n parameter C_WR_FREQ = 1,\n parameter C_WR_PNTR_WIDTH = 8,\n parameter C_WR_RESPONSE_LATENCY = 1,\n parameter C_MSGON_VAL = 1,\n parameter C_ENABLE_RST_SYNC = 1,\n parameter C_ERROR_INJECTION_TYPE = 0,\n parameter C_FIFO_TYPE = 0,\n parameter C_SYNCHRONIZER_STAGE = 2,\n parameter C_AXI_TYPE = 0\n )\n\n (\n input BACKUP,\n input BACKUP_MARKER,\n input CLK,\n input RST,\n input SRST,\n input WR_CLK,\n input WR_RST,\n input RD_CLK,\n input RD_RST,\n input [C_DIN_WIDTH-1:0] DIN,\n input WR_EN,\n input RD_EN,\n input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,\n input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,\n input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,\n input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,\n input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,\n input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,\n input INT_CLK,\n input INJECTDBITERR,\n input INJECTSBITERR,\n \n output [C_DOUT_WIDTH-1:0] DOUT,\n output FULL,\n output ALMOST_FULL,\n output WR_ACK,\n output OVERFLOW,\n output EMPTY,\n output ALMOST_EMPTY,\n output VALID,\n output UNDERFLOW,\n output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT,\n output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,\n output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,\n output PROG_FULL,\n output PROG_EMPTY,\n output SBITERR,\n output DBITERR,\n output wr_rst_busy_o,\n output wr_rst_busy,\n output rd_rst_busy,\n output wr_rst_i_out,\n output rd_rst_i_out\n );\n\n/*\n ******************************************************************************\n * Definition of Parameters\n ******************************************************************************\n * C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0)\n * C_COUNT_TYPE : *not used\n * C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus\n * C_DEFAULT_VALUE : *not used\n * C_DIN_WIDTH : Width of DIN bus\n * C_DOUT_RST_VAL : Reset value of DOUT\n * C_DOUT_WIDTH : Width of DOUT bus\n * C_ENABLE_RLOCS : *not used\n * C_FAMILY : not used in bhv model\n * C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1)\n * C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag\n * C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag\n * C_HAS_BACKUP : *not used\n * C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus\n * C_HAS_INT_CLK : not used in bhv model\n * C_HAS_MEMINIT_FILE : *not used\n * C_HAS_OVERFLOW : 1=Core has OVERFLOW flag\n * C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus\n * C_HAS_RD_RST : *not used\n * C_HAS_RST : 1=Core has Async Rst\n * C_HAS_SRST : 1=Core has Sync Rst\n * C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag\n * C_HAS_VALID : 1=Core has VALID flag\n * C_HAS_WR_ACK : 1=Core has WR_ACK flag\n * C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus\n * C_HAS_WR_RST : *not used\n * C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram\n * 1=Common-Clock ShiftRam\n * 2=Indep. Clocks Bram/Dram\n * 3=Virtex-4 Built-in\n * 4=Virtex-5 Built-in\n * C_INIT_WR_PNTR_VAL : *not used\n * C_MEMORY_TYPE : 1=Block RAM\n * 2=Distributed RAM\n * 3=Shift RAM\n * 4=Built-in FIFO\n * C_MIF_FILE_NAME : *not used\n * C_OPTIMIZATION_MODE : *not used\n * C_OVERFLOW_LOW : 1=OVERFLOW active low\n * C_PRELOAD_LATENCY : Latency of read: 0, 1, 2\n * C_PRELOAD_REGS : 1=Use output registers\n * C_PRIM_FIFO_TYPE : not used in bhv model\n * C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold\n * C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold\n * C_PROG_EMPTY_TYPE : 0=No programmable empty\n * 1=Single prog empty thresh constant\n * 2=Multiple prog empty thresh constants\n * 3=Single prog empty thresh input\n * 4=Multiple prog empty thresh inputs\n * C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold\n * C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold\n * C_PROG_FULL_TYPE : 0=No prog full\n * 1=Single prog full thresh constant\n * 2=Multiple prog full thresh constants\n * 3=Single prog full thresh input\n * 4=Multiple prog full thresh inputs\n * C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus\n * C_RD_DEPTH : Depth of read interface (2^N)\n * C_RD_FREQ : not used in bhv model\n * C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH)\n * C_UNDERFLOW_LOW : 1=UNDERFLOW active low\n * C_USE_DOUT_RST : 1=Resets DOUT on RST\n * C_USE_ECC : Used for error injection purpose\n * C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register\n * C_USE_FIFO16_FLAGS : not used in bhv model\n * C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count\n * C_VALID_LOW : 1=VALID active low\n * C_WR_ACK_LOW : 1=WR_ACK active low\n * C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus\n * C_WR_DEPTH : Depth of write interface (2^N)\n * C_WR_FREQ : not used in bhv model\n * C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH)\n * C_WR_RESPONSE_LATENCY : *not used\n * C_MSGON_VAL : *not used by bhv model\n * C_ENABLE_RST_SYNC : 0 = Use WR_RST & RD_RST\n * 1 = Use RST\n * C_ERROR_INJECTION_TYPE : 0 = No error injection\n * 1 = Single bit error injection only\n * 2 = Double bit error injection only\n * 3 = Single and double bit error injection\n ******************************************************************************\n * Definition of Ports\n ******************************************************************************\n * BACKUP : Not used\n * BACKUP_MARKER: Not used\n * CLK : Clock\n * DIN : Input data bus\n * PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag\n * PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag\n * PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag\n * PROG_FULL_THRESH : Threshold for Programmable Full Flag\n * PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag\n * PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag\n * RD_CLK : Read Domain Clock\n * RD_EN : Read enable\n * RD_RST : Read Reset\n * RST : Asynchronous Reset\n * SRST : Synchronous Reset\n * WR_CLK : Write Domain Clock\n * WR_EN : Write enable\n * WR_RST : Write Reset\n * INT_CLK : Internal Clock\n * INJECTSBITERR: Inject Signle bit error\n * INJECTDBITERR: Inject Double bit error\n * ALMOST_EMPTY : One word remaining in FIFO\n * ALMOST_FULL : One empty space remaining in FIFO\n * DATA_COUNT : Number of data words in fifo( synchronous to CLK)\n * DOUT : Output data bus\n * EMPTY : Empty flag\n * FULL : Full flag\n * OVERFLOW : Last write rejected\n * PROG_EMPTY : Programmable Empty Flag\n * PROG_FULL : Programmable Full Flag\n * RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)\n * UNDERFLOW : Last read rejected\n * VALID : Last read acknowledged, DOUT bus VALID\n * WR_ACK : Last write acknowledged\n * WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)\n * SBITERR : Single Bit ECC Error Detected\n * DBITERR : Double Bit ECC Error Detected\n ******************************************************************************\n */\n\n //----------------------------------------------------------------------------\n //- Internal Signals for delayed input signals\n //- All the input signals except Clock are delayed by 100 ps and then given to\n //- the models.\n //----------------------------------------------------------------------------\n \n reg rst_delayed ;\n reg empty_fb ;\n reg srst_delayed ;\n reg wr_rst_delayed ;\n reg rd_rst_delayed ;\n reg wr_en_delayed ;\n reg rd_en_delayed ;\n reg [C_DIN_WIDTH-1:0] din_delayed ;\n reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_delayed ;\n reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert_delayed ;\n reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate_delayed ;\n reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_delayed ;\n reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert_delayed ;\n reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate_delayed ;\n reg injectdbiterr_delayed ;\n reg injectsbiterr_delayed ;\n wire empty_p0_out;\n\n always @* rst_delayed <= #`TCQ RST ;\n always @* empty_fb <= #`TCQ empty_p0_out ;\n always @* srst_delayed <= #`TCQ SRST ; \n always @* wr_rst_delayed <= #`TCQ WR_RST ; \n always @* rd_rst_delayed <= #`TCQ RD_RST ; \n always @* din_delayed <= #`TCQ DIN ; \n always @* wr_en_delayed <= #`TCQ WR_EN ; \n always @* rd_en_delayed <= #`TCQ RD_EN ; \n always @* prog_empty_thresh_delayed <= #`TCQ PROG_EMPTY_THRESH ; \n always @* prog_empty_thresh_assert_delayed <= #`TCQ PROG_EMPTY_THRESH_ASSERT ; \n always @* prog_empty_thresh_negate_delayed <= #`TCQ PROG_EMPTY_THRESH_NEGATE ; \n always @* prog_full_thresh_delayed <= #`TCQ PROG_FULL_THRESH ; \n always @* prog_full_thresh_assert_delayed <= #`TCQ PROG_FULL_THRESH_ASSERT ; \n always @* prog_full_thresh_negate_delayed <= #`TCQ PROG_FULL_THRESH_NEGATE ; \n always @* injectdbiterr_delayed <= #`TCQ INJECTDBITERR ; \n always @* injectsbiterr_delayed <= #`TCQ INJECTSBITERR ; \n\n /*****************************************************************************\n * Derived parameters\n ****************************************************************************/\n //There are 2 Verilog behavioral models\n // 0 = Common-Clock FIFO/ShiftRam FIFO\n // 1 = Independent Clocks FIFO\n // 2 = Low Latency Synchronous FIFO\n // 3 = Low Latency Asynchronous FIFO\n localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 :\n (C_IMPLEMENTATION_TYPE == 2) ? 1 : 0;\n localparam IS_8SERIES = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\") ? 1 : 0;\n\n //Internal reset signals\n reg rd_rst_asreg = 0;\n wire rd_rst_asreg_d1;\n wire rd_rst_asreg_d2;\n reg rd_rst_asreg_d3 = 0;\n reg rd_rst_reg = 0;\n wire rd_rst_comb;\n reg wr_rst_d0 = 0;\n reg wr_rst_d1 = 0;\n reg wr_rst_d2 = 0;\n reg rd_rst_d0 = 0;\n reg rd_rst_d1 = 0;\n reg rd_rst_d2 = 0;\n reg rd_rst_d3 = 0;\n reg wrrst_done = 0;\n reg rdrst_done = 0;\n reg wr_rst_asreg = 0;\n wire wr_rst_asreg_d1;\n wire wr_rst_asreg_d2;\n reg wr_rst_asreg_d3 = 0;\n reg rd_rst_wr_d0 = 0;\n reg rd_rst_wr_d1 = 0;\n reg rd_rst_wr_d2 = 0;\n reg wr_rst_reg = 0;\n reg rst_active_i = 1'b1;\n reg rst_delayed_d1 = 1'b1;\n reg rst_delayed_d2 = 1'b1;\n wire wr_rst_comb;\n wire wr_rst_i;\n wire rd_rst_i;\n wire rst_i;\n\n //Internal reset signals\n reg rst_asreg = 0;\n reg srst_asreg = 0;\n wire rst_asreg_d1;\n wire rst_asreg_d2;\n reg srst_asreg_d1 = 0;\n reg srst_asreg_d2 = 0;\n reg rst_reg = 0;\n reg srst_reg = 0;\n wire rst_comb;\n wire srst_comb;\n reg rst_full_gen_i = 0;\n reg rst_full_ff_i = 0;\n reg [2:0] sckt_ff0_bsy_o_i = {3{1'b0}};\n \n wire RD_CLK_P0_IN;\n wire RST_P0_IN;\n wire RD_EN_FIFO_IN;\n wire RD_EN_P0_IN;\n\n wire ALMOST_EMPTY_FIFO_OUT;\n wire ALMOST_FULL_FIFO_OUT;\n wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT;\n wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT;\n wire EMPTY_FIFO_OUT;\n wire fifo_empty_fb;\n wire FULL_FIFO_OUT;\n wire OVERFLOW_FIFO_OUT;\n wire PROG_EMPTY_FIFO_OUT;\n wire PROG_FULL_FIFO_OUT;\n wire VALID_FIFO_OUT;\n wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT;\n wire UNDERFLOW_FIFO_OUT;\n wire WR_ACK_FIFO_OUT;\n wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT;\n\n\n //***************************************************************************\n // Internal Signals\n // The core uses either the internal_ wires or the preload0_ wires depending\n // on whether the core uses Preload0 or not.\n // When using preload0, the internal signals connect the internal core to\n // the preload logic, and the external core's interfaces are tied to the\n // preload0 signals from the preload logic.\n //***************************************************************************\n wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT;\n wire VALID_P0_OUT;\n wire EMPTY_P0_OUT;\n wire ALMOSTEMPTY_P0_OUT;\n reg EMPTY_P0_OUT_Q;\n reg ALMOSTEMPTY_P0_OUT_Q;\n wire UNDERFLOW_P0_OUT;\n wire RDEN_P0_OUT;\n wire [C_DOUT_WIDTH-1:0] DATA_P0_IN;\n wire EMPTY_P0_IN;\n reg [31:0] DATA_COUNT_FWFT;\n reg SS_FWFT_WR ;\n reg SS_FWFT_RD ;\n\n wire sbiterr_fifo_out;\n wire dbiterr_fifo_out;\n wire inject_sbit_err;\n wire inject_dbit_err;\n wire safety_ckt_wr_rst;\n wire safety_ckt_rd_rst;\n reg sckt_wr_rst_i_q = 1'b0;\n \n wire w_fab_read_data_valid_i;\n wire w_read_data_valid_i;\n wire w_ram_valid_i;\n // Assign 0 if not selected to avoid 'X' propogation to S/DBITERR.\n assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ?\n injectsbiterr_delayed : 0;\n assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ?\n injectdbiterr_delayed : 0;\n \n assign wr_rst_i_out = wr_rst_i;\n assign rd_rst_i_out = rd_rst_i;\n assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2];\n generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o\n wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK;\n always @ (posedge clk_i)\n sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy}; \n end endgenerate \n// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL\n// parameter (1=Independent Clocks, 0=Common Clock)\n\n localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL;\ngenerate\ncase (C_VERILOG_IMPL)\n0 : begin : block1\n //Common Clock Behavioral Model\n fifo_generator_v13_1_2_bhv_ver_ss\n #(\n .C_FAMILY (C_FAMILY),\n .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH), \n .C_DIN_WIDTH (C_DIN_WIDTH), \n .C_DOUT_RST_VAL (C_DOUT_RST_VAL), \n .C_DOUT_WIDTH (C_DOUT_WIDTH), \n .C_FULL_FLAGS_RST_VAL (FULL_FLAGS_RST_VAL), \n .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY), \n .C_HAS_ALMOST_FULL ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL), \n .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT), \n .C_HAS_OVERFLOW (C_HAS_OVERFLOW), \n .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), \n .C_HAS_RST (C_HAS_RST), \n .C_HAS_SRST (C_HAS_SRST), \n .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), \n .C_HAS_VALID (C_HAS_VALID), \n .C_HAS_WR_ACK (C_HAS_WR_ACK), \n .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), \n .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE), \n .C_MEMORY_TYPE (C_MEMORY_TYPE), \n .C_OVERFLOW_LOW (C_OVERFLOW_LOW), \n .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY), \n .C_PRELOAD_REGS (C_PRELOAD_REGS), \n .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE), \n .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL), \n .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL), \n .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE), \n .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH), \n .C_RD_DEPTH (C_RD_DEPTH), \n .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), \n .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), \n .C_USE_DOUT_RST (C_USE_DOUT_RST), \n .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),\n .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), \n .C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT), \n .C_VALID_LOW (C_VALID_LOW), \n .C_WR_ACK_LOW (C_WR_ACK_LOW), \n .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), \n .C_WR_DEPTH (C_WR_DEPTH), \n .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), \n .C_USE_ECC (C_USE_ECC), \n .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), \n .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),\n .C_FIFO_TYPE (C_FIFO_TYPE) \n )\n gen_ss\n (\n .SAFETY_CKT_WR_RST (safety_ckt_wr_rst),\n .CLK (CLK),\n .RST (rst_i),\n .SRST (srst_delayed),\n .RST_FULL_GEN (rst_full_gen_i),\n .RST_FULL_FF (rst_full_ff_i),\n .DIN (din_delayed),\n .WR_EN (wr_en_delayed),\n .RD_EN (RD_EN_FIFO_IN),\n .RD_EN_USER (rd_en_delayed),\n .USER_EMPTY_FB (empty_fb),\n .PROG_EMPTY_THRESH (prog_empty_thresh_delayed),\n .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n .PROG_FULL_THRESH (prog_full_thresh_delayed),\n .PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),\n .PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),\n .INJECTSBITERR (inject_sbit_err),\n .INJECTDBITERR (inject_dbit_err),\n .DOUT (DOUT_FIFO_OUT),\n .FULL (FULL_FIFO_OUT),\n .ALMOST_FULL (ALMOST_FULL_FIFO_OUT),\n .WR_ACK (WR_ACK_FIFO_OUT),\n .OVERFLOW (OVERFLOW_FIFO_OUT),\n .EMPTY (EMPTY_FIFO_OUT),\n .EMPTY_FB (fifo_empty_fb),\n .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),\n .VALID (VALID_FIFO_OUT),\n .UNDERFLOW (UNDERFLOW_FIFO_OUT),\n .DATA_COUNT (DATA_COUNT_FIFO_OUT),\n .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),\n .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),\n .PROG_FULL (PROG_FULL_FIFO_OUT),\n .PROG_EMPTY (PROG_EMPTY_FIFO_OUT),\n .WR_RST_BUSY (wr_rst_busy),\n .RD_RST_BUSY (rd_rst_busy),\n .SBITERR (sbiterr_fifo_out),\n .DBITERR (dbiterr_fifo_out)\n );\nend\n1 : begin : block1\n //Independent Clocks Behavioral Model\n fifo_generator_v13_1_2_bhv_ver_as\n #(\n .C_FAMILY (C_FAMILY),\n .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),\n .C_DIN_WIDTH (C_DIN_WIDTH),\n .C_DOUT_RST_VAL (C_DOUT_RST_VAL),\n .C_DOUT_WIDTH (C_DOUT_WIDTH),\n .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),\n .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),\n .C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),\n .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),\n .C_HAS_OVERFLOW (C_HAS_OVERFLOW),\n .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),\n .C_HAS_RST (C_HAS_RST),\n .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),\n .C_HAS_VALID (C_HAS_VALID),\n .C_HAS_WR_ACK (C_HAS_WR_ACK),\n .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),\n .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),\n .C_MEMORY_TYPE (C_MEMORY_TYPE),\n .C_OVERFLOW_LOW (C_OVERFLOW_LOW),\n .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),\n .C_PRELOAD_REGS (C_PRELOAD_REGS),\n .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),\n .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),\n .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),\n .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),\n .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),\n .C_RD_DEPTH (C_RD_DEPTH),\n .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),\n .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),\n .C_USE_DOUT_RST (C_USE_DOUT_RST),\n .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),\n .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), \n .C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),\n .C_VALID_LOW (C_VALID_LOW),\n .C_WR_ACK_LOW (C_WR_ACK_LOW),\n .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),\n .C_WR_DEPTH (C_WR_DEPTH),\n .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),\n .C_USE_ECC (C_USE_ECC),\n .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),\n .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),\n .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)\n )\n gen_as\n (\n .SAFETY_CKT_WR_RST (safety_ckt_wr_rst),\n .SAFETY_CKT_RD_RST (safety_ckt_rd_rst),\n .WR_CLK (WR_CLK),\n .RD_CLK (RD_CLK),\n .RST (rst_i),\n .RST_FULL_GEN (rst_full_gen_i),\n .RST_FULL_FF (rst_full_ff_i),\n .WR_RST (wr_rst_i),\n .RD_RST (rd_rst_i),\n .DIN (din_delayed),\n .WR_EN (wr_en_delayed),\n .RD_EN (RD_EN_FIFO_IN),\n .RD_EN_USER (rd_en_delayed),\n .PROG_EMPTY_THRESH (prog_empty_thresh_delayed),\n .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n .PROG_FULL_THRESH (prog_full_thresh_delayed),\n .PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),\n .PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),\n .INJECTSBITERR (inject_sbit_err),\n .INJECTDBITERR (inject_dbit_err),\n .USER_EMPTY_FB (EMPTY_P0_OUT),\n .DOUT (DOUT_FIFO_OUT),\n .FULL (FULL_FIFO_OUT),\n .ALMOST_FULL (ALMOST_FULL_FIFO_OUT),\n .WR_ACK (WR_ACK_FIFO_OUT),\n .OVERFLOW (OVERFLOW_FIFO_OUT),\n .EMPTY (EMPTY_FIFO_OUT),\n .EMPTY_FB (fifo_empty_fb),\n .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),\n .VALID (VALID_FIFO_OUT),\n .UNDERFLOW (UNDERFLOW_FIFO_OUT),\n .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),\n .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),\n .PROG_FULL (PROG_FULL_FIFO_OUT),\n .PROG_EMPTY (PROG_EMPTY_FIFO_OUT),\n .SBITERR (sbiterr_fifo_out),\n .fab_read_data_valid_i (w_fab_read_data_valid_i),\n .read_data_valid_i (w_read_data_valid_i),\n .ram_valid_i (w_ram_valid_i),\n .DBITERR (dbiterr_fifo_out)\n );\nend\n\n2 : begin : ll_afifo_inst\n fifo_generator_v13_1_2_beh_ver_ll_afifo\n #(\n .C_DIN_WIDTH (C_DIN_WIDTH),\n .C_DOUT_RST_VAL (C_DOUT_RST_VAL),\n .C_DOUT_WIDTH (C_DOUT_WIDTH),\n .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),\n .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),\n .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),\n .C_RD_DEPTH (C_RD_DEPTH),\n .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),\n .C_USE_DOUT_RST (C_USE_DOUT_RST),\n .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),\n .C_WR_DEPTH (C_WR_DEPTH),\n .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),\n .C_FIFO_TYPE (C_FIFO_TYPE)\n )\n gen_ll_afifo\n (\n .DIN (din_delayed),\n .RD_CLK (RD_CLK),\n .RD_EN (rd_en_delayed),\n .WR_RST (wr_rst_i),\n .RD_RST (rd_rst_i),\n .WR_CLK (WR_CLK),\n .WR_EN (wr_en_delayed),\n .DOUT (DOUT),\n .EMPTY (EMPTY),\n .FULL (FULL)\n );\nend\ndefault : begin : block1\n //Independent Clocks Behavioral Model\n fifo_generator_v13_1_2_bhv_ver_as\n #(\n .C_FAMILY (C_FAMILY),\n .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),\n .C_DIN_WIDTH (C_DIN_WIDTH),\n .C_DOUT_RST_VAL (C_DOUT_RST_VAL),\n .C_DOUT_WIDTH (C_DOUT_WIDTH),\n .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),\n .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),\n .C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),\n .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),\n .C_HAS_OVERFLOW (C_HAS_OVERFLOW),\n .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),\n .C_HAS_RST (C_HAS_RST),\n .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),\n .C_HAS_VALID (C_HAS_VALID),\n .C_HAS_WR_ACK (C_HAS_WR_ACK),\n .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),\n .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),\n .C_MEMORY_TYPE (C_MEMORY_TYPE),\n .C_OVERFLOW_LOW (C_OVERFLOW_LOW),\n .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),\n .C_PRELOAD_REGS (C_PRELOAD_REGS),\n .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),\n .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),\n .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),\n .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),\n .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),\n .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),\n .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),\n .C_RD_DEPTH (C_RD_DEPTH),\n .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),\n .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),\n .C_USE_DOUT_RST (C_USE_DOUT_RST),\n .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),\n .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),\n .C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),\n .C_VALID_LOW (C_VALID_LOW),\n .C_WR_ACK_LOW (C_WR_ACK_LOW),\n .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),\n .C_WR_DEPTH (C_WR_DEPTH),\n .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),\n .C_USE_ECC (C_USE_ECC),\n .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),\n .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),\n .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)\n )\n gen_as\n (\n .SAFETY_CKT_WR_RST (safety_ckt_wr_rst),\n .SAFETY_CKT_RD_RST (safety_ckt_rd_rst),\n .WR_CLK (WR_CLK),\n .RD_CLK (RD_CLK),\n .RST (rst_i),\n .RST_FULL_GEN (rst_full_gen_i),\n .RST_FULL_FF (rst_full_ff_i),\n .WR_RST (wr_rst_i),\n .RD_RST (rd_rst_i),\n .DIN (din_delayed),\n .WR_EN (wr_en_delayed),\n .RD_EN (RD_EN_FIFO_IN),\n .RD_EN_USER (rd_en_delayed),\n .PROG_EMPTY_THRESH (prog_empty_thresh_delayed),\n .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),\n .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),\n .PROG_FULL_THRESH (prog_full_thresh_delayed),\n .PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),\n .PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),\n .INJECTSBITERR (inject_sbit_err),\n .INJECTDBITERR (inject_dbit_err),\n .USER_EMPTY_FB (EMPTY_P0_OUT),\n .DOUT (DOUT_FIFO_OUT),\n .FULL (FULL_FIFO_OUT),\n .ALMOST_FULL (ALMOST_FULL_FIFO_OUT),\n .WR_ACK (WR_ACK_FIFO_OUT),\n .OVERFLOW (OVERFLOW_FIFO_OUT),\n .EMPTY (EMPTY_FIFO_OUT),\n .EMPTY_FB (fifo_empty_fb),\n .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),\n .VALID (VALID_FIFO_OUT),\n .UNDERFLOW (UNDERFLOW_FIFO_OUT),\n .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),\n .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),\n .PROG_FULL (PROG_FULL_FIFO_OUT),\n .PROG_EMPTY (PROG_EMPTY_FIFO_OUT),\n .SBITERR (sbiterr_fifo_out),\n .DBITERR (dbiterr_fifo_out)\n );\nend\n\nendcase\nendgenerate\n\n\n //**************************************************************************\n // Connect Internal Signals\n // (Signals labeled internal_*)\n // In the normal case, these signals tie directly to the FIFO's inputs and\n // outputs.\n // In the case of Preload Latency 0 or 1, there are intermediate\n // signals between the internal FIFO and the preload logic.\n //**************************************************************************\n \n \n //***********************************************\n // If First-Word Fall-Through, instantiate\n // the preload0 (FWFT) module\n //***********************************************\n wire rd_en_to_fwft_fifo;\n wire sbiterr_fwft;\n wire dbiterr_fwft;\n wire [C_DOUT_WIDTH-1:0] dout_fwft;\n wire empty_fwft;\n wire rd_en_fifo_in;\n wire stage2_reg_en_i;\n wire [1:0] valid_stages_i;\n wire rst_fwft;\n //wire empty_p0_out;\n reg [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1;\n\n localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;\n localparam IS_PKT_FIFO = (C_FIFO_TYPE == 1) ? 1 : 0;\n localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0;\n assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0;\n\n generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2\n\n\n fifo_generator_v13_1_2_bhv_ver_preload0\n #(\n .C_DOUT_RST_VAL (C_DOUT_RST_VAL),\n .C_DOUT_WIDTH (C_DOUT_WIDTH),\n .C_HAS_RST (C_HAS_RST),\n .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),\n .C_HAS_SRST (C_HAS_SRST),\n .C_USE_DOUT_RST (C_USE_DOUT_RST),\n .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),\n .C_USE_ECC (C_USE_ECC),\n .C_USERVALID_LOW (C_VALID_LOW),\n .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),\n .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),\n .C_MEMORY_TYPE (C_MEMORY_TYPE),\n .C_FIFO_TYPE (C_FIFO_TYPE)\n )\n fgpl0\n (\n .SAFETY_CKT_RD_RST(safety_ckt_rd_rst),\n .RD_CLK (RD_CLK_P0_IN),\n .RD_RST (RST_P0_IN),\n .SRST (srst_delayed),\n .WR_RST_BUSY (wr_rst_busy),\n .RD_RST_BUSY (rd_rst_busy),\n .RD_EN (RD_EN_P0_IN),\n .FIFOEMPTY (EMPTY_P0_IN),\n .FIFODATA (DATA_P0_IN),\n .FIFOSBITERR (sbiterr_fifo_out),\n .FIFODBITERR (dbiterr_fifo_out),\n // Output\n .USERDATA (dout_fwft),\n .USERVALID (VALID_P0_OUT),\n .USEREMPTY (empty_fwft),\n .USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT),\n .USERUNDERFLOW (UNDERFLOW_P0_OUT),\n .RAMVALID (),\n .FIFORDEN (rd_en_fifo_in),\n .USERSBITERR (sbiterr_fwft),\n .USERDBITERR (dbiterr_fwft),\n .STAGE2_REG_EN (stage2_reg_en_i),\n .fab_read_data_valid_i_o (w_fab_read_data_valid_i),\n .read_data_valid_i_o (w_read_data_valid_i),\n .ram_valid_i_o (w_ram_valid_i),\n .VALID_STAGES (valid_stages_i)\n );\n\n \n //***********************************************\n // Connect inputs to preload (FWFT) module\n //***********************************************\n //Connect the RD_CLK of the Preload (FWFT) module to CLK if we \n // have a common-clock FIFO, or RD_CLK if we have an \n // independent clock FIFO\n assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK);\n assign RST_P0_IN = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0;\n assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;\n assign EMPTY_P0_IN = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT;\n assign DATA_P0_IN = DOUT_FIFO_OUT;\n \n //***********************************************\n // Connect outputs from preload (FWFT) module\n //***********************************************\n assign VALID = VALID_P0_OUT ;\n assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT;\n assign UNDERFLOW = UNDERFLOW_P0_OUT ;\n \n assign RD_EN_FIFO_IN = rd_en_fifo_in;\n \n \n //***********************************************\n // Create DATA_COUNT from First-Word Fall-Through\n // data count\n //***********************************************\n assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT:\n (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] : \n DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1]; \n \n //***********************************************\n // Create DATA_COUNT from First-Word Fall-Through\n // data count\n //***********************************************\n always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin\n if (RST_P0_IN) begin\n EMPTY_P0_OUT_Q <= 1;\n ALMOSTEMPTY_P0_OUT_Q <= 1;\n end else begin\n EMPTY_P0_OUT_Q <= #`TCQ empty_p0_out;\n// EMPTY_P0_OUT_Q <= #`TCQ EMPTY_FIFO_OUT;\n ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT;\n end\n end //always\n \n \n //***********************************************\n // logic for common-clock data count when FWFT is selected\n //***********************************************\n initial begin\n SS_FWFT_RD = 1'b0;\n DATA_COUNT_FWFT = 0 ;\n SS_FWFT_WR = 1'b0 ;\n end //initial\n \n \n //***********************************************\n // common-clock data count is implemented as an\n // up-down counter. SS_FWFT_WR and SS_FWFT_RD\n // are the up/down enables for the counter.\n //***********************************************\n always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin\n if (C_VALID_LOW == 1) begin\n SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ;\n end else begin\n SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ;\n end\n SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ;\n end \n\n //***********************************************\n // common-clock data count is implemented as an\n // up-down counter for FWFT. This always block \n // calculates the counter.\n //***********************************************\n always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin\n if (RST_P0_IN) begin\n DATA_COUNT_FWFT <= 0;\n end else begin\n //if (srst_delayed && (C_HAS_SRST == 1) ) begin\n if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin\n DATA_COUNT_FWFT <= #`TCQ 0;\n end else begin\n case ( {SS_FWFT_WR, SS_FWFT_RD})\n 2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;\n 2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ;\n 2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ;\n 2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;\n endcase \n end //if SRST\n end //IF RST\n end //always\n\n end endgenerate // : block2\n\n // AXI Streaming Packet FIFO\n reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count = 0;\n reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count = 0;\n reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_plus1 = 0;\n reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_reg = 0;\n reg partial_packet = 0;\n reg stage1_eop_d1 = 0;\n reg rd_en_fifo_in_d1 = 0;\n reg eop_at_stage2 = 0;\n reg ram_pkt_empty = 0;\n reg ram_pkt_empty_d1 = 0;\n\n wire [C_DOUT_WIDTH-1:0] dout_p0_out;\n wire packet_empty_wr;\n wire wr_rst_fwft_pkt_fifo;\n wire dummy_wr_eop;\n wire ram_wr_en_pkt_fifo;\n wire wr_eop;\n wire ram_rd_en_compare;\n wire stage1_eop;\n wire pkt_ready_to_read;\n wire rd_en_2_stage2;\n\n // Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)\n // When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP\n // When dummy WR_EOP is high, mask the actual EOP to avoid double increment of\n // write packet count\n generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop\n always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin \n if (wr_rst_fwft_pkt_fifo)\n partial_packet <= 1'b0;\n else begin\n if (srst_delayed | wr_rst_busy | rd_rst_busy)\n partial_packet <= #`TCQ 1'b0;\n else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]))\n partial_packet <= #`TCQ 1'b1;\n else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo)\n partial_packet <= #`TCQ 1'b0;\n end\n end\n end endgenerate // gdummy_wr_eop\n\n generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin // gpkt_fifo_fwft\n assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0;\n assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet);\n assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1];\n \n always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n if (rst_fwft) begin\n stage1_eop_d1 <= 1'b0;\n rd_en_fifo_in_d1 <= 1'b0;\n end else begin\n if (srst_delayed | wr_rst_busy | rd_rst_busy) begin\n stage1_eop_d1 <= #`TCQ 1'b0;\n rd_en_fifo_in_d1 <= #`TCQ 1'b0;\n end else begin\n stage1_eop_d1 <= #`TCQ stage1_eop;\n rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in;\n end\n end\n end\n assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1;\n assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT);\n assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop);\n assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop;\n\n\n fifo_generator_v13_1_2_bhv_ver_preload0\n #(\n .C_DOUT_RST_VAL (C_DOUT_RST_VAL),\n .C_DOUT_WIDTH (C_DOUT_WIDTH),\n .C_HAS_RST (C_HAS_RST),\n .C_HAS_SRST (C_HAS_SRST),\n .C_USE_DOUT_RST (C_USE_DOUT_RST),\n .C_USE_ECC (C_USE_ECC),\n .C_USERVALID_LOW (C_VALID_LOW),\n .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),\n .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),\n .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),\n .C_MEMORY_TYPE (C_MEMORY_TYPE),\n .C_FIFO_TYPE (2) // Enable low latency fwft logic\n )\n pkt_fifo_fwft\n (\n .SAFETY_CKT_RD_RST(safety_ckt_rd_rst),\n .RD_CLK (RD_CLK_P0_IN),\n .RD_RST (rst_fwft),\n .SRST (srst_delayed),\n .WR_RST_BUSY (wr_rst_busy),\n .RD_RST_BUSY (rd_rst_busy),\n .RD_EN (rd_en_delayed),\n .FIFOEMPTY (pkt_ready_to_read),\n .FIFODATA (dout_fwft),\n .FIFOSBITERR (sbiterr_fwft),\n .FIFODBITERR (dbiterr_fwft),\n // Output\n .USERDATA (dout_p0_out),\n .USERVALID (),\n .USEREMPTY (empty_p0_out),\n .USERALMOSTEMPTY (),\n .USERUNDERFLOW (),\n .RAMVALID (),\n .FIFORDEN (rd_en_2_stage2),\n .USERSBITERR (SBITERR),\n .USERDBITERR (DBITERR),\n .STAGE2_REG_EN (),\n .VALID_STAGES ()\n );\n\n assign pkt_ready_to_read = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2));\n assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2;\n\n always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n if (rst_fwft)\n eop_at_stage2 <= 1'b0;\n else if (stage2_reg_en_i)\n eop_at_stage2 <= #`TCQ stage1_eop;\n end\n\n //---------------------------------------------------------------------------\n // Write and Read Packet Count\n //---------------------------------------------------------------------------\n always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin \n if (wr_rst_fwft_pkt_fifo)\n wr_pkt_count <= 0;\n else if (srst_delayed | wr_rst_busy | rd_rst_busy)\n wr_pkt_count <= #`TCQ 0;\n else if (wr_eop)\n wr_pkt_count <= #`TCQ wr_pkt_count + 1;\n end\n \n end endgenerate // gpkt_fifo_fwft\n\n assign DOUT = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out;\n assign EMPTY = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out;\n\n generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt\n always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n if (rst_fwft) begin\n rd_pkt_count <= 0;\n rd_pkt_count_plus1 <= 1;\n end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin\n rd_pkt_count <= #`TCQ 0;\n rd_pkt_count_plus1 <= #`TCQ 1;\n end else if (stage2_reg_en_i && stage1_eop) begin\n rd_pkt_count <= #`TCQ rd_pkt_count + 1;\n rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1;\n end\n end\n\n always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n if (rst_fwft) begin\n ram_pkt_empty <= 1'b1;\n ram_pkt_empty_d1 <= 1'b1;\n end else if (SRST | wr_rst_busy | rd_rst_busy) begin\n ram_pkt_empty <= #`TCQ 1'b1;\n ram_pkt_empty_d1 <= #`TCQ 1'b1;\n end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin\n ram_pkt_empty <= #`TCQ 1'b0;\n ram_pkt_empty_d1 <= #`TCQ 1'b0;\n end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin\n ram_pkt_empty <= #`TCQ 1'b1;\n end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin\n ram_pkt_empty_d1 <= #`TCQ 1'b1;\n end\n end\n end endgenerate //grss_pkt_cnt\n \n localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH;\n reg [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0;\n reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_b2g = 0;\n wire [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_rd;\n generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt\n // Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay\n always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin\n if (wr_rst_fwft_pkt_fifo)\n wr_pkt_count_b2g <= 0;\n else\n wr_pkt_count_b2g <= #`TCQ wr_pkt_count;\n end\n\n // Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay\n always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n if (rst_fwft)\n wr_pkt_count_q <= 0;\n else\n wr_pkt_count_q <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g};\n end\n\n always @* begin\n if (stage1_eop)\n rd_pkt_count <= rd_pkt_count_reg + 1;\n else\n rd_pkt_count <= rd_pkt_count_reg;\n end\n\n assign wr_pkt_count_rd = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH];\n\n always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n if (rst_fwft)\n rd_pkt_count_reg <= 0;\n else if (rd_en_fifo_in)\n rd_pkt_count_reg <= #`TCQ rd_pkt_count;\n end\n\n always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin \n if (rst_fwft) begin\n ram_pkt_empty <= 1'b1;\n ram_pkt_empty_d1 <= 1'b1;\n end else if (rd_pkt_count != wr_pkt_count_rd) begin\n ram_pkt_empty <= #`TCQ 1'b0;\n ram_pkt_empty_d1 <= #`TCQ 1'b0;\n end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin\n ram_pkt_empty <= #`TCQ 1'b1;\n end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin\n ram_pkt_empty_d1 <= #`TCQ 1'b1;\n end\n end\n\n // Synchronize the empty in write domain\n always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin\n if (wr_rst_fwft_pkt_fifo)\n pkt_empty_sync <= 'b1;\n else\n pkt_empty_sync <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out};\n end\n\n end endgenerate //gras_pkt_cnt\n\n generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO\n\n //***********************************************\n // If NOT First-Word Fall-Through, wire the outputs\n // of the internal _ss or _as FIFO directly to the\n // output, and do not instantiate the preload0\n // module.\n //***********************************************\n\n assign RD_CLK_P0_IN = 0;\n assign RST_P0_IN = 0;\n assign RD_EN_P0_IN = 0;\n\n assign RD_EN_FIFO_IN = rd_en_delayed;\n\n assign DOUT = DOUT_FIFO_OUT;\n assign DATA_P0_IN = 0;\n assign VALID = VALID_FIFO_OUT;\n assign EMPTY = EMPTY_FIFO_OUT;\n assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT;\n assign EMPTY_P0_IN = 0;\n assign UNDERFLOW = UNDERFLOW_FIFO_OUT;\n assign DATA_COUNT = DATA_COUNT_FIFO_OUT;\n assign SBITERR = sbiterr_fifo_out;\n assign DBITERR = dbiterr_fifo_out;\n\n end endgenerate // STD_FIFO\n\n generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO\n assign empty_p0_out = empty_fwft;\n assign SBITERR = sbiterr_fwft;\n assign DBITERR = dbiterr_fwft;\n assign DOUT = dout_fwft;\n assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;\n\n end endgenerate // NO_PKT_FIFO\n\n //***********************************************\n // Connect user flags to internal signals\n //***********************************************\n \n //If we are using extra logic for the FWFT data count, then override the\n //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n //RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY.\n generate\n if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3\n if (C_COMMON_CLOCK == 0) begin : block_ic\n assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);\n end //block_ic\n else begin\n assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n end \n end //block3\n endgenerate\n \n //If we are using extra logic for the FWFT data count, then override the\n //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.\n generate\n if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30\n if (C_COMMON_CLOCK == 0) begin : block_ic\n assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT);\n end \n else begin\n assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n end \n end //block30\n endgenerate\n\n\n \n //If we are using extra logic for the FWFT data count, then override the\n //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.\n //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.\n generate\n if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both\n if (C_COMMON_CLOCK == 0) begin : block_ic_both\n assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT));\n end \n else begin\n assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n end \n end //block30_both\n endgenerate\n\n generate\n if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both\n if (C_COMMON_CLOCK == 0) begin : block_ic_both\n assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT));\n end //block_ic_both\n else begin\n assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n end \n end //block3_both\n endgenerate\n\n\n //If we are not using extra logic for the FWFT data count,\n //then connect RD_DATA_COUNT to the RD_DATA_COUNT from the\n //internal FIFO instance \n generate\n if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31\n assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;\n end\n endgenerate\n\n //Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal\n //FIFO instance\n generate\n if (C_USE_FWFT_DATA_COUNT==1) begin : block4\n assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;\n end\n else begin : block4\n assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;\n end\n endgenerate\n\n\n //Connect other flags to the internal FIFO instance\n assign FULL = FULL_FIFO_OUT;\n assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT;\n assign WR_ACK = WR_ACK_FIFO_OUT;\n assign OVERFLOW = OVERFLOW_FIFO_OUT;\n assign PROG_FULL = PROG_FULL_FIFO_OUT;\n assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT;\n\n\n /**************************************************************************\n * find_log2\n * Returns the 'log2' value for the input value for the supported ratios\n ***************************************************************************/\n function integer find_log2;\n input integer int_val;\n integer i,j;\n begin\n i = 1;\n j = 0;\n for (i = 1; i < int_val; i = i*2) begin\n j = j + 1;\n end\n find_log2 = j;\n end\n endfunction\n\n // if an asynchronous FIFO has been selected, display a message that the FIFO\n // will not be cycle-accurate in simulation\n initial begin\n if (C_IMPLEMENTATION_TYPE == 2) begin\n $display(\"WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.\");\n end else if (C_MEMORY_TYPE == 4) begin\n $display(\"FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado.\");\n $finish;\n end\n\n if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin\n $display(\"FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH.\");\n $finish;\n end\n\n if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin\n $display(\"FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH.\");\n $finish;\n end\n\n if (C_USE_ECC == 1) begin\n if (C_DIN_WIDTH != C_DOUT_WIDTH) begin\n $display(\"FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration.\");\n $finish;\n end\n if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin\n $display(\"FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection.\");\n $finish;\n end\n end\n\n end //initial\n\n /**************************************************************************\n * Internal reset logic\n **************************************************************************/\n assign wr_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg : 0;\n assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg : 0;\n assign rst_i = C_HAS_RST ? rst_reg : 0;\n\n wire rst_2_sync;\n wire rst_2_sync_safety = (C_ENABLE_RST_SYNC == 1) ? rst_delayed : RD_RST; \n wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK;\n wire clk_2_sync_safety = (C_COMMON_CLOCK == 1) ? CLK : RD_CLK;\n localparam RST_SYNC_STAGES = (C_EN_SAFETY_CKT == 0) ? C_SYNCHRONIZER_STAGE :\n (C_COMMON_CLOCK == 1) ? 3 : C_SYNCHRONIZER_STAGE+2;\n reg [RST_SYNC_STAGES-1:0] wrst_reg = {RST_SYNC_STAGES{1'b0}};\n reg [RST_SYNC_STAGES-1:0] rrst_reg = {RST_SYNC_STAGES{1'b0}};\n reg [RST_SYNC_STAGES-1:0] arst_sync_q = {RST_SYNC_STAGES{1'b0}};\n reg [RST_SYNC_STAGES-1:0] wrst_q = {RST_SYNC_STAGES{1'b0}};\n reg [RST_SYNC_STAGES-1:0] rrst_q = {RST_SYNC_STAGES{1'b0}};\n reg [RST_SYNC_STAGES-1:0] rrst_wr = {RST_SYNC_STAGES{1'b0}};\n reg [RST_SYNC_STAGES-1:0] wrst_ext = {RST_SYNC_STAGES{1'b0}};\n reg [1:0] wrst_cc = {2{1'b0}};\n reg [1:0] rrst_cc = {2{1'b0}};\n\n generate \n if (C_EN_SAFETY_CKT == 1 && C_INTERFACE_TYPE == 0) begin : grst_safety_ckt\n reg[1:0] rst_d1_safety =1;\n reg[1:0] rst_d2_safety =1;\n reg[1:0] rst_d3_safety =1;\n reg[1:0] rst_d4_safety =1;\n reg[1:0] rst_d5_safety =1;\n reg[1:0] rst_d6_safety =1;\n reg[1:0] rst_d7_safety =1;\n always@(posedge rst_2_sync_safety or posedge clk_2_sync_safety) begin : prst\n if (rst_2_sync_safety == 1'b1) begin\n rst_d1_safety <= 1'b1;\n rst_d2_safety <= 1'b1;\n rst_d3_safety <= 1'b1;\n rst_d4_safety <= 1'b1;\n rst_d5_safety <= 1'b1;\n rst_d6_safety <= 1'b1;\n rst_d7_safety <= 1'b1;\n end\n else begin\n rst_d1_safety <= #`TCQ 1'b0;\n rst_d2_safety <= #`TCQ rst_d1_safety;\n rst_d3_safety <= #`TCQ rst_d2_safety;\n rst_d4_safety <= #`TCQ rst_d3_safety;\n rst_d5_safety <= #`TCQ rst_d4_safety;\n rst_d6_safety <= #`TCQ rst_d5_safety;\n rst_d7_safety <= #`TCQ rst_d6_safety;\n end //if\n end //prst\n always@(posedge rst_d7_safety or posedge WR_EN) begin : assert_safety\n if(rst_d7_safety == 1 && WR_EN == 1) begin \n $display(\"WARNING:A write attempt has been made within the 7 clock cycles of reset de-assertion. This can lead to data discrepancy when safety circuit is enabled.\"); \n \n end //if\n end //always\n end // grst_safety_ckt\n endgenerate \n \n// if (C_EN_SAFET_CKT == 1)\n// assertion:the reset shud be atleast 3 cycles wide. \n\n generate\n reg safety_ckt_wr_rst_i = 1'b0;\n if (C_ENABLE_RST_SYNC == 0) begin : gnrst_sync\n always @* begin\n wr_rst_reg <= wr_rst_delayed;\n rd_rst_reg <= rd_rst_delayed;\n rst_reg <= 1'b0;\n srst_reg <= 1'b0;\n end\n assign rst_2_sync = wr_rst_delayed;\n assign wr_rst_busy = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0;\n assign rd_rst_busy = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0;\n assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0;\n assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0;\n // end : gnrst_sync\n end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 0) begin : g7s_ic_rst\n reg fifo_wrst_done = 1'b0;\n reg fifo_rrst_done = 1'b0;\n reg sckt_wrst_i = 1'b0;\n reg sckt_wrst_i_q = 1'b0;\n reg rd_rst_active = 1'b0;\n reg rd_rst_middle = 1'b0;\n reg sckt_rd_rst_d1 = 1'b0;\n reg [1:0] rst_delayed_ic_w = 2'h0;\n wire rst_delayed_ic_w_i;\n reg [1:0] rst_delayed_ic_r = 2'h0;\n wire rst_delayed_ic_r_i;\n wire arst_sync_rst;\n wire fifo_rst_done;\n wire fifo_rst_active;\n assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg;\n assign rd_rst_comb = C_EN_SAFETY_CKT ? (!rd_rst_asreg_d2 && rd_rst_asreg) || rd_rst_active : !rd_rst_asreg_d2 && rd_rst_asreg;\n assign rst_2_sync = rst_delayed_ic_w_i;\n assign arst_sync_rst = arst_sync_q[RST_SYNC_STAGES-1];\n assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | fifo_rst_active : 1'b0;\n assign rd_rst_busy = C_EN_SAFETY_CKT ? safety_ckt_rd_rst : 1'b0;\n assign fifo_rst_done = fifo_wrst_done & fifo_rrst_done;\n assign fifo_rst_active = sckt_wrst_i | wrst_ext[RST_SYNC_STAGES-1] | rrst_wr[RST_SYNC_STAGES-1];\n\n always @(posedge WR_CLK or posedge rst_delayed) begin\n if (rst_delayed == 1'b1 && C_HAS_RST)\n rst_delayed_ic_w <= 2'b11;\n else\n rst_delayed_ic_w <= #`TCQ {rst_delayed_ic_w[0],1'b0};\n end\n assign rst_delayed_ic_w_i = rst_delayed_ic_w[1];\n\n always @(posedge RD_CLK or posedge rst_delayed) begin\n if (rst_delayed == 1'b1 && C_HAS_RST)\n rst_delayed_ic_r <= 2'b11;\n else\n rst_delayed_ic_r <= #`TCQ {rst_delayed_ic_r[0],1'b0};\n end\n assign rst_delayed_ic_r_i = rst_delayed_ic_r[1];\n\n always @(posedge WR_CLK) begin\n sckt_wrst_i_q <= #`TCQ sckt_wrst_i;\n sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;\n safety_ckt_wr_rst_i <= #`TCQ sckt_wrst_i | wr_rst_busy | sckt_wr_rst_i_q;\n if (arst_sync_rst && ~fifo_rst_active)\n sckt_wrst_i <= #`TCQ 1'b1;\n else if (sckt_wrst_i && fifo_rst_done)\n sckt_wrst_i <= #`TCQ 1'b0;\n else\n sckt_wrst_i <= #`TCQ sckt_wrst_i;\n\n if (rrst_wr[RST_SYNC_STAGES-2] & ~rrst_wr[RST_SYNC_STAGES-1])\n fifo_rrst_done <= #`TCQ 1'b1;\n else if (fifo_rst_done)\n fifo_rrst_done <= #`TCQ 1'b0;\n else\n fifo_rrst_done <= #`TCQ fifo_rrst_done;\n\n if (wrst_ext[RST_SYNC_STAGES-2] & ~wrst_ext[RST_SYNC_STAGES-1])\n fifo_wrst_done <= #`TCQ 1'b1;\n else if (fifo_rst_done)\n fifo_wrst_done <= #`TCQ 1'b0;\n else\n fifo_wrst_done <= #`TCQ fifo_wrst_done;\n end \n\n always @(posedge WR_CLK or posedge rst_delayed_ic_w_i) begin\n if (rst_delayed_ic_w_i == 1'b1) begin\n wr_rst_asreg <= 1'b1;\n end else begin\n if (wr_rst_asreg_d1 == 1'b1) begin\n wr_rst_asreg <= #`TCQ 1'b0;\n end else begin\n wr_rst_asreg <= #`TCQ wr_rst_asreg;\n end\n end \n end \n\n always @(posedge WR_CLK or posedge rst_delayed) begin\n if (rst_delayed == 1'b1) begin\n wr_rst_asreg <= 1'b1;\n end else begin\n if (wr_rst_asreg_d1 == 1'b1) begin\n wr_rst_asreg <= #`TCQ 1'b0;\n end else begin\n wr_rst_asreg <= #`TCQ wr_rst_asreg;\n end\n end \n end \n\n always @(posedge WR_CLK) begin\n wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],wr_rst_asreg};\n wrst_ext <= #`TCQ {wrst_ext[RST_SYNC_STAGES-2:0],sckt_wrst_i};\n rrst_wr <= #`TCQ {rrst_wr[RST_SYNC_STAGES-2:0],safety_ckt_rd_rst};\n arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_ic_w_i};\n end\n\n assign wr_rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2];\n assign wr_rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1];\n assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;\n\n always @(posedge WR_CLK or posedge wr_rst_comb) begin\n if (wr_rst_comb == 1'b1) begin\n wr_rst_reg <= 1'b1;\n end else begin\n wr_rst_reg <= #`TCQ 1'b0;\n end \n end \n\n always @(posedge RD_CLK or posedge rst_delayed_ic_r_i) begin\n if (rst_delayed_ic_r_i == 1'b1) begin\n rd_rst_asreg <= 1'b1;\n end else begin\n if (rd_rst_asreg_d1 == 1'b1) begin\n rd_rst_asreg <= #`TCQ 1'b0;\n end else begin\n rd_rst_asreg <= #`TCQ rd_rst_asreg;\n end\n end \n end \n\n always @(posedge RD_CLK) begin\n rrst_reg <= #`TCQ {rrst_reg[RST_SYNC_STAGES-2:0],rd_rst_asreg};\n rrst_q <= #`TCQ {rrst_q[RST_SYNC_STAGES-2:0],sckt_wrst_i};\n rrst_cc <= #`TCQ {rrst_cc[0],rd_rst_asreg_d2};\n sckt_rd_rst_d1 <= #`TCQ safety_ckt_rd_rst;\n if (!rd_rst_middle && rrst_reg[1] && !rrst_reg[2]) begin\n rd_rst_active <= #`TCQ 1'b1;\n rd_rst_middle <= #`TCQ 1'b1;\n end else if (safety_ckt_rd_rst)\n rd_rst_active <= #`TCQ 1'b0;\n else if (sckt_rd_rst_d1 && !safety_ckt_rd_rst)\n rd_rst_middle <= #`TCQ 1'b0;\n end\n assign rd_rst_asreg_d1 = rrst_reg[RST_SYNC_STAGES-2];\n assign rd_rst_asreg_d2 = C_EN_SAFETY_CKT ? rrst_reg[RST_SYNC_STAGES-1] : rrst_reg[1];\n assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rrst_q[2] : 1'b0;\n\n always @(posedge RD_CLK or posedge rd_rst_comb) begin\n if (rd_rst_comb == 1'b1) begin\n rd_rst_reg <= 1'b1;\n end else begin\n rd_rst_reg <= #`TCQ 1'b0;\n end \n end \n // end : g7s_ic_rst\n end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_rst\n reg [1:0] rst_delayed_cc = 2'h0;\n wire rst_delayed_cc_i;\n assign rst_comb = !rst_asreg_d2 && rst_asreg; \n assign rst_2_sync = rst_delayed_cc_i;\n assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | wrst_cc[1] : 1'b0;\n assign rd_rst_busy = C_EN_SAFETY_CKT ? arst_sync_q[1] | arst_sync_q[RST_SYNC_STAGES-1] | wrst_cc[1] : 1'b0;\n \n always @(posedge CLK or posedge rst_delayed) begin\n if (rst_delayed == 1'b1)\n rst_delayed_cc <= 2'b11;\n else\n rst_delayed_cc <= #`TCQ {rst_delayed_cc,1'b0};\n end \n assign rst_delayed_cc_i = rst_delayed_cc[1];\n \n always @(posedge CLK or posedge rst_delayed_cc_i) begin\n if (rst_delayed_cc_i == 1'b1) begin\n rst_asreg <= 1'b1;\n end else begin\n if (rst_asreg_d1 == 1'b1) begin\n rst_asreg <= #`TCQ 1'b0;\n end else begin\n rst_asreg <= #`TCQ rst_asreg;\n end\n end \n end \n \n always @(posedge CLK) begin\n wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],rst_asreg};\n wrst_cc <= #`TCQ {wrst_cc[0],arst_sync_q[RST_SYNC_STAGES-1]};\n sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;\n safety_ckt_wr_rst_i <= #`TCQ wrst_cc[1] | wr_rst_busy | sckt_wr_rst_i_q;\n arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_cc_i};\n end\n assign rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2];\n assign rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1];\n assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;\n assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;\n\n always @(posedge CLK or posedge rst_comb) begin\n if (rst_comb == 1'b1) begin\n rst_reg <= 1'b1;\n end else begin\n rst_reg <= #`TCQ 1'b0;\n end \n end \n // end : g7s_cc_rst\n end else if (IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst\n assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i;\n assign rd_rst_busy = rst_reg;\n assign rst_2_sync = srst_delayed;\n always @* rst_full_ff_i <= rst_reg;\n always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0;\n assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0;\n assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0;\n\n always @(posedge CLK) begin\n rst_delayed_d1 <= #`TCQ srst_delayed;\n rst_delayed_d2 <= #`TCQ rst_delayed_d1;\n sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;\n if (rst_reg || rst_delayed_d2) begin\n rst_active_i <= #`TCQ 1'b1;\n end else begin\n rst_active_i <= #`TCQ rst_reg;\n end \n end \n always @(posedge CLK) begin\n if (~rst_reg && srst_delayed) begin\n rst_reg <= #`TCQ 1'b1;\n end else if (rst_reg) begin\n rst_reg <= #`TCQ 1'b0;\n end else begin\n rst_reg <= #`TCQ rst_reg;\n end \n end \n // end : g8s_cc_rst\n end else begin \n assign wr_rst_busy = 1'b0;\n assign rd_rst_busy = 1'b0;\n assign safety_ckt_wr_rst = 1'b0;\n assign safety_ckt_rd_rst = 1'b0;\n end\n endgenerate \n\n generate\n if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1\n // RST_FULL_GEN replaces the reset falling edge detection used to de-assert\n // FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.\n\n // RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &\n // PROG_FULL\n reg rst_d1 = 1'b0;\n reg rst_d2 = 1'b0;\n reg rst_d3 = 1'b0;\n reg rst_d4 = 1'b0;\n reg rst_d5 = 1'b0;\n\n always @ (posedge rst_2_sync or posedge clk_2_sync) begin\n if (rst_2_sync) begin\n rst_d1 <= 1'b1;\n rst_d2 <= 1'b1;\n rst_d3 <= 1'b1;\n rst_d4 <= 1'b1;\n end else begin\n if (srst_delayed) begin\n rst_d1 <= #`TCQ 1'b1;\n rst_d2 <= #`TCQ 1'b1;\n rst_d3 <= #`TCQ 1'b1;\n rst_d4 <= #`TCQ 1'b1;\n end else begin\n rst_d1 <= #`TCQ wr_rst_busy;\n rst_d2 <= #`TCQ rst_d1;\n rst_d3 <= #`TCQ rst_d2 | safety_ckt_wr_rst;\n rst_d4 <= #`TCQ rst_d3;\n end\n end\n end\n\n always @* rst_full_ff_i <= (C_HAS_SRST == 0) ? rst_d2 : 1'b0 ;\n always @* rst_full_gen_i <= rst_d3;\n\n end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full\n always @* rst_full_ff_i <= (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;\n end\n endgenerate // grstd1\n\nendmodule //fifo_generator_v13_1_2_conv_ver\n\n\nmodule fifo_generator_v13_1_2_sync_stage\n #(\n parameter C_WIDTH = 10\n )\n (\n input RST,\n input CLK,\n input [C_WIDTH-1:0] DIN,\n output reg [C_WIDTH-1:0] DOUT = 0\n );\n always @ (posedge RST or posedge CLK) begin\n if (RST)\n DOUT <= 0;\n else\n DOUT <= #`TCQ DIN;\n end\nendmodule // fifo_generator_v13_1_2_sync_stage\n\n/*******************************************************************************\n * Declaration of Independent-Clocks FIFO Module\n ******************************************************************************/\nmodule fifo_generator_v13_1_2_bhv_ver_as\n \n /***************************************************************************\n * Declare user parameters and their defaults\n ***************************************************************************/\n #(\n parameter C_FAMILY = \"virtex7\",\n parameter C_DATA_COUNT_WIDTH = 2,\n parameter C_DIN_WIDTH = 8,\n parameter C_DOUT_RST_VAL = \"\",\n parameter C_DOUT_WIDTH = 8,\n parameter C_FULL_FLAGS_RST_VAL = 1,\n parameter C_HAS_ALMOST_EMPTY = 0,\n parameter C_HAS_ALMOST_FULL = 0,\n parameter C_HAS_DATA_COUNT = 0,\n parameter C_HAS_OVERFLOW = 0,\n parameter C_HAS_RD_DATA_COUNT = 0,\n parameter C_HAS_RST = 0,\n parameter C_HAS_UNDERFLOW = 0,\n parameter C_HAS_VALID = 0,\n parameter C_HAS_WR_ACK = 0,\n parameter C_HAS_WR_DATA_COUNT = 0,\n parameter C_IMPLEMENTATION_TYPE = 0,\n parameter C_MEMORY_TYPE = 1,\n parameter C_OVERFLOW_LOW = 0,\n parameter C_PRELOAD_LATENCY = 1,\n parameter C_PRELOAD_REGS = 0,\n parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n parameter C_PROG_EMPTY_TYPE = 0,\n parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,\n parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,\n parameter C_PROG_FULL_TYPE = 0,\n parameter C_RD_DATA_COUNT_WIDTH = 2,\n parameter C_RD_DEPTH = 256,\n parameter C_RD_PNTR_WIDTH = 8,\n parameter C_UNDERFLOW_LOW = 0,\n parameter C_USE_DOUT_RST = 0,\n parameter C_USE_EMBEDDED_REG = 0,\n parameter C_EN_SAFETY_CKT = 0,\n parameter C_USE_FWFT_DATA_COUNT = 0,\n parameter C_VALID_LOW = 0,\n parameter C_WR_ACK_LOW = 0,\n parameter C_WR_DATA_COUNT_WIDTH = 2,\n parameter C_WR_DEPTH = 256,\n parameter C_WR_PNTR_WIDTH = 8,\n parameter C_USE_ECC = 0, \n parameter C_ENABLE_RST_SYNC = 1,\n parameter C_ERROR_INJECTION_TYPE = 0,\n parameter C_SYNCHRONIZER_STAGE = 2 \n )\n\n /***************************************************************************\n * Declare Input and Output Ports\n ***************************************************************************/\n (\n input SAFETY_CKT_WR_RST,\n input SAFETY_CKT_RD_RST,\n input [C_DIN_WIDTH-1:0] DIN,\n input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,\n input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,\n input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,\n input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,\n input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,\n input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,\n input RD_CLK,\n input RD_EN,\n input RD_EN_USER,\n input RST,\n input RST_FULL_GEN,\n input RST_FULL_FF,\n input WR_RST,\n input RD_RST,\n input WR_CLK,\n input WR_EN,\n input INJECTDBITERR,\n input INJECTSBITERR,\n input USER_EMPTY_FB,\n input fab_read_data_valid_i,\n input read_data_valid_i,\n input ram_valid_i,\n output reg ALMOST_EMPTY = 1'b1,\n output reg ALMOST_FULL = C_FULL_FLAGS_RST_VAL,\n output [C_DOUT_WIDTH-1:0] DOUT,\n output reg EMPTY = 1'b1,\n output reg EMPTY_FB = 1'b1,\n output reg FULL = C_FULL_FLAGS_RST_VAL,\n output OVERFLOW,\n output PROG_EMPTY,\n output PROG_FULL,\n output VALID,\n output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,\n output UNDERFLOW,\n output WR_ACK,\n output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,\n output SBITERR,\n output DBITERR\n );\n\n\n reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;\n reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;\n reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;\n \n \n /***************************************************************************\n * Parameters used as constants\n **************************************************************************/\n localparam IS_8SERIES = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\") ? 1 : 0;\n //When RST is present, set FULL reset value to '1'.\n //If core has no RST, make sure FULL powers-on as '0'.\n localparam C_DEPTH_RATIO_WR = \n (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;\n localparam C_DEPTH_RATIO_RD = \n (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;\n localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;\n localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;\n\n // C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC\n // -----------------|------------------|-----------------|---------------\n // 1 | 8 | C_RD_PNTR_WIDTH | 2\n // 1 | 4 | C_RD_PNTR_WIDTH | 2\n // 1 | 2 | C_RD_PNTR_WIDTH | 2\n // 1 | 1 | C_WR_PNTR_WIDTH | 2\n // 2 | 1 | C_WR_PNTR_WIDTH | 4\n // 4 | 1 | C_WR_PNTR_WIDTH | 8\n // 8 | 1 | C_WR_PNTR_WIDTH | 16\n \n localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n\n localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;\n \n localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);\n \n localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;\n \n localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);\n\n\n\n /**************************************************************************\n * FIFO Contents Tracking and Data Count Calculations\n *************************************************************************/\n \n // Memory which will be used to simulate a FIFO\n reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n // Local parameters used to determine whether to inject ECC error or not\n localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;\n localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;\n localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;\n localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION;\n // Array that holds the error injection type (single/double bit error) on \n // a specific write operation, which is returned on read to corrupt the\n // output data.\n reg [1:0] ecc_err[C_WR_DEPTH-1:0];\n\n //The amount of data stored in the FIFO at any time is given\n // by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK\n // domain.\n //num_wr_bits is calculated by considering the total words in the FIFO,\n // and the state of the read pointer (which may not have yet crossed clock\n // domains.)\n //num_rd_bits is calculated by considering the total words in the FIFO,\n // and the state of the write pointer (which may not have yet crossed clock\n // domains.)\n reg [31:0] num_wr_bits;\n reg [31:0] num_rd_bits;\n reg [31:0] next_num_wr_bits;\n reg [31:0] next_num_rd_bits;\n\n //The write pointer - tracks write operations\n // (Works opposite to core: wr_ptr is a DOWN counter)\n reg [31:0] wr_ptr;\n reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.\n reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;\n reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;\n reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;\n wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;\n reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;\n wire wr_rst_i = WR_RST;\n reg wr_rst_d1 =0;\n\n //The read pointer - tracks read operations\n // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)\n reg [31:0] rd_ptr;\n reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.\n reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;\n reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;\n reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;\n reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;\n wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;\n reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;\n wire rd_rst_i = RD_RST;\n wire ram_rd_en;\n wire empty_int;\n wire almost_empty_int;\n wire ram_wr_en;\n wire full_int;\n wire almost_full_int;\n reg ram_rd_en_d1 = 1'b0;\n reg fab_rd_en_d1 = 1'b0;\n\n\n\n // Delayed ram_rd_en is needed only for STD Embedded register option\n generate\n if (C_PRELOAD_LATENCY == 2) begin : grd_d\n always @ (posedge RD_CLK or posedge rd_rst_i) begin\n if (rd_rst_i)\n ram_rd_en_d1 <= 1'b0;\n else\n ram_rd_en_d1 <= #`TCQ ram_rd_en;\n end\n end\n endgenerate\n \n generate\n if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1\n always @ (posedge RD_CLK or posedge rd_rst_i) begin\n if (rd_rst_i)\n ram_rd_en_d1 <= 1'b0;\n else\n ram_rd_en_d1 <= #`TCQ ram_rd_en;\n fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n end\n end\n endgenerate\n\n \n\n // Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation\n generate\n if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth\n assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0;\n end else begin : rdl // Read depth lesser than or equal to write depth\n assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n end\n endgenerate\n\n // Generate Empty and Almost Empty\n // ram_rd_en used to determine EMPTY should depend on the EMPTY.\n assign ram_rd_en = RD_EN & !EMPTY;\n assign empty_int = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1))));\n assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2))));\n\n // Register Empty and Almost Empty\n always @ (posedge RD_CLK or posedge rd_rst_i)\n begin\n if (rd_rst_i) begin\n EMPTY <= 1'b1;\n ALMOST_EMPTY <= 1'b1;\n rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};\n end else begin\n rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0};\n\n if (empty_int)\n EMPTY <= #`TCQ 1'b1;\n else\n EMPTY <= #`TCQ 1'b0;\n\n if (!EMPTY) begin\n if (almost_empty_int)\n ALMOST_EMPTY <= #`TCQ 1'b1;\n else\n ALMOST_EMPTY <= #`TCQ 1'b0;\n end\n end // rd_rst_i\n end // always\n always @ (posedge RD_CLK or posedge rd_rst_i)\n begin\n if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n EMPTY_FB <= 1'b1;\n end else begin\n if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT)\n EMPTY_FB <= #`TCQ 1'b1;\n else if (empty_int)\n EMPTY_FB <= #`TCQ 1'b1;\n else\n EMPTY_FB <= #`TCQ 1'b0;\n end // rd_rst_i\n end // always\n\n // Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation\n generate\n if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth\n assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;\n assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0;\n end else begin : wdl // Write depth lesser than or equal to read depth\n assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n end\n endgenerate\n\n // Generate FULL and ALMOST_FULL\n // ram_wr_en used to determine FULL should depend on the FULL.\n assign ram_wr_en = WR_EN & !FULL;\n assign full_int = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2))));\n assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3))));\n\n // Register FULL and ALMOST_FULL Empty\n always @ (posedge WR_CLK or posedge RST_FULL_FF)\n begin\n if (RST_FULL_FF) begin\n FULL <= C_FULL_FLAGS_RST_VAL;\n ALMOST_FULL <= C_FULL_FLAGS_RST_VAL;\n end else begin\n if (full_int) begin\n FULL <= #`TCQ 1'b1;\n end else begin\n FULL <= #`TCQ 1'b0;\n end\n\n if (RST_FULL_GEN) begin\n ALMOST_FULL <= #`TCQ 1'b0;\n end else if (!FULL) begin\n if (almost_full_int)\n ALMOST_FULL <= #`TCQ 1'b1;\n else\n ALMOST_FULL <= #`TCQ 1'b0;\n end\n end // wr_rst_i\n end // always\n always @ (posedge WR_CLK or posedge wr_rst_i)\n begin\n if (wr_rst_i) begin\n wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1'b0}};\n end else begin\n wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0};\n end // wr_rst_i\n end // always\n\n // Determine which stage in FWFT registers are valid\n reg stage1_valid = 0;\n reg stage2_valid = 0;\n generate\n if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc\n always @ (posedge RD_CLK or posedge rd_rst_i) begin\n if (rd_rst_i) begin\n stage1_valid <= 0;\n stage2_valid <= 0;\n end else begin\n\n if (!stage1_valid && !stage2_valid) begin\n if (!EMPTY)\n stage1_valid <= #`TCQ 1'b1;\n else\n stage1_valid <= #`TCQ 1'b0;\n end else if (stage1_valid && !stage2_valid) begin\n if (EMPTY) begin\n stage1_valid <= #`TCQ 1'b0;\n stage2_valid <= #`TCQ 1'b1;\n end else begin\n stage1_valid <= #`TCQ 1'b1;\n stage2_valid <= #`TCQ 1'b1;\n end\n end else if (!stage1_valid && stage2_valid) begin\n if (EMPTY && RD_EN_USER) begin\n stage1_valid <= #`TCQ 1'b0;\n stage2_valid <= #`TCQ 1'b0;\n end else if (!EMPTY && RD_EN_USER) begin\n stage1_valid <= #`TCQ 1'b1;\n stage2_valid <= #`TCQ 1'b0;\n end else if (!EMPTY && !RD_EN_USER) begin\n stage1_valid <= #`TCQ 1'b1;\n stage2_valid <= #`TCQ 1'b1;\n end else begin\n stage1_valid <= #`TCQ 1'b0;\n stage2_valid <= #`TCQ 1'b1;\n end\n end else if (stage1_valid && stage2_valid) begin\n if (EMPTY && RD_EN_USER) begin\n stage1_valid <= #`TCQ 1'b0;\n stage2_valid <= #`TCQ 1'b1;\n end else begin\n stage1_valid <= #`TCQ 1'b1;\n stage2_valid <= #`TCQ 1'b1;\n end\n end else begin\n stage1_valid <= #`TCQ 1'b0;\n stage2_valid <= #`TCQ 1'b0;\n end\n end // rd_rst_i\n end // always\n end\n endgenerate\n\n //Pointers passed into opposite clock domain\n reg [31:0] wr_ptr_rdclk;\n reg [31:0] wr_ptr_rdclk_next;\n reg [31:0] rd_ptr_wrclk;\n reg [31:0] rd_ptr_wrclk_next;\n\n //Amount of data stored in the FIFO scaled to the narrowest (deepest) port\n // (Do not include data in FWFT stages)\n //Used to calculate PROG_EMPTY.\n wire [31:0] num_read_words_pe = \n num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR);\n\n //Amount of data stored in the FIFO scaled to the narrowest (deepest) port\n // (Do not include data in FWFT stages)\n //Used to calculate PROG_FULL.\n wire [31:0] num_write_words_pf =\n num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD);\n\n /**************************\n * Read Data Count\n *************************/\n\n reg [31:0] num_read_words_dc;\n reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;\n \n always @(num_rd_bits) begin\n if (C_USE_FWFT_DATA_COUNT) begin\n \n //If using extra logic for FWFT Data Counts, \n // then scale FIFO contents to read domain, \n // and add two read words for FWFT stages\n //This value is only a temporary value and not used in the code.\n num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);\n \n //Trim the read words for use with RD_DATA_COUNT\n num_read_words_sized_i = \n num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];\n \n end else begin\n \n //If not using extra logic for FWFT Data Counts, \n // then scale FIFO contents to read domain.\n //This value is only a temporary value and not used in the code.\n num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;\n \n //Trim the read words for use with RD_DATA_COUNT\n num_read_words_sized_i = \n num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];\n \n end //if (C_USE_FWFT_DATA_COUNT)\n end //always\n\n \n /**************************\n * Write Data Count\n *************************/\n\n reg [31:0] num_write_words_dc;\n reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;\n \n always @(num_wr_bits) begin\n if (C_USE_FWFT_DATA_COUNT) begin\n \n //Calculate the Data Count value for the number of write words, \n // when using First-Word Fall-Through with extra logic for Data \n // Counts. This takes into consideration the number of words that \n // are expected to be stored in the FWFT register stages (it always \n // assumes they are filled).\n //This value is scaled to the Write Domain.\n //The expression (((A-1)/B))+1 divides A/B, but takes the \n // ceiling of the result.\n //When num_wr_bits==0, set the result manually to prevent \n // division errors.\n //EXTRA_WORDS_DC is the number of words added to write_words \n // due to FWFT.\n //This value is only a temporary value and not used in the code.\n num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;\n \n //Trim the write words for use with WR_DATA_COUNT\n num_write_words_sized_i = \n num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];\n \n end else begin\n \n //Calculate the Data Count value for the number of write words, when NOT\n // using First-Word Fall-Through with extra logic for Data Counts. This \n // calculates only the number of words in the internal FIFO.\n //The expression (((A-1)/B))+1 divides A/B, but takes the \n // ceiling of the result.\n //This value is scaled to the Write Domain.\n //When num_wr_bits==0, set the result manually to prevent \n // division errors.\n //This value is only a temporary value and not used in the code.\n num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;\n \n //Trim the read words for use with RD_DATA_COUNT\n num_write_words_sized_i = \n num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];\n \n end //if (C_USE_FWFT_DATA_COUNT)\n end //always\n\n \n \n /***************************************************************************\n * Internal registers and wires\n **************************************************************************/\n\n //Temporary signals used for calculating the model's outputs. These\n //are only used in the assign statements immediately following wire,\n //parameter, and function declarations.\n wire [C_DOUT_WIDTH-1:0] ideal_dout_out; \n wire valid_i;\n wire valid_out1;\n wire valid_out2;\n wire valid_out; \n wire underflow_i;\n\n //Ideal FIFO signals. These are the raw output of the behavioral model,\n //which behaves like an ideal FIFO.\n reg [1:0] err_type = 0;\n reg [1:0] err_type_d1 = 0;\n reg [1:0] err_type_both = 0;\n reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;\n reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;\n reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0;\n reg ideal_wr_ack = 0;\n reg ideal_valid = 0;\n reg ideal_overflow = C_OVERFLOW_LOW;\n reg ideal_underflow = C_UNDERFLOW_LOW;\n reg ideal_prog_full = 0;\n reg ideal_prog_empty = 1;\n reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;\n reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;\n\n //Assorted reg values for delayed versions of signals \n reg valid_d1 = 0;\n reg valid_d2 = 0; \n \n //user specified value for reseting the size of the fifo\n reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;\n \n //temporary registers for WR_RESPONSE_LATENCY feature\n \n integer tmp_wr_listsize;\n integer tmp_rd_listsize;\n \n //Signal for registered version of prog full and empty\n \n //Threshold values for Programmable Flags\n integer prog_empty_actual_thresh_assert;\n integer prog_empty_actual_thresh_negate;\n integer prog_full_actual_thresh_assert;\n integer prog_full_actual_thresh_negate;\n \n\n /****************************************************************************\n * Function Declarations\n ***************************************************************************/\n\n /**************************************************************************\n * write_fifo\n * This task writes a word to the FIFO memory and updates the \n * write pointer.\n * FIFO size is relative to write domain.\n ***************************************************************************/\n task write_fifo;\n begin\n memory[wr_ptr] <= DIN;\n wr_pntr <= #`TCQ wr_pntr + 1;\n // Store the type of error injection (double/single) on write\n case (C_ERROR_INJECTION_TYPE)\n 3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};\n 2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};\n 1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};\n default: ecc_err[wr_ptr] <= 0;\n endcase\n // (Works opposite to core: wr_ptr is a DOWN counter)\n if (wr_ptr == 0) begin\n wr_ptr <= C_WR_DEPTH - 1;\n end else begin\n wr_ptr <= wr_ptr - 1;\n end\n end\n endtask // write_fifo\n\n /**************************************************************************\n * read_fifo\n * This task reads a word from the FIFO memory and updates the read \n * pointer. It's output is the ideal_dout bus.\n * FIFO size is relative to write domain.\n ***************************************************************************/\n task read_fifo;\n integer i;\n reg [C_DOUT_WIDTH-1:0] tmp_dout;\n reg [C_DIN_WIDTH-1:0] memory_read;\n reg [31:0] tmp_rd_ptr;\n reg [31:0] rd_ptr_high;\n reg [31:0] rd_ptr_low;\n reg [1:0] tmp_ecc_err;\n begin\n rd_pntr <= #`TCQ rd_pntr + 1;\n // output is wider than input\n if (reads_per_write == 0) begin\n tmp_dout = 0;\n tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);\n for (i = writes_per_read - 1; i >= 0; i = i - 1) begin\n tmp_dout = tmp_dout << C_DIN_WIDTH;\n tmp_dout = tmp_dout | memory[tmp_rd_ptr];\n \n // (Works opposite to core: rd_ptr is a DOWN counter)\n if (tmp_rd_ptr == 0) begin\n tmp_rd_ptr = C_WR_DEPTH - 1;\n end else begin\n tmp_rd_ptr = tmp_rd_ptr - 1;\n end\n end\n\n // output is symmetric\n end else if (reads_per_write == 1) begin\n tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];\n // Retreive the error injection type. Based on the error injection type\n // corrupt the output data.\n tmp_ecc_err = ecc_err[rd_ptr];\n if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin\n if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error\n if (C_DOUT_WIDTH == 1) begin\n $display(\"FAILURE : Data width must be >= 2 for double bit error injection.\");\n $finish;\n end else if (C_DOUT_WIDTH == 2)\n tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};\n else\n tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};\n end else begin\n tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];\n end\n err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};\n end else begin\n err_type <= 0;\n end\n\n // input is wider than output\n end else begin\n rd_ptr_high = rd_ptr >> log2_reads_per_write;\n rd_ptr_low = rd_ptr & (reads_per_write - 1);\n memory_read = memory[rd_ptr_high];\n tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);\n end\n ideal_dout <= tmp_dout;\n \n // (Works opposite to core: rd_ptr is a DOWN counter)\n if (rd_ptr == 0) begin\n rd_ptr <= C_RD_DEPTH - 1;\n end else begin\n rd_ptr <= rd_ptr - 1;\n end\n end\n endtask\n\n /**************************************************************************\n * log2_val\n * Returns the 'log2' value for the input value for the supported ratios\n ***************************************************************************/\n function [31:0] log2_val;\n input [31:0] binary_val;\n\n begin\n if (binary_val == 8) begin\n log2_val = 3;\n end else if (binary_val == 4) begin\n log2_val = 2;\n end else begin\n log2_val = 1;\n end\n end\n endfunction\n\n /***********************************************************************\n * hexstr_conv\n * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n ***********************************************************************/\n function [C_DOUT_WIDTH-1:0] hexstr_conv;\n input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n integer index,i,j;\n reg [3:0] bin;\n\n begin\n index = 0;\n hexstr_conv = 'b0;\n for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )\n begin\n case (def_data[7:0])\n 8'b00000000 :\n begin\n bin = 4'b0000;\n i = -1;\n end\n 8'b00110000 : bin = 4'b0000;\n 8'b00110001 : bin = 4'b0001;\n 8'b00110010 : bin = 4'b0010;\n 8'b00110011 : bin = 4'b0011;\n 8'b00110100 : bin = 4'b0100;\n 8'b00110101 : bin = 4'b0101;\n 8'b00110110 : bin = 4'b0110;\n 8'b00110111 : bin = 4'b0111;\n 8'b00111000 : bin = 4'b1000;\n 8'b00111001 : bin = 4'b1001;\n 8'b01000001 : bin = 4'b1010;\n 8'b01000010 : bin = 4'b1011;\n 8'b01000011 : bin = 4'b1100;\n 8'b01000100 : bin = 4'b1101;\n 8'b01000101 : bin = 4'b1110;\n 8'b01000110 : bin = 4'b1111;\n 8'b01100001 : bin = 4'b1010;\n 8'b01100010 : bin = 4'b1011;\n 8'b01100011 : bin = 4'b1100;\n 8'b01100100 : bin = 4'b1101;\n 8'b01100101 : bin = 4'b1110;\n 8'b01100110 : bin = 4'b1111;\n default :\n begin\n bin = 4'bx;\n end\n endcase\n for( j=0; j<4; j=j+1)\n begin\n if ((index*4)+j < C_DOUT_WIDTH)\n begin\n hexstr_conv[(index*4)+j] = bin[j];\n end\n end\n index = index + 1;\n def_data = def_data >> 8;\n end\n end\n endfunction\n\n /*************************************************************************\n * Initialize Signals for clean power-on simulation\n *************************************************************************/\n initial begin\n num_wr_bits = 0;\n num_rd_bits = 0;\n next_num_wr_bits = 0;\n next_num_rd_bits = 0;\n rd_ptr = C_RD_DEPTH - 1;\n wr_ptr = C_WR_DEPTH - 1;\n wr_pntr = 0;\n rd_pntr = 0;\n rd_ptr_wrclk = rd_ptr;\n wr_ptr_rdclk = wr_ptr;\n dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);\n ideal_dout = dout_reset_val;\n err_type = 0;\n err_type_d1 = 0;\n err_type_both = 0;\n ideal_dout_d1 = dout_reset_val;\n ideal_wr_ack = 1'b0;\n ideal_valid = 1'b0;\n valid_d1 = 1'b0;\n valid_d2 = 1'b0;\n ideal_overflow = C_OVERFLOW_LOW;\n ideal_underflow = C_UNDERFLOW_LOW;\n ideal_wr_count = 0;\n ideal_rd_count = 0;\n ideal_prog_full = 1'b0;\n ideal_prog_empty = 1'b1;\n end\n\n\n /*************************************************************************\n * Connect the module inputs and outputs to the internal signals of the \n * behavioral model.\n *************************************************************************/\n //Inputs\n /*\n wire [C_DIN_WIDTH-1:0] DIN;\n wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;\n wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;\n wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;\n wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;\n wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;\n wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; \n wire RD_CLK;\n wire RD_EN;\n wire RST;\n wire WR_CLK;\n wire WR_EN;\n */\n\n //***************************************************************************\n // Dout may change behavior based on latency\n //***************************************************************************\n assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 &&\n (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )?\n ideal_dout_d1: ideal_dout; \n assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out; \n\n //***************************************************************************\n // Assign SBITERR and DBITERR based on latency \n //***************************************************************************\n assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && \n (C_PRELOAD_LATENCY == 2 &&\n (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ?\n err_type_d1[0]: err_type[0]; \n assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&\n (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n err_type_d1[1]: err_type[1]; \n \n //***************************************************************************\n // Safety-ckt logic with embedded reg/fabric reg\n //***************************************************************************\n generate\n if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin\n \n reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;\n reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;\n reg [1:0] rst_delayed_sft1 =1;\n reg [1:0] rst_delayed_sft2 =1;\n reg [1:0] rst_delayed_sft3 =1;\n reg [1:0] rst_delayed_sft4 =1;\n\n // if (C_HAS_VALID == 1) begin\n // assign valid_out = valid_d1;\n // end\n \n always@(posedge RD_CLK)\n begin\n rst_delayed_sft1 <= #`TCQ rd_rst_i;\n rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n end\n always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK)\n begin\n if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) \n ram_rd_en_d1 <= #`TCQ 1'b0;\n else \n ram_rd_en_d1 <= #`TCQ ram_rd_en;\n end\n \n always@(posedge rst_delayed_sft2 or posedge RD_CLK) \n begin\n if (rst_delayed_sft2 == 1'b1) begin\n if (C_USE_DOUT_RST == 1'b1) begin\n @(posedge RD_CLK)\n ideal_dout_d1 <= #`TCQ dout_reset_val;\n end\n end\n else begin\n if (ram_rd_en_d1) begin\n ideal_dout_d1 <= #`TCQ ideal_dout;\n err_type_d1[0] <= #`TCQ err_type[0];\n err_type_d1[1] <= #`TCQ err_type[1];\n end\n end \n end \n end \n endgenerate \n\n//***************************************************************************\n // Safety-ckt logic with embedded reg + fabric reg\n //***************************************************************************\n generate\n if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n \n reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;\n reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;\n reg [1:0] rst_delayed_sft1 =1;\n reg [1:0] rst_delayed_sft2 =1;\n reg [1:0] rst_delayed_sft3 =1;\n reg [1:0] rst_delayed_sft4 =1;\n\n always@(posedge RD_CLK) begin\n rst_delayed_sft1 <= #`TCQ rd_rst_i;\n rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n end\n always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin\n if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) \n ram_rd_en_d1 <= #`TCQ 1'b0;\n else begin\n ram_rd_en_d1 <= #`TCQ ram_rd_en;\n fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n end\n end\n \n always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin\n if (rst_delayed_sft2 == 1'b1) begin\n if (C_USE_DOUT_RST == 1'b1) begin\n @(posedge RD_CLK)\n ideal_dout_d1 <= #`TCQ dout_reset_val;\n ideal_dout_both <= #`TCQ dout_reset_val;\n end\n end else begin\n if (ram_rd_en_d1) begin\n ideal_dout_both <= #`TCQ ideal_dout;\n err_type_both[0] <= #`TCQ err_type[0];\n err_type_both[1] <= #`TCQ err_type[1];\n end\n \n if (fab_rd_en_d1) begin\n ideal_dout_d1 <= #`TCQ ideal_dout_both;\n err_type_d1[0] <= #`TCQ err_type_both[0];\n err_type_d1[1] <= #`TCQ err_type_both[1];\n end\n end \n end \n end \n endgenerate \n \n //***************************************************************************\n // Overflow may be active-low\n //***************************************************************************\n generate\n if (C_HAS_OVERFLOW==1) begin : blockOF1\n assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;\n end\n endgenerate\n\n assign PROG_EMPTY = ideal_prog_empty;\n assign PROG_FULL = ideal_prog_full;\n\n //***************************************************************************\n // Valid may change behavior based on latency or active-low\n //***************************************************************************\n generate\n if (C_HAS_VALID==1) begin : blockVL1\n assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;\n assign valid_out1 = (C_PRELOAD_LATENCY==2 &&\n (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)?\n valid_d1: valid_i; \n assign valid_out2 = (C_PRELOAD_LATENCY==2 &&\n (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)?\n valid_d2: valid_i; \n assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1;\n assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;\n end\n endgenerate\n\n\n //***************************************************************************\n // Underflow may change behavior based on latency or active-low \n //***************************************************************************\n generate\n if (C_HAS_UNDERFLOW==1) begin : blockUF1\n assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;\n assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;\n end\n endgenerate\n\n //***************************************************************************\n // Write acknowledge may be active low\n //***************************************************************************\n generate\n if (C_HAS_WR_ACK==1) begin : blockWK1\n assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;\n end\n endgenerate\n\n\n //***************************************************************************\n // Generate RD_DATA_COUNT if Use Extra Logic option is selected\n //***************************************************************************\n generate\n if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext\n\n reg [C_PNTR_WIDTH-1:0] adjusted_wr_pntr = 0;\n reg [C_PNTR_WIDTH-1:0] adjusted_rd_pntr = 0;\n wire [C_PNTR_WIDTH-1:0] diff_wr_rd_tmp;\n wire [C_PNTR_WIDTH:0] diff_wr_rd;\n reg [C_PNTR_WIDTH:0] wr_data_count_i = 0;\n always @* begin\n if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin\n adjusted_wr_pntr = wr_pntr;\n adjusted_rd_pntr = 0;\n adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;\n end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin\n adjusted_rd_pntr = rd_pntr_wr;\n adjusted_wr_pntr = 0;\n adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;\n end else begin\n adjusted_wr_pntr = wr_pntr;\n adjusted_rd_pntr = rd_pntr_wr;\n end\n end // always @*\n\n assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr;\n assign diff_wr_rd = {1'b0,diff_wr_rd_tmp};\n\n always @ (posedge wr_rst_i or posedge WR_CLK)\n begin\n if (wr_rst_i)\n wr_data_count_i <= 0;\n else\n wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC;\n end // always @ (posedge WR_CLK or posedge WR_CLK)\n\n always @* begin\n if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH)\n wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0];\n else\n wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n end // always @*\n end // wdc_fwft_ext\n endgenerate\n\n //***************************************************************************\n // Generate RD_DATA_COUNT if Use Extra Logic option is selected\n //***************************************************************************\n reg [C_RD_PNTR_WIDTH:0] rdc_fwft_ext_as = 0;\n\n generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both\n if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext\n reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;\n wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;\n wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;\n always @* begin\n if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin\n adjusted_wr_pntr_rd = 0;\n adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n end else begin\n adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n end\n end // always @*\n\n assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;\n assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};\n\n\n always @ (posedge rd_rst_i or posedge RD_CLK)\n begin\n if (rd_rst_i) begin\n rdc_fwft_ext_as <= 0;\n end else begin\n if (!stage2_valid)\n rdc_fwft_ext_as <= #`TCQ 0;\n else if (!stage1_valid && stage2_valid)\n rdc_fwft_ext_as <= #`TCQ 1;\n else\n rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2;\n end \n end // always @ (posedge WR_CLK or posedge WR_CLK)\n end // rdc_fwft_ext\n end\n endgenerate\n\n\n generate if (C_USE_EMBEDDED_REG == 3) begin\n if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext\n reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;\n wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;\n wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;\n always @* begin\n if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin\n adjusted_wr_pntr_rd = 0;\n adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;\n end else begin\n adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n end\n end // always @*\n\n assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;\n assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};\n wire [C_RD_PNTR_WIDTH:0] diff_rd_wr_1;\n // assign diff_rd_wr_1 = diff_rd_wr +2'h2;\n\n always @ (posedge rd_rst_i or posedge RD_CLK)\n begin\n if (rd_rst_i) begin\n rdc_fwft_ext_as <= #`TCQ 0;\n end else begin\n //if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1)))\n // rdc_fwft_ext_as <= 1'b0;\n //else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1))) \n // rdc_fwft_ext_as <= 1'b1;\n //else\n rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ;\n end\n\n\n\nend\nend\nend\nendgenerate\n \n\n //***************************************************************************\n // Assign the read data count value only if it is selected, \n // otherwise output zeros.\n //***************************************************************************\n generate\n if (C_HAS_RD_DATA_COUNT == 1) begin : grdc\n assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ?\n rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] :\n rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];\n end\n endgenerate\n\n generate\n if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc\n assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};\n end\n endgenerate\n\n //***************************************************************************\n // Assign the write data count value only if it is selected, \n // otherwise output zeros\n //***************************************************************************\n generate\n if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc\n assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ?\n wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] :\n wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH];\n end\n endgenerate\n \n generate\n if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc\n assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};\n end\n endgenerate\n\n\n /**************************************************************************\n * Assorted registers for delayed versions of signals\n **************************************************************************/\n //Capture delayed version of valid\n generate\n if (C_HAS_VALID==1) begin : blockVL2\n always @(posedge RD_CLK or posedge rd_rst_i) begin\n if (rd_rst_i == 1'b1) begin\n valid_d1 <= 1'b0;\n valid_d2 <= 1'b0;\n end else begin\n valid_d1 <= #`TCQ valid_i;\n valid_d2 <= #`TCQ valid_d1;\n end \n// if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin\n // valid_d2 <= #`TCQ valid_d1;\n // end \n end \n end\n endgenerate \n \n //Capture delayed version of dout\n /**************************************************************************\n *embedded/fabric reg with no safety ckt\n **************************************************************************/\n generate \n if (C_USE_EMBEDDED_REG < 3) begin\n always @(posedge RD_CLK or posedge rd_rst_i) begin\n if (rd_rst_i == 1'b1) begin\n if (C_USE_DOUT_RST == 1'b1) begin\n @(posedge RD_CLK)\n ideal_dout_d1 <= #`TCQ dout_reset_val;\n ideal_dout <= #`TCQ dout_reset_val;\n end\n // Reset err_type only if ECC is not selected\n if (C_USE_ECC == 0)\n err_type_d1 <= #`TCQ 0;\n end else if (ram_rd_en_d1) begin\n ideal_dout_d1 <= #`TCQ ideal_dout;\n err_type_d1 <= #`TCQ err_type;\n end \n end \n \nend \nendgenerate \n/**************************************************************************\n *embedded + fabric reg with no safety ckt\n **************************************************************************/\n\ngenerate \n if (C_USE_EMBEDDED_REG == 3) begin\n always @(posedge RD_CLK or posedge rd_rst_i) begin\n if (rd_rst_i == 1'b1) begin\n if (C_USE_DOUT_RST == 1'b1) begin\n @(posedge RD_CLK)\n ideal_dout <= #`TCQ dout_reset_val;\n ideal_dout_d1 <= #`TCQ dout_reset_val;\n ideal_dout_both <= #`TCQ dout_reset_val;\n end\n // Reset err_type only if ECC is not selected\n if (C_USE_ECC == 0) begin\n err_type_d1 <= #`TCQ 0;\n err_type_both <= #`TCQ 0;\n end\n end else begin\n if (ram_rd_en_d1) begin\n ideal_dout_both <= #`TCQ ideal_dout;\n err_type_both <= #`TCQ err_type;\n end \n if (fab_rd_en_d1) begin\n ideal_dout_d1 <= #`TCQ ideal_dout_both;\n err_type_d1 <= #`TCQ err_type_both;\n end\n end\n end \n end \nendgenerate \n\n \n /**************************************************************************\n * Overflow and Underflow Flag calculation\n * (handled separately because they don't support rst)\n **************************************************************************/\n generate\n if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw\n always @(posedge WR_CLK) begin\n ideal_overflow <= #`TCQ WR_EN & FULL;\n end\n end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw\n always @(posedge WR_CLK) begin\n //ideal_overflow <= #`TCQ WR_EN & (FULL | wr_rst_i);\n ideal_overflow <= #`TCQ WR_EN & (FULL );\n end\n end\n endgenerate\n\n generate\n if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw\n always @(posedge RD_CLK) begin\n ideal_underflow <= #`TCQ EMPTY & RD_EN;\n end\n end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw\n always @(posedge RD_CLK) begin\n ideal_underflow <= #`TCQ (EMPTY) & RD_EN;\n //ideal_underflow <= #`TCQ (rd_rst_i | EMPTY) & RD_EN;\n end\n end\n endgenerate\n\n /**************************************************************************\n * Write/Read Pointer Synchronization\n **************************************************************************/\n localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1;\n wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];\n wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];\n genvar gss;\n\n generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst\n fifo_generator_v13_1_2_sync_stage\n #(\n .C_WIDTH (C_WR_PNTR_WIDTH)\n )\n rd_stg_inst\n (\n .RST (rd_rst_i), \n .CLK (RD_CLK), \n .DIN (wr_pntr_sync_stgs[gss-1]), \n .DOUT (wr_pntr_sync_stgs[gss])\n );\n \n fifo_generator_v13_1_2_sync_stage\n #(\n .C_WIDTH (C_RD_PNTR_WIDTH)\n )\n wr_stg_inst\n (\n .RST (wr_rst_i), \n .CLK (WR_CLK), \n .DIN (rd_pntr_sync_stgs[gss-1]), \n .DOUT (rd_pntr_sync_stgs[gss])\n );\n end endgenerate // Sync_stage_inst\n\n assign wr_pntr_sync_stgs[0] = wr_pntr_rd1;\n assign rd_pntr_sync_stgs[0] = rd_pntr_wr1;\n always@* begin\n wr_pntr_rd <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];\n rd_pntr_wr <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];\n end\n\n /**************************************************************************\n * Write Domain Logic\n **************************************************************************/\n reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;\n always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp\n if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0)\n wr_pntr <= 0;\n else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1)\n wr_pntr <= #`TCQ 0;\n end\n always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w\n\n /****** Reset fifo (case 1)***************************************/\n if (wr_rst_i == 1'b1) begin\n num_wr_bits <= 0;\n next_num_wr_bits = 0;\n wr_ptr <= C_WR_DEPTH - 1;\n rd_ptr_wrclk <= C_RD_DEPTH - 1;\n ideal_wr_ack <= 0;\n ideal_wr_count <= 0;\n tmp_wr_listsize = 0;\n rd_ptr_wrclk_next <= 0;\n wr_pntr_rd1 <= 0;\n\n end else begin //wr_rst_i==0\n\n wr_pntr_rd1 <= #`TCQ wr_pntr;\n\n //Determine the current number of words in the FIFO\n tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :\n num_wr_bits/C_DIN_WIDTH;\n rd_ptr_wrclk_next = rd_ptr;\n if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin\n next_num_wr_bits = num_wr_bits -\n C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH\n - rd_ptr_wrclk_next);\n end else begin\n next_num_wr_bits = num_wr_bits -\n C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);\n end\n\n //If this is a write, handle the write by adding the value\n // to the linked list, and updating all outputs appropriately\n if (WR_EN == 1'b1) begin\n if (FULL == 1'b1) begin\n\n //If the FIFO is full, do NOT perform the write,\n // update flags accordingly\n if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD \n >= C_FIFO_WR_DEPTH) begin\n //write unsuccessful - do not change contents\n\n //Do not acknowledge the write\n ideal_wr_ack <= #`TCQ 0;\n //Reminder that FIFO is still full\n\n ideal_wr_count <= #`TCQ num_write_words_sized_i;\n\n //If the FIFO is one from full, but reporting full\n end else \n if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==\n C_FIFO_WR_DEPTH-1) begin\n //No change to FIFO\n\n //Write not successful\n ideal_wr_ack <= #`TCQ 0;\n //With DEPTH-1 words in the FIFO, it is almost_full\n\n ideal_wr_count <= #`TCQ num_write_words_sized_i;\n\n\n //If the FIFO is completely empty, but it is\n // reporting FULL for some reason (like reset)\n end else \n if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=\n C_FIFO_WR_DEPTH-2) begin\n //No change to FIFO\n\n //Write not successful\n ideal_wr_ack <= #`TCQ 0;\n //FIFO is really not close to full, so change flag status.\n\n ideal_wr_count <= #`TCQ num_write_words_sized_i;\n end //(tmp_wr_listsize == 0)\n\n end else begin\n\n //If the FIFO is full, do NOT perform the write,\n // update flags accordingly\n if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=\n C_FIFO_WR_DEPTH) begin\n //write unsuccessful - do not change contents\n\n //Do not acknowledge the write\n ideal_wr_ack <= #`TCQ 0;\n //Reminder that FIFO is still full\n\n ideal_wr_count <= #`TCQ num_write_words_sized_i;\n\n //If the FIFO is one from full\n end else \n if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==\n C_FIFO_WR_DEPTH-1) begin\n //Add value on DIN port to FIFO\n write_fifo;\n next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;\n\n //Write successful, so issue acknowledge\n // and no error\n ideal_wr_ack <= #`TCQ 1;\n //This write is CAUSING the FIFO to go full\n\n ideal_wr_count <= #`TCQ num_write_words_sized_i;\n\n //If the FIFO is 2 from full\n end else \n if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == \n C_FIFO_WR_DEPTH-2) begin\n //Add value on DIN port to FIFO\n write_fifo;\n next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;\n //Write successful, so issue acknowledge\n // and no error\n ideal_wr_ack <= #`TCQ 1;\n //Still 2 from full\n\n ideal_wr_count <= #`TCQ num_write_words_sized_i;\n\n //If the FIFO is not close to being full\n end else \n if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <\n C_FIFO_WR_DEPTH-2) begin\n //Add value on DIN port to FIFO\n write_fifo;\n next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;\n //Write successful, so issue acknowledge\n // and no error\n ideal_wr_ack <= #`TCQ 1;\n //Not even close to full.\n\n ideal_wr_count <= num_write_words_sized_i;\n\n end\n\n end\n\n end else begin //(WR_EN == 1'b1)\n\n //If user did not attempt a write, then do not\n // give ack or err\n ideal_wr_ack <= #`TCQ 0;\n ideal_wr_count <= #`TCQ num_write_words_sized_i;\n end\n num_wr_bits <= #`TCQ next_num_wr_bits;\n rd_ptr_wrclk <= #`TCQ rd_ptr;\n\n end //wr_rst_i==0\n end // gen_fifo_w\n\n\n /***************************************************************************\n * Programmable FULL flags\n ***************************************************************************/\n\n wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val;\n wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val;\n\n generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT\n assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC;\n assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC;\n end else begin // STD\n assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL;\n assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL;\n end endgenerate\n\n always @(posedge WR_CLK or posedge wr_rst_i) begin\n\n if (wr_rst_i == 1'b1) begin\n diff_pntr <= 0;\n end else begin\n if (ram_wr_en)\n diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1);\n else if (!ram_wr_en)\n diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr);\n end\n end\n\n\n always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf\n\n if (RST_FULL_FF == 1'b1) begin\n ideal_prog_full <= C_FULL_FLAGS_RST_VAL;\n end else begin\n\n if (RST_FULL_GEN)\n ideal_prog_full <= #`TCQ 0;\n //Single Programmable Full Constant Threshold\n else if (C_PROG_FULL_TYPE == 1) begin\n if (FULL == 0) begin\n if (diff_pntr >= pf_thr_assert_val)\n ideal_prog_full <= #`TCQ 1;\n else\n ideal_prog_full <= #`TCQ 0;\n end else\n ideal_prog_full <= #`TCQ ideal_prog_full;\n //Two Programmable Full Constant Thresholds\n end else if (C_PROG_FULL_TYPE == 2) begin\n if (FULL == 0) begin\n if (diff_pntr >= pf_thr_assert_val)\n ideal_prog_full <= #`TCQ 1;\n else if (diff_pntr < pf_thr_negate_val)\n ideal_prog_full <= #`TCQ 0;\n else\n ideal_prog_full <= #`TCQ ideal_prog_full;\n end else\n ideal_prog_full <= #`TCQ ideal_prog_full;\n //Single Programmable Full Threshold Input\n end else if (C_PROG_FULL_TYPE == 3) begin\n if (FULL == 0) begin\n if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT\n if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC))\n ideal_prog_full <= #`TCQ 1;\n else\n ideal_prog_full <= #`TCQ 0;\n end else begin // STD\n if (diff_pntr >= PROG_FULL_THRESH)\n ideal_prog_full <= #`TCQ 1;\n else\n ideal_prog_full <= #`TCQ 0;\n end\n end else\n ideal_prog_full <= #`TCQ ideal_prog_full;\n //Two Programmable Full Threshold Inputs\n end else if (C_PROG_FULL_TYPE == 4) begin\n if (FULL == 0) begin\n if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT\n if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC))\n ideal_prog_full <= #`TCQ 1;\n else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC))\n ideal_prog_full <= #`TCQ 0;\n else\n ideal_prog_full <= #`TCQ ideal_prog_full;\n end else begin // STD\n if (diff_pntr >= PROG_FULL_THRESH_ASSERT)\n ideal_prog_full <= #`TCQ 1;\n else if (diff_pntr < PROG_FULL_THRESH_NEGATE)\n ideal_prog_full <= #`TCQ 0;\n else\n ideal_prog_full <= #`TCQ ideal_prog_full;\n end\n end else\n ideal_prog_full <= #`TCQ ideal_prog_full;\n end // C_PROG_FULL_TYPE\n\n end //wr_rst_i==0\n end //\n\n \n /**************************************************************************\n * Read Domain Logic\n **************************************************************************/\n\n\n /*********************************************************\n * Programmable EMPTY flags\n *********************************************************/\n //Determine the Assert and Negate thresholds for Programmable Empty\n\n wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val;\n wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val;\n reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd = 0;\n\n always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe\n\n if (rd_rst_i) begin\n diff_pntr_rd <= 0;\n ideal_prog_empty <= 1'b1;\n end else begin\n if (ram_rd_en)\n diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1;\n else if (!ram_rd_en)\n diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr);\n else\n diff_pntr_rd <= #`TCQ diff_pntr_rd;\n \n if (C_PROG_EMPTY_TYPE == 1) begin\n if (EMPTY == 0) begin\n if (diff_pntr_rd <= pe_thr_assert_val)\n ideal_prog_empty <= #`TCQ 1;\n else\n ideal_prog_empty <= #`TCQ 0;\n end else\n ideal_prog_empty <= #`TCQ ideal_prog_empty;\n end else if (C_PROG_EMPTY_TYPE == 2) begin\n if (EMPTY == 0) begin\n if (diff_pntr_rd <= pe_thr_assert_val)\n ideal_prog_empty <= #`TCQ 1;\n else if (diff_pntr_rd > pe_thr_negate_val)\n ideal_prog_empty <= #`TCQ 0;\n else\n ideal_prog_empty <= #`TCQ ideal_prog_empty;\n end else\n ideal_prog_empty <= #`TCQ ideal_prog_empty;\n end else if (C_PROG_EMPTY_TYPE == 3) begin\n if (EMPTY == 0) begin\n if (diff_pntr_rd <= pe_thr_assert_val)\n ideal_prog_empty <= #`TCQ 1;\n else\n ideal_prog_empty <= #`TCQ 0;\n end else\n ideal_prog_empty <= #`TCQ ideal_prog_empty;\n end else if (C_PROG_EMPTY_TYPE == 4) begin\n if (EMPTY == 0) begin\n if (diff_pntr_rd <= pe_thr_assert_val)\n ideal_prog_empty <= #`TCQ 1;\n else if (diff_pntr_rd > pe_thr_negate_val)\n ideal_prog_empty <= #`TCQ 0;\n else\n ideal_prog_empty <= #`TCQ ideal_prog_empty;\n end else\n ideal_prog_empty <= #`TCQ ideal_prog_empty;\n end //C_PROG_EMPTY_TYPE\n end\n end // gen_pe\n\n generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input\n assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH;\n end endgenerate // single_pe_thr_input\n\n generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input\n assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT;\n assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE;\n end endgenerate // multiple_pe_thr_input\n\n generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const\n assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL;\n assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?\n C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL;\n end endgenerate // single_multiple_pe_thr_const\n\n always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp\n if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n rd_pntr <= 0;\n else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1)\n rd_pntr <= #`TCQ 0;\n end\n always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as\n\n /****** Reset fifo (case 1)***************************************/\n if (rd_rst_i) begin\n num_rd_bits <= 0;\n next_num_rd_bits = 0;\n rd_ptr <= C_RD_DEPTH -1;\n rd_pntr_wr1 <= 0;\n wr_ptr_rdclk <= C_WR_DEPTH -1;\n \n // DRAM resets asynchronously\n if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)\n ideal_dout <= dout_reset_val;\n \n // Reset err_type only if ECC is not selected\n if (C_USE_ECC == 0) begin\n err_type <= 0;\n err_type_d1 <= 0;\n err_type_both <= 0;\n end\n ideal_valid <= 1'b0;\n ideal_rd_count <= 0;\n\n end else begin //rd_rst_i==0\n\n rd_pntr_wr1 <= #`TCQ rd_pntr;\n\n //Determine the current number of words in the FIFO\n tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :\n num_rd_bits/C_DOUT_WIDTH;\n wr_ptr_rdclk_next = wr_ptr;\n\n if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin\n next_num_rd_bits = num_rd_bits +\n C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH\n - wr_ptr_rdclk_next);\n end else begin\n next_num_rd_bits = num_rd_bits +\n C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);\n end\n\n /*****************************************************************/\n // Read Operation - Read Latency 1\n /*****************************************************************/\n if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin\n ideal_valid <= #`TCQ 1'b0;\n\n if (ram_rd_en == 1'b1) begin\n\n if (EMPTY == 1'b1) begin\n\n //If the FIFO is completely empty, and is reporting empty\n if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)\n begin\n //Do not change the contents of the FIFO\n\n //Do not acknowledge the read from empty FIFO\n ideal_valid <= #`TCQ 1'b0;\n //Reminder that FIFO is still empty\n\n ideal_rd_count <= #`TCQ num_read_words_sized_i;\n end // if (tmp_rd_listsize <= 0)\n\n //If the FIFO is one from empty, but it is reporting empty\n else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)\n begin\n //Do not change the contents of the FIFO\n\n //Do not acknowledge the read from empty FIFO\n ideal_valid <= #`TCQ 1'b0;\n //Note that FIFO is no longer empty, but is almost empty (has one word left)\n\n ideal_rd_count <= #`TCQ num_read_words_sized_i;\n\n end // if (tmp_rd_listsize == 1)\n\n //If the FIFO is two from empty, and is reporting empty\n else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)\n begin\n //Do not change the contents of the FIFO\n\n //Do not acknowledge the read from empty FIFO\n ideal_valid <= #`TCQ 1'b0;\n //Fifo has two words, so is neither empty or almost empty\n\n ideal_rd_count <= #`TCQ num_read_words_sized_i;\n\n end // if (tmp_rd_listsize == 2)\n\n //If the FIFO is not close to empty, but is reporting that it is\n // Treat the FIFO as empty this time, but unset EMPTY flags.\n if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n end // else: if(ideal_empty == 1'b1)\n\n else //if (ideal_empty == 1'b0)\n begin\n\n //If the FIFO is completely full, and we are successfully reading from it\n if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)\n begin\n //Read the value from the FIFO\n read_fifo;\n next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n //Acknowledge the read from the FIFO, no error\n ideal_valid <= #`TCQ 1'b1;\n //Not close to empty\n\n ideal_rd_count <= #`TCQ num_read_words_sized_i;\n\n end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)\n\n //If the FIFO is not close to being empty\n else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))\n begin\n //Read the value from the FIFO\n read_fifo;\n next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n //Acknowledge the read from the FIFO, no error\n ideal_valid <= #`TCQ 1'b1;\n //Not close to empty\n\n ideal_rd_count <= #`TCQ num_read_words_sized_i;\n\n end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n\n //If the FIFO is two from empty\n else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)\n begin\n //Read the value from the FIFO\n read_fifo;\n next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n //Acknowledge the read from the FIFO, no error\n ideal_valid <= #`TCQ 1'b1;\n //Fifo is not yet empty. It is going almost_empty\n\n ideal_rd_count <= #`TCQ num_read_words_sized_i;\n\n end // if (tmp_rd_listsize == 2)\n\n //If the FIFO is one from empty\n else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))\n begin\n //Read the value from the FIFO\n read_fifo;\n next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n //Acknowledge the read from the FIFO, no error\n ideal_valid <= #`TCQ 1'b1;\n //Note that FIFO is GOING empty\n\n ideal_rd_count <= #`TCQ num_read_words_sized_i;\n\n end // if (tmp_rd_listsize == 1)\n\n\n //If the FIFO is completely empty\n else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)\n begin\n //Do not change the contents of the FIFO\n\n //Do not acknowledge the read from empty FIFO\n ideal_valid <= #`TCQ 1'b0;\n\n ideal_rd_count <= #`TCQ num_read_words_sized_i;\n\n end // if (tmp_rd_listsize <= 0)\n\n end // if (ideal_empty == 1'b0)\n\n end //(RD_EN == 1'b1)\n\n else //if (RD_EN == 1'b0)\n begin\n //If user did not attempt a read, do not give an ack or err\n ideal_valid <= #`TCQ 1'b0;\n\n ideal_rd_count <= #`TCQ num_read_words_sized_i;\n\n end // else: !if(RD_EN == 1'b1)\n\n /*****************************************************************/\n // Read Operation - Read Latency 0\n /*****************************************************************/\n end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin\n ideal_valid <= #`TCQ 1'b0;\n if (ram_rd_en == 1'b1) begin\n\n if (EMPTY == 1'b1) begin\n\n //If the FIFO is completely empty, and is reporting empty\n if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin\n //Do not change the contents of the FIFO\n\n //Do not acknowledge the read from empty FIFO\n ideal_valid <= #`TCQ 1'b0;\n //Reminder that FIFO is still empty\n\n ideal_rd_count <= #`TCQ num_read_words_sized_i;\n\n //If the FIFO is one from empty, but it is reporting empty\n end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin\n //Do not change the contents of the FIFO\n\n //Do not acknowledge the read from empty FIFO\n ideal_valid <= #`TCQ 1'b0;\n //Note that FIFO is no longer empty, but is almost empty (has one word left)\n\n ideal_rd_count <= #`TCQ num_read_words_sized_i;\n\n //If the FIFO is two from empty, and is reporting empty\n end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin\n //Do not change the contents of the FIFO\n\n //Do not acknowledge the read from empty FIFO\n ideal_valid <= #`TCQ 1'b0;\n //Fifo has two words, so is neither empty or almost empty\n\n ideal_rd_count <= #`TCQ num_read_words_sized_i;\n\n //If the FIFO is not close to empty, but is reporting that it is\n // Treat the FIFO as empty this time, but unset EMPTY flags.\n end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&\n (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))\n\n end else begin\n\n //If the FIFO is completely full, and we are successfully reading from it\n if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin\n //Read the value from the FIFO\n read_fifo;\n next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n //Acknowledge the read from the FIFO, no error\n ideal_valid <= #`TCQ 1'b1;\n //Not close to empty\n\n ideal_rd_count <= #`TCQ num_read_words_sized_i;\n\n //If the FIFO is not close to being empty\n end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&\n (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin\n //Read the value from the FIFO\n read_fifo;\n next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n //Acknowledge the read from the FIFO, no error\n ideal_valid <= #`TCQ 1'b1;\n //Not close to empty\n\n ideal_rd_count <= #`TCQ num_read_words_sized_i;\n\n //If the FIFO is two from empty\n end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin\n //Read the value from the FIFO\n read_fifo;\n next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n //Acknowledge the read from the FIFO, no error\n ideal_valid <= #`TCQ 1'b1;\n //Fifo is not yet empty. It is going almost_empty\n\n ideal_rd_count <= #`TCQ num_read_words_sized_i;\n\n //If the FIFO is one from empty\n end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin\n //Read the value from the FIFO\n read_fifo;\n next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n //Acknowledge the read from the FIFO, no error\n ideal_valid <= #`TCQ 1'b1;\n //Note that FIFO is GOING empty\n\n ideal_rd_count <= #`TCQ num_read_words_sized_i;\n\n //If the FIFO is completely empty\n end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin\n //Do not change the contents of the FIFO\n\n //Do not acknowledge the read from empty FIFO\n ideal_valid <= #`TCQ 1'b0;\n //Reminder that FIFO is still empty\n\n ideal_rd_count <= #`TCQ num_read_words_sized_i;\n\n end // if (tmp_rd_listsize <= 0)\n\n end // if (ideal_empty == 1'b0)\n\n end else begin//(RD_EN == 1'b0)\n\n \n //If user did not attempt a read, do not give an ack or err\n ideal_valid <= #`TCQ 1'b0;\n ideal_rd_count <= #`TCQ num_read_words_sized_i;\n\n end // else: !if(RD_EN == 1'b1)\n end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)\n\n num_rd_bits <= #`TCQ next_num_rd_bits;\n wr_ptr_rdclk <= #`TCQ wr_ptr;\n end //rd_rst_i==0\n end //always gen_fifo_r_as\n\nendmodule // fifo_generator_v13_1_2_bhv_ver_as\n\n\n/*******************************************************************************\n * Declaration of Low Latency Asynchronous FIFO\n ******************************************************************************/\nmodule fifo_generator_v13_1_2_beh_ver_ll_afifo\n \n /***************************************************************************\n * Declare user parameters and their defaults\n ***************************************************************************/\n #(\n parameter C_DIN_WIDTH = 8,\n parameter C_DOUT_RST_VAL = \"\",\n parameter C_DOUT_WIDTH = 8,\n parameter C_FULL_FLAGS_RST_VAL = 1,\n parameter C_HAS_RD_DATA_COUNT = 0,\n parameter C_HAS_WR_DATA_COUNT = 0,\n parameter C_RD_DEPTH = 256,\n parameter C_RD_PNTR_WIDTH = 8,\n parameter C_USE_DOUT_RST = 0,\n parameter C_WR_DATA_COUNT_WIDTH = 2,\n parameter C_WR_DEPTH = 256,\n parameter C_WR_PNTR_WIDTH = 8,\n parameter C_FIFO_TYPE = 0\n )\n\n /***************************************************************************\n * Declare Input and Output Ports\n ***************************************************************************/\n (\n input [C_DIN_WIDTH-1:0] DIN,\n input RD_CLK,\n input RD_EN,\n input WR_RST,\n input RD_RST,\n input WR_CLK,\n input WR_EN,\n output reg [C_DOUT_WIDTH-1:0] DOUT = 0,\n output reg EMPTY = 1'b1,\n output reg FULL = C_FULL_FLAGS_RST_VAL\n );\n\n //-----------------------------------------------------------------------------\n // Low Latency Asynchronous FIFO\n //-----------------------------------------------------------------------------\n\n // Memory which will be used to simulate a FIFO\n reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n integer i;\n initial begin\n for (i = 0; i < C_WR_DEPTH; i = i + 1)\n memory[i] = 0;\n end\n\n reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0;\n wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo;\n reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0;\n reg ll_afifo_full = 1'b0;\n reg ll_afifo_empty = 1'b1;\n wire write_allow;\n wire read_allow;\n\n assign write_allow = WR_EN & ~ll_afifo_full;\n assign read_allow = RD_EN & ~ll_afifo_empty;\n\n //-----------------------------------------------------------------------------\n // Write Pointer Generation\n //-----------------------------------------------------------------------------\n always @(posedge WR_CLK or posedge WR_RST) begin\n if (WR_RST)\n wr_pntr_ll_afifo <= 0;\n else if (write_allow)\n wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1;\n end\n\n //-----------------------------------------------------------------------------\n // Read Pointer Generation\n //-----------------------------------------------------------------------------\n always @(posedge RD_CLK or posedge RD_RST) begin\n if (RD_RST)\n rd_pntr_ll_afifo_q <= 0;\n else\n rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo;\n end\n assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q;\n \n //-----------------------------------------------------------------------------\n // Fill the Memory\n //-----------------------------------------------------------------------------\n always @(posedge WR_CLK) begin\n if (write_allow)\n memory[wr_pntr_ll_afifo] <= #`TCQ DIN;\n end\n\n //-----------------------------------------------------------------------------\n // Generate DOUT\n //-----------------------------------------------------------------------------\n always @(posedge RD_CLK) begin\n DOUT <= #`TCQ memory[rd_pntr_ll_afifo];\n end\n\n //-----------------------------------------------------------------------------\n // Generate EMPTY\n //-----------------------------------------------------------------------------\n always @(posedge RD_CLK or posedge RD_RST) begin\n if (RD_RST)\n ll_afifo_empty <= 1'b1;\n else\n ll_afifo_empty <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) | \n (read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1))));\n end\n\n //-----------------------------------------------------------------------------\n // Generate FULL\n //-----------------------------------------------------------------------------\n always @(posedge WR_CLK or posedge WR_RST) begin\n if (WR_RST)\n ll_afifo_full <= 1'b1;\n else\n ll_afifo_full <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) | \n (write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2))));\n end\n\n always @* begin\n FULL <= ll_afifo_full;\n EMPTY <= ll_afifo_empty;\n end\n\nendmodule // fifo_generator_v13_1_2_beh_ver_ll_afifo\n\n/*******************************************************************************\n * Declaration of top-level module\n ******************************************************************************/\nmodule fifo_generator_v13_1_2_bhv_ver_ss\n \n /**************************************************************************\n * Declare user parameters and their defaults\n *************************************************************************/\n #(\n parameter C_FAMILY = \"virtex7\",\n parameter C_DATA_COUNT_WIDTH = 2,\n parameter C_DIN_WIDTH = 8,\n parameter C_DOUT_RST_VAL = \"\",\n parameter C_DOUT_WIDTH = 8,\n parameter C_FULL_FLAGS_RST_VAL = 1,\n parameter C_HAS_ALMOST_EMPTY = 0,\n parameter C_HAS_ALMOST_FULL = 0,\n parameter C_HAS_DATA_COUNT = 0,\n parameter C_HAS_OVERFLOW = 0,\n parameter C_HAS_RD_DATA_COUNT = 0,\n parameter C_HAS_RST = 0,\n parameter C_HAS_SRST = 0,\n parameter C_HAS_UNDERFLOW = 0,\n parameter C_HAS_VALID = 0,\n parameter C_HAS_WR_ACK = 0,\n parameter C_HAS_WR_DATA_COUNT = 0,\n parameter C_IMPLEMENTATION_TYPE = 0,\n parameter C_MEMORY_TYPE = 1,\n parameter C_OVERFLOW_LOW = 0,\n parameter C_PRELOAD_LATENCY = 1,\n parameter C_PRELOAD_REGS = 0,\n parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,\n parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,\n parameter C_PROG_EMPTY_TYPE = 0,\n parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,\n parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,\n parameter C_PROG_FULL_TYPE = 0,\n parameter C_RD_DATA_COUNT_WIDTH = 2,\n parameter C_RD_DEPTH = 256,\n parameter C_RD_PNTR_WIDTH = 8,\n parameter C_UNDERFLOW_LOW = 0,\n parameter C_USE_DOUT_RST = 0,\n parameter C_USE_EMBEDDED_REG = 0,\n parameter C_EN_SAFETY_CKT = 0,\n parameter C_USE_FWFT_DATA_COUNT = 0,\n parameter C_VALID_LOW = 0,\n parameter C_WR_ACK_LOW = 0,\n parameter C_WR_DATA_COUNT_WIDTH = 2,\n parameter C_WR_DEPTH = 256,\n parameter C_WR_PNTR_WIDTH = 8,\n parameter C_USE_ECC = 0, \n parameter C_ENABLE_RST_SYNC = 1,\n parameter C_ERROR_INJECTION_TYPE = 0,\n parameter C_FIFO_TYPE = 0 \n )\n \n /**************************************************************************\n * Declare Input and Output Ports\n *************************************************************************/\n (\n //Inputs\n input SAFETY_CKT_WR_RST,\n input CLK,\n input [C_DIN_WIDTH-1:0] DIN,\n input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,\n input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,\n input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,\n input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,\n input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,\n input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,\n input RD_EN,\n input RD_EN_USER,\n input USER_EMPTY_FB,\n input RST,\n input RST_FULL_GEN,\n input RST_FULL_FF,\n input SRST,\n input WR_EN,\n input INJECTDBITERR,\n input INJECTSBITERR,\n input WR_RST_BUSY,\n input RD_RST_BUSY,\n \n //Outputs \n output ALMOST_EMPTY,\n output ALMOST_FULL,\n output reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0,\n output [C_DOUT_WIDTH-1:0] DOUT,\n output EMPTY,\n output reg EMPTY_FB = 1'b1,\n output FULL,\n output OVERFLOW,\n output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,\n output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,\n output PROG_EMPTY,\n output PROG_FULL,\n output VALID,\n output UNDERFLOW,\n output WR_ACK,\n output SBITERR,\n output DBITERR\n );\n\n\n reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;\n reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;\n wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss;\n wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss;\n reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;\n /***************************************************************************\n * Parameters used as constants\n **************************************************************************/\n localparam IS_8SERIES = (C_FAMILY == \"virtexu\" || C_FAMILY == \"kintexu\" || C_FAMILY == \"artixu\" || C_FAMILY == \"virtexuplus\" || C_FAMILY == \"zynquplus\" || C_FAMILY == \"kintexuplus\") ? 1 : 0;\n localparam C_DEPTH_RATIO_WR = \n (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;\n localparam C_DEPTH_RATIO_RD = \n (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;\n //localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;\n //localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;\n localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ; \n\n\n // C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC\n // -----------------|------------------|-----------------|---------------\n // 1 | 8 | C_RD_PNTR_WIDTH | 2\n // 1 | 4 | C_RD_PNTR_WIDTH | 2\n // 1 | 2 | C_RD_PNTR_WIDTH | 2\n // 1 | 1 | C_WR_PNTR_WIDTH | 2\n // 2 | 1 | C_WR_PNTR_WIDTH | 4\n // 4 | 1 | C_WR_PNTR_WIDTH | 8\n // 8 | 1 | C_WR_PNTR_WIDTH | 16\n \n localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n //wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);\n localparam EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);\n //localparam EXTRA_WORDS_PE_PARAM = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);\n\n localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;\n \n localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);\n \n localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;\n \n localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);\n\n\n //When RST is present, set FULL reset value to '1'.\n //If core has no RST, make sure FULL powers-on as '0'.\n //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not \n //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0.\n // Therefore, during SRST, all the FULL flags reset to 0.\n localparam C_HAS_FAST_FIFO = 0;\n localparam C_FIFO_WR_DEPTH = C_WR_DEPTH;\n localparam C_FIFO_RD_DEPTH = C_RD_DEPTH;\n // Local parameters used to determine whether to inject ECC error or not\n localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;\n localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;\n localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;\n localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION;\n localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH;\n localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1;\n localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;\n localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}}; \n localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}}; \n\n\n /**************************************************************************\n * FIFO Contents Tracking and Data Count Calculations\n *************************************************************************/\n // Memory which will be used to simulate a FIFO\n reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];\n reg [1:0] ecc_err[C_WR_DEPTH-1:0];\n\n \n /**************************************************************************\n * Internal Registers and wires\n *************************************************************************/\n\n //Temporary signals used for calculating the model's outputs. These\n //are only used in the assign statements immediately following wire,\n //parameter, and function declarations.\n wire underflow_i;\n wire valid_i;\n wire valid_out;\n reg [31:0] num_wr_bits;\n reg [31:0] num_rd_bits;\n reg [31:0] next_num_wr_bits;\n reg [31:0] next_num_rd_bits;\n\n //The write pointer - tracks write operations\n // (Works opposite to core: wr_ptr is a DOWN counter)\n reg [31:0] wr_ptr;\n reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;\n reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;\n reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;\n reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;\n reg wr_rst_d1 =0;\n\n //The read pointer - tracks read operations\n // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)\n reg [31:0] rd_ptr;\n reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;\n reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;\n reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;\n reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;\n reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;\n\n wire ram_rd_en;\n wire empty_int;\n wire almost_empty_int;\n wire ram_wr_en;\n wire full_int;\n wire almost_full_int;\n reg ram_rd_en_reg = 1'b0;\n reg ram_rd_en_d1 = 1'b0;\n reg fab_rd_en_d1 = 1'b0;\n wire srst_rrst_busy;\n\n\n\n //Ideal FIFO signals. These are the raw output of the behavioral model,\n //which behaves like an ideal FIFO.\n reg [1:0] err_type = 0;\n reg [1:0] err_type_d1 = 0;\n reg [1:0] err_type_both = 0;\n reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;\n reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;\n reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0;\n wire [C_DOUT_WIDTH-1:0] ideal_dout_out;\n wire fwft_enabled;\n reg ideal_wr_ack = 0;\n reg ideal_valid = 0;\n reg ideal_overflow = C_OVERFLOW_LOW;\n reg ideal_underflow = C_UNDERFLOW_LOW;\n\n reg full_i = C_FULL_FLAGS_RST_VAL;\n reg full_i_temp = 0;\n reg empty_i = 1;\n reg almost_full_i = 0;\n reg almost_empty_i = 1;\n reg prog_full_i = 0;\n reg prog_empty_i = 1;\n reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0;\n reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0;\n wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;\n wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;\n reg [C_RD_PNTR_WIDTH-1:0] diff_count = 0;\n\n reg write_allow_q = 0;\n reg read_allow_q = 0;\n reg valid_d1 = 0;\n reg valid_both = 0;\n reg valid_d2 = 0;\n wire rst_i;\n wire srst_i;\n\n //user specified value for reseting the size of the fifo\n reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;\n\n reg [31:0] wr_ptr_rdclk;\n reg [31:0] wr_ptr_rdclk_next;\n reg [31:0] rd_ptr_wrclk;\n reg [31:0] rd_ptr_wrclk_next;\n\n\n\n\n /****************************************************************************\n * Function Declarations\n ***************************************************************************/\n\n /****************************************************************************\n * hexstr_conv\n * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n ***************************************************************************/\n function [C_DOUT_WIDTH-1:0] hexstr_conv;\n input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n integer index,i,j;\n reg [3:0] bin;\n\n begin\n index = 0;\n hexstr_conv = 'b0;\n for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin\n case (def_data[7:0])\n 8'b00000000 : begin\n bin = 4'b0000;\n i = -1;\n end\n 8'b00110000 : bin = 4'b0000;\n 8'b00110001 : bin = 4'b0001;\n 8'b00110010 : bin = 4'b0010;\n 8'b00110011 : bin = 4'b0011;\n 8'b00110100 : bin = 4'b0100;\n 8'b00110101 : bin = 4'b0101;\n 8'b00110110 : bin = 4'b0110;\n 8'b00110111 : bin = 4'b0111;\n 8'b00111000 : bin = 4'b1000;\n 8'b00111001 : bin = 4'b1001;\n 8'b01000001 : bin = 4'b1010;\n 8'b01000010 : bin = 4'b1011;\n 8'b01000011 : bin = 4'b1100;\n 8'b01000100 : bin = 4'b1101;\n 8'b01000101 : bin = 4'b1110;\n 8'b01000110 : bin = 4'b1111;\n 8'b01100001 : bin = 4'b1010;\n 8'b01100010 : bin = 4'b1011;\n 8'b01100011 : bin = 4'b1100;\n 8'b01100100 : bin = 4'b1101;\n 8'b01100101 : bin = 4'b1110;\n 8'b01100110 : bin = 4'b1111;\n default : begin\n bin = 4'bx;\n end\n endcase\n for( j=0; j<4; j=j+1) begin\n if ((index*4)+j < C_DOUT_WIDTH) begin\n hexstr_conv[(index*4)+j] = bin[j];\n end\n end\n index = index + 1;\n def_data = def_data >> 8;\n end\n end\n endfunction\n /**************************************************************************\n * log2_val\n * Returns the 'log2' value for the input value for the supported ratios\n ***************************************************************************/\n function [31:0] log2_val;\n input [31:0] binary_val;\n\n begin\n if (binary_val == 8) begin\n log2_val = 3;\n end else if (binary_val == 4) begin\n log2_val = 2;\n end else begin\n log2_val = 1;\n end\n end\n endfunction\n\n reg ideal_prog_full = 0;\n reg ideal_prog_empty = 1;\n reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;\n reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;\n\n //Assorted reg values for delayed versions of signals \n //reg valid_d1 = 0;\n \n \n //user specified value for reseting the size of the fifo\n //reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;\n \n //temporary registers for WR_RESPONSE_LATENCY feature\n \n integer tmp_wr_listsize;\n integer tmp_rd_listsize;\n \n //Signal for registered version of prog full and empty\n \n //Threshold values for Programmable Flags\n integer prog_empty_actual_thresh_assert;\n integer prog_empty_actual_thresh_negate;\n integer prog_full_actual_thresh_assert;\n integer prog_full_actual_thresh_negate;\n\n\n /**************************************************************************\n * write_fifo\n * This task writes a word to the FIFO memory and updates the \n * write pointer.\n * FIFO size is relative to write domain.\n ***************************************************************************/\n task write_fifo;\n begin\n memory[wr_ptr] <= DIN;\n wr_pntr <= #`TCQ wr_pntr + 1;\n // Store the type of error injection (double/single) on write\n case (C_ERROR_INJECTION_TYPE)\n 3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};\n 2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};\n 1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};\n default: ecc_err[wr_ptr] <= 0;\n endcase\n // (Works opposite to core: wr_ptr is a DOWN counter)\n if (wr_ptr == 0) begin\n wr_ptr <= C_WR_DEPTH - 1;\n end else begin\n wr_ptr <= wr_ptr - 1;\n end\n end\n endtask // write_fifo\n\n /**************************************************************************\n * read_fifo\n * This task reads a word from the FIFO memory and updates the read \n * pointer. It's output is the ideal_dout bus.\n * FIFO size is relative to write domain.\n ***************************************************************************/\n task read_fifo;\n integer i;\n reg [C_DOUT_WIDTH-1:0] tmp_dout;\n reg [C_DIN_WIDTH-1:0] memory_read;\n reg [31:0] tmp_rd_ptr;\n reg [31:0] rd_ptr_high;\n reg [31:0] rd_ptr_low;\n reg [1:0] tmp_ecc_err;\n begin\n rd_pntr <= #`TCQ rd_pntr + 1;\n\n // output is wider than input\n if (reads_per_write == 0) begin\n tmp_dout = 0;\n tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);\n for (i = writes_per_read - 1; i >= 0; i = i - 1) begin\n tmp_dout = tmp_dout << C_DIN_WIDTH;\n tmp_dout = tmp_dout | memory[tmp_rd_ptr];\n \n // (Works opposite to core: rd_ptr is a DOWN counter)\n if (tmp_rd_ptr == 0) begin\n tmp_rd_ptr = C_WR_DEPTH - 1;\n end else begin\n tmp_rd_ptr = tmp_rd_ptr - 1;\n end\n end\n\n // output is symmetric\n end else if (reads_per_write == 1) begin\n tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];\n // Retreive the error injection type. Based on the error injection type\n // corrupt the output data.\n tmp_ecc_err = ecc_err[rd_ptr];\n if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin\n if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error\n if (C_DOUT_WIDTH == 1) begin\n $display(\"FAILURE : Data width must be >= 2 for double bit error injection.\");\n $finish;\n end else if (C_DOUT_WIDTH == 2)\n tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};\n else\n tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};\n end else begin\n tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];\n end\n err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};\n end else begin\n err_type <= 0;\n end\n\n // input is wider than output\n end else begin\n rd_ptr_high = rd_ptr >> log2_reads_per_write;\n rd_ptr_low = rd_ptr & (reads_per_write - 1);\n memory_read = memory[rd_ptr_high];\n tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);\n end\n ideal_dout <= tmp_dout;\n \n // (Works opposite to core: rd_ptr is a DOWN counter)\n if (rd_ptr == 0) begin\n rd_ptr <= C_RD_DEPTH - 1;\n end else begin\n rd_ptr <= rd_ptr - 1;\n end\n\n end\n endtask\n\n\n \n /*************************************************************************\n * Initialize Signals for clean power-on simulation\n *************************************************************************/\n initial begin\n num_wr_bits = 0;\n num_rd_bits = 0;\n next_num_wr_bits = 0;\n next_num_rd_bits = 0;\n rd_ptr = C_RD_DEPTH - 1;\n wr_ptr = C_WR_DEPTH - 1;\n wr_pntr = 0;\n rd_pntr = 0;\n rd_ptr_wrclk = rd_ptr;\n wr_ptr_rdclk = wr_ptr;\n dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);\n ideal_dout = dout_reset_val;\n err_type = 0;\n err_type_d1 = 0;\n err_type_both = 0;\n ideal_dout_d1 = dout_reset_val;\n ideal_dout_both = dout_reset_val;\n ideal_wr_ack = 1'b0;\n ideal_valid = 1'b0;\n valid_d1 = 1'b0;\n valid_both = 1'b0;\n ideal_overflow = C_OVERFLOW_LOW;\n ideal_underflow = C_UNDERFLOW_LOW;\n ideal_wr_count = 0;\n ideal_rd_count = 0;\n ideal_prog_full = 1'b0;\n ideal_prog_empty = 1'b1;\n\n end\n\n\n /*************************************************************************\n * Connect the module inputs and outputs to the internal signals of the\n * behavioral model.\n *************************************************************************/\n //Inputs\n /*\n wire CLK;\n wire [C_DIN_WIDTH-1:0] DIN;\n wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;\n wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;\n wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;\n wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;\n wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;\n wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;\n wire RD_EN;\n wire RST;\n wire WR_EN;\n */\n\n // Assign ALMOST_EPMTY\n generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae\n assign ALMOST_EMPTY = almost_empty_i;\n end else begin : gnae\n assign ALMOST_EMPTY = 0;\n end endgenerate // gae\n\n // Assign ALMOST_FULL\n generate if (C_HAS_ALMOST_FULL==1) begin : gaf\n assign ALMOST_FULL = almost_full_i;\n end else begin : gnaf\n assign ALMOST_FULL = 0;\n end endgenerate // gaf\n\n // Dout may change behavior based on latency\n localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?\n 1: 0;\n assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?\n 1: 0;\n assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?\n ideal_dout_d1: ideal_dout; \n assign DOUT = ideal_dout_out;\n\n // Assign SBITERR and DBITERR based on latency \n assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && \n ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n err_type_d1[0]: err_type[0]; \n assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&\n ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&\n (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?\n err_type_d1[1]: err_type[1]; \n\n assign EMPTY = empty_i;\n assign FULL = full_i;\n //saftey_ckt with one register\n\n generate\n if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin\n \n reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;\n reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;\n reg [1:0] rst_delayed_sft1 =1;\n reg [1:0] rst_delayed_sft2 =1;\n reg [1:0] rst_delayed_sft3 =1;\n reg [1:0] rst_delayed_sft4 =1;\n \n always@(posedge CLK)\n begin\n rst_delayed_sft1 <= #`TCQ rst_i;\n rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n end\n always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK)\n begin\n if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin \n ram_rd_en_d1 <= #`TCQ 1'b0;\n valid_d1 <= #`TCQ 1'b0;\n end\n else begin\n ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));\n valid_d1 <= #`TCQ valid_i;\n end\n end\n \n always@(posedge rst_delayed_sft2 or posedge CLK) \n begin\n if (rst_delayed_sft2 == 1'b1) begin\n if (C_USE_DOUT_RST == 1'b1) begin\n @(posedge CLK)\n ideal_dout_d1 <= #`TCQ dout_reset_val;\n end\n end\n else if (srst_rrst_busy == 1'b1) begin\n if (C_USE_DOUT_RST == 1'b1) begin\n ideal_dout_d1 <= #`TCQ dout_reset_val;\n end\n end else if (ram_rd_en_d1) begin\n ideal_dout_d1 <= #`TCQ ideal_dout;\n err_type_d1[0] <= #`TCQ err_type[0];\n err_type_d1[1] <= #`TCQ err_type[1];\n end\n end \n end //if \n endgenerate \n\n//safety ckt with both registers\n\ngenerate\n if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n \n reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;\n reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;\n reg [1:0] rst_delayed_sft1 =1;\n reg [1:0] rst_delayed_sft2 =1;\n reg [1:0] rst_delayed_sft3 =1;\n reg [1:0] rst_delayed_sft4 =1;\n \n always@(posedge CLK) begin\n rst_delayed_sft1 <= #`TCQ rst_i;\n rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n end\n always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin\n if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin \n ram_rd_en_d1 <= #`TCQ 1'b0;\n valid_d1 <= #`TCQ 1'b0;\n end else begin\n ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));\n fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;\n valid_both <= #`TCQ valid_i;\n valid_d1 <= #`TCQ valid_both;\n end\n end\n\n always@(posedge rst_delayed_sft2 or posedge CLK) begin\n if (rst_delayed_sft2 == 1'b1) begin\n if (C_USE_DOUT_RST == 1'b1) begin\n @(posedge CLK)\n ideal_dout_d1 <= #`TCQ dout_reset_val;\n end\n end else if (srst_rrst_busy == 1'b1) begin\n if (C_USE_DOUT_RST == 1'b1) begin\n ideal_dout_d1 <= #`TCQ dout_reset_val;\n end\n end else begin \n if (ram_rd_en_d1) begin\n ideal_dout_both <= #`TCQ ideal_dout;\n err_type_both[0] <= #`TCQ err_type[0];\n err_type_both[1] <= #`TCQ err_type[1];\n end\n if (fab_rd_en_d1) begin\n ideal_dout_d1 <= #`TCQ ideal_dout_both;\n err_type_d1[0] <= #`TCQ err_type_both[0];\n err_type_d1[1] <= #`TCQ err_type_both[1];\n end\n end\n end\n end //if \n endgenerate \n \n \n //Overflow may be active-low\n generate if (C_HAS_OVERFLOW==1) begin : gof\n assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;\n end else begin : gnof\n assign OVERFLOW = 0;\n end endgenerate // gof\n\n assign PROG_EMPTY = prog_empty_i;\n assign PROG_FULL = prog_full_i;\n\n //Valid may change behavior based on latency or active-low\n generate if (C_HAS_VALID==1) begin : gvalid\n assign valid_i = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid;\n assign valid_out = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ?\n valid_d1 : valid_i; \n assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;\n end else begin : gnvalid\n assign VALID = 0;\n end endgenerate // gvalid\n\n //Trim data count differently depending on set widths\n generate if (C_HAS_DATA_COUNT == 1) begin : gdc\n always @* begin\n diff_count <= wr_pntr - rd_pntr;\n if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin\n DATA_COUNT[C_RD_PNTR_WIDTH-1:0] <= diff_count;\n DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ; \n end else begin\n DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];\n end\n end\n// end else begin : gndc\n// always @* DATA_COUNT <= 0;\n end endgenerate // gdc\n\n //Underflow may change behavior based on latency or active-low\n generate if (C_HAS_UNDERFLOW==1) begin : guf\n assign underflow_i = ideal_underflow;\n assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;\n end else begin : gnuf\n assign UNDERFLOW = 0;\n end endgenerate // guf\n \n\n //Write acknowledge may be active low \n generate if (C_HAS_WR_ACK==1) begin : gwr_ack\n assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;\n end else begin : gnwr_ack\n assign WR_ACK = 0;\n end endgenerate // gwr_ack\n\n\n /*****************************************************************************\n * Internal reset logic \n ****************************************************************************/\n assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0;\n assign rst_i = C_HAS_RST ? RST : 0;\n assign srst_wrst_busy = srst_i;\n assign srst_rrst_busy = srst_i;\n\n /**************************************************************************\n * Assorted registers for delayed versions of signals\n **************************************************************************/\n //Capture delayed version of valid\n generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20\n always @(posedge CLK or posedge rst_i) begin\n if (rst_i == 1'b1) begin\n valid_d1 <= 1'b0;\n end else begin\n if (srst_rrst_busy) begin\n valid_d1 <= #`TCQ 1'b0;\n end else begin\n valid_d1 <= #`TCQ valid_i;\n end\n end \n end // always @ (posedge CLK or posedge rst_i)\n end \n endgenerate // blockVL20\n\n generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin \n always @(posedge CLK or posedge rst_i) begin\n if (rst_i == 1'b1) begin\n valid_d1 <= 1'b0;\n valid_both <= 1'b0;\n end else begin\n if (srst_rrst_busy) begin\n valid_d1 <= #`TCQ 1'b0;\n valid_both <= #`TCQ 1'b0;\n \n end else begin\n valid_both <= #`TCQ valid_i;\n valid_d1 <= #`TCQ valid_both;\n end\n end \n end // always @ (posedge CLK or posedge rst_i)\n end\n endgenerate // blockVL20\n\n\n // Determine which stage in FWFT registers are valid\n reg stage1_valid = 0;\n reg stage2_valid = 0;\n generate\n if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc\n always @ (posedge CLK or posedge rst_i) begin\n if (rst_i) begin\n stage1_valid <= #`TCQ 0;\n stage2_valid <= #`TCQ 0;\n end else begin\n\n if (!stage1_valid && !stage2_valid) begin\n if (!EMPTY)\n stage1_valid <= #`TCQ 1'b1;\n else\n stage1_valid <= #`TCQ 1'b0;\n end else if (stage1_valid && !stage2_valid) begin\n if (EMPTY) begin\n stage1_valid <= #`TCQ 1'b0;\n stage2_valid <= #`TCQ 1'b1;\n end else begin\n stage1_valid <= #`TCQ 1'b1;\n stage2_valid <= #`TCQ 1'b1;\n end\n end else if (!stage1_valid && stage2_valid) begin\n if (EMPTY && RD_EN) begin\n stage1_valid <= #`TCQ 1'b0;\n stage2_valid <= #`TCQ 1'b0;\n end else if (!EMPTY && RD_EN) begin\n stage1_valid <= #`TCQ 1'b1;\n stage2_valid <= #`TCQ 1'b0;\n end else if (!EMPTY && !RD_EN) begin\n stage1_valid <= #`TCQ 1'b1;\n stage2_valid <= #`TCQ 1'b1;\n end else begin\n stage1_valid <= #`TCQ 1'b0;\n stage2_valid <= #`TCQ 1'b1;\n end\n end else if (stage1_valid && stage2_valid) begin\n if (EMPTY && RD_EN) begin\n stage1_valid <= #`TCQ 1'b0;\n stage2_valid <= #`TCQ 1'b1;\n end else begin\n stage1_valid <= #`TCQ 1'b1;\n stage2_valid <= #`TCQ 1'b1;\n end\n end else begin\n stage1_valid <= #`TCQ 1'b0;\n stage2_valid <= #`TCQ 1'b0;\n end\n end // rd_rst_i\n end // always\n end\n endgenerate\n\n\n\n //***************************************************************************\n // Assign the read data count value only if it is selected, \n // otherwise output zeros.\n //***************************************************************************\n generate\n if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc\n assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];\n end\n endgenerate\n\n generate\n if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc\n assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};\n end\n endgenerate\n\n //***************************************************************************\n // Assign the write data count value only if it is selected, \n // otherwise output zeros\n //***************************************************************************\n generate\n if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc\n assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ;\n end\n endgenerate\n \n generate\n if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc\n assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};\n end\n endgenerate\n \n //reg ram_rd_en_d1 = 1'b0;\n //Capture delayed version of dout\n generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin\n always @(posedge CLK or posedge rst_i) begin\n if (rst_i == 1'b1) begin\n // Reset err_type only if ECC is not selected\n if (C_USE_ECC == 0) begin\n err_type_d1 <= #`TCQ 0;\n err_type_both <= #`TCQ 0;\n end\n // DRAM and SRAM reset asynchronously\n if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n ideal_dout_d1 <= #`TCQ dout_reset_val;\n end\n ram_rd_en_d1 <= #`TCQ 1'b0;\n if (C_USE_DOUT_RST == 1) begin\n @(posedge CLK)\n ideal_dout_d1 <= #`TCQ dout_reset_val;\n end\n end else begin\n ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;\n if (srst_rrst_busy) begin\n ram_rd_en_d1 <= #`TCQ 1'b0;\n // Reset err_type only if ECC is not selected\n if (C_USE_ECC == 0) begin\n err_type_d1 <= #`TCQ 0;\n err_type_both <= #`TCQ 0;\n end\n // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above\n if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n ideal_dout_d1 <= #`TCQ dout_reset_val;\n end \n if (C_USE_DOUT_RST == 1) begin\n // @(posedge CLK)\n ideal_dout_d1 <= #`TCQ dout_reset_val;\n end\n end else begin\n if (ram_rd_en_d1 ) begin\n ideal_dout_d1 <= #`TCQ ideal_dout;\n err_type_d1 <= #`TCQ err_type;\n end\n end\n end \n end // always\nend\nendgenerate \n\n//no safety ckt with both registers\n generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin\n always @(posedge CLK or posedge rst_i) begin\n if (rst_i == 1'b1) begin\n ram_rd_en_d1 <= #`TCQ 1'b0;\n fab_rd_en_d1 <= #`TCQ 1'b0;\n // Reset err_type only if ECC is not selected\n if (C_USE_ECC == 0) begin\n err_type_d1 <= #`TCQ 0;\n err_type_both <= #`TCQ 0;\n end\n // DRAM and SRAM reset asynchronously\n if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n ideal_dout_d1 <= #`TCQ dout_reset_val;\n ideal_dout_both <= #`TCQ dout_reset_val; \n \n end\n if (C_USE_DOUT_RST == 1) begin\n @(posedge CLK)\n ideal_dout_d1 <= #`TCQ dout_reset_val;\n ideal_dout_both <= #`TCQ dout_reset_val;\n end\n end else begin\n if (srst_rrst_busy) begin \n ram_rd_en_d1 <= #`TCQ 1'b0;\n fab_rd_en_d1 <= #`TCQ 1'b0;\n // Reset err_type only if ECC is not selected\n if (C_USE_ECC == 0) begin\n err_type_d1 <= #`TCQ 0;\n err_type_both <= #`TCQ 0;\n end\n // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above\n if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin\n ideal_dout_d1 <= #`TCQ dout_reset_val;\n end \n if (C_USE_DOUT_RST == 1) begin\n ideal_dout_d1 <= #`TCQ dout_reset_val;\n end\n end else begin\n ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;\n fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1);\n if (ram_rd_en_d1 ) begin\n ideal_dout_both <= #`TCQ ideal_dout;\n err_type_both <= #`TCQ err_type;\n end\n if (fab_rd_en_d1 ) begin\n ideal_dout_d1 <= #`TCQ ideal_dout_both;\n err_type_d1 <= #`TCQ err_type_both;\n end\n end\n end \n end // always\nend\nendgenerate \n /**************************************************************************\n * Overflow and Underflow Flag calculation\n * (handled separately because they don't support rst)\n **************************************************************************/\n generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw\n always @(posedge CLK) begin\n ideal_overflow <= #`TCQ WR_EN & full_i;\n end\n end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw\n always @(posedge CLK) begin\n //ideal_overflow <= #`TCQ WR_EN & (rst_i | full_i);\n ideal_overflow <= #`TCQ WR_EN & (WR_RST_BUSY | full_i);\n end\n end endgenerate // blockOF20\n \n generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw\n always @(posedge CLK) begin\n ideal_underflow <= #`TCQ empty_i & RD_EN;\n end\n end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw\n always @(posedge CLK) begin\n //ideal_underflow <= #`TCQ (rst_i | empty_i) & RD_EN;\n ideal_underflow <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN;\n end\n end endgenerate // blockUF20\n\n\n /**************************\n * Read Data Count\n *************************/\n\n reg [31:0] num_read_words_dc;\n reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;\n \n always @(num_rd_bits) begin\n if (C_USE_FWFT_DATA_COUNT) begin\n \n //If using extra logic for FWFT Data Counts, \n // then scale FIFO contents to read domain, \n // and add two read words for FWFT stages\n //This value is only a temporary value and not used in the code.\n num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);\n \n //Trim the read words for use with RD_DATA_COUNT\n num_read_words_sized_i = \n num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];\n \n end else begin\n \n //If not using extra logic for FWFT Data Counts, \n // then scale FIFO contents to read domain.\n //This value is only a temporary value and not used in the code.\n num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;\n \n //Trim the read words for use with RD_DATA_COUNT\n num_read_words_sized_i = \n num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];\n \n end //if (C_USE_FWFT_DATA_COUNT)\n end //always\n\n \n /**************************\n * Write Data Count\n *************************/\n\n reg [31:0] num_write_words_dc;\n reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;\n \n always @(num_wr_bits) begin\n if (C_USE_FWFT_DATA_COUNT) begin\n \n //Calculate the Data Count value for the number of write words, \n // when using First-Word Fall-Through with extra logic for Data \n // Counts. This takes into consideration the number of words that \n // are expected to be stored in the FWFT register stages (it always \n // assumes they are filled).\n //This value is scaled to the Write Domain.\n //The expression (((A-1)/B))+1 divides A/B, but takes the \n // ceiling of the result.\n //When num_wr_bits==0, set the result manually to prevent \n // division errors.\n //EXTRA_WORDS_DC is the number of words added to write_words \n // due to FWFT.\n //This value is only a temporary value and not used in the code.\n num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;\n \n //Trim the write words for use with WR_DATA_COUNT\n num_write_words_sized_i = \n num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];\n \n end else begin\n \n //Calculate the Data Count value for the number of write words, when NOT\n // using First-Word Fall-Through with extra logic for Data Counts. This \n // calculates only the number of words in the internal FIFO.\n //The expression (((A-1)/B))+1 divides A/B, but takes the \n // ceiling of the result.\n //This value is scaled to the Write Domain.\n //When num_wr_bits==0, set the result manually to prevent \n // division errors.\n //This value is only a temporary value and not used in the code.\n num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;\n \n //Trim the read words for use with RD_DATA_COUNT\n num_write_words_sized_i = \n num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];\n \n end //if (C_USE_FWFT_DATA_COUNT)\n end //always\n\n\n /*************************************************************************\n * Write and Read Logic \n ************************************************************************/\n wire write_allow;\n wire read_allow;\n wire read_allow_dc;\n wire write_only;\n wire read_only;\n //wire write_only_q;\n reg write_only_q;\n //wire read_only_q;\n reg read_only_q;\n reg full_reg;\n reg rst_full_ff_reg1;\n reg rst_full_ff_reg2;\n wire ram_full_comb;\n wire carry;\n \n assign write_allow = WR_EN & ~full_i;\n assign read_allow = RD_EN & ~empty_i;\n assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB;\n //assign write_only = write_allow & ~read_allow;\n //assign write_only_q = write_allow_q;\n //assign read_only = read_allow & ~write_allow;\n //assign read_only_q = read_allow_q ;\n wire [C_WR_PNTR_WIDTH-1:0] diff_pntr;\n wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe;\n reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0;\n reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0;\n reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0;\n wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ;\n wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym;\n reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0;\n reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0;\n wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max;\n wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max;\n\n assign diff_pntr_pe_max = DIFF_MAX_RD;\n assign diff_pntr_max = DIFF_MAX_WR;\n\n\n\n generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym\n assign write_only = write_allow & ~read_allow;\n assign read_only = read_allow & ~write_allow;\n end endgenerate\n generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd\n assign read_only = read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow;\n assign write_only = write_allow & ~(read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]));\n end endgenerate\n generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr\n assign read_only = read_allow & ~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n assign write_only = write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow;\n end endgenerate\n\n\n //-----------------------------------------------------------------------------\n // Write and Read pointer generation\n //-----------------------------------------------------------------------------\n always @(posedge CLK or posedge rst_i) begin\n if (rst_i && C_EN_SAFETY_CKT == 0) begin\n wr_pntr <= 0;\n rd_pntr <= 0;\n end else begin\n if (srst_i) begin\n wr_pntr <= #`TCQ 0;\n rd_pntr <= #`TCQ 0;\n end else begin\n if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1;\n if (read_allow) rd_pntr <= #`TCQ rd_pntr + 1;\n end\n end\n end\n\n generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout\n always @(posedge CLK) begin\n if (write_allow) begin\n if (ENABLE_ERR_INJECTION == 1)\n memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN};\n else\n memory[wr_pntr] <= #`TCQ DIN;\n end\n end\n\n reg [C_DATA_WIDTH-1:0] dout_tmp_q;\n reg [C_DATA_WIDTH-1:0] dout_tmp = 0;\n reg [C_DATA_WIDTH-1:0] dout_tmp1 = 0;\n always @(posedge CLK) begin\n dout_tmp_q <= #`TCQ ideal_dout;\n end\n\n\n\n always @* begin\n if (read_allow)\n ideal_dout <= memory[rd_pntr];\n else\n ideal_dout <= dout_tmp_q;\n end\n end endgenerate // gll_dm_dout\n\n\n /**************************************************************************\n * Write Domain Logic\n **************************************************************************/\n assign ram_rd_en = RD_EN & !EMPTY;\n\n //reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;\n generate if (C_FIFO_TYPE != 2) begin : gnll_din\n always @(posedge CLK or posedge rst_i) begin : gen_fifo_w\n\n /****** Reset fifo (case 1)***************************************/\n if (rst_i == 1'b1) begin\n num_wr_bits <= #`TCQ 0;\n next_num_wr_bits = #`TCQ 0;\n wr_ptr <= #`TCQ C_WR_DEPTH - 1;\n rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;\n ideal_wr_ack <= #`TCQ 0;\n ideal_wr_count <= #`TCQ 0;\n tmp_wr_listsize = #`TCQ 0;\n rd_ptr_wrclk_next <= #`TCQ 0;\n wr_pntr <= #`TCQ 0;\n wr_pntr_rd1 <= #`TCQ 0;\n\n end else begin //rst_i==0\n if (srst_wrst_busy) begin\n num_wr_bits <= #`TCQ 0;\n next_num_wr_bits = #`TCQ 0;\n wr_ptr <= #`TCQ C_WR_DEPTH - 1;\n rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;\n ideal_wr_ack <= #`TCQ 0;\n ideal_wr_count <= #`TCQ 0;\n tmp_wr_listsize = #`TCQ 0;\n rd_ptr_wrclk_next <= #`TCQ 0;\n wr_pntr <= #`TCQ 0;\n wr_pntr_rd1 <= #`TCQ 0;\n end else begin//srst_i=0\n\n wr_pntr_rd1 <= #`TCQ wr_pntr;\n\n //Determine the current number of words in the FIFO\n tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :\n num_wr_bits/C_DIN_WIDTH;\n rd_ptr_wrclk_next = rd_ptr;\n if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin\n next_num_wr_bits = num_wr_bits -\n C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH\n - rd_ptr_wrclk_next);\n end else begin\n next_num_wr_bits = num_wr_bits -\n C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);\n end\n\n if (WR_EN == 1'b1) begin\n if (FULL == 1'b1) begin\n\n ideal_wr_ack <= #`TCQ 0;\n //Reminder that FIFO is still full\n ideal_wr_count <= #`TCQ num_write_words_sized_i;\n\n end else begin\n write_fifo;\n next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;\n //Write successful, so issue acknowledge\n // and no error \n ideal_wr_ack <= #`TCQ 1;\n //Not even close to full.\n ideal_wr_count <= num_write_words_sized_i;\n\n //end\n\n end\n\n end else begin //(WR_EN == 1'b1)\n\n //If user did not attempt a write, then do not\n // give ack or err\n ideal_wr_ack <= #`TCQ 0;\n ideal_wr_count <= #`TCQ num_write_words_sized_i;\n end\n num_wr_bits <= #`TCQ next_num_wr_bits;\n rd_ptr_wrclk <= #`TCQ rd_ptr;\n\n end //srst_i==0\n end //wr_rst_i==0\n end // gen_fifo_w\n end endgenerate\n\n generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout\n always @(posedge CLK) begin\n if (rst_i || srst_rrst_busy) begin\n if (C_USE_DOUT_RST == 1) begin\n ideal_dout <= #`TCQ dout_reset_val;\n ideal_dout_both <= #`TCQ dout_reset_val;\n end\n end\n end\n end endgenerate\n\n\n\n\n generate if (C_FIFO_TYPE != 2) begin : gnll_dout\n always @(posedge CLK or posedge rst_i) begin : gen_fifo_r\n\n /****** Reset fifo (case 1)***************************************/\n if (rst_i) begin\n num_rd_bits <= #`TCQ 0;\n next_num_rd_bits = #`TCQ 0;\n rd_ptr <= #`TCQ C_RD_DEPTH -1;\n rd_pntr <= #`TCQ 0;\n //rd_pntr_wr1 <= #`TCQ 0;\n wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;\n \n // DRAM resets asynchronously\n if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)\n ideal_dout <= #`TCQ dout_reset_val;\n \n // Reset err_type only if ECC is not selected\n if (C_USE_ECC == 0) begin\n err_type <= #`TCQ 0;\n err_type_d1 <= 0;\n err_type_both <= 0;\n end\n ideal_valid <= #`TCQ 1'b0;\n ideal_rd_count <= #`TCQ 0;\n\n end else begin //rd_rst_i==0\n if (srst_rrst_busy) begin\n num_rd_bits <= #`TCQ 0;\n next_num_rd_bits = #`TCQ 0;\n rd_ptr <= #`TCQ C_RD_DEPTH -1;\n rd_pntr <= #`TCQ 0;\n //rd_pntr_wr1 <= #`TCQ 0;\n wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;\n \n // DRAM resets synchronously\n if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)\n ideal_dout <= #`TCQ dout_reset_val;\n \n // Reset err_type only if ECC is not selected\n if (C_USE_ECC == 0) begin\n err_type <= #`TCQ 0;\n err_type_d1 <= #`TCQ 0;\n err_type_both <= #`TCQ 0;\n end\n ideal_valid <= #`TCQ 1'b0;\n ideal_rd_count <= #`TCQ 0;\n end //srst_i\n else begin\n\n //rd_pntr_wr1 <= #`TCQ rd_pntr;\n\n //Determine the current number of words in the FIFO\n tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :\n num_rd_bits/C_DOUT_WIDTH;\n wr_ptr_rdclk_next = wr_ptr;\n\n if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin\n next_num_rd_bits = num_rd_bits +\n C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH\n - wr_ptr_rdclk_next);\n end else begin\n next_num_rd_bits = num_rd_bits +\n C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);\n end\n\n if (RD_EN == 1'b1) begin\n\n if (EMPTY == 1'b1) begin\n ideal_valid <= #`TCQ 1'b0;\n ideal_rd_count <= #`TCQ num_read_words_sized_i;\n end \n else \n begin\n read_fifo;\n next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;\n\n //Acknowledge the read from the FIFO, no error\n ideal_valid <= #`TCQ 1'b1;\n ideal_rd_count <= #`TCQ num_read_words_sized_i;\n\n end // if (tmp_rd_listsize == 2)\n end\n\n num_rd_bits <= #`TCQ next_num_rd_bits;\n wr_ptr_rdclk <= #`TCQ wr_ptr;\n end //s_rst_i==0\n end //rd_rst_i==0\n end //always\n end endgenerate\n\n //-----------------------------------------------------------------------------\n // Generate diff_pntr for PROG_FULL generation\n // Generate diff_pntr_pe for PROG_EMPTY generation\n //-----------------------------------------------------------------------------\n generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow\n always @(posedge CLK ) begin\n if (rst_i) begin\n write_only_q <= 1'b0;\n read_only_q <= 1'b0;\n diff_pntr_reg1 <= 0;\n diff_pntr_pe_reg1 <= 0;\n diff_pntr_reg2 <= 0;\n diff_pntr_pe_reg2 <= 0;\n end else begin\n if (srst_i || srst_wrst_busy || srst_rrst_busy) begin\n if (srst_rrst_busy) begin\n read_only_q <= #`TCQ 1'b0;\n diff_pntr_pe_reg1 <= #`TCQ 0;\n diff_pntr_pe_reg2 <= #`TCQ 0;\n end\n if (srst_wrst_busy) begin\n write_only_q <= #`TCQ 1'b0;\n diff_pntr_reg1 <= #`TCQ 0;\n diff_pntr_reg2 <= #`TCQ 0;\n end\n end else begin\n write_only_q <= #`TCQ write_only;\n read_only_q <= #`TCQ read_only;\n diff_pntr_reg2 <= #`TCQ diff_pntr_reg1;\n diff_pntr_pe_reg2 <= #`TCQ diff_pntr_pe_reg1;\n\n // Add 1 to the difference pointer value when only write happens.\n if (write_only) \n diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1;\n else\n diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;\n\n // Add 1 to the difference pointer value when write or both write & read or no write & read happen.\n if (read_only) \n diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1;\n else\n diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr;\n end\n end\n end\n assign diff_pntr_pe = diff_pntr_pe_reg1;\n assign diff_pntr = diff_pntr_reg1;\n end endgenerate // reg_write_allow\n\n generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym\n assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1};\n assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1};\n always @(posedge CLK ) begin\n if (rst_i) begin\n diff_pntr_pe_asym <= 0;\n diff_pntr_reg1 <= 0;\n full_reg <= 0;\n rst_full_ff_reg1 <= 1;\n rst_full_ff_reg2 <= 1;\n diff_pntr_pe_reg1 <= 0;\n end else begin\n if (srst_i || srst_wrst_busy || srst_rrst_busy) begin\n if (srst_wrst_busy)\n diff_pntr_reg1 <= #`TCQ 0;\n if (srst_rrst_busy)\n full_reg <= #`TCQ 0;\n rst_full_ff_reg1 <= #`TCQ 1;\n rst_full_ff_reg2 <= #`TCQ 1;\n diff_pntr_pe_asym <= #`TCQ 0;\n diff_pntr_pe_reg1 <= #`TCQ 0;\n end else begin\n diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym;\n full_reg <= #`TCQ full_i;\n rst_full_ff_reg1 <= #`TCQ RST_FULL_FF;\n rst_full_ff_reg2 <= #`TCQ rst_full_ff_reg1;\n if (~full_i) begin \n diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;\n end\n end\n end\n end\n assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1])));\n assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1];\n assign diff_pntr = diff_pntr_reg1;\n end endgenerate // reg_write_allow_asym\n\n\n //-----------------------------------------------------------------------------\n // Generate FULL flag\n //-----------------------------------------------------------------------------\n wire comp0;\n wire comp1;\n wire going_full;\n wire leaving_full;\n \n generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gpad \t\n assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr;\n assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0;\n end endgenerate\n\n generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin : gtrim \n assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n end endgenerate\n\n assign comp1 = (adj_rd_pntr_wr == (wr_pntr + 1'b1));\n assign comp0 = (adj_rd_pntr_wr == wr_pntr);\n\n generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp\n assign going_full = (comp1 & write_allow & ~read_allow);\n assign leaving_full = (comp0 & read_allow) | RST_FULL_GEN;\n end endgenerate\n\n // Write data width is bigger than read data width\n // Write depth is smaller than read depth\n // One write could be equal to 2 or 4 or 8 reads\n generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym\n assign going_full = (comp1 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));\n assign leaving_full = (comp0 & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;\n end endgenerate\n\n generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp \n assign going_full = (comp1 & write_allow & ~read_allow);\n assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN;\n end endgenerate\n\n\n assign ram_full_comb = going_full | (~leaving_full & full_i);\n\n always @(posedge CLK or posedge RST_FULL_FF) begin\n if (RST_FULL_FF)\n full_i <= C_FULL_FLAGS_RST_VAL;\n else if (srst_wrst_busy)\n full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n else\n full_i <= #`TCQ ram_full_comb;\n end\n\n //-----------------------------------------------------------------------------\n // Generate EMPTY flag\n //-----------------------------------------------------------------------------\n wire ecomp0;\n wire ecomp1;\n wire going_empty;\n wire leaving_empty;\n wire ram_empty_comb;\n\n \n generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : pad \t\n assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;\n assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0;\n end endgenerate\n\n generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin : trim \n assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n end endgenerate\n\n assign ecomp1 = (adj_wr_pntr_rd == (rd_pntr + 1'b1));\n assign ecomp0 = (adj_wr_pntr_rd == rd_pntr);\n\n\n generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp\n assign going_empty = (ecomp1 & ~write_allow & read_allow);\n assign leaving_empty = (ecomp0 & write_allow);\n end endgenerate\n\n generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp\n assign going_empty = (ecomp1 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));\n assign leaving_empty = (ecomp0 & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n end endgenerate\n \n generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp \n assign going_empty = (ecomp1 & ~write_allow & read_allow);\n assign leaving_empty =(ecomp0 & write_allow);\n end endgenerate\n\n\n\n assign ram_empty_comb = going_empty | (~leaving_empty & empty_i);\n\n always @(posedge CLK or posedge rst_i) begin\n if (rst_i)\n empty_i <= 1'b1;\n else if (srst_rrst_busy)\n empty_i <= #`TCQ 1'b1;\n else\n empty_i <= #`TCQ ram_empty_comb;\n end\n always @(posedge CLK or posedge rst_i) begin\n if (rst_i && C_EN_SAFETY_CKT == 0) begin\n EMPTY_FB <= 1'b1;\n end else begin\n if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT))\n EMPTY_FB <= #`TCQ 1'b1;\n else\n EMPTY_FB <= #`TCQ ram_empty_comb;\n end\n end // always\n\n //-----------------------------------------------------------------------------\n // Generate Read and write data counts for asymmetic common clock\n //-----------------------------------------------------------------------------\n\n reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0; \n wire [C_GRTR_PNTR_WIDTH :0] ratio; \n wire decr_by_one;\n wire incr_by_ratio;\n wire incr_by_one;\n wire decr_by_ratio;\n\n localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;\n\n generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr \n assign ratio = C_DEPTH_RATIO_RD;\n assign decr_by_one = (IS_FWFT == 1)? read_allow_dc : read_allow;\n assign incr_by_ratio = write_allow;\n\n always @(posedge CLK or posedge rst_i) begin\n if (rst_i)\n count_dc <= #`TCQ 0;\n else if (srst_wrst_busy)\n count_dc <= #`TCQ 0;\n else begin\n\t if (decr_by_one) begin\n\t if (!incr_by_ratio) \n count_dc <= #`TCQ count_dc - 1;\n else\n\t count_dc <= #`TCQ count_dc - 1 + ratio ;\n\t end\n\t else begin\n\t if (!incr_by_ratio) \n count_dc <= #`TCQ count_dc ;\n else\n\t count_dc <= #`TCQ count_dc + ratio ;\n\tend\n end\n end\n\n assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc;\n assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];\n\n end endgenerate\n\n\n generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd \n assign ratio = C_DEPTH_RATIO_WR;\n assign incr_by_one = write_allow;\n assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow;\n\n always @(posedge CLK or posedge rst_i) begin\n if (rst_i)\n count_dc <= #`TCQ 0;\n else if (srst_wrst_busy)\n count_dc <= #`TCQ 0;\n else begin\n\t if (incr_by_one) begin\n\t if (!decr_by_ratio) \n count_dc <= #`TCQ count_dc + 1;\n else\n\t count_dc <= #`TCQ count_dc + 1 - ratio ;\n\t end\n\t else begin\n\t if (!decr_by_ratio) \n count_dc <= #`TCQ count_dc ;\n else\n\t count_dc <= #`TCQ count_dc - ratio ;\n\tend\n end\n end\n\n assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc;\n assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];\n\n end endgenerate\n\n\n\n\n\n\n //-----------------------------------------------------------------------------\n // Generate WR_ACK flag\n //-----------------------------------------------------------------------------\n always @(posedge CLK or posedge rst_i) begin\n if (rst_i)\n ideal_wr_ack <= 1'b0;\n else if (srst_wrst_busy)\n ideal_wr_ack <= #`TCQ 1'b0;\n else if (WR_EN & ~full_i)\n ideal_wr_ack <= #`TCQ 1'b1;\n else\n ideal_wr_ack <= #`TCQ 1'b0;\n end\n\n //-----------------------------------------------------------------------------\n // Generate VALID flag\n //-----------------------------------------------------------------------------\n always @(posedge CLK or posedge rst_i) begin\n if (rst_i)\n ideal_valid <= 1'b0;\n else if (srst_rrst_busy)\n ideal_valid <= #`TCQ 1'b0;\n else if (RD_EN & ~empty_i)\n ideal_valid <= #`TCQ 1'b1;\n else\n ideal_valid <= #`TCQ 1'b0;\n end\n\n\n //-----------------------------------------------------------------------------\n // Generate ALMOST_FULL flag\n //-----------------------------------------------------------------------------\n //generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss\n\n wire fcomp2;\n wire going_afull;\n wire leaving_afull;\n wire ram_afull_comb;\n\n\n assign fcomp2 = (adj_rd_pntr_wr == (wr_pntr + 2'h2));\n\n generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp\n assign going_afull = (fcomp2 & write_allow & ~read_allow);\n assign leaving_afull = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN;\n end endgenerate\n\n // Write data width is bigger than read data width\n // Write depth is smaller than read depth\n // One write could be equal to 2 or 4 or 8 reads\n generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym\n assign going_afull = (fcomp2 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));\n assign leaving_afull = (comp1 & (~write_allow) & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;\n end endgenerate\n\n generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp \n assign going_afull = (fcomp2 & write_allow & ~read_allow);\n assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN;\n end endgenerate\n\n assign ram_afull_comb = going_afull | (~leaving_afull & almost_full_i);\n\n\n always @(posedge CLK or posedge RST_FULL_FF) begin\n if (RST_FULL_FF)\n almost_full_i <= C_FULL_FLAGS_RST_VAL;\n else if (srst_wrst_busy)\n almost_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n else\n almost_full_i <= #`TCQ ram_afull_comb;\n end\n // end endgenerate // gaf_ss\n\n //-----------------------------------------------------------------------------\n // Generate ALMOST_EMPTY flag\n //-----------------------------------------------------------------------------\n //generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss\n\n wire ecomp2;\n wire going_aempty;\n wire leaving_aempty;\n wire ram_aempty_comb;\n \n assign ecomp2 = (adj_wr_pntr_rd == (rd_pntr + 2'h2));\n \n generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp\n assign going_aempty = (ecomp2 & ~write_allow & read_allow);\n assign leaving_aempty = (ecomp1 & write_allow & ~read_allow);\n end endgenerate\n\n generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp\n assign going_aempty = (ecomp2 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));\n assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));\n end endgenerate\n \n generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp \n assign going_aempty = (ecomp2 & ~write_allow & read_allow);\n assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow);\n end endgenerate\n\n\n assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i);\n\n always @(posedge CLK or posedge rst_i) begin\n if (rst_i)\n almost_empty_i <= 1'b1;\n else if (srst_rrst_busy)\n almost_empty_i <= #`TCQ 1'b1;\n else\n almost_empty_i <= #`TCQ ram_aempty_comb;\n end\n // end endgenerate // gae_ss\n\n //-----------------------------------------------------------------------------\n // Generate PROG_FULL\n //-----------------------------------------------------------------------------\n\n localparam C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ? \n C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT \n C_PROG_FULL_THRESH_ASSERT_VAL; // STD\n localparam C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ? \n C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT\n C_PROG_FULL_THRESH_NEGATE_VAL; // STD\n\n //-----------------------------------------------------------------------------\n // Generate PROG_FULL for single programmable threshold constant\n //-----------------------------------------------------------------------------\n wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL; \n generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const\n always @(posedge CLK or posedge RST_FULL_FF) begin\n if (RST_FULL_FF && C_HAS_RST)\n prog_full_i <= C_FULL_FLAGS_RST_VAL;\n else begin \n if (srst_wrst_busy)\n prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n else if (IS_ASYMMETRY == 0) begin \n if (RST_FULL_GEN)\n prog_full_i <= #`TCQ 1'b0;\n else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)\n prog_full_i <= #`TCQ 1'b1;\n else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q)\n prog_full_i <= #`TCQ 1'b0;\n else\n prog_full_i <= #`TCQ prog_full_i;\n end\n else begin\n if (RST_FULL_GEN)\n prog_full_i <= #`TCQ 1'b0;\n else if (~RST_FULL_GEN ) begin \n if (diff_pntr>= C_PF_ASSERT_VAL )\n prog_full_i <= #`TCQ 1'b1;\n else if ((diff_pntr) < C_PF_ASSERT_VAL )\n prog_full_i <= #`TCQ 1'b0;\n else\n prog_full_i <= #`TCQ 1'b0;\n end \n else\n prog_full_i <= #`TCQ prog_full_i;\n end\n end\n end\n end endgenerate // single_pf_const\n\n //-----------------------------------------------------------------------------\n // Generate PROG_FULL for multiple programmable threshold constants\n //-----------------------------------------------------------------------------\n generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const\n always @(posedge CLK or posedge RST_FULL_FF) begin\n //if (RST_FULL_FF)\n if (RST_FULL_FF && C_HAS_RST)\n prog_full_i <= C_FULL_FLAGS_RST_VAL;\n else begin\n if (srst_wrst_busy)\n prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n else if (IS_ASYMMETRY == 0) begin \n if (RST_FULL_GEN)\n prog_full_i <= #`TCQ 1'b0;\n else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)\n prog_full_i <= #`TCQ 1'b1;\n else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q)\n prog_full_i <= #`TCQ 1'b0;\n else\n prog_full_i <= #`TCQ prog_full_i;\n end\n else begin\n if (RST_FULL_GEN)\n prog_full_i <= #`TCQ 1'b0;\n else if (~RST_FULL_GEN ) begin \n if (diff_pntr >= C_PF_ASSERT_VAL )\n prog_full_i <= #`TCQ 1'b1;\n else if (diff_pntr < C_PF_NEGATE_VAL)\n prog_full_i <= #`TCQ 1'b0;\n else\n prog_full_i <= #`TCQ prog_full_i;\n end \n else\n prog_full_i <= #`TCQ prog_full_i;\n end\n end\n end\n end endgenerate //multiple_pf_const\n\n //-----------------------------------------------------------------------------\n // Generate PROG_FULL for single programmable threshold input port\n //-----------------------------------------------------------------------------\n wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ? \n PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT\n PROG_FULL_THRESH; // STD\n generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input\n\n always @(posedge CLK or posedge RST_FULL_FF) begin//0\n //if (RST_FULL_FF)\n if (RST_FULL_FF && C_HAS_RST)\n prog_full_i <= C_FULL_FLAGS_RST_VAL;\n else begin //1\n if (srst_wrst_busy)\n prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n else if (IS_ASYMMETRY == 0) begin//2 \n if (RST_FULL_GEN)\n prog_full_i <= #`TCQ 1'b0;\n else if (~almost_full_i) begin//3\n if (diff_pntr > pf3_assert_val)\n prog_full_i <= #`TCQ 1'b1;\n else if (diff_pntr == pf3_assert_val) begin//4\n if (read_only_q)\n prog_full_i <= #`TCQ 1'b0;\n else\n prog_full_i <= #`TCQ 1'b1;\n end else//4\n prog_full_i <= #`TCQ 1'b0;\n end else//3\n prog_full_i <= #`TCQ prog_full_i;\n end //2\n else begin//5\n if (RST_FULL_GEN)\n prog_full_i <= #`TCQ 1'b0;\n else if (~full_i ) begin//6 \n if (diff_pntr >= pf3_assert_val )\n prog_full_i <= #`TCQ 1'b1;\n else if (diff_pntr < pf3_assert_val) begin//7\n prog_full_i <= #`TCQ 1'b0;\n end//7\n end//6\n else\n prog_full_i <= #`TCQ prog_full_i;\n end//5\n end//1\n end//0\n end endgenerate //single_pf_input\n \n //-----------------------------------------------------------------------------\n // Generate PROG_FULL for multiple programmable threshold input ports\n //-----------------------------------------------------------------------------\n wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ? \n (PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT\n PROG_FULL_THRESH_ASSERT; // STD\n wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ? \n (PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT\n PROG_FULL_THRESH_NEGATE; // STD\n\n generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs\n always @(posedge CLK or posedge RST_FULL_FF) begin\n if (RST_FULL_FF && C_HAS_RST)\n prog_full_i <= C_FULL_FLAGS_RST_VAL;\n else begin\n if (srst_wrst_busy)\n prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;\n else if (IS_ASYMMETRY == 0) begin \n if (RST_FULL_GEN)\n prog_full_i <= #`TCQ 1'b0;\n else if (~almost_full_i) begin\n if (diff_pntr >= pf_assert_val)\n prog_full_i <= #`TCQ 1'b1;\n else if ((diff_pntr == pf_negate_val && read_only_q) ||\n diff_pntr < pf_negate_val)\n prog_full_i <= #`TCQ 1'b0;\n else\n prog_full_i <= #`TCQ prog_full_i;\n end else\n prog_full_i <= #`TCQ prog_full_i;\n end\n else begin\n if (RST_FULL_GEN)\n prog_full_i <= #`TCQ 1'b0;\n else if (~full_i ) begin \n if (diff_pntr >= pf_assert_val )\n prog_full_i <= #`TCQ 1'b1;\n else if (diff_pntr < pf_negate_val) \n prog_full_i <= #`TCQ 1'b0;\n else\n prog_full_i <= #`TCQ prog_full_i;\n end \n else\n prog_full_i <= #`TCQ prog_full_i;\n end\n\n end\n end\n end endgenerate //multiple_pf_inputs\n\n //-----------------------------------------------------------------------------\n // Generate PROG_EMPTY\n //-----------------------------------------------------------------------------\n localparam C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?\n C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT\n C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD\n localparam C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?\n C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT\n C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD\n\n //-----------------------------------------------------------------------------\n // Generate PROG_EMPTY for single programmable threshold constant\n //-----------------------------------------------------------------------------\n generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const\n always @(posedge CLK or posedge rst_i) begin\n //if (rst_i) \n if (rst_i && C_HAS_RST) \n prog_empty_i <= 1'b1;\n else begin\n if (srst_rrst_busy) \n prog_empty_i <= #`TCQ 1'b1;\n else if (IS_ASYMMETRY == 0) begin \n if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)\n prog_empty_i <= #`TCQ 1'b1;\n else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q)\n prog_empty_i <= #`TCQ 1'b0;\n else\n prog_empty_i <= #`TCQ prog_empty_i;\n end\n else begin\n if (~rst_i ) begin \n if (diff_pntr_pe <= C_PE_ASSERT_VAL)\n prog_empty_i <= #`TCQ 1'b1;\n else if (diff_pntr_pe > C_PE_ASSERT_VAL)\n prog_empty_i <= #`TCQ 1'b0;\n end \n else\n prog_empty_i <= #`TCQ prog_empty_i;\n end\n end\n end\n end endgenerate // single_pe_const\n\n //-----------------------------------------------------------------------------\n // Generate PROG_EMPTY for multiple programmable threshold constants\n //-----------------------------------------------------------------------------\n generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const\n always @(posedge CLK or posedge rst_i) begin\n //if (rst_i)\n if (rst_i && C_HAS_RST) \n prog_empty_i <= 1'b1;\n else begin\n if (srst_rrst_busy)\n prog_empty_i <= #`TCQ 1'b1;\n else if (IS_ASYMMETRY == 0) begin \n if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)\n prog_empty_i <= #`TCQ 1'b1;\n else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q)\n prog_empty_i <= #`TCQ 1'b0;\n else\n prog_empty_i <= #`TCQ prog_empty_i;\n end\n else begin\n if (~rst_i ) begin \n if (diff_pntr_pe <= C_PE_ASSERT_VAL )\n prog_empty_i <= #`TCQ 1'b1;\n else if (diff_pntr_pe > C_PE_NEGATE_VAL) \n prog_empty_i <= #`TCQ 1'b0;\n else\n prog_empty_i <= #`TCQ prog_empty_i;\n end \n else\n prog_empty_i <= #`TCQ prog_empty_i;\n end\n\n end\n\n end\n end endgenerate //multiple_pe_const\n\n //-----------------------------------------------------------------------------\n // Generate PROG_EMPTY for single programmable threshold input port\n //-----------------------------------------------------------------------------\n wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ?\n (PROG_EMPTY_THRESH -2) : // FWFT\n PROG_EMPTY_THRESH; // STD\n generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input\n always @(posedge CLK or posedge rst_i) begin\n //if (rst_i)\n if (rst_i && C_HAS_RST) \n prog_empty_i <= 1'b1;\n else begin\n if (srst_rrst_busy)\n prog_empty_i <= #`TCQ 1'b1;\n else if (IS_ASYMMETRY == 0) begin \n if (~almost_full_i) begin\n if (diff_pntr_pe < pe3_assert_val)\n prog_empty_i <= #`TCQ 1'b1;\n else if (diff_pntr_pe == pe3_assert_val) begin\n if (write_only_q)\n prog_empty_i <= #`TCQ 1'b0;\n else\n prog_empty_i <= #`TCQ 1'b1;\n end else\n prog_empty_i <= #`TCQ 1'b0;\n end else\n prog_empty_i <= #`TCQ prog_empty_i;\n end\n else begin\n if (diff_pntr_pe <= pe3_assert_val )\n prog_empty_i <= #`TCQ 1'b1;\n else if (diff_pntr_pe > pe3_assert_val)\n prog_empty_i <= #`TCQ 1'b0;\n else\n prog_empty_i <= #`TCQ prog_empty_i;\n end \n end\n\n end\n end endgenerate // single_pe_input\n\n //-----------------------------------------------------------------------------\n // Generate PROG_EMPTY for multiple programmable threshold input ports\n //-----------------------------------------------------------------------------\n wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ?\n (PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT\n PROG_EMPTY_THRESH_ASSERT; // STD\n wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ?\n (PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT\n PROG_EMPTY_THRESH_NEGATE; // STD\n generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs\n always @(posedge CLK or posedge rst_i) begin\n //if (rst_i)\n if (rst_i && C_HAS_RST) \n prog_empty_i <= 1'b1;\n else begin\n if (srst_rrst_busy)\n prog_empty_i <= #`TCQ 1'b1;\n else if (IS_ASYMMETRY == 0) begin \n if (~almost_full_i) begin\n if (diff_pntr_pe <= pe4_assert_val)\n prog_empty_i <= #`TCQ 1'b1;\n else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) || \n (diff_pntr_pe > pe4_negate_val)) begin\n prog_empty_i <= #`TCQ 1'b0;\n end else\n prog_empty_i <= #`TCQ prog_empty_i;\n end else\n prog_empty_i <= #`TCQ prog_empty_i;\n end\n else begin\n if (diff_pntr_pe <= pe4_assert_val )\n prog_empty_i <= #`TCQ 1'b1;\n else if (diff_pntr_pe > pe4_negate_val) \n prog_empty_i <= #`TCQ 1'b0;\n else\n prog_empty_i <= #`TCQ prog_empty_i;\n end \n end\n end\n end endgenerate // multiple_pe_inputs\n\nendmodule // fifo_generator_v13_1_2_bhv_ver_ss\n\n\n\n/**************************************************************************\n * First-Word Fall-Through module (preload 0)\n **************************************************************************/\nmodule fifo_generator_v13_1_2_bhv_ver_preload0\n #(\n parameter C_DOUT_RST_VAL = \"\",\n parameter C_DOUT_WIDTH = 8,\n parameter C_HAS_RST = 0,\n parameter C_ENABLE_RST_SYNC = 0,\n parameter C_HAS_SRST = 0,\n parameter C_USE_EMBEDDED_REG = 0,\n parameter C_EN_SAFETY_CKT = 0, \n parameter C_USE_DOUT_RST = 0,\n parameter C_USE_ECC = 0,\n parameter C_USERVALID_LOW = 0,\n parameter C_USERUNDERFLOW_LOW = 0,\n parameter C_MEMORY_TYPE = 0,\n parameter C_FIFO_TYPE = 0\n )\n (\n //Inputs\n input SAFETY_CKT_RD_RST,\n input RD_CLK,\n input RD_RST,\n input SRST,\n input WR_RST_BUSY,\n input RD_RST_BUSY,\n input RD_EN,\n input FIFOEMPTY,\n input [C_DOUT_WIDTH-1:0] FIFODATA,\n input FIFOSBITERR,\n input FIFODBITERR,\n \n //Outputs\n output reg [C_DOUT_WIDTH-1:0] USERDATA,\n output USERVALID,\n output USERUNDERFLOW,\n output USEREMPTY,\n output USERALMOSTEMPTY,\n output RAMVALID,\n output FIFORDEN,\n output reg USERSBITERR,\n output reg USERDBITERR,\n output reg STAGE2_REG_EN,\n output fab_read_data_valid_i_o,\n output read_data_valid_i_o,\n output ram_valid_i_o,\n output [1:0] VALID_STAGES \n );\n //Internal signals\n wire preloadstage1;\n wire preloadstage2;\n reg ram_valid_i;\n reg fab_valid;\n reg read_data_valid_i;\n reg fab_read_data_valid_i;\n reg fab_read_data_valid_i_1;\n reg ram_valid_i_d;\n reg read_data_valid_i_d;\n reg fab_read_data_valid_i_d;\n wire ram_regout_en;\n reg ram_regout_en_d1;\n reg ram_regout_en_d2;\n wire fab_regout_en;\n wire ram_rd_en;\n reg empty_i = 1'b1;\n reg empty_sckt = 1'b1;\n reg sckt_rrst_q = 1'b0;\n reg sckt_rrst_done = 1'b0;\n reg empty_q = 1'b1;\n reg rd_en_q = 1'b0;\n reg almost_empty_i = 1'b1;\n reg almost_empty_q = 1'b1;\n wire rd_rst_i;\n wire srst_i;\n reg [C_DOUT_WIDTH-1:0] userdata_both;\n wire uservalid_both;\n wire uservalid_one;\n reg user_sbiterr_both = 1'b0;\n reg user_dbiterr_both = 1'b0;\n \nassign ram_valid_i_o = ram_valid_i;\nassign read_data_valid_i_o = read_data_valid_i;\nassign fab_read_data_valid_i_o = fab_read_data_valid_i; \n\n\n\n/*************************************************************************\n* FUNCTIONS\n*************************************************************************/\n\n /*************************************************************************\n * hexstr_conv\n * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)\n ***********************************************************************/\n function [C_DOUT_WIDTH-1:0] hexstr_conv;\n input [(C_DOUT_WIDTH*8)-1:0] def_data;\n\n integer index,i,j;\n reg [3:0] bin;\n\n begin\n index = 0;\n hexstr_conv = 'b0;\n for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )\n begin\n case (def_data[7:0])\n 8'b00000000 :\n begin\n bin = 4'b0000;\n i = -1;\n end\n 8'b00110000 : bin = 4'b0000;\n 8'b00110001 : bin = 4'b0001;\n 8'b00110010 : bin = 4'b0010;\n 8'b00110011 : bin = 4'b0011;\n 8'b00110100 : bin = 4'b0100;\n 8'b00110101 : bin = 4'b0101;\n 8'b00110110 : bin = 4'b0110;\n 8'b00110111 : bin = 4'b0111;\n 8'b00111000 : bin = 4'b1000;\n 8'b00111001 : bin = 4'b1001;\n 8'b01000001 : bin = 4'b1010;\n 8'b01000010 : bin = 4'b1011;\n 8'b01000011 : bin = 4'b1100;\n 8'b01000100 : bin = 4'b1101;\n 8'b01000101 : bin = 4'b1110;\n 8'b01000110 : bin = 4'b1111;\n 8'b01100001 : bin = 4'b1010;\n 8'b01100010 : bin = 4'b1011;\n 8'b01100011 : bin = 4'b1100;\n 8'b01100100 : bin = 4'b1101;\n 8'b01100101 : bin = 4'b1110;\n 8'b01100110 : bin = 4'b1111;\n default :\n begin\n bin = 4'bx;\n end\n endcase\n for( j=0; j<4; j=j+1)\n begin\n if ((index*4)+j < C_DOUT_WIDTH)\n begin\n hexstr_conv[(index*4)+j] = bin[j];\n end\n end\n index = index + 1;\n def_data = def_data >> 8;\n end\n end\n endfunction\n\n \n //*************************************************************************\n // Set power-on states for regs\n //*************************************************************************\n initial begin\n ram_valid_i = 1'b0;\n fab_valid = 1'b0;\n read_data_valid_i = 1'b0;\n fab_read_data_valid_i = 1'b0;\n fab_read_data_valid_i_1 = 1'b0;\n USERDATA = hexstr_conv(C_DOUT_RST_VAL);\n userdata_both = hexstr_conv(C_DOUT_RST_VAL);\n USERSBITERR = 1'b0;\n USERDBITERR = 1'b0;\n user_sbiterr_both = 1'b0;\n user_dbiterr_both = 1'b0;\n end //initial\n\n //***************************************************************************\n // connect up optional reset\n //***************************************************************************\n assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0;\n assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0;\n\n reg sckt_rd_rst_fwft = 1'b0;\n reg fwft_rst_done_i = 1'b0;\n wire fwft_rst_done;\n assign fwft_rst_done = C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1;\n always @ (posedge RD_CLK) begin\n sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST;\n end\n\n always @ (posedge rd_rst_i or posedge RD_CLK) begin\n if (rd_rst_i)\n fwft_rst_done_i <= 1'b0;\n else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST)\n fwft_rst_done_i <= #`TCQ 1'b1;\n end\n\n localparam INVALID = 0;\n localparam STAGE1_VALID = 2;\n localparam STAGE2_VALID = 1;\n localparam BOTH_STAGES_VALID = 3;\n\n reg [1:0] curr_fwft_state = INVALID;\n reg [1:0] next_fwft_state = INVALID;\n\n\ngenerate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin\n always @* begin\n case (curr_fwft_state)\n INVALID: begin\n if (~FIFOEMPTY)\n next_fwft_state <= STAGE1_VALID;\n else\n next_fwft_state <= INVALID;\n end\n STAGE1_VALID: begin\n if (FIFOEMPTY)\n next_fwft_state <= STAGE2_VALID;\n else\n next_fwft_state <= BOTH_STAGES_VALID;\n end\n STAGE2_VALID: begin\n if (FIFOEMPTY && RD_EN)\n next_fwft_state <= INVALID;\n else if (~FIFOEMPTY && RD_EN)\n next_fwft_state <= STAGE1_VALID;\n else if (~FIFOEMPTY && ~RD_EN)\n next_fwft_state <= BOTH_STAGES_VALID;\n else\n next_fwft_state <= STAGE2_VALID;\n end\n BOTH_STAGES_VALID: begin\n if (FIFOEMPTY && RD_EN)\n next_fwft_state <= STAGE2_VALID;\n else if (~FIFOEMPTY && RD_EN)\n next_fwft_state <= BOTH_STAGES_VALID;\n else\n next_fwft_state <= BOTH_STAGES_VALID;\n end\n default: next_fwft_state <= INVALID;\n endcase\n end\n\n always @ (posedge rd_rst_i or posedge RD_CLK) begin\n if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n curr_fwft_state <= INVALID;\n else if (srst_i)\n curr_fwft_state <= #`TCQ INVALID;\n else\n curr_fwft_state <= #`TCQ next_fwft_state;\n end\n\n always @* begin\n case (curr_fwft_state)\n INVALID: STAGE2_REG_EN <= 1'b0;\n STAGE1_VALID: STAGE2_REG_EN <= 1'b1;\n STAGE2_VALID: STAGE2_REG_EN <= 1'b0;\n BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;\n default: STAGE2_REG_EN <= 1'b0;\n endcase\n end\n\n \n assign VALID_STAGES = curr_fwft_state;\n\n //***************************************************************************\n // preloadstage2 indicates that stage2 needs to be updated. This is true\n // whenever read_data_valid is false, and RAM_valid is true.\n //***************************************************************************\n \n assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );\n \n\n //***************************************************************************\n // preloadstage1 indicates that stage1 needs to be updated. This is true\n // whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is\n // false (indicating that Stage1 needs updating), or preloadstage2 is active\n // (indicating that Stage2 is going to update, so Stage1, therefore, must\n // also be updated to keep it valid.\n //***************************************************************************\n assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);\n \n //***************************************************************************\n // Calculate RAM_REGOUT_EN\n // The output registers are controlled by the ram_regout_en signal.\n // These registers should be updated either when the output in Stage2 is\n // invalid (preloadstage2), OR when the user is reading, in which case the\n // Stage2 value will go invalid unless it is replenished.\n //***************************************************************************\n assign ram_regout_en = preloadstage2;\n\n //***************************************************************************\n // Calculate RAM_RD_EN\n // RAM_RD_EN will be asserted whenever the RAM needs to be read in order to\n // update the value in Stage1.\n // One case when this happens is when preloadstage1=true, which indicates\n // that the data in Stage1 or Stage2 is invalid, and needs to automatically\n // be updated.\n // The other case is when the user is reading from the FIFO, which \n // guarantees that Stage1 or Stage2 will be invalid on the next clock \n // cycle, unless it is replinished by data from the memory. So, as long \n // as the RAM has data in it, a read of the RAM should occur.\n //***************************************************************************\n assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;\n end\nendgenerate // gnll_fifo\n\n reg curr_state = 0;\n reg next_state = 0;\n reg leaving_empty_fwft = 0;\n reg going_empty_fwft = 0;\n reg empty_i_q = 0;\n reg ram_rd_en_fwft = 0;\n generate if (C_FIFO_TYPE == 2) begin : gll_fifo\n always @* begin // FSM fo FWFT\n case (curr_state)\n 1'b0: begin\n if (~FIFOEMPTY)\n next_state <= 1'b1;\n else\n next_state <= 1'b0;\n end\n 1'b1: begin\n if (FIFOEMPTY && RD_EN)\n next_state <= 1'b0;\n else\n next_state <= 1'b1;\n end\n default: next_state <= 1'b0;\n endcase\n end\n\n always @ (posedge RD_CLK or posedge rd_rst_i) begin\n if (rd_rst_i) begin\n empty_i <= 1'b1;\n empty_i_q <= 1'b1;\n ram_valid_i <= 1'b0;\n end else if (srst_i) begin\n empty_i <= #`TCQ 1'b1;\n empty_i_q <= #`TCQ 1'b1;\n ram_valid_i <= #`TCQ 1'b0;\n end else begin\n empty_i <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i);\n empty_i_q <= #`TCQ FIFOEMPTY;\n ram_valid_i <= #`TCQ next_state;\n end\n end //always\n\n always @ (posedge RD_CLK or posedge rd_rst_i) begin\n if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin\n curr_state <= 1'b0;\n end else if (srst_i) begin\n curr_state <= #`TCQ 1'b0;\n end else begin\n curr_state <= #`TCQ next_state;\n end\n end //always\n\n wire fe_of_empty; \n assign fe_of_empty = empty_i_q & ~FIFOEMPTY;\n\n always @* begin // Finding leaving empty\n case (curr_state)\n 1'b0: leaving_empty_fwft <= fe_of_empty;\n 1'b1: leaving_empty_fwft <= 1'b1;\n default: leaving_empty_fwft <= 1'b0;\n endcase\n end\n\n always @* begin // Finding going empty\n case (curr_state)\n 1'b1: going_empty_fwft <= FIFOEMPTY & RD_EN;\n default: going_empty_fwft <= 1'b0;\n endcase\n end\n\n always @* begin // Generating FWFT rd_en\n case (curr_state)\n 1'b0: ram_rd_en_fwft <= ~FIFOEMPTY;\n 1'b1: ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN;\n default: ram_rd_en_fwft <= 1'b0;\n endcase\n end\n\n assign ram_regout_en = ram_rd_en_fwft;\n //assign ram_regout_en_d1 = ram_rd_en_fwft;\n //assign ram_regout_en_d2 = ram_rd_en_fwft;\n assign ram_rd_en = ram_rd_en_fwft;\n end endgenerate // gll_fifo\n\n\n //***************************************************************************\n // Calculate RAMVALID_P0_OUT\n // RAMVALID_P0_OUT indicates that the data in Stage1 is valid.\n //\n // If the RAM is being read from on this clock cycle (ram_rd_en=1), then\n // RAMVALID_P0_OUT is certainly going to be true.\n // If the RAM is not being read from, but the output registers are being\n // updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,\n // therefore causing RAMVALID_P0_OUT to be false.\n // Otherwise, RAMVALID_P0_OUT will remain unchanged.\n //***************************************************************************\n // PROCESS regout_valid\n generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid\n always @ (posedge RD_CLK or posedge rd_rst_i) begin \n if (rd_rst_i) begin \n // asynchronous reset (active high)\n ram_valid_i <= #`TCQ 1'b0;\n end else begin\n if (srst_i) begin \n // synchronous reset (active high)\n ram_valid_i <= #`TCQ 1'b0;\n end else begin\n if (ram_rd_en == 1'b1) begin\n ram_valid_i <= #`TCQ 1'b1;\n end else begin\n if (ram_regout_en == 1'b1)\n ram_valid_i <= #`TCQ 1'b0;\n else\n ram_valid_i <= #`TCQ ram_valid_i;\n end\n end //srst_i\n end //rd_rst_i\n end //always\n end endgenerate // gnll_fifo_ram_valid\n \n //***************************************************************************\n // Calculate READ_DATA_VALID\n // READ_DATA_VALID indicates whether the value in Stage2 is valid or not.\n // Stage2 has valid data whenever Stage1 had valid data and \n // ram_regout_en_i=1, such that the data in Stage1 is propogated \n // into Stage2.\n //***************************************************************************\n \n generate if(C_USE_EMBEDDED_REG < 3) begin\n always @ (posedge RD_CLK or posedge rd_rst_i) begin\n if (rd_rst_i)\n read_data_valid_i <= #`TCQ 1'b0;\n else if (srst_i)\n read_data_valid_i <= #`TCQ 1'b0;\n else\n read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN);\n end //always\nend \nendgenerate\n\n \n \n //**************************************************************************\n // Calculate EMPTY\n // Defined as the inverse of READ_DATA_VALID\n //\n // Description:\n //\n // If read_data_valid_i indicates that the output is not valid,\n // and there is no valid data on the output of the ram to preload it\n // with, then we will report empty.\n //\n // If there is no valid data on the output of the ram and we are\n // reading, then the FIFO will go empty.\n //\n //**************************************************************************\n generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty\n always @ (posedge RD_CLK or posedge rd_rst_i) begin\n if (rd_rst_i) begin\n // asynchronous reset (active high)\n empty_i <= #`TCQ 1'b1;\n end else begin\n if (srst_i) begin\n // synchronous reset (active high)\n empty_i <= #`TCQ 1'b1;\n end else begin\n // rising clock edge\n empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);\n end\n end\n end //always\n end endgenerate // gnll_fifo_empty\n \n // Register RD_EN from user to calculate USERUNDERFLOW.\n // Register empty_i to calculate USERUNDERFLOW.\n always @ (posedge RD_CLK) begin\n rd_en_q <= #`TCQ RD_EN;\n empty_q <= #`TCQ empty_i;\n end //always\n \n \n //***************************************************************************\n // Calculate user_almost_empty\n // user_almost_empty is defined such that, unless more words are written\n // to the FIFO, the next read will cause the FIFO to go EMPTY.\n //\n // In most cases, whenever the output registers are updated (due to a user\n // read or a preload condition), then user_almost_empty will update to\n // whatever RAM_EMPTY is.\n //\n // The exception is when the output is valid, the user is not reading, and\n // Stage1 is not empty. In this condition, Stage1 will be preloaded from the\n // memory, so we need to make sure user_almost_empty deasserts properly under\n // this condition.\n //***************************************************************************\n generate if ( C_USE_EMBEDDED_REG < 3) begin\n always @ (posedge RD_CLK or posedge rd_rst_i)\n begin\n if (rd_rst_i) begin // asynchronous reset (active high)\n almost_empty_i <= #`TCQ 1'b1;\n almost_empty_q <= #`TCQ 1'b1;\n end else begin // rising clock edge\n if (srst_i) begin // synchronous reset (active high)\n almost_empty_i <= #`TCQ 1'b1;\n almost_empty_q <= #`TCQ 1'b1;\n end else begin\n if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin\n almost_empty_i <= #`TCQ FIFOEMPTY;\n end\n almost_empty_q <= #`TCQ empty_i;\n end\n end\n end //always\nend\nendgenerate\n \n \n \n // BRAM resets synchronously\n generate \n if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin\n always @ ( posedge rd_rst_i)\n begin\n if (rd_rst_i || srst_i) begin\n if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)\n @(posedge RD_CLK)\n USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n end\n end //always\n\n \n always @ (posedge RD_CLK or posedge rd_rst_i)\n begin\n if (rd_rst_i) begin //asynchronous reset (active high)\n if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n USERSBITERR <= #`TCQ 0;\n USERDBITERR <= #`TCQ 0;\n end\n // DRAM resets asynchronously\n if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)\n USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n end\n end else begin // rising clock edge\n if (srst_i) begin\n if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n USERSBITERR <= #`TCQ 0;\n USERDBITERR <= #`TCQ 0;\n end\n if (C_USE_DOUT_RST == 1) begin\n USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n end\n end else if (fwft_rst_done) begin\n if (ram_regout_en) begin\n USERDATA <= #`TCQ FIFODATA;\n USERSBITERR <= #`TCQ FIFOSBITERR;\n USERDBITERR <= #`TCQ FIFODBITERR;\n end\n end\n end\n end //always\n end //if\n endgenerate\n//safety ckt with one register\ngenerate\n if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin\n reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;\n reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;\n reg [1:0] rst_delayed_sft1 =1;\n reg [1:0] rst_delayed_sft2 =1;\n reg [1:0] rst_delayed_sft3 =1;\n reg [1:0] rst_delayed_sft4 =1;\n \n always@(posedge RD_CLK)\n begin\n rst_delayed_sft1 <= #`TCQ rd_rst_i;\n rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n end\n always @ (posedge RD_CLK)\n begin\n if (rd_rst_i || srst_i) begin\n if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin\n @(posedge RD_CLK)\n USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n end\n end\n end //always\n \n always @ (posedge RD_CLK or posedge rd_rst_i)\n begin\n if (rd_rst_i) begin //asynchronous reset (active high)\n if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n USERSBITERR <= #`TCQ 0;\n USERDBITERR <= #`TCQ 0;\n end\n // DRAM resets asynchronously\n if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)\n //@(posedge RD_CLK)\n USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n end \n end\n else begin // rising clock edge\n if (srst_i) begin\n if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n USERSBITERR <= #`TCQ 0;\n USERDBITERR <= #`TCQ 0;\n end\n if (C_USE_DOUT_RST == 1) begin\n // @(posedge RD_CLK)\n USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n end\n end else if (fwft_rst_done) begin\n if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n USERDATA <= #`TCQ FIFODATA;\n USERSBITERR <= #`TCQ FIFOSBITERR;\n USERDBITERR <= #`TCQ FIFODBITERR;\n end \n end\n end\n end //always\n end //if\nendgenerate\n\n\ngenerate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin\n \n\n always @* begin\n case (curr_fwft_state)\n INVALID: begin\n if (~FIFOEMPTY)\n next_fwft_state <= STAGE1_VALID;\n else\n next_fwft_state <= INVALID;\n end\n STAGE1_VALID: begin\n if (FIFOEMPTY)\n next_fwft_state <= STAGE2_VALID;\n else\n next_fwft_state <= BOTH_STAGES_VALID;\n end\n STAGE2_VALID: begin\n if (FIFOEMPTY && RD_EN)\n next_fwft_state <= INVALID;\n else if (~FIFOEMPTY && RD_EN)\n next_fwft_state <= STAGE1_VALID;\n else if (~FIFOEMPTY && ~RD_EN)\n next_fwft_state <= BOTH_STAGES_VALID;\n else\n next_fwft_state <= STAGE2_VALID;\n end\n BOTH_STAGES_VALID: begin\n if (FIFOEMPTY && RD_EN)\n next_fwft_state <= STAGE2_VALID;\n else if (~FIFOEMPTY && RD_EN)\n next_fwft_state <= BOTH_STAGES_VALID;\n else\n next_fwft_state <= BOTH_STAGES_VALID;\n end\n default: next_fwft_state <= INVALID;\n endcase\n end\n\n always @ (posedge rd_rst_i or posedge RD_CLK) begin\n if (rd_rst_i && C_EN_SAFETY_CKT == 0)\n curr_fwft_state <= INVALID;\n else if (srst_i)\n curr_fwft_state <= #`TCQ INVALID;\n else\n curr_fwft_state <= #`TCQ next_fwft_state;\n end\n\n always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay\n if (rd_rst_i == 1) begin\n ram_regout_en_d1 <= #`TCQ 1'b0;\n end\n else begin\n if (srst_i == 1'b1) \n ram_regout_en_d1 <= #`TCQ 1'b0;\n else\n ram_regout_en_d1 <= #`TCQ ram_regout_en;\n end\n end //always\n // assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i));\n assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0;\n\n always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1\n if (rd_rst_i == 1) begin\n ram_regout_en_d2 <= #`TCQ 1'b0;\n end\n else begin\n if (srst_i == 1'b1) \n ram_regout_en_d2 <= #`TCQ 1'b0;\n else\n ram_regout_en_d2 <= #`TCQ ram_regout_en_d1;\n end\n end //always\n\n \n\n always @* begin\n case (curr_fwft_state)\n INVALID: STAGE2_REG_EN <= 1'b0;\n STAGE1_VALID: STAGE2_REG_EN <= 1'b1;\n STAGE2_VALID: STAGE2_REG_EN <= 1'b0;\n BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;\n default: STAGE2_REG_EN <= 1'b0;\n endcase\n end\n\n always @ (posedge RD_CLK) begin\n ram_valid_i_d <= #`TCQ ram_valid_i;\n read_data_valid_i_d <= #`TCQ read_data_valid_i;\n fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i;\n\n end\n assign VALID_STAGES = curr_fwft_state;\n\n //***************************************************************************\n // preloadstage2 indicates that stage2 needs to be updated. This is true\n // whenever read_data_valid is false, and RAM_valid is true.\n //***************************************************************************\n \n assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );\n\n //***************************************************************************\n // preloadstage1 indicates that stage1 needs to be updated. This is true\n // whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is\n // false (indicating that Stage1 needs updating), or preloadstage2 is active\n // (indicating that Stage2 is going to update, so Stage1, therefore, must\n // also be updated to keep it valid.\n //***************************************************************************\n assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);\n \n //***************************************************************************\n // Calculate RAM_REGOUT_EN\n // The output registers are controlled by the ram_regout_en signal.\n // These registers should be updated either when the output in Stage2 is\n // invalid (preloadstage2), OR when the user is reading, in which case the\n // Stage2 value will go invalid unless it is replenished.\n //***************************************************************************\n assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0;\n\n //***************************************************************************\n // Calculate RAM_RD_EN\n // RAM_RD_EN will be asserted whenever the RAM needs to be read in order to\n // update the value in Stage1.\n // One case when this happens is when preloadstage1=true, which indicates\n // that the data in Stage1 or Stage2 is invalid, and needs to automatically\n // be updated.\n // The other case is when the user is reading from the FIFO, which \n // guarantees that Stage1 or Stage2 will be invalid on the next clock \n // cycle, unless it is replinished by data from the memory. So, as long \n // as the RAM has data in it, a read of the RAM should occur.\n //***************************************************************************\n assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1;\n end\n endgenerate // gnll_fifo\n\n \n\n //***************************************************************************\n // Calculate RAMVALID_P0_OUT\n // RAMVALID_P0_OUT indicates that the data in Stage1 is valid.\n //\n // If the RAM is being read from on this clock cycle (ram_rd_en=1), then\n // RAMVALID_P0_OUT is certainly going to be true.\n // If the RAM is not being read from, but the output registers are being\n // updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,\n // therefore causing RAMVALID_P0_OUT to be false // Otherwise, RAMVALID_P0_OUT will remain unchanged.\n //***************************************************************************\n // PROCESS regout_valid\n generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid\n\n \n always @ (posedge RD_CLK or posedge rd_rst_i) begin \n if (rd_rst_i) begin \n // asynchronous reset (active high)\n fab_valid <= #`TCQ 1'b0;\n end else begin\n if (srst_i) begin \n // synchronous reset (active high)\n fab_valid <= #`TCQ 1'b0;\n end else begin\n if (ram_regout_en == 1'b1) begin\n fab_valid <= #`TCQ 1'b1;\n end else begin\n if (fab_regout_en == 1'b1)\n fab_valid <= #`TCQ 1'b0;\n else\n fab_valid <= #`TCQ fab_valid;\n end\n end //srst_i\n end //rd_rst_i\n end //always\n end endgenerate // gnll_fifo_fab_valid\n\n \n //***************************************************************************\n // Calculate READ_DATA_VALID\n // READ_DATA_VALID indicates whether the value in Stage2 is valid or not.\n // Stage2 has valid data whenever Stage1 had valid data and \n // ram_regout_en_i=1, such that the data in Stage1 is propogated \n // into Stage2.\n //***************************************************************************\n generate if(C_USE_EMBEDDED_REG == 3) begin\n always @ (posedge RD_CLK or posedge rd_rst_i) begin\n if (rd_rst_i)\n read_data_valid_i <= #`TCQ 1'b0;\n else if (srst_i)\n read_data_valid_i <= #`TCQ 1'b0;\n else begin\n if (ram_regout_en == 1'b1) begin\n read_data_valid_i <= #`TCQ 1'b1;\n end else begin\n if (fab_regout_en == 1'b1)\n read_data_valid_i <= #`TCQ 1'b0;\n else\n read_data_valid_i <= #`TCQ read_data_valid_i;\n end \n end \n end //always\nend\nendgenerate\n\n//generate if(C_USE_EMBEDDED_REG == 3) begin\n// always @ (posedge RD_CLK or posedge rd_rst_i) begin\n// if (rd_rst_i)\n// read_data_valid_i <= #`TCQ 1'b0;\n// else if (srst_i)\n// read_data_valid_i <= #`TCQ 1'b0;\n//\n// if (ram_regout_en == 1'b1) begin\n// fab_read_data_valid_i <= #`TCQ 1'b0;\n// end else begin\n// if (fab_regout_en == 1'b1)\n// fab_read_data_valid_i <= #`TCQ 1'b1;\n// else\n// fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i;\n// end \n// end //always\n//end\n//endgenerate\n\n generate if(C_USE_EMBEDDED_REG == 3 ) begin \n always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid\n if (rd_rst_i)\n fab_read_data_valid_i <= #`TCQ 1'b0;\n else if (srst_i)\n fab_read_data_valid_i <= #`TCQ 1'b0;\n else \n fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN);\n end //always\nend\nendgenerate\n \nalways @ (posedge RD_CLK ) begin : proc_del1\n begin\n fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i;\n end\n end //always\n \n \n //**************************************************************************\n // Calculate EMPTY\n // Defined as the inverse of READ_DATA_VALID\n //\n // Description:\n //\n // If read_data_valid_i indicates that the output is not valid,\n // and there is no valid data on the output of the ram to preload it\n // with, then we will report empty.\n //\n // If there is no valid data on the output of the ram and we are\n // reading, then the FIFO will go empty.\n //\n //**************************************************************************\n generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both\n always @ (posedge RD_CLK or posedge rd_rst_i) begin\n if (rd_rst_i) begin\n // asynchronous reset (active high)\n empty_i <= #`TCQ 1'b1;\n end else begin\n if (srst_i) begin\n // synchronous reset (active high)\n empty_i <= #`TCQ 1'b1;\n end else begin\n // rising clock edge\n empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN);\n end\n end\n end //always\n end endgenerate // gnll_fifo_empty_both\n \n // Register RD_EN from user to calculate USERUNDERFLOW.\n // Register empty_i to calculate USERUNDERFLOW.\n always @ (posedge RD_CLK) begin\n rd_en_q <= #`TCQ RD_EN;\n empty_q <= #`TCQ empty_i;\n end //always\n \n \n //***************************************************************************\n // Calculate user_almost_empty\n // user_almost_empty is defined such that, unless more words are written\n // to the FIFO, the next read will cause the FIFO to go EMPTY.\n //\n // In most cases, whenever the output registers are updated (due to a user\n // read or a preload condition), then user_almost_empty will update to\n // whatever RAM_EMPTY is.\n //\n // The exception is when the output is valid, the user is not reading, and\n // Stage1 is not empty. In this condition, Stage1 will be preloaded from the\n // memory, so we need to make sure user_almost_empty deasserts properly under\n // this condition.\n //***************************************************************************\n reg FIFOEMPTY_1;\n generate if (C_USE_EMBEDDED_REG == 3 ) begin\n always @(posedge RD_CLK) begin\n FIFOEMPTY_1 <= #`TCQ FIFOEMPTY;\n end\n end\nendgenerate\n generate if (C_USE_EMBEDDED_REG == 3 ) begin\n always @ (posedge RD_CLK or posedge rd_rst_i)\n begin\n if (rd_rst_i) begin // asynchronous reset (active high)\n almost_empty_i <= #`TCQ 1'b1;\n almost_empty_q <= #`TCQ 1'b1;\n end else begin // rising clock edge\n if (srst_i) begin // synchronous reset (active high)\n almost_empty_i <= #`TCQ 1'b1;\n almost_empty_q <= #`TCQ 1'b1;\n end else begin\n if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin\n almost_empty_i <= #`TCQ (~ram_valid_i);\n end\n almost_empty_q <= #`TCQ empty_i;\n end\n end\n end //always\nend\nendgenerate\n always @ (posedge RD_CLK or posedge rd_rst_i) begin\n if (rd_rst_i) begin\n empty_sckt <= #`TCQ 1'b1;\n sckt_rrst_q <= #`TCQ 1'b0;\n sckt_rrst_done <= #`TCQ 1'b0;\n end else begin\n sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST;\n if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin\n sckt_rrst_done <= #`TCQ 1'b1;\n end else if (sckt_rrst_done) begin\n // rising clock edge\n empty_sckt <= #`TCQ 1'b0;\n end\n end\n end //always\n \n \n// assign USEREMPTY = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i;\n assign USEREMPTY = empty_i;\n assign USERALMOSTEMPTY = almost_empty_i;\n assign FIFORDEN = ram_rd_en;\n assign RAMVALID = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i;\n assign uservalid_both = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3) ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0);\n assign uservalid_one = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3) ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0);\n assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one;\n assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;\n//no safety ckt with both reg\ngenerate \n if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin\n always @ (posedge RD_CLK)\n begin\n if (rd_rst_i || srst_i) begin\n if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)\n USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n user_sbiterr_both <= #`TCQ 0;\n user_dbiterr_both <= #`TCQ 0;\n end\n end //always\n\n \n always @ (posedge RD_CLK or posedge rd_rst_i)\n begin\n if (rd_rst_i) begin //asynchronous reset (active high)\n if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n USERSBITERR <= #`TCQ 0;\n USERDBITERR <= #`TCQ 0;\n user_sbiterr_both <= #`TCQ 0;\n user_dbiterr_both <= #`TCQ 0;\n end\n // DRAM resets asynchronously\n if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)\n USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n user_sbiterr_both <= #`TCQ 0;\n user_dbiterr_both <= #`TCQ 0;\n end\n end else begin // rising clock edge\n if (srst_i) begin\n if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n USERSBITERR <= #`TCQ 0;\n USERDBITERR <= #`TCQ 0;\n user_sbiterr_both <= #`TCQ 0;\n user_dbiterr_both <= #`TCQ 0;\n end\n if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin\n USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n user_sbiterr_both <= #`TCQ 0;\n user_dbiterr_both <= #`TCQ 0;\n end\n end else begin\n if (fwft_rst_done) begin\n if (ram_regout_en) begin\n userdata_both <= #`TCQ FIFODATA; \n user_dbiterr_both <= #`TCQ FIFODBITERR;\n user_sbiterr_both <= #`TCQ FIFOSBITERR; \n end\n if (fab_regout_en) begin\n USERDATA <= #`TCQ userdata_both;\n USERDBITERR <= #`TCQ user_dbiterr_both;\n USERSBITERR <= #`TCQ user_sbiterr_both; \n end \n end \n end\n end\n end //always\n end //if\n endgenerate\n\n//safety_ckt with both registers\n generate\n if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin\n reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;\n reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;\n reg [1:0] rst_delayed_sft1 =1;\n reg [1:0] rst_delayed_sft2 =1;\n reg [1:0] rst_delayed_sft3 =1;\n reg [1:0] rst_delayed_sft4 =1;\n \n always@(posedge RD_CLK) begin\n rst_delayed_sft1 <= #`TCQ rd_rst_i;\n rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;\n rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; \n rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;\n end\n always @ (posedge RD_CLK) begin\n if (rd_rst_i || srst_i) begin\n if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin\n @(posedge RD_CLK)\n USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n user_sbiterr_both <= #`TCQ 0;\n user_dbiterr_both <= #`TCQ 0;\n end\n end\n end //always\n \n always @ (posedge RD_CLK or posedge rd_rst_i) begin\n if (rd_rst_i) begin //asynchronous reset (active high)\n if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n USERSBITERR <= #`TCQ 0;\n USERDBITERR <= #`TCQ 0;\n user_sbiterr_both <= #`TCQ 0;\n user_dbiterr_both <= #`TCQ 0;\n end\n // DRAM resets asynchronously\n if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)\n USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n user_sbiterr_both <= #`TCQ 0;\n user_dbiterr_both <= #`TCQ 0;\n end \n end else begin // rising clock edge\n if (srst_i) begin\n if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF\n USERSBITERR <= #`TCQ 0;\n USERDBITERR <= #`TCQ 0;\n user_sbiterr_both <= #`TCQ 0;\n user_dbiterr_both <= #`TCQ 0;\n end\n if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin\n USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);\n end\n end else if (fwft_rst_done) begin\n if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n userdata_both <= #`TCQ FIFODATA;\n user_dbiterr_both <= #`TCQ FIFODBITERR;\n user_sbiterr_both <= #`TCQ FIFOSBITERR; \n end\n if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin\n USERDATA <= #`TCQ userdata_both;\n USERDBITERR <= #`TCQ user_dbiterr_both;\n USERSBITERR <= #`TCQ user_sbiterr_both;\n end\n end\n end\n end //always\n end //if\nendgenerate\n\nendmodule //fifo_generator_v13_1_2_bhv_ver_preload0\n\n\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n// Register one AXI channel on forward and/or reverse signal path\n//\n// Verilog-standard: Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n// reg_slice\n//\n//--------------------------------------------------------------------------\n\nmodule fifo_generator_v13_1_2_axic_reg_slice #\n (\n parameter C_FAMILY = \"virtex7\",\n parameter C_DATA_WIDTH = 32,\n parameter C_REG_CONFIG = 32'h00000000\n )\n (\n // System Signals\n input wire ACLK,\n input wire ARESET,\n\n // Slave side\n input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n input wire S_VALID,\n output wire S_READY,\n\n // Master side\n output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n output wire M_VALID,\n input wire M_READY\n );\n\n generate\n ////////////////////////////////////////////////////////////////////\n //\n // Both FWD and REV mode\n //\n ////////////////////////////////////////////////////////////////////\n if (C_REG_CONFIG == 32'h00000000)\n begin\n reg [1:0] state;\n localparam [1:0] \n ZERO = 2'b10,\n ONE = 2'b11,\n TWO = 2'b01;\n \n reg [C_DATA_WIDTH-1:0] storage_data1 = 0;\n reg [C_DATA_WIDTH-1:0] storage_data2 = 0;\n reg load_s1;\n wire load_s2;\n wire load_s1_from_s2;\n reg s_ready_i; //local signal of output\n wire m_valid_i; //local signal of output\n\n // assign local signal to its output signal\n assign S_READY = s_ready_i;\n assign M_VALID = m_valid_i;\n\n reg areset_d1; // Reset delay register\n always @(posedge ACLK) begin\n areset_d1 <= ARESET;\n end\n \n // Load storage1 with either slave side data or from storage2\n always @(posedge ACLK) \n begin\n if (load_s1)\n if (load_s1_from_s2)\n storage_data1 <= storage_data2;\n else\n storage_data1 <= S_PAYLOAD_DATA; \n end\n\n // Load storage2 with slave side data\n always @(posedge ACLK) \n begin\n if (load_s2)\n storage_data2 <= S_PAYLOAD_DATA;\n end\n\n assign M_PAYLOAD_DATA = storage_data1;\n\n // Always load s2 on a valid transaction even if it's unnecessary\n assign load_s2 = S_VALID & s_ready_i;\n\n // Loading s1\n always @ *\n begin\n if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction\n // Load when ONE if we both have read and write at the same time\n ((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||\n // Load when TWO and we have a transaction on Master side\n ((state == TWO) && (M_READY == 1)))\n load_s1 = 1'b1;\n else\n load_s1 = 1'b0;\n end // always @ *\n\n assign load_s1_from_s2 = (state == TWO);\n \n // State Machine for handling output signals\n always @(posedge ACLK) begin\n if (ARESET) begin\n s_ready_i <= 1'b0;\n state <= ZERO;\n end else if (areset_d1) begin\n s_ready_i <= 1'b1;\n end else begin\n case (state)\n // No transaction stored locally\n ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE\n\n // One transaction stored locally\n ONE: begin\n if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO\n if (~M_READY & S_VALID) begin\n state <= TWO; // Got another one so move to TWO\n s_ready_i <= 1'b0;\n end\n end\n\n // TWO transaction stored locally\n TWO: if (M_READY) begin\n state <= ONE; // Read out one so move to ONE\n s_ready_i <= 1'b1;\n end\n endcase // case (state)\n end\n end // always @ (posedge ACLK)\n \n assign m_valid_i = state[0];\n\n end // if (C_REG_CONFIG == 1)\n ////////////////////////////////////////////////////////////////////\n //\n // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n // Operates same as 1-deep FIFO\n //\n ////////////////////////////////////////////////////////////////////\n else if (C_REG_CONFIG == 32'h00000001)\n begin\n reg [C_DATA_WIDTH-1:0] storage_data1 = 0;\n reg s_ready_i; //local signal of output\n reg m_valid_i; //local signal of output\n\n // assign local signal to its output signal\n assign S_READY = s_ready_i;\n assign M_VALID = m_valid_i;\n\n reg areset_d1; // Reset delay register\n always @(posedge ACLK) begin\n areset_d1 <= ARESET;\n end\n \n // Load storage1 with slave side data\n always @(posedge ACLK) \n begin\n if (ARESET) begin\n s_ready_i <= 1'b0;\n m_valid_i <= 1'b0;\n end else if (areset_d1) begin\n s_ready_i <= 1'b1;\n end else if (m_valid_i & M_READY) begin\n s_ready_i <= 1'b1;\n m_valid_i <= 1'b0;\n end else if (S_VALID & s_ready_i) begin\n s_ready_i <= 1'b0;\n m_valid_i <= 1'b1;\n end\n if (~m_valid_i) begin\n storage_data1 <= S_PAYLOAD_DATA; \n end\n end\n assign M_PAYLOAD_DATA = storage_data1;\n end // if (C_REG_CONFIG == 7)\n \n else begin : default_case\n // Passthrough\n assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n assign M_VALID = S_VALID;\n assign S_READY = M_READY; \n end\n\n endgenerate\nendmodule // reg_slice\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/mem_init_files/mig_a.prj", "content": "\n\n\n ddr3_if\n 1\n 1\n OFF\n 1024\n ON\n Enabled\n xc7k325t-ffg900/-2\n 4.0\n No Buffer\n Use System Clock\n ACTIVE LOW\n FALSE\n 0\n OFF\n 0\n \n DDR3_SDRAM/Components/MT41J256m16XX-107\n 1112\n 2.0V\n 4:1\n 199.84\n 0\n 899\n 1.000\n 1\n 1\n 1\n 1\n 32\n 1\n 1\n Disabled\n Normal\n 4\n FALSE\n \n 15\n 10\n 3\n 1.5V\n ROW_BANK_COLUMN\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 8 - Fixed\n Sequential\n 13\n Normal\n No\n Slow Exit\n Enable\n RZQ/7\n Disable\n Enable\n RZQ/6\n 0\n Disabled\n Enabled\n Output Buffer Enabled\n Full Array\n 9\n Enabled\n Normal\n Dynamic ODT off\n AXI\n \n RD_PRI_REG_STARVE_LIMIT\n 30\n 256\n 1\n 0\n \n \n\n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/mem_init_files/mig_b.prj", "content": "\n\n\n ddr3_if\n 1\n 1\n OFF\n 1024\n ON\n Enabled\n xc7k325t-ffg900/-2\n 4.0\n No Buffer\n Use System Clock\n ACTIVE LOW\n FALSE\n 0\n OFF\n 0\n \n DDR3_SDRAM/Components/MT41J256m16XX-107\n 1875\n 1.8V\n 4:1\n 200\n 0\n 1066\n 1.000\n 1\n 1\n 1\n 1\n 32\n 1\n 1\n Disabled\n Normal\n 2\n FALSE\n \n 15\n 10\n 3\n 1.5V\n ROW_BANK_COLUMN\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 8 - Fixed\n Sequential\n 7\n Normal\n No\n Slow Exit\n Enable\n RZQ/7\n Disable\n Enable\n RZQ/6\n 0\n Disabled\n Enabled\n Output Buffer Enabled\n Full Array\n 6\n Enabled\n Normal\n Dynamic ODT off\n AXI\n \n RD_PRI_REG_STARVE_LIMIT\n 30\n 256\n 1\n 0\n \n \n\n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/camera_pll_1/activehdl/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/camera_pll_1/ies/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/camera_pll_1/modelsim/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/camera_pll_1/questa/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/camera_pll_1/riviera/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/camera_pll_1/vcs/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/camera_pll_1/xsim/cmd.tcl", "content": "set curr_wave [current_wave_config]\nif { [string length $curr_wave] == 0 } {\n if { [llength [get_objects]] > 0} {\n add_wave /\n set_property needs_save false [current_wave_config]\n } else {\n send_msg_id Add_Wave-1 WARNING \"No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console.\"\n }\n}\n\nrun -all\nquit\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/camera_pll_1/xsim/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/camera_pll_1/xsim/vlog.prj", "content": "verilog xil_defaultlib \"../../../../ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_clk_wiz.v\" --include \"../../../ipstatic\"\nverilog xil_defaultlib \"../../../../ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll.v\" --include \"../../../ipstatic\"\n\nverilog xil_defaultlib \"glbl.v\"\n\nnosort\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/activehdl/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/activehdl/mig_b.prj", "content": "\n\n\n ddr3_if\n 1\n 1\n OFF\n 1024\n ON\n Enabled\n xc7k325t-ffg900/-2\n 4.0\n No Buffer\n Use System Clock\n ACTIVE LOW\n FALSE\n 0\n OFF\n 0\n \n DDR3_SDRAM/Components/MT41J256m16XX-107\n 1112\n 2.0V\n 4:1\n 199.84\n 0\n 899\n 1.000\n 1\n 1\n 1\n 1\n 32\n 1\n 1\n Disabled\n Normal\n 2\n FALSE\n \n 15\n 10\n 3\n 1.5V\n ROW_BANK_COLUMN\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 8 - Fixed\n Sequential\n 13\n Normal\n No\n Slow Exit\n Enable\n RZQ/7\n Disable\n Enable\n RZQ/6\n 0\n Disabled\n Enabled\n Output Buffer Enabled\n Full Array\n 9\n Enabled\n Normal\n Dynamic ODT off\n AXI\n \n RD_PRI_REG_STARVE_LIMIT\n 30\n 256\n 1\n 0\n \n \n\n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/ies/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/ies/mig_b.prj", "content": "\n\n\n ddr3_if\n 1\n 1\n OFF\n 1024\n ON\n Enabled\n xc7k325t-ffg900/-2\n 4.0\n No Buffer\n Use System Clock\n ACTIVE LOW\n FALSE\n 0\n OFF\n 0\n \n DDR3_SDRAM/Components/MT41J256m16XX-107\n 1112\n 2.0V\n 4:1\n 199.84\n 0\n 899\n 1.000\n 1\n 1\n 1\n 1\n 32\n 1\n 1\n Disabled\n Normal\n 2\n FALSE\n \n 15\n 10\n 3\n 1.5V\n ROW_BANK_COLUMN\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 8 - Fixed\n Sequential\n 13\n Normal\n No\n Slow Exit\n Enable\n RZQ/7\n Disable\n Enable\n RZQ/6\n 0\n Disabled\n Enabled\n Output Buffer Enabled\n Full Array\n 9\n Enabled\n Normal\n Dynamic ODT off\n AXI\n \n RD_PRI_REG_STARVE_LIMIT\n 30\n 256\n 1\n 0\n \n \n\n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/modelsim/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/modelsim/mig_b.prj", "content": "\n\n\n ddr3_if\n 1\n 1\n OFF\n 1024\n ON\n Enabled\n xc7k325t-ffg900/-2\n 4.0\n No Buffer\n Use System Clock\n ACTIVE LOW\n FALSE\n 0\n OFF\n 0\n \n DDR3_SDRAM/Components/MT41J256m16XX-107\n 1112\n 2.0V\n 4:1\n 199.84\n 0\n 899\n 1.000\n 1\n 1\n 1\n 1\n 32\n 1\n 1\n Disabled\n Normal\n 2\n FALSE\n \n 15\n 10\n 3\n 1.5V\n ROW_BANK_COLUMN\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 8 - Fixed\n Sequential\n 13\n Normal\n No\n Slow Exit\n Enable\n RZQ/7\n Disable\n Enable\n RZQ/6\n 0\n Disabled\n Enabled\n Output Buffer Enabled\n Full Array\n 9\n Enabled\n Normal\n Dynamic ODT off\n AXI\n \n RD_PRI_REG_STARVE_LIMIT\n 30\n 256\n 1\n 0\n \n \n\n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/questa/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/questa/mig_b.prj", "content": "\n\n\n ddr3_if\n 1\n 1\n OFF\n 1024\n ON\n Enabled\n xc7k325t-ffg900/-2\n 4.0\n No Buffer\n Use System Clock\n ACTIVE LOW\n FALSE\n 0\n OFF\n 0\n \n DDR3_SDRAM/Components/MT41J256m16XX-107\n 1112\n 2.0V\n 4:1\n 199.84\n 0\n 899\n 1.000\n 1\n 1\n 1\n 1\n 32\n 1\n 1\n Disabled\n Normal\n 2\n FALSE\n \n 15\n 10\n 3\n 1.5V\n ROW_BANK_COLUMN\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 8 - Fixed\n Sequential\n 13\n Normal\n No\n Slow Exit\n Enable\n RZQ/7\n Disable\n Enable\n RZQ/6\n 0\n Disabled\n Enabled\n Output Buffer Enabled\n Full Array\n 9\n Enabled\n Normal\n Dynamic ODT off\n AXI\n \n RD_PRI_REG_STARVE_LIMIT\n 30\n 256\n 1\n 0\n \n \n\n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/riviera/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/riviera/mig_b.prj", "content": "\n\n\n ddr3_if\n 1\n 1\n OFF\n 1024\n ON\n Enabled\n xc7k325t-ffg900/-2\n 4.0\n No Buffer\n Use System Clock\n ACTIVE LOW\n FALSE\n 0\n OFF\n 0\n \n DDR3_SDRAM/Components/MT41J256m16XX-107\n 1112\n 2.0V\n 4:1\n 199.84\n 0\n 899\n 1.000\n 1\n 1\n 1\n 1\n 32\n 1\n 1\n Disabled\n Normal\n 2\n FALSE\n \n 15\n 10\n 3\n 1.5V\n ROW_BANK_COLUMN\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 8 - Fixed\n Sequential\n 13\n Normal\n No\n Slow Exit\n Enable\n RZQ/7\n Disable\n Enable\n RZQ/6\n 0\n Disabled\n Enabled\n Output Buffer Enabled\n Full Array\n 9\n Enabled\n Normal\n Dynamic ODT off\n AXI\n \n RD_PRI_REG_STARVE_LIMIT\n 30\n 256\n 1\n 0\n \n \n\n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/vcs/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/vcs/mig_b.prj", "content": "\n\n\n ddr3_if\n 1\n 1\n OFF\n 1024\n ON\n Enabled\n xc7k325t-ffg900/-2\n 4.0\n No Buffer\n Use System Clock\n ACTIVE LOW\n FALSE\n 0\n OFF\n 0\n \n DDR3_SDRAM/Components/MT41J256m16XX-107\n 1112\n 2.0V\n 4:1\n 199.84\n 0\n 899\n 1.000\n 1\n 1\n 1\n 1\n 32\n 1\n 1\n Disabled\n Normal\n 2\n FALSE\n \n 15\n 10\n 3\n 1.5V\n ROW_BANK_COLUMN\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 8 - Fixed\n Sequential\n 13\n Normal\n No\n Slow Exit\n Enable\n RZQ/7\n Disable\n Enable\n RZQ/6\n 0\n Disabled\n Enabled\n Output Buffer Enabled\n Full Array\n 9\n Enabled\n Normal\n Dynamic ODT off\n AXI\n \n RD_PRI_REG_STARVE_LIMIT\n 30\n 256\n 1\n 0\n \n \n\n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/xsim/cmd.tcl", "content": "set curr_wave [current_wave_config]\nif { [string length $curr_wave] == 0 } {\n if { [llength [get_objects]] > 0} {\n add_wave /\n set_property needs_save false [current_wave_config]\n } else {\n send_msg_id Add_Wave-1 WARNING \"No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console.\"\n }\n}\n\nrun -all\nquit\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/xsim/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/xsim/mig_b.prj", "content": "\n\n\n ddr3_if\n 1\n 1\n OFF\n 1024\n ON\n Enabled\n xc7k325t-ffg900/-2\n 4.0\n No Buffer\n Use System Clock\n ACTIVE LOW\n FALSE\n 0\n OFF\n 0\n \n DDR3_SDRAM/Components/MT41J256m16XX-107\n 1112\n 2.0V\n 4:1\n 199.84\n 0\n 899\n 1.000\n 1\n 1\n 1\n 1\n 32\n 1\n 1\n Disabled\n Normal\n 2\n FALSE\n \n 15\n 10\n 3\n 1.5V\n ROW_BANK_COLUMN\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 8 - Fixed\n Sequential\n 13\n Normal\n No\n Slow Exit\n Enable\n RZQ/7\n Disable\n Enable\n RZQ/6\n 0\n Disabled\n Enabled\n Output Buffer Enabled\n Full Array\n 9\n Enabled\n Normal\n Dynamic ODT off\n AXI\n \n RD_PRI_REG_STARVE_LIMIT\n 30\n 256\n 1\n 0\n \n \n\n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/xsim/vlog.prj", "content": "verilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_addr_decode.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_read.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_reg_bank.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_reg.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_top.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_write.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_ar_channel.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_aw_channel.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_b_channel.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_cmd_arbiter.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_cmd_fsm.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_wr_cmd_fsm.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_cmd_translator.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_incr_cmd.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_r_channel.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_simple_fifo.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_fifo.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_w_channel.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_wrap_cmd.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_a_upsizer.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_axi_register_slice.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_axi_upsizer.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_axic_register_slice.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_carry_and.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_carry_latch_and.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_carry_latch_or.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_carry_or.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_command_fifo.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_comparator.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_comparator_sel.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_comparator_sel_static.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_r_upsizer.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_w_upsizer.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/clocking/mig_7series_v4_0_clk_ibuf.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/clocking/mig_7series_v4_0_infrastructure.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/clocking/mig_7series_v4_0_iodelay_ctrl.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/clocking/mig_7series_v4_0_tempmon.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_arb_mux.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_arb_row_col.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_arb_select.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_bank_cntrl.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_bank_common.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_bank_compare.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_bank_mach.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_bank_queue.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_bank_state.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_col_mach.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_mc.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_rank_cntrl.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_rank_common.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_rank_mach.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_round_robin_arb.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/ecc/mig_7series_v4_0_ecc_buf.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/ecc/mig_7series_v4_0_ecc_dec_fix.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/ecc/mig_7series_v4_0_ecc_gen.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/ecc/mig_7series_v4_0_ecc_merge_enc.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/ecc/mig_7series_v4_0_fi_xor.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/ip_top/mig_7series_v4_0_mem_intfc.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/ip_top/mig_7series_v4_0_memc_ui_top_axi.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_byte_group_io.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_byte_lane.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_tempmon.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_calib_top.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_skip_calib_tap.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_if_post_fifo.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_mc_phy.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_mc_phy_wrapper.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_of_pre_fifo.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_4lanes.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_init.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_dqs_found_cal.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_dqs_found_cal_hr.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_oclkdelay_cal.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_prbs_rdlvl.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_rdlvl.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_top.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_wrcal.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_wrlvl.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_wrlvl_off_delay.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_prbs_gen.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_lim.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_top.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_mux.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_data.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_samp.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_edge.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_cntlr.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_pd.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_tap_base.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_meta.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_edge_store.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_cc.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/ui/mig_7series_v4_0_ui_cmd.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/ui/mig_7series_v4_0_ui_rd_data.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/ui/mig_7series_v4_0_ui_top.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/ui/mig_7series_v4_0_ui_wr_data.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/ddr3_if_mig_sim.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/ddr3_if.v\" \n\nverilog xil_defaultlib \"glbl.v\"\n\nnosort\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/activehdl/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/activehdl/mig_a.prj", "content": "\n\n\n ddr3_if\n 1\n 1\n OFF\n 1024\n ON\n Enabled\n xc7k325t-ffg900/-2\n 4.0\n No Buffer\n Use System Clock\n ACTIVE LOW\n FALSE\n 0\n OFF\n 0\n \n DDR3_SDRAM/Components/MT41J256m16XX-107\n 1112\n 2.0V\n 4:1\n 199.84\n 0\n 899\n 1.000\n 1\n 1\n 1\n 1\n 32\n 1\n 1\n Disabled\n Normal\n 4\n FALSE\n \n 15\n 10\n 3\n 1.5V\n ROW_BANK_COLUMN\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 8 - Fixed\n Sequential\n 13\n Normal\n No\n Slow Exit\n Enable\n RZQ/7\n Disable\n Enable\n RZQ/6\n 0\n Disabled\n Enabled\n Output Buffer Enabled\n Full Array\n 9\n Enabled\n Normal\n Dynamic ODT off\n AXI\n \n RD_PRI_REG_STARVE_LIMIT\n 30\n 256\n 1\n 0\n \n \n\n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/ies/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/ies/mig_a.prj", "content": "\n\n\n ddr3_if\n 1\n 1\n OFF\n 1024\n ON\n Enabled\n xc7k325t-ffg900/-2\n 4.0\n No Buffer\n Use System Clock\n ACTIVE LOW\n FALSE\n 0\n OFF\n 0\n \n DDR3_SDRAM/Components/MT41J256m16XX-107\n 1112\n 2.0V\n 4:1\n 199.84\n 0\n 899\n 1.000\n 1\n 1\n 1\n 1\n 32\n 1\n 1\n Disabled\n Normal\n 4\n FALSE\n \n 15\n 10\n 3\n 1.5V\n ROW_BANK_COLUMN\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 8 - Fixed\n Sequential\n 13\n Normal\n No\n Slow Exit\n Enable\n RZQ/7\n Disable\n Enable\n RZQ/6\n 0\n Disabled\n Enabled\n Output Buffer Enabled\n Full Array\n 9\n Enabled\n Normal\n Dynamic ODT off\n AXI\n \n RD_PRI_REG_STARVE_LIMIT\n 30\n 256\n 1\n 0\n \n \n\n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/modelsim/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/modelsim/mig_a.prj", "content": "\n\n\n ddr3_if\n 1\n 1\n OFF\n 1024\n ON\n Enabled\n xc7k325t-ffg900/-2\n 4.0\n No Buffer\n Use System Clock\n ACTIVE LOW\n FALSE\n 0\n OFF\n 0\n \n DDR3_SDRAM/Components/MT41J256m16XX-107\n 1112\n 2.0V\n 4:1\n 199.84\n 0\n 899\n 1.000\n 1\n 1\n 1\n 1\n 32\n 1\n 1\n Disabled\n Normal\n 4\n FALSE\n \n 15\n 10\n 3\n 1.5V\n ROW_BANK_COLUMN\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 8 - Fixed\n Sequential\n 13\n Normal\n No\n Slow Exit\n Enable\n RZQ/7\n Disable\n Enable\n RZQ/6\n 0\n Disabled\n Enabled\n Output Buffer Enabled\n Full Array\n 9\n Enabled\n Normal\n Dynamic ODT off\n AXI\n \n RD_PRI_REG_STARVE_LIMIT\n 30\n 256\n 1\n 0\n \n \n\n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/questa/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/questa/mig_a.prj", "content": "\n\n\n ddr3_if\n 1\n 1\n OFF\n 1024\n ON\n Enabled\n xc7k325t-ffg900/-2\n 4.0\n No Buffer\n Use System Clock\n ACTIVE LOW\n FALSE\n 0\n OFF\n 0\n \n DDR3_SDRAM/Components/MT41J256m16XX-107\n 1112\n 2.0V\n 4:1\n 199.84\n 0\n 899\n 1.000\n 1\n 1\n 1\n 1\n 32\n 1\n 1\n Disabled\n Normal\n 4\n FALSE\n \n 15\n 10\n 3\n 1.5V\n ROW_BANK_COLUMN\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 8 - Fixed\n Sequential\n 13\n Normal\n No\n Slow Exit\n Enable\n RZQ/7\n Disable\n Enable\n RZQ/6\n 0\n Disabled\n Enabled\n Output Buffer Enabled\n Full Array\n 9\n Enabled\n Normal\n Dynamic ODT off\n AXI\n \n RD_PRI_REG_STARVE_LIMIT\n 30\n 256\n 1\n 0\n \n \n\n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/riviera/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/riviera/mig_a.prj", "content": "\n\n\n ddr3_if\n 1\n 1\n OFF\n 1024\n ON\n Enabled\n xc7k325t-ffg900/-2\n 4.0\n No Buffer\n Use System Clock\n ACTIVE LOW\n FALSE\n 0\n OFF\n 0\n \n DDR3_SDRAM/Components/MT41J256m16XX-107\n 1112\n 2.0V\n 4:1\n 199.84\n 0\n 899\n 1.000\n 1\n 1\n 1\n 1\n 32\n 1\n 1\n Disabled\n Normal\n 4\n FALSE\n \n 15\n 10\n 3\n 1.5V\n ROW_BANK_COLUMN\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 8 - Fixed\n Sequential\n 13\n Normal\n No\n Slow Exit\n Enable\n RZQ/7\n Disable\n Enable\n RZQ/6\n 0\n Disabled\n Enabled\n Output Buffer Enabled\n Full Array\n 9\n Enabled\n Normal\n Dynamic ODT off\n AXI\n \n RD_PRI_REG_STARVE_LIMIT\n 30\n 256\n 1\n 0\n \n \n\n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/vcs/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/vcs/mig_a.prj", "content": "\n\n\n ddr3_if\n 1\n 1\n OFF\n 1024\n ON\n Enabled\n xc7k325t-ffg900/-2\n 4.0\n No Buffer\n Use System Clock\n ACTIVE LOW\n FALSE\n 0\n OFF\n 0\n \n DDR3_SDRAM/Components/MT41J256m16XX-107\n 1112\n 2.0V\n 4:1\n 199.84\n 0\n 899\n 1.000\n 1\n 1\n 1\n 1\n 32\n 1\n 1\n Disabled\n Normal\n 4\n FALSE\n \n 15\n 10\n 3\n 1.5V\n ROW_BANK_COLUMN\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 8 - Fixed\n Sequential\n 13\n Normal\n No\n Slow Exit\n Enable\n RZQ/7\n Disable\n Enable\n RZQ/6\n 0\n Disabled\n Enabled\n Output Buffer Enabled\n Full Array\n 9\n Enabled\n Normal\n Dynamic ODT off\n AXI\n \n RD_PRI_REG_STARVE_LIMIT\n 30\n 256\n 1\n 0\n \n \n\n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/xsim/cmd.tcl", "content": "set curr_wave [current_wave_config]\nif { [string length $curr_wave] == 0 } {\n if { [llength [get_objects]] > 0} {\n add_wave /\n set_property needs_save false [current_wave_config]\n } else {\n send_msg_id Add_Wave-1 WARNING \"No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console.\"\n }\n}\n\nrun -all\nquit\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/xsim/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/xsim/mig_a.prj", "content": "\n\n\n ddr3_if\n 1\n 1\n OFF\n 1024\n ON\n Enabled\n xc7k325t-ffg900/-2\n 4.0\n No Buffer\n Use System Clock\n ACTIVE LOW\n FALSE\n 0\n OFF\n 0\n \n DDR3_SDRAM/Components/MT41J256m16XX-107\n 1112\n 2.0V\n 4:1\n 199.84\n 0\n 899\n 1.000\n 1\n 1\n 1\n 1\n 32\n 1\n 1\n Disabled\n Normal\n 4\n FALSE\n \n 15\n 10\n 3\n 1.5V\n ROW_BANK_COLUMN\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 8 - Fixed\n Sequential\n 13\n Normal\n No\n Slow Exit\n Enable\n RZQ/7\n Disable\n Enable\n RZQ/6\n 0\n Disabled\n Enabled\n Output Buffer Enabled\n Full Array\n 9\n Enabled\n Normal\n Dynamic ODT off\n AXI\n \n RD_PRI_REG_STARVE_LIMIT\n 30\n 256\n 1\n 0\n \n \n\n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/xsim/vlog.prj", "content": "verilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_addr_decode.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_read.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_reg_bank.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_reg.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_top.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_write.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_ar_channel.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_aw_channel.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_b_channel.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_cmd_arbiter.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_cmd_fsm.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_wr_cmd_fsm.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_cmd_translator.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_incr_cmd.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_r_channel.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_simple_fifo.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_fifo.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_w_channel.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_wrap_cmd.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_a_upsizer.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_axi_register_slice.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_axi_upsizer.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_axic_register_slice.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_carry_and.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_carry_latch_and.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_carry_latch_or.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_carry_or.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_command_fifo.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_comparator.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_comparator_sel.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_comparator_sel_static.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_r_upsizer.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_w_upsizer.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/clocking/mig_7series_v4_0_clk_ibuf.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/clocking/mig_7series_v4_0_infrastructure.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/clocking/mig_7series_v4_0_iodelay_ctrl.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/clocking/mig_7series_v4_0_tempmon.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_arb_mux.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_arb_row_col.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_arb_select.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_bank_cntrl.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_bank_common.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_bank_compare.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_bank_mach.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_bank_queue.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_bank_state.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_col_mach.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_mc.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_rank_cntrl.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_rank_common.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_rank_mach.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_round_robin_arb.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ecc/mig_7series_v4_0_ecc_buf.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ecc/mig_7series_v4_0_ecc_dec_fix.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ecc/mig_7series_v4_0_ecc_gen.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ecc/mig_7series_v4_0_ecc_merge_enc.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ecc/mig_7series_v4_0_fi_xor.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ip_top/mig_7series_v4_0_mem_intfc.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ip_top/mig_7series_v4_0_memc_ui_top_axi.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_byte_group_io.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_byte_lane.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_tempmon.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_calib_top.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_skip_calib_tap.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_if_post_fifo.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_mc_phy.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_mc_phy_wrapper.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_of_pre_fifo.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_4lanes.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_init.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_dqs_found_cal.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_dqs_found_cal_hr.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_oclkdelay_cal.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_prbs_rdlvl.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_rdlvl.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_top.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_wrcal.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_wrlvl.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_wrlvl_off_delay.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_prbs_gen.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_lim.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_top.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_mux.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_data.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_samp.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_edge.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_cntlr.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_pd.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_tap_base.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_meta.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_edge_store.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_cc.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ui/mig_7series_v4_0_ui_cmd.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ui/mig_7series_v4_0_ui_rd_data.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ui/mig_7series_v4_0_ui_top.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ui/mig_7series_v4_0_ui_wr_data.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ddr3_if_mig_sim.v\" \nverilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ddr3_if.v\" \n\nverilog xil_defaultlib \"glbl.v\"\n\nnosort\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/dvi_pll_1/activehdl/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/dvi_pll_1/ies/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/dvi_pll_1/modelsim/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/dvi_pll_1/questa/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/dvi_pll_1/riviera/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/dvi_pll_1/vcs/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/dvi_pll_1/xsim/cmd.tcl", "content": "set curr_wave [current_wave_config]\nif { [string length $curr_wave] == 0 } {\n if { [llength [get_objects]] > 0} {\n add_wave /\n set_property needs_save false [current_wave_config]\n } else {\n send_msg_id Add_Wave-1 WARNING \"No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console.\"\n }\n}\n\nrun -all\nquit\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/dvi_pll_1/xsim/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/dvi_pll_1/xsim/vlog.prj", "content": "verilog xil_defaultlib \"../../../../ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_clk_wiz.v\" --include \"../../../ipstatic\"\nverilog xil_defaultlib \"../../../../ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll.v\" --include \"../../../ipstatic\"\n\nverilog xil_defaultlib \"glbl.v\"\n\nnosort\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/framebuffer-ctrl/activehdl/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/framebuffer-ctrl/ies/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/framebuffer-ctrl/modelsim/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/framebuffer-ctrl/questa/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/framebuffer-ctrl/riviera/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/framebuffer-ctrl/vcs/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ila_0/activehdl/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ila_0/ies/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ila_0/modelsim/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ila_0/questa/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ila_0/riviera/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ila_0/vcs/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ila_0/xsim/cmd.tcl", "content": "set curr_wave [current_wave_config]\nif { [string length $curr_wave] == 0 } {\n if { [llength [get_objects]] > 0} {\n add_wave /\n set_property needs_save false [current_wave_config]\n } else {\n send_msg_id Add_Wave-1 WARNING \"No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console.\"\n }\n}\n\nrun -all\nquit\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ila_0/xsim/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ila_0/xsim/vlog.prj", "content": "verilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ila_0/sim/ila_0.v\" --include \"../../../../framebuffer_test.srcs/sources_1/ip/ila_0/hdl/verilog\"\n\nverilog xil_defaultlib \"glbl.v\"\n\nnosort\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer/activehdl/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer/ies/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer/modelsim/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer/questa/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer/riviera/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer/vcs/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer/xsim/cmd.tcl", "content": "set curr_wave [current_wave_config]\nif { [string length $curr_wave] == 0 } {\n if { [llength [get_objects]] > 0} {\n add_wave /\n set_property needs_save false [current_wave_config]\n } else {\n send_msg_id Add_Wave-1 WARNING \"No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console.\"\n }\n}\n\nrun -all\nquit\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer/xsim/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer/xsim/vlog.prj", "content": "verilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/input_line_buffer/sim/input_line_buffer.v\" \n\nverilog xil_defaultlib \"glbl.v\"\n\nnosort\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer_1/activehdl/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer_1/ies/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer_1/modelsim/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer_1/questa/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer_1/riviera/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer_1/vcs/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer_1/xsim/cmd.tcl", "content": "set curr_wave [current_wave_config]\nif { [string length $curr_wave] == 0 } {\n if { [llength [get_objects]] > 0} {\n add_wave /\n set_property needs_save false [current_wave_config]\n } else {\n send_msg_id Add_Wave-1 WARNING \"No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console.\"\n }\n}\n\nrun -all\nquit\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer_1/xsim/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer_1/xsim/vlog.prj", "content": "verilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/sim/input_line_buffer.v\" \n\nverilog xil_defaultlib \"glbl.v\"\n\nnosort\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer/activehdl/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer/ies/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer/modelsim/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer/questa/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer/riviera/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer/vcs/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer/xsim/cmd.tcl", "content": "set curr_wave [current_wave_config]\nif { [string length $curr_wave] == 0 } {\n if { [llength [get_objects]] > 0} {\n add_wave /\n set_property needs_save false [current_wave_config]\n } else {\n send_msg_id Add_Wave-1 WARNING \"No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console.\"\n }\n}\n\nrun -all\nquit\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer/xsim/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer/xsim/vlog.prj", "content": "verilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/output_line_buffer/sim/output_line_buffer.v\" \n\nverilog xil_defaultlib \"glbl.v\"\n\nnosort\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer_1/activehdl/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer_1/ies/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer_1/modelsim/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer_1/questa/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer_1/riviera/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer_1/vcs/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer_1/xsim/cmd.tcl", "content": "set curr_wave [current_wave_config]\nif { [string length $curr_wave] == 0 } {\n if { [llength [get_objects]] > 0} {\n add_wave /\n set_property needs_save false [current_wave_config]\n } else {\n send_msg_id Add_Wave-1 WARNING \"No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console.\"\n }\n}\n\nrun -all\nquit\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer_1/xsim/glbl.v", "content": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer_1/xsim/vlog.prj", "content": "verilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/sim/output_line_buffer.v\" \n\nverilog xil_defaultlib \"glbl.v\"\n\nnosort\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/camera_pll_synth_1/camera_pll.tcl", "content": "# \n# Synthesis run script generated by Vivado\n# \n\nset_msg_config -id {HDL 9-1061} -limit 100000\nset_msg_config -id {HDL 9-1654} -limit 100000\nset_msg_config -msgmgr_mode ooc_run\ncreate_project -in_memory -part xc7k325tffg900-2\n\nset_param project.singleFileAddWarning.threshold 0\nset_param project.compositeFile.enableAutoGeneration 0\nset_param synth.vivado.isSynthRun true\nset_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info\nset_property webtalk.parent_dir /home/dave/ip/examples/ov13850_demo/ov13850_demo.cache/wt [current_project]\nset_property parent.project_path /home/dave/ip/examples/ov13850_demo/ov13850_demo.xpr [current_project]\nset_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]\nset_property default_lib xil_defaultlib [current_project]\nset_property target_language Verilog [current_project]\nset_property ip_output_repo /home/dave/ip/examples/ov13850_demo/ov13850_demo.cache/ip [current_project]\nset_property ip_cache_permissions {read write} [current_project]\nread_ip -quiet /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll.xci\nset_property is_locked true [get_files /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll.xci]\n\nforeach dcp [get_files -quiet -all *.dcp] {\n set_property used_in_implementation false $dcp\n}\nread_xdc dont_touch.xdc\nset_property used_in_implementation false [get_files dont_touch.xdc]\n\nset cached_ip [config_ip_cache -export -no_bom -use_project_ipc -dir /home/dave/ip/examples/ov13850_demo/ov13850_demo.runs/camera_pll_synth_1 -new_name camera_pll -ip [get_ips camera_pll]]\n\nif { $cached_ip eq {} } {\n\nsynth_design -top camera_pll -part xc7k325tffg900-2 -mode out_of_context\n\n#---------------------------------------------------------\n# Generate Checkpoint/Stub/Simulation Files For IP Cache\n#---------------------------------------------------------\ncatch {\n write_checkpoint -force -noxdef -rename_prefix camera_pll_ camera_pll.dcp\n\n set ipCachedFiles {}\n write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ camera_pll_stub.v\n lappend ipCachedFiles camera_pll_stub.v\n\n write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ camera_pll_stub.vhdl\n lappend ipCachedFiles camera_pll_stub.vhdl\n\n write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ camera_pll_sim_netlist.v\n lappend ipCachedFiles camera_pll_sim_netlist.v\n\n write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ camera_pll_sim_netlist.vhdl\n lappend ipCachedFiles camera_pll_sim_netlist.vhdl\n\n config_ip_cache -add -dcp camera_pll.dcp -move_files $ipCachedFiles -use_project_ipc -ip [get_ips camera_pll]\n}\n\nrename_ref -prefix_all camera_pll_\n\nwrite_checkpoint -force -noxdef camera_pll.dcp\n\ncatch { report_utilization -file camera_pll_utilization_synth.rpt -pb camera_pll_utilization_synth.pb }\n\nif { [catch {\n file copy -force /home/dave/ip/examples/ov13850_demo/ov13850_demo.runs/camera_pll_synth_1/camera_pll.dcp /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll.dcp\n} _RESULT ] } { \n send_msg_id runtcl-3 error \"ERROR: Unable to successfully create or copy the sub-design checkpoint file.\"\n error \"ERROR: Unable to successfully create or copy the sub-design checkpoint file.\"\n}\n\nif { [catch {\n write_verilog -force -mode synth_stub /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_stub.v\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT\"\n}\n\nif { [catch {\n write_vhdl -force -mode synth_stub /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_stub.vhdl\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT\"\n}\n\nif { [catch {\n write_verilog -force -mode funcsim /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_sim_netlist.v\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT\"\n}\n\nif { [catch {\n write_vhdl -force -mode funcsim /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_sim_netlist.vhdl\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT\"\n}\n\n\n} else {\n\n\nif { [catch {\n file copy -force /home/dave/ip/examples/ov13850_demo/ov13850_demo.runs/camera_pll_synth_1/camera_pll.dcp /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll.dcp\n} _RESULT ] } { \n send_msg_id runtcl-3 error \"ERROR: Unable to successfully create or copy the sub-design checkpoint file.\"\n error \"ERROR: Unable to successfully create or copy the sub-design checkpoint file.\"\n}\n\nif { [catch {\n file rename -force /home/dave/ip/examples/ov13850_demo/ov13850_demo.runs/camera_pll_synth_1/camera_pll_stub.v /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_stub.v\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT\"\n}\n\nif { [catch {\n file rename -force /home/dave/ip/examples/ov13850_demo/ov13850_demo.runs/camera_pll_synth_1/camera_pll_stub.vhdl /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_stub.vhdl\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT\"\n}\n\nif { [catch {\n file rename -force /home/dave/ip/examples/ov13850_demo/ov13850_demo.runs/camera_pll_synth_1/camera_pll_sim_netlist.v /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_sim_netlist.v\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT\"\n}\n\nif { [catch {\n file rename -force /home/dave/ip/examples/ov13850_demo/ov13850_demo.runs/camera_pll_synth_1/camera_pll_sim_netlist.vhdl /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_sim_netlist.vhdl\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT\"\n}\n\n}; # end if cached_ip \n\nif {[file isdir /home/dave/ip/examples/ov13850_demo/ov13850_demo.ip_user_files/ip/camera_pll]} {\n catch { \n file copy -force /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_stub.v /home/dave/ip/examples/ov13850_demo/ov13850_demo.ip_user_files/ip/camera_pll\n }\n}\n\nif {[file isdir /home/dave/ip/examples/ov13850_demo/ov13850_demo.ip_user_files/ip/camera_pll]} {\n catch { \n file copy -force /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_stub.vhdl /home/dave/ip/examples/ov13850_demo/ov13850_demo.ip_user_files/ip/camera_pll\n }\n}\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/camera_pll_synth_1/dont_touch.xdc", "content": "# This file is automatically generated.\n# It contains project source information necessary for synthesis and implementation.\n\n# IP: /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll.xci\n# IP: The module: 'camera_pll' is the root of the design. Do not add the DONT_TOUCH constraint.\n\n# XDC: /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_board.xdc\n# XDC: The top module name and the constraint reference have the same name: 'camera_pll'. Do not add the DONT_TOUCH constraint.\nset_property DONT_TOUCH TRUE [get_cells inst]\n\n# XDC: /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll.xdc\n# XDC: The top module name and the constraint reference have the same name: 'camera_pll'. Do not add the DONT_TOUCH constraint.\n#dup# set_property DONT_TOUCH TRUE [get_cells inst]\n\n# XDC: /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_ooc.xdc\n# XDC: The top module name and the constraint reference have the same name: 'camera_pll'. Do not add the DONT_TOUCH constraint.\n#dup# set_property DONT_TOUCH TRUE [get_cells inst]\n\n# IP: /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll.xci\n# IP: The module: 'camera_pll' is the root of the design. Do not add the DONT_TOUCH constraint.\n\n# XDC: /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_board.xdc\n# XDC: The top module name and the constraint reference have the same name: 'camera_pll'. Do not add the DONT_TOUCH constraint.\n#dup# set_property DONT_TOUCH TRUE [get_cells inst]\n\n# XDC: /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll.xdc\n# XDC: The top module name and the constraint reference have the same name: 'camera_pll'. Do not add the DONT_TOUCH constraint.\n#dup# set_property DONT_TOUCH TRUE [get_cells inst]\n\n# XDC: /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_ooc.xdc\n# XDC: The top module name and the constraint reference have the same name: 'camera_pll'. Do not add the DONT_TOUCH constraint.\n#dup# set_property DONT_TOUCH TRUE [get_cells inst]\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/ddr3_if_synth_1/ddr3_if.tcl", "content": "# \n# Synthesis run script generated by Vivado\n# \n\nset_msg_config -msgmgr_mode ooc_run\ncreate_project -in_memory -part xc7k325tffg900-2\n\nset_param project.singleFileAddWarning.threshold 0\nset_param project.compositeFile.enableAutoGeneration 0\nset_param synth.vivado.isSynthRun true\nset_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info\nset_property webtalk.parent_dir /home/dave/ip/examples/framebuffer_test/framebuffer_test.cache/wt [current_project]\nset_property parent.project_path /home/dave/ip/examples/framebuffer_test/framebuffer_test.xpr [current_project]\nset_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]\nset_property default_lib xil_defaultlib [current_project]\nset_property target_language Verilog [current_project]\nset_property ip_output_repo /home/dave/ip/examples/framebuffer_test/framebuffer_test.cache/ip [current_project]\nset_property ip_cache_permissions {read write} [current_project]\nread_ip -quiet /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if.xci\nset_property is_locked true [get_files /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if.xci]\n\nforeach dcp [get_files -quiet -all *.dcp] {\n set_property used_in_implementation false $dcp\n}\n\nset cached_ip [config_ip_cache -export -no_bom -use_project_ipc -dir /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/ddr3_if_synth_1 -new_name ddr3_if -ip [get_ips ddr3_if]]\n\nif { $cached_ip eq {} } {\n\nsynth_design -top ddr3_if -part xc7k325tffg900-2 -mode out_of_context\n\n#---------------------------------------------------------\n# Generate Checkpoint/Stub/Simulation Files For IP Cache\n#---------------------------------------------------------\ncatch {\n write_checkpoint -force -noxdef -rename_prefix ddr3_if_ ddr3_if.dcp\n\n set ipCachedFiles {}\n write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ddr3_if_stub.v\n lappend ipCachedFiles ddr3_if_stub.v\n\n write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ddr3_if_stub.vhdl\n lappend ipCachedFiles ddr3_if_stub.vhdl\n\n write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ddr3_if_sim_netlist.v\n lappend ipCachedFiles ddr3_if_sim_netlist.v\n\n write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ddr3_if_sim_netlist.vhdl\n lappend ipCachedFiles ddr3_if_sim_netlist.vhdl\n\n config_ip_cache -add -dcp ddr3_if.dcp -move_files $ipCachedFiles -use_project_ipc -ip [get_ips ddr3_if]\n}\n\nrename_ref -prefix_all ddr3_if_\n\nwrite_checkpoint -force -noxdef ddr3_if.dcp\n\ncatch { report_utilization -file ddr3_if_utilization_synth.rpt -pb ddr3_if_utilization_synth.pb }\n\nif { [catch {\n file copy -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/ddr3_if_synth_1/ddr3_if.dcp /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if.dcp\n} _RESULT ] } { \n send_msg_id runtcl-3 error \"ERROR: Unable to successfully create or copy the sub-design checkpoint file.\"\n error \"ERROR: Unable to successfully create or copy the sub-design checkpoint file.\"\n}\n\nif { [catch {\n write_verilog -force -mode synth_stub /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if_stub.v\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT\"\n}\n\nif { [catch {\n write_vhdl -force -mode synth_stub /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if_stub.vhdl\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT\"\n}\n\nif { [catch {\n write_verilog -force -mode funcsim /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if_sim_netlist.v\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT\"\n}\n\nif { [catch {\n write_vhdl -force -mode funcsim /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if_sim_netlist.vhdl\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT\"\n}\n\n\n} else {\n\n\nif { [catch {\n file copy -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/ddr3_if_synth_1/ddr3_if.dcp /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if.dcp\n} _RESULT ] } { \n send_msg_id runtcl-3 error \"ERROR: Unable to successfully create or copy the sub-design checkpoint file.\"\n error \"ERROR: Unable to successfully create or copy the sub-design checkpoint file.\"\n}\n\nif { [catch {\n file rename -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/ddr3_if_synth_1/ddr3_if_stub.v /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if_stub.v\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT\"\n}\n\nif { [catch {\n file rename -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/ddr3_if_synth_1/ddr3_if_stub.vhdl /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if_stub.vhdl\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT\"\n}\n\nif { [catch {\n file rename -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/ddr3_if_synth_1/ddr3_if_sim_netlist.v /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if_sim_netlist.v\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT\"\n}\n\nif { [catch {\n file rename -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/ddr3_if_synth_1/ddr3_if_sim_netlist.vhdl /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if_sim_netlist.vhdl\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT\"\n}\n\n}; # end if cached_ip \n\nif {[file isdir /home/dave/ip/examples/framebuffer_test/framebuffer_test.ip_user_files/ip/ddr3_if]} {\n catch { \n file copy -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if_stub.v /home/dave/ip/examples/framebuffer_test/framebuffer_test.ip_user_files/ip/ddr3_if\n }\n}\n\nif {[file isdir /home/dave/ip/examples/framebuffer_test/framebuffer_test.ip_user_files/ip/ddr3_if]} {\n catch { \n file copy -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if_stub.vhdl /home/dave/ip/examples/framebuffer_test/framebuffer_test.ip_user_files/ip/ddr3_if\n }\n}\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/dvi_pll_synth_1/dont_touch.xdc", "content": "# This file is automatically generated.\n# It contains project source information necessary for synthesis and implementation.\n\n# IP: /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll.xci\n# IP: The module: 'dvi_pll' is the root of the design. Do not add the DONT_TOUCH constraint.\n\n# XDC: /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_board.xdc\n# XDC: The top module name and the constraint reference have the same name: 'dvi_pll'. Do not add the DONT_TOUCH constraint.\nset_property DONT_TOUCH TRUE [get_cells inst]\n\n# XDC: /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll.xdc\n# XDC: The top module name and the constraint reference have the same name: 'dvi_pll'. Do not add the DONT_TOUCH constraint.\n#dup# set_property DONT_TOUCH TRUE [get_cells inst]\n\n# XDC: /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_ooc.xdc\n# XDC: The top module name and the constraint reference have the same name: 'dvi_pll'. Do not add the DONT_TOUCH constraint.\n#dup# set_property DONT_TOUCH TRUE [get_cells inst]\n\n# IP: /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll.xci\n# IP: The module: 'dvi_pll' is the root of the design. Do not add the DONT_TOUCH constraint.\n\n# XDC: /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_board.xdc\n# XDC: The top module name and the constraint reference have the same name: 'dvi_pll'. Do not add the DONT_TOUCH constraint.\n#dup# set_property DONT_TOUCH TRUE [get_cells inst]\n\n# XDC: /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll.xdc\n# XDC: The top module name and the constraint reference have the same name: 'dvi_pll'. Do not add the DONT_TOUCH constraint.\n#dup# set_property DONT_TOUCH TRUE [get_cells inst]\n\n# XDC: /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_ooc.xdc\n# XDC: The top module name and the constraint reference have the same name: 'dvi_pll'. Do not add the DONT_TOUCH constraint.\n#dup# set_property DONT_TOUCH TRUE [get_cells inst]\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/dvi_pll_synth_1/dvi_pll.tcl", "content": "# \n# Synthesis run script generated by Vivado\n# \n\nset_param xicom.use_bs_reader 1\nset_msg_config -id {HDL 9-1061} -limit 100000\nset_msg_config -id {HDL 9-1654} -limit 100000\nset_msg_config -msgmgr_mode ooc_run\ncreate_project -in_memory -part xc7k325tffg900-2\n\nset_param project.singleFileAddWarning.threshold 0\nset_param project.compositeFile.enableAutoGeneration 0\nset_param synth.vivado.isSynthRun true\nset_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info\nset_property webtalk.parent_dir /home/dave/ip/examples/ov13850_demo/ov13850_demo.cache/wt [current_project]\nset_property parent.project_path /home/dave/ip/examples/ov13850_demo/ov13850_demo.xpr [current_project]\nset_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]\nset_property default_lib xil_defaultlib [current_project]\nset_property target_language Verilog [current_project]\nset_property ip_output_repo /home/dave/ip/examples/ov13850_demo/ov13850_demo.cache/ip [current_project]\nset_property ip_cache_permissions {read write} [current_project]\nread_ip -quiet /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll.xci\nset_property is_locked true [get_files /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll.xci]\n\nforeach dcp [get_files -quiet -all *.dcp] {\n set_property used_in_implementation false $dcp\n}\nread_xdc dont_touch.xdc\nset_property used_in_implementation false [get_files dont_touch.xdc]\n\nset cached_ip [config_ip_cache -export -no_bom -use_project_ipc -dir /home/dave/ip/examples/ov13850_demo/ov13850_demo.runs/dvi_pll_synth_1 -new_name dvi_pll -ip [get_ips dvi_pll]]\n\nif { $cached_ip eq {} } {\n\nsynth_design -top dvi_pll -part xc7k325tffg900-2 -mode out_of_context\n\n#---------------------------------------------------------\n# Generate Checkpoint/Stub/Simulation Files For IP Cache\n#---------------------------------------------------------\ncatch {\n write_checkpoint -force -noxdef -rename_prefix dvi_pll_ dvi_pll.dcp\n\n set ipCachedFiles {}\n write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dvi_pll_stub.v\n lappend ipCachedFiles dvi_pll_stub.v\n\n write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dvi_pll_stub.vhdl\n lappend ipCachedFiles dvi_pll_stub.vhdl\n\n write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dvi_pll_sim_netlist.v\n lappend ipCachedFiles dvi_pll_sim_netlist.v\n\n write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dvi_pll_sim_netlist.vhdl\n lappend ipCachedFiles dvi_pll_sim_netlist.vhdl\n\n config_ip_cache -add -dcp dvi_pll.dcp -move_files $ipCachedFiles -use_project_ipc -ip [get_ips dvi_pll]\n}\n\nrename_ref -prefix_all dvi_pll_\n\nwrite_checkpoint -force -noxdef dvi_pll.dcp\n\ncatch { report_utilization -file dvi_pll_utilization_synth.rpt -pb dvi_pll_utilization_synth.pb }\n\nif { [catch {\n file copy -force /home/dave/ip/examples/ov13850_demo/ov13850_demo.runs/dvi_pll_synth_1/dvi_pll.dcp /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll.dcp\n} _RESULT ] } { \n send_msg_id runtcl-3 error \"ERROR: Unable to successfully create or copy the sub-design checkpoint file.\"\n error \"ERROR: Unable to successfully create or copy the sub-design checkpoint file.\"\n}\n\nif { [catch {\n write_verilog -force -mode synth_stub /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_stub.v\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT\"\n}\n\nif { [catch {\n write_vhdl -force -mode synth_stub /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_stub.vhdl\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT\"\n}\n\nif { [catch {\n write_verilog -force -mode funcsim /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_sim_netlist.v\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT\"\n}\n\nif { [catch {\n write_vhdl -force -mode funcsim /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_sim_netlist.vhdl\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT\"\n}\n\n\n} else {\n\n\nif { [catch {\n file copy -force /home/dave/ip/examples/ov13850_demo/ov13850_demo.runs/dvi_pll_synth_1/dvi_pll.dcp /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll.dcp\n} _RESULT ] } { \n send_msg_id runtcl-3 error \"ERROR: Unable to successfully create or copy the sub-design checkpoint file.\"\n error \"ERROR: Unable to successfully create or copy the sub-design checkpoint file.\"\n}\n\nif { [catch {\n file rename -force /home/dave/ip/examples/ov13850_demo/ov13850_demo.runs/dvi_pll_synth_1/dvi_pll_stub.v /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_stub.v\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT\"\n}\n\nif { [catch {\n file rename -force /home/dave/ip/examples/ov13850_demo/ov13850_demo.runs/dvi_pll_synth_1/dvi_pll_stub.vhdl /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_stub.vhdl\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT\"\n}\n\nif { [catch {\n file rename -force /home/dave/ip/examples/ov13850_demo/ov13850_demo.runs/dvi_pll_synth_1/dvi_pll_sim_netlist.v /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_sim_netlist.v\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT\"\n}\n\nif { [catch {\n file rename -force /home/dave/ip/examples/ov13850_demo/ov13850_demo.runs/dvi_pll_synth_1/dvi_pll_sim_netlist.vhdl /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_sim_netlist.vhdl\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT\"\n}\n\n}; # end if cached_ip \n\nif {[file isdir /home/dave/ip/examples/ov13850_demo/ov13850_demo.ip_user_files/ip/dvi_pll]} {\n catch { \n file copy -force /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_stub.v /home/dave/ip/examples/ov13850_demo/ov13850_demo.ip_user_files/ip/dvi_pll\n }\n}\n\nif {[file isdir /home/dave/ip/examples/ov13850_demo/ov13850_demo.ip_user_files/ip/dvi_pll]} {\n catch { \n file copy -force /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_stub.vhdl /home/dave/ip/examples/ov13850_demo/ov13850_demo.ip_user_files/ip/dvi_pll\n }\n}\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/impl_1/ov13850_demo.tcl", "content": "proc start_step { step } {\n set stopFile \".stop.rst\"\n if {[file isfile .stop.rst]} {\n puts \"\"\n puts \"*** Halting run - EA reset detected ***\"\n puts \"\"\n puts \"\"\n return -code error\n }\n set beginFile \".$step.begin.rst\"\n set platform \"$::tcl_platform(platform)\"\n set user \"$::tcl_platform(user)\"\n set pid [pid]\n set host \"\"\n if { [string equal $platform unix] } {\n if { [info exist ::env(HOSTNAME)] } {\n set host $::env(HOSTNAME)\n }\n } else {\n if { [info exist ::env(COMPUTERNAME)] } {\n set host $::env(COMPUTERNAME)\n }\n }\n set ch [open $beginFile w]\n puts $ch \"\"\n puts $ch \"\"\n puts $ch \" \"\n puts $ch \" \"\n puts $ch \"\"\n close $ch\n}\n\nproc end_step { step } {\n set endFile \".$step.end.rst\"\n set ch [open $endFile w]\n close $ch\n}\n\nproc step_failed { step } {\n set endFile \".$step.error.rst\"\n set ch [open $endFile w]\n close $ch\n}\n\nset_msg_config -id {HDL 9-1061} -limit 100000\nset_msg_config -id {HDL 9-1654} -limit 100000\n\nstart_step write_bitstream\nset ACTIVE_STEP write_bitstream\nset rc [catch {\n create_msg_db write_bitstream.pb\n set_param xicom.use_bs_reader 1\n open_checkpoint ov13850_demo_routed.dcp\n set_property webtalk.parent_dir /home/dave/ip/examples/ov13850_demo/ov13850_demo.cache/wt [current_project]\n set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]\n catch { write_mem_info -force ov13850_demo.mmi }\n write_bitstream -force -no_partial_bitfile ov13850_demo.bit \n catch { write_sysdef -hwdef ov13850_demo.hwdef -bitfile ov13850_demo.bit -meminfo ov13850_demo.mmi -file ov13850_demo.sysdef }\n catch {write_debug_probes -quiet -force debug_nets}\n close_msg_db -file write_bitstream.pb\n} RESULT]\nif {$rc} {\n step_failed write_bitstream\n return -code error $RESULT\n} else {\n end_step write_bitstream\n unset ACTIVE_STEP \n}\n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/input_line_buffer_synth_1/dont_touch.xdc", "content": "# This file is automatically generated.\n# It contains project source information necessary for synthesis and implementation.\n\n# IP: /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer.xci\n# IP: The module: 'input_line_buffer' is the root of the design. Do not add the DONT_TOUCH constraint.\n\n# XDC: /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_ooc.xdc\n# XDC: The top module name and the constraint reference have the same name: 'input_line_buffer'. Do not add the DONT_TOUCH constraint.\nset_property DONT_TOUCH TRUE [get_cells U0]\n\n# IP: /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer.xci\n# IP: The module: 'input_line_buffer' is the root of the design. Do not add the DONT_TOUCH constraint.\n\n# XDC: /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_ooc.xdc\n# XDC: The top module name and the constraint reference have the same name: 'input_line_buffer'. Do not add the DONT_TOUCH constraint.\n#dup# set_property DONT_TOUCH TRUE [get_cells U0]\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/input_line_buffer_synth_1/input_line_buffer.tcl", "content": "# \n# Synthesis run script generated by Vivado\n# \n\nset_msg_config -msgmgr_mode ooc_run\ncreate_project -in_memory -part xc7k325tffg900-2\n\nset_param project.singleFileAddWarning.threshold 0\nset_param project.compositeFile.enableAutoGeneration 0\nset_param synth.vivado.isSynthRun true\nset_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info\nset_property webtalk.parent_dir /home/dave/ip/examples/framebuffer_test/framebuffer_test.cache/wt [current_project]\nset_property parent.project_path /home/dave/ip/examples/framebuffer_test/framebuffer_test.xpr [current_project]\nset_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]\nset_property default_lib xil_defaultlib [current_project]\nset_property target_language Verilog [current_project]\nset_property ip_output_repo /home/dave/ip/examples/framebuffer_test/framebuffer_test.cache/ip [current_project]\nset_property ip_cache_permissions {read write} [current_project]\nread_ip -quiet /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer.xci\nset_property is_locked true [get_files /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer.xci]\n\nforeach dcp [get_files -quiet -all *.dcp] {\n set_property used_in_implementation false $dcp\n}\nread_xdc dont_touch.xdc\nset_property used_in_implementation false [get_files dont_touch.xdc]\n\nset cached_ip [config_ip_cache -export -no_bom -use_project_ipc -dir /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/input_line_buffer_synth_1 -new_name input_line_buffer -ip [get_ips input_line_buffer]]\n\nif { $cached_ip eq {} } {\n\nsynth_design -top input_line_buffer -part xc7k325tffg900-2 -mode out_of_context\n\n#---------------------------------------------------------\n# Generate Checkpoint/Stub/Simulation Files For IP Cache\n#---------------------------------------------------------\ncatch {\n write_checkpoint -force -noxdef -rename_prefix input_line_buffer_ input_line_buffer.dcp\n\n set ipCachedFiles {}\n write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ input_line_buffer_stub.v\n lappend ipCachedFiles input_line_buffer_stub.v\n\n write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ input_line_buffer_stub.vhdl\n lappend ipCachedFiles input_line_buffer_stub.vhdl\n\n write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ input_line_buffer_sim_netlist.v\n lappend ipCachedFiles input_line_buffer_sim_netlist.v\n\n write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ input_line_buffer_sim_netlist.vhdl\n lappend ipCachedFiles input_line_buffer_sim_netlist.vhdl\n\n config_ip_cache -add -dcp input_line_buffer.dcp -move_files $ipCachedFiles -use_project_ipc -ip [get_ips input_line_buffer]\n}\n\nrename_ref -prefix_all input_line_buffer_\n\nwrite_checkpoint -force -noxdef input_line_buffer.dcp\n\ncatch { report_utilization -file input_line_buffer_utilization_synth.rpt -pb input_line_buffer_utilization_synth.pb }\n\nif { [catch {\n file copy -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/input_line_buffer_synth_1/input_line_buffer.dcp /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer.dcp\n} _RESULT ] } { \n send_msg_id runtcl-3 error \"ERROR: Unable to successfully create or copy the sub-design checkpoint file.\"\n error \"ERROR: Unable to successfully create or copy the sub-design checkpoint file.\"\n}\n\nif { [catch {\n write_verilog -force -mode synth_stub /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_stub.v\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT\"\n}\n\nif { [catch {\n write_vhdl -force -mode synth_stub /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_stub.vhdl\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT\"\n}\n\nif { [catch {\n write_verilog -force -mode funcsim /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_sim_netlist.v\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT\"\n}\n\nif { [catch {\n write_vhdl -force -mode funcsim /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_sim_netlist.vhdl\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT\"\n}\n\n\n} else {\n\n\nif { [catch {\n file copy -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/input_line_buffer_synth_1/input_line_buffer.dcp /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer.dcp\n} _RESULT ] } { \n send_msg_id runtcl-3 error \"ERROR: Unable to successfully create or copy the sub-design checkpoint file.\"\n error \"ERROR: Unable to successfully create or copy the sub-design checkpoint file.\"\n}\n\nif { [catch {\n file rename -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/input_line_buffer_synth_1/input_line_buffer_stub.v /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_stub.v\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT\"\n}\n\nif { [catch {\n file rename -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/input_line_buffer_synth_1/input_line_buffer_stub.vhdl /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_stub.vhdl\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT\"\n}\n\nif { [catch {\n file rename -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/input_line_buffer_synth_1/input_line_buffer_sim_netlist.v /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_sim_netlist.v\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT\"\n}\n\nif { [catch {\n file rename -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/input_line_buffer_synth_1/input_line_buffer_sim_netlist.vhdl /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_sim_netlist.vhdl\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT\"\n}\n\n}; # end if cached_ip \n\nif {[file isdir /home/dave/ip/examples/framebuffer_test/framebuffer_test.ip_user_files/ip/input_line_buffer]} {\n catch { \n file copy -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_stub.v /home/dave/ip/examples/framebuffer_test/framebuffer_test.ip_user_files/ip/input_line_buffer\n }\n}\n\nif {[file isdir /home/dave/ip/examples/framebuffer_test/framebuffer_test.ip_user_files/ip/input_line_buffer]} {\n catch { \n file copy -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_stub.vhdl /home/dave/ip/examples/framebuffer_test/framebuffer_test.ip_user_files/ip/input_line_buffer\n }\n}\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/input_line_buffer_synth_1/input_line_buffer_sim_netlist.v", "content": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// --------------------------------------------------------------------------------\n// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016\n// Date : Tue Nov 15 09:41:00 2016\n// Host : david-desktop-arch running 64-bit unknown\n// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix\n// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ input_line_buffer_sim_netlist.v\n// Design : input_line_buffer\n// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified\n// or synthesized. This netlist cannot be used for SDF annotated simulation.\n// Device : xc7k325tffg900-2\n// --------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CHECK_LICENSE_TYPE = \"input_line_buffer,blk_mem_gen_v8_3_4,{}\" *) (* downgradeipidentifiedwarnings = \"yes\" *) (* x_core_info = \"blk_mem_gen_v8_3_4,Vivado 2016.3\" *) \n(* NotValidForBitStream *)\nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix\n (clka,\n ena,\n wea,\n addra,\n dina,\n clkb,\n addrb,\n doutb);\n (* x_interface_info = \"xilinx.com:interface:bram:1.0 BRAM_PORTA CLK\" *) input clka;\n (* x_interface_info = \"xilinx.com:interface:bram:1.0 BRAM_PORTA EN\" *) input ena;\n (* x_interface_info = \"xilinx.com:interface:bram:1.0 BRAM_PORTA WE\" *) input [0:0]wea;\n (* x_interface_info = \"xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR\" *) input [11:0]addra;\n (* x_interface_info = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DIN\" *) input [63:0]dina;\n (* x_interface_info = \"xilinx.com:interface:bram:1.0 BRAM_PORTB CLK\" *) input clkb;\n (* x_interface_info = \"xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR\" *) input [9:0]addrb;\n (* x_interface_info = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT\" *) output [255:0]doutb;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [63:0]dina;\n wire [255:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire NLW_U0_dbiterr_UNCONNECTED;\n wire NLW_U0_rsta_busy_UNCONNECTED;\n wire NLW_U0_rstb_busy_UNCONNECTED;\n wire NLW_U0_s_axi_arready_UNCONNECTED;\n wire NLW_U0_s_axi_awready_UNCONNECTED;\n wire NLW_U0_s_axi_bvalid_UNCONNECTED;\n wire NLW_U0_s_axi_dbiterr_UNCONNECTED;\n wire NLW_U0_s_axi_rlast_UNCONNECTED;\n wire NLW_U0_s_axi_rvalid_UNCONNECTED;\n wire NLW_U0_s_axi_sbiterr_UNCONNECTED;\n wire NLW_U0_s_axi_wready_UNCONNECTED;\n wire NLW_U0_sbiterr_UNCONNECTED;\n wire [63:0]NLW_U0_douta_UNCONNECTED;\n wire [9:0]NLW_U0_rdaddrecc_UNCONNECTED;\n wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;\n wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;\n wire [9:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;\n wire [255:0]NLW_U0_s_axi_rdata_UNCONNECTED;\n wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;\n wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;\n\n (* C_ADDRA_WIDTH = \"12\" *) \n (* C_ADDRB_WIDTH = \"10\" *) \n (* C_ALGORITHM = \"1\" *) \n (* C_AXI_ID_WIDTH = \"4\" *) \n (* C_AXI_SLAVE_TYPE = \"0\" *) \n (* C_AXI_TYPE = \"1\" *) \n (* C_BYTE_SIZE = \"9\" *) \n (* C_COMMON_CLK = \"0\" *) \n (* C_COUNT_18K_BRAM = \"1\" *) \n (* C_COUNT_36K_BRAM = \"7\" *) \n (* C_CTRL_ECC_ALGO = \"NONE\" *) \n (* C_DEFAULT_DATA = \"0\" *) \n (* C_DISABLE_WARN_BHV_COLL = \"0\" *) \n (* C_DISABLE_WARN_BHV_RANGE = \"0\" *) \n (* C_ELABORATION_DIR = \"./\" *) \n (* C_ENABLE_32BIT_ADDRESS = \"0\" *) \n (* C_EN_DEEPSLEEP_PIN = \"0\" *) \n (* C_EN_ECC_PIPE = \"0\" *) \n (* C_EN_RDADDRA_CHG = \"0\" *) \n (* C_EN_RDADDRB_CHG = \"0\" *) \n (* C_EN_SAFETY_CKT = \"0\" *) \n (* C_EN_SHUTDOWN_PIN = \"0\" *) \n (* C_EN_SLEEP_PIN = \"0\" *) \n (* C_EST_POWER_SUMMARY = \"Estimated Power for IP : 36.714252 mW\" *) \n (* C_FAMILY = \"kintex7\" *) \n (* C_HAS_AXI_ID = \"0\" *) \n (* C_HAS_ENA = \"1\" *) \n (* C_HAS_ENB = \"0\" *) \n (* C_HAS_INJECTERR = \"0\" *) \n (* C_HAS_MEM_OUTPUT_REGS_A = \"0\" *) \n (* C_HAS_MEM_OUTPUT_REGS_B = \"0\" *) \n (* C_HAS_MUX_OUTPUT_REGS_A = \"0\" *) \n (* C_HAS_MUX_OUTPUT_REGS_B = \"0\" *) \n (* C_HAS_REGCEA = \"0\" *) \n (* C_HAS_REGCEB = \"0\" *) \n (* C_HAS_RSTA = \"0\" *) \n (* C_HAS_RSTB = \"0\" *) \n (* C_HAS_SOFTECC_INPUT_REGS_A = \"0\" *) \n (* C_HAS_SOFTECC_OUTPUT_REGS_B = \"0\" *) \n (* C_INITA_VAL = \"0\" *) \n (* C_INITB_VAL = \"0\" *) \n (* C_INIT_FILE = \"input_line_buffer.mem\" *) \n (* C_INIT_FILE_NAME = \"no_coe_file_loaded\" *) \n (* C_INTERFACE_TYPE = \"0\" *) \n (* C_LOAD_INIT_FILE = \"0\" *) \n (* C_MEM_TYPE = \"1\" *) \n (* C_MUX_PIPELINE_STAGES = \"0\" *) \n (* C_PRIM_TYPE = \"1\" *) \n (* C_READ_DEPTH_A = \"4096\" *) \n (* C_READ_DEPTH_B = \"1024\" *) \n (* C_READ_WIDTH_A = \"64\" *) \n (* C_READ_WIDTH_B = \"256\" *) \n (* C_RSTRAM_A = \"0\" *) \n (* C_RSTRAM_B = \"0\" *) \n (* C_RST_PRIORITY_A = \"CE\" *) \n (* C_RST_PRIORITY_B = \"CE\" *) \n (* C_SIM_COLLISION_CHECK = \"ALL\" *) \n (* C_USE_BRAM_BLOCK = \"0\" *) \n (* C_USE_BYTE_WEA = \"0\" *) \n (* C_USE_BYTE_WEB = \"0\" *) \n (* C_USE_DEFAULT_DATA = \"0\" *) \n (* C_USE_ECC = \"0\" *) \n (* C_USE_SOFTECC = \"0\" *) \n (* C_USE_URAM = \"0\" *) \n (* C_WEA_WIDTH = \"1\" *) \n (* C_WEB_WIDTH = \"1\" *) \n (* C_WRITE_DEPTH_A = \"4096\" *) \n (* C_WRITE_DEPTH_B = \"1024\" *) \n (* C_WRITE_MODE_A = \"NO_CHANGE\" *) \n (* C_WRITE_MODE_B = \"WRITE_FIRST\" *) \n (* C_WRITE_WIDTH_A = \"64\" *) \n (* C_WRITE_WIDTH_B = \"256\" *) \n (* C_XDEVICEFAMILY = \"kintex7\" *) \n (* downgradeipidentifiedwarnings = \"yes\" *) \n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 U0\n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dbiterr(NLW_U0_dbiterr_UNCONNECTED),\n .deepsleep(1'b0),\n .dina(dina),\n .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .douta(NLW_U0_douta_UNCONNECTED[63:0]),\n .doutb(doutb),\n .eccpipece(1'b0),\n .ena(ena),\n .enb(1'b0),\n .injectdbiterr(1'b0),\n .injectsbiterr(1'b0),\n .rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[9:0]),\n .regcea(1'b0),\n .regceb(1'b0),\n .rsta(1'b0),\n .rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),\n .rstb(1'b0),\n .rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),\n .s_aclk(1'b0),\n .s_aresetn(1'b0),\n .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axi_arburst({1'b0,1'b0}),\n .s_axi_arid({1'b0,1'b0,1'b0,1'b0}),\n .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),\n .s_axi_arsize({1'b0,1'b0,1'b0}),\n .s_axi_arvalid(1'b0),\n .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axi_awburst({1'b0,1'b0}),\n .s_axi_awid({1'b0,1'b0,1'b0,1'b0}),\n .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),\n .s_axi_awsize({1'b0,1'b0,1'b0}),\n .s_axi_awvalid(1'b0),\n .s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),\n .s_axi_bready(1'b0),\n .s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),\n .s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),\n .s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),\n .s_axi_injectdbiterr(1'b0),\n .s_axi_injectsbiterr(1'b0),\n .s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[9:0]),\n .s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[255:0]),\n .s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),\n .s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),\n .s_axi_rready(1'b0),\n .s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),\n .s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),\n .s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),\n .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axi_wlast(1'b0),\n .s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),\n .s_axi_wstrb(1'b0),\n .s_axi_wvalid(1'b0),\n .sbiterr(NLW_U0_sbiterr_UNCONNECTED),\n .shutdown(1'b0),\n .sleep(1'b0),\n .wea(wea),\n .web(1'b0));\nendmodule\n\nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [255:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [63:0]dina;\n input [0:0]wea;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [63:0]dina;\n wire [255:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width \\ramloop[0].ram.r \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina[3:0]),\n .doutb({doutb[195:192],doutb[131:128],doutb[67:64],doutb[3:0]}),\n .ena(ena),\n .wea(wea));\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0 \\ramloop[1].ram.r \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina[12:4]),\n .doutb({doutb[204:196],doutb[140:132],doutb[76:68],doutb[12:4]}),\n .ena(ena),\n .wea(wea));\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1 \\ramloop[2].ram.r \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina[21:13]),\n .doutb({doutb[213:205],doutb[149:141],doutb[85:77],doutb[21:13]}),\n .ena(ena),\n .wea(wea));\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2 \\ramloop[3].ram.r \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina[30:22]),\n .doutb({doutb[222:214],doutb[158:150],doutb[94:86],doutb[30:22]}),\n .ena(ena),\n .wea(wea));\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3 \\ramloop[4].ram.r \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina[39:31]),\n .doutb({doutb[231:223],doutb[167:159],doutb[103:95],doutb[39:31]}),\n .ena(ena),\n .wea(wea));\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4 \\ramloop[5].ram.r \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina[48:40]),\n .doutb({doutb[240:232],doutb[176:168],doutb[112:104],doutb[48:40]}),\n .ena(ena),\n .wea(wea));\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5 \\ramloop[6].ram.r \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina[57:49]),\n .doutb({doutb[249:241],doutb[185:177],doutb[121:113],doutb[57:49]}),\n .ena(ena),\n .wea(wea));\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6 \\ramloop[7].ram.r \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina[63:58]),\n .doutb({doutb[255:250],doutb[191:186],doutb[127:122],doutb[63:58]}),\n .ena(ena),\n .wea(wea));\nendmodule\n\nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [15:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [3:0]dina;\n input [0:0]wea;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [3:0]dina;\n wire [15:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper \\prim_noinit.ram \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [35:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [8:0]dina;\n input [0:0]wea;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [8:0]dina;\n wire [35:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0 \\prim_noinit.ram \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [35:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [8:0]dina;\n input [0:0]wea;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [8:0]dina;\n wire [35:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1 \\prim_noinit.ram \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [35:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [8:0]dina;\n input [0:0]wea;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [8:0]dina;\n wire [35:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2 \\prim_noinit.ram \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [35:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [8:0]dina;\n input [0:0]wea;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [8:0]dina;\n wire [35:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3 \\prim_noinit.ram \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [35:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [8:0]dina;\n input [0:0]wea;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [8:0]dina;\n wire [35:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4 \\prim_noinit.ram \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [35:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [8:0]dina;\n input [0:0]wea;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [8:0]dina;\n wire [35:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5 \\prim_noinit.ram \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [23:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [5:0]dina;\n input [0:0]wea;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [5:0]dina;\n wire [23:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6 \\prim_noinit.ram \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [15:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [3:0]dina;\n input [0:0]wea;\n\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_34 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_35 ;\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [3:0]dina;\n wire [15:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire [15:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ;\n wire [1:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB18E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(18'h00000),\n .INIT_B(18'h00000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_MODE(\"TDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(18),\n .READ_WIDTH_B(18),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(18'h00000),\n .SRVAL_B(18'h00000),\n .WRITE_MODE_A(\"NO_CHANGE\"),\n .WRITE_MODE_B(\"NO_CHANGE\"),\n .WRITE_WIDTH_A(4),\n .WRITE_WIDTH_B(4)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram \n (.ADDRARDADDR({addra,1'b0,1'b0}),\n .ADDRBWRADDR({addrb,1'b0,1'b0,1'b0,1'b0}),\n .CLKARDCLK(clka),\n .CLKBWRCLK(clkb),\n .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIPADIP({1'b0,1'b0}),\n .DIPBDIP({1'b0,1'b0}),\n .DOADO(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:0]),\n .DOBDO(doutb),\n .DOPADOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]),\n .DOPBDOP({\\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_34 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_35 }),\n .ENARDEN(ena),\n .ENBWREN(1'b1),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(1'b0),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .WEA({wea,wea}),\n .WEBWE({1'b0,1'b0,1'b0,1'b0}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [35:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [8:0]dina;\n input [0:0]wea;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [8:0]dina;\n wire [35:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;\n wire [31:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;\n wire [3:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;\n wire [7:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;\n wire [8:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB36E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .EN_ECC_READ(\"FALSE\"),\n .EN_ECC_WRITE(\"FALSE\"),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(36'h000000000),\n .INIT_B(36'h000000000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_EXTENSION_A(\"NONE\"),\n .RAM_EXTENSION_B(\"NONE\"),\n .RAM_MODE(\"TDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(36),\n .READ_WIDTH_B(36),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(36'h000000000),\n .SRVAL_B(36'h000000000),\n .WRITE_MODE_A(\"NO_CHANGE\"),\n .WRITE_MODE_B(\"NO_CHANGE\"),\n .WRITE_WIDTH_A(9),\n .WRITE_WIDTH_B(9)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram \n (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),\n .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .CASCADEINA(1'b0),\n .CASCADEINB(1'b0),\n .CASCADEOUTA(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),\n .CASCADEOUTB(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),\n .CLKARDCLK(clka),\n .CLKBWRCLK(clkb),\n .DBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),\n .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIPADIP({1'b0,1'b0,1'b0,dina[8]}),\n .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),\n .DOADO(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),\n .DOBDO({doutb[34:27],doutb[25:18],doutb[16:9],doutb[7:0]}),\n .DOPADOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),\n .DOPBDOP({doutb[35],doutb[26],doutb[17],doutb[8]}),\n .ECCPARITY(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),\n .ENARDEN(ena),\n .ENBWREN(1'b1),\n .INJECTDBITERR(1'b0),\n .INJECTSBITERR(1'b0),\n .RDADDRECC(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(1'b0),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .SBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),\n .WEA({wea,wea,wea,wea}),\n .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [35:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [8:0]dina;\n input [0:0]wea;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [8:0]dina;\n wire [35:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;\n wire [31:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;\n wire [3:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;\n wire [7:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;\n wire [8:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB36E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .EN_ECC_READ(\"FALSE\"),\n .EN_ECC_WRITE(\"FALSE\"),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(36'h000000000),\n .INIT_B(36'h000000000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_EXTENSION_A(\"NONE\"),\n .RAM_EXTENSION_B(\"NONE\"),\n .RAM_MODE(\"TDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(36),\n .READ_WIDTH_B(36),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(36'h000000000),\n .SRVAL_B(36'h000000000),\n .WRITE_MODE_A(\"NO_CHANGE\"),\n .WRITE_MODE_B(\"NO_CHANGE\"),\n .WRITE_WIDTH_A(9),\n .WRITE_WIDTH_B(9)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram \n (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),\n .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .CASCADEINA(1'b0),\n .CASCADEINB(1'b0),\n .CASCADEOUTA(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),\n .CASCADEOUTB(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),\n .CLKARDCLK(clka),\n .CLKBWRCLK(clkb),\n .DBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),\n .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIPADIP({1'b0,1'b0,1'b0,dina[8]}),\n .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),\n .DOADO(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),\n .DOBDO({doutb[34:27],doutb[25:18],doutb[16:9],doutb[7:0]}),\n .DOPADOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),\n .DOPBDOP({doutb[35],doutb[26],doutb[17],doutb[8]}),\n .ECCPARITY(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),\n .ENARDEN(ena),\n .ENBWREN(1'b1),\n .INJECTDBITERR(1'b0),\n .INJECTSBITERR(1'b0),\n .RDADDRECC(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(1'b0),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .SBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),\n .WEA({wea,wea,wea,wea}),\n .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [35:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [8:0]dina;\n input [0:0]wea;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [8:0]dina;\n wire [35:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;\n wire [31:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;\n wire [3:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;\n wire [7:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;\n wire [8:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB36E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .EN_ECC_READ(\"FALSE\"),\n .EN_ECC_WRITE(\"FALSE\"),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(36'h000000000),\n .INIT_B(36'h000000000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_EXTENSION_A(\"NONE\"),\n .RAM_EXTENSION_B(\"NONE\"),\n .RAM_MODE(\"TDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(36),\n .READ_WIDTH_B(36),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(36'h000000000),\n .SRVAL_B(36'h000000000),\n .WRITE_MODE_A(\"NO_CHANGE\"),\n .WRITE_MODE_B(\"NO_CHANGE\"),\n .WRITE_WIDTH_A(9),\n .WRITE_WIDTH_B(9)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram \n (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),\n .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .CASCADEINA(1'b0),\n .CASCADEINB(1'b0),\n .CASCADEOUTA(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),\n .CASCADEOUTB(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),\n .CLKARDCLK(clka),\n .CLKBWRCLK(clkb),\n .DBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),\n .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIPADIP({1'b0,1'b0,1'b0,dina[8]}),\n .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),\n .DOADO(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),\n .DOBDO({doutb[34:27],doutb[25:18],doutb[16:9],doutb[7:0]}),\n .DOPADOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),\n .DOPBDOP({doutb[35],doutb[26],doutb[17],doutb[8]}),\n .ECCPARITY(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),\n .ENARDEN(ena),\n .ENBWREN(1'b1),\n .INJECTDBITERR(1'b0),\n .INJECTSBITERR(1'b0),\n .RDADDRECC(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(1'b0),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .SBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),\n .WEA({wea,wea,wea,wea}),\n .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [35:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [8:0]dina;\n input [0:0]wea;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [8:0]dina;\n wire [35:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;\n wire [31:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;\n wire [3:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;\n wire [7:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;\n wire [8:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB36E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .EN_ECC_READ(\"FALSE\"),\n .EN_ECC_WRITE(\"FALSE\"),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(36'h000000000),\n .INIT_B(36'h000000000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_EXTENSION_A(\"NONE\"),\n .RAM_EXTENSION_B(\"NONE\"),\n .RAM_MODE(\"TDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(36),\n .READ_WIDTH_B(36),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(36'h000000000),\n .SRVAL_B(36'h000000000),\n .WRITE_MODE_A(\"NO_CHANGE\"),\n .WRITE_MODE_B(\"NO_CHANGE\"),\n .WRITE_WIDTH_A(9),\n .WRITE_WIDTH_B(9)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram \n (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),\n .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .CASCADEINA(1'b0),\n .CASCADEINB(1'b0),\n .CASCADEOUTA(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),\n .CASCADEOUTB(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),\n .CLKARDCLK(clka),\n .CLKBWRCLK(clkb),\n .DBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),\n .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIPADIP({1'b0,1'b0,1'b0,dina[8]}),\n .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),\n .DOADO(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),\n .DOBDO({doutb[34:27],doutb[25:18],doutb[16:9],doutb[7:0]}),\n .DOPADOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),\n .DOPBDOP({doutb[35],doutb[26],doutb[17],doutb[8]}),\n .ECCPARITY(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),\n .ENARDEN(ena),\n .ENBWREN(1'b1),\n .INJECTDBITERR(1'b0),\n .INJECTSBITERR(1'b0),\n .RDADDRECC(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(1'b0),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .SBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),\n .WEA({wea,wea,wea,wea}),\n .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [35:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [8:0]dina;\n input [0:0]wea;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [8:0]dina;\n wire [35:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;\n wire [31:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;\n wire [3:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;\n wire [7:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;\n wire [8:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB36E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .EN_ECC_READ(\"FALSE\"),\n .EN_ECC_WRITE(\"FALSE\"),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(36'h000000000),\n .INIT_B(36'h000000000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_EXTENSION_A(\"NONE\"),\n .RAM_EXTENSION_B(\"NONE\"),\n .RAM_MODE(\"TDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(36),\n .READ_WIDTH_B(36),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(36'h000000000),\n .SRVAL_B(36'h000000000),\n .WRITE_MODE_A(\"NO_CHANGE\"),\n .WRITE_MODE_B(\"NO_CHANGE\"),\n .WRITE_WIDTH_A(9),\n .WRITE_WIDTH_B(9)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram \n (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),\n .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .CASCADEINA(1'b0),\n .CASCADEINB(1'b0),\n .CASCADEOUTA(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),\n .CASCADEOUTB(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),\n .CLKARDCLK(clka),\n .CLKBWRCLK(clkb),\n .DBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),\n .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIPADIP({1'b0,1'b0,1'b0,dina[8]}),\n .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),\n .DOADO(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),\n .DOBDO({doutb[34:27],doutb[25:18],doutb[16:9],doutb[7:0]}),\n .DOPADOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),\n .DOPBDOP({doutb[35],doutb[26],doutb[17],doutb[8]}),\n .ECCPARITY(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),\n .ENARDEN(ena),\n .ENBWREN(1'b1),\n .INJECTDBITERR(1'b0),\n .INJECTSBITERR(1'b0),\n .RDADDRECC(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(1'b0),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .SBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),\n .WEA({wea,wea,wea,wea}),\n .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [35:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [8:0]dina;\n input [0:0]wea;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [8:0]dina;\n wire [35:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;\n wire [31:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;\n wire [3:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;\n wire [7:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;\n wire [8:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB36E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .EN_ECC_READ(\"FALSE\"),\n .EN_ECC_WRITE(\"FALSE\"),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(36'h000000000),\n .INIT_B(36'h000000000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_EXTENSION_A(\"NONE\"),\n .RAM_EXTENSION_B(\"NONE\"),\n .RAM_MODE(\"TDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(36),\n .READ_WIDTH_B(36),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(36'h000000000),\n .SRVAL_B(36'h000000000),\n .WRITE_MODE_A(\"NO_CHANGE\"),\n .WRITE_MODE_B(\"NO_CHANGE\"),\n .WRITE_WIDTH_A(9),\n .WRITE_WIDTH_B(9)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram \n (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),\n .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .CASCADEINA(1'b0),\n .CASCADEINB(1'b0),\n .CASCADEOUTA(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),\n .CASCADEOUTB(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),\n .CLKARDCLK(clka),\n .CLKBWRCLK(clkb),\n .DBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),\n .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIPADIP({1'b0,1'b0,1'b0,dina[8]}),\n .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),\n .DOADO(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),\n .DOBDO({doutb[34:27],doutb[25:18],doutb[16:9],doutb[7:0]}),\n .DOPADOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),\n .DOPBDOP({doutb[35],doutb[26],doutb[17],doutb[8]}),\n .ECCPARITY(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),\n .ENARDEN(ena),\n .ENBWREN(1'b1),\n .INJECTDBITERR(1'b0),\n .INJECTSBITERR(1'b0),\n .RDADDRECC(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(1'b0),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .SBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),\n .WEA({wea,wea,wea,wea}),\n .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [23:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [5:0]dina;\n input [0:0]wea;\n\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_54 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_62 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_70 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ;\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [5:0]dina;\n wire [23:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;\n wire [31:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;\n wire [3:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;\n wire [7:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;\n wire [8:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB36E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .EN_ECC_READ(\"FALSE\"),\n .EN_ECC_WRITE(\"FALSE\"),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(36'h000000000),\n .INIT_B(36'h000000000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_EXTENSION_A(\"NONE\"),\n .RAM_EXTENSION_B(\"NONE\"),\n .RAM_MODE(\"TDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(36),\n .READ_WIDTH_B(36),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(36'h000000000),\n .SRVAL_B(36'h000000000),\n .WRITE_MODE_A(\"NO_CHANGE\"),\n .WRITE_MODE_B(\"NO_CHANGE\"),\n .WRITE_WIDTH_A(9),\n .WRITE_WIDTH_B(9)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram \n (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),\n .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .CASCADEINA(1'b0),\n .CASCADEINB(1'b0),\n .CASCADEOUTA(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),\n .CASCADEOUTB(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),\n .CLKARDCLK(clka),\n .CLKBWRCLK(clkb),\n .DBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),\n .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIPADIP({1'b0,1'b0,1'b0,1'b0}),\n .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),\n .DOADO(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),\n .DOBDO({\\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_54 ,doutb[23:18],\\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_62 ,doutb[17:12],\\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_70 ,doutb[11:6],\\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78 ,doutb[5:0]}),\n .DOPADOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),\n .DOPBDOP({\\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }),\n .ECCPARITY(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),\n .ENARDEN(ena),\n .ENBWREN(1'b1),\n .INJECTDBITERR(1'b0),\n .INJECTSBITERR(1'b0),\n .RDADDRECC(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(1'b0),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .SBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),\n .WEA({wea,wea,wea,wea}),\n .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));\nendmodule\n\nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [255:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [63:0]dina;\n input [0:0]wea;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [63:0]dina;\n wire [255:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr \\valid.cstr \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* C_ADDRA_WIDTH = \"12\" *) (* C_ADDRB_WIDTH = \"10\" *) (* C_ALGORITHM = \"1\" *) \n(* C_AXI_ID_WIDTH = \"4\" *) (* C_AXI_SLAVE_TYPE = \"0\" *) (* C_AXI_TYPE = \"1\" *) \n(* C_BYTE_SIZE = \"9\" *) (* C_COMMON_CLK = \"0\" *) (* C_COUNT_18K_BRAM = \"1\" *) \n(* C_COUNT_36K_BRAM = \"7\" *) (* C_CTRL_ECC_ALGO = \"NONE\" *) (* C_DEFAULT_DATA = \"0\" *) \n(* C_DISABLE_WARN_BHV_COLL = \"0\" *) (* C_DISABLE_WARN_BHV_RANGE = \"0\" *) (* C_ELABORATION_DIR = \"./\" *) \n(* C_ENABLE_32BIT_ADDRESS = \"0\" *) (* C_EN_DEEPSLEEP_PIN = \"0\" *) (* C_EN_ECC_PIPE = \"0\" *) \n(* C_EN_RDADDRA_CHG = \"0\" *) (* C_EN_RDADDRB_CHG = \"0\" *) (* C_EN_SAFETY_CKT = \"0\" *) \n(* C_EN_SHUTDOWN_PIN = \"0\" *) (* C_EN_SLEEP_PIN = \"0\" *) (* C_EST_POWER_SUMMARY = \"Estimated Power for IP : 36.714252 mW\" *) \n(* C_FAMILY = \"kintex7\" *) (* C_HAS_AXI_ID = \"0\" *) (* C_HAS_ENA = \"1\" *) \n(* C_HAS_ENB = \"0\" *) (* C_HAS_INJECTERR = \"0\" *) (* C_HAS_MEM_OUTPUT_REGS_A = \"0\" *) \n(* C_HAS_MEM_OUTPUT_REGS_B = \"0\" *) (* C_HAS_MUX_OUTPUT_REGS_A = \"0\" *) (* C_HAS_MUX_OUTPUT_REGS_B = \"0\" *) \n(* C_HAS_REGCEA = \"0\" *) (* C_HAS_REGCEB = \"0\" *) (* C_HAS_RSTA = \"0\" *) \n(* C_HAS_RSTB = \"0\" *) (* C_HAS_SOFTECC_INPUT_REGS_A = \"0\" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = \"0\" *) \n(* C_INITA_VAL = \"0\" *) (* C_INITB_VAL = \"0\" *) (* C_INIT_FILE = \"input_line_buffer.mem\" *) \n(* C_INIT_FILE_NAME = \"no_coe_file_loaded\" *) (* C_INTERFACE_TYPE = \"0\" *) (* C_LOAD_INIT_FILE = \"0\" *) \n(* C_MEM_TYPE = \"1\" *) (* C_MUX_PIPELINE_STAGES = \"0\" *) (* C_PRIM_TYPE = \"1\" *) \n(* C_READ_DEPTH_A = \"4096\" *) (* C_READ_DEPTH_B = \"1024\" *) (* C_READ_WIDTH_A = \"64\" *) \n(* C_READ_WIDTH_B = \"256\" *) (* C_RSTRAM_A = \"0\" *) (* C_RSTRAM_B = \"0\" *) \n(* C_RST_PRIORITY_A = \"CE\" *) (* C_RST_PRIORITY_B = \"CE\" *) (* C_SIM_COLLISION_CHECK = \"ALL\" *) \n(* C_USE_BRAM_BLOCK = \"0\" *) (* C_USE_BYTE_WEA = \"0\" *) (* C_USE_BYTE_WEB = \"0\" *) \n(* C_USE_DEFAULT_DATA = \"0\" *) (* C_USE_ECC = \"0\" *) (* C_USE_SOFTECC = \"0\" *) \n(* C_USE_URAM = \"0\" *) (* C_WEA_WIDTH = \"1\" *) (* C_WEB_WIDTH = \"1\" *) \n(* C_WRITE_DEPTH_A = \"4096\" *) (* C_WRITE_DEPTH_B = \"1024\" *) (* C_WRITE_MODE_A = \"NO_CHANGE\" *) \n(* C_WRITE_MODE_B = \"WRITE_FIRST\" *) (* C_WRITE_WIDTH_A = \"64\" *) (* C_WRITE_WIDTH_B = \"256\" *) \n(* C_XDEVICEFAMILY = \"kintex7\" *) (* downgradeipidentifiedwarnings = \"yes\" *) \nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4\n (clka,\n rsta,\n ena,\n regcea,\n wea,\n addra,\n dina,\n douta,\n clkb,\n rstb,\n enb,\n regceb,\n web,\n addrb,\n dinb,\n doutb,\n injectsbiterr,\n injectdbiterr,\n eccpipece,\n sbiterr,\n dbiterr,\n rdaddrecc,\n sleep,\n deepsleep,\n shutdown,\n rsta_busy,\n rstb_busy,\n s_aclk,\n s_aresetn,\n s_axi_awid,\n s_axi_awaddr,\n s_axi_awlen,\n s_axi_awsize,\n s_axi_awburst,\n s_axi_awvalid,\n s_axi_awready,\n s_axi_wdata,\n s_axi_wstrb,\n s_axi_wlast,\n s_axi_wvalid,\n s_axi_wready,\n s_axi_bid,\n s_axi_bresp,\n s_axi_bvalid,\n s_axi_bready,\n s_axi_arid,\n s_axi_araddr,\n s_axi_arlen,\n s_axi_arsize,\n s_axi_arburst,\n s_axi_arvalid,\n s_axi_arready,\n s_axi_rid,\n s_axi_rdata,\n s_axi_rresp,\n s_axi_rlast,\n s_axi_rvalid,\n s_axi_rready,\n s_axi_injectsbiterr,\n s_axi_injectdbiterr,\n s_axi_sbiterr,\n s_axi_dbiterr,\n s_axi_rdaddrecc);\n input clka;\n input rsta;\n input ena;\n input regcea;\n input [0:0]wea;\n input [11:0]addra;\n input [63:0]dina;\n output [63:0]douta;\n input clkb;\n input rstb;\n input enb;\n input regceb;\n input [0:0]web;\n input [9:0]addrb;\n input [255:0]dinb;\n output [255:0]doutb;\n input injectsbiterr;\n input injectdbiterr;\n input eccpipece;\n output sbiterr;\n output dbiterr;\n output [9:0]rdaddrecc;\n input sleep;\n input deepsleep;\n input shutdown;\n output rsta_busy;\n output rstb_busy;\n input s_aclk;\n input s_aresetn;\n input [3:0]s_axi_awid;\n input [31:0]s_axi_awaddr;\n input [7:0]s_axi_awlen;\n input [2:0]s_axi_awsize;\n input [1:0]s_axi_awburst;\n input s_axi_awvalid;\n output s_axi_awready;\n input [63:0]s_axi_wdata;\n input [0:0]s_axi_wstrb;\n input s_axi_wlast;\n input s_axi_wvalid;\n output s_axi_wready;\n output [3:0]s_axi_bid;\n output [1:0]s_axi_bresp;\n output s_axi_bvalid;\n input s_axi_bready;\n input [3:0]s_axi_arid;\n input [31:0]s_axi_araddr;\n input [7:0]s_axi_arlen;\n input [2:0]s_axi_arsize;\n input [1:0]s_axi_arburst;\n input s_axi_arvalid;\n output s_axi_arready;\n output [3:0]s_axi_rid;\n output [255:0]s_axi_rdata;\n output [1:0]s_axi_rresp;\n output s_axi_rlast;\n output s_axi_rvalid;\n input s_axi_rready;\n input s_axi_injectsbiterr;\n input s_axi_injectdbiterr;\n output s_axi_sbiterr;\n output s_axi_dbiterr;\n output [9:0]s_axi_rdaddrecc;\n\n wire \\ ;\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [63:0]dina;\n wire [255:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n assign dbiterr = \\ ;\n assign douta[63] = \\ ;\n assign douta[62] = \\ ;\n assign douta[61] = \\ ;\n assign douta[60] = \\ ;\n assign douta[59] = \\ ;\n assign douta[58] = \\ ;\n assign douta[57] = \\ ;\n assign douta[56] = \\ ;\n assign douta[55] = \\ ;\n assign douta[54] = \\ ;\n assign douta[53] = \\ ;\n assign douta[52] = \\ ;\n assign douta[51] = \\ ;\n assign douta[50] = \\ ;\n assign douta[49] = \\ ;\n assign douta[48] = \\ ;\n assign douta[47] = \\ ;\n assign douta[46] = \\ ;\n assign douta[45] = \\ ;\n assign douta[44] = \\ ;\n assign douta[43] = \\ ;\n assign douta[42] = \\ ;\n assign douta[41] = \\ ;\n assign douta[40] = \\ ;\n assign douta[39] = \\ ;\n assign douta[38] = \\ ;\n assign douta[37] = \\ ;\n assign douta[36] = \\ ;\n assign douta[35] = \\ ;\n assign douta[34] = \\ ;\n assign douta[33] = \\ ;\n assign douta[32] = \\ ;\n assign douta[31] = \\ ;\n assign douta[30] = \\ ;\n assign douta[29] = \\ ;\n assign douta[28] = \\ ;\n assign douta[27] = \\ ;\n assign douta[26] = \\ ;\n assign douta[25] = \\ ;\n assign douta[24] = \\ ;\n assign douta[23] = \\ ;\n assign douta[22] = \\ ;\n assign douta[21] = \\ ;\n assign douta[20] = \\ ;\n assign douta[19] = \\ ;\n assign douta[18] = \\ ;\n assign douta[17] = \\ ;\n assign douta[16] = \\ ;\n assign douta[15] = \\ ;\n assign douta[14] = \\ ;\n assign douta[13] = \\ ;\n assign douta[12] = \\ ;\n assign douta[11] = \\ ;\n assign douta[10] = \\ ;\n assign douta[9] = \\ ;\n assign douta[8] = \\ ;\n assign douta[7] = \\ ;\n assign douta[6] = \\ ;\n assign douta[5] = \\ ;\n assign douta[4] = \\ ;\n assign douta[3] = \\ ;\n assign douta[2] = \\ ;\n assign douta[1] = \\ ;\n assign douta[0] = \\ ;\n assign rdaddrecc[9] = \\ ;\n assign rdaddrecc[8] = \\ ;\n assign rdaddrecc[7] = \\ ;\n assign rdaddrecc[6] = \\ ;\n assign rdaddrecc[5] = \\ ;\n assign rdaddrecc[4] = \\ ;\n assign rdaddrecc[3] = \\ ;\n assign rdaddrecc[2] = \\ ;\n assign rdaddrecc[1] = \\ ;\n assign rdaddrecc[0] = \\ ;\n assign rsta_busy = \\ ;\n assign rstb_busy = \\ ;\n assign s_axi_arready = \\ ;\n assign s_axi_awready = \\ ;\n assign s_axi_bid[3] = \\ ;\n assign s_axi_bid[2] = \\ ;\n assign s_axi_bid[1] = \\ ;\n assign s_axi_bid[0] = \\ ;\n assign s_axi_bresp[1] = \\ ;\n assign s_axi_bresp[0] = \\ ;\n assign s_axi_bvalid = \\ ;\n assign s_axi_dbiterr = \\ ;\n assign s_axi_rdaddrecc[9] = \\ ;\n assign s_axi_rdaddrecc[8] = \\ ;\n assign s_axi_rdaddrecc[7] = \\ ;\n assign s_axi_rdaddrecc[6] = \\ ;\n assign s_axi_rdaddrecc[5] = \\ ;\n assign s_axi_rdaddrecc[4] = \\ ;\n assign s_axi_rdaddrecc[3] = \\ ;\n assign s_axi_rdaddrecc[2] = \\ ;\n assign s_axi_rdaddrecc[1] = \\ ;\n assign s_axi_rdaddrecc[0] = \\ ;\n assign s_axi_rdata[255] = \\ ;\n assign s_axi_rdata[254] = \\ ;\n assign s_axi_rdata[253] = \\ ;\n assign s_axi_rdata[252] = \\ ;\n assign s_axi_rdata[251] = \\ ;\n assign s_axi_rdata[250] = \\ ;\n assign s_axi_rdata[249] = \\ ;\n assign s_axi_rdata[248] = \\ ;\n assign s_axi_rdata[247] = \\ ;\n assign s_axi_rdata[246] = \\ ;\n assign s_axi_rdata[245] = \\ ;\n assign s_axi_rdata[244] = \\ ;\n assign s_axi_rdata[243] = \\ ;\n assign s_axi_rdata[242] = \\ ;\n assign s_axi_rdata[241] = \\ ;\n assign s_axi_rdata[240] = \\ ;\n assign s_axi_rdata[239] = \\ ;\n assign s_axi_rdata[238] = \\ ;\n assign s_axi_rdata[237] = \\ ;\n assign s_axi_rdata[236] = \\ ;\n assign s_axi_rdata[235] = \\ ;\n assign s_axi_rdata[234] = \\ ;\n assign s_axi_rdata[233] = \\ ;\n assign s_axi_rdata[232] = \\ ;\n assign s_axi_rdata[231] = \\ ;\n assign s_axi_rdata[230] = \\ ;\n assign s_axi_rdata[229] = \\ ;\n assign s_axi_rdata[228] = \\ ;\n assign s_axi_rdata[227] = \\ ;\n assign s_axi_rdata[226] = \\ ;\n assign s_axi_rdata[225] = \\ ;\n assign s_axi_rdata[224] = \\ ;\n assign s_axi_rdata[223] = \\ ;\n assign s_axi_rdata[222] = \\ ;\n assign s_axi_rdata[221] = \\ ;\n assign s_axi_rdata[220] = \\ ;\n assign s_axi_rdata[219] = \\ ;\n assign s_axi_rdata[218] = \\ ;\n assign s_axi_rdata[217] = \\ ;\n assign s_axi_rdata[216] = \\ ;\n assign s_axi_rdata[215] = \\ ;\n assign s_axi_rdata[214] = \\ ;\n assign s_axi_rdata[213] = \\ ;\n assign s_axi_rdata[212] = \\ ;\n assign s_axi_rdata[211] = \\ ;\n assign s_axi_rdata[210] = \\ ;\n assign s_axi_rdata[209] = \\ ;\n assign s_axi_rdata[208] = \\ ;\n assign s_axi_rdata[207] = \\ ;\n assign s_axi_rdata[206] = \\ ;\n assign s_axi_rdata[205] = \\ ;\n assign s_axi_rdata[204] = \\ ;\n assign s_axi_rdata[203] = \\ ;\n assign s_axi_rdata[202] = \\ ;\n assign s_axi_rdata[201] = \\ ;\n assign s_axi_rdata[200] = \\ ;\n assign s_axi_rdata[199] = \\ ;\n assign s_axi_rdata[198] = \\ ;\n assign s_axi_rdata[197] = \\ ;\n assign s_axi_rdata[196] = \\ ;\n assign s_axi_rdata[195] = \\ ;\n assign s_axi_rdata[194] = \\ ;\n assign s_axi_rdata[193] = \\ ;\n assign s_axi_rdata[192] = \\ ;\n assign s_axi_rdata[191] = \\ ;\n assign s_axi_rdata[190] = \\ ;\n assign s_axi_rdata[189] = \\ ;\n assign s_axi_rdata[188] = \\ ;\n assign s_axi_rdata[187] = \\ ;\n assign s_axi_rdata[186] = \\ ;\n assign s_axi_rdata[185] = \\ ;\n assign s_axi_rdata[184] = \\ ;\n assign s_axi_rdata[183] = \\ ;\n assign s_axi_rdata[182] = \\ ;\n assign s_axi_rdata[181] = \\ ;\n assign s_axi_rdata[180] = \\ ;\n assign s_axi_rdata[179] = \\ ;\n assign s_axi_rdata[178] = \\ ;\n assign s_axi_rdata[177] = \\ ;\n assign s_axi_rdata[176] = \\ ;\n assign s_axi_rdata[175] = \\ ;\n assign s_axi_rdata[174] = \\ ;\n assign s_axi_rdata[173] = \\ ;\n assign s_axi_rdata[172] = \\ ;\n assign s_axi_rdata[171] = \\ ;\n assign s_axi_rdata[170] = \\ ;\n assign s_axi_rdata[169] = \\ ;\n assign s_axi_rdata[168] = \\ ;\n assign s_axi_rdata[167] = \\ ;\n assign s_axi_rdata[166] = \\ ;\n assign s_axi_rdata[165] = \\ ;\n assign s_axi_rdata[164] = \\ ;\n assign s_axi_rdata[163] = \\ ;\n assign s_axi_rdata[162] = \\ ;\n assign s_axi_rdata[161] = \\ ;\n assign s_axi_rdata[160] = \\ ;\n assign s_axi_rdata[159] = \\ ;\n assign s_axi_rdata[158] = \\ ;\n assign s_axi_rdata[157] = \\ ;\n assign s_axi_rdata[156] = \\ ;\n assign s_axi_rdata[155] = \\ ;\n assign s_axi_rdata[154] = \\ ;\n assign s_axi_rdata[153] = \\ ;\n assign s_axi_rdata[152] = \\ ;\n assign s_axi_rdata[151] = \\ ;\n assign s_axi_rdata[150] = \\ ;\n assign s_axi_rdata[149] = \\ ;\n assign s_axi_rdata[148] = \\ ;\n assign s_axi_rdata[147] = \\ ;\n assign s_axi_rdata[146] = \\ ;\n assign s_axi_rdata[145] = \\ ;\n assign s_axi_rdata[144] = \\ ;\n assign s_axi_rdata[143] = \\ ;\n assign s_axi_rdata[142] = \\ ;\n assign s_axi_rdata[141] = \\ ;\n assign s_axi_rdata[140] = \\ ;\n assign s_axi_rdata[139] = \\ ;\n assign s_axi_rdata[138] = \\ ;\n assign s_axi_rdata[137] = \\ ;\n assign s_axi_rdata[136] = \\ ;\n assign s_axi_rdata[135] = \\ ;\n assign s_axi_rdata[134] = \\ ;\n assign s_axi_rdata[133] = \\ ;\n assign s_axi_rdata[132] = \\ ;\n assign s_axi_rdata[131] = \\ ;\n assign s_axi_rdata[130] = \\ ;\n assign s_axi_rdata[129] = \\ ;\n assign s_axi_rdata[128] = \\ ;\n assign s_axi_rdata[127] = \\ ;\n assign s_axi_rdata[126] = \\ ;\n assign s_axi_rdata[125] = \\ ;\n assign s_axi_rdata[124] = \\ ;\n assign s_axi_rdata[123] = \\ ;\n assign s_axi_rdata[122] = \\ ;\n assign s_axi_rdata[121] = \\ ;\n assign s_axi_rdata[120] = \\ ;\n assign s_axi_rdata[119] = \\ ;\n assign s_axi_rdata[118] = \\ ;\n assign s_axi_rdata[117] = \\ ;\n assign s_axi_rdata[116] = \\ ;\n assign s_axi_rdata[115] = \\ ;\n assign s_axi_rdata[114] = \\ ;\n assign s_axi_rdata[113] = \\ ;\n assign s_axi_rdata[112] = \\ ;\n assign s_axi_rdata[111] = \\ ;\n assign s_axi_rdata[110] = \\ ;\n assign s_axi_rdata[109] = \\ ;\n assign s_axi_rdata[108] = \\ ;\n assign s_axi_rdata[107] = \\ ;\n assign s_axi_rdata[106] = \\ ;\n assign s_axi_rdata[105] = \\ ;\n assign s_axi_rdata[104] = \\ ;\n assign s_axi_rdata[103] = \\ ;\n assign s_axi_rdata[102] = \\ ;\n assign s_axi_rdata[101] = \\ ;\n assign s_axi_rdata[100] = \\ ;\n assign s_axi_rdata[99] = \\ ;\n assign s_axi_rdata[98] = \\ ;\n assign s_axi_rdata[97] = \\ ;\n assign s_axi_rdata[96] = \\ ;\n assign s_axi_rdata[95] = \\ ;\n assign s_axi_rdata[94] = \\ ;\n assign s_axi_rdata[93] = \\ ;\n assign s_axi_rdata[92] = \\ ;\n assign s_axi_rdata[91] = \\ ;\n assign s_axi_rdata[90] = \\ ;\n assign s_axi_rdata[89] = \\ ;\n assign s_axi_rdata[88] = \\ ;\n assign s_axi_rdata[87] = \\ ;\n assign s_axi_rdata[86] = \\ ;\n assign s_axi_rdata[85] = \\ ;\n assign s_axi_rdata[84] = \\ ;\n assign s_axi_rdata[83] = \\ ;\n assign s_axi_rdata[82] = \\ ;\n assign s_axi_rdata[81] = \\ ;\n assign s_axi_rdata[80] = \\ ;\n assign s_axi_rdata[79] = \\ ;\n assign s_axi_rdata[78] = \\ ;\n assign s_axi_rdata[77] = \\ ;\n assign s_axi_rdata[76] = \\ ;\n assign s_axi_rdata[75] = \\ ;\n assign s_axi_rdata[74] = \\ ;\n assign s_axi_rdata[73] = \\ ;\n assign s_axi_rdata[72] = \\ ;\n assign s_axi_rdata[71] = \\ ;\n assign s_axi_rdata[70] = \\ ;\n assign s_axi_rdata[69] = \\ ;\n assign s_axi_rdata[68] = \\ ;\n assign s_axi_rdata[67] = \\ ;\n assign s_axi_rdata[66] = \\ ;\n assign s_axi_rdata[65] = \\ ;\n assign s_axi_rdata[64] = \\ ;\n assign s_axi_rdata[63] = \\ ;\n assign s_axi_rdata[62] = \\ ;\n assign s_axi_rdata[61] = \\ ;\n assign s_axi_rdata[60] = \\ ;\n assign s_axi_rdata[59] = \\ ;\n assign s_axi_rdata[58] = \\ ;\n assign s_axi_rdata[57] = \\ ;\n assign s_axi_rdata[56] = \\ ;\n assign s_axi_rdata[55] = \\ ;\n assign s_axi_rdata[54] = \\ ;\n assign s_axi_rdata[53] = \\ ;\n assign s_axi_rdata[52] = \\ ;\n assign s_axi_rdata[51] = \\ ;\n assign s_axi_rdata[50] = \\ ;\n assign s_axi_rdata[49] = \\ ;\n assign s_axi_rdata[48] = \\ ;\n assign s_axi_rdata[47] = \\ ;\n assign s_axi_rdata[46] = \\ ;\n assign s_axi_rdata[45] = \\ ;\n assign s_axi_rdata[44] = \\ ;\n assign s_axi_rdata[43] = \\ ;\n assign s_axi_rdata[42] = \\ ;\n assign s_axi_rdata[41] = \\ ;\n assign s_axi_rdata[40] = \\ ;\n assign s_axi_rdata[39] = \\ ;\n assign s_axi_rdata[38] = \\ ;\n assign s_axi_rdata[37] = \\ ;\n assign s_axi_rdata[36] = \\ ;\n assign s_axi_rdata[35] = \\ ;\n assign s_axi_rdata[34] = \\ ;\n assign s_axi_rdata[33] = \\ ;\n assign s_axi_rdata[32] = \\ ;\n assign s_axi_rdata[31] = \\ ;\n assign s_axi_rdata[30] = \\ ;\n assign s_axi_rdata[29] = \\ ;\n assign s_axi_rdata[28] = \\ ;\n assign s_axi_rdata[27] = \\ ;\n assign s_axi_rdata[26] = \\ ;\n assign s_axi_rdata[25] = \\ ;\n assign s_axi_rdata[24] = \\ ;\n assign s_axi_rdata[23] = \\ ;\n assign s_axi_rdata[22] = \\ ;\n assign s_axi_rdata[21] = \\ ;\n assign s_axi_rdata[20] = \\ ;\n assign s_axi_rdata[19] = \\ ;\n assign s_axi_rdata[18] = \\ ;\n assign s_axi_rdata[17] = \\ ;\n assign s_axi_rdata[16] = \\ ;\n assign s_axi_rdata[15] = \\ ;\n assign s_axi_rdata[14] = \\ ;\n assign s_axi_rdata[13] = \\ ;\n assign s_axi_rdata[12] = \\ ;\n assign s_axi_rdata[11] = \\ ;\n assign s_axi_rdata[10] = \\ ;\n assign s_axi_rdata[9] = \\ ;\n assign s_axi_rdata[8] = \\ ;\n assign s_axi_rdata[7] = \\ ;\n assign s_axi_rdata[6] = \\ ;\n assign s_axi_rdata[5] = \\ ;\n assign s_axi_rdata[4] = \\ ;\n assign s_axi_rdata[3] = \\ ;\n assign s_axi_rdata[2] = \\ ;\n assign s_axi_rdata[1] = \\ ;\n assign s_axi_rdata[0] = \\ ;\n assign s_axi_rid[3] = \\ ;\n assign s_axi_rid[2] = \\ ;\n assign s_axi_rid[1] = \\ ;\n assign s_axi_rid[0] = \\ ;\n assign s_axi_rlast = \\ ;\n assign s_axi_rresp[1] = \\ ;\n assign s_axi_rresp[0] = \\ ;\n assign s_axi_rvalid = \\ ;\n assign s_axi_sbiterr = \\ ;\n assign s_axi_wready = \\ ;\n assign sbiterr = \\ ;\n GND GND\n (.G(\\ ));\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth inst_blk_mem_gen\n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [255:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [63:0]dina;\n input [0:0]wea;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [63:0]dina;\n wire [255:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top \\gnbram.gnativebmg.native_blk_mem_gen \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/input_line_buffer_synth_1/input_line_buffer_stub.v", "content": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// --------------------------------------------------------------------------------\n// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016\n// Date : Tue Nov 15 09:41:00 2016\n// Host : david-desktop-arch running 64-bit unknown\n// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix\n// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ input_line_buffer_stub.v\n// Design : input_line_buffer\n// Purpose : Stub declaration of top-level module interface\n// Device : xc7k325tffg900-2\n// --------------------------------------------------------------------------------\n\n// This empty module with port declaration file causes synthesis tools to infer a black box for IP.\n// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.\n// Please paste the declaration into a Verilog source file or add the file as an additional source.\n(* x_core_info = \"blk_mem_gen_v8_3_4,Vivado 2016.3\" *)\nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clka, ena, wea, addra, dina, clkb, addrb, doutb)\n/* synthesis syn_black_box black_box_pad_pin=\"clka,ena,wea[0:0],addra[11:0],dina[63:0],clkb,addrb[9:0],doutb[255:0]\" */;\n input clka;\n input ena;\n input [0:0]wea;\n input [11:0]addra;\n input [63:0]dina;\n input clkb;\n input [9:0]addrb;\n output [255:0]doutb;\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/output_line_buffer_synth_1/dont_touch.xdc", "content": "# This file is automatically generated.\n# It contains project source information necessary for synthesis and implementation.\n\n# IP: /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer.xci\n# IP: The module: 'output_line_buffer' is the root of the design. Do not add the DONT_TOUCH constraint.\n\n# XDC: /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_ooc.xdc\n# XDC: The top module name and the constraint reference have the same name: 'output_line_buffer'. Do not add the DONT_TOUCH constraint.\nset_property DONT_TOUCH TRUE [get_cells U0]\n\n# IP: /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer.xci\n# IP: The module: 'output_line_buffer' is the root of the design. Do not add the DONT_TOUCH constraint.\n\n# XDC: /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_ooc.xdc\n# XDC: The top module name and the constraint reference have the same name: 'output_line_buffer'. Do not add the DONT_TOUCH constraint.\n#dup# set_property DONT_TOUCH TRUE [get_cells U0]\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/output_line_buffer_synth_1/output_line_buffer.tcl", "content": "# \n# Synthesis run script generated by Vivado\n# \n\nset_msg_config -msgmgr_mode ooc_run\ncreate_project -in_memory -part xc7k325tffg900-2\n\nset_param project.singleFileAddWarning.threshold 0\nset_param project.compositeFile.enableAutoGeneration 0\nset_param synth.vivado.isSynthRun true\nset_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info\nset_property webtalk.parent_dir /home/dave/ip/examples/framebuffer_test/framebuffer_test.cache/wt [current_project]\nset_property parent.project_path /home/dave/ip/examples/framebuffer_test/framebuffer_test.xpr [current_project]\nset_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]\nset_property default_lib xil_defaultlib [current_project]\nset_property target_language Verilog [current_project]\nset_property ip_output_repo /home/dave/ip/examples/framebuffer_test/framebuffer_test.cache/ip [current_project]\nset_property ip_cache_permissions {read write} [current_project]\nread_ip -quiet /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer.xci\nset_property is_locked true [get_files /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer.xci]\n\nforeach dcp [get_files -quiet -all *.dcp] {\n set_property used_in_implementation false $dcp\n}\nread_xdc dont_touch.xdc\nset_property used_in_implementation false [get_files dont_touch.xdc]\n\nset cached_ip [config_ip_cache -export -no_bom -use_project_ipc -dir /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/output_line_buffer_synth_1 -new_name output_line_buffer -ip [get_ips output_line_buffer]]\n\nif { $cached_ip eq {} } {\n\nsynth_design -top output_line_buffer -part xc7k325tffg900-2 -mode out_of_context\n\n#---------------------------------------------------------\n# Generate Checkpoint/Stub/Simulation Files For IP Cache\n#---------------------------------------------------------\ncatch {\n write_checkpoint -force -noxdef -rename_prefix output_line_buffer_ output_line_buffer.dcp\n\n set ipCachedFiles {}\n write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ output_line_buffer_stub.v\n lappend ipCachedFiles output_line_buffer_stub.v\n\n write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ output_line_buffer_stub.vhdl\n lappend ipCachedFiles output_line_buffer_stub.vhdl\n\n write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ output_line_buffer_sim_netlist.v\n lappend ipCachedFiles output_line_buffer_sim_netlist.v\n\n write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ output_line_buffer_sim_netlist.vhdl\n lappend ipCachedFiles output_line_buffer_sim_netlist.vhdl\n\n config_ip_cache -add -dcp output_line_buffer.dcp -move_files $ipCachedFiles -use_project_ipc -ip [get_ips output_line_buffer]\n}\n\nrename_ref -prefix_all output_line_buffer_\n\nwrite_checkpoint -force -noxdef output_line_buffer.dcp\n\ncatch { report_utilization -file output_line_buffer_utilization_synth.rpt -pb output_line_buffer_utilization_synth.pb }\n\nif { [catch {\n file copy -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/output_line_buffer_synth_1/output_line_buffer.dcp /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer.dcp\n} _RESULT ] } { \n send_msg_id runtcl-3 error \"ERROR: Unable to successfully create or copy the sub-design checkpoint file.\"\n error \"ERROR: Unable to successfully create or copy the sub-design checkpoint file.\"\n}\n\nif { [catch {\n write_verilog -force -mode synth_stub /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_stub.v\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT\"\n}\n\nif { [catch {\n write_vhdl -force -mode synth_stub /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_stub.vhdl\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT\"\n}\n\nif { [catch {\n write_verilog -force -mode funcsim /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_sim_netlist.v\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT\"\n}\n\nif { [catch {\n write_vhdl -force -mode funcsim /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_sim_netlist.vhdl\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT\"\n}\n\n\n} else {\n\n\nif { [catch {\n file copy -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/output_line_buffer_synth_1/output_line_buffer.dcp /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer.dcp\n} _RESULT ] } { \n send_msg_id runtcl-3 error \"ERROR: Unable to successfully create or copy the sub-design checkpoint file.\"\n error \"ERROR: Unable to successfully create or copy the sub-design checkpoint file.\"\n}\n\nif { [catch {\n file rename -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/output_line_buffer_synth_1/output_line_buffer_stub.v /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_stub.v\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT\"\n}\n\nif { [catch {\n file rename -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/output_line_buffer_synth_1/output_line_buffer_stub.vhdl /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_stub.vhdl\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT\"\n}\n\nif { [catch {\n file rename -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/output_line_buffer_synth_1/output_line_buffer_sim_netlist.v /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_sim_netlist.v\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT\"\n}\n\nif { [catch {\n file rename -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.runs/output_line_buffer_synth_1/output_line_buffer_sim_netlist.vhdl /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_sim_netlist.vhdl\n} _RESULT ] } { \n puts \"CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT\"\n}\n\n}; # end if cached_ip \n\nif {[file isdir /home/dave/ip/examples/framebuffer_test/framebuffer_test.ip_user_files/ip/output_line_buffer]} {\n catch { \n file copy -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_stub.v /home/dave/ip/examples/framebuffer_test/framebuffer_test.ip_user_files/ip/output_line_buffer\n }\n}\n\nif {[file isdir /home/dave/ip/examples/framebuffer_test/framebuffer_test.ip_user_files/ip/output_line_buffer]} {\n catch { \n file copy -force /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_stub.vhdl /home/dave/ip/examples/framebuffer_test/framebuffer_test.ip_user_files/ip/output_line_buffer\n }\n}\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/output_line_buffer_synth_1/output_line_buffer_sim_netlist.v", "content": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// --------------------------------------------------------------------------------\n// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016\n// Date : Tue Nov 15 09:42:00 2016\n// Host : david-desktop-arch running 64-bit unknown\n// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix\n// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ output_line_buffer_sim_netlist.v\n// Design : output_line_buffer\n// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified\n// or synthesized. This netlist cannot be used for SDF annotated simulation.\n// Device : xc7k325tffg900-2\n// --------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CHECK_LICENSE_TYPE = \"output_line_buffer,blk_mem_gen_v8_3_4,{}\" *) (* downgradeipidentifiedwarnings = \"yes\" *) (* x_core_info = \"blk_mem_gen_v8_3_4,Vivado 2016.3\" *) \n(* NotValidForBitStream *)\nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix\n (clka,\n ena,\n wea,\n addra,\n dina,\n clkb,\n addrb,\n doutb);\n (* x_interface_info = \"xilinx.com:interface:bram:1.0 BRAM_PORTA CLK\" *) input clka;\n (* x_interface_info = \"xilinx.com:interface:bram:1.0 BRAM_PORTA EN\" *) input ena;\n (* x_interface_info = \"xilinx.com:interface:bram:1.0 BRAM_PORTA WE\" *) input [0:0]wea;\n (* x_interface_info = \"xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR\" *) input [9:0]addra;\n (* x_interface_info = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DIN\" *) input [255:0]dina;\n (* x_interface_info = \"xilinx.com:interface:bram:1.0 BRAM_PORTB CLK\" *) input clkb;\n (* x_interface_info = \"xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR\" *) input [11:0]addrb;\n (* x_interface_info = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT\" *) output [63:0]doutb;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [255:0]dina;\n wire [63:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire NLW_U0_dbiterr_UNCONNECTED;\n wire NLW_U0_rsta_busy_UNCONNECTED;\n wire NLW_U0_rstb_busy_UNCONNECTED;\n wire NLW_U0_s_axi_arready_UNCONNECTED;\n wire NLW_U0_s_axi_awready_UNCONNECTED;\n wire NLW_U0_s_axi_bvalid_UNCONNECTED;\n wire NLW_U0_s_axi_dbiterr_UNCONNECTED;\n wire NLW_U0_s_axi_rlast_UNCONNECTED;\n wire NLW_U0_s_axi_rvalid_UNCONNECTED;\n wire NLW_U0_s_axi_sbiterr_UNCONNECTED;\n wire NLW_U0_s_axi_wready_UNCONNECTED;\n wire NLW_U0_sbiterr_UNCONNECTED;\n wire [255:0]NLW_U0_douta_UNCONNECTED;\n wire [11:0]NLW_U0_rdaddrecc_UNCONNECTED;\n wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;\n wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;\n wire [11:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;\n wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;\n wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;\n wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;\n\n (* C_ADDRA_WIDTH = \"10\" *) \n (* C_ADDRB_WIDTH = \"12\" *) \n (* C_ALGORITHM = \"1\" *) \n (* C_AXI_ID_WIDTH = \"4\" *) \n (* C_AXI_SLAVE_TYPE = \"0\" *) \n (* C_AXI_TYPE = \"1\" *) \n (* C_BYTE_SIZE = \"9\" *) \n (* C_COMMON_CLK = \"0\" *) \n (* C_COUNT_18K_BRAM = \"1\" *) \n (* C_COUNT_36K_BRAM = \"7\" *) \n (* C_CTRL_ECC_ALGO = \"NONE\" *) \n (* C_DEFAULT_DATA = \"0\" *) \n (* C_DISABLE_WARN_BHV_COLL = \"0\" *) \n (* C_DISABLE_WARN_BHV_RANGE = \"0\" *) \n (* C_ELABORATION_DIR = \"./\" *) \n (* C_ENABLE_32BIT_ADDRESS = \"0\" *) \n (* C_EN_DEEPSLEEP_PIN = \"0\" *) \n (* C_EN_ECC_PIPE = \"0\" *) \n (* C_EN_RDADDRA_CHG = \"0\" *) \n (* C_EN_RDADDRB_CHG = \"0\" *) \n (* C_EN_SAFETY_CKT = \"0\" *) \n (* C_EN_SHUTDOWN_PIN = \"0\" *) \n (* C_EN_SLEEP_PIN = \"0\" *) \n (* C_EST_POWER_SUMMARY = \"Estimated Power for IP : 33.580152 mW\" *) \n (* C_FAMILY = \"kintex7\" *) \n (* C_HAS_AXI_ID = \"0\" *) \n (* C_HAS_ENA = \"1\" *) \n (* C_HAS_ENB = \"0\" *) \n (* C_HAS_INJECTERR = \"0\" *) \n (* C_HAS_MEM_OUTPUT_REGS_A = \"0\" *) \n (* C_HAS_MEM_OUTPUT_REGS_B = \"0\" *) \n (* C_HAS_MUX_OUTPUT_REGS_A = \"0\" *) \n (* C_HAS_MUX_OUTPUT_REGS_B = \"0\" *) \n (* C_HAS_REGCEA = \"0\" *) \n (* C_HAS_REGCEB = \"0\" *) \n (* C_HAS_RSTA = \"0\" *) \n (* C_HAS_RSTB = \"0\" *) \n (* C_HAS_SOFTECC_INPUT_REGS_A = \"0\" *) \n (* C_HAS_SOFTECC_OUTPUT_REGS_B = \"0\" *) \n (* C_INITA_VAL = \"0\" *) \n (* C_INITB_VAL = \"0\" *) \n (* C_INIT_FILE = \"output_line_buffer.mem\" *) \n (* C_INIT_FILE_NAME = \"no_coe_file_loaded\" *) \n (* C_INTERFACE_TYPE = \"0\" *) \n (* C_LOAD_INIT_FILE = \"0\" *) \n (* C_MEM_TYPE = \"1\" *) \n (* C_MUX_PIPELINE_STAGES = \"0\" *) \n (* C_PRIM_TYPE = \"1\" *) \n (* C_READ_DEPTH_A = \"1024\" *) \n (* C_READ_DEPTH_B = \"4096\" *) \n (* C_READ_WIDTH_A = \"256\" *) \n (* C_READ_WIDTH_B = \"64\" *) \n (* C_RSTRAM_A = \"0\" *) \n (* C_RSTRAM_B = \"0\" *) \n (* C_RST_PRIORITY_A = \"CE\" *) \n (* C_RST_PRIORITY_B = \"CE\" *) \n (* C_SIM_COLLISION_CHECK = \"ALL\" *) \n (* C_USE_BRAM_BLOCK = \"0\" *) \n (* C_USE_BYTE_WEA = \"0\" *) \n (* C_USE_BYTE_WEB = \"0\" *) \n (* C_USE_DEFAULT_DATA = \"0\" *) \n (* C_USE_ECC = \"0\" *) \n (* C_USE_SOFTECC = \"0\" *) \n (* C_USE_URAM = \"0\" *) \n (* C_WEA_WIDTH = \"1\" *) \n (* C_WEB_WIDTH = \"1\" *) \n (* C_WRITE_DEPTH_A = \"1024\" *) \n (* C_WRITE_DEPTH_B = \"4096\" *) \n (* C_WRITE_MODE_A = \"NO_CHANGE\" *) \n (* C_WRITE_MODE_B = \"WRITE_FIRST\" *) \n (* C_WRITE_WIDTH_A = \"256\" *) \n (* C_WRITE_WIDTH_B = \"64\" *) \n (* C_XDEVICEFAMILY = \"kintex7\" *) \n (* downgradeipidentifiedwarnings = \"yes\" *) \n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 U0\n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dbiterr(NLW_U0_dbiterr_UNCONNECTED),\n .deepsleep(1'b0),\n .dina(dina),\n .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .douta(NLW_U0_douta_UNCONNECTED[255:0]),\n .doutb(doutb),\n .eccpipece(1'b0),\n .ena(ena),\n .enb(1'b0),\n .injectdbiterr(1'b0),\n .injectsbiterr(1'b0),\n .rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[11:0]),\n .regcea(1'b0),\n .regceb(1'b0),\n .rsta(1'b0),\n .rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),\n .rstb(1'b0),\n .rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),\n .s_aclk(1'b0),\n .s_aresetn(1'b0),\n .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axi_arburst({1'b0,1'b0}),\n .s_axi_arid({1'b0,1'b0,1'b0,1'b0}),\n .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),\n .s_axi_arsize({1'b0,1'b0,1'b0}),\n .s_axi_arvalid(1'b0),\n .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axi_awburst({1'b0,1'b0}),\n .s_axi_awid({1'b0,1'b0,1'b0,1'b0}),\n .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),\n .s_axi_awsize({1'b0,1'b0,1'b0}),\n .s_axi_awvalid(1'b0),\n .s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),\n .s_axi_bready(1'b0),\n .s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),\n .s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),\n .s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),\n .s_axi_injectdbiterr(1'b0),\n .s_axi_injectsbiterr(1'b0),\n .s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[11:0]),\n .s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),\n .s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),\n .s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),\n .s_axi_rready(1'b0),\n .s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),\n .s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),\n .s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),\n .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axi_wlast(1'b0),\n .s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),\n .s_axi_wstrb(1'b0),\n .s_axi_wvalid(1'b0),\n .sbiterr(NLW_U0_sbiterr_UNCONNECTED),\n .shutdown(1'b0),\n .sleep(1'b0),\n .wea(wea),\n .web(1'b0));\nendmodule\n\nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [63:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [255:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [255:0]dina;\n wire [63:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width \\ramloop[0].ram.r \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina({dina[195:192],dina[131:128],dina[67:64],dina[3:0]}),\n .doutb(doutb[3:0]),\n .ena(ena),\n .wea(wea));\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0 \\ramloop[1].ram.r \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina({dina[204:196],dina[140:132],dina[76:68],dina[12:4]}),\n .doutb(doutb[12:4]),\n .ena(ena),\n .wea(wea));\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1 \\ramloop[2].ram.r \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina({dina[213:205],dina[149:141],dina[85:77],dina[21:13]}),\n .doutb(doutb[21:13]),\n .ena(ena),\n .wea(wea));\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2 \\ramloop[3].ram.r \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina({dina[222:214],dina[158:150],dina[94:86],dina[30:22]}),\n .doutb(doutb[30:22]),\n .ena(ena),\n .wea(wea));\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3 \\ramloop[4].ram.r \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina({dina[231:223],dina[167:159],dina[103:95],dina[39:31]}),\n .doutb(doutb[39:31]),\n .ena(ena),\n .wea(wea));\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4 \\ramloop[5].ram.r \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina({dina[240:232],dina[176:168],dina[112:104],dina[48:40]}),\n .doutb(doutb[48:40]),\n .ena(ena),\n .wea(wea));\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5 \\ramloop[6].ram.r \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina({dina[249:241],dina[185:177],dina[121:113],dina[57:49]}),\n .doutb(doutb[57:49]),\n .ena(ena),\n .wea(wea));\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6 \\ramloop[7].ram.r \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina({dina[255:250],dina[191:186],dina[127:122],dina[63:58]}),\n .doutb(doutb[63:58]),\n .ena(ena),\n .wea(wea));\nendmodule\n\nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [3:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [15:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [15:0]dina;\n wire [3:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper \\prim_noinit.ram \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [8:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [35:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [35:0]dina;\n wire [8:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0 \\prim_noinit.ram \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [8:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [35:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [35:0]dina;\n wire [8:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1 \\prim_noinit.ram \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [8:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [35:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [35:0]dina;\n wire [8:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2 \\prim_noinit.ram \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [8:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [35:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [35:0]dina;\n wire [8:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3 \\prim_noinit.ram \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [8:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [35:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [35:0]dina;\n wire [8:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4 \\prim_noinit.ram \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [8:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [35:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [35:0]dina;\n wire [8:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5 \\prim_noinit.ram \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [5:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [23:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [23:0]dina;\n wire [5:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6 \\prim_noinit.ram \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [3:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [15:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [15:0]dina;\n wire [3:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire [15:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ;\n wire [15:4]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;\n wire [1:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ;\n wire [1:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB18E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(18'h00000),\n .INIT_B(18'h00000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_MODE(\"TDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(4),\n .READ_WIDTH_B(4),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(18'h00000),\n .SRVAL_B(18'h00000),\n .WRITE_MODE_A(\"NO_CHANGE\"),\n .WRITE_MODE_B(\"NO_CHANGE\"),\n .WRITE_WIDTH_A(18),\n .WRITE_WIDTH_B(18)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram \n (.ADDRARDADDR({addra,1'b0,1'b0,1'b0,1'b0}),\n .ADDRBWRADDR({addrb,1'b0,1'b0}),\n .CLKARDCLK(clka),\n .CLKBWRCLK(clkb),\n .DIADI(dina),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIPADIP({1'b0,1'b0}),\n .DIPBDIP({1'b0,1'b0}),\n .DOADO(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:0]),\n .DOBDO({\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:4],doutb}),\n .DOPADOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]),\n .DOPBDOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]),\n .ENARDEN(ena),\n .ENBWREN(1'b1),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(1'b0),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .WEA({wea,wea}),\n .WEBWE({1'b0,1'b0,1'b0,1'b0}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [8:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [35:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [35:0]dina;\n wire [8:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;\n wire [31:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;\n wire [31:8]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;\n wire [3:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;\n wire [3:1]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;\n wire [7:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;\n wire [8:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB36E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .EN_ECC_READ(\"FALSE\"),\n .EN_ECC_WRITE(\"FALSE\"),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(36'h000000000),\n .INIT_B(36'h000000000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_EXTENSION_A(\"NONE\"),\n .RAM_EXTENSION_B(\"NONE\"),\n .RAM_MODE(\"TDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(9),\n .READ_WIDTH_B(9),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(36'h000000000),\n .SRVAL_B(36'h000000000),\n .WRITE_MODE_A(\"NO_CHANGE\"),\n .WRITE_MODE_B(\"NO_CHANGE\"),\n .WRITE_WIDTH_A(36),\n .WRITE_WIDTH_B(36)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram \n (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}),\n .CASCADEINA(1'b0),\n .CASCADEINB(1'b0),\n .CASCADEOUTA(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),\n .CASCADEOUTB(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),\n .CLKARDCLK(clka),\n .CLKBWRCLK(clkb),\n .DBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),\n .DIADI({dina[34:27],dina[25:18],dina[16:9],dina[7:0]}),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIPADIP({dina[35],dina[26],dina[17],dina[8]}),\n .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),\n .DOADO(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),\n .DOBDO({\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb[7:0]}),\n .DOPADOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),\n .DOPBDOP({\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb[8]}),\n .ECCPARITY(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),\n .ENARDEN(ena),\n .ENBWREN(1'b1),\n .INJECTDBITERR(1'b0),\n .INJECTSBITERR(1'b0),\n .RDADDRECC(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(1'b0),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .SBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),\n .WEA({wea,wea,wea,wea}),\n .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [8:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [35:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [35:0]dina;\n wire [8:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;\n wire [31:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;\n wire [31:8]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;\n wire [3:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;\n wire [3:1]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;\n wire [7:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;\n wire [8:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB36E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .EN_ECC_READ(\"FALSE\"),\n .EN_ECC_WRITE(\"FALSE\"),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(36'h000000000),\n .INIT_B(36'h000000000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_EXTENSION_A(\"NONE\"),\n .RAM_EXTENSION_B(\"NONE\"),\n .RAM_MODE(\"TDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(9),\n .READ_WIDTH_B(9),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(36'h000000000),\n .SRVAL_B(36'h000000000),\n .WRITE_MODE_A(\"NO_CHANGE\"),\n .WRITE_MODE_B(\"NO_CHANGE\"),\n .WRITE_WIDTH_A(36),\n .WRITE_WIDTH_B(36)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram \n (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}),\n .CASCADEINA(1'b0),\n .CASCADEINB(1'b0),\n .CASCADEOUTA(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),\n .CASCADEOUTB(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),\n .CLKARDCLK(clka),\n .CLKBWRCLK(clkb),\n .DBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),\n .DIADI({dina[34:27],dina[25:18],dina[16:9],dina[7:0]}),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIPADIP({dina[35],dina[26],dina[17],dina[8]}),\n .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),\n .DOADO(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),\n .DOBDO({\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb[7:0]}),\n .DOPADOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),\n .DOPBDOP({\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb[8]}),\n .ECCPARITY(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),\n .ENARDEN(ena),\n .ENBWREN(1'b1),\n .INJECTDBITERR(1'b0),\n .INJECTSBITERR(1'b0),\n .RDADDRECC(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(1'b0),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .SBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),\n .WEA({wea,wea,wea,wea}),\n .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [8:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [35:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [35:0]dina;\n wire [8:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;\n wire [31:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;\n wire [31:8]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;\n wire [3:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;\n wire [3:1]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;\n wire [7:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;\n wire [8:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB36E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .EN_ECC_READ(\"FALSE\"),\n .EN_ECC_WRITE(\"FALSE\"),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(36'h000000000),\n .INIT_B(36'h000000000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_EXTENSION_A(\"NONE\"),\n .RAM_EXTENSION_B(\"NONE\"),\n .RAM_MODE(\"TDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(9),\n .READ_WIDTH_B(9),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(36'h000000000),\n .SRVAL_B(36'h000000000),\n .WRITE_MODE_A(\"NO_CHANGE\"),\n .WRITE_MODE_B(\"NO_CHANGE\"),\n .WRITE_WIDTH_A(36),\n .WRITE_WIDTH_B(36)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram \n (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}),\n .CASCADEINA(1'b0),\n .CASCADEINB(1'b0),\n .CASCADEOUTA(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),\n .CASCADEOUTB(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),\n .CLKARDCLK(clka),\n .CLKBWRCLK(clkb),\n .DBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),\n .DIADI({dina[34:27],dina[25:18],dina[16:9],dina[7:0]}),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIPADIP({dina[35],dina[26],dina[17],dina[8]}),\n .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),\n .DOADO(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),\n .DOBDO({\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb[7:0]}),\n .DOPADOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),\n .DOPBDOP({\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb[8]}),\n .ECCPARITY(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),\n .ENARDEN(ena),\n .ENBWREN(1'b1),\n .INJECTDBITERR(1'b0),\n .INJECTSBITERR(1'b0),\n .RDADDRECC(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(1'b0),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .SBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),\n .WEA({wea,wea,wea,wea}),\n .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [8:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [35:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [35:0]dina;\n wire [8:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;\n wire [31:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;\n wire [31:8]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;\n wire [3:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;\n wire [3:1]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;\n wire [7:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;\n wire [8:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB36E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .EN_ECC_READ(\"FALSE\"),\n .EN_ECC_WRITE(\"FALSE\"),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(36'h000000000),\n .INIT_B(36'h000000000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_EXTENSION_A(\"NONE\"),\n .RAM_EXTENSION_B(\"NONE\"),\n .RAM_MODE(\"TDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(9),\n .READ_WIDTH_B(9),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(36'h000000000),\n .SRVAL_B(36'h000000000),\n .WRITE_MODE_A(\"NO_CHANGE\"),\n .WRITE_MODE_B(\"NO_CHANGE\"),\n .WRITE_WIDTH_A(36),\n .WRITE_WIDTH_B(36)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram \n (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}),\n .CASCADEINA(1'b0),\n .CASCADEINB(1'b0),\n .CASCADEOUTA(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),\n .CASCADEOUTB(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),\n .CLKARDCLK(clka),\n .CLKBWRCLK(clkb),\n .DBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),\n .DIADI({dina[34:27],dina[25:18],dina[16:9],dina[7:0]}),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIPADIP({dina[35],dina[26],dina[17],dina[8]}),\n .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),\n .DOADO(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),\n .DOBDO({\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb[7:0]}),\n .DOPADOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),\n .DOPBDOP({\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb[8]}),\n .ECCPARITY(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),\n .ENARDEN(ena),\n .ENBWREN(1'b1),\n .INJECTDBITERR(1'b0),\n .INJECTSBITERR(1'b0),\n .RDADDRECC(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(1'b0),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .SBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),\n .WEA({wea,wea,wea,wea}),\n .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [8:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [35:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [35:0]dina;\n wire [8:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;\n wire [31:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;\n wire [31:8]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;\n wire [3:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;\n wire [3:1]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;\n wire [7:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;\n wire [8:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB36E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .EN_ECC_READ(\"FALSE\"),\n .EN_ECC_WRITE(\"FALSE\"),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(36'h000000000),\n .INIT_B(36'h000000000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_EXTENSION_A(\"NONE\"),\n .RAM_EXTENSION_B(\"NONE\"),\n .RAM_MODE(\"TDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(9),\n .READ_WIDTH_B(9),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(36'h000000000),\n .SRVAL_B(36'h000000000),\n .WRITE_MODE_A(\"NO_CHANGE\"),\n .WRITE_MODE_B(\"NO_CHANGE\"),\n .WRITE_WIDTH_A(36),\n .WRITE_WIDTH_B(36)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram \n (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}),\n .CASCADEINA(1'b0),\n .CASCADEINB(1'b0),\n .CASCADEOUTA(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),\n .CASCADEOUTB(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),\n .CLKARDCLK(clka),\n .CLKBWRCLK(clkb),\n .DBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),\n .DIADI({dina[34:27],dina[25:18],dina[16:9],dina[7:0]}),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIPADIP({dina[35],dina[26],dina[17],dina[8]}),\n .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),\n .DOADO(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),\n .DOBDO({\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb[7:0]}),\n .DOPADOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),\n .DOPBDOP({\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb[8]}),\n .ECCPARITY(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),\n .ENARDEN(ena),\n .ENBWREN(1'b1),\n .INJECTDBITERR(1'b0),\n .INJECTSBITERR(1'b0),\n .RDADDRECC(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(1'b0),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .SBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),\n .WEA({wea,wea,wea,wea}),\n .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [8:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [35:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [35:0]dina;\n wire [8:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;\n wire [31:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;\n wire [31:8]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;\n wire [3:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;\n wire [3:1]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;\n wire [7:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;\n wire [8:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB36E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .EN_ECC_READ(\"FALSE\"),\n .EN_ECC_WRITE(\"FALSE\"),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(36'h000000000),\n .INIT_B(36'h000000000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_EXTENSION_A(\"NONE\"),\n .RAM_EXTENSION_B(\"NONE\"),\n .RAM_MODE(\"TDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(9),\n .READ_WIDTH_B(9),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(36'h000000000),\n .SRVAL_B(36'h000000000),\n .WRITE_MODE_A(\"NO_CHANGE\"),\n .WRITE_MODE_B(\"NO_CHANGE\"),\n .WRITE_WIDTH_A(36),\n .WRITE_WIDTH_B(36)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram \n (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}),\n .CASCADEINA(1'b0),\n .CASCADEINB(1'b0),\n .CASCADEOUTA(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),\n .CASCADEOUTB(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),\n .CLKARDCLK(clka),\n .CLKBWRCLK(clkb),\n .DBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),\n .DIADI({dina[34:27],dina[25:18],dina[16:9],dina[7:0]}),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIPADIP({dina[35],dina[26],dina[17],dina[8]}),\n .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),\n .DOADO(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),\n .DOBDO({\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb[7:0]}),\n .DOPADOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),\n .DOPBDOP({\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb[8]}),\n .ECCPARITY(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),\n .ENARDEN(ena),\n .ENBWREN(1'b1),\n .INJECTDBITERR(1'b0),\n .INJECTSBITERR(1'b0),\n .RDADDRECC(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(1'b0),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .SBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),\n .WEA({wea,wea,wea,wea}),\n .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [5:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [23:0]dina;\n input [0:0]wea;\n\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ;\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [23:0]dina;\n wire [5:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;\n wire [31:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;\n wire [31:8]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;\n wire [3:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;\n wire [3:1]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;\n wire [7:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;\n wire [8:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB36E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .EN_ECC_READ(\"FALSE\"),\n .EN_ECC_WRITE(\"FALSE\"),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(36'h000000000),\n .INIT_B(36'h000000000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_EXTENSION_A(\"NONE\"),\n .RAM_EXTENSION_B(\"NONE\"),\n .RAM_MODE(\"TDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(9),\n .READ_WIDTH_B(9),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(36'h000000000),\n .SRVAL_B(36'h000000000),\n .WRITE_MODE_A(\"NO_CHANGE\"),\n .WRITE_MODE_B(\"NO_CHANGE\"),\n .WRITE_WIDTH_A(36),\n .WRITE_WIDTH_B(36)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram \n (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}),\n .CASCADEINA(1'b0),\n .CASCADEINB(1'b0),\n .CASCADEOUTA(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),\n .CASCADEOUTB(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),\n .CLKARDCLK(clka),\n .CLKBWRCLK(clkb),\n .DBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),\n .DIADI({1'b0,1'b0,dina[23:18],1'b0,1'b0,dina[17:12],1'b0,1'b0,dina[11:6],1'b0,1'b0,dina[5:0]}),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIPADIP({1'b0,1'b0,1'b0,1'b0}),\n .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),\n .DOADO(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),\n .DOBDO({\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78 ,doutb}),\n .DOPADOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),\n .DOPBDOP({\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }),\n .ECCPARITY(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),\n .ENARDEN(ena),\n .ENBWREN(1'b1),\n .INJECTDBITERR(1'b0),\n .INJECTSBITERR(1'b0),\n .RDADDRECC(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(1'b0),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .SBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),\n .WEA({wea,wea,wea,wea}),\n .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));\nendmodule\n\nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [63:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [255:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [255:0]dina;\n wire [63:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr \\valid.cstr \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* C_ADDRA_WIDTH = \"10\" *) (* C_ADDRB_WIDTH = \"12\" *) (* C_ALGORITHM = \"1\" *) \n(* C_AXI_ID_WIDTH = \"4\" *) (* C_AXI_SLAVE_TYPE = \"0\" *) (* C_AXI_TYPE = \"1\" *) \n(* C_BYTE_SIZE = \"9\" *) (* C_COMMON_CLK = \"0\" *) (* C_COUNT_18K_BRAM = \"1\" *) \n(* C_COUNT_36K_BRAM = \"7\" *) (* C_CTRL_ECC_ALGO = \"NONE\" *) (* C_DEFAULT_DATA = \"0\" *) \n(* C_DISABLE_WARN_BHV_COLL = \"0\" *) (* C_DISABLE_WARN_BHV_RANGE = \"0\" *) (* C_ELABORATION_DIR = \"./\" *) \n(* C_ENABLE_32BIT_ADDRESS = \"0\" *) (* C_EN_DEEPSLEEP_PIN = \"0\" *) (* C_EN_ECC_PIPE = \"0\" *) \n(* C_EN_RDADDRA_CHG = \"0\" *) (* C_EN_RDADDRB_CHG = \"0\" *) (* C_EN_SAFETY_CKT = \"0\" *) \n(* C_EN_SHUTDOWN_PIN = \"0\" *) (* C_EN_SLEEP_PIN = \"0\" *) (* C_EST_POWER_SUMMARY = \"Estimated Power for IP : 33.580152 mW\" *) \n(* C_FAMILY = \"kintex7\" *) (* C_HAS_AXI_ID = \"0\" *) (* C_HAS_ENA = \"1\" *) \n(* C_HAS_ENB = \"0\" *) (* C_HAS_INJECTERR = \"0\" *) (* C_HAS_MEM_OUTPUT_REGS_A = \"0\" *) \n(* C_HAS_MEM_OUTPUT_REGS_B = \"0\" *) (* C_HAS_MUX_OUTPUT_REGS_A = \"0\" *) (* C_HAS_MUX_OUTPUT_REGS_B = \"0\" *) \n(* C_HAS_REGCEA = \"0\" *) (* C_HAS_REGCEB = \"0\" *) (* C_HAS_RSTA = \"0\" *) \n(* C_HAS_RSTB = \"0\" *) (* C_HAS_SOFTECC_INPUT_REGS_A = \"0\" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = \"0\" *) \n(* C_INITA_VAL = \"0\" *) (* C_INITB_VAL = \"0\" *) (* C_INIT_FILE = \"output_line_buffer.mem\" *) \n(* C_INIT_FILE_NAME = \"no_coe_file_loaded\" *) (* C_INTERFACE_TYPE = \"0\" *) (* C_LOAD_INIT_FILE = \"0\" *) \n(* C_MEM_TYPE = \"1\" *) (* C_MUX_PIPELINE_STAGES = \"0\" *) (* C_PRIM_TYPE = \"1\" *) \n(* C_READ_DEPTH_A = \"1024\" *) (* C_READ_DEPTH_B = \"4096\" *) (* C_READ_WIDTH_A = \"256\" *) \n(* C_READ_WIDTH_B = \"64\" *) (* C_RSTRAM_A = \"0\" *) (* C_RSTRAM_B = \"0\" *) \n(* C_RST_PRIORITY_A = \"CE\" *) (* C_RST_PRIORITY_B = \"CE\" *) (* C_SIM_COLLISION_CHECK = \"ALL\" *) \n(* C_USE_BRAM_BLOCK = \"0\" *) (* C_USE_BYTE_WEA = \"0\" *) (* C_USE_BYTE_WEB = \"0\" *) \n(* C_USE_DEFAULT_DATA = \"0\" *) (* C_USE_ECC = \"0\" *) (* C_USE_SOFTECC = \"0\" *) \n(* C_USE_URAM = \"0\" *) (* C_WEA_WIDTH = \"1\" *) (* C_WEB_WIDTH = \"1\" *) \n(* C_WRITE_DEPTH_A = \"1024\" *) (* C_WRITE_DEPTH_B = \"4096\" *) (* C_WRITE_MODE_A = \"NO_CHANGE\" *) \n(* C_WRITE_MODE_B = \"WRITE_FIRST\" *) (* C_WRITE_WIDTH_A = \"256\" *) (* C_WRITE_WIDTH_B = \"64\" *) \n(* C_XDEVICEFAMILY = \"kintex7\" *) (* downgradeipidentifiedwarnings = \"yes\" *) \nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4\n (clka,\n rsta,\n ena,\n regcea,\n wea,\n addra,\n dina,\n douta,\n clkb,\n rstb,\n enb,\n regceb,\n web,\n addrb,\n dinb,\n doutb,\n injectsbiterr,\n injectdbiterr,\n eccpipece,\n sbiterr,\n dbiterr,\n rdaddrecc,\n sleep,\n deepsleep,\n shutdown,\n rsta_busy,\n rstb_busy,\n s_aclk,\n s_aresetn,\n s_axi_awid,\n s_axi_awaddr,\n s_axi_awlen,\n s_axi_awsize,\n s_axi_awburst,\n s_axi_awvalid,\n s_axi_awready,\n s_axi_wdata,\n s_axi_wstrb,\n s_axi_wlast,\n s_axi_wvalid,\n s_axi_wready,\n s_axi_bid,\n s_axi_bresp,\n s_axi_bvalid,\n s_axi_bready,\n s_axi_arid,\n s_axi_araddr,\n s_axi_arlen,\n s_axi_arsize,\n s_axi_arburst,\n s_axi_arvalid,\n s_axi_arready,\n s_axi_rid,\n s_axi_rdata,\n s_axi_rresp,\n s_axi_rlast,\n s_axi_rvalid,\n s_axi_rready,\n s_axi_injectsbiterr,\n s_axi_injectdbiterr,\n s_axi_sbiterr,\n s_axi_dbiterr,\n s_axi_rdaddrecc);\n input clka;\n input rsta;\n input ena;\n input regcea;\n input [0:0]wea;\n input [9:0]addra;\n input [255:0]dina;\n output [255:0]douta;\n input clkb;\n input rstb;\n input enb;\n input regceb;\n input [0:0]web;\n input [11:0]addrb;\n input [63:0]dinb;\n output [63:0]doutb;\n input injectsbiterr;\n input injectdbiterr;\n input eccpipece;\n output sbiterr;\n output dbiterr;\n output [11:0]rdaddrecc;\n input sleep;\n input deepsleep;\n input shutdown;\n output rsta_busy;\n output rstb_busy;\n input s_aclk;\n input s_aresetn;\n input [3:0]s_axi_awid;\n input [31:0]s_axi_awaddr;\n input [7:0]s_axi_awlen;\n input [2:0]s_axi_awsize;\n input [1:0]s_axi_awburst;\n input s_axi_awvalid;\n output s_axi_awready;\n input [255:0]s_axi_wdata;\n input [0:0]s_axi_wstrb;\n input s_axi_wlast;\n input s_axi_wvalid;\n output s_axi_wready;\n output [3:0]s_axi_bid;\n output [1:0]s_axi_bresp;\n output s_axi_bvalid;\n input s_axi_bready;\n input [3:0]s_axi_arid;\n input [31:0]s_axi_araddr;\n input [7:0]s_axi_arlen;\n input [2:0]s_axi_arsize;\n input [1:0]s_axi_arburst;\n input s_axi_arvalid;\n output s_axi_arready;\n output [3:0]s_axi_rid;\n output [63:0]s_axi_rdata;\n output [1:0]s_axi_rresp;\n output s_axi_rlast;\n output s_axi_rvalid;\n input s_axi_rready;\n input s_axi_injectsbiterr;\n input s_axi_injectdbiterr;\n output s_axi_sbiterr;\n output s_axi_dbiterr;\n output [11:0]s_axi_rdaddrecc;\n\n wire \\ ;\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [255:0]dina;\n wire [63:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n assign dbiterr = \\ ;\n assign douta[255] = \\ ;\n assign douta[254] = \\ ;\n assign douta[253] = \\ ;\n assign douta[252] = \\ ;\n assign douta[251] = \\ ;\n assign douta[250] = \\ ;\n assign douta[249] = \\ ;\n assign douta[248] = \\ ;\n assign douta[247] = \\ ;\n assign douta[246] = \\ ;\n assign douta[245] = \\ ;\n assign douta[244] = \\ ;\n assign douta[243] = \\ ;\n assign douta[242] = \\ ;\n assign douta[241] = \\ ;\n assign douta[240] = \\ ;\n assign douta[239] = \\ ;\n assign douta[238] = \\ ;\n assign douta[237] = \\ ;\n assign douta[236] = \\ ;\n assign douta[235] = \\ ;\n assign douta[234] = \\ ;\n assign douta[233] = \\ ;\n assign douta[232] = \\ ;\n assign douta[231] = \\ ;\n assign douta[230] = \\ ;\n assign douta[229] = \\ ;\n assign douta[228] = \\ ;\n assign douta[227] = \\ ;\n assign douta[226] = \\ ;\n assign douta[225] = \\ ;\n assign douta[224] = \\ ;\n assign douta[223] = \\ ;\n assign douta[222] = \\ ;\n assign douta[221] = \\ ;\n assign douta[220] = \\ ;\n assign douta[219] = \\ ;\n assign douta[218] = \\ ;\n assign douta[217] = \\ ;\n assign douta[216] = \\ ;\n assign douta[215] = \\ ;\n assign douta[214] = \\ ;\n assign douta[213] = \\ ;\n assign douta[212] = \\ ;\n assign douta[211] = \\ ;\n assign douta[210] = \\ ;\n assign douta[209] = \\ ;\n assign douta[208] = \\ ;\n assign douta[207] = \\ ;\n assign douta[206] = \\ ;\n assign douta[205] = \\ ;\n assign douta[204] = \\ ;\n assign douta[203] = \\ ;\n assign douta[202] = \\ ;\n assign douta[201] = \\ ;\n assign douta[200] = \\ ;\n assign douta[199] = \\ ;\n assign douta[198] = \\ ;\n assign douta[197] = \\ ;\n assign douta[196] = \\ ;\n assign douta[195] = \\ ;\n assign douta[194] = \\ ;\n assign douta[193] = \\ ;\n assign douta[192] = \\ ;\n assign douta[191] = \\ ;\n assign douta[190] = \\ ;\n assign douta[189] = \\ ;\n assign douta[188] = \\ ;\n assign douta[187] = \\ ;\n assign douta[186] = \\ ;\n assign douta[185] = \\ ;\n assign douta[184] = \\ ;\n assign douta[183] = \\ ;\n assign douta[182] = \\ ;\n assign douta[181] = \\ ;\n assign douta[180] = \\ ;\n assign douta[179] = \\ ;\n assign douta[178] = \\ ;\n assign douta[177] = \\ ;\n assign douta[176] = \\ ;\n assign douta[175] = \\ ;\n assign douta[174] = \\ ;\n assign douta[173] = \\ ;\n assign douta[172] = \\ ;\n assign douta[171] = \\ ;\n assign douta[170] = \\ ;\n assign douta[169] = \\ ;\n assign douta[168] = \\ ;\n assign douta[167] = \\ ;\n assign douta[166] = \\ ;\n assign douta[165] = \\ ;\n assign douta[164] = \\ ;\n assign douta[163] = \\ ;\n assign douta[162] = \\ ;\n assign douta[161] = \\ ;\n assign douta[160] = \\ ;\n assign douta[159] = \\ ;\n assign douta[158] = \\ ;\n assign douta[157] = \\ ;\n assign douta[156] = \\ ;\n assign douta[155] = \\ ;\n assign douta[154] = \\ ;\n assign douta[153] = \\ ;\n assign douta[152] = \\ ;\n assign douta[151] = \\ ;\n assign douta[150] = \\ ;\n assign douta[149] = \\ ;\n assign douta[148] = \\ ;\n assign douta[147] = \\ ;\n assign douta[146] = \\ ;\n assign douta[145] = \\ ;\n assign douta[144] = \\ ;\n assign douta[143] = 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\\ ;\n assign douta[105] = \\ ;\n assign douta[104] = \\ ;\n assign douta[103] = \\ ;\n assign douta[102] = \\ ;\n assign douta[101] = \\ ;\n assign douta[100] = \\ ;\n assign douta[99] = \\ ;\n assign douta[98] = \\ ;\n assign douta[97] = \\ ;\n assign douta[96] = \\ ;\n assign douta[95] = \\ ;\n assign douta[94] = \\ ;\n assign douta[93] = \\ ;\n assign douta[92] = \\ ;\n assign douta[91] = \\ ;\n assign douta[90] = \\ ;\n assign douta[89] = \\ ;\n assign douta[88] = \\ ;\n assign douta[87] = \\ ;\n assign douta[86] = \\ ;\n assign douta[85] = \\ ;\n assign douta[84] = \\ ;\n assign douta[83] = \\ ;\n assign douta[82] = \\ ;\n assign douta[81] = \\ ;\n assign douta[80] = \\ ;\n assign douta[79] = \\ ;\n assign douta[78] = \\ ;\n assign douta[77] = \\ ;\n assign douta[76] = \\ ;\n assign douta[75] = \\ ;\n assign douta[74] = \\ ;\n assign douta[73] = \\ ;\n assign douta[72] = \\ ;\n assign douta[71] = \\ ;\n assign douta[70] = \\ ;\n assign douta[69] = \\ ;\n assign douta[68] = \\ ;\n assign douta[67] = \\ ;\n assign douta[66] = \\ ;\n assign douta[65] = \\ ;\n assign douta[64] = \\ ;\n assign douta[63] = \\ ;\n assign douta[62] = \\ ;\n assign douta[61] = \\ ;\n assign douta[60] = \\ ;\n assign douta[59] = \\ ;\n assign douta[58] = \\ ;\n assign douta[57] = \\ ;\n assign douta[56] = \\ ;\n assign douta[55] = \\ ;\n assign douta[54] = \\ ;\n assign douta[53] = \\ ;\n assign douta[52] = \\ ;\n assign douta[51] = \\ ;\n assign douta[50] = \\ ;\n assign douta[49] = \\ ;\n assign douta[48] = \\ ;\n assign douta[47] = \\ ;\n assign douta[46] = \\ ;\n assign douta[45] = \\ ;\n assign douta[44] = \\ ;\n assign douta[43] = \\ ;\n assign douta[42] = \\ ;\n assign douta[41] = \\ ;\n assign douta[40] = \\ ;\n assign douta[39] = \\ ;\n assign douta[38] = \\ ;\n assign douta[37] = \\ ;\n assign douta[36] = \\ ;\n assign douta[35] = \\ ;\n assign douta[34] = \\ ;\n assign douta[33] = \\ ;\n assign douta[32] = \\ ;\n assign douta[31] = \\ ;\n assign douta[30] = \\ ;\n assign douta[29] = \\ ;\n assign douta[28] = \\ ;\n assign douta[27] = \\ ;\n assign douta[26] = \\ ;\n assign douta[25] = \\ ;\n assign douta[24] = \\ ;\n assign douta[23] = \\ ;\n assign douta[22] = \\ ;\n assign douta[21] = \\ ;\n assign douta[20] = \\ ;\n assign douta[19] = \\ ;\n assign douta[18] = \\ ;\n assign douta[17] = \\ ;\n assign douta[16] = \\ ;\n assign douta[15] = \\ ;\n assign douta[14] = \\ ;\n assign douta[13] = \\ ;\n assign douta[12] = \\ ;\n assign douta[11] = \\ ;\n assign douta[10] = \\ ;\n assign douta[9] = \\ ;\n assign douta[8] = \\ ;\n assign douta[7] = \\ ;\n assign douta[6] = \\ ;\n assign douta[5] = \\ ;\n assign douta[4] = \\ ;\n assign douta[3] = \\ ;\n assign douta[2] = \\ ;\n assign douta[1] = \\ ;\n assign douta[0] = \\ ;\n assign rdaddrecc[11] = \\ ;\n assign rdaddrecc[10] = \\ ;\n assign rdaddrecc[9] = \\ ;\n assign rdaddrecc[8] = \\ ;\n assign rdaddrecc[7] = \\ ;\n assign rdaddrecc[6] = \\ ;\n assign rdaddrecc[5] = \\ ;\n assign rdaddrecc[4] = \\ ;\n assign rdaddrecc[3] = \\ ;\n assign rdaddrecc[2] = \\ ;\n assign rdaddrecc[1] = \\ ;\n assign rdaddrecc[0] = \\ ;\n assign rsta_busy = \\ ;\n assign rstb_busy = \\ ;\n assign s_axi_arready = \\ ;\n assign s_axi_awready = \\ ;\n assign s_axi_bid[3] = \\ ;\n assign s_axi_bid[2] = \\ ;\n assign s_axi_bid[1] = \\ ;\n assign s_axi_bid[0] = \\ ;\n assign s_axi_bresp[1] = \\ ;\n assign s_axi_bresp[0] = \\ ;\n assign s_axi_bvalid = \\ ;\n assign s_axi_dbiterr = \\ ;\n assign s_axi_rdaddrecc[11] = \\ ;\n assign s_axi_rdaddrecc[10] = \\ ;\n assign s_axi_rdaddrecc[9] = \\ ;\n assign s_axi_rdaddrecc[8] = \\ ;\n assign s_axi_rdaddrecc[7] = \\ ;\n assign s_axi_rdaddrecc[6] = \\ ;\n assign s_axi_rdaddrecc[5] = \\ ;\n assign s_axi_rdaddrecc[4] = \\ ;\n assign s_axi_rdaddrecc[3] = \\ ;\n assign s_axi_rdaddrecc[2] = \\ ;\n assign s_axi_rdaddrecc[1] = \\ ;\n assign s_axi_rdaddrecc[0] = \\ ;\n assign s_axi_rdata[63] = \\ ;\n assign s_axi_rdata[62] = \\ ;\n assign s_axi_rdata[61] = \\ ;\n assign s_axi_rdata[60] = \\ ;\n assign s_axi_rdata[59] = \\ ;\n assign s_axi_rdata[58] = \\ ;\n assign s_axi_rdata[57] = \\ ;\n assign s_axi_rdata[56] = \\ ;\n assign s_axi_rdata[55] = \\ ;\n assign s_axi_rdata[54] = \\ ;\n assign s_axi_rdata[53] = \\ ;\n assign s_axi_rdata[52] = \\ ;\n assign s_axi_rdata[51] = \\ ;\n assign s_axi_rdata[50] = \\ ;\n assign s_axi_rdata[49] = \\ ;\n assign s_axi_rdata[48] = \\ ;\n assign s_axi_rdata[47] = \\ ;\n assign s_axi_rdata[46] = \\ ;\n assign s_axi_rdata[45] = \\ ;\n assign s_axi_rdata[44] = \\ ;\n assign s_axi_rdata[43] = \\ ;\n assign s_axi_rdata[42] = \\ ;\n assign s_axi_rdata[41] = \\ ;\n assign s_axi_rdata[40] = \\ ;\n assign s_axi_rdata[39] = \\ ;\n assign s_axi_rdata[38] = \\ ;\n assign s_axi_rdata[37] = \\ ;\n assign s_axi_rdata[36] = \\ ;\n assign s_axi_rdata[35] = \\ ;\n assign s_axi_rdata[34] = \\ ;\n assign s_axi_rdata[33] = \\ ;\n assign s_axi_rdata[32] = \\ ;\n assign s_axi_rdata[31] = \\ ;\n assign s_axi_rdata[30] = \\ ;\n assign s_axi_rdata[29] = \\ ;\n assign s_axi_rdata[28] = \\ ;\n assign s_axi_rdata[27] = \\ ;\n assign s_axi_rdata[26] = \\ ;\n assign s_axi_rdata[25] = \\ ;\n assign s_axi_rdata[24] = \\ ;\n assign s_axi_rdata[23] = \\ ;\n assign s_axi_rdata[22] = \\ ;\n assign s_axi_rdata[21] = \\ ;\n assign s_axi_rdata[20] = \\ ;\n assign s_axi_rdata[19] = \\ ;\n assign s_axi_rdata[18] = \\ ;\n assign s_axi_rdata[17] = \\ ;\n assign s_axi_rdata[16] = \\ ;\n assign s_axi_rdata[15] = \\ ;\n assign s_axi_rdata[14] = \\ ;\n assign s_axi_rdata[13] = \\ ;\n assign s_axi_rdata[12] = \\ ;\n assign s_axi_rdata[11] = \\ ;\n assign s_axi_rdata[10] = \\ ;\n assign s_axi_rdata[9] = \\ ;\n assign s_axi_rdata[8] = \\ ;\n assign s_axi_rdata[7] = \\ ;\n assign s_axi_rdata[6] = \\ ;\n assign s_axi_rdata[5] = \\ ;\n assign s_axi_rdata[4] = \\ ;\n assign s_axi_rdata[3] = \\ ;\n assign s_axi_rdata[2] = \\ ;\n assign s_axi_rdata[1] = \\ ;\n assign s_axi_rdata[0] = \\ ;\n assign s_axi_rid[3] = \\ ;\n assign s_axi_rid[2] = \\ ;\n assign s_axi_rid[1] = \\ ;\n assign s_axi_rid[0] = \\ ;\n assign s_axi_rlast = \\ ;\n assign s_axi_rresp[1] = \\ ;\n assign s_axi_rresp[0] = \\ ;\n assign s_axi_rvalid = \\ ;\n assign s_axi_sbiterr = \\ ;\n assign s_axi_wready = \\ ;\n assign sbiterr = \\ ;\n GND GND\n (.G(\\ ));\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth inst_blk_mem_gen\n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [63:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [255:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [255:0]dina;\n wire [63:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top \\gnbram.gnativebmg.native_blk_mem_gen \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/output_line_buffer_synth_1/output_line_buffer_stub.v", "content": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// --------------------------------------------------------------------------------\n// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016\n// Date : Tue Nov 15 09:42:00 2016\n// Host : david-desktop-arch running 64-bit unknown\n// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix\n// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ output_line_buffer_stub.v\n// Design : output_line_buffer\n// Purpose : Stub declaration of top-level module interface\n// Device : xc7k325tffg900-2\n// --------------------------------------------------------------------------------\n\n// This empty module with port declaration file causes synthesis tools to infer a black box for IP.\n// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.\n// Please paste the declaration into a Verilog source file or add the file as an additional source.\n(* x_core_info = \"blk_mem_gen_v8_3_4,Vivado 2016.3\" *)\nmodule decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clka, ena, wea, addra, dina, clkb, addrb, doutb)\n/* synthesis syn_black_box black_box_pad_pin=\"clka,ena,wea[0:0],addra[9:0],dina[255:0],clkb,addrb[11:0],doutb[63:0]\" */;\n input clka;\n input ena;\n input [0:0]wea;\n input [9:0]addra;\n input [255:0]dina;\n input clkb;\n input [11:0]addrb;\n output [63:0]doutb;\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/synth_1/.Xil/ov13850_demo_propImpl.xdc", "content": "set_property SRC_FILE_INFO {cfile:/home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/constrs_1/imports/new/genesys2.xdc rfile:../../../ov13850_demo.srcs/constrs_1/imports/new/genesys2.xdc id:1} [current_design]\nset_property SRC_FILE_INFO {cfile:/home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/constrs_1/imports/constraints/ddr3_if.xdc rfile:../../../ov13850_demo.srcs/constrs_1/imports/constraints/ddr3_if.xdc id:2} [current_design]\nset_property src_info {type:XDC file:1 line:1 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AA20 [get_ports {hdmi_clk[1]}]\nset_property src_info {type:XDC file:1 line:4 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AC20 [get_ports {hdmi_d0[1]}]\nset_property src_info {type:XDC file:1 line:7 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AA22 [get_ports {hdmi_d1[1]}]\nset_property src_info {type:XDC file:1 line:10 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AB24 [get_ports {hdmi_d2[1]}]\nset_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN R19 [get_ports reset_n]\nset_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AD12 [get_ports clock_p]\nset_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN P27 [get_ports zoom_mode]\nset_property src_info {type:XDC file:1 line:29 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN P26 [get_ports freeze]\nset_property src_info {type:XDC file:1 line:32 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN D26 [get_ports {csi0_clk[1]}]\nset_property src_info {type:XDC file:1 line:35 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN B30 [get_ports {csi0_d1[1]}]\nset_property src_info {type:XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN B28 [get_ports {csi0_d3[1]}]\nset_property src_info {type:XDC file:1 line:41 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN D29 [get_ports {csi0_d0[1]}]\nset_property src_info {type:XDC file:1 line:44 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN B27 [get_ports {csi0_d2[1]}]\nset_property src_info {type:XDC file:1 line:47 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN M28 [get_ports cam_mclk]\nset_property src_info {type:XDC file:1 line:49 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN L28 [get_ports cam_i2c_sck]\nset_property src_info {type:XDC file:1 line:51 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN J29 [get_ports cam_i2c_sda]\nset_property src_info {type:XDC file:1 line:53 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN N21 [get_ports cam_rstn]\nset_property src_info {type:XDC file:1 line:63 export:INPUT save:INPUT read:READ} [current_design]\nset_output_delay -clock [get_clocks [get_clocks -filter {IS_GENERATED && MASTER_CLOCK == clock_p} -of_objects [get_pins pll1/inst/plle2_adv_inst/CLKOUT1]]] 0.000 [get_ports {{hdmi_clk[0]} {hdmi_clk[1]} {hdmi_d0[0]} {hdmi_d0[1]} {hdmi_d1[0]} {hdmi_d1[1]} {hdmi_d2[0]} {hdmi_d2[1]}}]\nset_property src_info {type:XDC file:1 line:64 export:INPUT save:INPUT read:READ} [current_design]\nset_output_delay -clock [get_clocks [get_clocks -filter {IS_GENERATED && MASTER_CLOCK == clock_p} -of_objects [get_pins pll1/inst/plle2_adv_inst/CLKOUT1]]] -clock_fall 0.000 [get_ports {{hdmi_clk[0]} {hdmi_clk[1]} {hdmi_d0[0]} {hdmi_d0[1]} {hdmi_d1[0]} {hdmi_d1[1]} {hdmi_d2[0]} {hdmi_d2[1]}}]\nset_property src_info {type:XDC file:1 line:66 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AH20 [get_ports {vga_b[0]}]\nset_property src_info {type:XDC file:1 line:67 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AG20 [get_ports {vga_b[1]}]\nset_property src_info {type:XDC file:1 line:68 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AF21 [get_ports {vga_b[2]}]\nset_property src_info {type:XDC file:1 line:69 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AK20 [get_ports {vga_b[3]}]\nset_property src_info {type:XDC file:1 line:70 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AG22 [get_ports {vga_b[4]}]\nset_property src_info {type:XDC file:1 line:71 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AJ23 [get_ports {vga_g[0]}]\nset_property src_info {type:XDC file:1 line:72 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AJ22 [get_ports {vga_g[1]}]\nset_property src_info {type:XDC file:1 line:73 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AH22 [get_ports {vga_g[2]}]\nset_property src_info {type:XDC file:1 line:74 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AK21 [get_ports {vga_g[3]}]\nset_property src_info {type:XDC file:1 line:75 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AJ21 [get_ports {vga_g[4]}]\nset_property src_info {type:XDC file:1 line:76 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AK23 [get_ports {vga_g[5]}]\nset_property src_info {type:XDC file:1 line:77 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AF20 [get_ports vga_hsync]\nset_property src_info {type:XDC file:1 line:78 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AK25 [get_ports {vga_r[0]}]\nset_property src_info {type:XDC file:1 line:79 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AG25 [get_ports {vga_r[1]}]\nset_property src_info {type:XDC file:1 line:80 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AH25 [get_ports {vga_r[2]}]\nset_property src_info {type:XDC file:1 line:81 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AK24 [get_ports {vga_r[3]}]\nset_property src_info {type:XDC file:1 line:82 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AJ24 [get_ports {vga_r[4]}]\nset_property src_info {type:XDC file:1 line:83 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AG23 [get_ports vga_vsync]\nset_property src_info {type:XDC file:2 line:34 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AD3 [get_ports {ddr3_dq[0]}]\nset_property src_info {type:XDC file:2 line:39 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AC2 [get_ports {ddr3_dq[1]}]\nset_property src_info {type:XDC file:2 line:44 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AC1 [get_ports {ddr3_dq[2]}]\nset_property src_info {type:XDC file:2 line:49 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AC5 [get_ports {ddr3_dq[3]}]\nset_property src_info {type:XDC file:2 line:54 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AC4 [get_ports {ddr3_dq[4]}]\nset_property src_info {type:XDC file:2 line:59 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AD6 [get_ports {ddr3_dq[5]}]\nset_property src_info {type:XDC file:2 line:64 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AE6 [get_ports {ddr3_dq[6]}]\nset_property src_info {type:XDC file:2 line:69 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AC7 [get_ports {ddr3_dq[7]}]\nset_property src_info {type:XDC file:2 line:74 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AF2 [get_ports {ddr3_dq[8]}]\nset_property src_info {type:XDC file:2 line:79 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AE1 [get_ports {ddr3_dq[9]}]\nset_property src_info {type:XDC file:2 line:84 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AF1 [get_ports {ddr3_dq[10]}]\nset_property src_info {type:XDC file:2 line:89 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AE4 [get_ports {ddr3_dq[11]}]\nset_property src_info {type:XDC file:2 line:94 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AE3 [get_ports {ddr3_dq[12]}]\nset_property src_info {type:XDC file:2 line:99 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AE5 [get_ports {ddr3_dq[13]}]\nset_property src_info {type:XDC file:2 line:104 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AF5 [get_ports {ddr3_dq[14]}]\nset_property src_info {type:XDC file:2 line:109 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AF6 [get_ports {ddr3_dq[15]}]\nset_property src_info {type:XDC file:2 line:114 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AJ4 [get_ports {ddr3_dq[16]}]\nset_property src_info {type:XDC file:2 line:119 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AH6 [get_ports {ddr3_dq[17]}]\nset_property src_info {type:XDC file:2 line:124 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AH5 [get_ports {ddr3_dq[18]}]\nset_property src_info {type:XDC file:2 line:129 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AH2 [get_ports {ddr3_dq[19]}]\nset_property src_info {type:XDC file:2 line:134 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AJ2 [get_ports {ddr3_dq[20]}]\nset_property src_info {type:XDC file:2 line:139 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AJ1 [get_ports {ddr3_dq[21]}]\nset_property src_info {type:XDC file:2 line:144 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AK1 [get_ports {ddr3_dq[22]}]\nset_property src_info {type:XDC file:2 line:149 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AJ3 [get_ports {ddr3_dq[23]}]\nset_property src_info {type:XDC file:2 line:154 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AF7 [get_ports {ddr3_dq[24]}]\nset_property src_info {type:XDC file:2 line:159 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AG7 [get_ports {ddr3_dq[25]}]\nset_property src_info {type:XDC file:2 line:164 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AJ6 [get_ports {ddr3_dq[26]}]\nset_property src_info {type:XDC file:2 line:169 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AK6 [get_ports {ddr3_dq[27]}]\nset_property src_info {type:XDC file:2 line:174 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AJ8 [get_ports {ddr3_dq[28]}]\nset_property src_info {type:XDC file:2 line:179 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AK8 [get_ports {ddr3_dq[29]}]\nset_property src_info {type:XDC file:2 line:184 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AK5 [get_ports {ddr3_dq[30]}]\nset_property src_info {type:XDC file:2 line:189 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AK4 [get_ports {ddr3_dq[31]}]\nset_property src_info {type:XDC file:2 line:194 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AH9 [get_ports {ddr3_addr[14]}]\nset_property src_info {type:XDC file:2 line:199 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AA12 [get_ports {ddr3_addr[13]}]\nset_property src_info {type:XDC file:2 line:204 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AB12 [get_ports {ddr3_addr[12]}]\nset_property src_info {type:XDC file:2 line:209 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AA8 [get_ports {ddr3_addr[11]}]\nset_property src_info {type:XDC file:2 line:214 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AB8 [get_ports {ddr3_addr[10]}]\nset_property src_info {type:XDC file:2 line:219 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN Y11 [get_ports {ddr3_addr[9]}]\nset_property src_info {type:XDC file:2 line:224 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN Y10 [get_ports {ddr3_addr[8]}]\nset_property src_info {type:XDC file:2 line:229 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AA11 [get_ports {ddr3_addr[7]}]\nset_property src_info {type:XDC file:2 line:234 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AA10 [get_ports {ddr3_addr[6]}]\nset_property src_info {type:XDC file:2 line:239 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AA13 [get_ports {ddr3_addr[5]}]\nset_property src_info {type:XDC file:2 line:244 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AD9 [get_ports {ddr3_addr[4]}]\nset_property src_info {type:XDC file:2 line:249 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AC10 [get_ports {ddr3_addr[3]}]\nset_property src_info {type:XDC file:2 line:254 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AD8 [get_ports {ddr3_addr[2]}]\nset_property src_info {type:XDC file:2 line:259 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AE8 [get_ports {ddr3_addr[1]}]\nset_property src_info {type:XDC file:2 line:264 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AC12 [get_ports {ddr3_addr[0]}]\nset_property src_info {type:XDC file:2 line:269 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AC11 [get_ports {ddr3_ba[2]}]\nset_property src_info {type:XDC file:2 line:274 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AB10 [get_ports {ddr3_ba[1]}]\nset_property src_info {type:XDC file:2 line:279 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AE9 [get_ports {ddr3_ba[0]}]\nset_property src_info {type:XDC file:2 line:284 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AE11 [get_ports ddr3_ras_n]\nset_property src_info {type:XDC file:2 line:289 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AF11 [get_ports ddr3_cas_n]\nset_property src_info {type:XDC file:2 line:294 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AG13 [get_ports ddr3_we_n]\nset_property src_info {type:XDC file:2 line:299 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AG5 [get_ports ddr3_reset_n]\nset_property src_info {type:XDC file:2 line:304 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AJ9 [get_ports {ddr3_cke[0]}]\nset_property src_info {type:XDC file:2 line:309 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AK9 [get_ports {ddr3_odt[0]}]\nset_property src_info {type:XDC file:2 line:314 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AH12 [get_ports {ddr3_cs_n[0]}]\nset_property src_info {type:XDC file:2 line:319 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AD4 [get_ports {ddr3_dm[0]}]\nset_property src_info {type:XDC file:2 line:324 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AF3 [get_ports {ddr3_dm[1]}]\nset_property src_info {type:XDC file:2 line:329 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AH4 [get_ports {ddr3_dm[2]}]\nset_property src_info {type:XDC file:2 line:334 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AF8 [get_ports {ddr3_dm[3]}]\nset_property src_info {type:XDC file:2 line:343 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AD2 [get_ports {ddr3_dqs_p[0]}]\nset_property src_info {type:XDC file:2 line:344 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AD1 [get_ports {ddr3_dqs_n[0]}]\nset_property src_info {type:XDC file:2 line:353 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AG4 [get_ports {ddr3_dqs_p[1]}]\nset_property src_info {type:XDC file:2 line:354 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AG3 [get_ports {ddr3_dqs_n[1]}]\nset_property src_info {type:XDC file:2 line:363 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AG2 [get_ports {ddr3_dqs_p[2]}]\nset_property src_info {type:XDC file:2 line:364 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AH1 [get_ports {ddr3_dqs_n[2]}]\nset_property src_info {type:XDC file:2 line:373 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AH7 [get_ports {ddr3_dqs_p[3]}]\nset_property src_info {type:XDC file:2 line:374 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AJ7 [get_ports {ddr3_dqs_n[3]}]\nset_property src_info {type:XDC file:2 line:383 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AB9 [get_ports {ddr3_ck_p[0]}]\nset_property src_info {type:XDC file:2 line:384 export:INPUT save:INPUT read:READ} [current_design]\nset_property PACKAGE_PIN AC9 [get_ports {ddr3_ck_n[0]}]\nset_property src_info {type:XDC file:2 line:388 export:INPUT save:INPUT read:READ} [current_design]\nset_property LOC PHASER_OUT_PHY_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}]\nset_property src_info {type:XDC file:2 line:389 export:INPUT save:INPUT read:READ} [current_design]\nset_property LOC PHASER_OUT_PHY_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}]\nset_property src_info {type:XDC file:2 line:390 export:INPUT save:INPUT read:READ} [current_design]\nset_property LOC PHASER_OUT_PHY_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}]\nset_property src_info {type:XDC file:2 line:391 export:INPUT save:INPUT read:READ} [current_design]\nset_property LOC PHASER_OUT_PHY_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}]\nset_property src_info {type:XDC file:2 line:392 export:INPUT save:INPUT read:READ} [current_design]\nset_property LOC PHASER_OUT_PHY_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}]\nset_property src_info {type:XDC file:2 line:393 export:INPUT save:INPUT read:READ} [current_design]\nset_property LOC PHASER_OUT_PHY_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}]\nset_property src_info {type:XDC file:2 line:394 export:INPUT save:INPUT read:READ} [current_design]\nset_property LOC PHASER_OUT_PHY_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}]\nset_property src_info {type:XDC file:2 line:395 export:INPUT save:INPUT read:READ} [current_design]\nset_property LOC PHASER_OUT_PHY_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}]\nset_property src_info {type:XDC file:2 line:401 export:INPUT save:INPUT read:READ} [current_design]\nset_property LOC PHASER_IN_PHY_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}]\nset_property src_info {type:XDC file:2 line:402 export:INPUT save:INPUT read:READ} [current_design]\nset_property LOC PHASER_IN_PHY_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}]\nset_property src_info {type:XDC file:2 line:403 export:INPUT save:INPUT read:READ} [current_design]\nset_property LOC PHASER_IN_PHY_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}]\nset_property src_info {type:XDC file:2 line:404 export:INPUT save:INPUT read:READ} [current_design]\nset_property LOC PHASER_IN_PHY_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}]\nset_property src_info {type:XDC file:2 line:408 export:INPUT save:INPUT read:READ} [current_design]\nset_property LOC OUT_FIFO_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}]\nset_property src_info {type:XDC file:2 line:409 export:INPUT save:INPUT read:READ} [current_design]\nset_property LOC OUT_FIFO_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}]\nset_property src_info {type:XDC file:2 line:410 export:INPUT save:INPUT read:READ} [current_design]\nset_property LOC OUT_FIFO_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}]\nset_property src_info {type:XDC file:2 line:411 export:INPUT save:INPUT read:READ} [current_design]\nset_property LOC OUT_FIFO_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}]\nset_property src_info {type:XDC file:2 line:412 export:INPUT save:INPUT read:READ} [current_design]\nset_property LOC OUT_FIFO_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}]\nset_property src_info {type:XDC file:2 line:413 export:INPUT save:INPUT read:READ} [current_design]\nset_property LOC OUT_FIFO_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}]\nset_property src_info {type:XDC file:2 line:414 export:INPUT save:INPUT read:READ} [current_design]\nset_property LOC OUT_FIFO_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}]\nset_property src_info {type:XDC file:2 line:415 export:INPUT save:INPUT read:READ} [current_design]\nset_property LOC OUT_FIFO_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}]\nset_property src_info {type:XDC file:2 line:417 export:INPUT save:INPUT read:READ} [current_design]\nset_property LOC IN_FIFO_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo}]\nset_property src_info {type:XDC file:2 line:418 export:INPUT save:INPUT read:READ} [current_design]\nset_property LOC IN_FIFO_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo}]\nset_property src_info {type:XDC file:2 line:419 export:INPUT save:INPUT read:READ} [current_design]\nset_property LOC IN_FIFO_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo}]\nset_property src_info {type:XDC file:2 line:420 export:INPUT save:INPUT read:READ} [current_design]\nset_property LOC IN_FIFO_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo}]\nset_property src_info {type:XDC file:2 line:422 export:INPUT save:INPUT read:READ} [current_design]\nset_property LOC PHY_CONTROL_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/phy_control_i}]\nset_property src_info {type:XDC file:2 line:423 export:INPUT save:INPUT read:READ} [current_design]\nset_property LOC PHY_CONTROL_X1Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i}]\nset_property src_info {type:XDC file:2 line:425 export:INPUT save:INPUT read:READ} [current_design]\nset_property LOC PHASER_REF_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/phaser_ref_i}]\nset_property src_info {type:XDC file:2 line:426 export:INPUT save:INPUT read:READ} [current_design]\nset_property LOC PHASER_REF_X1Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i}]\nset_property src_info {type:XDC file:2 line:428 export:INPUT save:INPUT read:READ} [current_design]\nset_property LOC OLOGIC_X1Y143 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts}]\nset_property src_info {type:XDC file:2 line:429 export:INPUT save:INPUT read:READ} [current_design]\nset_property LOC OLOGIC_X1Y131 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts}]\nset_property src_info {type:XDC file:2 line:430 export:INPUT save:INPUT read:READ} [current_design]\nset_property LOC OLOGIC_X1Y119 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts}]\nset_property src_info {type:XDC file:2 line:431 export:INPUT save:INPUT read:READ} [current_design]\nset_property LOC OLOGIC_X1Y107 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts}]\nset_property src_info {type:XDC file:2 line:433 export:INPUT save:INPUT read:READ} [current_design]\nset_property LOC PLLE2_ADV_X1Y1 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/plle2_i}]\nset_property src_info {type:XDC file:2 line:434 export:INPUT save:INPUT read:READ} [current_design]\nset_property LOC MMCME2_ADV_X1Y1 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/gen_mmcm.mmcm_i}]\nset_property src_info {type:XDC file:2 line:437 export:INPUT save:INPUT read:READ} [current_design]\nset_multicycle_path -setup -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] 6\nset_property src_info {type:XDC file:2 line:439 export:INPUT save:INPUT read:READ} [current_design]\nset_multicycle_path -hold -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] 5\nset_property src_info {type:XDC file:2 line:441 export:INPUT save:INPUT read:READ} [current_design]\nset_false_path -through [get_pins -filter {NAME =~ */DQSFOUND} -of [get_cells -hier -filter {REF_NAME == PHASER_IN_PHY}]]\nset_property src_info {type:XDC file:2 line:443 export:INPUT save:INPUT read:READ} [current_design]\nset_multicycle_path -setup -start -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] 2\nset_property src_info {type:XDC file:2 line:444 export:INPUT save:INPUT read:READ} [current_design]\nset_multicycle_path -hold -start -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] 1\nset_property src_info {type:XDC file:2 line:446 export:INPUT save:INPUT read:READ} [current_design]\nset_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1*}] 20.000\nset_property src_info {type:XDC file:2 line:447 export:INPUT save:INPUT read:READ} [current_design]\nset_max_delay -datapath_only -from [get_cells -hier *rstdiv0_sync_r1_reg*] -to [get_pins -filter {NAME =~ */RESET} -of [get_cells -hier -filter {REF_NAME == PHY_CONTROL}]] 5.000\nset_property src_info {type:XDC file:2 line:448 export:INPUT save:INPUT read:READ} [current_design]\nset_false_path -through [get_pins -hier -filter {NAME =~ */u_iodelay_ctrl/sys_rst}]\nset_property src_info {type:XDC file:2 line:450 export:INPUT save:INPUT read:READ} [current_design]\nset_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *ddr3_infrastructure/rstdiv0_sync_r1_reg*}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1*}] 20.000\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/synth_1/ov13850_demo.tcl", "content": "# \n# Synthesis run script generated by Vivado\n# \n\nset_param xicom.use_bs_reader 1\nset_msg_config -id {HDL 9-1061} -limit 100000\nset_msg_config -id {HDL 9-1654} -limit 100000\ncreate_project -in_memory -part xc7k325tffg900-2\n\nset_param project.singleFileAddWarning.threshold 0\nset_param project.compositeFile.enableAutoGeneration 0\nset_param synth.vivado.isSynthRun true\nset_property webtalk.parent_dir /home/dave/ip/examples/ov13850_demo/ov13850_demo.cache/wt [current_project]\nset_property parent.project_path /home/dave/ip/examples/ov13850_demo/ov13850_demo.xpr [current_project]\nset_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]\nset_property default_lib xil_defaultlib [current_project]\nset_property target_language Verilog [current_project]\nset_property ip_output_repo /home/dave/ip/examples/ov13850_demo/ov13850_demo.cache/ip [current_project]\nset_property ip_cache_permissions {read write} [current_project]\nadd_files -quiet /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer.dcp\nset_property used_in_implementation false [get_files /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer.dcp]\nadd_files -quiet /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer.dcp\nset_property used_in_implementation false [get_files /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer.dcp]\nadd_files -quiet /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll.dcp\nset_property used_in_implementation false [get_files /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll.dcp]\nadd_files -quiet /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll.dcp\nset_property used_in_implementation false [get_files /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll.dcp]\nadd_files -quiet /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if.dcp\nset_property used_in_implementation false [get_files /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if.dcp]\nread_vhdl -library xil_defaultlib {\n /home/dave/ip/mipi-csi-rx/csi_rx_line_buffer.vhd\n /home/dave/ip/mipi-csi-rx/csi_rx_word_align.vhd\n /home/dave/ip/mipi-csi-rx/csi_rx_idelayctrl_gen.vhd\n /home/dave/ip/mipi-csi-rx/csi_rx_hs_lane_phy.vhd\n /home/dave/ip/mipi-csi-rx/csi_rx_hs_clk_phy.vhd\n /home/dave/ip/mipi-csi-rx/csi_rx_hdr_ecc.vhd\n /home/dave/ip/mipi-csi-rx/csi_rx_clock_det.vhd\n /home/dave/ip/mipi-csi-rx/csi_rx_byte_align.vhd\n /home/dave/ip/video-misc/video_timing_ctrl.vhd\n /home/dave/ip/framebuffer-ctrl/framebuffer_ctrl.vhd\n /home/dave/ip/dvi-tx/dvi_tx_tmds_phy.vhd\n /home/dave/ip/dvi-tx/dvi_tx_tmds_enc.vhd\n /home/dave/ip/dvi-tx/dvi_tx_clk_drv.vhd\n /home/dave/ip/mipi-csi-rx/csi_rx_video_output.vhd\n /home/dave/ip/mipi-csi-rx/csi_rx_packet_handler.vhd\n /home/dave/ip/mipi-csi-rx/csi_rx_4_lane_link.vhd\n /home/dave/ip/mipi-csi-rx/csi_rx_10bit_unpack.vhd\n /home/dave/ip/video-misc/video_fb_output.vhd\n /home/dave/ip/ov-cam-control/ov_i2c_control.vhd\n /home/dave/ip/ov-cam-control/ov13850_4k_regs.vhd\n /home/dave/ip/dvi-tx/dvi_tx_top.vhd\n /home/dave/ip/mipi-csi-rx/csi_rx_top.vhd\n /home/dave/ip/demo-top/framebuffer_top.vhd\n /home/dave/ip/video-misc/image_gain_wb.vhd\n /home/dave/ip/video-misc/simple_debayer.vhd\n /home/dave/ip/ov-cam-control/ov13850_control_top.vhd\n /home/dave/ip/demo-top/ov13850_demo.vhd\n}\nforeach dcp [get_files -quiet -all *.dcp] {\n set_property used_in_implementation false $dcp\n}\nread_xdc /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/constrs_1/imports/new/genesys2.xdc\nset_property used_in_implementation false [get_files /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/constrs_1/imports/new/genesys2.xdc]\n\nread_xdc /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/constrs_1/imports/constraints/ddr3_if.xdc\nset_property used_in_implementation false [get_files /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/constrs_1/imports/constraints/ddr3_if.xdc]\n\n\nsynth_design -top ov13850_demo -part xc7k325tffg900-2 -retiming\n\n\nwrite_checkpoint -force -noxdef ov13850_demo.dcp\n\ncatch { report_utilization -file ov13850_demo_utilization_synth.rpt -pb ov13850_demo_utilization_synth.pb }\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.sim/sim_1/synth/func/genesys2_fbtest.tcl", "content": "set curr_wave [current_wave_config]\nif { [string length $curr_wave] == 0 } {\n if { [llength [get_objects]] > 0} {\n add_wave /\n set_property needs_save false [current_wave_config]\n } else {\n send_msg_id Add_Wave-1 WARNING \"No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console.\"\n }\n}\n\nrun 1000ns\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.sim/sim_1/synth/func/genesys2_fbtest_func_synth.v", "content": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// --------------------------------------------------------------------------------\n// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016\n// Date : Sat Nov 12 16:53:04 2016\n// Host : david-desktop-arch running 64-bit unknown\n// Command : write_verilog -mode funcsim -nolib -force -file\n// /home/dave/ip/examples/framebuffer_test/framebuffer_test.sim/sim_1/synth/func/genesys2_fbtest_func_synth.v\n// Design : genesys2_fbtest\n// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified\n// or synthesized. This netlist cannot be used for SDF annotated simulation.\n// Device : xc7k325tffg900-2\n// --------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\nmodule camera_pll\n (camera_pixel_clock,\n sysclk);\n output camera_pixel_clock;\n input sysclk;\n\n wire camera_pixel_clock;\n wire sysclk;\n\n camera_pll_camera_pll_clk_wiz inst\n (.camera_pixel_clock(camera_pixel_clock),\n .sysclk(sysclk));\nendmodule\n\n(* ORIG_REF_NAME = \"camera_pll_clk_wiz\" *) \nmodule camera_pll_camera_pll_clk_wiz\n (camera_pixel_clock,\n sysclk);\n output camera_pixel_clock;\n input sysclk;\n\n wire camera_pixel_clock;\n wire camera_pixel_clock_camera_pll;\n wire clkfbout_buf_camera_pll;\n wire clkfbout_camera_pll;\n wire sysclk;\n wire sysclk_camera_pll;\n wire NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED;\n wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED;\n wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED;\n wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED;\n wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED;\n wire NLW_plle2_adv_inst_DRDY_UNCONNECTED;\n wire NLW_plle2_adv_inst_LOCKED_UNCONNECTED;\n wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED;\n\n (* box_type = \"PRIMITIVE\" *) \n BUFG clkf_buf\n (.I(clkfbout_camera_pll),\n .O(clkfbout_buf_camera_pll));\n (* box_type = \"PRIMITIVE\" *) \n BUFG clkin1_bufg\n (.I(sysclk),\n .O(sysclk_camera_pll));\n (* box_type = \"PRIMITIVE\" *) \n BUFG clkout1_buf\n (.I(camera_pixel_clock_camera_pll),\n .O(camera_pixel_clock));\n (* box_type = \"PRIMITIVE\" *) \n PLLE2_ADV #(\n .BANDWIDTH(\"OPTIMIZED\"),\n .CLKFBOUT_MULT(17),\n .CLKFBOUT_PHASE(0.000000),\n .CLKIN1_PERIOD(5.000000),\n .CLKIN2_PERIOD(0.000000),\n .CLKOUT0_DIVIDE(2),\n .CLKOUT0_DUTY_CYCLE(0.500000),\n .CLKOUT0_PHASE(0.000000),\n .CLKOUT1_DIVIDE(1),\n .CLKOUT1_DUTY_CYCLE(0.500000),\n .CLKOUT1_PHASE(0.000000),\n .CLKOUT2_DIVIDE(1),\n .CLKOUT2_DUTY_CYCLE(0.500000),\n .CLKOUT2_PHASE(0.000000),\n .CLKOUT3_DIVIDE(1),\n .CLKOUT3_DUTY_CYCLE(0.500000),\n .CLKOUT3_PHASE(0.000000),\n .CLKOUT4_DIVIDE(1),\n .CLKOUT4_DUTY_CYCLE(0.500000),\n .CLKOUT4_PHASE(0.000000),\n .CLKOUT5_DIVIDE(1),\n .CLKOUT5_DUTY_CYCLE(0.500000),\n .CLKOUT5_PHASE(0.000000),\n .COMPENSATION(\"BUF_IN\"),\n .DIVCLK_DIVIDE(4),\n .IS_CLKINSEL_INVERTED(1'b0),\n .IS_PWRDWN_INVERTED(1'b0),\n .IS_RST_INVERTED(1'b0),\n .REF_JITTER1(0.010000),\n .REF_JITTER2(0.010000),\n .STARTUP_WAIT(\"FALSE\")) \n plle2_adv_inst\n (.CLKFBIN(clkfbout_buf_camera_pll),\n .CLKFBOUT(clkfbout_camera_pll),\n .CLKIN1(sysclk_camera_pll),\n .CLKIN2(1'b0),\n .CLKINSEL(1'b1),\n .CLKOUT0(camera_pixel_clock_camera_pll),\n .CLKOUT1(NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED),\n .CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED),\n .CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED),\n .CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED),\n .CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED),\n .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DCLK(1'b0),\n .DEN(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]),\n .DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED),\n .DWE(1'b0),\n .LOCKED(NLW_plle2_adv_inst_LOCKED_UNCONNECTED),\n .PWRDWN(1'b0),\n .RST(1'b0));\nendmodule\n\nmodule ddr3_if\n (ddr3_dq,\n ddr3_dqs_n,\n ddr3_dqs_p,\n ddr3_addr,\n ddr3_ba,\n ddr3_ras_n,\n ddr3_cas_n,\n ddr3_we_n,\n ddr3_reset_n,\n ddr3_ck_p,\n ddr3_ck_n,\n ddr3_cke,\n ddr3_cs_n,\n ddr3_dm,\n ddr3_odt,\n sys_clk_i,\n ui_clk,\n ui_clk_sync_rst,\n mmcm_locked,\n aresetn,\n app_sr_req,\n app_ref_req,\n app_zq_req,\n app_sr_active,\n app_ref_ack,\n app_zq_ack,\n s_axi_awid,\n s_axi_awaddr,\n s_axi_awlen,\n s_axi_awsize,\n s_axi_awburst,\n s_axi_awlock,\n s_axi_awcache,\n s_axi_awprot,\n s_axi_awqos,\n s_axi_awvalid,\n s_axi_awready,\n s_axi_wdata,\n s_axi_wstrb,\n s_axi_wlast,\n s_axi_wvalid,\n s_axi_wready,\n s_axi_bready,\n s_axi_bid,\n s_axi_bresp,\n s_axi_bvalid,\n s_axi_arid,\n s_axi_araddr,\n s_axi_arlen,\n s_axi_arsize,\n s_axi_arburst,\n s_axi_arlock,\n s_axi_arcache,\n s_axi_arprot,\n s_axi_arqos,\n s_axi_arvalid,\n s_axi_arready,\n s_axi_rready,\n s_axi_rid,\n s_axi_rdata,\n s_axi_rresp,\n s_axi_rlast,\n s_axi_rvalid,\n init_calib_complete,\n device_temp,\n sys_rst);\n inout [31:0]ddr3_dq;\n inout [3:0]ddr3_dqs_n;\n inout [3:0]ddr3_dqs_p;\n output [14:0]ddr3_addr;\n output [2:0]ddr3_ba;\n output ddr3_ras_n;\n output ddr3_cas_n;\n output ddr3_we_n;\n output ddr3_reset_n;\n output [0:0]ddr3_ck_p;\n output [0:0]ddr3_ck_n;\n output [0:0]ddr3_cke;\n output [0:0]ddr3_cs_n;\n output [3:0]ddr3_dm;\n output [0:0]ddr3_odt;\n input sys_clk_i;\n output ui_clk;\n output ui_clk_sync_rst;\n output mmcm_locked;\n input aresetn;\n input app_sr_req;\n input app_ref_req;\n input app_zq_req;\n output app_sr_active;\n output app_ref_ack;\n output app_zq_ack;\n input [0:0]s_axi_awid;\n input [29:0]s_axi_awaddr;\n input [7:0]s_axi_awlen;\n input [2:0]s_axi_awsize;\n input [1:0]s_axi_awburst;\n input [0:0]s_axi_awlock;\n input [3:0]s_axi_awcache;\n input [2:0]s_axi_awprot;\n input [3:0]s_axi_awqos;\n input s_axi_awvalid;\n output s_axi_awready;\n input [255:0]s_axi_wdata;\n input [31:0]s_axi_wstrb;\n input s_axi_wlast;\n input s_axi_wvalid;\n output s_axi_wready;\n input s_axi_bready;\n output [0:0]s_axi_bid;\n output [1:0]s_axi_bresp;\n output s_axi_bvalid;\n input [0:0]s_axi_arid;\n input [29:0]s_axi_araddr;\n input [7:0]s_axi_arlen;\n input [2:0]s_axi_arsize;\n input [1:0]s_axi_arburst;\n input [0:0]s_axi_arlock;\n input [3:0]s_axi_arcache;\n input [2:0]s_axi_arprot;\n input [3:0]s_axi_arqos;\n input s_axi_arvalid;\n output s_axi_arready;\n input s_axi_rready;\n output [0:0]s_axi_rid;\n output [255:0]s_axi_rdata;\n output [1:0]s_axi_rresp;\n output s_axi_rlast;\n output s_axi_rvalid;\n output init_calib_complete;\n output [11:0]device_temp;\n input sys_rst;\n\n wire \\ ;\n wire app_ref_ack;\n wire app_ref_req;\n wire app_sr_active;\n wire app_sr_req;\n wire app_zq_ack;\n wire app_zq_req;\n wire aresetn;\n wire [14:0]ddr3_addr;\n wire [2:0]ddr3_ba;\n wire ddr3_cas_n;\n wire [0:0]ddr3_ck_n;\n wire [0:0]ddr3_ck_p;\n wire [0:0]ddr3_cke;\n wire [0:0]ddr3_cs_n;\n wire [3:0]ddr3_dm;\n wire [31:0]ddr3_dq;\n wire [3:0]ddr3_dqs_n;\n wire [3:0]ddr3_dqs_p;\n wire [0:0]ddr3_odt;\n wire ddr3_ras_n;\n wire ddr3_reset_n;\n wire ddr3_we_n;\n wire [11:0]device_temp;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire init_calib_complete;\n wire \\lim_state_reg[6]_i_23_n_0 ;\n wire mmcm_locked;\n wire [29:0]s_axi_araddr;\n wire [1:0]s_axi_arburst;\n wire [0:0]s_axi_arid;\n wire [7:0]s_axi_arlen;\n wire s_axi_arready;\n wire s_axi_arvalid;\n wire [29:0]s_axi_awaddr;\n wire [1:0]s_axi_awburst;\n wire [0:0]s_axi_awid;\n wire [7:0]s_axi_awlen;\n wire s_axi_awready;\n wire s_axi_awvalid;\n wire [0:0]s_axi_bid;\n wire s_axi_bready;\n wire s_axi_bvalid;\n wire [255:0]s_axi_rdata;\n wire [0:0]s_axi_rid;\n wire s_axi_rlast;\n wire s_axi_rready;\n wire [1:1]\\^s_axi_rresp ;\n wire s_axi_rvalid;\n wire [255:0]s_axi_wdata;\n wire s_axi_wready;\n wire [31:0]s_axi_wstrb;\n wire s_axi_wvalid;\n wire \\stg2_target_r_reg[1]_i_2_n_0 ;\n wire stg3_dec2init_val_r_reg_i_11_n_0;\n wire sys_clk_i;\n wire sys_rst;\n wire u_ddr3_if_mig_n_112;\n wire u_ddr3_if_mig_n_113;\n wire u_ddr3_if_mig_n_127;\n wire [49:0]\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address ;\n wire [11:0]\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank ;\n wire [2:0]\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cas_n ;\n wire [3:3]\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cke ;\n wire [2:0]\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cs_n ;\n wire [0:0]\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_odt ;\n wire [1:0]\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_ras_n ;\n wire [2:0]\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_we_n ;\n wire \\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk ;\n wire \\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk ;\n wire \\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk ;\n wire \\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk ;\n wire [23:0]\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out ;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) wire \\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ;\n wire [3:0]\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ;\n wire [3:0]\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr ;\n wire [59:2]\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out ;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) wire \\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ;\n wire [3:0]\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ;\n wire [3:0]\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr ;\n wire [77:2]\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out ;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) wire \\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ;\n wire [3:0]\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ;\n wire [3:0]\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr ;\n wire ui_clk;\n wire ui_clk_sync_rst;\n wire [1:0]\\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED ;\n\n assign s_axi_bresp[1] = \\ ;\n assign s_axi_bresp[0] = \\ ;\n assign s_axi_rresp[1] = \\^s_axi_rresp [1];\n assign s_axi_rresp[0] = \\ ;\n GND GND\n (.G(\\ ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n \\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cs_n [1:0]),\n .DIB({1'b1,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cs_n [2]}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [1:0]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [3:2]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [5:4]),\n .DOD(\\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n \\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({1'b0,1'b0}),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [13:12]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [15:14]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [23:22]),\n .DOD(\\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n \\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({1'b0,1'b0}),\n .DIB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_we_n [1:0]),\n .DIC({1'b1,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_we_n [2]}),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [7:6]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [9:8]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [11:10]),\n .DOD(\\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n \\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({1'b0,1'b0}),\n .DIB({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [29],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [14]}),\n .DIC({init_calib_complete,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [44]}),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [31:30]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [33:32]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [35:34]),\n .DOD(\\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n \\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({1'b0,1'b0}),\n .DIB({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_odt ,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_odt }),\n .DIC({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_odt ,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_odt }),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [43:42]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [45:44]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [47:46]),\n .DOD(\\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n \\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({1'b0,1'b0}),\n .DIB({1'b0,1'b0}),\n .DIC({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cke ,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cke }),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [49:48]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [51:50]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [53:52]),\n .DOD(\\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n \\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cke ,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cke }),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [55:54]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [57:56]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [59:58]),\n .DOD(\\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n \\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({1'b0,1'b0}),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [7:6]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [3:2]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [5:4]),\n .DOD(\\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n \\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({1'b0,1'b0}),\n .DIB({1'b0,1'b0}),\n .DIC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cas_n [1:0]),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [13:12]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [15:14]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [17:16]),\n .DOD(\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n \\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({1'b1,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cas_n [2]}),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [19:18]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [21:20]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [23:22]),\n .DOD(\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n \\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_ras_n ),\n .DIB({1'b1,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cs_n [2]}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [25:24]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [27:26]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [29:28]),\n .DOD(\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n \\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({1'b0,1'b0}),\n .DIB({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [3],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [0]}),\n .DIC({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [9],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [6]}),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [31:30]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [33:32]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [35:34]),\n .DOD(\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n \\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({1'b0,1'b0}),\n .DIB({1'b0,1'b0}),\n .DIC({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [19],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [4]}),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [37:36]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [39:38]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [41:40]),\n .DOD(\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n \\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [49],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [34]}),\n .DIB({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [5],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [2]}),\n .DIC({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [11],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [8]}),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [43:42]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [45:44]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [47:46]),\n .DOD(\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n \\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [16],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [1]}),\n .DIB({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [46],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [31]}),\n .DIC({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [15],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [0]}),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [49:48]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [51:50]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [53:52]),\n .DOD(\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n \\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [45],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [30]}),\n .DIB({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [17],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [2]}),\n .DIC({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [47],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [32]}),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [55:54]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [57:56]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [59:58]),\n .DOD(\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n \\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({1'b0,1'b0}),\n .DIB({1'b0,1'b0}),\n .DIC({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [18],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [3]}),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [61:60]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [63:62]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [65:64]),\n .DOD(\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n \\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [48],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [33]}),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [67:66]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [69:68]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [71:70]),\n .DOD(\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n \\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({1'b0,1'b0}),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [7:6]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [3:2]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [5:4]),\n .DOD(\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n \\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [4],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [1]}),\n .DIB({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [10],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [7]}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [73:72]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [75:74]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [77:76]),\n .DOD(\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n LUT1 #(\n .INIT(2'h1)) \n \\lim_state_reg[6]_i_23 \n (.I0(u_ddr3_if_mig_n_113),\n .O(\\lim_state_reg[6]_i_23_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\stg2_target_r_reg[1]_i_2 \n (.I0(u_ddr3_if_mig_n_127),\n .O(\\stg2_target_r_reg[1]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n stg3_dec2init_val_r_reg_i_11\n (.I0(u_ddr3_if_mig_n_112),\n .O(stg3_dec2init_val_r_reg_i_11_n_0));\n ddr3_ifddr3_if_mig u_ddr3_if_mig\n (.CLKB0(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk ),\n .CLKB0_7(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk ),\n .CLKB0_8(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk ),\n .CLKB0_9(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk ),\n .D(u_ddr3_if_mig_n_127),\n .Q(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ),\n .app_ref_ack(app_ref_ack),\n .app_ref_req(app_ref_req),\n .app_sr_active(app_sr_active),\n .app_sr_req(app_sr_req),\n .app_zq_ack(app_zq_ack),\n .app_zq_req(app_zq_req),\n .aresetn(aresetn),\n .ddr3_addr(ddr3_addr),\n .ddr3_ba(ddr3_ba),\n .ddr3_cas_n(ddr3_cas_n),\n .ddr3_cke(ddr3_cke),\n .ddr3_cs_n(ddr3_cs_n),\n .ddr3_dm(ddr3_dm),\n .ddr3_dq(ddr3_dq),\n .ddr3_dqs_n(ddr3_dqs_n),\n .ddr3_dqs_p(ddr3_dqs_p),\n .ddr3_odt(ddr3_odt),\n .ddr3_ras_n(ddr3_ras_n),\n .ddr3_reset_n(ddr3_reset_n),\n .ddr3_we_n(ddr3_we_n),\n .ddr_ck_out({ddr3_ck_n,ddr3_ck_p}),\n .iserdes_clk(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk ),\n .iserdes_clk_2(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk ),\n .iserdes_clk_3(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk ),\n .iserdes_clk_4(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk ),\n .mem_out({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [23:22],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [15:0]}),\n .\\mmcm_current_reg[0] (stg3_dec2init_val_r_reg_i_11_n_0),\n .\\mmcm_init_trail_reg[0] (\\lim_state_reg[6]_i_23_n_0 ),\n .mmcm_locked(mmcm_locked),\n .out(device_temp),\n .phy_dout({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cke ,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_odt ,init_calib_complete,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [44],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [29],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [14]}),\n .rd_ptr(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr ),\n .rd_ptr_0(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr ),\n .rd_ptr_1(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr ),\n .\\rd_ptr_reg[3] ({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [77:12],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [5:2],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [7:6]}),\n .\\rd_ptr_reg[3]_0 ({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [59:42],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [35:30],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [5:2],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [7:6]}),\n .\\rd_ptr_timing_reg[0] ({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [10],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [7],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [4],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [1],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [48],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [33],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [18],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [3],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [47],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [32],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [17],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [2],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [45],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [30],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [15],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [0],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [46],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [31],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [16],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [1],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [11],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [8],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [5],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [2],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [49],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [34],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [19],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [4],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [9],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [6],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [3],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [0],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cs_n [2],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_ras_n ,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cas_n }),\n .\\rd_ptr_timing_reg[0]_0 ({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_we_n ,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cs_n [1:0]}),\n .s_axi_araddr(s_axi_araddr),\n .s_axi_arburst(s_axi_arburst[1]),\n .s_axi_arid(s_axi_arid),\n .s_axi_arlen(s_axi_arlen),\n .s_axi_arready(s_axi_arready),\n .s_axi_arvalid(s_axi_arvalid),\n .s_axi_awaddr(s_axi_awaddr),\n .s_axi_awburst(s_axi_awburst[1]),\n .s_axi_awid(s_axi_awid),\n .s_axi_awlen(s_axi_awlen),\n .s_axi_awready(s_axi_awready),\n .s_axi_awvalid(s_axi_awvalid),\n .s_axi_bid(s_axi_bid),\n .s_axi_bready(s_axi_bready),\n .s_axi_bvalid(s_axi_bvalid),\n .s_axi_rdata(s_axi_rdata),\n .s_axi_rid(s_axi_rid),\n .s_axi_rlast(s_axi_rlast),\n .s_axi_rready(s_axi_rready),\n .s_axi_rresp(\\^s_axi_rresp ),\n .s_axi_rvalid(s_axi_rvalid),\n .s_axi_wdata(s_axi_wdata),\n .s_axi_wready(s_axi_wready),\n .s_axi_wstrb(s_axi_wstrb),\n .s_axi_wvalid(s_axi_wvalid),\n .stg3_dec2init_val_r_reg(u_ddr3_if_mig_n_112),\n .stg3_inc2init_val_r_reg(u_ddr3_if_mig_n_113),\n .\\stg3_r_reg[0] (\\stg2_target_r_reg[1]_i_2_n_0 ),\n .sys_clk_i(sys_clk_i),\n .sys_rst(sys_rst),\n .ui_clk(ui_clk),\n .ui_clk_sync_rst(ui_clk_sync_rst),\n .wr_en(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ),\n .wr_en_5(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ),\n .wr_en_6(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ),\n .\\wr_ptr_timing_reg[2] (\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ),\n .\\wr_ptr_timing_reg[2]_0 (\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ));\nendmodule\n\n(* ORIG_REF_NAME = \"ddr3_if_mig\" *) \nmodule ddr3_ifddr3_if_mig\n (ui_clk,\n app_ref_ack,\n app_zq_ack,\n app_sr_active,\n ddr3_reset_n,\n ddr3_cas_n,\n ddr3_ras_n,\n ddr3_we_n,\n ddr3_addr,\n ddr3_ba,\n ddr3_cs_n,\n ddr3_odt,\n ddr3_cke,\n ddr3_dm,\n rd_ptr,\n rd_ptr_0,\n rd_ptr_1,\n ui_clk_sync_rst,\n iserdes_clk,\n iserdes_clk_2,\n iserdes_clk_3,\n iserdes_clk_4,\n phy_dout,\n out,\n mmcm_locked,\n \\rd_ptr_timing_reg[0] ,\n \\rd_ptr_timing_reg[0]_0 ,\n stg3_dec2init_val_r_reg,\n stg3_inc2init_val_r_reg,\n s_axi_arready,\n Q,\n \\wr_ptr_timing_reg[2] ,\n \\wr_ptr_timing_reg[2]_0 ,\n D,\n wr_en,\n wr_en_5,\n wr_en_6,\n ddr_ck_out,\n s_axi_awready,\n s_axi_wready,\n s_axi_rdata,\n s_axi_rresp,\n s_axi_rid,\n s_axi_bid,\n s_axi_bvalid,\n s_axi_rvalid,\n s_axi_rlast,\n ddr3_dq,\n ddr3_dqs_p,\n ddr3_dqs_n,\n app_ref_req,\n app_zq_req,\n app_sr_req,\n CLKB0,\n CLKB0_7,\n CLKB0_8,\n CLKB0_9,\n mem_out,\n \\rd_ptr_reg[3] ,\n \\rd_ptr_reg[3]_0 ,\n sys_rst,\n s_axi_arvalid,\n sys_clk_i,\n \\mmcm_init_trail_reg[0] ,\n \\mmcm_current_reg[0] ,\n \\stg3_r_reg[0] ,\n s_axi_awlen,\n s_axi_bready,\n s_axi_awvalid,\n s_axi_awaddr,\n s_axi_awburst,\n s_axi_wvalid,\n s_axi_awid,\n s_axi_arlen,\n s_axi_araddr,\n s_axi_arburst,\n s_axi_rready,\n s_axi_wstrb,\n s_axi_wdata,\n aresetn,\n s_axi_arid);\n output ui_clk;\n output app_ref_ack;\n output app_zq_ack;\n output app_sr_active;\n output ddr3_reset_n;\n output ddr3_cas_n;\n output ddr3_ras_n;\n output ddr3_we_n;\n output [14:0]ddr3_addr;\n output [2:0]ddr3_ba;\n output [0:0]ddr3_cs_n;\n output [0:0]ddr3_odt;\n output [0:0]ddr3_cke;\n output [3:0]ddr3_dm;\n output [3:0]rd_ptr;\n output [3:0]rd_ptr_0;\n output [3:0]rd_ptr_1;\n output ui_clk_sync_rst;\n output iserdes_clk;\n output iserdes_clk_2;\n output iserdes_clk_3;\n output iserdes_clk_4;\n output [5:0]phy_dout;\n output [11:0]out;\n output mmcm_locked;\n output [37:0]\\rd_ptr_timing_reg[0] ;\n output [4:0]\\rd_ptr_timing_reg[0]_0 ;\n output stg3_dec2init_val_r_reg;\n output stg3_inc2init_val_r_reg;\n output s_axi_arready;\n output [3:0]Q;\n output [3:0]\\wr_ptr_timing_reg[2] ;\n output [3:0]\\wr_ptr_timing_reg[2]_0 ;\n output [0:0]D;\n output wr_en;\n output wr_en_5;\n output wr_en_6;\n output [1:0]ddr_ck_out;\n output s_axi_awready;\n output s_axi_wready;\n output [255:0]s_axi_rdata;\n output [0:0]s_axi_rresp;\n output [0:0]s_axi_rid;\n output [0:0]s_axi_bid;\n output s_axi_bvalid;\n output s_axi_rvalid;\n output s_axi_rlast;\n inout [31:0]ddr3_dq;\n inout [3:0]ddr3_dqs_p;\n inout [3:0]ddr3_dqs_n;\n input app_ref_req;\n input app_zq_req;\n input app_sr_req;\n input CLKB0;\n input CLKB0_7;\n input CLKB0_8;\n input CLKB0_9;\n input [17:0]mem_out;\n input [71:0]\\rd_ptr_reg[3] ;\n input [29:0]\\rd_ptr_reg[3]_0 ;\n input sys_rst;\n input s_axi_arvalid;\n input sys_clk_i;\n input \\mmcm_init_trail_reg[0] ;\n input \\mmcm_current_reg[0] ;\n input \\stg3_r_reg[0] ;\n input [7:0]s_axi_awlen;\n input s_axi_bready;\n input s_axi_awvalid;\n input [29:0]s_axi_awaddr;\n input [0:0]s_axi_awburst;\n input s_axi_wvalid;\n input [0:0]s_axi_awid;\n input [7:0]s_axi_arlen;\n input [29:0]s_axi_araddr;\n input [0:0]s_axi_arburst;\n input s_axi_rready;\n input [31:0]s_axi_wstrb;\n input [255:0]s_axi_wdata;\n input aresetn;\n input [0:0]s_axi_arid;\n\n wire CLKB0;\n wire CLKB0_7;\n wire CLKB0_8;\n wire CLKB0_9;\n wire [0:0]D;\n wire [3:0]Q;\n wire app_ref_ack;\n wire app_ref_req;\n wire app_sr_active;\n wire app_sr_req;\n wire app_zq_ack;\n wire app_zq_req;\n wire aresetn;\n wire [14:0]ddr3_addr;\n wire [2:0]ddr3_ba;\n wire ddr3_cas_n;\n wire [0:0]ddr3_cke;\n wire [0:0]ddr3_cs_n;\n wire [3:0]ddr3_dm;\n wire [31:0]ddr3_dq;\n wire [3:0]ddr3_dqs_n;\n wire [3:0]ddr3_dqs_p;\n wire [0:0]ddr3_odt;\n wire ddr3_ras_n;\n wire ddr3_reset_n;\n wire ddr3_we_n;\n wire [1:0]ddr_ck_out;\n wire freq_refclk;\n wire [1:1]iodelay_ctrl_rdy;\n wire iserdes_clk;\n wire iserdes_clk_2;\n wire iserdes_clk_3;\n wire iserdes_clk_4;\n wire \\mem_intfc0/ddr_phy_top0/phy_mc_go ;\n wire \\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/pi_cnt_dec ;\n wire \\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/samp_edge_cnt0_en_r ;\n wire [11:0]\\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_100 ;\n wire \\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/po_cnt_dec ;\n wire \\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_samp/sm_r ;\n wire \\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/cnt_pwron_reset_done_r0 ;\n wire \\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/p_81_in ;\n wire \\mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/RST0 ;\n wire \\mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/bm_end_r1 ;\n wire \\mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/pass_open_bank_r ;\n wire \\mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/bm_end_r1 ;\n wire \\mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/rtp_timer_ns1 ;\n wire \\mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/pass_open_bank_r ;\n wire \\mem_intfc0/mc0/bank_mach0/insert_maint_r ;\n wire [17:0]mem_out;\n wire mem_refclk;\n wire \\mmcm_current_reg[0] ;\n wire \\mmcm_init_trail_reg[0] ;\n wire mmcm_locked;\n wire mmcm_ps_clk;\n wire [11:0]out;\n wire [5:0]phy_dout;\n wire pll_locked;\n wire poc_sample_pd;\n wire psdone;\n wire psen;\n wire [3:0]rd_ptr;\n wire [3:0]rd_ptr_0;\n wire [3:0]rd_ptr_1;\n wire [71:0]\\rd_ptr_reg[3] ;\n wire [29:0]\\rd_ptr_reg[3]_0 ;\n wire [37:0]\\rd_ptr_timing_reg[0] ;\n wire [4:0]\\rd_ptr_timing_reg[0]_0 ;\n (* MAX_FANOUT = \"10\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire rst_sync_r1;\n wire [29:0]s_axi_araddr;\n wire [0:0]s_axi_arburst;\n wire [0:0]s_axi_arid;\n wire [7:0]s_axi_arlen;\n wire s_axi_arready;\n wire s_axi_arvalid;\n wire [29:0]s_axi_awaddr;\n wire [0:0]s_axi_awburst;\n wire [0:0]s_axi_awid;\n wire [7:0]s_axi_awlen;\n wire s_axi_awready;\n wire s_axi_awvalid;\n wire [0:0]s_axi_bid;\n wire s_axi_bready;\n wire s_axi_bvalid;\n wire [255:0]s_axi_rdata;\n wire [0:0]s_axi_rid;\n wire s_axi_rlast;\n wire s_axi_rready;\n wire [0:0]s_axi_rresp;\n wire s_axi_rvalid;\n wire [255:0]s_axi_wdata;\n wire s_axi_wready;\n wire [31:0]s_axi_wstrb;\n wire s_axi_wvalid;\n wire stg3_dec2init_val_r_reg;\n wire stg3_inc2init_val_r_reg;\n wire \\stg3_r_reg[0] ;\n wire sync_pulse;\n wire sys_clk_i;\n wire sys_rst;\n wire sys_rst_act_hi;\n wire u_ddr3_clk_ibuf_n_0;\n wire u_ddr3_infrastructure_n_10;\n wire u_ddr3_infrastructure_n_11;\n wire u_ddr3_infrastructure_n_13;\n wire u_ddr3_infrastructure_n_14;\n wire u_ddr3_infrastructure_n_15;\n wire u_ddr3_infrastructure_n_16;\n wire u_ddr3_infrastructure_n_17;\n wire u_ddr3_infrastructure_n_18;\n wire u_ddr3_infrastructure_n_19;\n wire u_ddr3_infrastructure_n_20;\n wire u_ddr3_infrastructure_n_21;\n wire u_ddr3_infrastructure_n_22;\n wire u_ddr3_infrastructure_n_23;\n wire u_ddr3_infrastructure_n_24;\n wire u_ddr3_infrastructure_n_25;\n wire u_ddr3_infrastructure_n_26;\n wire u_ddr3_infrastructure_n_27;\n wire u_ddr3_infrastructure_n_28;\n wire u_ddr3_infrastructure_n_29;\n wire u_ddr3_infrastructure_n_30;\n wire u_ddr3_infrastructure_n_31;\n wire u_ddr3_infrastructure_n_32;\n wire u_ddr3_infrastructure_n_33;\n wire u_ddr3_infrastructure_n_34;\n wire u_ddr3_infrastructure_n_35;\n wire u_ddr3_infrastructure_n_36;\n wire u_ddr3_infrastructure_n_37;\n wire u_ddr3_infrastructure_n_39;\n wire u_ddr3_infrastructure_n_40;\n wire u_ddr3_infrastructure_n_42;\n wire u_ddr3_infrastructure_n_44;\n wire u_ddr3_infrastructure_n_45;\n wire u_ddr3_infrastructure_n_46;\n wire u_ddr3_infrastructure_n_47;\n wire u_ddr3_infrastructure_n_48;\n wire u_ddr3_infrastructure_n_49;\n wire u_ddr3_infrastructure_n_50;\n wire u_ddr3_infrastructure_n_52;\n wire u_ddr3_infrastructure_n_54;\n wire u_ddr3_infrastructure_n_9;\n wire u_memc_ui_top_axi_n_108;\n wire u_memc_ui_top_axi_n_111;\n wire u_memc_ui_top_axi_n_113;\n wire u_memc_ui_top_axi_n_114;\n wire u_memc_ui_top_axi_n_116;\n wire u_memc_ui_top_axi_n_117;\n wire u_memc_ui_top_axi_n_118;\n wire u_memc_ui_top_axi_n_61;\n wire ui_clk;\n wire ui_clk_sync_rst;\n wire wr_en;\n wire wr_en_5;\n wire wr_en_6;\n wire [3:0]\\wr_ptr_timing_reg[2] ;\n wire [3:0]\\wr_ptr_timing_reg[2]_0 ;\n\n ddr3_ifmig_7series_v4_0_tempmon \\temp_mon_enabled.u_tempmon \n (.CLK(ui_clk),\n .D(\\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_100 ),\n .in0(ui_clk_sync_rst),\n .mmcm_clk(u_ddr3_clk_ibuf_n_0),\n .out(out));\n ddr3_ifmig_7series_v4_0_clk_ibuf u_ddr3_clk_ibuf\n (.mmcm_clk(u_ddr3_clk_ibuf_n_0),\n .sys_clk_i(sys_clk_i));\n ddr3_ifmig_7series_v4_0_infrastructure u_ddr3_infrastructure\n (.AS(sys_rst_act_hi),\n .CLK(ui_clk),\n .E(psen),\n .RST0(\\mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/RST0 ),\n .SR(u_ddr3_infrastructure_n_14),\n .SS(u_ddr3_infrastructure_n_16),\n .bm_end_r1(\\mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/bm_end_r1 ),\n .bm_end_r1_1(\\mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/bm_end_r1 ),\n .cal2_if_reset_reg(u_ddr3_infrastructure_n_18),\n .cal2_prech_req_r_reg(u_ddr3_infrastructure_n_19),\n .\\cal2_state_r_reg[0] (u_ddr3_infrastructure_n_17),\n .cnt_pwron_reset_done_r0(\\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/cnt_pwron_reset_done_r0 ),\n .\\complex_address_reg[0] (u_ddr3_infrastructure_n_24),\n .\\en_cnt_div4.enable_wrlvl_cnt_reg[2] (u_ddr3_infrastructure_n_23),\n .\\en_cnt_div4.enable_wrlvl_cnt_reg[4] (u_ddr3_infrastructure_n_50),\n .\\en_cnt_div4.wrlvl_odt_reg (u_memc_ui_top_axi_n_116),\n .fine_adjust_reg(u_memc_ui_top_axi_n_61),\n .\\first_fail_taps_reg[0] (u_ddr3_infrastructure_n_26),\n .freq_refclk(freq_refclk),\n .\\gen_final_tap[2].final_val_reg[2][1] (u_ddr3_infrastructure_n_29),\n .in0(ui_clk_sync_rst),\n .\\init_state_r_reg[6] (u_ddr3_infrastructure_n_25),\n .insert_maint_r(\\mem_intfc0/mc0/bank_mach0/insert_maint_r ),\n .\\last_master_r_reg[2] (u_ddr3_infrastructure_n_33),\n .\\lim_state_reg[0] (u_memc_ui_top_axi_n_113),\n .mem_refclk(mem_refclk),\n .mmcm_clk(u_ddr3_clk_ibuf_n_0),\n .mmcm_locked(mmcm_locked),\n .mmcm_ps_clk(mmcm_ps_clk),\n .\\oneeighty_r_reg[0] (u_ddr3_infrastructure_n_37),\n .\\oneeighty_r_reg[0]_0 (u_ddr3_infrastructure_n_40),\n .p_81_in(\\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/p_81_in ),\n .pass_open_bank_r(\\mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/pass_open_bank_r ),\n .pass_open_bank_r_0(\\mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/pass_open_bank_r ),\n .phy_mc_go(\\mem_intfc0/ddr_phy_top0/phy_mc_go ),\n .pi_cnt_dec(\\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/pi_cnt_dec ),\n .\\pi_rdval_cnt_reg[0] ({u_ddr3_infrastructure_n_27,u_ddr3_infrastructure_n_28}),\n .\\pi_rst_stg1_cal_r_reg[1] (u_ddr3_infrastructure_n_47),\n .pll_locked(pll_locked),\n .po_cnt_dec(\\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/po_cnt_dec ),\n .poc_backup_r_reg(u_memc_ui_top_axi_n_114),\n .poc_sample_pd(poc_sample_pd),\n .prbs_found_1st_edge_r_reg(u_ddr3_infrastructure_n_21),\n .pre_wait_r_reg(u_ddr3_infrastructure_n_42),\n .psdone(psdone),\n .ras_timer_zero_r_reg(u_ddr3_infrastructure_n_45),\n .ras_timer_zero_r_reg_0(u_ddr3_infrastructure_n_46),\n .\\read_fifo.head_r_reg[0] (u_ddr3_infrastructure_n_13),\n .reset_reg(u_ddr3_infrastructure_n_10),\n .\\resume_wait_r_reg[10] (u_memc_ui_top_axi_n_108),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] (u_ddr3_infrastructure_n_34),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] (u_ddr3_infrastructure_n_44),\n .\\row_cnt_victim_rotate.complex_row_cnt_reg[7] (u_memc_ui_top_axi_n_118),\n .rst_out_reg(u_ddr3_infrastructure_n_22),\n .\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] (u_memc_ui_top_axi_n_111),\n .rst_sync_r1(rst_sync_r1),\n .rtp_timer_ns1(\\mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/rtp_timer_ns1 ),\n .samp_edge_cnt0_en_r(\\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/samp_edge_cnt0_en_r ),\n .\\samp_edge_cnt0_r_reg[11] (u_ddr3_infrastructure_n_48),\n .\\simp_stg3_final_r_reg[17] (u_ddr3_infrastructure_n_11),\n .sm_r(\\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_samp/sm_r ),\n .\\stg3_r_reg[1] (u_ddr3_infrastructure_n_39),\n .\\stg3_tap_cnt_reg[0] (u_ddr3_infrastructure_n_9),\n .sync_pulse(sync_pulse),\n .\\three_dec_max_limit_reg[11] (u_ddr3_infrastructure_n_20),\n .\\victim_sel_rotate.sel_reg[31] (u_ddr3_infrastructure_n_32),\n .\\wait_cnt_r_reg[3] (u_ddr3_infrastructure_n_49),\n .\\wait_cnt_reg[3] (u_ddr3_infrastructure_n_35),\n .\\wait_cnt_reg[3]_0 (u_ddr3_infrastructure_n_54),\n .\\wl_tap_count_r_reg[0] ({u_ddr3_infrastructure_n_30,u_ddr3_infrastructure_n_31}),\n .wr_victim_inc_reg(u_memc_ui_top_axi_n_117),\n .\\wr_victim_sel_ocal_reg[2] (u_ddr3_infrastructure_n_52),\n .\\wrcal_dqs_cnt_r_reg[2] (u_ddr3_infrastructure_n_15),\n .\\wrcal_reads_reg[0] (u_ddr3_infrastructure_n_36));\n ddr3_ifmig_7series_v4_0_iodelay_ctrl u_iodelay_ctrl\n (.AS(sys_rst_act_hi),\n .mmcm_clk(u_ddr3_clk_ibuf_n_0),\n .rst_sync_r1_reg(iodelay_ctrl_rdy),\n .sys_rst(sys_rst));\n (* x_core_info = \"mig_7series_v4_0_ddr3_7Series, ddr3_if, 2016.2\" *) \n ddr3_ifmig_7series_v4_0_memc_ui_top_axi u_memc_ui_top_axi\n (.CLK(ui_clk),\n .CLKB0(CLKB0),\n .CLKB0_7(CLKB0_7),\n .CLKB0_8(CLKB0_8),\n .CLKB0_9(CLKB0_9),\n .D(D),\n .E(psen),\n .Q(Q),\n .RST0(\\mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/RST0 ),\n .SR(u_ddr3_infrastructure_n_14),\n .SS(u_ddr3_infrastructure_n_16),\n .app_ref_ack(app_ref_ack),\n .app_ref_req(app_ref_req),\n .app_sr_active(app_sr_active),\n .app_sr_req(app_sr_req),\n .app_zq_ack(app_zq_ack),\n .app_zq_req(app_zq_req),\n .aresetn(aresetn),\n .bm_end_r1(\\mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/bm_end_r1 ),\n .bm_end_r1_0(\\mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/bm_end_r1 ),\n .bm_end_r1_reg(u_ddr3_infrastructure_n_45),\n .bm_end_r1_reg_0(u_ddr3_infrastructure_n_46),\n .cnt_pwron_reset_done_r0(\\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/cnt_pwron_reset_done_r0 ),\n .\\complex_row_cnt_ocal_reg[0] (u_memc_ui_top_axi_n_117),\n .ddr3_addr(ddr3_addr),\n .ddr3_ba(ddr3_ba),\n .ddr3_cas_n(ddr3_cas_n),\n .ddr3_cke(ddr3_cke),\n .ddr3_cs_n(ddr3_cs_n),\n .ddr3_dm(ddr3_dm),\n .ddr3_dq(ddr3_dq),\n .ddr3_dqs_n(ddr3_dqs_n),\n .ddr3_dqs_p(ddr3_dqs_p),\n .ddr3_odt(ddr3_odt),\n .ddr3_ras_n(ddr3_ras_n),\n .ddr3_reset_n(ddr3_reset_n),\n .ddr3_we_n(ddr3_we_n),\n .ddr_ck_out(ddr_ck_out),\n .\\device_temp_r_reg[11] (\\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_100 ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (iserdes_clk),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (iserdes_clk_2),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (iserdes_clk_3),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (iserdes_clk_4),\n .\\en_cnt_div4.enable_wrlvl_cnt_reg[3] (u_memc_ui_top_axi_n_116),\n .fine_adjust_reg(u_ddr3_infrastructure_n_47),\n .freq_refclk(freq_refclk),\n .\\generate_maint_cmds.insert_maint_r_lcl_reg (u_ddr3_infrastructure_n_44),\n .in0(ui_clk_sync_rst),\n .insert_maint_r(\\mem_intfc0/mc0/bank_mach0/insert_maint_r ),\n .mem_out(mem_out),\n .mem_refclk(mem_refclk),\n .\\mmcm_current_reg[0] (\\mmcm_current_reg[0] ),\n .\\mmcm_init_trail_reg[0] (\\mmcm_init_trail_reg[0] ),\n .mmcm_locked(mmcm_locked),\n .mmcm_ps_clk(mmcm_ps_clk),\n .out({s_axi_rresp,s_axi_rdata}),\n .p_81_in(\\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/p_81_in ),\n .pass_open_bank_r(\\mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/pass_open_bank_r ),\n .pass_open_bank_r_1(\\mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/pass_open_bank_r ),\n .pass_open_bank_r_lcl_reg(u_ddr3_infrastructure_n_42),\n .phy_dout(phy_dout),\n .phy_mc_go(\\mem_intfc0/ddr_phy_top0/phy_mc_go ),\n .pi_cnt_dec(\\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/pi_cnt_dec ),\n .pi_cnt_dec_reg(u_ddr3_infrastructure_n_49),\n .\\pi_rst_stg1_cal_r_reg[0] (u_memc_ui_top_axi_n_61),\n .pll_locked(pll_locked),\n .po_cnt_dec(\\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/po_cnt_dec ),\n .po_cnt_dec_reg(u_ddr3_infrastructure_n_54),\n .poc_sample_pd(poc_sample_pd),\n .psdone(psdone),\n .\\rd_ptr_reg[3] (\\rd_ptr_reg[3] ),\n .\\rd_ptr_reg[3]_0 (\\rd_ptr_reg[3]_0 ),\n .\\rd_ptr_timing_reg[0] (\\rd_ptr_timing_reg[0] ),\n .\\rd_ptr_timing_reg[0]_0 (\\rd_ptr_timing_reg[0]_0 ),\n .\\rd_ptr_timing_reg[2] (rd_ptr[3]),\n .\\rd_ptr_timing_reg[2]_0 (rd_ptr[2]),\n .\\rd_ptr_timing_reg[2]_1 (rd_ptr[1]),\n .\\rd_ptr_timing_reg[2]_10 (rd_ptr_1[3]),\n .\\rd_ptr_timing_reg[2]_2 (rd_ptr[0]),\n .\\rd_ptr_timing_reg[2]_3 (rd_ptr_0[3]),\n .\\rd_ptr_timing_reg[2]_4 (rd_ptr_0[2]),\n .\\rd_ptr_timing_reg[2]_5 (rd_ptr_0[1]),\n .\\rd_ptr_timing_reg[2]_6 (rd_ptr_0[0]),\n .\\rd_ptr_timing_reg[2]_7 (rd_ptr_1[0]),\n .\\rd_ptr_timing_reg[2]_8 (rd_ptr_1[1]),\n .\\rd_ptr_timing_reg[2]_9 (rd_ptr_1[2]),\n .\\resume_wait_r_reg[5] (u_memc_ui_top_axi_n_108),\n .\\row_cnt_victim_rotate.complex_row_cnt_reg[4] (u_memc_ui_top_axi_n_118),\n .\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] (iodelay_ctrl_rdy),\n .rst_sync_r1(rst_sync_r1),\n .rst_sync_r1_reg(u_memc_ui_top_axi_n_111),\n .rstdiv0_sync_r1_reg_rep__0(u_ddr3_infrastructure_n_13),\n .rstdiv0_sync_r1_reg_rep__10(u_ddr3_infrastructure_n_23),\n .rstdiv0_sync_r1_reg_rep__11(u_ddr3_infrastructure_n_24),\n .rstdiv0_sync_r1_reg_rep__12(u_ddr3_infrastructure_n_25),\n .rstdiv0_sync_r1_reg_rep__13(u_ddr3_infrastructure_n_26),\n .rstdiv0_sync_r1_reg_rep__14({u_ddr3_infrastructure_n_27,u_ddr3_infrastructure_n_28}),\n .rstdiv0_sync_r1_reg_rep__16(u_ddr3_infrastructure_n_29),\n .rstdiv0_sync_r1_reg_rep__17({u_ddr3_infrastructure_n_30,u_ddr3_infrastructure_n_31}),\n .rstdiv0_sync_r1_reg_rep__19(u_ddr3_infrastructure_n_32),\n .rstdiv0_sync_r1_reg_rep__2(u_ddr3_infrastructure_n_15),\n .rstdiv0_sync_r1_reg_rep__20(u_ddr3_infrastructure_n_33),\n .rstdiv0_sync_r1_reg_rep__21(u_ddr3_infrastructure_n_34),\n .rstdiv0_sync_r1_reg_rep__22(u_ddr3_infrastructure_n_35),\n .rstdiv0_sync_r1_reg_rep__23(u_ddr3_infrastructure_n_36),\n .rstdiv0_sync_r1_reg_rep__23_0(u_ddr3_infrastructure_n_50),\n .rstdiv0_sync_r1_reg_rep__23_1(u_ddr3_infrastructure_n_52),\n .rstdiv0_sync_r1_reg_rep__24(u_ddr3_infrastructure_n_37),\n .rstdiv0_sync_r1_reg_rep__25(u_ddr3_infrastructure_n_10),\n .rstdiv0_sync_r1_reg_rep__25_0(u_ddr3_infrastructure_n_11),\n .rstdiv0_sync_r1_reg_rep__25_1(u_ddr3_infrastructure_n_9),\n .rstdiv0_sync_r1_reg_rep__25_2(u_ddr3_infrastructure_n_39),\n .rstdiv0_sync_r1_reg_rep__4(u_ddr3_infrastructure_n_17),\n .rstdiv0_sync_r1_reg_rep__5(u_ddr3_infrastructure_n_18),\n .rstdiv0_sync_r1_reg_rep__6(u_ddr3_infrastructure_n_19),\n .rstdiv0_sync_r1_reg_rep__7(u_ddr3_infrastructure_n_20),\n .rstdiv0_sync_r1_reg_rep__8(u_ddr3_infrastructure_n_21),\n .rstdiv0_sync_r1_reg_rep__9(u_ddr3_infrastructure_n_22),\n .rtp_timer_ns1(\\mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/rtp_timer_ns1 ),\n .s_axi_araddr(s_axi_araddr),\n .s_axi_arburst(s_axi_arburst),\n .s_axi_arid(s_axi_arid),\n .s_axi_arlen(s_axi_arlen),\n .s_axi_arready(s_axi_arready),\n .s_axi_arvalid(s_axi_arvalid),\n .s_axi_awaddr(s_axi_awaddr),\n .s_axi_awburst(s_axi_awburst),\n .s_axi_awid(s_axi_awid),\n .s_axi_awlen(s_axi_awlen),\n .s_axi_awready(s_axi_awready),\n .s_axi_awvalid(s_axi_awvalid),\n .s_axi_bid(s_axi_bid),\n .s_axi_bready(s_axi_bready),\n .s_axi_bvalid(s_axi_bvalid),\n .s_axi_rid(s_axi_rid),\n .s_axi_rlast(s_axi_rlast),\n .s_axi_rready(s_axi_rready),\n .s_axi_rvalid(s_axi_rvalid),\n .s_axi_wdata(s_axi_wdata),\n .s_axi_wready(s_axi_wready),\n .s_axi_wstrb(s_axi_wstrb),\n .s_axi_wvalid(s_axi_wvalid),\n .samp_edge_cnt0_en_r(\\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/samp_edge_cnt0_en_r ),\n .samp_edge_cnt0_en_r_reg(u_ddr3_infrastructure_n_48),\n .sm_r(\\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_samp/sm_r ),\n .\\sm_r_reg[0] (u_memc_ui_top_axi_n_114),\n .\\sm_r_reg[0]_0 (u_ddr3_infrastructure_n_40),\n .\\stg2_tap_cnt_reg[0] (u_memc_ui_top_axi_n_113),\n .stg3_dec2init_val_r_reg(stg3_dec2init_val_r_reg),\n .stg3_inc2init_val_r_reg(stg3_inc2init_val_r_reg),\n .\\stg3_r_reg[0] (\\stg3_r_reg[0] ),\n .sync_pulse(sync_pulse),\n .sys_rst(sys_rst),\n .wr_en(wr_en),\n .wr_en_5(wr_en_5),\n .wr_en_6(wr_en_6),\n .\\wr_ptr_timing_reg[2] (\\wr_ptr_timing_reg[2] ),\n .\\wr_ptr_timing_reg[2]_0 (\\wr_ptr_timing_reg[2]_0 ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_arb_mux\" *) \nmodule ddr3_ifmig_7series_v4_0_arb_mux\n (\\cmd_pipe_plus.mc_address_reg[0] ,\n \\cmd_pipe_plus.mc_cmd_reg[0] ,\n DIC,\n col_data_buf_addr,\n cke_r,\n \\rnk_config_strobe_r_reg[0] ,\n \\periodic_rd_generation.periodic_rd_timer_r_reg[0] ,\n Q,\n read_this_rank,\n D,\n granted_col_r_reg,\n \\rtw_timer.rtw_cnt_r_reg[1] ,\n mc_odt_ns,\n col_rd_wr,\n mc_data_offset_2_ns,\n \\cmd_pipe_plus.mc_cas_n_reg[2] ,\n \\cmd_pipe_plus.mc_address_reg[0]_0 ,\n mc_cas_n_ns,\n \\cmd_pipe_plus.mc_cs_n_reg[0] ,\n mc_ras_n_ns,\n \\cmd_pipe_plus.mc_bank_reg[5] ,\n \\cmd_pipe_plus.mc_address_reg[25] ,\n granted_row_r_reg,\n granted_col_r_reg_0,\n granted_col_r_reg_1,\n override_demand_ns,\n granted_row_r_reg_0,\n \\wtr_timer.wtr_cnt_r_reg[2] ,\n act_this_rank,\n \\inhbt_act_faw.inhbt_act_faw_r_reg ,\n demand_priority_r_reg,\n demand_priority_r_reg_0,\n \\cmd_pipe_plus.mc_address_reg[10] ,\n \\cmd_pipe_plus.mc_bank_reg[8] ,\n \\cmd_pipe_plus.mc_bank_reg[7] ,\n \\cmd_pipe_plus.mc_bank_reg[6] ,\n \\cmd_pipe_plus.mc_address_reg[44] ,\n \\cmd_pipe_plus.mc_address_reg[43] ,\n \\cmd_pipe_plus.mc_address_reg[42] ,\n \\cmd_pipe_plus.mc_address_reg[41] ,\n \\cmd_pipe_plus.mc_address_reg[39] ,\n \\cmd_pipe_plus.mc_address_reg[38] ,\n \\cmd_pipe_plus.mc_address_reg[37] ,\n \\cmd_pipe_plus.mc_address_reg[36] ,\n \\cmd_pipe_plus.mc_address_reg[35] ,\n \\cmd_pipe_plus.mc_address_reg[34] ,\n \\cmd_pipe_plus.mc_address_reg[33] ,\n \\cmd_pipe_plus.mc_address_reg[32] ,\n \\cmd_pipe_plus.mc_address_reg[31] ,\n \\cmd_pipe_plus.mc_address_reg[30] ,\n \\cmd_pipe_plus.mc_we_n_reg[2] ,\n \\cmd_pipe_plus.mc_cas_n_reg[2]_0 ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[0] ,\n \\generate_maint_cmds.insert_maint_r_lcl_reg ,\n CLK,\n granted_row_ns,\n rnk_config_strobe_ns,\n granted_col_ns,\n granted_pre_ns,\n SR,\n mc_cke_ns,\n rnk_config_valid_r_lcl_reg,\n read_this_rank_r,\n rd_this_rank_r,\n rd_wr_r_lcl_reg,\n rd_wr_r_lcl_reg_0,\n col_wait_r_reg,\n col_wait_r_reg_0,\n rstdiv0_sync_r1_reg_rep__20,\n rstdiv0_sync_r1_reg_rep__21,\n \\rtw_timer.rtw_cnt_r_reg[1]_0 ,\n \\cmd_pipe_plus.mc_data_offset_2_reg[3] ,\n col_rd_wr_r1,\n auto_pre_r_lcl_reg,\n auto_pre_r_lcl_reg_0,\n head_r_lcl_reg,\n head_r_lcl_reg_0,\n maint_zq_r,\n maint_srx_r,\n \\grant_r_reg[1] ,\n row_cmd_wr,\n \\req_bank_r_lcl_reg[2] ,\n \\req_bank_r_lcl_reg[2]_0 ,\n req_row_r,\n act_wait_r_lcl_reg,\n inhbt_act_faw_r,\n ofs_rdy_r,\n ofs_rdy_r_0,\n wr_this_rank_r,\n req_data_buf_addr_r,\n \\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ,\n act_this_rank_r,\n req_periodic_rd_r,\n req_bank_rdy_r,\n req_bank_rdy_r_1,\n \\req_col_r_reg[9] ,\n \\req_col_r_reg[9]_0 ,\n auto_pre_r_lcl_reg_1,\n auto_pre_r_lcl_reg_2);\n output \\cmd_pipe_plus.mc_address_reg[0] ;\n output \\cmd_pipe_plus.mc_cmd_reg[0] ;\n output [0:0]DIC;\n output [4:0]col_data_buf_addr;\n output cke_r;\n output \\rnk_config_strobe_r_reg[0] ;\n output \\periodic_rd_generation.periodic_rd_timer_r_reg[0] ;\n output [1:0]Q;\n output read_this_rank;\n output [1:0]D;\n output granted_col_r_reg;\n output \\rtw_timer.rtw_cnt_r_reg[1] ;\n output [0:0]mc_odt_ns;\n output col_rd_wr;\n output [0:0]mc_data_offset_2_ns;\n output [1:0]\\cmd_pipe_plus.mc_cas_n_reg[2] ;\n output [1:0]\\cmd_pipe_plus.mc_address_reg[0]_0 ;\n output [1:0]mc_cas_n_ns;\n output \\cmd_pipe_plus.mc_cs_n_reg[0] ;\n output [1:0]mc_ras_n_ns;\n output [5:0]\\cmd_pipe_plus.mc_bank_reg[5] ;\n output [21:0]\\cmd_pipe_plus.mc_address_reg[25] ;\n output granted_row_r_reg;\n output granted_col_r_reg_0;\n output granted_col_r_reg_1;\n output override_demand_ns;\n output granted_row_r_reg_0;\n output \\wtr_timer.wtr_cnt_r_reg[2] ;\n output act_this_rank;\n output \\inhbt_act_faw.inhbt_act_faw_r_reg ;\n output demand_priority_r_reg;\n output demand_priority_r_reg_0;\n output \\cmd_pipe_plus.mc_address_reg[10] ;\n output \\cmd_pipe_plus.mc_bank_reg[8] ;\n output \\cmd_pipe_plus.mc_bank_reg[7] ;\n output \\cmd_pipe_plus.mc_bank_reg[6] ;\n output \\cmd_pipe_plus.mc_address_reg[44] ;\n output \\cmd_pipe_plus.mc_address_reg[43] ;\n output \\cmd_pipe_plus.mc_address_reg[42] ;\n output \\cmd_pipe_plus.mc_address_reg[41] ;\n output \\cmd_pipe_plus.mc_address_reg[39] ;\n output \\cmd_pipe_plus.mc_address_reg[38] ;\n output \\cmd_pipe_plus.mc_address_reg[37] ;\n output \\cmd_pipe_plus.mc_address_reg[36] ;\n output \\cmd_pipe_plus.mc_address_reg[35] ;\n output \\cmd_pipe_plus.mc_address_reg[34] ;\n output \\cmd_pipe_plus.mc_address_reg[33] ;\n output \\cmd_pipe_plus.mc_address_reg[32] ;\n output \\cmd_pipe_plus.mc_address_reg[31] ;\n output \\cmd_pipe_plus.mc_address_reg[30] ;\n output \\cmd_pipe_plus.mc_we_n_reg[2] ;\n output \\cmd_pipe_plus.mc_cas_n_reg[2]_0 ;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[0] ;\n input \\generate_maint_cmds.insert_maint_r_lcl_reg ;\n input CLK;\n input granted_row_ns;\n input rnk_config_strobe_ns;\n input granted_col_ns;\n input granted_pre_ns;\n input [0:0]SR;\n input [0:0]mc_cke_ns;\n input rnk_config_valid_r_lcl_reg;\n input read_this_rank_r;\n input [1:0]rd_this_rank_r;\n input rd_wr_r_lcl_reg;\n input rd_wr_r_lcl_reg_0;\n input col_wait_r_reg;\n input col_wait_r_reg_0;\n input rstdiv0_sync_r1_reg_rep__20;\n input rstdiv0_sync_r1_reg_rep__21;\n input [0:0]\\rtw_timer.rtw_cnt_r_reg[1]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_2_reg[3] ;\n input col_rd_wr_r1;\n input auto_pre_r_lcl_reg;\n input auto_pre_r_lcl_reg_0;\n input head_r_lcl_reg;\n input head_r_lcl_reg_0;\n input maint_zq_r;\n input maint_srx_r;\n input \\grant_r_reg[1] ;\n input [0:0]row_cmd_wr;\n input [2:0]\\req_bank_r_lcl_reg[2] ;\n input [2:0]\\req_bank_r_lcl_reg[2]_0 ;\n input [27:0]req_row_r;\n input act_wait_r_lcl_reg;\n input inhbt_act_faw_r;\n input ofs_rdy_r;\n input ofs_rdy_r_0;\n input [1:0]wr_this_rank_r;\n input [9:0]req_data_buf_addr_r;\n input [3:0]\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ;\n input [1:0]act_this_rank_r;\n input [1:0]req_periodic_rd_r;\n input req_bank_rdy_r;\n input req_bank_rdy_r_1;\n input [6:0]\\req_col_r_reg[9] ;\n input [6:0]\\req_col_r_reg[9]_0 ;\n input auto_pre_r_lcl_reg_1;\n input auto_pre_r_lcl_reg_2;\n\n wire CLK;\n wire [1:0]D;\n wire [0:0]DIC;\n wire [1:0]Q;\n wire [0:0]SR;\n wire act_this_rank;\n wire [1:0]act_this_rank_r;\n wire act_wait_r_lcl_reg;\n wire auto_pre_r_lcl_reg;\n wire auto_pre_r_lcl_reg_0;\n wire auto_pre_r_lcl_reg_1;\n wire auto_pre_r_lcl_reg_2;\n wire cke_r;\n wire \\cmd_pipe_plus.mc_address_reg[0] ;\n wire [1:0]\\cmd_pipe_plus.mc_address_reg[0]_0 ;\n wire \\cmd_pipe_plus.mc_address_reg[10] ;\n wire [21:0]\\cmd_pipe_plus.mc_address_reg[25] ;\n wire \\cmd_pipe_plus.mc_address_reg[30] ;\n wire \\cmd_pipe_plus.mc_address_reg[31] ;\n wire \\cmd_pipe_plus.mc_address_reg[32] ;\n wire \\cmd_pipe_plus.mc_address_reg[33] ;\n wire \\cmd_pipe_plus.mc_address_reg[34] ;\n wire \\cmd_pipe_plus.mc_address_reg[35] ;\n wire \\cmd_pipe_plus.mc_address_reg[36] ;\n wire \\cmd_pipe_plus.mc_address_reg[37] ;\n wire \\cmd_pipe_plus.mc_address_reg[38] ;\n wire \\cmd_pipe_plus.mc_address_reg[39] ;\n wire \\cmd_pipe_plus.mc_address_reg[41] ;\n wire \\cmd_pipe_plus.mc_address_reg[42] ;\n wire \\cmd_pipe_plus.mc_address_reg[43] ;\n wire \\cmd_pipe_plus.mc_address_reg[44] ;\n wire [5:0]\\cmd_pipe_plus.mc_bank_reg[5] ;\n wire \\cmd_pipe_plus.mc_bank_reg[6] ;\n wire \\cmd_pipe_plus.mc_bank_reg[7] ;\n wire \\cmd_pipe_plus.mc_bank_reg[8] ;\n wire [1:0]\\cmd_pipe_plus.mc_cas_n_reg[2] ;\n wire \\cmd_pipe_plus.mc_cas_n_reg[2]_0 ;\n wire \\cmd_pipe_plus.mc_cmd_reg[0] ;\n wire \\cmd_pipe_plus.mc_cs_n_reg[0] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[0] ;\n wire \\cmd_pipe_plus.mc_data_offset_2_reg[3] ;\n wire \\cmd_pipe_plus.mc_we_n_reg[2] ;\n wire [4:0]col_data_buf_addr;\n wire [4:4]col_data_buf_addr_r;\n wire col_periodic_rd_r;\n wire col_rd_wr;\n wire col_rd_wr_r1;\n wire col_wait_r_reg;\n wire col_wait_r_reg_0;\n wire [3:0]\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ;\n wire demand_priority_r_reg;\n wire demand_priority_r_reg_0;\n wire \\generate_maint_cmds.insert_maint_r_lcl_reg ;\n wire \\grant_r_reg[1] ;\n wire granted_col_ns;\n wire granted_col_r_reg;\n wire granted_col_r_reg_0;\n wire granted_col_r_reg_1;\n wire granted_pre_ns;\n wire granted_row_ns;\n wire granted_row_r_reg;\n wire granted_row_r_reg_0;\n wire head_r_lcl_reg;\n wire head_r_lcl_reg_0;\n wire \\inhbt_act_faw.inhbt_act_faw_r_reg ;\n wire inhbt_act_faw_r;\n wire maint_srx_r;\n wire maint_zq_r;\n wire [1:0]mc_cas_n_ns;\n wire [0:0]mc_cke_ns;\n wire [0:0]mc_data_offset_2_ns;\n wire [0:0]mc_odt_ns;\n wire [1:0]mc_ras_n_ns;\n wire ofs_rdy_r;\n wire ofs_rdy_r_0;\n wire override_demand_ns;\n wire \\periodic_rd_generation.periodic_rd_timer_r_reg[0] ;\n wire [1:0]rd_this_rank_r;\n wire rd_wr_r_lcl_reg;\n wire rd_wr_r_lcl_reg_0;\n wire read_this_rank;\n wire read_this_rank_r;\n wire [2:0]\\req_bank_r_lcl_reg[2] ;\n wire [2:0]\\req_bank_r_lcl_reg[2]_0 ;\n wire req_bank_rdy_r;\n wire req_bank_rdy_r_1;\n wire [6:0]\\req_col_r_reg[9] ;\n wire [6:0]\\req_col_r_reg[9]_0 ;\n wire [9:0]req_data_buf_addr_r;\n wire [1:0]req_periodic_rd_r;\n wire [27:0]req_row_r;\n wire rnk_config_strobe_ns;\n wire \\rnk_config_strobe_r_reg[0] ;\n wire rnk_config_valid_r_lcl_reg;\n wire [0:0]row_cmd_wr;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire \\rtw_timer.rtw_cnt_r_reg[1] ;\n wire [0:0]\\rtw_timer.rtw_cnt_r_reg[1]_0 ;\n wire [1:0]wr_this_rank_r;\n wire \\wtr_timer.wtr_cnt_r_reg[2] ;\n\n ddr3_ifmig_7series_v4_0_arb_row_col arb_row_col0\n (.CLK(CLK),\n .D(D),\n .DIC(DIC),\n .Q(Q),\n .SR(SR),\n .act_this_rank(act_this_rank),\n .act_this_rank_r(act_this_rank_r),\n .act_wait_r_lcl_reg(act_wait_r_lcl_reg),\n .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg),\n .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_0),\n .auto_pre_r_lcl_reg_1(auto_pre_r_lcl_reg_1),\n .auto_pre_r_lcl_reg_2(auto_pre_r_lcl_reg_2),\n .\\cmd_pipe_plus.mc_address_reg[0] (\\cmd_pipe_plus.mc_address_reg[0] ),\n .\\cmd_pipe_plus.mc_address_reg[0]_0 (\\cmd_pipe_plus.mc_address_reg[0]_0 ),\n .\\cmd_pipe_plus.mc_address_reg[10] (\\cmd_pipe_plus.mc_address_reg[10] ),\n .\\cmd_pipe_plus.mc_address_reg[25] (\\cmd_pipe_plus.mc_address_reg[25] ),\n .\\cmd_pipe_plus.mc_address_reg[30] (\\cmd_pipe_plus.mc_address_reg[30] ),\n .\\cmd_pipe_plus.mc_address_reg[31] (\\cmd_pipe_plus.mc_address_reg[31] ),\n .\\cmd_pipe_plus.mc_address_reg[32] (\\cmd_pipe_plus.mc_address_reg[32] ),\n .\\cmd_pipe_plus.mc_address_reg[33] (\\cmd_pipe_plus.mc_address_reg[33] ),\n .\\cmd_pipe_plus.mc_address_reg[34] (\\cmd_pipe_plus.mc_address_reg[34] ),\n .\\cmd_pipe_plus.mc_address_reg[35] (\\cmd_pipe_plus.mc_address_reg[35] ),\n .\\cmd_pipe_plus.mc_address_reg[36] (\\cmd_pipe_plus.mc_address_reg[36] ),\n .\\cmd_pipe_plus.mc_address_reg[37] (\\cmd_pipe_plus.mc_address_reg[37] ),\n .\\cmd_pipe_plus.mc_address_reg[38] (\\cmd_pipe_plus.mc_address_reg[38] ),\n .\\cmd_pipe_plus.mc_address_reg[39] (\\cmd_pipe_plus.mc_address_reg[39] ),\n .\\cmd_pipe_plus.mc_address_reg[41] (\\cmd_pipe_plus.mc_address_reg[41] ),\n .\\cmd_pipe_plus.mc_address_reg[42] (\\cmd_pipe_plus.mc_address_reg[42] ),\n .\\cmd_pipe_plus.mc_address_reg[43] (\\cmd_pipe_plus.mc_address_reg[43] ),\n .\\cmd_pipe_plus.mc_address_reg[44] (\\cmd_pipe_plus.mc_address_reg[44] ),\n .\\cmd_pipe_plus.mc_bank_reg[5] (\\cmd_pipe_plus.mc_bank_reg[5] ),\n .\\cmd_pipe_plus.mc_bank_reg[6] (\\cmd_pipe_plus.mc_bank_reg[6] ),\n .\\cmd_pipe_plus.mc_bank_reg[7] (\\cmd_pipe_plus.mc_bank_reg[7] ),\n .\\cmd_pipe_plus.mc_bank_reg[8] (\\cmd_pipe_plus.mc_bank_reg[8] ),\n .\\cmd_pipe_plus.mc_cas_n_reg[2] (\\cmd_pipe_plus.mc_cas_n_reg[2] ),\n .\\cmd_pipe_plus.mc_cas_n_reg[2]_0 (\\cmd_pipe_plus.mc_cas_n_reg[2]_0 ),\n .\\cmd_pipe_plus.mc_cmd_reg[0] (\\cmd_pipe_plus.mc_cmd_reg[0] ),\n .\\cmd_pipe_plus.mc_cs_n_reg[0] (\\cmd_pipe_plus.mc_cs_n_reg[0] ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[0] (\\cmd_pipe_plus.mc_data_offset_1_reg[0] ),\n .\\cmd_pipe_plus.mc_data_offset_2_reg[3] (\\cmd_pipe_plus.mc_data_offset_2_reg[3] ),\n .\\cmd_pipe_plus.mc_we_n_reg[2] (\\cmd_pipe_plus.mc_we_n_reg[2] ),\n .col_data_buf_addr(col_data_buf_addr),\n .col_data_buf_addr_r(col_data_buf_addr_r),\n .col_periodic_rd_r(col_periodic_rd_r),\n .col_rd_wr(col_rd_wr),\n .col_rd_wr_r1(col_rd_wr_r1),\n .col_wait_r_reg(col_wait_r_reg),\n .col_wait_r_reg_0(col_wait_r_reg_0),\n .\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] (\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ),\n .demand_priority_r_reg(demand_priority_r_reg),\n .demand_priority_r_reg_0(demand_priority_r_reg_0),\n .\\generate_maint_cmds.insert_maint_r_lcl_reg (\\generate_maint_cmds.insert_maint_r_lcl_reg ),\n .\\grant_r_reg[1] (\\grant_r_reg[1] ),\n .granted_col_ns(granted_col_ns),\n .granted_col_r_reg_0(granted_col_r_reg),\n .granted_col_r_reg_1(granted_col_r_reg_0),\n .granted_col_r_reg_2(granted_col_r_reg_1),\n .granted_pre_ns(granted_pre_ns),\n .granted_row_ns(granted_row_ns),\n .granted_row_r_reg_0(granted_row_r_reg),\n .granted_row_r_reg_1(granted_row_r_reg_0),\n .head_r_lcl_reg(head_r_lcl_reg),\n .head_r_lcl_reg_0(head_r_lcl_reg_0),\n .\\inhbt_act_faw.inhbt_act_faw_r_reg (\\inhbt_act_faw.inhbt_act_faw_r_reg ),\n .inhbt_act_faw_r(inhbt_act_faw_r),\n .maint_srx_r(maint_srx_r),\n .maint_zq_r(maint_zq_r),\n .mc_cas_n_ns(mc_cas_n_ns),\n .mc_data_offset_2_ns(mc_data_offset_2_ns),\n .mc_odt_ns(mc_odt_ns),\n .mc_ras_n_ns(mc_ras_n_ns),\n .ofs_rdy_r(ofs_rdy_r),\n .ofs_rdy_r_0(ofs_rdy_r_0),\n .override_demand_ns(override_demand_ns),\n .\\periodic_rd_generation.periodic_rd_timer_r_reg[0] (\\periodic_rd_generation.periodic_rd_timer_r_reg[0] ),\n .rd_this_rank_r(rd_this_rank_r),\n .rd_wr_r_lcl_reg(rd_wr_r_lcl_reg),\n .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg_0),\n .read_this_rank(read_this_rank),\n .read_this_rank_r(read_this_rank_r),\n .\\req_bank_r_lcl_reg[2] (\\req_bank_r_lcl_reg[2] ),\n .\\req_bank_r_lcl_reg[2]_0 (\\req_bank_r_lcl_reg[2]_0 ),\n .req_bank_rdy_r(req_bank_rdy_r),\n .req_bank_rdy_r_1(req_bank_rdy_r_1),\n .\\req_col_r_reg[9] (\\req_col_r_reg[9] ),\n .\\req_col_r_reg[9]_0 (\\req_col_r_reg[9]_0 ),\n .req_data_buf_addr_r(req_data_buf_addr_r),\n .req_periodic_rd_r(req_periodic_rd_r),\n .req_row_r(req_row_r),\n .rnk_config_strobe_ns(rnk_config_strobe_ns),\n .\\rnk_config_strobe_r_reg[0]_0 (\\rnk_config_strobe_r_reg[0] ),\n .rnk_config_valid_r_lcl_reg_0(rnk_config_valid_r_lcl_reg),\n .row_cmd_wr(row_cmd_wr),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .\\rtw_timer.rtw_cnt_r_reg[1] (\\rtw_timer.rtw_cnt_r_reg[1] ),\n .\\rtw_timer.rtw_cnt_r_reg[1]_0 (\\rtw_timer.rtw_cnt_r_reg[1]_0 ),\n .wr_this_rank_r(wr_this_rank_r),\n .\\wtr_timer.wtr_cnt_r_reg[2] (\\wtr_timer.wtr_cnt_r_reg[2] ));\n ddr3_ifmig_7series_v4_0_arb_select arb_select0\n (.CLK(CLK),\n .DIC(DIC),\n .SR(SR),\n .cke_r(cke_r),\n .col_data_buf_addr(col_data_buf_addr[4]),\n .col_data_buf_addr_r(col_data_buf_addr_r),\n .col_periodic_rd_r(col_periodic_rd_r),\n .mc_cke_ns(mc_cke_ns));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_arb_row_col\" *) \nmodule ddr3_ifmig_7series_v4_0_arb_row_col\n (\\cmd_pipe_plus.mc_address_reg[0] ,\n \\cmd_pipe_plus.mc_cmd_reg[0] ,\n \\rnk_config_strobe_r_reg[0]_0 ,\n \\periodic_rd_generation.periodic_rd_timer_r_reg[0] ,\n Q,\n read_this_rank,\n D,\n granted_col_r_reg_0,\n \\rtw_timer.rtw_cnt_r_reg[1] ,\n mc_odt_ns,\n col_rd_wr,\n mc_data_offset_2_ns,\n \\cmd_pipe_plus.mc_cas_n_reg[2] ,\n \\cmd_pipe_plus.mc_address_reg[0]_0 ,\n mc_cas_n_ns,\n \\cmd_pipe_plus.mc_cs_n_reg[0] ,\n mc_ras_n_ns,\n \\cmd_pipe_plus.mc_bank_reg[5] ,\n \\cmd_pipe_plus.mc_address_reg[25] ,\n granted_row_r_reg_0,\n granted_col_r_reg_1,\n granted_col_r_reg_2,\n override_demand_ns,\n granted_row_r_reg_1,\n \\wtr_timer.wtr_cnt_r_reg[2] ,\n col_data_buf_addr,\n act_this_rank,\n \\inhbt_act_faw.inhbt_act_faw_r_reg ,\n DIC,\n demand_priority_r_reg,\n demand_priority_r_reg_0,\n \\cmd_pipe_plus.mc_address_reg[10] ,\n \\cmd_pipe_plus.mc_bank_reg[8] ,\n \\cmd_pipe_plus.mc_bank_reg[7] ,\n \\cmd_pipe_plus.mc_bank_reg[6] ,\n \\cmd_pipe_plus.mc_address_reg[44] ,\n \\cmd_pipe_plus.mc_address_reg[43] ,\n \\cmd_pipe_plus.mc_address_reg[42] ,\n \\cmd_pipe_plus.mc_address_reg[41] ,\n \\cmd_pipe_plus.mc_address_reg[39] ,\n \\cmd_pipe_plus.mc_address_reg[38] ,\n \\cmd_pipe_plus.mc_address_reg[37] ,\n \\cmd_pipe_plus.mc_address_reg[36] ,\n \\cmd_pipe_plus.mc_address_reg[35] ,\n \\cmd_pipe_plus.mc_address_reg[34] ,\n \\cmd_pipe_plus.mc_address_reg[33] ,\n \\cmd_pipe_plus.mc_address_reg[32] ,\n \\cmd_pipe_plus.mc_address_reg[31] ,\n \\cmd_pipe_plus.mc_address_reg[30] ,\n \\cmd_pipe_plus.mc_we_n_reg[2] ,\n \\cmd_pipe_plus.mc_cas_n_reg[2]_0 ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[0] ,\n \\generate_maint_cmds.insert_maint_r_lcl_reg ,\n CLK,\n granted_row_ns,\n rnk_config_strobe_ns,\n granted_col_ns,\n granted_pre_ns,\n SR,\n rnk_config_valid_r_lcl_reg_0,\n read_this_rank_r,\n rd_this_rank_r,\n rd_wr_r_lcl_reg,\n rd_wr_r_lcl_reg_0,\n col_wait_r_reg,\n col_wait_r_reg_0,\n rstdiv0_sync_r1_reg_rep__20,\n rstdiv0_sync_r1_reg_rep__21,\n \\rtw_timer.rtw_cnt_r_reg[1]_0 ,\n \\cmd_pipe_plus.mc_data_offset_2_reg[3] ,\n col_rd_wr_r1,\n auto_pre_r_lcl_reg,\n auto_pre_r_lcl_reg_0,\n head_r_lcl_reg,\n head_r_lcl_reg_0,\n maint_zq_r,\n maint_srx_r,\n \\grant_r_reg[1] ,\n row_cmd_wr,\n \\req_bank_r_lcl_reg[2] ,\n \\req_bank_r_lcl_reg[2]_0 ,\n req_row_r,\n act_wait_r_lcl_reg,\n inhbt_act_faw_r,\n ofs_rdy_r,\n ofs_rdy_r_0,\n wr_this_rank_r,\n req_data_buf_addr_r,\n col_data_buf_addr_r,\n \\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ,\n act_this_rank_r,\n req_periodic_rd_r,\n col_periodic_rd_r,\n req_bank_rdy_r,\n req_bank_rdy_r_1,\n \\req_col_r_reg[9] ,\n \\req_col_r_reg[9]_0 ,\n auto_pre_r_lcl_reg_1,\n auto_pre_r_lcl_reg_2);\n output \\cmd_pipe_plus.mc_address_reg[0] ;\n output \\cmd_pipe_plus.mc_cmd_reg[0] ;\n output \\rnk_config_strobe_r_reg[0]_0 ;\n output \\periodic_rd_generation.periodic_rd_timer_r_reg[0] ;\n output [1:0]Q;\n output read_this_rank;\n output [1:0]D;\n output granted_col_r_reg_0;\n output \\rtw_timer.rtw_cnt_r_reg[1] ;\n output [0:0]mc_odt_ns;\n output col_rd_wr;\n output [0:0]mc_data_offset_2_ns;\n output [1:0]\\cmd_pipe_plus.mc_cas_n_reg[2] ;\n output [1:0]\\cmd_pipe_plus.mc_address_reg[0]_0 ;\n output [1:0]mc_cas_n_ns;\n output \\cmd_pipe_plus.mc_cs_n_reg[0] ;\n output [1:0]mc_ras_n_ns;\n output [5:0]\\cmd_pipe_plus.mc_bank_reg[5] ;\n output [21:0]\\cmd_pipe_plus.mc_address_reg[25] ;\n output granted_row_r_reg_0;\n output granted_col_r_reg_1;\n output granted_col_r_reg_2;\n output override_demand_ns;\n output granted_row_r_reg_1;\n output \\wtr_timer.wtr_cnt_r_reg[2] ;\n output [4:0]col_data_buf_addr;\n output act_this_rank;\n output \\inhbt_act_faw.inhbt_act_faw_r_reg ;\n output [0:0]DIC;\n output demand_priority_r_reg;\n output demand_priority_r_reg_0;\n output \\cmd_pipe_plus.mc_address_reg[10] ;\n output \\cmd_pipe_plus.mc_bank_reg[8] ;\n output \\cmd_pipe_plus.mc_bank_reg[7] ;\n output \\cmd_pipe_plus.mc_bank_reg[6] ;\n output \\cmd_pipe_plus.mc_address_reg[44] ;\n output \\cmd_pipe_plus.mc_address_reg[43] ;\n output \\cmd_pipe_plus.mc_address_reg[42] ;\n output \\cmd_pipe_plus.mc_address_reg[41] ;\n output \\cmd_pipe_plus.mc_address_reg[39] ;\n output \\cmd_pipe_plus.mc_address_reg[38] ;\n output \\cmd_pipe_plus.mc_address_reg[37] ;\n output \\cmd_pipe_plus.mc_address_reg[36] ;\n output \\cmd_pipe_plus.mc_address_reg[35] ;\n output \\cmd_pipe_plus.mc_address_reg[34] ;\n output \\cmd_pipe_plus.mc_address_reg[33] ;\n output \\cmd_pipe_plus.mc_address_reg[32] ;\n output \\cmd_pipe_plus.mc_address_reg[31] ;\n output \\cmd_pipe_plus.mc_address_reg[30] ;\n output \\cmd_pipe_plus.mc_we_n_reg[2] ;\n output \\cmd_pipe_plus.mc_cas_n_reg[2]_0 ;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[0] ;\n input \\generate_maint_cmds.insert_maint_r_lcl_reg ;\n input CLK;\n input granted_row_ns;\n input rnk_config_strobe_ns;\n input granted_col_ns;\n input granted_pre_ns;\n input [0:0]SR;\n input rnk_config_valid_r_lcl_reg_0;\n input read_this_rank_r;\n input [1:0]rd_this_rank_r;\n input rd_wr_r_lcl_reg;\n input rd_wr_r_lcl_reg_0;\n input col_wait_r_reg;\n input col_wait_r_reg_0;\n input rstdiv0_sync_r1_reg_rep__20;\n input rstdiv0_sync_r1_reg_rep__21;\n input [0:0]\\rtw_timer.rtw_cnt_r_reg[1]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_2_reg[3] ;\n input col_rd_wr_r1;\n input auto_pre_r_lcl_reg;\n input auto_pre_r_lcl_reg_0;\n input head_r_lcl_reg;\n input head_r_lcl_reg_0;\n input maint_zq_r;\n input maint_srx_r;\n input \\grant_r_reg[1] ;\n input [0:0]row_cmd_wr;\n input [2:0]\\req_bank_r_lcl_reg[2] ;\n input [2:0]\\req_bank_r_lcl_reg[2]_0 ;\n input [27:0]req_row_r;\n input act_wait_r_lcl_reg;\n input inhbt_act_faw_r;\n input ofs_rdy_r;\n input ofs_rdy_r_0;\n input [1:0]wr_this_rank_r;\n input [9:0]req_data_buf_addr_r;\n input [0:0]col_data_buf_addr_r;\n input [3:0]\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ;\n input [1:0]act_this_rank_r;\n input [1:0]req_periodic_rd_r;\n input col_periodic_rd_r;\n input req_bank_rdy_r;\n input req_bank_rdy_r_1;\n input [6:0]\\req_col_r_reg[9] ;\n input [6:0]\\req_col_r_reg[9]_0 ;\n input auto_pre_r_lcl_reg_1;\n input auto_pre_r_lcl_reg_2;\n\n wire CLK;\n wire [1:0]D;\n wire [0:0]DIC;\n wire [1:0]Q;\n wire [0:0]SR;\n wire act_this_rank;\n wire [1:0]act_this_rank_r;\n wire act_wait_r_lcl_reg;\n wire auto_pre_r_lcl_reg;\n wire auto_pre_r_lcl_reg_0;\n wire auto_pre_r_lcl_reg_1;\n wire auto_pre_r_lcl_reg_2;\n wire \\cmd_pipe_plus.mc_address_reg[0] ;\n wire [1:0]\\cmd_pipe_plus.mc_address_reg[0]_0 ;\n wire \\cmd_pipe_plus.mc_address_reg[10] ;\n wire [21:0]\\cmd_pipe_plus.mc_address_reg[25] ;\n wire \\cmd_pipe_plus.mc_address_reg[30] ;\n wire \\cmd_pipe_plus.mc_address_reg[31] ;\n wire \\cmd_pipe_plus.mc_address_reg[32] ;\n wire \\cmd_pipe_plus.mc_address_reg[33] ;\n wire \\cmd_pipe_plus.mc_address_reg[34] ;\n wire \\cmd_pipe_plus.mc_address_reg[35] ;\n wire \\cmd_pipe_plus.mc_address_reg[36] ;\n wire \\cmd_pipe_plus.mc_address_reg[37] ;\n wire \\cmd_pipe_plus.mc_address_reg[38] ;\n wire \\cmd_pipe_plus.mc_address_reg[39] ;\n wire \\cmd_pipe_plus.mc_address_reg[41] ;\n wire \\cmd_pipe_plus.mc_address_reg[42] ;\n wire \\cmd_pipe_plus.mc_address_reg[43] ;\n wire \\cmd_pipe_plus.mc_address_reg[44] ;\n wire [5:0]\\cmd_pipe_plus.mc_bank_reg[5] ;\n wire \\cmd_pipe_plus.mc_bank_reg[6] ;\n wire \\cmd_pipe_plus.mc_bank_reg[7] ;\n wire \\cmd_pipe_plus.mc_bank_reg[8] ;\n wire [1:0]\\cmd_pipe_plus.mc_cas_n_reg[2] ;\n wire \\cmd_pipe_plus.mc_cas_n_reg[2]_0 ;\n wire \\cmd_pipe_plus.mc_cmd_reg[0] ;\n wire \\cmd_pipe_plus.mc_cs_n_reg[0] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[0] ;\n wire \\cmd_pipe_plus.mc_data_offset_2_reg[3] ;\n wire \\cmd_pipe_plus.mc_ras_n[0]_i_2_n_0 ;\n wire \\cmd_pipe_plus.mc_we_n_reg[2] ;\n wire [4:0]col_data_buf_addr;\n wire [0:0]col_data_buf_addr_r;\n wire col_periodic_rd_r;\n wire col_rd_wr;\n wire col_rd_wr_r1;\n wire col_wait_r_reg;\n wire col_wait_r_reg_0;\n wire cs_en2;\n wire [3:0]\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ;\n wire demand_priority_r_reg;\n wire demand_priority_r_reg_0;\n wire \\genblk3[1].rnk_config_strobe_r_reg ;\n wire \\genblk3[2].rnk_config_strobe_r_reg ;\n wire \\generate_maint_cmds.insert_maint_r_lcl_reg ;\n wire \\grant_r_reg[1] ;\n wire granted_col_ns;\n wire granted_col_r_reg_0;\n wire granted_col_r_reg_1;\n wire granted_col_r_reg_2;\n wire granted_pre_ns;\n wire granted_row_ns;\n wire granted_row_r_reg_0;\n wire granted_row_r_reg_1;\n wire head_r_lcl_reg;\n wire head_r_lcl_reg_0;\n wire \\inhbt_act_faw.inhbt_act_faw_r_reg ;\n wire inhbt_act_faw_r;\n wire maint_srx_r;\n wire maint_zq_r;\n wire [1:0]mc_cas_n_ns;\n wire [0:0]mc_data_offset_2_ns;\n wire [0:0]mc_odt_ns;\n wire [1:0]mc_ras_n_ns;\n wire ofs_rdy_r;\n wire ofs_rdy_r_0;\n wire override_demand_ns;\n wire \\periodic_rd_generation.periodic_rd_timer_r_reg[0] ;\n wire [1:0]rd_this_rank_r;\n wire rd_wr_r_lcl_reg;\n wire rd_wr_r_lcl_reg_0;\n wire read_this_rank;\n wire read_this_rank_r;\n wire [2:0]\\req_bank_r_lcl_reg[2] ;\n wire [2:0]\\req_bank_r_lcl_reg[2]_0 ;\n wire req_bank_rdy_r;\n wire req_bank_rdy_r_1;\n wire [6:0]\\req_col_r_reg[9] ;\n wire [6:0]\\req_col_r_reg[9]_0 ;\n wire [9:0]req_data_buf_addr_r;\n wire [1:0]req_periodic_rd_r;\n wire [27:0]req_row_r;\n wire rnk_config_strobe;\n wire rnk_config_strobe_ns;\n wire \\rnk_config_strobe_r_reg[0]_0 ;\n wire rnk_config_valid_r_lcl_reg_0;\n wire [0:0]row_cmd_wr;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire \\rtw_timer.rtw_cnt_r_reg[1] ;\n wire [0:0]\\rtw_timer.rtw_cnt_r_reg[1]_0 ;\n wire sent_row;\n wire [1:0]wr_this_rank_r;\n wire \\wtr_timer.wtr_cnt_r_reg[2] ;\n\n (* SOFT_HLUTNM = \"soft_lutpair1048\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\cmd_pipe_plus.mc_cs_n[0]_i_1 \n (.I0(\\cmd_pipe_plus.mc_address_reg[0] ),\n .I1(sent_row),\n .O(\\cmd_pipe_plus.mc_cs_n_reg[0] ));\n LUT1 #(\n .INIT(2'h1)) \n \\cmd_pipe_plus.mc_data_offset[3]_i_1 \n (.I0(\\cmd_pipe_plus.mc_cmd_reg[0] ),\n .O(mc_cas_n_ns[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1048\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\cmd_pipe_plus.mc_ras_n[0]_i_2 \n (.I0(\\cmd_pipe_plus.mc_address_reg[0] ),\n .I1(rstdiv0_sync_r1_reg_rep__21),\n .O(\\cmd_pipe_plus.mc_ras_n[0]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\cmd_pipe_plus.mc_we_n[2]_i_1 \n (.I0(cs_en2),\n .O(mc_ras_n_ns[1]));\n ddr3_ifmig_7series_v4_0_round_robin_arb__parameterized4 col_arb0\n (.CLK(CLK),\n .D(D[1]),\n .DIC(DIC),\n .Q(Q),\n .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg_1),\n .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_2),\n .\\cmd_pipe_plus.mc_address_reg[25] (\\cmd_pipe_plus.mc_address_reg[25] [21:14]),\n .\\cmd_pipe_plus.mc_bank_reg[5] (\\cmd_pipe_plus.mc_bank_reg[5] [5:3]),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[0] (\\cmd_pipe_plus.mc_data_offset_1_reg[0] ),\n .\\cmd_pipe_plus.mc_data_offset_2_reg[3] (\\cmd_pipe_plus.mc_data_offset_2_reg[3] ),\n .col_data_buf_addr(col_data_buf_addr),\n .col_data_buf_addr_r(col_data_buf_addr_r),\n .col_periodic_rd_r(col_periodic_rd_r),\n .col_rd_wr(col_rd_wr),\n .col_rd_wr_r1(col_rd_wr_r1),\n .col_wait_r_reg(col_wait_r_reg),\n .col_wait_r_reg_0(col_wait_r_reg_0),\n .\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] (\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ),\n .demand_priority_r_reg(demand_priority_r_reg),\n .demand_priority_r_reg_0(demand_priority_r_reg_0),\n .\\genblk3[1].rnk_config_strobe_r_reg (\\genblk3[1].rnk_config_strobe_r_reg ),\n .\\genblk3[2].rnk_config_strobe_r_reg (\\genblk3[2].rnk_config_strobe_r_reg ),\n .granted_col_r_reg(granted_col_r_reg_0),\n .granted_col_r_reg_0(granted_col_r_reg_1),\n .granted_col_r_reg_1(granted_col_r_reg_2),\n .granted_col_r_reg_2(\\cmd_pipe_plus.mc_cmd_reg[0] ),\n .mc_data_offset_2_ns(mc_data_offset_2_ns),\n .mc_odt_ns(mc_odt_ns),\n .ofs_rdy_r(ofs_rdy_r),\n .ofs_rdy_r_0(ofs_rdy_r_0),\n .\\periodic_rd_generation.periodic_rd_timer_r_reg[0] (\\periodic_rd_generation.periodic_rd_timer_r_reg[0] ),\n .rd_this_rank_r(rd_this_rank_r),\n .rd_wr_r_lcl_reg(rd_wr_r_lcl_reg),\n .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg_0),\n .read_this_rank(read_this_rank),\n .read_this_rank_r(read_this_rank_r),\n .\\req_bank_r_lcl_reg[2] (\\req_bank_r_lcl_reg[2] ),\n .\\req_bank_r_lcl_reg[2]_0 (\\req_bank_r_lcl_reg[2]_0 ),\n .req_bank_rdy_r(req_bank_rdy_r),\n .req_bank_rdy_r_1(req_bank_rdy_r_1),\n .\\req_col_r_reg[9] (\\req_col_r_reg[9] ),\n .\\req_col_r_reg[9]_0 (\\req_col_r_reg[9]_0 ),\n .req_data_buf_addr_r(req_data_buf_addr_r),\n .req_periodic_rd_r(req_periodic_rd_r),\n .rnk_config_strobe(rnk_config_strobe),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .\\rtw_timer.rtw_cnt_r_reg[1] (\\rtw_timer.rtw_cnt_r_reg[1] ),\n .\\rtw_timer.rtw_cnt_r_reg[1]_0 (\\rtw_timer.rtw_cnt_r_reg[1]_0 ),\n .wr_this_rank_r(wr_this_rank_r),\n .\\wtr_timer.wtr_cnt_r_reg[2] (\\wtr_timer.wtr_cnt_r_reg[2] ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk3[1].rnk_config_strobe_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(rnk_config_strobe),\n .Q(\\genblk3[1].rnk_config_strobe_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\genblk3[2].rnk_config_strobe_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk3[1].rnk_config_strobe_r_reg ),\n .Q(\\genblk3[2].rnk_config_strobe_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n granted_col_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(granted_col_ns),\n .Q(\\cmd_pipe_plus.mc_cmd_reg[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n granted_row_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(granted_row_ns),\n .Q(sent_row),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n insert_maint_r1_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\generate_maint_cmds.insert_maint_r_lcl_reg ),\n .Q(\\cmd_pipe_plus.mc_address_reg[0] ),\n .R(1'b0));\n LUT3 #(\n .INIT(8'hFE)) \n override_demand_r_i_1\n (.I0(\\genblk3[1].rnk_config_strobe_r_reg ),\n .I1(\\genblk3[2].rnk_config_strobe_r_reg ),\n .I2(rnk_config_strobe),\n .O(override_demand_ns));\n FDRE #(\n .INIT(1'b0)) \n \\pre_4_1_1T_arb.granted_pre_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(granted_pre_ns),\n .Q(cs_en2),\n .R(1'b0));\n ddr3_ifmig_7series_v4_0_round_robin_arb__parameterized1 \\pre_4_1_1T_arb.pre_arb0 \n (.CLK(CLK),\n .Q(\\cmd_pipe_plus.mc_cas_n_reg[2] ),\n .act_wait_r_lcl_reg(act_wait_r_lcl_reg),\n .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg),\n .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_0),\n .\\cmd_pipe_plus.mc_address_reg[30] (\\cmd_pipe_plus.mc_address_reg[30] ),\n .\\cmd_pipe_plus.mc_address_reg[31] (\\cmd_pipe_plus.mc_address_reg[31] ),\n .\\cmd_pipe_plus.mc_address_reg[32] (\\cmd_pipe_plus.mc_address_reg[32] ),\n .\\cmd_pipe_plus.mc_address_reg[33] (\\cmd_pipe_plus.mc_address_reg[33] ),\n .\\cmd_pipe_plus.mc_address_reg[34] (\\cmd_pipe_plus.mc_address_reg[34] ),\n .\\cmd_pipe_plus.mc_address_reg[35] (\\cmd_pipe_plus.mc_address_reg[35] ),\n .\\cmd_pipe_plus.mc_address_reg[36] (\\cmd_pipe_plus.mc_address_reg[36] ),\n .\\cmd_pipe_plus.mc_address_reg[37] (\\cmd_pipe_plus.mc_address_reg[37] ),\n .\\cmd_pipe_plus.mc_address_reg[38] (\\cmd_pipe_plus.mc_address_reg[38] ),\n .\\cmd_pipe_plus.mc_address_reg[39] (\\cmd_pipe_plus.mc_address_reg[39] ),\n .\\cmd_pipe_plus.mc_address_reg[41] (\\cmd_pipe_plus.mc_address_reg[41] ),\n .\\cmd_pipe_plus.mc_address_reg[42] (\\cmd_pipe_plus.mc_address_reg[42] ),\n .\\cmd_pipe_plus.mc_address_reg[43] (\\cmd_pipe_plus.mc_address_reg[43] ),\n .\\cmd_pipe_plus.mc_address_reg[44] (\\cmd_pipe_plus.mc_address_reg[44] ),\n .\\cmd_pipe_plus.mc_bank_reg[6] (\\cmd_pipe_plus.mc_bank_reg[6] ),\n .\\cmd_pipe_plus.mc_bank_reg[7] (\\cmd_pipe_plus.mc_bank_reg[7] ),\n .\\cmd_pipe_plus.mc_bank_reg[8] (\\cmd_pipe_plus.mc_bank_reg[8] ),\n .\\cmd_pipe_plus.mc_cas_n_reg[2] (\\cmd_pipe_plus.mc_cas_n_reg[2]_0 ),\n .\\cmd_pipe_plus.mc_we_n_reg[2] (\\cmd_pipe_plus.mc_we_n_reg[2] ),\n .cs_en2(cs_en2),\n .\\req_bank_r_lcl_reg[2] (\\req_bank_r_lcl_reg[2]_0 ),\n .\\req_bank_r_lcl_reg[2]_0 (\\req_bank_r_lcl_reg[2] ),\n .req_row_r(req_row_r),\n .row_cmd_wr(row_cmd_wr),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21));\n FDRE #(\n .INIT(1'b0)) \n \\rnk_config_strobe_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(rnk_config_strobe_ns),\n .Q(rnk_config_strobe),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n rnk_config_valid_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rnk_config_valid_r_lcl_reg_0),\n .Q(\\rnk_config_strobe_r_reg[0]_0 ),\n .R(SR));\n ddr3_ifmig_7series_v4_0_round_robin_arb__parameterized2 row_arb0\n (.CLK(CLK),\n .D(D[0]),\n .Q(\\cmd_pipe_plus.mc_address_reg[0]_0 ),\n .act_this_rank(act_this_rank),\n .act_this_rank_r(act_this_rank_r),\n .act_wait_r_lcl_reg(act_wait_r_lcl_reg),\n .\\cmd_pipe_plus.mc_address_reg[10] (\\cmd_pipe_plus.mc_address_reg[10] ),\n .\\cmd_pipe_plus.mc_address_reg[14] (\\cmd_pipe_plus.mc_address_reg[25] [13:0]),\n .\\cmd_pipe_plus.mc_bank_reg[2] (\\cmd_pipe_plus.mc_bank_reg[5] [2:0]),\n .\\generate_maint_cmds.insert_maint_r_lcl_reg (\\generate_maint_cmds.insert_maint_r_lcl_reg ),\n .\\grant_r_reg[1]_0 (\\grant_r_reg[1] ),\n .granted_row_r_reg(granted_row_r_reg_0),\n .granted_row_r_reg_0(granted_row_r_reg_1),\n .head_r_lcl_reg(head_r_lcl_reg),\n .head_r_lcl_reg_0(head_r_lcl_reg_0),\n .\\inhbt_act_faw.inhbt_act_faw_r_reg (\\inhbt_act_faw.inhbt_act_faw_r_reg ),\n .inhbt_act_faw_r(inhbt_act_faw_r),\n .insert_maint_r1_lcl_reg(\\cmd_pipe_plus.mc_ras_n[0]_i_2_n_0 ),\n .insert_maint_r1_lcl_reg_0(\\cmd_pipe_plus.mc_cs_n_reg[0] ),\n .insert_maint_r1_lcl_reg_1(\\cmd_pipe_plus.mc_address_reg[0] ),\n .maint_srx_r(maint_srx_r),\n .maint_zq_r(maint_zq_r),\n .mc_cas_n_ns(mc_cas_n_ns[0]),\n .mc_ras_n_ns(mc_ras_n_ns[0]),\n .\\req_bank_r_lcl_reg[2] (\\req_bank_r_lcl_reg[2] ),\n .\\req_bank_r_lcl_reg[2]_0 (\\req_bank_r_lcl_reg[2]_0 ),\n .req_row_r(req_row_r),\n .row_cmd_wr(row_cmd_wr),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .sent_row(sent_row));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_arb_select\" *) \nmodule ddr3_ifmig_7series_v4_0_arb_select\n (col_periodic_rd_r,\n col_data_buf_addr_r,\n cke_r,\n DIC,\n CLK,\n col_data_buf_addr,\n SR,\n mc_cke_ns);\n output col_periodic_rd_r;\n output [0:0]col_data_buf_addr_r;\n output cke_r;\n input [0:0]DIC;\n input CLK;\n input [0:0]col_data_buf_addr;\n input [0:0]SR;\n input [0:0]mc_cke_ns;\n\n wire CLK;\n wire [0:0]DIC;\n wire [0:0]SR;\n wire cke_r;\n wire [0:0]col_data_buf_addr;\n wire [0:0]col_data_buf_addr_r;\n wire col_periodic_rd_r;\n wire [0:0]mc_cke_ns;\n\n FDSE #(\n .INIT(1'b1)) \n cke_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mc_cke_ns),\n .Q(cke_r),\n .S(SR));\n FDRE #(\n .INIT(1'b0)) \n \\col_mux.col_data_buf_addr_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(col_data_buf_addr),\n .Q(col_data_buf_addr_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\col_mux.col_periodic_rd_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(DIC),\n .Q(col_periodic_rd_r),\n .R(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_axi_mc\" *) \nmodule ddr3_ifmig_7series_v4_0_axi_mc\n (s_axi_arready,\n app_en_ns1,\n mc_app_cmd,\n E,\n s_axi_awready,\n s_axi_wready,\n mc_app_wdf_mask_reg,\n D,\n mc_app_wdf_data_reg,\n \\mc_app_wdf_data_reg_reg[255] ,\n out,\n s_axi_rid,\n s_axi_bid,\n s_axi_bvalid,\n w_cmd_rdy,\n \\app_addr_r1_reg[27] ,\n s_axi_rvalid,\n s_axi_rlast,\n app_wdf_mask,\n app_wdf_data,\n mc_app_wdf_wren_reg,\n s_axi_arvalid,\n app_rdy,\n reset_reg,\n app_en_r1,\n CLK,\n app_wdf_rdy,\n app_rd_data_valid,\n Q,\n mc_init_complete,\n s_axi_awlen,\n s_axi_bready,\n s_axi_awvalid,\n s_axi_awaddr,\n s_axi_awburst,\n s_axi_wvalid,\n s_axi_awid,\n s_axi_arlen,\n s_axi_araddr,\n s_axi_arburst,\n s_axi_rready,\n s_axi_wstrb,\n s_axi_wdata,\n aresetn,\n s_axi_arid);\n output s_axi_arready;\n output app_en_ns1;\n output [0:0]mc_app_cmd;\n output [0:0]E;\n output s_axi_awready;\n output s_axi_wready;\n output [31:0]mc_app_wdf_mask_reg;\n output [31:0]D;\n output [255:0]mc_app_wdf_data_reg;\n output [255:0]\\mc_app_wdf_data_reg_reg[255] ;\n output [256:0]out;\n output [0:0]s_axi_rid;\n output [0:0]s_axi_bid;\n output s_axi_bvalid;\n output w_cmd_rdy;\n output [24:0]\\app_addr_r1_reg[27] ;\n output s_axi_rvalid;\n output s_axi_rlast;\n output [31:0]app_wdf_mask;\n output [255:0]app_wdf_data;\n output mc_app_wdf_wren_reg;\n input s_axi_arvalid;\n input app_rdy;\n input reset_reg;\n input app_en_r1;\n input CLK;\n input app_wdf_rdy;\n input app_rd_data_valid;\n input [255:0]Q;\n input mc_init_complete;\n input [7:0]s_axi_awlen;\n input s_axi_bready;\n input s_axi_awvalid;\n input [29:0]s_axi_awaddr;\n input [0:0]s_axi_awburst;\n input s_axi_wvalid;\n input [0:0]s_axi_awid;\n input [7:0]s_axi_arlen;\n input [29:0]s_axi_araddr;\n input [0:0]s_axi_arburst;\n input s_axi_rready;\n input [31:0]s_axi_wstrb;\n input [255:0]s_axi_wdata;\n input aresetn;\n input [0:0]s_axi_arid;\n\n wire CLK;\n wire [31:0]D;\n wire [0:0]E;\n wire [255:0]Q;\n wire [24:0]\\app_addr_r1_reg[27] ;\n wire app_en_ns1;\n wire app_en_r1;\n wire app_rd_data_valid;\n wire app_rdy;\n wire [255:0]app_wdf_data;\n wire [31:0]app_wdf_mask;\n wire app_wdf_rdy;\n wire areset_d1;\n wire aresetn;\n wire awvalid_int;\n wire axi_mc_ar_channel_0_n_29;\n wire axi_mc_aw_channel_0_n_10;\n wire axi_mc_aw_channel_0_n_11;\n wire axi_mc_aw_channel_0_n_12;\n wire axi_mc_aw_channel_0_n_13;\n wire axi_mc_aw_channel_0_n_14;\n wire axi_mc_aw_channel_0_n_15;\n wire axi_mc_aw_channel_0_n_16;\n wire axi_mc_aw_channel_0_n_17;\n wire axi_mc_aw_channel_0_n_18;\n wire axi_mc_aw_channel_0_n_19;\n wire axi_mc_aw_channel_0_n_20;\n wire axi_mc_aw_channel_0_n_21;\n wire axi_mc_aw_channel_0_n_22;\n wire axi_mc_aw_channel_0_n_23;\n wire axi_mc_aw_channel_0_n_24;\n wire axi_mc_aw_channel_0_n_25;\n wire axi_mc_aw_channel_0_n_26;\n wire axi_mc_aw_channel_0_n_27;\n wire axi_mc_aw_channel_0_n_28;\n wire axi_mc_aw_channel_0_n_4;\n wire axi_mc_aw_channel_0_n_5;\n wire axi_mc_aw_channel_0_n_7;\n wire axi_mc_aw_channel_0_n_8;\n wire axi_mc_aw_channel_0_n_9;\n wire axi_mc_cmd_arbiter_0_n_3;\n wire axi_mc_cmd_arbiter_0_n_4;\n wire axi_mc_cmd_arbiter_0_n_5;\n wire axi_mc_cmd_arbiter_0_n_6;\n wire axvalid;\n wire b_awid;\n wire b_push;\n wire [0:0]mc_app_cmd;\n wire [255:0]mc_app_wdf_data_reg;\n wire [255:0]\\mc_app_wdf_data_reg_reg[255] ;\n wire [31:0]mc_app_wdf_mask_reg;\n wire mc_app_wdf_wren_reg;\n wire mc_init_complete;\n wire mc_init_complete_r;\n wire next;\n wire [256:0]out;\n wire p_0_in;\n wire r_arid;\n wire r_push;\n wire r_rlast;\n wire rd_cmd_en;\n wire rd_starve_cnt0;\n wire reset_reg;\n wire [29:0]s_axi_araddr;\n wire [0:0]s_axi_arburst;\n wire [0:0]s_axi_arid;\n wire [7:0]s_axi_arlen;\n wire s_axi_arready;\n wire s_axi_arvalid;\n wire [29:0]s_axi_awaddr;\n wire [0:0]s_axi_awburst;\n wire [0:0]s_axi_awid;\n wire [7:0]s_axi_awlen;\n wire s_axi_awready;\n wire s_axi_awvalid;\n wire [0:0]s_axi_bid;\n wire s_axi_bready;\n wire s_axi_bvalid;\n wire [0:0]s_axi_rid;\n wire s_axi_rlast;\n wire s_axi_rready;\n wire s_axi_rvalid;\n wire [255:0]s_axi_wdata;\n wire s_axi_wready;\n wire [31:0]s_axi_wstrb;\n wire s_axi_wvalid;\n wire w_cmd_rdy;\n wire wr_cmd_en;\n wire wvalid_int;\n\n LUT2 #(\n .INIT(4'h7)) \n areset_d1_i_1\n (.I0(mc_init_complete_r),\n .I1(aresetn),\n .O(p_0_in));\n (* equivalent_register_removal = \"no\" *) \n FDRE #(\n .INIT(1'b0)) \n areset_d1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in),\n .Q(areset_d1),\n .R(1'b0));\n ddr3_ifmig_7series_v4_0_axi_mc_ar_channel axi_mc_ar_channel_0\n (.CLK(CLK),\n .\\RD_PRI_REG_STARVE.rnw_i_reg (mc_app_cmd),\n .\\app_addr_r1_reg[27] ({\\app_addr_r1_reg[27] [24:4],\\app_addr_r1_reg[27] [2:0]}),\n .\\app_addr_r1_reg[6] (axi_mc_ar_channel_0_n_29),\n .areset_d1(areset_d1),\n .\\axaddr_incr_reg[10] (axi_mc_aw_channel_0_n_8),\n .\\axaddr_incr_reg[11] (axi_mc_aw_channel_0_n_9),\n .\\axaddr_incr_reg[12] (axi_mc_aw_channel_0_n_10),\n .\\axaddr_incr_reg[13] (axi_mc_aw_channel_0_n_11),\n .\\axaddr_incr_reg[14] (axi_mc_aw_channel_0_n_12),\n .\\axaddr_incr_reg[15] (axi_mc_aw_channel_0_n_13),\n .\\axaddr_incr_reg[16] (axi_mc_aw_channel_0_n_14),\n .\\axaddr_incr_reg[17] (axi_mc_aw_channel_0_n_15),\n .\\axaddr_incr_reg[18] (axi_mc_aw_channel_0_n_16),\n .\\axaddr_incr_reg[19] (axi_mc_aw_channel_0_n_17),\n .\\axaddr_incr_reg[20] (axi_mc_aw_channel_0_n_18),\n .\\axaddr_incr_reg[21] (axi_mc_aw_channel_0_n_19),\n .\\axaddr_incr_reg[22] (axi_mc_aw_channel_0_n_20),\n .\\axaddr_incr_reg[23] (axi_mc_aw_channel_0_n_21),\n .\\axaddr_incr_reg[24] (axi_mc_aw_channel_0_n_22),\n .\\axaddr_incr_reg[25] (axi_mc_aw_channel_0_n_23),\n .\\axaddr_incr_reg[26] (axi_mc_aw_channel_0_n_24),\n .\\axaddr_incr_reg[27] (axi_mc_aw_channel_0_n_25),\n .\\axaddr_incr_reg[28] (axi_mc_aw_channel_0_n_26),\n .\\axaddr_incr_reg[29] (axi_mc_aw_channel_0_n_27),\n .\\axaddr_incr_reg[5] (axi_mc_aw_channel_0_n_28),\n .\\axaddr_incr_reg[6] (axi_mc_aw_channel_0_n_4),\n .\\axaddr_incr_reg[7] (axi_mc_aw_channel_0_n_5),\n .\\axaddr_incr_reg[9] (axi_mc_aw_channel_0_n_7),\n .axready_reg(axi_mc_cmd_arbiter_0_n_5),\n .axready_reg_0(axi_mc_cmd_arbiter_0_n_6),\n .axvalid(axvalid),\n .in({r_arid,r_rlast}),\n .next(next),\n .r_push(r_push),\n .s_axi_araddr(s_axi_araddr),\n .s_axi_arburst(s_axi_arburst),\n .s_axi_arid(s_axi_arid),\n .s_axi_arlen(s_axi_arlen),\n .s_axi_arready(s_axi_arready),\n .s_axi_arvalid(s_axi_arvalid));\n ddr3_ifmig_7series_v4_0_axi_mc_aw_channel axi_mc_aw_channel_0\n (.CLK(CLK),\n .\\RD_PRI_REG_STARVE.rnw_i_reg (w_cmd_rdy),\n .\\RD_PRI_REG_STARVE.rnw_i_reg_0 (mc_app_cmd),\n .\\app_addr_r1_reg[10] (axi_mc_aw_channel_0_n_10),\n .\\app_addr_r1_reg[11] (axi_mc_aw_channel_0_n_11),\n .\\app_addr_r1_reg[12] (axi_mc_aw_channel_0_n_12),\n .\\app_addr_r1_reg[13] (axi_mc_aw_channel_0_n_13),\n .\\app_addr_r1_reg[14] (axi_mc_aw_channel_0_n_14),\n .\\app_addr_r1_reg[15] (axi_mc_aw_channel_0_n_15),\n .\\app_addr_r1_reg[16] (axi_mc_aw_channel_0_n_16),\n .\\app_addr_r1_reg[17] (axi_mc_aw_channel_0_n_17),\n .\\app_addr_r1_reg[18] (axi_mc_aw_channel_0_n_18),\n .\\app_addr_r1_reg[19] (axi_mc_aw_channel_0_n_19),\n .\\app_addr_r1_reg[20] (axi_mc_aw_channel_0_n_20),\n .\\app_addr_r1_reg[21] (axi_mc_aw_channel_0_n_21),\n .\\app_addr_r1_reg[22] (axi_mc_aw_channel_0_n_22),\n .\\app_addr_r1_reg[23] (axi_mc_aw_channel_0_n_23),\n .\\app_addr_r1_reg[24] (axi_mc_aw_channel_0_n_24),\n .\\app_addr_r1_reg[25] (axi_mc_aw_channel_0_n_25),\n .\\app_addr_r1_reg[26] (axi_mc_aw_channel_0_n_26),\n .\\app_addr_r1_reg[27] (axi_mc_aw_channel_0_n_27),\n .\\app_addr_r1_reg[3] (axi_mc_aw_channel_0_n_28),\n .\\app_addr_r1_reg[4] (axi_mc_aw_channel_0_n_4),\n .\\app_addr_r1_reg[5] (axi_mc_aw_channel_0_n_5),\n .\\app_addr_r1_reg[6] (\\app_addr_r1_reg[27] [3]),\n .\\app_addr_r1_reg[7] (axi_mc_aw_channel_0_n_7),\n .\\app_addr_r1_reg[8] (axi_mc_aw_channel_0_n_8),\n .\\app_addr_r1_reg[9] (axi_mc_aw_channel_0_n_9),\n .areset_d1(areset_d1),\n .awvalid_int(awvalid_int),\n .axready_reg(axi_mc_cmd_arbiter_0_n_3),\n .axready_reg_0(axi_mc_cmd_arbiter_0_n_4),\n .b_awid(b_awid),\n .b_push(b_push),\n .\\int_addr_reg[3] (axi_mc_ar_channel_0_n_29),\n .s_axi_awaddr(s_axi_awaddr),\n .s_axi_awburst(s_axi_awburst),\n .s_axi_awid(s_axi_awid),\n .s_axi_awlen(s_axi_awlen),\n .s_axi_awready(s_axi_awready),\n .s_axi_awvalid(s_axi_awvalid));\n ddr3_ifmig_7series_v4_0_axi_mc_b_channel axi_mc_b_channel_0\n (.CLK(CLK),\n .E(E),\n .\\RD_PRI_REG_STARVE.rnw_i_reg (mc_app_cmd),\n .app_en_ns1(app_en_ns1),\n .app_en_r1(app_en_r1),\n .app_rdy(app_rdy),\n .app_wdf_rdy(app_wdf_rdy),\n .areset_d1(areset_d1),\n .awvalid_int(awvalid_int),\n .b_awid(b_awid),\n .b_push(b_push),\n .rd_cmd_en(rd_cmd_en),\n .reset_reg(reset_reg),\n .s_axi_bid(s_axi_bid),\n .s_axi_bready(s_axi_bready),\n .s_axi_bvalid(s_axi_bvalid),\n .wr_cmd_en(wr_cmd_en),\n .wvalid_int(wvalid_int));\n ddr3_ifmig_7series_v4_0_axi_mc_cmd_arbiter axi_mc_cmd_arbiter_0\n (.CLK(CLK),\n .E(rd_starve_cnt0),\n .\\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 (mc_app_cmd),\n .app_rdy(app_rdy),\n .areset_d1(areset_d1),\n .\\axaddr_incr_reg[29] (axi_mc_cmd_arbiter_0_n_3),\n .\\axaddr_incr_reg[29]_0 (axi_mc_cmd_arbiter_0_n_5),\n .\\axlen_cnt_reg[1] (axi_mc_cmd_arbiter_0_n_4),\n .\\axlen_cnt_reg[1]_0 (axi_mc_cmd_arbiter_0_n_6),\n .axready_reg(s_axi_arready),\n .mc_app_wdf_wren_reg_reg(w_cmd_rdy),\n .next(next),\n .rd_cmd_en(rd_cmd_en),\n .s_axi_arburst(s_axi_arburst),\n .s_axi_arvalid(s_axi_arvalid),\n .s_axi_awburst(s_axi_awburst),\n .s_axi_awready(s_axi_awready),\n .s_axi_awvalid(s_axi_awvalid),\n .wr_cmd_en(wr_cmd_en));\n ddr3_ifmig_7series_v4_0_axi_mc_r_channel axi_mc_r_channel_0\n (.CLK(CLK),\n .E(rd_starve_cnt0),\n .Q(Q),\n .app_rd_data_valid(app_rd_data_valid),\n .app_rdy(app_rdy),\n .areset_d1(areset_d1),\n .axvalid(axvalid),\n .in({r_arid,r_rlast}),\n .out(out),\n .r_push(r_push),\n .rd_cmd_en(rd_cmd_en),\n .s_axi_arready(s_axi_arready),\n .s_axi_arvalid(s_axi_arvalid),\n .s_axi_rid(s_axi_rid),\n .s_axi_rlast(s_axi_rlast),\n .s_axi_rready(s_axi_rready),\n .s_axi_rvalid(s_axi_rvalid));\n ddr3_ifmig_7series_v4_0_axi_mc_w_channel axi_mc_w_channel_0\n (.CLK(CLK),\n .D(D),\n .\\RD_PRI_REG_STARVE.rnw_i_reg (w_cmd_rdy),\n .app_wdf_data(app_wdf_data),\n .app_wdf_mask(app_wdf_mask),\n .app_wdf_rdy(app_wdf_rdy),\n .areset_d1(areset_d1),\n .mc_app_wdf_data_reg(mc_app_wdf_data_reg),\n .\\mc_app_wdf_data_reg_reg[255]_0 (\\mc_app_wdf_data_reg_reg[255] ),\n .mc_app_wdf_mask_reg(mc_app_wdf_mask_reg),\n .mc_app_wdf_wren_reg(mc_app_wdf_wren_reg),\n .s_axi_wdata(s_axi_wdata),\n .s_axi_wready(s_axi_wready),\n .s_axi_wstrb(s_axi_wstrb),\n .s_axi_wvalid(s_axi_wvalid),\n .wvalid_int(wvalid_int));\n FDRE #(\n .INIT(1'b0)) \n mc_init_complete_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mc_init_complete),\n .Q(mc_init_complete_r),\n .R(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_axi_mc_ar_channel\" *) \nmodule ddr3_ifmig_7series_v4_0_axi_mc_ar_channel\n (s_axi_arready,\n r_push,\n in,\n axvalid,\n \\app_addr_r1_reg[27] ,\n \\app_addr_r1_reg[6] ,\n areset_d1,\n CLK,\n next,\n \\axaddr_incr_reg[6] ,\n \\axaddr_incr_reg[7] ,\n \\axaddr_incr_reg[9] ,\n \\axaddr_incr_reg[10] ,\n \\axaddr_incr_reg[11] ,\n \\axaddr_incr_reg[12] ,\n \\axaddr_incr_reg[13] ,\n \\axaddr_incr_reg[14] ,\n \\axaddr_incr_reg[15] ,\n \\axaddr_incr_reg[16] ,\n \\axaddr_incr_reg[17] ,\n \\axaddr_incr_reg[18] ,\n \\axaddr_incr_reg[19] ,\n \\axaddr_incr_reg[20] ,\n \\axaddr_incr_reg[21] ,\n \\axaddr_incr_reg[22] ,\n \\axaddr_incr_reg[23] ,\n \\axaddr_incr_reg[24] ,\n \\axaddr_incr_reg[25] ,\n \\axaddr_incr_reg[26] ,\n \\axaddr_incr_reg[27] ,\n \\axaddr_incr_reg[28] ,\n \\axaddr_incr_reg[29] ,\n \\axaddr_incr_reg[5] ,\n axready_reg,\n s_axi_arlen,\n s_axi_arvalid,\n s_axi_araddr,\n \\RD_PRI_REG_STARVE.rnw_i_reg ,\n axready_reg_0,\n s_axi_arburst,\n s_axi_arid);\n output s_axi_arready;\n output r_push;\n output [1:0]in;\n output axvalid;\n output [23:0]\\app_addr_r1_reg[27] ;\n output \\app_addr_r1_reg[6] ;\n input areset_d1;\n input CLK;\n input next;\n input \\axaddr_incr_reg[6] ;\n input \\axaddr_incr_reg[7] ;\n input \\axaddr_incr_reg[9] ;\n input \\axaddr_incr_reg[10] ;\n input \\axaddr_incr_reg[11] ;\n input \\axaddr_incr_reg[12] ;\n input \\axaddr_incr_reg[13] ;\n input \\axaddr_incr_reg[14] ;\n input \\axaddr_incr_reg[15] ;\n input \\axaddr_incr_reg[16] ;\n input \\axaddr_incr_reg[17] ;\n input \\axaddr_incr_reg[18] ;\n input \\axaddr_incr_reg[19] ;\n input \\axaddr_incr_reg[20] ;\n input \\axaddr_incr_reg[21] ;\n input \\axaddr_incr_reg[22] ;\n input \\axaddr_incr_reg[23] ;\n input \\axaddr_incr_reg[24] ;\n input \\axaddr_incr_reg[25] ;\n input \\axaddr_incr_reg[26] ;\n input \\axaddr_incr_reg[27] ;\n input \\axaddr_incr_reg[28] ;\n input \\axaddr_incr_reg[29] ;\n input \\axaddr_incr_reg[5] ;\n input axready_reg;\n input [7:0]s_axi_arlen;\n input s_axi_arvalid;\n input [29:0]s_axi_araddr;\n input \\RD_PRI_REG_STARVE.rnw_i_reg ;\n input axready_reg_0;\n input [0:0]s_axi_arburst;\n input [0:0]s_axi_arid;\n\n wire CLK;\n wire \\RD_PRI_REG_STARVE.rnw_i_reg ;\n wire [23:0]\\app_addr_r1_reg[27] ;\n wire \\app_addr_r1_reg[6] ;\n wire ar_cmd_fsm_0_n_101;\n wire ar_cmd_fsm_0_n_102;\n wire ar_cmd_fsm_0_n_103;\n wire ar_cmd_fsm_0_n_134;\n wire ar_cmd_fsm_0_n_135;\n wire ar_cmd_fsm_0_n_136;\n wire ar_cmd_fsm_0_n_137;\n wire ar_cmd_fsm_0_n_138;\n wire ar_cmd_fsm_0_n_139;\n wire ar_cmd_fsm_0_n_140;\n wire ar_cmd_fsm_0_n_141;\n wire ar_cmd_fsm_0_n_145;\n wire ar_cmd_fsm_0_n_146;\n wire ar_cmd_fsm_0_n_86;\n wire ar_cmd_fsm_0_n_87;\n wire ar_cmd_fsm_0_n_88;\n wire ar_cmd_fsm_0_n_89;\n wire ar_cmd_fsm_0_n_90;\n wire ar_cmd_fsm_0_n_91;\n wire ar_cmd_fsm_0_n_92;\n wire ar_cmd_fsm_0_n_93;\n wire ar_cmd_fsm_0_n_94;\n wire ar_cmd_fsm_0_n_95;\n wire areset_d1;\n wire arvalid_int;\n wire [29:0]axaddr;\n wire [29:0]axaddr_incr;\n wire \\axaddr_incr_reg[10] ;\n wire \\axaddr_incr_reg[11] ;\n wire \\axaddr_incr_reg[12] ;\n wire \\axaddr_incr_reg[13] ;\n wire \\axaddr_incr_reg[14] ;\n wire \\axaddr_incr_reg[15] ;\n wire \\axaddr_incr_reg[16] ;\n wire \\axaddr_incr_reg[17] ;\n wire \\axaddr_incr_reg[18] ;\n wire \\axaddr_incr_reg[19] ;\n wire \\axaddr_incr_reg[20] ;\n wire \\axaddr_incr_reg[21] ;\n wire \\axaddr_incr_reg[22] ;\n wire \\axaddr_incr_reg[23] ;\n wire \\axaddr_incr_reg[24] ;\n wire \\axaddr_incr_reg[25] ;\n wire \\axaddr_incr_reg[26] ;\n wire \\axaddr_incr_reg[27] ;\n wire \\axaddr_incr_reg[28] ;\n wire \\axaddr_incr_reg[29] ;\n wire \\axaddr_incr_reg[5] ;\n wire \\axaddr_incr_reg[6] ;\n wire \\axaddr_incr_reg[7] ;\n wire \\axaddr_incr_reg[9] ;\n wire [8:5]axaddr_int;\n wire [29:0]axaddr_int__0;\n wire [1:1]axburst;\n wire axi_mc_cmd_translator_0_n_30;\n wire axi_mc_cmd_translator_0_n_31;\n wire axi_mc_cmd_translator_0_n_32;\n wire axi_mc_cmd_translator_0_n_33;\n wire axi_mc_cmd_translator_0_n_34;\n wire axi_mc_cmd_translator_0_n_35;\n wire axi_mc_cmd_translator_0_n_36;\n wire axi_mc_cmd_translator_0_n_37;\n wire axi_mc_cmd_translator_0_n_72;\n wire axi_mc_cmd_translator_0_n_73;\n wire axi_mc_cmd_translator_0_n_74;\n wire axi_mc_cmd_translator_0_n_75;\n wire \\axi_mc_incr_cmd_0/axlen_cnt ;\n wire [29:0]\\axi_mc_incr_cmd_0/p_0_in ;\n wire [3:0]axi_mc_incr_cmd_byte_addr;\n wire [29:4]axi_mc_incr_cmd_byte_addr__0;\n wire \\axi_mc_wrap_cmd_0/axlen_cnt ;\n wire [3:0]\\axi_mc_wrap_cmd_0/int_addr ;\n wire [7:0]axlen;\n wire [3:0]axlen_int;\n wire [7:4]axlen_int__0;\n wire axready_reg;\n wire axready_reg_0;\n wire axvalid;\n wire [1:0]in;\n wire next;\n wire [29:0]p_0_in;\n wire r_push;\n wire [29:0]s_axi_araddr;\n wire [0:0]s_axi_arburst;\n wire [0:0]s_axi_arid;\n wire [7:0]s_axi_arlen;\n wire s_axi_arready;\n wire s_axi_arvalid;\n\n ddr3_ifmig_7series_v4_0_axi_mc_cmd_fsm ar_cmd_fsm_0\n (.CLK(CLK),\n .D({axlen_int__0,axlen_int}),\n .DI(ar_cmd_fsm_0_n_145),\n .E(\\axi_mc_incr_cmd_0/axlen_cnt ),\n .Q({axi_mc_cmd_translator_0_n_30,axi_mc_cmd_translator_0_n_31,axi_mc_cmd_translator_0_n_32,axi_mc_cmd_translator_0_n_33,axi_mc_cmd_translator_0_n_34,axi_mc_cmd_translator_0_n_35,axi_mc_cmd_translator_0_n_36,axi_mc_cmd_translator_0_n_37}),\n .\\RD_PRI_REG_STARVE.rnw_i_reg (\\RD_PRI_REG_STARVE.rnw_i_reg ),\n .S({ar_cmd_fsm_0_n_101,ar_cmd_fsm_0_n_102,ar_cmd_fsm_0_n_103}),\n .\\app_addr_r1_reg[27] (\\app_addr_r1_reg[27] ),\n .\\app_addr_r1_reg[6] (\\app_addr_r1_reg[6] ),\n .areset_d1(areset_d1),\n .arvalid_int(arvalid_int),\n .\\axaddr_incr_reg[10] (\\axaddr_incr_reg[10] ),\n .\\axaddr_incr_reg[11] (\\axaddr_incr_reg[11] ),\n .\\axaddr_incr_reg[12] (\\axaddr_incr_reg[12] ),\n .\\axaddr_incr_reg[13] (\\axaddr_incr_reg[13] ),\n .\\axaddr_incr_reg[14] (\\axaddr_incr_reg[14] ),\n .\\axaddr_incr_reg[15] (\\axaddr_incr_reg[15] ),\n .\\axaddr_incr_reg[16] (\\axaddr_incr_reg[16] ),\n .\\axaddr_incr_reg[17] (\\axaddr_incr_reg[17] ),\n .\\axaddr_incr_reg[18] (\\axaddr_incr_reg[18] ),\n .\\axaddr_incr_reg[19] (\\axaddr_incr_reg[19] ),\n .\\axaddr_incr_reg[20] (\\axaddr_incr_reg[20] ),\n .\\axaddr_incr_reg[21] (\\axaddr_incr_reg[21] ),\n .\\axaddr_incr_reg[22] (\\axaddr_incr_reg[22] ),\n .\\axaddr_incr_reg[23] (\\axaddr_incr_reg[23] ),\n .\\axaddr_incr_reg[24] (\\axaddr_incr_reg[24] ),\n .\\axaddr_incr_reg[25] (\\axaddr_incr_reg[25] ),\n .\\axaddr_incr_reg[26] (\\axaddr_incr_reg[26] ),\n .\\axaddr_incr_reg[27] (\\axaddr_incr_reg[27] ),\n .\\axaddr_incr_reg[28] (\\axaddr_incr_reg[28] ),\n .\\axaddr_incr_reg[29] ({axi_mc_incr_cmd_byte_addr__0[29:8],axi_mc_incr_cmd_byte_addr__0[4]}),\n .\\axaddr_incr_reg[29]_0 (p_0_in),\n .\\axaddr_incr_reg[29]_1 (axaddr_incr),\n .\\axaddr_incr_reg[29]_2 (\\axaddr_incr_reg[29] ),\n .\\axaddr_incr_reg[5] (\\axaddr_incr_reg[5] ),\n .\\axaddr_incr_reg[6] (\\axaddr_incr_reg[6] ),\n .\\axaddr_incr_reg[7] (\\axaddr_incr_reg[7] ),\n .\\axaddr_incr_reg[9] (\\axaddr_incr_reg[9] ),\n .\\axaddr_reg[29] ({axaddr_int__0[29:9],axaddr_int,axaddr_int__0[4:0]}),\n .\\axaddr_reg[29]_0 (axaddr),\n .axburst(axburst),\n .\\axburst_reg[1] (ar_cmd_fsm_0_n_95),\n .\\axid_reg[0] (ar_cmd_fsm_0_n_146),\n .\\axlen_cnt_reg[0] (\\axi_mc_wrap_cmd_0/axlen_cnt ),\n .\\axlen_cnt_reg[3] ({ar_cmd_fsm_0_n_138,ar_cmd_fsm_0_n_139,ar_cmd_fsm_0_n_140,ar_cmd_fsm_0_n_141}),\n .\\axlen_cnt_reg[3]_0 ({axi_mc_cmd_translator_0_n_72,axi_mc_cmd_translator_0_n_73,axi_mc_cmd_translator_0_n_74,axi_mc_cmd_translator_0_n_75}),\n .\\axlen_cnt_reg[7] ({ar_cmd_fsm_0_n_86,ar_cmd_fsm_0_n_87,ar_cmd_fsm_0_n_88,ar_cmd_fsm_0_n_89,ar_cmd_fsm_0_n_90,ar_cmd_fsm_0_n_91,ar_cmd_fsm_0_n_92,ar_cmd_fsm_0_n_93}),\n .\\axlen_reg[7] (axlen),\n .axready_reg_0(axready_reg),\n .axready_reg_1(axready_reg_0),\n .axvalid(axvalid),\n .in(in[1]),\n .in0(axi_mc_incr_cmd_byte_addr),\n .\\int_addr_reg[3] ({ar_cmd_fsm_0_n_134,ar_cmd_fsm_0_n_135,ar_cmd_fsm_0_n_136,ar_cmd_fsm_0_n_137}),\n .\\int_addr_reg[3]_0 (\\axi_mc_wrap_cmd_0/int_addr ),\n .next(next),\n .out(\\axi_mc_incr_cmd_0/p_0_in ),\n .r_rlast_reg(ar_cmd_fsm_0_n_94),\n .s_axi_araddr(s_axi_araddr),\n .s_axi_arburst(s_axi_arburst),\n .s_axi_arid(s_axi_arid),\n .s_axi_arlen(s_axi_arlen),\n .s_axi_arready(s_axi_arready),\n .s_axi_arvalid(s_axi_arvalid));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[0]),\n .Q(axaddr[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[10]),\n .Q(axaddr[10]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[11]),\n .Q(axaddr[11]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[12] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[12]),\n .Q(axaddr[12]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[13] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[13]),\n .Q(axaddr[13]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[14] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[14]),\n .Q(axaddr[14]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[15] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[15]),\n .Q(axaddr[15]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[16] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[16]),\n .Q(axaddr[16]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[17] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[17]),\n .Q(axaddr[17]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[18] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[18]),\n .Q(axaddr[18]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[19] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[19]),\n .Q(axaddr[19]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[1]),\n .Q(axaddr[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[20] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[20]),\n .Q(axaddr[20]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[21] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[21]),\n .Q(axaddr[21]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[22] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[22]),\n .Q(axaddr[22]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[23] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[23]),\n .Q(axaddr[23]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[24] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[24]),\n .Q(axaddr[24]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[25] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[25]),\n .Q(axaddr[25]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[26] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[26]),\n .Q(axaddr[26]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[27] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[27]),\n .Q(axaddr[27]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[28] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[28]),\n .Q(axaddr[28]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[29] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[29]),\n .Q(axaddr[29]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[2]),\n .Q(axaddr[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[3]),\n .Q(axaddr[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[4]),\n .Q(axaddr[4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int[5]),\n .Q(axaddr[5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int[6]),\n .Q(axaddr[6]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int[7]),\n .Q(axaddr[7]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int[8]),\n .Q(axaddr[8]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[9]),\n .Q(axaddr[9]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axburst_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(ar_cmd_fsm_0_n_95),\n .Q(axburst),\n .R(1'b0));\n ddr3_ifmig_7series_v4_0_axi_mc_cmd_translator__parameterized0 axi_mc_cmd_translator_0\n (.CLK(CLK),\n .D({ar_cmd_fsm_0_n_86,ar_cmd_fsm_0_n_87,ar_cmd_fsm_0_n_88,ar_cmd_fsm_0_n_89,ar_cmd_fsm_0_n_90,ar_cmd_fsm_0_n_91,ar_cmd_fsm_0_n_92,ar_cmd_fsm_0_n_93}),\n .DI(ar_cmd_fsm_0_n_145),\n .E(\\axi_mc_incr_cmd_0/axlen_cnt ),\n .Q({axi_mc_cmd_translator_0_n_30,axi_mc_cmd_translator_0_n_31,axi_mc_cmd_translator_0_n_32,axi_mc_cmd_translator_0_n_33,axi_mc_cmd_translator_0_n_34,axi_mc_cmd_translator_0_n_35,axi_mc_cmd_translator_0_n_36,axi_mc_cmd_translator_0_n_37}),\n .S({ar_cmd_fsm_0_n_101,ar_cmd_fsm_0_n_102,ar_cmd_fsm_0_n_103,axi_mc_incr_cmd_byte_addr__0[4]}),\n .\\app_addr_r1_reg[27] (axaddr_incr),\n .\\app_addr_r1_reg[6] (\\axi_mc_wrap_cmd_0/int_addr ),\n .areset_d1(areset_d1),\n .\\axlen_cnt_reg[3] ({axi_mc_cmd_translator_0_n_72,axi_mc_cmd_translator_0_n_73,axi_mc_cmd_translator_0_n_74,axi_mc_cmd_translator_0_n_75}),\n .\\axlen_cnt_reg[3]_0 ({ar_cmd_fsm_0_n_138,ar_cmd_fsm_0_n_139,ar_cmd_fsm_0_n_140,ar_cmd_fsm_0_n_141}),\n .axready_reg(axi_mc_incr_cmd_byte_addr__0[29:8]),\n .axready_reg_0(p_0_in),\n .axready_reg_1(\\axi_mc_wrap_cmd_0/axlen_cnt ),\n .axready_reg_2({ar_cmd_fsm_0_n_134,ar_cmd_fsm_0_n_135,ar_cmd_fsm_0_n_136,ar_cmd_fsm_0_n_137}),\n .in0(axi_mc_incr_cmd_byte_addr),\n .out(\\axi_mc_incr_cmd_0/p_0_in ));\n FDRE #(\n .INIT(1'b0)) \n \\axid_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(ar_cmd_fsm_0_n_146),\n .Q(in[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axlen_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(axlen_int[0]),\n .Q(axlen[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axlen_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(axlen_int[1]),\n .Q(axlen[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axlen_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(axlen_int[2]),\n .Q(axlen[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axlen_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(axlen_int[3]),\n .Q(axlen[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axlen_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(axlen_int__0[4]),\n .Q(axlen[4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axlen_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(axlen_int__0[5]),\n .Q(axlen[5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axlen_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(axlen_int__0[6]),\n .Q(axlen[6]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axlen_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(axlen_int__0[7]),\n .Q(axlen[7]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n axvalid_reg\n (.C(CLK),\n .CE(1'b1),\n .D(arvalid_int),\n .Q(axvalid),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n r_push_reg\n (.C(CLK),\n .CE(1'b1),\n .D(next),\n .Q(r_push),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n r_rlast_reg\n (.C(CLK),\n .CE(1'b1),\n .D(ar_cmd_fsm_0_n_94),\n .Q(in[0]),\n .R(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_axi_mc_aw_channel\" *) \nmodule ddr3_ifmig_7series_v4_0_axi_mc_aw_channel\n (s_axi_awready,\n awvalid_int,\n b_awid,\n b_push,\n \\app_addr_r1_reg[4] ,\n \\app_addr_r1_reg[5] ,\n \\app_addr_r1_reg[6] ,\n \\app_addr_r1_reg[7] ,\n \\app_addr_r1_reg[8] ,\n \\app_addr_r1_reg[9] ,\n \\app_addr_r1_reg[10] ,\n \\app_addr_r1_reg[11] ,\n \\app_addr_r1_reg[12] ,\n \\app_addr_r1_reg[13] ,\n \\app_addr_r1_reg[14] ,\n \\app_addr_r1_reg[15] ,\n \\app_addr_r1_reg[16] ,\n \\app_addr_r1_reg[17] ,\n \\app_addr_r1_reg[18] ,\n \\app_addr_r1_reg[19] ,\n \\app_addr_r1_reg[20] ,\n \\app_addr_r1_reg[21] ,\n \\app_addr_r1_reg[22] ,\n \\app_addr_r1_reg[23] ,\n \\app_addr_r1_reg[24] ,\n \\app_addr_r1_reg[25] ,\n \\app_addr_r1_reg[26] ,\n \\app_addr_r1_reg[27] ,\n \\app_addr_r1_reg[3] ,\n areset_d1,\n CLK,\n axready_reg,\n s_axi_awlen,\n s_axi_awvalid,\n \\RD_PRI_REG_STARVE.rnw_i_reg ,\n s_axi_awaddr,\n \\int_addr_reg[3] ,\n axready_reg_0,\n s_axi_awburst,\n \\RD_PRI_REG_STARVE.rnw_i_reg_0 ,\n s_axi_awid);\n output s_axi_awready;\n output awvalid_int;\n output b_awid;\n output b_push;\n output \\app_addr_r1_reg[4] ;\n output \\app_addr_r1_reg[5] ;\n output [0:0]\\app_addr_r1_reg[6] ;\n output \\app_addr_r1_reg[7] ;\n output \\app_addr_r1_reg[8] ;\n output \\app_addr_r1_reg[9] ;\n output \\app_addr_r1_reg[10] ;\n output \\app_addr_r1_reg[11] ;\n output \\app_addr_r1_reg[12] ;\n output \\app_addr_r1_reg[13] ;\n output \\app_addr_r1_reg[14] ;\n output \\app_addr_r1_reg[15] ;\n output \\app_addr_r1_reg[16] ;\n output \\app_addr_r1_reg[17] ;\n output \\app_addr_r1_reg[18] ;\n output \\app_addr_r1_reg[19] ;\n output \\app_addr_r1_reg[20] ;\n output \\app_addr_r1_reg[21] ;\n output \\app_addr_r1_reg[22] ;\n output \\app_addr_r1_reg[23] ;\n output \\app_addr_r1_reg[24] ;\n output \\app_addr_r1_reg[25] ;\n output \\app_addr_r1_reg[26] ;\n output \\app_addr_r1_reg[27] ;\n output \\app_addr_r1_reg[3] ;\n input areset_d1;\n input CLK;\n input axready_reg;\n input [7:0]s_axi_awlen;\n input s_axi_awvalid;\n input \\RD_PRI_REG_STARVE.rnw_i_reg ;\n input [29:0]s_axi_awaddr;\n input \\int_addr_reg[3] ;\n input axready_reg_0;\n input [0:0]s_axi_awburst;\n input \\RD_PRI_REG_STARVE.rnw_i_reg_0 ;\n input [0:0]s_axi_awid;\n\n wire CLK;\n wire \\RD_PRI_REG_STARVE.rnw_i_reg ;\n wire \\RD_PRI_REG_STARVE.rnw_i_reg_0 ;\n wire \\app_addr_r1_reg[10] ;\n wire \\app_addr_r1_reg[11] ;\n wire \\app_addr_r1_reg[12] ;\n wire \\app_addr_r1_reg[13] ;\n wire \\app_addr_r1_reg[14] ;\n wire \\app_addr_r1_reg[15] ;\n wire \\app_addr_r1_reg[16] ;\n wire \\app_addr_r1_reg[17] ;\n wire \\app_addr_r1_reg[18] ;\n wire \\app_addr_r1_reg[19] ;\n wire \\app_addr_r1_reg[20] ;\n wire \\app_addr_r1_reg[21] ;\n wire \\app_addr_r1_reg[22] ;\n wire \\app_addr_r1_reg[23] ;\n wire \\app_addr_r1_reg[24] ;\n wire \\app_addr_r1_reg[25] ;\n wire \\app_addr_r1_reg[26] ;\n wire \\app_addr_r1_reg[27] ;\n wire \\app_addr_r1_reg[3] ;\n wire \\app_addr_r1_reg[4] ;\n wire \\app_addr_r1_reg[5] ;\n wire [0:0]\\app_addr_r1_reg[6] ;\n wire \\app_addr_r1_reg[7] ;\n wire \\app_addr_r1_reg[8] ;\n wire \\app_addr_r1_reg[9] ;\n wire areset_d1;\n wire aw_cmd_fsm_0_n_10;\n wire aw_cmd_fsm_0_n_102;\n wire aw_cmd_fsm_0_n_11;\n wire aw_cmd_fsm_0_n_12;\n wire aw_cmd_fsm_0_n_134;\n wire aw_cmd_fsm_0_n_135;\n wire aw_cmd_fsm_0_n_136;\n wire aw_cmd_fsm_0_n_137;\n wire aw_cmd_fsm_0_n_138;\n wire aw_cmd_fsm_0_n_139;\n wire aw_cmd_fsm_0_n_14;\n wire aw_cmd_fsm_0_n_140;\n wire aw_cmd_fsm_0_n_141;\n wire aw_cmd_fsm_0_n_146;\n wire aw_cmd_fsm_0_n_5;\n wire aw_cmd_fsm_0_n_6;\n wire aw_cmd_fsm_0_n_7;\n wire aw_cmd_fsm_0_n_8;\n wire aw_cmd_fsm_0_n_9;\n wire awvalid_int;\n wire [29:0]axaddr;\n wire [29:0]axaddr_incr;\n wire [8:5]axaddr_int;\n wire [29:0]axaddr_int__0;\n wire [1:1]axburst;\n wire axi_mc_cmd_translator_0_n_30;\n wire axi_mc_cmd_translator_0_n_31;\n wire axi_mc_cmd_translator_0_n_32;\n wire axi_mc_cmd_translator_0_n_33;\n wire axi_mc_cmd_translator_0_n_34;\n wire axi_mc_cmd_translator_0_n_35;\n wire axi_mc_cmd_translator_0_n_36;\n wire axi_mc_cmd_translator_0_n_37;\n wire axi_mc_cmd_translator_0_n_72;\n wire axi_mc_cmd_translator_0_n_73;\n wire axi_mc_cmd_translator_0_n_74;\n wire axi_mc_cmd_translator_0_n_75;\n wire \\axi_mc_incr_cmd_0/axlen_cnt ;\n wire [29:0]\\axi_mc_incr_cmd_0/p_0_in ;\n wire [3:0]axi_mc_incr_cmd_byte_addr;\n wire [29:4]axi_mc_incr_cmd_byte_addr__0;\n wire \\axi_mc_wrap_cmd_0/axlen_cnt ;\n wire [3:0]\\axi_mc_wrap_cmd_0/int_addr ;\n wire axid;\n wire [7:0]axlen;\n wire [3:0]axlen_int;\n wire [7:4]axlen_int__0;\n wire axready_reg;\n wire axready_reg_0;\n wire axvalid;\n wire b_awid;\n wire b_push;\n wire \\int_addr_reg[3] ;\n wire [29:0]p_0_in;\n wire [29:0]s_axi_awaddr;\n wire [0:0]s_axi_awburst;\n wire [0:0]s_axi_awid;\n wire [7:0]s_axi_awlen;\n wire s_axi_awready;\n wire s_axi_awvalid;\n\n ddr3_ifmig_7series_v4_0_axi_mc_wr_cmd_fsm aw_cmd_fsm_0\n (.CLK(CLK),\n .D({aw_cmd_fsm_0_n_5,aw_cmd_fsm_0_n_6,aw_cmd_fsm_0_n_7,aw_cmd_fsm_0_n_8,aw_cmd_fsm_0_n_9,aw_cmd_fsm_0_n_10,aw_cmd_fsm_0_n_11,aw_cmd_fsm_0_n_12}),\n .E(\\axi_mc_incr_cmd_0/axlen_cnt ),\n .Q({axi_mc_cmd_translator_0_n_30,axi_mc_cmd_translator_0_n_31,axi_mc_cmd_translator_0_n_32,axi_mc_cmd_translator_0_n_33,axi_mc_cmd_translator_0_n_34,axi_mc_cmd_translator_0_n_35,axi_mc_cmd_translator_0_n_36,axi_mc_cmd_translator_0_n_37}),\n .\\RD_PRI_REG_STARVE.rnw_i_reg (\\RD_PRI_REG_STARVE.rnw_i_reg ),\n .\\RD_PRI_REG_STARVE.rnw_i_reg_0 (\\RD_PRI_REG_STARVE.rnw_i_reg_0 ),\n .S(aw_cmd_fsm_0_n_102),\n .\\app_addr_r1_reg[10] (\\app_addr_r1_reg[10] ),\n .\\app_addr_r1_reg[11] (\\app_addr_r1_reg[11] ),\n .\\app_addr_r1_reg[12] (\\app_addr_r1_reg[12] ),\n .\\app_addr_r1_reg[13] (\\app_addr_r1_reg[13] ),\n .\\app_addr_r1_reg[14] (\\app_addr_r1_reg[14] ),\n .\\app_addr_r1_reg[15] (\\app_addr_r1_reg[15] ),\n .\\app_addr_r1_reg[16] (\\app_addr_r1_reg[16] ),\n .\\app_addr_r1_reg[17] (\\app_addr_r1_reg[17] ),\n .\\app_addr_r1_reg[18] (\\app_addr_r1_reg[18] ),\n .\\app_addr_r1_reg[19] (\\app_addr_r1_reg[19] ),\n .\\app_addr_r1_reg[20] (\\app_addr_r1_reg[20] ),\n .\\app_addr_r1_reg[21] (\\app_addr_r1_reg[21] ),\n .\\app_addr_r1_reg[22] (\\app_addr_r1_reg[22] ),\n .\\app_addr_r1_reg[23] (\\app_addr_r1_reg[23] ),\n .\\app_addr_r1_reg[24] (\\app_addr_r1_reg[24] ),\n .\\app_addr_r1_reg[25] (\\app_addr_r1_reg[25] ),\n .\\app_addr_r1_reg[26] (\\app_addr_r1_reg[26] ),\n .\\app_addr_r1_reg[27] (\\app_addr_r1_reg[27] ),\n .\\app_addr_r1_reg[3] (\\app_addr_r1_reg[3] ),\n .\\app_addr_r1_reg[4] (\\app_addr_r1_reg[4] ),\n .\\app_addr_r1_reg[5] (\\app_addr_r1_reg[5] ),\n .\\app_addr_r1_reg[6] (\\app_addr_r1_reg[6] ),\n .\\app_addr_r1_reg[7] (\\app_addr_r1_reg[7] ),\n .\\app_addr_r1_reg[8] (\\app_addr_r1_reg[8] ),\n .\\app_addr_r1_reg[9] (\\app_addr_r1_reg[9] ),\n .areset_d1(areset_d1),\n .awvalid_int(awvalid_int),\n .\\axaddr_incr_reg[11] (aw_cmd_fsm_0_n_146),\n .\\axaddr_incr_reg[29] ({axi_mc_incr_cmd_byte_addr__0[29:9],axi_mc_incr_cmd_byte_addr__0[7:4]}),\n .\\axaddr_incr_reg[29]_0 (p_0_in),\n .\\axaddr_incr_reg[29]_1 (axaddr_incr),\n .\\axaddr_reg[29] ({axaddr_int__0[29:9],axaddr_int,axaddr_int__0[4:0]}),\n .\\axaddr_reg[29]_0 (axaddr),\n .axburst(axburst),\n .\\axburst_reg[1] (aw_cmd_fsm_0_n_14),\n .axid(axid),\n .\\axlen_cnt_reg[0] (\\axi_mc_wrap_cmd_0/axlen_cnt ),\n .\\axlen_cnt_reg[3] ({aw_cmd_fsm_0_n_138,aw_cmd_fsm_0_n_139,aw_cmd_fsm_0_n_140,aw_cmd_fsm_0_n_141}),\n .\\axlen_cnt_reg[3]_0 ({axi_mc_cmd_translator_0_n_72,axi_mc_cmd_translator_0_n_73,axi_mc_cmd_translator_0_n_74,axi_mc_cmd_translator_0_n_75}),\n .axlen_int(axlen_int),\n .\\axlen_reg[7] (axlen_int__0),\n .\\axlen_reg[7]_0 (axlen),\n .axready_reg_0(axready_reg),\n .axready_reg_1(axready_reg_0),\n .axvalid(axvalid),\n .b_awid(b_awid),\n .b_push(b_push),\n .in0(axi_mc_incr_cmd_byte_addr),\n .\\int_addr_reg[3] ({aw_cmd_fsm_0_n_134,aw_cmd_fsm_0_n_135,aw_cmd_fsm_0_n_136,aw_cmd_fsm_0_n_137}),\n .\\int_addr_reg[3]_0 (\\int_addr_reg[3] ),\n .\\int_addr_reg[3]_1 (\\axi_mc_wrap_cmd_0/int_addr ),\n .out(\\axi_mc_incr_cmd_0/p_0_in ),\n .s_axi_awaddr(s_axi_awaddr),\n .s_axi_awburst(s_axi_awburst),\n .s_axi_awid(s_axi_awid),\n .s_axi_awlen(s_axi_awlen),\n .s_axi_awready(s_axi_awready),\n .s_axi_awvalid(s_axi_awvalid));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[0]),\n .Q(axaddr[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[10]),\n .Q(axaddr[10]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[11]),\n .Q(axaddr[11]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[12] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[12]),\n .Q(axaddr[12]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[13] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[13]),\n .Q(axaddr[13]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[14] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[14]),\n .Q(axaddr[14]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[15] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[15]),\n .Q(axaddr[15]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[16] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[16]),\n .Q(axaddr[16]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[17] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[17]),\n .Q(axaddr[17]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[18] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[18]),\n .Q(axaddr[18]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[19] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[19]),\n .Q(axaddr[19]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[1]),\n .Q(axaddr[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[20] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[20]),\n .Q(axaddr[20]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[21] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[21]),\n .Q(axaddr[21]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[22] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[22]),\n .Q(axaddr[22]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[23] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[23]),\n .Q(axaddr[23]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[24] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[24]),\n .Q(axaddr[24]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[25] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[25]),\n .Q(axaddr[25]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[26] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[26]),\n .Q(axaddr[26]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[27] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[27]),\n .Q(axaddr[27]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[28] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[28]),\n .Q(axaddr[28]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[29] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[29]),\n .Q(axaddr[29]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[2]),\n .Q(axaddr[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[3]),\n .Q(axaddr[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[4]),\n .Q(axaddr[4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int[5]),\n .Q(axaddr[5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int[6]),\n .Q(axaddr[6]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int[7]),\n .Q(axaddr[7]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int[8]),\n .Q(axaddr[8]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[9]),\n .Q(axaddr[9]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axburst_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(aw_cmd_fsm_0_n_14),\n .Q(axburst),\n .R(1'b0));\n ddr3_ifmig_7series_v4_0_axi_mc_cmd_translator axi_mc_cmd_translator_0\n (.CLK(CLK),\n .D({aw_cmd_fsm_0_n_5,aw_cmd_fsm_0_n_6,aw_cmd_fsm_0_n_7,aw_cmd_fsm_0_n_8,aw_cmd_fsm_0_n_9,aw_cmd_fsm_0_n_10,aw_cmd_fsm_0_n_11,aw_cmd_fsm_0_n_12}),\n .E(\\axi_mc_incr_cmd_0/axlen_cnt ),\n .Q({axi_mc_cmd_translator_0_n_30,axi_mc_cmd_translator_0_n_31,axi_mc_cmd_translator_0_n_32,axi_mc_cmd_translator_0_n_33,axi_mc_cmd_translator_0_n_34,axi_mc_cmd_translator_0_n_35,axi_mc_cmd_translator_0_n_36,axi_mc_cmd_translator_0_n_37}),\n .S(aw_cmd_fsm_0_n_102),\n .\\app_addr_r1_reg[27] (axaddr_incr),\n .areset_d1(areset_d1),\n .\\axlen_cnt_reg[3] ({axi_mc_cmd_translator_0_n_72,axi_mc_cmd_translator_0_n_73,axi_mc_cmd_translator_0_n_74,axi_mc_cmd_translator_0_n_75}),\n .\\axlen_cnt_reg[3]_0 ({aw_cmd_fsm_0_n_138,aw_cmd_fsm_0_n_139,aw_cmd_fsm_0_n_140,aw_cmd_fsm_0_n_141}),\n .axready_reg({axi_mc_incr_cmd_byte_addr__0[29:9],axi_mc_incr_cmd_byte_addr__0[7:4]}),\n .axready_reg_0(aw_cmd_fsm_0_n_146),\n .axready_reg_1(p_0_in),\n .axready_reg_2(\\axi_mc_wrap_cmd_0/axlen_cnt ),\n .axready_reg_3({aw_cmd_fsm_0_n_134,aw_cmd_fsm_0_n_135,aw_cmd_fsm_0_n_136,aw_cmd_fsm_0_n_137}),\n .in0(axi_mc_incr_cmd_byte_addr),\n .\\int_addr_reg[3] (\\axi_mc_wrap_cmd_0/int_addr ),\n .out(\\axi_mc_incr_cmd_0/p_0_in ));\n FDRE #(\n .INIT(1'b0)) \n \\axid_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(b_awid),\n .Q(axid),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axlen_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(axlen_int[0]),\n .Q(axlen[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axlen_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(axlen_int[1]),\n .Q(axlen[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axlen_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(axlen_int[2]),\n .Q(axlen[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axlen_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(axlen_int[3]),\n .Q(axlen[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axlen_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(axlen_int__0[4]),\n .Q(axlen[4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axlen_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(axlen_int__0[5]),\n .Q(axlen[5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axlen_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(axlen_int__0[6]),\n .Q(axlen[6]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\axlen_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(axlen_int__0[7]),\n .Q(axlen[7]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n axvalid_reg\n (.C(CLK),\n .CE(1'b1),\n .D(awvalid_int),\n .Q(axvalid),\n .R(areset_d1));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_axi_mc_b_channel\" *) \nmodule ddr3_ifmig_7series_v4_0_axi_mc_b_channel\n (s_axi_bid,\n s_axi_bvalid,\n app_en_ns1,\n wr_cmd_en,\n E,\n b_push,\n b_awid,\n CLK,\n areset_d1,\n app_rdy,\n \\RD_PRI_REG_STARVE.rnw_i_reg ,\n rd_cmd_en,\n reset_reg,\n app_en_r1,\n s_axi_bready,\n wvalid_int,\n awvalid_int,\n app_wdf_rdy);\n output [0:0]s_axi_bid;\n output s_axi_bvalid;\n output app_en_ns1;\n output wr_cmd_en;\n output [0:0]E;\n input b_push;\n input b_awid;\n input CLK;\n input areset_d1;\n input app_rdy;\n input \\RD_PRI_REG_STARVE.rnw_i_reg ;\n input rd_cmd_en;\n input reset_reg;\n input app_en_r1;\n input s_axi_bready;\n input wvalid_int;\n input awvalid_int;\n input app_wdf_rdy;\n\n wire CLK;\n wire [0:0]E;\n wire \\RD_PRI_REG_STARVE.rnw_i_reg ;\n wire app_en_ns1;\n wire app_en_r1;\n wire app_rdy;\n wire app_wdf_rdy;\n wire areset_d1;\n wire awvalid_int;\n wire b_awid;\n wire b_push;\n wire bhandshake;\n wire bid_fifo_0_n_5;\n wire bid_i;\n wire rd_cmd_en;\n wire reset_reg;\n wire [0:0]s_axi_bid;\n wire s_axi_bready;\n wire s_axi_bvalid;\n wire wr_cmd_en;\n wire wvalid_int;\n\n ddr3_ifmig_7series_v4_0_axi_mc_fifo bid_fifo_0\n (.CLK(CLK),\n .E(E),\n .\\RD_PRI_REG_STARVE.rnw_i_reg (\\RD_PRI_REG_STARVE.rnw_i_reg ),\n .app_en_ns1(app_en_ns1),\n .app_en_r1(app_en_r1),\n .app_rdy(app_rdy),\n .app_wdf_rdy(app_wdf_rdy),\n .areset_d1(areset_d1),\n .awvalid_int(awvalid_int),\n .b_awid(b_awid),\n .b_push(b_push),\n .bhandshake(bhandshake),\n .bid_i(bid_i),\n .bvalid_i_reg(bid_fifo_0_n_5),\n .bvalid_i_reg_0(s_axi_bvalid),\n .rd_cmd_en(rd_cmd_en),\n .reset_reg(reset_reg),\n .s_axi_bready(s_axi_bready),\n .wr_cmd_en(wr_cmd_en),\n .wvalid_int(wvalid_int));\n FDRE #(\n .INIT(1'b0)) \n \\bid_t_reg[0] \n (.C(CLK),\n .CE(bhandshake),\n .D(bid_i),\n .Q(s_axi_bid),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n bvalid_i_reg\n (.C(CLK),\n .CE(1'b1),\n .D(bid_fifo_0_n_5),\n .Q(s_axi_bvalid),\n .R(areset_d1));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_axi_mc_cmd_arbiter\" *) \nmodule ddr3_ifmig_7series_v4_0_axi_mc_cmd_arbiter\n (\\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ,\n mc_app_wdf_wren_reg_reg,\n next,\n \\axaddr_incr_reg[29] ,\n \\axlen_cnt_reg[1] ,\n \\axaddr_incr_reg[29]_0 ,\n \\axlen_cnt_reg[1]_0 ,\n areset_d1,\n CLK,\n rd_cmd_en,\n wr_cmd_en,\n app_rdy,\n s_axi_awburst,\n s_axi_awready,\n s_axi_awvalid,\n s_axi_arburst,\n axready_reg,\n s_axi_arvalid,\n E);\n output \\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ;\n output mc_app_wdf_wren_reg_reg;\n output next;\n output \\axaddr_incr_reg[29] ;\n output \\axlen_cnt_reg[1] ;\n output \\axaddr_incr_reg[29]_0 ;\n output \\axlen_cnt_reg[1]_0 ;\n input areset_d1;\n input CLK;\n input rd_cmd_en;\n input wr_cmd_en;\n input app_rdy;\n input [0:0]s_axi_awburst;\n input s_axi_awready;\n input s_axi_awvalid;\n input [0:0]s_axi_arburst;\n input axready_reg;\n input s_axi_arvalid;\n input [0:0]E;\n\n wire CLK;\n wire [0:0]E;\n wire \\RD_PRI_REG_STARVE.rd_cmd_en_d1_i_1_n_0 ;\n wire \\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 ;\n wire \\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_4_n_0 ;\n wire [8:8]\\RD_PRI_REG_STARVE.rd_starve_cnt_reg__0 ;\n wire \\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ;\n wire \\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[1] ;\n wire \\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[2] ;\n wire \\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[3] ;\n wire \\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[4] ;\n wire \\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[5] ;\n wire \\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[6] ;\n wire \\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[7] ;\n wire \\RD_PRI_REG_STARVE.rnw_i_i_1_n_0 ;\n wire \\RD_PRI_REG_STARVE.wr_cmd_en_d1_i_1_n_0 ;\n wire \\RD_PRI_REG_STARVE.wr_enable_i_1_n_0 ;\n wire \\RD_PRI_REG_STARVE.wr_enable_i_2_n_0 ;\n wire \\RD_PRI_REG_STARVE.wr_enable_i_3_n_0 ;\n wire \\RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_4_n_0 ;\n wire \\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ;\n wire [7:0]\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 ;\n wire app_rdy;\n wire areset_d1;\n wire \\axaddr_incr_reg[29] ;\n wire \\axaddr_incr_reg[29]_0 ;\n wire \\axlen_cnt_reg[1] ;\n wire \\axlen_cnt_reg[1]_0 ;\n wire axready_reg;\n wire mc_app_wdf_wren_reg_reg;\n wire next;\n wire [8:0]p_0_in__0;\n wire [7:0]p_0_in__1;\n wire rd_cmd_en;\n wire rd_cmd_en_d1;\n wire [0:0]s_axi_arburst;\n wire s_axi_arvalid;\n wire [0:0]s_axi_awburst;\n wire s_axi_awready;\n wire s_axi_awvalid;\n wire wr_cmd_en;\n wire wr_cmd_en_d1;\n wire wr_enable;\n wire wr_starve_cnt;\n wire wr_starve_cnt0;\n\n (* SOFT_HLUTNM = \"soft_lutpair1154\" *) \n LUT4 #(\n .INIT(16'h8F80)) \n \\RD_PRI_REG_STARVE.rd_cmd_en_d1_i_1 \n (.I0(rd_cmd_en),\n .I1(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ),\n .I2(app_rdy),\n .I3(rd_cmd_en_d1),\n .O(\\RD_PRI_REG_STARVE.rd_cmd_en_d1_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\RD_PRI_REG_STARVE.rd_cmd_en_d1_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\RD_PRI_REG_STARVE.rd_cmd_en_d1_i_1_n_0 ),\n .Q(rd_cmd_en_d1),\n .R(areset_d1));\n LUT1 #(\n .INIT(2'h1)) \n \\RD_PRI_REG_STARVE.rd_starve_cnt[0]_i_1 \n (.I0(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ),\n .O(p_0_in__0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1158\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\RD_PRI_REG_STARVE.rd_starve_cnt[1]_i_1 \n (.I0(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ),\n .I1(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[1] ),\n .O(p_0_in__0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1158\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\RD_PRI_REG_STARVE.rd_starve_cnt[2]_i_1 \n (.I0(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ),\n .I1(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[1] ),\n .I2(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[2] ),\n .O(p_0_in__0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1151\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\RD_PRI_REG_STARVE.rd_starve_cnt[3]_i_1 \n (.I0(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[1] ),\n .I1(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ),\n .I2(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[2] ),\n .I3(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[3] ),\n .O(p_0_in__0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1151\" *) \n LUT5 #(\n .INIT(32'h7FFF8000)) \n \\RD_PRI_REG_STARVE.rd_starve_cnt[4]_i_1 \n (.I0(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[2] ),\n .I1(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ),\n .I2(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[1] ),\n .I3(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[3] ),\n .I4(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[4] ),\n .O(p_0_in__0[4]));\n LUT6 #(\n .INIT(64'h7FFFFFFF80000000)) \n \\RD_PRI_REG_STARVE.rd_starve_cnt[5]_i_1 \n (.I0(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[3] ),\n .I1(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[1] ),\n .I2(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ),\n .I3(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[2] ),\n .I4(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[4] ),\n .I5(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[5] ),\n .O(p_0_in__0[5]));\n LUT2 #(\n .INIT(4'h6)) \n \\RD_PRI_REG_STARVE.rd_starve_cnt[6]_i_1 \n (.I0(\\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_4_n_0 ),\n .I1(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[6] ),\n .O(p_0_in__0[6]));\n (* SOFT_HLUTNM = \"soft_lutpair1156\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\RD_PRI_REG_STARVE.rd_starve_cnt[7]_i_1 \n (.I0(\\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_4_n_0 ),\n .I1(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[6] ),\n .I2(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[7] ),\n .O(p_0_in__0[7]));\n LUT2 #(\n .INIT(4'hE)) \n \\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1 \n (.I0(areset_d1),\n .I1(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ),\n .O(\\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1156\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_3 \n (.I0(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[6] ),\n .I1(\\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_4_n_0 ),\n .I2(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[7] ),\n .I3(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg__0 ),\n .O(p_0_in__0[8]));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_4 \n (.I0(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[5] ),\n .I1(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[3] ),\n .I2(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[1] ),\n .I3(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ),\n .I4(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[2] ),\n .I5(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[4] ),\n .O(\\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_4_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\RD_PRI_REG_STARVE.rd_starve_cnt_reg[0] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__0[0]),\n .Q(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ),\n .R(\\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\RD_PRI_REG_STARVE.rd_starve_cnt_reg[1] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__0[1]),\n .Q(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[1] ),\n .R(\\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\RD_PRI_REG_STARVE.rd_starve_cnt_reg[2] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__0[2]),\n .Q(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[2] ),\n .R(\\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\RD_PRI_REG_STARVE.rd_starve_cnt_reg[3] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__0[3]),\n .Q(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[3] ),\n .R(\\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\RD_PRI_REG_STARVE.rd_starve_cnt_reg[4] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__0[4]),\n .Q(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[4] ),\n .R(\\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\RD_PRI_REG_STARVE.rd_starve_cnt_reg[5] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__0[5]),\n .Q(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[5] ),\n .R(\\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\RD_PRI_REG_STARVE.rd_starve_cnt_reg[6] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__0[6]),\n .Q(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[6] ),\n .R(\\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\RD_PRI_REG_STARVE.rd_starve_cnt_reg[7] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__0[7]),\n .Q(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[7] ),\n .R(\\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\RD_PRI_REG_STARVE.rd_starve_cnt_reg[8] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__0[8]),\n .Q(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg__0 ),\n .R(\\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h55554445)) \n \\RD_PRI_REG_STARVE.rnw_i_i_1 \n (.I0(wr_enable),\n .I1(rd_cmd_en),\n .I2(wr_cmd_en_d1),\n .I3(wr_cmd_en),\n .I4(rd_cmd_en_d1),\n .O(\\RD_PRI_REG_STARVE.rnw_i_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\RD_PRI_REG_STARVE.rnw_i_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\RD_PRI_REG_STARVE.rnw_i_i_1_n_0 ),\n .Q(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ),\n .S(areset_d1));\n LUT4 #(\n .INIT(16'h2F20)) \n \\RD_PRI_REG_STARVE.wr_cmd_en_d1_i_1 \n (.I0(wr_cmd_en),\n .I1(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ),\n .I2(app_rdy),\n .I3(wr_cmd_en_d1),\n .O(\\RD_PRI_REG_STARVE.wr_cmd_en_d1_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\RD_PRI_REG_STARVE.wr_cmd_en_d1_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\RD_PRI_REG_STARVE.wr_cmd_en_d1_i_1_n_0 ),\n .Q(wr_cmd_en_d1),\n .R(areset_d1));\n LUT5 #(\n .INIT(32'h0000BAAA)) \n \\RD_PRI_REG_STARVE.wr_enable_i_1 \n (.I0(wr_enable),\n .I1(\\RD_PRI_REG_STARVE.wr_enable_i_2_n_0 ),\n .I2(app_rdy),\n .I3(wr_cmd_en),\n .I4(wr_starve_cnt0),\n .O(\\RD_PRI_REG_STARVE.wr_enable_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\RD_PRI_REG_STARVE.wr_enable_i_2 \n (.I0(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [4]),\n .I1(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [5]),\n .I2(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [7]),\n .I3(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [6]),\n .I4(\\RD_PRI_REG_STARVE.wr_enable_i_3_n_0 ),\n .O(\\RD_PRI_REG_STARVE.wr_enable_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1155\" *) \n LUT4 #(\n .INIT(16'h7FFF)) \n \\RD_PRI_REG_STARVE.wr_enable_i_3 \n (.I0(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [3]),\n .I1(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [2]),\n .I2(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [1]),\n .I3(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [0]),\n .O(\\RD_PRI_REG_STARVE.wr_enable_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\RD_PRI_REG_STARVE.wr_enable_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\RD_PRI_REG_STARVE.wr_enable_i_1_n_0 ),\n .Q(wr_enable),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h6)) \n \\RD_PRI_REG_STARVE.wr_starve_cnt[0]_i_1 \n (.I0(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [0]),\n .I1(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ),\n .O(p_0_in__1[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1155\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\RD_PRI_REG_STARVE.wr_starve_cnt[1]_i_1 \n (.I0(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [0]),\n .I1(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ),\n .I2(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [1]),\n .O(p_0_in__1[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1152\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\RD_PRI_REG_STARVE.wr_starve_cnt[2]_i_1 \n (.I0(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ),\n .I1(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [0]),\n .I2(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [1]),\n .I3(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [2]),\n .O(p_0_in__1[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1152\" *) \n LUT5 #(\n .INIT(32'h7FFF8000)) \n \\RD_PRI_REG_STARVE.wr_starve_cnt[3]_i_1 \n (.I0(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [1]),\n .I1(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [0]),\n .I2(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ),\n .I3(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [2]),\n .I4(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [3]),\n .O(p_0_in__1[3]));\n LUT6 #(\n .INIT(64'h7FFFFFFF80000000)) \n \\RD_PRI_REG_STARVE.wr_starve_cnt[4]_i_1 \n (.I0(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [2]),\n .I1(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ),\n .I2(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [0]),\n .I3(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [1]),\n .I4(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [3]),\n .I5(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [4]),\n .O(p_0_in__1[4]));\n LUT2 #(\n .INIT(4'h6)) \n \\RD_PRI_REG_STARVE.wr_starve_cnt[5]_i_1 \n (.I0(\\RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_4_n_0 ),\n .I1(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [5]),\n .O(p_0_in__1[5]));\n (* SOFT_HLUTNM = \"soft_lutpair1157\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\RD_PRI_REG_STARVE.wr_starve_cnt[6]_i_1 \n (.I0(\\RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_4_n_0 ),\n .I1(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [5]),\n .I2(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [6]),\n .O(p_0_in__1[6]));\n LUT4 #(\n .INIT(16'hEEEF)) \n \\RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_1 \n (.I0(areset_d1),\n .I1(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg__0 ),\n .I2(wr_cmd_en_d1),\n .I3(wr_cmd_en),\n .O(wr_starve_cnt0));\n LUT3 #(\n .INIT(8'h80)) \n \\RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_2 \n (.I0(app_rdy),\n .I1(\\RD_PRI_REG_STARVE.wr_enable_i_2_n_0 ),\n .I2(wr_cmd_en),\n .O(wr_starve_cnt));\n (* SOFT_HLUTNM = \"soft_lutpair1157\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_3 \n (.I0(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [5]),\n .I1(\\RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_4_n_0 ),\n .I2(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [6]),\n .I3(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [7]),\n .O(p_0_in__1[7]));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_4 \n (.I0(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [4]),\n .I1(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [2]),\n .I2(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ),\n .I3(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [0]),\n .I4(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [1]),\n .I5(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [3]),\n .O(\\RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_4_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0] \n (.C(CLK),\n .CE(wr_starve_cnt),\n .D(p_0_in__1[0]),\n .Q(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [0]),\n .R(wr_starve_cnt0));\n FDRE #(\n .INIT(1'b0)) \n \\RD_PRI_REG_STARVE.wr_starve_cnt_reg[1] \n (.C(CLK),\n .CE(wr_starve_cnt),\n .D(p_0_in__1[1]),\n .Q(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [1]),\n .R(wr_starve_cnt0));\n FDRE #(\n .INIT(1'b0)) \n \\RD_PRI_REG_STARVE.wr_starve_cnt_reg[2] \n (.C(CLK),\n .CE(wr_starve_cnt),\n .D(p_0_in__1[2]),\n .Q(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [2]),\n .R(wr_starve_cnt0));\n FDRE #(\n .INIT(1'b0)) \n \\RD_PRI_REG_STARVE.wr_starve_cnt_reg[3] \n (.C(CLK),\n .CE(wr_starve_cnt),\n .D(p_0_in__1[3]),\n .Q(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [3]),\n .R(wr_starve_cnt0));\n FDRE #(\n .INIT(1'b0)) \n \\RD_PRI_REG_STARVE.wr_starve_cnt_reg[4] \n (.C(CLK),\n .CE(wr_starve_cnt),\n .D(p_0_in__1[4]),\n .Q(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [4]),\n .R(wr_starve_cnt0));\n FDRE #(\n .INIT(1'b0)) \n \\RD_PRI_REG_STARVE.wr_starve_cnt_reg[5] \n (.C(CLK),\n .CE(wr_starve_cnt),\n .D(p_0_in__1[5]),\n .Q(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [5]),\n .R(wr_starve_cnt0));\n FDRE #(\n .INIT(1'b0)) \n \\RD_PRI_REG_STARVE.wr_starve_cnt_reg[6] \n (.C(CLK),\n .CE(wr_starve_cnt),\n .D(p_0_in__1[6]),\n .Q(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [6]),\n .R(wr_starve_cnt0));\n FDRE #(\n .INIT(1'b0)) \n \\RD_PRI_REG_STARVE.wr_starve_cnt_reg[7] \n (.C(CLK),\n .CE(wr_starve_cnt),\n .D(p_0_in__1[7]),\n .Q(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [7]),\n .R(wr_starve_cnt0));\n LUT4 #(\n .INIT(16'h1000)) \n \\axlen_cnt[7]_i_5 \n (.I0(mc_app_wdf_wren_reg_reg),\n .I1(s_axi_awburst),\n .I2(s_axi_awready),\n .I3(s_axi_awvalid),\n .O(\\axaddr_incr_reg[29] ));\n (* SOFT_HLUTNM = \"soft_lutpair1153\" *) \n LUT4 #(\n .INIT(16'h1000)) \n \\axlen_cnt[7]_i_5__0 \n (.I0(next),\n .I1(s_axi_arburst),\n .I2(axready_reg),\n .I3(s_axi_arvalid),\n .O(\\axaddr_incr_reg[29]_0 ));\n LUT4 #(\n .INIT(16'h4000)) \n \\int_addr[3]_i_3 \n (.I0(mc_app_wdf_wren_reg_reg),\n .I1(s_axi_awburst),\n .I2(s_axi_awready),\n .I3(s_axi_awvalid),\n .O(\\axlen_cnt_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair1153\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\int_addr[3]_i_3__0 \n (.I0(next),\n .I1(s_axi_arburst),\n .I2(axready_reg),\n .I3(s_axi_arvalid),\n .O(\\axlen_cnt_reg[1]_0 ));\n LUT3 #(\n .INIT(8'h40)) \n mc_app_wdf_wren_reg_i_1\n (.I0(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ),\n .I1(app_rdy),\n .I2(wr_cmd_en),\n .O(mc_app_wdf_wren_reg_reg));\n (* SOFT_HLUTNM = \"soft_lutpair1154\" *) \n LUT3 #(\n .INIT(8'h80)) \n r_push_i_1\n (.I0(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ),\n .I1(app_rdy),\n .I2(rd_cmd_en),\n .O(next));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_axi_mc_cmd_fsm\" *) \nmodule ddr3_ifmig_7series_v4_0_axi_mc_cmd_fsm\n (s_axi_arready,\n D,\n \\app_addr_r1_reg[27] ,\n \\axaddr_incr_reg[29] ,\n \\axaddr_reg[29] ,\n \\axlen_cnt_reg[7] ,\n r_rlast_reg,\n \\axburst_reg[1] ,\n in0,\n \\app_addr_r1_reg[6] ,\n S,\n \\axaddr_incr_reg[29]_0 ,\n \\int_addr_reg[3] ,\n \\axlen_cnt_reg[3] ,\n arvalid_int,\n E,\n \\axlen_cnt_reg[0] ,\n DI,\n \\axid_reg[0] ,\n areset_d1,\n CLK,\n Q,\n \\axaddr_incr_reg[6] ,\n \\axaddr_incr_reg[7] ,\n \\axaddr_incr_reg[29]_1 ,\n \\axaddr_incr_reg[9] ,\n \\axaddr_incr_reg[10] ,\n \\axaddr_incr_reg[11] ,\n \\axaddr_incr_reg[12] ,\n \\axaddr_incr_reg[13] ,\n \\axaddr_incr_reg[14] ,\n \\axaddr_incr_reg[15] ,\n \\axaddr_incr_reg[16] ,\n \\axaddr_incr_reg[17] ,\n \\axaddr_incr_reg[18] ,\n \\axaddr_incr_reg[19] ,\n \\axaddr_incr_reg[20] ,\n \\axaddr_incr_reg[21] ,\n \\axaddr_incr_reg[22] ,\n \\axaddr_incr_reg[23] ,\n \\axaddr_incr_reg[24] ,\n \\axaddr_incr_reg[25] ,\n \\axaddr_incr_reg[26] ,\n \\axaddr_incr_reg[27] ,\n \\axaddr_incr_reg[28] ,\n \\axaddr_incr_reg[29]_2 ,\n \\axaddr_incr_reg[5] ,\n axready_reg_0,\n s_axi_arlen,\n \\axlen_reg[7] ,\n next,\n axvalid,\n s_axi_arvalid,\n s_axi_araddr,\n \\axaddr_reg[29]_0 ,\n \\int_addr_reg[3]_0 ,\n \\RD_PRI_REG_STARVE.rnw_i_reg ,\n out,\n axready_reg_1,\n \\axlen_cnt_reg[3]_0 ,\n axburst,\n s_axi_arburst,\n s_axi_arid,\n in);\n output s_axi_arready;\n output [7:0]D;\n output [23:0]\\app_addr_r1_reg[27] ;\n output [22:0]\\axaddr_incr_reg[29] ;\n output [29:0]\\axaddr_reg[29] ;\n output [7:0]\\axlen_cnt_reg[7] ;\n output r_rlast_reg;\n output \\axburst_reg[1] ;\n output [3:0]in0;\n output \\app_addr_r1_reg[6] ;\n output [2:0]S;\n output [29:0]\\axaddr_incr_reg[29]_0 ;\n output [3:0]\\int_addr_reg[3] ;\n output [3:0]\\axlen_cnt_reg[3] ;\n output arvalid_int;\n output [0:0]E;\n output [0:0]\\axlen_cnt_reg[0] ;\n output [0:0]DI;\n output \\axid_reg[0] ;\n input areset_d1;\n input CLK;\n input [7:0]Q;\n input \\axaddr_incr_reg[6] ;\n input \\axaddr_incr_reg[7] ;\n input [29:0]\\axaddr_incr_reg[29]_1 ;\n input \\axaddr_incr_reg[9] ;\n input \\axaddr_incr_reg[10] ;\n input \\axaddr_incr_reg[11] ;\n input \\axaddr_incr_reg[12] ;\n input \\axaddr_incr_reg[13] ;\n input \\axaddr_incr_reg[14] ;\n input \\axaddr_incr_reg[15] ;\n input \\axaddr_incr_reg[16] ;\n input \\axaddr_incr_reg[17] ;\n input \\axaddr_incr_reg[18] ;\n input \\axaddr_incr_reg[19] ;\n input \\axaddr_incr_reg[20] ;\n input \\axaddr_incr_reg[21] ;\n input \\axaddr_incr_reg[22] ;\n input \\axaddr_incr_reg[23] ;\n input \\axaddr_incr_reg[24] ;\n input \\axaddr_incr_reg[25] ;\n input \\axaddr_incr_reg[26] ;\n input \\axaddr_incr_reg[27] ;\n input \\axaddr_incr_reg[28] ;\n input \\axaddr_incr_reg[29]_2 ;\n input \\axaddr_incr_reg[5] ;\n input axready_reg_0;\n input [7:0]s_axi_arlen;\n input [7:0]\\axlen_reg[7] ;\n input next;\n input axvalid;\n input s_axi_arvalid;\n input [29:0]s_axi_araddr;\n input [29:0]\\axaddr_reg[29]_0 ;\n input [3:0]\\int_addr_reg[3]_0 ;\n input \\RD_PRI_REG_STARVE.rnw_i_reg ;\n input [29:0]out;\n input axready_reg_1;\n input [3:0]\\axlen_cnt_reg[3]_0 ;\n input [0:0]axburst;\n input [0:0]s_axi_arburst;\n input [0:0]s_axi_arid;\n input [0:0]in;\n\n wire CLK;\n wire [7:0]D;\n wire [0:0]DI;\n wire [0:0]E;\n wire [7:0]Q;\n wire \\RD_PRI_REG_STARVE.rnw_i_reg ;\n wire [2:0]S;\n wire \\app_addr_r1[27]_i_3_n_0 ;\n wire \\app_addr_r1[27]_i_4_n_0 ;\n wire \\app_addr_r1[6]_i_6_n_0 ;\n wire [23:0]\\app_addr_r1_reg[27] ;\n wire \\app_addr_r1_reg[6] ;\n wire areset_d1;\n wire arvalid_int;\n wire \\axaddr_incr_reg[10] ;\n wire \\axaddr_incr_reg[11] ;\n wire \\axaddr_incr_reg[12] ;\n wire \\axaddr_incr_reg[13] ;\n wire \\axaddr_incr_reg[14] ;\n wire \\axaddr_incr_reg[15] ;\n wire \\axaddr_incr_reg[16] ;\n wire \\axaddr_incr_reg[17] ;\n wire \\axaddr_incr_reg[18] ;\n wire \\axaddr_incr_reg[19] ;\n wire \\axaddr_incr_reg[20] ;\n wire \\axaddr_incr_reg[21] ;\n wire \\axaddr_incr_reg[22] ;\n wire \\axaddr_incr_reg[23] ;\n wire \\axaddr_incr_reg[24] ;\n wire \\axaddr_incr_reg[25] ;\n wire \\axaddr_incr_reg[26] ;\n wire \\axaddr_incr_reg[27] ;\n wire \\axaddr_incr_reg[28] ;\n wire [22:0]\\axaddr_incr_reg[29] ;\n wire [29:0]\\axaddr_incr_reg[29]_0 ;\n wire [29:0]\\axaddr_incr_reg[29]_1 ;\n wire \\axaddr_incr_reg[29]_2 ;\n wire \\axaddr_incr_reg[5] ;\n wire \\axaddr_incr_reg[6] ;\n wire \\axaddr_incr_reg[7] ;\n wire \\axaddr_incr_reg[9] ;\n wire [29:0]\\axaddr_reg[29] ;\n wire [29:0]\\axaddr_reg[29]_0 ;\n wire [0:0]axburst;\n wire \\axburst_reg[1] ;\n wire [3:2]\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/axlen_cnt_t__3 ;\n wire [8:5]\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr ;\n wire \\axi_mc_cmd_translator_0/incr_axhandshake ;\n wire \\axi_mc_cmd_translator_0/wrap_axhandshake ;\n wire [7:5]axi_mc_incr_cmd_byte_addr__0;\n wire \\axid_reg[0] ;\n wire \\axlen_cnt[2]_i_2__1_n_0 ;\n wire \\axlen_cnt[2]_i_2__2_n_0 ;\n wire \\axlen_cnt[3]_i_2__1_n_0 ;\n wire \\axlen_cnt[3]_i_2__2_n_0 ;\n wire \\axlen_cnt[4]_i_2__0_n_0 ;\n wire \\axlen_cnt[4]_i_3__0_n_0 ;\n wire \\axlen_cnt[5]_i_2__0_n_0 ;\n wire \\axlen_cnt[5]_i_3__0_n_0 ;\n wire \\axlen_cnt[7]_i_3__0_n_0 ;\n wire \\axlen_cnt[7]_i_4__0_n_0 ;\n wire [0:0]\\axlen_cnt_reg[0] ;\n wire [3:0]\\axlen_cnt_reg[3] ;\n wire [3:0]\\axlen_cnt_reg[3]_0 ;\n wire [7:0]\\axlen_cnt_reg[7] ;\n wire [7:0]\\axlen_reg[7] ;\n wire axready_i_1__0_n_0;\n wire axready_reg_0;\n wire axready_reg_1;\n wire axvalid;\n wire [0:0]in;\n wire [3:0]in0;\n wire \\int_addr[3]_i_5__0_n_0 ;\n wire [3:0]\\int_addr_reg[3] ;\n wire [3:0]\\int_addr_reg[3]_0 ;\n wire next;\n wire [29:0]out;\n wire r_rlast_i_4_n_0;\n wire r_rlast_i_5_n_0;\n wire r_rlast_i_6_n_0;\n wire r_rlast_reg;\n wire [29:0]s_axi_araddr;\n wire [0:0]s_axi_arburst;\n wire [0:0]s_axi_arid;\n wire [7:0]s_axi_arlen;\n wire s_axi_arready;\n wire s_axi_arvalid;\n\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[10]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [12]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [12]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[12] ),\n .O(\\app_addr_r1_reg[27] [6]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[11]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [13]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [13]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[13] ),\n .O(\\app_addr_r1_reg[27] [7]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[12]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [14]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [14]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[14] ),\n .O(\\app_addr_r1_reg[27] [8]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[13]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [15]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [15]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[15] ),\n .O(\\app_addr_r1_reg[27] [9]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[14]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [16]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [16]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[16] ),\n .O(\\app_addr_r1_reg[27] [10]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[15]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [17]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [17]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[17] ),\n .O(\\app_addr_r1_reg[27] [11]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[16]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [18]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [18]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[18] ),\n .O(\\app_addr_r1_reg[27] [12]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[17]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [19]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [19]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[19] ),\n .O(\\app_addr_r1_reg[27] [13]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[18]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [20]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [20]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[20] ),\n .O(\\app_addr_r1_reg[27] [14]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[19]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [21]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [21]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[21] ),\n .O(\\app_addr_r1_reg[27] [15]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[20]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [22]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [22]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[22] ),\n .O(\\app_addr_r1_reg[27] [16]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[21]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [23]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [23]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[23] ),\n .O(\\app_addr_r1_reg[27] [17]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[22]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [24]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [24]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[24] ),\n .O(\\app_addr_r1_reg[27] [18]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[23]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [25]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [25]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[25] ),\n .O(\\app_addr_r1_reg[27] [19]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[24]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [26]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [26]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[26] ),\n .O(\\app_addr_r1_reg[27] [20]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[25]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [27]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [27]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[27] ),\n .O(\\app_addr_r1_reg[27] [21]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[26]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [28]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [28]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[28] ),\n .O(\\app_addr_r1_reg[27] [22]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[27]_i_2 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [29]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [29]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[29]_2 ),\n .O(\\app_addr_r1_reg[27] [23]));\n (* SOFT_HLUTNM = \"soft_lutpair1124\" *) \n LUT4 #(\n .INIT(16'h02A2)) \n \\app_addr_r1[27]_i_3 \n (.I0(\\RD_PRI_REG_STARVE.rnw_i_reg ),\n .I1(axburst),\n .I2(s_axi_arready),\n .I3(s_axi_arburst),\n .O(\\app_addr_r1[27]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1124\" *) \n LUT4 #(\n .INIT(16'hE200)) \n \\app_addr_r1[27]_i_4 \n (.I0(axburst),\n .I1(s_axi_arready),\n .I2(s_axi_arburst),\n .I3(\\RD_PRI_REG_STARVE.rnw_i_reg ),\n .O(\\app_addr_r1[27]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFF888)) \n \\app_addr_r1[3]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(axi_mc_incr_cmd_byte_addr__0[5]),\n .I2(\\app_addr_r1[27]_i_4_n_0 ),\n .I3(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]),\n .I4(\\axaddr_incr_reg[5] ),\n .O(\\app_addr_r1_reg[27] [0]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_addr_r1[3]_i_2 \n (.I0(s_axi_araddr[5]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [5]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [5]),\n .O(axi_mc_incr_cmd_byte_addr__0[5]));\n LUT5 #(\n .INIT(32'hFFFFF888)) \n \\app_addr_r1[4]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(axi_mc_incr_cmd_byte_addr__0[6]),\n .I2(\\app_addr_r1[27]_i_4_n_0 ),\n .I3(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [6]),\n .I4(\\axaddr_incr_reg[6] ),\n .O(\\app_addr_r1_reg[27] [1]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_addr_r1[4]_i_2 \n (.I0(s_axi_araddr[6]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [6]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [6]),\n .O(axi_mc_incr_cmd_byte_addr__0[6]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_addr_r1[4]_i_3 \n (.I0(s_axi_araddr[6]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [6]),\n .I3(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I4(\\int_addr_reg[3]_0 [1]),\n .O(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [6]));\n LUT5 #(\n .INIT(32'hFFFFF888)) \n \\app_addr_r1[5]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(axi_mc_incr_cmd_byte_addr__0[7]),\n .I2(\\app_addr_r1[27]_i_4_n_0 ),\n .I3(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [7]),\n .I4(\\axaddr_incr_reg[7] ),\n .O(\\app_addr_r1_reg[27] [2]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_addr_r1[5]_i_2 \n (.I0(s_axi_araddr[7]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [7]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [7]),\n .O(axi_mc_incr_cmd_byte_addr__0[7]));\n LUT6 #(\n .INIT(64'hCACFCAC000000000)) \n \\app_addr_r1[6]_i_2 \n (.I0(\\int_addr_reg[3]_0 [3]),\n .I1(\\axaddr_reg[29] [8]),\n .I2(\\app_addr_r1[6]_i_6_n_0 ),\n .I3(\\axburst_reg[1] ),\n .I4(\\axaddr_incr_reg[29]_1 [8]),\n .I5(\\RD_PRI_REG_STARVE.rnw_i_reg ),\n .O(\\app_addr_r1_reg[6] ));\n (* SOFT_HLUTNM = \"soft_lutpair1127\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\app_addr_r1[6]_i_6 \n (.I0(s_axi_arvalid),\n .I1(s_axi_arready),\n .O(\\app_addr_r1[6]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[7]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [9]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [9]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[9] ),\n .O(\\app_addr_r1_reg[27] [3]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[8]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [10]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [10]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[10] ),\n .O(\\app_addr_r1_reg[27] [4]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[9]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [11]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [11]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[11] ),\n .O(\\app_addr_r1_reg[27] [5]));\n (* SOFT_HLUTNM = \"soft_lutpair1092\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[0]_i_1__0 \n (.I0(s_axi_araddr[0]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [0]),\n .O(\\axaddr_reg[29] [0]));\n (* SOFT_HLUTNM = \"soft_lutpair1104\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[10]_i_1__0 \n (.I0(s_axi_araddr[10]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [10]),\n .O(\\axaddr_reg[29] [10]));\n (* SOFT_HLUTNM = \"soft_lutpair1105\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[11]_i_1__0 \n (.I0(s_axi_araddr[11]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [11]),\n .O(\\axaddr_reg[29] [11]));\n (* SOFT_HLUTNM = \"soft_lutpair1106\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[12]_i_1__0 \n (.I0(s_axi_araddr[12]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [12]),\n .O(\\axaddr_reg[29] [12]));\n (* SOFT_HLUTNM = \"soft_lutpair1112\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[13]_i_1__0 \n (.I0(s_axi_araddr[13]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [13]),\n .O(\\axaddr_reg[29] [13]));\n (* SOFT_HLUTNM = \"soft_lutpair1107\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[14]_i_1__0 \n (.I0(s_axi_araddr[14]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [14]),\n .O(\\axaddr_reg[29] [14]));\n (* SOFT_HLUTNM = \"soft_lutpair1109\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[15]_i_1__0 \n (.I0(s_axi_araddr[15]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [15]),\n .O(\\axaddr_reg[29] [15]));\n (* SOFT_HLUTNM = \"soft_lutpair1110\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[16]_i_1__0 \n (.I0(s_axi_araddr[16]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [16]),\n .O(\\axaddr_reg[29] [16]));\n (* SOFT_HLUTNM = \"soft_lutpair1116\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[17]_i_1__0 \n (.I0(s_axi_araddr[17]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [17]),\n .O(\\axaddr_reg[29] [17]));\n (* SOFT_HLUTNM = \"soft_lutpair1111\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[18]_i_1__0 \n (.I0(s_axi_araddr[18]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [18]),\n .O(\\axaddr_reg[29] [18]));\n (* SOFT_HLUTNM = \"soft_lutpair1113\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[19]_i_1__0 \n (.I0(s_axi_araddr[19]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [19]),\n .O(\\axaddr_reg[29] [19]));\n (* SOFT_HLUTNM = \"soft_lutpair1093\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[1]_i_1__0 \n (.I0(s_axi_araddr[1]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [1]),\n .O(\\axaddr_reg[29] [1]));\n (* SOFT_HLUTNM = \"soft_lutpair1114\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[20]_i_1__0 \n (.I0(s_axi_araddr[20]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [20]),\n .O(\\axaddr_reg[29] [20]));\n (* SOFT_HLUTNM = \"soft_lutpair1120\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[21]_i_1__0 \n (.I0(s_axi_araddr[21]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [21]),\n .O(\\axaddr_reg[29] [21]));\n (* SOFT_HLUTNM = \"soft_lutpair1115\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[22]_i_1__0 \n (.I0(s_axi_araddr[22]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [22]),\n .O(\\axaddr_reg[29] [22]));\n (* SOFT_HLUTNM = \"soft_lutpair1117\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[23]_i_1__0 \n (.I0(s_axi_araddr[23]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [23]),\n .O(\\axaddr_reg[29] [23]));\n (* SOFT_HLUTNM = \"soft_lutpair1118\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[24]_i_1__0 \n (.I0(s_axi_araddr[24]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [24]),\n .O(\\axaddr_reg[29] [24]));\n (* SOFT_HLUTNM = \"soft_lutpair1100\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[25]_i_1__0 \n (.I0(s_axi_araddr[25]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [25]),\n .O(\\axaddr_reg[29] [25]));\n (* SOFT_HLUTNM = \"soft_lutpair1119\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[26]_i_1__0 \n (.I0(s_axi_araddr[26]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [26]),\n .O(\\axaddr_reg[29] [26]));\n (* SOFT_HLUTNM = \"soft_lutpair1121\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[27]_i_1__0 \n (.I0(s_axi_araddr[27]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [27]),\n .O(\\axaddr_reg[29] [27]));\n (* SOFT_HLUTNM = \"soft_lutpair1122\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[28]_i_1__0 \n (.I0(s_axi_araddr[28]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [28]),\n .O(\\axaddr_reg[29] [28]));\n (* SOFT_HLUTNM = \"soft_lutpair1123\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[29]_i_1__0 \n (.I0(s_axi_araddr[29]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [29]),\n .O(\\axaddr_reg[29] [29]));\n (* SOFT_HLUTNM = \"soft_lutpair1094\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[2]_i_1__0 \n (.I0(s_axi_araddr[2]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [2]),\n .O(\\axaddr_reg[29] [2]));\n (* SOFT_HLUTNM = \"soft_lutpair1095\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[3]_i_1__0 \n (.I0(s_axi_araddr[3]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [3]),\n .O(\\axaddr_reg[29] [3]));\n (* SOFT_HLUTNM = \"soft_lutpair1098\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[4]_i_1__0 \n (.I0(s_axi_araddr[4]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [4]),\n .O(\\axaddr_reg[29] [4]));\n (* SOFT_HLUTNM = \"soft_lutpair1097\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[5]_i_1__0 \n (.I0(s_axi_araddr[5]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [5]),\n .O(\\axaddr_reg[29] [5]));\n (* SOFT_HLUTNM = \"soft_lutpair1099\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[6]_i_1__0 \n (.I0(s_axi_araddr[6]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [6]),\n .O(\\axaddr_reg[29] [6]));\n (* SOFT_HLUTNM = \"soft_lutpair1102\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[7]_i_1__0 \n (.I0(s_axi_araddr[7]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [7]),\n .O(\\axaddr_reg[29] [7]));\n (* SOFT_HLUTNM = \"soft_lutpair1103\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[8]_i_1__0 \n (.I0(s_axi_araddr[8]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [8]),\n .O(\\axaddr_reg[29] [8]));\n (* SOFT_HLUTNM = \"soft_lutpair1108\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[9]_i_1__0 \n (.I0(s_axi_araddr[9]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [9]),\n .O(\\axaddr_reg[29] [9]));\n (* SOFT_HLUTNM = \"soft_lutpair1092\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[0]_i_1__0 \n (.I0(s_axi_araddr[0]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [0]),\n .I3(axready_reg_0),\n .I4(out[0]),\n .O(\\axaddr_incr_reg[29]_0 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair1104\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[10]_i_1__0 \n (.I0(s_axi_araddr[10]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [10]),\n .I3(axready_reg_0),\n .I4(out[10]),\n .O(\\axaddr_incr_reg[29]_0 [10]));\n (* SOFT_HLUTNM = \"soft_lutpair1105\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[11]_i_1__0 \n (.I0(s_axi_araddr[11]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [11]),\n .I3(axready_reg_0),\n .I4(out[11]),\n .O(\\axaddr_incr_reg[29]_0 [11]));\n (* SOFT_HLUTNM = \"soft_lutpair1106\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[12]_i_1__0 \n (.I0(s_axi_araddr[12]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [12]),\n .I3(axready_reg_0),\n .I4(out[12]),\n .O(\\axaddr_incr_reg[29]_0 [12]));\n (* SOFT_HLUTNM = \"soft_lutpair1112\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[13]_i_1__0 \n (.I0(s_axi_araddr[13]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [13]),\n .I3(axready_reg_0),\n .I4(out[13]),\n .O(\\axaddr_incr_reg[29]_0 [13]));\n (* SOFT_HLUTNM = \"soft_lutpair1107\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[14]_i_1__0 \n (.I0(s_axi_araddr[14]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [14]),\n .I3(axready_reg_0),\n .I4(out[14]),\n .O(\\axaddr_incr_reg[29]_0 [14]));\n (* SOFT_HLUTNM = \"soft_lutpair1109\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[15]_i_1__0 \n (.I0(s_axi_araddr[15]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [15]),\n .I3(axready_reg_0),\n .I4(out[15]),\n .O(\\axaddr_incr_reg[29]_0 [15]));\n (* SOFT_HLUTNM = \"soft_lutpair1110\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[16]_i_1__0 \n (.I0(s_axi_araddr[16]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [16]),\n .I3(axready_reg_0),\n .I4(out[16]),\n .O(\\axaddr_incr_reg[29]_0 [16]));\n (* SOFT_HLUTNM = \"soft_lutpair1116\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[17]_i_1__0 \n (.I0(s_axi_araddr[17]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [17]),\n .I3(axready_reg_0),\n .I4(out[17]),\n .O(\\axaddr_incr_reg[29]_0 [17]));\n (* SOFT_HLUTNM = \"soft_lutpair1111\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[18]_i_1__0 \n (.I0(s_axi_araddr[18]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [18]),\n .I3(axready_reg_0),\n .I4(out[18]),\n .O(\\axaddr_incr_reg[29]_0 [18]));\n (* SOFT_HLUTNM = \"soft_lutpair1113\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[19]_i_1__0 \n (.I0(s_axi_araddr[19]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [19]),\n .I3(axready_reg_0),\n .I4(out[19]),\n .O(\\axaddr_incr_reg[29]_0 [19]));\n (* SOFT_HLUTNM = \"soft_lutpair1093\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[1]_i_1__0 \n (.I0(s_axi_araddr[1]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [1]),\n .I3(axready_reg_0),\n .I4(out[1]),\n .O(\\axaddr_incr_reg[29]_0 [1]));\n (* SOFT_HLUTNM = \"soft_lutpair1114\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[20]_i_1__0 \n (.I0(s_axi_araddr[20]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [20]),\n .I3(axready_reg_0),\n .I4(out[20]),\n .O(\\axaddr_incr_reg[29]_0 [20]));\n (* SOFT_HLUTNM = \"soft_lutpair1120\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[21]_i_1__0 \n (.I0(s_axi_araddr[21]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [21]),\n .I3(axready_reg_0),\n .I4(out[21]),\n .O(\\axaddr_incr_reg[29]_0 [21]));\n (* SOFT_HLUTNM = \"soft_lutpair1115\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[22]_i_1__0 \n (.I0(s_axi_araddr[22]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [22]),\n .I3(axready_reg_0),\n .I4(out[22]),\n .O(\\axaddr_incr_reg[29]_0 [22]));\n (* SOFT_HLUTNM = \"soft_lutpair1117\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[23]_i_1__0 \n (.I0(s_axi_araddr[23]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [23]),\n .I3(axready_reg_0),\n .I4(out[23]),\n .O(\\axaddr_incr_reg[29]_0 [23]));\n (* SOFT_HLUTNM = \"soft_lutpair1118\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[24]_i_1__0 \n (.I0(s_axi_araddr[24]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [24]),\n .I3(axready_reg_0),\n .I4(out[24]),\n .O(\\axaddr_incr_reg[29]_0 [24]));\n (* SOFT_HLUTNM = \"soft_lutpair1100\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[25]_i_1__0 \n (.I0(s_axi_araddr[25]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [25]),\n .I3(axready_reg_0),\n .I4(out[25]),\n .O(\\axaddr_incr_reg[29]_0 [25]));\n (* SOFT_HLUTNM = \"soft_lutpair1119\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[26]_i_1__0 \n (.I0(s_axi_araddr[26]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [26]),\n .I3(axready_reg_0),\n .I4(out[26]),\n .O(\\axaddr_incr_reg[29]_0 [26]));\n (* SOFT_HLUTNM = \"soft_lutpair1121\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[27]_i_1__0 \n (.I0(s_axi_araddr[27]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [27]),\n .I3(axready_reg_0),\n .I4(out[27]),\n .O(\\axaddr_incr_reg[29]_0 [27]));\n (* SOFT_HLUTNM = \"soft_lutpair1122\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[28]_i_1__0 \n (.I0(s_axi_araddr[28]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [28]),\n .I3(axready_reg_0),\n .I4(out[28]),\n .O(\\axaddr_incr_reg[29]_0 [28]));\n (* SOFT_HLUTNM = \"soft_lutpair1123\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[29]_i_1__0 \n (.I0(s_axi_araddr[29]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [29]),\n .I3(axready_reg_0),\n .I4(out[29]),\n .O(\\axaddr_incr_reg[29]_0 [29]));\n (* SOFT_HLUTNM = \"soft_lutpair1094\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[2]_i_1__0 \n (.I0(s_axi_araddr[2]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [2]),\n .I3(axready_reg_0),\n .I4(out[2]),\n .O(\\axaddr_incr_reg[29]_0 [2]));\n (* SOFT_HLUTNM = \"soft_lutpair1095\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[3]_i_1__0 \n (.I0(s_axi_araddr[3]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [3]),\n .I3(axready_reg_0),\n .I4(out[3]),\n .O(\\axaddr_incr_reg[29]_0 [3]));\n (* SOFT_HLUTNM = \"soft_lutpair1098\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[4]_i_1__0 \n (.I0(s_axi_araddr[4]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [4]),\n .I3(axready_reg_0),\n .I4(out[4]),\n .O(\\axaddr_incr_reg[29]_0 [4]));\n (* SOFT_HLUTNM = \"soft_lutpair1097\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[5]_i_1__0 \n (.I0(s_axi_araddr[5]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [5]),\n .I3(axready_reg_0),\n .I4(out[5]),\n .O(\\axaddr_incr_reg[29]_0 [5]));\n (* SOFT_HLUTNM = \"soft_lutpair1099\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[6]_i_1__0 \n (.I0(s_axi_araddr[6]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [6]),\n .I3(axready_reg_0),\n .I4(out[6]),\n .O(\\axaddr_incr_reg[29]_0 [6]));\n (* SOFT_HLUTNM = \"soft_lutpair1102\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[7]_i_1__0 \n (.I0(s_axi_araddr[7]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [7]),\n .I3(axready_reg_0),\n .I4(out[7]),\n .O(\\axaddr_incr_reg[29]_0 [7]));\n (* SOFT_HLUTNM = \"soft_lutpair1103\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[8]_i_1__0 \n (.I0(s_axi_araddr[8]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [8]),\n .I3(axready_reg_0),\n .I4(out[8]),\n .O(\\axaddr_incr_reg[29]_0 [8]));\n (* SOFT_HLUTNM = \"soft_lutpair1108\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[9]_i_1__0 \n (.I0(s_axi_araddr[9]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [9]),\n .I3(axready_reg_0),\n .I4(out[9]),\n .O(\\axaddr_incr_reg[29]_0 [9]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_inferred_i_1__0\n (.I0(s_axi_araddr[3]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [3]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [3]),\n .O(in0[3]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_inferred_i_2__0\n (.I0(s_axi_araddr[2]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [2]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [2]),\n .O(in0[2]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_inferred_i_3__0\n (.I0(s_axi_araddr[1]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [1]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [1]),\n .O(in0[1]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_inferred_i_4__0\n (.I0(s_axi_araddr[0]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [0]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [0]),\n .O(in0[0]));\n LUT3 #(\n .INIT(8'h08)) \n axaddr_incr_p_inferred_i_5__0\n (.I0(s_axi_arvalid),\n .I1(s_axi_arready),\n .I2(s_axi_arburst),\n .O(\\axi_mc_cmd_translator_0/incr_axhandshake ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__0_i_1__0\n (.I0(s_axi_araddr[11]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [11]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [11]),\n .O(\\axaddr_incr_reg[29] [4]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__0_i_2__0\n (.I0(s_axi_araddr[10]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [10]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [10]),\n .O(\\axaddr_incr_reg[29] [3]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__0_i_3__0\n (.I0(s_axi_araddr[9]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [9]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [9]),\n .O(\\axaddr_incr_reg[29] [2]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__0_i_4\n (.I0(s_axi_araddr[8]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [8]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [8]),\n .O(\\axaddr_incr_reg[29] [1]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__1_i_1__0\n (.I0(s_axi_araddr[15]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [15]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [15]),\n .O(\\axaddr_incr_reg[29] [8]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__1_i_2__0\n (.I0(s_axi_araddr[14]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [14]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [14]),\n .O(\\axaddr_incr_reg[29] [7]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__1_i_3__0\n (.I0(s_axi_araddr[13]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [13]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [13]),\n .O(\\axaddr_incr_reg[29] [6]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__1_i_4__0\n (.I0(s_axi_araddr[12]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [12]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [12]),\n .O(\\axaddr_incr_reg[29] [5]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__2_i_1__0\n (.I0(s_axi_araddr[19]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [19]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [19]),\n .O(\\axaddr_incr_reg[29] [12]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__2_i_2__0\n (.I0(s_axi_araddr[18]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [18]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [18]),\n .O(\\axaddr_incr_reg[29] [11]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__2_i_3__0\n (.I0(s_axi_araddr[17]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [17]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [17]),\n .O(\\axaddr_incr_reg[29] [10]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__2_i_4__0\n (.I0(s_axi_araddr[16]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [16]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [16]),\n .O(\\axaddr_incr_reg[29] [9]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__3_i_1__0\n (.I0(s_axi_araddr[23]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [23]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [23]),\n .O(\\axaddr_incr_reg[29] [16]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__3_i_2__0\n (.I0(s_axi_araddr[22]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [22]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [22]),\n .O(\\axaddr_incr_reg[29] [15]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__3_i_3__0\n (.I0(s_axi_araddr[21]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [21]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [21]),\n .O(\\axaddr_incr_reg[29] [14]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__3_i_4__0\n (.I0(s_axi_araddr[20]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [20]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [20]),\n .O(\\axaddr_incr_reg[29] [13]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__4_i_1__0\n (.I0(s_axi_araddr[27]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [27]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [27]),\n .O(\\axaddr_incr_reg[29] [20]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__4_i_2__0\n (.I0(s_axi_araddr[26]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [26]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [26]),\n .O(\\axaddr_incr_reg[29] [19]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__4_i_3__0\n (.I0(s_axi_araddr[25]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [25]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [25]),\n .O(\\axaddr_incr_reg[29] [18]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__4_i_4__0\n (.I0(s_axi_araddr[24]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [24]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [24]),\n .O(\\axaddr_incr_reg[29] [17]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__5_i_1__0\n (.I0(s_axi_araddr[29]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [29]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [29]),\n .O(\\axaddr_incr_reg[29] [22]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__5_i_2__0\n (.I0(s_axi_araddr[28]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [28]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [28]),\n .O(\\axaddr_incr_reg[29] [21]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry_i_1__0\n (.I0(s_axi_araddr[5]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [5]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [5]),\n .O(DI));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry_i_2__0\n (.I0(s_axi_araddr[7]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [7]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [7]),\n .O(S[2]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry_i_3__0\n (.I0(s_axi_araddr[6]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [6]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [6]),\n .O(S[1]));\n LUT5 #(\n .INIT(32'h111DDD1D)) \n axaddr_incr_p_reg0_carry_i_4__0\n (.I0(\\axaddr_incr_reg[29]_1 [5]),\n .I1(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I2(\\axaddr_reg[29]_0 [5]),\n .I3(s_axi_arready),\n .I4(s_axi_araddr[5]),\n .O(S[0]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry_i_5__0\n (.I0(s_axi_araddr[4]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [4]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [4]),\n .O(\\axaddr_incr_reg[29] [0]));\n (* SOFT_HLUTNM = \"soft_lutpair1126\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axburst[1]_i_1__0 \n (.I0(s_axi_arburst),\n .I1(s_axi_arready),\n .I2(axburst),\n .O(\\axburst_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair1127\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axid[0]_i_1__0 \n (.I0(s_axi_arid),\n .I1(s_axi_arready),\n .I2(in),\n .O(\\axid_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair1125\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axlen[0]_i_1__0 \n (.I0(s_axi_arlen[0]),\n .I1(s_axi_arready),\n .I2(\\axlen_reg[7] [0]),\n .O(D[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1126\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axlen[1]_i_1__0 \n (.I0(s_axi_arlen[1]),\n .I1(s_axi_arready),\n .I2(\\axlen_reg[7] [1]),\n .O(D[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1101\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axlen[2]_i_1__0 \n (.I0(s_axi_arlen[2]),\n .I1(s_axi_arready),\n .I2(\\axlen_reg[7] [2]),\n .O(D[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1089\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axlen[3]_i_1__0 \n (.I0(s_axi_arlen[3]),\n .I1(s_axi_arready),\n .I2(\\axlen_reg[7] [3]),\n .O(D[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1086\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axlen[4]_i_1__0 \n (.I0(s_axi_arlen[4]),\n .I1(s_axi_arready),\n .I2(\\axlen_reg[7] [4]),\n .O(D[4]));\n (* SOFT_HLUTNM = \"soft_lutpair1088\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axlen[5]_i_1__0 \n (.I0(s_axi_arlen[5]),\n .I1(s_axi_arready),\n .I2(\\axlen_reg[7] [5]),\n .O(D[5]));\n (* SOFT_HLUTNM = \"soft_lutpair1091\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axlen[6]_i_1__0 \n (.I0(s_axi_arlen[6]),\n .I1(s_axi_arready),\n .I2(\\axlen_reg[7] [6]),\n .O(D[6]));\n (* SOFT_HLUTNM = \"soft_lutpair1090\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axlen[7]_i_1__0 \n (.I0(s_axi_arlen[7]),\n .I1(s_axi_arready),\n .I2(\\axlen_reg[7] [7]),\n .O(D[7]));\n LUT6 #(\n .INIT(64'hABABAB515151AB51)) \n \\axlen_cnt[0]_i_1__1 \n (.I0(axready_reg_0),\n .I1(Q[0]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axlen_reg[7] [0]),\n .I4(s_axi_arready),\n .I5(s_axi_arlen[0]),\n .O(\\axlen_cnt_reg[7] [0]));\n LUT6 #(\n .INIT(64'hABABAB515151AB51)) \n \\axlen_cnt[0]_i_1__2 \n (.I0(axready_reg_1),\n .I1(\\axlen_cnt_reg[3]_0 [0]),\n .I2(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I3(\\axlen_reg[7] [0]),\n .I4(s_axi_arready),\n .I5(s_axi_arlen[0]),\n .O(\\axlen_cnt_reg[3] [0]));\n LUT6 #(\n .INIT(64'hFFFFE4B100004E1B)) \n \\axlen_cnt[1]_i_1__1 \n (.I0(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I1(Q[1]),\n .I2(D[0]),\n .I3(Q[0]),\n .I4(axready_reg_0),\n .I5(D[1]),\n .O(\\axlen_cnt_reg[7] [1]));\n LUT6 #(\n .INIT(64'hFFFFE4B100004E1B)) \n \\axlen_cnt[1]_i_1__2 \n (.I0(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I1(\\axlen_cnt_reg[3]_0 [1]),\n .I2(D[0]),\n .I3(\\axlen_cnt_reg[3]_0 [0]),\n .I4(axready_reg_1),\n .I5(D[1]),\n .O(\\axlen_cnt_reg[3] [1]));\n LUT5 #(\n .INIT(32'hFFE1004B)) \n \\axlen_cnt[2]_i_1__1 \n (.I0(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I1(Q[2]),\n .I2(\\axlen_cnt[2]_i_2__1_n_0 ),\n .I3(axready_reg_0),\n .I4(D[2]),\n .O(\\axlen_cnt_reg[7] [2]));\n LUT5 #(\n .INIT(32'hFFE1004B)) \n \\axlen_cnt[2]_i_1__2 \n (.I0(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I1(\\axlen_cnt_reg[3]_0 [2]),\n .I2(\\axlen_cnt[2]_i_2__2_n_0 ),\n .I3(axready_reg_1),\n .I4(D[2]),\n .O(\\axlen_cnt_reg[3] [2]));\n LUT5 #(\n .INIT(32'hFFFACCFA)) \n \\axlen_cnt[2]_i_2__1 \n (.I0(Q[0]),\n .I1(D[0]),\n .I2(Q[1]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(D[1]),\n .O(\\axlen_cnt[2]_i_2__1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFACCFA)) \n \\axlen_cnt[2]_i_2__2 \n (.I0(\\axlen_cnt_reg[3]_0 [0]),\n .I1(D[0]),\n .I2(\\axlen_cnt_reg[3]_0 [1]),\n .I3(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I4(D[1]),\n .O(\\axlen_cnt[2]_i_2__2_n_0 ));\n LUT5 #(\n .INIT(32'hFFE1004B)) \n \\axlen_cnt[3]_i_1__1 \n (.I0(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I1(Q[3]),\n .I2(\\axlen_cnt[3]_i_2__1_n_0 ),\n .I3(axready_reg_0),\n .I4(D[3]),\n .O(\\axlen_cnt_reg[7] [3]));\n LUT5 #(\n .INIT(32'hFFE1004B)) \n \\axlen_cnt[3]_i_1__2 \n (.I0(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I1(\\axlen_cnt_reg[3]_0 [3]),\n .I2(\\axlen_cnt[3]_i_2__2_n_0 ),\n .I3(axready_reg_1),\n .I4(D[3]),\n .O(\\axlen_cnt_reg[3] [3]));\n LUT6 #(\n .INIT(64'hFEFEFEAEAEAEFEAE)) \n \\axlen_cnt[3]_i_2__1 \n (.I0(\\axlen_cnt[2]_i_2__1_n_0 ),\n .I1(Q[2]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axlen_reg[7] [2]),\n .I4(s_axi_arready),\n .I5(s_axi_arlen[2]),\n .O(\\axlen_cnt[3]_i_2__1_n_0 ));\n LUT6 #(\n .INIT(64'hFEFEFEAEAEAEFEAE)) \n \\axlen_cnt[3]_i_2__2 \n (.I0(\\axlen_cnt[2]_i_2__2_n_0 ),\n .I1(\\axlen_cnt_reg[3]_0 [2]),\n .I2(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I3(\\axlen_reg[7] [2]),\n .I4(s_axi_arready),\n .I5(s_axi_arlen[2]),\n .O(\\axlen_cnt[3]_i_2__2_n_0 ));\n LUT6 #(\n .INIT(64'hF606F6F6F6060606)) \n \\axlen_cnt[4]_i_1__0 \n (.I0(\\axlen_cnt[4]_i_2__0_n_0 ),\n .I1(\\axlen_cnt[4]_i_3__0_n_0 ),\n .I2(axready_reg_0),\n .I3(s_axi_arlen[4]),\n .I4(s_axi_arready),\n .I5(\\axlen_reg[7] [4]),\n .O(\\axlen_cnt_reg[7] [4]));\n LUT6 #(\n .INIT(64'h0101015151510151)) \n \\axlen_cnt[4]_i_2__0 \n (.I0(\\axlen_cnt[3]_i_2__1_n_0 ),\n .I1(Q[3]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axlen_reg[7] [3]),\n .I4(s_axi_arready),\n .I5(s_axi_arlen[3]),\n .O(\\axlen_cnt[4]_i_2__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1086\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axlen_cnt[4]_i_3__0 \n (.I0(s_axi_arlen[4]),\n .I1(s_axi_arready),\n .I2(\\axlen_reg[7] [4]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(Q[4]),\n .O(\\axlen_cnt[4]_i_3__0_n_0 ));\n LUT6 #(\n .INIT(64'hF909F9F9F9090909)) \n \\axlen_cnt[5]_i_1__0 \n (.I0(\\axlen_cnt[5]_i_2__0_n_0 ),\n .I1(\\axlen_cnt[5]_i_3__0_n_0 ),\n .I2(axready_reg_0),\n .I3(s_axi_arlen[5]),\n .I4(s_axi_arready),\n .I5(\\axlen_reg[7] [5]),\n .O(\\axlen_cnt_reg[7] [5]));\n (* SOFT_HLUTNM = \"soft_lutpair1088\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axlen_cnt[5]_i_2__0 \n (.I0(s_axi_arlen[5]),\n .I1(s_axi_arready),\n .I2(\\axlen_reg[7] [5]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(Q[5]),\n .O(\\axlen_cnt[5]_i_2__0_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFCFFFCAA)) \n \\axlen_cnt[5]_i_3__0 \n (.I0(Q[4]),\n .I1(D[4]),\n .I2(D[3]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(Q[3]),\n .I5(\\axlen_cnt[3]_i_2__1_n_0 ),\n .O(\\axlen_cnt[5]_i_3__0_n_0 ));\n LUT6 #(\n .INIT(64'hF909F9F9F9090909)) \n \\axlen_cnt[6]_i_1__0 \n (.I0(\\axlen_cnt[7]_i_3__0_n_0 ),\n .I1(\\axlen_cnt[7]_i_4__0_n_0 ),\n .I2(axready_reg_0),\n .I3(s_axi_arlen[6]),\n .I4(s_axi_arready),\n .I5(\\axlen_reg[7] [6]),\n .O(\\axlen_cnt_reg[7] [6]));\n (* SOFT_HLUTNM = \"soft_lutpair1096\" *) \n LUT5 #(\n .INIT(32'h0E000ECC)) \n \\axlen_cnt[7]_i_1__0 \n (.I0(s_axi_arvalid),\n .I1(next),\n .I2(s_axi_arburst),\n .I3(s_axi_arready),\n .I4(axburst),\n .O(E));\n LUT6 #(\n .INIT(64'hFFFFEEE10000444B)) \n \\axlen_cnt[7]_i_2__0 \n (.I0(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I1(Q[7]),\n .I2(\\axlen_cnt[7]_i_3__0_n_0 ),\n .I3(\\axlen_cnt[7]_i_4__0_n_0 ),\n .I4(axready_reg_0),\n .I5(D[7]),\n .O(\\axlen_cnt_reg[7] [7]));\n (* SOFT_HLUTNM = \"soft_lutpair1091\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axlen_cnt[7]_i_3__0 \n (.I0(s_axi_arlen[6]),\n .I1(s_axi_arready),\n .I2(\\axlen_reg[7] [6]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(Q[6]),\n .O(\\axlen_cnt[7]_i_3__0_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFEAE)) \n \\axlen_cnt[7]_i_4__0 \n (.I0(\\axlen_cnt[3]_i_2__1_n_0 ),\n .I1(Q[3]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(D[3]),\n .I4(\\axlen_cnt[4]_i_3__0_n_0 ),\n .I5(\\axlen_cnt[5]_i_2__0_n_0 ),\n .O(\\axlen_cnt[7]_i_4__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1087\" *) \n LUT5 #(\n .INIT(32'h888FFF8F)) \n axready_i_1__0\n (.I0(next),\n .I1(r_rlast_reg),\n .I2(axvalid),\n .I3(s_axi_arready),\n .I4(s_axi_arvalid),\n .O(axready_i_1__0_n_0));\n FDRE #(\n .INIT(1'b0)) \n axready_reg\n (.C(CLK),\n .CE(1'b1),\n .D(axready_i_1__0_n_0),\n .Q(s_axi_arready),\n .R(areset_d1));\n (* SOFT_HLUTNM = \"soft_lutpair1087\" *) \n LUT3 #(\n .INIT(8'hB8)) \n axvalid_i_1__0\n (.I0(s_axi_arvalid),\n .I1(s_axi_arready),\n .I2(axvalid),\n .O(arvalid_int));\n LUT6 #(\n .INIT(64'hF606F6F6F6060606)) \n \\int_addr[0]_i_1__0 \n (.I0(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]),\n .I1(D[0]),\n .I2(axready_reg_1),\n .I3(s_axi_araddr[5]),\n .I4(s_axi_arready),\n .I5(\\axaddr_reg[29]_0 [5]),\n .O(\\int_addr_reg[3] [0]));\n LUT6 #(\n .INIT(64'hBFBFBFEA40401540)) \n \\int_addr[1]_i_1__0 \n (.I0(axready_reg_1),\n .I1(D[1]),\n .I2(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]),\n .I3(\\int_addr_reg[3]_0 [1]),\n .I4(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I5(\\axaddr_reg[29] [6]),\n .O(\\int_addr_reg[3] [1]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\int_addr[1]_i_2__0 \n (.I0(s_axi_araddr[5]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [5]),\n .I3(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I4(\\int_addr_reg[3]_0 [0]),\n .O(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]));\n LUT6 #(\n .INIT(64'hBFBFBFEA40401540)) \n \\int_addr[2]_i_1__0 \n (.I0(axready_reg_1),\n .I1(D[2]),\n .I2(\\int_addr[3]_i_5__0_n_0 ),\n .I3(\\int_addr_reg[3]_0 [2]),\n .I4(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I5(\\axaddr_reg[29] [7]),\n .O(\\int_addr_reg[3] [2]));\n (* SOFT_HLUTNM = \"soft_lutpair1125\" *) \n LUT3 #(\n .INIT(8'h80)) \n \\int_addr[2]_i_2__0 \n (.I0(s_axi_arvalid),\n .I1(s_axi_arready),\n .I2(s_axi_arburst),\n .O(\\axi_mc_cmd_translator_0/wrap_axhandshake ));\n (* SOFT_HLUTNM = \"soft_lutpair1096\" *) \n LUT5 #(\n .INIT(32'hCFC08080)) \n \\int_addr[3]_i_1__0 \n (.I0(s_axi_arvalid),\n .I1(s_axi_arburst),\n .I2(s_axi_arready),\n .I3(axburst),\n .I4(next),\n .O(\\axlen_cnt_reg[0] ));\n LUT6 #(\n .INIT(64'h8BBBBBBBB8888888)) \n \\int_addr[3]_i_2__0 \n (.I0(\\axaddr_reg[29] [8]),\n .I1(axready_reg_1),\n .I2(D[3]),\n .I3(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [7]),\n .I4(\\int_addr[3]_i_5__0_n_0 ),\n .I5(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [8]),\n .O(\\int_addr_reg[3] [3]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\int_addr[3]_i_4__0 \n (.I0(s_axi_araddr[7]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [7]),\n .I3(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I4(\\int_addr_reg[3]_0 [2]),\n .O(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [7]));\n LUT6 #(\n .INIT(64'hEEE222E200000000)) \n \\int_addr[3]_i_5__0 \n (.I0(\\int_addr_reg[3]_0 [1]),\n .I1(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I2(\\axaddr_reg[29]_0 [6]),\n .I3(s_axi_arready),\n .I4(s_axi_araddr[6]),\n .I5(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]),\n .O(\\int_addr[3]_i_5__0_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\int_addr[3]_i_6__0 \n (.I0(s_axi_araddr[8]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [8]),\n .I3(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I4(\\int_addr_reg[3]_0 [3]),\n .O(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [8]));\n LUT6 #(\n .INIT(64'h0010FFFF00100010)) \n r_rlast_i_1\n (.I0(\\axlen_cnt[2]_i_2__2_n_0 ),\n .I1(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/axlen_cnt_t__3 [2]),\n .I2(\\axburst_reg[1] ),\n .I3(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/axlen_cnt_t__3 [3]),\n .I4(\\axlen_cnt[3]_i_2__1_n_0 ),\n .I5(r_rlast_i_4_n_0),\n .O(r_rlast_reg));\n (* SOFT_HLUTNM = \"soft_lutpair1101\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n r_rlast_i_2\n (.I0(s_axi_arlen[2]),\n .I1(s_axi_arready),\n .I2(\\axlen_reg[7] [2]),\n .I3(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I4(\\axlen_cnt_reg[3]_0 [2]),\n .O(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/axlen_cnt_t__3 [2]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n r_rlast_i_3\n (.I0(s_axi_arlen[3]),\n .I1(s_axi_arready),\n .I2(\\axlen_reg[7] [3]),\n .I3(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I4(\\axlen_cnt_reg[3]_0 [3]),\n .O(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/axlen_cnt_t__3 [3]));\n LUT6 #(\n .INIT(64'h0000000000000001)) \n r_rlast_i_4\n (.I0(r_rlast_i_5_n_0),\n .I1(\\axlen_cnt[7]_i_3__0_n_0 ),\n .I2(\\axlen_cnt[4]_i_3__0_n_0 ),\n .I3(\\axlen_cnt[5]_i_2__0_n_0 ),\n .I4(\\axburst_reg[1] ),\n .I5(r_rlast_i_6_n_0),\n .O(r_rlast_i_4_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1090\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n r_rlast_i_5\n (.I0(s_axi_arlen[7]),\n .I1(s_axi_arready),\n .I2(\\axlen_reg[7] [7]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(Q[7]),\n .O(r_rlast_i_5_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1089\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n r_rlast_i_6\n (.I0(s_axi_arlen[3]),\n .I1(s_axi_arready),\n .I2(\\axlen_reg[7] [3]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(Q[3]),\n .O(r_rlast_i_6_n_0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_axi_mc_cmd_translator\" *) \nmodule ddr3_ifmig_7series_v4_0_axi_mc_cmd_translator\n (out,\n Q,\n \\app_addr_r1_reg[27] ,\n \\int_addr_reg[3] ,\n \\axlen_cnt_reg[3] ,\n in0,\n axready_reg,\n S,\n axready_reg_0,\n areset_d1,\n E,\n D,\n CLK,\n axready_reg_1,\n axready_reg_2,\n axready_reg_3,\n \\axlen_cnt_reg[3]_0 );\n output [29:0]out;\n output [7:0]Q;\n output [29:0]\\app_addr_r1_reg[27] ;\n output [3:0]\\int_addr_reg[3] ;\n output [3:0]\\axlen_cnt_reg[3] ;\n input [3:0]in0;\n input [24:0]axready_reg;\n input [0:0]S;\n input [0:0]axready_reg_0;\n input areset_d1;\n input [0:0]E;\n input [7:0]D;\n input CLK;\n input [29:0]axready_reg_1;\n input [0:0]axready_reg_2;\n input [3:0]axready_reg_3;\n input [3:0]\\axlen_cnt_reg[3]_0 ;\n\n wire CLK;\n wire [7:0]D;\n wire [0:0]E;\n wire [7:0]Q;\n wire [0:0]S;\n wire [29:0]\\app_addr_r1_reg[27] ;\n wire areset_d1;\n wire [3:0]\\axlen_cnt_reg[3] ;\n wire [3:0]\\axlen_cnt_reg[3]_0 ;\n wire [24:0]axready_reg;\n wire [0:0]axready_reg_0;\n wire [29:0]axready_reg_1;\n wire [0:0]axready_reg_2;\n wire [3:0]axready_reg_3;\n wire [3:0]in0;\n wire [3:0]\\int_addr_reg[3] ;\n wire [29:0]out;\n\n ddr3_ifmig_7series_v4_0_axi_mc_incr_cmd axi_mc_incr_cmd_0\n (.CLK(CLK),\n .D(D),\n .E(E),\n .Q(Q),\n .S(S),\n .\\app_addr_r1_reg[27] (\\app_addr_r1_reg[27] ),\n .areset_d1(areset_d1),\n .axready_reg(axready_reg),\n .axready_reg_0(axready_reg_0),\n .axready_reg_1(axready_reg_1),\n .in0(in0),\n .out(out));\n ddr3_ifmig_7series_v4_0_axi_mc_wrap_cmd axi_mc_wrap_cmd_0\n (.CLK(CLK),\n .areset_d1(areset_d1),\n .\\axlen_cnt_reg[3]_0 (\\axlen_cnt_reg[3] ),\n .\\axlen_cnt_reg[3]_1 (\\axlen_cnt_reg[3]_0 ),\n .axready_reg(axready_reg_2),\n .axready_reg_0(axready_reg_3),\n .\\int_addr_reg[3]_0 (\\int_addr_reg[3] ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_axi_mc_cmd_translator\" *) \nmodule ddr3_ifmig_7series_v4_0_axi_mc_cmd_translator__parameterized0\n (out,\n Q,\n \\app_addr_r1_reg[27] ,\n \\app_addr_r1_reg[6] ,\n \\axlen_cnt_reg[3] ,\n in0,\n DI,\n S,\n axready_reg,\n areset_d1,\n E,\n D,\n CLK,\n axready_reg_0,\n axready_reg_1,\n axready_reg_2,\n \\axlen_cnt_reg[3]_0 );\n output [29:0]out;\n output [7:0]Q;\n output [29:0]\\app_addr_r1_reg[27] ;\n output [3:0]\\app_addr_r1_reg[6] ;\n output [3:0]\\axlen_cnt_reg[3] ;\n input [3:0]in0;\n input [0:0]DI;\n input [3:0]S;\n input [21:0]axready_reg;\n input areset_d1;\n input [0:0]E;\n input [7:0]D;\n input CLK;\n input [29:0]axready_reg_0;\n input [0:0]axready_reg_1;\n input [3:0]axready_reg_2;\n input [3:0]\\axlen_cnt_reg[3]_0 ;\n\n wire CLK;\n wire [7:0]D;\n wire [0:0]DI;\n wire [0:0]E;\n wire [7:0]Q;\n wire [3:0]S;\n wire [29:0]\\app_addr_r1_reg[27] ;\n wire [3:0]\\app_addr_r1_reg[6] ;\n wire areset_d1;\n wire [3:0]\\axlen_cnt_reg[3] ;\n wire [3:0]\\axlen_cnt_reg[3]_0 ;\n wire [21:0]axready_reg;\n wire [29:0]axready_reg_0;\n wire [0:0]axready_reg_1;\n wire [3:0]axready_reg_2;\n wire [3:0]in0;\n wire [29:0]out;\n\n ddr3_ifmig_7series_v4_0_axi_mc_incr_cmd__parameterized0 axi_mc_incr_cmd_0\n (.CLK(CLK),\n .D(D),\n .DI(DI),\n .E(E),\n .Q(Q),\n .S(S),\n .\\app_addr_r1_reg[27] (\\app_addr_r1_reg[27] ),\n .areset_d1(areset_d1),\n .axready_reg(axready_reg),\n .axready_reg_0(axready_reg_0),\n .in0(in0),\n .out(out));\n ddr3_ifmig_7series_v4_0_axi_mc_wrap_cmd__parameterized0 axi_mc_wrap_cmd_0\n (.CLK(CLK),\n .\\app_addr_r1_reg[6] (\\app_addr_r1_reg[6] ),\n .areset_d1(areset_d1),\n .\\axlen_cnt_reg[3]_0 (\\axlen_cnt_reg[3] ),\n .\\axlen_cnt_reg[3]_1 (\\axlen_cnt_reg[3]_0 ),\n .axready_reg(axready_reg_1),\n .axready_reg_0(axready_reg_2));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_axi_mc_fifo\" *) \nmodule ddr3_ifmig_7series_v4_0_axi_mc_fifo\n (bid_i,\n app_en_ns1,\n wr_cmd_en,\n E,\n bhandshake,\n bvalid_i_reg,\n b_push,\n b_awid,\n CLK,\n app_rdy,\n \\RD_PRI_REG_STARVE.rnw_i_reg ,\n rd_cmd_en,\n reset_reg,\n app_en_r1,\n bvalid_i_reg_0,\n s_axi_bready,\n wvalid_int,\n awvalid_int,\n app_wdf_rdy,\n areset_d1);\n output bid_i;\n output app_en_ns1;\n output wr_cmd_en;\n output [0:0]E;\n output bhandshake;\n output bvalid_i_reg;\n input b_push;\n input b_awid;\n input CLK;\n input app_rdy;\n input \\RD_PRI_REG_STARVE.rnw_i_reg ;\n input rd_cmd_en;\n input reset_reg;\n input app_en_r1;\n input bvalid_i_reg_0;\n input s_axi_bready;\n input wvalid_int;\n input awvalid_int;\n input app_wdf_rdy;\n input areset_d1;\n\n wire CLK;\n wire [0:0]E;\n wire \\RD_PRI_REG_STARVE.rnw_i_reg ;\n wire app_en_ns1;\n wire app_en_r1;\n wire app_rdy;\n wire app_wdf_rdy;\n wire areset_d1;\n wire awvalid_int;\n wire b_awid;\n wire b_push;\n wire bhandshake;\n wire bid_i;\n wire bvalid_i_reg;\n wire bvalid_i_reg_0;\n wire \\cnt_read[0]_i_1__1_n_0 ;\n wire \\cnt_read[1]_i_1_n_0 ;\n wire \\cnt_read[2]_i_1__0_n_0 ;\n wire \\cnt_read[3]_i_1__0_n_0 ;\n wire \\cnt_read[3]_i_2_n_0 ;\n wire \\cnt_read[3]_i_3_n_0 ;\n wire [2:0]cnt_read_reg__0;\n wire [3:3]cnt_read_reg__0__0;\n wire rd_cmd_en;\n wire reset_reg;\n wire s_axi_bready;\n wire wr_cmd_en;\n wire wvalid_int;\n\n LUT6 #(\n .INIT(64'h8080808080008080)) \n \\RD_PRI_REG_STARVE.rnw_i_i_2 \n (.I0(wvalid_int),\n .I1(awvalid_int),\n .I2(app_wdf_rdy),\n .I3(\\cnt_read[3]_i_3_n_0 ),\n .I4(cnt_read_reg__0[0]),\n .I5(cnt_read_reg__0__0),\n .O(wr_cmd_en));\n LUT4 #(\n .INIT(16'hA808)) \n \\app_addr_r1[27]_i_1 \n (.I0(app_rdy),\n .I1(wr_cmd_en),\n .I2(\\RD_PRI_REG_STARVE.rnw_i_reg ),\n .I3(rd_cmd_en),\n .O(E));\n LUT6 #(\n .INIT(64'h0000FD5D0000A808)) \n app_en_r1_i_1\n (.I0(app_rdy),\n .I1(wr_cmd_en),\n .I2(\\RD_PRI_REG_STARVE.rnw_i_reg ),\n .I3(rd_cmd_en),\n .I4(reset_reg),\n .I5(app_en_r1),\n .O(app_en_ns1));\n LUT2 #(\n .INIT(4'hB)) \n \\bid_t[0]_i_1 \n (.I0(s_axi_bready),\n .I1(bvalid_i_reg_0),\n .O(bhandshake));\n LUT6 #(\n .INIT(64'h7FFFFFFF7FFF7FFF)) \n bvalid_i_i_1\n (.I0(cnt_read_reg__0__0),\n .I1(cnt_read_reg__0[1]),\n .I2(cnt_read_reg__0[2]),\n .I3(cnt_read_reg__0[0]),\n .I4(s_axi_bready),\n .I5(bvalid_i_reg_0),\n .O(bvalid_i_reg));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_read[0]_i_1__1 \n (.I0(cnt_read_reg__0[0]),\n .O(\\cnt_read[0]_i_1__1_n_0 ));\n LUT6 #(\n .INIT(64'h52D2D2D22D2D2D2D)) \n \\cnt_read[1]_i_1 \n (.I0(b_push),\n .I1(bhandshake),\n .I2(cnt_read_reg__0[0]),\n .I3(cnt_read_reg__0[2]),\n .I4(cnt_read_reg__0__0),\n .I5(cnt_read_reg__0[1]),\n .O(\\cnt_read[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h4FFFFF30300000CF)) \n \\cnt_read[2]_i_1__0 \n (.I0(cnt_read_reg__0__0),\n .I1(bhandshake),\n .I2(b_push),\n .I3(cnt_read_reg__0[0]),\n .I4(cnt_read_reg__0[1]),\n .I5(cnt_read_reg__0[2]),\n .O(\\cnt_read[2]_i_1__0_n_0 ));\n LUT6 #(\n .INIT(64'h5959AA5959595959)) \n \\cnt_read[3]_i_1__0 \n (.I0(b_push),\n .I1(bvalid_i_reg_0),\n .I2(s_axi_bready),\n .I3(cnt_read_reg__0[0]),\n .I4(\\cnt_read[3]_i_3_n_0 ),\n .I5(cnt_read_reg__0__0),\n .O(\\cnt_read[3]_i_1__0_n_0 ));\n LUT6 #(\n .INIT(64'h5FFF2000FFBA0045)) \n \\cnt_read[3]_i_2 \n (.I0(cnt_read_reg__0[1]),\n .I1(bhandshake),\n .I2(b_push),\n .I3(cnt_read_reg__0[0]),\n .I4(cnt_read_reg__0__0),\n .I5(cnt_read_reg__0[2]),\n .O(\\cnt_read[3]_i_2_n_0 ));\n LUT2 #(\n .INIT(4'h7)) \n \\cnt_read[3]_i_3 \n (.I0(cnt_read_reg__0[1]),\n .I1(cnt_read_reg__0[2]),\n .O(\\cnt_read[3]_i_3_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\cnt_read_reg[0] \n (.C(CLK),\n .CE(\\cnt_read[3]_i_1__0_n_0 ),\n .D(\\cnt_read[0]_i_1__1_n_0 ),\n .Q(cnt_read_reg__0[0]),\n .S(areset_d1));\n FDSE #(\n .INIT(1'b1)) \n \\cnt_read_reg[1] \n (.C(CLK),\n .CE(\\cnt_read[3]_i_1__0_n_0 ),\n .D(\\cnt_read[1]_i_1_n_0 ),\n .Q(cnt_read_reg__0[1]),\n .S(areset_d1));\n FDSE #(\n .INIT(1'b1)) \n \\cnt_read_reg[2] \n (.C(CLK),\n .CE(\\cnt_read[3]_i_1__0_n_0 ),\n .D(\\cnt_read[2]_i_1__0_n_0 ),\n .Q(cnt_read_reg__0[2]),\n .S(areset_d1));\n FDSE #(\n .INIT(1'b1)) \n \\cnt_read_reg[3] \n (.C(CLK),\n .CE(\\cnt_read[3]_i_1__0_n_0 ),\n .D(\\cnt_read[3]_i_2_n_0 ),\n .Q(cnt_read_reg__0__0),\n .S(areset_d1));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_b_channel_0/bid_fifo_0/memory_reg[7] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_b_channel_0/bid_fifo_0/memory_reg[7][0]_srl8 \" *) \n SRL16E #(\n .INIT(16'h0000)) \n \\memory_reg[7][0]_srl8 \n (.A0(cnt_read_reg__0[0]),\n .A1(cnt_read_reg__0[1]),\n .A2(cnt_read_reg__0[2]),\n .A3(1'b0),\n .CE(b_push),\n .CLK(CLK),\n .D(b_awid),\n .Q(bid_i));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_axi_mc_fifo\" *) \nmodule ddr3_ifmig_7series_v4_0_axi_mc_fifo__parameterized0\n (rd_cmd_en,\n E,\n s_axi_rvalid,\n p_0_in,\n \\FSM_sequential_state_reg[1] ,\n \\FSM_sequential_state_reg[0] ,\n \\s_axi_rresp[1] ,\n s_axi_arvalid,\n s_axi_arready,\n axvalid,\n \\cnt_read_reg[5]_0 ,\n app_rdy,\n \\trans_buf_out_r_reg[0] ,\n app_rd_data_valid,\n s_axi_rready,\n out,\n tr_empty,\n in0,\n Q,\n CLK,\n areset_d1);\n output rd_cmd_en;\n output [0:0]E;\n output s_axi_rvalid;\n output p_0_in;\n output \\FSM_sequential_state_reg[1] ;\n output \\FSM_sequential_state_reg[0] ;\n output [256:0]\\s_axi_rresp[1] ;\n input s_axi_arvalid;\n input s_axi_arready;\n input axvalid;\n input \\cnt_read_reg[5]_0 ;\n input app_rdy;\n input \\trans_buf_out_r_reg[0] ;\n input app_rd_data_valid;\n input s_axi_rready;\n input [1:0]out;\n input tr_empty;\n input [1:0]in0;\n input [255:0]Q;\n input CLK;\n input areset_d1;\n\n wire CLK;\n wire [0:0]E;\n wire \\FSM_sequential_state_reg[0] ;\n wire \\FSM_sequential_state_reg[1] ;\n wire [255:0]Q;\n wire app_rd_data_valid;\n wire app_rdy;\n wire areset_d1;\n wire axvalid;\n wire \\cnt_read[0]_i_1_n_0 ;\n wire \\cnt_read[0]_rep_i_1_n_0 ;\n wire \\cnt_read[1]_i_1__0_n_0 ;\n wire \\cnt_read[1]_rep_i_1_n_0 ;\n wire \\cnt_read[2]_i_1__1_n_0 ;\n wire \\cnt_read[2]_rep_i_1_n_0 ;\n wire \\cnt_read[3]_i_1__1_n_0 ;\n wire \\cnt_read[3]_rep_i_1_n_0 ;\n wire \\cnt_read[4]_i_1__0_n_0 ;\n wire \\cnt_read[4]_rep_i_1_n_0 ;\n wire \\cnt_read[5]_i_1_n_0 ;\n wire \\cnt_read[5]_i_2__0_n_0 ;\n wire \\cnt_read[5]_i_3_n_0 ;\n wire \\cnt_read_reg[0]_rep_n_0 ;\n wire \\cnt_read_reg[1]_rep_n_0 ;\n wire \\cnt_read_reg[2]_rep_n_0 ;\n wire \\cnt_read_reg[3]_rep_n_0 ;\n wire \\cnt_read_reg[4]_rep_n_0 ;\n wire \\cnt_read_reg[5]_0 ;\n wire [5:5]cnt_read_reg__0;\n wire [4:0]cnt_read_reg__1;\n wire [1:0]in0;\n wire [1:0]out;\n wire p_0_in;\n wire r_push_i_4_n_0;\n wire rd_cmd_en;\n wire rvalid04_in;\n wire s_axi_arready;\n wire s_axi_arvalid;\n wire s_axi_rready;\n wire [256:0]\\s_axi_rresp[1] ;\n wire s_axi_rvalid;\n wire tr_empty;\n wire \\trans_buf_out_r_reg[0] ;\n wire \\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][100]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][101]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][102]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][103]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][104]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][105]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][106]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][107]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][108]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][109]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][110]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][111]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][112]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][113]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][114]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][115]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][116]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][117]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][118]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][119]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][120]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][121]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][122]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][123]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][124]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][125]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][126]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][127]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][128]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][129]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][130]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][131]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][132]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][133]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][134]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][135]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][136]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][137]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][138]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][139]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][140]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][141]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][142]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][143]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][144]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][145]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][146]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][147]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][148]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][149]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][150]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][151]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][152]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][153]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][154]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][155]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][156]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][157]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][158]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][159]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][160]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][161]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][162]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][163]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][164]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][165]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][166]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][167]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][168]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][169]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][170]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][171]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][172]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][173]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][174]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][175]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][176]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][177]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][178]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][179]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][180]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][181]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][182]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][183]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][184]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][185]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][186]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][187]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][188]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][189]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][190]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][191]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][192]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][193]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][194]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][195]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][196]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][197]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][198]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][199]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][200]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][201]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][202]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][203]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][204]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][205]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][206]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][207]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][208]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][209]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][210]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][211]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][212]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][213]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][214]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][215]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][216]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][217]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][218]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][219]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][220]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][221]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][222]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][223]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][224]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][225]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][226]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][227]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][228]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][229]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][230]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][231]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][232]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][233]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][234]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][235]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][236]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][237]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][238]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][239]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][240]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][241]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][242]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][243]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][244]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][245]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][246]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][247]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][248]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][249]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][250]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][251]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][252]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][253]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][254]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][255]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][256]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][34]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][35]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][36]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][37]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][38]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][39]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][40]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][41]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][42]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][43]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][44]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][45]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][46]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][47]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][48]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][49]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][50]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][51]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][52]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][53]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][54]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][55]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][56]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][57]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][58]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][59]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][60]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][61]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][62]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][63]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][64]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][65]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][66]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][67]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][68]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][69]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][70]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][71]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][72]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][73]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][74]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][75]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][76]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][77]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][78]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][79]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][80]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][81]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][82]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][83]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][84]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][85]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][86]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][87]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][88]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][89]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][90]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][91]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][92]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][93]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][94]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][95]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][96]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][97]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][98]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][99]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ;\n\n LUT5 #(\n .INIT(32'hF7FD4045)) \n \\FSM_sequential_state[0]_i_1 \n (.I0(out[0]),\n .I1(p_0_in),\n .I2(out[1]),\n .I3(tr_empty),\n .I4(in0[0]),\n .O(\\FSM_sequential_state_reg[0] ));\n LUT5 #(\n .INIT(32'hB7BA0002)) \n \\FSM_sequential_state[1]_i_1 \n (.I0(out[0]),\n .I1(p_0_in),\n .I2(out[1]),\n .I3(tr_empty),\n .I4(in0[1]),\n .O(\\FSM_sequential_state_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair1161\" *) \n LUT3 #(\n .INIT(8'hC8)) \n \\FSM_sequential_state[1]_i_2 \n (.I0(\\trans_buf_out_r_reg[0] ),\n .I1(rvalid04_in),\n .I2(s_axi_rready),\n .O(p_0_in));\n LUT2 #(\n .INIT(4'h8)) \n \\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_2 \n (.I0(rd_cmd_en),\n .I1(app_rdy),\n .O(E));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_read[0]_i_1 \n (.I0(cnt_read_reg__1[0]),\n .O(\\cnt_read[0]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_read[0]_rep_i_1 \n (.I0(cnt_read_reg__1[0]),\n .O(\\cnt_read[0]_rep_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAAA6666655599999)) \n \\cnt_read[1]_i_1__0 \n (.I0(cnt_read_reg__1[0]),\n .I1(app_rd_data_valid),\n .I2(s_axi_rready),\n .I3(\\trans_buf_out_r_reg[0] ),\n .I4(rvalid04_in),\n .I5(cnt_read_reg__1[1]),\n .O(\\cnt_read[1]_i_1__0_n_0 ));\n LUT6 #(\n .INIT(64'hAAA6666655599999)) \n \\cnt_read[1]_rep_i_1 \n (.I0(cnt_read_reg__1[0]),\n .I1(app_rd_data_valid),\n .I2(s_axi_rready),\n .I3(\\trans_buf_out_r_reg[0] ),\n .I4(rvalid04_in),\n .I5(cnt_read_reg__1[1]),\n .O(\\cnt_read[1]_rep_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1160\" *) \n LUT3 #(\n .INIT(8'h69)) \n \\cnt_read[2]_i_1__1 \n (.I0(\\cnt_read[5]_i_3_n_0 ),\n .I1(cnt_read_reg__1[2]),\n .I2(cnt_read_reg__1[1]),\n .O(\\cnt_read[2]_i_1__1_n_0 ));\n LUT3 #(\n .INIT(8'h69)) \n \\cnt_read[2]_rep_i_1 \n (.I0(\\cnt_read[5]_i_3_n_0 ),\n .I1(cnt_read_reg__1[2]),\n .I2(cnt_read_reg__1[1]),\n .O(\\cnt_read[2]_rep_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1160\" *) \n LUT4 #(\n .INIT(16'h78E1)) \n \\cnt_read[3]_i_1__1 \n (.I0(cnt_read_reg__1[1]),\n .I1(\\cnt_read[5]_i_3_n_0 ),\n .I2(cnt_read_reg__1[3]),\n .I3(cnt_read_reg__1[2]),\n .O(\\cnt_read[3]_i_1__1_n_0 ));\n LUT4 #(\n .INIT(16'h78E1)) \n \\cnt_read[3]_rep_i_1 \n (.I0(cnt_read_reg__1[1]),\n .I1(\\cnt_read[5]_i_3_n_0 ),\n .I2(cnt_read_reg__1[3]),\n .I3(cnt_read_reg__1[2]),\n .O(\\cnt_read[3]_rep_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1159\" *) \n LUT5 #(\n .INIT(32'h7F80FE01)) \n \\cnt_read[4]_i_1__0 \n (.I0(cnt_read_reg__1[1]),\n .I1(\\cnt_read[5]_i_3_n_0 ),\n .I2(cnt_read_reg__1[2]),\n .I3(cnt_read_reg__1[4]),\n .I4(cnt_read_reg__1[3]),\n .O(\\cnt_read[4]_i_1__0_n_0 ));\n LUT5 #(\n .INIT(32'h7F80FE01)) \n \\cnt_read[4]_rep_i_1 \n (.I0(cnt_read_reg__1[1]),\n .I1(\\cnt_read[5]_i_3_n_0 ),\n .I2(cnt_read_reg__1[2]),\n .I3(cnt_read_reg__1[4]),\n .I4(cnt_read_reg__1[3]),\n .O(\\cnt_read[4]_rep_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h56AA)) \n \\cnt_read[5]_i_1 \n (.I0(app_rd_data_valid),\n .I1(s_axi_rready),\n .I2(\\trans_buf_out_r_reg[0] ),\n .I3(rvalid04_in),\n .O(\\cnt_read[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h7FFF8000FFFE0001)) \n \\cnt_read[5]_i_2__0 \n (.I0(cnt_read_reg__1[1]),\n .I1(\\cnt_read[5]_i_3_n_0 ),\n .I2(cnt_read_reg__1[2]),\n .I3(cnt_read_reg__1[3]),\n .I4(cnt_read_reg__0),\n .I5(cnt_read_reg__1[4]),\n .O(\\cnt_read[5]_i_2__0_n_0 ));\n LUT6 #(\n .INIT(64'h00088888AAAEEEEE)) \n \\cnt_read[5]_i_3 \n (.I0(cnt_read_reg__1[0]),\n .I1(app_rd_data_valid),\n .I2(s_axi_rready),\n .I3(\\trans_buf_out_r_reg[0] ),\n .I4(rvalid04_in),\n .I5(cnt_read_reg__1[1]),\n .O(\\cnt_read[5]_i_3_n_0 ));\n (* ORIG_CELL_NAME = \"cnt_read_reg[0]\" *) \n FDSE #(\n .INIT(1'b1)) \n \\cnt_read_reg[0] \n (.C(CLK),\n .CE(\\cnt_read[5]_i_1_n_0 ),\n .D(\\cnt_read[0]_i_1_n_0 ),\n .Q(cnt_read_reg__1[0]),\n .S(areset_d1));\n (* ORIG_CELL_NAME = \"cnt_read_reg[0]\" *) \n FDSE #(\n .INIT(1'b1)) \n \\cnt_read_reg[0]_rep \n (.C(CLK),\n .CE(\\cnt_read[5]_i_1_n_0 ),\n .D(\\cnt_read[0]_rep_i_1_n_0 ),\n .Q(\\cnt_read_reg[0]_rep_n_0 ),\n .S(areset_d1));\n (* ORIG_CELL_NAME = \"cnt_read_reg[1]\" *) \n FDSE #(\n .INIT(1'b1)) \n \\cnt_read_reg[1] \n (.C(CLK),\n .CE(\\cnt_read[5]_i_1_n_0 ),\n .D(\\cnt_read[1]_i_1__0_n_0 ),\n .Q(cnt_read_reg__1[1]),\n .S(areset_d1));\n (* ORIG_CELL_NAME = \"cnt_read_reg[1]\" *) \n FDSE #(\n .INIT(1'b1)) \n \\cnt_read_reg[1]_rep \n (.C(CLK),\n .CE(\\cnt_read[5]_i_1_n_0 ),\n .D(\\cnt_read[1]_rep_i_1_n_0 ),\n .Q(\\cnt_read_reg[1]_rep_n_0 ),\n .S(areset_d1));\n (* ORIG_CELL_NAME = \"cnt_read_reg[2]\" *) \n FDSE #(\n .INIT(1'b1)) \n \\cnt_read_reg[2] \n (.C(CLK),\n .CE(\\cnt_read[5]_i_1_n_0 ),\n .D(\\cnt_read[2]_i_1__1_n_0 ),\n .Q(cnt_read_reg__1[2]),\n .S(areset_d1));\n (* ORIG_CELL_NAME = \"cnt_read_reg[2]\" *) \n FDSE #(\n .INIT(1'b1)) \n \\cnt_read_reg[2]_rep \n (.C(CLK),\n .CE(\\cnt_read[5]_i_1_n_0 ),\n .D(\\cnt_read[2]_rep_i_1_n_0 ),\n .Q(\\cnt_read_reg[2]_rep_n_0 ),\n .S(areset_d1));\n (* ORIG_CELL_NAME = \"cnt_read_reg[3]\" *) \n FDSE #(\n .INIT(1'b1)) \n \\cnt_read_reg[3] \n (.C(CLK),\n .CE(\\cnt_read[5]_i_1_n_0 ),\n .D(\\cnt_read[3]_i_1__1_n_0 ),\n .Q(cnt_read_reg__1[3]),\n .S(areset_d1));\n (* ORIG_CELL_NAME = \"cnt_read_reg[3]\" *) \n FDSE #(\n .INIT(1'b1)) \n \\cnt_read_reg[3]_rep \n (.C(CLK),\n .CE(\\cnt_read[5]_i_1_n_0 ),\n .D(\\cnt_read[3]_rep_i_1_n_0 ),\n .Q(\\cnt_read_reg[3]_rep_n_0 ),\n .S(areset_d1));\n (* ORIG_CELL_NAME = \"cnt_read_reg[4]\" *) \n FDSE #(\n .INIT(1'b1)) \n \\cnt_read_reg[4] \n (.C(CLK),\n .CE(\\cnt_read[5]_i_1_n_0 ),\n .D(\\cnt_read[4]_i_1__0_n_0 ),\n .Q(cnt_read_reg__1[4]),\n .S(areset_d1));\n (* ORIG_CELL_NAME = \"cnt_read_reg[4]\" *) \n FDSE #(\n .INIT(1'b1)) \n \\cnt_read_reg[4]_rep \n (.C(CLK),\n .CE(\\cnt_read[5]_i_1_n_0 ),\n .D(\\cnt_read[4]_rep_i_1_n_0 ),\n .Q(\\cnt_read_reg[4]_rep_n_0 ),\n .S(areset_d1));\n FDSE #(\n .INIT(1'b1)) \n \\cnt_read_reg[5] \n (.C(CLK),\n .CE(\\cnt_read[5]_i_1_n_0 ),\n .D(\\cnt_read[5]_i_2__0_n_0 ),\n .Q(cnt_read_reg__0),\n .S(areset_d1));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][0]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[0]),\n .Q(\\s_axi_rresp[1] [0]),\n .Q31(\\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][100]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][100]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[100]),\n .Q(\\s_axi_rresp[1] [100]),\n .Q31(\\NLW_memory_reg[31][100]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][101]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][101]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[101]),\n .Q(\\s_axi_rresp[1] [101]),\n .Q31(\\NLW_memory_reg[31][101]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][102]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][102]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[102]),\n .Q(\\s_axi_rresp[1] [102]),\n .Q31(\\NLW_memory_reg[31][102]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][103]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][103]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[103]),\n .Q(\\s_axi_rresp[1] [103]),\n .Q31(\\NLW_memory_reg[31][103]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][104]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][104]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[104]),\n .Q(\\s_axi_rresp[1] [104]),\n .Q31(\\NLW_memory_reg[31][104]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][105]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][105]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[105]),\n .Q(\\s_axi_rresp[1] [105]),\n .Q31(\\NLW_memory_reg[31][105]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][106]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][106]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[106]),\n .Q(\\s_axi_rresp[1] [106]),\n .Q31(\\NLW_memory_reg[31][106]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][107]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][107]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[107]),\n .Q(\\s_axi_rresp[1] [107]),\n .Q31(\\NLW_memory_reg[31][107]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][108]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][108]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[108]),\n .Q(\\s_axi_rresp[1] [108]),\n .Q31(\\NLW_memory_reg[31][108]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][109]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][109]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[109]),\n .Q(\\s_axi_rresp[1] [109]),\n .Q31(\\NLW_memory_reg[31][109]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][10]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[10]),\n .Q(\\s_axi_rresp[1] [10]),\n .Q31(\\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][110]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][110]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[110]),\n .Q(\\s_axi_rresp[1] [110]),\n .Q31(\\NLW_memory_reg[31][110]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][111]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][111]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[111]),\n .Q(\\s_axi_rresp[1] [111]),\n .Q31(\\NLW_memory_reg[31][111]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][112]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][112]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[112]),\n .Q(\\s_axi_rresp[1] [112]),\n .Q31(\\NLW_memory_reg[31][112]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][113]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][113]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[113]),\n .Q(\\s_axi_rresp[1] [113]),\n .Q31(\\NLW_memory_reg[31][113]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][114]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][114]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[114]),\n .Q(\\s_axi_rresp[1] [114]),\n .Q31(\\NLW_memory_reg[31][114]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][115]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][115]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[115]),\n .Q(\\s_axi_rresp[1] [115]),\n .Q31(\\NLW_memory_reg[31][115]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][116]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][116]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[116]),\n .Q(\\s_axi_rresp[1] [116]),\n .Q31(\\NLW_memory_reg[31][116]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][117]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][117]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[117]),\n .Q(\\s_axi_rresp[1] [117]),\n .Q31(\\NLW_memory_reg[31][117]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][118]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][118]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[118]),\n .Q(\\s_axi_rresp[1] [118]),\n .Q31(\\NLW_memory_reg[31][118]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][119]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][119]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[119]),\n .Q(\\s_axi_rresp[1] [119]),\n .Q31(\\NLW_memory_reg[31][119]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][11]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[11]),\n .Q(\\s_axi_rresp[1] [11]),\n .Q31(\\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][120]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][120]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[120]),\n .Q(\\s_axi_rresp[1] [120]),\n .Q31(\\NLW_memory_reg[31][120]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][121]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][121]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[121]),\n .Q(\\s_axi_rresp[1] [121]),\n .Q31(\\NLW_memory_reg[31][121]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][122]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][122]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[122]),\n .Q(\\s_axi_rresp[1] [122]),\n .Q31(\\NLW_memory_reg[31][122]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][123]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][123]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[123]),\n .Q(\\s_axi_rresp[1] [123]),\n .Q31(\\NLW_memory_reg[31][123]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][124]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][124]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[124]),\n .Q(\\s_axi_rresp[1] [124]),\n .Q31(\\NLW_memory_reg[31][124]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][125]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][125]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[125]),\n .Q(\\s_axi_rresp[1] [125]),\n .Q31(\\NLW_memory_reg[31][125]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][126]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][126]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[126]),\n .Q(\\s_axi_rresp[1] [126]),\n .Q31(\\NLW_memory_reg[31][126]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][127]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][127]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[127]),\n .Q(\\s_axi_rresp[1] [127]),\n .Q31(\\NLW_memory_reg[31][127]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][128]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][128]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[128]),\n .Q(\\s_axi_rresp[1] [128]),\n .Q31(\\NLW_memory_reg[31][128]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][129]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][129]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[129]),\n .Q(\\s_axi_rresp[1] [129]),\n .Q31(\\NLW_memory_reg[31][129]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][12]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[12]),\n .Q(\\s_axi_rresp[1] [12]),\n .Q31(\\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][130]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][130]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[130]),\n .Q(\\s_axi_rresp[1] [130]),\n .Q31(\\NLW_memory_reg[31][130]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][131]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][131]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[131]),\n .Q(\\s_axi_rresp[1] [131]),\n .Q31(\\NLW_memory_reg[31][131]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][132]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][132]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[132]),\n .Q(\\s_axi_rresp[1] [132]),\n .Q31(\\NLW_memory_reg[31][132]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][133]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][133]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[133]),\n .Q(\\s_axi_rresp[1] [133]),\n .Q31(\\NLW_memory_reg[31][133]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][134]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][134]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[134]),\n .Q(\\s_axi_rresp[1] [134]),\n .Q31(\\NLW_memory_reg[31][134]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][135]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][135]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[135]),\n .Q(\\s_axi_rresp[1] [135]),\n .Q31(\\NLW_memory_reg[31][135]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][136]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][136]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[136]),\n .Q(\\s_axi_rresp[1] [136]),\n .Q31(\\NLW_memory_reg[31][136]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][137]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][137]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[137]),\n .Q(\\s_axi_rresp[1] [137]),\n .Q31(\\NLW_memory_reg[31][137]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][138]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][138]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[138]),\n .Q(\\s_axi_rresp[1] [138]),\n .Q31(\\NLW_memory_reg[31][138]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][139]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][139]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[139]),\n .Q(\\s_axi_rresp[1] [139]),\n .Q31(\\NLW_memory_reg[31][139]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][13]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[13]),\n .Q(\\s_axi_rresp[1] [13]),\n .Q31(\\NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][140]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][140]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[140]),\n .Q(\\s_axi_rresp[1] [140]),\n .Q31(\\NLW_memory_reg[31][140]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][141]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][141]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[141]),\n .Q(\\s_axi_rresp[1] [141]),\n .Q31(\\NLW_memory_reg[31][141]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][142]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][142]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[142]),\n .Q(\\s_axi_rresp[1] [142]),\n .Q31(\\NLW_memory_reg[31][142]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][143]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][143]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[143]),\n .Q(\\s_axi_rresp[1] [143]),\n .Q31(\\NLW_memory_reg[31][143]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][144]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][144]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[144]),\n .Q(\\s_axi_rresp[1] [144]),\n .Q31(\\NLW_memory_reg[31][144]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][145]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][145]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[145]),\n .Q(\\s_axi_rresp[1] [145]),\n .Q31(\\NLW_memory_reg[31][145]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][146]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][146]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[146]),\n .Q(\\s_axi_rresp[1] [146]),\n .Q31(\\NLW_memory_reg[31][146]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][147]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][147]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[147]),\n .Q(\\s_axi_rresp[1] [147]),\n .Q31(\\NLW_memory_reg[31][147]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][148]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][148]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[148]),\n .Q(\\s_axi_rresp[1] [148]),\n .Q31(\\NLW_memory_reg[31][148]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][149]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][149]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[149]),\n .Q(\\s_axi_rresp[1] [149]),\n .Q31(\\NLW_memory_reg[31][149]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][14]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[14]),\n .Q(\\s_axi_rresp[1] [14]),\n .Q31(\\NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][150]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][150]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[150]),\n .Q(\\s_axi_rresp[1] [150]),\n .Q31(\\NLW_memory_reg[31][150]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][151]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][151]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[151]),\n .Q(\\s_axi_rresp[1] [151]),\n .Q31(\\NLW_memory_reg[31][151]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][152]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][152]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[152]),\n .Q(\\s_axi_rresp[1] [152]),\n .Q31(\\NLW_memory_reg[31][152]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][153]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][153]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[153]),\n .Q(\\s_axi_rresp[1] [153]),\n .Q31(\\NLW_memory_reg[31][153]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][154]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][154]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[154]),\n .Q(\\s_axi_rresp[1] [154]),\n .Q31(\\NLW_memory_reg[31][154]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][155]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][155]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[155]),\n .Q(\\s_axi_rresp[1] [155]),\n .Q31(\\NLW_memory_reg[31][155]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][156]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][156]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[156]),\n .Q(\\s_axi_rresp[1] [156]),\n .Q31(\\NLW_memory_reg[31][156]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][157]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][157]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[157]),\n .Q(\\s_axi_rresp[1] [157]),\n .Q31(\\NLW_memory_reg[31][157]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][158]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][158]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[158]),\n .Q(\\s_axi_rresp[1] [158]),\n .Q31(\\NLW_memory_reg[31][158]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][159]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][159]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[159]),\n .Q(\\s_axi_rresp[1] [159]),\n .Q31(\\NLW_memory_reg[31][159]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][15]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[15]),\n .Q(\\s_axi_rresp[1] [15]),\n .Q31(\\NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][160]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][160]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[160]),\n .Q(\\s_axi_rresp[1] [160]),\n .Q31(\\NLW_memory_reg[31][160]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][161]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][161]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[161]),\n .Q(\\s_axi_rresp[1] [161]),\n .Q31(\\NLW_memory_reg[31][161]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][162]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][162]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[162]),\n .Q(\\s_axi_rresp[1] [162]),\n .Q31(\\NLW_memory_reg[31][162]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][163]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][163]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[163]),\n .Q(\\s_axi_rresp[1] [163]),\n .Q31(\\NLW_memory_reg[31][163]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][164]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][164]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[164]),\n .Q(\\s_axi_rresp[1] [164]),\n .Q31(\\NLW_memory_reg[31][164]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][165]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][165]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[165]),\n .Q(\\s_axi_rresp[1] [165]),\n .Q31(\\NLW_memory_reg[31][165]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][166]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][166]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[166]),\n .Q(\\s_axi_rresp[1] [166]),\n .Q31(\\NLW_memory_reg[31][166]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][167]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][167]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[167]),\n .Q(\\s_axi_rresp[1] [167]),\n .Q31(\\NLW_memory_reg[31][167]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][168]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][168]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[168]),\n .Q(\\s_axi_rresp[1] [168]),\n .Q31(\\NLW_memory_reg[31][168]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][169]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][169]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[169]),\n .Q(\\s_axi_rresp[1] [169]),\n .Q31(\\NLW_memory_reg[31][169]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][16]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[16]),\n .Q(\\s_axi_rresp[1] [16]),\n .Q31(\\NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][170]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][170]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[170]),\n .Q(\\s_axi_rresp[1] [170]),\n .Q31(\\NLW_memory_reg[31][170]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][171]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][171]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[171]),\n .Q(\\s_axi_rresp[1] [171]),\n .Q31(\\NLW_memory_reg[31][171]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][172]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][172]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[172]),\n .Q(\\s_axi_rresp[1] [172]),\n .Q31(\\NLW_memory_reg[31][172]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][173]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][173]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[173]),\n .Q(\\s_axi_rresp[1] [173]),\n .Q31(\\NLW_memory_reg[31][173]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][174]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][174]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[174]),\n .Q(\\s_axi_rresp[1] [174]),\n .Q31(\\NLW_memory_reg[31][174]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][175]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][175]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[175]),\n .Q(\\s_axi_rresp[1] [175]),\n .Q31(\\NLW_memory_reg[31][175]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][176]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][176]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[176]),\n .Q(\\s_axi_rresp[1] [176]),\n .Q31(\\NLW_memory_reg[31][176]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][177]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][177]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[177]),\n .Q(\\s_axi_rresp[1] [177]),\n .Q31(\\NLW_memory_reg[31][177]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][178]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][178]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[178]),\n .Q(\\s_axi_rresp[1] [178]),\n .Q31(\\NLW_memory_reg[31][178]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][179]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][179]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[179]),\n .Q(\\s_axi_rresp[1] [179]),\n .Q31(\\NLW_memory_reg[31][179]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][17]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[17]),\n .Q(\\s_axi_rresp[1] [17]),\n .Q31(\\NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][180]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][180]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[180]),\n .Q(\\s_axi_rresp[1] [180]),\n .Q31(\\NLW_memory_reg[31][180]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][181]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][181]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[181]),\n .Q(\\s_axi_rresp[1] [181]),\n .Q31(\\NLW_memory_reg[31][181]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][182]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][182]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[182]),\n .Q(\\s_axi_rresp[1] [182]),\n .Q31(\\NLW_memory_reg[31][182]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][183]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][183]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[183]),\n .Q(\\s_axi_rresp[1] [183]),\n .Q31(\\NLW_memory_reg[31][183]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][184]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][184]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[184]),\n .Q(\\s_axi_rresp[1] [184]),\n .Q31(\\NLW_memory_reg[31][184]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][185]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][185]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[185]),\n .Q(\\s_axi_rresp[1] [185]),\n .Q31(\\NLW_memory_reg[31][185]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][186]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][186]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[186]),\n .Q(\\s_axi_rresp[1] [186]),\n .Q31(\\NLW_memory_reg[31][186]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][187]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][187]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[187]),\n .Q(\\s_axi_rresp[1] [187]),\n .Q31(\\NLW_memory_reg[31][187]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][188]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][188]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[188]),\n .Q(\\s_axi_rresp[1] [188]),\n .Q31(\\NLW_memory_reg[31][188]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][189]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][189]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[189]),\n .Q(\\s_axi_rresp[1] [189]),\n .Q31(\\NLW_memory_reg[31][189]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][18]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[18]),\n .Q(\\s_axi_rresp[1] [18]),\n .Q31(\\NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][190]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][190]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[190]),\n .Q(\\s_axi_rresp[1] [190]),\n .Q31(\\NLW_memory_reg[31][190]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][191]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][191]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[191]),\n .Q(\\s_axi_rresp[1] [191]),\n .Q31(\\NLW_memory_reg[31][191]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][192]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][192]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[192]),\n .Q(\\s_axi_rresp[1] [192]),\n .Q31(\\NLW_memory_reg[31][192]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][193]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][193]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[193]),\n .Q(\\s_axi_rresp[1] [193]),\n .Q31(\\NLW_memory_reg[31][193]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][194]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][194]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[194]),\n .Q(\\s_axi_rresp[1] [194]),\n .Q31(\\NLW_memory_reg[31][194]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][195]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][195]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[195]),\n .Q(\\s_axi_rresp[1] [195]),\n .Q31(\\NLW_memory_reg[31][195]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][196]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][196]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[196]),\n .Q(\\s_axi_rresp[1] [196]),\n .Q31(\\NLW_memory_reg[31][196]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][197]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][197]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[197]),\n .Q(\\s_axi_rresp[1] [197]),\n .Q31(\\NLW_memory_reg[31][197]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][198]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][198]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[198]),\n .Q(\\s_axi_rresp[1] [198]),\n .Q31(\\NLW_memory_reg[31][198]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][199]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][199]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[199]),\n .Q(\\s_axi_rresp[1] [199]),\n .Q31(\\NLW_memory_reg[31][199]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][19]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[19]),\n .Q(\\s_axi_rresp[1] [19]),\n .Q31(\\NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][1]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[1]),\n .Q(\\s_axi_rresp[1] [1]),\n .Q31(\\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][200]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][200]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[200]),\n .Q(\\s_axi_rresp[1] [200]),\n .Q31(\\NLW_memory_reg[31][200]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][201]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][201]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[201]),\n .Q(\\s_axi_rresp[1] [201]),\n .Q31(\\NLW_memory_reg[31][201]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][202]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][202]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[202]),\n .Q(\\s_axi_rresp[1] [202]),\n .Q31(\\NLW_memory_reg[31][202]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][203]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][203]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[203]),\n .Q(\\s_axi_rresp[1] [203]),\n .Q31(\\NLW_memory_reg[31][203]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][204]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][204]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[204]),\n .Q(\\s_axi_rresp[1] [204]),\n .Q31(\\NLW_memory_reg[31][204]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][205]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][205]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[205]),\n .Q(\\s_axi_rresp[1] [205]),\n .Q31(\\NLW_memory_reg[31][205]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][206]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][206]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[206]),\n .Q(\\s_axi_rresp[1] [206]),\n .Q31(\\NLW_memory_reg[31][206]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][207]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][207]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[207]),\n .Q(\\s_axi_rresp[1] [207]),\n .Q31(\\NLW_memory_reg[31][207]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][208]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][208]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[208]),\n .Q(\\s_axi_rresp[1] [208]),\n .Q31(\\NLW_memory_reg[31][208]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][209]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][209]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[209]),\n .Q(\\s_axi_rresp[1] [209]),\n .Q31(\\NLW_memory_reg[31][209]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][20]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[20]),\n .Q(\\s_axi_rresp[1] [20]),\n .Q31(\\NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][210]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][210]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[210]),\n .Q(\\s_axi_rresp[1] [210]),\n .Q31(\\NLW_memory_reg[31][210]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][211]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][211]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[211]),\n .Q(\\s_axi_rresp[1] [211]),\n .Q31(\\NLW_memory_reg[31][211]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][212]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][212]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[212]),\n .Q(\\s_axi_rresp[1] [212]),\n .Q31(\\NLW_memory_reg[31][212]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][213]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][213]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[213]),\n .Q(\\s_axi_rresp[1] [213]),\n .Q31(\\NLW_memory_reg[31][213]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][214]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][214]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[214]),\n .Q(\\s_axi_rresp[1] [214]),\n .Q31(\\NLW_memory_reg[31][214]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][215]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][215]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[215]),\n .Q(\\s_axi_rresp[1] [215]),\n .Q31(\\NLW_memory_reg[31][215]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][216]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][216]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[216]),\n .Q(\\s_axi_rresp[1] [216]),\n .Q31(\\NLW_memory_reg[31][216]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][217]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][217]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[217]),\n .Q(\\s_axi_rresp[1] [217]),\n .Q31(\\NLW_memory_reg[31][217]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][218]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][218]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[218]),\n .Q(\\s_axi_rresp[1] [218]),\n .Q31(\\NLW_memory_reg[31][218]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][219]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][219]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[219]),\n .Q(\\s_axi_rresp[1] [219]),\n .Q31(\\NLW_memory_reg[31][219]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][21]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[21]),\n .Q(\\s_axi_rresp[1] [21]),\n .Q31(\\NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][220]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][220]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[220]),\n .Q(\\s_axi_rresp[1] [220]),\n .Q31(\\NLW_memory_reg[31][220]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][221]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][221]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[221]),\n .Q(\\s_axi_rresp[1] [221]),\n .Q31(\\NLW_memory_reg[31][221]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][222]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][222]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[222]),\n .Q(\\s_axi_rresp[1] [222]),\n .Q31(\\NLW_memory_reg[31][222]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][223]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][223]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[223]),\n .Q(\\s_axi_rresp[1] [223]),\n .Q31(\\NLW_memory_reg[31][223]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][224]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][224]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[224]),\n .Q(\\s_axi_rresp[1] [224]),\n .Q31(\\NLW_memory_reg[31][224]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][225]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][225]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[225]),\n .Q(\\s_axi_rresp[1] [225]),\n .Q31(\\NLW_memory_reg[31][225]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][226]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][226]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[226]),\n .Q(\\s_axi_rresp[1] [226]),\n .Q31(\\NLW_memory_reg[31][226]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][227]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][227]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[227]),\n .Q(\\s_axi_rresp[1] [227]),\n .Q31(\\NLW_memory_reg[31][227]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][228]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][228]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[228]),\n .Q(\\s_axi_rresp[1] [228]),\n .Q31(\\NLW_memory_reg[31][228]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][229]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][229]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[229]),\n .Q(\\s_axi_rresp[1] [229]),\n .Q31(\\NLW_memory_reg[31][229]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][22]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[22]),\n .Q(\\s_axi_rresp[1] [22]),\n .Q31(\\NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][230]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][230]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[230]),\n .Q(\\s_axi_rresp[1] [230]),\n .Q31(\\NLW_memory_reg[31][230]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][231]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][231]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[231]),\n .Q(\\s_axi_rresp[1] [231]),\n .Q31(\\NLW_memory_reg[31][231]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][232]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][232]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[232]),\n .Q(\\s_axi_rresp[1] [232]),\n .Q31(\\NLW_memory_reg[31][232]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][233]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][233]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[233]),\n .Q(\\s_axi_rresp[1] [233]),\n .Q31(\\NLW_memory_reg[31][233]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][234]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][234]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[234]),\n .Q(\\s_axi_rresp[1] [234]),\n .Q31(\\NLW_memory_reg[31][234]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][235]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][235]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[235]),\n .Q(\\s_axi_rresp[1] [235]),\n .Q31(\\NLW_memory_reg[31][235]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][236]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][236]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[236]),\n .Q(\\s_axi_rresp[1] [236]),\n .Q31(\\NLW_memory_reg[31][236]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][237]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][237]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[237]),\n .Q(\\s_axi_rresp[1] [237]),\n .Q31(\\NLW_memory_reg[31][237]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][238]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][238]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[238]),\n .Q(\\s_axi_rresp[1] [238]),\n .Q31(\\NLW_memory_reg[31][238]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][239]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][239]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[239]),\n .Q(\\s_axi_rresp[1] [239]),\n .Q31(\\NLW_memory_reg[31][239]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][23]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[23]),\n .Q(\\s_axi_rresp[1] [23]),\n .Q31(\\NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][240]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][240]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[240]),\n .Q(\\s_axi_rresp[1] [240]),\n .Q31(\\NLW_memory_reg[31][240]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][241]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][241]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[241]),\n .Q(\\s_axi_rresp[1] [241]),\n .Q31(\\NLW_memory_reg[31][241]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][242]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][242]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[242]),\n .Q(\\s_axi_rresp[1] [242]),\n .Q31(\\NLW_memory_reg[31][242]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][243]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][243]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[243]),\n .Q(\\s_axi_rresp[1] [243]),\n .Q31(\\NLW_memory_reg[31][243]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][244]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][244]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[244]),\n .Q(\\s_axi_rresp[1] [244]),\n .Q31(\\NLW_memory_reg[31][244]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][245]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][245]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[245]),\n .Q(\\s_axi_rresp[1] [245]),\n .Q31(\\NLW_memory_reg[31][245]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][246]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][246]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[246]),\n .Q(\\s_axi_rresp[1] [246]),\n .Q31(\\NLW_memory_reg[31][246]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][247]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][247]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[247]),\n .Q(\\s_axi_rresp[1] [247]),\n .Q31(\\NLW_memory_reg[31][247]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][248]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][248]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[248]),\n .Q(\\s_axi_rresp[1] [248]),\n .Q31(\\NLW_memory_reg[31][248]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][249]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][249]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[249]),\n .Q(\\s_axi_rresp[1] [249]),\n .Q31(\\NLW_memory_reg[31][249]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][24]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[24]),\n .Q(\\s_axi_rresp[1] [24]),\n .Q31(\\NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][250]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][250]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[250]),\n .Q(\\s_axi_rresp[1] [250]),\n .Q31(\\NLW_memory_reg[31][250]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][251]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][251]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[251]),\n .Q(\\s_axi_rresp[1] [251]),\n .Q31(\\NLW_memory_reg[31][251]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][252]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][252]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[252]),\n .Q(\\s_axi_rresp[1] [252]),\n .Q31(\\NLW_memory_reg[31][252]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][253]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][253]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[253]),\n .Q(\\s_axi_rresp[1] [253]),\n .Q31(\\NLW_memory_reg[31][253]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][254]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][254]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[254]),\n .Q(\\s_axi_rresp[1] [254]),\n .Q31(\\NLW_memory_reg[31][254]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][255]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][255]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[255]),\n .Q(\\s_axi_rresp[1] [255]),\n .Q31(\\NLW_memory_reg[31][255]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][256]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][256]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(1'b0),\n .Q(\\s_axi_rresp[1] [256]),\n .Q31(\\NLW_memory_reg[31][256]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][25]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[25]),\n .Q(\\s_axi_rresp[1] [25]),\n .Q31(\\NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][26]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[26]),\n .Q(\\s_axi_rresp[1] [26]),\n .Q31(\\NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][27]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[27]),\n .Q(\\s_axi_rresp[1] [27]),\n .Q31(\\NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][28]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[28]),\n .Q(\\s_axi_rresp[1] [28]),\n .Q31(\\NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][29]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[29]),\n .Q(\\s_axi_rresp[1] [29]),\n .Q31(\\NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][2]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[2]),\n .Q(\\s_axi_rresp[1] [2]),\n .Q31(\\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][30]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[30]),\n .Q(\\s_axi_rresp[1] [30]),\n .Q31(\\NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][31]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[31]),\n .Q(\\s_axi_rresp[1] [31]),\n .Q31(\\NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][32]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[32]),\n .Q(\\s_axi_rresp[1] [32]),\n .Q31(\\NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][33]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[33]),\n .Q(\\s_axi_rresp[1] [33]),\n .Q31(\\NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][34]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][34]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[34]),\n .Q(\\s_axi_rresp[1] [34]),\n .Q31(\\NLW_memory_reg[31][34]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][35]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][35]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[35]),\n .Q(\\s_axi_rresp[1] [35]),\n .Q31(\\NLW_memory_reg[31][35]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][36]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][36]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[36]),\n .Q(\\s_axi_rresp[1] [36]),\n .Q31(\\NLW_memory_reg[31][36]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][37]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][37]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[37]),\n .Q(\\s_axi_rresp[1] [37]),\n .Q31(\\NLW_memory_reg[31][37]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][38]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][38]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[38]),\n .Q(\\s_axi_rresp[1] [38]),\n .Q31(\\NLW_memory_reg[31][38]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][39]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][39]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[39]),\n .Q(\\s_axi_rresp[1] [39]),\n .Q31(\\NLW_memory_reg[31][39]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][3]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[3]),\n .Q(\\s_axi_rresp[1] [3]),\n .Q31(\\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][40]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][40]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[40]),\n .Q(\\s_axi_rresp[1] [40]),\n .Q31(\\NLW_memory_reg[31][40]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][41]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][41]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[41]),\n .Q(\\s_axi_rresp[1] [41]),\n .Q31(\\NLW_memory_reg[31][41]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][42]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][42]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[42]),\n .Q(\\s_axi_rresp[1] [42]),\n .Q31(\\NLW_memory_reg[31][42]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][43]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][43]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[43]),\n .Q(\\s_axi_rresp[1] [43]),\n .Q31(\\NLW_memory_reg[31][43]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][44]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][44]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[44]),\n .Q(\\s_axi_rresp[1] [44]),\n .Q31(\\NLW_memory_reg[31][44]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][45]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][45]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[45]),\n .Q(\\s_axi_rresp[1] [45]),\n .Q31(\\NLW_memory_reg[31][45]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][46]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][46]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[46]),\n .Q(\\s_axi_rresp[1] [46]),\n .Q31(\\NLW_memory_reg[31][46]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][47]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][47]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[47]),\n .Q(\\s_axi_rresp[1] [47]),\n .Q31(\\NLW_memory_reg[31][47]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][48]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][48]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[48]),\n .Q(\\s_axi_rresp[1] [48]),\n .Q31(\\NLW_memory_reg[31][48]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][49]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][49]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[49]),\n .Q(\\s_axi_rresp[1] [49]),\n .Q31(\\NLW_memory_reg[31][49]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][4]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[4]),\n .Q(\\s_axi_rresp[1] [4]),\n .Q31(\\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][50]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][50]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[50]),\n .Q(\\s_axi_rresp[1] [50]),\n .Q31(\\NLW_memory_reg[31][50]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][51]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][51]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[51]),\n .Q(\\s_axi_rresp[1] [51]),\n .Q31(\\NLW_memory_reg[31][51]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][52]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][52]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[52]),\n .Q(\\s_axi_rresp[1] [52]),\n .Q31(\\NLW_memory_reg[31][52]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][53]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][53]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[53]),\n .Q(\\s_axi_rresp[1] [53]),\n .Q31(\\NLW_memory_reg[31][53]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][54]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][54]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[54]),\n .Q(\\s_axi_rresp[1] [54]),\n .Q31(\\NLW_memory_reg[31][54]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][55]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][55]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[55]),\n .Q(\\s_axi_rresp[1] [55]),\n .Q31(\\NLW_memory_reg[31][55]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][56]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][56]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[56]),\n .Q(\\s_axi_rresp[1] [56]),\n .Q31(\\NLW_memory_reg[31][56]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][57]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][57]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[57]),\n .Q(\\s_axi_rresp[1] [57]),\n .Q31(\\NLW_memory_reg[31][57]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][58]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][58]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[58]),\n .Q(\\s_axi_rresp[1] [58]),\n .Q31(\\NLW_memory_reg[31][58]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][59]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][59]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[59]),\n .Q(\\s_axi_rresp[1] [59]),\n .Q31(\\NLW_memory_reg[31][59]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][5]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[5]),\n .Q(\\s_axi_rresp[1] [5]),\n .Q31(\\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][60]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][60]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[60]),\n .Q(\\s_axi_rresp[1] [60]),\n .Q31(\\NLW_memory_reg[31][60]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][61]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][61]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[61]),\n .Q(\\s_axi_rresp[1] [61]),\n .Q31(\\NLW_memory_reg[31][61]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][62]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][62]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[62]),\n .Q(\\s_axi_rresp[1] [62]),\n .Q31(\\NLW_memory_reg[31][62]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][63]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][63]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[63]),\n .Q(\\s_axi_rresp[1] [63]),\n .Q31(\\NLW_memory_reg[31][63]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][64]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][64]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[64]),\n .Q(\\s_axi_rresp[1] [64]),\n .Q31(\\NLW_memory_reg[31][64]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][65]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][65]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[65]),\n .Q(\\s_axi_rresp[1] [65]),\n .Q31(\\NLW_memory_reg[31][65]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][66]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][66]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[66]),\n .Q(\\s_axi_rresp[1] [66]),\n .Q31(\\NLW_memory_reg[31][66]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][67]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][67]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[67]),\n .Q(\\s_axi_rresp[1] [67]),\n .Q31(\\NLW_memory_reg[31][67]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][68]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][68]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[68]),\n .Q(\\s_axi_rresp[1] [68]),\n .Q31(\\NLW_memory_reg[31][68]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][69]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][69]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[69]),\n .Q(\\s_axi_rresp[1] [69]),\n .Q31(\\NLW_memory_reg[31][69]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][6]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[6]),\n .Q(\\s_axi_rresp[1] [6]),\n .Q31(\\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][70]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][70]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[70]),\n .Q(\\s_axi_rresp[1] [70]),\n .Q31(\\NLW_memory_reg[31][70]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][71]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][71]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[71]),\n .Q(\\s_axi_rresp[1] [71]),\n .Q31(\\NLW_memory_reg[31][71]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][72]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][72]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[72]),\n .Q(\\s_axi_rresp[1] [72]),\n .Q31(\\NLW_memory_reg[31][72]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][73]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][73]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[73]),\n .Q(\\s_axi_rresp[1] [73]),\n .Q31(\\NLW_memory_reg[31][73]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][74]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][74]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[74]),\n .Q(\\s_axi_rresp[1] [74]),\n .Q31(\\NLW_memory_reg[31][74]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][75]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][75]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[75]),\n .Q(\\s_axi_rresp[1] [75]),\n .Q31(\\NLW_memory_reg[31][75]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][76]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][76]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[76]),\n .Q(\\s_axi_rresp[1] [76]),\n .Q31(\\NLW_memory_reg[31][76]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][77]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][77]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[77]),\n .Q(\\s_axi_rresp[1] [77]),\n .Q31(\\NLW_memory_reg[31][77]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][78]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][78]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[78]),\n .Q(\\s_axi_rresp[1] [78]),\n .Q31(\\NLW_memory_reg[31][78]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][79]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][79]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[79]),\n .Q(\\s_axi_rresp[1] [79]),\n .Q31(\\NLW_memory_reg[31][79]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][7]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[7]),\n .Q(\\s_axi_rresp[1] [7]),\n .Q31(\\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][80]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][80]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[80]),\n .Q(\\s_axi_rresp[1] [80]),\n .Q31(\\NLW_memory_reg[31][80]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][81]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][81]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[81]),\n .Q(\\s_axi_rresp[1] [81]),\n .Q31(\\NLW_memory_reg[31][81]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][82]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][82]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[82]),\n .Q(\\s_axi_rresp[1] [82]),\n .Q31(\\NLW_memory_reg[31][82]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][83]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][83]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[83]),\n .Q(\\s_axi_rresp[1] [83]),\n .Q31(\\NLW_memory_reg[31][83]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][84]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][84]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[84]),\n .Q(\\s_axi_rresp[1] [84]),\n .Q31(\\NLW_memory_reg[31][84]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][85]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][85]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[85]),\n .Q(\\s_axi_rresp[1] [85]),\n .Q31(\\NLW_memory_reg[31][85]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][86]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][86]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[86]),\n .Q(\\s_axi_rresp[1] [86]),\n .Q31(\\NLW_memory_reg[31][86]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][87]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][87]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[87]),\n .Q(\\s_axi_rresp[1] [87]),\n .Q31(\\NLW_memory_reg[31][87]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][88]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][88]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[88]),\n .Q(\\s_axi_rresp[1] [88]),\n .Q31(\\NLW_memory_reg[31][88]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][89]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][89]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[89]),\n .Q(\\s_axi_rresp[1] [89]),\n .Q31(\\NLW_memory_reg[31][89]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][8]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[8]),\n .Q(\\s_axi_rresp[1] [8]),\n .Q31(\\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][90]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][90]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[90]),\n .Q(\\s_axi_rresp[1] [90]),\n .Q31(\\NLW_memory_reg[31][90]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][91]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][91]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[91]),\n .Q(\\s_axi_rresp[1] [91]),\n .Q31(\\NLW_memory_reg[31][91]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][92]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][92]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[92]),\n .Q(\\s_axi_rresp[1] [92]),\n .Q31(\\NLW_memory_reg[31][92]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][93]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][93]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[93]),\n .Q(\\s_axi_rresp[1] [93]),\n .Q31(\\NLW_memory_reg[31][93]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][94]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][94]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[94]),\n .Q(\\s_axi_rresp[1] [94]),\n .Q31(\\NLW_memory_reg[31][94]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][95]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][95]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[95]),\n .Q(\\s_axi_rresp[1] [95]),\n .Q31(\\NLW_memory_reg[31][95]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][96]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][96]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[96]),\n .Q(\\s_axi_rresp[1] [96]),\n .Q31(\\NLW_memory_reg[31][96]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][97]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][97]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[97]),\n .Q(\\s_axi_rresp[1] [97]),\n .Q31(\\NLW_memory_reg[31][97]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][98]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][98]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[98]),\n .Q(\\s_axi_rresp[1] [98]),\n .Q31(\\NLW_memory_reg[31][98]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][99]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][99]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[99]),\n .Q(\\s_axi_rresp[1] [99]),\n .Q31(\\NLW_memory_reg[31][99]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][9]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[9]),\n .Q(\\s_axi_rresp[1] [9]),\n .Q31(\\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ));\n LUT6 #(\n .INIT(64'h00B8000000B800B8)) \n r_push_i_2\n (.I0(s_axi_arvalid),\n .I1(s_axi_arready),\n .I2(axvalid),\n .I3(\\cnt_read_reg[5]_0 ),\n .I4(cnt_read_reg__0),\n .I5(r_push_i_4_n_0),\n .O(rd_cmd_en));\n (* SOFT_HLUTNM = \"soft_lutpair1159\" *) \n LUT4 #(\n .INIT(16'h8000)) \n r_push_i_4\n (.I0(cnt_read_reg__1[2]),\n .I1(cnt_read_reg__1[1]),\n .I2(cnt_read_reg__1[4]),\n .I3(cnt_read_reg__1[3]),\n .O(r_push_i_4_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1161\" *) \n LUT2 #(\n .INIT(4'h2)) \n s_axi_rvalid_INST_0\n (.I0(rvalid04_in),\n .I1(\\trans_buf_out_r_reg[0] ),\n .O(s_axi_rvalid));\n LUT6 #(\n .INIT(64'h7FFFFFFFFFFFFFFF)) \n s_axi_rvalid_INST_0_i_1\n (.I0(cnt_read_reg__1[2]),\n .I1(cnt_read_reg__1[1]),\n .I2(cnt_read_reg__1[4]),\n .I3(cnt_read_reg__1[3]),\n .I4(cnt_read_reg__0),\n .I5(cnt_read_reg__1[0]),\n .O(rvalid04_in));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_axi_mc_fifo\" *) \nmodule ddr3_ifmig_7series_v4_0_axi_mc_fifo__parameterized1\n (E,\n tr_empty,\n \\RD_PRI_REG_STARVE.rd_starve_cnt_reg[8] ,\n \\trans_buf_out_r_reg[0] ,\n \\trans_buf_out_r1_reg[3] ,\n \\trans_buf_out_r_reg[2] ,\n \\trans_buf_out_r_reg[3] ,\n out,\n p_0_in,\n r_push,\n Q,\n \\trans_buf_out_r_reg[0]_0 ,\n assert_rlast,\n s_axi_rid,\n CLK,\n in,\n areset_d1);\n output [0:0]E;\n output tr_empty;\n output \\RD_PRI_REG_STARVE.rd_starve_cnt_reg[8] ;\n output \\trans_buf_out_r_reg[0] ;\n output [2:0]\\trans_buf_out_r1_reg[3] ;\n output \\trans_buf_out_r_reg[2] ;\n output \\trans_buf_out_r_reg[3] ;\n input [1:0]out;\n input p_0_in;\n input r_push;\n input [2:0]Q;\n input \\trans_buf_out_r_reg[0]_0 ;\n input assert_rlast;\n input [0:0]s_axi_rid;\n input CLK;\n input [1:0]in;\n input areset_d1;\n\n wire CLK;\n wire [0:0]E;\n wire [2:0]Q;\n wire \\RD_PRI_REG_STARVE.rd_starve_cnt_reg[8] ;\n wire areset_d1;\n wire assert_rlast;\n wire \\cnt_read[0]_i_1__0_n_0 ;\n wire \\cnt_read[1]_i_1__1_n_0 ;\n wire \\cnt_read[2]_i_1_n_0 ;\n wire \\cnt_read[3]_i_1_n_0 ;\n wire \\cnt_read[4]_i_1_n_0 ;\n wire \\cnt_read[5]_i_1__0_n_0 ;\n wire \\cnt_read[5]_i_2_n_0 ;\n wire \\cnt_read[5]_i_3__0_n_0 ;\n wire [4:0]cnt_read_reg__0;\n wire [5:5]cnt_read_reg__0__0;\n wire [1:0]in;\n wire load_stage1;\n wire [1:0]out;\n wire p_0_in;\n wire r_push;\n wire [0:0]s_axi_rid;\n wire tr_empty;\n wire [2:0]\\trans_buf_out_r1_reg[3] ;\n wire \\trans_buf_out_r_reg[0] ;\n wire \\trans_buf_out_r_reg[0]_0 ;\n wire \\trans_buf_out_r_reg[2] ;\n wire \\trans_buf_out_r_reg[3] ;\n wire \\NLW_memory_reg[29][0]_srl30_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[29][2]_srl30_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[29][3]_srl30_Q31_UNCONNECTED ;\n\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\FSM_sequential_state[1]_i_3 \n (.I0(cnt_read_reg__0[0]),\n .I1(cnt_read_reg__0[1]),\n .I2(cnt_read_reg__0__0),\n .I3(cnt_read_reg__0[2]),\n .I4(cnt_read_reg__0[3]),\n .I5(cnt_read_reg__0[4]),\n .O(tr_empty));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_read[0]_i_1__0 \n (.I0(cnt_read_reg__0[0]),\n .O(\\cnt_read[0]_i_1__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1162\" *) \n LUT5 #(\n .INIT(32'h56AAA955)) \n \\cnt_read[1]_i_1__1 \n (.I0(cnt_read_reg__0[0]),\n .I1(tr_empty),\n .I2(out[1]),\n .I3(r_push),\n .I4(cnt_read_reg__0[1]),\n .O(\\cnt_read[1]_i_1__1_n_0 ));\n LUT3 #(\n .INIT(8'h69)) \n \\cnt_read[2]_i_1 \n (.I0(\\cnt_read[5]_i_3__0_n_0 ),\n .I1(cnt_read_reg__0[2]),\n .I2(cnt_read_reg__0[1]),\n .O(\\cnt_read[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1163\" *) \n LUT4 #(\n .INIT(16'h78E1)) \n \\cnt_read[3]_i_1 \n (.I0(cnt_read_reg__0[1]),\n .I1(\\cnt_read[5]_i_3__0_n_0 ),\n .I2(cnt_read_reg__0[3]),\n .I3(cnt_read_reg__0[2]),\n .O(\\cnt_read[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1163\" *) \n LUT5 #(\n .INIT(32'h7F80FE01)) \n \\cnt_read[4]_i_1 \n (.I0(cnt_read_reg__0[1]),\n .I1(\\cnt_read[5]_i_3__0_n_0 ),\n .I2(cnt_read_reg__0[2]),\n .I3(cnt_read_reg__0[4]),\n .I4(cnt_read_reg__0[3]),\n .O(\\cnt_read[4]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hE1)) \n \\cnt_read[5]_i_1__0 \n (.I0(tr_empty),\n .I1(out[1]),\n .I2(r_push),\n .O(\\cnt_read[5]_i_1__0_n_0 ));\n LUT6 #(\n .INIT(64'h7FFF8000FFFE0001)) \n \\cnt_read[5]_i_2 \n (.I0(cnt_read_reg__0[1]),\n .I1(\\cnt_read[5]_i_3__0_n_0 ),\n .I2(cnt_read_reg__0[2]),\n .I3(cnt_read_reg__0[3]),\n .I4(cnt_read_reg__0__0),\n .I5(cnt_read_reg__0[4]),\n .O(\\cnt_read[5]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1162\" *) \n LUT5 #(\n .INIT(32'hA800FEAA)) \n \\cnt_read[5]_i_3__0 \n (.I0(cnt_read_reg__0[0]),\n .I1(tr_empty),\n .I2(out[1]),\n .I3(r_push),\n .I4(cnt_read_reg__0[1]),\n .O(\\cnt_read[5]_i_3__0_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\cnt_read_reg[0] \n (.C(CLK),\n .CE(\\cnt_read[5]_i_1__0_n_0 ),\n .D(\\cnt_read[0]_i_1__0_n_0 ),\n .Q(cnt_read_reg__0[0]),\n .S(areset_d1));\n FDSE #(\n .INIT(1'b1)) \n \\cnt_read_reg[1] \n (.C(CLK),\n .CE(\\cnt_read[5]_i_1__0_n_0 ),\n .D(\\cnt_read[1]_i_1__1_n_0 ),\n .Q(cnt_read_reg__0[1]),\n .S(areset_d1));\n FDSE #(\n .INIT(1'b1)) \n \\cnt_read_reg[2] \n (.C(CLK),\n .CE(\\cnt_read[5]_i_1__0_n_0 ),\n .D(\\cnt_read[2]_i_1_n_0 ),\n .Q(cnt_read_reg__0[2]),\n .S(areset_d1));\n FDSE #(\n .INIT(1'b1)) \n \\cnt_read_reg[3] \n (.C(CLK),\n .CE(\\cnt_read[5]_i_1__0_n_0 ),\n .D(\\cnt_read[3]_i_1_n_0 ),\n .Q(cnt_read_reg__0[3]),\n .S(areset_d1));\n FDSE #(\n .INIT(1'b1)) \n \\cnt_read_reg[4] \n (.C(CLK),\n .CE(\\cnt_read[5]_i_1__0_n_0 ),\n .D(\\cnt_read[4]_i_1_n_0 ),\n .Q(cnt_read_reg__0[4]),\n .S(areset_d1));\n FDSE #(\n .INIT(1'b1)) \n \\cnt_read_reg[5] \n (.C(CLK),\n .CE(\\cnt_read[5]_i_1__0_n_0 ),\n .D(\\cnt_read[5]_i_2_n_0 ),\n .Q(cnt_read_reg__0__0),\n .S(areset_d1));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/transaction_fifo_0/memory_reg[29] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/transaction_fifo_0/memory_reg[29][0]_srl30 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[29][0]_srl30 \n (.A(cnt_read_reg__0),\n .CE(r_push),\n .CLK(CLK),\n .D(1'b0),\n .Q(\\trans_buf_out_r1_reg[3] [0]),\n .Q31(\\NLW_memory_reg[29][0]_srl30_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/transaction_fifo_0/memory_reg[29] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/transaction_fifo_0/memory_reg[29][2]_srl30 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[29][2]_srl30 \n (.A(cnt_read_reg__0),\n .CE(r_push),\n .CLK(CLK),\n .D(in[0]),\n .Q(\\trans_buf_out_r1_reg[3] [1]),\n .Q31(\\NLW_memory_reg[29][2]_srl30_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/transaction_fifo_0/memory_reg[29] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/transaction_fifo_0/memory_reg[29][3]_srl30 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[29][3]_srl30 \n (.A(cnt_read_reg__0),\n .CE(r_push),\n .CLK(CLK),\n .D(in[1]),\n .Q(\\trans_buf_out_r1_reg[3] [2]),\n .Q31(\\NLW_memory_reg[29][3]_srl30_Q31_UNCONNECTED ));\n LUT5 #(\n .INIT(32'h10000000)) \n r_push_i_3\n (.I0(cnt_read_reg__0__0),\n .I1(cnt_read_reg__0[1]),\n .I2(cnt_read_reg__0[2]),\n .I3(cnt_read_reg__0[3]),\n .I4(cnt_read_reg__0[4]),\n .O(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg[8] ));\n (* SOFT_HLUTNM = \"soft_lutpair1164\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\trans_buf_out_r1[3]_i_1 \n (.I0(out[1]),\n .I1(tr_empty),\n .O(E));\n LUT6 #(\n .INIT(64'hFB08FFFFFB080000)) \n \\trans_buf_out_r[0]_i_1 \n (.I0(Q[0]),\n .I1(out[1]),\n .I2(out[0]),\n .I3(\\trans_buf_out_r1_reg[3] [0]),\n .I4(load_stage1),\n .I5(\\trans_buf_out_r_reg[0]_0 ),\n .O(\\trans_buf_out_r_reg[0] ));\n LUT6 #(\n .INIT(64'hFB08FFFFFB080000)) \n \\trans_buf_out_r[2]_i_1 \n (.I0(Q[1]),\n .I1(out[1]),\n .I2(out[0]),\n .I3(\\trans_buf_out_r1_reg[3] [1]),\n .I4(load_stage1),\n .I5(assert_rlast),\n .O(\\trans_buf_out_r_reg[2] ));\n LUT6 #(\n .INIT(64'hFB08FFFFFB080000)) \n \\trans_buf_out_r[3]_i_1 \n (.I0(Q[2]),\n .I1(out[1]),\n .I2(out[0]),\n .I3(\\trans_buf_out_r1_reg[3] [2]),\n .I4(load_stage1),\n .I5(s_axi_rid),\n .O(\\trans_buf_out_r_reg[3] ));\n (* SOFT_HLUTNM = \"soft_lutpair1164\" *) \n LUT4 #(\n .INIT(16'h1D01)) \n \\trans_buf_out_r[3]_i_2 \n (.I0(tr_empty),\n .I1(out[1]),\n .I2(out[0]),\n .I3(p_0_in),\n .O(load_stage1));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_axi_mc_incr_cmd\" *) \nmodule ddr3_ifmig_7series_v4_0_axi_mc_incr_cmd\n (out,\n Q,\n \\app_addr_r1_reg[27] ,\n in0,\n axready_reg,\n S,\n axready_reg_0,\n areset_d1,\n E,\n D,\n CLK,\n axready_reg_1);\n output [29:0]out;\n output [7:0]Q;\n output [29:0]\\app_addr_r1_reg[27] ;\n input [3:0]in0;\n input [24:0]axready_reg;\n input [0:0]S;\n input [0:0]axready_reg_0;\n input areset_d1;\n input [0:0]E;\n input [7:0]D;\n input CLK;\n input [29:0]axready_reg_1;\n\n wire CLK;\n wire [7:0]D;\n wire [0:0]E;\n wire [7:0]Q;\n wire [0:0]S;\n wire [29:0]\\app_addr_r1_reg[27] ;\n wire areset_d1;\n (* RTL_KEEP = \"true\" *) wire [29:0]axaddr_incr_p;\n wire axaddr_incr_p_reg0_carry__0_n_0;\n wire axaddr_incr_p_reg0_carry__0_n_1;\n wire axaddr_incr_p_reg0_carry__0_n_2;\n wire axaddr_incr_p_reg0_carry__0_n_3;\n wire axaddr_incr_p_reg0_carry__1_n_0;\n wire axaddr_incr_p_reg0_carry__1_n_1;\n wire axaddr_incr_p_reg0_carry__1_n_2;\n wire axaddr_incr_p_reg0_carry__1_n_3;\n wire axaddr_incr_p_reg0_carry__2_n_0;\n wire axaddr_incr_p_reg0_carry__2_n_1;\n wire axaddr_incr_p_reg0_carry__2_n_2;\n wire axaddr_incr_p_reg0_carry__2_n_3;\n wire axaddr_incr_p_reg0_carry__3_n_0;\n wire axaddr_incr_p_reg0_carry__3_n_1;\n wire axaddr_incr_p_reg0_carry__3_n_2;\n wire axaddr_incr_p_reg0_carry__3_n_3;\n wire axaddr_incr_p_reg0_carry__4_n_0;\n wire axaddr_incr_p_reg0_carry__4_n_1;\n wire axaddr_incr_p_reg0_carry__4_n_2;\n wire axaddr_incr_p_reg0_carry__4_n_3;\n wire axaddr_incr_p_reg0_carry__5_n_3;\n wire axaddr_incr_p_reg0_carry_n_0;\n wire axaddr_incr_p_reg0_carry_n_1;\n wire axaddr_incr_p_reg0_carry_n_2;\n wire axaddr_incr_p_reg0_carry_n_3;\n wire [24:0]axready_reg;\n wire [0:0]axready_reg_0;\n wire [29:0]axready_reg_1;\n wire [3:1]NLW_axaddr_incr_p_reg0_carry__5_CO_UNCONNECTED;\n wire [3:2]NLW_axaddr_incr_p_reg0_carry__5_O_UNCONNECTED;\n\n assign axaddr_incr_p[3:0] = in0[3:0];\n assign out[29:0] = axaddr_incr_p;\n CARRY4 axaddr_incr_p_reg0_carry\n (.CI(1'b0),\n .CO({axaddr_incr_p_reg0_carry_n_0,axaddr_incr_p_reg0_carry_n_1,axaddr_incr_p_reg0_carry_n_2,axaddr_incr_p_reg0_carry_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,axready_reg[1],1'b0}),\n .O(axaddr_incr_p[7:4]),\n .S({axready_reg[3:2],S,axready_reg[0]}));\n CARRY4 axaddr_incr_p_reg0_carry__0\n (.CI(axaddr_incr_p_reg0_carry_n_0),\n .CO({axaddr_incr_p_reg0_carry__0_n_0,axaddr_incr_p_reg0_carry__0_n_1,axaddr_incr_p_reg0_carry__0_n_2,axaddr_incr_p_reg0_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(axaddr_incr_p[11:8]),\n .S({axready_reg[6:4],axready_reg_0}));\n CARRY4 axaddr_incr_p_reg0_carry__1\n (.CI(axaddr_incr_p_reg0_carry__0_n_0),\n .CO({axaddr_incr_p_reg0_carry__1_n_0,axaddr_incr_p_reg0_carry__1_n_1,axaddr_incr_p_reg0_carry__1_n_2,axaddr_incr_p_reg0_carry__1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(axaddr_incr_p[15:12]),\n .S(axready_reg[10:7]));\n CARRY4 axaddr_incr_p_reg0_carry__2\n (.CI(axaddr_incr_p_reg0_carry__1_n_0),\n .CO({axaddr_incr_p_reg0_carry__2_n_0,axaddr_incr_p_reg0_carry__2_n_1,axaddr_incr_p_reg0_carry__2_n_2,axaddr_incr_p_reg0_carry__2_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(axaddr_incr_p[19:16]),\n .S(axready_reg[14:11]));\n CARRY4 axaddr_incr_p_reg0_carry__3\n (.CI(axaddr_incr_p_reg0_carry__2_n_0),\n .CO({axaddr_incr_p_reg0_carry__3_n_0,axaddr_incr_p_reg0_carry__3_n_1,axaddr_incr_p_reg0_carry__3_n_2,axaddr_incr_p_reg0_carry__3_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(axaddr_incr_p[23:20]),\n .S(axready_reg[18:15]));\n CARRY4 axaddr_incr_p_reg0_carry__4\n (.CI(axaddr_incr_p_reg0_carry__3_n_0),\n .CO({axaddr_incr_p_reg0_carry__4_n_0,axaddr_incr_p_reg0_carry__4_n_1,axaddr_incr_p_reg0_carry__4_n_2,axaddr_incr_p_reg0_carry__4_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(axaddr_incr_p[27:24]),\n .S(axready_reg[22:19]));\n CARRY4 axaddr_incr_p_reg0_carry__5\n (.CI(axaddr_incr_p_reg0_carry__4_n_0),\n .CO({NLW_axaddr_incr_p_reg0_carry__5_CO_UNCONNECTED[3:1],axaddr_incr_p_reg0_carry__5_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({NLW_axaddr_incr_p_reg0_carry__5_O_UNCONNECTED[3:2],axaddr_incr_p[29:28]}),\n .S({1'b0,1'b0,axready_reg[24:23]}));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[0] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[0]),\n .Q(\\app_addr_r1_reg[27] [0]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[10] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[10]),\n .Q(\\app_addr_r1_reg[27] [10]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[11] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[11]),\n .Q(\\app_addr_r1_reg[27] [11]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[12] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[12]),\n .Q(\\app_addr_r1_reg[27] [12]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[13] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[13]),\n .Q(\\app_addr_r1_reg[27] [13]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[14] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[14]),\n .Q(\\app_addr_r1_reg[27] [14]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[15] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[15]),\n .Q(\\app_addr_r1_reg[27] [15]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[16] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[16]),\n .Q(\\app_addr_r1_reg[27] [16]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[17] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[17]),\n .Q(\\app_addr_r1_reg[27] [17]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[18] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[18]),\n .Q(\\app_addr_r1_reg[27] [18]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[19] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[19]),\n .Q(\\app_addr_r1_reg[27] [19]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[1] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[1]),\n .Q(\\app_addr_r1_reg[27] [1]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[20] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[20]),\n .Q(\\app_addr_r1_reg[27] [20]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[21] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[21]),\n .Q(\\app_addr_r1_reg[27] [21]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[22] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[22]),\n .Q(\\app_addr_r1_reg[27] [22]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[23] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[23]),\n .Q(\\app_addr_r1_reg[27] [23]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[24] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[24]),\n .Q(\\app_addr_r1_reg[27] [24]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[25] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[25]),\n .Q(\\app_addr_r1_reg[27] [25]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[26] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[26]),\n .Q(\\app_addr_r1_reg[27] [26]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[27] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[27]),\n .Q(\\app_addr_r1_reg[27] [27]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[28] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[28]),\n .Q(\\app_addr_r1_reg[27] [28]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[29] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[29]),\n .Q(\\app_addr_r1_reg[27] [29]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[2] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[2]),\n .Q(\\app_addr_r1_reg[27] [2]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[3] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[3]),\n .Q(\\app_addr_r1_reg[27] [3]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[4] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[4]),\n .Q(\\app_addr_r1_reg[27] [4]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[5] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[5]),\n .Q(\\app_addr_r1_reg[27] [5]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[6] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[6]),\n .Q(\\app_addr_r1_reg[27] [6]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[7] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[7]),\n .Q(\\app_addr_r1_reg[27] [7]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[8] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[8]),\n .Q(\\app_addr_r1_reg[27] [8]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[9] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[9]),\n .Q(\\app_addr_r1_reg[27] [9]),\n .R(areset_d1));\n FDSE #(\n .INIT(1'b1)) \n \\axlen_cnt_reg[0] \n (.C(CLK),\n .CE(E),\n .D(D[0]),\n .Q(Q[0]),\n .S(areset_d1));\n FDSE #(\n .INIT(1'b1)) \n \\axlen_cnt_reg[1] \n (.C(CLK),\n .CE(E),\n .D(D[1]),\n .Q(Q[1]),\n .S(areset_d1));\n FDSE #(\n .INIT(1'b1)) \n \\axlen_cnt_reg[2] \n (.C(CLK),\n .CE(E),\n .D(D[2]),\n .Q(Q[2]),\n .S(areset_d1));\n FDSE #(\n .INIT(1'b1)) \n \\axlen_cnt_reg[3] \n (.C(CLK),\n .CE(E),\n .D(D[3]),\n .Q(Q[3]),\n .S(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axlen_cnt_reg[4] \n (.C(CLK),\n .CE(E),\n .D(D[4]),\n .Q(Q[4]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axlen_cnt_reg[5] \n (.C(CLK),\n .CE(E),\n .D(D[5]),\n .Q(Q[5]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axlen_cnt_reg[6] \n (.C(CLK),\n .CE(E),\n .D(D[6]),\n .Q(Q[6]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axlen_cnt_reg[7] \n (.C(CLK),\n .CE(E),\n .D(D[7]),\n .Q(Q[7]),\n .R(areset_d1));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_axi_mc_incr_cmd\" *) \nmodule ddr3_ifmig_7series_v4_0_axi_mc_incr_cmd__parameterized0\n (out,\n Q,\n \\app_addr_r1_reg[27] ,\n in0,\n DI,\n S,\n axready_reg,\n areset_d1,\n E,\n D,\n CLK,\n axready_reg_0);\n output [29:0]out;\n output [7:0]Q;\n output [29:0]\\app_addr_r1_reg[27] ;\n input [3:0]in0;\n input [0:0]DI;\n input [3:0]S;\n input [21:0]axready_reg;\n input areset_d1;\n input [0:0]E;\n input [7:0]D;\n input CLK;\n input [29:0]axready_reg_0;\n\n wire CLK;\n wire [7:0]D;\n wire [0:0]DI;\n wire [0:0]E;\n wire [7:0]Q;\n wire [3:0]S;\n wire [29:0]\\app_addr_r1_reg[27] ;\n wire areset_d1;\n (* RTL_KEEP = \"true\" *) wire [29:0]axaddr_incr_p;\n wire axaddr_incr_p_reg0_carry__0_n_0;\n wire axaddr_incr_p_reg0_carry__0_n_1;\n wire axaddr_incr_p_reg0_carry__0_n_2;\n wire axaddr_incr_p_reg0_carry__0_n_3;\n wire axaddr_incr_p_reg0_carry__1_n_0;\n wire axaddr_incr_p_reg0_carry__1_n_1;\n wire axaddr_incr_p_reg0_carry__1_n_2;\n wire axaddr_incr_p_reg0_carry__1_n_3;\n wire axaddr_incr_p_reg0_carry__2_n_0;\n wire axaddr_incr_p_reg0_carry__2_n_1;\n wire axaddr_incr_p_reg0_carry__2_n_2;\n wire axaddr_incr_p_reg0_carry__2_n_3;\n wire axaddr_incr_p_reg0_carry__3_n_0;\n wire axaddr_incr_p_reg0_carry__3_n_1;\n wire axaddr_incr_p_reg0_carry__3_n_2;\n wire axaddr_incr_p_reg0_carry__3_n_3;\n wire axaddr_incr_p_reg0_carry__4_n_0;\n wire axaddr_incr_p_reg0_carry__4_n_1;\n wire axaddr_incr_p_reg0_carry__4_n_2;\n wire axaddr_incr_p_reg0_carry__4_n_3;\n wire axaddr_incr_p_reg0_carry__5_n_3;\n wire axaddr_incr_p_reg0_carry_n_0;\n wire axaddr_incr_p_reg0_carry_n_1;\n wire axaddr_incr_p_reg0_carry_n_2;\n wire axaddr_incr_p_reg0_carry_n_3;\n wire [21:0]axready_reg;\n wire [29:0]axready_reg_0;\n wire [3:1]NLW_axaddr_incr_p_reg0_carry__5_CO_UNCONNECTED;\n wire [3:2]NLW_axaddr_incr_p_reg0_carry__5_O_UNCONNECTED;\n\n assign axaddr_incr_p[3:0] = in0[3:0];\n assign out[29:0] = axaddr_incr_p;\n CARRY4 axaddr_incr_p_reg0_carry\n (.CI(1'b0),\n .CO({axaddr_incr_p_reg0_carry_n_0,axaddr_incr_p_reg0_carry_n_1,axaddr_incr_p_reg0_carry_n_2,axaddr_incr_p_reg0_carry_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,DI,1'b0}),\n .O(axaddr_incr_p[7:4]),\n .S(S));\n CARRY4 axaddr_incr_p_reg0_carry__0\n (.CI(axaddr_incr_p_reg0_carry_n_0),\n .CO({axaddr_incr_p_reg0_carry__0_n_0,axaddr_incr_p_reg0_carry__0_n_1,axaddr_incr_p_reg0_carry__0_n_2,axaddr_incr_p_reg0_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(axaddr_incr_p[11:8]),\n .S(axready_reg[3:0]));\n CARRY4 axaddr_incr_p_reg0_carry__1\n (.CI(axaddr_incr_p_reg0_carry__0_n_0),\n .CO({axaddr_incr_p_reg0_carry__1_n_0,axaddr_incr_p_reg0_carry__1_n_1,axaddr_incr_p_reg0_carry__1_n_2,axaddr_incr_p_reg0_carry__1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(axaddr_incr_p[15:12]),\n .S(axready_reg[7:4]));\n CARRY4 axaddr_incr_p_reg0_carry__2\n (.CI(axaddr_incr_p_reg0_carry__1_n_0),\n .CO({axaddr_incr_p_reg0_carry__2_n_0,axaddr_incr_p_reg0_carry__2_n_1,axaddr_incr_p_reg0_carry__2_n_2,axaddr_incr_p_reg0_carry__2_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(axaddr_incr_p[19:16]),\n .S(axready_reg[11:8]));\n CARRY4 axaddr_incr_p_reg0_carry__3\n (.CI(axaddr_incr_p_reg0_carry__2_n_0),\n .CO({axaddr_incr_p_reg0_carry__3_n_0,axaddr_incr_p_reg0_carry__3_n_1,axaddr_incr_p_reg0_carry__3_n_2,axaddr_incr_p_reg0_carry__3_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(axaddr_incr_p[23:20]),\n .S(axready_reg[15:12]));\n CARRY4 axaddr_incr_p_reg0_carry__4\n (.CI(axaddr_incr_p_reg0_carry__3_n_0),\n .CO({axaddr_incr_p_reg0_carry__4_n_0,axaddr_incr_p_reg0_carry__4_n_1,axaddr_incr_p_reg0_carry__4_n_2,axaddr_incr_p_reg0_carry__4_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(axaddr_incr_p[27:24]),\n .S(axready_reg[19:16]));\n CARRY4 axaddr_incr_p_reg0_carry__5\n (.CI(axaddr_incr_p_reg0_carry__4_n_0),\n .CO({NLW_axaddr_incr_p_reg0_carry__5_CO_UNCONNECTED[3:1],axaddr_incr_p_reg0_carry__5_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({NLW_axaddr_incr_p_reg0_carry__5_O_UNCONNECTED[3:2],axaddr_incr_p[29:28]}),\n .S({1'b0,1'b0,axready_reg[21:20]}));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[0] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[0]),\n .Q(\\app_addr_r1_reg[27] [0]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[10] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[10]),\n .Q(\\app_addr_r1_reg[27] [10]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[11] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[11]),\n .Q(\\app_addr_r1_reg[27] [11]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[12] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[12]),\n .Q(\\app_addr_r1_reg[27] [12]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[13] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[13]),\n .Q(\\app_addr_r1_reg[27] [13]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[14] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[14]),\n .Q(\\app_addr_r1_reg[27] [14]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[15] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[15]),\n .Q(\\app_addr_r1_reg[27] [15]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[16] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[16]),\n .Q(\\app_addr_r1_reg[27] [16]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[17] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[17]),\n .Q(\\app_addr_r1_reg[27] [17]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[18] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[18]),\n .Q(\\app_addr_r1_reg[27] [18]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[19] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[19]),\n .Q(\\app_addr_r1_reg[27] [19]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[1] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[1]),\n .Q(\\app_addr_r1_reg[27] [1]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[20] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[20]),\n .Q(\\app_addr_r1_reg[27] [20]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[21] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[21]),\n .Q(\\app_addr_r1_reg[27] [21]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[22] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[22]),\n .Q(\\app_addr_r1_reg[27] [22]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[23] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[23]),\n .Q(\\app_addr_r1_reg[27] [23]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[24] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[24]),\n .Q(\\app_addr_r1_reg[27] [24]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[25] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[25]),\n .Q(\\app_addr_r1_reg[27] [25]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[26] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[26]),\n .Q(\\app_addr_r1_reg[27] [26]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[27] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[27]),\n .Q(\\app_addr_r1_reg[27] [27]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[28] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[28]),\n .Q(\\app_addr_r1_reg[27] [28]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[29] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[29]),\n .Q(\\app_addr_r1_reg[27] [29]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[2] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[2]),\n .Q(\\app_addr_r1_reg[27] [2]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[3] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[3]),\n .Q(\\app_addr_r1_reg[27] [3]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[4] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[4]),\n .Q(\\app_addr_r1_reg[27] [4]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[5] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[5]),\n .Q(\\app_addr_r1_reg[27] [5]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[6] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[6]),\n .Q(\\app_addr_r1_reg[27] [6]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[7] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[7]),\n .Q(\\app_addr_r1_reg[27] [7]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[8] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[8]),\n .Q(\\app_addr_r1_reg[27] [8]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axaddr_incr_reg[9] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[9]),\n .Q(\\app_addr_r1_reg[27] [9]),\n .R(areset_d1));\n FDSE #(\n .INIT(1'b1)) \n \\axlen_cnt_reg[0] \n (.C(CLK),\n .CE(E),\n .D(D[0]),\n .Q(Q[0]),\n .S(areset_d1));\n FDSE #(\n .INIT(1'b1)) \n \\axlen_cnt_reg[1] \n (.C(CLK),\n .CE(E),\n .D(D[1]),\n .Q(Q[1]),\n .S(areset_d1));\n FDSE #(\n .INIT(1'b1)) \n \\axlen_cnt_reg[2] \n (.C(CLK),\n .CE(E),\n .D(D[2]),\n .Q(Q[2]),\n .S(areset_d1));\n FDSE #(\n .INIT(1'b1)) \n \\axlen_cnt_reg[3] \n (.C(CLK),\n .CE(E),\n .D(D[3]),\n .Q(Q[3]),\n .S(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axlen_cnt_reg[4] \n (.C(CLK),\n .CE(E),\n .D(D[4]),\n .Q(Q[4]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axlen_cnt_reg[5] \n (.C(CLK),\n .CE(E),\n .D(D[5]),\n .Q(Q[5]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axlen_cnt_reg[6] \n (.C(CLK),\n .CE(E),\n .D(D[6]),\n .Q(Q[6]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\axlen_cnt_reg[7] \n (.C(CLK),\n .CE(E),\n .D(D[7]),\n .Q(Q[7]),\n .R(areset_d1));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_axi_mc_r_channel\" *) \nmodule ddr3_ifmig_7series_v4_0_axi_mc_r_channel\n (rd_cmd_en,\n E,\n s_axi_rvalid,\n s_axi_rlast,\n out,\n s_axi_rid,\n s_axi_arvalid,\n s_axi_arready,\n axvalid,\n app_rdy,\n app_rd_data_valid,\n s_axi_rready,\n r_push,\n Q,\n CLK,\n in,\n areset_d1);\n output rd_cmd_en;\n output [0:0]E;\n output s_axi_rvalid;\n output s_axi_rlast;\n output [256:0]out;\n output [0:0]s_axi_rid;\n input s_axi_arvalid;\n input s_axi_arready;\n input axvalid;\n input app_rdy;\n input app_rd_data_valid;\n input s_axi_rready;\n input r_push;\n input [255:0]Q;\n input CLK;\n input [1:0]in;\n input areset_d1;\n\n wire CLK;\n wire [0:0]E;\n wire [255:0]Q;\n wire app_rd_data_valid;\n wire app_rdy;\n wire areset_d1;\n wire assert_rlast;\n wire axvalid;\n wire [1:0]in;\n wire [256:0]out;\n wire p_0_in;\n wire r_push;\n wire rd_cmd_en;\n wire rd_data_fifo_0_n_4;\n wire rd_data_fifo_0_n_5;\n wire s_axi_arready;\n wire s_axi_arvalid;\n wire [0:0]s_axi_rid;\n wire s_axi_rlast;\n wire s_axi_rready;\n wire s_axi_rvalid;\n (* RTL_KEEP = \"yes\" *) wire [1:0]state;\n wire tr_empty;\n wire [3:0]trans_buf_out_r1;\n wire \\trans_buf_out_r_reg_n_0_[0] ;\n wire [3:0]trans_out;\n wire transaction_fifo_0_n_0;\n wire transaction_fifo_0_n_2;\n wire transaction_fifo_0_n_3;\n wire transaction_fifo_0_n_7;\n wire transaction_fifo_0_n_8;\n\n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\FSM_sequential_state_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data_fifo_0_n_5),\n .Q(state[0]),\n .R(areset_d1));\n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\FSM_sequential_state_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data_fifo_0_n_4),\n .Q(state[1]),\n .R(areset_d1));\n ddr3_ifmig_7series_v4_0_axi_mc_fifo__parameterized0 rd_data_fifo_0\n (.CLK(CLK),\n .E(E),\n .\\FSM_sequential_state_reg[0] (rd_data_fifo_0_n_5),\n .\\FSM_sequential_state_reg[1] (rd_data_fifo_0_n_4),\n .Q(Q),\n .app_rd_data_valid(app_rd_data_valid),\n .app_rdy(app_rdy),\n .areset_d1(areset_d1),\n .axvalid(axvalid),\n .\\cnt_read_reg[5]_0 (transaction_fifo_0_n_2),\n .in0(state),\n .out(state),\n .p_0_in(p_0_in),\n .rd_cmd_en(rd_cmd_en),\n .s_axi_arready(s_axi_arready),\n .s_axi_arvalid(s_axi_arvalid),\n .s_axi_rready(s_axi_rready),\n .\\s_axi_rresp[1] (out),\n .s_axi_rvalid(s_axi_rvalid),\n .tr_empty(tr_empty),\n .\\trans_buf_out_r_reg[0] (\\trans_buf_out_r_reg_n_0_[0] ));\n LUT2 #(\n .INIT(4'h2)) \n s_axi_rlast_INST_0\n (.I0(assert_rlast),\n .I1(\\trans_buf_out_r_reg_n_0_[0] ),\n .O(s_axi_rlast));\n FDRE #(\n .INIT(1'b0)) \n \\trans_buf_out_r1_reg[0] \n (.C(CLK),\n .CE(transaction_fifo_0_n_0),\n .D(trans_out[0]),\n .Q(trans_buf_out_r1[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\trans_buf_out_r1_reg[2] \n (.C(CLK),\n .CE(transaction_fifo_0_n_0),\n .D(trans_out[2]),\n .Q(trans_buf_out_r1[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\trans_buf_out_r1_reg[3] \n (.C(CLK),\n .CE(transaction_fifo_0_n_0),\n .D(trans_out[3]),\n .Q(trans_buf_out_r1[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\trans_buf_out_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(transaction_fifo_0_n_3),\n .Q(\\trans_buf_out_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\trans_buf_out_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(transaction_fifo_0_n_7),\n .Q(assert_rlast),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\trans_buf_out_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(transaction_fifo_0_n_8),\n .Q(s_axi_rid),\n .R(1'b0));\n ddr3_ifmig_7series_v4_0_axi_mc_fifo__parameterized1 transaction_fifo_0\n (.CLK(CLK),\n .E(transaction_fifo_0_n_0),\n .Q({trans_buf_out_r1[3:2],trans_buf_out_r1[0]}),\n .\\RD_PRI_REG_STARVE.rd_starve_cnt_reg[8] (transaction_fifo_0_n_2),\n .areset_d1(areset_d1),\n .assert_rlast(assert_rlast),\n .in(in),\n .out(state),\n .p_0_in(p_0_in),\n .r_push(r_push),\n .s_axi_rid(s_axi_rid),\n .tr_empty(tr_empty),\n .\\trans_buf_out_r1_reg[3] ({trans_out[3:2],trans_out[0]}),\n .\\trans_buf_out_r_reg[0] (transaction_fifo_0_n_3),\n .\\trans_buf_out_r_reg[0]_0 (\\trans_buf_out_r_reg_n_0_[0] ),\n .\\trans_buf_out_r_reg[2] (transaction_fifo_0_n_7),\n .\\trans_buf_out_r_reg[3] (transaction_fifo_0_n_8));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_axi_mc_w_channel\" *) \nmodule ddr3_ifmig_7series_v4_0_axi_mc_w_channel\n (wvalid_int,\n s_axi_wready,\n mc_app_wdf_wren_reg,\n app_wdf_mask,\n mc_app_wdf_mask_reg,\n D,\n app_wdf_data,\n mc_app_wdf_data_reg,\n \\mc_app_wdf_data_reg_reg[255]_0 ,\n areset_d1,\n CLK,\n app_wdf_rdy,\n \\RD_PRI_REG_STARVE.rnw_i_reg ,\n s_axi_wvalid,\n s_axi_wstrb,\n s_axi_wdata);\n output wvalid_int;\n output s_axi_wready;\n output mc_app_wdf_wren_reg;\n output [31:0]app_wdf_mask;\n output [31:0]mc_app_wdf_mask_reg;\n output [31:0]D;\n output [255:0]app_wdf_data;\n output [255:0]mc_app_wdf_data_reg;\n output [255:0]\\mc_app_wdf_data_reg_reg[255]_0 ;\n input areset_d1;\n input CLK;\n input app_wdf_rdy;\n input \\RD_PRI_REG_STARVE.rnw_i_reg ;\n input s_axi_wvalid;\n input [31:0]s_axi_wstrb;\n input [255:0]s_axi_wdata;\n\n wire CLK;\n wire [31:0]D;\n wire \\RD_PRI_REG_STARVE.rnw_i_reg ;\n wire [255:0]app_wdf_data;\n wire [31:0]app_wdf_mask;\n wire app_wdf_rdy;\n wire areset_d1;\n wire [255:0]mc_app_wdf_data_reg;\n wire [255:0]\\mc_app_wdf_data_reg_reg[255]_0 ;\n wire [31:0]mc_app_wdf_mask_reg;\n wire mc_app_wdf_wren_reg;\n wire [255:0]s_axi_wdata;\n wire s_axi_wready;\n wire [31:0]s_axi_wstrb;\n wire s_axi_wvalid;\n wire valid;\n wire [255:0]wdf_data;\n wire [31:0]wdf_mask;\n wire wready_i_1_n_0;\n wire wready_reg_rep__0_n_0;\n wire wready_reg_rep__1_n_0;\n wire wready_reg_rep__2_n_0;\n wire wready_reg_rep_n_0;\n wire wready_rep__0_i_1_n_0;\n wire wready_rep__1_i_1_n_0;\n wire wready_rep__2_i_1_n_0;\n wire wready_rep_i_1_n_0;\n wire wvalid_int;\n\n (* SOFT_HLUTNM = \"soft_lutpair1452\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[0]_i_1 \n (.I0(s_axi_wdata[0]),\n .I1(s_axi_wready),\n .I2(wdf_data[0]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[0]),\n .O(app_wdf_data[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1264\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[100]_i_1 \n (.I0(s_axi_wdata[100]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[100]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[100]),\n .O(app_wdf_data[100]));\n (* SOFT_HLUTNM = \"soft_lutpair1265\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[101]_i_1 \n (.I0(s_axi_wdata[101]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[101]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[101]),\n .O(app_wdf_data[101]));\n (* SOFT_HLUTNM = \"soft_lutpair1266\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[102]_i_1 \n (.I0(s_axi_wdata[102]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[102]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[102]),\n .O(app_wdf_data[102]));\n (* SOFT_HLUTNM = \"soft_lutpair1267\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[103]_i_1 \n (.I0(s_axi_wdata[103]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[103]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[103]),\n .O(app_wdf_data[103]));\n (* SOFT_HLUTNM = \"soft_lutpair1268\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[104]_i_1 \n (.I0(s_axi_wdata[104]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[104]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[104]),\n .O(app_wdf_data[104]));\n (* SOFT_HLUTNM = \"soft_lutpair1269\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[105]_i_1 \n (.I0(s_axi_wdata[105]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[105]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[105]),\n .O(app_wdf_data[105]));\n (* SOFT_HLUTNM = \"soft_lutpair1270\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[106]_i_1 \n (.I0(s_axi_wdata[106]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[106]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[106]),\n .O(app_wdf_data[106]));\n (* SOFT_HLUTNM = \"soft_lutpair1271\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[107]_i_1 \n (.I0(s_axi_wdata[107]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[107]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[107]),\n .O(app_wdf_data[107]));\n (* SOFT_HLUTNM = \"soft_lutpair1272\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[108]_i_1 \n (.I0(s_axi_wdata[108]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[108]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[108]),\n .O(app_wdf_data[108]));\n (* SOFT_HLUTNM = \"soft_lutpair1273\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[109]_i_1 \n (.I0(s_axi_wdata[109]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[109]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[109]),\n .O(app_wdf_data[109]));\n (* SOFT_HLUTNM = \"soft_lutpair1174\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[10]_i_1 \n (.I0(s_axi_wdata[10]),\n .I1(s_axi_wready),\n .I2(wdf_data[10]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[10]),\n .O(app_wdf_data[10]));\n (* SOFT_HLUTNM = \"soft_lutpair1274\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[110]_i_1 \n (.I0(s_axi_wdata[110]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[110]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[110]),\n .O(app_wdf_data[110]));\n (* SOFT_HLUTNM = \"soft_lutpair1275\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[111]_i_1 \n (.I0(s_axi_wdata[111]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[111]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[111]),\n .O(app_wdf_data[111]));\n (* SOFT_HLUTNM = \"soft_lutpair1276\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[112]_i_1 \n (.I0(s_axi_wdata[112]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[112]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[112]),\n .O(app_wdf_data[112]));\n (* SOFT_HLUTNM = \"soft_lutpair1277\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[113]_i_1 \n (.I0(s_axi_wdata[113]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[113]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[113]),\n .O(app_wdf_data[113]));\n (* SOFT_HLUTNM = \"soft_lutpair1278\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[114]_i_1 \n (.I0(s_axi_wdata[114]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[114]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[114]),\n .O(app_wdf_data[114]));\n (* SOFT_HLUTNM = \"soft_lutpair1279\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[115]_i_1 \n (.I0(s_axi_wdata[115]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[115]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[115]),\n .O(app_wdf_data[115]));\n (* SOFT_HLUTNM = \"soft_lutpair1280\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[116]_i_1 \n (.I0(s_axi_wdata[116]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[116]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[116]),\n .O(app_wdf_data[116]));\n (* SOFT_HLUTNM = \"soft_lutpair1281\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[117]_i_1 \n (.I0(s_axi_wdata[117]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[117]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[117]),\n .O(app_wdf_data[117]));\n (* SOFT_HLUTNM = \"soft_lutpair1282\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[118]_i_1 \n (.I0(s_axi_wdata[118]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[118]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[118]),\n .O(app_wdf_data[118]));\n (* SOFT_HLUTNM = \"soft_lutpair1283\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[119]_i_1 \n (.I0(s_axi_wdata[119]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[119]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[119]),\n .O(app_wdf_data[119]));\n (* SOFT_HLUTNM = \"soft_lutpair1175\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[11]_i_1 \n (.I0(s_axi_wdata[11]),\n .I1(s_axi_wready),\n .I2(wdf_data[11]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[11]),\n .O(app_wdf_data[11]));\n (* SOFT_HLUTNM = \"soft_lutpair1284\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[120]_i_1 \n (.I0(s_axi_wdata[120]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[120]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[120]),\n .O(app_wdf_data[120]));\n (* SOFT_HLUTNM = \"soft_lutpair1285\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[121]_i_1 \n (.I0(s_axi_wdata[121]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[121]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[121]),\n .O(app_wdf_data[121]));\n (* SOFT_HLUTNM = \"soft_lutpair1286\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[122]_i_1 \n (.I0(s_axi_wdata[122]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[122]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[122]),\n .O(app_wdf_data[122]));\n (* SOFT_HLUTNM = \"soft_lutpair1287\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[123]_i_1 \n (.I0(s_axi_wdata[123]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[123]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[123]),\n .O(app_wdf_data[123]));\n (* SOFT_HLUTNM = \"soft_lutpair1288\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[124]_i_1 \n (.I0(s_axi_wdata[124]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[124]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[124]),\n .O(app_wdf_data[124]));\n (* SOFT_HLUTNM = \"soft_lutpair1289\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[125]_i_1 \n (.I0(s_axi_wdata[125]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[125]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[125]),\n .O(app_wdf_data[125]));\n (* SOFT_HLUTNM = \"soft_lutpair1290\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[126]_i_1 \n (.I0(s_axi_wdata[126]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[126]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[126]),\n .O(app_wdf_data[126]));\n (* SOFT_HLUTNM = \"soft_lutpair1291\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[127]_i_1 \n (.I0(s_axi_wdata[127]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[127]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[127]),\n .O(app_wdf_data[127]));\n (* SOFT_HLUTNM = \"soft_lutpair1292\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[128]_i_1 \n (.I0(s_axi_wdata[128]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[128]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[128]),\n .O(app_wdf_data[128]));\n (* SOFT_HLUTNM = \"soft_lutpair1293\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[129]_i_1 \n (.I0(s_axi_wdata[129]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[129]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[129]),\n .O(app_wdf_data[129]));\n (* SOFT_HLUTNM = \"soft_lutpair1176\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[12]_i_1 \n (.I0(s_axi_wdata[12]),\n .I1(s_axi_wready),\n .I2(wdf_data[12]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[12]),\n .O(app_wdf_data[12]));\n (* SOFT_HLUTNM = \"soft_lutpair1294\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[130]_i_1 \n (.I0(s_axi_wdata[130]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[130]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[130]),\n .O(app_wdf_data[130]));\n (* SOFT_HLUTNM = \"soft_lutpair1295\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[131]_i_1 \n (.I0(s_axi_wdata[131]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[131]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[131]),\n .O(app_wdf_data[131]));\n (* SOFT_HLUTNM = \"soft_lutpair1296\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[132]_i_1 \n (.I0(s_axi_wdata[132]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[132]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[132]),\n .O(app_wdf_data[132]));\n (* SOFT_HLUTNM = \"soft_lutpair1297\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[133]_i_1 \n (.I0(s_axi_wdata[133]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[133]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[133]),\n .O(app_wdf_data[133]));\n (* SOFT_HLUTNM = \"soft_lutpair1298\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[134]_i_1 \n (.I0(s_axi_wdata[134]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[134]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[134]),\n .O(app_wdf_data[134]));\n (* SOFT_HLUTNM = \"soft_lutpair1299\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[135]_i_1 \n (.I0(s_axi_wdata[135]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[135]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[135]),\n .O(app_wdf_data[135]));\n (* SOFT_HLUTNM = \"soft_lutpair1300\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[136]_i_1 \n (.I0(s_axi_wdata[136]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[136]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[136]),\n .O(app_wdf_data[136]));\n (* SOFT_HLUTNM = \"soft_lutpair1301\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[137]_i_1 \n (.I0(s_axi_wdata[137]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[137]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[137]),\n .O(app_wdf_data[137]));\n (* SOFT_HLUTNM = \"soft_lutpair1302\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[138]_i_1 \n (.I0(s_axi_wdata[138]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[138]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[138]),\n .O(app_wdf_data[138]));\n (* SOFT_HLUTNM = \"soft_lutpair1303\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[139]_i_1 \n (.I0(s_axi_wdata[139]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[139]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[139]),\n .O(app_wdf_data[139]));\n (* SOFT_HLUTNM = \"soft_lutpair1177\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[13]_i_1 \n (.I0(s_axi_wdata[13]),\n .I1(s_axi_wready),\n .I2(wdf_data[13]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[13]),\n .O(app_wdf_data[13]));\n (* SOFT_HLUTNM = \"soft_lutpair1304\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[140]_i_1 \n (.I0(s_axi_wdata[140]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[140]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[140]),\n .O(app_wdf_data[140]));\n (* SOFT_HLUTNM = \"soft_lutpair1305\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[141]_i_1 \n (.I0(s_axi_wdata[141]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[141]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[141]),\n .O(app_wdf_data[141]));\n (* SOFT_HLUTNM = \"soft_lutpair1306\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[142]_i_1 \n (.I0(s_axi_wdata[142]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[142]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[142]),\n .O(app_wdf_data[142]));\n (* SOFT_HLUTNM = \"soft_lutpair1307\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[143]_i_1 \n (.I0(s_axi_wdata[143]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[143]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[143]),\n .O(app_wdf_data[143]));\n (* SOFT_HLUTNM = \"soft_lutpair1308\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[144]_i_1 \n (.I0(s_axi_wdata[144]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[144]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[144]),\n .O(app_wdf_data[144]));\n (* SOFT_HLUTNM = \"soft_lutpair1309\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[145]_i_1 \n (.I0(s_axi_wdata[145]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[145]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[145]),\n .O(app_wdf_data[145]));\n (* SOFT_HLUTNM = \"soft_lutpair1310\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[146]_i_1 \n (.I0(s_axi_wdata[146]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[146]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[146]),\n .O(app_wdf_data[146]));\n (* SOFT_HLUTNM = \"soft_lutpair1311\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[147]_i_1 \n (.I0(s_axi_wdata[147]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[147]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[147]),\n .O(app_wdf_data[147]));\n (* SOFT_HLUTNM = \"soft_lutpair1312\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[148]_i_1 \n (.I0(s_axi_wdata[148]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[148]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[148]),\n .O(app_wdf_data[148]));\n (* SOFT_HLUTNM = \"soft_lutpair1313\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[149]_i_1 \n (.I0(s_axi_wdata[149]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[149]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[149]),\n .O(app_wdf_data[149]));\n (* SOFT_HLUTNM = \"soft_lutpair1178\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[14]_i_1 \n (.I0(s_axi_wdata[14]),\n .I1(s_axi_wready),\n .I2(wdf_data[14]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[14]),\n .O(app_wdf_data[14]));\n (* SOFT_HLUTNM = \"soft_lutpair1314\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[150]_i_1 \n (.I0(s_axi_wdata[150]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[150]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[150]),\n .O(app_wdf_data[150]));\n (* SOFT_HLUTNM = \"soft_lutpair1315\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[151]_i_1 \n (.I0(s_axi_wdata[151]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[151]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[151]),\n .O(app_wdf_data[151]));\n (* SOFT_HLUTNM = \"soft_lutpair1316\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[152]_i_1 \n (.I0(s_axi_wdata[152]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[152]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[152]),\n .O(app_wdf_data[152]));\n (* SOFT_HLUTNM = \"soft_lutpair1317\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[153]_i_1 \n (.I0(s_axi_wdata[153]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[153]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[153]),\n .O(app_wdf_data[153]));\n (* SOFT_HLUTNM = \"soft_lutpair1318\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[154]_i_1 \n (.I0(s_axi_wdata[154]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[154]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[154]),\n .O(app_wdf_data[154]));\n (* SOFT_HLUTNM = \"soft_lutpair1319\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[155]_i_1 \n (.I0(s_axi_wdata[155]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[155]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[155]),\n .O(app_wdf_data[155]));\n (* SOFT_HLUTNM = \"soft_lutpair1320\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[156]_i_1 \n (.I0(s_axi_wdata[156]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[156]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[156]),\n .O(app_wdf_data[156]));\n (* SOFT_HLUTNM = \"soft_lutpair1321\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[157]_i_1 \n (.I0(s_axi_wdata[157]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[157]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[157]),\n .O(app_wdf_data[157]));\n (* SOFT_HLUTNM = \"soft_lutpair1322\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[158]_i_1 \n (.I0(s_axi_wdata[158]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[158]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[158]),\n .O(app_wdf_data[158]));\n (* SOFT_HLUTNM = \"soft_lutpair1323\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[159]_i_1 \n (.I0(s_axi_wdata[159]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[159]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[159]),\n .O(app_wdf_data[159]));\n (* SOFT_HLUTNM = \"soft_lutpair1179\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[15]_i_1 \n (.I0(s_axi_wdata[15]),\n .I1(s_axi_wready),\n .I2(wdf_data[15]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[15]),\n .O(app_wdf_data[15]));\n (* SOFT_HLUTNM = \"soft_lutpair1324\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[160]_i_1 \n (.I0(s_axi_wdata[160]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[160]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[160]),\n .O(app_wdf_data[160]));\n (* SOFT_HLUTNM = \"soft_lutpair1325\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[161]_i_1 \n (.I0(s_axi_wdata[161]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[161]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[161]),\n .O(app_wdf_data[161]));\n (* SOFT_HLUTNM = \"soft_lutpair1326\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[162]_i_1 \n (.I0(s_axi_wdata[162]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[162]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[162]),\n .O(app_wdf_data[162]));\n (* SOFT_HLUTNM = \"soft_lutpair1327\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[163]_i_1 \n (.I0(s_axi_wdata[163]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[163]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[163]),\n .O(app_wdf_data[163]));\n (* SOFT_HLUTNM = \"soft_lutpair1328\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[164]_i_1 \n (.I0(s_axi_wdata[164]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[164]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[164]),\n .O(app_wdf_data[164]));\n (* SOFT_HLUTNM = \"soft_lutpair1329\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[165]_i_1 \n (.I0(s_axi_wdata[165]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[165]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[165]),\n .O(app_wdf_data[165]));\n (* SOFT_HLUTNM = \"soft_lutpair1330\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[166]_i_1 \n (.I0(s_axi_wdata[166]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[166]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[166]),\n .O(app_wdf_data[166]));\n (* SOFT_HLUTNM = \"soft_lutpair1331\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[167]_i_1 \n (.I0(s_axi_wdata[167]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[167]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[167]),\n .O(app_wdf_data[167]));\n (* SOFT_HLUTNM = \"soft_lutpair1332\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[168]_i_1 \n (.I0(s_axi_wdata[168]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[168]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[168]),\n .O(app_wdf_data[168]));\n (* SOFT_HLUTNM = \"soft_lutpair1333\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[169]_i_1 \n (.I0(s_axi_wdata[169]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[169]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[169]),\n .O(app_wdf_data[169]));\n (* SOFT_HLUTNM = \"soft_lutpair1180\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[16]_i_1 \n (.I0(s_axi_wdata[16]),\n .I1(s_axi_wready),\n .I2(wdf_data[16]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[16]),\n .O(app_wdf_data[16]));\n (* SOFT_HLUTNM = \"soft_lutpair1334\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[170]_i_1 \n (.I0(s_axi_wdata[170]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[170]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[170]),\n .O(app_wdf_data[170]));\n (* SOFT_HLUTNM = \"soft_lutpair1335\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[171]_i_1 \n (.I0(s_axi_wdata[171]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[171]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[171]),\n .O(app_wdf_data[171]));\n (* SOFT_HLUTNM = \"soft_lutpair1336\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[172]_i_1 \n (.I0(s_axi_wdata[172]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[172]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[172]),\n .O(app_wdf_data[172]));\n (* SOFT_HLUTNM = \"soft_lutpair1337\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[173]_i_1 \n (.I0(s_axi_wdata[173]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[173]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[173]),\n .O(app_wdf_data[173]));\n (* SOFT_HLUTNM = \"soft_lutpair1338\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[174]_i_1 \n (.I0(s_axi_wdata[174]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[174]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[174]),\n .O(app_wdf_data[174]));\n (* SOFT_HLUTNM = \"soft_lutpair1339\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[175]_i_1 \n (.I0(s_axi_wdata[175]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[175]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[175]),\n .O(app_wdf_data[175]));\n (* SOFT_HLUTNM = \"soft_lutpair1340\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[176]_i_1 \n (.I0(s_axi_wdata[176]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[176]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[176]),\n .O(app_wdf_data[176]));\n (* SOFT_HLUTNM = \"soft_lutpair1341\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[177]_i_1 \n (.I0(s_axi_wdata[177]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[177]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[177]),\n .O(app_wdf_data[177]));\n (* SOFT_HLUTNM = \"soft_lutpair1342\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[178]_i_1 \n (.I0(s_axi_wdata[178]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[178]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[178]),\n .O(app_wdf_data[178]));\n (* SOFT_HLUTNM = \"soft_lutpair1343\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[179]_i_1 \n (.I0(s_axi_wdata[179]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[179]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[179]),\n .O(app_wdf_data[179]));\n (* SOFT_HLUTNM = \"soft_lutpair1181\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[17]_i_1 \n (.I0(s_axi_wdata[17]),\n .I1(s_axi_wready),\n .I2(wdf_data[17]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[17]),\n .O(app_wdf_data[17]));\n (* SOFT_HLUTNM = \"soft_lutpair1344\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[180]_i_1 \n (.I0(s_axi_wdata[180]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[180]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[180]),\n .O(app_wdf_data[180]));\n (* SOFT_HLUTNM = \"soft_lutpair1345\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[181]_i_1 \n (.I0(s_axi_wdata[181]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[181]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[181]),\n .O(app_wdf_data[181]));\n (* SOFT_HLUTNM = \"soft_lutpair1346\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[182]_i_1 \n (.I0(s_axi_wdata[182]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[182]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[182]),\n .O(app_wdf_data[182]));\n (* SOFT_HLUTNM = \"soft_lutpair1347\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[183]_i_1 \n (.I0(s_axi_wdata[183]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[183]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[183]),\n .O(app_wdf_data[183]));\n (* SOFT_HLUTNM = \"soft_lutpair1348\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[184]_i_1 \n (.I0(s_axi_wdata[184]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[184]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[184]),\n .O(app_wdf_data[184]));\n (* SOFT_HLUTNM = \"soft_lutpair1349\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[185]_i_1 \n (.I0(s_axi_wdata[185]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[185]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[185]),\n .O(app_wdf_data[185]));\n (* SOFT_HLUTNM = \"soft_lutpair1350\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[186]_i_1 \n (.I0(s_axi_wdata[186]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[186]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[186]),\n .O(app_wdf_data[186]));\n (* SOFT_HLUTNM = \"soft_lutpair1351\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[187]_i_1 \n (.I0(s_axi_wdata[187]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[187]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[187]),\n .O(app_wdf_data[187]));\n (* SOFT_HLUTNM = \"soft_lutpair1352\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[188]_i_1 \n (.I0(s_axi_wdata[188]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[188]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[188]),\n .O(app_wdf_data[188]));\n (* SOFT_HLUTNM = \"soft_lutpair1353\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[189]_i_1 \n (.I0(s_axi_wdata[189]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[189]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[189]),\n .O(app_wdf_data[189]));\n (* SOFT_HLUTNM = \"soft_lutpair1182\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[18]_i_1 \n (.I0(s_axi_wdata[18]),\n .I1(s_axi_wready),\n .I2(wdf_data[18]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[18]),\n .O(app_wdf_data[18]));\n (* SOFT_HLUTNM = \"soft_lutpair1354\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[190]_i_1 \n (.I0(s_axi_wdata[190]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[190]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[190]),\n .O(app_wdf_data[190]));\n (* SOFT_HLUTNM = \"soft_lutpair1355\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[191]_i_1 \n (.I0(s_axi_wdata[191]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[191]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[191]),\n .O(app_wdf_data[191]));\n (* SOFT_HLUTNM = \"soft_lutpair1356\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[192]_i_1 \n (.I0(s_axi_wdata[192]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[192]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[192]),\n .O(app_wdf_data[192]));\n (* SOFT_HLUTNM = \"soft_lutpair1357\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[193]_i_1 \n (.I0(s_axi_wdata[193]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[193]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[193]),\n .O(app_wdf_data[193]));\n (* SOFT_HLUTNM = \"soft_lutpair1358\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[194]_i_1 \n (.I0(s_axi_wdata[194]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[194]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[194]),\n .O(app_wdf_data[194]));\n (* SOFT_HLUTNM = \"soft_lutpair1359\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[195]_i_1 \n (.I0(s_axi_wdata[195]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[195]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[195]),\n .O(app_wdf_data[195]));\n (* SOFT_HLUTNM = \"soft_lutpair1360\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[196]_i_1 \n (.I0(s_axi_wdata[196]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[196]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[196]),\n .O(app_wdf_data[196]));\n (* SOFT_HLUTNM = \"soft_lutpair1361\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[197]_i_1 \n (.I0(s_axi_wdata[197]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[197]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[197]),\n .O(app_wdf_data[197]));\n (* SOFT_HLUTNM = \"soft_lutpair1362\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[198]_i_1 \n (.I0(s_axi_wdata[198]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[198]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[198]),\n .O(app_wdf_data[198]));\n (* SOFT_HLUTNM = \"soft_lutpair1363\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[199]_i_1 \n (.I0(s_axi_wdata[199]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[199]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[199]),\n .O(app_wdf_data[199]));\n (* SOFT_HLUTNM = \"soft_lutpair1183\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[19]_i_1 \n (.I0(s_axi_wdata[19]),\n .I1(s_axi_wready),\n .I2(wdf_data[19]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[19]),\n .O(app_wdf_data[19]));\n (* SOFT_HLUTNM = \"soft_lutpair1165\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[1]_i_1 \n (.I0(s_axi_wdata[1]),\n .I1(s_axi_wready),\n .I2(wdf_data[1]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[1]),\n .O(app_wdf_data[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1364\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[200]_i_1 \n (.I0(s_axi_wdata[200]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[200]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[200]),\n .O(app_wdf_data[200]));\n (* SOFT_HLUTNM = \"soft_lutpair1365\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[201]_i_1 \n (.I0(s_axi_wdata[201]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[201]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[201]),\n .O(app_wdf_data[201]));\n (* SOFT_HLUTNM = \"soft_lutpair1366\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[202]_i_1 \n (.I0(s_axi_wdata[202]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[202]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[202]),\n .O(app_wdf_data[202]));\n (* SOFT_HLUTNM = \"soft_lutpair1367\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[203]_i_1 \n (.I0(s_axi_wdata[203]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[203]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[203]),\n .O(app_wdf_data[203]));\n (* SOFT_HLUTNM = \"soft_lutpair1368\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[204]_i_1 \n (.I0(s_axi_wdata[204]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[204]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[204]),\n .O(app_wdf_data[204]));\n (* SOFT_HLUTNM = \"soft_lutpair1369\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[205]_i_1 \n (.I0(s_axi_wdata[205]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[205]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[205]),\n .O(app_wdf_data[205]));\n (* SOFT_HLUTNM = \"soft_lutpair1370\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[206]_i_1 \n (.I0(s_axi_wdata[206]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[206]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[206]),\n .O(app_wdf_data[206]));\n (* SOFT_HLUTNM = \"soft_lutpair1371\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[207]_i_1 \n (.I0(s_axi_wdata[207]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[207]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[207]),\n .O(app_wdf_data[207]));\n (* SOFT_HLUTNM = \"soft_lutpair1372\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[208]_i_1 \n (.I0(s_axi_wdata[208]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[208]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[208]),\n .O(app_wdf_data[208]));\n (* SOFT_HLUTNM = \"soft_lutpair1373\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[209]_i_1 \n (.I0(s_axi_wdata[209]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[209]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[209]),\n .O(app_wdf_data[209]));\n (* SOFT_HLUTNM = \"soft_lutpair1184\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[20]_i_1 \n (.I0(s_axi_wdata[20]),\n .I1(s_axi_wready),\n .I2(wdf_data[20]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[20]),\n .O(app_wdf_data[20]));\n (* SOFT_HLUTNM = \"soft_lutpair1374\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[210]_i_1 \n (.I0(s_axi_wdata[210]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[210]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[210]),\n .O(app_wdf_data[210]));\n (* SOFT_HLUTNM = \"soft_lutpair1375\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[211]_i_1 \n (.I0(s_axi_wdata[211]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[211]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[211]),\n .O(app_wdf_data[211]));\n (* SOFT_HLUTNM = \"soft_lutpair1376\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[212]_i_1 \n (.I0(s_axi_wdata[212]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[212]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[212]),\n .O(app_wdf_data[212]));\n (* SOFT_HLUTNM = \"soft_lutpair1377\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[213]_i_1 \n (.I0(s_axi_wdata[213]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[213]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[213]),\n .O(app_wdf_data[213]));\n (* SOFT_HLUTNM = \"soft_lutpair1378\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[214]_i_1 \n (.I0(s_axi_wdata[214]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[214]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[214]),\n .O(app_wdf_data[214]));\n (* SOFT_HLUTNM = \"soft_lutpair1379\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[215]_i_1 \n (.I0(s_axi_wdata[215]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[215]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[215]),\n .O(app_wdf_data[215]));\n (* SOFT_HLUTNM = \"soft_lutpair1380\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[216]_i_1 \n (.I0(s_axi_wdata[216]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[216]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[216]),\n .O(app_wdf_data[216]));\n (* SOFT_HLUTNM = \"soft_lutpair1381\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[217]_i_1 \n (.I0(s_axi_wdata[217]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[217]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[217]),\n .O(app_wdf_data[217]));\n (* SOFT_HLUTNM = \"soft_lutpair1382\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[218]_i_1 \n (.I0(s_axi_wdata[218]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[218]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[218]),\n .O(app_wdf_data[218]));\n (* SOFT_HLUTNM = \"soft_lutpair1383\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[219]_i_1 \n (.I0(s_axi_wdata[219]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[219]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[219]),\n .O(app_wdf_data[219]));\n (* SOFT_HLUTNM = \"soft_lutpair1185\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[21]_i_1 \n (.I0(s_axi_wdata[21]),\n .I1(s_axi_wready),\n .I2(wdf_data[21]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[21]),\n .O(app_wdf_data[21]));\n (* SOFT_HLUTNM = \"soft_lutpair1384\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[220]_i_1 \n (.I0(s_axi_wdata[220]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[220]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[220]),\n .O(app_wdf_data[220]));\n (* SOFT_HLUTNM = \"soft_lutpair1385\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[221]_i_1 \n (.I0(s_axi_wdata[221]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[221]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[221]),\n .O(app_wdf_data[221]));\n (* SOFT_HLUTNM = \"soft_lutpair1386\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[222]_i_1 \n (.I0(s_axi_wdata[222]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[222]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[222]),\n .O(app_wdf_data[222]));\n (* SOFT_HLUTNM = \"soft_lutpair1387\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[223]_i_1 \n (.I0(s_axi_wdata[223]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[223]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[223]),\n .O(app_wdf_data[223]));\n (* SOFT_HLUTNM = \"soft_lutpair1388\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[224]_i_1 \n (.I0(s_axi_wdata[224]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[224]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[224]),\n .O(app_wdf_data[224]));\n (* SOFT_HLUTNM = \"soft_lutpair1389\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[225]_i_1 \n (.I0(s_axi_wdata[225]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[225]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[225]),\n .O(app_wdf_data[225]));\n (* SOFT_HLUTNM = \"soft_lutpair1390\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[226]_i_1 \n (.I0(s_axi_wdata[226]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[226]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[226]),\n .O(app_wdf_data[226]));\n (* SOFT_HLUTNM = \"soft_lutpair1391\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[227]_i_1 \n (.I0(s_axi_wdata[227]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[227]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[227]),\n .O(app_wdf_data[227]));\n (* SOFT_HLUTNM = \"soft_lutpair1392\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[228]_i_1 \n (.I0(s_axi_wdata[228]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[228]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[228]),\n .O(app_wdf_data[228]));\n (* SOFT_HLUTNM = \"soft_lutpair1393\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[229]_i_1 \n (.I0(s_axi_wdata[229]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[229]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[229]),\n .O(app_wdf_data[229]));\n (* SOFT_HLUTNM = \"soft_lutpair1186\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[22]_i_1 \n (.I0(s_axi_wdata[22]),\n .I1(s_axi_wready),\n .I2(wdf_data[22]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[22]),\n .O(app_wdf_data[22]));\n (* SOFT_HLUTNM = \"soft_lutpair1394\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[230]_i_1 \n (.I0(s_axi_wdata[230]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[230]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[230]),\n .O(app_wdf_data[230]));\n (* SOFT_HLUTNM = \"soft_lutpair1395\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[231]_i_1 \n (.I0(s_axi_wdata[231]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[231]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[231]),\n .O(app_wdf_data[231]));\n (* SOFT_HLUTNM = \"soft_lutpair1396\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[232]_i_1 \n (.I0(s_axi_wdata[232]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[232]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[232]),\n .O(app_wdf_data[232]));\n (* SOFT_HLUTNM = \"soft_lutpair1397\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[233]_i_1 \n (.I0(s_axi_wdata[233]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[233]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[233]),\n .O(app_wdf_data[233]));\n (* SOFT_HLUTNM = \"soft_lutpair1398\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[234]_i_1 \n (.I0(s_axi_wdata[234]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[234]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[234]),\n .O(app_wdf_data[234]));\n (* SOFT_HLUTNM = \"soft_lutpair1399\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[235]_i_1 \n (.I0(s_axi_wdata[235]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[235]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[235]),\n .O(app_wdf_data[235]));\n (* SOFT_HLUTNM = \"soft_lutpair1400\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[236]_i_1 \n (.I0(s_axi_wdata[236]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[236]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[236]),\n .O(app_wdf_data[236]));\n (* SOFT_HLUTNM = \"soft_lutpair1401\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[237]_i_1 \n (.I0(s_axi_wdata[237]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[237]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[237]),\n .O(app_wdf_data[237]));\n (* SOFT_HLUTNM = \"soft_lutpair1402\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[238]_i_1 \n (.I0(s_axi_wdata[238]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[238]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[238]),\n .O(app_wdf_data[238]));\n (* SOFT_HLUTNM = \"soft_lutpair1403\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[239]_i_1 \n (.I0(s_axi_wdata[239]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[239]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[239]),\n .O(app_wdf_data[239]));\n (* SOFT_HLUTNM = \"soft_lutpair1187\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[23]_i_1 \n (.I0(s_axi_wdata[23]),\n .I1(s_axi_wready),\n .I2(wdf_data[23]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[23]),\n .O(app_wdf_data[23]));\n (* SOFT_HLUTNM = \"soft_lutpair1404\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[240]_i_1 \n (.I0(s_axi_wdata[240]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[240]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[240]),\n .O(app_wdf_data[240]));\n (* SOFT_HLUTNM = \"soft_lutpair1405\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[241]_i_1 \n (.I0(s_axi_wdata[241]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[241]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[241]),\n .O(app_wdf_data[241]));\n (* SOFT_HLUTNM = \"soft_lutpair1406\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[242]_i_1 \n (.I0(s_axi_wdata[242]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[242]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[242]),\n .O(app_wdf_data[242]));\n (* SOFT_HLUTNM = \"soft_lutpair1407\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[243]_i_1 \n (.I0(s_axi_wdata[243]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[243]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[243]),\n .O(app_wdf_data[243]));\n (* SOFT_HLUTNM = \"soft_lutpair1408\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[244]_i_1 \n (.I0(s_axi_wdata[244]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[244]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[244]),\n .O(app_wdf_data[244]));\n (* SOFT_HLUTNM = \"soft_lutpair1409\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[245]_i_1 \n (.I0(s_axi_wdata[245]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[245]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[245]),\n .O(app_wdf_data[245]));\n (* SOFT_HLUTNM = \"soft_lutpair1410\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[246]_i_1 \n (.I0(s_axi_wdata[246]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[246]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[246]),\n .O(app_wdf_data[246]));\n (* SOFT_HLUTNM = \"soft_lutpair1411\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[247]_i_1 \n (.I0(s_axi_wdata[247]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[247]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[247]),\n .O(app_wdf_data[247]));\n (* SOFT_HLUTNM = \"soft_lutpair1412\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[248]_i_1 \n (.I0(s_axi_wdata[248]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[248]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[248]),\n .O(app_wdf_data[248]));\n (* SOFT_HLUTNM = \"soft_lutpair1413\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[249]_i_1 \n (.I0(s_axi_wdata[249]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[249]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[249]),\n .O(app_wdf_data[249]));\n (* SOFT_HLUTNM = \"soft_lutpair1188\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[24]_i_1 \n (.I0(s_axi_wdata[24]),\n .I1(s_axi_wready),\n .I2(wdf_data[24]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[24]),\n .O(app_wdf_data[24]));\n (* SOFT_HLUTNM = \"soft_lutpair1414\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[250]_i_1 \n (.I0(s_axi_wdata[250]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[250]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[250]),\n .O(app_wdf_data[250]));\n (* SOFT_HLUTNM = \"soft_lutpair1415\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[251]_i_1 \n (.I0(s_axi_wdata[251]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[251]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[251]),\n .O(app_wdf_data[251]));\n (* SOFT_HLUTNM = \"soft_lutpair1416\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[252]_i_1 \n (.I0(s_axi_wdata[252]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[252]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[252]),\n .O(app_wdf_data[252]));\n (* SOFT_HLUTNM = \"soft_lutpair1417\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[253]_i_1 \n (.I0(s_axi_wdata[253]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[253]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[253]),\n .O(app_wdf_data[253]));\n (* SOFT_HLUTNM = \"soft_lutpair1418\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[254]_i_1 \n (.I0(s_axi_wdata[254]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[254]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[254]),\n .O(app_wdf_data[254]));\n (* SOFT_HLUTNM = \"soft_lutpair1419\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[255]_i_1 \n (.I0(s_axi_wdata[255]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[255]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[255]),\n .O(app_wdf_data[255]));\n (* SOFT_HLUTNM = \"soft_lutpair1189\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[25]_i_1 \n (.I0(s_axi_wdata[25]),\n .I1(s_axi_wready),\n .I2(wdf_data[25]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[25]),\n .O(app_wdf_data[25]));\n (* SOFT_HLUTNM = \"soft_lutpair1190\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[26]_i_1 \n (.I0(s_axi_wdata[26]),\n .I1(s_axi_wready),\n .I2(wdf_data[26]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[26]),\n .O(app_wdf_data[26]));\n (* SOFT_HLUTNM = \"soft_lutpair1191\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[27]_i_1 \n (.I0(s_axi_wdata[27]),\n .I1(s_axi_wready),\n .I2(wdf_data[27]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[27]),\n .O(app_wdf_data[27]));\n (* SOFT_HLUTNM = \"soft_lutpair1192\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[28]_i_1 \n (.I0(s_axi_wdata[28]),\n .I1(s_axi_wready),\n .I2(wdf_data[28]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[28]),\n .O(app_wdf_data[28]));\n (* SOFT_HLUTNM = \"soft_lutpair1193\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[29]_i_1 \n (.I0(s_axi_wdata[29]),\n .I1(s_axi_wready),\n .I2(wdf_data[29]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[29]),\n .O(app_wdf_data[29]));\n (* SOFT_HLUTNM = \"soft_lutpair1166\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[2]_i_1 \n (.I0(s_axi_wdata[2]),\n .I1(s_axi_wready),\n .I2(wdf_data[2]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[2]),\n .O(app_wdf_data[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1194\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[30]_i_1 \n (.I0(s_axi_wdata[30]),\n .I1(s_axi_wready),\n .I2(wdf_data[30]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[30]),\n .O(app_wdf_data[30]));\n (* SOFT_HLUTNM = \"soft_lutpair1195\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[31]_i_1 \n (.I0(s_axi_wdata[31]),\n .I1(s_axi_wready),\n .I2(wdf_data[31]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[31]),\n .O(app_wdf_data[31]));\n (* SOFT_HLUTNM = \"soft_lutpair1196\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[32]_i_1 \n (.I0(s_axi_wdata[32]),\n .I1(s_axi_wready),\n .I2(wdf_data[32]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[32]),\n .O(app_wdf_data[32]));\n (* SOFT_HLUTNM = \"soft_lutpair1197\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[33]_i_1 \n (.I0(s_axi_wdata[33]),\n .I1(s_axi_wready),\n .I2(wdf_data[33]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[33]),\n .O(app_wdf_data[33]));\n (* SOFT_HLUTNM = \"soft_lutpair1198\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[34]_i_1 \n (.I0(s_axi_wdata[34]),\n .I1(s_axi_wready),\n .I2(wdf_data[34]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[34]),\n .O(app_wdf_data[34]));\n (* SOFT_HLUTNM = \"soft_lutpair1199\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[35]_i_1 \n (.I0(s_axi_wdata[35]),\n .I1(s_axi_wready),\n .I2(wdf_data[35]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[35]),\n .O(app_wdf_data[35]));\n (* SOFT_HLUTNM = \"soft_lutpair1200\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[36]_i_1 \n (.I0(s_axi_wdata[36]),\n .I1(s_axi_wready),\n .I2(wdf_data[36]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[36]),\n .O(app_wdf_data[36]));\n (* SOFT_HLUTNM = \"soft_lutpair1201\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[37]_i_1 \n (.I0(s_axi_wdata[37]),\n .I1(s_axi_wready),\n .I2(wdf_data[37]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[37]),\n .O(app_wdf_data[37]));\n (* SOFT_HLUTNM = \"soft_lutpair1202\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[38]_i_1 \n (.I0(s_axi_wdata[38]),\n .I1(s_axi_wready),\n .I2(wdf_data[38]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[38]),\n .O(app_wdf_data[38]));\n (* SOFT_HLUTNM = \"soft_lutpair1203\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[39]_i_1 \n (.I0(s_axi_wdata[39]),\n .I1(s_axi_wready),\n .I2(wdf_data[39]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[39]),\n .O(app_wdf_data[39]));\n (* SOFT_HLUTNM = \"soft_lutpair1167\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[3]_i_1 \n (.I0(s_axi_wdata[3]),\n .I1(s_axi_wready),\n .I2(wdf_data[3]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[3]),\n .O(app_wdf_data[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1204\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[40]_i_1 \n (.I0(s_axi_wdata[40]),\n .I1(s_axi_wready),\n .I2(wdf_data[40]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[40]),\n .O(app_wdf_data[40]));\n (* SOFT_HLUTNM = \"soft_lutpair1205\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[41]_i_1 \n (.I0(s_axi_wdata[41]),\n .I1(s_axi_wready),\n .I2(wdf_data[41]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[41]),\n .O(app_wdf_data[41]));\n (* SOFT_HLUTNM = \"soft_lutpair1206\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[42]_i_1 \n (.I0(s_axi_wdata[42]),\n .I1(s_axi_wready),\n .I2(wdf_data[42]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[42]),\n .O(app_wdf_data[42]));\n (* SOFT_HLUTNM = \"soft_lutpair1207\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[43]_i_1 \n (.I0(s_axi_wdata[43]),\n .I1(s_axi_wready),\n .I2(wdf_data[43]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[43]),\n .O(app_wdf_data[43]));\n (* SOFT_HLUTNM = \"soft_lutpair1208\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[44]_i_1 \n (.I0(s_axi_wdata[44]),\n .I1(s_axi_wready),\n .I2(wdf_data[44]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[44]),\n .O(app_wdf_data[44]));\n (* SOFT_HLUTNM = \"soft_lutpair1209\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[45]_i_1 \n (.I0(s_axi_wdata[45]),\n .I1(s_axi_wready),\n .I2(wdf_data[45]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[45]),\n .O(app_wdf_data[45]));\n (* SOFT_HLUTNM = \"soft_lutpair1210\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[46]_i_1 \n (.I0(s_axi_wdata[46]),\n .I1(s_axi_wready),\n .I2(wdf_data[46]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[46]),\n .O(app_wdf_data[46]));\n (* SOFT_HLUTNM = \"soft_lutpair1211\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[47]_i_1 \n (.I0(s_axi_wdata[47]),\n .I1(s_axi_wready),\n .I2(wdf_data[47]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[47]),\n .O(app_wdf_data[47]));\n (* SOFT_HLUTNM = \"soft_lutpair1212\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[48]_i_1 \n (.I0(s_axi_wdata[48]),\n .I1(s_axi_wready),\n .I2(wdf_data[48]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[48]),\n .O(app_wdf_data[48]));\n (* SOFT_HLUTNM = \"soft_lutpair1213\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[49]_i_1 \n (.I0(s_axi_wdata[49]),\n .I1(s_axi_wready),\n .I2(wdf_data[49]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[49]),\n .O(app_wdf_data[49]));\n (* SOFT_HLUTNM = \"soft_lutpair1168\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[4]_i_1 \n (.I0(s_axi_wdata[4]),\n .I1(s_axi_wready),\n .I2(wdf_data[4]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[4]),\n .O(app_wdf_data[4]));\n (* SOFT_HLUTNM = \"soft_lutpair1214\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[50]_i_1 \n (.I0(s_axi_wdata[50]),\n .I1(s_axi_wready),\n .I2(wdf_data[50]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[50]),\n .O(app_wdf_data[50]));\n (* SOFT_HLUTNM = \"soft_lutpair1215\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[51]_i_1 \n (.I0(s_axi_wdata[51]),\n .I1(s_axi_wready),\n .I2(wdf_data[51]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[51]),\n .O(app_wdf_data[51]));\n (* SOFT_HLUTNM = \"soft_lutpair1216\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[52]_i_1 \n (.I0(s_axi_wdata[52]),\n .I1(s_axi_wready),\n .I2(wdf_data[52]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[52]),\n .O(app_wdf_data[52]));\n (* SOFT_HLUTNM = \"soft_lutpair1217\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[53]_i_1 \n (.I0(s_axi_wdata[53]),\n .I1(s_axi_wready),\n .I2(wdf_data[53]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[53]),\n .O(app_wdf_data[53]));\n (* SOFT_HLUTNM = \"soft_lutpair1218\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[54]_i_1 \n (.I0(s_axi_wdata[54]),\n .I1(s_axi_wready),\n .I2(wdf_data[54]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[54]),\n .O(app_wdf_data[54]));\n (* SOFT_HLUTNM = \"soft_lutpair1219\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[55]_i_1 \n (.I0(s_axi_wdata[55]),\n .I1(s_axi_wready),\n .I2(wdf_data[55]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[55]),\n .O(app_wdf_data[55]));\n (* SOFT_HLUTNM = \"soft_lutpair1220\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[56]_i_1 \n (.I0(s_axi_wdata[56]),\n .I1(s_axi_wready),\n .I2(wdf_data[56]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[56]),\n .O(app_wdf_data[56]));\n (* SOFT_HLUTNM = \"soft_lutpair1221\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[57]_i_1 \n (.I0(s_axi_wdata[57]),\n .I1(s_axi_wready),\n .I2(wdf_data[57]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[57]),\n .O(app_wdf_data[57]));\n (* SOFT_HLUTNM = \"soft_lutpair1222\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[58]_i_1 \n (.I0(s_axi_wdata[58]),\n .I1(s_axi_wready),\n .I2(wdf_data[58]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[58]),\n .O(app_wdf_data[58]));\n (* SOFT_HLUTNM = \"soft_lutpair1223\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[59]_i_1 \n (.I0(s_axi_wdata[59]),\n .I1(s_axi_wready),\n .I2(wdf_data[59]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[59]),\n .O(app_wdf_data[59]));\n (* SOFT_HLUTNM = \"soft_lutpair1169\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[5]_i_1 \n (.I0(s_axi_wdata[5]),\n .I1(s_axi_wready),\n .I2(wdf_data[5]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[5]),\n .O(app_wdf_data[5]));\n (* SOFT_HLUTNM = \"soft_lutpair1224\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[60]_i_1 \n (.I0(s_axi_wdata[60]),\n .I1(s_axi_wready),\n .I2(wdf_data[60]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[60]),\n .O(app_wdf_data[60]));\n (* SOFT_HLUTNM = \"soft_lutpair1225\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[61]_i_1 \n (.I0(s_axi_wdata[61]),\n .I1(s_axi_wready),\n .I2(wdf_data[61]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[61]),\n .O(app_wdf_data[61]));\n (* SOFT_HLUTNM = \"soft_lutpair1226\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[62]_i_1 \n (.I0(s_axi_wdata[62]),\n .I1(s_axi_wready),\n .I2(wdf_data[62]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[62]),\n .O(app_wdf_data[62]));\n (* SOFT_HLUTNM = \"soft_lutpair1227\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[63]_i_1 \n (.I0(s_axi_wdata[63]),\n .I1(s_axi_wready),\n .I2(wdf_data[63]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[63]),\n .O(app_wdf_data[63]));\n (* SOFT_HLUTNM = \"soft_lutpair1228\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[64]_i_1 \n (.I0(s_axi_wdata[64]),\n .I1(s_axi_wready),\n .I2(wdf_data[64]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[64]),\n .O(app_wdf_data[64]));\n (* SOFT_HLUTNM = \"soft_lutpair1229\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[65]_i_1 \n (.I0(s_axi_wdata[65]),\n .I1(s_axi_wready),\n .I2(wdf_data[65]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[65]),\n .O(app_wdf_data[65]));\n (* SOFT_HLUTNM = \"soft_lutpair1230\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[66]_i_1 \n (.I0(s_axi_wdata[66]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[66]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[66]),\n .O(app_wdf_data[66]));\n (* SOFT_HLUTNM = \"soft_lutpair1231\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[67]_i_1 \n (.I0(s_axi_wdata[67]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[67]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[67]),\n .O(app_wdf_data[67]));\n (* SOFT_HLUTNM = \"soft_lutpair1232\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[68]_i_1 \n (.I0(s_axi_wdata[68]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[68]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[68]),\n .O(app_wdf_data[68]));\n (* SOFT_HLUTNM = \"soft_lutpair1233\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[69]_i_1 \n (.I0(s_axi_wdata[69]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[69]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[69]),\n .O(app_wdf_data[69]));\n (* SOFT_HLUTNM = \"soft_lutpair1170\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[6]_i_1 \n (.I0(s_axi_wdata[6]),\n .I1(s_axi_wready),\n .I2(wdf_data[6]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[6]),\n .O(app_wdf_data[6]));\n (* SOFT_HLUTNM = \"soft_lutpair1234\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[70]_i_1 \n (.I0(s_axi_wdata[70]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[70]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[70]),\n .O(app_wdf_data[70]));\n (* SOFT_HLUTNM = \"soft_lutpair1235\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[71]_i_1 \n (.I0(s_axi_wdata[71]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[71]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[71]),\n .O(app_wdf_data[71]));\n (* SOFT_HLUTNM = \"soft_lutpair1236\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[72]_i_1 \n (.I0(s_axi_wdata[72]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[72]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[72]),\n .O(app_wdf_data[72]));\n (* SOFT_HLUTNM = \"soft_lutpair1237\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[73]_i_1 \n (.I0(s_axi_wdata[73]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[73]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[73]),\n .O(app_wdf_data[73]));\n (* SOFT_HLUTNM = \"soft_lutpair1238\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[74]_i_1 \n (.I0(s_axi_wdata[74]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[74]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[74]),\n .O(app_wdf_data[74]));\n (* SOFT_HLUTNM = \"soft_lutpair1239\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[75]_i_1 \n (.I0(s_axi_wdata[75]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[75]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[75]),\n .O(app_wdf_data[75]));\n (* SOFT_HLUTNM = \"soft_lutpair1240\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[76]_i_1 \n (.I0(s_axi_wdata[76]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[76]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[76]),\n .O(app_wdf_data[76]));\n (* SOFT_HLUTNM = \"soft_lutpair1241\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[77]_i_1 \n (.I0(s_axi_wdata[77]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[77]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[77]),\n .O(app_wdf_data[77]));\n (* SOFT_HLUTNM = \"soft_lutpair1242\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[78]_i_1 \n (.I0(s_axi_wdata[78]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[78]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[78]),\n .O(app_wdf_data[78]));\n (* SOFT_HLUTNM = \"soft_lutpair1243\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[79]_i_1 \n (.I0(s_axi_wdata[79]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[79]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[79]),\n .O(app_wdf_data[79]));\n (* SOFT_HLUTNM = \"soft_lutpair1171\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[7]_i_1 \n (.I0(s_axi_wdata[7]),\n .I1(s_axi_wready),\n .I2(wdf_data[7]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[7]),\n .O(app_wdf_data[7]));\n (* SOFT_HLUTNM = \"soft_lutpair1244\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[80]_i_1 \n (.I0(s_axi_wdata[80]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[80]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[80]),\n .O(app_wdf_data[80]));\n (* SOFT_HLUTNM = \"soft_lutpair1245\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[81]_i_1 \n (.I0(s_axi_wdata[81]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[81]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[81]),\n .O(app_wdf_data[81]));\n (* SOFT_HLUTNM = \"soft_lutpair1246\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[82]_i_1 \n (.I0(s_axi_wdata[82]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[82]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[82]),\n .O(app_wdf_data[82]));\n (* SOFT_HLUTNM = \"soft_lutpair1247\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[83]_i_1 \n (.I0(s_axi_wdata[83]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[83]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[83]),\n .O(app_wdf_data[83]));\n (* SOFT_HLUTNM = \"soft_lutpair1248\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[84]_i_1 \n (.I0(s_axi_wdata[84]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[84]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[84]),\n .O(app_wdf_data[84]));\n (* SOFT_HLUTNM = \"soft_lutpair1249\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[85]_i_1 \n (.I0(s_axi_wdata[85]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[85]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[85]),\n .O(app_wdf_data[85]));\n (* SOFT_HLUTNM = \"soft_lutpair1250\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[86]_i_1 \n (.I0(s_axi_wdata[86]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[86]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[86]),\n .O(app_wdf_data[86]));\n (* SOFT_HLUTNM = \"soft_lutpair1251\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[87]_i_1 \n (.I0(s_axi_wdata[87]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[87]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[87]),\n .O(app_wdf_data[87]));\n (* SOFT_HLUTNM = \"soft_lutpair1252\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[88]_i_1 \n (.I0(s_axi_wdata[88]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[88]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[88]),\n .O(app_wdf_data[88]));\n (* SOFT_HLUTNM = \"soft_lutpair1253\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[89]_i_1 \n (.I0(s_axi_wdata[89]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[89]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[89]),\n .O(app_wdf_data[89]));\n (* SOFT_HLUTNM = \"soft_lutpair1172\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[8]_i_1 \n (.I0(s_axi_wdata[8]),\n .I1(s_axi_wready),\n .I2(wdf_data[8]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[8]),\n .O(app_wdf_data[8]));\n (* SOFT_HLUTNM = \"soft_lutpair1254\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[90]_i_1 \n (.I0(s_axi_wdata[90]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[90]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[90]),\n .O(app_wdf_data[90]));\n (* SOFT_HLUTNM = \"soft_lutpair1255\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[91]_i_1 \n (.I0(s_axi_wdata[91]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[91]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[91]),\n .O(app_wdf_data[91]));\n (* SOFT_HLUTNM = \"soft_lutpair1256\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[92]_i_1 \n (.I0(s_axi_wdata[92]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[92]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[92]),\n .O(app_wdf_data[92]));\n (* SOFT_HLUTNM = \"soft_lutpair1257\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[93]_i_1 \n (.I0(s_axi_wdata[93]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[93]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[93]),\n .O(app_wdf_data[93]));\n (* SOFT_HLUTNM = \"soft_lutpair1258\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[94]_i_1 \n (.I0(s_axi_wdata[94]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[94]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[94]),\n .O(app_wdf_data[94]));\n (* SOFT_HLUTNM = \"soft_lutpair1259\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[95]_i_1 \n (.I0(s_axi_wdata[95]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[95]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[95]),\n .O(app_wdf_data[95]));\n (* SOFT_HLUTNM = \"soft_lutpair1260\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[96]_i_1 \n (.I0(s_axi_wdata[96]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[96]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[96]),\n .O(app_wdf_data[96]));\n (* SOFT_HLUTNM = \"soft_lutpair1261\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[97]_i_1 \n (.I0(s_axi_wdata[97]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[97]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[97]),\n .O(app_wdf_data[97]));\n (* SOFT_HLUTNM = \"soft_lutpair1262\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[98]_i_1 \n (.I0(s_axi_wdata[98]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[98]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[98]),\n .O(app_wdf_data[98]));\n (* SOFT_HLUTNM = \"soft_lutpair1263\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[99]_i_1 \n (.I0(s_axi_wdata[99]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[99]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[99]),\n .O(app_wdf_data[99]));\n (* SOFT_HLUTNM = \"soft_lutpair1173\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[9]_i_1 \n (.I0(s_axi_wdata[9]),\n .I1(s_axi_wready),\n .I2(wdf_data[9]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[9]),\n .O(app_wdf_data[9]));\n (* SOFT_HLUTNM = \"soft_lutpair1420\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[0]_i_1 \n (.I0(s_axi_wstrb[0]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_mask[0]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[0]),\n .O(app_wdf_mask[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1430\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[10]_i_1 \n (.I0(s_axi_wstrb[10]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[10]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[10]),\n .O(app_wdf_mask[10]));\n (* SOFT_HLUTNM = \"soft_lutpair1431\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[11]_i_1 \n (.I0(s_axi_wstrb[11]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[11]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[11]),\n .O(app_wdf_mask[11]));\n (* SOFT_HLUTNM = \"soft_lutpair1432\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[12]_i_1 \n (.I0(s_axi_wstrb[12]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[12]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[12]),\n .O(app_wdf_mask[12]));\n (* SOFT_HLUTNM = \"soft_lutpair1433\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[13]_i_1 \n (.I0(s_axi_wstrb[13]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[13]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[13]),\n .O(app_wdf_mask[13]));\n (* SOFT_HLUTNM = \"soft_lutpair1434\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[14]_i_1 \n (.I0(s_axi_wstrb[14]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[14]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[14]),\n .O(app_wdf_mask[14]));\n (* SOFT_HLUTNM = \"soft_lutpair1435\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[15]_i_1 \n (.I0(s_axi_wstrb[15]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[15]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[15]),\n .O(app_wdf_mask[15]));\n (* SOFT_HLUTNM = \"soft_lutpair1436\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[16]_i_1 \n (.I0(s_axi_wstrb[16]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[16]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[16]),\n .O(app_wdf_mask[16]));\n (* SOFT_HLUTNM = \"soft_lutpair1437\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[17]_i_1 \n (.I0(s_axi_wstrb[17]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[17]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[17]),\n .O(app_wdf_mask[17]));\n (* SOFT_HLUTNM = \"soft_lutpair1438\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[18]_i_1 \n (.I0(s_axi_wstrb[18]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[18]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[18]),\n .O(app_wdf_mask[18]));\n (* SOFT_HLUTNM = \"soft_lutpair1439\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[19]_i_1 \n (.I0(s_axi_wstrb[19]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[19]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[19]),\n .O(app_wdf_mask[19]));\n (* SOFT_HLUTNM = \"soft_lutpair1421\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[1]_i_1 \n (.I0(s_axi_wstrb[1]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_mask[1]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[1]),\n .O(app_wdf_mask[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1440\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[20]_i_1 \n (.I0(s_axi_wstrb[20]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[20]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[20]),\n .O(app_wdf_mask[20]));\n (* SOFT_HLUTNM = \"soft_lutpair1441\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[21]_i_1 \n (.I0(s_axi_wstrb[21]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[21]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[21]),\n .O(app_wdf_mask[21]));\n (* SOFT_HLUTNM = \"soft_lutpair1442\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[22]_i_1 \n (.I0(s_axi_wstrb[22]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[22]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[22]),\n .O(app_wdf_mask[22]));\n (* SOFT_HLUTNM = \"soft_lutpair1443\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[23]_i_1 \n (.I0(s_axi_wstrb[23]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[23]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[23]),\n .O(app_wdf_mask[23]));\n (* SOFT_HLUTNM = \"soft_lutpair1444\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[24]_i_1 \n (.I0(s_axi_wstrb[24]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[24]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[24]),\n .O(app_wdf_mask[24]));\n (* SOFT_HLUTNM = \"soft_lutpair1445\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[25]_i_1 \n (.I0(s_axi_wstrb[25]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[25]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[25]),\n .O(app_wdf_mask[25]));\n (* SOFT_HLUTNM = \"soft_lutpair1446\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[26]_i_1 \n (.I0(s_axi_wstrb[26]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[26]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[26]),\n .O(app_wdf_mask[26]));\n (* SOFT_HLUTNM = \"soft_lutpair1447\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[27]_i_1 \n (.I0(s_axi_wstrb[27]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[27]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[27]),\n .O(app_wdf_mask[27]));\n (* SOFT_HLUTNM = \"soft_lutpair1448\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[28]_i_1 \n (.I0(s_axi_wstrb[28]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[28]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[28]),\n .O(app_wdf_mask[28]));\n (* SOFT_HLUTNM = \"soft_lutpair1449\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[29]_i_1 \n (.I0(s_axi_wstrb[29]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[29]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[29]),\n .O(app_wdf_mask[29]));\n (* SOFT_HLUTNM = \"soft_lutpair1422\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[2]_i_1 \n (.I0(s_axi_wstrb[2]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_mask[2]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[2]),\n .O(app_wdf_mask[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1450\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[30]_i_1 \n (.I0(s_axi_wstrb[30]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[30]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[30]),\n .O(app_wdf_mask[30]));\n (* SOFT_HLUTNM = \"soft_lutpair1451\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[31]_i_1 \n (.I0(s_axi_wstrb[31]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[31]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[31]),\n .O(app_wdf_mask[31]));\n (* SOFT_HLUTNM = \"soft_lutpair1423\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[3]_i_1 \n (.I0(s_axi_wstrb[3]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_mask[3]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[3]),\n .O(app_wdf_mask[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1424\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[4]_i_1 \n (.I0(s_axi_wstrb[4]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_mask[4]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[4]),\n .O(app_wdf_mask[4]));\n (* SOFT_HLUTNM = \"soft_lutpair1425\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[5]_i_1 \n (.I0(s_axi_wstrb[5]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_mask[5]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[5]),\n .O(app_wdf_mask[5]));\n (* SOFT_HLUTNM = \"soft_lutpair1426\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[6]_i_1 \n (.I0(s_axi_wstrb[6]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_mask[6]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[6]),\n .O(app_wdf_mask[6]));\n (* SOFT_HLUTNM = \"soft_lutpair1427\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[7]_i_1 \n (.I0(s_axi_wstrb[7]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_mask[7]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[7]),\n .O(app_wdf_mask[7]));\n (* SOFT_HLUTNM = \"soft_lutpair1428\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[8]_i_1 \n (.I0(s_axi_wstrb[8]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[8]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[8]),\n .O(app_wdf_mask[8]));\n (* SOFT_HLUTNM = \"soft_lutpair1429\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[9]_i_1 \n (.I0(s_axi_wstrb[9]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[9]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[9]),\n .O(app_wdf_mask[9]));\n (* SOFT_HLUTNM = \"soft_lutpair1452\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[0]_i_1 \n (.I0(s_axi_wdata[0]),\n .I1(s_axi_wready),\n .I2(wdf_data[0]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair1264\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[100]_i_1 \n (.I0(s_axi_wdata[100]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[100]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [100]));\n (* SOFT_HLUTNM = \"soft_lutpair1265\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[101]_i_1 \n (.I0(s_axi_wdata[101]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[101]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [101]));\n (* SOFT_HLUTNM = \"soft_lutpair1266\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[102]_i_1 \n (.I0(s_axi_wdata[102]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[102]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [102]));\n (* SOFT_HLUTNM = \"soft_lutpair1267\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[103]_i_1 \n (.I0(s_axi_wdata[103]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[103]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [103]));\n (* SOFT_HLUTNM = \"soft_lutpair1268\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[104]_i_1 \n (.I0(s_axi_wdata[104]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[104]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [104]));\n (* SOFT_HLUTNM = \"soft_lutpair1269\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[105]_i_1 \n (.I0(s_axi_wdata[105]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[105]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [105]));\n (* SOFT_HLUTNM = \"soft_lutpair1270\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[106]_i_1 \n (.I0(s_axi_wdata[106]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[106]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [106]));\n (* SOFT_HLUTNM = \"soft_lutpair1271\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[107]_i_1 \n (.I0(s_axi_wdata[107]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[107]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [107]));\n (* SOFT_HLUTNM = \"soft_lutpair1272\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[108]_i_1 \n (.I0(s_axi_wdata[108]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[108]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [108]));\n (* SOFT_HLUTNM = \"soft_lutpair1273\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[109]_i_1 \n (.I0(s_axi_wdata[109]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[109]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [109]));\n (* SOFT_HLUTNM = \"soft_lutpair1174\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[10]_i_1 \n (.I0(s_axi_wdata[10]),\n .I1(s_axi_wready),\n .I2(wdf_data[10]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [10]));\n (* SOFT_HLUTNM = \"soft_lutpair1274\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[110]_i_1 \n (.I0(s_axi_wdata[110]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[110]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [110]));\n (* SOFT_HLUTNM = \"soft_lutpair1275\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[111]_i_1 \n (.I0(s_axi_wdata[111]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[111]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [111]));\n (* SOFT_HLUTNM = \"soft_lutpair1276\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[112]_i_1 \n (.I0(s_axi_wdata[112]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[112]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [112]));\n (* SOFT_HLUTNM = \"soft_lutpair1277\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[113]_i_1 \n (.I0(s_axi_wdata[113]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[113]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [113]));\n (* SOFT_HLUTNM = \"soft_lutpair1278\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[114]_i_1 \n (.I0(s_axi_wdata[114]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[114]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [114]));\n (* SOFT_HLUTNM = \"soft_lutpair1279\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[115]_i_1 \n (.I0(s_axi_wdata[115]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[115]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [115]));\n (* SOFT_HLUTNM = \"soft_lutpair1280\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[116]_i_1 \n (.I0(s_axi_wdata[116]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[116]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [116]));\n (* SOFT_HLUTNM = \"soft_lutpair1281\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[117]_i_1 \n (.I0(s_axi_wdata[117]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[117]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [117]));\n (* SOFT_HLUTNM = \"soft_lutpair1282\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[118]_i_1 \n (.I0(s_axi_wdata[118]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[118]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [118]));\n (* SOFT_HLUTNM = \"soft_lutpair1283\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[119]_i_1 \n (.I0(s_axi_wdata[119]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[119]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [119]));\n (* SOFT_HLUTNM = \"soft_lutpair1175\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[11]_i_1 \n (.I0(s_axi_wdata[11]),\n .I1(s_axi_wready),\n .I2(wdf_data[11]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [11]));\n (* SOFT_HLUTNM = \"soft_lutpair1284\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[120]_i_1 \n (.I0(s_axi_wdata[120]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[120]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [120]));\n (* SOFT_HLUTNM = \"soft_lutpair1285\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[121]_i_1 \n (.I0(s_axi_wdata[121]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[121]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [121]));\n (* SOFT_HLUTNM = \"soft_lutpair1286\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[122]_i_1 \n (.I0(s_axi_wdata[122]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[122]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [122]));\n (* SOFT_HLUTNM = \"soft_lutpair1287\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[123]_i_1 \n (.I0(s_axi_wdata[123]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[123]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [123]));\n (* SOFT_HLUTNM = \"soft_lutpair1288\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[124]_i_1 \n (.I0(s_axi_wdata[124]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[124]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [124]));\n (* SOFT_HLUTNM = \"soft_lutpair1289\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[125]_i_1 \n (.I0(s_axi_wdata[125]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[125]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [125]));\n (* SOFT_HLUTNM = \"soft_lutpair1290\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[126]_i_1 \n (.I0(s_axi_wdata[126]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[126]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [126]));\n (* SOFT_HLUTNM = \"soft_lutpair1291\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[127]_i_1 \n (.I0(s_axi_wdata[127]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[127]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [127]));\n (* SOFT_HLUTNM = \"soft_lutpair1292\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[128]_i_1 \n (.I0(s_axi_wdata[128]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[128]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [128]));\n (* SOFT_HLUTNM = \"soft_lutpair1293\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[129]_i_1 \n (.I0(s_axi_wdata[129]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[129]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [129]));\n (* SOFT_HLUTNM = \"soft_lutpair1176\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[12]_i_1 \n (.I0(s_axi_wdata[12]),\n .I1(s_axi_wready),\n .I2(wdf_data[12]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [12]));\n (* SOFT_HLUTNM = \"soft_lutpair1294\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[130]_i_1 \n (.I0(s_axi_wdata[130]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[130]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [130]));\n (* SOFT_HLUTNM = \"soft_lutpair1295\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[131]_i_1 \n (.I0(s_axi_wdata[131]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[131]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [131]));\n (* SOFT_HLUTNM = \"soft_lutpair1296\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[132]_i_1 \n (.I0(s_axi_wdata[132]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[132]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [132]));\n (* SOFT_HLUTNM = \"soft_lutpair1297\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[133]_i_1 \n (.I0(s_axi_wdata[133]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[133]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [133]));\n (* SOFT_HLUTNM = \"soft_lutpair1298\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[134]_i_1 \n (.I0(s_axi_wdata[134]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[134]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [134]));\n (* SOFT_HLUTNM = \"soft_lutpair1299\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[135]_i_1 \n (.I0(s_axi_wdata[135]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[135]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [135]));\n (* SOFT_HLUTNM = \"soft_lutpair1300\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[136]_i_1 \n (.I0(s_axi_wdata[136]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[136]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [136]));\n (* SOFT_HLUTNM = \"soft_lutpair1301\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[137]_i_1 \n (.I0(s_axi_wdata[137]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[137]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [137]));\n (* SOFT_HLUTNM = \"soft_lutpair1302\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[138]_i_1 \n (.I0(s_axi_wdata[138]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[138]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [138]));\n (* SOFT_HLUTNM = \"soft_lutpair1303\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[139]_i_1 \n (.I0(s_axi_wdata[139]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[139]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [139]));\n (* SOFT_HLUTNM = \"soft_lutpair1177\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[13]_i_1 \n (.I0(s_axi_wdata[13]),\n .I1(s_axi_wready),\n .I2(wdf_data[13]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [13]));\n (* SOFT_HLUTNM = \"soft_lutpair1304\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[140]_i_1 \n (.I0(s_axi_wdata[140]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[140]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [140]));\n (* SOFT_HLUTNM = \"soft_lutpair1305\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[141]_i_1 \n (.I0(s_axi_wdata[141]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[141]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [141]));\n (* SOFT_HLUTNM = \"soft_lutpair1306\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[142]_i_1 \n (.I0(s_axi_wdata[142]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[142]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [142]));\n (* SOFT_HLUTNM = \"soft_lutpair1307\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[143]_i_1 \n (.I0(s_axi_wdata[143]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[143]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [143]));\n (* SOFT_HLUTNM = \"soft_lutpair1308\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[144]_i_1 \n (.I0(s_axi_wdata[144]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[144]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [144]));\n (* SOFT_HLUTNM = \"soft_lutpair1309\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[145]_i_1 \n (.I0(s_axi_wdata[145]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[145]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [145]));\n (* SOFT_HLUTNM = \"soft_lutpair1310\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[146]_i_1 \n (.I0(s_axi_wdata[146]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[146]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [146]));\n (* SOFT_HLUTNM = \"soft_lutpair1311\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[147]_i_1 \n (.I0(s_axi_wdata[147]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[147]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [147]));\n (* SOFT_HLUTNM = \"soft_lutpair1312\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[148]_i_1 \n (.I0(s_axi_wdata[148]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[148]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [148]));\n (* SOFT_HLUTNM = \"soft_lutpair1313\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[149]_i_1 \n (.I0(s_axi_wdata[149]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[149]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [149]));\n (* SOFT_HLUTNM = \"soft_lutpair1178\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[14]_i_1 \n (.I0(s_axi_wdata[14]),\n .I1(s_axi_wready),\n .I2(wdf_data[14]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [14]));\n (* SOFT_HLUTNM = \"soft_lutpair1314\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[150]_i_1 \n (.I0(s_axi_wdata[150]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[150]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [150]));\n (* SOFT_HLUTNM = \"soft_lutpair1315\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[151]_i_1 \n (.I0(s_axi_wdata[151]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[151]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [151]));\n (* SOFT_HLUTNM = \"soft_lutpair1316\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[152]_i_1 \n (.I0(s_axi_wdata[152]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[152]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [152]));\n (* SOFT_HLUTNM = \"soft_lutpair1317\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[153]_i_1 \n (.I0(s_axi_wdata[153]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[153]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [153]));\n (* SOFT_HLUTNM = \"soft_lutpair1318\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[154]_i_1 \n (.I0(s_axi_wdata[154]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[154]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [154]));\n (* SOFT_HLUTNM = \"soft_lutpair1319\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[155]_i_1 \n (.I0(s_axi_wdata[155]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[155]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [155]));\n (* SOFT_HLUTNM = \"soft_lutpair1320\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[156]_i_1 \n (.I0(s_axi_wdata[156]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[156]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [156]));\n (* SOFT_HLUTNM = \"soft_lutpair1321\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[157]_i_1 \n (.I0(s_axi_wdata[157]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[157]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [157]));\n (* SOFT_HLUTNM = \"soft_lutpair1322\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[158]_i_1 \n (.I0(s_axi_wdata[158]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[158]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [158]));\n (* SOFT_HLUTNM = \"soft_lutpair1323\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[159]_i_1 \n (.I0(s_axi_wdata[159]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[159]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [159]));\n (* SOFT_HLUTNM = \"soft_lutpair1179\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[15]_i_1 \n (.I0(s_axi_wdata[15]),\n .I1(s_axi_wready),\n .I2(wdf_data[15]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [15]));\n (* SOFT_HLUTNM = \"soft_lutpair1324\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[160]_i_1 \n (.I0(s_axi_wdata[160]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[160]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [160]));\n (* SOFT_HLUTNM = \"soft_lutpair1325\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[161]_i_1 \n (.I0(s_axi_wdata[161]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[161]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [161]));\n (* SOFT_HLUTNM = \"soft_lutpair1326\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[162]_i_1 \n (.I0(s_axi_wdata[162]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[162]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [162]));\n (* SOFT_HLUTNM = \"soft_lutpair1327\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[163]_i_1 \n (.I0(s_axi_wdata[163]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[163]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [163]));\n (* SOFT_HLUTNM = \"soft_lutpair1328\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[164]_i_1 \n (.I0(s_axi_wdata[164]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[164]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [164]));\n (* SOFT_HLUTNM = \"soft_lutpair1329\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[165]_i_1 \n (.I0(s_axi_wdata[165]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[165]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [165]));\n (* SOFT_HLUTNM = \"soft_lutpair1330\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[166]_i_1 \n (.I0(s_axi_wdata[166]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[166]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [166]));\n (* SOFT_HLUTNM = \"soft_lutpair1331\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[167]_i_1 \n (.I0(s_axi_wdata[167]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[167]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [167]));\n (* SOFT_HLUTNM = \"soft_lutpair1332\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[168]_i_1 \n (.I0(s_axi_wdata[168]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[168]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [168]));\n (* SOFT_HLUTNM = \"soft_lutpair1333\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[169]_i_1 \n (.I0(s_axi_wdata[169]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[169]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [169]));\n (* SOFT_HLUTNM = \"soft_lutpair1180\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[16]_i_1 \n (.I0(s_axi_wdata[16]),\n .I1(s_axi_wready),\n .I2(wdf_data[16]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [16]));\n (* SOFT_HLUTNM = \"soft_lutpair1334\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[170]_i_1 \n (.I0(s_axi_wdata[170]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[170]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [170]));\n (* SOFT_HLUTNM = \"soft_lutpair1335\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[171]_i_1 \n (.I0(s_axi_wdata[171]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[171]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [171]));\n (* SOFT_HLUTNM = \"soft_lutpair1336\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[172]_i_1 \n (.I0(s_axi_wdata[172]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[172]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [172]));\n (* SOFT_HLUTNM = \"soft_lutpair1337\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[173]_i_1 \n (.I0(s_axi_wdata[173]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[173]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [173]));\n (* SOFT_HLUTNM = \"soft_lutpair1338\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[174]_i_1 \n (.I0(s_axi_wdata[174]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[174]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [174]));\n (* SOFT_HLUTNM = \"soft_lutpair1339\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[175]_i_1 \n (.I0(s_axi_wdata[175]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[175]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [175]));\n (* SOFT_HLUTNM = \"soft_lutpair1340\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[176]_i_1 \n (.I0(s_axi_wdata[176]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[176]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [176]));\n (* SOFT_HLUTNM = \"soft_lutpair1341\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[177]_i_1 \n (.I0(s_axi_wdata[177]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[177]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [177]));\n (* SOFT_HLUTNM = \"soft_lutpair1342\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[178]_i_1 \n (.I0(s_axi_wdata[178]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[178]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [178]));\n (* SOFT_HLUTNM = \"soft_lutpair1343\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[179]_i_1 \n (.I0(s_axi_wdata[179]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[179]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [179]));\n (* SOFT_HLUTNM = \"soft_lutpair1181\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[17]_i_1 \n (.I0(s_axi_wdata[17]),\n .I1(s_axi_wready),\n .I2(wdf_data[17]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [17]));\n (* SOFT_HLUTNM = \"soft_lutpair1344\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[180]_i_1 \n (.I0(s_axi_wdata[180]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[180]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [180]));\n (* SOFT_HLUTNM = \"soft_lutpair1345\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[181]_i_1 \n (.I0(s_axi_wdata[181]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[181]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [181]));\n (* SOFT_HLUTNM = \"soft_lutpair1346\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[182]_i_1 \n (.I0(s_axi_wdata[182]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[182]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [182]));\n (* SOFT_HLUTNM = \"soft_lutpair1347\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[183]_i_1 \n (.I0(s_axi_wdata[183]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[183]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [183]));\n (* SOFT_HLUTNM = \"soft_lutpair1348\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[184]_i_1 \n (.I0(s_axi_wdata[184]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[184]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [184]));\n (* SOFT_HLUTNM = \"soft_lutpair1349\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[185]_i_1 \n (.I0(s_axi_wdata[185]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[185]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [185]));\n (* SOFT_HLUTNM = \"soft_lutpair1350\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[186]_i_1 \n (.I0(s_axi_wdata[186]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[186]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [186]));\n (* SOFT_HLUTNM = \"soft_lutpair1351\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[187]_i_1 \n (.I0(s_axi_wdata[187]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[187]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [187]));\n (* SOFT_HLUTNM = \"soft_lutpair1352\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[188]_i_1 \n (.I0(s_axi_wdata[188]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[188]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [188]));\n (* SOFT_HLUTNM = \"soft_lutpair1353\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[189]_i_1 \n (.I0(s_axi_wdata[189]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[189]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [189]));\n (* SOFT_HLUTNM = \"soft_lutpair1182\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[18]_i_1 \n (.I0(s_axi_wdata[18]),\n .I1(s_axi_wready),\n .I2(wdf_data[18]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [18]));\n (* SOFT_HLUTNM = \"soft_lutpair1354\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[190]_i_1 \n (.I0(s_axi_wdata[190]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[190]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [190]));\n (* SOFT_HLUTNM = \"soft_lutpair1355\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[191]_i_1 \n (.I0(s_axi_wdata[191]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[191]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [191]));\n (* SOFT_HLUTNM = \"soft_lutpair1356\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[192]_i_1 \n (.I0(s_axi_wdata[192]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[192]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [192]));\n (* SOFT_HLUTNM = \"soft_lutpair1357\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[193]_i_1 \n (.I0(s_axi_wdata[193]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[193]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [193]));\n (* SOFT_HLUTNM = \"soft_lutpair1358\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[194]_i_1 \n (.I0(s_axi_wdata[194]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[194]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [194]));\n (* SOFT_HLUTNM = \"soft_lutpair1359\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[195]_i_1 \n (.I0(s_axi_wdata[195]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[195]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [195]));\n (* SOFT_HLUTNM = \"soft_lutpair1360\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[196]_i_1 \n (.I0(s_axi_wdata[196]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[196]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [196]));\n (* SOFT_HLUTNM = \"soft_lutpair1361\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[197]_i_1 \n (.I0(s_axi_wdata[197]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[197]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [197]));\n (* SOFT_HLUTNM = \"soft_lutpair1362\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[198]_i_1 \n (.I0(s_axi_wdata[198]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[198]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [198]));\n (* SOFT_HLUTNM = \"soft_lutpair1363\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[199]_i_1 \n (.I0(s_axi_wdata[199]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[199]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [199]));\n (* SOFT_HLUTNM = \"soft_lutpair1183\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[19]_i_1 \n (.I0(s_axi_wdata[19]),\n .I1(s_axi_wready),\n .I2(wdf_data[19]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [19]));\n (* SOFT_HLUTNM = \"soft_lutpair1165\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[1]_i_1 \n (.I0(s_axi_wdata[1]),\n .I1(s_axi_wready),\n .I2(wdf_data[1]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [1]));\n (* SOFT_HLUTNM = \"soft_lutpair1364\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[200]_i_1 \n (.I0(s_axi_wdata[200]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[200]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [200]));\n (* SOFT_HLUTNM = \"soft_lutpair1365\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[201]_i_1 \n (.I0(s_axi_wdata[201]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[201]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [201]));\n (* SOFT_HLUTNM = \"soft_lutpair1366\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[202]_i_1 \n (.I0(s_axi_wdata[202]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[202]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [202]));\n (* SOFT_HLUTNM = \"soft_lutpair1367\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[203]_i_1 \n (.I0(s_axi_wdata[203]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[203]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [203]));\n (* SOFT_HLUTNM = \"soft_lutpair1368\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[204]_i_1 \n (.I0(s_axi_wdata[204]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[204]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [204]));\n (* SOFT_HLUTNM = \"soft_lutpair1369\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[205]_i_1 \n (.I0(s_axi_wdata[205]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[205]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [205]));\n (* SOFT_HLUTNM = \"soft_lutpair1370\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[206]_i_1 \n (.I0(s_axi_wdata[206]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[206]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [206]));\n (* SOFT_HLUTNM = \"soft_lutpair1371\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[207]_i_1 \n (.I0(s_axi_wdata[207]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[207]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [207]));\n (* SOFT_HLUTNM = \"soft_lutpair1372\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[208]_i_1 \n (.I0(s_axi_wdata[208]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[208]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [208]));\n (* SOFT_HLUTNM = \"soft_lutpair1373\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[209]_i_1 \n (.I0(s_axi_wdata[209]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[209]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [209]));\n (* SOFT_HLUTNM = \"soft_lutpair1184\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[20]_i_1 \n (.I0(s_axi_wdata[20]),\n .I1(s_axi_wready),\n .I2(wdf_data[20]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [20]));\n (* SOFT_HLUTNM = \"soft_lutpair1374\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[210]_i_1 \n (.I0(s_axi_wdata[210]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[210]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [210]));\n (* SOFT_HLUTNM = \"soft_lutpair1375\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[211]_i_1 \n (.I0(s_axi_wdata[211]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[211]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [211]));\n (* SOFT_HLUTNM = \"soft_lutpair1376\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[212]_i_1 \n (.I0(s_axi_wdata[212]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[212]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [212]));\n (* SOFT_HLUTNM = \"soft_lutpair1377\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[213]_i_1 \n (.I0(s_axi_wdata[213]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[213]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [213]));\n (* SOFT_HLUTNM = \"soft_lutpair1378\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[214]_i_1 \n (.I0(s_axi_wdata[214]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[214]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [214]));\n (* SOFT_HLUTNM = \"soft_lutpair1379\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[215]_i_1 \n (.I0(s_axi_wdata[215]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[215]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [215]));\n (* SOFT_HLUTNM = \"soft_lutpair1380\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[216]_i_1 \n (.I0(s_axi_wdata[216]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[216]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [216]));\n (* SOFT_HLUTNM = \"soft_lutpair1381\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[217]_i_1 \n (.I0(s_axi_wdata[217]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[217]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [217]));\n (* SOFT_HLUTNM = \"soft_lutpair1382\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[218]_i_1 \n (.I0(s_axi_wdata[218]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[218]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [218]));\n (* SOFT_HLUTNM = \"soft_lutpair1383\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[219]_i_1 \n (.I0(s_axi_wdata[219]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[219]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [219]));\n (* SOFT_HLUTNM = \"soft_lutpair1185\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[21]_i_1 \n (.I0(s_axi_wdata[21]),\n .I1(s_axi_wready),\n .I2(wdf_data[21]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [21]));\n (* SOFT_HLUTNM = \"soft_lutpair1384\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[220]_i_1 \n (.I0(s_axi_wdata[220]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[220]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [220]));\n (* SOFT_HLUTNM = \"soft_lutpair1385\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[221]_i_1 \n (.I0(s_axi_wdata[221]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[221]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [221]));\n (* SOFT_HLUTNM = \"soft_lutpair1386\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[222]_i_1 \n (.I0(s_axi_wdata[222]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[222]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [222]));\n (* SOFT_HLUTNM = \"soft_lutpair1387\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[223]_i_1 \n (.I0(s_axi_wdata[223]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[223]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [223]));\n (* SOFT_HLUTNM = \"soft_lutpair1388\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[224]_i_1 \n (.I0(s_axi_wdata[224]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[224]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [224]));\n (* SOFT_HLUTNM = \"soft_lutpair1389\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[225]_i_1 \n (.I0(s_axi_wdata[225]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[225]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [225]));\n (* SOFT_HLUTNM = \"soft_lutpair1390\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[226]_i_1 \n (.I0(s_axi_wdata[226]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[226]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [226]));\n (* SOFT_HLUTNM = \"soft_lutpair1391\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[227]_i_1 \n (.I0(s_axi_wdata[227]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[227]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [227]));\n (* SOFT_HLUTNM = \"soft_lutpair1392\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[228]_i_1 \n (.I0(s_axi_wdata[228]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[228]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [228]));\n (* SOFT_HLUTNM = \"soft_lutpair1393\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[229]_i_1 \n (.I0(s_axi_wdata[229]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[229]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [229]));\n (* SOFT_HLUTNM = \"soft_lutpair1186\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[22]_i_1 \n (.I0(s_axi_wdata[22]),\n .I1(s_axi_wready),\n .I2(wdf_data[22]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [22]));\n (* SOFT_HLUTNM = \"soft_lutpair1394\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[230]_i_1 \n (.I0(s_axi_wdata[230]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[230]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [230]));\n (* SOFT_HLUTNM = \"soft_lutpair1395\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[231]_i_1 \n (.I0(s_axi_wdata[231]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[231]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [231]));\n (* SOFT_HLUTNM = \"soft_lutpair1396\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[232]_i_1 \n (.I0(s_axi_wdata[232]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[232]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [232]));\n (* SOFT_HLUTNM = \"soft_lutpair1397\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[233]_i_1 \n (.I0(s_axi_wdata[233]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[233]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [233]));\n (* SOFT_HLUTNM = \"soft_lutpair1398\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[234]_i_1 \n (.I0(s_axi_wdata[234]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[234]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [234]));\n (* SOFT_HLUTNM = \"soft_lutpair1399\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[235]_i_1 \n (.I0(s_axi_wdata[235]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[235]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [235]));\n (* SOFT_HLUTNM = \"soft_lutpair1400\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[236]_i_1 \n (.I0(s_axi_wdata[236]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[236]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [236]));\n (* SOFT_HLUTNM = \"soft_lutpair1401\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[237]_i_1 \n (.I0(s_axi_wdata[237]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[237]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [237]));\n (* SOFT_HLUTNM = \"soft_lutpair1402\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[238]_i_1 \n (.I0(s_axi_wdata[238]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[238]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [238]));\n (* SOFT_HLUTNM = \"soft_lutpair1403\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[239]_i_1 \n (.I0(s_axi_wdata[239]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[239]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [239]));\n (* SOFT_HLUTNM = \"soft_lutpair1187\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[23]_i_1 \n (.I0(s_axi_wdata[23]),\n .I1(s_axi_wready),\n .I2(wdf_data[23]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [23]));\n (* SOFT_HLUTNM = \"soft_lutpair1404\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[240]_i_1 \n (.I0(s_axi_wdata[240]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[240]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [240]));\n (* SOFT_HLUTNM = \"soft_lutpair1405\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[241]_i_1 \n (.I0(s_axi_wdata[241]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[241]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [241]));\n (* SOFT_HLUTNM = \"soft_lutpair1406\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[242]_i_1 \n (.I0(s_axi_wdata[242]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[242]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [242]));\n (* SOFT_HLUTNM = \"soft_lutpair1407\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[243]_i_1 \n (.I0(s_axi_wdata[243]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[243]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [243]));\n (* SOFT_HLUTNM = \"soft_lutpair1408\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[244]_i_1 \n (.I0(s_axi_wdata[244]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[244]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [244]));\n (* SOFT_HLUTNM = \"soft_lutpair1409\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[245]_i_1 \n (.I0(s_axi_wdata[245]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[245]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [245]));\n (* SOFT_HLUTNM = \"soft_lutpair1410\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[246]_i_1 \n (.I0(s_axi_wdata[246]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[246]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [246]));\n (* SOFT_HLUTNM = \"soft_lutpair1411\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[247]_i_1 \n (.I0(s_axi_wdata[247]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[247]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [247]));\n (* SOFT_HLUTNM = \"soft_lutpair1412\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[248]_i_1 \n (.I0(s_axi_wdata[248]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[248]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [248]));\n (* SOFT_HLUTNM = \"soft_lutpair1413\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[249]_i_1 \n (.I0(s_axi_wdata[249]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[249]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [249]));\n (* SOFT_HLUTNM = \"soft_lutpair1188\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[24]_i_1 \n (.I0(s_axi_wdata[24]),\n .I1(s_axi_wready),\n .I2(wdf_data[24]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [24]));\n (* SOFT_HLUTNM = \"soft_lutpair1414\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[250]_i_1 \n (.I0(s_axi_wdata[250]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[250]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [250]));\n (* SOFT_HLUTNM = \"soft_lutpair1415\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[251]_i_1 \n (.I0(s_axi_wdata[251]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[251]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [251]));\n (* SOFT_HLUTNM = \"soft_lutpair1416\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[252]_i_1 \n (.I0(s_axi_wdata[252]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[252]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [252]));\n (* SOFT_HLUTNM = \"soft_lutpair1417\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[253]_i_1 \n (.I0(s_axi_wdata[253]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[253]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [253]));\n (* SOFT_HLUTNM = \"soft_lutpair1418\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[254]_i_1 \n (.I0(s_axi_wdata[254]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[254]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [254]));\n (* SOFT_HLUTNM = \"soft_lutpair1419\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[255]_i_1 \n (.I0(s_axi_wdata[255]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[255]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [255]));\n (* SOFT_HLUTNM = \"soft_lutpair1189\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[25]_i_1 \n (.I0(s_axi_wdata[25]),\n .I1(s_axi_wready),\n .I2(wdf_data[25]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [25]));\n (* SOFT_HLUTNM = \"soft_lutpair1190\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[26]_i_1 \n (.I0(s_axi_wdata[26]),\n .I1(s_axi_wready),\n .I2(wdf_data[26]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [26]));\n (* SOFT_HLUTNM = \"soft_lutpair1191\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[27]_i_1 \n (.I0(s_axi_wdata[27]),\n .I1(s_axi_wready),\n .I2(wdf_data[27]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [27]));\n (* SOFT_HLUTNM = \"soft_lutpair1192\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[28]_i_1 \n (.I0(s_axi_wdata[28]),\n .I1(s_axi_wready),\n .I2(wdf_data[28]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [28]));\n (* SOFT_HLUTNM = \"soft_lutpair1193\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[29]_i_1 \n (.I0(s_axi_wdata[29]),\n .I1(s_axi_wready),\n .I2(wdf_data[29]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [29]));\n (* SOFT_HLUTNM = \"soft_lutpair1166\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[2]_i_1 \n (.I0(s_axi_wdata[2]),\n .I1(s_axi_wready),\n .I2(wdf_data[2]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [2]));\n (* SOFT_HLUTNM = \"soft_lutpair1194\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[30]_i_1 \n (.I0(s_axi_wdata[30]),\n .I1(s_axi_wready),\n .I2(wdf_data[30]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [30]));\n (* SOFT_HLUTNM = \"soft_lutpair1195\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[31]_i_1 \n (.I0(s_axi_wdata[31]),\n .I1(s_axi_wready),\n .I2(wdf_data[31]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [31]));\n (* SOFT_HLUTNM = \"soft_lutpair1196\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[32]_i_1 \n (.I0(s_axi_wdata[32]),\n .I1(s_axi_wready),\n .I2(wdf_data[32]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [32]));\n (* SOFT_HLUTNM = \"soft_lutpair1197\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[33]_i_1 \n (.I0(s_axi_wdata[33]),\n .I1(s_axi_wready),\n .I2(wdf_data[33]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [33]));\n (* SOFT_HLUTNM = \"soft_lutpair1198\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[34]_i_1 \n (.I0(s_axi_wdata[34]),\n .I1(s_axi_wready),\n .I2(wdf_data[34]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [34]));\n (* SOFT_HLUTNM = \"soft_lutpair1199\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[35]_i_1 \n (.I0(s_axi_wdata[35]),\n .I1(s_axi_wready),\n .I2(wdf_data[35]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [35]));\n (* SOFT_HLUTNM = \"soft_lutpair1200\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[36]_i_1 \n (.I0(s_axi_wdata[36]),\n .I1(s_axi_wready),\n .I2(wdf_data[36]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [36]));\n (* SOFT_HLUTNM = \"soft_lutpair1201\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[37]_i_1 \n (.I0(s_axi_wdata[37]),\n .I1(s_axi_wready),\n .I2(wdf_data[37]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [37]));\n (* SOFT_HLUTNM = \"soft_lutpair1202\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[38]_i_1 \n (.I0(s_axi_wdata[38]),\n .I1(s_axi_wready),\n .I2(wdf_data[38]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [38]));\n (* SOFT_HLUTNM = \"soft_lutpair1203\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[39]_i_1 \n (.I0(s_axi_wdata[39]),\n .I1(s_axi_wready),\n .I2(wdf_data[39]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [39]));\n (* SOFT_HLUTNM = \"soft_lutpair1167\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[3]_i_1 \n (.I0(s_axi_wdata[3]),\n .I1(s_axi_wready),\n .I2(wdf_data[3]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [3]));\n (* SOFT_HLUTNM = \"soft_lutpair1204\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[40]_i_1 \n (.I0(s_axi_wdata[40]),\n .I1(s_axi_wready),\n .I2(wdf_data[40]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [40]));\n (* SOFT_HLUTNM = \"soft_lutpair1205\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[41]_i_1 \n (.I0(s_axi_wdata[41]),\n .I1(s_axi_wready),\n .I2(wdf_data[41]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [41]));\n (* SOFT_HLUTNM = \"soft_lutpair1206\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[42]_i_1 \n (.I0(s_axi_wdata[42]),\n .I1(s_axi_wready),\n .I2(wdf_data[42]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [42]));\n (* SOFT_HLUTNM = \"soft_lutpair1207\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[43]_i_1 \n (.I0(s_axi_wdata[43]),\n .I1(s_axi_wready),\n .I2(wdf_data[43]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [43]));\n (* SOFT_HLUTNM = \"soft_lutpair1208\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[44]_i_1 \n (.I0(s_axi_wdata[44]),\n .I1(s_axi_wready),\n .I2(wdf_data[44]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [44]));\n (* SOFT_HLUTNM = \"soft_lutpair1209\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[45]_i_1 \n (.I0(s_axi_wdata[45]),\n .I1(s_axi_wready),\n .I2(wdf_data[45]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [45]));\n (* SOFT_HLUTNM = \"soft_lutpair1210\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[46]_i_1 \n (.I0(s_axi_wdata[46]),\n .I1(s_axi_wready),\n .I2(wdf_data[46]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [46]));\n (* SOFT_HLUTNM = \"soft_lutpair1211\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[47]_i_1 \n (.I0(s_axi_wdata[47]),\n .I1(s_axi_wready),\n .I2(wdf_data[47]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [47]));\n (* SOFT_HLUTNM = \"soft_lutpair1212\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[48]_i_1 \n (.I0(s_axi_wdata[48]),\n .I1(s_axi_wready),\n .I2(wdf_data[48]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [48]));\n (* SOFT_HLUTNM = \"soft_lutpair1213\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[49]_i_1 \n (.I0(s_axi_wdata[49]),\n .I1(s_axi_wready),\n .I2(wdf_data[49]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [49]));\n (* SOFT_HLUTNM = \"soft_lutpair1168\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[4]_i_1 \n (.I0(s_axi_wdata[4]),\n .I1(s_axi_wready),\n .I2(wdf_data[4]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [4]));\n (* SOFT_HLUTNM = \"soft_lutpair1214\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[50]_i_1 \n (.I0(s_axi_wdata[50]),\n .I1(s_axi_wready),\n .I2(wdf_data[50]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [50]));\n (* SOFT_HLUTNM = \"soft_lutpair1215\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[51]_i_1 \n (.I0(s_axi_wdata[51]),\n .I1(s_axi_wready),\n .I2(wdf_data[51]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [51]));\n (* SOFT_HLUTNM = \"soft_lutpair1216\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[52]_i_1 \n (.I0(s_axi_wdata[52]),\n .I1(s_axi_wready),\n .I2(wdf_data[52]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [52]));\n (* SOFT_HLUTNM = \"soft_lutpair1217\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[53]_i_1 \n (.I0(s_axi_wdata[53]),\n .I1(s_axi_wready),\n .I2(wdf_data[53]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [53]));\n (* SOFT_HLUTNM = \"soft_lutpair1218\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[54]_i_1 \n (.I0(s_axi_wdata[54]),\n .I1(s_axi_wready),\n .I2(wdf_data[54]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [54]));\n (* SOFT_HLUTNM = \"soft_lutpair1219\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[55]_i_1 \n (.I0(s_axi_wdata[55]),\n .I1(s_axi_wready),\n .I2(wdf_data[55]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [55]));\n (* SOFT_HLUTNM = \"soft_lutpair1220\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[56]_i_1 \n (.I0(s_axi_wdata[56]),\n .I1(s_axi_wready),\n .I2(wdf_data[56]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [56]));\n (* SOFT_HLUTNM = \"soft_lutpair1221\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[57]_i_1 \n (.I0(s_axi_wdata[57]),\n .I1(s_axi_wready),\n .I2(wdf_data[57]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [57]));\n (* SOFT_HLUTNM = \"soft_lutpair1222\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[58]_i_1 \n (.I0(s_axi_wdata[58]),\n .I1(s_axi_wready),\n .I2(wdf_data[58]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [58]));\n (* SOFT_HLUTNM = \"soft_lutpair1223\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[59]_i_1 \n (.I0(s_axi_wdata[59]),\n .I1(s_axi_wready),\n .I2(wdf_data[59]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [59]));\n (* SOFT_HLUTNM = \"soft_lutpair1169\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[5]_i_1 \n (.I0(s_axi_wdata[5]),\n .I1(s_axi_wready),\n .I2(wdf_data[5]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [5]));\n (* SOFT_HLUTNM = \"soft_lutpair1224\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[60]_i_1 \n (.I0(s_axi_wdata[60]),\n .I1(s_axi_wready),\n .I2(wdf_data[60]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [60]));\n (* SOFT_HLUTNM = \"soft_lutpair1225\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[61]_i_1 \n (.I0(s_axi_wdata[61]),\n .I1(s_axi_wready),\n .I2(wdf_data[61]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [61]));\n (* SOFT_HLUTNM = \"soft_lutpair1226\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[62]_i_1 \n (.I0(s_axi_wdata[62]),\n .I1(s_axi_wready),\n .I2(wdf_data[62]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [62]));\n (* SOFT_HLUTNM = \"soft_lutpair1227\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[63]_i_1 \n (.I0(s_axi_wdata[63]),\n .I1(s_axi_wready),\n .I2(wdf_data[63]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [63]));\n (* SOFT_HLUTNM = \"soft_lutpair1228\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[64]_i_1 \n (.I0(s_axi_wdata[64]),\n .I1(s_axi_wready),\n .I2(wdf_data[64]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [64]));\n (* SOFT_HLUTNM = \"soft_lutpair1229\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[65]_i_1 \n (.I0(s_axi_wdata[65]),\n .I1(s_axi_wready),\n .I2(wdf_data[65]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [65]));\n (* SOFT_HLUTNM = \"soft_lutpair1230\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[66]_i_1 \n (.I0(s_axi_wdata[66]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[66]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [66]));\n (* SOFT_HLUTNM = \"soft_lutpair1231\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[67]_i_1 \n (.I0(s_axi_wdata[67]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[67]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [67]));\n (* SOFT_HLUTNM = \"soft_lutpair1232\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[68]_i_1 \n (.I0(s_axi_wdata[68]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[68]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [68]));\n (* SOFT_HLUTNM = \"soft_lutpair1233\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[69]_i_1 \n (.I0(s_axi_wdata[69]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[69]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [69]));\n (* SOFT_HLUTNM = \"soft_lutpair1170\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[6]_i_1 \n (.I0(s_axi_wdata[6]),\n .I1(s_axi_wready),\n .I2(wdf_data[6]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [6]));\n (* SOFT_HLUTNM = \"soft_lutpair1234\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[70]_i_1 \n (.I0(s_axi_wdata[70]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[70]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [70]));\n (* SOFT_HLUTNM = \"soft_lutpair1235\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[71]_i_1 \n (.I0(s_axi_wdata[71]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[71]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [71]));\n (* SOFT_HLUTNM = \"soft_lutpair1236\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[72]_i_1 \n (.I0(s_axi_wdata[72]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[72]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [72]));\n (* SOFT_HLUTNM = \"soft_lutpair1237\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[73]_i_1 \n (.I0(s_axi_wdata[73]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[73]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [73]));\n (* SOFT_HLUTNM = \"soft_lutpair1238\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[74]_i_1 \n (.I0(s_axi_wdata[74]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[74]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [74]));\n (* SOFT_HLUTNM = \"soft_lutpair1239\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[75]_i_1 \n (.I0(s_axi_wdata[75]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[75]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [75]));\n (* SOFT_HLUTNM = \"soft_lutpair1240\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[76]_i_1 \n (.I0(s_axi_wdata[76]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[76]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [76]));\n (* SOFT_HLUTNM = \"soft_lutpair1241\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[77]_i_1 \n (.I0(s_axi_wdata[77]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[77]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [77]));\n (* SOFT_HLUTNM = \"soft_lutpair1242\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[78]_i_1 \n (.I0(s_axi_wdata[78]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[78]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [78]));\n (* SOFT_HLUTNM = \"soft_lutpair1243\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[79]_i_1 \n (.I0(s_axi_wdata[79]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[79]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [79]));\n (* SOFT_HLUTNM = \"soft_lutpair1171\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[7]_i_1 \n (.I0(s_axi_wdata[7]),\n .I1(s_axi_wready),\n .I2(wdf_data[7]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [7]));\n (* SOFT_HLUTNM = \"soft_lutpair1244\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[80]_i_1 \n (.I0(s_axi_wdata[80]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[80]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [80]));\n (* SOFT_HLUTNM = \"soft_lutpair1245\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[81]_i_1 \n (.I0(s_axi_wdata[81]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[81]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [81]));\n (* SOFT_HLUTNM = \"soft_lutpair1246\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[82]_i_1 \n (.I0(s_axi_wdata[82]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[82]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [82]));\n (* SOFT_HLUTNM = \"soft_lutpair1247\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[83]_i_1 \n (.I0(s_axi_wdata[83]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[83]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [83]));\n (* SOFT_HLUTNM = \"soft_lutpair1248\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[84]_i_1 \n (.I0(s_axi_wdata[84]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[84]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [84]));\n (* SOFT_HLUTNM = \"soft_lutpair1249\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[85]_i_1 \n (.I0(s_axi_wdata[85]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[85]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [85]));\n (* SOFT_HLUTNM = \"soft_lutpair1250\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[86]_i_1 \n (.I0(s_axi_wdata[86]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[86]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [86]));\n (* SOFT_HLUTNM = \"soft_lutpair1251\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[87]_i_1 \n (.I0(s_axi_wdata[87]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[87]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [87]));\n (* SOFT_HLUTNM = \"soft_lutpair1252\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[88]_i_1 \n (.I0(s_axi_wdata[88]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[88]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [88]));\n (* SOFT_HLUTNM = \"soft_lutpair1253\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[89]_i_1 \n (.I0(s_axi_wdata[89]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[89]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [89]));\n (* SOFT_HLUTNM = \"soft_lutpair1172\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[8]_i_1 \n (.I0(s_axi_wdata[8]),\n .I1(s_axi_wready),\n .I2(wdf_data[8]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [8]));\n (* SOFT_HLUTNM = \"soft_lutpair1254\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[90]_i_1 \n (.I0(s_axi_wdata[90]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[90]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [90]));\n (* SOFT_HLUTNM = \"soft_lutpair1255\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[91]_i_1 \n (.I0(s_axi_wdata[91]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[91]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [91]));\n (* SOFT_HLUTNM = \"soft_lutpair1256\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[92]_i_1 \n (.I0(s_axi_wdata[92]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[92]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [92]));\n (* SOFT_HLUTNM = \"soft_lutpair1257\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[93]_i_1 \n (.I0(s_axi_wdata[93]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[93]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [93]));\n (* SOFT_HLUTNM = \"soft_lutpair1258\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[94]_i_1 \n (.I0(s_axi_wdata[94]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[94]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [94]));\n (* SOFT_HLUTNM = \"soft_lutpair1259\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[95]_i_1 \n (.I0(s_axi_wdata[95]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[95]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [95]));\n (* SOFT_HLUTNM = \"soft_lutpair1260\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[96]_i_1 \n (.I0(s_axi_wdata[96]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[96]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [96]));\n (* SOFT_HLUTNM = \"soft_lutpair1261\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[97]_i_1 \n (.I0(s_axi_wdata[97]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[97]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [97]));\n (* SOFT_HLUTNM = \"soft_lutpair1262\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[98]_i_1 \n (.I0(s_axi_wdata[98]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[98]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [98]));\n (* SOFT_HLUTNM = \"soft_lutpair1263\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[99]_i_1 \n (.I0(s_axi_wdata[99]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[99]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [99]));\n (* SOFT_HLUTNM = \"soft_lutpair1173\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[9]_i_1 \n (.I0(s_axi_wdata[9]),\n .I1(s_axi_wready),\n .I2(wdf_data[9]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [9]));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[0] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [0]),\n .Q(mc_app_wdf_data_reg[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[100] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [100]),\n .Q(mc_app_wdf_data_reg[100]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[101] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [101]),\n .Q(mc_app_wdf_data_reg[101]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[102] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [102]),\n .Q(mc_app_wdf_data_reg[102]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[103] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [103]),\n .Q(mc_app_wdf_data_reg[103]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[104] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [104]),\n .Q(mc_app_wdf_data_reg[104]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[105] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [105]),\n .Q(mc_app_wdf_data_reg[105]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[106] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [106]),\n .Q(mc_app_wdf_data_reg[106]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[107] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [107]),\n .Q(mc_app_wdf_data_reg[107]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[108] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [108]),\n .Q(mc_app_wdf_data_reg[108]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[109] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [109]),\n .Q(mc_app_wdf_data_reg[109]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[10] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [10]),\n .Q(mc_app_wdf_data_reg[10]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[110] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [110]),\n .Q(mc_app_wdf_data_reg[110]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[111] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [111]),\n .Q(mc_app_wdf_data_reg[111]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[112] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [112]),\n .Q(mc_app_wdf_data_reg[112]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[113] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [113]),\n .Q(mc_app_wdf_data_reg[113]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[114] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [114]),\n .Q(mc_app_wdf_data_reg[114]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[115] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [115]),\n .Q(mc_app_wdf_data_reg[115]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[116] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [116]),\n .Q(mc_app_wdf_data_reg[116]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[117] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [117]),\n .Q(mc_app_wdf_data_reg[117]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[118] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [118]),\n .Q(mc_app_wdf_data_reg[118]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[119] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [119]),\n .Q(mc_app_wdf_data_reg[119]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[11] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [11]),\n .Q(mc_app_wdf_data_reg[11]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[120] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [120]),\n .Q(mc_app_wdf_data_reg[120]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[121] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [121]),\n .Q(mc_app_wdf_data_reg[121]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[122] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [122]),\n .Q(mc_app_wdf_data_reg[122]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[123] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [123]),\n .Q(mc_app_wdf_data_reg[123]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[124] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [124]),\n .Q(mc_app_wdf_data_reg[124]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[125] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [125]),\n .Q(mc_app_wdf_data_reg[125]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[126] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [126]),\n .Q(mc_app_wdf_data_reg[126]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[127] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [127]),\n .Q(mc_app_wdf_data_reg[127]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[128] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [128]),\n .Q(mc_app_wdf_data_reg[128]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[129] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [129]),\n .Q(mc_app_wdf_data_reg[129]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[12] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [12]),\n .Q(mc_app_wdf_data_reg[12]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[130] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [130]),\n .Q(mc_app_wdf_data_reg[130]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[131] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [131]),\n .Q(mc_app_wdf_data_reg[131]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[132] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [132]),\n .Q(mc_app_wdf_data_reg[132]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[133] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [133]),\n .Q(mc_app_wdf_data_reg[133]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[134] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [134]),\n .Q(mc_app_wdf_data_reg[134]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[135] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [135]),\n .Q(mc_app_wdf_data_reg[135]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[136] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [136]),\n .Q(mc_app_wdf_data_reg[136]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[137] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [137]),\n .Q(mc_app_wdf_data_reg[137]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[138] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [138]),\n .Q(mc_app_wdf_data_reg[138]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[139] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [139]),\n .Q(mc_app_wdf_data_reg[139]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[13] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [13]),\n .Q(mc_app_wdf_data_reg[13]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[140] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [140]),\n .Q(mc_app_wdf_data_reg[140]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[141] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [141]),\n .Q(mc_app_wdf_data_reg[141]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[142] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [142]),\n .Q(mc_app_wdf_data_reg[142]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[143] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [143]),\n .Q(mc_app_wdf_data_reg[143]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[144] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [144]),\n .Q(mc_app_wdf_data_reg[144]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[145] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [145]),\n .Q(mc_app_wdf_data_reg[145]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[146] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [146]),\n .Q(mc_app_wdf_data_reg[146]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[147] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [147]),\n .Q(mc_app_wdf_data_reg[147]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[148] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [148]),\n .Q(mc_app_wdf_data_reg[148]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[149] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [149]),\n .Q(mc_app_wdf_data_reg[149]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[14] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [14]),\n .Q(mc_app_wdf_data_reg[14]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[150] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [150]),\n .Q(mc_app_wdf_data_reg[150]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[151] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [151]),\n .Q(mc_app_wdf_data_reg[151]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[152] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [152]),\n .Q(mc_app_wdf_data_reg[152]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[153] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [153]),\n .Q(mc_app_wdf_data_reg[153]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[154] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [154]),\n .Q(mc_app_wdf_data_reg[154]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[155] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [155]),\n .Q(mc_app_wdf_data_reg[155]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[156] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [156]),\n .Q(mc_app_wdf_data_reg[156]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[157] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [157]),\n .Q(mc_app_wdf_data_reg[157]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[158] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [158]),\n .Q(mc_app_wdf_data_reg[158]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[159] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [159]),\n .Q(mc_app_wdf_data_reg[159]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[15] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [15]),\n .Q(mc_app_wdf_data_reg[15]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[160] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [160]),\n .Q(mc_app_wdf_data_reg[160]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[161] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [161]),\n .Q(mc_app_wdf_data_reg[161]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[162] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [162]),\n .Q(mc_app_wdf_data_reg[162]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[163] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [163]),\n .Q(mc_app_wdf_data_reg[163]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[164] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [164]),\n .Q(mc_app_wdf_data_reg[164]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[165] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [165]),\n .Q(mc_app_wdf_data_reg[165]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[166] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [166]),\n .Q(mc_app_wdf_data_reg[166]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[167] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [167]),\n .Q(mc_app_wdf_data_reg[167]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[168] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [168]),\n .Q(mc_app_wdf_data_reg[168]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[169] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [169]),\n .Q(mc_app_wdf_data_reg[169]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[16] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [16]),\n .Q(mc_app_wdf_data_reg[16]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[170] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [170]),\n .Q(mc_app_wdf_data_reg[170]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[171] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [171]),\n .Q(mc_app_wdf_data_reg[171]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[172] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [172]),\n .Q(mc_app_wdf_data_reg[172]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[173] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [173]),\n .Q(mc_app_wdf_data_reg[173]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[174] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [174]),\n .Q(mc_app_wdf_data_reg[174]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[175] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [175]),\n .Q(mc_app_wdf_data_reg[175]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[176] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [176]),\n .Q(mc_app_wdf_data_reg[176]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[177] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [177]),\n .Q(mc_app_wdf_data_reg[177]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[178] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [178]),\n .Q(mc_app_wdf_data_reg[178]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[179] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [179]),\n .Q(mc_app_wdf_data_reg[179]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[17] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [17]),\n .Q(mc_app_wdf_data_reg[17]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[180] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [180]),\n .Q(mc_app_wdf_data_reg[180]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[181] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [181]),\n .Q(mc_app_wdf_data_reg[181]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[182] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [182]),\n .Q(mc_app_wdf_data_reg[182]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[183] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [183]),\n .Q(mc_app_wdf_data_reg[183]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[184] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [184]),\n .Q(mc_app_wdf_data_reg[184]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[185] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [185]),\n .Q(mc_app_wdf_data_reg[185]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[186] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [186]),\n .Q(mc_app_wdf_data_reg[186]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[187] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [187]),\n .Q(mc_app_wdf_data_reg[187]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[188] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [188]),\n .Q(mc_app_wdf_data_reg[188]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[189] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [189]),\n .Q(mc_app_wdf_data_reg[189]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[18] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [18]),\n .Q(mc_app_wdf_data_reg[18]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[190] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [190]),\n .Q(mc_app_wdf_data_reg[190]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[191] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [191]),\n .Q(mc_app_wdf_data_reg[191]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[192] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [192]),\n .Q(mc_app_wdf_data_reg[192]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[193] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [193]),\n .Q(mc_app_wdf_data_reg[193]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[194] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [194]),\n .Q(mc_app_wdf_data_reg[194]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[195] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [195]),\n .Q(mc_app_wdf_data_reg[195]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[196] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [196]),\n .Q(mc_app_wdf_data_reg[196]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[197] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [197]),\n .Q(mc_app_wdf_data_reg[197]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[198] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [198]),\n .Q(mc_app_wdf_data_reg[198]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[199] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [199]),\n .Q(mc_app_wdf_data_reg[199]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[19] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [19]),\n .Q(mc_app_wdf_data_reg[19]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[1] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [1]),\n .Q(mc_app_wdf_data_reg[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[200] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [200]),\n .Q(mc_app_wdf_data_reg[200]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[201] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [201]),\n .Q(mc_app_wdf_data_reg[201]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[202] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [202]),\n .Q(mc_app_wdf_data_reg[202]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[203] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [203]),\n .Q(mc_app_wdf_data_reg[203]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[204] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [204]),\n .Q(mc_app_wdf_data_reg[204]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[205] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [205]),\n .Q(mc_app_wdf_data_reg[205]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[206] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [206]),\n .Q(mc_app_wdf_data_reg[206]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[207] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [207]),\n .Q(mc_app_wdf_data_reg[207]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[208] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [208]),\n .Q(mc_app_wdf_data_reg[208]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[209] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [209]),\n .Q(mc_app_wdf_data_reg[209]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[20] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [20]),\n .Q(mc_app_wdf_data_reg[20]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[210] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [210]),\n .Q(mc_app_wdf_data_reg[210]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[211] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [211]),\n .Q(mc_app_wdf_data_reg[211]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[212] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [212]),\n .Q(mc_app_wdf_data_reg[212]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[213] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [213]),\n .Q(mc_app_wdf_data_reg[213]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[214] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [214]),\n .Q(mc_app_wdf_data_reg[214]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[215] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [215]),\n .Q(mc_app_wdf_data_reg[215]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[216] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [216]),\n .Q(mc_app_wdf_data_reg[216]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[217] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [217]),\n .Q(mc_app_wdf_data_reg[217]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[218] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [218]),\n .Q(mc_app_wdf_data_reg[218]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[219] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [219]),\n .Q(mc_app_wdf_data_reg[219]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[21] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [21]),\n .Q(mc_app_wdf_data_reg[21]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[220] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [220]),\n .Q(mc_app_wdf_data_reg[220]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[221] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [221]),\n .Q(mc_app_wdf_data_reg[221]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[222] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [222]),\n .Q(mc_app_wdf_data_reg[222]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[223] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [223]),\n .Q(mc_app_wdf_data_reg[223]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[224] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [224]),\n .Q(mc_app_wdf_data_reg[224]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[225] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [225]),\n .Q(mc_app_wdf_data_reg[225]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[226] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [226]),\n .Q(mc_app_wdf_data_reg[226]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[227] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [227]),\n .Q(mc_app_wdf_data_reg[227]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[228] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [228]),\n .Q(mc_app_wdf_data_reg[228]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[229] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [229]),\n .Q(mc_app_wdf_data_reg[229]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[22] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [22]),\n .Q(mc_app_wdf_data_reg[22]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[230] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [230]),\n .Q(mc_app_wdf_data_reg[230]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[231] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [231]),\n .Q(mc_app_wdf_data_reg[231]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[232] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [232]),\n .Q(mc_app_wdf_data_reg[232]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[233] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [233]),\n .Q(mc_app_wdf_data_reg[233]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[234] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [234]),\n .Q(mc_app_wdf_data_reg[234]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[235] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [235]),\n .Q(mc_app_wdf_data_reg[235]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[236] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [236]),\n .Q(mc_app_wdf_data_reg[236]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[237] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [237]),\n .Q(mc_app_wdf_data_reg[237]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[238] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [238]),\n .Q(mc_app_wdf_data_reg[238]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[239] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [239]),\n .Q(mc_app_wdf_data_reg[239]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[23] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [23]),\n .Q(mc_app_wdf_data_reg[23]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[240] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [240]),\n .Q(mc_app_wdf_data_reg[240]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[241] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [241]),\n .Q(mc_app_wdf_data_reg[241]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[242] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [242]),\n .Q(mc_app_wdf_data_reg[242]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[243] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [243]),\n .Q(mc_app_wdf_data_reg[243]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[244] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [244]),\n .Q(mc_app_wdf_data_reg[244]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[245] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [245]),\n .Q(mc_app_wdf_data_reg[245]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[246] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [246]),\n .Q(mc_app_wdf_data_reg[246]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[247] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [247]),\n .Q(mc_app_wdf_data_reg[247]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[248] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [248]),\n .Q(mc_app_wdf_data_reg[248]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[249] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [249]),\n .Q(mc_app_wdf_data_reg[249]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[24] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [24]),\n .Q(mc_app_wdf_data_reg[24]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[250] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [250]),\n .Q(mc_app_wdf_data_reg[250]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[251] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [251]),\n .Q(mc_app_wdf_data_reg[251]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[252] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [252]),\n .Q(mc_app_wdf_data_reg[252]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[253] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [253]),\n .Q(mc_app_wdf_data_reg[253]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[254] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [254]),\n .Q(mc_app_wdf_data_reg[254]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[255] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [255]),\n .Q(mc_app_wdf_data_reg[255]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[25] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [25]),\n .Q(mc_app_wdf_data_reg[25]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[26] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [26]),\n .Q(mc_app_wdf_data_reg[26]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[27] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [27]),\n .Q(mc_app_wdf_data_reg[27]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[28] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [28]),\n .Q(mc_app_wdf_data_reg[28]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[29] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [29]),\n .Q(mc_app_wdf_data_reg[29]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[2] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [2]),\n .Q(mc_app_wdf_data_reg[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[30] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [30]),\n .Q(mc_app_wdf_data_reg[30]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[31] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [31]),\n .Q(mc_app_wdf_data_reg[31]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[32] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [32]),\n .Q(mc_app_wdf_data_reg[32]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[33] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [33]),\n .Q(mc_app_wdf_data_reg[33]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[34] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [34]),\n .Q(mc_app_wdf_data_reg[34]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[35] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [35]),\n .Q(mc_app_wdf_data_reg[35]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[36] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [36]),\n .Q(mc_app_wdf_data_reg[36]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[37] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [37]),\n .Q(mc_app_wdf_data_reg[37]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[38] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [38]),\n .Q(mc_app_wdf_data_reg[38]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[39] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [39]),\n .Q(mc_app_wdf_data_reg[39]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[3] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [3]),\n .Q(mc_app_wdf_data_reg[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[40] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [40]),\n .Q(mc_app_wdf_data_reg[40]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[41] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [41]),\n .Q(mc_app_wdf_data_reg[41]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[42] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [42]),\n .Q(mc_app_wdf_data_reg[42]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[43] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [43]),\n .Q(mc_app_wdf_data_reg[43]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[44] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [44]),\n .Q(mc_app_wdf_data_reg[44]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[45] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [45]),\n .Q(mc_app_wdf_data_reg[45]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[46] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [46]),\n .Q(mc_app_wdf_data_reg[46]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[47] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [47]),\n .Q(mc_app_wdf_data_reg[47]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[48] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [48]),\n .Q(mc_app_wdf_data_reg[48]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[49] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [49]),\n .Q(mc_app_wdf_data_reg[49]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[4] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [4]),\n .Q(mc_app_wdf_data_reg[4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[50] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [50]),\n .Q(mc_app_wdf_data_reg[50]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[51] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [51]),\n .Q(mc_app_wdf_data_reg[51]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[52] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [52]),\n .Q(mc_app_wdf_data_reg[52]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[53] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [53]),\n .Q(mc_app_wdf_data_reg[53]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[54] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [54]),\n .Q(mc_app_wdf_data_reg[54]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[55] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [55]),\n .Q(mc_app_wdf_data_reg[55]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[56] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [56]),\n .Q(mc_app_wdf_data_reg[56]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[57] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [57]),\n .Q(mc_app_wdf_data_reg[57]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[58] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [58]),\n .Q(mc_app_wdf_data_reg[58]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[59] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [59]),\n .Q(mc_app_wdf_data_reg[59]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[5] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [5]),\n .Q(mc_app_wdf_data_reg[5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[60] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [60]),\n .Q(mc_app_wdf_data_reg[60]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[61] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [61]),\n .Q(mc_app_wdf_data_reg[61]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[62] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [62]),\n .Q(mc_app_wdf_data_reg[62]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[63] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [63]),\n .Q(mc_app_wdf_data_reg[63]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[64] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [64]),\n .Q(mc_app_wdf_data_reg[64]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[65] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [65]),\n .Q(mc_app_wdf_data_reg[65]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[66] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [66]),\n .Q(mc_app_wdf_data_reg[66]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[67] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [67]),\n .Q(mc_app_wdf_data_reg[67]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[68] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [68]),\n .Q(mc_app_wdf_data_reg[68]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[69] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [69]),\n .Q(mc_app_wdf_data_reg[69]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[6] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [6]),\n .Q(mc_app_wdf_data_reg[6]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[70] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [70]),\n .Q(mc_app_wdf_data_reg[70]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[71] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [71]),\n .Q(mc_app_wdf_data_reg[71]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[72] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [72]),\n .Q(mc_app_wdf_data_reg[72]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[73] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [73]),\n .Q(mc_app_wdf_data_reg[73]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[74] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [74]),\n .Q(mc_app_wdf_data_reg[74]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[75] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [75]),\n .Q(mc_app_wdf_data_reg[75]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[76] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [76]),\n .Q(mc_app_wdf_data_reg[76]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[77] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [77]),\n .Q(mc_app_wdf_data_reg[77]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[78] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [78]),\n .Q(mc_app_wdf_data_reg[78]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[79] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [79]),\n .Q(mc_app_wdf_data_reg[79]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[7] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [7]),\n .Q(mc_app_wdf_data_reg[7]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[80] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [80]),\n .Q(mc_app_wdf_data_reg[80]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[81] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [81]),\n .Q(mc_app_wdf_data_reg[81]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[82] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [82]),\n .Q(mc_app_wdf_data_reg[82]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[83] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [83]),\n .Q(mc_app_wdf_data_reg[83]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[84] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [84]),\n .Q(mc_app_wdf_data_reg[84]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[85] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [85]),\n .Q(mc_app_wdf_data_reg[85]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[86] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [86]),\n .Q(mc_app_wdf_data_reg[86]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[87] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [87]),\n .Q(mc_app_wdf_data_reg[87]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[88] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [88]),\n .Q(mc_app_wdf_data_reg[88]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[89] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [89]),\n .Q(mc_app_wdf_data_reg[89]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[8] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [8]),\n .Q(mc_app_wdf_data_reg[8]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[90] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [90]),\n .Q(mc_app_wdf_data_reg[90]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[91] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [91]),\n .Q(mc_app_wdf_data_reg[91]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[92] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [92]),\n .Q(mc_app_wdf_data_reg[92]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[93] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [93]),\n .Q(mc_app_wdf_data_reg[93]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[94] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [94]),\n .Q(mc_app_wdf_data_reg[94]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[95] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [95]),\n .Q(mc_app_wdf_data_reg[95]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[96] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [96]),\n .Q(mc_app_wdf_data_reg[96]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[97] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [97]),\n .Q(mc_app_wdf_data_reg[97]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[98] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [98]),\n .Q(mc_app_wdf_data_reg[98]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[99] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [99]),\n .Q(mc_app_wdf_data_reg[99]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_data_reg_reg[9] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [9]),\n .Q(mc_app_wdf_data_reg[9]),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1420\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[0]_i_1 \n (.I0(s_axi_wstrb[0]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_mask[0]),\n .O(D[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1430\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[10]_i_1 \n (.I0(s_axi_wstrb[10]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[10]),\n .O(D[10]));\n (* SOFT_HLUTNM = \"soft_lutpair1431\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[11]_i_1 \n (.I0(s_axi_wstrb[11]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[11]),\n .O(D[11]));\n (* SOFT_HLUTNM = \"soft_lutpair1432\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[12]_i_1 \n (.I0(s_axi_wstrb[12]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[12]),\n .O(D[12]));\n (* SOFT_HLUTNM = \"soft_lutpair1433\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[13]_i_1 \n (.I0(s_axi_wstrb[13]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[13]),\n .O(D[13]));\n (* SOFT_HLUTNM = \"soft_lutpair1434\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[14]_i_1 \n (.I0(s_axi_wstrb[14]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[14]),\n .O(D[14]));\n (* SOFT_HLUTNM = \"soft_lutpair1435\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[15]_i_1 \n (.I0(s_axi_wstrb[15]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[15]),\n .O(D[15]));\n (* SOFT_HLUTNM = \"soft_lutpair1436\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[16]_i_1 \n (.I0(s_axi_wstrb[16]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[16]),\n .O(D[16]));\n (* SOFT_HLUTNM = \"soft_lutpair1437\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[17]_i_1 \n (.I0(s_axi_wstrb[17]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[17]),\n .O(D[17]));\n (* SOFT_HLUTNM = \"soft_lutpair1438\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[18]_i_1 \n (.I0(s_axi_wstrb[18]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[18]),\n .O(D[18]));\n (* SOFT_HLUTNM = \"soft_lutpair1439\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[19]_i_1 \n (.I0(s_axi_wstrb[19]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[19]),\n .O(D[19]));\n (* SOFT_HLUTNM = \"soft_lutpair1421\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[1]_i_1 \n (.I0(s_axi_wstrb[1]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_mask[1]),\n .O(D[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1440\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[20]_i_1 \n (.I0(s_axi_wstrb[20]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[20]),\n .O(D[20]));\n (* SOFT_HLUTNM = \"soft_lutpair1441\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[21]_i_1 \n (.I0(s_axi_wstrb[21]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[21]),\n .O(D[21]));\n (* SOFT_HLUTNM = \"soft_lutpair1442\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[22]_i_1 \n (.I0(s_axi_wstrb[22]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[22]),\n .O(D[22]));\n (* SOFT_HLUTNM = \"soft_lutpair1443\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[23]_i_1 \n (.I0(s_axi_wstrb[23]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[23]),\n .O(D[23]));\n (* SOFT_HLUTNM = \"soft_lutpair1444\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[24]_i_1 \n (.I0(s_axi_wstrb[24]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[24]),\n .O(D[24]));\n (* SOFT_HLUTNM = \"soft_lutpair1445\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[25]_i_1 \n (.I0(s_axi_wstrb[25]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[25]),\n .O(D[25]));\n (* SOFT_HLUTNM = \"soft_lutpair1446\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[26]_i_1 \n (.I0(s_axi_wstrb[26]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[26]),\n .O(D[26]));\n (* SOFT_HLUTNM = \"soft_lutpair1447\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[27]_i_1 \n (.I0(s_axi_wstrb[27]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[27]),\n .O(D[27]));\n (* SOFT_HLUTNM = \"soft_lutpair1448\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[28]_i_1 \n (.I0(s_axi_wstrb[28]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[28]),\n .O(D[28]));\n (* SOFT_HLUTNM = \"soft_lutpair1449\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[29]_i_1 \n (.I0(s_axi_wstrb[29]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[29]),\n .O(D[29]));\n (* SOFT_HLUTNM = \"soft_lutpair1422\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[2]_i_1 \n (.I0(s_axi_wstrb[2]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_mask[2]),\n .O(D[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1450\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[30]_i_1 \n (.I0(s_axi_wstrb[30]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[30]),\n .O(D[30]));\n (* SOFT_HLUTNM = \"soft_lutpair1451\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[31]_i_1 \n (.I0(s_axi_wstrb[31]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[31]),\n .O(D[31]));\n (* SOFT_HLUTNM = \"soft_lutpair1423\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[3]_i_1 \n (.I0(s_axi_wstrb[3]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_mask[3]),\n .O(D[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1424\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[4]_i_1 \n (.I0(s_axi_wstrb[4]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_mask[4]),\n .O(D[4]));\n (* SOFT_HLUTNM = \"soft_lutpair1425\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[5]_i_1 \n (.I0(s_axi_wstrb[5]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_mask[5]),\n .O(D[5]));\n (* SOFT_HLUTNM = \"soft_lutpair1426\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[6]_i_1 \n (.I0(s_axi_wstrb[6]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_mask[6]),\n .O(D[6]));\n (* SOFT_HLUTNM = \"soft_lutpair1427\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[7]_i_1 \n (.I0(s_axi_wstrb[7]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_mask[7]),\n .O(D[7]));\n (* SOFT_HLUTNM = \"soft_lutpair1428\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[8]_i_1 \n (.I0(s_axi_wstrb[8]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[8]),\n .O(D[8]));\n (* SOFT_HLUTNM = \"soft_lutpair1429\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[9]_i_1 \n (.I0(s_axi_wstrb[9]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[9]),\n .O(D[9]));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_mask_reg_reg[0] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[0]),\n .Q(mc_app_wdf_mask_reg[0]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_mask_reg_reg[10] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[10]),\n .Q(mc_app_wdf_mask_reg[10]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_mask_reg_reg[11] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[11]),\n .Q(mc_app_wdf_mask_reg[11]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_mask_reg_reg[12] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[12]),\n .Q(mc_app_wdf_mask_reg[12]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_mask_reg_reg[13] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[13]),\n .Q(mc_app_wdf_mask_reg[13]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_mask_reg_reg[14] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[14]),\n .Q(mc_app_wdf_mask_reg[14]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_mask_reg_reg[15] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[15]),\n .Q(mc_app_wdf_mask_reg[15]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_mask_reg_reg[16] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[16]),\n .Q(mc_app_wdf_mask_reg[16]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_mask_reg_reg[17] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[17]),\n .Q(mc_app_wdf_mask_reg[17]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_mask_reg_reg[18] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[18]),\n .Q(mc_app_wdf_mask_reg[18]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_mask_reg_reg[19] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[19]),\n .Q(mc_app_wdf_mask_reg[19]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_mask_reg_reg[1] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[1]),\n .Q(mc_app_wdf_mask_reg[1]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_mask_reg_reg[20] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[20]),\n .Q(mc_app_wdf_mask_reg[20]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_mask_reg_reg[21] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[21]),\n .Q(mc_app_wdf_mask_reg[21]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_mask_reg_reg[22] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[22]),\n .Q(mc_app_wdf_mask_reg[22]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_mask_reg_reg[23] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[23]),\n .Q(mc_app_wdf_mask_reg[23]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_mask_reg_reg[24] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[24]),\n .Q(mc_app_wdf_mask_reg[24]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_mask_reg_reg[25] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[25]),\n .Q(mc_app_wdf_mask_reg[25]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_mask_reg_reg[26] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[26]),\n .Q(mc_app_wdf_mask_reg[26]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_mask_reg_reg[27] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[27]),\n .Q(mc_app_wdf_mask_reg[27]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_mask_reg_reg[28] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[28]),\n .Q(mc_app_wdf_mask_reg[28]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_mask_reg_reg[29] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[29]),\n .Q(mc_app_wdf_mask_reg[29]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_mask_reg_reg[2] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[2]),\n .Q(mc_app_wdf_mask_reg[2]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_mask_reg_reg[30] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[30]),\n .Q(mc_app_wdf_mask_reg[30]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_mask_reg_reg[31] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[31]),\n .Q(mc_app_wdf_mask_reg[31]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_mask_reg_reg[3] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[3]),\n .Q(mc_app_wdf_mask_reg[3]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_mask_reg_reg[4] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[4]),\n .Q(mc_app_wdf_mask_reg[4]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_mask_reg_reg[5] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[5]),\n .Q(mc_app_wdf_mask_reg[5]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_mask_reg_reg[6] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[6]),\n .Q(mc_app_wdf_mask_reg[6]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_mask_reg_reg[7] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[7]),\n .Q(mc_app_wdf_mask_reg[7]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_mask_reg_reg[8] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[8]),\n .Q(mc_app_wdf_mask_reg[8]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\mc_app_wdf_mask_reg_reg[9] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[9]),\n .Q(mc_app_wdf_mask_reg[9]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n mc_app_wdf_wren_reg_reg\n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\RD_PRI_REG_STARVE.rnw_i_reg ),\n .Q(mc_app_wdf_wren_reg),\n .R(areset_d1));\n LUT3 #(\n .INIT(8'hB8)) \n valid_i_1\n (.I0(s_axi_wvalid),\n .I1(s_axi_wready),\n .I2(valid),\n .O(wvalid_int));\n FDRE #(\n .INIT(1'b0)) \n valid_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wvalid_int),\n .Q(valid),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [0]),\n .Q(wdf_data[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[100] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [100]),\n .Q(wdf_data[100]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[101] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [101]),\n .Q(wdf_data[101]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[102] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [102]),\n .Q(wdf_data[102]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[103] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [103]),\n .Q(wdf_data[103]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[104] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [104]),\n .Q(wdf_data[104]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[105] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [105]),\n .Q(wdf_data[105]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[106] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [106]),\n .Q(wdf_data[106]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[107] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [107]),\n .Q(wdf_data[107]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[108] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [108]),\n .Q(wdf_data[108]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[109] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [109]),\n .Q(wdf_data[109]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [10]),\n .Q(wdf_data[10]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[110] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [110]),\n .Q(wdf_data[110]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[111] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [111]),\n .Q(wdf_data[111]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[112] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [112]),\n .Q(wdf_data[112]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[113] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [113]),\n .Q(wdf_data[113]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[114] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [114]),\n .Q(wdf_data[114]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[115] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [115]),\n .Q(wdf_data[115]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[116] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [116]),\n .Q(wdf_data[116]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[117] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [117]),\n .Q(wdf_data[117]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[118] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [118]),\n .Q(wdf_data[118]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[119] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [119]),\n .Q(wdf_data[119]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [11]),\n .Q(wdf_data[11]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[120] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [120]),\n .Q(wdf_data[120]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[121] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [121]),\n .Q(wdf_data[121]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[122] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [122]),\n .Q(wdf_data[122]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[123] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [123]),\n .Q(wdf_data[123]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[124] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [124]),\n .Q(wdf_data[124]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[125] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [125]),\n .Q(wdf_data[125]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[126] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [126]),\n .Q(wdf_data[126]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[127] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [127]),\n .Q(wdf_data[127]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[128] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [128]),\n .Q(wdf_data[128]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[129] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [129]),\n .Q(wdf_data[129]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[12] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [12]),\n .Q(wdf_data[12]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[130] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [130]),\n .Q(wdf_data[130]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[131] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [131]),\n .Q(wdf_data[131]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[132] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [132]),\n .Q(wdf_data[132]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[133] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [133]),\n .Q(wdf_data[133]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[134] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [134]),\n .Q(wdf_data[134]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[135] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [135]),\n .Q(wdf_data[135]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[136] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [136]),\n .Q(wdf_data[136]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[137] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [137]),\n .Q(wdf_data[137]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[138] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [138]),\n .Q(wdf_data[138]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[139] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [139]),\n .Q(wdf_data[139]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[13] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [13]),\n .Q(wdf_data[13]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[140] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [140]),\n .Q(wdf_data[140]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[141] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [141]),\n .Q(wdf_data[141]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[142] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [142]),\n .Q(wdf_data[142]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[143] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [143]),\n .Q(wdf_data[143]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[144] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [144]),\n .Q(wdf_data[144]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[145] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [145]),\n .Q(wdf_data[145]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[146] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [146]),\n .Q(wdf_data[146]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[147] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [147]),\n .Q(wdf_data[147]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[148] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [148]),\n .Q(wdf_data[148]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[149] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [149]),\n .Q(wdf_data[149]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[14] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [14]),\n .Q(wdf_data[14]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[150] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [150]),\n .Q(wdf_data[150]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[151] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [151]),\n .Q(wdf_data[151]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[152] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [152]),\n .Q(wdf_data[152]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[153] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [153]),\n .Q(wdf_data[153]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[154] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [154]),\n .Q(wdf_data[154]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[155] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [155]),\n .Q(wdf_data[155]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[156] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [156]),\n .Q(wdf_data[156]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[157] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [157]),\n .Q(wdf_data[157]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[158] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [158]),\n .Q(wdf_data[158]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[159] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [159]),\n .Q(wdf_data[159]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[15] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [15]),\n .Q(wdf_data[15]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[160] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [160]),\n .Q(wdf_data[160]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[161] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [161]),\n .Q(wdf_data[161]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[162] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [162]),\n .Q(wdf_data[162]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[163] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [163]),\n .Q(wdf_data[163]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[164] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [164]),\n .Q(wdf_data[164]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[165] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [165]),\n .Q(wdf_data[165]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[166] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [166]),\n .Q(wdf_data[166]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[167] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [167]),\n .Q(wdf_data[167]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[168] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [168]),\n .Q(wdf_data[168]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[169] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [169]),\n .Q(wdf_data[169]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[16] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [16]),\n .Q(wdf_data[16]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[170] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [170]),\n .Q(wdf_data[170]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[171] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [171]),\n .Q(wdf_data[171]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[172] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [172]),\n .Q(wdf_data[172]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[173] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [173]),\n .Q(wdf_data[173]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[174] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [174]),\n .Q(wdf_data[174]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[175] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [175]),\n .Q(wdf_data[175]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[176] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [176]),\n .Q(wdf_data[176]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[177] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [177]),\n .Q(wdf_data[177]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[178] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [178]),\n .Q(wdf_data[178]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[179] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [179]),\n .Q(wdf_data[179]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[17] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [17]),\n .Q(wdf_data[17]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[180] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [180]),\n .Q(wdf_data[180]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[181] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [181]),\n .Q(wdf_data[181]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[182] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [182]),\n .Q(wdf_data[182]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[183] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [183]),\n .Q(wdf_data[183]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[184] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [184]),\n .Q(wdf_data[184]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[185] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [185]),\n .Q(wdf_data[185]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[186] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [186]),\n .Q(wdf_data[186]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[187] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [187]),\n .Q(wdf_data[187]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[188] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [188]),\n .Q(wdf_data[188]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[189] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [189]),\n .Q(wdf_data[189]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[18] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [18]),\n .Q(wdf_data[18]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[190] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [190]),\n .Q(wdf_data[190]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[191] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [191]),\n .Q(wdf_data[191]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[192] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [192]),\n .Q(wdf_data[192]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[193] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [193]),\n .Q(wdf_data[193]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[194] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [194]),\n .Q(wdf_data[194]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[195] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [195]),\n .Q(wdf_data[195]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[196] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [196]),\n .Q(wdf_data[196]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[197] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [197]),\n .Q(wdf_data[197]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[198] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [198]),\n .Q(wdf_data[198]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[199] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [199]),\n .Q(wdf_data[199]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[19] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [19]),\n .Q(wdf_data[19]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [1]),\n .Q(wdf_data[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[200] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [200]),\n .Q(wdf_data[200]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[201] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [201]),\n .Q(wdf_data[201]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[202] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [202]),\n .Q(wdf_data[202]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[203] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [203]),\n .Q(wdf_data[203]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[204] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [204]),\n .Q(wdf_data[204]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[205] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [205]),\n .Q(wdf_data[205]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[206] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [206]),\n .Q(wdf_data[206]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[207] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [207]),\n .Q(wdf_data[207]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[208] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [208]),\n .Q(wdf_data[208]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[209] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [209]),\n .Q(wdf_data[209]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[20] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [20]),\n .Q(wdf_data[20]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[210] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [210]),\n .Q(wdf_data[210]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[211] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [211]),\n .Q(wdf_data[211]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[212] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [212]),\n .Q(wdf_data[212]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[213] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [213]),\n .Q(wdf_data[213]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[214] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [214]),\n .Q(wdf_data[214]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[215] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [215]),\n .Q(wdf_data[215]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[216] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [216]),\n .Q(wdf_data[216]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[217] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [217]),\n .Q(wdf_data[217]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[218] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [218]),\n .Q(wdf_data[218]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[219] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [219]),\n .Q(wdf_data[219]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[21] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [21]),\n .Q(wdf_data[21]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[220] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [220]),\n .Q(wdf_data[220]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[221] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [221]),\n .Q(wdf_data[221]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[222] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [222]),\n .Q(wdf_data[222]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[223] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [223]),\n .Q(wdf_data[223]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[224] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [224]),\n .Q(wdf_data[224]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[225] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [225]),\n .Q(wdf_data[225]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[226] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [226]),\n .Q(wdf_data[226]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[227] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [227]),\n .Q(wdf_data[227]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[228] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [228]),\n .Q(wdf_data[228]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[229] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [229]),\n .Q(wdf_data[229]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[22] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [22]),\n .Q(wdf_data[22]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[230] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [230]),\n .Q(wdf_data[230]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[231] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [231]),\n .Q(wdf_data[231]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[232] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [232]),\n .Q(wdf_data[232]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[233] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [233]),\n .Q(wdf_data[233]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[234] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [234]),\n .Q(wdf_data[234]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[235] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [235]),\n .Q(wdf_data[235]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[236] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [236]),\n .Q(wdf_data[236]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[237] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [237]),\n .Q(wdf_data[237]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[238] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [238]),\n .Q(wdf_data[238]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[239] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [239]),\n .Q(wdf_data[239]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[23] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [23]),\n .Q(wdf_data[23]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[240] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [240]),\n .Q(wdf_data[240]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[241] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [241]),\n .Q(wdf_data[241]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[242] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [242]),\n .Q(wdf_data[242]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[243] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [243]),\n .Q(wdf_data[243]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[244] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [244]),\n .Q(wdf_data[244]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[245] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [245]),\n .Q(wdf_data[245]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[246] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [246]),\n .Q(wdf_data[246]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[247] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [247]),\n .Q(wdf_data[247]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[248] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [248]),\n .Q(wdf_data[248]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[249] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [249]),\n .Q(wdf_data[249]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[24] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [24]),\n .Q(wdf_data[24]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[250] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [250]),\n .Q(wdf_data[250]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[251] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [251]),\n .Q(wdf_data[251]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[252] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [252]),\n .Q(wdf_data[252]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[253] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [253]),\n .Q(wdf_data[253]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[254] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [254]),\n .Q(wdf_data[254]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[255] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [255]),\n .Q(wdf_data[255]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[25] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [25]),\n .Q(wdf_data[25]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[26] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [26]),\n .Q(wdf_data[26]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[27] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [27]),\n .Q(wdf_data[27]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[28] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [28]),\n .Q(wdf_data[28]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[29] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [29]),\n .Q(wdf_data[29]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [2]),\n .Q(wdf_data[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[30] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [30]),\n .Q(wdf_data[30]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[31] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [31]),\n .Q(wdf_data[31]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[32] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [32]),\n .Q(wdf_data[32]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[33] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [33]),\n .Q(wdf_data[33]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[34] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [34]),\n .Q(wdf_data[34]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[35] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [35]),\n .Q(wdf_data[35]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[36] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [36]),\n .Q(wdf_data[36]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[37] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [37]),\n .Q(wdf_data[37]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[38] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [38]),\n .Q(wdf_data[38]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[39] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [39]),\n .Q(wdf_data[39]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [3]),\n .Q(wdf_data[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[40] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [40]),\n .Q(wdf_data[40]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[41] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [41]),\n .Q(wdf_data[41]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[42] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [42]),\n .Q(wdf_data[42]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[43] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [43]),\n .Q(wdf_data[43]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[44] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [44]),\n .Q(wdf_data[44]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[45] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [45]),\n .Q(wdf_data[45]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[46] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [46]),\n .Q(wdf_data[46]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[47] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [47]),\n .Q(wdf_data[47]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[48] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [48]),\n .Q(wdf_data[48]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[49] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [49]),\n .Q(wdf_data[49]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [4]),\n .Q(wdf_data[4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[50] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [50]),\n .Q(wdf_data[50]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[51] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [51]),\n .Q(wdf_data[51]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[52] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [52]),\n .Q(wdf_data[52]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[53] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [53]),\n .Q(wdf_data[53]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[54] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [54]),\n .Q(wdf_data[54]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[55] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [55]),\n .Q(wdf_data[55]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[56] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [56]),\n .Q(wdf_data[56]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[57] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [57]),\n .Q(wdf_data[57]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[58] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [58]),\n .Q(wdf_data[58]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[59] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [59]),\n .Q(wdf_data[59]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [5]),\n .Q(wdf_data[5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[60] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [60]),\n .Q(wdf_data[60]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[61] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [61]),\n .Q(wdf_data[61]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[62] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [62]),\n .Q(wdf_data[62]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[63] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [63]),\n .Q(wdf_data[63]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[64] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [64]),\n .Q(wdf_data[64]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[65] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [65]),\n .Q(wdf_data[65]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[66] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [66]),\n .Q(wdf_data[66]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[67] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [67]),\n .Q(wdf_data[67]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[68] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [68]),\n .Q(wdf_data[68]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[69] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [69]),\n .Q(wdf_data[69]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [6]),\n .Q(wdf_data[6]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[70] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [70]),\n .Q(wdf_data[70]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[71] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [71]),\n .Q(wdf_data[71]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[72] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [72]),\n .Q(wdf_data[72]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[73] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [73]),\n .Q(wdf_data[73]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[74] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [74]),\n .Q(wdf_data[74]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[75] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [75]),\n .Q(wdf_data[75]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[76] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [76]),\n .Q(wdf_data[76]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[77] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [77]),\n .Q(wdf_data[77]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[78] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [78]),\n .Q(wdf_data[78]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[79] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [79]),\n .Q(wdf_data[79]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [7]),\n .Q(wdf_data[7]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[80] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [80]),\n .Q(wdf_data[80]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[81] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [81]),\n .Q(wdf_data[81]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[82] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [82]),\n .Q(wdf_data[82]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[83] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [83]),\n .Q(wdf_data[83]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[84] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [84]),\n .Q(wdf_data[84]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[85] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [85]),\n .Q(wdf_data[85]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[86] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [86]),\n .Q(wdf_data[86]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[87] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [87]),\n .Q(wdf_data[87]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[88] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [88]),\n .Q(wdf_data[88]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[89] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [89]),\n .Q(wdf_data[89]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [8]),\n .Q(wdf_data[8]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[90] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [90]),\n .Q(wdf_data[90]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[91] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [91]),\n .Q(wdf_data[91]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[92] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [92]),\n .Q(wdf_data[92]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[93] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [93]),\n .Q(wdf_data[93]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[94] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [94]),\n .Q(wdf_data[94]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[95] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [95]),\n .Q(wdf_data[95]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[96] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [96]),\n .Q(wdf_data[96]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[97] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [97]),\n .Q(wdf_data[97]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[98] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [98]),\n .Q(wdf_data[98]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[99] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [99]),\n .Q(wdf_data[99]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_data_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [9]),\n .Q(wdf_data[9]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_mask_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(D[0]),\n .Q(wdf_mask[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_mask_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(D[10]),\n .Q(wdf_mask[10]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_mask_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(D[11]),\n .Q(wdf_mask[11]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_mask_reg[12] \n (.C(CLK),\n .CE(1'b1),\n .D(D[12]),\n .Q(wdf_mask[12]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_mask_reg[13] \n (.C(CLK),\n .CE(1'b1),\n .D(D[13]),\n .Q(wdf_mask[13]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_mask_reg[14] \n (.C(CLK),\n .CE(1'b1),\n .D(D[14]),\n .Q(wdf_mask[14]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_mask_reg[15] \n (.C(CLK),\n .CE(1'b1),\n .D(D[15]),\n .Q(wdf_mask[15]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_mask_reg[16] \n (.C(CLK),\n .CE(1'b1),\n .D(D[16]),\n .Q(wdf_mask[16]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_mask_reg[17] \n (.C(CLK),\n .CE(1'b1),\n .D(D[17]),\n .Q(wdf_mask[17]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_mask_reg[18] \n (.C(CLK),\n .CE(1'b1),\n .D(D[18]),\n .Q(wdf_mask[18]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_mask_reg[19] \n (.C(CLK),\n .CE(1'b1),\n .D(D[19]),\n .Q(wdf_mask[19]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_mask_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(D[1]),\n .Q(wdf_mask[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_mask_reg[20] \n (.C(CLK),\n .CE(1'b1),\n .D(D[20]),\n .Q(wdf_mask[20]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_mask_reg[21] \n (.C(CLK),\n .CE(1'b1),\n .D(D[21]),\n .Q(wdf_mask[21]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_mask_reg[22] \n (.C(CLK),\n .CE(1'b1),\n .D(D[22]),\n .Q(wdf_mask[22]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_mask_reg[23] \n (.C(CLK),\n .CE(1'b1),\n .D(D[23]),\n .Q(wdf_mask[23]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_mask_reg[24] \n (.C(CLK),\n .CE(1'b1),\n .D(D[24]),\n .Q(wdf_mask[24]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_mask_reg[25] \n (.C(CLK),\n .CE(1'b1),\n .D(D[25]),\n .Q(wdf_mask[25]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_mask_reg[26] \n (.C(CLK),\n .CE(1'b1),\n .D(D[26]),\n .Q(wdf_mask[26]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_mask_reg[27] \n (.C(CLK),\n .CE(1'b1),\n .D(D[27]),\n .Q(wdf_mask[27]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_mask_reg[28] \n (.C(CLK),\n .CE(1'b1),\n .D(D[28]),\n .Q(wdf_mask[28]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_mask_reg[29] \n (.C(CLK),\n .CE(1'b1),\n .D(D[29]),\n .Q(wdf_mask[29]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_mask_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(D[2]),\n .Q(wdf_mask[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_mask_reg[30] \n (.C(CLK),\n .CE(1'b1),\n .D(D[30]),\n .Q(wdf_mask[30]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_mask_reg[31] \n (.C(CLK),\n .CE(1'b1),\n .D(D[31]),\n .Q(wdf_mask[31]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_mask_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(D[3]),\n .Q(wdf_mask[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_mask_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(D[4]),\n .Q(wdf_mask[4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_mask_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(D[5]),\n .Q(wdf_mask[5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_mask_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(D[6]),\n .Q(wdf_mask[6]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_mask_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(D[7]),\n .Q(wdf_mask[7]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_mask_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(D[8]),\n .Q(wdf_mask[8]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wdf_mask_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(D[9]),\n .Q(wdf_mask[9]),\n .R(1'b0));\n LUT4 #(\n .INIT(16'hABFB)) \n wready_i_1\n (.I0(\\RD_PRI_REG_STARVE.rnw_i_reg ),\n .I1(valid),\n .I2(s_axi_wready),\n .I3(s_axi_wvalid),\n .O(wready_i_1_n_0));\n (* ORIG_CELL_NAME = \"wready_reg\" *) \n FDRE #(\n .INIT(1'b0)) \n wready_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wready_i_1_n_0),\n .Q(s_axi_wready),\n .R(areset_d1));\n (* ORIG_CELL_NAME = \"wready_reg\" *) \n FDRE #(\n .INIT(1'b0)) \n wready_reg_rep\n (.C(CLK),\n .CE(1'b1),\n .D(wready_rep_i_1_n_0),\n .Q(wready_reg_rep_n_0),\n .R(areset_d1));\n (* ORIG_CELL_NAME = \"wready_reg\" *) \n FDRE #(\n .INIT(1'b0)) \n wready_reg_rep__0\n (.C(CLK),\n .CE(1'b1),\n .D(wready_rep__0_i_1_n_0),\n .Q(wready_reg_rep__0_n_0),\n .R(areset_d1));\n (* ORIG_CELL_NAME = \"wready_reg\" *) \n FDRE #(\n .INIT(1'b0)) \n wready_reg_rep__1\n (.C(CLK),\n .CE(1'b1),\n .D(wready_rep__1_i_1_n_0),\n .Q(wready_reg_rep__1_n_0),\n .R(areset_d1));\n (* ORIG_CELL_NAME = \"wready_reg\" *) \n FDRE #(\n .INIT(1'b0)) \n wready_reg_rep__2\n (.C(CLK),\n .CE(1'b1),\n .D(wready_rep__2_i_1_n_0),\n .Q(wready_reg_rep__2_n_0),\n .R(areset_d1));\n LUT4 #(\n .INIT(16'hABFB)) \n wready_rep__0_i_1\n (.I0(\\RD_PRI_REG_STARVE.rnw_i_reg ),\n .I1(valid),\n .I2(s_axi_wready),\n .I3(s_axi_wvalid),\n .O(wready_rep__0_i_1_n_0));\n LUT4 #(\n .INIT(16'hABFB)) \n wready_rep__1_i_1\n (.I0(\\RD_PRI_REG_STARVE.rnw_i_reg ),\n .I1(valid),\n .I2(s_axi_wready),\n .I3(s_axi_wvalid),\n .O(wready_rep__1_i_1_n_0));\n LUT4 #(\n .INIT(16'hABFB)) \n wready_rep__2_i_1\n (.I0(\\RD_PRI_REG_STARVE.rnw_i_reg ),\n .I1(valid),\n .I2(s_axi_wready),\n .I3(s_axi_wvalid),\n .O(wready_rep__2_i_1_n_0));\n LUT4 #(\n .INIT(16'hABFB)) \n wready_rep_i_1\n (.I0(\\RD_PRI_REG_STARVE.rnw_i_reg ),\n .I1(valid),\n .I2(s_axi_wready),\n .I3(s_axi_wvalid),\n .O(wready_rep_i_1_n_0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_axi_mc_wr_cmd_fsm\" *) \nmodule ddr3_ifmig_7series_v4_0_axi_mc_wr_cmd_fsm\n (s_axi_awready,\n axlen_int,\n D,\n b_push,\n \\axburst_reg[1] ,\n \\axlen_reg[7] ,\n in0,\n \\axaddr_incr_reg[29] ,\n \\app_addr_r1_reg[4] ,\n \\axaddr_reg[29] ,\n \\app_addr_r1_reg[5] ,\n \\app_addr_r1_reg[6] ,\n \\app_addr_r1_reg[7] ,\n \\app_addr_r1_reg[8] ,\n \\app_addr_r1_reg[9] ,\n \\app_addr_r1_reg[10] ,\n \\app_addr_r1_reg[11] ,\n \\app_addr_r1_reg[12] ,\n \\app_addr_r1_reg[13] ,\n \\app_addr_r1_reg[14] ,\n \\app_addr_r1_reg[15] ,\n \\app_addr_r1_reg[16] ,\n \\app_addr_r1_reg[17] ,\n \\app_addr_r1_reg[18] ,\n \\app_addr_r1_reg[19] ,\n \\app_addr_r1_reg[20] ,\n \\app_addr_r1_reg[21] ,\n \\app_addr_r1_reg[22] ,\n \\app_addr_r1_reg[23] ,\n \\app_addr_r1_reg[24] ,\n \\app_addr_r1_reg[25] ,\n \\app_addr_r1_reg[26] ,\n \\app_addr_r1_reg[27] ,\n S,\n \\app_addr_r1_reg[3] ,\n \\axaddr_incr_reg[29]_0 ,\n \\int_addr_reg[3] ,\n \\axlen_cnt_reg[3] ,\n awvalid_int,\n b_awid,\n E,\n \\axlen_cnt_reg[0] ,\n \\axaddr_incr_reg[11] ,\n areset_d1,\n CLK,\n Q,\n axready_reg_0,\n \\axlen_reg[7]_0 ,\n s_axi_awlen,\n axvalid,\n s_axi_awvalid,\n \\RD_PRI_REG_STARVE.rnw_i_reg ,\n s_axi_awaddr,\n \\axaddr_reg[29]_0 ,\n \\axaddr_incr_reg[29]_1 ,\n \\int_addr_reg[3]_0 ,\n out,\n axready_reg_1,\n \\int_addr_reg[3]_1 ,\n \\axlen_cnt_reg[3]_0 ,\n axburst,\n s_axi_awburst,\n \\RD_PRI_REG_STARVE.rnw_i_reg_0 ,\n s_axi_awid,\n axid);\n output s_axi_awready;\n output [3:0]axlen_int;\n output [7:0]D;\n output b_push;\n output \\axburst_reg[1] ;\n output [3:0]\\axlen_reg[7] ;\n output [3:0]in0;\n output [24:0]\\axaddr_incr_reg[29] ;\n output \\app_addr_r1_reg[4] ;\n output [29:0]\\axaddr_reg[29] ;\n output \\app_addr_r1_reg[5] ;\n output [0:0]\\app_addr_r1_reg[6] ;\n output \\app_addr_r1_reg[7] ;\n output \\app_addr_r1_reg[8] ;\n output \\app_addr_r1_reg[9] ;\n output \\app_addr_r1_reg[10] ;\n output \\app_addr_r1_reg[11] ;\n output \\app_addr_r1_reg[12] ;\n output \\app_addr_r1_reg[13] ;\n output \\app_addr_r1_reg[14] ;\n output \\app_addr_r1_reg[15] ;\n output \\app_addr_r1_reg[16] ;\n output \\app_addr_r1_reg[17] ;\n output \\app_addr_r1_reg[18] ;\n output \\app_addr_r1_reg[19] ;\n output \\app_addr_r1_reg[20] ;\n output \\app_addr_r1_reg[21] ;\n output \\app_addr_r1_reg[22] ;\n output \\app_addr_r1_reg[23] ;\n output \\app_addr_r1_reg[24] ;\n output \\app_addr_r1_reg[25] ;\n output \\app_addr_r1_reg[26] ;\n output \\app_addr_r1_reg[27] ;\n output [0:0]S;\n output \\app_addr_r1_reg[3] ;\n output [29:0]\\axaddr_incr_reg[29]_0 ;\n output [3:0]\\int_addr_reg[3] ;\n output [3:0]\\axlen_cnt_reg[3] ;\n output awvalid_int;\n output b_awid;\n output [0:0]E;\n output [0:0]\\axlen_cnt_reg[0] ;\n output [0:0]\\axaddr_incr_reg[11] ;\n input areset_d1;\n input CLK;\n input [7:0]Q;\n input axready_reg_0;\n input [7:0]\\axlen_reg[7]_0 ;\n input [7:0]s_axi_awlen;\n input axvalid;\n input s_axi_awvalid;\n input \\RD_PRI_REG_STARVE.rnw_i_reg ;\n input [29:0]s_axi_awaddr;\n input [29:0]\\axaddr_reg[29]_0 ;\n input [29:0]\\axaddr_incr_reg[29]_1 ;\n input \\int_addr_reg[3]_0 ;\n input [29:0]out;\n input axready_reg_1;\n input [3:0]\\int_addr_reg[3]_1 ;\n input [3:0]\\axlen_cnt_reg[3]_0 ;\n input [0:0]axburst;\n input [0:0]s_axi_awburst;\n input \\RD_PRI_REG_STARVE.rnw_i_reg_0 ;\n input [0:0]s_axi_awid;\n input axid;\n\n wire CLK;\n wire [7:0]D;\n wire [0:0]E;\n wire [7:0]Q;\n wire \\RD_PRI_REG_STARVE.rnw_i_reg ;\n wire \\RD_PRI_REG_STARVE.rnw_i_reg_0 ;\n wire [0:0]S;\n wire \\app_addr_r1[6]_i_3_n_0 ;\n wire \\app_addr_r1[6]_i_5_n_0 ;\n wire \\app_addr_r1_reg[10] ;\n wire \\app_addr_r1_reg[11] ;\n wire \\app_addr_r1_reg[12] ;\n wire \\app_addr_r1_reg[13] ;\n wire \\app_addr_r1_reg[14] ;\n wire \\app_addr_r1_reg[15] ;\n wire \\app_addr_r1_reg[16] ;\n wire \\app_addr_r1_reg[17] ;\n wire \\app_addr_r1_reg[18] ;\n wire \\app_addr_r1_reg[19] ;\n wire \\app_addr_r1_reg[20] ;\n wire \\app_addr_r1_reg[21] ;\n wire \\app_addr_r1_reg[22] ;\n wire \\app_addr_r1_reg[23] ;\n wire \\app_addr_r1_reg[24] ;\n wire \\app_addr_r1_reg[25] ;\n wire \\app_addr_r1_reg[26] ;\n wire \\app_addr_r1_reg[27] ;\n wire \\app_addr_r1_reg[3] ;\n wire \\app_addr_r1_reg[4] ;\n wire \\app_addr_r1_reg[5] ;\n wire [0:0]\\app_addr_r1_reg[6] ;\n wire \\app_addr_r1_reg[7] ;\n wire \\app_addr_r1_reg[8] ;\n wire \\app_addr_r1_reg[9] ;\n wire areset_d1;\n wire awvalid_int;\n wire [0:0]\\axaddr_incr_reg[11] ;\n wire [24:0]\\axaddr_incr_reg[29] ;\n wire [29:0]\\axaddr_incr_reg[29]_0 ;\n wire [29:0]\\axaddr_incr_reg[29]_1 ;\n wire [29:0]\\axaddr_reg[29] ;\n wire [29:0]\\axaddr_reg[29]_0 ;\n wire [0:0]axburst;\n wire \\axburst_reg[1] ;\n wire [8:5]\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr ;\n wire \\axi_mc_cmd_translator_0/incr_axhandshake ;\n wire \\axi_mc_cmd_translator_0/wrap_axhandshake ;\n wire [8:8]axi_mc_incr_cmd_byte_addr__0;\n wire axid;\n wire \\axlen_cnt[2]_i_2__0_n_0 ;\n wire \\axlen_cnt[2]_i_2_n_0 ;\n wire \\axlen_cnt[3]_i_2__0_n_0 ;\n wire \\axlen_cnt[3]_i_2_n_0 ;\n wire \\axlen_cnt[4]_i_2_n_0 ;\n wire \\axlen_cnt[4]_i_3_n_0 ;\n wire \\axlen_cnt[5]_i_2_n_0 ;\n wire \\axlen_cnt[5]_i_3_n_0 ;\n wire \\axlen_cnt[7]_i_3_n_0 ;\n wire \\axlen_cnt[7]_i_4_n_0 ;\n wire [0:0]\\axlen_cnt_reg[0] ;\n wire [3:0]\\axlen_cnt_reg[3] ;\n wire [3:0]\\axlen_cnt_reg[3]_0 ;\n wire [3:0]axlen_int;\n wire [3:0]\\axlen_reg[7] ;\n wire [7:0]\\axlen_reg[7]_0 ;\n wire axready_i_1_n_0;\n wire axready_reg_0;\n wire axready_reg_1;\n wire axvalid;\n wire b_awid;\n wire b_push;\n wire [3:0]in0;\n wire \\int_addr[3]_i_5_n_0 ;\n wire [3:0]\\int_addr_reg[3] ;\n wire \\int_addr_reg[3]_0 ;\n wire [3:0]\\int_addr_reg[3]_1 ;\n wire \\memory_reg[7][0]_srl8_i_2_n_0 ;\n wire \\memory_reg[7][0]_srl8_i_3_n_0 ;\n wire \\memory_reg[7][0]_srl8_i_4_n_0 ;\n wire \\memory_reg[7][0]_srl8_i_5_n_0 ;\n wire [29:0]out;\n wire [29:0]s_axi_awaddr;\n wire [0:0]s_axi_awburst;\n wire [0:0]s_axi_awid;\n wire [7:0]s_axi_awlen;\n wire s_axi_awready;\n wire s_axi_awvalid;\n\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[10]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [12]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [12]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[10] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[11]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [13]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [13]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[11] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[12]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [14]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [14]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[12] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[13]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [15]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [15]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[13] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[14]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [16]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [16]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[14] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[15]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [17]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [17]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[15] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[16]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [18]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [18]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[16] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[17]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [19]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [19]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[17] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[18]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [20]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [20]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[18] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[19]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [21]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [21]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[19] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[20]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [22]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [22]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[20] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[21]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [23]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [23]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[21] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[22]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [24]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [24]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[22] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[23]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [25]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [25]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[23] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[24]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [26]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [26]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[24] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[25]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [27]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [27]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[25] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[26]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [28]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [28]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[26] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[27]_i_5 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [29]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [29]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[27] ));\n LUT6 #(\n .INIT(64'hF8FFF88888888888)) \n \\app_addr_r1[3]_i_3 \n (.I0(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]),\n .I1(\\app_addr_r1[6]_i_5_n_0 ),\n .I2(\\axaddr_reg[29] [5]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [5]),\n .I5(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[3] ));\n LUT6 #(\n .INIT(64'hF8FFF88888888888)) \n \\app_addr_r1[4]_i_4 \n (.I0(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [6]),\n .I1(\\app_addr_r1[6]_i_5_n_0 ),\n .I2(\\axaddr_reg[29] [6]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [6]),\n .I5(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[4] ));\n (* SOFT_HLUTNM = \"soft_lutpair1130\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_addr_r1[4]_i_5 \n (.I0(s_axi_awaddr[6]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [6]),\n .I3(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I4(\\int_addr_reg[3]_1 [1]),\n .O(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [6]));\n LUT6 #(\n .INIT(64'hF8FFF88888888888)) \n \\app_addr_r1[5]_i_3 \n (.I0(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [7]),\n .I1(\\app_addr_r1[6]_i_5_n_0 ),\n .I2(\\axaddr_reg[29] [7]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [7]),\n .I5(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[5] ));\n LUT5 #(\n .INIT(32'hFFEAEAEA)) \n \\app_addr_r1[6]_i_1 \n (.I0(\\int_addr_reg[3]_0 ),\n .I1(\\app_addr_r1[6]_i_3_n_0 ),\n .I2(axi_mc_incr_cmd_byte_addr__0),\n .I3(\\app_addr_r1[6]_i_5_n_0 ),\n .I4(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [8]),\n .O(\\app_addr_r1_reg[6] ));\n (* SOFT_HLUTNM = \"soft_lutpair1136\" *) \n LUT4 #(\n .INIT(16'h001D)) \n \\app_addr_r1[6]_i_3 \n (.I0(axburst),\n .I1(s_axi_awready),\n .I2(s_axi_awburst),\n .I3(\\RD_PRI_REG_STARVE.rnw_i_reg_0 ),\n .O(\\app_addr_r1[6]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_addr_r1[6]_i_4 \n (.I0(s_axi_awaddr[8]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [8]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [8]),\n .O(axi_mc_incr_cmd_byte_addr__0));\n (* SOFT_HLUTNM = \"soft_lutpair1136\" *) \n LUT4 #(\n .INIT(16'h00E2)) \n \\app_addr_r1[6]_i_5 \n (.I0(axburst),\n .I1(s_axi_awready),\n .I2(s_axi_awburst),\n .I3(\\RD_PRI_REG_STARVE.rnw_i_reg_0 ),\n .O(\\app_addr_r1[6]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[7]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [9]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [9]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[7] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[8]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [10]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [10]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[8] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[9]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [11]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [11]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[9] ));\n (* SOFT_HLUTNM = \"soft_lutpair1132\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[0]_i_1 \n (.I0(s_axi_awaddr[0]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [0]),\n .O(\\axaddr_reg[29] [0]));\n (* SOFT_HLUTNM = \"soft_lutpair1147\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[10]_i_1 \n (.I0(s_axi_awaddr[10]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [10]),\n .O(\\axaddr_reg[29] [10]));\n (* SOFT_HLUTNM = \"soft_lutpair1147\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[11]_i_1 \n (.I0(s_axi_awaddr[11]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [11]),\n .O(\\axaddr_reg[29] [11]));\n (* SOFT_HLUTNM = \"soft_lutpair1146\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[12]_i_1 \n (.I0(s_axi_awaddr[12]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [12]),\n .O(\\axaddr_reg[29] [12]));\n (* SOFT_HLUTNM = \"soft_lutpair1146\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[13]_i_1 \n (.I0(s_axi_awaddr[13]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [13]),\n .O(\\axaddr_reg[29] [13]));\n (* SOFT_HLUTNM = \"soft_lutpair1145\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[14]_i_1 \n (.I0(s_axi_awaddr[14]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [14]),\n .O(\\axaddr_reg[29] [14]));\n (* SOFT_HLUTNM = \"soft_lutpair1145\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[15]_i_1 \n (.I0(s_axi_awaddr[15]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [15]),\n .O(\\axaddr_reg[29] [15]));\n (* SOFT_HLUTNM = \"soft_lutpair1144\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[16]_i_1 \n (.I0(s_axi_awaddr[16]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [16]),\n .O(\\axaddr_reg[29] [16]));\n (* SOFT_HLUTNM = \"soft_lutpair1144\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[17]_i_1 \n (.I0(s_axi_awaddr[17]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [17]),\n .O(\\axaddr_reg[29] [17]));\n (* SOFT_HLUTNM = \"soft_lutpair1143\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[18]_i_1 \n (.I0(s_axi_awaddr[18]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [18]),\n .O(\\axaddr_reg[29] [18]));\n (* SOFT_HLUTNM = \"soft_lutpair1143\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[19]_i_1 \n (.I0(s_axi_awaddr[19]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [19]),\n .O(\\axaddr_reg[29] [19]));\n (* SOFT_HLUTNM = \"soft_lutpair1133\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[1]_i_1 \n (.I0(s_axi_awaddr[1]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [1]),\n .O(\\axaddr_reg[29] [1]));\n (* SOFT_HLUTNM = \"soft_lutpair1142\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[20]_i_1 \n (.I0(s_axi_awaddr[20]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [20]),\n .O(\\axaddr_reg[29] [20]));\n (* SOFT_HLUTNM = \"soft_lutpair1142\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[21]_i_1 \n (.I0(s_axi_awaddr[21]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [21]),\n .O(\\axaddr_reg[29] [21]));\n (* SOFT_HLUTNM = \"soft_lutpair1141\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[22]_i_1 \n (.I0(s_axi_awaddr[22]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [22]),\n .O(\\axaddr_reg[29] [22]));\n (* SOFT_HLUTNM = \"soft_lutpair1141\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[23]_i_1 \n (.I0(s_axi_awaddr[23]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [23]),\n .O(\\axaddr_reg[29] [23]));\n (* SOFT_HLUTNM = \"soft_lutpair1140\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[24]_i_1 \n (.I0(s_axi_awaddr[24]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [24]),\n .O(\\axaddr_reg[29] [24]));\n (* SOFT_HLUTNM = \"soft_lutpair1140\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[25]_i_1 \n (.I0(s_axi_awaddr[25]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [25]),\n .O(\\axaddr_reg[29] [25]));\n (* SOFT_HLUTNM = \"soft_lutpair1139\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[26]_i_1 \n (.I0(s_axi_awaddr[26]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [26]),\n .O(\\axaddr_reg[29] [26]));\n (* SOFT_HLUTNM = \"soft_lutpair1139\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[27]_i_1 \n (.I0(s_axi_awaddr[27]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [27]),\n .O(\\axaddr_reg[29] [27]));\n (* SOFT_HLUTNM = \"soft_lutpair1138\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[28]_i_1 \n (.I0(s_axi_awaddr[28]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [28]),\n .O(\\axaddr_reg[29] [28]));\n (* SOFT_HLUTNM = \"soft_lutpair1138\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[29]_i_1 \n (.I0(s_axi_awaddr[29]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [29]),\n .O(\\axaddr_reg[29] [29]));\n (* SOFT_HLUTNM = \"soft_lutpair1134\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[2]_i_1 \n (.I0(s_axi_awaddr[2]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [2]),\n .O(\\axaddr_reg[29] [2]));\n (* SOFT_HLUTNM = \"soft_lutpair1135\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[3]_i_1 \n (.I0(s_axi_awaddr[3]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [3]),\n .O(\\axaddr_reg[29] [3]));\n (* SOFT_HLUTNM = \"soft_lutpair1149\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[4]_i_1 \n (.I0(s_axi_awaddr[4]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [4]),\n .O(\\axaddr_reg[29] [4]));\n (* SOFT_HLUTNM = \"soft_lutpair1131\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[5]_i_1 \n (.I0(s_axi_awaddr[5]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [5]),\n .O(\\axaddr_reg[29] [5]));\n (* SOFT_HLUTNM = \"soft_lutpair1130\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[6]_i_1 \n (.I0(s_axi_awaddr[6]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [6]),\n .O(\\axaddr_reg[29] [6]));\n (* SOFT_HLUTNM = \"soft_lutpair1129\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[7]_i_1 \n (.I0(s_axi_awaddr[7]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [7]),\n .O(\\axaddr_reg[29] [7]));\n (* SOFT_HLUTNM = \"soft_lutpair1128\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[8]_i_1 \n (.I0(s_axi_awaddr[8]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [8]),\n .O(\\axaddr_reg[29] [8]));\n (* SOFT_HLUTNM = \"soft_lutpair1148\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[9]_i_1 \n (.I0(s_axi_awaddr[9]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [9]),\n .O(\\axaddr_reg[29] [9]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[0]_i_1 \n (.I0(s_axi_awaddr[0]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [0]),\n .I3(axready_reg_0),\n .I4(out[0]),\n .O(\\axaddr_incr_reg[29]_0 [0]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[10]_i_1 \n (.I0(s_axi_awaddr[10]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [10]),\n .I3(axready_reg_0),\n .I4(out[10]),\n .O(\\axaddr_incr_reg[29]_0 [10]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[11]_i_1 \n (.I0(s_axi_awaddr[11]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [11]),\n .I3(axready_reg_0),\n .I4(out[11]),\n .O(\\axaddr_incr_reg[29]_0 [11]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[12]_i_1 \n (.I0(s_axi_awaddr[12]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [12]),\n .I3(axready_reg_0),\n .I4(out[12]),\n .O(\\axaddr_incr_reg[29]_0 [12]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[13]_i_1 \n (.I0(s_axi_awaddr[13]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [13]),\n .I3(axready_reg_0),\n .I4(out[13]),\n .O(\\axaddr_incr_reg[29]_0 [13]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[14]_i_1 \n (.I0(s_axi_awaddr[14]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [14]),\n .I3(axready_reg_0),\n .I4(out[14]),\n .O(\\axaddr_incr_reg[29]_0 [14]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[15]_i_1 \n (.I0(s_axi_awaddr[15]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [15]),\n .I3(axready_reg_0),\n .I4(out[15]),\n .O(\\axaddr_incr_reg[29]_0 [15]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[16]_i_1 \n (.I0(s_axi_awaddr[16]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [16]),\n .I3(axready_reg_0),\n .I4(out[16]),\n .O(\\axaddr_incr_reg[29]_0 [16]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[17]_i_1 \n (.I0(s_axi_awaddr[17]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [17]),\n .I3(axready_reg_0),\n .I4(out[17]),\n .O(\\axaddr_incr_reg[29]_0 [17]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[18]_i_1 \n (.I0(s_axi_awaddr[18]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [18]),\n .I3(axready_reg_0),\n .I4(out[18]),\n .O(\\axaddr_incr_reg[29]_0 [18]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[19]_i_1 \n (.I0(s_axi_awaddr[19]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [19]),\n .I3(axready_reg_0),\n .I4(out[19]),\n .O(\\axaddr_incr_reg[29]_0 [19]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[1]_i_1 \n (.I0(s_axi_awaddr[1]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [1]),\n .I3(axready_reg_0),\n .I4(out[1]),\n .O(\\axaddr_incr_reg[29]_0 [1]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[20]_i_1 \n (.I0(s_axi_awaddr[20]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [20]),\n .I3(axready_reg_0),\n .I4(out[20]),\n .O(\\axaddr_incr_reg[29]_0 [20]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[21]_i_1 \n (.I0(s_axi_awaddr[21]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [21]),\n .I3(axready_reg_0),\n .I4(out[21]),\n .O(\\axaddr_incr_reg[29]_0 [21]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[22]_i_1 \n (.I0(s_axi_awaddr[22]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [22]),\n .I3(axready_reg_0),\n .I4(out[22]),\n .O(\\axaddr_incr_reg[29]_0 [22]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[23]_i_1 \n (.I0(s_axi_awaddr[23]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [23]),\n .I3(axready_reg_0),\n .I4(out[23]),\n .O(\\axaddr_incr_reg[29]_0 [23]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[24]_i_1 \n (.I0(s_axi_awaddr[24]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [24]),\n .I3(axready_reg_0),\n .I4(out[24]),\n .O(\\axaddr_incr_reg[29]_0 [24]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[25]_i_1 \n (.I0(s_axi_awaddr[25]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [25]),\n .I3(axready_reg_0),\n .I4(out[25]),\n .O(\\axaddr_incr_reg[29]_0 [25]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[26]_i_1 \n (.I0(s_axi_awaddr[26]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [26]),\n .I3(axready_reg_0),\n .I4(out[26]),\n .O(\\axaddr_incr_reg[29]_0 [26]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[27]_i_1 \n (.I0(s_axi_awaddr[27]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [27]),\n .I3(axready_reg_0),\n .I4(out[27]),\n .O(\\axaddr_incr_reg[29]_0 [27]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[28]_i_1 \n (.I0(s_axi_awaddr[28]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [28]),\n .I3(axready_reg_0),\n .I4(out[28]),\n .O(\\axaddr_incr_reg[29]_0 [28]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[29]_i_1 \n (.I0(s_axi_awaddr[29]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [29]),\n .I3(axready_reg_0),\n .I4(out[29]),\n .O(\\axaddr_incr_reg[29]_0 [29]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[2]_i_1 \n (.I0(s_axi_awaddr[2]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [2]),\n .I3(axready_reg_0),\n .I4(out[2]),\n .O(\\axaddr_incr_reg[29]_0 [2]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[3]_i_1 \n (.I0(s_axi_awaddr[3]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [3]),\n .I3(axready_reg_0),\n .I4(out[3]),\n .O(\\axaddr_incr_reg[29]_0 [3]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[4]_i_1 \n (.I0(s_axi_awaddr[4]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [4]),\n .I3(axready_reg_0),\n .I4(out[4]),\n .O(\\axaddr_incr_reg[29]_0 [4]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[5]_i_1 \n (.I0(s_axi_awaddr[5]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [5]),\n .I3(axready_reg_0),\n .I4(out[5]),\n .O(\\axaddr_incr_reg[29]_0 [5]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[6]_i_1 \n (.I0(s_axi_awaddr[6]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [6]),\n .I3(axready_reg_0),\n .I4(out[6]),\n .O(\\axaddr_incr_reg[29]_0 [6]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[7]_i_1 \n (.I0(s_axi_awaddr[7]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [7]),\n .I3(axready_reg_0),\n .I4(out[7]),\n .O(\\axaddr_incr_reg[29]_0 [7]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[8]_i_1 \n (.I0(s_axi_awaddr[8]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [8]),\n .I3(axready_reg_0),\n .I4(out[8]),\n .O(\\axaddr_incr_reg[29]_0 [8]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[9]_i_1 \n (.I0(s_axi_awaddr[9]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [9]),\n .I3(axready_reg_0),\n .I4(out[9]),\n .O(\\axaddr_incr_reg[29]_0 [9]));\n (* SOFT_HLUTNM = \"soft_lutpair1135\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_inferred_i_1\n (.I0(s_axi_awaddr[3]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [3]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [3]),\n .O(in0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1134\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_inferred_i_2\n (.I0(s_axi_awaddr[2]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [2]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [2]),\n .O(in0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1133\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_inferred_i_3\n (.I0(s_axi_awaddr[1]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [1]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [1]),\n .O(in0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1132\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_inferred_i_4\n (.I0(s_axi_awaddr[0]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [0]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [0]),\n .O(in0[0]));\n LUT3 #(\n .INIT(8'h08)) \n axaddr_incr_p_inferred_i_5\n (.I0(s_axi_awvalid),\n .I1(s_axi_awready),\n .I2(s_axi_awburst),\n .O(\\axi_mc_cmd_translator_0/incr_axhandshake ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__0_i_1\n (.I0(s_axi_awaddr[11]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [11]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [11]),\n .O(\\axaddr_incr_reg[29] [6]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__0_i_2\n (.I0(s_axi_awaddr[10]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [10]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [10]),\n .O(\\axaddr_incr_reg[29] [5]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__0_i_3\n (.I0(s_axi_awaddr[9]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [9]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [9]),\n .O(\\axaddr_incr_reg[29] [4]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__0_i_4__0\n (.I0(s_axi_awaddr[8]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [8]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [8]),\n .O(\\axaddr_incr_reg[11] ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__1_i_1\n (.I0(s_axi_awaddr[15]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [15]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [15]),\n .O(\\axaddr_incr_reg[29] [10]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__1_i_2\n (.I0(s_axi_awaddr[14]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [14]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [14]),\n .O(\\axaddr_incr_reg[29] [9]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__1_i_3\n (.I0(s_axi_awaddr[13]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [13]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [13]),\n .O(\\axaddr_incr_reg[29] [8]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__1_i_4\n (.I0(s_axi_awaddr[12]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [12]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [12]),\n .O(\\axaddr_incr_reg[29] [7]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__2_i_1\n (.I0(s_axi_awaddr[19]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [19]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [19]),\n .O(\\axaddr_incr_reg[29] [14]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__2_i_2\n (.I0(s_axi_awaddr[18]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [18]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [18]),\n .O(\\axaddr_incr_reg[29] [13]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__2_i_3\n (.I0(s_axi_awaddr[17]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [17]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [17]),\n .O(\\axaddr_incr_reg[29] [12]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__2_i_4\n (.I0(s_axi_awaddr[16]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [16]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [16]),\n .O(\\axaddr_incr_reg[29] [11]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__3_i_1\n (.I0(s_axi_awaddr[23]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [23]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [23]),\n .O(\\axaddr_incr_reg[29] [18]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__3_i_2\n (.I0(s_axi_awaddr[22]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [22]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [22]),\n .O(\\axaddr_incr_reg[29] [17]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__3_i_3\n (.I0(s_axi_awaddr[21]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [21]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [21]),\n .O(\\axaddr_incr_reg[29] [16]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__3_i_4\n (.I0(s_axi_awaddr[20]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [20]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [20]),\n .O(\\axaddr_incr_reg[29] [15]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__4_i_1\n (.I0(s_axi_awaddr[27]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [27]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [27]),\n .O(\\axaddr_incr_reg[29] [22]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__4_i_2\n (.I0(s_axi_awaddr[26]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [26]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [26]),\n .O(\\axaddr_incr_reg[29] [21]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__4_i_3\n (.I0(s_axi_awaddr[25]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [25]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [25]),\n .O(\\axaddr_incr_reg[29] [20]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__4_i_4\n (.I0(s_axi_awaddr[24]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [24]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [24]),\n .O(\\axaddr_incr_reg[29] [19]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__5_i_1\n (.I0(s_axi_awaddr[29]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [29]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [29]),\n .O(\\axaddr_incr_reg[29] [24]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__5_i_2\n (.I0(s_axi_awaddr[28]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [28]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [28]),\n .O(\\axaddr_incr_reg[29] [23]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry_i_1\n (.I0(s_axi_awaddr[5]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [5]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [5]),\n .O(\\axaddr_incr_reg[29] [1]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry_i_2\n (.I0(s_axi_awaddr[7]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [7]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [7]),\n .O(\\axaddr_incr_reg[29] [3]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry_i_3\n (.I0(s_axi_awaddr[6]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [6]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [6]),\n .O(\\axaddr_incr_reg[29] [2]));\n LUT5 #(\n .INIT(32'h111DDD1D)) \n axaddr_incr_p_reg0_carry_i_4\n (.I0(\\axaddr_incr_reg[29]_1 [5]),\n .I1(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I2(\\axaddr_reg[29]_0 [5]),\n .I3(s_axi_awready),\n .I4(s_axi_awaddr[5]),\n .O(S));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry_i_5\n (.I0(s_axi_awaddr[4]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [4]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [4]),\n .O(\\axaddr_incr_reg[29] [0]));\n (* SOFT_HLUTNM = \"soft_lutpair1137\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axburst[1]_i_1 \n (.I0(s_axi_awburst),\n .I1(s_axi_awready),\n .I2(axburst),\n .O(\\axburst_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair1137\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axid[0]_i_1 \n (.I0(s_axi_awid),\n .I1(s_axi_awready),\n .I2(axid),\n .O(b_awid));\n LUT3 #(\n .INIT(8'hB8)) \n \\axlen[0]_i_1 \n (.I0(s_axi_awlen[0]),\n .I1(s_axi_awready),\n .I2(\\axlen_reg[7]_0 [0]),\n .O(axlen_int[0]));\n LUT3 #(\n .INIT(8'hB8)) \n \\axlen[1]_i_1 \n (.I0(s_axi_awlen[1]),\n .I1(s_axi_awready),\n .I2(\\axlen_reg[7]_0 [1]),\n .O(axlen_int[1]));\n LUT3 #(\n .INIT(8'hB8)) \n \\axlen[2]_i_1 \n (.I0(s_axi_awlen[2]),\n .I1(s_axi_awready),\n .I2(\\axlen_reg[7]_0 [2]),\n .O(axlen_int[2]));\n LUT3 #(\n .INIT(8'hB8)) \n \\axlen[3]_i_1 \n (.I0(s_axi_awlen[3]),\n .I1(s_axi_awready),\n .I2(\\axlen_reg[7]_0 [3]),\n .O(axlen_int[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1150\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axlen[4]_i_1 \n (.I0(s_axi_awlen[4]),\n .I1(s_axi_awready),\n .I2(\\axlen_reg[7]_0 [4]),\n .O(\\axlen_reg[7] [0]));\n (* SOFT_HLUTNM = \"soft_lutpair1150\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axlen[5]_i_1 \n (.I0(s_axi_awlen[5]),\n .I1(s_axi_awready),\n .I2(\\axlen_reg[7]_0 [5]),\n .O(\\axlen_reg[7] [1]));\n (* SOFT_HLUTNM = \"soft_lutpair1149\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axlen[6]_i_1 \n (.I0(s_axi_awlen[6]),\n .I1(s_axi_awready),\n .I2(\\axlen_reg[7]_0 [6]),\n .O(\\axlen_reg[7] [2]));\n (* SOFT_HLUTNM = \"soft_lutpair1148\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axlen[7]_i_1 \n (.I0(s_axi_awlen[7]),\n .I1(s_axi_awready),\n .I2(\\axlen_reg[7]_0 [7]),\n .O(\\axlen_reg[7] [3]));\n LUT6 #(\n .INIT(64'hABABAB515151AB51)) \n \\axlen_cnt[0]_i_1 \n (.I0(axready_reg_0),\n .I1(Q[0]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axlen_reg[7]_0 [0]),\n .I4(s_axi_awready),\n .I5(s_axi_awlen[0]),\n .O(D[0]));\n LUT6 #(\n .INIT(64'hABABAB515151AB51)) \n \\axlen_cnt[0]_i_1__0 \n (.I0(axready_reg_1),\n .I1(\\axlen_cnt_reg[3]_0 [0]),\n .I2(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I3(\\axlen_reg[7]_0 [0]),\n .I4(s_axi_awready),\n .I5(s_axi_awlen[0]),\n .O(\\axlen_cnt_reg[3] [0]));\n LUT6 #(\n .INIT(64'hFFFFE4B100004E1B)) \n \\axlen_cnt[1]_i_1 \n (.I0(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I1(Q[1]),\n .I2(axlen_int[0]),\n .I3(Q[0]),\n .I4(axready_reg_0),\n .I5(axlen_int[1]),\n .O(D[1]));\n LUT6 #(\n .INIT(64'hFFFFE4B100004E1B)) \n \\axlen_cnt[1]_i_1__0 \n (.I0(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I1(\\axlen_cnt_reg[3]_0 [1]),\n .I2(axlen_int[0]),\n .I3(\\axlen_cnt_reg[3]_0 [0]),\n .I4(axready_reg_1),\n .I5(axlen_int[1]),\n .O(\\axlen_cnt_reg[3] [1]));\n LUT5 #(\n .INIT(32'hFFE1004B)) \n \\axlen_cnt[2]_i_1 \n (.I0(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I1(Q[2]),\n .I2(\\axlen_cnt[2]_i_2_n_0 ),\n .I3(axready_reg_0),\n .I4(axlen_int[2]),\n .O(D[2]));\n LUT5 #(\n .INIT(32'hFFE1004B)) \n \\axlen_cnt[2]_i_1__0 \n (.I0(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I1(\\axlen_cnt_reg[3]_0 [2]),\n .I2(\\axlen_cnt[2]_i_2__0_n_0 ),\n .I3(axready_reg_1),\n .I4(axlen_int[2]),\n .O(\\axlen_cnt_reg[3] [2]));\n LUT5 #(\n .INIT(32'hFFFACCFA)) \n \\axlen_cnt[2]_i_2 \n (.I0(Q[0]),\n .I1(axlen_int[0]),\n .I2(Q[1]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(axlen_int[1]),\n .O(\\axlen_cnt[2]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFACCFA)) \n \\axlen_cnt[2]_i_2__0 \n (.I0(\\axlen_cnt_reg[3]_0 [0]),\n .I1(axlen_int[0]),\n .I2(\\axlen_cnt_reg[3]_0 [1]),\n .I3(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I4(axlen_int[1]),\n .O(\\axlen_cnt[2]_i_2__0_n_0 ));\n LUT5 #(\n .INIT(32'hFFE1004B)) \n \\axlen_cnt[3]_i_1 \n (.I0(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I1(Q[3]),\n .I2(\\axlen_cnt[3]_i_2_n_0 ),\n .I3(axready_reg_0),\n .I4(axlen_int[3]),\n .O(D[3]));\n LUT5 #(\n .INIT(32'hFF1E00B4)) \n \\axlen_cnt[3]_i_1__0 \n (.I0(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I1(\\axlen_cnt_reg[3]_0 [3]),\n .I2(\\axlen_cnt[3]_i_2__0_n_0 ),\n .I3(axready_reg_1),\n .I4(axlen_int[3]),\n .O(\\axlen_cnt_reg[3] [3]));\n LUT6 #(\n .INIT(64'hFEFEFEAEAEAEFEAE)) \n \\axlen_cnt[3]_i_2 \n (.I0(\\axlen_cnt[2]_i_2_n_0 ),\n .I1(Q[2]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axlen_reg[7]_0 [2]),\n .I4(s_axi_awready),\n .I5(s_axi_awlen[2]),\n .O(\\axlen_cnt[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0101015151510151)) \n \\axlen_cnt[3]_i_2__0 \n (.I0(\\axlen_cnt[2]_i_2__0_n_0 ),\n .I1(\\axlen_cnt_reg[3]_0 [2]),\n .I2(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I3(\\axlen_reg[7]_0 [2]),\n .I4(s_axi_awready),\n .I5(s_axi_awlen[2]),\n .O(\\axlen_cnt[3]_i_2__0_n_0 ));\n LUT6 #(\n .INIT(64'hF606F6F6F6060606)) \n \\axlen_cnt[4]_i_1 \n (.I0(\\axlen_cnt[4]_i_2_n_0 ),\n .I1(\\axlen_cnt[4]_i_3_n_0 ),\n .I2(axready_reg_0),\n .I3(s_axi_awlen[4]),\n .I4(s_axi_awready),\n .I5(\\axlen_reg[7]_0 [4]),\n .O(D[4]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axlen_cnt[4]_i_2 \n (.I0(s_axi_awlen[4]),\n .I1(s_axi_awready),\n .I2(\\axlen_reg[7]_0 [4]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(Q[4]),\n .O(\\axlen_cnt[4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0101015151510151)) \n \\axlen_cnt[4]_i_3 \n (.I0(\\axlen_cnt[3]_i_2_n_0 ),\n .I1(Q[3]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axlen_reg[7]_0 [3]),\n .I4(s_axi_awready),\n .I5(s_axi_awlen[3]),\n .O(\\axlen_cnt[4]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hF909F9F9F9090909)) \n \\axlen_cnt[5]_i_1 \n (.I0(\\axlen_cnt[5]_i_2_n_0 ),\n .I1(\\axlen_cnt[5]_i_3_n_0 ),\n .I2(axready_reg_0),\n .I3(s_axi_awlen[5]),\n .I4(s_axi_awready),\n .I5(\\axlen_reg[7]_0 [5]),\n .O(D[5]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axlen_cnt[5]_i_2 \n (.I0(s_axi_awlen[5]),\n .I1(s_axi_awready),\n .I2(\\axlen_reg[7]_0 [5]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(Q[5]),\n .O(\\axlen_cnt[5]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFEFEA)) \n \\axlen_cnt[5]_i_3 \n (.I0(\\axlen_cnt[4]_i_2_n_0 ),\n .I1(axlen_int[3]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(Q[3]),\n .I4(\\axlen_cnt[3]_i_2_n_0 ),\n .O(\\axlen_cnt[5]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hF909F9F9F9090909)) \n \\axlen_cnt[6]_i_1 \n (.I0(\\axlen_cnt[7]_i_3_n_0 ),\n .I1(\\axlen_cnt[7]_i_4_n_0 ),\n .I2(axready_reg_0),\n .I3(s_axi_awlen[6]),\n .I4(s_axi_awready),\n .I5(\\axlen_reg[7]_0 [6]),\n .O(D[6]));\n LUT5 #(\n .INIT(32'h0E000ECC)) \n \\axlen_cnt[7]_i_1 \n (.I0(s_axi_awvalid),\n .I1(\\RD_PRI_REG_STARVE.rnw_i_reg ),\n .I2(s_axi_awburst),\n .I3(s_axi_awready),\n .I4(axburst),\n .O(E));\n LUT6 #(\n .INIT(64'hFFFFEEE10000444B)) \n \\axlen_cnt[7]_i_2 \n (.I0(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I1(Q[7]),\n .I2(\\axlen_cnt[7]_i_3_n_0 ),\n .I3(\\axlen_cnt[7]_i_4_n_0 ),\n .I4(axready_reg_0),\n .I5(\\axlen_reg[7] [3]),\n .O(D[7]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axlen_cnt[7]_i_3 \n (.I0(s_axi_awlen[6]),\n .I1(s_axi_awready),\n .I2(\\axlen_reg[7]_0 [6]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(Q[6]),\n .O(\\axlen_cnt[7]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFEAE)) \n \\axlen_cnt[7]_i_4 \n (.I0(\\axlen_cnt[3]_i_2_n_0 ),\n .I1(Q[3]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(axlen_int[3]),\n .I4(\\axlen_cnt[4]_i_2_n_0 ),\n .I5(\\axlen_cnt[5]_i_2_n_0 ),\n .O(\\axlen_cnt[7]_i_4_n_0 ));\n LUT4 #(\n .INIT(16'hABFB)) \n axready_i_1\n (.I0(b_push),\n .I1(axvalid),\n .I2(s_axi_awready),\n .I3(s_axi_awvalid),\n .O(axready_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n axready_reg\n (.C(CLK),\n .CE(1'b1),\n .D(axready_i_1_n_0),\n .Q(s_axi_awready),\n .R(areset_d1));\n LUT3 #(\n .INIT(8'hB8)) \n axvalid_i_1\n (.I0(s_axi_awvalid),\n .I1(s_axi_awready),\n .I2(axvalid),\n .O(awvalid_int));\n LUT6 #(\n .INIT(64'hF606F6F6F6060606)) \n \\int_addr[0]_i_1 \n (.I0(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]),\n .I1(axlen_int[0]),\n .I2(axready_reg_1),\n .I3(s_axi_awaddr[5]),\n .I4(s_axi_awready),\n .I5(\\axaddr_reg[29]_0 [5]),\n .O(\\int_addr_reg[3] [0]));\n LUT6 #(\n .INIT(64'hBFBFBFEA40401540)) \n \\int_addr[1]_i_1 \n (.I0(axready_reg_1),\n .I1(axlen_int[1]),\n .I2(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]),\n .I3(\\int_addr_reg[3]_1 [1]),\n .I4(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I5(\\axaddr_reg[29] [6]),\n .O(\\int_addr_reg[3] [1]));\n (* SOFT_HLUTNM = \"soft_lutpair1131\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\int_addr[1]_i_2 \n (.I0(s_axi_awaddr[5]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [5]),\n .I3(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I4(\\int_addr_reg[3]_1 [0]),\n .O(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]));\n LUT6 #(\n .INIT(64'hBFBFBFEA40401540)) \n \\int_addr[2]_i_1 \n (.I0(axready_reg_1),\n .I1(axlen_int[2]),\n .I2(\\int_addr[3]_i_5_n_0 ),\n .I3(\\int_addr_reg[3]_1 [2]),\n .I4(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I5(\\axaddr_reg[29] [7]),\n .O(\\int_addr_reg[3] [2]));\n LUT3 #(\n .INIT(8'h80)) \n \\int_addr[2]_i_2 \n (.I0(s_axi_awvalid),\n .I1(s_axi_awready),\n .I2(s_axi_awburst),\n .O(\\axi_mc_cmd_translator_0/wrap_axhandshake ));\n LUT5 #(\n .INIT(32'hCFC08080)) \n \\int_addr[3]_i_1 \n (.I0(s_axi_awvalid),\n .I1(s_axi_awburst),\n .I2(s_axi_awready),\n .I3(axburst),\n .I4(\\RD_PRI_REG_STARVE.rnw_i_reg ),\n .O(\\axlen_cnt_reg[0] ));\n LUT6 #(\n .INIT(64'h8BBBBBBBB8888888)) \n \\int_addr[3]_i_2 \n (.I0(\\axaddr_reg[29] [8]),\n .I1(axready_reg_1),\n .I2(axlen_int[3]),\n .I3(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [7]),\n .I4(\\int_addr[3]_i_5_n_0 ),\n .I5(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [8]),\n .O(\\int_addr_reg[3] [3]));\n (* SOFT_HLUTNM = \"soft_lutpair1129\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\int_addr[3]_i_4 \n (.I0(s_axi_awaddr[7]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [7]),\n .I3(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I4(\\int_addr_reg[3]_1 [2]),\n .O(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [7]));\n LUT6 #(\n .INIT(64'hEEE222E200000000)) \n \\int_addr[3]_i_5 \n (.I0(\\int_addr_reg[3]_1 [1]),\n .I1(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I2(\\axaddr_reg[29]_0 [6]),\n .I3(s_axi_awready),\n .I4(s_axi_awaddr[6]),\n .I5(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]),\n .O(\\int_addr[3]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1128\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\int_addr[3]_i_6 \n (.I0(s_axi_awaddr[8]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [8]),\n .I3(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I4(\\int_addr_reg[3]_1 [3]),\n .O(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [8]));\n LUT5 #(\n .INIT(32'hAA000C00)) \n \\memory_reg[7][0]_srl8_i_1 \n (.I0(\\memory_reg[7][0]_srl8_i_2_n_0 ),\n .I1(\\memory_reg[7][0]_srl8_i_3_n_0 ),\n .I2(\\axlen_cnt[3]_i_2_n_0 ),\n .I3(\\RD_PRI_REG_STARVE.rnw_i_reg ),\n .I4(\\axburst_reg[1] ),\n .O(b_push));\n LUT6 #(\n .INIT(64'h0000000000440347)) \n \\memory_reg[7][0]_srl8_i_2 \n (.I0(axlen_int[2]),\n .I1(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I2(\\axlen_cnt_reg[3]_0 [2]),\n .I3(axlen_int[3]),\n .I4(\\axlen_cnt_reg[3]_0 [3]),\n .I5(\\axlen_cnt[2]_i_2__0_n_0 ),\n .O(\\memory_reg[7][0]_srl8_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h00000001)) \n \\memory_reg[7][0]_srl8_i_3 \n (.I0(\\axlen_cnt[4]_i_2_n_0 ),\n .I1(\\axlen_cnt[5]_i_2_n_0 ),\n .I2(\\memory_reg[7][0]_srl8_i_4_n_0 ),\n .I3(\\memory_reg[7][0]_srl8_i_5_n_0 ),\n .I4(\\axlen_cnt[7]_i_3_n_0 ),\n .O(\\memory_reg[7][0]_srl8_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\memory_reg[7][0]_srl8_i_4 \n (.I0(s_axi_awlen[7]),\n .I1(s_axi_awready),\n .I2(\\axlen_reg[7]_0 [7]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(Q[7]),\n .O(\\memory_reg[7][0]_srl8_i_4_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\memory_reg[7][0]_srl8_i_5 \n (.I0(s_axi_awlen[3]),\n .I1(s_axi_awready),\n .I2(\\axlen_reg[7]_0 [3]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(Q[3]),\n .O(\\memory_reg[7][0]_srl8_i_5_n_0 ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_axi_mc_wrap_cmd\" *) \nmodule ddr3_ifmig_7series_v4_0_axi_mc_wrap_cmd\n (\\int_addr_reg[3]_0 ,\n \\axlen_cnt_reg[3]_0 ,\n areset_d1,\n axready_reg,\n axready_reg_0,\n CLK,\n \\axlen_cnt_reg[3]_1 );\n output [3:0]\\int_addr_reg[3]_0 ;\n output [3:0]\\axlen_cnt_reg[3]_0 ;\n input areset_d1;\n input [0:0]axready_reg;\n input [3:0]axready_reg_0;\n input CLK;\n input [3:0]\\axlen_cnt_reg[3]_1 ;\n\n wire CLK;\n wire areset_d1;\n wire [3:0]\\axlen_cnt_reg[3]_0 ;\n wire [3:0]\\axlen_cnt_reg[3]_1 ;\n wire [0:0]axready_reg;\n wire [3:0]axready_reg_0;\n wire [3:0]\\int_addr_reg[3]_0 ;\n\n FDSE #(\n .INIT(1'b1)) \n \\axlen_cnt_reg[0] \n (.C(CLK),\n .CE(axready_reg),\n .D(\\axlen_cnt_reg[3]_1 [0]),\n .Q(\\axlen_cnt_reg[3]_0 [0]),\n .S(areset_d1));\n FDSE #(\n .INIT(1'b1)) \n \\axlen_cnt_reg[1] \n (.C(CLK),\n .CE(axready_reg),\n .D(\\axlen_cnt_reg[3]_1 [1]),\n .Q(\\axlen_cnt_reg[3]_0 [1]),\n .S(areset_d1));\n FDSE #(\n .INIT(1'b1)) \n \\axlen_cnt_reg[2] \n (.C(CLK),\n .CE(axready_reg),\n .D(\\axlen_cnt_reg[3]_1 [2]),\n .Q(\\axlen_cnt_reg[3]_0 [2]),\n .S(areset_d1));\n FDSE #(\n .INIT(1'b1)) \n \\axlen_cnt_reg[3] \n (.C(CLK),\n .CE(axready_reg),\n .D(\\axlen_cnt_reg[3]_1 [3]),\n .Q(\\axlen_cnt_reg[3]_0 [3]),\n .S(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\int_addr_reg[0] \n (.C(CLK),\n .CE(axready_reg),\n .D(axready_reg_0[0]),\n .Q(\\int_addr_reg[3]_0 [0]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\int_addr_reg[1] \n (.C(CLK),\n .CE(axready_reg),\n .D(axready_reg_0[1]),\n .Q(\\int_addr_reg[3]_0 [1]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\int_addr_reg[2] \n (.C(CLK),\n .CE(axready_reg),\n .D(axready_reg_0[2]),\n .Q(\\int_addr_reg[3]_0 [2]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\int_addr_reg[3] \n (.C(CLK),\n .CE(axready_reg),\n .D(axready_reg_0[3]),\n .Q(\\int_addr_reg[3]_0 [3]),\n .R(areset_d1));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_axi_mc_wrap_cmd\" *) \nmodule ddr3_ifmig_7series_v4_0_axi_mc_wrap_cmd__parameterized0\n (\\app_addr_r1_reg[6] ,\n \\axlen_cnt_reg[3]_0 ,\n areset_d1,\n axready_reg,\n axready_reg_0,\n CLK,\n \\axlen_cnt_reg[3]_1 );\n output [3:0]\\app_addr_r1_reg[6] ;\n output [3:0]\\axlen_cnt_reg[3]_0 ;\n input areset_d1;\n input [0:0]axready_reg;\n input [3:0]axready_reg_0;\n input CLK;\n input [3:0]\\axlen_cnt_reg[3]_1 ;\n\n wire CLK;\n wire [3:0]\\app_addr_r1_reg[6] ;\n wire areset_d1;\n wire [3:0]\\axlen_cnt_reg[3]_0 ;\n wire [3:0]\\axlen_cnt_reg[3]_1 ;\n wire [0:0]axready_reg;\n wire [3:0]axready_reg_0;\n\n FDSE #(\n .INIT(1'b1)) \n \\axlen_cnt_reg[0] \n (.C(CLK),\n .CE(axready_reg),\n .D(\\axlen_cnt_reg[3]_1 [0]),\n .Q(\\axlen_cnt_reg[3]_0 [0]),\n .S(areset_d1));\n FDSE #(\n .INIT(1'b1)) \n \\axlen_cnt_reg[1] \n (.C(CLK),\n .CE(axready_reg),\n .D(\\axlen_cnt_reg[3]_1 [1]),\n .Q(\\axlen_cnt_reg[3]_0 [1]),\n .S(areset_d1));\n FDSE #(\n .INIT(1'b1)) \n \\axlen_cnt_reg[2] \n (.C(CLK),\n .CE(axready_reg),\n .D(\\axlen_cnt_reg[3]_1 [2]),\n .Q(\\axlen_cnt_reg[3]_0 [2]),\n .S(areset_d1));\n FDSE #(\n .INIT(1'b1)) \n \\axlen_cnt_reg[3] \n (.C(CLK),\n .CE(axready_reg),\n .D(\\axlen_cnt_reg[3]_1 [3]),\n .Q(\\axlen_cnt_reg[3]_0 [3]),\n .S(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\int_addr_reg[0] \n (.C(CLK),\n .CE(axready_reg),\n .D(axready_reg_0[0]),\n .Q(\\app_addr_r1_reg[6] [0]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\int_addr_reg[1] \n (.C(CLK),\n .CE(axready_reg),\n .D(axready_reg_0[1]),\n .Q(\\app_addr_r1_reg[6] [1]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\int_addr_reg[2] \n (.C(CLK),\n .CE(axready_reg),\n .D(axready_reg_0[2]),\n .Q(\\app_addr_r1_reg[6] [2]),\n .R(areset_d1));\n FDRE #(\n .INIT(1'b0)) \n \\int_addr_reg[3] \n (.C(CLK),\n .CE(axready_reg),\n .D(axready_reg_0[3]),\n .Q(\\app_addr_r1_reg[6] [3]),\n .R(areset_d1));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_bank_cntrl\" *) \nmodule ddr3_ifmig_7series_v4_0_bank_cntrl\n (rb_hit_busy_r,\n E,\n idle_r_lcl_reg,\n \\rd_this_rank_r_reg[0] ,\n \\act_this_rank_r_reg[0] ,\n req_periodic_rd_r,\n bm_end_r1_reg,\n row_hit_r,\n bm_end_r1,\n bm_end_r1_reg_0,\n \\rp_timer.rp_timer_r_reg[1] ,\n act_this_rank_r,\n req_bank_rdy_r,\n req_bank_rdy_ns,\n demand_priority_r,\n demanded_prior_r,\n ofs_rdy_r,\n wr_this_rank_r,\n rd_this_rank_r,\n wait_for_maint_r_lcl_reg,\n bm_end_r1_reg_1,\n pre_bm_end_r,\n rb_hit_busies_r,\n pre_passing_open_bank_r,\n tail_r,\n q_entry_r,\n idle_r_lcl_reg_0,\n \\rp_timer.rp_timer_r_reg[1]_0 ,\n ordered_r_lcl,\n req_bank_rdy_r_reg,\n ofs_rdy_r0,\n granted_col_ns,\n granted_col_r_reg,\n Q,\n head_r_lcl_reg,\n head_r_lcl_reg_0,\n set_order_q_7,\n \\ras_timer_r_reg[2] ,\n \\ras_timer_r_reg[1] ,\n \\ras_timer_r_reg[0] ,\n pre_wait_r_reg,\n pre_wait_r_reg_0,\n \\q_entry_r_reg[0] ,\n act_wait_r_lcl_reg,\n granted_pre_ns,\n \\grant_r_reg[1] ,\n granted_row_r_reg,\n req_bank_rdy_r_reg_0,\n rnk_config_strobe_ns,\n \\rnk_config_strobe_r_reg[0] ,\n granted_col_r_reg_0,\n auto_pre_r_lcl_reg,\n pass_open_bank_r_lcl_reg,\n \\cmd_pipe_plus.mc_address_reg[14] ,\n \\cmd_pipe_plus.mc_bank_reg[2] ,\n \\col_mux.col_data_buf_addr_r_reg[4] ,\n \\cmd_pipe_plus.mc_address_reg[24] ,\n p_67_out,\n CLK,\n periodic_rd_insert,\n hi_priority,\n override_demand_ns,\n rstdiv0_sync_r1_reg_rep__0,\n phy_mc_ctl_full,\n SR,\n of_ctl_full_v,\n wait_for_maint_ns,\n pass_open_bank_r_lcl_reg_0,\n rb_hit_busies_ns,\n idle_r_lcl_reg_1,\n \\q_entry_r_reg[0]_0 ,\n head_r_lcl_reg_1,\n auto_pre_r_lcl_reg_0,\n ordered_r_lcl_reg,\n ordered_r_lcl_reg_0,\n \\entry_cnt_reg[2] ,\n \\entry_cnt_reg[2]_0 ,\n rd_wr_r_lcl_reg,\n col_wait_r_reg,\n \\wtr_timer.wtr_cnt_r_reg[1] ,\n \\grant_r_reg[0] ,\n cmd,\n \\grant_r_reg[1]_0 ,\n periodic_rd_ack_r_lcl_reg,\n use_addr,\n accept_internal_r,\n req_wr_r_lcl_reg,\n pre_bm_end_r_reg,\n rb_hit_busy_r_reg,\n periodic_rd_ack_r_lcl_reg_0,\n periodic_rd_ack_r_lcl_reg_1,\n \\ras_timer_r_reg[2]_0 ,\n bm_end_r1_reg_2,\n rd_wr_r_lcl_reg_0,\n \\grant_r_reg[0]_0 ,\n bm_end_r1_reg_3,\n req_wr_r_lcl_reg_0,\n pre_passing_open_bank_r_0,\n pass_open_bank_r_lcl_reg_1,\n maint_req_r,\n was_wr,\n accept_r_reg,\n rstdiv0_sync_r1_reg_rep__21,\n app_hi_pri_r2,\n idle_r_lcl_reg_2,\n accept_r_reg_0,\n \\grant_r_reg[0]_1 ,\n auto_pre_r_lcl_reg_1,\n \\grant_r_reg[1]_1 ,\n \\rnk_config_strobe_r_reg[0]_0 ,\n req_bank_rdy_ns_1,\n demand_priority_r_reg,\n rnk_config_valid_r_lcl_reg,\n \\rnk_config_strobe_r_reg[0]_1 ,\n \\order_q_r_reg[0] ,\n req_wr_r_lcl_reg_1,\n \\maint_controller.maint_wip_r_lcl_reg ,\n periodic_rd_cntr_r_reg,\n demanded_prior_r_1,\n demand_priority_r_2,\n \\app_addr_r1_reg[27] ,\n req_bank_rdy_r_reg_1,\n \\app_addr_r1_reg[12] ,\n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ,\n D,\n \\app_addr_r1_reg[9] ,\n rstdiv0_sync_r1_reg_rep__20,\n pass_open_bank_r_lcl_reg_2,\n granted_col_r_reg_1);\n output [0:0]rb_hit_busy_r;\n output [0:0]E;\n output [0:0]idle_r_lcl_reg;\n output \\rd_this_rank_r_reg[0] ;\n output \\act_this_rank_r_reg[0] ;\n output [0:0]req_periodic_rd_r;\n output bm_end_r1_reg;\n output row_hit_r;\n output bm_end_r1;\n output bm_end_r1_reg_0;\n output \\rp_timer.rp_timer_r_reg[1] ;\n output [0:0]act_this_rank_r;\n output req_bank_rdy_r;\n output req_bank_rdy_ns;\n output demand_priority_r;\n output demanded_prior_r;\n output ofs_rdy_r;\n output [0:0]wr_this_rank_r;\n output [0:0]rd_this_rank_r;\n output wait_for_maint_r_lcl_reg;\n output bm_end_r1_reg_1;\n output pre_bm_end_r;\n output [0:0]rb_hit_busies_r;\n output pre_passing_open_bank_r;\n output tail_r;\n output q_entry_r;\n output idle_r_lcl_reg_0;\n output \\rp_timer.rp_timer_r_reg[1]_0 ;\n output ordered_r_lcl;\n output req_bank_rdy_r_reg;\n output ofs_rdy_r0;\n output granted_col_ns;\n output granted_col_r_reg;\n output [1:0]Q;\n output head_r_lcl_reg;\n output head_r_lcl_reg_0;\n output set_order_q_7;\n output \\ras_timer_r_reg[2] ;\n output \\ras_timer_r_reg[1] ;\n output \\ras_timer_r_reg[0] ;\n output pre_wait_r_reg;\n output pre_wait_r_reg_0;\n output \\q_entry_r_reg[0] ;\n output act_wait_r_lcl_reg;\n output granted_pre_ns;\n output \\grant_r_reg[1] ;\n output granted_row_r_reg;\n output req_bank_rdy_r_reg_0;\n output rnk_config_strobe_ns;\n output \\rnk_config_strobe_r_reg[0] ;\n output granted_col_r_reg_0;\n output auto_pre_r_lcl_reg;\n output pass_open_bank_r_lcl_reg;\n output [14:0]\\cmd_pipe_plus.mc_address_reg[14] ;\n output [2:0]\\cmd_pipe_plus.mc_bank_reg[2] ;\n output [4:0]\\col_mux.col_data_buf_addr_r_reg[4] ;\n output [6:0]\\cmd_pipe_plus.mc_address_reg[24] ;\n input p_67_out;\n input CLK;\n input periodic_rd_insert;\n input hi_priority;\n input override_demand_ns;\n input rstdiv0_sync_r1_reg_rep__0;\n input phy_mc_ctl_full;\n input [0:0]SR;\n input [0:0]of_ctl_full_v;\n input wait_for_maint_ns;\n input pass_open_bank_r_lcl_reg_0;\n input rb_hit_busies_ns;\n input idle_r_lcl_reg_1;\n input \\q_entry_r_reg[0]_0 ;\n input head_r_lcl_reg_1;\n input auto_pre_r_lcl_reg_0;\n input ordered_r_lcl_reg;\n input ordered_r_lcl_reg_0;\n input \\entry_cnt_reg[2] ;\n input \\entry_cnt_reg[2]_0 ;\n input rd_wr_r_lcl_reg;\n input col_wait_r_reg;\n input \\wtr_timer.wtr_cnt_r_reg[1] ;\n input \\grant_r_reg[0] ;\n input [1:0]cmd;\n input [1:0]\\grant_r_reg[1]_0 ;\n input periodic_rd_ack_r_lcl_reg;\n input use_addr;\n input accept_internal_r;\n input req_wr_r_lcl_reg;\n input pre_bm_end_r_reg;\n input rb_hit_busy_r_reg;\n input periodic_rd_ack_r_lcl_reg_0;\n input periodic_rd_ack_r_lcl_reg_1;\n input \\ras_timer_r_reg[2]_0 ;\n input bm_end_r1_reg_2;\n input rd_wr_r_lcl_reg_0;\n input [0:0]\\grant_r_reg[0]_0 ;\n input bm_end_r1_reg_3;\n input req_wr_r_lcl_reg_0;\n input pre_passing_open_bank_r_0;\n input pass_open_bank_r_lcl_reg_1;\n input maint_req_r;\n input was_wr;\n input accept_r_reg;\n input rstdiv0_sync_r1_reg_rep__21;\n input app_hi_pri_r2;\n input [0:0]idle_r_lcl_reg_2;\n input accept_r_reg_0;\n input [0:0]\\grant_r_reg[0]_1 ;\n input auto_pre_r_lcl_reg_1;\n input \\grant_r_reg[1]_1 ;\n input \\rnk_config_strobe_r_reg[0]_0 ;\n input req_bank_rdy_ns_1;\n input demand_priority_r_reg;\n input rnk_config_valid_r_lcl_reg;\n input \\rnk_config_strobe_r_reg[0]_1 ;\n input \\order_q_r_reg[0] ;\n input req_wr_r_lcl_reg_1;\n input \\maint_controller.maint_wip_r_lcl_reg ;\n input periodic_rd_cntr_r_reg;\n input demanded_prior_r_1;\n input demand_priority_r_2;\n input [14:0]\\app_addr_r1_reg[27] ;\n input req_bank_rdy_r_reg_1;\n input [2:0]\\app_addr_r1_reg[12] ;\n input [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n input [1:0]D;\n input [6:0]\\app_addr_r1_reg[9] ;\n input rstdiv0_sync_r1_reg_rep__20;\n input pass_open_bank_r_lcl_reg_2;\n input granted_col_r_reg_1;\n\n wire CLK;\n wire [1:0]D;\n wire [0:0]E;\n wire [1:0]Q;\n wire [0:0]SR;\n wire accept_internal_r;\n wire accept_r_reg;\n wire accept_r_reg_0;\n wire [0:0]act_this_rank_r;\n wire \\act_this_rank_r_reg[0] ;\n wire act_wait_ns;\n wire act_wait_r_lcl_reg;\n wire [2:0]\\app_addr_r1_reg[12] ;\n wire [14:0]\\app_addr_r1_reg[27] ;\n wire [6:0]\\app_addr_r1_reg[9] ;\n wire app_hi_pri_r2;\n wire auto_pre_r_lcl_reg;\n wire auto_pre_r_lcl_reg_0;\n wire auto_pre_r_lcl_reg_1;\n wire bank_compare0_n_14;\n wire bank_compare0_n_15;\n wire bank_queue0_n_23;\n wire bank_state0_n_26;\n wire bm_end_r1;\n wire bm_end_r1_reg;\n wire bm_end_r1_reg_0;\n wire bm_end_r1_reg_1;\n wire bm_end_r1_reg_2;\n wire bm_end_r1_reg_3;\n wire [1:0]cmd;\n wire [14:0]\\cmd_pipe_plus.mc_address_reg[14] ;\n wire [6:0]\\cmd_pipe_plus.mc_address_reg[24] ;\n wire [2:0]\\cmd_pipe_plus.mc_bank_reg[2] ;\n wire [4:0]\\col_mux.col_data_buf_addr_r_reg[4] ;\n wire col_wait_r;\n wire col_wait_r_reg;\n wire demand_priority_r;\n wire demand_priority_r_2;\n wire demand_priority_r_reg;\n wire demanded_prior_r;\n wire demanded_prior_r_1;\n wire \\entry_cnt_reg[2] ;\n wire \\entry_cnt_reg[2]_0 ;\n wire \\grant_r_reg[0] ;\n wire [0:0]\\grant_r_reg[0]_0 ;\n wire [0:0]\\grant_r_reg[0]_1 ;\n wire \\grant_r_reg[1] ;\n wire [1:0]\\grant_r_reg[1]_0 ;\n wire \\grant_r_reg[1]_1 ;\n wire granted_col_ns;\n wire granted_col_r_reg;\n wire granted_col_r_reg_0;\n wire granted_col_r_reg_1;\n wire granted_pre_ns;\n wire granted_row_r_reg;\n wire head_r_lcl_reg;\n wire head_r_lcl_reg_0;\n wire head_r_lcl_reg_1;\n wire hi_priority;\n wire [0:0]idle_r_lcl_reg;\n wire idle_r_lcl_reg_0;\n wire idle_r_lcl_reg_1;\n wire [0:0]idle_r_lcl_reg_2;\n wire \\maint_controller.maint_wip_r_lcl_reg ;\n wire maint_req_r;\n wire [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n wire [0:0]of_ctl_full_v;\n wire ofs_rdy_r;\n wire ofs_rdy_r0;\n wire \\order_q_r_reg[0] ;\n wire ordered_r_lcl;\n wire ordered_r_lcl_reg;\n wire ordered_r_lcl_reg_0;\n wire override_demand_ns;\n wire p_67_out;\n wire pass_open_bank_r_lcl_reg;\n wire pass_open_bank_r_lcl_reg_0;\n wire pass_open_bank_r_lcl_reg_1;\n wire pass_open_bank_r_lcl_reg_2;\n wire periodic_rd_ack_r_lcl_reg;\n wire periodic_rd_ack_r_lcl_reg_0;\n wire periodic_rd_ack_r_lcl_reg_1;\n wire periodic_rd_cntr_r_reg;\n wire periodic_rd_insert;\n wire phy_mc_ctl_full;\n wire pre_bm_end_ns;\n wire pre_bm_end_r;\n wire pre_bm_end_r_reg;\n wire pre_passing_open_bank_ns;\n wire pre_passing_open_bank_r;\n wire pre_passing_open_bank_r_0;\n wire pre_wait_r_reg;\n wire pre_wait_r_reg_0;\n wire q_entry_r;\n wire \\q_entry_r_reg[0] ;\n wire \\q_entry_r_reg[0]_0 ;\n wire q_has_priority;\n wire q_has_rd;\n wire [2:0]ras_timer_passed_ns;\n wire \\ras_timer_r_reg[0] ;\n wire \\ras_timer_r_reg[1] ;\n wire \\ras_timer_r_reg[2] ;\n wire \\ras_timer_r_reg[2]_0 ;\n wire ras_timer_zero_r;\n wire rb_hit_busies_ns;\n wire [0:0]rb_hit_busies_r;\n wire [0:0]rb_hit_busy_r;\n wire rb_hit_busy_r_reg;\n wire [0:0]rd_this_rank_r;\n wire \\rd_this_rank_r_reg[0] ;\n wire rd_wr_ns;\n wire rd_wr_r_lcl_reg;\n wire rd_wr_r_lcl_reg_0;\n wire req_bank_rdy_ns;\n wire req_bank_rdy_ns_1;\n wire req_bank_rdy_r;\n wire req_bank_rdy_r_reg;\n wire req_bank_rdy_r_reg_0;\n wire req_bank_rdy_r_reg_1;\n wire [0:0]req_periodic_rd_r;\n wire req_priority_r;\n wire req_wr_r_lcl_reg;\n wire req_wr_r_lcl_reg_0;\n wire req_wr_r_lcl_reg_1;\n wire rnk_config_strobe_ns;\n wire \\rnk_config_strobe_r_reg[0] ;\n wire \\rnk_config_strobe_r_reg[0]_0 ;\n wire \\rnk_config_strobe_r_reg[0]_1 ;\n wire rnk_config_valid_r_lcl_reg;\n wire row_hit_r;\n wire \\rp_timer.rp_timer_r_reg[1] ;\n wire \\rp_timer.rp_timer_r_reg[1]_0 ;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire set_order_q_7;\n wire start_wtp_timer0;\n wire tail_r;\n wire use_addr;\n wire wait_for_maint_ns;\n wire wait_for_maint_r_lcl_reg;\n wire was_wr;\n wire [0:0]wr_this_rank_r;\n wire \\wtr_timer.wtr_cnt_r_reg[1] ;\n\n ddr3_ifmig_7series_v4_0_bank_compare_0 bank_compare0\n (.CLK(CLK),\n .D(D),\n .Q(Q),\n .act_wait_r_lcl_reg(act_wait_r_lcl_reg),\n .\\app_addr_r1_reg[12] (\\app_addr_r1_reg[12] ),\n .\\app_addr_r1_reg[27] (\\app_addr_r1_reg[27] ),\n .\\app_addr_r1_reg[9] (\\app_addr_r1_reg[9] ),\n .bm_end_r1_reg(bm_end_r1_reg),\n .cmd(cmd),\n .\\cmd_pipe_plus.mc_address_reg[14] (\\cmd_pipe_plus.mc_address_reg[14] ),\n .\\cmd_pipe_plus.mc_address_reg[24] (\\cmd_pipe_plus.mc_address_reg[24] ),\n .\\cmd_pipe_plus.mc_bank_reg[2] (\\cmd_pipe_plus.mc_bank_reg[2] ),\n .\\col_mux.col_data_buf_addr_r_reg[4] (\\col_mux.col_data_buf_addr_r_reg[4] ),\n .col_wait_r(col_wait_r),\n .col_wait_r_reg(col_wait_r_reg),\n .demand_priority_r_reg(bank_compare0_n_14),\n .\\grant_r_reg[0] (\\grant_r_reg[0] ),\n .\\grant_r_reg[1] (\\grant_r_reg[1]_0 ),\n .granted_col_ns(granted_col_ns),\n .granted_col_r_reg(granted_col_r_reg),\n .hi_priority(hi_priority),\n .idle_r_lcl_reg(idle_r_lcl_reg),\n .idle_r_lcl_reg_0(E),\n .\\maint_controller.maint_wip_r_lcl_reg (\\maint_controller.maint_wip_r_lcl_reg ),\n .maint_req_r(maint_req_r),\n .\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),\n .\\order_q_r_reg[0] (req_bank_rdy_r_reg),\n .override_demand_r_reg(bank_state0_n_26),\n .p_67_out(p_67_out),\n .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg),\n .pass_open_bank_r_lcl_reg_0(bm_end_r1_reg_1),\n .periodic_rd_cntr_r_reg(periodic_rd_cntr_r_reg),\n .periodic_rd_insert(periodic_rd_insert),\n .pre_passing_open_bank_r_reg(bank_queue0_n_23),\n .ras_timer_zero_r_reg(bank_compare0_n_15),\n .rb_hit_busy_r(rb_hit_busy_r),\n .\\rd_this_rank_r_reg[0] (\\rd_this_rank_r_reg[0] ),\n .rd_wr_ns(rd_wr_ns),\n .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg),\n .req_bank_rdy_ns(req_bank_rdy_ns),\n .req_bank_rdy_r_reg(req_bank_rdy_r_reg_0),\n .req_periodic_rd_r(req_periodic_rd_r),\n .req_priority_r(req_priority_r),\n .req_wr_r_lcl_reg_0(req_wr_r_lcl_reg_1),\n .\\rnk_config_strobe_r_reg[0] (\\rnk_config_strobe_r_reg[0]_0 ),\n .row_hit_r(row_hit_r),\n .start_wtp_timer0(start_wtp_timer0),\n .wait_for_maint_r_lcl_reg(wait_for_maint_r_lcl_reg),\n .\\wtr_timer.wtr_cnt_r_reg[1] (\\wtr_timer.wtr_cnt_r_reg[1] ));\n ddr3_ifmig_7series_v4_0_bank_queue bank_queue0\n (.CLK(CLK),\n .D(ras_timer_passed_ns),\n .SR(SR),\n .accept_internal_r(accept_internal_r),\n .accept_r_reg(accept_r_reg),\n .accept_r_reg_0(accept_r_reg_0),\n .act_wait_ns(act_wait_ns),\n .act_wait_r_lcl_reg(\\act_this_rank_r_reg[0] ),\n .app_hi_pri_r2(app_hi_pri_r2),\n .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_0),\n .bm_end_r1_reg(bm_end_r1_reg_1),\n .bm_end_r1_reg_0(bm_end_r1_reg_0),\n .bm_end_r1_reg_1(\\ras_timer_r_reg[2] ),\n .bm_end_r1_reg_2(bm_end_r1_reg_2),\n .bm_end_r1_reg_3(\\ras_timer_r_reg[1] ),\n .bm_end_r1_reg_4(bm_end_r1_reg_3),\n .cmd(cmd[0]),\n .\\grant_r_reg[0] (\\grant_r_reg[1]_0 [0]),\n .\\grant_r_reg[0]_0 (\\grant_r_reg[0]_0 ),\n .\\grant_r_reg[1] (\\grant_r_reg[1]_1 ),\n .granted_row_r_reg(granted_row_r_reg),\n .head_r_lcl_reg_0(head_r_lcl_reg),\n .head_r_lcl_reg_1(head_r_lcl_reg_0),\n .head_r_lcl_reg_2(head_r_lcl_reg_1),\n .idle_r_lcl_reg_0(idle_r_lcl_reg),\n .idle_r_lcl_reg_1(idle_r_lcl_reg_0),\n .idle_r_lcl_reg_2(idle_r_lcl_reg_1),\n .idle_r_lcl_reg_3(idle_r_lcl_reg_2),\n .maint_req_r(maint_req_r),\n .ordered_r_lcl(ordered_r_lcl),\n .ordered_r_lcl_reg_0(ordered_r_lcl_reg),\n .ordered_r_lcl_reg_1(ordered_r_lcl_reg_0),\n .pass_open_bank_r_lcl_reg_0(pass_open_bank_r_lcl_reg_0),\n .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg),\n .periodic_rd_ack_r_lcl_reg_0(periodic_rd_ack_r_lcl_reg_0),\n .periodic_rd_ack_r_lcl_reg_1(periodic_rd_ack_r_lcl_reg_1),\n .periodic_rd_insert(periodic_rd_insert),\n .pre_bm_end_ns(pre_bm_end_ns),\n .pre_bm_end_r(pre_bm_end_r),\n .pre_bm_end_r_reg_0(pre_bm_end_r_reg),\n .pre_passing_open_bank_ns(pre_passing_open_bank_ns),\n .pre_passing_open_bank_r(pre_passing_open_bank_r),\n .pre_passing_open_bank_r_0(pre_passing_open_bank_r_0),\n .q_entry_r(q_entry_r),\n .\\q_entry_r_reg[0]_0 (\\q_entry_r_reg[0] ),\n .\\q_entry_r_reg[0]_1 (\\q_entry_r_reg[0]_0 ),\n .q_has_priority(q_has_priority),\n .q_has_rd(q_has_rd),\n .\\ras_timer_r_reg[1] (\\ras_timer_r_reg[0] ),\n .\\ras_timer_r_reg[2] (bank_queue0_n_23),\n .\\ras_timer_r_reg[2]_0 (\\ras_timer_r_reg[2]_0 ),\n .ras_timer_zero_r(ras_timer_zero_r),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 (rb_hit_busies_r),\n .rb_hit_busies_ns(rb_hit_busies_ns),\n .rb_hit_busy_r(rb_hit_busy_r),\n .rb_hit_busy_r_reg(rb_hit_busy_r_reg),\n .rd_wr_ns(rd_wr_ns),\n .rd_wr_r_lcl_reg(\\rd_this_rank_r_reg[0] ),\n .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg_0),\n .req_bank_rdy_r_reg(req_bank_rdy_r_reg),\n .\\req_data_buf_addr_r_reg[4] (E),\n .req_wr_r_lcl_reg(req_wr_r_lcl_reg),\n .req_wr_r_lcl_reg_0(bm_end_r1_reg),\n .req_wr_r_lcl_reg_1(req_wr_r_lcl_reg_0),\n .\\rp_timer.rp_timer_r_reg[1] (\\rp_timer.rp_timer_r_reg[1]_0 ),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .set_order_q_7(set_order_q_7),\n .tail_r(tail_r),\n .use_addr(use_addr),\n .wait_for_maint_ns(wait_for_maint_ns),\n .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg),\n .was_wr(was_wr));\n ddr3_ifmig_7series_v4_0_bank_state bank_state0\n (.CLK(CLK),\n .D(ras_timer_passed_ns),\n .SR(SR),\n .accept_r_reg(accept_r_reg),\n .act_this_rank_r(act_this_rank_r),\n .\\act_this_rank_r_reg[0]_0 (\\act_this_rank_r_reg[0] ),\n .act_wait_ns(act_wait_ns),\n .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg),\n .auto_pre_r_lcl_reg_0(\\rp_timer.rp_timer_r_reg[1]_0 ),\n .auto_pre_r_lcl_reg_1(auto_pre_r_lcl_reg_1),\n .bm_end_r1(bm_end_r1),\n .bm_end_r1_reg_0(bm_end_r1_reg_3),\n .col_wait_r(col_wait_r),\n .demand_priority_r_2(demand_priority_r_2),\n .demand_priority_r_reg_0(demand_priority_r_reg),\n .demanded_prior_r_1(demanded_prior_r_1),\n .demanded_prior_r_reg_0(demand_priority_r),\n .demanded_prior_r_reg_1(demanded_prior_r),\n .\\entry_cnt_reg[2] (\\entry_cnt_reg[2] ),\n .\\entry_cnt_reg[2]_0 (\\entry_cnt_reg[2]_0 ),\n .\\grant_r_reg[0] (\\grant_r_reg[0]_0 ),\n .\\grant_r_reg[0]_0 (\\grant_r_reg[0]_1 ),\n .\\grant_r_reg[1] (\\grant_r_reg[1] ),\n .\\grant_r_reg[1]_0 (\\grant_r_reg[1]_0 ),\n .granted_col_r_reg(granted_col_r_reg_0),\n .granted_col_r_reg_0(bank_state0_n_26),\n .granted_col_r_reg_1(granted_col_r_reg_1),\n .granted_pre_ns(granted_pre_ns),\n .idle_r_lcl_reg(idle_r_lcl_reg),\n .of_ctl_full_v(of_ctl_full_v),\n .ofs_rdy_r(ofs_rdy_r),\n .ofs_rdy_r0(ofs_rdy_r0),\n .\\order_q_r_reg[0] (bank_compare0_n_14),\n .\\order_q_r_reg[0]_0 (\\order_q_r_reg[0] ),\n .override_demand_ns(override_demand_ns),\n .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg_0),\n .pass_open_bank_r_lcl_reg_0(pass_open_bank_r_lcl_reg_1),\n .pass_open_bank_r_lcl_reg_1(bm_end_r1_reg_1),\n .pass_open_bank_r_lcl_reg_2(pass_open_bank_r_lcl_reg_2),\n .phy_mc_ctl_full(phy_mc_ctl_full),\n .pre_bm_end_ns(pre_bm_end_ns),\n .pre_bm_end_r_reg(bm_end_r1_reg_0),\n .pre_passing_open_bank_ns(pre_passing_open_bank_ns),\n .pre_passing_open_bank_r_reg(bank_queue0_n_23),\n .pre_wait_r_reg_0(pre_wait_r_reg),\n .pre_wait_r_reg_1(pre_wait_r_reg_0),\n .q_has_priority(q_has_priority),\n .q_has_rd(q_has_rd),\n .\\ras_timer_r_reg[0]_0 (\\ras_timer_r_reg[0] ),\n .\\ras_timer_r_reg[1]_0 (\\ras_timer_r_reg[1] ),\n .\\ras_timer_r_reg[2]_0 (\\ras_timer_r_reg[2] ),\n .ras_timer_zero_r(ras_timer_zero_r),\n .rd_this_rank_r(rd_this_rank_r),\n .rd_wr_r_lcl_reg(\\rd_this_rank_r_reg[0] ),\n .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg),\n .rd_wr_r_lcl_reg_1(bank_compare0_n_15),\n .rd_wr_r_lcl_reg_2(req_bank_rdy_r_reg_0),\n .req_bank_rdy_ns(req_bank_rdy_ns),\n .req_bank_rdy_ns_1(req_bank_rdy_ns_1),\n .req_bank_rdy_r(req_bank_rdy_r),\n .req_bank_rdy_r_reg_0(req_bank_rdy_r_reg_1),\n .req_priority_r(req_priority_r),\n .req_wr_r_lcl_reg(bm_end_r1_reg),\n .rnk_config_strobe_ns(rnk_config_strobe_ns),\n .\\rnk_config_strobe_r_reg[0] (\\rnk_config_strobe_r_reg[0] ),\n .\\rnk_config_strobe_r_reg[0]_0 (\\rnk_config_strobe_r_reg[0]_1 ),\n .rnk_config_valid_r_lcl_reg(rnk_config_valid_r_lcl_reg),\n .\\rp_timer.rp_timer_r_reg[1]_0 (\\rp_timer.rp_timer_r_reg[1] ),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .start_wtp_timer0(start_wtp_timer0),\n .tail_r(tail_r),\n .wr_this_rank_r(wr_this_rank_r));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_bank_cntrl\" *) \nmodule ddr3_ifmig_7series_v4_0_bank_cntrl__parameterized0\n (q_has_priority_r_reg,\n E,\n idle_r_lcl_reg,\n \\rd_this_rank_r_reg[0] ,\n row_cmd_wr,\n req_periodic_rd_r,\n bm_end_r1_reg,\n act_this_rank_r,\n wr_this_rank_r,\n rd_this_rank_r,\n row_hit_r_0,\n bm_end_r1_0,\n bm_end_r1_reg_0,\n req_bank_rdy_r,\n req_bank_rdy_ns_1,\n demand_priority_r,\n demanded_prior_r,\n ofs_rdy_r,\n wait_for_maint_r_lcl_reg,\n bm_end_r1_reg_1,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ,\n pre_passing_open_bank_r,\n q_has_rd,\n q_has_priority,\n \\rcd_timer_gt_2.rcd_timer_r_reg[0] ,\n idle_r_lcl_reg_0,\n \\order_q_r_reg[0] ,\n tail_r_3,\n q_entry_r_4,\n \\rp_timer.rp_timer_r_reg[1] ,\n req_bank_rdy_r_reg,\n rb_hit_busies_ns,\n granted_col_r_reg,\n p_9_in,\n Q,\n pass_open_bank_r_lcl_reg,\n head_r_lcl_reg,\n \\q_entry_r_reg[0] ,\n \\q_entry_r_reg[0]_0 ,\n set_order_q,\n \\q_entry_r_reg[0]_1 ,\n \\ras_timer_r_reg[2] ,\n \\ras_timer_r_reg[0] ,\n \\ras_timer_r_reg[1] ,\n \\ras_timer_r_reg[2]_0 ,\n \\cmd_pipe_plus.mc_address_reg[10] ,\n \\cmd_pipe_plus.mc_address_reg[14] ,\n granted_row_ns,\n granted_row_r_reg,\n ras_timer_zero_r_reg,\n auto_pre_r_lcl_reg,\n \\pre_4_1_1T_arb.granted_pre_r_reg ,\n \\rnk_config_strobe_r_reg[0] ,\n \\cmd_pipe_plus.mc_address_reg[40] ,\n \\cmd_pipe_plus.mc_bank_reg[2] ,\n \\col_mux.col_data_buf_addr_r_reg[4] ,\n \\cmd_pipe_plus.mc_address_reg[24] ,\n p_28_out,\n CLK,\n periodic_rd_insert,\n hi_priority,\n rstdiv0_sync_r1_reg_rep__0,\n ofs_rdy_r0,\n wait_for_maint_ns,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ,\n q_has_rd_r_reg,\n q_has_priority_r_reg_0,\n SR,\n head_r_lcl_reg_0,\n ordered_r_lcl_reg,\n idle_r_lcl_reg_1,\n \\q_entry_r_reg[0]_2 ,\n auto_pre_r_lcl_reg_0,\n ordered_r_lcl_reg_0,\n \\req_bank_r_lcl_reg[0] ,\n rb_hit_busies_r,\n idle_r_lcl_reg_2,\n rstdiv0_sync_r1_reg_rep__20,\n \\wtr_timer.wtr_cnt_r_reg[1] ,\n \\order_q_r_reg[0]_0 ,\n \\grant_r_reg[0] ,\n init_calib_complete_reg_rep__6,\n cmd,\n \\grant_r_reg[1] ,\n periodic_rd_ack_r_lcl_reg,\n use_addr,\n accept_internal_r,\n periodic_rd_ack_r_lcl_reg_0,\n periodic_rd_ack_r_lcl_reg_1,\n pre_bm_end_r_reg,\n bm_end_r1_reg_2,\n \\grant_r_reg[1]_0 ,\n rtp_timer_ns1,\n accept_r_reg,\n rstdiv0_sync_r1_reg_rep__21,\n rb_hit_busy_r,\n \\ras_timer_r_reg[1]_0 ,\n bm_end_r1_reg_3,\n bm_end_r1_reg_4,\n req_wr_r_lcl_reg,\n pre_passing_open_bank_r_0,\n \\req_row_r_lcl_reg[10] ,\n \\grant_r_reg[0]_0 ,\n act_wait_r_lcl_reg,\n mc_cs_n_ns,\n head_r_lcl_reg_1,\n \\grant_r_reg[0]_1 ,\n \\ras_timer_r_reg[2]_1 ,\n rd_wr_r_lcl_reg,\n \\maint_controller.maint_wip_r_lcl_reg ,\n periodic_rd_cntr_r_reg,\n maint_req_r,\n \\grant_r_reg[1]_1 ,\n demanded_prior_r_1,\n demand_priority_r_2,\n \\app_addr_r1_reg[27] ,\n req_bank_rdy_r_reg_0,\n \\app_addr_r1_reg[12] ,\n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ,\n D,\n \\app_addr_r1_reg[9] ,\n granted_col_r_reg_0);\n output q_has_priority_r_reg;\n output [0:0]E;\n output [0:0]idle_r_lcl_reg;\n output \\rd_this_rank_r_reg[0] ;\n output [0:0]row_cmd_wr;\n output [0:0]req_periodic_rd_r;\n output bm_end_r1_reg;\n output [0:0]act_this_rank_r;\n output [0:0]wr_this_rank_r;\n output [0:0]rd_this_rank_r;\n output row_hit_r_0;\n output bm_end_r1_0;\n output bm_end_r1_reg_0;\n output req_bank_rdy_r;\n output req_bank_rdy_ns_1;\n output demand_priority_r;\n output demanded_prior_r;\n output ofs_rdy_r;\n output wait_for_maint_r_lcl_reg;\n output bm_end_r1_reg_1;\n output \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ;\n output pre_passing_open_bank_r;\n output q_has_rd;\n output q_has_priority;\n output \\rcd_timer_gt_2.rcd_timer_r_reg[0] ;\n output idle_r_lcl_reg_0;\n output \\order_q_r_reg[0] ;\n output tail_r_3;\n output q_entry_r_4;\n output \\rp_timer.rp_timer_r_reg[1] ;\n output req_bank_rdy_r_reg;\n output rb_hit_busies_ns;\n output granted_col_r_reg;\n output p_9_in;\n output [1:0]Q;\n output pass_open_bank_r_lcl_reg;\n output head_r_lcl_reg;\n output \\q_entry_r_reg[0] ;\n output \\q_entry_r_reg[0]_0 ;\n output set_order_q;\n output \\q_entry_r_reg[0]_1 ;\n output \\ras_timer_r_reg[2] ;\n output \\ras_timer_r_reg[0] ;\n output \\ras_timer_r_reg[1] ;\n output \\ras_timer_r_reg[2]_0 ;\n output [0:0]\\cmd_pipe_plus.mc_address_reg[10] ;\n output [13:0]\\cmd_pipe_plus.mc_address_reg[14] ;\n output granted_row_ns;\n output granted_row_r_reg;\n output [2:0]ras_timer_zero_r_reg;\n output auto_pre_r_lcl_reg;\n output \\pre_4_1_1T_arb.granted_pre_r_reg ;\n output \\rnk_config_strobe_r_reg[0] ;\n output \\cmd_pipe_plus.mc_address_reg[40] ;\n output [2:0]\\cmd_pipe_plus.mc_bank_reg[2] ;\n output [4:0]\\col_mux.col_data_buf_addr_r_reg[4] ;\n output [6:0]\\cmd_pipe_plus.mc_address_reg[24] ;\n input p_28_out;\n input CLK;\n input periodic_rd_insert;\n input hi_priority;\n input rstdiv0_sync_r1_reg_rep__0;\n input ofs_rdy_r0;\n input wait_for_maint_ns;\n input \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ;\n input q_has_rd_r_reg;\n input q_has_priority_r_reg_0;\n input [0:0]SR;\n input head_r_lcl_reg_0;\n input ordered_r_lcl_reg;\n input idle_r_lcl_reg_1;\n input \\q_entry_r_reg[0]_2 ;\n input auto_pre_r_lcl_reg_0;\n input ordered_r_lcl_reg_0;\n input \\req_bank_r_lcl_reg[0] ;\n input [0:0]rb_hit_busies_r;\n input [0:0]idle_r_lcl_reg_2;\n input rstdiv0_sync_r1_reg_rep__20;\n input \\wtr_timer.wtr_cnt_r_reg[1] ;\n input \\order_q_r_reg[0]_0 ;\n input \\grant_r_reg[0] ;\n input init_calib_complete_reg_rep__6;\n input [1:0]cmd;\n input [1:0]\\grant_r_reg[1] ;\n input periodic_rd_ack_r_lcl_reg;\n input use_addr;\n input accept_internal_r;\n input periodic_rd_ack_r_lcl_reg_0;\n input periodic_rd_ack_r_lcl_reg_1;\n input pre_bm_end_r_reg;\n input bm_end_r1_reg_2;\n input [0:0]\\grant_r_reg[1]_0 ;\n input rtp_timer_ns1;\n input accept_r_reg;\n input rstdiv0_sync_r1_reg_rep__21;\n input [0:0]rb_hit_busy_r;\n input \\ras_timer_r_reg[1]_0 ;\n input bm_end_r1_reg_3;\n input bm_end_r1_reg_4;\n input req_wr_r_lcl_reg;\n input pre_passing_open_bank_r_0;\n input [0:0]\\req_row_r_lcl_reg[10] ;\n input \\grant_r_reg[0]_0 ;\n input act_wait_r_lcl_reg;\n input [0:0]mc_cs_n_ns;\n input head_r_lcl_reg_1;\n input \\grant_r_reg[0]_1 ;\n input \\ras_timer_r_reg[2]_1 ;\n input rd_wr_r_lcl_reg;\n input \\maint_controller.maint_wip_r_lcl_reg ;\n input periodic_rd_cntr_r_reg;\n input maint_req_r;\n input [1:0]\\grant_r_reg[1]_1 ;\n input demanded_prior_r_1;\n input demand_priority_r_2;\n input [14:0]\\app_addr_r1_reg[27] ;\n input req_bank_rdy_r_reg_0;\n input [2:0]\\app_addr_r1_reg[12] ;\n input [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n input [1:0]D;\n input [6:0]\\app_addr_r1_reg[9] ;\n input granted_col_r_reg_0;\n\n wire CLK;\n wire [1:0]D;\n wire [0:0]E;\n wire [1:0]Q;\n wire [0:0]SR;\n wire accept_internal_r;\n wire accept_r_reg;\n wire [0:0]act_this_rank_r;\n wire act_wait_ns;\n wire act_wait_r_lcl_reg;\n wire [2:0]\\app_addr_r1_reg[12] ;\n wire [14:0]\\app_addr_r1_reg[27] ;\n wire [6:0]\\app_addr_r1_reg[9] ;\n wire auto_pre_r_lcl_reg;\n wire auto_pre_r_lcl_reg_0;\n wire bank_compare0_n_12;\n wire bank_queue0_n_18;\n wire bank_state0_n_16;\n wire bank_state0_n_27;\n wire bm_end_r1_0;\n wire bm_end_r1_reg;\n wire bm_end_r1_reg_0;\n wire bm_end_r1_reg_1;\n wire bm_end_r1_reg_2;\n wire bm_end_r1_reg_3;\n wire bm_end_r1_reg_4;\n wire [1:0]cmd;\n wire [0:0]\\cmd_pipe_plus.mc_address_reg[10] ;\n wire [13:0]\\cmd_pipe_plus.mc_address_reg[14] ;\n wire [6:0]\\cmd_pipe_plus.mc_address_reg[24] ;\n wire \\cmd_pipe_plus.mc_address_reg[40] ;\n wire [2:0]\\cmd_pipe_plus.mc_bank_reg[2] ;\n wire [4:0]\\col_mux.col_data_buf_addr_r_reg[4] ;\n wire col_wait_r;\n wire demand_priority_ns;\n wire demand_priority_r;\n wire demand_priority_r_2;\n wire demanded_prior_r;\n wire demanded_prior_r_1;\n wire \\grant_r_reg[0] ;\n wire \\grant_r_reg[0]_0 ;\n wire \\grant_r_reg[0]_1 ;\n wire [1:0]\\grant_r_reg[1] ;\n wire [0:0]\\grant_r_reg[1]_0 ;\n wire [1:0]\\grant_r_reg[1]_1 ;\n wire granted_col_r_reg;\n wire granted_col_r_reg_0;\n wire granted_row_ns;\n wire granted_row_r_reg;\n wire head_r_lcl_reg;\n wire head_r_lcl_reg_0;\n wire head_r_lcl_reg_1;\n wire hi_priority;\n wire [0:0]idle_r_lcl_reg;\n wire idle_r_lcl_reg_0;\n wire idle_r_lcl_reg_1;\n wire [0:0]idle_r_lcl_reg_2;\n wire init_calib_complete_reg_rep__6;\n wire \\maint_controller.maint_wip_r_lcl_reg ;\n wire maint_req_r;\n wire [0:0]mc_cs_n_ns;\n wire [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n wire ofs_rdy_r;\n wire ofs_rdy_r0;\n wire \\order_q_r_reg[0] ;\n wire \\order_q_r_reg[0]_0 ;\n wire ordered_r_lcl_reg;\n wire ordered_r_lcl_reg_0;\n wire p_28_out;\n wire p_9_in;\n wire pass_open_bank_ns;\n wire pass_open_bank_r_lcl_reg;\n wire periodic_rd_ack_r_lcl_reg;\n wire periodic_rd_ack_r_lcl_reg_0;\n wire periodic_rd_ack_r_lcl_reg_1;\n wire periodic_rd_cntr_r_reg;\n wire periodic_rd_insert;\n wire \\pre_4_1_1T_arb.granted_pre_r_reg ;\n wire pre_bm_end_ns;\n wire pre_bm_end_r;\n wire pre_bm_end_r_reg;\n wire pre_passing_open_bank_ns;\n wire pre_passing_open_bank_r;\n wire pre_passing_open_bank_r_0;\n wire pre_wait_r;\n wire q_entry_r_4;\n wire \\q_entry_r_reg[0] ;\n wire \\q_entry_r_reg[0]_0 ;\n wire \\q_entry_r_reg[0]_1 ;\n wire \\q_entry_r_reg[0]_2 ;\n wire q_has_priority;\n wire q_has_priority_r_reg;\n wire q_has_priority_r_reg_0;\n wire q_has_rd;\n wire q_has_rd_r_reg;\n wire [2:0]ras_timer_passed_ns;\n wire \\ras_timer_r_reg[0] ;\n wire \\ras_timer_r_reg[1] ;\n wire \\ras_timer_r_reg[1]_0 ;\n wire \\ras_timer_r_reg[2] ;\n wire \\ras_timer_r_reg[2]_0 ;\n wire \\ras_timer_r_reg[2]_1 ;\n wire ras_timer_zero_r;\n wire [2:0]ras_timer_zero_r_reg;\n wire \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ;\n wire \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ;\n wire rb_hit_busies_ns;\n wire [0:0]rb_hit_busies_r;\n wire [0:0]rb_hit_busy_r;\n wire \\rcd_timer_gt_2.rcd_timer_r_reg[0] ;\n wire [0:0]rd_this_rank_r;\n wire \\rd_this_rank_r_reg[0] ;\n wire rd_wr_ns;\n wire rd_wr_r_lcl_reg;\n wire \\req_bank_r_lcl_reg[0] ;\n wire req_bank_rdy_ns_1;\n wire req_bank_rdy_r;\n wire req_bank_rdy_r_reg;\n wire req_bank_rdy_r_reg_0;\n wire [0:0]req_periodic_rd_r;\n wire req_priority_r;\n wire [25:25]req_row_r;\n wire [0:0]\\req_row_r_lcl_reg[10] ;\n wire req_wr_r_lcl_reg;\n wire \\rnk_config_strobe_r_reg[0] ;\n wire [0:0]row_cmd_wr;\n wire row_hit_r_0;\n wire \\rp_timer.rp_timer_r_reg[1] ;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire rtp_timer_ns1;\n wire set_order_q;\n wire start_wtp_timer0;\n wire tail_r_3;\n wire use_addr;\n wire wait_for_maint_ns;\n wire wait_for_maint_r_lcl_reg;\n wire [0:0]wr_this_rank_r;\n wire \\wtr_timer.wtr_cnt_r_reg[1] ;\n\n ddr3_ifmig_7series_v4_0_bank_compare bank_compare0\n (.CLK(CLK),\n .D(D),\n .Q(Q),\n .accept_r_reg(accept_r_reg),\n .act_wait_r_lcl_reg(row_cmd_wr),\n .act_wait_r_lcl_reg_0(act_wait_r_lcl_reg),\n .\\app_addr_r1_reg[12] (\\app_addr_r1_reg[12] ),\n .\\app_addr_r1_reg[27] (\\app_addr_r1_reg[27] ),\n .\\app_addr_r1_reg[9] (\\app_addr_r1_reg[9] ),\n .bm_end_r1_reg(bm_end_r1_reg),\n .cmd(cmd),\n .\\cmd_pipe_plus.mc_address_reg[14] ({\\cmd_pipe_plus.mc_address_reg[14] [13:10],req_row_r,\\cmd_pipe_plus.mc_address_reg[14] [9:0]}),\n .\\cmd_pipe_plus.mc_address_reg[24] (\\cmd_pipe_plus.mc_address_reg[24] ),\n .\\cmd_pipe_plus.mc_address_reg[40] (\\cmd_pipe_plus.mc_address_reg[40] ),\n .\\cmd_pipe_plus.mc_bank_reg[2] (\\cmd_pipe_plus.mc_bank_reg[2] ),\n .\\col_mux.col_data_buf_addr_r_reg[4] (\\col_mux.col_data_buf_addr_r_reg[4] ),\n .\\grant_r_reg[1] (\\grant_r_reg[1] [1]),\n .\\grant_r_reg[1]_0 (\\grant_r_reg[1]_1 ),\n .hi_priority(hi_priority),\n .idle_r_lcl_reg(idle_r_lcl_reg),\n .idle_r_lcl_reg_0(E),\n .\\maint_controller.maint_wip_r_lcl_reg (\\maint_controller.maint_wip_r_lcl_reg ),\n .maint_req_r(maint_req_r),\n .\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),\n .p_28_out(p_28_out),\n .pass_open_bank_ns(pass_open_bank_ns),\n .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg),\n .pass_open_bank_r_lcl_reg_0(bm_end_r1_reg_1),\n .periodic_rd_cntr_r_reg(periodic_rd_cntr_r_reg),\n .periodic_rd_insert(periodic_rd_insert),\n .pre_bm_end_r(pre_bm_end_r),\n .pre_bm_end_r_reg(pre_bm_end_r_reg),\n .pre_wait_r(pre_wait_r),\n .\\q_entry_r_reg[0] (\\q_entry_r_reg[0] ),\n .q_has_priority_r_reg(q_has_priority_r_reg),\n .\\ras_timer_r_reg[2] (\\ras_timer_r_reg[2] ),\n .ras_timer_zero_r_reg(bank_compare0_n_12),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ),\n .rb_hit_busy_r(rb_hit_busy_r),\n .\\rd_this_rank_r_reg[0] (\\rd_this_rank_r_reg[0] ),\n .rd_wr_ns(rd_wr_ns),\n .req_periodic_rd_r(req_periodic_rd_r),\n .req_priority_r(req_priority_r),\n .\\req_row_r_lcl_reg[10]_0 (\\req_row_r_lcl_reg[10] ),\n .row_hit_r_0(row_hit_r_0),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .start_wtp_timer0(start_wtp_timer0),\n .tail_r_3(tail_r_3),\n .wait_for_maint_r_lcl_reg(wait_for_maint_r_lcl_reg));\n ddr3_ifmig_7series_v4_0_bank_queue__parameterized0 bank_queue0\n (.CLK(CLK),\n .D(ras_timer_passed_ns),\n .SR(SR),\n .accept_internal_r(accept_internal_r),\n .act_wait_ns(act_wait_ns),\n .act_wait_r_lcl_reg(bank_queue0_n_18),\n .act_wait_r_lcl_reg_0(row_cmd_wr),\n .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_0),\n .bm_end_r1_reg(bm_end_r1_reg_1),\n .bm_end_r1_reg_0(bm_end_r1_reg_0),\n .bm_end_r1_reg_1(bm_end_r1_reg_2),\n .bm_end_r1_reg_2(bm_end_r1_reg_3),\n .bm_end_r1_reg_3(\\ras_timer_r_reg[1] ),\n .bm_end_r1_reg_4(bm_end_r1_reg_4),\n .cmd(cmd[0]),\n .col_wait_r(col_wait_r),\n .col_wait_r_reg(bank_state0_n_16),\n .demand_priority_ns(demand_priority_ns),\n .demand_priority_r_reg(bank_state0_n_27),\n .\\grant_r_reg[0] (\\grant_r_reg[0] ),\n .\\grant_r_reg[0]_0 (\\grant_r_reg[0]_1 ),\n .\\grant_r_reg[1] (\\grant_r_reg[1] [1]),\n .\\grant_r_reg[1]_0 (\\grant_r_reg[1]_0 ),\n .granted_col_r_reg(granted_col_r_reg),\n .granted_row_ns(granted_row_ns),\n .granted_row_r_reg(granted_row_r_reg),\n .head_r_lcl_reg_0(head_r_lcl_reg),\n .head_r_lcl_reg_1(head_r_lcl_reg_0),\n .head_r_lcl_reg_2(head_r_lcl_reg_1),\n .idle_r_lcl_reg_0(idle_r_lcl_reg),\n .idle_r_lcl_reg_1(idle_r_lcl_reg_0),\n .idle_r_lcl_reg_2(idle_r_lcl_reg_1),\n .idle_r_lcl_reg_3(idle_r_lcl_reg_2),\n .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6),\n .\\order_q_r_reg[0]_0 (\\order_q_r_reg[0] ),\n .\\order_q_r_reg[0]_1 (\\order_q_r_reg[0]_0 ),\n .ordered_r_lcl_reg_0(ordered_r_lcl_reg),\n .ordered_r_lcl_reg_1(ordered_r_lcl_reg_0),\n .p_9_in(p_9_in),\n .pass_open_bank_ns(pass_open_bank_ns),\n .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg),\n .periodic_rd_ack_r_lcl_reg_0(periodic_rd_ack_r_lcl_reg_0),\n .periodic_rd_ack_r_lcl_reg_1(periodic_rd_ack_r_lcl_reg_1),\n .periodic_rd_insert(periodic_rd_insert),\n .pre_bm_end_ns(pre_bm_end_ns),\n .pre_bm_end_r(pre_bm_end_r),\n .pre_bm_end_r_reg_0(pre_bm_end_r_reg),\n .pre_passing_open_bank_ns(pre_passing_open_bank_ns),\n .pre_passing_open_bank_r(pre_passing_open_bank_r),\n .pre_passing_open_bank_r_0(pre_passing_open_bank_r_0),\n .q_entry_r_4(q_entry_r_4),\n .\\q_entry_r_reg[0]_0 (\\q_entry_r_reg[0]_0 ),\n .\\q_entry_r_reg[0]_1 (\\q_entry_r_reg[0]_1 ),\n .\\q_entry_r_reg[0]_2 (\\q_entry_r_reg[0]_2 ),\n .q_has_priority(q_has_priority),\n .q_has_priority_r_reg_0(q_has_priority_r_reg_0),\n .q_has_rd(q_has_rd),\n .q_has_rd_r_reg_0(q_has_rd_r_reg),\n .\\ras_timer_r_reg[1] (\\ras_timer_r_reg[1]_0 ),\n .\\ras_timer_r_reg[2] (\\ras_timer_r_reg[2]_0 ),\n .ras_timer_zero_r(ras_timer_zero_r),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ),\n .rb_hit_busies_ns(rb_hit_busies_ns),\n .rb_hit_busies_r(rb_hit_busies_r),\n .rb_hit_busy_r(rb_hit_busy_r),\n .rb_hit_busy_r_reg(\\q_entry_r_reg[0] ),\n .rb_hit_busy_r_reg_0(q_has_priority_r_reg),\n .rd_wr_ns(rd_wr_ns),\n .rd_wr_r_lcl_reg(\\rd_this_rank_r_reg[0] ),\n .rd_wr_r_lcl_reg_0(\\ras_timer_r_reg[0] ),\n .rd_wr_r_lcl_reg_1(rd_wr_r_lcl_reg),\n .\\req_bank_r_lcl_reg[0] (\\req_bank_r_lcl_reg[0] ),\n .req_bank_rdy_r_reg(req_bank_rdy_r_reg),\n .\\req_data_buf_addr_r_reg[4] (E),\n .req_priority_r(req_priority_r),\n .req_wr_r_lcl_reg(pass_open_bank_r_lcl_reg),\n .req_wr_r_lcl_reg_0(bm_end_r1_reg),\n .req_wr_r_lcl_reg_1(req_wr_r_lcl_reg),\n .\\rp_timer.rp_timer_r_reg[1] (\\rp_timer.rp_timer_r_reg[1] ),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .set_order_q(set_order_q),\n .tail_r_3(tail_r_3),\n .use_addr(use_addr),\n .wait_for_maint_ns(wait_for_maint_ns),\n .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg),\n .\\wtr_timer.wtr_cnt_r_reg[1] (\\wtr_timer.wtr_cnt_r_reg[1] ));\n ddr3_ifmig_7series_v4_0_bank_state__parameterized0 bank_state0\n (.CLK(CLK),\n .D(ras_timer_passed_ns),\n .Q(ras_timer_zero_r_reg),\n .SR(SR),\n .accept_r_reg(accept_r_reg),\n .act_this_rank_r(act_this_rank_r),\n .\\act_this_rank_r_reg[0]_0 (row_cmd_wr),\n .act_wait_ns(act_wait_ns),\n .act_wait_r_lcl_reg_0(act_wait_r_lcl_reg),\n .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg),\n .auto_pre_r_lcl_reg_0(\\rp_timer.rp_timer_r_reg[1] ),\n .bm_end_r1_0(bm_end_r1_0),\n .bm_end_r1_reg_0(bm_end_r1_reg_2),\n .\\cmd_pipe_plus.mc_address_reg[10] (\\cmd_pipe_plus.mc_address_reg[10] ),\n .col_wait_r(col_wait_r),\n .demand_priority_ns(demand_priority_ns),\n .demand_priority_r_2(demand_priority_r_2),\n .demand_priority_r_reg_0(bank_state0_n_16),\n .demand_priority_r_reg_1(bank_state0_n_27),\n .demanded_prior_r(demanded_prior_r),\n .demanded_prior_r_1(demanded_prior_r_1),\n .demanded_prior_r_reg_0(demand_priority_r),\n .\\grant_r_reg[0] (\\grant_r_reg[0]_0 ),\n .\\grant_r_reg[1] (\\grant_r_reg[1] ),\n .\\grant_r_reg[1]_0 (\\grant_r_reg[1]_0 ),\n .\\grant_r_reg[1]_1 (\\grant_r_reg[1]_1 [1]),\n .granted_col_r_reg(granted_col_r_reg_0),\n .mc_cs_n_ns(mc_cs_n_ns),\n .ofs_rdy_r(ofs_rdy_r),\n .ofs_rdy_r0(ofs_rdy_r0),\n .\\order_q_r_reg[0] (req_bank_rdy_r_reg),\n .pass_open_bank_ns(pass_open_bank_ns),\n .pass_open_bank_r_lcl_reg(bm_end_r1_reg_1),\n .\\pre_4_1_1T_arb.granted_pre_r_reg (\\pre_4_1_1T_arb.granted_pre_r_reg ),\n .pre_bm_end_ns(pre_bm_end_ns),\n .pre_bm_end_r_reg(bm_end_r1_reg_0),\n .pre_passing_open_bank_ns(pre_passing_open_bank_ns),\n .pre_passing_open_bank_r_reg(bank_queue0_n_18),\n .pre_wait_r(pre_wait_r),\n .q_has_rd(q_has_rd),\n .\\ras_timer_r_reg[0]_0 (\\ras_timer_r_reg[0] ),\n .\\ras_timer_r_reg[1]_0 (\\ras_timer_r_reg[1] ),\n .\\ras_timer_r_reg[2]_0 (\\ras_timer_r_reg[2]_0 ),\n .\\ras_timer_r_reg[2]_1 (\\ras_timer_r_reg[2]_1 ),\n .ras_timer_zero_r(ras_timer_zero_r),\n .\\rcd_timer_gt_2.rcd_timer_r_reg[0]_0 (\\rcd_timer_gt_2.rcd_timer_r_reg[0] ),\n .rd_this_rank_r(rd_this_rank_r),\n .rd_wr_r_lcl_reg(\\rd_this_rank_r_reg[0] ),\n .rd_wr_r_lcl_reg_0(bank_compare0_n_12),\n .rd_wr_r_lcl_reg_1(rd_wr_r_lcl_reg),\n .req_bank_rdy_ns_1(req_bank_rdy_ns_1),\n .req_bank_rdy_r(req_bank_rdy_r),\n .req_bank_rdy_r_reg_0(req_bank_rdy_r_reg_0),\n .\\req_row_r_lcl_reg[10] (req_row_r),\n .\\req_row_r_lcl_reg[10]_0 (\\req_row_r_lcl_reg[10] ),\n .req_wr_r_lcl_reg(bm_end_r1_reg),\n .\\rnk_config_strobe_r_reg[0] (\\rnk_config_strobe_r_reg[0] ),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .rtp_timer_ns1(rtp_timer_ns1),\n .start_wtp_timer0(start_wtp_timer0),\n .tail_r_3(tail_r_3),\n .wr_this_rank_r(wr_this_rank_r));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_bank_common\" *) \nmodule ddr3_ifmig_7series_v4_0_bank_common\n (\\maint_controller.maint_hit_busies_r_reg[0]_0 ,\n insert_maint_r1_lcl_reg,\n accept_internal_r,\n was_wr_reg_0,\n head_r_lcl_reg,\n accept_ns,\n was_wr,\n req_periodic_rd_r_lcl_reg,\n wait_for_maint_ns,\n wait_for_maint_r_lcl_reg,\n D,\n wait_for_maint_ns_0,\n wait_for_maint_r_lcl_reg_0,\n \\req_cmd_r_reg[1] ,\n periodic_rd_insert,\n head_r_lcl_reg_0,\n pass_open_bank_r_lcl_reg,\n q_has_rd_r_reg,\n q_has_priority_r_reg,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 ,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_1 ,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ,\n CLK,\n p_9_in,\n maint_srx_r,\n SR,\n \\periodic_read_request.periodic_rd_r_lcl_reg ,\n maint_req_r,\n rstdiv0_sync_r1_reg_rep__21,\n wait_for_maint_r_2,\n idle_r_lcl_reg,\n idle_r_lcl_reg_0,\n init_calib_complete_reg_rep__6,\n periodic_rd_r,\n cmd,\n Q,\n \\maint_controller.maint_wip_r_lcl_reg_0 ,\n clear_req,\n use_addr,\n head_r,\n E,\n wait_for_maint_r,\n \\req_cmd_r_reg[1]_0 ,\n req_wr_r_lcl_reg,\n idle_r,\n rb_hit_busy_r_reg,\n rb_hit_busy_r,\n \\generate_maint_cmds.insert_maint_r_lcl_reg_0 ,\n \\maintenance_request.maint_zq_r_lcl_reg ,\n \\generate_maint_cmds.insert_maint_r_lcl_reg_1 ,\n p_52_out,\n rstdiv0_sync_r1_reg_rep__20,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 );\n output \\maint_controller.maint_hit_busies_r_reg[0]_0 ;\n output insert_maint_r1_lcl_reg;\n output accept_internal_r;\n output was_wr_reg_0;\n output head_r_lcl_reg;\n output accept_ns;\n output was_wr;\n output req_periodic_rd_r_lcl_reg;\n output wait_for_maint_ns;\n output wait_for_maint_r_lcl_reg;\n output [1:0]D;\n output wait_for_maint_ns_0;\n output wait_for_maint_r_lcl_reg_0;\n output [1:0]\\req_cmd_r_reg[1] ;\n output periodic_rd_insert;\n output head_r_lcl_reg_0;\n output pass_open_bank_r_lcl_reg;\n output q_has_rd_r_reg;\n output q_has_priority_r_reg;\n output [2:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 ;\n output \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_1 ;\n output [0:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ;\n input CLK;\n input p_9_in;\n input maint_srx_r;\n input [0:0]SR;\n input \\periodic_read_request.periodic_rd_r_lcl_reg ;\n input maint_req_r;\n input rstdiv0_sync_r1_reg_rep__21;\n input wait_for_maint_r_2;\n input [0:0]idle_r_lcl_reg;\n input [0:0]idle_r_lcl_reg_0;\n input init_calib_complete_reg_rep__6;\n input periodic_rd_r;\n input [1:0]cmd;\n input [1:0]Q;\n input \\maint_controller.maint_wip_r_lcl_reg_0 ;\n input clear_req;\n input use_addr;\n input [1:0]head_r;\n input [0:0]E;\n input wait_for_maint_r;\n input [1:0]\\req_cmd_r_reg[1]_0 ;\n input req_wr_r_lcl_reg;\n input [0:0]idle_r;\n input [0:0]rb_hit_busy_r_reg;\n input [0:0]rb_hit_busy_r;\n input \\generate_maint_cmds.insert_maint_r_lcl_reg_0 ;\n input \\maintenance_request.maint_zq_r_lcl_reg ;\n input \\generate_maint_cmds.insert_maint_r_lcl_reg_1 ;\n input p_52_out;\n input rstdiv0_sync_r1_reg_rep__20;\n input [2:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 ;\n\n wire CLK;\n wire [1:0]D;\n wire [0:0]E;\n wire [1:0]Q;\n wire [0:0]SR;\n wire accept_internal_r;\n wire accept_ns;\n wire clear_req;\n wire [1:0]cmd;\n wire \\generate_maint_cmds.insert_maint_r_lcl_reg_0 ;\n wire \\generate_maint_cmds.insert_maint_r_lcl_reg_1 ;\n wire [1:0]head_r;\n wire head_r_lcl_reg;\n wire head_r_lcl_reg_0;\n wire [0:0]idle_r;\n wire [0:0]idle_r_lcl_reg;\n wire [0:0]idle_r_lcl_reg_0;\n wire init_calib_complete_reg_rep__6;\n wire insert_maint_ns;\n wire insert_maint_r1_lcl_reg;\n wire \\maint_controller.maint_hit_busies_r_reg[0]_0 ;\n wire \\maint_controller.maint_wip_r_lcl_i_2_n_0 ;\n wire \\maint_controller.maint_wip_r_lcl_reg_0 ;\n wire [1:0]maint_hit_busies_ns;\n wire [1:0]maint_hit_busies_r;\n wire maint_rdy;\n wire maint_rdy_r1;\n wire maint_req_r;\n wire maint_srx_r;\n wire maint_srx_r1;\n wire maint_wip_ns;\n wire \\maintenance_request.maint_zq_r_lcl_reg ;\n wire p_52_out;\n wire p_9_in;\n wire pass_open_bank_r_lcl_reg;\n wire periodic_rd_ack_ns;\n wire periodic_rd_insert;\n wire periodic_rd_r;\n wire \\periodic_read_request.periodic_rd_r_lcl_reg ;\n wire q_has_priority_r_reg;\n wire q_has_rd_r_reg;\n wire [0:0]rb_hit_busy_r;\n wire [0:0]rb_hit_busy_r_reg;\n wire [1:0]\\req_cmd_r_reg[1] ;\n wire [1:0]\\req_cmd_r_reg[1]_0 ;\n wire req_periodic_rd_r_lcl_reg;\n wire req_wr_r_lcl_reg;\n wire \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3_n_0 ;\n wire [0:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ;\n wire [2:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 ;\n wire [2:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 ;\n wire \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_1 ;\n wire [7:2]rfc_zq_xsdll_timer_ns;\n wire [7:2]rfc_zq_xsdll_timer_r;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire use_addr;\n wire wait_for_maint_ns;\n wire wait_for_maint_ns_0;\n wire wait_for_maint_r;\n wire wait_for_maint_r_2;\n wire wait_for_maint_r_lcl_reg;\n wire wait_for_maint_r_lcl_reg_0;\n wire was_wr;\n wire was_wr0;\n wire was_wr_reg_0;\n\n FDRE #(\n .INIT(1'b0)) \n accept_internal_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(p_9_in),\n .Q(accept_internal_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hE0000000E0E0E0E0)) \n accept_r_i_1\n (.I0(idle_r_lcl_reg),\n .I1(idle_r_lcl_reg_0),\n .I2(init_calib_complete_reg_rep__6),\n .I3(was_wr_reg_0),\n .I4(req_periodic_rd_r_lcl_reg),\n .I5(periodic_rd_r),\n .O(accept_ns));\n FDRE #(\n .INIT(1'b0)) \n accept_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(accept_ns),\n .Q(head_r_lcl_reg),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h444444444444444F)) \n \\generate_maint_cmds.insert_maint_r_lcl_i_1 \n (.I0(maint_srx_r1),\n .I1(maint_srx_r),\n .I2(maint_rdy_r1),\n .I3(maint_hit_busies_ns[1]),\n .I4(maint_hit_busies_ns[0]),\n .I5(\\maint_controller.maint_wip_r_lcl_reg_0 ),\n .O(insert_maint_ns));\n FDRE #(\n .INIT(1'b0)) \n \\generate_maint_cmds.insert_maint_r_lcl_reg \n (.C(CLK),\n .CE(1'b1),\n .D(insert_maint_ns),\n .Q(insert_maint_r1_lcl_reg),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1064\" *) \n LUT4 #(\n .INIT(16'h07FF)) \n i___11_i_1\n (.I0(use_addr),\n .I1(head_r_lcl_reg),\n .I2(was_wr_reg_0),\n .I3(rb_hit_busy_r_reg),\n .O(pass_open_bank_r_lcl_reg));\n LUT4 #(\n .INIT(16'hFFFE)) \n i___20_i_1\n (.I0(rfc_zq_xsdll_timer_r[3]),\n .I1(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [0]),\n .I2(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [1]),\n .I3(rfc_zq_xsdll_timer_r[2]),\n .O(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair1063\" *) \n LUT3 #(\n .INIT(8'h15)) \n i___35_i_2\n (.I0(was_wr_reg_0),\n .I1(head_r_lcl_reg),\n .I2(use_addr),\n .O(q_has_priority_r_reg));\n LUT5 #(\n .INIT(32'hE0000000)) \n i___4_i_1\n (.I0(was_wr_reg_0),\n .I1(use_addr),\n .I2(accept_internal_r),\n .I3(head_r[0]),\n .I4(idle_r),\n .O(wait_for_maint_r_lcl_reg_0));\n (* SOFT_HLUTNM = \"soft_lutpair1064\" *) \n LUT4 #(\n .INIT(16'h07FF)) \n i___4_i_2\n (.I0(use_addr),\n .I1(head_r_lcl_reg),\n .I2(was_wr_reg_0),\n .I3(rb_hit_busy_r),\n .O(q_has_rd_r_reg));\n (* SOFT_HLUTNM = \"soft_lutpair1063\" *) \n LUT5 #(\n .INIT(32'hF80707F8)) \n i___5_i_1\n (.I0(use_addr),\n .I1(head_r_lcl_reg),\n .I2(was_wr_reg_0),\n .I3(E),\n .I4(idle_r),\n .O(head_r_lcl_reg_0));\n LUT5 #(\n .INIT(32'hE0000000)) \n i___8_i_1\n (.I0(was_wr_reg_0),\n .I1(use_addr),\n .I2(accept_internal_r),\n .I3(head_r[1]),\n .I4(E),\n .O(wait_for_maint_r_lcl_reg));\n LUT6 #(\n .INIT(64'h888A8888888A888A)) \n \\maint_controller.maint_hit_busies_r[0]_i_1 \n (.I0(req_wr_r_lcl_reg),\n .I1(maint_hit_busies_r[0]),\n .I2(idle_r_lcl_reg),\n .I3(\\maint_controller.maint_hit_busies_r_reg[0]_0 ),\n .I4(req_periodic_rd_r_lcl_reg),\n .I5(maint_req_r),\n .O(maint_hit_busies_ns[0]));\n LUT6 #(\n .INIT(64'h4445444444454445)) \n \\maint_controller.maint_hit_busies_r[1]_i_1 \n (.I0(clear_req),\n .I1(maint_hit_busies_r[1]),\n .I2(idle_r_lcl_reg_0),\n .I3(\\maint_controller.maint_hit_busies_r_reg[0]_0 ),\n .I4(req_periodic_rd_r_lcl_reg),\n .I5(maint_req_r),\n .O(maint_hit_busies_ns[1]));\n FDRE #(\n .INIT(1'b0)) \n \\maint_controller.maint_hit_busies_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(maint_hit_busies_ns[0]),\n .Q(maint_hit_busies_r[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\maint_controller.maint_hit_busies_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(maint_hit_busies_ns[1]),\n .Q(maint_hit_busies_r[1]),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00005455)) \n \\maint_controller.maint_rdy_r1_i_1 \n (.I0(maint_hit_busies_ns[1]),\n .I1(p_52_out),\n .I2(rstdiv0_sync_r1_reg_rep__20),\n .I3(maint_hit_busies_r[0]),\n .I4(\\maint_controller.maint_wip_r_lcl_reg_0 ),\n .O(maint_rdy));\n FDRE #(\n .INIT(1'b0)) \n \\maint_controller.maint_rdy_r1_reg \n (.C(CLK),\n .CE(1'b1),\n .D(maint_rdy),\n .Q(maint_rdy_r1),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\maint_controller.maint_srx_r1_reg \n (.C(CLK),\n .CE(1'b1),\n .D(maint_srx_r),\n .Q(maint_srx_r1),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h000000000000FFBF)) \n \\maint_controller.maint_wip_r_lcl_i_1 \n (.I0(rfc_zq_xsdll_timer_r[2]),\n .I1(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [1]),\n .I2(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [0]),\n .I3(\\maint_controller.maint_wip_r_lcl_i_2_n_0 ),\n .I4(\\maint_controller.maint_wip_r_lcl_reg_0 ),\n .I5(rstdiv0_sync_r1_reg_rep__21),\n .O(maint_wip_ns));\n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n \\maint_controller.maint_wip_r_lcl_i_2 \n (.I0(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [2]),\n .I1(rfc_zq_xsdll_timer_r[5]),\n .I2(rfc_zq_xsdll_timer_r[7]),\n .I3(rfc_zq_xsdll_timer_r[3]),\n .I4(rfc_zq_xsdll_timer_r[6]),\n .O(\\maint_controller.maint_wip_r_lcl_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\maint_controller.maint_wip_r_lcl_reg \n (.C(CLK),\n .CE(1'b1),\n .D(maint_wip_ns),\n .Q(\\maint_controller.maint_hit_busies_r_reg[0]_0 ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00E0E0E000000000)) \n periodic_rd_ack_r_lcl_i_1\n (.I0(idle_r_lcl_reg),\n .I1(idle_r_lcl_reg_0),\n .I2(init_calib_complete_reg_rep__6),\n .I3(was_wr_reg_0),\n .I4(req_periodic_rd_r_lcl_reg),\n .I5(periodic_rd_r),\n .O(periodic_rd_ack_ns));\n FDRE #(\n .INIT(1'b0)) \n periodic_rd_ack_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(periodic_rd_ack_ns),\n .Q(was_wr_reg_0),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n periodic_rd_cntr_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\periodic_read_request.periodic_rd_r_lcl_reg ),\n .Q(req_periodic_rd_r_lcl_reg),\n .R(SR));\n LUT6 #(\n .INIT(64'hBFAAFFFFBFAA0000)) \n \\req_cmd_r[0]_i_1 \n (.I0(cmd[0]),\n .I1(was_wr_reg_0),\n .I2(req_periodic_rd_r_lcl_reg),\n .I3(periodic_rd_r),\n .I4(idle_r_lcl_reg_0),\n .I5(Q[0]),\n .O(D[0]));\n LUT6 #(\n .INIT(64'hBFAAFFFFBFAA0000)) \n \\req_cmd_r[0]_i_1__0 \n (.I0(cmd[0]),\n .I1(was_wr_reg_0),\n .I2(req_periodic_rd_r_lcl_reg),\n .I3(periodic_rd_r),\n .I4(idle_r_lcl_reg),\n .I5(\\req_cmd_r_reg[1]_0 [0]),\n .O(\\req_cmd_r_reg[1] [0]));\n LUT6 #(\n .INIT(64'h80AAFFFF80AA0000)) \n \\req_cmd_r[1]_i_1 \n (.I0(cmd[1]),\n .I1(was_wr_reg_0),\n .I2(req_periodic_rd_r_lcl_reg),\n .I3(periodic_rd_r),\n .I4(idle_r_lcl_reg_0),\n .I5(Q[1]),\n .O(D[1]));\n LUT6 #(\n .INIT(64'h80AAFFFF80AA0000)) \n \\req_cmd_r[1]_i_1__0 \n (.I0(cmd[1]),\n .I1(was_wr_reg_0),\n .I2(req_periodic_rd_r_lcl_reg),\n .I3(periodic_rd_r),\n .I4(idle_r_lcl_reg),\n .I5(\\req_cmd_r_reg[1]_0 [1]),\n .O(\\req_cmd_r_reg[1] [1]));\n (* SOFT_HLUTNM = \"soft_lutpair1065\" *) \n LUT3 #(\n .INIT(8'h2A)) \n req_periodic_rd_r_lcl_i_1\n (.I0(periodic_rd_r),\n .I1(req_periodic_rd_r_lcl_reg),\n .I2(was_wr_reg_0),\n .O(periodic_rd_insert));\n LUT5 #(\n .INIT(32'h11100001)) \n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[2]_i_1 \n (.I0(insert_maint_r1_lcl_reg),\n .I1(rstdiv0_sync_r1_reg_rep__21),\n .I2(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [0]),\n .I3(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [1]),\n .I4(rfc_zq_xsdll_timer_r[2]),\n .O(rfc_zq_xsdll_timer_ns[2]));\n LUT6 #(\n .INIT(64'hEEEEEEEBAAAAAAAA)) \n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_1 \n (.I0(\\maintenance_request.maint_zq_r_lcl_reg ),\n .I1(rfc_zq_xsdll_timer_r[3]),\n .I2(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [0]),\n .I3(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [1]),\n .I4(rfc_zq_xsdll_timer_r[2]),\n .I5(\\generate_maint_cmds.insert_maint_r_lcl_reg_1 ),\n .O(rfc_zq_xsdll_timer_ns[3]));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAAEEEB)) \n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[5]_i_1 \n (.I0(\\maintenance_request.maint_zq_r_lcl_reg ),\n .I1(rfc_zq_xsdll_timer_r[5]),\n .I2(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_1 ),\n .I3(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [2]),\n .I4(rstdiv0_sync_r1_reg_rep__21),\n .I5(insert_maint_r1_lcl_reg),\n .O(rfc_zq_xsdll_timer_ns[5]));\n LUT6 #(\n .INIT(64'h1111111000000001)) \n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_1 \n (.I0(insert_maint_r1_lcl_reg),\n .I1(rstdiv0_sync_r1_reg_rep__21),\n .I2(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [2]),\n .I3(rfc_zq_xsdll_timer_r[5]),\n .I4(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_1 ),\n .I5(rfc_zq_xsdll_timer_r[6]),\n .O(rfc_zq_xsdll_timer_ns[6]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1 \n (.I0(\\maint_controller.maint_wip_r_lcl_i_2_n_0 ),\n .I1(rstdiv0_sync_r1_reg_rep__21),\n .I2(insert_maint_r1_lcl_reg),\n .I3(rfc_zq_xsdll_timer_r[2]),\n .I4(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [1]),\n .I5(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [0]),\n .O(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF02020200)) \n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_2 \n (.I0(rfc_zq_xsdll_timer_r[7]),\n .I1(insert_maint_r1_lcl_reg),\n .I2(rstdiv0_sync_r1_reg_rep__21),\n .I3(rfc_zq_xsdll_timer_r[6]),\n .I4(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3_n_0 ),\n .I5(\\generate_maint_cmds.insert_maint_r_lcl_reg_0 ),\n .O(rfc_zq_xsdll_timer_ns[7]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3 \n (.I0(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [2]),\n .I1(rfc_zq_xsdll_timer_r[5]),\n .I2(rfc_zq_xsdll_timer_r[2]),\n .I3(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [1]),\n .I4(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [0]),\n .I5(rfc_zq_xsdll_timer_r[3]),\n .O(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] \n (.C(CLK),\n .CE(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ),\n .D(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 [0]),\n .Q(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] \n (.C(CLK),\n .CE(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ),\n .D(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 [1]),\n .Q(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[2] \n (.C(CLK),\n .CE(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ),\n .D(rfc_zq_xsdll_timer_ns[2]),\n .Q(rfc_zq_xsdll_timer_r[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] \n (.C(CLK),\n .CE(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ),\n .D(rfc_zq_xsdll_timer_ns[3]),\n .Q(rfc_zq_xsdll_timer_r[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] \n (.C(CLK),\n .CE(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ),\n .D(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 [2]),\n .Q(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 [2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] \n (.C(CLK),\n .CE(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ),\n .D(rfc_zq_xsdll_timer_ns[5]),\n .Q(rfc_zq_xsdll_timer_r[5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6] \n (.C(CLK),\n .CE(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ),\n .D(rfc_zq_xsdll_timer_ns[6]),\n .Q(rfc_zq_xsdll_timer_r[6]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] \n (.C(CLK),\n .CE(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ),\n .D(rfc_zq_xsdll_timer_ns[7]),\n .Q(rfc_zq_xsdll_timer_r[7]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00BA00BA00BA0000)) \n wait_for_maint_r_lcl_i_1\n (.I0(\\maint_controller.maint_hit_busies_r_reg[0]_0 ),\n .I1(req_periodic_rd_r_lcl_reg),\n .I2(maint_req_r),\n .I3(rstdiv0_sync_r1_reg_rep__21),\n .I4(wait_for_maint_r_lcl_reg),\n .I5(wait_for_maint_r_2),\n .O(wait_for_maint_ns));\n LUT6 #(\n .INIT(64'h00BA00BA00BA0000)) \n wait_for_maint_r_lcl_i_1__0\n (.I0(\\maint_controller.maint_hit_busies_r_reg[0]_0 ),\n .I1(req_periodic_rd_r_lcl_reg),\n .I2(maint_req_r),\n .I3(rstdiv0_sync_r1_reg_rep__21),\n .I4(wait_for_maint_r_lcl_reg_0),\n .I5(wait_for_maint_r),\n .O(wait_for_maint_ns_0));\n (* SOFT_HLUTNM = \"soft_lutpair1065\" *) \n LUT3 #(\n .INIT(8'h8A)) \n was_wr_i_1\n (.I0(cmd[0]),\n .I1(was_wr_reg_0),\n .I2(periodic_rd_r),\n .O(was_wr0));\n FDRE #(\n .INIT(1'b0)) \n was_wr_reg\n (.C(CLK),\n .CE(1'b1),\n .D(was_wr0),\n .Q(was_wr),\n .R(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_bank_compare\" *) \nmodule ddr3_ifmig_7series_v4_0_bank_compare\n (q_has_priority_r_reg,\n \\rd_this_rank_r_reg[0] ,\n req_periodic_rd_r,\n bm_end_r1_reg,\n req_priority_r,\n row_hit_r_0,\n Q,\n pass_open_bank_ns,\n pass_open_bank_r_lcl_reg,\n \\ras_timer_r_reg[2] ,\n \\q_entry_r_reg[0] ,\n ras_timer_zero_r_reg,\n start_wtp_timer0,\n \\cmd_pipe_plus.mc_address_reg[14] ,\n \\cmd_pipe_plus.mc_address_reg[40] ,\n \\cmd_pipe_plus.mc_bank_reg[2] ,\n \\col_mux.col_data_buf_addr_r_reg[4] ,\n \\cmd_pipe_plus.mc_address_reg[24] ,\n p_28_out,\n CLK,\n rd_wr_ns,\n idle_r_lcl_reg,\n periodic_rd_insert,\n hi_priority,\n cmd,\n accept_r_reg,\n tail_r_3,\n pre_wait_r,\n pass_open_bank_r_lcl_reg_0,\n rstdiv0_sync_r1_reg_rep__21,\n \\grant_r_reg[1] ,\n pre_bm_end_r,\n rb_hit_busy_r,\n pre_bm_end_r_reg,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ,\n \\maint_controller.maint_wip_r_lcl_reg ,\n periodic_rd_cntr_r_reg,\n maint_req_r,\n wait_for_maint_r_lcl_reg,\n \\app_addr_r1_reg[27] ,\n act_wait_r_lcl_reg,\n \\grant_r_reg[1]_0 ,\n act_wait_r_lcl_reg_0,\n \\req_row_r_lcl_reg[10]_0 ,\n \\app_addr_r1_reg[12] ,\n idle_r_lcl_reg_0,\n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ,\n D,\n \\app_addr_r1_reg[9] );\n output q_has_priority_r_reg;\n output \\rd_this_rank_r_reg[0] ;\n output [0:0]req_periodic_rd_r;\n output bm_end_r1_reg;\n output req_priority_r;\n output row_hit_r_0;\n output [1:0]Q;\n output pass_open_bank_ns;\n output pass_open_bank_r_lcl_reg;\n output \\ras_timer_r_reg[2] ;\n output \\q_entry_r_reg[0] ;\n output ras_timer_zero_r_reg;\n output start_wtp_timer0;\n output [14:0]\\cmd_pipe_plus.mc_address_reg[14] ;\n output \\cmd_pipe_plus.mc_address_reg[40] ;\n output [2:0]\\cmd_pipe_plus.mc_bank_reg[2] ;\n output [4:0]\\col_mux.col_data_buf_addr_r_reg[4] ;\n output [6:0]\\cmd_pipe_plus.mc_address_reg[24] ;\n input p_28_out;\n input CLK;\n input rd_wr_ns;\n input idle_r_lcl_reg;\n input periodic_rd_insert;\n input hi_priority;\n input [1:0]cmd;\n input accept_r_reg;\n input tail_r_3;\n input pre_wait_r;\n input pass_open_bank_r_lcl_reg_0;\n input rstdiv0_sync_r1_reg_rep__21;\n input [0:0]\\grant_r_reg[1] ;\n input pre_bm_end_r;\n input [0:0]rb_hit_busy_r;\n input pre_bm_end_r_reg;\n input \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ;\n input \\maint_controller.maint_wip_r_lcl_reg ;\n input periodic_rd_cntr_r_reg;\n input maint_req_r;\n input wait_for_maint_r_lcl_reg;\n input [14:0]\\app_addr_r1_reg[27] ;\n input act_wait_r_lcl_reg;\n input [1:0]\\grant_r_reg[1]_0 ;\n input act_wait_r_lcl_reg_0;\n input [0:0]\\req_row_r_lcl_reg[10]_0 ;\n input [2:0]\\app_addr_r1_reg[12] ;\n input idle_r_lcl_reg_0;\n input [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n input [1:0]D;\n input [6:0]\\app_addr_r1_reg[9] ;\n\n wire CLK;\n wire [1:0]D;\n wire [1:0]Q;\n wire accept_r_reg;\n wire act_wait_r_lcl_reg;\n wire act_wait_r_lcl_reg_0;\n wire [2:0]\\app_addr_r1_reg[12] ;\n wire [14:0]\\app_addr_r1_reg[27] ;\n wire [6:0]\\app_addr_r1_reg[9] ;\n wire bm_end_r1_reg;\n wire [1:0]cmd;\n wire [14:0]\\cmd_pipe_plus.mc_address_reg[14] ;\n wire [6:0]\\cmd_pipe_plus.mc_address_reg[24] ;\n wire \\cmd_pipe_plus.mc_address_reg[40] ;\n wire [2:0]\\cmd_pipe_plus.mc_bank_reg[2] ;\n wire [4:0]\\col_mux.col_data_buf_addr_r_reg[4] ;\n wire [0:0]\\grant_r_reg[1] ;\n wire [1:0]\\grant_r_reg[1]_0 ;\n wire hi_priority;\n wire idle_r_lcl_reg;\n wire idle_r_lcl_reg_0;\n wire \\maint_controller.maint_wip_r_lcl_reg ;\n wire maint_req_r;\n wire [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n wire p_28_out;\n wire pass_open_bank_ns;\n wire pass_open_bank_r_lcl_i_2_n_0;\n wire pass_open_bank_r_lcl_reg;\n wire pass_open_bank_r_lcl_reg_0;\n wire periodic_rd_cntr_r_reg;\n wire periodic_rd_insert;\n wire pre_bm_end_r;\n wire pre_bm_end_r_reg;\n wire pre_wait_r;\n wire \\q_entry_r_reg[0] ;\n wire q_has_priority_r_reg;\n wire \\ras_timer_r_reg[2] ;\n wire ras_timer_zero_r_reg;\n wire \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ;\n wire [0:0]rb_hit_busy_r;\n wire \\rd_this_rank_r_reg[0] ;\n wire rd_wr_ns;\n wire [0:0]req_periodic_rd_r;\n wire req_priority_r;\n wire [0:0]\\req_row_r_lcl_reg[10]_0 ;\n wire req_wr_r_lcl0;\n wire row_hit_ns_carry__0_i_1__0_n_0;\n wire row_hit_ns_carry__0_n_3;\n wire row_hit_ns_carry_i_1__0_n_0;\n wire row_hit_ns_carry_i_2__0_n_0;\n wire row_hit_ns_carry_i_3__0_n_0;\n wire row_hit_ns_carry_i_4__0_n_0;\n wire row_hit_ns_carry_n_0;\n wire row_hit_ns_carry_n_1;\n wire row_hit_ns_carry_n_2;\n wire row_hit_ns_carry_n_3;\n wire row_hit_r_0;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire start_wtp_timer0;\n wire tail_r_3;\n wire wait_for_maint_r_lcl_reg;\n wire [3:0]NLW_row_hit_ns_carry_O_UNCONNECTED;\n wire [3:1]NLW_row_hit_ns_carry__0_CO_UNCONNECTED;\n wire [3:0]NLW_row_hit_ns_carry__0_O_UNCONNECTED;\n\n (* SOFT_HLUTNM = \"soft_lutpair1057\" *) \n LUT4 #(\n .INIT(16'h7000)) \n act_wait_r_lcl_i_4\n (.I0(bm_end_r1_reg),\n .I1(\\rd_this_rank_r_reg[0] ),\n .I2(pass_open_bank_r_lcl_reg_0),\n .I3(\\grant_r_reg[1] ),\n .O(\\ras_timer_r_reg[2] ));\n LUT6 #(\n .INIT(64'h8F80808080808080)) \n \\cmd_pipe_plus.mc_address[40]_i_1 \n (.I0(\\cmd_pipe_plus.mc_address_reg[14] [10]),\n .I1(act_wait_r_lcl_reg),\n .I2(\\grant_r_reg[1]_0 [1]),\n .I3(\\grant_r_reg[1]_0 [0]),\n .I4(act_wait_r_lcl_reg_0),\n .I5(\\req_row_r_lcl_reg[10]_0 ),\n .O(\\cmd_pipe_plus.mc_address_reg[40] ));\n LUT4 #(\n .INIT(16'h6999)) \n i___12_i_1\n (.I0(q_has_priority_r_reg),\n .I1(rb_hit_busy_r),\n .I2(pre_bm_end_r_reg),\n .I3(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ),\n .O(\\q_entry_r_reg[0] ));\n LUT6 #(\n .INIT(64'hFFFFFFFFBFAAAAAA)) \n i___13_i_2\n (.I0(rstdiv0_sync_r1_reg_rep__21),\n .I1(bm_end_r1_reg),\n .I2(\\rd_this_rank_r_reg[0] ),\n .I3(pass_open_bank_r_lcl_reg_0),\n .I4(\\grant_r_reg[1] ),\n .I5(pre_bm_end_r),\n .O(pass_open_bank_r_lcl_reg));\n LUT6 #(\n .INIT(64'h5555555500000400)) \n pass_open_bank_r_lcl_i_1\n (.I0(pass_open_bank_r_lcl_reg),\n .I1(pass_open_bank_r_lcl_i_2_n_0),\n .I2(accept_r_reg),\n .I3(tail_r_3),\n .I4(pre_wait_r),\n .I5(pass_open_bank_r_lcl_reg_0),\n .O(pass_open_bank_ns));\n LUT5 #(\n .INIT(32'hAAAA2022)) \n pass_open_bank_r_lcl_i_2\n (.I0(row_hit_r_0),\n .I1(\\maint_controller.maint_wip_r_lcl_reg ),\n .I2(periodic_rd_cntr_r_reg),\n .I3(maint_req_r),\n .I4(wait_for_maint_r_lcl_reg),\n .O(pass_open_bank_r_lcl_i_2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1057\" *) \n LUT2 #(\n .INIT(4'hB)) \n ras_timer_zero_r_i_2\n (.I0(\\rd_this_rank_r_reg[0] ),\n .I1(\\grant_r_reg[1] ),\n .O(ras_timer_zero_r_reg));\n FDRE #(\n .INIT(1'b0)) \n rb_hit_busy_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(p_28_out),\n .Q(q_has_priority_r_reg),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n rd_wr_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rd_wr_ns),\n .Q(\\rd_this_rank_r_reg[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_bank_r_lcl_reg[0] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[12] [0]),\n .Q(\\cmd_pipe_plus.mc_bank_reg[2] [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_bank_r_lcl_reg[1] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[12] [1]),\n .Q(\\cmd_pipe_plus.mc_bank_reg[2] [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_bank_r_lcl_reg[2] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[12] [2]),\n .Q(\\cmd_pipe_plus.mc_bank_reg[2] [2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_cmd_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(D[0]),\n .Q(Q[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_cmd_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(D[1]),\n .Q(Q[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[3] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[9] [0]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[4] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[9] [1]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[5] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[9] [2]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[6] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[9] [3]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[7] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[9] [4]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[8] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[9] [5]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[9] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[9] [6]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [6]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_data_buf_addr_r_reg[0] \n (.C(CLK),\n .CE(idle_r_lcl_reg_0),\n .D(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [0]),\n .Q(\\col_mux.col_data_buf_addr_r_reg[4] [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_data_buf_addr_r_reg[1] \n (.C(CLK),\n .CE(idle_r_lcl_reg_0),\n .D(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [1]),\n .Q(\\col_mux.col_data_buf_addr_r_reg[4] [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_data_buf_addr_r_reg[2] \n (.C(CLK),\n .CE(idle_r_lcl_reg_0),\n .D(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [2]),\n .Q(\\col_mux.col_data_buf_addr_r_reg[4] [2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_data_buf_addr_r_reg[3] \n (.C(CLK),\n .CE(idle_r_lcl_reg_0),\n .D(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [3]),\n .Q(\\col_mux.col_data_buf_addr_r_reg[4] [3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_data_buf_addr_r_reg[4] \n (.C(CLK),\n .CE(idle_r_lcl_reg_0),\n .D(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [4]),\n .Q(\\col_mux.col_data_buf_addr_r_reg[4] [4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n req_periodic_rd_r_lcl_reg\n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(periodic_rd_insert),\n .Q(req_periodic_rd_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n req_priority_r_reg\n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(hi_priority),\n .Q(req_priority_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_row_r_lcl_reg[0] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[27] [0]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_row_r_lcl_reg[10] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[27] [10]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [10]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_row_r_lcl_reg[11] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[27] [11]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [11]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_row_r_lcl_reg[12] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[27] [12]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [12]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_row_r_lcl_reg[13] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[27] [13]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [13]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_row_r_lcl_reg[14] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[27] [14]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [14]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_row_r_lcl_reg[1] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[27] [1]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_row_r_lcl_reg[2] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[27] [2]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_row_r_lcl_reg[3] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[27] [3]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_row_r_lcl_reg[4] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[27] [4]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_row_r_lcl_reg[5] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[27] [5]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_row_r_lcl_reg[6] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[27] [6]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [6]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_row_r_lcl_reg[7] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[27] [7]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [7]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_row_r_lcl_reg[8] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[27] [8]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [8]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_row_r_lcl_reg[9] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[27] [9]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [9]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00AFCCAF00AFFFAF)) \n req_wr_r_lcl_i_1\n (.I0(Q[1]),\n .I1(cmd[1]),\n .I2(Q[0]),\n .I3(idle_r_lcl_reg),\n .I4(periodic_rd_insert),\n .I5(cmd[0]),\n .O(req_wr_r_lcl0));\n FDRE #(\n .INIT(1'b0)) \n req_wr_r_lcl_reg\n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(req_wr_r_lcl0),\n .Q(bm_end_r1_reg),\n .R(1'b0));\n CARRY4 row_hit_ns_carry\n (.CI(1'b0),\n .CO({row_hit_ns_carry_n_0,row_hit_ns_carry_n_1,row_hit_ns_carry_n_2,row_hit_ns_carry_n_3}),\n .CYINIT(1'b1),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(NLW_row_hit_ns_carry_O_UNCONNECTED[3:0]),\n .S({row_hit_ns_carry_i_1__0_n_0,row_hit_ns_carry_i_2__0_n_0,row_hit_ns_carry_i_3__0_n_0,row_hit_ns_carry_i_4__0_n_0}));\n CARRY4 row_hit_ns_carry__0\n (.CI(row_hit_ns_carry_n_0),\n .CO({NLW_row_hit_ns_carry__0_CO_UNCONNECTED[3:1],row_hit_ns_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(NLW_row_hit_ns_carry__0_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,1'b0,row_hit_ns_carry__0_i_1__0_n_0}));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n row_hit_ns_carry__0_i_1__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[14] [14]),\n .I1(\\app_addr_r1_reg[27] [14]),\n .I2(\\cmd_pipe_plus.mc_address_reg[14] [13]),\n .I3(\\app_addr_r1_reg[27] [13]),\n .I4(\\app_addr_r1_reg[27] [12]),\n .I5(\\cmd_pipe_plus.mc_address_reg[14] [12]),\n .O(row_hit_ns_carry__0_i_1__0_n_0));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n row_hit_ns_carry_i_1__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[14] [11]),\n .I1(\\app_addr_r1_reg[27] [11]),\n .I2(\\cmd_pipe_plus.mc_address_reg[14] [10]),\n .I3(\\app_addr_r1_reg[27] [10]),\n .I4(\\app_addr_r1_reg[27] [9]),\n .I5(\\cmd_pipe_plus.mc_address_reg[14] [9]),\n .O(row_hit_ns_carry_i_1__0_n_0));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n row_hit_ns_carry_i_2__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[14] [8]),\n .I1(\\app_addr_r1_reg[27] [8]),\n .I2(\\cmd_pipe_plus.mc_address_reg[14] [6]),\n .I3(\\app_addr_r1_reg[27] [6]),\n .I4(\\app_addr_r1_reg[27] [7]),\n .I5(\\cmd_pipe_plus.mc_address_reg[14] [7]),\n .O(row_hit_ns_carry_i_2__0_n_0));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n row_hit_ns_carry_i_3__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[14] [5]),\n .I1(\\app_addr_r1_reg[27] [5]),\n .I2(\\cmd_pipe_plus.mc_address_reg[14] [3]),\n .I3(\\app_addr_r1_reg[27] [3]),\n .I4(\\app_addr_r1_reg[27] [4]),\n .I5(\\cmd_pipe_plus.mc_address_reg[14] [4]),\n .O(row_hit_ns_carry_i_3__0_n_0));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n row_hit_ns_carry_i_4__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[14] [2]),\n .I1(\\app_addr_r1_reg[27] [2]),\n .I2(\\cmd_pipe_plus.mc_address_reg[14] [0]),\n .I3(\\app_addr_r1_reg[27] [0]),\n .I4(\\app_addr_r1_reg[27] [1]),\n .I5(\\cmd_pipe_plus.mc_address_reg[14] [1]),\n .O(row_hit_ns_carry_i_4__0_n_0));\n FDRE #(\n .INIT(1'b0)) \n row_hit_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(row_hit_ns_carry__0_n_3),\n .Q(row_hit_r_0),\n .R(1'b0));\n LUT1 #(\n .INIT(2'h1)) \n \\wr_this_rank_r[0]_i_1__0 \n (.I0(\\rd_this_rank_r_reg[0] ),\n .O(start_wtp_timer0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_bank_compare\" *) \nmodule ddr3_ifmig_7series_v4_0_bank_compare_0\n (rb_hit_busy_r,\n \\rd_this_rank_r_reg[0] ,\n req_periodic_rd_r,\n bm_end_r1_reg,\n req_priority_r,\n row_hit_r,\n granted_col_ns,\n granted_col_r_reg,\n Q,\n act_wait_r_lcl_reg,\n start_wtp_timer0,\n req_bank_rdy_r_reg,\n req_bank_rdy_ns,\n demand_priority_r_reg,\n ras_timer_zero_r_reg,\n pass_open_bank_r_lcl_reg,\n \\cmd_pipe_plus.mc_address_reg[14] ,\n \\cmd_pipe_plus.mc_bank_reg[2] ,\n \\col_mux.col_data_buf_addr_r_reg[4] ,\n \\cmd_pipe_plus.mc_address_reg[24] ,\n p_67_out,\n CLK,\n rd_wr_ns,\n idle_r_lcl_reg,\n periodic_rd_insert,\n hi_priority,\n col_wait_r_reg,\n \\wtr_timer.wtr_cnt_r_reg[1] ,\n pre_passing_open_bank_r_reg,\n col_wait_r,\n \\grant_r_reg[0] ,\n cmd,\n pass_open_bank_r_lcl_reg_0,\n \\grant_r_reg[1] ,\n override_demand_r_reg,\n \\rnk_config_strobe_r_reg[0] ,\n \\order_q_r_reg[0] ,\n rd_wr_r_lcl_reg_0,\n req_wr_r_lcl_reg_0,\n \\maint_controller.maint_wip_r_lcl_reg ,\n periodic_rd_cntr_r_reg,\n maint_req_r,\n wait_for_maint_r_lcl_reg,\n \\app_addr_r1_reg[27] ,\n \\app_addr_r1_reg[12] ,\n idle_r_lcl_reg_0,\n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ,\n D,\n \\app_addr_r1_reg[9] );\n output [0:0]rb_hit_busy_r;\n output \\rd_this_rank_r_reg[0] ;\n output [0:0]req_periodic_rd_r;\n output bm_end_r1_reg;\n output req_priority_r;\n output row_hit_r;\n output granted_col_ns;\n output granted_col_r_reg;\n output [1:0]Q;\n output act_wait_r_lcl_reg;\n output start_wtp_timer0;\n output req_bank_rdy_r_reg;\n output req_bank_rdy_ns;\n output demand_priority_r_reg;\n output ras_timer_zero_r_reg;\n output pass_open_bank_r_lcl_reg;\n output [14:0]\\cmd_pipe_plus.mc_address_reg[14] ;\n output [2:0]\\cmd_pipe_plus.mc_bank_reg[2] ;\n output [4:0]\\col_mux.col_data_buf_addr_r_reg[4] ;\n output [6:0]\\cmd_pipe_plus.mc_address_reg[24] ;\n input p_67_out;\n input CLK;\n input rd_wr_ns;\n input idle_r_lcl_reg;\n input periodic_rd_insert;\n input hi_priority;\n input col_wait_r_reg;\n input \\wtr_timer.wtr_cnt_r_reg[1] ;\n input pre_passing_open_bank_r_reg;\n input col_wait_r;\n input \\grant_r_reg[0] ;\n input [1:0]cmd;\n input pass_open_bank_r_lcl_reg_0;\n input [1:0]\\grant_r_reg[1] ;\n input override_demand_r_reg;\n input \\rnk_config_strobe_r_reg[0] ;\n input \\order_q_r_reg[0] ;\n input rd_wr_r_lcl_reg_0;\n input req_wr_r_lcl_reg_0;\n input \\maint_controller.maint_wip_r_lcl_reg ;\n input periodic_rd_cntr_r_reg;\n input maint_req_r;\n input wait_for_maint_r_lcl_reg;\n input [14:0]\\app_addr_r1_reg[27] ;\n input [2:0]\\app_addr_r1_reg[12] ;\n input idle_r_lcl_reg_0;\n input [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n input [1:0]D;\n input [6:0]\\app_addr_r1_reg[9] ;\n\n wire CLK;\n wire [1:0]D;\n wire [1:0]Q;\n wire act_wait_r_lcl_reg;\n wire [2:0]\\app_addr_r1_reg[12] ;\n wire [14:0]\\app_addr_r1_reg[27] ;\n wire [6:0]\\app_addr_r1_reg[9] ;\n wire bm_end_r1_reg;\n wire [1:0]cmd;\n wire [14:0]\\cmd_pipe_plus.mc_address_reg[14] ;\n wire [6:0]\\cmd_pipe_plus.mc_address_reg[24] ;\n wire [2:0]\\cmd_pipe_plus.mc_bank_reg[2] ;\n wire [4:0]\\col_mux.col_data_buf_addr_r_reg[4] ;\n wire col_wait_r;\n wire col_wait_r_reg;\n wire demand_priority_r_reg;\n wire \\grant_r[1]_i_7_n_0 ;\n wire \\grant_r_reg[0] ;\n wire [1:0]\\grant_r_reg[1] ;\n wire granted_col_ns;\n wire granted_col_r_reg;\n wire hi_priority;\n wire idle_r_lcl_reg;\n wire idle_r_lcl_reg_0;\n wire \\maint_controller.maint_wip_r_lcl_reg ;\n wire maint_req_r;\n wire [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n wire \\order_q_r_reg[0] ;\n wire override_demand_r_reg;\n wire p_67_out;\n wire pass_open_bank_r_lcl_reg;\n wire pass_open_bank_r_lcl_reg_0;\n wire periodic_rd_cntr_r_reg;\n wire periodic_rd_insert;\n wire pre_passing_open_bank_r_reg;\n wire ras_timer_zero_r_reg;\n wire [0:0]rb_hit_busy_r;\n wire \\rd_this_rank_r_reg[0] ;\n wire rd_wr_ns;\n wire rd_wr_r_lcl_reg_0;\n wire req_bank_rdy_ns;\n wire req_bank_rdy_r_reg;\n wire [0:0]req_periodic_rd_r;\n wire req_priority_r;\n wire req_wr_r_lcl0;\n wire req_wr_r_lcl_reg_0;\n wire \\rnk_config_strobe_r_reg[0] ;\n wire row_hit_ns;\n wire row_hit_ns_carry__0_i_1_n_0;\n wire row_hit_ns_carry_i_1_n_0;\n wire row_hit_ns_carry_i_2_n_0;\n wire row_hit_ns_carry_i_3_n_0;\n wire row_hit_ns_carry_i_4_n_0;\n wire row_hit_ns_carry_n_0;\n wire row_hit_ns_carry_n_1;\n wire row_hit_ns_carry_n_2;\n wire row_hit_ns_carry_n_3;\n wire row_hit_r;\n wire start_wtp_timer0;\n wire wait_for_maint_r_lcl_reg;\n wire \\wtr_timer.wtr_cnt_r_reg[1] ;\n wire [3:0]NLW_row_hit_ns_carry_O_UNCONNECTED;\n wire [3:1]NLW_row_hit_ns_carry__0_CO_UNCONNECTED;\n wire [3:0]NLW_row_hit_ns_carry__0_O_UNCONNECTED;\n\n (* SOFT_HLUTNM = \"soft_lutpair1050\" *) \n LUT4 #(\n .INIT(16'h7000)) \n act_wait_r_lcl_i_4__0\n (.I0(bm_end_r1_reg),\n .I1(\\rd_this_rank_r_reg[0] ),\n .I2(pass_open_bank_r_lcl_reg_0),\n .I3(\\grant_r_reg[1] [0]),\n .O(act_wait_r_lcl_reg));\n (* SOFT_HLUTNM = \"soft_lutpair1049\" *) \n LUT3 #(\n .INIT(8'h08)) \n demand_priority_r_i_3\n (.I0(req_bank_rdy_r_reg),\n .I1(\\order_q_r_reg[0] ),\n .I2(\\rd_this_rank_r_reg[0] ),\n .O(demand_priority_r_reg));\n LUT6 #(\n .INIT(64'h00A800FC00A80000)) \n \\grant_r[1]_i_3 \n (.I0(\\wtr_timer.wtr_cnt_r_reg[1] ),\n .I1(pre_passing_open_bank_r_reg),\n .I2(col_wait_r),\n .I3(\\grant_r[1]_i_7_n_0 ),\n .I4(\\rd_this_rank_r_reg[0] ),\n .I5(\\grant_r_reg[0] ),\n .O(granted_col_r_reg));\n (* SOFT_HLUTNM = \"soft_lutpair1049\" *) \n LUT5 #(\n .INIT(32'hEEEEFEEE)) \n \\grant_r[1]_i_7 \n (.I0(override_demand_r_reg),\n .I1(\\rnk_config_strobe_r_reg[0] ),\n .I2(req_bank_rdy_r_reg),\n .I3(\\order_q_r_reg[0] ),\n .I4(\\rd_this_rank_r_reg[0] ),\n .O(\\grant_r[1]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n granted_col_r_i_1\n (.I0(granted_col_r_reg),\n .I1(col_wait_r_reg),\n .O(granted_col_ns));\n LUT6 #(\n .INIT(64'hBF00BFBFBFBFBFBF)) \n i___10_i_2\n (.I0(\\rd_this_rank_r_reg[0] ),\n .I1(\\grant_r_reg[1] [0]),\n .I2(bm_end_r1_reg),\n .I3(rd_wr_r_lcl_reg_0),\n .I4(\\grant_r_reg[1] [1]),\n .I5(req_wr_r_lcl_reg_0),\n .O(req_bank_rdy_r_reg));\n LUT5 #(\n .INIT(32'hAAAA2022)) \n i___37_i_1\n (.I0(row_hit_r),\n .I1(\\maint_controller.maint_wip_r_lcl_reg ),\n .I2(periodic_rd_cntr_r_reg),\n .I3(maint_req_r),\n .I4(wait_for_maint_r_lcl_reg),\n .O(pass_open_bank_r_lcl_reg));\n (* SOFT_HLUTNM = \"soft_lutpair1050\" *) \n LUT2 #(\n .INIT(4'hB)) \n ras_timer_zero_r_i_2__0\n (.I0(\\rd_this_rank_r_reg[0] ),\n .I1(\\grant_r_reg[1] [0]),\n .O(ras_timer_zero_r_reg));\n FDRE #(\n .INIT(1'b0)) \n rb_hit_busy_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(p_67_out),\n .Q(rb_hit_busy_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n rd_wr_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rd_wr_ns),\n .Q(\\rd_this_rank_r_reg[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_bank_r_lcl_reg[0] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[12] [0]),\n .Q(\\cmd_pipe_plus.mc_bank_reg[2] [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_bank_r_lcl_reg[1] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[12] [1]),\n .Q(\\cmd_pipe_plus.mc_bank_reg[2] [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_bank_r_lcl_reg[2] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[12] [2]),\n .Q(\\cmd_pipe_plus.mc_bank_reg[2] [2]),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1051\" *) \n LUT4 #(\n .INIT(16'h8AAA)) \n req_bank_rdy_r_i_1\n (.I0(col_wait_r),\n .I1(\\rd_this_rank_r_reg[0] ),\n .I2(\\order_q_r_reg[0] ),\n .I3(req_bank_rdy_r_reg),\n .O(req_bank_rdy_ns));\n FDRE #(\n .INIT(1'b0)) \n \\req_cmd_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(D[0]),\n .Q(Q[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_cmd_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(D[1]),\n .Q(Q[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[3] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[9] [0]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[4] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[9] [1]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[5] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[9] [2]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[6] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[9] [3]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[7] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[9] [4]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[8] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[9] [5]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[9] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[9] [6]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [6]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_data_buf_addr_r_reg[0] \n (.C(CLK),\n .CE(idle_r_lcl_reg_0),\n .D(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [0]),\n .Q(\\col_mux.col_data_buf_addr_r_reg[4] [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_data_buf_addr_r_reg[1] \n (.C(CLK),\n .CE(idle_r_lcl_reg_0),\n .D(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [1]),\n .Q(\\col_mux.col_data_buf_addr_r_reg[4] [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_data_buf_addr_r_reg[2] \n (.C(CLK),\n .CE(idle_r_lcl_reg_0),\n .D(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [2]),\n .Q(\\col_mux.col_data_buf_addr_r_reg[4] [2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_data_buf_addr_r_reg[3] \n (.C(CLK),\n .CE(idle_r_lcl_reg_0),\n .D(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [3]),\n .Q(\\col_mux.col_data_buf_addr_r_reg[4] [3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_data_buf_addr_r_reg[4] \n (.C(CLK),\n .CE(idle_r_lcl_reg_0),\n .D(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [4]),\n .Q(\\col_mux.col_data_buf_addr_r_reg[4] [4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n req_periodic_rd_r_lcl_reg\n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(periodic_rd_insert),\n .Q(req_periodic_rd_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n req_priority_r_reg\n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(hi_priority),\n .Q(req_priority_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_row_r_lcl_reg[0] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[27] [0]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_row_r_lcl_reg[10] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[27] [10]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [10]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_row_r_lcl_reg[11] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[27] [11]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [11]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_row_r_lcl_reg[12] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[27] [12]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [12]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_row_r_lcl_reg[13] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[27] [13]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [13]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_row_r_lcl_reg[14] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[27] [14]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [14]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_row_r_lcl_reg[1] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[27] [1]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_row_r_lcl_reg[2] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[27] [2]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_row_r_lcl_reg[3] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[27] [3]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_row_r_lcl_reg[4] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[27] [4]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_row_r_lcl_reg[5] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[27] [5]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_row_r_lcl_reg[6] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[27] [6]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [6]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_row_r_lcl_reg[7] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[27] [7]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [7]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_row_r_lcl_reg[8] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[27] [8]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [8]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_row_r_lcl_reg[9] \n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(\\app_addr_r1_reg[27] [9]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [9]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00AFCCAF00AFFFAF)) \n req_wr_r_lcl_i_1__0\n (.I0(Q[1]),\n .I1(cmd[1]),\n .I2(Q[0]),\n .I3(idle_r_lcl_reg),\n .I4(periodic_rd_insert),\n .I5(cmd[0]),\n .O(req_wr_r_lcl0));\n FDRE #(\n .INIT(1'b0)) \n req_wr_r_lcl_reg\n (.C(CLK),\n .CE(idle_r_lcl_reg),\n .D(req_wr_r_lcl0),\n .Q(bm_end_r1_reg),\n .R(1'b0));\n CARRY4 row_hit_ns_carry\n (.CI(1'b0),\n .CO({row_hit_ns_carry_n_0,row_hit_ns_carry_n_1,row_hit_ns_carry_n_2,row_hit_ns_carry_n_3}),\n .CYINIT(1'b1),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(NLW_row_hit_ns_carry_O_UNCONNECTED[3:0]),\n .S({row_hit_ns_carry_i_1_n_0,row_hit_ns_carry_i_2_n_0,row_hit_ns_carry_i_3_n_0,row_hit_ns_carry_i_4_n_0}));\n CARRY4 row_hit_ns_carry__0\n (.CI(row_hit_ns_carry_n_0),\n .CO({NLW_row_hit_ns_carry__0_CO_UNCONNECTED[3:1],row_hit_ns}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(NLW_row_hit_ns_carry__0_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,1'b0,row_hit_ns_carry__0_i_1_n_0}));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n row_hit_ns_carry__0_i_1\n (.I0(\\cmd_pipe_plus.mc_address_reg[14] [14]),\n .I1(\\app_addr_r1_reg[27] [14]),\n .I2(\\cmd_pipe_plus.mc_address_reg[14] [13]),\n .I3(\\app_addr_r1_reg[27] [13]),\n .I4(\\app_addr_r1_reg[27] [12]),\n .I5(\\cmd_pipe_plus.mc_address_reg[14] [12]),\n .O(row_hit_ns_carry__0_i_1_n_0));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n row_hit_ns_carry_i_1\n (.I0(\\cmd_pipe_plus.mc_address_reg[14] [11]),\n .I1(\\app_addr_r1_reg[27] [11]),\n .I2(\\cmd_pipe_plus.mc_address_reg[14] [9]),\n .I3(\\app_addr_r1_reg[27] [9]),\n .I4(\\app_addr_r1_reg[27] [10]),\n .I5(\\cmd_pipe_plus.mc_address_reg[14] [10]),\n .O(row_hit_ns_carry_i_1_n_0));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n row_hit_ns_carry_i_2\n (.I0(\\cmd_pipe_plus.mc_address_reg[14] [8]),\n .I1(\\app_addr_r1_reg[27] [8]),\n .I2(\\cmd_pipe_plus.mc_address_reg[14] [7]),\n .I3(\\app_addr_r1_reg[27] [7]),\n .I4(\\app_addr_r1_reg[27] [6]),\n .I5(\\cmd_pipe_plus.mc_address_reg[14] [6]),\n .O(row_hit_ns_carry_i_2_n_0));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n row_hit_ns_carry_i_3\n (.I0(\\cmd_pipe_plus.mc_address_reg[14] [5]),\n .I1(\\app_addr_r1_reg[27] [5]),\n .I2(\\cmd_pipe_plus.mc_address_reg[14] [4]),\n .I3(\\app_addr_r1_reg[27] [4]),\n .I4(\\app_addr_r1_reg[27] [3]),\n .I5(\\cmd_pipe_plus.mc_address_reg[14] [3]),\n .O(row_hit_ns_carry_i_3_n_0));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n row_hit_ns_carry_i_4\n (.I0(\\cmd_pipe_plus.mc_address_reg[14] [2]),\n .I1(\\app_addr_r1_reg[27] [2]),\n .I2(\\cmd_pipe_plus.mc_address_reg[14] [1]),\n .I3(\\app_addr_r1_reg[27] [1]),\n .I4(\\app_addr_r1_reg[27] [0]),\n .I5(\\cmd_pipe_plus.mc_address_reg[14] [0]),\n .O(row_hit_ns_carry_i_4_n_0));\n FDRE #(\n .INIT(1'b0)) \n row_hit_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(row_hit_ns),\n .Q(row_hit_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1051\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\wr_this_rank_r[0]_i_1 \n (.I0(\\rd_this_rank_r_reg[0] ),\n .O(start_wtp_timer0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_bank_mach\" *) \nmodule ddr3_ifmig_7series_v4_0_bank_mach\n (maint_wip_r,\n insert_maint_r1_lcl_reg,\n insert_maint_r1,\n periodic_rd_ack_r,\n accept_ns,\n q_has_priority_r_reg,\n idle_r,\n idle_r_lcl_reg,\n idle_r_lcl_reg_0,\n was_wr,\n sent_col,\n DIC,\n rd_wr_r,\n col_data_buf_addr,\n \\act_this_rank_r_reg[0] ,\n cke_r,\n req_wr_r,\n row_hit_r,\n bm_end_r1,\n p_52_out,\n pre_wait_r,\n req_bank_rdy_ns,\n override_demand_ns,\n wr_this_rank_r,\n wait_for_maint_r,\n bm_end_r1_reg,\n pre_bm_end_r,\n row_hit_r_0,\n bm_end_r1_0,\n p_13_out,\n req_bank_rdy_ns_1,\n wait_for_maint_r_2,\n bm_end_r1_reg_0,\n rb_hit_busies_r,\n q_has_rd,\n q_has_priority,\n \\rcd_timer_gt_2.rcd_timer_r_reg[0] ,\n rnk_config_valid_r,\n periodic_rd_cntr_r,\n tail_r,\n q_entry_r,\n head_r,\n auto_pre_r,\n \\order_q_r_reg[0] ,\n ordered_r_lcl,\n order_q_r,\n tail_r_3,\n q_entry_r_4,\n auto_pre_r_5,\n order_q_r_6,\n \\periodic_rd_generation.periodic_rd_timer_r_reg[0] ,\n Q,\n read_this_rank,\n D,\n \\rtw_timer.rtw_cnt_r_reg[1] ,\n mc_odt_ns,\n col_rd_wr,\n mc_data_offset_2_ns,\n wait_for_maint_r_lcl_reg,\n clear_req,\n head_r_lcl_reg,\n q_has_priority_r_reg_0,\n \\q_entry_r_reg[0] ,\n \\q_entry_r_reg[0]_0 ,\n set_order_q,\n wait_for_maint_r_lcl_reg_0,\n head_r_lcl_reg_0,\n head_r_lcl_reg_1,\n set_order_q_7,\n \\cmd_pipe_plus.mc_address_reg[0] ,\n pass_open_bank_r_lcl_reg,\n \\q_entry_r_reg[0]_1 ,\n rtp_timer_r,\n q_has_rd_r_reg,\n \\q_entry_r_reg[0]_2 ,\n mc_cas_n_ns,\n mc_cs_n_ns,\n mc_ras_n_ns,\n \\cmd_pipe_plus.mc_bank_reg[5] ,\n \\cmd_pipe_plus.mc_bank_reg[2] ,\n \\cmd_pipe_plus.mc_bank_reg[2]_0 ,\n \\cmd_pipe_plus.mc_address_reg[25] ,\n req_bank_rdy_r_reg,\n \\rnk_config_strobe_r_reg[0] ,\n \\rnk_config_strobe_r_reg[0]_0 ,\n ras_timer_zero_r_reg,\n head_r_lcl_reg_2,\n auto_pre_r_lcl_reg,\n auto_pre_r_lcl_reg_0,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6] ,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 ,\n pass_open_bank_r_lcl_reg_0,\n \\wtr_timer.wtr_cnt_r_reg[2] ,\n act_this_rank,\n \\inhbt_act_faw.inhbt_act_faw_r_reg ,\n E,\n \\cmd_pipe_plus.mc_address_reg[40] ,\n \\cmd_pipe_plus.mc_bank_reg[8] ,\n \\cmd_pipe_plus.mc_bank_reg[7] ,\n \\cmd_pipe_plus.mc_bank_reg[6] ,\n \\cmd_pipe_plus.mc_address_reg[44] ,\n \\cmd_pipe_plus.mc_address_reg[43] ,\n \\cmd_pipe_plus.mc_address_reg[42] ,\n \\cmd_pipe_plus.mc_address_reg[41] ,\n \\cmd_pipe_plus.mc_address_reg[39] ,\n \\cmd_pipe_plus.mc_address_reg[38] ,\n \\cmd_pipe_plus.mc_address_reg[37] ,\n \\cmd_pipe_plus.mc_address_reg[36] ,\n \\cmd_pipe_plus.mc_address_reg[35] ,\n \\cmd_pipe_plus.mc_address_reg[34] ,\n \\cmd_pipe_plus.mc_address_reg[33] ,\n \\cmd_pipe_plus.mc_address_reg[32] ,\n \\cmd_pipe_plus.mc_address_reg[31] ,\n \\cmd_pipe_plus.mc_address_reg[30] ,\n \\cmd_pipe_plus.mc_we_n_reg[2] ,\n \\cmd_pipe_plus.mc_cas_n_reg[2] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[0] ,\n CLK,\n p_67_out,\n p_28_out,\n maint_srx_r,\n SR,\n mc_cke_ns,\n hi_priority,\n rstdiv0_sync_r1_reg_rep__0,\n phy_mc_ctl_full,\n of_ctl_full_v,\n pass_open_bank_r_lcl_reg_1,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ,\n q_has_rd_r_reg_0,\n q_has_priority_r_reg_1,\n rnk_config_valid_r_lcl_reg,\n \\periodic_read_request.periodic_rd_r_lcl_reg ,\n idle_r_lcl_reg_1,\n \\q_entry_r_reg[0]_3 ,\n head_r_lcl_reg_3,\n head_r_lcl_reg_4,\n auto_pre_r_lcl_reg_1,\n ordered_r_lcl_reg,\n ordered_r_lcl_reg_0,\n ordered_r_lcl_reg_1,\n idle_r_lcl_reg_2,\n \\q_entry_r_reg[0]_4 ,\n auto_pre_r_lcl_reg_2,\n ordered_r_lcl_reg_2,\n \\req_bank_r_lcl_reg[0] ,\n rstdiv0_sync_r1_reg_rep__20,\n \\entry_cnt_reg[2] ,\n \\entry_cnt_reg[2]_0 ,\n read_this_rank_r,\n rstdiv0_sync_r1_reg_rep__21,\n \\wtr_timer.wtr_cnt_r_reg[1] ,\n \\rtw_timer.rtw_cnt_r_reg[1]_0 ,\n \\cmd_pipe_plus.mc_data_offset_2_reg[3] ,\n col_rd_wr_r1,\n maint_req_r,\n init_calib_complete_reg_rep__6,\n periodic_rd_r,\n cmd,\n \\maint_controller.maint_wip_r_lcl_reg ,\n use_addr,\n req_wr_r_lcl_reg,\n bm_end_r1_reg_1,\n bm_end_r1_reg_2,\n rtp_timer_ns1,\n pass_open_bank_r_lcl_reg_2,\n app_hi_pri_r2,\n maint_zq_r,\n \\grant_r_reg[1] ,\n inhbt_act_faw_r,\n \\ras_timer_r_reg[2] ,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ,\n \\generate_maint_cmds.insert_maint_r_lcl_reg ,\n \\maintenance_request.maint_zq_r_lcl_reg ,\n \\generate_maint_cmds.insert_maint_r_lcl_reg_0 ,\n \\app_addr_r1_reg[27] ,\n \\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ,\n \\app_addr_r1_reg[12] ,\n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ,\n \\app_addr_r1_reg[9] ,\n pass_open_bank_r_lcl_reg_3);\n output maint_wip_r;\n output insert_maint_r1_lcl_reg;\n output insert_maint_r1;\n output periodic_rd_ack_r;\n output accept_ns;\n output [0:0]q_has_priority_r_reg;\n output [1:0]idle_r;\n output idle_r_lcl_reg;\n output idle_r_lcl_reg_0;\n output was_wr;\n output sent_col;\n output [0:0]DIC;\n output [1:0]rd_wr_r;\n output [4:0]col_data_buf_addr;\n output [0:0]\\act_this_rank_r_reg[0] ;\n output cke_r;\n output [1:0]req_wr_r;\n output row_hit_r;\n output bm_end_r1;\n output p_52_out;\n output pre_wait_r;\n output req_bank_rdy_ns;\n output override_demand_ns;\n output [1:0]wr_this_rank_r;\n output wait_for_maint_r;\n output bm_end_r1_reg;\n output pre_bm_end_r;\n output row_hit_r_0;\n output bm_end_r1_0;\n output p_13_out;\n output req_bank_rdy_ns_1;\n output wait_for_maint_r_2;\n output bm_end_r1_reg_0;\n output [0:0]rb_hit_busies_r;\n output q_has_rd;\n output q_has_priority;\n output \\rcd_timer_gt_2.rcd_timer_r_reg[0] ;\n output rnk_config_valid_r;\n output periodic_rd_cntr_r;\n output tail_r;\n output q_entry_r;\n output [1:0]head_r;\n output auto_pre_r;\n output \\order_q_r_reg[0] ;\n output ordered_r_lcl;\n output order_q_r;\n output tail_r_3;\n output q_entry_r_4;\n output auto_pre_r_5;\n output order_q_r_6;\n output \\periodic_rd_generation.periodic_rd_timer_r_reg[0] ;\n output [1:0]Q;\n output read_this_rank;\n output [1:0]D;\n output \\rtw_timer.rtw_cnt_r_reg[1] ;\n output [0:0]mc_odt_ns;\n output col_rd_wr;\n output [0:0]mc_data_offset_2_ns;\n output wait_for_maint_r_lcl_reg;\n output clear_req;\n output head_r_lcl_reg;\n output q_has_priority_r_reg_0;\n output \\q_entry_r_reg[0] ;\n output \\q_entry_r_reg[0]_0 ;\n output set_order_q;\n output wait_for_maint_r_lcl_reg_0;\n output head_r_lcl_reg_0;\n output head_r_lcl_reg_1;\n output set_order_q_7;\n output [1:0]\\cmd_pipe_plus.mc_address_reg[0] ;\n output pass_open_bank_r_lcl_reg;\n output \\q_entry_r_reg[0]_1 ;\n output [1:0]rtp_timer_r;\n output q_has_rd_r_reg;\n output \\q_entry_r_reg[0]_2 ;\n output [1:0]mc_cas_n_ns;\n output [0:0]mc_cs_n_ns;\n output [1:0]mc_ras_n_ns;\n output [5:0]\\cmd_pipe_plus.mc_bank_reg[5] ;\n output [2:0]\\cmd_pipe_plus.mc_bank_reg[2] ;\n output [2:0]\\cmd_pipe_plus.mc_bank_reg[2]_0 ;\n output [22:0]\\cmd_pipe_plus.mc_address_reg[25] ;\n output req_bank_rdy_r_reg;\n output \\rnk_config_strobe_r_reg[0] ;\n output \\rnk_config_strobe_r_reg[0]_0 ;\n output [2:0]ras_timer_zero_r_reg;\n output head_r_lcl_reg_2;\n output auto_pre_r_lcl_reg;\n output auto_pre_r_lcl_reg_0;\n output [2:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6] ;\n output \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 ;\n output pass_open_bank_r_lcl_reg_0;\n output \\wtr_timer.wtr_cnt_r_reg[2] ;\n output act_this_rank;\n output \\inhbt_act_faw.inhbt_act_faw_r_reg ;\n output [0:0]E;\n output \\cmd_pipe_plus.mc_address_reg[40] ;\n output \\cmd_pipe_plus.mc_bank_reg[8] ;\n output \\cmd_pipe_plus.mc_bank_reg[7] ;\n output \\cmd_pipe_plus.mc_bank_reg[6] ;\n output \\cmd_pipe_plus.mc_address_reg[44] ;\n output \\cmd_pipe_plus.mc_address_reg[43] ;\n output \\cmd_pipe_plus.mc_address_reg[42] ;\n output \\cmd_pipe_plus.mc_address_reg[41] ;\n output \\cmd_pipe_plus.mc_address_reg[39] ;\n output \\cmd_pipe_plus.mc_address_reg[38] ;\n output \\cmd_pipe_plus.mc_address_reg[37] ;\n output \\cmd_pipe_plus.mc_address_reg[36] ;\n output \\cmd_pipe_plus.mc_address_reg[35] ;\n output \\cmd_pipe_plus.mc_address_reg[34] ;\n output \\cmd_pipe_plus.mc_address_reg[33] ;\n output \\cmd_pipe_plus.mc_address_reg[32] ;\n output \\cmd_pipe_plus.mc_address_reg[31] ;\n output \\cmd_pipe_plus.mc_address_reg[30] ;\n output \\cmd_pipe_plus.mc_we_n_reg[2] ;\n output \\cmd_pipe_plus.mc_cas_n_reg[2] ;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[0] ;\n input CLK;\n input p_67_out;\n input p_28_out;\n input maint_srx_r;\n input [0:0]SR;\n input [0:0]mc_cke_ns;\n input hi_priority;\n input rstdiv0_sync_r1_reg_rep__0;\n input phy_mc_ctl_full;\n input [0:0]of_ctl_full_v;\n input pass_open_bank_r_lcl_reg_1;\n input \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ;\n input q_has_rd_r_reg_0;\n input q_has_priority_r_reg_1;\n input rnk_config_valid_r_lcl_reg;\n input \\periodic_read_request.periodic_rd_r_lcl_reg ;\n input idle_r_lcl_reg_1;\n input \\q_entry_r_reg[0]_3 ;\n input head_r_lcl_reg_3;\n input head_r_lcl_reg_4;\n input auto_pre_r_lcl_reg_1;\n input ordered_r_lcl_reg;\n input ordered_r_lcl_reg_0;\n input ordered_r_lcl_reg_1;\n input idle_r_lcl_reg_2;\n input \\q_entry_r_reg[0]_4 ;\n input auto_pre_r_lcl_reg_2;\n input ordered_r_lcl_reg_2;\n input \\req_bank_r_lcl_reg[0] ;\n input rstdiv0_sync_r1_reg_rep__20;\n input \\entry_cnt_reg[2] ;\n input \\entry_cnt_reg[2]_0 ;\n input read_this_rank_r;\n input rstdiv0_sync_r1_reg_rep__21;\n input \\wtr_timer.wtr_cnt_r_reg[1] ;\n input [0:0]\\rtw_timer.rtw_cnt_r_reg[1]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_2_reg[3] ;\n input col_rd_wr_r1;\n input maint_req_r;\n input init_calib_complete_reg_rep__6;\n input periodic_rd_r;\n input [1:0]cmd;\n input \\maint_controller.maint_wip_r_lcl_reg ;\n input use_addr;\n input req_wr_r_lcl_reg;\n input bm_end_r1_reg_1;\n input bm_end_r1_reg_2;\n input rtp_timer_ns1;\n input pass_open_bank_r_lcl_reg_2;\n input app_hi_pri_r2;\n input maint_zq_r;\n input \\grant_r_reg[1] ;\n input inhbt_act_faw_r;\n input \\ras_timer_r_reg[2] ;\n input [2:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ;\n input \\generate_maint_cmds.insert_maint_r_lcl_reg ;\n input \\maintenance_request.maint_zq_r_lcl_reg ;\n input \\generate_maint_cmds.insert_maint_r_lcl_reg_0 ;\n input [14:0]\\app_addr_r1_reg[27] ;\n input [3:0]\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ;\n input [2:0]\\app_addr_r1_reg[12] ;\n input [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n input [6:0]\\app_addr_r1_reg[9] ;\n input pass_open_bank_r_lcl_reg_3;\n\n wire CLK;\n wire [1:0]D;\n wire [0:0]DIC;\n wire [0:0]E;\n wire [1:0]Q;\n wire [0:0]SR;\n wire accept_internal_r;\n wire accept_ns;\n wire act_this_rank;\n wire [1:0]act_this_rank_r;\n wire [0:0]\\act_this_rank_r_reg[0] ;\n wire [2:0]\\app_addr_r1_reg[12] ;\n wire [14:0]\\app_addr_r1_reg[27] ;\n wire [6:0]\\app_addr_r1_reg[9] ;\n wire app_hi_pri_r2;\n wire arb_mux0_n_16;\n wire arb_mux0_n_58;\n wire arb_mux0_n_59;\n wire arb_mux0_n_60;\n wire arb_mux0_n_62;\n wire arb_mux0_n_66;\n wire arb_mux0_n_67;\n wire arb_mux0_n_68;\n wire \\arb_row_col0/granted_col_ns ;\n wire \\arb_row_col0/rnk_config_strobe_ns ;\n wire auto_pre_r;\n wire auto_pre_r_5;\n wire auto_pre_r_lcl_reg;\n wire auto_pre_r_lcl_reg_0;\n wire auto_pre_r_lcl_reg_1;\n wire auto_pre_r_lcl_reg_2;\n wire \\bank_cntrl[0].bank0_n_32 ;\n wire \\bank_cntrl[0].bank0_n_38 ;\n wire \\bank_cntrl[0].bank0_n_39 ;\n wire \\bank_cntrl[0].bank0_n_40 ;\n wire \\bank_cntrl[0].bank0_n_44 ;\n wire \\bank_cntrl[0].bank0_n_46 ;\n wire \\bank_cntrl[0].bank0_n_47 ;\n wire \\bank_cntrl[0].bank0_n_51 ;\n wire \\bank_cntrl[1].bank0_n_32 ;\n wire \\bank_cntrl[1].bank0_n_42 ;\n wire \\bank_cntrl[1].bank0_n_43 ;\n wire \\bank_cntrl[1].bank0_n_44 ;\n wire \\bank_cntrl[1].bank0_n_45 ;\n wire \\bank_cntrl[1].bank0_n_62 ;\n wire \\bank_cntrl[1].bank0_n_67 ;\n wire bank_common0_n_10;\n wire bank_common0_n_11;\n wire bank_common0_n_14;\n wire bank_common0_n_15;\n wire bank_common0_n_4;\n wire [1:0]\\bank_compare0/req_cmd_r ;\n wire [1:0]\\bank_compare0/req_cmd_r_2 ;\n wire [9:3]\\bank_compare0/req_col_r ;\n wire [9:3]\\bank_compare0/req_col_r_1 ;\n wire \\bank_queue0/pre_passing_open_bank_r ;\n wire \\bank_queue0/pre_passing_open_bank_r_3 ;\n wire \\bank_queue0/rb_hit_busies_ns ;\n wire \\bank_queue0/wait_for_maint_ns ;\n wire \\bank_queue0/wait_for_maint_ns_8 ;\n wire \\bank_state0/demand_priority_r ;\n wire \\bank_state0/demand_priority_r_6 ;\n wire \\bank_state0/demanded_prior_r ;\n wire \\bank_state0/demanded_prior_r_5 ;\n wire \\bank_state0/ofs_rdy_r ;\n wire \\bank_state0/ofs_rdy_r0 ;\n wire \\bank_state0/ofs_rdy_r_4 ;\n wire \\bank_state0/req_bank_rdy_r ;\n wire \\bank_state0/req_bank_rdy_r_7 ;\n wire bm_end_r1;\n wire bm_end_r1_0;\n wire bm_end_r1_reg;\n wire bm_end_r1_reg_0;\n wire bm_end_r1_reg_1;\n wire bm_end_r1_reg_2;\n wire cke_r;\n wire clear_req;\n wire [1:0]cmd;\n wire [1:0]\\cmd_pipe_plus.mc_address_reg[0] ;\n wire [22:0]\\cmd_pipe_plus.mc_address_reg[25] ;\n wire \\cmd_pipe_plus.mc_address_reg[30] ;\n wire \\cmd_pipe_plus.mc_address_reg[31] ;\n wire \\cmd_pipe_plus.mc_address_reg[32] ;\n wire \\cmd_pipe_plus.mc_address_reg[33] ;\n wire \\cmd_pipe_plus.mc_address_reg[34] ;\n wire \\cmd_pipe_plus.mc_address_reg[35] ;\n wire \\cmd_pipe_plus.mc_address_reg[36] ;\n wire \\cmd_pipe_plus.mc_address_reg[37] ;\n wire \\cmd_pipe_plus.mc_address_reg[38] ;\n wire \\cmd_pipe_plus.mc_address_reg[39] ;\n wire \\cmd_pipe_plus.mc_address_reg[40] ;\n wire \\cmd_pipe_plus.mc_address_reg[41] ;\n wire \\cmd_pipe_plus.mc_address_reg[42] ;\n wire \\cmd_pipe_plus.mc_address_reg[43] ;\n wire \\cmd_pipe_plus.mc_address_reg[44] ;\n wire [2:0]\\cmd_pipe_plus.mc_bank_reg[2] ;\n wire [2:0]\\cmd_pipe_plus.mc_bank_reg[2]_0 ;\n wire [5:0]\\cmd_pipe_plus.mc_bank_reg[5] ;\n wire \\cmd_pipe_plus.mc_bank_reg[6] ;\n wire \\cmd_pipe_plus.mc_bank_reg[7] ;\n wire \\cmd_pipe_plus.mc_bank_reg[8] ;\n wire \\cmd_pipe_plus.mc_cas_n_reg[2] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[0] ;\n wire \\cmd_pipe_plus.mc_data_offset_2_reg[3] ;\n wire \\cmd_pipe_plus.mc_we_n_reg[2] ;\n wire [4:0]col_data_buf_addr;\n wire col_rd_wr;\n wire col_rd_wr_r1;\n wire [3:0]\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ;\n wire \\entry_cnt_reg[2] ;\n wire \\entry_cnt_reg[2]_0 ;\n wire \\generate_maint_cmds.insert_maint_r_lcl_reg ;\n wire \\generate_maint_cmds.insert_maint_r_lcl_reg_0 ;\n wire \\grant_r_reg[1] ;\n wire granted_pre_ns;\n wire granted_row_ns;\n wire [1:0]head_r;\n wire head_r_lcl_reg;\n wire head_r_lcl_reg_0;\n wire head_r_lcl_reg_1;\n wire head_r_lcl_reg_2;\n wire head_r_lcl_reg_3;\n wire head_r_lcl_reg_4;\n wire hi_priority;\n wire [1:0]idle_r;\n wire idle_r_lcl_reg;\n wire idle_r_lcl_reg_0;\n wire idle_r_lcl_reg_1;\n wire idle_r_lcl_reg_2;\n wire \\inhbt_act_faw.inhbt_act_faw_r_reg ;\n wire inhbt_act_faw_r;\n wire init_calib_complete_reg_rep__6;\n wire insert_maint_r1;\n wire insert_maint_r1_lcl_reg;\n wire \\maint_controller.maint_wip_r_lcl_reg ;\n wire maint_req_r;\n wire maint_srx_r;\n wire maint_wip_r;\n wire maint_zq_r;\n wire \\maintenance_request.maint_zq_r_lcl_reg ;\n wire [1:0]mc_cas_n_ns;\n wire [0:0]mc_cke_ns;\n wire [0:0]mc_cs_n_ns;\n wire [0:0]mc_data_offset_2_ns;\n wire [0:0]mc_odt_ns;\n wire [1:0]mc_ras_n_ns;\n wire [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n wire [0:0]of_ctl_full_v;\n wire order_q_r;\n wire order_q_r_6;\n wire \\order_q_r_reg[0] ;\n wire ordered_r_lcl;\n wire ordered_r_lcl_reg;\n wire ordered_r_lcl_reg_0;\n wire ordered_r_lcl_reg_1;\n wire ordered_r_lcl_reg_2;\n wire override_demand_ns;\n wire p_13_out;\n wire p_28_out;\n wire p_52_out;\n wire p_67_out;\n wire p_9_in;\n wire pass_open_bank_r_lcl_reg;\n wire pass_open_bank_r_lcl_reg_0;\n wire pass_open_bank_r_lcl_reg_1;\n wire pass_open_bank_r_lcl_reg_2;\n wire pass_open_bank_r_lcl_reg_3;\n wire periodic_rd_ack_r;\n wire periodic_rd_cntr_r;\n wire \\periodic_rd_generation.periodic_rd_timer_r_reg[0] ;\n wire periodic_rd_insert;\n wire periodic_rd_r;\n wire \\periodic_read_request.periodic_rd_r_lcl_reg ;\n wire phy_mc_ctl_full;\n wire pre_bm_end_r;\n wire pre_wait_r;\n wire q_entry_r;\n wire q_entry_r_4;\n wire \\q_entry_r_reg[0] ;\n wire \\q_entry_r_reg[0]_0 ;\n wire \\q_entry_r_reg[0]_1 ;\n wire \\q_entry_r_reg[0]_2 ;\n wire \\q_entry_r_reg[0]_3 ;\n wire \\q_entry_r_reg[0]_4 ;\n wire q_has_priority;\n wire [0:0]q_has_priority_r_reg;\n wire q_has_priority_r_reg_0;\n wire q_has_priority_r_reg_1;\n wire q_has_rd;\n wire q_has_rd_r_reg;\n wire q_has_rd_r_reg_0;\n wire \\ras_timer_r_reg[2] ;\n wire [2:0]ras_timer_zero_r_reg;\n wire \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ;\n wire [0:0]rb_hit_busies_r;\n wire [1:1]rb_hit_busies_r_0;\n wire [0:0]rb_hit_busy_r;\n wire \\rcd_timer_gt_2.rcd_timer_r_reg[0] ;\n wire [1:0]rd_this_rank_r;\n wire [1:0]rd_wr_r;\n wire read_this_rank;\n wire read_this_rank_r;\n wire \\req_bank_r_lcl_reg[0] ;\n wire req_bank_rdy_ns;\n wire req_bank_rdy_ns_1;\n wire req_bank_rdy_r_reg;\n wire [9:0]req_data_buf_addr_r;\n wire [1:0]req_periodic_rd_r;\n wire [29:0]req_row_r;\n wire [1:0]req_wr_r;\n wire req_wr_r_lcl_reg;\n wire [2:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ;\n wire [2:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6] ;\n wire \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 ;\n wire \\rnk_config_strobe_r_reg[0] ;\n wire \\rnk_config_strobe_r_reg[0]_0 ;\n wire rnk_config_valid_r;\n wire rnk_config_valid_r_lcl_reg;\n wire [1:1]row_cmd_wr;\n wire row_hit_r;\n wire row_hit_r_0;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire rtp_timer_ns1;\n wire [1:0]rtp_timer_r;\n wire \\rtw_timer.rtw_cnt_r_reg[1] ;\n wire [0:0]\\rtw_timer.rtw_cnt_r_reg[1]_0 ;\n wire [1:0]sending_pre;\n wire sent_col;\n wire set_order_q;\n wire set_order_q_7;\n wire tail_r;\n wire tail_r_3;\n wire use_addr;\n wire wait_for_maint_r;\n wire wait_for_maint_r_2;\n wire wait_for_maint_r_lcl_reg;\n wire wait_for_maint_r_lcl_reg_0;\n wire was_wr;\n wire [1:0]wr_this_rank_r;\n wire \\wtr_timer.wtr_cnt_r_reg[1] ;\n wire \\wtr_timer.wtr_cnt_r_reg[2] ;\n\n ddr3_ifmig_7series_v4_0_arb_mux arb_mux0\n (.CLK(CLK),\n .D(D),\n .DIC(DIC),\n .Q(Q),\n .SR(SR),\n .act_this_rank(act_this_rank),\n .act_this_rank_r(act_this_rank_r),\n .act_wait_r_lcl_reg(\\act_this_rank_r_reg[0] ),\n .auto_pre_r_lcl_reg(\\bank_cntrl[1].bank0_n_67 ),\n .auto_pre_r_lcl_reg_0(\\bank_cntrl[0].bank0_n_46 ),\n .auto_pre_r_lcl_reg_1(auto_pre_r),\n .auto_pre_r_lcl_reg_2(auto_pre_r_5),\n .cke_r(cke_r),\n .\\cmd_pipe_plus.mc_address_reg[0] (insert_maint_r1),\n .\\cmd_pipe_plus.mc_address_reg[0]_0 (\\cmd_pipe_plus.mc_address_reg[0] ),\n .\\cmd_pipe_plus.mc_address_reg[10] (arb_mux0_n_68),\n .\\cmd_pipe_plus.mc_address_reg[25] ({\\cmd_pipe_plus.mc_address_reg[25] [22:11],\\cmd_pipe_plus.mc_address_reg[25] [9:0]}),\n .\\cmd_pipe_plus.mc_address_reg[30] (\\cmd_pipe_plus.mc_address_reg[30] ),\n .\\cmd_pipe_plus.mc_address_reg[31] (\\cmd_pipe_plus.mc_address_reg[31] ),\n .\\cmd_pipe_plus.mc_address_reg[32] (\\cmd_pipe_plus.mc_address_reg[32] ),\n .\\cmd_pipe_plus.mc_address_reg[33] (\\cmd_pipe_plus.mc_address_reg[33] ),\n .\\cmd_pipe_plus.mc_address_reg[34] (\\cmd_pipe_plus.mc_address_reg[34] ),\n .\\cmd_pipe_plus.mc_address_reg[35] (\\cmd_pipe_plus.mc_address_reg[35] ),\n .\\cmd_pipe_plus.mc_address_reg[36] (\\cmd_pipe_plus.mc_address_reg[36] ),\n .\\cmd_pipe_plus.mc_address_reg[37] (\\cmd_pipe_plus.mc_address_reg[37] ),\n .\\cmd_pipe_plus.mc_address_reg[38] (\\cmd_pipe_plus.mc_address_reg[38] ),\n .\\cmd_pipe_plus.mc_address_reg[39] (\\cmd_pipe_plus.mc_address_reg[39] ),\n .\\cmd_pipe_plus.mc_address_reg[41] (\\cmd_pipe_plus.mc_address_reg[41] ),\n .\\cmd_pipe_plus.mc_address_reg[42] (\\cmd_pipe_plus.mc_address_reg[42] ),\n .\\cmd_pipe_plus.mc_address_reg[43] (\\cmd_pipe_plus.mc_address_reg[43] ),\n .\\cmd_pipe_plus.mc_address_reg[44] (\\cmd_pipe_plus.mc_address_reg[44] ),\n .\\cmd_pipe_plus.mc_bank_reg[5] (\\cmd_pipe_plus.mc_bank_reg[5] ),\n .\\cmd_pipe_plus.mc_bank_reg[6] (\\cmd_pipe_plus.mc_bank_reg[6] ),\n .\\cmd_pipe_plus.mc_bank_reg[7] (\\cmd_pipe_plus.mc_bank_reg[7] ),\n .\\cmd_pipe_plus.mc_bank_reg[8] (\\cmd_pipe_plus.mc_bank_reg[8] ),\n .\\cmd_pipe_plus.mc_cas_n_reg[2] (sending_pre),\n .\\cmd_pipe_plus.mc_cas_n_reg[2]_0 (\\cmd_pipe_plus.mc_cas_n_reg[2] ),\n .\\cmd_pipe_plus.mc_cmd_reg[0] (sent_col),\n .\\cmd_pipe_plus.mc_cs_n_reg[0] (mc_cs_n_ns),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[0] (\\cmd_pipe_plus.mc_data_offset_1_reg[0] ),\n .\\cmd_pipe_plus.mc_data_offset_2_reg[3] (\\cmd_pipe_plus.mc_data_offset_2_reg[3] ),\n .\\cmd_pipe_plus.mc_we_n_reg[2] (\\cmd_pipe_plus.mc_we_n_reg[2] ),\n .col_data_buf_addr(col_data_buf_addr),\n .col_rd_wr(col_rd_wr),\n .col_rd_wr_r1(col_rd_wr_r1),\n .col_wait_r_reg(\\bank_cntrl[0].bank0_n_32 ),\n .col_wait_r_reg_0(\\bank_cntrl[1].bank0_n_32 ),\n .\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] (\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ),\n .demand_priority_r_reg(arb_mux0_n_66),\n .demand_priority_r_reg_0(arb_mux0_n_67),\n .\\generate_maint_cmds.insert_maint_r_lcl_reg (insert_maint_r1_lcl_reg),\n .\\grant_r_reg[1] (\\grant_r_reg[1] ),\n .granted_col_ns(\\arb_row_col0/granted_col_ns ),\n .granted_col_r_reg(arb_mux0_n_16),\n .granted_col_r_reg_0(arb_mux0_n_59),\n .granted_col_r_reg_1(arb_mux0_n_60),\n .granted_pre_ns(granted_pre_ns),\n .granted_row_ns(granted_row_ns),\n .granted_row_r_reg(arb_mux0_n_58),\n .granted_row_r_reg_0(arb_mux0_n_62),\n .head_r_lcl_reg(\\bank_cntrl[1].bank0_n_62 ),\n .head_r_lcl_reg_0(\\bank_cntrl[0].bank0_n_47 ),\n .\\inhbt_act_faw.inhbt_act_faw_r_reg (\\inhbt_act_faw.inhbt_act_faw_r_reg ),\n .inhbt_act_faw_r(inhbt_act_faw_r),\n .maint_srx_r(maint_srx_r),\n .maint_zq_r(maint_zq_r),\n .mc_cas_n_ns(mc_cas_n_ns),\n .mc_cke_ns(mc_cke_ns),\n .mc_data_offset_2_ns(mc_data_offset_2_ns),\n .mc_odt_ns(mc_odt_ns),\n .mc_ras_n_ns(mc_ras_n_ns),\n .ofs_rdy_r(\\bank_state0/ofs_rdy_r_4 ),\n .ofs_rdy_r_0(\\bank_state0/ofs_rdy_r ),\n .override_demand_ns(override_demand_ns),\n .\\periodic_rd_generation.periodic_rd_timer_r_reg[0] (\\periodic_rd_generation.periodic_rd_timer_r_reg[0] ),\n .rd_this_rank_r(rd_this_rank_r),\n .rd_wr_r_lcl_reg(rd_wr_r[1]),\n .rd_wr_r_lcl_reg_0(rd_wr_r[0]),\n .read_this_rank(read_this_rank),\n .read_this_rank_r(read_this_rank_r),\n .\\req_bank_r_lcl_reg[2] (\\cmd_pipe_plus.mc_bank_reg[2] ),\n .\\req_bank_r_lcl_reg[2]_0 (\\cmd_pipe_plus.mc_bank_reg[2]_0 ),\n .req_bank_rdy_r(\\bank_state0/req_bank_rdy_r ),\n .req_bank_rdy_r_1(\\bank_state0/req_bank_rdy_r_7 ),\n .\\req_col_r_reg[9] (\\bank_compare0/req_col_r ),\n .\\req_col_r_reg[9]_0 (\\bank_compare0/req_col_r_1 ),\n .req_data_buf_addr_r(req_data_buf_addr_r),\n .req_periodic_rd_r(req_periodic_rd_r),\n .req_row_r({req_row_r[29:26],req_row_r[24:11],req_row_r[9:0]}),\n .rnk_config_strobe_ns(\\arb_row_col0/rnk_config_strobe_ns ),\n .\\rnk_config_strobe_r_reg[0] (rnk_config_valid_r),\n .rnk_config_valid_r_lcl_reg(rnk_config_valid_r_lcl_reg),\n .row_cmd_wr(row_cmd_wr),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .\\rtw_timer.rtw_cnt_r_reg[1] (\\rtw_timer.rtw_cnt_r_reg[1] ),\n .\\rtw_timer.rtw_cnt_r_reg[1]_0 (\\rtw_timer.rtw_cnt_r_reg[1]_0 ),\n .wr_this_rank_r(wr_this_rank_r),\n .\\wtr_timer.wtr_cnt_r_reg[2] (\\wtr_timer.wtr_cnt_r_reg[2] ));\n ddr3_ifmig_7series_v4_0_bank_cntrl \\bank_cntrl[0].bank0 \n (.CLK(CLK),\n .D({bank_common0_n_14,bank_common0_n_15}),\n .E(idle_r[0]),\n .Q(\\bank_compare0/req_cmd_r ),\n .SR(SR),\n .accept_internal_r(accept_internal_r),\n .accept_r_reg(q_has_rd_r_reg),\n .accept_r_reg_0(bank_common0_n_4),\n .act_this_rank_r(act_this_rank_r[0]),\n .\\act_this_rank_r_reg[0] (\\act_this_rank_r_reg[0] ),\n .act_wait_r_lcl_reg(\\bank_cntrl[0].bank0_n_44 ),\n .\\app_addr_r1_reg[12] (\\app_addr_r1_reg[12] ),\n .\\app_addr_r1_reg[27] (\\app_addr_r1_reg[27] ),\n .\\app_addr_r1_reg[9] (\\app_addr_r1_reg[9] ),\n .app_hi_pri_r2(app_hi_pri_r2),\n .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg_0),\n .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_1),\n .auto_pre_r_lcl_reg_1(\\bank_cntrl[1].bank0_n_67 ),\n .bm_end_r1(bm_end_r1),\n .bm_end_r1_reg(req_wr_r[0]),\n .bm_end_r1_reg_0(p_52_out),\n .bm_end_r1_reg_1(bm_end_r1_reg),\n .bm_end_r1_reg_2(\\bank_cntrl[1].bank0_n_44 ),\n .bm_end_r1_reg_3(bm_end_r1_reg_1),\n .cmd(cmd),\n .\\cmd_pipe_plus.mc_address_reg[14] (req_row_r[14:0]),\n .\\cmd_pipe_plus.mc_address_reg[24] (\\bank_compare0/req_col_r ),\n .\\cmd_pipe_plus.mc_bank_reg[2] (\\cmd_pipe_plus.mc_bank_reg[2] ),\n .\\col_mux.col_data_buf_addr_r_reg[4] (req_data_buf_addr_r[4:0]),\n .col_wait_r_reg(\\bank_cntrl[1].bank0_n_32 ),\n .demand_priority_r(\\bank_state0/demand_priority_r ),\n .demand_priority_r_2(\\bank_state0/demand_priority_r_6 ),\n .demand_priority_r_reg(\\rnk_config_strobe_r_reg[0]_0 ),\n .demanded_prior_r(\\bank_state0/demanded_prior_r ),\n .demanded_prior_r_1(\\bank_state0/demanded_prior_r_5 ),\n .\\entry_cnt_reg[2] (\\entry_cnt_reg[2] ),\n .\\entry_cnt_reg[2]_0 (\\entry_cnt_reg[2]_0 ),\n .\\grant_r_reg[0] (arb_mux0_n_16),\n .\\grant_r_reg[0]_0 (\\cmd_pipe_plus.mc_address_reg[0] [0]),\n .\\grant_r_reg[0]_1 (sending_pre[0]),\n .\\grant_r_reg[1] (\\bank_cntrl[0].bank0_n_46 ),\n .\\grant_r_reg[1]_0 (Q),\n .\\grant_r_reg[1]_1 (arb_mux0_n_62),\n .granted_col_ns(\\arb_row_col0/granted_col_ns ),\n .granted_col_r_reg(\\bank_cntrl[0].bank0_n_32 ),\n .granted_col_r_reg_0(\\bank_cntrl[0].bank0_n_51 ),\n .granted_col_r_reg_1(sent_col),\n .granted_pre_ns(granted_pre_ns),\n .granted_row_r_reg(\\bank_cntrl[0].bank0_n_47 ),\n .head_r_lcl_reg(head_r_lcl_reg_0),\n .head_r_lcl_reg_0(head_r_lcl_reg_1),\n .head_r_lcl_reg_1(head_r_lcl_reg_3),\n .hi_priority(hi_priority),\n .idle_r_lcl_reg(idle_r_lcl_reg),\n .idle_r_lcl_reg_0(head_r[0]),\n .idle_r_lcl_reg_1(idle_r_lcl_reg_1),\n .idle_r_lcl_reg_2(idle_r[1]),\n .\\maint_controller.maint_wip_r_lcl_reg (maint_wip_r),\n .maint_req_r(maint_req_r),\n .\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),\n .of_ctl_full_v(of_ctl_full_v),\n .ofs_rdy_r(\\bank_state0/ofs_rdy_r ),\n .ofs_rdy_r0(\\bank_state0/ofs_rdy_r0 ),\n .\\order_q_r_reg[0] (order_q_r_6),\n .ordered_r_lcl(ordered_r_lcl),\n .ordered_r_lcl_reg(ordered_r_lcl_reg_0),\n .ordered_r_lcl_reg_0(ordered_r_lcl_reg_1),\n .override_demand_ns(override_demand_ns),\n .p_67_out(p_67_out),\n .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg_0),\n .pass_open_bank_r_lcl_reg_0(pass_open_bank_r_lcl_reg_1),\n .pass_open_bank_r_lcl_reg_1(pass_open_bank_r_lcl_reg_2),\n .pass_open_bank_r_lcl_reg_2(pass_open_bank_r_lcl_reg_3),\n .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r),\n .periodic_rd_ack_r_lcl_reg_0(q_has_priority_r_reg_0),\n .periodic_rd_ack_r_lcl_reg_1(wait_for_maint_r_lcl_reg_0),\n .periodic_rd_cntr_r_reg(periodic_rd_cntr_r),\n .periodic_rd_insert(periodic_rd_insert),\n .phy_mc_ctl_full(phy_mc_ctl_full),\n .pre_bm_end_r(pre_bm_end_r),\n .pre_bm_end_r_reg(p_13_out),\n .pre_passing_open_bank_r(\\bank_queue0/pre_passing_open_bank_r ),\n .pre_passing_open_bank_r_0(\\bank_queue0/pre_passing_open_bank_r_3 ),\n .pre_wait_r_reg(rtp_timer_r[0]),\n .pre_wait_r_reg_0(rtp_timer_r[1]),\n .q_entry_r(q_entry_r),\n .\\q_entry_r_reg[0] (\\q_entry_r_reg[0]_2 ),\n .\\q_entry_r_reg[0]_0 (\\q_entry_r_reg[0]_3 ),\n .\\ras_timer_r_reg[0] (\\bank_cntrl[0].bank0_n_40 ),\n .\\ras_timer_r_reg[1] (\\bank_cntrl[0].bank0_n_39 ),\n .\\ras_timer_r_reg[2] (\\bank_cntrl[0].bank0_n_38 ),\n .\\ras_timer_r_reg[2]_0 (\\bank_cntrl[1].bank0_n_45 ),\n .rb_hit_busies_ns(\\bank_queue0/rb_hit_busies_ns ),\n .rb_hit_busies_r(rb_hit_busies_r_0),\n .rb_hit_busy_r(rb_hit_busy_r),\n .rb_hit_busy_r_reg(q_has_priority_r_reg),\n .rd_this_rank_r(rd_this_rank_r[0]),\n .\\rd_this_rank_r_reg[0] (rd_wr_r[0]),\n .rd_wr_r_lcl_reg(rd_wr_r[1]),\n .rd_wr_r_lcl_reg_0(\\bank_cntrl[1].bank0_n_43 ),\n .req_bank_rdy_ns(req_bank_rdy_ns),\n .req_bank_rdy_ns_1(req_bank_rdy_ns_1),\n .req_bank_rdy_r(\\bank_state0/req_bank_rdy_r ),\n .req_bank_rdy_r_reg(order_q_r),\n .req_bank_rdy_r_reg_0(req_bank_rdy_r_reg),\n .req_bank_rdy_r_reg_1(arb_mux0_n_66),\n .req_periodic_rd_r(req_periodic_rd_r[0]),\n .req_wr_r_lcl_reg(req_wr_r_lcl_reg),\n .req_wr_r_lcl_reg_0(\\bank_cntrl[1].bank0_n_42 ),\n .req_wr_r_lcl_reg_1(req_wr_r[1]),\n .rnk_config_strobe_ns(\\arb_row_col0/rnk_config_strobe_ns ),\n .\\rnk_config_strobe_r_reg[0] (\\rnk_config_strobe_r_reg[0] ),\n .\\rnk_config_strobe_r_reg[0]_0 (arb_mux0_n_60),\n .\\rnk_config_strobe_r_reg[0]_1 (arb_mux0_n_59),\n .rnk_config_valid_r_lcl_reg(rnk_config_valid_r),\n .row_hit_r(row_hit_r),\n .\\rp_timer.rp_timer_r_reg[1] (pre_wait_r),\n .\\rp_timer.rp_timer_r_reg[1]_0 (auto_pre_r),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .set_order_q_7(set_order_q_7),\n .tail_r(tail_r),\n .use_addr(use_addr),\n .wait_for_maint_ns(\\bank_queue0/wait_for_maint_ns ),\n .wait_for_maint_r_lcl_reg(wait_for_maint_r),\n .was_wr(was_wr),\n .wr_this_rank_r(wr_this_rank_r[0]),\n .\\wtr_timer.wtr_cnt_r_reg[1] (\\wtr_timer.wtr_cnt_r_reg[1] ));\n ddr3_ifmig_7series_v4_0_bank_cntrl__parameterized0 \\bank_cntrl[1].bank0 \n (.CLK(CLK),\n .D({bank_common0_n_10,bank_common0_n_11}),\n .E(idle_r[1]),\n .Q(\\bank_compare0/req_cmd_r_2 ),\n .SR(SR),\n .accept_internal_r(accept_internal_r),\n .accept_r_reg(pass_open_bank_r_lcl_reg),\n .act_this_rank_r(act_this_rank_r[1]),\n .act_wait_r_lcl_reg(\\act_this_rank_r_reg[0] ),\n .\\app_addr_r1_reg[12] (\\app_addr_r1_reg[12] ),\n .\\app_addr_r1_reg[27] (\\app_addr_r1_reg[27] ),\n .\\app_addr_r1_reg[9] (\\app_addr_r1_reg[9] ),\n .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg),\n .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_2),\n .bm_end_r1_0(bm_end_r1_0),\n .bm_end_r1_reg(req_wr_r[1]),\n .bm_end_r1_reg_0(p_13_out),\n .bm_end_r1_reg_1(bm_end_r1_reg_0),\n .bm_end_r1_reg_2(bm_end_r1_reg_2),\n .bm_end_r1_reg_3(\\bank_cntrl[0].bank0_n_39 ),\n .bm_end_r1_reg_4(\\bank_cntrl[0].bank0_n_38 ),\n .cmd(cmd),\n .\\cmd_pipe_plus.mc_address_reg[10] (\\cmd_pipe_plus.mc_address_reg[25] [10]),\n .\\cmd_pipe_plus.mc_address_reg[14] ({req_row_r[29:26],req_row_r[24:15]}),\n .\\cmd_pipe_plus.mc_address_reg[24] (\\bank_compare0/req_col_r_1 ),\n .\\cmd_pipe_plus.mc_address_reg[40] (\\cmd_pipe_plus.mc_address_reg[40] ),\n .\\cmd_pipe_plus.mc_bank_reg[2] (\\cmd_pipe_plus.mc_bank_reg[2]_0 ),\n .\\col_mux.col_data_buf_addr_r_reg[4] (req_data_buf_addr_r[9:5]),\n .demand_priority_r(\\bank_state0/demand_priority_r_6 ),\n .demand_priority_r_2(\\bank_state0/demand_priority_r ),\n .demanded_prior_r(\\bank_state0/demanded_prior_r_5 ),\n .demanded_prior_r_1(\\bank_state0/demanded_prior_r ),\n .\\grant_r_reg[0] (arb_mux0_n_16),\n .\\grant_r_reg[0]_0 (arb_mux0_n_68),\n .\\grant_r_reg[0]_1 (arb_mux0_n_58),\n .\\grant_r_reg[1] (Q),\n .\\grant_r_reg[1]_0 (\\cmd_pipe_plus.mc_address_reg[0] [1]),\n .\\grant_r_reg[1]_1 (sending_pre),\n .granted_col_r_reg(\\bank_cntrl[1].bank0_n_32 ),\n .granted_col_r_reg_0(sent_col),\n .granted_row_ns(granted_row_ns),\n .granted_row_r_reg(\\bank_cntrl[1].bank0_n_62 ),\n .head_r_lcl_reg(head_r_lcl_reg),\n .head_r_lcl_reg_0(head_r_lcl_reg_4),\n .head_r_lcl_reg_1(\\bank_cntrl[0].bank0_n_47 ),\n .hi_priority(hi_priority),\n .idle_r_lcl_reg(idle_r_lcl_reg_0),\n .idle_r_lcl_reg_0(head_r[1]),\n .idle_r_lcl_reg_1(idle_r_lcl_reg_2),\n .idle_r_lcl_reg_2(idle_r_lcl_reg),\n .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6),\n .\\maint_controller.maint_wip_r_lcl_reg (maint_wip_r),\n .maint_req_r(maint_req_r),\n .mc_cs_n_ns(mc_cs_n_ns),\n .\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),\n .ofs_rdy_r(\\bank_state0/ofs_rdy_r_4 ),\n .ofs_rdy_r0(\\bank_state0/ofs_rdy_r0 ),\n .\\order_q_r_reg[0] (\\order_q_r_reg[0] ),\n .\\order_q_r_reg[0]_0 (\\bank_cntrl[0].bank0_n_51 ),\n .ordered_r_lcl_reg(ordered_r_lcl_reg),\n .ordered_r_lcl_reg_0(ordered_r_lcl_reg_2),\n .p_28_out(p_28_out),\n .p_9_in(p_9_in),\n .pass_open_bank_r_lcl_reg(clear_req),\n .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r),\n .periodic_rd_ack_r_lcl_reg_0(q_has_priority_r_reg_0),\n .periodic_rd_ack_r_lcl_reg_1(wait_for_maint_r_lcl_reg),\n .periodic_rd_cntr_r_reg(periodic_rd_cntr_r),\n .periodic_rd_insert(periodic_rd_insert),\n .\\pre_4_1_1T_arb.granted_pre_r_reg (\\bank_cntrl[1].bank0_n_67 ),\n .pre_bm_end_r_reg(p_52_out),\n .pre_passing_open_bank_r(\\bank_queue0/pre_passing_open_bank_r_3 ),\n .pre_passing_open_bank_r_0(\\bank_queue0/pre_passing_open_bank_r ),\n .q_entry_r_4(q_entry_r_4),\n .\\q_entry_r_reg[0] (\\q_entry_r_reg[0] ),\n .\\q_entry_r_reg[0]_0 (\\q_entry_r_reg[0]_0 ),\n .\\q_entry_r_reg[0]_1 (\\q_entry_r_reg[0]_1 ),\n .\\q_entry_r_reg[0]_2 (\\q_entry_r_reg[0]_4 ),\n .q_has_priority(q_has_priority),\n .q_has_priority_r_reg(q_has_priority_r_reg),\n .q_has_priority_r_reg_0(q_has_priority_r_reg_1),\n .q_has_rd(q_has_rd),\n .q_has_rd_r_reg(q_has_rd_r_reg_0),\n .\\ras_timer_r_reg[0] (\\bank_cntrl[1].bank0_n_43 ),\n .\\ras_timer_r_reg[1] (\\bank_cntrl[1].bank0_n_44 ),\n .\\ras_timer_r_reg[1]_0 (\\bank_cntrl[0].bank0_n_40 ),\n .\\ras_timer_r_reg[2] (\\bank_cntrl[1].bank0_n_42 ),\n .\\ras_timer_r_reg[2]_0 (\\bank_cntrl[1].bank0_n_45 ),\n .\\ras_timer_r_reg[2]_1 (\\ras_timer_r_reg[2] ),\n .ras_timer_zero_r_reg(ras_timer_zero_r_reg),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] (rb_hit_busies_r),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ),\n .rb_hit_busies_ns(\\bank_queue0/rb_hit_busies_ns ),\n .rb_hit_busies_r(rb_hit_busies_r_0),\n .rb_hit_busy_r(rb_hit_busy_r),\n .\\rcd_timer_gt_2.rcd_timer_r_reg[0] (\\rcd_timer_gt_2.rcd_timer_r_reg[0] ),\n .rd_this_rank_r(rd_this_rank_r[1]),\n .\\rd_this_rank_r_reg[0] (rd_wr_r[1]),\n .rd_wr_r_lcl_reg(req_bank_rdy_r_reg),\n .\\req_bank_r_lcl_reg[0] (\\req_bank_r_lcl_reg[0] ),\n .req_bank_rdy_ns_1(req_bank_rdy_ns_1),\n .req_bank_rdy_r(\\bank_state0/req_bank_rdy_r_7 ),\n .req_bank_rdy_r_reg(order_q_r_6),\n .req_bank_rdy_r_reg_0(arb_mux0_n_67),\n .req_periodic_rd_r(req_periodic_rd_r[1]),\n .\\req_row_r_lcl_reg[10] (req_row_r[10]),\n .req_wr_r_lcl_reg(\\bank_cntrl[0].bank0_n_44 ),\n .\\rnk_config_strobe_r_reg[0] (\\rnk_config_strobe_r_reg[0]_0 ),\n .row_cmd_wr(row_cmd_wr),\n .row_hit_r_0(row_hit_r_0),\n .\\rp_timer.rp_timer_r_reg[1] (auto_pre_r_5),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .rtp_timer_ns1(rtp_timer_ns1),\n .set_order_q(set_order_q),\n .tail_r_3(tail_r_3),\n .use_addr(use_addr),\n .wait_for_maint_ns(\\bank_queue0/wait_for_maint_ns_8 ),\n .wait_for_maint_r_lcl_reg(wait_for_maint_r_2),\n .wr_this_rank_r(wr_this_rank_r[1]),\n .\\wtr_timer.wtr_cnt_r_reg[1] (\\wtr_timer.wtr_cnt_r_reg[1] ));\n ddr3_ifmig_7series_v4_0_bank_common bank_common0\n (.CLK(CLK),\n .D({bank_common0_n_10,bank_common0_n_11}),\n .E(idle_r[1]),\n .Q(\\bank_compare0/req_cmd_r_2 ),\n .SR(SR),\n .accept_internal_r(accept_internal_r),\n .accept_ns(accept_ns),\n .clear_req(clear_req),\n .cmd(cmd),\n .\\generate_maint_cmds.insert_maint_r_lcl_reg_0 (\\generate_maint_cmds.insert_maint_r_lcl_reg ),\n .\\generate_maint_cmds.insert_maint_r_lcl_reg_1 (\\generate_maint_cmds.insert_maint_r_lcl_reg_0 ),\n .head_r(head_r),\n .head_r_lcl_reg(bank_common0_n_4),\n .head_r_lcl_reg_0(head_r_lcl_reg_2),\n .idle_r(idle_r[0]),\n .idle_r_lcl_reg(idle_r_lcl_reg),\n .idle_r_lcl_reg_0(idle_r_lcl_reg_0),\n .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6),\n .insert_maint_r1_lcl_reg(insert_maint_r1_lcl_reg),\n .\\maint_controller.maint_hit_busies_r_reg[0]_0 (maint_wip_r),\n .\\maint_controller.maint_wip_r_lcl_reg_0 (\\maint_controller.maint_wip_r_lcl_reg ),\n .maint_req_r(maint_req_r),\n .maint_srx_r(maint_srx_r),\n .\\maintenance_request.maint_zq_r_lcl_reg (\\maintenance_request.maint_zq_r_lcl_reg ),\n .p_52_out(p_52_out),\n .p_9_in(p_9_in),\n .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg),\n .periodic_rd_insert(periodic_rd_insert),\n .periodic_rd_r(periodic_rd_r),\n .\\periodic_read_request.periodic_rd_r_lcl_reg (\\periodic_read_request.periodic_rd_r_lcl_reg ),\n .q_has_priority_r_reg(q_has_priority_r_reg_0),\n .q_has_rd_r_reg(q_has_rd_r_reg),\n .rb_hit_busy_r(rb_hit_busy_r),\n .rb_hit_busy_r_reg(q_has_priority_r_reg),\n .\\req_cmd_r_reg[1] ({bank_common0_n_14,bank_common0_n_15}),\n .\\req_cmd_r_reg[1]_0 (\\bank_compare0/req_cmd_r ),\n .req_periodic_rd_r_lcl_reg(periodic_rd_cntr_r),\n .req_wr_r_lcl_reg(req_wr_r_lcl_reg),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 (E),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 (\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 (\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6] ),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_1 (\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 ),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .use_addr(use_addr),\n .wait_for_maint_ns(\\bank_queue0/wait_for_maint_ns_8 ),\n .wait_for_maint_ns_0(\\bank_queue0/wait_for_maint_ns ),\n .wait_for_maint_r(wait_for_maint_r),\n .wait_for_maint_r_2(wait_for_maint_r_2),\n .wait_for_maint_r_lcl_reg(wait_for_maint_r_lcl_reg),\n .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg_0),\n .was_wr(was_wr),\n .was_wr_reg_0(periodic_rd_ack_r));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_bank_queue\" *) \nmodule ddr3_ifmig_7series_v4_0_bank_queue\n (\\req_data_buf_addr_r_reg[4] ,\n idle_r_lcl_reg_0,\n wait_for_maint_r_lcl_reg_0,\n bm_end_r1_reg,\n pre_bm_end_r,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ,\n pre_passing_open_bank_r,\n q_has_rd,\n q_has_priority,\n tail_r,\n q_entry_r,\n idle_r_lcl_reg_1,\n \\rp_timer.rp_timer_r_reg[1] ,\n ordered_r_lcl,\n req_bank_rdy_r_reg,\n rd_wr_ns,\n head_r_lcl_reg_0,\n head_r_lcl_reg_1,\n bm_end_r1_reg_0,\n set_order_q_7,\n D,\n \\ras_timer_r_reg[2] ,\n act_wait_ns,\n \\q_entry_r_reg[0]_0 ,\n granted_row_r_reg,\n CLK,\n wait_for_maint_ns,\n pass_open_bank_r_lcl_reg_0,\n pre_bm_end_ns,\n rb_hit_busies_ns,\n pre_passing_open_bank_ns,\n rstdiv0_sync_r1_reg_rep__0,\n idle_r_lcl_reg_2,\n \\q_entry_r_reg[0]_1 ,\n SR,\n head_r_lcl_reg_2,\n auto_pre_r_lcl_reg_0,\n ordered_r_lcl_reg_0,\n ordered_r_lcl_reg_1,\n cmd,\n periodic_rd_insert,\n rd_wr_r_lcl_reg,\n \\grant_r_reg[0] ,\n periodic_rd_ack_r_lcl_reg,\n use_addr,\n accept_internal_r,\n req_wr_r_lcl_reg,\n pre_bm_end_r_reg_0,\n rb_hit_busy_r_reg,\n rb_hit_busy_r,\n periodic_rd_ack_r_lcl_reg_0,\n periodic_rd_ack_r_lcl_reg_1,\n req_wr_r_lcl_reg_0,\n \\ras_timer_r_reg[2]_0 ,\n bm_end_r1_reg_1,\n bm_end_r1_reg_2,\n bm_end_r1_reg_3,\n rd_wr_r_lcl_reg_0,\n \\ras_timer_r_reg[1] ,\n \\grant_r_reg[0]_0 ,\n act_wait_r_lcl_reg,\n bm_end_r1_reg_4,\n req_wr_r_lcl_reg_1,\n pre_passing_open_bank_r_0,\n maint_req_r,\n was_wr,\n accept_r_reg,\n rstdiv0_sync_r1_reg_rep__21,\n app_hi_pri_r2,\n idle_r_lcl_reg_3,\n accept_r_reg_0,\n ras_timer_zero_r,\n \\grant_r_reg[1] );\n output \\req_data_buf_addr_r_reg[4] ;\n output idle_r_lcl_reg_0;\n output wait_for_maint_r_lcl_reg_0;\n output bm_end_r1_reg;\n output pre_bm_end_r;\n output \\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ;\n output pre_passing_open_bank_r;\n output q_has_rd;\n output q_has_priority;\n output tail_r;\n output q_entry_r;\n output idle_r_lcl_reg_1;\n output \\rp_timer.rp_timer_r_reg[1] ;\n output ordered_r_lcl;\n output req_bank_rdy_r_reg;\n output rd_wr_ns;\n output head_r_lcl_reg_0;\n output head_r_lcl_reg_1;\n output bm_end_r1_reg_0;\n output set_order_q_7;\n output [2:0]D;\n output \\ras_timer_r_reg[2] ;\n output act_wait_ns;\n output \\q_entry_r_reg[0]_0 ;\n output granted_row_r_reg;\n input CLK;\n input wait_for_maint_ns;\n input pass_open_bank_r_lcl_reg_0;\n input pre_bm_end_ns;\n input rb_hit_busies_ns;\n input pre_passing_open_bank_ns;\n input rstdiv0_sync_r1_reg_rep__0;\n input idle_r_lcl_reg_2;\n input \\q_entry_r_reg[0]_1 ;\n input [0:0]SR;\n input head_r_lcl_reg_2;\n input auto_pre_r_lcl_reg_0;\n input ordered_r_lcl_reg_0;\n input ordered_r_lcl_reg_1;\n input [0:0]cmd;\n input periodic_rd_insert;\n input rd_wr_r_lcl_reg;\n input [0:0]\\grant_r_reg[0] ;\n input periodic_rd_ack_r_lcl_reg;\n input use_addr;\n input accept_internal_r;\n input req_wr_r_lcl_reg;\n input pre_bm_end_r_reg_0;\n input rb_hit_busy_r_reg;\n input [0:0]rb_hit_busy_r;\n input periodic_rd_ack_r_lcl_reg_0;\n input periodic_rd_ack_r_lcl_reg_1;\n input req_wr_r_lcl_reg_0;\n input \\ras_timer_r_reg[2]_0 ;\n input bm_end_r1_reg_1;\n input bm_end_r1_reg_2;\n input bm_end_r1_reg_3;\n input rd_wr_r_lcl_reg_0;\n input \\ras_timer_r_reg[1] ;\n input [0:0]\\grant_r_reg[0]_0 ;\n input act_wait_r_lcl_reg;\n input bm_end_r1_reg_4;\n input req_wr_r_lcl_reg_1;\n input pre_passing_open_bank_r_0;\n input maint_req_r;\n input was_wr;\n input accept_r_reg;\n input rstdiv0_sync_r1_reg_rep__21;\n input app_hi_pri_r2;\n input [0:0]idle_r_lcl_reg_3;\n input accept_r_reg_0;\n input ras_timer_zero_r;\n input \\grant_r_reg[1] ;\n\n wire CLK;\n wire [2:0]D;\n wire [0:0]SR;\n wire accept_internal_r;\n wire accept_r_reg;\n wire accept_r_reg_0;\n wire act_wait_ns;\n wire act_wait_r_lcl_reg;\n wire app_hi_pri_r2;\n wire auto_pre_r_lcl_reg_0;\n wire bm_end_r1_reg;\n wire bm_end_r1_reg_0;\n wire bm_end_r1_reg_1;\n wire bm_end_r1_reg_2;\n wire bm_end_r1_reg_3;\n wire bm_end_r1_reg_4;\n wire [0:0]cmd;\n wire [0:0]\\grant_r_reg[0] ;\n wire [0:0]\\grant_r_reg[0]_0 ;\n wire \\grant_r_reg[1] ;\n wire granted_row_r_reg;\n wire head_r_lcl_reg_0;\n wire head_r_lcl_reg_1;\n wire head_r_lcl_reg_2;\n wire i___6_i_2_n_0;\n wire idle_r_lcl_reg_0;\n wire idle_r_lcl_reg_1;\n wire idle_r_lcl_reg_2;\n wire [0:0]idle_r_lcl_reg_3;\n wire maint_req_r;\n wire ordered_r_lcl;\n wire ordered_r_lcl_reg_0;\n wire ordered_r_lcl_reg_1;\n wire pass_open_bank_r_lcl_reg_0;\n wire periodic_rd_ack_r_lcl_reg;\n wire periodic_rd_ack_r_lcl_reg_0;\n wire periodic_rd_ack_r_lcl_reg_1;\n wire periodic_rd_insert;\n wire pre_bm_end_ns;\n wire pre_bm_end_r;\n wire pre_bm_end_r_reg_0;\n wire pre_passing_open_bank_ns;\n wire pre_passing_open_bank_r;\n wire pre_passing_open_bank_r_0;\n wire q_entry_r;\n wire \\q_entry_r_reg[0]_0 ;\n wire \\q_entry_r_reg[0]_1 ;\n wire q_has_priority;\n wire q_has_priority_ns;\n wire q_has_rd;\n wire q_has_rd_ns;\n wire \\ras_timer_r_reg[1] ;\n wire \\ras_timer_r_reg[2] ;\n wire \\ras_timer_r_reg[2]_0 ;\n wire ras_timer_zero_r;\n wire \\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ;\n wire rb_hit_busies_ns;\n wire [0:0]rb_hit_busy_r;\n wire rb_hit_busy_r_reg;\n wire rd_wr_ns;\n wire rd_wr_r_lcl_reg;\n wire rd_wr_r_lcl_reg_0;\n wire req_bank_rdy_r_reg;\n wire \\req_data_buf_addr_r_reg[4] ;\n wire req_wr_r_lcl_reg;\n wire req_wr_r_lcl_reg_0;\n wire req_wr_r_lcl_reg_1;\n wire \\rp_timer.rp_timer_r_reg[1] ;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire set_order_q_7;\n wire tail_r;\n wire use_addr;\n wire wait_for_maint_ns;\n wire wait_for_maint_r_lcl_reg_0;\n wire was_wr;\n\n LUT6 #(\n .INIT(64'hFFFFFFFF88888F88)) \n act_wait_r_lcl_i_1\n (.I0(bm_end_r1_reg),\n .I1(bm_end_r1_reg_0),\n .I2(\\grant_r_reg[0]_0 ),\n .I3(act_wait_r_lcl_reg),\n .I4(\\ras_timer_r_reg[2] ),\n .I5(bm_end_r1_reg_4),\n .O(act_wait_ns));\n LUT5 #(\n .INIT(32'h00E00000)) \n act_wait_r_lcl_i_2\n (.I0(req_wr_r_lcl_reg_1),\n .I1(pre_passing_open_bank_r_0),\n .I2(q_entry_r),\n .I3(\\req_data_buf_addr_r_reg[4] ),\n .I4(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ),\n .O(\\ras_timer_r_reg[2] ));\n FDRE #(\n .INIT(1'b0)) \n auto_pre_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(auto_pre_r_lcl_reg_0),\n .Q(\\rp_timer.rp_timer_r_reg[1] ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hAAEAEAEA)) \n bm_end_r1_i_1__0\n (.I0(pre_bm_end_r),\n .I1(\\grant_r_reg[0] ),\n .I2(bm_end_r1_reg),\n .I3(rd_wr_r_lcl_reg),\n .I4(req_wr_r_lcl_reg_0),\n .O(bm_end_r1_reg_0));\n FDRE #(\n .INIT(1'b1)) \n \\compute_tail.tail_r_lcl_reg \n (.C(CLK),\n .CE(1'b1),\n .D(idle_r_lcl_reg_2),\n .Q(tail_r),\n .R(rstdiv0_sync_r1_reg_rep__0));\n LUT6 #(\n .INIT(64'h0000000000200000)) \n \\grant_r[1]_i_3__1 \n (.I0(idle_r_lcl_reg_1),\n .I1(wait_for_maint_r_lcl_reg_0),\n .I2(act_wait_r_lcl_reg),\n .I3(\\req_data_buf_addr_r_reg[4] ),\n .I4(ras_timer_zero_r),\n .I5(\\grant_r_reg[1] ),\n .O(granted_row_r_reg));\n FDSE #(\n .INIT(1'b1)) \n head_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(head_r_lcl_reg_2),\n .Q(idle_r_lcl_reg_1),\n .S(SR));\n LUT6 #(\n .INIT(64'h8000800080000000)) \n i___10_i_1\n (.I0(req_wr_r_lcl_reg_0),\n .I1(\\req_data_buf_addr_r_reg[4] ),\n .I2(idle_r_lcl_reg_1),\n .I3(accept_internal_r),\n .I4(use_addr),\n .I5(periodic_rd_ack_r_lcl_reg),\n .O(set_order_q_7));\n LUT6 #(\n .INIT(64'h6969699669966996)) \n i___12_i_2\n (.I0(bm_end_r1_reg_0),\n .I1(\\req_data_buf_addr_r_reg[4] ),\n .I2(idle_r_lcl_reg_3),\n .I3(periodic_rd_ack_r_lcl_reg),\n .I4(accept_r_reg_0),\n .I5(use_addr),\n .O(\\q_entry_r_reg[0]_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFF0F8FFF8)) \n i___5_i_3\n (.I0(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ),\n .I1(pre_bm_end_r_reg_0),\n .I2(periodic_rd_ack_r_lcl_reg_1),\n .I3(\\req_data_buf_addr_r_reg[4] ),\n .I4(periodic_rd_ack_r_lcl_reg_0),\n .I5(bm_end_r1_reg_0),\n .O(head_r_lcl_reg_1));\n LUT6 #(\n .INIT(64'h8BBBB888B8888BBB)) \n i___6_i_1\n (.I0(q_entry_r),\n .I1(i___6_i_2_n_0),\n .I2(pre_bm_end_r_reg_0),\n .I3(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ),\n .I4(rb_hit_busy_r_reg),\n .I5(rb_hit_busy_r),\n .O(head_r_lcl_reg_0));\n LUT5 #(\n .INIT(32'h00880F88)) \n i___6_i_2\n (.I0(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ),\n .I1(pre_bm_end_r_reg_0),\n .I2(periodic_rd_ack_r_lcl_reg_0),\n .I3(\\req_data_buf_addr_r_reg[4] ),\n .I4(periodic_rd_ack_r_lcl_reg_1),\n .O(i___6_i_2_n_0));\n LUT6 #(\n .INIT(64'h02AAAAAAFFFFFFFF)) \n idle_r_lcl_i_1__0\n (.I0(\\req_data_buf_addr_r_reg[4] ),\n .I1(periodic_rd_ack_r_lcl_reg),\n .I2(use_addr),\n .I3(accept_internal_r),\n .I4(idle_r_lcl_reg_1),\n .I5(req_wr_r_lcl_reg),\n .O(idle_r_lcl_reg_0));\n FDRE #(\n .INIT(1'b0)) \n idle_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(idle_r_lcl_reg_0),\n .Q(\\req_data_buf_addr_r_reg[4] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\order_q_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(ordered_r_lcl_reg_1),\n .Q(req_bank_rdy_r_reg),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n ordered_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(ordered_r_lcl_reg_0),\n .Q(ordered_r_lcl),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n pass_open_bank_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pass_open_bank_r_lcl_reg_0),\n .Q(bm_end_r1_reg),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n pre_bm_end_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pre_bm_end_ns),\n .Q(pre_bm_end_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n pre_passing_open_bank_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pre_passing_open_bank_ns),\n .Q(pre_passing_open_bank_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\q_entry_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\q_entry_r_reg[0]_1 ),\n .Q(q_entry_r),\n .R(rstdiv0_sync_r1_reg_rep__0));\n LUT6 #(\n .INIT(64'h1010111010101010)) \n q_has_priority_r_i_1\n (.I0(bm_end_r1_reg_0),\n .I1(rstdiv0_sync_r1_reg_rep__21),\n .I2(q_has_priority),\n .I3(rb_hit_busy_r),\n .I4(periodic_rd_ack_r_lcl_reg_0),\n .I5(app_hi_pri_r2),\n .O(q_has_priority_ns));\n FDRE #(\n .INIT(1'b0)) \n q_has_priority_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(q_has_priority_ns),\n .Q(q_has_priority),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h88A888A888A8AAAA)) \n q_has_rd_r_i_1\n (.I0(req_wr_r_lcl_reg),\n .I1(q_has_rd),\n .I2(maint_req_r),\n .I3(\\req_data_buf_addr_r_reg[4] ),\n .I4(was_wr),\n .I5(accept_r_reg),\n .O(q_has_rd_ns));\n FDRE #(\n .INIT(1'b0)) \n q_has_rd_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(q_has_rd_ns),\n .Q(q_has_rd),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1052\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\ras_timer_r[0]_i_1 \n (.I0(rd_wr_r_lcl_reg_0),\n .I1(\\ras_timer_r_reg[2] ),\n .I2(\\ras_timer_r_reg[1] ),\n .O(D[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1052\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\ras_timer_r[1]_i_1 \n (.I0(bm_end_r1_reg_2),\n .I1(\\ras_timer_r_reg[2] ),\n .I2(bm_end_r1_reg_3),\n .O(D[1]));\n LUT3 #(\n .INIT(8'hB8)) \n \\ras_timer_r[2]_i_1 \n (.I0(\\ras_timer_r_reg[2]_0 ),\n .I1(\\ras_timer_r_reg[2] ),\n .I2(bm_end_r1_reg_1),\n .O(D[2]));\n FDRE #(\n .INIT(1'b0)) \n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(rb_hit_busies_ns),\n .Q(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hE0E0EFE0)) \n rd_wr_r_lcl_i_1__0\n (.I0(cmd),\n .I1(periodic_rd_insert),\n .I2(idle_r_lcl_reg_0),\n .I3(rd_wr_r_lcl_reg),\n .I4(\\grant_r_reg[0] ),\n .O(rd_wr_ns));\n FDRE #(\n .INIT(1'b0)) \n wait_for_maint_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wait_for_maint_ns),\n .Q(wait_for_maint_r_lcl_reg_0),\n .R(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_bank_queue\" *) \nmodule ddr3_ifmig_7series_v4_0_bank_queue__parameterized0\n (\\req_data_buf_addr_r_reg[4] ,\n idle_r_lcl_reg_0,\n wait_for_maint_r_lcl_reg_0,\n bm_end_r1_reg,\n pre_bm_end_r,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ,\n pre_passing_open_bank_r,\n q_has_rd,\n q_has_priority,\n idle_r_lcl_reg_1,\n \\order_q_r_reg[0]_0 ,\n tail_r_3,\n q_entry_r_4,\n \\rp_timer.rp_timer_r_reg[1] ,\n req_bank_rdy_r_reg,\n rb_hit_busies_ns,\n bm_end_r1_reg_0,\n granted_col_r_reg,\n act_wait_r_lcl_reg,\n p_9_in,\n rd_wr_ns,\n demand_priority_ns,\n head_r_lcl_reg_0,\n \\q_entry_r_reg[0]_0 ,\n set_order_q,\n act_wait_ns,\n \\q_entry_r_reg[0]_1 ,\n D,\n granted_row_ns,\n granted_row_r_reg,\n CLK,\n wait_for_maint_ns,\n pass_open_bank_ns,\n pre_bm_end_ns,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ,\n pre_passing_open_bank_ns,\n q_has_rd_r_reg_0,\n q_has_priority_r_reg_0,\n rstdiv0_sync_r1_reg_rep__0,\n head_r_lcl_reg_1,\n ordered_r_lcl_reg_0,\n idle_r_lcl_reg_2,\n SR,\n \\q_entry_r_reg[0]_2 ,\n auto_pre_r_lcl_reg_0,\n ordered_r_lcl_reg_1,\n \\req_bank_r_lcl_reg[0] ,\n rb_hit_busies_r,\n idle_r_lcl_reg_3,\n rstdiv0_sync_r1_reg_rep__20,\n \\wtr_timer.wtr_cnt_r_reg[1] ,\n col_wait_r,\n \\order_q_r_reg[0]_1 ,\n rd_wr_r_lcl_reg,\n \\grant_r_reg[0] ,\n init_calib_complete_reg_rep__6,\n cmd,\n periodic_rd_insert,\n \\grant_r_reg[1] ,\n demand_priority_r_reg,\n req_priority_r,\n col_wait_r_reg,\n req_wr_r_lcl_reg,\n periodic_rd_ack_r_lcl_reg,\n use_addr,\n accept_internal_r,\n periodic_rd_ack_r_lcl_reg_0,\n periodic_rd_ack_r_lcl_reg_1,\n rb_hit_busy_r_reg,\n pre_bm_end_r_reg_0,\n req_wr_r_lcl_reg_0,\n bm_end_r1_reg_1,\n \\grant_r_reg[1]_0 ,\n act_wait_r_lcl_reg_0,\n rb_hit_busy_r_reg_0,\n rb_hit_busy_r,\n \\ras_timer_r_reg[1] ,\n rd_wr_r_lcl_reg_0,\n bm_end_r1_reg_2,\n bm_end_r1_reg_3,\n bm_end_r1_reg_4,\n \\ras_timer_r_reg[2] ,\n req_wr_r_lcl_reg_1,\n pre_passing_open_bank_r_0,\n head_r_lcl_reg_2,\n ras_timer_zero_r,\n \\grant_r_reg[0]_0 ,\n rd_wr_r_lcl_reg_1);\n output \\req_data_buf_addr_r_reg[4] ;\n output idle_r_lcl_reg_0;\n output wait_for_maint_r_lcl_reg_0;\n output bm_end_r1_reg;\n output pre_bm_end_r;\n output \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ;\n output pre_passing_open_bank_r;\n output q_has_rd;\n output q_has_priority;\n output idle_r_lcl_reg_1;\n output \\order_q_r_reg[0]_0 ;\n output tail_r_3;\n output q_entry_r_4;\n output \\rp_timer.rp_timer_r_reg[1] ;\n output req_bank_rdy_r_reg;\n output rb_hit_busies_ns;\n output bm_end_r1_reg_0;\n output granted_col_r_reg;\n output act_wait_r_lcl_reg;\n output p_9_in;\n output rd_wr_ns;\n output demand_priority_ns;\n output head_r_lcl_reg_0;\n output \\q_entry_r_reg[0]_0 ;\n output set_order_q;\n output act_wait_ns;\n output \\q_entry_r_reg[0]_1 ;\n output [2:0]D;\n output granted_row_ns;\n output granted_row_r_reg;\n input CLK;\n input wait_for_maint_ns;\n input pass_open_bank_ns;\n input pre_bm_end_ns;\n input \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ;\n input pre_passing_open_bank_ns;\n input q_has_rd_r_reg_0;\n input q_has_priority_r_reg_0;\n input rstdiv0_sync_r1_reg_rep__0;\n input head_r_lcl_reg_1;\n input ordered_r_lcl_reg_0;\n input idle_r_lcl_reg_2;\n input [0:0]SR;\n input \\q_entry_r_reg[0]_2 ;\n input auto_pre_r_lcl_reg_0;\n input ordered_r_lcl_reg_1;\n input \\req_bank_r_lcl_reg[0] ;\n input [0:0]rb_hit_busies_r;\n input [0:0]idle_r_lcl_reg_3;\n input rstdiv0_sync_r1_reg_rep__20;\n input \\wtr_timer.wtr_cnt_r_reg[1] ;\n input col_wait_r;\n input \\order_q_r_reg[0]_1 ;\n input rd_wr_r_lcl_reg;\n input \\grant_r_reg[0] ;\n input init_calib_complete_reg_rep__6;\n input [0:0]cmd;\n input periodic_rd_insert;\n input [0:0]\\grant_r_reg[1] ;\n input demand_priority_r_reg;\n input req_priority_r;\n input col_wait_r_reg;\n input req_wr_r_lcl_reg;\n input periodic_rd_ack_r_lcl_reg;\n input use_addr;\n input accept_internal_r;\n input periodic_rd_ack_r_lcl_reg_0;\n input periodic_rd_ack_r_lcl_reg_1;\n input rb_hit_busy_r_reg;\n input pre_bm_end_r_reg_0;\n input req_wr_r_lcl_reg_0;\n input bm_end_r1_reg_1;\n input [0:0]\\grant_r_reg[1]_0 ;\n input act_wait_r_lcl_reg_0;\n input rb_hit_busy_r_reg_0;\n input [0:0]rb_hit_busy_r;\n input \\ras_timer_r_reg[1] ;\n input rd_wr_r_lcl_reg_0;\n input bm_end_r1_reg_2;\n input bm_end_r1_reg_3;\n input bm_end_r1_reg_4;\n input \\ras_timer_r_reg[2] ;\n input req_wr_r_lcl_reg_1;\n input pre_passing_open_bank_r_0;\n input head_r_lcl_reg_2;\n input ras_timer_zero_r;\n input \\grant_r_reg[0]_0 ;\n input rd_wr_r_lcl_reg_1;\n\n wire CLK;\n wire [2:0]D;\n wire [0:0]SR;\n wire accept_internal_r;\n wire act_wait_ns;\n wire act_wait_r_lcl_reg;\n wire act_wait_r_lcl_reg_0;\n wire auto_pre_r_lcl_reg_0;\n wire bm_end_r1_reg;\n wire bm_end_r1_reg_0;\n wire bm_end_r1_reg_1;\n wire bm_end_r1_reg_2;\n wire bm_end_r1_reg_3;\n wire bm_end_r1_reg_4;\n wire [0:0]cmd;\n wire col_wait_r;\n wire col_wait_r_reg;\n wire demand_priority_ns;\n wire demand_priority_r_i_3__0_n_0;\n wire demand_priority_r_reg;\n wire \\grant_r_reg[0] ;\n wire \\grant_r_reg[0]_0 ;\n wire [0:0]\\grant_r_reg[1] ;\n wire [0:0]\\grant_r_reg[1]_0 ;\n wire granted_col_r_reg;\n wire granted_row_ns;\n wire granted_row_r_reg;\n wire head_r_lcl_reg_0;\n wire head_r_lcl_reg_1;\n wire head_r_lcl_reg_2;\n wire i___7_i_3_n_0;\n wire idle_r_lcl_reg_0;\n wire idle_r_lcl_reg_1;\n wire idle_r_lcl_reg_2;\n wire [0:0]idle_r_lcl_reg_3;\n wire init_calib_complete_reg_rep__6;\n wire \\order_q_r_reg[0]_0 ;\n wire \\order_q_r_reg[0]_1 ;\n wire ordered_r_lcl_reg_0;\n wire ordered_r_lcl_reg_1;\n wire p_9_in;\n wire pass_open_bank_ns;\n wire periodic_rd_ack_r_lcl_reg;\n wire periodic_rd_ack_r_lcl_reg_0;\n wire periodic_rd_ack_r_lcl_reg_1;\n wire periodic_rd_insert;\n wire pre_bm_end_ns;\n wire pre_bm_end_r;\n wire pre_bm_end_r_reg_0;\n wire pre_passing_open_bank_ns;\n wire pre_passing_open_bank_r;\n wire pre_passing_open_bank_r_0;\n wire q_entry_r_4;\n wire \\q_entry_r_reg[0]_0 ;\n wire \\q_entry_r_reg[0]_1 ;\n wire \\q_entry_r_reg[0]_2 ;\n wire q_has_priority;\n wire q_has_priority_r_reg_0;\n wire q_has_rd;\n wire q_has_rd_r_reg_0;\n wire \\ras_timer_r_reg[1] ;\n wire \\ras_timer_r_reg[2] ;\n wire ras_timer_zero_r;\n wire \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ;\n wire \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ;\n wire rb_hit_busies_ns;\n wire [0:0]rb_hit_busies_r;\n wire [0:0]rb_hit_busy_r;\n wire rb_hit_busy_r_reg;\n wire rb_hit_busy_r_reg_0;\n wire rd_wr_ns;\n wire rd_wr_r_lcl_reg;\n wire rd_wr_r_lcl_reg_0;\n wire rd_wr_r_lcl_reg_1;\n wire \\req_bank_r_lcl_reg[0] ;\n wire req_bank_rdy_r_reg;\n wire \\req_data_buf_addr_r_reg[4] ;\n wire req_priority_r;\n wire req_wr_r_lcl_reg;\n wire req_wr_r_lcl_reg_0;\n wire req_wr_r_lcl_reg_1;\n wire \\rp_timer.rp_timer_r_reg[1] ;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire set_order_q;\n wire tail_r_3;\n wire use_addr;\n wire wait_for_maint_ns;\n wire wait_for_maint_r_lcl_reg_0;\n wire \\wtr_timer.wtr_cnt_r_reg[1] ;\n\n LUT3 #(\n .INIT(8'hA8)) \n accept_internal_r_i_1\n (.I0(init_calib_complete_reg_rep__6),\n .I1(idle_r_lcl_reg_0),\n .I2(idle_r_lcl_reg_3),\n .O(p_9_in));\n LUT6 #(\n .INIT(64'hEAEAEAEAEAFFEAEA)) \n act_wait_r_lcl_i_1__0\n (.I0(bm_end_r1_reg_1),\n .I1(bm_end_r1_reg_0),\n .I2(bm_end_r1_reg),\n .I3(\\grant_r_reg[1]_0 ),\n .I4(act_wait_r_lcl_reg_0),\n .I5(act_wait_r_lcl_reg),\n .O(act_wait_ns));\n LUT5 #(\n .INIT(32'h00E00000)) \n act_wait_r_lcl_i_3\n (.I0(req_wr_r_lcl_reg_1),\n .I1(pre_passing_open_bank_r_0),\n .I2(q_entry_r_4),\n .I3(\\req_data_buf_addr_r_reg[4] ),\n .I4(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ),\n .O(act_wait_r_lcl_reg));\n FDRE #(\n .INIT(1'b0)) \n auto_pre_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(auto_pre_r_lcl_reg_0),\n .Q(\\rp_timer.rp_timer_r_reg[1] ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hAAEAEAEA)) \n bm_end_r1_i_1\n (.I0(pre_bm_end_r),\n .I1(\\grant_r_reg[1] ),\n .I2(bm_end_r1_reg),\n .I3(rd_wr_r_lcl_reg),\n .I4(req_wr_r_lcl_reg_0),\n .O(bm_end_r1_reg_0));\n FDRE #(\n .INIT(1'b1)) \n \\compute_tail.tail_r_lcl_reg \n (.C(CLK),\n .CE(1'b1),\n .D(idle_r_lcl_reg_2),\n .Q(tail_r_3),\n .R(rstdiv0_sync_r1_reg_rep__0));\n LUT6 #(\n .INIT(64'h000000000000AAFE)) \n demand_priority_r_i_1\n (.I0(demand_priority_r_reg),\n .I1(req_priority_r),\n .I2(q_has_priority),\n .I3(demand_priority_r_i_3__0_n_0),\n .I4(col_wait_r_reg),\n .I5(idle_r_lcl_reg_0),\n .O(demand_priority_ns));\n LUT3 #(\n .INIT(8'h08)) \n demand_priority_r_i_3__0\n (.I0(rd_wr_r_lcl_reg_1),\n .I1(req_bank_rdy_r_reg),\n .I2(rd_wr_r_lcl_reg),\n .O(demand_priority_r_i_3__0_n_0));\n LUT6 #(\n .INIT(64'h00A800FC00A80000)) \n \\grant_r[1]_i_2 \n (.I0(\\wtr_timer.wtr_cnt_r_reg[1] ),\n .I1(act_wait_r_lcl_reg),\n .I2(col_wait_r),\n .I3(\\order_q_r_reg[0]_1 ),\n .I4(rd_wr_r_lcl_reg),\n .I5(\\grant_r_reg[0] ),\n .O(granted_col_r_reg));\n LUT6 #(\n .INIT(64'h0000000000200000)) \n \\grant_r[1]_i_2__0 \n (.I0(idle_r_lcl_reg_1),\n .I1(wait_for_maint_r_lcl_reg_0),\n .I2(act_wait_r_lcl_reg_0),\n .I3(\\req_data_buf_addr_r_reg[4] ),\n .I4(ras_timer_zero_r),\n .I5(\\grant_r_reg[0]_0 ),\n .O(granted_row_r_reg));\n LUT2 #(\n .INIT(4'hE)) \n granted_row_r_i_1\n (.I0(granted_row_r_reg),\n .I1(head_r_lcl_reg_2),\n .O(granted_row_ns));\n FDRE #(\n .INIT(1'b0)) \n head_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(head_r_lcl_reg_1),\n .Q(idle_r_lcl_reg_1),\n .R(rstdiv0_sync_r1_reg_rep__0));\n LUT6 #(\n .INIT(64'h8000800080000000)) \n i___14_i_1\n (.I0(req_wr_r_lcl_reg_0),\n .I1(\\req_data_buf_addr_r_reg[4] ),\n .I2(idle_r_lcl_reg_1),\n .I3(accept_internal_r),\n .I4(use_addr),\n .I5(periodic_rd_ack_r_lcl_reg),\n .O(set_order_q));\n LUT4 #(\n .INIT(16'h8778)) \n i___5_i_2\n (.I0(bm_end_r1_reg_0),\n .I1(rb_hit_busies_r),\n .I2(rb_hit_busy_r_reg_0),\n .I3(rb_hit_busy_r),\n .O(\\q_entry_r_reg[0]_1 ));\n LUT6 #(\n .INIT(64'hBBBBBABB88888A88)) \n i___7_i_1\n (.I0(q_entry_r_4),\n .I1(i___7_i_3_n_0),\n .I2(periodic_rd_ack_r_lcl_reg_0),\n .I3(\\req_data_buf_addr_r_reg[4] ),\n .I4(periodic_rd_ack_r_lcl_reg_1),\n .I5(rb_hit_busy_r_reg),\n .O(head_r_lcl_reg_0));\n LUT6 #(\n .INIT(64'hEFFFEFEEEFEEEFEE)) \n i___7_i_2\n (.I0(bm_end_r1_reg_0),\n .I1(periodic_rd_ack_r_lcl_reg_1),\n .I2(periodic_rd_ack_r_lcl_reg_0),\n .I3(\\req_data_buf_addr_r_reg[4] ),\n .I4(pre_bm_end_r_reg_0),\n .I5(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ),\n .O(\\q_entry_r_reg[0]_0 ));\n LUT3 #(\n .INIT(8'h08)) \n i___7_i_3\n (.I0(pre_bm_end_r_reg_0),\n .I1(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ),\n .I2(\\req_data_buf_addr_r_reg[4] ),\n .O(i___7_i_3_n_0));\n LUT6 #(\n .INIT(64'hAAAEEEEEEEEEEEEE)) \n idle_r_lcl_i_1\n (.I0(req_wr_r_lcl_reg),\n .I1(\\req_data_buf_addr_r_reg[4] ),\n .I2(periodic_rd_ack_r_lcl_reg),\n .I3(use_addr),\n .I4(accept_internal_r),\n .I5(idle_r_lcl_reg_1),\n .O(idle_r_lcl_reg_0));\n FDRE #(\n .INIT(1'b0)) \n idle_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(idle_r_lcl_reg_0),\n .Q(\\req_data_buf_addr_r_reg[4] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\order_q_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(ordered_r_lcl_reg_1),\n .Q(req_bank_rdy_r_reg),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n ordered_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(ordered_r_lcl_reg_0),\n .Q(\\order_q_r_reg[0]_0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n pass_open_bank_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pass_open_bank_ns),\n .Q(bm_end_r1_reg),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n pre_bm_end_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pre_bm_end_ns),\n .Q(pre_bm_end_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n pre_passing_open_bank_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pre_passing_open_bank_ns),\n .Q(pre_passing_open_bank_r),\n .R(1'b0));\n FDSE #(\n .INIT(1'b1)) \n \\q_entry_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\q_entry_r_reg[0]_2 ),\n .Q(q_entry_r_4),\n .S(SR));\n FDRE #(\n .INIT(1'b0)) \n q_has_priority_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(q_has_priority_r_reg_0),\n .Q(q_has_priority),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n q_has_rd_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(q_has_rd_r_reg_0),\n .Q(q_has_rd),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1058\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\ras_timer_r[0]_i_1__0 \n (.I0(\\ras_timer_r_reg[1] ),\n .I1(act_wait_r_lcl_reg),\n .I2(rd_wr_r_lcl_reg_0),\n .O(D[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1058\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\ras_timer_r[1]_i_1__0 \n (.I0(bm_end_r1_reg_2),\n .I1(act_wait_r_lcl_reg),\n .I2(bm_end_r1_reg_3),\n .O(D[1]));\n LUT3 #(\n .INIT(8'hB8)) \n \\ras_timer_r[2]_i_1__0 \n (.I0(bm_end_r1_reg_4),\n .I1(act_wait_r_lcl_reg),\n .I2(\\ras_timer_r_reg[2] ),\n .O(D[2]));\n LUT6 #(\n .INIT(64'h00000000000022F0)) \n \\rb_hit_busies.rb_hit_busies_r_lcl[1]_i_1 \n (.I0(\\req_bank_r_lcl_reg[0] ),\n .I1(idle_r_lcl_reg_0),\n .I2(rb_hit_busies_r),\n .I3(idle_r_lcl_reg_3),\n .I4(bm_end_r1_reg_0),\n .I5(rstdiv0_sync_r1_reg_rep__20),\n .O(rb_hit_busies_ns));\n FDRE #(\n .INIT(1'b0)) \n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ),\n .Q(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hE0E0EFE0)) \n rd_wr_r_lcl_i_1\n (.I0(cmd),\n .I1(periodic_rd_insert),\n .I2(idle_r_lcl_reg_0),\n .I3(rd_wr_r_lcl_reg),\n .I4(\\grant_r_reg[1] ),\n .O(rd_wr_ns));\n FDRE #(\n .INIT(1'b0)) \n wait_for_maint_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wait_for_maint_ns),\n .Q(wait_for_maint_r_lcl_reg_0),\n .R(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_bank_state\" *) \nmodule ddr3_ifmig_7series_v4_0_bank_state\n (\\act_this_rank_r_reg[0]_0 ,\n bm_end_r1,\n ras_timer_zero_r,\n \\rp_timer.rp_timer_r_reg[1]_0 ,\n act_this_rank_r,\n req_bank_rdy_r,\n demanded_prior_r_reg_0,\n demanded_prior_r_reg_1,\n ofs_rdy_r,\n wr_this_rank_r,\n rd_this_rank_r,\n col_wait_r,\n ofs_rdy_r0,\n pre_wait_r_reg_0,\n pre_wait_r_reg_1,\n pre_bm_end_ns,\n pre_passing_open_bank_ns,\n \\ras_timer_r_reg[1]_0 ,\n \\ras_timer_r_reg[2]_0 ,\n granted_pre_ns,\n \\grant_r_reg[1] ,\n rnk_config_strobe_ns,\n \\rnk_config_strobe_r_reg[0] ,\n granted_col_r_reg,\n \\ras_timer_r_reg[0]_0 ,\n auto_pre_r_lcl_reg,\n granted_col_r_reg_0,\n act_wait_ns,\n CLK,\n pre_bm_end_r_reg,\n req_bank_rdy_ns,\n override_demand_ns,\n rstdiv0_sync_r1_reg_rep__0,\n phy_mc_ctl_full,\n SR,\n of_ctl_full_v,\n start_wtp_timer0,\n rd_wr_r_lcl_reg,\n \\entry_cnt_reg[2] ,\n \\entry_cnt_reg[2]_0 ,\n rd_wr_r_lcl_reg_0,\n req_priority_r,\n q_has_priority,\n \\order_q_r_reg[0] ,\n idle_r_lcl_reg,\n \\grant_r_reg[1]_0 ,\n pre_passing_open_bank_r_reg,\n pass_open_bank_r_lcl_reg,\n pass_open_bank_r_lcl_reg_0,\n rd_wr_r_lcl_reg_1,\n bm_end_r1_reg_0,\n rstdiv0_sync_r1_reg_rep__21,\n \\grant_r_reg[0] ,\n \\grant_r_reg[0]_0 ,\n auto_pre_r_lcl_reg_0,\n auto_pre_r_lcl_reg_1,\n req_bank_rdy_ns_1,\n demand_priority_r_reg_0,\n rnk_config_valid_r_lcl_reg,\n \\rnk_config_strobe_r_reg[0]_0 ,\n rd_wr_r_lcl_reg_2,\n \\order_q_r_reg[0]_0 ,\n tail_r,\n accept_r_reg,\n demanded_prior_r_1,\n demand_priority_r_2,\n q_has_rd,\n req_wr_r_lcl_reg,\n req_bank_rdy_r_reg_0,\n D,\n rstdiv0_sync_r1_reg_rep__20,\n pass_open_bank_r_lcl_reg_1,\n pass_open_bank_r_lcl_reg_2,\n granted_col_r_reg_1);\n output \\act_this_rank_r_reg[0]_0 ;\n output bm_end_r1;\n output ras_timer_zero_r;\n output \\rp_timer.rp_timer_r_reg[1]_0 ;\n output [0:0]act_this_rank_r;\n output req_bank_rdy_r;\n output demanded_prior_r_reg_0;\n output demanded_prior_r_reg_1;\n output ofs_rdy_r;\n output [0:0]wr_this_rank_r;\n output [0:0]rd_this_rank_r;\n output col_wait_r;\n output ofs_rdy_r0;\n output pre_wait_r_reg_0;\n output pre_wait_r_reg_1;\n output pre_bm_end_ns;\n output pre_passing_open_bank_ns;\n output \\ras_timer_r_reg[1]_0 ;\n output \\ras_timer_r_reg[2]_0 ;\n output granted_pre_ns;\n output \\grant_r_reg[1] ;\n output rnk_config_strobe_ns;\n output \\rnk_config_strobe_r_reg[0] ;\n output granted_col_r_reg;\n output \\ras_timer_r_reg[0]_0 ;\n output auto_pre_r_lcl_reg;\n output granted_col_r_reg_0;\n input act_wait_ns;\n input CLK;\n input pre_bm_end_r_reg;\n input req_bank_rdy_ns;\n input override_demand_ns;\n input rstdiv0_sync_r1_reg_rep__0;\n input phy_mc_ctl_full;\n input [0:0]SR;\n input [0:0]of_ctl_full_v;\n input start_wtp_timer0;\n input rd_wr_r_lcl_reg;\n input \\entry_cnt_reg[2] ;\n input \\entry_cnt_reg[2]_0 ;\n input rd_wr_r_lcl_reg_0;\n input req_priority_r;\n input q_has_priority;\n input \\order_q_r_reg[0] ;\n input [0:0]idle_r_lcl_reg;\n input [1:0]\\grant_r_reg[1]_0 ;\n input pre_passing_open_bank_r_reg;\n input pass_open_bank_r_lcl_reg;\n input pass_open_bank_r_lcl_reg_0;\n input rd_wr_r_lcl_reg_1;\n input bm_end_r1_reg_0;\n input rstdiv0_sync_r1_reg_rep__21;\n input [0:0]\\grant_r_reg[0] ;\n input [0:0]\\grant_r_reg[0]_0 ;\n input auto_pre_r_lcl_reg_0;\n input auto_pre_r_lcl_reg_1;\n input req_bank_rdy_ns_1;\n input demand_priority_r_reg_0;\n input rnk_config_valid_r_lcl_reg;\n input \\rnk_config_strobe_r_reg[0]_0 ;\n input rd_wr_r_lcl_reg_2;\n input \\order_q_r_reg[0]_0 ;\n input tail_r;\n input accept_r_reg;\n input demanded_prior_r_1;\n input demand_priority_r_2;\n input q_has_rd;\n input req_wr_r_lcl_reg;\n input req_bank_rdy_r_reg_0;\n input [2:0]D;\n input rstdiv0_sync_r1_reg_rep__20;\n input pass_open_bank_r_lcl_reg_1;\n input pass_open_bank_r_lcl_reg_2;\n input granted_col_r_reg_1;\n\n wire CLK;\n wire [2:0]D;\n wire [0:0]SR;\n wire accept_r_reg;\n wire [0:0]act_this_rank_r;\n wire \\act_this_rank_r_reg[0]_0 ;\n wire act_wait_ns;\n wire auto_pre_r_lcl_reg;\n wire auto_pre_r_lcl_reg_0;\n wire auto_pre_r_lcl_reg_1;\n wire \\bank_cntrl[1].bank0/bank_state0/phy_mc_cmd_full_r ;\n wire \\bank_cntrl[1].bank0/bank_state0/phy_mc_ctl_full_r ;\n wire bm_end_r1;\n wire bm_end_r1_reg_0;\n wire col_wait_r;\n wire col_wait_r_i_1_n_0;\n wire demand_priority_ns;\n wire demand_priority_r_2;\n wire demand_priority_r_i_2_n_0;\n wire demand_priority_r_i_4_n_0;\n wire demand_priority_r_reg_0;\n wire demanded_prior_ns;\n wire demanded_prior_r_1;\n wire demanded_prior_r_reg_0;\n wire demanded_prior_r_reg_1;\n wire \\entry_cnt_reg[2] ;\n wire \\entry_cnt_reg[2]_0 ;\n wire \\grant_r[1]_i_8_n_0 ;\n wire [0:0]\\grant_r_reg[0] ;\n wire [0:0]\\grant_r_reg[0]_0 ;\n wire \\grant_r_reg[1] ;\n wire [1:0]\\grant_r_reg[1]_0 ;\n wire granted_col_r_reg;\n wire granted_col_r_reg_0;\n wire granted_col_r_reg_1;\n wire granted_pre_ns;\n wire [0:0]idle_r_lcl_reg;\n wire [0:0]of_ctl_full_v;\n wire ofs_rdy_r;\n wire ofs_rdy_r0;\n wire ofs_rdy_r0_0;\n wire \\order_q_r_reg[0] ;\n wire \\order_q_r_reg[0]_0 ;\n wire override_demand_ns;\n wire override_demand_r;\n wire pass_open_bank_r_lcl_reg;\n wire pass_open_bank_r_lcl_reg_0;\n wire pass_open_bank_r_lcl_reg_1;\n wire pass_open_bank_r_lcl_reg_2;\n wire phy_mc_ctl_full;\n wire pre_bm_end_ns;\n wire pre_bm_end_r_reg;\n wire pre_passing_open_bank_ns;\n wire pre_passing_open_bank_r_reg;\n wire pre_wait_ns;\n wire pre_wait_r_reg_0;\n wire pre_wait_r_reg_1;\n wire q_has_priority;\n wire q_has_rd;\n wire [2:0]ras_timer_r;\n wire \\ras_timer_r[2]_i_4_n_0 ;\n wire \\ras_timer_r_reg[0]_0 ;\n wire \\ras_timer_r_reg[1]_0 ;\n wire \\ras_timer_r_reg[2]_0 ;\n wire ras_timer_zero_ns;\n wire ras_timer_zero_r;\n wire rcd_active_r;\n wire \\rcd_timer_gt_2.rcd_timer_r[0]_i_1_n_0 ;\n wire [0:0]rd_this_rank_r;\n wire rd_wr_r_lcl_reg;\n wire rd_wr_r_lcl_reg_0;\n wire rd_wr_r_lcl_reg_1;\n wire rd_wr_r_lcl_reg_2;\n wire req_bank_rdy_ns;\n wire req_bank_rdy_ns_1;\n wire req_bank_rdy_r;\n wire req_bank_rdy_r_reg_0;\n wire req_priority_r;\n wire req_wr_r_lcl_reg;\n wire rnk_config_strobe_ns;\n wire \\rnk_config_strobe_r_reg[0] ;\n wire \\rnk_config_strobe_r_reg[0]_0 ;\n wire rnk_config_valid_r_lcl_reg;\n wire \\rp_timer.rp_timer_r[0]_i_1_n_0 ;\n wire \\rp_timer.rp_timer_r[1]_i_2_n_0 ;\n wire \\rp_timer.rp_timer_r_reg[1]_0 ;\n wire [0:0]rp_timer_ns;\n wire [1:0]rp_timer_r;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire \\rtp_timer_r[0]_i_1_n_0 ;\n wire start_pre;\n wire start_wtp_timer0;\n wire [1:0]starve_limit_cntr_r;\n wire \\starve_limit_cntr_r[0]_i_1_n_0 ;\n wire \\starve_limit_cntr_r[1]_i_1_n_0 ;\n wire tail_r;\n wire [0:0]wr_this_rank_r;\n\n FDRE #(\n .INIT(1'b0)) \n \\act_this_rank_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\act_this_rank_r_reg[0]_0 ),\n .Q(act_this_rank_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n act_wait_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(act_wait_ns),\n .Q(\\act_this_rank_r_reg[0]_0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n bm_end_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pre_bm_end_r_reg),\n .Q(bm_end_r1),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1055\" *) \n LUT4 #(\n .INIT(16'hFFBA)) \n col_wait_r_i_1\n (.I0(rcd_active_r),\n .I1(\\grant_r_reg[1]_0 [0]),\n .I2(col_wait_r),\n .I3(pre_passing_open_bank_r_reg),\n .O(col_wait_r_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n col_wait_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(col_wait_r_i_1_n_0),\n .Q(col_wait_r),\n .R(SR));\n LUT6 #(\n .INIT(64'h000000000000AAFE)) \n demand_priority_r_i_1__0\n (.I0(demand_priority_r_i_2_n_0),\n .I1(req_priority_r),\n .I2(q_has_priority),\n .I3(\\order_q_r_reg[0] ),\n .I4(demand_priority_r_i_4_n_0),\n .I5(idle_r_lcl_reg),\n .O(demand_priority_ns));\n LUT6 #(\n .INIT(64'hEAAAEAEAAAAAAAAA)) \n demand_priority_r_i_2\n (.I0(demanded_prior_r_reg_0),\n .I1(starve_limit_cntr_r[0]),\n .I2(starve_limit_cntr_r[1]),\n .I3(q_has_rd),\n .I4(req_wr_r_lcl_reg),\n .I5(req_bank_rdy_r_reg_0),\n .O(demand_priority_r_i_2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1055\" *) \n LUT4 #(\n .INIT(16'h0051)) \n demand_priority_r_i_4\n (.I0(pre_passing_open_bank_r_reg),\n .I1(col_wait_r),\n .I2(\\grant_r_reg[1]_0 [0]),\n .I3(rcd_active_r),\n .O(demand_priority_r_i_4_n_0));\n FDRE #(\n .INIT(1'b0)) \n demand_priority_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(demand_priority_ns),\n .Q(demanded_prior_r_reg_0),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00000D00)) \n demanded_prior_r_i_1\n (.I0(demanded_prior_r_reg_0),\n .I1(demanded_prior_r_reg_1),\n .I2(demanded_prior_r_1),\n .I3(demand_priority_r_2),\n .I4(\\grant_r_reg[1]_0 [1]),\n .O(demanded_prior_ns));\n FDRE #(\n .INIT(1'b0)) \n demanded_prior_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(demanded_prior_ns),\n .Q(demanded_prior_r_reg_1),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000100FFFFFFFF)) \n \\grant_r[1]_i_10 \n (.I0(override_demand_r),\n .I1(demanded_prior_r_reg_0),\n .I2(demanded_prior_r_1),\n .I3(demand_priority_r_2),\n .I4(\\grant_r_reg[1]_0 [1]),\n .I5(rnk_config_valid_r_lcl_reg),\n .O(granted_col_r_reg_0));\n (* SOFT_HLUTNM = \"soft_lutpair1053\" *) \n LUT4 #(\n .INIT(16'h1000)) \n \\grant_r[1]_i_3__0 \n (.I0(auto_pre_r_lcl_reg_0),\n .I1(\\grant_r_reg[0]_0 ),\n .I2(\\rp_timer.rp_timer_r_reg[1]_0 ),\n .I3(ras_timer_zero_r),\n .O(\\grant_r_reg[1] ));\n LUT5 #(\n .INIT(32'hEEEEFEEE)) \n \\grant_r[1]_i_5 \n (.I0(\\grant_r[1]_i_8_n_0 ),\n .I1(\\rnk_config_strobe_r_reg[0]_0 ),\n .I2(rd_wr_r_lcl_reg_2),\n .I3(\\order_q_r_reg[0]_0 ),\n .I4(rd_wr_r_lcl_reg_0),\n .O(granted_col_r_reg));\n LUT6 #(\n .INIT(64'h5555555555575555)) \n \\grant_r[1]_i_8 \n (.I0(rnk_config_valid_r_lcl_reg),\n .I1(override_demand_r),\n .I2(demand_priority_r_2),\n .I3(demanded_prior_r_reg_1),\n .I4(demanded_prior_r_reg_0),\n .I5(\\grant_r_reg[1]_0 [0]),\n .O(\\grant_r[1]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'h2222222220222020)) \n i___36_i_1\n (.I0(tail_r),\n .I1(accept_r_reg),\n .I2(rcd_active_r),\n .I3(\\grant_r_reg[1]_0 [0]),\n .I4(col_wait_r),\n .I5(\\act_this_rank_r_reg[0]_0 ),\n .O(auto_pre_r_lcl_reg));\n LUT4 #(\n .INIT(16'h0010)) \n i___43_i_1\n (.I0(demand_priority_r_2),\n .I1(demanded_prior_r_reg_1),\n .I2(demanded_prior_r_reg_0),\n .I3(\\grant_r_reg[1]_0 [0]),\n .O(\\rnk_config_strobe_r_reg[0] ));\n LUT5 #(\n .INIT(32'h000F0001)) \n ofs_rdy_r_i_1\n (.I0(\\entry_cnt_reg[2] ),\n .I1(\\entry_cnt_reg[2]_0 ),\n .I2(\\bank_cntrl[1].bank0/bank_state0/phy_mc_ctl_full_r ),\n .I3(\\bank_cntrl[1].bank0/bank_state0/phy_mc_cmd_full_r ),\n .I4(rd_wr_r_lcl_reg),\n .O(ofs_rdy_r0_0));\n LUT5 #(\n .INIT(32'h000F0001)) \n ofs_rdy_r_i_1__0\n (.I0(\\entry_cnt_reg[2] ),\n .I1(\\entry_cnt_reg[2]_0 ),\n .I2(\\bank_cntrl[1].bank0/bank_state0/phy_mc_ctl_full_r ),\n .I3(\\bank_cntrl[1].bank0/bank_state0/phy_mc_cmd_full_r ),\n .I4(rd_wr_r_lcl_reg_0),\n .O(ofs_rdy_r0));\n FDRE #(\n .INIT(1'b0)) \n ofs_rdy_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(ofs_rdy_r0_0),\n .Q(ofs_rdy_r),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n override_demand_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(override_demand_ns),\n .Q(override_demand_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n phy_mc_cmd_full_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(of_ctl_full_v),\n .Q(\\bank_cntrl[1].bank0/bank_state0/phy_mc_cmd_full_r ),\n .R(SR));\n FDRE #(\n .INIT(1'b0)) \n phy_mc_ctl_full_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(phy_mc_ctl_full),\n .Q(\\bank_cntrl[1].bank0/bank_state0/phy_mc_ctl_full_r ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n (* SOFT_HLUTNM = \"soft_lutpair1054\" *) \n LUT5 #(\n .INIT(32'hFFFF0008)) \n \\pre_4_1_1T_arb.granted_pre_r_i_1 \n (.I0(ras_timer_zero_r),\n .I1(\\rp_timer.rp_timer_r_reg[1]_0 ),\n .I2(\\grant_r_reg[0]_0 ),\n .I3(auto_pre_r_lcl_reg_0),\n .I4(auto_pre_r_lcl_reg_1),\n .O(granted_pre_ns));\n (* SOFT_HLUTNM = \"soft_lutpair1056\" *) \n LUT3 #(\n .INIT(8'hBA)) \n pre_bm_end_r_i_1__0\n (.I0(pre_passing_open_bank_ns),\n .I1(rp_timer_r[1]),\n .I2(rp_timer_r[0]),\n .O(pre_bm_end_ns));\n LUT6 #(\n .INIT(64'hAAA8AAAAAAA8AAA8)) \n pre_passing_open_bank_r_i_1__0\n (.I0(pass_open_bank_r_lcl_reg),\n .I1(\\grant_r_reg[1]_0 [0]),\n .I2(pre_wait_r_reg_1),\n .I3(pre_wait_r_reg_0),\n .I4(ras_timer_zero_r),\n .I5(\\rp_timer.rp_timer_r_reg[1]_0 ),\n .O(pre_passing_open_bank_ns));\n LUT6 #(\n .INIT(64'h0040555500400040)) \n pre_wait_r_i_1__0\n (.I0(pass_open_bank_r_lcl_reg),\n .I1(pass_open_bank_r_lcl_reg_0),\n .I2(pre_wait_r_reg_0),\n .I3(pre_wait_r_reg_1),\n .I4(rp_timer_ns),\n .I5(\\rp_timer.rp_timer_r_reg[1]_0 ),\n .O(pre_wait_ns));\n (* SOFT_HLUTNM = \"soft_lutpair1053\" *) \n LUT5 #(\n .INIT(32'hEAEAEAAA)) \n pre_wait_r_i_3\n (.I0(rstdiv0_sync_r1_reg_rep__21),\n .I1(ras_timer_zero_r),\n .I2(\\rp_timer.rp_timer_r_reg[1]_0 ),\n .I3(\\grant_r_reg[0]_0 ),\n .I4(auto_pre_r_lcl_reg_0),\n .O(rp_timer_ns));\n FDRE #(\n .INIT(1'b0)) \n pre_wait_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pre_wait_ns),\n .Q(\\rp_timer.rp_timer_r_reg[1]_0 ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h000000000E0E000E)) \n \\ras_timer_r[0]_i_3 \n (.I0(ras_timer_r[1]),\n .I1(ras_timer_r[2]),\n .I2(ras_timer_r[0]),\n .I3(\\grant_r_reg[1]_0 [0]),\n .I4(rd_wr_r_lcl_reg),\n .I5(bm_end_r1_reg_0),\n .O(\\ras_timer_r_reg[0]_0 ));\n LUT6 #(\n .INIT(64'h1110101111101010)) \n \\ras_timer_r[1]_i_3 \n (.I0(bm_end_r1),\n .I1(rstdiv0_sync_r1_reg_rep__21),\n .I2(\\ras_timer_r[2]_i_4_n_0 ),\n .I3(ras_timer_r[0]),\n .I4(ras_timer_r[1]),\n .I5(ras_timer_r[2]),\n .O(\\ras_timer_r_reg[1]_0 ));\n LUT6 #(\n .INIT(64'h1110111011101010)) \n \\ras_timer_r[2]_i_3 \n (.I0(bm_end_r1),\n .I1(rstdiv0_sync_r1_reg_rep__21),\n .I2(\\ras_timer_r[2]_i_4_n_0 ),\n .I3(ras_timer_r[2]),\n .I4(ras_timer_r[1]),\n .I5(ras_timer_r[0]),\n .O(\\ras_timer_r_reg[2]_0 ));\n LUT6 #(\n .INIT(64'h22222222222222F2)) \n \\ras_timer_r[2]_i_4 \n (.I0(\\grant_r_reg[1]_0 [0]),\n .I1(rd_wr_r_lcl_reg),\n .I2(\\rcd_timer_gt_2.rcd_timer_r[0]_i_1_n_0 ),\n .I3(ras_timer_r[2]),\n .I4(ras_timer_r[1]),\n .I5(ras_timer_r[0]),\n .O(\\ras_timer_r[2]_i_4_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\ras_timer_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(D[0]),\n .Q(ras_timer_r[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\ras_timer_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(D[1]),\n .Q(ras_timer_r[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\ras_timer_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(D[2]),\n .Q(ras_timer_r[2]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFFF1000FFFF1100)) \n ras_timer_zero_r_i_1\n (.I0(ras_timer_r[1]),\n .I1(ras_timer_r[2]),\n .I2(ras_timer_r[0]),\n .I3(rd_wr_r_lcl_reg_1),\n .I4(bm_end_r1_reg_0),\n .I5(\\rcd_timer_gt_2.rcd_timer_r[0]_i_1_n_0 ),\n .O(ras_timer_zero_ns));\n FDRE #(\n .INIT(1'b0)) \n ras_timer_zero_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(ras_timer_zero_ns),\n .Q(ras_timer_zero_r),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h8)) \n \\rcd_timer_gt_2.rcd_timer_r[0]_i_1 \n (.I0(\\act_this_rank_r_reg[0]_0 ),\n .I1(\\grant_r_reg[0] ),\n .O(\\rcd_timer_gt_2.rcd_timer_r[0]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rcd_timer_gt_2.rcd_timer_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rcd_timer_gt_2.rcd_timer_r[0]_i_1_n_0 ),\n .Q(rcd_active_r),\n .R(SR));\n FDRE #(\n .INIT(1'b0)) \n \\rd_this_rank_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_wr_r_lcl_reg),\n .Q(rd_this_rank_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n req_bank_rdy_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(req_bank_rdy_ns),\n .Q(req_bank_rdy_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0000004F00000044)) \n \\rnk_config_strobe_r[0]_i_1 \n (.I0(\\rnk_config_strobe_r_reg[0] ),\n .I1(req_bank_rdy_ns_1),\n .I2(demand_priority_r_reg_0),\n .I3(rnk_config_valid_r_lcl_reg),\n .I4(override_demand_ns),\n .I5(req_bank_rdy_ns),\n .O(rnk_config_strobe_ns));\n (* SOFT_HLUTNM = \"soft_lutpair1056\" *) \n LUT4 #(\n .INIT(16'h0004)) \n \\rp_timer.rp_timer_r[0]_i_1 \n (.I0(rp_timer_r[0]),\n .I1(rp_timer_r[1]),\n .I2(start_pre),\n .I3(rstdiv0_sync_r1_reg_rep__20),\n .O(\\rp_timer.rp_timer_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1054\" *) \n LUT4 #(\n .INIT(16'hE000)) \n \\rp_timer.rp_timer_r[0]_i_2 \n (.I0(auto_pre_r_lcl_reg_0),\n .I1(\\grant_r_reg[0]_0 ),\n .I2(\\rp_timer.rp_timer_r_reg[1]_0 ),\n .I3(ras_timer_zero_r),\n .O(start_pre));\n LUT6 #(\n .INIT(64'hF888F888F8888888)) \n \\rp_timer.rp_timer_r[1]_i_2 \n (.I0(rp_timer_r[1]),\n .I1(rp_timer_r[0]),\n .I2(ras_timer_zero_r),\n .I3(\\rp_timer.rp_timer_r_reg[1]_0 ),\n .I4(\\grant_r_reg[0]_0 ),\n .I5(auto_pre_r_lcl_reg_0),\n .O(\\rp_timer.rp_timer_r[1]_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rp_timer.rp_timer_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rp_timer.rp_timer_r[0]_i_1_n_0 ),\n .Q(rp_timer_r[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rp_timer.rp_timer_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rp_timer.rp_timer_r[1]_i_2_n_0 ),\n .Q(rp_timer_r[1]),\n .R(rstdiv0_sync_r1_reg_rep__0));\n LUT4 #(\n .INIT(16'h0010)) \n \\rtp_timer_r[0]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__20),\n .I1(pass_open_bank_r_lcl_reg_1),\n .I2(pre_wait_r_reg_1),\n .I3(pre_wait_r_reg_0),\n .O(\\rtp_timer_r[0]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rtp_timer_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rtp_timer_r[0]_i_1_n_0 ),\n .Q(pre_wait_r_reg_0),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rtp_timer_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(pass_open_bank_r_lcl_reg_2),\n .Q(pre_wait_r_reg_1),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFF7080800000000)) \n \\starve_limit_cntr_r[0]_i_1 \n (.I0(req_bank_rdy_r),\n .I1(granted_col_r_reg_1),\n .I2(\\grant_r_reg[1]_0 [0]),\n .I3(starve_limit_cntr_r[1]),\n .I4(starve_limit_cntr_r[0]),\n .I5(col_wait_r),\n .O(\\starve_limit_cntr_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFF08FF0000000000)) \n \\starve_limit_cntr_r[1]_i_1 \n (.I0(req_bank_rdy_r),\n .I1(granted_col_r_reg_1),\n .I2(\\grant_r_reg[1]_0 [0]),\n .I3(starve_limit_cntr_r[1]),\n .I4(starve_limit_cntr_r[0]),\n .I5(col_wait_r),\n .O(\\starve_limit_cntr_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\starve_limit_cntr_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\starve_limit_cntr_r[0]_i_1_n_0 ),\n .Q(starve_limit_cntr_r[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\starve_limit_cntr_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\starve_limit_cntr_r[1]_i_1_n_0 ),\n .Q(starve_limit_cntr_r[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wr_this_rank_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(start_wtp_timer0),\n .Q(wr_this_rank_r),\n .R(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_bank_state\" *) \nmodule ddr3_ifmig_7series_v4_0_bank_state__parameterized0\n (\\act_this_rank_r_reg[0]_0 ,\n act_this_rank_r,\n wr_this_rank_r,\n rd_this_rank_r,\n bm_end_r1_0,\n ras_timer_zero_r,\n pre_wait_r,\n req_bank_rdy_r,\n req_bank_rdy_ns_1,\n demanded_prior_r_reg_0,\n demanded_prior_r,\n ofs_rdy_r,\n \\rcd_timer_gt_2.rcd_timer_r_reg[0]_0 ,\n col_wait_r,\n pre_bm_end_ns,\n pre_passing_open_bank_ns,\n demand_priority_r_reg_0,\n \\cmd_pipe_plus.mc_address_reg[10] ,\n Q,\n \\ras_timer_r_reg[2]_0 ,\n \\ras_timer_r_reg[1]_0 ,\n \\ras_timer_r_reg[0]_0 ,\n auto_pre_r_lcl_reg,\n \\pre_4_1_1T_arb.granted_pre_r_reg ,\n \\rnk_config_strobe_r_reg[0] ,\n demand_priority_r_reg_1,\n act_wait_ns,\n CLK,\n start_wtp_timer0,\n rd_wr_r_lcl_reg,\n pre_bm_end_r_reg,\n demand_priority_ns,\n rstdiv0_sync_r1_reg_rep__0,\n ofs_rdy_r0,\n SR,\n pass_open_bank_ns,\n \\grant_r_reg[1] ,\n rtp_timer_ns1,\n pre_passing_open_bank_r_reg,\n \\req_row_r_lcl_reg[10] ,\n \\grant_r_reg[0] ,\n act_wait_r_lcl_reg_0,\n \\req_row_r_lcl_reg[10]_0 ,\n mc_cs_n_ns,\n rd_wr_r_lcl_reg_0,\n bm_end_r1_reg_0,\n \\ras_timer_r_reg[2]_1 ,\n rstdiv0_sync_r1_reg_rep__21,\n \\order_q_r_reg[0] ,\n rd_wr_r_lcl_reg_1,\n tail_r_3,\n accept_r_reg,\n \\grant_r_reg[1]_0 ,\n auto_pre_r_lcl_reg_0,\n \\grant_r_reg[1]_1 ,\n demanded_prior_r_1,\n demand_priority_r_2,\n q_has_rd,\n req_wr_r_lcl_reg,\n req_bank_rdy_r_reg_0,\n D,\n pass_open_bank_r_lcl_reg,\n rstdiv0_sync_r1_reg_rep__20,\n granted_col_r_reg);\n output \\act_this_rank_r_reg[0]_0 ;\n output [0:0]act_this_rank_r;\n output [0:0]wr_this_rank_r;\n output [0:0]rd_this_rank_r;\n output bm_end_r1_0;\n output ras_timer_zero_r;\n output pre_wait_r;\n output req_bank_rdy_r;\n output req_bank_rdy_ns_1;\n output demanded_prior_r_reg_0;\n output demanded_prior_r;\n output ofs_rdy_r;\n output \\rcd_timer_gt_2.rcd_timer_r_reg[0]_0 ;\n output col_wait_r;\n output pre_bm_end_ns;\n output pre_passing_open_bank_ns;\n output demand_priority_r_reg_0;\n output [0:0]\\cmd_pipe_plus.mc_address_reg[10] ;\n output [2:0]Q;\n output \\ras_timer_r_reg[2]_0 ;\n output \\ras_timer_r_reg[1]_0 ;\n output \\ras_timer_r_reg[0]_0 ;\n output auto_pre_r_lcl_reg;\n output \\pre_4_1_1T_arb.granted_pre_r_reg ;\n output \\rnk_config_strobe_r_reg[0] ;\n output demand_priority_r_reg_1;\n input act_wait_ns;\n input CLK;\n input start_wtp_timer0;\n input rd_wr_r_lcl_reg;\n input pre_bm_end_r_reg;\n input demand_priority_ns;\n input rstdiv0_sync_r1_reg_rep__0;\n input ofs_rdy_r0;\n input [0:0]SR;\n input pass_open_bank_ns;\n input [1:0]\\grant_r_reg[1] ;\n input rtp_timer_ns1;\n input pre_passing_open_bank_r_reg;\n input [0:0]\\req_row_r_lcl_reg[10] ;\n input \\grant_r_reg[0] ;\n input act_wait_r_lcl_reg_0;\n input [0:0]\\req_row_r_lcl_reg[10]_0 ;\n input [0:0]mc_cs_n_ns;\n input rd_wr_r_lcl_reg_0;\n input bm_end_r1_reg_0;\n input \\ras_timer_r_reg[2]_1 ;\n input rstdiv0_sync_r1_reg_rep__21;\n input \\order_q_r_reg[0] ;\n input rd_wr_r_lcl_reg_1;\n input tail_r_3;\n input accept_r_reg;\n input [0:0]\\grant_r_reg[1]_0 ;\n input auto_pre_r_lcl_reg_0;\n input [0:0]\\grant_r_reg[1]_1 ;\n input demanded_prior_r_1;\n input demand_priority_r_2;\n input q_has_rd;\n input req_wr_r_lcl_reg;\n input req_bank_rdy_r_reg_0;\n input [2:0]D;\n input pass_open_bank_r_lcl_reg;\n input rstdiv0_sync_r1_reg_rep__20;\n input granted_col_r_reg;\n\n wire CLK;\n wire [2:0]D;\n wire [2:0]Q;\n wire [0:0]SR;\n wire accept_r_reg;\n wire [0:0]act_this_rank_r;\n wire \\act_this_rank_r_reg[0]_0 ;\n wire act_wait_ns;\n wire act_wait_r_lcl_reg_0;\n wire auto_pre_r_lcl_reg;\n wire auto_pre_r_lcl_reg_0;\n wire bm_end_r1_0;\n wire bm_end_r1_reg_0;\n wire [0:0]\\cmd_pipe_plus.mc_address_reg[10] ;\n wire col_wait_r;\n wire col_wait_r_i_1__0_n_0;\n wire demand_priority_ns;\n wire demand_priority_r_2;\n wire demand_priority_r_reg_0;\n wire demand_priority_r_reg_1;\n wire demanded_prior_ns;\n wire demanded_prior_r;\n wire demanded_prior_r_1;\n wire demanded_prior_r_reg_0;\n wire \\grant_r_reg[0] ;\n wire [1:0]\\grant_r_reg[1] ;\n wire [0:0]\\grant_r_reg[1]_0 ;\n wire [0:0]\\grant_r_reg[1]_1 ;\n wire granted_col_r_reg;\n wire [0:0]mc_cs_n_ns;\n wire ofs_rdy_r;\n wire ofs_rdy_r0;\n wire \\order_q_r_reg[0] ;\n wire pass_open_bank_ns;\n wire pass_open_bank_r_lcl_reg;\n wire \\pre_4_1_1T_arb.granted_pre_r_reg ;\n wire pre_bm_end_ns;\n wire pre_bm_end_r_reg;\n wire pre_passing_open_bank_ns;\n wire pre_passing_open_bank_r_reg;\n wire pre_wait_ns;\n wire pre_wait_r;\n wire q_has_rd;\n wire \\ras_timer_r_reg[0]_0 ;\n wire \\ras_timer_r_reg[1]_0 ;\n wire \\ras_timer_r_reg[2]_0 ;\n wire \\ras_timer_r_reg[2]_1 ;\n wire ras_timer_zero_r;\n wire ras_timer_zero_r_i_1__0_n_0;\n wire rcd_active_r;\n wire \\rcd_timer_gt_2.rcd_timer_r_reg[0]_0 ;\n wire [0:0]rd_this_rank_r;\n wire rd_wr_r_lcl_reg;\n wire rd_wr_r_lcl_reg_0;\n wire rd_wr_r_lcl_reg_1;\n wire req_bank_rdy_ns_1;\n wire req_bank_rdy_r;\n wire req_bank_rdy_r_reg_0;\n wire [0:0]\\req_row_r_lcl_reg[10] ;\n wire [0:0]\\req_row_r_lcl_reg[10]_0 ;\n wire req_wr_r_lcl_reg;\n wire \\rnk_config_strobe_r_reg[0] ;\n wire \\rp_timer.rp_timer_r[0]_i_1_n_0 ;\n wire \\rp_timer.rp_timer_r[1]_i_1_n_0 ;\n wire \\rp_timer.rp_timer_r_reg_n_0_[0] ;\n wire \\rp_timer.rp_timer_r_reg_n_0_[1] ;\n wire [0:0]rp_timer_ns;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire rtp_timer_ns1;\n wire [1:0]rtp_timer_r;\n wire \\rtp_timer_r[0]_i_1_n_0 ;\n wire \\rtp_timer_r[1]_i_1_n_0 ;\n wire start_pre;\n wire start_wtp_timer0;\n wire [1:0]starve_limit_cntr_r;\n wire \\starve_limit_cntr_r[0]_i_1_n_0 ;\n wire \\starve_limit_cntr_r[1]_i_1_n_0 ;\n wire tail_r_3;\n wire [0:0]wr_this_rank_r;\n\n FDRE #(\n .INIT(1'b0)) \n \\act_this_rank_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\act_this_rank_r_reg[0]_0 ),\n .Q(act_this_rank_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n act_wait_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(act_wait_ns),\n .Q(\\act_this_rank_r_reg[0]_0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n bm_end_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pre_bm_end_r_reg),\n .Q(bm_end_r1_0),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFFFFFFFF8888888)) \n \\cmd_pipe_plus.mc_address[10]_i_1 \n (.I0(\\rcd_timer_gt_2.rcd_timer_r_reg[0]_0 ),\n .I1(\\req_row_r_lcl_reg[10] ),\n .I2(\\grant_r_reg[0] ),\n .I3(act_wait_r_lcl_reg_0),\n .I4(\\req_row_r_lcl_reg[10]_0 ),\n .I5(mc_cs_n_ns),\n .O(\\cmd_pipe_plus.mc_address_reg[10] ));\n (* SOFT_HLUTNM = \"soft_lutpair1062\" *) \n LUT4 #(\n .INIT(16'hFFBA)) \n col_wait_r_i_1__0\n (.I0(rcd_active_r),\n .I1(\\grant_r_reg[1] [1]),\n .I2(col_wait_r),\n .I3(pre_passing_open_bank_r_reg),\n .O(col_wait_r_i_1__0_n_0));\n FDRE #(\n .INIT(1'b0)) \n col_wait_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(col_wait_r_i_1__0_n_0),\n .Q(col_wait_r),\n .R(SR));\n LUT6 #(\n .INIT(64'hEAAAEAEAAAAAAAAA)) \n demand_priority_r_i_2__0\n (.I0(demanded_prior_r_reg_0),\n .I1(starve_limit_cntr_r[0]),\n .I2(starve_limit_cntr_r[1]),\n .I3(q_has_rd),\n .I4(req_wr_r_lcl_reg),\n .I5(req_bank_rdy_r_reg_0),\n .O(demand_priority_r_reg_1));\n (* SOFT_HLUTNM = \"soft_lutpair1062\" *) \n LUT4 #(\n .INIT(16'h0051)) \n demand_priority_r_i_4__0\n (.I0(pre_passing_open_bank_r_reg),\n .I1(col_wait_r),\n .I2(\\grant_r_reg[1] [1]),\n .I3(rcd_active_r),\n .O(demand_priority_r_reg_0));\n FDRE #(\n .INIT(1'b0)) \n demand_priority_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(demand_priority_ns),\n .Q(demanded_prior_r_reg_0),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00000D00)) \n demanded_prior_r_i_1__0\n (.I0(demanded_prior_r_reg_0),\n .I1(demanded_prior_r),\n .I2(demanded_prior_r_1),\n .I3(demand_priority_r_2),\n .I4(\\grant_r_reg[1] [0]),\n .O(demanded_prior_ns));\n FDRE #(\n .INIT(1'b0)) \n demanded_prior_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(demanded_prior_ns),\n .Q(demanded_prior_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1059\" *) \n LUT4 #(\n .INIT(16'h1000)) \n \\grant_r[1]_i_2__1 \n (.I0(auto_pre_r_lcl_reg_0),\n .I1(\\grant_r_reg[1]_1 ),\n .I2(pre_wait_r),\n .I3(ras_timer_zero_r),\n .O(\\pre_4_1_1T_arb.granted_pre_r_reg ));\n LUT6 #(\n .INIT(64'h2222222220222020)) \n i___13_i_1\n (.I0(tail_r_3),\n .I1(accept_r_reg),\n .I2(rcd_active_r),\n .I3(\\grant_r_reg[1] [1]),\n .I4(col_wait_r),\n .I5(\\act_this_rank_r_reg[0]_0 ),\n .O(auto_pre_r_lcl_reg));\n LUT4 #(\n .INIT(16'h0010)) \n i___43_i_2\n (.I0(demand_priority_r_2),\n .I1(demanded_prior_r),\n .I2(demanded_prior_r_reg_0),\n .I3(\\grant_r_reg[1] [1]),\n .O(\\rnk_config_strobe_r_reg[0] ));\n FDRE #(\n .INIT(1'b0)) \n ofs_rdy_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(ofs_rdy_r0),\n .Q(ofs_rdy_r),\n .R(rstdiv0_sync_r1_reg_rep__0));\n (* SOFT_HLUTNM = \"soft_lutpair1061\" *) \n LUT3 #(\n .INIT(8'hBA)) \n pre_bm_end_r_i_1\n (.I0(pre_passing_open_bank_ns),\n .I1(\\rp_timer.rp_timer_r_reg_n_0_[1] ),\n .I2(\\rp_timer.rp_timer_r_reg_n_0_[0] ),\n .O(pre_bm_end_ns));\n LUT6 #(\n .INIT(64'hAAA8AAAAAAA8AAA8)) \n pre_passing_open_bank_r_i_1\n (.I0(pass_open_bank_ns),\n .I1(\\grant_r_reg[1] [1]),\n .I2(rtp_timer_r[1]),\n .I3(rtp_timer_r[0]),\n .I4(ras_timer_zero_r),\n .I5(pre_wait_r),\n .O(pre_passing_open_bank_ns));\n LUT6 #(\n .INIT(64'h0404040404550404)) \n pre_wait_r_i_1\n (.I0(pass_open_bank_ns),\n .I1(pre_wait_r),\n .I2(rp_timer_ns),\n .I3(rtp_timer_ns1),\n .I4(rtp_timer_r[0]),\n .I5(rtp_timer_r[1]),\n .O(pre_wait_ns));\n (* SOFT_HLUTNM = \"soft_lutpair1059\" *) \n LUT5 #(\n .INIT(32'hEAEAEAAA)) \n pre_wait_r_i_2__0\n (.I0(rstdiv0_sync_r1_reg_rep__21),\n .I1(ras_timer_zero_r),\n .I2(pre_wait_r),\n .I3(\\grant_r_reg[1]_1 ),\n .I4(auto_pre_r_lcl_reg_0),\n .O(rp_timer_ns));\n FDRE #(\n .INIT(1'b0)) \n pre_wait_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pre_wait_ns),\n .Q(pre_wait_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h000000000000BBB0)) \n \\ras_timer_r[0]_i_2 \n (.I0(rd_wr_r_lcl_reg),\n .I1(\\grant_r_reg[1] [1]),\n .I2(Q[2]),\n .I3(Q[1]),\n .I4(bm_end_r1_reg_0),\n .I5(Q[0]),\n .O(\\ras_timer_r_reg[0]_0 ));\n LUT6 #(\n .INIT(64'h1110101111101010)) \n \\ras_timer_r[1]_i_2 \n (.I0(bm_end_r1_0),\n .I1(rstdiv0_sync_r1_reg_rep__21),\n .I2(\\ras_timer_r_reg[2]_1 ),\n .I3(Q[0]),\n .I4(Q[1]),\n .I5(Q[2]),\n .O(\\ras_timer_r_reg[1]_0 ));\n LUT6 #(\n .INIT(64'h000000000000EEEA)) \n \\ras_timer_r[2]_i_2 \n (.I0(\\ras_timer_r_reg[2]_1 ),\n .I1(Q[2]),\n .I2(Q[1]),\n .I3(Q[0]),\n .I4(bm_end_r1_0),\n .I5(rstdiv0_sync_r1_reg_rep__21),\n .O(\\ras_timer_r_reg[2]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\ras_timer_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(D[0]),\n .Q(Q[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\ras_timer_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(D[1]),\n .Q(Q[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\ras_timer_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(D[2]),\n .Q(Q[2]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFF02FF00FF02FF02)) \n ras_timer_zero_r_i_1__0\n (.I0(rd_wr_r_lcl_reg_0),\n .I1(Q[2]),\n .I2(Q[1]),\n .I3(bm_end_r1_reg_0),\n .I4(Q[0]),\n .I5(\\rcd_timer_gt_2.rcd_timer_r_reg[0]_0 ),\n .O(ras_timer_zero_r_i_1__0_n_0));\n FDRE #(\n .INIT(1'b0)) \n ras_timer_zero_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(ras_timer_zero_r_i_1__0_n_0),\n .Q(ras_timer_zero_r),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h8)) \n \\rcd_timer_gt_2.rcd_timer_r[0]_i_1__0 \n (.I0(\\act_this_rank_r_reg[0]_0 ),\n .I1(\\grant_r_reg[1]_0 ),\n .O(\\rcd_timer_gt_2.rcd_timer_r_reg[0]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rcd_timer_gt_2.rcd_timer_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rcd_timer_gt_2.rcd_timer_r_reg[0]_0 ),\n .Q(rcd_active_r),\n .R(SR));\n FDRE #(\n .INIT(1'b0)) \n \\rd_this_rank_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_wr_r_lcl_reg),\n .Q(rd_this_rank_r),\n .R(1'b0));\n LUT4 #(\n .INIT(16'h8AAA)) \n req_bank_rdy_r_i_1__0\n (.I0(col_wait_r),\n .I1(rd_wr_r_lcl_reg),\n .I2(\\order_q_r_reg[0] ),\n .I3(rd_wr_r_lcl_reg_1),\n .O(req_bank_rdy_ns_1));\n FDRE #(\n .INIT(1'b0)) \n req_bank_rdy_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(req_bank_rdy_ns_1),\n .Q(req_bank_rdy_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1061\" *) \n LUT4 #(\n .INIT(16'h0004)) \n \\rp_timer.rp_timer_r[0]_i_1 \n (.I0(\\rp_timer.rp_timer_r_reg_n_0_[0] ),\n .I1(\\rp_timer.rp_timer_r_reg_n_0_[1] ),\n .I2(start_pre),\n .I3(rstdiv0_sync_r1_reg_rep__20),\n .O(\\rp_timer.rp_timer_r[0]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hE000)) \n \\rp_timer.rp_timer_r[0]_i_2__0 \n (.I0(auto_pre_r_lcl_reg_0),\n .I1(\\grant_r_reg[1]_1 ),\n .I2(pre_wait_r),\n .I3(ras_timer_zero_r),\n .O(start_pre));\n LUT6 #(\n .INIT(64'hF888F888F8888888)) \n \\rp_timer.rp_timer_r[1]_i_1 \n (.I0(\\rp_timer.rp_timer_r_reg_n_0_[1] ),\n .I1(\\rp_timer.rp_timer_r_reg_n_0_[0] ),\n .I2(ras_timer_zero_r),\n .I3(pre_wait_r),\n .I4(\\grant_r_reg[1]_1 ),\n .I5(auto_pre_r_lcl_reg_0),\n .O(\\rp_timer.rp_timer_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rp_timer.rp_timer_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rp_timer.rp_timer_r[0]_i_1_n_0 ),\n .Q(\\rp_timer.rp_timer_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rp_timer.rp_timer_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rp_timer.rp_timer_r[1]_i_1_n_0 ),\n .Q(\\rp_timer.rp_timer_r_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n (* SOFT_HLUTNM = \"soft_lutpair1060\" *) \n LUT4 #(\n .INIT(16'h0002)) \n \\rtp_timer_r[0]_i_1 \n (.I0(rtp_timer_r[1]),\n .I1(rtp_timer_r[0]),\n .I2(rstdiv0_sync_r1_reg_rep__20),\n .I3(pass_open_bank_r_lcl_reg),\n .O(\\rtp_timer_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1060\" *) \n LUT5 #(\n .INIT(32'h000000C2)) \n \\rtp_timer_r[1]_i_1 \n (.I0(\\grant_r_reg[1] [1]),\n .I1(rtp_timer_r[1]),\n .I2(rtp_timer_r[0]),\n .I3(pass_open_bank_r_lcl_reg),\n .I4(rstdiv0_sync_r1_reg_rep__20),\n .O(\\rtp_timer_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rtp_timer_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rtp_timer_r[0]_i_1_n_0 ),\n .Q(rtp_timer_r[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rtp_timer_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rtp_timer_r[1]_i_1_n_0 ),\n .Q(rtp_timer_r[1]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFF7080800000000)) \n \\starve_limit_cntr_r[0]_i_1 \n (.I0(req_bank_rdy_r),\n .I1(granted_col_r_reg),\n .I2(\\grant_r_reg[1] [1]),\n .I3(starve_limit_cntr_r[1]),\n .I4(starve_limit_cntr_r[0]),\n .I5(col_wait_r),\n .O(\\starve_limit_cntr_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFF08FF0000000000)) \n \\starve_limit_cntr_r[1]_i_1 \n (.I0(req_bank_rdy_r),\n .I1(granted_col_r_reg),\n .I2(\\grant_r_reg[1] [1]),\n .I3(starve_limit_cntr_r[1]),\n .I4(starve_limit_cntr_r[0]),\n .I5(col_wait_r),\n .O(\\starve_limit_cntr_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\starve_limit_cntr_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\starve_limit_cntr_r[0]_i_1_n_0 ),\n .Q(starve_limit_cntr_r[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\starve_limit_cntr_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\starve_limit_cntr_r[1]_i_1_n_0 ),\n .Q(starve_limit_cntr_r[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wr_this_rank_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(start_wtp_timer0),\n .Q(wr_this_rank_r),\n .R(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_clk_ibuf\" *) \nmodule ddr3_ifmig_7series_v4_0_clk_ibuf\n (mmcm_clk,\n sys_clk_i);\n output mmcm_clk;\n input sys_clk_i;\n\n (* RTL_KEEP = \"true\" *) (* syn_keep = \"true\" *) wire sys_clk_ibufg;\n\n assign mmcm_clk = sys_clk_ibufg;\n assign sys_clk_ibufg = sys_clk_i;\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_col_mach\" *) \nmodule ddr3_ifmig_7series_v4_0_col_mach\n (col_rd_wr_r1,\n col_rd_wr_r2,\n sent_col_r2,\n D,\n bypass__0,\n Q,\n mc_read_idle_r_reg,\n \\read_fifo.tail_r_reg[2]_0 ,\n mc_ref_zq_wip_ns,\n \\read_fifo.tail_r_reg[1]_0 ,\n wr_data_en_ns,\n \\read_fifo.fifo_out_data_r_reg[7]_0 ,\n app_rd_data_end_ns,\n CLK,\n col_data_buf_addr,\n ADDRA,\n DIC,\n col_rd_wr,\n mc_cmd,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,\n \\rd_buf_indx.rd_buf_indx_r_reg[4] ,\n maint_ref_zq_wip,\n rstdiv0_sync_r1_reg_rep__22,\n \\not_strict_mode.status_ram.rd_buf_we_r1_reg ,\n SR,\n \\read_fifo.tail_r_reg[0]_0 ,\n rstdiv0_sync_r1_reg_rep__0,\n E);\n output col_rd_wr_r1;\n output col_rd_wr_r2;\n output sent_col_r2;\n output [3:0]D;\n output bypass__0;\n output [7:0]Q;\n output mc_read_idle_r_reg;\n output [1:0]\\read_fifo.tail_r_reg[2]_0 ;\n output mc_ref_zq_wip_ns;\n output \\read_fifo.tail_r_reg[1]_0 ;\n output wr_data_en_ns;\n output \\read_fifo.fifo_out_data_r_reg[7]_0 ;\n output app_rd_data_end_ns;\n input CLK;\n input [4:0]col_data_buf_addr;\n input [2:0]ADDRA;\n input [0:0]DIC;\n input col_rd_wr;\n input [0:0]mc_cmd;\n input \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n input [4:0]\\rd_buf_indx.rd_buf_indx_r_reg[4] ;\n input maint_ref_zq_wip;\n input rstdiv0_sync_r1_reg_rep__22;\n input [0:0]\\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n input [0:0]SR;\n input \\read_fifo.tail_r_reg[0]_0 ;\n input rstdiv0_sync_r1_reg_rep__0;\n input [0:0]E;\n\n wire [2:0]ADDRA;\n wire CLK;\n wire [3:0]D;\n wire [0:0]DIC;\n wire [0:0]E;\n wire [7:0]Q;\n wire [0:0]SR;\n wire app_rd_data_end_ns;\n wire bypass__0;\n wire [4:0]col_data_buf_addr;\n wire col_rd_wr;\n wire col_rd_wr_r1;\n wire col_rd_wr_r2;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n wire [7:0]fifo_out_data_ns;\n wire [4:0]head_r;\n wire maint_ref_zq_wip;\n wire [0:0]mc_cmd;\n wire mc_read_idle_r_reg;\n wire mc_ref_zq_wip_ns;\n wire mc_ref_zq_wip_r_i_2_n_0;\n wire [0:0]\\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n wire [4:0]p_0_in;\n wire \\rd_buf_indx.rd_buf_indx_r[0]_i_3_n_0 ;\n wire \\rd_buf_indx.rd_buf_indx_r[0]_i_4_n_0 ;\n wire [4:0]\\rd_buf_indx.rd_buf_indx_r_reg[4] ;\n wire \\read_fifo.fifo_out_data_r_reg[7]_0 ;\n wire \\read_fifo.tail_r[1]_i_1_n_0 ;\n wire \\read_fifo.tail_r[2]_i_1_n_0 ;\n wire \\read_fifo.tail_r[3]_i_1_n_0 ;\n wire \\read_fifo.tail_r[4]_i_1_n_0 ;\n wire \\read_fifo.tail_r_reg[0]_0 ;\n wire \\read_fifo.tail_r_reg[1]_0 ;\n wire [1:0]\\read_fifo.tail_r_reg[2]_0 ;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__22;\n wire sent_col_r2;\n wire [3:0]tail_ns;\n wire [4:3]tail_r;\n wire wr_data_en_ns;\n wire [1:0]\\NLW_read_fifo.fifo_ram[0].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_read_fifo.fifo_ram[1].RAM32M0_DOA_UNCONNECTED ;\n wire [1:0]\\NLW_read_fifo.fifo_ram[1].RAM32M0_DOB_UNCONNECTED ;\n wire [1:0]\\NLW_read_fifo.fifo_ram[1].RAM32M0_DOD_UNCONNECTED ;\n\n LUT2 #(\n .INIT(4'h2)) \n \\cmd_pipe_plus.wr_data_en_i_1 \n (.I0(mc_cmd),\n .I1(col_rd_wr_r1),\n .O(wr_data_en_ns));\n FDRE #(\n .INIT(1'b0)) \n \\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(col_data_buf_addr[0]),\n .Q(D[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(col_data_buf_addr[1]),\n .Q(D[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(col_data_buf_addr[2]),\n .Q(D[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(col_data_buf_addr[3]),\n .Q(D[3]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h9555555555555555)) \n i___56_i_2\n (.I0(tail_r[4]),\n .I1(\\read_fifo.tail_r_reg[2]_0 [0]),\n .I2(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I3(\\read_fifo.tail_r_reg[1]_0 ),\n .I4(\\read_fifo.tail_r_reg[2]_0 [1]),\n .I5(tail_r[3]),\n .O(\\read_fifo.fifo_out_data_r_reg[7]_0 ));\n LUT5 #(\n .INIT(32'h09000009)) \n mc_read_idle_r_i_1\n (.I0(tail_r[4]),\n .I1(head_r[4]),\n .I2(mc_ref_zq_wip_r_i_2_n_0),\n .I3(head_r[3]),\n .I4(tail_r[3]),\n .O(mc_read_idle_r_reg));\n LUT6 #(\n .INIT(64'h0082000000000082)) \n mc_ref_zq_wip_r_i_1\n (.I0(maint_ref_zq_wip),\n .I1(tail_r[4]),\n .I2(head_r[4]),\n .I3(mc_ref_zq_wip_r_i_2_n_0),\n .I4(head_r[3]),\n .I5(tail_r[3]),\n .O(mc_ref_zq_wip_ns));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n mc_ref_zq_wip_r_i_2\n (.I0(head_r[1]),\n .I1(\\read_fifo.tail_r_reg[2]_0 [0]),\n .I2(head_r[2]),\n .I3(\\read_fifo.tail_r_reg[2]_0 [1]),\n .I4(\\read_fifo.tail_r_reg[1]_0 ),\n .I5(head_r[0]),\n .O(mc_ref_zq_wip_r_i_2_n_0));\n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data_end_i_1 \n (.I0(Q[7]),\n .I1(bypass__0),\n .I2(\\not_strict_mode.status_ram.rd_buf_we_r1_reg ),\n .O(app_rd_data_end_ns));\n FDRE #(\n .INIT(1'b0)) \n \\offset_pipe_0.col_rd_wr_r1_reg \n (.C(CLK),\n .CE(1'b1),\n .D(col_rd_wr),\n .Q(col_rd_wr_r1),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\offset_pipe_1.col_rd_wr_r2_reg \n (.C(CLK),\n .CE(1'b1),\n .D(col_rd_wr_r1),\n .Q(col_rd_wr_r2),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h2000000000002000)) \n \\rd_buf_indx.rd_buf_indx_r[0]_i_2 \n (.I0(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I1(Q[6]),\n .I2(\\rd_buf_indx.rd_buf_indx_r[0]_i_3_n_0 ),\n .I3(\\rd_buf_indx.rd_buf_indx_r[0]_i_4_n_0 ),\n .I4(\\rd_buf_indx.rd_buf_indx_r_reg[4] [1]),\n .I5(Q[2]),\n .O(bypass__0));\n LUT4 #(\n .INIT(16'h9009)) \n \\rd_buf_indx.rd_buf_indx_r[0]_i_3 \n (.I0(Q[5]),\n .I1(\\rd_buf_indx.rd_buf_indx_r_reg[4] [4]),\n .I2(Q[1]),\n .I3(\\rd_buf_indx.rd_buf_indx_r_reg[4] [0]),\n .O(\\rd_buf_indx.rd_buf_indx_r[0]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'h9009)) \n \\rd_buf_indx.rd_buf_indx_r[0]_i_4 \n (.I0(Q[3]),\n .I1(\\rd_buf_indx.rd_buf_indx_r_reg[4] [2]),\n .I2(Q[4]),\n .I3(\\rd_buf_indx.rd_buf_indx_r_reg[4] [3]),\n .O(\\rd_buf_indx.rd_buf_indx_r[0]_i_4_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\read_fifo.fifo_out_data_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(fifo_out_data_ns[0]),\n .Q(Q[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\read_fifo.fifo_out_data_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(fifo_out_data_ns[1]),\n .Q(Q[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\read_fifo.fifo_out_data_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(fifo_out_data_ns[2]),\n .Q(Q[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\read_fifo.fifo_out_data_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(fifo_out_data_ns[3]),\n .Q(Q[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\read_fifo.fifo_out_data_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(fifo_out_data_ns[4]),\n .Q(Q[4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\read_fifo.fifo_out_data_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(fifo_out_data_ns[5]),\n .Q(Q[5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\read_fifo.fifo_out_data_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(fifo_out_data_ns[6]),\n .Q(Q[6]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\read_fifo.fifo_out_data_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(fifo_out_data_ns[7]),\n .Q(Q[7]),\n .R(1'b0));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\read_fifo.fifo_ram[0].RAM32M0 \n (.ADDRA({ADDRA[2],tail_ns[3],ADDRA[1:0],tail_ns[0]}),\n .ADDRB({ADDRA[2],tail_ns[3],ADDRA[1:0],tail_ns[0]}),\n .ADDRC({ADDRA[2],tail_ns[3],ADDRA[1:0],tail_ns[0]}),\n .ADDRD(head_r),\n .DIA(col_data_buf_addr[4:3]),\n .DIB(col_data_buf_addr[2:1]),\n .DIC({col_data_buf_addr[0],1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(fifo_out_data_ns[5:4]),\n .DOB(fifo_out_data_ns[3:2]),\n .DOC(fifo_out_data_ns[1:0]),\n .DOD(\\NLW_read_fifo.fifo_ram[0].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(1'b1));\n LUT6 #(\n .INIT(64'h000000007FFF8000)) \n \\read_fifo.fifo_ram[0].RAM32M0_i_6 \n (.I0(\\read_fifo.tail_r_reg[2]_0 [0]),\n .I1(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I2(\\read_fifo.tail_r_reg[1]_0 ),\n .I3(\\read_fifo.tail_r_reg[2]_0 [1]),\n .I4(tail_r[3]),\n .I5(rstdiv0_sync_r1_reg_rep__22),\n .O(tail_ns[3]));\n LUT3 #(\n .INIT(8'h06)) \n \\read_fifo.fifo_ram[0].RAM32M0_i_7 \n (.I0(\\read_fifo.tail_r_reg[1]_0 ),\n .I1(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I2(rstdiv0_sync_r1_reg_rep__22),\n .O(tail_ns[0]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\read_fifo.fifo_ram[1].RAM32M0 \n (.ADDRA({ADDRA[2],tail_ns[3],ADDRA[1:0],tail_ns[0]}),\n .ADDRB({ADDRA[2],tail_ns[3],ADDRA[1:0],tail_ns[0]}),\n .ADDRC({ADDRA[2],tail_ns[3],ADDRA[1:0],tail_ns[0]}),\n .ADDRD(head_r),\n .DIA({1'b0,1'b0}),\n .DIB({1'b0,1'b0}),\n .DIC({1'b1,DIC}),\n .DID({1'b0,1'b0}),\n .DOA(\\NLW_read_fifo.fifo_ram[1].RAM32M0_DOA_UNCONNECTED [1:0]),\n .DOB(\\NLW_read_fifo.fifo_ram[1].RAM32M0_DOB_UNCONNECTED [1:0]),\n .DOC(fifo_out_data_ns[7:6]),\n .DOD(\\NLW_read_fifo.fifo_ram[1].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(1'b1));\n LUT1 #(\n .INIT(2'h1)) \n \\read_fifo.head_r[0]_i_1 \n (.I0(head_r[0]),\n .O(p_0_in[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1068\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\read_fifo.head_r[1]_i_1 \n (.I0(head_r[0]),\n .I1(head_r[1]),\n .O(p_0_in[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1068\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\read_fifo.head_r[2]_i_1 \n (.I0(head_r[2]),\n .I1(head_r[1]),\n .I2(head_r[0]),\n .O(p_0_in[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1066\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\read_fifo.head_r[3]_i_1 \n (.I0(head_r[3]),\n .I1(head_r[0]),\n .I2(head_r[1]),\n .I3(head_r[2]),\n .O(p_0_in[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1066\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\read_fifo.head_r[4]_i_1 \n (.I0(head_r[4]),\n .I1(head_r[2]),\n .I2(head_r[1]),\n .I3(head_r[0]),\n .I4(head_r[3]),\n .O(p_0_in[4]));\n FDRE #(\n .INIT(1'b0)) \n \\read_fifo.head_r_reg[0] \n (.C(CLK),\n .CE(E),\n .D(p_0_in[0]),\n .Q(head_r[0]),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\read_fifo.head_r_reg[1] \n (.C(CLK),\n .CE(E),\n .D(p_0_in[1]),\n .Q(head_r[1]),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\read_fifo.head_r_reg[2] \n (.C(CLK),\n .CE(E),\n .D(p_0_in[2]),\n .Q(head_r[2]),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\read_fifo.head_r_reg[3] \n (.C(CLK),\n .CE(E),\n .D(p_0_in[3]),\n .Q(head_r[3]),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\read_fifo.head_r_reg[4] \n (.C(CLK),\n .CE(E),\n .D(p_0_in[4]),\n .Q(head_r[4]),\n .R(rstdiv0_sync_r1_reg_rep__0));\n LUT3 #(\n .INIT(8'h78)) \n \\read_fifo.tail_r[1]_i_1 \n (.I0(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I1(\\read_fifo.tail_r_reg[1]_0 ),\n .I2(\\read_fifo.tail_r_reg[2]_0 [0]),\n .O(\\read_fifo.tail_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1067\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\read_fifo.tail_r[2]_i_1 \n (.I0(\\read_fifo.tail_r_reg[1]_0 ),\n .I1(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I2(\\read_fifo.tail_r_reg[2]_0 [0]),\n .I3(\\read_fifo.tail_r_reg[2]_0 [1]),\n .O(\\read_fifo.tail_r[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1067\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\read_fifo.tail_r[3]_i_1 \n (.I0(tail_r[3]),\n .I1(\\read_fifo.tail_r_reg[2]_0 [1]),\n .I2(\\read_fifo.tail_r_reg[1]_0 ),\n .I3(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I4(\\read_fifo.tail_r_reg[2]_0 [0]),\n .O(\\read_fifo.tail_r[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h7FFFFFFF80000000)) \n \\read_fifo.tail_r[4]_i_1 \n (.I0(tail_r[3]),\n .I1(\\read_fifo.tail_r_reg[2]_0 [1]),\n .I2(\\read_fifo.tail_r_reg[1]_0 ),\n .I3(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I4(\\read_fifo.tail_r_reg[2]_0 [0]),\n .I5(tail_r[4]),\n .O(\\read_fifo.tail_r[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\read_fifo.tail_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\read_fifo.tail_r_reg[0]_0 ),\n .Q(\\read_fifo.tail_r_reg[1]_0 ),\n .R(SR));\n FDRE #(\n .INIT(1'b0)) \n \\read_fifo.tail_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\read_fifo.tail_r[1]_i_1_n_0 ),\n .Q(\\read_fifo.tail_r_reg[2]_0 [0]),\n .R(SR));\n FDRE #(\n .INIT(1'b0)) \n \\read_fifo.tail_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\read_fifo.tail_r[2]_i_1_n_0 ),\n .Q(\\read_fifo.tail_r_reg[2]_0 [1]),\n .R(SR));\n FDRE #(\n .INIT(1'b0)) \n \\read_fifo.tail_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\read_fifo.tail_r[3]_i_1_n_0 ),\n .Q(tail_r[3]),\n .R(SR));\n FDRE #(\n .INIT(1'b0)) \n \\read_fifo.tail_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\read_fifo.tail_r[4]_i_1_n_0 ),\n .Q(tail_r[4]),\n .R(SR));\n FDRE #(\n .INIT(1'b0)) \n sent_col_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mc_cmd),\n .Q(sent_col_r2),\n .R(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_byte_group_io\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_byte_group_io\n (mem_dqs_out,\n mem_dqs_ts,\n D0,\n D1,\n D2,\n D3,\n D4,\n D5,\n D6,\n D7,\n mem_dq_out,\n mem_dq_ts,\n idelay_ld_rst,\n rst_r4,\n oserdes_clk,\n oserdes_clkdiv,\n po_oserdes_rst,\n DTSBUS,\n oserdes_clk_delayed,\n DQSBUS,\n CTSBUS,\n CLK,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n mem_dq_in,\n idelay_inc,\n LD0,\n A_rst_primitives,\n A_rst_primitives_reg,\n CLKB0,\n iserdes_clkdiv,\n of_dqbus,\n E,\n \\fine_delay_mod_reg[23] );\n output [0:0]mem_dqs_out;\n output [0:0]mem_dqs_ts;\n output [3:0]D0;\n output [3:0]D1;\n output [3:0]D2;\n output [3:0]D3;\n output [3:0]D4;\n output [3:0]D5;\n output [3:0]D6;\n output [3:0]D7;\n output [8:0]mem_dq_out;\n output [8:0]mem_dq_ts;\n output idelay_ld_rst;\n output rst_r4;\n input oserdes_clk;\n input oserdes_clkdiv;\n input po_oserdes_rst;\n input [1:0]DTSBUS;\n input oserdes_clk_delayed;\n input [1:0]DQSBUS;\n input [0:0]CTSBUS;\n input CLK;\n input \\gen_byte_sel_div1.calib_in_common_reg ;\n input [7:0]mem_dq_in;\n input idelay_inc;\n input LD0;\n input A_rst_primitives;\n input A_rst_primitives_reg;\n input CLKB0;\n input iserdes_clkdiv;\n input [35:0]of_dqbus;\n input [0:0]E;\n input [7:0]\\fine_delay_mod_reg[23] ;\n\n wire A_rst_primitives;\n wire A_rst_primitives_reg;\n wire CLK;\n wire CLKB0;\n wire [0:0]CTSBUS;\n wire [3:0]D0;\n wire [3:0]D1;\n wire [3:0]D2;\n wire [3:0]D3;\n wire [3:0]D4;\n wire [3:0]D5;\n wire [3:0]D6;\n wire [3:0]D7;\n wire [1:0]DQSBUS;\n wire [1:0]DTSBUS;\n wire [0:0]E;\n wire LD0;\n wire data_in_dly_0;\n wire data_in_dly_1;\n wire data_in_dly_2;\n wire data_in_dly_3;\n wire data_in_dly_4;\n wire data_in_dly_5;\n wire data_in_dly_6;\n wire data_in_dly_7;\n wire [7:0]\\fine_delay_mod_reg[23] ;\n wire [23:2]fine_delay_r;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire idelay_inc;\n wire idelay_ld_rst;\n wire idelay_ld_rst_i_1_n_0;\n wire iserdes_clkdiv;\n wire [7:0]mem_dq_in;\n wire [8:0]mem_dq_out;\n wire [8:0]mem_dq_ts;\n wire [0:0]mem_dqs_out;\n wire [0:0]mem_dqs_ts;\n wire [35:0]of_dqbus;\n wire oserdes_clk;\n wire oserdes_clk_delayed;\n wire oserdes_clkdiv;\n wire po_oserdes_rst;\n wire rst_r3_reg_srl3_n_0;\n wire rst_r4;\n wire tbyte_out;\n wire \\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ;\n wire \\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ;\n wire [4:0]\\NLW_input_[0].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[0].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[0].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[0].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[0].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[0].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[0].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[0].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[0].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ;\n\n (* __SRVAL = \"FALSE\" *) \n (* box_type = \"PRIMITIVE\" *) \n ODDR #(\n .DDR_CLK_EDGE(\"SAME_EDGE\"),\n .INIT(1'b0),\n .IS_C_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .SRTYPE(\"SYNC\")) \n \\dqs_gen.oddr_dqs \n (.C(oserdes_clk_delayed),\n .CE(1'b1),\n .D1(DQSBUS[0]),\n .D2(DQSBUS[1]),\n .Q(mem_dqs_out),\n .R(1'b0),\n .S(\\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ));\n (* __SRVAL = \"TRUE\" *) \n (* box_type = \"PRIMITIVE\" *) \n ODDR #(\n .DDR_CLK_EDGE(\"SAME_EDGE\"),\n .INIT(1'b0),\n .IS_C_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .SRTYPE(\"SYNC\")) \n \\dqs_gen.oddr_dqsts \n (.C(oserdes_clk_delayed),\n .CE(1'b1),\n .D1(CTSBUS),\n .D2(CTSBUS),\n .Q(mem_dqs_ts),\n .R(\\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ),\n .S(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_r_reg[11] \n (.C(CLK),\n .CE(E),\n .D(\\fine_delay_mod_reg[23] [3]),\n .Q(fine_delay_r[11]),\n .R(A_rst_primitives));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_r_reg[14] \n (.C(CLK),\n .CE(E),\n .D(\\fine_delay_mod_reg[23] [4]),\n .Q(fine_delay_r[14]),\n .R(A_rst_primitives));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_r_reg[17] \n (.C(CLK),\n .CE(E),\n .D(\\fine_delay_mod_reg[23] [5]),\n .Q(fine_delay_r[17]),\n .R(A_rst_primitives));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_r_reg[20] \n (.C(CLK),\n .CE(E),\n .D(\\fine_delay_mod_reg[23] [6]),\n .Q(fine_delay_r[20]),\n .R(A_rst_primitives));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_r_reg[23] \n (.C(CLK),\n .CE(E),\n .D(\\fine_delay_mod_reg[23] [7]),\n .Q(fine_delay_r[23]),\n .R(A_rst_primitives));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_r_reg[2] \n (.C(CLK),\n .CE(E),\n .D(\\fine_delay_mod_reg[23] [0]),\n .Q(fine_delay_r[2]),\n .R(A_rst_primitives));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_r_reg[5] \n (.C(CLK),\n .CE(E),\n .D(\\fine_delay_mod_reg[23] [1]),\n .Q(fine_delay_r[5]),\n .R(A_rst_primitives));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_r_reg[8] \n (.C(CLK),\n .CE(E),\n .D(\\fine_delay_mod_reg[23] [2]),\n .Q(fine_delay_r[8]),\n .R(A_rst_primitives));\n LUT2 #(\n .INIT(4'h2)) \n idelay_ld_rst_i_1\n (.I0(idelay_ld_rst),\n .I1(rst_r4),\n .O(idelay_ld_rst_i_1_n_0));\n FDSE #(\n .INIT(1'b1)) \n idelay_ld_rst_reg\n (.C(CLK),\n .CE(1'b1),\n .D(idelay_ld_rst_i_1_n_0),\n .Q(idelay_ld_rst),\n .S(A_rst_primitives));\n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[0].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[0].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_0),\n .IDATAIN(mem_dq_in[0]),\n .IFDLY({fine_delay_r[2],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* box_type = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[0].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0),\n .CLKDIV(\\NLW_input_[0].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[0]),\n .DDLY(data_in_dly_0),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[0].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[0].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[0].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D0[3]),\n .Q2(D0[2]),\n .Q3(D0[1]),\n .Q4(D0[0]),\n .Q5(\\NLW_input_[0].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[0].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[0].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[0].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_1),\n .IDATAIN(mem_dq_in[1]),\n .IFDLY({fine_delay_r[5],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* box_type = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[1].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0),\n .CLKDIV(\\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[1]),\n .DDLY(data_in_dly_1),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D1[3]),\n .Q2(D1[2]),\n .Q3(D1[1]),\n .Q4(D1[0]),\n .Q5(\\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_2),\n .IDATAIN(mem_dq_in[2]),\n .IFDLY({fine_delay_r[8],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* box_type = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[2].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0),\n .CLKDIV(\\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[2]),\n .DDLY(data_in_dly_2),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D2[3]),\n .Q2(D2[2]),\n .Q3(D2[1]),\n .Q4(D2[0]),\n .Q5(\\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_3),\n .IDATAIN(mem_dq_in[3]),\n .IFDLY({fine_delay_r[11],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* box_type = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[3].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0),\n .CLKDIV(\\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[3]),\n .DDLY(data_in_dly_3),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D3[3]),\n .Q2(D3[2]),\n .Q3(D3[1]),\n .Q4(D3[0]),\n .Q5(\\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_4),\n .IDATAIN(mem_dq_in[4]),\n .IFDLY({fine_delay_r[14],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* box_type = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[4].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0),\n .CLKDIV(\\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[4]),\n .DDLY(data_in_dly_4),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D4[3]),\n .Q2(D4[2]),\n .Q3(D4[1]),\n .Q4(D4[0]),\n .Q5(\\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_5),\n .IDATAIN(mem_dq_in[5]),\n .IFDLY({fine_delay_r[17],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* box_type = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[5].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0),\n .CLKDIV(\\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[5]),\n .DDLY(data_in_dly_5),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D5[3]),\n .Q2(D5[2]),\n .Q3(D5[1]),\n .Q4(D5[0]),\n .Q5(\\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_6),\n .IDATAIN(mem_dq_in[6]),\n .IFDLY({fine_delay_r[20],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* box_type = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[6].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0),\n .CLKDIV(\\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[6]),\n .DDLY(data_in_dly_6),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D6[3]),\n .Q2(D6[2]),\n .Q3(D6[1]),\n .Q4(D6[0]),\n .Q5(\\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_7),\n .IDATAIN(mem_dq_in[7]),\n .IFDLY({fine_delay_r[23],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* box_type = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[7].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0),\n .CLKDIV(\\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[7]),\n .DDLY(data_in_dly_7),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D7[3]),\n .Q2(D7[2]),\n .Q3(D7[1]),\n .Q4(D7[0]),\n .Q5(\\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[0].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[0]),\n .D2(of_dqbus[1]),\n .D3(of_dqbus[2]),\n .D4(of_dqbus[3]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[0]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[0]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[1].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[4]),\n .D2(of_dqbus[5]),\n .D3(of_dqbus[6]),\n .D4(of_dqbus[7]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[1]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[1]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[2].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[8]),\n .D2(of_dqbus[9]),\n .D3(of_dqbus[10]),\n .D4(of_dqbus[11]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[2]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[2]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[3].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[12]),\n .D2(of_dqbus[13]),\n .D3(of_dqbus[14]),\n .D4(of_dqbus[15]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[3]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[3]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[4].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[16]),\n .D2(of_dqbus[17]),\n .D3(of_dqbus[18]),\n .D4(of_dqbus[19]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[4]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[4]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[5].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[20]),\n .D2(of_dqbus[21]),\n .D3(of_dqbus[22]),\n .D4(of_dqbus[23]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[5]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[5]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[6].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[24]),\n .D2(of_dqbus[25]),\n .D3(of_dqbus[26]),\n .D4(of_dqbus[27]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[6]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[6]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[7].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[28]),\n .D2(of_dqbus[29]),\n .D3(of_dqbus[30]),\n .D4(of_dqbus[31]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[7]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[7]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[9].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[32]),\n .D2(of_dqbus[33]),\n .D3(of_dqbus[34]),\n .D4(of_dqbus[35]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[8]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[8]));\n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/rst_r3_reg_srl3 \" *) \n SRL16E #(\n .INIT(16'h0000)) \n rst_r3_reg_srl3\n (.A0(1'b0),\n .A1(1'b1),\n .A2(1'b0),\n .A3(1'b0),\n .CE(1'b1),\n .CLK(CLK),\n .D(A_rst_primitives),\n .Q(rst_r3_reg_srl3_n_0));\n FDRE #(\n .INIT(1'b0)) \n rst_r4_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rst_r3_reg_srl3_n_0),\n .Q(rst_r4),\n .R(1'b0));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"TRUE\"),\n .TRISTATE_WIDTH(4)) \n \\slave_ts.oserdes_slave_ts \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(1'b0),\n .D2(1'b0),\n .D3(1'b0),\n .D4(1'b0),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ),\n .OQ(\\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ),\n .T1(DTSBUS[0]),\n .T2(DTSBUS[0]),\n .T3(DTSBUS[1]),\n .T4(DTSBUS[1]),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(tbyte_out),\n .TCE(1'b1),\n .TFB(\\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ),\n .TQ(\\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_byte_group_io\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_byte_group_io__parameterized0\n (mem_dqs_out,\n mem_dqs_ts,\n D1,\n D2,\n D3,\n D4,\n D5,\n D6,\n D7,\n D8,\n mem_dq_out,\n mem_dq_ts,\n idelay_ld_rst_0,\n oserdes_clk,\n oserdes_clkdiv,\n po_oserdes_rst,\n DTSBUS,\n oserdes_clk_delayed,\n DQSBUS,\n CTSBUS,\n CLK,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n mem_dq_in,\n idelay_inc,\n LD0_3,\n A_rst_primitives,\n A_rst_primitives_reg,\n CLKB0_7,\n iserdes_clkdiv,\n of_dqbus,\n rst_r4,\n \\gen_byte_sel_div1.calib_in_common_reg_0 ,\n \\calib_sel_reg[0] );\n output [0:0]mem_dqs_out;\n output [0:0]mem_dqs_ts;\n output [3:0]D1;\n output [3:0]D2;\n output [3:0]D3;\n output [3:0]D4;\n output [3:0]D5;\n output [3:0]D6;\n output [3:0]D7;\n output [3:0]D8;\n output [8:0]mem_dq_out;\n output [8:0]mem_dq_ts;\n output idelay_ld_rst_0;\n input oserdes_clk;\n input oserdes_clkdiv;\n input po_oserdes_rst;\n input [1:0]DTSBUS;\n input oserdes_clk_delayed;\n input [1:0]DQSBUS;\n input [0:0]CTSBUS;\n input CLK;\n input \\gen_byte_sel_div1.calib_in_common_reg ;\n input [7:0]mem_dq_in;\n input idelay_inc;\n input LD0_3;\n input A_rst_primitives;\n input A_rst_primitives_reg;\n input CLKB0_7;\n input iserdes_clkdiv;\n input [35:0]of_dqbus;\n input rst_r4;\n input [0:0]\\gen_byte_sel_div1.calib_in_common_reg_0 ;\n input [7:0]\\calib_sel_reg[0] ;\n\n wire A_rst_primitives;\n wire A_rst_primitives_reg;\n wire CLK;\n wire CLKB0_7;\n wire [0:0]CTSBUS;\n wire [3:0]D1;\n wire [3:0]D2;\n wire [3:0]D3;\n wire [3:0]D4;\n wire [3:0]D5;\n wire [3:0]D6;\n wire [3:0]D7;\n wire [3:0]D8;\n wire [1:0]DQSBUS;\n wire [1:0]DTSBUS;\n wire LD0_3;\n wire [7:0]\\calib_sel_reg[0] ;\n wire data_in_dly_1;\n wire data_in_dly_2;\n wire data_in_dly_3;\n wire data_in_dly_4;\n wire data_in_dly_5;\n wire data_in_dly_6;\n wire data_in_dly_7;\n wire data_in_dly_8;\n wire [26:5]fine_delay_r;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire [0:0]\\gen_byte_sel_div1.calib_in_common_reg_0 ;\n wire idelay_inc;\n wire idelay_ld_rst_0;\n wire idelay_ld_rst_i_1__0_n_0;\n wire iserdes_clkdiv;\n wire [7:0]mem_dq_in;\n wire [8:0]mem_dq_out;\n wire [8:0]mem_dq_ts;\n wire [0:0]mem_dqs_out;\n wire [0:0]mem_dqs_ts;\n wire [35:0]of_dqbus;\n wire oserdes_clk;\n wire oserdes_clk_delayed;\n wire oserdes_clkdiv;\n wire po_oserdes_rst;\n wire rst_r4;\n wire tbyte_out;\n wire \\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ;\n wire \\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ;\n wire [4:0]\\NLW_input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ;\n\n (* __SRVAL = \"FALSE\" *) \n (* box_type = \"PRIMITIVE\" *) \n ODDR #(\n .DDR_CLK_EDGE(\"SAME_EDGE\"),\n .INIT(1'b0),\n .IS_C_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .SRTYPE(\"SYNC\")) \n \\dqs_gen.oddr_dqs \n (.C(oserdes_clk_delayed),\n .CE(1'b1),\n .D1(DQSBUS[0]),\n .D2(DQSBUS[1]),\n .Q(mem_dqs_out),\n .R(1'b0),\n .S(\\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ));\n (* __SRVAL = \"TRUE\" *) \n (* box_type = \"PRIMITIVE\" *) \n ODDR #(\n .DDR_CLK_EDGE(\"SAME_EDGE\"),\n .INIT(1'b0),\n .IS_C_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .SRTYPE(\"SYNC\")) \n \\dqs_gen.oddr_dqsts \n (.C(oserdes_clk_delayed),\n .CE(1'b1),\n .D1(CTSBUS),\n .D2(CTSBUS),\n .Q(mem_dqs_ts),\n .R(\\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ),\n .S(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_r_reg[11] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[0] [2]),\n .Q(fine_delay_r[11]),\n .R(A_rst_primitives));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_r_reg[14] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[0] [3]),\n .Q(fine_delay_r[14]),\n .R(A_rst_primitives));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_r_reg[17] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[0] [4]),\n .Q(fine_delay_r[17]),\n .R(A_rst_primitives));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_r_reg[20] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[0] [5]),\n .Q(fine_delay_r[20]),\n .R(A_rst_primitives));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_r_reg[23] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[0] [6]),\n .Q(fine_delay_r[23]),\n .R(A_rst_primitives));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_r_reg[26] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[0] [7]),\n .Q(fine_delay_r[26]),\n .R(A_rst_primitives));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_r_reg[5] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[0] [0]),\n .Q(fine_delay_r[5]),\n .R(A_rst_primitives));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_r_reg[8] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[0] [1]),\n .Q(fine_delay_r[8]),\n .R(A_rst_primitives));\n LUT2 #(\n .INIT(4'h2)) \n idelay_ld_rst_i_1__0\n (.I0(idelay_ld_rst_0),\n .I1(rst_r4),\n .O(idelay_ld_rst_i_1__0_n_0));\n FDSE #(\n .INIT(1'b1)) \n idelay_ld_rst_reg\n (.C(CLK),\n .CE(1'b1),\n .D(idelay_ld_rst_i_1__0_n_0),\n .Q(idelay_ld_rst_0),\n .S(A_rst_primitives));\n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_1),\n .IDATAIN(mem_dq_in[0]),\n .IFDLY({fine_delay_r[5],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_3),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* box_type = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[1].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_7),\n .CLKDIV(\\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[0]),\n .DDLY(data_in_dly_1),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D1[3]),\n .Q2(D1[2]),\n .Q3(D1[1]),\n .Q4(D1[0]),\n .Q5(\\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_2),\n .IDATAIN(mem_dq_in[1]),\n .IFDLY({fine_delay_r[8],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_3),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* box_type = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[2].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_7),\n .CLKDIV(\\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[1]),\n .DDLY(data_in_dly_2),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D2[3]),\n .Q2(D2[2]),\n .Q3(D2[1]),\n .Q4(D2[0]),\n .Q5(\\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_3),\n .IDATAIN(mem_dq_in[2]),\n .IFDLY({fine_delay_r[11],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_3),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* box_type = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[3].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_7),\n .CLKDIV(\\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[2]),\n .DDLY(data_in_dly_3),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D3[3]),\n .Q2(D3[2]),\n .Q3(D3[1]),\n .Q4(D3[0]),\n .Q5(\\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_4),\n .IDATAIN(mem_dq_in[3]),\n .IFDLY({fine_delay_r[14],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_3),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* box_type = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[4].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_7),\n .CLKDIV(\\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[3]),\n .DDLY(data_in_dly_4),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D4[3]),\n .Q2(D4[2]),\n .Q3(D4[1]),\n .Q4(D4[0]),\n .Q5(\\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_5),\n .IDATAIN(mem_dq_in[4]),\n .IFDLY({fine_delay_r[17],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_3),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* box_type = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[5].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_7),\n .CLKDIV(\\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[4]),\n .DDLY(data_in_dly_5),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D5[3]),\n .Q2(D5[2]),\n .Q3(D5[1]),\n .Q4(D5[0]),\n .Q5(\\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_6),\n .IDATAIN(mem_dq_in[5]),\n .IFDLY({fine_delay_r[20],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_3),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* box_type = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[6].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_7),\n .CLKDIV(\\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[5]),\n .DDLY(data_in_dly_6),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D6[3]),\n .Q2(D6[2]),\n .Q3(D6[1]),\n .Q4(D6[0]),\n .Q5(\\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_7),\n .IDATAIN(mem_dq_in[6]),\n .IFDLY({fine_delay_r[23],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_3),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* box_type = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[7].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_7),\n .CLKDIV(\\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[6]),\n .DDLY(data_in_dly_7),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D7[3]),\n .Q2(D7[2]),\n .Q3(D7[1]),\n .Q4(D7[0]),\n .Q5(\\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_8),\n .IDATAIN(mem_dq_in[7]),\n .IFDLY({fine_delay_r[26],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_3),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* box_type = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[8].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_7),\n .CLKDIV(\\NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[7]),\n .DDLY(data_in_dly_8),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D8[3]),\n .Q2(D8[2]),\n .Q3(D8[1]),\n .Q4(D8[0]),\n .Q5(\\NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[1].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[0]),\n .D2(of_dqbus[1]),\n .D3(of_dqbus[2]),\n .D4(of_dqbus[3]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[0]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[0]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[2].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[4]),\n .D2(of_dqbus[5]),\n .D3(of_dqbus[6]),\n .D4(of_dqbus[7]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[1]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[1]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[3].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[8]),\n .D2(of_dqbus[9]),\n .D3(of_dqbus[10]),\n .D4(of_dqbus[11]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[2]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[2]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[4].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[12]),\n .D2(of_dqbus[13]),\n .D3(of_dqbus[14]),\n .D4(of_dqbus[15]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[3]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[3]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[5].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[16]),\n .D2(of_dqbus[17]),\n .D3(of_dqbus[18]),\n .D4(of_dqbus[19]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[4]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[4]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[6].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[20]),\n .D2(of_dqbus[21]),\n .D3(of_dqbus[22]),\n .D4(of_dqbus[23]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[5]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[5]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[7].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[24]),\n .D2(of_dqbus[25]),\n .D3(of_dqbus[26]),\n .D4(of_dqbus[27]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[6]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[6]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[8].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[28]),\n .D2(of_dqbus[29]),\n .D3(of_dqbus[30]),\n .D4(of_dqbus[31]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[7]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[7]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[9].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[32]),\n .D2(of_dqbus[33]),\n .D3(of_dqbus[34]),\n .D4(of_dqbus[35]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[8]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[8]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"TRUE\"),\n .TRISTATE_WIDTH(4)) \n \\slave_ts.oserdes_slave_ts \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(1'b0),\n .D2(1'b0),\n .D3(1'b0),\n .D4(1'b0),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ),\n .OQ(\\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ),\n .T1(DTSBUS[0]),\n .T2(DTSBUS[0]),\n .T3(DTSBUS[1]),\n .T4(DTSBUS[1]),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(tbyte_out),\n .TCE(1'b1),\n .TFB(\\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ),\n .TQ(\\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_byte_group_io\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_byte_group_io__parameterized1\n (mem_dqs_out,\n mem_dqs_ts,\n D1,\n D2,\n D3,\n D4,\n D5,\n D6,\n D7,\n D8,\n mem_dq_out,\n mem_dq_ts,\n idelay_ld_rst_1,\n oserdes_clk,\n oserdes_clkdiv,\n po_oserdes_rst,\n DTSBUS,\n oserdes_clk_delayed,\n DQSBUS,\n CTSBUS,\n CLK,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n mem_dq_in,\n idelay_inc,\n LD0_4,\n A_rst_primitives,\n A_rst_primitives_reg,\n CLKB0_8,\n iserdes_clkdiv,\n of_dqbus,\n rst_r4,\n \\gen_byte_sel_div1.calib_in_common_reg_0 ,\n \\calib_sel_reg[1] );\n output [0:0]mem_dqs_out;\n output [0:0]mem_dqs_ts;\n output [3:0]D1;\n output [3:0]D2;\n output [3:0]D3;\n output [3:0]D4;\n output [3:0]D5;\n output [3:0]D6;\n output [3:0]D7;\n output [3:0]D8;\n output [8:0]mem_dq_out;\n output [8:0]mem_dq_ts;\n output idelay_ld_rst_1;\n input oserdes_clk;\n input oserdes_clkdiv;\n input po_oserdes_rst;\n input [1:0]DTSBUS;\n input oserdes_clk_delayed;\n input [1:0]DQSBUS;\n input [0:0]CTSBUS;\n input CLK;\n input \\gen_byte_sel_div1.calib_in_common_reg ;\n input [7:0]mem_dq_in;\n input idelay_inc;\n input LD0_4;\n input A_rst_primitives;\n input A_rst_primitives_reg;\n input CLKB0_8;\n input iserdes_clkdiv;\n input [35:0]of_dqbus;\n input rst_r4;\n input [0:0]\\gen_byte_sel_div1.calib_in_common_reg_0 ;\n input [7:0]\\calib_sel_reg[1] ;\n\n wire A_rst_primitives;\n wire A_rst_primitives_reg;\n wire CLK;\n wire CLKB0_8;\n wire [0:0]CTSBUS;\n wire [3:0]D1;\n wire [3:0]D2;\n wire [3:0]D3;\n wire [3:0]D4;\n wire [3:0]D5;\n wire [3:0]D6;\n wire [3:0]D7;\n wire [3:0]D8;\n wire [1:0]DQSBUS;\n wire [1:0]DTSBUS;\n wire LD0_4;\n wire [7:0]\\calib_sel_reg[1] ;\n wire data_in_dly_1;\n wire data_in_dly_2;\n wire data_in_dly_3;\n wire data_in_dly_4;\n wire data_in_dly_5;\n wire data_in_dly_6;\n wire data_in_dly_7;\n wire data_in_dly_8;\n wire [26:5]fine_delay_r;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire [0:0]\\gen_byte_sel_div1.calib_in_common_reg_0 ;\n wire idelay_inc;\n wire idelay_ld_rst_1;\n wire idelay_ld_rst_i_1__1_n_0;\n wire iserdes_clkdiv;\n wire [7:0]mem_dq_in;\n wire [8:0]mem_dq_out;\n wire [8:0]mem_dq_ts;\n wire [0:0]mem_dqs_out;\n wire [0:0]mem_dqs_ts;\n wire [35:0]of_dqbus;\n wire oserdes_clk;\n wire oserdes_clk_delayed;\n wire oserdes_clkdiv;\n wire po_oserdes_rst;\n wire rst_r4;\n wire tbyte_out;\n wire \\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ;\n wire \\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ;\n wire [4:0]\\NLW_input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ;\n\n (* __SRVAL = \"FALSE\" *) \n (* box_type = \"PRIMITIVE\" *) \n ODDR #(\n .DDR_CLK_EDGE(\"SAME_EDGE\"),\n .INIT(1'b0),\n .IS_C_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .SRTYPE(\"SYNC\")) \n \\dqs_gen.oddr_dqs \n (.C(oserdes_clk_delayed),\n .CE(1'b1),\n .D1(DQSBUS[0]),\n .D2(DQSBUS[1]),\n .Q(mem_dqs_out),\n .R(1'b0),\n .S(\\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ));\n (* __SRVAL = \"TRUE\" *) \n (* box_type = \"PRIMITIVE\" *) \n ODDR #(\n .DDR_CLK_EDGE(\"SAME_EDGE\"),\n .INIT(1'b0),\n .IS_C_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .SRTYPE(\"SYNC\")) \n \\dqs_gen.oddr_dqsts \n (.C(oserdes_clk_delayed),\n .CE(1'b1),\n .D1(CTSBUS),\n .D2(CTSBUS),\n .Q(mem_dqs_ts),\n .R(\\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ),\n .S(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_r_reg[11] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[1] [2]),\n .Q(fine_delay_r[11]),\n .R(A_rst_primitives));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_r_reg[14] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[1] [3]),\n .Q(fine_delay_r[14]),\n .R(A_rst_primitives));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_r_reg[17] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[1] [4]),\n .Q(fine_delay_r[17]),\n .R(A_rst_primitives));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_r_reg[20] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[1] [5]),\n .Q(fine_delay_r[20]),\n .R(A_rst_primitives));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_r_reg[23] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[1] [6]),\n .Q(fine_delay_r[23]),\n .R(A_rst_primitives));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_r_reg[26] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[1] [7]),\n .Q(fine_delay_r[26]),\n .R(A_rst_primitives));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_r_reg[5] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[1] [0]),\n .Q(fine_delay_r[5]),\n .R(A_rst_primitives));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_r_reg[8] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[1] [1]),\n .Q(fine_delay_r[8]),\n .R(A_rst_primitives));\n LUT2 #(\n .INIT(4'h2)) \n idelay_ld_rst_i_1__1\n (.I0(idelay_ld_rst_1),\n .I1(rst_r4),\n .O(idelay_ld_rst_i_1__1_n_0));\n FDSE #(\n .INIT(1'b1)) \n idelay_ld_rst_reg\n (.C(CLK),\n .CE(1'b1),\n .D(idelay_ld_rst_i_1__1_n_0),\n .Q(idelay_ld_rst_1),\n .S(A_rst_primitives));\n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_1),\n .IDATAIN(mem_dq_in[0]),\n .IFDLY({fine_delay_r[5],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_4),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* box_type = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[1].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_8),\n .CLKDIV(\\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[0]),\n .DDLY(data_in_dly_1),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D1[3]),\n .Q2(D1[2]),\n .Q3(D1[1]),\n .Q4(D1[0]),\n .Q5(\\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_2),\n .IDATAIN(mem_dq_in[1]),\n .IFDLY({fine_delay_r[8],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_4),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* box_type = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[2].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_8),\n .CLKDIV(\\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[1]),\n .DDLY(data_in_dly_2),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D2[3]),\n .Q2(D2[2]),\n .Q3(D2[1]),\n .Q4(D2[0]),\n .Q5(\\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_3),\n .IDATAIN(mem_dq_in[2]),\n .IFDLY({fine_delay_r[11],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_4),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* box_type = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[3].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_8),\n .CLKDIV(\\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[2]),\n .DDLY(data_in_dly_3),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D3[3]),\n .Q2(D3[2]),\n .Q3(D3[1]),\n .Q4(D3[0]),\n .Q5(\\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_4),\n .IDATAIN(mem_dq_in[3]),\n .IFDLY({fine_delay_r[14],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_4),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* box_type = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[4].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_8),\n .CLKDIV(\\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[3]),\n .DDLY(data_in_dly_4),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D4[3]),\n .Q2(D4[2]),\n .Q3(D4[1]),\n .Q4(D4[0]),\n .Q5(\\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_5),\n .IDATAIN(mem_dq_in[4]),\n .IFDLY({fine_delay_r[17],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_4),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* box_type = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[5].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_8),\n .CLKDIV(\\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[4]),\n .DDLY(data_in_dly_5),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D5[3]),\n .Q2(D5[2]),\n .Q3(D5[1]),\n .Q4(D5[0]),\n .Q5(\\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_6),\n .IDATAIN(mem_dq_in[5]),\n .IFDLY({fine_delay_r[20],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_4),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* box_type = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[6].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_8),\n .CLKDIV(\\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[5]),\n .DDLY(data_in_dly_6),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D6[3]),\n .Q2(D6[2]),\n .Q3(D6[1]),\n .Q4(D6[0]),\n .Q5(\\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_7),\n .IDATAIN(mem_dq_in[6]),\n .IFDLY({fine_delay_r[23],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_4),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* box_type = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[7].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_8),\n .CLKDIV(\\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[6]),\n .DDLY(data_in_dly_7),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D7[3]),\n .Q2(D7[2]),\n .Q3(D7[1]),\n .Q4(D7[0]),\n .Q5(\\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_8),\n .IDATAIN(mem_dq_in[7]),\n .IFDLY({fine_delay_r[26],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_4),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* box_type = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[8].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_8),\n .CLKDIV(\\NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[7]),\n .DDLY(data_in_dly_8),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D8[3]),\n .Q2(D8[2]),\n .Q3(D8[1]),\n .Q4(D8[0]),\n .Q5(\\NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[1].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[0]),\n .D2(of_dqbus[1]),\n .D3(of_dqbus[2]),\n .D4(of_dqbus[3]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[0]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[0]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[2].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[4]),\n .D2(of_dqbus[5]),\n .D3(of_dqbus[6]),\n .D4(of_dqbus[7]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[1]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[1]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[3].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[8]),\n .D2(of_dqbus[9]),\n .D3(of_dqbus[10]),\n .D4(of_dqbus[11]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[2]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[2]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[4].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[12]),\n .D2(of_dqbus[13]),\n .D3(of_dqbus[14]),\n .D4(of_dqbus[15]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[3]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[3]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[5].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[16]),\n .D2(of_dqbus[17]),\n .D3(of_dqbus[18]),\n .D4(of_dqbus[19]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[4]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[4]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[6].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[20]),\n .D2(of_dqbus[21]),\n .D3(of_dqbus[22]),\n .D4(of_dqbus[23]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[5]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[5]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[7].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[24]),\n .D2(of_dqbus[25]),\n .D3(of_dqbus[26]),\n .D4(of_dqbus[27]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[6]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[6]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[8].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[28]),\n .D2(of_dqbus[29]),\n .D3(of_dqbus[30]),\n .D4(of_dqbus[31]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[7]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[7]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[9].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[32]),\n .D2(of_dqbus[33]),\n .D3(of_dqbus[34]),\n .D4(of_dqbus[35]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[8]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[8]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"TRUE\"),\n .TRISTATE_WIDTH(4)) \n \\slave_ts.oserdes_slave_ts \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(1'b0),\n .D2(1'b0),\n .D3(1'b0),\n .D4(1'b0),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ),\n .OQ(\\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ),\n .T1(DTSBUS[0]),\n .T2(DTSBUS[0]),\n .T3(DTSBUS[1]),\n .T4(DTSBUS[1]),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(tbyte_out),\n .TCE(1'b1),\n .TFB(\\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ),\n .TQ(\\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_byte_group_io\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_byte_group_io__parameterized2\n (mem_dqs_out,\n mem_dqs_ts,\n D1,\n D2,\n D3,\n D4,\n D5,\n D6,\n D7,\n D8,\n mem_dq_out,\n mem_dq_ts,\n idelay_ld_rst_2,\n oserdes_clk,\n oserdes_clkdiv,\n po_oserdes_rst,\n DTSBUS,\n oserdes_clk_delayed,\n DQSBUS,\n CTSBUS,\n CLK,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n mem_dq_in,\n idelay_inc,\n LD0_5,\n A_rst_primitives,\n A_rst_primitives_reg,\n CLKB0_9,\n iserdes_clkdiv,\n of_dqbus,\n rst_r4,\n \\gen_byte_sel_div1.calib_in_common_reg_0 ,\n \\calib_sel_reg[0] );\n output [0:0]mem_dqs_out;\n output [0:0]mem_dqs_ts;\n output [3:0]D1;\n output [3:0]D2;\n output [3:0]D3;\n output [3:0]D4;\n output [3:0]D5;\n output [3:0]D6;\n output [3:0]D7;\n output [3:0]D8;\n output [8:0]mem_dq_out;\n output [8:0]mem_dq_ts;\n output idelay_ld_rst_2;\n input oserdes_clk;\n input oserdes_clkdiv;\n input po_oserdes_rst;\n input [1:0]DTSBUS;\n input oserdes_clk_delayed;\n input [1:0]DQSBUS;\n input [0:0]CTSBUS;\n input CLK;\n input \\gen_byte_sel_div1.calib_in_common_reg ;\n input [7:0]mem_dq_in;\n input idelay_inc;\n input LD0_5;\n input A_rst_primitives;\n input A_rst_primitives_reg;\n input CLKB0_9;\n input iserdes_clkdiv;\n input [35:0]of_dqbus;\n input rst_r4;\n input [0:0]\\gen_byte_sel_div1.calib_in_common_reg_0 ;\n input [7:0]\\calib_sel_reg[0] ;\n\n wire A_rst_primitives;\n wire A_rst_primitives_reg;\n wire CLK;\n wire CLKB0_9;\n wire [0:0]CTSBUS;\n wire [3:0]D1;\n wire [3:0]D2;\n wire [3:0]D3;\n wire [3:0]D4;\n wire [3:0]D5;\n wire [3:0]D6;\n wire [3:0]D7;\n wire [3:0]D8;\n wire [1:0]DQSBUS;\n wire [1:0]DTSBUS;\n wire LD0_5;\n wire [7:0]\\calib_sel_reg[0] ;\n wire data_in_dly_1;\n wire data_in_dly_2;\n wire data_in_dly_3;\n wire data_in_dly_4;\n wire data_in_dly_5;\n wire data_in_dly_6;\n wire data_in_dly_7;\n wire data_in_dly_8;\n wire [26:5]fine_delay_r;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire [0:0]\\gen_byte_sel_div1.calib_in_common_reg_0 ;\n wire idelay_inc;\n wire idelay_ld_rst_2;\n wire idelay_ld_rst_i_1__2_n_0;\n wire iserdes_clkdiv;\n wire [7:0]mem_dq_in;\n wire [8:0]mem_dq_out;\n wire [8:0]mem_dq_ts;\n wire [0:0]mem_dqs_out;\n wire [0:0]mem_dqs_ts;\n wire [35:0]of_dqbus;\n wire oserdes_clk;\n wire oserdes_clk_delayed;\n wire oserdes_clkdiv;\n wire po_oserdes_rst;\n wire rst_r4;\n wire tbyte_out;\n wire \\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ;\n wire \\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ;\n wire [4:0]\\NLW_input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ;\n\n (* __SRVAL = \"FALSE\" *) \n (* box_type = \"PRIMITIVE\" *) \n ODDR #(\n .DDR_CLK_EDGE(\"SAME_EDGE\"),\n .INIT(1'b0),\n .IS_C_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .SRTYPE(\"SYNC\")) \n \\dqs_gen.oddr_dqs \n (.C(oserdes_clk_delayed),\n .CE(1'b1),\n .D1(DQSBUS[0]),\n .D2(DQSBUS[1]),\n .Q(mem_dqs_out),\n .R(1'b0),\n .S(\\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ));\n (* __SRVAL = \"TRUE\" *) \n (* box_type = \"PRIMITIVE\" *) \n ODDR #(\n .DDR_CLK_EDGE(\"SAME_EDGE\"),\n .INIT(1'b0),\n .IS_C_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .SRTYPE(\"SYNC\")) \n \\dqs_gen.oddr_dqsts \n (.C(oserdes_clk_delayed),\n .CE(1'b1),\n .D1(CTSBUS),\n .D2(CTSBUS),\n .Q(mem_dqs_ts),\n .R(\\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ),\n .S(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_r_reg[11] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[0] [2]),\n .Q(fine_delay_r[11]),\n .R(A_rst_primitives));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_r_reg[14] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[0] [3]),\n .Q(fine_delay_r[14]),\n .R(A_rst_primitives));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_r_reg[17] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[0] [4]),\n .Q(fine_delay_r[17]),\n .R(A_rst_primitives));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_r_reg[20] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[0] [5]),\n .Q(fine_delay_r[20]),\n .R(A_rst_primitives));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_r_reg[23] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[0] [6]),\n .Q(fine_delay_r[23]),\n .R(A_rst_primitives));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_r_reg[26] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[0] [7]),\n .Q(fine_delay_r[26]),\n .R(A_rst_primitives));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_r_reg[5] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[0] [0]),\n .Q(fine_delay_r[5]),\n .R(A_rst_primitives));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_r_reg[8] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[0] [1]),\n .Q(fine_delay_r[8]),\n .R(A_rst_primitives));\n LUT2 #(\n .INIT(4'h2)) \n idelay_ld_rst_i_1__2\n (.I0(idelay_ld_rst_2),\n .I1(rst_r4),\n .O(idelay_ld_rst_i_1__2_n_0));\n FDSE #(\n .INIT(1'b1)) \n idelay_ld_rst_reg\n (.C(CLK),\n .CE(1'b1),\n .D(idelay_ld_rst_i_1__2_n_0),\n .Q(idelay_ld_rst_2),\n .S(A_rst_primitives));\n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_1),\n .IDATAIN(mem_dq_in[0]),\n .IFDLY({fine_delay_r[5],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_5),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* box_type = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[1].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_9),\n .CLKDIV(\\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[0]),\n .DDLY(data_in_dly_1),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D1[3]),\n .Q2(D1[2]),\n .Q3(D1[1]),\n .Q4(D1[0]),\n .Q5(\\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_2),\n .IDATAIN(mem_dq_in[1]),\n .IFDLY({fine_delay_r[8],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_5),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* box_type = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[2].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_9),\n .CLKDIV(\\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[1]),\n .DDLY(data_in_dly_2),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D2[3]),\n .Q2(D2[2]),\n .Q3(D2[1]),\n .Q4(D2[0]),\n .Q5(\\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_3),\n .IDATAIN(mem_dq_in[2]),\n .IFDLY({fine_delay_r[11],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_5),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* box_type = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[3].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_9),\n .CLKDIV(\\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[2]),\n .DDLY(data_in_dly_3),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D3[3]),\n .Q2(D3[2]),\n .Q3(D3[1]),\n .Q4(D3[0]),\n .Q5(\\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_4),\n .IDATAIN(mem_dq_in[3]),\n .IFDLY({fine_delay_r[14],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_5),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* box_type = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[4].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_9),\n .CLKDIV(\\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[3]),\n .DDLY(data_in_dly_4),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D4[3]),\n .Q2(D4[2]),\n .Q3(D4[1]),\n .Q4(D4[0]),\n .Q5(\\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_5),\n .IDATAIN(mem_dq_in[4]),\n .IFDLY({fine_delay_r[17],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_5),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* box_type = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[5].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_9),\n .CLKDIV(\\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[4]),\n .DDLY(data_in_dly_5),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D5[3]),\n .Q2(D5[2]),\n .Q3(D5[1]),\n .Q4(D5[0]),\n .Q5(\\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_6),\n .IDATAIN(mem_dq_in[5]),\n .IFDLY({fine_delay_r[20],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_5),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* box_type = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[6].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_9),\n .CLKDIV(\\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[5]),\n .DDLY(data_in_dly_6),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D6[3]),\n .Q2(D6[2]),\n .Q3(D6[1]),\n .Q4(D6[0]),\n .Q5(\\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_7),\n .IDATAIN(mem_dq_in[6]),\n .IFDLY({fine_delay_r[23],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_5),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* box_type = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[7].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_9),\n .CLKDIV(\\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[6]),\n .DDLY(data_in_dly_7),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D7[3]),\n .Q2(D7[2]),\n .Q3(D7[1]),\n .Q4(D7[0]),\n .Q5(\\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_8),\n .IDATAIN(mem_dq_in[7]),\n .IFDLY({fine_delay_r[26],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_5),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* box_type = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[8].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_9),\n .CLKDIV(\\NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[7]),\n .DDLY(data_in_dly_8),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D8[3]),\n .Q2(D8[2]),\n .Q3(D8[1]),\n .Q4(D8[0]),\n .Q5(\\NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[1].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[0]),\n .D2(of_dqbus[1]),\n .D3(of_dqbus[2]),\n .D4(of_dqbus[3]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[0]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[0]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[2].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[4]),\n .D2(of_dqbus[5]),\n .D3(of_dqbus[6]),\n .D4(of_dqbus[7]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[1]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[1]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[3].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[8]),\n .D2(of_dqbus[9]),\n .D3(of_dqbus[10]),\n .D4(of_dqbus[11]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[2]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[2]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[4].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[12]),\n .D2(of_dqbus[13]),\n .D3(of_dqbus[14]),\n .D4(of_dqbus[15]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[3]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[3]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[5].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[16]),\n .D2(of_dqbus[17]),\n .D3(of_dqbus[18]),\n .D4(of_dqbus[19]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[4]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[4]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[6].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[20]),\n .D2(of_dqbus[21]),\n .D3(of_dqbus[22]),\n .D4(of_dqbus[23]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[5]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[5]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[7].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[24]),\n .D2(of_dqbus[25]),\n .D3(of_dqbus[26]),\n .D4(of_dqbus[27]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[6]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[6]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[8].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[28]),\n .D2(of_dqbus[29]),\n .D3(of_dqbus[30]),\n .D4(of_dqbus[31]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[7]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[7]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[9].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[32]),\n .D2(of_dqbus[33]),\n .D3(of_dqbus[34]),\n .D4(of_dqbus[35]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[8]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[8]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"TRUE\"),\n .TRISTATE_WIDTH(4)) \n \\slave_ts.oserdes_slave_ts \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(1'b0),\n .D2(1'b0),\n .D3(1'b0),\n .D4(1'b0),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ),\n .OQ(\\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ),\n .T1(DTSBUS[0]),\n .T2(DTSBUS[0]),\n .T3(DTSBUS[1]),\n .T4(DTSBUS[1]),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(tbyte_out),\n .TCE(1'b1),\n .TFB(\\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ),\n .TQ(\\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_byte_group_io\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_byte_group_io__parameterized3\n (mem_dq_out,\n oserdes_clk,\n oserdes_clkdiv,\n oserdes_dq,\n oserdes_rst);\n output [1:0]mem_dq_out;\n input oserdes_clk;\n input oserdes_clkdiv;\n input [7:0]oserdes_dq;\n input oserdes_rst;\n\n wire [1:0]mem_dq_out;\n wire oserdes_clk;\n wire oserdes_clkdiv;\n wire [7:0]oserdes_dq;\n wire oserdes_rst;\n wire \\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[0].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[0]),\n .D2(oserdes_dq[1]),\n .D3(oserdes_dq[2]),\n .D4(oserdes_dq[3]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[0]),\n .RST(oserdes_rst),\n .SHIFTIN1(\\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[1].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[4]),\n .D2(oserdes_dq[5]),\n .D3(oserdes_dq[6]),\n .D4(oserdes_dq[7]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[1]),\n .RST(oserdes_rst),\n .SHIFTIN1(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_byte_group_io\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_byte_group_io__parameterized4\n (mem_dq_out,\n oserdes_clk,\n oserdes_clkdiv,\n oserdes_dq,\n oserdes_rst);\n output [2:0]mem_dq_out;\n input oserdes_clk;\n input oserdes_clkdiv;\n input [11:0]oserdes_dq;\n input oserdes_rst;\n\n wire [2:0]mem_dq_out;\n wire oserdes_clk;\n wire oserdes_clkdiv;\n wire [11:0]oserdes_dq;\n wire oserdes_rst;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[10].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[4]),\n .D2(oserdes_dq[5]),\n .D3(oserdes_dq[6]),\n .D4(oserdes_dq[7]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[1]),\n .RST(oserdes_rst),\n .SHIFTIN1(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[11].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[8]),\n .D2(oserdes_dq[9]),\n .D3(oserdes_dq[10]),\n .D4(oserdes_dq[11]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[2]),\n .RST(oserdes_rst),\n .SHIFTIN1(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[4].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[0]),\n .D2(oserdes_dq[1]),\n .D3(oserdes_dq[2]),\n .D4(oserdes_dq[3]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[0]),\n .RST(oserdes_rst),\n .SHIFTIN1(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_byte_group_io\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_byte_group_io__parameterized5\n (mem_dq_out,\n oserdes_clk,\n oserdes_clkdiv,\n oserdes_dq,\n po_oserdes_rst);\n output [9:0]mem_dq_out;\n input oserdes_clk;\n input oserdes_clkdiv;\n input [39:0]oserdes_dq;\n input po_oserdes_rst;\n\n wire [9:0]mem_dq_out;\n wire oserdes_clk;\n wire oserdes_clkdiv;\n wire [39:0]oserdes_dq;\n wire po_oserdes_rst;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[10].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[32]),\n .D2(oserdes_dq[33]),\n .D3(oserdes_dq[34]),\n .D4(oserdes_dq[35]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[8]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[11].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[36]),\n .D2(oserdes_dq[37]),\n .D3(oserdes_dq[38]),\n .D4(oserdes_dq[39]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[9]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[2].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[0]),\n .D2(oserdes_dq[1]),\n .D3(oserdes_dq[2]),\n .D4(oserdes_dq[3]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[0]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[3].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[4]),\n .D2(oserdes_dq[5]),\n .D3(oserdes_dq[6]),\n .D4(oserdes_dq[7]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[1]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[4].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[8]),\n .D2(oserdes_dq[9]),\n .D3(oserdes_dq[10]),\n .D4(oserdes_dq[11]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[2]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[5].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[12]),\n .D2(oserdes_dq[13]),\n .D3(oserdes_dq[14]),\n .D4(oserdes_dq[15]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[3]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[6].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[16]),\n .D2(oserdes_dq[17]),\n .D3(oserdes_dq[18]),\n .D4(oserdes_dq[19]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[4]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[7].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[20]),\n .D2(oserdes_dq[21]),\n .D3(oserdes_dq[22]),\n .D4(oserdes_dq[23]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[5]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[8].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[24]),\n .D2(oserdes_dq[25]),\n .D3(oserdes_dq[26]),\n .D4(oserdes_dq[27]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[6]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[9].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[28]),\n .D2(oserdes_dq[29]),\n .D3(oserdes_dq[30]),\n .D4(oserdes_dq[31]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[7]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_byte_group_io\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_byte_group_io__parameterized6\n (mem_dq_out,\n oserdes_clk,\n oserdes_clkdiv,\n oserdes_dq,\n po_oserdes_rst);\n output [8:0]mem_dq_out;\n input oserdes_clk;\n input oserdes_clkdiv;\n input [35:0]oserdes_dq;\n input po_oserdes_rst;\n\n wire [8:0]mem_dq_out;\n wire oserdes_clk;\n wire oserdes_clkdiv;\n wire [35:0]oserdes_dq;\n wire po_oserdes_rst;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[1].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[0]),\n .D2(oserdes_dq[1]),\n .D3(oserdes_dq[2]),\n .D4(oserdes_dq[3]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[0]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[2].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[4]),\n .D2(oserdes_dq[5]),\n .D3(oserdes_dq[6]),\n .D4(oserdes_dq[7]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[1]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[3].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[8]),\n .D2(oserdes_dq[9]),\n .D3(oserdes_dq[10]),\n .D4(oserdes_dq[11]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[2]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[4].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[12]),\n .D2(oserdes_dq[13]),\n .D3(oserdes_dq[14]),\n .D4(oserdes_dq[15]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[3]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[5].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[16]),\n .D2(oserdes_dq[17]),\n .D3(oserdes_dq[18]),\n .D4(oserdes_dq[19]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[4]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[6].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[20]),\n .D2(oserdes_dq[21]),\n .D3(oserdes_dq[22]),\n .D4(oserdes_dq[23]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[5]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[7].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[24]),\n .D2(oserdes_dq[25]),\n .D3(oserdes_dq[26]),\n .D4(oserdes_dq[27]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[6]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[8].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[28]),\n .D2(oserdes_dq[29]),\n .D3(oserdes_dq[30]),\n .D4(oserdes_dq[31]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[7]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[9].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[32]),\n .D2(oserdes_dq[33]),\n .D3(oserdes_dq[34]),\n .D4(oserdes_dq[35]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[8]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_byte_lane\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_byte_lane\n (\\pi_dqs_found_lanes_r1_reg[0] ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,\n pi_phase_locked_all_r1_reg,\n COUNTERREADVAL,\n \\po_counter_read_val_reg[8] ,\n mem_dqs_out,\n mem_dqs_ts,\n mem_dq_out,\n mem_dq_ts,\n if_empty_r,\n \\wr_ptr_reg[1] ,\n idelay_ld_rst,\n rst_r4,\n \\not_strict_mode.app_rd_data_reg[252] ,\n \\my_empty_reg[1] ,\n \\data_bytes_r_reg[63] ,\n \\not_strict_mode.app_rd_data_reg[255] ,\n \\not_strict_mode.app_rd_data_reg[254] ,\n \\not_strict_mode.app_rd_data_reg[253] ,\n \\not_strict_mode.app_rd_data_reg[252]_0 ,\n \\not_strict_mode.app_rd_data_reg[251] ,\n \\not_strict_mode.app_rd_data_reg[250] ,\n \\not_strict_mode.app_rd_data_reg[249] ,\n \\not_strict_mode.app_rd_data_reg[248] ,\n \\not_strict_mode.app_rd_data_reg[223] ,\n \\not_strict_mode.app_rd_data_reg[222] ,\n \\not_strict_mode.app_rd_data_reg[221] ,\n \\not_strict_mode.app_rd_data_reg[220] ,\n \\not_strict_mode.app_rd_data_reg[219] ,\n \\not_strict_mode.app_rd_data_reg[218] ,\n \\not_strict_mode.app_rd_data_reg[217] ,\n \\not_strict_mode.app_rd_data_reg[216] ,\n \\not_strict_mode.app_rd_data_reg[191] ,\n \\not_strict_mode.app_rd_data_reg[190] ,\n \\not_strict_mode.app_rd_data_reg[189] ,\n \\not_strict_mode.app_rd_data_reg[188] ,\n \\not_strict_mode.app_rd_data_reg[187] ,\n \\not_strict_mode.app_rd_data_reg[186] ,\n \\not_strict_mode.app_rd_data_reg[185] ,\n \\not_strict_mode.app_rd_data_reg[184] ,\n \\not_strict_mode.app_rd_data_reg[159] ,\n \\not_strict_mode.app_rd_data_reg[158] ,\n \\not_strict_mode.app_rd_data_reg[157] ,\n \\not_strict_mode.app_rd_data_reg[156] ,\n \\not_strict_mode.app_rd_data_reg[155] ,\n \\not_strict_mode.app_rd_data_reg[154] ,\n \\not_strict_mode.app_rd_data_reg[153] ,\n \\not_strict_mode.app_rd_data_reg[152] ,\n \\not_strict_mode.app_rd_data_reg[127] ,\n \\not_strict_mode.app_rd_data_reg[126] ,\n \\not_strict_mode.app_rd_data_reg[125] ,\n \\not_strict_mode.app_rd_data_reg[124] ,\n \\not_strict_mode.app_rd_data_reg[123] ,\n \\not_strict_mode.app_rd_data_reg[122] ,\n \\not_strict_mode.app_rd_data_reg[121] ,\n \\not_strict_mode.app_rd_data_reg[120] ,\n \\not_strict_mode.app_rd_data_reg[95] ,\n \\not_strict_mode.app_rd_data_reg[94] ,\n \\not_strict_mode.app_rd_data_reg[93] ,\n \\not_strict_mode.app_rd_data_reg[92] ,\n \\not_strict_mode.app_rd_data_reg[91] ,\n \\not_strict_mode.app_rd_data_reg[90] ,\n \\not_strict_mode.app_rd_data_reg[89] ,\n \\not_strict_mode.app_rd_data_reg[88] ,\n \\not_strict_mode.app_rd_data_reg[63] ,\n \\not_strict_mode.app_rd_data_reg[62] ,\n \\not_strict_mode.app_rd_data_reg[61] ,\n \\not_strict_mode.app_rd_data_reg[60] ,\n \\not_strict_mode.app_rd_data_reg[59] ,\n \\not_strict_mode.app_rd_data_reg[58] ,\n \\not_strict_mode.app_rd_data_reg[57] ,\n \\not_strict_mode.app_rd_data_reg[56] ,\n \\not_strict_mode.app_rd_data_reg[31] ,\n \\not_strict_mode.app_rd_data_reg[30] ,\n \\not_strict_mode.app_rd_data_reg[29] ,\n \\not_strict_mode.app_rd_data_reg[28] ,\n \\not_strict_mode.app_rd_data_reg[27] ,\n \\not_strict_mode.app_rd_data_reg[26] ,\n \\not_strict_mode.app_rd_data_reg[25] ,\n \\not_strict_mode.app_rd_data_reg[24] ,\n \\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,\n \\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,\n \\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,\n \\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,\n \\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,\n \\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,\n \\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,\n \\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,\n \\not_strict_mode.app_rd_data_reg[255]_0 ,\n \\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ,\n \\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ,\n \\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ,\n \\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ,\n \\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ,\n \\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ,\n \\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ,\n \\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ,\n \\not_strict_mode.app_rd_data_reg[31]_0 ,\n \\not_strict_mode.app_rd_data_reg[31]_1 ,\n \\my_empty_reg[7] ,\n A_byte_rd_en,\n p_0_out,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,\n \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,\n \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,\n \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,\n \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,\n Q,\n phaser_ctl_bus,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n \\calib_sel_reg[0] ,\n pi_en_stg2_f_reg,\n pi_stg2_f_incdec_reg,\n freq_refclk,\n mem_refclk,\n mem_dqs_in,\n A_rst_primitives,\n \\gen_byte_sel_div1.calib_in_common_reg_0 ,\n sync_pulse,\n CLK,\n PCENABLECALIB,\n COUNTERLOADVAL,\n \\gen_byte_sel_div1.calib_in_common_reg_1 ,\n ck_po_stg2_f_en_reg,\n ck_po_stg2_f_indec_reg,\n delay_done_r4_reg,\n \\write_buffer.wr_buf_out_data_reg[255] ,\n \\write_buffer.wr_buf_out_data_reg[254] ,\n \\write_buffer.wr_buf_out_data_reg[253] ,\n \\write_buffer.wr_buf_out_data_reg[252] ,\n \\write_buffer.wr_buf_out_data_reg[251] ,\n \\write_buffer.wr_buf_out_data_reg[250] ,\n \\write_buffer.wr_buf_out_data_reg[249] ,\n \\write_buffer.wr_buf_out_data_reg[248] ,\n \\gen_byte_sel_div1.calib_in_common_reg_2 ,\n mem_dq_in,\n idelay_inc,\n LD0,\n CLKB0,\n phy_if_reset,\n mux_wrdata_en,\n init_calib_complete_reg_rep,\n \\write_buffer.wr_buf_out_data_reg[287] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ,\n \\byte_r_reg[0] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ,\n \\byte_r_reg[1] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ,\n \\rd_mux_sel_r_reg[1] ,\n \\read_fifo.fifo_out_data_r_reg[6] ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,\n A,\n phy_dout,\n E,\n \\fine_delay_mod_reg[23] ,\n D_byte_rd_en,\n B_byte_rd_en,\n if_empty_r_0,\n my_empty,\n \\po_stg2_wrcal_cnt_reg[1] );\n output [0:0]\\pi_dqs_found_lanes_r1_reg[0] ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n output pi_phase_locked_all_r1_reg;\n output [5:0]COUNTERREADVAL;\n output [8:0]\\po_counter_read_val_reg[8] ;\n output [0:0]mem_dqs_out;\n output [0:0]mem_dqs_ts;\n output [8:0]mem_dq_out;\n output [8:0]mem_dq_ts;\n output [0:0]if_empty_r;\n output [0:0]\\wr_ptr_reg[1] ;\n output idelay_ld_rst;\n output rst_r4;\n output \\not_strict_mode.app_rd_data_reg[252] ;\n output \\my_empty_reg[1] ;\n output [63:0]\\data_bytes_r_reg[63] ;\n output \\not_strict_mode.app_rd_data_reg[255] ;\n output \\not_strict_mode.app_rd_data_reg[254] ;\n output \\not_strict_mode.app_rd_data_reg[253] ;\n output \\not_strict_mode.app_rd_data_reg[252]_0 ;\n output \\not_strict_mode.app_rd_data_reg[251] ;\n output \\not_strict_mode.app_rd_data_reg[250] ;\n output \\not_strict_mode.app_rd_data_reg[249] ;\n output \\not_strict_mode.app_rd_data_reg[248] ;\n output \\not_strict_mode.app_rd_data_reg[223] ;\n output \\not_strict_mode.app_rd_data_reg[222] ;\n output \\not_strict_mode.app_rd_data_reg[221] ;\n output \\not_strict_mode.app_rd_data_reg[220] ;\n output \\not_strict_mode.app_rd_data_reg[219] ;\n output \\not_strict_mode.app_rd_data_reg[218] ;\n output \\not_strict_mode.app_rd_data_reg[217] ;\n output \\not_strict_mode.app_rd_data_reg[216] ;\n output \\not_strict_mode.app_rd_data_reg[191] ;\n output \\not_strict_mode.app_rd_data_reg[190] ;\n output \\not_strict_mode.app_rd_data_reg[189] ;\n output \\not_strict_mode.app_rd_data_reg[188] ;\n output \\not_strict_mode.app_rd_data_reg[187] ;\n output \\not_strict_mode.app_rd_data_reg[186] ;\n output \\not_strict_mode.app_rd_data_reg[185] ;\n output \\not_strict_mode.app_rd_data_reg[184] ;\n output \\not_strict_mode.app_rd_data_reg[159] ;\n output \\not_strict_mode.app_rd_data_reg[158] ;\n output \\not_strict_mode.app_rd_data_reg[157] ;\n output \\not_strict_mode.app_rd_data_reg[156] ;\n output \\not_strict_mode.app_rd_data_reg[155] ;\n output \\not_strict_mode.app_rd_data_reg[154] ;\n output \\not_strict_mode.app_rd_data_reg[153] ;\n output \\not_strict_mode.app_rd_data_reg[152] ;\n output \\not_strict_mode.app_rd_data_reg[127] ;\n output \\not_strict_mode.app_rd_data_reg[126] ;\n output \\not_strict_mode.app_rd_data_reg[125] ;\n output \\not_strict_mode.app_rd_data_reg[124] ;\n output \\not_strict_mode.app_rd_data_reg[123] ;\n output \\not_strict_mode.app_rd_data_reg[122] ;\n output \\not_strict_mode.app_rd_data_reg[121] ;\n output \\not_strict_mode.app_rd_data_reg[120] ;\n output \\not_strict_mode.app_rd_data_reg[95] ;\n output \\not_strict_mode.app_rd_data_reg[94] ;\n output \\not_strict_mode.app_rd_data_reg[93] ;\n output \\not_strict_mode.app_rd_data_reg[92] ;\n output \\not_strict_mode.app_rd_data_reg[91] ;\n output \\not_strict_mode.app_rd_data_reg[90] ;\n output \\not_strict_mode.app_rd_data_reg[89] ;\n output \\not_strict_mode.app_rd_data_reg[88] ;\n output \\not_strict_mode.app_rd_data_reg[63] ;\n output \\not_strict_mode.app_rd_data_reg[62] ;\n output \\not_strict_mode.app_rd_data_reg[61] ;\n output \\not_strict_mode.app_rd_data_reg[60] ;\n output \\not_strict_mode.app_rd_data_reg[59] ;\n output \\not_strict_mode.app_rd_data_reg[58] ;\n output \\not_strict_mode.app_rd_data_reg[57] ;\n output \\not_strict_mode.app_rd_data_reg[56] ;\n output \\not_strict_mode.app_rd_data_reg[31] ;\n output \\not_strict_mode.app_rd_data_reg[30] ;\n output \\not_strict_mode.app_rd_data_reg[29] ;\n output \\not_strict_mode.app_rd_data_reg[28] ;\n output \\not_strict_mode.app_rd_data_reg[27] ;\n output \\not_strict_mode.app_rd_data_reg[26] ;\n output \\not_strict_mode.app_rd_data_reg[25] ;\n output \\not_strict_mode.app_rd_data_reg[24] ;\n output \\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n output \\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n output \\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n output \\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n output \\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n output \\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n output \\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n output \\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n output [63:0]\\not_strict_mode.app_rd_data_reg[255]_0 ;\n output \\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ;\n output \\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ;\n output \\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ;\n output \\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ;\n output \\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ;\n output \\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ;\n output \\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ;\n output \\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[31]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[31]_1 ;\n output [63:0]\\my_empty_reg[7] ;\n output A_byte_rd_en;\n output p_0_out;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n output \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n output \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n output \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n output \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n output [2:0]Q;\n input [3:0]phaser_ctl_bus;\n input \\gen_byte_sel_div1.calib_in_common_reg ;\n input \\calib_sel_reg[0] ;\n input pi_en_stg2_f_reg;\n input pi_stg2_f_incdec_reg;\n input freq_refclk;\n input mem_refclk;\n input [0:0]mem_dqs_in;\n input A_rst_primitives;\n input \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n input sync_pulse;\n input CLK;\n input [1:0]PCENABLECALIB;\n input [5:0]COUNTERLOADVAL;\n input \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n input ck_po_stg2_f_en_reg;\n input ck_po_stg2_f_indec_reg;\n input delay_done_r4_reg;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[255] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[254] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[253] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[252] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[251] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[250] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[249] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[248] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n input [7:0]mem_dq_in;\n input idelay_inc;\n input LD0;\n input CLKB0;\n input phy_if_reset;\n input mux_wrdata_en;\n input init_calib_complete_reg_rep;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[287] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;\n input \\byte_r_reg[0] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ;\n input \\byte_r_reg[1] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ;\n input [1:0]\\rd_mux_sel_r_reg[1] ;\n input \\read_fifo.fifo_out_data_r_reg[6] ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n input [1:0]A;\n input [71:0]phy_dout;\n input [0:0]E;\n input [7:0]\\fine_delay_mod_reg[23] ;\n input D_byte_rd_en;\n input B_byte_rd_en;\n input [0:0]if_empty_r_0;\n input [0:0]my_empty;\n input [1:0]\\po_stg2_wrcal_cnt_reg[1] ;\n\n wire [1:0]A;\n wire A_byte_rd_en;\n wire A_rst_primitives;\n wire B_byte_rd_en;\n wire CLK;\n wire CLKB0;\n wire [5:0]COUNTERLOADVAL;\n wire [5:0]COUNTERREADVAL;\n wire D_byte_rd_en;\n wire [0:0]E;\n wire LD0;\n wire [1:0]PCENABLECALIB;\n wire [2:0]Q;\n wire \\byte_r_reg[0] ;\n wire \\byte_r_reg[1] ;\n wire \\calib_sel_reg[0] ;\n wire ck_po_stg2_f_en_reg;\n wire ck_po_stg2_f_indec_reg;\n wire [63:0]\\data_bytes_r_reg[63] ;\n wire delay_done_r4_reg;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2 ;\n wire [7:0]\\fine_delay_mod_reg[23] ;\n wire freq_refclk;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n wire \\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n wire \\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n wire \\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n wire \\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;\n wire \\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n wire \\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n wire \\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n wire \\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ;\n wire idelay_inc;\n wire idelay_ld_rst;\n wire [3:0]if_d0;\n wire [3:0]if_d1;\n wire [3:0]if_d2;\n wire [3:0]if_d3;\n wire [3:0]if_d4;\n wire [3:0]if_d5;\n wire [3:0]if_d6;\n wire [3:0]if_d7;\n wire if_empty_;\n wire [0:0]if_empty_r;\n wire [0:0]if_empty_r_0;\n wire ififo_rst;\n wire ififo_wr_enable;\n wire \\in_fifo_gen.in_fifo_n_0 ;\n wire \\in_fifo_gen.in_fifo_n_1 ;\n wire \\in_fifo_gen.in_fifo_n_3 ;\n wire init_calib_complete_reg_rep;\n wire iserdes_clkdiv;\n wire [7:0]mem_dq_in;\n wire [8:0]mem_dq_out;\n wire [8:0]mem_dq_ts;\n wire [0:0]mem_dqs_in;\n wire [0:0]mem_dqs_out;\n wire [0:0]mem_dqs_ts;\n wire mem_refclk;\n wire mux_wrdata_en;\n wire [0:0]my_empty;\n wire \\my_empty_reg[1] ;\n wire [63:0]\\my_empty_reg[7] ;\n wire \\not_strict_mode.app_rd_data_reg[120] ;\n wire \\not_strict_mode.app_rd_data_reg[121] ;\n wire \\not_strict_mode.app_rd_data_reg[122] ;\n wire \\not_strict_mode.app_rd_data_reg[123] ;\n wire \\not_strict_mode.app_rd_data_reg[124] ;\n wire \\not_strict_mode.app_rd_data_reg[125] ;\n wire \\not_strict_mode.app_rd_data_reg[126] ;\n wire \\not_strict_mode.app_rd_data_reg[127] ;\n wire \\not_strict_mode.app_rd_data_reg[152] ;\n wire \\not_strict_mode.app_rd_data_reg[153] ;\n wire \\not_strict_mode.app_rd_data_reg[154] ;\n wire \\not_strict_mode.app_rd_data_reg[155] ;\n wire \\not_strict_mode.app_rd_data_reg[156] ;\n wire \\not_strict_mode.app_rd_data_reg[157] ;\n wire \\not_strict_mode.app_rd_data_reg[158] ;\n wire \\not_strict_mode.app_rd_data_reg[159] ;\n wire \\not_strict_mode.app_rd_data_reg[184] ;\n wire \\not_strict_mode.app_rd_data_reg[185] ;\n wire \\not_strict_mode.app_rd_data_reg[186] ;\n wire \\not_strict_mode.app_rd_data_reg[187] ;\n wire \\not_strict_mode.app_rd_data_reg[188] ;\n wire \\not_strict_mode.app_rd_data_reg[189] ;\n wire \\not_strict_mode.app_rd_data_reg[190] ;\n wire \\not_strict_mode.app_rd_data_reg[191] ;\n wire \\not_strict_mode.app_rd_data_reg[216] ;\n wire \\not_strict_mode.app_rd_data_reg[217] ;\n wire \\not_strict_mode.app_rd_data_reg[218] ;\n wire \\not_strict_mode.app_rd_data_reg[219] ;\n wire \\not_strict_mode.app_rd_data_reg[220] ;\n wire \\not_strict_mode.app_rd_data_reg[221] ;\n wire \\not_strict_mode.app_rd_data_reg[222] ;\n wire \\not_strict_mode.app_rd_data_reg[223] ;\n wire \\not_strict_mode.app_rd_data_reg[248] ;\n wire \\not_strict_mode.app_rd_data_reg[249] ;\n wire \\not_strict_mode.app_rd_data_reg[24] ;\n wire \\not_strict_mode.app_rd_data_reg[250] ;\n wire \\not_strict_mode.app_rd_data_reg[251] ;\n wire \\not_strict_mode.app_rd_data_reg[252] ;\n wire \\not_strict_mode.app_rd_data_reg[252]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[253] ;\n wire \\not_strict_mode.app_rd_data_reg[254] ;\n wire \\not_strict_mode.app_rd_data_reg[255] ;\n wire [63:0]\\not_strict_mode.app_rd_data_reg[255]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[25] ;\n wire \\not_strict_mode.app_rd_data_reg[26] ;\n wire \\not_strict_mode.app_rd_data_reg[27] ;\n wire \\not_strict_mode.app_rd_data_reg[28] ;\n wire \\not_strict_mode.app_rd_data_reg[29] ;\n wire \\not_strict_mode.app_rd_data_reg[30] ;\n wire \\not_strict_mode.app_rd_data_reg[31] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[31]_0 ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[31]_1 ;\n wire \\not_strict_mode.app_rd_data_reg[56] ;\n wire \\not_strict_mode.app_rd_data_reg[57] ;\n wire \\not_strict_mode.app_rd_data_reg[58] ;\n wire \\not_strict_mode.app_rd_data_reg[59] ;\n wire \\not_strict_mode.app_rd_data_reg[60] ;\n wire \\not_strict_mode.app_rd_data_reg[61] ;\n wire \\not_strict_mode.app_rd_data_reg[62] ;\n wire \\not_strict_mode.app_rd_data_reg[63] ;\n wire \\not_strict_mode.app_rd_data_reg[88] ;\n wire \\not_strict_mode.app_rd_data_reg[89] ;\n wire \\not_strict_mode.app_rd_data_reg[90] ;\n wire \\not_strict_mode.app_rd_data_reg[91] ;\n wire \\not_strict_mode.app_rd_data_reg[92] ;\n wire \\not_strict_mode.app_rd_data_reg[93] ;\n wire \\not_strict_mode.app_rd_data_reg[94] ;\n wire \\not_strict_mode.app_rd_data_reg[95] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n wire [7:0]of_d9;\n wire [39:0]of_dqbus;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ;\n wire ofifo_rst;\n wire oserdes_clk;\n wire oserdes_clk_delayed;\n wire oserdes_clkdiv;\n wire [1:0]oserdes_dq_ts;\n wire [1:0]oserdes_dqs;\n wire [1:0]oserdes_dqs_ts;\n wire out_fifo_n_0;\n wire out_fifo_n_1;\n wire out_fifo_n_2;\n wire out_fifo_n_3;\n wire p_0_out;\n wire [3:0]phaser_ctl_bus;\n wire \\phaser_in_gen.phaser_in_n_1 ;\n wire \\phaser_in_gen.phaser_in_n_2 ;\n wire \\phaser_in_gen.phaser_in_n_5 ;\n wire \\phaser_in_gen.phaser_in_n_7 ;\n wire phaser_out_n_0;\n wire phaser_out_n_1;\n wire [71:0]phy_dout;\n wire phy_if_reset;\n wire [0:0]\\pi_dqs_found_lanes_r1_reg[0] ;\n wire pi_en_stg2_f_reg;\n wire pi_phase_locked_all_r1_reg;\n wire pi_stg2_f_incdec_reg;\n wire [8:0]\\po_counter_read_val_reg[8] ;\n wire po_oserdes_rst;\n wire po_rd_enable;\n wire [1:0]\\po_stg2_wrcal_cnt_reg[1] ;\n wire [79:0]rd_data;\n wire [65:1]rd_data_r;\n wire [1:0]\\rd_mux_sel_r_reg[1] ;\n wire \\read_fifo.fifo_out_data_r_reg[6] ;\n wire rst_r4;\n wire sync_pulse;\n wire [0:0]\\wr_ptr_reg[1] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[248] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[249] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[250] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[251] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[252] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[253] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[254] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[255] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[287] ;\n wire [7:4]\\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED ;\n wire [7:4]\\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED ;\n wire [7:4]NLW_out_fifo_Q5_UNCONNECTED;\n wire [7:4]NLW_out_fifo_Q6_UNCONNECTED;\n wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;\n\n ddr3_ifmig_7series_v4_0_ddr_byte_group_io ddr_byte_group_io\n (.A_rst_primitives(A_rst_primitives),\n .A_rst_primitives_reg(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),\n .CLK(CLK),\n .CLKB0(CLKB0),\n .CTSBUS(oserdes_dqs_ts[0]),\n .D0(if_d0),\n .D1(if_d1),\n .D2(if_d2),\n .D3(if_d3),\n .D4(if_d4),\n .D5(if_d5),\n .D6(if_d6),\n .D7(if_d7),\n .DQSBUS(oserdes_dqs),\n .DTSBUS(oserdes_dq_ts),\n .E(E),\n .LD0(LD0),\n .\\fine_delay_mod_reg[23] (\\fine_delay_mod_reg[23] ),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\gen_byte_sel_div1.calib_in_common_reg_2 ),\n .idelay_inc(idelay_inc),\n .idelay_ld_rst(idelay_ld_rst),\n .iserdes_clkdiv(iserdes_clkdiv),\n .mem_dq_in(mem_dq_in),\n .mem_dq_out(mem_dq_out),\n .mem_dq_ts(mem_dq_ts),\n .mem_dqs_out(mem_dqs_out),\n .mem_dqs_ts(mem_dqs_ts),\n .of_dqbus({of_dqbus[39:36],of_dqbus[31:0]}),\n .oserdes_clk(oserdes_clk),\n .oserdes_clk_delayed(oserdes_clk_delayed),\n .oserdes_clkdiv(oserdes_clkdiv),\n .po_oserdes_rst(po_oserdes_rst),\n .rst_r4(rst_r4));\n (* syn_maxfan = \"3\" *) \n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(if_empty_),\n .Q(if_empty_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[0]),\n .Q(\\not_strict_mode.app_rd_data_reg[31]_0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[10]),\n .Q(rd_data_r[10]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[11]),\n .Q(rd_data_r[11]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[12]),\n .Q(rd_data_r[12]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[13]),\n .Q(rd_data_r[13]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[14]),\n .Q(rd_data_r[14]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[15]),\n .Q(rd_data_r[15]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[16]),\n .Q(rd_data_r[16]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[17]),\n .Q(rd_data_r[17]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[18]),\n .Q(rd_data_r[18]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[19]),\n .Q(rd_data_r[19]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[1]),\n .Q(rd_data_r[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[20]),\n .Q(rd_data_r[20]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[21]),\n .Q(rd_data_r[21]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[22]),\n .Q(rd_data_r[22]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[23]),\n .Q(rd_data_r[23]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[24]),\n .Q(rd_data_r[24]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[25]),\n .Q(rd_data_r[25]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[26]),\n .Q(rd_data_r[26]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[27]),\n .Q(rd_data_r[27]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[28]),\n .Q(rd_data_r[28]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[29]),\n .Q(rd_data_r[29]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[2]),\n .Q(rd_data_r[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[30]),\n .Q(rd_data_r[30]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[31]),\n .Q(rd_data_r[31]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[32]),\n .Q(rd_data_r[32]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[33]),\n .Q(rd_data_r[33]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[34]),\n .Q(rd_data_r[34]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[35]),\n .Q(rd_data_r[35]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[36]),\n .Q(rd_data_r[36]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[37]),\n .Q(rd_data_r[37]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[38]),\n .Q(rd_data_r[38]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[39]),\n .Q(rd_data_r[39]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[3]),\n .Q(rd_data_r[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[40]),\n .Q(rd_data_r[40]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[41]),\n .Q(rd_data_r[41]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[42]),\n .Q(rd_data_r[42]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[43]),\n .Q(rd_data_r[43]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[44]),\n .Q(rd_data_r[44]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[45]),\n .Q(rd_data_r[45]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[46]),\n .Q(rd_data_r[46]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[47]),\n .Q(rd_data_r[47]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[48]),\n .Q(rd_data_r[48]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[49]),\n .Q(rd_data_r[49]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[4]),\n .Q(rd_data_r[4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[50]),\n .Q(rd_data_r[50]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[51]),\n .Q(rd_data_r[51]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[52]),\n .Q(rd_data_r[52]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[53]),\n .Q(rd_data_r[53]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[54]),\n .Q(rd_data_r[54]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[55]),\n .Q(rd_data_r[55]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[56]),\n .Q(rd_data_r[56]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[57]),\n .Q(rd_data_r[57]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[58]),\n .Q(rd_data_r[58]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[59]),\n .Q(rd_data_r[59]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[5]),\n .Q(rd_data_r[5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[60]),\n .Q(rd_data_r[60]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[61]),\n .Q(rd_data_r[61]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[62]),\n .Q(rd_data_r[62]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[63]),\n .Q(rd_data_r[63]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[64]),\n .Q(rd_data_r[64]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[65]),\n .Q(rd_data_r[65]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[6]),\n .Q(rd_data_r[6]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[7]),\n .Q(rd_data_r[7]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[8]),\n .Q(rd_data_r[8]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[9]),\n .Q(rd_data_r[9]),\n .R(1'b0));\n ddr3_ifmig_7series_v4_0_ddr_if_post_fifo_6 \\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo \n (.A(A),\n .A_byte_rd_en(A_byte_rd_en),\n .B_byte_rd_en(B_byte_rd_en),\n .CLK(CLK),\n .D_byte_rd_en(D_byte_rd_en),\n .Q({rd_data_r,\\not_strict_mode.app_rd_data_reg[31]_0 }),\n .\\byte_r_reg[0] (\\byte_r_reg[0] ),\n .\\byte_r_reg[1] (\\byte_r_reg[1] ),\n .\\data_bytes_r_reg[63] (\\data_bytes_r_reg[63] ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (if_empty_r),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2 ),\n .\\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] (\\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] (\\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] (\\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] (\\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] (\\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] (\\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] (\\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] (\\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),\n .\\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] (\\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] (\\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] (\\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] (\\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] (\\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] (\\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] (\\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] (\\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),\n .\\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] (\\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] (\\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] (\\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] (\\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] (\\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] (\\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] (\\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] (\\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),\n .\\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] (\\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] (\\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] (\\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] (\\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] (\\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] (\\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] (\\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] (\\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),\n .\\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] (\\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] (\\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] (\\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] (\\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] (\\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] (\\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] (\\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] (\\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),\n .\\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] (\\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] (\\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] (\\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] (\\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] (\\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] (\\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] (\\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] (\\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),\n .\\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] (\\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] (\\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] (\\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] (\\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] (\\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] (\\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] (\\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] (\\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),\n .\\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] (\\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] (\\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] (\\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] (\\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] (\\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] (\\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] (\\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] (\\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),\n .\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] (\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ),\n .\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] (\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ),\n .\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] (\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ),\n .\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] (\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ),\n .if_empty_r_0(if_empty_r_0),\n .ififo_rst(ififo_rst),\n .my_empty(my_empty),\n .\\not_strict_mode.app_rd_data_reg[120] (\\not_strict_mode.app_rd_data_reg[120] ),\n .\\not_strict_mode.app_rd_data_reg[121] (\\not_strict_mode.app_rd_data_reg[121] ),\n .\\not_strict_mode.app_rd_data_reg[122] (\\not_strict_mode.app_rd_data_reg[122] ),\n .\\not_strict_mode.app_rd_data_reg[123] (\\not_strict_mode.app_rd_data_reg[123] ),\n .\\not_strict_mode.app_rd_data_reg[124] (\\not_strict_mode.app_rd_data_reg[124] ),\n .\\not_strict_mode.app_rd_data_reg[125] (\\not_strict_mode.app_rd_data_reg[125] ),\n .\\not_strict_mode.app_rd_data_reg[126] (\\not_strict_mode.app_rd_data_reg[126] ),\n .\\not_strict_mode.app_rd_data_reg[127] (\\not_strict_mode.app_rd_data_reg[127] ),\n .\\not_strict_mode.app_rd_data_reg[152] (\\not_strict_mode.app_rd_data_reg[152] ),\n .\\not_strict_mode.app_rd_data_reg[153] (\\not_strict_mode.app_rd_data_reg[153] ),\n .\\not_strict_mode.app_rd_data_reg[154] (\\not_strict_mode.app_rd_data_reg[154] ),\n .\\not_strict_mode.app_rd_data_reg[155] (\\not_strict_mode.app_rd_data_reg[155] ),\n .\\not_strict_mode.app_rd_data_reg[156] (\\not_strict_mode.app_rd_data_reg[156] ),\n .\\not_strict_mode.app_rd_data_reg[157] (\\not_strict_mode.app_rd_data_reg[157] ),\n .\\not_strict_mode.app_rd_data_reg[158] (\\not_strict_mode.app_rd_data_reg[158] ),\n .\\not_strict_mode.app_rd_data_reg[159] (\\not_strict_mode.app_rd_data_reg[159] ),\n .\\not_strict_mode.app_rd_data_reg[184] (\\not_strict_mode.app_rd_data_reg[184] ),\n .\\not_strict_mode.app_rd_data_reg[185] (\\not_strict_mode.app_rd_data_reg[185] ),\n .\\not_strict_mode.app_rd_data_reg[186] (\\not_strict_mode.app_rd_data_reg[186] ),\n .\\not_strict_mode.app_rd_data_reg[187] (\\not_strict_mode.app_rd_data_reg[187] ),\n .\\not_strict_mode.app_rd_data_reg[188] (\\not_strict_mode.app_rd_data_reg[188] ),\n .\\not_strict_mode.app_rd_data_reg[189] (\\not_strict_mode.app_rd_data_reg[189] ),\n .\\not_strict_mode.app_rd_data_reg[190] (\\not_strict_mode.app_rd_data_reg[190] ),\n .\\not_strict_mode.app_rd_data_reg[191] (\\not_strict_mode.app_rd_data_reg[191] ),\n .\\not_strict_mode.app_rd_data_reg[216] (\\not_strict_mode.app_rd_data_reg[216] ),\n .\\not_strict_mode.app_rd_data_reg[217] (\\not_strict_mode.app_rd_data_reg[217] ),\n .\\not_strict_mode.app_rd_data_reg[218] (\\not_strict_mode.app_rd_data_reg[218] ),\n .\\not_strict_mode.app_rd_data_reg[219] (\\not_strict_mode.app_rd_data_reg[219] ),\n .\\not_strict_mode.app_rd_data_reg[220] (\\not_strict_mode.app_rd_data_reg[220] ),\n .\\not_strict_mode.app_rd_data_reg[221] (\\not_strict_mode.app_rd_data_reg[221] ),\n .\\not_strict_mode.app_rd_data_reg[222] (\\not_strict_mode.app_rd_data_reg[222] ),\n .\\not_strict_mode.app_rd_data_reg[223] (\\not_strict_mode.app_rd_data_reg[223] ),\n .\\not_strict_mode.app_rd_data_reg[248] (\\not_strict_mode.app_rd_data_reg[248] ),\n .\\not_strict_mode.app_rd_data_reg[249] (\\not_strict_mode.app_rd_data_reg[249] ),\n .\\not_strict_mode.app_rd_data_reg[24] (\\not_strict_mode.app_rd_data_reg[24] ),\n .\\not_strict_mode.app_rd_data_reg[250] (\\not_strict_mode.app_rd_data_reg[250] ),\n .\\not_strict_mode.app_rd_data_reg[251] (\\not_strict_mode.app_rd_data_reg[251] ),\n .\\not_strict_mode.app_rd_data_reg[252] (\\not_strict_mode.app_rd_data_reg[252] ),\n .\\not_strict_mode.app_rd_data_reg[252]_0 (\\not_strict_mode.app_rd_data_reg[252]_0 ),\n .\\not_strict_mode.app_rd_data_reg[253] (\\not_strict_mode.app_rd_data_reg[253] ),\n .\\not_strict_mode.app_rd_data_reg[254] (\\not_strict_mode.app_rd_data_reg[254] ),\n .\\not_strict_mode.app_rd_data_reg[255] (\\not_strict_mode.app_rd_data_reg[255] ),\n .\\not_strict_mode.app_rd_data_reg[255]_0 (\\not_strict_mode.app_rd_data_reg[255]_0 ),\n .\\not_strict_mode.app_rd_data_reg[25] (\\not_strict_mode.app_rd_data_reg[25] ),\n .\\not_strict_mode.app_rd_data_reg[26] (\\not_strict_mode.app_rd_data_reg[26] ),\n .\\not_strict_mode.app_rd_data_reg[27] (\\not_strict_mode.app_rd_data_reg[27] ),\n .\\not_strict_mode.app_rd_data_reg[28] (\\not_strict_mode.app_rd_data_reg[28] ),\n .\\not_strict_mode.app_rd_data_reg[29] (\\not_strict_mode.app_rd_data_reg[29] ),\n .\\not_strict_mode.app_rd_data_reg[30] (\\not_strict_mode.app_rd_data_reg[30] ),\n .\\not_strict_mode.app_rd_data_reg[31] (\\not_strict_mode.app_rd_data_reg[31] ),\n .\\not_strict_mode.app_rd_data_reg[31]_0 (\\not_strict_mode.app_rd_data_reg[31]_1 ),\n .\\not_strict_mode.app_rd_data_reg[56] (\\not_strict_mode.app_rd_data_reg[56] ),\n .\\not_strict_mode.app_rd_data_reg[57] (\\not_strict_mode.app_rd_data_reg[57] ),\n .\\not_strict_mode.app_rd_data_reg[58] (\\not_strict_mode.app_rd_data_reg[58] ),\n .\\not_strict_mode.app_rd_data_reg[59] (\\not_strict_mode.app_rd_data_reg[59] ),\n .\\not_strict_mode.app_rd_data_reg[60] (\\not_strict_mode.app_rd_data_reg[60] ),\n .\\not_strict_mode.app_rd_data_reg[61] (\\not_strict_mode.app_rd_data_reg[61] ),\n .\\not_strict_mode.app_rd_data_reg[62] (\\not_strict_mode.app_rd_data_reg[62] ),\n .\\not_strict_mode.app_rd_data_reg[63] (\\not_strict_mode.app_rd_data_reg[63] ),\n .\\not_strict_mode.app_rd_data_reg[88] (\\not_strict_mode.app_rd_data_reg[88] ),\n .\\not_strict_mode.app_rd_data_reg[89] (\\not_strict_mode.app_rd_data_reg[89] ),\n .\\not_strict_mode.app_rd_data_reg[90] (\\not_strict_mode.app_rd_data_reg[90] ),\n .\\not_strict_mode.app_rd_data_reg[91] (\\not_strict_mode.app_rd_data_reg[91] ),\n .\\not_strict_mode.app_rd_data_reg[92] (\\not_strict_mode.app_rd_data_reg[92] ),\n .\\not_strict_mode.app_rd_data_reg[93] (\\not_strict_mode.app_rd_data_reg[93] ),\n .\\not_strict_mode.app_rd_data_reg[94] (\\not_strict_mode.app_rd_data_reg[94] ),\n .\\not_strict_mode.app_rd_data_reg[95] (\\not_strict_mode.app_rd_data_reg[95] ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ),\n .p_0_out(p_0_out),\n .\\po_stg2_wrcal_cnt_reg[1] (\\po_stg2_wrcal_cnt_reg[1] ),\n .\\rd_mux_sel_r_reg[1] (\\rd_mux_sel_r_reg[1] ),\n .\\read_fifo.fifo_out_data_r_reg[6] (\\read_fifo.fifo_out_data_r_reg[6] ),\n .\\wr_ptr_reg[1]_0 (\\wr_ptr_reg[1] ));\n FDSE #(\n .INIT(1'b1)) \n ififo_rst_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .Q(ififo_rst),\n .S(phy_if_reset));\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n IN_FIFO #(\n .ALMOST_EMPTY_VALUE(1),\n .ALMOST_FULL_VALUE(1),\n .ARRAY_MODE(\"ARRAY_MODE_4_X_8\"),\n .SYNCHRONOUS_MODE(\"FALSE\")) \n \\in_fifo_gen.in_fifo \n (.ALMOSTEMPTY(\\in_fifo_gen.in_fifo_n_0 ),\n .ALMOSTFULL(\\in_fifo_gen.in_fifo_n_1 ),\n .D0(if_d0),\n .D1(if_d1),\n .D2(if_d2),\n .D3(if_d3),\n .D4(if_d4),\n .D5({\\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED [7:4],if_d5}),\n .D6({\\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED [7:4],if_d6}),\n .D7(if_d7),\n .D8({1'b0,1'b0,1'b0,1'b0}),\n .D9({1'b0,1'b0,1'b0,1'b0}),\n .EMPTY(if_empty_),\n .FULL(\\in_fifo_gen.in_fifo_n_3 ),\n .Q0(rd_data[7:0]),\n .Q1(rd_data[15:8]),\n .Q2(rd_data[23:16]),\n .Q3(rd_data[31:24]),\n .Q4(rd_data[39:32]),\n .Q5(rd_data[47:40]),\n .Q6(rd_data[55:48]),\n .Q7(rd_data[63:56]),\n .Q8(rd_data[71:64]),\n .Q9(rd_data[79:72]),\n .RDCLK(CLK),\n .RDEN(1'b1),\n .RESET(ififo_rst),\n .WRCLK(iserdes_clkdiv),\n .WREN(ififo_wr_enable));\n ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized2 \\of_pre_fifo_gen.u_ddr_of_pre_fifo \n (.CLK(CLK),\n .D8({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }),\n .D9(of_d9),\n .Q(Q),\n .init_calib_complete_reg_rep(init_calib_complete_reg_rep),\n .mux_wrdata_en(mux_wrdata_en),\n .\\my_empty_reg[1]_0 (\\my_empty_reg[1] ),\n .\\my_empty_reg[7]_0 (\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ),\n .\\my_empty_reg[7]_1 (\\my_empty_reg[7] ),\n .ofifo_rst(ofifo_rst),\n .ofifo_rst_reg(out_fifo_n_3),\n .phy_dout(phy_dout),\n .\\write_buffer.wr_buf_out_data_reg[287] (\\write_buffer.wr_buf_out_data_reg[287] ));\n FDSE #(\n .INIT(1'b1)) \n ofifo_rst_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .Q(ofifo_rst),\n .S(A_rst_primitives));\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n OUT_FIFO #(\n .ALMOST_EMPTY_VALUE(1),\n .ALMOST_FULL_VALUE(1),\n .ARRAY_MODE(\"ARRAY_MODE_8_X_4\"),\n .OUTPUT_DISABLE(\"FALSE\"),\n .SYNCHRONOUS_MODE(\"FALSE\")) \n out_fifo\n (.ALMOSTEMPTY(out_fifo_n_0),\n .ALMOSTFULL(out_fifo_n_1),\n .D0(\\write_buffer.wr_buf_out_data_reg[255] ),\n .D1(\\write_buffer.wr_buf_out_data_reg[254] ),\n .D2(\\write_buffer.wr_buf_out_data_reg[253] ),\n .D3(\\write_buffer.wr_buf_out_data_reg[252] ),\n .D4(\\write_buffer.wr_buf_out_data_reg[251] ),\n .D5(\\write_buffer.wr_buf_out_data_reg[250] ),\n .D6(\\write_buffer.wr_buf_out_data_reg[249] ),\n .D7(\\write_buffer.wr_buf_out_data_reg[248] ),\n .D8({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }),\n .D9(of_d9),\n .EMPTY(out_fifo_n_2),\n .FULL(out_fifo_n_3),\n .Q0(of_dqbus[3:0]),\n .Q1(of_dqbus[7:4]),\n .Q2(of_dqbus[11:8]),\n .Q3(of_dqbus[15:12]),\n .Q4(of_dqbus[19:16]),\n .Q5({NLW_out_fifo_Q5_UNCONNECTED[7:4],of_dqbus[23:20]}),\n .Q6({NLW_out_fifo_Q6_UNCONNECTED[7:4],of_dqbus[27:24]}),\n .Q7(of_dqbus[31:28]),\n .Q8(of_dqbus[35:32]),\n .Q9(of_dqbus[39:36]),\n .RDCLK(oserdes_clkdiv),\n .RDEN(po_rd_enable),\n .RESET(ofifo_rst),\n .WRCLK(CLK),\n .WREN(\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ));\n (* box_type = \"PRIMITIVE\" *) \n PHASER_IN_PHY #(\n .BURST_MODE(\"TRUE\"),\n .CLKOUT_DIV(2),\n .DQS_AUTO_RECAL(1'b1),\n .DQS_BIAS_MODE(\"FALSE\"),\n .DQS_FIND_PATTERN(3'b000),\n .FINE_DELAY(33),\n .FREQ_REF_DIV(\"NONE\"),\n .IS_RST_INVERTED(1'b0),\n .MEMREFCLK_PERIOD(1.112000),\n .OUTPUT_CLK_SRC(\"DELAYED_REF\"),\n .PHASEREFCLK_PERIOD(1.112000),\n .REFCLK_PERIOD(1.112000),\n .SEL_CLK_OFFSET(6),\n .SYNC_IN_DIV_RST(\"TRUE\"),\n .WR_CYCLES(\"FALSE\")) \n \\phaser_in_gen.phaser_in \n (.BURSTPENDINGPHY(phaser_ctl_bus[1]),\n .COUNTERLOADEN(\\gen_byte_sel_div1.calib_in_common_reg ),\n .COUNTERLOADVAL(COUNTERLOADVAL),\n .COUNTERREADEN(\\calib_sel_reg[0] ),\n .COUNTERREADVAL(COUNTERREADVAL),\n .DQSFOUND(\\pi_dqs_found_lanes_r1_reg[0] ),\n .DQSOUTOFRANGE(\\phaser_in_gen.phaser_in_n_1 ),\n .ENCALIBPHY(PCENABLECALIB),\n .FINEENABLE(pi_en_stg2_f_reg),\n .FINEINC(pi_stg2_f_incdec_reg),\n .FINEOVERFLOW(\\phaser_in_gen.phaser_in_n_2 ),\n .FREQREFCLK(freq_refclk),\n .ICLK(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),\n .ICLKDIV(iserdes_clkdiv),\n .ISERDESRST(\\phaser_in_gen.phaser_in_n_5 ),\n .MEMREFCLK(mem_refclk),\n .PHASELOCKED(pi_phase_locked_all_r1_reg),\n .PHASEREFCLK(mem_dqs_in),\n .RANKSELPHY(phaser_ctl_bus[3:2]),\n .RCLK(\\phaser_in_gen.phaser_in_n_7 ),\n .RST(A_rst_primitives),\n .RSTDQSFIND(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .SYNCIN(sync_pulse),\n .SYSCLK(CLK),\n .WRENABLE(ififo_wr_enable));\n (* box_type = \"PRIMITIVE\" *) \n PHASER_OUT_PHY #(\n .CLKOUT_DIV(2),\n .COARSE_BYPASS(\"FALSE\"),\n .COARSE_DELAY(0),\n .DATA_CTL_N(\"TRUE\"),\n .DATA_RD_CYCLES(\"FALSE\"),\n .FINE_DELAY(60),\n .IS_RST_INVERTED(1'b0),\n .MEMREFCLK_PERIOD(1.111111),\n .OCLKDELAY_INV(\"TRUE\"),\n .OCLK_DELAY(28),\n .OUTPUT_CLK_SRC(\"DELAYED_REF\"),\n .PHASEREFCLK_PERIOD(1.000000),\n .PO(3'b111),\n .REFCLK_PERIOD(1.112000),\n .SYNC_IN_DIV_RST(\"TRUE\")) \n phaser_out\n (.BURSTPENDINGPHY(phaser_ctl_bus[0]),\n .COARSEENABLE(\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .COARSEINC(\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .COARSEOVERFLOW(phaser_out_n_0),\n .COUNTERLOADEN(1'b0),\n .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .COUNTERREADEN(\\calib_sel_reg[0] ),\n .COUNTERREADVAL(\\po_counter_read_val_reg[8] ),\n .CTSBUS(oserdes_dqs_ts),\n .DQSBUS(oserdes_dqs),\n .DTSBUS(oserdes_dq_ts),\n .ENCALIBPHY(PCENABLECALIB),\n .FINEENABLE(ck_po_stg2_f_en_reg),\n .FINEINC(ck_po_stg2_f_indec_reg),\n .FINEOVERFLOW(phaser_out_n_1),\n .FREQREFCLK(freq_refclk),\n .MEMREFCLK(mem_refclk),\n .OCLK(oserdes_clk),\n .OCLKDELAYED(oserdes_clk_delayed),\n .OCLKDIV(oserdes_clkdiv),\n .OSERDESRST(po_oserdes_rst),\n .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),\n .RDENABLE(po_rd_enable),\n .RST(A_rst_primitives),\n .SELFINEOCLKDELAY(delay_done_r4_reg),\n .SYNCIN(sync_pulse),\n .SYSCLK(CLK));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_byte_lane\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_byte_lane__parameterized0\n (\\pi_dqs_found_lanes_r1_reg[1] ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,\n B_rclk,\n COUNTERREADVAL,\n \\po_counter_read_val_reg[8] ,\n mem_dqs_out,\n mem_dqs_ts,\n mem_dq_out,\n mem_dq_ts,\n if_empty_r,\n \\rd_ptr_timing_reg[1] ,\n idelay_ld_rst_0,\n \\not_strict_mode.app_rd_data_reg[244] ,\n \\my_empty_reg[1] ,\n rd_buf_we,\n \\not_strict_mode.status_ram.rd_buf_we_r1_reg ,\n phy_rddata_en,\n mux_rd_valid_r_reg,\n \\read_fifo.tail_r_reg[0] ,\n \\not_strict_mode.app_rd_data_reg[247] ,\n \\not_strict_mode.app_rd_data_reg[16] ,\n \\not_strict_mode.app_rd_data_reg[17] ,\n \\not_strict_mode.app_rd_data_reg[18] ,\n \\not_strict_mode.app_rd_data_reg[19] ,\n \\not_strict_mode.app_rd_data_reg[20] ,\n \\not_strict_mode.app_rd_data_reg[21] ,\n \\not_strict_mode.app_rd_data_reg[22] ,\n \\not_strict_mode.app_rd_data_reg[23] ,\n \\not_strict_mode.app_rd_data_reg[48] ,\n \\not_strict_mode.app_rd_data_reg[49] ,\n \\not_strict_mode.app_rd_data_reg[50] ,\n \\not_strict_mode.app_rd_data_reg[51] ,\n \\not_strict_mode.app_rd_data_reg[52] ,\n \\not_strict_mode.app_rd_data_reg[53] ,\n \\not_strict_mode.app_rd_data_reg[54] ,\n \\not_strict_mode.app_rd_data_reg[55] ,\n \\not_strict_mode.app_rd_data_reg[80] ,\n \\not_strict_mode.app_rd_data_reg[81] ,\n \\not_strict_mode.app_rd_data_reg[82] ,\n \\not_strict_mode.app_rd_data_reg[83] ,\n \\not_strict_mode.app_rd_data_reg[84] ,\n \\not_strict_mode.app_rd_data_reg[85] ,\n \\not_strict_mode.app_rd_data_reg[86] ,\n \\not_strict_mode.app_rd_data_reg[87] ,\n \\not_strict_mode.app_rd_data_reg[112] ,\n \\not_strict_mode.app_rd_data_reg[113] ,\n \\not_strict_mode.app_rd_data_reg[114] ,\n \\not_strict_mode.app_rd_data_reg[115] ,\n \\not_strict_mode.app_rd_data_reg[116] ,\n \\not_strict_mode.app_rd_data_reg[117] ,\n \\not_strict_mode.app_rd_data_reg[118] ,\n \\not_strict_mode.app_rd_data_reg[119] ,\n \\not_strict_mode.app_rd_data_reg[144] ,\n \\not_strict_mode.app_rd_data_reg[145] ,\n \\not_strict_mode.app_rd_data_reg[146] ,\n \\not_strict_mode.app_rd_data_reg[147] ,\n \\not_strict_mode.app_rd_data_reg[148] ,\n \\not_strict_mode.app_rd_data_reg[149] ,\n \\not_strict_mode.app_rd_data_reg[150] ,\n \\not_strict_mode.app_rd_data_reg[151] ,\n \\not_strict_mode.app_rd_data_reg[176] ,\n \\not_strict_mode.app_rd_data_reg[177] ,\n \\not_strict_mode.app_rd_data_reg[178] ,\n \\not_strict_mode.app_rd_data_reg[179] ,\n \\not_strict_mode.app_rd_data_reg[180] ,\n \\not_strict_mode.app_rd_data_reg[181] ,\n \\not_strict_mode.app_rd_data_reg[182] ,\n \\not_strict_mode.app_rd_data_reg[183] ,\n \\not_strict_mode.app_rd_data_reg[208] ,\n \\not_strict_mode.app_rd_data_reg[209] ,\n \\not_strict_mode.app_rd_data_reg[210] ,\n \\not_strict_mode.app_rd_data_reg[211] ,\n \\not_strict_mode.app_rd_data_reg[212] ,\n \\not_strict_mode.app_rd_data_reg[213] ,\n \\not_strict_mode.app_rd_data_reg[214] ,\n \\not_strict_mode.app_rd_data_reg[215] ,\n \\not_strict_mode.app_rd_data_reg[240] ,\n \\not_strict_mode.app_rd_data_reg[241] ,\n \\not_strict_mode.app_rd_data_reg[242] ,\n \\not_strict_mode.app_rd_data_reg[243] ,\n \\not_strict_mode.app_rd_data_reg[244]_0 ,\n \\not_strict_mode.app_rd_data_reg[245] ,\n \\not_strict_mode.app_rd_data_reg[246] ,\n \\not_strict_mode.app_rd_data_reg[247]_0 ,\n pi_phase_locked_all_r1_reg,\n phy_if_empty_r_reg,\n \\not_strict_mode.app_rd_data_reg[23]_0 ,\n \\not_strict_mode.app_rd_data_reg[23]_1 ,\n \\my_empty_reg[7] ,\n B_byte_rd_en,\n Q,\n phaser_ctl_bus,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n \\calib_sel_reg[0] ,\n pi_en_stg2_f_reg,\n pi_stg2_f_incdec_reg,\n freq_refclk,\n mem_refclk,\n mem_dqs_in,\n A_rst_primitives,\n \\gen_byte_sel_div1.calib_in_common_reg_0 ,\n sync_pulse,\n CLK,\n PCENABLECALIB,\n \\calib_zero_inputs_reg[0] ,\n \\gen_byte_sel_div1.calib_in_common_reg_1 ,\n ck_po_stg2_f_en_reg,\n ck_po_stg2_f_indec_reg,\n delay_done_r4_reg,\n \\write_buffer.wr_buf_out_data_reg[247] ,\n \\write_buffer.wr_buf_out_data_reg[246] ,\n \\write_buffer.wr_buf_out_data_reg[245] ,\n \\write_buffer.wr_buf_out_data_reg[244] ,\n \\write_buffer.wr_buf_out_data_reg[243] ,\n \\write_buffer.wr_buf_out_data_reg[242] ,\n \\write_buffer.wr_buf_out_data_reg[241] ,\n \\write_buffer.wr_buf_out_data_reg[240] ,\n \\gen_byte_sel_div1.calib_in_common_reg_2 ,\n mem_dq_in,\n idelay_inc,\n LD0_3,\n CLKB0_7,\n phy_if_reset,\n mux_wrdata_en,\n rst_r4,\n \\read_fifo.fifo_out_data_r_reg[6] ,\n ram_init_done_r,\n init_calib_complete_reg_rep,\n \\write_buffer.wr_buf_out_data_reg[286] ,\n if_empty_r_0,\n my_empty,\n \\my_empty_reg[4] ,\n prbs_rdlvl_start_reg,\n out,\n tail_r,\n \\read_fifo.fifo_out_data_r_reg[6]_0 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,\n A_rst_primitives_reg,\n A_rst_primitives_reg_0,\n A_rst_primitives_reg_1,\n phy_dout,\n \\gen_byte_sel_div1.calib_in_common_reg_3 ,\n \\calib_sel_reg[0]_0 ,\n D_byte_rd_en,\n A_byte_rd_en);\n output [0:0]\\pi_dqs_found_lanes_r1_reg[1] ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n output B_rclk;\n output [5:0]COUNTERREADVAL;\n output [8:0]\\po_counter_read_val_reg[8] ;\n output [0:0]mem_dqs_out;\n output [0:0]mem_dqs_ts;\n output [8:0]mem_dq_out;\n output [8:0]mem_dq_ts;\n output [0:0]if_empty_r;\n output [0:0]\\rd_ptr_timing_reg[1] ;\n output idelay_ld_rst_0;\n output \\not_strict_mode.app_rd_data_reg[244] ;\n output \\my_empty_reg[1] ;\n output rd_buf_we;\n output \\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n output phy_rddata_en;\n output mux_rd_valid_r_reg;\n output \\read_fifo.tail_r_reg[0] ;\n output [63:0]\\not_strict_mode.app_rd_data_reg[247] ;\n output \\not_strict_mode.app_rd_data_reg[16] ;\n output \\not_strict_mode.app_rd_data_reg[17] ;\n output \\not_strict_mode.app_rd_data_reg[18] ;\n output \\not_strict_mode.app_rd_data_reg[19] ;\n output \\not_strict_mode.app_rd_data_reg[20] ;\n output \\not_strict_mode.app_rd_data_reg[21] ;\n output \\not_strict_mode.app_rd_data_reg[22] ;\n output \\not_strict_mode.app_rd_data_reg[23] ;\n output \\not_strict_mode.app_rd_data_reg[48] ;\n output \\not_strict_mode.app_rd_data_reg[49] ;\n output \\not_strict_mode.app_rd_data_reg[50] ;\n output \\not_strict_mode.app_rd_data_reg[51] ;\n output \\not_strict_mode.app_rd_data_reg[52] ;\n output \\not_strict_mode.app_rd_data_reg[53] ;\n output \\not_strict_mode.app_rd_data_reg[54] ;\n output \\not_strict_mode.app_rd_data_reg[55] ;\n output \\not_strict_mode.app_rd_data_reg[80] ;\n output \\not_strict_mode.app_rd_data_reg[81] ;\n output \\not_strict_mode.app_rd_data_reg[82] ;\n output \\not_strict_mode.app_rd_data_reg[83] ;\n output \\not_strict_mode.app_rd_data_reg[84] ;\n output \\not_strict_mode.app_rd_data_reg[85] ;\n output \\not_strict_mode.app_rd_data_reg[86] ;\n output \\not_strict_mode.app_rd_data_reg[87] ;\n output \\not_strict_mode.app_rd_data_reg[112] ;\n output \\not_strict_mode.app_rd_data_reg[113] ;\n output \\not_strict_mode.app_rd_data_reg[114] ;\n output \\not_strict_mode.app_rd_data_reg[115] ;\n output \\not_strict_mode.app_rd_data_reg[116] ;\n output \\not_strict_mode.app_rd_data_reg[117] ;\n output \\not_strict_mode.app_rd_data_reg[118] ;\n output \\not_strict_mode.app_rd_data_reg[119] ;\n output \\not_strict_mode.app_rd_data_reg[144] ;\n output \\not_strict_mode.app_rd_data_reg[145] ;\n output \\not_strict_mode.app_rd_data_reg[146] ;\n output \\not_strict_mode.app_rd_data_reg[147] ;\n output \\not_strict_mode.app_rd_data_reg[148] ;\n output \\not_strict_mode.app_rd_data_reg[149] ;\n output \\not_strict_mode.app_rd_data_reg[150] ;\n output \\not_strict_mode.app_rd_data_reg[151] ;\n output \\not_strict_mode.app_rd_data_reg[176] ;\n output \\not_strict_mode.app_rd_data_reg[177] ;\n output \\not_strict_mode.app_rd_data_reg[178] ;\n output \\not_strict_mode.app_rd_data_reg[179] ;\n output \\not_strict_mode.app_rd_data_reg[180] ;\n output \\not_strict_mode.app_rd_data_reg[181] ;\n output \\not_strict_mode.app_rd_data_reg[182] ;\n output \\not_strict_mode.app_rd_data_reg[183] ;\n output \\not_strict_mode.app_rd_data_reg[208] ;\n output \\not_strict_mode.app_rd_data_reg[209] ;\n output \\not_strict_mode.app_rd_data_reg[210] ;\n output \\not_strict_mode.app_rd_data_reg[211] ;\n output \\not_strict_mode.app_rd_data_reg[212] ;\n output \\not_strict_mode.app_rd_data_reg[213] ;\n output \\not_strict_mode.app_rd_data_reg[214] ;\n output \\not_strict_mode.app_rd_data_reg[215] ;\n output \\not_strict_mode.app_rd_data_reg[240] ;\n output \\not_strict_mode.app_rd_data_reg[241] ;\n output \\not_strict_mode.app_rd_data_reg[242] ;\n output \\not_strict_mode.app_rd_data_reg[243] ;\n output \\not_strict_mode.app_rd_data_reg[244]_0 ;\n output \\not_strict_mode.app_rd_data_reg[245] ;\n output \\not_strict_mode.app_rd_data_reg[246] ;\n output \\not_strict_mode.app_rd_data_reg[247]_0 ;\n output pi_phase_locked_all_r1_reg;\n output phy_if_empty_r_reg;\n output [0:0]\\not_strict_mode.app_rd_data_reg[23]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[23]_1 ;\n output [63:0]\\my_empty_reg[7] ;\n output B_byte_rd_en;\n output [2:0]Q;\n input [3:0]phaser_ctl_bus;\n input \\gen_byte_sel_div1.calib_in_common_reg ;\n input \\calib_sel_reg[0] ;\n input pi_en_stg2_f_reg;\n input pi_stg2_f_incdec_reg;\n input freq_refclk;\n input mem_refclk;\n input [0:0]mem_dqs_in;\n input A_rst_primitives;\n input \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n input sync_pulse;\n input CLK;\n input [1:0]PCENABLECALIB;\n input [5:0]\\calib_zero_inputs_reg[0] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n input ck_po_stg2_f_en_reg;\n input ck_po_stg2_f_indec_reg;\n input delay_done_r4_reg;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[247] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[246] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[245] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[244] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[243] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[242] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[241] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[240] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n input [7:0]mem_dq_in;\n input idelay_inc;\n input LD0_3;\n input CLKB0_7;\n input phy_if_reset;\n input mux_wrdata_en;\n input rst_r4;\n input [0:0]\\read_fifo.fifo_out_data_r_reg[6] ;\n input ram_init_done_r;\n input init_calib_complete_reg_rep;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[286] ;\n input [0:0]if_empty_r_0;\n input [1:0]my_empty;\n input \\my_empty_reg[4] ;\n input prbs_rdlvl_start_reg;\n input out;\n input [0:0]tail_r;\n input \\read_fifo.fifo_out_data_r_reg[6]_0 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n input A_rst_primitives_reg;\n input A_rst_primitives_reg_0;\n input A_rst_primitives_reg_1;\n input [71:0]phy_dout;\n input [0:0]\\gen_byte_sel_div1.calib_in_common_reg_3 ;\n input [7:0]\\calib_sel_reg[0]_0 ;\n input D_byte_rd_en;\n input A_byte_rd_en;\n\n wire A_byte_rd_en;\n wire A_rst_primitives;\n wire A_rst_primitives_reg;\n wire A_rst_primitives_reg_0;\n wire A_rst_primitives_reg_1;\n wire B_byte_rd_en;\n wire B_rclk;\n wire CLK;\n wire CLKB0_7;\n wire [5:0]COUNTERREADVAL;\n wire D_byte_rd_en;\n wire LD0_3;\n wire [1:0]PCENABLECALIB;\n wire [2:0]Q;\n wire \\calib_sel_reg[0] ;\n wire [7:0]\\calib_sel_reg[0]_0 ;\n wire [5:0]\\calib_zero_inputs_reg[0] ;\n wire ck_po_stg2_f_en_reg;\n wire ck_po_stg2_f_indec_reg;\n wire delay_done_r4_reg;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n wire freq_refclk;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n wire [0:0]\\gen_byte_sel_div1.calib_in_common_reg_3 ;\n wire idelay_inc;\n wire idelay_ld_rst_0;\n wire [3:0]if_d1;\n wire [3:0]if_d2;\n wire [3:0]if_d3;\n wire [3:0]if_d4;\n wire [3:0]if_d5;\n wire [3:0]if_d6;\n wire [3:0]if_d7;\n wire [3:0]if_d8;\n wire if_empty_;\n wire [0:0]if_empty_r;\n wire [0:0]if_empty_r_0;\n wire ififo_rst;\n wire ififo_wr_enable;\n wire \\in_fifo_gen.in_fifo_n_0 ;\n wire \\in_fifo_gen.in_fifo_n_1 ;\n wire \\in_fifo_gen.in_fifo_n_3 ;\n wire init_calib_complete_reg_rep;\n wire iserdes_clkdiv;\n wire [7:0]mem_dq_in;\n wire [8:0]mem_dq_out;\n wire [8:0]mem_dq_ts;\n wire [0:0]mem_dqs_in;\n wire [0:0]mem_dqs_out;\n wire [0:0]mem_dqs_ts;\n wire mem_refclk;\n wire mux_rd_valid_r_reg;\n wire mux_wrdata_en;\n wire [1:0]my_empty;\n wire \\my_empty_reg[1] ;\n wire \\my_empty_reg[4] ;\n wire [63:0]\\my_empty_reg[7] ;\n wire \\not_strict_mode.app_rd_data_reg[112] ;\n wire \\not_strict_mode.app_rd_data_reg[113] ;\n wire \\not_strict_mode.app_rd_data_reg[114] ;\n wire \\not_strict_mode.app_rd_data_reg[115] ;\n wire \\not_strict_mode.app_rd_data_reg[116] ;\n wire \\not_strict_mode.app_rd_data_reg[117] ;\n wire \\not_strict_mode.app_rd_data_reg[118] ;\n wire \\not_strict_mode.app_rd_data_reg[119] ;\n wire \\not_strict_mode.app_rd_data_reg[144] ;\n wire \\not_strict_mode.app_rd_data_reg[145] ;\n wire \\not_strict_mode.app_rd_data_reg[146] ;\n wire \\not_strict_mode.app_rd_data_reg[147] ;\n wire \\not_strict_mode.app_rd_data_reg[148] ;\n wire \\not_strict_mode.app_rd_data_reg[149] ;\n wire \\not_strict_mode.app_rd_data_reg[150] ;\n wire \\not_strict_mode.app_rd_data_reg[151] ;\n wire \\not_strict_mode.app_rd_data_reg[16] ;\n wire \\not_strict_mode.app_rd_data_reg[176] ;\n wire \\not_strict_mode.app_rd_data_reg[177] ;\n wire \\not_strict_mode.app_rd_data_reg[178] ;\n wire \\not_strict_mode.app_rd_data_reg[179] ;\n wire \\not_strict_mode.app_rd_data_reg[17] ;\n wire \\not_strict_mode.app_rd_data_reg[180] ;\n wire \\not_strict_mode.app_rd_data_reg[181] ;\n wire \\not_strict_mode.app_rd_data_reg[182] ;\n wire \\not_strict_mode.app_rd_data_reg[183] ;\n wire \\not_strict_mode.app_rd_data_reg[18] ;\n wire \\not_strict_mode.app_rd_data_reg[19] ;\n wire \\not_strict_mode.app_rd_data_reg[208] ;\n wire \\not_strict_mode.app_rd_data_reg[209] ;\n wire \\not_strict_mode.app_rd_data_reg[20] ;\n wire \\not_strict_mode.app_rd_data_reg[210] ;\n wire \\not_strict_mode.app_rd_data_reg[211] ;\n wire \\not_strict_mode.app_rd_data_reg[212] ;\n wire \\not_strict_mode.app_rd_data_reg[213] ;\n wire \\not_strict_mode.app_rd_data_reg[214] ;\n wire \\not_strict_mode.app_rd_data_reg[215] ;\n wire \\not_strict_mode.app_rd_data_reg[21] ;\n wire \\not_strict_mode.app_rd_data_reg[22] ;\n wire \\not_strict_mode.app_rd_data_reg[23] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[23]_0 ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[23]_1 ;\n wire \\not_strict_mode.app_rd_data_reg[240] ;\n wire \\not_strict_mode.app_rd_data_reg[241] ;\n wire \\not_strict_mode.app_rd_data_reg[242] ;\n wire \\not_strict_mode.app_rd_data_reg[243] ;\n wire \\not_strict_mode.app_rd_data_reg[244] ;\n wire \\not_strict_mode.app_rd_data_reg[244]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[245] ;\n wire \\not_strict_mode.app_rd_data_reg[246] ;\n wire [63:0]\\not_strict_mode.app_rd_data_reg[247] ;\n wire \\not_strict_mode.app_rd_data_reg[247]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[48] ;\n wire \\not_strict_mode.app_rd_data_reg[49] ;\n wire \\not_strict_mode.app_rd_data_reg[50] ;\n wire \\not_strict_mode.app_rd_data_reg[51] ;\n wire \\not_strict_mode.app_rd_data_reg[52] ;\n wire \\not_strict_mode.app_rd_data_reg[53] ;\n wire \\not_strict_mode.app_rd_data_reg[54] ;\n wire \\not_strict_mode.app_rd_data_reg[55] ;\n wire \\not_strict_mode.app_rd_data_reg[80] ;\n wire \\not_strict_mode.app_rd_data_reg[81] ;\n wire \\not_strict_mode.app_rd_data_reg[82] ;\n wire \\not_strict_mode.app_rd_data_reg[83] ;\n wire \\not_strict_mode.app_rd_data_reg[84] ;\n wire \\not_strict_mode.app_rd_data_reg[85] ;\n wire \\not_strict_mode.app_rd_data_reg[86] ;\n wire \\not_strict_mode.app_rd_data_reg[87] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n wire \\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n wire [7:0]of_d9;\n wire [39:0]of_dqbus;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ;\n wire ofifo_rst;\n wire oserdes_clk;\n wire oserdes_clk_delayed;\n wire oserdes_clkdiv;\n wire [1:0]oserdes_dq_ts;\n wire [1:0]oserdes_dqs;\n wire [1:0]oserdes_dqs_ts;\n wire out;\n wire out_fifo_n_0;\n wire out_fifo_n_1;\n wire out_fifo_n_2;\n wire out_fifo_n_3;\n wire [3:0]phaser_ctl_bus;\n wire \\phaser_in_gen.phaser_in_n_1 ;\n wire \\phaser_in_gen.phaser_in_n_2 ;\n wire \\phaser_in_gen.phaser_in_n_5 ;\n wire \\phaser_in_gen.phaser_in_n_6 ;\n wire phaser_out_n_0;\n wire phaser_out_n_1;\n wire [71:0]phy_dout;\n wire phy_if_empty_r_reg;\n wire phy_if_reset;\n wire phy_rddata_en;\n wire [0:0]\\pi_dqs_found_lanes_r1_reg[1] ;\n wire pi_en_stg2_f_reg;\n wire pi_phase_locked_all_r1_reg;\n wire pi_stg2_f_incdec_reg;\n wire [8:0]\\po_counter_read_val_reg[8] ;\n wire po_oserdes_rst;\n wire po_rd_enable;\n wire prbs_rdlvl_start_reg;\n wire ram_init_done_r;\n wire rd_buf_we;\n wire [79:0]rd_data;\n wire [71:6]rd_data_r;\n wire [0:0]\\rd_ptr_timing_reg[1] ;\n wire [0:0]\\read_fifo.fifo_out_data_r_reg[6] ;\n wire \\read_fifo.fifo_out_data_r_reg[6]_0 ;\n wire \\read_fifo.tail_r_reg[0] ;\n wire rst_r4;\n wire sync_pulse;\n wire [0:0]tail_r;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[240] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[241] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[242] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[243] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[244] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[245] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[246] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[247] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[286] ;\n wire [7:4]\\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED ;\n wire [7:4]\\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED ;\n wire [7:4]NLW_out_fifo_Q5_UNCONNECTED;\n wire [7:4]NLW_out_fifo_Q6_UNCONNECTED;\n wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;\n\n ddr3_ifmig_7series_v4_0_ddr_byte_group_io__parameterized0 ddr_byte_group_io\n (.A_rst_primitives(A_rst_primitives),\n .A_rst_primitives_reg(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),\n .CLK(CLK),\n .CLKB0_7(CLKB0_7),\n .CTSBUS(oserdes_dqs_ts[0]),\n .D1(if_d1),\n .D2(if_d2),\n .D3(if_d3),\n .D4(if_d4),\n .D5(if_d5),\n .D6(if_d6),\n .D7(if_d7),\n .D8(if_d8),\n .DQSBUS(oserdes_dqs),\n .DTSBUS(oserdes_dq_ts),\n .LD0_3(LD0_3),\n .\\calib_sel_reg[0] (\\calib_sel_reg[0]_0 ),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\gen_byte_sel_div1.calib_in_common_reg_2 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_0 (\\gen_byte_sel_div1.calib_in_common_reg_3 ),\n .idelay_inc(idelay_inc),\n .idelay_ld_rst_0(idelay_ld_rst_0),\n .iserdes_clkdiv(iserdes_clkdiv),\n .mem_dq_in(mem_dq_in),\n .mem_dq_out(mem_dq_out),\n .mem_dq_ts(mem_dq_ts),\n .mem_dqs_out(mem_dqs_out),\n .mem_dqs_ts(mem_dqs_ts),\n .of_dqbus(of_dqbus[39:4]),\n .oserdes_clk(oserdes_clk),\n .oserdes_clk_delayed(oserdes_clk_delayed),\n .oserdes_clkdiv(oserdes_clkdiv),\n .po_oserdes_rst(po_oserdes_rst),\n .rst_r4(rst_r4));\n (* syn_maxfan = \"3\" *) \n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(if_empty_),\n .Q(if_empty_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[10]),\n .Q(rd_data_r[10]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[11]),\n .Q(rd_data_r[11]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[12]),\n .Q(rd_data_r[12]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[13]),\n .Q(rd_data_r[13]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[14]),\n .Q(rd_data_r[14]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[15]),\n .Q(rd_data_r[15]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[16]),\n .Q(rd_data_r[16]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[17]),\n .Q(rd_data_r[17]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[18]),\n .Q(rd_data_r[18]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[19]),\n .Q(rd_data_r[19]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[20]),\n .Q(rd_data_r[20]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[21]),\n .Q(rd_data_r[21]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[22]),\n .Q(rd_data_r[22]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[23]),\n .Q(rd_data_r[23]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[24]),\n .Q(rd_data_r[24]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[25]),\n .Q(rd_data_r[25]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[26]),\n .Q(rd_data_r[26]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[27]),\n .Q(rd_data_r[27]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[28]),\n .Q(rd_data_r[28]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[29]),\n .Q(rd_data_r[29]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[30]),\n .Q(rd_data_r[30]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[31]),\n .Q(rd_data_r[31]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[32]),\n .Q(rd_data_r[32]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[33]),\n .Q(rd_data_r[33]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[34]),\n .Q(rd_data_r[34]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[35]),\n .Q(rd_data_r[35]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[36]),\n .Q(rd_data_r[36]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[37]),\n .Q(rd_data_r[37]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[38]),\n .Q(rd_data_r[38]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[39]),\n .Q(rd_data_r[39]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[40]),\n .Q(rd_data_r[40]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[41]),\n .Q(rd_data_r[41]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[42]),\n .Q(rd_data_r[42]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[43]),\n .Q(rd_data_r[43]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[44]),\n .Q(rd_data_r[44]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[45]),\n .Q(rd_data_r[45]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[46]),\n .Q(rd_data_r[46]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[47]),\n .Q(rd_data_r[47]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[48]),\n .Q(rd_data_r[48]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[49]),\n .Q(rd_data_r[49]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[50]),\n .Q(rd_data_r[50]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[51]),\n .Q(rd_data_r[51]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[52]),\n .Q(rd_data_r[52]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[53]),\n .Q(rd_data_r[53]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[54]),\n .Q(rd_data_r[54]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[55]),\n .Q(rd_data_r[55]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[56]),\n .Q(rd_data_r[56]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[57]),\n .Q(rd_data_r[57]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[58]),\n .Q(rd_data_r[58]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[59]),\n .Q(rd_data_r[59]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[60]),\n .Q(rd_data_r[60]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[61]),\n .Q(rd_data_r[61]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[62]),\n .Q(rd_data_r[62]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[63]),\n .Q(rd_data_r[63]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[64]),\n .Q(rd_data_r[64]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[65]),\n .Q(rd_data_r[65]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[66]),\n .Q(rd_data_r[66]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[67]),\n .Q(rd_data_r[67]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[68]),\n .Q(rd_data_r[68]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[69]),\n .Q(rd_data_r[69]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[6]),\n .Q(rd_data_r[6]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[70]),\n .Q(rd_data_r[70]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[71]),\n .Q(rd_data_r[71]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[7]),\n .Q(rd_data_r[7]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[8]),\n .Q(\\not_strict_mode.app_rd_data_reg[23]_0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[9]),\n .Q(rd_data_r[9]),\n .R(1'b0));\n ddr3_ifmig_7series_v4_0_ddr_if_post_fifo_5 \\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo \n (.A_byte_rd_en(A_byte_rd_en),\n .B_byte_rd_en(B_byte_rd_en),\n .CLK(CLK),\n .D_byte_rd_en(D_byte_rd_en),\n .Q({rd_data_r[71:9],\\not_strict_mode.app_rd_data_reg[23]_0 ,rd_data_r[7:6]}),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (if_empty_r),\n .if_empty_r_0(if_empty_r_0),\n .ififo_rst(ififo_rst),\n .mux_rd_valid_r_reg(mux_rd_valid_r_reg),\n .my_empty(my_empty),\n .\\my_empty_reg[4]_0 (\\my_empty_reg[4] ),\n .\\not_strict_mode.app_rd_data_reg[112] (\\not_strict_mode.app_rd_data_reg[112] ),\n .\\not_strict_mode.app_rd_data_reg[113] (\\not_strict_mode.app_rd_data_reg[113] ),\n .\\not_strict_mode.app_rd_data_reg[114] (\\not_strict_mode.app_rd_data_reg[114] ),\n .\\not_strict_mode.app_rd_data_reg[115] (\\not_strict_mode.app_rd_data_reg[115] ),\n .\\not_strict_mode.app_rd_data_reg[116] (\\not_strict_mode.app_rd_data_reg[116] ),\n .\\not_strict_mode.app_rd_data_reg[117] (\\not_strict_mode.app_rd_data_reg[117] ),\n .\\not_strict_mode.app_rd_data_reg[118] (\\not_strict_mode.app_rd_data_reg[118] ),\n .\\not_strict_mode.app_rd_data_reg[119] (\\not_strict_mode.app_rd_data_reg[119] ),\n .\\not_strict_mode.app_rd_data_reg[144] (\\not_strict_mode.app_rd_data_reg[144] ),\n .\\not_strict_mode.app_rd_data_reg[145] (\\not_strict_mode.app_rd_data_reg[145] ),\n .\\not_strict_mode.app_rd_data_reg[146] (\\not_strict_mode.app_rd_data_reg[146] ),\n .\\not_strict_mode.app_rd_data_reg[147] (\\not_strict_mode.app_rd_data_reg[147] ),\n .\\not_strict_mode.app_rd_data_reg[148] (\\not_strict_mode.app_rd_data_reg[148] ),\n .\\not_strict_mode.app_rd_data_reg[149] (\\not_strict_mode.app_rd_data_reg[149] ),\n .\\not_strict_mode.app_rd_data_reg[150] (\\not_strict_mode.app_rd_data_reg[150] ),\n .\\not_strict_mode.app_rd_data_reg[151] (\\not_strict_mode.app_rd_data_reg[151] ),\n .\\not_strict_mode.app_rd_data_reg[16] (\\not_strict_mode.app_rd_data_reg[16] ),\n .\\not_strict_mode.app_rd_data_reg[176] (\\not_strict_mode.app_rd_data_reg[176] ),\n .\\not_strict_mode.app_rd_data_reg[177] (\\not_strict_mode.app_rd_data_reg[177] ),\n .\\not_strict_mode.app_rd_data_reg[178] (\\not_strict_mode.app_rd_data_reg[178] ),\n .\\not_strict_mode.app_rd_data_reg[179] (\\not_strict_mode.app_rd_data_reg[179] ),\n .\\not_strict_mode.app_rd_data_reg[17] (\\not_strict_mode.app_rd_data_reg[17] ),\n .\\not_strict_mode.app_rd_data_reg[180] (\\not_strict_mode.app_rd_data_reg[180] ),\n .\\not_strict_mode.app_rd_data_reg[181] (\\not_strict_mode.app_rd_data_reg[181] ),\n .\\not_strict_mode.app_rd_data_reg[182] (\\not_strict_mode.app_rd_data_reg[182] ),\n .\\not_strict_mode.app_rd_data_reg[183] (\\not_strict_mode.app_rd_data_reg[183] ),\n .\\not_strict_mode.app_rd_data_reg[18] (\\not_strict_mode.app_rd_data_reg[18] ),\n .\\not_strict_mode.app_rd_data_reg[19] (\\not_strict_mode.app_rd_data_reg[19] ),\n .\\not_strict_mode.app_rd_data_reg[208] (\\not_strict_mode.app_rd_data_reg[208] ),\n .\\not_strict_mode.app_rd_data_reg[209] (\\not_strict_mode.app_rd_data_reg[209] ),\n .\\not_strict_mode.app_rd_data_reg[20] (\\not_strict_mode.app_rd_data_reg[20] ),\n .\\not_strict_mode.app_rd_data_reg[210] (\\not_strict_mode.app_rd_data_reg[210] ),\n .\\not_strict_mode.app_rd_data_reg[211] (\\not_strict_mode.app_rd_data_reg[211] ),\n .\\not_strict_mode.app_rd_data_reg[212] (\\not_strict_mode.app_rd_data_reg[212] ),\n .\\not_strict_mode.app_rd_data_reg[213] (\\not_strict_mode.app_rd_data_reg[213] ),\n .\\not_strict_mode.app_rd_data_reg[214] (\\not_strict_mode.app_rd_data_reg[214] ),\n .\\not_strict_mode.app_rd_data_reg[215] (\\not_strict_mode.app_rd_data_reg[215] ),\n .\\not_strict_mode.app_rd_data_reg[21] (\\not_strict_mode.app_rd_data_reg[21] ),\n .\\not_strict_mode.app_rd_data_reg[22] (\\not_strict_mode.app_rd_data_reg[22] ),\n .\\not_strict_mode.app_rd_data_reg[23] (\\not_strict_mode.app_rd_data_reg[23] ),\n .\\not_strict_mode.app_rd_data_reg[23]_0 (\\not_strict_mode.app_rd_data_reg[23]_1 ),\n .\\not_strict_mode.app_rd_data_reg[240] (\\not_strict_mode.app_rd_data_reg[240] ),\n .\\not_strict_mode.app_rd_data_reg[241] (\\not_strict_mode.app_rd_data_reg[241] ),\n .\\not_strict_mode.app_rd_data_reg[242] (\\not_strict_mode.app_rd_data_reg[242] ),\n .\\not_strict_mode.app_rd_data_reg[243] (\\not_strict_mode.app_rd_data_reg[243] ),\n .\\not_strict_mode.app_rd_data_reg[244] (\\not_strict_mode.app_rd_data_reg[244] ),\n .\\not_strict_mode.app_rd_data_reg[244]_0 (\\not_strict_mode.app_rd_data_reg[244]_0 ),\n .\\not_strict_mode.app_rd_data_reg[245] (\\not_strict_mode.app_rd_data_reg[245] ),\n .\\not_strict_mode.app_rd_data_reg[246] (\\not_strict_mode.app_rd_data_reg[246] ),\n .\\not_strict_mode.app_rd_data_reg[247] (\\not_strict_mode.app_rd_data_reg[247] ),\n .\\not_strict_mode.app_rd_data_reg[247]_0 (\\not_strict_mode.app_rd_data_reg[247]_0 ),\n .\\not_strict_mode.app_rd_data_reg[48] (\\not_strict_mode.app_rd_data_reg[48] ),\n .\\not_strict_mode.app_rd_data_reg[49] (\\not_strict_mode.app_rd_data_reg[49] ),\n .\\not_strict_mode.app_rd_data_reg[50] (\\not_strict_mode.app_rd_data_reg[50] ),\n .\\not_strict_mode.app_rd_data_reg[51] (\\not_strict_mode.app_rd_data_reg[51] ),\n .\\not_strict_mode.app_rd_data_reg[52] (\\not_strict_mode.app_rd_data_reg[52] ),\n .\\not_strict_mode.app_rd_data_reg[53] (\\not_strict_mode.app_rd_data_reg[53] ),\n .\\not_strict_mode.app_rd_data_reg[54] (\\not_strict_mode.app_rd_data_reg[54] ),\n .\\not_strict_mode.app_rd_data_reg[55] (\\not_strict_mode.app_rd_data_reg[55] ),\n .\\not_strict_mode.app_rd_data_reg[80] (\\not_strict_mode.app_rd_data_reg[80] ),\n .\\not_strict_mode.app_rd_data_reg[81] (\\not_strict_mode.app_rd_data_reg[81] ),\n .\\not_strict_mode.app_rd_data_reg[82] (\\not_strict_mode.app_rd_data_reg[82] ),\n .\\not_strict_mode.app_rd_data_reg[83] (\\not_strict_mode.app_rd_data_reg[83] ),\n .\\not_strict_mode.app_rd_data_reg[84] (\\not_strict_mode.app_rd_data_reg[84] ),\n .\\not_strict_mode.app_rd_data_reg[85] (\\not_strict_mode.app_rd_data_reg[85] ),\n .\\not_strict_mode.app_rd_data_reg[86] (\\not_strict_mode.app_rd_data_reg[86] ),\n .\\not_strict_mode.app_rd_data_reg[87] (\\not_strict_mode.app_rd_data_reg[87] ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ),\n .\\not_strict_mode.status_ram.rd_buf_we_r1_reg (\\not_strict_mode.status_ram.rd_buf_we_r1_reg ),\n .out(out),\n .phy_if_empty_r_reg(phy_if_empty_r_reg),\n .phy_rddata_en(phy_rddata_en),\n .prbs_rdlvl_start_reg(prbs_rdlvl_start_reg),\n .ram_init_done_r(ram_init_done_r),\n .rd_buf_we(rd_buf_we),\n .\\rd_ptr_timing_reg[1]_0 (\\rd_ptr_timing_reg[1] ),\n .\\read_fifo.fifo_out_data_r_reg[6] (\\read_fifo.fifo_out_data_r_reg[6] ),\n .\\read_fifo.fifo_out_data_r_reg[6]_0 (\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .\\read_fifo.tail_r_reg[0] (\\read_fifo.tail_r_reg[0] ),\n .tail_r(tail_r));\n FDSE #(\n .INIT(1'b1)) \n ififo_rst_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .Q(ififo_rst),\n .S(phy_if_reset));\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n IN_FIFO #(\n .ALMOST_EMPTY_VALUE(1),\n .ALMOST_FULL_VALUE(1),\n .ARRAY_MODE(\"ARRAY_MODE_4_X_8\"),\n .SYNCHRONOUS_MODE(\"FALSE\")) \n \\in_fifo_gen.in_fifo \n (.ALMOSTEMPTY(\\in_fifo_gen.in_fifo_n_0 ),\n .ALMOSTFULL(\\in_fifo_gen.in_fifo_n_1 ),\n .D0({1'b0,1'b0,1'b0,1'b0}),\n .D1(if_d1),\n .D2(if_d2),\n .D3(if_d3),\n .D4(if_d4),\n .D5({\\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED [7:4],if_d5}),\n .D6({\\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED [7:4],if_d6}),\n .D7(if_d7),\n .D8(if_d8),\n .D9({1'b0,1'b0,1'b0,1'b0}),\n .EMPTY(if_empty_),\n .FULL(\\in_fifo_gen.in_fifo_n_3 ),\n .Q0(rd_data[7:0]),\n .Q1(rd_data[15:8]),\n .Q2(rd_data[23:16]),\n .Q3(rd_data[31:24]),\n .Q4(rd_data[39:32]),\n .Q5(rd_data[47:40]),\n .Q6(rd_data[55:48]),\n .Q7(rd_data[63:56]),\n .Q8(rd_data[71:64]),\n .Q9(rd_data[79:72]),\n .RDCLK(CLK),\n .RDEN(1'b1),\n .RESET(ififo_rst),\n .WRCLK(iserdes_clkdiv),\n .WREN(ififo_wr_enable));\n ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized3 \\of_pre_fifo_gen.u_ddr_of_pre_fifo \n (.CLK(CLK),\n .D0({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }),\n .D9(of_d9),\n .Q(Q),\n .init_calib_complete_reg_rep(init_calib_complete_reg_rep),\n .mux_wrdata_en(mux_wrdata_en),\n .\\my_empty_reg[1]_0 (\\my_empty_reg[1] ),\n .\\my_empty_reg[7]_0 (\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ),\n .\\my_empty_reg[7]_1 (\\my_empty_reg[7] ),\n .ofifo_rst(ofifo_rst),\n .ofifo_rst_reg(out_fifo_n_3),\n .phy_dout(phy_dout),\n .\\write_buffer.wr_buf_out_data_reg[286] (\\write_buffer.wr_buf_out_data_reg[286] ));\n FDSE #(\n .INIT(1'b1)) \n ofifo_rst_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .Q(ofifo_rst),\n .S(A_rst_primitives));\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n OUT_FIFO #(\n .ALMOST_EMPTY_VALUE(1),\n .ALMOST_FULL_VALUE(1),\n .ARRAY_MODE(\"ARRAY_MODE_8_X_4\"),\n .OUTPUT_DISABLE(\"FALSE\"),\n .SYNCHRONOUS_MODE(\"FALSE\")) \n out_fifo\n (.ALMOSTEMPTY(out_fifo_n_0),\n .ALMOSTFULL(out_fifo_n_1),\n .D0({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }),\n .D1(\\write_buffer.wr_buf_out_data_reg[247] ),\n .D2(\\write_buffer.wr_buf_out_data_reg[246] ),\n .D3(\\write_buffer.wr_buf_out_data_reg[245] ),\n .D4(\\write_buffer.wr_buf_out_data_reg[244] ),\n .D5(\\write_buffer.wr_buf_out_data_reg[243] ),\n .D6(\\write_buffer.wr_buf_out_data_reg[242] ),\n .D7(\\write_buffer.wr_buf_out_data_reg[241] ),\n .D8(\\write_buffer.wr_buf_out_data_reg[240] ),\n .D9(of_d9),\n .EMPTY(out_fifo_n_2),\n .FULL(out_fifo_n_3),\n .Q0(of_dqbus[3:0]),\n .Q1(of_dqbus[7:4]),\n .Q2(of_dqbus[11:8]),\n .Q3(of_dqbus[15:12]),\n .Q4(of_dqbus[19:16]),\n .Q5({NLW_out_fifo_Q5_UNCONNECTED[7:4],of_dqbus[23:20]}),\n .Q6({NLW_out_fifo_Q6_UNCONNECTED[7:4],of_dqbus[27:24]}),\n .Q7(of_dqbus[31:28]),\n .Q8(of_dqbus[35:32]),\n .Q9(of_dqbus[39:36]),\n .RDCLK(oserdes_clkdiv),\n .RDEN(po_rd_enable),\n .RESET(ofifo_rst),\n .WRCLK(CLK),\n .WREN(\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ));\n (* box_type = \"PRIMITIVE\" *) \n PHASER_IN_PHY #(\n .BURST_MODE(\"TRUE\"),\n .CLKOUT_DIV(2),\n .DQS_AUTO_RECAL(1'b1),\n .DQS_BIAS_MODE(\"FALSE\"),\n .DQS_FIND_PATTERN(3'b000),\n .FINE_DELAY(33),\n .FREQ_REF_DIV(\"NONE\"),\n .IS_RST_INVERTED(1'b0),\n .MEMREFCLK_PERIOD(1.112000),\n .OUTPUT_CLK_SRC(\"DELAYED_REF\"),\n .PHASEREFCLK_PERIOD(1.112000),\n .REFCLK_PERIOD(1.112000),\n .SEL_CLK_OFFSET(6),\n .SYNC_IN_DIV_RST(\"TRUE\"),\n .WR_CYCLES(\"FALSE\")) \n \\phaser_in_gen.phaser_in \n (.BURSTPENDINGPHY(phaser_ctl_bus[1]),\n .COUNTERLOADEN(\\gen_byte_sel_div1.calib_in_common_reg ),\n .COUNTERLOADVAL(\\calib_zero_inputs_reg[0] ),\n .COUNTERREADEN(\\calib_sel_reg[0] ),\n .COUNTERREADVAL(COUNTERREADVAL),\n .DQSFOUND(\\pi_dqs_found_lanes_r1_reg[1] ),\n .DQSOUTOFRANGE(\\phaser_in_gen.phaser_in_n_1 ),\n .ENCALIBPHY(PCENABLECALIB),\n .FINEENABLE(pi_en_stg2_f_reg),\n .FINEINC(pi_stg2_f_incdec_reg),\n .FINEOVERFLOW(\\phaser_in_gen.phaser_in_n_2 ),\n .FREQREFCLK(freq_refclk),\n .ICLK(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),\n .ICLKDIV(iserdes_clkdiv),\n .ISERDESRST(\\phaser_in_gen.phaser_in_n_5 ),\n .MEMREFCLK(mem_refclk),\n .PHASELOCKED(\\phaser_in_gen.phaser_in_n_6 ),\n .PHASEREFCLK(mem_dqs_in),\n .RANKSELPHY(phaser_ctl_bus[3:2]),\n .RCLK(B_rclk),\n .RST(A_rst_primitives),\n .RSTDQSFIND(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .SYNCIN(sync_pulse),\n .SYSCLK(CLK),\n .WRENABLE(ififo_wr_enable));\n (* box_type = \"PRIMITIVE\" *) \n PHASER_OUT_PHY #(\n .CLKOUT_DIV(2),\n .COARSE_BYPASS(\"FALSE\"),\n .COARSE_DELAY(0),\n .DATA_CTL_N(\"TRUE\"),\n .DATA_RD_CYCLES(\"FALSE\"),\n .FINE_DELAY(60),\n .IS_RST_INVERTED(1'b0),\n .MEMREFCLK_PERIOD(1.111111),\n .OCLKDELAY_INV(\"TRUE\"),\n .OCLK_DELAY(28),\n .OUTPUT_CLK_SRC(\"DELAYED_REF\"),\n .PHASEREFCLK_PERIOD(1.000000),\n .PO(3'b111),\n .REFCLK_PERIOD(1.112000),\n .SYNC_IN_DIV_RST(\"TRUE\")) \n phaser_out\n (.BURSTPENDINGPHY(phaser_ctl_bus[0]),\n .COARSEENABLE(\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .COARSEINC(\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .COARSEOVERFLOW(phaser_out_n_0),\n .COUNTERLOADEN(1'b0),\n .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .COUNTERREADEN(\\calib_sel_reg[0] ),\n .COUNTERREADVAL(\\po_counter_read_val_reg[8] ),\n .CTSBUS(oserdes_dqs_ts),\n .DQSBUS(oserdes_dqs),\n .DTSBUS(oserdes_dq_ts),\n .ENCALIBPHY(PCENABLECALIB),\n .FINEENABLE(ck_po_stg2_f_en_reg),\n .FINEINC(ck_po_stg2_f_indec_reg),\n .FINEOVERFLOW(phaser_out_n_1),\n .FREQREFCLK(freq_refclk),\n .MEMREFCLK(mem_refclk),\n .OCLK(oserdes_clk),\n .OCLKDELAYED(oserdes_clk_delayed),\n .OCLKDIV(oserdes_clkdiv),\n .OSERDESRST(po_oserdes_rst),\n .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),\n .RDENABLE(po_rd_enable),\n .RST(A_rst_primitives),\n .SELFINEOCLKDELAY(delay_done_r4_reg),\n .SYNCIN(sync_pulse),\n .SYSCLK(CLK));\n LUT4 #(\n .INIT(16'h8000)) \n pi_phase_locked_all_inferred_i_1\n (.I0(\\phaser_in_gen.phaser_in_n_6 ),\n .I1(A_rst_primitives_reg),\n .I2(A_rst_primitives_reg_0),\n .I3(A_rst_primitives_reg_1),\n .O(pi_phase_locked_all_r1_reg));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_byte_lane\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_byte_lane__parameterized1\n (\\pi_dqs_found_lanes_r1_reg[2] ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,\n pi_phase_locked_all_r1_reg,\n COUNTERREADVAL,\n \\po_counter_read_val_reg[8] ,\n mem_dqs_out,\n mem_dqs_ts,\n mem_dq_out,\n mem_dq_ts,\n if_empty_r,\n \\rd_ptr_timing_reg[1] ,\n idelay_ld_rst_1,\n \\not_strict_mode.app_rd_data_reg[236] ,\n \\my_empty_reg[1] ,\n \\not_strict_mode.app_rd_data_reg[239] ,\n \\not_strict_mode.app_rd_data_reg[8] ,\n \\not_strict_mode.app_rd_data_reg[9] ,\n \\not_strict_mode.app_rd_data_reg[10] ,\n \\not_strict_mode.app_rd_data_reg[11] ,\n \\not_strict_mode.app_rd_data_reg[12] ,\n \\not_strict_mode.app_rd_data_reg[13] ,\n \\not_strict_mode.app_rd_data_reg[14] ,\n \\not_strict_mode.app_rd_data_reg[15] ,\n \\not_strict_mode.app_rd_data_reg[40] ,\n \\not_strict_mode.app_rd_data_reg[41] ,\n \\not_strict_mode.app_rd_data_reg[42] ,\n \\not_strict_mode.app_rd_data_reg[43] ,\n \\not_strict_mode.app_rd_data_reg[44] ,\n \\not_strict_mode.app_rd_data_reg[45] ,\n \\not_strict_mode.app_rd_data_reg[46] ,\n \\not_strict_mode.app_rd_data_reg[47] ,\n \\not_strict_mode.app_rd_data_reg[72] ,\n \\not_strict_mode.app_rd_data_reg[73] ,\n \\not_strict_mode.app_rd_data_reg[74] ,\n \\not_strict_mode.app_rd_data_reg[75] ,\n \\not_strict_mode.app_rd_data_reg[76] ,\n \\not_strict_mode.app_rd_data_reg[77] ,\n \\not_strict_mode.app_rd_data_reg[78] ,\n \\not_strict_mode.app_rd_data_reg[79] ,\n \\not_strict_mode.app_rd_data_reg[104] ,\n \\not_strict_mode.app_rd_data_reg[105] ,\n \\not_strict_mode.app_rd_data_reg[106] ,\n \\not_strict_mode.app_rd_data_reg[107] ,\n \\not_strict_mode.app_rd_data_reg[108] ,\n \\not_strict_mode.app_rd_data_reg[109] ,\n \\not_strict_mode.app_rd_data_reg[110] ,\n \\not_strict_mode.app_rd_data_reg[111] ,\n \\not_strict_mode.app_rd_data_reg[136] ,\n \\not_strict_mode.app_rd_data_reg[137] ,\n \\not_strict_mode.app_rd_data_reg[138] ,\n \\not_strict_mode.app_rd_data_reg[139] ,\n \\not_strict_mode.app_rd_data_reg[140] ,\n \\not_strict_mode.app_rd_data_reg[141] ,\n \\not_strict_mode.app_rd_data_reg[142] ,\n \\not_strict_mode.app_rd_data_reg[143] ,\n \\not_strict_mode.app_rd_data_reg[168] ,\n \\not_strict_mode.app_rd_data_reg[169] ,\n \\not_strict_mode.app_rd_data_reg[170] ,\n \\not_strict_mode.app_rd_data_reg[171] ,\n \\not_strict_mode.app_rd_data_reg[172] ,\n \\not_strict_mode.app_rd_data_reg[173] ,\n \\not_strict_mode.app_rd_data_reg[174] ,\n \\not_strict_mode.app_rd_data_reg[175] ,\n \\not_strict_mode.app_rd_data_reg[200] ,\n \\not_strict_mode.app_rd_data_reg[201] ,\n \\not_strict_mode.app_rd_data_reg[202] ,\n \\not_strict_mode.app_rd_data_reg[203] ,\n \\not_strict_mode.app_rd_data_reg[204] ,\n \\not_strict_mode.app_rd_data_reg[205] ,\n \\not_strict_mode.app_rd_data_reg[206] ,\n \\not_strict_mode.app_rd_data_reg[207] ,\n \\not_strict_mode.app_rd_data_reg[232] ,\n \\not_strict_mode.app_rd_data_reg[233] ,\n \\not_strict_mode.app_rd_data_reg[234] ,\n \\not_strict_mode.app_rd_data_reg[235] ,\n \\not_strict_mode.app_rd_data_reg[236]_0 ,\n \\not_strict_mode.app_rd_data_reg[237] ,\n \\not_strict_mode.app_rd_data_reg[238] ,\n \\not_strict_mode.app_rd_data_reg[239]_0 ,\n \\not_strict_mode.app_rd_data_reg[15]_0 ,\n \\not_strict_mode.app_rd_data_reg[15]_1 ,\n \\my_empty_reg[7] ,\n C_byte_rd_en,\n Q,\n phaser_ctl_bus,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n \\calib_sel_reg[1] ,\n pi_en_stg2_f_reg,\n pi_stg2_f_incdec_reg,\n freq_refclk,\n mem_refclk,\n mem_dqs_in,\n A_rst_primitives,\n \\gen_byte_sel_div1.calib_in_common_reg_0 ,\n sync_pulse,\n CLK,\n PCENABLECALIB,\n \\calib_zero_inputs_reg[0] ,\n \\gen_byte_sel_div1.calib_in_common_reg_1 ,\n ck_po_stg2_f_en_reg,\n ck_po_stg2_f_indec_reg,\n delay_done_r4_reg,\n \\write_buffer.wr_buf_out_data_reg[239] ,\n \\write_buffer.wr_buf_out_data_reg[238] ,\n \\write_buffer.wr_buf_out_data_reg[237] ,\n \\write_buffer.wr_buf_out_data_reg[236] ,\n \\write_buffer.wr_buf_out_data_reg[235] ,\n \\write_buffer.wr_buf_out_data_reg[234] ,\n \\write_buffer.wr_buf_out_data_reg[233] ,\n \\write_buffer.wr_buf_out_data_reg[232] ,\n \\gen_byte_sel_div1.calib_in_common_reg_2 ,\n mem_dq_in,\n idelay_inc,\n LD0_4,\n CLKB0_8,\n phy_if_reset,\n mux_wrdata_en,\n rst_r4,\n init_calib_complete_reg_rep,\n \\write_buffer.wr_buf_out_data_reg[285] ,\n \\read_fifo.fifo_out_data_r_reg[6] ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,\n phy_dout,\n \\gen_byte_sel_div1.calib_in_common_reg_3 ,\n \\calib_sel_reg[1]_0 ,\n D_byte_rd_en,\n A_byte_rd_en,\n if_empty_r_0,\n \\my_empty_reg[4] );\n output [0:0]\\pi_dqs_found_lanes_r1_reg[2] ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n output pi_phase_locked_all_r1_reg;\n output [5:0]COUNTERREADVAL;\n output [8:0]\\po_counter_read_val_reg[8] ;\n output [0:0]mem_dqs_out;\n output [0:0]mem_dqs_ts;\n output [8:0]mem_dq_out;\n output [8:0]mem_dq_ts;\n output [0:0]if_empty_r;\n output [1:0]\\rd_ptr_timing_reg[1] ;\n output idelay_ld_rst_1;\n output \\not_strict_mode.app_rd_data_reg[236] ;\n output \\my_empty_reg[1] ;\n output [63:0]\\not_strict_mode.app_rd_data_reg[239] ;\n output \\not_strict_mode.app_rd_data_reg[8] ;\n output \\not_strict_mode.app_rd_data_reg[9] ;\n output \\not_strict_mode.app_rd_data_reg[10] ;\n output \\not_strict_mode.app_rd_data_reg[11] ;\n output \\not_strict_mode.app_rd_data_reg[12] ;\n output \\not_strict_mode.app_rd_data_reg[13] ;\n output \\not_strict_mode.app_rd_data_reg[14] ;\n output \\not_strict_mode.app_rd_data_reg[15] ;\n output \\not_strict_mode.app_rd_data_reg[40] ;\n output \\not_strict_mode.app_rd_data_reg[41] ;\n output \\not_strict_mode.app_rd_data_reg[42] ;\n output \\not_strict_mode.app_rd_data_reg[43] ;\n output \\not_strict_mode.app_rd_data_reg[44] ;\n output \\not_strict_mode.app_rd_data_reg[45] ;\n output \\not_strict_mode.app_rd_data_reg[46] ;\n output \\not_strict_mode.app_rd_data_reg[47] ;\n output \\not_strict_mode.app_rd_data_reg[72] ;\n output \\not_strict_mode.app_rd_data_reg[73] ;\n output \\not_strict_mode.app_rd_data_reg[74] ;\n output \\not_strict_mode.app_rd_data_reg[75] ;\n output \\not_strict_mode.app_rd_data_reg[76] ;\n output \\not_strict_mode.app_rd_data_reg[77] ;\n output \\not_strict_mode.app_rd_data_reg[78] ;\n output \\not_strict_mode.app_rd_data_reg[79] ;\n output \\not_strict_mode.app_rd_data_reg[104] ;\n output \\not_strict_mode.app_rd_data_reg[105] ;\n output \\not_strict_mode.app_rd_data_reg[106] ;\n output \\not_strict_mode.app_rd_data_reg[107] ;\n output \\not_strict_mode.app_rd_data_reg[108] ;\n output \\not_strict_mode.app_rd_data_reg[109] ;\n output \\not_strict_mode.app_rd_data_reg[110] ;\n output \\not_strict_mode.app_rd_data_reg[111] ;\n output \\not_strict_mode.app_rd_data_reg[136] ;\n output \\not_strict_mode.app_rd_data_reg[137] ;\n output \\not_strict_mode.app_rd_data_reg[138] ;\n output \\not_strict_mode.app_rd_data_reg[139] ;\n output \\not_strict_mode.app_rd_data_reg[140] ;\n output \\not_strict_mode.app_rd_data_reg[141] ;\n output \\not_strict_mode.app_rd_data_reg[142] ;\n output \\not_strict_mode.app_rd_data_reg[143] ;\n output \\not_strict_mode.app_rd_data_reg[168] ;\n output \\not_strict_mode.app_rd_data_reg[169] ;\n output \\not_strict_mode.app_rd_data_reg[170] ;\n output \\not_strict_mode.app_rd_data_reg[171] ;\n output \\not_strict_mode.app_rd_data_reg[172] ;\n output \\not_strict_mode.app_rd_data_reg[173] ;\n output \\not_strict_mode.app_rd_data_reg[174] ;\n output \\not_strict_mode.app_rd_data_reg[175] ;\n output \\not_strict_mode.app_rd_data_reg[200] ;\n output \\not_strict_mode.app_rd_data_reg[201] ;\n output \\not_strict_mode.app_rd_data_reg[202] ;\n output \\not_strict_mode.app_rd_data_reg[203] ;\n output \\not_strict_mode.app_rd_data_reg[204] ;\n output \\not_strict_mode.app_rd_data_reg[205] ;\n output \\not_strict_mode.app_rd_data_reg[206] ;\n output \\not_strict_mode.app_rd_data_reg[207] ;\n output \\not_strict_mode.app_rd_data_reg[232] ;\n output \\not_strict_mode.app_rd_data_reg[233] ;\n output \\not_strict_mode.app_rd_data_reg[234] ;\n output \\not_strict_mode.app_rd_data_reg[235] ;\n output \\not_strict_mode.app_rd_data_reg[236]_0 ;\n output \\not_strict_mode.app_rd_data_reg[237] ;\n output \\not_strict_mode.app_rd_data_reg[238] ;\n output \\not_strict_mode.app_rd_data_reg[239]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[15]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[15]_1 ;\n output [63:0]\\my_empty_reg[7] ;\n output C_byte_rd_en;\n output [2:0]Q;\n input [3:0]phaser_ctl_bus;\n input \\gen_byte_sel_div1.calib_in_common_reg ;\n input \\calib_sel_reg[1] ;\n input pi_en_stg2_f_reg;\n input pi_stg2_f_incdec_reg;\n input freq_refclk;\n input mem_refclk;\n input [0:0]mem_dqs_in;\n input A_rst_primitives;\n input \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n input sync_pulse;\n input CLK;\n input [1:0]PCENABLECALIB;\n input [5:0]\\calib_zero_inputs_reg[0] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n input ck_po_stg2_f_en_reg;\n input ck_po_stg2_f_indec_reg;\n input delay_done_r4_reg;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[239] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[238] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[237] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[236] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[235] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[234] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[233] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[232] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n input [7:0]mem_dq_in;\n input idelay_inc;\n input LD0_4;\n input CLKB0_8;\n input phy_if_reset;\n input mux_wrdata_en;\n input rst_r4;\n input init_calib_complete_reg_rep;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[285] ;\n input \\read_fifo.fifo_out_data_r_reg[6] ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n input [71:0]phy_dout;\n input [0:0]\\gen_byte_sel_div1.calib_in_common_reg_3 ;\n input [7:0]\\calib_sel_reg[1]_0 ;\n input D_byte_rd_en;\n input A_byte_rd_en;\n input [0:0]if_empty_r_0;\n input [0:0]\\my_empty_reg[4] ;\n\n wire A_byte_rd_en;\n wire A_rst_primitives;\n wire CLK;\n wire CLKB0_8;\n wire [5:0]COUNTERREADVAL;\n wire C_byte_rd_en;\n wire D_byte_rd_en;\n wire LD0_4;\n wire [1:0]PCENABLECALIB;\n wire [2:0]Q;\n wire \\calib_sel_reg[1] ;\n wire [7:0]\\calib_sel_reg[1]_0 ;\n wire [5:0]\\calib_zero_inputs_reg[0] ;\n wire ck_po_stg2_f_en_reg;\n wire ck_po_stg2_f_indec_reg;\n wire delay_done_r4_reg;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n wire freq_refclk;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n wire [0:0]\\gen_byte_sel_div1.calib_in_common_reg_3 ;\n wire idelay_inc;\n wire idelay_ld_rst_1;\n wire [3:0]if_d1;\n wire [3:0]if_d2;\n wire [3:0]if_d3;\n wire [3:0]if_d4;\n wire [3:0]if_d5;\n wire [3:0]if_d6;\n wire [3:0]if_d7;\n wire [3:0]if_d8;\n wire if_empty_;\n wire [0:0]if_empty_r;\n wire [0:0]if_empty_r_0;\n wire ififo_rst;\n wire ififo_wr_enable;\n wire \\in_fifo_gen.in_fifo_n_0 ;\n wire \\in_fifo_gen.in_fifo_n_1 ;\n wire \\in_fifo_gen.in_fifo_n_3 ;\n wire init_calib_complete_reg_rep;\n wire iserdes_clkdiv;\n wire [7:0]mem_dq_in;\n wire [8:0]mem_dq_out;\n wire [8:0]mem_dq_ts;\n wire [0:0]mem_dqs_in;\n wire [0:0]mem_dqs_out;\n wire [0:0]mem_dqs_ts;\n wire mem_refclk;\n wire mux_wrdata_en;\n wire \\my_empty_reg[1] ;\n wire [0:0]\\my_empty_reg[4] ;\n wire [63:0]\\my_empty_reg[7] ;\n wire \\not_strict_mode.app_rd_data_reg[104] ;\n wire \\not_strict_mode.app_rd_data_reg[105] ;\n wire \\not_strict_mode.app_rd_data_reg[106] ;\n wire \\not_strict_mode.app_rd_data_reg[107] ;\n wire \\not_strict_mode.app_rd_data_reg[108] ;\n wire \\not_strict_mode.app_rd_data_reg[109] ;\n wire \\not_strict_mode.app_rd_data_reg[10] ;\n wire \\not_strict_mode.app_rd_data_reg[110] ;\n wire \\not_strict_mode.app_rd_data_reg[111] ;\n wire \\not_strict_mode.app_rd_data_reg[11] ;\n wire \\not_strict_mode.app_rd_data_reg[12] ;\n wire \\not_strict_mode.app_rd_data_reg[136] ;\n wire \\not_strict_mode.app_rd_data_reg[137] ;\n wire \\not_strict_mode.app_rd_data_reg[138] ;\n wire \\not_strict_mode.app_rd_data_reg[139] ;\n wire \\not_strict_mode.app_rd_data_reg[13] ;\n wire \\not_strict_mode.app_rd_data_reg[140] ;\n wire \\not_strict_mode.app_rd_data_reg[141] ;\n wire \\not_strict_mode.app_rd_data_reg[142] ;\n wire \\not_strict_mode.app_rd_data_reg[143] ;\n wire \\not_strict_mode.app_rd_data_reg[14] ;\n wire \\not_strict_mode.app_rd_data_reg[15] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[15]_0 ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[15]_1 ;\n wire \\not_strict_mode.app_rd_data_reg[168] ;\n wire \\not_strict_mode.app_rd_data_reg[169] ;\n wire \\not_strict_mode.app_rd_data_reg[170] ;\n wire \\not_strict_mode.app_rd_data_reg[171] ;\n wire \\not_strict_mode.app_rd_data_reg[172] ;\n wire \\not_strict_mode.app_rd_data_reg[173] ;\n wire \\not_strict_mode.app_rd_data_reg[174] ;\n wire \\not_strict_mode.app_rd_data_reg[175] ;\n wire \\not_strict_mode.app_rd_data_reg[200] ;\n wire \\not_strict_mode.app_rd_data_reg[201] ;\n wire \\not_strict_mode.app_rd_data_reg[202] ;\n wire \\not_strict_mode.app_rd_data_reg[203] ;\n wire \\not_strict_mode.app_rd_data_reg[204] ;\n wire \\not_strict_mode.app_rd_data_reg[205] ;\n wire \\not_strict_mode.app_rd_data_reg[206] ;\n wire \\not_strict_mode.app_rd_data_reg[207] ;\n wire \\not_strict_mode.app_rd_data_reg[232] ;\n wire \\not_strict_mode.app_rd_data_reg[233] ;\n wire \\not_strict_mode.app_rd_data_reg[234] ;\n wire \\not_strict_mode.app_rd_data_reg[235] ;\n wire \\not_strict_mode.app_rd_data_reg[236] ;\n wire \\not_strict_mode.app_rd_data_reg[236]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[237] ;\n wire \\not_strict_mode.app_rd_data_reg[238] ;\n wire [63:0]\\not_strict_mode.app_rd_data_reg[239] ;\n wire \\not_strict_mode.app_rd_data_reg[239]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[40] ;\n wire \\not_strict_mode.app_rd_data_reg[41] ;\n wire \\not_strict_mode.app_rd_data_reg[42] ;\n wire \\not_strict_mode.app_rd_data_reg[43] ;\n wire \\not_strict_mode.app_rd_data_reg[44] ;\n wire \\not_strict_mode.app_rd_data_reg[45] ;\n wire \\not_strict_mode.app_rd_data_reg[46] ;\n wire \\not_strict_mode.app_rd_data_reg[47] ;\n wire \\not_strict_mode.app_rd_data_reg[72] ;\n wire \\not_strict_mode.app_rd_data_reg[73] ;\n wire \\not_strict_mode.app_rd_data_reg[74] ;\n wire \\not_strict_mode.app_rd_data_reg[75] ;\n wire \\not_strict_mode.app_rd_data_reg[76] ;\n wire \\not_strict_mode.app_rd_data_reg[77] ;\n wire \\not_strict_mode.app_rd_data_reg[78] ;\n wire \\not_strict_mode.app_rd_data_reg[79] ;\n wire \\not_strict_mode.app_rd_data_reg[8] ;\n wire \\not_strict_mode.app_rd_data_reg[9] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n wire [7:0]of_d9;\n wire [39:0]of_dqbus;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ;\n wire ofifo_rst;\n wire oserdes_clk;\n wire oserdes_clk_delayed;\n wire oserdes_clkdiv;\n wire [1:0]oserdes_dq_ts;\n wire [1:0]oserdes_dqs;\n wire [1:0]oserdes_dqs_ts;\n wire out_fifo_n_0;\n wire out_fifo_n_1;\n wire out_fifo_n_2;\n wire out_fifo_n_3;\n wire [3:0]phaser_ctl_bus;\n wire \\phaser_in_gen.phaser_in_n_1 ;\n wire \\phaser_in_gen.phaser_in_n_2 ;\n wire \\phaser_in_gen.phaser_in_n_5 ;\n wire \\phaser_in_gen.phaser_in_n_7 ;\n wire phaser_out_n_0;\n wire phaser_out_n_1;\n wire [71:0]phy_dout;\n wire phy_if_reset;\n wire [0:0]\\pi_dqs_found_lanes_r1_reg[2] ;\n wire pi_en_stg2_f_reg;\n wire pi_phase_locked_all_r1_reg;\n wire pi_stg2_f_incdec_reg;\n wire [8:0]\\po_counter_read_val_reg[8] ;\n wire po_oserdes_rst;\n wire po_rd_enable;\n wire [79:0]rd_data;\n wire [71:6]rd_data_r;\n wire [1:0]\\rd_ptr_timing_reg[1] ;\n wire \\read_fifo.fifo_out_data_r_reg[6] ;\n wire rst_r4;\n wire sync_pulse;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[232] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[233] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[234] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[235] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[236] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[237] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[238] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[239] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[285] ;\n wire [7:4]\\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED ;\n wire [7:4]\\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED ;\n wire [7:4]NLW_out_fifo_Q5_UNCONNECTED;\n wire [7:4]NLW_out_fifo_Q6_UNCONNECTED;\n wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;\n\n ddr3_ifmig_7series_v4_0_ddr_byte_group_io__parameterized1 ddr_byte_group_io\n (.A_rst_primitives(A_rst_primitives),\n .A_rst_primitives_reg(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),\n .CLK(CLK),\n .CLKB0_8(CLKB0_8),\n .CTSBUS(oserdes_dqs_ts[0]),\n .D1(if_d1),\n .D2(if_d2),\n .D3(if_d3),\n .D4(if_d4),\n .D5(if_d5),\n .D6(if_d6),\n .D7(if_d7),\n .D8(if_d8),\n .DQSBUS(oserdes_dqs),\n .DTSBUS(oserdes_dq_ts),\n .LD0_4(LD0_4),\n .\\calib_sel_reg[1] (\\calib_sel_reg[1]_0 ),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\gen_byte_sel_div1.calib_in_common_reg_2 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_0 (\\gen_byte_sel_div1.calib_in_common_reg_3 ),\n .idelay_inc(idelay_inc),\n .idelay_ld_rst_1(idelay_ld_rst_1),\n .iserdes_clkdiv(iserdes_clkdiv),\n .mem_dq_in(mem_dq_in),\n .mem_dq_out(mem_dq_out),\n .mem_dq_ts(mem_dq_ts),\n .mem_dqs_out(mem_dqs_out),\n .mem_dqs_ts(mem_dqs_ts),\n .of_dqbus(of_dqbus[39:4]),\n .oserdes_clk(oserdes_clk),\n .oserdes_clk_delayed(oserdes_clk_delayed),\n .oserdes_clkdiv(oserdes_clkdiv),\n .po_oserdes_rst(po_oserdes_rst),\n .rst_r4(rst_r4));\n (* syn_maxfan = \"3\" *) \n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(if_empty_),\n .Q(if_empty_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[10]),\n .Q(rd_data_r[10]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[11]),\n .Q(rd_data_r[11]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[12]),\n .Q(rd_data_r[12]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[13]),\n .Q(rd_data_r[13]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[14]),\n .Q(rd_data_r[14]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[15]),\n .Q(rd_data_r[15]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[16]),\n .Q(rd_data_r[16]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[17]),\n .Q(rd_data_r[17]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[18]),\n .Q(rd_data_r[18]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[19]),\n .Q(rd_data_r[19]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[20]),\n .Q(rd_data_r[20]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[21]),\n .Q(rd_data_r[21]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[22]),\n .Q(rd_data_r[22]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[23]),\n .Q(rd_data_r[23]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[24]),\n .Q(rd_data_r[24]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[25]),\n .Q(rd_data_r[25]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[26]),\n .Q(rd_data_r[26]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[27]),\n .Q(rd_data_r[27]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[28]),\n .Q(rd_data_r[28]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[29]),\n .Q(rd_data_r[29]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[30]),\n .Q(rd_data_r[30]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[31]),\n .Q(rd_data_r[31]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[32]),\n .Q(rd_data_r[32]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[33]),\n .Q(rd_data_r[33]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[34]),\n .Q(rd_data_r[34]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[35]),\n .Q(rd_data_r[35]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[36]),\n .Q(rd_data_r[36]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[37]),\n .Q(rd_data_r[37]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[38]),\n .Q(rd_data_r[38]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[39]),\n .Q(rd_data_r[39]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[40]),\n .Q(rd_data_r[40]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[41]),\n .Q(rd_data_r[41]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[42]),\n .Q(rd_data_r[42]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[43]),\n .Q(rd_data_r[43]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[44]),\n .Q(rd_data_r[44]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[45]),\n .Q(rd_data_r[45]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[46]),\n .Q(rd_data_r[46]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[47]),\n .Q(rd_data_r[47]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[48]),\n .Q(rd_data_r[48]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[49]),\n .Q(rd_data_r[49]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[50]),\n .Q(rd_data_r[50]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[51]),\n .Q(rd_data_r[51]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[52]),\n .Q(rd_data_r[52]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[53]),\n .Q(rd_data_r[53]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[54]),\n .Q(rd_data_r[54]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[55]),\n .Q(rd_data_r[55]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[56]),\n .Q(rd_data_r[56]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[57]),\n .Q(rd_data_r[57]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[58]),\n .Q(rd_data_r[58]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[59]),\n .Q(rd_data_r[59]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[60]),\n .Q(rd_data_r[60]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[61]),\n .Q(rd_data_r[61]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[62]),\n .Q(rd_data_r[62]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[63]),\n .Q(rd_data_r[63]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[64]),\n .Q(rd_data_r[64]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[65]),\n .Q(rd_data_r[65]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[66]),\n .Q(rd_data_r[66]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[67]),\n .Q(rd_data_r[67]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[68]),\n .Q(rd_data_r[68]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[69]),\n .Q(rd_data_r[69]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[6]),\n .Q(rd_data_r[6]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[70]),\n .Q(rd_data_r[70]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[71]),\n .Q(rd_data_r[71]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[7]),\n .Q(rd_data_r[7]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[8]),\n .Q(\\not_strict_mode.app_rd_data_reg[15]_0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[9]),\n .Q(rd_data_r[9]),\n .R(1'b0));\n ddr3_ifmig_7series_v4_0_ddr_if_post_fifo_4 \\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo \n (.A_byte_rd_en(A_byte_rd_en),\n .CLK(CLK),\n .C_byte_rd_en(C_byte_rd_en),\n .D_byte_rd_en(D_byte_rd_en),\n .Q({rd_data_r[71:9],\\not_strict_mode.app_rd_data_reg[15]_0 ,rd_data_r[7:6]}),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (if_empty_r),\n .if_empty_r_0(if_empty_r_0),\n .ififo_rst(ififo_rst),\n .\\my_empty_reg[4]_0 (\\my_empty_reg[4] ),\n .\\not_strict_mode.app_rd_data_reg[104] (\\not_strict_mode.app_rd_data_reg[104] ),\n .\\not_strict_mode.app_rd_data_reg[105] (\\not_strict_mode.app_rd_data_reg[105] ),\n .\\not_strict_mode.app_rd_data_reg[106] (\\not_strict_mode.app_rd_data_reg[106] ),\n .\\not_strict_mode.app_rd_data_reg[107] (\\not_strict_mode.app_rd_data_reg[107] ),\n .\\not_strict_mode.app_rd_data_reg[108] (\\not_strict_mode.app_rd_data_reg[108] ),\n .\\not_strict_mode.app_rd_data_reg[109] (\\not_strict_mode.app_rd_data_reg[109] ),\n .\\not_strict_mode.app_rd_data_reg[10] (\\not_strict_mode.app_rd_data_reg[10] ),\n .\\not_strict_mode.app_rd_data_reg[110] (\\not_strict_mode.app_rd_data_reg[110] ),\n .\\not_strict_mode.app_rd_data_reg[111] (\\not_strict_mode.app_rd_data_reg[111] ),\n .\\not_strict_mode.app_rd_data_reg[11] (\\not_strict_mode.app_rd_data_reg[11] ),\n .\\not_strict_mode.app_rd_data_reg[12] (\\not_strict_mode.app_rd_data_reg[12] ),\n .\\not_strict_mode.app_rd_data_reg[136] (\\not_strict_mode.app_rd_data_reg[136] ),\n .\\not_strict_mode.app_rd_data_reg[137] (\\not_strict_mode.app_rd_data_reg[137] ),\n .\\not_strict_mode.app_rd_data_reg[138] (\\not_strict_mode.app_rd_data_reg[138] ),\n .\\not_strict_mode.app_rd_data_reg[139] (\\not_strict_mode.app_rd_data_reg[139] ),\n .\\not_strict_mode.app_rd_data_reg[13] (\\not_strict_mode.app_rd_data_reg[13] ),\n .\\not_strict_mode.app_rd_data_reg[140] (\\not_strict_mode.app_rd_data_reg[140] ),\n .\\not_strict_mode.app_rd_data_reg[141] (\\not_strict_mode.app_rd_data_reg[141] ),\n .\\not_strict_mode.app_rd_data_reg[142] (\\not_strict_mode.app_rd_data_reg[142] ),\n .\\not_strict_mode.app_rd_data_reg[143] (\\not_strict_mode.app_rd_data_reg[143] ),\n .\\not_strict_mode.app_rd_data_reg[14] (\\not_strict_mode.app_rd_data_reg[14] ),\n .\\not_strict_mode.app_rd_data_reg[15] (\\not_strict_mode.app_rd_data_reg[15] ),\n .\\not_strict_mode.app_rd_data_reg[15]_0 (\\not_strict_mode.app_rd_data_reg[15]_1 ),\n .\\not_strict_mode.app_rd_data_reg[168] (\\not_strict_mode.app_rd_data_reg[168] ),\n .\\not_strict_mode.app_rd_data_reg[169] (\\not_strict_mode.app_rd_data_reg[169] ),\n .\\not_strict_mode.app_rd_data_reg[170] (\\not_strict_mode.app_rd_data_reg[170] ),\n .\\not_strict_mode.app_rd_data_reg[171] (\\not_strict_mode.app_rd_data_reg[171] ),\n .\\not_strict_mode.app_rd_data_reg[172] (\\not_strict_mode.app_rd_data_reg[172] ),\n .\\not_strict_mode.app_rd_data_reg[173] (\\not_strict_mode.app_rd_data_reg[173] ),\n .\\not_strict_mode.app_rd_data_reg[174] (\\not_strict_mode.app_rd_data_reg[174] ),\n .\\not_strict_mode.app_rd_data_reg[175] (\\not_strict_mode.app_rd_data_reg[175] ),\n .\\not_strict_mode.app_rd_data_reg[200] (\\not_strict_mode.app_rd_data_reg[200] ),\n .\\not_strict_mode.app_rd_data_reg[201] (\\not_strict_mode.app_rd_data_reg[201] ),\n .\\not_strict_mode.app_rd_data_reg[202] (\\not_strict_mode.app_rd_data_reg[202] ),\n .\\not_strict_mode.app_rd_data_reg[203] (\\not_strict_mode.app_rd_data_reg[203] ),\n .\\not_strict_mode.app_rd_data_reg[204] (\\not_strict_mode.app_rd_data_reg[204] ),\n .\\not_strict_mode.app_rd_data_reg[205] (\\not_strict_mode.app_rd_data_reg[205] ),\n .\\not_strict_mode.app_rd_data_reg[206] (\\not_strict_mode.app_rd_data_reg[206] ),\n .\\not_strict_mode.app_rd_data_reg[207] (\\not_strict_mode.app_rd_data_reg[207] ),\n .\\not_strict_mode.app_rd_data_reg[232] (\\not_strict_mode.app_rd_data_reg[232] ),\n .\\not_strict_mode.app_rd_data_reg[233] (\\not_strict_mode.app_rd_data_reg[233] ),\n .\\not_strict_mode.app_rd_data_reg[234] (\\not_strict_mode.app_rd_data_reg[234] ),\n .\\not_strict_mode.app_rd_data_reg[235] (\\not_strict_mode.app_rd_data_reg[235] ),\n .\\not_strict_mode.app_rd_data_reg[236] (\\not_strict_mode.app_rd_data_reg[236] ),\n .\\not_strict_mode.app_rd_data_reg[236]_0 (\\not_strict_mode.app_rd_data_reg[236]_0 ),\n .\\not_strict_mode.app_rd_data_reg[237] (\\not_strict_mode.app_rd_data_reg[237] ),\n .\\not_strict_mode.app_rd_data_reg[238] (\\not_strict_mode.app_rd_data_reg[238] ),\n .\\not_strict_mode.app_rd_data_reg[239] (\\not_strict_mode.app_rd_data_reg[239] ),\n .\\not_strict_mode.app_rd_data_reg[239]_0 (\\not_strict_mode.app_rd_data_reg[239]_0 ),\n .\\not_strict_mode.app_rd_data_reg[40] (\\not_strict_mode.app_rd_data_reg[40] ),\n .\\not_strict_mode.app_rd_data_reg[41] (\\not_strict_mode.app_rd_data_reg[41] ),\n .\\not_strict_mode.app_rd_data_reg[42] (\\not_strict_mode.app_rd_data_reg[42] ),\n .\\not_strict_mode.app_rd_data_reg[43] (\\not_strict_mode.app_rd_data_reg[43] ),\n .\\not_strict_mode.app_rd_data_reg[44] (\\not_strict_mode.app_rd_data_reg[44] ),\n .\\not_strict_mode.app_rd_data_reg[45] (\\not_strict_mode.app_rd_data_reg[45] ),\n .\\not_strict_mode.app_rd_data_reg[46] (\\not_strict_mode.app_rd_data_reg[46] ),\n .\\not_strict_mode.app_rd_data_reg[47] (\\not_strict_mode.app_rd_data_reg[47] ),\n .\\not_strict_mode.app_rd_data_reg[72] (\\not_strict_mode.app_rd_data_reg[72] ),\n .\\not_strict_mode.app_rd_data_reg[73] (\\not_strict_mode.app_rd_data_reg[73] ),\n .\\not_strict_mode.app_rd_data_reg[74] (\\not_strict_mode.app_rd_data_reg[74] ),\n .\\not_strict_mode.app_rd_data_reg[75] (\\not_strict_mode.app_rd_data_reg[75] ),\n .\\not_strict_mode.app_rd_data_reg[76] (\\not_strict_mode.app_rd_data_reg[76] ),\n .\\not_strict_mode.app_rd_data_reg[77] (\\not_strict_mode.app_rd_data_reg[77] ),\n .\\not_strict_mode.app_rd_data_reg[78] (\\not_strict_mode.app_rd_data_reg[78] ),\n .\\not_strict_mode.app_rd_data_reg[79] (\\not_strict_mode.app_rd_data_reg[79] ),\n .\\not_strict_mode.app_rd_data_reg[8] (\\not_strict_mode.app_rd_data_reg[8] ),\n .\\not_strict_mode.app_rd_data_reg[9] (\\not_strict_mode.app_rd_data_reg[9] ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ),\n .phy_if_empty_r_reg(\\rd_ptr_timing_reg[1] [0]),\n .\\rd_ptr_timing_reg[1]_0 (\\rd_ptr_timing_reg[1] [1]),\n .\\read_fifo.fifo_out_data_r_reg[6] (\\read_fifo.fifo_out_data_r_reg[6] ));\n FDSE #(\n .INIT(1'b1)) \n ififo_rst_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .Q(ififo_rst),\n .S(phy_if_reset));\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n IN_FIFO #(\n .ALMOST_EMPTY_VALUE(1),\n .ALMOST_FULL_VALUE(1),\n .ARRAY_MODE(\"ARRAY_MODE_4_X_8\"),\n .SYNCHRONOUS_MODE(\"FALSE\")) \n \\in_fifo_gen.in_fifo \n (.ALMOSTEMPTY(\\in_fifo_gen.in_fifo_n_0 ),\n .ALMOSTFULL(\\in_fifo_gen.in_fifo_n_1 ),\n .D0({1'b0,1'b0,1'b0,1'b0}),\n .D1(if_d1),\n .D2(if_d2),\n .D3(if_d3),\n .D4(if_d4),\n .D5({\\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED [7:4],if_d5}),\n .D6({\\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED [7:4],if_d6}),\n .D7(if_d7),\n .D8(if_d8),\n .D9({1'b0,1'b0,1'b0,1'b0}),\n .EMPTY(if_empty_),\n .FULL(\\in_fifo_gen.in_fifo_n_3 ),\n .Q0(rd_data[7:0]),\n .Q1(rd_data[15:8]),\n .Q2(rd_data[23:16]),\n .Q3(rd_data[31:24]),\n .Q4(rd_data[39:32]),\n .Q5(rd_data[47:40]),\n .Q6(rd_data[55:48]),\n .Q7(rd_data[63:56]),\n .Q8(rd_data[71:64]),\n .Q9(rd_data[79:72]),\n .RDCLK(CLK),\n .RDEN(1'b1),\n .RESET(ififo_rst),\n .WRCLK(iserdes_clkdiv),\n .WREN(ififo_wr_enable));\n ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized4 \\of_pre_fifo_gen.u_ddr_of_pre_fifo \n (.CLK(CLK),\n .D0({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }),\n .D9(of_d9),\n .Q(Q),\n .init_calib_complete_reg_rep(init_calib_complete_reg_rep),\n .mux_wrdata_en(mux_wrdata_en),\n .\\my_empty_reg[1]_0 (\\my_empty_reg[1] ),\n .\\my_empty_reg[7]_0 (\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ),\n .\\my_empty_reg[7]_1 (\\my_empty_reg[7] ),\n .ofifo_rst(ofifo_rst),\n .ofifo_rst_reg(out_fifo_n_3),\n .phy_dout(phy_dout),\n .\\write_buffer.wr_buf_out_data_reg[285] (\\write_buffer.wr_buf_out_data_reg[285] ));\n FDSE #(\n .INIT(1'b1)) \n ofifo_rst_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .Q(ofifo_rst),\n .S(A_rst_primitives));\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n OUT_FIFO #(\n .ALMOST_EMPTY_VALUE(1),\n .ALMOST_FULL_VALUE(1),\n .ARRAY_MODE(\"ARRAY_MODE_8_X_4\"),\n .OUTPUT_DISABLE(\"FALSE\"),\n .SYNCHRONOUS_MODE(\"FALSE\")) \n out_fifo\n (.ALMOSTEMPTY(out_fifo_n_0),\n .ALMOSTFULL(out_fifo_n_1),\n .D0({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }),\n .D1(\\write_buffer.wr_buf_out_data_reg[239] ),\n .D2(\\write_buffer.wr_buf_out_data_reg[238] ),\n .D3(\\write_buffer.wr_buf_out_data_reg[237] ),\n .D4(\\write_buffer.wr_buf_out_data_reg[236] ),\n .D5(\\write_buffer.wr_buf_out_data_reg[235] ),\n .D6(\\write_buffer.wr_buf_out_data_reg[234] ),\n .D7(\\write_buffer.wr_buf_out_data_reg[233] ),\n .D8(\\write_buffer.wr_buf_out_data_reg[232] ),\n .D9(of_d9),\n .EMPTY(out_fifo_n_2),\n .FULL(out_fifo_n_3),\n .Q0(of_dqbus[3:0]),\n .Q1(of_dqbus[7:4]),\n .Q2(of_dqbus[11:8]),\n .Q3(of_dqbus[15:12]),\n .Q4(of_dqbus[19:16]),\n .Q5({NLW_out_fifo_Q5_UNCONNECTED[7:4],of_dqbus[23:20]}),\n .Q6({NLW_out_fifo_Q6_UNCONNECTED[7:4],of_dqbus[27:24]}),\n .Q7(of_dqbus[31:28]),\n .Q8(of_dqbus[35:32]),\n .Q9(of_dqbus[39:36]),\n .RDCLK(oserdes_clkdiv),\n .RDEN(po_rd_enable),\n .RESET(ofifo_rst),\n .WRCLK(CLK),\n .WREN(\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ));\n (* box_type = \"PRIMITIVE\" *) \n PHASER_IN_PHY #(\n .BURST_MODE(\"TRUE\"),\n .CLKOUT_DIV(2),\n .DQS_AUTO_RECAL(1'b1),\n .DQS_BIAS_MODE(\"FALSE\"),\n .DQS_FIND_PATTERN(3'b000),\n .FINE_DELAY(33),\n .FREQ_REF_DIV(\"NONE\"),\n .IS_RST_INVERTED(1'b0),\n .MEMREFCLK_PERIOD(1.112000),\n .OUTPUT_CLK_SRC(\"DELAYED_REF\"),\n .PHASEREFCLK_PERIOD(1.112000),\n .REFCLK_PERIOD(1.112000),\n .SEL_CLK_OFFSET(6),\n .SYNC_IN_DIV_RST(\"TRUE\"),\n .WR_CYCLES(\"FALSE\")) \n \\phaser_in_gen.phaser_in \n (.BURSTPENDINGPHY(phaser_ctl_bus[1]),\n .COUNTERLOADEN(\\gen_byte_sel_div1.calib_in_common_reg ),\n .COUNTERLOADVAL(\\calib_zero_inputs_reg[0] ),\n .COUNTERREADEN(\\calib_sel_reg[1] ),\n .COUNTERREADVAL(COUNTERREADVAL),\n .DQSFOUND(\\pi_dqs_found_lanes_r1_reg[2] ),\n .DQSOUTOFRANGE(\\phaser_in_gen.phaser_in_n_1 ),\n .ENCALIBPHY(PCENABLECALIB),\n .FINEENABLE(pi_en_stg2_f_reg),\n .FINEINC(pi_stg2_f_incdec_reg),\n .FINEOVERFLOW(\\phaser_in_gen.phaser_in_n_2 ),\n .FREQREFCLK(freq_refclk),\n .ICLK(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),\n .ICLKDIV(iserdes_clkdiv),\n .ISERDESRST(\\phaser_in_gen.phaser_in_n_5 ),\n .MEMREFCLK(mem_refclk),\n .PHASELOCKED(pi_phase_locked_all_r1_reg),\n .PHASEREFCLK(mem_dqs_in),\n .RANKSELPHY(phaser_ctl_bus[3:2]),\n .RCLK(\\phaser_in_gen.phaser_in_n_7 ),\n .RST(A_rst_primitives),\n .RSTDQSFIND(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .SYNCIN(sync_pulse),\n .SYSCLK(CLK),\n .WRENABLE(ififo_wr_enable));\n (* box_type = \"PRIMITIVE\" *) \n PHASER_OUT_PHY #(\n .CLKOUT_DIV(2),\n .COARSE_BYPASS(\"FALSE\"),\n .COARSE_DELAY(0),\n .DATA_CTL_N(\"TRUE\"),\n .DATA_RD_CYCLES(\"FALSE\"),\n .FINE_DELAY(60),\n .IS_RST_INVERTED(1'b0),\n .MEMREFCLK_PERIOD(1.111111),\n .OCLKDELAY_INV(\"TRUE\"),\n .OCLK_DELAY(28),\n .OUTPUT_CLK_SRC(\"DELAYED_REF\"),\n .PHASEREFCLK_PERIOD(1.000000),\n .PO(3'b111),\n .REFCLK_PERIOD(1.112000),\n .SYNC_IN_DIV_RST(\"TRUE\")) \n phaser_out\n (.BURSTPENDINGPHY(phaser_ctl_bus[0]),\n .COARSEENABLE(\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .COARSEINC(\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .COARSEOVERFLOW(phaser_out_n_0),\n .COUNTERLOADEN(1'b0),\n .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .COUNTERREADEN(\\calib_sel_reg[1] ),\n .COUNTERREADVAL(\\po_counter_read_val_reg[8] ),\n .CTSBUS(oserdes_dqs_ts),\n .DQSBUS(oserdes_dqs),\n .DTSBUS(oserdes_dq_ts),\n .ENCALIBPHY(PCENABLECALIB),\n .FINEENABLE(ck_po_stg2_f_en_reg),\n .FINEINC(ck_po_stg2_f_indec_reg),\n .FINEOVERFLOW(phaser_out_n_1),\n .FREQREFCLK(freq_refclk),\n .MEMREFCLK(mem_refclk),\n .OCLK(oserdes_clk),\n .OCLKDELAYED(oserdes_clk_delayed),\n .OCLKDIV(oserdes_clkdiv),\n .OSERDESRST(po_oserdes_rst),\n .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),\n .RDENABLE(po_rd_enable),\n .RST(A_rst_primitives),\n .SELFINEOCLKDELAY(delay_done_r4_reg),\n .SYNCIN(sync_pulse),\n .SYSCLK(CLK));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_byte_lane\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_byte_lane__parameterized2\n (\\pi_dqs_found_lanes_r1_reg[3] ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,\n pi_phase_locked_all_r1_reg,\n mem_dqs_out,\n mem_dqs_ts,\n mem_dq_out,\n mem_dq_ts,\n idelay_ld_rst_2,\n \\not_strict_mode.app_rd_data_reg[228] ,\n \\my_empty_reg[1] ,\n \\not_strict_mode.app_rd_data_reg[231] ,\n \\not_strict_mode.app_rd_data_reg[0] ,\n \\not_strict_mode.app_rd_data_reg[1] ,\n \\not_strict_mode.app_rd_data_reg[2] ,\n \\not_strict_mode.app_rd_data_reg[3] ,\n \\not_strict_mode.app_rd_data_reg[4] ,\n \\not_strict_mode.app_rd_data_reg[5] ,\n \\not_strict_mode.app_rd_data_reg[6] ,\n \\not_strict_mode.app_rd_data_reg[7] ,\n \\not_strict_mode.app_rd_data_reg[32] ,\n \\not_strict_mode.app_rd_data_reg[33] ,\n \\not_strict_mode.app_rd_data_reg[34] ,\n \\not_strict_mode.app_rd_data_reg[35] ,\n \\not_strict_mode.app_rd_data_reg[36] ,\n \\not_strict_mode.app_rd_data_reg[37] ,\n \\not_strict_mode.app_rd_data_reg[38] ,\n \\not_strict_mode.app_rd_data_reg[39] ,\n \\not_strict_mode.app_rd_data_reg[64] ,\n \\not_strict_mode.app_rd_data_reg[65] ,\n \\not_strict_mode.app_rd_data_reg[66] ,\n \\not_strict_mode.app_rd_data_reg[67] ,\n \\not_strict_mode.app_rd_data_reg[68] ,\n \\not_strict_mode.app_rd_data_reg[69] ,\n \\not_strict_mode.app_rd_data_reg[70] ,\n \\not_strict_mode.app_rd_data_reg[71] ,\n \\not_strict_mode.app_rd_data_reg[96] ,\n \\not_strict_mode.app_rd_data_reg[97] ,\n \\not_strict_mode.app_rd_data_reg[98] ,\n \\not_strict_mode.app_rd_data_reg[99] ,\n \\not_strict_mode.app_rd_data_reg[100] ,\n \\not_strict_mode.app_rd_data_reg[101] ,\n \\not_strict_mode.app_rd_data_reg[102] ,\n \\not_strict_mode.app_rd_data_reg[103] ,\n \\not_strict_mode.app_rd_data_reg[128] ,\n \\not_strict_mode.app_rd_data_reg[129] ,\n \\not_strict_mode.app_rd_data_reg[130] ,\n \\not_strict_mode.app_rd_data_reg[131] ,\n \\not_strict_mode.app_rd_data_reg[132] ,\n \\not_strict_mode.app_rd_data_reg[133] ,\n \\not_strict_mode.app_rd_data_reg[134] ,\n \\not_strict_mode.app_rd_data_reg[135] ,\n \\not_strict_mode.app_rd_data_reg[160] ,\n \\not_strict_mode.app_rd_data_reg[161] ,\n \\not_strict_mode.app_rd_data_reg[162] ,\n \\not_strict_mode.app_rd_data_reg[163] ,\n \\not_strict_mode.app_rd_data_reg[164] ,\n \\not_strict_mode.app_rd_data_reg[165] ,\n \\not_strict_mode.app_rd_data_reg[166] ,\n \\not_strict_mode.app_rd_data_reg[167] ,\n \\not_strict_mode.app_rd_data_reg[192] ,\n \\not_strict_mode.app_rd_data_reg[193] ,\n \\not_strict_mode.app_rd_data_reg[194] ,\n \\not_strict_mode.app_rd_data_reg[195] ,\n \\not_strict_mode.app_rd_data_reg[196] ,\n \\not_strict_mode.app_rd_data_reg[197] ,\n \\not_strict_mode.app_rd_data_reg[198] ,\n \\not_strict_mode.app_rd_data_reg[199] ,\n \\not_strict_mode.app_rd_data_reg[224] ,\n \\not_strict_mode.app_rd_data_reg[225] ,\n \\not_strict_mode.app_rd_data_reg[226] ,\n \\not_strict_mode.app_rd_data_reg[227] ,\n \\not_strict_mode.app_rd_data_reg[228]_0 ,\n \\not_strict_mode.app_rd_data_reg[229] ,\n \\not_strict_mode.app_rd_data_reg[230] ,\n \\not_strict_mode.app_rd_data_reg[231]_0 ,\n mux_rd_valid_r_reg,\n \\not_strict_mode.app_rd_data_reg[7]_0 ,\n \\not_strict_mode.app_rd_data_reg[7]_1 ,\n \\my_empty_reg[7] ,\n D_byte_rd_en,\n D,\n \\po_counter_read_val_reg[8] ,\n Q,\n phaser_ctl_bus,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n \\calib_sel_reg[0] ,\n pi_en_stg2_f_reg,\n pi_stg2_f_incdec_reg,\n freq_refclk,\n mem_refclk,\n mem_dqs_in,\n A_rst_primitives,\n \\gen_byte_sel_div1.calib_in_common_reg_0 ,\n sync_pulse,\n CLK,\n PCENABLECALIB,\n \\calib_zero_inputs_reg[0] ,\n \\gen_byte_sel_div1.calib_in_common_reg_1 ,\n ck_po_stg2_f_en_reg,\n ck_po_stg2_f_indec_reg,\n delay_done_r4_reg,\n \\write_buffer.wr_buf_out_data_reg[231] ,\n \\write_buffer.wr_buf_out_data_reg[230] ,\n \\write_buffer.wr_buf_out_data_reg[229] ,\n \\write_buffer.wr_buf_out_data_reg[228] ,\n \\write_buffer.wr_buf_out_data_reg[227] ,\n \\write_buffer.wr_buf_out_data_reg[226] ,\n \\write_buffer.wr_buf_out_data_reg[225] ,\n \\write_buffer.wr_buf_out_data_reg[224] ,\n \\gen_byte_sel_div1.calib_in_common_reg_2 ,\n mem_dq_in,\n idelay_inc,\n LD0_5,\n CLKB0_9,\n phy_if_reset,\n mux_wrdata_en,\n rst_r4,\n init_calib_complete_reg_rep,\n \\write_buffer.wr_buf_out_data_reg[284] ,\n \\read_fifo.fifo_out_data_r_reg[6] ,\n DOC,\n DOB,\n DOA,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,\n \\my_empty_reg[4] ,\n if_empty_r,\n phy_dout,\n \\gen_byte_sel_div1.calib_in_common_reg_3 ,\n \\calib_sel_reg[0]_0 ,\n C_byte_rd_en,\n A_byte_rd_en,\n if_empty_r_0,\n \\my_empty_reg[4]_0 ,\n COUNTERREADVAL,\n \\calib_sel_reg[1] ,\n A_rst_primitives_reg,\n A_rst_primitives_reg_0,\n A_rst_primitives_reg_1,\n A_rst_primitives_reg_2,\n A_rst_primitives_reg_3);\n output [0:0]\\pi_dqs_found_lanes_r1_reg[3] ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n output pi_phase_locked_all_r1_reg;\n output [0:0]mem_dqs_out;\n output [0:0]mem_dqs_ts;\n output [8:0]mem_dq_out;\n output [8:0]mem_dq_ts;\n output idelay_ld_rst_2;\n output \\not_strict_mode.app_rd_data_reg[228] ;\n output \\my_empty_reg[1] ;\n output [63:0]\\not_strict_mode.app_rd_data_reg[231] ;\n output \\not_strict_mode.app_rd_data_reg[0] ;\n output \\not_strict_mode.app_rd_data_reg[1] ;\n output \\not_strict_mode.app_rd_data_reg[2] ;\n output \\not_strict_mode.app_rd_data_reg[3] ;\n output \\not_strict_mode.app_rd_data_reg[4] ;\n output \\not_strict_mode.app_rd_data_reg[5] ;\n output \\not_strict_mode.app_rd_data_reg[6] ;\n output \\not_strict_mode.app_rd_data_reg[7] ;\n output \\not_strict_mode.app_rd_data_reg[32] ;\n output \\not_strict_mode.app_rd_data_reg[33] ;\n output \\not_strict_mode.app_rd_data_reg[34] ;\n output \\not_strict_mode.app_rd_data_reg[35] ;\n output \\not_strict_mode.app_rd_data_reg[36] ;\n output \\not_strict_mode.app_rd_data_reg[37] ;\n output \\not_strict_mode.app_rd_data_reg[38] ;\n output \\not_strict_mode.app_rd_data_reg[39] ;\n output \\not_strict_mode.app_rd_data_reg[64] ;\n output \\not_strict_mode.app_rd_data_reg[65] ;\n output \\not_strict_mode.app_rd_data_reg[66] ;\n output \\not_strict_mode.app_rd_data_reg[67] ;\n output \\not_strict_mode.app_rd_data_reg[68] ;\n output \\not_strict_mode.app_rd_data_reg[69] ;\n output \\not_strict_mode.app_rd_data_reg[70] ;\n output \\not_strict_mode.app_rd_data_reg[71] ;\n output \\not_strict_mode.app_rd_data_reg[96] ;\n output \\not_strict_mode.app_rd_data_reg[97] ;\n output \\not_strict_mode.app_rd_data_reg[98] ;\n output \\not_strict_mode.app_rd_data_reg[99] ;\n output \\not_strict_mode.app_rd_data_reg[100] ;\n output \\not_strict_mode.app_rd_data_reg[101] ;\n output \\not_strict_mode.app_rd_data_reg[102] ;\n output \\not_strict_mode.app_rd_data_reg[103] ;\n output \\not_strict_mode.app_rd_data_reg[128] ;\n output \\not_strict_mode.app_rd_data_reg[129] ;\n output \\not_strict_mode.app_rd_data_reg[130] ;\n output \\not_strict_mode.app_rd_data_reg[131] ;\n output \\not_strict_mode.app_rd_data_reg[132] ;\n output \\not_strict_mode.app_rd_data_reg[133] ;\n output \\not_strict_mode.app_rd_data_reg[134] ;\n output \\not_strict_mode.app_rd_data_reg[135] ;\n output \\not_strict_mode.app_rd_data_reg[160] ;\n output \\not_strict_mode.app_rd_data_reg[161] ;\n output \\not_strict_mode.app_rd_data_reg[162] ;\n output \\not_strict_mode.app_rd_data_reg[163] ;\n output \\not_strict_mode.app_rd_data_reg[164] ;\n output \\not_strict_mode.app_rd_data_reg[165] ;\n output \\not_strict_mode.app_rd_data_reg[166] ;\n output \\not_strict_mode.app_rd_data_reg[167] ;\n output \\not_strict_mode.app_rd_data_reg[192] ;\n output \\not_strict_mode.app_rd_data_reg[193] ;\n output \\not_strict_mode.app_rd_data_reg[194] ;\n output \\not_strict_mode.app_rd_data_reg[195] ;\n output \\not_strict_mode.app_rd_data_reg[196] ;\n output \\not_strict_mode.app_rd_data_reg[197] ;\n output \\not_strict_mode.app_rd_data_reg[198] ;\n output \\not_strict_mode.app_rd_data_reg[199] ;\n output \\not_strict_mode.app_rd_data_reg[224] ;\n output \\not_strict_mode.app_rd_data_reg[225] ;\n output \\not_strict_mode.app_rd_data_reg[226] ;\n output \\not_strict_mode.app_rd_data_reg[227] ;\n output \\not_strict_mode.app_rd_data_reg[228]_0 ;\n output \\not_strict_mode.app_rd_data_reg[229] ;\n output \\not_strict_mode.app_rd_data_reg[230] ;\n output \\not_strict_mode.app_rd_data_reg[231]_0 ;\n output mux_rd_valid_r_reg;\n output [0:0]\\not_strict_mode.app_rd_data_reg[7]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[7]_1 ;\n output [63:0]\\my_empty_reg[7] ;\n output D_byte_rd_en;\n output [5:0]D;\n output [8:0]\\po_counter_read_val_reg[8] ;\n output [2:0]Q;\n input [3:0]phaser_ctl_bus;\n input \\gen_byte_sel_div1.calib_in_common_reg ;\n input \\calib_sel_reg[0] ;\n input pi_en_stg2_f_reg;\n input pi_stg2_f_incdec_reg;\n input freq_refclk;\n input mem_refclk;\n input [0:0]mem_dqs_in;\n input A_rst_primitives;\n input \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n input sync_pulse;\n input CLK;\n input [1:0]PCENABLECALIB;\n input [5:0]\\calib_zero_inputs_reg[0] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n input ck_po_stg2_f_en_reg;\n input ck_po_stg2_f_indec_reg;\n input delay_done_r4_reg;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[231] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[230] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[229] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[228] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[227] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[226] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[225] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[224] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n input [7:0]mem_dq_in;\n input idelay_inc;\n input LD0_5;\n input CLKB0_9;\n input phy_if_reset;\n input mux_wrdata_en;\n input rst_r4;\n input init_calib_complete_reg_rep;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[284] ;\n input \\read_fifo.fifo_out_data_r_reg[6] ;\n input [1:0]DOC;\n input [1:0]DOB;\n input [1:0]DOA;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n input [0:0]\\my_empty_reg[4] ;\n input [0:0]if_empty_r;\n input [71:0]phy_dout;\n input [0:0]\\gen_byte_sel_div1.calib_in_common_reg_3 ;\n input [7:0]\\calib_sel_reg[0]_0 ;\n input C_byte_rd_en;\n input A_byte_rd_en;\n input [0:0]if_empty_r_0;\n input [0:0]\\my_empty_reg[4]_0 ;\n input [5:0]COUNTERREADVAL;\n input [1:0]\\calib_sel_reg[1] ;\n input [5:0]A_rst_primitives_reg;\n input [5:0]A_rst_primitives_reg_0;\n input [8:0]A_rst_primitives_reg_1;\n input [8:0]A_rst_primitives_reg_2;\n input [8:0]A_rst_primitives_reg_3;\n\n wire A_byte_rd_en;\n wire A_rst_primitives;\n wire [5:0]A_rst_primitives_reg;\n wire [5:0]A_rst_primitives_reg_0;\n wire [8:0]A_rst_primitives_reg_1;\n wire [8:0]A_rst_primitives_reg_2;\n wire [8:0]A_rst_primitives_reg_3;\n wire CLK;\n wire CLKB0_9;\n wire [5:0]COUNTERREADVAL;\n wire C_byte_rd_en;\n wire [5:0]D;\n wire [1:0]DOA;\n wire [1:0]DOB;\n wire [1:0]DOC;\n wire D_byte_rd_en;\n wire [5:0]D_pi_counter_read_val;\n wire [8:0]D_po_counter_read_val;\n wire LD0_5;\n wire [1:0]PCENABLECALIB;\n wire [2:0]Q;\n wire \\calib_sel_reg[0] ;\n wire [7:0]\\calib_sel_reg[0]_0 ;\n wire [1:0]\\calib_sel_reg[1] ;\n wire [5:0]\\calib_zero_inputs_reg[0] ;\n wire ck_po_stg2_f_en_reg;\n wire ck_po_stg2_f_indec_reg;\n wire delay_done_r4_reg;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n wire freq_refclk;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n wire [0:0]\\gen_byte_sel_div1.calib_in_common_reg_3 ;\n wire idelay_inc;\n wire idelay_ld_rst_2;\n wire [3:0]if_d1;\n wire [3:0]if_d2;\n wire [3:0]if_d3;\n wire [3:0]if_d4;\n wire [3:0]if_d5;\n wire [3:0]if_d6;\n wire [3:0]if_d7;\n wire [3:0]if_d8;\n wire if_empty_;\n wire [0:0]if_empty_r;\n wire [0:0]if_empty_r_0;\n wire [3:3]if_empty_r_1;\n wire ififo_rst;\n wire ififo_wr_enable;\n wire \\in_fifo_gen.in_fifo_n_0 ;\n wire \\in_fifo_gen.in_fifo_n_1 ;\n wire \\in_fifo_gen.in_fifo_n_3 ;\n wire init_calib_complete_reg_rep;\n wire iserdes_clkdiv;\n wire [7:0]mem_dq_in;\n wire [8:0]mem_dq_out;\n wire [8:0]mem_dq_ts;\n wire [0:0]mem_dqs_in;\n wire [0:0]mem_dqs_out;\n wire [0:0]mem_dqs_ts;\n wire mem_refclk;\n wire mux_rd_valid_r_reg;\n wire mux_wrdata_en;\n wire \\my_empty_reg[1] ;\n wire [0:0]\\my_empty_reg[4] ;\n wire [0:0]\\my_empty_reg[4]_0 ;\n wire [63:0]\\my_empty_reg[7] ;\n wire \\not_strict_mode.app_rd_data_reg[0] ;\n wire \\not_strict_mode.app_rd_data_reg[100] ;\n wire \\not_strict_mode.app_rd_data_reg[101] ;\n wire \\not_strict_mode.app_rd_data_reg[102] ;\n wire \\not_strict_mode.app_rd_data_reg[103] ;\n wire \\not_strict_mode.app_rd_data_reg[128] ;\n wire \\not_strict_mode.app_rd_data_reg[129] ;\n wire \\not_strict_mode.app_rd_data_reg[130] ;\n wire \\not_strict_mode.app_rd_data_reg[131] ;\n wire \\not_strict_mode.app_rd_data_reg[132] ;\n wire \\not_strict_mode.app_rd_data_reg[133] ;\n wire \\not_strict_mode.app_rd_data_reg[134] ;\n wire \\not_strict_mode.app_rd_data_reg[135] ;\n wire \\not_strict_mode.app_rd_data_reg[160] ;\n wire \\not_strict_mode.app_rd_data_reg[161] ;\n wire \\not_strict_mode.app_rd_data_reg[162] ;\n wire \\not_strict_mode.app_rd_data_reg[163] ;\n wire \\not_strict_mode.app_rd_data_reg[164] ;\n wire \\not_strict_mode.app_rd_data_reg[165] ;\n wire \\not_strict_mode.app_rd_data_reg[166] ;\n wire \\not_strict_mode.app_rd_data_reg[167] ;\n wire \\not_strict_mode.app_rd_data_reg[192] ;\n wire \\not_strict_mode.app_rd_data_reg[193] ;\n wire \\not_strict_mode.app_rd_data_reg[194] ;\n wire \\not_strict_mode.app_rd_data_reg[195] ;\n wire \\not_strict_mode.app_rd_data_reg[196] ;\n wire \\not_strict_mode.app_rd_data_reg[197] ;\n wire \\not_strict_mode.app_rd_data_reg[198] ;\n wire \\not_strict_mode.app_rd_data_reg[199] ;\n wire \\not_strict_mode.app_rd_data_reg[1] ;\n wire \\not_strict_mode.app_rd_data_reg[224] ;\n wire \\not_strict_mode.app_rd_data_reg[225] ;\n wire \\not_strict_mode.app_rd_data_reg[226] ;\n wire \\not_strict_mode.app_rd_data_reg[227] ;\n wire \\not_strict_mode.app_rd_data_reg[228] ;\n wire \\not_strict_mode.app_rd_data_reg[228]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[229] ;\n wire \\not_strict_mode.app_rd_data_reg[230] ;\n wire [63:0]\\not_strict_mode.app_rd_data_reg[231] ;\n wire \\not_strict_mode.app_rd_data_reg[231]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[2] ;\n wire \\not_strict_mode.app_rd_data_reg[32] ;\n wire \\not_strict_mode.app_rd_data_reg[33] ;\n wire \\not_strict_mode.app_rd_data_reg[34] ;\n wire \\not_strict_mode.app_rd_data_reg[35] ;\n wire \\not_strict_mode.app_rd_data_reg[36] ;\n wire \\not_strict_mode.app_rd_data_reg[37] ;\n wire \\not_strict_mode.app_rd_data_reg[38] ;\n wire \\not_strict_mode.app_rd_data_reg[39] ;\n wire \\not_strict_mode.app_rd_data_reg[3] ;\n wire \\not_strict_mode.app_rd_data_reg[4] ;\n wire \\not_strict_mode.app_rd_data_reg[5] ;\n wire \\not_strict_mode.app_rd_data_reg[64] ;\n wire \\not_strict_mode.app_rd_data_reg[65] ;\n wire \\not_strict_mode.app_rd_data_reg[66] ;\n wire \\not_strict_mode.app_rd_data_reg[67] ;\n wire \\not_strict_mode.app_rd_data_reg[68] ;\n wire \\not_strict_mode.app_rd_data_reg[69] ;\n wire \\not_strict_mode.app_rd_data_reg[6] ;\n wire \\not_strict_mode.app_rd_data_reg[70] ;\n wire \\not_strict_mode.app_rd_data_reg[71] ;\n wire \\not_strict_mode.app_rd_data_reg[7] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[7]_0 ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[7]_1 ;\n wire \\not_strict_mode.app_rd_data_reg[96] ;\n wire \\not_strict_mode.app_rd_data_reg[97] ;\n wire \\not_strict_mode.app_rd_data_reg[98] ;\n wire \\not_strict_mode.app_rd_data_reg[99] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n wire [7:0]of_d9;\n wire [39:0]of_dqbus;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ;\n wire ofifo_rst;\n wire oserdes_clk;\n wire oserdes_clk_delayed;\n wire oserdes_clkdiv;\n wire [1:0]oserdes_dq_ts;\n wire [1:0]oserdes_dqs;\n wire [1:0]oserdes_dqs_ts;\n wire out_fifo_n_0;\n wire out_fifo_n_1;\n wire out_fifo_n_2;\n wire out_fifo_n_3;\n wire [3:0]phaser_ctl_bus;\n wire \\phaser_in_gen.phaser_in_n_1 ;\n wire \\phaser_in_gen.phaser_in_n_2 ;\n wire \\phaser_in_gen.phaser_in_n_5 ;\n wire \\phaser_in_gen.phaser_in_n_7 ;\n wire phaser_out_n_0;\n wire phaser_out_n_1;\n wire [71:0]phy_dout;\n wire phy_if_reset;\n wire [0:0]\\pi_dqs_found_lanes_r1_reg[3] ;\n wire pi_en_stg2_f_reg;\n wire pi_phase_locked_all_r1_reg;\n wire pi_stg2_f_incdec_reg;\n wire [8:0]\\po_counter_read_val_reg[8] ;\n wire po_oserdes_rst;\n wire po_rd_enable;\n wire [79:0]rd_data;\n wire [71:6]rd_data_r;\n wire \\read_fifo.fifo_out_data_r_reg[6] ;\n wire rst_r4;\n wire sync_pulse;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[224] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[225] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[226] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[227] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[228] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[229] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[230] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[231] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[284] ;\n wire [7:4]\\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED ;\n wire [7:4]\\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED ;\n wire [7:4]NLW_out_fifo_Q5_UNCONNECTED;\n wire [7:4]NLW_out_fifo_Q6_UNCONNECTED;\n wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;\n\n ddr3_ifmig_7series_v4_0_ddr_byte_group_io__parameterized2 ddr_byte_group_io\n (.A_rst_primitives(A_rst_primitives),\n .A_rst_primitives_reg(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),\n .CLK(CLK),\n .CLKB0_9(CLKB0_9),\n .CTSBUS(oserdes_dqs_ts[0]),\n .D1(if_d1),\n .D2(if_d2),\n .D3(if_d3),\n .D4(if_d4),\n .D5(if_d5),\n .D6(if_d6),\n .D7(if_d7),\n .D8(if_d8),\n .DQSBUS(oserdes_dqs),\n .DTSBUS(oserdes_dq_ts),\n .LD0_5(LD0_5),\n .\\calib_sel_reg[0] (\\calib_sel_reg[0]_0 ),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\gen_byte_sel_div1.calib_in_common_reg_2 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_0 (\\gen_byte_sel_div1.calib_in_common_reg_3 ),\n .idelay_inc(idelay_inc),\n .idelay_ld_rst_2(idelay_ld_rst_2),\n .iserdes_clkdiv(iserdes_clkdiv),\n .mem_dq_in(mem_dq_in),\n .mem_dq_out(mem_dq_out),\n .mem_dq_ts(mem_dq_ts),\n .mem_dqs_out(mem_dqs_out),\n .mem_dqs_ts(mem_dqs_ts),\n .of_dqbus(of_dqbus[39:4]),\n .oserdes_clk(oserdes_clk),\n .oserdes_clk_delayed(oserdes_clk_delayed),\n .oserdes_clkdiv(oserdes_clkdiv),\n .po_oserdes_rst(po_oserdes_rst),\n .rst_r4(rst_r4));\n (* syn_maxfan = \"3\" *) \n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(if_empty_),\n .Q(if_empty_r_1),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[10]),\n .Q(rd_data_r[10]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[11]),\n .Q(rd_data_r[11]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[12]),\n .Q(rd_data_r[12]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[13]),\n .Q(rd_data_r[13]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[14]),\n .Q(rd_data_r[14]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[15]),\n .Q(rd_data_r[15]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[16]),\n .Q(rd_data_r[16]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[17]),\n .Q(rd_data_r[17]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[18]),\n .Q(rd_data_r[18]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[19]),\n .Q(rd_data_r[19]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[20]),\n .Q(rd_data_r[20]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[21]),\n .Q(rd_data_r[21]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[22]),\n .Q(rd_data_r[22]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[23]),\n .Q(rd_data_r[23]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[24]),\n .Q(rd_data_r[24]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[25]),\n .Q(rd_data_r[25]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[26]),\n .Q(rd_data_r[26]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[27]),\n .Q(rd_data_r[27]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[28]),\n .Q(rd_data_r[28]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[29]),\n .Q(rd_data_r[29]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[30]),\n .Q(rd_data_r[30]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[31]),\n .Q(rd_data_r[31]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[32]),\n .Q(rd_data_r[32]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[33]),\n .Q(rd_data_r[33]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[34]),\n .Q(rd_data_r[34]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[35]),\n .Q(rd_data_r[35]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[36]),\n .Q(rd_data_r[36]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[37]),\n .Q(rd_data_r[37]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[38]),\n .Q(rd_data_r[38]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[39]),\n .Q(rd_data_r[39]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[40]),\n .Q(rd_data_r[40]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[41]),\n .Q(rd_data_r[41]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[42]),\n .Q(rd_data_r[42]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[43]),\n .Q(rd_data_r[43]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[44]),\n .Q(rd_data_r[44]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[45]),\n .Q(rd_data_r[45]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[46]),\n .Q(rd_data_r[46]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[47]),\n .Q(rd_data_r[47]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[48]),\n .Q(rd_data_r[48]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[49]),\n .Q(rd_data_r[49]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[50]),\n .Q(rd_data_r[50]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[51]),\n .Q(rd_data_r[51]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[52]),\n .Q(rd_data_r[52]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[53]),\n .Q(rd_data_r[53]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[54]),\n .Q(rd_data_r[54]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[55]),\n .Q(rd_data_r[55]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[56]),\n .Q(rd_data_r[56]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[57]),\n .Q(rd_data_r[57]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[58]),\n .Q(rd_data_r[58]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[59]),\n .Q(rd_data_r[59]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[60]),\n .Q(rd_data_r[60]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[61]),\n .Q(rd_data_r[61]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[62]),\n .Q(rd_data_r[62]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[63]),\n .Q(rd_data_r[63]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[64]),\n .Q(rd_data_r[64]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[65]),\n .Q(rd_data_r[65]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[66]),\n .Q(rd_data_r[66]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[67]),\n .Q(rd_data_r[67]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[68]),\n .Q(rd_data_r[68]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[69]),\n .Q(rd_data_r[69]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[6]),\n .Q(rd_data_r[6]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[70]),\n .Q(rd_data_r[70]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[71]),\n .Q(rd_data_r[71]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[7]),\n .Q(rd_data_r[7]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[8]),\n .Q(\\not_strict_mode.app_rd_data_reg[7]_0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[9]),\n .Q(rd_data_r[9]),\n .R(1'b0));\n ddr3_ifmig_7series_v4_0_ddr_if_post_fifo \\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo \n (.A_byte_rd_en(A_byte_rd_en),\n .CLK(CLK),\n .C_byte_rd_en(C_byte_rd_en),\n .DOA(DOA),\n .DOB(DOB),\n .DOC(DOC),\n .D_byte_rd_en(D_byte_rd_en),\n .Q({rd_data_r[71:9],\\not_strict_mode.app_rd_data_reg[7]_0 ,rd_data_r[7:6]}),\n .if_empty_r(if_empty_r),\n .if_empty_r_0(if_empty_r_0),\n .if_empty_r_1(if_empty_r_1),\n .ififo_rst(ififo_rst),\n .mux_rd_valid_r_reg(mux_rd_valid_r_reg),\n .\\my_empty_reg[4]_0 (\\my_empty_reg[4] ),\n .\\my_empty_reg[4]_1 (\\my_empty_reg[4]_0 ),\n .\\not_strict_mode.app_rd_data_reg[0] (\\not_strict_mode.app_rd_data_reg[0] ),\n .\\not_strict_mode.app_rd_data_reg[100] (\\not_strict_mode.app_rd_data_reg[100] ),\n .\\not_strict_mode.app_rd_data_reg[101] (\\not_strict_mode.app_rd_data_reg[101] ),\n .\\not_strict_mode.app_rd_data_reg[102] (\\not_strict_mode.app_rd_data_reg[102] ),\n .\\not_strict_mode.app_rd_data_reg[103] (\\not_strict_mode.app_rd_data_reg[103] ),\n .\\not_strict_mode.app_rd_data_reg[128] (\\not_strict_mode.app_rd_data_reg[128] ),\n .\\not_strict_mode.app_rd_data_reg[129] (\\not_strict_mode.app_rd_data_reg[129] ),\n .\\not_strict_mode.app_rd_data_reg[130] (\\not_strict_mode.app_rd_data_reg[130] ),\n .\\not_strict_mode.app_rd_data_reg[131] (\\not_strict_mode.app_rd_data_reg[131] ),\n .\\not_strict_mode.app_rd_data_reg[132] (\\not_strict_mode.app_rd_data_reg[132] ),\n .\\not_strict_mode.app_rd_data_reg[133] (\\not_strict_mode.app_rd_data_reg[133] ),\n .\\not_strict_mode.app_rd_data_reg[134] (\\not_strict_mode.app_rd_data_reg[134] ),\n .\\not_strict_mode.app_rd_data_reg[135] (\\not_strict_mode.app_rd_data_reg[135] ),\n .\\not_strict_mode.app_rd_data_reg[160] (\\not_strict_mode.app_rd_data_reg[160] ),\n .\\not_strict_mode.app_rd_data_reg[161] (\\not_strict_mode.app_rd_data_reg[161] ),\n .\\not_strict_mode.app_rd_data_reg[162] (\\not_strict_mode.app_rd_data_reg[162] ),\n .\\not_strict_mode.app_rd_data_reg[163] (\\not_strict_mode.app_rd_data_reg[163] ),\n .\\not_strict_mode.app_rd_data_reg[164] (\\not_strict_mode.app_rd_data_reg[164] ),\n .\\not_strict_mode.app_rd_data_reg[165] (\\not_strict_mode.app_rd_data_reg[165] ),\n .\\not_strict_mode.app_rd_data_reg[166] (\\not_strict_mode.app_rd_data_reg[166] ),\n .\\not_strict_mode.app_rd_data_reg[167] (\\not_strict_mode.app_rd_data_reg[167] ),\n .\\not_strict_mode.app_rd_data_reg[192] (\\not_strict_mode.app_rd_data_reg[192] ),\n .\\not_strict_mode.app_rd_data_reg[193] (\\not_strict_mode.app_rd_data_reg[193] ),\n .\\not_strict_mode.app_rd_data_reg[194] (\\not_strict_mode.app_rd_data_reg[194] ),\n .\\not_strict_mode.app_rd_data_reg[195] (\\not_strict_mode.app_rd_data_reg[195] ),\n .\\not_strict_mode.app_rd_data_reg[196] (\\not_strict_mode.app_rd_data_reg[196] ),\n .\\not_strict_mode.app_rd_data_reg[197] (\\not_strict_mode.app_rd_data_reg[197] ),\n .\\not_strict_mode.app_rd_data_reg[198] (\\not_strict_mode.app_rd_data_reg[198] ),\n .\\not_strict_mode.app_rd_data_reg[199] (\\not_strict_mode.app_rd_data_reg[199] ),\n .\\not_strict_mode.app_rd_data_reg[1] (\\not_strict_mode.app_rd_data_reg[1] ),\n .\\not_strict_mode.app_rd_data_reg[224] (\\not_strict_mode.app_rd_data_reg[224] ),\n .\\not_strict_mode.app_rd_data_reg[225] (\\not_strict_mode.app_rd_data_reg[225] ),\n .\\not_strict_mode.app_rd_data_reg[226] (\\not_strict_mode.app_rd_data_reg[226] ),\n .\\not_strict_mode.app_rd_data_reg[227] (\\not_strict_mode.app_rd_data_reg[227] ),\n .\\not_strict_mode.app_rd_data_reg[228] (\\not_strict_mode.app_rd_data_reg[228] ),\n .\\not_strict_mode.app_rd_data_reg[228]_0 (\\not_strict_mode.app_rd_data_reg[228]_0 ),\n .\\not_strict_mode.app_rd_data_reg[229] (\\not_strict_mode.app_rd_data_reg[229] ),\n .\\not_strict_mode.app_rd_data_reg[230] (\\not_strict_mode.app_rd_data_reg[230] ),\n .\\not_strict_mode.app_rd_data_reg[231] (\\not_strict_mode.app_rd_data_reg[231] ),\n .\\not_strict_mode.app_rd_data_reg[231]_0 (\\not_strict_mode.app_rd_data_reg[231]_0 ),\n .\\not_strict_mode.app_rd_data_reg[2] (\\not_strict_mode.app_rd_data_reg[2] ),\n .\\not_strict_mode.app_rd_data_reg[32] (\\not_strict_mode.app_rd_data_reg[32] ),\n .\\not_strict_mode.app_rd_data_reg[33] (\\not_strict_mode.app_rd_data_reg[33] ),\n .\\not_strict_mode.app_rd_data_reg[34] (\\not_strict_mode.app_rd_data_reg[34] ),\n .\\not_strict_mode.app_rd_data_reg[35] (\\not_strict_mode.app_rd_data_reg[35] ),\n .\\not_strict_mode.app_rd_data_reg[36] (\\not_strict_mode.app_rd_data_reg[36] ),\n .\\not_strict_mode.app_rd_data_reg[37] (\\not_strict_mode.app_rd_data_reg[37] ),\n .\\not_strict_mode.app_rd_data_reg[38] (\\not_strict_mode.app_rd_data_reg[38] ),\n .\\not_strict_mode.app_rd_data_reg[39] (\\not_strict_mode.app_rd_data_reg[39] ),\n .\\not_strict_mode.app_rd_data_reg[3] (\\not_strict_mode.app_rd_data_reg[3] ),\n .\\not_strict_mode.app_rd_data_reg[4] (\\not_strict_mode.app_rd_data_reg[4] ),\n .\\not_strict_mode.app_rd_data_reg[5] (\\not_strict_mode.app_rd_data_reg[5] ),\n .\\not_strict_mode.app_rd_data_reg[64] (\\not_strict_mode.app_rd_data_reg[64] ),\n .\\not_strict_mode.app_rd_data_reg[65] (\\not_strict_mode.app_rd_data_reg[65] ),\n .\\not_strict_mode.app_rd_data_reg[66] (\\not_strict_mode.app_rd_data_reg[66] ),\n .\\not_strict_mode.app_rd_data_reg[67] (\\not_strict_mode.app_rd_data_reg[67] ),\n .\\not_strict_mode.app_rd_data_reg[68] (\\not_strict_mode.app_rd_data_reg[68] ),\n .\\not_strict_mode.app_rd_data_reg[69] (\\not_strict_mode.app_rd_data_reg[69] ),\n .\\not_strict_mode.app_rd_data_reg[6] (\\not_strict_mode.app_rd_data_reg[6] ),\n .\\not_strict_mode.app_rd_data_reg[70] (\\not_strict_mode.app_rd_data_reg[70] ),\n .\\not_strict_mode.app_rd_data_reg[71] (\\not_strict_mode.app_rd_data_reg[71] ),\n .\\not_strict_mode.app_rd_data_reg[7] (\\not_strict_mode.app_rd_data_reg[7] ),\n .\\not_strict_mode.app_rd_data_reg[7]_0 (\\not_strict_mode.app_rd_data_reg[7]_1 ),\n .\\not_strict_mode.app_rd_data_reg[96] (\\not_strict_mode.app_rd_data_reg[96] ),\n .\\not_strict_mode.app_rd_data_reg[97] (\\not_strict_mode.app_rd_data_reg[97] ),\n .\\not_strict_mode.app_rd_data_reg[98] (\\not_strict_mode.app_rd_data_reg[98] ),\n .\\not_strict_mode.app_rd_data_reg[99] (\\not_strict_mode.app_rd_data_reg[99] ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ),\n .\\read_fifo.fifo_out_data_r_reg[6] (\\read_fifo.fifo_out_data_r_reg[6] ));\n FDSE #(\n .INIT(1'b1)) \n ififo_rst_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .Q(ififo_rst),\n .S(phy_if_reset));\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n IN_FIFO #(\n .ALMOST_EMPTY_VALUE(1),\n .ALMOST_FULL_VALUE(1),\n .ARRAY_MODE(\"ARRAY_MODE_4_X_8\"),\n .SYNCHRONOUS_MODE(\"FALSE\")) \n \\in_fifo_gen.in_fifo \n (.ALMOSTEMPTY(\\in_fifo_gen.in_fifo_n_0 ),\n .ALMOSTFULL(\\in_fifo_gen.in_fifo_n_1 ),\n .D0({1'b0,1'b0,1'b0,1'b0}),\n .D1(if_d1),\n .D2(if_d2),\n .D3(if_d3),\n .D4(if_d4),\n .D5({\\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED [7:4],if_d5}),\n .D6({\\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED [7:4],if_d6}),\n .D7(if_d7),\n .D8(if_d8),\n .D9({1'b0,1'b0,1'b0,1'b0}),\n .EMPTY(if_empty_),\n .FULL(\\in_fifo_gen.in_fifo_n_3 ),\n .Q0(rd_data[7:0]),\n .Q1(rd_data[15:8]),\n .Q2(rd_data[23:16]),\n .Q3(rd_data[31:24]),\n .Q4(rd_data[39:32]),\n .Q5(rd_data[47:40]),\n .Q6(rd_data[55:48]),\n .Q7(rd_data[63:56]),\n .Q8(rd_data[71:64]),\n .Q9(rd_data[79:72]),\n .RDCLK(CLK),\n .RDEN(1'b1),\n .RESET(ififo_rst),\n .WRCLK(iserdes_clkdiv),\n .WREN(ififo_wr_enable));\n ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized5 \\of_pre_fifo_gen.u_ddr_of_pre_fifo \n (.CLK(CLK),\n .D0({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }),\n .D9(of_d9),\n .Q(Q),\n .init_calib_complete_reg_rep(init_calib_complete_reg_rep),\n .mux_wrdata_en(mux_wrdata_en),\n .\\my_empty_reg[1]_0 (\\my_empty_reg[1] ),\n .\\my_empty_reg[7]_0 (\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ),\n .\\my_empty_reg[7]_1 (\\my_empty_reg[7] ),\n .ofifo_rst(ofifo_rst),\n .ofifo_rst_reg(out_fifo_n_3),\n .phy_dout(phy_dout),\n .\\write_buffer.wr_buf_out_data_reg[284] (\\write_buffer.wr_buf_out_data_reg[284] ));\n FDSE #(\n .INIT(1'b1)) \n ofifo_rst_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .Q(ofifo_rst),\n .S(A_rst_primitives));\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n OUT_FIFO #(\n .ALMOST_EMPTY_VALUE(1),\n .ALMOST_FULL_VALUE(1),\n .ARRAY_MODE(\"ARRAY_MODE_8_X_4\"),\n .OUTPUT_DISABLE(\"FALSE\"),\n .SYNCHRONOUS_MODE(\"FALSE\")) \n out_fifo\n (.ALMOSTEMPTY(out_fifo_n_0),\n .ALMOSTFULL(out_fifo_n_1),\n .D0({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }),\n .D1(\\write_buffer.wr_buf_out_data_reg[231] ),\n .D2(\\write_buffer.wr_buf_out_data_reg[230] ),\n .D3(\\write_buffer.wr_buf_out_data_reg[229] ),\n .D4(\\write_buffer.wr_buf_out_data_reg[228] ),\n .D5(\\write_buffer.wr_buf_out_data_reg[227] ),\n .D6(\\write_buffer.wr_buf_out_data_reg[226] ),\n .D7(\\write_buffer.wr_buf_out_data_reg[225] ),\n .D8(\\write_buffer.wr_buf_out_data_reg[224] ),\n .D9(of_d9),\n .EMPTY(out_fifo_n_2),\n .FULL(out_fifo_n_3),\n .Q0(of_dqbus[3:0]),\n .Q1(of_dqbus[7:4]),\n .Q2(of_dqbus[11:8]),\n .Q3(of_dqbus[15:12]),\n .Q4(of_dqbus[19:16]),\n .Q5({NLW_out_fifo_Q5_UNCONNECTED[7:4],of_dqbus[23:20]}),\n .Q6({NLW_out_fifo_Q6_UNCONNECTED[7:4],of_dqbus[27:24]}),\n .Q7(of_dqbus[31:28]),\n .Q8(of_dqbus[35:32]),\n .Q9(of_dqbus[39:36]),\n .RDCLK(oserdes_clkdiv),\n .RDEN(po_rd_enable),\n .RESET(ofifo_rst),\n .WRCLK(CLK),\n .WREN(\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ));\n (* box_type = \"PRIMITIVE\" *) \n PHASER_IN_PHY #(\n .BURST_MODE(\"TRUE\"),\n .CLKOUT_DIV(2),\n .DQS_AUTO_RECAL(1'b1),\n .DQS_BIAS_MODE(\"FALSE\"),\n .DQS_FIND_PATTERN(3'b000),\n .FINE_DELAY(33),\n .FREQ_REF_DIV(\"NONE\"),\n .IS_RST_INVERTED(1'b0),\n .MEMREFCLK_PERIOD(1.112000),\n .OUTPUT_CLK_SRC(\"DELAYED_REF\"),\n .PHASEREFCLK_PERIOD(1.112000),\n .REFCLK_PERIOD(1.112000),\n .SEL_CLK_OFFSET(6),\n .SYNC_IN_DIV_RST(\"TRUE\"),\n .WR_CYCLES(\"FALSE\")) \n \\phaser_in_gen.phaser_in \n (.BURSTPENDINGPHY(phaser_ctl_bus[1]),\n .COUNTERLOADEN(\\gen_byte_sel_div1.calib_in_common_reg ),\n .COUNTERLOADVAL(\\calib_zero_inputs_reg[0] ),\n .COUNTERREADEN(\\calib_sel_reg[0] ),\n .COUNTERREADVAL(D_pi_counter_read_val),\n .DQSFOUND(\\pi_dqs_found_lanes_r1_reg[3] ),\n .DQSOUTOFRANGE(\\phaser_in_gen.phaser_in_n_1 ),\n .ENCALIBPHY(PCENABLECALIB),\n .FINEENABLE(pi_en_stg2_f_reg),\n .FINEINC(pi_stg2_f_incdec_reg),\n .FINEOVERFLOW(\\phaser_in_gen.phaser_in_n_2 ),\n .FREQREFCLK(freq_refclk),\n .ICLK(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),\n .ICLKDIV(iserdes_clkdiv),\n .ISERDESRST(\\phaser_in_gen.phaser_in_n_5 ),\n .MEMREFCLK(mem_refclk),\n .PHASELOCKED(pi_phase_locked_all_r1_reg),\n .PHASEREFCLK(mem_dqs_in),\n .RANKSELPHY(phaser_ctl_bus[3:2]),\n .RCLK(\\phaser_in_gen.phaser_in_n_7 ),\n .RST(A_rst_primitives),\n .RSTDQSFIND(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .SYNCIN(sync_pulse),\n .SYSCLK(CLK),\n .WRENABLE(ififo_wr_enable));\n (* box_type = \"PRIMITIVE\" *) \n PHASER_OUT_PHY #(\n .CLKOUT_DIV(2),\n .COARSE_BYPASS(\"FALSE\"),\n .COARSE_DELAY(0),\n .DATA_CTL_N(\"TRUE\"),\n .DATA_RD_CYCLES(\"FALSE\"),\n .FINE_DELAY(60),\n .IS_RST_INVERTED(1'b0),\n .MEMREFCLK_PERIOD(1.111111),\n .OCLKDELAY_INV(\"TRUE\"),\n .OCLK_DELAY(28),\n .OUTPUT_CLK_SRC(\"DELAYED_REF\"),\n .PHASEREFCLK_PERIOD(1.000000),\n .PO(3'b111),\n .REFCLK_PERIOD(1.112000),\n .SYNC_IN_DIV_RST(\"TRUE\")) \n phaser_out\n (.BURSTPENDINGPHY(phaser_ctl_bus[0]),\n .COARSEENABLE(\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .COARSEINC(\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .COARSEOVERFLOW(phaser_out_n_0),\n .COUNTERLOADEN(1'b0),\n .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .COUNTERREADEN(\\calib_sel_reg[0] ),\n .COUNTERREADVAL(D_po_counter_read_val),\n .CTSBUS(oserdes_dqs_ts),\n .DQSBUS(oserdes_dqs),\n .DTSBUS(oserdes_dq_ts),\n .ENCALIBPHY(PCENABLECALIB),\n .FINEENABLE(ck_po_stg2_f_en_reg),\n .FINEINC(ck_po_stg2_f_indec_reg),\n .FINEOVERFLOW(phaser_out_n_1),\n .FREQREFCLK(freq_refclk),\n .MEMREFCLK(mem_refclk),\n .OCLK(oserdes_clk),\n .OCLKDELAYED(oserdes_clk_delayed),\n .OCLKDIV(oserdes_clkdiv),\n .OSERDESRST(po_oserdes_rst),\n .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),\n .RDENABLE(po_rd_enable),\n .RST(A_rst_primitives),\n .SELFINEOCLKDELAY(delay_done_r4_reg),\n .SYNCIN(sync_pulse),\n .SYSCLK(CLK));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\pi_counter_read_val[0]_i_1 \n (.I0(D_pi_counter_read_val[0]),\n .I1(COUNTERREADVAL[0]),\n .I2(\\calib_sel_reg[1] [0]),\n .I3(A_rst_primitives_reg[0]),\n .I4(\\calib_sel_reg[1] [1]),\n .I5(A_rst_primitives_reg_0[0]),\n .O(D[0]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\pi_counter_read_val[1]_i_1 \n (.I0(D_pi_counter_read_val[1]),\n .I1(COUNTERREADVAL[1]),\n .I2(\\calib_sel_reg[1] [0]),\n .I3(A_rst_primitives_reg[1]),\n .I4(\\calib_sel_reg[1] [1]),\n .I5(A_rst_primitives_reg_0[1]),\n .O(D[1]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\pi_counter_read_val[2]_i_1 \n (.I0(D_pi_counter_read_val[2]),\n .I1(COUNTERREADVAL[2]),\n .I2(\\calib_sel_reg[1] [0]),\n .I3(A_rst_primitives_reg[2]),\n .I4(\\calib_sel_reg[1] [1]),\n .I5(A_rst_primitives_reg_0[2]),\n .O(D[2]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\pi_counter_read_val[3]_i_1 \n (.I0(D_pi_counter_read_val[3]),\n .I1(COUNTERREADVAL[3]),\n .I2(\\calib_sel_reg[1] [0]),\n .I3(A_rst_primitives_reg[3]),\n .I4(\\calib_sel_reg[1] [1]),\n .I5(A_rst_primitives_reg_0[3]),\n .O(D[3]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\pi_counter_read_val[4]_i_1 \n (.I0(D_pi_counter_read_val[4]),\n .I1(COUNTERREADVAL[4]),\n .I2(\\calib_sel_reg[1] [0]),\n .I3(A_rst_primitives_reg[4]),\n .I4(\\calib_sel_reg[1] [1]),\n .I5(A_rst_primitives_reg_0[4]),\n .O(D[4]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\pi_counter_read_val[5]_i_1 \n (.I0(D_pi_counter_read_val[5]),\n .I1(COUNTERREADVAL[5]),\n .I2(\\calib_sel_reg[1] [0]),\n .I3(A_rst_primitives_reg[5]),\n .I4(\\calib_sel_reg[1] [1]),\n .I5(A_rst_primitives_reg_0[5]),\n .O(D[5]));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[0]_i_1__0 \n (.I0(D_po_counter_read_val[0]),\n .I1(A_rst_primitives_reg_1[0]),\n .I2(A_rst_primitives_reg_2[0]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_3[0]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(\\po_counter_read_val_reg[8] [0]));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[1]_i_1__0 \n (.I0(D_po_counter_read_val[1]),\n .I1(A_rst_primitives_reg_1[1]),\n .I2(A_rst_primitives_reg_2[1]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_3[1]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(\\po_counter_read_val_reg[8] [1]));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[2]_i_1__0 \n (.I0(D_po_counter_read_val[2]),\n .I1(A_rst_primitives_reg_1[2]),\n .I2(A_rst_primitives_reg_2[2]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_3[2]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(\\po_counter_read_val_reg[8] [2]));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[3]_i_1__0 \n (.I0(D_po_counter_read_val[3]),\n .I1(A_rst_primitives_reg_1[3]),\n .I2(A_rst_primitives_reg_2[3]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_3[3]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(\\po_counter_read_val_reg[8] [3]));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[4]_i_1__0 \n (.I0(D_po_counter_read_val[4]),\n .I1(A_rst_primitives_reg_1[4]),\n .I2(A_rst_primitives_reg_2[4]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_3[4]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(\\po_counter_read_val_reg[8] [4]));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[5]_i_1__0 \n (.I0(D_po_counter_read_val[5]),\n .I1(A_rst_primitives_reg_1[5]),\n .I2(A_rst_primitives_reg_2[5]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_3[5]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(\\po_counter_read_val_reg[8] [5]));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[6]_i_1__0 \n (.I0(D_po_counter_read_val[6]),\n .I1(A_rst_primitives_reg_1[6]),\n .I2(A_rst_primitives_reg_2[6]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_3[6]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(\\po_counter_read_val_reg[8] [6]));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[7]_i_1__0 \n (.I0(D_po_counter_read_val[7]),\n .I1(A_rst_primitives_reg_1[7]),\n .I2(A_rst_primitives_reg_2[7]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_3[7]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(\\po_counter_read_val_reg[8] [7]));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[8]_i_1__0 \n (.I0(D_po_counter_read_val[8]),\n .I1(A_rst_primitives_reg_1[8]),\n .I2(A_rst_primitives_reg_2[8]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_3[8]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(\\po_counter_read_val_reg[8] [8]));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_byte_lane\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_byte_lane__parameterized3\n (SR,\n \\rd_ptr_timing_reg[2] ,\n \\rd_ptr_timing_reg[2]_0 ,\n \\rd_ptr_timing_reg[2]_1 ,\n \\rd_ptr_timing_reg[2]_2 ,\n A_of_full,\n COUNTERREADVAL,\n wr_en,\n \\my_empty_reg[1] ,\n Q,\n mem_dq_out,\n A_rst_primitives,\n CLK,\n D0,\n D1,\n OUTBURSTPENDING,\n \\calib_sel_reg[1] ,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n \\calib_sel_reg[1]_0 ,\n \\calib_sel_reg[1]_1 ,\n freq_refclk,\n mem_refclk,\n \\calib_sel_reg[1]_2 ,\n sync_pulse,\n PCENABLECALIB,\n mux_cmd_wren,\n mem_out);\n output [0:0]SR;\n output \\rd_ptr_timing_reg[2] ;\n output \\rd_ptr_timing_reg[2]_0 ;\n output \\rd_ptr_timing_reg[2]_1 ;\n output \\rd_ptr_timing_reg[2]_2 ;\n output A_of_full;\n output [8:0]COUNTERREADVAL;\n output wr_en;\n output \\my_empty_reg[1] ;\n output [3:0]Q;\n output [1:0]mem_dq_out;\n input A_rst_primitives;\n input CLK;\n input [2:0]D0;\n input [2:0]D1;\n input [0:0]OUTBURSTPENDING;\n input \\calib_sel_reg[1] ;\n input \\gen_byte_sel_div1.calib_in_common_reg ;\n input \\calib_sel_reg[1]_0 ;\n input \\calib_sel_reg[1]_1 ;\n input freq_refclk;\n input mem_refclk;\n input \\calib_sel_reg[1]_2 ;\n input sync_pulse;\n input [1:0]PCENABLECALIB;\n input mux_cmd_wren;\n input [11:0]mem_out;\n\n wire A_of_a_full;\n wire A_of_full;\n wire A_po_coarse_overflow;\n wire A_po_fine_overflow;\n wire A_rst_primitives;\n wire CLK;\n wire [8:0]COUNTERREADVAL;\n wire [2:0]D0;\n wire [2:0]D1;\n wire [0:0]OUTBURSTPENDING;\n wire [1:0]PCENABLECALIB;\n wire [3:0]Q;\n wire [0:0]SR;\n wire \\calib_sel_reg[1] ;\n wire \\calib_sel_reg[1]_0 ;\n wire \\calib_sel_reg[1]_1 ;\n wire \\calib_sel_reg[1]_2 ;\n wire freq_refclk;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire [1:0]mem_dq_out;\n wire [11:0]mem_out;\n wire mem_refclk;\n wire mux_cmd_wren;\n wire \\my_empty_reg[1] ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ;\n wire [3:0]of_q0;\n wire [3:0]of_q1;\n wire [3:0]of_q2;\n wire [3:0]of_q3;\n wire [3:0]of_q4;\n wire [7:0]of_q5;\n wire [7:0]of_q6;\n wire [3:0]of_q7;\n wire [3:0]of_q8;\n wire [3:0]of_q9;\n wire oserdes_clk;\n wire oserdes_clk_delayed;\n wire oserdes_clkdiv;\n wire [1:0]oserdes_dq_ts;\n wire [1:0]oserdes_dqs;\n wire [1:0]oserdes_dqs_ts;\n wire out_fifo_n_0;\n wire out_fifo_n_2;\n wire po_oserdes_rst;\n wire po_rd_enable;\n wire \\rd_ptr_timing_reg[2] ;\n wire \\rd_ptr_timing_reg[2]_0 ;\n wire \\rd_ptr_timing_reg[2]_1 ;\n wire \\rd_ptr_timing_reg[2]_2 ;\n wire sync_pulse;\n wire wr_en;\n wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;\n\n ddr3_ifmig_7series_v4_0_ddr_byte_group_io__parameterized3 ddr_byte_group_io\n (.mem_dq_out(mem_dq_out),\n .oserdes_clk(oserdes_clk),\n .oserdes_clkdiv(oserdes_clkdiv),\n .oserdes_dq({of_q1,of_q0}),\n .oserdes_rst(po_oserdes_rst));\n ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized6 \\of_pre_fifo_gen.u_ddr_of_pre_fifo \n (.CLK(CLK),\n .D0({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 }),\n .D1({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 }),\n .D2({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 }),\n .Q(Q),\n .SR(SR),\n .mem_out(mem_out),\n .mux_cmd_wren(mux_cmd_wren),\n .\\my_empty_reg[1]_0 (\\my_empty_reg[1] ),\n .ofifo_rst_reg(A_of_full),\n .\\rd_ptr_timing_reg[0]_0 (\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ),\n .\\rd_ptr_timing_reg[2]_0 (\\rd_ptr_timing_reg[2] ),\n .\\rd_ptr_timing_reg[2]_1 (\\rd_ptr_timing_reg[2]_0 ),\n .\\rd_ptr_timing_reg[2]_2 (\\rd_ptr_timing_reg[2]_1 ),\n .\\rd_ptr_timing_reg[2]_3 (\\rd_ptr_timing_reg[2]_2 ),\n .wr_en(wr_en));\n FDRE #(\n .INIT(1'b1)) \n ofifo_rst_reg\n (.C(CLK),\n .CE(1'b1),\n .D(A_rst_primitives),\n .Q(SR),\n .R(1'b0));\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n OUT_FIFO #(\n .ALMOST_EMPTY_VALUE(1),\n .ALMOST_FULL_VALUE(1),\n .ARRAY_MODE(\"ARRAY_MODE_4_X_4\"),\n .OUTPUT_DISABLE(\"FALSE\"),\n .SYNCHRONOUS_MODE(\"FALSE\")) \n out_fifo\n (.ALMOSTEMPTY(out_fifo_n_0),\n .ALMOSTFULL(A_of_a_full),\n .D0({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,D0}),\n .D1({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ,D1}),\n .D2({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 }),\n .D3({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 }),\n .D4({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 }),\n .D5({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 }),\n .D6({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 }),\n .D7({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 }),\n .D8({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 }),\n .D9({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 }),\n .EMPTY(out_fifo_n_2),\n .FULL(A_of_full),\n .Q0(of_q0),\n .Q1(of_q1),\n .Q2(of_q2),\n .Q3(of_q3),\n .Q4(of_q4),\n .Q5(of_q5),\n .Q6(of_q6),\n .Q7(of_q7),\n .Q8(of_q8),\n .Q9(of_q9),\n .RDCLK(oserdes_clkdiv),\n .RDEN(po_rd_enable),\n .RESET(SR),\n .WRCLK(CLK),\n .WREN(\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ));\n (* box_type = \"PRIMITIVE\" *) \n PHASER_OUT_PHY #(\n .CLKOUT_DIV(4),\n .COARSE_BYPASS(\"FALSE\"),\n .COARSE_DELAY(0),\n .DATA_CTL_N(\"FALSE\"),\n .DATA_RD_CYCLES(\"FALSE\"),\n .FINE_DELAY(60),\n .IS_RST_INVERTED(1'b0),\n .MEMREFCLK_PERIOD(1.111111),\n .OCLKDELAY_INV(\"TRUE\"),\n .OCLK_DELAY(28),\n .OUTPUT_CLK_SRC(\"DELAYED_REF\"),\n .PHASEREFCLK_PERIOD(1.000000),\n .PO(3'b111),\n .REFCLK_PERIOD(1.112000),\n .SYNC_IN_DIV_RST(\"TRUE\")) \n phaser_out\n (.BURSTPENDINGPHY(OUTBURSTPENDING),\n .COARSEENABLE(\\calib_sel_reg[1] ),\n .COARSEINC(\\calib_sel_reg[1] ),\n .COARSEOVERFLOW(A_po_coarse_overflow),\n .COUNTERLOADEN(1'b0),\n .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .COUNTERREADEN(\\gen_byte_sel_div1.calib_in_common_reg ),\n .COUNTERREADVAL(COUNTERREADVAL),\n .CTSBUS(oserdes_dqs_ts),\n .DQSBUS(oserdes_dqs),\n .DTSBUS(oserdes_dq_ts),\n .ENCALIBPHY(PCENABLECALIB),\n .FINEENABLE(\\calib_sel_reg[1]_0 ),\n .FINEINC(\\calib_sel_reg[1]_1 ),\n .FINEOVERFLOW(A_po_fine_overflow),\n .FREQREFCLK(freq_refclk),\n .MEMREFCLK(mem_refclk),\n .OCLK(oserdes_clk),\n .OCLKDELAYED(oserdes_clk_delayed),\n .OCLKDIV(oserdes_clkdiv),\n .OSERDESRST(po_oserdes_rst),\n .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),\n .RDENABLE(po_rd_enable),\n .RST(A_rst_primitives),\n .SELFINEOCLKDELAY(\\calib_sel_reg[1]_2 ),\n .SYNCIN(sync_pulse),\n .SYSCLK(CLK));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_byte_lane\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_byte_lane__parameterized4\n (\\rd_ptr_timing_reg[2] ,\n \\rd_ptr_timing_reg[2]_0 ,\n \\rd_ptr_timing_reg[2]_1 ,\n \\rd_ptr_timing_reg[2]_2 ,\n COUNTERREADVAL,\n wr_en_5,\n \\my_empty_reg[1] ,\n of_ctl_full_v,\n Q,\n mem_dq_out,\n SR,\n CLK,\n init_calib_complete_reg_rep__6,\n D5,\n D6,\n OUTBURSTPENDING,\n \\calib_sel_reg[1] ,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n \\calib_sel_reg[1]_0 ,\n \\calib_sel_reg[1]_1 ,\n freq_refclk,\n mem_refclk,\n A_rst_primitives,\n \\calib_sel_reg[1]_2 ,\n sync_pulse,\n PCENABLECALIB,\n mux_cmd_wren,\n \\rd_ptr_reg[3] ,\n C_of_full,\n A_of_full,\n D_of_full);\n output \\rd_ptr_timing_reg[2] ;\n output \\rd_ptr_timing_reg[2]_0 ;\n output \\rd_ptr_timing_reg[2]_1 ;\n output \\rd_ptr_timing_reg[2]_2 ;\n output [8:0]COUNTERREADVAL;\n output wr_en_5;\n output \\my_empty_reg[1] ;\n output [0:0]of_ctl_full_v;\n output [3:0]Q;\n output [2:0]mem_dq_out;\n input [0:0]SR;\n input CLK;\n input [3:0]init_calib_complete_reg_rep__6;\n input [3:0]D5;\n input [3:0]D6;\n input [0:0]OUTBURSTPENDING;\n input \\calib_sel_reg[1] ;\n input \\gen_byte_sel_div1.calib_in_common_reg ;\n input \\calib_sel_reg[1]_0 ;\n input \\calib_sel_reg[1]_1 ;\n input freq_refclk;\n input mem_refclk;\n input A_rst_primitives;\n input \\calib_sel_reg[1]_2 ;\n input sync_pulse;\n input [1:0]PCENABLECALIB;\n input mux_cmd_wren;\n input [17:0]\\rd_ptr_reg[3] ;\n input C_of_full;\n input A_of_full;\n input D_of_full;\n\n wire A_of_full;\n wire A_rst_primitives;\n wire B_of_a_full;\n wire B_of_full;\n wire B_po_coarse_overflow;\n wire B_po_fine_overflow;\n wire CLK;\n wire [8:0]COUNTERREADVAL;\n wire C_of_full;\n wire [3:0]D5;\n wire [3:0]D6;\n wire D_of_full;\n wire [0:0]OUTBURSTPENDING;\n wire [1:0]PCENABLECALIB;\n wire [3:0]Q;\n wire [0:0]SR;\n wire \\calib_sel_reg[1] ;\n wire \\calib_sel_reg[1]_0 ;\n wire \\calib_sel_reg[1]_1 ;\n wire \\calib_sel_reg[1]_2 ;\n wire freq_refclk;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire [3:0]init_calib_complete_reg_rep__6;\n wire [2:0]mem_dq_out;\n wire mem_refclk;\n wire mux_cmd_wren;\n wire \\my_empty_reg[1] ;\n wire [0:0]of_ctl_full_v;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ;\n wire [3:0]of_q0;\n wire [3:0]of_q1;\n wire [3:0]of_q2;\n wire [3:0]of_q3;\n wire [3:0]of_q4;\n wire [7:0]of_q5;\n wire [7:0]of_q6;\n wire [3:0]of_q7;\n wire [3:0]of_q8;\n wire [3:0]of_q9;\n wire oserdes_clk;\n wire oserdes_clk_delayed;\n wire oserdes_clkdiv;\n wire [1:0]oserdes_dq_ts;\n wire [1:0]oserdes_dqs;\n wire [1:0]oserdes_dqs_ts;\n wire out_fifo_n_0;\n wire out_fifo_n_2;\n wire po_oserdes_rst;\n wire po_rd_enable;\n wire [17:0]\\rd_ptr_reg[3] ;\n wire \\rd_ptr_timing_reg[2] ;\n wire \\rd_ptr_timing_reg[2]_0 ;\n wire \\rd_ptr_timing_reg[2]_1 ;\n wire \\rd_ptr_timing_reg[2]_2 ;\n wire sync_pulse;\n wire wr_en_5;\n wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;\n\n ddr3_ifmig_7series_v4_0_ddr_byte_group_io__parameterized4 ddr_byte_group_io\n (.mem_dq_out(mem_dq_out),\n .oserdes_clk(oserdes_clk),\n .oserdes_clkdiv(oserdes_clkdiv),\n .oserdes_dq({of_q6[7:4],of_q5[7:4],of_q4}),\n .oserdes_rst(po_oserdes_rst));\n ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized7 \\of_pre_fifo_gen.u_ddr_of_pre_fifo \n (.B_of_full(B_of_full),\n .CLK(CLK),\n .D0({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 }),\n .D3({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 }),\n .D5({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 }),\n .D6({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 }),\n .D7({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 }),\n .Q(Q),\n .SR(SR),\n .mux_cmd_wren(mux_cmd_wren),\n .\\my_empty_reg[1]_0 (\\my_empty_reg[1] ),\n .\\my_full_reg[3]_0 (\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ),\n .\\rd_ptr_reg[3]_0 (\\rd_ptr_reg[3] ),\n .\\rd_ptr_timing_reg[2]_0 (\\rd_ptr_timing_reg[2] ),\n .\\rd_ptr_timing_reg[2]_1 (\\rd_ptr_timing_reg[2]_0 ),\n .\\rd_ptr_timing_reg[2]_2 (\\rd_ptr_timing_reg[2]_1 ),\n .\\rd_ptr_timing_reg[2]_3 (\\rd_ptr_timing_reg[2]_2 ),\n .wr_en_5(wr_en_5));\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n OUT_FIFO #(\n .ALMOST_EMPTY_VALUE(1),\n .ALMOST_FULL_VALUE(1),\n .ARRAY_MODE(\"ARRAY_MODE_4_X_4\"),\n .OUTPUT_DISABLE(\"FALSE\"),\n .SYNCHRONOUS_MODE(\"FALSE\")) \n out_fifo\n (.ALMOSTEMPTY(out_fifo_n_0),\n .ALMOSTFULL(B_of_a_full),\n .D0({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 }),\n .D1({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 }),\n .D2({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 }),\n .D3({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 }),\n .D4({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,init_calib_complete_reg_rep__6}),\n .D5({D5,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 }),\n .D6({D6,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 }),\n .D7({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 }),\n .D8({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 }),\n .D9({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 }),\n .EMPTY(out_fifo_n_2),\n .FULL(B_of_full),\n .Q0(of_q0),\n .Q1(of_q1),\n .Q2(of_q2),\n .Q3(of_q3),\n .Q4(of_q4),\n .Q5(of_q5),\n .Q6(of_q6),\n .Q7(of_q7),\n .Q8(of_q8),\n .Q9(of_q9),\n .RDCLK(oserdes_clkdiv),\n .RDEN(po_rd_enable),\n .RESET(SR),\n .WRCLK(CLK),\n .WREN(\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ));\n (* box_type = \"PRIMITIVE\" *) \n PHASER_OUT_PHY #(\n .CLKOUT_DIV(4),\n .COARSE_BYPASS(\"FALSE\"),\n .COARSE_DELAY(0),\n .DATA_CTL_N(\"FALSE\"),\n .DATA_RD_CYCLES(\"FALSE\"),\n .FINE_DELAY(60),\n .IS_RST_INVERTED(1'b0),\n .MEMREFCLK_PERIOD(1.111111),\n .OCLKDELAY_INV(\"TRUE\"),\n .OCLK_DELAY(28),\n .OUTPUT_CLK_SRC(\"DELAYED_REF\"),\n .PHASEREFCLK_PERIOD(1.000000),\n .PO(3'b111),\n .REFCLK_PERIOD(1.112000),\n .SYNC_IN_DIV_RST(\"TRUE\")) \n phaser_out\n (.BURSTPENDINGPHY(OUTBURSTPENDING),\n .COARSEENABLE(\\calib_sel_reg[1] ),\n .COARSEINC(\\calib_sel_reg[1] ),\n .COARSEOVERFLOW(B_po_coarse_overflow),\n .COUNTERLOADEN(1'b0),\n .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .COUNTERREADEN(\\gen_byte_sel_div1.calib_in_common_reg ),\n .COUNTERREADVAL(COUNTERREADVAL),\n .CTSBUS(oserdes_dqs_ts),\n .DQSBUS(oserdes_dqs),\n .DTSBUS(oserdes_dq_ts),\n .ENCALIBPHY(PCENABLECALIB),\n .FINEENABLE(\\calib_sel_reg[1]_0 ),\n .FINEINC(\\calib_sel_reg[1]_1 ),\n .FINEOVERFLOW(B_po_fine_overflow),\n .FREQREFCLK(freq_refclk),\n .MEMREFCLK(mem_refclk),\n .OCLK(oserdes_clk),\n .OCLKDELAYED(oserdes_clk_delayed),\n .OCLKDIV(oserdes_clkdiv),\n .OSERDESRST(po_oserdes_rst),\n .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),\n .RDENABLE(po_rd_enable),\n .RST(A_rst_primitives),\n .SELFINEOCLKDELAY(\\calib_sel_reg[1]_2 ),\n .SYNCIN(sync_pulse),\n .SYSCLK(CLK));\n LUT4 #(\n .INIT(16'hFFFE)) \n phy_mc_cmd_full_r_i_1\n (.I0(B_of_full),\n .I1(C_of_full),\n .I2(A_of_full),\n .I3(D_of_full),\n .O(of_ctl_full_v));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_byte_lane\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_byte_lane__parameterized5\n (C_of_full,\n \\rd_ptr_timing_reg[2] ,\n \\rd_ptr_timing_reg[2]_0 ,\n \\rd_ptr_timing_reg[2]_1 ,\n \\rd_ptr_timing_reg[2]_2 ,\n COUNTERREADVAL,\n wr_en_6,\n \\my_empty_reg[1] ,\n Q,\n mem_dq_out,\n SR,\n CLK,\n D2,\n D3,\n \\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ,\n \\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ,\n D7,\n D8,\n D9,\n OUTBURSTPENDING,\n \\calib_sel_reg[0] ,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n \\calib_sel_reg[0]_0 ,\n \\calib_sel_reg[0]_1 ,\n freq_refclk,\n mem_refclk,\n A_rst_primitives,\n \\calib_sel_reg[0]_2 ,\n sync_pulse,\n PCENABLECALIB,\n mux_cmd_wren,\n \\rd_ptr_reg[3] );\n output C_of_full;\n output \\rd_ptr_timing_reg[2] ;\n output \\rd_ptr_timing_reg[2]_0 ;\n output \\rd_ptr_timing_reg[2]_1 ;\n output \\rd_ptr_timing_reg[2]_2 ;\n output [8:0]COUNTERREADVAL;\n output wr_en_6;\n output \\my_empty_reg[1] ;\n output [3:0]Q;\n output [9:0]mem_dq_out;\n input [0:0]SR;\n input CLK;\n input [2:0]D2;\n input [2:0]D3;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ;\n input [7:0]\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ;\n input [7:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ;\n input [3:0]D7;\n input [3:0]D8;\n input [3:0]D9;\n input [0:0]OUTBURSTPENDING;\n input \\calib_sel_reg[0] ;\n input \\gen_byte_sel_div1.calib_in_common_reg ;\n input \\calib_sel_reg[0]_0 ;\n input \\calib_sel_reg[0]_1 ;\n input freq_refclk;\n input mem_refclk;\n input A_rst_primitives;\n input \\calib_sel_reg[0]_2 ;\n input sync_pulse;\n input [1:0]PCENABLECALIB;\n input mux_cmd_wren;\n input [33:0]\\rd_ptr_reg[3] ;\n\n wire A_rst_primitives;\n wire CLK;\n wire [8:0]COUNTERREADVAL;\n wire C_of_a_full;\n wire C_of_full;\n wire C_po_coarse_overflow;\n wire C_po_fine_overflow;\n wire [2:0]D2;\n wire [2:0]D3;\n wire [3:0]D7;\n wire [3:0]D8;\n wire [3:0]D9;\n wire [0:0]OUTBURSTPENDING;\n wire [1:0]PCENABLECALIB;\n wire [3:0]Q;\n wire [0:0]SR;\n wire \\calib_sel_reg[0] ;\n wire \\calib_sel_reg[0]_0 ;\n wire \\calib_sel_reg[0]_1 ;\n wire \\calib_sel_reg[0]_2 ;\n wire freq_refclk;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire [7:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ;\n wire [7:0]\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ;\n wire [9:0]mem_dq_out;\n wire mem_refclk;\n wire mux_cmd_wren;\n wire \\my_empty_reg[1] ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_40 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ;\n wire [3:0]of_q0;\n wire [3:0]of_q1;\n wire [3:0]of_q2;\n wire [3:0]of_q3;\n wire [3:0]of_q4;\n wire [7:0]of_q5;\n wire [7:0]of_q6;\n wire [3:0]of_q7;\n wire [3:0]of_q8;\n wire [3:0]of_q9;\n wire oserdes_clk;\n wire oserdes_clk_delayed;\n wire oserdes_clkdiv;\n wire [1:0]oserdes_dq_ts;\n wire [1:0]oserdes_dqs;\n wire [1:0]oserdes_dqs_ts;\n wire out_fifo_n_0;\n wire out_fifo_n_2;\n wire po_oserdes_rst;\n wire po_rd_enable;\n wire [33:0]\\rd_ptr_reg[3] ;\n wire \\rd_ptr_timing_reg[2] ;\n wire \\rd_ptr_timing_reg[2]_0 ;\n wire \\rd_ptr_timing_reg[2]_1 ;\n wire \\rd_ptr_timing_reg[2]_2 ;\n wire sync_pulse;\n wire wr_en_6;\n wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;\n\n ddr3_ifmig_7series_v4_0_ddr_byte_group_io__parameterized5 ddr_byte_group_io\n (.mem_dq_out(mem_dq_out),\n .oserdes_clk(oserdes_clk),\n .oserdes_clkdiv(oserdes_clkdiv),\n .oserdes_dq({of_q6[7:4],of_q5[7:4],of_q9,of_q8,of_q7,of_q6[3:0],of_q5[3:0],of_q4,of_q3,of_q2}),\n .po_oserdes_rst(po_oserdes_rst));\n ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized8 \\of_pre_fifo_gen.u_ddr_of_pre_fifo \n (.CLK(CLK),\n .D0({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 }),\n .D1({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 }),\n .D2({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 }),\n .D3({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 }),\n .D4({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 }),\n .D7({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 }),\n .D8({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 }),\n .D9({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_40 }),\n .Q(Q),\n .SR(SR),\n .mux_cmd_wren(mux_cmd_wren),\n .\\my_empty_reg[1]_0 (\\my_empty_reg[1] ),\n .ofifo_rst_reg(C_of_full),\n .\\rd_ptr_reg[3]_0 (\\rd_ptr_reg[3] ),\n .\\rd_ptr_timing_reg[0]_0 (\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ),\n .\\rd_ptr_timing_reg[2]_0 (\\rd_ptr_timing_reg[2] ),\n .\\rd_ptr_timing_reg[2]_1 (\\rd_ptr_timing_reg[2]_0 ),\n .\\rd_ptr_timing_reg[2]_2 (\\rd_ptr_timing_reg[2]_1 ),\n .\\rd_ptr_timing_reg[2]_3 (\\rd_ptr_timing_reg[2]_2 ),\n .wr_en_6(wr_en_6));\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n OUT_FIFO #(\n .ALMOST_EMPTY_VALUE(1),\n .ALMOST_FULL_VALUE(1),\n .ARRAY_MODE(\"ARRAY_MODE_4_X_4\"),\n .OUTPUT_DISABLE(\"FALSE\"),\n .SYNCHRONOUS_MODE(\"FALSE\")) \n out_fifo\n (.ALMOSTEMPTY(out_fifo_n_0),\n .ALMOSTFULL(C_of_a_full),\n .D0({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 }),\n .D1({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 }),\n .D2({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,D2}),\n .D3({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ,D3}),\n .D4({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 ,\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] }),\n .D5(\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ),\n .D6(\\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ),\n .D7({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ,D7}),\n .D8({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ,D8}),\n .D9({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_40 ,D9}),\n .EMPTY(out_fifo_n_2),\n .FULL(C_of_full),\n .Q0(of_q0),\n .Q1(of_q1),\n .Q2(of_q2),\n .Q3(of_q3),\n .Q4(of_q4),\n .Q5(of_q5),\n .Q6(of_q6),\n .Q7(of_q7),\n .Q8(of_q8),\n .Q9(of_q9),\n .RDCLK(oserdes_clkdiv),\n .RDEN(po_rd_enable),\n .RESET(SR),\n .WRCLK(CLK),\n .WREN(\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ));\n (* box_type = \"PRIMITIVE\" *) \n PHASER_OUT_PHY #(\n .CLKOUT_DIV(4),\n .COARSE_BYPASS(\"FALSE\"),\n .COARSE_DELAY(0),\n .DATA_CTL_N(\"FALSE\"),\n .DATA_RD_CYCLES(\"FALSE\"),\n .FINE_DELAY(60),\n .IS_RST_INVERTED(1'b0),\n .MEMREFCLK_PERIOD(1.111111),\n .OCLKDELAY_INV(\"TRUE\"),\n .OCLK_DELAY(28),\n .OUTPUT_CLK_SRC(\"DELAYED_REF\"),\n .PHASEREFCLK_PERIOD(1.000000),\n .PO(3'b111),\n .REFCLK_PERIOD(1.112000),\n .SYNC_IN_DIV_RST(\"TRUE\")) \n phaser_out\n (.BURSTPENDINGPHY(OUTBURSTPENDING),\n .COARSEENABLE(\\calib_sel_reg[0] ),\n .COARSEINC(\\calib_sel_reg[0] ),\n .COARSEOVERFLOW(C_po_coarse_overflow),\n .COUNTERLOADEN(1'b0),\n .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .COUNTERREADEN(\\gen_byte_sel_div1.calib_in_common_reg ),\n .COUNTERREADVAL(COUNTERREADVAL),\n .CTSBUS(oserdes_dqs_ts),\n .DQSBUS(oserdes_dqs),\n .DTSBUS(oserdes_dq_ts),\n .ENCALIBPHY(PCENABLECALIB),\n .FINEENABLE(\\calib_sel_reg[0]_0 ),\n .FINEINC(\\calib_sel_reg[0]_1 ),\n .FINEOVERFLOW(C_po_fine_overflow),\n .FREQREFCLK(freq_refclk),\n .MEMREFCLK(mem_refclk),\n .OCLK(oserdes_clk),\n .OCLKDELAYED(oserdes_clk_delayed),\n .OCLKDIV(oserdes_clkdiv),\n .OSERDESRST(po_oserdes_rst),\n .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),\n .RDENABLE(po_rd_enable),\n .RST(A_rst_primitives),\n .SELFINEOCLKDELAY(\\calib_sel_reg[0]_2 ),\n .SYNCIN(sync_pulse),\n .SYSCLK(CLK));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_byte_lane\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_byte_lane__parameterized6\n (\\my_empty_reg[1] ,\n D,\n ddr_ck_out,\n D_of_full,\n mem_dq_out,\n \\my_empty_reg[7] ,\n init_calib_complete_reg_rep__5,\n mc_cas_n,\n mc_address,\n init_calib_complete_reg_rep,\n COUNTERREADVAL,\n A_rst_primitives_reg,\n \\calib_sel_reg[1] ,\n A_rst_primitives_reg_0,\n SR,\n CLK,\n OUTBURSTPENDING,\n D_po_coarse_enable110_out,\n D_po_counter_read_en122_out,\n D_po_fine_enable107_out,\n D_po_fine_inc113_out,\n freq_refclk,\n mem_refclk,\n A_rst_primitives,\n D_po_sel_fine_oclk_delay125_out,\n sync_pulse,\n PCENABLECALIB,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ,\n D4,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ,\n mux_cmd_wren,\n phy_dout,\n init_calib_complete_reg_rep__6);\n output \\my_empty_reg[1] ;\n output [8:0]D;\n output [1:0]ddr_ck_out;\n output D_of_full;\n output [8:0]mem_dq_out;\n output [31:0]\\my_empty_reg[7] ;\n input init_calib_complete_reg_rep__5;\n input [0:0]mc_cas_n;\n input [1:0]mc_address;\n input init_calib_complete_reg_rep;\n input [8:0]COUNTERREADVAL;\n input [8:0]A_rst_primitives_reg;\n input [1:0]\\calib_sel_reg[1] ;\n input [8:0]A_rst_primitives_reg_0;\n input [0:0]SR;\n input CLK;\n input [0:0]OUTBURSTPENDING;\n input D_po_coarse_enable110_out;\n input D_po_counter_read_en122_out;\n input D_po_fine_enable107_out;\n input D_po_fine_inc113_out;\n input freq_refclk;\n input mem_refclk;\n input A_rst_primitives;\n input D_po_sel_fine_oclk_delay125_out;\n input sync_pulse;\n input [1:0]PCENABLECALIB;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ;\n input [3:0]D4;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ;\n input mux_cmd_wren;\n input [35:0]phy_dout;\n input init_calib_complete_reg_rep__6;\n\n wire A_rst_primitives;\n wire [8:0]A_rst_primitives_reg;\n wire [8:0]A_rst_primitives_reg_0;\n wire CLK;\n wire [8:0]COUNTERREADVAL;\n wire [8:0]D;\n wire [3:0]D4;\n wire D_of_full;\n wire D_po_coarse_enable110_out;\n wire D_po_counter_read_en122_out;\n wire [8:0]D_po_counter_read_val;\n wire D_po_fine_enable107_out;\n wire D_po_fine_inc113_out;\n wire D_po_sel_fine_oclk_delay125_out;\n wire [0:0]OUTBURSTPENDING;\n wire [1:0]PCENABLECALIB;\n wire [0:0]SR;\n wire [1:0]\\calib_sel_reg[1] ;\n wire [1:0]ddr_ck_out;\n wire [0:0]ddr_ck_out_q;\n wire freq_refclk;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ;\n wire init_calib_complete_reg_rep;\n wire init_calib_complete_reg_rep__5;\n wire init_calib_complete_reg_rep__6;\n wire [1:0]mc_address;\n wire [0:0]mc_cas_n;\n wire [8:0]mem_dq_out;\n wire mem_refclk;\n wire mux_cmd_wren;\n wire \\my_empty_reg[1] ;\n wire [31:0]\\my_empty_reg[7] ;\n wire [3:0]of_d9;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_40 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_41 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_42 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_43 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_44 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_45 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_46 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_47 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ;\n wire [3:0]of_q0;\n wire [3:0]of_q1;\n wire [3:0]of_q2;\n wire [3:0]of_q3;\n wire [3:0]of_q4;\n wire [7:0]of_q5;\n wire [7:0]of_q6;\n wire [3:0]of_q7;\n wire [3:0]of_q8;\n wire [3:0]of_q9;\n wire oserdes_clk;\n wire oserdes_clk_delayed;\n wire oserdes_clkdiv;\n wire [1:0]oserdes_dq_ts;\n wire [1:0]oserdes_dqs;\n wire [1:0]oserdes_dqs_ts;\n wire out_fifo_n_0;\n wire out_fifo_n_1;\n wire out_fifo_n_2;\n wire phaser_out_n_0;\n wire phaser_out_n_1;\n wire [35:0]phy_dout;\n wire po_oserdes_rst;\n wire po_rd_enable;\n wire sync_pulse;\n wire \\NLW_ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_S_UNCONNECTED ;\n wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;\n\n ddr3_ifmig_7series_v4_0_ddr_byte_group_io__parameterized6 ddr_byte_group_io\n (.mem_dq_out(mem_dq_out),\n .oserdes_clk(oserdes_clk),\n .oserdes_clkdiv(oserdes_clkdiv),\n .oserdes_dq({of_q9,of_q8,of_q7,of_q6[3:0],of_q5[3:0],of_q4,of_q3,of_q2,of_q1}),\n .po_oserdes_rst(po_oserdes_rst));\n (* __SRVAL = \"FALSE\" *) \n (* box_type = \"PRIMITIVE\" *) \n ODDR #(\n .DDR_CLK_EDGE(\"SAME_EDGE\"),\n .INIT(1'b0),\n .IS_C_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .SRTYPE(\"SYNC\")) \n \\ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck \n (.C(oserdes_clk),\n .CE(1'b1),\n .D1(1'b0),\n .D2(1'b1),\n .Q(ddr_ck_out_q),\n .R(1'b0),\n .S(\\NLW_ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_S_UNCONNECTED ));\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* XILINX_LEGACY_PRIM = \"OBUFDS\" *) \n (* box_type = \"PRIMITIVE\" *) \n OBUFDS #(\n .IOSTANDARD(\"DEFAULT\")) \n \\ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_obuf \n (.I(ddr_ck_out_q),\n .O(ddr_ck_out[0]),\n .OB(ddr_ck_out[1]));\n ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized9 \\of_pre_fifo_gen.u_ddr_of_pre_fifo \n (.CLK(CLK),\n .D0({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 }),\n .D1({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 }),\n .D2({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 }),\n .D3({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 }),\n .D4({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 }),\n .D5({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 }),\n .D6({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 }),\n .D7({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_40 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_41 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_42 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_43 }),\n .D8({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_44 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_45 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_46 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_47 }),\n .D9({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,of_d9}),\n .SR(SR),\n .init_calib_complete_reg_rep(init_calib_complete_reg_rep),\n .init_calib_complete_reg_rep__5(init_calib_complete_reg_rep__5),\n .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6),\n .mc_address(mc_address),\n .mc_cas_n(mc_cas_n),\n .mux_cmd_wren(mux_cmd_wren),\n .\\my_empty_reg[1]_0 (\\my_empty_reg[1] ),\n .\\my_empty_reg[7]_0 (\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ),\n .\\my_empty_reg[7]_1 (\\my_empty_reg[7] ),\n .ofifo_rst_reg(D_of_full),\n .phy_dout(phy_dout));\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n OUT_FIFO #(\n .ALMOST_EMPTY_VALUE(1),\n .ALMOST_FULL_VALUE(1),\n .ARRAY_MODE(\"ARRAY_MODE_4_X_4\"),\n .OUTPUT_DISABLE(\"FALSE\"),\n .SYNCHRONOUS_MODE(\"FALSE\")) \n out_fifo\n (.ALMOSTEMPTY(out_fifo_n_0),\n .ALMOSTFULL(out_fifo_n_1),\n .D0({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1 }),\n .D1({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ,\\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] }),\n .D2({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ,\\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] }),\n .D3({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ,\\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] }),\n .D4({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 ,D4}),\n .D5({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ,\\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] }),\n .D6({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 ,\\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] }),\n .D7({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_40 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_41 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_42 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_43 ,\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] }),\n .D8({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_44 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_45 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_46 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_47 ,\\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] }),\n .D9({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,of_d9}),\n .EMPTY(out_fifo_n_2),\n .FULL(D_of_full),\n .Q0(of_q0),\n .Q1(of_q1),\n .Q2(of_q2),\n .Q3(of_q3),\n .Q4(of_q4),\n .Q5(of_q5),\n .Q6(of_q6),\n .Q7(of_q7),\n .Q8(of_q8),\n .Q9(of_q9),\n .RDCLK(oserdes_clkdiv),\n .RDEN(po_rd_enable),\n .RESET(SR),\n .WRCLK(CLK),\n .WREN(\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ));\n (* box_type = \"PRIMITIVE\" *) \n PHASER_OUT_PHY #(\n .CLKOUT_DIV(4),\n .COARSE_BYPASS(\"FALSE\"),\n .COARSE_DELAY(0),\n .DATA_CTL_N(\"FALSE\"),\n .DATA_RD_CYCLES(\"FALSE\"),\n .FINE_DELAY(60),\n .IS_RST_INVERTED(1'b0),\n .MEMREFCLK_PERIOD(1.111111),\n .OCLKDELAY_INV(\"TRUE\"),\n .OCLK_DELAY(28),\n .OUTPUT_CLK_SRC(\"DELAYED_REF\"),\n .PHASEREFCLK_PERIOD(1.000000),\n .PO(3'b111),\n .REFCLK_PERIOD(1.112000),\n .SYNC_IN_DIV_RST(\"TRUE\")) \n phaser_out\n (.BURSTPENDINGPHY(OUTBURSTPENDING),\n .COARSEENABLE(D_po_coarse_enable110_out),\n .COARSEINC(D_po_coarse_enable110_out),\n .COARSEOVERFLOW(phaser_out_n_0),\n .COUNTERLOADEN(1'b0),\n .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .COUNTERREADEN(D_po_counter_read_en122_out),\n .COUNTERREADVAL(D_po_counter_read_val),\n .CTSBUS(oserdes_dqs_ts),\n .DQSBUS(oserdes_dqs),\n .DTSBUS(oserdes_dq_ts),\n .ENCALIBPHY(PCENABLECALIB),\n .FINEENABLE(D_po_fine_enable107_out),\n .FINEINC(D_po_fine_inc113_out),\n .FINEOVERFLOW(phaser_out_n_1),\n .FREQREFCLK(freq_refclk),\n .MEMREFCLK(mem_refclk),\n .OCLK(oserdes_clk),\n .OCLKDELAYED(oserdes_clk_delayed),\n .OCLKDIV(oserdes_clkdiv),\n .OSERDESRST(po_oserdes_rst),\n .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),\n .RDENABLE(po_rd_enable),\n .RST(A_rst_primitives),\n .SELFINEOCLKDELAY(D_po_sel_fine_oclk_delay125_out),\n .SYNCIN(sync_pulse),\n .SYSCLK(CLK));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[0]_i_1 \n (.I0(D_po_counter_read_val[0]),\n .I1(COUNTERREADVAL[0]),\n .I2(A_rst_primitives_reg[0]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_0[0]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(D[0]));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[1]_i_1 \n (.I0(D_po_counter_read_val[1]),\n .I1(COUNTERREADVAL[1]),\n .I2(A_rst_primitives_reg[1]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_0[1]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(D[1]));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[2]_i_1 \n (.I0(D_po_counter_read_val[2]),\n .I1(COUNTERREADVAL[2]),\n .I2(A_rst_primitives_reg[2]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_0[2]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(D[2]));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[3]_i_1 \n (.I0(D_po_counter_read_val[3]),\n .I1(COUNTERREADVAL[3]),\n .I2(A_rst_primitives_reg[3]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_0[3]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(D[3]));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[4]_i_1 \n (.I0(D_po_counter_read_val[4]),\n .I1(COUNTERREADVAL[4]),\n .I2(A_rst_primitives_reg[4]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_0[4]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(D[4]));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[5]_i_1 \n (.I0(D_po_counter_read_val[5]),\n .I1(COUNTERREADVAL[5]),\n .I2(A_rst_primitives_reg[5]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_0[5]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(D[5]));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[6]_i_1 \n (.I0(D_po_counter_read_val[6]),\n .I1(COUNTERREADVAL[6]),\n .I2(A_rst_primitives_reg[6]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_0[6]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(D[6]));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[7]_i_1 \n (.I0(D_po_counter_read_val[7]),\n .I1(COUNTERREADVAL[7]),\n .I2(A_rst_primitives_reg[7]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_0[7]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(D[7]));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[8]_i_1 \n (.I0(D_po_counter_read_val[8]),\n .I1(COUNTERREADVAL[8]),\n .I2(A_rst_primitives_reg[8]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_0[8]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(D[8]));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_calib_top\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_calib_top\n (idelay_inc,\n phy_dout,\n phy_if_reset,\n \\samps_r_reg[9] ,\n \\my_empty_reg[7] ,\n \\rd_ptr_timing_reg[0] ,\n app_zq_r_reg,\n \\periodic_rd_generation.periodic_rd_timer_r_reg[1] ,\n init_calib_complete_r_reg,\n \\pi_rst_stg1_cal_r_reg[0] ,\n samp_edge_cnt0_en_r,\n pi_en_stg2_f_timing_reg,\n out,\n dqs_po_en_stg2_f_reg,\n prbs_rdlvl_start_r_reg,\n A,\n fine_delay_sel_r_reg,\n \\rd_ptr_timing_reg[0]_0 ,\n \\my_empty_reg[7]_0 ,\n \\my_empty_reg[7]_1 ,\n \\my_empty_reg[7]_2 ,\n \\my_empty_reg[7]_3 ,\n LD0,\n \\po_rdval_cnt_reg[8] ,\n LD0_0,\n LD0_1,\n LD0_2,\n D_po_counter_read_en122_out,\n D_po_fine_enable107_out,\n D_po_coarse_enable110_out,\n D_po_fine_inc113_out,\n D_po_sel_fine_oclk_delay125_out,\n \\po_counter_read_val_reg[8] ,\n \\po_counter_read_val_reg[8]_0 ,\n \\po_counter_read_val_reg[8]_1 ,\n \\po_counter_read_val_reg[8]_2 ,\n \\po_counter_read_val_reg[8]_3 ,\n \\po_counter_read_val_reg[8]_4 ,\n \\po_counter_read_val_reg[8]_5 ,\n \\po_counter_read_val_reg[8]_6 ,\n \\po_counter_read_val_reg[8]_7 ,\n \\po_counter_read_val_reg[8]_8 ,\n \\po_counter_read_val_reg[8]_9 ,\n \\po_counter_read_val_reg[8]_10 ,\n \\po_counter_read_val_reg[8]_11 ,\n E,\n \\po_counter_read_val_reg[8]_12 ,\n \\po_counter_read_val_reg[8]_13 ,\n \\po_counter_read_val_reg[8]_14 ,\n \\po_counter_read_val_reg[8]_15 ,\n \\pi_dqs_found_lanes_r1_reg[3] ,\n \\fine_delay_r_reg[5] ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,\n \\po_counter_read_val_reg[8]_16 ,\n \\po_counter_read_val_reg[8]_17 ,\n \\po_counter_read_val_reg[8]_18 ,\n ififo_rst_reg,\n \\pi_dqs_found_lanes_r1_reg[3]_0 ,\n \\pi_dqs_found_lanes_r1_reg[3]_1 ,\n \\pi_dqs_found_lanes_r1_reg[3]_2 ,\n \\pi_dqs_found_lanes_r1_reg[2] ,\n \\fine_delay_r_reg[5]_0 ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,\n \\po_counter_read_val_reg[8]_19 ,\n \\po_counter_read_val_reg[8]_20 ,\n \\po_counter_read_val_reg[8]_21 ,\n ififo_rst_reg_0,\n \\pi_dqs_found_lanes_r1_reg[2]_0 ,\n \\pi_dqs_found_lanes_r1_reg[2]_1 ,\n \\pi_dqs_found_lanes_r1_reg[2]_2 ,\n \\pi_dqs_found_lanes_r1_reg[1] ,\n \\fine_delay_r_reg[5]_1 ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,\n \\po_counter_read_val_reg[8]_22 ,\n \\po_counter_read_val_reg[8]_23 ,\n \\po_counter_read_val_reg[8]_24 ,\n ififo_rst_reg_1,\n \\pi_dqs_found_lanes_r1_reg[1]_0 ,\n \\pi_dqs_found_lanes_r1_reg[1]_1 ,\n \\pi_dqs_found_lanes_r1_reg[1]_2 ,\n D,\n COUNTERLOADVAL,\n \\pi_dqs_found_lanes_r1_reg[0] ,\n \\fine_delay_r_reg[2] ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,\n \\po_counter_read_val_reg[8]_25 ,\n \\po_counter_read_val_reg[8]_26 ,\n \\po_counter_read_val_reg[8]_27 ,\n ififo_rst_reg_2,\n \\pi_dqs_found_lanes_r1_reg[0]_0 ,\n \\pi_dqs_found_lanes_r1_reg[0]_1 ,\n \\pi_dqs_found_lanes_r1_reg[0]_2 ,\n \\po_counter_read_val_reg[8]_28 ,\n \\po_counter_read_val_reg[8]_29 ,\n stg3_dec2init_val_r_reg,\n stg3_inc2init_val_r_reg,\n A_1__s_port_,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 ,\n \\A[1]__4 ,\n D2,\n D0,\n D3,\n D5,\n D6,\n D1,\n \\rd_ptr_timing_reg[0]_1 ,\n D7,\n D8,\n \\rd_ptr_timing_reg[0]_2 ,\n \\my_empty_reg[7]_4 ,\n \\my_empty_reg[7]_5 ,\n \\my_empty_reg[7]_6 ,\n D4,\n \\my_empty_reg[7]_7 ,\n \\my_empty_reg[7]_8 ,\n \\my_empty_reg[7]_9 ,\n \\my_empty_reg[7]_10 ,\n \\my_full_reg[3] ,\n \\rd_ptr_timing_reg[0]_3 ,\n D9,\n \\my_empty_reg[7]_11 ,\n \\my_empty_reg[7]_12 ,\n \\my_empty_reg[7]_13 ,\n \\my_empty_reg[7]_14 ,\n \\my_empty_reg[7]_15 ,\n \\my_empty_reg[7]_16 ,\n \\my_empty_reg[7]_17 ,\n \\my_empty_reg[7]_18 ,\n \\my_empty_reg[7]_19 ,\n \\my_empty_reg[7]_20 ,\n \\my_empty_reg[7]_21 ,\n \\my_empty_reg[7]_22 ,\n \\my_empty_reg[7]_23 ,\n \\my_empty_reg[7]_24 ,\n \\my_empty_reg[7]_25 ,\n \\my_empty_reg[7]_26 ,\n \\my_empty_reg[7]_27 ,\n \\my_empty_reg[7]_28 ,\n \\my_empty_reg[7]_29 ,\n \\my_empty_reg[7]_30 ,\n \\my_empty_reg[7]_31 ,\n \\my_empty_reg[7]_32 ,\n \\my_empty_reg[7]_33 ,\n \\my_empty_reg[7]_34 ,\n \\my_empty_reg[7]_35 ,\n \\my_empty_reg[7]_36 ,\n \\my_empty_reg[7]_37 ,\n \\my_empty_reg[7]_38 ,\n \\my_empty_reg[7]_39 ,\n \\my_empty_reg[7]_40 ,\n \\my_empty_reg[7]_41 ,\n \\my_empty_reg[7]_42 ,\n \\byte_r_reg[0] ,\n \\byte_r_reg[1] ,\n \\stg2_tap_cnt_reg[0] ,\n \\sm_r_reg[0] ,\n \\zero2fuzz_r_reg[0] ,\n maint_prescaler_r1,\n \\cmd_pipe_plus.mc_data_offset_reg[4] ,\n \\cmd_pipe_plus.mc_data_offset_reg[5] ,\n \\cmd_pipe_plus.mc_data_offset_reg[1] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[4] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[5] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[1] ,\n \\cmd_pipe_plus.mc_data_offset_reg[0] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[0] ,\n \\rdlvl_dqs_tap_cnt_r_reg[0][3][0] ,\n \\idelay_tap_cnt_r_reg[0][3][0] ,\n \\en_cnt_div4.enable_wrlvl_cnt_reg[3] ,\n \\complex_row_cnt_ocal_reg[0] ,\n \\row_cnt_victim_rotate.complex_row_cnt_reg[4] ,\n \\fine_delay_mod_reg[5] ,\n \\fine_delay_mod_reg[20] ,\n \\phy_ctl_wd_i1_reg[24] ,\n phy_write_calib,\n phy_read_calib,\n \\fine_delay_mod_reg[26] ,\n \\genblk9[1].fine_delay_incdec_pb_reg[1] ,\n \\genblk9[2].fine_delay_incdec_pb_reg[2] ,\n \\genblk9[3].fine_delay_incdec_pb_reg[3] ,\n \\genblk9[5].fine_delay_incdec_pb_reg[5] ,\n \\genblk9[6].fine_delay_incdec_pb_reg[6] ,\n \\genblk9[7].fine_delay_incdec_pb_reg[7] ,\n mux_wrdata_en,\n mux_cmd_wren,\n mux_reset_n,\n \\data_offset_1_i1_reg[5] ,\n \\rd_ptr_timing_reg[0]_4 ,\n \\my_full_reg[3]_0 ,\n \\byte_sel_data_map_reg[1] ,\n \\A[0]__4 ,\n \\A[0]__0 ,\n \\A[2]__2 ,\n \\A[1]__0 ,\n \\A[1]__4_0 ,\n \\A[1]__3 ,\n \\A[2]__1 ,\n \\pi_dqs_found_lanes_r1_reg[1]_3 ,\n \\pi_dqs_found_lanes_r1_reg[2]_3 ,\n \\pi_dqs_found_lanes_r1_reg[3]_3 ,\n \\fine_delay_r_reg[26] ,\n \\fine_delay_r_reg[26]_0 ,\n \\fine_delay_r_reg[26]_1 ,\n \\qcntr_r_reg[0] ,\n CLK,\n rstdiv0_sync_r1_reg_rep__20,\n poc_sample_pd,\n rstdiv0_sync_r1_reg_rep__10,\n rstdiv0_sync_r1_reg_rep__9,\n phy_rddata_en,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ,\n \\po_stg2_wrcal_cnt_reg[1] ,\n \\po_stg2_wrcal_cnt_reg[1]_0 ,\n \\po_stg2_wrcal_cnt_reg[1]_1 ,\n \\po_stg2_wrcal_cnt_reg[1]_2 ,\n \\mcGo_r_reg[15] ,\n in0,\n rstdiv0_sync_r1_reg_rep__12,\n SR,\n rstdiv0_sync_r1_reg_rep__23,\n rstdiv0_sync_r1_reg_rep__13,\n rstdiv0_sync_r1_reg_rep__14,\n \\rd_mux_sel_r_reg[1] ,\n \\rd_mux_sel_r_reg[1]_0 ,\n \\rd_mux_sel_r_reg[1]_1 ,\n \\rd_mux_sel_r_reg[1]_2 ,\n \\rd_mux_sel_r_reg[1]_3 ,\n \\rd_mux_sel_r_reg[1]_4 ,\n \\rd_mux_sel_r_reg[1]_5 ,\n \\rd_mux_sel_r_reg[1]_6 ,\n \\rd_mux_sel_r_reg[1]_7 ,\n \\rd_mux_sel_r_reg[1]_8 ,\n \\rd_mux_sel_r_reg[1]_9 ,\n \\rd_mux_sel_r_reg[1]_10 ,\n \\rd_mux_sel_r_reg[1]_11 ,\n \\rd_mux_sel_r_reg[1]_12 ,\n \\rd_mux_sel_r_reg[1]_13 ,\n \\rd_mux_sel_r_reg[1]_14 ,\n \\rd_mux_sel_r_reg[1]_15 ,\n \\rd_mux_sel_r_reg[1]_16 ,\n \\rd_mux_sel_r_reg[1]_17 ,\n \\rd_mux_sel_r_reg[1]_18 ,\n \\rd_mux_sel_r_reg[1]_19 ,\n \\rd_mux_sel_r_reg[1]_20 ,\n \\rd_mux_sel_r_reg[1]_21 ,\n \\rd_mux_sel_r_reg[1]_22 ,\n \\rd_mux_sel_r_reg[1]_23 ,\n \\rd_mux_sel_r_reg[1]_24 ,\n \\rd_mux_sel_r_reg[1]_25 ,\n \\rd_mux_sel_r_reg[1]_26 ,\n \\rd_mux_sel_r_reg[1]_27 ,\n \\rd_mux_sel_r_reg[1]_28 ,\n \\rd_mux_sel_r_reg[1]_29 ,\n \\rd_mux_sel_r_reg[1]_30 ,\n \\rd_mux_sel_r_reg[1]_31 ,\n \\rd_mux_sel_r_reg[1]_32 ,\n \\rd_mux_sel_r_reg[1]_33 ,\n \\rd_mux_sel_r_reg[1]_34 ,\n \\rd_mux_sel_r_reg[1]_35 ,\n \\rd_mux_sel_r_reg[1]_36 ,\n \\rd_mux_sel_r_reg[1]_37 ,\n \\rd_mux_sel_r_reg[1]_38 ,\n \\rd_mux_sel_r_reg[1]_39 ,\n \\rd_mux_sel_r_reg[1]_40 ,\n \\rd_mux_sel_r_reg[1]_41 ,\n \\rd_mux_sel_r_reg[1]_42 ,\n \\rd_mux_sel_r_reg[1]_43 ,\n \\rd_mux_sel_r_reg[1]_44 ,\n \\rd_mux_sel_r_reg[1]_45 ,\n \\rd_mux_sel_r_reg[1]_46 ,\n \\rd_mux_sel_r_reg[1]_47 ,\n \\rd_mux_sel_r_reg[1]_48 ,\n \\rd_mux_sel_r_reg[1]_49 ,\n \\rd_mux_sel_r_reg[1]_50 ,\n \\rd_mux_sel_r_reg[1]_51 ,\n \\rd_mux_sel_r_reg[1]_52 ,\n \\rd_mux_sel_r_reg[1]_53 ,\n \\rd_mux_sel_r_reg[1]_54 ,\n \\rd_mux_sel_r_reg[1]_55 ,\n \\rd_mux_sel_r_reg[1]_56 ,\n \\rd_mux_sel_r_reg[1]_57 ,\n \\rd_mux_sel_r_reg[1]_58 ,\n \\rd_mux_sel_r_reg[1]_59 ,\n \\rd_mux_sel_r_reg[1]_60 ,\n \\rd_mux_sel_r_reg[1]_61 ,\n \\rd_mux_sel_r_reg[1]_62 ,\n rstdiv0_sync_r1_reg_rep__22,\n A_rst_primitives_reg,\n rstdiv0_sync_r1_reg_rep__11,\n cnt_pwron_reset_done_r0,\n rstdiv0_sync_r1_reg_rep__17,\n rstdiv0_sync_r1_reg_rep__16,\n SS,\n tempmon_sample_en,\n rstdiv0_sync_r1_reg_rep__2,\n rstdiv0_sync_r1_reg_rep__6,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ,\n rstdiv0_sync_r1_reg_rep__7,\n \\A[1]_0 ,\n \\A[1]_1 ,\n \\A[1]_2 ,\n \\A[1]_3 ,\n \\A[1]_4 ,\n \\A[1]_5 ,\n \\A[1]_6 ,\n \\A[1]_7 ,\n \\A[1]_8 ,\n \\A[1]_9 ,\n \\A[1]_10 ,\n \\A[1]_11 ,\n \\A[1]_12 ,\n \\A[1]_13 ,\n \\A[1]_14 ,\n \\A[1]_15 ,\n \\A[1]_16 ,\n \\A[1]_17 ,\n \\A[1]_18 ,\n \\A[1]_19 ,\n \\A[1]_20 ,\n \\A[1]_21 ,\n \\A[1]_22 ,\n \\A[1]_23 ,\n \\A[1]_24 ,\n \\A[1]_25 ,\n \\A[1]_26 ,\n \\A[1]_27 ,\n \\A[1]_28 ,\n \\A[1]_29 ,\n \\A[1]_30 ,\n \\A[1]_31 ,\n \\A[1]_32 ,\n \\A[1]_33 ,\n \\A[1]_34 ,\n \\A[1]_35 ,\n \\A[1]_36 ,\n \\A[1]_37 ,\n \\A[1]_38 ,\n \\A[1]_39 ,\n \\A[1]_40 ,\n \\A[1]_41 ,\n \\A[1]_42 ,\n \\A[1]_43 ,\n \\A[1]_44 ,\n \\A[1]_45 ,\n \\A[1]_46 ,\n \\A[1]_47 ,\n \\A[1]_48 ,\n \\A[1]_49 ,\n \\A[1]_50 ,\n \\A[1]_51 ,\n \\A[1]_52 ,\n \\A[1]_53 ,\n \\A[1]_54 ,\n \\A[1]_55 ,\n \\A[1]_56 ,\n \\A[1]_57 ,\n \\A[1]_58 ,\n \\A[1]_59 ,\n \\A[1]_60 ,\n \\A[1]_61 ,\n \\A[1]_62 ,\n \\A[1]_63 ,\n rstdiv0_sync_r1_reg_rep__8,\n rstdiv0_sync_r1_reg_rep,\n p_0_out,\n \\po_stg2_wrcal_cnt_reg[1]_3 ,\n \\po_stg2_wrcal_cnt_reg[1]_4 ,\n \\po_stg2_wrcal_cnt_reg[1]_5 ,\n \\po_stg2_wrcal_cnt_reg[1]_6 ,\n \\po_stg2_wrcal_cnt_reg[1]_7 ,\n \\po_stg2_wrcal_cnt_reg[1]_8 ,\n \\po_stg2_wrcal_cnt_reg[1]_9 ,\n \\po_stg2_wrcal_cnt_reg[1]_10 ,\n \\po_stg2_wrcal_cnt_reg[1]_11 ,\n \\po_stg2_wrcal_cnt_reg[1]_12 ,\n \\po_stg2_wrcal_cnt_reg[1]_13 ,\n \\po_stg2_wrcal_cnt_reg[1]_14 ,\n \\po_stg2_wrcal_cnt_reg[1]_15 ,\n \\po_stg2_wrcal_cnt_reg[1]_16 ,\n \\po_stg2_wrcal_cnt_reg[1]_17 ,\n \\po_stg2_wrcal_cnt_reg[1]_18 ,\n \\po_stg2_wrcal_cnt_reg[1]_19 ,\n \\po_stg2_wrcal_cnt_reg[1]_20 ,\n \\po_stg2_wrcal_cnt_reg[1]_21 ,\n \\po_stg2_wrcal_cnt_reg[1]_22 ,\n \\po_stg2_wrcal_cnt_reg[1]_23 ,\n \\po_stg2_wrcal_cnt_reg[1]_24 ,\n \\po_stg2_wrcal_cnt_reg[1]_25 ,\n \\po_stg2_wrcal_cnt_reg[1]_26 ,\n \\po_stg2_wrcal_cnt_reg[1]_27 ,\n \\po_stg2_wrcal_cnt_reg[1]_28 ,\n \\po_stg2_wrcal_cnt_reg[1]_29 ,\n \\po_stg2_wrcal_cnt_reg[1]_30 ,\n \\po_stg2_wrcal_cnt_reg[1]_31 ,\n \\po_stg2_wrcal_cnt_reg[1]_32 ,\n \\po_stg2_wrcal_cnt_reg[1]_33 ,\n \\po_stg2_wrcal_cnt_reg[1]_34 ,\n \\po_stg2_wrcal_cnt_reg[1]_35 ,\n \\po_stg2_wrcal_cnt_reg[1]_36 ,\n \\po_stg2_wrcal_cnt_reg[1]_37 ,\n \\po_stg2_wrcal_cnt_reg[1]_38 ,\n \\po_stg2_wrcal_cnt_reg[1]_39 ,\n \\po_stg2_wrcal_cnt_reg[1]_40 ,\n \\po_stg2_wrcal_cnt_reg[1]_41 ,\n \\po_stg2_wrcal_cnt_reg[1]_42 ,\n \\po_stg2_wrcal_cnt_reg[1]_43 ,\n \\po_stg2_wrcal_cnt_reg[1]_44 ,\n \\po_stg2_wrcal_cnt_reg[1]_45 ,\n \\po_stg2_wrcal_cnt_reg[1]_46 ,\n \\po_stg2_wrcal_cnt_reg[1]_47 ,\n \\po_stg2_wrcal_cnt_reg[1]_48 ,\n \\po_stg2_wrcal_cnt_reg[1]_49 ,\n \\po_stg2_wrcal_cnt_reg[1]_50 ,\n \\po_stg2_wrcal_cnt_reg[1]_51 ,\n \\po_stg2_wrcal_cnt_reg[1]_52 ,\n \\po_stg2_wrcal_cnt_reg[1]_53 ,\n \\po_stg2_wrcal_cnt_reg[1]_54 ,\n \\po_stg2_wrcal_cnt_reg[1]_55 ,\n \\po_stg2_wrcal_cnt_reg[1]_56 ,\n \\po_stg2_wrcal_cnt_reg[1]_57 ,\n \\po_stg2_wrcal_cnt_reg[1]_58 ,\n \\po_stg2_wrcal_cnt_reg[1]_59 ,\n \\po_stg2_wrcal_cnt_reg[1]_60 ,\n \\po_stg2_wrcal_cnt_reg[1]_61 ,\n rstdiv0_sync_r1_reg_rep__4,\n rstdiv0_sync_r1_reg_rep__5,\n Q,\n idelay_ld_rst,\n idelay_ld_rst_3,\n idelay_ld_rst_4,\n idelay_ld_rst_5,\n rstdiv0_sync_r1_reg_rep__25,\n rstdiv0_sync_r1_reg_rep__25_0,\n rstdiv0_sync_r1_reg_rep__24,\n \\sm_r_reg[0]_0 ,\n fine_delay_sel_r,\n fine_delay_mod,\n mc_cas_n,\n \\rd_ptr_reg[3] ,\n \\my_empty_reg[1] ,\n mem_out,\n \\my_empty_reg[1]_0 ,\n mc_ras_n,\n mc_odt,\n \\rd_ptr_reg[3]_0 ,\n \\my_empty_reg[1]_1 ,\n mc_cke,\n mc_we_n,\n mc_address,\n \\rd_ptr_reg[3]_1 ,\n \\my_empty_reg[1]_2 ,\n mc_bank,\n \\rd_ptr_reg[3]_2 ,\n \\my_empty_reg[1]_3 ,\n \\rd_ptr_reg[3]_3 ,\n \\my_empty_reg[1]_4 ,\n \\rd_ptr_reg[3]_4 ,\n \\my_empty_reg[1]_5 ,\n \\rd_ptr_reg[3]_5 ,\n \\my_empty_reg[1]_6 ,\n mc_cs_n,\n \\pi_counter_read_val_reg[5] ,\n \\po_counter_read_val_reg[2] ,\n rstdiv0_sync_r1_reg_rep__25_1,\n rstdiv0_sync_r1_reg_rep__25_2,\n \\mmcm_init_trail_reg[0] ,\n \\mmcm_current_reg[0] ,\n \\po_counter_read_val_reg[8]_30 ,\n \\po_counter_read_val_reg[8]_31 ,\n \\po_counter_read_val_reg[5] ,\n \\A[2]__2_0 ,\n psdone,\n rstdiv0_sync_r1_reg_rep__0,\n rstdiv0_sync_r1_reg_rep__19,\n \\byte_r_reg[0]_0 ,\n fine_adjust_reg,\n samp_edge_cnt0_en_r_reg,\n pi_cnt_dec_reg,\n rstdiv0_sync_r1_reg_rep__23_0,\n p_81_in,\n rstdiv0_sync_r1_reg_rep__23_1,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ,\n my_empty,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ,\n my_empty_6,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ,\n my_empty_7,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ,\n my_empty_8,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ,\n po_cnt_dec_reg,\n \\device_temp_r_reg[11] ,\n mc_wrdata_en,\n \\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[2] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[3] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ,\n mc_cmd,\n \\cmd_pipe_plus.mc_data_offset_reg[0]_0 ,\n \\cmd_pipe_plus.mc_data_offset_reg[1]_0 ,\n \\cmd_pipe_plus.mc_data_offset_reg[2] ,\n \\cmd_pipe_plus.mc_data_offset_reg[3] ,\n \\cmd_pipe_plus.mc_data_offset_reg[4]_0 ,\n \\cmd_pipe_plus.mc_data_offset_reg[5]_0 ,\n \\stg3_r_reg[0] ,\n pd_out);\n output idelay_inc;\n output [33:0]phy_dout;\n output phy_if_reset;\n output \\samps_r_reg[9] ;\n output \\my_empty_reg[7] ;\n output \\rd_ptr_timing_reg[0] ;\n output app_zq_r_reg;\n output \\periodic_rd_generation.periodic_rd_timer_r_reg[1] ;\n output init_calib_complete_r_reg;\n output \\pi_rst_stg1_cal_r_reg[0] ;\n output samp_edge_cnt0_en_r;\n output pi_en_stg2_f_timing_reg;\n output out;\n output dqs_po_en_stg2_f_reg;\n output prbs_rdlvl_start_r_reg;\n output [1:0]A;\n output fine_delay_sel_r_reg;\n output [33:0]\\rd_ptr_timing_reg[0]_0 ;\n output [71:0]\\my_empty_reg[7]_0 ;\n output [71:0]\\my_empty_reg[7]_1 ;\n output [71:0]\\my_empty_reg[7]_2 ;\n output [71:0]\\my_empty_reg[7]_3 ;\n output LD0;\n output [2:0]\\po_rdval_cnt_reg[8] ;\n output LD0_0;\n output LD0_1;\n output LD0_2;\n output D_po_counter_read_en122_out;\n output D_po_fine_enable107_out;\n output D_po_coarse_enable110_out;\n output D_po_fine_inc113_out;\n output D_po_sel_fine_oclk_delay125_out;\n output \\po_counter_read_val_reg[8] ;\n output \\po_counter_read_val_reg[8]_0 ;\n output \\po_counter_read_val_reg[8]_1 ;\n output \\po_counter_read_val_reg[8]_2 ;\n output \\po_counter_read_val_reg[8]_3 ;\n output \\po_counter_read_val_reg[8]_4 ;\n output \\po_counter_read_val_reg[8]_5 ;\n output \\po_counter_read_val_reg[8]_6 ;\n output \\po_counter_read_val_reg[8]_7 ;\n output \\po_counter_read_val_reg[8]_8 ;\n output \\po_counter_read_val_reg[8]_9 ;\n output \\po_counter_read_val_reg[8]_10 ;\n output \\po_counter_read_val_reg[8]_11 ;\n output [0:0]E;\n output \\po_counter_read_val_reg[8]_12 ;\n output \\po_counter_read_val_reg[8]_13 ;\n output \\po_counter_read_val_reg[8]_14 ;\n output \\po_counter_read_val_reg[8]_15 ;\n output \\pi_dqs_found_lanes_r1_reg[3] ;\n output [0:0]\\fine_delay_r_reg[5] ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n output \\po_counter_read_val_reg[8]_16 ;\n output \\po_counter_read_val_reg[8]_17 ;\n output \\po_counter_read_val_reg[8]_18 ;\n output ififo_rst_reg;\n output \\pi_dqs_found_lanes_r1_reg[3]_0 ;\n output \\pi_dqs_found_lanes_r1_reg[3]_1 ;\n output \\pi_dqs_found_lanes_r1_reg[3]_2 ;\n output \\pi_dqs_found_lanes_r1_reg[2] ;\n output [0:0]\\fine_delay_r_reg[5]_0 ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n output \\po_counter_read_val_reg[8]_19 ;\n output \\po_counter_read_val_reg[8]_20 ;\n output \\po_counter_read_val_reg[8]_21 ;\n output ififo_rst_reg_0;\n output \\pi_dqs_found_lanes_r1_reg[2]_0 ;\n output \\pi_dqs_found_lanes_r1_reg[2]_1 ;\n output \\pi_dqs_found_lanes_r1_reg[2]_2 ;\n output \\pi_dqs_found_lanes_r1_reg[1] ;\n output [0:0]\\fine_delay_r_reg[5]_1 ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;\n output \\po_counter_read_val_reg[8]_22 ;\n output \\po_counter_read_val_reg[8]_23 ;\n output \\po_counter_read_val_reg[8]_24 ;\n output ififo_rst_reg_1;\n output \\pi_dqs_found_lanes_r1_reg[1]_0 ;\n output \\pi_dqs_found_lanes_r1_reg[1]_1 ;\n output \\pi_dqs_found_lanes_r1_reg[1]_2 ;\n output [7:0]D;\n output [5:0]COUNTERLOADVAL;\n output \\pi_dqs_found_lanes_r1_reg[0] ;\n output [0:0]\\fine_delay_r_reg[2] ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;\n output \\po_counter_read_val_reg[8]_25 ;\n output \\po_counter_read_val_reg[8]_26 ;\n output \\po_counter_read_val_reg[8]_27 ;\n output ififo_rst_reg_2;\n output \\pi_dqs_found_lanes_r1_reg[0]_0 ;\n output \\pi_dqs_found_lanes_r1_reg[0]_1 ;\n output \\pi_dqs_found_lanes_r1_reg[0]_2 ;\n output \\po_counter_read_val_reg[8]_28 ;\n output \\po_counter_read_val_reg[8]_29 ;\n output stg3_dec2init_val_r_reg;\n output stg3_inc2init_val_r_reg;\n output A_1__s_port_;\n output [1:0]\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 ;\n output \\A[1]__4 ;\n output [2:0]D2;\n output [2:0]D0;\n output [2:0]D3;\n output [3:0]D5;\n output [3:0]D6;\n output [2:0]D1;\n output [7:0]\\rd_ptr_timing_reg[0]_1 ;\n output [3:0]D7;\n output [3:0]D8;\n output [7:0]\\rd_ptr_timing_reg[0]_2 ;\n output [3:0]\\my_empty_reg[7]_4 ;\n output [3:0]\\my_empty_reg[7]_5 ;\n output [3:0]\\my_empty_reg[7]_6 ;\n output [3:0]D4;\n output [3:0]\\my_empty_reg[7]_7 ;\n output [3:0]\\my_empty_reg[7]_8 ;\n output [3:0]\\my_empty_reg[7]_9 ;\n output [3:0]\\my_empty_reg[7]_10 ;\n output [3:0]\\my_full_reg[3] ;\n output [3:0]\\rd_ptr_timing_reg[0]_3 ;\n output [3:0]D9;\n output [7:0]\\my_empty_reg[7]_11 ;\n output [7:0]\\my_empty_reg[7]_12 ;\n output [7:0]\\my_empty_reg[7]_13 ;\n output [7:0]\\my_empty_reg[7]_14 ;\n output [7:0]\\my_empty_reg[7]_15 ;\n output [7:0]\\my_empty_reg[7]_16 ;\n output [7:0]\\my_empty_reg[7]_17 ;\n output [7:0]\\my_empty_reg[7]_18 ;\n output [7:0]\\my_empty_reg[7]_19 ;\n output [7:0]\\my_empty_reg[7]_20 ;\n output [7:0]\\my_empty_reg[7]_21 ;\n output [7:0]\\my_empty_reg[7]_22 ;\n output [7:0]\\my_empty_reg[7]_23 ;\n output [7:0]\\my_empty_reg[7]_24 ;\n output [7:0]\\my_empty_reg[7]_25 ;\n output [7:0]\\my_empty_reg[7]_26 ;\n output [7:0]\\my_empty_reg[7]_27 ;\n output [7:0]\\my_empty_reg[7]_28 ;\n output [7:0]\\my_empty_reg[7]_29 ;\n output [7:0]\\my_empty_reg[7]_30 ;\n output [7:0]\\my_empty_reg[7]_31 ;\n output [7:0]\\my_empty_reg[7]_32 ;\n output [7:0]\\my_empty_reg[7]_33 ;\n output [7:0]\\my_empty_reg[7]_34 ;\n output [7:0]\\my_empty_reg[7]_35 ;\n output [7:0]\\my_empty_reg[7]_36 ;\n output [7:0]\\my_empty_reg[7]_37 ;\n output [7:0]\\my_empty_reg[7]_38 ;\n output [7:0]\\my_empty_reg[7]_39 ;\n output [7:0]\\my_empty_reg[7]_40 ;\n output [7:0]\\my_empty_reg[7]_41 ;\n output [7:0]\\my_empty_reg[7]_42 ;\n output \\byte_r_reg[0] ;\n output \\byte_r_reg[1] ;\n output \\stg2_tap_cnt_reg[0] ;\n output \\sm_r_reg[0] ;\n output [0:0]\\zero2fuzz_r_reg[0] ;\n output maint_prescaler_r1;\n output \\cmd_pipe_plus.mc_data_offset_reg[4] ;\n output [5:0]\\cmd_pipe_plus.mc_data_offset_reg[5] ;\n output \\cmd_pipe_plus.mc_data_offset_reg[1] ;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[4] ;\n output [5:0]\\cmd_pipe_plus.mc_data_offset_1_reg[5] ;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[1] ;\n output \\cmd_pipe_plus.mc_data_offset_reg[0] ;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[0] ;\n output [1:0]\\rdlvl_dqs_tap_cnt_r_reg[0][3][0] ;\n output [1:0]\\idelay_tap_cnt_r_reg[0][3][0] ;\n output \\en_cnt_div4.enable_wrlvl_cnt_reg[3] ;\n output \\complex_row_cnt_ocal_reg[0] ;\n output \\row_cnt_victim_rotate.complex_row_cnt_reg[4] ;\n output \\fine_delay_mod_reg[5] ;\n output \\fine_delay_mod_reg[20] ;\n output [10:0]\\phy_ctl_wd_i1_reg[24] ;\n output phy_write_calib;\n output phy_read_calib;\n output \\fine_delay_mod_reg[26] ;\n output \\genblk9[1].fine_delay_incdec_pb_reg[1] ;\n output \\genblk9[2].fine_delay_incdec_pb_reg[2] ;\n output \\genblk9[3].fine_delay_incdec_pb_reg[3] ;\n output \\genblk9[5].fine_delay_incdec_pb_reg[5] ;\n output \\genblk9[6].fine_delay_incdec_pb_reg[6] ;\n output \\genblk9[7].fine_delay_incdec_pb_reg[7] ;\n output mux_wrdata_en;\n output mux_cmd_wren;\n output mux_reset_n;\n output [5:0]\\data_offset_1_i1_reg[5] ;\n output [1:0]\\rd_ptr_timing_reg[0]_4 ;\n output [1:0]\\my_full_reg[3]_0 ;\n output \\byte_sel_data_map_reg[1] ;\n output \\A[0]__4 ;\n output \\A[0]__0 ;\n output \\A[2]__2 ;\n output \\A[1]__0 ;\n output \\A[1]__4_0 ;\n output \\A[1]__3 ;\n output \\A[2]__1 ;\n output [5:0]\\pi_dqs_found_lanes_r1_reg[1]_3 ;\n output [5:0]\\pi_dqs_found_lanes_r1_reg[2]_3 ;\n output [5:0]\\pi_dqs_found_lanes_r1_reg[3]_3 ;\n output [7:0]\\fine_delay_r_reg[26] ;\n output [7:0]\\fine_delay_r_reg[26]_0 ;\n output [7:0]\\fine_delay_r_reg[26]_1 ;\n output [0:0]\\qcntr_r_reg[0] ;\n input CLK;\n input rstdiv0_sync_r1_reg_rep__20;\n input poc_sample_pd;\n input rstdiv0_sync_r1_reg_rep__10;\n input rstdiv0_sync_r1_reg_rep__9;\n input phy_rddata_en;\n input \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;\n input \\po_stg2_wrcal_cnt_reg[1] ;\n input \\po_stg2_wrcal_cnt_reg[1]_0 ;\n input \\po_stg2_wrcal_cnt_reg[1]_1 ;\n input \\po_stg2_wrcal_cnt_reg[1]_2 ;\n input \\mcGo_r_reg[15] ;\n input [3:0]in0;\n input [0:0]rstdiv0_sync_r1_reg_rep__12;\n input [0:0]SR;\n input rstdiv0_sync_r1_reg_rep__23;\n input rstdiv0_sync_r1_reg_rep__13;\n input [1:0]rstdiv0_sync_r1_reg_rep__14;\n input \\rd_mux_sel_r_reg[1] ;\n input \\rd_mux_sel_r_reg[1]_0 ;\n input \\rd_mux_sel_r_reg[1]_1 ;\n input \\rd_mux_sel_r_reg[1]_2 ;\n input \\rd_mux_sel_r_reg[1]_3 ;\n input \\rd_mux_sel_r_reg[1]_4 ;\n input \\rd_mux_sel_r_reg[1]_5 ;\n input \\rd_mux_sel_r_reg[1]_6 ;\n input \\rd_mux_sel_r_reg[1]_7 ;\n input \\rd_mux_sel_r_reg[1]_8 ;\n input \\rd_mux_sel_r_reg[1]_9 ;\n input \\rd_mux_sel_r_reg[1]_10 ;\n input \\rd_mux_sel_r_reg[1]_11 ;\n input \\rd_mux_sel_r_reg[1]_12 ;\n input \\rd_mux_sel_r_reg[1]_13 ;\n input \\rd_mux_sel_r_reg[1]_14 ;\n input \\rd_mux_sel_r_reg[1]_15 ;\n input \\rd_mux_sel_r_reg[1]_16 ;\n input \\rd_mux_sel_r_reg[1]_17 ;\n input \\rd_mux_sel_r_reg[1]_18 ;\n input \\rd_mux_sel_r_reg[1]_19 ;\n input \\rd_mux_sel_r_reg[1]_20 ;\n input \\rd_mux_sel_r_reg[1]_21 ;\n input \\rd_mux_sel_r_reg[1]_22 ;\n input \\rd_mux_sel_r_reg[1]_23 ;\n input \\rd_mux_sel_r_reg[1]_24 ;\n input \\rd_mux_sel_r_reg[1]_25 ;\n input \\rd_mux_sel_r_reg[1]_26 ;\n input \\rd_mux_sel_r_reg[1]_27 ;\n input \\rd_mux_sel_r_reg[1]_28 ;\n input \\rd_mux_sel_r_reg[1]_29 ;\n input \\rd_mux_sel_r_reg[1]_30 ;\n input \\rd_mux_sel_r_reg[1]_31 ;\n input \\rd_mux_sel_r_reg[1]_32 ;\n input \\rd_mux_sel_r_reg[1]_33 ;\n input \\rd_mux_sel_r_reg[1]_34 ;\n input \\rd_mux_sel_r_reg[1]_35 ;\n input \\rd_mux_sel_r_reg[1]_36 ;\n input \\rd_mux_sel_r_reg[1]_37 ;\n input \\rd_mux_sel_r_reg[1]_38 ;\n input \\rd_mux_sel_r_reg[1]_39 ;\n input \\rd_mux_sel_r_reg[1]_40 ;\n input \\rd_mux_sel_r_reg[1]_41 ;\n input \\rd_mux_sel_r_reg[1]_42 ;\n input \\rd_mux_sel_r_reg[1]_43 ;\n input \\rd_mux_sel_r_reg[1]_44 ;\n input \\rd_mux_sel_r_reg[1]_45 ;\n input \\rd_mux_sel_r_reg[1]_46 ;\n input \\rd_mux_sel_r_reg[1]_47 ;\n input \\rd_mux_sel_r_reg[1]_48 ;\n input \\rd_mux_sel_r_reg[1]_49 ;\n input \\rd_mux_sel_r_reg[1]_50 ;\n input \\rd_mux_sel_r_reg[1]_51 ;\n input \\rd_mux_sel_r_reg[1]_52 ;\n input \\rd_mux_sel_r_reg[1]_53 ;\n input \\rd_mux_sel_r_reg[1]_54 ;\n input \\rd_mux_sel_r_reg[1]_55 ;\n input \\rd_mux_sel_r_reg[1]_56 ;\n input \\rd_mux_sel_r_reg[1]_57 ;\n input \\rd_mux_sel_r_reg[1]_58 ;\n input \\rd_mux_sel_r_reg[1]_59 ;\n input \\rd_mux_sel_r_reg[1]_60 ;\n input \\rd_mux_sel_r_reg[1]_61 ;\n input \\rd_mux_sel_r_reg[1]_62 ;\n input rstdiv0_sync_r1_reg_rep__22;\n input A_rst_primitives_reg;\n input rstdiv0_sync_r1_reg_rep__11;\n input cnt_pwron_reset_done_r0;\n input [1:0]rstdiv0_sync_r1_reg_rep__17;\n input [0:0]rstdiv0_sync_r1_reg_rep__16;\n input [0:0]SS;\n input tempmon_sample_en;\n input rstdiv0_sync_r1_reg_rep__2;\n input rstdiv0_sync_r1_reg_rep__6;\n input \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ;\n input [0:0]rstdiv0_sync_r1_reg_rep__7;\n input \\A[1]_0 ;\n input \\A[1]_1 ;\n input \\A[1]_2 ;\n input \\A[1]_3 ;\n input \\A[1]_4 ;\n input \\A[1]_5 ;\n input \\A[1]_6 ;\n input \\A[1]_7 ;\n input \\A[1]_8 ;\n input \\A[1]_9 ;\n input \\A[1]_10 ;\n input \\A[1]_11 ;\n input \\A[1]_12 ;\n input \\A[1]_13 ;\n input \\A[1]_14 ;\n input \\A[1]_15 ;\n input \\A[1]_16 ;\n input \\A[1]_17 ;\n input \\A[1]_18 ;\n input \\A[1]_19 ;\n input \\A[1]_20 ;\n input \\A[1]_21 ;\n input \\A[1]_22 ;\n input \\A[1]_23 ;\n input \\A[1]_24 ;\n input \\A[1]_25 ;\n input \\A[1]_26 ;\n input \\A[1]_27 ;\n input \\A[1]_28 ;\n input \\A[1]_29 ;\n input \\A[1]_30 ;\n input \\A[1]_31 ;\n input \\A[1]_32 ;\n input \\A[1]_33 ;\n input \\A[1]_34 ;\n input \\A[1]_35 ;\n input \\A[1]_36 ;\n input \\A[1]_37 ;\n input \\A[1]_38 ;\n input \\A[1]_39 ;\n input \\A[1]_40 ;\n input \\A[1]_41 ;\n input \\A[1]_42 ;\n input \\A[1]_43 ;\n input \\A[1]_44 ;\n input \\A[1]_45 ;\n input \\A[1]_46 ;\n input \\A[1]_47 ;\n input \\A[1]_48 ;\n input \\A[1]_49 ;\n input \\A[1]_50 ;\n input \\A[1]_51 ;\n input \\A[1]_52 ;\n input \\A[1]_53 ;\n input \\A[1]_54 ;\n input \\A[1]_55 ;\n input \\A[1]_56 ;\n input \\A[1]_57 ;\n input \\A[1]_58 ;\n input \\A[1]_59 ;\n input \\A[1]_60 ;\n input \\A[1]_61 ;\n input \\A[1]_62 ;\n input \\A[1]_63 ;\n input rstdiv0_sync_r1_reg_rep__8;\n input rstdiv0_sync_r1_reg_rep;\n input p_0_out;\n input \\po_stg2_wrcal_cnt_reg[1]_3 ;\n input \\po_stg2_wrcal_cnt_reg[1]_4 ;\n input \\po_stg2_wrcal_cnt_reg[1]_5 ;\n input \\po_stg2_wrcal_cnt_reg[1]_6 ;\n input \\po_stg2_wrcal_cnt_reg[1]_7 ;\n input \\po_stg2_wrcal_cnt_reg[1]_8 ;\n input \\po_stg2_wrcal_cnt_reg[1]_9 ;\n input \\po_stg2_wrcal_cnt_reg[1]_10 ;\n input \\po_stg2_wrcal_cnt_reg[1]_11 ;\n input \\po_stg2_wrcal_cnt_reg[1]_12 ;\n input \\po_stg2_wrcal_cnt_reg[1]_13 ;\n input \\po_stg2_wrcal_cnt_reg[1]_14 ;\n input \\po_stg2_wrcal_cnt_reg[1]_15 ;\n input \\po_stg2_wrcal_cnt_reg[1]_16 ;\n input \\po_stg2_wrcal_cnt_reg[1]_17 ;\n input \\po_stg2_wrcal_cnt_reg[1]_18 ;\n input \\po_stg2_wrcal_cnt_reg[1]_19 ;\n input \\po_stg2_wrcal_cnt_reg[1]_20 ;\n input \\po_stg2_wrcal_cnt_reg[1]_21 ;\n input \\po_stg2_wrcal_cnt_reg[1]_22 ;\n input \\po_stg2_wrcal_cnt_reg[1]_23 ;\n input \\po_stg2_wrcal_cnt_reg[1]_24 ;\n input \\po_stg2_wrcal_cnt_reg[1]_25 ;\n input \\po_stg2_wrcal_cnt_reg[1]_26 ;\n input \\po_stg2_wrcal_cnt_reg[1]_27 ;\n input \\po_stg2_wrcal_cnt_reg[1]_28 ;\n input \\po_stg2_wrcal_cnt_reg[1]_29 ;\n input \\po_stg2_wrcal_cnt_reg[1]_30 ;\n input \\po_stg2_wrcal_cnt_reg[1]_31 ;\n input \\po_stg2_wrcal_cnt_reg[1]_32 ;\n input \\po_stg2_wrcal_cnt_reg[1]_33 ;\n input \\po_stg2_wrcal_cnt_reg[1]_34 ;\n input \\po_stg2_wrcal_cnt_reg[1]_35 ;\n input \\po_stg2_wrcal_cnt_reg[1]_36 ;\n input \\po_stg2_wrcal_cnt_reg[1]_37 ;\n input \\po_stg2_wrcal_cnt_reg[1]_38 ;\n input \\po_stg2_wrcal_cnt_reg[1]_39 ;\n input \\po_stg2_wrcal_cnt_reg[1]_40 ;\n input \\po_stg2_wrcal_cnt_reg[1]_41 ;\n input \\po_stg2_wrcal_cnt_reg[1]_42 ;\n input \\po_stg2_wrcal_cnt_reg[1]_43 ;\n input \\po_stg2_wrcal_cnt_reg[1]_44 ;\n input \\po_stg2_wrcal_cnt_reg[1]_45 ;\n input \\po_stg2_wrcal_cnt_reg[1]_46 ;\n input \\po_stg2_wrcal_cnt_reg[1]_47 ;\n input \\po_stg2_wrcal_cnt_reg[1]_48 ;\n input \\po_stg2_wrcal_cnt_reg[1]_49 ;\n input \\po_stg2_wrcal_cnt_reg[1]_50 ;\n input \\po_stg2_wrcal_cnt_reg[1]_51 ;\n input \\po_stg2_wrcal_cnt_reg[1]_52 ;\n input \\po_stg2_wrcal_cnt_reg[1]_53 ;\n input \\po_stg2_wrcal_cnt_reg[1]_54 ;\n input \\po_stg2_wrcal_cnt_reg[1]_55 ;\n input \\po_stg2_wrcal_cnt_reg[1]_56 ;\n input \\po_stg2_wrcal_cnt_reg[1]_57 ;\n input \\po_stg2_wrcal_cnt_reg[1]_58 ;\n input \\po_stg2_wrcal_cnt_reg[1]_59 ;\n input \\po_stg2_wrcal_cnt_reg[1]_60 ;\n input \\po_stg2_wrcal_cnt_reg[1]_61 ;\n input [0:0]rstdiv0_sync_r1_reg_rep__4;\n input rstdiv0_sync_r1_reg_rep__5;\n input [287:0]Q;\n input idelay_ld_rst;\n input idelay_ld_rst_3;\n input idelay_ld_rst_4;\n input idelay_ld_rst_5;\n input rstdiv0_sync_r1_reg_rep__25;\n input rstdiv0_sync_r1_reg_rep__25_0;\n input rstdiv0_sync_r1_reg_rep__24;\n input [0:0]\\sm_r_reg[0]_0 ;\n input fine_delay_sel_r;\n input [8:0]fine_delay_mod;\n input [2:0]mc_cas_n;\n input [37:0]\\rd_ptr_reg[3] ;\n input \\my_empty_reg[1] ;\n input [5:0]mem_out;\n input \\my_empty_reg[1]_0 ;\n input [2:0]mc_ras_n;\n input [0:0]mc_odt;\n input [11:0]\\rd_ptr_reg[3]_0 ;\n input \\my_empty_reg[1]_1 ;\n input [0:0]mc_cke;\n input [2:0]mc_we_n;\n input [35:0]mc_address;\n input [31:0]\\rd_ptr_reg[3]_1 ;\n input \\my_empty_reg[1]_2 ;\n input [8:0]mc_bank;\n input [63:0]\\rd_ptr_reg[3]_2 ;\n input \\my_empty_reg[1]_3 ;\n input [63:0]\\rd_ptr_reg[3]_3 ;\n input \\my_empty_reg[1]_4 ;\n input [63:0]\\rd_ptr_reg[3]_4 ;\n input \\my_empty_reg[1]_5 ;\n input [63:0]\\rd_ptr_reg[3]_5 ;\n input \\my_empty_reg[1]_6 ;\n input [0:0]mc_cs_n;\n input [5:0]\\pi_counter_read_val_reg[5] ;\n input \\po_counter_read_val_reg[2] ;\n input rstdiv0_sync_r1_reg_rep__25_1;\n input rstdiv0_sync_r1_reg_rep__25_2;\n input \\mmcm_init_trail_reg[0] ;\n input \\mmcm_current_reg[0] ;\n input [4:0]\\po_counter_read_val_reg[8]_30 ;\n input [4:0]\\po_counter_read_val_reg[8]_31 ;\n input [5:0]\\po_counter_read_val_reg[5] ;\n input \\A[2]__2_0 ;\n input psdone;\n input rstdiv0_sync_r1_reg_rep__0;\n input [0:0]rstdiv0_sync_r1_reg_rep__19;\n input [63:0]\\byte_r_reg[0]_0 ;\n input fine_adjust_reg;\n input samp_edge_cnt0_en_r_reg;\n input [0:0]pi_cnt_dec_reg;\n input rstdiv0_sync_r1_reg_rep__23_0;\n input p_81_in;\n input rstdiv0_sync_r1_reg_rep__23_1;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;\n input [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;\n input [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ;\n input [0:0]my_empty;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;\n input [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;\n input [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ;\n input [0:0]my_empty_6;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;\n input [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;\n input [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ;\n input [0:0]my_empty_7;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ;\n input [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ;\n input [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ;\n input [0:0]my_empty_8;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;\n input [0:0]po_cnt_dec_reg;\n input [11:0]\\device_temp_r_reg[11] ;\n input mc_wrdata_en;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[2] ;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[3] ;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ;\n input [1:0]mc_cmd;\n input \\cmd_pipe_plus.mc_data_offset_reg[0]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_reg[1]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_reg[2] ;\n input \\cmd_pipe_plus.mc_data_offset_reg[3] ;\n input \\cmd_pipe_plus.mc_data_offset_reg[4]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_reg[5]_0 ;\n input \\stg3_r_reg[0] ;\n input pd_out;\n\n wire [1:0]A;\n wire \\A[0]__0 ;\n wire \\A[0]__4 ;\n wire \\A[1]_0 ;\n wire \\A[1]_1 ;\n wire \\A[1]_10 ;\n wire \\A[1]_11 ;\n wire \\A[1]_12 ;\n wire \\A[1]_13 ;\n wire \\A[1]_14 ;\n wire \\A[1]_15 ;\n wire \\A[1]_16 ;\n wire \\A[1]_17 ;\n wire \\A[1]_18 ;\n wire \\A[1]_19 ;\n wire \\A[1]_2 ;\n wire \\A[1]_20 ;\n wire \\A[1]_21 ;\n wire \\A[1]_22 ;\n wire \\A[1]_23 ;\n wire \\A[1]_24 ;\n wire \\A[1]_25 ;\n wire \\A[1]_26 ;\n wire \\A[1]_27 ;\n wire \\A[1]_28 ;\n wire \\A[1]_29 ;\n wire \\A[1]_3 ;\n wire \\A[1]_30 ;\n wire \\A[1]_31 ;\n wire \\A[1]_32 ;\n wire \\A[1]_33 ;\n wire \\A[1]_34 ;\n wire \\A[1]_35 ;\n wire \\A[1]_36 ;\n wire \\A[1]_37 ;\n wire \\A[1]_38 ;\n wire \\A[1]_39 ;\n wire \\A[1]_4 ;\n wire \\A[1]_40 ;\n wire \\A[1]_41 ;\n wire \\A[1]_42 ;\n wire \\A[1]_43 ;\n wire \\A[1]_44 ;\n wire \\A[1]_45 ;\n wire \\A[1]_46 ;\n wire \\A[1]_47 ;\n wire \\A[1]_48 ;\n wire \\A[1]_49 ;\n wire \\A[1]_5 ;\n wire \\A[1]_50 ;\n wire \\A[1]_51 ;\n wire \\A[1]_52 ;\n wire \\A[1]_53 ;\n wire \\A[1]_54 ;\n wire \\A[1]_55 ;\n wire \\A[1]_56 ;\n wire \\A[1]_57 ;\n wire \\A[1]_58 ;\n wire \\A[1]_59 ;\n wire \\A[1]_6 ;\n wire \\A[1]_60 ;\n wire \\A[1]_61 ;\n wire \\A[1]_62 ;\n wire \\A[1]_63 ;\n wire \\A[1]_7 ;\n wire \\A[1]_8 ;\n wire \\A[1]_9 ;\n wire \\A[1]__0 ;\n wire \\A[1]__3 ;\n wire \\A[1]__4 ;\n wire \\A[1]__4_0 ;\n wire \\A[2]__1 ;\n wire \\A[2]__2 ;\n wire \\A[2]__2_0 ;\n wire A_1__s_net_1;\n wire A_rst_primitives_reg;\n wire CLK;\n wire [5:0]COUNTERLOADVAL;\n wire [7:0]D;\n wire [2:0]D0;\n wire [2:0]D1;\n wire [2:0]D2;\n wire [2:0]D3;\n wire [3:0]D4;\n wire [3:0]D5;\n wire [3:0]D6;\n wire [3:0]D7;\n wire [3:0]D8;\n wire [3:0]D9;\n wire D_po_coarse_enable110_out;\n wire D_po_counter_read_en122_out;\n wire D_po_fine_enable107_out;\n wire D_po_fine_inc113_out;\n wire D_po_sel_fine_oclk_delay125_out;\n wire [0:0]E;\n wire LD0;\n wire LD0_0;\n wire LD0_1;\n wire LD0_2;\n wire [287:0]Q;\n wire [0:0]SR;\n wire [0:0]SS;\n wire app_zq_r_reg;\n wire bit_cnt;\n wire burst_addr_r_i_1_n_0;\n wire \\byte_r_reg[0] ;\n wire [63:0]\\byte_r_reg[0]_0 ;\n wire \\byte_r_reg[1] ;\n wire [2:2]byte_sel_cnt;\n wire \\byte_sel_data_map_reg[1] ;\n wire cal1_cnt_cpt_r1;\n wire cal1_state_r1535_out;\n wire cal1_wait_r;\n wire cal2_done_r;\n wire cal2_done_r_i_1_n_0;\n wire cal2_if_reset_i_1_n_0;\n wire calib_complete;\n wire calib_in_common;\n wire [1:1]calib_zero_inputs;\n wire [0:0]calib_zero_inputs__0;\n wire ck_addr_cmd_delay_done;\n wire ck_po_stg2_f_en;\n wire ck_po_stg2_f_en_i_1_n_0;\n wire ck_po_stg2_f_indec;\n wire ck_po_stg2_f_indec_i_1_n_0;\n wire cmd_delay_start0;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[0] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[1] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[2] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[3] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[4] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ;\n wire [5:0]\\cmd_pipe_plus.mc_data_offset_1_reg[5] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[0] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[0]_0 ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[1] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[1]_0 ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[2] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[3] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[4] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[4]_0 ;\n wire [5:0]\\cmd_pipe_plus.mc_data_offset_reg[5] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[5]_0 ;\n wire cmd_po_en_stg2_f;\n wire cnt_cmd_done_r;\n wire cnt_dllk_zqinit_done_r;\n wire cnt_dllk_zqinit_done_r_i_1_n_0;\n wire [7:6]cnt_dllk_zqinit_r_reg__0;\n wire cnt_init_af_done_r;\n wire cnt_init_af_done_r_i_1_n_0;\n wire [1:0]cnt_init_af_r;\n wire cnt_init_mr_done_r;\n wire cnt_init_mr_done_r_i_1_n_0;\n wire [1:0]cnt_init_mr_r;\n wire cnt_init_mr_r1;\n wire cnt_pwron_cke_done_r;\n wire cnt_pwron_cke_done_r_i_1_n_0;\n wire [7:0]cnt_pwron_r_reg__0;\n wire cnt_pwron_reset_done_r;\n wire cnt_pwron_reset_done_r0;\n wire cnt_pwron_reset_done_r_i_1_n_0;\n wire cnt_shift_r0;\n wire cnt_txpr_done_r;\n wire cnt_txpr_done_r_i_1_n_0;\n wire [2:0]cnt_txpr_r_reg__0;\n wire cnt_wait_state;\n wire complex_act_start;\n wire complex_init_pi_dec_done;\n wire complex_init_pi_dec_done_r_i_1_n_0;\n wire complex_ocal_num_samples_done_r;\n wire [2:0]complex_ocal_rd_victim_sel;\n wire complex_ocal_ref_req;\n wire complex_ocal_reset_rd_addr;\n wire complex_oclk_calib_resume;\n wire complex_pi_incdec_done;\n wire complex_pi_incdec_done_i_1_n_0;\n wire \\complex_row_cnt_ocal_reg[0] ;\n wire [2:0]ctl_lane_cnt;\n wire ctl_lane_sel;\n wire [5:0]\\data_offset_1_i1_reg[5] ;\n wire ddr2_pre_flag_r_i_1_n_0;\n wire ddr2_refresh_flag_r;\n wire ddr2_refresh_flag_r_i_1_n_0;\n wire ddr3_lm_done_r;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_1 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_10 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_100 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_102 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_103 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_104 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_105 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_106 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_107 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_108 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_109 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_11 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_110 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_111 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_112 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_113 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_115 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_116 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_117 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_13 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_14 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_15 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_16 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_17 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_18 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_19 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_2 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_20 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_21 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_22 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_23 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_24 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_25 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_26 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_27 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_28 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_29 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_30 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_32 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_34 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_35 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_4 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_44 ;\n (* MAX_FANOUT = \"100\" *) (* RTL_MAX_FANOUT = \"found\" *) wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_45 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_50 ;\n (* MAX_FANOUT = \"100\" *) (* RTL_MAX_FANOUT = \"found\" *) wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_51 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_58 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_59 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_64 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_65 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_68 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_69 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_78 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_79 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_84 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_85 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_87 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_88 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_89 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_9 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_90 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_93 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_94 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_95 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_98 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_99 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_1 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_101 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_102 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_106 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_107 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_108 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_110 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_112 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_114 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_116 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_118 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_120 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_122 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_124 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_126 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_128 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_130 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_132 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_134 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_136 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_137 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_138 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_139 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_140 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_141 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_142 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_144 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_145 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_146 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_147 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_148 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_149 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_150 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_151 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_152 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_153 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_154 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_155 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_156 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_157 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_158 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_159 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_161 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_180 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_183 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_184 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_185 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_186 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_188 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_189 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_190 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_2 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_3 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_30 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_39 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_4 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_40 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_41 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_42 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_43 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_44 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_45 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_46 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_47 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_50 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_51 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_52 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_56 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_6 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_60 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_79 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_80 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_81 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_82 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_83 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_84 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_85 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_86 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_87 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_88 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_9 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_91 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_92 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_93 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_94 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_95 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_96 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_99 ;\n wire ddr_phy_tempmon_0_n_2;\n wire ddr_phy_tempmon_0_n_3;\n wire ddr_phy_tempmon_0_n_4;\n wire ddr_phy_tempmon_0_n_5;\n wire ddr_phy_tempmon_0_n_6;\n wire [5:0]dec_cnt_reg;\n wire detect_edge_done_r;\n wire detect_pi_found_dqs;\n wire [11:0]\\device_temp_r_reg[11] ;\n wire done_dqs_dec239_out;\n wire done_dqs_tap_inc;\n wire dq_cnt_inc_i_1_n_0;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ;\n wire [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ;\n wire [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;\n wire [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ;\n wire [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ;\n wire [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ;\n wire [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;\n wire [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;\n wire [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ;\n wire dqs_found_prech_req;\n wire dqs_found_prech_req_i_1_n_0;\n wire dqs_po_dec_done;\n wire dqs_po_dec_done_r2;\n wire dqs_po_en_stg2_f;\n wire dqs_po_en_stg2_f_reg;\n wire dqs_po_stg2_f_incdec;\n wire dqs_wl_po_stg2_c_incdec;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_10 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_100 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_101 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_102 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_105 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_106 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_107 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_108 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_12 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_13 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_14 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_27 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_41 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_42 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_43 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_44 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_46 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_5 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_69 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_70 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_72 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_74 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_75 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_76 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_81 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_82 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_83 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_84 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_85 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_86 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_87 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_88 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_89 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_9 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_90 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_91 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_92 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_93 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_94 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_96 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_97 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_98 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_99 ;\n wire early1_data_i_1_n_0;\n wire early2_data_i_1_n_0;\n wire \\en_cnt_div4.enable_wrlvl_cnt_reg[3] ;\n wire [2:1]final_coarse_tap;\n wire final_dec_done_i_1_n_0;\n wire fine_adj_state_r144_out;\n wire fine_adj_state_r16_out;\n wire fine_adjust_done_r_i_1_n_0;\n wire fine_adjust_i_1_n_0;\n wire fine_adjust_reg;\n wire [8:0]fine_delay_mod;\n wire \\fine_delay_mod_reg[20] ;\n wire \\fine_delay_mod_reg[26] ;\n wire \\fine_delay_mod_reg[5] ;\n wire [7:0]\\fine_delay_r_reg[26] ;\n wire [7:0]\\fine_delay_r_reg[26]_0 ;\n wire [7:0]\\fine_delay_r_reg[26]_1 ;\n wire [0:0]\\fine_delay_r_reg[2] ;\n wire [0:0]\\fine_delay_r_reg[5] ;\n wire [0:0]\\fine_delay_r_reg[5]_0 ;\n wire [0:0]\\fine_delay_r_reg[5]_1 ;\n wire fine_delay_sel_i_1_n_0;\n wire fine_delay_sel_r;\n wire fine_delay_sel_r_reg;\n wire fine_dly_error_i_1_n_0;\n wire first_rdlvl_pat_r;\n wire first_wrcal_pat_r;\n wire flag_ck_negedge09_out;\n wire flag_ck_negedge_i_1_n_0;\n wire found_first_edge_r_i_1_n_0;\n wire found_second_edge_r_i_1_n_0;\n wire found_stable_eye_last_r;\n wire found_stable_eye_last_r_i_1_n_0;\n wire [1:0]\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 ;\n wire \\gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[0] ;\n wire \\gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[1] ;\n wire \\gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[2] ;\n wire \\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1_n_0 ;\n wire \\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 ;\n wire \\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 ;\n wire \\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 ;\n wire \\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 ;\n wire \\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 ;\n wire \\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 ;\n wire \\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 ;\n wire \\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 ;\n wire \\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 ;\n wire \\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 ;\n wire \\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 ;\n wire \\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 ;\n wire \\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 ;\n wire \\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 ;\n wire \\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 ;\n wire \\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 ;\n wire \\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 ;\n wire \\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 ;\n wire \\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 ;\n wire \\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 ;\n wire \\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 ;\n wire \\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 ;\n wire \\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 ;\n wire \\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 ;\n wire \\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 ;\n wire \\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 ;\n wire \\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_208 ;\n wire \\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 ;\n wire \\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 ;\n wire \\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 ;\n wire \\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 ;\n wire \\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 ;\n wire \\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 ;\n wire \\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 ;\n wire \\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 ;\n wire \\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 ;\n wire \\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 ;\n wire \\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 ;\n wire \\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 ;\n wire \\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 ;\n wire \\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 ;\n wire \\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 ;\n wire \\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 ;\n wire \\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 ;\n wire \\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 ;\n wire \\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 ;\n wire \\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 ;\n wire \\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 ;\n wire \\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 ;\n wire \\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 ;\n wire \\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 ;\n wire \\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 ;\n wire \\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 ;\n wire \\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 ;\n wire \\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 ;\n wire \\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 ;\n wire \\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_212 ;\n wire \\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 ;\n wire \\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 ;\n wire \\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 ;\n wire \\gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1_n_0 ;\n wire \\gen_track_left_edge[0].pb_found_edge_r[0]_i_1_n_0 ;\n wire \\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1_n_0 ;\n wire \\gen_track_left_edge[0].pb_found_stable_eye_r_reg ;\n wire \\gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1_n_0 ;\n wire \\gen_track_left_edge[1].pb_found_edge_r[1]_i_1_n_0 ;\n wire \\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1_n_0 ;\n wire \\gen_track_left_edge[1].pb_found_stable_eye_r_reg ;\n wire \\gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1_n_0 ;\n wire \\gen_track_left_edge[2].pb_found_edge_r[2]_i_1_n_0 ;\n wire \\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1_n_0 ;\n wire \\gen_track_left_edge[2].pb_found_stable_eye_r_reg ;\n wire \\gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1_n_0 ;\n wire \\gen_track_left_edge[3].pb_found_edge_r[3]_i_1_n_0 ;\n wire \\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1_n_0 ;\n wire \\gen_track_left_edge[3].pb_found_stable_eye_r_reg ;\n wire \\gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1_n_0 ;\n wire \\gen_track_left_edge[4].pb_found_edge_r[4]_i_1_n_0 ;\n wire \\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1_n_0 ;\n wire \\gen_track_left_edge[4].pb_found_stable_eye_r_reg ;\n wire \\gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1_n_0 ;\n wire \\gen_track_left_edge[5].pb_found_edge_r[5]_i_1_n_0 ;\n wire \\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1_n_0 ;\n wire \\gen_track_left_edge[5].pb_found_stable_eye_r_reg ;\n wire \\gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1_n_0 ;\n wire \\gen_track_left_edge[6].pb_found_edge_r[6]_i_1_n_0 ;\n wire \\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1_n_0 ;\n wire \\gen_track_left_edge[6].pb_found_stable_eye_r_reg ;\n wire \\gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_2_n_0 ;\n wire \\gen_track_left_edge[7].pb_found_edge_r[7]_i_1_n_0 ;\n wire \\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1_n_0 ;\n wire \\gen_track_left_edge[7].pb_found_stable_eye_r_reg ;\n wire \\genblk8[0].left_edge_found_pb[0]_i_1_n_0 ;\n wire \\genblk8[0].left_edge_updated[0]_i_1_n_0 ;\n wire \\genblk8[0].right_edge_found_pb[0]_i_1_n_0 ;\n wire \\genblk8[1].left_edge_found_pb[1]_i_1_n_0 ;\n wire \\genblk8[1].left_edge_updated[1]_i_1_n_0 ;\n wire \\genblk8[1].right_edge_found_pb[1]_i_1_n_0 ;\n wire \\genblk8[2].left_edge_found_pb[2]_i_1_n_0 ;\n wire \\genblk8[2].left_edge_updated[2]_i_1_n_0 ;\n wire \\genblk8[2].right_edge_found_pb[2]_i_1_n_0 ;\n wire \\genblk8[3].left_edge_found_pb[3]_i_1_n_0 ;\n wire \\genblk8[3].left_edge_updated[3]_i_1_n_0 ;\n wire \\genblk8[3].right_edge_found_pb[3]_i_1_n_0 ;\n wire \\genblk8[4].left_edge_found_pb[4]_i_1_n_0 ;\n wire \\genblk8[4].left_edge_updated[4]_i_1_n_0 ;\n wire \\genblk8[4].right_edge_found_pb[4]_i_1_n_0 ;\n wire \\genblk8[5].left_edge_found_pb[5]_i_1_n_0 ;\n wire \\genblk8[5].left_edge_updated[5]_i_1_n_0 ;\n wire \\genblk8[5].right_edge_found_pb[5]_i_1_n_0 ;\n wire \\genblk8[6].left_edge_found_pb[6]_i_1_n_0 ;\n wire \\genblk8[6].left_edge_updated[6]_i_1_n_0 ;\n wire \\genblk8[6].right_edge_found_pb[6]_i_1_n_0 ;\n wire \\genblk8[7].left_edge_found_pb[7]_i_1_n_0 ;\n wire \\genblk8[7].left_edge_updated[7]_i_1_n_0 ;\n wire \\genblk8[7].right_edge_found_pb[7]_i_1_n_0 ;\n wire \\genblk9[0].fine_delay_incdec_pb[0]_i_7_n_0 ;\n wire \\genblk9[1].fine_delay_incdec_pb_reg[1] ;\n wire \\genblk9[2].fine_delay_incdec_pb_reg[2] ;\n wire \\genblk9[3].fine_delay_incdec_pb_reg[3] ;\n wire \\genblk9[5].fine_delay_incdec_pb_reg[5] ;\n wire \\genblk9[6].fine_delay_incdec_pb_reg[6] ;\n wire \\genblk9[7].fine_delay_incdec_pb_reg[7] ;\n wire idel_adj_inc_i_1_n_0;\n wire idel_pat_detect_valid_r_i_1_n_0;\n wire idelay_ce;\n wire idelay_ce_int;\n wire idelay_ce_r1;\n wire idelay_inc;\n wire idelay_inc_int;\n wire idelay_inc_r1;\n wire idelay_ld;\n wire idelay_ld_done_i_1_n_0;\n wire idelay_ld_i_1_n_0;\n wire idelay_ld_rst;\n wire idelay_ld_rst_3;\n wire idelay_ld_rst_4;\n wire idelay_ld_rst_5;\n wire [1:0]\\idelay_tap_cnt_r_reg[0][3][0] ;\n wire ififo_rst_reg;\n wire ififo_rst_reg_0;\n wire ififo_rst_reg_1;\n wire ififo_rst_reg_2;\n wire [3:0]in0;\n wire inhibit_edge_detect_r;\n wire inhibit_edge_detect_r_i_1_n_0;\n wire init_calib_complete_r_reg;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire init_calib_complete_reg_rep__0_n_0;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire init_calib_complete_reg_rep__10_n_0;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire init_calib_complete_reg_rep__11_n_0;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire init_calib_complete_reg_rep__12_n_0;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire init_calib_complete_reg_rep__13_n_0;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire init_calib_complete_reg_rep__1_n_0;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire init_calib_complete_reg_rep__2_n_0;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire init_calib_complete_reg_rep__3_n_0;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire init_calib_complete_reg_rep__4_n_0;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire init_calib_complete_reg_rep__8_n_0;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire init_calib_complete_reg_rep__9_n_0;\n wire init_complete_r_i_1_n_0;\n wire init_complete_r_timing_i_1_n_0;\n wire init_complete_r_timing_orig;\n wire init_dec_done_i_1_n_0;\n wire init_dqsfound_done_r2;\n wire init_dqsfound_done_r5;\n wire init_dqsfound_done_r_i_1_n_0;\n wire [6:6]init_state_r;\n wire [7:0]left_edge_updated;\n wire lim2init_prech_req;\n wire maint_prescaler_r1;\n wire \\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_11 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_12 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_13 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_17 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_0 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_10 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_12 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_24 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_25 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_26 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_27 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_28 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_29 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_30 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_31 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_36 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_37 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_38 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_40 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_41 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_42 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_46 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_47 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_48 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_49 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_50 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_54 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_55 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_56 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_58 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_7 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_8 ;\n wire \\mcGo_r_reg[15] ;\n wire [35:0]mc_address;\n wire [8:0]mc_bank;\n wire [2:0]mc_cas_n;\n wire [0:0]mc_cke;\n wire [1:0]mc_cmd;\n wire [0:0]mc_cs_n;\n wire [0:0]mc_odt;\n wire [2:0]mc_ras_n;\n wire [2:0]mc_we_n;\n wire mc_wrdata_en;\n wire mem_init_done_r;\n wire [5:0]mem_out;\n wire \\mmcm_current_reg[0] ;\n wire \\mmcm_init_trail_reg[0] ;\n wire mpr_dec_cpt_r_i_1_n_0;\n wire mpr_end_if_reset;\n wire mpr_last_byte_done;\n wire mpr_last_byte_done_i_1_n_0;\n wire mpr_rank_done_r_i_1_n_0;\n wire mpr_rdlvl_done_r_i_1_n_0;\n wire mpr_rdlvl_start_r;\n wire mpr_rnk_done;\n wire mux_cmd_wren;\n wire mux_reset_n;\n wire mux_wrdata_en;\n wire [0:0]my_empty;\n wire [0:0]my_empty_6;\n wire [0:0]my_empty_7;\n wire [0:0]my_empty_8;\n wire \\my_empty_reg[1] ;\n wire \\my_empty_reg[1]_0 ;\n wire \\my_empty_reg[1]_1 ;\n wire \\my_empty_reg[1]_2 ;\n wire \\my_empty_reg[1]_3 ;\n wire \\my_empty_reg[1]_4 ;\n wire \\my_empty_reg[1]_5 ;\n wire \\my_empty_reg[1]_6 ;\n wire \\my_empty_reg[7] ;\n wire [71:0]\\my_empty_reg[7]_0 ;\n wire [71:0]\\my_empty_reg[7]_1 ;\n wire [3:0]\\my_empty_reg[7]_10 ;\n wire [7:0]\\my_empty_reg[7]_11 ;\n wire [7:0]\\my_empty_reg[7]_12 ;\n wire [7:0]\\my_empty_reg[7]_13 ;\n wire [7:0]\\my_empty_reg[7]_14 ;\n wire [7:0]\\my_empty_reg[7]_15 ;\n wire [7:0]\\my_empty_reg[7]_16 ;\n wire [7:0]\\my_empty_reg[7]_17 ;\n wire [7:0]\\my_empty_reg[7]_18 ;\n wire [7:0]\\my_empty_reg[7]_19 ;\n wire [71:0]\\my_empty_reg[7]_2 ;\n wire [7:0]\\my_empty_reg[7]_20 ;\n wire [7:0]\\my_empty_reg[7]_21 ;\n wire [7:0]\\my_empty_reg[7]_22 ;\n wire [7:0]\\my_empty_reg[7]_23 ;\n wire [7:0]\\my_empty_reg[7]_24 ;\n wire [7:0]\\my_empty_reg[7]_25 ;\n wire [7:0]\\my_empty_reg[7]_26 ;\n wire [7:0]\\my_empty_reg[7]_27 ;\n wire [7:0]\\my_empty_reg[7]_28 ;\n wire [7:0]\\my_empty_reg[7]_29 ;\n wire [71:0]\\my_empty_reg[7]_3 ;\n wire [7:0]\\my_empty_reg[7]_30 ;\n wire [7:0]\\my_empty_reg[7]_31 ;\n wire [7:0]\\my_empty_reg[7]_32 ;\n wire [7:0]\\my_empty_reg[7]_33 ;\n wire [7:0]\\my_empty_reg[7]_34 ;\n wire [7:0]\\my_empty_reg[7]_35 ;\n wire [7:0]\\my_empty_reg[7]_36 ;\n wire [7:0]\\my_empty_reg[7]_37 ;\n wire [7:0]\\my_empty_reg[7]_38 ;\n wire [7:0]\\my_empty_reg[7]_39 ;\n wire [3:0]\\my_empty_reg[7]_4 ;\n wire [7:0]\\my_empty_reg[7]_40 ;\n wire [7:0]\\my_empty_reg[7]_41 ;\n wire [7:0]\\my_empty_reg[7]_42 ;\n wire [3:0]\\my_empty_reg[7]_5 ;\n wire [3:0]\\my_empty_reg[7]_6 ;\n wire [3:0]\\my_empty_reg[7]_7 ;\n wire [3:0]\\my_empty_reg[7]_8 ;\n wire [3:0]\\my_empty_reg[7]_9 ;\n wire [3:0]\\my_full_reg[3] ;\n wire [1:0]\\my_full_reg[3]_0 ;\n wire new_cnt_dqs_r;\n wire new_cnt_dqs_r_i_1_n_0;\n wire no_err_win_detected_latch_i_1_n_0;\n wire num_samples_done_ind_i_1_n_0;\n wire num_samples_done_r;\n wire ocal_last_byte_done;\n wire ocd_prech_req;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_0 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_1 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_13 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_15 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_2 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_28 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_29 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_3 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_30 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_31 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_4 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_47 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_48 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_49 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_50 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_51 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_52 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_53 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_54 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_55 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_56 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_57 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_58 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_59 ;\n wire out;\n wire p_0_in;\n wire p_0_in102_in;\n wire p_0_in10_in;\n wire p_0_in13_in;\n wire p_0_in16_in;\n wire p_0_in1_in;\n wire p_0_in23_in;\n wire p_0_in4_in;\n wire p_0_in7_in;\n wire p_0_in84_in;\n wire p_0_in87_in;\n wire p_0_in90_in;\n wire p_0_in93_in;\n wire p_0_in96_in;\n wire p_0_in99_in;\n wire [3:2]p_0_in_0;\n wire p_0_in_2;\n wire p_0_out;\n wire p_103_out;\n wire p_106_out;\n wire p_119_out;\n wire p_122_out;\n wire p_127_out;\n wire p_130_out;\n wire p_143_out;\n wire p_146_out;\n wire p_154_out;\n wire p_1_in;\n wire p_1_in27_in;\n wire p_1_in50_in;\n wire p_2_in24_in;\n wire p_3_in25_in;\n wire p_81_in;\n wire p_95_out;\n wire p_98_out;\n wire [7:0]pb_detect_edge_done_r;\n wire pb_found_stable_eye_r52_out;\n wire pb_found_stable_eye_r56_out;\n wire pb_found_stable_eye_r60_out;\n wire pb_found_stable_eye_r64_out;\n wire pb_found_stable_eye_r68_out;\n wire pb_found_stable_eye_r72_out;\n wire pb_found_stable_eye_r76_out;\n wire pd_out;\n wire \\periodic_rd_generation.periodic_rd_timer_r_reg[1] ;\n wire \\phaser_in_gen.phaser_in_i_12__0_n_0 ;\n wire \\phaser_in_gen.phaser_in_i_12__1_n_0 ;\n wire \\phaser_in_gen.phaser_in_i_12__2_n_0 ;\n wire \\phaser_in_gen.phaser_in_i_12_n_0 ;\n wire [10:0]\\phy_ctl_wd_i1_reg[24] ;\n wire [33:0]phy_dout;\n wire phy_if_reset;\n wire phy_if_reset0__0;\n wire phy_if_reset_w;\n wire phy_rddata_en;\n wire phy_rddata_en_1;\n wire phy_read_calib;\n wire phy_write_calib;\n wire pi_calib_done;\n wire pi_cnt_dec_i_1_n_0;\n wire [0:0]pi_cnt_dec_reg;\n wire [5:0]\\pi_counter_read_val_reg[5] ;\n wire [1:1]pi_dqs_found_all_bank;\n wire [1:0]pi_dqs_found_all_bank_r;\n wire [0:0]pi_dqs_found_any_bank;\n wire \\pi_dqs_found_any_bank[0]_i_1_n_0 ;\n wire pi_dqs_found_done_r1;\n wire \\pi_dqs_found_lanes_r1_reg[0] ;\n wire \\pi_dqs_found_lanes_r1_reg[0]_0 ;\n wire \\pi_dqs_found_lanes_r1_reg[0]_1 ;\n wire \\pi_dqs_found_lanes_r1_reg[0]_2 ;\n wire \\pi_dqs_found_lanes_r1_reg[1] ;\n wire \\pi_dqs_found_lanes_r1_reg[1]_0 ;\n wire \\pi_dqs_found_lanes_r1_reg[1]_1 ;\n wire \\pi_dqs_found_lanes_r1_reg[1]_2 ;\n wire [5:0]\\pi_dqs_found_lanes_r1_reg[1]_3 ;\n wire \\pi_dqs_found_lanes_r1_reg[2] ;\n wire \\pi_dqs_found_lanes_r1_reg[2]_0 ;\n wire \\pi_dqs_found_lanes_r1_reg[2]_1 ;\n wire \\pi_dqs_found_lanes_r1_reg[2]_2 ;\n wire [5:0]\\pi_dqs_found_lanes_r1_reg[2]_3 ;\n wire \\pi_dqs_found_lanes_r1_reg[3] ;\n wire \\pi_dqs_found_lanes_r1_reg[3]_0 ;\n wire \\pi_dqs_found_lanes_r1_reg[3]_1 ;\n wire \\pi_dqs_found_lanes_r1_reg[3]_2 ;\n wire [5:0]\\pi_dqs_found_lanes_r1_reg[3]_3 ;\n wire pi_dqs_found_rank_done;\n wire pi_en_stg2_f_timing_reg;\n wire pi_fine_dly_dec_done;\n wire \\pi_rst_stg1_cal_r_reg[0] ;\n wire pi_stg2_f_incdec_timing_i_1_n_0;\n wire pi_stg2_load_timing_i_1_n_0;\n wire [1:0]pi_stg2_rdlvl_cnt;\n wire po_cnt_dec_i_1__0_n_0;\n wire po_cnt_dec_i_1_n_0;\n wire [0:0]po_cnt_dec_reg;\n wire po_cnt_inc_i_1_n_0;\n wire \\po_counter_read_val_reg[2] ;\n wire [5:0]\\po_counter_read_val_reg[5] ;\n wire \\po_counter_read_val_reg[8] ;\n wire \\po_counter_read_val_reg[8]_0 ;\n wire \\po_counter_read_val_reg[8]_1 ;\n wire \\po_counter_read_val_reg[8]_10 ;\n wire \\po_counter_read_val_reg[8]_11 ;\n wire \\po_counter_read_val_reg[8]_12 ;\n wire \\po_counter_read_val_reg[8]_13 ;\n wire \\po_counter_read_val_reg[8]_14 ;\n wire \\po_counter_read_val_reg[8]_15 ;\n wire \\po_counter_read_val_reg[8]_16 ;\n wire \\po_counter_read_val_reg[8]_17 ;\n wire \\po_counter_read_val_reg[8]_18 ;\n wire \\po_counter_read_val_reg[8]_19 ;\n wire \\po_counter_read_val_reg[8]_2 ;\n wire \\po_counter_read_val_reg[8]_20 ;\n wire \\po_counter_read_val_reg[8]_21 ;\n wire \\po_counter_read_val_reg[8]_22 ;\n wire \\po_counter_read_val_reg[8]_23 ;\n wire \\po_counter_read_val_reg[8]_24 ;\n wire \\po_counter_read_val_reg[8]_25 ;\n wire \\po_counter_read_val_reg[8]_26 ;\n wire \\po_counter_read_val_reg[8]_27 ;\n wire \\po_counter_read_val_reg[8]_28 ;\n wire \\po_counter_read_val_reg[8]_29 ;\n wire \\po_counter_read_val_reg[8]_3 ;\n wire [4:0]\\po_counter_read_val_reg[8]_30 ;\n wire [4:0]\\po_counter_read_val_reg[8]_31 ;\n wire \\po_counter_read_val_reg[8]_4 ;\n wire \\po_counter_read_val_reg[8]_5 ;\n wire \\po_counter_read_val_reg[8]_6 ;\n wire \\po_counter_read_val_reg[8]_7 ;\n wire \\po_counter_read_val_reg[8]_8 ;\n wire \\po_counter_read_val_reg[8]_9 ;\n wire po_en_stg23;\n wire [0:0]po_enstg2_f;\n wire [2:0]\\po_rdval_cnt_reg[8] ;\n wire po_stg23_incdec;\n wire [0:0]po_stg2_fincdec;\n wire [2:2]po_stg2_wrcal_cnt;\n wire \\po_stg2_wrcal_cnt_reg[1] ;\n wire \\po_stg2_wrcal_cnt_reg[1]_0 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_1 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_10 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_11 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_12 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_13 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_14 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_15 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_16 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_17 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_18 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_19 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_2 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_20 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_21 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_22 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_23 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_24 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_25 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_26 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_27 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_28 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_29 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_3 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_30 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_31 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_32 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_33 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_34 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_35 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_36 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_37 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_38 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_39 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_4 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_40 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_41 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_42 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_43 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_44 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_45 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_46 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_47 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_48 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_49 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_5 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_50 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_51 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_52 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_53 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_54 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_55 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_56 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_57 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_58 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_59 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_6 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_60 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_61 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_7 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_8 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_9 ;\n wire poc_sample_pd;\n wire \\prbs_dqs_cnt_r[0]_i_1_n_0 ;\n wire \\prbs_dqs_cnt_r[1]_i_1_n_0 ;\n wire \\prbs_dqs_cnt_r[2]_i_1_n_0 ;\n wire prbs_dqs_tap_limit_r_i_1_n_0;\n wire prbs_found_1st_edge_r_i_1_n_0;\n wire prbs_last_byte_done;\n wire prbs_last_byte_done_i_1_n_0;\n wire prbs_last_byte_done_r;\n wire prbs_pi_stg2_f_en;\n wire prbs_pi_stg2_f_incdec;\n wire prbs_prech_req_r;\n wire prbs_prech_req_r_i_1_n_0;\n wire prbs_rdlvl_done_i_1_n_0;\n wire prbs_rdlvl_done_pulse0;\n wire prbs_rdlvl_done_r1;\n wire prbs_rdlvl_start_r;\n wire prbs_rdlvl_start_r_reg;\n wire [4:0]prbs_state_r;\n wire prbs_state_r178_out;\n wire prbs_tap_en_r;\n wire prbs_tap_en_r_i_1_n_0;\n wire prbs_tap_inc_r;\n wire prbs_tap_inc_r_i_1_n_0;\n wire prech_done;\n wire prech_pending_r;\n wire prech_pending_r_i_1_n_0;\n wire prech_req;\n wire psdone;\n wire [0:0]\\qcntr_r_reg[0] ;\n wire rank_done_r_i_1_n_0;\n wire rd_active_r1;\n wire rd_active_r2;\n wire \\rd_addr[7]_i_1_n_0 ;\n wire \\rd_byte_data_offset_reg[0]_3 ;\n wire rd_data_offset_cal_done;\n wire [3:2]rd_data_offset_ranks_0;\n wire [3:2]rd_data_offset_ranks_1;\n wire \\rd_mux_sel_r_reg[1] ;\n wire \\rd_mux_sel_r_reg[1]_0 ;\n wire \\rd_mux_sel_r_reg[1]_1 ;\n wire \\rd_mux_sel_r_reg[1]_10 ;\n wire \\rd_mux_sel_r_reg[1]_11 ;\n wire \\rd_mux_sel_r_reg[1]_12 ;\n wire \\rd_mux_sel_r_reg[1]_13 ;\n wire \\rd_mux_sel_r_reg[1]_14 ;\n wire \\rd_mux_sel_r_reg[1]_15 ;\n wire \\rd_mux_sel_r_reg[1]_16 ;\n wire \\rd_mux_sel_r_reg[1]_17 ;\n wire \\rd_mux_sel_r_reg[1]_18 ;\n wire \\rd_mux_sel_r_reg[1]_19 ;\n wire \\rd_mux_sel_r_reg[1]_2 ;\n wire \\rd_mux_sel_r_reg[1]_20 ;\n wire \\rd_mux_sel_r_reg[1]_21 ;\n wire \\rd_mux_sel_r_reg[1]_22 ;\n wire \\rd_mux_sel_r_reg[1]_23 ;\n wire \\rd_mux_sel_r_reg[1]_24 ;\n wire \\rd_mux_sel_r_reg[1]_25 ;\n wire \\rd_mux_sel_r_reg[1]_26 ;\n wire \\rd_mux_sel_r_reg[1]_27 ;\n wire \\rd_mux_sel_r_reg[1]_28 ;\n wire \\rd_mux_sel_r_reg[1]_29 ;\n wire \\rd_mux_sel_r_reg[1]_3 ;\n wire \\rd_mux_sel_r_reg[1]_30 ;\n wire \\rd_mux_sel_r_reg[1]_31 ;\n wire \\rd_mux_sel_r_reg[1]_32 ;\n wire \\rd_mux_sel_r_reg[1]_33 ;\n wire \\rd_mux_sel_r_reg[1]_34 ;\n wire \\rd_mux_sel_r_reg[1]_35 ;\n wire \\rd_mux_sel_r_reg[1]_36 ;\n wire \\rd_mux_sel_r_reg[1]_37 ;\n wire \\rd_mux_sel_r_reg[1]_38 ;\n wire \\rd_mux_sel_r_reg[1]_39 ;\n wire \\rd_mux_sel_r_reg[1]_4 ;\n wire \\rd_mux_sel_r_reg[1]_40 ;\n wire \\rd_mux_sel_r_reg[1]_41 ;\n wire \\rd_mux_sel_r_reg[1]_42 ;\n wire \\rd_mux_sel_r_reg[1]_43 ;\n wire \\rd_mux_sel_r_reg[1]_44 ;\n wire \\rd_mux_sel_r_reg[1]_45 ;\n wire \\rd_mux_sel_r_reg[1]_46 ;\n wire \\rd_mux_sel_r_reg[1]_47 ;\n wire \\rd_mux_sel_r_reg[1]_48 ;\n wire \\rd_mux_sel_r_reg[1]_49 ;\n wire \\rd_mux_sel_r_reg[1]_5 ;\n wire \\rd_mux_sel_r_reg[1]_50 ;\n wire \\rd_mux_sel_r_reg[1]_51 ;\n wire \\rd_mux_sel_r_reg[1]_52 ;\n wire \\rd_mux_sel_r_reg[1]_53 ;\n wire \\rd_mux_sel_r_reg[1]_54 ;\n wire \\rd_mux_sel_r_reg[1]_55 ;\n wire \\rd_mux_sel_r_reg[1]_56 ;\n wire \\rd_mux_sel_r_reg[1]_57 ;\n wire \\rd_mux_sel_r_reg[1]_58 ;\n wire \\rd_mux_sel_r_reg[1]_59 ;\n wire \\rd_mux_sel_r_reg[1]_6 ;\n wire \\rd_mux_sel_r_reg[1]_60 ;\n wire \\rd_mux_sel_r_reg[1]_61 ;\n wire \\rd_mux_sel_r_reg[1]_62 ;\n wire \\rd_mux_sel_r_reg[1]_7 ;\n wire \\rd_mux_sel_r_reg[1]_8 ;\n wire \\rd_mux_sel_r_reg[1]_9 ;\n wire [37:0]\\rd_ptr_reg[3] ;\n wire [11:0]\\rd_ptr_reg[3]_0 ;\n wire [31:0]\\rd_ptr_reg[3]_1 ;\n wire [63:0]\\rd_ptr_reg[3]_2 ;\n wire [63:0]\\rd_ptr_reg[3]_3 ;\n wire [63:0]\\rd_ptr_reg[3]_4 ;\n wire [63:0]\\rd_ptr_reg[3]_5 ;\n wire \\rd_ptr_timing_reg[0] ;\n wire [33:0]\\rd_ptr_timing_reg[0]_0 ;\n wire [7:0]\\rd_ptr_timing_reg[0]_1 ;\n wire [7:0]\\rd_ptr_timing_reg[0]_2 ;\n wire [3:0]\\rd_ptr_timing_reg[0]_3 ;\n wire [1:0]\\rd_ptr_timing_reg[0]_4 ;\n wire [1:0]\\rdlvl_dqs_tap_cnt_r_reg[0][3][0] ;\n wire rdlvl_last_byte_done;\n wire rdlvl_last_byte_done_int_i_1_n_0;\n wire rdlvl_pi_incdec;\n wire rdlvl_pi_incdec_i_1_n_0;\n wire rdlvl_prech_req;\n wire rdlvl_rank_done_r_i_1_n_0;\n wire [14:14]rdlvl_start_dly0_r;\n wire rdlvl_start_pre;\n wire rdlvl_start_pre_i_1_n_0;\n wire rdlvl_stg1_done_int;\n wire rdlvl_stg1_done_int_i_1_n_0;\n wire rdlvl_stg1_rank_done;\n wire rdlvl_stg1_start_i_1_n_0;\n wire rdlvl_stg1_start_int;\n wire [2:2]regl_dqs_cnt;\n wire reset_if;\n wire reset_if_r8_reg_srl8_n_0;\n wire reset_if_r9;\n wire reset_rd_addr;\n wire reset_rd_addr0;\n wire reset_rd_addr_i_1_n_0;\n wire right_edge_found;\n wire right_edge_found_i_1_n_0;\n wire right_gain_pb;\n wire \\row_cnt_victim_rotate.complex_row_cnt_reg[4] ;\n wire rst_dqs_find;\n wire rst_dqs_find_i_1_n_0;\n wire rstdiv0_sync_r1_reg_rep;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__10;\n wire rstdiv0_sync_r1_reg_rep__11;\n wire [0:0]rstdiv0_sync_r1_reg_rep__12;\n wire rstdiv0_sync_r1_reg_rep__13;\n wire [1:0]rstdiv0_sync_r1_reg_rep__14;\n wire [0:0]rstdiv0_sync_r1_reg_rep__16;\n wire [1:0]rstdiv0_sync_r1_reg_rep__17;\n wire [0:0]rstdiv0_sync_r1_reg_rep__19;\n wire rstdiv0_sync_r1_reg_rep__2;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__22;\n wire rstdiv0_sync_r1_reg_rep__23;\n wire rstdiv0_sync_r1_reg_rep__23_0;\n wire rstdiv0_sync_r1_reg_rep__23_1;\n wire rstdiv0_sync_r1_reg_rep__24;\n wire rstdiv0_sync_r1_reg_rep__25;\n wire rstdiv0_sync_r1_reg_rep__25_0;\n wire rstdiv0_sync_r1_reg_rep__25_1;\n wire rstdiv0_sync_r1_reg_rep__25_2;\n wire [0:0]rstdiv0_sync_r1_reg_rep__4;\n wire rstdiv0_sync_r1_reg_rep__5;\n wire rstdiv0_sync_r1_reg_rep__6;\n wire [0:0]rstdiv0_sync_r1_reg_rep__7;\n wire rstdiv0_sync_r1_reg_rep__8;\n wire rstdiv0_sync_r1_reg_rep__9;\n wire samp_edge_cnt0_en_r;\n wire samp_edge_cnt0_en_r_reg;\n wire samples_cnt_r;\n wire \\samps_r_reg[9] ;\n wire sel;\n wire \\sm_r_reg[0] ;\n wire [0:0]\\sm_r_reg[0]_0 ;\n wire sr_valid_r108_out;\n wire stable_cnt1;\n wire stable_cnt227_in;\n wire stg1_wr_done;\n wire \\stg2_tap_cnt_reg[0] ;\n wire stg3_dec2init_val_r_reg;\n wire stg3_inc2init_val_r_reg;\n wire \\stg3_r_reg[0] ;\n wire store_sr_r_i_1_n_0;\n wire temp_lmr_done;\n wire tempmon_pi_f_en_r;\n wire tempmon_pi_f_inc;\n wire tempmon_pi_f_inc_r;\n wire tempmon_sample_en;\n wire tempmon_sel_pi_incdec;\n wire u_ddr_phy_init_n_101;\n wire u_ddr_phy_init_n_102;\n wire u_ddr_phy_init_n_104;\n wire u_ddr_phy_init_n_105;\n wire u_ddr_phy_init_n_106;\n wire u_ddr_phy_init_n_107;\n wire u_ddr_phy_init_n_108;\n wire u_ddr_phy_init_n_109;\n wire u_ddr_phy_init_n_110;\n wire u_ddr_phy_init_n_111;\n wire u_ddr_phy_init_n_114;\n wire u_ddr_phy_init_n_115;\n wire u_ddr_phy_init_n_116;\n wire u_ddr_phy_init_n_117;\n wire u_ddr_phy_init_n_120;\n wire u_ddr_phy_init_n_121;\n wire u_ddr_phy_init_n_122;\n wire u_ddr_phy_init_n_123;\n wire u_ddr_phy_init_n_124;\n wire u_ddr_phy_init_n_125;\n wire u_ddr_phy_init_n_126;\n wire u_ddr_phy_init_n_127;\n wire u_ddr_phy_init_n_18;\n wire u_ddr_phy_init_n_24;\n wire u_ddr_phy_init_n_29;\n wire u_ddr_phy_init_n_31;\n wire u_ddr_phy_init_n_33;\n wire u_ddr_phy_init_n_462;\n wire u_ddr_phy_init_n_464;\n wire u_ddr_phy_init_n_465;\n wire u_ddr_phy_init_n_468;\n wire u_ddr_phy_init_n_469;\n wire u_ddr_phy_init_n_470;\n wire u_ddr_phy_init_n_473;\n wire u_ddr_phy_init_n_474;\n wire u_ddr_phy_init_n_475;\n wire u_ddr_phy_init_n_476;\n wire u_ddr_phy_init_n_477;\n wire u_ddr_phy_init_n_478;\n wire u_ddr_phy_init_n_479;\n wire u_ddr_phy_init_n_480;\n wire u_ddr_phy_init_n_485;\n wire u_ddr_phy_init_n_490;\n wire u_ddr_phy_init_n_496;\n wire u_ddr_phy_init_n_497;\n wire u_ddr_phy_init_n_499;\n wire u_ddr_phy_init_n_500;\n wire u_ddr_phy_init_n_501;\n wire u_ddr_phy_init_n_502;\n wire u_ddr_phy_init_n_784;\n wire u_ddr_phy_init_n_785;\n wire u_ddr_phy_init_n_786;\n wire u_ddr_phy_init_n_790;\n wire u_ddr_phy_init_n_791;\n wire u_ddr_phy_init_n_9;\n wire u_ddr_phy_wrcal_n_100;\n wire u_ddr_phy_wrcal_n_101;\n wire u_ddr_phy_wrcal_n_102;\n wire u_ddr_phy_wrcal_n_103;\n wire u_ddr_phy_wrcal_n_104;\n wire u_ddr_phy_wrcal_n_105;\n wire u_ddr_phy_wrcal_n_106;\n wire u_ddr_phy_wrcal_n_107;\n wire u_ddr_phy_wrcal_n_108;\n wire u_ddr_phy_wrcal_n_109;\n wire u_ddr_phy_wrcal_n_110;\n wire u_ddr_phy_wrcal_n_111;\n wire u_ddr_phy_wrcal_n_112;\n wire u_ddr_phy_wrcal_n_113;\n wire u_ddr_phy_wrcal_n_114;\n wire u_ddr_phy_wrcal_n_115;\n wire u_ddr_phy_wrcal_n_116;\n wire u_ddr_phy_wrcal_n_117;\n wire u_ddr_phy_wrcal_n_118;\n wire u_ddr_phy_wrcal_n_119;\n wire u_ddr_phy_wrcal_n_120;\n wire u_ddr_phy_wrcal_n_4;\n wire u_ddr_phy_wrcal_n_5;\n wire u_ddr_phy_wrcal_n_66;\n wire u_ddr_phy_wrcal_n_67;\n wire u_ddr_phy_wrcal_n_69;\n wire u_ddr_phy_wrcal_n_71;\n wire u_ddr_phy_wrcal_n_73;\n wire u_ddr_phy_wrcal_n_74;\n wire u_ddr_phy_wrcal_n_81;\n wire u_ddr_phy_wrcal_n_82;\n wire u_ddr_phy_wrcal_n_83;\n wire u_ddr_phy_wrcal_n_84;\n wire u_ddr_phy_wrcal_n_85;\n wire u_ddr_phy_wrcal_n_89;\n wire u_ddr_phy_wrcal_n_90;\n wire u_ddr_phy_wrcal_n_91;\n wire u_ddr_phy_wrcal_n_92;\n wire u_ddr_phy_wrcal_n_93;\n wire u_ddr_phy_wrcal_n_94;\n wire u_ddr_phy_wrcal_n_95;\n wire u_ddr_phy_wrcal_n_96;\n wire u_ddr_phy_wrcal_n_97;\n wire u_ddr_phy_wrcal_n_98;\n wire u_ddr_prbs_gen_n_0;\n wire u_ddr_prbs_gen_n_1;\n wire u_ddr_prbs_gen_n_10;\n wire u_ddr_prbs_gen_n_100;\n wire u_ddr_prbs_gen_n_101;\n wire u_ddr_prbs_gen_n_102;\n wire u_ddr_prbs_gen_n_103;\n wire u_ddr_prbs_gen_n_104;\n wire u_ddr_prbs_gen_n_105;\n wire u_ddr_prbs_gen_n_106;\n wire u_ddr_prbs_gen_n_107;\n wire u_ddr_prbs_gen_n_108;\n wire u_ddr_prbs_gen_n_109;\n wire u_ddr_prbs_gen_n_11;\n wire u_ddr_prbs_gen_n_110;\n wire u_ddr_prbs_gen_n_111;\n wire u_ddr_prbs_gen_n_112;\n wire u_ddr_prbs_gen_n_113;\n wire u_ddr_prbs_gen_n_114;\n wire u_ddr_prbs_gen_n_115;\n wire u_ddr_prbs_gen_n_116;\n wire u_ddr_prbs_gen_n_117;\n wire u_ddr_prbs_gen_n_118;\n wire u_ddr_prbs_gen_n_119;\n wire u_ddr_prbs_gen_n_12;\n wire u_ddr_prbs_gen_n_120;\n wire u_ddr_prbs_gen_n_121;\n wire u_ddr_prbs_gen_n_13;\n wire u_ddr_prbs_gen_n_14;\n wire u_ddr_prbs_gen_n_15;\n wire u_ddr_prbs_gen_n_16;\n wire u_ddr_prbs_gen_n_17;\n wire u_ddr_prbs_gen_n_18;\n wire u_ddr_prbs_gen_n_19;\n wire u_ddr_prbs_gen_n_2;\n wire u_ddr_prbs_gen_n_20;\n wire u_ddr_prbs_gen_n_21;\n wire u_ddr_prbs_gen_n_22;\n wire u_ddr_prbs_gen_n_23;\n wire u_ddr_prbs_gen_n_24;\n wire u_ddr_prbs_gen_n_25;\n wire u_ddr_prbs_gen_n_26;\n wire u_ddr_prbs_gen_n_27;\n wire u_ddr_prbs_gen_n_28;\n wire u_ddr_prbs_gen_n_29;\n wire u_ddr_prbs_gen_n_3;\n wire u_ddr_prbs_gen_n_30;\n wire u_ddr_prbs_gen_n_31;\n wire u_ddr_prbs_gen_n_32;\n wire u_ddr_prbs_gen_n_33;\n wire u_ddr_prbs_gen_n_34;\n wire u_ddr_prbs_gen_n_35;\n wire u_ddr_prbs_gen_n_36;\n wire u_ddr_prbs_gen_n_37;\n wire u_ddr_prbs_gen_n_38;\n wire u_ddr_prbs_gen_n_39;\n wire u_ddr_prbs_gen_n_4;\n wire u_ddr_prbs_gen_n_40;\n wire u_ddr_prbs_gen_n_41;\n wire u_ddr_prbs_gen_n_42;\n wire u_ddr_prbs_gen_n_43;\n wire u_ddr_prbs_gen_n_44;\n wire u_ddr_prbs_gen_n_45;\n wire u_ddr_prbs_gen_n_46;\n wire u_ddr_prbs_gen_n_47;\n wire u_ddr_prbs_gen_n_48;\n wire u_ddr_prbs_gen_n_49;\n wire u_ddr_prbs_gen_n_5;\n wire u_ddr_prbs_gen_n_50;\n wire u_ddr_prbs_gen_n_51;\n wire u_ddr_prbs_gen_n_52;\n wire u_ddr_prbs_gen_n_53;\n wire u_ddr_prbs_gen_n_54;\n wire u_ddr_prbs_gen_n_55;\n wire u_ddr_prbs_gen_n_56;\n wire u_ddr_prbs_gen_n_57;\n wire u_ddr_prbs_gen_n_58;\n wire u_ddr_prbs_gen_n_59;\n wire u_ddr_prbs_gen_n_6;\n wire u_ddr_prbs_gen_n_60;\n wire u_ddr_prbs_gen_n_61;\n wire u_ddr_prbs_gen_n_62;\n wire u_ddr_prbs_gen_n_63;\n wire u_ddr_prbs_gen_n_64;\n wire u_ddr_prbs_gen_n_65;\n wire u_ddr_prbs_gen_n_66;\n wire u_ddr_prbs_gen_n_67;\n wire u_ddr_prbs_gen_n_68;\n wire u_ddr_prbs_gen_n_69;\n wire u_ddr_prbs_gen_n_7;\n wire u_ddr_prbs_gen_n_70;\n wire u_ddr_prbs_gen_n_71;\n wire u_ddr_prbs_gen_n_72;\n wire u_ddr_prbs_gen_n_73;\n wire u_ddr_prbs_gen_n_74;\n wire u_ddr_prbs_gen_n_75;\n wire u_ddr_prbs_gen_n_76;\n wire u_ddr_prbs_gen_n_77;\n wire u_ddr_prbs_gen_n_78;\n wire u_ddr_prbs_gen_n_79;\n wire u_ddr_prbs_gen_n_8;\n wire u_ddr_prbs_gen_n_80;\n wire u_ddr_prbs_gen_n_81;\n wire u_ddr_prbs_gen_n_82;\n wire u_ddr_prbs_gen_n_83;\n wire u_ddr_prbs_gen_n_84;\n wire u_ddr_prbs_gen_n_85;\n wire u_ddr_prbs_gen_n_86;\n wire u_ddr_prbs_gen_n_87;\n wire u_ddr_prbs_gen_n_88;\n wire u_ddr_prbs_gen_n_89;\n wire u_ddr_prbs_gen_n_9;\n wire u_ddr_prbs_gen_n_90;\n wire u_ddr_prbs_gen_n_91;\n wire u_ddr_prbs_gen_n_92;\n wire u_ddr_prbs_gen_n_93;\n wire u_ddr_prbs_gen_n_94;\n wire u_ddr_prbs_gen_n_95;\n wire u_ddr_prbs_gen_n_96;\n wire u_ddr_prbs_gen_n_97;\n wire u_ddr_prbs_gen_n_98;\n wire u_ddr_prbs_gen_n_99;\n wire [2:0]\\u_ocd_lim/stg2_tap_cnt_reg ;\n wire [2:0]\\u_ocd_lim/stg3_dec_val00_out ;\n wire [2:0]\\u_ocd_lim/stg3_init_val ;\n wire [8:2]\\u_ocd_po_cntlr/stg2_target_ns ;\n wire [1:0]wait_cnt_r_reg__0;\n wire [0:0]wait_cnt_r_reg__0_1;\n wire wl_edge_detect_valid_r_i_1_n_0;\n wire [0:0]wl_po_fine_cnt_sel_0;\n wire [2:1]wl_po_fine_cnt_sel_0__0;\n wire wl_sm_start;\n wire wr_level_done_i_1_n_0;\n wire wr_level_done_r_i_1_n_0;\n wire wrcal_pat_resume_r;\n wire wrcal_pat_resume_r_i_1_n_0;\n wire wrcal_prech_req;\n wire wrcal_rd_wait;\n wire wrcal_resume_r;\n wire wrcal_resume_w;\n wire wrcal_sanity_chk;\n wire wrcal_sanity_chk_done_i_2_n_0;\n wire wrlvl_byte_done;\n wire wrlvl_byte_redo;\n wire wrlvl_byte_redo_i_1_n_0;\n wire wrlvl_byte_redo_r;\n wire wrlvl_done_r1;\n wire wrlvl_final_if_rst;\n wire wrlvl_final_mux;\n wire wrlvl_final_r;\n wire wrlvl_rank_done;\n wire wrlvl_rank_done_r_i_1_n_0;\n wire [0:0]\\zero2fuzz_r_reg[0] ;\n\n assign A_1__s_port_ = A_1__s_net_1;\n (* SOFT_HLUTNM = \"soft_lutpair727\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\A[0]__0_i_1 \n (.I0(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]),\n .I1(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]),\n .I2(byte_sel_cnt),\n .O(\\A[0]__0 ));\n (* SOFT_HLUTNM = \"soft_lutpair726\" *) \n LUT3 #(\n .INIT(8'h20)) \n \\A[0]__4_i_1 \n (.I0(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]),\n .I1(byte_sel_cnt),\n .I2(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]),\n .O(\\A[0]__4 ));\n (* SOFT_HLUTNM = \"soft_lutpair726\" *) \n LUT3 #(\n .INIT(8'h02)) \n \\A[1]__0_i_1 \n (.I0(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]),\n .I1(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]),\n .I2(byte_sel_cnt),\n .O(\\A[1]__0 ));\n (* SOFT_HLUTNM = \"soft_lutpair730\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\A[1]__3_i_1 \n (.I0(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]),\n .I1(byte_sel_cnt),\n .O(\\A[1]__3 ));\n (* SOFT_HLUTNM = \"soft_lutpair725\" *) \n LUT3 #(\n .INIT(8'h02)) \n \\A[1]__4_i_1 \n (.I0(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]),\n .I1(byte_sel_cnt),\n .I2(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]),\n .O(\\A[1]__4_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair729\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\A[1]_i_1 \n (.I0(byte_sel_cnt),\n .I1(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]),\n .O(\\A[1]__4 ));\n (* SOFT_HLUTNM = \"soft_lutpair729\" *) \n LUT2 #(\n .INIT(4'h4)) \n \\A[1]_i_2 \n (.I0(byte_sel_cnt),\n .I1(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]),\n .O(A_1__s_net_1));\n (* SOFT_HLUTNM = \"soft_lutpair730\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\A[2]__1_i_1 \n (.I0(byte_sel_cnt),\n .O(\\A[2]__1 ));\n (* SOFT_HLUTNM = \"soft_lutpair727\" *) \n LUT3 #(\n .INIT(8'h07)) \n \\A[2]__2_i_1 \n (.I0(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]),\n .I1(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]),\n .I2(byte_sel_cnt),\n .O(\\A[2]__2 ));\n LUT5 #(\n .INIT(32'h000000AB)) \n burst_addr_r_i_1\n (.I0(u_ddr_phy_init_n_476),\n .I1(u_ddr_phy_init_n_31),\n .I2(u_ddr_phy_init_n_109),\n .I3(u_ddr_phy_wrcal_n_82),\n .I4(rstdiv0_sync_r1_reg_rep__23),\n .O(burst_addr_r_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair725\" *) \n LUT3 #(\n .INIT(8'h40)) \n \\byte_sel_data_map[1]_i_1 \n (.I0(byte_sel_cnt),\n .I1(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]),\n .I2(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]),\n .O(\\byte_sel_data_map_reg[1] ));\n LUT4 #(\n .INIT(16'hBFB0)) \n cal2_done_r_i_1\n (.I0(u_ddr_phy_wrcal_n_5),\n .I1(wrcal_sanity_chk),\n .I2(u_ddr_phy_wrcal_n_117),\n .I3(cal2_done_r),\n .O(cal2_done_r_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFFBABF00008A80)) \n cal2_if_reset_i_1\n (.I0(u_ddr_phy_wrcal_n_120),\n .I1(u_ddr_phy_wrcal_n_115),\n .I2(u_ddr_phy_wrcal_n_111),\n .I3(u_ddr_phy_wrcal_n_114),\n .I4(u_ddr_phy_wrcal_n_108),\n .I5(phy_if_reset_w),\n .O(cal2_if_reset_i_1_n_0));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\calib_sel_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_100 ),\n .Q(\\po_rdval_cnt_reg[8] [0]),\n .R(1'b0));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\calib_sel_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_99 ),\n .Q(\\po_rdval_cnt_reg[8] [1]),\n .R(1'b0));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\calib_sel_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(ddr_phy_tempmon_0_n_3),\n .Q(\\po_rdval_cnt_reg[8] [2]),\n .R(1'b0));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\calib_zero_inputs_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_101 ),\n .Q(calib_zero_inputs__0),\n .R(1'b0));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\calib_zero_inputs_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(ddr_phy_tempmon_0_n_4),\n .Q(calib_zero_inputs),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hDFBF0820)) \n ck_po_stg2_f_en_i_1\n (.I0(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ),\n .I1(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_43 ),\n .I2(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_44 ),\n .I3(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_46 ),\n .I4(ck_po_stg2_f_en),\n .O(ck_po_stg2_f_en_i_1_n_0));\n LUT5 #(\n .INIT(32'hD7BF0020)) \n ck_po_stg2_f_indec_i_1\n (.I0(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ),\n .I1(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_43 ),\n .I2(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_44 ),\n .I3(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_46 ),\n .I4(ck_po_stg2_f_indec),\n .O(ck_po_stg2_f_indec_i_1_n_0));\n LUT4 #(\n .INIT(16'hEAAA)) \n cnt_dllk_zqinit_done_r_i_1\n (.I0(cnt_dllk_zqinit_done_r),\n .I1(cnt_dllk_zqinit_r_reg__0[6]),\n .I2(u_ddr_phy_init_n_496),\n .I3(cnt_dllk_zqinit_r_reg__0[7]),\n .O(cnt_dllk_zqinit_done_r_i_1_n_0));\n LUT6 #(\n .INIT(64'h00000000BA8A8A8A)) \n cnt_init_af_done_r_i_1\n (.I0(cnt_init_af_done_r),\n .I1(mem_init_done_r),\n .I2(u_ddr_phy_init_n_110),\n .I3(cnt_init_af_r[1]),\n .I4(cnt_init_af_r[0]),\n .I5(u_ddr_phy_init_n_115),\n .O(cnt_init_af_done_r_i_1_n_0));\n LUT6 #(\n .INIT(64'h000000000000E222)) \n cnt_init_mr_done_r_i_1\n (.I0(cnt_init_mr_done_r),\n .I1(temp_lmr_done),\n .I2(cnt_init_mr_r[0]),\n .I3(cnt_init_mr_r[1]),\n .I4(cnt_init_mr_r1),\n .I5(u_ddr_phy_init_n_115),\n .O(cnt_init_mr_done_r_i_1_n_0));\n LUT6 #(\n .INIT(64'h00000000AAAABAAA)) \n cnt_pwron_cke_done_r_i_1\n (.I0(cnt_pwron_cke_done_r),\n .I1(u_ddr_phy_init_n_490),\n .I2(cnt_pwron_r_reg__0[7]),\n .I3(cnt_pwron_r_reg__0[1]),\n .I4(cnt_pwron_r_reg__0[0]),\n .I5(cnt_pwron_reset_done_r0),\n .O(cnt_pwron_cke_done_r_i_1_n_0));\n LUT6 #(\n .INIT(64'h00000000FFFF0040)) \n cnt_pwron_reset_done_r_i_1\n (.I0(cnt_pwron_r_reg__0[7]),\n .I1(cnt_pwron_r_reg__0[5]),\n .I2(cnt_pwron_r_reg__0[0]),\n .I3(u_ddr_phy_init_n_485),\n .I4(cnt_pwron_reset_done_r),\n .I5(cnt_pwron_reset_done_r0),\n .O(cnt_pwron_reset_done_r_i_1_n_0));\n LUT5 #(\n .INIT(32'hBAAAAAAA)) \n cnt_txpr_done_r_i_1\n (.I0(cnt_txpr_done_r),\n .I1(u_ddr_phy_init_n_500),\n .I2(cnt_txpr_r_reg__0[2]),\n .I3(cnt_txpr_r_reg__0[0]),\n .I4(cnt_txpr_r_reg__0[1]),\n .O(cnt_txpr_done_r_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFB00000020)) \n complex_init_pi_dec_done_r_i_1\n (.I0(prbs_state_r[4]),\n .I1(prbs_state_r[3]),\n .I2(prbs_state_r[0]),\n .I3(prbs_state_r[2]),\n .I4(prbs_state_r[1]),\n .I5(complex_init_pi_dec_done),\n .O(complex_init_pi_dec_done_r_i_1_n_0));\n LUT6 #(\n .INIT(64'h4474FFFF44740000)) \n complex_pi_incdec_done_i_1\n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_109 ),\n .I1(prbs_state_r[0]),\n .I2(cnt_wait_state),\n .I3(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_107 ),\n .I4(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_105 ),\n .I5(complex_pi_incdec_done),\n .O(complex_pi_incdec_done_i_1_n_0));\n LUT4 #(\n .INIT(16'h00CE)) \n ddr2_pre_flag_r_i_1\n (.I0(u_ddr_phy_init_n_29),\n .I1(temp_lmr_done),\n .I2(u_ddr_phy_init_n_479),\n .I3(u_ddr_phy_init_n_115),\n .O(ddr2_pre_flag_r_i_1_n_0));\n LUT6 #(\n .INIT(64'h00000000FFFF70F0)) \n ddr2_refresh_flag_r_i_1\n (.I0(u_ddr_phy_init_n_480),\n .I1(cnt_cmd_done_r),\n .I2(ddr2_refresh_flag_r),\n .I3(cnt_init_mr_done_r),\n .I4(cnt_init_mr_r1),\n .I5(u_ddr_phy_init_n_115),\n .O(ddr2_refresh_flag_r_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair724\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/d_out \n (.I0(app_zq_r_reg),\n .I1(\\rd_ptr_reg[3]_0 [3]),\n .I2(\\my_empty_reg[1]_1 ),\n .O(\\my_full_reg[3] [3]));\n ddr3_ifmig_7series_v4_0_ddr_phy_prbs_rdlvl \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl \n (.A(A),\n .\\A[0]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_9 ),\n .\\A[1]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_10 ),\n .\\A[1]_1 (\\A[1]_0 ),\n .\\A[1]_10 (\\A[1]_9 ),\n .\\A[1]_11 (\\A[1]_10 ),\n .\\A[1]_12 (\\A[1]_11 ),\n .\\A[1]_13 (\\A[1]_12 ),\n .\\A[1]_14 (\\A[1]_13 ),\n .\\A[1]_15 (\\A[1]_14 ),\n .\\A[1]_16 (\\A[1]_15 ),\n .\\A[1]_17 (\\A[1]_16 ),\n .\\A[1]_18 (\\A[1]_17 ),\n .\\A[1]_19 (\\A[1]_18 ),\n .\\A[1]_2 (\\A[1]_1 ),\n .\\A[1]_20 (\\A[1]_19 ),\n .\\A[1]_21 (\\A[1]_20 ),\n .\\A[1]_22 (\\A[1]_21 ),\n .\\A[1]_23 (\\A[1]_22 ),\n .\\A[1]_24 (\\A[1]_23 ),\n .\\A[1]_25 (\\A[1]_24 ),\n .\\A[1]_26 (\\A[1]_25 ),\n .\\A[1]_27 (\\A[1]_26 ),\n .\\A[1]_28 (\\A[1]_27 ),\n .\\A[1]_29 (\\A[1]_28 ),\n .\\A[1]_3 (\\A[1]_2 ),\n .\\A[1]_30 (\\A[1]_29 ),\n .\\A[1]_31 (\\A[1]_30 ),\n .\\A[1]_32 (\\A[1]_31 ),\n .\\A[1]_33 (\\A[1]_32 ),\n .\\A[1]_34 (\\A[1]_33 ),\n .\\A[1]_35 (\\A[1]_34 ),\n .\\A[1]_36 (\\A[1]_35 ),\n .\\A[1]_37 (\\A[1]_36 ),\n .\\A[1]_38 (\\A[1]_37 ),\n .\\A[1]_39 (\\A[1]_38 ),\n .\\A[1]_4 (\\A[1]_3 ),\n .\\A[1]_40 (\\A[1]_39 ),\n .\\A[1]_41 (\\A[1]_40 ),\n .\\A[1]_42 (\\A[1]_41 ),\n .\\A[1]_43 (\\A[1]_42 ),\n .\\A[1]_44 (\\A[1]_43 ),\n .\\A[1]_45 (\\A[1]_44 ),\n .\\A[1]_46 (\\A[1]_45 ),\n .\\A[1]_47 (\\A[1]_46 ),\n .\\A[1]_48 (\\A[1]_47 ),\n .\\A[1]_49 (\\A[1]_48 ),\n .\\A[1]_5 (\\A[1]_4 ),\n .\\A[1]_50 (\\A[1]_49 ),\n .\\A[1]_51 (\\A[1]_50 ),\n .\\A[1]_52 (\\A[1]_51 ),\n .\\A[1]_53 (\\A[1]_52 ),\n .\\A[1]_54 (\\A[1]_53 ),\n .\\A[1]_55 (\\A[1]_54 ),\n .\\A[1]_56 (\\A[1]_55 ),\n .\\A[1]_57 (\\A[1]_56 ),\n .\\A[1]_58 (\\A[1]_57 ),\n .\\A[1]_59 (\\A[1]_58 ),\n .\\A[1]_6 (\\A[1]_5 ),\n .\\A[1]_60 (\\A[1]_59 ),\n .\\A[1]_61 (\\A[1]_60 ),\n .\\A[1]_62 (\\A[1]_61 ),\n .\\A[1]_63 (\\A[1]_62 ),\n .\\A[1]_64 (\\A[1]_63 ),\n .\\A[1]_7 (\\A[1]_6 ),\n .\\A[1]_8 (\\A[1]_7 ),\n .\\A[1]_9 (\\A[1]_8 ),\n .\\A[2]__2 (\\A[2]__2_0 ),\n .CLK(CLK),\n .D(left_edge_updated),\n .E(samples_cnt_r),\n .Q(prbs_state_r),\n .SR(SR),\n .bit_cnt(bit_cnt),\n .\\calib_sel_reg[3] (\\po_rdval_cnt_reg[8] [2]),\n .\\calib_sel_reg[3]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_94 ),\n .\\calib_sel_reg[3]_1 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_95 ),\n .\\calib_sel_reg[3]_2 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_93 ),\n .cnt_wait_state(cnt_wait_state),\n .compare_err_latch_reg_0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_109 ),\n .complex_act_start(complex_act_start),\n .complex_init_pi_dec_done(complex_init_pi_dec_done),\n .complex_ocal_reset_rd_addr(complex_ocal_reset_rd_addr),\n .complex_oclkdelay_calib_done_r1_reg(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_51 ),\n .complex_pi_incdec_done(complex_pi_incdec_done),\n .complex_pi_incdec_done_reg_0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_105 ),\n .complex_pi_incdec_done_reg_1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_107 ),\n .\\dec_cnt_reg[0]_0 (fine_dly_error_i_1_n_0),\n .\\dout_o_reg[0] (u_ddr_prbs_gen_n_114),\n .\\dout_o_reg[0]_0 (u_ddr_prbs_gen_n_115),\n .\\dout_o_reg[0]_1 (u_ddr_prbs_gen_n_116),\n .\\dout_o_reg[0]_2 (u_ddr_prbs_gen_n_117),\n .\\dout_o_reg[0]_3 (u_ddr_prbs_gen_n_118),\n .\\dout_o_reg[0]_4 (u_ddr_prbs_gen_n_119),\n .\\dout_o_reg[0]_5 (u_ddr_prbs_gen_n_120),\n .\\dout_o_reg[0]_6 (u_ddr_prbs_gen_n_121),\n .\\dout_o_reg[1] (u_ddr_prbs_gen_n_106),\n .\\dout_o_reg[1]_0 (u_ddr_prbs_gen_n_107),\n .\\dout_o_reg[1]_1 (u_ddr_prbs_gen_n_108),\n .\\dout_o_reg[1]_2 (u_ddr_prbs_gen_n_109),\n .\\dout_o_reg[1]_3 (u_ddr_prbs_gen_n_110),\n .\\dout_o_reg[1]_4 (u_ddr_prbs_gen_n_111),\n .\\dout_o_reg[1]_5 (u_ddr_prbs_gen_n_112),\n .\\dout_o_reg[1]_6 (u_ddr_prbs_gen_n_113),\n .\\dout_o_reg[2] (u_ddr_prbs_gen_n_98),\n .\\dout_o_reg[2]_0 (u_ddr_prbs_gen_n_99),\n .\\dout_o_reg[2]_1 (u_ddr_prbs_gen_n_100),\n .\\dout_o_reg[2]_2 (u_ddr_prbs_gen_n_101),\n .\\dout_o_reg[2]_3 (u_ddr_prbs_gen_n_102),\n .\\dout_o_reg[2]_4 (u_ddr_prbs_gen_n_103),\n .\\dout_o_reg[2]_5 (u_ddr_prbs_gen_n_104),\n .\\dout_o_reg[2]_6 (u_ddr_prbs_gen_n_105),\n .\\dout_o_reg[3] (u_ddr_prbs_gen_n_90),\n .\\dout_o_reg[3]_0 (u_ddr_prbs_gen_n_91),\n .\\dout_o_reg[3]_1 (u_ddr_prbs_gen_n_92),\n .\\dout_o_reg[3]_2 (u_ddr_prbs_gen_n_93),\n .\\dout_o_reg[3]_3 (u_ddr_prbs_gen_n_94),\n .\\dout_o_reg[3]_4 (u_ddr_prbs_gen_n_95),\n .\\dout_o_reg[3]_5 (u_ddr_prbs_gen_n_96),\n .\\dout_o_reg[3]_6 (u_ddr_prbs_gen_n_97),\n .\\dout_o_reg[4] (u_ddr_prbs_gen_n_82),\n .\\dout_o_reg[4]_0 (u_ddr_prbs_gen_n_83),\n .\\dout_o_reg[4]_1 (u_ddr_prbs_gen_n_84),\n .\\dout_o_reg[4]_2 (u_ddr_prbs_gen_n_85),\n .\\dout_o_reg[4]_3 (u_ddr_prbs_gen_n_86),\n .\\dout_o_reg[4]_4 (u_ddr_prbs_gen_n_87),\n .\\dout_o_reg[4]_5 (u_ddr_prbs_gen_n_88),\n .\\dout_o_reg[4]_6 (u_ddr_prbs_gen_n_89),\n .\\dout_o_reg[5] (u_ddr_prbs_gen_n_74),\n .\\dout_o_reg[5]_0 (u_ddr_prbs_gen_n_75),\n .\\dout_o_reg[5]_1 (u_ddr_prbs_gen_n_76),\n .\\dout_o_reg[5]_2 (u_ddr_prbs_gen_n_77),\n .\\dout_o_reg[5]_3 (u_ddr_prbs_gen_n_78),\n .\\dout_o_reg[5]_4 (u_ddr_prbs_gen_n_79),\n .\\dout_o_reg[5]_5 (u_ddr_prbs_gen_n_80),\n .\\dout_o_reg[5]_6 (u_ddr_prbs_gen_n_81),\n .\\dout_o_reg[6] (u_ddr_prbs_gen_n_66),\n .\\dout_o_reg[6]_0 (u_ddr_prbs_gen_n_67),\n .\\dout_o_reg[6]_1 (u_ddr_prbs_gen_n_68),\n .\\dout_o_reg[6]_2 (u_ddr_prbs_gen_n_69),\n .\\dout_o_reg[6]_3 (u_ddr_prbs_gen_n_70),\n .\\dout_o_reg[6]_4 (u_ddr_prbs_gen_n_71),\n .\\dout_o_reg[6]_5 (u_ddr_prbs_gen_n_72),\n .\\dout_o_reg[6]_6 (u_ddr_prbs_gen_n_73),\n .\\dout_o_reg[7] (u_ddr_prbs_gen_n_58),\n .\\dout_o_reg[7]_0 (u_ddr_prbs_gen_n_59),\n .\\dout_o_reg[7]_1 (u_ddr_prbs_gen_n_60),\n .\\dout_o_reg[7]_2 (u_ddr_prbs_gen_n_61),\n .\\dout_o_reg[7]_3 (u_ddr_prbs_gen_n_62),\n .\\dout_o_reg[7]_4 (u_ddr_prbs_gen_n_63),\n .\\dout_o_reg[7]_5 (u_ddr_prbs_gen_n_64),\n .\\dout_o_reg[7]_6 (u_ddr_prbs_gen_n_65),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ),\n .dqs_found_done_r_reg(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_10 ),\n .\\fine_delay_mod_reg[20] (\\fine_delay_mod_reg[20] ),\n .\\fine_delay_mod_reg[26] (\\fine_delay_mod_reg[26] ),\n .\\fine_delay_mod_reg[5] (\\fine_delay_mod_reg[5] ),\n .fine_delay_sel_r_reg(fine_delay_sel_r_reg),\n .fine_delay_sel_reg_0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_102 ),\n .fine_delay_sel_reg_1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_104 ),\n .fine_dly_error_reg_0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_108 ),\n .fine_dly_error_reg_1(prbs_rdlvl_done_i_1_n_0),\n .\\genblk8[0].left_edge_found_pb_reg[0]_0 (\\genblk8[0].left_edge_found_pb[0]_i_1_n_0 ),\n .\\genblk8[0].left_edge_updated_reg[0]_0 (\\genblk8[0].left_edge_updated[0]_i_1_n_0 ),\n .\\genblk8[0].left_loss_pb_reg[0]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_15 ),\n .\\genblk8[0].left_loss_pb_reg[0]_1 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_69 ),\n .\\genblk8[0].right_edge_found_pb_reg[0]_0 (\\genblk8[0].right_edge_found_pb[0]_i_1_n_0 ),\n .\\genblk8[0].right_edge_pb_reg[0]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_23 ),\n .\\genblk8[0].right_edge_pb_reg[0]_1 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_68 ),\n .\\genblk8[1].left_edge_found_pb_reg[1]_0 (\\genblk8[1].left_edge_found_pb[1]_i_1_n_0 ),\n .\\genblk8[1].left_edge_updated_reg[1]_0 (\\genblk8[1].left_edge_updated[1]_i_1_n_0 ),\n .\\genblk8[1].left_loss_pb_reg[6]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_16 ),\n .\\genblk8[1].right_edge_found_pb_reg[1]_0 (\\genblk8[1].right_edge_found_pb[1]_i_1_n_0 ),\n .\\genblk8[1].right_edge_pb_reg[6]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_24 ),\n .\\genblk8[2].left_edge_found_pb_reg[2]_0 (\\genblk8[2].left_edge_found_pb[2]_i_1_n_0 ),\n .\\genblk8[2].left_edge_updated_reg[2]_0 (\\genblk8[2].left_edge_updated[2]_i_1_n_0 ),\n .\\genblk8[2].left_loss_pb_reg[12]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_17 ),\n .\\genblk8[2].right_edge_found_pb_reg[2]_0 (\\genblk8[2].right_edge_found_pb[2]_i_1_n_0 ),\n .\\genblk8[2].right_edge_pb_reg[12]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_25 ),\n .\\genblk8[2].right_edge_pb_reg[12]_1 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_64 ),\n .\\genblk8[2].right_edge_pb_reg[12]_2 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_65 ),\n .\\genblk8[3].left_edge_found_pb_reg[3]_0 (\\genblk8[3].left_edge_found_pb[3]_i_1_n_0 ),\n .\\genblk8[3].left_edge_updated_reg[3]_0 (\\genblk8[3].left_edge_updated[3]_i_1_n_0 ),\n .\\genblk8[3].left_loss_pb_reg[18]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_18 ),\n .\\genblk8[3].right_edge_found_pb_reg[3]_0 (\\genblk8[3].right_edge_found_pb[3]_i_1_n_0 ),\n .\\genblk8[3].right_edge_pb_reg[18]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_26 ),\n .\\genblk8[4].left_edge_found_pb_reg[4]_0 (\\genblk8[4].left_edge_found_pb[4]_i_1_n_0 ),\n .\\genblk8[4].left_edge_updated_reg[4]_0 (\\genblk8[4].left_edge_updated[4]_i_1_n_0 ),\n .\\genblk8[4].left_loss_pb_reg[24]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_19 ),\n .\\genblk8[4].right_edge_found_pb_reg[4]_0 (\\genblk8[4].right_edge_found_pb[4]_i_1_n_0 ),\n .\\genblk8[4].right_edge_pb_reg[24]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_27 ),\n .\\genblk8[5].left_edge_found_pb_reg[5]_0 (\\genblk8[5].left_edge_found_pb[5]_i_1_n_0 ),\n .\\genblk8[5].left_edge_updated_reg[5]_0 (\\genblk8[5].left_edge_updated[5]_i_1_n_0 ),\n .\\genblk8[5].left_loss_pb_reg[30]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_20 ),\n .\\genblk8[5].right_edge_found_pb_reg[5]_0 (\\genblk8[5].right_edge_found_pb[5]_i_1_n_0 ),\n .\\genblk8[5].right_edge_pb_reg[30]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_28 ),\n .\\genblk8[5].right_edge_pb_reg[30]_1 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_58 ),\n .\\genblk8[5].right_gain_pb_reg[30]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_59 ),\n .\\genblk8[6].left_edge_found_pb_reg[6]_0 (\\genblk8[6].left_edge_found_pb[6]_i_1_n_0 ),\n .\\genblk8[6].left_edge_updated_reg[6]_0 (\\genblk8[6].left_edge_updated[6]_i_1_n_0 ),\n .\\genblk8[6].left_loss_pb_reg[36]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_21 ),\n .\\genblk8[6].right_edge_found_pb_reg[6]_0 (\\genblk8[6].right_edge_found_pb[6]_i_1_n_0 ),\n .\\genblk8[6].right_edge_pb_reg[36]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_29 ),\n .\\genblk8[7].left_edge_found_pb_reg[7]_0 (\\genblk8[7].left_edge_found_pb[7]_i_1_n_0 ),\n .\\genblk8[7].left_edge_updated_reg[7]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ),\n .\\genblk8[7].left_edge_updated_reg[7]_1 (\\genblk8[7].left_edge_updated[7]_i_1_n_0 ),\n .\\genblk8[7].left_loss_pb_reg[42]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_22 ),\n .\\genblk8[7].right_edge_found_pb_reg[7]_0 (\\genblk8[7].right_edge_found_pb[7]_i_1_n_0 ),\n .\\genblk8[7].right_edge_pb_reg[42]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_30 ),\n .\\genblk8[7].right_edge_pb_reg[42]_1 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ),\n .\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_78 ),\n .\\genblk9[1].fine_delay_incdec_pb_reg[1]_0 (\\genblk9[1].fine_delay_incdec_pb_reg[1] ),\n .\\genblk9[2].fine_delay_incdec_pb_reg[2]_0 (\\genblk9[2].fine_delay_incdec_pb_reg[2] ),\n .\\genblk9[3].fine_delay_incdec_pb_reg[3]_0 (\\genblk9[3].fine_delay_incdec_pb_reg[3] ),\n .\\genblk9[5].fine_delay_incdec_pb_reg[5]_0 (\\genblk9[5].fine_delay_incdec_pb_reg[5] ),\n .\\genblk9[6].fine_delay_incdec_pb_reg[6]_0 (\\genblk9[6].fine_delay_incdec_pb_reg[6] ),\n .\\genblk9[7].fine_delay_incdec_pb_reg[7]_0 (\\genblk9[7].fine_delay_incdec_pb_reg[7] ),\n .\\init_state_r_reg[0] (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_87 ),\n .\\init_state_r_reg[0]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_89 ),\n .\\init_state_r_reg[1] (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_88 ),\n .\\init_state_r_reg[1]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_90 ),\n .\\largest_left_edge_reg[0]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_35 ),\n .\\match_flag_or_reg[0]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_34 ),\n .new_cnt_dqs_r(new_cnt_dqs_r),\n .new_cnt_dqs_r_reg_0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_113 ),\n .new_cnt_dqs_r_reg_1(prbs_dqs_tap_limit_r_i_1_n_0),\n .no_err_win_detected_latch_reg_0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_11 ),\n .no_err_win_detected_latch_reg_1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_103 ),\n .no_err_win_detected_reg_0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_98 ),\n .no_err_win_detected_reg_1(right_edge_found_i_1_n_0),\n .\\num_refresh_reg[1] (u_ddr_phy_init_n_117),\n .num_samples_done_ind_reg_0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_106 ),\n .num_samples_done_r(num_samples_done_r),\n .ocal_last_byte_done(ocal_last_byte_done),\n .oclkdelay_center_calib_done_r_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_4 ),\n .\\oclkdelay_ref_cnt_reg[0] (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_85 ),\n .\\one_rank.stg1_wr_done_reg (u_ddr_phy_init_n_116),\n .p_103_out(p_103_out),\n .p_106_out(p_106_out),\n .p_119_out(p_119_out),\n .p_122_out(p_122_out),\n .p_127_out(p_127_out),\n .p_130_out(p_130_out),\n .p_143_out(p_143_out),\n .p_146_out(p_146_out),\n .p_154_out(p_154_out),\n .p_95_out(p_95_out),\n .p_98_out(p_98_out),\n .\\pi_counter_read_val_reg[5] ({\\pi_counter_read_val_reg[5] [5],\\pi_counter_read_val_reg[5] [3],\\pi_counter_read_val_reg[5] [1:0]}),\n .pi_en_stg2_f_timing_reg_0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_4 ),\n .\\prbs_dec_tap_cnt_reg[1]_0 ({dec_cnt_reg[5],dec_cnt_reg[0]}),\n .\\prbs_dqs_cnt_r_reg[0]_0 (\\prbs_dqs_cnt_r[1]_i_1_n_0 ),\n .\\prbs_dqs_cnt_r_reg[0]_1 (\\prbs_dqs_cnt_r[0]_i_1_n_0 ),\n .\\prbs_dqs_cnt_r_reg[0]_2 (\\prbs_dqs_cnt_r[2]_i_1_n_0 ),\n .\\prbs_dqs_cnt_r_reg[1]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_110 ),\n .\\prbs_dqs_cnt_r_reg[2]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_50 ),\n .prbs_found_1st_edge_r_reg_0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_14 ),\n .prbs_found_1st_edge_r_reg_1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_99 ),\n .prbs_last_byte_done(prbs_last_byte_done),\n .prbs_last_byte_done_reg_0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_112 ),\n .prbs_pi_stg2_f_en(prbs_pi_stg2_f_en),\n .prbs_pi_stg2_f_incdec(prbs_pi_stg2_f_incdec),\n .prbs_prech_req_r(prbs_prech_req_r),\n .prbs_rdlvl_done_pulse0(prbs_rdlvl_done_pulse0),\n .prbs_rdlvl_done_r1(prbs_rdlvl_done_r1),\n .prbs_rdlvl_done_reg_0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_44 ),\n .prbs_rdlvl_done_reg_1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_111 ),\n .prbs_rdlvl_start_r(prbs_rdlvl_start_r),\n .prbs_rdlvl_start_reg(prbs_rdlvl_start_r_reg),\n .prbs_rdlvl_start_reg_0(u_ddr_phy_init_n_127),\n .prbs_state_r178_out(prbs_state_r178_out),\n .\\prbs_state_r_reg[0]_0 (fine_delay_sel_i_1_n_0),\n .\\prbs_state_r_reg[0]_1 (prbs_tap_inc_r_i_1_n_0),\n .\\prbs_state_r_reg[0]_2 (prbs_tap_en_r_i_1_n_0),\n .\\prbs_state_r_reg[0]_3 (prbs_last_byte_done_i_1_n_0),\n .\\prbs_state_r_reg[0]_4 (complex_pi_incdec_done_i_1_n_0),\n .\\prbs_state_r_reg[3]_0 (prbs_found_1st_edge_r_i_1_n_0),\n .\\prbs_state_r_reg[3]_1 (no_err_win_detected_latch_i_1_n_0),\n .\\prbs_state_r_reg[4]_0 (new_cnt_dqs_r_i_1_n_0),\n .\\prbs_state_r_reg[4]_1 (num_samples_done_ind_i_1_n_0),\n .\\prbs_state_r_reg[4]_2 (reset_rd_addr_i_1_n_0),\n .\\prbs_state_r_reg[4]_3 (complex_init_pi_dec_done_r_i_1_n_0),\n .prbs_tap_en_r(prbs_tap_en_r),\n .prbs_tap_en_r_reg_0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_100 ),\n .prbs_tap_inc_r(prbs_tap_inc_r),\n .prbs_tap_inc_r_reg_0(pi_stg2_f_incdec_timing_i_1_n_0),\n .prech_done(prech_done),\n .prech_done_reg(prbs_prech_req_r_i_1_n_0),\n .prech_req_r_reg(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_2 ),\n .\\rd_victim_sel_reg[2]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_84 ),\n .\\rd_victim_sel_reg[2]_1 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_115 ),\n .\\rd_victim_sel_reg[2]_2 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_116 ),\n .\\rd_victim_sel_reg[2]_3 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_117 ),\n .\\rdlvl_cpt_tap_cnt_reg[5]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_13 ),\n .\\rdlvl_cpt_tap_cnt_reg[5]_1 ({\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_93 ,\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_94 ,\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_95 }),\n .rdlvl_last_byte_done(rdlvl_last_byte_done),\n .rdlvl_stg1_done_int_reg(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_56 ),\n .rdlvl_stg1_start_int(rdlvl_stg1_start_int),\n .reset_rd_addr(reset_rd_addr),\n .reset_rd_addr0(reset_rd_addr0),\n .right_edge_found(right_edge_found),\n .right_edge_found_reg_0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_32 ),\n .right_edge_found_reg_1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_79 ),\n .right_gain_pb(right_gain_pb),\n .\\row_cnt_victim_rotate.complex_row_cnt_reg[4] (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_1 ),\n .rstdiv0_sync_r1_reg_rep(rstdiv0_sync_r1_reg_rep),\n .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2),\n .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22),\n .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23),\n .rstdiv0_sync_r1_reg_rep__7(rstdiv0_sync_r1_reg_rep__7),\n .rstdiv0_sync_r1_reg_rep__8(rstdiv0_sync_r1_reg_rep__8),\n .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9),\n .\\stage_cnt_reg[1]_0 (\\genblk9[0].fine_delay_incdec_pb[0]_i_7_n_0 ),\n .\\stg1_wr_rd_cnt_reg[3] (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_45 ),\n .wrcal_done_reg(u_ddr_phy_wrcal_n_82),\n .wrlvl_final_mux(wrlvl_final_mux));\n ddr3_ifmig_7series_v4_0_ddr_phy_rdlvl \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl \n (.CLK(CLK),\n .COUNTERLOADVAL(COUNTERLOADVAL),\n .D({\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_155 ,\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_156 }),\n .E(u_ddr_phy_init_n_465),\n .\\FSM_sequential_cal1_state_r_reg[1]_0 (rdlvl_pi_incdec_i_1_n_0),\n .\\FSM_sequential_cal1_state_r_reg[2]_0 (idel_adj_inc_i_1_n_0),\n .\\FSM_sequential_cal1_state_r_reg[3]_0 (mpr_dec_cpt_r_i_1_n_0),\n .\\FSM_sequential_cal1_state_r_reg[4]_0 (idel_pat_detect_valid_r_i_1_n_0),\n .\\FSM_sequential_cal1_state_r_reg[4]_1 (mpr_last_byte_done_i_1_n_0),\n .\\FSM_sequential_cal1_state_r_reg[4]_2 (mpr_rank_done_r_i_1_n_0),\n .\\FSM_sequential_cal1_state_r_reg[4]_3 (rdlvl_rank_done_r_i_1_n_0),\n .\\FSM_sequential_cal1_state_r_reg[4]_4 (rdlvl_last_byte_done_int_i_1_n_0),\n .Q(calib_zero_inputs__0),\n .SR(SR),\n .cal1_cnt_cpt_r1(cal1_cnt_cpt_r1),\n .cal1_dq_idel_ce_reg_0(u_ddr_phy_wrcal_n_89),\n .cal1_state_r1535_out(cal1_state_r1535_out),\n .cal1_wait_r(cal1_wait_r),\n .calib_in_common(calib_in_common),\n .\\calib_sel_reg[3] (\\po_rdval_cnt_reg[8] ),\n .\\calib_sel_reg[3]_0 ({\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_93 ,\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_94 ,\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_95 }),\n .cmd_delay_start0(cmd_delay_start0),\n .\\cnt_idel_dec_cpt_r_reg[0]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_60 ),\n .cnt_init_af_done_r(cnt_init_af_done_r),\n .complex_ocal_ref_req(complex_ocal_ref_req),\n .detect_edge_done_r(detect_edge_done_r),\n .\\dout_o_reg[6] (u_ddr_prbs_gen_n_70),\n .\\dout_o_reg[6]_0 (u_ddr_prbs_gen_n_66),\n .dqs_found_done_r_reg(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_10 ),\n .dqs_found_done_r_reg_0(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_82 ),\n .dqs_found_prech_req(dqs_found_prech_req),\n .dqs_po_dec_done(dqs_po_dec_done),\n .dqs_po_dec_done_r2(dqs_po_dec_done_r2),\n .first_wrcal_pat_r(first_wrcal_pat_r),\n .found_edge_r_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_40 ),\n .found_edge_r_reg_1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_41 ),\n .found_edge_r_reg_2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_42 ),\n .found_edge_r_reg_3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_44 ),\n .found_edge_r_reg_4(found_first_edge_r_i_1_n_0),\n .found_first_edge_r_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_4 ),\n .found_stable_eye_last_r(found_stable_eye_last_r),\n .found_stable_eye_last_r_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_3 ),\n .found_stable_eye_last_r_reg_1(found_second_edge_r_i_1_n_0),\n .found_stable_eye_r_reg_0(found_stable_eye_last_r_i_1_n_0),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[2] (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_158 ),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_159 ),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_157 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_0 (\\phaser_in_gen.phaser_in_i_12_n_0 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_1 (\\phaser_in_gen.phaser_in_i_12__0_n_0 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_2 (\\phaser_in_gen.phaser_in_i_12__1_n_0 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_3 (\\phaser_in_gen.phaser_in_i_12__2_n_0 ),\n .\\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_30 ),\n .\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg[0]_0 (\\gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1_n_0 ),\n .\\gen_track_left_edge[0].pb_detect_edge_done_r_reg[0]_0 (\\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1_n_0 ),\n .\\gen_track_left_edge[0].pb_found_edge_r_reg[0]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_39 ),\n .\\gen_track_left_edge[0].pb_found_edge_r_reg[0]_1 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_108 ),\n .\\gen_track_left_edge[0].pb_found_edge_r_reg[0]_2 (\\gen_track_left_edge[0].pb_found_edge_r[0]_i_1_n_0 ),\n .\\gen_track_left_edge[0].pb_found_stable_eye_r_reg (\\gen_track_left_edge[0].pb_found_stable_eye_r_reg ),\n .\\gen_track_left_edge[0].pb_found_stable_eye_r_reg[0]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_124 ),\n .\\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_9 ),\n .\\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_107 ),\n .\\gen_track_left_edge[1].pb_detect_edge_done_r_reg[1]_0 (\\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1_n_0 ),\n .\\gen_track_left_edge[1].pb_found_edge_r_reg[1]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_110 ),\n .\\gen_track_left_edge[1].pb_found_edge_r_reg[1]_1 (\\gen_track_left_edge[1].pb_found_edge_r[1]_i_1_n_0 ),\n .\\gen_track_left_edge[1].pb_found_stable_eye_r_reg (\\gen_track_left_edge[1].pb_found_stable_eye_r_reg ),\n .\\gen_track_left_edge[1].pb_found_stable_eye_r_reg[1]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_126 ),\n .\\gen_track_left_edge[2].pb_detect_edge_done_r_reg[2]_0 (\\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1_n_0 ),\n .\\gen_track_left_edge[2].pb_found_edge_r_reg[2]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_112 ),\n .\\gen_track_left_edge[2].pb_found_edge_r_reg[2]_1 (\\gen_track_left_edge[2].pb_found_edge_r[2]_i_1_n_0 ),\n .\\gen_track_left_edge[2].pb_found_stable_eye_r_reg (\\gen_track_left_edge[2].pb_found_stable_eye_r_reg ),\n .\\gen_track_left_edge[2].pb_found_stable_eye_r_reg[2]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_128 ),\n .\\gen_track_left_edge[3].pb_detect_edge_done_r_reg[3]_0 (\\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1_n_0 ),\n .\\gen_track_left_edge[3].pb_found_edge_r_reg[3]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_114 ),\n .\\gen_track_left_edge[3].pb_found_edge_r_reg[3]_1 (\\gen_track_left_edge[3].pb_found_edge_r[3]_i_1_n_0 ),\n .\\gen_track_left_edge[3].pb_found_stable_eye_r_reg (\\gen_track_left_edge[3].pb_found_stable_eye_r_reg ),\n .\\gen_track_left_edge[3].pb_found_stable_eye_r_reg[3]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_130 ),\n .\\gen_track_left_edge[4].pb_detect_edge_done_r_reg[4]_0 (\\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1_n_0 ),\n .\\gen_track_left_edge[4].pb_found_edge_r_reg[4]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_43 ),\n .\\gen_track_left_edge[4].pb_found_edge_r_reg[4]_1 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_116 ),\n .\\gen_track_left_edge[4].pb_found_edge_r_reg[4]_2 (\\gen_track_left_edge[4].pb_found_edge_r[4]_i_1_n_0 ),\n .\\gen_track_left_edge[4].pb_found_stable_eye_r_reg (\\gen_track_left_edge[4].pb_found_stable_eye_r_reg ),\n .\\gen_track_left_edge[4].pb_found_stable_eye_r_reg[4]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_132 ),\n .\\gen_track_left_edge[5].pb_detect_edge_done_r_reg[5]_0 (\\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1_n_0 ),\n .\\gen_track_left_edge[5].pb_found_edge_r_reg[5]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_118 ),\n .\\gen_track_left_edge[5].pb_found_edge_r_reg[5]_1 (\\gen_track_left_edge[5].pb_found_edge_r[5]_i_1_n_0 ),\n .\\gen_track_left_edge[5].pb_found_stable_eye_r_reg (\\gen_track_left_edge[5].pb_found_stable_eye_r_reg ),\n .\\gen_track_left_edge[5].pb_found_stable_eye_r_reg[5]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_134 ),\n .\\gen_track_left_edge[6].pb_detect_edge_done_r_reg[6]_0 (\\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1_n_0 ),\n .\\gen_track_left_edge[6].pb_found_edge_r_reg[6]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_45 ),\n .\\gen_track_left_edge[6].pb_found_edge_r_reg[6]_1 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_120 ),\n .\\gen_track_left_edge[6].pb_found_edge_r_reg[6]_2 (\\gen_track_left_edge[6].pb_found_edge_r[6]_i_1_n_0 ),\n .\\gen_track_left_edge[6].pb_found_stable_eye_r_reg (\\gen_track_left_edge[6].pb_found_stable_eye_r_reg ),\n .\\gen_track_left_edge[6].pb_found_stable_eye_r_reg[6]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_136 ),\n .\\gen_track_left_edge[7].pb_detect_edge_done_r_reg[7]_0 (\\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1_n_0 ),\n .\\gen_track_left_edge[7].pb_found_edge_r_reg[7]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_46 ),\n .\\gen_track_left_edge[7].pb_found_edge_r_reg[7]_1 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_122 ),\n .\\gen_track_left_edge[7].pb_found_edge_r_reg[7]_2 (\\gen_track_left_edge[7].pb_found_edge_r[7]_i_1_n_0 ),\n .\\gen_track_left_edge[7].pb_found_stable_eye_r_reg (\\gen_track_left_edge[7].pb_found_stable_eye_r_reg ),\n .\\gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_137 ),\n .\\gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_1 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_138 ),\n .\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ),\n .\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .idel_adj_inc_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_52 ),\n .idel_adj_inc_reg_1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_88 ),\n .idel_adj_inc_reg_2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_140 ),\n .\\idel_dec_cnt_reg[0]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_186 ),\n .idelay_ce_int(idelay_ce_int),\n .idelay_inc_int(idelay_inc_int),\n .\\init_state_r_reg[0] (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_80 ),\n .\\init_state_r_reg[0]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_81 ),\n .\\init_state_r_reg[0]_1 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_82 ),\n .\\init_state_r_reg[0]_2 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_148 ),\n .\\init_state_r_reg[0]_3 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_150 ),\n .\\init_state_r_reg[0]_4 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_152 ),\n .\\init_state_r_reg[1] (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_142 ),\n .\\init_state_r_reg[1]_0 ({u_ddr_phy_init_n_107,u_ddr_phy_init_n_108}),\n .\\init_state_r_reg[2] (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_144 ),\n .\\init_state_r_reg[2]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_145 ),\n .\\init_state_r_reg[2]_1 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_146 ),\n .\\init_state_r_reg[2]_2 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_154 ),\n .\\init_state_r_reg[3] (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_149 ),\n .\\init_state_r_reg[3]_0 (u_ddr_phy_init_n_111),\n .\\init_state_r_reg[4] (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_151 ),\n .\\init_state_r_reg[5] (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_147 ),\n .\\init_state_r_reg[5]_0 (u_ddr_phy_init_n_474),\n .mem_init_done_r(mem_init_done_r),\n .mpr_dec_cpt_r_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_51 ),\n .mpr_dec_cpt_r_reg_1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_190 ),\n .mpr_last_byte_done(mpr_last_byte_done),\n .mpr_last_byte_done_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_183 ),\n .mpr_rank_done_r_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_184 ),\n .mpr_rank_done_r_reg_1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_189 ),\n .mpr_rd_rise0_prev_r_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_50 ),\n .mpr_rd_rise0_prev_r_reg_1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_102 ),\n .mpr_rdlvl_done_r1_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ),\n .mpr_rdlvl_done_r_reg_0(mpr_rdlvl_done_r_i_1_n_0),\n .mpr_rdlvl_done_r_reg_1(rdlvl_stg1_done_int_i_1_n_0),\n .mpr_rdlvl_start_r(mpr_rdlvl_start_r),\n .mpr_rdlvl_start_reg(u_ddr_phy_init_n_464),\n .mpr_rnk_done(mpr_rnk_done),\n .mpr_valid_r1_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_6 ),\n .mpr_valid_r_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_106 ),\n .\\num_refresh_reg[1] (u_ddr_phy_init_n_117),\n .oclkdelay_calib_done_r_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ),\n .oclkdelay_center_calib_done_r_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_4 ),\n .\\one_rank.stg1_wr_done_reg (u_ddr_phy_init_n_116),\n .out({\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_83 ,\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_84 ,\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_85 ,\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_86 ,\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_87 }),\n .p_0_in(p_0_in),\n .p_0_in102_in(p_0_in102_in),\n .p_0_in10_in(p_0_in10_in),\n .p_0_in13_in(p_0_in13_in),\n .p_0_in16_in(p_0_in16_in),\n .p_0_in1_in(p_0_in1_in),\n .p_0_in4_in(p_0_in4_in),\n .p_0_in7_in(p_0_in7_in),\n .p_0_in84_in(p_0_in84_in),\n .p_0_in87_in(p_0_in87_in),\n .p_0_in90_in(p_0_in90_in),\n .p_0_in93_in(p_0_in93_in),\n .p_0_in96_in(p_0_in96_in),\n .p_0_in99_in(p_0_in99_in),\n .pb_detect_edge_done_r(pb_detect_edge_done_r),\n .pb_found_stable_eye_r52_out(pb_found_stable_eye_r52_out),\n .pb_found_stable_eye_r56_out(pb_found_stable_eye_r56_out),\n .pb_found_stable_eye_r60_out(pb_found_stable_eye_r60_out),\n .pb_found_stable_eye_r64_out(pb_found_stable_eye_r64_out),\n .pb_found_stable_eye_r68_out(pb_found_stable_eye_r68_out),\n .pb_found_stable_eye_r72_out(pb_found_stable_eye_r72_out),\n .pb_found_stable_eye_r76_out(pb_found_stable_eye_r76_out),\n .phy_rddata_en_1(phy_rddata_en_1),\n .pi_cnt_dec_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_141 ),\n .pi_cnt_dec_reg_1(pi_cnt_dec_reg),\n .\\pi_counter_read_val_reg[5] ({\\pi_counter_read_val_reg[5] [5:4],\\pi_counter_read_val_reg[5] [2:0]}),\n .\\pi_dqs_found_lanes_r1_reg[0] (\\pi_dqs_found_lanes_r1_reg[0]_0 ),\n .\\pi_dqs_found_lanes_r1_reg[0]_0 (\\pi_dqs_found_lanes_r1_reg[0]_1 ),\n .\\pi_dqs_found_lanes_r1_reg[0]_1 (\\pi_dqs_found_lanes_r1_reg[0]_2 ),\n .\\pi_dqs_found_lanes_r1_reg[1] (\\pi_dqs_found_lanes_r1_reg[1]_0 ),\n .\\pi_dqs_found_lanes_r1_reg[1]_0 (\\pi_dqs_found_lanes_r1_reg[1]_1 ),\n .\\pi_dqs_found_lanes_r1_reg[1]_1 (\\pi_dqs_found_lanes_r1_reg[1]_2 ),\n .\\pi_dqs_found_lanes_r1_reg[1]_2 (\\pi_dqs_found_lanes_r1_reg[1]_3 ),\n .\\pi_dqs_found_lanes_r1_reg[2] (\\pi_dqs_found_lanes_r1_reg[2]_0 ),\n .\\pi_dqs_found_lanes_r1_reg[2]_0 (\\pi_dqs_found_lanes_r1_reg[2]_1 ),\n .\\pi_dqs_found_lanes_r1_reg[2]_1 (\\pi_dqs_found_lanes_r1_reg[2]_2 ),\n .\\pi_dqs_found_lanes_r1_reg[2]_2 (\\pi_dqs_found_lanes_r1_reg[2]_3 ),\n .\\pi_dqs_found_lanes_r1_reg[3] (\\pi_dqs_found_lanes_r1_reg[3]_0 ),\n .\\pi_dqs_found_lanes_r1_reg[3]_0 (\\pi_dqs_found_lanes_r1_reg[3]_1 ),\n .\\pi_dqs_found_lanes_r1_reg[3]_1 (\\pi_dqs_found_lanes_r1_reg[3]_2 ),\n .\\pi_dqs_found_lanes_r1_reg[3]_2 (\\pi_dqs_found_lanes_r1_reg[3]_3 ),\n .pi_en_stg2_f_timing_reg_0(pi_en_stg2_f_timing_reg),\n .pi_fine_dly_dec_done(pi_fine_dly_dec_done),\n .\\pi_rdval_cnt_reg[1]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_96 ),\n .pi_stg2_rdlvl_cnt(pi_stg2_rdlvl_cnt),\n .\\pi_stg2_reg_l_timing_reg[0]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_99 ),\n .\\po_stg2_wrcal_cnt_reg[0] (u_ddr_phy_wrcal_n_85),\n .\\po_stg2_wrcal_cnt_reg[1] (\\idelay_tap_cnt_r_reg[0][3][0] [1]),\n .\\po_stg2_wrcal_cnt_reg[2] (u_ddr_phy_wrcal_n_107),\n .\\prbs_dqs_cnt_r_reg[2] (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_50 ),\n .prbs_last_byte_done_r(prbs_last_byte_done_r),\n .prbs_pi_stg2_f_en(prbs_pi_stg2_f_en),\n .prbs_pi_stg2_f_incdec(prbs_pi_stg2_f_incdec),\n .prbs_rdlvl_done_reg(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_45 ),\n .prbs_rdlvl_done_reg_rep(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_51 ),\n .prbs_rdlvl_done_reg_rep_0(u_ddr_phy_init_n_497),\n .prbs_rdlvl_done_reg_rep_1(u_ddr_phy_wrcal_n_94),\n .prbs_rdlvl_prech_req_reg(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_2 ),\n .prech_done(prech_done),\n .prech_req(prech_req),\n .\\rd_mux_sel_r_reg[1]_0 (\\rd_mux_sel_r_reg[1] ),\n .\\rd_mux_sel_r_reg[1]_1 (\\rd_mux_sel_r_reg[1]_0 ),\n .\\rd_mux_sel_r_reg[1]_10 (\\rd_mux_sel_r_reg[1]_9 ),\n .\\rd_mux_sel_r_reg[1]_11 (\\rd_mux_sel_r_reg[1]_10 ),\n .\\rd_mux_sel_r_reg[1]_12 (\\rd_mux_sel_r_reg[1]_11 ),\n .\\rd_mux_sel_r_reg[1]_13 (\\rd_mux_sel_r_reg[1]_12 ),\n .\\rd_mux_sel_r_reg[1]_14 (\\rd_mux_sel_r_reg[1]_13 ),\n .\\rd_mux_sel_r_reg[1]_15 (\\rd_mux_sel_r_reg[1]_14 ),\n .\\rd_mux_sel_r_reg[1]_16 (\\rd_mux_sel_r_reg[1]_15 ),\n .\\rd_mux_sel_r_reg[1]_17 (\\rd_mux_sel_r_reg[1]_16 ),\n .\\rd_mux_sel_r_reg[1]_18 (\\rd_mux_sel_r_reg[1]_17 ),\n .\\rd_mux_sel_r_reg[1]_19 (\\rd_mux_sel_r_reg[1]_18 ),\n .\\rd_mux_sel_r_reg[1]_2 (\\rd_mux_sel_r_reg[1]_1 ),\n .\\rd_mux_sel_r_reg[1]_20 (\\rd_mux_sel_r_reg[1]_19 ),\n .\\rd_mux_sel_r_reg[1]_21 (\\rd_mux_sel_r_reg[1]_20 ),\n .\\rd_mux_sel_r_reg[1]_22 (\\rd_mux_sel_r_reg[1]_21 ),\n .\\rd_mux_sel_r_reg[1]_23 (\\rd_mux_sel_r_reg[1]_22 ),\n .\\rd_mux_sel_r_reg[1]_24 (\\rd_mux_sel_r_reg[1]_23 ),\n .\\rd_mux_sel_r_reg[1]_25 (\\rd_mux_sel_r_reg[1]_24 ),\n .\\rd_mux_sel_r_reg[1]_26 (\\rd_mux_sel_r_reg[1]_25 ),\n .\\rd_mux_sel_r_reg[1]_27 (\\rd_mux_sel_r_reg[1]_26 ),\n .\\rd_mux_sel_r_reg[1]_28 (\\rd_mux_sel_r_reg[1]_27 ),\n .\\rd_mux_sel_r_reg[1]_29 (\\rd_mux_sel_r_reg[1]_28 ),\n .\\rd_mux_sel_r_reg[1]_3 (\\rd_mux_sel_r_reg[1]_2 ),\n .\\rd_mux_sel_r_reg[1]_30 (\\rd_mux_sel_r_reg[1]_29 ),\n .\\rd_mux_sel_r_reg[1]_31 (\\rd_mux_sel_r_reg[1]_30 ),\n .\\rd_mux_sel_r_reg[1]_32 (\\rd_mux_sel_r_reg[1]_31 ),\n .\\rd_mux_sel_r_reg[1]_33 (\\rd_mux_sel_r_reg[1]_32 ),\n .\\rd_mux_sel_r_reg[1]_34 (\\rd_mux_sel_r_reg[1]_33 ),\n .\\rd_mux_sel_r_reg[1]_35 (\\rd_mux_sel_r_reg[1]_34 ),\n .\\rd_mux_sel_r_reg[1]_36 (\\rd_mux_sel_r_reg[1]_35 ),\n .\\rd_mux_sel_r_reg[1]_37 (\\rd_mux_sel_r_reg[1]_36 ),\n .\\rd_mux_sel_r_reg[1]_38 (\\rd_mux_sel_r_reg[1]_37 ),\n .\\rd_mux_sel_r_reg[1]_39 (\\rd_mux_sel_r_reg[1]_38 ),\n .\\rd_mux_sel_r_reg[1]_4 (\\rd_mux_sel_r_reg[1]_3 ),\n .\\rd_mux_sel_r_reg[1]_40 (\\rd_mux_sel_r_reg[1]_39 ),\n .\\rd_mux_sel_r_reg[1]_41 (\\rd_mux_sel_r_reg[1]_40 ),\n .\\rd_mux_sel_r_reg[1]_42 (\\rd_mux_sel_r_reg[1]_41 ),\n .\\rd_mux_sel_r_reg[1]_43 (\\rd_mux_sel_r_reg[1]_42 ),\n .\\rd_mux_sel_r_reg[1]_44 (\\rd_mux_sel_r_reg[1]_43 ),\n .\\rd_mux_sel_r_reg[1]_45 (\\rd_mux_sel_r_reg[1]_44 ),\n .\\rd_mux_sel_r_reg[1]_46 (\\rd_mux_sel_r_reg[1]_45 ),\n .\\rd_mux_sel_r_reg[1]_47 (\\rd_mux_sel_r_reg[1]_46 ),\n .\\rd_mux_sel_r_reg[1]_48 (\\rd_mux_sel_r_reg[1]_47 ),\n .\\rd_mux_sel_r_reg[1]_49 (\\rd_mux_sel_r_reg[1]_48 ),\n .\\rd_mux_sel_r_reg[1]_5 (\\rd_mux_sel_r_reg[1]_4 ),\n .\\rd_mux_sel_r_reg[1]_50 (\\rd_mux_sel_r_reg[1]_49 ),\n .\\rd_mux_sel_r_reg[1]_51 (\\rd_mux_sel_r_reg[1]_50 ),\n .\\rd_mux_sel_r_reg[1]_52 (\\rd_mux_sel_r_reg[1]_51 ),\n .\\rd_mux_sel_r_reg[1]_53 (\\rd_mux_sel_r_reg[1]_52 ),\n .\\rd_mux_sel_r_reg[1]_54 (\\rd_mux_sel_r_reg[1]_53 ),\n .\\rd_mux_sel_r_reg[1]_55 (\\rd_mux_sel_r_reg[1]_54 ),\n .\\rd_mux_sel_r_reg[1]_56 (\\rd_mux_sel_r_reg[1]_55 ),\n .\\rd_mux_sel_r_reg[1]_57 (\\rd_mux_sel_r_reg[1]_56 ),\n .\\rd_mux_sel_r_reg[1]_58 (\\rd_mux_sel_r_reg[1]_57 ),\n .\\rd_mux_sel_r_reg[1]_59 (\\rd_mux_sel_r_reg[1]_58 ),\n .\\rd_mux_sel_r_reg[1]_6 (\\rd_mux_sel_r_reg[1]_5 ),\n .\\rd_mux_sel_r_reg[1]_60 (\\rd_mux_sel_r_reg[1]_59 ),\n .\\rd_mux_sel_r_reg[1]_61 (\\rd_mux_sel_r_reg[1]_60 ),\n .\\rd_mux_sel_r_reg[1]_62 (\\rd_mux_sel_r_reg[1]_61 ),\n .\\rd_mux_sel_r_reg[1]_63 (\\rd_mux_sel_r_reg[1]_62 ),\n .\\rd_mux_sel_r_reg[1]_7 (\\rd_mux_sel_r_reg[1]_6 ),\n .\\rd_mux_sel_r_reg[1]_8 (\\rd_mux_sel_r_reg[1]_7 ),\n .\\rd_mux_sel_r_reg[1]_9 (\\rd_mux_sel_r_reg[1]_8 ),\n .\\rdlvl_cpt_tap_cnt_reg[1] (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_94 ),\n .\\rdlvl_cpt_tap_cnt_reg[2] (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_95 ),\n .\\rdlvl_cpt_tap_cnt_reg[4] (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_93 ),\n .\\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 (\\rdlvl_dqs_tap_cnt_r_reg[0][3][0] ),\n .rdlvl_last_byte_done(rdlvl_last_byte_done),\n .rdlvl_pi_incdec(rdlvl_pi_incdec),\n .rdlvl_pi_incdec_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_180 ),\n .rdlvl_pi_incdec_reg_1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_185 ),\n .rdlvl_prech_req(rdlvl_prech_req),\n .rdlvl_rank_done_r_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_188 ),\n .rdlvl_stg1_done_int(rdlvl_stg1_done_int),\n .rdlvl_stg1_done_r1_reg(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_56 ),\n .rdlvl_stg1_rank_done(rdlvl_stg1_rank_done),\n .rdlvl_stg1_start_reg(u_ddr_phy_init_n_33),\n .rdlvl_stg1_start_reg_0(cnt_shift_r0),\n .\\regl_dqs_cnt_r_reg[2]_0 (regl_dqs_cnt),\n .\\regl_dqs_cnt_reg[0]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_101 ),\n .\\regl_dqs_cnt_reg[2]_0 (pi_stg2_load_timing_i_1_n_0),\n .\\right_edge_taps_r_reg[0]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_47 ),\n .\\right_edge_taps_r_reg[0]_1 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_91 ),\n .\\right_edge_taps_r_reg[0]_2 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_139 ),\n .rstdiv0_sync_r1_reg_rep__13(rstdiv0_sync_r1_reg_rep__13),\n .rstdiv0_sync_r1_reg_rep__14(rstdiv0_sync_r1_reg_rep__14),\n .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22),\n .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23),\n .samp_cnt_done_r_reg_0(\\gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_2_n_0 ),\n .samp_cnt_done_r_reg_1(\\gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1_n_0 ),\n .samp_cnt_done_r_reg_2(\\gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1_n_0 ),\n .samp_cnt_done_r_reg_3(\\gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1_n_0 ),\n .samp_cnt_done_r_reg_4(\\gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1_n_0 ),\n .samp_cnt_done_r_reg_5(\\gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1_n_0 ),\n .samp_cnt_done_r_reg_6(\\gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1_n_0 ),\n .samp_edge_cnt0_en_r(samp_edge_cnt0_en_r),\n .samp_edge_cnt0_en_r_reg_0(samp_edge_cnt0_en_r_reg),\n .\\second_edge_taps_r_reg[5]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_161 ),\n .sr_valid_r108_out(sr_valid_r108_out),\n .sr_valid_r1_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_2 ),\n .stg1_wr_done(stg1_wr_done),\n .\\stg1_wr_rd_cnt_reg[3] (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_79 ),\n .store_sr_r_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_1 ),\n .store_sr_req_r_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_92 ),\n .store_sr_req_r_reg_1(store_sr_r_i_1_n_0),\n .tempmon_pi_f_en_r(tempmon_pi_f_en_r),\n .tempmon_pi_f_inc_r(tempmon_pi_f_inc_r),\n .\\wait_cnt_r_reg[0]_0 (wait_cnt_r_reg__0),\n .\\wait_cnt_r_reg[0]_1 (pi_cnt_dec_i_1_n_0),\n .wr_level_done_reg(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_12 ),\n .wrcal_done_reg(u_ddr_phy_wrcal_n_82),\n .wrcal_prech_req(wrcal_prech_req),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[254] (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_153 ),\n .wrlvl_byte_redo(wrlvl_byte_redo),\n .wrlvl_byte_redo_reg(u_ddr_phy_wrcal_n_95),\n .wrlvl_done_r1(wrlvl_done_r1),\n .wrlvl_done_r1_reg(u_ddr_phy_wrcal_n_91),\n .wrlvl_done_r1_reg_0(u_ddr_phy_init_n_499),\n .wrlvl_final_mux(wrlvl_final_mux),\n .wrlvl_final_mux_reg(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_84 ));\n ddr3_ifmig_7series_v4_0_ddr_phy_tempmon ddr_phy_tempmon_0\n (.CLK(CLK),\n .D(ddr_phy_tempmon_0_n_3),\n .SS(SS),\n .calib_complete(calib_complete),\n .calib_in_common(calib_in_common),\n .\\calib_zero_inputs_reg[1] (ddr_phy_tempmon_0_n_4),\n .\\calib_zero_inputs_reg[1]_0 (ddr_phy_tempmon_0_n_5),\n .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done),\n .cmd_delay_start0(cmd_delay_start0),\n .ctl_lane_sel(ctl_lane_sel),\n .delay_done_r4_reg(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_98 ),\n .\\device_temp_r_reg[11] (\\device_temp_r_reg[11] ),\n .fine_adjust_done_r_reg(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_12 ),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[0] (ddr_phy_tempmon_0_n_2),\n .\\gen_byte_sel_div1.calib_in_common_reg (ddr_phy_tempmon_0_n_6),\n .oclkdelay_calib_done_r_reg(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_157 ),\n .rd_data_offset_cal_done(rd_data_offset_cal_done),\n .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2),\n .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),\n .rstdiv0_sync_r1_reg_rep__4(rstdiv0_sync_r1_reg_rep__4),\n .rstdiv0_sync_r1_reg_rep__5(rstdiv0_sync_r1_reg_rep__5),\n .rstdiv0_sync_r1_reg_rep__6(rstdiv0_sync_r1_reg_rep__6),\n .rstdiv0_sync_r1_reg_rep__7(rstdiv0_sync_r1_reg_rep__7),\n .tempmon_pi_f_inc(tempmon_pi_f_inc),\n .tempmon_sample_en(tempmon_sample_en),\n .tempmon_sel_pi_incdec(tempmon_sel_pi_incdec));\n LUT6 #(\n .INIT(64'hFEFFFFFF02000000)) \n dq_cnt_inc_i_1\n (.I0(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_56 ),\n .I1(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_30 ),\n .I2(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_29 ),\n .I3(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_31 ),\n .I4(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_27 ),\n .I5(p_0_in_2),\n .O(dq_cnt_inc_i_1_n_0));\n LUT6 #(\n .INIT(64'h00E2FFFF00E20000)) \n dqs_found_prech_req_i_1\n (.I0(fine_adj_state_r16_out),\n .I1(fine_adj_state_r144_out),\n .I2(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_74 ),\n .I3(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_44 ),\n .I4(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_106 ),\n .I5(dqs_found_prech_req),\n .O(dqs_found_prech_req_i_1_n_0));\n ddr3_ifmig_7series_v4_0_ddr_phy_dqs_found_cal \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal \n (.CLK(CLK),\n .D({\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_99 ,\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_100 }),\n .D_po_fine_enable107_out(D_po_fine_enable107_out),\n .D_po_fine_inc113_out(D_po_fine_inc113_out),\n .\\FSM_sequential_fine_adj_state_r_reg[0]_0 ({\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_43 ,\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_44 ,\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ,\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_46 }),\n .\\FSM_sequential_fine_adj_state_r_reg[0]_1 (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_76 ),\n .\\FSM_sequential_fine_adj_state_r_reg[0]_2 (fine_adjust_i_1_n_0),\n .\\FSM_sequential_fine_adj_state_r_reg[0]_3 (fine_adjust_done_r_i_1_n_0),\n .\\FSM_sequential_fine_adj_state_r_reg[1]_0 (rst_dqs_find_i_1_n_0),\n .\\FSM_sequential_fine_adj_state_r_reg[1]_1 (final_dec_done_i_1_n_0),\n .\\FSM_sequential_fine_adj_state_r_reg[1]_2 (ck_po_stg2_f_indec_i_1_n_0),\n .\\FSM_sequential_fine_adj_state_r_reg[1]_3 (ck_po_stg2_f_en_i_1_n_0),\n .\\FSM_sequential_fine_adj_state_r_reg[2]_0 (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_41 ),\n .\\FSM_sequential_fine_adj_state_r_reg[2]_1 (dqs_found_prech_req_i_1_n_0),\n .Q(\\po_rdval_cnt_reg[8] [1:0]),\n .SR(SR),\n .byte_sel_cnt(byte_sel_cnt),\n .\\calib_data_offset_0_reg[0] (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_89 ),\n .\\calib_data_offset_0_reg[1] (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_88 ),\n .\\calib_data_offset_0_reg[4] (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_87 ),\n .\\calib_data_offset_0_reg[5] (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_86 ),\n .\\calib_data_offset_1_reg[0] (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_93 ),\n .\\calib_data_offset_1_reg[1] (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_92 ),\n .\\calib_data_offset_1_reg[4] (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_91 ),\n .\\calib_data_offset_1_reg[5] (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_90 ),\n .calib_in_common(calib_in_common),\n .\\calib_zero_inputs_reg[0] (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_101 ),\n .\\calib_zero_inputs_reg[1] (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_98 ),\n .\\calib_zero_inputs_reg[1]_0 ({calib_zero_inputs,calib_zero_inputs__0}),\n .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done),\n .ck_po_stg2_f_en(ck_po_stg2_f_en),\n .ck_po_stg2_f_indec(ck_po_stg2_f_indec),\n .cmd_delay_start0(cmd_delay_start0),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[0] (\\cmd_pipe_plus.mc_data_offset_1_reg[0] ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[1] (\\cmd_pipe_plus.mc_data_offset_1_reg[1] ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[4] (\\cmd_pipe_plus.mc_data_offset_1_reg[4] ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[5] (\\cmd_pipe_plus.mc_data_offset_1_reg[5] ),\n .\\cmd_pipe_plus.mc_data_offset_reg[0] (\\cmd_pipe_plus.mc_data_offset_reg[0] ),\n .\\cmd_pipe_plus.mc_data_offset_reg[1] (\\cmd_pipe_plus.mc_data_offset_reg[1] ),\n .\\cmd_pipe_plus.mc_data_offset_reg[4] (\\cmd_pipe_plus.mc_data_offset_reg[4] ),\n .\\cmd_pipe_plus.mc_data_offset_reg[5] (\\cmd_pipe_plus.mc_data_offset_reg[5] ),\n .cnt_cmd_done_r(cnt_cmd_done_r),\n .ctl_lane_cnt(ctl_lane_cnt),\n .ctl_lane_sel(ctl_lane_sel),\n .\\dec_cnt_reg[0]_0 (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_42 ),\n .detect_pi_found_dqs(detect_pi_found_dqs),\n .dqs_found_prech_req(dqs_found_prech_req),\n .dqs_found_prech_req_reg_0(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_74 ),\n .dqs_found_prech_req_reg_1(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_106 ),\n .dqs_po_dec_done(dqs_po_dec_done),\n .dqs_po_en_stg2_f(dqs_po_en_stg2_f),\n .dqs_po_stg2_f_incdec(dqs_po_stg2_f_incdec),\n .final_dec_done_reg_0(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_14 ),\n .final_dec_done_reg_1(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_75 ),\n .fine_adj_state_r144_out(fine_adj_state_r144_out),\n .fine_adj_state_r16_out(fine_adj_state_r16_out),\n .fine_adjust_done_r_reg_0(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_12 ),\n .fine_adjust_reg_0(fine_adjust_reg),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[0] (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_102 ),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 (\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[1] (\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_27 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_0 (\\phaser_in_gen.phaser_in_i_12_n_0 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_1 (\\phaser_in_gen.phaser_in_i_12__0_n_0 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_2 (\\phaser_in_gen.phaser_in_i_12__1_n_0 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_3 (\\phaser_in_gen.phaser_in_i_12__2_n_0 ),\n .\\gen_byte_sel_div1.ctl_lane_sel_reg[0] (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_94 ),\n .\\gen_byte_sel_div1.ctl_lane_sel_reg[0]_0 (\\gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[0] ),\n .\\gen_byte_sel_div1.ctl_lane_sel_reg[1] (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_96 ),\n .\\gen_byte_sel_div1.ctl_lane_sel_reg[1]_0 (\\gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[1] ),\n .\\gen_byte_sel_div1.ctl_lane_sel_reg[2] (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_97 ),\n .\\gen_byte_sel_div1.ctl_lane_sel_reg[2]_0 (\\gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[2] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_83 ),\n .ififo_rst_reg(ififo_rst_reg),\n .ififo_rst_reg_0(ififo_rst_reg_0),\n .ififo_rst_reg_1(ififo_rst_reg_1),\n .ififo_rst_reg_2(ififo_rst_reg_2),\n .in0(in0),\n .init_calib_complete_reg(ddr_phy_tempmon_0_n_5),\n .init_dec_done_reg_0(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_13 ),\n .init_dec_done_reg_1(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_108 ),\n .init_dec_done_reg_2(init_dec_done_i_1_n_0),\n .init_dqsfound_done_r2(init_dqsfound_done_r2),\n .init_dqsfound_done_r5(init_dqsfound_done_r5),\n .init_dqsfound_done_r_reg_0(init_dqsfound_done_r_i_1_n_0),\n .\\init_state_r_reg[1] (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_81 ),\n .\\init_state_r_reg[1]_0 (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_84 ),\n .\\init_state_r_reg[1]_1 (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_85 ),\n .\\init_state_r_reg[2] (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_82 ),\n .mpr_rdlvl_done_r_reg(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_147 ),\n .\\num_refresh_reg[1] (u_ddr_phy_init_n_117),\n .oclkdelay_calib_done_r_reg(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_157 ),\n .oclkdelay_calib_done_r_reg_0(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ),\n .oclkdelay_center_calib_done_r_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_4 ),\n .out({p_3_in25_in,p_2_in24_in,p_0_in23_in,\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_5 }),\n .p_1_in27_in(p_1_in27_in),\n .p_1_in50_in(p_1_in50_in),\n .pi_calib_done(pi_calib_done),\n .\\pi_dqs_found_all_bank_r_reg[1]_0 (pi_dqs_found_all_bank),\n .\\pi_dqs_found_all_bank_r_reg[1]_1 (rank_done_r_i_1_n_0),\n .pi_dqs_found_any_bank(pi_dqs_found_any_bank),\n .pi_dqs_found_done_r1(pi_dqs_found_done_r1),\n .pi_dqs_found_done_r1_reg(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_10 ),\n .\\pi_dqs_found_lanes_r3_reg[3]_0 (\\pi_dqs_found_any_bank[0]_i_1_n_0 ),\n .pi_dqs_found_rank_done(pi_dqs_found_rank_done),\n .pi_dqs_found_start_reg(u_ddr_phy_init_n_502),\n .pi_dqs_found_start_reg_0(u_ddr_phy_init_n_501),\n .pi_f_inc_reg(ddr_phy_tempmon_0_n_6),\n .pi_fine_dly_dec_done(pi_fine_dly_dec_done),\n .\\pi_rst_stg1_cal_r_reg[0]_0 (\\pi_rst_stg1_cal_r_reg[0] ),\n .\\pi_rst_stg1_cal_r_reg[0]_1 (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_72 ),\n .\\po_counter_read_val_reg[8] (\\po_counter_read_val_reg[8]_1 ),\n .\\po_counter_read_val_reg[8]_0 (\\po_counter_read_val_reg[8]_2 ),\n .\\po_counter_read_val_reg[8]_1 (\\po_counter_read_val_reg[8]_6 ),\n .\\po_counter_read_val_reg[8]_10 (\\po_counter_read_val_reg[8]_23 ),\n .\\po_counter_read_val_reg[8]_11 (\\po_counter_read_val_reg[8]_25 ),\n .\\po_counter_read_val_reg[8]_12 (\\po_counter_read_val_reg[8]_26 ),\n .\\po_counter_read_val_reg[8]_2 (\\po_counter_read_val_reg[8]_7 ),\n .\\po_counter_read_val_reg[8]_3 (\\po_counter_read_val_reg[8]_9 ),\n .\\po_counter_read_val_reg[8]_4 (\\po_counter_read_val_reg[8]_10 ),\n .\\po_counter_read_val_reg[8]_5 (\\po_counter_read_val_reg[8]_16 ),\n .\\po_counter_read_val_reg[8]_6 (\\po_counter_read_val_reg[8]_17 ),\n .\\po_counter_read_val_reg[8]_7 (\\po_counter_read_val_reg[8]_19 ),\n .\\po_counter_read_val_reg[8]_8 (\\po_counter_read_val_reg[8]_20 ),\n .\\po_counter_read_val_reg[8]_9 (\\po_counter_read_val_reg[8]_22 ),\n .po_en_stg23(po_en_stg23),\n .po_en_stg2_f(cmd_po_en_stg2_f),\n .po_enstg2_f(po_enstg2_f),\n .po_stg23_incdec(po_stg23_incdec),\n .po_stg2_fincdec(po_stg2_fincdec),\n .prbs_last_byte_done_r(prbs_last_byte_done_r),\n .prbs_rdlvl_done_reg_rep(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_51 ),\n .prech_done(prech_done),\n .rank_done_r_reg_0(pi_dqs_found_all_bank_r),\n .\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 ({\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_69 ,\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_70 }),\n .\\rank_final_loop[0].final_do_max_reg[0][3]_0 (rd_data_offset_ranks_0),\n .\\rank_final_loop[0].final_do_max_reg[0][3]_1 (rd_data_offset_ranks_1),\n .\\rd_byte_data_offset_reg[0][9]_0 (p_0_in_0),\n .\\rd_byte_data_offset_reg[0]_3 (\\rd_byte_data_offset_reg[0]_3 ),\n .rd_data_offset_cal_done(rd_data_offset_cal_done),\n .rdlvl_stg1_done_int_reg(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_56 ),\n .rst_dqs_find(rst_dqs_find),\n .rst_dqs_find_r1_reg_0(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_9 ),\n .rst_dqs_find_reg_0(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_105 ),\n .rst_dqs_find_reg_1(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_107 ),\n .rstdiv0_sync_r1_reg_rep__12(rstdiv0_sync_r1_reg_rep__12),\n .rstdiv0_sync_r1_reg_rep__13(rstdiv0_sync_r1_reg_rep__13),\n .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),\n .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2),\n .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23),\n .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),\n .tempmon_sel_pi_incdec(tempmon_sel_pi_incdec),\n .wrcal_done_reg(u_ddr_phy_wrcal_n_82),\n .wrlvl_byte_redo(wrlvl_byte_redo),\n .wrlvl_done_r1(wrlvl_done_r1),\n .wrlvl_final_mux(wrlvl_final_mux));\n LUT4 #(\n .INIT(16'h2F20)) \n early1_data_i_1\n (.I0(u_ddr_phy_wrcal_n_67),\n .I1(u_ddr_phy_wrcal_n_110),\n .I2(u_ddr_phy_wrcal_n_119),\n .I3(u_ddr_phy_wrcal_n_73),\n .O(early1_data_i_1_n_0));\n LUT5 #(\n .INIT(32'h04FF0400)) \n early2_data_i_1\n (.I0(u_ddr_phy_wrcal_n_67),\n .I1(u_ddr_phy_wrcal_n_66),\n .I2(u_ddr_phy_wrcal_n_110),\n .I3(u_ddr_phy_wrcal_n_119),\n .I4(u_ddr_phy_wrcal_n_74),\n .O(early2_data_i_1_n_0));\n LUT5 #(\n .INIT(32'hFFFF0400)) \n final_dec_done_i_1\n (.I0(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ),\n .I1(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_108 ),\n .I2(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_75 ),\n .I3(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_13 ),\n .I4(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_14 ),\n .O(final_dec_done_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFF00100000)) \n fine_adjust_done_r_i_1\n (.I0(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_46 ),\n .I1(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_44 ),\n .I2(p_1_in27_in),\n .I3(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_43 ),\n .I4(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ),\n .I5(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_12 ),\n .O(fine_adjust_done_r_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFF00000100)) \n fine_adjust_i_1\n (.I0(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_46 ),\n .I1(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_43 ),\n .I2(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_44 ),\n .I3(init_dqsfound_done_r5),\n .I4(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ),\n .I5(\\pi_rst_stg1_cal_r_reg[0] ),\n .O(fine_adjust_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair711\" *) \n LUT5 #(\n .INIT(32'h0000F200)) \n \\fine_delay_r[11]_i_1 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[3]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26] [2]));\n (* SOFT_HLUTNM = \"soft_lutpair699\" *) \n LUT5 #(\n .INIT(32'h0000F200)) \n \\fine_delay_r[11]_i_1__0 \n (.I0(\\po_rdval_cnt_reg[8] [1]),\n .I1(\\po_rdval_cnt_reg[8] [0]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[3]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26]_0 [2]));\n (* SOFT_HLUTNM = \"soft_lutpair711\" *) \n LUT5 #(\n .INIT(32'h0000F800)) \n \\fine_delay_r[11]_i_1__1 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[3]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26]_1 [2]));\n (* SOFT_HLUTNM = \"soft_lutpair699\" *) \n LUT5 #(\n .INIT(32'h22220002)) \n \\fine_delay_r[11]_i_1__2 \n (.I0(fine_delay_mod[3]),\n .I1(calib_zero_inputs__0),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .I3(\\po_rdval_cnt_reg[8] [1]),\n .I4(calib_in_common),\n .O(D[3]));\n (* SOFT_HLUTNM = \"soft_lutpair710\" *) \n LUT5 #(\n .INIT(32'h0000F200)) \n \\fine_delay_r[14]_i_1 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[4]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26] [3]));\n (* SOFT_HLUTNM = \"soft_lutpair700\" *) \n LUT5 #(\n .INIT(32'h0000F200)) \n \\fine_delay_r[14]_i_1__0 \n (.I0(\\po_rdval_cnt_reg[8] [1]),\n .I1(\\po_rdval_cnt_reg[8] [0]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[4]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26]_0 [3]));\n (* SOFT_HLUTNM = \"soft_lutpair710\" *) \n LUT5 #(\n .INIT(32'h0000F800)) \n \\fine_delay_r[14]_i_1__1 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[4]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26]_1 [3]));\n (* SOFT_HLUTNM = \"soft_lutpair700\" *) \n LUT5 #(\n .INIT(32'h22220002)) \n \\fine_delay_r[14]_i_1__2 \n (.I0(fine_delay_mod[4]),\n .I1(calib_zero_inputs__0),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .I3(\\po_rdval_cnt_reg[8] [1]),\n .I4(calib_in_common),\n .O(D[4]));\n (* SOFT_HLUTNM = \"soft_lutpair702\" *) \n LUT5 #(\n .INIT(32'h0000F200)) \n \\fine_delay_r[17]_i_1 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[5]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26] [4]));\n (* SOFT_HLUTNM = \"soft_lutpair708\" *) \n LUT5 #(\n .INIT(32'h0000F200)) \n \\fine_delay_r[17]_i_1__0 \n (.I0(\\po_rdval_cnt_reg[8] [1]),\n .I1(\\po_rdval_cnt_reg[8] [0]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[5]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26]_0 [4]));\n (* SOFT_HLUTNM = \"soft_lutpair708\" *) \n LUT5 #(\n .INIT(32'h0000F800)) \n \\fine_delay_r[17]_i_1__1 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[5]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26]_1 [4]));\n (* SOFT_HLUTNM = \"soft_lutpair702\" *) \n LUT5 #(\n .INIT(32'h22220002)) \n \\fine_delay_r[17]_i_1__2 \n (.I0(fine_delay_mod[5]),\n .I1(calib_zero_inputs__0),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .I3(\\po_rdval_cnt_reg[8] [1]),\n .I4(calib_in_common),\n .O(D[5]));\n (* SOFT_HLUTNM = \"soft_lutpair701\" *) \n LUT5 #(\n .INIT(32'h0000F200)) \n \\fine_delay_r[20]_i_1 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[6]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26] [5]));\n (* SOFT_HLUTNM = \"soft_lutpair709\" *) \n LUT5 #(\n .INIT(32'h0000F200)) \n \\fine_delay_r[20]_i_1__0 \n (.I0(\\po_rdval_cnt_reg[8] [1]),\n .I1(\\po_rdval_cnt_reg[8] [0]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[6]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26]_0 [5]));\n (* SOFT_HLUTNM = \"soft_lutpair709\" *) \n LUT5 #(\n .INIT(32'h0000F800)) \n \\fine_delay_r[20]_i_1__1 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[6]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26]_1 [5]));\n (* SOFT_HLUTNM = \"soft_lutpair701\" *) \n LUT5 #(\n .INIT(32'h22220002)) \n \\fine_delay_r[20]_i_1__2 \n (.I0(fine_delay_mod[6]),\n .I1(calib_zero_inputs__0),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .I3(\\po_rdval_cnt_reg[8] [1]),\n .I4(calib_in_common),\n .O(D[6]));\n (* SOFT_HLUTNM = \"soft_lutpair703\" *) \n LUT5 #(\n .INIT(32'h0000F200)) \n \\fine_delay_r[23]_i_1 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[7]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26] [6]));\n (* SOFT_HLUTNM = \"soft_lutpair712\" *) \n LUT5 #(\n .INIT(32'h0000F200)) \n \\fine_delay_r[23]_i_1__0 \n (.I0(\\po_rdval_cnt_reg[8] [1]),\n .I1(\\po_rdval_cnt_reg[8] [0]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[7]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26]_0 [6]));\n (* SOFT_HLUTNM = \"soft_lutpair712\" *) \n LUT5 #(\n .INIT(32'h0000F800)) \n \\fine_delay_r[23]_i_1__1 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[7]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26]_1 [6]));\n (* SOFT_HLUTNM = \"soft_lutpair697\" *) \n LUT5 #(\n .INIT(32'h0000AB00)) \n \\fine_delay_r[23]_i_1__2 \n (.I0(calib_in_common),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .I3(fine_delay_sel_r),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[2] ));\n (* SOFT_HLUTNM = \"soft_lutpair703\" *) \n LUT5 #(\n .INIT(32'h22220002)) \n \\fine_delay_r[23]_i_2 \n (.I0(fine_delay_mod[7]),\n .I1(calib_zero_inputs__0),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .I3(\\po_rdval_cnt_reg[8] [1]),\n .I4(calib_in_common),\n .O(D[7]));\n (* SOFT_HLUTNM = \"soft_lutpair694\" *) \n LUT5 #(\n .INIT(32'h0000EA00)) \n \\fine_delay_r[26]_i_1 \n (.I0(calib_in_common),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .I3(fine_delay_sel_r),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[5] ));\n (* SOFT_HLUTNM = \"soft_lutpair697\" *) \n LUT5 #(\n .INIT(32'h0000BA00)) \n \\fine_delay_r[26]_i_1__0 \n (.I0(calib_in_common),\n .I1(\\po_rdval_cnt_reg[8] [0]),\n .I2(\\po_rdval_cnt_reg[8] [1]),\n .I3(fine_delay_sel_r),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[5]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair694\" *) \n LUT5 #(\n .INIT(32'h0000BA00)) \n \\fine_delay_r[26]_i_1__1 \n (.I0(calib_in_common),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .I3(fine_delay_sel_r),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[5]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair706\" *) \n LUT5 #(\n .INIT(32'h0000F200)) \n \\fine_delay_r[26]_i_2 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[8]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26] [7]));\n (* SOFT_HLUTNM = \"soft_lutpair706\" *) \n LUT5 #(\n .INIT(32'h0000F200)) \n \\fine_delay_r[26]_i_2__0 \n (.I0(\\po_rdval_cnt_reg[8] [1]),\n .I1(\\po_rdval_cnt_reg[8] [0]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[8]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26]_0 [7]));\n (* SOFT_HLUTNM = \"soft_lutpair714\" *) \n LUT5 #(\n .INIT(32'h0000F800)) \n \\fine_delay_r[26]_i_2__1 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[8]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26]_1 [7]));\n (* SOFT_HLUTNM = \"soft_lutpair705\" *) \n LUT5 #(\n .INIT(32'h44440004)) \n \\fine_delay_r[2]_i_1 \n (.I0(calib_zero_inputs__0),\n .I1(fine_delay_mod[0]),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .I3(\\po_rdval_cnt_reg[8] [1]),\n .I4(calib_in_common),\n .O(D[0]));\n (* SOFT_HLUTNM = \"soft_lutpair704\" *) \n LUT5 #(\n .INIT(32'h0000F200)) \n \\fine_delay_r[5]_i_1 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[1]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26] [0]));\n (* SOFT_HLUTNM = \"soft_lutpair713\" *) \n LUT5 #(\n .INIT(32'h0000F200)) \n \\fine_delay_r[5]_i_1__0 \n (.I0(\\po_rdval_cnt_reg[8] [1]),\n .I1(\\po_rdval_cnt_reg[8] [0]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[1]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26]_0 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair713\" *) \n LUT5 #(\n .INIT(32'h0000F800)) \n \\fine_delay_r[5]_i_1__1 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[1]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26]_1 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair704\" *) \n LUT5 #(\n .INIT(32'h22220002)) \n \\fine_delay_r[5]_i_1__2 \n (.I0(fine_delay_mod[1]),\n .I1(calib_zero_inputs__0),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .I3(\\po_rdval_cnt_reg[8] [1]),\n .I4(calib_in_common),\n .O(D[1]));\n (* SOFT_HLUTNM = \"soft_lutpair707\" *) \n LUT5 #(\n .INIT(32'h0000F200)) \n \\fine_delay_r[8]_i_1 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[2]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26] [1]));\n (* SOFT_HLUTNM = \"soft_lutpair707\" *) \n LUT5 #(\n .INIT(32'h0000F200)) \n \\fine_delay_r[8]_i_1__0 \n (.I0(\\po_rdval_cnt_reg[8] [1]),\n .I1(\\po_rdval_cnt_reg[8] [0]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[2]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26]_0 [1]));\n (* SOFT_HLUTNM = \"soft_lutpair698\" *) \n LUT5 #(\n .INIT(32'h0000F800)) \n \\fine_delay_r[8]_i_1__1 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[2]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26]_1 [1]));\n (* SOFT_HLUTNM = \"soft_lutpair698\" *) \n LUT5 #(\n .INIT(32'h22220002)) \n \\fine_delay_r[8]_i_1__2 \n (.I0(fine_delay_mod[2]),\n .I1(calib_zero_inputs__0),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .I3(\\po_rdval_cnt_reg[8] [1]),\n .I4(calib_in_common),\n .O(D[2]));\n LUT6 #(\n .INIT(64'hFFFFDFDD00000008)) \n fine_delay_sel_i_1\n (.I0(prbs_state_r[0]),\n .I1(prbs_state_r[4]),\n .I2(prbs_state_r[3]),\n .I3(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_102 ),\n .I4(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_104 ),\n .I5(fine_delay_sel_r_reg),\n .O(fine_delay_sel_i_1_n_0));\n LUT6 #(\n .INIT(64'h8FFFFFFF80000000)) \n fine_dly_error_i_1\n (.I0(dec_cnt_reg[0]),\n .I1(dec_cnt_reg[5]),\n .I2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_108 ),\n .I3(prbs_state_r[1]),\n .I4(prbs_state_r[0]),\n .I5(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_44 ),\n .O(fine_dly_error_i_1_n_0));\n LUT6 #(\n .INIT(64'h00000000FFFFAAA8)) \n flag_ck_negedge_i_1\n (.I0(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_7 ),\n .I1(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_40 ),\n .I2(stable_cnt1),\n .I3(stable_cnt227_in),\n .I4(flag_ck_negedge09_out),\n .I5(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_47 ),\n .O(flag_ck_negedge_i_1_n_0));\n LUT6 #(\n .INIT(64'h3F3FFBFF00000800)) \n found_first_edge_r_i_1\n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_4 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_91 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_84 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_139 ),\n .I4(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_85 ),\n .I5(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_47 ),\n .O(found_first_edge_r_i_1_n_0));\n LUT5 #(\n .INIT(32'h08FF0800)) \n found_second_edge_r_i_1\n (.I0(found_stable_eye_last_r),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_47 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_84 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_161 ),\n .I4(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_60 ),\n .O(found_second_edge_r_i_1_n_0));\n LUT3 #(\n .INIT(8'hB8)) \n found_stable_eye_last_r_i_1\n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_3 ),\n .I1(detect_edge_done_r),\n .I2(found_stable_eye_last_r),\n .O(found_stable_eye_last_r_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_byte_sel_div1.byte_sel_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_48 ),\n .Q(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_byte_sel_div1.byte_sel_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_49 ),\n .Q(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_byte_sel_div1.byte_sel_cnt_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_50 ),\n .Q(byte_sel_cnt),\n .R(1'b0));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\gen_byte_sel_div1.calib_in_common_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_27 ),\n .Q(calib_in_common),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE #(\n .INIT(1'b0)) \n \\gen_byte_sel_div1.ctl_lane_sel_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_94 ),\n .Q(\\gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE #(\n .INIT(1'b0)) \n \\gen_byte_sel_div1.ctl_lane_sel_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_96 ),\n .Q(\\gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE #(\n .INIT(1'b0)) \n \\gen_byte_sel_div1.ctl_lane_sel_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_97 ),\n .Q(\\gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[2] ),\n .R(rstdiv0_sync_r1_reg_rep__9));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 ),\n .O(\\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 ),\n .O(\\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 ),\n .O(\\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 ),\n .O(\\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 ),\n .O(\\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 ),\n .O(\\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 ),\n .O(\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 ),\n .O(\\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 ),\n .O(\\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 ),\n .O(\\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 ),\n .O(\\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 ),\n .O(\\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 ),\n .O(\\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 ),\n .O(\\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 ),\n .O(\\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 ),\n .O(\\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 ),\n .O(\\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 ),\n .O(\\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 ),\n .O(\\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 ),\n .O(\\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 ),\n .O(\\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 ),\n .O(\\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 ),\n .O(\\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 ),\n .O(\\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 ),\n .O(\\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 ),\n .O(\\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 ),\n .O(\\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 ),\n .O(\\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_208 ),\n .O(\\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 ),\n .O(\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 ),\n .O(\\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 ),\n .O(\\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 ),\n .O(\\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 ),\n .O(\\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 ),\n .O(\\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 ),\n .O(\\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 ),\n .O(\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 ),\n .O(\\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 ),\n .O(\\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 ),\n .O(\\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 ),\n .O(\\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 ),\n .O(\\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 ),\n .O(\\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 ),\n .O(\\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 ),\n .O(\\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 ),\n .O(\\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 ),\n .O(\\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 ),\n .O(\\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 ),\n .O(\\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 ),\n .O(\\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 ),\n .O(\\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 ),\n .O(\\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 ),\n .O(\\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 ),\n .O(\\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 ),\n .O(\\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 ),\n .O(\\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 ),\n .O(\\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 ),\n .O(\\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_212 ),\n .O(\\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 ),\n .O(\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h5554)) \n \\gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_9 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ),\n .I3(pb_detect_edge_done_r[0]),\n .O(\\gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h5050505051515051)) \n \\gen_track_left_edge[0].pb_found_edge_r[0]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_108 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_39 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ),\n .I4(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_107 ),\n .I5(pb_detect_edge_done_r[0]),\n .O(\\gen_track_left_edge[0].pb_found_edge_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFEFE01000000)) \n \\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_108 ),\n .I1(pb_detect_edge_done_r[0]),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_124 ),\n .I4(pb_found_stable_eye_r76_out),\n .I5(\\gen_track_left_edge[0].pb_found_stable_eye_r_reg ),\n .O(\\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h5554)) \n \\gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ),\n .I2(p_0_in102_in),\n .I3(pb_detect_edge_done_r[1]),\n .O(\\gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h5050505051515051)) \n \\gen_track_left_edge[1].pb_found_edge_r[1]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_110 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_40 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ),\n .I4(p_0_in16_in),\n .I5(pb_detect_edge_done_r[1]),\n .O(\\gen_track_left_edge[1].pb_found_edge_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFEFE01000000)) \n \\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_110 ),\n .I1(pb_detect_edge_done_r[1]),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_126 ),\n .I4(pb_found_stable_eye_r72_out),\n .I5(\\gen_track_left_edge[1].pb_found_stable_eye_r_reg ),\n .O(\\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h5554)) \n \\gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ),\n .I2(p_0_in99_in),\n .I3(pb_detect_edge_done_r[2]),\n .O(\\gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h5050505051515051)) \n \\gen_track_left_edge[2].pb_found_edge_r[2]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_112 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_41 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ),\n .I4(p_0_in13_in),\n .I5(pb_detect_edge_done_r[2]),\n .O(\\gen_track_left_edge[2].pb_found_edge_r[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFEFE01000000)) \n \\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_112 ),\n .I1(pb_detect_edge_done_r[2]),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_128 ),\n .I4(pb_found_stable_eye_r68_out),\n .I5(\\gen_track_left_edge[2].pb_found_stable_eye_r_reg ),\n .O(\\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h5554)) \n \\gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ),\n .I2(p_0_in96_in),\n .I3(pb_detect_edge_done_r[3]),\n .O(\\gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h5050505051515051)) \n \\gen_track_left_edge[3].pb_found_edge_r[3]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_114 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_42 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ),\n .I4(p_0_in10_in),\n .I5(pb_detect_edge_done_r[3]),\n .O(\\gen_track_left_edge[3].pb_found_edge_r[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFEFE01000000)) \n \\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_114 ),\n .I1(pb_detect_edge_done_r[3]),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_130 ),\n .I4(pb_found_stable_eye_r64_out),\n .I5(\\gen_track_left_edge[3].pb_found_stable_eye_r_reg ),\n .O(\\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h5554)) \n \\gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ),\n .I2(p_0_in93_in),\n .I3(pb_detect_edge_done_r[4]),\n .O(\\gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h5050505051515051)) \n \\gen_track_left_edge[4].pb_found_edge_r[4]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_116 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_43 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ),\n .I4(p_0_in7_in),\n .I5(pb_detect_edge_done_r[4]),\n .O(\\gen_track_left_edge[4].pb_found_edge_r[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFEFE01000000)) \n \\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_116 ),\n .I1(pb_detect_edge_done_r[4]),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_132 ),\n .I4(pb_found_stable_eye_r60_out),\n .I5(\\gen_track_left_edge[4].pb_found_stable_eye_r_reg ),\n .O(\\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h5554)) \n \\gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ),\n .I2(p_0_in90_in),\n .I3(pb_detect_edge_done_r[5]),\n .O(\\gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h5050505051515051)) \n \\gen_track_left_edge[5].pb_found_edge_r[5]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_118 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_44 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ),\n .I4(p_0_in4_in),\n .I5(pb_detect_edge_done_r[5]),\n .O(\\gen_track_left_edge[5].pb_found_edge_r[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFEFE01000000)) \n \\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_118 ),\n .I1(pb_detect_edge_done_r[5]),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_134 ),\n .I4(pb_found_stable_eye_r56_out),\n .I5(\\gen_track_left_edge[5].pb_found_stable_eye_r_reg ),\n .O(\\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h5554)) \n \\gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ),\n .I2(p_0_in87_in),\n .I3(pb_detect_edge_done_r[6]),\n .O(\\gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h5050505051515051)) \n \\gen_track_left_edge[6].pb_found_edge_r[6]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_120 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_45 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ),\n .I4(p_0_in1_in),\n .I5(pb_detect_edge_done_r[6]),\n .O(\\gen_track_left_edge[6].pb_found_edge_r[6]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFEFE01000000)) \n \\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_120 ),\n .I1(pb_detect_edge_done_r[6]),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_136 ),\n .I4(pb_found_stable_eye_r52_out),\n .I5(\\gen_track_left_edge[6].pb_found_stable_eye_r_reg ),\n .O(\\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h5554)) \n \\gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_2 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ),\n .I2(p_0_in84_in),\n .I3(pb_detect_edge_done_r[7]),\n .O(\\gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h5050505051515051)) \n \\gen_track_left_edge[7].pb_found_edge_r[7]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_122 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_46 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ),\n .I4(p_0_in),\n .I5(pb_detect_edge_done_r[7]),\n .O(\\gen_track_left_edge[7].pb_found_edge_r[7]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFEFE01000000)) \n \\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_122 ),\n .I1(pb_detect_edge_done_r[7]),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_138 ),\n .I4(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_137 ),\n .I5(\\gen_track_left_edge[7].pb_found_stable_eye_r_reg ),\n .O(\\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hCF88)) \n \\genblk8[0].left_edge_found_pb[0]_i_1 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_69 ),\n .I1(p_154_out),\n .I2(right_gain_pb),\n .I3(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_15 ),\n .O(\\genblk8[0].left_edge_found_pb[0]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hCF88)) \n \\genblk8[0].left_edge_updated[0]_i_1 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_69 ),\n .I1(p_154_out),\n .I2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ),\n .I3(left_edge_updated[0]),\n .O(\\genblk8[0].left_edge_updated[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hCCFE0000CCFECCCC)) \n \\genblk8[0].right_edge_found_pb[0]_i_1 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ),\n .I1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_23 ),\n .I2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_68 ),\n .I3(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_69 ),\n .I4(p_154_out),\n .I5(right_gain_pb),\n .O(\\genblk8[0].right_edge_found_pb[0]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hCF88)) \n \\genblk8[1].left_edge_found_pb[1]_i_1 \n (.I0(p_146_out),\n .I1(p_154_out),\n .I2(right_gain_pb),\n .I3(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_16 ),\n .O(\\genblk8[1].left_edge_found_pb[1]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hCF88)) \n \\genblk8[1].left_edge_updated[1]_i_1 \n (.I0(p_146_out),\n .I1(p_154_out),\n .I2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ),\n .I3(left_edge_updated[1]),\n .O(\\genblk8[1].left_edge_updated[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hCCFE0000CCFECCCC)) \n \\genblk8[1].right_edge_found_pb[1]_i_1 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ),\n .I1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_24 ),\n .I2(p_143_out),\n .I3(p_146_out),\n .I4(p_154_out),\n .I5(right_gain_pb),\n .O(\\genblk8[1].right_edge_found_pb[1]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hCF88)) \n \\genblk8[2].left_edge_found_pb[2]_i_1 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_65 ),\n .I1(p_154_out),\n .I2(right_gain_pb),\n .I3(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_17 ),\n .O(\\genblk8[2].left_edge_found_pb[2]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hCF88)) \n \\genblk8[2].left_edge_updated[2]_i_1 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_65 ),\n .I1(p_154_out),\n .I2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ),\n .I3(left_edge_updated[2]),\n .O(\\genblk8[2].left_edge_updated[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hCCFE0000CCFECCCC)) \n \\genblk8[2].right_edge_found_pb[2]_i_1 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ),\n .I1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_25 ),\n .I2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_64 ),\n .I3(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_65 ),\n .I4(p_154_out),\n .I5(right_gain_pb),\n .O(\\genblk8[2].right_edge_found_pb[2]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hCF88)) \n \\genblk8[3].left_edge_found_pb[3]_i_1 \n (.I0(p_130_out),\n .I1(p_154_out),\n .I2(right_gain_pb),\n .I3(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_18 ),\n .O(\\genblk8[3].left_edge_found_pb[3]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hCF88)) \n \\genblk8[3].left_edge_updated[3]_i_1 \n (.I0(p_130_out),\n .I1(p_154_out),\n .I2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ),\n .I3(left_edge_updated[3]),\n .O(\\genblk8[3].left_edge_updated[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hCCFE0000CCFECCCC)) \n \\genblk8[3].right_edge_found_pb[3]_i_1 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ),\n .I1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_26 ),\n .I2(p_127_out),\n .I3(p_130_out),\n .I4(p_154_out),\n .I5(right_gain_pb),\n .O(\\genblk8[3].right_edge_found_pb[3]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hCF88)) \n \\genblk8[4].left_edge_found_pb[4]_i_1 \n (.I0(p_122_out),\n .I1(p_154_out),\n .I2(right_gain_pb),\n .I3(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_19 ),\n .O(\\genblk8[4].left_edge_found_pb[4]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hCF88)) \n \\genblk8[4].left_edge_updated[4]_i_1 \n (.I0(p_122_out),\n .I1(p_154_out),\n .I2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ),\n .I3(left_edge_updated[4]),\n .O(\\genblk8[4].left_edge_updated[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hCCFE0000CCFECCCC)) \n \\genblk8[4].right_edge_found_pb[4]_i_1 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ),\n .I1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_27 ),\n .I2(p_119_out),\n .I3(p_122_out),\n .I4(p_154_out),\n .I5(right_gain_pb),\n .O(\\genblk8[4].right_edge_found_pb[4]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hCF88)) \n \\genblk8[5].left_edge_found_pb[5]_i_1 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_59 ),\n .I1(p_154_out),\n .I2(right_gain_pb),\n .I3(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_20 ),\n .O(\\genblk8[5].left_edge_found_pb[5]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hCF88)) \n \\genblk8[5].left_edge_updated[5]_i_1 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_59 ),\n .I1(p_154_out),\n .I2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ),\n .I3(left_edge_updated[5]),\n .O(\\genblk8[5].left_edge_updated[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hCCFE0000CCFECCCC)) \n \\genblk8[5].right_edge_found_pb[5]_i_1 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ),\n .I1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_28 ),\n .I2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_58 ),\n .I3(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_59 ),\n .I4(p_154_out),\n .I5(right_gain_pb),\n .O(\\genblk8[5].right_edge_found_pb[5]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hCF88)) \n \\genblk8[6].left_edge_found_pb[6]_i_1 \n (.I0(p_106_out),\n .I1(p_154_out),\n .I2(right_gain_pb),\n .I3(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_21 ),\n .O(\\genblk8[6].left_edge_found_pb[6]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hCF88)) \n \\genblk8[6].left_edge_updated[6]_i_1 \n (.I0(p_106_out),\n .I1(p_154_out),\n .I2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ),\n .I3(left_edge_updated[6]),\n .O(\\genblk8[6].left_edge_updated[6]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hCCFE0000CCFECCCC)) \n \\genblk8[6].right_edge_found_pb[6]_i_1 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ),\n .I1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_29 ),\n .I2(p_103_out),\n .I3(p_106_out),\n .I4(p_154_out),\n .I5(right_gain_pb),\n .O(\\genblk8[6].right_edge_found_pb[6]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hCF88)) \n \\genblk8[7].left_edge_found_pb[7]_i_1 \n (.I0(p_98_out),\n .I1(p_154_out),\n .I2(right_gain_pb),\n .I3(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_22 ),\n .O(\\genblk8[7].left_edge_found_pb[7]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hCF88)) \n \\genblk8[7].left_edge_updated[7]_i_1 \n (.I0(p_98_out),\n .I1(p_154_out),\n .I2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ),\n .I3(left_edge_updated[7]),\n .O(\\genblk8[7].left_edge_updated[7]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hCCFE0000CCFECCCC)) \n \\genblk8[7].right_edge_found_pb[7]_i_1 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ),\n .I1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_30 ),\n .I2(p_95_out),\n .I3(p_98_out),\n .I4(p_154_out),\n .I5(right_gain_pb),\n .O(\\genblk8[7].right_edge_found_pb[7]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h4)) \n \\genblk9[0].fine_delay_incdec_pb[0]_i_7 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_78 ),\n .I1(bit_cnt),\n .O(\\genblk9[0].fine_delay_incdec_pb[0]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hFFDF77DF00000000)) \n idel_adj_inc_i_1\n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_88 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_85 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_140 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_86 ),\n .I4(cal1_wait_r),\n .I5(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_52 ),\n .O(idel_adj_inc_i_1_n_0));\n LUT6 #(\n .INIT(64'hF0F0B1F0F0B0F0F0)) \n idel_pat_detect_valid_r_i_1\n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_186 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_83 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_50 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_86 ),\n .I4(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_85 ),\n .I5(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_87 ),\n .O(idel_pat_detect_valid_r_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n idelay_ce_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(idelay_ce_int),\n .Q(idelay_ce_r1),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE #(\n .INIT(1'b0)) \n idelay_ce_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(idelay_ce_r1),\n .Q(idelay_ce),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE #(\n .INIT(1'b0)) \n idelay_inc_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(idelay_inc_int),\n .Q(idelay_inc_r1),\n .R(rstdiv0_sync_r1_reg_rep__9));\n (* syn_maxfan = \"30\" *) \n FDRE #(\n .INIT(1'b0)) \n idelay_inc_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(idelay_inc_r1),\n .Q(idelay_inc),\n .R(rstdiv0_sync_r1_reg_rep__9));\n LUT6 #(\n .INIT(64'hFFFFFCFF00000080)) \n idelay_ld_done_i_1\n (.I0(u_ddr_phy_wrcal_n_113),\n .I1(u_ddr_phy_wrcal_n_111),\n .I2(u_ddr_phy_wrcal_n_109),\n .I3(u_ddr_phy_wrcal_n_110),\n .I4(u_ddr_phy_wrcal_n_108),\n .I5(u_ddr_phy_wrcal_n_69),\n .O(idelay_ld_done_i_1_n_0));\n LUT4 #(\n .INIT(16'h2F20)) \n idelay_ld_i_1\n (.I0(u_ddr_phy_wrcal_n_4),\n .I1(u_ddr_phy_wrcal_n_109),\n .I2(u_ddr_phy_wrcal_n_116),\n .I3(idelay_ld),\n .O(idelay_ld_i_1_n_0));\n LUT3 #(\n .INIT(8'hB8)) \n inhibit_edge_detect_r_i_1\n (.I0(inhibit_edge_detect_r),\n .I1(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_58 ),\n .I2(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_10 ),\n .O(inhibit_edge_detect_r_i_1_n_0));\n (* ORIG_CELL_NAME = \"init_calib_complete_reg\" *) \n FDRE #(\n .INIT(1'b0)) \n init_calib_complete_reg\n (.C(CLK),\n .CE(1'b1),\n .D(calib_complete),\n .Q(phy_dout[33]),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* ORIG_CELL_NAME = \"init_calib_complete_reg\" *) \n FDRE #(\n .INIT(1'b0)) \n init_calib_complete_reg_rep\n (.C(CLK),\n .CE(1'b1),\n .D(calib_complete),\n .Q(\\my_empty_reg[7] ),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* ORIG_CELL_NAME = \"init_calib_complete_reg\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n init_calib_complete_reg_rep__0\n (.C(CLK),\n .CE(1'b1),\n .D(calib_complete),\n .Q(init_calib_complete_reg_rep__0_n_0),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* ORIG_CELL_NAME = \"init_calib_complete_reg\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n init_calib_complete_reg_rep__1\n (.C(CLK),\n .CE(1'b1),\n .D(calib_complete),\n .Q(init_calib_complete_reg_rep__1_n_0),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* ORIG_CELL_NAME = \"init_calib_complete_reg\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n init_calib_complete_reg_rep__10\n (.C(CLK),\n .CE(1'b1),\n .D(calib_complete),\n .Q(init_calib_complete_reg_rep__10_n_0),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* ORIG_CELL_NAME = \"init_calib_complete_reg\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n init_calib_complete_reg_rep__11\n (.C(CLK),\n .CE(1'b1),\n .D(calib_complete),\n .Q(init_calib_complete_reg_rep__11_n_0),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* ORIG_CELL_NAME = \"init_calib_complete_reg\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n init_calib_complete_reg_rep__12\n (.C(CLK),\n .CE(1'b1),\n .D(calib_complete),\n .Q(init_calib_complete_reg_rep__12_n_0),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* ORIG_CELL_NAME = \"init_calib_complete_reg\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n init_calib_complete_reg_rep__13\n (.C(CLK),\n .CE(1'b1),\n .D(calib_complete),\n .Q(init_calib_complete_reg_rep__13_n_0),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* ORIG_CELL_NAME = \"init_calib_complete_reg\" *) \n FDRE #(\n .INIT(1'b0)) \n init_calib_complete_reg_rep__14\n (.C(CLK),\n .CE(1'b1),\n .D(calib_complete),\n .Q(init_calib_complete_r_reg),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* ORIG_CELL_NAME = \"init_calib_complete_reg\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n init_calib_complete_reg_rep__2\n (.C(CLK),\n .CE(1'b1),\n .D(calib_complete),\n .Q(init_calib_complete_reg_rep__2_n_0),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* ORIG_CELL_NAME = \"init_calib_complete_reg\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n init_calib_complete_reg_rep__3\n (.C(CLK),\n .CE(1'b1),\n .D(calib_complete),\n .Q(init_calib_complete_reg_rep__3_n_0),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* ORIG_CELL_NAME = \"init_calib_complete_reg\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n init_calib_complete_reg_rep__4\n (.C(CLK),\n .CE(1'b1),\n .D(calib_complete),\n .Q(init_calib_complete_reg_rep__4_n_0),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* ORIG_CELL_NAME = \"init_calib_complete_reg\" *) \n FDRE #(\n .INIT(1'b0)) \n init_calib_complete_reg_rep__5\n (.C(CLK),\n .CE(1'b1),\n .D(calib_complete),\n .Q(\\rd_ptr_timing_reg[0] ),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* ORIG_CELL_NAME = \"init_calib_complete_reg\" *) \n FDRE #(\n .INIT(1'b0)) \n init_calib_complete_reg_rep__6\n (.C(CLK),\n .CE(1'b1),\n .D(calib_complete),\n .Q(app_zq_r_reg),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* ORIG_CELL_NAME = \"init_calib_complete_reg\" *) \n FDRE #(\n .INIT(1'b0)) \n init_calib_complete_reg_rep__7\n (.C(CLK),\n .CE(1'b1),\n .D(calib_complete),\n .Q(\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* ORIG_CELL_NAME = \"init_calib_complete_reg\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n init_calib_complete_reg_rep__8\n (.C(CLK),\n .CE(1'b1),\n .D(calib_complete),\n .Q(init_calib_complete_reg_rep__8_n_0),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* ORIG_CELL_NAME = \"init_calib_complete_reg\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n init_calib_complete_reg_rep__9\n (.C(CLK),\n .CE(1'b1),\n .D(calib_complete),\n .Q(init_calib_complete_reg_rep__9_n_0),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hFFFF0004)) \n init_complete_r_i_1\n (.I0(init_state_r),\n .I1(u_ddr_phy_init_n_105),\n .I2(u_ddr_phy_init_n_104),\n .I3(u_ddr_phy_init_n_470),\n .I4(u_ddr_phy_init_n_18),\n .O(init_complete_r_i_1_n_0));\n LUT5 #(\n .INIT(32'hFFFF0004)) \n init_complete_r_timing_i_1\n (.I0(init_state_r),\n .I1(u_ddr_phy_init_n_105),\n .I2(u_ddr_phy_init_n_104),\n .I3(u_ddr_phy_init_n_470),\n .I4(init_complete_r_timing_orig),\n .O(init_complete_r_timing_i_1_n_0));\n LUT6 #(\n .INIT(64'hAAAAAAAAAABAAAAA)) \n init_dec_done_i_1\n (.I0(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_13 ),\n .I1(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_41 ),\n .I2(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_76 ),\n .I3(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_42 ),\n .I4(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_108 ),\n .I5(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ),\n .O(init_dec_done_i_1_n_0));\n LUT6 #(\n .INIT(64'h00000000000000E2)) \n init_dqsfound_done_r_i_1\n (.I0(rd_data_offset_cal_done),\n .I1(p_1_in27_in),\n .I2(\\rd_byte_data_offset_reg[0]_3 ),\n .I3(rstdiv0_sync_r1_reg_rep__23),\n .I4(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_72 ),\n .I5(p_1_in50_in),\n .O(init_dqsfound_done_r_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair696\" *) \n LUT5 #(\n .INIT(32'h0000AB00)) \n \\input_[0].iserdes_dq_.idelay_finedelay_dq.idelaye2_i_1 \n (.I0(calib_in_common),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .I3(idelay_ce),\n .I4(calib_zero_inputs__0),\n .O(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ));\n (* SOFT_HLUTNM = \"soft_lutpair695\" *) \n LUT5 #(\n .INIT(32'h0000EA00)) \n \\input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_i_1 \n (.I0(calib_in_common),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .I3(idelay_ce),\n .I4(calib_zero_inputs__0),\n .O(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ));\n (* SOFT_HLUTNM = \"soft_lutpair695\" *) \n LUT5 #(\n .INIT(32'h0000BA00)) \n \\input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_i_1__0 \n (.I0(calib_in_common),\n .I1(\\po_rdval_cnt_reg[8] [0]),\n .I2(\\po_rdval_cnt_reg[8] [1]),\n .I3(idelay_ce),\n .I4(calib_zero_inputs__0),\n .O(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair696\" *) \n LUT5 #(\n .INIT(32'h0000BA00)) \n \\input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_i_1__1 \n (.I0(calib_in_common),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .I3(idelay_ce),\n .I4(calib_zero_inputs__0),\n .O(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ));\n ddr3_ifmig_7series_v4_0_ddr_phy_ck_addr_cmd_delay \\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay \n (.CLK(CLK),\n .D_po_coarse_enable110_out(D_po_coarse_enable110_out),\n .Q(\\po_rdval_cnt_reg[8] [1:0]),\n .calib_in_common(calib_in_common),\n .\\calib_zero_inputs_reg[1] ({calib_zero_inputs,calib_zero_inputs__0}),\n .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done),\n .cmd_delay_start0(cmd_delay_start0),\n .cnt_pwron_cke_done_r(cnt_pwron_cke_done_r),\n .ctl_lane_cnt(ctl_lane_cnt),\n .delay_dec_done_reg_0(\\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_12 ),\n .delay_dec_done_reg_1(\\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_13 ),\n .dqs_po_dec_done(dqs_po_dec_done),\n .dqs_wl_po_stg2_c_incdec(dqs_wl_po_stg2_c_incdec),\n .\\init_state_r_reg[0] (\\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_11 ),\n .\\mcGo_r_reg[15] (\\mcGo_r_reg[15] ),\n .p_1_in(p_1_in),\n .pi_fine_dly_dec_done(pi_fine_dly_dec_done),\n .po_cnt_inc_reg_0(\\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_17 ),\n .\\po_counter_read_val_reg[8] (\\po_counter_read_val_reg[8]_0 ),\n .\\po_counter_read_val_reg[8]_0 (\\po_counter_read_val_reg[8]_4 ),\n .\\po_counter_read_val_reg[8]_1 (\\po_counter_read_val_reg[8]_5 ),\n .\\po_counter_read_val_reg[8]_2 (\\po_counter_read_val_reg[8]_18 ),\n .\\po_counter_read_val_reg[8]_3 (\\po_counter_read_val_reg[8]_21 ),\n .\\po_counter_read_val_reg[8]_4 (\\po_counter_read_val_reg[8]_24 ),\n .\\po_counter_read_val_reg[8]_5 (\\po_counter_read_val_reg[8]_27 ),\n .po_en_stg2_f(cmd_po_en_stg2_f),\n .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23),\n .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),\n .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9),\n .\\wait_cnt_r_reg[0]_0 (wait_cnt_r_reg__0_1),\n .\\wait_cnt_r_reg[0]_1 (po_cnt_inc_i_1_n_0),\n .\\wait_cnt_r_reg[0]_2 (po_cnt_dec_i_1_n_0));\n ddr3_ifmig_7series_v4_0_ddr_phy_wrlvl \\mb_wrlvl_inst.u_ddr_phy_wrlvl \n (.CLK(CLK),\n .D({\\u_ocd_po_cntlr/stg2_target_ns ,wl_po_fine_cnt_sel_0}),\n .\\FSM_sequential_wl_state_r_reg[0]_0 (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_8 ),\n .\\FSM_sequential_wl_state_r_reg[0]_1 (wr_level_done_r_i_1_n_0),\n .\\FSM_sequential_wl_state_r_reg[1]_0 (dq_cnt_inc_i_1_n_0),\n .\\FSM_sequential_wl_state_r_reg[2]_0 (wl_edge_detect_valid_r_i_1_n_0),\n .\\FSM_sequential_wl_state_r_reg[2]_1 (wrlvl_rank_done_r_i_1_n_0),\n .O({\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_0 ,\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_1 ,\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_2 ,\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_3 }),\n .Q(\\u_ocd_lim/stg3_init_val ),\n .S(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_59 ),\n .SR({rstdiv0_sync_r1_reg_rep__16,rstdiv0_sync_r1_reg_rep__14[0]}),\n .\\byte_r_reg[0] (\\byte_r_reg[0] ),\n .\\byte_r_reg[1] (\\byte_r_reg[1] ),\n .byte_sel_cnt(byte_sel_cnt),\n .\\calib_sel_reg[3] (\\po_rdval_cnt_reg[8] [2]),\n .delay_done_r4_reg(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_102 ),\n .done_dqs_dec239_out(done_dqs_dec239_out),\n .done_dqs_tap_inc(done_dqs_tap_inc),\n .dq_cnt_inc_reg_0(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_56 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ),\n .dqs_po_dec_done(dqs_po_dec_done),\n .dqs_po_en_stg2_f(dqs_po_en_stg2_f),\n .dqs_po_en_stg2_f_reg_0(dqs_po_en_stg2_f_reg),\n .dqs_po_stg2_f_incdec(dqs_po_stg2_f_incdec),\n .dqs_wl_po_stg2_c_incdec(dqs_wl_po_stg2_c_incdec),\n .early1_data_reg(u_ddr_phy_wrcal_n_101),\n .early1_data_reg_0(u_ddr_phy_wrcal_n_73),\n .flag_ck_negedge09_out(flag_ck_negedge09_out),\n .flag_ck_negedge_reg_0(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_47 ),\n .flag_ck_negedge_reg_1(flag_ck_negedge_i_1_n_0),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[0] (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_48 ),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 (\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[1] (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_49 ),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 (\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[2] (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_50 ),\n .inhibit_edge_detect_r(inhibit_edge_detect_r),\n .inhibit_edge_detect_r_reg_0(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_58 ),\n .inhibit_edge_detect_r_reg_1(inhibit_edge_detect_r_i_1_n_0),\n .\\lim_state_reg[12] (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_36 ),\n .\\mcGo_r_reg[15] (\\mcGo_r_reg[15] ),\n .my_empty(my_empty),\n .my_empty_6(my_empty_6),\n .my_empty_7(my_empty_7),\n .my_empty_8(my_empty_8),\n .oclkdelay_calib_done_r_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ),\n .oclkdelay_calib_done_r_reg_0(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_56 ),\n .oclkdelay_calib_done_r_reg_1(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_57 ),\n .out({\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_27 ,\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_28 ,\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_29 ,\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_30 ,\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_31 }),\n .p_0_in(p_0_in_2),\n .p_1_in(p_1_in),\n .pi_f_inc_reg(ddr_phy_tempmon_0_n_2),\n .pi_fine_dly_dec_done(pi_fine_dly_dec_done),\n .po_cnt_dec_reg_0(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_46 ),\n .po_cnt_dec_reg_1(po_cnt_dec_reg),\n .\\po_counter_read_val_reg[5] ({\\po_counter_read_val_reg[5] [5:4],\\po_counter_read_val_reg[5] [2:1]}),\n .\\po_counter_read_val_reg[8] (\\po_counter_read_val_reg[8]_30 ),\n .\\po_counter_read_val_reg[8]_0 (\\po_counter_read_val_reg[8]_31 ),\n .\\po_rdval_cnt_reg[0]_0 (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_38 ),\n .\\po_stg2_wrcal_cnt_reg[0] (u_ddr_phy_wrcal_n_100),\n .\\po_stg2_wrcal_cnt_reg[1] (u_ddr_phy_wrcal_n_98),\n .\\po_stg2_wrcal_cnt_reg[2] ({po_stg2_wrcal_cnt,\\idelay_tap_cnt_r_reg[0][3][0] }),\n .\\po_stg2_wrcal_cnt_reg[2]_0 (u_ddr_phy_wrcal_n_97),\n .\\prbs_dqs_cnt_r_reg[2] (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_158 ),\n .\\rank_cnt_r_reg[0]_0 (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_41 ),\n .\\rank_cnt_r_reg[0]_1 (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_42 ),\n .\\rd_data_edge_detect_r_reg[0]_0 (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_7 ),\n .\\rd_data_edge_detect_r_reg[0]_1 (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_10 ),\n .rstdiv0_sync_r1_reg_rep(rstdiv0_sync_r1_reg_rep),\n .rstdiv0_sync_r1_reg_rep__17(rstdiv0_sync_r1_reg_rep__17),\n .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22),\n .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),\n .\\single_rank.done_dqs_dec_reg_0 (wr_level_done_i_1_n_0),\n .stable_cnt1(stable_cnt1),\n .stable_cnt227_in(stable_cnt227_in),\n .\\stable_cnt_reg[3]_0 (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_40 ),\n .\\stg2_r_reg[0] (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_37 ),\n .\\stg2_r_reg[4] (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_24 ),\n .\\stg2_r_reg[5] (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_26 ),\n .\\stg2_tap_cnt_reg[2] (\\u_ocd_lim/stg2_tap_cnt_reg ),\n .\\stg2_target_r_reg[4] (wl_po_fine_cnt_sel_0__0),\n .\\stg3_dec_val_reg[2] (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_25 ),\n .\\stg3_dec_val_reg[2]_0 (\\u_ocd_lim/stg3_dec_val00_out ),\n .\\stg3_r_reg[5] ({\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_29 ,\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_30 ,\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_31 }),\n .\\wait_cnt_reg[0]_0 (po_cnt_dec_i_1__0_n_0),\n .wl_sm_start(wl_sm_start),\n .wr_level_done_r1_reg_0(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_0 ),\n .wr_level_done_r_reg_0(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_54 ),\n .wr_lvl_start_reg(u_ddr_phy_init_n_790),\n .wrlvl_byte_done(wrlvl_byte_done),\n .wrlvl_byte_redo(wrlvl_byte_redo),\n .wrlvl_byte_redo_r(wrlvl_byte_redo_r),\n .wrlvl_byte_redo_reg(u_ddr_phy_wrcal_n_102),\n .wrlvl_done_r_reg(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_12 ),\n .wrlvl_final_mux(wrlvl_final_mux),\n .wrlvl_final_r(wrlvl_final_r),\n .wrlvl_rank_done(wrlvl_rank_done),\n .wrlvl_rank_done_r_reg_0(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_55 ),\n .\\wrlvl_redo_corse_inc_reg[2]_0 (final_coarse_tap));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_1\n (.I0(init_calib_complete_reg_rep__13_n_0),\n .I1(mc_cas_n[1]),\n .O(phy_dout[32]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_1__1\n (.I0(\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .I1(Q[260]),\n .O(\\my_empty_reg[7]_0 [65]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_1__2\n (.I0(\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .I1(Q[261]),\n .O(\\my_empty_reg[7]_1 [65]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_1__3\n (.I0(\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .I1(Q[262]),\n .O(\\my_empty_reg[7]_2 [65]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_1__4\n (.I0(\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .I1(Q[263]),\n .O(\\my_empty_reg[7]_3 [65]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_2__1\n (.I0(\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .I1(Q[256]),\n .O(\\my_empty_reg[7]_0 [64]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_2__2\n (.I0(\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .I1(Q[257]),\n .O(\\my_empty_reg[7]_1 [64]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_2__3\n (.I0(\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .I1(Q[258]),\n .O(\\my_empty_reg[7]_2 [64]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_2__4\n (.I0(\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .I1(Q[259]),\n .O(\\my_empty_reg[7]_3 [64]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_3__1\n (.I0(\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .I1(Q[268]),\n .O(\\my_empty_reg[7]_0 [67]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_3__2\n (.I0(\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .I1(Q[269]),\n .O(\\my_empty_reg[7]_1 [67]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_3__3\n (.I0(\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .I1(Q[270]),\n .O(\\my_empty_reg[7]_2 [67]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_3__4\n (.I0(\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .I1(Q[271]),\n .O(\\my_empty_reg[7]_3 [67]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_4__0\n (.I0(\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .I1(Q[264]),\n .O(\\my_empty_reg[7]_0 [66]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_4__1\n (.I0(\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .I1(Q[265]),\n .O(\\my_empty_reg[7]_1 [66]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_4__2\n (.I0(\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .I1(Q[266]),\n .O(\\my_empty_reg[7]_2 [66]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_4__3\n (.I0(\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .I1(Q[267]),\n .O(\\my_empty_reg[7]_3 [66]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_5\n (.I0(\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .I1(Q[276]),\n .O(\\my_empty_reg[7]_0 [69]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_5__0\n (.I0(\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .I1(Q[277]),\n .O(\\my_empty_reg[7]_1 [69]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_5__1\n (.I0(\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .I1(Q[278]),\n .O(\\my_empty_reg[7]_2 [69]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_5__2\n (.I0(\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .I1(Q[279]),\n .O(\\my_empty_reg[7]_3 [69]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_6\n (.I0(\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .I1(Q[272]),\n .O(\\my_empty_reg[7]_0 [68]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_6__0\n (.I0(\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .I1(Q[273]),\n .O(\\my_empty_reg[7]_1 [68]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_6__1\n (.I0(\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .I1(Q[274]),\n .O(\\my_empty_reg[7]_2 [68]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_6__2\n (.I0(\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .I1(Q[275]),\n .O(\\my_empty_reg[7]_3 [68]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_78_79_i_1\n (.I0(\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .I1(Q[284]),\n .O(\\my_empty_reg[7]_0 [71]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_78_79_i_1__0\n (.I0(\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .I1(Q[285]),\n .O(\\my_empty_reg[7]_1 [71]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_78_79_i_1__1\n (.I0(\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .I1(Q[286]),\n .O(\\my_empty_reg[7]_2 [71]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_78_79_i_1__2\n (.I0(\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .I1(Q[287]),\n .O(\\my_empty_reg[7]_3 [71]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_78_79_i_2\n (.I0(\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .I1(Q[280]),\n .O(\\my_empty_reg[7]_0 [70]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_78_79_i_2__0\n (.I0(\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .I1(Q[281]),\n .O(\\my_empty_reg[7]_1 [70]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_78_79_i_2__1\n (.I0(\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .I1(Q[282]),\n .O(\\my_empty_reg[7]_2 [70]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_78_79_i_2__2\n (.I0(\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .I1(Q[283]),\n .O(\\my_empty_reg[7]_3 [70]));\n LUT6 #(\n .INIT(64'hAFFFFFFF04000000)) \n mpr_dec_cpt_r_i_1\n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_84 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_92 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_85 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_102 ),\n .I4(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_190 ),\n .I5(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_51 ),\n .O(mpr_dec_cpt_r_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair715\" *) \n LUT4 #(\n .INIT(16'h2F20)) \n mpr_last_byte_done_i_1\n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_83 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_183 ),\n .I3(mpr_last_byte_done),\n .O(mpr_last_byte_done_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFFFC8C00000080)) \n mpr_rank_done_r_i_1\n (.I0(cal1_cnt_cpt_r1),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_83 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_84 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_189 ),\n .I4(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_184 ),\n .I5(mpr_rnk_done),\n .O(mpr_rank_done_r_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair728\" *) \n LUT2 #(\n .INIT(4'hE)) \n mpr_rdlvl_done_r_i_1\n (.I0(rdlvl_stg1_done_int),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ),\n .O(mpr_rdlvl_done_r_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFEFFFF00020000)) \n new_cnt_dqs_r_i_1\n (.I0(new_cnt_dqs_r),\n .I1(prbs_state_r[4]),\n .I2(prbs_state_r[1]),\n .I3(prbs_state_r[2]),\n .I4(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_113 ),\n .I5(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_13 ),\n .O(new_cnt_dqs_r_i_1_n_0));\n LUT6 #(\n .INIT(64'h8F888FFF80888000)) \n no_err_win_detected_latch_i_1\n (.I0(prbs_state_r[3]),\n .I1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_11 ),\n .I2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_103 ),\n .I3(prbs_state_r[0]),\n .I4(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_98 ),\n .I5(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_35 ),\n .O(no_err_win_detected_latch_i_1_n_0));\n LUT6 #(\n .INIT(64'hF0F0F4F0B0B0F0F0)) \n num_samples_done_ind_i_1\n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_106 ),\n .I1(prbs_state_r[4]),\n .I2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_34 ),\n .I3(num_samples_done_r),\n .I4(prbs_state_r[1]),\n .I5(prbs_state_r[0]),\n .O(num_samples_done_ind_i_1_n_0));\n ddr3_ifmig_7series_v4_0_ddr_phy_oclkdelay_cal \\oclk_calib.u_ddr_phy_oclkdelay_cal \n (.CLK(CLK),\n .D(\\u_ocd_lim/stg3_dec_val00_out ),\n .D_po_sel_fine_oclk_delay125_out(D_po_sel_fine_oclk_delay125_out),\n .O({\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_0 ,\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_1 ,\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_2 ,\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_3 }),\n .Q(\\po_rdval_cnt_reg[8] [1:0]),\n .S(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_59 ),\n .\\byte_r_reg[0] (\\byte_r_reg[0] ),\n .\\byte_r_reg[0]_0 (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_24 ),\n .\\byte_r_reg[0]_1 (\\byte_r_reg[0]_0 ),\n .\\byte_r_reg[1] (\\byte_r_reg[1] ),\n .\\cal2_state_r_reg[0] (\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_58 ),\n .calib_in_common(calib_in_common),\n .\\calib_zero_inputs_reg[1] ({calib_zero_inputs,calib_zero_inputs__0}),\n .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done),\n .cnt_cmd_done_r(cnt_cmd_done_r),\n .\\cnt_shift_r_reg[0] (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_106 ),\n .complex_ocal_num_samples_done_r(complex_ocal_num_samples_done_r),\n .complex_ocal_rd_victim_sel(complex_ocal_rd_victim_sel),\n .complex_ocal_ref_req(complex_ocal_ref_req),\n .complex_oclk_calib_resume(complex_oclk_calib_resume),\n .done_r_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_13 ),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[0] (\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_56 ),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[1] (\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_57 ),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\phaser_in_gen.phaser_in_i_12__0_n_0 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_0 (\\phaser_in_gen.phaser_in_i_12__2_n_0 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_1 (\\phaser_in_gen.phaser_in_i_12__1_n_0 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_2 (\\phaser_in_gen.phaser_in_i_12_n_0 ),\n .\\init_state_r_reg[0] (\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_49 ),\n .\\init_state_r_reg[0]_0 (u_ddr_phy_init_n_114),\n .\\init_state_r_reg[0]_1 (u_ddr_phy_init_n_478),\n .\\init_state_r_reg[2] (\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_48 ),\n .\\init_state_r_reg[4] (\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_47 ),\n .\\init_state_r_reg[4]_0 (\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_54 ),\n .\\init_state_r_reg[4]_1 ({u_ddr_phy_init_n_105,u_ddr_phy_init_n_106,u_ddr_phy_init_n_108}),\n .\\init_state_r_reg[5] (\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_50 ),\n .\\init_state_r_reg[5]_0 (\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_51 ),\n .\\init_state_r_reg[5]_1 (\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_53 ),\n .\\init_state_r_reg[6] (\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_52 ),\n .lim2init_prech_req(lim2init_prech_req),\n .\\mmcm_current_reg[0] (\\mmcm_current_reg[0] ),\n .\\mmcm_init_trail_reg[0] (\\mmcm_init_trail_reg[0] ),\n .mpr_rdlvl_done_r_reg(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ),\n .ocal_last_byte_done(ocal_last_byte_done),\n .ocal_last_byte_done_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_4 ),\n .ocal_last_byte_done_reg_0(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_55 ),\n .ocd_prech_req(ocd_prech_req),\n .oclkdelay_calib_done_r_reg(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_159 ),\n .oclkdelay_calib_start_int_reg(u_ddr_phy_init_n_462),\n .oclkdelay_calib_start_int_reg_0(u_ddr_phy_init_n_24),\n .oclkdelay_center_calib_start_r_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_15 ),\n .oclkdelay_int_ref_req_reg(u_ddr_phy_init_n_477),\n .pd_out(pd_out),\n .phy_rddata_en(phy_rddata_en),\n .phy_rddata_en_1(phy_rddata_en_1),\n .pi_stg2_rdlvl_cnt(pi_stg2_rdlvl_cnt),\n .\\po_counter_read_val_reg[2] (\\po_counter_read_val_reg[2] ),\n .\\po_counter_read_val_reg[5] (\\po_counter_read_val_reg[5] ),\n .\\po_counter_read_val_reg[8] (\\po_counter_read_val_reg[8]_3 ),\n .\\po_counter_read_val_reg[8]_0 (\\po_counter_read_val_reg[8]_8 ),\n .\\po_counter_read_val_reg[8]_1 (\\po_counter_read_val_reg[8]_11 ),\n .\\po_counter_read_val_reg[8]_2 (\\po_counter_read_val_reg[8]_12 ),\n .\\po_counter_read_val_reg[8]_3 (\\po_counter_read_val_reg[8]_13 ),\n .\\po_counter_read_val_reg[8]_4 (\\po_counter_read_val_reg[8]_14 ),\n .\\po_counter_read_val_reg[8]_5 (\\po_counter_read_val_reg[8]_15 ),\n .po_en_stg23(po_en_stg23),\n .po_stg23_incdec(po_stg23_incdec),\n .\\po_stg2_wrcal_cnt_reg[0] (u_ddr_phy_wrcal_n_105),\n .\\po_stg2_wrcal_cnt_reg[1] (u_ddr_phy_wrcal_n_106),\n .poc_sample_pd(poc_sample_pd),\n .prbs_rdlvl_done_reg(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_45 ),\n .prbs_rdlvl_done_reg_rep(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_51 ),\n .prech_done(prech_done),\n .prech_req_posedge_r_reg(u_ddr_phy_init_n_9),\n .psdone(psdone),\n .\\qcntr_r_reg[0] (\\qcntr_r_reg[0] ),\n .rd_active_r1(rd_active_r1),\n .rd_active_r2(rd_active_r2),\n .rdlvl_stg1_start_reg(u_ddr_phy_init_n_33),\n .\\resume_wait_r_reg[5] (E),\n .rstdiv0_sync_r1_reg_rep(rstdiv0_sync_r1_reg_rep),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10),\n .rstdiv0_sync_r1_reg_rep__11(rstdiv0_sync_r1_reg_rep__11),\n .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),\n .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),\n .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25),\n .rstdiv0_sync_r1_reg_rep__25_0(rstdiv0_sync_r1_reg_rep__25_0),\n .rstdiv0_sync_r1_reg_rep__25_1(rstdiv0_sync_r1_reg_rep__25_1),\n .rstdiv0_sync_r1_reg_rep__25_2(rstdiv0_sync_r1_reg_rep__25_2),\n .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9),\n .\\samps_r_reg[9] (\\samps_r_reg[9] ),\n .\\sm_r_reg[0] (\\sm_r_reg[0] ),\n .\\sm_r_reg[0]_0 (\\sm_r_reg[0]_0 ),\n .sr_valid_r108_out(sr_valid_r108_out),\n .\\stg2_tap_cnt_reg[0] (\\stg2_tap_cnt_reg[0] ),\n .\\stg2_tap_cnt_reg[2] (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_36 ),\n .\\stg2_tap_cnt_reg[3] (\\u_ocd_lim/stg2_tap_cnt_reg ),\n .\\stg2_target_r_reg[8] ({\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_29 ,\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_30 ,\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_31 }),\n .stg3_dec2init_val_r_reg(stg3_dec2init_val_r_reg),\n .stg3_inc2init_val_r_reg(stg3_inc2init_val_r_reg),\n .\\stg3_r_reg[0] (\\stg3_r_reg[0] ),\n .\\stg3_tap_cnt_reg[2] (\\u_ocd_lim/stg3_init_val ),\n .\\wl_po_fine_cnt_reg[14] (wl_po_fine_cnt_sel_0__0),\n .\\wl_po_fine_cnt_reg[17] (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_26 ),\n .\\wl_po_fine_cnt_reg[18] (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_37 ),\n .\\wl_po_fine_cnt_reg[23] ({\\u_ocd_po_cntlr/stg2_target_ns ,wl_po_fine_cnt_sel_0}),\n .\\wl_po_fine_cnt_reg[3] (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_25 ),\n .wr_level_done_reg(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_12 ),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] (\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_28 ),\n .wrlvl_byte_done(wrlvl_byte_done),\n .wrlvl_final_mux(wrlvl_final_mux),\n .wrlvl_final_mux_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ),\n .\\zero2fuzz_r_reg[0] (\\zero2fuzz_r_reg[0] ));\n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_10__6\n (.I0(mc_address[35]),\n .I1(\\my_empty_reg[7] ),\n .I2(\\rd_ptr_reg[3]_0 [2]),\n .I3(\\my_empty_reg[1]_1 ),\n .O(\\my_full_reg[3] [2]));\n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_11__2\n (.I0(\\rd_ptr_timing_reg[0] ),\n .I1(mc_cas_n[1]),\n .I2(\\rd_ptr_reg[3]_0 [1]),\n .I3(\\my_empty_reg[1]_1 ),\n .O(\\my_full_reg[3] [1]));\n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_12__6\n (.I0(mc_address[13]),\n .I1(\\my_empty_reg[7] ),\n .I2(\\rd_ptr_reg[3]_0 [0]),\n .I3(\\my_empty_reg[1]_1 ),\n .O(\\my_full_reg[3] [0]));\n LUT4 #(\n .INIT(16'hBBF0)) \n out_fifo_i_15__6\n (.I0(mc_we_n[2]),\n .I1(\\my_empty_reg[7] ),\n .I2(mem_out[5]),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D1[2]));\n LUT4 #(\n .INIT(16'hBBF0)) \n out_fifo_i_17__5\n (.I0(mc_we_n[0]),\n .I1(\\my_empty_reg[7] ),\n .I2(mem_out[3]),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D1[0]));\n LUT4 #(\n .INIT(16'hBBF0)) \n out_fifo_i_17__6\n (.I0(mc_cas_n[2]),\n .I1(\\my_empty_reg[7] ),\n .I2(\\rd_ptr_reg[3] [2]),\n .I3(\\my_empty_reg[1] ),\n .O(D2[2]));\n LUT4 #(\n .INIT(16'hBBF0)) \n out_fifo_i_19__6\n (.I0(mc_cas_n[0]),\n .I1(\\my_empty_reg[7] ),\n .I2(\\rd_ptr_reg[3] [0]),\n .I3(\\my_empty_reg[1] ),\n .O(D2[0]));\n LUT4 #(\n .INIT(16'hBBF0)) \n out_fifo_i_25__5\n (.I0(mc_ras_n[2]),\n .I1(\\my_empty_reg[7] ),\n .I2(\\rd_ptr_reg[3] [5]),\n .I3(\\my_empty_reg[1] ),\n .O(D3[2]));\n LUT4 #(\n .INIT(16'hBBF0)) \n out_fifo_i_27__5\n (.I0(mc_ras_n[0]),\n .I1(\\my_empty_reg[7] ),\n .I2(\\rd_ptr_reg[3] [3]),\n .I3(\\my_empty_reg[1] ),\n .O(D3[0]));\n LUT4 #(\n .INIT(16'hBBF0)) \n out_fifo_i_7__6\n (.I0(mc_ras_n[2]),\n .I1(\\my_empty_reg[7] ),\n .I2(mem_out[2]),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D0[2]));\n LUT4 #(\n .INIT(16'hBBF0)) \n out_fifo_i_9__6\n (.I0(mc_cs_n),\n .I1(\\my_empty_reg[7] ),\n .I2(mem_out[0]),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair724\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\periodic_read_request.periodic_rd_r_lcl_i_1 \n (.I0(app_zq_r_reg),\n .O(maint_prescaler_r1));\n (* SOFT_HLUTNM = \"soft_lutpair721\" *) \n LUT3 #(\n .INIT(8'hEA)) \n \\phaser_in_gen.phaser_in_i_12 \n (.I0(calib_in_common),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .O(\\phaser_in_gen.phaser_in_i_12_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair722\" *) \n LUT3 #(\n .INIT(8'hBA)) \n \\phaser_in_gen.phaser_in_i_12__0 \n (.I0(calib_in_common),\n .I1(\\po_rdval_cnt_reg[8] [0]),\n .I2(\\po_rdval_cnt_reg[8] [1]),\n .O(\\phaser_in_gen.phaser_in_i_12__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair722\" *) \n LUT3 #(\n .INIT(8'hBA)) \n \\phaser_in_gen.phaser_in_i_12__1 \n (.I0(calib_in_common),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .O(\\phaser_in_gen.phaser_in_i_12__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair721\" *) \n LUT3 #(\n .INIT(8'hAB)) \n \\phaser_in_gen.phaser_in_i_12__2 \n (.I0(calib_in_common),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .O(\\phaser_in_gen.phaser_in_i_12__2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair705\" *) \n LUT4 #(\n .INIT(16'h00F8)) \n \\phaser_in_gen.phaser_in_i_2 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(calib_zero_inputs__0),\n .O(\\pi_dqs_found_lanes_r1_reg[3] ));\n (* SOFT_HLUTNM = \"soft_lutpair714\" *) \n LUT4 #(\n .INIT(16'h00F2)) \n \\phaser_in_gen.phaser_in_i_2__0 \n (.I0(\\po_rdval_cnt_reg[8] [1]),\n .I1(\\po_rdval_cnt_reg[8] [0]),\n .I2(calib_in_common),\n .I3(calib_zero_inputs__0),\n .O(\\pi_dqs_found_lanes_r1_reg[2] ));\n (* SOFT_HLUTNM = \"soft_lutpair718\" *) \n LUT4 #(\n .INIT(16'h00F2)) \n \\phaser_in_gen.phaser_in_i_2__1 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(calib_zero_inputs__0),\n .O(\\pi_dqs_found_lanes_r1_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair718\" *) \n LUT4 #(\n .INIT(16'h00F1)) \n \\phaser_in_gen.phaser_in_i_2__2 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(calib_zero_inputs__0),\n .O(\\pi_dqs_found_lanes_r1_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair717\" *) \n LUT4 #(\n .INIT(16'h0040)) \n phaser_out_i_2\n (.I0(calib_in_common),\n .I1(\\po_rdval_cnt_reg[8] [0]),\n .I2(\\po_rdval_cnt_reg[8] [1]),\n .I3(calib_zero_inputs),\n .O(D_po_counter_read_en122_out));\n (* SOFT_HLUTNM = \"soft_lutpair719\" *) \n LUT4 #(\n .INIT(16'h0001)) \n phaser_out_i_2__0\n (.I0(calib_in_common),\n .I1(\\po_rdval_cnt_reg[8] [0]),\n .I2(\\po_rdval_cnt_reg[8] [1]),\n .I3(calib_zero_inputs),\n .O(\\po_counter_read_val_reg[8] ));\n (* SOFT_HLUTNM = \"soft_lutpair717\" *) \n LUT4 #(\n .INIT(16'h0004)) \n phaser_out_i_2__5\n (.I0(calib_in_common),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .I3(calib_zero_inputs),\n .O(\\po_counter_read_val_reg[8]_28 ));\n (* SOFT_HLUTNM = \"soft_lutpair719\" *) \n LUT4 #(\n .INIT(16'h0004)) \n phaser_out_i_2__6\n (.I0(calib_in_common),\n .I1(\\po_rdval_cnt_reg[8] [0]),\n .I2(\\po_rdval_cnt_reg[8] [1]),\n .I3(calib_zero_inputs),\n .O(\\po_counter_read_val_reg[8]_29 ));\n LUT4 #(\n .INIT(16'hFFFE)) \n phy_if_reset0\n (.I0(reset_if),\n .I1(phy_if_reset_w),\n .I2(mpr_end_if_reset),\n .I3(wrlvl_final_if_rst),\n .O(phy_if_reset0__0));\n FDRE #(\n .INIT(1'b0)) \n phy_if_reset_reg\n (.C(CLK),\n .CE(1'b1),\n .D(phy_if_reset0__0),\n .Q(phy_if_reset),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0000000000400000)) \n pi_cnt_dec_i_1\n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_141 ),\n .I1(wait_cnt_r_reg__0[0]),\n .I2(dqs_po_dec_done_r2),\n .I3(wait_cnt_r_reg__0[1]),\n .I4(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_96 ),\n .I5(rstdiv0_sync_r1_reg_rep__22),\n .O(pi_cnt_dec_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFEFFFFFFFE0000)) \n \\pi_dqs_found_any_bank[0]_i_1 \n (.I0(p_3_in25_in),\n .I1(p_2_in24_in),\n .I2(p_0_in23_in),\n .I3(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_5 ),\n .I4(u_ddr_phy_init_n_502),\n .I5(pi_dqs_found_any_bank),\n .O(\\pi_dqs_found_any_bank[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair723\" *) \n LUT3 #(\n .INIT(8'h08)) \n pi_stg2_f_incdec_timing_i_1\n (.I0(prbs_tap_inc_r),\n .I1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_4 ),\n .I2(rstdiv0_sync_r1_reg_rep__22),\n .O(pi_stg2_f_incdec_timing_i_1_n_0));\n LUT3 #(\n .INIT(8'h04)) \n pi_stg2_load_timing_i_1\n (.I0(regl_dqs_cnt),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_101 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_99 ),\n .O(pi_stg2_load_timing_i_1_n_0));\n LUT6 #(\n .INIT(64'h0000000000800000)) \n po_cnt_dec_i_1\n (.I0(wait_cnt_r_reg__0_1),\n .I1(pi_fine_dly_dec_done),\n .I2(dqs_po_dec_done),\n .I3(\\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_17 ),\n .I4(\\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_12 ),\n .I5(rstdiv0_sync_r1_reg_rep__24),\n .O(po_cnt_dec_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair720\" *) \n LUT3 #(\n .INIT(8'h04)) \n po_cnt_dec_i_1__0\n (.I0(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_46 ),\n .I1(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_38 ),\n .I2(rstdiv0_sync_r1_reg_rep__22),\n .O(po_cnt_dec_i_1__0_n_0));\n LUT5 #(\n .INIT(32'h00000020)) \n po_cnt_inc_i_1\n (.I0(wait_cnt_r_reg__0_1),\n .I1(\\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_17 ),\n .I2(\\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_13 ),\n .I3(\\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_12 ),\n .I4(rstdiv0_sync_r1_reg_rep__23),\n .O(po_cnt_inc_i_1_n_0));\n LUT4 #(\n .INIT(16'hFFFE)) \n po_en_stg2_f0\n (.I0(ck_po_stg2_f_en),\n .I1(dqs_po_en_stg2_f),\n .I2(cmd_po_en_stg2_f),\n .I3(po_en_stg23),\n .O(po_enstg2_f));\n LUT3 #(\n .INIT(8'hFE)) \n po_stg2_f_incdec0\n (.I0(ck_po_stg2_f_indec),\n .I1(dqs_po_stg2_f_incdec),\n .I2(po_stg23_incdec),\n .O(po_stg2_fincdec));\n LUT2 #(\n .INIT(4'h6)) \n \\prbs_dqs_cnt_r[0]_i_1 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_110 ),\n .I1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_9 ),\n .O(\\prbs_dqs_cnt_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair716\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\prbs_dqs_cnt_r[1]_i_1 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_9 ),\n .I1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_110 ),\n .I2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_10 ),\n .O(\\prbs_dqs_cnt_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair716\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\prbs_dqs_cnt_r[2]_i_1 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_9 ),\n .I1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_10 ),\n .I2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_110 ),\n .I3(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_50 ),\n .O(\\prbs_dqs_cnt_r[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair723\" *) \n LUT3 #(\n .INIT(8'h02)) \n prbs_dqs_tap_limit_r_i_1\n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ),\n .I1(rstdiv0_sync_r1_reg_rep__22),\n .I2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_13 ),\n .O(prbs_dqs_tap_limit_r_i_1_n_0));\n LUT6 #(\n .INIT(64'hF2FFFFFF02000000)) \n prbs_found_1st_edge_r_i_1\n (.I0(prbs_state_r178_out),\n .I1(prbs_state_r[3]),\n .I2(prbs_state_r[0]),\n .I3(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_107 ),\n .I4(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_99 ),\n .I5(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_14 ),\n .O(prbs_found_1st_edge_r_i_1_n_0));\n LUT6 #(\n .INIT(64'hDFDFF5F502000000)) \n prbs_last_byte_done_i_1\n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_107 ),\n .I1(prbs_state_r[0]),\n .I2(prbs_state_r[1]),\n .I3(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_112 ),\n .I4(prbs_state_r[3]),\n .I5(prbs_last_byte_done),\n .O(prbs_last_byte_done_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFF337F300000400)) \n prbs_prech_req_r_i_1\n (.I0(prech_done),\n .I1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_107 ),\n .I2(prbs_state_r[1]),\n .I3(prbs_state_r[3]),\n .I4(prbs_state_r[0]),\n .I5(prbs_prech_req_r),\n .O(prbs_prech_req_r_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFF7FFF00004000)) \n prbs_rdlvl_done_i_1\n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_44 ),\n .I1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_111 ),\n .I2(prbs_state_r[3]),\n .I3(prbs_state_r[1]),\n .I4(prbs_state_r[2]),\n .I5(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_51 ),\n .O(prbs_rdlvl_done_i_1_n_0));\n LUT6 #(\n .INIT(64'hA8AAFFFFA8AA0000)) \n prbs_tap_en_r_i_1\n (.I0(prbs_state_r[0]),\n .I1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_100 ),\n .I2(prbs_state_r[1]),\n .I3(prbs_state_r[3]),\n .I4(prbs_tap_en_r),\n .I5(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_4 ),\n .O(prbs_tap_en_r_i_1_n_0));\n LUT6 #(\n .INIT(64'h8A00FFFF8A000000)) \n prbs_tap_inc_r_i_1\n (.I0(prbs_state_r[0]),\n .I1(prbs_state_r[1]),\n .I2(prbs_state_r[3]),\n .I3(prbs_state_r[2]),\n .I4(prbs_tap_en_r),\n .I5(prbs_tap_inc_r),\n .O(prbs_tap_inc_r_i_1_n_0));\n LUT3 #(\n .INIT(8'hBA)) \n prech_pending_r_i_1\n (.I0(u_ddr_phy_init_n_9),\n .I1(u_ddr_phy_init_n_468),\n .I2(prech_pending_r),\n .O(prech_pending_r_i_1_n_0));\n LUT6 #(\n .INIT(64'h0000000000707070)) \n rank_done_r_i_1\n (.I0(pi_dqs_found_all_bank_r[1]),\n .I1(pi_dqs_found_all_bank_r[0]),\n .I2(p_1_in27_in),\n .I3(rd_data_offset_cal_done),\n .I4(\\rd_byte_data_offset_reg[0]_3 ),\n .I5(rstdiv0_sync_r1_reg_rep__23),\n .O(rank_done_r_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair720\" *) \n LUT3 #(\n .INIT(8'hFE)) \n \\rd_addr[7]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__22),\n .I1(complex_ocal_reset_rd_addr),\n .I2(reset_rd_addr),\n .O(\\rd_addr[7]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair715\" *) \n LUT4 #(\n .INIT(16'h8F80)) \n rdlvl_last_byte_done_int_i_1\n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_83 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_183 ),\n .I3(rdlvl_last_byte_done),\n .O(rdlvl_last_byte_done_int_i_1_n_0));\n LUT5 #(\n .INIT(32'h70FF7000)) \n rdlvl_pi_incdec_i_1\n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_86 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_87 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_180 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_185 ),\n .I4(rdlvl_pi_incdec),\n .O(rdlvl_pi_incdec_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFFFC8C00000080)) \n rdlvl_rank_done_r_i_1\n (.I0(cal1_cnt_cpt_r1),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_83 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_84 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_188 ),\n .I4(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_184 ),\n .I5(rdlvl_stg1_rank_done),\n .O(rdlvl_rank_done_r_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFF00010000)) \n rdlvl_start_pre_i_1\n (.I0(u_ddr_phy_init_n_102),\n .I1(u_ddr_phy_init_n_469),\n .I2(u_ddr_phy_init_n_108),\n .I3(u_ddr_phy_init_n_107),\n .I4(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_10 ),\n .I5(rdlvl_start_pre),\n .O(rdlvl_start_pre_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair728\" *) \n LUT3 #(\n .INIT(8'hB8)) \n rdlvl_stg1_done_int_i_1\n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ),\n .I1(rdlvl_stg1_done_int),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_56 ),\n .O(rdlvl_stg1_done_int_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFEFFFF00020000)) \n rdlvl_stg1_start_i_1\n (.I0(rdlvl_start_dly0_r),\n .I1(u_ddr_phy_init_n_473),\n .I2(u_ddr_phy_init_n_108),\n .I3(u_ddr_phy_init_n_107),\n .I4(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_10 ),\n .I5(u_ddr_phy_init_n_33),\n .O(rdlvl_stg1_start_i_1_n_0));\n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/reset_if_r8_reg_srl8 \" *) \n SRL16E #(\n .INIT(16'h0000)) \n reset_if_r8_reg_srl8\n (.A0(1'b1),\n .A1(1'b1),\n .A2(1'b1),\n .A3(1'b0),\n .CE(1'b1),\n .CLK(CLK),\n .D(reset_if),\n .Q(reset_if_r8_reg_srl8_n_0));\n FDRE #(\n .INIT(1'b0)) \n reset_if_r9_reg\n (.C(CLK),\n .CE(1'b1),\n .D(reset_if_r8_reg_srl8_n_0),\n .Q(reset_if_r9),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n reset_if_reg\n (.C(CLK),\n .CE(1'b1),\n .D(u_ddr_phy_init_n_101),\n .Q(reset_if),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFEFFEFF00000010)) \n reset_rd_addr_i_1\n (.I0(prbs_state_r[4]),\n .I1(prbs_state_r[2]),\n .I2(prbs_state_r[3]),\n .I3(prbs_state_r[0]),\n .I4(prbs_state_r[1]),\n .I5(reset_rd_addr),\n .O(reset_rd_addr_i_1_n_0));\n LUT5 #(\n .INIT(32'h04FF0400)) \n right_edge_found_i_1\n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_11 ),\n .I1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_79 ),\n .I2(prbs_state_r[4]),\n .I3(right_edge_found),\n .I4(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_32 ),\n .O(right_edge_found_i_1_n_0));\n LUT5 #(\n .INIT(32'hBABF8A80)) \n rst_dqs_find_i_1\n (.I0(rst_dqs_find),\n .I1(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_107 ),\n .I2(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ),\n .I3(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_105 ),\n .I4(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_9 ),\n .O(rst_dqs_find_i_1_n_0));\n LUT4 #(\n .INIT(16'hABAA)) \n store_sr_r_i_1\n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_1 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_6 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_2 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_30 ),\n .O(store_sr_r_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n tempmon_pi_f_en_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(tempmon_sel_pi_incdec),\n .Q(tempmon_pi_f_en_r),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE #(\n .INIT(1'b0)) \n tempmon_pi_f_inc_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(tempmon_pi_f_inc),\n .Q(tempmon_pi_f_inc_r),\n .R(rstdiv0_sync_r1_reg_rep__9));\n ddr3_ifmig_7series_v4_0_ddr_phy_init u_ddr_phy_init\n (.A_rst_primitives_reg(A_rst_primitives_reg),\n .CLK(CLK),\n .D({\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_155 ,\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_156 }),\n .D0(D0[1]),\n .D1(D1[1]),\n .D2(D2[1]),\n .D3(D3[1]),\n .D4(D4),\n .D5(D5),\n .D6(D6),\n .D7(D7),\n .D8(D8),\n .D9(D9),\n .E(u_ddr_phy_init_n_465),\n .Q({init_state_r,u_ddr_phy_init_n_104,u_ddr_phy_init_n_105,u_ddr_phy_init_n_106,u_ddr_phy_init_n_107,u_ddr_phy_init_n_108}),\n .\\back_to_back_reads_4_1.num_reads_reg[0]_0 (u_ddr_phy_init_n_473),\n .\\back_to_back_reads_4_1.num_reads_reg[1]_0 (u_ddr_phy_init_n_474),\n .burst_addr_r_reg_0(u_ddr_phy_init_n_31),\n .burst_addr_r_reg_1(u_ddr_phy_init_n_476),\n .burst_addr_r_reg_2(burst_addr_r_i_1_n_0),\n .cal1_state_r1535_out(cal1_state_r1535_out),\n .calib_complete(calib_complete),\n .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[0] (\\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[1] (\\cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[2] (\\cmd_pipe_plus.mc_data_offset_1_reg[2] ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[3] (\\cmd_pipe_plus.mc_data_offset_1_reg[3] ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[4] (\\cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[5] (\\cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_reg[0] (\\cmd_pipe_plus.mc_data_offset_reg[0]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_reg[1] (\\cmd_pipe_plus.mc_data_offset_reg[1]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_reg[2] (\\cmd_pipe_plus.mc_data_offset_reg[2] ),\n .\\cmd_pipe_plus.mc_data_offset_reg[3] (\\cmd_pipe_plus.mc_data_offset_reg[3] ),\n .\\cmd_pipe_plus.mc_data_offset_reg[4] (\\cmd_pipe_plus.mc_data_offset_reg[4]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_reg[5] (\\cmd_pipe_plus.mc_data_offset_reg[5]_0 ),\n .cnt_cmd_done_r(cnt_cmd_done_r),\n .cnt_cmd_done_r_reg_0(ddr2_refresh_flag_r_i_1_n_0),\n .cnt_cmd_done_r_reg_1(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_54 ),\n .cnt_dllk_zqinit_done_r(cnt_dllk_zqinit_done_r),\n .cnt_dllk_zqinit_done_r_reg_0(cnt_dllk_zqinit_done_r_i_1_n_0),\n .cnt_init_af_done_r(cnt_init_af_done_r),\n .cnt_init_af_done_r_reg_0(cnt_init_af_done_r_i_1_n_0),\n .cnt_init_af_done_r_reg_1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_144 ),\n .cnt_init_af_r(cnt_init_af_r),\n .cnt_init_mr_done_r(cnt_init_mr_done_r),\n .cnt_init_mr_done_r_reg_0(cnt_init_mr_done_r_i_1_n_0),\n .cnt_init_mr_r(cnt_init_mr_r),\n .cnt_init_mr_r1(cnt_init_mr_r1),\n .\\cnt_init_mr_r_reg[1]_0 (u_ddr_phy_init_n_110),\n .cnt_pwron_cke_done_r(cnt_pwron_cke_done_r),\n .cnt_pwron_cke_done_r_reg_0(u_ddr_phy_init_n_490),\n .cnt_pwron_cke_done_r_reg_1(cnt_pwron_cke_done_r_i_1_n_0),\n .\\cnt_pwron_r_reg[7]_0 ({cnt_pwron_r_reg__0[7],cnt_pwron_r_reg__0[5],cnt_pwron_r_reg__0[1:0]}),\n .\\cnt_pwron_r_reg[7]_1 (cnt_pwron_reset_done_r_i_1_n_0),\n .cnt_pwron_reset_done_r(cnt_pwron_reset_done_r),\n .cnt_pwron_reset_done_r_reg_0(u_ddr_phy_init_n_485),\n .\\cnt_shift_r_reg[0] (cnt_shift_r0),\n .\\cnt_shift_r_reg[0]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_106 ),\n .cnt_txpr_done_r(cnt_txpr_done_r),\n .cnt_txpr_done_r_reg_0(u_ddr_phy_init_n_500),\n .cnt_txpr_done_r_reg_1(cnt_txpr_done_r_i_1_n_0),\n .\\cnt_txpr_r_reg[2]_0 (cnt_txpr_r_reg__0),\n .complex_act_start(complex_act_start),\n .complex_init_pi_dec_done(complex_init_pi_dec_done),\n .complex_ocal_num_samples_done_r(complex_ocal_num_samples_done_r),\n .complex_ocal_rd_victim_sel(complex_ocal_rd_victim_sel),\n .complex_ocal_ref_req(complex_ocal_ref_req),\n .complex_ocal_reset_rd_addr(complex_ocal_reset_rd_addr),\n .complex_oclk_calib_resume(complex_oclk_calib_resume),\n .complex_oclkdelay_calib_start_int_reg_0(u_ddr_phy_init_n_114),\n .complex_pi_incdec_done(complex_pi_incdec_done),\n .\\complex_row_cnt_ocal_reg[0]_0 (\\complex_row_cnt_ocal_reg[0] ),\n .complex_victim_inc_reg(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_1 ),\n .\\data_offset_1_i1_reg[5] (\\data_offset_1_i1_reg[5] ),\n .ddr2_pre_flag_r_reg_0(u_ddr_phy_init_n_29),\n .ddr2_pre_flag_r_reg_1(u_ddr_phy_init_n_479),\n .ddr2_pre_flag_r_reg_2(ddr2_pre_flag_r_i_1_n_0),\n .ddr2_refresh_flag_r(ddr2_refresh_flag_r),\n .ddr2_refresh_flag_r_reg_0(u_ddr_phy_init_n_480),\n .ddr3_lm_done_r(ddr3_lm_done_r),\n .delay_done_r4_reg(\\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_11 ),\n .detect_pi_found_dqs(detect_pi_found_dqs),\n .done_dqs_tap_inc(done_dqs_tap_inc),\n .done_r_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_13 ),\n .\\dout_o_reg[0] (u_ddr_prbs_gen_n_120),\n .\\dout_o_reg[0]_0 (u_ddr_prbs_gen_n_116),\n .\\dout_o_reg[10] (u_ddr_prbs_gen_n_6),\n .\\dout_o_reg[10]_0 (u_ddr_prbs_gen_n_5),\n .\\dout_o_reg[11] (u_ddr_prbs_gen_n_41),\n .\\dout_o_reg[11]_0 (u_ddr_prbs_gen_n_42),\n .\\dout_o_reg[11]_1 (u_ddr_prbs_gen_n_51),\n .\\dout_o_reg[11]_2 (u_ddr_prbs_gen_n_52),\n .\\dout_o_reg[11]_3 (u_ddr_prbs_gen_n_16),\n .\\dout_o_reg[11]_4 (u_ddr_prbs_gen_n_15),\n .\\dout_o_reg[12] (u_ddr_prbs_gen_n_2),\n .\\dout_o_reg[12]_0 (u_ddr_prbs_gen_n_1),\n .\\dout_o_reg[13] (u_ddr_prbs_gen_n_53),\n .\\dout_o_reg[13]_0 (u_ddr_prbs_gen_n_54),\n .\\dout_o_reg[13]_1 (u_ddr_prbs_gen_n_28),\n .\\dout_o_reg[13]_2 (u_ddr_prbs_gen_n_27),\n .\\dout_o_reg[13]_3 (u_ddr_prbs_gen_n_18),\n .\\dout_o_reg[13]_4 (u_ddr_prbs_gen_n_17),\n .\\dout_o_reg[13]_5 (u_ddr_prbs_gen_n_14),\n .\\dout_o_reg[13]_6 (u_ddr_prbs_gen_n_13),\n .\\dout_o_reg[14] (u_ddr_prbs_gen_n_46),\n .\\dout_o_reg[14]_0 (u_ddr_prbs_gen_n_45),\n .\\dout_o_reg[14]_1 (u_ddr_prbs_gen_n_44),\n .\\dout_o_reg[14]_2 (u_ddr_prbs_gen_n_43),\n .\\dout_o_reg[15] (u_ddr_prbs_gen_n_12),\n .\\dout_o_reg[15]_0 (u_ddr_prbs_gen_n_11),\n .\\dout_o_reg[15]_1 (u_ddr_prbs_gen_n_10),\n .\\dout_o_reg[15]_2 (u_ddr_prbs_gen_n_9),\n .\\dout_o_reg[1] (u_ddr_prbs_gen_n_19),\n .\\dout_o_reg[1]_0 (u_ddr_prbs_gen_n_20),\n .\\dout_o_reg[2] (u_ddr_prbs_gen_n_105),\n .\\dout_o_reg[2]_0 (u_ddr_prbs_gen_n_101),\n .\\dout_o_reg[3] (u_ddr_prbs_gen_n_21),\n .\\dout_o_reg[3]_0 (u_ddr_prbs_gen_n_22),\n .\\dout_o_reg[4] (u_ddr_prbs_gen_n_88),\n .\\dout_o_reg[4]_0 (u_ddr_prbs_gen_n_84),\n .\\dout_o_reg[6] (u_ddr_prbs_gen_n_56),\n .\\dout_o_reg[7] (u_ddr_prbs_gen_n_24),\n .\\dout_o_reg[7]_0 (u_ddr_prbs_gen_n_23),\n .\\dout_o_reg[7]_1 (u_ddr_prbs_gen_n_25),\n .\\dout_o_reg[7]_2 (u_ddr_prbs_gen_n_26),\n .\\dout_o_reg[8] (u_ddr_prbs_gen_n_48),\n .\\dout_o_reg[8]_0 (u_ddr_prbs_gen_n_47),\n .\\dout_o_reg[8]_1 (u_ddr_prbs_gen_n_8),\n .\\dout_o_reg[8]_2 (u_ddr_prbs_gen_n_7),\n .\\dout_o_reg[8]_3 (u_ddr_prbs_gen_n_4),\n .\\dout_o_reg[8]_4 (u_ddr_prbs_gen_n_3),\n .\\dout_o_reg[9] (u_ddr_prbs_gen_n_49),\n .\\dout_o_reg[9]_0 (u_ddr_prbs_gen_n_50),\n .\\dout_o_reg[9]_1 (u_ddr_prbs_gen_n_38),\n .\\dout_o_reg[9]_2 (u_ddr_prbs_gen_n_37),\n .\\dout_o_reg[9]_3 (u_ddr_prbs_gen_n_36),\n .\\dout_o_reg[9]_4 (u_ddr_prbs_gen_n_35),\n .dqs_found_done_r_reg(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_10 ),\n .dqs_found_done_r_reg_0(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_83 ),\n .dqs_found_done_r_reg_1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_149 ),\n .dqs_found_done_r_reg_2(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_85 ),\n .dqs_found_prech_req(dqs_found_prech_req),\n .dqs_found_start_r_reg(u_ddr_phy_init_n_502),\n .\\en_cnt_div4.enable_wrlvl_cnt_reg[3]_0 (\\en_cnt_div4.enable_wrlvl_cnt_reg[3] ),\n .first_rdlvl_pat_r(first_rdlvl_pat_r),\n .first_rdlvl_pat_r_reg_0(u_ddr_prbs_gen_n_55),\n .first_wrcal_pat_r(first_wrcal_pat_r),\n .in0(init_complete_r_timing_orig),\n .init_calib_complete_reg_rep(\\my_empty_reg[7] ),\n .init_calib_complete_reg_rep__0(init_calib_complete_reg_rep__0_n_0),\n .init_calib_complete_reg_rep__1(init_calib_complete_reg_rep__1_n_0),\n .init_calib_complete_reg_rep__10(init_calib_complete_reg_rep__10_n_0),\n .init_calib_complete_reg_rep__11(init_calib_complete_reg_rep__11_n_0),\n .init_calib_complete_reg_rep__12(init_calib_complete_reg_rep__12_n_0),\n .init_calib_complete_reg_rep__13(init_calib_complete_reg_rep__13_n_0),\n .init_calib_complete_reg_rep__14(init_calib_complete_r_reg),\n .init_calib_complete_reg_rep__2(init_calib_complete_reg_rep__2_n_0),\n .init_calib_complete_reg_rep__3(init_calib_complete_reg_rep__3_n_0),\n .init_calib_complete_reg_rep__4(init_calib_complete_reg_rep__4_n_0),\n .init_calib_complete_reg_rep__5(\\rd_ptr_timing_reg[0] ),\n .init_calib_complete_reg_rep__6(app_zq_r_reg),\n .init_calib_complete_reg_rep__7(\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .init_calib_complete_reg_rep__8(init_calib_complete_reg_rep__8_n_0),\n .init_calib_complete_reg_rep__9(init_calib_complete_reg_rep__9_n_0),\n .init_complete_r1_reg_0(u_ddr_phy_init_n_18),\n .init_dqsfound_done_r2(init_dqsfound_done_r2),\n .\\init_state_r_reg[0]_0 (u_ddr_phy_init_n_497),\n .\\init_state_r_reg[0]_1 (rdlvl_start_pre_i_1_n_0),\n .\\init_state_r_reg[1]_0 (u_ddr_phy_init_n_111),\n .\\init_state_r_reg[1]_1 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_80 ),\n .\\init_state_r_reg[2]_0 (u_ddr_phy_init_n_117),\n .\\init_state_r_reg[2]_1 (u_ddr_phy_init_n_499),\n .\\init_state_r_reg[2]_2 (\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_48 ),\n .\\init_state_r_reg[4]_0 (u_ddr_phy_init_n_475),\n .\\init_state_r_reg[5]_0 (u_ddr_phy_init_n_478),\n .\\init_state_r_reg[6]_0 (init_complete_r_i_1_n_0),\n .\\init_state_r_reg[6]_1 (init_complete_r_timing_i_1_n_0),\n .lim2init_prech_req(lim2init_prech_req),\n .lim_start_r_reg(u_ddr_phy_init_n_462),\n .\\mcGo_r_reg[15] (\\mcGo_r_reg[15] ),\n .mc_address({mc_address[34:14],mc_address[12:0]}),\n .mc_bank(mc_bank),\n .mc_cas_n(mc_cas_n[1]),\n .mc_cke(mc_cke),\n .mc_cmd(mc_cmd),\n .mc_odt(mc_odt),\n .mc_ras_n(mc_ras_n[1]),\n .mc_we_n(mc_we_n[1]),\n .mc_wrdata_en(mc_wrdata_en),\n .mem_init_done_r(mem_init_done_r),\n .mem_init_done_r_reg_0(cnt_dllk_zqinit_r_reg__0),\n .mem_init_done_r_reg_1(u_ddr_phy_init_n_496),\n .mem_init_done_r_reg_2(u_ddr_phy_wrcal_n_92),\n .mem_out({mem_out[4],mem_out[1]}),\n .mpr_end_if_reset(mpr_end_if_reset),\n .mpr_last_byte_done(mpr_last_byte_done),\n .mpr_rdlvl_done_r_reg(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ),\n .mpr_rdlvl_done_r_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_142 ),\n .mpr_rdlvl_done_r_reg_1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_146 ),\n .mpr_rdlvl_done_r_reg_2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_147 ),\n .mpr_rdlvl_start_r(mpr_rdlvl_start_r),\n .mpr_rdlvl_start_r_reg(u_ddr_phy_init_n_464),\n .mux_cmd_wren(mux_cmd_wren),\n .mux_reset_n(mux_reset_n),\n .mux_wrdata_en(mux_wrdata_en),\n .\\my_empty_reg[1] (\\my_empty_reg[1] ),\n .\\my_empty_reg[1]_0 (\\my_empty_reg[1]_0 ),\n .\\my_empty_reg[1]_1 (\\my_empty_reg[1]_1 ),\n .\\my_empty_reg[1]_2 (\\my_empty_reg[1]_2 ),\n .\\my_empty_reg[1]_3 (\\my_empty_reg[1]_3 ),\n .\\my_empty_reg[1]_4 (\\my_empty_reg[1]_4 ),\n .\\my_empty_reg[1]_5 (\\my_empty_reg[1]_5 ),\n .\\my_empty_reg[1]_6 (\\my_empty_reg[1]_6 ),\n .\\my_empty_reg[7] (\\my_empty_reg[7]_4 ),\n .\\my_empty_reg[7]_0 (\\my_empty_reg[7]_5 ),\n .\\my_empty_reg[7]_1 (\\my_empty_reg[7]_6 ),\n .\\my_empty_reg[7]_10 (\\my_empty_reg[7]_15 ),\n .\\my_empty_reg[7]_11 (\\my_empty_reg[7]_16 ),\n .\\my_empty_reg[7]_12 (\\my_empty_reg[7]_17 ),\n .\\my_empty_reg[7]_13 (\\my_empty_reg[7]_18 ),\n .\\my_empty_reg[7]_14 (\\my_empty_reg[7]_19 ),\n .\\my_empty_reg[7]_15 (\\my_empty_reg[7]_20 ),\n .\\my_empty_reg[7]_16 (\\my_empty_reg[7]_21 ),\n .\\my_empty_reg[7]_17 (\\my_empty_reg[7]_22 ),\n .\\my_empty_reg[7]_18 (\\my_empty_reg[7]_23 ),\n .\\my_empty_reg[7]_19 (\\my_empty_reg[7]_24 ),\n .\\my_empty_reg[7]_2 (\\my_empty_reg[7]_7 ),\n .\\my_empty_reg[7]_20 (\\my_empty_reg[7]_25 ),\n .\\my_empty_reg[7]_21 (\\my_empty_reg[7]_26 ),\n .\\my_empty_reg[7]_22 (\\my_empty_reg[7]_27 ),\n .\\my_empty_reg[7]_23 (\\my_empty_reg[7]_28 ),\n .\\my_empty_reg[7]_24 (\\my_empty_reg[7]_29 ),\n .\\my_empty_reg[7]_25 (\\my_empty_reg[7]_30 ),\n .\\my_empty_reg[7]_26 (\\my_empty_reg[7]_31 ),\n .\\my_empty_reg[7]_27 (\\my_empty_reg[7]_32 ),\n .\\my_empty_reg[7]_28 (\\my_empty_reg[7]_33 ),\n .\\my_empty_reg[7]_29 (\\my_empty_reg[7]_34 ),\n .\\my_empty_reg[7]_3 (\\my_empty_reg[7]_8 ),\n .\\my_empty_reg[7]_30 (\\my_empty_reg[7]_35 ),\n .\\my_empty_reg[7]_31 (\\my_empty_reg[7]_36 ),\n .\\my_empty_reg[7]_32 (\\my_empty_reg[7]_37 ),\n .\\my_empty_reg[7]_33 (\\my_empty_reg[7]_38 ),\n .\\my_empty_reg[7]_34 (\\my_empty_reg[7]_39 ),\n .\\my_empty_reg[7]_35 (\\my_empty_reg[7]_40 ),\n .\\my_empty_reg[7]_36 (\\my_empty_reg[7]_41 ),\n .\\my_empty_reg[7]_37 (\\my_empty_reg[7]_42 ),\n .\\my_empty_reg[7]_38 (\\my_empty_reg[7]_0 [63:0]),\n .\\my_empty_reg[7]_39 (\\my_empty_reg[7]_1 [63:0]),\n .\\my_empty_reg[7]_4 (\\my_empty_reg[7]_9 ),\n .\\my_empty_reg[7]_40 (\\my_empty_reg[7]_2 [63:0]),\n .\\my_empty_reg[7]_41 (\\my_empty_reg[7]_3 [63:0]),\n .\\my_empty_reg[7]_5 (\\my_empty_reg[7]_10 ),\n .\\my_empty_reg[7]_6 (\\my_empty_reg[7]_11 ),\n .\\my_empty_reg[7]_7 (\\my_empty_reg[7]_12 ),\n .\\my_empty_reg[7]_8 (\\my_empty_reg[7]_13 ),\n .\\my_empty_reg[7]_9 (\\my_empty_reg[7]_14 ),\n .\\my_full_reg[3] (\\my_full_reg[3]_0 ),\n .new_cnt_dqs_r_reg(u_ddr_phy_init_n_127),\n .num_samples_done_r(num_samples_done_r),\n .ocal_last_byte_done(ocal_last_byte_done),\n .ocd_prech_req(ocd_prech_req),\n .oclk_calib_resume_level_reg_0(u_ddr_phy_init_n_102),\n .oclk_calib_resume_r_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_47 ),\n .oclk_calib_resume_r_reg_0(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_51 ),\n .oclkdelay_calib_done_r_reg(u_ddr_prbs_gen_n_40),\n .oclkdelay_calib_done_r_reg_0(u_ddr_prbs_gen_n_39),\n .oclkdelay_calib_done_r_reg_1(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_28 ),\n .oclkdelay_calib_done_r_reg_2(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ),\n .oclkdelay_calib_done_r_reg_3(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_50 ),\n .oclkdelay_calib_done_r_reg_4(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_81 ),\n .oclkdelay_calib_done_r_reg_5(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_81 ),\n .oclkdelay_center_calib_done_r_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_55 ),\n .oclkdelay_center_calib_done_r_reg_0(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_4 ),\n .oclkdelay_center_calib_start_r_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_15 ),\n .oclkdelay_center_calib_start_r_reg_0(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_49 ),\n .oclkdelay_int_ref_req_reg_0(u_ddr_phy_init_n_477),\n .\\oclkdelay_ref_cnt_reg[13]_0 (u_ddr_phy_init_n_24),\n .\\odd_cwl.phy_cas_n_reg[1]_0 (u_ddr_phy_init_n_109),\n .\\one_rank.stg1_wr_done_reg_0 (u_ddr_phy_init_n_116),\n .out(out),\n .p_81_in(p_81_in),\n .\\phy_ctl_wd_i1_reg[24] (\\phy_ctl_wd_i1_reg[24] ),\n .phy_dout(phy_dout[31:0]),\n .phy_if_empty_r_reg(u_ddr_prbs_gen_n_0),\n .phy_rddata_en_1(phy_rddata_en_1),\n .phy_read_calib(phy_read_calib),\n .phy_write_calib(phy_write_calib),\n .pi_calib_done(pi_calib_done),\n .\\pi_dqs_found_all_bank_reg[1] (u_ddr_phy_init_n_501),\n .\\pi_dqs_found_all_bank_reg[1]_0 (pi_dqs_found_all_bank),\n .pi_dqs_found_done_r1(pi_dqs_found_done_r1),\n .pi_dqs_found_done_r1_reg_0(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_86 ),\n .pi_dqs_found_done_r1_reg_1(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_87 ),\n .pi_dqs_found_done_r1_reg_2(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_88 ),\n .pi_dqs_found_done_r1_reg_3(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_89 ),\n .pi_dqs_found_done_r1_reg_4(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_90 ),\n .pi_dqs_found_done_r1_reg_5(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_91 ),\n .pi_dqs_found_done_r1_reg_6(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_92 ),\n .pi_dqs_found_done_r1_reg_7(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_93 ),\n .pi_dqs_found_rank_done(pi_dqs_found_rank_done),\n .prbs_last_byte_done(prbs_last_byte_done),\n .prbs_last_byte_done_r(prbs_last_byte_done_r),\n .prbs_last_byte_done_reg(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_90 ),\n .prbs_rdlvl_done_pulse0(prbs_rdlvl_done_pulse0),\n .prbs_rdlvl_done_r1(prbs_rdlvl_done_r1),\n .prbs_rdlvl_done_reg(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_45 ),\n .prbs_rdlvl_done_reg_0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_85 ),\n .prbs_rdlvl_done_reg_rep(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_51 ),\n .prbs_rdlvl_done_reg_rep_0(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_52 ),\n .prbs_rdlvl_done_reg_rep_1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_145 ),\n .prbs_rdlvl_done_reg_rep_2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_87 ),\n .prbs_rdlvl_done_reg_rep_3(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_88 ),\n .prbs_rdlvl_prech_req_reg(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_2 ),\n .prbs_rdlvl_start_r(prbs_rdlvl_start_r),\n .prbs_rdlvl_start_r_reg(prbs_rdlvl_start_r_reg),\n .prech_done(prech_done),\n .prech_pending_r(prech_pending_r),\n .prech_pending_r_reg_0(u_ddr_phy_init_n_9),\n .prech_pending_r_reg_1(u_ddr_phy_init_n_468),\n .prech_req(prech_req),\n .prech_req_posedge_r_reg_0(prech_pending_r_i_1_n_0),\n .\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3] (rd_data_offset_ranks_0),\n .\\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] (rd_data_offset_ranks_1),\n .\\rd_addr_reg[0] (u_ddr_phy_init_n_786),\n .\\rd_addr_reg[3] (u_ddr_prbs_gen_n_57),\n .\\rd_addr_reg_rep[7] (u_ddr_phy_init_n_785),\n .\\rd_byte_data_offset_reg[0][3] ({\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_69 ,\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_70 }),\n .\\rd_byte_data_offset_reg[0][9] (p_0_in_0),\n .\\rd_ptr_reg[3] ({\\rd_ptr_reg[3] [37:6],\\rd_ptr_reg[3] [4],\\rd_ptr_reg[3] [1]}),\n .\\rd_ptr_reg[3]_0 (\\rd_ptr_reg[3]_0 [11:4]),\n .\\rd_ptr_reg[3]_1 (\\rd_ptr_reg[3]_1 ),\n .\\rd_ptr_reg[3]_2 (\\rd_ptr_reg[3]_2 ),\n .\\rd_ptr_reg[3]_3 (\\rd_ptr_reg[3]_3 ),\n .\\rd_ptr_reg[3]_4 (\\rd_ptr_reg[3]_4 ),\n .\\rd_ptr_reg[3]_5 (\\rd_ptr_reg[3]_5 ),\n .\\rd_ptr_timing_reg[0] (\\rd_ptr_timing_reg[0]_0 ),\n .\\rd_ptr_timing_reg[0]_0 (\\rd_ptr_timing_reg[0]_1 ),\n .\\rd_ptr_timing_reg[0]_1 (\\rd_ptr_timing_reg[0]_2 ),\n .\\rd_ptr_timing_reg[0]_2 (\\rd_ptr_timing_reg[0]_3 ),\n .\\rd_ptr_timing_reg[0]_3 (\\rd_ptr_timing_reg[0]_4 ),\n .\\rd_victim_sel_reg[0] (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_116 ),\n .\\rd_victim_sel_reg[1] (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_115 ),\n .\\rd_victim_sel_reg[2] (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_117 ),\n .rdlvl_last_byte_done(rdlvl_last_byte_done),\n .rdlvl_pi_incdec(rdlvl_pi_incdec),\n .rdlvl_prech_req(rdlvl_prech_req),\n .rdlvl_start_dly0_r(rdlvl_start_dly0_r),\n .\\rdlvl_start_dly0_r_reg[14]_0 (rdlvl_stg1_start_i_1_n_0),\n .rdlvl_start_pre(rdlvl_start_pre),\n .rdlvl_start_pre_reg_0(u_ddr_phy_init_n_469),\n .rdlvl_stg1_done_int_reg(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_56 ),\n .rdlvl_stg1_done_int_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_153 ),\n .rdlvl_stg1_done_int_reg_1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_79 ),\n .rdlvl_stg1_done_int_reg_2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_154 ),\n .rdlvl_stg1_done_int_reg_3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_151 ),\n .rdlvl_stg1_done_int_reg_4(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_82 ),\n .rdlvl_stg1_rank_done(rdlvl_stg1_rank_done),\n .rdlvl_stg1_start_int(rdlvl_stg1_start_int),\n .rdlvl_stg1_start_r_reg(u_ddr_phy_init_n_33),\n .read_calib_reg_0(u_ddr_phy_init_n_470),\n .\\reg_ctrl_cnt_r_reg[3]_0 (u_ddr_phy_init_n_115),\n .reset_if(reset_if),\n .reset_if_r9(reset_if_r9),\n .reset_if_reg(u_ddr_phy_init_n_101),\n .reset_rd_addr(reset_rd_addr),\n .reset_rd_addr0(reset_rd_addr0),\n .\\row_cnt_victim_rotate.complex_row_cnt_reg[4]_0 (\\row_cnt_victim_rotate.complex_row_cnt_reg[4] ),\n .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10),\n .rstdiv0_sync_r1_reg_rep__11(rstdiv0_sync_r1_reg_rep__11),\n .rstdiv0_sync_r1_reg_rep__12(rstdiv0_sync_r1_reg_rep__12),\n .rstdiv0_sync_r1_reg_rep__18(rstdiv0_sync_r1_reg_rep__17[0]),\n .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22),\n .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23),\n .rstdiv0_sync_r1_reg_rep__23_0(rstdiv0_sync_r1_reg_rep__23_0),\n .rstdiv0_sync_r1_reg_rep__23_1(rstdiv0_sync_r1_reg_rep__23_1),\n .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),\n .\\samples_cnt_r_reg[11] (samples_cnt_r),\n .\\samples_cnt_r_reg[11]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_84 ),\n .stg1_wr_done(stg1_wr_done),\n .temp_lmr_done(temp_lmr_done),\n .\\victim_sel_rotate.sel_reg[31] ({sel,u_ddr_phy_init_n_120,u_ddr_phy_init_n_121,u_ddr_phy_init_n_122,u_ddr_phy_init_n_123,u_ddr_phy_init_n_124,u_ddr_phy_init_n_125,u_ddr_phy_init_n_126}),\n .wl_sm_start(wl_sm_start),\n .wr_level_done_reg(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_12 ),\n .wr_level_start_r_reg(u_ddr_phy_init_n_790),\n .wrcal_done_reg(u_ddr_phy_wrcal_n_103),\n .wrcal_done_reg_0(u_ddr_phy_wrcal_n_83),\n .wrcal_done_reg_1(u_ddr_phy_wrcal_n_84),\n .wrcal_done_reg_10(u_ddr_phy_wrcal_n_82),\n .wrcal_done_reg_11(u_ddr_phy_wrcal_n_81),\n .wrcal_done_reg_2(u_ddr_phy_wrcal_n_104),\n .wrcal_done_reg_3(u_ddr_prbs_gen_n_34),\n .wrcal_done_reg_4(u_ddr_prbs_gen_n_33),\n .wrcal_done_reg_5(u_ddr_prbs_gen_n_32),\n .wrcal_done_reg_6(u_ddr_prbs_gen_n_31),\n .wrcal_done_reg_7(u_ddr_prbs_gen_n_30),\n .wrcal_done_reg_8(u_ddr_prbs_gen_n_29),\n .wrcal_done_reg_9(u_ddr_phy_wrcal_n_93),\n .\\wrcal_dqs_cnt_r_reg[0] (u_ddr_phy_init_n_784),\n .wrcal_prech_req(wrcal_prech_req),\n .wrcal_rd_wait(wrcal_rd_wait),\n .wrcal_resume_r(wrcal_resume_r),\n .wrcal_resume_w(wrcal_resume_w),\n .wrcal_sanity_chk(wrcal_sanity_chk),\n .wrcal_sanity_chk_done_reg(u_ddr_phy_wrcal_n_96),\n .wrcal_sanity_chk_done_reg_0(u_ddr_phy_wrcal_n_71),\n .wrcal_sanity_chk_r_reg(u_ddr_phy_wrcal_n_5),\n .wrcal_start_reg_0(u_ddr_phy_init_n_791),\n .\\write_buffer.wr_buf_out_data_reg[255] (Q[255:0]),\n .write_request_r_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_53 ),\n .wrlvl_byte_redo(wrlvl_byte_redo),\n .wrlvl_byte_redo_reg(u_ddr_phy_wrcal_n_95),\n .wrlvl_byte_redo_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_148 ),\n .wrlvl_done_r1(wrlvl_done_r1),\n .wrlvl_final_if_rst(wrlvl_final_if_rst),\n .wrlvl_final_mux(wrlvl_final_mux),\n .wrlvl_final_mux_reg(u_ddr_phy_wrcal_n_90),\n .wrlvl_final_mux_reg_0(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_84 ),\n .wrlvl_rank_done(wrlvl_rank_done));\n ddr3_ifmig_7series_v4_0_ddr_phy_wrcal u_ddr_phy_wrcal\n (.CLK(CLK),\n .\\FSM_sequential_wl_state_r_reg[0] (u_ddr_phy_wrcal_n_102),\n .LD0(LD0),\n .LD0_0(LD0_0),\n .LD0_1(LD0_1),\n .LD0_2(LD0_2),\n .Q(calib_zero_inputs__0),\n .cal2_done_r(cal2_done_r),\n .cal2_done_r_reg_0(u_ddr_phy_wrcal_n_117),\n .cal2_if_reset_reg_0(u_ddr_phy_wrcal_n_114),\n .cal2_if_reset_reg_1(u_ddr_phy_wrcal_n_115),\n .cal2_if_reset_reg_2(u_ddr_phy_wrcal_n_120),\n .\\cal2_state_r_reg[0]_0 (idelay_ld_done_i_1_n_0),\n .\\cal2_state_r_reg[0]_1 (cal2_if_reset_i_1_n_0),\n .\\cal2_state_r_reg[2]_0 (wrcal_pat_resume_r_i_1_n_0),\n .\\cal2_state_r_reg[3]_0 (wrcal_sanity_chk_done_i_2_n_0),\n .calib_in_common(calib_in_common),\n .\\calib_sel_reg[1] (\\po_rdval_cnt_reg[8] [1:0]),\n .\\corse_cnt_reg[0][2] (u_ddr_phy_wrcal_n_100),\n .\\corse_cnt_reg[1][2] (u_ddr_phy_wrcal_n_97),\n .\\corse_cnt_reg[2][2] (u_ddr_phy_wrcal_n_98),\n .ddr3_lm_done_r(ddr3_lm_done_r),\n .done_dqs_dec239_out(done_dqs_dec239_out),\n .dqs_found_done_r_reg(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_10 ),\n .dqs_found_done_r_reg_0(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_82 ),\n .early1_data_reg_0(u_ddr_phy_wrcal_n_67),\n .early1_data_reg_1(u_ddr_phy_wrcal_n_73),\n .early1_data_reg_2(u_ddr_phy_wrcal_n_119),\n .early2_data_reg_0(u_ddr_phy_wrcal_n_66),\n .early2_data_reg_1(u_ddr_phy_wrcal_n_74),\n .\\final_coarse_tap_reg[3][2] (final_coarse_tap),\n .first_wrcal_pat_r(first_wrcal_pat_r),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[0] (u_ddr_phy_wrcal_n_105),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[1] (u_ddr_phy_wrcal_n_106),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[2] (u_ddr_phy_wrcal_n_107),\n .\\gen_pat_match_div4.early1_data_match_r_reg_0 (early1_data_i_1_n_0),\n .\\gen_pat_match_div4.early1_data_match_r_reg_1 (early2_data_i_1_n_0),\n .\\gen_pat_match_div4.early2_data_match_r_reg_0 (wrlvl_byte_redo_i_1_n_0),\n .\\gen_pat_match_div4.pat_data_match_valid_r_reg_0 (idelay_ld_i_1_n_0),\n .\\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0][0]_0 (\\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 (\\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 ),\n .\\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0][0]_0 (\\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 (\\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 ),\n .\\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0][0]_0 (\\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 (\\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 ),\n .\\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0][0]_0 (\\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 (\\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 ),\n .\\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0][0]_0 (\\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 (\\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 ),\n .\\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0][0]_0 (\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 (\\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 ),\n .\\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0][0]_0 (\\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 (\\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 ),\n .\\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1][0]_0 (\\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 (\\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 ),\n .\\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1][0]_0 (\\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 (\\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 ),\n .\\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1][0]_0 (\\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 (\\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 ),\n .\\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1][0]_0 (\\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 (\\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 ),\n .\\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1][0]_0 (\\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 (\\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 ),\n .\\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1][0]_0 (\\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 (\\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 ),\n .\\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1][0]_0 (\\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 (\\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 ),\n .\\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1][0]_0 (\\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 (\\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 ),\n .\\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2][0]_0 (\\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 (\\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 ),\n .\\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2][0]_0 (\\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 (\\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 ),\n .\\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2][0]_0 (\\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 (\\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 ),\n .\\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2][0]_0 (\\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 (\\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 ),\n .\\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2][0]_0 (\\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 (\\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 ),\n .\\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2][0]_0 (\\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 (\\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 ),\n .\\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2][0]_0 (\\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 (\\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 ),\n .\\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2][0]_0 (\\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 (\\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 ),\n .\\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3][0]_0 (\\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 (\\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 ),\n .\\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3][0]_0 (\\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 (\\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 ),\n .\\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3][0]_0 (\\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 (\\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 ),\n .\\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3][0]_0 (\\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_208 (\\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_208 ),\n .\\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3][0]_0 (\\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 (\\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 ),\n .\\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3][0]_0 (\\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 (\\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 ),\n .\\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3][0]_0 (\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 (\\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 ),\n .\\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4][0]_0 (\\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 (\\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 ),\n .\\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4][0]_0 (\\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 (\\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 ),\n .\\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4][0]_0 (\\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 (\\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 ),\n .\\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4][0]_0 (\\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 (\\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 ),\n .\\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4][0]_0 (\\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 (\\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 ),\n .\\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4][0]_0 (\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 (\\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 ),\n .\\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4][0]_0 (\\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 (\\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 ),\n .\\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5][0]_0 (\\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 (\\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 ),\n .\\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5][0]_0 (\\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 (\\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 ),\n .\\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5][0]_0 (\\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 (\\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 ),\n .\\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5][0]_0 (\\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 (\\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 ),\n .\\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5][0]_0 (\\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 (\\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 ),\n .\\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5][0]_0 (\\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 (\\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 ),\n .\\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5][0]_0 (\\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 (\\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 ),\n .\\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5][0]_0 (\\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 (\\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 ),\n .\\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6][0]_0 (\\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 (\\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 ),\n .\\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6][0]_0 (\\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 (\\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 ),\n .\\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6][0]_0 (\\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 (\\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 ),\n .\\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6][0]_0 (\\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 (\\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 ),\n .\\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6][0]_0 (\\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 (\\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 ),\n .\\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6][0]_0 (\\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 (\\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 ),\n .\\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6][0]_0 (\\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 (\\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 ),\n .\\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6][0]_0 (\\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 (\\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 ),\n .\\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7][0]_0 (\\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 (\\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 ),\n .\\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7][0]_0 (\\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 (\\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 ),\n .\\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7][0]_0 (\\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 (\\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 ),\n .\\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7][0]_0 (\\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_212 (\\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_212 ),\n .\\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7][0]_0 (\\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 (\\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 ),\n .\\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7][0]_0 (\\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 (\\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 ),\n .\\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7][0]_0 (\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 (\\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 ),\n .idelay_ce_int(idelay_ce_int),\n .idelay_ld(idelay_ld),\n .idelay_ld_done_reg_0(u_ddr_phy_wrcal_n_113),\n .idelay_ld_reg_0(u_ddr_phy_wrcal_n_4),\n .idelay_ld_reg_1(u_ddr_phy_wrcal_n_116),\n .idelay_ld_rst(idelay_ld_rst),\n .idelay_ld_rst_3(idelay_ld_rst_3),\n .idelay_ld_rst_4(idelay_ld_rst_4),\n .idelay_ld_rst_5(idelay_ld_rst_5),\n .\\idelay_tap_cnt_r_reg[0][1][0] (u_ddr_phy_wrcal_n_89),\n .\\idelay_tap_cnt_r_reg[0][2][0] (u_ddr_phy_wrcal_n_85),\n .\\idelay_tap_cnt_r_reg[0][2][0]_0 ({po_stg2_wrcal_cnt,\\idelay_tap_cnt_r_reg[0][3][0] }),\n .\\init_state_r_reg[0] (u_ddr_phy_wrcal_n_90),\n .\\init_state_r_reg[0]_0 (u_ddr_phy_wrcal_n_93),\n .\\init_state_r_reg[0]_1 (u_ddr_phy_wrcal_n_94),\n .\\init_state_r_reg[0]_2 (u_ddr_phy_wrcal_n_96),\n .\\init_state_r_reg[2] (u_ddr_phy_wrcal_n_91),\n .\\init_state_r_reg[3] (u_ddr_phy_wrcal_n_81),\n .\\init_state_r_reg[4] (u_ddr_phy_wrcal_n_92),\n .\\init_state_r_reg[5] (u_ddr_phy_wrcal_n_95),\n .mem_init_done_r(mem_init_done_r),\n .mpr_last_byte_done(mpr_last_byte_done),\n .mpr_rdlvl_done_r_reg(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ),\n .\\not_empty_wait_cnt_reg[0]_0 ({u_ddr_phy_wrcal_n_108,u_ddr_phy_wrcal_n_109,u_ddr_phy_wrcal_n_110,u_ddr_phy_wrcal_n_111}),\n .oclkdelay_calib_done_r_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ),\n .oclkdelay_calib_done_r_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_150 ),\n .oclkdelay_center_calib_done_r_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_4 ),\n .p_0_out(p_0_out),\n .phy_if_reset_w(phy_if_reset_w),\n .phy_rddata_en_1(phy_rddata_en_1),\n .phy_rddata_en_r1_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_58 ),\n .\\po_stg2_wrcal_cnt_reg[1]_0 (\\po_stg2_wrcal_cnt_reg[1] ),\n .\\po_stg2_wrcal_cnt_reg[1]_1 (\\po_stg2_wrcal_cnt_reg[1]_0 ),\n .\\po_stg2_wrcal_cnt_reg[1]_10 (\\po_stg2_wrcal_cnt_reg[1]_9 ),\n .\\po_stg2_wrcal_cnt_reg[1]_11 (\\po_stg2_wrcal_cnt_reg[1]_10 ),\n .\\po_stg2_wrcal_cnt_reg[1]_12 (\\po_stg2_wrcal_cnt_reg[1]_11 ),\n .\\po_stg2_wrcal_cnt_reg[1]_13 (\\po_stg2_wrcal_cnt_reg[1]_12 ),\n .\\po_stg2_wrcal_cnt_reg[1]_14 (\\po_stg2_wrcal_cnt_reg[1]_13 ),\n .\\po_stg2_wrcal_cnt_reg[1]_15 (\\po_stg2_wrcal_cnt_reg[1]_14 ),\n .\\po_stg2_wrcal_cnt_reg[1]_16 (\\po_stg2_wrcal_cnt_reg[1]_15 ),\n .\\po_stg2_wrcal_cnt_reg[1]_17 (\\po_stg2_wrcal_cnt_reg[1]_16 ),\n .\\po_stg2_wrcal_cnt_reg[1]_18 (\\po_stg2_wrcal_cnt_reg[1]_17 ),\n .\\po_stg2_wrcal_cnt_reg[1]_19 (\\po_stg2_wrcal_cnt_reg[1]_18 ),\n .\\po_stg2_wrcal_cnt_reg[1]_2 (\\po_stg2_wrcal_cnt_reg[1]_1 ),\n .\\po_stg2_wrcal_cnt_reg[1]_20 (\\po_stg2_wrcal_cnt_reg[1]_19 ),\n .\\po_stg2_wrcal_cnt_reg[1]_21 (\\po_stg2_wrcal_cnt_reg[1]_20 ),\n .\\po_stg2_wrcal_cnt_reg[1]_22 (\\po_stg2_wrcal_cnt_reg[1]_21 ),\n .\\po_stg2_wrcal_cnt_reg[1]_23 (\\po_stg2_wrcal_cnt_reg[1]_22 ),\n .\\po_stg2_wrcal_cnt_reg[1]_24 (\\po_stg2_wrcal_cnt_reg[1]_23 ),\n .\\po_stg2_wrcal_cnt_reg[1]_25 (\\po_stg2_wrcal_cnt_reg[1]_24 ),\n .\\po_stg2_wrcal_cnt_reg[1]_26 (\\po_stg2_wrcal_cnt_reg[1]_25 ),\n .\\po_stg2_wrcal_cnt_reg[1]_27 (\\po_stg2_wrcal_cnt_reg[1]_26 ),\n .\\po_stg2_wrcal_cnt_reg[1]_28 (\\po_stg2_wrcal_cnt_reg[1]_27 ),\n .\\po_stg2_wrcal_cnt_reg[1]_29 (\\po_stg2_wrcal_cnt_reg[1]_28 ),\n .\\po_stg2_wrcal_cnt_reg[1]_3 (\\po_stg2_wrcal_cnt_reg[1]_2 ),\n .\\po_stg2_wrcal_cnt_reg[1]_30 (\\po_stg2_wrcal_cnt_reg[1]_29 ),\n .\\po_stg2_wrcal_cnt_reg[1]_31 (\\po_stg2_wrcal_cnt_reg[1]_30 ),\n .\\po_stg2_wrcal_cnt_reg[1]_32 (\\po_stg2_wrcal_cnt_reg[1]_31 ),\n .\\po_stg2_wrcal_cnt_reg[1]_33 (\\po_stg2_wrcal_cnt_reg[1]_32 ),\n .\\po_stg2_wrcal_cnt_reg[1]_34 (\\po_stg2_wrcal_cnt_reg[1]_33 ),\n .\\po_stg2_wrcal_cnt_reg[1]_35 (\\po_stg2_wrcal_cnt_reg[1]_34 ),\n .\\po_stg2_wrcal_cnt_reg[1]_36 (\\po_stg2_wrcal_cnt_reg[1]_35 ),\n .\\po_stg2_wrcal_cnt_reg[1]_37 (\\po_stg2_wrcal_cnt_reg[1]_36 ),\n .\\po_stg2_wrcal_cnt_reg[1]_38 (\\po_stg2_wrcal_cnt_reg[1]_37 ),\n .\\po_stg2_wrcal_cnt_reg[1]_39 (\\po_stg2_wrcal_cnt_reg[1]_38 ),\n .\\po_stg2_wrcal_cnt_reg[1]_4 (\\po_stg2_wrcal_cnt_reg[1]_3 ),\n .\\po_stg2_wrcal_cnt_reg[1]_40 (\\po_stg2_wrcal_cnt_reg[1]_39 ),\n .\\po_stg2_wrcal_cnt_reg[1]_41 (\\po_stg2_wrcal_cnt_reg[1]_40 ),\n .\\po_stg2_wrcal_cnt_reg[1]_42 (\\po_stg2_wrcal_cnt_reg[1]_41 ),\n .\\po_stg2_wrcal_cnt_reg[1]_43 (\\po_stg2_wrcal_cnt_reg[1]_42 ),\n .\\po_stg2_wrcal_cnt_reg[1]_44 (\\po_stg2_wrcal_cnt_reg[1]_43 ),\n .\\po_stg2_wrcal_cnt_reg[1]_45 (\\po_stg2_wrcal_cnt_reg[1]_44 ),\n .\\po_stg2_wrcal_cnt_reg[1]_46 (\\po_stg2_wrcal_cnt_reg[1]_45 ),\n .\\po_stg2_wrcal_cnt_reg[1]_47 (\\po_stg2_wrcal_cnt_reg[1]_46 ),\n .\\po_stg2_wrcal_cnt_reg[1]_48 (\\po_stg2_wrcal_cnt_reg[1]_47 ),\n .\\po_stg2_wrcal_cnt_reg[1]_49 (\\po_stg2_wrcal_cnt_reg[1]_48 ),\n .\\po_stg2_wrcal_cnt_reg[1]_5 (\\po_stg2_wrcal_cnt_reg[1]_4 ),\n .\\po_stg2_wrcal_cnt_reg[1]_50 (\\po_stg2_wrcal_cnt_reg[1]_49 ),\n .\\po_stg2_wrcal_cnt_reg[1]_51 (\\po_stg2_wrcal_cnt_reg[1]_50 ),\n .\\po_stg2_wrcal_cnt_reg[1]_52 (\\po_stg2_wrcal_cnt_reg[1]_51 ),\n .\\po_stg2_wrcal_cnt_reg[1]_53 (\\po_stg2_wrcal_cnt_reg[1]_52 ),\n .\\po_stg2_wrcal_cnt_reg[1]_54 (\\po_stg2_wrcal_cnt_reg[1]_53 ),\n .\\po_stg2_wrcal_cnt_reg[1]_55 (\\po_stg2_wrcal_cnt_reg[1]_54 ),\n .\\po_stg2_wrcal_cnt_reg[1]_56 (\\po_stg2_wrcal_cnt_reg[1]_55 ),\n .\\po_stg2_wrcal_cnt_reg[1]_57 (\\po_stg2_wrcal_cnt_reg[1]_56 ),\n .\\po_stg2_wrcal_cnt_reg[1]_58 (\\po_stg2_wrcal_cnt_reg[1]_57 ),\n .\\po_stg2_wrcal_cnt_reg[1]_59 (\\po_stg2_wrcal_cnt_reg[1]_58 ),\n .\\po_stg2_wrcal_cnt_reg[1]_6 (\\po_stg2_wrcal_cnt_reg[1]_5 ),\n .\\po_stg2_wrcal_cnt_reg[1]_60 (\\po_stg2_wrcal_cnt_reg[1]_59 ),\n .\\po_stg2_wrcal_cnt_reg[1]_61 (\\po_stg2_wrcal_cnt_reg[1]_60 ),\n .\\po_stg2_wrcal_cnt_reg[1]_62 (\\po_stg2_wrcal_cnt_reg[1]_61 ),\n .\\po_stg2_wrcal_cnt_reg[1]_7 (\\po_stg2_wrcal_cnt_reg[1]_6 ),\n .\\po_stg2_wrcal_cnt_reg[1]_8 (\\po_stg2_wrcal_cnt_reg[1]_7 ),\n .\\po_stg2_wrcal_cnt_reg[1]_9 (\\po_stg2_wrcal_cnt_reg[1]_8 ),\n .\\prbs_dqs_cnt_r_reg[0] (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_9 ),\n .\\prbs_dqs_cnt_r_reg[1] (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_10 ),\n .prbs_rdlvl_done_reg(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_45 ),\n .prbs_rdlvl_done_reg_rep(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_51 ),\n .prbs_rdlvl_done_reg_rep_0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_89 ),\n .prech_done(prech_done),\n .prech_req_posedge_r_reg(u_ddr_phy_init_n_9),\n .rd_active_r1(rd_active_r1),\n .rd_active_r2(rd_active_r2),\n .rdlvl_stg1_done_int_reg(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_56 ),\n .rdlvl_stg1_done_int_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_152 ),\n .rdlvl_stg1_start_int_reg(u_ddr_phy_init_n_475),\n .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2),\n .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22),\n .rstdiv0_sync_r1_reg_rep__4(rstdiv0_sync_r1_reg_rep__4),\n .rstdiv0_sync_r1_reg_rep__5(rstdiv0_sync_r1_reg_rep__5),\n .rstdiv0_sync_r1_reg_rep__6(rstdiv0_sync_r1_reg_rep__6),\n .wl_sm_start(wl_sm_start),\n .wrcal_done_reg_0(u_ddr_phy_wrcal_n_5),\n .wrcal_done_reg_1(u_ddr_phy_wrcal_n_82),\n .wrcal_pat_resume_r(wrcal_pat_resume_r),\n .wrcal_pat_resume_r_reg_0(u_ddr_phy_wrcal_n_69),\n .wrcal_pat_resume_r_reg_1(u_ddr_phy_wrcal_n_112),\n .wrcal_prech_req(wrcal_prech_req),\n .wrcal_rd_wait(wrcal_rd_wait),\n .wrcal_resume_r(wrcal_resume_r),\n .wrcal_resume_w(wrcal_resume_w),\n .wrcal_sanity_chk(wrcal_sanity_chk),\n .wrcal_sanity_chk_done_reg_0(u_ddr_phy_wrcal_n_71),\n .wrcal_sanity_chk_r_reg_0(cal2_done_r_i_1_n_0),\n .wrcal_sanity_chk_reg(u_ddr_phy_init_n_784),\n .wrcal_start_reg(u_ddr_phy_init_n_791),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] (u_ddr_phy_wrcal_n_84),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] (u_ddr_phy_wrcal_n_104),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] (u_ddr_phy_wrcal_n_103),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] (u_ddr_phy_wrcal_n_83),\n .wrlvl_byte_done(wrlvl_byte_done),\n .wrlvl_byte_redo(wrlvl_byte_redo),\n .wrlvl_byte_redo_r(wrlvl_byte_redo_r),\n .wrlvl_byte_redo_reg_0(u_ddr_phy_wrcal_n_118),\n .wrlvl_done_r1(wrlvl_done_r1),\n .wrlvl_final_mux(wrlvl_final_mux),\n .\\wrlvl_redo_corse_inc_reg[2] (u_ddr_phy_wrcal_n_101));\n ddr3_ifmig_7series_v4_0_ddr_prbs_gen u_ddr_prbs_gen\n (.CLK(CLK),\n .D({sel,u_ddr_phy_init_n_120,u_ddr_phy_init_n_121,u_ddr_phy_init_n_122,u_ddr_phy_init_n_123,u_ddr_phy_init_n_124,u_ddr_phy_init_n_125,u_ddr_phy_init_n_126}),\n .E(u_ddr_phy_init_n_786),\n .Q(u_ddr_prbs_gen_n_57),\n .SR(\\rd_addr[7]_i_1_n_0 ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ),\n .first_rdlvl_pat_r(first_rdlvl_pat_r),\n .\\gen_mux_rd[0].compare_data_fall0_r1_reg[0] (u_ddr_prbs_gen_n_66),\n .\\gen_mux_rd[0].compare_data_fall1_r1_reg[0] (u_ddr_prbs_gen_n_82),\n .\\gen_mux_rd[0].compare_data_fall2_r1_reg[0] (u_ddr_prbs_gen_n_98),\n .\\gen_mux_rd[0].compare_data_fall3_r1_reg[0] (u_ddr_prbs_gen_n_114),\n .\\gen_mux_rd[0].compare_data_rise0_r1_reg[0] (u_ddr_prbs_gen_n_58),\n .\\gen_mux_rd[0].compare_data_rise1_r1_reg[0] (u_ddr_prbs_gen_n_74),\n .\\gen_mux_rd[0].compare_data_rise2_r1_reg[0] (u_ddr_prbs_gen_n_90),\n .\\gen_mux_rd[0].compare_data_rise3_r1_reg[0] (u_ddr_prbs_gen_n_106),\n .\\gen_mux_rd[1].compare_data_fall0_r1_reg[1] (u_ddr_prbs_gen_n_67),\n .\\gen_mux_rd[1].compare_data_fall1_r1_reg[1] (u_ddr_prbs_gen_n_83),\n .\\gen_mux_rd[1].compare_data_fall2_r1_reg[1] (u_ddr_prbs_gen_n_99),\n .\\gen_mux_rd[1].compare_data_fall3_r1_reg[1] (u_ddr_prbs_gen_n_115),\n .\\gen_mux_rd[1].compare_data_rise0_r1_reg[1] (u_ddr_prbs_gen_n_59),\n .\\gen_mux_rd[1].compare_data_rise1_r1_reg[1] (u_ddr_prbs_gen_n_75),\n .\\gen_mux_rd[1].compare_data_rise2_r1_reg[1] (u_ddr_prbs_gen_n_91),\n .\\gen_mux_rd[1].compare_data_rise3_r1_reg[1] (u_ddr_prbs_gen_n_107),\n .\\gen_mux_rd[2].compare_data_fall0_r1_reg[2] (u_ddr_prbs_gen_n_68),\n .\\gen_mux_rd[2].compare_data_fall2_r1_reg[2] (u_ddr_prbs_gen_n_100),\n .\\gen_mux_rd[2].compare_data_fall3_r1_reg[2] (u_ddr_prbs_gen_n_116),\n .\\gen_mux_rd[2].compare_data_rise0_r1_reg[2] (u_ddr_prbs_gen_n_60),\n .\\gen_mux_rd[2].compare_data_rise1_r1_reg[2] (u_ddr_prbs_gen_n_76),\n .\\gen_mux_rd[2].compare_data_rise2_r1_reg[2] (u_ddr_prbs_gen_n_92),\n .\\gen_mux_rd[2].compare_data_rise3_r1_reg[2] (u_ddr_prbs_gen_n_108),\n .\\gen_mux_rd[3].compare_data_fall0_r1_reg[3] (u_ddr_prbs_gen_n_69),\n .\\gen_mux_rd[3].compare_data_fall1_r1_reg[3] (u_ddr_prbs_gen_n_85),\n .\\gen_mux_rd[3].compare_data_fall3_r1_reg[3] (u_ddr_prbs_gen_n_117),\n .\\gen_mux_rd[3].compare_data_rise0_r1_reg[3] (u_ddr_prbs_gen_n_61),\n .\\gen_mux_rd[3].compare_data_rise1_r1_reg[3] (u_ddr_prbs_gen_n_77),\n .\\gen_mux_rd[3].compare_data_rise2_r1_reg[3] (u_ddr_prbs_gen_n_93),\n .\\gen_mux_rd[3].compare_data_rise3_r1_reg[3] (u_ddr_prbs_gen_n_109),\n .\\gen_mux_rd[4].compare_data_fall0_r1_reg[4] (u_ddr_prbs_gen_n_70),\n .\\gen_mux_rd[4].compare_data_fall1_r1_reg[4] (u_ddr_prbs_gen_n_86),\n .\\gen_mux_rd[4].compare_data_fall2_r1_reg[4] (u_ddr_prbs_gen_n_102),\n .\\gen_mux_rd[4].compare_data_fall3_r1_reg[4] (u_ddr_prbs_gen_n_118),\n .\\gen_mux_rd[4].compare_data_rise0_r1_reg[4] (u_ddr_prbs_gen_n_62),\n .\\gen_mux_rd[4].compare_data_rise1_r1_reg[4] (u_ddr_prbs_gen_n_78),\n .\\gen_mux_rd[4].compare_data_rise2_r1_reg[4] (u_ddr_prbs_gen_n_94),\n .\\gen_mux_rd[4].compare_data_rise3_r1_reg[4] (u_ddr_prbs_gen_n_110),\n .\\gen_mux_rd[5].compare_data_fall0_r1_reg[5] (u_ddr_prbs_gen_n_71),\n .\\gen_mux_rd[5].compare_data_fall1_r1_reg[5] (u_ddr_prbs_gen_n_87),\n .\\gen_mux_rd[5].compare_data_fall2_r1_reg[5] (u_ddr_prbs_gen_n_103),\n .\\gen_mux_rd[5].compare_data_fall3_r1_reg[5] (u_ddr_prbs_gen_n_119),\n .\\gen_mux_rd[5].compare_data_rise0_r1_reg[5] (u_ddr_prbs_gen_n_63),\n .\\gen_mux_rd[5].compare_data_rise1_r1_reg[5] (u_ddr_prbs_gen_n_79),\n .\\gen_mux_rd[5].compare_data_rise2_r1_reg[5] (u_ddr_prbs_gen_n_95),\n .\\gen_mux_rd[5].compare_data_rise3_r1_reg[5] (u_ddr_prbs_gen_n_111),\n .\\gen_mux_rd[6].compare_data_fall0_r1_reg[6] (u_ddr_prbs_gen_n_72),\n .\\gen_mux_rd[6].compare_data_fall2_r1_reg[6] (u_ddr_prbs_gen_n_104),\n .\\gen_mux_rd[6].compare_data_fall3_r1_reg[6] (u_ddr_prbs_gen_n_120),\n .\\gen_mux_rd[6].compare_data_rise0_r1_reg[6] (u_ddr_prbs_gen_n_64),\n .\\gen_mux_rd[6].compare_data_rise1_r1_reg[6] (u_ddr_prbs_gen_n_80),\n .\\gen_mux_rd[6].compare_data_rise2_r1_reg[6] (u_ddr_prbs_gen_n_96),\n .\\gen_mux_rd[6].compare_data_rise3_r1_reg[6] (u_ddr_prbs_gen_n_112),\n .\\gen_mux_rd[7].compare_data_fall0_r1_reg[7] (u_ddr_prbs_gen_n_73),\n .\\gen_mux_rd[7].compare_data_fall1_r1_reg[7] (u_ddr_prbs_gen_n_89),\n .\\gen_mux_rd[7].compare_data_fall3_r1_reg[7] (u_ddr_prbs_gen_n_121),\n .\\gen_mux_rd[7].compare_data_rise0_r1_reg[7] (u_ddr_prbs_gen_n_65),\n .\\gen_mux_rd[7].compare_data_rise1_r1_reg[7] (u_ddr_prbs_gen_n_81),\n .\\gen_mux_rd[7].compare_data_rise2_r1_reg[7] (u_ddr_prbs_gen_n_97),\n .\\gen_mux_rd[7].compare_data_rise3_r1_reg[7] (u_ddr_prbs_gen_n_113),\n .oclkdelay_calib_done_r_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ),\n .\\rd_addr_reg[0]_0 (u_ddr_prbs_gen_n_0),\n .\\rd_addr_reg[3]_0 (u_ddr_phy_init_n_785),\n .rdlvl_stg1_done_int_reg(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_56 ),\n .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),\n .wrcal_done_reg(u_ddr_phy_wrcal_n_82),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[120] (u_ddr_prbs_gen_n_1),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[121] (u_ddr_prbs_gen_n_29),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[122] (u_ddr_prbs_gen_n_84),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[123] (u_ddr_prbs_gen_n_30),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[124] (u_ddr_prbs_gen_n_2),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[125] (u_ddr_prbs_gen_n_31),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[126] (u_ddr_prbs_gen_n_88),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[127] (u_ddr_prbs_gen_n_32),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[152] (u_ddr_prbs_gen_n_22),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[153] (u_ddr_prbs_gen_n_42),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[154] (u_ddr_prbs_gen_n_15),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[155] (u_ddr_prbs_gen_n_52),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[156] (u_ddr_prbs_gen_n_21),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[157] (u_ddr_prbs_gen_n_41),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[158] (u_ddr_prbs_gen_n_16),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[159] (u_ddr_prbs_gen_n_51),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[184] (u_ddr_prbs_gen_n_33),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[185] (u_ddr_prbs_gen_n_39),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] (u_ddr_prbs_gen_n_5),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187] (u_ddr_prbs_gen_n_101),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[188] (u_ddr_prbs_gen_n_34),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[189] (u_ddr_prbs_gen_n_40),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[190] (u_ddr_prbs_gen_n_6),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] (u_ddr_prbs_gen_n_105),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[216] (u_ddr_prbs_gen_n_35),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[217] (u_ddr_prbs_gen_n_50),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[218] (u_ddr_prbs_gen_n_20),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[219] (u_ddr_prbs_gen_n_36),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[220] (u_ddr_prbs_gen_n_37),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] (u_ddr_prbs_gen_n_49),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[222] (u_ddr_prbs_gen_n_19),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[223] (u_ddr_prbs_gen_n_38),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[248] (u_ddr_prbs_gen_n_47),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[249] (u_ddr_prbs_gen_n_3),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[24] (u_ddr_prbs_gen_n_9),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[251] (u_ddr_prbs_gen_n_7),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[252] (u_ddr_prbs_gen_n_48),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[253] (u_ddr_prbs_gen_n_4),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[255] (u_ddr_prbs_gen_n_8),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[25] (u_ddr_prbs_gen_n_23),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[26] (u_ddr_prbs_gen_n_26),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[27] (u_ddr_prbs_gen_n_10),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[28] (u_ddr_prbs_gen_n_11),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[29] (u_ddr_prbs_gen_n_24),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[30] (u_ddr_prbs_gen_n_25),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[31] (u_ddr_prbs_gen_n_12),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] (u_ddr_prbs_gen_n_55),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[58] (u_ddr_prbs_gen_n_43),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[59] (u_ddr_prbs_gen_n_44),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[61] (u_ddr_prbs_gen_n_56),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[62] (u_ddr_prbs_gen_n_45),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[63] (u_ddr_prbs_gen_n_46),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[88] (u_ddr_prbs_gen_n_54),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[89] (u_ddr_prbs_gen_n_13),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[90] (u_ddr_prbs_gen_n_17),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] (u_ddr_prbs_gen_n_27),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[92] (u_ddr_prbs_gen_n_53),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[93] (u_ddr_prbs_gen_n_14),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[94] (u_ddr_prbs_gen_n_18),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[95] (u_ddr_prbs_gen_n_28));\n LUT6 #(\n .INIT(64'hEEBAFFFF00001000)) \n wl_edge_detect_valid_r_i_1\n (.I0(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_29 ),\n .I1(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_30 ),\n .I2(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_28 ),\n .I3(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_27 ),\n .I4(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_31 ),\n .I5(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_8 ),\n .O(wl_edge_detect_valid_r_i_1_n_0));\n LUT5 #(\n .INIT(32'hA2A200A2)) \n wr_level_done_i_1\n (.I0(done_dqs_tap_inc),\n .I1(wrlvl_final_mux),\n .I2(wrlvl_final_r),\n .I3(wrlvl_byte_redo),\n .I4(wrlvl_byte_redo_r),\n .O(wr_level_done_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFFFF0200000002)) \n wr_level_done_r_i_1\n (.I0(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_31 ),\n .I1(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_41 ),\n .I2(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_42 ),\n .I3(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_29 ),\n .I4(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_54 ),\n .I5(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_0 ),\n .O(wr_level_done_r_i_1_n_0));\n LUT5 #(\n .INIT(32'hF8FFF800)) \n wrcal_pat_resume_r_i_1\n (.I0(u_ddr_phy_wrcal_n_109),\n .I1(u_ddr_phy_wrcal_n_69),\n .I2(u_ddr_phy_wrcal_n_110),\n .I3(u_ddr_phy_wrcal_n_112),\n .I4(wrcal_pat_resume_r),\n .O(wrcal_pat_resume_r_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFF00004000)) \n wrcal_sanity_chk_done_i_2\n (.I0(u_ddr_phy_wrcal_n_108),\n .I1(u_ddr_phy_wrcal_n_109),\n .I2(u_ddr_phy_wrcal_n_5),\n .I3(u_ddr_phy_wrcal_n_110),\n .I4(u_ddr_phy_wrcal_n_111),\n .I5(u_ddr_phy_wrcal_n_71),\n .O(wrcal_sanity_chk_done_i_2_n_0));\n LUT6 #(\n .INIT(64'h0EFFFFFF0E000000)) \n wrlvl_byte_redo_i_1\n (.I0(u_ddr_phy_wrcal_n_66),\n .I1(u_ddr_phy_wrcal_n_67),\n .I2(u_ddr_phy_wrcal_n_110),\n .I3(u_ddr_phy_wrcal_n_118),\n .I4(u_ddr_phy_wrcal_n_111),\n .I5(wrlvl_byte_redo),\n .O(wrlvl_byte_redo_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n wrlvl_final_mux_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ),\n .Q(wrlvl_final_mux),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h40FF4000)) \n wrlvl_rank_done_r_i_1\n (.I0(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_29 ),\n .I1(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_31 ),\n .I2(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_27 ),\n .I3(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_55 ),\n .I4(wrlvl_rank_done),\n .O(wrlvl_rank_done_r_i_1_n_0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_if_post_fifo\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_if_post_fifo\n (\\not_strict_mode.app_rd_data_reg[228] ,\n \\not_strict_mode.app_rd_data_reg[231] ,\n \\not_strict_mode.app_rd_data_reg[0] ,\n \\not_strict_mode.app_rd_data_reg[1] ,\n \\not_strict_mode.app_rd_data_reg[2] ,\n \\not_strict_mode.app_rd_data_reg[3] ,\n \\not_strict_mode.app_rd_data_reg[4] ,\n \\not_strict_mode.app_rd_data_reg[5] ,\n \\not_strict_mode.app_rd_data_reg[6] ,\n \\not_strict_mode.app_rd_data_reg[7] ,\n \\not_strict_mode.app_rd_data_reg[32] ,\n \\not_strict_mode.app_rd_data_reg[33] ,\n \\not_strict_mode.app_rd_data_reg[34] ,\n \\not_strict_mode.app_rd_data_reg[35] ,\n \\not_strict_mode.app_rd_data_reg[36] ,\n \\not_strict_mode.app_rd_data_reg[37] ,\n \\not_strict_mode.app_rd_data_reg[38] ,\n \\not_strict_mode.app_rd_data_reg[39] ,\n \\not_strict_mode.app_rd_data_reg[64] ,\n \\not_strict_mode.app_rd_data_reg[65] ,\n \\not_strict_mode.app_rd_data_reg[66] ,\n \\not_strict_mode.app_rd_data_reg[67] ,\n \\not_strict_mode.app_rd_data_reg[68] ,\n \\not_strict_mode.app_rd_data_reg[69] ,\n \\not_strict_mode.app_rd_data_reg[70] ,\n \\not_strict_mode.app_rd_data_reg[71] ,\n \\not_strict_mode.app_rd_data_reg[96] ,\n \\not_strict_mode.app_rd_data_reg[97] ,\n \\not_strict_mode.app_rd_data_reg[98] ,\n \\not_strict_mode.app_rd_data_reg[99] ,\n \\not_strict_mode.app_rd_data_reg[100] ,\n \\not_strict_mode.app_rd_data_reg[101] ,\n \\not_strict_mode.app_rd_data_reg[102] ,\n \\not_strict_mode.app_rd_data_reg[103] ,\n \\not_strict_mode.app_rd_data_reg[128] ,\n \\not_strict_mode.app_rd_data_reg[129] ,\n \\not_strict_mode.app_rd_data_reg[130] ,\n \\not_strict_mode.app_rd_data_reg[131] ,\n \\not_strict_mode.app_rd_data_reg[132] ,\n \\not_strict_mode.app_rd_data_reg[133] ,\n \\not_strict_mode.app_rd_data_reg[134] ,\n \\not_strict_mode.app_rd_data_reg[135] ,\n \\not_strict_mode.app_rd_data_reg[160] ,\n \\not_strict_mode.app_rd_data_reg[161] ,\n \\not_strict_mode.app_rd_data_reg[162] ,\n \\not_strict_mode.app_rd_data_reg[163] ,\n \\not_strict_mode.app_rd_data_reg[164] ,\n \\not_strict_mode.app_rd_data_reg[165] ,\n \\not_strict_mode.app_rd_data_reg[166] ,\n \\not_strict_mode.app_rd_data_reg[167] ,\n \\not_strict_mode.app_rd_data_reg[192] ,\n \\not_strict_mode.app_rd_data_reg[193] ,\n \\not_strict_mode.app_rd_data_reg[194] ,\n \\not_strict_mode.app_rd_data_reg[195] ,\n \\not_strict_mode.app_rd_data_reg[196] ,\n \\not_strict_mode.app_rd_data_reg[197] ,\n \\not_strict_mode.app_rd_data_reg[198] ,\n \\not_strict_mode.app_rd_data_reg[199] ,\n \\not_strict_mode.app_rd_data_reg[224] ,\n \\not_strict_mode.app_rd_data_reg[225] ,\n \\not_strict_mode.app_rd_data_reg[226] ,\n \\not_strict_mode.app_rd_data_reg[227] ,\n \\not_strict_mode.app_rd_data_reg[228]_0 ,\n \\not_strict_mode.app_rd_data_reg[229] ,\n \\not_strict_mode.app_rd_data_reg[230] ,\n \\not_strict_mode.app_rd_data_reg[231]_0 ,\n mux_rd_valid_r_reg,\n \\not_strict_mode.app_rd_data_reg[7]_0 ,\n D_byte_rd_en,\n ififo_rst,\n CLK,\n if_empty_r_1,\n \\read_fifo.fifo_out_data_r_reg[6] ,\n DOC,\n DOB,\n DOA,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,\n \\my_empty_reg[4]_0 ,\n if_empty_r,\n Q,\n C_byte_rd_en,\n A_byte_rd_en,\n if_empty_r_0,\n \\my_empty_reg[4]_1 );\n output \\not_strict_mode.app_rd_data_reg[228] ;\n output [63:0]\\not_strict_mode.app_rd_data_reg[231] ;\n output \\not_strict_mode.app_rd_data_reg[0] ;\n output \\not_strict_mode.app_rd_data_reg[1] ;\n output \\not_strict_mode.app_rd_data_reg[2] ;\n output \\not_strict_mode.app_rd_data_reg[3] ;\n output \\not_strict_mode.app_rd_data_reg[4] ;\n output \\not_strict_mode.app_rd_data_reg[5] ;\n output \\not_strict_mode.app_rd_data_reg[6] ;\n output \\not_strict_mode.app_rd_data_reg[7] ;\n output \\not_strict_mode.app_rd_data_reg[32] ;\n output \\not_strict_mode.app_rd_data_reg[33] ;\n output \\not_strict_mode.app_rd_data_reg[34] ;\n output \\not_strict_mode.app_rd_data_reg[35] ;\n output \\not_strict_mode.app_rd_data_reg[36] ;\n output \\not_strict_mode.app_rd_data_reg[37] ;\n output \\not_strict_mode.app_rd_data_reg[38] ;\n output \\not_strict_mode.app_rd_data_reg[39] ;\n output \\not_strict_mode.app_rd_data_reg[64] ;\n output \\not_strict_mode.app_rd_data_reg[65] ;\n output \\not_strict_mode.app_rd_data_reg[66] ;\n output \\not_strict_mode.app_rd_data_reg[67] ;\n output \\not_strict_mode.app_rd_data_reg[68] ;\n output \\not_strict_mode.app_rd_data_reg[69] ;\n output \\not_strict_mode.app_rd_data_reg[70] ;\n output \\not_strict_mode.app_rd_data_reg[71] ;\n output \\not_strict_mode.app_rd_data_reg[96] ;\n output \\not_strict_mode.app_rd_data_reg[97] ;\n output \\not_strict_mode.app_rd_data_reg[98] ;\n output \\not_strict_mode.app_rd_data_reg[99] ;\n output \\not_strict_mode.app_rd_data_reg[100] ;\n output \\not_strict_mode.app_rd_data_reg[101] ;\n output \\not_strict_mode.app_rd_data_reg[102] ;\n output \\not_strict_mode.app_rd_data_reg[103] ;\n output \\not_strict_mode.app_rd_data_reg[128] ;\n output \\not_strict_mode.app_rd_data_reg[129] ;\n output \\not_strict_mode.app_rd_data_reg[130] ;\n output \\not_strict_mode.app_rd_data_reg[131] ;\n output \\not_strict_mode.app_rd_data_reg[132] ;\n output \\not_strict_mode.app_rd_data_reg[133] ;\n output \\not_strict_mode.app_rd_data_reg[134] ;\n output \\not_strict_mode.app_rd_data_reg[135] ;\n output \\not_strict_mode.app_rd_data_reg[160] ;\n output \\not_strict_mode.app_rd_data_reg[161] ;\n output \\not_strict_mode.app_rd_data_reg[162] ;\n output \\not_strict_mode.app_rd_data_reg[163] ;\n output \\not_strict_mode.app_rd_data_reg[164] ;\n output \\not_strict_mode.app_rd_data_reg[165] ;\n output \\not_strict_mode.app_rd_data_reg[166] ;\n output \\not_strict_mode.app_rd_data_reg[167] ;\n output \\not_strict_mode.app_rd_data_reg[192] ;\n output \\not_strict_mode.app_rd_data_reg[193] ;\n output \\not_strict_mode.app_rd_data_reg[194] ;\n output \\not_strict_mode.app_rd_data_reg[195] ;\n output \\not_strict_mode.app_rd_data_reg[196] ;\n output \\not_strict_mode.app_rd_data_reg[197] ;\n output \\not_strict_mode.app_rd_data_reg[198] ;\n output \\not_strict_mode.app_rd_data_reg[199] ;\n output \\not_strict_mode.app_rd_data_reg[224] ;\n output \\not_strict_mode.app_rd_data_reg[225] ;\n output \\not_strict_mode.app_rd_data_reg[226] ;\n output \\not_strict_mode.app_rd_data_reg[227] ;\n output \\not_strict_mode.app_rd_data_reg[228]_0 ;\n output \\not_strict_mode.app_rd_data_reg[229] ;\n output \\not_strict_mode.app_rd_data_reg[230] ;\n output \\not_strict_mode.app_rd_data_reg[231]_0 ;\n output mux_rd_valid_r_reg;\n output [0:0]\\not_strict_mode.app_rd_data_reg[7]_0 ;\n output D_byte_rd_en;\n input ififo_rst;\n input CLK;\n input [0:0]if_empty_r_1;\n input \\read_fifo.fifo_out_data_r_reg[6] ;\n input [1:0]DOC;\n input [1:0]DOB;\n input [1:0]DOA;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n input [0:0]\\my_empty_reg[4]_0 ;\n input [0:0]if_empty_r;\n input [65:0]Q;\n input C_byte_rd_en;\n input A_byte_rd_en;\n input [0:0]if_empty_r_0;\n input [0:0]\\my_empty_reg[4]_1 ;\n\n wire A_byte_rd_en;\n wire CLK;\n wire C_byte_rd_en;\n wire [1:0]DOA;\n wire [1:0]DOB;\n wire [1:0]DOC;\n wire D_byte_rd_en;\n wire [65:0]Q;\n wire [0:0]if_empty_r;\n wire [0:0]if_empty_r_0;\n wire [0:0]if_empty_r_1;\n wire ififo_rst;\n wire [71:9]mem_out;\n wire mem_reg_0_3_6_11_n_0;\n wire mem_reg_0_3_6_11_n_1;\n wire mux_rd_valid_r_reg;\n wire [3:0]my_empty;\n wire \\my_empty[4]_i_1_n_0 ;\n wire \\my_empty[4]_i_2__2_n_0 ;\n wire [0:0]\\my_empty_reg[4]_0 ;\n wire [0:0]\\my_empty_reg[4]_1 ;\n wire \\my_empty_reg[4]_rep__0_n_0 ;\n wire \\my_empty_reg[4]_rep_n_0 ;\n wire [1:0]my_full;\n wire \\my_full[0]_i_1__2_n_0 ;\n wire \\my_full[0]_i_2__2_n_0 ;\n wire \\my_full[1]_i_1__2_n_0 ;\n wire \\my_full[1]_i_2__2_n_0 ;\n wire \\not_strict_mode.app_rd_data_reg[0] ;\n wire \\not_strict_mode.app_rd_data_reg[100] ;\n wire \\not_strict_mode.app_rd_data_reg[101] ;\n wire \\not_strict_mode.app_rd_data_reg[102] ;\n wire \\not_strict_mode.app_rd_data_reg[103] ;\n wire \\not_strict_mode.app_rd_data_reg[128] ;\n wire \\not_strict_mode.app_rd_data_reg[129] ;\n wire \\not_strict_mode.app_rd_data_reg[130] ;\n wire \\not_strict_mode.app_rd_data_reg[131] ;\n wire \\not_strict_mode.app_rd_data_reg[132] ;\n wire \\not_strict_mode.app_rd_data_reg[133] ;\n wire \\not_strict_mode.app_rd_data_reg[134] ;\n wire \\not_strict_mode.app_rd_data_reg[135] ;\n wire \\not_strict_mode.app_rd_data_reg[160] ;\n wire \\not_strict_mode.app_rd_data_reg[161] ;\n wire \\not_strict_mode.app_rd_data_reg[162] ;\n wire \\not_strict_mode.app_rd_data_reg[163] ;\n wire \\not_strict_mode.app_rd_data_reg[164] ;\n wire \\not_strict_mode.app_rd_data_reg[165] ;\n wire \\not_strict_mode.app_rd_data_reg[166] ;\n wire \\not_strict_mode.app_rd_data_reg[167] ;\n wire \\not_strict_mode.app_rd_data_reg[192] ;\n wire \\not_strict_mode.app_rd_data_reg[193] ;\n wire \\not_strict_mode.app_rd_data_reg[194] ;\n wire \\not_strict_mode.app_rd_data_reg[195] ;\n wire \\not_strict_mode.app_rd_data_reg[196] ;\n wire \\not_strict_mode.app_rd_data_reg[197] ;\n wire \\not_strict_mode.app_rd_data_reg[198] ;\n wire \\not_strict_mode.app_rd_data_reg[199] ;\n wire \\not_strict_mode.app_rd_data_reg[1] ;\n wire \\not_strict_mode.app_rd_data_reg[224] ;\n wire \\not_strict_mode.app_rd_data_reg[225] ;\n wire \\not_strict_mode.app_rd_data_reg[226] ;\n wire \\not_strict_mode.app_rd_data_reg[227] ;\n wire \\not_strict_mode.app_rd_data_reg[228] ;\n wire \\not_strict_mode.app_rd_data_reg[228]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[229] ;\n wire \\not_strict_mode.app_rd_data_reg[230] ;\n wire [63:0]\\not_strict_mode.app_rd_data_reg[231] ;\n wire \\not_strict_mode.app_rd_data_reg[231]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[2] ;\n wire \\not_strict_mode.app_rd_data_reg[32] ;\n wire \\not_strict_mode.app_rd_data_reg[33] ;\n wire \\not_strict_mode.app_rd_data_reg[34] ;\n wire \\not_strict_mode.app_rd_data_reg[35] ;\n wire \\not_strict_mode.app_rd_data_reg[36] ;\n wire \\not_strict_mode.app_rd_data_reg[37] ;\n wire \\not_strict_mode.app_rd_data_reg[38] ;\n wire \\not_strict_mode.app_rd_data_reg[39] ;\n wire \\not_strict_mode.app_rd_data_reg[3] ;\n wire \\not_strict_mode.app_rd_data_reg[4] ;\n wire \\not_strict_mode.app_rd_data_reg[5] ;\n wire \\not_strict_mode.app_rd_data_reg[64] ;\n wire \\not_strict_mode.app_rd_data_reg[65] ;\n wire \\not_strict_mode.app_rd_data_reg[66] ;\n wire \\not_strict_mode.app_rd_data_reg[67] ;\n wire \\not_strict_mode.app_rd_data_reg[68] ;\n wire \\not_strict_mode.app_rd_data_reg[69] ;\n wire \\not_strict_mode.app_rd_data_reg[6] ;\n wire \\not_strict_mode.app_rd_data_reg[70] ;\n wire \\not_strict_mode.app_rd_data_reg[71] ;\n wire \\not_strict_mode.app_rd_data_reg[7] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[7]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[96] ;\n wire \\not_strict_mode.app_rd_data_reg[97] ;\n wire \\not_strict_mode.app_rd_data_reg[98] ;\n wire \\not_strict_mode.app_rd_data_reg[99] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n wire \\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ;\n wire [1:0]rd_ptr;\n wire \\rd_ptr[0]_i_1__2_n_0 ;\n wire \\rd_ptr[1]_i_1__2_n_0 ;\n (* RTL_KEEP = \"true\" *) (* syn_maxfan = \"10\" *) wire [1:0]rd_ptr_timing;\n wire \\rd_ptr_timing[0]_i_1__6_n_0 ;\n wire \\rd_ptr_timing[1]_i_1__7_n_0 ;\n wire \\read_fifo.fifo_out_data_r_reg[6] ;\n (* MAX_FANOUT = \"40\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire wr_en;\n wire [1:0]wr_ptr;\n wire \\wr_ptr[0]_i_1__8_n_0 ;\n wire \\wr_ptr[1]_i_1__8_n_0 ;\n wire \\wr_ptr[1]_i_3__2_n_0 ;\n wire [1:0]NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED;\n\n (* SOFT_HLUTNM = \"soft_lutpair887\" *) \n LUT4 #(\n .INIT(16'hF888)) \n i___55_i_2\n (.I0(my_empty[0]),\n .I1(if_empty_r_1),\n .I2(\\my_empty_reg[4]_0 ),\n .I3(if_empty_r),\n .O(mux_rd_valid_r_reg));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_12_17\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[7:6]),\n .DIB(Q[9:8]),\n .DIC(Q[11:10]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[13:12]),\n .DOB(mem_out[15:14]),\n .DOC(mem_out[17:16]),\n .DOD(NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_18_23\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[13:12]),\n .DIB(Q[15:14]),\n .DIC(Q[17:16]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[19:18]),\n .DOB(mem_out[21:20]),\n .DOC(mem_out[23:22]),\n .DOD(NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_24_29\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[19:18]),\n .DIB(Q[21:20]),\n .DIC(Q[23:22]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[25:24]),\n .DOB(mem_out[27:26]),\n .DOC(mem_out[29:28]),\n .DOD(NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_30_35\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[25:24]),\n .DIB(Q[27:26]),\n .DIC(Q[29:28]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[31:30]),\n .DOB(mem_out[33:32]),\n .DOC(mem_out[35:34]),\n .DOD(NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_36_41\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[31:30]),\n .DIB(Q[33:32]),\n .DIC(Q[35:34]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[37:36]),\n .DOB(mem_out[39:38]),\n .DOC(mem_out[41:40]),\n .DOD(NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_42_47\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[37:36]),\n .DIB(Q[39:38]),\n .DIC(Q[41:40]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[43:42]),\n .DOB(mem_out[45:44]),\n .DOC(mem_out[47:46]),\n .DOD(NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_48_53\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[43:42]),\n .DIB(Q[45:44]),\n .DIC(Q[47:46]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[49:48]),\n .DOB(mem_out[51:50]),\n .DOC(mem_out[53:52]),\n .DOD(NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_54_59\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[49:48]),\n .DIB(Q[51:50]),\n .DIC(Q[53:52]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[55:54]),\n .DOB(mem_out[57:56]),\n .DOC(mem_out[59:58]),\n .DOD(NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_60_65\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[55:54]),\n .DIB(Q[57:56]),\n .DIC(Q[59:58]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[61:60]),\n .DOB(mem_out[63:62]),\n .DOC(mem_out[65:64]),\n .DOD(NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_66_71\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[61:60]),\n .DIB(Q[63:62]),\n .DIC(Q[65:64]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[67:66]),\n .DOB(mem_out[69:68]),\n .DOC(mem_out[71:70]),\n .DOD(NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_6_11\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[1:0]),\n .DIB(Q[3:2]),\n .DIC(Q[5:4]),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_3_6_11_n_0,mem_reg_0_3_6_11_n_1}),\n .DOB({mem_out[9],\\not_strict_mode.app_rd_data_reg[7]_0 }),\n .DOC(mem_out[11:10]),\n .DOD(NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n LUT4 #(\n .INIT(16'h0151)) \n mem_reg_0_3_6_11_i_1__1\n (.I0(if_empty_r_1),\n .I1(my_full[0]),\n .I2(\\wr_ptr[1]_i_3__2_n_0 ),\n .I3(my_empty[2]),\n .O(wr_en));\n (* SOFT_HLUTNM = \"soft_lutpair920\" *) \n LUT1 #(\n .INIT(2'h2)) \n mem_reg_0_3_6_11_i_2__1\n (.I0(my_empty[0]),\n .O(my_empty[2]));\n LUT4 #(\n .INIT(16'h0140)) \n \\my_empty[4]_i_1 \n (.I0(my_full[1]),\n .I1(if_empty_r_1),\n .I2(\\wr_ptr[1]_i_3__2_n_0 ),\n .I3(my_empty[1]),\n .O(\\my_empty[4]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h00000960)) \n \\my_empty[4]_i_2__2 \n (.I0(wr_ptr[1]),\n .I1(rd_ptr[1]),\n .I2(rd_ptr[0]),\n .I3(wr_ptr[0]),\n .I4(my_empty[1]),\n .O(\\my_empty[4]_i_2__2_n_0 ));\n (* ORIG_CELL_NAME = \"my_empty_reg[4]\" *) \n FDSE #(\n .INIT(1'b1)) \n \\my_empty_reg[4] \n (.C(CLK),\n .CE(\\my_empty[4]_i_1_n_0 ),\n .D(\\my_empty[4]_i_2__2_n_0 ),\n .Q(my_empty[0]),\n .S(ififo_rst));\n (* ORIG_CELL_NAME = \"my_empty_reg[4]\" *) \n FDSE #(\n .INIT(1'b1)) \n \\my_empty_reg[4]_rep \n (.C(CLK),\n .CE(\\my_empty[4]_i_1_n_0 ),\n .D(\\my_empty[4]_i_2__2_n_0 ),\n .Q(\\my_empty_reg[4]_rep_n_0 ),\n .S(ififo_rst));\n (* ORIG_CELL_NAME = \"my_empty_reg[4]\" *) \n FDSE #(\n .INIT(1'b1)) \n \\my_empty_reg[4]_rep__0 \n (.C(CLK),\n .CE(\\my_empty[4]_i_1_n_0 ),\n .D(\\my_empty[4]_i_2__2_n_0 ),\n .Q(\\my_empty_reg[4]_rep__0_n_0 ),\n .S(ififo_rst));\n LUT6 #(\n .INIT(64'hBAAAAAAB8AAAAAA8)) \n \\my_full[0]_i_1__2 \n (.I0(my_full[0]),\n .I1(my_empty[1]),\n .I2(my_full[1]),\n .I3(if_empty_r_1),\n .I4(\\wr_ptr[1]_i_3__2_n_0 ),\n .I5(\\my_full[0]_i_2__2_n_0 ),\n .O(\\my_full[0]_i_1__2_n_0 ));\n LUT5 #(\n .INIT(32'h00000960)) \n \\my_full[0]_i_2__2 \n (.I0(rd_ptr[1]),\n .I1(wr_ptr[1]),\n .I2(wr_ptr[0]),\n .I3(rd_ptr[0]),\n .I4(my_full[1]),\n .O(\\my_full[0]_i_2__2_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAA00411400)) \n \\my_full[1]_i_1__2 \n (.I0(\\my_full[1]_i_2__2_n_0 ),\n .I1(rd_ptr[1]),\n .I2(wr_ptr[1]),\n .I3(wr_ptr[0]),\n .I4(rd_ptr[0]),\n .I5(my_full[1]),\n .O(\\my_full[1]_i_1__2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair885\" *) \n LUT4 #(\n .INIT(16'hBFFE)) \n \\my_full[1]_i_2__2 \n (.I0(my_empty[1]),\n .I1(my_full[1]),\n .I2(if_empty_r_1),\n .I3(\\wr_ptr[1]_i_3__2_n_0 ),\n .O(\\my_full[1]_i_2__2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\my_full_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_full[0]_i_1__2_n_0 ),\n .Q(my_full[0]),\n .R(ififo_rst));\n FDRE #(\n .INIT(1'b0)) \n \\my_full_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_full[1]_i_1__2_n_0 ),\n .Q(my_full[1]),\n .R(ififo_rst));\n (* SOFT_HLUTNM = \"soft_lutpair888\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[0] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(DOC[0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [0]));\n (* SOFT_HLUTNM = \"soft_lutpair902\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[100]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[100] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [28]));\n (* SOFT_HLUTNM = \"soft_lutpair902\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[101]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[101] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [29]));\n (* SOFT_HLUTNM = \"soft_lutpair903\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[102]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[102] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [30]));\n (* SOFT_HLUTNM = \"soft_lutpair903\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[103]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[103] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [31]));\n (* SOFT_HLUTNM = \"soft_lutpair904\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[128]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[128] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [32]));\n (* SOFT_HLUTNM = \"soft_lutpair904\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[129]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[129] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [33]));\n (* SOFT_HLUTNM = \"soft_lutpair905\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[130]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[130] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [34]));\n (* SOFT_HLUTNM = \"soft_lutpair906\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[131]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[131] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [35]));\n (* SOFT_HLUTNM = \"soft_lutpair905\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[132]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[132] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [36]));\n (* SOFT_HLUTNM = \"soft_lutpair906\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[133]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[133] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [37]));\n (* SOFT_HLUTNM = \"soft_lutpair907\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[134]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[134] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [38]));\n (* SOFT_HLUTNM = \"soft_lutpair907\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[135]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[135] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [39]));\n (* SOFT_HLUTNM = \"soft_lutpair908\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[160]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[160] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [40]));\n (* SOFT_HLUTNM = \"soft_lutpair908\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[161]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[161] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [41]));\n (* SOFT_HLUTNM = \"soft_lutpair909\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[162]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[162] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [42]));\n (* SOFT_HLUTNM = \"soft_lutpair909\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[163]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[163] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [43]));\n (* SOFT_HLUTNM = \"soft_lutpair910\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[164]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[164] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [44]));\n (* SOFT_HLUTNM = \"soft_lutpair910\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[165]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[165] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [45]));\n (* SOFT_HLUTNM = \"soft_lutpair911\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[166]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[166] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [46]));\n (* SOFT_HLUTNM = \"soft_lutpair911\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[167]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[167] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [47]));\n (* SOFT_HLUTNM = \"soft_lutpair912\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[192]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[192] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [48]));\n (* SOFT_HLUTNM = \"soft_lutpair912\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[193]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[193] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [49]));\n (* SOFT_HLUTNM = \"soft_lutpair913\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[194]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[194] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [50]));\n (* SOFT_HLUTNM = \"soft_lutpair913\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[195]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[195] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [51]));\n (* SOFT_HLUTNM = \"soft_lutpair914\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[196]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[196] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [52]));\n (* SOFT_HLUTNM = \"soft_lutpair914\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[197]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[197] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [53]));\n (* SOFT_HLUTNM = \"soft_lutpair915\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[198]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[198] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [54]));\n (* SOFT_HLUTNM = \"soft_lutpair915\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[199]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[199] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [55]));\n (* SOFT_HLUTNM = \"soft_lutpair889\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[1] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(DOC[1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [1]));\n (* SOFT_HLUTNM = \"soft_lutpair916\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[224]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[224] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [56]));\n (* SOFT_HLUTNM = \"soft_lutpair916\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[225]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[225] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [57]));\n (* SOFT_HLUTNM = \"soft_lutpair917\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[226]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[226] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [58]));\n (* SOFT_HLUTNM = \"soft_lutpair917\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[227]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[227] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [59]));\n (* SOFT_HLUTNM = \"soft_lutpair918\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[228]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[228]_0 ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [60]));\n (* SOFT_HLUTNM = \"soft_lutpair918\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[229]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[229] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [61]));\n (* SOFT_HLUTNM = \"soft_lutpair919\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[230]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[230] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [62]));\n (* SOFT_HLUTNM = \"soft_lutpair919\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[231]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[231]_0 ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [63]));\n (* SOFT_HLUTNM = \"soft_lutpair890\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[2] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(DOB[0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [2]));\n (* SOFT_HLUTNM = \"soft_lutpair891\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[32]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[32] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [8]));\n (* SOFT_HLUTNM = \"soft_lutpair892\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[33]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[33] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [9]));\n (* SOFT_HLUTNM = \"soft_lutpair893\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[34]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[34] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [10]));\n (* SOFT_HLUTNM = \"soft_lutpair893\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[35]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[35] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [11]));\n (* SOFT_HLUTNM = \"soft_lutpair894\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[36]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[36] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [12]));\n (* SOFT_HLUTNM = \"soft_lutpair894\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[37]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[37] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [13]));\n (* SOFT_HLUTNM = \"soft_lutpair895\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[38]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[38] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [14]));\n (* SOFT_HLUTNM = \"soft_lutpair895\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[39]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[39] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [15]));\n (* SOFT_HLUTNM = \"soft_lutpair891\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[3] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(DOB[1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [3]));\n (* SOFT_HLUTNM = \"soft_lutpair892\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[4] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(DOA[0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [4]));\n (* SOFT_HLUTNM = \"soft_lutpair888\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[5] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(DOA[1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [5]));\n (* SOFT_HLUTNM = \"soft_lutpair896\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[64]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[64] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [16]));\n (* SOFT_HLUTNM = \"soft_lutpair896\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[65]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[65] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [17]));\n (* SOFT_HLUTNM = \"soft_lutpair897\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[66]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[66] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [18]));\n (* SOFT_HLUTNM = \"soft_lutpair897\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[67]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[67] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [19]));\n (* SOFT_HLUTNM = \"soft_lutpair898\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[68]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[68] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [20]));\n (* SOFT_HLUTNM = \"soft_lutpair898\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[69]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[69] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [21]));\n (* SOFT_HLUTNM = \"soft_lutpair889\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[6] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [6]));\n (* SOFT_HLUTNM = \"soft_lutpair899\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[70]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[70] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [22]));\n (* SOFT_HLUTNM = \"soft_lutpair899\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[71]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[71] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [23]));\n (* SOFT_HLUTNM = \"soft_lutpair890\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[7] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [7]));\n (* SOFT_HLUTNM = \"soft_lutpair900\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[96]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[96] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [24]));\n (* SOFT_HLUTNM = \"soft_lutpair900\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[97]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[97] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [25]));\n (* SOFT_HLUTNM = \"soft_lutpair901\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[98]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[98] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [26]));\n (* SOFT_HLUTNM = \"soft_lutpair901\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[99]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[99] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [27]));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_2 \n (.I0(Q[18]),\n .I1(mem_out[24]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[5] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_3 \n (.I0(Q[26]),\n .I1(mem_out[32]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[4] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_4 \n (.I0(Q[34]),\n .I1(mem_out[40]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[3] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_5 \n (.I0(Q[42]),\n .I1(mem_out[48]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[2] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_6 \n (.I0(Q[50]),\n .I1(mem_out[56]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[1] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_7 \n (.I0(Q[58]),\n .I1(mem_out[64]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[0] ));\n LUT1 #(\n .INIT(2'h2)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_8 \n (.I0(\\my_empty_reg[4]_rep_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[228] ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9 \n (.I0(\\my_empty_reg[4]_rep__0_n_0 ),\n .O(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_1 \n (.I0(Q[52]),\n .I1(mem_out[58]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[65] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_2 \n (.I0(Q[60]),\n .I1(mem_out[66]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[64] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_1 \n (.I0(Q[4]),\n .I1(mem_out[10]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[71] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_2 \n (.I0(Q[12]),\n .I1(mem_out[18]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[70] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_3 \n (.I0(Q[20]),\n .I1(mem_out[26]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[69] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_4 \n (.I0(Q[28]),\n .I1(mem_out[34]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[68] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_5 \n (.I0(Q[36]),\n .I1(mem_out[42]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[67] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_6 \n (.I0(Q[44]),\n .I1(mem_out[50]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[66] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_1 \n (.I0(Q[21]),\n .I1(mem_out[27]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[101] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_2 \n (.I0(Q[29]),\n .I1(mem_out[35]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[100] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_3 \n (.I0(Q[37]),\n .I1(mem_out[43]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[99] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_4 \n (.I0(Q[45]),\n .I1(mem_out[51]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[98] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_5 \n (.I0(Q[53]),\n .I1(mem_out[59]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[97] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_6 \n (.I0(Q[61]),\n .I1(mem_out[67]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[96] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_5 \n (.I0(Q[5]),\n .I1(mem_out[11]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[103] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_6 \n (.I0(Q[13]),\n .I1(mem_out[19]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[102] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_5 \n (.I0(Q[2]),\n .I1(\\not_strict_mode.app_rd_data_reg[7]_0 ),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[7] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_6 \n (.I0(Q[10]),\n .I1(mem_out[16]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[6] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_1 \n (.I0(Q[38]),\n .I1(mem_out[44]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[131] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_2 \n (.I0(Q[46]),\n .I1(mem_out[52]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[130] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_3 \n (.I0(Q[54]),\n .I1(mem_out[60]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[129] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_4 \n (.I0(Q[62]),\n .I1(mem_out[68]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[128] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_3 \n (.I0(Q[6]),\n .I1(mem_out[12]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[135] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_4 \n (.I0(Q[14]),\n .I1(mem_out[20]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[134] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_5 \n (.I0(Q[22]),\n .I1(mem_out[28]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[133] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_6 \n (.I0(Q[30]),\n .I1(mem_out[36]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[132] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_1 \n (.I0(Q[55]),\n .I1(mem_out[61]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[161] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_2 \n (.I0(Q[63]),\n .I1(mem_out[69]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[160] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_1 \n (.I0(Q[7]),\n .I1(mem_out[13]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[167] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_2 \n (.I0(Q[15]),\n .I1(mem_out[21]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[166] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_3 \n (.I0(Q[23]),\n .I1(mem_out[29]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[165] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_4 \n (.I0(Q[31]),\n .I1(mem_out[37]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[164] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_5 \n (.I0(Q[39]),\n .I1(mem_out[45]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[163] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_6 \n (.I0(Q[47]),\n .I1(mem_out[53]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[162] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_1 \n (.I0(Q[24]),\n .I1(mem_out[30]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[197] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_2 \n (.I0(Q[32]),\n .I1(mem_out[38]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[196] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_3 \n (.I0(Q[40]),\n .I1(mem_out[46]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[195] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_4 \n (.I0(Q[48]),\n .I1(mem_out[54]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[194] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_5 \n (.I0(Q[56]),\n .I1(mem_out[62]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[193] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_6 \n (.I0(Q[64]),\n .I1(mem_out[70]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[192] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_5 \n (.I0(Q[8]),\n .I1(mem_out[14]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[199] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_6 \n (.I0(Q[16]),\n .I1(mem_out[22]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[198] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_1 \n (.I0(Q[41]),\n .I1(mem_out[47]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[227] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_2 \n (.I0(Q[49]),\n .I1(mem_out[55]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[226] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_3 \n (.I0(Q[57]),\n .I1(mem_out[63]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[225] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_4 \n (.I0(Q[65]),\n .I1(mem_out[71]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[224] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_3 \n (.I0(Q[9]),\n .I1(mem_out[15]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[231]_0 ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_4 \n (.I0(Q[17]),\n .I1(mem_out[23]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[230] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_5 \n (.I0(Q[25]),\n .I1(mem_out[31]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[229] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_6 \n (.I0(Q[33]),\n .I1(mem_out[39]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[228]_0 ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_1 \n (.I0(Q[35]),\n .I1(mem_out[41]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[35] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_2 \n (.I0(Q[43]),\n .I1(mem_out[49]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[34] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_3 \n (.I0(Q[51]),\n .I1(mem_out[57]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[33] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_4 \n (.I0(Q[59]),\n .I1(mem_out[65]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[32] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_3 \n (.I0(Q[3]),\n .I1(mem_out[9]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[39] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_4 \n (.I0(Q[11]),\n .I1(mem_out[17]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[38] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_5 \n (.I0(Q[19]),\n .I1(mem_out[25]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[37] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_6 \n (.I0(Q[27]),\n .I1(mem_out[33]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[36] ));\n (* SOFT_HLUTNM = \"soft_lutpair886\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\rd_ptr[0]_i_1__2 \n (.I0(my_empty[1]),\n .I1(\\wr_ptr[1]_i_3__2_n_0 ),\n .I2(rd_ptr[0]),\n .O(\\rd_ptr[0]_i_1__2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair886\" *) \n LUT4 #(\n .INIT(16'hDF20)) \n \\rd_ptr[1]_i_1__2 \n (.I0(rd_ptr[0]),\n .I1(my_empty[1]),\n .I2(\\wr_ptr[1]_i_3__2_n_0 ),\n .I3(rd_ptr[1]),\n .O(\\rd_ptr[1]_i_1__2_n_0 ));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_ptr[0]_i_1__2_n_0 ),\n .Q(rd_ptr[0]),\n .R(ififo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_ptr[1]_i_1__2_n_0 ),\n .Q(rd_ptr[1]),\n .R(ififo_rst));\n LUT4 #(\n .INIT(16'hA2AE)) \n \\rd_ptr_timing[0]_i_1__6 \n (.I0(rd_ptr_timing[0]),\n .I1(\\wr_ptr[1]_i_3__2_n_0 ),\n .I2(my_empty[1]),\n .I3(rd_ptr[0]),\n .O(\\rd_ptr_timing[0]_i_1__6_n_0 ));\n LUT5 #(\n .INIT(32'hF0F066F0)) \n \\rd_ptr_timing[1]_i_1__7 \n (.I0(rd_ptr[0]),\n .I1(rd_ptr[1]),\n .I2(rd_ptr_timing[1]),\n .I3(\\wr_ptr[1]_i_3__2_n_0 ),\n .I4(my_empty[1]),\n .O(\\rd_ptr_timing[1]_i_1__7_n_0 ));\n (* KEEP = \"yes\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_ptr_timing[0]_i_1__6_n_0 ),\n .Q(rd_ptr_timing[0]),\n .R(ififo_rst));\n (* KEEP = \"yes\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_ptr_timing[1]_i_1__7_n_0 ),\n .Q(rd_ptr_timing[1]),\n .R(ififo_rst));\n (* SOFT_HLUTNM = \"soft_lutpair885\" *) \n LUT5 #(\n .INIT(32'hEEFA1105)) \n \\wr_ptr[0]_i_1__8 \n (.I0(if_empty_r_1),\n .I1(my_empty[1]),\n .I2(my_full[1]),\n .I3(\\wr_ptr[1]_i_3__2_n_0 ),\n .I4(wr_ptr[0]),\n .O(\\wr_ptr[0]_i_1__8_n_0 ));\n LUT6 #(\n .INIT(64'hFDFDFFDD02020022)) \n \\wr_ptr[1]_i_1__8 \n (.I0(wr_ptr[0]),\n .I1(if_empty_r_1),\n .I2(my_empty[1]),\n .I3(my_full[1]),\n .I4(\\wr_ptr[1]_i_3__2_n_0 ),\n .I5(wr_ptr[1]),\n .O(\\wr_ptr[1]_i_1__8_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair920\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\wr_ptr[1]_i_2__2 \n (.I0(my_empty[0]),\n .O(my_empty[1]));\n LUT6 #(\n .INIT(64'h0000700070007000)) \n \\wr_ptr[1]_i_3__2 \n (.I0(my_empty[3]),\n .I1(if_empty_r_1),\n .I2(C_byte_rd_en),\n .I3(A_byte_rd_en),\n .I4(if_empty_r_0),\n .I5(\\my_empty_reg[4]_1 ),\n .O(\\wr_ptr[1]_i_3__2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair887\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\wr_ptr[1]_i_4__1 \n (.I0(my_empty[0]),\n .O(my_empty[3]));\n LUT2 #(\n .INIT(4'h7)) \n \\wr_ptr[1]_i_5__1 \n (.I0(if_empty_r_1),\n .I1(my_empty[3]),\n .O(D_byte_rd_en));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_ptr[0]_i_1__8_n_0 ),\n .Q(wr_ptr[0]),\n .R(ififo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_ptr[1]_i_1__8_n_0 ),\n .Q(wr_ptr[1]),\n .R(ififo_rst));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_if_post_fifo\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_if_post_fifo_4\n (phy_if_empty_r_reg,\n \\not_strict_mode.app_rd_data_reg[236] ,\n \\rd_ptr_timing_reg[1]_0 ,\n \\not_strict_mode.app_rd_data_reg[239] ,\n \\not_strict_mode.app_rd_data_reg[8] ,\n \\not_strict_mode.app_rd_data_reg[9] ,\n \\not_strict_mode.app_rd_data_reg[10] ,\n \\not_strict_mode.app_rd_data_reg[11] ,\n \\not_strict_mode.app_rd_data_reg[12] ,\n \\not_strict_mode.app_rd_data_reg[13] ,\n \\not_strict_mode.app_rd_data_reg[14] ,\n \\not_strict_mode.app_rd_data_reg[15] ,\n \\not_strict_mode.app_rd_data_reg[40] ,\n \\not_strict_mode.app_rd_data_reg[41] ,\n \\not_strict_mode.app_rd_data_reg[42] ,\n \\not_strict_mode.app_rd_data_reg[43] ,\n \\not_strict_mode.app_rd_data_reg[44] ,\n \\not_strict_mode.app_rd_data_reg[45] ,\n \\not_strict_mode.app_rd_data_reg[46] ,\n \\not_strict_mode.app_rd_data_reg[47] ,\n \\not_strict_mode.app_rd_data_reg[72] ,\n \\not_strict_mode.app_rd_data_reg[73] ,\n \\not_strict_mode.app_rd_data_reg[74] ,\n \\not_strict_mode.app_rd_data_reg[75] ,\n \\not_strict_mode.app_rd_data_reg[76] ,\n \\not_strict_mode.app_rd_data_reg[77] ,\n \\not_strict_mode.app_rd_data_reg[78] ,\n \\not_strict_mode.app_rd_data_reg[79] ,\n \\not_strict_mode.app_rd_data_reg[104] ,\n \\not_strict_mode.app_rd_data_reg[105] ,\n \\not_strict_mode.app_rd_data_reg[106] ,\n \\not_strict_mode.app_rd_data_reg[107] ,\n \\not_strict_mode.app_rd_data_reg[108] ,\n \\not_strict_mode.app_rd_data_reg[109] ,\n \\not_strict_mode.app_rd_data_reg[110] ,\n \\not_strict_mode.app_rd_data_reg[111] ,\n \\not_strict_mode.app_rd_data_reg[136] ,\n \\not_strict_mode.app_rd_data_reg[137] ,\n \\not_strict_mode.app_rd_data_reg[138] ,\n \\not_strict_mode.app_rd_data_reg[139] ,\n \\not_strict_mode.app_rd_data_reg[140] ,\n \\not_strict_mode.app_rd_data_reg[141] ,\n \\not_strict_mode.app_rd_data_reg[142] ,\n \\not_strict_mode.app_rd_data_reg[143] ,\n \\not_strict_mode.app_rd_data_reg[168] ,\n \\not_strict_mode.app_rd_data_reg[169] ,\n \\not_strict_mode.app_rd_data_reg[170] ,\n \\not_strict_mode.app_rd_data_reg[171] ,\n \\not_strict_mode.app_rd_data_reg[172] ,\n \\not_strict_mode.app_rd_data_reg[173] ,\n \\not_strict_mode.app_rd_data_reg[174] ,\n \\not_strict_mode.app_rd_data_reg[175] ,\n \\not_strict_mode.app_rd_data_reg[200] ,\n \\not_strict_mode.app_rd_data_reg[201] ,\n \\not_strict_mode.app_rd_data_reg[202] ,\n \\not_strict_mode.app_rd_data_reg[203] ,\n \\not_strict_mode.app_rd_data_reg[204] ,\n \\not_strict_mode.app_rd_data_reg[205] ,\n \\not_strict_mode.app_rd_data_reg[206] ,\n \\not_strict_mode.app_rd_data_reg[207] ,\n \\not_strict_mode.app_rd_data_reg[232] ,\n \\not_strict_mode.app_rd_data_reg[233] ,\n \\not_strict_mode.app_rd_data_reg[234] ,\n \\not_strict_mode.app_rd_data_reg[235] ,\n \\not_strict_mode.app_rd_data_reg[236]_0 ,\n \\not_strict_mode.app_rd_data_reg[237] ,\n \\not_strict_mode.app_rd_data_reg[238] ,\n \\not_strict_mode.app_rd_data_reg[239]_0 ,\n \\not_strict_mode.app_rd_data_reg[15]_0 ,\n C_byte_rd_en,\n ififo_rst,\n CLK,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,\n \\read_fifo.fifo_out_data_r_reg[6] ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,\n Q,\n D_byte_rd_en,\n A_byte_rd_en,\n if_empty_r_0,\n \\my_empty_reg[4]_0 );\n output phy_if_empty_r_reg;\n output \\not_strict_mode.app_rd_data_reg[236] ;\n output [0:0]\\rd_ptr_timing_reg[1]_0 ;\n output [63:0]\\not_strict_mode.app_rd_data_reg[239] ;\n output \\not_strict_mode.app_rd_data_reg[8] ;\n output \\not_strict_mode.app_rd_data_reg[9] ;\n output \\not_strict_mode.app_rd_data_reg[10] ;\n output \\not_strict_mode.app_rd_data_reg[11] ;\n output \\not_strict_mode.app_rd_data_reg[12] ;\n output \\not_strict_mode.app_rd_data_reg[13] ;\n output \\not_strict_mode.app_rd_data_reg[14] ;\n output \\not_strict_mode.app_rd_data_reg[15] ;\n output \\not_strict_mode.app_rd_data_reg[40] ;\n output \\not_strict_mode.app_rd_data_reg[41] ;\n output \\not_strict_mode.app_rd_data_reg[42] ;\n output \\not_strict_mode.app_rd_data_reg[43] ;\n output \\not_strict_mode.app_rd_data_reg[44] ;\n output \\not_strict_mode.app_rd_data_reg[45] ;\n output \\not_strict_mode.app_rd_data_reg[46] ;\n output \\not_strict_mode.app_rd_data_reg[47] ;\n output \\not_strict_mode.app_rd_data_reg[72] ;\n output \\not_strict_mode.app_rd_data_reg[73] ;\n output \\not_strict_mode.app_rd_data_reg[74] ;\n output \\not_strict_mode.app_rd_data_reg[75] ;\n output \\not_strict_mode.app_rd_data_reg[76] ;\n output \\not_strict_mode.app_rd_data_reg[77] ;\n output \\not_strict_mode.app_rd_data_reg[78] ;\n output \\not_strict_mode.app_rd_data_reg[79] ;\n output \\not_strict_mode.app_rd_data_reg[104] ;\n output \\not_strict_mode.app_rd_data_reg[105] ;\n output \\not_strict_mode.app_rd_data_reg[106] ;\n output \\not_strict_mode.app_rd_data_reg[107] ;\n output \\not_strict_mode.app_rd_data_reg[108] ;\n output \\not_strict_mode.app_rd_data_reg[109] ;\n output \\not_strict_mode.app_rd_data_reg[110] ;\n output \\not_strict_mode.app_rd_data_reg[111] ;\n output \\not_strict_mode.app_rd_data_reg[136] ;\n output \\not_strict_mode.app_rd_data_reg[137] ;\n output \\not_strict_mode.app_rd_data_reg[138] ;\n output \\not_strict_mode.app_rd_data_reg[139] ;\n output \\not_strict_mode.app_rd_data_reg[140] ;\n output \\not_strict_mode.app_rd_data_reg[141] ;\n output \\not_strict_mode.app_rd_data_reg[142] ;\n output \\not_strict_mode.app_rd_data_reg[143] ;\n output \\not_strict_mode.app_rd_data_reg[168] ;\n output \\not_strict_mode.app_rd_data_reg[169] ;\n output \\not_strict_mode.app_rd_data_reg[170] ;\n output \\not_strict_mode.app_rd_data_reg[171] ;\n output \\not_strict_mode.app_rd_data_reg[172] ;\n output \\not_strict_mode.app_rd_data_reg[173] ;\n output \\not_strict_mode.app_rd_data_reg[174] ;\n output \\not_strict_mode.app_rd_data_reg[175] ;\n output \\not_strict_mode.app_rd_data_reg[200] ;\n output \\not_strict_mode.app_rd_data_reg[201] ;\n output \\not_strict_mode.app_rd_data_reg[202] ;\n output \\not_strict_mode.app_rd_data_reg[203] ;\n output \\not_strict_mode.app_rd_data_reg[204] ;\n output \\not_strict_mode.app_rd_data_reg[205] ;\n output \\not_strict_mode.app_rd_data_reg[206] ;\n output \\not_strict_mode.app_rd_data_reg[207] ;\n output \\not_strict_mode.app_rd_data_reg[232] ;\n output \\not_strict_mode.app_rd_data_reg[233] ;\n output \\not_strict_mode.app_rd_data_reg[234] ;\n output \\not_strict_mode.app_rd_data_reg[235] ;\n output \\not_strict_mode.app_rd_data_reg[236]_0 ;\n output \\not_strict_mode.app_rd_data_reg[237] ;\n output \\not_strict_mode.app_rd_data_reg[238] ;\n output \\not_strict_mode.app_rd_data_reg[239]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[15]_0 ;\n output C_byte_rd_en;\n input ififo_rst;\n input CLK;\n input \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n input \\read_fifo.fifo_out_data_r_reg[6] ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n input [65:0]Q;\n input D_byte_rd_en;\n input A_byte_rd_en;\n input [0:0]if_empty_r_0;\n input [0:0]\\my_empty_reg[4]_0 ;\n\n wire A_byte_rd_en;\n wire CLK;\n wire C_byte_rd_en;\n wire D_byte_rd_en;\n wire [65:0]Q;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n wire [0:0]if_empty_r_0;\n wire ififo_rst;\n wire [71:9]mem_out;\n wire mem_reg_0_3_6_11_n_0;\n wire mem_reg_0_3_6_11_n_1;\n wire [2:1]my_empty;\n wire \\my_empty[4]_i_1__0_n_0 ;\n wire \\my_empty[4]_i_2__1_n_0 ;\n wire [0:0]\\my_empty_reg[4]_0 ;\n wire \\my_empty_reg[4]_rep__0_n_0 ;\n wire \\my_empty_reg[4]_rep_n_0 ;\n wire [1:0]my_full;\n wire \\my_full[0]_i_1__1_n_0 ;\n wire \\my_full[0]_i_2__1_n_0 ;\n wire \\my_full[1]_i_1__1_n_0 ;\n wire \\my_full[1]_i_2__1_n_0 ;\n wire \\not_strict_mode.app_rd_data_reg[104] ;\n wire \\not_strict_mode.app_rd_data_reg[105] ;\n wire \\not_strict_mode.app_rd_data_reg[106] ;\n wire \\not_strict_mode.app_rd_data_reg[107] ;\n wire \\not_strict_mode.app_rd_data_reg[108] ;\n wire \\not_strict_mode.app_rd_data_reg[109] ;\n wire \\not_strict_mode.app_rd_data_reg[10] ;\n wire \\not_strict_mode.app_rd_data_reg[110] ;\n wire \\not_strict_mode.app_rd_data_reg[111] ;\n wire \\not_strict_mode.app_rd_data_reg[11] ;\n wire \\not_strict_mode.app_rd_data_reg[12] ;\n wire \\not_strict_mode.app_rd_data_reg[136] ;\n wire \\not_strict_mode.app_rd_data_reg[137] ;\n wire \\not_strict_mode.app_rd_data_reg[138] ;\n wire \\not_strict_mode.app_rd_data_reg[139] ;\n wire \\not_strict_mode.app_rd_data_reg[13] ;\n wire \\not_strict_mode.app_rd_data_reg[140] ;\n wire \\not_strict_mode.app_rd_data_reg[141] ;\n wire \\not_strict_mode.app_rd_data_reg[142] ;\n wire \\not_strict_mode.app_rd_data_reg[143] ;\n wire \\not_strict_mode.app_rd_data_reg[14] ;\n wire \\not_strict_mode.app_rd_data_reg[15] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[15]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[168] ;\n wire \\not_strict_mode.app_rd_data_reg[169] ;\n wire \\not_strict_mode.app_rd_data_reg[170] ;\n wire \\not_strict_mode.app_rd_data_reg[171] ;\n wire \\not_strict_mode.app_rd_data_reg[172] ;\n wire \\not_strict_mode.app_rd_data_reg[173] ;\n wire \\not_strict_mode.app_rd_data_reg[174] ;\n wire \\not_strict_mode.app_rd_data_reg[175] ;\n wire \\not_strict_mode.app_rd_data_reg[200] ;\n wire \\not_strict_mode.app_rd_data_reg[201] ;\n wire \\not_strict_mode.app_rd_data_reg[202] ;\n wire \\not_strict_mode.app_rd_data_reg[203] ;\n wire \\not_strict_mode.app_rd_data_reg[204] ;\n wire \\not_strict_mode.app_rd_data_reg[205] ;\n wire \\not_strict_mode.app_rd_data_reg[206] ;\n wire \\not_strict_mode.app_rd_data_reg[207] ;\n wire \\not_strict_mode.app_rd_data_reg[232] ;\n wire \\not_strict_mode.app_rd_data_reg[233] ;\n wire \\not_strict_mode.app_rd_data_reg[234] ;\n wire \\not_strict_mode.app_rd_data_reg[235] ;\n wire \\not_strict_mode.app_rd_data_reg[236] ;\n wire \\not_strict_mode.app_rd_data_reg[236]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[237] ;\n wire \\not_strict_mode.app_rd_data_reg[238] ;\n wire [63:0]\\not_strict_mode.app_rd_data_reg[239] ;\n wire \\not_strict_mode.app_rd_data_reg[239]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[40] ;\n wire \\not_strict_mode.app_rd_data_reg[41] ;\n wire \\not_strict_mode.app_rd_data_reg[42] ;\n wire \\not_strict_mode.app_rd_data_reg[43] ;\n wire \\not_strict_mode.app_rd_data_reg[44] ;\n wire \\not_strict_mode.app_rd_data_reg[45] ;\n wire \\not_strict_mode.app_rd_data_reg[46] ;\n wire \\not_strict_mode.app_rd_data_reg[47] ;\n wire \\not_strict_mode.app_rd_data_reg[72] ;\n wire \\not_strict_mode.app_rd_data_reg[73] ;\n wire \\not_strict_mode.app_rd_data_reg[74] ;\n wire \\not_strict_mode.app_rd_data_reg[75] ;\n wire \\not_strict_mode.app_rd_data_reg[76] ;\n wire \\not_strict_mode.app_rd_data_reg[77] ;\n wire \\not_strict_mode.app_rd_data_reg[78] ;\n wire \\not_strict_mode.app_rd_data_reg[79] ;\n wire \\not_strict_mode.app_rd_data_reg[8] ;\n wire \\not_strict_mode.app_rd_data_reg[9] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n wire \\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ;\n wire phy_if_empty_r_reg;\n wire [1:0]rd_ptr;\n wire \\rd_ptr[0]_i_1__1_n_0 ;\n wire \\rd_ptr[1]_i_1__1_n_0 ;\n (* RTL_KEEP = \"true\" *) (* syn_maxfan = \"10\" *) wire [1:0]rd_ptr_timing;\n wire \\rd_ptr_timing[0]_i_1__4_n_0 ;\n wire \\rd_ptr_timing[1]_i_1__6_n_0 ;\n wire [0:0]\\rd_ptr_timing_reg[1]_0 ;\n wire \\read_fifo.fifo_out_data_r_reg[6] ;\n (* MAX_FANOUT = \"40\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire wr_en;\n wire [1:0]wr_ptr;\n wire \\wr_ptr[0]_i_1__6_n_0 ;\n wire \\wr_ptr[1]_i_1__6_n_0 ;\n wire \\wr_ptr[1]_i_3__1_n_0 ;\n wire [1:0]NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED;\n\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_12_17\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[7:6]),\n .DIB(Q[9:8]),\n .DIC(Q[11:10]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[13:12]),\n .DOB(mem_out[15:14]),\n .DOC(mem_out[17:16]),\n .DOD(NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_18_23\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[13:12]),\n .DIB(Q[15:14]),\n .DIC(Q[17:16]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[19:18]),\n .DOB(mem_out[21:20]),\n .DOC(mem_out[23:22]),\n .DOD(NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_24_29\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[19:18]),\n .DIB(Q[21:20]),\n .DIC(Q[23:22]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[25:24]),\n .DOB(mem_out[27:26]),\n .DOC(mem_out[29:28]),\n .DOD(NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_30_35\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[25:24]),\n .DIB(Q[27:26]),\n .DIC(Q[29:28]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[31:30]),\n .DOB(mem_out[33:32]),\n .DOC(mem_out[35:34]),\n .DOD(NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_36_41\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[31:30]),\n .DIB(Q[33:32]),\n .DIC(Q[35:34]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[37:36]),\n .DOB(mem_out[39:38]),\n .DOC(mem_out[41:40]),\n .DOD(NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_42_47\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[37:36]),\n .DIB(Q[39:38]),\n .DIC(Q[41:40]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[43:42]),\n .DOB(mem_out[45:44]),\n .DOC(mem_out[47:46]),\n .DOD(NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_48_53\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[43:42]),\n .DIB(Q[45:44]),\n .DIC(Q[47:46]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[49:48]),\n .DOB(mem_out[51:50]),\n .DOC(mem_out[53:52]),\n .DOD(NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_54_59\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[49:48]),\n .DIB(Q[51:50]),\n .DIC(Q[53:52]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[55:54]),\n .DOB(mem_out[57:56]),\n .DOC(mem_out[59:58]),\n .DOD(NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_60_65\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[55:54]),\n .DIB(Q[57:56]),\n .DIC(Q[59:58]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[61:60]),\n .DOB(mem_out[63:62]),\n .DOC(mem_out[65:64]),\n .DOD(NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_66_71\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[61:60]),\n .DIB(Q[63:62]),\n .DIC(Q[65:64]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[67:66]),\n .DOB(mem_out[69:68]),\n .DOC(mem_out[71:70]),\n .DOD(NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_6_11\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[1:0]),\n .DIB(Q[3:2]),\n .DIC(Q[5:4]),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_3_6_11_n_0,mem_reg_0_3_6_11_n_1}),\n .DOB({mem_out[9],\\not_strict_mode.app_rd_data_reg[15]_0 }),\n .DOC(mem_out[11:10]),\n .DOD(NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n LUT4 #(\n .INIT(16'h0151)) \n mem_reg_0_3_6_11_i_1__0\n (.I0(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I1(my_full[0]),\n .I2(\\wr_ptr[1]_i_3__1_n_0 ),\n .I3(my_empty[2]),\n .O(wr_en));\n (* SOFT_HLUTNM = \"soft_lutpair868\" *) \n LUT1 #(\n .INIT(2'h2)) \n mem_reg_0_3_6_11_i_2__0\n (.I0(phy_if_empty_r_reg),\n .O(my_empty[2]));\n LUT4 #(\n .INIT(16'h0140)) \n \\my_empty[4]_i_1__0 \n (.I0(my_full[1]),\n .I1(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I2(\\wr_ptr[1]_i_3__1_n_0 ),\n .I3(my_empty[1]),\n .O(\\my_empty[4]_i_1__0_n_0 ));\n LUT5 #(\n .INIT(32'h00000960)) \n \\my_empty[4]_i_2__1 \n (.I0(wr_ptr[1]),\n .I1(rd_ptr[1]),\n .I2(rd_ptr[0]),\n .I3(wr_ptr[0]),\n .I4(my_empty[1]),\n .O(\\my_empty[4]_i_2__1_n_0 ));\n (* ORIG_CELL_NAME = \"my_empty_reg[4]\" *) \n FDSE #(\n .INIT(1'b1)) \n \\my_empty_reg[4] \n (.C(CLK),\n .CE(\\my_empty[4]_i_1__0_n_0 ),\n .D(\\my_empty[4]_i_2__1_n_0 ),\n .Q(phy_if_empty_r_reg),\n .S(ififo_rst));\n (* ORIG_CELL_NAME = \"my_empty_reg[4]\" *) \n FDSE #(\n .INIT(1'b1)) \n \\my_empty_reg[4]_rep \n (.C(CLK),\n .CE(\\my_empty[4]_i_1__0_n_0 ),\n .D(\\my_empty[4]_i_2__1_n_0 ),\n .Q(\\my_empty_reg[4]_rep_n_0 ),\n .S(ififo_rst));\n (* ORIG_CELL_NAME = \"my_empty_reg[4]\" *) \n FDSE #(\n .INIT(1'b1)) \n \\my_empty_reg[4]_rep__0 \n (.C(CLK),\n .CE(\\my_empty[4]_i_1__0_n_0 ),\n .D(\\my_empty[4]_i_2__1_n_0 ),\n .Q(\\my_empty_reg[4]_rep__0_n_0 ),\n .S(ififo_rst));\n LUT6 #(\n .INIT(64'hBAAAAAAB8AAAAAA8)) \n \\my_full[0]_i_1__1 \n (.I0(my_full[0]),\n .I1(my_empty[1]),\n .I2(my_full[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I4(\\wr_ptr[1]_i_3__1_n_0 ),\n .I5(\\my_full[0]_i_2__1_n_0 ),\n .O(\\my_full[0]_i_1__1_n_0 ));\n LUT5 #(\n .INIT(32'h00000960)) \n \\my_full[0]_i_2__1 \n (.I0(rd_ptr[1]),\n .I1(wr_ptr[1]),\n .I2(wr_ptr[0]),\n .I3(rd_ptr[0]),\n .I4(my_full[1]),\n .O(\\my_full[0]_i_2__1_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAA00411400)) \n \\my_full[1]_i_1__1 \n (.I0(\\my_full[1]_i_2__1_n_0 ),\n .I1(rd_ptr[1]),\n .I2(wr_ptr[1]),\n .I3(wr_ptr[0]),\n .I4(rd_ptr[0]),\n .I5(my_full[1]),\n .O(\\my_full[1]_i_1__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair834\" *) \n LUT4 #(\n .INIT(16'hBFFE)) \n \\my_full[1]_i_2__1 \n (.I0(my_empty[1]),\n .I1(my_full[1]),\n .I2(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I3(\\wr_ptr[1]_i_3__1_n_0 ),\n .O(\\my_full[1]_i_2__1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\my_full_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_full[0]_i_1__1_n_0 ),\n .Q(my_full[0]),\n .R(ififo_rst));\n FDRE #(\n .INIT(1'b0)) \n \\my_full_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_full[1]_i_1__1_n_0 ),\n .Q(my_full[1]),\n .R(ififo_rst));\n (* SOFT_HLUTNM = \"soft_lutpair848\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[104]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[104] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [24]));\n (* SOFT_HLUTNM = \"soft_lutpair848\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[105]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[105] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [25]));\n (* SOFT_HLUTNM = \"soft_lutpair849\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[106]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[106] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [26]));\n (* SOFT_HLUTNM = \"soft_lutpair849\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[107]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[107] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [27]));\n (* SOFT_HLUTNM = \"soft_lutpair850\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[108]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[108] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [28]));\n (* SOFT_HLUTNM = \"soft_lutpair850\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[109]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[109] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [29]));\n (* SOFT_HLUTNM = \"soft_lutpair838\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[10]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[10] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [2]));\n (* SOFT_HLUTNM = \"soft_lutpair851\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[110]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[110] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [30]));\n (* SOFT_HLUTNM = \"soft_lutpair851\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[111]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[111] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [31]));\n (* SOFT_HLUTNM = \"soft_lutpair839\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[11]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[11] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [3]));\n (* SOFT_HLUTNM = \"soft_lutpair840\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[12]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[12] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [4]));\n (* SOFT_HLUTNM = \"soft_lutpair852\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[136]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[136] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [32]));\n (* SOFT_HLUTNM = \"soft_lutpair852\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[137]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[137] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [33]));\n (* SOFT_HLUTNM = \"soft_lutpair853\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[138]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[138] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [34]));\n (* SOFT_HLUTNM = \"soft_lutpair853\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[139]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[139] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [35]));\n (* SOFT_HLUTNM = \"soft_lutpair837\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[13]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[13] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [5]));\n (* SOFT_HLUTNM = \"soft_lutpair854\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[140]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[140] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [36]));\n (* SOFT_HLUTNM = \"soft_lutpair854\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[141]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[141] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [37]));\n (* SOFT_HLUTNM = \"soft_lutpair855\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[142]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[142] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [38]));\n (* SOFT_HLUTNM = \"soft_lutpair855\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[143]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[143] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [39]));\n (* SOFT_HLUTNM = \"soft_lutpair838\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[14]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[14] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [6]));\n (* SOFT_HLUTNM = \"soft_lutpair839\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[15]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[15] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [7]));\n (* SOFT_HLUTNM = \"soft_lutpair856\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[168]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[168] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [40]));\n (* SOFT_HLUTNM = \"soft_lutpair856\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[169]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[169] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [41]));\n (* SOFT_HLUTNM = \"soft_lutpair857\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[170]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[170] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [42]));\n (* SOFT_HLUTNM = \"soft_lutpair857\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[171]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[171] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [43]));\n (* SOFT_HLUTNM = \"soft_lutpair858\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[172]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[172] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [44]));\n (* SOFT_HLUTNM = \"soft_lutpair858\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[173]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[173] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [45]));\n (* SOFT_HLUTNM = \"soft_lutpair859\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[174]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[174] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [46]));\n (* SOFT_HLUTNM = \"soft_lutpair859\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[175]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[175] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [47]));\n (* SOFT_HLUTNM = \"soft_lutpair860\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[200]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[200] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [48]));\n (* SOFT_HLUTNM = \"soft_lutpair860\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[201]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[201] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [49]));\n (* SOFT_HLUTNM = \"soft_lutpair861\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[202]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[202] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [50]));\n (* SOFT_HLUTNM = \"soft_lutpair861\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[203]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[203] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [51]));\n (* SOFT_HLUTNM = \"soft_lutpair862\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[204]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[204] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [52]));\n (* SOFT_HLUTNM = \"soft_lutpair862\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[205]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[205] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [53]));\n (* SOFT_HLUTNM = \"soft_lutpair863\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[206]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[206] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [54]));\n (* SOFT_HLUTNM = \"soft_lutpair863\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[207]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[207] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [55]));\n (* SOFT_HLUTNM = \"soft_lutpair864\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[232]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[232] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [56]));\n (* SOFT_HLUTNM = \"soft_lutpair864\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[233]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[233] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [57]));\n (* SOFT_HLUTNM = \"soft_lutpair865\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[234]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[234] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [58]));\n (* SOFT_HLUTNM = \"soft_lutpair865\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[235]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[235] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [59]));\n (* SOFT_HLUTNM = \"soft_lutpair866\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[236]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[236]_0 ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [60]));\n (* SOFT_HLUTNM = \"soft_lutpair866\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[237]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[237] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [61]));\n (* SOFT_HLUTNM = \"soft_lutpair867\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[238]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[238] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [62]));\n (* SOFT_HLUTNM = \"soft_lutpair867\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[239]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[239]_0 ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [63]));\n (* SOFT_HLUTNM = \"soft_lutpair836\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[40]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[40] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [8]));\n (* SOFT_HLUTNM = \"soft_lutpair840\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[41]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[41] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [9]));\n (* SOFT_HLUTNM = \"soft_lutpair841\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[42]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[42] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [10]));\n (* SOFT_HLUTNM = \"soft_lutpair841\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[43]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[43] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [11]));\n (* SOFT_HLUTNM = \"soft_lutpair842\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[44]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[44] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [12]));\n (* SOFT_HLUTNM = \"soft_lutpair842\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[45]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[45] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [13]));\n (* SOFT_HLUTNM = \"soft_lutpair843\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[46]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[46] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [14]));\n (* SOFT_HLUTNM = \"soft_lutpair843\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[47]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[47] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [15]));\n (* SOFT_HLUTNM = \"soft_lutpair844\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[72]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[72] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [16]));\n (* SOFT_HLUTNM = \"soft_lutpair844\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[73]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[73] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [17]));\n (* SOFT_HLUTNM = \"soft_lutpair845\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[74]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[74] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [18]));\n (* SOFT_HLUTNM = \"soft_lutpair845\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[75]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[75] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [19]));\n (* SOFT_HLUTNM = \"soft_lutpair846\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[76]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[76] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [20]));\n (* SOFT_HLUTNM = \"soft_lutpair846\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[77]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[77] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [21]));\n (* SOFT_HLUTNM = \"soft_lutpair847\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[78]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[78] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [22]));\n (* SOFT_HLUTNM = \"soft_lutpair847\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[79]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[79] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [23]));\n (* SOFT_HLUTNM = \"soft_lutpair836\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[8]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[8] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [0]));\n (* SOFT_HLUTNM = \"soft_lutpair837\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[9]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[9] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [1]));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_1 \n (.I0(Q[20]),\n .I1(mem_out[26]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[77] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_2 \n (.I0(Q[28]),\n .I1(mem_out[34]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[76] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_3 \n (.I0(Q[36]),\n .I1(mem_out[42]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[75] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_4 \n (.I0(Q[44]),\n .I1(mem_out[50]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[74] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_5 \n (.I0(Q[52]),\n .I1(mem_out[58]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[73] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_6 \n (.I0(Q[60]),\n .I1(mem_out[66]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[72] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_5 \n (.I0(Q[4]),\n .I1(mem_out[10]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[79] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_6 \n (.I0(Q[12]),\n .I1(mem_out[18]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[78] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_1 \n (.I0(Q[37]),\n .I1(mem_out[43]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[107] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_2 \n (.I0(Q[45]),\n .I1(mem_out[51]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[106] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_3 \n (.I0(Q[53]),\n .I1(mem_out[59]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[105] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_4 \n (.I0(Q[61]),\n .I1(mem_out[67]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[104] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_3 \n (.I0(Q[5]),\n .I1(mem_out[11]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[111] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_4 \n (.I0(Q[13]),\n .I1(mem_out[19]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[110] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_5 \n (.I0(Q[21]),\n .I1(mem_out[27]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[109] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_6 \n (.I0(Q[29]),\n .I1(mem_out[35]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[108] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_1 \n (.I0(Q[34]),\n .I1(mem_out[40]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[11] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_2 \n (.I0(Q[42]),\n .I1(mem_out[48]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[10] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_3 \n (.I0(Q[50]),\n .I1(mem_out[56]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[9] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_4 \n (.I0(Q[58]),\n .I1(mem_out[64]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[8] ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7 \n (.I0(\\my_empty_reg[4]_rep__0_n_0 ),\n .O(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_1 \n (.I0(Q[54]),\n .I1(mem_out[60]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[137] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_2 \n (.I0(Q[62]),\n .I1(mem_out[68]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[136] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_1 \n (.I0(Q[6]),\n .I1(mem_out[12]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[143] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_2 \n (.I0(Q[14]),\n .I1(mem_out[20]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[142] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_3 \n (.I0(Q[22]),\n .I1(mem_out[28]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[141] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_4 \n (.I0(Q[30]),\n .I1(mem_out[36]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[140] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_5 \n (.I0(Q[38]),\n .I1(mem_out[44]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[139] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_6 \n (.I0(Q[46]),\n .I1(mem_out[52]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[138] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_1 \n (.I0(Q[23]),\n .I1(mem_out[29]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[173] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_2 \n (.I0(Q[31]),\n .I1(mem_out[37]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[172] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_3 \n (.I0(Q[39]),\n .I1(mem_out[45]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[171] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_4 \n (.I0(Q[47]),\n .I1(mem_out[53]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[170] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_5 \n (.I0(Q[55]),\n .I1(mem_out[61]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[169] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_6 \n (.I0(Q[63]),\n .I1(mem_out[69]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[168] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_5 \n (.I0(Q[7]),\n .I1(mem_out[13]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[175] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_6 \n (.I0(Q[15]),\n .I1(mem_out[21]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[174] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_3 \n (.I0(Q[2]),\n .I1(\\not_strict_mode.app_rd_data_reg[15]_0 ),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[15] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_4 \n (.I0(Q[10]),\n .I1(mem_out[16]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[14] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_5 \n (.I0(Q[18]),\n .I1(mem_out[24]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[13] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_6 \n (.I0(Q[26]),\n .I1(mem_out[32]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[12] ));\n LUT1 #(\n .INIT(2'h2)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_8 \n (.I0(\\my_empty_reg[4]_rep_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[236] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_1 \n (.I0(Q[40]),\n .I1(mem_out[46]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[203] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_2 \n (.I0(Q[48]),\n .I1(mem_out[54]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[202] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_3 \n (.I0(Q[56]),\n .I1(mem_out[62]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[201] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_4 \n (.I0(Q[64]),\n .I1(mem_out[70]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[200] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_3 \n (.I0(Q[8]),\n .I1(mem_out[14]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[207] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_4 \n (.I0(Q[16]),\n .I1(mem_out[22]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[206] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_5 \n (.I0(Q[24]),\n .I1(mem_out[30]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[205] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_6 \n (.I0(Q[32]),\n .I1(mem_out[38]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[204] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_1 \n (.I0(Q[57]),\n .I1(mem_out[63]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[233] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_2 \n (.I0(Q[65]),\n .I1(mem_out[71]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[232] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_1 \n (.I0(Q[9]),\n .I1(mem_out[15]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[239]_0 ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_2 \n (.I0(Q[17]),\n .I1(mem_out[23]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[238] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_3 \n (.I0(Q[25]),\n .I1(mem_out[31]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[237] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_4 \n (.I0(Q[33]),\n .I1(mem_out[39]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[236]_0 ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_5 \n (.I0(Q[41]),\n .I1(mem_out[47]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[235] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_6 \n (.I0(Q[49]),\n .I1(mem_out[55]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[234] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_1 \n (.I0(Q[51]),\n .I1(mem_out[57]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[41] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_2 \n (.I0(Q[59]),\n .I1(mem_out[65]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[40] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_1 \n (.I0(Q[3]),\n .I1(mem_out[9]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[47] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_2 \n (.I0(Q[11]),\n .I1(mem_out[17]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[46] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_3 \n (.I0(Q[19]),\n .I1(mem_out[25]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[45] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_4 \n (.I0(Q[27]),\n .I1(mem_out[33]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[44] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_5 \n (.I0(Q[35]),\n .I1(mem_out[41]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[43] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_6 \n (.I0(Q[43]),\n .I1(mem_out[49]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[42] ));\n (* SOFT_HLUTNM = \"soft_lutpair835\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\rd_ptr[0]_i_1__1 \n (.I0(my_empty[1]),\n .I1(\\wr_ptr[1]_i_3__1_n_0 ),\n .I2(rd_ptr[0]),\n .O(\\rd_ptr[0]_i_1__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair835\" *) \n LUT4 #(\n .INIT(16'hDF20)) \n \\rd_ptr[1]_i_1__1 \n (.I0(rd_ptr[0]),\n .I1(my_empty[1]),\n .I2(\\wr_ptr[1]_i_3__1_n_0 ),\n .I3(rd_ptr[1]),\n .O(\\rd_ptr[1]_i_1__1_n_0 ));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_ptr[0]_i_1__1_n_0 ),\n .Q(rd_ptr[0]),\n .R(ififo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_ptr[1]_i_1__1_n_0 ),\n .Q(rd_ptr[1]),\n .R(ififo_rst));\n LUT4 #(\n .INIT(16'hA2AE)) \n \\rd_ptr_timing[0]_i_1__4 \n (.I0(rd_ptr_timing[0]),\n .I1(\\wr_ptr[1]_i_3__1_n_0 ),\n .I2(my_empty[1]),\n .I3(rd_ptr[0]),\n .O(\\rd_ptr_timing[0]_i_1__4_n_0 ));\n LUT5 #(\n .INIT(32'hF0F066F0)) \n \\rd_ptr_timing[1]_i_1__6 \n (.I0(rd_ptr[0]),\n .I1(rd_ptr[1]),\n .I2(rd_ptr_timing[1]),\n .I3(\\wr_ptr[1]_i_3__1_n_0 ),\n .I4(my_empty[1]),\n .O(\\rd_ptr_timing[1]_i_1__6_n_0 ));\n (* KEEP = \"yes\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_ptr_timing[0]_i_1__4_n_0 ),\n .Q(rd_ptr_timing[0]),\n .R(ififo_rst));\n (* KEEP = \"yes\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_ptr_timing[1]_i_1__6_n_0 ),\n .Q(rd_ptr_timing[1]),\n .R(ififo_rst));\n (* SOFT_HLUTNM = \"soft_lutpair834\" *) \n LUT5 #(\n .INIT(32'hEEFA1105)) \n \\wr_ptr[0]_i_1__6 \n (.I0(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I1(my_empty[1]),\n .I2(my_full[1]),\n .I3(\\wr_ptr[1]_i_3__1_n_0 ),\n .I4(wr_ptr[0]),\n .O(\\wr_ptr[0]_i_1__6_n_0 ));\n LUT6 #(\n .INIT(64'hFDFDFFDD02020022)) \n \\wr_ptr[1]_i_1__6 \n (.I0(wr_ptr[0]),\n .I1(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I2(my_empty[1]),\n .I3(my_full[1]),\n .I4(\\wr_ptr[1]_i_3__1_n_0 ),\n .I5(wr_ptr[1]),\n .O(\\wr_ptr[1]_i_1__6_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\wr_ptr[1]_i_2__1 \n (.I0(phy_if_empty_r_reg),\n .O(my_empty[1]));\n LUT6 #(\n .INIT(64'h0000700070007000)) \n \\wr_ptr[1]_i_3__1 \n (.I0(\\rd_ptr_timing_reg[1]_0 ),\n .I1(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I2(D_byte_rd_en),\n .I3(A_byte_rd_en),\n .I4(if_empty_r_0),\n .I5(\\my_empty_reg[4]_0 ),\n .O(\\wr_ptr[1]_i_3__1_n_0 ));\n LUT2 #(\n .INIT(4'h7)) \n \\wr_ptr[1]_i_5__0 \n (.I0(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I1(\\rd_ptr_timing_reg[1]_0 ),\n .O(C_byte_rd_en));\n (* SOFT_HLUTNM = \"soft_lutpair868\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\wr_ptr[1]_i_7 \n (.I0(phy_if_empty_r_reg),\n .O(\\rd_ptr_timing_reg[1]_0 ));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_ptr[0]_i_1__6_n_0 ),\n .Q(wr_ptr[0]),\n .R(ififo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_ptr[1]_i_1__6_n_0 ),\n .Q(wr_ptr[1]),\n .R(ififo_rst));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_if_post_fifo\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_if_post_fifo_5\n (\\not_strict_mode.app_rd_data_reg[244] ,\n \\rd_ptr_timing_reg[1]_0 ,\n rd_buf_we,\n \\not_strict_mode.status_ram.rd_buf_we_r1_reg ,\n phy_rddata_en,\n mux_rd_valid_r_reg,\n \\read_fifo.tail_r_reg[0] ,\n \\not_strict_mode.app_rd_data_reg[247] ,\n \\not_strict_mode.app_rd_data_reg[16] ,\n \\not_strict_mode.app_rd_data_reg[17] ,\n \\not_strict_mode.app_rd_data_reg[18] ,\n \\not_strict_mode.app_rd_data_reg[19] ,\n \\not_strict_mode.app_rd_data_reg[20] ,\n \\not_strict_mode.app_rd_data_reg[21] ,\n \\not_strict_mode.app_rd_data_reg[22] ,\n \\not_strict_mode.app_rd_data_reg[23] ,\n \\not_strict_mode.app_rd_data_reg[48] ,\n \\not_strict_mode.app_rd_data_reg[49] ,\n \\not_strict_mode.app_rd_data_reg[50] ,\n \\not_strict_mode.app_rd_data_reg[51] ,\n \\not_strict_mode.app_rd_data_reg[52] ,\n \\not_strict_mode.app_rd_data_reg[53] ,\n \\not_strict_mode.app_rd_data_reg[54] ,\n \\not_strict_mode.app_rd_data_reg[55] ,\n \\not_strict_mode.app_rd_data_reg[80] ,\n \\not_strict_mode.app_rd_data_reg[81] ,\n \\not_strict_mode.app_rd_data_reg[82] ,\n \\not_strict_mode.app_rd_data_reg[83] ,\n \\not_strict_mode.app_rd_data_reg[84] ,\n \\not_strict_mode.app_rd_data_reg[85] ,\n \\not_strict_mode.app_rd_data_reg[86] ,\n \\not_strict_mode.app_rd_data_reg[87] ,\n \\not_strict_mode.app_rd_data_reg[112] ,\n \\not_strict_mode.app_rd_data_reg[113] ,\n \\not_strict_mode.app_rd_data_reg[114] ,\n \\not_strict_mode.app_rd_data_reg[115] ,\n \\not_strict_mode.app_rd_data_reg[116] ,\n \\not_strict_mode.app_rd_data_reg[117] ,\n \\not_strict_mode.app_rd_data_reg[118] ,\n \\not_strict_mode.app_rd_data_reg[119] ,\n \\not_strict_mode.app_rd_data_reg[144] ,\n \\not_strict_mode.app_rd_data_reg[145] ,\n \\not_strict_mode.app_rd_data_reg[146] ,\n \\not_strict_mode.app_rd_data_reg[147] ,\n \\not_strict_mode.app_rd_data_reg[148] ,\n \\not_strict_mode.app_rd_data_reg[149] ,\n \\not_strict_mode.app_rd_data_reg[150] ,\n \\not_strict_mode.app_rd_data_reg[151] ,\n \\not_strict_mode.app_rd_data_reg[176] ,\n \\not_strict_mode.app_rd_data_reg[177] ,\n \\not_strict_mode.app_rd_data_reg[178] ,\n \\not_strict_mode.app_rd_data_reg[179] ,\n \\not_strict_mode.app_rd_data_reg[180] ,\n \\not_strict_mode.app_rd_data_reg[181] ,\n \\not_strict_mode.app_rd_data_reg[182] ,\n \\not_strict_mode.app_rd_data_reg[183] ,\n \\not_strict_mode.app_rd_data_reg[208] ,\n \\not_strict_mode.app_rd_data_reg[209] ,\n \\not_strict_mode.app_rd_data_reg[210] ,\n \\not_strict_mode.app_rd_data_reg[211] ,\n \\not_strict_mode.app_rd_data_reg[212] ,\n \\not_strict_mode.app_rd_data_reg[213] ,\n \\not_strict_mode.app_rd_data_reg[214] ,\n \\not_strict_mode.app_rd_data_reg[215] ,\n \\not_strict_mode.app_rd_data_reg[240] ,\n \\not_strict_mode.app_rd_data_reg[241] ,\n \\not_strict_mode.app_rd_data_reg[242] ,\n \\not_strict_mode.app_rd_data_reg[243] ,\n \\not_strict_mode.app_rd_data_reg[244]_0 ,\n \\not_strict_mode.app_rd_data_reg[245] ,\n \\not_strict_mode.app_rd_data_reg[246] ,\n \\not_strict_mode.app_rd_data_reg[247]_0 ,\n phy_if_empty_r_reg,\n \\not_strict_mode.app_rd_data_reg[23]_0 ,\n B_byte_rd_en,\n ififo_rst,\n CLK,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,\n \\read_fifo.fifo_out_data_r_reg[6] ,\n ram_init_done_r,\n if_empty_r_0,\n my_empty,\n \\my_empty_reg[4]_0 ,\n prbs_rdlvl_start_reg,\n out,\n tail_r,\n \\read_fifo.fifo_out_data_r_reg[6]_0 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,\n Q,\n D_byte_rd_en,\n A_byte_rd_en);\n output \\not_strict_mode.app_rd_data_reg[244] ;\n output [0:0]\\rd_ptr_timing_reg[1]_0 ;\n output rd_buf_we;\n output \\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n output phy_rddata_en;\n output mux_rd_valid_r_reg;\n output \\read_fifo.tail_r_reg[0] ;\n output [63:0]\\not_strict_mode.app_rd_data_reg[247] ;\n output \\not_strict_mode.app_rd_data_reg[16] ;\n output \\not_strict_mode.app_rd_data_reg[17] ;\n output \\not_strict_mode.app_rd_data_reg[18] ;\n output \\not_strict_mode.app_rd_data_reg[19] ;\n output \\not_strict_mode.app_rd_data_reg[20] ;\n output \\not_strict_mode.app_rd_data_reg[21] ;\n output \\not_strict_mode.app_rd_data_reg[22] ;\n output \\not_strict_mode.app_rd_data_reg[23] ;\n output \\not_strict_mode.app_rd_data_reg[48] ;\n output \\not_strict_mode.app_rd_data_reg[49] ;\n output \\not_strict_mode.app_rd_data_reg[50] ;\n output \\not_strict_mode.app_rd_data_reg[51] ;\n output \\not_strict_mode.app_rd_data_reg[52] ;\n output \\not_strict_mode.app_rd_data_reg[53] ;\n output \\not_strict_mode.app_rd_data_reg[54] ;\n output \\not_strict_mode.app_rd_data_reg[55] ;\n output \\not_strict_mode.app_rd_data_reg[80] ;\n output \\not_strict_mode.app_rd_data_reg[81] ;\n output \\not_strict_mode.app_rd_data_reg[82] ;\n output \\not_strict_mode.app_rd_data_reg[83] ;\n output \\not_strict_mode.app_rd_data_reg[84] ;\n output \\not_strict_mode.app_rd_data_reg[85] ;\n output \\not_strict_mode.app_rd_data_reg[86] ;\n output \\not_strict_mode.app_rd_data_reg[87] ;\n output \\not_strict_mode.app_rd_data_reg[112] ;\n output \\not_strict_mode.app_rd_data_reg[113] ;\n output \\not_strict_mode.app_rd_data_reg[114] ;\n output \\not_strict_mode.app_rd_data_reg[115] ;\n output \\not_strict_mode.app_rd_data_reg[116] ;\n output \\not_strict_mode.app_rd_data_reg[117] ;\n output \\not_strict_mode.app_rd_data_reg[118] ;\n output \\not_strict_mode.app_rd_data_reg[119] ;\n output \\not_strict_mode.app_rd_data_reg[144] ;\n output \\not_strict_mode.app_rd_data_reg[145] ;\n output \\not_strict_mode.app_rd_data_reg[146] ;\n output \\not_strict_mode.app_rd_data_reg[147] ;\n output \\not_strict_mode.app_rd_data_reg[148] ;\n output \\not_strict_mode.app_rd_data_reg[149] ;\n output \\not_strict_mode.app_rd_data_reg[150] ;\n output \\not_strict_mode.app_rd_data_reg[151] ;\n output \\not_strict_mode.app_rd_data_reg[176] ;\n output \\not_strict_mode.app_rd_data_reg[177] ;\n output \\not_strict_mode.app_rd_data_reg[178] ;\n output \\not_strict_mode.app_rd_data_reg[179] ;\n output \\not_strict_mode.app_rd_data_reg[180] ;\n output \\not_strict_mode.app_rd_data_reg[181] ;\n output \\not_strict_mode.app_rd_data_reg[182] ;\n output \\not_strict_mode.app_rd_data_reg[183] ;\n output \\not_strict_mode.app_rd_data_reg[208] ;\n output \\not_strict_mode.app_rd_data_reg[209] ;\n output \\not_strict_mode.app_rd_data_reg[210] ;\n output \\not_strict_mode.app_rd_data_reg[211] ;\n output \\not_strict_mode.app_rd_data_reg[212] ;\n output \\not_strict_mode.app_rd_data_reg[213] ;\n output \\not_strict_mode.app_rd_data_reg[214] ;\n output \\not_strict_mode.app_rd_data_reg[215] ;\n output \\not_strict_mode.app_rd_data_reg[240] ;\n output \\not_strict_mode.app_rd_data_reg[241] ;\n output \\not_strict_mode.app_rd_data_reg[242] ;\n output \\not_strict_mode.app_rd_data_reg[243] ;\n output \\not_strict_mode.app_rd_data_reg[244]_0 ;\n output \\not_strict_mode.app_rd_data_reg[245] ;\n output \\not_strict_mode.app_rd_data_reg[246] ;\n output \\not_strict_mode.app_rd_data_reg[247]_0 ;\n output phy_if_empty_r_reg;\n output [0:0]\\not_strict_mode.app_rd_data_reg[23]_0 ;\n output B_byte_rd_en;\n input ififo_rst;\n input CLK;\n input \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n input [0:0]\\read_fifo.fifo_out_data_r_reg[6] ;\n input ram_init_done_r;\n input [0:0]if_empty_r_0;\n input [1:0]my_empty;\n input \\my_empty_reg[4]_0 ;\n input prbs_rdlvl_start_reg;\n input out;\n input [0:0]tail_r;\n input \\read_fifo.fifo_out_data_r_reg[6]_0 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n input [65:0]Q;\n input D_byte_rd_en;\n input A_byte_rd_en;\n\n wire A_byte_rd_en;\n wire B_byte_rd_en;\n wire CLK;\n wire D_byte_rd_en;\n wire [65:0]Q;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n wire [0:0]if_empty_r_0;\n wire ififo_rst;\n wire [71:9]mem_out;\n wire mem_reg_0_3_6_11_n_0;\n wire mem_reg_0_3_6_11_n_1;\n wire mux_rd_valid_r_reg;\n wire [1:0]my_empty;\n wire \\my_empty[4]_i_1__1_n_0 ;\n wire \\my_empty[4]_i_2__0_n_0 ;\n wire [2:0]my_empty_0;\n wire \\my_empty_reg[4]_0 ;\n wire \\my_empty_reg[4]_rep__0_n_0 ;\n wire \\my_empty_reg[4]_rep_n_0 ;\n wire [1:0]my_full;\n wire \\my_full[0]_i_1__0_n_0 ;\n wire \\my_full[0]_i_2__0_n_0 ;\n wire \\my_full[1]_i_1__0_n_0 ;\n wire \\my_full[1]_i_2__0_n_0 ;\n wire \\not_strict_mode.app_rd_data_reg[112] ;\n wire \\not_strict_mode.app_rd_data_reg[113] ;\n wire \\not_strict_mode.app_rd_data_reg[114] ;\n wire \\not_strict_mode.app_rd_data_reg[115] ;\n wire \\not_strict_mode.app_rd_data_reg[116] ;\n wire \\not_strict_mode.app_rd_data_reg[117] ;\n wire \\not_strict_mode.app_rd_data_reg[118] ;\n wire \\not_strict_mode.app_rd_data_reg[119] ;\n wire \\not_strict_mode.app_rd_data_reg[144] ;\n wire \\not_strict_mode.app_rd_data_reg[145] ;\n wire \\not_strict_mode.app_rd_data_reg[146] ;\n wire \\not_strict_mode.app_rd_data_reg[147] ;\n wire \\not_strict_mode.app_rd_data_reg[148] ;\n wire \\not_strict_mode.app_rd_data_reg[149] ;\n wire \\not_strict_mode.app_rd_data_reg[150] ;\n wire \\not_strict_mode.app_rd_data_reg[151] ;\n wire \\not_strict_mode.app_rd_data_reg[16] ;\n wire \\not_strict_mode.app_rd_data_reg[176] ;\n wire \\not_strict_mode.app_rd_data_reg[177] ;\n wire \\not_strict_mode.app_rd_data_reg[178] ;\n wire \\not_strict_mode.app_rd_data_reg[179] ;\n wire \\not_strict_mode.app_rd_data_reg[17] ;\n wire \\not_strict_mode.app_rd_data_reg[180] ;\n wire \\not_strict_mode.app_rd_data_reg[181] ;\n wire \\not_strict_mode.app_rd_data_reg[182] ;\n wire \\not_strict_mode.app_rd_data_reg[183] ;\n wire \\not_strict_mode.app_rd_data_reg[18] ;\n wire \\not_strict_mode.app_rd_data_reg[19] ;\n wire \\not_strict_mode.app_rd_data_reg[208] ;\n wire \\not_strict_mode.app_rd_data_reg[209] ;\n wire \\not_strict_mode.app_rd_data_reg[20] ;\n wire \\not_strict_mode.app_rd_data_reg[210] ;\n wire \\not_strict_mode.app_rd_data_reg[211] ;\n wire \\not_strict_mode.app_rd_data_reg[212] ;\n wire \\not_strict_mode.app_rd_data_reg[213] ;\n wire \\not_strict_mode.app_rd_data_reg[214] ;\n wire \\not_strict_mode.app_rd_data_reg[215] ;\n wire \\not_strict_mode.app_rd_data_reg[21] ;\n wire \\not_strict_mode.app_rd_data_reg[22] ;\n wire \\not_strict_mode.app_rd_data_reg[23] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[23]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[240] ;\n wire \\not_strict_mode.app_rd_data_reg[241] ;\n wire \\not_strict_mode.app_rd_data_reg[242] ;\n wire \\not_strict_mode.app_rd_data_reg[243] ;\n wire \\not_strict_mode.app_rd_data_reg[244] ;\n wire \\not_strict_mode.app_rd_data_reg[244]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[245] ;\n wire \\not_strict_mode.app_rd_data_reg[246] ;\n wire [63:0]\\not_strict_mode.app_rd_data_reg[247] ;\n wire \\not_strict_mode.app_rd_data_reg[247]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[48] ;\n wire \\not_strict_mode.app_rd_data_reg[49] ;\n wire \\not_strict_mode.app_rd_data_reg[50] ;\n wire \\not_strict_mode.app_rd_data_reg[51] ;\n wire \\not_strict_mode.app_rd_data_reg[52] ;\n wire \\not_strict_mode.app_rd_data_reg[53] ;\n wire \\not_strict_mode.app_rd_data_reg[54] ;\n wire \\not_strict_mode.app_rd_data_reg[55] ;\n wire \\not_strict_mode.app_rd_data_reg[80] ;\n wire \\not_strict_mode.app_rd_data_reg[81] ;\n wire \\not_strict_mode.app_rd_data_reg[82] ;\n wire \\not_strict_mode.app_rd_data_reg[83] ;\n wire \\not_strict_mode.app_rd_data_reg[84] ;\n wire \\not_strict_mode.app_rd_data_reg[85] ;\n wire \\not_strict_mode.app_rd_data_reg[86] ;\n wire \\not_strict_mode.app_rd_data_reg[87] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n wire \\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ;\n wire \\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n wire out;\n wire phy_if_empty_r_reg;\n wire phy_rddata_en;\n wire prbs_rdlvl_start_reg;\n wire ram_init_done_r;\n wire rd_buf_we;\n wire [1:0]rd_ptr;\n wire \\rd_ptr[0]_i_1__0_n_0 ;\n wire \\rd_ptr[1]_i_1__0_n_0 ;\n (* RTL_KEEP = \"true\" *) (* syn_maxfan = \"10\" *) wire [1:0]rd_ptr_timing;\n wire \\rd_ptr_timing[0]_i_1__2_n_0 ;\n wire \\rd_ptr_timing[1]_i_1__5_n_0 ;\n wire [0:0]\\rd_ptr_timing_reg[1]_0 ;\n wire [0:0]\\read_fifo.fifo_out_data_r_reg[6] ;\n wire \\read_fifo.fifo_out_data_r_reg[6]_0 ;\n wire \\read_fifo.tail_r_reg[0] ;\n wire [0:0]tail_r;\n (* MAX_FANOUT = \"40\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire wr_en;\n wire [1:0]wr_ptr;\n wire \\wr_ptr[0]_i_1__4_n_0 ;\n wire \\wr_ptr[1]_i_1__4_n_0 ;\n wire \\wr_ptr[1]_i_3__0_n_0 ;\n wire [1:0]NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED;\n\n LUT6 #(\n .INIT(64'h0000077700000000)) \n i___55_i_1\n (.I0(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I1(my_empty_0[0]),\n .I2(if_empty_r_0),\n .I3(my_empty[0]),\n .I4(\\my_empty_reg[4]_0 ),\n .I5(out),\n .O(\\not_strict_mode.status_ram.rd_buf_we_r1_reg ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_12_17\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[7:6]),\n .DIB(Q[9:8]),\n .DIC(Q[11:10]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[13:12]),\n .DOB(mem_out[15:14]),\n .DOC(mem_out[17:16]),\n .DOD(NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_18_23\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[13:12]),\n .DIB(Q[15:14]),\n .DIC(Q[17:16]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[19:18]),\n .DOB(mem_out[21:20]),\n .DOC(mem_out[23:22]),\n .DOD(NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_24_29\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[19:18]),\n .DIB(Q[21:20]),\n .DIC(Q[23:22]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[25:24]),\n .DOB(mem_out[27:26]),\n .DOC(mem_out[29:28]),\n .DOD(NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_30_35\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[25:24]),\n .DIB(Q[27:26]),\n .DIC(Q[29:28]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[31:30]),\n .DOB(mem_out[33:32]),\n .DOC(mem_out[35:34]),\n .DOD(NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_36_41\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[31:30]),\n .DIB(Q[33:32]),\n .DIC(Q[35:34]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[37:36]),\n .DOB(mem_out[39:38]),\n .DOC(mem_out[41:40]),\n .DOD(NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_42_47\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[37:36]),\n .DIB(Q[39:38]),\n .DIC(Q[41:40]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[43:42]),\n .DOB(mem_out[45:44]),\n .DOC(mem_out[47:46]),\n .DOD(NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_48_53\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[43:42]),\n .DIB(Q[45:44]),\n .DIC(Q[47:46]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[49:48]),\n .DOB(mem_out[51:50]),\n .DOC(mem_out[53:52]),\n .DOD(NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_54_59\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[49:48]),\n .DIB(Q[51:50]),\n .DIC(Q[53:52]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[55:54]),\n .DOB(mem_out[57:56]),\n .DOC(mem_out[59:58]),\n .DOD(NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_60_65\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[55:54]),\n .DIB(Q[57:56]),\n .DIC(Q[59:58]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[61:60]),\n .DOB(mem_out[63:62]),\n .DOC(mem_out[65:64]),\n .DOD(NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_66_71\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[61:60]),\n .DIB(Q[63:62]),\n .DIC(Q[65:64]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[67:66]),\n .DOB(mem_out[69:68]),\n .DOC(mem_out[71:70]),\n .DOD(NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_6_11\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[1:0]),\n .DIB(Q[3:2]),\n .DIC(Q[5:4]),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_3_6_11_n_0,mem_reg_0_3_6_11_n_1}),\n .DOB({mem_out[9],\\not_strict_mode.app_rd_data_reg[23]_0 }),\n .DOC(mem_out[11:10]),\n .DOD(NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n LUT4 #(\n .INIT(16'h0151)) \n mem_reg_0_3_6_11_i_1\n (.I0(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I1(my_full[0]),\n .I2(\\wr_ptr[1]_i_3__0_n_0 ),\n .I3(my_empty_0[2]),\n .O(wr_en));\n (* SOFT_HLUTNM = \"soft_lutpair817\" *) \n LUT1 #(\n .INIT(2'h2)) \n mem_reg_0_3_6_11_i_2\n (.I0(my_empty_0[0]),\n .O(my_empty_0[2]));\n LUT6 #(\n .INIT(64'h0000077700000000)) \n mux_rd_valid_r_i_1\n (.I0(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I1(my_empty_0[0]),\n .I2(if_empty_r_0),\n .I3(my_empty[0]),\n .I4(\\my_empty_reg[4]_0 ),\n .I5(prbs_rdlvl_start_reg),\n .O(mux_rd_valid_r_reg));\n LUT4 #(\n .INIT(16'h0140)) \n \\my_empty[4]_i_1__1 \n (.I0(my_full[1]),\n .I1(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I2(\\wr_ptr[1]_i_3__0_n_0 ),\n .I3(my_empty_0[1]),\n .O(\\my_empty[4]_i_1__1_n_0 ));\n LUT5 #(\n .INIT(32'h00000960)) \n \\my_empty[4]_i_2__0 \n (.I0(wr_ptr[1]),\n .I1(rd_ptr[1]),\n .I2(rd_ptr[0]),\n .I3(wr_ptr[0]),\n .I4(my_empty_0[1]),\n .O(\\my_empty[4]_i_2__0_n_0 ));\n (* ORIG_CELL_NAME = \"my_empty_reg[4]\" *) \n FDSE #(\n .INIT(1'b1)) \n \\my_empty_reg[4] \n (.C(CLK),\n .CE(\\my_empty[4]_i_1__1_n_0 ),\n .D(\\my_empty[4]_i_2__0_n_0 ),\n .Q(my_empty_0[0]),\n .S(ififo_rst));\n (* ORIG_CELL_NAME = \"my_empty_reg[4]\" *) \n FDSE #(\n .INIT(1'b1)) \n \\my_empty_reg[4]_rep \n (.C(CLK),\n .CE(\\my_empty[4]_i_1__1_n_0 ),\n .D(\\my_empty[4]_i_2__0_n_0 ),\n .Q(\\my_empty_reg[4]_rep_n_0 ),\n .S(ififo_rst));\n (* ORIG_CELL_NAME = \"my_empty_reg[4]\" *) \n FDSE #(\n .INIT(1'b1)) \n \\my_empty_reg[4]_rep__0 \n (.C(CLK),\n .CE(\\my_empty[4]_i_1__1_n_0 ),\n .D(\\my_empty[4]_i_2__0_n_0 ),\n .Q(\\my_empty_reg[4]_rep__0_n_0 ),\n .S(ififo_rst));\n LUT6 #(\n .INIT(64'hBAAAAAAB8AAAAAA8)) \n \\my_full[0]_i_1__0 \n (.I0(my_full[0]),\n .I1(my_empty_0[1]),\n .I2(my_full[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I4(\\wr_ptr[1]_i_3__0_n_0 ),\n .I5(\\my_full[0]_i_2__0_n_0 ),\n .O(\\my_full[0]_i_1__0_n_0 ));\n LUT5 #(\n .INIT(32'h00000960)) \n \\my_full[0]_i_2__0 \n (.I0(rd_ptr[1]),\n .I1(wr_ptr[1]),\n .I2(wr_ptr[0]),\n .I3(rd_ptr[0]),\n .I4(my_full[1]),\n .O(\\my_full[0]_i_2__0_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAA00411400)) \n \\my_full[1]_i_1__0 \n (.I0(\\my_full[1]_i_2__0_n_0 ),\n .I1(rd_ptr[1]),\n .I2(wr_ptr[1]),\n .I3(wr_ptr[0]),\n .I4(rd_ptr[0]),\n .I5(my_full[1]),\n .O(\\my_full[1]_i_1__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair783\" *) \n LUT4 #(\n .INIT(16'hBFFE)) \n \\my_full[1]_i_2__0 \n (.I0(my_empty_0[1]),\n .I1(my_full[1]),\n .I2(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I3(\\wr_ptr[1]_i_3__0_n_0 ),\n .O(\\my_full[1]_i_2__0_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\my_full_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_full[0]_i_1__0_n_0 ),\n .Q(my_full[0]),\n .R(ififo_rst));\n FDRE #(\n .INIT(1'b0)) \n \\my_full_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_full[1]_i_1__0_n_0 ),\n .Q(my_full[1]),\n .R(ififo_rst));\n (* SOFT_HLUTNM = \"soft_lutpair797\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[112]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[112] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [24]));\n (* SOFT_HLUTNM = \"soft_lutpair797\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[113]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[113] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [25]));\n (* SOFT_HLUTNM = \"soft_lutpair798\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[114]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[114] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [26]));\n (* SOFT_HLUTNM = \"soft_lutpair798\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[115]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[115] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [27]));\n (* SOFT_HLUTNM = \"soft_lutpair799\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[116]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[116] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [28]));\n (* SOFT_HLUTNM = \"soft_lutpair799\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[117]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[117] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [29]));\n (* SOFT_HLUTNM = \"soft_lutpair800\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[118]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[118] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [30]));\n (* SOFT_HLUTNM = \"soft_lutpair800\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[119]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[119] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [31]));\n (* SOFT_HLUTNM = \"soft_lutpair801\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[144]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[144] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [32]));\n (* SOFT_HLUTNM = \"soft_lutpair801\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[145]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[145] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [33]));\n (* SOFT_HLUTNM = \"soft_lutpair802\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[146]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[146] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [34]));\n (* SOFT_HLUTNM = \"soft_lutpair802\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[147]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[147] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [35]));\n (* SOFT_HLUTNM = \"soft_lutpair803\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[148]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[148] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [36]));\n (* SOFT_HLUTNM = \"soft_lutpair804\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[149]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[149] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [37]));\n (* SOFT_HLUTNM = \"soft_lutpair803\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[150]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[150] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [38]));\n (* SOFT_HLUTNM = \"soft_lutpair804\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[151]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[151] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [39]));\n (* SOFT_HLUTNM = \"soft_lutpair785\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[16]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[16] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [0]));\n (* SOFT_HLUTNM = \"soft_lutpair805\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[176]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[176] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [40]));\n (* SOFT_HLUTNM = \"soft_lutpair805\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[177]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[177] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [41]));\n (* SOFT_HLUTNM = \"soft_lutpair806\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[178]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[178] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [42]));\n (* SOFT_HLUTNM = \"soft_lutpair806\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[179]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[179] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [43]));\n (* SOFT_HLUTNM = \"soft_lutpair786\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[17]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[17] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [1]));\n (* SOFT_HLUTNM = \"soft_lutpair807\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[180]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[180] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [44]));\n (* SOFT_HLUTNM = \"soft_lutpair807\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[181]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[181] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [45]));\n (* SOFT_HLUTNM = \"soft_lutpair808\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[182]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[182] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [46]));\n (* SOFT_HLUTNM = \"soft_lutpair808\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[183]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[183] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [47]));\n (* SOFT_HLUTNM = \"soft_lutpair787\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[18]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[18] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [2]));\n (* SOFT_HLUTNM = \"soft_lutpair788\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[19]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[19] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [3]));\n (* SOFT_HLUTNM = \"soft_lutpair809\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[208]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[208] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [48]));\n (* SOFT_HLUTNM = \"soft_lutpair809\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[209]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[209] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [49]));\n (* SOFT_HLUTNM = \"soft_lutpair789\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[20]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[20] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [4]));\n (* SOFT_HLUTNM = \"soft_lutpair810\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[210]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[210] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [50]));\n (* SOFT_HLUTNM = \"soft_lutpair810\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[211]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[211] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [51]));\n (* SOFT_HLUTNM = \"soft_lutpair811\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[212]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[212] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [52]));\n (* SOFT_HLUTNM = \"soft_lutpair811\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[213]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[213] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [53]));\n (* SOFT_HLUTNM = \"soft_lutpair812\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[214]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[214] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [54]));\n (* SOFT_HLUTNM = \"soft_lutpair812\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[215]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[215] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [55]));\n (* SOFT_HLUTNM = \"soft_lutpair790\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[21]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[21] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [5]));\n (* SOFT_HLUTNM = \"soft_lutpair791\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[22]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[22] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [6]));\n (* SOFT_HLUTNM = \"soft_lutpair792\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[23]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[23] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [7]));\n (* SOFT_HLUTNM = \"soft_lutpair813\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[240]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[240] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [56]));\n (* SOFT_HLUTNM = \"soft_lutpair813\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[241]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[241] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [57]));\n (* SOFT_HLUTNM = \"soft_lutpair814\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[242]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[242] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [58]));\n (* SOFT_HLUTNM = \"soft_lutpair814\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[243]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[243] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [59]));\n (* SOFT_HLUTNM = \"soft_lutpair815\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[244]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[244]_0 ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [60]));\n (* SOFT_HLUTNM = \"soft_lutpair815\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[245]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[245] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [61]));\n (* SOFT_HLUTNM = \"soft_lutpair816\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[246]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[246] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [62]));\n (* SOFT_HLUTNM = \"soft_lutpair816\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[247]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[247]_0 ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [63]));\n (* SOFT_HLUTNM = \"soft_lutpair785\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[48]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[48] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [8]));\n (* SOFT_HLUTNM = \"soft_lutpair786\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[49]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[49] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [9]));\n (* SOFT_HLUTNM = \"soft_lutpair787\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[50]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[50] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [10]));\n (* SOFT_HLUTNM = \"soft_lutpair788\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[51]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[51] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [11]));\n (* SOFT_HLUTNM = \"soft_lutpair789\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[52]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[52] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [12]));\n (* SOFT_HLUTNM = \"soft_lutpair790\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[53]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[53] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [13]));\n (* SOFT_HLUTNM = \"soft_lutpair791\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[54]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[54] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [14]));\n (* SOFT_HLUTNM = \"soft_lutpair792\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[55]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[55] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [15]));\n (* SOFT_HLUTNM = \"soft_lutpair793\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[80]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[80] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [16]));\n (* SOFT_HLUTNM = \"soft_lutpair793\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[81]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[81] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [17]));\n (* SOFT_HLUTNM = \"soft_lutpair794\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[82]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[82] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [18]));\n (* SOFT_HLUTNM = \"soft_lutpair794\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[83]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[83] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [19]));\n (* SOFT_HLUTNM = \"soft_lutpair795\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[84]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[84] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [20]));\n (* SOFT_HLUTNM = \"soft_lutpair795\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[85]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[85] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [21]));\n (* SOFT_HLUTNM = \"soft_lutpair796\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[86]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[86] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [22]));\n (* SOFT_HLUTNM = \"soft_lutpair796\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[87]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[87] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [23]));\n LUT3 #(\n .INIT(8'h2F)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_1 \n (.I0(\\not_strict_mode.status_ram.rd_buf_we_r1_reg ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(ram_init_done_r),\n .O(rd_buf_we));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_1 \n (.I0(Q[36]),\n .I1(mem_out[42]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[83] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_2 \n (.I0(Q[44]),\n .I1(mem_out[50]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[82] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_3 \n (.I0(Q[52]),\n .I1(mem_out[58]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[81] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_4 \n (.I0(Q[60]),\n .I1(mem_out[66]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[80] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_3 \n (.I0(Q[4]),\n .I1(mem_out[10]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[87] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_4 \n (.I0(Q[12]),\n .I1(mem_out[18]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[86] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_5 \n (.I0(Q[20]),\n .I1(mem_out[26]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[85] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_6 \n (.I0(Q[28]),\n .I1(mem_out[34]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[84] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_1 \n (.I0(Q[53]),\n .I1(mem_out[59]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[113] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_2 \n (.I0(Q[61]),\n .I1(mem_out[67]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[112] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_1 \n (.I0(Q[5]),\n .I1(mem_out[11]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[119] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_2 \n (.I0(Q[13]),\n .I1(mem_out[19]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[118] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_3 \n (.I0(Q[21]),\n .I1(mem_out[27]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[117] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_4 \n (.I0(Q[29]),\n .I1(mem_out[35]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[116] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_5 \n (.I0(Q[37]),\n .I1(mem_out[43]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[115] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_6 \n (.I0(Q[45]),\n .I1(mem_out[51]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[114] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_1 \n (.I0(Q[22]),\n .I1(mem_out[28]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[149] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_2 \n (.I0(Q[30]),\n .I1(mem_out[36]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[148] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_3 \n (.I0(Q[38]),\n .I1(mem_out[44]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[147] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_4 \n (.I0(Q[46]),\n .I1(mem_out[52]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[146] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_5 \n (.I0(Q[54]),\n .I1(mem_out[60]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[145] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_6 \n (.I0(Q[62]),\n .I1(mem_out[68]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[144] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_5 \n (.I0(Q[6]),\n .I1(mem_out[12]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[151] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_6 \n (.I0(Q[14]),\n .I1(mem_out[20]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[150] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_1 \n (.I0(Q[39]),\n .I1(mem_out[45]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[179] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_2 \n (.I0(Q[47]),\n .I1(mem_out[53]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[178] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_3 \n (.I0(Q[55]),\n .I1(mem_out[61]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[177] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_4 \n (.I0(Q[63]),\n .I1(mem_out[69]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[176] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_1 \n (.I0(Q[50]),\n .I1(mem_out[56]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[17] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_2 \n (.I0(Q[58]),\n .I1(mem_out[64]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[16] ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7 \n (.I0(\\my_empty_reg[4]_rep__0_n_0 ),\n .O(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_3 \n (.I0(Q[7]),\n .I1(mem_out[13]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[183] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_4 \n (.I0(Q[15]),\n .I1(mem_out[21]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[182] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_5 \n (.I0(Q[23]),\n .I1(mem_out[29]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[181] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_6 \n (.I0(Q[31]),\n .I1(mem_out[37]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[180] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_1 \n (.I0(Q[56]),\n .I1(mem_out[62]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[209] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_2 \n (.I0(Q[64]),\n .I1(mem_out[70]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[208] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_1 \n (.I0(Q[8]),\n .I1(mem_out[14]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[215] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_2 \n (.I0(Q[16]),\n .I1(mem_out[22]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[214] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_3 \n (.I0(Q[24]),\n .I1(mem_out[30]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[213] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_4 \n (.I0(Q[32]),\n .I1(mem_out[38]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[212] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_5 \n (.I0(Q[40]),\n .I1(mem_out[46]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[211] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_6 \n (.I0(Q[48]),\n .I1(mem_out[54]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[210] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_1 \n (.I0(Q[2]),\n .I1(\\not_strict_mode.app_rd_data_reg[23]_0 ),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[23] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_2 \n (.I0(Q[10]),\n .I1(mem_out[16]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[22] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_3 \n (.I0(Q[18]),\n .I1(mem_out[24]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[21] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_4 \n (.I0(Q[26]),\n .I1(mem_out[32]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[20] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_5 \n (.I0(Q[34]),\n .I1(mem_out[40]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[19] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_6 \n (.I0(Q[42]),\n .I1(mem_out[48]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[18] ));\n LUT1 #(\n .INIT(2'h2)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_7 \n (.I0(\\my_empty_reg[4]_rep_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[244] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_1 \n (.I0(Q[25]),\n .I1(mem_out[31]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[245] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_2 \n (.I0(Q[33]),\n .I1(mem_out[39]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[244]_0 ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_3 \n (.I0(Q[41]),\n .I1(mem_out[47]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[243] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_4 \n (.I0(Q[49]),\n .I1(mem_out[55]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[242] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_5 \n (.I0(Q[57]),\n .I1(mem_out[63]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[241] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_6 \n (.I0(Q[65]),\n .I1(mem_out[71]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[240] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_5 \n (.I0(Q[9]),\n .I1(mem_out[15]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[247]_0 ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_6 \n (.I0(Q[17]),\n .I1(mem_out[23]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[246] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_1 \n (.I0(Q[19]),\n .I1(mem_out[25]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[53] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_2 \n (.I0(Q[27]),\n .I1(mem_out[33]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[52] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_3 \n (.I0(Q[35]),\n .I1(mem_out[41]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[51] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_4 \n (.I0(Q[43]),\n .I1(mem_out[49]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[50] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_5 \n (.I0(Q[51]),\n .I1(mem_out[57]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[49] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_6 \n (.I0(Q[59]),\n .I1(mem_out[65]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[48] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_5 \n (.I0(Q[3]),\n .I1(mem_out[9]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[55] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_6 \n (.I0(Q[11]),\n .I1(mem_out[17]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[54] ));\n (* SOFT_HLUTNM = \"soft_lutpair782\" *) \n LUT5 #(\n .INIT(32'hFFFFF888)) \n phy_if_empty_r_i_1\n (.I0(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I1(my_empty_0[0]),\n .I2(if_empty_r_0),\n .I3(my_empty[0]),\n .I4(\\my_empty_reg[4]_0 ),\n .O(phy_if_empty_r_reg));\n (* SOFT_HLUTNM = \"soft_lutpair782\" *) \n LUT5 #(\n .INIT(32'h00000777)) \n phy_rddata_en_r1_i_1\n (.I0(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I1(my_empty_0[0]),\n .I2(if_empty_r_0),\n .I3(my_empty[0]),\n .I4(\\my_empty_reg[4]_0 ),\n .O(phy_rddata_en));\n (* SOFT_HLUTNM = \"soft_lutpair784\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\rd_ptr[0]_i_1__0 \n (.I0(my_empty_0[1]),\n .I1(\\wr_ptr[1]_i_3__0_n_0 ),\n .I2(rd_ptr[0]),\n .O(\\rd_ptr[0]_i_1__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair784\" *) \n LUT4 #(\n .INIT(16'hDF20)) \n \\rd_ptr[1]_i_1__0 \n (.I0(rd_ptr[0]),\n .I1(my_empty_0[1]),\n .I2(\\wr_ptr[1]_i_3__0_n_0 ),\n .I3(rd_ptr[1]),\n .O(\\rd_ptr[1]_i_1__0_n_0 ));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_ptr[0]_i_1__0_n_0 ),\n .Q(rd_ptr[0]),\n .R(ififo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_ptr[1]_i_1__0_n_0 ),\n .Q(rd_ptr[1]),\n .R(ififo_rst));\n LUT4 #(\n .INIT(16'hA2AE)) \n \\rd_ptr_timing[0]_i_1__2 \n (.I0(rd_ptr_timing[0]),\n .I1(\\wr_ptr[1]_i_3__0_n_0 ),\n .I2(my_empty_0[1]),\n .I3(rd_ptr[0]),\n .O(\\rd_ptr_timing[0]_i_1__2_n_0 ));\n LUT5 #(\n .INIT(32'hF0F066F0)) \n \\rd_ptr_timing[1]_i_1__5 \n (.I0(rd_ptr[0]),\n .I1(rd_ptr[1]),\n .I2(rd_ptr_timing[1]),\n .I3(\\wr_ptr[1]_i_3__0_n_0 ),\n .I4(my_empty_0[1]),\n .O(\\rd_ptr_timing[1]_i_1__5_n_0 ));\n (* KEEP = \"yes\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_ptr_timing[0]_i_1__2_n_0 ),\n .Q(rd_ptr_timing[0]),\n .R(ififo_rst));\n (* KEEP = \"yes\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_ptr_timing[1]_i_1__5_n_0 ),\n .Q(rd_ptr_timing[1]),\n .R(ififo_rst));\n LUT2 #(\n .INIT(4'h6)) \n \\read_fifo.tail_r[0]_i_1 \n (.I0(\\not_strict_mode.status_ram.rd_buf_we_r1_reg ),\n .I1(tail_r),\n .O(\\read_fifo.tail_r_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair783\" *) \n LUT5 #(\n .INIT(32'hEEFA1105)) \n \\wr_ptr[0]_i_1__4 \n (.I0(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I1(my_empty_0[1]),\n .I2(my_full[1]),\n .I3(\\wr_ptr[1]_i_3__0_n_0 ),\n .I4(wr_ptr[0]),\n .O(\\wr_ptr[0]_i_1__4_n_0 ));\n LUT6 #(\n .INIT(64'hFDFDFFDD02020022)) \n \\wr_ptr[1]_i_1__4 \n (.I0(wr_ptr[0]),\n .I1(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I2(my_empty_0[1]),\n .I3(my_full[1]),\n .I4(\\wr_ptr[1]_i_3__0_n_0 ),\n .I5(wr_ptr[1]),\n .O(\\wr_ptr[1]_i_1__4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\wr_ptr[1]_i_2__0 \n (.I0(my_empty_0[0]),\n .O(my_empty_0[1]));\n LUT6 #(\n .INIT(64'h0000700070007000)) \n \\wr_ptr[1]_i_3__0 \n (.I0(\\rd_ptr_timing_reg[1]_0 ),\n .I1(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I2(D_byte_rd_en),\n .I3(A_byte_rd_en),\n .I4(if_empty_r_0),\n .I5(my_empty[1]),\n .O(\\wr_ptr[1]_i_3__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair817\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\wr_ptr[1]_i_4__0 \n (.I0(my_empty_0[0]),\n .O(\\rd_ptr_timing_reg[1]_0 ));\n LUT2 #(\n .INIT(4'h7)) \n \\wr_ptr[1]_i_6 \n (.I0(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I1(\\rd_ptr_timing_reg[1]_0 ),\n .O(B_byte_rd_en));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_ptr[0]_i_1__4_n_0 ),\n .Q(wr_ptr[0]),\n .R(ififo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_ptr[1]_i_1__4_n_0 ),\n .Q(wr_ptr[1]),\n .R(ififo_rst));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_if_post_fifo\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_if_post_fifo_6\n (\\wr_ptr_reg[1]_0 ,\n \\not_strict_mode.app_rd_data_reg[252] ,\n \\data_bytes_r_reg[63] ,\n \\not_strict_mode.app_rd_data_reg[255] ,\n \\not_strict_mode.app_rd_data_reg[254] ,\n \\not_strict_mode.app_rd_data_reg[253] ,\n \\not_strict_mode.app_rd_data_reg[252]_0 ,\n \\not_strict_mode.app_rd_data_reg[251] ,\n \\not_strict_mode.app_rd_data_reg[250] ,\n \\not_strict_mode.app_rd_data_reg[249] ,\n \\not_strict_mode.app_rd_data_reg[248] ,\n \\not_strict_mode.app_rd_data_reg[223] ,\n \\not_strict_mode.app_rd_data_reg[222] ,\n \\not_strict_mode.app_rd_data_reg[221] ,\n \\not_strict_mode.app_rd_data_reg[220] ,\n \\not_strict_mode.app_rd_data_reg[219] ,\n \\not_strict_mode.app_rd_data_reg[218] ,\n \\not_strict_mode.app_rd_data_reg[217] ,\n \\not_strict_mode.app_rd_data_reg[216] ,\n \\not_strict_mode.app_rd_data_reg[191] ,\n \\not_strict_mode.app_rd_data_reg[190] ,\n \\not_strict_mode.app_rd_data_reg[189] ,\n \\not_strict_mode.app_rd_data_reg[188] ,\n \\not_strict_mode.app_rd_data_reg[187] ,\n \\not_strict_mode.app_rd_data_reg[186] ,\n \\not_strict_mode.app_rd_data_reg[185] ,\n \\not_strict_mode.app_rd_data_reg[184] ,\n \\not_strict_mode.app_rd_data_reg[159] ,\n \\not_strict_mode.app_rd_data_reg[158] ,\n \\not_strict_mode.app_rd_data_reg[157] ,\n \\not_strict_mode.app_rd_data_reg[156] ,\n \\not_strict_mode.app_rd_data_reg[155] ,\n \\not_strict_mode.app_rd_data_reg[154] ,\n \\not_strict_mode.app_rd_data_reg[153] ,\n \\not_strict_mode.app_rd_data_reg[152] ,\n \\not_strict_mode.app_rd_data_reg[127] ,\n \\not_strict_mode.app_rd_data_reg[126] ,\n \\not_strict_mode.app_rd_data_reg[125] ,\n \\not_strict_mode.app_rd_data_reg[124] ,\n \\not_strict_mode.app_rd_data_reg[123] ,\n \\not_strict_mode.app_rd_data_reg[122] ,\n \\not_strict_mode.app_rd_data_reg[121] ,\n \\not_strict_mode.app_rd_data_reg[120] ,\n \\not_strict_mode.app_rd_data_reg[95] ,\n \\not_strict_mode.app_rd_data_reg[94] ,\n \\not_strict_mode.app_rd_data_reg[93] ,\n \\not_strict_mode.app_rd_data_reg[92] ,\n \\not_strict_mode.app_rd_data_reg[91] ,\n \\not_strict_mode.app_rd_data_reg[90] ,\n \\not_strict_mode.app_rd_data_reg[89] ,\n \\not_strict_mode.app_rd_data_reg[88] ,\n \\not_strict_mode.app_rd_data_reg[63] ,\n \\not_strict_mode.app_rd_data_reg[62] ,\n \\not_strict_mode.app_rd_data_reg[61] ,\n \\not_strict_mode.app_rd_data_reg[60] ,\n \\not_strict_mode.app_rd_data_reg[59] ,\n \\not_strict_mode.app_rd_data_reg[58] ,\n \\not_strict_mode.app_rd_data_reg[57] ,\n \\not_strict_mode.app_rd_data_reg[56] ,\n \\not_strict_mode.app_rd_data_reg[31] ,\n \\not_strict_mode.app_rd_data_reg[30] ,\n \\not_strict_mode.app_rd_data_reg[29] ,\n \\not_strict_mode.app_rd_data_reg[28] ,\n \\not_strict_mode.app_rd_data_reg[27] ,\n \\not_strict_mode.app_rd_data_reg[26] ,\n \\not_strict_mode.app_rd_data_reg[25] ,\n \\not_strict_mode.app_rd_data_reg[24] ,\n \\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,\n \\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,\n \\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,\n \\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,\n \\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,\n \\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,\n \\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,\n \\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,\n \\not_strict_mode.app_rd_data_reg[255]_0 ,\n \\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ,\n \\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ,\n \\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ,\n \\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ,\n \\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ,\n \\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ,\n \\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ,\n \\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ,\n \\not_strict_mode.app_rd_data_reg[31]_0 ,\n A_byte_rd_en,\n p_0_out,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,\n \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,\n \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,\n \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,\n \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,\n ififo_rst,\n CLK,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ,\n \\byte_r_reg[0] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ,\n \\byte_r_reg[1] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ,\n \\rd_mux_sel_r_reg[1] ,\n \\read_fifo.fifo_out_data_r_reg[6] ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,\n A,\n Q,\n D_byte_rd_en,\n B_byte_rd_en,\n if_empty_r_0,\n my_empty,\n \\po_stg2_wrcal_cnt_reg[1] );\n output \\wr_ptr_reg[1]_0 ;\n output \\not_strict_mode.app_rd_data_reg[252] ;\n output [63:0]\\data_bytes_r_reg[63] ;\n output \\not_strict_mode.app_rd_data_reg[255] ;\n output \\not_strict_mode.app_rd_data_reg[254] ;\n output \\not_strict_mode.app_rd_data_reg[253] ;\n output \\not_strict_mode.app_rd_data_reg[252]_0 ;\n output \\not_strict_mode.app_rd_data_reg[251] ;\n output \\not_strict_mode.app_rd_data_reg[250] ;\n output \\not_strict_mode.app_rd_data_reg[249] ;\n output \\not_strict_mode.app_rd_data_reg[248] ;\n output \\not_strict_mode.app_rd_data_reg[223] ;\n output \\not_strict_mode.app_rd_data_reg[222] ;\n output \\not_strict_mode.app_rd_data_reg[221] ;\n output \\not_strict_mode.app_rd_data_reg[220] ;\n output \\not_strict_mode.app_rd_data_reg[219] ;\n output \\not_strict_mode.app_rd_data_reg[218] ;\n output \\not_strict_mode.app_rd_data_reg[217] ;\n output \\not_strict_mode.app_rd_data_reg[216] ;\n output \\not_strict_mode.app_rd_data_reg[191] ;\n output \\not_strict_mode.app_rd_data_reg[190] ;\n output \\not_strict_mode.app_rd_data_reg[189] ;\n output \\not_strict_mode.app_rd_data_reg[188] ;\n output \\not_strict_mode.app_rd_data_reg[187] ;\n output \\not_strict_mode.app_rd_data_reg[186] ;\n output \\not_strict_mode.app_rd_data_reg[185] ;\n output \\not_strict_mode.app_rd_data_reg[184] ;\n output \\not_strict_mode.app_rd_data_reg[159] ;\n output \\not_strict_mode.app_rd_data_reg[158] ;\n output \\not_strict_mode.app_rd_data_reg[157] ;\n output \\not_strict_mode.app_rd_data_reg[156] ;\n output \\not_strict_mode.app_rd_data_reg[155] ;\n output \\not_strict_mode.app_rd_data_reg[154] ;\n output \\not_strict_mode.app_rd_data_reg[153] ;\n output \\not_strict_mode.app_rd_data_reg[152] ;\n output \\not_strict_mode.app_rd_data_reg[127] ;\n output \\not_strict_mode.app_rd_data_reg[126] ;\n output \\not_strict_mode.app_rd_data_reg[125] ;\n output \\not_strict_mode.app_rd_data_reg[124] ;\n output \\not_strict_mode.app_rd_data_reg[123] ;\n output \\not_strict_mode.app_rd_data_reg[122] ;\n output \\not_strict_mode.app_rd_data_reg[121] ;\n output \\not_strict_mode.app_rd_data_reg[120] ;\n output \\not_strict_mode.app_rd_data_reg[95] ;\n output \\not_strict_mode.app_rd_data_reg[94] ;\n output \\not_strict_mode.app_rd_data_reg[93] ;\n output \\not_strict_mode.app_rd_data_reg[92] ;\n output \\not_strict_mode.app_rd_data_reg[91] ;\n output \\not_strict_mode.app_rd_data_reg[90] ;\n output \\not_strict_mode.app_rd_data_reg[89] ;\n output \\not_strict_mode.app_rd_data_reg[88] ;\n output \\not_strict_mode.app_rd_data_reg[63] ;\n output \\not_strict_mode.app_rd_data_reg[62] ;\n output \\not_strict_mode.app_rd_data_reg[61] ;\n output \\not_strict_mode.app_rd_data_reg[60] ;\n output \\not_strict_mode.app_rd_data_reg[59] ;\n output \\not_strict_mode.app_rd_data_reg[58] ;\n output \\not_strict_mode.app_rd_data_reg[57] ;\n output \\not_strict_mode.app_rd_data_reg[56] ;\n output \\not_strict_mode.app_rd_data_reg[31] ;\n output \\not_strict_mode.app_rd_data_reg[30] ;\n output \\not_strict_mode.app_rd_data_reg[29] ;\n output \\not_strict_mode.app_rd_data_reg[28] ;\n output \\not_strict_mode.app_rd_data_reg[27] ;\n output \\not_strict_mode.app_rd_data_reg[26] ;\n output \\not_strict_mode.app_rd_data_reg[25] ;\n output \\not_strict_mode.app_rd_data_reg[24] ;\n output \\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n output \\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n output \\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n output \\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n output \\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n output \\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n output \\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n output \\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n output [63:0]\\not_strict_mode.app_rd_data_reg[255]_0 ;\n output \\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ;\n output \\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ;\n output \\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ;\n output \\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ;\n output \\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ;\n output \\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ;\n output \\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ;\n output \\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[31]_0 ;\n output A_byte_rd_en;\n output p_0_out;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n output \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n output \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n output \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n output \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n input ififo_rst;\n input CLK;\n input \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;\n input \\byte_r_reg[0] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;\n input \\byte_r_reg[1] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;\n input [1:0]\\rd_mux_sel_r_reg[1] ;\n input \\read_fifo.fifo_out_data_r_reg[6] ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n input [1:0]A;\n input [65:0]Q;\n input D_byte_rd_en;\n input B_byte_rd_en;\n input [0:0]if_empty_r_0;\n input [0:0]my_empty;\n input [1:0]\\po_stg2_wrcal_cnt_reg[1] ;\n\n wire [1:0]A;\n wire A_byte_rd_en;\n wire B_byte_rd_en;\n wire CLK;\n wire D_byte_rd_en;\n wire [65:0]Q;\n wire \\byte_r_reg[0] ;\n wire \\byte_r_reg[1] ;\n wire [63:0]\\data_bytes_r_reg[63] ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ;\n wire \\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n wire \\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n wire \\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n wire \\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;\n wire \\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n wire \\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n wire \\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n wire \\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ;\n wire [0:0]if_empty_r_0;\n wire ififo_rst;\n wire [63:1]mem_out;\n wire mem_reg_0_3_60_65_n_4;\n wire mem_reg_0_3_60_65_n_5;\n wire [0:0]my_empty;\n wire \\my_empty[4]_i_1__2_n_0 ;\n wire \\my_empty[4]_i_2_n_0 ;\n wire [3:1]my_empty_0;\n wire \\my_empty_reg[4]_rep__0_n_0 ;\n wire \\my_empty_reg[4]_rep_n_0 ;\n wire [1:0]my_full;\n wire \\my_full[0]_i_1_n_0 ;\n wire \\my_full[0]_i_2_n_0 ;\n wire \\my_full[1]_i_1_n_0 ;\n wire \\my_full[1]_i_2_n_0 ;\n wire \\not_strict_mode.app_rd_data_reg[120] ;\n wire \\not_strict_mode.app_rd_data_reg[121] ;\n wire \\not_strict_mode.app_rd_data_reg[122] ;\n wire \\not_strict_mode.app_rd_data_reg[123] ;\n wire \\not_strict_mode.app_rd_data_reg[124] ;\n wire \\not_strict_mode.app_rd_data_reg[125] ;\n wire \\not_strict_mode.app_rd_data_reg[126] ;\n wire \\not_strict_mode.app_rd_data_reg[127] ;\n wire \\not_strict_mode.app_rd_data_reg[152] ;\n wire \\not_strict_mode.app_rd_data_reg[153] ;\n wire \\not_strict_mode.app_rd_data_reg[154] ;\n wire \\not_strict_mode.app_rd_data_reg[155] ;\n wire \\not_strict_mode.app_rd_data_reg[156] ;\n wire \\not_strict_mode.app_rd_data_reg[157] ;\n wire \\not_strict_mode.app_rd_data_reg[158] ;\n wire \\not_strict_mode.app_rd_data_reg[159] ;\n wire \\not_strict_mode.app_rd_data_reg[184] ;\n wire \\not_strict_mode.app_rd_data_reg[185] ;\n wire \\not_strict_mode.app_rd_data_reg[186] ;\n wire \\not_strict_mode.app_rd_data_reg[187] ;\n wire \\not_strict_mode.app_rd_data_reg[188] ;\n wire \\not_strict_mode.app_rd_data_reg[189] ;\n wire \\not_strict_mode.app_rd_data_reg[190] ;\n wire \\not_strict_mode.app_rd_data_reg[191] ;\n wire \\not_strict_mode.app_rd_data_reg[216] ;\n wire \\not_strict_mode.app_rd_data_reg[217] ;\n wire \\not_strict_mode.app_rd_data_reg[218] ;\n wire \\not_strict_mode.app_rd_data_reg[219] ;\n wire \\not_strict_mode.app_rd_data_reg[220] ;\n wire \\not_strict_mode.app_rd_data_reg[221] ;\n wire \\not_strict_mode.app_rd_data_reg[222] ;\n wire \\not_strict_mode.app_rd_data_reg[223] ;\n wire \\not_strict_mode.app_rd_data_reg[248] ;\n wire \\not_strict_mode.app_rd_data_reg[249] ;\n wire \\not_strict_mode.app_rd_data_reg[24] ;\n wire \\not_strict_mode.app_rd_data_reg[250] ;\n wire \\not_strict_mode.app_rd_data_reg[251] ;\n wire \\not_strict_mode.app_rd_data_reg[252] ;\n wire \\not_strict_mode.app_rd_data_reg[252]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[253] ;\n wire \\not_strict_mode.app_rd_data_reg[254] ;\n wire \\not_strict_mode.app_rd_data_reg[255] ;\n wire [63:0]\\not_strict_mode.app_rd_data_reg[255]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[25] ;\n wire \\not_strict_mode.app_rd_data_reg[26] ;\n wire \\not_strict_mode.app_rd_data_reg[27] ;\n wire \\not_strict_mode.app_rd_data_reg[28] ;\n wire \\not_strict_mode.app_rd_data_reg[29] ;\n wire \\not_strict_mode.app_rd_data_reg[30] ;\n wire \\not_strict_mode.app_rd_data_reg[31] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[31]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[56] ;\n wire \\not_strict_mode.app_rd_data_reg[57] ;\n wire \\not_strict_mode.app_rd_data_reg[58] ;\n wire \\not_strict_mode.app_rd_data_reg[59] ;\n wire \\not_strict_mode.app_rd_data_reg[60] ;\n wire \\not_strict_mode.app_rd_data_reg[61] ;\n wire \\not_strict_mode.app_rd_data_reg[62] ;\n wire \\not_strict_mode.app_rd_data_reg[63] ;\n wire \\not_strict_mode.app_rd_data_reg[88] ;\n wire \\not_strict_mode.app_rd_data_reg[89] ;\n wire \\not_strict_mode.app_rd_data_reg[90] ;\n wire \\not_strict_mode.app_rd_data_reg[91] ;\n wire \\not_strict_mode.app_rd_data_reg[92] ;\n wire \\not_strict_mode.app_rd_data_reg[93] ;\n wire \\not_strict_mode.app_rd_data_reg[94] ;\n wire \\not_strict_mode.app_rd_data_reg[95] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n wire \\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ;\n wire p_0_out;\n wire [1:0]\\po_stg2_wrcal_cnt_reg[1] ;\n wire [1:0]\\rd_mux_sel_r_reg[1] ;\n wire [1:0]rd_ptr;\n wire \\rd_ptr[0]_i_1_n_0 ;\n wire \\rd_ptr[1]_i_1_n_0 ;\n (* RTL_KEEP = \"true\" *) (* syn_maxfan = \"10\" *) wire [1:0]rd_ptr_timing;\n wire \\rd_ptr_timing[0]_i_1__0_n_0 ;\n wire \\rd_ptr_timing[1]_i_1__4_n_0 ;\n wire \\read_fifo.fifo_out_data_r_reg[6] ;\n (* MAX_FANOUT = \"40\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire wr_en;\n wire [1:0]wr_ptr;\n wire \\wr_ptr[0]_i_1__2_n_0 ;\n wire \\wr_ptr[1]_i_1__2_n_0 ;\n wire \\wr_ptr[1]_i_3_n_0 ;\n wire \\wr_ptr_reg[1]_0 ;\n wire [1:0]NLW_mem_reg_0_3_0_5_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED;\n\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[24] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ),\n .O(\\data_bytes_r_reg[63] [0]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[10]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[58] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ),\n .O(\\data_bytes_r_reg[63] [10]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[11]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[59] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ),\n .O(\\data_bytes_r_reg[63] [11]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[12]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[60] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ),\n .O(\\data_bytes_r_reg[63] [12]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[13]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[61] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ),\n .O(\\data_bytes_r_reg[63] [13]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[14]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[62] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ),\n .O(\\data_bytes_r_reg[63] [14]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[15]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[63] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ),\n .O(\\data_bytes_r_reg[63] [15]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[16]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[88] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ),\n .O(\\data_bytes_r_reg[63] [16]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[17]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[89] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ),\n .O(\\data_bytes_r_reg[63] [17]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[18]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[90] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ),\n .O(\\data_bytes_r_reg[63] [18]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[19]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[91] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ),\n .O(\\data_bytes_r_reg[63] [19]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[25] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ),\n .O(\\data_bytes_r_reg[63] [1]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[20]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[92] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ),\n .O(\\data_bytes_r_reg[63] [20]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[21]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[93] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ),\n .O(\\data_bytes_r_reg[63] [21]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[22]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[94] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ),\n .O(\\data_bytes_r_reg[63] [22]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[23]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[95] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ),\n .O(\\data_bytes_r_reg[63] [23]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[24]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[120] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ),\n .O(\\data_bytes_r_reg[63] [24]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[25]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[121] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ),\n .O(\\data_bytes_r_reg[63] [25]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[26]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[122] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ),\n .O(\\data_bytes_r_reg[63] [26]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[27]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[123] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ),\n .O(\\data_bytes_r_reg[63] [27]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[28]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[124] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ),\n .O(\\data_bytes_r_reg[63] [28]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[29]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[125] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ),\n .O(\\data_bytes_r_reg[63] [29]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[26] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),\n .O(\\data_bytes_r_reg[63] [2]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[30]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[126] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ),\n .O(\\data_bytes_r_reg[63] [30]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[31]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[127] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ),\n .O(\\data_bytes_r_reg[63] [31]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[32]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[152] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ),\n .O(\\data_bytes_r_reg[63] [32]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[33]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[153] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ),\n .O(\\data_bytes_r_reg[63] [33]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[34]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[154] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ),\n .O(\\data_bytes_r_reg[63] [34]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[35]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[155] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ),\n .O(\\data_bytes_r_reg[63] [35]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[36]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[156] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ),\n .O(\\data_bytes_r_reg[63] [36]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[37]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[157] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ),\n .O(\\data_bytes_r_reg[63] [37]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[38]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[158] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ),\n .O(\\data_bytes_r_reg[63] [38]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[39]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[159] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ),\n .O(\\data_bytes_r_reg[63] [39]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[27] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ),\n .O(\\data_bytes_r_reg[63] [3]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[40]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[184] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ),\n .O(\\data_bytes_r_reg[63] [40]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[41]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[185] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ),\n .O(\\data_bytes_r_reg[63] [41]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[42]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[186] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ),\n .O(\\data_bytes_r_reg[63] [42]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[43]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[187] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ),\n .O(\\data_bytes_r_reg[63] [43]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[44]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[188] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ),\n .O(\\data_bytes_r_reg[63] [44]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[45]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[189] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ),\n .O(\\data_bytes_r_reg[63] [45]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[46]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[190] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ),\n .O(\\data_bytes_r_reg[63] [46]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[47]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[191] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ),\n .O(\\data_bytes_r_reg[63] [47]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[48]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[216] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ),\n .O(\\data_bytes_r_reg[63] [48]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[49]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[217] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ),\n .O(\\data_bytes_r_reg[63] [49]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[28] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),\n .O(\\data_bytes_r_reg[63] [4]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[50]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[218] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ),\n .O(\\data_bytes_r_reg[63] [50]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[51]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[219] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ),\n .O(\\data_bytes_r_reg[63] [51]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[52]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[220] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ),\n .O(\\data_bytes_r_reg[63] [52]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[53]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[221] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ),\n .O(\\data_bytes_r_reg[63] [53]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[54]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[222] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ),\n .O(\\data_bytes_r_reg[63] [54]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[55]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[223] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ),\n .O(\\data_bytes_r_reg[63] [55]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[56]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[248] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ),\n .O(\\data_bytes_r_reg[63] [56]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[57]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[249] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ),\n .O(\\data_bytes_r_reg[63] [57]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[58]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[250] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ),\n .O(\\data_bytes_r_reg[63] [58]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[59]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[251] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ),\n .O(\\data_bytes_r_reg[63] [59]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[29] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),\n .O(\\data_bytes_r_reg[63] [5]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[60]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[252]_0 ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ),\n .O(\\data_bytes_r_reg[63] [60]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[61]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[253] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ),\n .O(\\data_bytes_r_reg[63] [61]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[62]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[254] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ),\n .O(\\data_bytes_r_reg[63] [62]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[63]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[255] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ),\n .O(\\data_bytes_r_reg[63] [63]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[30] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),\n .O(\\data_bytes_r_reg[63] [6]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[31] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ),\n .O(\\data_bytes_r_reg[63] [7]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[8]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[56] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ),\n .O(\\data_bytes_r_reg[63] [8]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[9]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[57] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ),\n .O(\\data_bytes_r_reg[63] [9]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[0].mux_rd_fall0_r1[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[56] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ),\n .O(\\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[0].mux_rd_fall0_r[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[56] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ),\n .O(\\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[0].mux_rd_fall1_r1[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[120] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ),\n .O(\\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[0].mux_rd_fall1_r[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[120] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ),\n .O(\\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[0].mux_rd_fall2_r1[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[184] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ),\n .O(\\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[0].mux_rd_fall2_r[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[184] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ),\n .O(\\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[0].mux_rd_fall3_r1[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[248] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ),\n .O(\\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[0].mux_rd_fall3_r[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[248] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ),\n .O(\\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[0].mux_rd_rise0_r1[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[24] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ),\n .O(\\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[0].mux_rd_rise0_r[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[24] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ),\n .O(\\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[0].mux_rd_rise1_r1[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[88] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ),\n .O(\\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[0].mux_rd_rise1_r[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[88] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ),\n .O(\\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[0].mux_rd_rise2_r1[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[152] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ),\n .O(\\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[0].mux_rd_rise2_r[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[152] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ),\n .O(\\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[0].mux_rd_rise3_r1[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[216] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ),\n .O(\\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[0].mux_rd_rise3_r[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[216] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ),\n .O(\\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[1].mux_rd_fall0_r1[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[57] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ),\n .O(\\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[1].mux_rd_fall0_r[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[57] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ),\n .O(\\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[1].mux_rd_fall1_r1[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[121] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ),\n .O(\\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[1].mux_rd_fall1_r[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[121] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ),\n .O(\\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[1].mux_rd_fall2_r1[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[185] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ),\n .O(\\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[1].mux_rd_fall2_r[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[185] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ),\n .O(\\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[1].mux_rd_fall3_r1[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[249] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ),\n .O(\\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[1].mux_rd_fall3_r[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[249] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ),\n .O(\\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[1].mux_rd_rise0_r1[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[25] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ),\n .O(\\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[1].mux_rd_rise0_r[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[25] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ),\n .O(\\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[1].mux_rd_rise1_r1[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[89] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ),\n .O(\\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[1].mux_rd_rise1_r[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[89] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ),\n .O(\\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[1].mux_rd_rise2_r1[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[153] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ),\n .O(\\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[1].mux_rd_rise2_r[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[153] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ),\n .O(\\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[1].mux_rd_rise3_r1[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[217] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ),\n .O(\\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[1].mux_rd_rise3_r[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[217] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ),\n .O(\\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[2].mux_rd_fall0_r1[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[58] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ),\n .O(\\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[2].mux_rd_fall0_r[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[58] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ),\n .O(\\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[2].mux_rd_fall1_r1[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[122] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ),\n .O(\\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[2].mux_rd_fall1_r[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[122] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ),\n .O(\\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[2].mux_rd_fall2_r1[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[186] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ),\n .O(\\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[2].mux_rd_fall2_r[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[186] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ),\n .O(\\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[2].mux_rd_fall3_r1[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[250] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ),\n .O(\\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[2].mux_rd_fall3_r[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[250] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ),\n .O(\\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[2].mux_rd_rise0_r1[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[26] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),\n .O(\\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[2].mux_rd_rise0_r[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[26] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),\n .O(\\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[2].mux_rd_rise1_r1[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[90] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ),\n .O(\\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[2].mux_rd_rise1_r[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[90] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ),\n .O(\\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[2].mux_rd_rise2_r1[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[154] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ),\n .O(\\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[2].mux_rd_rise2_r[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[154] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ),\n .O(\\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[2].mux_rd_rise3_r1[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[218] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ),\n .O(\\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[2].mux_rd_rise3_r[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[218] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ),\n .O(\\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[3].mux_rd_fall0_r1[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[59] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ),\n .O(\\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[3].mux_rd_fall0_r[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[59] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ),\n .O(\\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[3].mux_rd_fall1_r1[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[123] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ),\n .O(\\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[3].mux_rd_fall1_r[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[123] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ),\n .O(\\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[3].mux_rd_fall2_r1[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[187] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ),\n .O(\\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[3].mux_rd_fall2_r[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[187] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ),\n .O(\\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[3].mux_rd_fall3_r1[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[251] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ),\n .O(\\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[3].mux_rd_fall3_r[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[251] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ),\n .O(\\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[3].mux_rd_rise0_r1[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[27] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ),\n .O(\\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[3].mux_rd_rise0_r[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[27] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ),\n .O(\\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[3].mux_rd_rise1_r1[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[91] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ),\n .O(\\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[3].mux_rd_rise1_r[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[91] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ),\n .O(\\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[3].mux_rd_rise2_r1[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[155] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ),\n .O(\\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[3].mux_rd_rise2_r[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[155] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ),\n .O(\\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[3].mux_rd_rise3_r1[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[219] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ),\n .O(\\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[3].mux_rd_rise3_r[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[219] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ),\n .O(\\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[4].mux_rd_fall0_r1[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[60] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ),\n .O(\\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[4].mux_rd_fall0_r[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[60] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ),\n .O(\\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[4].mux_rd_fall1_r1[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[124] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ),\n .O(\\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[4].mux_rd_fall1_r[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[124] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ),\n .O(\\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[4].mux_rd_fall2_r1[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[188] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ),\n .O(\\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[4].mux_rd_fall2_r[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[188] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ),\n .O(\\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[4].mux_rd_fall3_r1[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[252]_0 ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ),\n .O(\\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[4].mux_rd_fall3_r[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[252]_0 ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ),\n .O(\\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[4].mux_rd_rise0_r1[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[28] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),\n .O(\\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[4].mux_rd_rise0_r[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[28] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),\n .O(\\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[4].mux_rd_rise1_r1[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[92] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ),\n .O(\\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[4].mux_rd_rise1_r[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[92] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ),\n .O(\\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[4].mux_rd_rise2_r1[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[156] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ),\n .O(\\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[4].mux_rd_rise2_r[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[156] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ),\n .O(\\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[4].mux_rd_rise3_r1[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[220] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ),\n .O(\\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[4].mux_rd_rise3_r[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[220] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ),\n .O(\\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[5].mux_rd_fall0_r1[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[61] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ),\n .O(\\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[5].mux_rd_fall0_r[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[61] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ),\n .O(\\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[5].mux_rd_fall1_r1[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[125] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ),\n .O(\\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[5].mux_rd_fall1_r[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[125] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ),\n .O(\\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[5].mux_rd_fall2_r1[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[189] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ),\n .O(\\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[5].mux_rd_fall2_r[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[189] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ),\n .O(\\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[5].mux_rd_fall3_r1[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[253] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ),\n .O(\\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[5].mux_rd_fall3_r[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[253] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ),\n .O(\\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[5].mux_rd_rise0_r1[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[29] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),\n .O(\\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[5].mux_rd_rise0_r[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[29] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),\n .O(\\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[5].mux_rd_rise1_r1[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[93] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ),\n .O(\\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[5].mux_rd_rise1_r[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[93] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ),\n .O(\\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[5].mux_rd_rise2_r1[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[157] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ),\n .O(\\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[5].mux_rd_rise2_r[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[157] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ),\n .O(\\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[5].mux_rd_rise3_r1[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[221] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ),\n .O(\\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[5].mux_rd_rise3_r[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[221] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ),\n .O(\\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[6].mux_rd_fall0_r1[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[62] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ),\n .O(\\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[6].mux_rd_fall0_r[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[62] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ),\n .O(\\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[6].mux_rd_fall1_r1[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[126] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ),\n .O(\\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[6].mux_rd_fall1_r[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[126] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ),\n .O(\\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[6].mux_rd_fall2_r1[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[190] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ),\n .O(\\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[6].mux_rd_fall2_r[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[190] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ),\n .O(\\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[6].mux_rd_fall3_r1[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[254] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ),\n .O(\\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[6].mux_rd_fall3_r[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[254] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ),\n .O(\\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[6].mux_rd_rise0_r1[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[30] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),\n .O(\\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[6].mux_rd_rise0_r[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[30] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),\n .O(\\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[6].mux_rd_rise1_r1[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[94] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ),\n .O(\\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[6].mux_rd_rise1_r[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[94] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ),\n .O(\\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[6].mux_rd_rise2_r1[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[158] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ),\n .O(\\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[6].mux_rd_rise2_r[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[158] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ),\n .O(\\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[6].mux_rd_rise3_r1[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[222] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ),\n .O(\\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[6].mux_rd_rise3_r[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[222] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ),\n .O(\\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[7].mux_rd_fall0_r1[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[63] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ),\n .O(\\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[7].mux_rd_fall0_r[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[63] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ),\n .O(\\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[7].mux_rd_fall1_r1[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[127] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ),\n .O(\\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[7].mux_rd_fall1_r[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[127] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ),\n .O(\\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[7].mux_rd_fall2_r1[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[191] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ),\n .O(\\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[7].mux_rd_fall2_r[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[191] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ),\n .O(\\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[7].mux_rd_fall3_r1[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[255] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ),\n .O(\\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[7].mux_rd_fall3_r[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[255] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ),\n .O(\\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[7].mux_rd_rise0_r1[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[31] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ),\n .O(\\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[7].mux_rd_rise0_r[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[31] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ),\n .O(\\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[7].mux_rd_rise1_r1[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[95] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ),\n .O(\\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[7].mux_rd_rise1_r[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[95] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ),\n .O(\\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[7].mux_rd_rise2_r1[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[159] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ),\n .O(\\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[7].mux_rd_rise2_r[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[159] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ),\n .O(\\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[7].mux_rd_rise3_r1[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[223] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ),\n .O(\\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[7].mux_rd_rise3_r[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[223] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ),\n .O(\\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[56] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[120] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[184] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[248] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[24] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[88] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ),\n .O(p_0_out));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[216] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[57] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[121] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[185] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[249] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[25] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[89] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[153] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[217] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[58] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[122] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[186] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[250] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[26] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[90] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[154] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[218] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[59] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[123] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[187] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[251] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[27] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[91] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[155] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[60] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[124] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[188] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[252]_0 ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[28] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[92] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[220] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[61] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[125] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[189] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[253] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[29] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[93] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[157] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[221] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[62] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[126] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[190] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[254] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[30] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[94] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[158] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[222] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[63] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[127] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[191] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[255] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[31] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[95] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[159] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[152] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ),\n .O(\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[219] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ),\n .O(\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[156] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ),\n .O(\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[223] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ),\n .O(\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_0_5\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[1:0]),\n .DIB(Q[3:2]),\n .DIC(Q[5:4]),\n .DID({1'b0,1'b0}),\n .DOA({mem_out[1],\\not_strict_mode.app_rd_data_reg[31]_0 }),\n .DOB(mem_out[3:2]),\n .DOC(mem_out[5:4]),\n .DOD(NLW_mem_reg_0_3_0_5_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n LUT4 #(\n .INIT(16'h0151)) \n mem_reg_0_3_0_5_i_1\n (.I0(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I1(my_full[0]),\n .I2(\\wr_ptr[1]_i_3_n_0 ),\n .I3(my_empty_0[2]),\n .O(wr_en));\n LUT1 #(\n .INIT(2'h2)) \n mem_reg_0_3_0_5_i_2\n (.I0(\\wr_ptr_reg[1]_0 ),\n .O(my_empty_0[2]));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_12_17\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[13:12]),\n .DIB(Q[15:14]),\n .DIC(Q[17:16]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[13:12]),\n .DOB(mem_out[15:14]),\n .DOC(mem_out[17:16]),\n .DOD(NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_18_23\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[19:18]),\n .DIB(Q[21:20]),\n .DIC(Q[23:22]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[19:18]),\n .DOB(mem_out[21:20]),\n .DOC(mem_out[23:22]),\n .DOD(NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_24_29\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[25:24]),\n .DIB(Q[27:26]),\n .DIC(Q[29:28]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[25:24]),\n .DOB(mem_out[27:26]),\n .DOC(mem_out[29:28]),\n .DOD(NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_30_35\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[31:30]),\n .DIB(Q[33:32]),\n .DIC(Q[35:34]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[31:30]),\n .DOB(mem_out[33:32]),\n .DOC(mem_out[35:34]),\n .DOD(NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_36_41\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[37:36]),\n .DIB(Q[39:38]),\n .DIC(Q[41:40]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[37:36]),\n .DOB(mem_out[39:38]),\n .DOC(mem_out[41:40]),\n .DOD(NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_42_47\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[43:42]),\n .DIB(Q[45:44]),\n .DIC(Q[47:46]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[43:42]),\n .DOB(mem_out[45:44]),\n .DOC(mem_out[47:46]),\n .DOD(NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_48_53\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[49:48]),\n .DIB(Q[51:50]),\n .DIC(Q[53:52]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[49:48]),\n .DOB(mem_out[51:50]),\n .DOC(mem_out[53:52]),\n .DOD(NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_54_59\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[55:54]),\n .DIB(Q[57:56]),\n .DIC(Q[59:58]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[55:54]),\n .DOB(mem_out[57:56]),\n .DOC(mem_out[59:58]),\n .DOD(NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_60_65\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[61:60]),\n .DIB(Q[63:62]),\n .DIC(Q[65:64]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[61:60]),\n .DOB(mem_out[63:62]),\n .DOC({mem_reg_0_3_60_65_n_4,mem_reg_0_3_60_65_n_5}),\n .DOD(NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_3_6_11\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[7:6]),\n .DIB(Q[9:8]),\n .DIC(Q[11:10]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[7:6]),\n .DOB(mem_out[9:8]),\n .DOC(mem_out[11:10]),\n .DOD(NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n LUT4 #(\n .INIT(16'h0140)) \n \\my_empty[4]_i_1__2 \n (.I0(my_full[1]),\n .I1(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I2(\\wr_ptr[1]_i_3_n_0 ),\n .I3(my_empty_0[1]),\n .O(\\my_empty[4]_i_1__2_n_0 ));\n LUT5 #(\n .INIT(32'h00000960)) \n \\my_empty[4]_i_2 \n (.I0(wr_ptr[1]),\n .I1(rd_ptr[1]),\n .I2(rd_ptr[0]),\n .I3(wr_ptr[0]),\n .I4(my_empty_0[1]),\n .O(\\my_empty[4]_i_2_n_0 ));\n (* ORIG_CELL_NAME = \"my_empty_reg[4]\" *) \n FDSE #(\n .INIT(1'b1)) \n \\my_empty_reg[4] \n (.C(CLK),\n .CE(\\my_empty[4]_i_1__2_n_0 ),\n .D(\\my_empty[4]_i_2_n_0 ),\n .Q(\\wr_ptr_reg[1]_0 ),\n .S(ififo_rst));\n (* ORIG_CELL_NAME = \"my_empty_reg[4]\" *) \n FDSE #(\n .INIT(1'b1)) \n \\my_empty_reg[4]_rep \n (.C(CLK),\n .CE(\\my_empty[4]_i_1__2_n_0 ),\n .D(\\my_empty[4]_i_2_n_0 ),\n .Q(\\my_empty_reg[4]_rep_n_0 ),\n .S(ififo_rst));\n (* ORIG_CELL_NAME = \"my_empty_reg[4]\" *) \n FDSE #(\n .INIT(1'b1)) \n \\my_empty_reg[4]_rep__0 \n (.C(CLK),\n .CE(\\my_empty[4]_i_1__2_n_0 ),\n .D(\\my_empty[4]_i_2_n_0 ),\n .Q(\\my_empty_reg[4]_rep__0_n_0 ),\n .S(ififo_rst));\n LUT6 #(\n .INIT(64'hBAAAAAAB8AAAAAA8)) \n \\my_full[0]_i_1 \n (.I0(my_full[0]),\n .I1(my_empty_0[1]),\n .I2(my_full[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I4(\\wr_ptr[1]_i_3_n_0 ),\n .I5(\\my_full[0]_i_2_n_0 ),\n .O(\\my_full[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h00000960)) \n \\my_full[0]_i_2 \n (.I0(rd_ptr[1]),\n .I1(wr_ptr[1]),\n .I2(wr_ptr[0]),\n .I3(rd_ptr[0]),\n .I4(my_full[1]),\n .O(\\my_full[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAA00411400)) \n \\my_full[1]_i_1 \n (.I0(\\my_full[1]_i_2_n_0 ),\n .I1(rd_ptr[1]),\n .I2(wr_ptr[1]),\n .I3(wr_ptr[0]),\n .I4(rd_ptr[0]),\n .I5(my_full[1]),\n .O(\\my_full[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair731\" *) \n LUT4 #(\n .INIT(16'hBFFE)) \n \\my_full[1]_i_2 \n (.I0(my_empty_0[1]),\n .I1(my_full[1]),\n .I2(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I3(\\wr_ptr[1]_i_3_n_0 ),\n .O(\\my_full[1]_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\my_full_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_full[0]_i_1_n_0 ),\n .Q(my_full[0]),\n .R(ififo_rst));\n FDRE #(\n .INIT(1'b0)) \n \\my_full_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_full[1]_i_1_n_0 ),\n .Q(my_full[1]),\n .R(ififo_rst));\n (* SOFT_HLUTNM = \"soft_lutpair757\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[120]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[120] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [24]));\n (* SOFT_HLUTNM = \"soft_lutpair758\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[121]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[121] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [25]));\n (* SOFT_HLUTNM = \"soft_lutpair759\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[122]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[122] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [26]));\n (* SOFT_HLUTNM = \"soft_lutpair760\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[123]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[123] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [27]));\n (* SOFT_HLUTNM = \"soft_lutpair761\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[124]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[124] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [28]));\n (* SOFT_HLUTNM = \"soft_lutpair762\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[125]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[125] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [29]));\n (* SOFT_HLUTNM = \"soft_lutpair763\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[126]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[126] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [30]));\n (* SOFT_HLUTNM = \"soft_lutpair764\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[127]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[127] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [31]));\n (* SOFT_HLUTNM = \"soft_lutpair764\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[152]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[152] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [32]));\n (* SOFT_HLUTNM = \"soft_lutpair763\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[153]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[153] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [33]));\n (* SOFT_HLUTNM = \"soft_lutpair762\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[154]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[154] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [34]));\n (* SOFT_HLUTNM = \"soft_lutpair761\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[155]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[155] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [35]));\n (* SOFT_HLUTNM = \"soft_lutpair760\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[156]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[156] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [36]));\n (* SOFT_HLUTNM = \"soft_lutpair759\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[157]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[157] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [37]));\n (* SOFT_HLUTNM = \"soft_lutpair758\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[158]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[158] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [38]));\n (* SOFT_HLUTNM = \"soft_lutpair757\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[159]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[159] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [39]));\n (* SOFT_HLUTNM = \"soft_lutpair756\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[184]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[184] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [40]));\n (* SOFT_HLUTNM = \"soft_lutpair755\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[185]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[185] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [41]));\n (* SOFT_HLUTNM = \"soft_lutpair754\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[186]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[186] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [42]));\n (* SOFT_HLUTNM = \"soft_lutpair753\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[187]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[187] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [43]));\n (* SOFT_HLUTNM = \"soft_lutpair752\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[188]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[188] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [44]));\n (* SOFT_HLUTNM = \"soft_lutpair751\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[189]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[189] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [45]));\n (* SOFT_HLUTNM = \"soft_lutpair750\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[190]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[190] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [46]));\n (* SOFT_HLUTNM = \"soft_lutpair749\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[191]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[191] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [47]));\n (* SOFT_HLUTNM = \"soft_lutpair748\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[216]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[216] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [48]));\n (* SOFT_HLUTNM = \"soft_lutpair747\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[217]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[217] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [49]));\n (* SOFT_HLUTNM = \"soft_lutpair746\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[218]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[218] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [50]));\n (* SOFT_HLUTNM = \"soft_lutpair745\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[219]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[219] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [51]));\n (* SOFT_HLUTNM = \"soft_lutpair744\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[220]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[220] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [52]));\n (* SOFT_HLUTNM = \"soft_lutpair743\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[221]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[221] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [53]));\n (* SOFT_HLUTNM = \"soft_lutpair742\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[222]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[222] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [54]));\n (* SOFT_HLUTNM = \"soft_lutpair741\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[223]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[223] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [55]));\n (* SOFT_HLUTNM = \"soft_lutpair740\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[248]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[248] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [56]));\n (* SOFT_HLUTNM = \"soft_lutpair739\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[249]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[249] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [57]));\n (* SOFT_HLUTNM = \"soft_lutpair733\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[24]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[24] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair738\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[250]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[250] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [58]));\n (* SOFT_HLUTNM = \"soft_lutpair737\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[251]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[251] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [59]));\n (* SOFT_HLUTNM = \"soft_lutpair736\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[252]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[252]_0 ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [60]));\n (* SOFT_HLUTNM = \"soft_lutpair735\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[253]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[253] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [61]));\n (* SOFT_HLUTNM = \"soft_lutpair734\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[254]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[254] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [62]));\n (* SOFT_HLUTNM = \"soft_lutpair733\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[255]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[255] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [63]));\n (* SOFT_HLUTNM = \"soft_lutpair734\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[25]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[25] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [1]));\n (* SOFT_HLUTNM = \"soft_lutpair735\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[26]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[26] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [2]));\n (* SOFT_HLUTNM = \"soft_lutpair736\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[27]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[27] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [3]));\n (* SOFT_HLUTNM = \"soft_lutpair737\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[28]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[28] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [4]));\n (* SOFT_HLUTNM = \"soft_lutpair738\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[29]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[29] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [5]));\n (* SOFT_HLUTNM = \"soft_lutpair739\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[30]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[30] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [6]));\n (* SOFT_HLUTNM = \"soft_lutpair740\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[31]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[31] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [7]));\n (* SOFT_HLUTNM = \"soft_lutpair741\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[56]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[56] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [8]));\n (* SOFT_HLUTNM = \"soft_lutpair742\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[57]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[57] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [9]));\n (* SOFT_HLUTNM = \"soft_lutpair743\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[58]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[58] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [10]));\n (* SOFT_HLUTNM = \"soft_lutpair744\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[59]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[59] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [11]));\n (* SOFT_HLUTNM = \"soft_lutpair745\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[60]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[60] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [12]));\n (* SOFT_HLUTNM = \"soft_lutpair746\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[61]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[61] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [13]));\n (* SOFT_HLUTNM = \"soft_lutpair747\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[62]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[62] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [14]));\n (* SOFT_HLUTNM = \"soft_lutpair748\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[63]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[63] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [15]));\n (* SOFT_HLUTNM = \"soft_lutpair749\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[88]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[88] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [16]));\n (* SOFT_HLUTNM = \"soft_lutpair750\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[89]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[89] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [17]));\n (* SOFT_HLUTNM = \"soft_lutpair751\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[90]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[90] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [18]));\n (* SOFT_HLUTNM = \"soft_lutpair752\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[91]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[91] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [19]));\n (* SOFT_HLUTNM = \"soft_lutpair753\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[92]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[92] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [20]));\n (* SOFT_HLUTNM = \"soft_lutpair754\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[93]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[93] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [21]));\n (* SOFT_HLUTNM = \"soft_lutpair755\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[94]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[94] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [22]));\n (* SOFT_HLUTNM = \"soft_lutpair756\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[95]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[95] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [23]));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_3 \n (.I0(Q[1]),\n .I1(mem_out[1]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[63] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_4 \n (.I0(Q[9]),\n .I1(mem_out[9]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[62] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_5 \n (.I0(Q[17]),\n .I1(mem_out[17]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[61] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_6 \n (.I0(Q[25]),\n .I1(mem_out[25]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[60] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_1 \n (.I0(Q[50]),\n .I1(mem_out[50]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[89] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_2 \n (.I0(Q[58]),\n .I1(mem_out[58]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[88] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_1 \n (.I0(Q[2]),\n .I1(mem_out[2]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[95] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_2 \n (.I0(Q[10]),\n .I1(mem_out[10]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[94] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_3 \n (.I0(Q[18]),\n .I1(mem_out[18]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[93] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_4 \n (.I0(Q[26]),\n .I1(mem_out[26]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[92] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_5 \n (.I0(Q[34]),\n .I1(mem_out[34]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[91] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_6 \n (.I0(Q[42]),\n .I1(mem_out[42]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[90] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_1 \n (.I0(Q[19]),\n .I1(mem_out[19]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[125] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_2 \n (.I0(Q[27]),\n .I1(mem_out[27]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[124] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_3 \n (.I0(Q[35]),\n .I1(mem_out[35]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[123] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_4 \n (.I0(Q[43]),\n .I1(mem_out[43]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[122] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_5 \n (.I0(Q[51]),\n .I1(mem_out[51]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[121] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_6 \n (.I0(Q[59]),\n .I1(mem_out[59]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[120] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_5 \n (.I0(Q[3]),\n .I1(mem_out[3]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[127] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_6 \n (.I0(Q[11]),\n .I1(mem_out[11]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[126] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_1 \n (.I0(Q[36]),\n .I1(mem_out[36]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[155] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_2 \n (.I0(Q[44]),\n .I1(mem_out[44]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[154] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_3 \n (.I0(Q[52]),\n .I1(mem_out[52]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[153] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_4 \n (.I0(Q[60]),\n .I1(mem_out[60]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[152] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_3 \n (.I0(Q[4]),\n .I1(mem_out[4]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[159] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_4 \n (.I0(Q[12]),\n .I1(mem_out[12]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[158] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_5 \n (.I0(Q[20]),\n .I1(mem_out[20]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[157] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_6 \n (.I0(Q[28]),\n .I1(mem_out[28]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[156] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_1 \n (.I0(Q[53]),\n .I1(mem_out[53]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[185] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_2 \n (.I0(Q[61]),\n .I1(mem_out[61]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[184] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_1 \n (.I0(Q[5]),\n .I1(mem_out[5]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[191] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_2 \n (.I0(Q[13]),\n .I1(mem_out[13]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[190] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_3 \n (.I0(Q[21]),\n .I1(mem_out[21]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[189] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_4 \n (.I0(Q[29]),\n .I1(mem_out[29]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[188] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_5 \n (.I0(Q[37]),\n .I1(mem_out[37]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[187] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_6 \n (.I0(Q[45]),\n .I1(mem_out[45]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[186] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_1 \n (.I0(Q[22]),\n .I1(mem_out[22]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[221] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_2 \n (.I0(Q[30]),\n .I1(mem_out[30]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[220] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_3 \n (.I0(Q[38]),\n .I1(mem_out[38]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[219] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_4 \n (.I0(Q[46]),\n .I1(mem_out[46]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[218] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_5 \n (.I0(Q[54]),\n .I1(mem_out[54]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[217] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_6 \n (.I0(Q[62]),\n .I1(mem_out[62]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[216] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_5 \n (.I0(Q[6]),\n .I1(mem_out[6]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[223] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_6 \n (.I0(Q[14]),\n .I1(mem_out[14]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[222] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_1 \n (.I0(Q[39]),\n .I1(mem_out[39]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[251] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_2 \n (.I0(Q[47]),\n .I1(mem_out[47]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[250] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_3 \n (.I0(Q[55]),\n .I1(mem_out[55]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[249] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_4 \n (.I0(Q[63]),\n .I1(mem_out[63]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[248] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_1 \n (.I0(Q[7]),\n .I1(mem_out[7]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[255] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_2 \n (.I0(Q[15]),\n .I1(mem_out[15]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[254] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_3 \n (.I0(Q[23]),\n .I1(mem_out[23]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[253] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_4 \n (.I0(Q[31]),\n .I1(mem_out[31]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[252]_0 ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_1 \n (.I0(Q[16]),\n .I1(mem_out[16]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[29] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_2 \n (.I0(Q[24]),\n .I1(mem_out[24]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[28] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_3 \n (.I0(Q[32]),\n .I1(mem_out[32]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[27] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_4 \n (.I0(Q[40]),\n .I1(mem_out[40]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[26] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_5 \n (.I0(Q[48]),\n .I1(mem_out[48]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[25] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_6 \n (.I0(Q[56]),\n .I1(mem_out[56]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[24] ));\n LUT1 #(\n .INIT(2'h2)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_7 \n (.I0(\\my_empty_reg[4]_rep_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[252] ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8 \n (.I0(\\my_empty_reg[4]_rep__0_n_0 ),\n .O(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_5 \n (.I0(Q[0]),\n .I1(\\not_strict_mode.app_rd_data_reg[31]_0 ),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[31] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_6 \n (.I0(Q[8]),\n .I1(mem_out[8]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[30] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_1 \n (.I0(Q[33]),\n .I1(mem_out[33]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[59] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_2 \n (.I0(Q[41]),\n .I1(mem_out[41]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[58] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_3 \n (.I0(Q[49]),\n .I1(mem_out[49]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[57] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_4 \n (.I0(Q[57]),\n .I1(mem_out[57]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[56] ));\n (* SOFT_HLUTNM = \"soft_lutpair732\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\rd_ptr[0]_i_1 \n (.I0(my_empty_0[1]),\n .I1(\\wr_ptr[1]_i_3_n_0 ),\n .I2(rd_ptr[0]),\n .O(\\rd_ptr[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair732\" *) \n LUT4 #(\n .INIT(16'hDF20)) \n \\rd_ptr[1]_i_1 \n (.I0(rd_ptr[0]),\n .I1(my_empty_0[1]),\n .I2(\\wr_ptr[1]_i_3_n_0 ),\n .I3(rd_ptr[1]),\n .O(\\rd_ptr[1]_i_1_n_0 ));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_ptr[0]_i_1_n_0 ),\n .Q(rd_ptr[0]),\n .R(ififo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_ptr[1]_i_1_n_0 ),\n .Q(rd_ptr[1]),\n .R(ififo_rst));\n LUT4 #(\n .INIT(16'hA2AE)) \n \\rd_ptr_timing[0]_i_1__0 \n (.I0(rd_ptr_timing[0]),\n .I1(\\wr_ptr[1]_i_3_n_0 ),\n .I2(my_empty_0[1]),\n .I3(rd_ptr[0]),\n .O(\\rd_ptr_timing[0]_i_1__0_n_0 ));\n LUT5 #(\n .INIT(32'hF0F066F0)) \n \\rd_ptr_timing[1]_i_1__4 \n (.I0(rd_ptr[0]),\n .I1(rd_ptr[1]),\n .I2(rd_ptr_timing[1]),\n .I3(\\wr_ptr[1]_i_3_n_0 ),\n .I4(my_empty_0[1]),\n .O(\\rd_ptr_timing[1]_i_1__4_n_0 ));\n (* KEEP = \"yes\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_ptr_timing[0]_i_1__0_n_0 ),\n .Q(rd_ptr_timing[0]),\n .R(ififo_rst));\n (* KEEP = \"yes\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_ptr_timing[1]_i_1__4_n_0 ),\n .Q(rd_ptr_timing[1]),\n .R(ififo_rst));\n (* SOFT_HLUTNM = \"soft_lutpair731\" *) \n LUT5 #(\n .INIT(32'hEEFA1105)) \n \\wr_ptr[0]_i_1__2 \n (.I0(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I1(my_empty_0[1]),\n .I2(my_full[1]),\n .I3(\\wr_ptr[1]_i_3_n_0 ),\n .I4(wr_ptr[0]),\n .O(\\wr_ptr[0]_i_1__2_n_0 ));\n LUT6 #(\n .INIT(64'hFDFDFFDD02020022)) \n \\wr_ptr[1]_i_1__2 \n (.I0(wr_ptr[0]),\n .I1(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I2(my_empty_0[1]),\n .I3(my_full[1]),\n .I4(\\wr_ptr[1]_i_3_n_0 ),\n .I5(wr_ptr[1]),\n .O(\\wr_ptr[1]_i_1__2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair765\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\wr_ptr[1]_i_2 \n (.I0(\\wr_ptr_reg[1]_0 ),\n .O(my_empty_0[1]));\n LUT6 #(\n .INIT(64'h0000700070007000)) \n \\wr_ptr[1]_i_3 \n (.I0(my_empty_0[3]),\n .I1(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I2(D_byte_rd_en),\n .I3(B_byte_rd_en),\n .I4(if_empty_r_0),\n .I5(my_empty),\n .O(\\wr_ptr[1]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair765\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\wr_ptr[1]_i_4 \n (.I0(\\wr_ptr_reg[1]_0 ),\n .O(my_empty_0[3]));\n LUT2 #(\n .INIT(4'h7)) \n \\wr_ptr[1]_i_5 \n (.I0(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I1(my_empty_0[3]),\n .O(A_byte_rd_en));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_ptr[0]_i_1__2_n_0 ),\n .Q(wr_ptr[0]),\n .R(ififo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_ptr[1]_i_1__2_n_0 ),\n .Q(wr_ptr[1]),\n .R(ififo_rst));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_mc_phy\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_mc_phy\n (\\rd_ptr_timing_reg[2] ,\n \\rd_ptr_timing_reg[2]_0 ,\n \\rd_ptr_timing_reg[2]_1 ,\n \\rd_ptr_timing_reg[2]_2 ,\n \\rd_ptr_timing_reg[2]_3 ,\n \\rd_ptr_timing_reg[2]_4 ,\n \\rd_ptr_timing_reg[2]_5 ,\n \\rd_ptr_timing_reg[2]_6 ,\n \\rd_ptr_timing_reg[2]_7 ,\n \\rd_ptr_timing_reg[2]_8 ,\n \\rd_ptr_timing_reg[2]_9 ,\n \\rd_ptr_timing_reg[2]_10 ,\n \\pi_dqs_found_lanes_r1_reg[3] ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,\n mem_dqs_out,\n mem_dqs_ts,\n mem_dq_out,\n mem_dq_ts,\n idelay_ld_rst,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,\n idelay_ld_rst_0,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,\n idelay_ld_rst_1,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,\n idelay_ld_rst_2,\n \\calib_seq_reg[0] ,\n \\not_strict_mode.app_rd_data_reg[252] ,\n \\not_strict_mode.app_rd_data_reg[244] ,\n \\not_strict_mode.app_rd_data_reg[236] ,\n \\not_strict_mode.app_rd_data_reg[228] ,\n \\my_empty_reg[1] ,\n \\my_empty_reg[1]_0 ,\n phy_mc_ctl_full,\n \\my_empty_reg[1]_1 ,\n \\my_empty_reg[1]_2 ,\n \\my_empty_reg[1]_3 ,\n \\my_empty_reg[1]_4 ,\n \\my_empty_reg[1]_5 ,\n rd_buf_we,\n \\not_strict_mode.status_ram.rd_buf_we_r1_reg ,\n \\my_empty_reg[1]_6 ,\n phy_rddata_en,\n mux_rd_valid_r_reg,\n rst_sync_r1_reg,\n \\byte_r_reg[0] ,\n \\po_counter_read_val_r_reg[5] ,\n \\data_bytes_r_reg[63] ,\n \\not_strict_mode.app_rd_data_reg[255] ,\n \\not_strict_mode.app_rd_data_reg[239] ,\n \\not_strict_mode.app_rd_data_reg[247] ,\n \\not_strict_mode.app_rd_data_reg[231] ,\n \\not_strict_mode.app_rd_data_reg[254] ,\n \\not_strict_mode.app_rd_data_reg[238] ,\n \\not_strict_mode.app_rd_data_reg[246] ,\n \\not_strict_mode.app_rd_data_reg[230] ,\n \\not_strict_mode.app_rd_data_reg[253] ,\n \\not_strict_mode.app_rd_data_reg[237] ,\n \\not_strict_mode.app_rd_data_reg[245] ,\n \\not_strict_mode.app_rd_data_reg[229] ,\n \\not_strict_mode.app_rd_data_reg[252]_0 ,\n \\not_strict_mode.app_rd_data_reg[236]_0 ,\n \\not_strict_mode.app_rd_data_reg[244]_0 ,\n \\not_strict_mode.app_rd_data_reg[228]_0 ,\n \\not_strict_mode.app_rd_data_reg[251] ,\n \\not_strict_mode.app_rd_data_reg[235] ,\n \\not_strict_mode.app_rd_data_reg[243] ,\n \\not_strict_mode.app_rd_data_reg[227] ,\n \\not_strict_mode.app_rd_data_reg[250] ,\n \\not_strict_mode.app_rd_data_reg[234] ,\n \\not_strict_mode.app_rd_data_reg[242] ,\n \\not_strict_mode.app_rd_data_reg[226] ,\n \\not_strict_mode.app_rd_data_reg[249] ,\n \\not_strict_mode.app_rd_data_reg[233] ,\n \\not_strict_mode.app_rd_data_reg[241] ,\n \\not_strict_mode.app_rd_data_reg[225] ,\n \\not_strict_mode.app_rd_data_reg[248] ,\n \\not_strict_mode.app_rd_data_reg[232] ,\n \\not_strict_mode.app_rd_data_reg[240] ,\n \\not_strict_mode.app_rd_data_reg[224] ,\n \\not_strict_mode.app_rd_data_reg[223] ,\n \\not_strict_mode.app_rd_data_reg[207] ,\n \\not_strict_mode.app_rd_data_reg[215] ,\n \\not_strict_mode.app_rd_data_reg[199] ,\n \\not_strict_mode.app_rd_data_reg[222] ,\n \\not_strict_mode.app_rd_data_reg[206] ,\n \\not_strict_mode.app_rd_data_reg[214] ,\n \\not_strict_mode.app_rd_data_reg[198] ,\n \\not_strict_mode.app_rd_data_reg[221] ,\n \\not_strict_mode.app_rd_data_reg[205] ,\n \\not_strict_mode.app_rd_data_reg[213] ,\n \\not_strict_mode.app_rd_data_reg[197] ,\n \\not_strict_mode.app_rd_data_reg[220] ,\n \\not_strict_mode.app_rd_data_reg[204] ,\n \\not_strict_mode.app_rd_data_reg[212] ,\n \\not_strict_mode.app_rd_data_reg[196] ,\n \\not_strict_mode.app_rd_data_reg[219] ,\n \\not_strict_mode.app_rd_data_reg[203] ,\n \\not_strict_mode.app_rd_data_reg[211] ,\n \\not_strict_mode.app_rd_data_reg[195] ,\n \\not_strict_mode.app_rd_data_reg[218] ,\n \\not_strict_mode.app_rd_data_reg[202] ,\n \\not_strict_mode.app_rd_data_reg[210] ,\n \\not_strict_mode.app_rd_data_reg[194] ,\n \\not_strict_mode.app_rd_data_reg[217] ,\n \\not_strict_mode.app_rd_data_reg[201] ,\n \\not_strict_mode.app_rd_data_reg[209] ,\n \\not_strict_mode.app_rd_data_reg[193] ,\n \\not_strict_mode.app_rd_data_reg[216] ,\n \\not_strict_mode.app_rd_data_reg[200] ,\n \\not_strict_mode.app_rd_data_reg[208] ,\n \\not_strict_mode.app_rd_data_reg[192] ,\n \\not_strict_mode.app_rd_data_reg[191] ,\n \\not_strict_mode.app_rd_data_reg[175] ,\n \\not_strict_mode.app_rd_data_reg[183] ,\n \\not_strict_mode.app_rd_data_reg[167] ,\n \\not_strict_mode.app_rd_data_reg[190] ,\n \\not_strict_mode.app_rd_data_reg[174] ,\n \\not_strict_mode.app_rd_data_reg[182] ,\n \\not_strict_mode.app_rd_data_reg[166] ,\n \\not_strict_mode.app_rd_data_reg[189] ,\n \\not_strict_mode.app_rd_data_reg[173] ,\n \\not_strict_mode.app_rd_data_reg[181] ,\n \\not_strict_mode.app_rd_data_reg[165] ,\n \\not_strict_mode.app_rd_data_reg[188] ,\n \\not_strict_mode.app_rd_data_reg[172] ,\n \\not_strict_mode.app_rd_data_reg[180] ,\n \\not_strict_mode.app_rd_data_reg[164] ,\n \\not_strict_mode.app_rd_data_reg[187] ,\n \\not_strict_mode.app_rd_data_reg[171] ,\n \\not_strict_mode.app_rd_data_reg[179] ,\n \\not_strict_mode.app_rd_data_reg[163] ,\n \\not_strict_mode.app_rd_data_reg[186] ,\n \\not_strict_mode.app_rd_data_reg[170] ,\n \\not_strict_mode.app_rd_data_reg[178] ,\n \\not_strict_mode.app_rd_data_reg[162] ,\n \\not_strict_mode.app_rd_data_reg[185] ,\n \\not_strict_mode.app_rd_data_reg[169] ,\n \\not_strict_mode.app_rd_data_reg[177] ,\n \\not_strict_mode.app_rd_data_reg[161] ,\n \\not_strict_mode.app_rd_data_reg[184] ,\n \\not_strict_mode.app_rd_data_reg[168] ,\n \\not_strict_mode.app_rd_data_reg[176] ,\n \\not_strict_mode.app_rd_data_reg[160] ,\n \\not_strict_mode.app_rd_data_reg[159] ,\n \\not_strict_mode.app_rd_data_reg[143] ,\n \\not_strict_mode.app_rd_data_reg[151] ,\n \\not_strict_mode.app_rd_data_reg[135] ,\n \\not_strict_mode.app_rd_data_reg[158] ,\n \\not_strict_mode.app_rd_data_reg[142] ,\n \\not_strict_mode.app_rd_data_reg[150] ,\n \\not_strict_mode.app_rd_data_reg[134] ,\n \\not_strict_mode.app_rd_data_reg[157] ,\n \\not_strict_mode.app_rd_data_reg[141] ,\n \\not_strict_mode.app_rd_data_reg[149] ,\n \\not_strict_mode.app_rd_data_reg[133] ,\n \\not_strict_mode.app_rd_data_reg[156] ,\n \\not_strict_mode.app_rd_data_reg[140] ,\n \\not_strict_mode.app_rd_data_reg[148] ,\n \\not_strict_mode.app_rd_data_reg[132] ,\n \\not_strict_mode.app_rd_data_reg[155] ,\n \\not_strict_mode.app_rd_data_reg[139] ,\n \\not_strict_mode.app_rd_data_reg[147] ,\n \\not_strict_mode.app_rd_data_reg[131] ,\n \\not_strict_mode.app_rd_data_reg[154] ,\n \\not_strict_mode.app_rd_data_reg[138] ,\n \\not_strict_mode.app_rd_data_reg[146] ,\n \\not_strict_mode.app_rd_data_reg[130] ,\n \\not_strict_mode.app_rd_data_reg[153] ,\n \\not_strict_mode.app_rd_data_reg[137] ,\n \\not_strict_mode.app_rd_data_reg[145] ,\n \\not_strict_mode.app_rd_data_reg[129] ,\n \\not_strict_mode.app_rd_data_reg[152] ,\n \\not_strict_mode.app_rd_data_reg[136] ,\n \\not_strict_mode.app_rd_data_reg[144] ,\n \\not_strict_mode.app_rd_data_reg[128] ,\n \\not_strict_mode.app_rd_data_reg[127] ,\n \\not_strict_mode.app_rd_data_reg[111] ,\n \\not_strict_mode.app_rd_data_reg[119] ,\n \\not_strict_mode.app_rd_data_reg[103] ,\n \\not_strict_mode.app_rd_data_reg[126] ,\n \\not_strict_mode.app_rd_data_reg[110] ,\n \\not_strict_mode.app_rd_data_reg[118] ,\n \\not_strict_mode.app_rd_data_reg[102] ,\n \\not_strict_mode.app_rd_data_reg[125] ,\n \\not_strict_mode.app_rd_data_reg[109] ,\n \\not_strict_mode.app_rd_data_reg[117] ,\n \\not_strict_mode.app_rd_data_reg[101] ,\n \\not_strict_mode.app_rd_data_reg[124] ,\n \\not_strict_mode.app_rd_data_reg[108] ,\n \\not_strict_mode.app_rd_data_reg[116] ,\n \\not_strict_mode.app_rd_data_reg[100] ,\n \\not_strict_mode.app_rd_data_reg[123] ,\n \\not_strict_mode.app_rd_data_reg[107] ,\n \\not_strict_mode.app_rd_data_reg[115] ,\n \\not_strict_mode.app_rd_data_reg[99] ,\n \\not_strict_mode.app_rd_data_reg[122] ,\n \\not_strict_mode.app_rd_data_reg[106] ,\n \\not_strict_mode.app_rd_data_reg[114] ,\n \\not_strict_mode.app_rd_data_reg[98] ,\n \\not_strict_mode.app_rd_data_reg[121] ,\n \\not_strict_mode.app_rd_data_reg[105] ,\n \\not_strict_mode.app_rd_data_reg[113] ,\n \\not_strict_mode.app_rd_data_reg[97] ,\n \\not_strict_mode.app_rd_data_reg[120] ,\n \\not_strict_mode.app_rd_data_reg[104] ,\n \\not_strict_mode.app_rd_data_reg[112] ,\n \\not_strict_mode.app_rd_data_reg[96] ,\n \\not_strict_mode.app_rd_data_reg[95] ,\n \\not_strict_mode.app_rd_data_reg[79] ,\n \\not_strict_mode.app_rd_data_reg[87] ,\n \\not_strict_mode.app_rd_data_reg[71] ,\n \\not_strict_mode.app_rd_data_reg[94] ,\n \\not_strict_mode.app_rd_data_reg[78] ,\n \\not_strict_mode.app_rd_data_reg[86] ,\n \\not_strict_mode.app_rd_data_reg[70] ,\n \\not_strict_mode.app_rd_data_reg[93] ,\n \\not_strict_mode.app_rd_data_reg[77] ,\n \\not_strict_mode.app_rd_data_reg[85] ,\n \\not_strict_mode.app_rd_data_reg[69] ,\n \\not_strict_mode.app_rd_data_reg[92] ,\n \\not_strict_mode.app_rd_data_reg[76] ,\n \\not_strict_mode.app_rd_data_reg[84] ,\n \\not_strict_mode.app_rd_data_reg[68] ,\n \\not_strict_mode.app_rd_data_reg[91] ,\n \\not_strict_mode.app_rd_data_reg[75] ,\n \\not_strict_mode.app_rd_data_reg[83] ,\n \\not_strict_mode.app_rd_data_reg[67] ,\n \\not_strict_mode.app_rd_data_reg[90] ,\n \\not_strict_mode.app_rd_data_reg[74] ,\n \\not_strict_mode.app_rd_data_reg[82] ,\n \\not_strict_mode.app_rd_data_reg[66] ,\n \\not_strict_mode.app_rd_data_reg[89] ,\n \\not_strict_mode.app_rd_data_reg[73] ,\n \\not_strict_mode.app_rd_data_reg[81] ,\n \\not_strict_mode.app_rd_data_reg[65] ,\n \\not_strict_mode.app_rd_data_reg[88] ,\n \\not_strict_mode.app_rd_data_reg[72] ,\n \\not_strict_mode.app_rd_data_reg[80] ,\n \\not_strict_mode.app_rd_data_reg[64] ,\n \\not_strict_mode.app_rd_data_reg[63] ,\n \\not_strict_mode.app_rd_data_reg[47] ,\n \\not_strict_mode.app_rd_data_reg[55] ,\n \\not_strict_mode.app_rd_data_reg[39] ,\n \\not_strict_mode.app_rd_data_reg[62] ,\n \\not_strict_mode.app_rd_data_reg[46] ,\n \\not_strict_mode.app_rd_data_reg[54] ,\n \\not_strict_mode.app_rd_data_reg[38] ,\n \\not_strict_mode.app_rd_data_reg[61] ,\n \\not_strict_mode.app_rd_data_reg[45] ,\n \\not_strict_mode.app_rd_data_reg[53] ,\n \\not_strict_mode.app_rd_data_reg[37] ,\n \\not_strict_mode.app_rd_data_reg[60] ,\n \\not_strict_mode.app_rd_data_reg[44] ,\n \\not_strict_mode.app_rd_data_reg[52] ,\n \\not_strict_mode.app_rd_data_reg[36] ,\n \\not_strict_mode.app_rd_data_reg[59] ,\n \\not_strict_mode.app_rd_data_reg[43] ,\n \\not_strict_mode.app_rd_data_reg[51] ,\n \\not_strict_mode.app_rd_data_reg[35] ,\n \\not_strict_mode.app_rd_data_reg[58] ,\n \\not_strict_mode.app_rd_data_reg[42] ,\n \\not_strict_mode.app_rd_data_reg[50] ,\n \\not_strict_mode.app_rd_data_reg[34] ,\n \\not_strict_mode.app_rd_data_reg[57] ,\n \\not_strict_mode.app_rd_data_reg[41] ,\n \\not_strict_mode.app_rd_data_reg[49] ,\n \\not_strict_mode.app_rd_data_reg[33] ,\n \\not_strict_mode.app_rd_data_reg[56] ,\n \\not_strict_mode.app_rd_data_reg[40] ,\n \\not_strict_mode.app_rd_data_reg[48] ,\n \\not_strict_mode.app_rd_data_reg[32] ,\n \\not_strict_mode.app_rd_data_reg[31] ,\n \\not_strict_mode.app_rd_data_reg[15] ,\n \\not_strict_mode.app_rd_data_reg[23] ,\n \\not_strict_mode.app_rd_data_reg[7] ,\n \\not_strict_mode.app_rd_data_reg[30] ,\n \\not_strict_mode.app_rd_data_reg[14] ,\n \\not_strict_mode.app_rd_data_reg[22] ,\n \\not_strict_mode.app_rd_data_reg[6] ,\n \\not_strict_mode.app_rd_data_reg[29] ,\n \\not_strict_mode.app_rd_data_reg[13] ,\n \\not_strict_mode.app_rd_data_reg[21] ,\n \\not_strict_mode.app_rd_data_reg[5] ,\n \\not_strict_mode.app_rd_data_reg[28] ,\n \\not_strict_mode.app_rd_data_reg[12] ,\n \\not_strict_mode.app_rd_data_reg[20] ,\n \\not_strict_mode.app_rd_data_reg[4] ,\n \\not_strict_mode.app_rd_data_reg[27] ,\n \\not_strict_mode.app_rd_data_reg[11] ,\n \\not_strict_mode.app_rd_data_reg[19] ,\n \\not_strict_mode.app_rd_data_reg[3] ,\n \\not_strict_mode.app_rd_data_reg[26] ,\n \\not_strict_mode.app_rd_data_reg[10] ,\n \\not_strict_mode.app_rd_data_reg[18] ,\n \\not_strict_mode.app_rd_data_reg[2] ,\n \\not_strict_mode.app_rd_data_reg[25] ,\n \\not_strict_mode.app_rd_data_reg[9] ,\n \\not_strict_mode.app_rd_data_reg[17] ,\n \\not_strict_mode.app_rd_data_reg[1] ,\n \\not_strict_mode.app_rd_data_reg[24] ,\n \\not_strict_mode.app_rd_data_reg[8] ,\n \\not_strict_mode.app_rd_data_reg[16] ,\n \\not_strict_mode.app_rd_data_reg[0] ,\n \\read_fifo.tail_r_reg[0] ,\n \\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,\n \\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,\n \\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,\n \\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,\n \\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,\n \\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,\n \\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,\n \\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,\n \\not_strict_mode.app_rd_data_reg[255]_0 ,\n of_ctl_full_v,\n pi_phase_locked_all_r1_reg,\n \\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ,\n \\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ,\n \\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ,\n \\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ,\n \\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ,\n \\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ,\n \\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ,\n \\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ,\n wr_en,\n wr_en_5,\n wr_en_6,\n \\not_strict_mode.app_rd_data_reg[31]_0 ,\n \\not_strict_mode.app_rd_data_reg[31]_1 ,\n \\my_empty_reg[7] ,\n \\not_strict_mode.app_rd_data_reg[23]_0 ,\n \\not_strict_mode.app_rd_data_reg[23]_1 ,\n \\my_empty_reg[7]_0 ,\n \\not_strict_mode.app_rd_data_reg[15]_0 ,\n \\not_strict_mode.app_rd_data_reg[15]_1 ,\n \\my_empty_reg[7]_1 ,\n \\not_strict_mode.app_rd_data_reg[7]_0 ,\n \\not_strict_mode.app_rd_data_reg[7]_1 ,\n \\my_empty_reg[7]_2 ,\n ofs_rdy_r_reg,\n ofs_rdy_r_reg_0,\n \\po_rdval_cnt_reg[8] ,\n \\pi_rdval_cnt_reg[5] ,\n \\wr_ptr_timing_reg[2] ,\n \\wr_ptr_timing_reg[2]_0 ,\n \\wr_ptr_timing_reg[2]_1 ,\n \\po_rdval_cnt_reg[8]_0 ,\n phy_if_empty_r_reg,\n p_0_out,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,\n \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,\n \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,\n \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,\n \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,\n ddr_ck_out,\n \\my_empty_reg[7]_3 ,\n CLK,\n init_calib_complete_reg_rep__6,\n D5,\n D6,\n D2,\n D3,\n \\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ,\n \\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ,\n D7,\n D8,\n D9,\n D0,\n D1,\n \\calib_sel_reg[0] ,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n \\calib_sel_reg[0]_0 ,\n \\calib_sel_reg[0]_1 ,\n freq_refclk,\n mem_refclk,\n \\calib_sel_reg[0]_2 ,\n sync_pulse,\n \\calib_sel_reg[1] ,\n \\gen_byte_sel_div1.calib_in_common_reg_0 ,\n \\calib_sel_reg[1]_0 ,\n \\calib_sel_reg[1]_1 ,\n \\calib_sel_reg[1]_2 ,\n \\calib_sel_reg[1]_3 ,\n \\gen_byte_sel_div1.calib_in_common_reg_1 ,\n \\calib_sel_reg[1]_4 ,\n \\calib_sel_reg[1]_5 ,\n \\calib_sel_reg[1]_6 ,\n phy_ctl_wr_i2,\n pll_locked,\n phy_read_calib,\n in0,\n phy_write_calib,\n Q,\n \\data_offset_1_i2_reg[5] ,\n \\gen_byte_sel_div1.calib_in_common_reg_2 ,\n \\calib_sel_reg[0]_3 ,\n pi_en_stg2_f_reg,\n pi_stg2_f_incdec_reg,\n mem_dqs_in,\n \\gen_byte_sel_div1.calib_in_common_reg_3 ,\n COUNTERLOADVAL,\n \\gen_byte_sel_div1.calib_in_common_reg_4 ,\n ck_po_stg2_f_en_reg,\n ck_po_stg2_f_indec_reg,\n delay_done_r4_reg,\n \\write_buffer.wr_buf_out_data_reg[255] ,\n \\write_buffer.wr_buf_out_data_reg[254] ,\n \\write_buffer.wr_buf_out_data_reg[253] ,\n \\write_buffer.wr_buf_out_data_reg[252] ,\n \\write_buffer.wr_buf_out_data_reg[251] ,\n \\write_buffer.wr_buf_out_data_reg[250] ,\n \\write_buffer.wr_buf_out_data_reg[249] ,\n \\write_buffer.wr_buf_out_data_reg[248] ,\n \\gen_byte_sel_div1.calib_in_common_reg_5 ,\n mem_dq_in,\n idelay_inc,\n LD0,\n CLKB0,\n phy_if_reset,\n \\gen_byte_sel_div1.calib_in_common_reg_6 ,\n \\calib_sel_reg[0]_4 ,\n pi_en_stg2_f_reg_0,\n pi_stg2_f_incdec_reg_0,\n \\gen_byte_sel_div1.calib_in_common_reg_7 ,\n \\calib_zero_inputs_reg[0] ,\n \\gen_byte_sel_div1.calib_in_common_reg_8 ,\n ck_po_stg2_f_en_reg_0,\n ck_po_stg2_f_indec_reg_0,\n delay_done_r4_reg_0,\n \\write_buffer.wr_buf_out_data_reg[247] ,\n \\write_buffer.wr_buf_out_data_reg[246] ,\n \\write_buffer.wr_buf_out_data_reg[245] ,\n \\write_buffer.wr_buf_out_data_reg[244] ,\n \\write_buffer.wr_buf_out_data_reg[243] ,\n \\write_buffer.wr_buf_out_data_reg[242] ,\n \\write_buffer.wr_buf_out_data_reg[241] ,\n \\write_buffer.wr_buf_out_data_reg[240] ,\n \\gen_byte_sel_div1.calib_in_common_reg_9 ,\n LD0_3,\n CLKB0_7,\n \\gen_byte_sel_div1.calib_in_common_reg_10 ,\n \\calib_sel_reg[1]_7 ,\n pi_en_stg2_f_reg_1,\n pi_stg2_f_incdec_reg_1,\n \\gen_byte_sel_div1.calib_in_common_reg_11 ,\n \\calib_zero_inputs_reg[0]_0 ,\n \\gen_byte_sel_div1.calib_in_common_reg_12 ,\n ck_po_stg2_f_en_reg_1,\n ck_po_stg2_f_indec_reg_1,\n delay_done_r4_reg_1,\n \\write_buffer.wr_buf_out_data_reg[239] ,\n \\write_buffer.wr_buf_out_data_reg[238] ,\n \\write_buffer.wr_buf_out_data_reg[237] ,\n \\write_buffer.wr_buf_out_data_reg[236] ,\n \\write_buffer.wr_buf_out_data_reg[235] ,\n \\write_buffer.wr_buf_out_data_reg[234] ,\n \\write_buffer.wr_buf_out_data_reg[233] ,\n \\write_buffer.wr_buf_out_data_reg[232] ,\n \\gen_byte_sel_div1.calib_in_common_reg_13 ,\n LD0_4,\n CLKB0_8,\n \\gen_byte_sel_div1.calib_in_common_reg_14 ,\n \\calib_sel_reg[0]_5 ,\n pi_en_stg2_f_reg_2,\n pi_stg2_f_incdec_reg_2,\n \\gen_byte_sel_div1.calib_in_common_reg_15 ,\n \\calib_zero_inputs_reg[0]_1 ,\n \\gen_byte_sel_div1.calib_in_common_reg_16 ,\n ck_po_stg2_f_en_reg_2,\n ck_po_stg2_f_indec_reg_2,\n delay_done_r4_reg_2,\n \\write_buffer.wr_buf_out_data_reg[231] ,\n \\write_buffer.wr_buf_out_data_reg[230] ,\n \\write_buffer.wr_buf_out_data_reg[229] ,\n \\write_buffer.wr_buf_out_data_reg[228] ,\n \\write_buffer.wr_buf_out_data_reg[227] ,\n \\write_buffer.wr_buf_out_data_reg[226] ,\n \\write_buffer.wr_buf_out_data_reg[225] ,\n \\write_buffer.wr_buf_out_data_reg[224] ,\n \\gen_byte_sel_div1.calib_in_common_reg_17 ,\n LD0_5,\n CLKB0_9,\n RST0,\n rstdiv0_sync_r1_reg_rep__9,\n mux_cmd_wren,\n mem_out,\n \\rd_ptr_reg[3] ,\n mux_wrdata_en,\n \\rd_ptr_reg[3]_0 ,\n \\read_fifo.fifo_out_data_r_reg[6] ,\n ram_init_done_r,\n init_calib_complete_reg_rep__5,\n mc_cas_n,\n mc_address,\n init_calib_complete_reg_rep,\n \\write_buffer.wr_buf_out_data_reg[287] ,\n prbs_rdlvl_start_reg,\n out,\n sys_rst,\n \\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ,\n mmcm_locked,\n \\byte_r_reg[0]_0 ,\n \\byte_r_reg[1] ,\n tail_r,\n \\rd_mux_sel_r_reg[1] ,\n \\read_fifo.fifo_out_data_r_reg[6]_0 ,\n DOC,\n DOB,\n DOA,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ,\n A,\n mux_wrdata,\n mux_wrdata_mask,\n E,\n \\fine_delay_mod_reg[23] ,\n \\gen_byte_sel_div1.calib_in_common_reg_18 ,\n \\calib_sel_reg[0]_6 ,\n \\gen_byte_sel_div1.calib_in_common_reg_19 ,\n \\calib_sel_reg[1]_8 ,\n \\gen_byte_sel_div1.calib_in_common_reg_20 ,\n \\calib_sel_reg[0]_7 ,\n \\calib_sel_reg[3] ,\n \\po_stg2_wrcal_cnt_reg[1] ,\n D_po_coarse_enable110_out,\n D_po_counter_read_en122_out,\n D_po_fine_enable107_out,\n D_po_fine_inc113_out,\n D_po_sel_fine_oclk_delay125_out,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ,\n D4,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ,\n phy_dout,\n init_calib_complete_reg_rep__6_0);\n output \\rd_ptr_timing_reg[2] ;\n output \\rd_ptr_timing_reg[2]_0 ;\n output \\rd_ptr_timing_reg[2]_1 ;\n output \\rd_ptr_timing_reg[2]_2 ;\n output \\rd_ptr_timing_reg[2]_3 ;\n output \\rd_ptr_timing_reg[2]_4 ;\n output \\rd_ptr_timing_reg[2]_5 ;\n output \\rd_ptr_timing_reg[2]_6 ;\n output \\rd_ptr_timing_reg[2]_7 ;\n output \\rd_ptr_timing_reg[2]_8 ;\n output \\rd_ptr_timing_reg[2]_9 ;\n output \\rd_ptr_timing_reg[2]_10 ;\n output [3:0]\\pi_dqs_found_lanes_r1_reg[3] ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n output [3:0]mem_dqs_out;\n output [3:0]mem_dqs_ts;\n output [59:0]mem_dq_out;\n output [35:0]mem_dq_ts;\n output idelay_ld_rst;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n output idelay_ld_rst_0;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;\n output idelay_ld_rst_1;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;\n output idelay_ld_rst_2;\n output \\calib_seq_reg[0] ;\n output \\not_strict_mode.app_rd_data_reg[252] ;\n output \\not_strict_mode.app_rd_data_reg[244] ;\n output \\not_strict_mode.app_rd_data_reg[236] ;\n output \\not_strict_mode.app_rd_data_reg[228] ;\n output \\my_empty_reg[1] ;\n output \\my_empty_reg[1]_0 ;\n output phy_mc_ctl_full;\n output \\my_empty_reg[1]_1 ;\n output \\my_empty_reg[1]_2 ;\n output \\my_empty_reg[1]_3 ;\n output \\my_empty_reg[1]_4 ;\n output \\my_empty_reg[1]_5 ;\n output rd_buf_we;\n output \\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n output \\my_empty_reg[1]_6 ;\n output phy_rddata_en;\n output mux_rd_valid_r_reg;\n output rst_sync_r1_reg;\n output \\byte_r_reg[0] ;\n output [5:0]\\po_counter_read_val_r_reg[5] ;\n output [63:0]\\data_bytes_r_reg[63] ;\n output \\not_strict_mode.app_rd_data_reg[255] ;\n output \\not_strict_mode.app_rd_data_reg[239] ;\n output \\not_strict_mode.app_rd_data_reg[247] ;\n output \\not_strict_mode.app_rd_data_reg[231] ;\n output \\not_strict_mode.app_rd_data_reg[254] ;\n output \\not_strict_mode.app_rd_data_reg[238] ;\n output \\not_strict_mode.app_rd_data_reg[246] ;\n output \\not_strict_mode.app_rd_data_reg[230] ;\n output \\not_strict_mode.app_rd_data_reg[253] ;\n output \\not_strict_mode.app_rd_data_reg[237] ;\n output \\not_strict_mode.app_rd_data_reg[245] ;\n output \\not_strict_mode.app_rd_data_reg[229] ;\n output \\not_strict_mode.app_rd_data_reg[252]_0 ;\n output \\not_strict_mode.app_rd_data_reg[236]_0 ;\n output \\not_strict_mode.app_rd_data_reg[244]_0 ;\n output \\not_strict_mode.app_rd_data_reg[228]_0 ;\n output \\not_strict_mode.app_rd_data_reg[251] ;\n output \\not_strict_mode.app_rd_data_reg[235] ;\n output \\not_strict_mode.app_rd_data_reg[243] ;\n output \\not_strict_mode.app_rd_data_reg[227] ;\n output \\not_strict_mode.app_rd_data_reg[250] ;\n output \\not_strict_mode.app_rd_data_reg[234] ;\n output \\not_strict_mode.app_rd_data_reg[242] ;\n output \\not_strict_mode.app_rd_data_reg[226] ;\n output \\not_strict_mode.app_rd_data_reg[249] ;\n output \\not_strict_mode.app_rd_data_reg[233] ;\n output \\not_strict_mode.app_rd_data_reg[241] ;\n output \\not_strict_mode.app_rd_data_reg[225] ;\n output \\not_strict_mode.app_rd_data_reg[248] ;\n output \\not_strict_mode.app_rd_data_reg[232] ;\n output \\not_strict_mode.app_rd_data_reg[240] ;\n output \\not_strict_mode.app_rd_data_reg[224] ;\n output \\not_strict_mode.app_rd_data_reg[223] ;\n output \\not_strict_mode.app_rd_data_reg[207] ;\n output \\not_strict_mode.app_rd_data_reg[215] ;\n output \\not_strict_mode.app_rd_data_reg[199] ;\n output \\not_strict_mode.app_rd_data_reg[222] ;\n output \\not_strict_mode.app_rd_data_reg[206] ;\n output \\not_strict_mode.app_rd_data_reg[214] ;\n output \\not_strict_mode.app_rd_data_reg[198] ;\n output \\not_strict_mode.app_rd_data_reg[221] ;\n output \\not_strict_mode.app_rd_data_reg[205] ;\n output \\not_strict_mode.app_rd_data_reg[213] ;\n output \\not_strict_mode.app_rd_data_reg[197] ;\n output \\not_strict_mode.app_rd_data_reg[220] ;\n output \\not_strict_mode.app_rd_data_reg[204] ;\n output \\not_strict_mode.app_rd_data_reg[212] ;\n output \\not_strict_mode.app_rd_data_reg[196] ;\n output \\not_strict_mode.app_rd_data_reg[219] ;\n output \\not_strict_mode.app_rd_data_reg[203] ;\n output \\not_strict_mode.app_rd_data_reg[211] ;\n output \\not_strict_mode.app_rd_data_reg[195] ;\n output \\not_strict_mode.app_rd_data_reg[218] ;\n output \\not_strict_mode.app_rd_data_reg[202] ;\n output \\not_strict_mode.app_rd_data_reg[210] ;\n output \\not_strict_mode.app_rd_data_reg[194] ;\n output \\not_strict_mode.app_rd_data_reg[217] ;\n output \\not_strict_mode.app_rd_data_reg[201] ;\n output \\not_strict_mode.app_rd_data_reg[209] ;\n output \\not_strict_mode.app_rd_data_reg[193] ;\n output \\not_strict_mode.app_rd_data_reg[216] ;\n output \\not_strict_mode.app_rd_data_reg[200] ;\n output \\not_strict_mode.app_rd_data_reg[208] ;\n output \\not_strict_mode.app_rd_data_reg[192] ;\n output \\not_strict_mode.app_rd_data_reg[191] ;\n output \\not_strict_mode.app_rd_data_reg[175] ;\n output \\not_strict_mode.app_rd_data_reg[183] ;\n output \\not_strict_mode.app_rd_data_reg[167] ;\n output \\not_strict_mode.app_rd_data_reg[190] ;\n output \\not_strict_mode.app_rd_data_reg[174] ;\n output \\not_strict_mode.app_rd_data_reg[182] ;\n output \\not_strict_mode.app_rd_data_reg[166] ;\n output \\not_strict_mode.app_rd_data_reg[189] ;\n output \\not_strict_mode.app_rd_data_reg[173] ;\n output \\not_strict_mode.app_rd_data_reg[181] ;\n output \\not_strict_mode.app_rd_data_reg[165] ;\n output \\not_strict_mode.app_rd_data_reg[188] ;\n output \\not_strict_mode.app_rd_data_reg[172] ;\n output \\not_strict_mode.app_rd_data_reg[180] ;\n output \\not_strict_mode.app_rd_data_reg[164] ;\n output \\not_strict_mode.app_rd_data_reg[187] ;\n output \\not_strict_mode.app_rd_data_reg[171] ;\n output \\not_strict_mode.app_rd_data_reg[179] ;\n output \\not_strict_mode.app_rd_data_reg[163] ;\n output \\not_strict_mode.app_rd_data_reg[186] ;\n output \\not_strict_mode.app_rd_data_reg[170] ;\n output \\not_strict_mode.app_rd_data_reg[178] ;\n output \\not_strict_mode.app_rd_data_reg[162] ;\n output \\not_strict_mode.app_rd_data_reg[185] ;\n output \\not_strict_mode.app_rd_data_reg[169] ;\n output \\not_strict_mode.app_rd_data_reg[177] ;\n output \\not_strict_mode.app_rd_data_reg[161] ;\n output \\not_strict_mode.app_rd_data_reg[184] ;\n output \\not_strict_mode.app_rd_data_reg[168] ;\n output \\not_strict_mode.app_rd_data_reg[176] ;\n output \\not_strict_mode.app_rd_data_reg[160] ;\n output \\not_strict_mode.app_rd_data_reg[159] ;\n output \\not_strict_mode.app_rd_data_reg[143] ;\n output \\not_strict_mode.app_rd_data_reg[151] ;\n output \\not_strict_mode.app_rd_data_reg[135] ;\n output \\not_strict_mode.app_rd_data_reg[158] ;\n output \\not_strict_mode.app_rd_data_reg[142] ;\n output \\not_strict_mode.app_rd_data_reg[150] ;\n output \\not_strict_mode.app_rd_data_reg[134] ;\n output \\not_strict_mode.app_rd_data_reg[157] ;\n output \\not_strict_mode.app_rd_data_reg[141] ;\n output \\not_strict_mode.app_rd_data_reg[149] ;\n output \\not_strict_mode.app_rd_data_reg[133] ;\n output \\not_strict_mode.app_rd_data_reg[156] ;\n output \\not_strict_mode.app_rd_data_reg[140] ;\n output \\not_strict_mode.app_rd_data_reg[148] ;\n output \\not_strict_mode.app_rd_data_reg[132] ;\n output \\not_strict_mode.app_rd_data_reg[155] ;\n output \\not_strict_mode.app_rd_data_reg[139] ;\n output \\not_strict_mode.app_rd_data_reg[147] ;\n output \\not_strict_mode.app_rd_data_reg[131] ;\n output \\not_strict_mode.app_rd_data_reg[154] ;\n output \\not_strict_mode.app_rd_data_reg[138] ;\n output \\not_strict_mode.app_rd_data_reg[146] ;\n output \\not_strict_mode.app_rd_data_reg[130] ;\n output \\not_strict_mode.app_rd_data_reg[153] ;\n output \\not_strict_mode.app_rd_data_reg[137] ;\n output \\not_strict_mode.app_rd_data_reg[145] ;\n output \\not_strict_mode.app_rd_data_reg[129] ;\n output \\not_strict_mode.app_rd_data_reg[152] ;\n output \\not_strict_mode.app_rd_data_reg[136] ;\n output \\not_strict_mode.app_rd_data_reg[144] ;\n output \\not_strict_mode.app_rd_data_reg[128] ;\n output \\not_strict_mode.app_rd_data_reg[127] ;\n output \\not_strict_mode.app_rd_data_reg[111] ;\n output \\not_strict_mode.app_rd_data_reg[119] ;\n output \\not_strict_mode.app_rd_data_reg[103] ;\n output \\not_strict_mode.app_rd_data_reg[126] ;\n output \\not_strict_mode.app_rd_data_reg[110] ;\n output \\not_strict_mode.app_rd_data_reg[118] ;\n output \\not_strict_mode.app_rd_data_reg[102] ;\n output \\not_strict_mode.app_rd_data_reg[125] ;\n output \\not_strict_mode.app_rd_data_reg[109] ;\n output \\not_strict_mode.app_rd_data_reg[117] ;\n output \\not_strict_mode.app_rd_data_reg[101] ;\n output \\not_strict_mode.app_rd_data_reg[124] ;\n output \\not_strict_mode.app_rd_data_reg[108] ;\n output \\not_strict_mode.app_rd_data_reg[116] ;\n output \\not_strict_mode.app_rd_data_reg[100] ;\n output \\not_strict_mode.app_rd_data_reg[123] ;\n output \\not_strict_mode.app_rd_data_reg[107] ;\n output \\not_strict_mode.app_rd_data_reg[115] ;\n output \\not_strict_mode.app_rd_data_reg[99] ;\n output \\not_strict_mode.app_rd_data_reg[122] ;\n output \\not_strict_mode.app_rd_data_reg[106] ;\n output \\not_strict_mode.app_rd_data_reg[114] ;\n output \\not_strict_mode.app_rd_data_reg[98] ;\n output \\not_strict_mode.app_rd_data_reg[121] ;\n output \\not_strict_mode.app_rd_data_reg[105] ;\n output \\not_strict_mode.app_rd_data_reg[113] ;\n output \\not_strict_mode.app_rd_data_reg[97] ;\n output \\not_strict_mode.app_rd_data_reg[120] ;\n output \\not_strict_mode.app_rd_data_reg[104] ;\n output \\not_strict_mode.app_rd_data_reg[112] ;\n output \\not_strict_mode.app_rd_data_reg[96] ;\n output \\not_strict_mode.app_rd_data_reg[95] ;\n output \\not_strict_mode.app_rd_data_reg[79] ;\n output \\not_strict_mode.app_rd_data_reg[87] ;\n output \\not_strict_mode.app_rd_data_reg[71] ;\n output \\not_strict_mode.app_rd_data_reg[94] ;\n output \\not_strict_mode.app_rd_data_reg[78] ;\n output \\not_strict_mode.app_rd_data_reg[86] ;\n output \\not_strict_mode.app_rd_data_reg[70] ;\n output \\not_strict_mode.app_rd_data_reg[93] ;\n output \\not_strict_mode.app_rd_data_reg[77] ;\n output \\not_strict_mode.app_rd_data_reg[85] ;\n output \\not_strict_mode.app_rd_data_reg[69] ;\n output \\not_strict_mode.app_rd_data_reg[92] ;\n output \\not_strict_mode.app_rd_data_reg[76] ;\n output \\not_strict_mode.app_rd_data_reg[84] ;\n output \\not_strict_mode.app_rd_data_reg[68] ;\n output \\not_strict_mode.app_rd_data_reg[91] ;\n output \\not_strict_mode.app_rd_data_reg[75] ;\n output \\not_strict_mode.app_rd_data_reg[83] ;\n output \\not_strict_mode.app_rd_data_reg[67] ;\n output \\not_strict_mode.app_rd_data_reg[90] ;\n output \\not_strict_mode.app_rd_data_reg[74] ;\n output \\not_strict_mode.app_rd_data_reg[82] ;\n output \\not_strict_mode.app_rd_data_reg[66] ;\n output \\not_strict_mode.app_rd_data_reg[89] ;\n output \\not_strict_mode.app_rd_data_reg[73] ;\n output \\not_strict_mode.app_rd_data_reg[81] ;\n output \\not_strict_mode.app_rd_data_reg[65] ;\n output \\not_strict_mode.app_rd_data_reg[88] ;\n output \\not_strict_mode.app_rd_data_reg[72] ;\n output \\not_strict_mode.app_rd_data_reg[80] ;\n output \\not_strict_mode.app_rd_data_reg[64] ;\n output \\not_strict_mode.app_rd_data_reg[63] ;\n output \\not_strict_mode.app_rd_data_reg[47] ;\n output \\not_strict_mode.app_rd_data_reg[55] ;\n output \\not_strict_mode.app_rd_data_reg[39] ;\n output \\not_strict_mode.app_rd_data_reg[62] ;\n output \\not_strict_mode.app_rd_data_reg[46] ;\n output \\not_strict_mode.app_rd_data_reg[54] ;\n output \\not_strict_mode.app_rd_data_reg[38] ;\n output \\not_strict_mode.app_rd_data_reg[61] ;\n output \\not_strict_mode.app_rd_data_reg[45] ;\n output \\not_strict_mode.app_rd_data_reg[53] ;\n output \\not_strict_mode.app_rd_data_reg[37] ;\n output \\not_strict_mode.app_rd_data_reg[60] ;\n output \\not_strict_mode.app_rd_data_reg[44] ;\n output \\not_strict_mode.app_rd_data_reg[52] ;\n output \\not_strict_mode.app_rd_data_reg[36] ;\n output \\not_strict_mode.app_rd_data_reg[59] ;\n output \\not_strict_mode.app_rd_data_reg[43] ;\n output \\not_strict_mode.app_rd_data_reg[51] ;\n output \\not_strict_mode.app_rd_data_reg[35] ;\n output \\not_strict_mode.app_rd_data_reg[58] ;\n output \\not_strict_mode.app_rd_data_reg[42] ;\n output \\not_strict_mode.app_rd_data_reg[50] ;\n output \\not_strict_mode.app_rd_data_reg[34] ;\n output \\not_strict_mode.app_rd_data_reg[57] ;\n output \\not_strict_mode.app_rd_data_reg[41] ;\n output \\not_strict_mode.app_rd_data_reg[49] ;\n output \\not_strict_mode.app_rd_data_reg[33] ;\n output \\not_strict_mode.app_rd_data_reg[56] ;\n output \\not_strict_mode.app_rd_data_reg[40] ;\n output \\not_strict_mode.app_rd_data_reg[48] ;\n output \\not_strict_mode.app_rd_data_reg[32] ;\n output \\not_strict_mode.app_rd_data_reg[31] ;\n output \\not_strict_mode.app_rd_data_reg[15] ;\n output \\not_strict_mode.app_rd_data_reg[23] ;\n output \\not_strict_mode.app_rd_data_reg[7] ;\n output \\not_strict_mode.app_rd_data_reg[30] ;\n output \\not_strict_mode.app_rd_data_reg[14] ;\n output \\not_strict_mode.app_rd_data_reg[22] ;\n output \\not_strict_mode.app_rd_data_reg[6] ;\n output \\not_strict_mode.app_rd_data_reg[29] ;\n output \\not_strict_mode.app_rd_data_reg[13] ;\n output \\not_strict_mode.app_rd_data_reg[21] ;\n output \\not_strict_mode.app_rd_data_reg[5] ;\n output \\not_strict_mode.app_rd_data_reg[28] ;\n output \\not_strict_mode.app_rd_data_reg[12] ;\n output \\not_strict_mode.app_rd_data_reg[20] ;\n output \\not_strict_mode.app_rd_data_reg[4] ;\n output \\not_strict_mode.app_rd_data_reg[27] ;\n output \\not_strict_mode.app_rd_data_reg[11] ;\n output \\not_strict_mode.app_rd_data_reg[19] ;\n output \\not_strict_mode.app_rd_data_reg[3] ;\n output \\not_strict_mode.app_rd_data_reg[26] ;\n output \\not_strict_mode.app_rd_data_reg[10] ;\n output \\not_strict_mode.app_rd_data_reg[18] ;\n output \\not_strict_mode.app_rd_data_reg[2] ;\n output \\not_strict_mode.app_rd_data_reg[25] ;\n output \\not_strict_mode.app_rd_data_reg[9] ;\n output \\not_strict_mode.app_rd_data_reg[17] ;\n output \\not_strict_mode.app_rd_data_reg[1] ;\n output \\not_strict_mode.app_rd_data_reg[24] ;\n output \\not_strict_mode.app_rd_data_reg[8] ;\n output \\not_strict_mode.app_rd_data_reg[16] ;\n output \\not_strict_mode.app_rd_data_reg[0] ;\n output \\read_fifo.tail_r_reg[0] ;\n output \\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n output \\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n output \\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n output \\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n output \\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n output \\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n output \\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n output \\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n output [255:0]\\not_strict_mode.app_rd_data_reg[255]_0 ;\n output [0:0]of_ctl_full_v;\n output pi_phase_locked_all_r1_reg;\n output \\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ;\n output \\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ;\n output \\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ;\n output \\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ;\n output \\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ;\n output \\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ;\n output \\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ;\n output \\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ;\n output wr_en;\n output wr_en_5;\n output wr_en_6;\n output [0:0]\\not_strict_mode.app_rd_data_reg[31]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[31]_1 ;\n output [63:0]\\my_empty_reg[7] ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[23]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[23]_1 ;\n output [63:0]\\my_empty_reg[7]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[15]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[15]_1 ;\n output [63:0]\\my_empty_reg[7]_1 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[7]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[7]_1 ;\n output [63:0]\\my_empty_reg[7]_2 ;\n output ofs_rdy_r_reg;\n output ofs_rdy_r_reg_0;\n output [4:0]\\po_rdval_cnt_reg[8] ;\n output [5:0]\\pi_rdval_cnt_reg[5] ;\n output [3:0]\\wr_ptr_timing_reg[2] ;\n output [3:0]\\wr_ptr_timing_reg[2]_0 ;\n output [3:0]\\wr_ptr_timing_reg[2]_1 ;\n output [4:0]\\po_rdval_cnt_reg[8]_0 ;\n output phy_if_empty_r_reg;\n output p_0_out;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n output \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n output \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n output \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n output \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n output [1:0]ddr_ck_out;\n output [31:0]\\my_empty_reg[7]_3 ;\n input CLK;\n input [3:0]init_calib_complete_reg_rep__6;\n input [3:0]D5;\n input [3:0]D6;\n input [2:0]D2;\n input [2:0]D3;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ;\n input [7:0]\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ;\n input [7:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ;\n input [3:0]D7;\n input [3:0]D8;\n input [3:0]D9;\n input [2:0]D0;\n input [2:0]D1;\n input \\calib_sel_reg[0] ;\n input \\gen_byte_sel_div1.calib_in_common_reg ;\n input \\calib_sel_reg[0]_0 ;\n input \\calib_sel_reg[0]_1 ;\n input freq_refclk;\n input mem_refclk;\n input \\calib_sel_reg[0]_2 ;\n input sync_pulse;\n input \\calib_sel_reg[1] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n input \\calib_sel_reg[1]_0 ;\n input \\calib_sel_reg[1]_1 ;\n input \\calib_sel_reg[1]_2 ;\n input \\calib_sel_reg[1]_3 ;\n input \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n input \\calib_sel_reg[1]_4 ;\n input \\calib_sel_reg[1]_5 ;\n input \\calib_sel_reg[1]_6 ;\n input phy_ctl_wr_i2;\n input pll_locked;\n input phy_read_calib;\n input in0;\n input phy_write_calib;\n input [10:0]Q;\n input [5:0]\\data_offset_1_i2_reg[5] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n input \\calib_sel_reg[0]_3 ;\n input pi_en_stg2_f_reg;\n input pi_stg2_f_incdec_reg;\n input [3:0]mem_dqs_in;\n input \\gen_byte_sel_div1.calib_in_common_reg_3 ;\n input [5:0]COUNTERLOADVAL;\n input \\gen_byte_sel_div1.calib_in_common_reg_4 ;\n input ck_po_stg2_f_en_reg;\n input ck_po_stg2_f_indec_reg;\n input delay_done_r4_reg;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[255] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[254] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[253] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[252] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[251] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[250] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[249] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[248] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_5 ;\n input [31:0]mem_dq_in;\n input idelay_inc;\n input LD0;\n input CLKB0;\n input phy_if_reset;\n input \\gen_byte_sel_div1.calib_in_common_reg_6 ;\n input \\calib_sel_reg[0]_4 ;\n input pi_en_stg2_f_reg_0;\n input pi_stg2_f_incdec_reg_0;\n input \\gen_byte_sel_div1.calib_in_common_reg_7 ;\n input [5:0]\\calib_zero_inputs_reg[0] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_8 ;\n input ck_po_stg2_f_en_reg_0;\n input ck_po_stg2_f_indec_reg_0;\n input delay_done_r4_reg_0;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[247] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[246] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[245] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[244] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[243] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[242] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[241] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[240] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_9 ;\n input LD0_3;\n input CLKB0_7;\n input \\gen_byte_sel_div1.calib_in_common_reg_10 ;\n input \\calib_sel_reg[1]_7 ;\n input pi_en_stg2_f_reg_1;\n input pi_stg2_f_incdec_reg_1;\n input \\gen_byte_sel_div1.calib_in_common_reg_11 ;\n input [5:0]\\calib_zero_inputs_reg[0]_0 ;\n input \\gen_byte_sel_div1.calib_in_common_reg_12 ;\n input ck_po_stg2_f_en_reg_1;\n input ck_po_stg2_f_indec_reg_1;\n input delay_done_r4_reg_1;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[239] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[238] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[237] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[236] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[235] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[234] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[233] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[232] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_13 ;\n input LD0_4;\n input CLKB0_8;\n input \\gen_byte_sel_div1.calib_in_common_reg_14 ;\n input \\calib_sel_reg[0]_5 ;\n input pi_en_stg2_f_reg_2;\n input pi_stg2_f_incdec_reg_2;\n input \\gen_byte_sel_div1.calib_in_common_reg_15 ;\n input [5:0]\\calib_zero_inputs_reg[0]_1 ;\n input \\gen_byte_sel_div1.calib_in_common_reg_16 ;\n input ck_po_stg2_f_en_reg_2;\n input ck_po_stg2_f_indec_reg_2;\n input delay_done_r4_reg_2;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[231] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[230] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[229] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[228] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[227] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[226] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[225] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[224] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_17 ;\n input LD0_5;\n input CLKB0_9;\n input RST0;\n input rstdiv0_sync_r1_reg_rep__9;\n input mux_cmd_wren;\n input [11:0]mem_out;\n input [33:0]\\rd_ptr_reg[3] ;\n input mux_wrdata_en;\n input [17:0]\\rd_ptr_reg[3]_0 ;\n input [0:0]\\read_fifo.fifo_out_data_r_reg[6] ;\n input ram_init_done_r;\n input init_calib_complete_reg_rep__5;\n input [0:0]mc_cas_n;\n input [1:0]mc_address;\n input init_calib_complete_reg_rep;\n input [31:0]\\write_buffer.wr_buf_out_data_reg[287] ;\n input prbs_rdlvl_start_reg;\n input out;\n input sys_rst;\n input [0:0]\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ;\n input mmcm_locked;\n input \\byte_r_reg[0]_0 ;\n input \\byte_r_reg[1] ;\n input [0:0]tail_r;\n input [1:0]\\rd_mux_sel_r_reg[1] ;\n input \\read_fifo.fifo_out_data_r_reg[6]_0 ;\n input [1:0]DOC;\n input [1:0]DOB;\n input [1:0]DOA;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ;\n input [1:0]A;\n input [255:0]mux_wrdata;\n input [31:0]mux_wrdata_mask;\n input [0:0]E;\n input [7:0]\\fine_delay_mod_reg[23] ;\n input [0:0]\\gen_byte_sel_div1.calib_in_common_reg_18 ;\n input [7:0]\\calib_sel_reg[0]_6 ;\n input [0:0]\\gen_byte_sel_div1.calib_in_common_reg_19 ;\n input [7:0]\\calib_sel_reg[1]_8 ;\n input [0:0]\\gen_byte_sel_div1.calib_in_common_reg_20 ;\n input [7:0]\\calib_sel_reg[0]_7 ;\n input [2:0]\\calib_sel_reg[3] ;\n input [1:0]\\po_stg2_wrcal_cnt_reg[1] ;\n input D_po_coarse_enable110_out;\n input D_po_counter_read_en122_out;\n input D_po_fine_enable107_out;\n input D_po_fine_inc113_out;\n input D_po_sel_fine_oclk_delay125_out;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ;\n input [3:0]D4;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ;\n input [35:0]phy_dout;\n input init_calib_complete_reg_rep__6_0;\n\n wire [1:0]A;\n wire CLK;\n wire CLKB0;\n wire CLKB0_7;\n wire CLKB0_8;\n wire CLKB0_9;\n wire [5:0]COUNTERLOADVAL;\n wire [2:0]D0;\n wire [2:0]D1;\n wire [2:0]D2;\n wire [2:0]D3;\n wire [3:0]D4;\n wire [3:0]D5;\n wire [3:0]D6;\n wire [3:0]D7;\n wire [3:0]D8;\n wire [3:0]D9;\n wire [1:0]DOA;\n wire [1:0]DOB;\n wire [1:0]DOC;\n wire D_po_coarse_enable110_out;\n wire D_po_counter_read_en122_out;\n wire D_po_fine_enable107_out;\n wire D_po_fine_inc113_out;\n wire D_po_sel_fine_oclk_delay125_out;\n wire [0:0]E;\n wire LD0;\n wire LD0_3;\n wire LD0_4;\n wire LD0_5;\n wire [10:0]Q;\n wire RST0;\n wire [0:0]_phy_ctl_full_p__0;\n wire \\byte_r_reg[0] ;\n wire \\byte_r_reg[0]_0 ;\n wire \\byte_r_reg[1] ;\n wire \\calib_sel_reg[0] ;\n wire \\calib_sel_reg[0]_0 ;\n wire \\calib_sel_reg[0]_1 ;\n wire \\calib_sel_reg[0]_2 ;\n wire \\calib_sel_reg[0]_3 ;\n wire \\calib_sel_reg[0]_4 ;\n wire \\calib_sel_reg[0]_5 ;\n wire [7:0]\\calib_sel_reg[0]_6 ;\n wire [7:0]\\calib_sel_reg[0]_7 ;\n wire \\calib_sel_reg[1] ;\n wire \\calib_sel_reg[1]_0 ;\n wire \\calib_sel_reg[1]_1 ;\n wire \\calib_sel_reg[1]_2 ;\n wire \\calib_sel_reg[1]_3 ;\n wire \\calib_sel_reg[1]_4 ;\n wire \\calib_sel_reg[1]_5 ;\n wire \\calib_sel_reg[1]_6 ;\n wire \\calib_sel_reg[1]_7 ;\n wire [7:0]\\calib_sel_reg[1]_8 ;\n wire [2:0]\\calib_sel_reg[3] ;\n wire \\calib_seq_reg[0] ;\n wire [5:0]\\calib_zero_inputs_reg[0] ;\n wire [5:0]\\calib_zero_inputs_reg[0]_0 ;\n wire [5:0]\\calib_zero_inputs_reg[0]_1 ;\n wire ck_po_stg2_f_en_reg;\n wire ck_po_stg2_f_en_reg_0;\n wire ck_po_stg2_f_en_reg_1;\n wire ck_po_stg2_f_en_reg_2;\n wire ck_po_stg2_f_indec_reg;\n wire ck_po_stg2_f_indec_reg_0;\n wire ck_po_stg2_f_indec_reg_1;\n wire ck_po_stg2_f_indec_reg_2;\n wire [63:0]\\data_bytes_r_reg[63] ;\n wire [5:0]\\data_offset_1_i2_reg[5] ;\n wire [1:0]ddr_ck_out;\n wire \\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_105 ;\n wire \\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_93 ;\n wire \\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_95 ;\n wire delay_done_r4_reg;\n wire delay_done_r4_reg_0;\n wire delay_done_r4_reg_1;\n wire delay_done_r4_reg_2;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;\n wire [7:0]\\fine_delay_mod_reg[23] ;\n wire freq_refclk;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_10 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_11 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_12 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_13 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_14 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_15 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_16 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_17 ;\n wire [0:0]\\gen_byte_sel_div1.calib_in_common_reg_18 ;\n wire [0:0]\\gen_byte_sel_div1.calib_in_common_reg_19 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n wire [0:0]\\gen_byte_sel_div1.calib_in_common_reg_20 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_3 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_4 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_5 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_6 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_7 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_8 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_9 ;\n wire \\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n wire \\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n wire \\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n wire \\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;\n wire \\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n wire \\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n wire \\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n wire \\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n wire [7:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ;\n wire [7:0]\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ;\n wire idelay_inc;\n wire idelay_ld_rst;\n wire idelay_ld_rst_0;\n wire idelay_ld_rst_1;\n wire idelay_ld_rst_2;\n wire in0;\n wire init_calib_complete_reg_rep;\n wire init_calib_complete_reg_rep__5;\n wire [3:0]init_calib_complete_reg_rep__6;\n wire init_calib_complete_reg_rep__6_0;\n wire \\mcGo_r_reg[13]_srl14___u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12_n_0 ;\n wire \\mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13_n_0 ;\n wire mcGo_r_reg_gate_n_0;\n wire mcGo_r_reg_r_0_n_0;\n wire mcGo_r_reg_r_10_n_0;\n wire mcGo_r_reg_r_11_n_0;\n wire mcGo_r_reg_r_12_n_0;\n wire mcGo_r_reg_r_13_n_0;\n wire mcGo_r_reg_r_1_n_0;\n wire mcGo_r_reg_r_2_n_0;\n wire mcGo_r_reg_r_3_n_0;\n wire mcGo_r_reg_r_4_n_0;\n wire mcGo_r_reg_r_5_n_0;\n wire mcGo_r_reg_r_6_n_0;\n wire mcGo_r_reg_r_7_n_0;\n wire mcGo_r_reg_r_8_n_0;\n wire mcGo_r_reg_r_9_n_0;\n wire mcGo_r_reg_r_n_0;\n wire [1:1]mcGo_w__0;\n wire [1:0]mc_address;\n wire [0:0]mc_cas_n;\n wire [31:0]mem_dq_in;\n wire [59:0]mem_dq_out;\n wire [35:0]mem_dq_ts;\n wire [3:0]mem_dqs_in;\n wire [3:0]mem_dqs_out;\n wire [3:0]mem_dqs_ts;\n wire [11:0]mem_out;\n wire mem_refclk;\n wire mmcm_locked;\n wire mux_cmd_wren;\n wire mux_rd_valid_r_reg;\n wire [255:0]mux_wrdata;\n wire mux_wrdata_en;\n wire [31:0]mux_wrdata_mask;\n wire \\my_empty_reg[1] ;\n wire \\my_empty_reg[1]_0 ;\n wire \\my_empty_reg[1]_1 ;\n wire \\my_empty_reg[1]_2 ;\n wire \\my_empty_reg[1]_3 ;\n wire \\my_empty_reg[1]_4 ;\n wire \\my_empty_reg[1]_5 ;\n wire \\my_empty_reg[1]_6 ;\n wire [63:0]\\my_empty_reg[7] ;\n wire [63:0]\\my_empty_reg[7]_0 ;\n wire [63:0]\\my_empty_reg[7]_1 ;\n wire [63:0]\\my_empty_reg[7]_2 ;\n wire [31:0]\\my_empty_reg[7]_3 ;\n wire \\not_strict_mode.app_rd_data_reg[0] ;\n wire \\not_strict_mode.app_rd_data_reg[100] ;\n wire \\not_strict_mode.app_rd_data_reg[101] ;\n wire \\not_strict_mode.app_rd_data_reg[102] ;\n wire \\not_strict_mode.app_rd_data_reg[103] ;\n wire \\not_strict_mode.app_rd_data_reg[104] ;\n wire \\not_strict_mode.app_rd_data_reg[105] ;\n wire \\not_strict_mode.app_rd_data_reg[106] ;\n wire \\not_strict_mode.app_rd_data_reg[107] ;\n wire \\not_strict_mode.app_rd_data_reg[108] ;\n wire \\not_strict_mode.app_rd_data_reg[109] ;\n wire \\not_strict_mode.app_rd_data_reg[10] ;\n wire \\not_strict_mode.app_rd_data_reg[110] ;\n wire \\not_strict_mode.app_rd_data_reg[111] ;\n wire \\not_strict_mode.app_rd_data_reg[112] ;\n wire \\not_strict_mode.app_rd_data_reg[113] ;\n wire \\not_strict_mode.app_rd_data_reg[114] ;\n wire \\not_strict_mode.app_rd_data_reg[115] ;\n wire \\not_strict_mode.app_rd_data_reg[116] ;\n wire \\not_strict_mode.app_rd_data_reg[117] ;\n wire \\not_strict_mode.app_rd_data_reg[118] ;\n wire \\not_strict_mode.app_rd_data_reg[119] ;\n wire \\not_strict_mode.app_rd_data_reg[11] ;\n wire \\not_strict_mode.app_rd_data_reg[120] ;\n wire \\not_strict_mode.app_rd_data_reg[121] ;\n wire \\not_strict_mode.app_rd_data_reg[122] ;\n wire \\not_strict_mode.app_rd_data_reg[123] ;\n wire \\not_strict_mode.app_rd_data_reg[124] ;\n wire \\not_strict_mode.app_rd_data_reg[125] ;\n wire \\not_strict_mode.app_rd_data_reg[126] ;\n wire \\not_strict_mode.app_rd_data_reg[127] ;\n wire \\not_strict_mode.app_rd_data_reg[128] ;\n wire \\not_strict_mode.app_rd_data_reg[129] ;\n wire \\not_strict_mode.app_rd_data_reg[12] ;\n wire \\not_strict_mode.app_rd_data_reg[130] ;\n wire \\not_strict_mode.app_rd_data_reg[131] ;\n wire \\not_strict_mode.app_rd_data_reg[132] ;\n wire \\not_strict_mode.app_rd_data_reg[133] ;\n wire \\not_strict_mode.app_rd_data_reg[134] ;\n wire \\not_strict_mode.app_rd_data_reg[135] ;\n wire \\not_strict_mode.app_rd_data_reg[136] ;\n wire \\not_strict_mode.app_rd_data_reg[137] ;\n wire \\not_strict_mode.app_rd_data_reg[138] ;\n wire \\not_strict_mode.app_rd_data_reg[139] ;\n wire \\not_strict_mode.app_rd_data_reg[13] ;\n wire \\not_strict_mode.app_rd_data_reg[140] ;\n wire \\not_strict_mode.app_rd_data_reg[141] ;\n wire \\not_strict_mode.app_rd_data_reg[142] ;\n wire \\not_strict_mode.app_rd_data_reg[143] ;\n wire \\not_strict_mode.app_rd_data_reg[144] ;\n wire \\not_strict_mode.app_rd_data_reg[145] ;\n wire \\not_strict_mode.app_rd_data_reg[146] ;\n wire \\not_strict_mode.app_rd_data_reg[147] ;\n wire \\not_strict_mode.app_rd_data_reg[148] ;\n wire \\not_strict_mode.app_rd_data_reg[149] ;\n wire \\not_strict_mode.app_rd_data_reg[14] ;\n wire \\not_strict_mode.app_rd_data_reg[150] ;\n wire \\not_strict_mode.app_rd_data_reg[151] ;\n wire \\not_strict_mode.app_rd_data_reg[152] ;\n wire \\not_strict_mode.app_rd_data_reg[153] ;\n wire \\not_strict_mode.app_rd_data_reg[154] ;\n wire \\not_strict_mode.app_rd_data_reg[155] ;\n wire \\not_strict_mode.app_rd_data_reg[156] ;\n wire \\not_strict_mode.app_rd_data_reg[157] ;\n wire \\not_strict_mode.app_rd_data_reg[158] ;\n wire \\not_strict_mode.app_rd_data_reg[159] ;\n wire \\not_strict_mode.app_rd_data_reg[15] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[15]_0 ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[15]_1 ;\n wire \\not_strict_mode.app_rd_data_reg[160] ;\n wire \\not_strict_mode.app_rd_data_reg[161] ;\n wire \\not_strict_mode.app_rd_data_reg[162] ;\n wire \\not_strict_mode.app_rd_data_reg[163] ;\n wire \\not_strict_mode.app_rd_data_reg[164] ;\n wire \\not_strict_mode.app_rd_data_reg[165] ;\n wire \\not_strict_mode.app_rd_data_reg[166] ;\n wire \\not_strict_mode.app_rd_data_reg[167] ;\n wire \\not_strict_mode.app_rd_data_reg[168] ;\n wire \\not_strict_mode.app_rd_data_reg[169] ;\n wire \\not_strict_mode.app_rd_data_reg[16] ;\n wire \\not_strict_mode.app_rd_data_reg[170] ;\n wire \\not_strict_mode.app_rd_data_reg[171] ;\n wire \\not_strict_mode.app_rd_data_reg[172] ;\n wire \\not_strict_mode.app_rd_data_reg[173] ;\n wire \\not_strict_mode.app_rd_data_reg[174] ;\n wire \\not_strict_mode.app_rd_data_reg[175] ;\n wire \\not_strict_mode.app_rd_data_reg[176] ;\n wire \\not_strict_mode.app_rd_data_reg[177] ;\n wire \\not_strict_mode.app_rd_data_reg[178] ;\n wire \\not_strict_mode.app_rd_data_reg[179] ;\n wire \\not_strict_mode.app_rd_data_reg[17] ;\n wire \\not_strict_mode.app_rd_data_reg[180] ;\n wire \\not_strict_mode.app_rd_data_reg[181] ;\n wire \\not_strict_mode.app_rd_data_reg[182] ;\n wire \\not_strict_mode.app_rd_data_reg[183] ;\n wire \\not_strict_mode.app_rd_data_reg[184] ;\n wire \\not_strict_mode.app_rd_data_reg[185] ;\n wire \\not_strict_mode.app_rd_data_reg[186] ;\n wire \\not_strict_mode.app_rd_data_reg[187] ;\n wire \\not_strict_mode.app_rd_data_reg[188] ;\n wire \\not_strict_mode.app_rd_data_reg[189] ;\n wire \\not_strict_mode.app_rd_data_reg[18] ;\n wire \\not_strict_mode.app_rd_data_reg[190] ;\n wire \\not_strict_mode.app_rd_data_reg[191] ;\n wire \\not_strict_mode.app_rd_data_reg[192] ;\n wire \\not_strict_mode.app_rd_data_reg[193] ;\n wire \\not_strict_mode.app_rd_data_reg[194] ;\n wire \\not_strict_mode.app_rd_data_reg[195] ;\n wire \\not_strict_mode.app_rd_data_reg[196] ;\n wire \\not_strict_mode.app_rd_data_reg[197] ;\n wire \\not_strict_mode.app_rd_data_reg[198] ;\n wire \\not_strict_mode.app_rd_data_reg[199] ;\n wire \\not_strict_mode.app_rd_data_reg[19] ;\n wire \\not_strict_mode.app_rd_data_reg[1] ;\n wire \\not_strict_mode.app_rd_data_reg[200] ;\n wire \\not_strict_mode.app_rd_data_reg[201] ;\n wire \\not_strict_mode.app_rd_data_reg[202] ;\n wire \\not_strict_mode.app_rd_data_reg[203] ;\n wire \\not_strict_mode.app_rd_data_reg[204] ;\n wire \\not_strict_mode.app_rd_data_reg[205] ;\n wire \\not_strict_mode.app_rd_data_reg[206] ;\n wire \\not_strict_mode.app_rd_data_reg[207] ;\n wire \\not_strict_mode.app_rd_data_reg[208] ;\n wire \\not_strict_mode.app_rd_data_reg[209] ;\n wire \\not_strict_mode.app_rd_data_reg[20] ;\n wire \\not_strict_mode.app_rd_data_reg[210] ;\n wire \\not_strict_mode.app_rd_data_reg[211] ;\n wire \\not_strict_mode.app_rd_data_reg[212] ;\n wire \\not_strict_mode.app_rd_data_reg[213] ;\n wire \\not_strict_mode.app_rd_data_reg[214] ;\n wire \\not_strict_mode.app_rd_data_reg[215] ;\n wire \\not_strict_mode.app_rd_data_reg[216] ;\n wire \\not_strict_mode.app_rd_data_reg[217] ;\n wire \\not_strict_mode.app_rd_data_reg[218] ;\n wire \\not_strict_mode.app_rd_data_reg[219] ;\n wire \\not_strict_mode.app_rd_data_reg[21] ;\n wire \\not_strict_mode.app_rd_data_reg[220] ;\n wire \\not_strict_mode.app_rd_data_reg[221] ;\n wire \\not_strict_mode.app_rd_data_reg[222] ;\n wire \\not_strict_mode.app_rd_data_reg[223] ;\n wire \\not_strict_mode.app_rd_data_reg[224] ;\n wire \\not_strict_mode.app_rd_data_reg[225] ;\n wire \\not_strict_mode.app_rd_data_reg[226] ;\n wire \\not_strict_mode.app_rd_data_reg[227] ;\n wire \\not_strict_mode.app_rd_data_reg[228] ;\n wire \\not_strict_mode.app_rd_data_reg[228]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[229] ;\n wire \\not_strict_mode.app_rd_data_reg[22] ;\n wire \\not_strict_mode.app_rd_data_reg[230] ;\n wire \\not_strict_mode.app_rd_data_reg[231] ;\n wire \\not_strict_mode.app_rd_data_reg[232] ;\n wire \\not_strict_mode.app_rd_data_reg[233] ;\n wire \\not_strict_mode.app_rd_data_reg[234] ;\n wire \\not_strict_mode.app_rd_data_reg[235] ;\n wire \\not_strict_mode.app_rd_data_reg[236] ;\n wire \\not_strict_mode.app_rd_data_reg[236]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[237] ;\n wire \\not_strict_mode.app_rd_data_reg[238] ;\n wire \\not_strict_mode.app_rd_data_reg[239] ;\n wire \\not_strict_mode.app_rd_data_reg[23] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[23]_0 ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[23]_1 ;\n wire \\not_strict_mode.app_rd_data_reg[240] ;\n wire \\not_strict_mode.app_rd_data_reg[241] ;\n wire \\not_strict_mode.app_rd_data_reg[242] ;\n wire \\not_strict_mode.app_rd_data_reg[243] ;\n wire \\not_strict_mode.app_rd_data_reg[244] ;\n wire \\not_strict_mode.app_rd_data_reg[244]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[245] ;\n wire \\not_strict_mode.app_rd_data_reg[246] ;\n wire \\not_strict_mode.app_rd_data_reg[247] ;\n wire \\not_strict_mode.app_rd_data_reg[248] ;\n wire \\not_strict_mode.app_rd_data_reg[249] ;\n wire \\not_strict_mode.app_rd_data_reg[24] ;\n wire \\not_strict_mode.app_rd_data_reg[250] ;\n wire \\not_strict_mode.app_rd_data_reg[251] ;\n wire \\not_strict_mode.app_rd_data_reg[252] ;\n wire \\not_strict_mode.app_rd_data_reg[252]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[253] ;\n wire \\not_strict_mode.app_rd_data_reg[254] ;\n wire \\not_strict_mode.app_rd_data_reg[255] ;\n wire [255:0]\\not_strict_mode.app_rd_data_reg[255]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[25] ;\n wire \\not_strict_mode.app_rd_data_reg[26] ;\n wire \\not_strict_mode.app_rd_data_reg[27] ;\n wire \\not_strict_mode.app_rd_data_reg[28] ;\n wire \\not_strict_mode.app_rd_data_reg[29] ;\n wire \\not_strict_mode.app_rd_data_reg[2] ;\n wire \\not_strict_mode.app_rd_data_reg[30] ;\n wire \\not_strict_mode.app_rd_data_reg[31] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[31]_0 ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[31]_1 ;\n wire \\not_strict_mode.app_rd_data_reg[32] ;\n wire \\not_strict_mode.app_rd_data_reg[33] ;\n wire \\not_strict_mode.app_rd_data_reg[34] ;\n wire \\not_strict_mode.app_rd_data_reg[35] ;\n wire \\not_strict_mode.app_rd_data_reg[36] ;\n wire \\not_strict_mode.app_rd_data_reg[37] ;\n wire \\not_strict_mode.app_rd_data_reg[38] ;\n wire \\not_strict_mode.app_rd_data_reg[39] ;\n wire \\not_strict_mode.app_rd_data_reg[3] ;\n wire \\not_strict_mode.app_rd_data_reg[40] ;\n wire \\not_strict_mode.app_rd_data_reg[41] ;\n wire \\not_strict_mode.app_rd_data_reg[42] ;\n wire \\not_strict_mode.app_rd_data_reg[43] ;\n wire \\not_strict_mode.app_rd_data_reg[44] ;\n wire \\not_strict_mode.app_rd_data_reg[45] ;\n wire \\not_strict_mode.app_rd_data_reg[46] ;\n wire \\not_strict_mode.app_rd_data_reg[47] ;\n wire \\not_strict_mode.app_rd_data_reg[48] ;\n wire \\not_strict_mode.app_rd_data_reg[49] ;\n wire \\not_strict_mode.app_rd_data_reg[4] ;\n wire \\not_strict_mode.app_rd_data_reg[50] ;\n wire \\not_strict_mode.app_rd_data_reg[51] ;\n wire \\not_strict_mode.app_rd_data_reg[52] ;\n wire \\not_strict_mode.app_rd_data_reg[53] ;\n wire \\not_strict_mode.app_rd_data_reg[54] ;\n wire \\not_strict_mode.app_rd_data_reg[55] ;\n wire \\not_strict_mode.app_rd_data_reg[56] ;\n wire \\not_strict_mode.app_rd_data_reg[57] ;\n wire \\not_strict_mode.app_rd_data_reg[58] ;\n wire \\not_strict_mode.app_rd_data_reg[59] ;\n wire \\not_strict_mode.app_rd_data_reg[5] ;\n wire \\not_strict_mode.app_rd_data_reg[60] ;\n wire \\not_strict_mode.app_rd_data_reg[61] ;\n wire \\not_strict_mode.app_rd_data_reg[62] ;\n wire \\not_strict_mode.app_rd_data_reg[63] ;\n wire \\not_strict_mode.app_rd_data_reg[64] ;\n wire \\not_strict_mode.app_rd_data_reg[65] ;\n wire \\not_strict_mode.app_rd_data_reg[66] ;\n wire \\not_strict_mode.app_rd_data_reg[67] ;\n wire \\not_strict_mode.app_rd_data_reg[68] ;\n wire \\not_strict_mode.app_rd_data_reg[69] ;\n wire \\not_strict_mode.app_rd_data_reg[6] ;\n wire \\not_strict_mode.app_rd_data_reg[70] ;\n wire \\not_strict_mode.app_rd_data_reg[71] ;\n wire \\not_strict_mode.app_rd_data_reg[72] ;\n wire \\not_strict_mode.app_rd_data_reg[73] ;\n wire \\not_strict_mode.app_rd_data_reg[74] ;\n wire \\not_strict_mode.app_rd_data_reg[75] ;\n wire \\not_strict_mode.app_rd_data_reg[76] ;\n wire \\not_strict_mode.app_rd_data_reg[77] ;\n wire \\not_strict_mode.app_rd_data_reg[78] ;\n wire \\not_strict_mode.app_rd_data_reg[79] ;\n wire \\not_strict_mode.app_rd_data_reg[7] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[7]_0 ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[7]_1 ;\n wire \\not_strict_mode.app_rd_data_reg[80] ;\n wire \\not_strict_mode.app_rd_data_reg[81] ;\n wire \\not_strict_mode.app_rd_data_reg[82] ;\n wire \\not_strict_mode.app_rd_data_reg[83] ;\n wire \\not_strict_mode.app_rd_data_reg[84] ;\n wire \\not_strict_mode.app_rd_data_reg[85] ;\n wire \\not_strict_mode.app_rd_data_reg[86] ;\n wire \\not_strict_mode.app_rd_data_reg[87] ;\n wire \\not_strict_mode.app_rd_data_reg[88] ;\n wire \\not_strict_mode.app_rd_data_reg[89] ;\n wire \\not_strict_mode.app_rd_data_reg[8] ;\n wire \\not_strict_mode.app_rd_data_reg[90] ;\n wire \\not_strict_mode.app_rd_data_reg[91] ;\n wire \\not_strict_mode.app_rd_data_reg[92] ;\n wire \\not_strict_mode.app_rd_data_reg[93] ;\n wire \\not_strict_mode.app_rd_data_reg[94] ;\n wire \\not_strict_mode.app_rd_data_reg[95] ;\n wire \\not_strict_mode.app_rd_data_reg[96] ;\n wire \\not_strict_mode.app_rd_data_reg[97] ;\n wire \\not_strict_mode.app_rd_data_reg[98] ;\n wire \\not_strict_mode.app_rd_data_reg[99] ;\n wire \\not_strict_mode.app_rd_data_reg[9] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ;\n wire \\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n wire [0:0]of_ctl_full_v;\n wire ofs_rdy_r_reg;\n wire ofs_rdy_r_reg_0;\n wire out;\n wire p_0_out;\n wire phy_ctl_mstr_empty;\n wire phy_ctl_wr_i2;\n wire [35:0]phy_dout;\n wire phy_if_empty_r_reg;\n wire phy_if_reset;\n wire phy_mc_ctl_full;\n wire phy_rddata_en;\n wire phy_read_calib;\n wire phy_write_calib;\n wire [3:0]\\pi_dqs_found_lanes_r1_reg[3] ;\n wire pi_en_stg2_f_reg;\n wire pi_en_stg2_f_reg_0;\n wire pi_en_stg2_f_reg_1;\n wire pi_en_stg2_f_reg_2;\n wire pi_phase_locked_all_r1_reg;\n wire [5:0]\\pi_rdval_cnt_reg[5] ;\n wire pi_stg2_f_incdec_reg;\n wire pi_stg2_f_incdec_reg_0;\n wire pi_stg2_f_incdec_reg_1;\n wire pi_stg2_f_incdec_reg_2;\n wire pll_locked;\n wire [5:0]\\po_counter_read_val_r_reg[5] ;\n wire [5:1]\\po_counter_read_val_w[0]_0 ;\n wire [4:0]\\po_rdval_cnt_reg[8] ;\n wire [4:0]\\po_rdval_cnt_reg[8]_0 ;\n wire [1:0]\\po_stg2_wrcal_cnt_reg[1] ;\n wire prbs_rdlvl_start_reg;\n wire ram_init_done_r;\n wire rclk_delay_11;\n wire \\rclk_delay_reg[10]_srl11_i_1_n_0 ;\n wire rd_buf_we;\n wire [1:0]\\rd_mux_sel_r_reg[1] ;\n wire [33:0]\\rd_ptr_reg[3] ;\n wire [17:0]\\rd_ptr_reg[3]_0 ;\n wire \\rd_ptr_timing_reg[2] ;\n wire \\rd_ptr_timing_reg[2]_0 ;\n wire \\rd_ptr_timing_reg[2]_1 ;\n wire \\rd_ptr_timing_reg[2]_10 ;\n wire \\rd_ptr_timing_reg[2]_2 ;\n wire \\rd_ptr_timing_reg[2]_3 ;\n wire \\rd_ptr_timing_reg[2]_4 ;\n wire \\rd_ptr_timing_reg[2]_5 ;\n wire \\rd_ptr_timing_reg[2]_6 ;\n wire \\rd_ptr_timing_reg[2]_7 ;\n wire \\rd_ptr_timing_reg[2]_8 ;\n wire \\rd_ptr_timing_reg[2]_9 ;\n wire [0:0]\\read_fifo.fifo_out_data_r_reg[6] ;\n wire \\read_fifo.fifo_out_data_r_reg[6]_0 ;\n wire \\read_fifo.tail_r_reg[0] ;\n wire [1:1]ref_dll_lock_w;\n wire rst_out_i_1_n_0;\n wire rst_primitives;\n wire rst_primitives_i_1_n_0;\n wire [0:0]\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ;\n wire rst_sync_r1_reg;\n wire rstdiv0_sync_r1_reg_rep__9;\n wire sync_pulse;\n wire sys_rst;\n wire [0:0]tail_r;\n wire wr_en;\n wire wr_en_5;\n wire wr_en_6;\n wire [3:0]\\wr_ptr_timing_reg[2] ;\n wire [3:0]\\wr_ptr_timing_reg[2]_0 ;\n wire [3:0]\\wr_ptr_timing_reg[2]_1 ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[224] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[225] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[226] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[227] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[228] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[229] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[230] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[231] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[232] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[233] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[234] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[235] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[236] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[237] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[238] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[239] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[240] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[241] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[242] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[243] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[244] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[245] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[246] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[247] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[248] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[249] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[250] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[251] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[252] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[253] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[254] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[255] ;\n wire [31:0]\\write_buffer.wr_buf_out_data_reg[287] ;\n\n ddr3_ifmig_7series_v4_0_ddr_phy_4lanes \\ddr_phy_4lanes_0.u_ddr_phy_4lanes \n (.A(A),\n .CLK(CLK),\n .CLKB0(CLKB0),\n .CLKB0_7(CLKB0_7),\n .CLKB0_8(CLKB0_8),\n .CLKB0_9(CLKB0_9),\n .COUNTERLOADVAL(COUNTERLOADVAL),\n .DOA(DOA),\n .DOB(DOB),\n .DOC(DOC),\n .E(E),\n .LD0(LD0),\n .LD0_3(LD0_3),\n .LD0_4(LD0_4),\n .LD0_5(LD0_5),\n .Q(Q),\n .RST0(RST0),\n ._phy_ctl_full_p__0(_phy_ctl_full_p__0),\n .\\byte_r_reg[0] (\\byte_r_reg[0]_0 ),\n .\\byte_r_reg[1] (\\byte_r_reg[1] ),\n .\\calib_sel_reg[0] (\\calib_sel_reg[0]_3 ),\n .\\calib_sel_reg[0]_0 (\\calib_sel_reg[0]_4 ),\n .\\calib_sel_reg[0]_1 (\\calib_sel_reg[0]_5 ),\n .\\calib_sel_reg[0]_2 (\\calib_sel_reg[0]_6 ),\n .\\calib_sel_reg[0]_3 (\\calib_sel_reg[0]_7 ),\n .\\calib_sel_reg[1] (\\calib_sel_reg[1]_7 ),\n .\\calib_sel_reg[1]_0 (\\calib_sel_reg[1]_8 ),\n .\\calib_sel_reg[1]_1 (\\calib_sel_reg[3] [1:0]),\n .\\calib_zero_inputs_reg[0] (\\calib_zero_inputs_reg[0] ),\n .\\calib_zero_inputs_reg[0]_0 (\\calib_zero_inputs_reg[0]_0 ),\n .\\calib_zero_inputs_reg[0]_1 (\\calib_zero_inputs_reg[0]_1 ),\n .ck_po_stg2_f_en_reg(ck_po_stg2_f_en_reg),\n .ck_po_stg2_f_en_reg_0(ck_po_stg2_f_en_reg_0),\n .ck_po_stg2_f_en_reg_1(ck_po_stg2_f_en_reg_1),\n .ck_po_stg2_f_en_reg_2(ck_po_stg2_f_en_reg_2),\n .ck_po_stg2_f_indec_reg(ck_po_stg2_f_indec_reg),\n .ck_po_stg2_f_indec_reg_0(ck_po_stg2_f_indec_reg_0),\n .ck_po_stg2_f_indec_reg_1(ck_po_stg2_f_indec_reg_1),\n .ck_po_stg2_f_indec_reg_2(ck_po_stg2_f_indec_reg_2),\n .\\data_bytes_r_reg[63] (\\data_bytes_r_reg[63] ),\n .delay_done_r4_reg(delay_done_r4_reg),\n .delay_done_r4_reg_0(delay_done_r4_reg_0),\n .delay_done_r4_reg_1(delay_done_r4_reg_1),\n .delay_done_r4_reg_2(delay_done_r4_reg_2),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ),\n .\\fine_delay_mod_reg[23] (\\fine_delay_mod_reg[23] ),\n .freq_refclk(freq_refclk),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\gen_byte_sel_div1.calib_in_common_reg_2 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_0 (\\gen_byte_sel_div1.calib_in_common_reg_3 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_1 (\\gen_byte_sel_div1.calib_in_common_reg_4 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_10 (\\gen_byte_sel_div1.calib_in_common_reg_13 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_11 (\\gen_byte_sel_div1.calib_in_common_reg_14 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_12 (\\gen_byte_sel_div1.calib_in_common_reg_15 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_13 (\\gen_byte_sel_div1.calib_in_common_reg_16 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_14 (\\gen_byte_sel_div1.calib_in_common_reg_17 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_15 (\\gen_byte_sel_div1.calib_in_common_reg_18 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_16 (\\gen_byte_sel_div1.calib_in_common_reg_19 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_17 (\\gen_byte_sel_div1.calib_in_common_reg_20 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_2 (\\gen_byte_sel_div1.calib_in_common_reg_5 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_3 (\\gen_byte_sel_div1.calib_in_common_reg_6 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_4 (\\gen_byte_sel_div1.calib_in_common_reg_7 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_5 (\\gen_byte_sel_div1.calib_in_common_reg_8 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_6 (\\gen_byte_sel_div1.calib_in_common_reg_9 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_7 (\\gen_byte_sel_div1.calib_in_common_reg_10 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_8 (\\gen_byte_sel_div1.calib_in_common_reg_11 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_9 (\\gen_byte_sel_div1.calib_in_common_reg_12 ),\n .\\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] (\\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] (\\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] (\\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] (\\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] (\\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] (\\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] (\\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] (\\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),\n .\\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] (\\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] (\\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] (\\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] (\\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] (\\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] (\\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] (\\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] (\\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),\n .\\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] (\\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] (\\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] (\\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] (\\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] (\\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] (\\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] (\\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] (\\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),\n .\\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] (\\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] (\\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] (\\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] (\\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] (\\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] (\\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] (\\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] (\\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),\n .\\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] (\\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] (\\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] (\\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] (\\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] (\\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] (\\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] (\\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] (\\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),\n .\\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] (\\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] (\\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] (\\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] (\\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] (\\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] (\\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] (\\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] (\\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),\n .\\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] (\\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] (\\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] (\\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] (\\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] (\\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] (\\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] (\\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] (\\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),\n .\\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] (\\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] (\\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] (\\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] (\\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] (\\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] (\\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] (\\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] (\\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),\n .\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] (\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ),\n .\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] (\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ),\n .\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] (\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ),\n .\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] (\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ),\n .idelay_inc(idelay_inc),\n .idelay_ld_rst(idelay_ld_rst),\n .idelay_ld_rst_0(idelay_ld_rst_0),\n .idelay_ld_rst_1(idelay_ld_rst_1),\n .idelay_ld_rst_2(idelay_ld_rst_2),\n .in0(in0),\n .init_calib_complete_reg_rep(init_calib_complete_reg_rep),\n .\\mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13 (\\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_105 ),\n .mcGo_reg_0(\\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_95 ),\n .mcGo_w__0(mcGo_w__0),\n .mem_dq_in(mem_dq_in),\n .mem_dq_out(mem_dq_out[35:0]),\n .mem_dq_ts(mem_dq_ts),\n .mem_dqs_in(mem_dqs_in),\n .mem_dqs_out(mem_dqs_out),\n .mem_dqs_ts(mem_dqs_ts),\n .mem_refclk(mem_refclk),\n .mmcm_locked(mmcm_locked),\n .mux_rd_valid_r_reg(mux_rd_valid_r_reg),\n .mux_wrdata(mux_wrdata),\n .mux_wrdata_en(mux_wrdata_en),\n .mux_wrdata_mask(mux_wrdata_mask),\n .\\my_empty_reg[1] (\\my_empty_reg[1]_2 ),\n .\\my_empty_reg[1]_0 (\\my_empty_reg[1]_3 ),\n .\\my_empty_reg[1]_1 (\\my_empty_reg[1]_4 ),\n .\\my_empty_reg[1]_2 (\\my_empty_reg[1]_5 ),\n .\\my_empty_reg[7] (\\my_empty_reg[7] ),\n .\\my_empty_reg[7]_0 (\\my_empty_reg[7]_0 ),\n .\\my_empty_reg[7]_1 (\\my_empty_reg[7]_1 ),\n .\\my_empty_reg[7]_2 (\\my_empty_reg[7]_2 ),\n .\\not_strict_mode.app_rd_data_reg[0] (\\not_strict_mode.app_rd_data_reg[0] ),\n .\\not_strict_mode.app_rd_data_reg[100] (\\not_strict_mode.app_rd_data_reg[100] ),\n .\\not_strict_mode.app_rd_data_reg[101] (\\not_strict_mode.app_rd_data_reg[101] ),\n .\\not_strict_mode.app_rd_data_reg[102] (\\not_strict_mode.app_rd_data_reg[102] ),\n .\\not_strict_mode.app_rd_data_reg[103] (\\not_strict_mode.app_rd_data_reg[103] ),\n .\\not_strict_mode.app_rd_data_reg[104] (\\not_strict_mode.app_rd_data_reg[104] ),\n .\\not_strict_mode.app_rd_data_reg[105] (\\not_strict_mode.app_rd_data_reg[105] ),\n .\\not_strict_mode.app_rd_data_reg[106] (\\not_strict_mode.app_rd_data_reg[106] ),\n .\\not_strict_mode.app_rd_data_reg[107] (\\not_strict_mode.app_rd_data_reg[107] ),\n .\\not_strict_mode.app_rd_data_reg[108] (\\not_strict_mode.app_rd_data_reg[108] ),\n .\\not_strict_mode.app_rd_data_reg[109] (\\not_strict_mode.app_rd_data_reg[109] ),\n .\\not_strict_mode.app_rd_data_reg[10] (\\not_strict_mode.app_rd_data_reg[10] ),\n .\\not_strict_mode.app_rd_data_reg[110] (\\not_strict_mode.app_rd_data_reg[110] ),\n .\\not_strict_mode.app_rd_data_reg[111] (\\not_strict_mode.app_rd_data_reg[111] ),\n .\\not_strict_mode.app_rd_data_reg[112] (\\not_strict_mode.app_rd_data_reg[112] ),\n .\\not_strict_mode.app_rd_data_reg[113] (\\not_strict_mode.app_rd_data_reg[113] ),\n .\\not_strict_mode.app_rd_data_reg[114] (\\not_strict_mode.app_rd_data_reg[114] ),\n .\\not_strict_mode.app_rd_data_reg[115] (\\not_strict_mode.app_rd_data_reg[115] ),\n .\\not_strict_mode.app_rd_data_reg[116] (\\not_strict_mode.app_rd_data_reg[116] ),\n .\\not_strict_mode.app_rd_data_reg[117] (\\not_strict_mode.app_rd_data_reg[117] ),\n .\\not_strict_mode.app_rd_data_reg[118] (\\not_strict_mode.app_rd_data_reg[118] ),\n .\\not_strict_mode.app_rd_data_reg[119] (\\not_strict_mode.app_rd_data_reg[119] ),\n .\\not_strict_mode.app_rd_data_reg[11] (\\not_strict_mode.app_rd_data_reg[11] ),\n .\\not_strict_mode.app_rd_data_reg[120] (\\not_strict_mode.app_rd_data_reg[120] ),\n .\\not_strict_mode.app_rd_data_reg[121] (\\not_strict_mode.app_rd_data_reg[121] ),\n .\\not_strict_mode.app_rd_data_reg[122] (\\not_strict_mode.app_rd_data_reg[122] ),\n .\\not_strict_mode.app_rd_data_reg[123] (\\not_strict_mode.app_rd_data_reg[123] ),\n .\\not_strict_mode.app_rd_data_reg[124] (\\not_strict_mode.app_rd_data_reg[124] ),\n .\\not_strict_mode.app_rd_data_reg[125] (\\not_strict_mode.app_rd_data_reg[125] ),\n .\\not_strict_mode.app_rd_data_reg[126] (\\not_strict_mode.app_rd_data_reg[126] ),\n .\\not_strict_mode.app_rd_data_reg[127] (\\not_strict_mode.app_rd_data_reg[127] ),\n .\\not_strict_mode.app_rd_data_reg[128] (\\not_strict_mode.app_rd_data_reg[128] ),\n .\\not_strict_mode.app_rd_data_reg[129] (\\not_strict_mode.app_rd_data_reg[129] ),\n .\\not_strict_mode.app_rd_data_reg[12] (\\not_strict_mode.app_rd_data_reg[12] ),\n .\\not_strict_mode.app_rd_data_reg[130] (\\not_strict_mode.app_rd_data_reg[130] ),\n .\\not_strict_mode.app_rd_data_reg[131] (\\not_strict_mode.app_rd_data_reg[131] ),\n .\\not_strict_mode.app_rd_data_reg[132] (\\not_strict_mode.app_rd_data_reg[132] ),\n .\\not_strict_mode.app_rd_data_reg[133] (\\not_strict_mode.app_rd_data_reg[133] ),\n .\\not_strict_mode.app_rd_data_reg[134] (\\not_strict_mode.app_rd_data_reg[134] ),\n .\\not_strict_mode.app_rd_data_reg[135] (\\not_strict_mode.app_rd_data_reg[135] ),\n .\\not_strict_mode.app_rd_data_reg[136] (\\not_strict_mode.app_rd_data_reg[136] ),\n .\\not_strict_mode.app_rd_data_reg[137] (\\not_strict_mode.app_rd_data_reg[137] ),\n .\\not_strict_mode.app_rd_data_reg[138] (\\not_strict_mode.app_rd_data_reg[138] ),\n .\\not_strict_mode.app_rd_data_reg[139] (\\not_strict_mode.app_rd_data_reg[139] ),\n .\\not_strict_mode.app_rd_data_reg[13] (\\not_strict_mode.app_rd_data_reg[13] ),\n .\\not_strict_mode.app_rd_data_reg[140] (\\not_strict_mode.app_rd_data_reg[140] ),\n .\\not_strict_mode.app_rd_data_reg[141] (\\not_strict_mode.app_rd_data_reg[141] ),\n .\\not_strict_mode.app_rd_data_reg[142] (\\not_strict_mode.app_rd_data_reg[142] ),\n .\\not_strict_mode.app_rd_data_reg[143] (\\not_strict_mode.app_rd_data_reg[143] ),\n .\\not_strict_mode.app_rd_data_reg[144] (\\not_strict_mode.app_rd_data_reg[144] ),\n .\\not_strict_mode.app_rd_data_reg[145] (\\not_strict_mode.app_rd_data_reg[145] ),\n .\\not_strict_mode.app_rd_data_reg[146] (\\not_strict_mode.app_rd_data_reg[146] ),\n .\\not_strict_mode.app_rd_data_reg[147] (\\not_strict_mode.app_rd_data_reg[147] ),\n .\\not_strict_mode.app_rd_data_reg[148] (\\not_strict_mode.app_rd_data_reg[148] ),\n .\\not_strict_mode.app_rd_data_reg[149] (\\not_strict_mode.app_rd_data_reg[149] ),\n .\\not_strict_mode.app_rd_data_reg[14] (\\not_strict_mode.app_rd_data_reg[14] ),\n .\\not_strict_mode.app_rd_data_reg[150] (\\not_strict_mode.app_rd_data_reg[150] ),\n .\\not_strict_mode.app_rd_data_reg[151] (\\not_strict_mode.app_rd_data_reg[151] ),\n .\\not_strict_mode.app_rd_data_reg[152] (\\not_strict_mode.app_rd_data_reg[152] ),\n .\\not_strict_mode.app_rd_data_reg[153] (\\not_strict_mode.app_rd_data_reg[153] ),\n .\\not_strict_mode.app_rd_data_reg[154] (\\not_strict_mode.app_rd_data_reg[154] ),\n .\\not_strict_mode.app_rd_data_reg[155] (\\not_strict_mode.app_rd_data_reg[155] ),\n .\\not_strict_mode.app_rd_data_reg[156] (\\not_strict_mode.app_rd_data_reg[156] ),\n .\\not_strict_mode.app_rd_data_reg[157] (\\not_strict_mode.app_rd_data_reg[157] ),\n .\\not_strict_mode.app_rd_data_reg[158] (\\not_strict_mode.app_rd_data_reg[158] ),\n .\\not_strict_mode.app_rd_data_reg[159] (\\not_strict_mode.app_rd_data_reg[159] ),\n .\\not_strict_mode.app_rd_data_reg[15] (\\not_strict_mode.app_rd_data_reg[15] ),\n .\\not_strict_mode.app_rd_data_reg[15]_0 (\\not_strict_mode.app_rd_data_reg[15]_0 ),\n .\\not_strict_mode.app_rd_data_reg[15]_1 (\\not_strict_mode.app_rd_data_reg[15]_1 ),\n .\\not_strict_mode.app_rd_data_reg[160] (\\not_strict_mode.app_rd_data_reg[160] ),\n .\\not_strict_mode.app_rd_data_reg[161] (\\not_strict_mode.app_rd_data_reg[161] ),\n .\\not_strict_mode.app_rd_data_reg[162] (\\not_strict_mode.app_rd_data_reg[162] ),\n .\\not_strict_mode.app_rd_data_reg[163] (\\not_strict_mode.app_rd_data_reg[163] ),\n .\\not_strict_mode.app_rd_data_reg[164] (\\not_strict_mode.app_rd_data_reg[164] ),\n .\\not_strict_mode.app_rd_data_reg[165] (\\not_strict_mode.app_rd_data_reg[165] ),\n .\\not_strict_mode.app_rd_data_reg[166] (\\not_strict_mode.app_rd_data_reg[166] ),\n .\\not_strict_mode.app_rd_data_reg[167] (\\not_strict_mode.app_rd_data_reg[167] ),\n .\\not_strict_mode.app_rd_data_reg[168] (\\not_strict_mode.app_rd_data_reg[168] ),\n .\\not_strict_mode.app_rd_data_reg[169] (\\not_strict_mode.app_rd_data_reg[169] ),\n .\\not_strict_mode.app_rd_data_reg[16] (\\not_strict_mode.app_rd_data_reg[16] ),\n .\\not_strict_mode.app_rd_data_reg[170] (\\not_strict_mode.app_rd_data_reg[170] ),\n .\\not_strict_mode.app_rd_data_reg[171] (\\not_strict_mode.app_rd_data_reg[171] ),\n .\\not_strict_mode.app_rd_data_reg[172] (\\not_strict_mode.app_rd_data_reg[172] ),\n .\\not_strict_mode.app_rd_data_reg[173] (\\not_strict_mode.app_rd_data_reg[173] ),\n .\\not_strict_mode.app_rd_data_reg[174] (\\not_strict_mode.app_rd_data_reg[174] ),\n .\\not_strict_mode.app_rd_data_reg[175] (\\not_strict_mode.app_rd_data_reg[175] ),\n .\\not_strict_mode.app_rd_data_reg[176] (\\not_strict_mode.app_rd_data_reg[176] ),\n .\\not_strict_mode.app_rd_data_reg[177] (\\not_strict_mode.app_rd_data_reg[177] ),\n .\\not_strict_mode.app_rd_data_reg[178] (\\not_strict_mode.app_rd_data_reg[178] ),\n .\\not_strict_mode.app_rd_data_reg[179] (\\not_strict_mode.app_rd_data_reg[179] ),\n .\\not_strict_mode.app_rd_data_reg[17] (\\not_strict_mode.app_rd_data_reg[17] ),\n .\\not_strict_mode.app_rd_data_reg[180] (\\not_strict_mode.app_rd_data_reg[180] ),\n .\\not_strict_mode.app_rd_data_reg[181] (\\not_strict_mode.app_rd_data_reg[181] ),\n .\\not_strict_mode.app_rd_data_reg[182] (\\not_strict_mode.app_rd_data_reg[182] ),\n .\\not_strict_mode.app_rd_data_reg[183] (\\not_strict_mode.app_rd_data_reg[183] ),\n .\\not_strict_mode.app_rd_data_reg[184] (\\not_strict_mode.app_rd_data_reg[184] ),\n .\\not_strict_mode.app_rd_data_reg[185] (\\not_strict_mode.app_rd_data_reg[185] ),\n .\\not_strict_mode.app_rd_data_reg[186] (\\not_strict_mode.app_rd_data_reg[186] ),\n .\\not_strict_mode.app_rd_data_reg[187] (\\not_strict_mode.app_rd_data_reg[187] ),\n .\\not_strict_mode.app_rd_data_reg[188] (\\not_strict_mode.app_rd_data_reg[188] ),\n .\\not_strict_mode.app_rd_data_reg[189] (\\not_strict_mode.app_rd_data_reg[189] ),\n .\\not_strict_mode.app_rd_data_reg[18] (\\not_strict_mode.app_rd_data_reg[18] ),\n .\\not_strict_mode.app_rd_data_reg[190] (\\not_strict_mode.app_rd_data_reg[190] ),\n .\\not_strict_mode.app_rd_data_reg[191] (\\not_strict_mode.app_rd_data_reg[191] ),\n .\\not_strict_mode.app_rd_data_reg[192] (\\not_strict_mode.app_rd_data_reg[192] ),\n .\\not_strict_mode.app_rd_data_reg[193] (\\not_strict_mode.app_rd_data_reg[193] ),\n .\\not_strict_mode.app_rd_data_reg[194] (\\not_strict_mode.app_rd_data_reg[194] ),\n .\\not_strict_mode.app_rd_data_reg[195] (\\not_strict_mode.app_rd_data_reg[195] ),\n .\\not_strict_mode.app_rd_data_reg[196] (\\not_strict_mode.app_rd_data_reg[196] ),\n .\\not_strict_mode.app_rd_data_reg[197] (\\not_strict_mode.app_rd_data_reg[197] ),\n .\\not_strict_mode.app_rd_data_reg[198] (\\not_strict_mode.app_rd_data_reg[198] ),\n .\\not_strict_mode.app_rd_data_reg[199] (\\not_strict_mode.app_rd_data_reg[199] ),\n .\\not_strict_mode.app_rd_data_reg[19] (\\not_strict_mode.app_rd_data_reg[19] ),\n .\\not_strict_mode.app_rd_data_reg[1] (\\not_strict_mode.app_rd_data_reg[1] ),\n .\\not_strict_mode.app_rd_data_reg[200] (\\not_strict_mode.app_rd_data_reg[200] ),\n .\\not_strict_mode.app_rd_data_reg[201] (\\not_strict_mode.app_rd_data_reg[201] ),\n .\\not_strict_mode.app_rd_data_reg[202] (\\not_strict_mode.app_rd_data_reg[202] ),\n .\\not_strict_mode.app_rd_data_reg[203] (\\not_strict_mode.app_rd_data_reg[203] ),\n .\\not_strict_mode.app_rd_data_reg[204] (\\not_strict_mode.app_rd_data_reg[204] ),\n .\\not_strict_mode.app_rd_data_reg[205] (\\not_strict_mode.app_rd_data_reg[205] ),\n .\\not_strict_mode.app_rd_data_reg[206] (\\not_strict_mode.app_rd_data_reg[206] ),\n .\\not_strict_mode.app_rd_data_reg[207] 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.\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 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.\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ),\n .\\not_strict_mode.status_ram.rd_buf_we_r1_reg (\\not_strict_mode.status_ram.rd_buf_we_r1_reg ),\n .ofs_rdy_r_reg(ofs_rdy_r_reg),\n .ofs_rdy_r_reg_0(ofs_rdy_r_reg_0),\n .out(out),\n .p_0_out(p_0_out),\n .phy_ctl_mstr_empty(phy_ctl_mstr_empty),\n .phy_ctl_wr_i2(phy_ctl_wr_i2),\n .phy_ctl_wr_i2_reg(rst_primitives_i_1_n_0),\n .phy_if_empty_r_reg(phy_if_empty_r_reg),\n .phy_if_reset(phy_if_reset),\n .phy_rddata_en(phy_rddata_en),\n .phy_read_calib(phy_read_calib),\n .phy_write_calib(phy_write_calib),\n .\\pi_dqs_found_lanes_r1_reg[3] (\\pi_dqs_found_lanes_r1_reg[3] ),\n .pi_en_stg2_f_reg(pi_en_stg2_f_reg),\n .pi_en_stg2_f_reg_0(pi_en_stg2_f_reg_0),\n .pi_en_stg2_f_reg_1(pi_en_stg2_f_reg_1),\n .pi_en_stg2_f_reg_2(pi_en_stg2_f_reg_2),\n .pi_phase_locked_all_r1_reg(pi_phase_locked_all_r1_reg),\n .\\pi_rdval_cnt_reg[5] (\\pi_rdval_cnt_reg[5] ),\n .pi_stg2_f_incdec_reg(pi_stg2_f_incdec_reg),\n .pi_stg2_f_incdec_reg_0(pi_stg2_f_incdec_reg_0),\n .pi_stg2_f_incdec_reg_1(pi_stg2_f_incdec_reg_1),\n .pi_stg2_f_incdec_reg_2(pi_stg2_f_incdec_reg_2),\n .pll_locked(pll_locked),\n .\\po_rdval_cnt_reg[8] ({\\po_rdval_cnt_reg[8] [4:2],\\po_counter_read_val_w[0]_0 [5:4],\\po_rdval_cnt_reg[8] [1],\\po_counter_read_val_w[0]_0 [2:1],\\po_rdval_cnt_reg[8] [0]}),\n .\\po_stg2_wrcal_cnt_reg[1] (\\po_stg2_wrcal_cnt_reg[1] ),\n .prbs_rdlvl_start_reg(prbs_rdlvl_start_reg),\n .ram_init_done_r(ram_init_done_r),\n .rclk_delay_11(rclk_delay_11),\n .\\rclk_delay_reg[11]_0 (rst_out_i_1_n_0),\n .rd_buf_we(rd_buf_we),\n .\\rd_mux_sel_r_reg[1] (\\rd_mux_sel_r_reg[1] ),\n .\\read_fifo.fifo_out_data_r_reg[6] (\\read_fifo.fifo_out_data_r_reg[6] ),\n .\\read_fifo.fifo_out_data_r_reg[6]_0 (\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .\\read_fifo.tail_r_reg[0] (\\read_fifo.tail_r_reg[0] ),\n .ref_dll_lock_w(ref_dll_lock_w),\n .rst_primitives(rst_primitives),\n .rst_primitives_reg_0(\\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_93 ),\n .rst_primitives_reg_1(\\rclk_delay_reg[10]_srl11_i_1_n_0 ),\n .\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] (\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .rst_sync_r1_reg(rst_sync_r1_reg),\n .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9),\n .sync_pulse(sync_pulse),\n .sys_rst(sys_rst),\n .tail_r(tail_r),\n .\\write_buffer.wr_buf_out_data_reg[224] (\\write_buffer.wr_buf_out_data_reg[224] ),\n .\\write_buffer.wr_buf_out_data_reg[225] (\\write_buffer.wr_buf_out_data_reg[225] ),\n .\\write_buffer.wr_buf_out_data_reg[226] (\\write_buffer.wr_buf_out_data_reg[226] ),\n .\\write_buffer.wr_buf_out_data_reg[227] (\\write_buffer.wr_buf_out_data_reg[227] ),\n .\\write_buffer.wr_buf_out_data_reg[228] (\\write_buffer.wr_buf_out_data_reg[228] ),\n .\\write_buffer.wr_buf_out_data_reg[229] (\\write_buffer.wr_buf_out_data_reg[229] ),\n .\\write_buffer.wr_buf_out_data_reg[230] (\\write_buffer.wr_buf_out_data_reg[230] ),\n .\\write_buffer.wr_buf_out_data_reg[231] (\\write_buffer.wr_buf_out_data_reg[231] ),\n .\\write_buffer.wr_buf_out_data_reg[232] (\\write_buffer.wr_buf_out_data_reg[232] ),\n .\\write_buffer.wr_buf_out_data_reg[233] (\\write_buffer.wr_buf_out_data_reg[233] ),\n .\\write_buffer.wr_buf_out_data_reg[234] (\\write_buffer.wr_buf_out_data_reg[234] ),\n .\\write_buffer.wr_buf_out_data_reg[235] (\\write_buffer.wr_buf_out_data_reg[235] ),\n .\\write_buffer.wr_buf_out_data_reg[236] (\\write_buffer.wr_buf_out_data_reg[236] ),\n .\\write_buffer.wr_buf_out_data_reg[237] (\\write_buffer.wr_buf_out_data_reg[237] ),\n .\\write_buffer.wr_buf_out_data_reg[238] (\\write_buffer.wr_buf_out_data_reg[238] ),\n .\\write_buffer.wr_buf_out_data_reg[239] (\\write_buffer.wr_buf_out_data_reg[239] ),\n .\\write_buffer.wr_buf_out_data_reg[240] (\\write_buffer.wr_buf_out_data_reg[240] ),\n .\\write_buffer.wr_buf_out_data_reg[241] (\\write_buffer.wr_buf_out_data_reg[241] ),\n .\\write_buffer.wr_buf_out_data_reg[242] (\\write_buffer.wr_buf_out_data_reg[242] ),\n .\\write_buffer.wr_buf_out_data_reg[243] (\\write_buffer.wr_buf_out_data_reg[243] ),\n .\\write_buffer.wr_buf_out_data_reg[244] (\\write_buffer.wr_buf_out_data_reg[244] ),\n .\\write_buffer.wr_buf_out_data_reg[245] (\\write_buffer.wr_buf_out_data_reg[245] ),\n .\\write_buffer.wr_buf_out_data_reg[246] (\\write_buffer.wr_buf_out_data_reg[246] ),\n .\\write_buffer.wr_buf_out_data_reg[247] (\\write_buffer.wr_buf_out_data_reg[247] ),\n .\\write_buffer.wr_buf_out_data_reg[248] (\\write_buffer.wr_buf_out_data_reg[248] ),\n .\\write_buffer.wr_buf_out_data_reg[249] (\\write_buffer.wr_buf_out_data_reg[249] ),\n .\\write_buffer.wr_buf_out_data_reg[250] (\\write_buffer.wr_buf_out_data_reg[250] ),\n .\\write_buffer.wr_buf_out_data_reg[251] (\\write_buffer.wr_buf_out_data_reg[251] ),\n .\\write_buffer.wr_buf_out_data_reg[252] (\\write_buffer.wr_buf_out_data_reg[252] ),\n .\\write_buffer.wr_buf_out_data_reg[253] (\\write_buffer.wr_buf_out_data_reg[253] ),\n .\\write_buffer.wr_buf_out_data_reg[254] (\\write_buffer.wr_buf_out_data_reg[254] ),\n .\\write_buffer.wr_buf_out_data_reg[255] (\\write_buffer.wr_buf_out_data_reg[255] ),\n .\\write_buffer.wr_buf_out_data_reg[287] (\\write_buffer.wr_buf_out_data_reg[287] ));\n ddr3_ifmig_7series_v4_0_ddr_phy_4lanes__parameterized0 \\ddr_phy_4lanes_1.u_ddr_phy_4lanes \n (.CLK(CLK),\n .D0(D0),\n .D1(D1),\n .D2(D2),\n .D3(D3),\n .D4(D4),\n .D5(D5),\n .D6(D6),\n .D7(D7),\n .D8(D8),\n .D9(D9),\n .D_po_coarse_enable110_out(D_po_coarse_enable110_out),\n .D_po_counter_read_en122_out(D_po_counter_read_en122_out),\n .D_po_fine_enable107_out(D_po_fine_enable107_out),\n .D_po_fine_inc113_out(D_po_fine_inc113_out),\n .D_po_sel_fine_oclk_delay125_out(D_po_sel_fine_oclk_delay125_out),\n .PHYCTLWD({Q[10:9],\\data_offset_1_i2_reg[5] ,Q[2:0]}),\n .Q(\\wr_ptr_timing_reg[2] ),\n .RST0(RST0),\n ._phy_ctl_full_p__0(_phy_ctl_full_p__0),\n .\\byte_r_reg[0] (\\byte_r_reg[0] ),\n .\\calib_sel_reg[0] (\\calib_sel_reg[0] ),\n .\\calib_sel_reg[0]_0 (\\calib_sel_reg[0]_0 ),\n .\\calib_sel_reg[0]_1 (\\calib_sel_reg[0]_1 ),\n .\\calib_sel_reg[0]_2 (\\calib_sel_reg[0]_2 ),\n .\\calib_sel_reg[1] (\\calib_sel_reg[1] ),\n .\\calib_sel_reg[1]_0 (\\calib_sel_reg[1]_0 ),\n .\\calib_sel_reg[1]_1 (\\calib_sel_reg[1]_1 ),\n .\\calib_sel_reg[1]_2 (\\calib_sel_reg[1]_2 ),\n .\\calib_sel_reg[1]_3 (\\calib_sel_reg[1]_3 ),\n .\\calib_sel_reg[1]_4 (\\calib_sel_reg[1]_4 ),\n .\\calib_sel_reg[1]_5 (\\calib_sel_reg[1]_5 ),\n .\\calib_sel_reg[1]_6 (\\calib_sel_reg[1]_6 ),\n .\\calib_sel_reg[3] (\\calib_sel_reg[3] ),\n .ddr_ck_out(ddr_ck_out),\n .freq_refclk(freq_refclk),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\gen_byte_sel_div1.calib_in_common_reg ),\n .\\gen_byte_sel_div1.calib_in_common_reg_0 (\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_1 (\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] (\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] (\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ),\n .in0(in0),\n .init_calib_complete_reg_rep(init_calib_complete_reg_rep),\n .init_calib_complete_reg_rep__5(init_calib_complete_reg_rep__5),\n .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6),\n .init_calib_complete_reg_rep__6_0(init_calib_complete_reg_rep__6_0),\n .mcGo_w__0(mcGo_w__0),\n .mc_address(mc_address),\n .mc_cas_n(mc_cas_n),\n .mem_dq_out(mem_dq_out[59:36]),\n .mem_out(mem_out),\n .mem_refclk(mem_refclk),\n .mux_cmd_wren(mux_cmd_wren),\n .\\my_empty_reg[1] (\\my_empty_reg[1] ),\n .\\my_empty_reg[1]_0 (\\my_empty_reg[1]_0 ),\n .\\my_empty_reg[1]_1 (\\my_empty_reg[1]_1 ),\n .\\my_empty_reg[1]_2 (\\my_empty_reg[1]_6 ),\n .\\my_empty_reg[7] (\\my_empty_reg[7]_3 ),\n .of_ctl_full_v(of_ctl_full_v),\n .phy_ctl_mstr_empty(phy_ctl_mstr_empty),\n .phy_ctl_wr_i2(phy_ctl_wr_i2),\n .phy_dout(phy_dout),\n .phy_mc_ctl_full(phy_mc_ctl_full),\n .phy_read_calib(phy_read_calib),\n .phy_write_calib(phy_write_calib),\n .pll_locked(pll_locked),\n .\\po_counter_read_val_r_reg[5] (\\po_counter_read_val_r_reg[5] ),\n .\\po_counter_read_val_reg[5]_0 ({\\po_counter_read_val_w[0]_0 [5:4],\\po_rdval_cnt_reg[8] [1],\\po_counter_read_val_w[0]_0 [2:1],\\po_rdval_cnt_reg[8] [0]}),\n .\\po_rdval_cnt_reg[8] (\\po_rdval_cnt_reg[8]_0 ),\n .\\rd_ptr_reg[3] (\\rd_ptr_reg[3] ),\n .\\rd_ptr_reg[3]_0 (\\rd_ptr_reg[3]_0 ),\n .\\rd_ptr_timing_reg[2] (\\rd_ptr_timing_reg[2] ),\n .\\rd_ptr_timing_reg[2]_0 (\\rd_ptr_timing_reg[2]_0 ),\n .\\rd_ptr_timing_reg[2]_1 (\\rd_ptr_timing_reg[2]_1 ),\n .\\rd_ptr_timing_reg[2]_10 (\\rd_ptr_timing_reg[2]_10 ),\n .\\rd_ptr_timing_reg[2]_2 (\\rd_ptr_timing_reg[2]_2 ),\n .\\rd_ptr_timing_reg[2]_3 (\\rd_ptr_timing_reg[2]_3 ),\n .\\rd_ptr_timing_reg[2]_4 (\\rd_ptr_timing_reg[2]_4 ),\n .\\rd_ptr_timing_reg[2]_5 (\\rd_ptr_timing_reg[2]_5 ),\n .\\rd_ptr_timing_reg[2]_6 (\\rd_ptr_timing_reg[2]_6 ),\n .\\rd_ptr_timing_reg[2]_7 (\\rd_ptr_timing_reg[2]_7 ),\n .\\rd_ptr_timing_reg[2]_8 (\\rd_ptr_timing_reg[2]_8 ),\n .\\rd_ptr_timing_reg[2]_9 (\\rd_ptr_timing_reg[2]_9 ),\n .ref_dll_lock_w(ref_dll_lock_w),\n .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9),\n .sync_pulse(sync_pulse),\n .wr_en(wr_en),\n .wr_en_5(wr_en_5),\n .wr_en_6(wr_en_6),\n .\\wr_ptr_timing_reg[2] (\\wr_ptr_timing_reg[2]_0 ),\n .\\wr_ptr_timing_reg[2]_0 (\\wr_ptr_timing_reg[2]_1 ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/mcGo_r_reg \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/mcGo_r_reg[13]_srl14___u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12 \" *) \n SRL16E #(\n .INIT(16'h0000)) \n \\mcGo_r_reg[13]_srl14___u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12 \n (.A0(1'b1),\n .A1(1'b0),\n .A2(1'b1),\n .A3(1'b1),\n .CE(1'b1),\n .CLK(CLK),\n .D(\\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_105 ),\n .Q(\\mcGo_r_reg[13]_srl14___u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13 \n (.C(CLK),\n .CE(1'b1),\n .D(\\mcGo_r_reg[13]_srl14___u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12_n_0 ),\n .Q(\\mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13_n_0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mcGo_r_reg[15] \n (.C(CLK),\n .CE(1'b1),\n .D(mcGo_r_reg_gate_n_0),\n .Q(\\calib_seq_reg[0] ),\n .R(in0));\n LUT2 #(\n .INIT(4'h8)) \n mcGo_r_reg_gate\n (.I0(\\mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13_n_0 ),\n .I1(mcGo_r_reg_r_13_n_0),\n .O(mcGo_r_reg_gate_n_0));\n FDRE #(\n .INIT(1'b0)) \n mcGo_r_reg_r\n (.C(CLK),\n .CE(1'b1),\n .D(1'b1),\n .Q(mcGo_r_reg_r_n_0),\n .R(in0));\n FDRE #(\n .INIT(1'b0)) \n mcGo_r_reg_r_0\n (.C(CLK),\n .CE(1'b1),\n .D(mcGo_r_reg_r_n_0),\n .Q(mcGo_r_reg_r_0_n_0),\n .R(in0));\n FDRE #(\n .INIT(1'b0)) \n mcGo_r_reg_r_1\n (.C(CLK),\n .CE(1'b1),\n .D(mcGo_r_reg_r_0_n_0),\n .Q(mcGo_r_reg_r_1_n_0),\n .R(in0));\n FDRE #(\n .INIT(1'b0)) \n mcGo_r_reg_r_10\n (.C(CLK),\n .CE(1'b1),\n .D(mcGo_r_reg_r_9_n_0),\n .Q(mcGo_r_reg_r_10_n_0),\n .R(in0));\n FDRE #(\n .INIT(1'b0)) \n mcGo_r_reg_r_11\n (.C(CLK),\n .CE(1'b1),\n .D(mcGo_r_reg_r_10_n_0),\n .Q(mcGo_r_reg_r_11_n_0),\n .R(in0));\n FDRE #(\n .INIT(1'b0)) \n mcGo_r_reg_r_12\n (.C(CLK),\n .CE(1'b1),\n .D(mcGo_r_reg_r_11_n_0),\n .Q(mcGo_r_reg_r_12_n_0),\n .R(in0));\n FDRE #(\n .INIT(1'b0)) \n mcGo_r_reg_r_13\n (.C(CLK),\n .CE(1'b1),\n .D(mcGo_r_reg_r_12_n_0),\n .Q(mcGo_r_reg_r_13_n_0),\n .R(in0));\n FDRE #(\n .INIT(1'b0)) \n mcGo_r_reg_r_2\n (.C(CLK),\n .CE(1'b1),\n .D(mcGo_r_reg_r_1_n_0),\n .Q(mcGo_r_reg_r_2_n_0),\n .R(in0));\n FDRE #(\n .INIT(1'b0)) \n mcGo_r_reg_r_3\n (.C(CLK),\n .CE(1'b1),\n .D(mcGo_r_reg_r_2_n_0),\n .Q(mcGo_r_reg_r_3_n_0),\n .R(in0));\n FDRE #(\n .INIT(1'b0)) \n mcGo_r_reg_r_4\n (.C(CLK),\n .CE(1'b1),\n .D(mcGo_r_reg_r_3_n_0),\n .Q(mcGo_r_reg_r_4_n_0),\n .R(in0));\n FDRE #(\n .INIT(1'b0)) \n mcGo_r_reg_r_5\n (.C(CLK),\n .CE(1'b1),\n .D(mcGo_r_reg_r_4_n_0),\n .Q(mcGo_r_reg_r_5_n_0),\n .R(in0));\n FDRE #(\n .INIT(1'b0)) \n mcGo_r_reg_r_6\n (.C(CLK),\n .CE(1'b1),\n .D(mcGo_r_reg_r_5_n_0),\n .Q(mcGo_r_reg_r_6_n_0),\n .R(in0));\n FDRE #(\n .INIT(1'b0)) \n mcGo_r_reg_r_7\n (.C(CLK),\n .CE(1'b1),\n .D(mcGo_r_reg_r_6_n_0),\n .Q(mcGo_r_reg_r_7_n_0),\n .R(in0));\n FDRE #(\n .INIT(1'b0)) \n mcGo_r_reg_r_8\n (.C(CLK),\n .CE(1'b1),\n .D(mcGo_r_reg_r_7_n_0),\n .Q(mcGo_r_reg_r_8_n_0),\n .R(in0));\n FDRE #(\n .INIT(1'b0)) \n mcGo_r_reg_r_9\n (.C(CLK),\n .CE(1'b1),\n .D(mcGo_r_reg_r_8_n_0),\n .Q(mcGo_r_reg_r_9_n_0),\n .R(in0));\n LUT1 #(\n .INIT(2'h1)) \n \\rclk_delay_reg[10]_srl11_i_1 \n (.I0(rst_primitives),\n .O(\\rclk_delay_reg[10]_srl11_i_1_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n rst_out_i_1\n (.I0(rclk_delay_11),\n .I1(\\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_95 ),\n .O(rst_out_i_1_n_0));\n LUT1 #(\n .INIT(2'h1)) \n rst_primitives_i_1\n (.I0(\\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_93 ),\n .O(rst_primitives_i_1_n_0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_mc_phy_wrapper\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_mc_phy_wrapper\n (ddr3_reset_n,\n ddr3_cas_n,\n ddr3_ras_n,\n ddr3_we_n,\n ddr3_addr,\n ddr3_ba,\n ddr3_cs_n,\n ddr3_odt,\n ddr3_cke,\n ddr3_dm,\n fine_delay_sel_r,\n \\fine_delay_mod_reg[26]_0 ,\n \\rd_ptr_timing_reg[2] ,\n \\rd_ptr_timing_reg[2]_0 ,\n \\rd_ptr_timing_reg[2]_1 ,\n \\rd_ptr_timing_reg[2]_2 ,\n \\rd_ptr_timing_reg[2]_3 ,\n \\rd_ptr_timing_reg[2]_4 ,\n \\rd_ptr_timing_reg[2]_5 ,\n \\rd_ptr_timing_reg[2]_6 ,\n \\rd_ptr_timing_reg[2]_7 ,\n \\rd_ptr_timing_reg[2]_8 ,\n \\rd_ptr_timing_reg[2]_9 ,\n \\rd_ptr_timing_reg[2]_10 ,\n \\pi_dqs_found_lanes_r1_reg[3] ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,\n \\not_strict_mode.app_rd_data_reg[252] ,\n idelay_ld_rst,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,\n \\not_strict_mode.app_rd_data_reg[244] ,\n idelay_ld_rst_0,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,\n \\not_strict_mode.app_rd_data_reg[236] ,\n idelay_ld_rst_1,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,\n \\not_strict_mode.app_rd_data_reg[228] ,\n idelay_ld_rst_2,\n \\calib_seq_reg[0] ,\n \\my_empty_reg[1] ,\n \\my_empty_reg[1]_0 ,\n phy_mc_ctl_full,\n \\my_empty_reg[1]_1 ,\n \\my_empty_reg[1]_2 ,\n \\my_empty_reg[1]_3 ,\n \\my_empty_reg[1]_4 ,\n \\my_empty_reg[1]_5 ,\n rd_buf_we,\n \\not_strict_mode.status_ram.rd_buf_we_r1_reg ,\n \\my_empty_reg[7] ,\n \\my_empty_reg[1]_6 ,\n phy_rddata_en,\n mux_rd_valid_r_reg,\n rst_sync_r1_reg,\n \\byte_r_reg[0] ,\n \\po_counter_read_val_r_reg[5] ,\n \\data_bytes_r_reg[63] ,\n \\not_strict_mode.app_rd_data_reg[255] ,\n \\not_strict_mode.app_rd_data_reg[239] ,\n \\not_strict_mode.app_rd_data_reg[247] ,\n \\not_strict_mode.app_rd_data_reg[231] ,\n \\not_strict_mode.app_rd_data_reg[254] ,\n \\not_strict_mode.app_rd_data_reg[238] ,\n \\not_strict_mode.app_rd_data_reg[246] ,\n \\not_strict_mode.app_rd_data_reg[230] ,\n \\not_strict_mode.app_rd_data_reg[253] ,\n \\not_strict_mode.app_rd_data_reg[237] ,\n \\not_strict_mode.app_rd_data_reg[245] ,\n \\not_strict_mode.app_rd_data_reg[229] ,\n \\not_strict_mode.app_rd_data_reg[252]_0 ,\n \\not_strict_mode.app_rd_data_reg[236]_0 ,\n \\not_strict_mode.app_rd_data_reg[244]_0 ,\n \\not_strict_mode.app_rd_data_reg[228]_0 ,\n \\not_strict_mode.app_rd_data_reg[251] ,\n \\not_strict_mode.app_rd_data_reg[235] ,\n \\not_strict_mode.app_rd_data_reg[243] ,\n \\not_strict_mode.app_rd_data_reg[227] ,\n \\not_strict_mode.app_rd_data_reg[250] ,\n \\not_strict_mode.app_rd_data_reg[234] ,\n \\not_strict_mode.app_rd_data_reg[242] ,\n \\not_strict_mode.app_rd_data_reg[226] ,\n \\not_strict_mode.app_rd_data_reg[249] ,\n \\not_strict_mode.app_rd_data_reg[233] ,\n \\not_strict_mode.app_rd_data_reg[241] ,\n \\not_strict_mode.app_rd_data_reg[225] ,\n \\not_strict_mode.app_rd_data_reg[248] ,\n \\not_strict_mode.app_rd_data_reg[232] ,\n \\not_strict_mode.app_rd_data_reg[240] ,\n \\not_strict_mode.app_rd_data_reg[224] ,\n \\not_strict_mode.app_rd_data_reg[223] ,\n \\not_strict_mode.app_rd_data_reg[207] ,\n \\not_strict_mode.app_rd_data_reg[215] ,\n \\not_strict_mode.app_rd_data_reg[199] ,\n \\not_strict_mode.app_rd_data_reg[222] ,\n \\not_strict_mode.app_rd_data_reg[206] ,\n \\not_strict_mode.app_rd_data_reg[214] ,\n \\not_strict_mode.app_rd_data_reg[198] ,\n \\not_strict_mode.app_rd_data_reg[221] ,\n \\not_strict_mode.app_rd_data_reg[205] ,\n \\not_strict_mode.app_rd_data_reg[213] ,\n \\not_strict_mode.app_rd_data_reg[197] ,\n \\not_strict_mode.app_rd_data_reg[220] ,\n \\not_strict_mode.app_rd_data_reg[204] ,\n \\not_strict_mode.app_rd_data_reg[212] ,\n \\not_strict_mode.app_rd_data_reg[196] ,\n \\not_strict_mode.app_rd_data_reg[219] ,\n \\not_strict_mode.app_rd_data_reg[203] ,\n \\not_strict_mode.app_rd_data_reg[211] ,\n \\not_strict_mode.app_rd_data_reg[195] ,\n \\not_strict_mode.app_rd_data_reg[218] ,\n \\not_strict_mode.app_rd_data_reg[202] ,\n \\not_strict_mode.app_rd_data_reg[210] ,\n \\not_strict_mode.app_rd_data_reg[194] ,\n \\not_strict_mode.app_rd_data_reg[217] ,\n \\not_strict_mode.app_rd_data_reg[201] ,\n \\not_strict_mode.app_rd_data_reg[209] ,\n \\not_strict_mode.app_rd_data_reg[193] ,\n \\not_strict_mode.app_rd_data_reg[216] ,\n \\not_strict_mode.app_rd_data_reg[200] ,\n \\not_strict_mode.app_rd_data_reg[208] ,\n \\not_strict_mode.app_rd_data_reg[192] ,\n \\not_strict_mode.app_rd_data_reg[191] ,\n \\not_strict_mode.app_rd_data_reg[175] ,\n \\not_strict_mode.app_rd_data_reg[183] ,\n \\not_strict_mode.app_rd_data_reg[167] ,\n \\not_strict_mode.app_rd_data_reg[190] ,\n \\not_strict_mode.app_rd_data_reg[174] ,\n \\not_strict_mode.app_rd_data_reg[182] ,\n \\not_strict_mode.app_rd_data_reg[166] ,\n \\not_strict_mode.app_rd_data_reg[189] ,\n \\not_strict_mode.app_rd_data_reg[173] ,\n \\not_strict_mode.app_rd_data_reg[181] ,\n \\not_strict_mode.app_rd_data_reg[165] ,\n \\not_strict_mode.app_rd_data_reg[188] ,\n \\not_strict_mode.app_rd_data_reg[172] ,\n \\not_strict_mode.app_rd_data_reg[180] ,\n \\not_strict_mode.app_rd_data_reg[164] ,\n \\not_strict_mode.app_rd_data_reg[187] ,\n \\not_strict_mode.app_rd_data_reg[171] ,\n \\not_strict_mode.app_rd_data_reg[179] ,\n \\not_strict_mode.app_rd_data_reg[163] ,\n \\not_strict_mode.app_rd_data_reg[186] ,\n \\not_strict_mode.app_rd_data_reg[170] ,\n \\not_strict_mode.app_rd_data_reg[178] ,\n \\not_strict_mode.app_rd_data_reg[162] ,\n \\not_strict_mode.app_rd_data_reg[185] ,\n \\not_strict_mode.app_rd_data_reg[169] ,\n \\not_strict_mode.app_rd_data_reg[177] ,\n \\not_strict_mode.app_rd_data_reg[161] ,\n \\not_strict_mode.app_rd_data_reg[184] ,\n \\not_strict_mode.app_rd_data_reg[168] ,\n \\not_strict_mode.app_rd_data_reg[176] ,\n \\not_strict_mode.app_rd_data_reg[160] ,\n \\not_strict_mode.app_rd_data_reg[159] ,\n \\not_strict_mode.app_rd_data_reg[143] ,\n \\not_strict_mode.app_rd_data_reg[151] ,\n \\not_strict_mode.app_rd_data_reg[135] ,\n \\not_strict_mode.app_rd_data_reg[158] ,\n \\not_strict_mode.app_rd_data_reg[142] ,\n \\not_strict_mode.app_rd_data_reg[150] ,\n \\not_strict_mode.app_rd_data_reg[134] ,\n \\not_strict_mode.app_rd_data_reg[157] ,\n \\not_strict_mode.app_rd_data_reg[141] ,\n \\not_strict_mode.app_rd_data_reg[149] ,\n \\not_strict_mode.app_rd_data_reg[133] ,\n \\not_strict_mode.app_rd_data_reg[156] ,\n \\not_strict_mode.app_rd_data_reg[140] ,\n \\not_strict_mode.app_rd_data_reg[148] ,\n \\not_strict_mode.app_rd_data_reg[132] ,\n \\not_strict_mode.app_rd_data_reg[155] ,\n \\not_strict_mode.app_rd_data_reg[139] ,\n \\not_strict_mode.app_rd_data_reg[147] ,\n \\not_strict_mode.app_rd_data_reg[131] ,\n \\not_strict_mode.app_rd_data_reg[154] ,\n \\not_strict_mode.app_rd_data_reg[138] ,\n \\not_strict_mode.app_rd_data_reg[146] ,\n \\not_strict_mode.app_rd_data_reg[130] ,\n \\not_strict_mode.app_rd_data_reg[153] ,\n \\not_strict_mode.app_rd_data_reg[137] ,\n \\not_strict_mode.app_rd_data_reg[145] ,\n \\not_strict_mode.app_rd_data_reg[129] ,\n \\not_strict_mode.app_rd_data_reg[152] ,\n \\not_strict_mode.app_rd_data_reg[136] ,\n \\not_strict_mode.app_rd_data_reg[144] ,\n \\not_strict_mode.app_rd_data_reg[128] ,\n \\not_strict_mode.app_rd_data_reg[127] ,\n \\not_strict_mode.app_rd_data_reg[111] ,\n \\not_strict_mode.app_rd_data_reg[119] ,\n \\not_strict_mode.app_rd_data_reg[103] ,\n \\not_strict_mode.app_rd_data_reg[126] ,\n \\not_strict_mode.app_rd_data_reg[110] ,\n \\not_strict_mode.app_rd_data_reg[118] ,\n \\not_strict_mode.app_rd_data_reg[102] ,\n \\not_strict_mode.app_rd_data_reg[125] ,\n \\not_strict_mode.app_rd_data_reg[109] ,\n \\not_strict_mode.app_rd_data_reg[117] ,\n \\not_strict_mode.app_rd_data_reg[101] ,\n \\not_strict_mode.app_rd_data_reg[124] ,\n \\not_strict_mode.app_rd_data_reg[108] ,\n \\not_strict_mode.app_rd_data_reg[116] ,\n \\not_strict_mode.app_rd_data_reg[100] ,\n \\not_strict_mode.app_rd_data_reg[123] ,\n \\not_strict_mode.app_rd_data_reg[107] ,\n \\not_strict_mode.app_rd_data_reg[115] ,\n \\not_strict_mode.app_rd_data_reg[99] ,\n \\not_strict_mode.app_rd_data_reg[122] ,\n \\not_strict_mode.app_rd_data_reg[106] ,\n \\not_strict_mode.app_rd_data_reg[114] ,\n \\not_strict_mode.app_rd_data_reg[98] ,\n \\not_strict_mode.app_rd_data_reg[121] ,\n \\not_strict_mode.app_rd_data_reg[105] ,\n \\not_strict_mode.app_rd_data_reg[113] ,\n \\not_strict_mode.app_rd_data_reg[97] ,\n \\not_strict_mode.app_rd_data_reg[120] ,\n \\not_strict_mode.app_rd_data_reg[104] ,\n \\not_strict_mode.app_rd_data_reg[112] ,\n \\not_strict_mode.app_rd_data_reg[96] ,\n \\not_strict_mode.app_rd_data_reg[95] ,\n \\not_strict_mode.app_rd_data_reg[79] ,\n \\not_strict_mode.app_rd_data_reg[87] ,\n \\not_strict_mode.app_rd_data_reg[71] ,\n \\not_strict_mode.app_rd_data_reg[94] ,\n \\not_strict_mode.app_rd_data_reg[78] ,\n \\not_strict_mode.app_rd_data_reg[86] ,\n \\not_strict_mode.app_rd_data_reg[70] ,\n \\not_strict_mode.app_rd_data_reg[93] ,\n \\not_strict_mode.app_rd_data_reg[77] ,\n \\not_strict_mode.app_rd_data_reg[85] ,\n \\not_strict_mode.app_rd_data_reg[69] ,\n \\not_strict_mode.app_rd_data_reg[92] ,\n \\not_strict_mode.app_rd_data_reg[76] ,\n \\not_strict_mode.app_rd_data_reg[84] ,\n \\not_strict_mode.app_rd_data_reg[68] ,\n \\not_strict_mode.app_rd_data_reg[91] ,\n \\not_strict_mode.app_rd_data_reg[75] ,\n \\not_strict_mode.app_rd_data_reg[83] ,\n \\not_strict_mode.app_rd_data_reg[67] ,\n \\not_strict_mode.app_rd_data_reg[90] ,\n \\not_strict_mode.app_rd_data_reg[74] ,\n \\not_strict_mode.app_rd_data_reg[82] ,\n \\not_strict_mode.app_rd_data_reg[66] ,\n \\not_strict_mode.app_rd_data_reg[89] ,\n \\not_strict_mode.app_rd_data_reg[73] ,\n \\not_strict_mode.app_rd_data_reg[81] ,\n \\not_strict_mode.app_rd_data_reg[65] ,\n \\not_strict_mode.app_rd_data_reg[88] ,\n \\not_strict_mode.app_rd_data_reg[72] ,\n \\not_strict_mode.app_rd_data_reg[80] ,\n \\not_strict_mode.app_rd_data_reg[64] ,\n \\not_strict_mode.app_rd_data_reg[63] ,\n \\not_strict_mode.app_rd_data_reg[47] ,\n \\not_strict_mode.app_rd_data_reg[55] ,\n \\not_strict_mode.app_rd_data_reg[39] ,\n \\not_strict_mode.app_rd_data_reg[62] ,\n \\not_strict_mode.app_rd_data_reg[46] ,\n \\not_strict_mode.app_rd_data_reg[54] ,\n \\not_strict_mode.app_rd_data_reg[38] ,\n \\not_strict_mode.app_rd_data_reg[61] ,\n \\not_strict_mode.app_rd_data_reg[45] ,\n \\not_strict_mode.app_rd_data_reg[53] ,\n \\not_strict_mode.app_rd_data_reg[37] ,\n \\not_strict_mode.app_rd_data_reg[60] ,\n \\not_strict_mode.app_rd_data_reg[44] ,\n \\not_strict_mode.app_rd_data_reg[52] ,\n \\not_strict_mode.app_rd_data_reg[36] ,\n \\not_strict_mode.app_rd_data_reg[59] ,\n \\not_strict_mode.app_rd_data_reg[43] ,\n \\not_strict_mode.app_rd_data_reg[51] ,\n \\not_strict_mode.app_rd_data_reg[35] ,\n \\not_strict_mode.app_rd_data_reg[58] ,\n \\not_strict_mode.app_rd_data_reg[42] ,\n \\not_strict_mode.app_rd_data_reg[50] ,\n \\not_strict_mode.app_rd_data_reg[34] ,\n \\not_strict_mode.app_rd_data_reg[57] ,\n \\not_strict_mode.app_rd_data_reg[41] ,\n \\not_strict_mode.app_rd_data_reg[49] ,\n \\not_strict_mode.app_rd_data_reg[33] ,\n \\not_strict_mode.app_rd_data_reg[56] ,\n \\not_strict_mode.app_rd_data_reg[40] ,\n \\not_strict_mode.app_rd_data_reg[48] ,\n \\not_strict_mode.app_rd_data_reg[32] ,\n \\not_strict_mode.app_rd_data_reg[31] ,\n \\not_strict_mode.app_rd_data_reg[15] ,\n \\not_strict_mode.app_rd_data_reg[23] ,\n \\not_strict_mode.app_rd_data_reg[7] ,\n \\not_strict_mode.app_rd_data_reg[30] ,\n \\not_strict_mode.app_rd_data_reg[14] ,\n \\not_strict_mode.app_rd_data_reg[22] ,\n \\not_strict_mode.app_rd_data_reg[6] ,\n \\not_strict_mode.app_rd_data_reg[29] ,\n \\not_strict_mode.app_rd_data_reg[13] ,\n \\not_strict_mode.app_rd_data_reg[21] ,\n \\not_strict_mode.app_rd_data_reg[5] ,\n \\not_strict_mode.app_rd_data_reg[28] ,\n \\not_strict_mode.app_rd_data_reg[12] ,\n \\not_strict_mode.app_rd_data_reg[20] ,\n \\not_strict_mode.app_rd_data_reg[4] ,\n \\not_strict_mode.app_rd_data_reg[27] ,\n \\not_strict_mode.app_rd_data_reg[11] ,\n \\not_strict_mode.app_rd_data_reg[19] ,\n \\not_strict_mode.app_rd_data_reg[3] ,\n \\not_strict_mode.app_rd_data_reg[26] ,\n \\not_strict_mode.app_rd_data_reg[10] ,\n \\not_strict_mode.app_rd_data_reg[18] ,\n \\not_strict_mode.app_rd_data_reg[2] ,\n \\not_strict_mode.app_rd_data_reg[25] ,\n \\not_strict_mode.app_rd_data_reg[9] ,\n \\not_strict_mode.app_rd_data_reg[17] ,\n \\not_strict_mode.app_rd_data_reg[1] ,\n \\not_strict_mode.app_rd_data_reg[24] ,\n \\not_strict_mode.app_rd_data_reg[8] ,\n \\not_strict_mode.app_rd_data_reg[16] ,\n \\not_strict_mode.app_rd_data_reg[0] ,\n \\read_fifo.tail_r_reg[0] ,\n \\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,\n \\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,\n \\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,\n \\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,\n \\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,\n \\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,\n \\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,\n \\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,\n \\not_strict_mode.app_rd_data_reg[255]_0 ,\n of_ctl_full_v,\n pd_out,\n pi_phase_locked_all_r1_reg,\n \\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ,\n \\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ,\n \\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ,\n \\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ,\n \\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ,\n \\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ,\n \\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ,\n \\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ,\n wr_en,\n wr_en_5,\n wr_en_6,\n fine_delay_mod,\n \\not_strict_mode.app_rd_data_reg[31]_0 ,\n \\not_strict_mode.app_rd_data_reg[31]_1 ,\n \\my_empty_reg[7]_0 ,\n \\not_strict_mode.app_rd_data_reg[23]_0 ,\n \\not_strict_mode.app_rd_data_reg[23]_1 ,\n \\my_empty_reg[7]_1 ,\n \\not_strict_mode.app_rd_data_reg[15]_0 ,\n \\not_strict_mode.app_rd_data_reg[15]_1 ,\n \\my_empty_reg[7]_2 ,\n \\not_strict_mode.app_rd_data_reg[7]_0 ,\n \\not_strict_mode.app_rd_data_reg[7]_1 ,\n \\my_empty_reg[7]_3 ,\n ofs_rdy_r_reg,\n ofs_rdy_r_reg_0,\n \\po_rdval_cnt_reg[8] ,\n \\pi_rdval_cnt_reg[5] ,\n \\wr_ptr_timing_reg[2] ,\n \\wr_ptr_timing_reg[2]_0 ,\n \\wr_ptr_timing_reg[2]_1 ,\n \\po_rdval_cnt_reg[8]_0 ,\n phy_if_empty_r_reg,\n p_0_out,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,\n \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,\n \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,\n \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,\n \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,\n ddr_ck_out,\n ddr3_dq,\n ddr3_dqs_p,\n ddr3_dqs_n,\n mux_reset_n,\n idle,\n mmcm_ps_clk,\n rst_sync_r1,\n CLK,\n mux_cmd_wren,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[2] ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 ,\n fine_delay_sel_reg,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[2]_1 ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_1 ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_2 ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_3 ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_4 ,\n init_calib_complete_reg_rep__6,\n D5,\n D6,\n D2,\n D3,\n \\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ,\n \\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ,\n D7,\n D8,\n D9,\n D0,\n D1,\n \\calib_sel_reg[0] ,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n \\calib_sel_reg[0]_0 ,\n \\calib_sel_reg[0]_1 ,\n freq_refclk,\n mem_refclk,\n \\calib_sel_reg[0]_2 ,\n sync_pulse,\n \\calib_sel_reg[1] ,\n \\gen_byte_sel_div1.calib_in_common_reg_0 ,\n \\calib_sel_reg[1]_0 ,\n \\calib_sel_reg[1]_1 ,\n \\calib_sel_reg[1]_2 ,\n \\calib_sel_reg[1]_3 ,\n \\gen_byte_sel_div1.calib_in_common_reg_1 ,\n \\calib_sel_reg[1]_4 ,\n \\calib_sel_reg[1]_5 ,\n \\calib_sel_reg[1]_6 ,\n pll_locked,\n phy_read_calib,\n in0,\n phy_write_calib,\n \\gen_byte_sel_div1.calib_in_common_reg_2 ,\n \\calib_sel_reg[0]_3 ,\n pi_en_stg2_f_reg,\n pi_stg2_f_incdec_reg,\n \\gen_byte_sel_div1.calib_in_common_reg_3 ,\n COUNTERLOADVAL,\n \\gen_byte_sel_div1.calib_in_common_reg_4 ,\n ck_po_stg2_f_en_reg,\n ck_po_stg2_f_indec_reg,\n delay_done_r4_reg,\n \\write_buffer.wr_buf_out_data_reg[255] ,\n \\write_buffer.wr_buf_out_data_reg[254] ,\n \\write_buffer.wr_buf_out_data_reg[253] ,\n \\write_buffer.wr_buf_out_data_reg[252] ,\n \\write_buffer.wr_buf_out_data_reg[251] ,\n \\write_buffer.wr_buf_out_data_reg[250] ,\n \\write_buffer.wr_buf_out_data_reg[249] ,\n \\write_buffer.wr_buf_out_data_reg[248] ,\n \\gen_byte_sel_div1.calib_in_common_reg_5 ,\n idelay_inc,\n LD0,\n CLKB0,\n phy_if_reset,\n \\gen_byte_sel_div1.calib_in_common_reg_6 ,\n \\calib_sel_reg[0]_4 ,\n pi_en_stg2_f_reg_0,\n pi_stg2_f_incdec_reg_0,\n \\gen_byte_sel_div1.calib_in_common_reg_7 ,\n \\calib_zero_inputs_reg[0] ,\n \\gen_byte_sel_div1.calib_in_common_reg_8 ,\n ck_po_stg2_f_en_reg_0,\n ck_po_stg2_f_indec_reg_0,\n delay_done_r4_reg_0,\n \\write_buffer.wr_buf_out_data_reg[247] ,\n \\write_buffer.wr_buf_out_data_reg[246] ,\n \\write_buffer.wr_buf_out_data_reg[245] ,\n \\write_buffer.wr_buf_out_data_reg[244] ,\n \\write_buffer.wr_buf_out_data_reg[243] ,\n \\write_buffer.wr_buf_out_data_reg[242] ,\n \\write_buffer.wr_buf_out_data_reg[241] ,\n \\write_buffer.wr_buf_out_data_reg[240] ,\n \\gen_byte_sel_div1.calib_in_common_reg_9 ,\n LD0_3,\n CLKB0_7,\n \\gen_byte_sel_div1.calib_in_common_reg_10 ,\n \\calib_sel_reg[1]_7 ,\n pi_en_stg2_f_reg_1,\n pi_stg2_f_incdec_reg_1,\n \\gen_byte_sel_div1.calib_in_common_reg_11 ,\n \\calib_zero_inputs_reg[0]_0 ,\n \\gen_byte_sel_div1.calib_in_common_reg_12 ,\n ck_po_stg2_f_en_reg_1,\n ck_po_stg2_f_indec_reg_1,\n delay_done_r4_reg_1,\n \\write_buffer.wr_buf_out_data_reg[239] ,\n \\write_buffer.wr_buf_out_data_reg[238] ,\n \\write_buffer.wr_buf_out_data_reg[237] ,\n \\write_buffer.wr_buf_out_data_reg[236] ,\n \\write_buffer.wr_buf_out_data_reg[235] ,\n \\write_buffer.wr_buf_out_data_reg[234] ,\n \\write_buffer.wr_buf_out_data_reg[233] ,\n \\write_buffer.wr_buf_out_data_reg[232] ,\n \\gen_byte_sel_div1.calib_in_common_reg_13 ,\n LD0_4,\n CLKB0_8,\n \\gen_byte_sel_div1.calib_in_common_reg_14 ,\n \\calib_sel_reg[0]_5 ,\n pi_en_stg2_f_reg_2,\n pi_stg2_f_incdec_reg_2,\n \\gen_byte_sel_div1.calib_in_common_reg_15 ,\n \\calib_zero_inputs_reg[0]_1 ,\n \\gen_byte_sel_div1.calib_in_common_reg_16 ,\n ck_po_stg2_f_en_reg_2,\n ck_po_stg2_f_indec_reg_2,\n delay_done_r4_reg_2,\n \\write_buffer.wr_buf_out_data_reg[231] ,\n \\write_buffer.wr_buf_out_data_reg[230] ,\n \\write_buffer.wr_buf_out_data_reg[229] ,\n \\write_buffer.wr_buf_out_data_reg[228] ,\n \\write_buffer.wr_buf_out_data_reg[227] ,\n \\write_buffer.wr_buf_out_data_reg[226] ,\n \\write_buffer.wr_buf_out_data_reg[225] ,\n \\write_buffer.wr_buf_out_data_reg[224] ,\n \\gen_byte_sel_div1.calib_in_common_reg_17 ,\n LD0_5,\n CLKB0_9,\n RST0,\n rstdiv0_sync_r1_reg_rep__9,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[2]_2 ,\n mem_out,\n \\rd_ptr_reg[3] ,\n mux_wrdata_en,\n \\rd_ptr_reg[3]_0 ,\n \\read_fifo.fifo_out_data_r_reg[6] ,\n ram_init_done_r,\n \\genblk9[6].fine_delay_incdec_pb_reg[6] ,\n \\genblk9[5].fine_delay_incdec_pb_reg[5] ,\n \\genblk9[7].fine_delay_incdec_pb_reg[7] ,\n \\genblk9[4].fine_delay_incdec_pb_reg[4] ,\n \\genblk9[3].fine_delay_incdec_pb_reg[3] ,\n \\genblk9[4].fine_delay_incdec_pb_reg[4]_0 ,\n init_calib_complete_reg_rep__5,\n mc_cas_n,\n mc_address,\n init_calib_complete_reg_rep,\n Q,\n prbs_rdlvl_start_reg,\n out,\n sys_rst,\n \\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ,\n mmcm_locked,\n \\byte_r_reg[0]_0 ,\n \\byte_r_reg[1] ,\n tail_r,\n \\rd_mux_sel_r_reg[1] ,\n \\read_fifo.fifo_out_data_r_reg[6]_0 ,\n DOC,\n DOB,\n DOA,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ,\n \\genblk9[0].fine_delay_incdec_pb_reg[0] ,\n \\genblk9[1].fine_delay_incdec_pb_reg[1] ,\n \\genblk9[2].fine_delay_incdec_pb_reg[2] ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[1] ,\n A,\n SR,\n D,\n \\cmd_pipe_plus.mc_data_offset_1_reg[5] ,\n mux_wrdata,\n mux_wrdata_mask,\n E,\n \\fine_delay_mod_reg[23]_0 ,\n \\gen_byte_sel_div1.calib_in_common_reg_18 ,\n \\calib_sel_reg[0]_6 ,\n \\gen_byte_sel_div1.calib_in_common_reg_19 ,\n \\calib_sel_reg[1]_8 ,\n \\gen_byte_sel_div1.calib_in_common_reg_20 ,\n \\calib_sel_reg[0]_7 ,\n \\calib_sel_reg[3] ,\n \\po_stg2_wrcal_cnt_reg[1] ,\n D_po_coarse_enable110_out,\n D_po_counter_read_en122_out,\n D_po_fine_enable107_out,\n D_po_fine_inc113_out,\n D_po_sel_fine_oclk_delay125_out,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ,\n D4,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ,\n phy_dout,\n init_calib_complete_reg_rep__6_0);\n output ddr3_reset_n;\n output ddr3_cas_n;\n output ddr3_ras_n;\n output ddr3_we_n;\n output [14:0]ddr3_addr;\n output [2:0]ddr3_ba;\n output [0:0]ddr3_cs_n;\n output [0:0]ddr3_odt;\n output [0:0]ddr3_cke;\n output [3:0]ddr3_dm;\n output fine_delay_sel_r;\n output \\fine_delay_mod_reg[26]_0 ;\n output \\rd_ptr_timing_reg[2] ;\n output \\rd_ptr_timing_reg[2]_0 ;\n output \\rd_ptr_timing_reg[2]_1 ;\n output \\rd_ptr_timing_reg[2]_2 ;\n output \\rd_ptr_timing_reg[2]_3 ;\n output \\rd_ptr_timing_reg[2]_4 ;\n output \\rd_ptr_timing_reg[2]_5 ;\n output \\rd_ptr_timing_reg[2]_6 ;\n output \\rd_ptr_timing_reg[2]_7 ;\n output \\rd_ptr_timing_reg[2]_8 ;\n output \\rd_ptr_timing_reg[2]_9 ;\n output \\rd_ptr_timing_reg[2]_10 ;\n output [3:0]\\pi_dqs_found_lanes_r1_reg[3] ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[252] ;\n output idelay_ld_rst;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[244] ;\n output idelay_ld_rst_0;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[236] ;\n output idelay_ld_rst_1;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[228] ;\n output idelay_ld_rst_2;\n output \\calib_seq_reg[0] ;\n output \\my_empty_reg[1] ;\n output \\my_empty_reg[1]_0 ;\n output phy_mc_ctl_full;\n output \\my_empty_reg[1]_1 ;\n output \\my_empty_reg[1]_2 ;\n output \\my_empty_reg[1]_3 ;\n output \\my_empty_reg[1]_4 ;\n output \\my_empty_reg[1]_5 ;\n output rd_buf_we;\n output \\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n output [31:0]\\my_empty_reg[7] ;\n output \\my_empty_reg[1]_6 ;\n output phy_rddata_en;\n output mux_rd_valid_r_reg;\n output rst_sync_r1_reg;\n output \\byte_r_reg[0] ;\n output [5:0]\\po_counter_read_val_r_reg[5] ;\n output [63:0]\\data_bytes_r_reg[63] ;\n output \\not_strict_mode.app_rd_data_reg[255] ;\n output \\not_strict_mode.app_rd_data_reg[239] ;\n output \\not_strict_mode.app_rd_data_reg[247] ;\n output \\not_strict_mode.app_rd_data_reg[231] ;\n output \\not_strict_mode.app_rd_data_reg[254] ;\n output \\not_strict_mode.app_rd_data_reg[238] ;\n output \\not_strict_mode.app_rd_data_reg[246] ;\n output \\not_strict_mode.app_rd_data_reg[230] ;\n output \\not_strict_mode.app_rd_data_reg[253] ;\n output \\not_strict_mode.app_rd_data_reg[237] ;\n output \\not_strict_mode.app_rd_data_reg[245] ;\n output \\not_strict_mode.app_rd_data_reg[229] ;\n output \\not_strict_mode.app_rd_data_reg[252]_0 ;\n output \\not_strict_mode.app_rd_data_reg[236]_0 ;\n output \\not_strict_mode.app_rd_data_reg[244]_0 ;\n output \\not_strict_mode.app_rd_data_reg[228]_0 ;\n output \\not_strict_mode.app_rd_data_reg[251] ;\n output \\not_strict_mode.app_rd_data_reg[235] ;\n output \\not_strict_mode.app_rd_data_reg[243] ;\n output \\not_strict_mode.app_rd_data_reg[227] ;\n output \\not_strict_mode.app_rd_data_reg[250] ;\n output \\not_strict_mode.app_rd_data_reg[234] ;\n output \\not_strict_mode.app_rd_data_reg[242] ;\n output \\not_strict_mode.app_rd_data_reg[226] ;\n output \\not_strict_mode.app_rd_data_reg[249] ;\n output \\not_strict_mode.app_rd_data_reg[233] ;\n output \\not_strict_mode.app_rd_data_reg[241] ;\n output \\not_strict_mode.app_rd_data_reg[225] ;\n output \\not_strict_mode.app_rd_data_reg[248] ;\n output \\not_strict_mode.app_rd_data_reg[232] ;\n output \\not_strict_mode.app_rd_data_reg[240] ;\n output \\not_strict_mode.app_rd_data_reg[224] ;\n output \\not_strict_mode.app_rd_data_reg[223] ;\n output \\not_strict_mode.app_rd_data_reg[207] ;\n output \\not_strict_mode.app_rd_data_reg[215] ;\n output \\not_strict_mode.app_rd_data_reg[199] ;\n output \\not_strict_mode.app_rd_data_reg[222] ;\n output \\not_strict_mode.app_rd_data_reg[206] ;\n output \\not_strict_mode.app_rd_data_reg[214] ;\n output \\not_strict_mode.app_rd_data_reg[198] ;\n output \\not_strict_mode.app_rd_data_reg[221] ;\n output \\not_strict_mode.app_rd_data_reg[205] ;\n output \\not_strict_mode.app_rd_data_reg[213] ;\n output \\not_strict_mode.app_rd_data_reg[197] ;\n output \\not_strict_mode.app_rd_data_reg[220] ;\n output \\not_strict_mode.app_rd_data_reg[204] ;\n output \\not_strict_mode.app_rd_data_reg[212] ;\n output \\not_strict_mode.app_rd_data_reg[196] ;\n output \\not_strict_mode.app_rd_data_reg[219] ;\n output \\not_strict_mode.app_rd_data_reg[203] ;\n output \\not_strict_mode.app_rd_data_reg[211] ;\n output \\not_strict_mode.app_rd_data_reg[195] ;\n output \\not_strict_mode.app_rd_data_reg[218] ;\n output \\not_strict_mode.app_rd_data_reg[202] ;\n output \\not_strict_mode.app_rd_data_reg[210] ;\n output \\not_strict_mode.app_rd_data_reg[194] ;\n output \\not_strict_mode.app_rd_data_reg[217] ;\n output \\not_strict_mode.app_rd_data_reg[201] ;\n output \\not_strict_mode.app_rd_data_reg[209] ;\n output \\not_strict_mode.app_rd_data_reg[193] ;\n output \\not_strict_mode.app_rd_data_reg[216] ;\n output \\not_strict_mode.app_rd_data_reg[200] ;\n output \\not_strict_mode.app_rd_data_reg[208] ;\n output \\not_strict_mode.app_rd_data_reg[192] ;\n output \\not_strict_mode.app_rd_data_reg[191] ;\n output \\not_strict_mode.app_rd_data_reg[175] ;\n output \\not_strict_mode.app_rd_data_reg[183] ;\n output \\not_strict_mode.app_rd_data_reg[167] ;\n output \\not_strict_mode.app_rd_data_reg[190] ;\n output \\not_strict_mode.app_rd_data_reg[174] ;\n output \\not_strict_mode.app_rd_data_reg[182] ;\n output \\not_strict_mode.app_rd_data_reg[166] ;\n output \\not_strict_mode.app_rd_data_reg[189] ;\n output \\not_strict_mode.app_rd_data_reg[173] ;\n output \\not_strict_mode.app_rd_data_reg[181] ;\n output \\not_strict_mode.app_rd_data_reg[165] ;\n output \\not_strict_mode.app_rd_data_reg[188] ;\n output \\not_strict_mode.app_rd_data_reg[172] ;\n output \\not_strict_mode.app_rd_data_reg[180] ;\n output \\not_strict_mode.app_rd_data_reg[164] ;\n output \\not_strict_mode.app_rd_data_reg[187] ;\n output \\not_strict_mode.app_rd_data_reg[171] ;\n output \\not_strict_mode.app_rd_data_reg[179] ;\n output \\not_strict_mode.app_rd_data_reg[163] ;\n output \\not_strict_mode.app_rd_data_reg[186] ;\n output \\not_strict_mode.app_rd_data_reg[170] ;\n output \\not_strict_mode.app_rd_data_reg[178] ;\n output \\not_strict_mode.app_rd_data_reg[162] ;\n output \\not_strict_mode.app_rd_data_reg[185] ;\n output \\not_strict_mode.app_rd_data_reg[169] ;\n output \\not_strict_mode.app_rd_data_reg[177] ;\n output \\not_strict_mode.app_rd_data_reg[161] ;\n output \\not_strict_mode.app_rd_data_reg[184] ;\n output \\not_strict_mode.app_rd_data_reg[168] ;\n output \\not_strict_mode.app_rd_data_reg[176] ;\n output \\not_strict_mode.app_rd_data_reg[160] ;\n output \\not_strict_mode.app_rd_data_reg[159] ;\n output \\not_strict_mode.app_rd_data_reg[143] ;\n output \\not_strict_mode.app_rd_data_reg[151] ;\n output \\not_strict_mode.app_rd_data_reg[135] ;\n output \\not_strict_mode.app_rd_data_reg[158] ;\n output \\not_strict_mode.app_rd_data_reg[142] ;\n output \\not_strict_mode.app_rd_data_reg[150] ;\n output \\not_strict_mode.app_rd_data_reg[134] ;\n output \\not_strict_mode.app_rd_data_reg[157] ;\n output \\not_strict_mode.app_rd_data_reg[141] ;\n output \\not_strict_mode.app_rd_data_reg[149] ;\n output \\not_strict_mode.app_rd_data_reg[133] ;\n output \\not_strict_mode.app_rd_data_reg[156] ;\n output \\not_strict_mode.app_rd_data_reg[140] ;\n output \\not_strict_mode.app_rd_data_reg[148] ;\n output \\not_strict_mode.app_rd_data_reg[132] ;\n output \\not_strict_mode.app_rd_data_reg[155] ;\n output \\not_strict_mode.app_rd_data_reg[139] ;\n output \\not_strict_mode.app_rd_data_reg[147] ;\n output \\not_strict_mode.app_rd_data_reg[131] ;\n output \\not_strict_mode.app_rd_data_reg[154] ;\n output \\not_strict_mode.app_rd_data_reg[138] ;\n output \\not_strict_mode.app_rd_data_reg[146] ;\n output \\not_strict_mode.app_rd_data_reg[130] ;\n output \\not_strict_mode.app_rd_data_reg[153] ;\n output \\not_strict_mode.app_rd_data_reg[137] ;\n output \\not_strict_mode.app_rd_data_reg[145] ;\n output \\not_strict_mode.app_rd_data_reg[129] ;\n output \\not_strict_mode.app_rd_data_reg[152] ;\n output \\not_strict_mode.app_rd_data_reg[136] ;\n output \\not_strict_mode.app_rd_data_reg[144] ;\n output \\not_strict_mode.app_rd_data_reg[128] ;\n output \\not_strict_mode.app_rd_data_reg[127] ;\n output \\not_strict_mode.app_rd_data_reg[111] ;\n output \\not_strict_mode.app_rd_data_reg[119] ;\n output \\not_strict_mode.app_rd_data_reg[103] ;\n output \\not_strict_mode.app_rd_data_reg[126] ;\n output \\not_strict_mode.app_rd_data_reg[110] ;\n output \\not_strict_mode.app_rd_data_reg[118] ;\n output \\not_strict_mode.app_rd_data_reg[102] ;\n output \\not_strict_mode.app_rd_data_reg[125] ;\n output \\not_strict_mode.app_rd_data_reg[109] ;\n output \\not_strict_mode.app_rd_data_reg[117] ;\n output \\not_strict_mode.app_rd_data_reg[101] ;\n output \\not_strict_mode.app_rd_data_reg[124] ;\n output \\not_strict_mode.app_rd_data_reg[108] ;\n output \\not_strict_mode.app_rd_data_reg[116] ;\n output \\not_strict_mode.app_rd_data_reg[100] ;\n output \\not_strict_mode.app_rd_data_reg[123] ;\n output \\not_strict_mode.app_rd_data_reg[107] ;\n output \\not_strict_mode.app_rd_data_reg[115] ;\n output \\not_strict_mode.app_rd_data_reg[99] ;\n output \\not_strict_mode.app_rd_data_reg[122] ;\n output \\not_strict_mode.app_rd_data_reg[106] ;\n output \\not_strict_mode.app_rd_data_reg[114] ;\n output \\not_strict_mode.app_rd_data_reg[98] ;\n output \\not_strict_mode.app_rd_data_reg[121] ;\n output \\not_strict_mode.app_rd_data_reg[105] ;\n output \\not_strict_mode.app_rd_data_reg[113] ;\n output \\not_strict_mode.app_rd_data_reg[97] ;\n output \\not_strict_mode.app_rd_data_reg[120] ;\n output \\not_strict_mode.app_rd_data_reg[104] ;\n output \\not_strict_mode.app_rd_data_reg[112] ;\n output \\not_strict_mode.app_rd_data_reg[96] ;\n output \\not_strict_mode.app_rd_data_reg[95] ;\n output \\not_strict_mode.app_rd_data_reg[79] ;\n output \\not_strict_mode.app_rd_data_reg[87] ;\n output \\not_strict_mode.app_rd_data_reg[71] ;\n output \\not_strict_mode.app_rd_data_reg[94] ;\n output \\not_strict_mode.app_rd_data_reg[78] ;\n output \\not_strict_mode.app_rd_data_reg[86] ;\n output \\not_strict_mode.app_rd_data_reg[70] ;\n output \\not_strict_mode.app_rd_data_reg[93] ;\n output \\not_strict_mode.app_rd_data_reg[77] ;\n output \\not_strict_mode.app_rd_data_reg[85] ;\n output \\not_strict_mode.app_rd_data_reg[69] ;\n output \\not_strict_mode.app_rd_data_reg[92] ;\n output \\not_strict_mode.app_rd_data_reg[76] ;\n output \\not_strict_mode.app_rd_data_reg[84] ;\n output \\not_strict_mode.app_rd_data_reg[68] ;\n output \\not_strict_mode.app_rd_data_reg[91] ;\n output \\not_strict_mode.app_rd_data_reg[75] ;\n output \\not_strict_mode.app_rd_data_reg[83] ;\n output \\not_strict_mode.app_rd_data_reg[67] ;\n output \\not_strict_mode.app_rd_data_reg[90] ;\n output \\not_strict_mode.app_rd_data_reg[74] ;\n output \\not_strict_mode.app_rd_data_reg[82] ;\n output \\not_strict_mode.app_rd_data_reg[66] ;\n output \\not_strict_mode.app_rd_data_reg[89] ;\n output \\not_strict_mode.app_rd_data_reg[73] ;\n output \\not_strict_mode.app_rd_data_reg[81] ;\n output \\not_strict_mode.app_rd_data_reg[65] ;\n output \\not_strict_mode.app_rd_data_reg[88] ;\n output \\not_strict_mode.app_rd_data_reg[72] ;\n output \\not_strict_mode.app_rd_data_reg[80] ;\n output \\not_strict_mode.app_rd_data_reg[64] ;\n output \\not_strict_mode.app_rd_data_reg[63] ;\n output \\not_strict_mode.app_rd_data_reg[47] ;\n output \\not_strict_mode.app_rd_data_reg[55] ;\n output \\not_strict_mode.app_rd_data_reg[39] ;\n output \\not_strict_mode.app_rd_data_reg[62] ;\n output \\not_strict_mode.app_rd_data_reg[46] ;\n output \\not_strict_mode.app_rd_data_reg[54] ;\n output \\not_strict_mode.app_rd_data_reg[38] ;\n output \\not_strict_mode.app_rd_data_reg[61] ;\n output \\not_strict_mode.app_rd_data_reg[45] ;\n output \\not_strict_mode.app_rd_data_reg[53] ;\n output \\not_strict_mode.app_rd_data_reg[37] ;\n output \\not_strict_mode.app_rd_data_reg[60] ;\n output \\not_strict_mode.app_rd_data_reg[44] ;\n output \\not_strict_mode.app_rd_data_reg[52] ;\n output \\not_strict_mode.app_rd_data_reg[36] ;\n output \\not_strict_mode.app_rd_data_reg[59] ;\n output \\not_strict_mode.app_rd_data_reg[43] ;\n output \\not_strict_mode.app_rd_data_reg[51] ;\n output \\not_strict_mode.app_rd_data_reg[35] ;\n output \\not_strict_mode.app_rd_data_reg[58] ;\n output \\not_strict_mode.app_rd_data_reg[42] ;\n output \\not_strict_mode.app_rd_data_reg[50] ;\n output \\not_strict_mode.app_rd_data_reg[34] ;\n output \\not_strict_mode.app_rd_data_reg[57] ;\n output \\not_strict_mode.app_rd_data_reg[41] ;\n output \\not_strict_mode.app_rd_data_reg[49] ;\n output \\not_strict_mode.app_rd_data_reg[33] ;\n output \\not_strict_mode.app_rd_data_reg[56] ;\n output \\not_strict_mode.app_rd_data_reg[40] ;\n output \\not_strict_mode.app_rd_data_reg[48] ;\n output \\not_strict_mode.app_rd_data_reg[32] ;\n output \\not_strict_mode.app_rd_data_reg[31] ;\n output \\not_strict_mode.app_rd_data_reg[15] ;\n output \\not_strict_mode.app_rd_data_reg[23] ;\n output \\not_strict_mode.app_rd_data_reg[7] ;\n output \\not_strict_mode.app_rd_data_reg[30] ;\n output \\not_strict_mode.app_rd_data_reg[14] ;\n output \\not_strict_mode.app_rd_data_reg[22] ;\n output \\not_strict_mode.app_rd_data_reg[6] ;\n output \\not_strict_mode.app_rd_data_reg[29] ;\n output \\not_strict_mode.app_rd_data_reg[13] ;\n output \\not_strict_mode.app_rd_data_reg[21] ;\n output \\not_strict_mode.app_rd_data_reg[5] ;\n output \\not_strict_mode.app_rd_data_reg[28] ;\n output \\not_strict_mode.app_rd_data_reg[12] ;\n output \\not_strict_mode.app_rd_data_reg[20] ;\n output \\not_strict_mode.app_rd_data_reg[4] ;\n output \\not_strict_mode.app_rd_data_reg[27] ;\n output \\not_strict_mode.app_rd_data_reg[11] ;\n output \\not_strict_mode.app_rd_data_reg[19] ;\n output \\not_strict_mode.app_rd_data_reg[3] ;\n output \\not_strict_mode.app_rd_data_reg[26] ;\n output \\not_strict_mode.app_rd_data_reg[10] ;\n output \\not_strict_mode.app_rd_data_reg[18] ;\n output \\not_strict_mode.app_rd_data_reg[2] ;\n output \\not_strict_mode.app_rd_data_reg[25] ;\n output \\not_strict_mode.app_rd_data_reg[9] ;\n output \\not_strict_mode.app_rd_data_reg[17] ;\n output \\not_strict_mode.app_rd_data_reg[1] ;\n output \\not_strict_mode.app_rd_data_reg[24] ;\n output \\not_strict_mode.app_rd_data_reg[8] ;\n output \\not_strict_mode.app_rd_data_reg[16] ;\n output \\not_strict_mode.app_rd_data_reg[0] ;\n output \\read_fifo.tail_r_reg[0] ;\n output \\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n output \\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n output \\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n output \\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n output \\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n output \\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n output \\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n output \\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n output [255:0]\\not_strict_mode.app_rd_data_reg[255]_0 ;\n output [0:0]of_ctl_full_v;\n output pd_out;\n output pi_phase_locked_all_r1_reg;\n output \\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ;\n output \\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ;\n output \\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ;\n output \\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ;\n output \\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ;\n output \\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ;\n output \\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ;\n output \\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ;\n output wr_en;\n output wr_en_5;\n output wr_en_6;\n output [8:0]fine_delay_mod;\n output [0:0]\\not_strict_mode.app_rd_data_reg[31]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[31]_1 ;\n output [63:0]\\my_empty_reg[7]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[23]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[23]_1 ;\n output [63:0]\\my_empty_reg[7]_1 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[15]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[15]_1 ;\n output [63:0]\\my_empty_reg[7]_2 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[7]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[7]_1 ;\n output [63:0]\\my_empty_reg[7]_3 ;\n output ofs_rdy_r_reg;\n output ofs_rdy_r_reg_0;\n output [4:0]\\po_rdval_cnt_reg[8] ;\n output [5:0]\\pi_rdval_cnt_reg[5] ;\n output [3:0]\\wr_ptr_timing_reg[2] ;\n output [3:0]\\wr_ptr_timing_reg[2]_0 ;\n output [3:0]\\wr_ptr_timing_reg[2]_1 ;\n output [4:0]\\po_rdval_cnt_reg[8]_0 ;\n output phy_if_empty_r_reg;\n output p_0_out;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n output \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n output \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n output \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n output \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n output [1:0]ddr_ck_out;\n inout [31:0]ddr3_dq;\n inout [3:0]ddr3_dqs_p;\n inout [3:0]ddr3_dqs_n;\n input mux_reset_n;\n input idle;\n input mmcm_ps_clk;\n input rst_sync_r1;\n input CLK;\n input mux_cmd_wren;\n input \\gen_byte_sel_div1.byte_sel_cnt_reg[2] ;\n input \\gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 ;\n input fine_delay_sel_reg;\n input \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ;\n input \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ;\n input \\gen_byte_sel_div1.byte_sel_cnt_reg[2]_1 ;\n input \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_1 ;\n input \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_2 ;\n input \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_3 ;\n input \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_4 ;\n input [3:0]init_calib_complete_reg_rep__6;\n input [3:0]D5;\n input [3:0]D6;\n input [2:0]D2;\n input [2:0]D3;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ;\n input [7:0]\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ;\n input [7:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ;\n input [3:0]D7;\n input [3:0]D8;\n input [3:0]D9;\n input [2:0]D0;\n input [2:0]D1;\n input \\calib_sel_reg[0] ;\n input \\gen_byte_sel_div1.calib_in_common_reg ;\n input \\calib_sel_reg[0]_0 ;\n input \\calib_sel_reg[0]_1 ;\n input freq_refclk;\n input mem_refclk;\n input \\calib_sel_reg[0]_2 ;\n input sync_pulse;\n input \\calib_sel_reg[1] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n input \\calib_sel_reg[1]_0 ;\n input \\calib_sel_reg[1]_1 ;\n input \\calib_sel_reg[1]_2 ;\n input \\calib_sel_reg[1]_3 ;\n input \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n input \\calib_sel_reg[1]_4 ;\n input \\calib_sel_reg[1]_5 ;\n input \\calib_sel_reg[1]_6 ;\n input pll_locked;\n input phy_read_calib;\n input in0;\n input phy_write_calib;\n input \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n input \\calib_sel_reg[0]_3 ;\n input pi_en_stg2_f_reg;\n input pi_stg2_f_incdec_reg;\n input \\gen_byte_sel_div1.calib_in_common_reg_3 ;\n input [5:0]COUNTERLOADVAL;\n input \\gen_byte_sel_div1.calib_in_common_reg_4 ;\n input ck_po_stg2_f_en_reg;\n input ck_po_stg2_f_indec_reg;\n input delay_done_r4_reg;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[255] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[254] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[253] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[252] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[251] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[250] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[249] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[248] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_5 ;\n input idelay_inc;\n input LD0;\n input CLKB0;\n input phy_if_reset;\n input \\gen_byte_sel_div1.calib_in_common_reg_6 ;\n input \\calib_sel_reg[0]_4 ;\n input pi_en_stg2_f_reg_0;\n input pi_stg2_f_incdec_reg_0;\n input \\gen_byte_sel_div1.calib_in_common_reg_7 ;\n input [5:0]\\calib_zero_inputs_reg[0] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_8 ;\n input ck_po_stg2_f_en_reg_0;\n input ck_po_stg2_f_indec_reg_0;\n input delay_done_r4_reg_0;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[247] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[246] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[245] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[244] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[243] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[242] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[241] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[240] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_9 ;\n input LD0_3;\n input CLKB0_7;\n input \\gen_byte_sel_div1.calib_in_common_reg_10 ;\n input \\calib_sel_reg[1]_7 ;\n input pi_en_stg2_f_reg_1;\n input pi_stg2_f_incdec_reg_1;\n input \\gen_byte_sel_div1.calib_in_common_reg_11 ;\n input [5:0]\\calib_zero_inputs_reg[0]_0 ;\n input \\gen_byte_sel_div1.calib_in_common_reg_12 ;\n input ck_po_stg2_f_en_reg_1;\n input ck_po_stg2_f_indec_reg_1;\n input delay_done_r4_reg_1;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[239] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[238] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[237] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[236] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[235] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[234] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[233] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[232] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_13 ;\n input LD0_4;\n input CLKB0_8;\n input \\gen_byte_sel_div1.calib_in_common_reg_14 ;\n input \\calib_sel_reg[0]_5 ;\n input pi_en_stg2_f_reg_2;\n input pi_stg2_f_incdec_reg_2;\n input \\gen_byte_sel_div1.calib_in_common_reg_15 ;\n input [5:0]\\calib_zero_inputs_reg[0]_1 ;\n input \\gen_byte_sel_div1.calib_in_common_reg_16 ;\n input ck_po_stg2_f_en_reg_2;\n input ck_po_stg2_f_indec_reg_2;\n input delay_done_r4_reg_2;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[231] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[230] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[229] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[228] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[227] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[226] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[225] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[224] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_17 ;\n input LD0_5;\n input CLKB0_9;\n input RST0;\n input rstdiv0_sync_r1_reg_rep__9;\n input \\gen_byte_sel_div1.byte_sel_cnt_reg[2]_2 ;\n input [11:0]mem_out;\n input [33:0]\\rd_ptr_reg[3] ;\n input mux_wrdata_en;\n input [17:0]\\rd_ptr_reg[3]_0 ;\n input [0:0]\\read_fifo.fifo_out_data_r_reg[6] ;\n input ram_init_done_r;\n input \\genblk9[6].fine_delay_incdec_pb_reg[6] ;\n input \\genblk9[5].fine_delay_incdec_pb_reg[5] ;\n input \\genblk9[7].fine_delay_incdec_pb_reg[7] ;\n input \\genblk9[4].fine_delay_incdec_pb_reg[4] ;\n input \\genblk9[3].fine_delay_incdec_pb_reg[3] ;\n input \\genblk9[4].fine_delay_incdec_pb_reg[4]_0 ;\n input init_calib_complete_reg_rep__5;\n input [0:0]mc_cas_n;\n input [1:0]mc_address;\n input init_calib_complete_reg_rep;\n input [31:0]Q;\n input prbs_rdlvl_start_reg;\n input out;\n input sys_rst;\n input [0:0]\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ;\n input mmcm_locked;\n input \\byte_r_reg[0]_0 ;\n input \\byte_r_reg[1] ;\n input [0:0]tail_r;\n input [1:0]\\rd_mux_sel_r_reg[1] ;\n input \\read_fifo.fifo_out_data_r_reg[6]_0 ;\n input [1:0]DOC;\n input [1:0]DOB;\n input [1:0]DOA;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ;\n input \\genblk9[0].fine_delay_incdec_pb_reg[0] ;\n input \\genblk9[1].fine_delay_incdec_pb_reg[1] ;\n input \\genblk9[2].fine_delay_incdec_pb_reg[2] ;\n input [1:0]\\gen_byte_sel_div1.byte_sel_cnt_reg[1] ;\n input [1:0]A;\n input [0:0]SR;\n input [10:0]D;\n input [5:0]\\cmd_pipe_plus.mc_data_offset_1_reg[5] ;\n input [255:0]mux_wrdata;\n input [31:0]mux_wrdata_mask;\n input [0:0]E;\n input [7:0]\\fine_delay_mod_reg[23]_0 ;\n input [0:0]\\gen_byte_sel_div1.calib_in_common_reg_18 ;\n input [7:0]\\calib_sel_reg[0]_6 ;\n input [0:0]\\gen_byte_sel_div1.calib_in_common_reg_19 ;\n input [7:0]\\calib_sel_reg[1]_8 ;\n input [0:0]\\gen_byte_sel_div1.calib_in_common_reg_20 ;\n input [7:0]\\calib_sel_reg[0]_7 ;\n input [2:0]\\calib_sel_reg[3] ;\n input [1:0]\\po_stg2_wrcal_cnt_reg[1] ;\n input D_po_coarse_enable110_out;\n input D_po_counter_read_en122_out;\n input D_po_fine_enable107_out;\n input D_po_fine_inc113_out;\n input D_po_sel_fine_oclk_delay125_out;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ;\n input [3:0]D4;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ;\n input [35:0]phy_dout;\n input init_calib_complete_reg_rep__6_0;\n\n wire [1:0]A;\n wire \\A[0]__0_n_0 ;\n wire \\A[0]__4_n_0 ;\n wire \\A[1]__0_n_0 ;\n wire \\A[1]__3_n_0 ;\n wire \\A[1]__4_n_0 ;\n wire \\A[2]__1_n_0 ;\n wire \\A_n_0_[1] ;\n wire CLK;\n wire CLKB0;\n wire CLKB0_7;\n wire CLKB0_8;\n wire CLKB0_9;\n wire [5:0]COUNTERLOADVAL;\n wire [10:0]D;\n wire [2:0]D0;\n wire [2:0]D1;\n wire [2:0]D2;\n wire [2:0]D3;\n wire [3:0]D4;\n wire [3:0]D5;\n wire [3:0]D6;\n wire [3:0]D7;\n wire [3:0]D8;\n wire [3:0]D9;\n wire [1:0]DOA;\n wire [1:0]DOB;\n wire [1:0]DOC;\n wire D_po_coarse_enable110_out;\n wire D_po_counter_read_en122_out;\n wire D_po_fine_enable107_out;\n wire D_po_fine_inc113_out;\n wire D_po_sel_fine_oclk_delay125_out;\n wire [0:0]E;\n wire LD0;\n wire LD0_3;\n wire LD0_4;\n wire LD0_5;\n wire [31:0]Q;\n wire RST0;\n wire [0:0]SR;\n wire \\byte_r_reg[0] ;\n wire \\byte_r_reg[0]_0 ;\n wire \\byte_r_reg[1] ;\n wire [1:1]byte_sel_data_map;\n wire \\calib_sel_reg[0] ;\n wire \\calib_sel_reg[0]_0 ;\n wire \\calib_sel_reg[0]_1 ;\n wire \\calib_sel_reg[0]_2 ;\n wire \\calib_sel_reg[0]_3 ;\n wire \\calib_sel_reg[0]_4 ;\n wire \\calib_sel_reg[0]_5 ;\n wire [7:0]\\calib_sel_reg[0]_6 ;\n wire [7:0]\\calib_sel_reg[0]_7 ;\n wire \\calib_sel_reg[1] ;\n wire \\calib_sel_reg[1]_0 ;\n wire \\calib_sel_reg[1]_1 ;\n wire \\calib_sel_reg[1]_2 ;\n wire \\calib_sel_reg[1]_3 ;\n wire \\calib_sel_reg[1]_4 ;\n wire \\calib_sel_reg[1]_5 ;\n wire \\calib_sel_reg[1]_6 ;\n wire \\calib_sel_reg[1]_7 ;\n wire [7:0]\\calib_sel_reg[1]_8 ;\n wire [2:0]\\calib_sel_reg[3] ;\n wire \\calib_seq_reg[0] ;\n wire [5:0]\\calib_zero_inputs_reg[0] ;\n wire [5:0]\\calib_zero_inputs_reg[0]_0 ;\n wire [5:0]\\calib_zero_inputs_reg[0]_1 ;\n wire ck_po_stg2_f_en_reg;\n wire ck_po_stg2_f_en_reg_0;\n wire ck_po_stg2_f_en_reg_1;\n wire ck_po_stg2_f_en_reg_2;\n wire ck_po_stg2_f_indec_reg;\n wire ck_po_stg2_f_indec_reg_0;\n wire ck_po_stg2_f_indec_reg_1;\n wire ck_po_stg2_f_indec_reg_2;\n wire [5:0]\\cmd_pipe_plus.mc_data_offset_1_reg[5] ;\n wire [63:0]\\data_bytes_r_reg[63] ;\n wire [5:0]data_offset_1_i1;\n wire [5:0]data_offset_1_i2;\n wire [14:0]ddr3_addr;\n wire [2:0]ddr3_ba;\n wire ddr3_cas_n;\n wire [0:0]ddr3_cke;\n wire [0:0]ddr3_cs_n;\n wire [3:0]ddr3_dm;\n wire [31:0]ddr3_dq;\n wire [3:0]ddr3_dqs_n;\n wire [3:0]ddr3_dqs_p;\n wire [0:0]ddr3_odt;\n wire ddr3_ras_n;\n wire ddr3_reset_n;\n wire ddr3_we_n;\n wire [1:0]ddr_ck_out;\n wire delay_done_r4_reg;\n wire delay_done_r4_reg_0;\n wire delay_done_r4_reg_1;\n wire delay_done_r4_reg_2;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;\n wire [8:0]fine_delay_mod;\n wire [11:2]fine_delay_mod0;\n wire \\fine_delay_mod[11]_i_10_n_0 ;\n wire \\fine_delay_mod[11]_i_11_n_0 ;\n wire \\fine_delay_mod[11]_i_12_n_0 ;\n wire \\fine_delay_mod[11]_i_1_n_0 ;\n wire \\fine_delay_mod[11]_i_2_n_0 ;\n wire \\fine_delay_mod[11]_i_3_n_0 ;\n wire \\fine_delay_mod[11]_i_4_n_0 ;\n wire \\fine_delay_mod[11]_i_5_n_0 ;\n wire \\fine_delay_mod[11]_i_7_n_0 ;\n wire \\fine_delay_mod[11]_i_9_n_0 ;\n wire \\fine_delay_mod[14]_i_1_n_0 ;\n wire \\fine_delay_mod[14]_i_2_n_0 ;\n wire \\fine_delay_mod[14]_i_3_n_0 ;\n wire \\fine_delay_mod[14]_i_4_n_0 ;\n wire \\fine_delay_mod[14]_i_5_n_0 ;\n wire \\fine_delay_mod[14]_i_6_n_0 ;\n wire \\fine_delay_mod[14]_i_7_n_0 ;\n wire \\fine_delay_mod[14]_i_8_n_0 ;\n wire \\fine_delay_mod[17]_i_1_n_0 ;\n wire \\fine_delay_mod[17]_i_2_n_0 ;\n wire \\fine_delay_mod[17]_i_3_n_0 ;\n wire \\fine_delay_mod[17]_i_4_n_0 ;\n wire \\fine_delay_mod[17]_i_5_n_0 ;\n wire \\fine_delay_mod[17]_i_6_n_0 ;\n wire \\fine_delay_mod[17]_i_7_n_0 ;\n wire \\fine_delay_mod[17]_i_8_n_0 ;\n wire \\fine_delay_mod[17]_i_9_n_0 ;\n wire \\fine_delay_mod[20]_i_1_n_0 ;\n wire \\fine_delay_mod[20]_i_2_n_0 ;\n wire \\fine_delay_mod[20]_i_3_n_0 ;\n wire \\fine_delay_mod[20]_i_4_n_0 ;\n wire \\fine_delay_mod[20]_i_5_n_0 ;\n wire \\fine_delay_mod[20]_i_6_n_0 ;\n wire \\fine_delay_mod[20]_i_7_n_0 ;\n wire \\fine_delay_mod[20]_i_8_n_0 ;\n wire \\fine_delay_mod[20]_i_9_n_0 ;\n wire \\fine_delay_mod[23]_i_10_n_0 ;\n wire \\fine_delay_mod[23]_i_1_n_0 ;\n wire \\fine_delay_mod[23]_i_2_n_0 ;\n wire \\fine_delay_mod[23]_i_3_n_0 ;\n wire \\fine_delay_mod[23]_i_4_n_0 ;\n wire \\fine_delay_mod[23]_i_5_n_0 ;\n wire \\fine_delay_mod[23]_i_6_n_0 ;\n wire \\fine_delay_mod[23]_i_7_n_0 ;\n wire \\fine_delay_mod[23]_i_8_n_0 ;\n wire \\fine_delay_mod[23]_i_9_n_0 ;\n wire \\fine_delay_mod[26]_i_1_n_0 ;\n wire \\fine_delay_mod[2]_i_10_n_0 ;\n wire \\fine_delay_mod[2]_i_1_n_0 ;\n wire \\fine_delay_mod[2]_i_2_n_0 ;\n wire \\fine_delay_mod[2]_i_3_n_0 ;\n wire \\fine_delay_mod[2]_i_4_n_0 ;\n wire \\fine_delay_mod[2]_i_5_n_0 ;\n wire \\fine_delay_mod[2]_i_7_n_0 ;\n wire \\fine_delay_mod[2]_i_8_n_0 ;\n wire \\fine_delay_mod[2]_i_9_n_0 ;\n wire \\fine_delay_mod[5]_i_10_n_0 ;\n wire \\fine_delay_mod[5]_i_11_n_0 ;\n wire \\fine_delay_mod[5]_i_12_n_0 ;\n wire \\fine_delay_mod[5]_i_1_n_0 ;\n wire \\fine_delay_mod[5]_i_2_n_0 ;\n wire \\fine_delay_mod[5]_i_3_n_0 ;\n wire \\fine_delay_mod[5]_i_4_n_0 ;\n wire \\fine_delay_mod[5]_i_5_n_0 ;\n wire \\fine_delay_mod[5]_i_7_n_0 ;\n wire \\fine_delay_mod[5]_i_8_n_0 ;\n wire \\fine_delay_mod[5]_i_9_n_0 ;\n wire \\fine_delay_mod[8]_i_10_n_0 ;\n wire \\fine_delay_mod[8]_i_1_n_0 ;\n wire \\fine_delay_mod[8]_i_2_n_0 ;\n wire \\fine_delay_mod[8]_i_3_n_0 ;\n wire \\fine_delay_mod[8]_i_4_n_0 ;\n wire \\fine_delay_mod[8]_i_5_n_0 ;\n wire \\fine_delay_mod[8]_i_7_n_0 ;\n wire \\fine_delay_mod[8]_i_8_n_0 ;\n wire \\fine_delay_mod[8]_i_9_n_0 ;\n wire [7:0]\\fine_delay_mod_reg[23]_0 ;\n wire \\fine_delay_mod_reg[26]_0 ;\n wire fine_delay_sel_r;\n wire fine_delay_sel_reg;\n wire freq_refclk;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_1 ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_2 ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_3 ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_4 ;\n wire [1:0]\\gen_byte_sel_div1.byte_sel_cnt_reg[1] ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[2] ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[2]_1 ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[2]_2 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_10 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_11 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_12 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_13 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_14 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_15 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_16 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_17 ;\n wire [0:0]\\gen_byte_sel_div1.calib_in_common_reg_18 ;\n wire [0:0]\\gen_byte_sel_div1.calib_in_common_reg_19 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n wire [0:0]\\gen_byte_sel_div1.calib_in_common_reg_20 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_3 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_4 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_5 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_6 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_7 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_8 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_9 ;\n wire \\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n wire \\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n wire \\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n wire \\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;\n wire \\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n wire \\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n wire \\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n wire \\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n wire [7:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ;\n wire [7:0]\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ;\n wire \\genblk9[0].fine_delay_incdec_pb_reg[0] ;\n wire \\genblk9[1].fine_delay_incdec_pb_reg[1] ;\n wire \\genblk9[2].fine_delay_incdec_pb_reg[2] ;\n wire \\genblk9[3].fine_delay_incdec_pb_reg[3] ;\n wire \\genblk9[4].fine_delay_incdec_pb_reg[4] ;\n wire \\genblk9[4].fine_delay_incdec_pb_reg[4]_0 ;\n wire \\genblk9[5].fine_delay_incdec_pb_reg[5] ;\n wire \\genblk9[6].fine_delay_incdec_pb_reg[6] ;\n wire \\genblk9[7].fine_delay_incdec_pb_reg[7] ;\n wire idelay_inc;\n wire idelay_ld_rst;\n wire idelay_ld_rst_0;\n wire idelay_ld_rst_1;\n wire idelay_ld_rst_2;\n wire idle;\n wire in0;\n wire in_dqs_lpbk_to_iddr_0;\n wire in_dqs_lpbk_to_iddr_1;\n wire in_dqs_lpbk_to_iddr_2;\n wire in_dqs_lpbk_to_iddr_3;\n wire init_calib_complete_reg_rep;\n wire init_calib_complete_reg_rep__5;\n wire [3:0]init_calib_complete_reg_rep__6;\n wire init_calib_complete_reg_rep__6_0;\n wire [1:0]mc_address;\n wire [0:0]mc_cas_n;\n wire [38:0]mem_dq_in;\n wire [93:0]mem_dq_out;\n wire [45:0]mem_dq_ts;\n wire [3:0]mem_dqs_in;\n wire [3:0]mem_dqs_out;\n wire [3:0]mem_dqs_ts;\n wire [11:0]mem_out;\n wire mem_refclk;\n wire mmcm_locked;\n wire mmcm_ps_clk;\n wire mux_cmd_wren;\n wire mux_rd_valid_r_reg;\n wire mux_reset_n;\n wire [255:0]mux_wrdata;\n wire mux_wrdata_en;\n wire [31:0]mux_wrdata_mask;\n wire \\my_empty_reg[1] ;\n wire \\my_empty_reg[1]_0 ;\n wire \\my_empty_reg[1]_1 ;\n wire \\my_empty_reg[1]_2 ;\n wire \\my_empty_reg[1]_3 ;\n wire \\my_empty_reg[1]_4 ;\n wire \\my_empty_reg[1]_5 ;\n wire \\my_empty_reg[1]_6 ;\n wire [31:0]\\my_empty_reg[7] ;\n wire [63:0]\\my_empty_reg[7]_0 ;\n wire [63:0]\\my_empty_reg[7]_1 ;\n wire [63:0]\\my_empty_reg[7]_2 ;\n wire [63:0]\\my_empty_reg[7]_3 ;\n wire \\not_strict_mode.app_rd_data_reg[0] ;\n wire \\not_strict_mode.app_rd_data_reg[100] ;\n wire \\not_strict_mode.app_rd_data_reg[101] ;\n wire \\not_strict_mode.app_rd_data_reg[102] ;\n wire \\not_strict_mode.app_rd_data_reg[103] ;\n wire \\not_strict_mode.app_rd_data_reg[104] ;\n wire \\not_strict_mode.app_rd_data_reg[105] ;\n wire \\not_strict_mode.app_rd_data_reg[106] ;\n wire \\not_strict_mode.app_rd_data_reg[107] ;\n wire \\not_strict_mode.app_rd_data_reg[108] ;\n wire \\not_strict_mode.app_rd_data_reg[109] ;\n wire \\not_strict_mode.app_rd_data_reg[10] ;\n wire \\not_strict_mode.app_rd_data_reg[110] ;\n wire \\not_strict_mode.app_rd_data_reg[111] ;\n wire \\not_strict_mode.app_rd_data_reg[112] ;\n wire \\not_strict_mode.app_rd_data_reg[113] ;\n wire \\not_strict_mode.app_rd_data_reg[114] ;\n wire \\not_strict_mode.app_rd_data_reg[115] ;\n wire \\not_strict_mode.app_rd_data_reg[116] ;\n wire \\not_strict_mode.app_rd_data_reg[117] ;\n wire \\not_strict_mode.app_rd_data_reg[118] ;\n wire \\not_strict_mode.app_rd_data_reg[119] ;\n wire \\not_strict_mode.app_rd_data_reg[11] ;\n wire \\not_strict_mode.app_rd_data_reg[120] ;\n wire \\not_strict_mode.app_rd_data_reg[121] ;\n wire \\not_strict_mode.app_rd_data_reg[122] ;\n wire \\not_strict_mode.app_rd_data_reg[123] ;\n wire \\not_strict_mode.app_rd_data_reg[124] ;\n wire \\not_strict_mode.app_rd_data_reg[125] ;\n wire \\not_strict_mode.app_rd_data_reg[126] ;\n wire \\not_strict_mode.app_rd_data_reg[127] ;\n wire \\not_strict_mode.app_rd_data_reg[128] ;\n wire \\not_strict_mode.app_rd_data_reg[129] ;\n wire \\not_strict_mode.app_rd_data_reg[12] ;\n wire \\not_strict_mode.app_rd_data_reg[130] ;\n wire \\not_strict_mode.app_rd_data_reg[131] ;\n wire \\not_strict_mode.app_rd_data_reg[132] ;\n wire \\not_strict_mode.app_rd_data_reg[133] ;\n wire \\not_strict_mode.app_rd_data_reg[134] ;\n wire \\not_strict_mode.app_rd_data_reg[135] ;\n wire \\not_strict_mode.app_rd_data_reg[136] ;\n wire \\not_strict_mode.app_rd_data_reg[137] ;\n wire \\not_strict_mode.app_rd_data_reg[138] ;\n wire \\not_strict_mode.app_rd_data_reg[139] ;\n wire \\not_strict_mode.app_rd_data_reg[13] ;\n wire \\not_strict_mode.app_rd_data_reg[140] ;\n wire \\not_strict_mode.app_rd_data_reg[141] ;\n wire \\not_strict_mode.app_rd_data_reg[142] ;\n wire \\not_strict_mode.app_rd_data_reg[143] ;\n wire \\not_strict_mode.app_rd_data_reg[144] ;\n wire \\not_strict_mode.app_rd_data_reg[145] ;\n wire \\not_strict_mode.app_rd_data_reg[146] ;\n wire \\not_strict_mode.app_rd_data_reg[147] ;\n wire \\not_strict_mode.app_rd_data_reg[148] ;\n wire \\not_strict_mode.app_rd_data_reg[149] ;\n wire \\not_strict_mode.app_rd_data_reg[14] ;\n wire \\not_strict_mode.app_rd_data_reg[150] ;\n wire \\not_strict_mode.app_rd_data_reg[151] ;\n wire \\not_strict_mode.app_rd_data_reg[152] ;\n wire \\not_strict_mode.app_rd_data_reg[153] ;\n wire \\not_strict_mode.app_rd_data_reg[154] ;\n wire \\not_strict_mode.app_rd_data_reg[155] ;\n wire \\not_strict_mode.app_rd_data_reg[156] ;\n wire \\not_strict_mode.app_rd_data_reg[157] ;\n wire \\not_strict_mode.app_rd_data_reg[158] ;\n wire \\not_strict_mode.app_rd_data_reg[159] ;\n wire \\not_strict_mode.app_rd_data_reg[15] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[15]_0 ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[15]_1 ;\n wire \\not_strict_mode.app_rd_data_reg[160] ;\n wire \\not_strict_mode.app_rd_data_reg[161] ;\n wire \\not_strict_mode.app_rd_data_reg[162] ;\n wire \\not_strict_mode.app_rd_data_reg[163] ;\n wire \\not_strict_mode.app_rd_data_reg[164] ;\n wire \\not_strict_mode.app_rd_data_reg[165] ;\n wire \\not_strict_mode.app_rd_data_reg[166] ;\n wire \\not_strict_mode.app_rd_data_reg[167] ;\n wire \\not_strict_mode.app_rd_data_reg[168] ;\n wire \\not_strict_mode.app_rd_data_reg[169] ;\n wire \\not_strict_mode.app_rd_data_reg[16] ;\n wire \\not_strict_mode.app_rd_data_reg[170] ;\n wire \\not_strict_mode.app_rd_data_reg[171] ;\n wire \\not_strict_mode.app_rd_data_reg[172] ;\n wire \\not_strict_mode.app_rd_data_reg[173] ;\n wire \\not_strict_mode.app_rd_data_reg[174] ;\n wire \\not_strict_mode.app_rd_data_reg[175] ;\n wire \\not_strict_mode.app_rd_data_reg[176] ;\n wire \\not_strict_mode.app_rd_data_reg[177] ;\n wire \\not_strict_mode.app_rd_data_reg[178] ;\n wire \\not_strict_mode.app_rd_data_reg[179] ;\n wire \\not_strict_mode.app_rd_data_reg[17] ;\n wire \\not_strict_mode.app_rd_data_reg[180] ;\n wire \\not_strict_mode.app_rd_data_reg[181] ;\n wire \\not_strict_mode.app_rd_data_reg[182] ;\n wire \\not_strict_mode.app_rd_data_reg[183] ;\n wire \\not_strict_mode.app_rd_data_reg[184] ;\n wire \\not_strict_mode.app_rd_data_reg[185] ;\n wire \\not_strict_mode.app_rd_data_reg[186] ;\n wire \\not_strict_mode.app_rd_data_reg[187] ;\n wire \\not_strict_mode.app_rd_data_reg[188] ;\n wire \\not_strict_mode.app_rd_data_reg[189] ;\n wire \\not_strict_mode.app_rd_data_reg[18] ;\n wire \\not_strict_mode.app_rd_data_reg[190] ;\n wire \\not_strict_mode.app_rd_data_reg[191] ;\n wire \\not_strict_mode.app_rd_data_reg[192] ;\n wire \\not_strict_mode.app_rd_data_reg[193] ;\n wire \\not_strict_mode.app_rd_data_reg[194] ;\n wire \\not_strict_mode.app_rd_data_reg[195] ;\n wire \\not_strict_mode.app_rd_data_reg[196] ;\n wire \\not_strict_mode.app_rd_data_reg[197] ;\n wire \\not_strict_mode.app_rd_data_reg[198] ;\n wire \\not_strict_mode.app_rd_data_reg[199] ;\n wire \\not_strict_mode.app_rd_data_reg[19] ;\n wire \\not_strict_mode.app_rd_data_reg[1] ;\n wire \\not_strict_mode.app_rd_data_reg[200] ;\n wire \\not_strict_mode.app_rd_data_reg[201] ;\n wire \\not_strict_mode.app_rd_data_reg[202] ;\n wire \\not_strict_mode.app_rd_data_reg[203] ;\n wire \\not_strict_mode.app_rd_data_reg[204] ;\n wire \\not_strict_mode.app_rd_data_reg[205] ;\n wire \\not_strict_mode.app_rd_data_reg[206] ;\n wire \\not_strict_mode.app_rd_data_reg[207] ;\n wire \\not_strict_mode.app_rd_data_reg[208] ;\n wire \\not_strict_mode.app_rd_data_reg[209] ;\n wire \\not_strict_mode.app_rd_data_reg[20] ;\n wire \\not_strict_mode.app_rd_data_reg[210] ;\n wire \\not_strict_mode.app_rd_data_reg[211] ;\n wire \\not_strict_mode.app_rd_data_reg[212] ;\n wire \\not_strict_mode.app_rd_data_reg[213] ;\n wire \\not_strict_mode.app_rd_data_reg[214] ;\n wire \\not_strict_mode.app_rd_data_reg[215] ;\n wire \\not_strict_mode.app_rd_data_reg[216] ;\n wire \\not_strict_mode.app_rd_data_reg[217] ;\n wire \\not_strict_mode.app_rd_data_reg[218] ;\n wire \\not_strict_mode.app_rd_data_reg[219] ;\n wire \\not_strict_mode.app_rd_data_reg[21] ;\n wire \\not_strict_mode.app_rd_data_reg[220] ;\n wire \\not_strict_mode.app_rd_data_reg[221] ;\n wire \\not_strict_mode.app_rd_data_reg[222] ;\n wire \\not_strict_mode.app_rd_data_reg[223] ;\n wire \\not_strict_mode.app_rd_data_reg[224] ;\n wire \\not_strict_mode.app_rd_data_reg[225] ;\n wire \\not_strict_mode.app_rd_data_reg[226] ;\n wire \\not_strict_mode.app_rd_data_reg[227] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[228] ;\n wire \\not_strict_mode.app_rd_data_reg[228]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[229] ;\n wire \\not_strict_mode.app_rd_data_reg[22] ;\n wire \\not_strict_mode.app_rd_data_reg[230] ;\n wire \\not_strict_mode.app_rd_data_reg[231] ;\n wire \\not_strict_mode.app_rd_data_reg[232] ;\n wire \\not_strict_mode.app_rd_data_reg[233] ;\n wire \\not_strict_mode.app_rd_data_reg[234] ;\n wire \\not_strict_mode.app_rd_data_reg[235] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[236] ;\n wire \\not_strict_mode.app_rd_data_reg[236]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[237] ;\n wire \\not_strict_mode.app_rd_data_reg[238] ;\n wire \\not_strict_mode.app_rd_data_reg[239] ;\n wire \\not_strict_mode.app_rd_data_reg[23] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[23]_0 ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[23]_1 ;\n wire \\not_strict_mode.app_rd_data_reg[240] ;\n wire \\not_strict_mode.app_rd_data_reg[241] ;\n wire \\not_strict_mode.app_rd_data_reg[242] ;\n wire \\not_strict_mode.app_rd_data_reg[243] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[244] ;\n wire \\not_strict_mode.app_rd_data_reg[244]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[245] ;\n wire \\not_strict_mode.app_rd_data_reg[246] ;\n wire \\not_strict_mode.app_rd_data_reg[247] ;\n wire \\not_strict_mode.app_rd_data_reg[248] ;\n wire \\not_strict_mode.app_rd_data_reg[249] ;\n wire \\not_strict_mode.app_rd_data_reg[24] ;\n wire \\not_strict_mode.app_rd_data_reg[250] ;\n wire \\not_strict_mode.app_rd_data_reg[251] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[252] ;\n wire \\not_strict_mode.app_rd_data_reg[252]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[253] ;\n wire \\not_strict_mode.app_rd_data_reg[254] ;\n wire \\not_strict_mode.app_rd_data_reg[255] ;\n wire [255:0]\\not_strict_mode.app_rd_data_reg[255]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[25] ;\n wire \\not_strict_mode.app_rd_data_reg[26] ;\n wire \\not_strict_mode.app_rd_data_reg[27] ;\n wire \\not_strict_mode.app_rd_data_reg[28] ;\n wire \\not_strict_mode.app_rd_data_reg[29] ;\n wire \\not_strict_mode.app_rd_data_reg[2] ;\n wire \\not_strict_mode.app_rd_data_reg[30] ;\n wire \\not_strict_mode.app_rd_data_reg[31] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[31]_0 ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[31]_1 ;\n wire \\not_strict_mode.app_rd_data_reg[32] ;\n wire \\not_strict_mode.app_rd_data_reg[33] ;\n wire \\not_strict_mode.app_rd_data_reg[34] ;\n wire \\not_strict_mode.app_rd_data_reg[35] ;\n wire \\not_strict_mode.app_rd_data_reg[36] ;\n wire \\not_strict_mode.app_rd_data_reg[37] ;\n wire \\not_strict_mode.app_rd_data_reg[38] ;\n wire \\not_strict_mode.app_rd_data_reg[39] ;\n wire \\not_strict_mode.app_rd_data_reg[3] ;\n wire \\not_strict_mode.app_rd_data_reg[40] ;\n wire \\not_strict_mode.app_rd_data_reg[41] ;\n wire \\not_strict_mode.app_rd_data_reg[42] ;\n wire \\not_strict_mode.app_rd_data_reg[43] ;\n wire \\not_strict_mode.app_rd_data_reg[44] ;\n wire \\not_strict_mode.app_rd_data_reg[45] ;\n wire \\not_strict_mode.app_rd_data_reg[46] ;\n wire \\not_strict_mode.app_rd_data_reg[47] ;\n wire \\not_strict_mode.app_rd_data_reg[48] ;\n wire \\not_strict_mode.app_rd_data_reg[49] ;\n wire \\not_strict_mode.app_rd_data_reg[4] ;\n wire \\not_strict_mode.app_rd_data_reg[50] ;\n wire \\not_strict_mode.app_rd_data_reg[51] ;\n wire \\not_strict_mode.app_rd_data_reg[52] ;\n wire \\not_strict_mode.app_rd_data_reg[53] ;\n wire \\not_strict_mode.app_rd_data_reg[54] ;\n wire \\not_strict_mode.app_rd_data_reg[55] ;\n wire \\not_strict_mode.app_rd_data_reg[56] ;\n wire \\not_strict_mode.app_rd_data_reg[57] ;\n wire \\not_strict_mode.app_rd_data_reg[58] ;\n wire \\not_strict_mode.app_rd_data_reg[59] ;\n wire \\not_strict_mode.app_rd_data_reg[5] ;\n wire \\not_strict_mode.app_rd_data_reg[60] ;\n wire \\not_strict_mode.app_rd_data_reg[61] ;\n wire \\not_strict_mode.app_rd_data_reg[62] ;\n wire \\not_strict_mode.app_rd_data_reg[63] ;\n wire \\not_strict_mode.app_rd_data_reg[64] ;\n wire \\not_strict_mode.app_rd_data_reg[65] ;\n wire \\not_strict_mode.app_rd_data_reg[66] ;\n wire \\not_strict_mode.app_rd_data_reg[67] ;\n wire \\not_strict_mode.app_rd_data_reg[68] ;\n wire \\not_strict_mode.app_rd_data_reg[69] ;\n wire \\not_strict_mode.app_rd_data_reg[6] ;\n wire \\not_strict_mode.app_rd_data_reg[70] ;\n wire \\not_strict_mode.app_rd_data_reg[71] ;\n wire \\not_strict_mode.app_rd_data_reg[72] ;\n wire \\not_strict_mode.app_rd_data_reg[73] ;\n wire \\not_strict_mode.app_rd_data_reg[74] ;\n wire \\not_strict_mode.app_rd_data_reg[75] ;\n wire \\not_strict_mode.app_rd_data_reg[76] ;\n wire \\not_strict_mode.app_rd_data_reg[77] ;\n wire \\not_strict_mode.app_rd_data_reg[78] ;\n wire \\not_strict_mode.app_rd_data_reg[79] ;\n wire \\not_strict_mode.app_rd_data_reg[7] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[7]_0 ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[7]_1 ;\n wire \\not_strict_mode.app_rd_data_reg[80] ;\n wire \\not_strict_mode.app_rd_data_reg[81] ;\n wire \\not_strict_mode.app_rd_data_reg[82] ;\n wire \\not_strict_mode.app_rd_data_reg[83] ;\n wire \\not_strict_mode.app_rd_data_reg[84] ;\n wire \\not_strict_mode.app_rd_data_reg[85] ;\n wire \\not_strict_mode.app_rd_data_reg[86] ;\n wire \\not_strict_mode.app_rd_data_reg[87] ;\n wire \\not_strict_mode.app_rd_data_reg[88] ;\n wire \\not_strict_mode.app_rd_data_reg[89] ;\n wire \\not_strict_mode.app_rd_data_reg[8] ;\n wire \\not_strict_mode.app_rd_data_reg[90] ;\n wire \\not_strict_mode.app_rd_data_reg[91] ;\n wire \\not_strict_mode.app_rd_data_reg[92] ;\n wire \\not_strict_mode.app_rd_data_reg[93] ;\n wire \\not_strict_mode.app_rd_data_reg[94] ;\n wire \\not_strict_mode.app_rd_data_reg[95] ;\n wire \\not_strict_mode.app_rd_data_reg[96] ;\n wire \\not_strict_mode.app_rd_data_reg[97] ;\n wire \\not_strict_mode.app_rd_data_reg[98] ;\n wire \\not_strict_mode.app_rd_data_reg[99] ;\n wire \\not_strict_mode.app_rd_data_reg[9] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ;\n wire \\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n wire [0:0]of_ctl_full_v;\n wire ofs_rdy_r_reg;\n wire ofs_rdy_r_reg_0;\n wire out;\n wire p_0_out;\n wire pd_out;\n wire [2:0]pd_out_pre;\n wire [24:0]phy_ctl_wd_i1;\n wire [24:0]phy_ctl_wd_i2;\n wire phy_ctl_wr_i1;\n wire phy_ctl_wr_i2;\n wire [35:0]phy_dout;\n wire phy_if_empty_r_reg;\n wire phy_if_reset;\n wire phy_mc_ctl_full;\n wire phy_rddata_en;\n wire phy_read_calib;\n wire phy_write_calib;\n wire [3:0]\\pi_dqs_found_lanes_r1_reg[3] ;\n wire pi_en_stg2_f_reg;\n wire pi_en_stg2_f_reg_0;\n wire pi_en_stg2_f_reg_1;\n wire pi_en_stg2_f_reg_2;\n wire pi_phase_locked_all_r1_reg;\n wire [5:0]\\pi_rdval_cnt_reg[5] ;\n wire pi_stg2_f_incdec_reg;\n wire pi_stg2_f_incdec_reg_0;\n wire pi_stg2_f_incdec_reg_1;\n wire pi_stg2_f_incdec_reg_2;\n wire pll_locked;\n wire [5:0]\\po_counter_read_val_r_reg[5] ;\n wire [4:0]\\po_rdval_cnt_reg[8] ;\n wire [4:0]\\po_rdval_cnt_reg[8]_0 ;\n wire [1:0]\\po_stg2_wrcal_cnt_reg[1] ;\n wire prbs_rdlvl_start_reg;\n wire ram_init_done_r;\n wire rd_buf_we;\n wire [1:0]\\rd_mux_sel_r_reg[1] ;\n wire [33:0]\\rd_ptr_reg[3] ;\n wire [17:0]\\rd_ptr_reg[3]_0 ;\n wire \\rd_ptr_timing_reg[2] ;\n wire \\rd_ptr_timing_reg[2]_0 ;\n wire \\rd_ptr_timing_reg[2]_1 ;\n wire \\rd_ptr_timing_reg[2]_10 ;\n wire \\rd_ptr_timing_reg[2]_2 ;\n wire \\rd_ptr_timing_reg[2]_3 ;\n wire \\rd_ptr_timing_reg[2]_4 ;\n wire \\rd_ptr_timing_reg[2]_5 ;\n wire \\rd_ptr_timing_reg[2]_6 ;\n wire \\rd_ptr_timing_reg[2]_7 ;\n wire \\rd_ptr_timing_reg[2]_8 ;\n wire \\rd_ptr_timing_reg[2]_9 ;\n wire [0:0]\\read_fifo.fifo_out_data_r_reg[6] ;\n wire \\read_fifo.fifo_out_data_r_reg[6]_0 ;\n wire \\read_fifo.tail_r_reg[0] ;\n wire [0:0]\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ;\n wire rst_sync_r1;\n wire rst_sync_r1_reg;\n wire rstdiv0_sync_r1_reg_rep__9;\n wire sync_pulse;\n wire sys_rst;\n wire [0:0]tail_r;\n wire wr_en;\n wire wr_en_5;\n wire wr_en_6;\n wire [3:0]\\wr_ptr_timing_reg[2] ;\n wire [3:0]\\wr_ptr_timing_reg[2]_0 ;\n wire [3:0]\\wr_ptr_timing_reg[2]_1 ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[224] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[225] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[226] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[227] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[228] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[229] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[230] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[231] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[232] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[233] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[234] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[235] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[236] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[237] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[238] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[239] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[240] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[241] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[242] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[243] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[244] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[245] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[246] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[247] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[248] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[249] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[250] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[251] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[252] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[253] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[254] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[255] ;\n\n FDRE #(\n .INIT(1'b0)) \n \\A[0]__0 \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ),\n .Q(\\A[0]__0_n_0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\A[0]__4 \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_byte_sel_div1.byte_sel_cnt_reg[0]_1 ),\n .Q(\\A[0]__4_n_0 ),\n .R(1'b0));\n FDSE #(\n .INIT(1'b1)) \n \\A[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 ),\n .Q(\\A_n_0_[1] ),\n .S(\\gen_byte_sel_div1.byte_sel_cnt_reg[2] ));\n FDSE #(\n .INIT(1'b1)) \n \\A[1]__0 \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_byte_sel_div1.byte_sel_cnt_reg[0]_2 ),\n .Q(\\A[1]__0_n_0 ),\n .S(\\gen_byte_sel_div1.byte_sel_cnt_reg[2] ));\n FDSE #(\n .INIT(1'b1)) \n \\A[1]__3 \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_byte_sel_div1.byte_sel_cnt_reg[0]_3 ),\n .Q(\\A[1]__3_n_0 ),\n .S(\\gen_byte_sel_div1.byte_sel_cnt_reg[2] ));\n FDSE #(\n .INIT(1'b1)) \n \\A[1]__4 \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_byte_sel_div1.byte_sel_cnt_reg[0]_4 ),\n .Q(\\A[1]__4_n_0 ),\n .S(\\gen_byte_sel_div1.byte_sel_cnt_reg[2] ));\n FDRE #(\n .INIT(1'b0)) \n \\A[2]__1 \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_byte_sel_div1.byte_sel_cnt_reg[2]_1 ),\n .Q(\\A[2]__1_n_0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\A[2]__2 \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_byte_sel_div1.byte_sel_cnt_reg[0] ),\n .Q(\\fine_delay_mod_reg[26]_0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\byte_sel_data_map_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_byte_sel_div1.byte_sel_cnt_reg[2]_2 ),\n .Q(byte_sel_data_map),\n .R(1'b0));\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* box_type = \"PRIMITIVE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\cke_odt_thru_outfifo.gen_cke_obuf[0].u_cs_n_obuf \n (.I(mem_dq_out[71]),\n .O(ddr3_cke));\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* box_type = \"PRIMITIVE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\cke_odt_thru_outfifo.gen_odt_obuf.gen_odt_obuf[0].u_cs_n_obuf \n (.I(mem_dq_out[70]),\n .O(ddr3_odt));\n FDRE #(\n .INIT(1'b0)) \n \\data_offset_1_i1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [0]),\n .Q(data_offset_1_i1[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_offset_1_i1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [1]),\n .Q(data_offset_1_i1[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_offset_1_i1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [2]),\n .Q(data_offset_1_i1[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_offset_1_i1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [3]),\n .Q(data_offset_1_i1[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_offset_1_i1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [4]),\n .Q(data_offset_1_i1[4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_offset_1_i1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [5]),\n .Q(data_offset_1_i1[5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_offset_1_i2_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(data_offset_1_i1[0]),\n .Q(data_offset_1_i2[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_offset_1_i2_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(data_offset_1_i1[1]),\n .Q(data_offset_1_i2[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_offset_1_i2_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(data_offset_1_i1[2]),\n .Q(data_offset_1_i2[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_offset_1_i2_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(data_offset_1_i1[3]),\n .Q(data_offset_1_i2[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_offset_1_i2_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(data_offset_1_i1[4]),\n .Q(data_offset_1_i2[4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_offset_1_i2_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(data_offset_1_i1[5]),\n .Q(data_offset_1_i2[5]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFFEFFFFFFFE0000)) \n \\fine_delay_mod[11]_i_1 \n (.I0(\\fine_delay_mod[11]_i_2_n_0 ),\n .I1(\\fine_delay_mod[11]_i_3_n_0 ),\n .I2(\\fine_delay_mod[11]_i_4_n_0 ),\n .I3(\\fine_delay_mod[11]_i_5_n_0 ),\n .I4(fine_delay_mod0[11]),\n .I5(fine_delay_mod[3]),\n .O(\\fine_delay_mod[11]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1024\" *) \n LUT5 #(\n .INIT(32'h00575757)) \n \\fine_delay_mod[11]_i_10 \n (.I0(\\A[0]__4_n_0 ),\n .I1(\\A[1]__4_n_0 ),\n .I2(byte_sel_data_map),\n .I3(\\fine_delay_mod_reg[26]_0 ),\n .I4(\\A[1]__3_n_0 ),\n .O(\\fine_delay_mod[11]_i_10_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1023\" *) \n LUT5 #(\n .INIT(32'h0000F888)) \n \\fine_delay_mod[11]_i_11 \n (.I0(\\A[1]__0_n_0 ),\n .I1(\\A[0]__0_n_0 ),\n .I2(\\fine_delay_mod_reg[26]_0 ),\n .I3(\\A_n_0_[1] ),\n .I4(\\A[2]__1_n_0 ),\n .O(\\fine_delay_mod[11]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'h0088008800F80088)) \n \\fine_delay_mod[11]_i_12 \n (.I0(\\A[0]__4_n_0 ),\n .I1(byte_sel_data_map),\n .I2(\\A[0]__0_n_0 ),\n .I3(\\fine_delay_mod_reg[26]_0 ),\n .I4(byte_sel_data_map),\n .I5(\\A[0]__0_n_0 ),\n .O(\\fine_delay_mod[11]_i_12_n_0 ));\n LUT6 #(\n .INIT(64'hF780808080808080)) \n \\fine_delay_mod[11]_i_2 \n (.I0(\\A[1]__4_n_0 ),\n .I1(\\A[0]__4_n_0 ),\n .I2(\\genblk9[6].fine_delay_incdec_pb_reg[6] ),\n .I3(\\A[1]__3_n_0 ),\n .I4(\\genblk9[5].fine_delay_incdec_pb_reg[5] ),\n .I5(\\fine_delay_mod_reg[26]_0 ),\n .O(\\fine_delay_mod[11]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000770400000000)) \n \\fine_delay_mod[11]_i_3 \n (.I0(\\A[1]__3_n_0 ),\n .I1(\\fine_delay_mod_reg[26]_0 ),\n .I2(\\A[1]__4_n_0 ),\n .I3(\\fine_delay_mod[11]_i_7_n_0 ),\n .I4(\\A[2]__1_n_0 ),\n .I5(\\fine_delay_mod[23]_i_6_n_0 ),\n .O(\\fine_delay_mod[11]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0700000000000000)) \n \\fine_delay_mod[11]_i_4 \n (.I0(\\A[1]__3_n_0 ),\n .I1(\\fine_delay_mod_reg[26]_0 ),\n .I2(\\A[1]__4_n_0 ),\n .I3(\\A[0]__4_n_0 ),\n .I4(byte_sel_data_map),\n .I5(\\genblk9[4].fine_delay_incdec_pb_reg[4] ),\n .O(\\fine_delay_mod[11]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h8000800088008000)) \n \\fine_delay_mod[11]_i_5 \n (.I0(\\fine_delay_mod[11]_i_9_n_0 ),\n .I1(\\fine_delay_mod[11]_i_10_n_0 ),\n .I2(\\A[2]__1_n_0 ),\n .I3(\\A[0]__0_n_0 ),\n .I4(\\fine_delay_mod[23]_i_8_n_0 ),\n .I5(\\A[1]__0_n_0 ),\n .O(\\fine_delay_mod[11]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFF888)) \n \\fine_delay_mod[11]_i_6 \n (.I0(\\A[1]__4_n_0 ),\n .I1(\\A[0]__4_n_0 ),\n .I2(\\fine_delay_mod_reg[26]_0 ),\n .I3(\\A[1]__3_n_0 ),\n .I4(\\fine_delay_mod[11]_i_11_n_0 ),\n .I5(\\fine_delay_mod[11]_i_12_n_0 ),\n .O(fine_delay_mod0[11]));\n (* SOFT_HLUTNM = \"soft_lutpair1035\" *) \n LUT3 #(\n .INIT(8'h1F)) \n \\fine_delay_mod[11]_i_7 \n (.I0(byte_sel_data_map),\n .I1(\\A[1]__4_n_0 ),\n .I2(\\A[0]__4_n_0 ),\n .O(\\fine_delay_mod[11]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1029\" *) \n LUT4 #(\n .INIT(16'h0008)) \n \\fine_delay_mod[11]_i_9 \n (.I0(byte_sel_data_map),\n .I1(\\genblk9[0].fine_delay_incdec_pb_reg[0] ),\n .I2(\\fine_delay_mod_reg[26]_0 ),\n .I3(\\A[0]__0_n_0 ),\n .O(\\fine_delay_mod[11]_i_9_n_0 ));\n LUT5 #(\n .INIT(32'hEEEFEEE0)) \n \\fine_delay_mod[14]_i_1 \n (.I0(\\fine_delay_mod[14]_i_2_n_0 ),\n .I1(\\fine_delay_mod[14]_i_3_n_0 ),\n .I2(\\fine_delay_mod[14]_i_4_n_0 ),\n .I3(\\fine_delay_mod[14]_i_5_n_0 ),\n .I4(fine_delay_mod[4]),\n .O(\\fine_delay_mod[14]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hC480FFFFC4800000)) \n \\fine_delay_mod[14]_i_2 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(\\A[2]__1_n_0 ),\n .I2(\\fine_delay_mod[14]_i_6_n_0 ),\n .I3(\\genblk9[3].fine_delay_incdec_pb_reg[3] ),\n .I4(\\fine_delay_mod[14]_i_7_n_0 ),\n .I5(\\genblk9[4].fine_delay_incdec_pb_reg[4]_0 ),\n .O(\\fine_delay_mod[14]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00B0003000300030)) \n \\fine_delay_mod[14]_i_3 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(\\A[2]__1_n_0 ),\n .I2(\\fine_delay_mod[17]_i_8_n_0 ),\n .I3(\\A[0]__0_n_0 ),\n .I4(\\A[1]__0_n_0 ),\n .I5(\\fine_delay_mod[14]_i_8_n_0 ),\n .O(\\fine_delay_mod[14]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1032\" *) \n LUT4 #(\n .INIT(16'h444C)) \n \\fine_delay_mod[14]_i_4 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(\\A[2]__1_n_0 ),\n .I2(\\A[0]__0_n_0 ),\n .I3(\\A[1]__0_n_0 ),\n .O(\\fine_delay_mod[14]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h000000FF02020202)) \n \\fine_delay_mod[14]_i_5 \n (.I0(\\A[0]__0_n_0 ),\n .I1(byte_sel_data_map),\n .I2(\\A[0]__0_n_0 ),\n .I3(\\A[0]__4_n_0 ),\n .I4(byte_sel_data_map),\n .I5(\\fine_delay_mod_reg[26]_0 ),\n .O(\\fine_delay_mod[14]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h020202FF02020200)) \n \\fine_delay_mod[14]_i_6 \n (.I0(\\genblk9[1].fine_delay_incdec_pb_reg[1] ),\n .I1(\\A_n_0_[1] ),\n .I2(\\fine_delay_mod_reg[26]_0 ),\n .I3(\\A[1]__0_n_0 ),\n .I4(\\A[0]__0_n_0 ),\n .I5(\\genblk9[2].fine_delay_incdec_pb_reg[2] ),\n .O(\\fine_delay_mod[14]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1037\" *) \n LUT3 #(\n .INIT(8'hFD)) \n \\fine_delay_mod[14]_i_7 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(byte_sel_data_map),\n .I2(\\A[0]__4_n_0 ),\n .O(\\fine_delay_mod[14]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\fine_delay_mod[14]_i_8 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(\\A_n_0_[1] ),\n .O(\\fine_delay_mod[14]_i_8_n_0 ));\n LUT5 #(\n .INIT(32'hEEEFEEE0)) \n \\fine_delay_mod[17]_i_1 \n (.I0(\\fine_delay_mod[17]_i_2_n_0 ),\n .I1(\\fine_delay_mod[17]_i_3_n_0 ),\n .I2(\\fine_delay_mod[17]_i_4_n_0 ),\n .I3(\\fine_delay_mod[17]_i_5_n_0 ),\n .I4(fine_delay_mod[5]),\n .O(\\fine_delay_mod[17]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hC840FFFFC8400000)) \n \\fine_delay_mod[17]_i_2 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(\\A[2]__1_n_0 ),\n .I2(\\fine_delay_mod[17]_i_6_n_0 ),\n .I3(\\genblk9[3].fine_delay_incdec_pb_reg[3] ),\n .I4(\\fine_delay_mod[17]_i_7_n_0 ),\n .I5(\\genblk9[4].fine_delay_incdec_pb_reg[4]_0 ),\n .O(\\fine_delay_mod[17]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h7030000030300000)) \n \\fine_delay_mod[17]_i_3 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(\\A[2]__1_n_0 ),\n .I2(\\fine_delay_mod[17]_i_8_n_0 ),\n .I3(\\A[1]__0_n_0 ),\n .I4(\\A[0]__0_n_0 ),\n .I5(\\fine_delay_mod[17]_i_9_n_0 ),\n .O(\\fine_delay_mod[17]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1032\" *) \n LUT4 #(\n .INIT(16'h88C8)) \n \\fine_delay_mod[17]_i_4 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(\\A[2]__1_n_0 ),\n .I2(\\A[0]__0_n_0 ),\n .I3(\\A[1]__0_n_0 ),\n .O(\\fine_delay_mod[17]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h0000FF0020202020)) \n \\fine_delay_mod[17]_i_5 \n (.I0(\\A[0]__0_n_0 ),\n .I1(byte_sel_data_map),\n .I2(\\A[0]__0_n_0 ),\n .I3(\\A[0]__4_n_0 ),\n .I4(byte_sel_data_map),\n .I5(\\fine_delay_mod_reg[26]_0 ),\n .O(\\fine_delay_mod[17]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h08FF080808000808)) \n \\fine_delay_mod[17]_i_6 \n (.I0(\\genblk9[1].fine_delay_incdec_pb_reg[1] ),\n .I1(\\fine_delay_mod_reg[26]_0 ),\n .I2(\\A_n_0_[1] ),\n .I3(\\A[1]__0_n_0 ),\n .I4(\\A[0]__0_n_0 ),\n .I5(\\genblk9[2].fine_delay_incdec_pb_reg[2] ),\n .O(\\fine_delay_mod[17]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1038\" *) \n LUT3 #(\n .INIT(8'hDF)) \n \\fine_delay_mod[17]_i_7 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(byte_sel_data_map),\n .I2(\\A[0]__4_n_0 ),\n .O(\\fine_delay_mod[17]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1026\" *) \n LUT4 #(\n .INIT(16'h0400)) \n \\fine_delay_mod[17]_i_8 \n (.I0(byte_sel_data_map),\n .I1(\\A[0]__0_n_0 ),\n .I2(\\fine_delay_mod_reg[26]_0 ),\n .I3(\\genblk9[0].fine_delay_incdec_pb_reg[0] ),\n .O(\\fine_delay_mod[17]_i_8_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1040\" *) \n LUT2 #(\n .INIT(4'hB)) \n \\fine_delay_mod[17]_i_9 \n (.I0(\\A_n_0_[1] ),\n .I1(\\fine_delay_mod_reg[26]_0 ),\n .O(\\fine_delay_mod[17]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hFCFFFEFEFC00FEFE)) \n \\fine_delay_mod[20]_i_1 \n (.I0(\\genblk9[4].fine_delay_incdec_pb_reg[4]_0 ),\n .I1(\\fine_delay_mod[20]_i_2_n_0 ),\n .I2(\\fine_delay_mod[20]_i_3_n_0 ),\n .I3(\\fine_delay_mod[20]_i_4_n_0 ),\n .I4(\\fine_delay_mod[20]_i_5_n_0 ),\n .I5(fine_delay_mod[6]),\n .O(\\fine_delay_mod[20]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1036\" *) \n LUT3 #(\n .INIT(8'h80)) \n \\fine_delay_mod[20]_i_2 \n (.I0(\\fine_delay_mod[20]_i_6_n_0 ),\n .I1(\\A[2]__1_n_0 ),\n .I2(\\fine_delay_mod[20]_i_5_n_0 ),\n .O(\\fine_delay_mod[20]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h004400C4)) \n \\fine_delay_mod[20]_i_3 \n (.I0(\\A[2]__1_n_0 ),\n .I1(\\fine_delay_mod[23]_i_7_n_0 ),\n .I2(\\fine_delay_mod[20]_i_7_n_0 ),\n .I3(\\A[0]__0_n_0 ),\n .I4(\\A[1]__0_n_0 ),\n .O(\\fine_delay_mod[20]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hFF808080)) \n \\fine_delay_mod[20]_i_4 \n (.I0(\\A[0]__0_n_0 ),\n .I1(byte_sel_data_map),\n .I2(\\fine_delay_mod[20]_i_8_n_0 ),\n .I3(\\A[2]__1_n_0 ),\n .I4(\\fine_delay_mod[20]_i_9_n_0 ),\n .O(\\fine_delay_mod[20]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1037\" *) \n LUT3 #(\n .INIT(8'hF7)) \n \\fine_delay_mod[20]_i_5 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(byte_sel_data_map),\n .I2(\\A[0]__4_n_0 ),\n .O(\\fine_delay_mod[20]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h08FF080808000808)) \n \\fine_delay_mod[20]_i_6 \n (.I0(\\genblk9[1].fine_delay_incdec_pb_reg[1] ),\n .I1(\\A_n_0_[1] ),\n .I2(\\fine_delay_mod_reg[26]_0 ),\n .I3(\\A[0]__0_n_0 ),\n .I4(\\A[1]__0_n_0 ),\n .I5(\\genblk9[2].fine_delay_incdec_pb_reg[2] ),\n .O(\\fine_delay_mod[20]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1040\" *) \n LUT2 #(\n .INIT(4'hB)) \n \\fine_delay_mod[20]_i_7 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(\\A_n_0_[1] ),\n .O(\\fine_delay_mod[20]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1039\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\fine_delay_mod[20]_i_8 \n (.I0(\\A[0]__0_n_0 ),\n .I1(\\fine_delay_mod_reg[26]_0 ),\n .O(\\fine_delay_mod[20]_i_8_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1030\" *) \n LUT4 #(\n .INIT(16'h22F2)) \n \\fine_delay_mod[20]_i_9 \n (.I0(\\A_n_0_[1] ),\n .I1(\\fine_delay_mod_reg[26]_0 ),\n .I2(\\A[1]__0_n_0 ),\n .I3(\\A[0]__0_n_0 ),\n .O(\\fine_delay_mod[20]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hFCFFFEFEFC00FEFE)) \n \\fine_delay_mod[23]_i_1 \n (.I0(\\genblk9[4].fine_delay_incdec_pb_reg[4]_0 ),\n .I1(\\fine_delay_mod[23]_i_2_n_0 ),\n .I2(\\fine_delay_mod[23]_i_3_n_0 ),\n .I3(\\fine_delay_mod[23]_i_4_n_0 ),\n .I4(\\fine_delay_mod[23]_i_5_n_0 ),\n .I5(fine_delay_mod[7]),\n .O(\\fine_delay_mod[23]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1027\" *) \n LUT4 #(\n .INIT(16'hF888)) \n \\fine_delay_mod[23]_i_10 \n (.I0(\\A_n_0_[1] ),\n .I1(\\fine_delay_mod_reg[26]_0 ),\n .I2(\\A[0]__0_n_0 ),\n .I3(\\A[1]__0_n_0 ),\n .O(\\fine_delay_mod[23]_i_10_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1036\" *) \n LUT3 #(\n .INIT(8'h80)) \n \\fine_delay_mod[23]_i_2 \n (.I0(\\fine_delay_mod[23]_i_6_n_0 ),\n .I1(\\A[2]__1_n_0 ),\n .I2(\\fine_delay_mod[23]_i_5_n_0 ),\n .O(\\fine_delay_mod[23]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h4400C400)) \n \\fine_delay_mod[23]_i_3 \n (.I0(\\A[2]__1_n_0 ),\n .I1(\\fine_delay_mod[23]_i_7_n_0 ),\n .I2(\\fine_delay_mod[23]_i_8_n_0 ),\n .I3(\\A[0]__0_n_0 ),\n .I4(\\A[1]__0_n_0 ),\n .O(\\fine_delay_mod[23]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1025\" *) \n LUT5 #(\n .INIT(32'hFF808080)) \n \\fine_delay_mod[23]_i_4 \n (.I0(\\A[0]__0_n_0 ),\n .I1(byte_sel_data_map),\n .I2(\\fine_delay_mod[23]_i_9_n_0 ),\n .I3(\\A[2]__1_n_0 ),\n .I4(\\fine_delay_mod[23]_i_10_n_0 ),\n .O(\\fine_delay_mod[23]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1038\" *) \n LUT3 #(\n .INIT(8'h7F)) \n \\fine_delay_mod[23]_i_5 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(byte_sel_data_map),\n .I2(\\A[0]__4_n_0 ),\n .O(\\fine_delay_mod[23]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFF80808000808080)) \n \\fine_delay_mod[23]_i_6 \n (.I0(\\genblk9[1].fine_delay_incdec_pb_reg[1] ),\n .I1(\\A_n_0_[1] ),\n .I2(\\fine_delay_mod_reg[26]_0 ),\n .I3(\\A[1]__0_n_0 ),\n .I4(\\A[0]__0_n_0 ),\n .I5(\\genblk9[2].fine_delay_incdec_pb_reg[2] ),\n .O(\\fine_delay_mod[23]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1029\" *) \n LUT4 #(\n .INIT(16'h0800)) \n \\fine_delay_mod[23]_i_7 \n (.I0(byte_sel_data_map),\n .I1(\\genblk9[0].fine_delay_incdec_pb_reg[0] ),\n .I2(\\fine_delay_mod_reg[26]_0 ),\n .I3(\\A[0]__0_n_0 ),\n .O(\\fine_delay_mod[23]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1031\" *) \n LUT2 #(\n .INIT(4'h7)) \n \\fine_delay_mod[23]_i_8 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(\\A_n_0_[1] ),\n .O(\\fine_delay_mod[23]_i_8_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1039\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\fine_delay_mod[23]_i_9 \n (.I0(\\A[0]__0_n_0 ),\n .I1(\\fine_delay_mod_reg[26]_0 ),\n .O(\\fine_delay_mod[23]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFEF00000020)) \n \\fine_delay_mod[26]_i_1 \n (.I0(\\genblk9[0].fine_delay_incdec_pb_reg[0] ),\n .I1(\\A[0]__0_n_0 ),\n .I2(\\fine_delay_mod_reg[26]_0 ),\n .I3(\\A[0]__0_n_0 ),\n .I4(byte_sel_data_map),\n .I5(fine_delay_mod[8]),\n .O(\\fine_delay_mod[26]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFEFFFFFFFE0000)) \n \\fine_delay_mod[2]_i_1 \n (.I0(\\fine_delay_mod[2]_i_2_n_0 ),\n .I1(\\fine_delay_mod[2]_i_3_n_0 ),\n .I2(\\fine_delay_mod[2]_i_4_n_0 ),\n .I3(\\fine_delay_mod[2]_i_5_n_0 ),\n .I4(fine_delay_mod0[2]),\n .I5(fine_delay_mod[0]),\n .O(\\fine_delay_mod[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1027\" *) \n LUT4 #(\n .INIT(16'h111F)) \n \\fine_delay_mod[2]_i_10 \n (.I0(\\A_n_0_[1] ),\n .I1(\\fine_delay_mod_reg[26]_0 ),\n .I2(\\A[0]__0_n_0 ),\n .I3(\\A[1]__0_n_0 ),\n .O(\\fine_delay_mod[2]_i_10_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1033\" *) \n LUT4 #(\n .INIT(16'h1000)) \n \\fine_delay_mod[2]_i_2 \n (.I0(\\A[1]__4_n_0 ),\n .I1(\\A[0]__4_n_0 ),\n .I2(\\genblk9[6].fine_delay_incdec_pb_reg[6] ),\n .I3(\\fine_delay_mod_reg[26]_0 ),\n .O(\\fine_delay_mod[2]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h00A80000)) \n \\fine_delay_mod[2]_i_3 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(\\A[1]__4_n_0 ),\n .I2(\\fine_delay_mod[2]_i_7_n_0 ),\n .I3(\\A[2]__1_n_0 ),\n .I4(\\fine_delay_mod[14]_i_6_n_0 ),\n .O(\\fine_delay_mod[2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h5500752055005500)) \n \\fine_delay_mod[2]_i_4 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(\\A[0]__4_n_0 ),\n .I2(\\A[1]__4_n_0 ),\n .I3(\\genblk9[7].fine_delay_incdec_pb_reg[7] ),\n .I4(byte_sel_data_map),\n .I5(\\genblk9[4].fine_delay_incdec_pb_reg[4] ),\n .O(\\fine_delay_mod[2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hAA80000000000000)) \n \\fine_delay_mod[2]_i_5 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(byte_sel_data_map),\n .I2(\\A[1]__4_n_0 ),\n .I3(\\A[0]__4_n_0 ),\n .I4(\\fine_delay_mod[5]_i_8_n_0 ),\n .I5(\\fine_delay_mod[2]_i_8_n_0 ),\n .O(\\fine_delay_mod[2]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFDDDFDDDFFFFFDDD)) \n \\fine_delay_mod[2]_i_6 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(\\fine_delay_mod[2]_i_9_n_0 ),\n .I2(\\fine_delay_mod[5]_i_11_n_0 ),\n .I3(\\fine_delay_mod[20]_i_8_n_0 ),\n .I4(\\fine_delay_mod[2]_i_10_n_0 ),\n .I5(\\A[2]__1_n_0 ),\n .O(fine_delay_mod0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1034\" *) \n LUT3 #(\n .INIT(8'hF8)) \n \\fine_delay_mod[2]_i_7 \n (.I0(byte_sel_data_map),\n .I1(\\A[1]__4_n_0 ),\n .I2(\\A[0]__4_n_0 ),\n .O(\\fine_delay_mod[2]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1022\" *) \n LUT5 #(\n .INIT(32'h00FF00A8)) \n \\fine_delay_mod[2]_i_8 \n (.I0(\\A[1]__0_n_0 ),\n .I1(\\fine_delay_mod_reg[26]_0 ),\n .I2(\\A_n_0_[1] ),\n .I3(\\A[0]__0_n_0 ),\n .I4(\\A[2]__1_n_0 ),\n .O(\\fine_delay_mod[2]_i_8_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1028\" *) \n LUT4 #(\n .INIT(16'h010F)) \n \\fine_delay_mod[2]_i_9 \n (.I0(byte_sel_data_map),\n .I1(\\fine_delay_mod_reg[26]_0 ),\n .I2(\\A[0]__4_n_0 ),\n .I3(\\A[1]__4_n_0 ),\n .O(\\fine_delay_mod[2]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hFFFEFFFFFFFE0000)) \n \\fine_delay_mod[5]_i_1 \n (.I0(\\fine_delay_mod[5]_i_2_n_0 ),\n .I1(\\fine_delay_mod[5]_i_3_n_0 ),\n .I2(\\fine_delay_mod[5]_i_4_n_0 ),\n .I3(\\fine_delay_mod[5]_i_5_n_0 ),\n .I4(fine_delay_mod0[5]),\n .I5(fine_delay_mod[1]),\n .O(\\fine_delay_mod[5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1028\" *) \n LUT4 #(\n .INIT(16'h10F0)) \n \\fine_delay_mod[5]_i_10 \n (.I0(byte_sel_data_map),\n .I1(\\fine_delay_mod_reg[26]_0 ),\n .I2(\\A[0]__4_n_0 ),\n .I3(\\A[1]__4_n_0 ),\n .O(\\fine_delay_mod[5]_i_10_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1025\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\fine_delay_mod[5]_i_11 \n (.I0(byte_sel_data_map),\n .I1(\\A[0]__0_n_0 ),\n .O(\\fine_delay_mod[5]_i_11_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1030\" *) \n LUT4 #(\n .INIT(16'h22F2)) \n \\fine_delay_mod[5]_i_12 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(\\A_n_0_[1] ),\n .I2(\\A[0]__0_n_0 ),\n .I3(\\A[1]__0_n_0 ),\n .O(\\fine_delay_mod[5]_i_12_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1033\" *) \n LUT4 #(\n .INIT(16'h0040)) \n \\fine_delay_mod[5]_i_2 \n (.I0(\\A[1]__4_n_0 ),\n .I1(\\A[0]__4_n_0 ),\n .I2(\\genblk9[6].fine_delay_incdec_pb_reg[6] ),\n .I3(\\fine_delay_mod_reg[26]_0 ),\n .O(\\fine_delay_mod[5]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1031\" *) \n LUT4 #(\n .INIT(16'h0400)) \n \\fine_delay_mod[5]_i_3 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(\\fine_delay_mod[5]_i_7_n_0 ),\n .I2(\\A[2]__1_n_0 ),\n .I3(\\fine_delay_mod[17]_i_6_n_0 ),\n .O(\\fine_delay_mod[5]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hAA00EA40AA00AA00)) \n \\fine_delay_mod[5]_i_4 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(\\A[1]__4_n_0 ),\n .I2(\\A[0]__4_n_0 ),\n .I3(\\genblk9[7].fine_delay_incdec_pb_reg[7] ),\n .I4(byte_sel_data_map),\n .I5(\\genblk9[4].fine_delay_incdec_pb_reg[4] ),\n .O(\\fine_delay_mod[5]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h4055000000000000)) \n \\fine_delay_mod[5]_i_5 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(byte_sel_data_map),\n .I2(\\A[1]__4_n_0 ),\n .I3(\\A[0]__4_n_0 ),\n .I4(\\fine_delay_mod[5]_i_8_n_0 ),\n .I5(\\fine_delay_mod[5]_i_9_n_0 ),\n .O(\\fine_delay_mod[5]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFEEEFEEEFFFFFEEE)) \n \\fine_delay_mod[5]_i_6 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(\\fine_delay_mod[5]_i_10_n_0 ),\n .I2(\\fine_delay_mod[5]_i_11_n_0 ),\n .I3(\\fine_delay_mod[23]_i_9_n_0 ),\n .I4(\\fine_delay_mod[5]_i_12_n_0 ),\n .I5(\\A[2]__1_n_0 ),\n .O(fine_delay_mod0[5]));\n (* SOFT_HLUTNM = \"soft_lutpair1035\" *) \n LUT3 #(\n .INIT(8'h8F)) \n \\fine_delay_mod[5]_i_7 \n (.I0(byte_sel_data_map),\n .I1(\\A[1]__4_n_0 ),\n .I2(\\A[0]__4_n_0 ),\n .O(\\fine_delay_mod[5]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1026\" *) \n LUT4 #(\n .INIT(16'h0004)) \n \\fine_delay_mod[5]_i_8 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(\\genblk9[0].fine_delay_incdec_pb_reg[0] ),\n .I2(\\A[0]__0_n_0 ),\n .I3(byte_sel_data_map),\n .O(\\fine_delay_mod[5]_i_8_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1022\" *) \n LUT5 #(\n .INIT(32'hFF008A00)) \n \\fine_delay_mod[5]_i_9 \n (.I0(\\A[1]__0_n_0 ),\n .I1(\\A_n_0_[1] ),\n .I2(\\fine_delay_mod_reg[26]_0 ),\n .I3(\\A[0]__0_n_0 ),\n .I4(\\A[2]__1_n_0 ),\n .O(\\fine_delay_mod[5]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hFFFEFFFFFFFE0000)) \n \\fine_delay_mod[8]_i_1 \n (.I0(\\fine_delay_mod[8]_i_2_n_0 ),\n .I1(\\fine_delay_mod[8]_i_3_n_0 ),\n .I2(\\fine_delay_mod[8]_i_4_n_0 ),\n .I3(\\fine_delay_mod[8]_i_5_n_0 ),\n .I4(fine_delay_mod0[8]),\n .I5(fine_delay_mod[2]),\n .O(\\fine_delay_mod[8]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00440044004F0044)) \n \\fine_delay_mod[8]_i_10 \n (.I0(\\A[0]__4_n_0 ),\n .I1(byte_sel_data_map),\n .I2(\\A[0]__0_n_0 ),\n .I3(\\fine_delay_mod_reg[26]_0 ),\n .I4(byte_sel_data_map),\n .I5(\\A[0]__0_n_0 ),\n .O(\\fine_delay_mod[8]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'h40404040FB404040)) \n \\fine_delay_mod[8]_i_2 \n (.I0(\\A[0]__4_n_0 ),\n .I1(\\A[1]__4_n_0 ),\n .I2(\\genblk9[6].fine_delay_incdec_pb_reg[6] ),\n .I3(\\A[1]__3_n_0 ),\n .I4(\\genblk9[5].fine_delay_incdec_pb_reg[5] ),\n .I5(\\fine_delay_mod_reg[26]_0 ),\n .O(\\fine_delay_mod[8]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000DD0C00000000)) \n \\fine_delay_mod[8]_i_3 \n (.I0(\\A[1]__3_n_0 ),\n .I1(\\fine_delay_mod_reg[26]_0 ),\n .I2(\\A[1]__4_n_0 ),\n .I3(\\fine_delay_mod[8]_i_7_n_0 ),\n .I4(\\A[2]__1_n_0 ),\n .I5(\\fine_delay_mod[20]_i_6_n_0 ),\n .O(\\fine_delay_mod[8]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h000D000000000000)) \n \\fine_delay_mod[8]_i_4 \n (.I0(\\A[1]__3_n_0 ),\n .I1(\\fine_delay_mod_reg[26]_0 ),\n .I2(\\A[1]__4_n_0 ),\n .I3(\\A[0]__4_n_0 ),\n .I4(byte_sel_data_map),\n .I5(\\genblk9[4].fine_delay_incdec_pb_reg[4] ),\n .O(\\fine_delay_mod[8]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h0080008000880080)) \n \\fine_delay_mod[8]_i_5 \n (.I0(\\fine_delay_mod[11]_i_9_n_0 ),\n .I1(\\fine_delay_mod[8]_i_8_n_0 ),\n .I2(\\A[2]__1_n_0 ),\n .I3(\\A[0]__0_n_0 ),\n .I4(\\fine_delay_mod[20]_i_7_n_0 ),\n .I5(\\A[1]__0_n_0 ),\n .O(\\fine_delay_mod[8]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF4F44)) \n \\fine_delay_mod[8]_i_6 \n (.I0(\\A[0]__4_n_0 ),\n .I1(\\A[1]__4_n_0 ),\n .I2(\\fine_delay_mod_reg[26]_0 ),\n .I3(\\A[1]__3_n_0 ),\n .I4(\\fine_delay_mod[8]_i_9_n_0 ),\n .I5(\\fine_delay_mod[8]_i_10_n_0 ),\n .O(fine_delay_mod0[8]));\n (* SOFT_HLUTNM = \"soft_lutpair1034\" *) \n LUT3 #(\n .INIT(8'hF1)) \n \\fine_delay_mod[8]_i_7 \n (.I0(byte_sel_data_map),\n .I1(\\A[1]__4_n_0 ),\n .I2(\\A[0]__4_n_0 ),\n .O(\\fine_delay_mod[8]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1024\" *) \n LUT5 #(\n .INIT(32'hAB00ABAB)) \n \\fine_delay_mod[8]_i_8 \n (.I0(\\A[0]__4_n_0 ),\n .I1(\\A[1]__4_n_0 ),\n .I2(byte_sel_data_map),\n .I3(\\fine_delay_mod_reg[26]_0 ),\n .I4(\\A[1]__3_n_0 ),\n .O(\\fine_delay_mod[8]_i_8_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1023\" *) \n LUT5 #(\n .INIT(32'h00004F44)) \n \\fine_delay_mod[8]_i_9 \n (.I0(\\A[0]__0_n_0 ),\n .I1(\\A[1]__0_n_0 ),\n .I2(\\fine_delay_mod_reg[26]_0 ),\n .I3(\\A_n_0_[1] ),\n .I4(\\A[2]__1_n_0 ),\n .O(\\fine_delay_mod[8]_i_9_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_mod_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(\\fine_delay_mod[11]_i_1_n_0 ),\n .Q(fine_delay_mod[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_mod_reg[14] \n (.C(CLK),\n .CE(1'b1),\n .D(\\fine_delay_mod[14]_i_1_n_0 ),\n .Q(fine_delay_mod[4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_mod_reg[17] \n (.C(CLK),\n .CE(1'b1),\n .D(\\fine_delay_mod[17]_i_1_n_0 ),\n .Q(fine_delay_mod[5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_mod_reg[20] \n (.C(CLK),\n .CE(1'b1),\n .D(\\fine_delay_mod[20]_i_1_n_0 ),\n .Q(fine_delay_mod[6]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_mod_reg[23] \n (.C(CLK),\n .CE(1'b1),\n .D(\\fine_delay_mod[23]_i_1_n_0 ),\n .Q(fine_delay_mod[7]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_mod_reg[26] \n (.C(CLK),\n .CE(1'b1),\n .D(\\fine_delay_mod[26]_i_1_n_0 ),\n .Q(fine_delay_mod[8]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_mod_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\fine_delay_mod[2]_i_1_n_0 ),\n .Q(fine_delay_mod[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_mod_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\fine_delay_mod[5]_i_1_n_0 ),\n .Q(fine_delay_mod[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fine_delay_mod_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(\\fine_delay_mod[8]_i_1_n_0 ),\n .Q(fine_delay_mod[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n fine_delay_sel_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(fine_delay_sel_reg),\n .Q(fine_delay_sel_r),\n .R(1'b0));\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* box_type = \"PRIMITIVE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_addr_obuf[0].u_addr_obuf \n (.I(mem_dq_out[83]),\n .O(ddr3_addr[0]));\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* box_type = \"PRIMITIVE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_addr_obuf[10].u_addr_obuf \n (.I(mem_dq_out[90]),\n .O(ddr3_addr[10]));\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* box_type = \"PRIMITIVE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_addr_obuf[11].u_addr_obuf \n (.I(mem_dq_out[91]),\n .O(ddr3_addr[11]));\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* box_type = \"PRIMITIVE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_addr_obuf[12].u_addr_obuf \n (.I(mem_dq_out[92]),\n .O(ddr3_addr[12]));\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* box_type = \"PRIMITIVE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_addr_obuf[13].u_addr_obuf \n (.I(mem_dq_out[93]),\n .O(ddr3_addr[13]));\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* box_type = \"PRIMITIVE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_addr_obuf[14].u_addr_obuf \n (.I(mem_dq_out[64]),\n .O(ddr3_addr[14]));\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* box_type = \"PRIMITIVE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_addr_obuf[1].u_addr_obuf \n (.I(mem_dq_out[78]),\n .O(ddr3_addr[1]));\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* box_type = \"PRIMITIVE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_addr_obuf[2].u_addr_obuf \n (.I(mem_dq_out[79]),\n .O(ddr3_addr[2]));\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* box_type = \"PRIMITIVE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_addr_obuf[3].u_addr_obuf \n (.I(mem_dq_out[80]),\n .O(ddr3_addr[3]));\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* box_type = \"PRIMITIVE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_addr_obuf[4].u_addr_obuf \n (.I(mem_dq_out[77]),\n .O(ddr3_addr[4]));\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* box_type = \"PRIMITIVE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_addr_obuf[5].u_addr_obuf \n (.I(mem_dq_out[85]),\n .O(ddr3_addr[5]));\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* box_type = \"PRIMITIVE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_addr_obuf[6].u_addr_obuf \n (.I(mem_dq_out[86]),\n .O(ddr3_addr[6]));\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* box_type = \"PRIMITIVE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_addr_obuf[7].u_addr_obuf \n (.I(mem_dq_out[87]),\n .O(ddr3_addr[7]));\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* box_type = \"PRIMITIVE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_addr_obuf[8].u_addr_obuf \n (.I(mem_dq_out[88]),\n .O(ddr3_addr[8]));\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* box_type = \"PRIMITIVE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_addr_obuf[9].u_addr_obuf \n (.I(mem_dq_out[89]),\n .O(ddr3_addr[9]));\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* box_type = \"PRIMITIVE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_bank_obuf[0].u_bank_obuf \n (.I(mem_dq_out[76]),\n .O(ddr3_ba[0]));\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* box_type = \"PRIMITIVE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_bank_obuf[1].u_bank_obuf \n (.I(mem_dq_out[81]),\n .O(ddr3_ba[1]));\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* box_type = \"PRIMITIVE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_bank_obuf[2].u_bank_obuf \n (.I(mem_dq_out[82]),\n .O(ddr3_ba[2]));\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* box_type = \"PRIMITIVE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_cs_n_obuf.gen_cs_obuf[0].u_cs_n_obuf \n (.I(mem_dq_out[48]),\n .O(ddr3_cs_n));\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* box_type = \"PRIMITIVE\" *) \n OBUFT #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_dm_obuf.loop_dm[0].u_dm_obuf \n (.I(mem_dq_out[45]),\n .O(ddr3_dm[0]),\n .T(mem_dq_ts[45]));\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* box_type = \"PRIMITIVE\" *) \n OBUFT #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_dm_obuf.loop_dm[1].u_dm_obuf \n (.I(mem_dq_out[33]),\n .O(ddr3_dm[1]),\n .T(mem_dq_ts[33]));\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* box_type = \"PRIMITIVE\" *) \n OBUFT #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_dm_obuf.loop_dm[2].u_dm_obuf \n (.I(mem_dq_out[21]),\n .O(ddr3_dm[2]),\n .T(mem_dq_ts[21]));\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* box_type = \"PRIMITIVE\" *) \n OBUFT #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_dm_obuf.loop_dm[3].u_dm_obuf \n (.I(mem_dq_out[9]),\n .O(ddr3_dm[3]),\n .T(mem_dq_ts[9]));\n (* box_type = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[0].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[44]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[0]),\n .O(mem_dq_in[38]),\n .T(mem_dq_ts[44]));\n (* box_type = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[10].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[30]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[10]),\n .O(mem_dq_in[26]),\n .T(mem_dq_ts[30]));\n (* box_type = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[11].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[29]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[11]),\n .O(mem_dq_in[25]),\n .T(mem_dq_ts[29]));\n (* box_type = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[12].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[28]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[12]),\n .O(mem_dq_in[24]),\n .T(mem_dq_ts[28]));\n (* box_type = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[13].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[27]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[13]),\n .O(mem_dq_in[23]),\n .T(mem_dq_ts[27]));\n (* box_type = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[14].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[26]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[14]),\n .O(mem_dq_in[22]),\n .T(mem_dq_ts[26]));\n (* box_type = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[15].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[25]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[15]),\n .O(mem_dq_in[21]),\n .T(mem_dq_ts[25]));\n (* box_type = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[16].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[20]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[16]),\n .O(mem_dq_in[18]),\n .T(mem_dq_ts[20]));\n (* box_type = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[17].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[19]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[17]),\n .O(mem_dq_in[17]),\n .T(mem_dq_ts[19]));\n (* box_type = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[18].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[18]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[18]),\n .O(mem_dq_in[16]),\n .T(mem_dq_ts[18]));\n (* box_type = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[19].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[17]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[19]),\n .O(mem_dq_in[15]),\n .T(mem_dq_ts[17]));\n (* box_type = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[1].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[43]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[1]),\n .O(mem_dq_in[37]),\n .T(mem_dq_ts[43]));\n (* box_type = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[20].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[16]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[20]),\n .O(mem_dq_in[14]),\n .T(mem_dq_ts[16]));\n (* box_type = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[21].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[15]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[21]),\n .O(mem_dq_in[13]),\n .T(mem_dq_ts[15]));\n (* box_type = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[22].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[14]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[22]),\n .O(mem_dq_in[12]),\n .T(mem_dq_ts[14]));\n (* box_type = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[23].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[13]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[23]),\n .O(mem_dq_in[11]),\n .T(mem_dq_ts[13]));\n (* box_type = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[24].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[7]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[24]),\n .O(mem_dq_in[7]),\n .T(mem_dq_ts[7]));\n (* box_type = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[25].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[6]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[25]),\n .O(mem_dq_in[6]),\n .T(mem_dq_ts[6]));\n (* box_type = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[26].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[5]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[26]),\n .O(mem_dq_in[5]),\n .T(mem_dq_ts[5]));\n (* box_type = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[27].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[4]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[27]),\n .O(mem_dq_in[4]),\n .T(mem_dq_ts[4]));\n (* box_type = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[28].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[3]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[28]),\n .O(mem_dq_in[3]),\n .T(mem_dq_ts[3]));\n (* box_type = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[29].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[2]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[29]),\n .O(mem_dq_in[2]),\n .T(mem_dq_ts[2]));\n (* box_type = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[2].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[42]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[2]),\n .O(mem_dq_in[36]),\n .T(mem_dq_ts[42]));\n (* box_type = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[30].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[1]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[30]),\n .O(mem_dq_in[1]),\n .T(mem_dq_ts[1]));\n (* box_type = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[31].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[0]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[31]),\n .O(mem_dq_in[0]),\n .T(mem_dq_ts[0]));\n (* box_type = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[3].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[41]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[3]),\n .O(mem_dq_in[35]),\n .T(mem_dq_ts[41]));\n (* box_type = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[4].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[40]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[4]),\n .O(mem_dq_in[34]),\n .T(mem_dq_ts[40]));\n (* box_type = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[5].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[39]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[5]),\n .O(mem_dq_in[33]),\n .T(mem_dq_ts[39]));\n (* box_type = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[6].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[38]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[6]),\n .O(mem_dq_in[32]),\n .T(mem_dq_ts[38]));\n (* box_type = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[7].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[37]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[7]),\n .O(mem_dq_in[31]),\n .T(mem_dq_ts[37]));\n (* box_type = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[8].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[32]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[8]),\n .O(mem_dq_in[28]),\n .T(mem_dq_ts[32]));\n (* box_type = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[9].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[31]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[9]),\n .O(mem_dq_in[27]),\n .T(mem_dq_ts[31]));\n ddr3_ifmig_7series_v4_0_poc_pd \\gen_dqs_iobuf_HP.gen_dqs_iobuf[0].gen_dqs_diff.u_iddr_edge_det \n (.CLK(CLK),\n .in_dqs_lpbk_to_iddr_0(in_dqs_lpbk_to_iddr_0),\n .mmcm_ps_clk(mmcm_ps_clk),\n .pd_out_pre(pd_out_pre[0]),\n .rst_sync_r1(rst_sync_r1));\n (* box_type = \"PRIMITIVE\" *) \n IOBUFDS_DIFF_OUT_DCIEN #(\n .DQS_BIAS(\"TRUE\"),\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"FALSE\")) \n \\gen_dqs_iobuf_HP.gen_dqs_iobuf[0].gen_dqs_diff.u_iobuf_dqs \n (.DCITERMDISABLE(idle),\n .I(mem_dqs_out[3]),\n .IBUFDISABLE(1'b0),\n .IO(ddr3_dqs_p[0]),\n .IOB(ddr3_dqs_n[0]),\n .O(mem_dqs_in[3]),\n .OB(in_dqs_lpbk_to_iddr_0),\n .TM(mem_dqs_ts[3]),\n .TS(mem_dqs_ts[3]));\n ddr3_ifmig_7series_v4_0_poc_pd_1 \\gen_dqs_iobuf_HP.gen_dqs_iobuf[1].gen_dqs_diff.u_iddr_edge_det \n (.CLK(CLK),\n .in_dqs_lpbk_to_iddr_1(in_dqs_lpbk_to_iddr_1),\n .mmcm_ps_clk(mmcm_ps_clk),\n .pd_out_pre(pd_out_pre[1]),\n .rst_sync_r1(rst_sync_r1));\n (* box_type = \"PRIMITIVE\" *) \n IOBUFDS_DIFF_OUT_DCIEN #(\n .DQS_BIAS(\"TRUE\"),\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"FALSE\")) \n \\gen_dqs_iobuf_HP.gen_dqs_iobuf[1].gen_dqs_diff.u_iobuf_dqs \n (.DCITERMDISABLE(idle),\n .I(mem_dqs_out[2]),\n .IBUFDISABLE(1'b0),\n .IO(ddr3_dqs_p[1]),\n .IOB(ddr3_dqs_n[1]),\n .O(mem_dqs_in[2]),\n .OB(in_dqs_lpbk_to_iddr_1),\n .TM(mem_dqs_ts[2]),\n .TS(mem_dqs_ts[2]));\n ddr3_ifmig_7series_v4_0_poc_pd_2 \\gen_dqs_iobuf_HP.gen_dqs_iobuf[2].gen_dqs_diff.u_iddr_edge_det \n (.CLK(CLK),\n .in_dqs_lpbk_to_iddr_2(in_dqs_lpbk_to_iddr_2),\n .mmcm_ps_clk(mmcm_ps_clk),\n .pd_out_pre(pd_out_pre[2]),\n .rst_sync_r1(rst_sync_r1));\n (* box_type = \"PRIMITIVE\" *) \n IOBUFDS_DIFF_OUT_DCIEN #(\n .DQS_BIAS(\"TRUE\"),\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"FALSE\")) \n \\gen_dqs_iobuf_HP.gen_dqs_iobuf[2].gen_dqs_diff.u_iobuf_dqs \n (.DCITERMDISABLE(idle),\n .I(mem_dqs_out[1]),\n .IBUFDISABLE(1'b0),\n .IO(ddr3_dqs_p[2]),\n .IOB(ddr3_dqs_n[2]),\n .O(mem_dqs_in[1]),\n .OB(in_dqs_lpbk_to_iddr_2),\n .TM(mem_dqs_ts[1]),\n .TS(mem_dqs_ts[1]));\n ddr3_ifmig_7series_v4_0_poc_pd_3 \\gen_dqs_iobuf_HP.gen_dqs_iobuf[3].gen_dqs_diff.u_iddr_edge_det \n (.CLK(CLK),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[1] (\\gen_byte_sel_div1.byte_sel_cnt_reg[1] ),\n .in_dqs_lpbk_to_iddr_3(in_dqs_lpbk_to_iddr_3),\n .mmcm_ps_clk(mmcm_ps_clk),\n .pd_out(pd_out),\n .pd_out_r_reg_0(pd_out_pre),\n .rst_sync_r1(rst_sync_r1));\n (* box_type = \"PRIMITIVE\" *) \n IOBUFDS_DIFF_OUT_DCIEN #(\n .DQS_BIAS(\"TRUE\"),\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"FALSE\")) \n \\gen_dqs_iobuf_HP.gen_dqs_iobuf[3].gen_dqs_diff.u_iobuf_dqs \n (.DCITERMDISABLE(idle),\n .I(mem_dqs_out[0]),\n .IBUFDISABLE(1'b0),\n .IO(ddr3_dqs_p[3]),\n .IOB(ddr3_dqs_n[3]),\n .O(mem_dqs_in[0]),\n .OB(in_dqs_lpbk_to_iddr_3),\n .TM(mem_dqs_ts[0]),\n .TS(mem_dqs_ts[0]));\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* box_type = \"PRIMITIVE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_reset_obuf.u_reset_obuf \n (.I(mux_reset_n),\n .O(ddr3_reset_n));\n ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo \\genblk24.phy_ctl_pre_fifo_0 \n (.CLK(CLK),\n .SR(SR));\n ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized0 \\genblk24.phy_ctl_pre_fifo_1 \n (.CLK(CLK),\n .SR(SR));\n ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized1 \\genblk24.phy_ctl_pre_fifo_2 \n (.CLK(CLK),\n .SR(SR));\n FDRE #(\n .INIT(1'b0)) \n \\phy_ctl_wd_i1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(D[0]),\n .Q(phy_ctl_wd_i1[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\phy_ctl_wd_i1_reg[17] \n (.C(CLK),\n .CE(1'b1),\n .D(D[3]),\n .Q(phy_ctl_wd_i1[17]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\phy_ctl_wd_i1_reg[18] \n (.C(CLK),\n .CE(1'b1),\n .D(D[4]),\n .Q(phy_ctl_wd_i1[18]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\phy_ctl_wd_i1_reg[19] \n (.C(CLK),\n .CE(1'b1),\n .D(D[5]),\n .Q(phy_ctl_wd_i1[19]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\phy_ctl_wd_i1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(D[1]),\n .Q(phy_ctl_wd_i1[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\phy_ctl_wd_i1_reg[20] \n (.C(CLK),\n .CE(1'b1),\n .D(D[6]),\n .Q(phy_ctl_wd_i1[20]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\phy_ctl_wd_i1_reg[21] \n (.C(CLK),\n .CE(1'b1),\n .D(D[7]),\n .Q(phy_ctl_wd_i1[21]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\phy_ctl_wd_i1_reg[22] \n (.C(CLK),\n .CE(1'b1),\n .D(D[8]),\n .Q(phy_ctl_wd_i1[22]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\phy_ctl_wd_i1_reg[23] \n (.C(CLK),\n .CE(1'b1),\n .D(D[9]),\n .Q(phy_ctl_wd_i1[23]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\phy_ctl_wd_i1_reg[24] \n (.C(CLK),\n .CE(1'b1),\n .D(D[10]),\n .Q(phy_ctl_wd_i1[24]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\phy_ctl_wd_i1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(D[2]),\n .Q(phy_ctl_wd_i1[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\phy_ctl_wd_i2_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(phy_ctl_wd_i1[0]),\n .Q(phy_ctl_wd_i2[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\phy_ctl_wd_i2_reg[17] \n (.C(CLK),\n .CE(1'b1),\n .D(phy_ctl_wd_i1[17]),\n .Q(phy_ctl_wd_i2[17]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\phy_ctl_wd_i2_reg[18] \n (.C(CLK),\n .CE(1'b1),\n .D(phy_ctl_wd_i1[18]),\n .Q(phy_ctl_wd_i2[18]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\phy_ctl_wd_i2_reg[19] \n (.C(CLK),\n .CE(1'b1),\n .D(phy_ctl_wd_i1[19]),\n .Q(phy_ctl_wd_i2[19]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\phy_ctl_wd_i2_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(phy_ctl_wd_i1[1]),\n .Q(phy_ctl_wd_i2[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\phy_ctl_wd_i2_reg[20] \n (.C(CLK),\n .CE(1'b1),\n .D(phy_ctl_wd_i1[20]),\n .Q(phy_ctl_wd_i2[20]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\phy_ctl_wd_i2_reg[21] \n (.C(CLK),\n .CE(1'b1),\n .D(phy_ctl_wd_i1[21]),\n .Q(phy_ctl_wd_i2[21]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\phy_ctl_wd_i2_reg[22] \n (.C(CLK),\n .CE(1'b1),\n .D(phy_ctl_wd_i1[22]),\n .Q(phy_ctl_wd_i2[22]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\phy_ctl_wd_i2_reg[23] \n (.C(CLK),\n .CE(1'b1),\n .D(phy_ctl_wd_i1[23]),\n .Q(phy_ctl_wd_i2[23]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\phy_ctl_wd_i2_reg[24] \n (.C(CLK),\n .CE(1'b1),\n .D(phy_ctl_wd_i1[24]),\n .Q(phy_ctl_wd_i2[24]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\phy_ctl_wd_i2_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(phy_ctl_wd_i1[2]),\n .Q(phy_ctl_wd_i2[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n phy_ctl_wr_i1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mux_cmd_wren),\n .Q(phy_ctl_wr_i1),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n phy_ctl_wr_i2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(phy_ctl_wr_i1),\n .Q(phy_ctl_wr_i2),\n .R(1'b0));\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* box_type = \"PRIMITIVE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n u_cas_n_obuf\n (.I(mem_dq_out[74]),\n .O(ddr3_cas_n));\n ddr3_ifmig_7series_v4_0_ddr_mc_phy u_ddr_mc_phy\n (.A(A),\n .CLK(CLK),\n .CLKB0(CLKB0),\n .CLKB0_7(CLKB0_7),\n .CLKB0_8(CLKB0_8),\n .CLKB0_9(CLKB0_9),\n .COUNTERLOADVAL(COUNTERLOADVAL),\n .D0(D0),\n .D1(D1),\n .D2(D2),\n .D3(D3),\n .D4(D4),\n .D5(D5),\n .D6(D6),\n .D7(D7),\n .D8(D8),\n .D9(D9),\n .DOA(DOA),\n .DOB(DOB),\n .DOC(DOC),\n .D_po_coarse_enable110_out(D_po_coarse_enable110_out),\n .D_po_counter_read_en122_out(D_po_counter_read_en122_out),\n .D_po_fine_enable107_out(D_po_fine_enable107_out),\n .D_po_fine_inc113_out(D_po_fine_inc113_out),\n .D_po_sel_fine_oclk_delay125_out(D_po_sel_fine_oclk_delay125_out),\n .E(E),\n .LD0(LD0),\n .LD0_3(LD0_3),\n .LD0_4(LD0_4),\n .LD0_5(LD0_5),\n .Q({phy_ctl_wd_i2[24:17],phy_ctl_wd_i2[2:0]}),\n .RST0(RST0),\n .\\byte_r_reg[0] (\\byte_r_reg[0] ),\n .\\byte_r_reg[0]_0 (\\byte_r_reg[0]_0 ),\n .\\byte_r_reg[1] (\\byte_r_reg[1] ),\n .\\calib_sel_reg[0] (\\calib_sel_reg[0] ),\n .\\calib_sel_reg[0]_0 (\\calib_sel_reg[0]_0 ),\n .\\calib_sel_reg[0]_1 (\\calib_sel_reg[0]_1 ),\n .\\calib_sel_reg[0]_2 (\\calib_sel_reg[0]_2 ),\n .\\calib_sel_reg[0]_3 (\\calib_sel_reg[0]_3 ),\n .\\calib_sel_reg[0]_4 (\\calib_sel_reg[0]_4 ),\n .\\calib_sel_reg[0]_5 (\\calib_sel_reg[0]_5 ),\n .\\calib_sel_reg[0]_6 (\\calib_sel_reg[0]_6 ),\n .\\calib_sel_reg[0]_7 (\\calib_sel_reg[0]_7 ),\n .\\calib_sel_reg[1] (\\calib_sel_reg[1] ),\n .\\calib_sel_reg[1]_0 (\\calib_sel_reg[1]_0 ),\n .\\calib_sel_reg[1]_1 (\\calib_sel_reg[1]_1 ),\n .\\calib_sel_reg[1]_2 (\\calib_sel_reg[1]_2 ),\n .\\calib_sel_reg[1]_3 (\\calib_sel_reg[1]_3 ),\n .\\calib_sel_reg[1]_4 (\\calib_sel_reg[1]_4 ),\n .\\calib_sel_reg[1]_5 (\\calib_sel_reg[1]_5 ),\n .\\calib_sel_reg[1]_6 (\\calib_sel_reg[1]_6 ),\n .\\calib_sel_reg[1]_7 (\\calib_sel_reg[1]_7 ),\n .\\calib_sel_reg[1]_8 (\\calib_sel_reg[1]_8 ),\n .\\calib_sel_reg[3] (\\calib_sel_reg[3] ),\n .\\calib_seq_reg[0] (\\calib_seq_reg[0] ),\n .\\calib_zero_inputs_reg[0] (\\calib_zero_inputs_reg[0] ),\n .\\calib_zero_inputs_reg[0]_0 (\\calib_zero_inputs_reg[0]_0 ),\n .\\calib_zero_inputs_reg[0]_1 (\\calib_zero_inputs_reg[0]_1 ),\n .ck_po_stg2_f_en_reg(ck_po_stg2_f_en_reg),\n .ck_po_stg2_f_en_reg_0(ck_po_stg2_f_en_reg_0),\n .ck_po_stg2_f_en_reg_1(ck_po_stg2_f_en_reg_1),\n .ck_po_stg2_f_en_reg_2(ck_po_stg2_f_en_reg_2),\n .ck_po_stg2_f_indec_reg(ck_po_stg2_f_indec_reg),\n .ck_po_stg2_f_indec_reg_0(ck_po_stg2_f_indec_reg_0),\n .ck_po_stg2_f_indec_reg_1(ck_po_stg2_f_indec_reg_1),\n .ck_po_stg2_f_indec_reg_2(ck_po_stg2_f_indec_reg_2),\n .\\data_bytes_r_reg[63] (\\data_bytes_r_reg[63] ),\n .\\data_offset_1_i2_reg[5] (data_offset_1_i2),\n .ddr_ck_out(ddr_ck_out),\n .delay_done_r4_reg(delay_done_r4_reg),\n .delay_done_r4_reg_0(delay_done_r4_reg_0),\n .delay_done_r4_reg_1(delay_done_r4_reg_1),\n .delay_done_r4_reg_2(delay_done_r4_reg_2),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ),\n .\\fine_delay_mod_reg[23] (\\fine_delay_mod_reg[23]_0 ),\n .freq_refclk(freq_refclk),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\gen_byte_sel_div1.calib_in_common_reg ),\n .\\gen_byte_sel_div1.calib_in_common_reg_0 (\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_1 (\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_10 (\\gen_byte_sel_div1.calib_in_common_reg_10 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_11 (\\gen_byte_sel_div1.calib_in_common_reg_11 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_12 (\\gen_byte_sel_div1.calib_in_common_reg_12 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_13 (\\gen_byte_sel_div1.calib_in_common_reg_13 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_14 (\\gen_byte_sel_div1.calib_in_common_reg_14 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_15 (\\gen_byte_sel_div1.calib_in_common_reg_15 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_16 (\\gen_byte_sel_div1.calib_in_common_reg_16 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_17 (\\gen_byte_sel_div1.calib_in_common_reg_17 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_18 (\\gen_byte_sel_div1.calib_in_common_reg_18 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_19 (\\gen_byte_sel_div1.calib_in_common_reg_19 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_2 (\\gen_byte_sel_div1.calib_in_common_reg_2 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_20 (\\gen_byte_sel_div1.calib_in_common_reg_20 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_3 (\\gen_byte_sel_div1.calib_in_common_reg_3 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_4 (\\gen_byte_sel_div1.calib_in_common_reg_4 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_5 (\\gen_byte_sel_div1.calib_in_common_reg_5 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_6 (\\gen_byte_sel_div1.calib_in_common_reg_6 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_7 (\\gen_byte_sel_div1.calib_in_common_reg_7 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_8 (\\gen_byte_sel_div1.calib_in_common_reg_8 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_9 (\\gen_byte_sel_div1.calib_in_common_reg_9 ),\n .\\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] (\\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] (\\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] (\\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] (\\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] (\\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] (\\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] (\\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] (\\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),\n .\\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] (\\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] (\\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] (\\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] (\\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] (\\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] (\\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] (\\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] (\\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),\n .\\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] (\\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] (\\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] (\\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] (\\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] (\\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] (\\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] (\\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] (\\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),\n .\\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] (\\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] (\\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] (\\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] (\\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] (\\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] (\\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] (\\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] (\\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),\n .\\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] (\\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] (\\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] (\\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] (\\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] (\\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] (\\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] (\\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] (\\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),\n .\\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] (\\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] (\\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] (\\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] (\\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] (\\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] (\\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] (\\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] (\\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),\n .\\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] (\\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] (\\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] (\\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] (\\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] (\\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] (\\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] (\\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] (\\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),\n .\\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] (\\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] (\\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] (\\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] (\\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] (\\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] (\\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] (\\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] (\\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] (\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] (\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ),\n .\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] (\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ),\n .\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] (\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ),\n .\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] (\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ),\n .\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] (\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ),\n .idelay_inc(idelay_inc),\n .idelay_ld_rst(idelay_ld_rst),\n .idelay_ld_rst_0(idelay_ld_rst_0),\n .idelay_ld_rst_1(idelay_ld_rst_1),\n .idelay_ld_rst_2(idelay_ld_rst_2),\n .in0(in0),\n .init_calib_complete_reg_rep(init_calib_complete_reg_rep),\n .init_calib_complete_reg_rep__5(init_calib_complete_reg_rep__5),\n .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6),\n .init_calib_complete_reg_rep__6_0(init_calib_complete_reg_rep__6_0),\n .mc_address(mc_address),\n .mc_cas_n(mc_cas_n),\n .mem_dq_in({mem_dq_in[38:31],mem_dq_in[28:21],mem_dq_in[18:11],mem_dq_in[7:0]}),\n .mem_dq_out({mem_dq_out[93:85],mem_dq_out[83:74],mem_dq_out[71:70],mem_dq_out[64],mem_dq_out[49:48],mem_dq_out[45:37],mem_dq_out[33:25],mem_dq_out[21:13],mem_dq_out[9],mem_dq_out[7:0]}),\n .mem_dq_ts({mem_dq_ts[45:37],mem_dq_ts[33:25],mem_dq_ts[21:13],mem_dq_ts[9],mem_dq_ts[7:0]}),\n .mem_dqs_in(mem_dqs_in),\n .mem_dqs_out(mem_dqs_out),\n .mem_dqs_ts(mem_dqs_ts),\n .mem_out(mem_out),\n .mem_refclk(mem_refclk),\n .mmcm_locked(mmcm_locked),\n .mux_cmd_wren(mux_cmd_wren),\n .mux_rd_valid_r_reg(mux_rd_valid_r_reg),\n .mux_wrdata(mux_wrdata),\n .mux_wrdata_en(mux_wrdata_en),\n .mux_wrdata_mask(mux_wrdata_mask),\n .\\my_empty_reg[1] (\\my_empty_reg[1] ),\n .\\my_empty_reg[1]_0 (\\my_empty_reg[1]_0 ),\n .\\my_empty_reg[1]_1 (\\my_empty_reg[1]_1 ),\n .\\my_empty_reg[1]_2 (\\my_empty_reg[1]_2 ),\n .\\my_empty_reg[1]_3 (\\my_empty_reg[1]_3 ),\n .\\my_empty_reg[1]_4 (\\my_empty_reg[1]_4 ),\n .\\my_empty_reg[1]_5 (\\my_empty_reg[1]_5 ),\n .\\my_empty_reg[1]_6 (\\my_empty_reg[1]_6 ),\n .\\my_empty_reg[7] (\\my_empty_reg[7]_0 ),\n .\\my_empty_reg[7]_0 (\\my_empty_reg[7]_1 ),\n .\\my_empty_reg[7]_1 (\\my_empty_reg[7]_2 ),\n .\\my_empty_reg[7]_2 (\\my_empty_reg[7]_3 ),\n .\\my_empty_reg[7]_3 (\\my_empty_reg[7] ),\n .\\not_strict_mode.app_rd_data_reg[0] (\\not_strict_mode.app_rd_data_reg[0] ),\n .\\not_strict_mode.app_rd_data_reg[100] (\\not_strict_mode.app_rd_data_reg[100] ),\n .\\not_strict_mode.app_rd_data_reg[101] (\\not_strict_mode.app_rd_data_reg[101] ),\n .\\not_strict_mode.app_rd_data_reg[102] (\\not_strict_mode.app_rd_data_reg[102] ),\n .\\not_strict_mode.app_rd_data_reg[103] (\\not_strict_mode.app_rd_data_reg[103] ),\n .\\not_strict_mode.app_rd_data_reg[104] (\\not_strict_mode.app_rd_data_reg[104] ),\n .\\not_strict_mode.app_rd_data_reg[105] (\\not_strict_mode.app_rd_data_reg[105] ),\n .\\not_strict_mode.app_rd_data_reg[106] (\\not_strict_mode.app_rd_data_reg[106] ),\n .\\not_strict_mode.app_rd_data_reg[107] (\\not_strict_mode.app_rd_data_reg[107] ),\n .\\not_strict_mode.app_rd_data_reg[108] (\\not_strict_mode.app_rd_data_reg[108] ),\n .\\not_strict_mode.app_rd_data_reg[109] (\\not_strict_mode.app_rd_data_reg[109] ),\n .\\not_strict_mode.app_rd_data_reg[10] (\\not_strict_mode.app_rd_data_reg[10] ),\n .\\not_strict_mode.app_rd_data_reg[110] (\\not_strict_mode.app_rd_data_reg[110] ),\n .\\not_strict_mode.app_rd_data_reg[111] (\\not_strict_mode.app_rd_data_reg[111] ),\n .\\not_strict_mode.app_rd_data_reg[112] (\\not_strict_mode.app_rd_data_reg[112] ),\n .\\not_strict_mode.app_rd_data_reg[113] (\\not_strict_mode.app_rd_data_reg[113] ),\n .\\not_strict_mode.app_rd_data_reg[114] (\\not_strict_mode.app_rd_data_reg[114] ),\n .\\not_strict_mode.app_rd_data_reg[115] (\\not_strict_mode.app_rd_data_reg[115] ),\n .\\not_strict_mode.app_rd_data_reg[116] (\\not_strict_mode.app_rd_data_reg[116] ),\n .\\not_strict_mode.app_rd_data_reg[117] (\\not_strict_mode.app_rd_data_reg[117] ),\n .\\not_strict_mode.app_rd_data_reg[118] (\\not_strict_mode.app_rd_data_reg[118] ),\n .\\not_strict_mode.app_rd_data_reg[119] (\\not_strict_mode.app_rd_data_reg[119] ),\n .\\not_strict_mode.app_rd_data_reg[11] (\\not_strict_mode.app_rd_data_reg[11] ),\n .\\not_strict_mode.app_rd_data_reg[120] (\\not_strict_mode.app_rd_data_reg[120] ),\n .\\not_strict_mode.app_rd_data_reg[121] (\\not_strict_mode.app_rd_data_reg[121] ),\n .\\not_strict_mode.app_rd_data_reg[122] (\\not_strict_mode.app_rd_data_reg[122] ),\n .\\not_strict_mode.app_rd_data_reg[123] (\\not_strict_mode.app_rd_data_reg[123] ),\n .\\not_strict_mode.app_rd_data_reg[124] (\\not_strict_mode.app_rd_data_reg[124] ),\n .\\not_strict_mode.app_rd_data_reg[125] (\\not_strict_mode.app_rd_data_reg[125] ),\n .\\not_strict_mode.app_rd_data_reg[126] (\\not_strict_mode.app_rd_data_reg[126] ),\n .\\not_strict_mode.app_rd_data_reg[127] (\\not_strict_mode.app_rd_data_reg[127] ),\n .\\not_strict_mode.app_rd_data_reg[128] (\\not_strict_mode.app_rd_data_reg[128] ),\n .\\not_strict_mode.app_rd_data_reg[129] (\\not_strict_mode.app_rd_data_reg[129] ),\n .\\not_strict_mode.app_rd_data_reg[12] (\\not_strict_mode.app_rd_data_reg[12] ),\n .\\not_strict_mode.app_rd_data_reg[130] (\\not_strict_mode.app_rd_data_reg[130] ),\n .\\not_strict_mode.app_rd_data_reg[131] (\\not_strict_mode.app_rd_data_reg[131] ),\n .\\not_strict_mode.app_rd_data_reg[132] (\\not_strict_mode.app_rd_data_reg[132] ),\n .\\not_strict_mode.app_rd_data_reg[133] (\\not_strict_mode.app_rd_data_reg[133] ),\n .\\not_strict_mode.app_rd_data_reg[134] (\\not_strict_mode.app_rd_data_reg[134] ),\n .\\not_strict_mode.app_rd_data_reg[135] (\\not_strict_mode.app_rd_data_reg[135] ),\n .\\not_strict_mode.app_rd_data_reg[136] (\\not_strict_mode.app_rd_data_reg[136] ),\n .\\not_strict_mode.app_rd_data_reg[137] (\\not_strict_mode.app_rd_data_reg[137] ),\n .\\not_strict_mode.app_rd_data_reg[138] (\\not_strict_mode.app_rd_data_reg[138] ),\n .\\not_strict_mode.app_rd_data_reg[139] (\\not_strict_mode.app_rd_data_reg[139] ),\n .\\not_strict_mode.app_rd_data_reg[13] (\\not_strict_mode.app_rd_data_reg[13] ),\n .\\not_strict_mode.app_rd_data_reg[140] (\\not_strict_mode.app_rd_data_reg[140] ),\n .\\not_strict_mode.app_rd_data_reg[141] (\\not_strict_mode.app_rd_data_reg[141] ),\n .\\not_strict_mode.app_rd_data_reg[142] (\\not_strict_mode.app_rd_data_reg[142] ),\n .\\not_strict_mode.app_rd_data_reg[143] (\\not_strict_mode.app_rd_data_reg[143] ),\n .\\not_strict_mode.app_rd_data_reg[144] (\\not_strict_mode.app_rd_data_reg[144] ),\n .\\not_strict_mode.app_rd_data_reg[145] (\\not_strict_mode.app_rd_data_reg[145] ),\n .\\not_strict_mode.app_rd_data_reg[146] (\\not_strict_mode.app_rd_data_reg[146] ),\n .\\not_strict_mode.app_rd_data_reg[147] (\\not_strict_mode.app_rd_data_reg[147] ),\n .\\not_strict_mode.app_rd_data_reg[148] (\\not_strict_mode.app_rd_data_reg[148] ),\n .\\not_strict_mode.app_rd_data_reg[149] (\\not_strict_mode.app_rd_data_reg[149] ),\n .\\not_strict_mode.app_rd_data_reg[14] (\\not_strict_mode.app_rd_data_reg[14] ),\n .\\not_strict_mode.app_rd_data_reg[150] (\\not_strict_mode.app_rd_data_reg[150] ),\n .\\not_strict_mode.app_rd_data_reg[151] (\\not_strict_mode.app_rd_data_reg[151] ),\n .\\not_strict_mode.app_rd_data_reg[152] (\\not_strict_mode.app_rd_data_reg[152] ),\n .\\not_strict_mode.app_rd_data_reg[153] (\\not_strict_mode.app_rd_data_reg[153] ),\n .\\not_strict_mode.app_rd_data_reg[154] (\\not_strict_mode.app_rd_data_reg[154] ),\n .\\not_strict_mode.app_rd_data_reg[155] (\\not_strict_mode.app_rd_data_reg[155] ),\n .\\not_strict_mode.app_rd_data_reg[156] (\\not_strict_mode.app_rd_data_reg[156] ),\n .\\not_strict_mode.app_rd_data_reg[157] (\\not_strict_mode.app_rd_data_reg[157] ),\n .\\not_strict_mode.app_rd_data_reg[158] (\\not_strict_mode.app_rd_data_reg[158] ),\n .\\not_strict_mode.app_rd_data_reg[159] (\\not_strict_mode.app_rd_data_reg[159] ),\n .\\not_strict_mode.app_rd_data_reg[15] (\\not_strict_mode.app_rd_data_reg[15] ),\n .\\not_strict_mode.app_rd_data_reg[15]_0 (\\not_strict_mode.app_rd_data_reg[15]_0 ),\n .\\not_strict_mode.app_rd_data_reg[15]_1 (\\not_strict_mode.app_rd_data_reg[15]_1 ),\n .\\not_strict_mode.app_rd_data_reg[160] (\\not_strict_mode.app_rd_data_reg[160] ),\n .\\not_strict_mode.app_rd_data_reg[161] (\\not_strict_mode.app_rd_data_reg[161] ),\n .\\not_strict_mode.app_rd_data_reg[162] (\\not_strict_mode.app_rd_data_reg[162] ),\n .\\not_strict_mode.app_rd_data_reg[163] (\\not_strict_mode.app_rd_data_reg[163] ),\n .\\not_strict_mode.app_rd_data_reg[164] (\\not_strict_mode.app_rd_data_reg[164] ),\n .\\not_strict_mode.app_rd_data_reg[165] (\\not_strict_mode.app_rd_data_reg[165] ),\n .\\not_strict_mode.app_rd_data_reg[166] (\\not_strict_mode.app_rd_data_reg[166] ),\n .\\not_strict_mode.app_rd_data_reg[167] (\\not_strict_mode.app_rd_data_reg[167] ),\n .\\not_strict_mode.app_rd_data_reg[168] (\\not_strict_mode.app_rd_data_reg[168] ),\n .\\not_strict_mode.app_rd_data_reg[169] (\\not_strict_mode.app_rd_data_reg[169] ),\n .\\not_strict_mode.app_rd_data_reg[16] (\\not_strict_mode.app_rd_data_reg[16] ),\n .\\not_strict_mode.app_rd_data_reg[170] (\\not_strict_mode.app_rd_data_reg[170] ),\n .\\not_strict_mode.app_rd_data_reg[171] (\\not_strict_mode.app_rd_data_reg[171] ),\n .\\not_strict_mode.app_rd_data_reg[172] (\\not_strict_mode.app_rd_data_reg[172] ),\n .\\not_strict_mode.app_rd_data_reg[173] (\\not_strict_mode.app_rd_data_reg[173] ),\n .\\not_strict_mode.app_rd_data_reg[174] (\\not_strict_mode.app_rd_data_reg[174] ),\n .\\not_strict_mode.app_rd_data_reg[175] (\\not_strict_mode.app_rd_data_reg[175] ),\n .\\not_strict_mode.app_rd_data_reg[176] (\\not_strict_mode.app_rd_data_reg[176] ),\n .\\not_strict_mode.app_rd_data_reg[177] (\\not_strict_mode.app_rd_data_reg[177] ),\n .\\not_strict_mode.app_rd_data_reg[178] (\\not_strict_mode.app_rd_data_reg[178] ),\n .\\not_strict_mode.app_rd_data_reg[179] (\\not_strict_mode.app_rd_data_reg[179] ),\n .\\not_strict_mode.app_rd_data_reg[17] (\\not_strict_mode.app_rd_data_reg[17] ),\n .\\not_strict_mode.app_rd_data_reg[180] (\\not_strict_mode.app_rd_data_reg[180] ),\n .\\not_strict_mode.app_rd_data_reg[181] (\\not_strict_mode.app_rd_data_reg[181] ),\n .\\not_strict_mode.app_rd_data_reg[182] (\\not_strict_mode.app_rd_data_reg[182] ),\n .\\not_strict_mode.app_rd_data_reg[183] (\\not_strict_mode.app_rd_data_reg[183] ),\n .\\not_strict_mode.app_rd_data_reg[184] (\\not_strict_mode.app_rd_data_reg[184] ),\n .\\not_strict_mode.app_rd_data_reg[185] (\\not_strict_mode.app_rd_data_reg[185] ),\n .\\not_strict_mode.app_rd_data_reg[186] (\\not_strict_mode.app_rd_data_reg[186] ),\n .\\not_strict_mode.app_rd_data_reg[187] (\\not_strict_mode.app_rd_data_reg[187] ),\n .\\not_strict_mode.app_rd_data_reg[188] (\\not_strict_mode.app_rd_data_reg[188] ),\n .\\not_strict_mode.app_rd_data_reg[189] (\\not_strict_mode.app_rd_data_reg[189] ),\n .\\not_strict_mode.app_rd_data_reg[18] (\\not_strict_mode.app_rd_data_reg[18] ),\n .\\not_strict_mode.app_rd_data_reg[190] (\\not_strict_mode.app_rd_data_reg[190] ),\n .\\not_strict_mode.app_rd_data_reg[191] (\\not_strict_mode.app_rd_data_reg[191] ),\n .\\not_strict_mode.app_rd_data_reg[192] (\\not_strict_mode.app_rd_data_reg[192] ),\n .\\not_strict_mode.app_rd_data_reg[193] (\\not_strict_mode.app_rd_data_reg[193] ),\n .\\not_strict_mode.app_rd_data_reg[194] (\\not_strict_mode.app_rd_data_reg[194] ),\n .\\not_strict_mode.app_rd_data_reg[195] (\\not_strict_mode.app_rd_data_reg[195] ),\n .\\not_strict_mode.app_rd_data_reg[196] (\\not_strict_mode.app_rd_data_reg[196] ),\n .\\not_strict_mode.app_rd_data_reg[197] (\\not_strict_mode.app_rd_data_reg[197] ),\n .\\not_strict_mode.app_rd_data_reg[198] (\\not_strict_mode.app_rd_data_reg[198] ),\n .\\not_strict_mode.app_rd_data_reg[199] (\\not_strict_mode.app_rd_data_reg[199] ),\n .\\not_strict_mode.app_rd_data_reg[19] (\\not_strict_mode.app_rd_data_reg[19] ),\n .\\not_strict_mode.app_rd_data_reg[1] (\\not_strict_mode.app_rd_data_reg[1] ),\n .\\not_strict_mode.app_rd_data_reg[200] (\\not_strict_mode.app_rd_data_reg[200] ),\n .\\not_strict_mode.app_rd_data_reg[201] (\\not_strict_mode.app_rd_data_reg[201] ),\n .\\not_strict_mode.app_rd_data_reg[202] (\\not_strict_mode.app_rd_data_reg[202] ),\n .\\not_strict_mode.app_rd_data_reg[203] (\\not_strict_mode.app_rd_data_reg[203] ),\n .\\not_strict_mode.app_rd_data_reg[204] (\\not_strict_mode.app_rd_data_reg[204] ),\n .\\not_strict_mode.app_rd_data_reg[205] (\\not_strict_mode.app_rd_data_reg[205] ),\n .\\not_strict_mode.app_rd_data_reg[206] (\\not_strict_mode.app_rd_data_reg[206] ),\n .\\not_strict_mode.app_rd_data_reg[207] (\\not_strict_mode.app_rd_data_reg[207] ),\n .\\not_strict_mode.app_rd_data_reg[208] (\\not_strict_mode.app_rd_data_reg[208] ),\n .\\not_strict_mode.app_rd_data_reg[209] (\\not_strict_mode.app_rd_data_reg[209] ),\n .\\not_strict_mode.app_rd_data_reg[20] (\\not_strict_mode.app_rd_data_reg[20] ),\n .\\not_strict_mode.app_rd_data_reg[210] (\\not_strict_mode.app_rd_data_reg[210] ),\n .\\not_strict_mode.app_rd_data_reg[211] (\\not_strict_mode.app_rd_data_reg[211] ),\n .\\not_strict_mode.app_rd_data_reg[212] (\\not_strict_mode.app_rd_data_reg[212] ),\n .\\not_strict_mode.app_rd_data_reg[213] (\\not_strict_mode.app_rd_data_reg[213] ),\n .\\not_strict_mode.app_rd_data_reg[214] (\\not_strict_mode.app_rd_data_reg[214] ),\n .\\not_strict_mode.app_rd_data_reg[215] (\\not_strict_mode.app_rd_data_reg[215] ),\n .\\not_strict_mode.app_rd_data_reg[216] (\\not_strict_mode.app_rd_data_reg[216] ),\n .\\not_strict_mode.app_rd_data_reg[217] (\\not_strict_mode.app_rd_data_reg[217] ),\n .\\not_strict_mode.app_rd_data_reg[218] (\\not_strict_mode.app_rd_data_reg[218] ),\n .\\not_strict_mode.app_rd_data_reg[219] (\\not_strict_mode.app_rd_data_reg[219] ),\n .\\not_strict_mode.app_rd_data_reg[21] (\\not_strict_mode.app_rd_data_reg[21] ),\n .\\not_strict_mode.app_rd_data_reg[220] (\\not_strict_mode.app_rd_data_reg[220] ),\n .\\not_strict_mode.app_rd_data_reg[221] (\\not_strict_mode.app_rd_data_reg[221] ),\n .\\not_strict_mode.app_rd_data_reg[222] (\\not_strict_mode.app_rd_data_reg[222] ),\n .\\not_strict_mode.app_rd_data_reg[223] (\\not_strict_mode.app_rd_data_reg[223] ),\n .\\not_strict_mode.app_rd_data_reg[224] (\\not_strict_mode.app_rd_data_reg[224] ),\n .\\not_strict_mode.app_rd_data_reg[225] (\\not_strict_mode.app_rd_data_reg[225] ),\n .\\not_strict_mode.app_rd_data_reg[226] (\\not_strict_mode.app_rd_data_reg[226] ),\n .\\not_strict_mode.app_rd_data_reg[227] (\\not_strict_mode.app_rd_data_reg[227] ),\n .\\not_strict_mode.app_rd_data_reg[228] (\\not_strict_mode.app_rd_data_reg[228] ),\n .\\not_strict_mode.app_rd_data_reg[228]_0 (\\not_strict_mode.app_rd_data_reg[228]_0 ),\n .\\not_strict_mode.app_rd_data_reg[229] (\\not_strict_mode.app_rd_data_reg[229] ),\n .\\not_strict_mode.app_rd_data_reg[22] (\\not_strict_mode.app_rd_data_reg[22] ),\n .\\not_strict_mode.app_rd_data_reg[230] (\\not_strict_mode.app_rd_data_reg[230] ),\n .\\not_strict_mode.app_rd_data_reg[231] (\\not_strict_mode.app_rd_data_reg[231] ),\n .\\not_strict_mode.app_rd_data_reg[232] (\\not_strict_mode.app_rd_data_reg[232] ),\n .\\not_strict_mode.app_rd_data_reg[233] (\\not_strict_mode.app_rd_data_reg[233] ),\n .\\not_strict_mode.app_rd_data_reg[234] (\\not_strict_mode.app_rd_data_reg[234] ),\n .\\not_strict_mode.app_rd_data_reg[235] (\\not_strict_mode.app_rd_data_reg[235] ),\n .\\not_strict_mode.app_rd_data_reg[236] (\\not_strict_mode.app_rd_data_reg[236] ),\n .\\not_strict_mode.app_rd_data_reg[236]_0 (\\not_strict_mode.app_rd_data_reg[236]_0 ),\n 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(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ),\n .\\not_strict_mode.status_ram.rd_buf_we_r1_reg (\\not_strict_mode.status_ram.rd_buf_we_r1_reg ),\n .of_ctl_full_v(of_ctl_full_v),\n .ofs_rdy_r_reg(ofs_rdy_r_reg),\n .ofs_rdy_r_reg_0(ofs_rdy_r_reg_0),\n .out(out),\n .p_0_out(p_0_out),\n .phy_ctl_wr_i2(phy_ctl_wr_i2),\n .phy_dout(phy_dout),\n .phy_if_empty_r_reg(phy_if_empty_r_reg),\n .phy_if_reset(phy_if_reset),\n .phy_mc_ctl_full(phy_mc_ctl_full),\n .phy_rddata_en(phy_rddata_en),\n .phy_read_calib(phy_read_calib),\n .phy_write_calib(phy_write_calib),\n .\\pi_dqs_found_lanes_r1_reg[3] (\\pi_dqs_found_lanes_r1_reg[3] ),\n .pi_en_stg2_f_reg(pi_en_stg2_f_reg),\n .pi_en_stg2_f_reg_0(pi_en_stg2_f_reg_0),\n .pi_en_stg2_f_reg_1(pi_en_stg2_f_reg_1),\n .pi_en_stg2_f_reg_2(pi_en_stg2_f_reg_2),\n .pi_phase_locked_all_r1_reg(pi_phase_locked_all_r1_reg),\n .\\pi_rdval_cnt_reg[5] (\\pi_rdval_cnt_reg[5] ),\n .pi_stg2_f_incdec_reg(pi_stg2_f_incdec_reg),\n .pi_stg2_f_incdec_reg_0(pi_stg2_f_incdec_reg_0),\n .pi_stg2_f_incdec_reg_1(pi_stg2_f_incdec_reg_1),\n .pi_stg2_f_incdec_reg_2(pi_stg2_f_incdec_reg_2),\n .pll_locked(pll_locked),\n .\\po_counter_read_val_r_reg[5] (\\po_counter_read_val_r_reg[5] ),\n .\\po_rdval_cnt_reg[8] (\\po_rdval_cnt_reg[8] ),\n .\\po_rdval_cnt_reg[8]_0 (\\po_rdval_cnt_reg[8]_0 ),\n .\\po_stg2_wrcal_cnt_reg[1] (\\po_stg2_wrcal_cnt_reg[1] ),\n .prbs_rdlvl_start_reg(prbs_rdlvl_start_reg),\n .ram_init_done_r(ram_init_done_r),\n .rd_buf_we(rd_buf_we),\n .\\rd_mux_sel_r_reg[1] (\\rd_mux_sel_r_reg[1] ),\n .\\rd_ptr_reg[3] (\\rd_ptr_reg[3] ),\n .\\rd_ptr_reg[3]_0 (\\rd_ptr_reg[3]_0 ),\n .\\rd_ptr_timing_reg[2] (\\rd_ptr_timing_reg[2] ),\n .\\rd_ptr_timing_reg[2]_0 (\\rd_ptr_timing_reg[2]_0 ),\n .\\rd_ptr_timing_reg[2]_1 (\\rd_ptr_timing_reg[2]_1 ),\n .\\rd_ptr_timing_reg[2]_10 (\\rd_ptr_timing_reg[2]_10 ),\n .\\rd_ptr_timing_reg[2]_2 (\\rd_ptr_timing_reg[2]_2 ),\n .\\rd_ptr_timing_reg[2]_3 (\\rd_ptr_timing_reg[2]_3 ),\n .\\rd_ptr_timing_reg[2]_4 (\\rd_ptr_timing_reg[2]_4 ),\n .\\rd_ptr_timing_reg[2]_5 (\\rd_ptr_timing_reg[2]_5 ),\n .\\rd_ptr_timing_reg[2]_6 (\\rd_ptr_timing_reg[2]_6 ),\n .\\rd_ptr_timing_reg[2]_7 (\\rd_ptr_timing_reg[2]_7 ),\n .\\rd_ptr_timing_reg[2]_8 (\\rd_ptr_timing_reg[2]_8 ),\n .\\rd_ptr_timing_reg[2]_9 (\\rd_ptr_timing_reg[2]_9 ),\n .\\read_fifo.fifo_out_data_r_reg[6] (\\read_fifo.fifo_out_data_r_reg[6] ),\n .\\read_fifo.fifo_out_data_r_reg[6]_0 (\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .\\read_fifo.tail_r_reg[0] (\\read_fifo.tail_r_reg[0] ),\n .\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] (\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .rst_sync_r1_reg(rst_sync_r1_reg),\n .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9),\n .sync_pulse(sync_pulse),\n .sys_rst(sys_rst),\n .tail_r(tail_r),\n .wr_en(wr_en),\n .wr_en_5(wr_en_5),\n .wr_en_6(wr_en_6),\n .\\wr_ptr_timing_reg[2] (\\wr_ptr_timing_reg[2] ),\n .\\wr_ptr_timing_reg[2]_0 (\\wr_ptr_timing_reg[2]_0 ),\n .\\wr_ptr_timing_reg[2]_1 (\\wr_ptr_timing_reg[2]_1 ),\n .\\write_buffer.wr_buf_out_data_reg[224] (\\write_buffer.wr_buf_out_data_reg[224] ),\n .\\write_buffer.wr_buf_out_data_reg[225] (\\write_buffer.wr_buf_out_data_reg[225] ),\n .\\write_buffer.wr_buf_out_data_reg[226] (\\write_buffer.wr_buf_out_data_reg[226] ),\n .\\write_buffer.wr_buf_out_data_reg[227] (\\write_buffer.wr_buf_out_data_reg[227] ),\n .\\write_buffer.wr_buf_out_data_reg[228] (\\write_buffer.wr_buf_out_data_reg[228] ),\n .\\write_buffer.wr_buf_out_data_reg[229] (\\write_buffer.wr_buf_out_data_reg[229] ),\n .\\write_buffer.wr_buf_out_data_reg[230] (\\write_buffer.wr_buf_out_data_reg[230] ),\n .\\write_buffer.wr_buf_out_data_reg[231] (\\write_buffer.wr_buf_out_data_reg[231] ),\n .\\write_buffer.wr_buf_out_data_reg[232] (\\write_buffer.wr_buf_out_data_reg[232] ),\n .\\write_buffer.wr_buf_out_data_reg[233] (\\write_buffer.wr_buf_out_data_reg[233] ),\n .\\write_buffer.wr_buf_out_data_reg[234] (\\write_buffer.wr_buf_out_data_reg[234] ),\n .\\write_buffer.wr_buf_out_data_reg[235] (\\write_buffer.wr_buf_out_data_reg[235] ),\n .\\write_buffer.wr_buf_out_data_reg[236] (\\write_buffer.wr_buf_out_data_reg[236] ),\n .\\write_buffer.wr_buf_out_data_reg[237] (\\write_buffer.wr_buf_out_data_reg[237] ),\n .\\write_buffer.wr_buf_out_data_reg[238] (\\write_buffer.wr_buf_out_data_reg[238] ),\n .\\write_buffer.wr_buf_out_data_reg[239] (\\write_buffer.wr_buf_out_data_reg[239] ),\n .\\write_buffer.wr_buf_out_data_reg[240] (\\write_buffer.wr_buf_out_data_reg[240] ),\n .\\write_buffer.wr_buf_out_data_reg[241] (\\write_buffer.wr_buf_out_data_reg[241] ),\n .\\write_buffer.wr_buf_out_data_reg[242] (\\write_buffer.wr_buf_out_data_reg[242] ),\n .\\write_buffer.wr_buf_out_data_reg[243] (\\write_buffer.wr_buf_out_data_reg[243] ),\n .\\write_buffer.wr_buf_out_data_reg[244] (\\write_buffer.wr_buf_out_data_reg[244] ),\n .\\write_buffer.wr_buf_out_data_reg[245] (\\write_buffer.wr_buf_out_data_reg[245] ),\n .\\write_buffer.wr_buf_out_data_reg[246] (\\write_buffer.wr_buf_out_data_reg[246] ),\n .\\write_buffer.wr_buf_out_data_reg[247] (\\write_buffer.wr_buf_out_data_reg[247] ),\n .\\write_buffer.wr_buf_out_data_reg[248] (\\write_buffer.wr_buf_out_data_reg[248] ),\n .\\write_buffer.wr_buf_out_data_reg[249] (\\write_buffer.wr_buf_out_data_reg[249] ),\n .\\write_buffer.wr_buf_out_data_reg[250] (\\write_buffer.wr_buf_out_data_reg[250] ),\n .\\write_buffer.wr_buf_out_data_reg[251] (\\write_buffer.wr_buf_out_data_reg[251] ),\n .\\write_buffer.wr_buf_out_data_reg[252] (\\write_buffer.wr_buf_out_data_reg[252] ),\n .\\write_buffer.wr_buf_out_data_reg[253] (\\write_buffer.wr_buf_out_data_reg[253] ),\n .\\write_buffer.wr_buf_out_data_reg[254] (\\write_buffer.wr_buf_out_data_reg[254] ),\n .\\write_buffer.wr_buf_out_data_reg[255] (\\write_buffer.wr_buf_out_data_reg[255] ),\n .\\write_buffer.wr_buf_out_data_reg[287] (Q));\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* box_type = \"PRIMITIVE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n u_ras_n_obuf\n (.I(mem_dq_out[75]),\n .O(ddr3_ras_n));\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* box_type = \"PRIMITIVE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n u_we_n_obuf\n (.I(mem_dq_out[49]),\n .O(ddr3_we_n));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_of_pre_fifo\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo\n (SR,\n CLK);\n input [0:0]SR;\n input CLK;\n\n wire CLK;\n wire [0:0]SR;\n (* MAX_FANOUT = \"50\" *) (* RTL_KEEP = \"true\" *) (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) wire [2:0]rd_ptr_timing;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) wire wr_en;\n (* MAX_FANOUT = \"50\" *) (* RTL_KEEP = \"true\" *) (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) wire [2:0]wr_ptr_timing;\n\n LUT1 #(\n .INIT(2'h2)) \n i_0\n (.I0(1'b0),\n .O(wr_en));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[0] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b1),\n .Q(rd_ptr_timing[0]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[1] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b0),\n .Q(rd_ptr_timing[1]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[2] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b0),\n .Q(rd_ptr_timing[2]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[0] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b1),\n .Q(wr_ptr_timing[0]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[1] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b0),\n .Q(wr_ptr_timing[1]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[2] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b0),\n .Q(wr_ptr_timing[2]),\n .R(SR));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_of_pre_fifo\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized0\n (SR,\n CLK);\n input [0:0]SR;\n input CLK;\n\n wire CLK;\n wire [0:0]SR;\n (* MAX_FANOUT = \"50\" *) (* RTL_KEEP = \"true\" *) (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) wire [2:0]rd_ptr_timing;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) wire wr_en;\n (* MAX_FANOUT = \"50\" *) (* RTL_KEEP = \"true\" *) (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) wire [2:0]wr_ptr_timing;\n\n LUT1 #(\n .INIT(2'h2)) \n i_0\n (.I0(1'b0),\n .O(wr_en));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[0] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b1),\n .Q(rd_ptr_timing[0]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[1] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b0),\n .Q(rd_ptr_timing[1]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[2] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b0),\n .Q(rd_ptr_timing[2]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[0] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b1),\n .Q(wr_ptr_timing[0]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[1] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b0),\n .Q(wr_ptr_timing[1]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[2] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b0),\n .Q(wr_ptr_timing[2]),\n .R(SR));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_of_pre_fifo\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized1\n (SR,\n CLK);\n input [0:0]SR;\n input CLK;\n\n wire CLK;\n wire [0:0]SR;\n (* MAX_FANOUT = \"50\" *) (* RTL_KEEP = \"true\" *) (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) wire [2:0]rd_ptr_timing;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) wire wr_en;\n (* MAX_FANOUT = \"50\" *) (* RTL_KEEP = \"true\" *) (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) wire [2:0]wr_ptr_timing;\n\n LUT1 #(\n .INIT(2'h2)) \n i_0\n (.I0(1'b0),\n .O(wr_en));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[0] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b1),\n .Q(rd_ptr_timing[0]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[1] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b0),\n .Q(rd_ptr_timing[1]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[2] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b0),\n .Q(rd_ptr_timing[2]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[0] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b1),\n .Q(wr_ptr_timing[0]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[1] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b0),\n .Q(wr_ptr_timing[1]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[2] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b0),\n .Q(wr_ptr_timing[2]),\n .R(SR));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_of_pre_fifo\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized2\n (\\my_empty_reg[7]_0 ,\n \\my_empty_reg[1]_0 ,\n D8,\n D9,\n \\my_empty_reg[7]_1 ,\n Q,\n ofifo_rst,\n CLK,\n ofifo_rst_reg,\n mux_wrdata_en,\n init_calib_complete_reg_rep,\n \\write_buffer.wr_buf_out_data_reg[287] ,\n phy_dout);\n output \\my_empty_reg[7]_0 ;\n output \\my_empty_reg[1]_0 ;\n output [7:0]D8;\n output [7:0]D9;\n output [63:0]\\my_empty_reg[7]_1 ;\n output [2:0]Q;\n input ofifo_rst;\n input CLK;\n input ofifo_rst_reg;\n input mux_wrdata_en;\n input init_calib_complete_reg_rep;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[287] ;\n input [71:0]phy_dout;\n\n wire CLK;\n wire [7:0]D8;\n wire [7:0]D9;\n wire [2:0]Q;\n wire \\entry_cnt[0]_i_1_n_0 ;\n wire \\entry_cnt[1]_i_1_n_0 ;\n wire \\entry_cnt[2]_i_1_n_0 ;\n wire \\entry_cnt[3]_i_1_n_0 ;\n wire \\entry_cnt[4]_i_1_n_0 ;\n wire \\entry_cnt[4]_i_2_n_0 ;\n wire \\entry_cnt[4]_i_3_n_0 ;\n wire \\entry_cnt_reg_n_0_[0] ;\n wire \\entry_cnt_reg_n_0_[1] ;\n wire init_calib_complete_reg_rep;\n wire mem_reg_0_15_60_65_n_4;\n wire mem_reg_0_15_60_65_n_5;\n wire mem_reg_0_15_66_71_n_0;\n wire mem_reg_0_15_66_71_n_1;\n wire mem_reg_0_15_66_71_n_2;\n wire mem_reg_0_15_66_71_n_3;\n wire mem_reg_0_15_66_71_n_4;\n wire mem_reg_0_15_66_71_n_5;\n wire mem_reg_0_15_72_77_n_0;\n wire mem_reg_0_15_72_77_n_1;\n wire mem_reg_0_15_72_77_n_2;\n wire mem_reg_0_15_72_77_n_3;\n wire mem_reg_0_15_72_77_n_4;\n wire mem_reg_0_15_72_77_n_5;\n wire mem_reg_0_15_78_79_n_0;\n wire mem_reg_0_15_78_79_n_1;\n wire mux_wrdata_en;\n wire my_empty0;\n wire \\my_empty[1]_i_1__0_n_0 ;\n wire \\my_empty[7]_i_1__0_n_0 ;\n wire \\my_empty[7]_i_3__0_n_0 ;\n wire \\my_empty[7]_i_4__0_n_0 ;\n wire \\my_empty_reg[1]_0 ;\n wire \\my_empty_reg[7]_0 ;\n wire [63:0]\\my_empty_reg[7]_1 ;\n wire \\my_empty_reg_n_0_[7] ;\n wire my_full0;\n wire \\my_full[4]_i_1_n_0 ;\n wire \\my_full[4]_i_3__0_n_0 ;\n wire \\my_full[4]_i_4__0_n_0 ;\n wire \\my_full_reg_n_0_[4] ;\n wire [3:0]nxt_rd_ptr;\n wire [3:0]nxt_wr_ptr;\n wire ofifo_rst;\n wire ofifo_rst_reg;\n wire [71:0]phy_dout;\n wire \\rd_ptr_reg_n_0_[0] ;\n wire \\rd_ptr_reg_n_0_[1] ;\n wire \\rd_ptr_reg_n_0_[2] ;\n wire \\rd_ptr_reg_n_0_[3] ;\n wire [3:0]rd_ptr_timing;\n wire \\rd_ptr_timing[3]_i_1__0_n_0 ;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) wire wr_en;\n wire [3:0]wr_ptr;\n wire wr_ptr0;\n wire [3:0]wr_ptr_timing;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[287] ;\n wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED;\n\n (* SOFT_HLUTNM = \"soft_lutpair769\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\entry_cnt[0]_i_1 \n (.I0(\\entry_cnt_reg_n_0_[0] ),\n .O(\\entry_cnt[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair766\" *) \n LUT5 #(\n .INIT(32'hAA6A5595)) \n \\entry_cnt[1]_i_1 \n (.I0(\\entry_cnt_reg_n_0_[0] ),\n .I1(ofifo_rst_reg),\n .I2(mux_wrdata_en),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(\\entry_cnt_reg_n_0_[1] ),\n .O(\\entry_cnt[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFF7F0080AAEA5515)) \n \\entry_cnt[2]_i_1 \n (.I0(\\entry_cnt_reg_n_0_[0] ),\n .I1(ofifo_rst_reg),\n .I2(mux_wrdata_en),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(Q[0]),\n .I5(\\entry_cnt_reg_n_0_[1] ),\n .O(\\entry_cnt[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair769\" *) \n LUT5 #(\n .INIT(32'h7F80FE01)) \n \\entry_cnt[3]_i_1 \n (.I0(\\entry_cnt[4]_i_3_n_0 ),\n .I1(\\entry_cnt_reg_n_0_[0] ),\n .I2(\\entry_cnt_reg_n_0_[1] ),\n .I3(Q[1]),\n .I4(Q[0]),\n .O(\\entry_cnt[3]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h5003)) \n \\entry_cnt[4]_i_1 \n (.I0(\\my_full_reg_n_0_[4] ),\n .I1(\\my_empty_reg_n_0_[7] ),\n .I2(mux_wrdata_en),\n .I3(ofifo_rst_reg),\n .O(\\entry_cnt[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h7FFF8000FFFE0001)) \n \\entry_cnt[4]_i_2 \n (.I0(\\entry_cnt_reg_n_0_[1] ),\n .I1(\\entry_cnt_reg_n_0_[0] ),\n .I2(\\entry_cnt[4]_i_3_n_0 ),\n .I3(Q[0]),\n .I4(Q[2]),\n .I5(Q[1]),\n .O(\\entry_cnt[4]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair766\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\entry_cnt[4]_i_3 \n (.I0(ofifo_rst_reg),\n .I1(mux_wrdata_en),\n .I2(\\my_full_reg_n_0_[4] ),\n .O(\\entry_cnt[4]_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\entry_cnt_reg[0] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1_n_0 ),\n .D(\\entry_cnt[0]_i_1_n_0 ),\n .Q(\\entry_cnt_reg_n_0_[0] ),\n .R(ofifo_rst));\n FDRE #(\n .INIT(1'b0)) \n \\entry_cnt_reg[1] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1_n_0 ),\n .D(\\entry_cnt[1]_i_1_n_0 ),\n .Q(\\entry_cnt_reg_n_0_[1] ),\n .R(ofifo_rst));\n FDRE #(\n .INIT(1'b0)) \n \\entry_cnt_reg[2] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1_n_0 ),\n .D(\\entry_cnt[2]_i_1_n_0 ),\n .Q(Q[0]),\n .R(ofifo_rst));\n FDRE #(\n .INIT(1'b0)) \n \\entry_cnt_reg[3] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1_n_0 ),\n .D(\\entry_cnt[3]_i_1_n_0 ),\n .Q(Q[1]),\n .R(ofifo_rst));\n FDRE #(\n .INIT(1'b0)) \n \\entry_cnt_reg[4] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1_n_0 ),\n .D(\\entry_cnt[4]_i_2_n_0 ),\n .Q(Q[2]),\n .R(ofifo_rst));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_0_5\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[1:0]),\n .DIB(phy_dout[3:2]),\n .DIC(phy_dout[5:4]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [1:0]),\n .DOB(\\my_empty_reg[7]_1 [3:2]),\n .DOC(\\my_empty_reg[7]_1 [5:4]),\n .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n LUT4 #(\n .INIT(16'h082A)) \n mem_reg_0_15_0_5_i_1__0\n (.I0(mux_wrdata_en),\n .I1(ofifo_rst_reg),\n .I2(\\my_full_reg_n_0_[4] ),\n .I3(\\my_empty_reg[1]_0 ),\n .O(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_12_17\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[13:12]),\n .DIB(phy_dout[15:14]),\n .DIC(phy_dout[17:16]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [13:12]),\n .DOB(\\my_empty_reg[7]_1 [15:14]),\n .DOC(\\my_empty_reg[7]_1 [17:16]),\n .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_18_23\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[19:18]),\n .DIB(phy_dout[21:20]),\n .DIC(phy_dout[23:22]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [19:18]),\n .DOB(\\my_empty_reg[7]_1 [21:20]),\n .DOC(\\my_empty_reg[7]_1 [23:22]),\n .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_24_29\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[25:24]),\n .DIB(phy_dout[27:26]),\n .DIC(phy_dout[29:28]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [25:24]),\n .DOB(\\my_empty_reg[7]_1 [27:26]),\n .DOC(\\my_empty_reg[7]_1 [29:28]),\n .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_30_35\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[31:30]),\n .DIB(phy_dout[33:32]),\n .DIC(phy_dout[35:34]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [31:30]),\n .DOB(\\my_empty_reg[7]_1 [33:32]),\n .DOC(\\my_empty_reg[7]_1 [35:34]),\n .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_36_41\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[37:36]),\n .DIB(phy_dout[39:38]),\n .DIC(phy_dout[41:40]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [37:36]),\n .DOB(\\my_empty_reg[7]_1 [39:38]),\n .DOC(\\my_empty_reg[7]_1 [41:40]),\n .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_42_47\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[43:42]),\n .DIB(phy_dout[45:44]),\n .DIC(phy_dout[47:46]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [43:42]),\n .DOB(\\my_empty_reg[7]_1 [45:44]),\n .DOC(\\my_empty_reg[7]_1 [47:46]),\n .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_48_53\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[49:48]),\n .DIB(phy_dout[51:50]),\n .DIC(phy_dout[53:52]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [49:48]),\n .DOB(\\my_empty_reg[7]_1 [51:50]),\n .DOC(\\my_empty_reg[7]_1 [53:52]),\n .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_54_59\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[55:54]),\n .DIB(phy_dout[57:56]),\n .DIC(phy_dout[59:58]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [55:54]),\n .DOB(\\my_empty_reg[7]_1 [57:56]),\n .DOC(\\my_empty_reg[7]_1 [59:58]),\n .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_60_65\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[61:60]),\n .DIB(phy_dout[63:62]),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [61:60]),\n .DOB(\\my_empty_reg[7]_1 [63:62]),\n .DOC({mem_reg_0_15_60_65_n_4,mem_reg_0_15_60_65_n_5}),\n .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_66_71\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA({1'b0,1'b0}),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_15_66_71_n_0,mem_reg_0_15_66_71_n_1}),\n .DOB({mem_reg_0_15_66_71_n_2,mem_reg_0_15_66_71_n_3}),\n .DOC({mem_reg_0_15_66_71_n_4,mem_reg_0_15_66_71_n_5}),\n .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_6_11\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[7:6]),\n .DIB(phy_dout[9:8]),\n .DIC(phy_dout[11:10]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [7:6]),\n .DOB(\\my_empty_reg[7]_1 [9:8]),\n .DOC(\\my_empty_reg[7]_1 [11:10]),\n .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_72_77\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[65:64]),\n .DIB(phy_dout[67:66]),\n .DIC(phy_dout[69:68]),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_15_72_77_n_0,mem_reg_0_15_72_77_n_1}),\n .DOB({mem_reg_0_15_72_77_n_2,mem_reg_0_15_72_77_n_3}),\n .DOC({mem_reg_0_15_72_77_n_4,mem_reg_0_15_72_77_n_5}),\n .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_78_79\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[71:70]),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_15_78_79_n_0,mem_reg_0_15_78_79_n_1}),\n .DOB(NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED[1:0]),\n .DOC(NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED[1:0]),\n .DOD(NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n LUT6 #(\n .INIT(64'hFFFFFFFFF071F070)) \n \\my_empty[1]_i_1__0 \n (.I0(mux_wrdata_en),\n .I1(ofifo_rst_reg),\n .I2(\\my_empty_reg[1]_0 ),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(my_empty0),\n .I5(ofifo_rst),\n .O(\\my_empty[1]_i_1__0_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFF071F070)) \n \\my_empty[7]_i_1__0 \n (.I0(mux_wrdata_en),\n .I1(ofifo_rst_reg),\n .I2(\\my_empty_reg_n_0_[7] ),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(my_empty0),\n .I5(ofifo_rst),\n .O(\\my_empty[7]_i_1__0_n_0 ));\n LUT5 #(\n .INIT(32'h4A400D08)) \n \\my_empty[7]_i_2__0 \n (.I0(wr_ptr_timing[2]),\n .I1(\\my_empty[7]_i_3__0_n_0 ),\n .I2(wr_ptr_timing[3]),\n .I3(\\my_empty[7]_i_4__0_n_0 ),\n .I4(\\rd_ptr_reg_n_0_[2] ),\n .O(my_empty0));\n (* SOFT_HLUTNM = \"soft_lutpair768\" *) \n LUT5 #(\n .INIT(32'h00000040)) \n \\my_empty[7]_i_3__0 \n (.I0(wr_ptr_timing[1]),\n .I1(\\rd_ptr_reg_n_0_[0] ),\n .I2(\\rd_ptr_reg_n_0_[1] ),\n .I3(\\rd_ptr_reg_n_0_[3] ),\n .I4(wr_ptr_timing[0]),\n .O(\\my_empty[7]_i_3__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair768\" *) \n LUT5 #(\n .INIT(32'h84210842)) \n \\my_empty[7]_i_4__0 \n (.I0(wr_ptr_timing[0]),\n .I1(wr_ptr_timing[1]),\n .I2(\\rd_ptr_reg_n_0_[0] ),\n .I3(\\rd_ptr_reg_n_0_[1] ),\n .I4(\\rd_ptr_reg_n_0_[3] ),\n .O(\\my_empty[7]_i_4__0_n_0 ));\n (* syn_maxfan = \"3\" *) \n FDRE #(\n .INIT(1'b0)) \n \\my_empty_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_empty[1]_i_1__0_n_0 ),\n .Q(\\my_empty_reg[1]_0 ),\n .R(1'b0));\n (* syn_maxfan = \"3\" *) \n FDRE #(\n .INIT(1'b0)) \n \\my_empty_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_empty[7]_i_1__0_n_0 ),\n .Q(\\my_empty_reg_n_0_[7] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000FF00FC80)) \n \\my_full[4]_i_1 \n (.I0(my_full0),\n .I1(mux_wrdata_en),\n .I2(ofifo_rst_reg),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(\\my_empty_reg_n_0_[7] ),\n .I5(ofifo_rst),\n .O(\\my_full[4]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h4A400D08)) \n \\my_full[4]_i_2__0 \n (.I0(rd_ptr_timing[2]),\n .I1(\\my_full[4]_i_3__0_n_0 ),\n .I2(rd_ptr_timing[3]),\n .I3(\\my_full[4]_i_4__0_n_0 ),\n .I4(wr_ptr[2]),\n .O(my_full0));\n (* SOFT_HLUTNM = \"soft_lutpair767\" *) \n LUT5 #(\n .INIT(32'h00000040)) \n \\my_full[4]_i_3__0 \n (.I0(rd_ptr_timing[1]),\n .I1(wr_ptr[0]),\n .I2(wr_ptr[1]),\n .I3(wr_ptr[3]),\n .I4(rd_ptr_timing[0]),\n .O(\\my_full[4]_i_3__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair767\" *) \n LUT5 #(\n .INIT(32'h84210842)) \n \\my_full[4]_i_4__0 \n (.I0(rd_ptr_timing[0]),\n .I1(rd_ptr_timing[1]),\n .I2(wr_ptr[0]),\n .I3(wr_ptr[1]),\n .I4(wr_ptr[3]),\n .O(\\my_full[4]_i_4__0_n_0 ));\n (* syn_maxfan = \"3\" *) \n FDRE #(\n .INIT(1'b0)) \n \\my_full_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_full[4]_i_1_n_0 ),\n .Q(\\my_full_reg_n_0_[4] ),\n .R(1'b0));\n LUT3 #(\n .INIT(8'h0D)) \n out_fifo_i_1__3\n (.I0(\\my_empty_reg[1]_0 ),\n .I1(mux_wrdata_en),\n .I2(ofifo_rst_reg),\n .O(\\my_empty_reg[7]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair775\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_66__0\n (.I0(mem_reg_0_15_66_71_n_4),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D8[7]));\n (* SOFT_HLUTNM = \"soft_lutpair772\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_67__0\n (.I0(mem_reg_0_15_66_71_n_5),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D8[6]));\n (* SOFT_HLUTNM = \"soft_lutpair774\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_68__1\n (.I0(mem_reg_0_15_66_71_n_2),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D8[5]));\n (* SOFT_HLUTNM = \"soft_lutpair770\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_69__1\n (.I0(mem_reg_0_15_66_71_n_3),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D8[4]));\n (* SOFT_HLUTNM = \"soft_lutpair778\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_70\n (.I0(mem_reg_0_15_66_71_n_0),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D8[3]));\n (* SOFT_HLUTNM = \"soft_lutpair771\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_71\n (.I0(mem_reg_0_15_66_71_n_1),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D8[2]));\n (* SOFT_HLUTNM = \"soft_lutpair779\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_72\n (.I0(mem_reg_0_15_60_65_n_4),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D8[1]));\n (* SOFT_HLUTNM = \"soft_lutpair773\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_73\n (.I0(mem_reg_0_15_60_65_n_5),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D8[0]));\n (* SOFT_HLUTNM = \"soft_lutpair772\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_74__3\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[287] [7]),\n .I2(mem_reg_0_15_78_79_n_0),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[7]));\n (* SOFT_HLUTNM = \"soft_lutpair775\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_75__3\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[287] [6]),\n .I2(mem_reg_0_15_78_79_n_1),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[6]));\n (* SOFT_HLUTNM = \"soft_lutpair773\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_76__3\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[287] [5]),\n .I2(mem_reg_0_15_72_77_n_4),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[5]));\n (* SOFT_HLUTNM = \"soft_lutpair771\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_77__3\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[287] [4]),\n .I2(mem_reg_0_15_72_77_n_5),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[4]));\n (* SOFT_HLUTNM = \"soft_lutpair774\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_78__3\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[287] [3]),\n .I2(mem_reg_0_15_72_77_n_2),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[3]));\n (* SOFT_HLUTNM = \"soft_lutpair778\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_79__2\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[287] [2]),\n .I2(mem_reg_0_15_72_77_n_3),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[2]));\n (* SOFT_HLUTNM = \"soft_lutpair770\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_80__2\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[287] [1]),\n .I2(mem_reg_0_15_72_77_n_0),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[1]));\n (* SOFT_HLUTNM = \"soft_lutpair779\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_81__2\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[287] [0]),\n .I2(mem_reg_0_15_72_77_n_1),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[0]));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[0] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__0_n_0 ),\n .D(nxt_rd_ptr[0]),\n .Q(\\rd_ptr_reg_n_0_[0] ),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[1] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__0_n_0 ),\n .D(nxt_rd_ptr[1]),\n .Q(\\rd_ptr_reg_n_0_[1] ),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[2] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__0_n_0 ),\n .D(nxt_rd_ptr[2]),\n .Q(\\rd_ptr_reg_n_0_[2] ),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[3] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__0_n_0 ),\n .D(nxt_rd_ptr[3]),\n .Q(\\rd_ptr_reg_n_0_[3] ),\n .R(ofifo_rst));\n (* SOFT_HLUTNM = \"soft_lutpair780\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\rd_ptr_timing[0]_i_1__1 \n (.I0(\\rd_ptr_reg_n_0_[3] ),\n .I1(\\rd_ptr_reg_n_0_[0] ),\n .O(nxt_rd_ptr[0]));\n (* SOFT_HLUTNM = \"soft_lutpair780\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\rd_ptr_timing[1]_i_1__0 \n (.I0(\\rd_ptr_reg_n_0_[3] ),\n .I1(\\rd_ptr_reg_n_0_[0] ),\n .I2(\\rd_ptr_reg_n_0_[1] ),\n .O(nxt_rd_ptr[1]));\n (* SOFT_HLUTNM = \"soft_lutpair777\" *) \n LUT4 #(\n .INIT(16'hAA6A)) \n \\rd_ptr_timing[2]_i_1__0 \n (.I0(\\rd_ptr_reg_n_0_[2] ),\n .I1(\\rd_ptr_reg_n_0_[0] ),\n .I2(\\rd_ptr_reg_n_0_[1] ),\n .I3(\\rd_ptr_reg_n_0_[3] ),\n .O(nxt_rd_ptr[2]));\n LUT2 #(\n .INIT(4'h1)) \n \\rd_ptr_timing[3]_i_1__0 \n (.I0(\\my_empty_reg_n_0_[7] ),\n .I1(ofifo_rst_reg),\n .O(\\rd_ptr_timing[3]_i_1__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair777\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\rd_ptr_timing[3]_i_2__0 \n (.I0(\\rd_ptr_reg_n_0_[3] ),\n .I1(\\rd_ptr_reg_n_0_[1] ),\n .I2(\\rd_ptr_reg_n_0_[0] ),\n .I3(\\rd_ptr_reg_n_0_[2] ),\n .O(nxt_rd_ptr[3]));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[0] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__0_n_0 ),\n .D(nxt_rd_ptr[0]),\n .Q(rd_ptr_timing[0]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[1] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__0_n_0 ),\n .D(nxt_rd_ptr[1]),\n .Q(rd_ptr_timing[1]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[2] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__0_n_0 ),\n .D(nxt_rd_ptr[2]),\n .Q(rd_ptr_timing[2]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[3] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__0_n_0 ),\n .D(nxt_rd_ptr[3]),\n .Q(rd_ptr_timing[3]),\n .R(ofifo_rst));\n (* SOFT_HLUTNM = \"soft_lutpair781\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\wr_ptr[0]_i_1__3 \n (.I0(wr_ptr[3]),\n .I1(wr_ptr[0]),\n .O(nxt_wr_ptr[0]));\n (* SOFT_HLUTNM = \"soft_lutpair781\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\wr_ptr[1]_i_1__3 \n (.I0(wr_ptr[3]),\n .I1(wr_ptr[0]),\n .I2(wr_ptr[1]),\n .O(nxt_wr_ptr[1]));\n (* SOFT_HLUTNM = \"soft_lutpair776\" *) \n LUT4 #(\n .INIT(16'hAA6A)) \n \\wr_ptr[2]_i_1__2 \n (.I0(wr_ptr[2]),\n .I1(wr_ptr[0]),\n .I2(wr_ptr[1]),\n .I3(wr_ptr[3]),\n .O(nxt_wr_ptr[2]));\n LUT4 #(\n .INIT(16'h082A)) \n \\wr_ptr[3]_i_1__2 \n (.I0(mux_wrdata_en),\n .I1(ofifo_rst_reg),\n .I2(\\my_full_reg_n_0_[4] ),\n .I3(\\my_empty_reg_n_0_[7] ),\n .O(wr_ptr0));\n (* SOFT_HLUTNM = \"soft_lutpair776\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\wr_ptr[3]_i_2 \n (.I0(wr_ptr[3]),\n .I1(wr_ptr[1]),\n .I2(wr_ptr[0]),\n .I3(wr_ptr[2]),\n .O(nxt_wr_ptr[3]));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[0] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[0]),\n .Q(wr_ptr[0]),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[1] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[1]),\n .Q(wr_ptr[1]),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[2] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[2]),\n .Q(wr_ptr[2]),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[3] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[3]),\n .Q(wr_ptr[3]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[0] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[0]),\n .Q(wr_ptr_timing[0]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[1] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[1]),\n .Q(wr_ptr_timing[1]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[2] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[2]),\n .Q(wr_ptr_timing[2]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[3] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[3]),\n .Q(wr_ptr_timing[3]),\n .R(ofifo_rst));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_of_pre_fifo\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized3\n (\\my_empty_reg[7]_0 ,\n \\my_empty_reg[1]_0 ,\n D0,\n D9,\n \\my_empty_reg[7]_1 ,\n Q,\n ofifo_rst,\n CLK,\n ofifo_rst_reg,\n mux_wrdata_en,\n init_calib_complete_reg_rep,\n \\write_buffer.wr_buf_out_data_reg[286] ,\n phy_dout);\n output \\my_empty_reg[7]_0 ;\n output \\my_empty_reg[1]_0 ;\n output [7:0]D0;\n output [7:0]D9;\n output [63:0]\\my_empty_reg[7]_1 ;\n output [2:0]Q;\n input ofifo_rst;\n input CLK;\n input ofifo_rst_reg;\n input mux_wrdata_en;\n input init_calib_complete_reg_rep;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[286] ;\n input [71:0]phy_dout;\n\n wire CLK;\n wire [7:0]D0;\n wire [7:0]D9;\n wire [2:0]Q;\n wire \\entry_cnt[0]_i_1__0_n_0 ;\n wire \\entry_cnt[1]_i_1__0_n_0 ;\n wire \\entry_cnt[2]_i_1__0_n_0 ;\n wire \\entry_cnt[3]_i_1__0_n_0 ;\n wire \\entry_cnt[4]_i_1__0_n_0 ;\n wire \\entry_cnt[4]_i_2__0_n_0 ;\n wire \\entry_cnt[4]_i_3__0_n_0 ;\n wire \\entry_cnt_reg_n_0_[0] ;\n wire \\entry_cnt_reg_n_0_[1] ;\n wire init_calib_complete_reg_rep;\n wire mem_reg_0_15_0_5_n_0;\n wire mem_reg_0_15_0_5_n_1;\n wire mem_reg_0_15_0_5_n_2;\n wire mem_reg_0_15_0_5_n_3;\n wire mem_reg_0_15_0_5_n_4;\n wire mem_reg_0_15_0_5_n_5;\n wire mem_reg_0_15_6_11_n_0;\n wire mem_reg_0_15_6_11_n_1;\n wire mem_reg_0_15_72_77_n_0;\n wire mem_reg_0_15_72_77_n_1;\n wire mem_reg_0_15_72_77_n_2;\n wire mem_reg_0_15_72_77_n_3;\n wire mem_reg_0_15_72_77_n_4;\n wire mem_reg_0_15_72_77_n_5;\n wire mem_reg_0_15_78_79_n_0;\n wire mem_reg_0_15_78_79_n_1;\n wire mux_wrdata_en;\n wire my_empty0;\n wire \\my_empty[1]_i_1__1_n_0 ;\n wire \\my_empty[7]_i_1__1_n_0 ;\n wire \\my_empty[7]_i_3__1_n_0 ;\n wire \\my_empty[7]_i_4__1_n_0 ;\n wire \\my_empty_reg[1]_0 ;\n wire \\my_empty_reg[7]_0 ;\n wire [63:0]\\my_empty_reg[7]_1 ;\n wire \\my_empty_reg_n_0_[7] ;\n wire my_full0;\n wire \\my_full[4]_i_1__0_n_0 ;\n wire \\my_full[4]_i_3__1_n_0 ;\n wire \\my_full[4]_i_4__1_n_0 ;\n wire \\my_full_reg_n_0_[4] ;\n wire [3:0]nxt_rd_ptr;\n wire [3:0]nxt_wr_ptr;\n wire ofifo_rst;\n wire ofifo_rst_reg;\n wire [71:0]phy_dout;\n wire \\rd_ptr_reg_n_0_[0] ;\n wire \\rd_ptr_reg_n_0_[1] ;\n wire \\rd_ptr_reg_n_0_[2] ;\n wire \\rd_ptr_reg_n_0_[3] ;\n wire [3:0]rd_ptr_timing;\n wire \\rd_ptr_timing[3]_i_1__1_n_0 ;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) wire wr_en;\n wire [3:0]wr_ptr;\n wire wr_ptr0;\n wire [3:0]wr_ptr_timing;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[286] ;\n wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED;\n\n (* SOFT_HLUTNM = \"soft_lutpair820\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\entry_cnt[0]_i_1__0 \n (.I0(\\entry_cnt_reg_n_0_[0] ),\n .O(\\entry_cnt[0]_i_1__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair818\" *) \n LUT5 #(\n .INIT(32'hAA6A5595)) \n \\entry_cnt[1]_i_1__0 \n (.I0(\\entry_cnt_reg_n_0_[0] ),\n .I1(ofifo_rst_reg),\n .I2(mux_wrdata_en),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(\\entry_cnt_reg_n_0_[1] ),\n .O(\\entry_cnt[1]_i_1__0_n_0 ));\n LUT6 #(\n .INIT(64'hFF7F0080AAEA5515)) \n \\entry_cnt[2]_i_1__0 \n (.I0(\\entry_cnt_reg_n_0_[0] ),\n .I1(ofifo_rst_reg),\n .I2(mux_wrdata_en),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(Q[0]),\n .I5(\\entry_cnt_reg_n_0_[1] ),\n .O(\\entry_cnt[2]_i_1__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair820\" *) \n LUT5 #(\n .INIT(32'h7F80FE01)) \n \\entry_cnt[3]_i_1__0 \n (.I0(\\entry_cnt[4]_i_3__0_n_0 ),\n .I1(\\entry_cnt_reg_n_0_[0] ),\n .I2(\\entry_cnt_reg_n_0_[1] ),\n .I3(Q[1]),\n .I4(Q[0]),\n .O(\\entry_cnt[3]_i_1__0_n_0 ));\n LUT4 #(\n .INIT(16'h5003)) \n \\entry_cnt[4]_i_1__0 \n (.I0(\\my_full_reg_n_0_[4] ),\n .I1(\\my_empty_reg_n_0_[7] ),\n .I2(mux_wrdata_en),\n .I3(ofifo_rst_reg),\n .O(\\entry_cnt[4]_i_1__0_n_0 ));\n LUT6 #(\n .INIT(64'h7FFF8000FFFE0001)) \n \\entry_cnt[4]_i_2__0 \n (.I0(\\entry_cnt_reg_n_0_[1] ),\n .I1(\\entry_cnt_reg_n_0_[0] ),\n .I2(\\entry_cnt[4]_i_3__0_n_0 ),\n .I3(Q[0]),\n .I4(Q[2]),\n .I5(Q[1]),\n .O(\\entry_cnt[4]_i_2__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair818\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\entry_cnt[4]_i_3__0 \n (.I0(ofifo_rst_reg),\n .I1(mux_wrdata_en),\n .I2(\\my_full_reg_n_0_[4] ),\n .O(\\entry_cnt[4]_i_3__0_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\entry_cnt_reg[0] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1__0_n_0 ),\n .D(\\entry_cnt[0]_i_1__0_n_0 ),\n .Q(\\entry_cnt_reg_n_0_[0] ),\n .R(ofifo_rst));\n FDRE #(\n .INIT(1'b0)) \n \\entry_cnt_reg[1] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1__0_n_0 ),\n .D(\\entry_cnt[1]_i_1__0_n_0 ),\n .Q(\\entry_cnt_reg_n_0_[1] ),\n .R(ofifo_rst));\n FDRE #(\n .INIT(1'b0)) \n \\entry_cnt_reg[2] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1__0_n_0 ),\n .D(\\entry_cnt[2]_i_1__0_n_0 ),\n .Q(Q[0]),\n .R(ofifo_rst));\n FDRE #(\n .INIT(1'b0)) \n \\entry_cnt_reg[3] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1__0_n_0 ),\n .D(\\entry_cnt[3]_i_1__0_n_0 ),\n .Q(Q[1]),\n .R(ofifo_rst));\n FDRE #(\n .INIT(1'b0)) \n \\entry_cnt_reg[4] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1__0_n_0 ),\n .D(\\entry_cnt[4]_i_2__0_n_0 ),\n .Q(Q[2]),\n .R(ofifo_rst));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_0_5\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA({1'b0,1'b0}),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_15_0_5_n_0,mem_reg_0_15_0_5_n_1}),\n .DOB({mem_reg_0_15_0_5_n_2,mem_reg_0_15_0_5_n_3}),\n .DOC({mem_reg_0_15_0_5_n_4,mem_reg_0_15_0_5_n_5}),\n .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n LUT4 #(\n .INIT(16'h082A)) \n mem_reg_0_15_0_5_i_1__1\n (.I0(mux_wrdata_en),\n .I1(ofifo_rst_reg),\n .I2(\\my_full_reg_n_0_[4] ),\n .I3(\\my_empty_reg[1]_0 ),\n .O(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_12_17\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[5:4]),\n .DIB(phy_dout[7:6]),\n .DIC(phy_dout[9:8]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [5:4]),\n .DOB(\\my_empty_reg[7]_1 [7:6]),\n .DOC(\\my_empty_reg[7]_1 [9:8]),\n .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_18_23\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[11:10]),\n .DIB(phy_dout[13:12]),\n .DIC(phy_dout[15:14]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [11:10]),\n .DOB(\\my_empty_reg[7]_1 [13:12]),\n .DOC(\\my_empty_reg[7]_1 [15:14]),\n .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_24_29\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[17:16]),\n .DIB(phy_dout[19:18]),\n .DIC(phy_dout[21:20]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [17:16]),\n .DOB(\\my_empty_reg[7]_1 [19:18]),\n .DOC(\\my_empty_reg[7]_1 [21:20]),\n .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_30_35\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[23:22]),\n .DIB(phy_dout[25:24]),\n .DIC(phy_dout[27:26]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [23:22]),\n .DOB(\\my_empty_reg[7]_1 [25:24]),\n .DOC(\\my_empty_reg[7]_1 [27:26]),\n .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_36_41\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[29:28]),\n .DIB(phy_dout[31:30]),\n .DIC(phy_dout[33:32]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [29:28]),\n .DOB(\\my_empty_reg[7]_1 [31:30]),\n .DOC(\\my_empty_reg[7]_1 [33:32]),\n .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_42_47\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[35:34]),\n .DIB(phy_dout[37:36]),\n .DIC(phy_dout[39:38]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [35:34]),\n .DOB(\\my_empty_reg[7]_1 [37:36]),\n .DOC(\\my_empty_reg[7]_1 [39:38]),\n .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_48_53\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[41:40]),\n .DIB(phy_dout[43:42]),\n .DIC(phy_dout[45:44]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [41:40]),\n .DOB(\\my_empty_reg[7]_1 [43:42]),\n .DOC(\\my_empty_reg[7]_1 [45:44]),\n .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_54_59\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[47:46]),\n .DIB(phy_dout[49:48]),\n .DIC(phy_dout[51:50]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [47:46]),\n .DOB(\\my_empty_reg[7]_1 [49:48]),\n .DOC(\\my_empty_reg[7]_1 [51:50]),\n .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_60_65\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[53:52]),\n .DIB(phy_dout[55:54]),\n .DIC(phy_dout[57:56]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [53:52]),\n .DOB(\\my_empty_reg[7]_1 [55:54]),\n .DOC(\\my_empty_reg[7]_1 [57:56]),\n .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_66_71\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[59:58]),\n .DIB(phy_dout[61:60]),\n .DIC(phy_dout[63:62]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [59:58]),\n .DOB(\\my_empty_reg[7]_1 [61:60]),\n .DOC(\\my_empty_reg[7]_1 [63:62]),\n .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_6_11\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA({1'b0,1'b0}),\n .DIB(phy_dout[1:0]),\n .DIC(phy_dout[3:2]),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_15_6_11_n_0,mem_reg_0_15_6_11_n_1}),\n .DOB(\\my_empty_reg[7]_1 [1:0]),\n .DOC(\\my_empty_reg[7]_1 [3:2]),\n .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_72_77\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[65:64]),\n .DIB(phy_dout[67:66]),\n .DIC(phy_dout[69:68]),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_15_72_77_n_0,mem_reg_0_15_72_77_n_1}),\n .DOB({mem_reg_0_15_72_77_n_2,mem_reg_0_15_72_77_n_3}),\n .DOC({mem_reg_0_15_72_77_n_4,mem_reg_0_15_72_77_n_5}),\n .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_78_79\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[71:70]),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_15_78_79_n_0,mem_reg_0_15_78_79_n_1}),\n .DOB(NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED[1:0]),\n .DOC(NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED[1:0]),\n .DOD(NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n LUT6 #(\n .INIT(64'hFFFFFFFFF071F070)) \n \\my_empty[1]_i_1__1 \n (.I0(mux_wrdata_en),\n .I1(ofifo_rst_reg),\n .I2(\\my_empty_reg[1]_0 ),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(my_empty0),\n .I5(ofifo_rst),\n .O(\\my_empty[1]_i_1__1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFF071F070)) \n \\my_empty[7]_i_1__1 \n (.I0(mux_wrdata_en),\n .I1(ofifo_rst_reg),\n .I2(\\my_empty_reg_n_0_[7] ),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(my_empty0),\n .I5(ofifo_rst),\n .O(\\my_empty[7]_i_1__1_n_0 ));\n LUT5 #(\n .INIT(32'h4A400D08)) \n \\my_empty[7]_i_2__1 \n (.I0(wr_ptr_timing[2]),\n .I1(\\my_empty[7]_i_3__1_n_0 ),\n .I2(wr_ptr_timing[3]),\n .I3(\\my_empty[7]_i_4__1_n_0 ),\n .I4(\\rd_ptr_reg_n_0_[2] ),\n .O(my_empty0));\n (* SOFT_HLUTNM = \"soft_lutpair821\" *) \n LUT5 #(\n .INIT(32'h00000040)) \n \\my_empty[7]_i_3__1 \n (.I0(wr_ptr_timing[1]),\n .I1(\\rd_ptr_reg_n_0_[0] ),\n .I2(\\rd_ptr_reg_n_0_[1] ),\n .I3(\\rd_ptr_reg_n_0_[3] ),\n .I4(wr_ptr_timing[0]),\n .O(\\my_empty[7]_i_3__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair821\" *) \n LUT5 #(\n .INIT(32'h84210842)) \n \\my_empty[7]_i_4__1 \n (.I0(wr_ptr_timing[0]),\n .I1(wr_ptr_timing[1]),\n .I2(\\rd_ptr_reg_n_0_[0] ),\n .I3(\\rd_ptr_reg_n_0_[1] ),\n .I4(\\rd_ptr_reg_n_0_[3] ),\n .O(\\my_empty[7]_i_4__1_n_0 ));\n (* syn_maxfan = \"3\" *) \n FDRE #(\n .INIT(1'b0)) \n \\my_empty_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_empty[1]_i_1__1_n_0 ),\n .Q(\\my_empty_reg[1]_0 ),\n .R(1'b0));\n (* syn_maxfan = \"3\" *) \n FDRE #(\n .INIT(1'b0)) \n \\my_empty_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_empty[7]_i_1__1_n_0 ),\n .Q(\\my_empty_reg_n_0_[7] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000FF00FC80)) \n \\my_full[4]_i_1__0 \n (.I0(my_full0),\n .I1(mux_wrdata_en),\n .I2(ofifo_rst_reg),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(\\my_empty_reg_n_0_[7] ),\n .I5(ofifo_rst),\n .O(\\my_full[4]_i_1__0_n_0 ));\n LUT5 #(\n .INIT(32'h4A400D08)) \n \\my_full[4]_i_2__1 \n (.I0(rd_ptr_timing[2]),\n .I1(\\my_full[4]_i_3__1_n_0 ),\n .I2(rd_ptr_timing[3]),\n .I3(\\my_full[4]_i_4__1_n_0 ),\n .I4(wr_ptr[2]),\n .O(my_full0));\n (* SOFT_HLUTNM = \"soft_lutpair819\" *) \n LUT5 #(\n .INIT(32'h00000040)) \n \\my_full[4]_i_3__1 \n (.I0(rd_ptr_timing[1]),\n .I1(wr_ptr[0]),\n .I2(wr_ptr[1]),\n .I3(wr_ptr[3]),\n .I4(rd_ptr_timing[0]),\n .O(\\my_full[4]_i_3__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair819\" *) \n LUT5 #(\n .INIT(32'h84210842)) \n \\my_full[4]_i_4__1 \n (.I0(rd_ptr_timing[0]),\n .I1(rd_ptr_timing[1]),\n .I2(wr_ptr[0]),\n .I3(wr_ptr[1]),\n .I4(wr_ptr[3]),\n .O(\\my_full[4]_i_4__1_n_0 ));\n (* syn_maxfan = \"3\" *) \n FDRE #(\n .INIT(1'b0)) \n \\my_full_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_full[4]_i_1__0_n_0 ),\n .Q(\\my_full_reg_n_0_[4] ),\n .R(1'b0));\n LUT3 #(\n .INIT(8'h0D)) \n out_fifo_i_1__4\n (.I0(\\my_empty_reg[1]_0 ),\n .I1(mux_wrdata_en),\n .I2(ofifo_rst_reg),\n .O(\\my_empty_reg[7]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair827\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_2__3\n (.I0(mem_reg_0_15_6_11_n_0),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[7]));\n (* SOFT_HLUTNM = \"soft_lutpair823\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_3__3\n (.I0(mem_reg_0_15_6_11_n_1),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[6]));\n (* SOFT_HLUTNM = \"soft_lutpair828\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_4__3\n (.I0(mem_reg_0_15_0_5_n_4),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[5]));\n (* SOFT_HLUTNM = \"soft_lutpair825\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_5__3\n (.I0(mem_reg_0_15_0_5_n_5),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[4]));\n (* SOFT_HLUTNM = \"soft_lutpair826\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_6__3\n (.I0(mem_reg_0_15_0_5_n_2),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair824\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_74__2\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[286] [7]),\n .I2(mem_reg_0_15_78_79_n_0),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[7]));\n (* SOFT_HLUTNM = \"soft_lutpair827\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_75__2\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[286] [6]),\n .I2(mem_reg_0_15_78_79_n_1),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[6]));\n (* SOFT_HLUTNM = \"soft_lutpair825\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_76__2\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[286] [5]),\n .I2(mem_reg_0_15_72_77_n_4),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[5]));\n (* SOFT_HLUTNM = \"soft_lutpair826\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_77__2\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[286] [4]),\n .I2(mem_reg_0_15_72_77_n_5),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[4]));\n (* SOFT_HLUTNM = \"soft_lutpair823\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_78__2\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[286] [3]),\n .I2(mem_reg_0_15_72_77_n_2),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[3]));\n (* SOFT_HLUTNM = \"soft_lutpair829\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_79__1\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[286] [2]),\n .I2(mem_reg_0_15_72_77_n_3),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[2]));\n (* SOFT_HLUTNM = \"soft_lutpair822\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_7__2\n (.I0(mem_reg_0_15_0_5_n_3),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair822\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_80__1\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[286] [1]),\n .I2(mem_reg_0_15_72_77_n_0),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[1]));\n (* SOFT_HLUTNM = \"soft_lutpair828\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_81__1\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[286] [0]),\n .I2(mem_reg_0_15_72_77_n_1),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[0]));\n (* SOFT_HLUTNM = \"soft_lutpair829\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_8__2\n (.I0(mem_reg_0_15_0_5_n_0),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair824\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_9__2\n (.I0(mem_reg_0_15_0_5_n_1),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[0]));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[0] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[0]),\n .Q(\\rd_ptr_reg_n_0_[0] ),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[1] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[1]),\n .Q(\\rd_ptr_reg_n_0_[1] ),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[2] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[2]),\n .Q(\\rd_ptr_reg_n_0_[2] ),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[3] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[3]),\n .Q(\\rd_ptr_reg_n_0_[3] ),\n .R(ofifo_rst));\n (* SOFT_HLUTNM = \"soft_lutpair833\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\rd_ptr_timing[0]_i_1__3 \n (.I0(\\rd_ptr_reg_n_0_[3] ),\n .I1(\\rd_ptr_reg_n_0_[0] ),\n .O(nxt_rd_ptr[0]));\n (* SOFT_HLUTNM = \"soft_lutpair833\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\rd_ptr_timing[1]_i_1__1 \n (.I0(\\rd_ptr_reg_n_0_[3] ),\n .I1(\\rd_ptr_reg_n_0_[0] ),\n .I2(\\rd_ptr_reg_n_0_[1] ),\n .O(nxt_rd_ptr[1]));\n (* SOFT_HLUTNM = \"soft_lutpair831\" *) \n LUT4 #(\n .INIT(16'hAA6A)) \n \\rd_ptr_timing[2]_i_1__1 \n (.I0(\\rd_ptr_reg_n_0_[2] ),\n .I1(\\rd_ptr_reg_n_0_[0] ),\n .I2(\\rd_ptr_reg_n_0_[1] ),\n .I3(\\rd_ptr_reg_n_0_[3] ),\n .O(nxt_rd_ptr[2]));\n LUT2 #(\n .INIT(4'h1)) \n \\rd_ptr_timing[3]_i_1__1 \n (.I0(\\my_empty_reg_n_0_[7] ),\n .I1(ofifo_rst_reg),\n .O(\\rd_ptr_timing[3]_i_1__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair831\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\rd_ptr_timing[3]_i_2__1 \n (.I0(\\rd_ptr_reg_n_0_[3] ),\n .I1(\\rd_ptr_reg_n_0_[1] ),\n .I2(\\rd_ptr_reg_n_0_[0] ),\n .I3(\\rd_ptr_reg_n_0_[2] ),\n .O(nxt_rd_ptr[3]));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[0] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[0]),\n .Q(rd_ptr_timing[0]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[1] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[1]),\n .Q(rd_ptr_timing[1]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[2] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[2]),\n .Q(rd_ptr_timing[2]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[3] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[3]),\n .Q(rd_ptr_timing[3]),\n .R(ofifo_rst));\n (* SOFT_HLUTNM = \"soft_lutpair832\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\wr_ptr[0]_i_1__5 \n (.I0(wr_ptr[3]),\n .I1(wr_ptr[0]),\n .O(nxt_wr_ptr[0]));\n (* SOFT_HLUTNM = \"soft_lutpair832\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\wr_ptr[1]_i_1__5 \n (.I0(wr_ptr[3]),\n .I1(wr_ptr[0]),\n .I2(wr_ptr[1]),\n .O(nxt_wr_ptr[1]));\n (* SOFT_HLUTNM = \"soft_lutpair830\" *) \n LUT4 #(\n .INIT(16'hAA6A)) \n \\wr_ptr[2]_i_1__3 \n (.I0(wr_ptr[2]),\n .I1(wr_ptr[0]),\n .I2(wr_ptr[1]),\n .I3(wr_ptr[3]),\n .O(nxt_wr_ptr[2]));\n LUT4 #(\n .INIT(16'h082A)) \n \\wr_ptr[3]_i_1__3 \n (.I0(mux_wrdata_en),\n .I1(ofifo_rst_reg),\n .I2(\\my_full_reg_n_0_[4] ),\n .I3(\\my_empty_reg_n_0_[7] ),\n .O(wr_ptr0));\n (* SOFT_HLUTNM = \"soft_lutpair830\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\wr_ptr[3]_i_2__0 \n (.I0(wr_ptr[3]),\n .I1(wr_ptr[1]),\n .I2(wr_ptr[0]),\n .I3(wr_ptr[2]),\n .O(nxt_wr_ptr[3]));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[0] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[0]),\n .Q(wr_ptr[0]),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[1] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[1]),\n .Q(wr_ptr[1]),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[2] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[2]),\n .Q(wr_ptr[2]),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[3] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[3]),\n .Q(wr_ptr[3]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[0] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[0]),\n .Q(wr_ptr_timing[0]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[1] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[1]),\n .Q(wr_ptr_timing[1]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[2] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[2]),\n .Q(wr_ptr_timing[2]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[3] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[3]),\n .Q(wr_ptr_timing[3]),\n .R(ofifo_rst));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_of_pre_fifo\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized4\n (\\my_empty_reg[7]_0 ,\n \\my_empty_reg[1]_0 ,\n D0,\n D9,\n \\my_empty_reg[7]_1 ,\n Q,\n ofifo_rst,\n CLK,\n ofifo_rst_reg,\n mux_wrdata_en,\n init_calib_complete_reg_rep,\n \\write_buffer.wr_buf_out_data_reg[285] ,\n phy_dout);\n output \\my_empty_reg[7]_0 ;\n output \\my_empty_reg[1]_0 ;\n output [7:0]D0;\n output [7:0]D9;\n output [63:0]\\my_empty_reg[7]_1 ;\n output [2:0]Q;\n input ofifo_rst;\n input CLK;\n input ofifo_rst_reg;\n input mux_wrdata_en;\n input init_calib_complete_reg_rep;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[285] ;\n input [71:0]phy_dout;\n\n wire CLK;\n wire [7:0]D0;\n wire [7:0]D9;\n wire [2:0]Q;\n wire \\entry_cnt[0]_i_1__1_n_0 ;\n wire \\entry_cnt[1]_i_1__1_n_0 ;\n wire \\entry_cnt[2]_i_1__1_n_0 ;\n wire \\entry_cnt[3]_i_1__1_n_0 ;\n wire \\entry_cnt[4]_i_1__1_n_0 ;\n wire \\entry_cnt[4]_i_2__1_n_0 ;\n wire \\entry_cnt[4]_i_3__1_n_0 ;\n wire \\entry_cnt_reg_n_0_[0] ;\n wire \\entry_cnt_reg_n_0_[1] ;\n wire init_calib_complete_reg_rep;\n wire mem_reg_0_15_0_5_n_0;\n wire mem_reg_0_15_0_5_n_1;\n wire mem_reg_0_15_0_5_n_2;\n wire mem_reg_0_15_0_5_n_3;\n wire mem_reg_0_15_0_5_n_4;\n wire mem_reg_0_15_0_5_n_5;\n wire mem_reg_0_15_6_11_n_0;\n wire mem_reg_0_15_6_11_n_1;\n wire mem_reg_0_15_72_77_n_0;\n wire mem_reg_0_15_72_77_n_1;\n wire mem_reg_0_15_72_77_n_2;\n wire mem_reg_0_15_72_77_n_3;\n wire mem_reg_0_15_72_77_n_4;\n wire mem_reg_0_15_72_77_n_5;\n wire mem_reg_0_15_78_79_n_0;\n wire mem_reg_0_15_78_79_n_1;\n wire mux_wrdata_en;\n wire my_empty0;\n wire \\my_empty[1]_i_1__2_n_0 ;\n wire \\my_empty[7]_i_1__2_n_0 ;\n wire \\my_empty[7]_i_3__2_n_0 ;\n wire \\my_empty[7]_i_4__2_n_0 ;\n wire \\my_empty_reg[1]_0 ;\n wire \\my_empty_reg[7]_0 ;\n wire [63:0]\\my_empty_reg[7]_1 ;\n wire \\my_empty_reg_n_0_[7] ;\n wire my_full0;\n wire \\my_full[4]_i_1__1_n_0 ;\n wire \\my_full[4]_i_3__2_n_0 ;\n wire \\my_full[4]_i_4__2_n_0 ;\n wire \\my_full_reg_n_0_[4] ;\n wire [3:0]nxt_rd_ptr;\n wire [3:0]nxt_wr_ptr;\n wire ofifo_rst;\n wire ofifo_rst_reg;\n wire [71:0]phy_dout;\n wire \\rd_ptr_reg_n_0_[0] ;\n wire \\rd_ptr_reg_n_0_[1] ;\n wire \\rd_ptr_reg_n_0_[2] ;\n wire \\rd_ptr_reg_n_0_[3] ;\n wire [3:0]rd_ptr_timing;\n wire \\rd_ptr_timing[3]_i_1__2_n_0 ;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) wire wr_en;\n wire [3:0]wr_ptr;\n wire wr_ptr0;\n wire [3:0]wr_ptr_timing;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[285] ;\n wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED;\n\n (* SOFT_HLUTNM = \"soft_lutpair871\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\entry_cnt[0]_i_1__1 \n (.I0(\\entry_cnt_reg_n_0_[0] ),\n .O(\\entry_cnt[0]_i_1__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair869\" *) \n LUT5 #(\n .INIT(32'hAA6A5595)) \n \\entry_cnt[1]_i_1__1 \n (.I0(\\entry_cnt_reg_n_0_[0] ),\n .I1(ofifo_rst_reg),\n .I2(mux_wrdata_en),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(\\entry_cnt_reg_n_0_[1] ),\n .O(\\entry_cnt[1]_i_1__1_n_0 ));\n LUT6 #(\n .INIT(64'hFF7F0080AAEA5515)) \n \\entry_cnt[2]_i_1__1 \n (.I0(\\entry_cnt_reg_n_0_[0] ),\n .I1(ofifo_rst_reg),\n .I2(mux_wrdata_en),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(Q[0]),\n .I5(\\entry_cnt_reg_n_0_[1] ),\n .O(\\entry_cnt[2]_i_1__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair871\" *) \n LUT5 #(\n .INIT(32'h7F80FE01)) \n \\entry_cnt[3]_i_1__1 \n (.I0(\\entry_cnt[4]_i_3__1_n_0 ),\n .I1(\\entry_cnt_reg_n_0_[0] ),\n .I2(\\entry_cnt_reg_n_0_[1] ),\n .I3(Q[1]),\n .I4(Q[0]),\n .O(\\entry_cnt[3]_i_1__1_n_0 ));\n LUT4 #(\n .INIT(16'h5003)) \n \\entry_cnt[4]_i_1__1 \n (.I0(\\my_full_reg_n_0_[4] ),\n .I1(\\my_empty_reg_n_0_[7] ),\n .I2(mux_wrdata_en),\n .I3(ofifo_rst_reg),\n .O(\\entry_cnt[4]_i_1__1_n_0 ));\n LUT6 #(\n .INIT(64'h7FFF8000FFFE0001)) \n \\entry_cnt[4]_i_2__1 \n (.I0(\\entry_cnt_reg_n_0_[1] ),\n .I1(\\entry_cnt_reg_n_0_[0] ),\n .I2(\\entry_cnt[4]_i_3__1_n_0 ),\n .I3(Q[0]),\n .I4(Q[2]),\n .I5(Q[1]),\n .O(\\entry_cnt[4]_i_2__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair869\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\entry_cnt[4]_i_3__1 \n (.I0(ofifo_rst_reg),\n .I1(mux_wrdata_en),\n .I2(\\my_full_reg_n_0_[4] ),\n .O(\\entry_cnt[4]_i_3__1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\entry_cnt_reg[0] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1__1_n_0 ),\n .D(\\entry_cnt[0]_i_1__1_n_0 ),\n .Q(\\entry_cnt_reg_n_0_[0] ),\n .R(ofifo_rst));\n FDRE #(\n .INIT(1'b0)) \n \\entry_cnt_reg[1] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1__1_n_0 ),\n .D(\\entry_cnt[1]_i_1__1_n_0 ),\n .Q(\\entry_cnt_reg_n_0_[1] ),\n .R(ofifo_rst));\n FDRE #(\n .INIT(1'b0)) \n \\entry_cnt_reg[2] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1__1_n_0 ),\n .D(\\entry_cnt[2]_i_1__1_n_0 ),\n .Q(Q[0]),\n .R(ofifo_rst));\n FDRE #(\n .INIT(1'b0)) \n \\entry_cnt_reg[3] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1__1_n_0 ),\n .D(\\entry_cnt[3]_i_1__1_n_0 ),\n .Q(Q[1]),\n .R(ofifo_rst));\n FDRE #(\n .INIT(1'b0)) \n \\entry_cnt_reg[4] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1__1_n_0 ),\n .D(\\entry_cnt[4]_i_2__1_n_0 ),\n .Q(Q[2]),\n .R(ofifo_rst));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_0_5\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA({1'b0,1'b0}),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_15_0_5_n_0,mem_reg_0_15_0_5_n_1}),\n .DOB({mem_reg_0_15_0_5_n_2,mem_reg_0_15_0_5_n_3}),\n .DOC({mem_reg_0_15_0_5_n_4,mem_reg_0_15_0_5_n_5}),\n .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n LUT4 #(\n .INIT(16'h082A)) \n mem_reg_0_15_0_5_i_1__2\n (.I0(mux_wrdata_en),\n .I1(ofifo_rst_reg),\n .I2(\\my_full_reg_n_0_[4] ),\n .I3(\\my_empty_reg[1]_0 ),\n .O(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_12_17\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[5:4]),\n .DIB(phy_dout[7:6]),\n .DIC(phy_dout[9:8]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [5:4]),\n .DOB(\\my_empty_reg[7]_1 [7:6]),\n .DOC(\\my_empty_reg[7]_1 [9:8]),\n .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_18_23\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[11:10]),\n .DIB(phy_dout[13:12]),\n .DIC(phy_dout[15:14]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [11:10]),\n .DOB(\\my_empty_reg[7]_1 [13:12]),\n .DOC(\\my_empty_reg[7]_1 [15:14]),\n .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_24_29\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[17:16]),\n .DIB(phy_dout[19:18]),\n .DIC(phy_dout[21:20]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [17:16]),\n .DOB(\\my_empty_reg[7]_1 [19:18]),\n .DOC(\\my_empty_reg[7]_1 [21:20]),\n .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_30_35\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[23:22]),\n .DIB(phy_dout[25:24]),\n .DIC(phy_dout[27:26]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [23:22]),\n .DOB(\\my_empty_reg[7]_1 [25:24]),\n .DOC(\\my_empty_reg[7]_1 [27:26]),\n .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_36_41\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[29:28]),\n .DIB(phy_dout[31:30]),\n .DIC(phy_dout[33:32]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [29:28]),\n .DOB(\\my_empty_reg[7]_1 [31:30]),\n .DOC(\\my_empty_reg[7]_1 [33:32]),\n .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_42_47\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[35:34]),\n .DIB(phy_dout[37:36]),\n .DIC(phy_dout[39:38]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [35:34]),\n .DOB(\\my_empty_reg[7]_1 [37:36]),\n .DOC(\\my_empty_reg[7]_1 [39:38]),\n .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_48_53\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[41:40]),\n .DIB(phy_dout[43:42]),\n .DIC(phy_dout[45:44]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [41:40]),\n .DOB(\\my_empty_reg[7]_1 [43:42]),\n .DOC(\\my_empty_reg[7]_1 [45:44]),\n .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_54_59\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[47:46]),\n .DIB(phy_dout[49:48]),\n .DIC(phy_dout[51:50]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [47:46]),\n .DOB(\\my_empty_reg[7]_1 [49:48]),\n .DOC(\\my_empty_reg[7]_1 [51:50]),\n .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_60_65\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[53:52]),\n .DIB(phy_dout[55:54]),\n .DIC(phy_dout[57:56]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [53:52]),\n .DOB(\\my_empty_reg[7]_1 [55:54]),\n .DOC(\\my_empty_reg[7]_1 [57:56]),\n .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_66_71\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[59:58]),\n .DIB(phy_dout[61:60]),\n .DIC(phy_dout[63:62]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [59:58]),\n .DOB(\\my_empty_reg[7]_1 [61:60]),\n .DOC(\\my_empty_reg[7]_1 [63:62]),\n .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_6_11\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA({1'b0,1'b0}),\n .DIB(phy_dout[1:0]),\n .DIC(phy_dout[3:2]),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_15_6_11_n_0,mem_reg_0_15_6_11_n_1}),\n .DOB(\\my_empty_reg[7]_1 [1:0]),\n .DOC(\\my_empty_reg[7]_1 [3:2]),\n .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_72_77\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[65:64]),\n .DIB(phy_dout[67:66]),\n .DIC(phy_dout[69:68]),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_15_72_77_n_0,mem_reg_0_15_72_77_n_1}),\n .DOB({mem_reg_0_15_72_77_n_2,mem_reg_0_15_72_77_n_3}),\n .DOC({mem_reg_0_15_72_77_n_4,mem_reg_0_15_72_77_n_5}),\n .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_78_79\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[71:70]),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_15_78_79_n_0,mem_reg_0_15_78_79_n_1}),\n .DOB(NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED[1:0]),\n .DOC(NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED[1:0]),\n .DOD(NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n LUT6 #(\n .INIT(64'hFFFFFFFFF071F070)) \n \\my_empty[1]_i_1__2 \n (.I0(mux_wrdata_en),\n .I1(ofifo_rst_reg),\n .I2(\\my_empty_reg[1]_0 ),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(my_empty0),\n .I5(ofifo_rst),\n .O(\\my_empty[1]_i_1__2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFF071F070)) \n \\my_empty[7]_i_1__2 \n (.I0(mux_wrdata_en),\n .I1(ofifo_rst_reg),\n .I2(\\my_empty_reg_n_0_[7] ),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(my_empty0),\n .I5(ofifo_rst),\n .O(\\my_empty[7]_i_1__2_n_0 ));\n LUT5 #(\n .INIT(32'h4A400D08)) \n \\my_empty[7]_i_2__2 \n (.I0(wr_ptr_timing[2]),\n .I1(\\my_empty[7]_i_3__2_n_0 ),\n .I2(wr_ptr_timing[3]),\n .I3(\\my_empty[7]_i_4__2_n_0 ),\n .I4(\\rd_ptr_reg_n_0_[2] ),\n .O(my_empty0));\n (* SOFT_HLUTNM = \"soft_lutpair872\" *) \n LUT5 #(\n .INIT(32'h00000040)) \n \\my_empty[7]_i_3__2 \n (.I0(wr_ptr_timing[1]),\n .I1(\\rd_ptr_reg_n_0_[0] ),\n .I2(\\rd_ptr_reg_n_0_[1] ),\n .I3(\\rd_ptr_reg_n_0_[3] ),\n .I4(wr_ptr_timing[0]),\n .O(\\my_empty[7]_i_3__2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair872\" *) \n LUT5 #(\n .INIT(32'h84210842)) \n \\my_empty[7]_i_4__2 \n (.I0(wr_ptr_timing[0]),\n .I1(wr_ptr_timing[1]),\n .I2(\\rd_ptr_reg_n_0_[0] ),\n .I3(\\rd_ptr_reg_n_0_[1] ),\n .I4(\\rd_ptr_reg_n_0_[3] ),\n .O(\\my_empty[7]_i_4__2_n_0 ));\n (* syn_maxfan = \"3\" *) \n FDRE #(\n .INIT(1'b0)) \n \\my_empty_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_empty[1]_i_1__2_n_0 ),\n .Q(\\my_empty_reg[1]_0 ),\n .R(1'b0));\n (* syn_maxfan = \"3\" *) \n FDRE #(\n .INIT(1'b0)) \n \\my_empty_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_empty[7]_i_1__2_n_0 ),\n .Q(\\my_empty_reg_n_0_[7] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000FF00FC80)) \n \\my_full[4]_i_1__1 \n (.I0(my_full0),\n .I1(mux_wrdata_en),\n .I2(ofifo_rst_reg),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(\\my_empty_reg_n_0_[7] ),\n .I5(ofifo_rst),\n .O(\\my_full[4]_i_1__1_n_0 ));\n LUT5 #(\n .INIT(32'h4A400D08)) \n \\my_full[4]_i_2__2 \n (.I0(rd_ptr_timing[2]),\n .I1(\\my_full[4]_i_3__2_n_0 ),\n .I2(rd_ptr_timing[3]),\n .I3(\\my_full[4]_i_4__2_n_0 ),\n .I4(wr_ptr[2]),\n .O(my_full0));\n (* SOFT_HLUTNM = \"soft_lutpair870\" *) \n LUT5 #(\n .INIT(32'h00000040)) \n \\my_full[4]_i_3__2 \n (.I0(rd_ptr_timing[1]),\n .I1(wr_ptr[0]),\n .I2(wr_ptr[1]),\n .I3(wr_ptr[3]),\n .I4(rd_ptr_timing[0]),\n .O(\\my_full[4]_i_3__2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair870\" *) \n LUT5 #(\n .INIT(32'h84210842)) \n \\my_full[4]_i_4__2 \n (.I0(rd_ptr_timing[0]),\n .I1(rd_ptr_timing[1]),\n .I2(wr_ptr[0]),\n .I3(wr_ptr[1]),\n .I4(wr_ptr[3]),\n .O(\\my_full[4]_i_4__2_n_0 ));\n (* syn_maxfan = \"3\" *) \n FDRE #(\n .INIT(1'b0)) \n \\my_full_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_full[4]_i_1__1_n_0 ),\n .Q(\\my_full_reg_n_0_[4] ),\n .R(1'b0));\n LUT3 #(\n .INIT(8'h0D)) \n out_fifo_i_1__5\n (.I0(\\my_empty_reg[1]_0 ),\n .I1(mux_wrdata_en),\n .I2(ofifo_rst_reg),\n .O(\\my_empty_reg[7]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair878\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_2__4\n (.I0(mem_reg_0_15_6_11_n_0),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[7]));\n (* SOFT_HLUTNM = \"soft_lutpair874\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_3__4\n (.I0(mem_reg_0_15_6_11_n_1),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[6]));\n (* SOFT_HLUTNM = \"soft_lutpair879\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_4__4\n (.I0(mem_reg_0_15_0_5_n_4),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[5]));\n (* SOFT_HLUTNM = \"soft_lutpair876\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_5__4\n (.I0(mem_reg_0_15_0_5_n_5),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[4]));\n (* SOFT_HLUTNM = \"soft_lutpair877\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_6__4\n (.I0(mem_reg_0_15_0_5_n_2),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair875\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_74__1\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[285] [7]),\n .I2(mem_reg_0_15_78_79_n_0),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[7]));\n (* SOFT_HLUTNM = \"soft_lutpair878\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_75__1\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[285] [6]),\n .I2(mem_reg_0_15_78_79_n_1),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[6]));\n (* SOFT_HLUTNM = \"soft_lutpair876\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_76__1\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[285] [5]),\n .I2(mem_reg_0_15_72_77_n_4),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[5]));\n (* SOFT_HLUTNM = \"soft_lutpair877\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_77__1\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[285] [4]),\n .I2(mem_reg_0_15_72_77_n_5),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[4]));\n (* SOFT_HLUTNM = \"soft_lutpair874\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_78__1\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[285] [3]),\n .I2(mem_reg_0_15_72_77_n_2),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[3]));\n (* SOFT_HLUTNM = \"soft_lutpair880\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_79__0\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[285] [2]),\n .I2(mem_reg_0_15_72_77_n_3),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[2]));\n (* SOFT_HLUTNM = \"soft_lutpair873\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_7__3\n (.I0(mem_reg_0_15_0_5_n_3),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair873\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_80__0\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[285] [1]),\n .I2(mem_reg_0_15_72_77_n_0),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[1]));\n (* SOFT_HLUTNM = \"soft_lutpair879\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_81__0\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[285] [0]),\n .I2(mem_reg_0_15_72_77_n_1),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[0]));\n (* SOFT_HLUTNM = \"soft_lutpair880\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_8__3\n (.I0(mem_reg_0_15_0_5_n_0),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair875\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_9__3\n (.I0(mem_reg_0_15_0_5_n_1),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[0]));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[0] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__2_n_0 ),\n .D(nxt_rd_ptr[0]),\n .Q(\\rd_ptr_reg_n_0_[0] ),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[1] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__2_n_0 ),\n .D(nxt_rd_ptr[1]),\n .Q(\\rd_ptr_reg_n_0_[1] ),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[2] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__2_n_0 ),\n .D(nxt_rd_ptr[2]),\n .Q(\\rd_ptr_reg_n_0_[2] ),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[3] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__2_n_0 ),\n .D(nxt_rd_ptr[3]),\n .Q(\\rd_ptr_reg_n_0_[3] ),\n .R(ofifo_rst));\n (* SOFT_HLUTNM = \"soft_lutpair884\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\rd_ptr_timing[0]_i_1__5 \n (.I0(\\rd_ptr_reg_n_0_[3] ),\n .I1(\\rd_ptr_reg_n_0_[0] ),\n .O(nxt_rd_ptr[0]));\n (* SOFT_HLUTNM = \"soft_lutpair884\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\rd_ptr_timing[1]_i_1__2 \n (.I0(\\rd_ptr_reg_n_0_[3] ),\n .I1(\\rd_ptr_reg_n_0_[0] ),\n .I2(\\rd_ptr_reg_n_0_[1] ),\n .O(nxt_rd_ptr[1]));\n (* SOFT_HLUTNM = \"soft_lutpair882\" *) \n LUT4 #(\n .INIT(16'hAA6A)) \n \\rd_ptr_timing[2]_i_1__2 \n (.I0(\\rd_ptr_reg_n_0_[2] ),\n .I1(\\rd_ptr_reg_n_0_[0] ),\n .I2(\\rd_ptr_reg_n_0_[1] ),\n .I3(\\rd_ptr_reg_n_0_[3] ),\n .O(nxt_rd_ptr[2]));\n LUT2 #(\n .INIT(4'h1)) \n \\rd_ptr_timing[3]_i_1__2 \n (.I0(\\my_empty_reg_n_0_[7] ),\n .I1(ofifo_rst_reg),\n .O(\\rd_ptr_timing[3]_i_1__2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair882\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\rd_ptr_timing[3]_i_2__2 \n (.I0(\\rd_ptr_reg_n_0_[3] ),\n .I1(\\rd_ptr_reg_n_0_[1] ),\n .I2(\\rd_ptr_reg_n_0_[0] ),\n .I3(\\rd_ptr_reg_n_0_[2] ),\n .O(nxt_rd_ptr[3]));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[0] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__2_n_0 ),\n .D(nxt_rd_ptr[0]),\n .Q(rd_ptr_timing[0]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[1] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__2_n_0 ),\n .D(nxt_rd_ptr[1]),\n .Q(rd_ptr_timing[1]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[2] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__2_n_0 ),\n .D(nxt_rd_ptr[2]),\n .Q(rd_ptr_timing[2]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[3] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__2_n_0 ),\n .D(nxt_rd_ptr[3]),\n .Q(rd_ptr_timing[3]),\n .R(ofifo_rst));\n (* SOFT_HLUTNM = \"soft_lutpair883\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\wr_ptr[0]_i_1__7 \n (.I0(wr_ptr[3]),\n .I1(wr_ptr[0]),\n .O(nxt_wr_ptr[0]));\n (* SOFT_HLUTNM = \"soft_lutpair883\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\wr_ptr[1]_i_1__7 \n (.I0(wr_ptr[3]),\n .I1(wr_ptr[0]),\n .I2(wr_ptr[1]),\n .O(nxt_wr_ptr[1]));\n (* SOFT_HLUTNM = \"soft_lutpair881\" *) \n LUT4 #(\n .INIT(16'hAA6A)) \n \\wr_ptr[2]_i_1__4 \n (.I0(wr_ptr[2]),\n .I1(wr_ptr[0]),\n .I2(wr_ptr[1]),\n .I3(wr_ptr[3]),\n .O(nxt_wr_ptr[2]));\n LUT4 #(\n .INIT(16'h082A)) \n \\wr_ptr[3]_i_1__4 \n (.I0(mux_wrdata_en),\n .I1(ofifo_rst_reg),\n .I2(\\my_full_reg_n_0_[4] ),\n .I3(\\my_empty_reg_n_0_[7] ),\n .O(wr_ptr0));\n (* SOFT_HLUTNM = \"soft_lutpair881\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\wr_ptr[3]_i_2__1 \n (.I0(wr_ptr[3]),\n .I1(wr_ptr[1]),\n .I2(wr_ptr[0]),\n .I3(wr_ptr[2]),\n .O(nxt_wr_ptr[3]));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[0] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[0]),\n .Q(wr_ptr[0]),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[1] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[1]),\n .Q(wr_ptr[1]),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[2] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[2]),\n .Q(wr_ptr[2]),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[3] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[3]),\n .Q(wr_ptr[3]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[0] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[0]),\n .Q(wr_ptr_timing[0]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[1] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[1]),\n .Q(wr_ptr_timing[1]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[2] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[2]),\n .Q(wr_ptr_timing[2]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[3] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[3]),\n .Q(wr_ptr_timing[3]),\n .R(ofifo_rst));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_of_pre_fifo\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized5\n (\\my_empty_reg[7]_0 ,\n \\my_empty_reg[1]_0 ,\n D0,\n D9,\n \\my_empty_reg[7]_1 ,\n Q,\n ofifo_rst,\n CLK,\n ofifo_rst_reg,\n mux_wrdata_en,\n init_calib_complete_reg_rep,\n \\write_buffer.wr_buf_out_data_reg[284] ,\n phy_dout);\n output \\my_empty_reg[7]_0 ;\n output \\my_empty_reg[1]_0 ;\n output [7:0]D0;\n output [7:0]D9;\n output [63:0]\\my_empty_reg[7]_1 ;\n output [2:0]Q;\n input ofifo_rst;\n input CLK;\n input ofifo_rst_reg;\n input mux_wrdata_en;\n input init_calib_complete_reg_rep;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[284] ;\n input [71:0]phy_dout;\n\n wire CLK;\n wire [7:0]D0;\n wire [7:0]D9;\n wire [2:0]Q;\n wire \\entry_cnt[0]_i_1__2_n_0 ;\n wire \\entry_cnt[1]_i_1__2_n_0 ;\n wire \\entry_cnt[2]_i_1__2_n_0 ;\n wire \\entry_cnt[3]_i_1__2_n_0 ;\n wire \\entry_cnt[4]_i_1__2_n_0 ;\n wire \\entry_cnt[4]_i_2__2_n_0 ;\n wire \\entry_cnt[4]_i_3__2_n_0 ;\n wire \\entry_cnt_reg_n_0_[0] ;\n wire \\entry_cnt_reg_n_0_[1] ;\n wire init_calib_complete_reg_rep;\n wire mem_reg_0_15_0_5_n_0;\n wire mem_reg_0_15_0_5_n_1;\n wire mem_reg_0_15_0_5_n_2;\n wire mem_reg_0_15_0_5_n_3;\n wire mem_reg_0_15_0_5_n_4;\n wire mem_reg_0_15_0_5_n_5;\n wire mem_reg_0_15_6_11_n_0;\n wire mem_reg_0_15_6_11_n_1;\n wire mem_reg_0_15_72_77_n_0;\n wire mem_reg_0_15_72_77_n_1;\n wire mem_reg_0_15_72_77_n_2;\n wire mem_reg_0_15_72_77_n_3;\n wire mem_reg_0_15_72_77_n_4;\n wire mem_reg_0_15_72_77_n_5;\n wire mem_reg_0_15_78_79_n_0;\n wire mem_reg_0_15_78_79_n_1;\n wire mux_wrdata_en;\n wire my_empty0;\n wire \\my_empty[1]_i_1__3_n_0 ;\n wire \\my_empty[7]_i_1__3_n_0 ;\n wire \\my_empty[7]_i_3__3_n_0 ;\n wire \\my_empty[7]_i_4__3_n_0 ;\n wire \\my_empty_reg[1]_0 ;\n wire \\my_empty_reg[7]_0 ;\n wire [63:0]\\my_empty_reg[7]_1 ;\n wire \\my_empty_reg_n_0_[7] ;\n wire my_full0;\n wire \\my_full[4]_i_1__2_n_0 ;\n wire \\my_full[4]_i_3__3_n_0 ;\n wire \\my_full[4]_i_4__3_n_0 ;\n wire \\my_full_reg_n_0_[4] ;\n wire [3:0]nxt_rd_ptr;\n wire [3:0]nxt_wr_ptr;\n wire ofifo_rst;\n wire ofifo_rst_reg;\n wire [71:0]phy_dout;\n wire \\rd_ptr_reg_n_0_[0] ;\n wire \\rd_ptr_reg_n_0_[1] ;\n wire \\rd_ptr_reg_n_0_[2] ;\n wire \\rd_ptr_reg_n_0_[3] ;\n wire [3:0]rd_ptr_timing;\n wire \\rd_ptr_timing[3]_i_1__3_n_0 ;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) wire wr_en;\n wire [3:0]wr_ptr;\n wire wr_ptr0;\n wire [3:0]wr_ptr_timing;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[284] ;\n wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED;\n\n (* SOFT_HLUTNM = \"soft_lutpair923\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\entry_cnt[0]_i_1__2 \n (.I0(\\entry_cnt_reg_n_0_[0] ),\n .O(\\entry_cnt[0]_i_1__2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair921\" *) \n LUT5 #(\n .INIT(32'hAA6A5595)) \n \\entry_cnt[1]_i_1__2 \n (.I0(\\entry_cnt_reg_n_0_[0] ),\n .I1(ofifo_rst_reg),\n .I2(mux_wrdata_en),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(\\entry_cnt_reg_n_0_[1] ),\n .O(\\entry_cnt[1]_i_1__2_n_0 ));\n LUT6 #(\n .INIT(64'hFF7F0080AAEA5515)) \n \\entry_cnt[2]_i_1__2 \n (.I0(\\entry_cnt_reg_n_0_[0] ),\n .I1(ofifo_rst_reg),\n .I2(mux_wrdata_en),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(Q[0]),\n .I5(\\entry_cnt_reg_n_0_[1] ),\n .O(\\entry_cnt[2]_i_1__2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair923\" *) \n LUT5 #(\n .INIT(32'h7F80FE01)) \n \\entry_cnt[3]_i_1__2 \n (.I0(\\entry_cnt[4]_i_3__2_n_0 ),\n .I1(\\entry_cnt_reg_n_0_[0] ),\n .I2(\\entry_cnt_reg_n_0_[1] ),\n .I3(Q[1]),\n .I4(Q[0]),\n .O(\\entry_cnt[3]_i_1__2_n_0 ));\n LUT4 #(\n .INIT(16'h5003)) \n \\entry_cnt[4]_i_1__2 \n (.I0(\\my_full_reg_n_0_[4] ),\n .I1(\\my_empty_reg_n_0_[7] ),\n .I2(mux_wrdata_en),\n .I3(ofifo_rst_reg),\n .O(\\entry_cnt[4]_i_1__2_n_0 ));\n LUT6 #(\n .INIT(64'h7FFF8000FFFE0001)) \n \\entry_cnt[4]_i_2__2 \n (.I0(\\entry_cnt_reg_n_0_[1] ),\n .I1(\\entry_cnt_reg_n_0_[0] ),\n .I2(\\entry_cnt[4]_i_3__2_n_0 ),\n .I3(Q[0]),\n .I4(Q[2]),\n .I5(Q[1]),\n .O(\\entry_cnt[4]_i_2__2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair921\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\entry_cnt[4]_i_3__2 \n (.I0(ofifo_rst_reg),\n .I1(mux_wrdata_en),\n .I2(\\my_full_reg_n_0_[4] ),\n .O(\\entry_cnt[4]_i_3__2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\entry_cnt_reg[0] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1__2_n_0 ),\n .D(\\entry_cnt[0]_i_1__2_n_0 ),\n .Q(\\entry_cnt_reg_n_0_[0] ),\n .R(ofifo_rst));\n FDRE #(\n .INIT(1'b0)) \n \\entry_cnt_reg[1] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1__2_n_0 ),\n .D(\\entry_cnt[1]_i_1__2_n_0 ),\n .Q(\\entry_cnt_reg_n_0_[1] ),\n .R(ofifo_rst));\n FDRE #(\n .INIT(1'b0)) \n \\entry_cnt_reg[2] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1__2_n_0 ),\n .D(\\entry_cnt[2]_i_1__2_n_0 ),\n .Q(Q[0]),\n .R(ofifo_rst));\n FDRE #(\n .INIT(1'b0)) \n \\entry_cnt_reg[3] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1__2_n_0 ),\n .D(\\entry_cnt[3]_i_1__2_n_0 ),\n .Q(Q[1]),\n .R(ofifo_rst));\n FDRE #(\n .INIT(1'b0)) \n \\entry_cnt_reg[4] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1__2_n_0 ),\n .D(\\entry_cnt[4]_i_2__2_n_0 ),\n .Q(Q[2]),\n .R(ofifo_rst));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_0_5\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA({1'b0,1'b0}),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_15_0_5_n_0,mem_reg_0_15_0_5_n_1}),\n .DOB({mem_reg_0_15_0_5_n_2,mem_reg_0_15_0_5_n_3}),\n .DOC({mem_reg_0_15_0_5_n_4,mem_reg_0_15_0_5_n_5}),\n .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n LUT4 #(\n .INIT(16'h082A)) \n mem_reg_0_15_0_5_i_1__3\n (.I0(mux_wrdata_en),\n .I1(ofifo_rst_reg),\n .I2(\\my_full_reg_n_0_[4] ),\n .I3(\\my_empty_reg[1]_0 ),\n .O(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_12_17\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[5:4]),\n .DIB(phy_dout[7:6]),\n .DIC(phy_dout[9:8]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [5:4]),\n .DOB(\\my_empty_reg[7]_1 [7:6]),\n .DOC(\\my_empty_reg[7]_1 [9:8]),\n .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_18_23\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[11:10]),\n .DIB(phy_dout[13:12]),\n .DIC(phy_dout[15:14]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [11:10]),\n .DOB(\\my_empty_reg[7]_1 [13:12]),\n .DOC(\\my_empty_reg[7]_1 [15:14]),\n .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_24_29\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[17:16]),\n .DIB(phy_dout[19:18]),\n .DIC(phy_dout[21:20]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [17:16]),\n .DOB(\\my_empty_reg[7]_1 [19:18]),\n .DOC(\\my_empty_reg[7]_1 [21:20]),\n .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_30_35\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[23:22]),\n .DIB(phy_dout[25:24]),\n .DIC(phy_dout[27:26]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [23:22]),\n .DOB(\\my_empty_reg[7]_1 [25:24]),\n .DOC(\\my_empty_reg[7]_1 [27:26]),\n .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_36_41\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[29:28]),\n .DIB(phy_dout[31:30]),\n .DIC(phy_dout[33:32]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [29:28]),\n .DOB(\\my_empty_reg[7]_1 [31:30]),\n .DOC(\\my_empty_reg[7]_1 [33:32]),\n .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_42_47\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[35:34]),\n .DIB(phy_dout[37:36]),\n .DIC(phy_dout[39:38]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [35:34]),\n .DOB(\\my_empty_reg[7]_1 [37:36]),\n .DOC(\\my_empty_reg[7]_1 [39:38]),\n .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_48_53\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[41:40]),\n .DIB(phy_dout[43:42]),\n .DIC(phy_dout[45:44]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [41:40]),\n .DOB(\\my_empty_reg[7]_1 [43:42]),\n .DOC(\\my_empty_reg[7]_1 [45:44]),\n .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_54_59\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[47:46]),\n .DIB(phy_dout[49:48]),\n .DIC(phy_dout[51:50]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [47:46]),\n .DOB(\\my_empty_reg[7]_1 [49:48]),\n .DOC(\\my_empty_reg[7]_1 [51:50]),\n .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_60_65\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[53:52]),\n .DIB(phy_dout[55:54]),\n .DIC(phy_dout[57:56]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [53:52]),\n .DOB(\\my_empty_reg[7]_1 [55:54]),\n .DOC(\\my_empty_reg[7]_1 [57:56]),\n .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_66_71\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[59:58]),\n .DIB(phy_dout[61:60]),\n .DIC(phy_dout[63:62]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [59:58]),\n .DOB(\\my_empty_reg[7]_1 [61:60]),\n .DOC(\\my_empty_reg[7]_1 [63:62]),\n .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_6_11\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA({1'b0,1'b0}),\n .DIB(phy_dout[1:0]),\n .DIC(phy_dout[3:2]),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_15_6_11_n_0,mem_reg_0_15_6_11_n_1}),\n .DOB(\\my_empty_reg[7]_1 [1:0]),\n .DOC(\\my_empty_reg[7]_1 [3:2]),\n .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_72_77\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[65:64]),\n .DIB(phy_dout[67:66]),\n .DIC(phy_dout[69:68]),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_15_72_77_n_0,mem_reg_0_15_72_77_n_1}),\n .DOB({mem_reg_0_15_72_77_n_2,mem_reg_0_15_72_77_n_3}),\n .DOC({mem_reg_0_15_72_77_n_4,mem_reg_0_15_72_77_n_5}),\n .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_78_79\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[71:70]),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_15_78_79_n_0,mem_reg_0_15_78_79_n_1}),\n .DOB(NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED[1:0]),\n .DOC(NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED[1:0]),\n .DOD(NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n LUT6 #(\n .INIT(64'hFFFFFFFFF071F070)) \n \\my_empty[1]_i_1__3 \n (.I0(mux_wrdata_en),\n .I1(ofifo_rst_reg),\n .I2(\\my_empty_reg[1]_0 ),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(my_empty0),\n .I5(ofifo_rst),\n .O(\\my_empty[1]_i_1__3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFF071F070)) \n \\my_empty[7]_i_1__3 \n (.I0(mux_wrdata_en),\n .I1(ofifo_rst_reg),\n .I2(\\my_empty_reg_n_0_[7] ),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(my_empty0),\n .I5(ofifo_rst),\n .O(\\my_empty[7]_i_1__3_n_0 ));\n LUT5 #(\n .INIT(32'h4A400D08)) \n \\my_empty[7]_i_2__3 \n (.I0(wr_ptr_timing[2]),\n .I1(\\my_empty[7]_i_3__3_n_0 ),\n .I2(wr_ptr_timing[3]),\n .I3(\\my_empty[7]_i_4__3_n_0 ),\n .I4(\\rd_ptr_reg_n_0_[2] ),\n .O(my_empty0));\n (* SOFT_HLUTNM = \"soft_lutpair924\" *) \n LUT5 #(\n .INIT(32'h00000040)) \n \\my_empty[7]_i_3__3 \n (.I0(wr_ptr_timing[1]),\n .I1(\\rd_ptr_reg_n_0_[0] ),\n .I2(\\rd_ptr_reg_n_0_[1] ),\n .I3(\\rd_ptr_reg_n_0_[3] ),\n .I4(wr_ptr_timing[0]),\n .O(\\my_empty[7]_i_3__3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair924\" *) \n LUT5 #(\n .INIT(32'h84210842)) \n \\my_empty[7]_i_4__3 \n (.I0(wr_ptr_timing[0]),\n .I1(wr_ptr_timing[1]),\n .I2(\\rd_ptr_reg_n_0_[0] ),\n .I3(\\rd_ptr_reg_n_0_[1] ),\n .I4(\\rd_ptr_reg_n_0_[3] ),\n .O(\\my_empty[7]_i_4__3_n_0 ));\n (* syn_maxfan = \"3\" *) \n FDRE #(\n .INIT(1'b0)) \n \\my_empty_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_empty[1]_i_1__3_n_0 ),\n .Q(\\my_empty_reg[1]_0 ),\n .R(1'b0));\n (* syn_maxfan = \"3\" *) \n FDRE #(\n .INIT(1'b0)) \n \\my_empty_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_empty[7]_i_1__3_n_0 ),\n .Q(\\my_empty_reg_n_0_[7] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000FF00FC80)) \n \\my_full[4]_i_1__2 \n (.I0(my_full0),\n .I1(mux_wrdata_en),\n .I2(ofifo_rst_reg),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(\\my_empty_reg_n_0_[7] ),\n .I5(ofifo_rst),\n .O(\\my_full[4]_i_1__2_n_0 ));\n LUT5 #(\n .INIT(32'h4A400D08)) \n \\my_full[4]_i_2__3 \n (.I0(rd_ptr_timing[2]),\n .I1(\\my_full[4]_i_3__3_n_0 ),\n .I2(rd_ptr_timing[3]),\n .I3(\\my_full[4]_i_4__3_n_0 ),\n .I4(wr_ptr[2]),\n .O(my_full0));\n (* SOFT_HLUTNM = \"soft_lutpair922\" *) \n LUT5 #(\n .INIT(32'h00000040)) \n \\my_full[4]_i_3__3 \n (.I0(rd_ptr_timing[1]),\n .I1(wr_ptr[0]),\n .I2(wr_ptr[1]),\n .I3(wr_ptr[3]),\n .I4(rd_ptr_timing[0]),\n .O(\\my_full[4]_i_3__3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair922\" *) \n LUT5 #(\n .INIT(32'h84210842)) \n \\my_full[4]_i_4__3 \n (.I0(rd_ptr_timing[0]),\n .I1(rd_ptr_timing[1]),\n .I2(wr_ptr[0]),\n .I3(wr_ptr[1]),\n .I4(wr_ptr[3]),\n .O(\\my_full[4]_i_4__3_n_0 ));\n (* syn_maxfan = \"3\" *) \n FDRE #(\n .INIT(1'b0)) \n \\my_full_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_full[4]_i_1__2_n_0 ),\n .Q(\\my_full_reg_n_0_[4] ),\n .R(1'b0));\n LUT3 #(\n .INIT(8'h0D)) \n out_fifo_i_1__6\n (.I0(\\my_empty_reg[1]_0 ),\n .I1(mux_wrdata_en),\n .I2(ofifo_rst_reg),\n .O(\\my_empty_reg[7]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair930\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_2__5\n (.I0(mem_reg_0_15_6_11_n_0),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[7]));\n (* SOFT_HLUTNM = \"soft_lutpair926\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_3__5\n (.I0(mem_reg_0_15_6_11_n_1),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[6]));\n (* SOFT_HLUTNM = \"soft_lutpair931\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_4__5\n (.I0(mem_reg_0_15_0_5_n_4),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[5]));\n (* SOFT_HLUTNM = \"soft_lutpair928\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_5__5\n (.I0(mem_reg_0_15_0_5_n_5),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[4]));\n (* SOFT_HLUTNM = \"soft_lutpair929\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_6__5\n (.I0(mem_reg_0_15_0_5_n_2),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair927\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_74__0\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[284] [7]),\n .I2(mem_reg_0_15_78_79_n_0),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[7]));\n (* SOFT_HLUTNM = \"soft_lutpair930\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_75__0\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[284] [6]),\n .I2(mem_reg_0_15_78_79_n_1),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[6]));\n (* SOFT_HLUTNM = \"soft_lutpair928\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_76__0\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[284] [5]),\n .I2(mem_reg_0_15_72_77_n_4),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[5]));\n (* SOFT_HLUTNM = \"soft_lutpair929\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_77__0\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[284] [4]),\n .I2(mem_reg_0_15_72_77_n_5),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[4]));\n (* SOFT_HLUTNM = \"soft_lutpair926\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_78__0\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[284] [3]),\n .I2(mem_reg_0_15_72_77_n_2),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[3]));\n (* SOFT_HLUTNM = \"soft_lutpair932\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_79\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[284] [2]),\n .I2(mem_reg_0_15_72_77_n_3),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[2]));\n (* SOFT_HLUTNM = \"soft_lutpair925\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_7__4\n (.I0(mem_reg_0_15_0_5_n_3),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair925\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_80\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[284] [1]),\n .I2(mem_reg_0_15_72_77_n_0),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[1]));\n (* SOFT_HLUTNM = \"soft_lutpair931\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_81\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[284] [0]),\n .I2(mem_reg_0_15_72_77_n_1),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[0]));\n (* SOFT_HLUTNM = \"soft_lutpair932\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_8__4\n (.I0(mem_reg_0_15_0_5_n_0),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair927\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_9__4\n (.I0(mem_reg_0_15_0_5_n_1),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[0]));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[0] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__3_n_0 ),\n .D(nxt_rd_ptr[0]),\n .Q(\\rd_ptr_reg_n_0_[0] ),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[1] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__3_n_0 ),\n .D(nxt_rd_ptr[1]),\n .Q(\\rd_ptr_reg_n_0_[1] ),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[2] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__3_n_0 ),\n .D(nxt_rd_ptr[2]),\n .Q(\\rd_ptr_reg_n_0_[2] ),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[3] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__3_n_0 ),\n .D(nxt_rd_ptr[3]),\n .Q(\\rd_ptr_reg_n_0_[3] ),\n .R(ofifo_rst));\n (* SOFT_HLUTNM = \"soft_lutpair936\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\rd_ptr_timing[0]_i_1__7 \n (.I0(\\rd_ptr_reg_n_0_[3] ),\n .I1(\\rd_ptr_reg_n_0_[0] ),\n .O(nxt_rd_ptr[0]));\n (* SOFT_HLUTNM = \"soft_lutpair936\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\rd_ptr_timing[1]_i_1__3 \n (.I0(\\rd_ptr_reg_n_0_[3] ),\n .I1(\\rd_ptr_reg_n_0_[0] ),\n .I2(\\rd_ptr_reg_n_0_[1] ),\n .O(nxt_rd_ptr[1]));\n (* SOFT_HLUTNM = \"soft_lutpair934\" *) \n LUT4 #(\n .INIT(16'hAA6A)) \n \\rd_ptr_timing[2]_i_1__3 \n (.I0(\\rd_ptr_reg_n_0_[2] ),\n .I1(\\rd_ptr_reg_n_0_[0] ),\n .I2(\\rd_ptr_reg_n_0_[1] ),\n .I3(\\rd_ptr_reg_n_0_[3] ),\n .O(nxt_rd_ptr[2]));\n LUT2 #(\n .INIT(4'h1)) \n \\rd_ptr_timing[3]_i_1__3 \n (.I0(\\my_empty_reg_n_0_[7] ),\n .I1(ofifo_rst_reg),\n .O(\\rd_ptr_timing[3]_i_1__3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair934\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\rd_ptr_timing[3]_i_2__3 \n (.I0(\\rd_ptr_reg_n_0_[3] ),\n .I1(\\rd_ptr_reg_n_0_[1] ),\n .I2(\\rd_ptr_reg_n_0_[0] ),\n .I3(\\rd_ptr_reg_n_0_[2] ),\n .O(nxt_rd_ptr[3]));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[0] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__3_n_0 ),\n .D(nxt_rd_ptr[0]),\n .Q(rd_ptr_timing[0]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[1] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__3_n_0 ),\n .D(nxt_rd_ptr[1]),\n .Q(rd_ptr_timing[1]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[2] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__3_n_0 ),\n .D(nxt_rd_ptr[2]),\n .Q(rd_ptr_timing[2]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[3] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__3_n_0 ),\n .D(nxt_rd_ptr[3]),\n .Q(rd_ptr_timing[3]),\n .R(ofifo_rst));\n (* SOFT_HLUTNM = \"soft_lutpair935\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\wr_ptr[0]_i_1__9 \n (.I0(wr_ptr[3]),\n .I1(wr_ptr[0]),\n .O(nxt_wr_ptr[0]));\n (* SOFT_HLUTNM = \"soft_lutpair935\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\wr_ptr[1]_i_1__9 \n (.I0(wr_ptr[3]),\n .I1(wr_ptr[0]),\n .I2(wr_ptr[1]),\n .O(nxt_wr_ptr[1]));\n (* SOFT_HLUTNM = \"soft_lutpair933\" *) \n LUT4 #(\n .INIT(16'hAA6A)) \n \\wr_ptr[2]_i_1__5 \n (.I0(wr_ptr[2]),\n .I1(wr_ptr[0]),\n .I2(wr_ptr[1]),\n .I3(wr_ptr[3]),\n .O(nxt_wr_ptr[2]));\n LUT4 #(\n .INIT(16'h082A)) \n \\wr_ptr[3]_i_1__5 \n (.I0(mux_wrdata_en),\n .I1(ofifo_rst_reg),\n .I2(\\my_full_reg_n_0_[4] ),\n .I3(\\my_empty_reg_n_0_[7] ),\n .O(wr_ptr0));\n (* SOFT_HLUTNM = \"soft_lutpair933\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\wr_ptr[3]_i_2__2 \n (.I0(wr_ptr[3]),\n .I1(wr_ptr[1]),\n .I2(wr_ptr[0]),\n .I3(wr_ptr[2]),\n .O(nxt_wr_ptr[3]));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[0] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[0]),\n .Q(wr_ptr[0]),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[1] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[1]),\n .Q(wr_ptr[1]),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[2] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[2]),\n .Q(wr_ptr[2]),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[3] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[3]),\n .Q(wr_ptr[3]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[0] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[0]),\n .Q(wr_ptr_timing[0]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[1] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[1]),\n .Q(wr_ptr_timing[1]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[2] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[2]),\n .Q(wr_ptr_timing[2]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[3] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[3]),\n .Q(wr_ptr_timing[3]),\n .R(ofifo_rst));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_of_pre_fifo\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized6\n (\\rd_ptr_timing_reg[2]_0 ,\n \\rd_ptr_timing_reg[2]_1 ,\n \\rd_ptr_timing_reg[2]_2 ,\n \\rd_ptr_timing_reg[2]_3 ,\n wr_en,\n \\my_empty_reg[1]_0 ,\n D0,\n D1,\n \\rd_ptr_timing_reg[0]_0 ,\n D2,\n Q,\n SR,\n CLK,\n mux_cmd_wren,\n ofifo_rst_reg,\n mem_out);\n output \\rd_ptr_timing_reg[2]_0 ;\n output \\rd_ptr_timing_reg[2]_1 ;\n output \\rd_ptr_timing_reg[2]_2 ;\n output \\rd_ptr_timing_reg[2]_3 ;\n output wr_en;\n output \\my_empty_reg[1]_0 ;\n output [4:0]D0;\n output [4:0]D1;\n output \\rd_ptr_timing_reg[0]_0 ;\n output [1:0]D2;\n output [3:0]Q;\n input [0:0]SR;\n input CLK;\n input mux_cmd_wren;\n input ofifo_rst_reg;\n input [11:0]mem_out;\n\n wire CLK;\n wire [4:0]D0;\n wire [4:0]D1;\n wire [1:0]D2;\n wire [3:0]Q;\n wire [0:0]SR;\n wire [11:0]mem_out;\n wire mux_cmd_wren;\n wire my_empty0;\n wire \\my_empty[1]_i_1__6_n_0 ;\n wire \\my_empty[6]_i_1__1_n_0 ;\n wire \\my_empty[6]_i_3_n_0 ;\n wire \\my_empty[6]_i_4_n_0 ;\n wire \\my_empty_reg[1]_0 ;\n wire \\my_empty_reg_n_0_[6] ;\n wire my_full0;\n wire \\my_full[3]_i_1_n_0 ;\n wire \\my_full[3]_i_3_n_0 ;\n wire \\my_full[3]_i_4_n_0 ;\n wire \\my_full_reg_n_0_[3] ;\n wire [3:0]nxt_rd_ptr;\n wire [3:0]nxt_wr_ptr;\n wire ofifo_rst_reg;\n wire \\rd_ptr[0]_i_1__1_n_0 ;\n wire [3:0]rd_ptr_timing;\n wire \\rd_ptr_timing_reg[0]_0 ;\n wire \\rd_ptr_timing_reg[2]_0 ;\n wire \\rd_ptr_timing_reg[2]_1 ;\n wire \\rd_ptr_timing_reg[2]_2 ;\n wire \\rd_ptr_timing_reg[2]_3 ;\n wire wr_en;\n wire wr_ptr0__0;\n wire [3:0]wr_ptr_timing;\n\n (* SOFT_HLUTNM = \"soft_lutpair937\" *) \n LUT5 #(\n .INIT(32'hC0F0F0F2)) \n \\my_empty[1]_i_1__6 \n (.I0(my_empty0),\n .I1(\\my_full_reg_n_0_[3] ),\n .I2(\\my_empty_reg[1]_0 ),\n .I3(ofifo_rst_reg),\n .I4(mux_cmd_wren),\n .O(\\my_empty[1]_i_1__6_n_0 ));\n LUT5 #(\n .INIT(32'hC0F0F0F2)) \n \\my_empty[6]_i_1__1 \n (.I0(my_empty0),\n .I1(\\my_full_reg_n_0_[3] ),\n .I2(\\my_empty_reg_n_0_[6] ),\n .I3(ofifo_rst_reg),\n .I4(mux_cmd_wren),\n .O(\\my_empty[6]_i_1__1_n_0 ));\n LUT5 #(\n .INIT(32'h4A400D08)) \n \\my_empty[6]_i_2 \n (.I0(wr_ptr_timing[2]),\n .I1(\\my_empty[6]_i_3_n_0 ),\n .I2(wr_ptr_timing[3]),\n .I3(\\my_empty[6]_i_4_n_0 ),\n .I4(\\rd_ptr_timing_reg[2]_2 ),\n .O(my_empty0));\n (* SOFT_HLUTNM = \"soft_lutpair938\" *) \n LUT5 #(\n .INIT(32'h00000040)) \n \\my_empty[6]_i_3 \n (.I0(wr_ptr_timing[1]),\n .I1(\\rd_ptr_timing_reg[2]_0 ),\n .I2(\\rd_ptr_timing_reg[2]_1 ),\n .I3(\\rd_ptr_timing_reg[2]_3 ),\n .I4(wr_ptr_timing[0]),\n .O(\\my_empty[6]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair938\" *) \n LUT5 #(\n .INIT(32'h84210842)) \n \\my_empty[6]_i_4 \n (.I0(wr_ptr_timing[0]),\n .I1(wr_ptr_timing[1]),\n .I2(\\rd_ptr_timing_reg[2]_0 ),\n .I3(\\rd_ptr_timing_reg[2]_1 ),\n .I4(\\rd_ptr_timing_reg[2]_3 ),\n .O(\\my_empty[6]_i_4_n_0 ));\n (* syn_maxfan = \"3\" *) \n FDSE #(\n .INIT(1'b1)) \n \\my_empty_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_empty[1]_i_1__6_n_0 ),\n .Q(\\my_empty_reg[1]_0 ),\n .S(SR));\n (* syn_maxfan = \"3\" *) \n FDSE #(\n .INIT(1'b1)) \n \\my_empty_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_empty[6]_i_1__1_n_0 ),\n .Q(\\my_empty_reg_n_0_[6] ),\n .S(SR));\n LUT6 #(\n .INIT(64'h00000000FF00FC80)) \n \\my_full[3]_i_1 \n (.I0(my_full0),\n .I1(mux_cmd_wren),\n .I2(ofifo_rst_reg),\n .I3(\\my_full_reg_n_0_[3] ),\n .I4(\\my_empty_reg_n_0_[6] ),\n .I5(SR),\n .O(\\my_full[3]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h4A400D08)) \n \\my_full[3]_i_2 \n (.I0(rd_ptr_timing[2]),\n .I1(\\my_full[3]_i_3_n_0 ),\n .I2(rd_ptr_timing[3]),\n .I3(\\my_full[3]_i_4_n_0 ),\n .I4(Q[2]),\n .O(my_full0));\n (* SOFT_HLUTNM = \"soft_lutpair939\" *) \n LUT5 #(\n .INIT(32'h00000040)) \n \\my_full[3]_i_3 \n (.I0(rd_ptr_timing[1]),\n .I1(Q[0]),\n .I2(Q[1]),\n .I3(Q[3]),\n .I4(rd_ptr_timing[0]),\n .O(\\my_full[3]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair939\" *) \n LUT5 #(\n .INIT(32'h84210842)) \n \\my_full[3]_i_4 \n (.I0(rd_ptr_timing[0]),\n .I1(rd_ptr_timing[1]),\n .I2(Q[0]),\n .I3(Q[1]),\n .I4(Q[3]),\n .O(\\my_full[3]_i_4_n_0 ));\n (* syn_maxfan = \"3\" *) \n FDRE #(\n .INIT(1'b0)) \n \\my_full_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_full[3]_i_1_n_0 ),\n .Q(\\my_full_reg_n_0_[3] ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair948\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_10__0\n (.I0(mem_out[9]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D1[4]));\n (* SOFT_HLUTNM = \"soft_lutpair944\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_11__0\n (.I0(mem_out[8]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D1[3]));\n (* SOFT_HLUTNM = \"soft_lutpair947\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_12__0\n (.I0(mem_out[7]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D1[2]));\n (* SOFT_HLUTNM = \"soft_lutpair945\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_13__0\n (.I0(mem_out[6]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D1[1]));\n (* SOFT_HLUTNM = \"soft_lutpair949\" *) \n LUT2 #(\n .INIT(4'hE)) \n out_fifo_i_14\n (.I0(mem_out[5]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D1[0]));\n (* SOFT_HLUTNM = \"soft_lutpair946\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_18__0\n (.I0(mem_out[11]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D2[1]));\n (* SOFT_HLUTNM = \"soft_lutpair946\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_19__0\n (.I0(mem_out[10]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D2[0]));\n (* SOFT_HLUTNM = \"soft_lutpair937\" *) \n LUT3 #(\n .INIT(8'h0D)) \n out_fifo_i_1__0\n (.I0(\\my_empty_reg[1]_0 ),\n .I1(mux_cmd_wren),\n .I2(ofifo_rst_reg),\n .O(\\rd_ptr_timing_reg[0]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair948\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_2__0\n (.I0(mem_out[4]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[4]));\n (* SOFT_HLUTNM = \"soft_lutpair944\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_3__0\n (.I0(mem_out[3]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair949\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_4__0\n (.I0(mem_out[2]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair945\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_5__0\n (.I0(mem_out[1]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair947\" *) \n LUT2 #(\n .INIT(4'hE)) \n out_fifo_i_6__0\n (.I0(mem_out[0]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[0]));\n LUT4 #(\n .INIT(16'h082A)) \n p_17_out\n (.I0(mux_cmd_wren),\n .I1(ofifo_rst_reg),\n .I2(\\my_full_reg_n_0_[3] ),\n .I3(\\my_empty_reg[1]_0 ),\n .O(wr_en));\n LUT2 #(\n .INIT(4'h1)) \n \\rd_ptr[0]_i_1__1 \n (.I0(\\my_empty_reg_n_0_[6] ),\n .I1(ofifo_rst_reg),\n .O(\\rd_ptr[0]_i_1__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair942\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\rd_ptr[0]_i_2 \n (.I0(\\rd_ptr_timing_reg[2]_3 ),\n .I1(\\rd_ptr_timing_reg[2]_0 ),\n .O(nxt_rd_ptr[0]));\n (* SOFT_HLUTNM = \"soft_lutpair942\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\rd_ptr[1]_i_1 \n (.I0(\\rd_ptr_timing_reg[2]_3 ),\n .I1(\\rd_ptr_timing_reg[2]_0 ),\n .I2(\\rd_ptr_timing_reg[2]_1 ),\n .O(nxt_rd_ptr[1]));\n (* SOFT_HLUTNM = \"soft_lutpair941\" *) \n LUT4 #(\n .INIT(16'hAA6A)) \n \\rd_ptr[2]_i_1 \n (.I0(\\rd_ptr_timing_reg[2]_2 ),\n .I1(\\rd_ptr_timing_reg[2]_0 ),\n .I2(\\rd_ptr_timing_reg[2]_1 ),\n .I3(\\rd_ptr_timing_reg[2]_3 ),\n .O(nxt_rd_ptr[2]));\n (* SOFT_HLUTNM = \"soft_lutpair941\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\rd_ptr[3]_i_1 \n (.I0(\\rd_ptr_timing_reg[2]_3 ),\n .I1(\\rd_ptr_timing_reg[2]_1 ),\n .I2(\\rd_ptr_timing_reg[2]_0 ),\n .I3(\\rd_ptr_timing_reg[2]_2 ),\n .O(nxt_rd_ptr[3]));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[0] \n (.C(CLK),\n .CE(\\rd_ptr[0]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[0]),\n .Q(\\rd_ptr_timing_reg[2]_0 ),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[1] \n (.C(CLK),\n .CE(\\rd_ptr[0]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[1]),\n .Q(\\rd_ptr_timing_reg[2]_1 ),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[2] \n (.C(CLK),\n .CE(\\rd_ptr[0]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[2]),\n .Q(\\rd_ptr_timing_reg[2]_2 ),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[3] \n (.C(CLK),\n .CE(\\rd_ptr[0]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[3]),\n .Q(\\rd_ptr_timing_reg[2]_3 ),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[0] \n (.C(CLK),\n .CE(\\rd_ptr[0]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[0]),\n .Q(rd_ptr_timing[0]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[1] \n (.C(CLK),\n .CE(\\rd_ptr[0]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[1]),\n .Q(rd_ptr_timing[1]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[2] \n (.C(CLK),\n .CE(\\rd_ptr[0]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[2]),\n .Q(rd_ptr_timing[2]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[3] \n (.C(CLK),\n .CE(\\rd_ptr[0]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[3]),\n .Q(rd_ptr_timing[3]),\n .R(SR));\n LUT4 #(\n .INIT(16'h082A)) \n wr_ptr0\n (.I0(mux_cmd_wren),\n .I1(ofifo_rst_reg),\n .I2(\\my_full_reg_n_0_[3] ),\n .I3(\\my_empty_reg_n_0_[6] ),\n .O(wr_ptr0__0));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[0] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[0]),\n .Q(Q[0]),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[1] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[1]),\n .Q(Q[1]),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[2] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[2]),\n .Q(Q[2]),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[3] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[3]),\n .Q(Q[3]),\n .R(SR));\n (* SOFT_HLUTNM = \"soft_lutpair943\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\wr_ptr_timing[0]_i_1 \n (.I0(Q[3]),\n .I1(Q[0]),\n .O(nxt_wr_ptr[0]));\n (* SOFT_HLUTNM = \"soft_lutpair943\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\wr_ptr_timing[1]_i_1 \n (.I0(Q[3]),\n .I1(Q[0]),\n .I2(Q[1]),\n .O(nxt_wr_ptr[1]));\n (* SOFT_HLUTNM = \"soft_lutpair940\" *) \n LUT4 #(\n .INIT(16'hAA6A)) \n \\wr_ptr_timing[2]_i_1 \n (.I0(Q[2]),\n .I1(Q[0]),\n .I2(Q[1]),\n .I3(Q[3]),\n .O(nxt_wr_ptr[2]));\n (* SOFT_HLUTNM = \"soft_lutpair940\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\wr_ptr_timing[3]_i_1 \n (.I0(Q[3]),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(Q[2]),\n .O(nxt_wr_ptr[3]));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[0] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[0]),\n .Q(wr_ptr_timing[0]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[1] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[1]),\n .Q(wr_ptr_timing[1]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[2] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[2]),\n .Q(wr_ptr_timing[2]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[3] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[3]),\n .Q(wr_ptr_timing[3]),\n .R(SR));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_of_pre_fifo\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized7\n (\\rd_ptr_timing_reg[2]_0 ,\n \\rd_ptr_timing_reg[2]_1 ,\n \\rd_ptr_timing_reg[2]_2 ,\n \\rd_ptr_timing_reg[2]_3 ,\n wr_en_5,\n \\my_empty_reg[1]_0 ,\n \\my_full_reg[3]_0 ,\n D0,\n D3,\n D5,\n D6,\n D7,\n Q,\n SR,\n CLK,\n mux_cmd_wren,\n B_of_full,\n \\rd_ptr_reg[3]_0 );\n output \\rd_ptr_timing_reg[2]_0 ;\n output \\rd_ptr_timing_reg[2]_1 ;\n output \\rd_ptr_timing_reg[2]_2 ;\n output \\rd_ptr_timing_reg[2]_3 ;\n output wr_en_5;\n output \\my_empty_reg[1]_0 ;\n output \\my_full_reg[3]_0 ;\n output [5:0]D0;\n output [1:0]D3;\n output [1:0]D5;\n output [3:0]D6;\n output [3:0]D7;\n output [3:0]Q;\n input [0:0]SR;\n input CLK;\n input mux_cmd_wren;\n input B_of_full;\n input [17:0]\\rd_ptr_reg[3]_0 ;\n\n wire B_of_full;\n wire CLK;\n wire [5:0]D0;\n wire [1:0]D3;\n wire [1:0]D5;\n wire [3:0]D6;\n wire [3:0]D7;\n wire [3:0]Q;\n wire [0:0]SR;\n wire mux_cmd_wren;\n wire my_empty0;\n wire \\my_empty[1]_i_1__4_n_0 ;\n wire \\my_empty[6]_i_1_n_0 ;\n wire \\my_empty[6]_i_3__0_n_0 ;\n wire \\my_empty[6]_i_4__0_n_0 ;\n wire \\my_empty_reg[1]_0 ;\n wire \\my_empty_reg_n_0_[6] ;\n wire my_full0;\n wire \\my_full[3]_i_1__0_n_0 ;\n wire \\my_full[3]_i_3__0_n_0 ;\n wire \\my_full[3]_i_4__0_n_0 ;\n wire \\my_full_reg[3]_0 ;\n wire \\my_full_reg_n_0_[3] ;\n wire [3:0]nxt_rd_ptr;\n wire [3:0]nxt_wr_ptr;\n wire \\rd_ptr[3]_i_1__0_n_0 ;\n wire [17:0]\\rd_ptr_reg[3]_0 ;\n wire [3:0]rd_ptr_timing;\n wire \\rd_ptr_timing_reg[2]_0 ;\n wire \\rd_ptr_timing_reg[2]_1 ;\n wire \\rd_ptr_timing_reg[2]_2 ;\n wire \\rd_ptr_timing_reg[2]_3 ;\n wire wr_en_5;\n wire wr_ptr0__0;\n wire [3:0]wr_ptr_timing;\n\n (* SOFT_HLUTNM = \"soft_lutpair952\" *) \n LUT5 #(\n .INIT(32'hC0F0F0F2)) \n \\my_empty[1]_i_1__4 \n (.I0(my_empty0),\n .I1(\\my_full_reg_n_0_[3] ),\n .I2(\\my_empty_reg[1]_0 ),\n .I3(B_of_full),\n .I4(mux_cmd_wren),\n .O(\\my_empty[1]_i_1__4_n_0 ));\n LUT5 #(\n .INIT(32'hC0F0F0F2)) \n \\my_empty[6]_i_1 \n (.I0(my_empty0),\n .I1(\\my_full_reg_n_0_[3] ),\n .I2(\\my_empty_reg_n_0_[6] ),\n .I3(B_of_full),\n .I4(mux_cmd_wren),\n .O(\\my_empty[6]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h4A400D08)) \n \\my_empty[6]_i_2__0 \n (.I0(wr_ptr_timing[2]),\n .I1(\\my_empty[6]_i_3__0_n_0 ),\n .I2(wr_ptr_timing[3]),\n .I3(\\my_empty[6]_i_4__0_n_0 ),\n .I4(\\rd_ptr_timing_reg[2]_1 ),\n .O(my_empty0));\n (* SOFT_HLUTNM = \"soft_lutpair951\" *) \n LUT5 #(\n .INIT(32'h00000040)) \n \\my_empty[6]_i_3__0 \n (.I0(wr_ptr_timing[1]),\n .I1(\\rd_ptr_timing_reg[2]_3 ),\n .I2(\\rd_ptr_timing_reg[2]_2 ),\n .I3(\\rd_ptr_timing_reg[2]_0 ),\n .I4(wr_ptr_timing[0]),\n .O(\\my_empty[6]_i_3__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair951\" *) \n LUT5 #(\n .INIT(32'h84210842)) \n \\my_empty[6]_i_4__0 \n (.I0(wr_ptr_timing[0]),\n .I1(wr_ptr_timing[1]),\n .I2(\\rd_ptr_timing_reg[2]_3 ),\n .I3(\\rd_ptr_timing_reg[2]_2 ),\n .I4(\\rd_ptr_timing_reg[2]_0 ),\n .O(\\my_empty[6]_i_4__0_n_0 ));\n (* syn_maxfan = \"3\" *) \n FDSE #(\n .INIT(1'b1)) \n \\my_empty_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_empty[1]_i_1__4_n_0 ),\n .Q(\\my_empty_reg[1]_0 ),\n .S(SR));\n (* syn_maxfan = \"3\" *) \n FDSE #(\n .INIT(1'b1)) \n \\my_empty_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_empty[6]_i_1_n_0 ),\n .Q(\\my_empty_reg_n_0_[6] ),\n .S(SR));\n LUT6 #(\n .INIT(64'h00000000FF00FC80)) \n \\my_full[3]_i_1__0 \n (.I0(my_full0),\n .I1(mux_cmd_wren),\n .I2(B_of_full),\n .I3(\\my_full_reg_n_0_[3] ),\n .I4(\\my_empty_reg_n_0_[6] ),\n .I5(SR),\n .O(\\my_full[3]_i_1__0_n_0 ));\n LUT5 #(\n .INIT(32'h4A400D08)) \n \\my_full[3]_i_2__0 \n (.I0(rd_ptr_timing[2]),\n .I1(\\my_full[3]_i_3__0_n_0 ),\n .I2(rd_ptr_timing[3]),\n .I3(\\my_full[3]_i_4__0_n_0 ),\n .I4(Q[2]),\n .O(my_full0));\n (* SOFT_HLUTNM = \"soft_lutpair950\" *) \n LUT5 #(\n .INIT(32'h00000040)) \n \\my_full[3]_i_3__0 \n (.I0(rd_ptr_timing[1]),\n .I1(Q[0]),\n .I2(Q[1]),\n .I3(Q[3]),\n .I4(rd_ptr_timing[0]),\n .O(\\my_full[3]_i_3__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair950\" *) \n LUT5 #(\n .INIT(32'h84210842)) \n \\my_full[3]_i_4__0 \n (.I0(rd_ptr_timing[0]),\n .I1(rd_ptr_timing[1]),\n .I2(Q[0]),\n .I3(Q[1]),\n .I4(Q[3]),\n .O(\\my_full[3]_i_4__0_n_0 ));\n (* syn_maxfan = \"3\" *) \n FDRE #(\n .INIT(1'b0)) \n \\my_full_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_full[3]_i_1__0_n_0 ),\n .Q(\\my_full_reg_n_0_[3] ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair958\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_17\n (.I0(\\rd_ptr_reg[3]_0 [9]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D5[1]));\n (* SOFT_HLUTNM = \"soft_lutpair964\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_18__1\n (.I0(\\rd_ptr_reg[3]_0 [8]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D5[0]));\n (* SOFT_HLUTNM = \"soft_lutpair952\" *) \n LUT3 #(\n .INIT(8'h0D)) \n out_fifo_i_1__1\n (.I0(\\my_empty_reg[1]_0 ),\n .I1(mux_cmd_wren),\n .I2(B_of_full),\n .O(\\my_full_reg[3]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair960\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_23\n (.I0(\\rd_ptr_reg[3]_0 [13]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D6[3]));\n (* SOFT_HLUTNM = \"soft_lutpair964\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_24__0\n (.I0(\\rd_ptr_reg[3]_0 [12]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D6[2]));\n (* SOFT_HLUTNM = \"soft_lutpair959\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_25\n (.I0(\\rd_ptr_reg[3]_0 [11]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D6[1]));\n (* SOFT_HLUTNM = \"soft_lutpair962\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_26__0\n (.I0(\\rd_ptr_reg[3]_0 [10]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D6[0]));\n (* SOFT_HLUTNM = \"soft_lutpair965\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_27__0\n (.I0(\\rd_ptr_reg[3]_0 [17]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D7[3]));\n (* SOFT_HLUTNM = \"soft_lutpair961\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_28__0\n (.I0(\\rd_ptr_reg[3]_0 [16]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D7[2]));\n (* SOFT_HLUTNM = \"soft_lutpair957\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_29__0\n (.I0(\\rd_ptr_reg[3]_0 [15]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D7[1]));\n (* SOFT_HLUTNM = \"soft_lutpair961\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_2__1\n (.I0(\\rd_ptr_reg[3]_0 [1]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[5]));\n (* SOFT_HLUTNM = \"soft_lutpair965\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_30\n (.I0(\\rd_ptr_reg[3]_0 [14]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D7[0]));\n (* SOFT_HLUTNM = \"soft_lutpair958\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_3__1\n (.I0(\\rd_ptr_reg[3]_0 [0]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[4]));\n (* SOFT_HLUTNM = \"soft_lutpair962\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_4__1\n (.I0(\\rd_ptr_reg[3]_0 [5]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair959\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_5__1\n (.I0(\\rd_ptr_reg[3]_0 [4]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair960\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_6__1\n (.I0(\\rd_ptr_reg[3]_0 [3]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair957\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_7__0\n (.I0(\\rd_ptr_reg[3]_0 [2]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair963\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_8__0\n (.I0(\\rd_ptr_reg[3]_0 [7]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D3[1]));\n (* SOFT_HLUTNM = \"soft_lutpair963\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_9__0\n (.I0(\\rd_ptr_reg[3]_0 [6]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D3[0]));\n LUT4 #(\n .INIT(16'h082A)) \n p_17_out\n (.I0(mux_cmd_wren),\n .I1(B_of_full),\n .I2(\\my_full_reg_n_0_[3] ),\n .I3(\\my_empty_reg[1]_0 ),\n .O(wr_en_5));\n (* SOFT_HLUTNM = \"soft_lutpair955\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\rd_ptr[0]_i_1 \n (.I0(\\rd_ptr_timing_reg[2]_0 ),\n .I1(\\rd_ptr_timing_reg[2]_3 ),\n .O(nxt_rd_ptr[0]));\n (* SOFT_HLUTNM = \"soft_lutpair955\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\rd_ptr[1]_i_1__0 \n (.I0(\\rd_ptr_timing_reg[2]_0 ),\n .I1(\\rd_ptr_timing_reg[2]_3 ),\n .I2(\\rd_ptr_timing_reg[2]_2 ),\n .O(nxt_rd_ptr[1]));\n (* SOFT_HLUTNM = \"soft_lutpair953\" *) \n LUT4 #(\n .INIT(16'hAA6A)) \n \\rd_ptr[2]_i_1__0 \n (.I0(\\rd_ptr_timing_reg[2]_1 ),\n .I1(\\rd_ptr_timing_reg[2]_3 ),\n .I2(\\rd_ptr_timing_reg[2]_2 ),\n .I3(\\rd_ptr_timing_reg[2]_0 ),\n .O(nxt_rd_ptr[2]));\n LUT2 #(\n .INIT(4'h1)) \n \\rd_ptr[3]_i_1__0 \n (.I0(\\my_empty_reg_n_0_[6] ),\n .I1(B_of_full),\n .O(\\rd_ptr[3]_i_1__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair953\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\rd_ptr[3]_i_2 \n (.I0(\\rd_ptr_timing_reg[2]_0 ),\n .I1(\\rd_ptr_timing_reg[2]_2 ),\n .I2(\\rd_ptr_timing_reg[2]_3 ),\n .I3(\\rd_ptr_timing_reg[2]_1 ),\n .O(nxt_rd_ptr[3]));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[0] \n (.C(CLK),\n .CE(\\rd_ptr[3]_i_1__0_n_0 ),\n .D(nxt_rd_ptr[0]),\n .Q(\\rd_ptr_timing_reg[2]_3 ),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[1] \n (.C(CLK),\n .CE(\\rd_ptr[3]_i_1__0_n_0 ),\n .D(nxt_rd_ptr[1]),\n .Q(\\rd_ptr_timing_reg[2]_2 ),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[2] \n (.C(CLK),\n .CE(\\rd_ptr[3]_i_1__0_n_0 ),\n .D(nxt_rd_ptr[2]),\n .Q(\\rd_ptr_timing_reg[2]_1 ),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[3] \n (.C(CLK),\n .CE(\\rd_ptr[3]_i_1__0_n_0 ),\n .D(nxt_rd_ptr[3]),\n .Q(\\rd_ptr_timing_reg[2]_0 ),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[0] \n (.C(CLK),\n .CE(\\rd_ptr[3]_i_1__0_n_0 ),\n .D(nxt_rd_ptr[0]),\n .Q(rd_ptr_timing[0]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[1] \n (.C(CLK),\n .CE(\\rd_ptr[3]_i_1__0_n_0 ),\n .D(nxt_rd_ptr[1]),\n .Q(rd_ptr_timing[1]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[2] \n (.C(CLK),\n .CE(\\rd_ptr[3]_i_1__0_n_0 ),\n .D(nxt_rd_ptr[2]),\n .Q(rd_ptr_timing[2]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[3] \n (.C(CLK),\n .CE(\\rd_ptr[3]_i_1__0_n_0 ),\n .D(nxt_rd_ptr[3]),\n .Q(rd_ptr_timing[3]),\n .R(SR));\n LUT4 #(\n .INIT(16'h082A)) \n wr_ptr0\n (.I0(mux_cmd_wren),\n .I1(B_of_full),\n .I2(\\my_full_reg_n_0_[3] ),\n .I3(\\my_empty_reg_n_0_[6] ),\n .O(wr_ptr0__0));\n (* SOFT_HLUTNM = \"soft_lutpair956\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\wr_ptr[0]_i_1__0 \n (.I0(Q[3]),\n .I1(Q[0]),\n .O(nxt_wr_ptr[0]));\n (* SOFT_HLUTNM = \"soft_lutpair956\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\wr_ptr[1]_i_1__0 \n (.I0(Q[3]),\n .I1(Q[0]),\n .I2(Q[1]),\n .O(nxt_wr_ptr[1]));\n (* SOFT_HLUTNM = \"soft_lutpair954\" *) \n LUT4 #(\n .INIT(16'hAA6A)) \n \\wr_ptr[2]_i_1__0 \n (.I0(Q[2]),\n .I1(Q[0]),\n .I2(Q[1]),\n .I3(Q[3]),\n .O(nxt_wr_ptr[2]));\n (* SOFT_HLUTNM = \"soft_lutpair954\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\wr_ptr[3]_i_1__0 \n (.I0(Q[3]),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(Q[2]),\n .O(nxt_wr_ptr[3]));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[0] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[0]),\n .Q(Q[0]),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[1] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[1]),\n .Q(Q[1]),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[2] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[2]),\n .Q(Q[2]),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[3] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[3]),\n .Q(Q[3]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[0] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[0]),\n .Q(wr_ptr_timing[0]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[1] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[1]),\n .Q(wr_ptr_timing[1]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[2] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[2]),\n .Q(wr_ptr_timing[2]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[3] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[3]),\n .Q(wr_ptr_timing[3]),\n .R(SR));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_of_pre_fifo\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized8\n (\\rd_ptr_timing_reg[2]_0 ,\n \\rd_ptr_timing_reg[2]_1 ,\n \\rd_ptr_timing_reg[2]_2 ,\n \\rd_ptr_timing_reg[2]_3 ,\n wr_en_6,\n \\my_empty_reg[1]_0 ,\n D2,\n D3,\n \\rd_ptr_timing_reg[0]_0 ,\n D0,\n D1,\n D4,\n D7,\n D8,\n D9,\n Q,\n SR,\n CLK,\n mux_cmd_wren,\n ofifo_rst_reg,\n \\rd_ptr_reg[3]_0 );\n output \\rd_ptr_timing_reg[2]_0 ;\n output \\rd_ptr_timing_reg[2]_1 ;\n output \\rd_ptr_timing_reg[2]_2 ;\n output \\rd_ptr_timing_reg[2]_3 ;\n output wr_en_6;\n output \\my_empty_reg[1]_0 ;\n output [4:0]D2;\n output [4:0]D3;\n output \\rd_ptr_timing_reg[0]_0 ;\n output [5:0]D0;\n output [3:0]D1;\n output [3:0]D4;\n output [3:0]D7;\n output [3:0]D8;\n output [1:0]D9;\n output [3:0]Q;\n input [0:0]SR;\n input CLK;\n input mux_cmd_wren;\n input ofifo_rst_reg;\n input [33:0]\\rd_ptr_reg[3]_0 ;\n\n wire CLK;\n wire [5:0]D0;\n wire [3:0]D1;\n wire [4:0]D2;\n wire [4:0]D3;\n wire [3:0]D4;\n wire [3:0]D7;\n wire [3:0]D8;\n wire [1:0]D9;\n wire [3:0]Q;\n wire [0:0]SR;\n wire mux_cmd_wren;\n wire my_empty0;\n wire \\my_empty[1]_i_1__5_n_0 ;\n wire \\my_empty[6]_i_1__0_n_0 ;\n wire \\my_empty[6]_i_3__1_n_0 ;\n wire \\my_empty[6]_i_4__1_n_0 ;\n wire \\my_empty_reg[1]_0 ;\n wire \\my_empty_reg_n_0_[6] ;\n wire my_full0;\n wire \\my_full[3]_i_1__1_n_0 ;\n wire \\my_full[3]_i_3__1_n_0 ;\n wire \\my_full[3]_i_4__1_n_0 ;\n wire \\my_full_reg_n_0_[3] ;\n wire [3:0]nxt_rd_ptr;\n wire [3:0]nxt_wr_ptr;\n wire ofifo_rst_reg;\n wire \\rd_ptr[3]_i_1__1_n_0 ;\n wire [33:0]\\rd_ptr_reg[3]_0 ;\n wire [3:0]rd_ptr_timing;\n wire \\rd_ptr_timing_reg[0]_0 ;\n wire \\rd_ptr_timing_reg[2]_0 ;\n wire \\rd_ptr_timing_reg[2]_1 ;\n wire \\rd_ptr_timing_reg[2]_2 ;\n wire \\rd_ptr_timing_reg[2]_3 ;\n wire wr_en_6;\n wire wr_ptr0__0;\n wire [3:0]wr_ptr_timing;\n\n (* SOFT_HLUTNM = \"soft_lutpair968\" *) \n LUT5 #(\n .INIT(32'hC0F0F0F2)) \n \\my_empty[1]_i_1__5 \n (.I0(my_empty0),\n .I1(\\my_full_reg_n_0_[3] ),\n .I2(\\my_empty_reg[1]_0 ),\n .I3(ofifo_rst_reg),\n .I4(mux_cmd_wren),\n .O(\\my_empty[1]_i_1__5_n_0 ));\n LUT5 #(\n .INIT(32'hC0F0F0F2)) \n \\my_empty[6]_i_1__0 \n (.I0(my_empty0),\n .I1(\\my_full_reg_n_0_[3] ),\n .I2(\\my_empty_reg_n_0_[6] ),\n .I3(ofifo_rst_reg),\n .I4(mux_cmd_wren),\n .O(\\my_empty[6]_i_1__0_n_0 ));\n LUT5 #(\n .INIT(32'h4A400D08)) \n \\my_empty[6]_i_2__1 \n (.I0(wr_ptr_timing[2]),\n .I1(\\my_empty[6]_i_3__1_n_0 ),\n .I2(wr_ptr_timing[3]),\n .I3(\\my_empty[6]_i_4__1_n_0 ),\n .I4(\\rd_ptr_timing_reg[2]_1 ),\n .O(my_empty0));\n (* SOFT_HLUTNM = \"soft_lutpair966\" *) \n LUT5 #(\n .INIT(32'h00000040)) \n \\my_empty[6]_i_3__1 \n (.I0(wr_ptr_timing[1]),\n .I1(\\rd_ptr_timing_reg[2]_3 ),\n .I2(\\rd_ptr_timing_reg[2]_2 ),\n .I3(\\rd_ptr_timing_reg[2]_0 ),\n .I4(wr_ptr_timing[0]),\n .O(\\my_empty[6]_i_3__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair966\" *) \n LUT5 #(\n .INIT(32'h84210842)) \n \\my_empty[6]_i_4__1 \n (.I0(wr_ptr_timing[0]),\n .I1(wr_ptr_timing[1]),\n .I2(\\rd_ptr_timing_reg[2]_3 ),\n .I3(\\rd_ptr_timing_reg[2]_2 ),\n .I4(\\rd_ptr_timing_reg[2]_0 ),\n .O(\\my_empty[6]_i_4__1_n_0 ));\n (* syn_maxfan = \"3\" *) \n FDSE #(\n .INIT(1'b1)) \n \\my_empty_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_empty[1]_i_1__5_n_0 ),\n .Q(\\my_empty_reg[1]_0 ),\n .S(SR));\n (* syn_maxfan = \"3\" *) \n FDSE #(\n .INIT(1'b1)) \n \\my_empty_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_empty[6]_i_1__0_n_0 ),\n .Q(\\my_empty_reg_n_0_[6] ),\n .S(SR));\n LUT6 #(\n .INIT(64'h00000000FF00FC80)) \n \\my_full[3]_i_1__1 \n (.I0(my_full0),\n .I1(mux_cmd_wren),\n .I2(ofifo_rst_reg),\n .I3(\\my_full_reg_n_0_[3] ),\n .I4(\\my_empty_reg_n_0_[6] ),\n .I5(SR),\n .O(\\my_full[3]_i_1__1_n_0 ));\n LUT5 #(\n .INIT(32'h4A400D08)) \n \\my_full[3]_i_2__1 \n (.I0(rd_ptr_timing[2]),\n .I1(\\my_full[3]_i_3__1_n_0 ),\n .I2(rd_ptr_timing[3]),\n .I3(\\my_full[3]_i_4__1_n_0 ),\n .I4(Q[2]),\n .O(my_full0));\n (* SOFT_HLUTNM = \"soft_lutpair967\" *) \n LUT5 #(\n .INIT(32'h00000040)) \n \\my_full[3]_i_3__1 \n (.I0(rd_ptr_timing[1]),\n .I1(Q[0]),\n .I2(Q[1]),\n .I3(Q[3]),\n .I4(rd_ptr_timing[0]),\n .O(\\my_full[3]_i_3__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair967\" *) \n LUT5 #(\n .INIT(32'h84210842)) \n \\my_full[3]_i_4__1 \n (.I0(rd_ptr_timing[0]),\n .I1(rd_ptr_timing[1]),\n .I2(Q[0]),\n .I3(Q[1]),\n .I4(Q[3]),\n .O(\\my_full[3]_i_4__1_n_0 ));\n (* syn_maxfan = \"3\" *) \n FDRE #(\n .INIT(1'b0)) \n \\my_full_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_full[3]_i_1__1_n_0 ),\n .Q(\\my_full_reg_n_0_[3] ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair982\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_10__1\n (.I0(\\rd_ptr_reg[3]_0 [7]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D1[1]));\n (* SOFT_HLUTNM = \"soft_lutpair976\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_11__1\n (.I0(\\rd_ptr_reg[3]_0 [6]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D1[0]));\n (* SOFT_HLUTNM = \"soft_lutpair983\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_12__1\n (.I0(\\rd_ptr_reg[3]_0 [14]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D2[4]));\n (* SOFT_HLUTNM = \"soft_lutpair979\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_13__1\n (.I0(\\rd_ptr_reg[3]_0 [13]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D2[3]));\n (* SOFT_HLUTNM = \"soft_lutpair976\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_14__0\n (.I0(\\rd_ptr_reg[3]_0 [12]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D2[2]));\n (* SOFT_HLUTNM = \"soft_lutpair978\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_15\n (.I0(\\rd_ptr_reg[3]_0 [11]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D2[1]));\n (* SOFT_HLUTNM = \"soft_lutpair975\" *) \n LUT2 #(\n .INIT(4'hE)) \n out_fifo_i_16\n (.I0(\\rd_ptr_reg[3]_0 [10]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D2[0]));\n (* SOFT_HLUTNM = \"soft_lutpair968\" *) \n LUT3 #(\n .INIT(8'h0D)) \n out_fifo_i_1__2\n (.I0(\\my_empty_reg[1]_0 ),\n .I1(mux_cmd_wren),\n .I2(ofifo_rst_reg),\n .O(\\rd_ptr_timing_reg[0]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair986\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_20__0\n (.I0(\\rd_ptr_reg[3]_0 [19]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D3[4]));\n (* SOFT_HLUTNM = \"soft_lutpair979\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_21__0\n (.I0(\\rd_ptr_reg[3]_0 [18]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D3[3]));\n (* SOFT_HLUTNM = \"soft_lutpair987\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_22\n (.I0(\\rd_ptr_reg[3]_0 [17]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D3[2]));\n (* SOFT_HLUTNM = \"soft_lutpair978\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_23__0\n (.I0(\\rd_ptr_reg[3]_0 [16]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D3[1]));\n (* SOFT_HLUTNM = \"soft_lutpair985\" *) \n LUT2 #(\n .INIT(4'hE)) \n out_fifo_i_24\n (.I0(\\rd_ptr_reg[3]_0 [15]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D3[0]));\n (* SOFT_HLUTNM = \"soft_lutpair988\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_28__1\n (.I0(\\rd_ptr_reg[3]_0 [23]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D4[3]));\n (* SOFT_HLUTNM = \"soft_lutpair973\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_29__1\n (.I0(\\rd_ptr_reg[3]_0 [22]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D4[2]));\n (* SOFT_HLUTNM = \"soft_lutpair980\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_2__2\n (.I0(\\rd_ptr_reg[3]_0 [1]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[5]));\n (* SOFT_HLUTNM = \"soft_lutpair989\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_30__0\n (.I0(\\rd_ptr_reg[3]_0 [21]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D4[1]));\n (* SOFT_HLUTNM = \"soft_lutpair983\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_31\n (.I0(\\rd_ptr_reg[3]_0 [20]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D4[0]));\n (* SOFT_HLUTNM = \"soft_lutpair975\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_3__2\n (.I0(\\rd_ptr_reg[3]_0 [0]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[4]));\n (* SOFT_HLUTNM = \"soft_lutpair982\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_4__2\n (.I0(\\rd_ptr_reg[3]_0 [5]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair988\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_52__0\n (.I0(\\rd_ptr_reg[3]_0 [27]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D7[3]));\n (* SOFT_HLUTNM = \"soft_lutpair977\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_53__0\n (.I0(\\rd_ptr_reg[3]_0 [26]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D7[2]));\n (* SOFT_HLUTNM = \"soft_lutpair985\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_54\n (.I0(\\rd_ptr_reg[3]_0 [25]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D7[1]));\n (* SOFT_HLUTNM = \"soft_lutpair981\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_55\n (.I0(\\rd_ptr_reg[3]_0 [24]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D7[0]));\n (* SOFT_HLUTNM = \"soft_lutpair977\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_5__2\n (.I0(\\rd_ptr_reg[3]_0 [4]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair986\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_60__0\n (.I0(\\rd_ptr_reg[3]_0 [31]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D8[3]));\n (* SOFT_HLUTNM = \"soft_lutpair984\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_61__0\n (.I0(\\rd_ptr_reg[3]_0 [30]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D8[2]));\n (* SOFT_HLUTNM = \"soft_lutpair989\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_62\n (.I0(\\rd_ptr_reg[3]_0 [29]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D8[1]));\n (* SOFT_HLUTNM = \"soft_lutpair974\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_63\n (.I0(\\rd_ptr_reg[3]_0 [28]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D8[0]));\n (* SOFT_HLUTNM = \"soft_lutpair987\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_68__0\n (.I0(\\rd_ptr_reg[3]_0 [33]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D9[1]));\n (* SOFT_HLUTNM = \"soft_lutpair984\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_69__0\n (.I0(\\rd_ptr_reg[3]_0 [32]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D9[0]));\n (* SOFT_HLUTNM = \"soft_lutpair980\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_6__2\n (.I0(\\rd_ptr_reg[3]_0 [3]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair973\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_7__1\n (.I0(\\rd_ptr_reg[3]_0 [2]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair981\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_8__1\n (.I0(\\rd_ptr_reg[3]_0 [9]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D1[3]));\n (* SOFT_HLUTNM = \"soft_lutpair974\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_9__1\n (.I0(\\rd_ptr_reg[3]_0 [8]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D1[2]));\n LUT4 #(\n .INIT(16'h082A)) \n p_17_out\n (.I0(mux_cmd_wren),\n .I1(ofifo_rst_reg),\n .I2(\\my_full_reg_n_0_[3] ),\n .I3(\\my_empty_reg[1]_0 ),\n .O(wr_en_6));\n (* SOFT_HLUTNM = \"soft_lutpair972\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\rd_ptr[0]_i_1__0 \n (.I0(\\rd_ptr_timing_reg[2]_0 ),\n .I1(\\rd_ptr_timing_reg[2]_3 ),\n .O(nxt_rd_ptr[0]));\n (* SOFT_HLUTNM = \"soft_lutpair972\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\rd_ptr[1]_i_1__1 \n (.I0(\\rd_ptr_timing_reg[2]_0 ),\n .I1(\\rd_ptr_timing_reg[2]_3 ),\n .I2(\\rd_ptr_timing_reg[2]_2 ),\n .O(nxt_rd_ptr[1]));\n (* SOFT_HLUTNM = \"soft_lutpair969\" *) \n LUT4 #(\n .INIT(16'hAA6A)) \n \\rd_ptr[2]_i_1__1 \n (.I0(\\rd_ptr_timing_reg[2]_1 ),\n .I1(\\rd_ptr_timing_reg[2]_3 ),\n .I2(\\rd_ptr_timing_reg[2]_2 ),\n .I3(\\rd_ptr_timing_reg[2]_0 ),\n .O(nxt_rd_ptr[2]));\n LUT2 #(\n .INIT(4'h1)) \n \\rd_ptr[3]_i_1__1 \n (.I0(\\my_empty_reg_n_0_[6] ),\n .I1(ofifo_rst_reg),\n .O(\\rd_ptr[3]_i_1__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair969\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\rd_ptr[3]_i_2__0 \n (.I0(\\rd_ptr_timing_reg[2]_0 ),\n .I1(\\rd_ptr_timing_reg[2]_2 ),\n .I2(\\rd_ptr_timing_reg[2]_3 ),\n .I3(\\rd_ptr_timing_reg[2]_1 ),\n .O(nxt_rd_ptr[3]));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[0] \n (.C(CLK),\n .CE(\\rd_ptr[3]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[0]),\n .Q(\\rd_ptr_timing_reg[2]_3 ),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[1] \n (.C(CLK),\n .CE(\\rd_ptr[3]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[1]),\n .Q(\\rd_ptr_timing_reg[2]_2 ),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[2] \n (.C(CLK),\n .CE(\\rd_ptr[3]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[2]),\n .Q(\\rd_ptr_timing_reg[2]_1 ),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[3] \n (.C(CLK),\n .CE(\\rd_ptr[3]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[3]),\n .Q(\\rd_ptr_timing_reg[2]_0 ),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[0] \n (.C(CLK),\n .CE(\\rd_ptr[3]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[0]),\n .Q(rd_ptr_timing[0]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[1] \n (.C(CLK),\n .CE(\\rd_ptr[3]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[1]),\n .Q(rd_ptr_timing[1]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[2] \n (.C(CLK),\n .CE(\\rd_ptr[3]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[2]),\n .Q(rd_ptr_timing[2]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[3] \n (.C(CLK),\n .CE(\\rd_ptr[3]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[3]),\n .Q(rd_ptr_timing[3]),\n .R(SR));\n LUT4 #(\n .INIT(16'h082A)) \n wr_ptr0\n (.I0(mux_cmd_wren),\n .I1(ofifo_rst_reg),\n .I2(\\my_full_reg_n_0_[3] ),\n .I3(\\my_empty_reg_n_0_[6] ),\n .O(wr_ptr0__0));\n (* SOFT_HLUTNM = \"soft_lutpair971\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\wr_ptr[0]_i_1__1 \n (.I0(Q[3]),\n .I1(Q[0]),\n .O(nxt_wr_ptr[0]));\n (* SOFT_HLUTNM = \"soft_lutpair971\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\wr_ptr[1]_i_1__1 \n (.I0(Q[3]),\n .I1(Q[0]),\n .I2(Q[1]),\n .O(nxt_wr_ptr[1]));\n (* SOFT_HLUTNM = \"soft_lutpair970\" *) \n LUT4 #(\n .INIT(16'hAA6A)) \n \\wr_ptr[2]_i_1__1 \n (.I0(Q[2]),\n .I1(Q[0]),\n .I2(Q[1]),\n .I3(Q[3]),\n .O(nxt_wr_ptr[2]));\n (* SOFT_HLUTNM = \"soft_lutpair970\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\wr_ptr[3]_i_1__1 \n (.I0(Q[3]),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(Q[2]),\n .O(nxt_wr_ptr[3]));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[0] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[0]),\n .Q(Q[0]),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[1] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[1]),\n .Q(Q[1]),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[2] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[2]),\n .Q(Q[2]),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[3] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[3]),\n .Q(Q[3]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[0] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[0]),\n .Q(wr_ptr_timing[0]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[1] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[1]),\n .Q(wr_ptr_timing[1]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[2] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[2]),\n .Q(wr_ptr_timing[2]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[3] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[3]),\n .Q(wr_ptr_timing[3]),\n .R(SR));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_of_pre_fifo\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_of_pre_fifo__parameterized9\n (D9,\n \\my_empty_reg[1]_0 ,\n \\my_empty_reg[7]_0 ,\n D0,\n D1,\n D2,\n D3,\n D4,\n D5,\n D6,\n D7,\n D8,\n \\my_empty_reg[7]_1 ,\n SR,\n CLK,\n init_calib_complete_reg_rep__5,\n mc_cas_n,\n mc_address,\n init_calib_complete_reg_rep,\n mux_cmd_wren,\n ofifo_rst_reg,\n phy_dout,\n init_calib_complete_reg_rep__6);\n output [7:0]D9;\n output \\my_empty_reg[1]_0 ;\n output \\my_empty_reg[7]_0 ;\n output [5:0]D0;\n output [3:0]D1;\n output [3:0]D2;\n output [3:0]D3;\n output [3:0]D4;\n output [3:0]D5;\n output [3:0]D6;\n output [3:0]D7;\n output [3:0]D8;\n output [31:0]\\my_empty_reg[7]_1 ;\n input [0:0]SR;\n input CLK;\n input init_calib_complete_reg_rep__5;\n input [0:0]mc_cas_n;\n input [1:0]mc_address;\n input init_calib_complete_reg_rep;\n input mux_cmd_wren;\n input ofifo_rst_reg;\n input [35:0]phy_dout;\n input init_calib_complete_reg_rep__6;\n\n wire CLK;\n wire [5:0]D0;\n wire [3:0]D1;\n wire [3:0]D2;\n wire [3:0]D3;\n wire [3:0]D4;\n wire [3:0]D5;\n wire [3:0]D6;\n wire [3:0]D7;\n wire [3:0]D8;\n wire [7:0]D9;\n wire [0:0]SR;\n wire init_calib_complete_reg_rep;\n wire init_calib_complete_reg_rep__5;\n wire init_calib_complete_reg_rep__6;\n wire [1:0]mc_address;\n wire [0:0]mc_cas_n;\n wire [77:0]mem_out;\n wire mux_cmd_wren;\n wire my_empty0;\n wire \\my_empty[1]_i_1_n_0 ;\n wire \\my_empty[7]_i_1_n_0 ;\n wire \\my_empty[7]_i_3_n_0 ;\n wire \\my_empty[7]_i_4_n_0 ;\n wire \\my_empty_reg[1]_0 ;\n wire \\my_empty_reg[7]_0 ;\n wire [31:0]\\my_empty_reg[7]_1 ;\n wire \\my_empty_reg_n_0_[7] ;\n wire my_full0;\n wire \\my_full[4]_i_1_n_0 ;\n wire \\my_full[4]_i_3_n_0 ;\n wire \\my_full[4]_i_4_n_0 ;\n wire \\my_full_reg_n_0_[4] ;\n wire [3:0]nxt_rd_ptr;\n wire [3:0]nxt_wr_ptr;\n wire ofifo_rst_reg;\n wire [35:0]phy_dout;\n wire [3:0]rd_ptr;\n wire [3:0]rd_ptr_timing;\n wire \\rd_ptr_timing[3]_i_1_n_0 ;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) wire wr_en;\n wire [3:0]wr_ptr;\n wire wr_ptr0__0;\n wire [3:0]wr_ptr_timing;\n wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED;\n\n (* SOFT_HLUTNM = \"soft_lutpair1000\" *) \n LUT3 #(\n .INIT(8'hAC)) \n d_out\n (.I0(init_calib_complete_reg_rep__6),\n .I1(mem_out[75]),\n .I2(\\my_empty_reg[1]_0 ),\n .O(D9[3]));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_0_5\n (.ADDRA({1'b0,rd_ptr}),\n .ADDRB({1'b0,rd_ptr}),\n .ADDRC({1'b0,rd_ptr}),\n .ADDRD({1'b0,wr_ptr}),\n .DIA({1'b0,1'b0}),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[1:0]),\n .DOB(mem_out[3:2]),\n .DOC(mem_out[5:4]),\n .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_12_17\n (.ADDRA({1'b0,rd_ptr}),\n .ADDRB({1'b0,rd_ptr}),\n .ADDRC({1'b0,rd_ptr}),\n .ADDRD({1'b0,wr_ptr}),\n .DIA({1'b0,1'b0}),\n .DIB({1'b0,1'b0}),\n .DIC(phy_dout[5:4]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[13:12]),\n .DOB(mem_out[15:14]),\n .DOC(\\my_empty_reg[7]_1 [5:4]),\n .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_18_23\n (.ADDRA({1'b0,rd_ptr}),\n .ADDRB({1'b0,rd_ptr}),\n .ADDRC({1'b0,rd_ptr}),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[7:6]),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [7:6]),\n .DOB(mem_out[21:20]),\n .DOC(mem_out[23:22]),\n .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_24_29\n (.ADDRA({1'b0,rd_ptr}),\n .ADDRB({1'b0,rd_ptr}),\n .ADDRC({1'b0,rd_ptr}),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[9:8]),\n .DIB(phy_dout[11:10]),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [9:8]),\n .DOB(\\my_empty_reg[7]_1 [11:10]),\n .DOC(mem_out[29:28]),\n .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_30_35\n (.ADDRA({1'b0,rd_ptr}),\n .ADDRB({1'b0,rd_ptr}),\n .ADDRC({1'b0,rd_ptr}),\n .ADDRD({1'b0,wr_ptr}),\n .DIA({1'b0,1'b0}),\n .DIB(phy_dout[13:12]),\n .DIC(phy_dout[15:14]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[31:30]),\n .DOB(\\my_empty_reg[7]_1 [13:12]),\n .DOC(\\my_empty_reg[7]_1 [15:14]),\n .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_36_41\n (.ADDRA({1'b0,rd_ptr}),\n .ADDRB({1'b0,rd_ptr}),\n .ADDRC({1'b0,rd_ptr}),\n .ADDRD({1'b0,wr_ptr}),\n .DIA({1'b0,1'b0}),\n .DIB({1'b0,1'b0}),\n .DIC(phy_dout[17:16]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[37:36]),\n .DOB(mem_out[39:38]),\n .DOC(\\my_empty_reg[7]_1 [17:16]),\n .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_42_47\n (.ADDRA({1'b0,rd_ptr}),\n .ADDRB({1'b0,rd_ptr}),\n .ADDRC({1'b0,rd_ptr}),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[19:18]),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [19:18]),\n .DOB(mem_out[45:44]),\n .DOC(mem_out[47:46]),\n .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_48_53\n (.ADDRA({1'b0,rd_ptr}),\n .ADDRB({1'b0,rd_ptr}),\n .ADDRC({1'b0,rd_ptr}),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[21:20]),\n .DIB(phy_dout[23:22]),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [21:20]),\n .DOB(\\my_empty_reg[7]_1 [23:22]),\n .DOC(mem_out[53:52]),\n .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_54_59\n (.ADDRA({1'b0,rd_ptr}),\n .ADDRB({1'b0,rd_ptr}),\n .ADDRC({1'b0,rd_ptr}),\n .ADDRD({1'b0,wr_ptr}),\n .DIA({1'b0,1'b0}),\n .DIB(phy_dout[25:24]),\n .DIC(phy_dout[27:26]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[55:54]),\n .DOB(\\my_empty_reg[7]_1 [25:24]),\n .DOC(\\my_empty_reg[7]_1 [27:26]),\n .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_60_65\n (.ADDRA({1'b0,rd_ptr}),\n .ADDRB({1'b0,rd_ptr}),\n .ADDRC({1'b0,rd_ptr}),\n .ADDRD({1'b0,wr_ptr}),\n .DIA({1'b0,1'b0}),\n .DIB({1'b0,1'b0}),\n .DIC(phy_dout[29:28]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[61:60]),\n .DOB(mem_out[63:62]),\n .DOC(\\my_empty_reg[7]_1 [29:28]),\n .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_66_71\n (.ADDRA({1'b0,rd_ptr}),\n .ADDRB({1'b0,rd_ptr}),\n .ADDRC({1'b0,rd_ptr}),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[31:30]),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [31:30]),\n .DOB(mem_out[69:68]),\n .DOC(mem_out[71:70]),\n .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_6_11\n (.ADDRA({1'b0,rd_ptr}),\n .ADDRB({1'b0,rd_ptr}),\n .ADDRC({1'b0,rd_ptr}),\n .ADDRD({1'b0,wr_ptr}),\n .DIA({1'b0,1'b0}),\n .DIB(phy_dout[1:0]),\n .DIC(phy_dout[3:2]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[7:6]),\n .DOB(\\my_empty_reg[7]_1 [1:0]),\n .DOC(\\my_empty_reg[7]_1 [3:2]),\n .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)) \n mem_reg_0_15_72_77\n (.ADDRA({1'b0,rd_ptr}),\n .ADDRB({1'b0,rd_ptr}),\n .ADDRC({1'b0,rd_ptr}),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[33:32]),\n .DIB(phy_dout[35:34]),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[73:72]),\n .DOB(mem_out[75:74]),\n .DOC(mem_out[77:76]),\n .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n LUT6 #(\n .INIT(64'hFFFFFFFFF071F070)) \n \\my_empty[1]_i_1 \n (.I0(mux_cmd_wren),\n .I1(ofifo_rst_reg),\n .I2(\\my_empty_reg[1]_0 ),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(my_empty0),\n .I5(SR),\n .O(\\my_empty[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFF071F070)) \n \\my_empty[7]_i_1 \n (.I0(mux_cmd_wren),\n .I1(ofifo_rst_reg),\n .I2(\\my_empty_reg_n_0_[7] ),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(my_empty0),\n .I5(SR),\n .O(\\my_empty[7]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h4A400D08)) \n \\my_empty[7]_i_2 \n (.I0(wr_ptr_timing[2]),\n .I1(\\my_empty[7]_i_3_n_0 ),\n .I2(wr_ptr_timing[3]),\n .I3(\\my_empty[7]_i_4_n_0 ),\n .I4(rd_ptr[2]),\n .O(my_empty0));\n (* SOFT_HLUTNM = \"soft_lutpair990\" *) \n LUT5 #(\n .INIT(32'h00000040)) \n \\my_empty[7]_i_3 \n (.I0(wr_ptr_timing[1]),\n .I1(rd_ptr[0]),\n .I2(rd_ptr[1]),\n .I3(rd_ptr[3]),\n .I4(wr_ptr_timing[0]),\n .O(\\my_empty[7]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair990\" *) \n LUT5 #(\n .INIT(32'h84210842)) \n \\my_empty[7]_i_4 \n (.I0(wr_ptr_timing[0]),\n .I1(wr_ptr_timing[1]),\n .I2(rd_ptr[0]),\n .I3(rd_ptr[1]),\n .I4(rd_ptr[3]),\n .O(\\my_empty[7]_i_4_n_0 ));\n (* syn_maxfan = \"3\" *) \n FDRE #(\n .INIT(1'b0)) \n \\my_empty_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_empty[1]_i_1_n_0 ),\n .Q(\\my_empty_reg[1]_0 ),\n .R(1'b0));\n (* syn_maxfan = \"3\" *) \n FDRE #(\n .INIT(1'b0)) \n \\my_empty_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_empty[7]_i_1_n_0 ),\n .Q(\\my_empty_reg_n_0_[7] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000FF00FC80)) \n \\my_full[4]_i_1 \n (.I0(my_full0),\n .I1(mux_cmd_wren),\n .I2(ofifo_rst_reg),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(\\my_empty_reg_n_0_[7] ),\n .I5(SR),\n .O(\\my_full[4]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h4A400D08)) \n \\my_full[4]_i_2 \n (.I0(rd_ptr_timing[2]),\n .I1(\\my_full[4]_i_3_n_0 ),\n .I2(rd_ptr_timing[3]),\n .I3(\\my_full[4]_i_4_n_0 ),\n .I4(wr_ptr[2]),\n .O(my_full0));\n (* SOFT_HLUTNM = \"soft_lutpair991\" *) \n LUT5 #(\n .INIT(32'h00000040)) \n \\my_full[4]_i_3 \n (.I0(rd_ptr_timing[1]),\n .I1(wr_ptr[0]),\n .I2(wr_ptr[1]),\n .I3(wr_ptr[3]),\n .I4(rd_ptr_timing[0]),\n .O(\\my_full[4]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair991\" *) \n LUT5 #(\n .INIT(32'h84210842)) \n \\my_full[4]_i_4 \n (.I0(rd_ptr_timing[0]),\n .I1(rd_ptr_timing[1]),\n .I2(wr_ptr[0]),\n .I3(wr_ptr[1]),\n .I4(wr_ptr[3]),\n .O(\\my_full[4]_i_4_n_0 ));\n (* syn_maxfan = \"3\" *) \n FDRE #(\n .INIT(1'b0)) \n \\my_full_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_full[4]_i_1_n_0 ),\n .Q(\\my_full_reg_n_0_[4] ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair998\" *) \n LUT3 #(\n .INIT(8'h0D)) \n out_fifo_i_1\n (.I0(\\my_empty_reg[1]_0 ),\n .I1(mux_cmd_wren),\n .I2(ofifo_rst_reg),\n .O(\\my_empty_reg[7]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1006\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_10\n (.I0(mem_out[15]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D1[3]));\n (* SOFT_HLUTNM = \"soft_lutpair995\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_11\n (.I0(mem_out[14]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D1[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1009\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_12\n (.I0(mem_out[13]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D1[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1000\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_13\n (.I0(mem_out[12]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D1[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1010\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_18\n (.I0(mem_out[23]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D2[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1003\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_19\n (.I0(mem_out[22]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D2[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1007\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_2\n (.I0(mem_out[7]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[5]));\n (* SOFT_HLUTNM = \"soft_lutpair1010\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_20\n (.I0(mem_out[21]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D2[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1002\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_21\n (.I0(mem_out[20]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D2[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1015\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_26\n (.I0(mem_out[31]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D3[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1003\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_27\n (.I0(mem_out[30]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D3[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1016\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_28\n (.I0(mem_out[29]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D3[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1005\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_29\n (.I0(mem_out[28]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D3[0]));\n (* SOFT_HLUTNM = \"soft_lutpair996\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_3\n (.I0(mem_out[6]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[4]));\n (* SOFT_HLUTNM = \"soft_lutpair1018\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_34\n (.I0(mem_out[39]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D4[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1004\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_35\n (.I0(mem_out[38]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D4[2]));\n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_36\n (.I0(mem_out[37]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D4[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1008\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_37\n (.I0(mem_out[36]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D4[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1008\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_4\n (.I0(mem_out[5]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1017\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_42\n (.I0(mem_out[47]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D5[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1006\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_43\n (.I0(mem_out[46]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D5[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1014\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_44\n (.I0(mem_out[45]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D5[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1004\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_45\n (.I0(mem_out[44]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D5[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1001\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_5\n (.I0(mem_out[4]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1014\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_50\n (.I0(mem_out[55]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D6[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1011\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_51\n (.I0(mem_out[54]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D6[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1015\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_52\n (.I0(mem_out[53]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D6[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1011\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_53\n (.I0(mem_out[52]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D6[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1012\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_58\n (.I0(mem_out[63]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D7[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1002\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_59\n (.I0(mem_out[62]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D7[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1005\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_6\n (.I0(mem_out[3]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1016\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_60\n (.I0(mem_out[61]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D7[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1007\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_61\n (.I0(mem_out[60]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D7[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1017\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_66\n (.I0(mem_out[71]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D8[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1012\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_67\n (.I0(mem_out[70]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D8[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1013\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_68\n (.I0(mem_out[69]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D8[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1001\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_69\n (.I0(mem_out[68]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D8[0]));\n (* SOFT_HLUTNM = \"soft_lutpair994\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_7\n (.I0(mem_out[2]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1018\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_74\n (.I0(mem_out[77]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D9[5]));\n (* SOFT_HLUTNM = \"soft_lutpair1013\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_75\n (.I0(mem_out[76]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D9[4]));\n (* SOFT_HLUTNM = \"soft_lutpair996\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_76\n (.I0(mc_address[1]),\n .I1(init_calib_complete_reg_rep),\n .I2(mem_out[74]),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[2]));\n (* SOFT_HLUTNM = \"soft_lutpair995\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_77\n (.I0(init_calib_complete_reg_rep__5),\n .I1(mc_cas_n),\n .I2(mem_out[73]),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[1]));\n (* SOFT_HLUTNM = \"soft_lutpair994\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_78\n (.I0(mc_address[0]),\n .I1(init_calib_complete_reg_rep),\n .I2(mem_out[72]),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1009\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_8\n (.I0(mem_out[1]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D9[7]));\n (* SOFT_HLUTNM = \"soft_lutpair998\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_9\n (.I0(mem_out[0]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D9[6]));\n LUT4 #(\n .INIT(16'h082A)) \n p_17_out\n (.I0(mux_cmd_wren),\n .I1(ofifo_rst_reg),\n .I2(\\my_full_reg_n_0_[4] ),\n .I3(\\my_empty_reg[1]_0 ),\n .O(wr_en));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[0] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1_n_0 ),\n .D(nxt_rd_ptr[0]),\n .Q(rd_ptr[0]),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[1] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1_n_0 ),\n .D(nxt_rd_ptr[1]),\n .Q(rd_ptr[1]),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[2] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1_n_0 ),\n .D(nxt_rd_ptr[2]),\n .Q(rd_ptr[2]),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_reg[3] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1_n_0 ),\n .D(nxt_rd_ptr[3]),\n .Q(rd_ptr[3]),\n .R(SR));\n (* SOFT_HLUTNM = \"soft_lutpair999\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\rd_ptr_timing[0]_i_1 \n (.I0(rd_ptr[3]),\n .I1(rd_ptr[0]),\n .O(nxt_rd_ptr[0]));\n (* SOFT_HLUTNM = \"soft_lutpair999\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\rd_ptr_timing[1]_i_1 \n (.I0(rd_ptr[3]),\n .I1(rd_ptr[0]),\n .I2(rd_ptr[1]),\n .O(nxt_rd_ptr[1]));\n (* SOFT_HLUTNM = \"soft_lutpair993\" *) \n LUT4 #(\n .INIT(16'hAA6A)) \n \\rd_ptr_timing[2]_i_1 \n (.I0(rd_ptr[2]),\n .I1(rd_ptr[0]),\n .I2(rd_ptr[1]),\n .I3(rd_ptr[3]),\n .O(nxt_rd_ptr[2]));\n LUT2 #(\n .INIT(4'h1)) \n \\rd_ptr_timing[3]_i_1 \n (.I0(\\my_empty_reg_n_0_[7] ),\n .I1(ofifo_rst_reg),\n .O(\\rd_ptr_timing[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair993\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\rd_ptr_timing[3]_i_2 \n (.I0(rd_ptr[3]),\n .I1(rd_ptr[1]),\n .I2(rd_ptr[0]),\n .I3(rd_ptr[2]),\n .O(nxt_rd_ptr[3]));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[0] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1_n_0 ),\n .D(nxt_rd_ptr[0]),\n .Q(rd_ptr_timing[0]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[1] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1_n_0 ),\n .D(nxt_rd_ptr[1]),\n .Q(rd_ptr_timing[1]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[2] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1_n_0 ),\n .D(nxt_rd_ptr[2]),\n .Q(rd_ptr_timing[2]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_ptr_timing_reg[3] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1_n_0 ),\n .D(nxt_rd_ptr[3]),\n .Q(rd_ptr_timing[3]),\n .R(SR));\n LUT4 #(\n .INIT(16'h082A)) \n wr_ptr0\n (.I0(mux_cmd_wren),\n .I1(ofifo_rst_reg),\n .I2(\\my_full_reg_n_0_[4] ),\n .I3(\\my_empty_reg_n_0_[7] ),\n .O(wr_ptr0__0));\n (* SOFT_HLUTNM = \"soft_lutpair997\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\wr_ptr[0]_i_1 \n (.I0(wr_ptr[3]),\n .I1(wr_ptr[0]),\n .O(nxt_wr_ptr[0]));\n (* SOFT_HLUTNM = \"soft_lutpair997\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\wr_ptr[1]_i_1 \n (.I0(wr_ptr[3]),\n .I1(wr_ptr[0]),\n .I2(wr_ptr[1]),\n .O(nxt_wr_ptr[1]));\n (* SOFT_HLUTNM = \"soft_lutpair992\" *) \n LUT4 #(\n .INIT(16'hAA6A)) \n \\wr_ptr[2]_i_1 \n (.I0(wr_ptr[2]),\n .I1(wr_ptr[0]),\n .I2(wr_ptr[1]),\n .I3(wr_ptr[3]),\n .O(nxt_wr_ptr[2]));\n (* SOFT_HLUTNM = \"soft_lutpair992\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\wr_ptr[3]_i_1 \n (.I0(wr_ptr[3]),\n .I1(wr_ptr[1]),\n .I2(wr_ptr[0]),\n .I3(wr_ptr[2]),\n .O(nxt_wr_ptr[3]));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[0] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[0]),\n .Q(wr_ptr[0]),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[1] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[1]),\n .Q(wr_ptr[1]),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[2] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[2]),\n .Q(wr_ptr[2]),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_reg[3] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[3]),\n .Q(wr_ptr[3]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[0] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[0]),\n .Q(wr_ptr_timing[0]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[1] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[1]),\n .Q(wr_ptr_timing[1]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[2] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[2]),\n .Q(wr_ptr_timing[2]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wr_ptr_timing_reg[3] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[3]),\n .Q(wr_ptr_timing[3]),\n .R(SR));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_phy_4lanes\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_phy_4lanes\n (\\pi_dqs_found_lanes_r1_reg[3] ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,\n mem_dqs_out,\n mem_dqs_ts,\n mem_dq_out,\n mem_dq_ts,\n idelay_ld_rst,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,\n idelay_ld_rst_0,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,\n idelay_ld_rst_1,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,\n idelay_ld_rst_2,\n _phy_ctl_full_p__0,\n rst_primitives_reg_0,\n rst_primitives,\n mcGo_reg_0,\n rclk_delay_11,\n \\not_strict_mode.app_rd_data_reg[252] ,\n \\not_strict_mode.app_rd_data_reg[244] ,\n \\not_strict_mode.app_rd_data_reg[236] ,\n \\not_strict_mode.app_rd_data_reg[228] ,\n \\my_empty_reg[1] ,\n \\my_empty_reg[1]_0 ,\n \\my_empty_reg[1]_1 ,\n \\my_empty_reg[1]_2 ,\n \\mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13 ,\n rd_buf_we,\n \\not_strict_mode.status_ram.rd_buf_we_r1_reg ,\n phy_rddata_en,\n mux_rd_valid_r_reg,\n rst_sync_r1_reg,\n \\data_bytes_r_reg[63] ,\n \\not_strict_mode.app_rd_data_reg[255] ,\n \\not_strict_mode.app_rd_data_reg[239] ,\n \\not_strict_mode.app_rd_data_reg[247] ,\n \\not_strict_mode.app_rd_data_reg[231] ,\n \\not_strict_mode.app_rd_data_reg[254] ,\n \\not_strict_mode.app_rd_data_reg[238] ,\n \\not_strict_mode.app_rd_data_reg[246] ,\n \\not_strict_mode.app_rd_data_reg[230] ,\n \\not_strict_mode.app_rd_data_reg[253] ,\n \\not_strict_mode.app_rd_data_reg[237] ,\n \\not_strict_mode.app_rd_data_reg[245] ,\n \\not_strict_mode.app_rd_data_reg[229] ,\n \\not_strict_mode.app_rd_data_reg[252]_0 ,\n \\not_strict_mode.app_rd_data_reg[236]_0 ,\n \\not_strict_mode.app_rd_data_reg[244]_0 ,\n \\not_strict_mode.app_rd_data_reg[228]_0 ,\n \\not_strict_mode.app_rd_data_reg[251] ,\n \\not_strict_mode.app_rd_data_reg[235] ,\n \\not_strict_mode.app_rd_data_reg[243] ,\n \\not_strict_mode.app_rd_data_reg[227] ,\n \\not_strict_mode.app_rd_data_reg[250] ,\n \\not_strict_mode.app_rd_data_reg[234] ,\n \\not_strict_mode.app_rd_data_reg[242] ,\n \\not_strict_mode.app_rd_data_reg[226] ,\n \\not_strict_mode.app_rd_data_reg[249] ,\n \\not_strict_mode.app_rd_data_reg[233] ,\n \\not_strict_mode.app_rd_data_reg[241] ,\n \\not_strict_mode.app_rd_data_reg[225] ,\n \\not_strict_mode.app_rd_data_reg[248] ,\n \\not_strict_mode.app_rd_data_reg[232] ,\n \\not_strict_mode.app_rd_data_reg[240] ,\n \\not_strict_mode.app_rd_data_reg[224] ,\n \\not_strict_mode.app_rd_data_reg[223] ,\n \\not_strict_mode.app_rd_data_reg[207] ,\n \\not_strict_mode.app_rd_data_reg[215] ,\n \\not_strict_mode.app_rd_data_reg[199] ,\n \\not_strict_mode.app_rd_data_reg[222] ,\n \\not_strict_mode.app_rd_data_reg[206] ,\n \\not_strict_mode.app_rd_data_reg[214] ,\n \\not_strict_mode.app_rd_data_reg[198] ,\n \\not_strict_mode.app_rd_data_reg[221] ,\n \\not_strict_mode.app_rd_data_reg[205] ,\n \\not_strict_mode.app_rd_data_reg[213] ,\n \\not_strict_mode.app_rd_data_reg[197] ,\n \\not_strict_mode.app_rd_data_reg[220] ,\n \\not_strict_mode.app_rd_data_reg[204] ,\n \\not_strict_mode.app_rd_data_reg[212] ,\n \\not_strict_mode.app_rd_data_reg[196] ,\n \\not_strict_mode.app_rd_data_reg[219] ,\n \\not_strict_mode.app_rd_data_reg[203] ,\n \\not_strict_mode.app_rd_data_reg[211] ,\n \\not_strict_mode.app_rd_data_reg[195] ,\n \\not_strict_mode.app_rd_data_reg[218] ,\n \\not_strict_mode.app_rd_data_reg[202] ,\n \\not_strict_mode.app_rd_data_reg[210] ,\n \\not_strict_mode.app_rd_data_reg[194] ,\n \\not_strict_mode.app_rd_data_reg[217] ,\n \\not_strict_mode.app_rd_data_reg[201] ,\n \\not_strict_mode.app_rd_data_reg[209] ,\n \\not_strict_mode.app_rd_data_reg[193] ,\n \\not_strict_mode.app_rd_data_reg[216] ,\n \\not_strict_mode.app_rd_data_reg[200] ,\n \\not_strict_mode.app_rd_data_reg[208] ,\n \\not_strict_mode.app_rd_data_reg[192] ,\n \\not_strict_mode.app_rd_data_reg[191] ,\n \\not_strict_mode.app_rd_data_reg[175] ,\n \\not_strict_mode.app_rd_data_reg[183] ,\n \\not_strict_mode.app_rd_data_reg[167] ,\n \\not_strict_mode.app_rd_data_reg[190] ,\n \\not_strict_mode.app_rd_data_reg[174] ,\n \\not_strict_mode.app_rd_data_reg[182] ,\n \\not_strict_mode.app_rd_data_reg[166] ,\n \\not_strict_mode.app_rd_data_reg[189] ,\n \\not_strict_mode.app_rd_data_reg[173] ,\n \\not_strict_mode.app_rd_data_reg[181] ,\n \\not_strict_mode.app_rd_data_reg[165] ,\n \\not_strict_mode.app_rd_data_reg[188] ,\n \\not_strict_mode.app_rd_data_reg[172] ,\n \\not_strict_mode.app_rd_data_reg[180] ,\n \\not_strict_mode.app_rd_data_reg[164] ,\n \\not_strict_mode.app_rd_data_reg[187] ,\n \\not_strict_mode.app_rd_data_reg[171] ,\n \\not_strict_mode.app_rd_data_reg[179] ,\n \\not_strict_mode.app_rd_data_reg[163] ,\n \\not_strict_mode.app_rd_data_reg[186] ,\n \\not_strict_mode.app_rd_data_reg[170] ,\n \\not_strict_mode.app_rd_data_reg[178] ,\n \\not_strict_mode.app_rd_data_reg[162] ,\n \\not_strict_mode.app_rd_data_reg[185] ,\n \\not_strict_mode.app_rd_data_reg[169] ,\n \\not_strict_mode.app_rd_data_reg[177] ,\n \\not_strict_mode.app_rd_data_reg[161] ,\n \\not_strict_mode.app_rd_data_reg[184] ,\n \\not_strict_mode.app_rd_data_reg[168] ,\n \\not_strict_mode.app_rd_data_reg[176] ,\n \\not_strict_mode.app_rd_data_reg[160] ,\n \\not_strict_mode.app_rd_data_reg[159] ,\n \\not_strict_mode.app_rd_data_reg[143] ,\n \\not_strict_mode.app_rd_data_reg[151] ,\n \\not_strict_mode.app_rd_data_reg[135] ,\n \\not_strict_mode.app_rd_data_reg[158] ,\n \\not_strict_mode.app_rd_data_reg[142] ,\n \\not_strict_mode.app_rd_data_reg[150] ,\n \\not_strict_mode.app_rd_data_reg[134] ,\n \\not_strict_mode.app_rd_data_reg[157] ,\n \\not_strict_mode.app_rd_data_reg[141] ,\n \\not_strict_mode.app_rd_data_reg[149] ,\n \\not_strict_mode.app_rd_data_reg[133] ,\n \\not_strict_mode.app_rd_data_reg[156] ,\n \\not_strict_mode.app_rd_data_reg[140] ,\n \\not_strict_mode.app_rd_data_reg[148] ,\n \\not_strict_mode.app_rd_data_reg[132] ,\n \\not_strict_mode.app_rd_data_reg[155] ,\n \\not_strict_mode.app_rd_data_reg[139] ,\n \\not_strict_mode.app_rd_data_reg[147] ,\n \\not_strict_mode.app_rd_data_reg[131] ,\n \\not_strict_mode.app_rd_data_reg[154] ,\n \\not_strict_mode.app_rd_data_reg[138] ,\n \\not_strict_mode.app_rd_data_reg[146] ,\n \\not_strict_mode.app_rd_data_reg[130] ,\n \\not_strict_mode.app_rd_data_reg[153] ,\n \\not_strict_mode.app_rd_data_reg[137] ,\n \\not_strict_mode.app_rd_data_reg[145] ,\n \\not_strict_mode.app_rd_data_reg[129] ,\n \\not_strict_mode.app_rd_data_reg[152] ,\n \\not_strict_mode.app_rd_data_reg[136] ,\n \\not_strict_mode.app_rd_data_reg[144] ,\n \\not_strict_mode.app_rd_data_reg[128] ,\n \\not_strict_mode.app_rd_data_reg[127] ,\n \\not_strict_mode.app_rd_data_reg[111] ,\n \\not_strict_mode.app_rd_data_reg[119] ,\n \\not_strict_mode.app_rd_data_reg[103] ,\n \\not_strict_mode.app_rd_data_reg[126] ,\n \\not_strict_mode.app_rd_data_reg[110] ,\n \\not_strict_mode.app_rd_data_reg[118] ,\n \\not_strict_mode.app_rd_data_reg[102] ,\n \\not_strict_mode.app_rd_data_reg[125] ,\n \\not_strict_mode.app_rd_data_reg[109] ,\n \\not_strict_mode.app_rd_data_reg[117] ,\n \\not_strict_mode.app_rd_data_reg[101] ,\n \\not_strict_mode.app_rd_data_reg[124] ,\n \\not_strict_mode.app_rd_data_reg[108] ,\n \\not_strict_mode.app_rd_data_reg[116] ,\n \\not_strict_mode.app_rd_data_reg[100] ,\n \\not_strict_mode.app_rd_data_reg[123] ,\n \\not_strict_mode.app_rd_data_reg[107] ,\n \\not_strict_mode.app_rd_data_reg[115] ,\n \\not_strict_mode.app_rd_data_reg[99] ,\n \\not_strict_mode.app_rd_data_reg[122] ,\n \\not_strict_mode.app_rd_data_reg[106] ,\n \\not_strict_mode.app_rd_data_reg[114] ,\n \\not_strict_mode.app_rd_data_reg[98] ,\n \\not_strict_mode.app_rd_data_reg[121] ,\n \\not_strict_mode.app_rd_data_reg[105] ,\n \\not_strict_mode.app_rd_data_reg[113] ,\n \\not_strict_mode.app_rd_data_reg[97] ,\n \\not_strict_mode.app_rd_data_reg[120] ,\n \\not_strict_mode.app_rd_data_reg[104] ,\n \\not_strict_mode.app_rd_data_reg[112] ,\n \\not_strict_mode.app_rd_data_reg[96] ,\n \\not_strict_mode.app_rd_data_reg[95] ,\n \\not_strict_mode.app_rd_data_reg[79] ,\n \\not_strict_mode.app_rd_data_reg[87] ,\n \\not_strict_mode.app_rd_data_reg[71] ,\n \\not_strict_mode.app_rd_data_reg[94] ,\n \\not_strict_mode.app_rd_data_reg[78] ,\n \\not_strict_mode.app_rd_data_reg[86] ,\n \\not_strict_mode.app_rd_data_reg[70] ,\n \\not_strict_mode.app_rd_data_reg[93] ,\n \\not_strict_mode.app_rd_data_reg[77] ,\n \\not_strict_mode.app_rd_data_reg[85] ,\n \\not_strict_mode.app_rd_data_reg[69] ,\n \\not_strict_mode.app_rd_data_reg[92] ,\n \\not_strict_mode.app_rd_data_reg[76] ,\n \\not_strict_mode.app_rd_data_reg[84] ,\n \\not_strict_mode.app_rd_data_reg[68] ,\n \\not_strict_mode.app_rd_data_reg[91] ,\n \\not_strict_mode.app_rd_data_reg[75] ,\n \\not_strict_mode.app_rd_data_reg[83] ,\n \\not_strict_mode.app_rd_data_reg[67] ,\n \\not_strict_mode.app_rd_data_reg[90] ,\n \\not_strict_mode.app_rd_data_reg[74] ,\n \\not_strict_mode.app_rd_data_reg[82] ,\n \\not_strict_mode.app_rd_data_reg[66] ,\n \\not_strict_mode.app_rd_data_reg[89] ,\n \\not_strict_mode.app_rd_data_reg[73] ,\n \\not_strict_mode.app_rd_data_reg[81] ,\n \\not_strict_mode.app_rd_data_reg[65] ,\n \\not_strict_mode.app_rd_data_reg[88] ,\n \\not_strict_mode.app_rd_data_reg[72] ,\n \\not_strict_mode.app_rd_data_reg[80] ,\n \\not_strict_mode.app_rd_data_reg[64] ,\n \\not_strict_mode.app_rd_data_reg[63] ,\n \\not_strict_mode.app_rd_data_reg[47] ,\n \\not_strict_mode.app_rd_data_reg[55] ,\n \\not_strict_mode.app_rd_data_reg[39] ,\n \\not_strict_mode.app_rd_data_reg[62] ,\n \\not_strict_mode.app_rd_data_reg[46] ,\n \\not_strict_mode.app_rd_data_reg[54] ,\n \\not_strict_mode.app_rd_data_reg[38] ,\n \\not_strict_mode.app_rd_data_reg[61] ,\n \\not_strict_mode.app_rd_data_reg[45] ,\n \\not_strict_mode.app_rd_data_reg[53] ,\n \\not_strict_mode.app_rd_data_reg[37] ,\n \\not_strict_mode.app_rd_data_reg[60] ,\n \\not_strict_mode.app_rd_data_reg[44] ,\n \\not_strict_mode.app_rd_data_reg[52] ,\n \\not_strict_mode.app_rd_data_reg[36] ,\n \\not_strict_mode.app_rd_data_reg[59] ,\n \\not_strict_mode.app_rd_data_reg[43] ,\n \\not_strict_mode.app_rd_data_reg[51] ,\n \\not_strict_mode.app_rd_data_reg[35] ,\n \\not_strict_mode.app_rd_data_reg[58] ,\n \\not_strict_mode.app_rd_data_reg[42] ,\n \\not_strict_mode.app_rd_data_reg[50] ,\n \\not_strict_mode.app_rd_data_reg[34] ,\n \\not_strict_mode.app_rd_data_reg[57] ,\n \\not_strict_mode.app_rd_data_reg[41] ,\n \\not_strict_mode.app_rd_data_reg[49] ,\n \\not_strict_mode.app_rd_data_reg[33] ,\n \\not_strict_mode.app_rd_data_reg[56] ,\n \\not_strict_mode.app_rd_data_reg[40] ,\n \\not_strict_mode.app_rd_data_reg[48] ,\n \\not_strict_mode.app_rd_data_reg[32] ,\n \\not_strict_mode.app_rd_data_reg[31] ,\n \\not_strict_mode.app_rd_data_reg[15] ,\n \\not_strict_mode.app_rd_data_reg[23] ,\n \\not_strict_mode.app_rd_data_reg[7] ,\n \\not_strict_mode.app_rd_data_reg[30] ,\n \\not_strict_mode.app_rd_data_reg[14] ,\n \\not_strict_mode.app_rd_data_reg[22] ,\n \\not_strict_mode.app_rd_data_reg[6] ,\n \\not_strict_mode.app_rd_data_reg[29] ,\n \\not_strict_mode.app_rd_data_reg[13] ,\n \\not_strict_mode.app_rd_data_reg[21] ,\n \\not_strict_mode.app_rd_data_reg[5] ,\n \\not_strict_mode.app_rd_data_reg[28] ,\n \\not_strict_mode.app_rd_data_reg[12] ,\n \\not_strict_mode.app_rd_data_reg[20] ,\n \\not_strict_mode.app_rd_data_reg[4] ,\n \\not_strict_mode.app_rd_data_reg[27] ,\n \\not_strict_mode.app_rd_data_reg[11] ,\n \\not_strict_mode.app_rd_data_reg[19] ,\n \\not_strict_mode.app_rd_data_reg[3] ,\n \\not_strict_mode.app_rd_data_reg[26] ,\n \\not_strict_mode.app_rd_data_reg[10] ,\n \\not_strict_mode.app_rd_data_reg[18] ,\n \\not_strict_mode.app_rd_data_reg[2] ,\n \\not_strict_mode.app_rd_data_reg[25] ,\n \\not_strict_mode.app_rd_data_reg[9] ,\n \\not_strict_mode.app_rd_data_reg[17] ,\n \\not_strict_mode.app_rd_data_reg[1] ,\n \\not_strict_mode.app_rd_data_reg[24] ,\n \\not_strict_mode.app_rd_data_reg[8] ,\n \\not_strict_mode.app_rd_data_reg[16] ,\n \\not_strict_mode.app_rd_data_reg[0] ,\n \\read_fifo.tail_r_reg[0] ,\n \\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,\n \\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,\n \\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,\n \\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,\n \\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,\n \\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,\n \\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,\n \\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,\n \\not_strict_mode.app_rd_data_reg[255]_0 ,\n pi_phase_locked_all_r1_reg,\n \\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ,\n \\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ,\n \\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ,\n \\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ,\n \\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ,\n \\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ,\n \\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ,\n \\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ,\n \\not_strict_mode.app_rd_data_reg[31]_0 ,\n \\not_strict_mode.app_rd_data_reg[31]_1 ,\n \\my_empty_reg[7] ,\n \\not_strict_mode.app_rd_data_reg[23]_0 ,\n \\not_strict_mode.app_rd_data_reg[23]_1 ,\n \\my_empty_reg[7]_0 ,\n \\not_strict_mode.app_rd_data_reg[15]_0 ,\n \\not_strict_mode.app_rd_data_reg[15]_1 ,\n \\my_empty_reg[7]_1 ,\n \\not_strict_mode.app_rd_data_reg[7]_0 ,\n \\not_strict_mode.app_rd_data_reg[7]_1 ,\n \\my_empty_reg[7]_2 ,\n ofs_rdy_r_reg,\n ofs_rdy_r_reg_0,\n \\po_rdval_cnt_reg[8] ,\n \\pi_rdval_cnt_reg[5] ,\n phy_if_empty_r_reg,\n p_0_out,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,\n \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,\n \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,\n \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,\n \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n \\calib_sel_reg[0] ,\n pi_en_stg2_f_reg,\n pi_stg2_f_incdec_reg,\n freq_refclk,\n mem_refclk,\n mem_dqs_in,\n \\gen_byte_sel_div1.calib_in_common_reg_0 ,\n sync_pulse,\n CLK,\n COUNTERLOADVAL,\n \\gen_byte_sel_div1.calib_in_common_reg_1 ,\n ck_po_stg2_f_en_reg,\n ck_po_stg2_f_indec_reg,\n delay_done_r4_reg,\n \\write_buffer.wr_buf_out_data_reg[255] ,\n \\write_buffer.wr_buf_out_data_reg[254] ,\n \\write_buffer.wr_buf_out_data_reg[253] ,\n \\write_buffer.wr_buf_out_data_reg[252] ,\n \\write_buffer.wr_buf_out_data_reg[251] ,\n \\write_buffer.wr_buf_out_data_reg[250] ,\n \\write_buffer.wr_buf_out_data_reg[249] ,\n \\write_buffer.wr_buf_out_data_reg[248] ,\n \\gen_byte_sel_div1.calib_in_common_reg_2 ,\n mem_dq_in,\n idelay_inc,\n LD0,\n CLKB0,\n phy_if_reset,\n \\gen_byte_sel_div1.calib_in_common_reg_3 ,\n \\calib_sel_reg[0]_0 ,\n pi_en_stg2_f_reg_0,\n pi_stg2_f_incdec_reg_0,\n \\gen_byte_sel_div1.calib_in_common_reg_4 ,\n \\calib_zero_inputs_reg[0] ,\n \\gen_byte_sel_div1.calib_in_common_reg_5 ,\n ck_po_stg2_f_en_reg_0,\n ck_po_stg2_f_indec_reg_0,\n delay_done_r4_reg_0,\n \\write_buffer.wr_buf_out_data_reg[247] ,\n \\write_buffer.wr_buf_out_data_reg[246] ,\n \\write_buffer.wr_buf_out_data_reg[245] ,\n \\write_buffer.wr_buf_out_data_reg[244] ,\n \\write_buffer.wr_buf_out_data_reg[243] ,\n \\write_buffer.wr_buf_out_data_reg[242] ,\n \\write_buffer.wr_buf_out_data_reg[241] ,\n \\write_buffer.wr_buf_out_data_reg[240] ,\n \\gen_byte_sel_div1.calib_in_common_reg_6 ,\n LD0_3,\n CLKB0_7,\n \\gen_byte_sel_div1.calib_in_common_reg_7 ,\n \\calib_sel_reg[1] ,\n pi_en_stg2_f_reg_1,\n pi_stg2_f_incdec_reg_1,\n \\gen_byte_sel_div1.calib_in_common_reg_8 ,\n \\calib_zero_inputs_reg[0]_0 ,\n \\gen_byte_sel_div1.calib_in_common_reg_9 ,\n ck_po_stg2_f_en_reg_1,\n ck_po_stg2_f_indec_reg_1,\n delay_done_r4_reg_1,\n \\write_buffer.wr_buf_out_data_reg[239] ,\n \\write_buffer.wr_buf_out_data_reg[238] ,\n \\write_buffer.wr_buf_out_data_reg[237] ,\n \\write_buffer.wr_buf_out_data_reg[236] ,\n \\write_buffer.wr_buf_out_data_reg[235] ,\n \\write_buffer.wr_buf_out_data_reg[234] ,\n \\write_buffer.wr_buf_out_data_reg[233] ,\n \\write_buffer.wr_buf_out_data_reg[232] ,\n \\gen_byte_sel_div1.calib_in_common_reg_10 ,\n LD0_4,\n CLKB0_8,\n \\gen_byte_sel_div1.calib_in_common_reg_11 ,\n \\calib_sel_reg[0]_1 ,\n pi_en_stg2_f_reg_2,\n pi_stg2_f_incdec_reg_2,\n \\gen_byte_sel_div1.calib_in_common_reg_12 ,\n \\calib_zero_inputs_reg[0]_1 ,\n \\gen_byte_sel_div1.calib_in_common_reg_13 ,\n ck_po_stg2_f_en_reg_2,\n ck_po_stg2_f_indec_reg_2,\n delay_done_r4_reg_2,\n \\write_buffer.wr_buf_out_data_reg[231] ,\n \\write_buffer.wr_buf_out_data_reg[230] ,\n \\write_buffer.wr_buf_out_data_reg[229] ,\n \\write_buffer.wr_buf_out_data_reg[228] ,\n \\write_buffer.wr_buf_out_data_reg[227] ,\n \\write_buffer.wr_buf_out_data_reg[226] ,\n \\write_buffer.wr_buf_out_data_reg[225] ,\n \\write_buffer.wr_buf_out_data_reg[224] ,\n \\gen_byte_sel_div1.calib_in_common_reg_14 ,\n LD0_5,\n CLKB0_9,\n phy_ctl_mstr_empty,\n phy_ctl_wr_i2,\n pll_locked,\n phy_read_calib,\n in0,\n phy_write_calib,\n Q,\n RST0,\n phy_ctl_wr_i2_reg,\n \\rclk_delay_reg[11]_0 ,\n rstdiv0_sync_r1_reg_rep__9,\n rst_primitives_reg_1,\n mux_wrdata_en,\n mcGo_w__0,\n \\read_fifo.fifo_out_data_r_reg[6] ,\n ram_init_done_r,\n init_calib_complete_reg_rep,\n \\write_buffer.wr_buf_out_data_reg[287] ,\n prbs_rdlvl_start_reg,\n out,\n ref_dll_lock_w,\n sys_rst,\n \\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ,\n mmcm_locked,\n \\byte_r_reg[0] ,\n \\byte_r_reg[1] ,\n tail_r,\n \\rd_mux_sel_r_reg[1] ,\n \\read_fifo.fifo_out_data_r_reg[6]_0 ,\n DOC,\n DOB,\n DOA,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ,\n A,\n mux_wrdata,\n mux_wrdata_mask,\n E,\n \\fine_delay_mod_reg[23] ,\n \\gen_byte_sel_div1.calib_in_common_reg_15 ,\n \\calib_sel_reg[0]_2 ,\n \\gen_byte_sel_div1.calib_in_common_reg_16 ,\n \\calib_sel_reg[1]_0 ,\n \\gen_byte_sel_div1.calib_in_common_reg_17 ,\n \\calib_sel_reg[0]_3 ,\n \\calib_sel_reg[1]_1 ,\n \\po_stg2_wrcal_cnt_reg[1] );\n output [3:0]\\pi_dqs_found_lanes_r1_reg[3] ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n output [3:0]mem_dqs_out;\n output [3:0]mem_dqs_ts;\n output [35:0]mem_dq_out;\n output [35:0]mem_dq_ts;\n output idelay_ld_rst;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n output idelay_ld_rst_0;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;\n output idelay_ld_rst_1;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;\n output idelay_ld_rst_2;\n output [0:0]_phy_ctl_full_p__0;\n output rst_primitives_reg_0;\n output rst_primitives;\n output mcGo_reg_0;\n output rclk_delay_11;\n output \\not_strict_mode.app_rd_data_reg[252] ;\n output \\not_strict_mode.app_rd_data_reg[244] ;\n output \\not_strict_mode.app_rd_data_reg[236] ;\n output \\not_strict_mode.app_rd_data_reg[228] ;\n output \\my_empty_reg[1] ;\n output \\my_empty_reg[1]_0 ;\n output \\my_empty_reg[1]_1 ;\n output \\my_empty_reg[1]_2 ;\n output \\mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13 ;\n output rd_buf_we;\n output \\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n output phy_rddata_en;\n output mux_rd_valid_r_reg;\n output rst_sync_r1_reg;\n output [63:0]\\data_bytes_r_reg[63] ;\n output \\not_strict_mode.app_rd_data_reg[255] ;\n output \\not_strict_mode.app_rd_data_reg[239] ;\n output \\not_strict_mode.app_rd_data_reg[247] ;\n output \\not_strict_mode.app_rd_data_reg[231] ;\n output \\not_strict_mode.app_rd_data_reg[254] ;\n output \\not_strict_mode.app_rd_data_reg[238] ;\n output \\not_strict_mode.app_rd_data_reg[246] ;\n output \\not_strict_mode.app_rd_data_reg[230] ;\n output \\not_strict_mode.app_rd_data_reg[253] ;\n output \\not_strict_mode.app_rd_data_reg[237] ;\n output \\not_strict_mode.app_rd_data_reg[245] ;\n output \\not_strict_mode.app_rd_data_reg[229] ;\n output \\not_strict_mode.app_rd_data_reg[252]_0 ;\n output \\not_strict_mode.app_rd_data_reg[236]_0 ;\n output \\not_strict_mode.app_rd_data_reg[244]_0 ;\n output \\not_strict_mode.app_rd_data_reg[228]_0 ;\n output \\not_strict_mode.app_rd_data_reg[251] ;\n output \\not_strict_mode.app_rd_data_reg[235] ;\n output \\not_strict_mode.app_rd_data_reg[243] ;\n output \\not_strict_mode.app_rd_data_reg[227] ;\n output \\not_strict_mode.app_rd_data_reg[250] ;\n output \\not_strict_mode.app_rd_data_reg[234] ;\n output \\not_strict_mode.app_rd_data_reg[242] ;\n output \\not_strict_mode.app_rd_data_reg[226] ;\n output \\not_strict_mode.app_rd_data_reg[249] ;\n output \\not_strict_mode.app_rd_data_reg[233] ;\n output \\not_strict_mode.app_rd_data_reg[241] ;\n output \\not_strict_mode.app_rd_data_reg[225] ;\n output \\not_strict_mode.app_rd_data_reg[248] ;\n output \\not_strict_mode.app_rd_data_reg[232] ;\n output \\not_strict_mode.app_rd_data_reg[240] ;\n output \\not_strict_mode.app_rd_data_reg[224] ;\n output \\not_strict_mode.app_rd_data_reg[223] ;\n output \\not_strict_mode.app_rd_data_reg[207] ;\n output \\not_strict_mode.app_rd_data_reg[215] ;\n output \\not_strict_mode.app_rd_data_reg[199] ;\n output \\not_strict_mode.app_rd_data_reg[222] ;\n output \\not_strict_mode.app_rd_data_reg[206] ;\n output \\not_strict_mode.app_rd_data_reg[214] ;\n output \\not_strict_mode.app_rd_data_reg[198] ;\n output \\not_strict_mode.app_rd_data_reg[221] ;\n output \\not_strict_mode.app_rd_data_reg[205] ;\n output \\not_strict_mode.app_rd_data_reg[213] ;\n output \\not_strict_mode.app_rd_data_reg[197] ;\n output \\not_strict_mode.app_rd_data_reg[220] ;\n output \\not_strict_mode.app_rd_data_reg[204] ;\n output \\not_strict_mode.app_rd_data_reg[212] ;\n output \\not_strict_mode.app_rd_data_reg[196] ;\n output \\not_strict_mode.app_rd_data_reg[219] ;\n output \\not_strict_mode.app_rd_data_reg[203] ;\n output \\not_strict_mode.app_rd_data_reg[211] ;\n output \\not_strict_mode.app_rd_data_reg[195] ;\n output \\not_strict_mode.app_rd_data_reg[218] ;\n output \\not_strict_mode.app_rd_data_reg[202] ;\n output \\not_strict_mode.app_rd_data_reg[210] ;\n output \\not_strict_mode.app_rd_data_reg[194] ;\n output \\not_strict_mode.app_rd_data_reg[217] ;\n output \\not_strict_mode.app_rd_data_reg[201] ;\n output \\not_strict_mode.app_rd_data_reg[209] ;\n output \\not_strict_mode.app_rd_data_reg[193] ;\n output \\not_strict_mode.app_rd_data_reg[216] ;\n output \\not_strict_mode.app_rd_data_reg[200] ;\n output \\not_strict_mode.app_rd_data_reg[208] ;\n output \\not_strict_mode.app_rd_data_reg[192] ;\n output \\not_strict_mode.app_rd_data_reg[191] ;\n output \\not_strict_mode.app_rd_data_reg[175] ;\n output \\not_strict_mode.app_rd_data_reg[183] ;\n output \\not_strict_mode.app_rd_data_reg[167] ;\n output \\not_strict_mode.app_rd_data_reg[190] ;\n output \\not_strict_mode.app_rd_data_reg[174] ;\n output \\not_strict_mode.app_rd_data_reg[182] ;\n output \\not_strict_mode.app_rd_data_reg[166] ;\n output \\not_strict_mode.app_rd_data_reg[189] ;\n output \\not_strict_mode.app_rd_data_reg[173] ;\n output \\not_strict_mode.app_rd_data_reg[181] ;\n output \\not_strict_mode.app_rd_data_reg[165] ;\n output \\not_strict_mode.app_rd_data_reg[188] ;\n output \\not_strict_mode.app_rd_data_reg[172] ;\n output \\not_strict_mode.app_rd_data_reg[180] ;\n output \\not_strict_mode.app_rd_data_reg[164] ;\n output \\not_strict_mode.app_rd_data_reg[187] ;\n output \\not_strict_mode.app_rd_data_reg[171] ;\n output \\not_strict_mode.app_rd_data_reg[179] ;\n output \\not_strict_mode.app_rd_data_reg[163] ;\n output \\not_strict_mode.app_rd_data_reg[186] ;\n output \\not_strict_mode.app_rd_data_reg[170] ;\n output \\not_strict_mode.app_rd_data_reg[178] ;\n output \\not_strict_mode.app_rd_data_reg[162] ;\n output \\not_strict_mode.app_rd_data_reg[185] ;\n output \\not_strict_mode.app_rd_data_reg[169] ;\n output \\not_strict_mode.app_rd_data_reg[177] ;\n output \\not_strict_mode.app_rd_data_reg[161] ;\n output \\not_strict_mode.app_rd_data_reg[184] ;\n output \\not_strict_mode.app_rd_data_reg[168] ;\n output \\not_strict_mode.app_rd_data_reg[176] ;\n output \\not_strict_mode.app_rd_data_reg[160] ;\n output \\not_strict_mode.app_rd_data_reg[159] ;\n output \\not_strict_mode.app_rd_data_reg[143] ;\n output \\not_strict_mode.app_rd_data_reg[151] ;\n output \\not_strict_mode.app_rd_data_reg[135] ;\n output \\not_strict_mode.app_rd_data_reg[158] ;\n output \\not_strict_mode.app_rd_data_reg[142] ;\n output \\not_strict_mode.app_rd_data_reg[150] ;\n output \\not_strict_mode.app_rd_data_reg[134] ;\n output \\not_strict_mode.app_rd_data_reg[157] ;\n output \\not_strict_mode.app_rd_data_reg[141] ;\n output \\not_strict_mode.app_rd_data_reg[149] ;\n output \\not_strict_mode.app_rd_data_reg[133] ;\n output \\not_strict_mode.app_rd_data_reg[156] ;\n output \\not_strict_mode.app_rd_data_reg[140] ;\n output \\not_strict_mode.app_rd_data_reg[148] ;\n output \\not_strict_mode.app_rd_data_reg[132] ;\n output \\not_strict_mode.app_rd_data_reg[155] ;\n output \\not_strict_mode.app_rd_data_reg[139] ;\n output \\not_strict_mode.app_rd_data_reg[147] ;\n output \\not_strict_mode.app_rd_data_reg[131] ;\n output \\not_strict_mode.app_rd_data_reg[154] ;\n output \\not_strict_mode.app_rd_data_reg[138] ;\n output \\not_strict_mode.app_rd_data_reg[146] ;\n output \\not_strict_mode.app_rd_data_reg[130] ;\n output \\not_strict_mode.app_rd_data_reg[153] ;\n output \\not_strict_mode.app_rd_data_reg[137] ;\n output \\not_strict_mode.app_rd_data_reg[145] ;\n output \\not_strict_mode.app_rd_data_reg[129] ;\n output \\not_strict_mode.app_rd_data_reg[152] ;\n output \\not_strict_mode.app_rd_data_reg[136] ;\n output \\not_strict_mode.app_rd_data_reg[144] ;\n output \\not_strict_mode.app_rd_data_reg[128] ;\n output \\not_strict_mode.app_rd_data_reg[127] ;\n output \\not_strict_mode.app_rd_data_reg[111] ;\n output \\not_strict_mode.app_rd_data_reg[119] ;\n output \\not_strict_mode.app_rd_data_reg[103] ;\n output \\not_strict_mode.app_rd_data_reg[126] ;\n output \\not_strict_mode.app_rd_data_reg[110] ;\n output \\not_strict_mode.app_rd_data_reg[118] ;\n output \\not_strict_mode.app_rd_data_reg[102] ;\n output \\not_strict_mode.app_rd_data_reg[125] ;\n output \\not_strict_mode.app_rd_data_reg[109] ;\n output \\not_strict_mode.app_rd_data_reg[117] ;\n output \\not_strict_mode.app_rd_data_reg[101] ;\n output \\not_strict_mode.app_rd_data_reg[124] ;\n output \\not_strict_mode.app_rd_data_reg[108] ;\n output \\not_strict_mode.app_rd_data_reg[116] ;\n output \\not_strict_mode.app_rd_data_reg[100] ;\n output \\not_strict_mode.app_rd_data_reg[123] ;\n output \\not_strict_mode.app_rd_data_reg[107] ;\n output \\not_strict_mode.app_rd_data_reg[115] ;\n output \\not_strict_mode.app_rd_data_reg[99] ;\n output \\not_strict_mode.app_rd_data_reg[122] ;\n output \\not_strict_mode.app_rd_data_reg[106] ;\n output \\not_strict_mode.app_rd_data_reg[114] ;\n output \\not_strict_mode.app_rd_data_reg[98] ;\n output \\not_strict_mode.app_rd_data_reg[121] ;\n output \\not_strict_mode.app_rd_data_reg[105] ;\n output \\not_strict_mode.app_rd_data_reg[113] ;\n output \\not_strict_mode.app_rd_data_reg[97] ;\n output \\not_strict_mode.app_rd_data_reg[120] ;\n output \\not_strict_mode.app_rd_data_reg[104] ;\n output \\not_strict_mode.app_rd_data_reg[112] ;\n output \\not_strict_mode.app_rd_data_reg[96] ;\n output \\not_strict_mode.app_rd_data_reg[95] ;\n output \\not_strict_mode.app_rd_data_reg[79] ;\n output \\not_strict_mode.app_rd_data_reg[87] ;\n output \\not_strict_mode.app_rd_data_reg[71] ;\n output \\not_strict_mode.app_rd_data_reg[94] ;\n output \\not_strict_mode.app_rd_data_reg[78] ;\n output \\not_strict_mode.app_rd_data_reg[86] ;\n output \\not_strict_mode.app_rd_data_reg[70] ;\n output \\not_strict_mode.app_rd_data_reg[93] ;\n output \\not_strict_mode.app_rd_data_reg[77] ;\n output \\not_strict_mode.app_rd_data_reg[85] ;\n output \\not_strict_mode.app_rd_data_reg[69] ;\n output \\not_strict_mode.app_rd_data_reg[92] ;\n output \\not_strict_mode.app_rd_data_reg[76] ;\n output \\not_strict_mode.app_rd_data_reg[84] ;\n output \\not_strict_mode.app_rd_data_reg[68] ;\n output \\not_strict_mode.app_rd_data_reg[91] ;\n output \\not_strict_mode.app_rd_data_reg[75] ;\n output \\not_strict_mode.app_rd_data_reg[83] ;\n output \\not_strict_mode.app_rd_data_reg[67] ;\n output \\not_strict_mode.app_rd_data_reg[90] ;\n output \\not_strict_mode.app_rd_data_reg[74] ;\n output \\not_strict_mode.app_rd_data_reg[82] ;\n output \\not_strict_mode.app_rd_data_reg[66] ;\n output \\not_strict_mode.app_rd_data_reg[89] ;\n output \\not_strict_mode.app_rd_data_reg[73] ;\n output \\not_strict_mode.app_rd_data_reg[81] ;\n output \\not_strict_mode.app_rd_data_reg[65] ;\n output \\not_strict_mode.app_rd_data_reg[88] ;\n output \\not_strict_mode.app_rd_data_reg[72] ;\n output \\not_strict_mode.app_rd_data_reg[80] ;\n output \\not_strict_mode.app_rd_data_reg[64] ;\n output \\not_strict_mode.app_rd_data_reg[63] ;\n output \\not_strict_mode.app_rd_data_reg[47] ;\n output \\not_strict_mode.app_rd_data_reg[55] ;\n output \\not_strict_mode.app_rd_data_reg[39] ;\n output \\not_strict_mode.app_rd_data_reg[62] ;\n output \\not_strict_mode.app_rd_data_reg[46] ;\n output \\not_strict_mode.app_rd_data_reg[54] ;\n output \\not_strict_mode.app_rd_data_reg[38] ;\n output \\not_strict_mode.app_rd_data_reg[61] ;\n output \\not_strict_mode.app_rd_data_reg[45] ;\n output \\not_strict_mode.app_rd_data_reg[53] ;\n output \\not_strict_mode.app_rd_data_reg[37] ;\n output \\not_strict_mode.app_rd_data_reg[60] ;\n output \\not_strict_mode.app_rd_data_reg[44] ;\n output \\not_strict_mode.app_rd_data_reg[52] ;\n output \\not_strict_mode.app_rd_data_reg[36] ;\n output \\not_strict_mode.app_rd_data_reg[59] ;\n output \\not_strict_mode.app_rd_data_reg[43] ;\n output \\not_strict_mode.app_rd_data_reg[51] ;\n output \\not_strict_mode.app_rd_data_reg[35] ;\n output \\not_strict_mode.app_rd_data_reg[58] ;\n output \\not_strict_mode.app_rd_data_reg[42] ;\n output \\not_strict_mode.app_rd_data_reg[50] ;\n output \\not_strict_mode.app_rd_data_reg[34] ;\n output \\not_strict_mode.app_rd_data_reg[57] ;\n output \\not_strict_mode.app_rd_data_reg[41] ;\n output \\not_strict_mode.app_rd_data_reg[49] ;\n output \\not_strict_mode.app_rd_data_reg[33] ;\n output \\not_strict_mode.app_rd_data_reg[56] ;\n output \\not_strict_mode.app_rd_data_reg[40] ;\n output \\not_strict_mode.app_rd_data_reg[48] ;\n output \\not_strict_mode.app_rd_data_reg[32] ;\n output \\not_strict_mode.app_rd_data_reg[31] ;\n output \\not_strict_mode.app_rd_data_reg[15] ;\n output \\not_strict_mode.app_rd_data_reg[23] ;\n output \\not_strict_mode.app_rd_data_reg[7] ;\n output \\not_strict_mode.app_rd_data_reg[30] ;\n output \\not_strict_mode.app_rd_data_reg[14] ;\n output \\not_strict_mode.app_rd_data_reg[22] ;\n output \\not_strict_mode.app_rd_data_reg[6] ;\n output \\not_strict_mode.app_rd_data_reg[29] ;\n output \\not_strict_mode.app_rd_data_reg[13] ;\n output \\not_strict_mode.app_rd_data_reg[21] ;\n output \\not_strict_mode.app_rd_data_reg[5] ;\n output \\not_strict_mode.app_rd_data_reg[28] ;\n output \\not_strict_mode.app_rd_data_reg[12] ;\n output \\not_strict_mode.app_rd_data_reg[20] ;\n output \\not_strict_mode.app_rd_data_reg[4] ;\n output \\not_strict_mode.app_rd_data_reg[27] ;\n output \\not_strict_mode.app_rd_data_reg[11] ;\n output \\not_strict_mode.app_rd_data_reg[19] ;\n output \\not_strict_mode.app_rd_data_reg[3] ;\n output \\not_strict_mode.app_rd_data_reg[26] ;\n output \\not_strict_mode.app_rd_data_reg[10] ;\n output \\not_strict_mode.app_rd_data_reg[18] ;\n output \\not_strict_mode.app_rd_data_reg[2] ;\n output \\not_strict_mode.app_rd_data_reg[25] ;\n output \\not_strict_mode.app_rd_data_reg[9] ;\n output \\not_strict_mode.app_rd_data_reg[17] ;\n output \\not_strict_mode.app_rd_data_reg[1] ;\n output \\not_strict_mode.app_rd_data_reg[24] ;\n output \\not_strict_mode.app_rd_data_reg[8] ;\n output \\not_strict_mode.app_rd_data_reg[16] ;\n output \\not_strict_mode.app_rd_data_reg[0] ;\n output \\read_fifo.tail_r_reg[0] ;\n output \\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n output \\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n output \\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n output \\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n output \\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n output \\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n output \\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n output \\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n output [255:0]\\not_strict_mode.app_rd_data_reg[255]_0 ;\n output pi_phase_locked_all_r1_reg;\n output \\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ;\n output \\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ;\n output \\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ;\n output \\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ;\n output \\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ;\n output \\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ;\n output \\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ;\n output \\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[31]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[31]_1 ;\n output [63:0]\\my_empty_reg[7] ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[23]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[23]_1 ;\n output [63:0]\\my_empty_reg[7]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[15]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[15]_1 ;\n output [63:0]\\my_empty_reg[7]_1 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[7]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[7]_1 ;\n output [63:0]\\my_empty_reg[7]_2 ;\n output ofs_rdy_r_reg;\n output ofs_rdy_r_reg_0;\n output [8:0]\\po_rdval_cnt_reg[8] ;\n output [5:0]\\pi_rdval_cnt_reg[5] ;\n output phy_if_empty_r_reg;\n output p_0_out;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n output \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n output \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n output \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n output \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n input \\gen_byte_sel_div1.calib_in_common_reg ;\n input \\calib_sel_reg[0] ;\n input pi_en_stg2_f_reg;\n input pi_stg2_f_incdec_reg;\n input freq_refclk;\n input mem_refclk;\n input [3:0]mem_dqs_in;\n input \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n input sync_pulse;\n input CLK;\n input [5:0]COUNTERLOADVAL;\n input \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n input ck_po_stg2_f_en_reg;\n input ck_po_stg2_f_indec_reg;\n input delay_done_r4_reg;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[255] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[254] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[253] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[252] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[251] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[250] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[249] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[248] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n input [31:0]mem_dq_in;\n input idelay_inc;\n input LD0;\n input CLKB0;\n input phy_if_reset;\n input \\gen_byte_sel_div1.calib_in_common_reg_3 ;\n input \\calib_sel_reg[0]_0 ;\n input pi_en_stg2_f_reg_0;\n input pi_stg2_f_incdec_reg_0;\n input \\gen_byte_sel_div1.calib_in_common_reg_4 ;\n input [5:0]\\calib_zero_inputs_reg[0] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_5 ;\n input ck_po_stg2_f_en_reg_0;\n input ck_po_stg2_f_indec_reg_0;\n input delay_done_r4_reg_0;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[247] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[246] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[245] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[244] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[243] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[242] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[241] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[240] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_6 ;\n input LD0_3;\n input CLKB0_7;\n input \\gen_byte_sel_div1.calib_in_common_reg_7 ;\n input \\calib_sel_reg[1] ;\n input pi_en_stg2_f_reg_1;\n input pi_stg2_f_incdec_reg_1;\n input \\gen_byte_sel_div1.calib_in_common_reg_8 ;\n input [5:0]\\calib_zero_inputs_reg[0]_0 ;\n input \\gen_byte_sel_div1.calib_in_common_reg_9 ;\n input ck_po_stg2_f_en_reg_1;\n input ck_po_stg2_f_indec_reg_1;\n input delay_done_r4_reg_1;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[239] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[238] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[237] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[236] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[235] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[234] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[233] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[232] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_10 ;\n input LD0_4;\n input CLKB0_8;\n input \\gen_byte_sel_div1.calib_in_common_reg_11 ;\n input \\calib_sel_reg[0]_1 ;\n input pi_en_stg2_f_reg_2;\n input pi_stg2_f_incdec_reg_2;\n input \\gen_byte_sel_div1.calib_in_common_reg_12 ;\n input [5:0]\\calib_zero_inputs_reg[0]_1 ;\n input \\gen_byte_sel_div1.calib_in_common_reg_13 ;\n input ck_po_stg2_f_en_reg_2;\n input ck_po_stg2_f_indec_reg_2;\n input delay_done_r4_reg_2;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[231] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[230] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[229] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[228] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[227] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[226] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[225] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[224] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_14 ;\n input LD0_5;\n input CLKB0_9;\n input phy_ctl_mstr_empty;\n input phy_ctl_wr_i2;\n input pll_locked;\n input phy_read_calib;\n input in0;\n input phy_write_calib;\n input [10:0]Q;\n input RST0;\n input phy_ctl_wr_i2_reg;\n input \\rclk_delay_reg[11]_0 ;\n input rstdiv0_sync_r1_reg_rep__9;\n input rst_primitives_reg_1;\n input mux_wrdata_en;\n input [0:0]mcGo_w__0;\n input [0:0]\\read_fifo.fifo_out_data_r_reg[6] ;\n input ram_init_done_r;\n input init_calib_complete_reg_rep;\n input [31:0]\\write_buffer.wr_buf_out_data_reg[287] ;\n input prbs_rdlvl_start_reg;\n input out;\n input [0:0]ref_dll_lock_w;\n input sys_rst;\n input [0:0]\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ;\n input mmcm_locked;\n input \\byte_r_reg[0] ;\n input \\byte_r_reg[1] ;\n input [0:0]tail_r;\n input [1:0]\\rd_mux_sel_r_reg[1] ;\n input \\read_fifo.fifo_out_data_r_reg[6]_0 ;\n input [1:0]DOC;\n input [1:0]DOB;\n input [1:0]DOA;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ;\n input [1:0]A;\n input [255:0]mux_wrdata;\n input [31:0]mux_wrdata_mask;\n input [0:0]E;\n input [7:0]\\fine_delay_mod_reg[23] ;\n input [0:0]\\gen_byte_sel_div1.calib_in_common_reg_15 ;\n input [7:0]\\calib_sel_reg[0]_2 ;\n input [0:0]\\gen_byte_sel_div1.calib_in_common_reg_16 ;\n input [7:0]\\calib_sel_reg[1]_0 ;\n input [0:0]\\gen_byte_sel_div1.calib_in_common_reg_17 ;\n input [7:0]\\calib_sel_reg[0]_3 ;\n input [1:0]\\calib_sel_reg[1]_1 ;\n input [1:0]\\po_stg2_wrcal_cnt_reg[1] ;\n\n wire [1:0]A;\n wire A_byte_rd_en;\n wire [5:0]A_pi_counter_read_val;\n (* async_reg = \"true\" *) wire A_pi_rst_div2;\n wire [8:0]A_po_counter_read_val;\n wire A_rst_primitives;\n wire B_byte_rd_en;\n wire [5:0]B_pi_counter_read_val;\n (* async_reg = \"true\" *) wire B_pi_rst_div2;\n wire [8:0]B_po_counter_read_val;\n wire B_rclk;\n wire CLK;\n wire CLKB0;\n wire CLKB0_7;\n wire CLKB0_8;\n wire CLKB0_9;\n wire [5:0]COUNTERLOADVAL;\n wire C_byte_rd_en;\n wire [5:0]C_pi_counter_read_val;\n (* async_reg = \"true\" *) wire C_pi_rst_div2;\n wire [8:0]C_po_counter_read_val;\n wire [1:0]DOA;\n wire [1:0]DOB;\n wire [1:0]DOC;\n wire D_byte_rd_en;\n (* async_reg = \"true\" *) wire D_pi_rst_div2;\n wire [0:0]E;\n wire LD0;\n wire LD0_3;\n wire LD0_4;\n wire LD0_5;\n wire [10:0]Q;\n wire RST0;\n wire [0:0]_phy_ctl_full_p__0;\n wire \\byte_r_reg[0] ;\n wire \\byte_r_reg[1] ;\n wire \\calib_sel_reg[0] ;\n wire \\calib_sel_reg[0]_0 ;\n wire \\calib_sel_reg[0]_1 ;\n wire [7:0]\\calib_sel_reg[0]_2 ;\n wire [7:0]\\calib_sel_reg[0]_3 ;\n wire \\calib_sel_reg[1] ;\n wire [7:0]\\calib_sel_reg[1]_0 ;\n wire [1:0]\\calib_sel_reg[1]_1 ;\n wire [5:0]\\calib_zero_inputs_reg[0] ;\n wire [5:0]\\calib_zero_inputs_reg[0]_0 ;\n wire [5:0]\\calib_zero_inputs_reg[0]_1 ;\n wire ck_po_stg2_f_en_reg;\n wire ck_po_stg2_f_en_reg_0;\n wire ck_po_stg2_f_en_reg_1;\n wire ck_po_stg2_f_en_reg_2;\n wire ck_po_stg2_f_indec_reg;\n wire ck_po_stg2_f_indec_reg_0;\n wire ck_po_stg2_f_indec_reg_1;\n wire ck_po_stg2_f_indec_reg_2;\n wire [63:0]\\data_bytes_r_reg[63] ;\n wire \\ddr_byte_lane_A.ddr_byte_lane_A_n_2 ;\n wire \\ddr_byte_lane_C.ddr_byte_lane_C_n_2 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_154 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_2 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_222 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_223 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_224 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_225 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_226 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_227 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_228 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_229 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_230 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_231 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_232 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_233 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_234 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_235 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_236 ;\n wire delay_done_r4_reg;\n wire delay_done_r4_reg_0;\n wire delay_done_r4_reg_1;\n wire delay_done_r4_reg_2;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;\n wire [0:0]\\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ;\n wire [3:3]\\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1 ;\n wire [3:0]\\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4 ;\n wire [7:0]\\fine_delay_mod_reg[23] ;\n wire freq_refclk;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_10 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_11 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_12 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_13 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_14 ;\n wire [0:0]\\gen_byte_sel_div1.calib_in_common_reg_15 ;\n wire [0:0]\\gen_byte_sel_div1.calib_in_common_reg_16 ;\n wire [0:0]\\gen_byte_sel_div1.calib_in_common_reg_17 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_3 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_4 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_5 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_6 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_7 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_8 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_9 ;\n wire \\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n wire \\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n wire \\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n wire \\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;\n wire \\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n wire \\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n wire \\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n wire \\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ;\n wire idelay_inc;\n wire idelay_ld_rst;\n wire idelay_ld_rst_0;\n wire idelay_ld_rst_1;\n wire idelay_ld_rst_2;\n wire [3:3]if_empty_r;\n wire [3:3]if_empty_r_2;\n wire [3:3]if_empty_r_5;\n wire in0;\n wire init_calib_complete_reg_rep;\n wire \\mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13 ;\n wire mcGo_reg_0;\n wire [0:0]mcGo_w;\n wire [0:0]mcGo_w__0;\n wire [31:0]mem_dq_in;\n wire [35:0]mem_dq_out;\n wire [35:0]mem_dq_ts;\n wire [3:0]mem_dqs_in;\n wire [3:0]mem_dqs_out;\n wire [3:0]mem_dqs_ts;\n wire mem_refclk;\n wire mmcm_locked;\n wire mux_rd_valid_r_reg;\n wire [255:0]mux_wrdata;\n wire mux_wrdata_en;\n wire [31:0]mux_wrdata_mask;\n wire \\my_empty_reg[1] ;\n wire \\my_empty_reg[1]_0 ;\n wire \\my_empty_reg[1]_1 ;\n wire \\my_empty_reg[1]_2 ;\n wire [63:0]\\my_empty_reg[7] ;\n wire [63:0]\\my_empty_reg[7]_0 ;\n wire [63:0]\\my_empty_reg[7]_1 ;\n wire [63:0]\\my_empty_reg[7]_2 ;\n wire \\not_strict_mode.app_rd_data_reg[0] ;\n wire \\not_strict_mode.app_rd_data_reg[100] ;\n wire \\not_strict_mode.app_rd_data_reg[101] ;\n wire \\not_strict_mode.app_rd_data_reg[102] ;\n wire \\not_strict_mode.app_rd_data_reg[103] ;\n wire \\not_strict_mode.app_rd_data_reg[104] ;\n wire \\not_strict_mode.app_rd_data_reg[105] ;\n wire \\not_strict_mode.app_rd_data_reg[106] ;\n wire \\not_strict_mode.app_rd_data_reg[107] ;\n wire \\not_strict_mode.app_rd_data_reg[108] ;\n wire \\not_strict_mode.app_rd_data_reg[109] ;\n wire \\not_strict_mode.app_rd_data_reg[10] ;\n wire \\not_strict_mode.app_rd_data_reg[110] ;\n wire \\not_strict_mode.app_rd_data_reg[111] ;\n wire \\not_strict_mode.app_rd_data_reg[112] ;\n wire \\not_strict_mode.app_rd_data_reg[113] ;\n wire \\not_strict_mode.app_rd_data_reg[114] ;\n wire \\not_strict_mode.app_rd_data_reg[115] ;\n wire \\not_strict_mode.app_rd_data_reg[116] ;\n wire \\not_strict_mode.app_rd_data_reg[117] ;\n wire \\not_strict_mode.app_rd_data_reg[118] ;\n wire \\not_strict_mode.app_rd_data_reg[119] ;\n wire \\not_strict_mode.app_rd_data_reg[11] ;\n wire \\not_strict_mode.app_rd_data_reg[120] ;\n wire \\not_strict_mode.app_rd_data_reg[121] ;\n wire \\not_strict_mode.app_rd_data_reg[122] ;\n wire \\not_strict_mode.app_rd_data_reg[123] ;\n wire \\not_strict_mode.app_rd_data_reg[124] ;\n wire \\not_strict_mode.app_rd_data_reg[125] ;\n wire \\not_strict_mode.app_rd_data_reg[126] ;\n wire \\not_strict_mode.app_rd_data_reg[127] ;\n wire \\not_strict_mode.app_rd_data_reg[128] ;\n wire \\not_strict_mode.app_rd_data_reg[129] ;\n wire \\not_strict_mode.app_rd_data_reg[12] ;\n wire \\not_strict_mode.app_rd_data_reg[130] ;\n wire \\not_strict_mode.app_rd_data_reg[131] ;\n wire \\not_strict_mode.app_rd_data_reg[132] ;\n wire \\not_strict_mode.app_rd_data_reg[133] ;\n wire \\not_strict_mode.app_rd_data_reg[134] ;\n wire \\not_strict_mode.app_rd_data_reg[135] ;\n wire \\not_strict_mode.app_rd_data_reg[136] ;\n wire \\not_strict_mode.app_rd_data_reg[137] ;\n wire \\not_strict_mode.app_rd_data_reg[138] ;\n wire \\not_strict_mode.app_rd_data_reg[139] ;\n wire \\not_strict_mode.app_rd_data_reg[13] ;\n wire \\not_strict_mode.app_rd_data_reg[140] ;\n wire \\not_strict_mode.app_rd_data_reg[141] ;\n wire \\not_strict_mode.app_rd_data_reg[142] ;\n wire \\not_strict_mode.app_rd_data_reg[143] ;\n wire \\not_strict_mode.app_rd_data_reg[144] ;\n wire \\not_strict_mode.app_rd_data_reg[145] ;\n wire \\not_strict_mode.app_rd_data_reg[146] ;\n wire \\not_strict_mode.app_rd_data_reg[147] ;\n wire \\not_strict_mode.app_rd_data_reg[148] ;\n wire \\not_strict_mode.app_rd_data_reg[149] ;\n wire \\not_strict_mode.app_rd_data_reg[14] ;\n wire \\not_strict_mode.app_rd_data_reg[150] ;\n wire \\not_strict_mode.app_rd_data_reg[151] ;\n wire \\not_strict_mode.app_rd_data_reg[152] ;\n wire \\not_strict_mode.app_rd_data_reg[153] ;\n wire \\not_strict_mode.app_rd_data_reg[154] ;\n wire \\not_strict_mode.app_rd_data_reg[155] ;\n wire \\not_strict_mode.app_rd_data_reg[156] ;\n wire \\not_strict_mode.app_rd_data_reg[157] ;\n wire \\not_strict_mode.app_rd_data_reg[158] ;\n wire \\not_strict_mode.app_rd_data_reg[159] ;\n wire \\not_strict_mode.app_rd_data_reg[15] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[15]_0 ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[15]_1 ;\n wire \\not_strict_mode.app_rd_data_reg[160] ;\n wire \\not_strict_mode.app_rd_data_reg[161] ;\n wire \\not_strict_mode.app_rd_data_reg[162] ;\n wire \\not_strict_mode.app_rd_data_reg[163] ;\n wire \\not_strict_mode.app_rd_data_reg[164] ;\n wire \\not_strict_mode.app_rd_data_reg[165] ;\n wire \\not_strict_mode.app_rd_data_reg[166] ;\n wire \\not_strict_mode.app_rd_data_reg[167] ;\n wire \\not_strict_mode.app_rd_data_reg[168] ;\n wire \\not_strict_mode.app_rd_data_reg[169] ;\n wire \\not_strict_mode.app_rd_data_reg[16] ;\n wire \\not_strict_mode.app_rd_data_reg[170] ;\n wire \\not_strict_mode.app_rd_data_reg[171] ;\n wire \\not_strict_mode.app_rd_data_reg[172] ;\n wire \\not_strict_mode.app_rd_data_reg[173] ;\n wire \\not_strict_mode.app_rd_data_reg[174] ;\n wire \\not_strict_mode.app_rd_data_reg[175] ;\n wire \\not_strict_mode.app_rd_data_reg[176] ;\n wire \\not_strict_mode.app_rd_data_reg[177] ;\n wire \\not_strict_mode.app_rd_data_reg[178] ;\n wire \\not_strict_mode.app_rd_data_reg[179] ;\n wire \\not_strict_mode.app_rd_data_reg[17] ;\n wire \\not_strict_mode.app_rd_data_reg[180] ;\n wire \\not_strict_mode.app_rd_data_reg[181] ;\n wire \\not_strict_mode.app_rd_data_reg[182] ;\n wire \\not_strict_mode.app_rd_data_reg[183] ;\n wire \\not_strict_mode.app_rd_data_reg[184] ;\n wire \\not_strict_mode.app_rd_data_reg[185] ;\n wire \\not_strict_mode.app_rd_data_reg[186] ;\n wire \\not_strict_mode.app_rd_data_reg[187] ;\n wire \\not_strict_mode.app_rd_data_reg[188] ;\n wire \\not_strict_mode.app_rd_data_reg[189] ;\n wire \\not_strict_mode.app_rd_data_reg[18] ;\n wire \\not_strict_mode.app_rd_data_reg[190] ;\n wire \\not_strict_mode.app_rd_data_reg[191] ;\n wire \\not_strict_mode.app_rd_data_reg[192] ;\n wire \\not_strict_mode.app_rd_data_reg[193] ;\n wire \\not_strict_mode.app_rd_data_reg[194] ;\n wire \\not_strict_mode.app_rd_data_reg[195] ;\n wire \\not_strict_mode.app_rd_data_reg[196] ;\n wire \\not_strict_mode.app_rd_data_reg[197] ;\n wire \\not_strict_mode.app_rd_data_reg[198] ;\n wire \\not_strict_mode.app_rd_data_reg[199] ;\n wire \\not_strict_mode.app_rd_data_reg[19] ;\n wire \\not_strict_mode.app_rd_data_reg[1] ;\n wire \\not_strict_mode.app_rd_data_reg[200] ;\n wire \\not_strict_mode.app_rd_data_reg[201] ;\n wire \\not_strict_mode.app_rd_data_reg[202] ;\n wire \\not_strict_mode.app_rd_data_reg[203] ;\n wire \\not_strict_mode.app_rd_data_reg[204] ;\n wire \\not_strict_mode.app_rd_data_reg[205] ;\n wire \\not_strict_mode.app_rd_data_reg[206] ;\n wire \\not_strict_mode.app_rd_data_reg[207] ;\n wire \\not_strict_mode.app_rd_data_reg[208] ;\n wire \\not_strict_mode.app_rd_data_reg[209] ;\n wire \\not_strict_mode.app_rd_data_reg[20] ;\n wire \\not_strict_mode.app_rd_data_reg[210] ;\n wire \\not_strict_mode.app_rd_data_reg[211] ;\n wire \\not_strict_mode.app_rd_data_reg[212] ;\n wire \\not_strict_mode.app_rd_data_reg[213] ;\n wire \\not_strict_mode.app_rd_data_reg[214] ;\n wire \\not_strict_mode.app_rd_data_reg[215] ;\n wire \\not_strict_mode.app_rd_data_reg[216] ;\n wire \\not_strict_mode.app_rd_data_reg[217] ;\n wire \\not_strict_mode.app_rd_data_reg[218] ;\n wire \\not_strict_mode.app_rd_data_reg[219] ;\n wire \\not_strict_mode.app_rd_data_reg[21] ;\n wire \\not_strict_mode.app_rd_data_reg[220] ;\n wire \\not_strict_mode.app_rd_data_reg[221] ;\n wire \\not_strict_mode.app_rd_data_reg[222] ;\n wire \\not_strict_mode.app_rd_data_reg[223] ;\n wire \\not_strict_mode.app_rd_data_reg[224] ;\n wire \\not_strict_mode.app_rd_data_reg[225] ;\n wire \\not_strict_mode.app_rd_data_reg[226] ;\n wire \\not_strict_mode.app_rd_data_reg[227] ;\n wire \\not_strict_mode.app_rd_data_reg[228] ;\n wire \\not_strict_mode.app_rd_data_reg[228]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[229] ;\n wire \\not_strict_mode.app_rd_data_reg[22] ;\n wire \\not_strict_mode.app_rd_data_reg[230] ;\n wire \\not_strict_mode.app_rd_data_reg[231] ;\n wire \\not_strict_mode.app_rd_data_reg[232] ;\n wire \\not_strict_mode.app_rd_data_reg[233] ;\n wire \\not_strict_mode.app_rd_data_reg[234] ;\n wire \\not_strict_mode.app_rd_data_reg[235] ;\n wire \\not_strict_mode.app_rd_data_reg[236] ;\n wire \\not_strict_mode.app_rd_data_reg[236]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[237] ;\n wire \\not_strict_mode.app_rd_data_reg[238] ;\n wire \\not_strict_mode.app_rd_data_reg[239] ;\n wire \\not_strict_mode.app_rd_data_reg[23] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[23]_0 ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[23]_1 ;\n wire \\not_strict_mode.app_rd_data_reg[240] ;\n wire \\not_strict_mode.app_rd_data_reg[241] ;\n wire \\not_strict_mode.app_rd_data_reg[242] ;\n wire \\not_strict_mode.app_rd_data_reg[243] ;\n wire \\not_strict_mode.app_rd_data_reg[244] ;\n wire \\not_strict_mode.app_rd_data_reg[244]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[245] ;\n wire \\not_strict_mode.app_rd_data_reg[246] ;\n wire \\not_strict_mode.app_rd_data_reg[247] ;\n wire \\not_strict_mode.app_rd_data_reg[248] ;\n wire \\not_strict_mode.app_rd_data_reg[249] ;\n wire \\not_strict_mode.app_rd_data_reg[24] ;\n wire \\not_strict_mode.app_rd_data_reg[250] ;\n wire \\not_strict_mode.app_rd_data_reg[251] ;\n wire \\not_strict_mode.app_rd_data_reg[252] ;\n wire \\not_strict_mode.app_rd_data_reg[252]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[253] ;\n wire \\not_strict_mode.app_rd_data_reg[254] ;\n wire \\not_strict_mode.app_rd_data_reg[255] ;\n wire [255:0]\\not_strict_mode.app_rd_data_reg[255]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[25] ;\n wire \\not_strict_mode.app_rd_data_reg[26] ;\n wire \\not_strict_mode.app_rd_data_reg[27] ;\n wire \\not_strict_mode.app_rd_data_reg[28] ;\n wire \\not_strict_mode.app_rd_data_reg[29] ;\n wire \\not_strict_mode.app_rd_data_reg[2] ;\n wire \\not_strict_mode.app_rd_data_reg[30] ;\n wire \\not_strict_mode.app_rd_data_reg[31] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[31]_0 ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[31]_1 ;\n wire \\not_strict_mode.app_rd_data_reg[32] ;\n wire \\not_strict_mode.app_rd_data_reg[33] ;\n wire \\not_strict_mode.app_rd_data_reg[34] ;\n wire \\not_strict_mode.app_rd_data_reg[35] ;\n wire \\not_strict_mode.app_rd_data_reg[36] ;\n wire \\not_strict_mode.app_rd_data_reg[37] ;\n wire \\not_strict_mode.app_rd_data_reg[38] ;\n wire \\not_strict_mode.app_rd_data_reg[39] ;\n wire \\not_strict_mode.app_rd_data_reg[3] ;\n wire \\not_strict_mode.app_rd_data_reg[40] ;\n wire \\not_strict_mode.app_rd_data_reg[41] ;\n wire \\not_strict_mode.app_rd_data_reg[42] ;\n wire \\not_strict_mode.app_rd_data_reg[43] ;\n wire \\not_strict_mode.app_rd_data_reg[44] ;\n wire \\not_strict_mode.app_rd_data_reg[45] ;\n wire \\not_strict_mode.app_rd_data_reg[46] ;\n wire \\not_strict_mode.app_rd_data_reg[47] ;\n wire \\not_strict_mode.app_rd_data_reg[48] ;\n wire \\not_strict_mode.app_rd_data_reg[49] ;\n wire \\not_strict_mode.app_rd_data_reg[4] ;\n wire \\not_strict_mode.app_rd_data_reg[50] ;\n wire \\not_strict_mode.app_rd_data_reg[51] ;\n wire \\not_strict_mode.app_rd_data_reg[52] ;\n wire \\not_strict_mode.app_rd_data_reg[53] ;\n wire \\not_strict_mode.app_rd_data_reg[54] ;\n wire \\not_strict_mode.app_rd_data_reg[55] ;\n wire \\not_strict_mode.app_rd_data_reg[56] ;\n wire \\not_strict_mode.app_rd_data_reg[57] ;\n wire \\not_strict_mode.app_rd_data_reg[58] ;\n wire \\not_strict_mode.app_rd_data_reg[59] ;\n wire \\not_strict_mode.app_rd_data_reg[5] ;\n wire \\not_strict_mode.app_rd_data_reg[60] ;\n wire \\not_strict_mode.app_rd_data_reg[61] ;\n wire \\not_strict_mode.app_rd_data_reg[62] ;\n wire \\not_strict_mode.app_rd_data_reg[63] ;\n wire \\not_strict_mode.app_rd_data_reg[64] ;\n wire \\not_strict_mode.app_rd_data_reg[65] ;\n wire \\not_strict_mode.app_rd_data_reg[66] ;\n wire \\not_strict_mode.app_rd_data_reg[67] ;\n wire \\not_strict_mode.app_rd_data_reg[68] ;\n wire \\not_strict_mode.app_rd_data_reg[69] ;\n wire \\not_strict_mode.app_rd_data_reg[6] ;\n wire \\not_strict_mode.app_rd_data_reg[70] ;\n wire \\not_strict_mode.app_rd_data_reg[71] ;\n wire \\not_strict_mode.app_rd_data_reg[72] ;\n wire \\not_strict_mode.app_rd_data_reg[73] ;\n wire \\not_strict_mode.app_rd_data_reg[74] ;\n wire \\not_strict_mode.app_rd_data_reg[75] ;\n wire \\not_strict_mode.app_rd_data_reg[76] ;\n wire \\not_strict_mode.app_rd_data_reg[77] ;\n wire \\not_strict_mode.app_rd_data_reg[78] ;\n wire \\not_strict_mode.app_rd_data_reg[79] ;\n wire \\not_strict_mode.app_rd_data_reg[7] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[7]_0 ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[7]_1 ;\n wire \\not_strict_mode.app_rd_data_reg[80] ;\n wire \\not_strict_mode.app_rd_data_reg[81] ;\n wire \\not_strict_mode.app_rd_data_reg[82] ;\n wire \\not_strict_mode.app_rd_data_reg[83] ;\n wire \\not_strict_mode.app_rd_data_reg[84] ;\n wire \\not_strict_mode.app_rd_data_reg[85] ;\n wire \\not_strict_mode.app_rd_data_reg[86] ;\n wire \\not_strict_mode.app_rd_data_reg[87] ;\n wire \\not_strict_mode.app_rd_data_reg[88] ;\n wire \\not_strict_mode.app_rd_data_reg[89] ;\n wire \\not_strict_mode.app_rd_data_reg[8] ;\n wire \\not_strict_mode.app_rd_data_reg[90] ;\n wire \\not_strict_mode.app_rd_data_reg[91] ;\n wire \\not_strict_mode.app_rd_data_reg[92] ;\n wire \\not_strict_mode.app_rd_data_reg[93] ;\n wire \\not_strict_mode.app_rd_data_reg[94] ;\n wire \\not_strict_mode.app_rd_data_reg[95] ;\n wire \\not_strict_mode.app_rd_data_reg[96] ;\n wire \\not_strict_mode.app_rd_data_reg[97] ;\n wire \\not_strict_mode.app_rd_data_reg[98] ;\n wire \\not_strict_mode.app_rd_data_reg[99] ;\n wire \\not_strict_mode.app_rd_data_reg[9] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ;\n wire \\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n wire [4:2]\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0 ;\n wire [4:2]\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_0 ;\n wire [4:2]\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_3 ;\n wire [4:2]\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_6 ;\n wire ofs_rdy_r_reg;\n wire ofs_rdy_r_reg_0;\n wire out;\n wire p_0_out;\n wire [15:0]phaser_ctl_bus;\n wire phy_control_i_n_0;\n wire phy_control_i_n_1;\n wire phy_control_i_n_14;\n wire phy_control_i_n_15;\n wire phy_control_i_n_16;\n wire phy_control_i_n_17;\n wire phy_ctl_mstr_empty;\n wire phy_ctl_wr_i2;\n wire phy_ctl_wr_i2_reg;\n wire [1:0]phy_encalib;\n wire phy_if_empty_r_reg;\n wire phy_if_reset;\n wire phy_rddata_en;\n wire phy_read_calib;\n wire phy_write_calib;\n wire [3:0]\\pi_dqs_found_lanes_r1_reg[3] ;\n wire pi_en_stg2_f_reg;\n wire pi_en_stg2_f_reg_0;\n wire pi_en_stg2_f_reg_1;\n wire pi_en_stg2_f_reg_2;\n wire pi_phase_locked_all_r1_reg;\n wire [5:0]\\pi_rdval_cnt_reg[5] ;\n wire pi_stg2_f_incdec_reg;\n wire pi_stg2_f_incdec_reg_0;\n wire pi_stg2_f_incdec_reg_1;\n wire pi_stg2_f_incdec_reg_2;\n wire pll_locked;\n wire [8:0]\\po_rdval_cnt_reg[8] ;\n wire [1:0]\\po_stg2_wrcal_cnt_reg[1] ;\n wire prbs_rdlvl_start_reg;\n wire ram_init_done_r;\n wire rclk_delay_11;\n wire \\rclk_delay_reg[10]_srl11_n_0 ;\n wire \\rclk_delay_reg[11]_0 ;\n wire rd_buf_we;\n wire [1:0]\\rd_mux_sel_r_reg[1] ;\n wire [0:0]\\read_fifo.fifo_out_data_r_reg[6] ;\n wire \\read_fifo.fifo_out_data_r_reg[6]_0 ;\n wire \\read_fifo.tail_r_reg[0] ;\n wire [0:0]ref_dll_lock_w;\n wire [0:0]ref_dll_lock_w__0;\n wire rst_primitives;\n wire rst_primitives_reg_0;\n wire rst_primitives_reg_1;\n wire rst_r4;\n wire [0:0]\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ;\n wire rst_sync_r1_reg;\n wire rstdiv0_sync_r1_reg_rep__9;\n wire sync_pulse;\n wire sys_rst;\n wire [0:0]tail_r;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[224] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[225] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[226] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[227] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[228] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[229] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[230] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[231] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[232] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[233] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[234] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[235] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[236] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[237] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[238] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[239] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[240] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[241] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[242] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[243] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[244] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[245] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[246] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[247] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[248] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[249] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[250] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[251] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[252] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[253] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[254] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[255] ;\n wire [31:0]\\write_buffer.wr_buf_out_data_reg[287] ;\n\n FDRE #(\n .INIT(1'b0)) \n A_rst_primitives_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rst_primitives),\n .Q(A_rst_primitives),\n .R(1'b0));\n ddr3_ifmig_7series_v4_0_ddr_byte_lane \\ddr_byte_lane_A.ddr_byte_lane_A \n (.A(A),\n .A_byte_rd_en(A_byte_rd_en),\n .A_rst_primitives(A_rst_primitives),\n .B_byte_rd_en(B_byte_rd_en),\n .CLK(CLK),\n .CLKB0(CLKB0),\n .COUNTERLOADVAL(COUNTERLOADVAL),\n .COUNTERREADVAL(A_pi_counter_read_val),\n .D_byte_rd_en(D_byte_rd_en),\n .E(E),\n .LD0(LD0),\n .PCENABLECALIB(phy_encalib),\n .Q(\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0 ),\n .\\byte_r_reg[0] (\\byte_r_reg[0] ),\n .\\byte_r_reg[1] (\\byte_r_reg[1] ),\n .\\calib_sel_reg[0] (\\calib_sel_reg[0] ),\n .ck_po_stg2_f_en_reg(ck_po_stg2_f_en_reg),\n .ck_po_stg2_f_indec_reg(ck_po_stg2_f_indec_reg),\n .\\data_bytes_r_reg[63] (\\data_bytes_r_reg[63] ),\n .delay_done_r4_reg(delay_done_r4_reg),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 (\\not_strict_mode.app_rd_data_reg[79] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 (\\not_strict_mode.app_rd_data_reg[87] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2 (\\not_strict_mode.app_rd_data_reg[71] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 (\\not_strict_mode.app_rd_data_reg[111] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 (\\not_strict_mode.app_rd_data_reg[119] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2 (\\not_strict_mode.app_rd_data_reg[103] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 (\\not_strict_mode.app_rd_data_reg[143] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 (\\not_strict_mode.app_rd_data_reg[151] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2 (\\not_strict_mode.app_rd_data_reg[135] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 (\\not_strict_mode.app_rd_data_reg[175] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 (\\not_strict_mode.app_rd_data_reg[183] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2 (\\not_strict_mode.app_rd_data_reg[167] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 (\\not_strict_mode.app_rd_data_reg[207] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 (\\not_strict_mode.app_rd_data_reg[215] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2 (\\not_strict_mode.app_rd_data_reg[199] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 (\\not_strict_mode.app_rd_data_reg[239] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 (\\not_strict_mode.app_rd_data_reg[247] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2 (\\not_strict_mode.app_rd_data_reg[231] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\\not_strict_mode.app_rd_data_reg[14] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 (\\not_strict_mode.app_rd_data_reg[22] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 (\\not_strict_mode.app_rd_data_reg[6] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 (\\not_strict_mode.app_rd_data_reg[46] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 (\\not_strict_mode.app_rd_data_reg[54] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 (\\not_strict_mode.app_rd_data_reg[38] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 (\\not_strict_mode.app_rd_data_reg[78] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 (\\not_strict_mode.app_rd_data_reg[86] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 (\\not_strict_mode.app_rd_data_reg[70] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 (\\not_strict_mode.app_rd_data_reg[110] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 (\\not_strict_mode.app_rd_data_reg[118] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 (\\not_strict_mode.app_rd_data_reg[102] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 (\\not_strict_mode.app_rd_data_reg[142] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 (\\not_strict_mode.app_rd_data_reg[150] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 (\\not_strict_mode.app_rd_data_reg[134] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 (\\not_strict_mode.app_rd_data_reg[174] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 (\\not_strict_mode.app_rd_data_reg[182] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 (\\not_strict_mode.app_rd_data_reg[166] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 (\\not_strict_mode.app_rd_data_reg[206] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 (\\not_strict_mode.app_rd_data_reg[214] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 (\\not_strict_mode.app_rd_data_reg[198] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 (\\not_strict_mode.app_rd_data_reg[238] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 (\\not_strict_mode.app_rd_data_reg[246] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 (\\not_strict_mode.app_rd_data_reg[230] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\\not_strict_mode.app_rd_data_reg[13] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 (\\not_strict_mode.app_rd_data_reg[21] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 (\\not_strict_mode.app_rd_data_reg[5] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 (\\not_strict_mode.app_rd_data_reg[45] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 (\\not_strict_mode.app_rd_data_reg[53] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 (\\not_strict_mode.app_rd_data_reg[37] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 (\\not_strict_mode.app_rd_data_reg[77] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 (\\not_strict_mode.app_rd_data_reg[85] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 (\\not_strict_mode.app_rd_data_reg[69] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 (\\not_strict_mode.app_rd_data_reg[109] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 (\\not_strict_mode.app_rd_data_reg[117] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 (\\not_strict_mode.app_rd_data_reg[101] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 (\\not_strict_mode.app_rd_data_reg[141] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 (\\not_strict_mode.app_rd_data_reg[149] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 (\\not_strict_mode.app_rd_data_reg[133] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 (\\not_strict_mode.app_rd_data_reg[173] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 (\\not_strict_mode.app_rd_data_reg[181] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 (\\not_strict_mode.app_rd_data_reg[165] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 (\\not_strict_mode.app_rd_data_reg[205] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 (\\not_strict_mode.app_rd_data_reg[213] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 (\\not_strict_mode.app_rd_data_reg[197] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 (\\not_strict_mode.app_rd_data_reg[237] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 (\\not_strict_mode.app_rd_data_reg[245] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 (\\not_strict_mode.app_rd_data_reg[229] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\\not_strict_mode.app_rd_data_reg[12] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 (\\not_strict_mode.app_rd_data_reg[20] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 (\\not_strict_mode.app_rd_data_reg[4] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 (\\not_strict_mode.app_rd_data_reg[44] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 (\\not_strict_mode.app_rd_data_reg[52] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 (\\not_strict_mode.app_rd_data_reg[36] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 (\\not_strict_mode.app_rd_data_reg[76] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 (\\not_strict_mode.app_rd_data_reg[84] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 (\\not_strict_mode.app_rd_data_reg[68] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 (\\not_strict_mode.app_rd_data_reg[108] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 (\\not_strict_mode.app_rd_data_reg[116] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 (\\not_strict_mode.app_rd_data_reg[100] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 (\\not_strict_mode.app_rd_data_reg[140] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 (\\not_strict_mode.app_rd_data_reg[148] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 (\\not_strict_mode.app_rd_data_reg[132] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 (\\not_strict_mode.app_rd_data_reg[172] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 (\\not_strict_mode.app_rd_data_reg[180] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 (\\not_strict_mode.app_rd_data_reg[164] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 (\\not_strict_mode.app_rd_data_reg[204] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 (\\not_strict_mode.app_rd_data_reg[212] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 (\\not_strict_mode.app_rd_data_reg[196] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 (\\not_strict_mode.app_rd_data_reg[236]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 (\\not_strict_mode.app_rd_data_reg[244]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 (\\not_strict_mode.app_rd_data_reg[228]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\\not_strict_mode.app_rd_data_reg[11] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 (\\not_strict_mode.app_rd_data_reg[19] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 (\\not_strict_mode.app_rd_data_reg[3] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 (\\not_strict_mode.app_rd_data_reg[43] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 (\\not_strict_mode.app_rd_data_reg[51] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 (\\not_strict_mode.app_rd_data_reg[35] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 (\\not_strict_mode.app_rd_data_reg[75] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 (\\not_strict_mode.app_rd_data_reg[83] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 (\\not_strict_mode.app_rd_data_reg[67] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 (\\not_strict_mode.app_rd_data_reg[107] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 (\\not_strict_mode.app_rd_data_reg[115] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 (\\not_strict_mode.app_rd_data_reg[99] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 (\\not_strict_mode.app_rd_data_reg[139] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 (\\not_strict_mode.app_rd_data_reg[147] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 (\\not_strict_mode.app_rd_data_reg[131] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 (\\not_strict_mode.app_rd_data_reg[171] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 (\\not_strict_mode.app_rd_data_reg[179] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 (\\not_strict_mode.app_rd_data_reg[163] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 (\\not_strict_mode.app_rd_data_reg[203] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 (\\not_strict_mode.app_rd_data_reg[211] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 (\\not_strict_mode.app_rd_data_reg[195] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 (\\not_strict_mode.app_rd_data_reg[235] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 (\\not_strict_mode.app_rd_data_reg[243] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 (\\not_strict_mode.app_rd_data_reg[227] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\\not_strict_mode.app_rd_data_reg[10] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 (\\not_strict_mode.app_rd_data_reg[18] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 (\\not_strict_mode.app_rd_data_reg[2] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 (\\not_strict_mode.app_rd_data_reg[42] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 (\\not_strict_mode.app_rd_data_reg[50] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 (\\not_strict_mode.app_rd_data_reg[34] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 (\\not_strict_mode.app_rd_data_reg[74] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 (\\not_strict_mode.app_rd_data_reg[82] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 (\\not_strict_mode.app_rd_data_reg[66] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 (\\not_strict_mode.app_rd_data_reg[106] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 (\\not_strict_mode.app_rd_data_reg[114] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 (\\not_strict_mode.app_rd_data_reg[98] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 (\\not_strict_mode.app_rd_data_reg[138] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 (\\not_strict_mode.app_rd_data_reg[146] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 (\\not_strict_mode.app_rd_data_reg[130] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 (\\not_strict_mode.app_rd_data_reg[170] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 (\\not_strict_mode.app_rd_data_reg[178] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 (\\not_strict_mode.app_rd_data_reg[162] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 (\\not_strict_mode.app_rd_data_reg[202] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 (\\not_strict_mode.app_rd_data_reg[210] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 (\\not_strict_mode.app_rd_data_reg[194] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 (\\not_strict_mode.app_rd_data_reg[234] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 (\\not_strict_mode.app_rd_data_reg[242] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 (\\not_strict_mode.app_rd_data_reg[226] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\\not_strict_mode.app_rd_data_reg[9] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 (\\not_strict_mode.app_rd_data_reg[17] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 (\\not_strict_mode.app_rd_data_reg[1] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 (\\not_strict_mode.app_rd_data_reg[41] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 (\\not_strict_mode.app_rd_data_reg[49] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 (\\not_strict_mode.app_rd_data_reg[33] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 (\\not_strict_mode.app_rd_data_reg[73] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 (\\not_strict_mode.app_rd_data_reg[81] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 (\\not_strict_mode.app_rd_data_reg[65] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 (\\not_strict_mode.app_rd_data_reg[105] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 (\\not_strict_mode.app_rd_data_reg[113] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 (\\not_strict_mode.app_rd_data_reg[97] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 (\\not_strict_mode.app_rd_data_reg[137] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 (\\not_strict_mode.app_rd_data_reg[145] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 (\\not_strict_mode.app_rd_data_reg[129] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 (\\not_strict_mode.app_rd_data_reg[169] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 (\\not_strict_mode.app_rd_data_reg[177] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 (\\not_strict_mode.app_rd_data_reg[161] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 (\\not_strict_mode.app_rd_data_reg[201] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 (\\not_strict_mode.app_rd_data_reg[209] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 (\\not_strict_mode.app_rd_data_reg[193] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 (\\not_strict_mode.app_rd_data_reg[233] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 (\\not_strict_mode.app_rd_data_reg[241] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 (\\not_strict_mode.app_rd_data_reg[225] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (\\not_strict_mode.app_rd_data_reg[8] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 (\\not_strict_mode.app_rd_data_reg[16] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 (\\not_strict_mode.app_rd_data_reg[0] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 (\\not_strict_mode.app_rd_data_reg[40] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 (\\not_strict_mode.app_rd_data_reg[48] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 (\\not_strict_mode.app_rd_data_reg[32] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] (\\not_strict_mode.app_rd_data_reg[72] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 (\\not_strict_mode.app_rd_data_reg[80] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 (\\not_strict_mode.app_rd_data_reg[64] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (\\not_strict_mode.app_rd_data_reg[104] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 (\\not_strict_mode.app_rd_data_reg[112] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 (\\not_strict_mode.app_rd_data_reg[96] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] (\\not_strict_mode.app_rd_data_reg[136] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 (\\not_strict_mode.app_rd_data_reg[144] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 (\\not_strict_mode.app_rd_data_reg[128] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] (\\not_strict_mode.app_rd_data_reg[168] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 (\\not_strict_mode.app_rd_data_reg[176] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 (\\not_strict_mode.app_rd_data_reg[160] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] (\\not_strict_mode.app_rd_data_reg[200] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 (\\not_strict_mode.app_rd_data_reg[208] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 (\\not_strict_mode.app_rd_data_reg[192] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] (\\not_strict_mode.app_rd_data_reg[232] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 (\\not_strict_mode.app_rd_data_reg[240] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 (\\not_strict_mode.app_rd_data_reg[224] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (\\not_strict_mode.app_rd_data_reg[15] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 (\\not_strict_mode.app_rd_data_reg[23] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 (\\not_strict_mode.app_rd_data_reg[7] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 (\\not_strict_mode.app_rd_data_reg[47] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 (\\not_strict_mode.app_rd_data_reg[55] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2 (\\not_strict_mode.app_rd_data_reg[39] ),\n .\\fine_delay_mod_reg[23] (\\fine_delay_mod_reg[23] ),\n .freq_refclk(freq_refclk),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\gen_byte_sel_div1.calib_in_common_reg ),\n .\\gen_byte_sel_div1.calib_in_common_reg_0 (\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_1 (\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_2 (\\gen_byte_sel_div1.calib_in_common_reg_2 ),\n .\\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] (\\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] (\\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] (\\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] (\\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] (\\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] (\\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] (\\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] (\\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),\n .\\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] (\\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] (\\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] (\\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] (\\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] (\\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] (\\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] (\\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] (\\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),\n .\\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] (\\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] (\\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] (\\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] (\\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] (\\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] (\\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] (\\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] (\\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),\n .\\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] (\\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] (\\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] (\\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] (\\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] (\\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] (\\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] (\\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] (\\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),\n .\\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] (\\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] (\\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] (\\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] (\\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] (\\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] (\\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] (\\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] (\\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),\n .\\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] (\\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] (\\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] (\\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] (\\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] (\\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] (\\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] (\\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] (\\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),\n .\\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] (\\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] (\\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] (\\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] (\\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] (\\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] (\\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] (\\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] (\\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),\n .\\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] (\\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] (\\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] (\\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] (\\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] (\\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] (\\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] (\\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] (\\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),\n .\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] (\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ),\n .\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] (\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ),\n .\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] (\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ),\n .\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] (\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ),\n .idelay_inc(idelay_inc),\n .idelay_ld_rst(idelay_ld_rst),\n .if_empty_r(if_empty_r),\n .if_empty_r_0(if_empty_r_5),\n .init_calib_complete_reg_rep(init_calib_complete_reg_rep),\n .mem_dq_in(mem_dq_in[7:0]),\n .mem_dq_out(mem_dq_out[8:0]),\n .mem_dq_ts(mem_dq_ts[8:0]),\n .mem_dqs_in(mem_dqs_in[0]),\n .mem_dqs_out(mem_dqs_out[0]),\n .mem_dqs_ts(mem_dqs_ts[0]),\n .mem_refclk(mem_refclk),\n .mux_wrdata_en(mux_wrdata_en),\n .my_empty(\\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4 [3]),\n .\\my_empty_reg[1] (\\my_empty_reg[1] ),\n .\\my_empty_reg[7] (\\my_empty_reg[7] ),\n .\\not_strict_mode.app_rd_data_reg[120] (\\not_strict_mode.app_rd_data_reg[120] ),\n .\\not_strict_mode.app_rd_data_reg[121] (\\not_strict_mode.app_rd_data_reg[121] ),\n .\\not_strict_mode.app_rd_data_reg[122] (\\not_strict_mode.app_rd_data_reg[122] ),\n .\\not_strict_mode.app_rd_data_reg[123] (\\not_strict_mode.app_rd_data_reg[123] ),\n .\\not_strict_mode.app_rd_data_reg[124] (\\not_strict_mode.app_rd_data_reg[124] ),\n .\\not_strict_mode.app_rd_data_reg[125] (\\not_strict_mode.app_rd_data_reg[125] ),\n .\\not_strict_mode.app_rd_data_reg[126] (\\not_strict_mode.app_rd_data_reg[126] ),\n .\\not_strict_mode.app_rd_data_reg[127] (\\not_strict_mode.app_rd_data_reg[127] ),\n .\\not_strict_mode.app_rd_data_reg[152] (\\not_strict_mode.app_rd_data_reg[152] ),\n .\\not_strict_mode.app_rd_data_reg[153] (\\not_strict_mode.app_rd_data_reg[153] ),\n .\\not_strict_mode.app_rd_data_reg[154] (\\not_strict_mode.app_rd_data_reg[154] ),\n .\\not_strict_mode.app_rd_data_reg[155] (\\not_strict_mode.app_rd_data_reg[155] ),\n .\\not_strict_mode.app_rd_data_reg[156] (\\not_strict_mode.app_rd_data_reg[156] ),\n .\\not_strict_mode.app_rd_data_reg[157] (\\not_strict_mode.app_rd_data_reg[157] ),\n .\\not_strict_mode.app_rd_data_reg[158] (\\not_strict_mode.app_rd_data_reg[158] ),\n .\\not_strict_mode.app_rd_data_reg[159] (\\not_strict_mode.app_rd_data_reg[159] ),\n .\\not_strict_mode.app_rd_data_reg[184] (\\not_strict_mode.app_rd_data_reg[184] ),\n .\\not_strict_mode.app_rd_data_reg[185] (\\not_strict_mode.app_rd_data_reg[185] ),\n .\\not_strict_mode.app_rd_data_reg[186] (\\not_strict_mode.app_rd_data_reg[186] ),\n .\\not_strict_mode.app_rd_data_reg[187] (\\not_strict_mode.app_rd_data_reg[187] ),\n .\\not_strict_mode.app_rd_data_reg[188] (\\not_strict_mode.app_rd_data_reg[188] ),\n .\\not_strict_mode.app_rd_data_reg[189] (\\not_strict_mode.app_rd_data_reg[189] ),\n .\\not_strict_mode.app_rd_data_reg[190] (\\not_strict_mode.app_rd_data_reg[190] ),\n .\\not_strict_mode.app_rd_data_reg[191] (\\not_strict_mode.app_rd_data_reg[191] ),\n .\\not_strict_mode.app_rd_data_reg[216] (\\not_strict_mode.app_rd_data_reg[216] ),\n .\\not_strict_mode.app_rd_data_reg[217] (\\not_strict_mode.app_rd_data_reg[217] ),\n .\\not_strict_mode.app_rd_data_reg[218] (\\not_strict_mode.app_rd_data_reg[218] ),\n .\\not_strict_mode.app_rd_data_reg[219] (\\not_strict_mode.app_rd_data_reg[219] ),\n .\\not_strict_mode.app_rd_data_reg[220] (\\not_strict_mode.app_rd_data_reg[220] ),\n .\\not_strict_mode.app_rd_data_reg[221] (\\not_strict_mode.app_rd_data_reg[221] ),\n .\\not_strict_mode.app_rd_data_reg[222] (\\not_strict_mode.app_rd_data_reg[222] ),\n .\\not_strict_mode.app_rd_data_reg[223] (\\not_strict_mode.app_rd_data_reg[223] ),\n .\\not_strict_mode.app_rd_data_reg[248] (\\not_strict_mode.app_rd_data_reg[248] ),\n .\\not_strict_mode.app_rd_data_reg[249] (\\not_strict_mode.app_rd_data_reg[249] ),\n .\\not_strict_mode.app_rd_data_reg[24] (\\not_strict_mode.app_rd_data_reg[24] ),\n .\\not_strict_mode.app_rd_data_reg[250] (\\not_strict_mode.app_rd_data_reg[250] ),\n .\\not_strict_mode.app_rd_data_reg[251] (\\not_strict_mode.app_rd_data_reg[251] ),\n .\\not_strict_mode.app_rd_data_reg[252] (\\not_strict_mode.app_rd_data_reg[252] ),\n .\\not_strict_mode.app_rd_data_reg[252]_0 (\\not_strict_mode.app_rd_data_reg[252]_0 ),\n .\\not_strict_mode.app_rd_data_reg[253] (\\not_strict_mode.app_rd_data_reg[253] ),\n .\\not_strict_mode.app_rd_data_reg[254] (\\not_strict_mode.app_rd_data_reg[254] ),\n .\\not_strict_mode.app_rd_data_reg[255] (\\not_strict_mode.app_rd_data_reg[255] ),\n .\\not_strict_mode.app_rd_data_reg[255]_0 ({\\not_strict_mode.app_rd_data_reg[255]_0 [255:248],\\not_strict_mode.app_rd_data_reg[255]_0 [223:216],\\not_strict_mode.app_rd_data_reg[255]_0 [191:184],\\not_strict_mode.app_rd_data_reg[255]_0 [159:152],\\not_strict_mode.app_rd_data_reg[255]_0 [127:120],\\not_strict_mode.app_rd_data_reg[255]_0 [95:88],\\not_strict_mode.app_rd_data_reg[255]_0 [63:56],\\not_strict_mode.app_rd_data_reg[255]_0 [31:24]}),\n .\\not_strict_mode.app_rd_data_reg[25] (\\not_strict_mode.app_rd_data_reg[25] ),\n .\\not_strict_mode.app_rd_data_reg[26] (\\not_strict_mode.app_rd_data_reg[26] ),\n .\\not_strict_mode.app_rd_data_reg[27] (\\not_strict_mode.app_rd_data_reg[27] ),\n .\\not_strict_mode.app_rd_data_reg[28] (\\not_strict_mode.app_rd_data_reg[28] ),\n .\\not_strict_mode.app_rd_data_reg[29] (\\not_strict_mode.app_rd_data_reg[29] ),\n .\\not_strict_mode.app_rd_data_reg[30] (\\not_strict_mode.app_rd_data_reg[30] ),\n .\\not_strict_mode.app_rd_data_reg[31] (\\not_strict_mode.app_rd_data_reg[31] ),\n .\\not_strict_mode.app_rd_data_reg[31]_0 (\\not_strict_mode.app_rd_data_reg[31]_0 ),\n .\\not_strict_mode.app_rd_data_reg[31]_1 (\\not_strict_mode.app_rd_data_reg[31]_1 ),\n .\\not_strict_mode.app_rd_data_reg[56] (\\not_strict_mode.app_rd_data_reg[56] ),\n .\\not_strict_mode.app_rd_data_reg[57] (\\not_strict_mode.app_rd_data_reg[57] ),\n .\\not_strict_mode.app_rd_data_reg[58] (\\not_strict_mode.app_rd_data_reg[58] ),\n .\\not_strict_mode.app_rd_data_reg[59] (\\not_strict_mode.app_rd_data_reg[59] ),\n .\\not_strict_mode.app_rd_data_reg[60] (\\not_strict_mode.app_rd_data_reg[60] ),\n .\\not_strict_mode.app_rd_data_reg[61] (\\not_strict_mode.app_rd_data_reg[61] ),\n .\\not_strict_mode.app_rd_data_reg[62] (\\not_strict_mode.app_rd_data_reg[62] ),\n .\\not_strict_mode.app_rd_data_reg[63] (\\not_strict_mode.app_rd_data_reg[63] ),\n .\\not_strict_mode.app_rd_data_reg[88] (\\not_strict_mode.app_rd_data_reg[88] ),\n .\\not_strict_mode.app_rd_data_reg[89] (\\not_strict_mode.app_rd_data_reg[89] ),\n .\\not_strict_mode.app_rd_data_reg[90] (\\not_strict_mode.app_rd_data_reg[90] ),\n .\\not_strict_mode.app_rd_data_reg[91] (\\not_strict_mode.app_rd_data_reg[91] ),\n .\\not_strict_mode.app_rd_data_reg[92] (\\not_strict_mode.app_rd_data_reg[92] ),\n .\\not_strict_mode.app_rd_data_reg[93] (\\not_strict_mode.app_rd_data_reg[93] ),\n .\\not_strict_mode.app_rd_data_reg[94] (\\not_strict_mode.app_rd_data_reg[94] ),\n .\\not_strict_mode.app_rd_data_reg[95] (\\not_strict_mode.app_rd_data_reg[95] ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ),\n .p_0_out(p_0_out),\n .phaser_ctl_bus({phaser_ctl_bus[9:8],phaser_ctl_bus[4],phaser_ctl_bus[0]}),\n .phy_dout({mux_wrdata_mask[31],mux_wrdata_mask[27],mux_wrdata_mask[23],mux_wrdata_mask[19],mux_wrdata_mask[15],mux_wrdata_mask[11],mux_wrdata_mask[7],mux_wrdata_mask[3],mux_wrdata[248],mux_wrdata[216],mux_wrdata[184],mux_wrdata[152],mux_wrdata[120],mux_wrdata[88],mux_wrdata[56],mux_wrdata[24],mux_wrdata[249],mux_wrdata[217],mux_wrdata[185],mux_wrdata[153],mux_wrdata[121],mux_wrdata[89],mux_wrdata[57],mux_wrdata[25],mux_wrdata[250],mux_wrdata[218],mux_wrdata[186],mux_wrdata[154],mux_wrdata[122],mux_wrdata[90],mux_wrdata[58],mux_wrdata[26],mux_wrdata[251],mux_wrdata[219],mux_wrdata[187],mux_wrdata[155],mux_wrdata[123],mux_wrdata[91],mux_wrdata[59],mux_wrdata[27],mux_wrdata[252],mux_wrdata[220],mux_wrdata[188],mux_wrdata[156],mux_wrdata[124],mux_wrdata[92],mux_wrdata[60],mux_wrdata[28],mux_wrdata[253],mux_wrdata[221],mux_wrdata[189],mux_wrdata[157],mux_wrdata[125],mux_wrdata[93],mux_wrdata[61],mux_wrdata[29],mux_wrdata[254],mux_wrdata[222],mux_wrdata[190],mux_wrdata[158],mux_wrdata[126],mux_wrdata[94],mux_wrdata[62],mux_wrdata[30],mux_wrdata[255],mux_wrdata[223],mux_wrdata[191],mux_wrdata[159],mux_wrdata[127],mux_wrdata[95],mux_wrdata[63],mux_wrdata[31]}),\n .phy_if_reset(phy_if_reset),\n .\\pi_dqs_found_lanes_r1_reg[0] (\\pi_dqs_found_lanes_r1_reg[3] [0]),\n .pi_en_stg2_f_reg(pi_en_stg2_f_reg),\n .pi_phase_locked_all_r1_reg(\\ddr_byte_lane_A.ddr_byte_lane_A_n_2 ),\n .pi_stg2_f_incdec_reg(pi_stg2_f_incdec_reg),\n .\\po_counter_read_val_reg[8] (A_po_counter_read_val),\n .\\po_stg2_wrcal_cnt_reg[1] (\\po_stg2_wrcal_cnt_reg[1] ),\n .\\rd_mux_sel_r_reg[1] (\\rd_mux_sel_r_reg[1] ),\n .\\read_fifo.fifo_out_data_r_reg[6] (\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .rst_r4(rst_r4),\n .sync_pulse(sync_pulse),\n .\\wr_ptr_reg[1] (\\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ),\n .\\write_buffer.wr_buf_out_data_reg[248] (\\write_buffer.wr_buf_out_data_reg[248] ),\n .\\write_buffer.wr_buf_out_data_reg[249] (\\write_buffer.wr_buf_out_data_reg[249] ),\n .\\write_buffer.wr_buf_out_data_reg[250] (\\write_buffer.wr_buf_out_data_reg[250] ),\n .\\write_buffer.wr_buf_out_data_reg[251] (\\write_buffer.wr_buf_out_data_reg[251] ),\n .\\write_buffer.wr_buf_out_data_reg[252] (\\write_buffer.wr_buf_out_data_reg[252] ),\n .\\write_buffer.wr_buf_out_data_reg[253] (\\write_buffer.wr_buf_out_data_reg[253] ),\n .\\write_buffer.wr_buf_out_data_reg[254] (\\write_buffer.wr_buf_out_data_reg[254] ),\n .\\write_buffer.wr_buf_out_data_reg[255] (\\write_buffer.wr_buf_out_data_reg[255] ),\n .\\write_buffer.wr_buf_out_data_reg[287] ({\\write_buffer.wr_buf_out_data_reg[287] [31],\\write_buffer.wr_buf_out_data_reg[287] [27],\\write_buffer.wr_buf_out_data_reg[287] [23],\\write_buffer.wr_buf_out_data_reg[287] [19],\\write_buffer.wr_buf_out_data_reg[287] [15],\\write_buffer.wr_buf_out_data_reg[287] [11],\\write_buffer.wr_buf_out_data_reg[287] [7],\\write_buffer.wr_buf_out_data_reg[287] [3]}));\n ddr3_ifmig_7series_v4_0_ddr_byte_lane__parameterized0 \\ddr_byte_lane_B.ddr_byte_lane_B \n (.A_byte_rd_en(A_byte_rd_en),\n .A_rst_primitives(A_rst_primitives),\n .A_rst_primitives_reg(\\ddr_byte_lane_C.ddr_byte_lane_C_n_2 ),\n .A_rst_primitives_reg_0(\\ddr_byte_lane_A.ddr_byte_lane_A_n_2 ),\n .A_rst_primitives_reg_1(\\ddr_byte_lane_D.ddr_byte_lane_D_n_2 ),\n .B_byte_rd_en(B_byte_rd_en),\n .B_rclk(B_rclk),\n .CLK(CLK),\n .CLKB0_7(CLKB0_7),\n .COUNTERREADVAL(B_pi_counter_read_val),\n .D_byte_rd_en(D_byte_rd_en),\n .LD0_3(LD0_3),\n .PCENABLECALIB(phy_encalib),\n .Q(\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_0 ),\n .\\calib_sel_reg[0] (\\calib_sel_reg[0]_0 ),\n .\\calib_sel_reg[0]_0 (\\calib_sel_reg[0]_2 ),\n .\\calib_zero_inputs_reg[0] (\\calib_zero_inputs_reg[0] ),\n .ck_po_stg2_f_en_reg(ck_po_stg2_f_en_reg_0),\n .ck_po_stg2_f_indec_reg(ck_po_stg2_f_indec_reg_0),\n .delay_done_r4_reg(delay_done_r4_reg_0),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),\n .freq_refclk(freq_refclk),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\gen_byte_sel_div1.calib_in_common_reg_3 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_0 (\\gen_byte_sel_div1.calib_in_common_reg_4 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_1 (\\gen_byte_sel_div1.calib_in_common_reg_5 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_2 (\\gen_byte_sel_div1.calib_in_common_reg_6 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_3 (\\gen_byte_sel_div1.calib_in_common_reg_15 ),\n .idelay_inc(idelay_inc),\n .idelay_ld_rst_0(idelay_ld_rst_0),\n .if_empty_r(if_empty_r_2),\n .if_empty_r_0(if_empty_r_5),\n .init_calib_complete_reg_rep(init_calib_complete_reg_rep),\n .mem_dq_in(mem_dq_in[15:8]),\n .mem_dq_out(mem_dq_out[17:9]),\n .mem_dq_ts(mem_dq_ts[17:9]),\n .mem_dqs_in(mem_dqs_in[1]),\n .mem_dqs_out(mem_dqs_out[1]),\n .mem_dqs_ts(mem_dqs_ts[1]),\n .mem_refclk(mem_refclk),\n .mux_rd_valid_r_reg(mux_rd_valid_r_reg),\n .mux_wrdata_en(mux_wrdata_en),\n .my_empty({\\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4 [3],\\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4 [0]}),\n .\\my_empty_reg[1] (\\my_empty_reg[1]_0 ),\n .\\my_empty_reg[4] (\\ddr_byte_lane_D.ddr_byte_lane_D_n_154 ),\n .\\my_empty_reg[7] (\\my_empty_reg[7]_0 ),\n .\\not_strict_mode.app_rd_data_reg[112] (\\not_strict_mode.app_rd_data_reg[112] ),\n .\\not_strict_mode.app_rd_data_reg[113] (\\not_strict_mode.app_rd_data_reg[113] ),\n .\\not_strict_mode.app_rd_data_reg[114] (\\not_strict_mode.app_rd_data_reg[114] ),\n .\\not_strict_mode.app_rd_data_reg[115] (\\not_strict_mode.app_rd_data_reg[115] ),\n .\\not_strict_mode.app_rd_data_reg[116] (\\not_strict_mode.app_rd_data_reg[116] ),\n .\\not_strict_mode.app_rd_data_reg[117] (\\not_strict_mode.app_rd_data_reg[117] ),\n .\\not_strict_mode.app_rd_data_reg[118] (\\not_strict_mode.app_rd_data_reg[118] ),\n .\\not_strict_mode.app_rd_data_reg[119] (\\not_strict_mode.app_rd_data_reg[119] ),\n .\\not_strict_mode.app_rd_data_reg[144] (\\not_strict_mode.app_rd_data_reg[144] ),\n .\\not_strict_mode.app_rd_data_reg[145] (\\not_strict_mode.app_rd_data_reg[145] ),\n .\\not_strict_mode.app_rd_data_reg[146] (\\not_strict_mode.app_rd_data_reg[146] ),\n .\\not_strict_mode.app_rd_data_reg[147] (\\not_strict_mode.app_rd_data_reg[147] ),\n .\\not_strict_mode.app_rd_data_reg[148] (\\not_strict_mode.app_rd_data_reg[148] ),\n .\\not_strict_mode.app_rd_data_reg[149] (\\not_strict_mode.app_rd_data_reg[149] ),\n .\\not_strict_mode.app_rd_data_reg[150] (\\not_strict_mode.app_rd_data_reg[150] ),\n .\\not_strict_mode.app_rd_data_reg[151] (\\not_strict_mode.app_rd_data_reg[151] ),\n .\\not_strict_mode.app_rd_data_reg[16] (\\not_strict_mode.app_rd_data_reg[16] ),\n .\\not_strict_mode.app_rd_data_reg[176] (\\not_strict_mode.app_rd_data_reg[176] ),\n .\\not_strict_mode.app_rd_data_reg[177] (\\not_strict_mode.app_rd_data_reg[177] ),\n .\\not_strict_mode.app_rd_data_reg[178] (\\not_strict_mode.app_rd_data_reg[178] ),\n .\\not_strict_mode.app_rd_data_reg[179] (\\not_strict_mode.app_rd_data_reg[179] ),\n .\\not_strict_mode.app_rd_data_reg[17] (\\not_strict_mode.app_rd_data_reg[17] ),\n .\\not_strict_mode.app_rd_data_reg[180] (\\not_strict_mode.app_rd_data_reg[180] ),\n .\\not_strict_mode.app_rd_data_reg[181] (\\not_strict_mode.app_rd_data_reg[181] ),\n .\\not_strict_mode.app_rd_data_reg[182] (\\not_strict_mode.app_rd_data_reg[182] ),\n .\\not_strict_mode.app_rd_data_reg[183] (\\not_strict_mode.app_rd_data_reg[183] ),\n .\\not_strict_mode.app_rd_data_reg[18] (\\not_strict_mode.app_rd_data_reg[18] ),\n .\\not_strict_mode.app_rd_data_reg[19] (\\not_strict_mode.app_rd_data_reg[19] ),\n .\\not_strict_mode.app_rd_data_reg[208] (\\not_strict_mode.app_rd_data_reg[208] ),\n .\\not_strict_mode.app_rd_data_reg[209] (\\not_strict_mode.app_rd_data_reg[209] ),\n .\\not_strict_mode.app_rd_data_reg[20] (\\not_strict_mode.app_rd_data_reg[20] ),\n .\\not_strict_mode.app_rd_data_reg[210] (\\not_strict_mode.app_rd_data_reg[210] ),\n .\\not_strict_mode.app_rd_data_reg[211] (\\not_strict_mode.app_rd_data_reg[211] ),\n .\\not_strict_mode.app_rd_data_reg[212] (\\not_strict_mode.app_rd_data_reg[212] ),\n .\\not_strict_mode.app_rd_data_reg[213] (\\not_strict_mode.app_rd_data_reg[213] ),\n .\\not_strict_mode.app_rd_data_reg[214] (\\not_strict_mode.app_rd_data_reg[214] ),\n .\\not_strict_mode.app_rd_data_reg[215] (\\not_strict_mode.app_rd_data_reg[215] ),\n .\\not_strict_mode.app_rd_data_reg[21] (\\not_strict_mode.app_rd_data_reg[21] ),\n .\\not_strict_mode.app_rd_data_reg[22] (\\not_strict_mode.app_rd_data_reg[22] ),\n .\\not_strict_mode.app_rd_data_reg[23] (\\not_strict_mode.app_rd_data_reg[23] ),\n .\\not_strict_mode.app_rd_data_reg[23]_0 (\\not_strict_mode.app_rd_data_reg[23]_0 ),\n .\\not_strict_mode.app_rd_data_reg[23]_1 (\\not_strict_mode.app_rd_data_reg[23]_1 ),\n .\\not_strict_mode.app_rd_data_reg[240] (\\not_strict_mode.app_rd_data_reg[240] ),\n .\\not_strict_mode.app_rd_data_reg[241] (\\not_strict_mode.app_rd_data_reg[241] ),\n .\\not_strict_mode.app_rd_data_reg[242] (\\not_strict_mode.app_rd_data_reg[242] ),\n .\\not_strict_mode.app_rd_data_reg[243] (\\not_strict_mode.app_rd_data_reg[243] ),\n .\\not_strict_mode.app_rd_data_reg[244] (\\not_strict_mode.app_rd_data_reg[244] ),\n .\\not_strict_mode.app_rd_data_reg[244]_0 (\\not_strict_mode.app_rd_data_reg[244]_0 ),\n .\\not_strict_mode.app_rd_data_reg[245] (\\not_strict_mode.app_rd_data_reg[245] ),\n .\\not_strict_mode.app_rd_data_reg[246] (\\not_strict_mode.app_rd_data_reg[246] ),\n .\\not_strict_mode.app_rd_data_reg[247] ({\\not_strict_mode.app_rd_data_reg[255]_0 [247:240],\\not_strict_mode.app_rd_data_reg[255]_0 [215:208],\\not_strict_mode.app_rd_data_reg[255]_0 [183:176],\\not_strict_mode.app_rd_data_reg[255]_0 [151:144],\\not_strict_mode.app_rd_data_reg[255]_0 [119:112],\\not_strict_mode.app_rd_data_reg[255]_0 [87:80],\\not_strict_mode.app_rd_data_reg[255]_0 [55:48],\\not_strict_mode.app_rd_data_reg[255]_0 [23:16]}),\n .\\not_strict_mode.app_rd_data_reg[247]_0 (\\not_strict_mode.app_rd_data_reg[247] ),\n .\\not_strict_mode.app_rd_data_reg[48] (\\not_strict_mode.app_rd_data_reg[48] ),\n .\\not_strict_mode.app_rd_data_reg[49] (\\not_strict_mode.app_rd_data_reg[49] ),\n .\\not_strict_mode.app_rd_data_reg[50] (\\not_strict_mode.app_rd_data_reg[50] ),\n .\\not_strict_mode.app_rd_data_reg[51] (\\not_strict_mode.app_rd_data_reg[51] ),\n .\\not_strict_mode.app_rd_data_reg[52] (\\not_strict_mode.app_rd_data_reg[52] ),\n .\\not_strict_mode.app_rd_data_reg[53] (\\not_strict_mode.app_rd_data_reg[53] ),\n .\\not_strict_mode.app_rd_data_reg[54] (\\not_strict_mode.app_rd_data_reg[54] ),\n .\\not_strict_mode.app_rd_data_reg[55] (\\not_strict_mode.app_rd_data_reg[55] ),\n .\\not_strict_mode.app_rd_data_reg[80] (\\not_strict_mode.app_rd_data_reg[80] ),\n .\\not_strict_mode.app_rd_data_reg[81] (\\not_strict_mode.app_rd_data_reg[81] ),\n .\\not_strict_mode.app_rd_data_reg[82] (\\not_strict_mode.app_rd_data_reg[82] ),\n .\\not_strict_mode.app_rd_data_reg[83] (\\not_strict_mode.app_rd_data_reg[83] ),\n .\\not_strict_mode.app_rd_data_reg[84] (\\not_strict_mode.app_rd_data_reg[84] ),\n .\\not_strict_mode.app_rd_data_reg[85] (\\not_strict_mode.app_rd_data_reg[85] ),\n .\\not_strict_mode.app_rd_data_reg[86] (\\not_strict_mode.app_rd_data_reg[86] ),\n .\\not_strict_mode.app_rd_data_reg[87] (\\not_strict_mode.app_rd_data_reg[87] ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ),\n .\\not_strict_mode.status_ram.rd_buf_we_r1_reg (\\not_strict_mode.status_ram.rd_buf_we_r1_reg ),\n .out(out),\n .phaser_ctl_bus({phaser_ctl_bus[11:10],phaser_ctl_bus[5],phaser_ctl_bus[1]}),\n .phy_dout({mux_wrdata_mask[30],mux_wrdata_mask[26],mux_wrdata_mask[22],mux_wrdata_mask[18],mux_wrdata_mask[14],mux_wrdata_mask[10],mux_wrdata_mask[6],mux_wrdata_mask[2],mux_wrdata[240],mux_wrdata[208],mux_wrdata[176],mux_wrdata[144],mux_wrdata[112],mux_wrdata[80],mux_wrdata[48],mux_wrdata[16],mux_wrdata[241],mux_wrdata[209],mux_wrdata[177],mux_wrdata[145],mux_wrdata[113],mux_wrdata[81],mux_wrdata[49],mux_wrdata[17],mux_wrdata[242],mux_wrdata[210],mux_wrdata[178],mux_wrdata[146],mux_wrdata[114],mux_wrdata[82],mux_wrdata[50],mux_wrdata[18],mux_wrdata[243],mux_wrdata[211],mux_wrdata[179],mux_wrdata[147],mux_wrdata[115],mux_wrdata[83],mux_wrdata[51],mux_wrdata[19],mux_wrdata[244],mux_wrdata[212],mux_wrdata[180],mux_wrdata[148],mux_wrdata[116],mux_wrdata[84],mux_wrdata[52],mux_wrdata[20],mux_wrdata[245],mux_wrdata[213],mux_wrdata[181],mux_wrdata[149],mux_wrdata[117],mux_wrdata[85],mux_wrdata[53],mux_wrdata[21],mux_wrdata[246],mux_wrdata[214],mux_wrdata[182],mux_wrdata[150],mux_wrdata[118],mux_wrdata[86],mux_wrdata[54],mux_wrdata[22],mux_wrdata[247],mux_wrdata[215],mux_wrdata[183],mux_wrdata[151],mux_wrdata[119],mux_wrdata[87],mux_wrdata[55],mux_wrdata[23]}),\n .phy_if_empty_r_reg(phy_if_empty_r_reg),\n .phy_if_reset(phy_if_reset),\n .phy_rddata_en(phy_rddata_en),\n .\\pi_dqs_found_lanes_r1_reg[1] (\\pi_dqs_found_lanes_r1_reg[3] [1]),\n .pi_en_stg2_f_reg(pi_en_stg2_f_reg_0),\n .pi_phase_locked_all_r1_reg(pi_phase_locked_all_r1_reg),\n .pi_stg2_f_incdec_reg(pi_stg2_f_incdec_reg_0),\n .\\po_counter_read_val_reg[8] (B_po_counter_read_val),\n .prbs_rdlvl_start_reg(prbs_rdlvl_start_reg),\n .ram_init_done_r(ram_init_done_r),\n .rd_buf_we(rd_buf_we),\n .\\rd_ptr_timing_reg[1] (\\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1 ),\n .\\read_fifo.fifo_out_data_r_reg[6] (\\read_fifo.fifo_out_data_r_reg[6] ),\n .\\read_fifo.fifo_out_data_r_reg[6]_0 (\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .\\read_fifo.tail_r_reg[0] (\\read_fifo.tail_r_reg[0] ),\n .rst_r4(rst_r4),\n .sync_pulse(sync_pulse),\n .tail_r(tail_r),\n .\\write_buffer.wr_buf_out_data_reg[240] (\\write_buffer.wr_buf_out_data_reg[240] ),\n .\\write_buffer.wr_buf_out_data_reg[241] (\\write_buffer.wr_buf_out_data_reg[241] ),\n .\\write_buffer.wr_buf_out_data_reg[242] (\\write_buffer.wr_buf_out_data_reg[242] ),\n .\\write_buffer.wr_buf_out_data_reg[243] (\\write_buffer.wr_buf_out_data_reg[243] ),\n .\\write_buffer.wr_buf_out_data_reg[244] (\\write_buffer.wr_buf_out_data_reg[244] ),\n .\\write_buffer.wr_buf_out_data_reg[245] (\\write_buffer.wr_buf_out_data_reg[245] ),\n .\\write_buffer.wr_buf_out_data_reg[246] (\\write_buffer.wr_buf_out_data_reg[246] ),\n .\\write_buffer.wr_buf_out_data_reg[247] (\\write_buffer.wr_buf_out_data_reg[247] ),\n .\\write_buffer.wr_buf_out_data_reg[286] ({\\write_buffer.wr_buf_out_data_reg[287] [30],\\write_buffer.wr_buf_out_data_reg[287] [26],\\write_buffer.wr_buf_out_data_reg[287] [22],\\write_buffer.wr_buf_out_data_reg[287] [18],\\write_buffer.wr_buf_out_data_reg[287] [14],\\write_buffer.wr_buf_out_data_reg[287] [10],\\write_buffer.wr_buf_out_data_reg[287] [6],\\write_buffer.wr_buf_out_data_reg[287] [2]}));\n ddr3_ifmig_7series_v4_0_ddr_byte_lane__parameterized1 \\ddr_byte_lane_C.ddr_byte_lane_C \n (.A_byte_rd_en(A_byte_rd_en),\n .A_rst_primitives(A_rst_primitives),\n .CLK(CLK),\n .CLKB0_8(CLKB0_8),\n .COUNTERREADVAL(C_pi_counter_read_val),\n .C_byte_rd_en(C_byte_rd_en),\n .D_byte_rd_en(D_byte_rd_en),\n .LD0_4(LD0_4),\n .PCENABLECALIB(phy_encalib),\n .Q(\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_3 ),\n .\\calib_sel_reg[1] (\\calib_sel_reg[1] ),\n .\\calib_sel_reg[1]_0 (\\calib_sel_reg[1]_0 ),\n .\\calib_zero_inputs_reg[0] (\\calib_zero_inputs_reg[0]_0 ),\n .ck_po_stg2_f_en_reg(ck_po_stg2_f_en_reg_1),\n .ck_po_stg2_f_indec_reg(ck_po_stg2_f_indec_reg_1),\n .delay_done_r4_reg(delay_done_r4_reg_1),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),\n .freq_refclk(freq_refclk),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\gen_byte_sel_div1.calib_in_common_reg_7 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_0 (\\gen_byte_sel_div1.calib_in_common_reg_8 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_1 (\\gen_byte_sel_div1.calib_in_common_reg_9 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_2 (\\gen_byte_sel_div1.calib_in_common_reg_10 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_3 (\\gen_byte_sel_div1.calib_in_common_reg_16 ),\n .idelay_inc(idelay_inc),\n .idelay_ld_rst_1(idelay_ld_rst_1),\n .if_empty_r(if_empty_r_5),\n .if_empty_r_0(if_empty_r_2),\n .init_calib_complete_reg_rep(init_calib_complete_reg_rep),\n .mem_dq_in(mem_dq_in[23:16]),\n .mem_dq_out(mem_dq_out[26:18]),\n .mem_dq_ts(mem_dq_ts[26:18]),\n .mem_dqs_in(mem_dqs_in[2]),\n .mem_dqs_out(mem_dqs_out[2]),\n .mem_dqs_ts(mem_dqs_ts[2]),\n .mem_refclk(mem_refclk),\n .mux_wrdata_en(mux_wrdata_en),\n .\\my_empty_reg[1] (\\my_empty_reg[1]_1 ),\n .\\my_empty_reg[4] (\\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1 ),\n .\\my_empty_reg[7] (\\my_empty_reg[7]_1 ),\n .\\not_strict_mode.app_rd_data_reg[104] (\\not_strict_mode.app_rd_data_reg[104] ),\n .\\not_strict_mode.app_rd_data_reg[105] (\\not_strict_mode.app_rd_data_reg[105] ),\n .\\not_strict_mode.app_rd_data_reg[106] (\\not_strict_mode.app_rd_data_reg[106] ),\n .\\not_strict_mode.app_rd_data_reg[107] (\\not_strict_mode.app_rd_data_reg[107] ),\n .\\not_strict_mode.app_rd_data_reg[108] (\\not_strict_mode.app_rd_data_reg[108] ),\n .\\not_strict_mode.app_rd_data_reg[109] (\\not_strict_mode.app_rd_data_reg[109] ),\n .\\not_strict_mode.app_rd_data_reg[10] (\\not_strict_mode.app_rd_data_reg[10] ),\n .\\not_strict_mode.app_rd_data_reg[110] (\\not_strict_mode.app_rd_data_reg[110] ),\n .\\not_strict_mode.app_rd_data_reg[111] (\\not_strict_mode.app_rd_data_reg[111] ),\n .\\not_strict_mode.app_rd_data_reg[11] (\\not_strict_mode.app_rd_data_reg[11] ),\n .\\not_strict_mode.app_rd_data_reg[12] (\\not_strict_mode.app_rd_data_reg[12] ),\n .\\not_strict_mode.app_rd_data_reg[136] (\\not_strict_mode.app_rd_data_reg[136] ),\n .\\not_strict_mode.app_rd_data_reg[137] (\\not_strict_mode.app_rd_data_reg[137] ),\n .\\not_strict_mode.app_rd_data_reg[138] (\\not_strict_mode.app_rd_data_reg[138] ),\n .\\not_strict_mode.app_rd_data_reg[139] (\\not_strict_mode.app_rd_data_reg[139] ),\n .\\not_strict_mode.app_rd_data_reg[13] (\\not_strict_mode.app_rd_data_reg[13] ),\n .\\not_strict_mode.app_rd_data_reg[140] (\\not_strict_mode.app_rd_data_reg[140] ),\n .\\not_strict_mode.app_rd_data_reg[141] (\\not_strict_mode.app_rd_data_reg[141] ),\n .\\not_strict_mode.app_rd_data_reg[142] (\\not_strict_mode.app_rd_data_reg[142] ),\n .\\not_strict_mode.app_rd_data_reg[143] (\\not_strict_mode.app_rd_data_reg[143] ),\n .\\not_strict_mode.app_rd_data_reg[14] (\\not_strict_mode.app_rd_data_reg[14] ),\n .\\not_strict_mode.app_rd_data_reg[15] (\\not_strict_mode.app_rd_data_reg[15] ),\n .\\not_strict_mode.app_rd_data_reg[15]_0 (\\not_strict_mode.app_rd_data_reg[15]_0 ),\n .\\not_strict_mode.app_rd_data_reg[15]_1 (\\not_strict_mode.app_rd_data_reg[15]_1 ),\n .\\not_strict_mode.app_rd_data_reg[168] (\\not_strict_mode.app_rd_data_reg[168] ),\n .\\not_strict_mode.app_rd_data_reg[169] (\\not_strict_mode.app_rd_data_reg[169] ),\n .\\not_strict_mode.app_rd_data_reg[170] (\\not_strict_mode.app_rd_data_reg[170] ),\n .\\not_strict_mode.app_rd_data_reg[171] (\\not_strict_mode.app_rd_data_reg[171] ),\n .\\not_strict_mode.app_rd_data_reg[172] (\\not_strict_mode.app_rd_data_reg[172] ),\n .\\not_strict_mode.app_rd_data_reg[173] (\\not_strict_mode.app_rd_data_reg[173] ),\n .\\not_strict_mode.app_rd_data_reg[174] (\\not_strict_mode.app_rd_data_reg[174] ),\n .\\not_strict_mode.app_rd_data_reg[175] (\\not_strict_mode.app_rd_data_reg[175] ),\n .\\not_strict_mode.app_rd_data_reg[200] (\\not_strict_mode.app_rd_data_reg[200] ),\n .\\not_strict_mode.app_rd_data_reg[201] (\\not_strict_mode.app_rd_data_reg[201] ),\n .\\not_strict_mode.app_rd_data_reg[202] (\\not_strict_mode.app_rd_data_reg[202] ),\n .\\not_strict_mode.app_rd_data_reg[203] (\\not_strict_mode.app_rd_data_reg[203] ),\n .\\not_strict_mode.app_rd_data_reg[204] (\\not_strict_mode.app_rd_data_reg[204] ),\n .\\not_strict_mode.app_rd_data_reg[205] (\\not_strict_mode.app_rd_data_reg[205] ),\n .\\not_strict_mode.app_rd_data_reg[206] (\\not_strict_mode.app_rd_data_reg[206] ),\n .\\not_strict_mode.app_rd_data_reg[207] (\\not_strict_mode.app_rd_data_reg[207] ),\n .\\not_strict_mode.app_rd_data_reg[232] (\\not_strict_mode.app_rd_data_reg[232] ),\n .\\not_strict_mode.app_rd_data_reg[233] (\\not_strict_mode.app_rd_data_reg[233] ),\n .\\not_strict_mode.app_rd_data_reg[234] (\\not_strict_mode.app_rd_data_reg[234] ),\n .\\not_strict_mode.app_rd_data_reg[235] (\\not_strict_mode.app_rd_data_reg[235] ),\n .\\not_strict_mode.app_rd_data_reg[236] (\\not_strict_mode.app_rd_data_reg[236] ),\n .\\not_strict_mode.app_rd_data_reg[236]_0 (\\not_strict_mode.app_rd_data_reg[236]_0 ),\n .\\not_strict_mode.app_rd_data_reg[237] (\\not_strict_mode.app_rd_data_reg[237] ),\n .\\not_strict_mode.app_rd_data_reg[238] (\\not_strict_mode.app_rd_data_reg[238] ),\n .\\not_strict_mode.app_rd_data_reg[239] ({\\not_strict_mode.app_rd_data_reg[255]_0 [239:232],\\not_strict_mode.app_rd_data_reg[255]_0 [207:200],\\not_strict_mode.app_rd_data_reg[255]_0 [175:168],\\not_strict_mode.app_rd_data_reg[255]_0 [143:136],\\not_strict_mode.app_rd_data_reg[255]_0 [111:104],\\not_strict_mode.app_rd_data_reg[255]_0 [79:72],\\not_strict_mode.app_rd_data_reg[255]_0 [47:40],\\not_strict_mode.app_rd_data_reg[255]_0 [15:8]}),\n .\\not_strict_mode.app_rd_data_reg[239]_0 (\\not_strict_mode.app_rd_data_reg[239] ),\n .\\not_strict_mode.app_rd_data_reg[40] (\\not_strict_mode.app_rd_data_reg[40] ),\n .\\not_strict_mode.app_rd_data_reg[41] (\\not_strict_mode.app_rd_data_reg[41] ),\n .\\not_strict_mode.app_rd_data_reg[42] (\\not_strict_mode.app_rd_data_reg[42] ),\n .\\not_strict_mode.app_rd_data_reg[43] (\\not_strict_mode.app_rd_data_reg[43] ),\n .\\not_strict_mode.app_rd_data_reg[44] (\\not_strict_mode.app_rd_data_reg[44] ),\n .\\not_strict_mode.app_rd_data_reg[45] (\\not_strict_mode.app_rd_data_reg[45] ),\n .\\not_strict_mode.app_rd_data_reg[46] (\\not_strict_mode.app_rd_data_reg[46] ),\n .\\not_strict_mode.app_rd_data_reg[47] (\\not_strict_mode.app_rd_data_reg[47] ),\n .\\not_strict_mode.app_rd_data_reg[72] (\\not_strict_mode.app_rd_data_reg[72] ),\n .\\not_strict_mode.app_rd_data_reg[73] (\\not_strict_mode.app_rd_data_reg[73] ),\n .\\not_strict_mode.app_rd_data_reg[74] (\\not_strict_mode.app_rd_data_reg[74] ),\n .\\not_strict_mode.app_rd_data_reg[75] (\\not_strict_mode.app_rd_data_reg[75] ),\n .\\not_strict_mode.app_rd_data_reg[76] (\\not_strict_mode.app_rd_data_reg[76] ),\n .\\not_strict_mode.app_rd_data_reg[77] (\\not_strict_mode.app_rd_data_reg[77] ),\n .\\not_strict_mode.app_rd_data_reg[78] (\\not_strict_mode.app_rd_data_reg[78] ),\n .\\not_strict_mode.app_rd_data_reg[79] (\\not_strict_mode.app_rd_data_reg[79] ),\n .\\not_strict_mode.app_rd_data_reg[8] (\\not_strict_mode.app_rd_data_reg[8] ),\n .\\not_strict_mode.app_rd_data_reg[9] (\\not_strict_mode.app_rd_data_reg[9] ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ),\n .phaser_ctl_bus({phaser_ctl_bus[13:12],phaser_ctl_bus[6],phaser_ctl_bus[2]}),\n .phy_dout({mux_wrdata_mask[29],mux_wrdata_mask[25],mux_wrdata_mask[21],mux_wrdata_mask[17],mux_wrdata_mask[13],mux_wrdata_mask[9],mux_wrdata_mask[5],mux_wrdata_mask[1],mux_wrdata[232],mux_wrdata[200],mux_wrdata[168],mux_wrdata[136],mux_wrdata[104],mux_wrdata[72],mux_wrdata[40],mux_wrdata[8],mux_wrdata[233],mux_wrdata[201],mux_wrdata[169],mux_wrdata[137],mux_wrdata[105],mux_wrdata[73],mux_wrdata[41],mux_wrdata[9],mux_wrdata[234],mux_wrdata[202],mux_wrdata[170],mux_wrdata[138],mux_wrdata[106],mux_wrdata[74],mux_wrdata[42],mux_wrdata[10],mux_wrdata[235],mux_wrdata[203],mux_wrdata[171],mux_wrdata[139],mux_wrdata[107],mux_wrdata[75],mux_wrdata[43],mux_wrdata[11],mux_wrdata[236],mux_wrdata[204],mux_wrdata[172],mux_wrdata[140],mux_wrdata[108],mux_wrdata[76],mux_wrdata[44],mux_wrdata[12],mux_wrdata[237],mux_wrdata[205],mux_wrdata[173],mux_wrdata[141],mux_wrdata[109],mux_wrdata[77],mux_wrdata[45],mux_wrdata[13],mux_wrdata[238],mux_wrdata[206],mux_wrdata[174],mux_wrdata[142],mux_wrdata[110],mux_wrdata[78],mux_wrdata[46],mux_wrdata[14],mux_wrdata[239],mux_wrdata[207],mux_wrdata[175],mux_wrdata[143],mux_wrdata[111],mux_wrdata[79],mux_wrdata[47],mux_wrdata[15]}),\n .phy_if_reset(phy_if_reset),\n .\\pi_dqs_found_lanes_r1_reg[2] (\\pi_dqs_found_lanes_r1_reg[3] [2]),\n .pi_en_stg2_f_reg(pi_en_stg2_f_reg_1),\n .pi_phase_locked_all_r1_reg(\\ddr_byte_lane_C.ddr_byte_lane_C_n_2 ),\n .pi_stg2_f_incdec_reg(pi_stg2_f_incdec_reg_1),\n .\\po_counter_read_val_reg[8] (C_po_counter_read_val),\n .\\rd_ptr_timing_reg[1] ({\\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4 [3],\\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4 [0]}),\n .\\read_fifo.fifo_out_data_r_reg[6] (\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .rst_r4(rst_r4),\n .sync_pulse(sync_pulse),\n .\\write_buffer.wr_buf_out_data_reg[232] (\\write_buffer.wr_buf_out_data_reg[232] ),\n .\\write_buffer.wr_buf_out_data_reg[233] (\\write_buffer.wr_buf_out_data_reg[233] ),\n .\\write_buffer.wr_buf_out_data_reg[234] (\\write_buffer.wr_buf_out_data_reg[234] ),\n .\\write_buffer.wr_buf_out_data_reg[235] (\\write_buffer.wr_buf_out_data_reg[235] ),\n .\\write_buffer.wr_buf_out_data_reg[236] (\\write_buffer.wr_buf_out_data_reg[236] ),\n .\\write_buffer.wr_buf_out_data_reg[237] (\\write_buffer.wr_buf_out_data_reg[237] ),\n .\\write_buffer.wr_buf_out_data_reg[238] (\\write_buffer.wr_buf_out_data_reg[238] ),\n .\\write_buffer.wr_buf_out_data_reg[239] (\\write_buffer.wr_buf_out_data_reg[239] ),\n .\\write_buffer.wr_buf_out_data_reg[285] ({\\write_buffer.wr_buf_out_data_reg[287] [29],\\write_buffer.wr_buf_out_data_reg[287] [25],\\write_buffer.wr_buf_out_data_reg[287] [21],\\write_buffer.wr_buf_out_data_reg[287] [17],\\write_buffer.wr_buf_out_data_reg[287] [13],\\write_buffer.wr_buf_out_data_reg[287] [9],\\write_buffer.wr_buf_out_data_reg[287] [5],\\write_buffer.wr_buf_out_data_reg[287] [1]}));\n ddr3_ifmig_7series_v4_0_ddr_byte_lane__parameterized2 \\ddr_byte_lane_D.ddr_byte_lane_D \n (.A_byte_rd_en(A_byte_rd_en),\n .A_rst_primitives(A_rst_primitives),\n .A_rst_primitives_reg(C_pi_counter_read_val),\n .A_rst_primitives_reg_0(A_pi_counter_read_val),\n .A_rst_primitives_reg_1(B_po_counter_read_val),\n .A_rst_primitives_reg_2(C_po_counter_read_val),\n .A_rst_primitives_reg_3(A_po_counter_read_val),\n .CLK(CLK),\n .CLKB0_9(CLKB0_9),\n .COUNTERREADVAL(B_pi_counter_read_val),\n .C_byte_rd_en(C_byte_rd_en),\n .D({\\ddr_byte_lane_D.ddr_byte_lane_D_n_222 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_223 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_224 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_225 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_226 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_227 }),\n .DOA(DOA),\n .DOB(DOB),\n .DOC(DOC),\n .D_byte_rd_en(D_byte_rd_en),\n .LD0_5(LD0_5),\n .PCENABLECALIB(phy_encalib),\n .Q(\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_6 ),\n .\\calib_sel_reg[0] (\\calib_sel_reg[0]_1 ),\n .\\calib_sel_reg[0]_0 (\\calib_sel_reg[0]_3 ),\n .\\calib_sel_reg[1] (\\calib_sel_reg[1]_1 ),\n .\\calib_zero_inputs_reg[0] (\\calib_zero_inputs_reg[0]_1 ),\n .ck_po_stg2_f_en_reg(ck_po_stg2_f_en_reg_2),\n .ck_po_stg2_f_indec_reg(ck_po_stg2_f_indec_reg_2),\n .delay_done_r4_reg(delay_done_r4_reg_2),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ),\n .freq_refclk(freq_refclk),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\gen_byte_sel_div1.calib_in_common_reg_11 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_0 (\\gen_byte_sel_div1.calib_in_common_reg_12 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_1 (\\gen_byte_sel_div1.calib_in_common_reg_13 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_2 (\\gen_byte_sel_div1.calib_in_common_reg_14 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_3 (\\gen_byte_sel_div1.calib_in_common_reg_17 ),\n .idelay_inc(idelay_inc),\n .idelay_ld_rst_2(idelay_ld_rst_2),\n .if_empty_r(if_empty_r),\n .if_empty_r_0(if_empty_r_2),\n .init_calib_complete_reg_rep(init_calib_complete_reg_rep),\n .mem_dq_in(mem_dq_in[31:24]),\n .mem_dq_out(mem_dq_out[35:27]),\n .mem_dq_ts(mem_dq_ts[35:27]),\n .mem_dqs_in(mem_dqs_in[3]),\n .mem_dqs_out(mem_dqs_out[3]),\n .mem_dqs_ts(mem_dqs_ts[3]),\n .mem_refclk(mem_refclk),\n .mux_rd_valid_r_reg(\\ddr_byte_lane_D.ddr_byte_lane_D_n_154 ),\n .mux_wrdata_en(mux_wrdata_en),\n .\\my_empty_reg[1] (\\my_empty_reg[1]_2 ),\n .\\my_empty_reg[4] (\\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ),\n .\\my_empty_reg[4]_0 (\\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1 ),\n .\\my_empty_reg[7] (\\my_empty_reg[7]_2 ),\n .\\not_strict_mode.app_rd_data_reg[0] (\\not_strict_mode.app_rd_data_reg[0] ),\n .\\not_strict_mode.app_rd_data_reg[100] (\\not_strict_mode.app_rd_data_reg[100] ),\n .\\not_strict_mode.app_rd_data_reg[101] (\\not_strict_mode.app_rd_data_reg[101] ),\n .\\not_strict_mode.app_rd_data_reg[102] (\\not_strict_mode.app_rd_data_reg[102] ),\n .\\not_strict_mode.app_rd_data_reg[103] (\\not_strict_mode.app_rd_data_reg[103] ),\n .\\not_strict_mode.app_rd_data_reg[128] (\\not_strict_mode.app_rd_data_reg[128] ),\n .\\not_strict_mode.app_rd_data_reg[129] (\\not_strict_mode.app_rd_data_reg[129] ),\n .\\not_strict_mode.app_rd_data_reg[130] (\\not_strict_mode.app_rd_data_reg[130] ),\n .\\not_strict_mode.app_rd_data_reg[131] (\\not_strict_mode.app_rd_data_reg[131] ),\n .\\not_strict_mode.app_rd_data_reg[132] (\\not_strict_mode.app_rd_data_reg[132] ),\n .\\not_strict_mode.app_rd_data_reg[133] (\\not_strict_mode.app_rd_data_reg[133] ),\n .\\not_strict_mode.app_rd_data_reg[134] (\\not_strict_mode.app_rd_data_reg[134] ),\n .\\not_strict_mode.app_rd_data_reg[135] (\\not_strict_mode.app_rd_data_reg[135] ),\n .\\not_strict_mode.app_rd_data_reg[160] (\\not_strict_mode.app_rd_data_reg[160] ),\n .\\not_strict_mode.app_rd_data_reg[161] (\\not_strict_mode.app_rd_data_reg[161] ),\n .\\not_strict_mode.app_rd_data_reg[162] (\\not_strict_mode.app_rd_data_reg[162] ),\n .\\not_strict_mode.app_rd_data_reg[163] (\\not_strict_mode.app_rd_data_reg[163] ),\n .\\not_strict_mode.app_rd_data_reg[164] (\\not_strict_mode.app_rd_data_reg[164] ),\n .\\not_strict_mode.app_rd_data_reg[165] (\\not_strict_mode.app_rd_data_reg[165] ),\n .\\not_strict_mode.app_rd_data_reg[166] (\\not_strict_mode.app_rd_data_reg[166] ),\n .\\not_strict_mode.app_rd_data_reg[167] (\\not_strict_mode.app_rd_data_reg[167] ),\n .\\not_strict_mode.app_rd_data_reg[192] (\\not_strict_mode.app_rd_data_reg[192] ),\n .\\not_strict_mode.app_rd_data_reg[193] (\\not_strict_mode.app_rd_data_reg[193] ),\n .\\not_strict_mode.app_rd_data_reg[194] (\\not_strict_mode.app_rd_data_reg[194] ),\n .\\not_strict_mode.app_rd_data_reg[195] (\\not_strict_mode.app_rd_data_reg[195] ),\n .\\not_strict_mode.app_rd_data_reg[196] (\\not_strict_mode.app_rd_data_reg[196] ),\n .\\not_strict_mode.app_rd_data_reg[197] (\\not_strict_mode.app_rd_data_reg[197] ),\n .\\not_strict_mode.app_rd_data_reg[198] (\\not_strict_mode.app_rd_data_reg[198] ),\n .\\not_strict_mode.app_rd_data_reg[199] (\\not_strict_mode.app_rd_data_reg[199] ),\n .\\not_strict_mode.app_rd_data_reg[1] (\\not_strict_mode.app_rd_data_reg[1] ),\n .\\not_strict_mode.app_rd_data_reg[224] (\\not_strict_mode.app_rd_data_reg[224] ),\n .\\not_strict_mode.app_rd_data_reg[225] (\\not_strict_mode.app_rd_data_reg[225] ),\n .\\not_strict_mode.app_rd_data_reg[226] (\\not_strict_mode.app_rd_data_reg[226] ),\n .\\not_strict_mode.app_rd_data_reg[227] (\\not_strict_mode.app_rd_data_reg[227] ),\n .\\not_strict_mode.app_rd_data_reg[228] (\\not_strict_mode.app_rd_data_reg[228] ),\n .\\not_strict_mode.app_rd_data_reg[228]_0 (\\not_strict_mode.app_rd_data_reg[228]_0 ),\n .\\not_strict_mode.app_rd_data_reg[229] (\\not_strict_mode.app_rd_data_reg[229] ),\n .\\not_strict_mode.app_rd_data_reg[230] (\\not_strict_mode.app_rd_data_reg[230] ),\n .\\not_strict_mode.app_rd_data_reg[231] ({\\not_strict_mode.app_rd_data_reg[255]_0 [231:224],\\not_strict_mode.app_rd_data_reg[255]_0 [199:192],\\not_strict_mode.app_rd_data_reg[255]_0 [167:160],\\not_strict_mode.app_rd_data_reg[255]_0 [135:128],\\not_strict_mode.app_rd_data_reg[255]_0 [103:96],\\not_strict_mode.app_rd_data_reg[255]_0 [71:64],\\not_strict_mode.app_rd_data_reg[255]_0 [39:32],\\not_strict_mode.app_rd_data_reg[255]_0 [7:0]}),\n .\\not_strict_mode.app_rd_data_reg[231]_0 (\\not_strict_mode.app_rd_data_reg[231] ),\n .\\not_strict_mode.app_rd_data_reg[2] (\\not_strict_mode.app_rd_data_reg[2] ),\n .\\not_strict_mode.app_rd_data_reg[32] (\\not_strict_mode.app_rd_data_reg[32] ),\n .\\not_strict_mode.app_rd_data_reg[33] (\\not_strict_mode.app_rd_data_reg[33] ),\n .\\not_strict_mode.app_rd_data_reg[34] (\\not_strict_mode.app_rd_data_reg[34] ),\n .\\not_strict_mode.app_rd_data_reg[35] (\\not_strict_mode.app_rd_data_reg[35] ),\n .\\not_strict_mode.app_rd_data_reg[36] (\\not_strict_mode.app_rd_data_reg[36] ),\n .\\not_strict_mode.app_rd_data_reg[37] (\\not_strict_mode.app_rd_data_reg[37] ),\n .\\not_strict_mode.app_rd_data_reg[38] (\\not_strict_mode.app_rd_data_reg[38] ),\n .\\not_strict_mode.app_rd_data_reg[39] (\\not_strict_mode.app_rd_data_reg[39] ),\n .\\not_strict_mode.app_rd_data_reg[3] (\\not_strict_mode.app_rd_data_reg[3] ),\n .\\not_strict_mode.app_rd_data_reg[4] (\\not_strict_mode.app_rd_data_reg[4] ),\n .\\not_strict_mode.app_rd_data_reg[5] (\\not_strict_mode.app_rd_data_reg[5] ),\n .\\not_strict_mode.app_rd_data_reg[64] (\\not_strict_mode.app_rd_data_reg[64] ),\n .\\not_strict_mode.app_rd_data_reg[65] (\\not_strict_mode.app_rd_data_reg[65] ),\n .\\not_strict_mode.app_rd_data_reg[66] (\\not_strict_mode.app_rd_data_reg[66] ),\n .\\not_strict_mode.app_rd_data_reg[67] (\\not_strict_mode.app_rd_data_reg[67] ),\n .\\not_strict_mode.app_rd_data_reg[68] (\\not_strict_mode.app_rd_data_reg[68] ),\n .\\not_strict_mode.app_rd_data_reg[69] (\\not_strict_mode.app_rd_data_reg[69] ),\n .\\not_strict_mode.app_rd_data_reg[6] (\\not_strict_mode.app_rd_data_reg[6] ),\n .\\not_strict_mode.app_rd_data_reg[70] (\\not_strict_mode.app_rd_data_reg[70] ),\n .\\not_strict_mode.app_rd_data_reg[71] (\\not_strict_mode.app_rd_data_reg[71] ),\n .\\not_strict_mode.app_rd_data_reg[7] (\\not_strict_mode.app_rd_data_reg[7] ),\n .\\not_strict_mode.app_rd_data_reg[7]_0 (\\not_strict_mode.app_rd_data_reg[7]_0 ),\n .\\not_strict_mode.app_rd_data_reg[7]_1 (\\not_strict_mode.app_rd_data_reg[7]_1 ),\n .\\not_strict_mode.app_rd_data_reg[96] (\\not_strict_mode.app_rd_data_reg[96] ),\n .\\not_strict_mode.app_rd_data_reg[97] (\\not_strict_mode.app_rd_data_reg[97] ),\n .\\not_strict_mode.app_rd_data_reg[98] (\\not_strict_mode.app_rd_data_reg[98] ),\n .\\not_strict_mode.app_rd_data_reg[99] (\\not_strict_mode.app_rd_data_reg[99] ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ),\n .phaser_ctl_bus({phaser_ctl_bus[15:14],phaser_ctl_bus[7],phaser_ctl_bus[3]}),\n .phy_dout({mux_wrdata_mask[28],mux_wrdata_mask[24],mux_wrdata_mask[20],mux_wrdata_mask[16],mux_wrdata_mask[12],mux_wrdata_mask[8],mux_wrdata_mask[4],mux_wrdata_mask[0],mux_wrdata[224],mux_wrdata[192],mux_wrdata[160],mux_wrdata[128],mux_wrdata[96],mux_wrdata[64],mux_wrdata[32],mux_wrdata[0],mux_wrdata[225],mux_wrdata[193],mux_wrdata[161],mux_wrdata[129],mux_wrdata[97],mux_wrdata[65],mux_wrdata[33],mux_wrdata[1],mux_wrdata[226],mux_wrdata[194],mux_wrdata[162],mux_wrdata[130],mux_wrdata[98],mux_wrdata[66],mux_wrdata[34],mux_wrdata[2],mux_wrdata[227],mux_wrdata[195],mux_wrdata[163],mux_wrdata[131],mux_wrdata[99],mux_wrdata[67],mux_wrdata[35],mux_wrdata[3],mux_wrdata[228],mux_wrdata[196],mux_wrdata[164],mux_wrdata[132],mux_wrdata[100],mux_wrdata[68],mux_wrdata[36],mux_wrdata[4],mux_wrdata[229],mux_wrdata[197],mux_wrdata[165],mux_wrdata[133],mux_wrdata[101],mux_wrdata[69],mux_wrdata[37],mux_wrdata[5],mux_wrdata[230],mux_wrdata[198],mux_wrdata[166],mux_wrdata[134],mux_wrdata[102],mux_wrdata[70],mux_wrdata[38],mux_wrdata[6],mux_wrdata[231],mux_wrdata[199],mux_wrdata[167],mux_wrdata[135],mux_wrdata[103],mux_wrdata[71],mux_wrdata[39],mux_wrdata[7]}),\n .phy_if_reset(phy_if_reset),\n .\\pi_dqs_found_lanes_r1_reg[3] (\\pi_dqs_found_lanes_r1_reg[3] [3]),\n .pi_en_stg2_f_reg(pi_en_stg2_f_reg_2),\n .pi_phase_locked_all_r1_reg(\\ddr_byte_lane_D.ddr_byte_lane_D_n_2 ),\n .pi_stg2_f_incdec_reg(pi_stg2_f_incdec_reg_2),\n .\\po_counter_read_val_reg[8] ({\\ddr_byte_lane_D.ddr_byte_lane_D_n_228 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_229 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_230 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_231 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_232 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_233 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_234 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_235 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_236 }),\n .\\read_fifo.fifo_out_data_r_reg[6] (\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .rst_r4(rst_r4),\n .sync_pulse(sync_pulse),\n .\\write_buffer.wr_buf_out_data_reg[224] (\\write_buffer.wr_buf_out_data_reg[224] ),\n .\\write_buffer.wr_buf_out_data_reg[225] (\\write_buffer.wr_buf_out_data_reg[225] ),\n .\\write_buffer.wr_buf_out_data_reg[226] (\\write_buffer.wr_buf_out_data_reg[226] ),\n .\\write_buffer.wr_buf_out_data_reg[227] (\\write_buffer.wr_buf_out_data_reg[227] ),\n .\\write_buffer.wr_buf_out_data_reg[228] (\\write_buffer.wr_buf_out_data_reg[228] ),\n .\\write_buffer.wr_buf_out_data_reg[229] (\\write_buffer.wr_buf_out_data_reg[229] ),\n .\\write_buffer.wr_buf_out_data_reg[230] (\\write_buffer.wr_buf_out_data_reg[230] ),\n .\\write_buffer.wr_buf_out_data_reg[231] (\\write_buffer.wr_buf_out_data_reg[231] ),\n .\\write_buffer.wr_buf_out_data_reg[284] ({\\write_buffer.wr_buf_out_data_reg[287] [28],\\write_buffer.wr_buf_out_data_reg[287] [24],\\write_buffer.wr_buf_out_data_reg[287] [20],\\write_buffer.wr_buf_out_data_reg[287] [16],\\write_buffer.wr_buf_out_data_reg[287] [12],\\write_buffer.wr_buf_out_data_reg[287] [8],\\write_buffer.wr_buf_out_data_reg[287] [4],\\write_buffer.wr_buf_out_data_reg[287] [0]}));\n LUT1 #(\n .INIT(2'h2)) \n i_0\n (.I0(1'b0),\n .O(A_pi_rst_div2));\n LUT1 #(\n .INIT(2'h2)) \n i_1\n (.I0(1'b0),\n .O(B_pi_rst_div2));\n LUT1 #(\n .INIT(2'h2)) \n i_2\n (.I0(1'b0),\n .O(C_pi_rst_div2));\n LUT1 #(\n .INIT(2'h2)) \n i_3\n (.I0(1'b0),\n .O(D_pi_rst_div2));\n LUT2 #(\n .INIT(4'h8)) \n \\mcGo_r_reg[13]_srl14___u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12_i_1 \n (.I0(mcGo_w),\n .I1(mcGo_w__0),\n .O(\\mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13 ));\n FDRE #(\n .INIT(1'b0)) \n mcGo_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mcGo_reg_0),\n .Q(mcGo_w),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n ofs_rdy_r_i_2\n (.I0(\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_3 [2]),\n .I1(\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_3 [4]),\n .I2(\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_3 [3]),\n .I3(\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_0 [2]),\n .I4(\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_0 [4]),\n .I5(\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_0 [3]),\n .O(ofs_rdy_r_reg_0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n ofs_rdy_r_i_3\n (.I0(\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_6 [2]),\n .I1(\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_6 [4]),\n .I2(\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_6 [3]),\n .I3(\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0 [2]),\n .I4(\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0 [4]),\n .I5(\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0 [3]),\n .O(ofs_rdy_r_reg));\n (* box_type = \"PRIMITIVE\" *) \n PHASER_REF #(\n .IS_PWRDWN_INVERTED(1'b0),\n .IS_RST_INVERTED(1'b0)) \n phaser_ref_i\n (.CLKIN(freq_refclk),\n .LOCKED(ref_dll_lock_w__0),\n .PWRDWN(1'b0),\n .RST(RST0));\n (* box_type = \"PRIMITIVE\" *) \n PHY_CONTROL #(\n .AO_TOGGLE(1),\n .AO_WRLVL_EN(4'b0000),\n .BURST_MODE(\"TRUE\"),\n .CLK_RATIO(4),\n .CMD_OFFSET(8),\n .CO_DURATION(1),\n .DATA_CTL_A_N(\"TRUE\"),\n .DATA_CTL_B_N(\"TRUE\"),\n .DATA_CTL_C_N(\"TRUE\"),\n .DATA_CTL_D_N(\"TRUE\"),\n .DISABLE_SEQ_MATCH(\"TRUE\"),\n .DI_DURATION(1),\n .DO_DURATION(1),\n .EVENTS_DELAY(18),\n .FOUR_WINDOW_CLOCKS(63),\n .MULTI_REGION(\"TRUE\"),\n .PHY_COUNT_ENABLE(\"FALSE\"),\n .RD_CMD_OFFSET_0(10),\n .RD_CMD_OFFSET_1(10),\n .RD_CMD_OFFSET_2(10),\n .RD_CMD_OFFSET_3(10),\n .RD_DURATION_0(6),\n .RD_DURATION_1(6),\n .RD_DURATION_2(6),\n .RD_DURATION_3(6),\n .SYNC_MODE(\"FALSE\"),\n .WR_CMD_OFFSET_0(8),\n .WR_CMD_OFFSET_1(8),\n .WR_CMD_OFFSET_2(8),\n .WR_CMD_OFFSET_3(8),\n .WR_DURATION_0(7),\n .WR_DURATION_1(7),\n .WR_DURATION_2(7),\n .WR_DURATION_3(7)) \n phy_control_i\n (.AUXOUTPUT({phy_control_i_n_14,phy_control_i_n_15,phy_control_i_n_16,phy_control_i_n_17}),\n .INBURSTPENDING(phaser_ctl_bus[7:4]),\n .INRANKA(phaser_ctl_bus[9:8]),\n .INRANKB(phaser_ctl_bus[11:10]),\n .INRANKC(phaser_ctl_bus[13:12]),\n .INRANKD(phaser_ctl_bus[15:14]),\n .MEMREFCLK(mem_refclk),\n .OUTBURSTPENDING(phaser_ctl_bus[3:0]),\n .PCENABLECALIB(phy_encalib),\n .PHYCLK(CLK),\n .PHYCTLALMOSTFULL(phy_control_i_n_0),\n .PHYCTLEMPTY(phy_control_i_n_1),\n .PHYCTLFULL(_phy_ctl_full_p__0),\n .PHYCTLMSTREMPTY(phy_ctl_mstr_empty),\n .PHYCTLREADY(rst_primitives_reg_0),\n .PHYCTLWD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,Q[10:3],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,Q[2:0]}),\n .PHYCTLWRENABLE(phy_ctl_wr_i2),\n .PLLLOCK(pll_locked),\n .READCALIBENABLE(phy_read_calib),\n .REFDLLLOCK(ref_dll_lock_w__0),\n .RESET(in0),\n .SYNCIN(sync_pulse),\n .WRITECALIBENABLE(phy_write_calib));\n FDRE #(\n .INIT(1'b0)) \n \\pi_counter_read_val_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_227 ),\n .Q(\\pi_rdval_cnt_reg[5] [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\pi_counter_read_val_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_226 ),\n .Q(\\pi_rdval_cnt_reg[5] [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\pi_counter_read_val_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_225 ),\n .Q(\\pi_rdval_cnt_reg[5] [2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\pi_counter_read_val_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_224 ),\n .Q(\\pi_rdval_cnt_reg[5] [3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\pi_counter_read_val_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_223 ),\n .Q(\\pi_rdval_cnt_reg[5] [4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\pi_counter_read_val_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_222 ),\n .Q(\\pi_rdval_cnt_reg[5] [5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\po_counter_read_val_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_236 ),\n .Q(\\po_rdval_cnt_reg[8] [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\po_counter_read_val_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_235 ),\n .Q(\\po_rdval_cnt_reg[8] [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\po_counter_read_val_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_234 ),\n .Q(\\po_rdval_cnt_reg[8] [2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\po_counter_read_val_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_233 ),\n .Q(\\po_rdval_cnt_reg[8] [3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\po_counter_read_val_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_232 ),\n .Q(\\po_rdval_cnt_reg[8] [4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\po_counter_read_val_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_231 ),\n .Q(\\po_rdval_cnt_reg[8] [5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\po_counter_read_val_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_230 ),\n .Q(\\po_rdval_cnt_reg[8] [6]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\po_counter_read_val_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_229 ),\n .Q(\\po_rdval_cnt_reg[8] [7]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\po_counter_read_val_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_228 ),\n .Q(\\po_rdval_cnt_reg[8] [8]),\n .R(1'b0));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rclk_delay_reg \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rclk_delay_reg[10]_srl11 \" *) \n SRL16E #(\n .INIT(16'h0000)) \n \\rclk_delay_reg[10]_srl11 \n (.A0(1'b0),\n .A1(1'b1),\n .A2(1'b0),\n .A3(1'b1),\n .CE(1'b1),\n .CLK(CLK),\n .D(rst_primitives_reg_1),\n .Q(\\rclk_delay_reg[10]_srl11_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rclk_delay_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rclk_delay_reg[10]_srl11_n_0 ),\n .Q(rclk_delay_11),\n .R(1'b0));\n FDCE #(\n .INIT(1'b0)) \n rst_out_reg\n (.C(CLK),\n .CE(1'b1),\n .CLR(rstdiv0_sync_r1_reg_rep__9),\n .D(\\rclk_delay_reg[11]_0 ),\n .Q(mcGo_reg_0));\n FDRE #(\n .INIT(1'b0)) \n rst_primitives_reg\n (.C(CLK),\n .CE(1'b1),\n .D(phy_ctl_wr_i2_reg),\n .Q(rst_primitives),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h7FFFFFFF)) \n \\rstdiv2_sync_r[11]_i_1 \n (.I0(ref_dll_lock_w__0),\n .I1(ref_dll_lock_w),\n .I2(sys_rst),\n .I3(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .I4(mmcm_locked),\n .O(rst_sync_r1_reg));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_phy_4lanes\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_phy_4lanes__parameterized0\n (\\rd_ptr_timing_reg[2] ,\n \\rd_ptr_timing_reg[2]_0 ,\n \\rd_ptr_timing_reg[2]_1 ,\n \\rd_ptr_timing_reg[2]_2 ,\n \\rd_ptr_timing_reg[2]_3 ,\n \\rd_ptr_timing_reg[2]_4 ,\n \\rd_ptr_timing_reg[2]_5 ,\n \\rd_ptr_timing_reg[2]_6 ,\n \\rd_ptr_timing_reg[2]_7 ,\n \\rd_ptr_timing_reg[2]_8 ,\n \\rd_ptr_timing_reg[2]_9 ,\n \\rd_ptr_timing_reg[2]_10 ,\n phy_ctl_mstr_empty,\n ref_dll_lock_w,\n mcGo_w__0,\n \\my_empty_reg[1] ,\n \\my_empty_reg[1]_0 ,\n phy_mc_ctl_full,\n \\my_empty_reg[1]_1 ,\n \\my_empty_reg[1]_2 ,\n \\byte_r_reg[0] ,\n \\po_counter_read_val_r_reg[5] ,\n of_ctl_full_v,\n wr_en,\n wr_en_5,\n wr_en_6,\n Q,\n \\wr_ptr_timing_reg[2] ,\n \\wr_ptr_timing_reg[2]_0 ,\n mem_dq_out,\n \\po_rdval_cnt_reg[8] ,\n ddr_ck_out,\n \\my_empty_reg[7] ,\n CLK,\n init_calib_complete_reg_rep__6,\n D5,\n D6,\n D2,\n D3,\n \\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ,\n \\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ,\n D7,\n D8,\n D9,\n D0,\n D1,\n \\calib_sel_reg[0] ,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n \\calib_sel_reg[0]_0 ,\n \\calib_sel_reg[0]_1 ,\n freq_refclk,\n mem_refclk,\n \\calib_sel_reg[0]_2 ,\n sync_pulse,\n \\calib_sel_reg[1] ,\n \\gen_byte_sel_div1.calib_in_common_reg_0 ,\n \\calib_sel_reg[1]_0 ,\n \\calib_sel_reg[1]_1 ,\n \\calib_sel_reg[1]_2 ,\n \\calib_sel_reg[1]_3 ,\n \\gen_byte_sel_div1.calib_in_common_reg_1 ,\n \\calib_sel_reg[1]_4 ,\n \\calib_sel_reg[1]_5 ,\n \\calib_sel_reg[1]_6 ,\n phy_ctl_wr_i2,\n pll_locked,\n phy_read_calib,\n in0,\n phy_write_calib,\n PHYCTLWD,\n RST0,\n rstdiv0_sync_r1_reg_rep__9,\n mux_cmd_wren,\n mem_out,\n \\rd_ptr_reg[3] ,\n _phy_ctl_full_p__0,\n \\rd_ptr_reg[3]_0 ,\n init_calib_complete_reg_rep__5,\n mc_cas_n,\n mc_address,\n init_calib_complete_reg_rep,\n \\calib_sel_reg[3] ,\n \\po_counter_read_val_reg[5]_0 ,\n D_po_coarse_enable110_out,\n D_po_counter_read_en122_out,\n D_po_fine_enable107_out,\n D_po_fine_inc113_out,\n D_po_sel_fine_oclk_delay125_out,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ,\n D4,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ,\n phy_dout,\n init_calib_complete_reg_rep__6_0);\n output \\rd_ptr_timing_reg[2] ;\n output \\rd_ptr_timing_reg[2]_0 ;\n output \\rd_ptr_timing_reg[2]_1 ;\n output \\rd_ptr_timing_reg[2]_2 ;\n output \\rd_ptr_timing_reg[2]_3 ;\n output \\rd_ptr_timing_reg[2]_4 ;\n output \\rd_ptr_timing_reg[2]_5 ;\n output \\rd_ptr_timing_reg[2]_6 ;\n output \\rd_ptr_timing_reg[2]_7 ;\n output \\rd_ptr_timing_reg[2]_8 ;\n output \\rd_ptr_timing_reg[2]_9 ;\n output \\rd_ptr_timing_reg[2]_10 ;\n output phy_ctl_mstr_empty;\n output [0:0]ref_dll_lock_w;\n output [0:0]mcGo_w__0;\n output \\my_empty_reg[1] ;\n output \\my_empty_reg[1]_0 ;\n output phy_mc_ctl_full;\n output \\my_empty_reg[1]_1 ;\n output \\my_empty_reg[1]_2 ;\n output \\byte_r_reg[0] ;\n output [5:0]\\po_counter_read_val_r_reg[5] ;\n output [0:0]of_ctl_full_v;\n output wr_en;\n output wr_en_5;\n output wr_en_6;\n output [3:0]Q;\n output [3:0]\\wr_ptr_timing_reg[2] ;\n output [3:0]\\wr_ptr_timing_reg[2]_0 ;\n output [23:0]mem_dq_out;\n output [4:0]\\po_rdval_cnt_reg[8] ;\n output [1:0]ddr_ck_out;\n output [31:0]\\my_empty_reg[7] ;\n input CLK;\n input [3:0]init_calib_complete_reg_rep__6;\n input [3:0]D5;\n input [3:0]D6;\n input [2:0]D2;\n input [2:0]D3;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ;\n input [7:0]\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ;\n input [7:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ;\n input [3:0]D7;\n input [3:0]D8;\n input [3:0]D9;\n input [2:0]D0;\n input [2:0]D1;\n input \\calib_sel_reg[0] ;\n input \\gen_byte_sel_div1.calib_in_common_reg ;\n input \\calib_sel_reg[0]_0 ;\n input \\calib_sel_reg[0]_1 ;\n input freq_refclk;\n input mem_refclk;\n input \\calib_sel_reg[0]_2 ;\n input sync_pulse;\n input \\calib_sel_reg[1] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n input \\calib_sel_reg[1]_0 ;\n input \\calib_sel_reg[1]_1 ;\n input \\calib_sel_reg[1]_2 ;\n input \\calib_sel_reg[1]_3 ;\n input \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n input \\calib_sel_reg[1]_4 ;\n input \\calib_sel_reg[1]_5 ;\n input \\calib_sel_reg[1]_6 ;\n input phy_ctl_wr_i2;\n input pll_locked;\n input phy_read_calib;\n input in0;\n input phy_write_calib;\n input [10:0]PHYCTLWD;\n input RST0;\n input rstdiv0_sync_r1_reg_rep__9;\n input mux_cmd_wren;\n input [11:0]mem_out;\n input [33:0]\\rd_ptr_reg[3] ;\n input [0:0]_phy_ctl_full_p__0;\n input [17:0]\\rd_ptr_reg[3]_0 ;\n input init_calib_complete_reg_rep__5;\n input [0:0]mc_cas_n;\n input [1:0]mc_address;\n input init_calib_complete_reg_rep;\n input [2:0]\\calib_sel_reg[3] ;\n input [5:0]\\po_counter_read_val_reg[5]_0 ;\n input D_po_coarse_enable110_out;\n input D_po_counter_read_en122_out;\n input D_po_fine_enable107_out;\n input D_po_fine_inc113_out;\n input D_po_sel_fine_oclk_delay125_out;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ;\n input [3:0]D4;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ;\n input [35:0]phy_dout;\n input init_calib_complete_reg_rep__6_0;\n\n wire A_of_full;\n (* async_reg = \"true\" *) wire A_pi_rst_div2;\n wire [8:0]A_po_counter_read_val;\n wire A_rst_primitives;\n (* async_reg = \"true\" *) wire B_pi_rst_div2;\n wire [8:0]B_po_counter_read_val;\n wire CLK;\n wire C_of_full;\n (* async_reg = \"true\" *) wire C_pi_rst_div2;\n wire [8:0]C_po_counter_read_val;\n wire [2:0]D0;\n wire [2:0]D1;\n wire [2:0]D2;\n wire [2:0]D3;\n wire [3:0]D4;\n wire [3:0]D5;\n wire [3:0]D6;\n wire [3:0]D7;\n wire [3:0]D8;\n wire [3:0]D9;\n wire D_of_full;\n (* async_reg = \"true\" *) wire D_pi_rst_div2;\n wire D_po_coarse_enable110_out;\n wire D_po_counter_read_en122_out;\n wire D_po_fine_enable107_out;\n wire D_po_fine_inc113_out;\n wire D_po_sel_fine_oclk_delay125_out;\n wire [10:0]PHYCTLWD;\n wire [3:0]Q;\n wire RST0;\n wire [1:1]_phy_ctl_full_p;\n wire [0:0]_phy_ctl_full_p__0;\n wire \\byte_r_reg[0] ;\n wire \\calib_sel_reg[0] ;\n wire \\calib_sel_reg[0]_0 ;\n wire \\calib_sel_reg[0]_1 ;\n wire \\calib_sel_reg[0]_2 ;\n wire \\calib_sel_reg[1] ;\n wire \\calib_sel_reg[1]_0 ;\n wire \\calib_sel_reg[1]_1 ;\n wire \\calib_sel_reg[1]_2 ;\n wire \\calib_sel_reg[1]_3 ;\n wire \\calib_sel_reg[1]_4 ;\n wire \\calib_sel_reg[1]_5 ;\n wire \\calib_sel_reg[1]_6 ;\n wire [2:0]\\calib_sel_reg[3] ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_1 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_2 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_3 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_4 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_5 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_6 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_7 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_8 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_9 ;\n wire [1:0]ddr_ck_out;\n wire freq_refclk;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n wire [7:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ;\n wire [7:0]\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ;\n wire in0;\n wire init_calib_complete_reg_rep;\n wire init_calib_complete_reg_rep__5;\n wire [3:0]init_calib_complete_reg_rep__6;\n wire init_calib_complete_reg_rep__6_0;\n wire [0:0]mcGo_w__0;\n wire [1:0]mc_address;\n wire [0:0]mc_cas_n;\n wire [23:0]mem_dq_out;\n wire [11:0]mem_out;\n wire mem_refclk;\n wire mux_cmd_wren;\n wire \\my_empty_reg[1] ;\n wire \\my_empty_reg[1]_0 ;\n wire \\my_empty_reg[1]_1 ;\n wire \\my_empty_reg[1]_2 ;\n wire [31:0]\\my_empty_reg[7] ;\n wire [0:0]of_ctl_full_v;\n wire ofifo_rst;\n wire [3:3]phaser_ctl_bus;\n wire phy_control_i_n_0;\n wire phy_control_i_n_10;\n wire phy_control_i_n_11;\n wire phy_control_i_n_14;\n wire phy_control_i_n_15;\n wire phy_control_i_n_16;\n wire phy_control_i_n_17;\n wire phy_control_i_n_18;\n wire phy_control_i_n_19;\n wire phy_control_i_n_20;\n wire phy_control_i_n_21;\n wire phy_control_i_n_23;\n wire phy_control_i_n_24;\n wire phy_control_i_n_25;\n wire phy_control_i_n_3;\n wire phy_control_i_n_4;\n wire phy_control_i_n_5;\n wire phy_control_i_n_6;\n wire phy_control_i_n_7;\n wire phy_control_i_n_8;\n wire phy_control_i_n_9;\n wire phy_ctl_mstr_empty;\n wire phy_ctl_wr_i2;\n wire [35:0]phy_dout;\n wire [1:0]phy_encalib;\n wire phy_mc_ctl_full;\n wire phy_read_calib;\n wire phy_write_calib;\n wire pll_locked;\n wire [5:0]\\po_counter_read_val_r_reg[5] ;\n wire [5:0]\\po_counter_read_val_reg[5]_0 ;\n wire [5:1]\\po_counter_read_val_w[1]_2 ;\n wire [4:0]\\po_rdval_cnt_reg[8] ;\n wire rclk_delay_11;\n wire \\rclk_delay_reg[10]_srl11_i_1__0_n_0 ;\n wire \\rclk_delay_reg[10]_srl11_n_0 ;\n wire [33:0]\\rd_ptr_reg[3] ;\n wire [17:0]\\rd_ptr_reg[3]_0 ;\n wire \\rd_ptr_timing_reg[2] ;\n wire \\rd_ptr_timing_reg[2]_0 ;\n wire \\rd_ptr_timing_reg[2]_1 ;\n wire \\rd_ptr_timing_reg[2]_10 ;\n wire \\rd_ptr_timing_reg[2]_2 ;\n wire \\rd_ptr_timing_reg[2]_3 ;\n wire \\rd_ptr_timing_reg[2]_4 ;\n wire \\rd_ptr_timing_reg[2]_5 ;\n wire \\rd_ptr_timing_reg[2]_6 ;\n wire \\rd_ptr_timing_reg[2]_7 ;\n wire \\rd_ptr_timing_reg[2]_8 ;\n wire \\rd_ptr_timing_reg[2]_9 ;\n wire [0:0]ref_dll_lock_w;\n wire rst_out_i_1__0_n_0;\n wire rst_out_reg_n_0;\n wire rst_primitives;\n wire rst_primitives_i_1__0_n_0;\n wire rstdiv0_sync_r1_reg_rep__9;\n wire sync_pulse;\n wire wr_en;\n wire wr_en_5;\n wire wr_en_6;\n wire [3:0]\\wr_ptr_timing_reg[2] ;\n wire [3:0]\\wr_ptr_timing_reg[2]_0 ;\n\n FDRE #(\n .INIT(1'b0)) \n A_rst_primitives_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rst_primitives),\n .Q(A_rst_primitives),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\byte_r[0]_i_3 \n (.I0(\\po_counter_read_val_r_reg[5] [2]),\n .I1(\\po_counter_read_val_r_reg[5] [5]),\n .I2(\\po_counter_read_val_r_reg[5] [0]),\n .I3(\\po_counter_read_val_r_reg[5] [3]),\n .I4(\\po_counter_read_val_r_reg[5] [1]),\n .I5(\\po_counter_read_val_r_reg[5] [4]),\n .O(\\byte_r_reg[0] ));\n ddr3_ifmig_7series_v4_0_ddr_byte_lane__parameterized3 \\ddr_byte_lane_A.ddr_byte_lane_A \n (.A_of_full(A_of_full),\n .A_rst_primitives(A_rst_primitives),\n .CLK(CLK),\n .COUNTERREADVAL(A_po_counter_read_val),\n .D0(D0),\n .D1(D1),\n .OUTBURSTPENDING(phy_control_i_n_25),\n .PCENABLECALIB(phy_encalib),\n .Q(\\wr_ptr_timing_reg[2]_0 ),\n .SR(ofifo_rst),\n .\\calib_sel_reg[1] (\\calib_sel_reg[1] ),\n .\\calib_sel_reg[1]_0 (\\calib_sel_reg[1]_0 ),\n .\\calib_sel_reg[1]_1 (\\calib_sel_reg[1]_1 ),\n .\\calib_sel_reg[1]_2 (\\calib_sel_reg[1]_2 ),\n .freq_refclk(freq_refclk),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .mem_dq_out(mem_dq_out[1:0]),\n .mem_out(mem_out),\n .mem_refclk(mem_refclk),\n .mux_cmd_wren(mux_cmd_wren),\n .\\my_empty_reg[1] (\\my_empty_reg[1] ),\n .\\rd_ptr_timing_reg[2] (\\rd_ptr_timing_reg[2]_7 ),\n .\\rd_ptr_timing_reg[2]_0 (\\rd_ptr_timing_reg[2]_8 ),\n .\\rd_ptr_timing_reg[2]_1 (\\rd_ptr_timing_reg[2]_9 ),\n .\\rd_ptr_timing_reg[2]_2 (\\rd_ptr_timing_reg[2]_10 ),\n .sync_pulse(sync_pulse),\n .wr_en(wr_en));\n ddr3_ifmig_7series_v4_0_ddr_byte_lane__parameterized4 \\ddr_byte_lane_B.ddr_byte_lane_B \n (.A_of_full(A_of_full),\n .A_rst_primitives(A_rst_primitives),\n .CLK(CLK),\n .COUNTERREADVAL(B_po_counter_read_val),\n .C_of_full(C_of_full),\n .D5(D5),\n .D6(D6),\n .D_of_full(D_of_full),\n .OUTBURSTPENDING(phy_control_i_n_24),\n .PCENABLECALIB(phy_encalib),\n .Q(Q),\n .SR(ofifo_rst),\n .\\calib_sel_reg[1] (\\calib_sel_reg[1]_3 ),\n .\\calib_sel_reg[1]_0 (\\calib_sel_reg[1]_4 ),\n .\\calib_sel_reg[1]_1 (\\calib_sel_reg[1]_5 ),\n .\\calib_sel_reg[1]_2 (\\calib_sel_reg[1]_6 ),\n .freq_refclk(freq_refclk),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6),\n .mem_dq_out(mem_dq_out[4:2]),\n .mem_refclk(mem_refclk),\n .mux_cmd_wren(mux_cmd_wren),\n .\\my_empty_reg[1] (\\my_empty_reg[1]_1 ),\n .of_ctl_full_v(of_ctl_full_v),\n .\\rd_ptr_reg[3] (\\rd_ptr_reg[3]_0 ),\n .\\rd_ptr_timing_reg[2] (\\rd_ptr_timing_reg[2] ),\n .\\rd_ptr_timing_reg[2]_0 (\\rd_ptr_timing_reg[2]_0 ),\n .\\rd_ptr_timing_reg[2]_1 (\\rd_ptr_timing_reg[2]_1 ),\n .\\rd_ptr_timing_reg[2]_2 (\\rd_ptr_timing_reg[2]_2 ),\n .sync_pulse(sync_pulse),\n .wr_en_5(wr_en_5));\n ddr3_ifmig_7series_v4_0_ddr_byte_lane__parameterized5 \\ddr_byte_lane_C.ddr_byte_lane_C \n (.A_rst_primitives(A_rst_primitives),\n .CLK(CLK),\n .COUNTERREADVAL(C_po_counter_read_val),\n .C_of_full(C_of_full),\n .D2(D2),\n .D3(D3),\n .D7(D7),\n .D8(D8),\n .D9(D9),\n .OUTBURSTPENDING(phy_control_i_n_23),\n .PCENABLECALIB(phy_encalib),\n .Q(\\wr_ptr_timing_reg[2] ),\n .SR(ofifo_rst),\n .\\calib_sel_reg[0] (\\calib_sel_reg[0] ),\n .\\calib_sel_reg[0]_0 (\\calib_sel_reg[0]_0 ),\n .\\calib_sel_reg[0]_1 (\\calib_sel_reg[0]_1 ),\n .\\calib_sel_reg[0]_2 (\\calib_sel_reg[0]_2 ),\n .freq_refclk(freq_refclk),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\gen_byte_sel_div1.calib_in_common_reg ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] (\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] (\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ),\n .mem_dq_out(mem_dq_out[14:5]),\n .mem_refclk(mem_refclk),\n .mux_cmd_wren(mux_cmd_wren),\n .\\my_empty_reg[1] (\\my_empty_reg[1]_0 ),\n .\\rd_ptr_reg[3] (\\rd_ptr_reg[3] ),\n .\\rd_ptr_timing_reg[2] (\\rd_ptr_timing_reg[2]_3 ),\n .\\rd_ptr_timing_reg[2]_0 (\\rd_ptr_timing_reg[2]_4 ),\n .\\rd_ptr_timing_reg[2]_1 (\\rd_ptr_timing_reg[2]_5 ),\n .\\rd_ptr_timing_reg[2]_2 (\\rd_ptr_timing_reg[2]_6 ),\n .sync_pulse(sync_pulse),\n .wr_en_6(wr_en_6));\n ddr3_ifmig_7series_v4_0_ddr_byte_lane__parameterized6 \\ddr_byte_lane_D.ddr_byte_lane_D \n (.A_rst_primitives(A_rst_primitives),\n .A_rst_primitives_reg(C_po_counter_read_val),\n .A_rst_primitives_reg_0(A_po_counter_read_val),\n .CLK(CLK),\n .COUNTERREADVAL(B_po_counter_read_val),\n .D({\\ddr_byte_lane_D.ddr_byte_lane_D_n_1 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_2 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_3 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_4 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_5 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_6 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_7 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_8 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_9 }),\n .D4(D4),\n .D_of_full(D_of_full),\n .D_po_coarse_enable110_out(D_po_coarse_enable110_out),\n .D_po_counter_read_en122_out(D_po_counter_read_en122_out),\n .D_po_fine_enable107_out(D_po_fine_enable107_out),\n .D_po_fine_inc113_out(D_po_fine_inc113_out),\n .D_po_sel_fine_oclk_delay125_out(D_po_sel_fine_oclk_delay125_out),\n .OUTBURSTPENDING(phaser_ctl_bus),\n .PCENABLECALIB(phy_encalib),\n .SR(ofifo_rst),\n .\\calib_sel_reg[1] (\\calib_sel_reg[3] [1:0]),\n .ddr_ck_out(ddr_ck_out),\n .freq_refclk(freq_refclk),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ),\n .init_calib_complete_reg_rep(init_calib_complete_reg_rep),\n .init_calib_complete_reg_rep__5(init_calib_complete_reg_rep__5),\n .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6_0),\n .mc_address(mc_address),\n .mc_cas_n(mc_cas_n),\n .mem_dq_out(mem_dq_out[23:15]),\n .mem_refclk(mem_refclk),\n .mux_cmd_wren(mux_cmd_wren),\n .\\my_empty_reg[1] (\\my_empty_reg[1]_2 ),\n .\\my_empty_reg[7] (\\my_empty_reg[7] ),\n .phy_dout(phy_dout),\n .sync_pulse(sync_pulse));\n LUT1 #(\n .INIT(2'h2)) \n i_0\n (.I0(1'b0),\n .O(A_pi_rst_div2));\n LUT1 #(\n .INIT(2'h2)) \n i_1\n (.I0(1'b0),\n .O(B_pi_rst_div2));\n LUT1 #(\n .INIT(2'h2)) \n i_2\n (.I0(1'b0),\n .O(C_pi_rst_div2));\n LUT1 #(\n .INIT(2'h2)) \n i_3\n (.I0(1'b0),\n .O(D_pi_rst_div2));\n FDRE #(\n .INIT(1'b0)) \n mcGo_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rst_out_reg_n_0),\n .Q(mcGo_w__0),\n .R(1'b0));\n (* box_type = \"PRIMITIVE\" *) \n PHASER_REF #(\n .IS_PWRDWN_INVERTED(1'b0),\n .IS_RST_INVERTED(1'b0)) \n phaser_ref_i\n (.CLKIN(freq_refclk),\n .LOCKED(ref_dll_lock_w),\n .PWRDWN(1'b0),\n .RST(RST0));\n (* box_type = \"PRIMITIVE\" *) \n PHY_CONTROL #(\n .AO_TOGGLE(1),\n .AO_WRLVL_EN(4'b0000),\n .BURST_MODE(\"TRUE\"),\n .CLK_RATIO(4),\n .CMD_OFFSET(8),\n .CO_DURATION(1),\n .DATA_CTL_A_N(\"FALSE\"),\n .DATA_CTL_B_N(\"FALSE\"),\n .DATA_CTL_C_N(\"FALSE\"),\n .DATA_CTL_D_N(\"FALSE\"),\n .DISABLE_SEQ_MATCH(\"TRUE\"),\n .DI_DURATION(1),\n .DO_DURATION(1),\n .EVENTS_DELAY(18),\n .FOUR_WINDOW_CLOCKS(63),\n .MULTI_REGION(\"TRUE\"),\n .PHY_COUNT_ENABLE(\"FALSE\"),\n .RD_CMD_OFFSET_0(10),\n .RD_CMD_OFFSET_1(10),\n .RD_CMD_OFFSET_2(10),\n .RD_CMD_OFFSET_3(10),\n .RD_DURATION_0(6),\n .RD_DURATION_1(6),\n .RD_DURATION_2(6),\n .RD_DURATION_3(6),\n .SYNC_MODE(\"FALSE\"),\n .WR_CMD_OFFSET_0(8),\n .WR_CMD_OFFSET_1(8),\n .WR_CMD_OFFSET_2(8),\n .WR_CMD_OFFSET_3(8),\n .WR_DURATION_0(7),\n .WR_DURATION_1(7),\n .WR_DURATION_2(7),\n .WR_DURATION_3(7)) \n phy_control_i\n (.AUXOUTPUT({phy_control_i_n_14,phy_control_i_n_15,phy_control_i_n_16,phy_control_i_n_17}),\n .INBURSTPENDING({phy_control_i_n_18,phy_control_i_n_19,phy_control_i_n_20,phy_control_i_n_21}),\n .INRANKA({phy_control_i_n_4,phy_control_i_n_5}),\n .INRANKB({phy_control_i_n_6,phy_control_i_n_7}),\n .INRANKC({phy_control_i_n_8,phy_control_i_n_9}),\n .INRANKD({phy_control_i_n_10,phy_control_i_n_11}),\n .MEMREFCLK(mem_refclk),\n .OUTBURSTPENDING({phaser_ctl_bus,phy_control_i_n_23,phy_control_i_n_24,phy_control_i_n_25}),\n .PCENABLECALIB(phy_encalib),\n .PHYCLK(CLK),\n .PHYCTLALMOSTFULL(phy_control_i_n_0),\n .PHYCTLEMPTY(phy_ctl_mstr_empty),\n .PHYCTLFULL(_phy_ctl_full_p),\n .PHYCTLMSTREMPTY(phy_ctl_mstr_empty),\n .PHYCTLREADY(phy_control_i_n_3),\n .PHYCTLWD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,PHYCTLWD[10:3],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PHYCTLWD[2:0]}),\n .PHYCTLWRENABLE(phy_ctl_wr_i2),\n .PLLLOCK(pll_locked),\n .READCALIBENABLE(phy_read_calib),\n .REFDLLLOCK(ref_dll_lock_w),\n .RESET(in0),\n .SYNCIN(sync_pulse),\n .WRITECALIBENABLE(phy_write_calib));\n LUT2 #(\n .INIT(4'hE)) \n phy_mc_ctl_full_r_i_1\n (.I0(_phy_ctl_full_p),\n .I1(_phy_ctl_full_p__0),\n .O(phy_mc_ctl_full));\n (* SOFT_HLUTNM = \"soft_lutpair1019\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\po_counter_read_val_r[0]_i_1 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_counter_read_val_reg[5]_0 [0]),\n .I2(\\calib_sel_reg[3] [2]),\n .O(\\po_counter_read_val_r_reg[5] [0]));\n (* SOFT_HLUTNM = \"soft_lutpair1019\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\po_counter_read_val_r[1]_i_1 \n (.I0(\\po_counter_read_val_w[1]_2 [1]),\n .I1(\\po_counter_read_val_reg[5]_0 [1]),\n .I2(\\calib_sel_reg[3] [2]),\n .O(\\po_counter_read_val_r_reg[5] [1]));\n (* SOFT_HLUTNM = \"soft_lutpair1020\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\po_counter_read_val_r[2]_i_1 \n (.I0(\\po_counter_read_val_w[1]_2 [2]),\n .I1(\\po_counter_read_val_reg[5]_0 [2]),\n .I2(\\calib_sel_reg[3] [2]),\n .O(\\po_counter_read_val_r_reg[5] [2]));\n (* SOFT_HLUTNM = \"soft_lutpair1020\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\po_counter_read_val_r[3]_i_1 \n (.I0(\\po_rdval_cnt_reg[8] [1]),\n .I1(\\po_counter_read_val_reg[5]_0 [3]),\n .I2(\\calib_sel_reg[3] [2]),\n .O(\\po_counter_read_val_r_reg[5] [3]));\n (* SOFT_HLUTNM = \"soft_lutpair1021\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\po_counter_read_val_r[4]_i_1 \n (.I0(\\po_counter_read_val_w[1]_2 [4]),\n .I1(\\po_counter_read_val_reg[5]_0 [4]),\n .I2(\\calib_sel_reg[3] [2]),\n .O(\\po_counter_read_val_r_reg[5] [4]));\n (* SOFT_HLUTNM = \"soft_lutpair1021\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\po_counter_read_val_r[5]_i_1 \n (.I0(\\po_counter_read_val_w[1]_2 [5]),\n .I1(\\po_counter_read_val_reg[5]_0 [5]),\n .I2(\\calib_sel_reg[3] [2]),\n .O(\\po_counter_read_val_r_reg[5] [5]));\n FDRE #(\n .INIT(1'b0)) \n \\po_counter_read_val_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_9 ),\n .Q(\\po_rdval_cnt_reg[8] [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\po_counter_read_val_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_8 ),\n .Q(\\po_counter_read_val_w[1]_2 [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\po_counter_read_val_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_7 ),\n .Q(\\po_counter_read_val_w[1]_2 [2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\po_counter_read_val_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_6 ),\n .Q(\\po_rdval_cnt_reg[8] [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\po_counter_read_val_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_5 ),\n .Q(\\po_counter_read_val_w[1]_2 [4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\po_counter_read_val_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_4 ),\n .Q(\\po_counter_read_val_w[1]_2 [5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\po_counter_read_val_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_3 ),\n .Q(\\po_rdval_cnt_reg[8] [2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\po_counter_read_val_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_2 ),\n .Q(\\po_rdval_cnt_reg[8] [3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\po_counter_read_val_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_1 ),\n .Q(\\po_rdval_cnt_reg[8] [4]),\n .R(1'b0));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/rclk_delay_reg \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/rclk_delay_reg[10]_srl11 \" *) \n SRL16E #(\n .INIT(16'h0000)) \n \\rclk_delay_reg[10]_srl11 \n (.A0(1'b0),\n .A1(1'b1),\n .A2(1'b0),\n .A3(1'b1),\n .CE(1'b1),\n .CLK(CLK),\n .D(\\rclk_delay_reg[10]_srl11_i_1__0_n_0 ),\n .Q(\\rclk_delay_reg[10]_srl11_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\rclk_delay_reg[10]_srl11_i_1__0 \n (.I0(rst_primitives),\n .O(\\rclk_delay_reg[10]_srl11_i_1__0_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rclk_delay_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rclk_delay_reg[10]_srl11_n_0 ),\n .Q(rclk_delay_11),\n .R(1'b0));\n LUT2 #(\n .INIT(4'hE)) \n rst_out_i_1__0\n (.I0(rclk_delay_11),\n .I1(rst_out_reg_n_0),\n .O(rst_out_i_1__0_n_0));\n FDCE #(\n .INIT(1'b0)) \n rst_out_reg\n (.C(CLK),\n .CE(1'b1),\n .CLR(rstdiv0_sync_r1_reg_rep__9),\n .D(rst_out_i_1__0_n_0),\n .Q(rst_out_reg_n_0));\n LUT1 #(\n .INIT(2'h1)) \n rst_primitives_i_1__0\n (.I0(phy_control_i_n_3),\n .O(rst_primitives_i_1__0_n_0));\n FDRE #(\n .INIT(1'b0)) \n rst_primitives_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rst_primitives_i_1__0_n_0),\n .Q(rst_primitives),\n .R(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_phy_ck_addr_cmd_delay\n (ck_addr_cmd_delay_done,\n po_en_stg2_f,\n D_po_coarse_enable110_out,\n \\po_counter_read_val_reg[8] ,\n \\po_counter_read_val_reg[8]_0 ,\n \\po_counter_read_val_reg[8]_1 ,\n \\po_counter_read_val_reg[8]_2 ,\n \\po_counter_read_val_reg[8]_3 ,\n \\po_counter_read_val_reg[8]_4 ,\n \\po_counter_read_val_reg[8]_5 ,\n \\wait_cnt_r_reg[0]_0 ,\n \\init_state_r_reg[0] ,\n delay_dec_done_reg_0,\n delay_dec_done_reg_1,\n ctl_lane_cnt,\n po_cnt_inc_reg_0,\n CLK,\n rstdiv0_sync_r1_reg_rep__9,\n \\wait_cnt_r_reg[0]_1 ,\n \\wait_cnt_r_reg[0]_2 ,\n Q,\n calib_in_common,\n dqs_wl_po_stg2_c_incdec,\n \\calib_zero_inputs_reg[1] ,\n cnt_pwron_cke_done_r,\n \\mcGo_r_reg[15] ,\n pi_fine_dly_dec_done,\n dqs_po_dec_done,\n rstdiv0_sync_r1_reg_rep__24,\n rstdiv0_sync_r1_reg_rep__23,\n cmd_delay_start0,\n p_1_in);\n output ck_addr_cmd_delay_done;\n output po_en_stg2_f;\n output D_po_coarse_enable110_out;\n output \\po_counter_read_val_reg[8] ;\n output \\po_counter_read_val_reg[8]_0 ;\n output \\po_counter_read_val_reg[8]_1 ;\n output \\po_counter_read_val_reg[8]_2 ;\n output \\po_counter_read_val_reg[8]_3 ;\n output \\po_counter_read_val_reg[8]_4 ;\n output \\po_counter_read_val_reg[8]_5 ;\n output [0:0]\\wait_cnt_r_reg[0]_0 ;\n output \\init_state_r_reg[0] ;\n output delay_dec_done_reg_0;\n output delay_dec_done_reg_1;\n output [2:0]ctl_lane_cnt;\n output po_cnt_inc_reg_0;\n input CLK;\n input rstdiv0_sync_r1_reg_rep__9;\n input \\wait_cnt_r_reg[0]_1 ;\n input \\wait_cnt_r_reg[0]_2 ;\n input [1:0]Q;\n input calib_in_common;\n input dqs_wl_po_stg2_c_incdec;\n input [1:0]\\calib_zero_inputs_reg[1] ;\n input cnt_pwron_cke_done_r;\n input \\mcGo_r_reg[15] ;\n input pi_fine_dly_dec_done;\n input dqs_po_dec_done;\n input rstdiv0_sync_r1_reg_rep__24;\n input rstdiv0_sync_r1_reg_rep__23;\n input cmd_delay_start0;\n input p_1_in;\n\n wire CLK;\n wire D_po_coarse_enable110_out;\n wire [1:0]Q;\n wire calib_in_common;\n wire [1:0]\\calib_zero_inputs_reg[1] ;\n wire ck_addr_cmd_delay_done;\n wire cmd_delay_start0;\n wire cnt_pwron_cke_done_r;\n wire [2:0]ctl_lane_cnt;\n wire ctl_lane_cnt1;\n wire \\ctl_lane_cnt[0]_i_1_n_0 ;\n wire \\ctl_lane_cnt[1]_i_1_n_0 ;\n wire \\ctl_lane_cnt[2]_i_1_n_0 ;\n wire \\ctl_lane_cnt[2]_i_4_n_0 ;\n wire \\ctl_lane_cnt[3]_i_1_n_0 ;\n wire \\ctl_lane_cnt[3]_i_3_n_0 ;\n wire \\ctl_lane_cnt_reg_n_0_[3] ;\n wire delay_cnt_r0;\n wire \\delay_cnt_r[0]_i_1_n_0 ;\n wire \\delay_cnt_r[0]_i_2_n_0 ;\n wire \\delay_cnt_r[1]_i_1_n_0 ;\n wire \\delay_cnt_r[2]_i_1_n_0 ;\n wire \\delay_cnt_r[3]_i_1_n_0 ;\n wire \\delay_cnt_r[4]_i_1_n_0 ;\n wire \\delay_cnt_r[5]_i_1_n_0 ;\n wire \\delay_cnt_r[5]_i_3_n_0 ;\n wire \\delay_cnt_r[5]_i_5_n_0 ;\n wire \\delay_cnt_r_reg_n_0_[0] ;\n wire \\delay_cnt_r_reg_n_0_[1] ;\n wire \\delay_cnt_r_reg_n_0_[2] ;\n wire \\delay_cnt_r_reg_n_0_[3] ;\n wire \\delay_cnt_r_reg_n_0_[4] ;\n wire \\delay_cnt_r_reg_n_0_[5] ;\n wire delay_dec_done;\n wire delay_dec_done_i_1_n_0;\n wire delay_dec_done_reg_0;\n wire delay_dec_done_reg_1;\n wire delay_done_r3_reg_srl3_n_0;\n wire delaydec_cnt_r0;\n wire delaydec_cnt_r10_in;\n wire \\delaydec_cnt_r[0]_i_1_n_0 ;\n wire \\delaydec_cnt_r[1]_i_1_n_0 ;\n wire \\delaydec_cnt_r[2]_i_1_n_0 ;\n wire \\delaydec_cnt_r[3]_i_1_n_0 ;\n wire \\delaydec_cnt_r[4]_i_1_n_0 ;\n wire \\delaydec_cnt_r[5]_i_1_n_0 ;\n wire \\delaydec_cnt_r[5]_i_3_n_0 ;\n wire [5:0]delaydec_cnt_r_reg__0;\n wire dqs_po_dec_done;\n wire dqs_wl_po_stg2_c_incdec;\n wire \\init_state_r_reg[0] ;\n wire \\mcGo_r_reg[15] ;\n wire p_1_in;\n wire p_3_in;\n wire pi_fine_dly_dec_done;\n wire po_cnt_dec;\n wire po_cnt_inc;\n wire po_cnt_inc_reg_0;\n wire \\po_counter_read_val_reg[8] ;\n wire \\po_counter_read_val_reg[8]_0 ;\n wire \\po_counter_read_val_reg[8]_1 ;\n wire \\po_counter_read_val_reg[8]_2 ;\n wire \\po_counter_read_val_reg[8]_3 ;\n wire \\po_counter_read_val_reg[8]_4 ;\n wire \\po_counter_read_val_reg[8]_5 ;\n wire po_en_stg2_f;\n wire rstdiv0_sync_r1_reg_rep__23;\n wire rstdiv0_sync_r1_reg_rep__24;\n wire rstdiv0_sync_r1_reg_rep__9;\n wire wait_cnt_r0;\n wire [0:0]wait_cnt_r0__0;\n wire \\wait_cnt_r[1]_i_1__0_n_0 ;\n wire \\wait_cnt_r[2]_i_1__1_n_0 ;\n wire \\wait_cnt_r[3]_i_1__0_n_0 ;\n wire \\wait_cnt_r[3]_i_3__0_n_0 ;\n wire [0:0]\\wait_cnt_r_reg[0]_0 ;\n wire \\wait_cnt_r_reg[0]_1 ;\n wire \\wait_cnt_r_reg[0]_2 ;\n wire [3:1]wait_cnt_r_reg__0__0;\n\n LUT6 #(\n .INIT(64'h00000000DE000000)) \n \\ctl_lane_cnt[0]_i_1 \n (.I0(ctl_lane_cnt[0]),\n .I1(ctl_lane_cnt1),\n .I2(delaydec_cnt_r10_in),\n .I3(pi_fine_dly_dec_done),\n .I4(dqs_po_dec_done),\n .I5(rstdiv0_sync_r1_reg_rep__24),\n .O(\\ctl_lane_cnt[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00000000DEEE0000)) \n \\ctl_lane_cnt[1]_i_1 \n (.I0(ctl_lane_cnt[1]),\n .I1(ctl_lane_cnt1),\n .I2(delaydec_cnt_r10_in),\n .I3(ctl_lane_cnt[0]),\n .I4(cmd_delay_start0),\n .I5(rstdiv0_sync_r1_reg_rep__24),\n .O(\\ctl_lane_cnt[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000006AAA)) \n \\ctl_lane_cnt[2]_i_1 \n (.I0(ctl_lane_cnt[2]),\n .I1(delaydec_cnt_r10_in),\n .I2(ctl_lane_cnt[0]),\n .I3(ctl_lane_cnt[1]),\n .I4(p_1_in),\n .I5(ctl_lane_cnt1),\n .O(\\ctl_lane_cnt[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair305\" *) \n LUT4 #(\n .INIT(16'h0004)) \n \\ctl_lane_cnt[2]_i_3 \n (.I0(\\delay_cnt_r[0]_i_2_n_0 ),\n .I1(delaydec_cnt_r_reg__0[0]),\n .I2(delay_dec_done),\n .I3(\\ctl_lane_cnt[2]_i_4_n_0 ),\n .O(ctl_lane_cnt1));\n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n \\ctl_lane_cnt[2]_i_4 \n (.I0(delaydec_cnt_r_reg__0[4]),\n .I1(delaydec_cnt_r_reg__0[2]),\n .I2(delaydec_cnt_r_reg__0[1]),\n .I3(delaydec_cnt_r_reg__0[3]),\n .I4(delaydec_cnt_r_reg__0[5]),\n .O(\\ctl_lane_cnt[2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h000000006AAAAAAA)) \n \\ctl_lane_cnt[3]_i_1 \n (.I0(\\ctl_lane_cnt_reg_n_0_[3] ),\n .I1(delaydec_cnt_r10_in),\n .I2(ctl_lane_cnt[2]),\n .I3(ctl_lane_cnt[1]),\n .I4(ctl_lane_cnt[0]),\n .I5(\\ctl_lane_cnt[3]_i_3_n_0 ),\n .O(\\ctl_lane_cnt[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000054555555)) \n \\ctl_lane_cnt[3]_i_2 \n (.I0(delay_dec_done_reg_1),\n .I1(\\ctl_lane_cnt_reg_n_0_[3] ),\n .I2(ctl_lane_cnt[2]),\n .I3(ctl_lane_cnt[1]),\n .I4(ctl_lane_cnt[0]),\n .I5(delay_dec_done_reg_0),\n .O(delaydec_cnt_r10_in));\n LUT4 #(\n .INIT(16'hFFBF)) \n \\ctl_lane_cnt[3]_i_3 \n (.I0(ctl_lane_cnt1),\n .I1(pi_fine_dly_dec_done),\n .I2(dqs_po_dec_done),\n .I3(rstdiv0_sync_r1_reg_rep__24),\n .O(\\ctl_lane_cnt[3]_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\ctl_lane_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ctl_lane_cnt[0]_i_1_n_0 ),\n .Q(ctl_lane_cnt[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\ctl_lane_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ctl_lane_cnt[1]_i_1_n_0 ),\n .Q(ctl_lane_cnt[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\ctl_lane_cnt_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ctl_lane_cnt[2]_i_1_n_0 ),\n .Q(ctl_lane_cnt[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\ctl_lane_cnt_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ctl_lane_cnt[3]_i_1_n_0 ),\n .Q(\\ctl_lane_cnt_reg_n_0_[3] ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hDDFFEEFC)) \n \\delay_cnt_r[0]_i_1 \n (.I0(po_cnt_inc),\n .I1(delay_dec_done_reg_0),\n .I2(\\delay_cnt_r[0]_i_2_n_0 ),\n .I3(delay_dec_done_reg_1),\n .I4(\\delay_cnt_r_reg_n_0_[0] ),\n .O(\\delay_cnt_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair302\" *) \n LUT4 #(\n .INIT(16'hEFFF)) \n \\delay_cnt_r[0]_i_2 \n (.I0(\\ctl_lane_cnt_reg_n_0_[3] ),\n .I1(ctl_lane_cnt[2]),\n .I2(ctl_lane_cnt[1]),\n .I3(ctl_lane_cnt[0]),\n .O(\\delay_cnt_r[0]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair307\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\delay_cnt_r[1]_i_1 \n (.I0(\\delay_cnt_r_reg_n_0_[0] ),\n .I1(\\delay_cnt_r_reg_n_0_[1] ),\n .O(\\delay_cnt_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair307\" *) \n LUT3 #(\n .INIT(8'hE1)) \n \\delay_cnt_r[2]_i_1 \n (.I0(\\delay_cnt_r_reg_n_0_[1] ),\n .I1(\\delay_cnt_r_reg_n_0_[0] ),\n .I2(\\delay_cnt_r_reg_n_0_[2] ),\n .O(\\delay_cnt_r[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair303\" *) \n LUT4 #(\n .INIT(16'hFE01)) \n \\delay_cnt_r[3]_i_1 \n (.I0(\\delay_cnt_r_reg_n_0_[2] ),\n .I1(\\delay_cnt_r_reg_n_0_[0] ),\n .I2(\\delay_cnt_r_reg_n_0_[1] ),\n .I3(\\delay_cnt_r_reg_n_0_[3] ),\n .O(\\delay_cnt_r[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair303\" *) \n LUT5 #(\n .INIT(32'hFFFE0001)) \n \\delay_cnt_r[4]_i_1 \n (.I0(\\delay_cnt_r_reg_n_0_[3] ),\n .I1(\\delay_cnt_r_reg_n_0_[1] ),\n .I2(\\delay_cnt_r_reg_n_0_[0] ),\n .I3(\\delay_cnt_r_reg_n_0_[2] ),\n .I4(\\delay_cnt_r_reg_n_0_[4] ),\n .O(\\delay_cnt_r[4]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hFE)) \n \\delay_cnt_r[5]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__23),\n .I1(delay_dec_done_reg_0),\n .I2(\\delay_cnt_r[5]_i_5_n_0 ),\n .O(\\delay_cnt_r[5]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\delay_cnt_r[5]_i_2 \n (.I0(delay_dec_done_reg_1),\n .I1(po_cnt_inc),\n .O(delay_cnt_r0));\n LUT6 #(\n .INIT(64'hFFFFFFFE00000001)) \n \\delay_cnt_r[5]_i_3 \n (.I0(\\delay_cnt_r_reg_n_0_[4] ),\n .I1(\\delay_cnt_r_reg_n_0_[2] ),\n .I2(\\delay_cnt_r_reg_n_0_[0] ),\n .I3(\\delay_cnt_r_reg_n_0_[1] ),\n .I4(\\delay_cnt_r_reg_n_0_[3] ),\n .I5(\\delay_cnt_r_reg_n_0_[5] ),\n .O(\\delay_cnt_r[5]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\delay_cnt_r[5]_i_4 \n (.I0(delaydec_cnt_r_reg__0[5]),\n .I1(delaydec_cnt_r_reg__0[3]),\n .I2(delaydec_cnt_r_reg__0[1]),\n .I3(delaydec_cnt_r_reg__0[2]),\n .I4(delaydec_cnt_r_reg__0[4]),\n .I5(delaydec_cnt_r_reg__0[0]),\n .O(delay_dec_done_reg_0));\n (* SOFT_HLUTNM = \"soft_lutpair302\" *) \n LUT5 #(\n .INIT(32'h0000FFF7)) \n \\delay_cnt_r[5]_i_5 \n (.I0(ctl_lane_cnt[0]),\n .I1(ctl_lane_cnt[1]),\n .I2(ctl_lane_cnt[2]),\n .I3(\\ctl_lane_cnt_reg_n_0_[3] ),\n .I4(delay_dec_done_reg_1),\n .O(\\delay_cnt_r[5]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\delay_cnt_r[5]_i_6 \n (.I0(\\delay_cnt_r_reg_n_0_[4] ),\n .I1(\\delay_cnt_r_reg_n_0_[2] ),\n .I2(\\delay_cnt_r_reg_n_0_[0] ),\n .I3(\\delay_cnt_r_reg_n_0_[1] ),\n .I4(\\delay_cnt_r_reg_n_0_[3] ),\n .I5(\\delay_cnt_r_reg_n_0_[5] ),\n .O(delay_dec_done_reg_1));\n FDRE #(\n .INIT(1'b0)) \n \\delay_cnt_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\delay_cnt_r[0]_i_1_n_0 ),\n .Q(\\delay_cnt_r_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE #(\n .INIT(1'b0)) \n \\delay_cnt_r_reg[1] \n (.C(CLK),\n .CE(delay_cnt_r0),\n .D(\\delay_cnt_r[1]_i_1_n_0 ),\n .Q(\\delay_cnt_r_reg_n_0_[1] ),\n .R(\\delay_cnt_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\delay_cnt_r_reg[2] \n (.C(CLK),\n .CE(delay_cnt_r0),\n .D(\\delay_cnt_r[2]_i_1_n_0 ),\n .Q(\\delay_cnt_r_reg_n_0_[2] ),\n .R(\\delay_cnt_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\delay_cnt_r_reg[3] \n (.C(CLK),\n .CE(delay_cnt_r0),\n .D(\\delay_cnt_r[3]_i_1_n_0 ),\n .Q(\\delay_cnt_r_reg_n_0_[3] ),\n .R(\\delay_cnt_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\delay_cnt_r_reg[4] \n (.C(CLK),\n .CE(delay_cnt_r0),\n .D(\\delay_cnt_r[4]_i_1_n_0 ),\n .Q(\\delay_cnt_r_reg_n_0_[4] ),\n .R(\\delay_cnt_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\delay_cnt_r_reg[5] \n (.C(CLK),\n .CE(delay_cnt_r0),\n .D(\\delay_cnt_r[5]_i_3_n_0 ),\n .Q(\\delay_cnt_r_reg_n_0_[5] ),\n .R(\\delay_cnt_r[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00000000AAAB0000)) \n delay_dec_done_i_1\n (.I0(delay_dec_done),\n .I1(\\delay_cnt_r[0]_i_2_n_0 ),\n .I2(delay_dec_done_reg_0),\n .I3(delay_dec_done_reg_1),\n .I4(cmd_delay_start0),\n .I5(rstdiv0_sync_r1_reg_rep__24),\n .O(delay_dec_done_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n delay_dec_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(delay_dec_done_i_1_n_0),\n .Q(delay_dec_done),\n .R(1'b0));\n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/delay_done_r3_reg_srl3 \" *) \n SRL16E #(\n .INIT(16'h0000)) \n delay_done_r3_reg_srl3\n (.A0(1'b0),\n .A1(1'b1),\n .A2(1'b0),\n .A3(1'b0),\n .CE(1'b1),\n .CLK(CLK),\n .D(delay_dec_done),\n .Q(delay_done_r3_reg_srl3_n_0));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n delay_done_r4_reg\n (.C(CLK),\n .CE(1'b1),\n .D(delay_done_r3_reg_srl3_n_0),\n .Q(ck_addr_cmd_delay_done),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair309\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\delaydec_cnt_r[0]_i_1 \n (.I0(delaydec_cnt_r_reg__0[0]),\n .O(\\delaydec_cnt_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair305\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\delaydec_cnt_r[1]_i_1 \n (.I0(delaydec_cnt_r_reg__0[0]),\n .I1(delaydec_cnt_r_reg__0[1]),\n .O(\\delaydec_cnt_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair309\" *) \n LUT3 #(\n .INIT(8'hE1)) \n \\delaydec_cnt_r[2]_i_1 \n (.I0(delaydec_cnt_r_reg__0[0]),\n .I1(delaydec_cnt_r_reg__0[1]),\n .I2(delaydec_cnt_r_reg__0[2]),\n .O(\\delaydec_cnt_r[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair304\" *) \n LUT4 #(\n .INIT(16'hFE01)) \n \\delaydec_cnt_r[3]_i_1 \n (.I0(delaydec_cnt_r_reg__0[0]),\n .I1(delaydec_cnt_r_reg__0[1]),\n .I2(delaydec_cnt_r_reg__0[2]),\n .I3(delaydec_cnt_r_reg__0[3]),\n .O(\\delaydec_cnt_r[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair304\" *) \n LUT5 #(\n .INIT(32'hFFFE0001)) \n \\delaydec_cnt_r[4]_i_1 \n (.I0(delaydec_cnt_r_reg__0[0]),\n .I1(delaydec_cnt_r_reg__0[2]),\n .I2(delaydec_cnt_r_reg__0[1]),\n .I3(delaydec_cnt_r_reg__0[3]),\n .I4(delaydec_cnt_r_reg__0[4]),\n .O(\\delaydec_cnt_r[4]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hFFBF)) \n \\delaydec_cnt_r[5]_i_1 \n (.I0(delaydec_cnt_r10_in),\n .I1(pi_fine_dly_dec_done),\n .I2(dqs_po_dec_done),\n .I3(rstdiv0_sync_r1_reg_rep__24),\n .O(\\delaydec_cnt_r[5]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\delaydec_cnt_r[5]_i_2 \n (.I0(delay_dec_done_reg_0),\n .I1(po_cnt_dec),\n .O(delaydec_cnt_r0));\n LUT6 #(\n .INIT(64'hFFFFFFFE00000001)) \n \\delaydec_cnt_r[5]_i_3 \n (.I0(delaydec_cnt_r_reg__0[0]),\n .I1(delaydec_cnt_r_reg__0[3]),\n .I2(delaydec_cnt_r_reg__0[1]),\n .I3(delaydec_cnt_r_reg__0[2]),\n .I4(delaydec_cnt_r_reg__0[4]),\n .I5(delaydec_cnt_r_reg__0[5]),\n .O(\\delaydec_cnt_r[5]_i_3_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\delaydec_cnt_r_reg[0] \n (.C(CLK),\n .CE(delaydec_cnt_r0),\n .D(\\delaydec_cnt_r[0]_i_1_n_0 ),\n .Q(delaydec_cnt_r_reg__0[0]),\n .S(\\delaydec_cnt_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\delaydec_cnt_r_reg[1] \n (.C(CLK),\n .CE(delaydec_cnt_r0),\n .D(\\delaydec_cnt_r[1]_i_1_n_0 ),\n .Q(delaydec_cnt_r_reg__0[1]),\n .R(\\delaydec_cnt_r[5]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\delaydec_cnt_r_reg[2] \n (.C(CLK),\n .CE(delaydec_cnt_r0),\n .D(\\delaydec_cnt_r[2]_i_1_n_0 ),\n .Q(delaydec_cnt_r_reg__0[2]),\n .S(\\delaydec_cnt_r[5]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\delaydec_cnt_r_reg[3] \n (.C(CLK),\n .CE(delaydec_cnt_r0),\n .D(\\delaydec_cnt_r[3]_i_1_n_0 ),\n .Q(delaydec_cnt_r_reg__0[3]),\n .S(\\delaydec_cnt_r[5]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\delaydec_cnt_r_reg[4] \n (.C(CLK),\n .CE(delaydec_cnt_r0),\n .D(\\delaydec_cnt_r[4]_i_1_n_0 ),\n .Q(delaydec_cnt_r_reg__0[4]),\n .S(\\delaydec_cnt_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\delaydec_cnt_r_reg[5] \n (.C(CLK),\n .CE(delaydec_cnt_r0),\n .D(\\delaydec_cnt_r[5]_i_3_n_0 ),\n .Q(delaydec_cnt_r_reg__0[5]),\n .R(\\delaydec_cnt_r[5]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h80)) \n \\init_state_r[0]_i_39 \n (.I0(ck_addr_cmd_delay_done),\n .I1(cnt_pwron_cke_done_r),\n .I2(\\mcGo_r_reg[15] ),\n .O(\\init_state_r_reg[0] ));\n LUT6 #(\n .INIT(64'h0000000008080800)) \n phaser_out_i_1\n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(calib_in_common),\n .I3(p_3_in),\n .I4(dqs_wl_po_stg2_c_incdec),\n .I5(\\calib_zero_inputs_reg[1] [1]),\n .O(D_po_coarse_enable110_out));\n LUT6 #(\n .INIT(64'h0000000001010100)) \n phaser_out_i_1__0\n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(calib_in_common),\n .I3(p_3_in),\n .I4(dqs_wl_po_stg2_c_incdec),\n .I5(\\calib_zero_inputs_reg[1] [1]),\n .O(\\po_counter_read_val_reg[8] ));\n LUT6 #(\n .INIT(64'h0000000004040400)) \n phaser_out_i_1__1\n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(calib_in_common),\n .I3(p_3_in),\n .I4(dqs_wl_po_stg2_c_incdec),\n .I5(\\calib_zero_inputs_reg[1] [1]),\n .O(\\po_counter_read_val_reg[8]_0 ));\n LUT6 #(\n .INIT(64'h0000000004040400)) \n phaser_out_i_1__2\n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(calib_in_common),\n .I3(p_3_in),\n .I4(dqs_wl_po_stg2_c_incdec),\n .I5(\\calib_zero_inputs_reg[1] [1]),\n .O(\\po_counter_read_val_reg[8]_1 ));\n LUT6 #(\n .INIT(64'h00000000EAEAEA00)) \n phaser_out_i_1__3\n (.I0(calib_in_common),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(p_3_in),\n .I4(dqs_wl_po_stg2_c_incdec),\n .I5(\\calib_zero_inputs_reg[1] [0]),\n .O(\\po_counter_read_val_reg[8]_2 ));\n LUT6 #(\n .INIT(64'h00000000BABABA00)) \n phaser_out_i_1__4\n (.I0(calib_in_common),\n .I1(Q[0]),\n .I2(Q[1]),\n .I3(p_3_in),\n .I4(dqs_wl_po_stg2_c_incdec),\n .I5(\\calib_zero_inputs_reg[1] [0]),\n .O(\\po_counter_read_val_reg[8]_3 ));\n LUT6 #(\n .INIT(64'h00000000BABABA00)) \n phaser_out_i_1__5\n (.I0(calib_in_common),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(p_3_in),\n .I4(dqs_wl_po_stg2_c_incdec),\n .I5(\\calib_zero_inputs_reg[1] [0]),\n .O(\\po_counter_read_val_reg[8]_4 ));\n LUT6 #(\n .INIT(64'h00000000ABABAB00)) \n phaser_out_i_1__6\n (.I0(calib_in_common),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(p_3_in),\n .I4(dqs_wl_po_stg2_c_incdec),\n .I5(\\calib_zero_inputs_reg[1] [0]),\n .O(\\po_counter_read_val_reg[8]_5 ));\n FDRE #(\n .INIT(1'b0)) \n po_cnt_dec_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\wait_cnt_r_reg[0]_2 ),\n .Q(po_cnt_dec),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair306\" *) \n LUT3 #(\n .INIT(8'hFE)) \n po_cnt_inc_i_2\n (.I0(wait_cnt_r_reg__0__0[2]),\n .I1(wait_cnt_r_reg__0__0[1]),\n .I2(wait_cnt_r_reg__0__0[3]),\n .O(po_cnt_inc_reg_0));\n FDRE #(\n .INIT(1'b0)) \n po_cnt_inc_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\wait_cnt_r_reg[0]_1 ),\n .Q(po_cnt_inc),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n po_en_stg2_f_reg\n (.C(CLK),\n .CE(1'b1),\n .D(po_cnt_dec),\n .Q(po_en_stg2_f),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE #(\n .INIT(1'b0)) \n po_stg2_c_incdec_reg\n (.C(CLK),\n .CE(1'b1),\n .D(po_cnt_inc),\n .Q(p_3_in),\n .R(rstdiv0_sync_r1_reg_rep__9));\n LUT1 #(\n .INIT(2'h1)) \n \\wait_cnt_r[0]_i_1__0 \n (.I0(\\wait_cnt_r_reg[0]_0 ),\n .O(wait_cnt_r0__0));\n (* SOFT_HLUTNM = \"soft_lutpair308\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\wait_cnt_r[1]_i_1__0 \n (.I0(\\wait_cnt_r_reg[0]_0 ),\n .I1(wait_cnt_r_reg__0__0[1]),\n .O(\\wait_cnt_r[1]_i_1__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair308\" *) \n LUT3 #(\n .INIT(8'hE1)) \n \\wait_cnt_r[2]_i_1__1 \n (.I0(wait_cnt_r_reg__0__0[1]),\n .I1(\\wait_cnt_r_reg[0]_0 ),\n .I2(wait_cnt_r_reg__0__0[2]),\n .O(\\wait_cnt_r[2]_i_1__1_n_0 ));\n LUT3 #(\n .INIT(8'hFE)) \n \\wait_cnt_r[3]_i_1__0 \n (.I0(rstdiv0_sync_r1_reg_rep__23),\n .I1(po_cnt_dec),\n .I2(po_cnt_inc),\n .O(\\wait_cnt_r[3]_i_1__0_n_0 ));\n LUT6 #(\n .INIT(64'hC0C0C0C0C0C0C080)) \n \\wait_cnt_r[3]_i_2__0 \n (.I0(\\wait_cnt_r_reg[0]_0 ),\n .I1(pi_fine_dly_dec_done),\n .I2(dqs_po_dec_done),\n .I3(wait_cnt_r_reg__0__0[2]),\n .I4(wait_cnt_r_reg__0__0[1]),\n .I5(wait_cnt_r_reg__0__0[3]),\n .O(wait_cnt_r0));\n (* SOFT_HLUTNM = \"soft_lutpair306\" *) \n LUT4 #(\n .INIT(16'hFE01)) \n \\wait_cnt_r[3]_i_3__0 \n (.I0(\\wait_cnt_r_reg[0]_0 ),\n .I1(wait_cnt_r_reg__0__0[1]),\n .I2(wait_cnt_r_reg__0__0[2]),\n .I3(wait_cnt_r_reg__0__0[3]),\n .O(\\wait_cnt_r[3]_i_3__0_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\wait_cnt_r_reg[0] \n (.C(CLK),\n .CE(wait_cnt_r0),\n .D(wait_cnt_r0__0),\n .Q(\\wait_cnt_r_reg[0]_0 ),\n .R(\\wait_cnt_r[3]_i_1__0_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\wait_cnt_r_reg[1] \n (.C(CLK),\n .CE(wait_cnt_r0),\n .D(\\wait_cnt_r[1]_i_1__0_n_0 ),\n .Q(wait_cnt_r_reg__0__0[1]),\n .R(\\wait_cnt_r[3]_i_1__0_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\wait_cnt_r_reg[2] \n (.C(CLK),\n .CE(wait_cnt_r0),\n .D(\\wait_cnt_r[2]_i_1__1_n_0 ),\n .Q(wait_cnt_r_reg__0__0[2]),\n .R(\\wait_cnt_r[3]_i_1__0_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\wait_cnt_r_reg[3] \n (.C(CLK),\n .CE(wait_cnt_r0),\n .D(\\wait_cnt_r[3]_i_3__0_n_0 ),\n .Q(wait_cnt_r_reg__0__0[3]),\n .S(\\wait_cnt_r[3]_i_1__0_n_0 ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_phy_dqs_found_cal\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_phy_dqs_found_cal\n (init_dqsfound_done_r2,\n init_dqsfound_done_r5,\n out,\n pi_dqs_found_any_bank,\n pi_dqs_found_rank_done,\n rd_data_offset_cal_done,\n rst_dqs_find_r1_reg_0,\n pi_dqs_found_done_r1_reg,\n \\pi_rst_stg1_cal_r_reg[0]_0 ,\n fine_adjust_done_r_reg_0,\n init_dec_done_reg_0,\n final_dec_done_reg_0,\n dqs_found_prech_req,\n ck_po_stg2_f_indec,\n ck_po_stg2_f_en,\n \\pi_dqs_found_all_bank_r_reg[1]_0 ,\n D_po_fine_enable107_out,\n D_po_fine_inc113_out,\n \\po_counter_read_val_reg[8] ,\n \\po_counter_read_val_reg[8]_0 ,\n \\po_counter_read_val_reg[8]_1 ,\n \\po_counter_read_val_reg[8]_2 ,\n \\po_counter_read_val_reg[8]_3 ,\n \\po_counter_read_val_reg[8]_4 ,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n \\po_counter_read_val_reg[8]_5 ,\n \\po_counter_read_val_reg[8]_6 ,\n ififo_rst_reg,\n \\po_counter_read_val_reg[8]_7 ,\n \\po_counter_read_val_reg[8]_8 ,\n ififo_rst_reg_0,\n \\po_counter_read_val_reg[8]_9 ,\n \\po_counter_read_val_reg[8]_10 ,\n ififo_rst_reg_1,\n \\po_counter_read_val_reg[8]_11 ,\n \\po_counter_read_val_reg[8]_12 ,\n ififo_rst_reg_2,\n fine_adj_state_r144_out,\n \\FSM_sequential_fine_adj_state_r_reg[2]_0 ,\n \\dec_cnt_reg[0]_0 ,\n \\FSM_sequential_fine_adj_state_r_reg[0]_0 ,\n \\rd_byte_data_offset_reg[0][9]_0 ,\n \\cmd_pipe_plus.mc_data_offset_reg[4] ,\n \\cmd_pipe_plus.mc_data_offset_reg[5] ,\n \\cmd_pipe_plus.mc_data_offset_reg[1] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[4] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[5] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[1] ,\n \\cmd_pipe_plus.mc_data_offset_reg[0] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[0] ,\n \\rd_byte_data_offset_reg[0]_3 ,\n p_1_in27_in,\n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 ,\n p_1_in50_in,\n \\pi_rst_stg1_cal_r_reg[0]_1 ,\n fine_adj_state_r16_out,\n dqs_found_prech_req_reg_0,\n final_dec_done_reg_1,\n \\FSM_sequential_fine_adj_state_r_reg[0]_1 ,\n \\rank_final_loop[0].final_do_max_reg[0][3]_0 ,\n \\rank_final_loop[0].final_do_max_reg[0][3]_1 ,\n \\init_state_r_reg[1] ,\n \\init_state_r_reg[2] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ,\n \\init_state_r_reg[1]_0 ,\n \\init_state_r_reg[1]_1 ,\n \\calib_data_offset_0_reg[5] ,\n \\calib_data_offset_0_reg[4] ,\n \\calib_data_offset_0_reg[1] ,\n \\calib_data_offset_0_reg[0] ,\n \\calib_data_offset_1_reg[5] ,\n \\calib_data_offset_1_reg[4] ,\n \\calib_data_offset_1_reg[1] ,\n \\calib_data_offset_1_reg[0] ,\n \\gen_byte_sel_div1.ctl_lane_sel_reg[0] ,\n ctl_lane_sel,\n \\gen_byte_sel_div1.ctl_lane_sel_reg[1] ,\n \\gen_byte_sel_div1.ctl_lane_sel_reg[2] ,\n \\calib_zero_inputs_reg[1] ,\n D,\n \\calib_zero_inputs_reg[0] ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ,\n rank_done_r_reg_0,\n rst_dqs_find_reg_0,\n dqs_found_prech_req_reg_1,\n rst_dqs_find_reg_1,\n init_dec_done_reg_1,\n rst_dqs_find,\n CLK,\n in0,\n pi_dqs_found_start_reg,\n rstdiv0_sync_r1_reg_rep__12,\n SR,\n rstdiv0_sync_r1_reg_rep__13,\n \\pi_dqs_found_lanes_r3_reg[3]_0 ,\n \\pi_dqs_found_all_bank_r_reg[1]_1 ,\n init_dqsfound_done_r_reg_0,\n \\FSM_sequential_fine_adj_state_r_reg[0]_2 ,\n \\FSM_sequential_fine_adj_state_r_reg[1]_0 ,\n \\FSM_sequential_fine_adj_state_r_reg[0]_3 ,\n init_dec_done_reg_2,\n \\FSM_sequential_fine_adj_state_r_reg[1]_1 ,\n \\FSM_sequential_fine_adj_state_r_reg[2]_1 ,\n \\FSM_sequential_fine_adj_state_r_reg[1]_2 ,\n \\FSM_sequential_fine_adj_state_r_reg[1]_3 ,\n pi_dqs_found_start_reg_0,\n Q,\n calib_in_common,\n po_enstg2_f,\n \\calib_zero_inputs_reg[1]_0 ,\n po_stg2_fincdec,\n pi_calib_done,\n oclkdelay_calib_done_r_reg,\n pi_f_inc_reg,\n \\gen_byte_sel_div1.calib_in_common_reg_0 ,\n dqs_po_stg2_f_incdec,\n po_stg23_incdec,\n dqs_po_en_stg2_f,\n po_en_stg2_f,\n po_en_stg23,\n \\gen_byte_sel_div1.calib_in_common_reg_1 ,\n \\gen_byte_sel_div1.calib_in_common_reg_2 ,\n \\gen_byte_sel_div1.calib_in_common_reg_3 ,\n wrcal_done_reg,\n rdlvl_stg1_done_int_reg,\n prbs_rdlvl_done_reg_rep,\n rstdiv0_sync_r1_reg_rep__23,\n detect_pi_found_dqs,\n \\num_refresh_reg[1] ,\n oclkdelay_calib_done_r_reg_0,\n mpr_rdlvl_done_r_reg,\n cnt_cmd_done_r,\n prbs_last_byte_done_r,\n wrlvl_byte_redo,\n wrlvl_done_r1,\n oclkdelay_center_calib_done_r_reg,\n wrlvl_final_mux,\n pi_dqs_found_done_r1,\n ck_addr_cmd_delay_done,\n ctl_lane_cnt,\n \\gen_byte_sel_div1.ctl_lane_sel_reg[0]_0 ,\n \\gen_byte_sel_div1.ctl_lane_sel_reg[1]_0 ,\n \\gen_byte_sel_div1.ctl_lane_sel_reg[2]_0 ,\n pi_fine_dly_dec_done,\n dqs_po_dec_done,\n tempmon_sel_pi_incdec,\n byte_sel_cnt,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[1] ,\n init_calib_complete_reg,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ,\n cmd_delay_start0,\n rstdiv0_sync_r1_reg_rep__24,\n fine_adjust_reg_0,\n rstdiv0_sync_r1_reg_rep__2,\n rstdiv0_sync_r1_reg_rep__19,\n prech_done);\n output init_dqsfound_done_r2;\n output init_dqsfound_done_r5;\n output [3:0]out;\n output [0:0]pi_dqs_found_any_bank;\n output pi_dqs_found_rank_done;\n output rd_data_offset_cal_done;\n output rst_dqs_find_r1_reg_0;\n output pi_dqs_found_done_r1_reg;\n output \\pi_rst_stg1_cal_r_reg[0]_0 ;\n output fine_adjust_done_r_reg_0;\n output init_dec_done_reg_0;\n output final_dec_done_reg_0;\n output dqs_found_prech_req;\n output ck_po_stg2_f_indec;\n output ck_po_stg2_f_en;\n output [0:0]\\pi_dqs_found_all_bank_r_reg[1]_0 ;\n output D_po_fine_enable107_out;\n output D_po_fine_inc113_out;\n output \\po_counter_read_val_reg[8] ;\n output \\po_counter_read_val_reg[8]_0 ;\n output \\po_counter_read_val_reg[8]_1 ;\n output \\po_counter_read_val_reg[8]_2 ;\n output \\po_counter_read_val_reg[8]_3 ;\n output \\po_counter_read_val_reg[8]_4 ;\n output \\gen_byte_sel_div1.calib_in_common_reg ;\n output \\po_counter_read_val_reg[8]_5 ;\n output \\po_counter_read_val_reg[8]_6 ;\n output ififo_rst_reg;\n output \\po_counter_read_val_reg[8]_7 ;\n output \\po_counter_read_val_reg[8]_8 ;\n output ififo_rst_reg_0;\n output \\po_counter_read_val_reg[8]_9 ;\n output \\po_counter_read_val_reg[8]_10 ;\n output ififo_rst_reg_1;\n output \\po_counter_read_val_reg[8]_11 ;\n output \\po_counter_read_val_reg[8]_12 ;\n output ififo_rst_reg_2;\n output fine_adj_state_r144_out;\n output \\FSM_sequential_fine_adj_state_r_reg[2]_0 ;\n output \\dec_cnt_reg[0]_0 ;\n output [3:0]\\FSM_sequential_fine_adj_state_r_reg[0]_0 ;\n output [1:0]\\rd_byte_data_offset_reg[0][9]_0 ;\n output \\cmd_pipe_plus.mc_data_offset_reg[4] ;\n output [5:0]\\cmd_pipe_plus.mc_data_offset_reg[5] ;\n output \\cmd_pipe_plus.mc_data_offset_reg[1] ;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[4] ;\n output [5:0]\\cmd_pipe_plus.mc_data_offset_1_reg[5] ;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[1] ;\n output \\cmd_pipe_plus.mc_data_offset_reg[0] ;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[0] ;\n output \\rd_byte_data_offset_reg[0]_3 ;\n output p_1_in27_in;\n output [1:0]\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 ;\n output p_1_in50_in;\n output \\pi_rst_stg1_cal_r_reg[0]_1 ;\n output fine_adj_state_r16_out;\n output dqs_found_prech_req_reg_0;\n output final_dec_done_reg_1;\n output \\FSM_sequential_fine_adj_state_r_reg[0]_1 ;\n output [1:0]\\rank_final_loop[0].final_do_max_reg[0][3]_0 ;\n output [1:0]\\rank_final_loop[0].final_do_max_reg[0][3]_1 ;\n output \\init_state_r_reg[1] ;\n output \\init_state_r_reg[2] ;\n output \\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ;\n output \\init_state_r_reg[1]_0 ;\n output \\init_state_r_reg[1]_1 ;\n output \\calib_data_offset_0_reg[5] ;\n output \\calib_data_offset_0_reg[4] ;\n output \\calib_data_offset_0_reg[1] ;\n output \\calib_data_offset_0_reg[0] ;\n output \\calib_data_offset_1_reg[5] ;\n output \\calib_data_offset_1_reg[4] ;\n output \\calib_data_offset_1_reg[1] ;\n output \\calib_data_offset_1_reg[0] ;\n output \\gen_byte_sel_div1.ctl_lane_sel_reg[0] ;\n output ctl_lane_sel;\n output \\gen_byte_sel_div1.ctl_lane_sel_reg[1] ;\n output \\gen_byte_sel_div1.ctl_lane_sel_reg[2] ;\n output \\calib_zero_inputs_reg[1] ;\n output [1:0]D;\n output [0:0]\\calib_zero_inputs_reg[0] ;\n output \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ;\n output [1:0]rank_done_r_reg_0;\n output rst_dqs_find_reg_0;\n output dqs_found_prech_req_reg_1;\n output rst_dqs_find_reg_1;\n output init_dec_done_reg_1;\n output rst_dqs_find;\n input CLK;\n input [3:0]in0;\n input pi_dqs_found_start_reg;\n input [0:0]rstdiv0_sync_r1_reg_rep__12;\n input [0:0]SR;\n input rstdiv0_sync_r1_reg_rep__13;\n input \\pi_dqs_found_lanes_r3_reg[3]_0 ;\n input \\pi_dqs_found_all_bank_r_reg[1]_1 ;\n input init_dqsfound_done_r_reg_0;\n input \\FSM_sequential_fine_adj_state_r_reg[0]_2 ;\n input \\FSM_sequential_fine_adj_state_r_reg[1]_0 ;\n input \\FSM_sequential_fine_adj_state_r_reg[0]_3 ;\n input init_dec_done_reg_2;\n input \\FSM_sequential_fine_adj_state_r_reg[1]_1 ;\n input \\FSM_sequential_fine_adj_state_r_reg[2]_1 ;\n input \\FSM_sequential_fine_adj_state_r_reg[1]_2 ;\n input \\FSM_sequential_fine_adj_state_r_reg[1]_3 ;\n input pi_dqs_found_start_reg_0;\n input [1:0]Q;\n input calib_in_common;\n input [0:0]po_enstg2_f;\n input [1:0]\\calib_zero_inputs_reg[1]_0 ;\n input [0:0]po_stg2_fincdec;\n input pi_calib_done;\n input oclkdelay_calib_done_r_reg;\n input pi_f_inc_reg;\n input \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n input dqs_po_stg2_f_incdec;\n input po_stg23_incdec;\n input dqs_po_en_stg2_f;\n input po_en_stg2_f;\n input po_en_stg23;\n input \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n input \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n input \\gen_byte_sel_div1.calib_in_common_reg_3 ;\n input wrcal_done_reg;\n input rdlvl_stg1_done_int_reg;\n input prbs_rdlvl_done_reg_rep;\n input rstdiv0_sync_r1_reg_rep__23;\n input detect_pi_found_dqs;\n input \\num_refresh_reg[1] ;\n input oclkdelay_calib_done_r_reg_0;\n input mpr_rdlvl_done_r_reg;\n input cnt_cmd_done_r;\n input prbs_last_byte_done_r;\n input wrlvl_byte_redo;\n input wrlvl_done_r1;\n input oclkdelay_center_calib_done_r_reg;\n input wrlvl_final_mux;\n input pi_dqs_found_done_r1;\n input ck_addr_cmd_delay_done;\n input [2:0]ctl_lane_cnt;\n input \\gen_byte_sel_div1.ctl_lane_sel_reg[0]_0 ;\n input \\gen_byte_sel_div1.ctl_lane_sel_reg[1]_0 ;\n input \\gen_byte_sel_div1.ctl_lane_sel_reg[2]_0 ;\n input pi_fine_dly_dec_done;\n input dqs_po_dec_done;\n input tempmon_sel_pi_incdec;\n input [0:0]byte_sel_cnt;\n input \\gen_byte_sel_div1.byte_sel_cnt_reg[1] ;\n input init_calib_complete_reg;\n input \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ;\n input cmd_delay_start0;\n input rstdiv0_sync_r1_reg_rep__24;\n input fine_adjust_reg_0;\n input rstdiv0_sync_r1_reg_rep__2;\n input [0:0]rstdiv0_sync_r1_reg_rep__19;\n input prech_done;\n\n wire CLK;\n wire [1:0]D;\n wire D_po_fine_enable107_out;\n wire D_po_fine_inc113_out;\n wire \\FSM_sequential_fine_adj_state_r[0]_i_1_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r[0]_i_4_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r[0]_i_5_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r[1]_i_2_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r[1]_i_3_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r[1]_i_5_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r[2]_i_1_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r[2]_i_2_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r[2]_i_4_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r[3]_i_1_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r[3]_i_2_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r[3]_i_3_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r[3]_i_4_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r[3]_i_5_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r[3]_i_6_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r[3]_i_8_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r[3]_i_9_n_0 ;\n (* RTL_KEEP = \"yes\" *) wire [3:0]\\FSM_sequential_fine_adj_state_r_reg[0]_0 ;\n wire \\FSM_sequential_fine_adj_state_r_reg[0]_1 ;\n wire \\FSM_sequential_fine_adj_state_r_reg[0]_2 ;\n wire \\FSM_sequential_fine_adj_state_r_reg[0]_3 ;\n wire \\FSM_sequential_fine_adj_state_r_reg[0]_i_3_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r_reg[1]_0 ;\n wire \\FSM_sequential_fine_adj_state_r_reg[1]_1 ;\n wire \\FSM_sequential_fine_adj_state_r_reg[1]_2 ;\n wire \\FSM_sequential_fine_adj_state_r_reg[1]_3 ;\n wire \\FSM_sequential_fine_adj_state_r_reg[1]_i_1_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r_reg[2]_0 ;\n wire \\FSM_sequential_fine_adj_state_r_reg[2]_1 ;\n wire [1:0]Q;\n wire [0:0]SR;\n wire [0:0]byte_sel_cnt;\n wire \\calib_data_offset_0_reg[0] ;\n wire \\calib_data_offset_0_reg[1] ;\n wire \\calib_data_offset_0_reg[4] ;\n wire \\calib_data_offset_0_reg[5] ;\n wire \\calib_data_offset_1_reg[0] ;\n wire \\calib_data_offset_1_reg[1] ;\n wire \\calib_data_offset_1_reg[4] ;\n wire \\calib_data_offset_1_reg[5] ;\n wire calib_in_common;\n wire [0:0]\\calib_zero_inputs_reg[0] ;\n wire \\calib_zero_inputs_reg[1] ;\n wire [1:0]\\calib_zero_inputs_reg[1]_0 ;\n wire ck_addr_cmd_delay_done;\n wire ck_po_stg2_f_en;\n wire ck_po_stg2_f_indec;\n wire cmd_delay_start0;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[0] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[1] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[4] ;\n wire [5:0]\\cmd_pipe_plus.mc_data_offset_1_reg[5] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[0] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[1] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[4] ;\n wire [5:0]\\cmd_pipe_plus.mc_data_offset_reg[5] ;\n wire cnt_cmd_done_r;\n wire [2:0]ctl_lane_cnt;\n wire ctl_lane_cnt_0;\n wire [3:0]ctl_lane_cnt__0;\n wire \\ctl_lane_cnt_reg_n_0_[3] ;\n wire ctl_lane_sel;\n wire [5:0]dec_cnt;\n wire \\dec_cnt[0]_i_2_n_0 ;\n wire \\dec_cnt[0]_i_4_n_0 ;\n wire \\dec_cnt[0]_i_5_n_0 ;\n wire \\dec_cnt[0]_i_6_n_0 ;\n wire \\dec_cnt[0]_i_7_n_0 ;\n wire \\dec_cnt[1]_i_2_n_0 ;\n wire \\dec_cnt[1]_i_3_n_0 ;\n wire \\dec_cnt[1]_i_4_n_0 ;\n wire \\dec_cnt[2]_i_2_n_0 ;\n wire \\dec_cnt[2]_i_3_n_0 ;\n wire \\dec_cnt[2]_i_4_n_0 ;\n wire \\dec_cnt[3]_i_2_n_0 ;\n wire \\dec_cnt[3]_i_3_n_0 ;\n wire \\dec_cnt[3]_i_4_n_0 ;\n wire \\dec_cnt[4]_i_2_n_0 ;\n wire \\dec_cnt[4]_i_3_n_0 ;\n wire \\dec_cnt[4]_i_5_n_0 ;\n wire \\dec_cnt[4]_i_6_n_0 ;\n wire \\dec_cnt[4]_i_7_n_0 ;\n wire \\dec_cnt[5]_i_10_n_0 ;\n wire \\dec_cnt[5]_i_1_n_0 ;\n wire \\dec_cnt[5]_i_3_n_0 ;\n wire \\dec_cnt[5]_i_4_n_0 ;\n wire \\dec_cnt[5]_i_6_n_0 ;\n wire \\dec_cnt[5]_i_7_n_0 ;\n wire \\dec_cnt[5]_i_8_n_0 ;\n wire \\dec_cnt[5]_i_9_n_0 ;\n wire \\dec_cnt_reg[0]_0 ;\n wire \\dec_cnt_reg[0]_i_3_n_0 ;\n wire \\dec_cnt_reg[0]_i_3_n_1 ;\n wire \\dec_cnt_reg[0]_i_3_n_2 ;\n wire \\dec_cnt_reg[0]_i_3_n_3 ;\n wire \\dec_cnt_reg[0]_i_3_n_4 ;\n wire \\dec_cnt_reg[0]_i_3_n_5 ;\n wire \\dec_cnt_reg[0]_i_3_n_6 ;\n wire \\dec_cnt_reg[4]_i_4_n_3 ;\n wire \\dec_cnt_reg[4]_i_4_n_6 ;\n wire \\dec_cnt_reg[4]_i_4_n_7 ;\n wire \\dec_cnt_reg_n_0_[0] ;\n wire \\dec_cnt_reg_n_0_[1] ;\n wire \\dec_cnt_reg_n_0_[2] ;\n wire \\dec_cnt_reg_n_0_[3] ;\n wire \\dec_cnt_reg_n_0_[4] ;\n wire \\dec_cnt_reg_n_0_[5] ;\n wire detect_pi_found_dqs;\n wire detect_rd_cnt0;\n wire [3:0]detect_rd_cnt0__0;\n wire \\detect_rd_cnt[1]_i_1_n_0 ;\n wire \\detect_rd_cnt[3]_i_1_n_0 ;\n wire [3:0]detect_rd_cnt_reg__0;\n wire dqs_found_done_r0;\n wire dqs_found_done_r_i_3_n_0;\n wire dqs_found_prech_req;\n wire dqs_found_prech_req_i_5_n_0;\n wire dqs_found_prech_req_reg_0;\n wire dqs_found_prech_req_reg_1;\n wire dqs_found_start_r;\n wire dqs_po_dec_done;\n wire dqs_po_en_stg2_f;\n wire dqs_po_stg2_f_incdec;\n wire final_data_offset;\n wire final_data_offset_mc;\n wire final_dec_done_reg_0;\n wire final_dec_done_reg_1;\n wire fine_adj_state_r110_out;\n wire fine_adj_state_r134_out;\n wire fine_adj_state_r141_out;\n wire fine_adj_state_r144_out;\n wire fine_adj_state_r167_out;\n wire fine_adj_state_r16_out;\n wire fine_adj_state_r17_out;\n wire fine_adjust_done_r_reg_0;\n wire [2:0]fine_adjust_lane_cnt;\n wire fine_adjust_reg_0;\n wire first_fail_detect;\n wire first_fail_detect_i_1_n_0;\n wire first_fail_detect_i_2_n_0;\n wire first_fail_detect_reg_n_0;\n wire \\first_fail_taps[0]_i_1_n_0 ;\n wire \\first_fail_taps[1]_i_1_n_0 ;\n wire \\first_fail_taps[2]_i_1_n_0 ;\n wire \\first_fail_taps[3]_i_1_n_0 ;\n wire \\first_fail_taps[4]_i_1_n_0 ;\n wire \\first_fail_taps[5]_i_2_n_0 ;\n wire \\first_fail_taps[5]_i_4_n_0 ;\n wire \\first_fail_taps[5]_i_5_n_0 ;\n wire \\first_fail_taps[5]_i_6_n_0 ;\n wire \\first_fail_taps[5]_i_7_n_0 ;\n wire \\first_fail_taps_reg_n_0_[0] ;\n wire \\first_fail_taps_reg_n_0_[1] ;\n wire \\first_fail_taps_reg_n_0_[2] ;\n wire \\first_fail_taps_reg_n_0_[3] ;\n wire \\first_fail_taps_reg_n_0_[4] ;\n wire \\first_fail_taps_reg_n_0_[5] ;\n wire \\gen_byte_sel_div1.byte_sel_cnt[2]_i_9_n_0 ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[1] ;\n wire \\gen_byte_sel_div1.calib_in_common_i_2_n_0 ;\n wire \\gen_byte_sel_div1.calib_in_common_i_5_n_0 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_3 ;\n wire \\gen_byte_sel_div1.ctl_lane_sel[2]_i_2_n_0 ;\n wire \\gen_byte_sel_div1.ctl_lane_sel_reg[0] ;\n wire \\gen_byte_sel_div1.ctl_lane_sel_reg[0]_0 ;\n wire \\gen_byte_sel_div1.ctl_lane_sel_reg[1] ;\n wire \\gen_byte_sel_div1.ctl_lane_sel_reg[1]_0 ;\n wire \\gen_byte_sel_div1.ctl_lane_sel_reg[2] ;\n wire \\gen_byte_sel_div1.ctl_lane_sel_reg[2]_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ;\n wire ififo_rst_reg;\n wire ififo_rst_reg_0;\n wire ififo_rst_reg_1;\n wire ififo_rst_reg_2;\n wire [3:0]in0;\n wire inc_cnt;\n wire \\inc_cnt[4]_i_1_n_0 ;\n wire \\inc_cnt_reg_n_0_[0] ;\n wire \\inc_cnt_reg_n_0_[1] ;\n wire \\inc_cnt_reg_n_0_[2] ;\n wire \\inc_cnt_reg_n_0_[3] ;\n wire \\inc_cnt_reg_n_0_[4] ;\n wire \\inc_cnt_reg_n_0_[5] ;\n wire init_calib_complete_reg;\n wire init_dec_cnt;\n wire [5:0]init_dec_cnt0;\n wire \\init_dec_cnt[1]_i_1_n_0 ;\n wire [5:0]init_dec_cnt_reg__0;\n wire init_dec_done_reg_0;\n wire init_dec_done_reg_1;\n wire init_dec_done_reg_2;\n wire init_dqsfound_done_r1_reg_n_0;\n wire init_dqsfound_done_r2;\n wire init_dqsfound_done_r4_reg_srl2_n_0;\n wire init_dqsfound_done_r5;\n wire init_dqsfound_done_r_reg_0;\n wire \\init_state_r[1]_i_29_n_0 ;\n wire \\init_state_r[1]_i_30_n_0 ;\n wire \\init_state_r_reg[1] ;\n wire \\init_state_r_reg[1]_0 ;\n wire \\init_state_r_reg[1]_1 ;\n wire \\init_state_r_reg[2] ;\n wire mpr_rdlvl_done_r_reg;\n wire n_0_0;\n wire n_0_1;\n wire n_0_2;\n wire n_0_3;\n wire \\num_refresh_reg[1] ;\n wire oclkdelay_calib_done_r_reg;\n wire oclkdelay_calib_done_r_reg_0;\n wire oclkdelay_center_calib_done_r_reg;\n wire [5:0]p_0_in;\n wire p_0_in19_in;\n wire [5:0]p_0_in__0;\n wire [4:0]p_0_in__1;\n wire [5:0]p_1_in;\n wire p_1_in27_in;\n wire p_1_in50_in;\n wire p_22_out;\n wire pi_calib_done;\n wire [0:0]pi_dqs_found_all_bank;\n wire \\pi_dqs_found_all_bank[0]_i_1_n_0 ;\n wire [0:0]\\pi_dqs_found_all_bank_r_reg[1]_0 ;\n wire \\pi_dqs_found_all_bank_r_reg[1]_1 ;\n wire [0:0]pi_dqs_found_any_bank;\n wire \\pi_dqs_found_any_bank_r_reg_n_0_[0] ;\n wire pi_dqs_found_done_r1;\n wire pi_dqs_found_done_r1_reg;\n (* async_reg = \"true\" *) wire [7:0]pi_dqs_found_lanes_r1;\n (* async_reg = \"true\" *) wire [7:0]pi_dqs_found_lanes_r2;\n (* async_reg = \"true\" *) wire [7:0]pi_dqs_found_lanes_r3;\n wire \\pi_dqs_found_lanes_r3_reg[3]_0 ;\n wire pi_dqs_found_rank_done;\n wire pi_dqs_found_start_reg;\n wire pi_dqs_found_start_reg_0;\n wire pi_f_inc_reg;\n wire pi_fine_dly_dec_done;\n wire \\pi_rst_stg1_cal[0]_i_1_n_0 ;\n wire \\pi_rst_stg1_cal[1]_i_1_n_0 ;\n wire pi_rst_stg1_cal_r1_reg0;\n wire pi_rst_stg1_cal_r1_reg017_out;\n wire \\pi_rst_stg1_cal_r1_reg_n_0_[0] ;\n wire \\pi_rst_stg1_cal_r[0]_i_1_n_0 ;\n wire \\pi_rst_stg1_cal_r[0]_i_2_n_0 ;\n wire \\pi_rst_stg1_cal_r[0]_i_3_n_0 ;\n wire \\pi_rst_stg1_cal_r[1]_i_1_n_0 ;\n wire \\pi_rst_stg1_cal_r[1]_i_2_n_0 ;\n wire \\pi_rst_stg1_cal_r_reg[0]_0 ;\n wire \\pi_rst_stg1_cal_r_reg[0]_1 ;\n wire \\pi_rst_stg1_cal_reg_n_0_[1] ;\n wire \\po_counter_read_val_reg[8] ;\n wire \\po_counter_read_val_reg[8]_0 ;\n wire \\po_counter_read_val_reg[8]_1 ;\n wire \\po_counter_read_val_reg[8]_10 ;\n wire \\po_counter_read_val_reg[8]_11 ;\n wire \\po_counter_read_val_reg[8]_12 ;\n wire \\po_counter_read_val_reg[8]_2 ;\n wire \\po_counter_read_val_reg[8]_3 ;\n wire \\po_counter_read_val_reg[8]_4 ;\n wire \\po_counter_read_val_reg[8]_5 ;\n wire \\po_counter_read_val_reg[8]_6 ;\n wire \\po_counter_read_val_reg[8]_7 ;\n wire \\po_counter_read_val_reg[8]_8 ;\n wire \\po_counter_read_val_reg[8]_9 ;\n wire po_en_stg23;\n wire po_en_stg2_f;\n wire [0:0]po_enstg2_f;\n wire po_stg23_incdec;\n wire [0:0]po_stg2_fincdec;\n wire prbs_last_byte_done_r;\n wire prbs_rdlvl_done_reg_rep;\n wire prech_done;\n wire rank_done_r1;\n wire [1:0]rank_done_r_reg_0;\n wire \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0 ;\n wire \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1_n_0 ;\n wire \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1_n_0 ;\n wire \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1_n_0 ;\n wire \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1_n_0 ;\n wire \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2_n_0 ;\n wire [1:0]\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 ;\n wire \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ;\n wire \\rank_final_loop[0].final_do_index[0][0]_i_1_n_0 ;\n wire \\rank_final_loop[0].final_do_index[0][1]_i_1_n_0 ;\n wire \\rank_final_loop[0].final_do_index[0][2]_i_1_n_0 ;\n wire \\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ;\n wire \\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ;\n wire \\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ;\n wire \\rank_final_loop[0].final_do_max[0][0]_i_1_n_0 ;\n wire \\rank_final_loop[0].final_do_max[0][1]_i_1_n_0 ;\n wire \\rank_final_loop[0].final_do_max[0][2]_i_1_n_0 ;\n wire \\rank_final_loop[0].final_do_max[0][2]_i_2_n_0 ;\n wire \\rank_final_loop[0].final_do_max[0][3]_i_1_n_0 ;\n wire \\rank_final_loop[0].final_do_max[0][3]_i_2_n_0 ;\n wire \\rank_final_loop[0].final_do_max[0][4]_i_1_n_0 ;\n wire \\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ;\n wire \\rank_final_loop[0].final_do_max[0][5]_i_2_n_0 ;\n wire \\rank_final_loop[0].final_do_max[0][5]_i_3_n_0 ;\n wire \\rank_final_loop[0].final_do_max[0][5]_i_4_n_0 ;\n wire \\rank_final_loop[0].final_do_max[0][5]_i_5_n_0 ;\n wire \\rank_final_loop[0].final_do_max[0][5]_i_6_n_0 ;\n wire \\rank_final_loop[0].final_do_max[0][5]_i_7_n_0 ;\n wire \\rank_final_loop[0].final_do_max[0][5]_i_8_n_0 ;\n wire \\rank_final_loop[0].final_do_max[0][5]_i_9_n_0 ;\n wire [1:0]\\rank_final_loop[0].final_do_max_reg[0][3]_0 ;\n wire [1:0]\\rank_final_loop[0].final_do_max_reg[0][3]_1 ;\n wire [5:0]\\rank_final_loop[0].final_do_max_reg[0]__0 ;\n wire rd_byte_data_offset;\n wire \\rd_byte_data_offset[0][11]_i_1_n_0 ;\n wire \\rd_byte_data_offset[0][11]_i_2_n_0 ;\n wire \\rd_byte_data_offset[0][11]_i_4_n_0 ;\n wire \\rd_byte_data_offset[0][5]_i_1_n_0 ;\n wire \\rd_byte_data_offset[0][5]_i_3_n_0 ;\n wire \\rd_byte_data_offset[0][5]_i_4_n_0 ;\n wire \\rd_byte_data_offset[0][7]_i_1_n_0 ;\n wire [1:0]\\rd_byte_data_offset_reg[0][9]_0 ;\n wire \\rd_byte_data_offset_reg[0]_3 ;\n wire \\rd_byte_data_offset_reg_n_0_[0][0] ;\n wire \\rd_byte_data_offset_reg_n_0_[0][1] ;\n wire \\rd_byte_data_offset_reg_n_0_[0][4] ;\n wire \\rd_byte_data_offset_reg_n_0_[0][5] ;\n wire rd_data_offset_cal_done;\n wire [5:0]rd_data_offset_ranks_0;\n wire [5:0]rd_data_offset_ranks_1;\n wire rdlvl_stg1_done_int_reg;\n wire \\rnk_cnt_r[0]_i_1_n_0 ;\n wire \\rnk_cnt_r[1]_i_1_n_0 ;\n wire \\rnk_cnt_r_reg_n_0_[0] ;\n wire \\rnk_cnt_r_reg_n_0_[1] ;\n wire rst_dqs_find;\n wire rst_dqs_find_i_5_n_0;\n wire rst_dqs_find_i_6_n_0;\n wire rst_dqs_find_r1;\n wire rst_dqs_find_r1_reg_0;\n wire rst_dqs_find_r2;\n wire rst_dqs_find_reg_0;\n wire rst_dqs_find_reg_1;\n wire [0:0]rst_stg1_cal;\n wire [0:0]rstdiv0_sync_r1_reg_rep__12;\n wire rstdiv0_sync_r1_reg_rep__13;\n wire [0:0]rstdiv0_sync_r1_reg_rep__19;\n wire rstdiv0_sync_r1_reg_rep__2;\n wire rstdiv0_sync_r1_reg_rep__23;\n wire rstdiv0_sync_r1_reg_rep__24;\n wire stable_pass_cnt;\n wire \\stable_pass_cnt[3]_i_1_n_0 ;\n wire \\stable_pass_cnt[5]_i_2_n_0 ;\n wire \\stable_pass_cnt[5]_i_3_n_0 ;\n wire [5:1]stable_pass_cnt_reg__0;\n wire \\stable_pass_cnt_reg_n_0_[0] ;\n wire tempmon_sel_pi_incdec;\n wire wrcal_done_reg;\n wire wrlvl_byte_redo;\n wire wrlvl_done_r1;\n wire wrlvl_final_mux;\n wire [0:0]\\NLW_dec_cnt_reg[0]_i_3_O_UNCONNECTED ;\n wire [3:1]\\NLW_dec_cnt_reg[4]_i_4_CO_UNCONNECTED ;\n wire [3:2]\\NLW_dec_cnt_reg[4]_i_4_O_UNCONNECTED ;\n\n assign out[3:0] = pi_dqs_found_lanes_r3[3:0];\n LUT6 #(\n .INIT(64'hF3B0FFFFF3B00000)) \n \\FSM_sequential_fine_adj_state_r[0]_i_1 \n (.I0(\\FSM_sequential_fine_adj_state_r_reg[0]_1 ),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .I3(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .I4(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]),\n .I5(\\FSM_sequential_fine_adj_state_r_reg[0]_i_3_n_0 ),\n .O(\\FSM_sequential_fine_adj_state_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair270\" *) \n LUT4 #(\n .INIT(16'h0008)) \n \\FSM_sequential_fine_adj_state_r[0]_i_2 \n (.I0(fine_adjust_lane_cnt[1]),\n .I1(fine_adjust_lane_cnt[0]),\n .I2(\\ctl_lane_cnt_reg_n_0_[3] ),\n .I3(fine_adjust_lane_cnt[2]),\n .O(\\FSM_sequential_fine_adj_state_r_reg[0]_1 ));\n LUT5 #(\n .INIT(32'hA8AAFFFF)) \n \\FSM_sequential_fine_adj_state_r[0]_i_4 \n (.I0(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .I1(\\dec_cnt_reg[0]_0 ),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[2]_0 ),\n .I3(\\FSM_sequential_fine_adj_state_r_reg[0]_1 ),\n .I4(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .O(\\FSM_sequential_fine_adj_state_r[0]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'hCCCC7477)) \n \\FSM_sequential_fine_adj_state_r[0]_i_5 \n (.I0(fine_adj_state_r167_out),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[2]_0 ),\n .I3(final_dec_done_reg_0),\n .I4(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .O(\\FSM_sequential_fine_adj_state_r[0]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFAFF0AFF030F030)) \n \\FSM_sequential_fine_adj_state_r[1]_i_2 \n (.I0(fine_adj_state_r167_out),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[2]_0 ),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I3(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .I4(\\FSM_sequential_fine_adj_state_r[1]_i_5_n_0 ),\n .I5(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .O(\\FSM_sequential_fine_adj_state_r[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FFEA00EA)) \n \\FSM_sequential_fine_adj_state_r[1]_i_3 \n (.I0(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .I1(pi_dqs_found_all_bank),\n .I2(\\pi_dqs_found_all_bank_r_reg[1]_0 ),\n .I3(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .I4(\\FSM_sequential_fine_adj_state_r[3]_i_6_n_0 ),\n .I5(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .O(\\FSM_sequential_fine_adj_state_r[1]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair267\" *) \n LUT5 #(\n .INIT(32'h00000040)) \n \\FSM_sequential_fine_adj_state_r[1]_i_4 \n (.I0(detect_rd_cnt_reg__0[1]),\n .I1(detect_rd_cnt_reg__0[0]),\n .I2(detect_pi_found_dqs),\n .I3(detect_rd_cnt_reg__0[2]),\n .I4(detect_rd_cnt_reg__0[3]),\n .O(fine_adj_state_r167_out));\n LUT6 #(\n .INIT(64'h0000000000001000)) \n \\FSM_sequential_fine_adj_state_r[1]_i_5 \n (.I0(fine_adjust_lane_cnt[2]),\n .I1(\\ctl_lane_cnt_reg_n_0_[3] ),\n .I2(fine_adjust_lane_cnt[0]),\n .I3(fine_adjust_lane_cnt[1]),\n .I4(\\dec_cnt_reg[0]_0 ),\n .I5(\\FSM_sequential_fine_adj_state_r_reg[2]_0 ),\n .O(\\FSM_sequential_fine_adj_state_r[1]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h0033CCBB33FFFC00)) \n \\FSM_sequential_fine_adj_state_r[2]_i_1 \n (.I0(\\FSM_sequential_fine_adj_state_r[2]_i_2_n_0 ),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[2]_0 ),\n .I3(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I4(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .I5(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .O(\\FSM_sequential_fine_adj_state_r[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hC8FF40FF88FF0000)) \n \\FSM_sequential_fine_adj_state_r[2]_i_2 \n (.I0(\\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ),\n .I1(\\FSM_sequential_fine_adj_state_r[2]_i_4_n_0 ),\n .I2(fine_adj_state_r134_out),\n .I3(fine_adj_state_r144_out),\n .I4(fine_adj_state_r110_out),\n .I5(fine_adj_state_r17_out),\n .O(\\FSM_sequential_fine_adj_state_r[2]_i_2_n_0 ));\n LUT3 #(\n .INIT(8'h8F)) \n \\FSM_sequential_fine_adj_state_r[2]_i_3 \n (.I0(\\first_fail_taps[5]_i_5_n_0 ),\n .I1(\\first_fail_taps[5]_i_7_n_0 ),\n .I2(first_fail_detect_reg_n_0),\n .O(\\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ));\n LUT3 #(\n .INIT(8'h54)) \n \\FSM_sequential_fine_adj_state_r[2]_i_4 \n (.I0(fine_adj_state_r141_out),\n .I1(first_fail_detect_i_2_n_0),\n .I2(first_fail_detect_reg_n_0),\n .O(\\FSM_sequential_fine_adj_state_r[2]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h0000BF00)) \n \\FSM_sequential_fine_adj_state_r[2]_i_5 \n (.I0(\\first_fail_taps[5]_i_6_n_0 ),\n .I1(\\inc_cnt_reg_n_0_[0] ),\n .I2(\\inc_cnt_reg_n_0_[4] ),\n .I3(\\first_fail_taps[5]_i_5_n_0 ),\n .I4(\\first_fail_taps[5]_i_7_n_0 ),\n .O(fine_adj_state_r134_out));\n LUT6 #(\n .INIT(64'h0000000000101000)) \n \\FSM_sequential_fine_adj_state_r[2]_i_6 \n (.I0(\\inc_cnt_reg_n_0_[0] ),\n .I1(\\inc_cnt_reg_n_0_[1] ),\n .I2(\\inc_cnt_reg_n_0_[3] ),\n .I3(\\inc_cnt_reg_n_0_[2] ),\n .I4(\\inc_cnt_reg_n_0_[4] ),\n .I5(\\inc_cnt_reg_n_0_[5] ),\n .O(fine_adj_state_r110_out));\n LUT6 #(\n .INIT(64'h0000008000000028)) \n \\FSM_sequential_fine_adj_state_r[2]_i_7 \n (.I0(\\inc_cnt_reg_n_0_[5] ),\n .I1(\\inc_cnt_reg_n_0_[4] ),\n .I2(\\inc_cnt_reg_n_0_[2] ),\n .I3(\\inc_cnt_reg_n_0_[0] ),\n .I4(\\inc_cnt_reg_n_0_[1] ),\n .I5(\\inc_cnt_reg_n_0_[3] ),\n .O(fine_adj_state_r17_out));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\FSM_sequential_fine_adj_state_r[3]_i_1 \n (.I0(\\FSM_sequential_fine_adj_state_r[3]_i_3_n_0 ),\n .I1(detect_pi_found_dqs),\n .I2(\\FSM_sequential_fine_adj_state_r[3]_i_4_n_0 ),\n .I3(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]),\n .I4(\\FSM_sequential_fine_adj_state_r[3]_i_5_n_0 ),\n .O(\\FSM_sequential_fine_adj_state_r[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h33BBFF88CC003000)) \n \\FSM_sequential_fine_adj_state_r[3]_i_2 \n (.I0(\\FSM_sequential_fine_adj_state_r[3]_i_6_n_0 ),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[2]_0 ),\n .I3(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I4(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .I5(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .O(\\FSM_sequential_fine_adj_state_r[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hBFBFBFBFFFFCFCFC)) \n \\FSM_sequential_fine_adj_state_r[3]_i_3 \n (.I0(prech_done),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .I3(pi_dqs_found_all_bank),\n .I4(\\pi_dqs_found_all_bank_r_reg[1]_0 ),\n .I5(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .O(\\FSM_sequential_fine_adj_state_r[3]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hBFBFBFBFCFCCCCCC)) \n \\FSM_sequential_fine_adj_state_r[3]_i_4 \n (.I0(prech_done),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .I3(\\pi_dqs_found_all_bank_r_reg[1]_0 ),\n .I4(pi_dqs_found_all_bank),\n .I5(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .O(\\FSM_sequential_fine_adj_state_r[3]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFF4FFFFFFF40)) \n \\FSM_sequential_fine_adj_state_r[3]_i_5 \n (.I0(pi_dqs_found_any_bank),\n .I1(rst_dqs_find_r2),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I3(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .I4(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .I5(init_dqsfound_done_r5),\n .O(\\FSM_sequential_fine_adj_state_r[3]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'h0000FD0D)) \n \\FSM_sequential_fine_adj_state_r[3]_i_6 \n (.I0(first_fail_detect_i_2_n_0),\n .I1(fine_adj_state_r16_out),\n .I2(fine_adj_state_r144_out),\n .I3(\\FSM_sequential_fine_adj_state_r[3]_i_8_n_0 ),\n .I4(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .O(\\FSM_sequential_fine_adj_state_r[3]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\FSM_sequential_fine_adj_state_r[3]_i_7 \n (.I0(init_dec_cnt_reg__0[5]),\n .I1(init_dec_cnt_reg__0[3]),\n .I2(init_dec_cnt_reg__0[0]),\n .I3(init_dec_cnt_reg__0[1]),\n .I4(init_dec_cnt_reg__0[2]),\n .I5(init_dec_cnt_reg__0[4]),\n .O(\\FSM_sequential_fine_adj_state_r_reg[2]_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFB8FFFFFFBB)) \n \\FSM_sequential_fine_adj_state_r[3]_i_8 \n (.I0(fine_adj_state_r110_out),\n .I1(\\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ),\n .I2(fine_adj_state_r17_out),\n .I3(fine_adj_state_r141_out),\n .I4(\\FSM_sequential_fine_adj_state_r[3]_i_9_n_0 ),\n .I5(fine_adj_state_r134_out),\n .O(\\FSM_sequential_fine_adj_state_r[3]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h1)) \n \\FSM_sequential_fine_adj_state_r[3]_i_9 \n (.I0(first_fail_detect_reg_n_0),\n .I1(first_fail_detect_i_2_n_0),\n .O(\\FSM_sequential_fine_adj_state_r[3]_i_9_n_0 ));\n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\FSM_sequential_fine_adj_state_r_reg[0] \n (.C(CLK),\n .CE(\\FSM_sequential_fine_adj_state_r[3]_i_1_n_0 ),\n .D(\\FSM_sequential_fine_adj_state_r[0]_i_1_n_0 ),\n .Q(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n MUXF7 \\FSM_sequential_fine_adj_state_r_reg[0]_i_3 \n (.I0(\\FSM_sequential_fine_adj_state_r[0]_i_4_n_0 ),\n .I1(\\FSM_sequential_fine_adj_state_r[0]_i_5_n_0 ),\n .O(\\FSM_sequential_fine_adj_state_r_reg[0]_i_3_n_0 ),\n .S(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]));\n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\FSM_sequential_fine_adj_state_r_reg[1] \n (.C(CLK),\n .CE(\\FSM_sequential_fine_adj_state_r[3]_i_1_n_0 ),\n .D(\\FSM_sequential_fine_adj_state_r_reg[1]_i_1_n_0 ),\n .Q(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n MUXF7 \\FSM_sequential_fine_adj_state_r_reg[1]_i_1 \n (.I0(\\FSM_sequential_fine_adj_state_r[1]_i_2_n_0 ),\n .I1(\\FSM_sequential_fine_adj_state_r[1]_i_3_n_0 ),\n .O(\\FSM_sequential_fine_adj_state_r_reg[1]_i_1_n_0 ),\n .S(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]));\n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\FSM_sequential_fine_adj_state_r_reg[2] \n (.C(CLK),\n .CE(\\FSM_sequential_fine_adj_state_r[3]_i_1_n_0 ),\n .D(\\FSM_sequential_fine_adj_state_r[2]_i_1_n_0 ),\n .Q(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\FSM_sequential_fine_adj_state_r_reg[3] \n (.C(CLK),\n .CE(\\FSM_sequential_fine_adj_state_r[3]_i_1_n_0 ),\n .D(\\FSM_sequential_fine_adj_state_r[3]_i_2_n_0 ),\n .Q(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n (* SOFT_HLUTNM = \"soft_lutpair293\" *) \n LUT4 #(\n .INIT(16'hCDC8)) \n \\calib_data_offset_0[0]_i_1 \n (.I0(pi_dqs_found_done_r1),\n .I1(rd_data_offset_ranks_0[0]),\n .I2(init_dqsfound_done_r2),\n .I3(\\rd_byte_data_offset_reg_n_0_[0][0] ),\n .O(\\calib_data_offset_0_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair292\" *) \n LUT4 #(\n .INIT(16'hCDC8)) \n \\calib_data_offset_0[1]_i_1 \n (.I0(pi_dqs_found_done_r1),\n .I1(rd_data_offset_ranks_0[1]),\n .I2(init_dqsfound_done_r2),\n .I3(\\rd_byte_data_offset_reg_n_0_[0][1] ),\n .O(\\calib_data_offset_0_reg[1] ));\n LUT4 #(\n .INIT(16'hCDC8)) \n \\calib_data_offset_0[4]_i_1 \n (.I0(pi_dqs_found_done_r1),\n .I1(rd_data_offset_ranks_0[4]),\n .I2(init_dqsfound_done_r2),\n .I3(\\rd_byte_data_offset_reg_n_0_[0][4] ),\n .O(\\calib_data_offset_0_reg[4] ));\n LUT4 #(\n .INIT(16'hCDC8)) \n \\calib_data_offset_0[5]_i_2 \n (.I0(pi_dqs_found_done_r1),\n .I1(rd_data_offset_ranks_0[5]),\n .I2(init_dqsfound_done_r2),\n .I3(\\rd_byte_data_offset_reg_n_0_[0][5] ),\n .O(\\calib_data_offset_0_reg[5] ));\n (* SOFT_HLUTNM = \"soft_lutpair291\" *) \n LUT4 #(\n .INIT(16'hCDC8)) \n \\calib_data_offset_1[0]_i_1 \n (.I0(pi_dqs_found_done_r1),\n .I1(rd_data_offset_ranks_1[0]),\n .I2(init_dqsfound_done_r2),\n .I3(p_0_in[0]),\n .O(\\calib_data_offset_1_reg[0] ));\n LUT4 #(\n .INIT(16'hCDC8)) \n \\calib_data_offset_1[1]_i_1 \n (.I0(pi_dqs_found_done_r1),\n .I1(rd_data_offset_ranks_1[1]),\n .I2(init_dqsfound_done_r2),\n .I3(p_0_in[1]),\n .O(\\calib_data_offset_1_reg[1] ));\n LUT4 #(\n .INIT(16'hCDC8)) \n \\calib_data_offset_1[4]_i_1 \n (.I0(pi_dqs_found_done_r1),\n .I1(rd_data_offset_ranks_1[4]),\n .I2(init_dqsfound_done_r2),\n .I3(p_0_in[4]),\n .O(\\calib_data_offset_1_reg[4] ));\n LUT4 #(\n .INIT(16'hCDC8)) \n \\calib_data_offset_1[5]_i_1 \n (.I0(pi_dqs_found_done_r1),\n .I1(rd_data_offset_ranks_1[5]),\n .I2(init_dqsfound_done_r2),\n .I3(p_0_in[5]),\n .O(\\calib_data_offset_1_reg[5] ));\n LUT6 #(\n .INIT(64'h4040404F00000000)) \n \\calib_sel[0]_i_1 \n (.I0(\\gen_byte_sel_div1.ctl_lane_sel_reg[2]_0 ),\n .I1(\\gen_byte_sel_div1.ctl_lane_sel_reg[0]_0 ),\n .I2(ctl_lane_sel),\n .I3(byte_sel_cnt),\n .I4(\\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ),\n .I5(init_calib_complete_reg),\n .O(D[0]));\n LUT6 #(\n .INIT(64'h4040404F00000000)) \n \\calib_sel[1]_i_1 \n (.I0(\\gen_byte_sel_div1.ctl_lane_sel_reg[2]_0 ),\n .I1(\\gen_byte_sel_div1.ctl_lane_sel_reg[1]_0 ),\n .I2(ctl_lane_sel),\n .I3(byte_sel_cnt),\n .I4(\\gen_byte_sel_div1.byte_sel_cnt_reg[1] ),\n .I5(init_calib_complete_reg),\n .O(D[1]));\n (* SOFT_HLUTNM = \"soft_lutpair275\" *) \n LUT5 #(\n .INIT(32'h08008888)) \n \\calib_sel[3]_i_2 \n (.I0(dqs_po_dec_done),\n .I1(pi_fine_dly_dec_done),\n .I2(fine_adjust_done_r_reg_0),\n .I3(rd_data_offset_cal_done),\n .I4(ck_addr_cmd_delay_done),\n .O(ctl_lane_sel));\n (* SOFT_HLUTNM = \"soft_lutpair285\" *) \n LUT4 #(\n .INIT(16'h10FF)) \n \\calib_zero_inputs[0]_i_1 \n (.I0(rst_stg1_cal),\n .I1(\\pi_rst_stg1_cal_reg_n_0_[1] ),\n .I2(ctl_lane_sel),\n .I3(init_calib_complete_reg),\n .O(\\calib_zero_inputs_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair275\" *) \n LUT3 #(\n .INIT(8'hA2)) \n \\calib_zero_inputs[1]_i_2 \n (.I0(ck_addr_cmd_delay_done),\n .I1(rd_data_offset_cal_done),\n .I2(fine_adjust_done_r_reg_0),\n .O(\\calib_zero_inputs_reg[1] ));\n FDRE #(\n .INIT(1'b0)) \n ck_po_stg2_f_en_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_fine_adj_state_r_reg[1]_3 ),\n .Q(ck_po_stg2_f_en),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n ck_po_stg2_f_indec_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_fine_adj_state_r_reg[1]_2 ),\n .Q(ck_po_stg2_f_indec),\n .R(rstdiv0_sync_r1_reg_rep__12));\n LUT1 #(\n .INIT(2'h1)) \n \\cmd_pipe_plus.mc_data_offset[0]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_reg[5] [0]),\n .O(\\cmd_pipe_plus.mc_data_offset_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair272\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\cmd_pipe_plus.mc_data_offset[1]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_reg[5] [0]),\n .I1(\\cmd_pipe_plus.mc_data_offset_reg[5] [1]),\n .O(\\cmd_pipe_plus.mc_data_offset_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair272\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\cmd_pipe_plus.mc_data_offset[4]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_reg[5] [4]),\n .I1(\\cmd_pipe_plus.mc_data_offset_reg[5] [2]),\n .I2(\\cmd_pipe_plus.mc_data_offset_reg[5] [1]),\n .I3(\\cmd_pipe_plus.mc_data_offset_reg[5] [0]),\n .I4(\\cmd_pipe_plus.mc_data_offset_reg[5] [3]),\n .O(\\cmd_pipe_plus.mc_data_offset_reg[4] ));\n LUT1 #(\n .INIT(2'h1)) \n \\cmd_pipe_plus.mc_data_offset_1[0]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [0]),\n .O(\\cmd_pipe_plus.mc_data_offset_1_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair281\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\cmd_pipe_plus.mc_data_offset_1[1]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [0]),\n .I1(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [1]),\n .O(\\cmd_pipe_plus.mc_data_offset_1_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair281\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\cmd_pipe_plus.mc_data_offset_1[4]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [4]),\n .I1(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [2]),\n .I2(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [1]),\n .I3(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [0]),\n .I4(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [3]),\n .O(\\cmd_pipe_plus.mc_data_offset_1_reg[4] ));\n (* SOFT_HLUTNM = \"soft_lutpair300\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\ctl_lane_cnt[0]_i_1__0 \n (.I0(fine_adjust_lane_cnt[0]),\n .O(ctl_lane_cnt__0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair300\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\ctl_lane_cnt[1]_i_1__0 \n (.I0(fine_adjust_lane_cnt[0]),\n .I1(fine_adjust_lane_cnt[1]),\n .O(ctl_lane_cnt__0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair290\" *) \n LUT4 #(\n .INIT(16'h4AAA)) \n \\ctl_lane_cnt[2]_i_1__0 \n (.I0(fine_adjust_lane_cnt[2]),\n .I1(\\ctl_lane_cnt_reg_n_0_[3] ),\n .I2(fine_adjust_lane_cnt[0]),\n .I3(fine_adjust_lane_cnt[1]),\n .O(ctl_lane_cnt__0[2]));\n LUT4 #(\n .INIT(16'h2040)) \n \\ctl_lane_cnt[3]_i_1__0 \n (.I0(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .I3(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .O(ctl_lane_cnt_0));\n (* SOFT_HLUTNM = \"soft_lutpair290\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\ctl_lane_cnt[3]_i_2__0 \n (.I0(\\ctl_lane_cnt_reg_n_0_[3] ),\n .I1(fine_adjust_lane_cnt[0]),\n .I2(fine_adjust_lane_cnt[1]),\n .I3(fine_adjust_lane_cnt[2]),\n .O(ctl_lane_cnt__0[3]));\n FDRE #(\n .INIT(1'b0)) \n \\ctl_lane_cnt_reg[0] \n (.C(CLK),\n .CE(ctl_lane_cnt_0),\n .D(ctl_lane_cnt__0[0]),\n .Q(fine_adjust_lane_cnt[0]),\n .R(SR));\n FDRE #(\n .INIT(1'b0)) \n \\ctl_lane_cnt_reg[1] \n (.C(CLK),\n .CE(ctl_lane_cnt_0),\n .D(ctl_lane_cnt__0[1]),\n .Q(fine_adjust_lane_cnt[1]),\n .R(SR));\n FDRE #(\n .INIT(1'b0)) \n \\ctl_lane_cnt_reg[2] \n (.C(CLK),\n .CE(ctl_lane_cnt_0),\n .D(ctl_lane_cnt__0[2]),\n .Q(fine_adjust_lane_cnt[2]),\n .R(SR));\n FDRE #(\n .INIT(1'b0)) \n \\ctl_lane_cnt_reg[3] \n (.C(CLK),\n .CE(ctl_lane_cnt_0),\n .D(ctl_lane_cnt__0[3]),\n .Q(\\ctl_lane_cnt_reg_n_0_[3] ),\n .R(SR));\n LUT6 #(\n .INIT(64'h7444744474777444)) \n \\dec_cnt[0]_i_1 \n (.I0(\\dec_cnt_reg_n_0_[0] ),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I2(\\dec_cnt[0]_i_2_n_0 ),\n .I3(fine_adj_state_r144_out),\n .I4(\\dec_cnt_reg[0]_i_3_n_6 ),\n .I5(\\dec_cnt[5]_i_9_n_0 ),\n .O(dec_cnt[0]));\n LUT6 #(\n .INIT(64'h0000888BFFFF888B)) \n \\dec_cnt[0]_i_2 \n (.I0(\\dec_cnt_reg[0]_i_3_n_6 ),\n .I1(first_fail_detect_i_2_n_0),\n .I2(\\first_fail_taps_reg_n_0_[1] ),\n .I3(\\first_fail_taps[5]_i_5_n_0 ),\n .I4(fine_adj_state_r141_out),\n .I5(\\inc_cnt_reg_n_0_[1] ),\n .O(\\dec_cnt[0]_i_2_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\dec_cnt[0]_i_4 \n (.I0(\\inc_cnt_reg_n_0_[3] ),\n .I1(\\first_fail_taps_reg_n_0_[3] ),\n .O(\\dec_cnt[0]_i_4_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\dec_cnt[0]_i_5 \n (.I0(\\inc_cnt_reg_n_0_[2] ),\n .I1(\\first_fail_taps_reg_n_0_[2] ),\n .O(\\dec_cnt[0]_i_5_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\dec_cnt[0]_i_6 \n (.I0(\\inc_cnt_reg_n_0_[1] ),\n .I1(\\first_fail_taps_reg_n_0_[1] ),\n .O(\\dec_cnt[0]_i_6_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\dec_cnt[0]_i_7 \n (.I0(\\inc_cnt_reg_n_0_[0] ),\n .I1(\\first_fail_taps_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_7_n_0 ));\n LUT4 #(\n .INIT(16'h9F90)) \n \\dec_cnt[1]_i_1 \n (.I0(\\dec_cnt_reg_n_0_[0] ),\n .I1(\\dec_cnt_reg_n_0_[1] ),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I3(\\dec_cnt[1]_i_2_n_0 ),\n .O(dec_cnt[1]));\n LUT6 #(\n .INIT(64'h08880888FBBB0888)) \n \\dec_cnt[1]_i_2 \n (.I0(\\dec_cnt[1]_i_3_n_0 ),\n .I1(detect_pi_found_dqs),\n .I2(\\pi_dqs_found_all_bank_r_reg[1]_0 ),\n .I3(pi_dqs_found_all_bank),\n .I4(\\dec_cnt_reg[0]_i_3_n_5 ),\n .I5(\\dec_cnt[5]_i_9_n_0 ),\n .O(\\dec_cnt[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h6F606F6F6F606060)) \n \\dec_cnt[1]_i_3 \n (.I0(\\inc_cnt_reg_n_0_[1] ),\n .I1(\\inc_cnt_reg_n_0_[2] ),\n .I2(fine_adj_state_r141_out),\n .I3(\\dec_cnt_reg[0]_i_3_n_5 ),\n .I4(first_fail_detect_i_2_n_0),\n .I5(\\dec_cnt[1]_i_4_n_0 ),\n .O(\\dec_cnt[1]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h5555555540000000)) \n \\dec_cnt[1]_i_4 \n (.I0(\\first_fail_taps_reg_n_0_[2] ),\n .I1(stable_pass_cnt_reg__0[4]),\n .I2(stable_pass_cnt_reg__0[3]),\n .I3(stable_pass_cnt_reg__0[2]),\n .I4(stable_pass_cnt_reg__0[1]),\n .I5(stable_pass_cnt_reg__0[5]),\n .O(\\dec_cnt[1]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'hE1FFE100)) \n \\dec_cnt[2]_i_1 \n (.I0(\\dec_cnt_reg_n_0_[0] ),\n .I1(\\dec_cnt_reg_n_0_[1] ),\n .I2(\\dec_cnt_reg_n_0_[2] ),\n .I3(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I4(\\dec_cnt[2]_i_2_n_0 ),\n .O(dec_cnt[2]));\n LUT6 #(\n .INIT(64'h08880888FBBB0888)) \n \\dec_cnt[2]_i_2 \n (.I0(\\dec_cnt[2]_i_3_n_0 ),\n .I1(detect_pi_found_dqs),\n .I2(\\pi_dqs_found_all_bank_r_reg[1]_0 ),\n .I3(pi_dqs_found_all_bank),\n .I4(\\dec_cnt_reg[0]_i_3_n_4 ),\n .I5(\\dec_cnt[5]_i_9_n_0 ),\n .O(\\dec_cnt[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hB888B888B888B8BB)) \n \\dec_cnt[2]_i_3 \n (.I0(\\dec_cnt[2]_i_4_n_0 ),\n .I1(fine_adj_state_r141_out),\n .I2(\\dec_cnt_reg[0]_i_3_n_4 ),\n .I3(first_fail_detect_i_2_n_0),\n .I4(\\first_fail_taps_reg_n_0_[3] ),\n .I5(\\first_fail_taps[5]_i_5_n_0 ),\n .O(\\dec_cnt[2]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair296\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\dec_cnt[2]_i_4 \n (.I0(\\inc_cnt_reg_n_0_[3] ),\n .I1(\\inc_cnt_reg_n_0_[1] ),\n .I2(\\inc_cnt_reg_n_0_[2] ),\n .O(\\dec_cnt[2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFE01FFFFFE010000)) \n \\dec_cnt[3]_i_1 \n (.I0(\\dec_cnt_reg_n_0_[2] ),\n .I1(\\dec_cnt_reg_n_0_[1] ),\n .I2(\\dec_cnt_reg_n_0_[0] ),\n .I3(\\dec_cnt_reg_n_0_[3] ),\n .I4(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I5(\\dec_cnt[3]_i_2_n_0 ),\n .O(dec_cnt[3]));\n LUT6 #(\n .INIT(64'h08880888FBBB0888)) \n \\dec_cnt[3]_i_2 \n (.I0(\\dec_cnt[3]_i_3_n_0 ),\n .I1(detect_pi_found_dqs),\n .I2(\\pi_dqs_found_all_bank_r_reg[1]_0 ),\n .I3(pi_dqs_found_all_bank),\n .I4(\\dec_cnt_reg[4]_i_4_n_7 ),\n .I5(\\dec_cnt[5]_i_9_n_0 ),\n .O(\\dec_cnt[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hB888B888B888B8BB)) \n \\dec_cnt[3]_i_3 \n (.I0(\\dec_cnt[3]_i_4_n_0 ),\n .I1(fine_adj_state_r141_out),\n .I2(\\dec_cnt_reg[4]_i_4_n_7 ),\n .I3(first_fail_detect_i_2_n_0),\n .I4(\\first_fail_taps_reg_n_0_[4] ),\n .I5(\\first_fail_taps[5]_i_5_n_0 ),\n .O(\\dec_cnt[3]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair279\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\dec_cnt[3]_i_4 \n (.I0(\\inc_cnt_reg_n_0_[4] ),\n .I1(\\inc_cnt_reg_n_0_[3] ),\n .I2(\\inc_cnt_reg_n_0_[1] ),\n .I3(\\inc_cnt_reg_n_0_[2] ),\n .O(\\dec_cnt[3]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hB888B888B8BBB888)) \n \\dec_cnt[4]_i_1 \n (.I0(\\dec_cnt[4]_i_2_n_0 ),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I2(\\dec_cnt[4]_i_3_n_0 ),\n .I3(fine_adj_state_r144_out),\n .I4(\\dec_cnt_reg[4]_i_4_n_6 ),\n .I5(\\dec_cnt[5]_i_9_n_0 ),\n .O(dec_cnt[4]));\n (* SOFT_HLUTNM = \"soft_lutpair282\" *) \n LUT5 #(\n .INIT(32'hFFFE0001)) \n \\dec_cnt[4]_i_2 \n (.I0(\\dec_cnt_reg_n_0_[3] ),\n .I1(\\dec_cnt_reg_n_0_[0] ),\n .I2(\\dec_cnt_reg_n_0_[1] ),\n .I3(\\dec_cnt_reg_n_0_[2] ),\n .I4(\\dec_cnt_reg_n_0_[4] ),\n .O(\\dec_cnt[4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hB888B888B888B8BB)) \n \\dec_cnt[4]_i_3 \n (.I0(\\dec_cnt[4]_i_5_n_0 ),\n .I1(fine_adj_state_r141_out),\n .I2(\\dec_cnt_reg[4]_i_4_n_6 ),\n .I3(first_fail_detect_i_2_n_0),\n .I4(\\first_fail_taps_reg_n_0_[5] ),\n .I5(\\first_fail_taps[5]_i_5_n_0 ),\n .O(\\dec_cnt[4]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair279\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\dec_cnt[4]_i_5 \n (.I0(\\inc_cnt_reg_n_0_[5] ),\n .I1(\\inc_cnt_reg_n_0_[4] ),\n .I2(\\inc_cnt_reg_n_0_[2] ),\n .I3(\\inc_cnt_reg_n_0_[1] ),\n .I4(\\inc_cnt_reg_n_0_[3] ),\n .O(\\dec_cnt[4]_i_5_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\dec_cnt[4]_i_6 \n (.I0(\\inc_cnt_reg_n_0_[5] ),\n .I1(\\first_fail_taps_reg_n_0_[5] ),\n .O(\\dec_cnt[4]_i_6_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\dec_cnt[4]_i_7 \n (.I0(\\inc_cnt_reg_n_0_[4] ),\n .I1(\\first_fail_taps_reg_n_0_[4] ),\n .O(\\dec_cnt[4]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h0808C80800000000)) \n \\dec_cnt[5]_i_1 \n (.I0(\\dec_cnt[5]_i_3_n_0 ),\n .I1(\\dec_cnt[5]_i_4_n_0 ),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I3(\\dec_cnt_reg[0]_0 ),\n .I4(\\dec_cnt[5]_i_6_n_0 ),\n .I5(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]),\n .O(\\dec_cnt[5]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h2220)) \n \\dec_cnt[5]_i_10 \n (.I0(\\first_fail_taps[5]_i_4_n_0 ),\n .I1(fine_adj_state_r141_out),\n .I2(first_fail_detect_reg_n_0),\n .I3(first_fail_detect_i_2_n_0),\n .O(\\dec_cnt[5]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'h9F909F9F9F909090)) \n \\dec_cnt[5]_i_2 \n (.I0(\\dec_cnt[5]_i_7_n_0 ),\n .I1(\\dec_cnt_reg_n_0_[5] ),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I3(\\dec_cnt[5]_i_8_n_0 ),\n .I4(fine_adj_state_r144_out),\n .I5(\\dec_cnt[5]_i_9_n_0 ),\n .O(dec_cnt[5]));\n LUT6 #(\n .INIT(64'h0555000035550000)) \n \\dec_cnt[5]_i_3 \n (.I0(\\dec_cnt[5]_i_10_n_0 ),\n .I1(fine_adj_state_r16_out),\n .I2(pi_dqs_found_all_bank),\n .I3(\\pi_dqs_found_all_bank_r_reg[1]_0 ),\n .I4(detect_pi_found_dqs),\n .I5(first_fail_detect_i_2_n_0),\n .O(\\dec_cnt[5]_i_3_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\dec_cnt[5]_i_4 \n (.I0(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .O(\\dec_cnt[5]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\dec_cnt[5]_i_5 \n (.I0(\\dec_cnt_reg_n_0_[5] ),\n .I1(\\dec_cnt_reg_n_0_[3] ),\n .I2(\\dec_cnt_reg_n_0_[0] ),\n .I3(\\dec_cnt_reg_n_0_[1] ),\n .I4(\\dec_cnt_reg_n_0_[2] ),\n .I5(\\dec_cnt_reg_n_0_[4] ),\n .O(\\dec_cnt_reg[0]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair270\" *) \n LUT5 #(\n .INIT(32'hFEFFFFFF)) \n \\dec_cnt[5]_i_6 \n (.I0(\\FSM_sequential_fine_adj_state_r_reg[2]_0 ),\n .I1(fine_adjust_lane_cnt[2]),\n .I2(\\ctl_lane_cnt_reg_n_0_[3] ),\n .I3(fine_adjust_lane_cnt[0]),\n .I4(fine_adjust_lane_cnt[1]),\n .O(\\dec_cnt[5]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair282\" *) \n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n \\dec_cnt[5]_i_7 \n (.I0(\\dec_cnt_reg_n_0_[4] ),\n .I1(\\dec_cnt_reg_n_0_[2] ),\n .I2(\\dec_cnt_reg_n_0_[1] ),\n .I3(\\dec_cnt_reg_n_0_[0] ),\n .I4(\\dec_cnt_reg_n_0_[3] ),\n .O(\\dec_cnt[5]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h0080000000D00000)) \n \\dec_cnt[5]_i_8 \n (.I0(\\first_fail_taps[5]_i_5_n_0 ),\n .I1(\\inc_cnt_reg_n_0_[0] ),\n .I2(\\inc_cnt_reg_n_0_[4] ),\n .I3(\\first_fail_taps[5]_i_6_n_0 ),\n .I4(\\inc_cnt_reg_n_0_[5] ),\n .I5(first_fail_detect_reg_n_0),\n .O(\\dec_cnt[5]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'hFFFE0000FFFFFFFF)) \n \\dec_cnt[5]_i_9 \n (.I0(\\first_fail_taps_reg_n_0_[2] ),\n .I1(\\first_fail_taps_reg_n_0_[1] ),\n .I2(\\first_fail_taps_reg_n_0_[4] ),\n .I3(\\first_fail_taps_reg_n_0_[3] ),\n .I4(\\first_fail_taps_reg_n_0_[5] ),\n .I5(first_fail_detect_reg_n_0),\n .O(\\dec_cnt[5]_i_9_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\dec_cnt_reg[0] \n (.C(CLK),\n .CE(\\dec_cnt[5]_i_1_n_0 ),\n .D(dec_cnt[0]),\n .Q(\\dec_cnt_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__12));\n CARRY4 \\dec_cnt_reg[0]_i_3 \n (.CI(1'b0),\n .CO({\\dec_cnt_reg[0]_i_3_n_0 ,\\dec_cnt_reg[0]_i_3_n_1 ,\\dec_cnt_reg[0]_i_3_n_2 ,\\dec_cnt_reg[0]_i_3_n_3 }),\n .CYINIT(1'b1),\n .DI({\\inc_cnt_reg_n_0_[3] ,\\inc_cnt_reg_n_0_[2] ,\\inc_cnt_reg_n_0_[1] ,\\inc_cnt_reg_n_0_[0] }),\n .O({\\dec_cnt_reg[0]_i_3_n_4 ,\\dec_cnt_reg[0]_i_3_n_5 ,\\dec_cnt_reg[0]_i_3_n_6 ,\\NLW_dec_cnt_reg[0]_i_3_O_UNCONNECTED [0]}),\n .S({\\dec_cnt[0]_i_4_n_0 ,\\dec_cnt[0]_i_5_n_0 ,\\dec_cnt[0]_i_6_n_0 ,\\dec_cnt[0]_i_7_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\dec_cnt_reg[1] \n (.C(CLK),\n .CE(\\dec_cnt[5]_i_1_n_0 ),\n .D(dec_cnt[1]),\n .Q(\\dec_cnt_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE #(\n .INIT(1'b0)) \n \\dec_cnt_reg[2] \n (.C(CLK),\n .CE(\\dec_cnt[5]_i_1_n_0 ),\n .D(dec_cnt[2]),\n .Q(\\dec_cnt_reg_n_0_[2] ),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE #(\n .INIT(1'b0)) \n \\dec_cnt_reg[3] \n (.C(CLK),\n .CE(\\dec_cnt[5]_i_1_n_0 ),\n .D(dec_cnt[3]),\n .Q(\\dec_cnt_reg_n_0_[3] ),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE #(\n .INIT(1'b0)) \n \\dec_cnt_reg[4] \n (.C(CLK),\n .CE(\\dec_cnt[5]_i_1_n_0 ),\n .D(dec_cnt[4]),\n .Q(\\dec_cnt_reg_n_0_[4] ),\n .R(rstdiv0_sync_r1_reg_rep__12));\n CARRY4 \\dec_cnt_reg[4]_i_4 \n (.CI(\\dec_cnt_reg[0]_i_3_n_0 ),\n .CO({\\NLW_dec_cnt_reg[4]_i_4_CO_UNCONNECTED [3:1],\\dec_cnt_reg[4]_i_4_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,\\inc_cnt_reg_n_0_[4] }),\n .O({\\NLW_dec_cnt_reg[4]_i_4_O_UNCONNECTED [3:2],\\dec_cnt_reg[4]_i_4_n_6 ,\\dec_cnt_reg[4]_i_4_n_7 }),\n .S({1'b0,1'b0,\\dec_cnt[4]_i_6_n_0 ,\\dec_cnt[4]_i_7_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\dec_cnt_reg[5] \n (.C(CLK),\n .CE(\\dec_cnt[5]_i_1_n_0 ),\n .D(dec_cnt[5]),\n .Q(\\dec_cnt_reg_n_0_[5] ),\n .R(rstdiv0_sync_r1_reg_rep__12));\n LUT1 #(\n .INIT(2'h1)) \n \\detect_rd_cnt[0]_i_1 \n (.I0(detect_rd_cnt_reg__0[0]),\n .O(detect_rd_cnt0__0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair295\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\detect_rd_cnt[1]_i_1 \n (.I0(detect_rd_cnt_reg__0[0]),\n .I1(detect_rd_cnt_reg__0[1]),\n .O(\\detect_rd_cnt[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair295\" *) \n LUT3 #(\n .INIT(8'hA9)) \n \\detect_rd_cnt[2]_i_1 \n (.I0(detect_rd_cnt_reg__0[2]),\n .I1(detect_rd_cnt_reg__0[1]),\n .I2(detect_rd_cnt_reg__0[0]),\n .O(detect_rd_cnt0__0[2]));\n LUT5 #(\n .INIT(32'hAAAAAAAB)) \n \\detect_rd_cnt[3]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__23),\n .I1(detect_rd_cnt_reg__0[2]),\n .I2(detect_rd_cnt_reg__0[3]),\n .I3(detect_rd_cnt_reg__0[0]),\n .I4(detect_rd_cnt_reg__0[1]),\n .O(\\detect_rd_cnt[3]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAAAAAAA8)) \n \\detect_rd_cnt[3]_i_2 \n (.I0(detect_pi_found_dqs),\n .I1(detect_rd_cnt_reg__0[2]),\n .I2(detect_rd_cnt_reg__0[3]),\n .I3(detect_rd_cnt_reg__0[0]),\n .I4(detect_rd_cnt_reg__0[1]),\n .O(detect_rd_cnt0));\n (* SOFT_HLUTNM = \"soft_lutpair267\" *) \n LUT4 #(\n .INIT(16'hAAA9)) \n \\detect_rd_cnt[3]_i_3 \n (.I0(detect_rd_cnt_reg__0[3]),\n .I1(detect_rd_cnt_reg__0[2]),\n .I2(detect_rd_cnt_reg__0[0]),\n .I3(detect_rd_cnt_reg__0[1]),\n .O(detect_rd_cnt0__0[3]));\n FDSE #(\n .INIT(1'b1)) \n \\detect_rd_cnt_reg[0] \n (.C(CLK),\n .CE(detect_rd_cnt0),\n .D(detect_rd_cnt0__0[0]),\n .Q(detect_rd_cnt_reg__0[0]),\n .S(\\detect_rd_cnt[3]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\detect_rd_cnt_reg[1] \n (.C(CLK),\n .CE(detect_rd_cnt0),\n .D(\\detect_rd_cnt[1]_i_1_n_0 ),\n .Q(detect_rd_cnt_reg__0[1]),\n .S(\\detect_rd_cnt[3]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\detect_rd_cnt_reg[2] \n (.C(CLK),\n .CE(detect_rd_cnt0),\n .D(detect_rd_cnt0__0[2]),\n .Q(detect_rd_cnt_reg__0[2]),\n .S(\\detect_rd_cnt[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\detect_rd_cnt_reg[3] \n (.C(CLK),\n .CE(detect_rd_cnt0),\n .D(detect_rd_cnt0__0[3]),\n .Q(detect_rd_cnt_reg__0[3]),\n .R(\\detect_rd_cnt[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000800000000000)) \n dqs_found_done_r_i_1\n (.I0(\\rd_byte_data_offset_reg[0]_3 ),\n .I1(init_dqsfound_done_r1_reg_n_0),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]),\n .I3(dqs_found_done_r_i_3_n_0),\n .I4(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I5(p_1_in27_in),\n .O(dqs_found_done_r0));\n LUT2 #(\n .INIT(4'h1)) \n dqs_found_done_r_i_2\n (.I0(\\rnk_cnt_r_reg_n_0_[1] ),\n .I1(\\rnk_cnt_r_reg_n_0_[0] ),\n .O(\\rd_byte_data_offset_reg[0]_3 ));\n LUT2 #(\n .INIT(4'h1)) \n dqs_found_done_r_i_3\n (.I0(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .O(dqs_found_done_r_i_3_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair289\" *) \n LUT2 #(\n .INIT(4'h8)) \n dqs_found_done_r_i_4\n (.I0(pi_dqs_found_all_bank),\n .I1(\\pi_dqs_found_all_bank_r_reg[1]_0 ),\n .O(p_1_in27_in));\n FDRE #(\n .INIT(1'b0)) \n dqs_found_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(dqs_found_done_r0),\n .Q(pi_dqs_found_done_r1_reg),\n .R(rstdiv0_sync_r1_reg_rep__12));\n LUT6 #(\n .INIT(64'h0201010000020200)) \n dqs_found_prech_req_i_2\n (.I0(\\inc_cnt_reg_n_0_[3] ),\n .I1(\\inc_cnt_reg_n_0_[1] ),\n .I2(\\inc_cnt_reg_n_0_[0] ),\n .I3(\\inc_cnt_reg_n_0_[2] ),\n .I4(\\inc_cnt_reg_n_0_[4] ),\n .I5(\\inc_cnt_reg_n_0_[5] ),\n .O(fine_adj_state_r16_out));\n LUT3 #(\n .INIT(8'hB8)) \n dqs_found_prech_req_i_3\n (.I0(fine_adj_state_r110_out),\n .I1(\\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ),\n .I2(fine_adj_state_r17_out),\n .O(dqs_found_prech_req_reg_0));\n LUT6 #(\n .INIT(64'hC008000800000000)) \n dqs_found_prech_req_i_4\n (.I0(dqs_found_prech_req_i_5_n_0),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .I3(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I4(prech_done),\n .I5(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]),\n .O(dqs_found_prech_req_reg_1));\n LUT6 #(\n .INIT(64'hF0C0F040F0800000)) \n dqs_found_prech_req_i_5\n (.I0(\\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ),\n .I1(\\dec_cnt[5]_i_10_n_0 ),\n .I2(detect_pi_found_dqs),\n .I3(p_1_in27_in),\n .I4(fine_adj_state_r110_out),\n .I5(fine_adj_state_r17_out),\n .O(dqs_found_prech_req_i_5_n_0));\n FDRE #(\n .INIT(1'b0)) \n dqs_found_prech_req_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_fine_adj_state_r_reg[2]_1 ),\n .Q(dqs_found_prech_req),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n dqs_found_start_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_start_reg),\n .Q(dqs_found_start_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFBF)) \n final_dec_done_i_2\n (.I0(\\dec_cnt_reg[0]_0 ),\n .I1(fine_adjust_lane_cnt[1]),\n .I2(fine_adjust_lane_cnt[0]),\n .I3(\\ctl_lane_cnt_reg_n_0_[3] ),\n .I4(fine_adjust_lane_cnt[2]),\n .I5(\\FSM_sequential_fine_adj_state_r_reg[2]_0 ),\n .O(final_dec_done_reg_1));\n FDRE #(\n .INIT(1'b0)) \n final_dec_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_fine_adj_state_r_reg[1]_1 ),\n .Q(final_dec_done_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE #(\n .INIT(1'b0)) \n fine_adjust_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_fine_adj_state_r_reg[0]_3 ),\n .Q(fine_adjust_done_r_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n fine_adjust_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_fine_adj_state_r_reg[0]_2 ),\n .Q(\\pi_rst_stg1_cal_r_reg[0]_0 ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n LUT5 #(\n .INIT(32'hFFFFAEAF)) \n first_fail_detect_i_1\n (.I0(\\first_fail_taps[5]_i_4_n_0 ),\n .I1(\\first_fail_taps[5]_i_5_n_0 ),\n .I2(first_fail_detect_i_2_n_0),\n .I3(first_fail_detect_reg_n_0),\n .I4(fine_adj_state_r141_out),\n .O(first_fail_detect_i_1_n_0));\n LUT6 #(\n .INIT(64'h7FFFFFFFFFFFFFFF)) \n first_fail_detect_i_2\n (.I0(\\inc_cnt_reg_n_0_[5] ),\n .I1(\\inc_cnt_reg_n_0_[3] ),\n .I2(\\inc_cnt_reg_n_0_[1] ),\n .I3(\\inc_cnt_reg_n_0_[2] ),\n .I4(\\inc_cnt_reg_n_0_[4] ),\n .I5(\\inc_cnt_reg_n_0_[0] ),\n .O(first_fail_detect_i_2_n_0));\n LUT6 #(\n .INIT(64'h000000000000FF08)) \n first_fail_detect_i_3\n (.I0(\\inc_cnt_reg_n_0_[4] ),\n .I1(\\inc_cnt_reg_n_0_[0] ),\n .I2(\\first_fail_taps[5]_i_6_n_0 ),\n .I3(\\inc_cnt_reg_n_0_[5] ),\n .I4(\\first_fail_taps[5]_i_5_n_0 ),\n .I5(first_fail_detect_reg_n_0),\n .O(fine_adj_state_r141_out));\n FDRE #(\n .INIT(1'b0)) \n first_fail_detect_reg\n (.C(CLK),\n .CE(first_fail_detect),\n .D(first_fail_detect_i_1_n_0),\n .Q(first_fail_detect_reg_n_0),\n .R(SR));\n LUT3 #(\n .INIT(8'hB8)) \n \\first_fail_taps[0]_i_1 \n (.I0(\\inc_cnt_reg_n_0_[0] ),\n .I1(\\first_fail_taps[5]_i_4_n_0 ),\n .I2(\\first_fail_taps[5]_i_5_n_0 ),\n .O(\\first_fail_taps[0]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hB8)) \n \\first_fail_taps[1]_i_1 \n (.I0(\\inc_cnt_reg_n_0_[1] ),\n .I1(\\first_fail_taps[5]_i_4_n_0 ),\n .I2(\\first_fail_taps[5]_i_5_n_0 ),\n .O(\\first_fail_taps[1]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hB8)) \n \\first_fail_taps[2]_i_1 \n (.I0(\\inc_cnt_reg_n_0_[2] ),\n .I1(\\first_fail_taps[5]_i_4_n_0 ),\n .I2(\\first_fail_taps[5]_i_5_n_0 ),\n .O(\\first_fail_taps[2]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hB8)) \n \\first_fail_taps[3]_i_1 \n (.I0(\\inc_cnt_reg_n_0_[3] ),\n .I1(\\first_fail_taps[5]_i_4_n_0 ),\n .I2(\\first_fail_taps[5]_i_5_n_0 ),\n .O(\\first_fail_taps[3]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hB8)) \n \\first_fail_taps[4]_i_1 \n (.I0(\\inc_cnt_reg_n_0_[4] ),\n .I1(\\first_fail_taps[5]_i_4_n_0 ),\n .I2(\\first_fail_taps[5]_i_5_n_0 ),\n .O(\\first_fail_taps[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0020000000000000)) \n \\first_fail_taps[5]_i_1 \n (.I0(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .I3(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I4(fine_adj_state_r144_out),\n .I5(first_fail_detect_i_1_n_0),\n .O(first_fail_detect));\n LUT3 #(\n .INIT(8'hB8)) \n \\first_fail_taps[5]_i_2 \n (.I0(\\inc_cnt_reg_n_0_[5] ),\n .I1(\\first_fail_taps[5]_i_4_n_0 ),\n .I2(\\first_fail_taps[5]_i_5_n_0 ),\n .O(\\first_fail_taps[5]_i_2_n_0 ));\n LUT3 #(\n .INIT(8'h2A)) \n \\first_fail_taps[5]_i_3 \n (.I0(detect_pi_found_dqs),\n .I1(\\pi_dqs_found_all_bank_r_reg[1]_0 ),\n .I2(pi_dqs_found_all_bank),\n .O(fine_adj_state_r144_out));\n LUT6 #(\n .INIT(64'hFFFFF7FF00FF00FF)) \n \\first_fail_taps[5]_i_4 \n (.I0(\\inc_cnt_reg_n_0_[4] ),\n .I1(\\inc_cnt_reg_n_0_[0] ),\n .I2(\\first_fail_taps[5]_i_6_n_0 ),\n .I3(first_fail_detect_reg_n_0),\n .I4(\\first_fail_taps[5]_i_7_n_0 ),\n .I5(\\first_fail_taps[5]_i_5_n_0 ),\n .O(\\first_fail_taps[5]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h15555555)) \n \\first_fail_taps[5]_i_5 \n (.I0(stable_pass_cnt_reg__0[5]),\n .I1(stable_pass_cnt_reg__0[1]),\n .I2(stable_pass_cnt_reg__0[2]),\n .I3(stable_pass_cnt_reg__0[3]),\n .I4(stable_pass_cnt_reg__0[4]),\n .O(\\first_fail_taps[5]_i_5_n_0 ));\n LUT3 #(\n .INIT(8'h7F)) \n \\first_fail_taps[5]_i_6 \n (.I0(\\inc_cnt_reg_n_0_[2] ),\n .I1(\\inc_cnt_reg_n_0_[1] ),\n .I2(\\inc_cnt_reg_n_0_[3] ),\n .O(\\first_fail_taps[5]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h00000001FFFFFFFF)) \n \\first_fail_taps[5]_i_7 \n (.I0(\\inc_cnt_reg_n_0_[3] ),\n .I1(\\inc_cnt_reg_n_0_[1] ),\n .I2(\\inc_cnt_reg_n_0_[0] ),\n .I3(\\inc_cnt_reg_n_0_[2] ),\n .I4(\\inc_cnt_reg_n_0_[4] ),\n .I5(\\inc_cnt_reg_n_0_[5] ),\n .O(\\first_fail_taps[5]_i_7_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\first_fail_taps_reg[0] \n (.C(CLK),\n .CE(first_fail_detect),\n .D(\\first_fail_taps[0]_i_1_n_0 ),\n .Q(\\first_fail_taps_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n \\first_fail_taps_reg[1] \n (.C(CLK),\n .CE(first_fail_detect),\n .D(\\first_fail_taps[1]_i_1_n_0 ),\n .Q(\\first_fail_taps_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n \\first_fail_taps_reg[2] \n (.C(CLK),\n .CE(first_fail_detect),\n .D(\\first_fail_taps[2]_i_1_n_0 ),\n .Q(\\first_fail_taps_reg_n_0_[2] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n \\first_fail_taps_reg[3] \n (.C(CLK),\n .CE(first_fail_detect),\n .D(\\first_fail_taps[3]_i_1_n_0 ),\n .Q(\\first_fail_taps_reg_n_0_[3] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n \\first_fail_taps_reg[4] \n (.C(CLK),\n .CE(first_fail_detect),\n .D(\\first_fail_taps[4]_i_1_n_0 ),\n .Q(\\first_fail_taps_reg_n_0_[4] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n \\first_fail_taps_reg[5] \n (.C(CLK),\n .CE(first_fail_detect),\n .D(\\first_fail_taps[5]_i_2_n_0 ),\n .Q(\\first_fail_taps_reg_n_0_[5] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n LUT6 #(\n .INIT(64'hFFFFFFFF88A8FFFF)) \n \\gen_byte_sel_div1.byte_sel_cnt[2]_i_4 \n (.I0(ck_addr_cmd_delay_done),\n .I1(\\gen_byte_sel_div1.byte_sel_cnt[2]_i_9_n_0 ),\n .I2(rd_data_offset_cal_done),\n .I3(fine_adjust_done_r_reg_0),\n .I4(cmd_delay_start0),\n .I5(rstdiv0_sync_r1_reg_rep__24),\n .O(\\gen_byte_sel_div1.byte_sel_cnt_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair288\" *) \n LUT2 #(\n .INIT(4'h7)) \n \\gen_byte_sel_div1.byte_sel_cnt[2]_i_9 \n (.I0(pi_dqs_found_done_r1_reg),\n .I1(pi_calib_done),\n .O(\\gen_byte_sel_div1.byte_sel_cnt[2]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAEAAAAAAA2A)) \n \\gen_byte_sel_div1.calib_in_common_i_1 \n (.I0(\\gen_byte_sel_div1.calib_in_common_i_2_n_0 ),\n .I1(pi_dqs_found_done_r1_reg),\n .I2(pi_calib_done),\n .I3(oclkdelay_calib_done_r_reg),\n .I4(pi_f_inc_reg),\n .I5(calib_in_common),\n .O(\\gen_byte_sel_div1.calib_in_common_reg ));\n LUT6 #(\n .INIT(64'hBFBFFFBFFFBFFFBF)) \n \\gen_byte_sel_div1.calib_in_common_i_2 \n (.I0(\\gen_byte_sel_div1.calib_in_common_i_5_n_0 ),\n .I1(pi_fine_dly_dec_done),\n .I2(dqs_po_dec_done),\n .I3(\\calib_zero_inputs_reg[1] ),\n .I4(pi_calib_done),\n .I5(pi_dqs_found_done_r1_reg),\n .O(\\gen_byte_sel_div1.calib_in_common_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h3533000005000000)) \n \\gen_byte_sel_div1.calib_in_common_i_5 \n (.I0(\\gen_byte_sel_div1.ctl_lane_sel[2]_i_2_n_0 ),\n .I1(oclkdelay_calib_done_r_reg),\n .I2(fine_adjust_done_r_reg_0),\n .I3(rd_data_offset_cal_done),\n .I4(ck_addr_cmd_delay_done),\n .I5(tempmon_sel_pi_incdec),\n .O(\\gen_byte_sel_div1.calib_in_common_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h8F80FFFF8F800000)) \n \\gen_byte_sel_div1.ctl_lane_sel[0]_i_1 \n (.I0(\\gen_byte_sel_div1.ctl_lane_sel[2]_i_2_n_0 ),\n .I1(fine_adjust_lane_cnt[0]),\n .I2(ck_addr_cmd_delay_done),\n .I3(ctl_lane_cnt[0]),\n .I4(ctl_lane_sel),\n .I5(\\gen_byte_sel_div1.ctl_lane_sel_reg[0]_0 ),\n .O(\\gen_byte_sel_div1.ctl_lane_sel_reg[0] ));\n LUT6 #(\n .INIT(64'h8F80FFFF8F800000)) \n \\gen_byte_sel_div1.ctl_lane_sel[1]_i_1 \n (.I0(\\gen_byte_sel_div1.ctl_lane_sel[2]_i_2_n_0 ),\n .I1(fine_adjust_lane_cnt[1]),\n .I2(ck_addr_cmd_delay_done),\n .I3(ctl_lane_cnt[1]),\n .I4(ctl_lane_sel),\n .I5(\\gen_byte_sel_div1.ctl_lane_sel_reg[1]_0 ),\n .O(\\gen_byte_sel_div1.ctl_lane_sel_reg[1] ));\n LUT6 #(\n .INIT(64'h8F80FFFF8F800000)) \n \\gen_byte_sel_div1.ctl_lane_sel[2]_i_1 \n (.I0(\\gen_byte_sel_div1.ctl_lane_sel[2]_i_2_n_0 ),\n .I1(fine_adjust_lane_cnt[2]),\n .I2(ck_addr_cmd_delay_done),\n .I3(ctl_lane_cnt[2]),\n .I4(ctl_lane_sel),\n .I5(\\gen_byte_sel_div1.ctl_lane_sel_reg[2]_0 ),\n .O(\\gen_byte_sel_div1.ctl_lane_sel_reg[2] ));\n (* SOFT_HLUTNM = \"soft_lutpair285\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\gen_byte_sel_div1.ctl_lane_sel[2]_i_2 \n (.I0(rst_stg1_cal),\n .I1(\\pi_rst_stg1_cal_reg_n_0_[1] ),\n .O(\\gen_byte_sel_div1.ctl_lane_sel[2]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair287\" *) \n LUT3 #(\n .INIT(8'h80)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_3 \n (.I0(pi_dqs_found_done_r1_reg),\n .I1(rdlvl_stg1_done_int_reg),\n .I2(prbs_rdlvl_done_reg_rep),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ));\n LUT1 #(\n .INIT(2'h2)) \n i_0\n (.I0(1'b1),\n .O(n_0_0));\n LUT1 #(\n .INIT(2'h2)) \n i_1\n (.I0(1'b1),\n .O(n_0_1));\n LUT1 #(\n .INIT(2'h2)) \n i_2\n (.I0(1'b1),\n .O(n_0_2));\n LUT1 #(\n .INIT(2'h2)) \n i_3\n (.I0(1'b1),\n .O(n_0_3));\n (* SOFT_HLUTNM = \"soft_lutpair299\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\inc_cnt[0]_i_1 \n (.I0(\\inc_cnt_reg_n_0_[0] ),\n .O(p_0_in__0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair299\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\inc_cnt[1]_i_1 \n (.I0(\\inc_cnt_reg_n_0_[0] ),\n .I1(\\inc_cnt_reg_n_0_[1] ),\n .O(p_0_in__0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair296\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\inc_cnt[2]_i_1 \n (.I0(\\inc_cnt_reg_n_0_[2] ),\n .I1(\\inc_cnt_reg_n_0_[1] ),\n .I2(\\inc_cnt_reg_n_0_[0] ),\n .O(p_0_in__0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair284\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\inc_cnt[3]_i_1 \n (.I0(\\inc_cnt_reg_n_0_[3] ),\n .I1(\\inc_cnt_reg_n_0_[0] ),\n .I2(\\inc_cnt_reg_n_0_[1] ),\n .I3(\\inc_cnt_reg_n_0_[2] ),\n .O(p_0_in__0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair284\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\inc_cnt[4]_i_1 \n (.I0(\\inc_cnt_reg_n_0_[4] ),\n .I1(\\inc_cnt_reg_n_0_[0] ),\n .I2(\\inc_cnt_reg_n_0_[2] ),\n .I3(\\inc_cnt_reg_n_0_[1] ),\n .I4(\\inc_cnt_reg_n_0_[3] ),\n .O(\\inc_cnt[4]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h00200000)) \n \\inc_cnt[5]_i_1 \n (.I0(\\FSM_sequential_fine_adj_state_r_reg[0]_1 ),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .I3(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I4(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]),\n .O(inc_cnt));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n \\inc_cnt[5]_i_2 \n (.I0(\\inc_cnt_reg_n_0_[5] ),\n .I1(\\inc_cnt_reg_n_0_[3] ),\n .I2(\\inc_cnt_reg_n_0_[1] ),\n .I3(\\inc_cnt_reg_n_0_[2] ),\n .I4(\\inc_cnt_reg_n_0_[0] ),\n .I5(\\inc_cnt_reg_n_0_[4] ),\n .O(p_0_in__0[5]));\n FDRE #(\n .INIT(1'b0)) \n \\inc_cnt_reg[0] \n (.C(CLK),\n .CE(inc_cnt),\n .D(p_0_in__0[0]),\n .Q(\\inc_cnt_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE #(\n .INIT(1'b0)) \n \\inc_cnt_reg[1] \n (.C(CLK),\n .CE(inc_cnt),\n .D(p_0_in__0[1]),\n .Q(\\inc_cnt_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE #(\n .INIT(1'b0)) \n \\inc_cnt_reg[2] \n (.C(CLK),\n .CE(inc_cnt),\n .D(p_0_in__0[2]),\n .Q(\\inc_cnt_reg_n_0_[2] ),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE #(\n .INIT(1'b0)) \n \\inc_cnt_reg[3] \n (.C(CLK),\n .CE(inc_cnt),\n .D(p_0_in__0[3]),\n .Q(\\inc_cnt_reg_n_0_[3] ),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE #(\n .INIT(1'b0)) \n \\inc_cnt_reg[4] \n (.C(CLK),\n .CE(inc_cnt),\n .D(\\inc_cnt[4]_i_1_n_0 ),\n .Q(\\inc_cnt_reg_n_0_[4] ),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE #(\n .INIT(1'b0)) \n \\inc_cnt_reg[5] \n (.C(CLK),\n .CE(inc_cnt),\n .D(p_0_in__0[5]),\n .Q(\\inc_cnt_reg_n_0_[5] ),\n .R(rstdiv0_sync_r1_reg_rep__2));\n LUT1 #(\n .INIT(2'h1)) \n \\init_dec_cnt[0]_i_1 \n (.I0(init_dec_cnt_reg__0[0]),\n .O(init_dec_cnt0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair297\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\init_dec_cnt[1]_i_1 \n (.I0(init_dec_cnt_reg__0[0]),\n .I1(init_dec_cnt_reg__0[1]),\n .O(\\init_dec_cnt[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair297\" *) \n LUT3 #(\n .INIT(8'hE1)) \n \\init_dec_cnt[2]_i_1 \n (.I0(init_dec_cnt_reg__0[0]),\n .I1(init_dec_cnt_reg__0[1]),\n .I2(init_dec_cnt_reg__0[2]),\n .O(init_dec_cnt0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair280\" *) \n LUT4 #(\n .INIT(16'hFE01)) \n \\init_dec_cnt[3]_i_1 \n (.I0(init_dec_cnt_reg__0[2]),\n .I1(init_dec_cnt_reg__0[1]),\n .I2(init_dec_cnt_reg__0[0]),\n .I3(init_dec_cnt_reg__0[3]),\n .O(init_dec_cnt0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair280\" *) \n LUT5 #(\n .INIT(32'hFFFE0001)) \n \\init_dec_cnt[4]_i_1 \n (.I0(init_dec_cnt_reg__0[3]),\n .I1(init_dec_cnt_reg__0[0]),\n .I2(init_dec_cnt_reg__0[1]),\n .I3(init_dec_cnt_reg__0[2]),\n .I4(init_dec_cnt_reg__0[4]),\n .O(init_dec_cnt0[4]));\n LUT6 #(\n .INIT(64'h2000000000000000)) \n \\init_dec_cnt[5]_i_1 \n (.I0(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .I3(\\FSM_sequential_fine_adj_state_r_reg[0]_1 ),\n .I4(\\FSM_sequential_fine_adj_state_r_reg[2]_0 ),\n .I5(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]),\n .O(init_dec_cnt));\n LUT6 #(\n .INIT(64'hFFFFFFFE00000001)) \n \\init_dec_cnt[5]_i_2 \n (.I0(init_dec_cnt_reg__0[4]),\n .I1(init_dec_cnt_reg__0[2]),\n .I2(init_dec_cnt_reg__0[1]),\n .I3(init_dec_cnt_reg__0[0]),\n .I4(init_dec_cnt_reg__0[3]),\n .I5(init_dec_cnt_reg__0[5]),\n .O(init_dec_cnt0[5]));\n FDSE #(\n .INIT(1'b1)) \n \\init_dec_cnt_reg[0] \n (.C(CLK),\n .CE(init_dec_cnt),\n .D(init_dec_cnt0[0]),\n .Q(init_dec_cnt_reg__0[0]),\n .S(rstdiv0_sync_r1_reg_rep__2));\n FDSE #(\n .INIT(1'b1)) \n \\init_dec_cnt_reg[1] \n (.C(CLK),\n .CE(init_dec_cnt),\n .D(\\init_dec_cnt[1]_i_1_n_0 ),\n .Q(init_dec_cnt_reg__0[1]),\n .S(rstdiv0_sync_r1_reg_rep__2));\n FDSE #(\n .INIT(1'b1)) \n \\init_dec_cnt_reg[2] \n (.C(CLK),\n .CE(init_dec_cnt),\n .D(init_dec_cnt0[2]),\n .Q(init_dec_cnt_reg__0[2]),\n .S(rstdiv0_sync_r1_reg_rep__2));\n FDSE #(\n .INIT(1'b1)) \n \\init_dec_cnt_reg[3] \n (.C(CLK),\n .CE(init_dec_cnt),\n .D(init_dec_cnt0[3]),\n .Q(init_dec_cnt_reg__0[3]),\n .S(rstdiv0_sync_r1_reg_rep__2));\n FDSE #(\n .INIT(1'b1)) \n \\init_dec_cnt_reg[4] \n (.C(CLK),\n .CE(init_dec_cnt),\n .D(init_dec_cnt0[4]),\n .Q(init_dec_cnt_reg__0[4]),\n .S(rstdiv0_sync_r1_reg_rep__2));\n FDRE #(\n .INIT(1'b0)) \n \\init_dec_cnt_reg[5] \n (.C(CLK),\n .CE(init_dec_cnt),\n .D(init_dec_cnt0[5]),\n .Q(init_dec_cnt_reg__0[5]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n LUT3 #(\n .INIT(8'h08)) \n init_dec_done_i_2\n (.I0(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .O(init_dec_done_reg_1));\n FDRE #(\n .INIT(1'b0)) \n init_dec_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(init_dec_done_reg_2),\n .Q(init_dec_done_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n init_dqsfound_done_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rd_data_offset_cal_done),\n .Q(init_dqsfound_done_r1_reg_n_0),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n init_dqsfound_done_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(init_dqsfound_done_r1_reg_n_0),\n .Q(init_dqsfound_done_r2),\n .R(1'b0));\n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_right.u_ddr_phy_dqs_found_cal/init_dqsfound_done_r4_reg_srl2 \" *) \n SRL16E #(\n .INIT(16'h0000)) \n init_dqsfound_done_r4_reg_srl2\n (.A0(1'b1),\n .A1(1'b0),\n .A2(1'b0),\n .A3(1'b0),\n .CE(1'b1),\n .CLK(CLK),\n .D(init_dqsfound_done_r2),\n .Q(init_dqsfound_done_r4_reg_srl2_n_0));\n FDRE #(\n .INIT(1'b0)) \n init_dqsfound_done_r5_reg\n (.C(CLK),\n .CE(1'b1),\n .D(init_dqsfound_done_r4_reg_srl2_n_0),\n .Q(init_dqsfound_done_r5),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n init_dqsfound_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(init_dqsfound_done_r_reg_0),\n .Q(rd_data_offset_cal_done),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0003FFFF33A3FFFF)) \n \\init_state_r[1]_i_14 \n (.I0(\\init_state_r[1]_i_29_n_0 ),\n .I1(\\num_refresh_reg[1] ),\n .I2(oclkdelay_calib_done_r_reg_0),\n .I3(mpr_rdlvl_done_r_reg),\n .I4(cnt_cmd_done_r),\n .I5(\\init_state_r[1]_i_30_n_0 ),\n .O(\\init_state_r_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair288\" *) \n LUT4 #(\n .INIT(16'h00DF)) \n \\init_state_r[1]_i_29 \n (.I0(pi_dqs_found_done_r1_reg),\n .I1(prbs_rdlvl_done_reg_rep),\n .I2(prbs_last_byte_done_r),\n .I3(wrcal_done_reg),\n .O(\\init_state_r[1]_i_29_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair287\" *) \n LUT4 #(\n .INIT(16'h5DFD)) \n \\init_state_r[1]_i_30 \n (.I0(pi_dqs_found_done_r1_reg),\n .I1(wrcal_done_reg),\n .I2(rdlvl_stg1_done_int_reg),\n .I3(prbs_rdlvl_done_reg_rep),\n .O(\\init_state_r[1]_i_30_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair286\" *) \n LUT2 #(\n .INIT(4'h7)) \n \\init_state_r[1]_i_31 \n (.I0(pi_dqs_found_done_r1_reg),\n .I1(wrcal_done_reg),\n .O(\\init_state_r_reg[1]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair286\" *) \n LUT4 #(\n .INIT(16'hFFFB)) \n \\init_state_r[1]_i_44 \n (.I0(wrlvl_final_mux),\n .I1(pi_dqs_found_done_r1_reg),\n .I2(wrlvl_byte_redo),\n .I3(wrlvl_done_r1),\n .O(\\init_state_r_reg[1]_0 ));\n LUT6 #(\n .INIT(64'hF0FDFDFDFDFDFDFD)) \n \\init_state_r[2]_i_31 \n (.I0(pi_dqs_found_done_r1_reg),\n .I1(wrlvl_byte_redo),\n .I2(wrlvl_done_r1),\n .I3(oclkdelay_center_calib_done_r_reg),\n .I4(prbs_rdlvl_done_reg_rep),\n .I5(rdlvl_stg1_done_int_reg),\n .O(\\init_state_r_reg[2] ));\n (* SOFT_HLUTNM = \"soft_lutpair263\" *) \n LUT5 #(\n .INIT(32'h0000EA00)) \n \\phaser_in_gen.phaser_in_i_5 \n (.I0(calib_in_common),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(rst_stg1_cal),\n .I4(\\calib_zero_inputs_reg[1]_0 [0]),\n .O(ififo_rst_reg));\n (* SOFT_HLUTNM = \"soft_lutpair263\" *) \n LUT5 #(\n .INIT(32'h0000BA00)) \n \\phaser_in_gen.phaser_in_i_5__0 \n (.I0(calib_in_common),\n .I1(Q[0]),\n .I2(Q[1]),\n .I3(rst_stg1_cal),\n .I4(\\calib_zero_inputs_reg[1]_0 [0]),\n .O(ififo_rst_reg_0));\n (* SOFT_HLUTNM = \"soft_lutpair264\" *) \n LUT5 #(\n .INIT(32'h0000BA00)) \n \\phaser_in_gen.phaser_in_i_5__1 \n (.I0(calib_in_common),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(rst_stg1_cal),\n .I4(\\calib_zero_inputs_reg[1]_0 [0]),\n .O(ififo_rst_reg_1));\n (* SOFT_HLUTNM = \"soft_lutpair264\" *) \n LUT5 #(\n .INIT(32'h0000AB00)) \n \\phaser_in_gen.phaser_in_i_5__2 \n (.I0(calib_in_common),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(rst_stg1_cal),\n .I4(\\calib_zero_inputs_reg[1]_0 [0]),\n .O(ififo_rst_reg_2));\n LUT6 #(\n .INIT(64'h00000000AAAAAAA8)) \n phaser_out_i_2__1\n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .I1(ck_po_stg2_f_en),\n .I2(dqs_po_en_stg2_f),\n .I3(po_en_stg2_f),\n .I4(po_en_stg23),\n .I5(\\calib_zero_inputs_reg[1]_0 [0]),\n .O(\\po_counter_read_val_reg[8]_6 ));\n LUT6 #(\n .INIT(64'h00000000AAAAAAA8)) \n phaser_out_i_2__2\n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .I1(ck_po_stg2_f_en),\n .I2(dqs_po_en_stg2_f),\n .I3(po_en_stg2_f),\n .I4(po_en_stg23),\n .I5(\\calib_zero_inputs_reg[1]_0 [0]),\n .O(\\po_counter_read_val_reg[8]_8 ));\n LUT6 #(\n .INIT(64'h00000000AAAAAAA8)) \n phaser_out_i_2__3\n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_2 ),\n .I1(ck_po_stg2_f_en),\n .I2(dqs_po_en_stg2_f),\n .I3(po_en_stg2_f),\n .I4(po_en_stg23),\n .I5(\\calib_zero_inputs_reg[1]_0 [0]),\n .O(\\po_counter_read_val_reg[8]_10 ));\n LUT6 #(\n .INIT(64'h00000000AAAAAAA8)) \n phaser_out_i_2__4\n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_3 ),\n .I1(ck_po_stg2_f_en),\n .I2(dqs_po_en_stg2_f),\n .I3(po_en_stg2_f),\n .I4(po_en_stg23),\n .I5(\\calib_zero_inputs_reg[1]_0 [0]),\n .O(\\po_counter_read_val_reg[8]_12 ));\n (* SOFT_HLUTNM = \"soft_lutpair268\" *) \n LUT5 #(\n .INIT(32'h00000800)) \n phaser_out_i_3\n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(calib_in_common),\n .I3(po_enstg2_f),\n .I4(\\calib_zero_inputs_reg[1]_0 [1]),\n .O(D_po_fine_enable107_out));\n (* SOFT_HLUTNM = \"soft_lutpair268\" *) \n LUT5 #(\n .INIT(32'h00000100)) \n phaser_out_i_3__0\n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(calib_in_common),\n .I3(po_enstg2_f),\n .I4(\\calib_zero_inputs_reg[1]_0 [1]),\n .O(\\po_counter_read_val_reg[8] ));\n (* SOFT_HLUTNM = \"soft_lutpair271\" *) \n LUT5 #(\n .INIT(32'h00000400)) \n phaser_out_i_3__1\n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(calib_in_common),\n .I3(po_enstg2_f),\n .I4(\\calib_zero_inputs_reg[1]_0 [1]),\n .O(\\po_counter_read_val_reg[8]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair271\" *) \n LUT5 #(\n .INIT(32'h00000400)) \n phaser_out_i_3__2\n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(calib_in_common),\n .I3(po_enstg2_f),\n .I4(\\calib_zero_inputs_reg[1]_0 [1]),\n .O(\\po_counter_read_val_reg[8]_3 ));\n LUT5 #(\n .INIT(32'h0000AAA8)) \n phaser_out_i_3__3\n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .I1(ck_po_stg2_f_indec),\n .I2(dqs_po_stg2_f_incdec),\n .I3(po_stg23_incdec),\n .I4(\\calib_zero_inputs_reg[1]_0 [0]),\n .O(\\po_counter_read_val_reg[8]_5 ));\n LUT5 #(\n .INIT(32'h0000AAA8)) \n phaser_out_i_3__4\n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .I1(ck_po_stg2_f_indec),\n .I2(dqs_po_stg2_f_incdec),\n .I3(po_stg23_incdec),\n .I4(\\calib_zero_inputs_reg[1]_0 [0]),\n .O(\\po_counter_read_val_reg[8]_7 ));\n LUT5 #(\n .INIT(32'h0000AAA8)) \n phaser_out_i_3__5\n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_2 ),\n .I1(ck_po_stg2_f_indec),\n .I2(dqs_po_stg2_f_incdec),\n .I3(po_stg23_incdec),\n .I4(\\calib_zero_inputs_reg[1]_0 [0]),\n .O(\\po_counter_read_val_reg[8]_9 ));\n LUT5 #(\n .INIT(32'h0000AAA8)) \n phaser_out_i_3__6\n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_3 ),\n .I1(ck_po_stg2_f_indec),\n .I2(dqs_po_stg2_f_incdec),\n .I3(po_stg23_incdec),\n .I4(\\calib_zero_inputs_reg[1]_0 [0]),\n .O(\\po_counter_read_val_reg[8]_11 ));\n (* SOFT_HLUTNM = \"soft_lutpair265\" *) \n LUT5 #(\n .INIT(32'h00000800)) \n phaser_out_i_4\n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(calib_in_common),\n .I3(po_stg2_fincdec),\n .I4(\\calib_zero_inputs_reg[1]_0 [1]),\n .O(D_po_fine_inc113_out));\n (* SOFT_HLUTNM = \"soft_lutpair266\" *) \n LUT5 #(\n .INIT(32'h00000100)) \n phaser_out_i_4__0\n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(calib_in_common),\n .I3(po_stg2_fincdec),\n .I4(\\calib_zero_inputs_reg[1]_0 [1]),\n .O(\\po_counter_read_val_reg[8]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair265\" *) \n LUT5 #(\n .INIT(32'h00000400)) \n phaser_out_i_4__1\n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(calib_in_common),\n .I3(po_stg2_fincdec),\n .I4(\\calib_zero_inputs_reg[1]_0 [1]),\n .O(\\po_counter_read_val_reg[8]_2 ));\n (* SOFT_HLUTNM = \"soft_lutpair266\" *) \n LUT5 #(\n .INIT(32'h00000400)) \n phaser_out_i_4__2\n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(calib_in_common),\n .I3(po_stg2_fincdec),\n .I4(\\calib_zero_inputs_reg[1]_0 [1]),\n .O(\\po_counter_read_val_reg[8]_4 ));\n LUT6 #(\n .INIT(64'h8000FFFF80000000)) \n \\pi_dqs_found_all_bank[0]_i_1 \n (.I0(pi_dqs_found_lanes_r3[2]),\n .I1(pi_dqs_found_lanes_r3[3]),\n .I2(pi_dqs_found_lanes_r3[1]),\n .I3(pi_dqs_found_lanes_r3[0]),\n .I4(pi_dqs_found_start_reg),\n .I5(pi_dqs_found_all_bank),\n .O(\\pi_dqs_found_all_bank[0]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\pi_dqs_found_all_bank_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_all_bank),\n .Q(rank_done_r_reg_0[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\pi_dqs_found_all_bank_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\pi_dqs_found_all_bank_r_reg[1]_0 ),\n .Q(rank_done_r_reg_0[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\pi_dqs_found_all_bank_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\pi_dqs_found_all_bank[0]_i_1_n_0 ),\n .Q(pi_dqs_found_all_bank),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n \\pi_dqs_found_all_bank_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_start_reg_0),\n .Q(\\pi_dqs_found_all_bank_r_reg[1]_0 ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n \\pi_dqs_found_any_bank_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_any_bank),\n .Q(\\pi_dqs_found_any_bank_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\pi_dqs_found_any_bank_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\pi_dqs_found_lanes_r3_reg[3]_0 ),\n .Q(pi_dqs_found_any_bank),\n .R(rstdiv0_sync_r1_reg_rep__13));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\pi_dqs_found_lanes_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(in0[0]),\n .Q(pi_dqs_found_lanes_r1[0]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\pi_dqs_found_lanes_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(in0[1]),\n .Q(pi_dqs_found_lanes_r1[1]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\pi_dqs_found_lanes_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(in0[2]),\n .Q(pi_dqs_found_lanes_r1[2]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\pi_dqs_found_lanes_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(in0[3]),\n .Q(pi_dqs_found_lanes_r1[3]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\pi_dqs_found_lanes_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(n_0_3),\n .Q(pi_dqs_found_lanes_r1[4]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\pi_dqs_found_lanes_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(n_0_2),\n .Q(pi_dqs_found_lanes_r1[5]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\pi_dqs_found_lanes_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(n_0_1),\n .Q(pi_dqs_found_lanes_r1[6]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\pi_dqs_found_lanes_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(n_0_0),\n .Q(pi_dqs_found_lanes_r1[7]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\pi_dqs_found_lanes_r2_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_lanes_r1[0]),\n .Q(pi_dqs_found_lanes_r2[0]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\pi_dqs_found_lanes_r2_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_lanes_r1[1]),\n .Q(pi_dqs_found_lanes_r2[1]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\pi_dqs_found_lanes_r2_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_lanes_r1[2]),\n .Q(pi_dqs_found_lanes_r2[2]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\pi_dqs_found_lanes_r2_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_lanes_r1[3]),\n .Q(pi_dqs_found_lanes_r2[3]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\pi_dqs_found_lanes_r2_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_lanes_r1[4]),\n .Q(pi_dqs_found_lanes_r2[4]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\pi_dqs_found_lanes_r2_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_lanes_r1[5]),\n .Q(pi_dqs_found_lanes_r2[5]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\pi_dqs_found_lanes_r2_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_lanes_r1[6]),\n .Q(pi_dqs_found_lanes_r2[6]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\pi_dqs_found_lanes_r2_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_lanes_r1[7]),\n .Q(pi_dqs_found_lanes_r2[7]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\pi_dqs_found_lanes_r3_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_lanes_r2[0]),\n .Q(pi_dqs_found_lanes_r3[0]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\pi_dqs_found_lanes_r3_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_lanes_r2[1]),\n .Q(pi_dqs_found_lanes_r3[1]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\pi_dqs_found_lanes_r3_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_lanes_r2[2]),\n .Q(pi_dqs_found_lanes_r3[2]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\pi_dqs_found_lanes_r3_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_lanes_r2[3]),\n .Q(pi_dqs_found_lanes_r3[3]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\pi_dqs_found_lanes_r3_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_lanes_r2[4]),\n .Q(pi_dqs_found_lanes_r3[4]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\pi_dqs_found_lanes_r3_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_lanes_r2[5]),\n .Q(pi_dqs_found_lanes_r3[5]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\pi_dqs_found_lanes_r3_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_lanes_r2[6]),\n .Q(pi_dqs_found_lanes_r3[6]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\pi_dqs_found_lanes_r3_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_lanes_r2[7]),\n .Q(pi_dqs_found_lanes_r3[7]),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair301\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\pi_rst_stg1_cal[0]_i_1 \n (.I0(\\pi_rst_stg1_cal_r_reg[0]_1 ),\n .I1(rst_dqs_find_r1_reg_0),\n .O(\\pi_rst_stg1_cal[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair301\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\pi_rst_stg1_cal[1]_i_1 \n (.I0(p_1_in50_in),\n .I1(rst_dqs_find_r1_reg_0),\n .O(\\pi_rst_stg1_cal[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h1111111010101010)) \n \\pi_rst_stg1_cal_r1[0]_i_1 \n (.I0(\\pi_rst_stg1_cal_r_reg[0]_0 ),\n .I1(rstdiv0_sync_r1_reg_rep__23),\n .I2(\\pi_rst_stg1_cal_r_reg[0]_1 ),\n .I3(\\pi_dqs_found_any_bank_r_reg_n_0_[0] ),\n .I4(pi_dqs_found_all_bank),\n .I5(\\pi_rst_stg1_cal_r1_reg_n_0_[0] ),\n .O(pi_rst_stg1_cal_r1_reg017_out));\n LUT5 #(\n .INIT(32'h11101010)) \n \\pi_rst_stg1_cal_r1[1]_i_1 \n (.I0(\\pi_rst_stg1_cal_r_reg[0]_0 ),\n .I1(rstdiv0_sync_r1_reg_rep__23),\n .I2(p_1_in50_in),\n .I3(p_0_in19_in),\n .I4(\\pi_dqs_found_all_bank_r_reg[1]_0 ),\n .O(pi_rst_stg1_cal_r1_reg0));\n FDRE #(\n .INIT(1'b0)) \n \\pi_rst_stg1_cal_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_rst_stg1_cal_r1_reg017_out),\n .Q(\\pi_rst_stg1_cal_r1_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\pi_rst_stg1_cal_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_rst_stg1_cal_r1_reg0),\n .Q(p_0_in19_in),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000000000FE)) \n \\pi_rst_stg1_cal_r[0]_i_1 \n (.I0(\\pi_rst_stg1_cal_r_reg[0]_1 ),\n .I1(\\pi_rst_stg1_cal_r[0]_i_2_n_0 ),\n .I2(\\pi_rst_stg1_cal_r[0]_i_3_n_0 ),\n .I3(rstdiv0_sync_r1_reg_rep__23),\n .I4(\\pi_rst_stg1_cal_r_reg[0]_0 ),\n .I5(\\pi_rst_stg1_cal_r1_reg_n_0_[0] ),\n .O(\\pi_rst_stg1_cal_r[0]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h0007)) \n \\pi_rst_stg1_cal_r[0]_i_2 \n (.I0(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [1]),\n .I1(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [0]),\n .I2(\\rd_byte_data_offset_reg_n_0_[0][5] ),\n .I3(\\rd_byte_data_offset_reg_n_0_[0][4] ),\n .O(\\pi_rst_stg1_cal_r[0]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair289\" *) \n LUT4 #(\n .INIT(16'h4F44)) \n \\pi_rst_stg1_cal_r[0]_i_3 \n (.I0(dqs_found_start_r),\n .I1(pi_dqs_found_start_reg),\n .I2(pi_dqs_found_all_bank),\n .I3(\\pi_dqs_found_any_bank_r_reg_n_0_[0] ),\n .O(\\pi_rst_stg1_cal_r[0]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h00000000EFEE0000)) \n \\pi_rst_stg1_cal_r[1]_i_1 \n (.I0(p_1_in50_in),\n .I1(\\pi_rst_stg1_cal_r[1]_i_2_n_0 ),\n .I2(dqs_found_start_r),\n .I3(pi_dqs_found_start_reg),\n .I4(fine_adjust_reg_0),\n .I5(p_0_in19_in),\n .O(\\pi_rst_stg1_cal_r[1]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h0007)) \n \\pi_rst_stg1_cal_r[1]_i_2 \n (.I0(\\rd_byte_data_offset_reg[0][9]_0 [1]),\n .I1(\\rd_byte_data_offset_reg[0][9]_0 [0]),\n .I2(p_0_in[5]),\n .I3(p_0_in[4]),\n .O(\\pi_rst_stg1_cal_r[1]_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\pi_rst_stg1_cal_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\pi_rst_stg1_cal_r[0]_i_1_n_0 ),\n .Q(\\pi_rst_stg1_cal_r_reg[0]_1 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\pi_rst_stg1_cal_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\pi_rst_stg1_cal_r[1]_i_1_n_0 ),\n .Q(p_1_in50_in),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\pi_rst_stg1_cal_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\pi_rst_stg1_cal[0]_i_1_n_0 ),\n .Q(rst_stg1_cal),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n \\pi_rst_stg1_cal_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\pi_rst_stg1_cal[1]_i_1_n_0 ),\n .Q(\\pi_rst_stg1_cal_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n rank_done_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_rank_done),\n .Q(rank_done_r1),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n rank_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\pi_dqs_found_all_bank_r_reg[1]_1 ),\n .Q(pi_dqs_found_rank_done),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h2)) \n \\rank_final_loop[0].bank_final_loop[0].final_data_offset[0][5]_i_1 \n (.I0(rd_data_offset_cal_done),\n .I1(init_dqsfound_done_r1_reg_n_0),\n .O(p_22_out));\n (* SOFT_HLUTNM = \"soft_lutpair293\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1 \n (.I0(\\rd_byte_data_offset_reg_n_0_[0][0] ),\n .O(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair292\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1 \n (.I0(\\rd_byte_data_offset_reg_n_0_[0][1] ),\n .I1(\\rd_byte_data_offset_reg_n_0_[0][0] ),\n .O(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hA9)) \n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1 \n (.I0(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [0]),\n .I1(\\rd_byte_data_offset_reg_n_0_[0][0] ),\n .I2(\\rd_byte_data_offset_reg_n_0_[0][1] ),\n .O(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair274\" *) \n LUT4 #(\n .INIT(16'hAAA9)) \n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1 \n (.I0(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [1]),\n .I1(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [0]),\n .I2(\\rd_byte_data_offset_reg_n_0_[0][1] ),\n .I3(\\rd_byte_data_offset_reg_n_0_[0][0] ),\n .O(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair274\" *) \n LUT5 #(\n .INIT(32'hAAAAAAA9)) \n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1 \n (.I0(\\rd_byte_data_offset_reg_n_0_[0][4] ),\n .I1(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [1]),\n .I2(\\rd_byte_data_offset_reg_n_0_[0][0] ),\n .I3(\\rd_byte_data_offset_reg_n_0_[0][1] ),\n .I4(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [0]),\n .O(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h04)) \n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_1 \n (.I0(init_dqsfound_done_r1_reg_n_0),\n .I1(rd_data_offset_cal_done),\n .I2(rstdiv0_sync_r1_reg_rep__23),\n .O(final_data_offset_mc));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAAAAA9)) \n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2 \n (.I0(\\rd_byte_data_offset_reg_n_0_[0][5] ),\n .I1(\\rd_byte_data_offset_reg_n_0_[0][4] ),\n .I2(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [0]),\n .I3(\\rd_byte_data_offset_reg_n_0_[0][1] ),\n .I4(\\rd_byte_data_offset_reg_n_0_[0][0] ),\n .I5(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [1]),\n .O(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] \n (.C(CLK),\n .CE(final_data_offset_mc),\n .D(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0 ),\n .Q(\\cmd_pipe_plus.mc_data_offset_reg[5] [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][1] \n (.C(CLK),\n .CE(final_data_offset_mc),\n .D(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1_n_0 ),\n .Q(\\cmd_pipe_plus.mc_data_offset_reg[5] [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][2] \n (.C(CLK),\n .CE(final_data_offset_mc),\n .D(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1_n_0 ),\n .Q(\\cmd_pipe_plus.mc_data_offset_reg[5] [2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][3] \n (.C(CLK),\n .CE(final_data_offset_mc),\n .D(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1_n_0 ),\n .Q(\\cmd_pipe_plus.mc_data_offset_reg[5] [3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4] \n (.C(CLK),\n .CE(final_data_offset_mc),\n .D(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1_n_0 ),\n .Q(\\cmd_pipe_plus.mc_data_offset_reg[5] [4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] \n (.C(CLK),\n .CE(final_data_offset_mc),\n .D(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2_n_0 ),\n .Q(\\cmd_pipe_plus.mc_data_offset_reg[5] [5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][0] \n (.C(CLK),\n .CE(p_22_out),\n .D(\\rd_byte_data_offset_reg_n_0_[0][0] ),\n .Q(rd_data_offset_ranks_0[0]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE #(\n .INIT(1'b0)) \n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][1] \n (.C(CLK),\n .CE(p_22_out),\n .D(\\rd_byte_data_offset_reg_n_0_[0][1] ),\n .Q(rd_data_offset_ranks_0[1]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE #(\n .INIT(1'b0)) \n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][2] \n (.C(CLK),\n .CE(p_22_out),\n .D(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [0]),\n .Q(\\rank_final_loop[0].final_do_max_reg[0][3]_0 [0]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE #(\n .INIT(1'b0)) \n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3] \n (.C(CLK),\n .CE(p_22_out),\n .D(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [1]),\n .Q(\\rank_final_loop[0].final_do_max_reg[0][3]_0 [1]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE #(\n .INIT(1'b0)) \n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][4] \n (.C(CLK),\n .CE(p_22_out),\n .D(\\rd_byte_data_offset_reg_n_0_[0][4] ),\n .Q(rd_data_offset_ranks_0[4]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE #(\n .INIT(1'b0)) \n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][5] \n (.C(CLK),\n .CE(p_22_out),\n .D(\\rd_byte_data_offset_reg_n_0_[0][5] ),\n .Q(rd_data_offset_ranks_0[5]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n LUT3 #(\n .INIT(8'h8A)) \n \\rank_final_loop[0].bank_final_loop[1].final_data_offset[0][11]_i_1 \n (.I0(init_dqsfound_done_r5),\n .I1(init_dqsfound_done_r1_reg_n_0),\n .I2(rd_data_offset_cal_done),\n .O(final_data_offset));\n LUT4 #(\n .INIT(16'h00D0)) \n \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1 \n (.I0(rd_data_offset_cal_done),\n .I1(init_dqsfound_done_r1_reg_n_0),\n .I2(init_dqsfound_done_r5),\n .I3(rstdiv0_sync_r1_reg_rep__23),\n .O(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10] \n (.C(CLK),\n .CE(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ),\n .D(\\rank_final_loop[0].final_do_max_reg[0]__0 [4]),\n .Q(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] \n (.C(CLK),\n .CE(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ),\n .D(\\rank_final_loop[0].final_do_max_reg[0]__0 [5]),\n .Q(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] \n (.C(CLK),\n .CE(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ),\n .D(\\rank_final_loop[0].final_do_max_reg[0]__0 [0]),\n .Q(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][7] \n (.C(CLK),\n .CE(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ),\n .D(\\rank_final_loop[0].final_do_max_reg[0]__0 [1]),\n .Q(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][8] \n (.C(CLK),\n .CE(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ),\n .D(\\rank_final_loop[0].final_do_max_reg[0]__0 [2]),\n .Q(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][9] \n (.C(CLK),\n .CE(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ),\n .D(\\rank_final_loop[0].final_do_max_reg[0]__0 [3]),\n .Q(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][10] \n (.C(CLK),\n .CE(final_data_offset),\n .D(\\rank_final_loop[0].final_do_max_reg[0]__0 [4]),\n .Q(rd_data_offset_ranks_1[4]),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n \\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][11] \n (.C(CLK),\n .CE(final_data_offset),\n .D(\\rank_final_loop[0].final_do_max_reg[0]__0 [5]),\n .Q(rd_data_offset_ranks_1[5]),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n \\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][6] \n (.C(CLK),\n .CE(final_data_offset),\n .D(\\rank_final_loop[0].final_do_max_reg[0]__0 [0]),\n .Q(rd_data_offset_ranks_1[0]),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n \\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][7] \n (.C(CLK),\n .CE(final_data_offset),\n .D(\\rank_final_loop[0].final_do_max_reg[0]__0 [1]),\n .Q(rd_data_offset_ranks_1[1]),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n \\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][8] \n (.C(CLK),\n .CE(final_data_offset),\n .D(\\rank_final_loop[0].final_do_max_reg[0]__0 [2]),\n .Q(\\rank_final_loop[0].final_do_max_reg[0][3]_1 [0]),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n \\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] \n (.C(CLK),\n .CE(final_data_offset),\n .D(\\rank_final_loop[0].final_do_max_reg[0]__0 [3]),\n .Q(\\rank_final_loop[0].final_do_max_reg[0][3]_1 [1]),\n .R(rstdiv0_sync_r1_reg_rep__13));\n LUT1 #(\n .INIT(2'h1)) \n \\rank_final_loop[0].final_do_index[0][0]_i_1 \n (.I0(\\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),\n .O(\\rank_final_loop[0].final_do_index[0][0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair283\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\rank_final_loop[0].final_do_index[0][1]_i_1 \n (.I0(\\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),\n .I1(\\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ),\n .O(\\rank_final_loop[0].final_do_index[0][1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair269\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\rank_final_loop[0].final_do_index[0][2]_i_1 \n (.I0(\\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ),\n .I1(\\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ),\n .I2(\\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),\n .O(\\rank_final_loop[0].final_do_index[0][2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rank_final_loop[0].final_do_index_reg[0][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rank_final_loop[0].final_do_index[0][0]_i_1_n_0 ),\n .Q(\\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n \\rank_final_loop[0].final_do_index_reg[0][1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rank_final_loop[0].final_do_index[0][1]_i_1_n_0 ),\n .Q(\\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n \\rank_final_loop[0].final_do_index_reg[0][2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rank_final_loop[0].final_do_index[0][2]_i_1_n_0 ),\n .Q(\\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n (* SOFT_HLUTNM = \"soft_lutpair273\" *) \n LUT5 #(\n .INIT(32'hEFEEEFFF)) \n \\rank_final_loop[0].final_do_max[0][0]_i_1 \n (.I0(\\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ),\n .I1(\\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ),\n .I2(rd_data_offset_ranks_1[0]),\n .I3(\\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),\n .I4(rd_data_offset_ranks_0[0]),\n .O(\\rank_final_loop[0].final_do_max[0][0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFAF5FCFCFAF5F3F3)) \n \\rank_final_loop[0].final_do_max[0][1]_i_1 \n (.I0(rd_data_offset_ranks_1[1]),\n .I1(rd_data_offset_ranks_0[1]),\n .I2(\\rank_final_loop[0].final_do_max[0][5]_i_5_n_0 ),\n .I3(rd_data_offset_ranks_1[0]),\n .I4(\\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),\n .I5(rd_data_offset_ranks_0[0]),\n .O(\\rank_final_loop[0].final_do_max[0][1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h555555555555A959)) \n \\rank_final_loop[0].final_do_max[0][2]_i_1 \n (.I0(\\rank_final_loop[0].final_do_max[0][2]_i_2_n_0 ),\n .I1(\\rank_final_loop[0].final_do_max_reg[0][3]_0 [0]),\n .I2(\\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),\n .I3(\\rank_final_loop[0].final_do_max_reg[0][3]_1 [0]),\n .I4(\\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ),\n .I5(\\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ),\n .O(\\rank_final_loop[0].final_do_max[0][2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FAFFFACC)) \n \\rank_final_loop[0].final_do_max[0][2]_i_2 \n (.I0(rd_data_offset_ranks_1[0]),\n .I1(rd_data_offset_ranks_0[0]),\n .I2(rd_data_offset_ranks_1[1]),\n .I3(\\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),\n .I4(rd_data_offset_ranks_0[1]),\n .I5(\\rank_final_loop[0].final_do_max[0][5]_i_5_n_0 ),\n .O(\\rank_final_loop[0].final_do_max[0][2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h555555555555A959)) \n \\rank_final_loop[0].final_do_max[0][3]_i_1 \n (.I0(\\rank_final_loop[0].final_do_max[0][3]_i_2_n_0 ),\n .I1(\\rank_final_loop[0].final_do_max_reg[0][3]_0 [1]),\n .I2(\\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),\n .I3(\\rank_final_loop[0].final_do_max_reg[0][3]_1 [1]),\n .I4(\\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ),\n .I5(\\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ),\n .O(\\rank_final_loop[0].final_do_max[0][3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF10111000)) \n \\rank_final_loop[0].final_do_max[0][3]_i_2 \n (.I0(\\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ),\n .I1(\\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ),\n .I2(\\rank_final_loop[0].final_do_max_reg[0][3]_1 [0]),\n .I3(\\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),\n .I4(\\rank_final_loop[0].final_do_max_reg[0][3]_0 [0]),\n .I5(\\rank_final_loop[0].final_do_max[0][2]_i_2_n_0 ),\n .O(\\rank_final_loop[0].final_do_max[0][3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hEFEEEFFF10111000)) \n \\rank_final_loop[0].final_do_max[0][4]_i_1 \n (.I0(\\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ),\n .I1(\\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ),\n .I2(rd_data_offset_ranks_1[4]),\n .I3(\\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),\n .I4(rd_data_offset_ranks_0[4]),\n .I5(\\rank_final_loop[0].final_do_max[0][5]_i_7_n_0 ),\n .O(\\rank_final_loop[0].final_do_max[0][4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FFFF4F44)) \n \\rank_final_loop[0].final_do_max[0][5]_i_1 \n (.I0(\\rank_final_loop[0].final_do_max_reg[0]__0 [5]),\n .I1(rd_data_offset_ranks_0[5]),\n .I2(\\rank_final_loop[0].final_do_max_reg[0]__0 [4]),\n .I3(rd_data_offset_ranks_0[4]),\n .I4(\\rank_final_loop[0].final_do_max[0][5]_i_3_n_0 ),\n .I5(\\rank_final_loop[0].final_do_max[0][5]_i_4_n_0 ),\n .O(\\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h4540BABF45404540)) \n \\rank_final_loop[0].final_do_max[0][5]_i_2 \n (.I0(\\rank_final_loop[0].final_do_max[0][5]_i_5_n_0 ),\n .I1(rd_data_offset_ranks_1[5]),\n .I2(\\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),\n .I3(rd_data_offset_ranks_0[5]),\n .I4(\\rank_final_loop[0].final_do_max[0][5]_i_6_n_0 ),\n .I5(\\rank_final_loop[0].final_do_max[0][5]_i_7_n_0 ),\n .O(\\rank_final_loop[0].final_do_max[0][5]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FFFF4F44)) \n \\rank_final_loop[0].final_do_max[0][5]_i_3 \n (.I0(\\rank_final_loop[0].final_do_max_reg[0]__0 [3]),\n .I1(\\rank_final_loop[0].final_do_max_reg[0][3]_0 [1]),\n .I2(\\rank_final_loop[0].final_do_max_reg[0]__0 [2]),\n .I3(\\rank_final_loop[0].final_do_max_reg[0][3]_0 [0]),\n .I4(\\rank_final_loop[0].final_do_max[0][5]_i_8_n_0 ),\n .I5(\\rank_final_loop[0].final_do_max[0][5]_i_9_n_0 ),\n .O(\\rank_final_loop[0].final_do_max[0][5]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair269\" *) \n LUT5 #(\n .INIT(32'hFFFFFFF4)) \n \\rank_final_loop[0].final_do_max[0][5]_i_4 \n (.I0(rd_data_offset_ranks_0[5]),\n .I1(\\rank_final_loop[0].final_do_max_reg[0]__0 [5]),\n .I2(\\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),\n .I3(\\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ),\n .I4(\\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ),\n .O(\\rank_final_loop[0].final_do_max[0][5]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair273\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\rank_final_loop[0].final_do_max[0][5]_i_5 \n (.I0(\\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ),\n .I1(\\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ),\n .O(\\rank_final_loop[0].final_do_max[0][5]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair283\" *) \n LUT5 #(\n .INIT(32'h000000E2)) \n \\rank_final_loop[0].final_do_max[0][5]_i_6 \n (.I0(rd_data_offset_ranks_0[4]),\n .I1(\\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),\n .I2(rd_data_offset_ranks_1[4]),\n .I3(\\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ),\n .I4(\\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ),\n .O(\\rank_final_loop[0].final_do_max[0][5]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h00000000EFEEEFFF)) \n \\rank_final_loop[0].final_do_max[0][5]_i_7 \n (.I0(\\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ),\n .I1(\\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ),\n .I2(\\rank_final_loop[0].final_do_max_reg[0][3]_1 [1]),\n .I3(\\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),\n .I4(\\rank_final_loop[0].final_do_max_reg[0][3]_0 [1]),\n .I5(\\rank_final_loop[0].final_do_max[0][3]_i_2_n_0 ),\n .O(\\rank_final_loop[0].final_do_max[0][5]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h40F4000040F440F4)) \n \\rank_final_loop[0].final_do_max[0][5]_i_8 \n (.I0(\\rank_final_loop[0].final_do_max_reg[0]__0 [0]),\n .I1(rd_data_offset_ranks_0[0]),\n .I2(rd_data_offset_ranks_0[1]),\n .I3(\\rank_final_loop[0].final_do_max_reg[0]__0 [1]),\n .I4(\\rank_final_loop[0].final_do_max_reg[0][3]_0 [0]),\n .I5(\\rank_final_loop[0].final_do_max_reg[0]__0 [2]),\n .O(\\rank_final_loop[0].final_do_max[0][5]_i_8_n_0 ));\n LUT4 #(\n .INIT(16'h4F44)) \n \\rank_final_loop[0].final_do_max[0][5]_i_9 \n (.I0(\\rank_final_loop[0].final_do_max_reg[0][3]_0 [1]),\n .I1(\\rank_final_loop[0].final_do_max_reg[0]__0 [3]),\n .I2(rd_data_offset_ranks_0[4]),\n .I3(\\rank_final_loop[0].final_do_max_reg[0]__0 [4]),\n .O(\\rank_final_loop[0].final_do_max[0][5]_i_9_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rank_final_loop[0].final_do_max_reg[0][0] \n (.C(CLK),\n .CE(\\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ),\n .D(\\rank_final_loop[0].final_do_max[0][0]_i_1_n_0 ),\n .Q(\\rank_final_loop[0].final_do_max_reg[0]__0 [0]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE #(\n .INIT(1'b0)) \n \\rank_final_loop[0].final_do_max_reg[0][1] \n (.C(CLK),\n .CE(\\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ),\n .D(\\rank_final_loop[0].final_do_max[0][1]_i_1_n_0 ),\n .Q(\\rank_final_loop[0].final_do_max_reg[0]__0 [1]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE #(\n .INIT(1'b0)) \n \\rank_final_loop[0].final_do_max_reg[0][2] \n (.C(CLK),\n .CE(\\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ),\n .D(\\rank_final_loop[0].final_do_max[0][2]_i_1_n_0 ),\n .Q(\\rank_final_loop[0].final_do_max_reg[0]__0 [2]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE #(\n .INIT(1'b0)) \n \\rank_final_loop[0].final_do_max_reg[0][3] \n (.C(CLK),\n .CE(\\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ),\n .D(\\rank_final_loop[0].final_do_max[0][3]_i_1_n_0 ),\n .Q(\\rank_final_loop[0].final_do_max_reg[0]__0 [3]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE #(\n .INIT(1'b0)) \n \\rank_final_loop[0].final_do_max_reg[0][4] \n (.C(CLK),\n .CE(\\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ),\n .D(\\rank_final_loop[0].final_do_max[0][4]_i_1_n_0 ),\n .Q(\\rank_final_loop[0].final_do_max_reg[0]__0 [4]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE #(\n .INIT(1'b0)) \n \\rank_final_loop[0].final_do_max_reg[0][5] \n (.C(CLK),\n .CE(\\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ),\n .D(\\rank_final_loop[0].final_do_max[0][5]_i_2_n_0 ),\n .Q(\\rank_final_loop[0].final_do_max_reg[0]__0 [5]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n (* SOFT_HLUTNM = \"soft_lutpair278\" *) \n LUT5 #(\n .INIT(32'hAAAAAAA9)) \n \\rd_byte_data_offset[0][10]_i_1 \n (.I0(p_0_in[4]),\n .I1(\\rd_byte_data_offset_reg[0][9]_0 [1]),\n .I2(p_0_in[1]),\n .I3(p_0_in[0]),\n .I4(\\rd_byte_data_offset_reg[0][9]_0 [0]),\n .O(p_1_in[4]));\n LUT4 #(\n .INIT(16'hAAAB)) \n \\rd_byte_data_offset[0][11]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__23),\n .I1(\\rd_byte_data_offset[0][11]_i_4_n_0 ),\n .I2(\\rnk_cnt_r_reg_n_0_[1] ),\n .I3(\\rnk_cnt_r_reg_n_0_[0] ),\n .O(\\rd_byte_data_offset[0][11]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000080000000000)) \n \\rd_byte_data_offset[0][11]_i_2 \n (.I0(\\rd_byte_data_offset[0][5]_i_4_n_0 ),\n .I1(\\rd_byte_data_offset_reg[0]_3 ),\n .I2(\\pi_rst_stg1_cal_r_reg[0]_0 ),\n .I3(dqs_found_start_r),\n .I4(\\pi_dqs_found_all_bank_r_reg[1]_0 ),\n .I5(\\rd_byte_data_offset[0][11]_i_4_n_0 ),\n .O(\\rd_byte_data_offset[0][11]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAAAAA9)) \n \\rd_byte_data_offset[0][11]_i_3 \n (.I0(p_0_in[5]),\n .I1(p_0_in[4]),\n .I2(\\rd_byte_data_offset_reg[0][9]_0 [0]),\n .I3(p_0_in[0]),\n .I4(p_0_in[1]),\n .I5(\\rd_byte_data_offset_reg[0][9]_0 [1]),\n .O(p_1_in[5]));\n LUT6 #(\n .INIT(64'hBBBBBBB0BBB0BBB0)) \n \\rd_byte_data_offset[0][11]_i_4 \n (.I0(rd_data_offset_cal_done),\n .I1(rank_done_r1),\n .I2(p_0_in[4]),\n .I3(p_0_in[5]),\n .I4(\\rd_byte_data_offset_reg[0][9]_0 [0]),\n .I5(\\rd_byte_data_offset_reg[0][9]_0 [1]),\n .O(\\rd_byte_data_offset[0][11]_i_4_n_0 ));\n LUT4 #(\n .INIT(16'hAAAB)) \n \\rd_byte_data_offset[0][5]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__23),\n .I1(\\rd_byte_data_offset[0][5]_i_3_n_0 ),\n .I2(\\rnk_cnt_r_reg_n_0_[1] ),\n .I3(\\rnk_cnt_r_reg_n_0_[0] ),\n .O(\\rd_byte_data_offset[0][5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000080000000000)) \n \\rd_byte_data_offset[0][5]_i_2 \n (.I0(\\rd_byte_data_offset[0][5]_i_4_n_0 ),\n .I1(\\rd_byte_data_offset_reg[0]_3 ),\n .I2(\\pi_rst_stg1_cal_r_reg[0]_0 ),\n .I3(dqs_found_start_r),\n .I4(pi_dqs_found_all_bank),\n .I5(\\rd_byte_data_offset[0][5]_i_3_n_0 ),\n .O(rd_byte_data_offset));\n LUT6 #(\n .INIT(64'hFEEE0000FEEEFEEE)) \n \\rd_byte_data_offset[0][5]_i_3 \n (.I0(\\rd_byte_data_offset_reg_n_0_[0][4] ),\n .I1(\\rd_byte_data_offset_reg_n_0_[0][5] ),\n .I2(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [0]),\n .I3(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [1]),\n .I4(rd_data_offset_cal_done),\n .I5(rank_done_r1),\n .O(\\rd_byte_data_offset[0][5]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000001000)) \n \\rd_byte_data_offset[0][5]_i_4 \n (.I0(detect_rd_cnt_reg__0[3]),\n .I1(detect_rd_cnt_reg__0[2]),\n .I2(detect_pi_found_dqs),\n .I3(detect_rd_cnt_reg__0[0]),\n .I4(detect_rd_cnt_reg__0[1]),\n .I5(rd_data_offset_cal_done),\n .O(\\rd_byte_data_offset[0][5]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair298\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\rd_byte_data_offset[0][6]_i_1 \n (.I0(p_0_in[0]),\n .O(p_1_in[0]));\n (* SOFT_HLUTNM = \"soft_lutpair291\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\rd_byte_data_offset[0][7]_i_1 \n (.I0(p_0_in[0]),\n .I1(p_0_in[1]),\n .O(\\rd_byte_data_offset[0][7]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair298\" *) \n LUT3 #(\n .INIT(8'hA9)) \n \\rd_byte_data_offset[0][8]_i_1 \n (.I0(\\rd_byte_data_offset_reg[0][9]_0 [0]),\n .I1(p_0_in[1]),\n .I2(p_0_in[0]),\n .O(p_1_in[2]));\n (* SOFT_HLUTNM = \"soft_lutpair278\" *) \n LUT4 #(\n .INIT(16'hAAA9)) \n \\rd_byte_data_offset[0][9]_i_1 \n (.I0(\\rd_byte_data_offset_reg[0][9]_0 [1]),\n .I1(\\rd_byte_data_offset_reg[0][9]_0 [0]),\n .I2(p_0_in[0]),\n .I3(p_0_in[1]),\n .O(p_1_in[3]));\n FDRE #(\n .INIT(1'b0)) \n \\rd_byte_data_offset_reg[0][0] \n (.C(CLK),\n .CE(rd_byte_data_offset),\n .D(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0 ),\n .Q(\\rd_byte_data_offset_reg_n_0_[0][0] ),\n .R(\\rd_byte_data_offset[0][5]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\rd_byte_data_offset_reg[0][10] \n (.C(CLK),\n .CE(\\rd_byte_data_offset[0][11]_i_2_n_0 ),\n .D(p_1_in[4]),\n .Q(p_0_in[4]),\n .S(\\rd_byte_data_offset[0][11]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rd_byte_data_offset_reg[0][11] \n (.C(CLK),\n .CE(\\rd_byte_data_offset[0][11]_i_2_n_0 ),\n .D(p_1_in[5]),\n .Q(p_0_in[5]),\n .R(\\rd_byte_data_offset[0][11]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\rd_byte_data_offset_reg[0][1] \n (.C(CLK),\n .CE(rd_byte_data_offset),\n .D(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1_n_0 ),\n .Q(\\rd_byte_data_offset_reg_n_0_[0][1] ),\n .S(\\rd_byte_data_offset[0][5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rd_byte_data_offset_reg[0][2] \n (.C(CLK),\n .CE(rd_byte_data_offset),\n .D(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1_n_0 ),\n .Q(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [0]),\n .R(\\rd_byte_data_offset[0][5]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\rd_byte_data_offset_reg[0][3] \n (.C(CLK),\n .CE(rd_byte_data_offset),\n .D(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1_n_0 ),\n .Q(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [1]),\n .S(\\rd_byte_data_offset[0][5]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\rd_byte_data_offset_reg[0][4] \n (.C(CLK),\n .CE(rd_byte_data_offset),\n .D(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1_n_0 ),\n .Q(\\rd_byte_data_offset_reg_n_0_[0][4] ),\n .S(\\rd_byte_data_offset[0][5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rd_byte_data_offset_reg[0][5] \n (.C(CLK),\n .CE(rd_byte_data_offset),\n .D(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2_n_0 ),\n .Q(\\rd_byte_data_offset_reg_n_0_[0][5] ),\n .R(\\rd_byte_data_offset[0][5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rd_byte_data_offset_reg[0][6] \n (.C(CLK),\n .CE(\\rd_byte_data_offset[0][11]_i_2_n_0 ),\n .D(p_1_in[0]),\n .Q(p_0_in[0]),\n .R(\\rd_byte_data_offset[0][11]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\rd_byte_data_offset_reg[0][7] \n (.C(CLK),\n .CE(\\rd_byte_data_offset[0][11]_i_2_n_0 ),\n .D(\\rd_byte_data_offset[0][7]_i_1_n_0 ),\n .Q(p_0_in[1]),\n .S(\\rd_byte_data_offset[0][11]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rd_byte_data_offset_reg[0][8] \n (.C(CLK),\n .CE(\\rd_byte_data_offset[0][11]_i_2_n_0 ),\n .D(p_1_in[2]),\n .Q(\\rd_byte_data_offset_reg[0][9]_0 [0]),\n .R(\\rd_byte_data_offset[0][11]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\rd_byte_data_offset_reg[0][9] \n (.C(CLK),\n .CE(\\rd_byte_data_offset[0][11]_i_2_n_0 ),\n .D(p_1_in[3]),\n .Q(\\rd_byte_data_offset_reg[0][9]_0 [1]),\n .S(\\rd_byte_data_offset[0][11]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair294\" *) \n LUT3 #(\n .INIT(8'hD2)) \n \\rnk_cnt_r[0]_i_1 \n (.I0(pi_dqs_found_rank_done),\n .I1(rd_data_offset_cal_done),\n .I2(\\rnk_cnt_r_reg_n_0_[0] ),\n .O(\\rnk_cnt_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair294\" *) \n LUT4 #(\n .INIT(16'hF708)) \n \\rnk_cnt_r[1]_i_1 \n (.I0(\\rnk_cnt_r_reg_n_0_[0] ),\n .I1(pi_dqs_found_rank_done),\n .I2(rd_data_offset_cal_done),\n .I3(\\rnk_cnt_r_reg_n_0_[1] ),\n .O(\\rnk_cnt_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rnk_cnt_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rnk_cnt_r[0]_i_1_n_0 ),\n .Q(\\rnk_cnt_r_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n \\rnk_cnt_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rnk_cnt_r[1]_i_1_n_0 ),\n .Q(\\rnk_cnt_r_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n LUT5 #(\n .INIT(32'h8800FF30)) \n rst_dqs_find_i_2\n (.I0(prech_done),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]),\n .I2(init_dqsfound_done_r5),\n .I3(rst_dqs_find_i_5_n_0),\n .I4(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .O(rst_dqs_find));\n LUT6 #(\n .INIT(64'hBB00BB0030333000)) \n rst_dqs_find_i_3\n (.I0(prech_done),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I2(rst_dqs_find_i_6_n_0),\n .I3(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .I4(p_1_in27_in),\n .I5(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .O(rst_dqs_find_reg_1));\n LUT6 #(\n .INIT(64'h0000004F00000040)) \n rst_dqs_find_i_4\n (.I0(pi_dqs_found_any_bank),\n .I1(rst_dqs_find_r2),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I3(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .I4(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .I5(init_dqsfound_done_r5),\n .O(rst_dqs_find_reg_0));\n LUT5 #(\n .INIT(32'hFFFF8A80)) \n rst_dqs_find_i_5\n (.I0(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .I1(\\first_fail_taps[5]_i_4_n_0 ),\n .I2(fine_adj_state_r144_out),\n .I3(first_fail_detect_i_2_n_0),\n .I4(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .O(rst_dqs_find_i_5_n_0));\n LUT6 #(\n .INIT(64'h40F0F0F040000000)) \n rst_dqs_find_i_6\n (.I0(fine_adj_state_r16_out),\n .I1(first_fail_detect_i_2_n_0),\n .I2(detect_pi_found_dqs),\n .I3(\\pi_dqs_found_all_bank_r_reg[1]_0 ),\n .I4(pi_dqs_found_all_bank),\n .I5(\\dec_cnt[5]_i_10_n_0 ),\n .O(rst_dqs_find_i_6_n_0));\n FDRE #(\n .INIT(1'b0)) \n rst_dqs_find_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rst_dqs_find_r1_reg_0),\n .Q(rst_dqs_find_r1),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n rst_dqs_find_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rst_dqs_find_r1),\n .Q(rst_dqs_find_r2),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n rst_dqs_find_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_fine_adj_state_r_reg[1]_0 ),\n .Q(rst_dqs_find_r1_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__13));\n (* SOFT_HLUTNM = \"soft_lutpair277\" *) \n LUT4 #(\n .INIT(16'h4055)) \n \\stable_pass_cnt[0]_i_1 \n (.I0(\\stable_pass_cnt_reg_n_0_[0] ),\n .I1(pi_dqs_found_all_bank),\n .I2(\\pi_dqs_found_all_bank_r_reg[1]_0 ),\n .I3(detect_pi_found_dqs),\n .O(p_0_in__1[0]));\n (* SOFT_HLUTNM = \"soft_lutpair277\" *) \n LUT5 #(\n .INIT(32'h60006666)) \n \\stable_pass_cnt[1]_i_1 \n (.I0(stable_pass_cnt_reg__0[1]),\n .I1(\\stable_pass_cnt_reg_n_0_[0] ),\n .I2(pi_dqs_found_all_bank),\n .I3(\\pi_dqs_found_all_bank_r_reg[1]_0 ),\n .I4(detect_pi_found_dqs),\n .O(p_0_in__1[1]));\n LUT6 #(\n .INIT(64'h7800000078787878)) \n \\stable_pass_cnt[2]_i_1 \n (.I0(\\stable_pass_cnt_reg_n_0_[0] ),\n .I1(stable_pass_cnt_reg__0[1]),\n .I2(stable_pass_cnt_reg__0[2]),\n .I3(pi_dqs_found_all_bank),\n .I4(\\pi_dqs_found_all_bank_r_reg[1]_0 ),\n .I5(detect_pi_found_dqs),\n .O(p_0_in__1[2]));\n (* SOFT_HLUTNM = \"soft_lutpair276\" *) \n LUT5 #(\n .INIT(32'h15554000)) \n \\stable_pass_cnt[3]_i_1 \n (.I0(fine_adj_state_r144_out),\n .I1(stable_pass_cnt_reg__0[2]),\n .I2(stable_pass_cnt_reg__0[1]),\n .I3(\\stable_pass_cnt_reg_n_0_[0] ),\n .I4(stable_pass_cnt_reg__0[3]),\n .O(\\stable_pass_cnt[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h000000007FFF8000)) \n \\stable_pass_cnt[4]_i_1 \n (.I0(\\stable_pass_cnt_reg_n_0_[0] ),\n .I1(stable_pass_cnt_reg__0[1]),\n .I2(stable_pass_cnt_reg__0[2]),\n .I3(stable_pass_cnt_reg__0[3]),\n .I4(stable_pass_cnt_reg__0[4]),\n .I5(fine_adj_state_r144_out),\n .O(p_0_in__1[4]));\n LUT5 #(\n .INIT(32'h00200000)) \n \\stable_pass_cnt[5]_i_1 \n (.I0(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .I3(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I4(detect_pi_found_dqs),\n .O(stable_pass_cnt));\n LUT5 #(\n .INIT(32'h15554000)) \n \\stable_pass_cnt[5]_i_2 \n (.I0(fine_adj_state_r144_out),\n .I1(stable_pass_cnt_reg__0[4]),\n .I2(stable_pass_cnt_reg__0[3]),\n .I3(\\stable_pass_cnt[5]_i_3_n_0 ),\n .I4(stable_pass_cnt_reg__0[5]),\n .O(\\stable_pass_cnt[5]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair276\" *) \n LUT3 #(\n .INIT(8'h80)) \n \\stable_pass_cnt[5]_i_3 \n (.I0(stable_pass_cnt_reg__0[2]),\n .I1(stable_pass_cnt_reg__0[1]),\n .I2(\\stable_pass_cnt_reg_n_0_[0] ),\n .O(\\stable_pass_cnt[5]_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\stable_pass_cnt_reg[0] \n (.C(CLK),\n .CE(stable_pass_cnt),\n .D(p_0_in__1[0]),\n .Q(\\stable_pass_cnt_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE #(\n .INIT(1'b0)) \n \\stable_pass_cnt_reg[1] \n (.C(CLK),\n .CE(stable_pass_cnt),\n .D(p_0_in__1[1]),\n .Q(stable_pass_cnt_reg__0[1]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE #(\n .INIT(1'b0)) \n \\stable_pass_cnt_reg[2] \n (.C(CLK),\n .CE(stable_pass_cnt),\n .D(p_0_in__1[2]),\n .Q(stable_pass_cnt_reg__0[2]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE #(\n .INIT(1'b0)) \n \\stable_pass_cnt_reg[3] \n (.C(CLK),\n .CE(stable_pass_cnt),\n .D(\\stable_pass_cnt[3]_i_1_n_0 ),\n .Q(stable_pass_cnt_reg__0[3]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE #(\n .INIT(1'b0)) \n \\stable_pass_cnt_reg[4] \n (.C(CLK),\n .CE(stable_pass_cnt),\n .D(p_0_in__1[4]),\n .Q(stable_pass_cnt_reg__0[4]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE #(\n .INIT(1'b0)) \n \\stable_pass_cnt_reg[5] \n (.C(CLK),\n .CE(stable_pass_cnt),\n .D(\\stable_pass_cnt[5]_i_2_n_0 ),\n .Q(stable_pass_cnt_reg__0[5]),\n .R(rstdiv0_sync_r1_reg_rep__2));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_phy_init\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_phy_init\n (prbs_rdlvl_done_r1,\n prech_done,\n rdlvl_start_pre,\n rdlvl_start_dly0_r,\n in0,\n out,\n cnt_cmd_done_r,\n wrlvl_done_r1,\n prbs_last_byte_done_r,\n prech_pending_r_reg_0,\n pi_calib_done,\n wrcal_resume_r,\n complex_ocal_reset_rd_addr,\n wl_sm_start,\n wrcal_rd_wait,\n wrcal_sanity_chk,\n detect_pi_found_dqs,\n mpr_end_if_reset,\n init_complete_r1_reg_0,\n calib_complete,\n cnt_pwron_reset_done_r,\n cnt_pwron_cke_done_r,\n pi_dqs_found_done_r1,\n complex_act_start,\n \\oclkdelay_ref_cnt_reg[13]_0 ,\n cnt_txpr_done_r,\n cnt_dllk_zqinit_done_r,\n cnt_init_mr_done_r,\n ddr2_refresh_flag_r,\n ddr2_pre_flag_r_reg_0,\n cnt_init_af_done_r,\n burst_addr_r_reg_0,\n prech_pending_r,\n rdlvl_stg1_start_r_reg,\n ocal_last_byte_done,\n \\rd_ptr_timing_reg[0] ,\n phy_dout,\n reset_if_reg,\n oclk_calib_resume_level_reg_0,\n Q,\n \\odd_cwl.phy_cas_n_reg[1]_0 ,\n \\cnt_init_mr_r_reg[1]_0 ,\n \\init_state_r_reg[1]_0 ,\n cnt_init_mr_r,\n complex_oclkdelay_calib_start_int_reg_0,\n \\reg_ctrl_cnt_r_reg[3]_0 ,\n \\one_rank.stg1_wr_done_reg_0 ,\n \\init_state_r_reg[2]_0 ,\n mem_init_done_r,\n \\victim_sel_rotate.sel_reg[31] ,\n new_cnt_dqs_r_reg,\n prbs_rdlvl_start_r_reg,\n first_wrcal_pat_r,\n D2,\n D0,\n D3,\n D5,\n D6,\n D1,\n \\rd_ptr_timing_reg[0]_0 ,\n D7,\n D8,\n \\rd_ptr_timing_reg[0]_1 ,\n \\my_empty_reg[7] ,\n \\my_empty_reg[7]_0 ,\n \\my_empty_reg[7]_1 ,\n D4,\n \\my_empty_reg[7]_2 ,\n \\my_empty_reg[7]_3 ,\n \\my_empty_reg[7]_4 ,\n \\my_empty_reg[7]_5 ,\n \\rd_ptr_timing_reg[0]_2 ,\n D9,\n \\my_empty_reg[7]_6 ,\n \\my_empty_reg[7]_7 ,\n \\my_empty_reg[7]_8 ,\n \\my_empty_reg[7]_9 ,\n \\my_empty_reg[7]_10 ,\n \\my_empty_reg[7]_11 ,\n \\my_empty_reg[7]_12 ,\n \\my_empty_reg[7]_13 ,\n \\my_empty_reg[7]_14 ,\n \\my_empty_reg[7]_15 ,\n \\my_empty_reg[7]_16 ,\n \\my_empty_reg[7]_17 ,\n \\my_empty_reg[7]_18 ,\n \\my_empty_reg[7]_19 ,\n \\my_empty_reg[7]_20 ,\n \\my_empty_reg[7]_21 ,\n \\my_empty_reg[7]_22 ,\n \\my_empty_reg[7]_23 ,\n \\my_empty_reg[7]_24 ,\n \\my_empty_reg[7]_25 ,\n \\my_empty_reg[7]_26 ,\n \\my_empty_reg[7]_27 ,\n \\my_empty_reg[7]_28 ,\n \\my_empty_reg[7]_29 ,\n \\my_empty_reg[7]_30 ,\n \\my_empty_reg[7]_31 ,\n \\my_empty_reg[7]_32 ,\n \\my_empty_reg[7]_33 ,\n \\my_empty_reg[7]_34 ,\n \\my_empty_reg[7]_35 ,\n \\my_empty_reg[7]_36 ,\n \\my_empty_reg[7]_37 ,\n lim_start_r_reg,\n cal1_state_r1535_out,\n mpr_rdlvl_start_r_reg,\n E,\n \\cnt_shift_r_reg[0] ,\n cnt_init_mr_r1,\n prech_pending_r_reg_1,\n rdlvl_start_pre_reg_0,\n read_calib_reg_0,\n temp_lmr_done,\n stg1_wr_done,\n \\back_to_back_reads_4_1.num_reads_reg[0]_0 ,\n \\back_to_back_reads_4_1.num_reads_reg[1]_0 ,\n \\init_state_r_reg[4]_0 ,\n burst_addr_r_reg_1,\n oclkdelay_int_ref_req_reg_0,\n \\init_state_r_reg[5]_0 ,\n ddr2_pre_flag_r_reg_1,\n ddr2_refresh_flag_r_reg_0,\n \\en_cnt_div4.enable_wrlvl_cnt_reg[3]_0 ,\n \\complex_row_cnt_ocal_reg[0]_0 ,\n ddr3_lm_done_r,\n \\row_cnt_victim_rotate.complex_row_cnt_reg[4]_0 ,\n cnt_pwron_reset_done_r_reg_0,\n \\cnt_pwron_r_reg[7]_0 ,\n cnt_pwron_cke_done_r_reg_0,\n \\cnt_txpr_r_reg[2]_0 ,\n mem_init_done_r_reg_0,\n mem_init_done_r_reg_1,\n \\init_state_r_reg[0]_0 ,\n rdlvl_stg1_start_int,\n \\init_state_r_reg[2]_1 ,\n cnt_txpr_done_r_reg_0,\n \\pi_dqs_found_all_bank_reg[1] ,\n dqs_found_start_r_reg,\n mux_wrdata_en,\n mux_cmd_wren,\n mux_reset_n,\n \\data_offset_1_i1_reg[5] ,\n \\rd_ptr_timing_reg[0]_3 ,\n \\my_full_reg[3] ,\n \\phy_ctl_wd_i1_reg[24] ,\n \\my_empty_reg[7]_38 ,\n \\my_empty_reg[7]_39 ,\n \\my_empty_reg[7]_40 ,\n \\my_empty_reg[7]_41 ,\n \\samples_cnt_r_reg[11] ,\n \\wrcal_dqs_cnt_r_reg[0] ,\n \\rd_addr_reg_rep[7] ,\n \\rd_addr_reg[0] ,\n cnt_init_af_r,\n wrlvl_final_if_rst,\n wr_level_start_r_reg,\n wrcal_start_reg_0,\n phy_write_calib,\n phy_read_calib,\n first_rdlvl_pat_r,\n prbs_rdlvl_done_reg_rep,\n CLK,\n rdlvl_stg1_done_int_reg,\n A_rst_primitives_reg,\n rstdiv0_sync_r1_reg_rep__11,\n wr_level_done_reg,\n prbs_last_byte_done,\n wrlvl_rank_done,\n prbs_rdlvl_done_pulse0,\n rstdiv0_sync_r1_reg_rep__12,\n reset_rd_addr0,\n prech_req,\n wrcal_resume_w,\n rdlvl_last_byte_done,\n dqs_found_done_r_reg,\n rstdiv0_sync_r1_reg_rep__10,\n cnt_pwron_cke_done_r_reg_1,\n cnt_txpr_done_r_reg_1,\n cnt_dllk_zqinit_done_r_reg_0,\n cnt_init_mr_done_r_reg_0,\n cnt_cmd_done_r_reg_0,\n ddr2_pre_flag_r_reg_2,\n cnt_init_af_done_r_reg_0,\n burst_addr_r_reg_2,\n prech_req_posedge_r_reg_0,\n \\init_state_r_reg[0]_1 ,\n \\rdlvl_start_dly0_r_reg[14]_0 ,\n \\init_state_r_reg[6]_0 ,\n \\cnt_pwron_r_reg[7]_1 ,\n \\init_state_r_reg[6]_1 ,\n oclkdelay_center_calib_done_r_reg,\n rdlvl_stg1_done_int_reg_0,\n oclkdelay_calib_done_r_reg,\n oclkdelay_calib_done_r_reg_0,\n \\dout_o_reg[11] ,\n \\dout_o_reg[11]_0 ,\n D,\n wrcal_done_reg,\n \\dout_o_reg[9] ,\n \\dout_o_reg[9]_0 ,\n \\dout_o_reg[11]_1 ,\n \\dout_o_reg[11]_2 ,\n \\dout_o_reg[13] ,\n \\dout_o_reg[13]_0 ,\n wrcal_done_reg_0,\n \\dout_o_reg[9]_1 ,\n \\dout_o_reg[9]_2 ,\n \\dout_o_reg[9]_3 ,\n \\dout_o_reg[9]_4 ,\n \\dout_o_reg[13]_1 ,\n \\dout_o_reg[13]_2 ,\n \\dout_o_reg[1] ,\n \\dout_o_reg[1]_0 ,\n \\dout_o_reg[13]_3 ,\n \\dout_o_reg[13]_4 ,\n oclkdelay_calib_done_r_reg_1,\n \\dout_o_reg[11]_3 ,\n \\dout_o_reg[11]_4 ,\n \\dout_o_reg[13]_5 ,\n \\dout_o_reg[13]_6 ,\n \\dout_o_reg[15] ,\n \\dout_o_reg[7] ,\n \\dout_o_reg[15]_0 ,\n \\dout_o_reg[15]_1 ,\n \\dout_o_reg[7]_0 ,\n \\dout_o_reg[15]_2 ,\n wrcal_done_reg_1,\n \\dout_o_reg[3] ,\n \\dout_o_reg[3]_0 ,\n \\dout_o_reg[7]_1 ,\n \\dout_o_reg[7]_2 ,\n \\dout_o_reg[8] ,\n \\dout_o_reg[8]_0 ,\n \\dout_o_reg[14] ,\n \\dout_o_reg[14]_0 ,\n \\dout_o_reg[6] ,\n \\dout_o_reg[14]_1 ,\n \\dout_o_reg[14]_2 ,\n first_rdlvl_pat_r_reg_0,\n wrcal_done_reg_2,\n \\dout_o_reg[2] ,\n \\dout_o_reg[2]_0 ,\n \\dout_o_reg[4] ,\n \\dout_o_reg[4]_0 ,\n \\dout_o_reg[8]_1 ,\n \\dout_o_reg[8]_2 ,\n \\dout_o_reg[10] ,\n \\dout_o_reg[10]_0 ,\n \\dout_o_reg[8]_3 ,\n \\dout_o_reg[8]_4 ,\n \\dout_o_reg[12] ,\n \\dout_o_reg[12]_0 ,\n wrcal_done_reg_3,\n wrcal_done_reg_4,\n wrcal_done_reg_5,\n wrcal_done_reg_6,\n wrcal_done_reg_7,\n wrcal_done_reg_8,\n init_calib_complete_reg_rep__13,\n rstdiv0_sync_r1_reg_rep__24,\n reset_if_r9,\n prbs_rdlvl_done_reg,\n reset_if,\n delay_done_r4_reg,\n dqs_found_done_r_reg_0,\n wrcal_done_reg_9,\n oclkdelay_center_calib_start_r_reg,\n oclk_calib_resume_r_reg,\n prbs_rdlvl_done_reg_rep_0,\n complex_oclk_calib_resume,\n pi_dqs_found_rank_done,\n wrcal_sanity_chk_done_reg,\n wrcal_done_reg_10,\n wrlvl_byte_redo,\n wrcal_prech_req,\n \\init_state_r_reg[1]_1 ,\n prbs_rdlvl_start_r,\n oclkdelay_calib_done_r_reg_2,\n mc_cas_n,\n init_calib_complete_reg_rep__6,\n \\rd_ptr_reg[3] ,\n \\my_empty_reg[1] ,\n mem_out,\n \\my_empty_reg[1]_0 ,\n mc_ras_n,\n mc_odt,\n \\rd_ptr_reg[3]_0 ,\n \\my_empty_reg[1]_1 ,\n mc_cke,\n mc_we_n,\n mc_address,\n \\rd_ptr_reg[3]_1 ,\n \\my_empty_reg[1]_2 ,\n init_calib_complete_reg_rep__5,\n mc_bank,\n \\write_buffer.wr_buf_out_data_reg[255] ,\n \\rd_ptr_reg[3]_2 ,\n \\my_empty_reg[1]_3 ,\n \\rd_ptr_reg[3]_3 ,\n \\my_empty_reg[1]_4 ,\n init_calib_complete_reg_rep__4,\n \\rd_ptr_reg[3]_4 ,\n \\my_empty_reg[1]_5 ,\n \\rd_ptr_reg[3]_5 ,\n \\my_empty_reg[1]_6 ,\n init_calib_complete_reg_rep__3,\n init_calib_complete_reg_rep__2,\n init_calib_complete_reg_rep__1,\n init_calib_complete_reg_rep__0,\n init_calib_complete_reg_rep,\n \\rd_byte_data_offset_reg[0][3] ,\n init_dqsfound_done_r2,\n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3] ,\n \\rd_byte_data_offset_reg[0][9] ,\n \\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] ,\n mpr_rdlvl_start_r,\n phy_rddata_en_1,\n mpr_rdlvl_done_r_reg,\n \\cnt_shift_r_reg[0]_0 ,\n rstdiv0_sync_r1_reg_rep__22,\n \\mcGo_r_reg[15] ,\n ck_addr_cmd_delay_done,\n prbs_rdlvl_done_reg_0,\n wrlvl_final_mux,\n mpr_rdlvl_done_r_reg_0,\n \\init_state_r_reg[2]_2 ,\n rstdiv0_sync_r1_reg_rep__23,\n rdlvl_pi_incdec,\n dqs_found_prech_req,\n prbs_rdlvl_prech_req_reg,\n complex_ocal_ref_req,\n rdlvl_prech_req,\n complex_pi_incdec_done,\n wrcal_done_reg_11,\n rdlvl_stg1_done_int_reg_1,\n phy_if_empty_r_reg,\n wrcal_sanity_chk_done_reg_0,\n rdlvl_stg1_done_int_reg_2,\n oclkdelay_calib_done_r_reg_3,\n lim2init_prech_req,\n ocd_prech_req,\n oclkdelay_calib_done_r_reg_4,\n cnt_cmd_done_r_reg_1,\n oclkdelay_center_calib_start_r_reg_0,\n oclk_calib_resume_r_reg_0,\n mpr_rdlvl_done_r_reg_1,\n dqs_found_done_r_reg_1,\n wrlvl_byte_redo_reg,\n mpr_rdlvl_done_r_reg_2,\n oclkdelay_center_calib_done_r_reg_0,\n complex_victim_inc_reg,\n complex_ocal_num_samples_done_r,\n reset_rd_addr,\n dqs_found_done_r_reg_2,\n prbs_last_byte_done_reg,\n \\rd_victim_sel_reg[1] ,\n \\rd_victim_sel_reg[0] ,\n \\rd_victim_sel_reg[2] ,\n cnt_init_af_done_r_reg_1,\n num_samples_done_r,\n complex_init_pi_dec_done,\n done_r_reg,\n rdlvl_stg1_rank_done,\n write_request_r_reg,\n complex_ocal_rd_victim_sel,\n prbs_rdlvl_done_reg_rep_1,\n prbs_rdlvl_done_reg_rep_2,\n wrlvl_final_mux_reg,\n oclkdelay_calib_done_r_reg_5,\n wrlvl_byte_redo_reg_0,\n mem_init_done_r_reg_2,\n rdlvl_stg1_done_int_reg_3,\n wrlvl_final_mux_reg_0,\n prbs_rdlvl_done_reg_rep_3,\n mpr_last_byte_done,\n rdlvl_stg1_done_int_reg_4,\n \\dout_o_reg[0] ,\n \\dout_o_reg[0]_0 ,\n \\pi_dqs_found_all_bank_reg[1]_0 ,\n mc_wrdata_en,\n init_calib_complete_reg_rep__14,\n \\cmd_pipe_plus.mc_data_offset_1_reg[0] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[1] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[2] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[3] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[4] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[5] ,\n mc_cmd,\n \\cmd_pipe_plus.mc_data_offset_reg[0] ,\n \\cmd_pipe_plus.mc_data_offset_reg[1] ,\n \\cmd_pipe_plus.mc_data_offset_reg[2] ,\n \\cmd_pipe_plus.mc_data_offset_reg[3] ,\n \\cmd_pipe_plus.mc_data_offset_reg[4] ,\n \\cmd_pipe_plus.mc_data_offset_reg[5] ,\n init_calib_complete_reg_rep__12,\n init_calib_complete_reg_rep__11,\n init_calib_complete_reg_rep__10,\n init_calib_complete_reg_rep__9,\n init_calib_complete_reg_rep__8,\n init_calib_complete_reg_rep__7,\n \\samples_cnt_r_reg[11]_0 ,\n wrcal_sanity_chk_r_reg,\n \\rd_addr_reg[3] ,\n rstdiv0_sync_r1_reg_rep__20,\n rstdiv0_sync_r1_reg_rep__23_0,\n done_dqs_tap_inc,\n p_81_in,\n rstdiv0_sync_r1_reg_rep__23_1,\n pi_dqs_found_done_r1_reg_0,\n pi_dqs_found_done_r1_reg_1,\n pi_dqs_found_done_r1_reg_2,\n pi_dqs_found_done_r1_reg_3,\n pi_dqs_found_done_r1_reg_4,\n pi_dqs_found_done_r1_reg_5,\n pi_dqs_found_done_r1_reg_6,\n pi_dqs_found_done_r1_reg_7,\n rstdiv0_sync_r1_reg_rep__19,\n rstdiv0_sync_r1_reg_rep__18);\n output prbs_rdlvl_done_r1;\n output prech_done;\n output rdlvl_start_pre;\n output [0:0]rdlvl_start_dly0_r;\n output in0;\n output out;\n output cnt_cmd_done_r;\n output wrlvl_done_r1;\n output prbs_last_byte_done_r;\n output prech_pending_r_reg_0;\n output pi_calib_done;\n output wrcal_resume_r;\n output complex_ocal_reset_rd_addr;\n output wl_sm_start;\n output wrcal_rd_wait;\n output wrcal_sanity_chk;\n output detect_pi_found_dqs;\n output mpr_end_if_reset;\n output init_complete_r1_reg_0;\n output calib_complete;\n output cnt_pwron_reset_done_r;\n output cnt_pwron_cke_done_r;\n output pi_dqs_found_done_r1;\n output complex_act_start;\n output \\oclkdelay_ref_cnt_reg[13]_0 ;\n output cnt_txpr_done_r;\n output cnt_dllk_zqinit_done_r;\n output cnt_init_mr_done_r;\n output ddr2_refresh_flag_r;\n output ddr2_pre_flag_r_reg_0;\n output cnt_init_af_done_r;\n output burst_addr_r_reg_0;\n output prech_pending_r;\n output rdlvl_stg1_start_r_reg;\n output ocal_last_byte_done;\n output [33:0]\\rd_ptr_timing_reg[0] ;\n output [31:0]phy_dout;\n output reset_if_reg;\n output oclk_calib_resume_level_reg_0;\n output [5:0]Q;\n output \\odd_cwl.phy_cas_n_reg[1]_0 ;\n output \\cnt_init_mr_r_reg[1]_0 ;\n output \\init_state_r_reg[1]_0 ;\n output [1:0]cnt_init_mr_r;\n output complex_oclkdelay_calib_start_int_reg_0;\n output \\reg_ctrl_cnt_r_reg[3]_0 ;\n output \\one_rank.stg1_wr_done_reg_0 ;\n output \\init_state_r_reg[2]_0 ;\n output mem_init_done_r;\n output [7:0]\\victim_sel_rotate.sel_reg[31] ;\n output new_cnt_dqs_r_reg;\n output prbs_rdlvl_start_r_reg;\n output first_wrcal_pat_r;\n output [0:0]D2;\n output [0:0]D0;\n output [0:0]D3;\n output [3:0]D5;\n output [3:0]D6;\n output [0:0]D1;\n output [7:0]\\rd_ptr_timing_reg[0]_0 ;\n output [3:0]D7;\n output [3:0]D8;\n output [7:0]\\rd_ptr_timing_reg[0]_1 ;\n output [3:0]\\my_empty_reg[7] ;\n output [3:0]\\my_empty_reg[7]_0 ;\n output [3:0]\\my_empty_reg[7]_1 ;\n output [3:0]D4;\n output [3:0]\\my_empty_reg[7]_2 ;\n output [3:0]\\my_empty_reg[7]_3 ;\n output [3:0]\\my_empty_reg[7]_4 ;\n output [3:0]\\my_empty_reg[7]_5 ;\n output [3:0]\\rd_ptr_timing_reg[0]_2 ;\n output [3:0]D9;\n output [7:0]\\my_empty_reg[7]_6 ;\n output [7:0]\\my_empty_reg[7]_7 ;\n output [7:0]\\my_empty_reg[7]_8 ;\n output [7:0]\\my_empty_reg[7]_9 ;\n output [7:0]\\my_empty_reg[7]_10 ;\n output [7:0]\\my_empty_reg[7]_11 ;\n output [7:0]\\my_empty_reg[7]_12 ;\n output [7:0]\\my_empty_reg[7]_13 ;\n output [7:0]\\my_empty_reg[7]_14 ;\n output [7:0]\\my_empty_reg[7]_15 ;\n output [7:0]\\my_empty_reg[7]_16 ;\n output [7:0]\\my_empty_reg[7]_17 ;\n output [7:0]\\my_empty_reg[7]_18 ;\n output [7:0]\\my_empty_reg[7]_19 ;\n output [7:0]\\my_empty_reg[7]_20 ;\n output [7:0]\\my_empty_reg[7]_21 ;\n output [7:0]\\my_empty_reg[7]_22 ;\n output [7:0]\\my_empty_reg[7]_23 ;\n output [7:0]\\my_empty_reg[7]_24 ;\n output [7:0]\\my_empty_reg[7]_25 ;\n output [7:0]\\my_empty_reg[7]_26 ;\n output [7:0]\\my_empty_reg[7]_27 ;\n output [7:0]\\my_empty_reg[7]_28 ;\n output [7:0]\\my_empty_reg[7]_29 ;\n output [7:0]\\my_empty_reg[7]_30 ;\n output [7:0]\\my_empty_reg[7]_31 ;\n output [7:0]\\my_empty_reg[7]_32 ;\n output [7:0]\\my_empty_reg[7]_33 ;\n output [7:0]\\my_empty_reg[7]_34 ;\n output [7:0]\\my_empty_reg[7]_35 ;\n output [7:0]\\my_empty_reg[7]_36 ;\n output [7:0]\\my_empty_reg[7]_37 ;\n output lim_start_r_reg;\n output cal1_state_r1535_out;\n output mpr_rdlvl_start_r_reg;\n output [0:0]E;\n output [0:0]\\cnt_shift_r_reg[0] ;\n output cnt_init_mr_r1;\n output prech_pending_r_reg_1;\n output rdlvl_start_pre_reg_0;\n output read_calib_reg_0;\n output temp_lmr_done;\n output stg1_wr_done;\n output \\back_to_back_reads_4_1.num_reads_reg[0]_0 ;\n output \\back_to_back_reads_4_1.num_reads_reg[1]_0 ;\n output \\init_state_r_reg[4]_0 ;\n output burst_addr_r_reg_1;\n output oclkdelay_int_ref_req_reg_0;\n output \\init_state_r_reg[5]_0 ;\n output ddr2_pre_flag_r_reg_1;\n output ddr2_refresh_flag_r_reg_0;\n output \\en_cnt_div4.enable_wrlvl_cnt_reg[3]_0 ;\n output \\complex_row_cnt_ocal_reg[0]_0 ;\n output ddr3_lm_done_r;\n output \\row_cnt_victim_rotate.complex_row_cnt_reg[4]_0 ;\n output cnt_pwron_reset_done_r_reg_0;\n output [3:0]\\cnt_pwron_r_reg[7]_0 ;\n output cnt_pwron_cke_done_r_reg_0;\n output [2:0]\\cnt_txpr_r_reg[2]_0 ;\n output [1:0]mem_init_done_r_reg_0;\n output mem_init_done_r_reg_1;\n output \\init_state_r_reg[0]_0 ;\n output rdlvl_stg1_start_int;\n output \\init_state_r_reg[2]_1 ;\n output cnt_txpr_done_r_reg_0;\n output \\pi_dqs_found_all_bank_reg[1] ;\n output dqs_found_start_r_reg;\n output mux_wrdata_en;\n output mux_cmd_wren;\n output mux_reset_n;\n output [5:0]\\data_offset_1_i1_reg[5] ;\n output [1:0]\\rd_ptr_timing_reg[0]_3 ;\n output [1:0]\\my_full_reg[3] ;\n output [10:0]\\phy_ctl_wd_i1_reg[24] ;\n output [63:0]\\my_empty_reg[7]_38 ;\n output [63:0]\\my_empty_reg[7]_39 ;\n output [63:0]\\my_empty_reg[7]_40 ;\n output [63:0]\\my_empty_reg[7]_41 ;\n output [0:0]\\samples_cnt_r_reg[11] ;\n output \\wrcal_dqs_cnt_r_reg[0] ;\n output \\rd_addr_reg_rep[7] ;\n output [0:0]\\rd_addr_reg[0] ;\n output [1:0]cnt_init_af_r;\n output wrlvl_final_if_rst;\n output wr_level_start_r_reg;\n output wrcal_start_reg_0;\n output phy_write_calib;\n output phy_read_calib;\n output first_rdlvl_pat_r;\n input prbs_rdlvl_done_reg_rep;\n input CLK;\n input rdlvl_stg1_done_int_reg;\n input A_rst_primitives_reg;\n input rstdiv0_sync_r1_reg_rep__11;\n input wr_level_done_reg;\n input prbs_last_byte_done;\n input wrlvl_rank_done;\n input prbs_rdlvl_done_pulse0;\n input [0:0]rstdiv0_sync_r1_reg_rep__12;\n input reset_rd_addr0;\n input prech_req;\n input wrcal_resume_w;\n input rdlvl_last_byte_done;\n input dqs_found_done_r_reg;\n input rstdiv0_sync_r1_reg_rep__10;\n input cnt_pwron_cke_done_r_reg_1;\n input cnt_txpr_done_r_reg_1;\n input cnt_dllk_zqinit_done_r_reg_0;\n input cnt_init_mr_done_r_reg_0;\n input cnt_cmd_done_r_reg_0;\n input ddr2_pre_flag_r_reg_2;\n input cnt_init_af_done_r_reg_0;\n input burst_addr_r_reg_2;\n input prech_req_posedge_r_reg_0;\n input \\init_state_r_reg[0]_1 ;\n input \\rdlvl_start_dly0_r_reg[14]_0 ;\n input \\init_state_r_reg[6]_0 ;\n input \\cnt_pwron_r_reg[7]_1 ;\n input \\init_state_r_reg[6]_1 ;\n input oclkdelay_center_calib_done_r_reg;\n input rdlvl_stg1_done_int_reg_0;\n input oclkdelay_calib_done_r_reg;\n input oclkdelay_calib_done_r_reg_0;\n input \\dout_o_reg[11] ;\n input \\dout_o_reg[11]_0 ;\n input [1:0]D;\n input wrcal_done_reg;\n input \\dout_o_reg[9] ;\n input \\dout_o_reg[9]_0 ;\n input \\dout_o_reg[11]_1 ;\n input \\dout_o_reg[11]_2 ;\n input \\dout_o_reg[13] ;\n input \\dout_o_reg[13]_0 ;\n input wrcal_done_reg_0;\n input \\dout_o_reg[9]_1 ;\n input \\dout_o_reg[9]_2 ;\n input \\dout_o_reg[9]_3 ;\n input \\dout_o_reg[9]_4 ;\n input \\dout_o_reg[13]_1 ;\n input \\dout_o_reg[13]_2 ;\n input \\dout_o_reg[1] ;\n input \\dout_o_reg[1]_0 ;\n input \\dout_o_reg[13]_3 ;\n input \\dout_o_reg[13]_4 ;\n input oclkdelay_calib_done_r_reg_1;\n input \\dout_o_reg[11]_3 ;\n input \\dout_o_reg[11]_4 ;\n input \\dout_o_reg[13]_5 ;\n input \\dout_o_reg[13]_6 ;\n input \\dout_o_reg[15] ;\n input \\dout_o_reg[7] ;\n input \\dout_o_reg[15]_0 ;\n input \\dout_o_reg[15]_1 ;\n input \\dout_o_reg[7]_0 ;\n input \\dout_o_reg[15]_2 ;\n input wrcal_done_reg_1;\n input \\dout_o_reg[3] ;\n input \\dout_o_reg[3]_0 ;\n input \\dout_o_reg[7]_1 ;\n input \\dout_o_reg[7]_2 ;\n input \\dout_o_reg[8] ;\n input \\dout_o_reg[8]_0 ;\n input \\dout_o_reg[14] ;\n input \\dout_o_reg[14]_0 ;\n input \\dout_o_reg[6] ;\n input \\dout_o_reg[14]_1 ;\n input \\dout_o_reg[14]_2 ;\n input first_rdlvl_pat_r_reg_0;\n input wrcal_done_reg_2;\n input \\dout_o_reg[2] ;\n input \\dout_o_reg[2]_0 ;\n input \\dout_o_reg[4] ;\n input \\dout_o_reg[4]_0 ;\n input \\dout_o_reg[8]_1 ;\n input \\dout_o_reg[8]_2 ;\n input \\dout_o_reg[10] ;\n input \\dout_o_reg[10]_0 ;\n input \\dout_o_reg[8]_3 ;\n input \\dout_o_reg[8]_4 ;\n input \\dout_o_reg[12] ;\n input \\dout_o_reg[12]_0 ;\n input wrcal_done_reg_3;\n input wrcal_done_reg_4;\n input wrcal_done_reg_5;\n input wrcal_done_reg_6;\n input wrcal_done_reg_7;\n input wrcal_done_reg_8;\n input init_calib_complete_reg_rep__13;\n input rstdiv0_sync_r1_reg_rep__24;\n input reset_if_r9;\n input prbs_rdlvl_done_reg;\n input reset_if;\n input delay_done_r4_reg;\n input dqs_found_done_r_reg_0;\n input wrcal_done_reg_9;\n input oclkdelay_center_calib_start_r_reg;\n input oclk_calib_resume_r_reg;\n input prbs_rdlvl_done_reg_rep_0;\n input complex_oclk_calib_resume;\n input pi_dqs_found_rank_done;\n input wrcal_sanity_chk_done_reg;\n input wrcal_done_reg_10;\n input wrlvl_byte_redo;\n input wrcal_prech_req;\n input \\init_state_r_reg[1]_1 ;\n input prbs_rdlvl_start_r;\n input oclkdelay_calib_done_r_reg_2;\n input [0:0]mc_cas_n;\n input init_calib_complete_reg_rep__6;\n input [33:0]\\rd_ptr_reg[3] ;\n input \\my_empty_reg[1] ;\n input [1:0]mem_out;\n input \\my_empty_reg[1]_0 ;\n input [0:0]mc_ras_n;\n input [0:0]mc_odt;\n input [7:0]\\rd_ptr_reg[3]_0 ;\n input \\my_empty_reg[1]_1 ;\n input [0:0]mc_cke;\n input [0:0]mc_we_n;\n input [33:0]mc_address;\n input [31:0]\\rd_ptr_reg[3]_1 ;\n input \\my_empty_reg[1]_2 ;\n input init_calib_complete_reg_rep__5;\n input [8:0]mc_bank;\n input [255:0]\\write_buffer.wr_buf_out_data_reg[255] ;\n input [63:0]\\rd_ptr_reg[3]_2 ;\n input \\my_empty_reg[1]_3 ;\n input [63:0]\\rd_ptr_reg[3]_3 ;\n input \\my_empty_reg[1]_4 ;\n input init_calib_complete_reg_rep__4;\n input [63:0]\\rd_ptr_reg[3]_4 ;\n input \\my_empty_reg[1]_5 ;\n input [63:0]\\rd_ptr_reg[3]_5 ;\n input \\my_empty_reg[1]_6 ;\n input init_calib_complete_reg_rep__3;\n input init_calib_complete_reg_rep__2;\n input init_calib_complete_reg_rep__1;\n input init_calib_complete_reg_rep__0;\n input init_calib_complete_reg_rep;\n input [1:0]\\rd_byte_data_offset_reg[0][3] ;\n input init_dqsfound_done_r2;\n input [1:0]\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3] ;\n input [1:0]\\rd_byte_data_offset_reg[0][9] ;\n input [1:0]\\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] ;\n input mpr_rdlvl_start_r;\n input phy_rddata_en_1;\n input mpr_rdlvl_done_r_reg;\n input \\cnt_shift_r_reg[0]_0 ;\n input rstdiv0_sync_r1_reg_rep__22;\n input \\mcGo_r_reg[15] ;\n input ck_addr_cmd_delay_done;\n input prbs_rdlvl_done_reg_0;\n input wrlvl_final_mux;\n input mpr_rdlvl_done_r_reg_0;\n input \\init_state_r_reg[2]_2 ;\n input rstdiv0_sync_r1_reg_rep__23;\n input rdlvl_pi_incdec;\n input dqs_found_prech_req;\n input prbs_rdlvl_prech_req_reg;\n input complex_ocal_ref_req;\n input rdlvl_prech_req;\n input complex_pi_incdec_done;\n input wrcal_done_reg_11;\n input rdlvl_stg1_done_int_reg_1;\n input phy_if_empty_r_reg;\n input wrcal_sanity_chk_done_reg_0;\n input rdlvl_stg1_done_int_reg_2;\n input oclkdelay_calib_done_r_reg_3;\n input lim2init_prech_req;\n input ocd_prech_req;\n input oclkdelay_calib_done_r_reg_4;\n input cnt_cmd_done_r_reg_1;\n input oclkdelay_center_calib_start_r_reg_0;\n input oclk_calib_resume_r_reg_0;\n input mpr_rdlvl_done_r_reg_1;\n input dqs_found_done_r_reg_1;\n input wrlvl_byte_redo_reg;\n input mpr_rdlvl_done_r_reg_2;\n input oclkdelay_center_calib_done_r_reg_0;\n input complex_victim_inc_reg;\n input complex_ocal_num_samples_done_r;\n input reset_rd_addr;\n input dqs_found_done_r_reg_2;\n input prbs_last_byte_done_reg;\n input \\rd_victim_sel_reg[1] ;\n input \\rd_victim_sel_reg[0] ;\n input \\rd_victim_sel_reg[2] ;\n input cnt_init_af_done_r_reg_1;\n input num_samples_done_r;\n input complex_init_pi_dec_done;\n input done_r_reg;\n input rdlvl_stg1_rank_done;\n input write_request_r_reg;\n input [2:0]complex_ocal_rd_victim_sel;\n input prbs_rdlvl_done_reg_rep_1;\n input prbs_rdlvl_done_reg_rep_2;\n input wrlvl_final_mux_reg;\n input oclkdelay_calib_done_r_reg_5;\n input wrlvl_byte_redo_reg_0;\n input mem_init_done_r_reg_2;\n input rdlvl_stg1_done_int_reg_3;\n input wrlvl_final_mux_reg_0;\n input prbs_rdlvl_done_reg_rep_3;\n input mpr_last_byte_done;\n input rdlvl_stg1_done_int_reg_4;\n input \\dout_o_reg[0] ;\n input \\dout_o_reg[0]_0 ;\n input [0:0]\\pi_dqs_found_all_bank_reg[1]_0 ;\n input mc_wrdata_en;\n input init_calib_complete_reg_rep__14;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[0] ;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[1] ;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[2] ;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[3] ;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[4] ;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[5] ;\n input [1:0]mc_cmd;\n input \\cmd_pipe_plus.mc_data_offset_reg[0] ;\n input \\cmd_pipe_plus.mc_data_offset_reg[1] ;\n input \\cmd_pipe_plus.mc_data_offset_reg[2] ;\n input \\cmd_pipe_plus.mc_data_offset_reg[3] ;\n input \\cmd_pipe_plus.mc_data_offset_reg[4] ;\n input \\cmd_pipe_plus.mc_data_offset_reg[5] ;\n input init_calib_complete_reg_rep__12;\n input init_calib_complete_reg_rep__11;\n input init_calib_complete_reg_rep__10;\n input init_calib_complete_reg_rep__9;\n input init_calib_complete_reg_rep__8;\n input init_calib_complete_reg_rep__7;\n input \\samples_cnt_r_reg[11]_0 ;\n input wrcal_sanity_chk_r_reg;\n input [0:0]\\rd_addr_reg[3] ;\n input rstdiv0_sync_r1_reg_rep__20;\n input rstdiv0_sync_r1_reg_rep__23_0;\n input done_dqs_tap_inc;\n input p_81_in;\n input rstdiv0_sync_r1_reg_rep__23_1;\n input pi_dqs_found_done_r1_reg_0;\n input pi_dqs_found_done_r1_reg_1;\n input pi_dqs_found_done_r1_reg_2;\n input pi_dqs_found_done_r1_reg_3;\n input pi_dqs_found_done_r1_reg_4;\n input pi_dqs_found_done_r1_reg_5;\n input pi_dqs_found_done_r1_reg_6;\n input pi_dqs_found_done_r1_reg_7;\n input [0:0]rstdiv0_sync_r1_reg_rep__19;\n input [0:0]rstdiv0_sync_r1_reg_rep__18;\n\n wire A_rst_primitives_reg;\n wire CLK;\n wire [1:0]D;\n wire [0:0]D0;\n wire [0:0]D1;\n wire [0:0]D2;\n wire [0:0]D3;\n wire [3:0]D4;\n wire [3:0]D5;\n wire [3:0]D6;\n wire [3:0]D7;\n wire [3:0]D8;\n wire [3:0]D9;\n wire \\DDR3_1rank.phy_int_cs_n[1]_i_1_n_0 ;\n wire \\DDR3_1rank.phy_int_cs_n[1]_i_3_n_0 ;\n wire \\DDR3_1rank.phy_int_cs_n[1]_i_4_n_0 ;\n wire \\DDR3_1rank.phy_int_cs_n[1]_i_5_n_0 ;\n wire \\DDR3_1rank.phy_int_cs_n[1]_i_6_n_0 ;\n wire \\DDR3_1rank.phy_int_cs_n[1]_i_7_n_0 ;\n wire \\DDR3_1rank.phy_int_cs_n[1]_i_8_n_0 ;\n wire [0:0]E;\n wire [5:0]Q;\n wire \\back_to_back_reads_4_1.num_reads[0]_i_1_n_0 ;\n wire \\back_to_back_reads_4_1.num_reads[1]_i_1_n_0 ;\n wire \\back_to_back_reads_4_1.num_reads[1]_i_2_n_0 ;\n wire \\back_to_back_reads_4_1.num_reads[2]_i_1_n_0 ;\n wire \\back_to_back_reads_4_1.num_reads_reg[0]_0 ;\n wire \\back_to_back_reads_4_1.num_reads_reg[1]_0 ;\n wire [1:0]bank_w;\n wire burst_addr_r_reg_0;\n wire burst_addr_r_reg_1;\n wire burst_addr_r_reg_2;\n wire cal1_state_r1535_out;\n wire [3:3]calib_cke;\n wire [2:0]calib_cmd;\n wire \\calib_cmd[0]_i_1_n_0 ;\n wire \\calib_cmd[1]_i_1_n_0 ;\n wire \\calib_cmd[2]_i_1_n_0 ;\n wire \\calib_cmd[2]_i_2_n_0 ;\n wire \\calib_cmd[2]_i_3_n_0 ;\n wire \\calib_cmd[2]_i_4_n_0 ;\n wire \\calib_cmd[2]_i_5_n_0 ;\n wire \\calib_cmd[2]_i_6_n_0 ;\n wire \\calib_cmd[2]_i_7_n_0 ;\n wire \\calib_cmd[2]_i_8_n_0 ;\n wire calib_complete;\n wire calib_ctl_wren;\n wire calib_ctl_wren0;\n wire [5:0]calib_data_offset_0;\n wire \\calib_data_offset_0[2]_i_1_n_0 ;\n wire \\calib_data_offset_0[3]_i_1_n_0 ;\n wire \\calib_data_offset_0[3]_i_2_n_0 ;\n wire \\calib_data_offset_0[5]_i_1_n_0 ;\n wire [5:0]calib_data_offset_1;\n wire \\calib_data_offset_1[2]_i_1_n_0 ;\n wire \\calib_data_offset_1[3]_i_1_n_0 ;\n wire [0:0]calib_odt;\n wire \\calib_odt[0]_i_1_n_0 ;\n wire \\calib_odt[0]_i_2_n_0 ;\n wire \\calib_odt[0]_i_3_n_0 ;\n wire \\calib_odt[0]_i_4_n_0 ;\n wire \\calib_seq[0]_i_1_n_0 ;\n wire \\calib_seq[1]_i_1_n_0 ;\n wire calib_wrdata_en;\n wire ck_addr_cmd_delay_done;\n wire clear;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[0] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[1] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[2] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[3] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[4] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[5] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[0] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[1] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[2] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[3] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[4] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[5] ;\n wire cnt_cmd_done_m7_r;\n wire cnt_cmd_done_m7_r_i_1_n_0;\n wire cnt_cmd_done_m7_r_i_2_n_0;\n wire cnt_cmd_done_r;\n wire cnt_cmd_done_r_i_1_n_0;\n wire cnt_cmd_done_r_reg_0;\n wire cnt_cmd_done_r_reg_1;\n wire \\cnt_cmd_r[0]_i_1_n_0 ;\n wire \\cnt_cmd_r[1]_i_1_n_0 ;\n wire \\cnt_cmd_r[2]_i_1_n_0 ;\n wire \\cnt_cmd_r[3]_i_1_n_0 ;\n wire \\cnt_cmd_r[4]_i_1_n_0 ;\n wire \\cnt_cmd_r[5]_i_1_n_0 ;\n wire \\cnt_cmd_r[6]_i_1_n_0 ;\n wire \\cnt_cmd_r[6]_i_2_n_0 ;\n wire \\cnt_cmd_r[6]_i_3_n_0 ;\n wire \\cnt_cmd_r[6]_i_4_n_0 ;\n wire \\cnt_cmd_r[6]_i_5_n_0 ;\n wire \\cnt_cmd_r_reg_n_0_[0] ;\n wire \\cnt_cmd_r_reg_n_0_[1] ;\n wire \\cnt_cmd_r_reg_n_0_[2] ;\n wire \\cnt_cmd_r_reg_n_0_[3] ;\n wire \\cnt_cmd_r_reg_n_0_[4] ;\n wire \\cnt_cmd_r_reg_n_0_[5] ;\n wire \\cnt_cmd_r_reg_n_0_[6] ;\n wire cnt_dllk_zqinit_done_r;\n wire cnt_dllk_zqinit_done_r_reg_0;\n wire cnt_dllk_zqinit_r;\n wire [5:0]cnt_dllk_zqinit_r_reg__0;\n wire cnt_init_af_done_r;\n wire cnt_init_af_done_r_reg_0;\n wire cnt_init_af_done_r_reg_1;\n wire [1:0]cnt_init_af_r;\n wire \\cnt_init_af_r[0]_i_1_n_0 ;\n wire \\cnt_init_af_r[1]_i_1_n_0 ;\n wire cnt_init_mr_done_r;\n wire cnt_init_mr_done_r_reg_0;\n wire [1:0]cnt_init_mr_r;\n wire cnt_init_mr_r1;\n wire \\cnt_init_mr_r[0]_i_1_n_0 ;\n wire \\cnt_init_mr_r[1]_i_1_n_0 ;\n wire \\cnt_init_mr_r_reg[1]_0 ;\n wire [9:0]cnt_pwron_ce_r_reg__0;\n wire cnt_pwron_cke_done_r;\n wire cnt_pwron_cke_done_r_reg_0;\n wire cnt_pwron_cke_done_r_reg_1;\n wire \\cnt_pwron_r[6]_i_2_n_0 ;\n wire \\cnt_pwron_r[8]_i_2_n_0 ;\n wire [3:0]\\cnt_pwron_r_reg[7]_0 ;\n wire \\cnt_pwron_r_reg[7]_1 ;\n wire [8:2]cnt_pwron_r_reg__0;\n wire cnt_pwron_reset_done_r;\n wire cnt_pwron_reset_done_r_reg_0;\n wire [0:0]\\cnt_shift_r_reg[0] ;\n wire \\cnt_shift_r_reg[0]_0 ;\n wire cnt_txpr_done_r;\n wire cnt_txpr_done_r_reg_0;\n wire cnt_txpr_done_r_reg_1;\n wire \\cnt_txpr_r[7]_i_3_n_0 ;\n wire [2:0]\\cnt_txpr_r_reg[2]_0 ;\n wire [7:3]cnt_txpr_r_reg__0;\n wire complex_act_start;\n wire complex_act_start0;\n wire complex_address0;\n wire \\complex_address[9]_i_2_n_0 ;\n wire \\complex_address[9]_i_3_n_0 ;\n wire \\complex_address[9]_i_4_n_0 ;\n wire \\complex_address_reg_n_0_[0] ;\n wire \\complex_address_reg_n_0_[1] ;\n wire \\complex_address_reg_n_0_[2] ;\n wire \\complex_address_reg_n_0_[3] ;\n wire \\complex_address_reg_n_0_[4] ;\n wire \\complex_address_reg_n_0_[5] ;\n wire \\complex_address_reg_n_0_[6] ;\n wire \\complex_address_reg_n_0_[7] ;\n wire \\complex_address_reg_n_0_[8] ;\n wire \\complex_address_reg_n_0_[9] ;\n wire complex_byte_rd_done;\n wire complex_byte_rd_done_i_1_n_0;\n wire complex_byte_rd_done_i_2_n_0;\n wire complex_init_pi_dec_done;\n wire complex_mask_lim_done;\n wire complex_mask_lim_done_i_1_n_0;\n wire \\complex_num_reads[0]_i_1_n_0 ;\n wire \\complex_num_reads[1]_i_1_n_0 ;\n wire \\complex_num_reads[1]_i_2_n_0 ;\n wire \\complex_num_reads[2]_i_1_n_0 ;\n wire \\complex_num_reads[2]_i_2_n_0 ;\n wire \\complex_num_reads[2]_i_3_n_0 ;\n wire \\complex_num_reads[2]_i_4_n_0 ;\n wire \\complex_num_reads[2]_i_5_n_0 ;\n wire \\complex_num_reads[2]_i_6_n_0 ;\n wire \\complex_num_reads[3]_i_1_n_0 ;\n wire \\complex_num_reads[3]_i_2_n_0 ;\n wire \\complex_num_reads[3]_i_3_n_0 ;\n wire \\complex_num_reads[3]_i_4_n_0 ;\n wire \\complex_num_reads[3]_i_5_n_0 ;\n wire \\complex_num_reads[3]_i_6_n_0 ;\n wire \\complex_num_reads[3]_i_7_n_0 ;\n wire \\complex_num_reads[3]_i_8_n_0 ;\n wire \\complex_num_reads_dec[3]_i_1_n_0 ;\n wire \\complex_num_reads_dec[3]_i_3_n_0 ;\n wire \\complex_num_reads_dec[3]_i_4_n_0 ;\n wire [3:0]complex_num_reads_dec_reg__0;\n wire \\complex_num_reads_reg_n_0_[0] ;\n wire \\complex_num_reads_reg_n_0_[1] ;\n wire \\complex_num_reads_reg_n_0_[2] ;\n wire \\complex_num_reads_reg_n_0_[3] ;\n wire \\complex_num_writes[0]_i_1_n_0 ;\n wire \\complex_num_writes[0]_i_2_n_0 ;\n wire \\complex_num_writes[1]_i_1_n_0 ;\n wire \\complex_num_writes[1]_i_2_n_0 ;\n wire \\complex_num_writes[2]_i_1_n_0 ;\n wire \\complex_num_writes[2]_i_2_n_0 ;\n wire \\complex_num_writes[2]_i_3_n_0 ;\n wire \\complex_num_writes[2]_i_4_n_0 ;\n wire \\complex_num_writes[2]_i_5_n_0 ;\n wire \\complex_num_writes[2]_i_6_n_0 ;\n wire \\complex_num_writes[2]_i_7_n_0 ;\n wire \\complex_num_writes[2]_i_8_n_0 ;\n wire \\complex_num_writes[3]_i_1_n_0 ;\n wire \\complex_num_writes[3]_i_2_n_0 ;\n wire \\complex_num_writes[3]_i_3_n_0 ;\n wire \\complex_num_writes[3]_i_4_n_0 ;\n wire \\complex_num_writes[4]_i_10_n_0 ;\n wire \\complex_num_writes[4]_i_11_n_0 ;\n wire \\complex_num_writes[4]_i_12_n_0 ;\n wire \\complex_num_writes[4]_i_13_n_0 ;\n wire \\complex_num_writes[4]_i_14_n_0 ;\n wire \\complex_num_writes[4]_i_15_n_0 ;\n wire \\complex_num_writes[4]_i_1_n_0 ;\n wire \\complex_num_writes[4]_i_2_n_0 ;\n wire \\complex_num_writes[4]_i_3_n_0 ;\n wire \\complex_num_writes[4]_i_4_n_0 ;\n wire \\complex_num_writes[4]_i_5_n_0 ;\n wire \\complex_num_writes[4]_i_6_n_0 ;\n wire \\complex_num_writes[4]_i_7_n_0 ;\n wire \\complex_num_writes[4]_i_8_n_0 ;\n wire \\complex_num_writes[4]_i_9_n_0 ;\n wire \\complex_num_writes_dec[4]_i_2_n_0 ;\n wire \\complex_num_writes_dec[4]_i_4_n_0 ;\n wire \\complex_num_writes_dec[4]_i_5_n_0 ;\n wire \\complex_num_writes_dec[4]_i_6_n_0 ;\n wire [4:0]complex_num_writes_dec_reg__0;\n wire \\complex_num_writes_reg_n_0_[0] ;\n wire \\complex_num_writes_reg_n_0_[1] ;\n wire \\complex_num_writes_reg_n_0_[2] ;\n wire \\complex_num_writes_reg_n_0_[3] ;\n wire \\complex_num_writes_reg_n_0_[4] ;\n wire complex_ocal_num_samples_done_r;\n wire complex_ocal_odt_ext;\n wire complex_ocal_odt_ext_i_1_n_0;\n wire complex_ocal_odt_ext_i_2_n_0;\n wire complex_ocal_odt_ext_i_3_n_0;\n wire complex_ocal_odt_ext_i_4_n_0;\n wire [2:0]complex_ocal_rd_victim_sel;\n wire complex_ocal_ref_req;\n wire complex_ocal_reset_rd_addr;\n wire complex_ocal_reset_rd_addr0;\n wire complex_ocal_reset_rd_addr_i_2_n_0;\n wire complex_ocal_reset_rd_addr_i_3_n_0;\n wire complex_ocal_wr_start;\n wire complex_ocal_wr_start_i_1_n_0;\n wire complex_oclk_calib_resume;\n wire complex_oclkdelay_calib_done_r1;\n wire complex_oclkdelay_calib_start_int;\n wire complex_oclkdelay_calib_start_int_i_1_n_0;\n wire complex_oclkdelay_calib_start_int_i_2_n_0;\n wire complex_oclkdelay_calib_start_int_reg_0;\n wire complex_oclkdelay_calib_start_r1;\n wire complex_oclkdelay_calib_start_r2;\n wire complex_odt_ext;\n wire complex_odt_ext_i_1_n_0;\n wire complex_pi_incdec_done;\n wire complex_row0_rd_done;\n wire complex_row0_rd_done1;\n wire complex_row0_rd_done_i_1_n_0;\n wire complex_row0_rd_done_i_2_n_0;\n wire complex_row0_wr_done;\n wire complex_row0_wr_done0;\n wire [2:0]complex_row1_rd_cnt;\n wire \\complex_row1_rd_cnt[0]_i_1_n_0 ;\n wire \\complex_row1_rd_cnt[1]_i_1_n_0 ;\n wire \\complex_row1_rd_cnt[2]_i_1_n_0 ;\n wire complex_row1_rd_done;\n wire complex_row1_rd_done_i_1_n_0;\n wire complex_row1_rd_done_i_2_n_0;\n wire complex_row1_rd_done_r1;\n wire complex_row1_wr_done;\n wire complex_row_cnt;\n wire complex_row_cnt_ocal;\n wire complex_row_cnt_ocal0;\n wire \\complex_row_cnt_ocal[7]_i_5_n_0 ;\n wire \\complex_row_cnt_ocal[7]_i_6_n_0 ;\n wire \\complex_row_cnt_ocal[7]_i_7_n_0 ;\n wire \\complex_row_cnt_ocal[7]_i_8_n_0 ;\n wire \\complex_row_cnt_ocal[7]_i_9_n_0 ;\n wire \\complex_row_cnt_ocal_reg[0]_0 ;\n wire [7:0]complex_row_cnt_ocal_reg__0;\n wire complex_sample_cnt_inc;\n wire complex_sample_cnt_inc0;\n wire complex_sample_cnt_inc_i_2_n_0;\n wire complex_sample_cnt_inc_r1;\n wire complex_sample_cnt_inc_r2;\n wire complex_victim_inc_reg;\n wire \\complex_wait_cnt[3]_i_1_n_0 ;\n wire \\complex_wait_cnt[3]_i_3_n_0 ;\n wire [3:0]complex_wait_cnt_reg__0;\n wire complex_wr_done;\n wire [5:0]\\data_offset_1_i1_reg[5] ;\n wire ddr2_pre_flag_r_reg_0;\n wire ddr2_pre_flag_r_reg_1;\n wire ddr2_pre_flag_r_reg_2;\n wire ddr2_refresh_flag_r;\n wire ddr2_refresh_flag_r_reg_0;\n wire ddr3_lm_done_r;\n wire ddr3_lm_done_r_i_1_n_0;\n wire ddr3_lm_done_r_i_2_n_0;\n wire delay_done_r4_reg;\n wire detect_pi_found_dqs;\n wire detect_pi_found_dqs0;\n wire done_dqs_tap_inc;\n wire done_r_reg;\n wire \\dout_o_reg[0] ;\n wire \\dout_o_reg[0]_0 ;\n wire \\dout_o_reg[10] ;\n wire \\dout_o_reg[10]_0 ;\n wire \\dout_o_reg[11] ;\n wire \\dout_o_reg[11]_0 ;\n wire \\dout_o_reg[11]_1 ;\n wire \\dout_o_reg[11]_2 ;\n wire \\dout_o_reg[11]_3 ;\n wire \\dout_o_reg[11]_4 ;\n wire \\dout_o_reg[12] ;\n wire \\dout_o_reg[12]_0 ;\n wire \\dout_o_reg[13] ;\n wire \\dout_o_reg[13]_0 ;\n wire \\dout_o_reg[13]_1 ;\n wire \\dout_o_reg[13]_2 ;\n wire \\dout_o_reg[13]_3 ;\n wire \\dout_o_reg[13]_4 ;\n wire \\dout_o_reg[13]_5 ;\n wire \\dout_o_reg[13]_6 ;\n wire \\dout_o_reg[14] ;\n wire \\dout_o_reg[14]_0 ;\n wire \\dout_o_reg[14]_1 ;\n wire \\dout_o_reg[14]_2 ;\n wire \\dout_o_reg[15] ;\n wire \\dout_o_reg[15]_0 ;\n wire \\dout_o_reg[15]_1 ;\n wire \\dout_o_reg[15]_2 ;\n wire \\dout_o_reg[1] ;\n wire \\dout_o_reg[1]_0 ;\n wire \\dout_o_reg[2] ;\n wire \\dout_o_reg[2]_0 ;\n wire \\dout_o_reg[3] ;\n wire \\dout_o_reg[3]_0 ;\n wire \\dout_o_reg[4] ;\n wire \\dout_o_reg[4]_0 ;\n wire \\dout_o_reg[6] ;\n wire \\dout_o_reg[7] ;\n wire \\dout_o_reg[7]_0 ;\n wire \\dout_o_reg[7]_1 ;\n wire \\dout_o_reg[7]_2 ;\n wire \\dout_o_reg[8] ;\n wire \\dout_o_reg[8]_0 ;\n wire \\dout_o_reg[8]_1 ;\n wire \\dout_o_reg[8]_2 ;\n wire \\dout_o_reg[8]_3 ;\n wire \\dout_o_reg[8]_4 ;\n wire \\dout_o_reg[9] ;\n wire \\dout_o_reg[9]_0 ;\n wire \\dout_o_reg[9]_1 ;\n wire \\dout_o_reg[9]_2 ;\n wire \\dout_o_reg[9]_3 ;\n wire \\dout_o_reg[9]_4 ;\n wire [1:0]dqs_asrt_cnt;\n wire \\dqs_asrt_cnt[0]_i_1_n_0 ;\n wire \\dqs_asrt_cnt[1]_i_1_n_0 ;\n wire dqs_found_done_r_reg;\n wire dqs_found_done_r_reg_0;\n wire dqs_found_done_r_reg_1;\n wire dqs_found_done_r_reg_2;\n wire dqs_found_prech_req;\n wire dqs_found_start_r_reg;\n wire \\en_cnt_div4.enable_wrlvl_cnt[0]_i_1_n_0 ;\n wire \\en_cnt_div4.enable_wrlvl_cnt[1]_i_1_n_0 ;\n wire \\en_cnt_div4.enable_wrlvl_cnt[2]_i_1_n_0 ;\n wire \\en_cnt_div4.enable_wrlvl_cnt[3]_i_2_n_0 ;\n wire \\en_cnt_div4.enable_wrlvl_cnt[4]_i_1_n_0 ;\n wire \\en_cnt_div4.enable_wrlvl_cnt_reg[3]_0 ;\n wire \\en_cnt_div4.wrlvl_odt_i_1_n_0 ;\n wire \\en_cnt_div4.wrlvl_odt_i_2_n_0 ;\n wire [4:0]enable_wrlvl_cnt;\n wire enable_wrlvl_cnt0;\n wire first_rdlvl_pat_r;\n wire first_rdlvl_pat_r_i_1_n_0;\n wire first_rdlvl_pat_r_reg_0;\n wire first_wrcal_pat_r;\n wire first_wrcal_pat_r_i_1_n_0;\n wire first_wrcal_pat_r_i_2_n_0;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_1_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_5_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_6_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_7_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_1_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_1_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_4_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_1_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_7_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_10_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_1_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_9_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_1_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_4_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_5_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_7_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_8_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_9_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_1_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_5_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_6_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_7_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_8_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_11_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_13_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_1_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_9_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_11_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_12_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_1_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_13_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_15_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_16_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_17_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_18_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_1_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_1_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_1_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_4_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_5_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_1_n_0 ;\n wire [1:1]\\gen_rnk[0].mr1_r_reg[0]_196 ;\n wire init_calib_complete_reg_rep;\n wire init_calib_complete_reg_rep__0;\n wire init_calib_complete_reg_rep__1;\n wire init_calib_complete_reg_rep__10;\n wire init_calib_complete_reg_rep__11;\n wire init_calib_complete_reg_rep__12;\n wire init_calib_complete_reg_rep__13;\n wire init_calib_complete_reg_rep__14;\n wire init_calib_complete_reg_rep__2;\n wire init_calib_complete_reg_rep__3;\n wire init_calib_complete_reg_rep__4;\n wire init_calib_complete_reg_rep__5;\n wire init_calib_complete_reg_rep__6;\n wire init_calib_complete_reg_rep__7;\n wire init_calib_complete_reg_rep__8;\n wire init_calib_complete_reg_rep__9;\n wire init_complete_r1;\n wire init_complete_r1_reg_0;\n (* RTL_KEEP = \"true\" *) wire init_complete_r1_timing;\n wire init_complete_r2;\n (* RTL_KEEP = \"true\" *) wire init_complete_r_timing;\n wire init_dqsfound_done_r2;\n wire init_next_state1100_out;\n wire [6:0]init_state_r1;\n wire \\init_state_r[0]_i_10_n_0 ;\n wire \\init_state_r[0]_i_11_n_0 ;\n wire \\init_state_r[0]_i_13_n_0 ;\n wire \\init_state_r[0]_i_14_n_0 ;\n wire \\init_state_r[0]_i_15_n_0 ;\n wire \\init_state_r[0]_i_16_n_0 ;\n wire \\init_state_r[0]_i_17_n_0 ;\n wire \\init_state_r[0]_i_18_n_0 ;\n wire \\init_state_r[0]_i_19_n_0 ;\n wire \\init_state_r[0]_i_1_n_0 ;\n wire \\init_state_r[0]_i_20_n_0 ;\n wire \\init_state_r[0]_i_21_n_0 ;\n wire \\init_state_r[0]_i_22_n_0 ;\n wire \\init_state_r[0]_i_23_n_0 ;\n wire \\init_state_r[0]_i_24_n_0 ;\n wire \\init_state_r[0]_i_25_n_0 ;\n wire \\init_state_r[0]_i_26_n_0 ;\n wire \\init_state_r[0]_i_27_n_0 ;\n wire \\init_state_r[0]_i_28_n_0 ;\n wire \\init_state_r[0]_i_29_n_0 ;\n wire \\init_state_r[0]_i_2_n_0 ;\n wire \\init_state_r[0]_i_30_n_0 ;\n wire \\init_state_r[0]_i_31_n_0 ;\n wire \\init_state_r[0]_i_33_n_0 ;\n wire \\init_state_r[0]_i_34_n_0 ;\n wire \\init_state_r[0]_i_3_n_0 ;\n wire \\init_state_r[0]_i_40_n_0 ;\n wire \\init_state_r[0]_i_41_n_0 ;\n wire \\init_state_r[0]_i_42_n_0 ;\n wire \\init_state_r[0]_i_43_n_0 ;\n wire \\init_state_r[0]_i_45_n_0 ;\n wire \\init_state_r[0]_i_46_n_0 ;\n wire \\init_state_r[0]_i_51_n_0 ;\n wire \\init_state_r[0]_i_5_n_0 ;\n wire \\init_state_r[0]_i_6_n_0 ;\n wire \\init_state_r[0]_i_7_n_0 ;\n wire \\init_state_r[0]_i_8_n_0 ;\n wire \\init_state_r[0]_i_9_n_0 ;\n wire \\init_state_r[1]_i_10_n_0 ;\n wire \\init_state_r[1]_i_11_n_0 ;\n wire \\init_state_r[1]_i_12_n_0 ;\n wire \\init_state_r[1]_i_13_n_0 ;\n wire \\init_state_r[1]_i_15_n_0 ;\n wire \\init_state_r[1]_i_16_n_0 ;\n wire \\init_state_r[1]_i_17_n_0 ;\n wire \\init_state_r[1]_i_18_n_0 ;\n wire \\init_state_r[1]_i_19_n_0 ;\n wire \\init_state_r[1]_i_1_n_0 ;\n wire \\init_state_r[1]_i_20_n_0 ;\n wire \\init_state_r[1]_i_21_n_0 ;\n wire \\init_state_r[1]_i_22_n_0 ;\n wire \\init_state_r[1]_i_23_n_0 ;\n wire \\init_state_r[1]_i_24_n_0 ;\n wire \\init_state_r[1]_i_25_n_0 ;\n wire \\init_state_r[1]_i_26_n_0 ;\n wire \\init_state_r[1]_i_27_n_0 ;\n wire \\init_state_r[1]_i_28_n_0 ;\n wire \\init_state_r[1]_i_2_n_0 ;\n wire \\init_state_r[1]_i_33_n_0 ;\n wire \\init_state_r[1]_i_34_n_0 ;\n wire \\init_state_r[1]_i_35_n_0 ;\n wire \\init_state_r[1]_i_36_n_0 ;\n wire \\init_state_r[1]_i_37_n_0 ;\n wire \\init_state_r[1]_i_39_n_0 ;\n wire \\init_state_r[1]_i_3_n_0 ;\n wire \\init_state_r[1]_i_40_n_0 ;\n wire \\init_state_r[1]_i_41_n_0 ;\n wire \\init_state_r[1]_i_42_n_0 ;\n wire \\init_state_r[1]_i_43_n_0 ;\n wire \\init_state_r[1]_i_46_n_0 ;\n wire \\init_state_r[1]_i_47_n_0 ;\n wire \\init_state_r[1]_i_48_n_0 ;\n wire \\init_state_r[1]_i_5_n_0 ;\n wire \\init_state_r[1]_i_6_n_0 ;\n wire \\init_state_r[1]_i_7_n_0 ;\n wire \\init_state_r[1]_i_8_n_0 ;\n wire \\init_state_r[1]_i_9_n_0 ;\n wire \\init_state_r[2]_i_10_n_0 ;\n wire \\init_state_r[2]_i_11_n_0 ;\n wire \\init_state_r[2]_i_12_n_0 ;\n wire \\init_state_r[2]_i_14_n_0 ;\n wire \\init_state_r[2]_i_16_n_0 ;\n wire \\init_state_r[2]_i_17_n_0 ;\n wire \\init_state_r[2]_i_18_n_0 ;\n wire \\init_state_r[2]_i_1_n_0 ;\n wire \\init_state_r[2]_i_20_n_0 ;\n wire \\init_state_r[2]_i_21_n_0 ;\n wire \\init_state_r[2]_i_22_n_0 ;\n wire \\init_state_r[2]_i_24_n_0 ;\n wire \\init_state_r[2]_i_25_n_0 ;\n wire \\init_state_r[2]_i_26_n_0 ;\n wire \\init_state_r[2]_i_27_n_0 ;\n wire \\init_state_r[2]_i_2_n_0 ;\n wire \\init_state_r[2]_i_32_n_0 ;\n wire \\init_state_r[2]_i_33_n_0 ;\n wire \\init_state_r[2]_i_34_n_0 ;\n wire \\init_state_r[2]_i_35_n_0 ;\n wire \\init_state_r[2]_i_36_n_0 ;\n wire \\init_state_r[2]_i_37_n_0 ;\n wire \\init_state_r[2]_i_3_n_0 ;\n wire \\init_state_r[2]_i_4_n_0 ;\n wire \\init_state_r[2]_i_5_n_0 ;\n wire \\init_state_r[2]_i_6_n_0 ;\n wire \\init_state_r[2]_i_7_n_0 ;\n wire \\init_state_r[2]_i_8_n_0 ;\n wire \\init_state_r[2]_i_9_n_0 ;\n wire \\init_state_r[3]_i_10_n_0 ;\n wire \\init_state_r[3]_i_11_n_0 ;\n wire \\init_state_r[3]_i_13_n_0 ;\n wire \\init_state_r[3]_i_14_n_0 ;\n wire \\init_state_r[3]_i_15_n_0 ;\n wire \\init_state_r[3]_i_16_n_0 ;\n wire \\init_state_r[3]_i_17_n_0 ;\n wire \\init_state_r[3]_i_18_n_0 ;\n wire \\init_state_r[3]_i_19_n_0 ;\n wire \\init_state_r[3]_i_1_n_0 ;\n wire \\init_state_r[3]_i_20_n_0 ;\n wire \\init_state_r[3]_i_21_n_0 ;\n wire \\init_state_r[3]_i_22_n_0 ;\n wire \\init_state_r[3]_i_23_n_0 ;\n wire \\init_state_r[3]_i_24_n_0 ;\n wire \\init_state_r[3]_i_25_n_0 ;\n wire \\init_state_r[3]_i_2_n_0 ;\n wire \\init_state_r[3]_i_3_n_0 ;\n wire \\init_state_r[3]_i_4_n_0 ;\n wire \\init_state_r[3]_i_5_n_0 ;\n wire \\init_state_r[3]_i_6_n_0 ;\n wire \\init_state_r[3]_i_7_n_0 ;\n wire \\init_state_r[4]_i_10_n_0 ;\n wire \\init_state_r[4]_i_11_n_0 ;\n wire \\init_state_r[4]_i_12_n_0 ;\n wire \\init_state_r[4]_i_13_n_0 ;\n wire \\init_state_r[4]_i_15_n_0 ;\n wire \\init_state_r[4]_i_16_n_0 ;\n wire \\init_state_r[4]_i_17_n_0 ;\n wire \\init_state_r[4]_i_18_n_0 ;\n wire \\init_state_r[4]_i_19_n_0 ;\n wire \\init_state_r[4]_i_1_n_0 ;\n wire \\init_state_r[4]_i_20_n_0 ;\n wire \\init_state_r[4]_i_21_n_0 ;\n wire \\init_state_r[4]_i_22_n_0 ;\n wire \\init_state_r[4]_i_26_n_0 ;\n wire \\init_state_r[4]_i_27_n_0 ;\n wire \\init_state_r[4]_i_28_n_0 ;\n wire \\init_state_r[4]_i_29_n_0 ;\n wire \\init_state_r[4]_i_2_n_0 ;\n wire \\init_state_r[4]_i_30_n_0 ;\n wire \\init_state_r[4]_i_31_n_0 ;\n wire \\init_state_r[4]_i_32_n_0 ;\n wire \\init_state_r[4]_i_33_n_0 ;\n wire \\init_state_r[4]_i_37_n_0 ;\n wire \\init_state_r[4]_i_38_n_0 ;\n wire \\init_state_r[4]_i_39_n_0 ;\n wire \\init_state_r[4]_i_3_n_0 ;\n wire \\init_state_r[4]_i_40_n_0 ;\n wire \\init_state_r[4]_i_4_n_0 ;\n wire \\init_state_r[4]_i_5_n_0 ;\n wire \\init_state_r[4]_i_6_n_0 ;\n wire \\init_state_r[4]_i_7_n_0 ;\n wire \\init_state_r[4]_i_8_n_0 ;\n wire \\init_state_r[4]_i_9_n_0 ;\n wire \\init_state_r[5]_i_10_n_0 ;\n wire \\init_state_r[5]_i_11_n_0 ;\n wire \\init_state_r[5]_i_12_n_0 ;\n wire \\init_state_r[5]_i_13_n_0 ;\n wire \\init_state_r[5]_i_14_n_0 ;\n wire \\init_state_r[5]_i_15_n_0 ;\n wire \\init_state_r[5]_i_16_n_0 ;\n wire \\init_state_r[5]_i_17_n_0 ;\n wire \\init_state_r[5]_i_18_n_0 ;\n wire \\init_state_r[5]_i_19_n_0 ;\n wire \\init_state_r[5]_i_1_n_0 ;\n wire \\init_state_r[5]_i_20_n_0 ;\n wire \\init_state_r[5]_i_21_n_0 ;\n wire \\init_state_r[5]_i_22_n_0 ;\n wire \\init_state_r[5]_i_23_n_0 ;\n wire \\init_state_r[5]_i_24_n_0 ;\n wire \\init_state_r[5]_i_25_n_0 ;\n wire \\init_state_r[5]_i_26_n_0 ;\n wire \\init_state_r[5]_i_27_n_0 ;\n wire \\init_state_r[5]_i_29_n_0 ;\n wire \\init_state_r[5]_i_2_n_0 ;\n wire \\init_state_r[5]_i_31_n_0 ;\n wire \\init_state_r[5]_i_32_n_0 ;\n wire \\init_state_r[5]_i_33_n_0 ;\n wire \\init_state_r[5]_i_34_n_0 ;\n wire \\init_state_r[5]_i_35_n_0 ;\n wire \\init_state_r[5]_i_36_n_0 ;\n wire \\init_state_r[5]_i_38_n_0 ;\n wire \\init_state_r[5]_i_39_n_0 ;\n wire \\init_state_r[5]_i_3_n_0 ;\n wire \\init_state_r[5]_i_40_n_0 ;\n wire \\init_state_r[5]_i_41_n_0 ;\n wire \\init_state_r[5]_i_42_n_0 ;\n wire \\init_state_r[5]_i_43_n_0 ;\n wire \\init_state_r[5]_i_44_n_0 ;\n wire \\init_state_r[5]_i_45_n_0 ;\n wire \\init_state_r[5]_i_48_n_0 ;\n wire \\init_state_r[5]_i_49_n_0 ;\n wire \\init_state_r[5]_i_4_n_0 ;\n wire \\init_state_r[5]_i_50_n_0 ;\n wire \\init_state_r[5]_i_51_n_0 ;\n wire \\init_state_r[5]_i_52_n_0 ;\n wire \\init_state_r[5]_i_53_n_0 ;\n wire \\init_state_r[5]_i_54_n_0 ;\n wire \\init_state_r[5]_i_56_n_0 ;\n wire \\init_state_r[5]_i_57_n_0 ;\n wire \\init_state_r[5]_i_58_n_0 ;\n wire \\init_state_r[5]_i_5_n_0 ;\n wire \\init_state_r[5]_i_60_n_0 ;\n wire \\init_state_r[5]_i_61_n_0 ;\n wire \\init_state_r[5]_i_62_n_0 ;\n wire \\init_state_r[5]_i_6_n_0 ;\n wire \\init_state_r[5]_i_7_n_0 ;\n wire \\init_state_r[5]_i_8_n_0 ;\n wire \\init_state_r[5]_i_9_n_0 ;\n wire \\init_state_r[6]_i_10_n_0 ;\n wire \\init_state_r[6]_i_11_n_0 ;\n wire \\init_state_r[6]_i_12_n_0 ;\n wire \\init_state_r[6]_i_13_n_0 ;\n wire \\init_state_r[6]_i_14_n_0 ;\n wire \\init_state_r[6]_i_15_n_0 ;\n wire \\init_state_r[6]_i_16_n_0 ;\n wire \\init_state_r[6]_i_17_n_0 ;\n wire \\init_state_r[6]_i_18_n_0 ;\n wire \\init_state_r[6]_i_19_n_0 ;\n wire \\init_state_r[6]_i_20_n_0 ;\n wire \\init_state_r[6]_i_21_n_0 ;\n wire \\init_state_r[6]_i_22_n_0 ;\n wire \\init_state_r[6]_i_23_n_0 ;\n wire \\init_state_r[6]_i_2_n_0 ;\n wire \\init_state_r[6]_i_3_n_0 ;\n wire \\init_state_r[6]_i_4_n_0 ;\n wire \\init_state_r[6]_i_5_n_0 ;\n wire \\init_state_r[6]_i_6_n_0 ;\n wire \\init_state_r[6]_i_8_n_0 ;\n wire \\init_state_r[6]_i_9_n_0 ;\n wire \\init_state_r_reg[0]_0 ;\n wire \\init_state_r_reg[0]_1 ;\n wire \\init_state_r_reg[1]_0 ;\n wire \\init_state_r_reg[1]_1 ;\n wire \\init_state_r_reg[2]_0 ;\n wire \\init_state_r_reg[2]_1 ;\n wire \\init_state_r_reg[2]_2 ;\n wire \\init_state_r_reg[4]_0 ;\n wire \\init_state_r_reg[5]_0 ;\n wire \\init_state_r_reg[6]_0 ;\n wire \\init_state_r_reg[6]_1 ;\n wire \\init_state_r_reg_n_0_[3] ;\n wire lim2init_prech_req;\n wire lim_start_r_reg;\n wire mask_lim_done;\n wire mask_lim_done_i_1_n_0;\n wire \\mcGo_r_reg[15] ;\n wire [33:0]mc_address;\n wire [8:0]mc_bank;\n wire [0:0]mc_cas_n;\n wire [0:0]mc_cke;\n wire [1:0]mc_cmd;\n wire [0:0]mc_odt;\n wire [0:0]mc_ras_n;\n wire [0:0]mc_we_n;\n wire mc_wrdata_en;\n wire mem_init_done_r;\n wire mem_init_done_r_i_1_n_0;\n wire [1:0]mem_init_done_r_reg_0;\n wire mem_init_done_r_reg_1;\n wire mem_init_done_r_reg_2;\n wire [1:0]mem_out;\n wire mpr_end_if_reset;\n wire mpr_end_if_reset0;\n wire mpr_last_byte_done;\n wire mpr_rdlvl_done_r_reg;\n wire mpr_rdlvl_done_r_reg_0;\n wire mpr_rdlvl_done_r_reg_1;\n wire mpr_rdlvl_done_r_reg_2;\n wire mpr_rdlvl_start_i_1_n_0;\n wire mpr_rdlvl_start_i_2_n_0;\n wire mpr_rdlvl_start_r;\n wire mpr_rdlvl_start_r_reg;\n wire mux_cmd_wren;\n wire mux_reset_n;\n wire mux_wrdata_en;\n wire \\my_empty_reg[1] ;\n wire \\my_empty_reg[1]_0 ;\n wire \\my_empty_reg[1]_1 ;\n wire \\my_empty_reg[1]_2 ;\n wire \\my_empty_reg[1]_3 ;\n wire \\my_empty_reg[1]_4 ;\n wire \\my_empty_reg[1]_5 ;\n wire \\my_empty_reg[1]_6 ;\n wire [3:0]\\my_empty_reg[7] ;\n wire [3:0]\\my_empty_reg[7]_0 ;\n wire [3:0]\\my_empty_reg[7]_1 ;\n wire [7:0]\\my_empty_reg[7]_10 ;\n wire [7:0]\\my_empty_reg[7]_11 ;\n wire [7:0]\\my_empty_reg[7]_12 ;\n wire [7:0]\\my_empty_reg[7]_13 ;\n wire [7:0]\\my_empty_reg[7]_14 ;\n wire [7:0]\\my_empty_reg[7]_15 ;\n wire [7:0]\\my_empty_reg[7]_16 ;\n wire [7:0]\\my_empty_reg[7]_17 ;\n wire [7:0]\\my_empty_reg[7]_18 ;\n wire [7:0]\\my_empty_reg[7]_19 ;\n wire [3:0]\\my_empty_reg[7]_2 ;\n wire [7:0]\\my_empty_reg[7]_20 ;\n wire [7:0]\\my_empty_reg[7]_21 ;\n wire [7:0]\\my_empty_reg[7]_22 ;\n wire [7:0]\\my_empty_reg[7]_23 ;\n wire [7:0]\\my_empty_reg[7]_24 ;\n wire [7:0]\\my_empty_reg[7]_25 ;\n wire [7:0]\\my_empty_reg[7]_26 ;\n wire [7:0]\\my_empty_reg[7]_27 ;\n wire [7:0]\\my_empty_reg[7]_28 ;\n wire [7:0]\\my_empty_reg[7]_29 ;\n wire [3:0]\\my_empty_reg[7]_3 ;\n wire [7:0]\\my_empty_reg[7]_30 ;\n wire [7:0]\\my_empty_reg[7]_31 ;\n wire [7:0]\\my_empty_reg[7]_32 ;\n wire [7:0]\\my_empty_reg[7]_33 ;\n wire [7:0]\\my_empty_reg[7]_34 ;\n wire [7:0]\\my_empty_reg[7]_35 ;\n wire [7:0]\\my_empty_reg[7]_36 ;\n wire [7:0]\\my_empty_reg[7]_37 ;\n wire [63:0]\\my_empty_reg[7]_38 ;\n wire [63:0]\\my_empty_reg[7]_39 ;\n wire [3:0]\\my_empty_reg[7]_4 ;\n wire [63:0]\\my_empty_reg[7]_40 ;\n wire [63:0]\\my_empty_reg[7]_41 ;\n wire [3:0]\\my_empty_reg[7]_5 ;\n wire [7:0]\\my_empty_reg[7]_6 ;\n wire [7:0]\\my_empty_reg[7]_7 ;\n wire [7:0]\\my_empty_reg[7]_8 ;\n wire [7:0]\\my_empty_reg[7]_9 ;\n wire [1:0]\\my_full_reg[3] ;\n wire new_cnt_dqs_r_reg;\n wire [2:0]num_reads;\n wire num_reads0;\n wire num_refresh0;\n wire \\num_refresh[3]_i_1_n_0 ;\n wire \\num_refresh[3]_i_4_n_0 ;\n wire \\num_refresh[3]_i_5_n_0 ;\n wire \\num_refresh[3]_i_6_n_0 ;\n wire [3:0]num_refresh_reg__0;\n wire num_samples_done_r;\n wire \\ocal_act_wait_cnt[3]_i_1_n_0 ;\n wire \\ocal_act_wait_cnt[3]_i_3_n_0 ;\n wire [3:0]ocal_act_wait_cnt_reg__0;\n wire ocal_last_byte_done;\n wire ocd_prech_req;\n wire oclk_calib_resume_level;\n wire oclk_calib_resume_level_i_1_n_0;\n wire oclk_calib_resume_level_reg_0;\n wire oclk_calib_resume_r_reg;\n wire oclk_calib_resume_r_reg_0;\n wire [3:2]oclk_wr_cnt0;\n wire \\oclk_wr_cnt[0]_i_1_n_0 ;\n wire \\oclk_wr_cnt[1]_i_1_n_0 ;\n wire \\oclk_wr_cnt[3]_i_1_n_0 ;\n wire \\oclk_wr_cnt[3]_i_4_n_0 ;\n wire [3:0]oclk_wr_cnt_reg__0;\n wire oclkdelay_calib_done_r_reg;\n wire oclkdelay_calib_done_r_reg_0;\n wire oclkdelay_calib_done_r_reg_1;\n wire oclkdelay_calib_done_r_reg_2;\n wire oclkdelay_calib_done_r_reg_3;\n wire oclkdelay_calib_done_r_reg_4;\n wire oclkdelay_calib_done_r_reg_5;\n wire oclkdelay_calib_start_int_i_1_n_0;\n wire oclkdelay_calib_start_pre;\n wire oclkdelay_center_calib_done_r_reg;\n wire oclkdelay_center_calib_done_r_reg_0;\n wire oclkdelay_center_calib_start_r_reg;\n wire oclkdelay_center_calib_start_r_reg_0;\n wire oclkdelay_int_ref_req0;\n wire oclkdelay_int_ref_req_i_1_n_0;\n wire oclkdelay_int_ref_req_i_2_n_0;\n wire oclkdelay_int_ref_req_i_3_n_0;\n wire oclkdelay_int_ref_req_i_5_n_0;\n wire oclkdelay_int_ref_req_reg_0;\n wire \\oclkdelay_ref_cnt[0]_i_1_n_0 ;\n wire \\oclkdelay_ref_cnt[0]_i_4_n_0 ;\n wire \\oclkdelay_ref_cnt[0]_i_5_n_0 ;\n wire \\oclkdelay_ref_cnt[0]_i_6_n_0 ;\n wire \\oclkdelay_ref_cnt[0]_i_7_n_0 ;\n wire \\oclkdelay_ref_cnt[12]_i_2_n_0 ;\n wire \\oclkdelay_ref_cnt[12]_i_3_n_0 ;\n wire \\oclkdelay_ref_cnt[4]_i_2_n_0 ;\n wire \\oclkdelay_ref_cnt[4]_i_3_n_0 ;\n wire \\oclkdelay_ref_cnt[4]_i_4_n_0 ;\n wire \\oclkdelay_ref_cnt[4]_i_5_n_0 ;\n wire \\oclkdelay_ref_cnt[8]_i_2_n_0 ;\n wire \\oclkdelay_ref_cnt[8]_i_3_n_0 ;\n wire \\oclkdelay_ref_cnt[8]_i_4_n_0 ;\n wire \\oclkdelay_ref_cnt[8]_i_5_n_0 ;\n wire [13:0]oclkdelay_ref_cnt_reg;\n wire \\oclkdelay_ref_cnt_reg[0]_i_2_n_0 ;\n wire \\oclkdelay_ref_cnt_reg[0]_i_2_n_1 ;\n wire \\oclkdelay_ref_cnt_reg[0]_i_2_n_2 ;\n wire \\oclkdelay_ref_cnt_reg[0]_i_2_n_3 ;\n wire \\oclkdelay_ref_cnt_reg[0]_i_2_n_4 ;\n wire \\oclkdelay_ref_cnt_reg[0]_i_2_n_5 ;\n wire \\oclkdelay_ref_cnt_reg[0]_i_2_n_6 ;\n wire \\oclkdelay_ref_cnt_reg[0]_i_2_n_7 ;\n wire \\oclkdelay_ref_cnt_reg[12]_i_1_n_3 ;\n wire \\oclkdelay_ref_cnt_reg[12]_i_1_n_6 ;\n wire \\oclkdelay_ref_cnt_reg[12]_i_1_n_7 ;\n wire \\oclkdelay_ref_cnt_reg[13]_0 ;\n wire \\oclkdelay_ref_cnt_reg[4]_i_1_n_0 ;\n wire \\oclkdelay_ref_cnt_reg[4]_i_1_n_1 ;\n wire \\oclkdelay_ref_cnt_reg[4]_i_1_n_2 ;\n wire \\oclkdelay_ref_cnt_reg[4]_i_1_n_3 ;\n wire \\oclkdelay_ref_cnt_reg[4]_i_1_n_4 ;\n wire \\oclkdelay_ref_cnt_reg[4]_i_1_n_5 ;\n wire \\oclkdelay_ref_cnt_reg[4]_i_1_n_6 ;\n wire \\oclkdelay_ref_cnt_reg[4]_i_1_n_7 ;\n wire \\oclkdelay_ref_cnt_reg[8]_i_1_n_0 ;\n wire \\oclkdelay_ref_cnt_reg[8]_i_1_n_1 ;\n wire \\oclkdelay_ref_cnt_reg[8]_i_1_n_2 ;\n wire \\oclkdelay_ref_cnt_reg[8]_i_1_n_3 ;\n wire \\oclkdelay_ref_cnt_reg[8]_i_1_n_4 ;\n wire \\oclkdelay_ref_cnt_reg[8]_i_1_n_5 ;\n wire \\oclkdelay_ref_cnt_reg[8]_i_1_n_6 ;\n wire \\oclkdelay_ref_cnt_reg[8]_i_1_n_7 ;\n wire [5:5]oclkdelay_start_dly_r;\n wire \\oclkdelay_start_dly_r_reg[4]_srl5_n_0 ;\n wire \\odd_cwl.phy_cas_n[1]_i_1_n_0 ;\n wire \\odd_cwl.phy_cas_n_reg[1]_0 ;\n wire \\odd_cwl.phy_ras_n[1]_i_1_n_0 ;\n wire \\odd_cwl.phy_ras_n[1]_i_2_n_0 ;\n wire \\odd_cwl.phy_we_n[1]_i_1_n_0 ;\n wire \\one_rank.stg1_wr_done_i_1_n_0 ;\n wire \\one_rank.stg1_wr_done_reg_0 ;\n wire \\one_rank_complex.complex_wr_done_i_1_n_0 ;\n wire \\one_rank_complex.complex_wr_done_i_2_n_0 ;\n wire \\one_rank_complex.complex_wr_done_i_3_n_0 ;\n wire \\one_rank_complex.complex_wr_done_i_4_n_0 ;\n wire \\one_rank_complex.complex_wr_done_i_5_n_0 ;\n wire p_0_in0_in;\n wire [9:0]p_0_in__0;\n wire [8:0]p_0_in__0__0;\n wire [7:0]p_0_in__1;\n wire [3:1]p_0_in__2;\n wire [7:0]p_0_in__3;\n wire [3:0]p_0_in__4;\n wire [7:0]p_0_in__5;\n wire [3:0]p_0_in__6;\n wire [4:0]p_0_in__7;\n wire [3:0]p_0_in__8;\n wire [3:0]p_0_in__9;\n wire p_81_in;\n wire [11:9]phy_bank;\n wire [1:1]phy_cas_n;\n wire [1:1]phy_cs_n;\n wire [10:0]\\phy_ctl_wd_i1_reg[24] ;\n wire [31:0]phy_dout;\n wire phy_if_empty_r_reg;\n wire [1:1]phy_ras_n;\n wire phy_rddata_en_1;\n wire phy_read_calib;\n wire phy_reset_n;\n wire [1:1]phy_we_n;\n wire [255:24]phy_wrdata;\n wire phy_wrdata_en;\n wire phy_write_calib;\n wire pi_calib_done;\n wire pi_calib_done_r;\n wire pi_calib_done_r_i_1_n_0;\n wire pi_calib_rank_done_r;\n wire \\pi_dqs_found_all_bank_reg[1] ;\n wire [0:0]\\pi_dqs_found_all_bank_reg[1]_0 ;\n wire pi_dqs_found_done_r1;\n wire pi_dqs_found_done_r1_reg_0;\n wire pi_dqs_found_done_r1_reg_1;\n wire pi_dqs_found_done_r1_reg_2;\n wire pi_dqs_found_done_r1_reg_3;\n wire pi_dqs_found_done_r1_reg_4;\n wire pi_dqs_found_done_r1_reg_5;\n wire pi_dqs_found_done_r1_reg_6;\n wire pi_dqs_found_done_r1_reg_7;\n wire pi_dqs_found_rank_done;\n wire pi_dqs_found_start_i_1_n_0;\n (* async_reg = \"true\" *) wire pi_phase_locked_all_r1;\n (* async_reg = \"true\" *) wire pi_phase_locked_all_r2;\n (* async_reg = \"true\" *) wire pi_phase_locked_all_r3;\n (* async_reg = \"true\" *) wire pi_phase_locked_all_r4;\n wire prbs_gen_clk_en;\n wire prbs_gen_clk_en040_out;\n wire prbs_gen_clk_en_i_1_n_0;\n wire prbs_gen_clk_en_i_2_n_0;\n wire prbs_gen_clk_en_i_3_n_0;\n wire prbs_gen_clk_en_i_5_n_0;\n wire prbs_gen_oclk_clk_en;\n wire prbs_gen_oclk_clk_en_i_1_n_0;\n wire prbs_gen_oclk_clk_en_i_2_n_0;\n wire prbs_gen_oclk_clk_en_i_3_n_0;\n wire prbs_gen_oclk_clk_en_i_4_n_0;\n wire prbs_gen_oclk_clk_en_i_5_n_0;\n wire prbs_gen_oclk_clk_en_i_6_n_0;\n wire prbs_gen_oclk_clk_en_i_7_n_0;\n wire prbs_gen_oclk_clk_en_i_8_n_0;\n wire prbs_gen_oclk_clk_en_i_9_n_0;\n wire prbs_last_byte_done;\n wire prbs_last_byte_done_r;\n wire prbs_last_byte_done_reg;\n wire prbs_rdlvl_done_pulse;\n wire prbs_rdlvl_done_pulse0;\n wire prbs_rdlvl_done_r1;\n wire prbs_rdlvl_done_r2;\n wire prbs_rdlvl_done_r3;\n wire prbs_rdlvl_done_reg;\n wire prbs_rdlvl_done_reg_0;\n wire prbs_rdlvl_done_reg_rep;\n wire prbs_rdlvl_done_reg_rep_0;\n wire prbs_rdlvl_done_reg_rep_1;\n wire prbs_rdlvl_done_reg_rep_2;\n wire prbs_rdlvl_done_reg_rep_3;\n wire prbs_rdlvl_prech_req_reg;\n wire prbs_rdlvl_start_i_1_n_0;\n wire prbs_rdlvl_start_i_2_n_0;\n wire prbs_rdlvl_start_i_3_n_0;\n wire prbs_rdlvl_start_r;\n wire prbs_rdlvl_start_r_reg;\n wire prech_done;\n wire \\prech_done_dly_r_reg[15]_srl16_n_0 ;\n wire prech_done_pre;\n wire prech_done_r2;\n wire prech_done_r3;\n wire prech_pending_r;\n wire prech_pending_r_i_3_n_0;\n wire prech_pending_r_i_4_n_0;\n wire prech_pending_r_i_5_n_0;\n wire prech_pending_r_i_6_n_0;\n wire prech_pending_r_i_7_n_0;\n wire prech_pending_r_i_8_n_0;\n wire prech_pending_r_i_9_n_0;\n wire prech_pending_r_reg_0;\n wire prech_pending_r_reg_1;\n wire prech_req;\n wire prech_req_posedge_r0;\n wire prech_req_posedge_r_i_2_n_0;\n wire prech_req_posedge_r_reg_0;\n wire prech_req_r;\n wire pwron_ce_r;\n wire pwron_ce_r_i_2_n_0;\n wire pwron_ce_r_i_3_n_0;\n wire [1:0]\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3] ;\n wire [1:0]\\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] ;\n wire [0:0]\\rd_addr_reg[0] ;\n wire [0:0]\\rd_addr_reg[3] ;\n wire \\rd_addr_reg_rep[7] ;\n wire [1:0]\\rd_byte_data_offset_reg[0][3] ;\n wire [1:0]\\rd_byte_data_offset_reg[0][9] ;\n wire [33:0]\\rd_ptr_reg[3] ;\n wire [7:0]\\rd_ptr_reg[3]_0 ;\n wire [31:0]\\rd_ptr_reg[3]_1 ;\n wire [63:0]\\rd_ptr_reg[3]_2 ;\n wire [63:0]\\rd_ptr_reg[3]_3 ;\n wire [63:0]\\rd_ptr_reg[3]_4 ;\n wire [63:0]\\rd_ptr_reg[3]_5 ;\n wire [33:0]\\rd_ptr_timing_reg[0] ;\n wire [7:0]\\rd_ptr_timing_reg[0]_0 ;\n wire [7:0]\\rd_ptr_timing_reg[0]_1 ;\n wire [3:0]\\rd_ptr_timing_reg[0]_2 ;\n wire [1:0]\\rd_ptr_timing_reg[0]_3 ;\n wire \\rd_victim_sel_reg[0] ;\n wire \\rd_victim_sel_reg[1] ;\n wire \\rd_victim_sel_reg[2] ;\n wire rdlvl_last_byte_done;\n wire rdlvl_last_byte_done_r;\n wire rdlvl_pi_incdec;\n wire rdlvl_prech_req;\n wire [0:0]rdlvl_start_dly0_r;\n wire \\rdlvl_start_dly0_r_reg[13]_srl14_n_0 ;\n wire \\rdlvl_start_dly0_r_reg[14]_0 ;\n wire rdlvl_start_pre;\n wire rdlvl_start_pre_reg_0;\n wire rdlvl_stg1_done_int_reg;\n wire rdlvl_stg1_done_int_reg_0;\n wire rdlvl_stg1_done_int_reg_1;\n wire rdlvl_stg1_done_int_reg_2;\n wire rdlvl_stg1_done_int_reg_3;\n wire rdlvl_stg1_done_int_reg_4;\n wire rdlvl_stg1_done_r1;\n wire rdlvl_stg1_rank_done;\n wire rdlvl_stg1_start_int;\n wire rdlvl_stg1_start_int_i_1_n_0;\n wire rdlvl_stg1_start_int_i_2_n_0;\n wire rdlvl_stg1_start_r_reg;\n wire read_calib_i_1_n_0;\n wire read_calib_i_2_n_0;\n wire read_calib_reg_0;\n wire reg_ctrl_cnt_r;\n wire \\reg_ctrl_cnt_r[0]_i_1_n_0 ;\n wire \\reg_ctrl_cnt_r_reg[3]_0 ;\n wire [3:0]reg_ctrl_cnt_r_reg__0;\n wire reset_if;\n wire reset_if_i_2_n_0;\n wire reset_if_r9;\n wire reset_if_reg;\n wire reset_rd_addr;\n wire reset_rd_addr0;\n wire reset_rd_addr_r1;\n wire \\row_cnt_victim_rotate.complex_row_cnt[0]_i_1_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt[1]_i_1_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt[2]_i_1_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt[3]_i_1_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt[4]_i_10_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt[4]_i_3_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt[4]_i_7_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt[5]_i_1_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt[6]_i_1_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt_reg[4]_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ;\n wire \\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ;\n wire \\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ;\n wire \\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ;\n wire \\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ;\n wire \\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ;\n wire \\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ;\n wire \\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ;\n wire rstdiv0_sync_r1_reg_rep__10;\n wire rstdiv0_sync_r1_reg_rep__11;\n wire [0:0]rstdiv0_sync_r1_reg_rep__12;\n wire [0:0]rstdiv0_sync_r1_reg_rep__18;\n wire [0:0]rstdiv0_sync_r1_reg_rep__19;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__22;\n wire rstdiv0_sync_r1_reg_rep__23;\n wire rstdiv0_sync_r1_reg_rep__23_0;\n wire rstdiv0_sync_r1_reg_rep__23_1;\n wire rstdiv0_sync_r1_reg_rep__24;\n wire [0:0]\\samples_cnt_r_reg[11] ;\n wire \\samples_cnt_r_reg[11]_0 ;\n wire stg1_wr_done;\n wire \\stg1_wr_rd_cnt[0]_i_1_n_0 ;\n wire \\stg1_wr_rd_cnt[1]_i_1_n_0 ;\n wire \\stg1_wr_rd_cnt[2]_i_1_n_0 ;\n wire \\stg1_wr_rd_cnt[3]_i_1_n_0 ;\n wire \\stg1_wr_rd_cnt[3]_i_2_n_0 ;\n wire \\stg1_wr_rd_cnt[4]_i_1_n_0 ;\n wire \\stg1_wr_rd_cnt[4]_i_3_n_0 ;\n wire \\stg1_wr_rd_cnt[4]_i_4_n_0 ;\n wire \\stg1_wr_rd_cnt[4]_i_5_n_0 ;\n wire \\stg1_wr_rd_cnt[4]_i_6_n_0 ;\n wire \\stg1_wr_rd_cnt[5]_i_1_n_0 ;\n wire \\stg1_wr_rd_cnt[5]_i_2_n_0 ;\n wire \\stg1_wr_rd_cnt[6]_i_1_n_0 ;\n wire \\stg1_wr_rd_cnt[6]_i_2_n_0 ;\n wire \\stg1_wr_rd_cnt[7]_i_1_n_0 ;\n wire \\stg1_wr_rd_cnt[8]_i_1_n_0 ;\n wire \\stg1_wr_rd_cnt[8]_i_2_n_0 ;\n wire \\stg1_wr_rd_cnt[8]_i_3_n_0 ;\n wire \\stg1_wr_rd_cnt[8]_i_4_n_0 ;\n wire \\stg1_wr_rd_cnt[8]_i_5_n_0 ;\n wire \\stg1_wr_rd_cnt[8]_i_6_n_0 ;\n wire \\stg1_wr_rd_cnt_reg_n_0_[0] ;\n wire \\stg1_wr_rd_cnt_reg_n_0_[1] ;\n wire \\stg1_wr_rd_cnt_reg_n_0_[2] ;\n wire \\stg1_wr_rd_cnt_reg_n_0_[3] ;\n wire \\stg1_wr_rd_cnt_reg_n_0_[4] ;\n wire \\stg1_wr_rd_cnt_reg_n_0_[5] ;\n wire \\stg1_wr_rd_cnt_reg_n_0_[6] ;\n wire \\stg1_wr_rd_cnt_reg_n_0_[7] ;\n wire \\stg1_wr_rd_cnt_reg_n_0_[8] ;\n wire temp_lmr_done;\n wire \\victim_sel[0]_i_1_n_0 ;\n wire \\victim_sel[0]_i_2_n_0 ;\n wire \\victim_sel[1]_i_1_n_0 ;\n wire \\victim_sel[1]_i_2_n_0 ;\n wire \\victim_sel[2]_i_1_n_0 ;\n wire \\victim_sel[2]_i_2_n_0 ;\n wire \\victim_sel[2]_i_3_n_0 ;\n wire \\victim_sel[2]_i_4_n_0 ;\n wire \\victim_sel[2]_i_5_n_0 ;\n wire \\victim_sel_reg_n_0_[0] ;\n wire \\victim_sel_reg_n_0_[1] ;\n wire \\victim_sel_reg_n_0_[2] ;\n wire [7:0]\\victim_sel_rotate.sel_reg[31] ;\n wire wl_sm_start;\n wire \\wr_done_victim_rotate.complex_row0_wr_done_i_1_n_0 ;\n wire \\wr_done_victim_rotate.complex_row1_wr_done_i_1_n_0 ;\n wire wr_level_done_reg;\n wire wr_level_dqs_asrt;\n wire wr_level_dqs_asrt_i_1_n_0;\n wire wr_level_dqs_asrt_r1;\n wire wr_level_start_r_reg;\n wire wr_lvl_start_i_1_n_0;\n wire wr_victim_inc;\n wire wr_victim_inc0;\n wire wr_victim_inc_i_2_n_0;\n wire wr_victim_inc_i_3_n_0;\n wire [2:0]wr_victim_sel;\n wire \\wr_victim_sel[0]_i_1_n_0 ;\n wire \\wr_victim_sel[1]_i_1_n_0 ;\n wire \\wr_victim_sel[2]_i_1_n_0 ;\n wire [2:0]wr_victim_sel_ocal;\n wire \\wr_victim_sel_ocal[0]_i_1_n_0 ;\n wire \\wr_victim_sel_ocal[1]_i_1_n_0 ;\n wire \\wr_victim_sel_ocal[2]_i_1_n_0 ;\n wire wrcal_done_reg;\n wire wrcal_done_reg_0;\n wire wrcal_done_reg_1;\n wire wrcal_done_reg_10;\n wire wrcal_done_reg_11;\n wire wrcal_done_reg_2;\n wire wrcal_done_reg_3;\n wire wrcal_done_reg_4;\n wire wrcal_done_reg_5;\n wire wrcal_done_reg_6;\n wire wrcal_done_reg_7;\n wire wrcal_done_reg_8;\n wire wrcal_done_reg_9;\n wire \\wrcal_dqs_cnt_r_reg[0] ;\n wire wrcal_final_chk;\n wire wrcal_final_chk_i_1_n_0;\n wire wrcal_final_chk_i_2_n_0;\n wire wrcal_prech_req;\n wire wrcal_rd_wait;\n wire wrcal_rd_wait_i_1_n_0;\n wire wrcal_reads;\n wire wrcal_reads05_out;\n wire \\wrcal_reads[0]_i_1_n_0 ;\n wire \\wrcal_reads[1]_i_1_n_0 ;\n wire \\wrcal_reads[2]_i_1_n_0 ;\n wire \\wrcal_reads[3]_i_1_n_0 ;\n wire \\wrcal_reads[4]_i_1_n_0 ;\n wire \\wrcal_reads[5]_i_1_n_0 ;\n wire \\wrcal_reads[5]_i_2_n_0 ;\n wire \\wrcal_reads[6]_i_1_n_0 ;\n wire \\wrcal_reads[7]_i_2_n_0 ;\n wire \\wrcal_reads[7]_i_3_n_0 ;\n wire \\wrcal_reads[7]_i_5_n_0 ;\n wire \\wrcal_reads[7]_i_6_n_0 ;\n wire \\wrcal_reads[7]_i_7_n_0 ;\n wire \\wrcal_reads_reg_n_0_[0] ;\n wire \\wrcal_reads_reg_n_0_[1] ;\n wire \\wrcal_reads_reg_n_0_[2] ;\n wire \\wrcal_reads_reg_n_0_[3] ;\n wire \\wrcal_reads_reg_n_0_[4] ;\n wire \\wrcal_reads_reg_n_0_[5] ;\n wire \\wrcal_reads_reg_n_0_[6] ;\n wire \\wrcal_reads_reg_n_0_[7] ;\n wire wrcal_resume_r;\n wire wrcal_resume_w;\n wire wrcal_sanity_chk;\n wire wrcal_sanity_chk_done_reg;\n wire wrcal_sanity_chk_done_reg_0;\n wire wrcal_sanity_chk_r_reg;\n wire [5:5]wrcal_start_dly_r;\n wire \\wrcal_start_dly_r_reg[4]_srl5_n_0 ;\n wire wrcal_start_i_1_n_0;\n wire wrcal_start_pre;\n wire wrcal_start_reg_0;\n wire [3:2]wrcal_wr_cnt0;\n wire \\wrcal_wr_cnt[0]_i_1_n_0 ;\n wire \\wrcal_wr_cnt[1]_i_1_n_0 ;\n wire \\wrcal_wr_cnt[3]_i_1_n_0 ;\n wire \\wrcal_wr_cnt[3]_i_2_n_0 ;\n wire \\wrcal_wr_cnt[3]_i_4_n_0 ;\n wire [3:0]wrcal_wr_cnt_reg__0;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata[250]_i_1_n_0 ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata[254]_i_2_n_0 ;\n wire [255:0]\\write_buffer.wr_buf_out_data_reg[255] ;\n wire write_calib_i_1_n_0;\n wire write_calib_i_2_n_0;\n wire write_request_r_reg;\n wire wrlvl_active;\n wire wrlvl_active_i_1_n_0;\n wire wrlvl_active_r1;\n wire wrlvl_byte_redo;\n wire wrlvl_byte_redo_reg;\n wire wrlvl_byte_redo_reg_0;\n wire wrlvl_done_r;\n wire wrlvl_done_r1;\n wire wrlvl_final_if_rst;\n wire wrlvl_final_if_rst_i_1_n_0;\n wire wrlvl_final_if_rst_i_2_n_0;\n wire wrlvl_final_mux;\n wire wrlvl_final_mux_reg;\n wire wrlvl_final_mux_reg_0;\n wire wrlvl_odt;\n wire wrlvl_odt_ctl;\n wire wrlvl_odt_ctl_i_1_n_0;\n wire wrlvl_odt_ctl_i_2_n_0;\n wire wrlvl_odt_ctl_i_3_n_0;\n wire wrlvl_rank_done;\n wire wrlvl_rank_done_r1;\n wire wrlvl_rank_done_r6_reg_srl5_n_0;\n wire wrlvl_rank_done_r7;\n wire [3:1]\\NLW_oclkdelay_ref_cnt_reg[12]_i_1_CO_UNCONNECTED ;\n wire [3:2]\\NLW_oclkdelay_ref_cnt_reg[12]_i_1_O_UNCONNECTED ;\n\n assign in0 = init_complete_r_timing;\n assign out = init_complete_r1_timing;\n LUT6 #(\n .INIT(64'h000000000000E0EE)) \n \\DDR3_1rank.phy_int_cs_n[1]_i_1 \n (.I0(\\odd_cwl.phy_cas_n_reg[1]_0 ),\n .I1(\\DDR3_1rank.phy_int_cs_n[1]_i_3_n_0 ),\n .I2(rdlvl_stg1_start_int_i_2_n_0),\n .I3(\\DDR3_1rank.phy_int_cs_n[1]_i_4_n_0 ),\n .I4(\\DDR3_1rank.phy_int_cs_n[1]_i_5_n_0 ),\n .I5(\\DDR3_1rank.phy_int_cs_n[1]_i_6_n_0 ),\n .O(\\DDR3_1rank.phy_int_cs_n[1]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\DDR3_1rank.phy_int_cs_n[1]_i_2 \n (.I0(\\calib_cmd[2]_i_2_n_0 ),\n .I1(\\calib_cmd[2]_i_3_n_0 ),\n .O(\\odd_cwl.phy_cas_n_reg[1]_0 ));\n LUT6 #(\n .INIT(64'h0000000000000010)) \n \\DDR3_1rank.phy_int_cs_n[1]_i_3 \n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(Q[5]),\n .I3(oclk_calib_resume_level_reg_0),\n .I4(Q[3]),\n .I5(Q[4]),\n .O(\\DDR3_1rank.phy_int_cs_n[1]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair594\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\DDR3_1rank.phy_int_cs_n[1]_i_4 \n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(Q[2]),\n .I2(Q[0]),\n .O(\\DDR3_1rank.phy_int_cs_n[1]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFAAAAABBA)) \n \\DDR3_1rank.phy_int_cs_n[1]_i_5 \n (.I0(write_calib_i_2_n_0),\n .I1(read_calib_i_2_n_0),\n .I2(Q[2]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(prbs_rdlvl_start_i_2_n_0),\n .I5(temp_lmr_done),\n .O(\\DDR3_1rank.phy_int_cs_n[1]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\DDR3_1rank.phy_int_cs_n[1]_i_6 \n (.I0(\\num_refresh[3]_i_4_n_0 ),\n .I1(\\DDR3_1rank.phy_int_cs_n[1]_i_7_n_0 ),\n .I2(\\victim_sel[2]_i_5_n_0 ),\n .I3(\\DDR3_1rank.phy_int_cs_n[1]_i_8_n_0 ),\n .I4(complex_row1_rd_done_i_2_n_0),\n .I5(\\cnt_init_mr_r_reg[1]_0 ),\n .O(\\DDR3_1rank.phy_int_cs_n[1]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000040000)) \n \\DDR3_1rank.phy_int_cs_n[1]_i_7 \n (.I0(prbs_rdlvl_start_i_2_n_0),\n .I1(Q[2]),\n .I2(\\init_state_r_reg_n_0_[3] ),\n .I3(Q[5]),\n .I4(Q[3]),\n .I5(Q[4]),\n .O(\\DDR3_1rank.phy_int_cs_n[1]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h0000000800000000)) \n \\DDR3_1rank.phy_int_cs_n[1]_i_8 \n (.I0(Q[2]),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .I2(Q[4]),\n .I3(prbs_rdlvl_start_i_2_n_0),\n .I4(Q[5]),\n .I5(Q[3]),\n .O(\\DDR3_1rank.phy_int_cs_n[1]_i_8_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\DDR3_1rank.phy_int_cs_n_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\DDR3_1rank.phy_int_cs_n[1]_i_1_n_0 ),\n .Q(phy_cs_n),\n .S(rstdiv0_sync_r1_reg_rep__12));\n LUT2 #(\n .INIT(4'h2)) \n \\FSM_sequential_cal1_state_r[5]_i_10 \n (.I0(mpr_rdlvl_start_r_reg),\n .I1(mpr_rdlvl_start_r),\n .O(cal1_state_r1535_out));\n LUT6 #(\n .INIT(64'h0000000066666706)) \n \\back_to_back_reads_4_1.num_reads[0]_i_1 \n (.I0(num_reads[0]),\n .I1(num_reads0),\n .I2(Q[1]),\n .I3(Q[0]),\n .I4(\\back_to_back_reads_4_1.num_reads_reg[0]_0 ),\n .I5(rstdiv0_sync_r1_reg_rep__24),\n .O(\\back_to_back_reads_4_1.num_reads[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair501\" *) \n LUT3 #(\n .INIT(8'hFE)) \n \\back_to_back_reads_4_1.num_reads[0]_i_2 \n (.I0(num_reads[0]),\n .I1(num_reads[2]),\n .I2(num_reads[1]),\n .O(num_reads0));\n (* SOFT_HLUTNM = \"soft_lutpair518\" *) \n LUT5 #(\n .INIT(32'hFFFFFEFF)) \n \\back_to_back_reads_4_1.num_reads[0]_i_3 \n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(Q[2]),\n .I2(Q[5]),\n .I3(Q[3]),\n .I4(Q[4]),\n .O(\\back_to_back_reads_4_1.num_reads_reg[0]_0 ));\n LUT6 #(\n .INIT(64'h00000000CC320000)) \n \\back_to_back_reads_4_1.num_reads[1]_i_1 \n (.I0(\\back_to_back_reads_4_1.num_reads[1]_i_2_n_0 ),\n .I1(num_reads[1]),\n .I2(num_reads[2]),\n .I3(num_reads[0]),\n .I4(\\back_to_back_reads_4_1.num_reads_reg[1]_0 ),\n .I5(rstdiv0_sync_r1_reg_rep__24),\n .O(\\back_to_back_reads_4_1.num_reads[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000020)) \n \\back_to_back_reads_4_1.num_reads[1]_i_2 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .I1(Q[4]),\n .I2(Q[3]),\n .I3(Q[5]),\n .I4(Q[2]),\n .I5(\\init_state_r_reg_n_0_[3] ),\n .O(\\back_to_back_reads_4_1.num_reads[1]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h00C80000)) \n \\back_to_back_reads_4_1.num_reads[2]_i_1 \n (.I0(num_reads[1]),\n .I1(num_reads[2]),\n .I2(num_reads[0]),\n .I3(rstdiv0_sync_r1_reg_rep__20),\n .I4(\\back_to_back_reads_4_1.num_reads_reg[1]_0 ),\n .O(\\back_to_back_reads_4_1.num_reads[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\back_to_back_reads_4_1.num_reads_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\back_to_back_reads_4_1.num_reads[0]_i_1_n_0 ),\n .Q(num_reads[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\back_to_back_reads_4_1.num_reads_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\back_to_back_reads_4_1.num_reads[1]_i_1_n_0 ),\n .Q(num_reads[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\back_to_back_reads_4_1.num_reads_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\back_to_back_reads_4_1.num_reads[2]_i_1_n_0 ),\n .Q(num_reads[2]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0000010000009595)) \n burst_addr_r_i_2\n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(Q[1]),\n .I2(Q[2]),\n .I3(Q[0]),\n .I4(\\init_state_r[5]_i_26_n_0 ),\n .I5(Q[3]),\n .O(burst_addr_r_reg_1));\n FDRE #(\n .INIT(1'b0)) \n burst_addr_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(burst_addr_r_reg_2),\n .Q(burst_addr_r_reg_0),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\calib_cke_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(cnt_pwron_cke_done_r),\n .Q(calib_cke),\n .R(rstdiv0_sync_r1_reg_rep__12));\n (* SOFT_HLUTNM = \"soft_lutpair572\" *) \n LUT3 #(\n .INIT(8'hFB)) \n \\calib_cmd[0]_i_1 \n (.I0(wr_level_dqs_asrt),\n .I1(\\calib_cmd[2]_i_2_n_0 ),\n .I2(\\calib_cmd[2]_i_3_n_0 ),\n .O(\\calib_cmd[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair572\" *) \n LUT3 #(\n .INIT(8'h40)) \n \\calib_cmd[1]_i_1 \n (.I0(wr_level_dqs_asrt),\n .I1(\\calib_cmd[2]_i_2_n_0 ),\n .I2(\\calib_cmd[2]_i_3_n_0 ),\n .O(\\calib_cmd[1]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h04)) \n \\calib_cmd[2]_i_1 \n (.I0(wr_level_dqs_asrt),\n .I1(\\calib_cmd[2]_i_2_n_0 ),\n .I2(\\calib_cmd[2]_i_3_n_0 ),\n .O(\\calib_cmd[2]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h01)) \n \\calib_cmd[2]_i_2 \n (.I0(\\wrcal_wr_cnt[3]_i_2_n_0 ),\n .I1(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .I2(\\calib_cmd[2]_i_4_n_0 ),\n .O(\\calib_cmd[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFEFEFEFEFFFFFEFF)) \n \\calib_cmd[2]_i_3 \n (.I0(\\calib_cmd[2]_i_5_n_0 ),\n .I1(\\calib_cmd[2]_i_6_n_0 ),\n .I2(\\back_to_back_reads_4_1.num_reads[1]_i_2_n_0 ),\n .I3(\\calib_cmd[2]_i_7_n_0 ),\n .I4(\\calib_cmd[2]_i_8_n_0 ),\n .I5(rdlvl_pi_incdec),\n .O(\\calib_cmd[2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h08080000000000FF)) \n \\calib_cmd[2]_i_4 \n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(Q[2]),\n .I2(read_calib_i_2_n_0),\n .I3(prbs_rdlvl_start_i_3_n_0),\n .I4(Q[0]),\n .I5(Q[1]),\n .O(\\calib_cmd[2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000040048)) \n \\calib_cmd[2]_i_5 \n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(Q[3]),\n .I3(\\init_state_r[5]_i_26_n_0 ),\n .I4(Q[2]),\n .I5(\\init_state_r_reg_n_0_[3] ),\n .O(\\calib_cmd[2]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000040200)) \n \\calib_cmd[2]_i_6 \n (.I0(Q[1]),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .I2(Q[0]),\n .I3(Q[2]),\n .I4(Q[3]),\n .I5(\\init_state_r[5]_i_26_n_0 ),\n .O(\\calib_cmd[2]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair504\" *) \n LUT5 #(\n .INIT(32'hFFFFFDFF)) \n \\calib_cmd[2]_i_7 \n (.I0(Q[0]),\n .I1(read_calib_i_2_n_0),\n .I2(Q[2]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[1]),\n .O(\\calib_cmd[2]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000100)) \n \\calib_cmd[2]_i_8 \n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(Q[4]),\n .I3(Q[3]),\n .I4(Q[5]),\n .I5(oclk_calib_resume_level_reg_0),\n .O(\\calib_cmd[2]_i_8_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\calib_cmd_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\calib_cmd[0]_i_1_n_0 ),\n .Q(calib_cmd[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\calib_cmd_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\calib_cmd[1]_i_1_n_0 ),\n .Q(calib_cmd[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\calib_cmd_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\calib_cmd[2]_i_1_n_0 ),\n .Q(calib_cmd[2]),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h8)) \n calib_ctl_wren_i_1\n (.I0(cnt_pwron_cke_done_r),\n .I1(\\mcGo_r_reg[15] ),\n .O(calib_ctl_wren0));\n FDRE #(\n .INIT(1'b0)) \n calib_ctl_wren_reg\n (.C(CLK),\n .CE(1'b1),\n .D(calib_ctl_wren0),\n .Q(calib_ctl_wren),\n .R(rstdiv0_sync_r1_reg_rep__11));\n LUT6 #(\n .INIT(64'h8888000088800080)) \n \\calib_data_offset_0[2]_i_1 \n (.I0(pi_calib_done),\n .I1(\\calib_cmd[2]_i_3_n_0 ),\n .I2(\\rd_byte_data_offset_reg[0][3] [0]),\n .I3(init_dqsfound_done_r2),\n .I4(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3] [0]),\n .I5(pi_dqs_found_done_r1),\n .O(\\calib_data_offset_0[2]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'hB)) \n \\calib_data_offset_0[3]_i_1 \n (.I0(wr_level_dqs_asrt),\n .I1(\\calib_cmd[2]_i_2_n_0 ),\n .O(\\calib_data_offset_0[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8888000088800080)) \n \\calib_data_offset_0[3]_i_2 \n (.I0(pi_calib_done),\n .I1(\\calib_cmd[2]_i_3_n_0 ),\n .I2(\\rd_byte_data_offset_reg[0][3] [1]),\n .I3(init_dqsfound_done_r2),\n .I4(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3] [1]),\n .I5(pi_dqs_found_done_r1),\n .O(\\calib_data_offset_0[3]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'hBFFF)) \n \\calib_data_offset_0[5]_i_1 \n (.I0(wr_level_dqs_asrt),\n .I1(\\calib_cmd[2]_i_2_n_0 ),\n .I2(pi_calib_done),\n .I3(\\calib_cmd[2]_i_3_n_0 ),\n .O(\\calib_data_offset_0[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\calib_data_offset_0_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_done_r1_reg_3),\n .Q(calib_data_offset_0[0]),\n .R(\\calib_data_offset_0[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\calib_data_offset_0_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_done_r1_reg_2),\n .Q(calib_data_offset_0[1]),\n .R(\\calib_data_offset_0[5]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\calib_data_offset_0_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\calib_data_offset_0[2]_i_1_n_0 ),\n .Q(calib_data_offset_0[2]),\n .S(\\calib_data_offset_0[3]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\calib_data_offset_0_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\calib_data_offset_0[3]_i_2_n_0 ),\n .Q(calib_data_offset_0[3]),\n .S(\\calib_data_offset_0[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\calib_data_offset_0_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_done_r1_reg_1),\n .Q(calib_data_offset_0[4]),\n .R(\\calib_data_offset_0[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\calib_data_offset_0_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_done_r1_reg_0),\n .Q(calib_data_offset_0[5]),\n .R(\\calib_data_offset_0[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8888000088800080)) \n \\calib_data_offset_1[2]_i_1 \n (.I0(pi_calib_done),\n .I1(\\calib_cmd[2]_i_3_n_0 ),\n .I2(\\rd_byte_data_offset_reg[0][9] [0]),\n .I3(init_dqsfound_done_r2),\n .I4(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] [0]),\n .I5(pi_dqs_found_done_r1),\n .O(\\calib_data_offset_1[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8888000088800080)) \n \\calib_data_offset_1[3]_i_1 \n (.I0(pi_calib_done),\n .I1(\\calib_cmd[2]_i_3_n_0 ),\n .I2(\\rd_byte_data_offset_reg[0][9] [1]),\n .I3(init_dqsfound_done_r2),\n .I4(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] [1]),\n .I5(pi_dqs_found_done_r1),\n .O(\\calib_data_offset_1[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\calib_data_offset_1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_done_r1_reg_7),\n .Q(calib_data_offset_1[0]),\n .R(\\calib_data_offset_0[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\calib_data_offset_1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_done_r1_reg_6),\n .Q(calib_data_offset_1[1]),\n .R(\\calib_data_offset_0[5]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\calib_data_offset_1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\calib_data_offset_1[2]_i_1_n_0 ),\n .Q(calib_data_offset_1[2]),\n .S(\\calib_data_offset_0[3]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\calib_data_offset_1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\calib_data_offset_1[3]_i_1_n_0 ),\n .Q(calib_data_offset_1[3]),\n .S(\\calib_data_offset_0[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\calib_data_offset_1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_done_r1_reg_5),\n .Q(calib_data_offset_1[4]),\n .R(\\calib_data_offset_0[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\calib_data_offset_1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_done_r1_reg_4),\n .Q(calib_data_offset_1[5]),\n .R(\\calib_data_offset_0[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h0000AAA2)) \n \\calib_odt[0]_i_1 \n (.I0(\\gen_rnk[0].mr1_r_reg[0]_196 ),\n .I1(\\calib_cmd[2]_i_2_n_0 ),\n .I2(\\calib_odt[0]_i_2_n_0 ),\n .I3(\\calib_odt[0]_i_3_n_0 ),\n .I4(rstdiv0_sync_r1_reg_rep__23),\n .O(\\calib_odt[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hCFDCCFDFCCDCCCDF)) \n \\calib_odt[0]_i_2 \n (.I0(first_wrcal_pat_r_i_2_n_0),\n .I1(stg1_wr_done),\n .I2(Q[1]),\n .I3(Q[0]),\n .I4(complex_ocal_odt_ext_i_4_n_0),\n .I5(\\stg1_wr_rd_cnt[4]_i_5_n_0 ),\n .O(\\calib_odt[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF2000)) \n \\calib_odt[0]_i_3 \n (.I0(wrlvl_odt),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .I2(Q[2]),\n .I3(\\calib_odt[0]_i_4_n_0 ),\n .I4(complex_odt_ext),\n .I5(complex_ocal_odt_ext),\n .O(\\calib_odt[0]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair522\" *) \n LUT5 #(\n .INIT(32'h00100000)) \n \\calib_odt[0]_i_4 \n (.I0(Q[4]),\n .I1(Q[5]),\n .I2(Q[0]),\n .I3(Q[3]),\n .I4(Q[1]),\n .O(\\calib_odt[0]_i_4_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\calib_odt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\calib_odt[0]_i_1_n_0 ),\n .Q(calib_odt),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair556\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\calib_seq[0]_i_1 \n (.I0(cnt_pwron_cke_done_r),\n .I1(\\mcGo_r_reg[15] ),\n .I2(\\phy_ctl_wd_i1_reg[24] [9]),\n .O(\\calib_seq[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair556\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\calib_seq[1]_i_1 \n (.I0(\\phy_ctl_wd_i1_reg[24] [9]),\n .I1(cnt_pwron_cke_done_r),\n .I2(\\mcGo_r_reg[15] ),\n .I3(\\phy_ctl_wd_i1_reg[24] [10]),\n .O(\\calib_seq[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\calib_seq_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\calib_seq[0]_i_1_n_0 ),\n .Q(\\phy_ctl_wd_i1_reg[24] [9]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE #(\n .INIT(1'b0)) \n \\calib_seq_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\calib_seq[1]_i_1_n_0 ),\n .Q(\\phy_ctl_wd_i1_reg[24] [10]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n LUT1 #(\n .INIT(2'h1)) \n calib_wrdata_en_i_1\n (.I0(\\calib_cmd[2]_i_2_n_0 ),\n .O(phy_wrdata_en));\n FDRE #(\n .INIT(1'b0)) \n calib_wrdata_en_reg\n (.C(CLK),\n .CE(1'b1),\n .D(phy_wrdata_en),\n .Q(calib_wrdata_en),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0000000000008000)) \n cnt_cmd_done_m7_r_i_1\n (.I0(\\cnt_cmd_r_reg_n_0_[6] ),\n .I1(\\cnt_cmd_r_reg_n_0_[5] ),\n .I2(\\cnt_cmd_r_reg_n_0_[4] ),\n .I3(\\cnt_cmd_r_reg_n_0_[3] ),\n .I4(cnt_cmd_done_m7_r_i_2_n_0),\n .I5(\\cnt_cmd_r_reg_n_0_[2] ),\n .O(cnt_cmd_done_m7_r_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair601\" *) \n LUT2 #(\n .INIT(4'hE)) \n cnt_cmd_done_m7_r_i_2\n (.I0(\\cnt_cmd_r_reg_n_0_[0] ),\n .I1(\\cnt_cmd_r_reg_n_0_[1] ),\n .O(cnt_cmd_done_m7_r_i_2_n_0));\n FDRE #(\n .INIT(1'b0)) \n cnt_cmd_done_m7_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cnt_cmd_done_m7_r_i_1_n_0),\n .Q(cnt_cmd_done_m7_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair577\" *) \n LUT3 #(\n .INIT(8'h80)) \n cnt_cmd_done_r_i_1\n (.I0(\\cnt_cmd_r[6]_i_5_n_0 ),\n .I1(\\cnt_cmd_r_reg_n_0_[5] ),\n .I2(\\cnt_cmd_r_reg_n_0_[6] ),\n .O(cnt_cmd_done_r_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n cnt_cmd_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cnt_cmd_done_r_i_1_n_0),\n .Q(cnt_cmd_done_r),\n .R(1'b0));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_cmd_r[0]_i_1 \n (.I0(\\cnt_cmd_r_reg_n_0_[0] ),\n .O(\\cnt_cmd_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair601\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\cnt_cmd_r[1]_i_1 \n (.I0(\\cnt_cmd_r_reg_n_0_[1] ),\n .I1(\\cnt_cmd_r_reg_n_0_[0] ),\n .O(\\cnt_cmd_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair552\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\cnt_cmd_r[2]_i_1 \n (.I0(\\cnt_cmd_r_reg_n_0_[2] ),\n .I1(\\cnt_cmd_r_reg_n_0_[1] ),\n .I2(\\cnt_cmd_r_reg_n_0_[0] ),\n .O(\\cnt_cmd_r[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair552\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\cnt_cmd_r[3]_i_1 \n (.I0(\\cnt_cmd_r_reg_n_0_[3] ),\n .I1(\\cnt_cmd_r_reg_n_0_[2] ),\n .I2(\\cnt_cmd_r_reg_n_0_[0] ),\n .I3(\\cnt_cmd_r_reg_n_0_[1] ),\n .O(\\cnt_cmd_r[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair484\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\cnt_cmd_r[4]_i_1 \n (.I0(\\cnt_cmd_r_reg_n_0_[4] ),\n .I1(\\cnt_cmd_r_reg_n_0_[3] ),\n .I2(\\cnt_cmd_r_reg_n_0_[1] ),\n .I3(\\cnt_cmd_r_reg_n_0_[0] ),\n .I4(\\cnt_cmd_r_reg_n_0_[2] ),\n .O(\\cnt_cmd_r[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n \\cnt_cmd_r[5]_i_1 \n (.I0(\\cnt_cmd_r_reg_n_0_[5] ),\n .I1(\\cnt_cmd_r_reg_n_0_[4] ),\n .I2(\\cnt_cmd_r_reg_n_0_[3] ),\n .I3(\\cnt_cmd_r_reg_n_0_[1] ),\n .I4(\\cnt_cmd_r_reg_n_0_[0] ),\n .I5(\\cnt_cmd_r_reg_n_0_[2] ),\n .O(\\cnt_cmd_r[5]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hFE)) \n \\cnt_cmd_r[6]_i_1 \n (.I0(\\cnt_cmd_r[6]_i_3_n_0 ),\n .I1(\\cnt_cmd_r[6]_i_4_n_0 ),\n .I2(Q[5]),\n .O(\\cnt_cmd_r[6]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair577\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\cnt_cmd_r[6]_i_2 \n (.I0(\\cnt_cmd_r_reg_n_0_[6] ),\n .I1(\\cnt_cmd_r_reg_n_0_[5] ),\n .I2(\\cnt_cmd_r[6]_i_5_n_0 ),\n .O(\\cnt_cmd_r[6]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h5544151145411111)) \n \\cnt_cmd_r[6]_i_3 \n (.I0(Q[0]),\n .I1(Q[4]),\n .I2(\\init_state_r_reg_n_0_[3] ),\n .I3(Q[2]),\n .I4(Q[3]),\n .I5(Q[1]),\n .O(\\cnt_cmd_r[6]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hA8AAA8A2A820A8AA)) \n \\cnt_cmd_r[6]_i_4 \n (.I0(Q[0]),\n .I1(Q[3]),\n .I2(Q[4]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[1]),\n .I5(Q[2]),\n .O(\\cnt_cmd_r[6]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair484\" *) \n LUT5 #(\n .INIT(32'h80000000)) \n \\cnt_cmd_r[6]_i_5 \n (.I0(\\cnt_cmd_r_reg_n_0_[2] ),\n .I1(\\cnt_cmd_r_reg_n_0_[0] ),\n .I2(\\cnt_cmd_r_reg_n_0_[1] ),\n .I3(\\cnt_cmd_r_reg_n_0_[3] ),\n .I4(\\cnt_cmd_r_reg_n_0_[4] ),\n .O(\\cnt_cmd_r[6]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_cmd_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cnt_cmd_r[0]_i_1_n_0 ),\n .Q(\\cnt_cmd_r_reg_n_0_[0] ),\n .R(\\cnt_cmd_r[6]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_cmd_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cnt_cmd_r[1]_i_1_n_0 ),\n .Q(\\cnt_cmd_r_reg_n_0_[1] ),\n .R(\\cnt_cmd_r[6]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_cmd_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cnt_cmd_r[2]_i_1_n_0 ),\n .Q(\\cnt_cmd_r_reg_n_0_[2] ),\n .R(\\cnt_cmd_r[6]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_cmd_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cnt_cmd_r[3]_i_1_n_0 ),\n .Q(\\cnt_cmd_r_reg_n_0_[3] ),\n .R(\\cnt_cmd_r[6]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_cmd_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cnt_cmd_r[4]_i_1_n_0 ),\n .Q(\\cnt_cmd_r_reg_n_0_[4] ),\n .R(\\cnt_cmd_r[6]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_cmd_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cnt_cmd_r[5]_i_1_n_0 ),\n .Q(\\cnt_cmd_r_reg_n_0_[5] ),\n .R(\\cnt_cmd_r[6]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_cmd_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cnt_cmd_r[6]_i_2_n_0 ),\n .Q(\\cnt_cmd_r_reg_n_0_[6] ),\n .R(\\cnt_cmd_r[6]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n cnt_dllk_zqinit_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cnt_dllk_zqinit_done_r_reg_0),\n .Q(cnt_dllk_zqinit_done_r),\n .R(cnt_dllk_zqinit_r));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_dllk_zqinit_r[0]_i_1 \n (.I0(cnt_dllk_zqinit_r_reg__0[0]),\n .O(p_0_in__3[0]));\n (* SOFT_HLUTNM = \"soft_lutpair595\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\cnt_dllk_zqinit_r[1]_i_1 \n (.I0(cnt_dllk_zqinit_r_reg__0[1]),\n .I1(cnt_dllk_zqinit_r_reg__0[0]),\n .O(p_0_in__3[1]));\n (* SOFT_HLUTNM = \"soft_lutpair595\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\cnt_dllk_zqinit_r[2]_i_1 \n (.I0(cnt_dllk_zqinit_r_reg__0[2]),\n .I1(cnt_dllk_zqinit_r_reg__0[0]),\n .I2(cnt_dllk_zqinit_r_reg__0[1]),\n .O(p_0_in__3[2]));\n (* SOFT_HLUTNM = \"soft_lutpair517\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\cnt_dllk_zqinit_r[3]_i_1 \n (.I0(cnt_dllk_zqinit_r_reg__0[3]),\n .I1(cnt_dllk_zqinit_r_reg__0[1]),\n .I2(cnt_dllk_zqinit_r_reg__0[0]),\n .I3(cnt_dllk_zqinit_r_reg__0[2]),\n .O(p_0_in__3[3]));\n (* SOFT_HLUTNM = \"soft_lutpair517\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\cnt_dllk_zqinit_r[4]_i_1 \n (.I0(cnt_dllk_zqinit_r_reg__0[4]),\n .I1(cnt_dllk_zqinit_r_reg__0[2]),\n .I2(cnt_dllk_zqinit_r_reg__0[0]),\n .I3(cnt_dllk_zqinit_r_reg__0[1]),\n .I4(cnt_dllk_zqinit_r_reg__0[3]),\n .O(p_0_in__3[4]));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n \\cnt_dllk_zqinit_r[5]_i_1 \n (.I0(cnt_dllk_zqinit_r_reg__0[5]),\n .I1(cnt_dllk_zqinit_r_reg__0[3]),\n .I2(cnt_dllk_zqinit_r_reg__0[1]),\n .I3(cnt_dllk_zqinit_r_reg__0[0]),\n .I4(cnt_dllk_zqinit_r_reg__0[2]),\n .I5(cnt_dllk_zqinit_r_reg__0[4]),\n .O(p_0_in__3[5]));\n (* SOFT_HLUTNM = \"soft_lutpair592\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\cnt_dllk_zqinit_r[6]_i_1 \n (.I0(mem_init_done_r_reg_0[0]),\n .I1(mem_init_done_r_reg_1),\n .O(p_0_in__3[6]));\n LUT6 #(\n .INIT(64'h0000000000000010)) \n \\cnt_dllk_zqinit_r[7]_i_1 \n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(\\wrcal_reads[7]_i_5_n_0 ),\n .I3(Q[5]),\n .I4(Q[4]),\n .I5(Q[3]),\n .O(cnt_dllk_zqinit_r));\n (* SOFT_HLUTNM = \"soft_lutpair592\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\cnt_dllk_zqinit_r[7]_i_2 \n (.I0(mem_init_done_r_reg_0[1]),\n .I1(mem_init_done_r_reg_1),\n .I2(mem_init_done_r_reg_0[0]),\n .O(p_0_in__3[7]));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_dllk_zqinit_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__3[0]),\n .Q(cnt_dllk_zqinit_r_reg__0[0]),\n .R(cnt_dllk_zqinit_r));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_dllk_zqinit_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__3[1]),\n .Q(cnt_dllk_zqinit_r_reg__0[1]),\n .R(cnt_dllk_zqinit_r));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_dllk_zqinit_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__3[2]),\n .Q(cnt_dllk_zqinit_r_reg__0[2]),\n .R(cnt_dllk_zqinit_r));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_dllk_zqinit_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__3[3]),\n .Q(cnt_dllk_zqinit_r_reg__0[3]),\n .R(cnt_dllk_zqinit_r));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_dllk_zqinit_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__3[4]),\n .Q(cnt_dllk_zqinit_r_reg__0[4]),\n .R(cnt_dllk_zqinit_r));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_dllk_zqinit_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__3[5]),\n .Q(cnt_dllk_zqinit_r_reg__0[5]),\n .R(cnt_dllk_zqinit_r));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_dllk_zqinit_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__3[6]),\n .Q(mem_init_done_r_reg_0[0]),\n .R(cnt_dllk_zqinit_r));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_dllk_zqinit_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__3[7]),\n .Q(mem_init_done_r_reg_0[1]),\n .R(cnt_dllk_zqinit_r));\n FDRE #(\n .INIT(1'b0)) \n cnt_init_af_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cnt_init_af_done_r_reg_0),\n .Q(cnt_init_af_done_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair497\" *) \n LUT4 #(\n .INIT(16'h009A)) \n \\cnt_init_af_r[0]_i_1 \n (.I0(cnt_init_af_r[0]),\n .I1(mem_init_done_r),\n .I2(\\cnt_init_mr_r_reg[1]_0 ),\n .I3(\\reg_ctrl_cnt_r_reg[3]_0 ),\n .O(\\cnt_init_af_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair497\" *) \n LUT5 #(\n .INIT(32'h00009AAA)) \n \\cnt_init_af_r[1]_i_1 \n (.I0(cnt_init_af_r[1]),\n .I1(mem_init_done_r),\n .I2(\\cnt_init_mr_r_reg[1]_0 ),\n .I3(cnt_init_af_r[0]),\n .I4(\\reg_ctrl_cnt_r_reg[3]_0 ),\n .O(\\cnt_init_af_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_init_af_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cnt_init_af_r[0]_i_1_n_0 ),\n .Q(cnt_init_af_r[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_init_af_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cnt_init_af_r[1]_i_1_n_0 ),\n .Q(cnt_init_af_r[1]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0000000004000000)) \n cnt_init_mr_done_r_i_2\n (.I0(Q[5]),\n .I1(Q[3]),\n .I2(Q[4]),\n .I3(\\init_state_r_reg[1]_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .I5(mem_init_done_r),\n .O(cnt_init_mr_r1));\n FDRE #(\n .INIT(1'b0)) \n cnt_init_mr_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cnt_init_mr_done_r_reg_0),\n .Q(cnt_init_mr_done_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00006606)) \n \\cnt_init_mr_r[0]_i_1 \n (.I0(cnt_init_mr_r[0]),\n .I1(temp_lmr_done),\n .I2(\\cnt_init_mr_r_reg[1]_0 ),\n .I3(mem_init_done_r),\n .I4(\\reg_ctrl_cnt_r_reg[3]_0 ),\n .O(\\cnt_init_mr_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h000000006A6A006A)) \n \\cnt_init_mr_r[1]_i_1 \n (.I0(cnt_init_mr_r[1]),\n .I1(temp_lmr_done),\n .I2(cnt_init_mr_r[0]),\n .I3(\\cnt_init_mr_r_reg[1]_0 ),\n .I4(mem_init_done_r),\n .I5(\\reg_ctrl_cnt_r_reg[3]_0 ),\n .O(\\cnt_init_mr_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\cnt_init_mr_r[1]_i_2 \n (.I0(Q[1]),\n .I1(Q[4]),\n .I2(Q[5]),\n .I3(oclk_calib_resume_level_reg_0),\n .I4(Q[3]),\n .I5(Q[0]),\n .O(temp_lmr_done));\n LUT6 #(\n .INIT(64'h0000000000080000)) \n \\cnt_init_mr_r[1]_i_3 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .I2(Q[2]),\n .I3(Q[4]),\n .I4(Q[3]),\n .I5(Q[5]),\n .O(\\cnt_init_mr_r_reg[1]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_init_mr_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cnt_init_mr_r[0]_i_1_n_0 ),\n .Q(cnt_init_mr_r[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_init_mr_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cnt_init_mr_r[1]_i_1_n_0 ),\n .Q(cnt_init_mr_r[1]),\n .R(1'b0));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_pwron_ce_r[0]_i_1 \n (.I0(cnt_pwron_ce_r_reg__0[0]),\n .O(p_0_in__0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair599\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\cnt_pwron_ce_r[1]_i_1 \n (.I0(cnt_pwron_ce_r_reg__0[1]),\n .I1(cnt_pwron_ce_r_reg__0[0]),\n .O(p_0_in__0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair599\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\cnt_pwron_ce_r[2]_i_1 \n (.I0(cnt_pwron_ce_r_reg__0[2]),\n .I1(cnt_pwron_ce_r_reg__0[0]),\n .I2(cnt_pwron_ce_r_reg__0[1]),\n .O(p_0_in__0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair492\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\cnt_pwron_ce_r[3]_i_1 \n (.I0(cnt_pwron_ce_r_reg__0[3]),\n .I1(cnt_pwron_ce_r_reg__0[1]),\n .I2(cnt_pwron_ce_r_reg__0[0]),\n .I3(cnt_pwron_ce_r_reg__0[2]),\n .O(p_0_in__0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair492\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\cnt_pwron_ce_r[4]_i_1 \n (.I0(cnt_pwron_ce_r_reg__0[4]),\n .I1(cnt_pwron_ce_r_reg__0[2]),\n .I2(cnt_pwron_ce_r_reg__0[0]),\n .I3(cnt_pwron_ce_r_reg__0[1]),\n .I4(cnt_pwron_ce_r_reg__0[3]),\n .O(p_0_in__0[4]));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n \\cnt_pwron_ce_r[5]_i_1 \n (.I0(cnt_pwron_ce_r_reg__0[5]),\n .I1(cnt_pwron_ce_r_reg__0[3]),\n .I2(cnt_pwron_ce_r_reg__0[1]),\n .I3(cnt_pwron_ce_r_reg__0[0]),\n .I4(cnt_pwron_ce_r_reg__0[2]),\n .I5(cnt_pwron_ce_r_reg__0[4]),\n .O(p_0_in__0[5]));\n (* SOFT_HLUTNM = \"soft_lutpair598\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\cnt_pwron_ce_r[6]_i_1 \n (.I0(cnt_pwron_ce_r_reg__0[6]),\n .I1(pwron_ce_r_i_3_n_0),\n .O(p_0_in__0[6]));\n (* SOFT_HLUTNM = \"soft_lutpair598\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\cnt_pwron_ce_r[7]_i_1 \n (.I0(cnt_pwron_ce_r_reg__0[7]),\n .I1(pwron_ce_r_i_3_n_0),\n .I2(cnt_pwron_ce_r_reg__0[6]),\n .O(p_0_in__0[7]));\n (* SOFT_HLUTNM = \"soft_lutpair508\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\cnt_pwron_ce_r[8]_i_1 \n (.I0(cnt_pwron_ce_r_reg__0[8]),\n .I1(cnt_pwron_ce_r_reg__0[6]),\n .I2(pwron_ce_r_i_3_n_0),\n .I3(cnt_pwron_ce_r_reg__0[7]),\n .O(p_0_in__0[8]));\n (* SOFT_HLUTNM = \"soft_lutpair508\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\cnt_pwron_ce_r[9]_i_1 \n (.I0(cnt_pwron_ce_r_reg__0[9]),\n .I1(cnt_pwron_ce_r_reg__0[7]),\n .I2(pwron_ce_r_i_3_n_0),\n .I3(cnt_pwron_ce_r_reg__0[6]),\n .I4(cnt_pwron_ce_r_reg__0[8]),\n .O(p_0_in__0[9]));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_pwron_ce_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0[0]),\n .Q(cnt_pwron_ce_r_reg__0[0]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_pwron_ce_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0[1]),\n .Q(cnt_pwron_ce_r_reg__0[1]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_pwron_ce_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0[2]),\n .Q(cnt_pwron_ce_r_reg__0[2]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_pwron_ce_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0[3]),\n .Q(cnt_pwron_ce_r_reg__0[3]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_pwron_ce_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0[4]),\n .Q(cnt_pwron_ce_r_reg__0[4]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_pwron_ce_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0[5]),\n .Q(cnt_pwron_ce_r_reg__0[5]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_pwron_ce_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0[6]),\n .Q(cnt_pwron_ce_r_reg__0[6]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_pwron_ce_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0[7]),\n .Q(cnt_pwron_ce_r_reg__0[7]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_pwron_ce_r_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0[8]),\n .Q(cnt_pwron_ce_r_reg__0[8]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_pwron_ce_r_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0[9]),\n .Q(cnt_pwron_ce_r_reg__0[9]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n LUT6 #(\n .INIT(64'hFEFFFFFFFFFFFFFF)) \n cnt_pwron_cke_done_r_i_2\n (.I0(cnt_pwron_r_reg__0[8]),\n .I1(cnt_pwron_r_reg__0[6]),\n .I2(\\cnt_pwron_r_reg[7]_0 [2]),\n .I3(cnt_pwron_r_reg__0[4]),\n .I4(cnt_pwron_r_reg__0[3]),\n .I5(cnt_pwron_r_reg__0[2]),\n .O(cnt_pwron_cke_done_r_reg_0));\n FDRE #(\n .INIT(1'b0)) \n cnt_pwron_cke_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cnt_pwron_cke_done_r_reg_1),\n .Q(cnt_pwron_cke_done_r),\n .R(1'b0));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_pwron_r[0]_i_1 \n (.I0(\\cnt_pwron_r_reg[7]_0 [0]),\n .O(p_0_in__0__0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair597\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\cnt_pwron_r[1]_i_1 \n (.I0(\\cnt_pwron_r_reg[7]_0 [1]),\n .I1(\\cnt_pwron_r_reg[7]_0 [0]),\n .O(p_0_in__0__0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair597\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\cnt_pwron_r[2]_i_1 \n (.I0(cnt_pwron_r_reg__0[2]),\n .I1(\\cnt_pwron_r_reg[7]_0 [0]),\n .I2(\\cnt_pwron_r_reg[7]_0 [1]),\n .O(p_0_in__0__0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair512\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\cnt_pwron_r[3]_i_1 \n (.I0(cnt_pwron_r_reg__0[3]),\n .I1(\\cnt_pwron_r_reg[7]_0 [1]),\n .I2(\\cnt_pwron_r_reg[7]_0 [0]),\n .I3(cnt_pwron_r_reg__0[2]),\n .O(p_0_in__0__0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair512\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\cnt_pwron_r[4]_i_1 \n (.I0(cnt_pwron_r_reg__0[4]),\n .I1(cnt_pwron_r_reg__0[3]),\n .I2(cnt_pwron_r_reg__0[2]),\n .I3(\\cnt_pwron_r_reg[7]_0 [1]),\n .I4(\\cnt_pwron_r_reg[7]_0 [0]),\n .O(p_0_in__0__0[4]));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n \\cnt_pwron_r[5]_i_1 \n (.I0(\\cnt_pwron_r_reg[7]_0 [2]),\n .I1(\\cnt_pwron_r_reg[7]_0 [0]),\n .I2(\\cnt_pwron_r_reg[7]_0 [1]),\n .I3(cnt_pwron_r_reg__0[2]),\n .I4(cnt_pwron_r_reg__0[3]),\n .I5(cnt_pwron_r_reg__0[4]),\n .O(p_0_in__0__0[5]));\n LUT6 #(\n .INIT(64'hA6AAAAAAAAAAAAAA)) \n \\cnt_pwron_r[6]_i_1 \n (.I0(cnt_pwron_r_reg__0[6]),\n .I1(cnt_pwron_r_reg__0[4]),\n .I2(\\cnt_pwron_r[6]_i_2_n_0 ),\n .I3(\\cnt_pwron_r_reg[7]_0 [1]),\n .I4(\\cnt_pwron_r_reg[7]_0 [0]),\n .I5(\\cnt_pwron_r_reg[7]_0 [2]),\n .O(p_0_in__0__0[6]));\n LUT2 #(\n .INIT(4'h7)) \n \\cnt_pwron_r[6]_i_2 \n (.I0(cnt_pwron_r_reg__0[3]),\n .I1(cnt_pwron_r_reg__0[2]),\n .O(\\cnt_pwron_r[6]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair532\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\cnt_pwron_r[7]_i_1 \n (.I0(\\cnt_pwron_r_reg[7]_0 [3]),\n .I1(\\cnt_pwron_r[8]_i_2_n_0 ),\n .I2(cnt_pwron_r_reg__0[6]),\n .O(p_0_in__0__0[7]));\n (* SOFT_HLUTNM = \"soft_lutpair532\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\cnt_pwron_r[8]_i_1 \n (.I0(cnt_pwron_r_reg__0[8]),\n .I1(cnt_pwron_r_reg__0[6]),\n .I2(\\cnt_pwron_r[8]_i_2_n_0 ),\n .I3(\\cnt_pwron_r_reg[7]_0 [3]),\n .O(p_0_in__0__0[8]));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\cnt_pwron_r[8]_i_2 \n (.I0(\\cnt_pwron_r_reg[7]_0 [2]),\n .I1(\\cnt_pwron_r_reg[7]_0 [0]),\n .I2(\\cnt_pwron_r_reg[7]_0 [1]),\n .I3(cnt_pwron_r_reg__0[2]),\n .I4(cnt_pwron_r_reg__0[3]),\n .I5(cnt_pwron_r_reg__0[4]),\n .O(\\cnt_pwron_r[8]_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_pwron_r_reg[0] \n (.C(CLK),\n .CE(pwron_ce_r),\n .D(p_0_in__0__0[0]),\n .Q(\\cnt_pwron_r_reg[7]_0 [0]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_pwron_r_reg[1] \n (.C(CLK),\n .CE(pwron_ce_r),\n .D(p_0_in__0__0[1]),\n .Q(\\cnt_pwron_r_reg[7]_0 [1]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_pwron_r_reg[2] \n (.C(CLK),\n .CE(pwron_ce_r),\n .D(p_0_in__0__0[2]),\n .Q(cnt_pwron_r_reg__0[2]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_pwron_r_reg[3] \n (.C(CLK),\n .CE(pwron_ce_r),\n .D(p_0_in__0__0[3]),\n .Q(cnt_pwron_r_reg__0[3]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_pwron_r_reg[4] \n (.C(CLK),\n .CE(pwron_ce_r),\n .D(p_0_in__0__0[4]),\n .Q(cnt_pwron_r_reg__0[4]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_pwron_r_reg[5] \n (.C(CLK),\n .CE(pwron_ce_r),\n .D(p_0_in__0__0[5]),\n .Q(\\cnt_pwron_r_reg[7]_0 [2]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_pwron_r_reg[6] \n (.C(CLK),\n .CE(pwron_ce_r),\n .D(p_0_in__0__0[6]),\n .Q(cnt_pwron_r_reg__0[6]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_pwron_r_reg[7] \n (.C(CLK),\n .CE(pwron_ce_r),\n .D(p_0_in__0__0[7]),\n .Q(\\cnt_pwron_r_reg[7]_0 [3]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_pwron_r_reg[8] \n (.C(CLK),\n .CE(pwron_ce_r),\n .D(p_0_in__0__0[8]),\n .Q(cnt_pwron_r_reg__0[8]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n LUT6 #(\n .INIT(64'hFFFEFFFFFFFFFFFF)) \n cnt_pwron_reset_done_r_i_2\n (.I0(cnt_pwron_r_reg__0[8]),\n .I1(cnt_pwron_r_reg__0[6]),\n .I2(\\cnt_pwron_r_reg[7]_0 [1]),\n .I3(cnt_pwron_r_reg__0[4]),\n .I4(cnt_pwron_r_reg__0[3]),\n .I5(cnt_pwron_r_reg__0[2]),\n .O(cnt_pwron_reset_done_r_reg_0));\n FDRE #(\n .INIT(1'b0)) \n cnt_pwron_reset_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\cnt_pwron_r_reg[7]_1 ),\n .Q(cnt_pwron_reset_done_r),\n .R(1'b0));\n LUT3 #(\n .INIT(8'hBA)) \n \\cnt_shift_r[3]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__22),\n .I1(rdlvl_stg1_start_r_reg),\n .I2(mpr_rdlvl_done_r_reg),\n .O(\\cnt_shift_r_reg[0] ));\n LUT5 #(\n .INIT(32'h88C88888)) \n \\cnt_shift_r[3]_i_2 \n (.I0(rdlvl_stg1_start_r_reg),\n .I1(phy_rddata_en_1),\n .I2(mpr_rdlvl_start_r_reg),\n .I3(mpr_rdlvl_done_r_reg),\n .I4(\\cnt_shift_r_reg[0]_0 ),\n .O(E));\n LUT5 #(\n .INIT(32'hFFFFFFEF)) \n cnt_txpr_done_r_i_2\n (.I0(cnt_txpr_r_reg__0[7]),\n .I1(cnt_txpr_r_reg__0[4]),\n .I2(cnt_txpr_r_reg__0[6]),\n .I3(cnt_txpr_r_reg__0[3]),\n .I4(cnt_txpr_r_reg__0[5]),\n .O(cnt_txpr_done_r_reg_0));\n FDRE #(\n .INIT(1'b0)) \n cnt_txpr_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cnt_txpr_done_r_reg_1),\n .Q(cnt_txpr_done_r),\n .R(clear));\n (* SOFT_HLUTNM = \"soft_lutpair606\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\cnt_txpr_r[0]_i_1 \n (.I0(\\cnt_txpr_r_reg[2]_0 [0]),\n .O(p_0_in__1[0]));\n (* SOFT_HLUTNM = \"soft_lutpair606\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\cnt_txpr_r[1]_i_1 \n (.I0(\\cnt_txpr_r_reg[2]_0 [1]),\n .I1(\\cnt_txpr_r_reg[2]_0 [0]),\n .O(p_0_in__1[1]));\n (* SOFT_HLUTNM = \"soft_lutpair596\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\cnt_txpr_r[2]_i_1 \n (.I0(\\cnt_txpr_r_reg[2]_0 [2]),\n .I1(\\cnt_txpr_r_reg[2]_0 [0]),\n .I2(\\cnt_txpr_r_reg[2]_0 [1]),\n .O(p_0_in__1[2]));\n (* SOFT_HLUTNM = \"soft_lutpair487\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\cnt_txpr_r[3]_i_1 \n (.I0(cnt_txpr_r_reg__0[3]),\n .I1(\\cnt_txpr_r_reg[2]_0 [1]),\n .I2(\\cnt_txpr_r_reg[2]_0 [0]),\n .I3(\\cnt_txpr_r_reg[2]_0 [2]),\n .O(p_0_in__1[3]));\n (* SOFT_HLUTNM = \"soft_lutpair487\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\cnt_txpr_r[4]_i_1 \n (.I0(cnt_txpr_r_reg__0[4]),\n .I1(\\cnt_txpr_r_reg[2]_0 [2]),\n .I2(\\cnt_txpr_r_reg[2]_0 [0]),\n .I3(\\cnt_txpr_r_reg[2]_0 [1]),\n .I4(cnt_txpr_r_reg__0[3]),\n .O(p_0_in__1[4]));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n \\cnt_txpr_r[5]_i_1 \n (.I0(cnt_txpr_r_reg__0[5]),\n .I1(cnt_txpr_r_reg__0[3]),\n .I2(\\cnt_txpr_r_reg[2]_0 [1]),\n .I3(\\cnt_txpr_r_reg[2]_0 [0]),\n .I4(\\cnt_txpr_r_reg[2]_0 [2]),\n .I5(cnt_txpr_r_reg__0[4]),\n .O(p_0_in__1[5]));\n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\cnt_txpr_r[6]_i_1 \n (.I0(cnt_txpr_r_reg__0[6]),\n .I1(cnt_txpr_r_reg__0[4]),\n .I2(\\cnt_txpr_r[7]_i_3_n_0 ),\n .I3(cnt_txpr_r_reg__0[3]),\n .I4(cnt_txpr_r_reg__0[5]),\n .O(p_0_in__1[6]));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_txpr_r[7]_i_1 \n (.I0(cnt_pwron_cke_done_r),\n .O(clear));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n \\cnt_txpr_r[7]_i_2 \n (.I0(cnt_txpr_r_reg__0[7]),\n .I1(cnt_txpr_r_reg__0[6]),\n .I2(cnt_txpr_r_reg__0[5]),\n .I3(cnt_txpr_r_reg__0[3]),\n .I4(\\cnt_txpr_r[7]_i_3_n_0 ),\n .I5(cnt_txpr_r_reg__0[4]),\n .O(p_0_in__1[7]));\n (* SOFT_HLUTNM = \"soft_lutpair596\" *) \n LUT3 #(\n .INIT(8'h80)) \n \\cnt_txpr_r[7]_i_3 \n (.I0(\\cnt_txpr_r_reg[2]_0 [2]),\n .I1(\\cnt_txpr_r_reg[2]_0 [0]),\n .I2(\\cnt_txpr_r_reg[2]_0 [1]),\n .O(\\cnt_txpr_r[7]_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_txpr_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__1[0]),\n .Q(\\cnt_txpr_r_reg[2]_0 [0]),\n .R(clear));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_txpr_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__1[1]),\n .Q(\\cnt_txpr_r_reg[2]_0 [1]),\n .R(clear));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_txpr_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__1[2]),\n .Q(\\cnt_txpr_r_reg[2]_0 [2]),\n .R(clear));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_txpr_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__1[3]),\n .Q(cnt_txpr_r_reg__0[3]),\n .R(clear));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_txpr_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__1[4]),\n .Q(cnt_txpr_r_reg__0[4]),\n .R(clear));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_txpr_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__1[5]),\n .Q(cnt_txpr_r_reg__0[5]),\n .R(clear));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_txpr_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__1[6]),\n .Q(cnt_txpr_r_reg__0[6]),\n .R(clear));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_txpr_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__1[7]),\n .Q(cnt_txpr_r_reg__0[7]),\n .R(clear));\n LUT6 #(\n .INIT(64'h0000404000034040)) \n complex_act_start_i_1\n (.I0(read_calib_reg_0),\n .I1(Q[4]),\n .I2(Q[3]),\n .I3(oclk_calib_resume_level_reg_0),\n .I4(Q[5]),\n .I5(prbs_rdlvl_start_i_2_n_0),\n .O(complex_act_start0));\n FDRE #(\n .INIT(1'b0)) \n complex_act_start_reg\n (.C(CLK),\n .CE(1'b1),\n .D(complex_act_start0),\n .Q(complex_act_start),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hFFFEFD00)) \n \\complex_address[9]_i_1 \n (.I0(init_state_r1[2]),\n .I1(init_state_r1[6]),\n .I2(\\complex_address[9]_i_2_n_0 ),\n .I3(\\complex_address[9]_i_3_n_0 ),\n .I4(\\complex_address[9]_i_4_n_0 ),\n .O(complex_address0));\n (* SOFT_HLUTNM = \"soft_lutpair510\" *) \n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\complex_address[9]_i_2 \n (.I0(init_state_r1[3]),\n .I1(init_state_r1[4]),\n .I2(init_state_r1[5]),\n .I3(init_state_r1[0]),\n .I4(init_state_r1[1]),\n .O(\\complex_address[9]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h2000000000000000)) \n \\complex_address[9]_i_3 \n (.I0(Q[4]),\n .I1(Q[5]),\n .I2(Q[3]),\n .I3(Q[2]),\n .I4(\\init_state_r_reg_n_0_[3] ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .O(\\complex_address[9]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0000200000000000)) \n \\complex_address[9]_i_4 \n (.I0(Q[4]),\n .I1(Q[5]),\n .I2(Q[3]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[2]),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .O(\\complex_address[9]_i_4_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\complex_address_reg[0] \n (.C(CLK),\n .CE(complex_address0),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),\n .Q(\\complex_address_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE #(\n .INIT(1'b0)) \n \\complex_address_reg[1] \n (.C(CLK),\n .CE(complex_address0),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),\n .Q(\\complex_address_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE #(\n .INIT(1'b0)) \n \\complex_address_reg[2] \n (.C(CLK),\n .CE(complex_address0),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),\n .Q(\\complex_address_reg_n_0_[2] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE #(\n .INIT(1'b0)) \n \\complex_address_reg[3] \n (.C(CLK),\n .CE(complex_address0),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .Q(\\complex_address_reg_n_0_[3] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE #(\n .INIT(1'b0)) \n \\complex_address_reg[4] \n (.C(CLK),\n .CE(complex_address0),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .Q(\\complex_address_reg_n_0_[4] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE #(\n .INIT(1'b0)) \n \\complex_address_reg[5] \n (.C(CLK),\n .CE(complex_address0),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),\n .Q(\\complex_address_reg_n_0_[5] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE #(\n .INIT(1'b0)) \n \\complex_address_reg[6] \n (.C(CLK),\n .CE(complex_address0),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),\n .Q(\\complex_address_reg_n_0_[6] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE #(\n .INIT(1'b0)) \n \\complex_address_reg[7] \n (.C(CLK),\n .CE(complex_address0),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),\n .Q(\\complex_address_reg_n_0_[7] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE #(\n .INIT(1'b0)) \n \\complex_address_reg[8] \n (.C(CLK),\n .CE(complex_address0),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),\n .Q(\\complex_address_reg_n_0_[8] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE #(\n .INIT(1'b0)) \n \\complex_address_reg[9] \n (.C(CLK),\n .CE(complex_address0),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),\n .Q(\\complex_address_reg_n_0_[9] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n LUT5 #(\n .INIT(32'h0000000E)) \n complex_byte_rd_done_i_1\n (.I0(complex_byte_rd_done),\n .I1(complex_byte_rd_done_i_2_n_0),\n .I2(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .I3(prbs_rdlvl_done_pulse),\n .I4(rstdiv0_sync_r1_reg_rep__24),\n .O(complex_byte_rd_done_i_1_n_0));\n LUT6 #(\n .INIT(64'h0000800000000000)) \n complex_byte_rd_done_i_2\n (.I0(complex_row1_rd_cnt[0]),\n .I1(complex_row1_rd_cnt[1]),\n .I2(complex_row1_rd_cnt[2]),\n .I3(complex_row1_rd_done),\n .I4(complex_row1_rd_done_r1),\n .I5(prbs_rdlvl_done_reg_rep),\n .O(complex_byte_rd_done_i_2_n_0));\n FDRE #(\n .INIT(1'b0)) \n complex_byte_rd_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(complex_byte_rd_done_i_1_n_0),\n .Q(complex_byte_rd_done),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h000000AE)) \n complex_mask_lim_done_i_1\n (.I0(complex_mask_lim_done),\n .I1(complex_oclkdelay_calib_start_int),\n .I2(prbs_rdlvl_done_reg),\n .I3(prbs_rdlvl_done_r3),\n .I4(rstdiv0_sync_r1_reg_rep__24),\n .O(complex_mask_lim_done_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n complex_mask_lim_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(complex_mask_lim_done_i_1_n_0),\n .Q(complex_mask_lim_done),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hFFFF26EE)) \n \\complex_num_reads[0]_i_1 \n (.I0(\\complex_num_reads_reg_n_0_[0] ),\n .I1(\\complex_num_reads[3]_i_2_n_0 ),\n .I2(\\complex_num_writes[4]_i_5_n_0 ),\n .I3(\\complex_num_reads[2]_i_4_n_0 ),\n .I4(\\complex_num_reads[3]_i_4_n_0 ),\n .O(\\complex_num_reads[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h000000000222FE22)) \n \\complex_num_reads[1]_i_1 \n (.I0(\\complex_num_reads_reg_n_0_[1] ),\n .I1(\\complex_num_reads[2]_i_2_n_0 ),\n .I2(\\complex_num_writes[2]_i_4_n_0 ),\n .I3(\\complex_num_reads[2]_i_4_n_0 ),\n .I4(\\complex_num_reads[1]_i_2_n_0 ),\n .I5(\\complex_num_reads[2]_i_5_n_0 ),\n .O(\\complex_num_reads[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair550\" *) \n LUT4 #(\n .INIT(16'hA88A)) \n \\complex_num_reads[1]_i_2 \n (.I0(\\complex_num_reads[3]_i_8_n_0 ),\n .I1(\\complex_num_writes[4]_i_5_n_0 ),\n .I2(\\complex_num_reads_reg_n_0_[1] ),\n .I3(\\complex_num_reads_reg_n_0_[0] ),\n .O(\\complex_num_reads[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00000000002E2222)) \n \\complex_num_reads[2]_i_1 \n (.I0(\\complex_num_reads_reg_n_0_[2] ),\n .I1(\\complex_num_reads[2]_i_2_n_0 ),\n .I2(\\complex_num_reads[2]_i_3_n_0 ),\n .I3(\\complex_num_writes[2]_i_4_n_0 ),\n .I4(\\complex_num_reads[2]_i_4_n_0 ),\n .I5(\\complex_num_reads[2]_i_5_n_0 ),\n .O(\\complex_num_reads[2]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hEA)) \n \\complex_num_reads[2]_i_2 \n (.I0(\\complex_num_reads[3]_i_2_n_0 ),\n .I1(\\complex_num_reads[2]_i_4_n_0 ),\n .I2(\\complex_num_reads[2]_i_6_n_0 ),\n .O(\\complex_num_reads[2]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'h802A)) \n \\complex_num_reads[2]_i_3 \n (.I0(\\complex_num_writes[2]_i_6_n_0 ),\n .I1(\\complex_num_reads_reg_n_0_[1] ),\n .I2(\\complex_num_reads_reg_n_0_[0] ),\n .I3(\\complex_num_reads_reg_n_0_[2] ),\n .O(\\complex_num_reads[2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000008000)) \n \\complex_num_reads[2]_i_4 \n (.I0(\\complex_address[9]_i_4_n_0 ),\n .I1(complex_wait_cnt_reg__0[2]),\n .I2(complex_wait_cnt_reg__0[3]),\n .I3(complex_wait_cnt_reg__0[1]),\n .I4(complex_wait_cnt_reg__0[0]),\n .I5(complex_row0_rd_done),\n .O(\\complex_num_reads[2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFEAAAAAAAAAAAAA)) \n \\complex_num_reads[2]_i_5 \n (.I0(rstdiv0_sync_r1_reg_rep__23),\n .I1(\\complex_num_reads_reg_n_0_[2] ),\n .I2(\\complex_num_reads_reg_n_0_[1] ),\n .I3(\\complex_num_reads_reg_n_0_[3] ),\n .I4(\\complex_num_writes[4]_i_7_n_0 ),\n .I5(\\complex_num_reads[2]_i_4_n_0 ),\n .O(\\complex_num_reads[2]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000200)) \n \\complex_num_reads[2]_i_6 \n (.I0(\\complex_num_writes[2]_i_7_n_0 ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[4] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[5] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[3] ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[1] ),\n .I5(\\stg1_wr_rd_cnt_reg_n_0_[2] ),\n .O(\\complex_num_reads[2]_i_6_n_0 ));\n LUT4 #(\n .INIT(16'h00E2)) \n \\complex_num_reads[3]_i_1 \n (.I0(\\complex_num_reads_reg_n_0_[3] ),\n .I1(\\complex_num_reads[3]_i_2_n_0 ),\n .I2(\\complex_num_reads[3]_i_3_n_0 ),\n .I3(\\complex_num_reads[3]_i_4_n_0 ),\n .O(\\complex_num_reads[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFEFEFE0EFEFEFEFE)) \n \\complex_num_reads[3]_i_2 \n (.I0(\\complex_num_writes[3]_i_4_n_0 ),\n .I1(stg1_wr_done),\n .I2(\\complex_num_reads[2]_i_4_n_0 ),\n .I3(\\complex_num_writes[4]_i_7_n_0 ),\n .I4(\\complex_num_reads[3]_i_5_n_0 ),\n .I5(\\complex_num_reads[3]_i_6_n_0 ),\n .O(\\complex_num_reads[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h8AA8A8A8A8A8A8A8)) \n \\complex_num_reads[3]_i_3 \n (.I0(\\complex_num_reads[2]_i_4_n_0 ),\n .I1(\\complex_num_writes[4]_i_5_n_0 ),\n .I2(\\complex_num_reads_reg_n_0_[3] ),\n .I3(\\complex_num_reads_reg_n_0_[1] ),\n .I4(\\complex_num_reads_reg_n_0_[0] ),\n .I5(\\complex_num_reads_reg_n_0_[2] ),\n .O(\\complex_num_reads[3]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFEF0F0F0FEFFF0F0)) \n \\complex_num_reads[3]_i_4 \n (.I0(\\complex_num_reads_reg_n_0_[3] ),\n .I1(\\complex_num_reads[3]_i_7_n_0 ),\n .I2(rstdiv0_sync_r1_reg_rep__23),\n .I3(\\complex_num_writes[4]_i_7_n_0 ),\n .I4(\\complex_num_reads[2]_i_4_n_0 ),\n .I5(\\complex_num_reads[3]_i_8_n_0 ),\n .O(\\complex_num_reads[3]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair493\" *) \n LUT5 #(\n .INIT(32'hAAAABBBF)) \n \\complex_num_reads[3]_i_5 \n (.I0(\\complex_num_writes[4]_i_5_n_0 ),\n .I1(\\complex_num_reads_reg_n_0_[2] ),\n .I2(\\complex_num_reads_reg_n_0_[0] ),\n .I3(\\complex_num_reads_reg_n_0_[1] ),\n .I4(\\complex_num_reads_reg_n_0_[3] ),\n .O(\\complex_num_reads[3]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'hFEAAEAAA)) \n \\complex_num_reads[3]_i_6 \n (.I0(\\complex_num_writes[4]_i_14_n_0 ),\n .I1(\\complex_num_reads_reg_n_0_[1] ),\n .I2(\\complex_num_reads_reg_n_0_[2] ),\n .I3(\\complex_num_reads_reg_n_0_[3] ),\n .I4(\\complex_num_writes[4]_i_15_n_0 ),\n .O(\\complex_num_reads[3]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair493\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\complex_num_reads[3]_i_7 \n (.I0(\\complex_num_reads_reg_n_0_[2] ),\n .I1(\\complex_num_reads_reg_n_0_[1] ),\n .O(\\complex_num_reads[3]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFDEFFFFFFFFF)) \n \\complex_num_reads[3]_i_8 \n (.I0(\\stg1_wr_rd_cnt_reg_n_0_[4] ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[5] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[3] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[2] ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[1] ),\n .I5(\\complex_num_writes[2]_i_7_n_0 ),\n .O(\\complex_num_reads[3]_i_8_n_0 ));\n LUT3 #(\n .INIT(8'h74)) \n \\complex_num_reads_dec[0]_i_2 \n (.I0(complex_num_reads_dec_reg__0[0]),\n .I1(\\complex_num_reads_dec[3]_i_3_n_0 ),\n .I2(\\complex_num_reads_reg_n_0_[0] ),\n .O(p_0_in__8[0]));\n LUT4 #(\n .INIT(16'h9F90)) \n \\complex_num_reads_dec[1]_i_1 \n (.I0(complex_num_reads_dec_reg__0[1]),\n .I1(complex_num_reads_dec_reg__0[0]),\n .I2(\\complex_num_reads_dec[3]_i_3_n_0 ),\n .I3(\\complex_num_reads_reg_n_0_[1] ),\n .O(p_0_in__8[1]));\n LUT5 #(\n .INIT(32'hA9FFA900)) \n \\complex_num_reads_dec[2]_i_1 \n (.I0(complex_num_reads_dec_reg__0[2]),\n .I1(complex_num_reads_dec_reg__0[0]),\n .I2(complex_num_reads_dec_reg__0[1]),\n .I3(\\complex_num_reads_dec[3]_i_3_n_0 ),\n .I4(\\complex_num_reads_reg_n_0_[2] ),\n .O(p_0_in__8[2]));\n LUT6 #(\n .INIT(64'hDDDDDDDDDDDDDDD5)) \n \\complex_num_reads_dec[3]_i_1 \n (.I0(\\complex_num_reads_dec[3]_i_3_n_0 ),\n .I1(\\stg1_wr_rd_cnt[8]_i_4_n_0 ),\n .I2(complex_num_reads_dec_reg__0[0]),\n .I3(complex_num_reads_dec_reg__0[1]),\n .I4(complex_num_reads_dec_reg__0[2]),\n .I5(complex_num_reads_dec_reg__0[3]),\n .O(\\complex_num_reads_dec[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAAA9FFFFAAA90000)) \n \\complex_num_reads_dec[3]_i_2 \n (.I0(complex_num_reads_dec_reg__0[3]),\n .I1(complex_num_reads_dec_reg__0[2]),\n .I2(complex_num_reads_dec_reg__0[1]),\n .I3(complex_num_reads_dec_reg__0[0]),\n .I4(\\complex_num_reads_dec[3]_i_3_n_0 ),\n .I5(\\complex_num_reads_reg_n_0_[3] ),\n .O(p_0_in__8[3]));\n LUT6 #(\n .INIT(64'h5545555555555555)) \n \\complex_num_reads_dec[3]_i_3 \n (.I0(\\complex_num_reads_dec[3]_i_4_n_0 ),\n .I1(complex_row0_rd_done),\n .I2(prbs_gen_oclk_clk_en_i_8_n_0),\n .I3(complex_oclkdelay_calib_start_int_i_2_n_0),\n .I4(\\init_state_r_reg[1]_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .O(\\complex_num_reads_dec[3]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF00400000)) \n \\complex_num_reads_dec[3]_i_4 \n (.I0(prbs_rdlvl_start_i_2_n_0),\n .I1(\\wrcal_reads[7]_i_5_n_0 ),\n .I2(Q[3]),\n .I3(Q[5]),\n .I4(Q[4]),\n .I5(stg1_wr_done),\n .O(\\complex_num_reads_dec[3]_i_4_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\complex_num_reads_dec_reg[0] \n (.C(CLK),\n .CE(\\complex_num_reads_dec[3]_i_1_n_0 ),\n .D(p_0_in__8[0]),\n .Q(complex_num_reads_dec_reg__0[0]),\n .S(rstdiv0_sync_r1_reg_rep__18));\n FDRE #(\n .INIT(1'b0)) \n \\complex_num_reads_dec_reg[1] \n (.C(CLK),\n .CE(\\complex_num_reads_dec[3]_i_1_n_0 ),\n .D(p_0_in__8[1]),\n .Q(complex_num_reads_dec_reg__0[1]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE #(\n .INIT(1'b0)) \n \\complex_num_reads_dec_reg[2] \n (.C(CLK),\n .CE(\\complex_num_reads_dec[3]_i_1_n_0 ),\n .D(p_0_in__8[2]),\n .Q(complex_num_reads_dec_reg__0[2]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE #(\n .INIT(1'b0)) \n \\complex_num_reads_dec_reg[3] \n (.C(CLK),\n .CE(\\complex_num_reads_dec[3]_i_1_n_0 ),\n .D(p_0_in__8[3]),\n .Q(complex_num_reads_dec_reg__0[3]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE #(\n .INIT(1'b0)) \n \\complex_num_reads_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\complex_num_reads[0]_i_1_n_0 ),\n .Q(\\complex_num_reads_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\complex_num_reads_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\complex_num_reads[1]_i_1_n_0 ),\n .Q(\\complex_num_reads_reg_n_0_[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\complex_num_reads_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\complex_num_reads[2]_i_1_n_0 ),\n .Q(\\complex_num_reads_reg_n_0_[2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\complex_num_reads_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\complex_num_reads[3]_i_1_n_0 ),\n .Q(\\complex_num_reads_reg_n_0_[3] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFFFFFFF22622E6E)) \n \\complex_num_writes[0]_i_1 \n (.I0(\\complex_num_writes_reg_n_0_[0] ),\n .I1(\\complex_num_writes[3]_i_2_n_0 ),\n .I2(\\complex_num_writes[4]_i_4_n_0 ),\n .I3(\\complex_num_writes[4]_i_5_n_0 ),\n .I4(\\complex_num_writes[0]_i_2_n_0 ),\n .I5(\\complex_num_writes[4]_i_6_n_0 ),\n .O(\\complex_num_writes[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000200000000000)) \n \\complex_num_writes[0]_i_2 \n (.I0(complex_row0_wr_done),\n .I1(prbs_rdlvl_start_i_2_n_0),\n .I2(\\wrcal_reads[7]_i_5_n_0 ),\n .I3(Q[3]),\n .I4(Q[5]),\n .I5(Q[4]),\n .O(\\complex_num_writes[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FEEE0222)) \n \\complex_num_writes[1]_i_1 \n (.I0(\\complex_num_writes_reg_n_0_[1] ),\n .I1(\\complex_num_writes[2]_i_2_n_0 ),\n .I2(\\complex_num_writes[4]_i_4_n_0 ),\n .I3(\\complex_num_writes[2]_i_4_n_0 ),\n .I4(\\complex_num_writes[1]_i_2_n_0 ),\n .I5(\\complex_num_writes[2]_i_5_n_0 ),\n .O(\\complex_num_writes[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hBAAABABABABABAAA)) \n \\complex_num_writes[1]_i_2 \n (.I0(\\complex_num_writes[0]_i_2_n_0 ),\n .I1(\\complex_num_writes[4]_i_5_n_0 ),\n .I2(\\complex_num_writes[4]_i_4_n_0 ),\n .I3(\\complex_num_writes[4]_i_11_n_0 ),\n .I4(\\complex_num_writes_reg_n_0_[0] ),\n .I5(\\complex_num_writes_reg_n_0_[1] ),\n .O(\\complex_num_writes[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000E2E2E2)) \n \\complex_num_writes[2]_i_1 \n (.I0(\\complex_num_writes_reg_n_0_[2] ),\n .I1(\\complex_num_writes[2]_i_2_n_0 ),\n .I2(\\complex_num_writes[2]_i_3_n_0 ),\n .I3(\\complex_num_writes[4]_i_4_n_0 ),\n .I4(\\complex_num_writes[2]_i_4_n_0 ),\n .I5(\\complex_num_writes[2]_i_5_n_0 ),\n .O(\\complex_num_writes[2]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hBA)) \n \\complex_num_writes[2]_i_2 \n (.I0(\\complex_num_writes[4]_i_2_n_0 ),\n .I1(\\complex_num_writes[2]_i_6_n_0 ),\n .I2(\\complex_num_writes[4]_i_4_n_0 ),\n .O(\\complex_num_writes[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF7FD5FFFF0000)) \n \\complex_num_writes[2]_i_3 \n (.I0(\\complex_num_writes[2]_i_6_n_0 ),\n .I1(\\complex_num_writes_reg_n_0_[1] ),\n .I2(\\complex_num_writes_reg_n_0_[0] ),\n .I3(\\complex_num_writes_reg_n_0_[2] ),\n .I4(\\complex_num_writes[0]_i_2_n_0 ),\n .I5(\\complex_num_writes[4]_i_4_n_0 ),\n .O(\\complex_num_writes[2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0000002000000000)) \n \\complex_num_writes[2]_i_4 \n (.I0(\\complex_num_writes[2]_i_7_n_0 ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[1] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[2] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[3] ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[5] ),\n .I5(\\stg1_wr_rd_cnt_reg_n_0_[4] ),\n .O(\\complex_num_writes[2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFEEEAAAAAAAAAAAA)) \n \\complex_num_writes[2]_i_5 \n (.I0(complex_row0_rd_done1),\n .I1(\\complex_num_writes[2]_i_8_n_0 ),\n .I2(\\complex_num_writes_reg_n_0_[2] ),\n .I3(\\complex_num_writes_reg_n_0_[1] ),\n .I4(\\complex_num_writes[4]_i_7_n_0 ),\n .I5(\\complex_num_writes[4]_i_4_n_0 ),\n .O(\\complex_num_writes[2]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair550\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\complex_num_writes[2]_i_6 \n (.I0(\\complex_num_reads[2]_i_6_n_0 ),\n .I1(\\complex_num_writes[4]_i_5_n_0 ),\n .O(\\complex_num_writes[2]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair558\" *) \n LUT4 #(\n .INIT(16'h1000)) \n \\complex_num_writes[2]_i_7 \n (.I0(\\stg1_wr_rd_cnt_reg_n_0_[8] ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[7] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[0] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[6] ),\n .O(\\complex_num_writes[2]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\complex_num_writes[2]_i_8 \n (.I0(\\complex_num_writes_reg_n_0_[4] ),\n .I1(\\complex_num_writes_reg_n_0_[3] ),\n .O(\\complex_num_writes[2]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'h00000000EEE2E2E2)) \n \\complex_num_writes[3]_i_1 \n (.I0(\\complex_num_writes_reg_n_0_[3] ),\n .I1(\\complex_num_writes[3]_i_2_n_0 ),\n .I2(\\complex_num_writes[3]_i_3_n_0 ),\n .I3(complex_row0_wr_done),\n .I4(\\complex_num_writes[3]_i_4_n_0 ),\n .I5(\\complex_num_writes[4]_i_6_n_0 ),\n .O(\\complex_num_writes[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair570\" *) \n LUT3 #(\n .INIT(8'hF8)) \n \\complex_num_writes[3]_i_2 \n (.I0(\\complex_num_writes[4]_i_5_n_0 ),\n .I1(\\complex_num_writes[4]_i_4_n_0 ),\n .I2(\\complex_num_writes[4]_i_2_n_0 ),\n .O(\\complex_num_writes[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h8AA8A8A8A8A8A8A8)) \n \\complex_num_writes[3]_i_3 \n (.I0(\\complex_num_writes[4]_i_4_n_0 ),\n .I1(\\complex_num_writes[4]_i_5_n_0 ),\n .I2(\\complex_num_writes_reg_n_0_[3] ),\n .I3(\\complex_num_writes_reg_n_0_[1] ),\n .I4(\\complex_num_writes_reg_n_0_[0] ),\n .I5(\\complex_num_writes_reg_n_0_[2] ),\n .O(\\complex_num_writes[3]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000002000)) \n \\complex_num_writes[3]_i_4 \n (.I0(Q[4]),\n .I1(Q[5]),\n .I2(Q[3]),\n .I3(Q[2]),\n .I4(\\init_state_r_reg_n_0_[3] ),\n .I5(prbs_rdlvl_start_i_2_n_0),\n .O(\\complex_num_writes[3]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000E2E2E2)) \n \\complex_num_writes[4]_i_1 \n (.I0(\\complex_num_writes_reg_n_0_[4] ),\n .I1(\\complex_num_writes[4]_i_2_n_0 ),\n .I2(\\complex_num_writes[4]_i_3_n_0 ),\n .I3(\\complex_num_writes[4]_i_4_n_0 ),\n .I4(\\complex_num_writes[4]_i_5_n_0 ),\n .I5(\\complex_num_writes[4]_i_6_n_0 ),\n .O(\\complex_num_writes[4]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair575\" *) \n LUT3 #(\n .INIT(8'h80)) \n \\complex_num_writes[4]_i_10 \n (.I0(\\complex_num_writes_reg_n_0_[2] ),\n .I1(\\complex_num_writes_reg_n_0_[0] ),\n .I2(\\complex_num_writes_reg_n_0_[1] ),\n .O(\\complex_num_writes[4]_i_10_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair570\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\complex_num_writes[4]_i_11 \n (.I0(\\complex_num_reads[3]_i_8_n_0 ),\n .I1(\\complex_num_writes[4]_i_4_n_0 ),\n .I2(\\complex_num_writes[4]_i_7_n_0 ),\n .O(\\complex_num_writes[4]_i_11_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair603\" *) \n LUT2 #(\n .INIT(4'h7)) \n \\complex_num_writes[4]_i_12 \n (.I0(\\stg1_wr_rd_cnt_reg_n_0_[1] ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[2] ),\n .O(\\complex_num_writes[4]_i_12_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\complex_num_writes[4]_i_13 \n (.I0(\\stg1_wr_rd_cnt_reg_n_0_[8] ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[7] ),\n .O(\\complex_num_writes[4]_i_13_n_0 ));\n LUT6 #(\n .INIT(64'hEEEEEEECEEECEEEC)) \n \\complex_num_writes[4]_i_14 \n (.I0(\\stg1_wr_rd_cnt_reg_n_0_[6] ),\n .I1(\\complex_num_writes[4]_i_13_n_0 ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[4] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[5] ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[3] ),\n .I5(\\stg1_wr_rd_cnt[4]_i_3_n_0 ),\n .O(\\complex_num_writes[4]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'hFFFEFFFEFFFEFEFE)) \n \\complex_num_writes[4]_i_15 \n (.I0(\\stg1_wr_rd_cnt_reg_n_0_[8] ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[7] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[6] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[5] ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[4] ),\n .I5(\\stg1_wr_rd_cnt_reg_n_0_[3] ),\n .O(\\complex_num_writes[4]_i_15_n_0 ));\n LUT5 #(\n .INIT(32'hEEE2EEEE)) \n \\complex_num_writes[4]_i_2 \n (.I0(\\complex_num_writes[3]_i_4_n_0 ),\n .I1(\\complex_num_writes[4]_i_4_n_0 ),\n .I2(\\complex_num_writes[4]_i_7_n_0 ),\n .I3(\\complex_num_writes[4]_i_8_n_0 ),\n .I4(\\complex_num_writes[4]_i_9_n_0 ),\n .O(\\complex_num_writes[4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFF6A6A6AFF000000)) \n \\complex_num_writes[4]_i_3 \n (.I0(\\complex_num_writes_reg_n_0_[4] ),\n .I1(\\complex_num_writes_reg_n_0_[3] ),\n .I2(\\complex_num_writes[4]_i_10_n_0 ),\n .I3(complex_row0_wr_done),\n .I4(\\complex_num_writes[3]_i_4_n_0 ),\n .I5(\\complex_num_writes[4]_i_4_n_0 ),\n .O(\\complex_num_writes[4]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000008000)) \n \\complex_num_writes[4]_i_4 \n (.I0(\\complex_address[9]_i_3_n_0 ),\n .I1(complex_wait_cnt_reg__0[2]),\n .I2(complex_wait_cnt_reg__0[3]),\n .I3(complex_wait_cnt_reg__0[1]),\n .I4(complex_wait_cnt_reg__0[0]),\n .I5(complex_row0_wr_done),\n .O(\\complex_num_writes[4]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair486\" *) \n LUT5 #(\n .INIT(32'h40000000)) \n \\complex_num_writes[4]_i_5 \n (.I0(wr_victim_inc_i_3_n_0),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[0] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[5] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[1] ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[2] ),\n .O(\\complex_num_writes[4]_i_5_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\complex_num_writes[4]_i_6 \n (.I0(\\complex_num_writes[2]_i_5_n_0 ),\n .I1(\\complex_num_writes[4]_i_11_n_0 ),\n .O(\\complex_num_writes[4]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF008A00)) \n \\complex_num_writes[4]_i_7 \n (.I0(\\stg1_wr_rd_cnt_reg_n_0_[4] ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[3] ),\n .I2(\\complex_num_writes[4]_i_12_n_0 ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[6] ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[5] ),\n .I5(\\complex_num_writes[4]_i_13_n_0 ),\n .O(\\complex_num_writes[4]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h000000000000222A)) \n \\complex_num_writes[4]_i_8 \n (.I0(\\complex_num_writes[4]_i_14_n_0 ),\n .I1(\\complex_num_writes_reg_n_0_[2] ),\n .I2(\\complex_num_writes_reg_n_0_[0] ),\n .I3(\\complex_num_writes_reg_n_0_[1] ),\n .I4(\\complex_num_writes_reg_n_0_[4] ),\n .I5(\\complex_num_writes_reg_n_0_[3] ),\n .O(\\complex_num_writes[4]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFE080)) \n \\complex_num_writes[4]_i_9 \n (.I0(\\complex_num_writes_reg_n_0_[1] ),\n .I1(\\complex_num_writes_reg_n_0_[2] ),\n .I2(\\complex_num_writes_reg_n_0_[3] ),\n .I3(\\complex_num_writes[4]_i_15_n_0 ),\n .I4(\\complex_num_writes[4]_i_14_n_0 ),\n .I5(\\complex_num_writes_reg_n_0_[4] ),\n .O(\\complex_num_writes[4]_i_9_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair575\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\complex_num_writes_dec[0]_i_1 \n (.I0(complex_num_writes_dec_reg__0[0]),\n .I1(\\complex_num_writes_dec[4]_i_4_n_0 ),\n .I2(\\complex_num_writes_reg_n_0_[0] ),\n .O(p_0_in__7[0]));\n LUT4 #(\n .INIT(16'h9F90)) \n \\complex_num_writes_dec[1]_i_1 \n (.I0(complex_num_writes_dec_reg__0[0]),\n .I1(complex_num_writes_dec_reg__0[1]),\n .I2(\\complex_num_writes_dec[4]_i_4_n_0 ),\n .I3(\\complex_num_writes_reg_n_0_[1] ),\n .O(p_0_in__7[1]));\n (* SOFT_HLUTNM = \"soft_lutpair488\" *) \n LUT5 #(\n .INIT(32'hA9FFA900)) \n \\complex_num_writes_dec[2]_i_1 \n (.I0(complex_num_writes_dec_reg__0[2]),\n .I1(complex_num_writes_dec_reg__0[1]),\n .I2(complex_num_writes_dec_reg__0[0]),\n .I3(\\complex_num_writes_dec[4]_i_4_n_0 ),\n .I4(\\complex_num_writes_reg_n_0_[2] ),\n .O(p_0_in__7[2]));\n LUT6 #(\n .INIT(64'hAAA9FFFFAAA90000)) \n \\complex_num_writes_dec[3]_i_1 \n (.I0(complex_num_writes_dec_reg__0[3]),\n .I1(complex_num_writes_dec_reg__0[2]),\n .I2(complex_num_writes_dec_reg__0[0]),\n .I3(complex_num_writes_dec_reg__0[1]),\n .I4(\\complex_num_writes_dec[4]_i_4_n_0 ),\n .I5(\\complex_num_writes_reg_n_0_[3] ),\n .O(p_0_in__7[3]));\n LUT2 #(\n .INIT(4'hE)) \n \\complex_num_writes_dec[4]_i_1 \n (.I0(prbs_rdlvl_done_pulse),\n .I1(rstdiv0_sync_r1_reg_rep__23),\n .O(complex_row0_rd_done1));\n LUT5 #(\n .INIT(32'hDDDDDDD5)) \n \\complex_num_writes_dec[4]_i_2 \n (.I0(\\complex_num_writes_dec[4]_i_4_n_0 ),\n .I1(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .I2(complex_num_writes_dec_reg__0[1]),\n .I3(complex_num_writes_dec_reg__0[0]),\n .I4(\\complex_num_writes_dec[4]_i_5_n_0 ),\n .O(\\complex_num_writes_dec[4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hAA9AFFFFAA9A0000)) \n \\complex_num_writes_dec[4]_i_3 \n (.I0(complex_num_writes_dec_reg__0[4]),\n .I1(complex_num_writes_dec_reg__0[3]),\n .I2(\\complex_num_writes_dec[4]_i_6_n_0 ),\n .I3(complex_num_writes_dec_reg__0[2]),\n .I4(\\complex_num_writes_dec[4]_i_4_n_0 ),\n .I5(\\complex_num_writes_reg_n_0_[4] ),\n .O(p_0_in__7[4]));\n LUT5 #(\n .INIT(32'h10111111)) \n \\complex_num_writes_dec[4]_i_4 \n (.I0(stg1_wr_done),\n .I1(\\complex_num_writes[3]_i_4_n_0 ),\n .I2(complex_row0_rd_done),\n .I3(prbs_gen_oclk_clk_en_i_8_n_0),\n .I4(\\complex_address[9]_i_3_n_0 ),\n .O(\\complex_num_writes_dec[4]_i_4_n_0 ));\n LUT3 #(\n .INIT(8'hFE)) \n \\complex_num_writes_dec[4]_i_5 \n (.I0(complex_num_writes_dec_reg__0[3]),\n .I1(complex_num_writes_dec_reg__0[2]),\n .I2(complex_num_writes_dec_reg__0[4]),\n .O(\\complex_num_writes_dec[4]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair488\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\complex_num_writes_dec[4]_i_6 \n (.I0(complex_num_writes_dec_reg__0[0]),\n .I1(complex_num_writes_dec_reg__0[1]),\n .O(\\complex_num_writes_dec[4]_i_6_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\complex_num_writes_dec_reg[0] \n (.C(CLK),\n .CE(\\complex_num_writes_dec[4]_i_2_n_0 ),\n .D(p_0_in__7[0]),\n .Q(complex_num_writes_dec_reg__0[0]),\n .S(complex_row0_rd_done1));\n FDRE #(\n .INIT(1'b0)) \n \\complex_num_writes_dec_reg[1] \n (.C(CLK),\n .CE(\\complex_num_writes_dec[4]_i_2_n_0 ),\n .D(p_0_in__7[1]),\n .Q(complex_num_writes_dec_reg__0[1]),\n .R(complex_row0_rd_done1));\n FDRE #(\n .INIT(1'b0)) \n \\complex_num_writes_dec_reg[2] \n (.C(CLK),\n .CE(\\complex_num_writes_dec[4]_i_2_n_0 ),\n .D(p_0_in__7[2]),\n .Q(complex_num_writes_dec_reg__0[2]),\n .R(complex_row0_rd_done1));\n FDRE #(\n .INIT(1'b0)) \n \\complex_num_writes_dec_reg[3] \n (.C(CLK),\n .CE(\\complex_num_writes_dec[4]_i_2_n_0 ),\n .D(p_0_in__7[3]),\n .Q(complex_num_writes_dec_reg__0[3]),\n .R(complex_row0_rd_done1));\n FDRE #(\n .INIT(1'b0)) \n \\complex_num_writes_dec_reg[4] \n (.C(CLK),\n .CE(\\complex_num_writes_dec[4]_i_2_n_0 ),\n .D(p_0_in__7[4]),\n .Q(complex_num_writes_dec_reg__0[4]),\n .R(complex_row0_rd_done1));\n FDRE #(\n .INIT(1'b0)) \n \\complex_num_writes_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\complex_num_writes[0]_i_1_n_0 ),\n .Q(\\complex_num_writes_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\complex_num_writes_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\complex_num_writes[1]_i_1_n_0 ),\n .Q(\\complex_num_writes_reg_n_0_[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\complex_num_writes_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\complex_num_writes[2]_i_1_n_0 ),\n .Q(\\complex_num_writes_reg_n_0_[2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\complex_num_writes_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\complex_num_writes[3]_i_1_n_0 ),\n .Q(\\complex_num_writes_reg_n_0_[3] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\complex_num_writes_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\complex_num_writes[4]_i_1_n_0 ),\n .Q(\\complex_num_writes_reg_n_0_[4] ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h0000AABA)) \n complex_ocal_odt_ext_i_1\n (.I0(complex_ocal_odt_ext),\n .I1(complex_ocal_odt_ext_i_2_n_0),\n .I2(Q[5]),\n .I3(Q[1]),\n .I4(complex_ocal_odt_ext_i_3_n_0),\n .O(complex_ocal_odt_ext_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair538\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n complex_ocal_odt_ext_i_2\n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(Q[2]),\n .I2(Q[3]),\n .I3(Q[4]),\n .O(complex_ocal_odt_ext_i_2_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFF400040F0)) \n complex_ocal_odt_ext_i_3\n (.I0(\\back_to_back_reads_4_1.num_reads_reg[0]_0 ),\n .I1(cnt_cmd_done_m7_r),\n .I2(Q[1]),\n .I3(Q[0]),\n .I4(complex_ocal_odt_ext_i_4_n_0),\n .I5(rstdiv0_sync_r1_reg_rep__23),\n .O(complex_ocal_odt_ext_i_3_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair518\" *) \n LUT5 #(\n .INIT(32'hFFEFFFFF)) \n complex_ocal_odt_ext_i_4\n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(Q[2]),\n .I2(Q[3]),\n .I3(Q[5]),\n .I4(Q[4]),\n .O(complex_ocal_odt_ext_i_4_n_0));\n FDRE #(\n .INIT(1'b0)) \n complex_ocal_odt_ext_reg\n (.C(CLK),\n .CE(1'b1),\n .D(complex_ocal_odt_ext_i_1_n_0),\n .Q(complex_ocal_odt_ext),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h44444F4444444444)) \n complex_ocal_reset_rd_addr_i_1\n (.I0(prbs_last_byte_done_r),\n .I1(prbs_last_byte_done),\n .I2(complex_ocal_reset_rd_addr_i_2_n_0),\n .I3(complex_wait_cnt_reg__0[3]),\n .I4(complex_wait_cnt_reg__0[2]),\n .I5(complex_ocal_reset_rd_addr_i_3_n_0),\n .O(complex_ocal_reset_rd_addr0));\n (* SOFT_HLUTNM = \"soft_lutpair602\" *) \n LUT2 #(\n .INIT(4'hB)) \n complex_ocal_reset_rd_addr_i_2\n (.I0(complex_wait_cnt_reg__0[1]),\n .I1(complex_wait_cnt_reg__0[0]),\n .O(complex_ocal_reset_rd_addr_i_2_n_0));\n LUT6 #(\n .INIT(64'h0000000000000020)) \n complex_ocal_reset_rd_addr_i_3\n (.I0(Q[4]),\n .I1(Q[5]),\n .I2(Q[3]),\n .I3(\\init_state_r[4]_i_5_n_0 ),\n .I4(Q[1]),\n .I5(Q[0]),\n .O(complex_ocal_reset_rd_addr_i_3_n_0));\n FDRE #(\n .INIT(1'b0)) \n complex_ocal_reset_rd_addr_reg\n (.C(CLK),\n .CE(1'b1),\n .D(complex_ocal_reset_rd_addr0),\n .Q(complex_ocal_reset_rd_addr),\n .R(1'b0));\n LUT2 #(\n .INIT(4'hE)) \n complex_ocal_wr_start_i_1\n (.I0(complex_ocal_reset_rd_addr),\n .I1(complex_ocal_wr_start),\n .O(complex_ocal_wr_start_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n complex_ocal_wr_start_reg\n (.C(CLK),\n .CE(1'b1),\n .D(complex_ocal_wr_start_i_1_n_0),\n .Q(complex_ocal_wr_start),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE #(\n .INIT(1'b0)) \n complex_oclkdelay_calib_done_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prbs_rdlvl_done_reg_rep),\n .Q(complex_oclkdelay_calib_done_r1),\n .R(rstdiv0_sync_r1_reg_rep__11));\n LUT6 #(\n .INIT(64'hFFFFFFFF00040000)) \n complex_oclkdelay_calib_start_int_i_1\n (.I0(complex_oclkdelay_calib_start_int_i_2_n_0),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .I2(Q[2]),\n .I3(complex_oclkdelay_calib_start_int_reg_0),\n .I4(prbs_last_byte_done_r),\n .I5(complex_oclkdelay_calib_start_int),\n .O(complex_oclkdelay_calib_start_int_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair569\" *) \n LUT3 #(\n .INIT(8'hDF)) \n complex_oclkdelay_calib_start_int_i_2\n (.I0(Q[4]),\n .I1(Q[5]),\n .I2(Q[3]),\n .O(complex_oclkdelay_calib_start_int_i_2_n_0));\n LUT2 #(\n .INIT(4'hB)) \n complex_oclkdelay_calib_start_int_i_3\n (.I0(Q[0]),\n .I1(Q[1]),\n .O(complex_oclkdelay_calib_start_int_reg_0));\n FDRE #(\n .INIT(1'b0)) \n complex_oclkdelay_calib_start_int_reg\n (.C(CLK),\n .CE(1'b1),\n .D(complex_oclkdelay_calib_start_int_i_1_n_0),\n .Q(complex_oclkdelay_calib_start_int),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE #(\n .INIT(1'b0)) \n complex_oclkdelay_calib_start_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(complex_oclkdelay_calib_start_int),\n .Q(complex_oclkdelay_calib_start_r1),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n complex_oclkdelay_calib_start_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(complex_oclkdelay_calib_start_r1),\n .Q(complex_oclkdelay_calib_start_r2),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h000000000000AAEA)) \n complex_odt_ext_i_1\n (.I0(complex_odt_ext),\n .I1(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .I2(rdlvl_stg1_done_r1),\n .I3(complex_sample_cnt_inc_i_2_n_0),\n .I4(complex_row1_rd_done_i_2_n_0),\n .I5(rstdiv0_sync_r1_reg_rep__23),\n .O(complex_odt_ext_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n complex_odt_ext_reg\n (.C(CLK),\n .CE(1'b1),\n .D(complex_odt_ext_i_1_n_0),\n .Q(complex_odt_ext),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair557\" *) \n LUT4 #(\n .INIT(16'h0002)) \n complex_row0_rd_done_i_1\n (.I0(complex_row0_rd_done_i_2_n_0),\n .I1(prbs_rdlvl_done_pulse),\n .I2(rstdiv0_sync_r1_reg_rep__24),\n .I3(complex_sample_cnt_inc),\n .O(complex_row0_rd_done_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFF0000E000)) \n complex_row0_rd_done_i_2\n (.I0(prbs_rdlvl_start_r_reg),\n .I1(complex_oclkdelay_calib_start_int),\n .I2(complex_row1_wr_done),\n .I3(complex_row0_wr_done),\n .I4(wr_victim_inc_i_2_n_0),\n .I5(complex_row0_rd_done),\n .O(complex_row0_rd_done_i_2_n_0));\n FDRE #(\n .INIT(1'b0)) \n complex_row0_rd_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(complex_row0_rd_done_i_1_n_0),\n .Q(complex_row0_rd_done),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h0000009A)) \n \\complex_row1_rd_cnt[0]_i_1 \n (.I0(complex_row1_rd_cnt[0]),\n .I1(complex_row1_rd_done_r1),\n .I2(complex_row1_rd_done),\n .I3(rstdiv0_sync_r1_reg_rep__24),\n .I4(prbs_rdlvl_done_pulse),\n .O(\\complex_row1_rd_cnt[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000009AAA)) \n \\complex_row1_rd_cnt[1]_i_1 \n (.I0(complex_row1_rd_cnt[1]),\n .I1(complex_row1_rd_done_r1),\n .I2(complex_row1_rd_done),\n .I3(complex_row1_rd_cnt[0]),\n .I4(rstdiv0_sync_r1_reg_rep__24),\n .I5(prbs_rdlvl_done_pulse),\n .O(\\complex_row1_rd_cnt[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h000000009AAAAAAA)) \n \\complex_row1_rd_cnt[2]_i_1 \n (.I0(complex_row1_rd_cnt[2]),\n .I1(complex_row1_rd_done_r1),\n .I2(complex_row1_rd_done),\n .I3(complex_row1_rd_cnt[0]),\n .I4(complex_row1_rd_cnt[1]),\n .I5(complex_row0_rd_done1),\n .O(\\complex_row1_rd_cnt[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\complex_row1_rd_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\complex_row1_rd_cnt[0]_i_1_n_0 ),\n .Q(complex_row1_rd_cnt[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\complex_row1_rd_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\complex_row1_rd_cnt[1]_i_1_n_0 ),\n .Q(complex_row1_rd_cnt[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\complex_row1_rd_cnt_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\complex_row1_rd_cnt[2]_i_1_n_0 ),\n .Q(complex_row1_rd_cnt[2]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000000000AE)) \n complex_row1_rd_done_i_1\n (.I0(complex_row1_rd_done),\n .I1(complex_row0_rd_done),\n .I2(wr_victim_inc_i_2_n_0),\n .I3(complex_row1_rd_done_i_2_n_0),\n .I4(prbs_rdlvl_done_pulse),\n .I5(rstdiv0_sync_r1_reg_rep__24),\n .O(complex_row1_rd_done_i_1_n_0));\n LUT6 #(\n .INIT(64'h0000000000100000)) \n complex_row1_rd_done_i_2\n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(Q[2]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[3]),\n .I5(Q[5]),\n .O(complex_row1_rd_done_i_2_n_0));\n FDRE #(\n .INIT(1'b0)) \n complex_row1_rd_done_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(complex_row1_rd_done),\n .Q(complex_row1_rd_done_r1),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n complex_row1_rd_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(complex_row1_rd_done_i_1_n_0),\n .Q(complex_row1_rd_done),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair609\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\complex_row_cnt_ocal[0]_i_1 \n (.I0(complex_row_cnt_ocal_reg__0[0]),\n .O(p_0_in__5[0]));\n (* SOFT_HLUTNM = \"soft_lutpair609\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\complex_row_cnt_ocal[1]_i_1 \n (.I0(complex_row_cnt_ocal_reg__0[1]),\n .I1(complex_row_cnt_ocal_reg__0[0]),\n .O(p_0_in__5[1]));\n (* SOFT_HLUTNM = \"soft_lutpair560\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\complex_row_cnt_ocal[2]_i_1 \n (.I0(complex_row_cnt_ocal_reg__0[2]),\n .I1(complex_row_cnt_ocal_reg__0[0]),\n .I2(complex_row_cnt_ocal_reg__0[1]),\n .O(p_0_in__5[2]));\n (* SOFT_HLUTNM = \"soft_lutpair560\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\complex_row_cnt_ocal[3]_i_1 \n (.I0(complex_row_cnt_ocal_reg__0[3]),\n .I1(complex_row_cnt_ocal_reg__0[1]),\n .I2(complex_row_cnt_ocal_reg__0[0]),\n .I3(complex_row_cnt_ocal_reg__0[2]),\n .O(p_0_in__5[3]));\n (* SOFT_HLUTNM = \"soft_lutpair480\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\complex_row_cnt_ocal[4]_i_1 \n (.I0(complex_row_cnt_ocal_reg__0[4]),\n .I1(complex_row_cnt_ocal_reg__0[3]),\n .I2(complex_row_cnt_ocal_reg__0[2]),\n .I3(complex_row_cnt_ocal_reg__0[0]),\n .I4(complex_row_cnt_ocal_reg__0[1]),\n .O(p_0_in__5[4]));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n \\complex_row_cnt_ocal[5]_i_1 \n (.I0(complex_row_cnt_ocal_reg__0[5]),\n .I1(complex_row_cnt_ocal_reg__0[1]),\n .I2(complex_row_cnt_ocal_reg__0[0]),\n .I3(complex_row_cnt_ocal_reg__0[2]),\n .I4(complex_row_cnt_ocal_reg__0[3]),\n .I5(complex_row_cnt_ocal_reg__0[4]),\n .O(p_0_in__5[5]));\n (* SOFT_HLUTNM = \"soft_lutpair509\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\complex_row_cnt_ocal[6]_i_1 \n (.I0(complex_row_cnt_ocal_reg__0[6]),\n .I1(complex_row_cnt_ocal_reg__0[4]),\n .I2(\\complex_row_cnt_ocal[7]_i_8_n_0 ),\n .I3(complex_row_cnt_ocal_reg__0[5]),\n .O(p_0_in__5[6]));\n LUT5 #(\n .INIT(32'hFFFFFFFB)) \n \\complex_row_cnt_ocal[7]_i_1 \n (.I0(\\complex_row_cnt_ocal_reg[0]_0 ),\n .I1(rdlvl_stg1_done_r1),\n .I2(complex_byte_rd_done),\n .I3(rstdiv0_sync_r1_reg_rep__23),\n .I4(prbs_rdlvl_done_pulse),\n .O(complex_row_cnt_ocal0));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAA0800)) \n \\complex_row_cnt_ocal[7]_i_2 \n (.I0(\\complex_row_cnt_ocal[7]_i_5_n_0 ),\n .I1(\\complex_row_cnt_ocal[7]_i_6_n_0 ),\n .I2(\\complex_row_cnt_ocal[7]_i_7_n_0 ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[3] ),\n .I4(wr_victim_inc),\n .I5(complex_sample_cnt_inc_r2),\n .O(complex_row_cnt_ocal));\n (* SOFT_HLUTNM = \"soft_lutpair509\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\complex_row_cnt_ocal[7]_i_3 \n (.I0(complex_row_cnt_ocal_reg__0[7]),\n .I1(complex_row_cnt_ocal_reg__0[5]),\n .I2(\\complex_row_cnt_ocal[7]_i_8_n_0 ),\n .I3(complex_row_cnt_ocal_reg__0[4]),\n .I4(complex_row_cnt_ocal_reg__0[6]),\n .O(p_0_in__5[7]));\n LUT6 #(\n .INIT(64'h0000000000000008)) \n \\complex_row_cnt_ocal[7]_i_4 \n (.I0(\\complex_row_cnt_ocal[7]_i_8_n_0 ),\n .I1(wr_victim_inc),\n .I2(complex_row_cnt_ocal_reg__0[4]),\n .I3(complex_row_cnt_ocal_reg__0[7]),\n .I4(complex_row_cnt_ocal_reg__0[5]),\n .I5(complex_row_cnt_ocal_reg__0[6]),\n .O(\\complex_row_cnt_ocal_reg[0]_0 ));\n LUT6 #(\n .INIT(64'h0000000000000004)) \n \\complex_row_cnt_ocal[7]_i_5 \n (.I0(\\complex_row_cnt_ocal[7]_i_8_n_0 ),\n .I1(prbs_rdlvl_done_reg_rep),\n .I2(complex_row_cnt_ocal_reg__0[4]),\n .I3(complex_row_cnt_ocal_reg__0[7]),\n .I4(complex_row_cnt_ocal_reg__0[5]),\n .I5(complex_row_cnt_ocal_reg__0[6]),\n .O(\\complex_row_cnt_ocal[7]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000002000)) \n \\complex_row_cnt_ocal[7]_i_6 \n (.I0(Q[4]),\n .I1(Q[5]),\n .I2(Q[3]),\n .I3(\\wrcal_reads[7]_i_5_n_0 ),\n .I4(Q[1]),\n .I5(Q[0]),\n .O(\\complex_row_cnt_ocal[7]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFBFFFFFFFFFF)) \n \\complex_row_cnt_ocal[7]_i_7 \n (.I0(\\complex_row_cnt_ocal[7]_i_9_n_0 ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[4] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[5] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[2] ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[0] ),\n .I5(\\stg1_wr_rd_cnt_reg_n_0_[1] ),\n .O(\\complex_row_cnt_ocal[7]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair480\" *) \n LUT4 #(\n .INIT(16'h8000)) \n \\complex_row_cnt_ocal[7]_i_8 \n (.I0(complex_row_cnt_ocal_reg__0[1]),\n .I1(complex_row_cnt_ocal_reg__0[0]),\n .I2(complex_row_cnt_ocal_reg__0[2]),\n .I3(complex_row_cnt_ocal_reg__0[3]),\n .O(\\complex_row_cnt_ocal[7]_i_8_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair514\" *) \n LUT3 #(\n .INIT(8'hFE)) \n \\complex_row_cnt_ocal[7]_i_9 \n (.I0(\\stg1_wr_rd_cnt_reg_n_0_[6] ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[7] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[8] ),\n .O(\\complex_row_cnt_ocal[7]_i_9_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\complex_row_cnt_ocal_reg[0] \n (.C(CLK),\n .CE(complex_row_cnt_ocal),\n .D(p_0_in__5[0]),\n .Q(complex_row_cnt_ocal_reg__0[0]),\n .R(complex_row_cnt_ocal0));\n FDRE #(\n .INIT(1'b0)) \n \\complex_row_cnt_ocal_reg[1] \n (.C(CLK),\n .CE(complex_row_cnt_ocal),\n .D(p_0_in__5[1]),\n .Q(complex_row_cnt_ocal_reg__0[1]),\n .R(complex_row_cnt_ocal0));\n FDRE #(\n .INIT(1'b0)) \n \\complex_row_cnt_ocal_reg[2] \n (.C(CLK),\n .CE(complex_row_cnt_ocal),\n .D(p_0_in__5[2]),\n .Q(complex_row_cnt_ocal_reg__0[2]),\n .R(complex_row_cnt_ocal0));\n FDRE #(\n .INIT(1'b0)) \n \\complex_row_cnt_ocal_reg[3] \n (.C(CLK),\n .CE(complex_row_cnt_ocal),\n .D(p_0_in__5[3]),\n .Q(complex_row_cnt_ocal_reg__0[3]),\n .R(complex_row_cnt_ocal0));\n FDRE #(\n .INIT(1'b0)) \n \\complex_row_cnt_ocal_reg[4] \n (.C(CLK),\n .CE(complex_row_cnt_ocal),\n .D(p_0_in__5[4]),\n .Q(complex_row_cnt_ocal_reg__0[4]),\n .R(complex_row_cnt_ocal0));\n FDRE #(\n .INIT(1'b0)) \n \\complex_row_cnt_ocal_reg[5] \n (.C(CLK),\n .CE(complex_row_cnt_ocal),\n .D(p_0_in__5[5]),\n .Q(complex_row_cnt_ocal_reg__0[5]),\n .R(complex_row_cnt_ocal0));\n FDRE #(\n .INIT(1'b0)) \n \\complex_row_cnt_ocal_reg[6] \n (.C(CLK),\n .CE(complex_row_cnt_ocal),\n .D(p_0_in__5[6]),\n .Q(complex_row_cnt_ocal_reg__0[6]),\n .R(complex_row_cnt_ocal0));\n FDRE #(\n .INIT(1'b0)) \n \\complex_row_cnt_ocal_reg[7] \n (.C(CLK),\n .CE(complex_row_cnt_ocal),\n .D(p_0_in__5[7]),\n .Q(complex_row_cnt_ocal_reg__0[7]),\n .R(complex_row_cnt_ocal0));\n LUT2 #(\n .INIT(4'h2)) \n complex_sample_cnt_inc_i_1\n (.I0(complex_row1_rd_done),\n .I1(complex_sample_cnt_inc_i_2_n_0),\n .O(complex_sample_cnt_inc0));\n (* SOFT_HLUTNM = \"soft_lutpair486\" *) \n LUT5 #(\n .INIT(32'hFFFFFFEF)) \n complex_sample_cnt_inc_i_2\n (.I0(wr_victim_inc_i_3_n_0),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[5] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[0] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[1] ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[2] ),\n .O(complex_sample_cnt_inc_i_2_n_0));\n FDRE #(\n .INIT(1'b0)) \n complex_sample_cnt_inc_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(complex_sample_cnt_inc),\n .Q(complex_sample_cnt_inc_r1),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n complex_sample_cnt_inc_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(complex_sample_cnt_inc_r1),\n .Q(complex_sample_cnt_inc_r2),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n complex_sample_cnt_inc_reg\n (.C(CLK),\n .CE(1'b1),\n .D(complex_sample_cnt_inc0),\n .Q(complex_sample_cnt_inc),\n .R(rstdiv0_sync_r1_reg_rep__11));\n LUT1 #(\n .INIT(2'h1)) \n \\complex_wait_cnt[0]_i_1 \n (.I0(complex_wait_cnt_reg__0[0]),\n .O(p_0_in__6[0]));\n (* SOFT_HLUTNM = \"soft_lutpair602\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\complex_wait_cnt[1]_i_1 \n (.I0(complex_wait_cnt_reg__0[1]),\n .I1(complex_wait_cnt_reg__0[0]),\n .O(p_0_in__6[1]));\n (* SOFT_HLUTNM = \"soft_lutpair554\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\complex_wait_cnt[2]_i_1 \n (.I0(complex_wait_cnt_reg__0[1]),\n .I1(complex_wait_cnt_reg__0[0]),\n .I2(complex_wait_cnt_reg__0[2]),\n .O(p_0_in__6[2]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFBABEFBF)) \n \\complex_wait_cnt[3]_i_1 \n (.I0(complex_oclkdelay_calib_start_int_i_2_n_0),\n .I1(Q[2]),\n .I2(\\init_state_r_reg_n_0_[3] ),\n .I3(Q[1]),\n .I4(Q[0]),\n .I5(\\complex_wait_cnt[3]_i_3_n_0 ),\n .O(\\complex_wait_cnt[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair554\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\complex_wait_cnt[3]_i_2 \n (.I0(complex_wait_cnt_reg__0[3]),\n .I1(complex_wait_cnt_reg__0[1]),\n .I2(complex_wait_cnt_reg__0[0]),\n .I3(complex_wait_cnt_reg__0[2]),\n .O(p_0_in__6[3]));\n (* SOFT_HLUTNM = \"soft_lutpair502\" *) \n LUT5 #(\n .INIT(32'hEAAAAAAA)) \n \\complex_wait_cnt[3]_i_3 \n (.I0(rstdiv0_sync_r1_reg_rep__23),\n .I1(complex_wait_cnt_reg__0[3]),\n .I2(complex_wait_cnt_reg__0[2]),\n .I3(complex_wait_cnt_reg__0[1]),\n .I4(complex_wait_cnt_reg__0[0]),\n .O(\\complex_wait_cnt[3]_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\complex_wait_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__6[0]),\n .Q(complex_wait_cnt_reg__0[0]),\n .R(\\complex_wait_cnt[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\complex_wait_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__6[1]),\n .Q(complex_wait_cnt_reg__0[1]),\n .R(\\complex_wait_cnt[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\complex_wait_cnt_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__6[2]),\n .Q(complex_wait_cnt_reg__0[2]),\n .R(\\complex_wait_cnt[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\complex_wait_cnt_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__6[3]),\n .Q(complex_wait_cnt_reg__0[3]),\n .R(\\complex_wait_cnt[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair585\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\data_offset_1_i1[0]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_1_reg[0] ),\n .I1(init_calib_complete_reg_rep__14),\n .I2(calib_data_offset_1[0]),\n .O(\\data_offset_1_i1_reg[5] [0]));\n (* SOFT_HLUTNM = \"soft_lutpair586\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\data_offset_1_i1[1]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_1_reg[1] ),\n .I1(init_calib_complete_reg_rep__14),\n .I2(calib_data_offset_1[1]),\n .O(\\data_offset_1_i1_reg[5] [1]));\n (* SOFT_HLUTNM = \"soft_lutpair587\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\data_offset_1_i1[2]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_1_reg[2] ),\n .I1(init_calib_complete_reg_rep__14),\n .I2(calib_data_offset_1[2]),\n .O(\\data_offset_1_i1_reg[5] [2]));\n (* SOFT_HLUTNM = \"soft_lutpair588\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\data_offset_1_i1[3]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_1_reg[3] ),\n .I1(init_calib_complete_reg_rep__14),\n .I2(calib_data_offset_1[3]),\n .O(\\data_offset_1_i1_reg[5] [3]));\n (* SOFT_HLUTNM = \"soft_lutpair587\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\data_offset_1_i1[4]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_1_reg[4] ),\n .I1(init_calib_complete_reg_rep__14),\n .I2(calib_data_offset_1[4]),\n .O(\\data_offset_1_i1_reg[5] [4]));\n (* SOFT_HLUTNM = \"soft_lutpair586\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\data_offset_1_i1[5]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_1_reg[5] ),\n .I1(init_calib_complete_reg_rep__14),\n .I2(calib_data_offset_1[5]),\n .O(\\data_offset_1_i1_reg[5] [5]));\n (* SOFT_HLUTNM = \"soft_lutpair536\" *) \n LUT4 #(\n .INIT(16'h8000)) \n ddr2_pre_flag_r_i_2\n (.I0(ddr2_refresh_flag_r_reg_0),\n .I1(cnt_cmd_done_r),\n .I2(ddr2_refresh_flag_r),\n .I3(cnt_init_mr_done_r),\n .O(ddr2_pre_flag_r_reg_1));\n FDRE #(\n .INIT(1'b0)) \n ddr2_pre_flag_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(ddr2_pre_flag_r_reg_2),\n .Q(ddr2_pre_flag_r_reg_0),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0000010000000000)) \n ddr2_refresh_flag_r_i_2\n (.I0(oclk_calib_resume_level_reg_0),\n .I1(Q[5]),\n .I2(Q[4]),\n .I3(Q[0]),\n .I4(Q[3]),\n .I5(Q[1]),\n .O(ddr2_refresh_flag_r_reg_0));\n FDRE #(\n .INIT(1'b0)) \n ddr2_refresh_flag_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cnt_cmd_done_r_reg_0),\n .Q(ddr2_refresh_flag_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFFFFFFF00000200)) \n ddr3_lm_done_r_i_1\n (.I0(wrcal_done_reg_10),\n .I1(oclk_calib_resume_level_reg_0),\n .I2(\\init_state_r[5]_i_2_n_0 ),\n .I3(Q[0]),\n .I4(ddr3_lm_done_r_i_2_n_0),\n .I5(ddr3_lm_done_r),\n .O(ddr3_lm_done_r_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair495\" *) \n LUT2 #(\n .INIT(4'hB)) \n ddr3_lm_done_r_i_2\n (.I0(Q[3]),\n .I1(Q[1]),\n .O(ddr3_lm_done_r_i_2_n_0));\n FDRE #(\n .INIT(1'b0)) \n ddr3_lm_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(ddr3_lm_done_r_i_1_n_0),\n .Q(ddr3_lm_done_r),\n .R(rstdiv0_sync_r1_reg_rep__12));\n LUT6 #(\n .INIT(64'h0000000000000080)) \n detect_pi_found_dqs_i_1\n (.I0(\\cnt_cmd_r_reg_n_0_[5] ),\n .I1(\\cnt_cmd_r[6]_i_5_n_0 ),\n .I2(Q[1]),\n .I3(Q[0]),\n .I4(\\back_to_back_reads_4_1.num_reads_reg[0]_0 ),\n .I5(\\cnt_cmd_r_reg_n_0_[6] ),\n .O(detect_pi_found_dqs0));\n FDRE #(\n .INIT(1'b0)) \n detect_pi_found_dqs_reg\n (.C(CLK),\n .CE(1'b1),\n .D(detect_pi_found_dqs0),\n .Q(detect_pi_found_dqs),\n .R(rstdiv0_sync_r1_reg_rep__11));\n LUT6 #(\n .INIT(64'h00000000DADA00DA)) \n \\dqs_asrt_cnt[0]_i_1 \n (.I0(dqs_asrt_cnt[0]),\n .I1(dqs_asrt_cnt[1]),\n .I2(wr_level_dqs_asrt),\n .I3(wrlvl_done_r),\n .I4(wrlvl_done_r1),\n .I5(rstdiv0_sync_r1_reg_rep__23),\n .O(\\dqs_asrt_cnt[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00000000ECEC00EC)) \n \\dqs_asrt_cnt[1]_i_1 \n (.I0(dqs_asrt_cnt[0]),\n .I1(dqs_asrt_cnt[1]),\n .I2(wr_level_dqs_asrt),\n .I3(wrlvl_done_r),\n .I4(wrlvl_done_r1),\n .I5(rstdiv0_sync_r1_reg_rep__23),\n .O(\\dqs_asrt_cnt[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\dqs_asrt_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dqs_asrt_cnt[0]_i_1_n_0 ),\n .Q(dqs_asrt_cnt[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dqs_asrt_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dqs_asrt_cnt[1]_i_1_n_0 ),\n .Q(dqs_asrt_cnt[1]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h000000000F0F0F0E)) \n \\en_cnt_div4.enable_wrlvl_cnt[0]_i_1 \n (.I0(enable_wrlvl_cnt[3]),\n .I1(enable_wrlvl_cnt[4]),\n .I2(enable_wrlvl_cnt[0]),\n .I3(enable_wrlvl_cnt[1]),\n .I4(enable_wrlvl_cnt[2]),\n .I5(rstdiv0_sync_r1_reg_rep__23_0),\n .O(\\en_cnt_div4.enable_wrlvl_cnt[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00000000F00FF00E)) \n \\en_cnt_div4.enable_wrlvl_cnt[1]_i_1 \n (.I0(enable_wrlvl_cnt[3]),\n .I1(enable_wrlvl_cnt[4]),\n .I2(enable_wrlvl_cnt[0]),\n .I3(enable_wrlvl_cnt[1]),\n .I4(enable_wrlvl_cnt[2]),\n .I5(rstdiv0_sync_r1_reg_rep__23_0),\n .O(\\en_cnt_div4.enable_wrlvl_cnt[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFF0000E)) \n \\en_cnt_div4.enable_wrlvl_cnt[2]_i_1 \n (.I0(enable_wrlvl_cnt[3]),\n .I1(enable_wrlvl_cnt[4]),\n .I2(enable_wrlvl_cnt[0]),\n .I3(enable_wrlvl_cnt[1]),\n .I4(enable_wrlvl_cnt[2]),\n .I5(\\en_cnt_div4.enable_wrlvl_cnt_reg[3]_0 ),\n .O(\\en_cnt_div4.enable_wrlvl_cnt[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFAAAAAAA4)) \n \\en_cnt_div4.enable_wrlvl_cnt[3]_i_2 \n (.I0(enable_wrlvl_cnt[3]),\n .I1(enable_wrlvl_cnt[4]),\n .I2(enable_wrlvl_cnt[0]),\n .I3(enable_wrlvl_cnt[1]),\n .I4(enable_wrlvl_cnt[2]),\n .I5(\\en_cnt_div4.enable_wrlvl_cnt_reg[3]_0 ),\n .O(\\en_cnt_div4.enable_wrlvl_cnt[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h444444444444444F)) \n \\en_cnt_div4.enable_wrlvl_cnt[3]_i_3 \n (.I0(enable_wrlvl_cnt0),\n .I1(wrlvl_odt),\n .I2(read_calib_reg_0),\n .I3(Q[3]),\n .I4(Q[4]),\n .I5(Q[5]),\n .O(\\en_cnt_div4.enable_wrlvl_cnt_reg[3]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair516\" *) \n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n \\en_cnt_div4.enable_wrlvl_cnt[3]_i_4 \n (.I0(enable_wrlvl_cnt[2]),\n .I1(enable_wrlvl_cnt[1]),\n .I2(enable_wrlvl_cnt[0]),\n .I3(enable_wrlvl_cnt[4]),\n .I4(enable_wrlvl_cnt[3]),\n .O(enable_wrlvl_cnt0));\n LUT6 #(\n .INIT(64'h00000000CCCCCCC8)) \n \\en_cnt_div4.enable_wrlvl_cnt[4]_i_1 \n (.I0(enable_wrlvl_cnt[3]),\n .I1(enable_wrlvl_cnt[4]),\n .I2(enable_wrlvl_cnt[0]),\n .I3(enable_wrlvl_cnt[1]),\n .I4(enable_wrlvl_cnt[2]),\n .I5(rstdiv0_sync_r1_reg_rep__23_0),\n .O(\\en_cnt_div4.enable_wrlvl_cnt[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\en_cnt_div4.enable_wrlvl_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\en_cnt_div4.enable_wrlvl_cnt[0]_i_1_n_0 ),\n .Q(enable_wrlvl_cnt[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\en_cnt_div4.enable_wrlvl_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\en_cnt_div4.enable_wrlvl_cnt[1]_i_1_n_0 ),\n .Q(enable_wrlvl_cnt[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\en_cnt_div4.enable_wrlvl_cnt_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\en_cnt_div4.enable_wrlvl_cnt[2]_i_1_n_0 ),\n .Q(enable_wrlvl_cnt[2]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE #(\n .INIT(1'b0)) \n \\en_cnt_div4.enable_wrlvl_cnt_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\en_cnt_div4.enable_wrlvl_cnt[3]_i_2_n_0 ),\n .Q(enable_wrlvl_cnt[3]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE #(\n .INIT(1'b0)) \n \\en_cnt_div4.enable_wrlvl_cnt_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\en_cnt_div4.enable_wrlvl_cnt[4]_i_1_n_0 ),\n .Q(enable_wrlvl_cnt[4]),\n .R(1'b0));\n LUT4 #(\n .INIT(16'h000E)) \n \\en_cnt_div4.wrlvl_odt_i_1 \n (.I0(wrlvl_odt),\n .I1(\\en_cnt_div4.wrlvl_odt_i_2_n_0 ),\n .I2(wrlvl_odt_ctl),\n .I3(rstdiv0_sync_r1_reg_rep__24),\n .O(\\en_cnt_div4.wrlvl_odt_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair516\" *) \n LUT5 #(\n .INIT(32'h00000010)) \n \\en_cnt_div4.wrlvl_odt_i_2 \n (.I0(enable_wrlvl_cnt[4]),\n .I1(enable_wrlvl_cnt[3]),\n .I2(enable_wrlvl_cnt[0]),\n .I3(enable_wrlvl_cnt[2]),\n .I4(enable_wrlvl_cnt[1]),\n .O(\\en_cnt_div4.wrlvl_odt_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\en_cnt_div4.wrlvl_odt_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\en_cnt_div4.wrlvl_odt_i_1_n_0 ),\n .Q(wrlvl_odt),\n .R(1'b0));\n LUT4 #(\n .INIT(16'hFFF4)) \n first_rdlvl_pat_r_i_1\n (.I0(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .I1(first_rdlvl_pat_r),\n .I2(rdlvl_stg1_rank_done),\n .I3(rstdiv0_sync_r1_reg_rep__23),\n .O(first_rdlvl_pat_r_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n first_rdlvl_pat_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(first_rdlvl_pat_r_i_1_n_0),\n .Q(first_rdlvl_pat_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFEFEFEFEFEFCFEFF)) \n first_wrcal_pat_r_i_1\n (.I0(first_wrcal_pat_r),\n .I1(rstdiv0_sync_r1_reg_rep__23),\n .I2(wrcal_resume_w),\n .I3(Q[1]),\n .I4(Q[0]),\n .I5(first_wrcal_pat_r_i_2_n_0),\n .O(first_wrcal_pat_r_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair491\" *) \n LUT5 #(\n .INIT(32'hFFFFFEFF)) \n first_wrcal_pat_r_i_2\n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(Q[2]),\n .I2(Q[5]),\n .I3(Q[4]),\n .I4(Q[3]),\n .O(first_wrcal_pat_r_i_2_n_0));\n FDRE #(\n .INIT(1'b0)) \n first_wrcal_pat_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(first_wrcal_pat_r_i_1_n_0),\n .Q(first_wrcal_pat_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0404550404040404)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_1 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3_n_0 ),\n .I3(reg_ctrl_cnt_r),\n .I4(reg_ctrl_cnt_r_reg__0[3]),\n .I5(reg_ctrl_cnt_r_reg__0[0]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF4F44FFFF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ),\n .I3(\\complex_address_reg_n_0_[0] ),\n .I4(prbs_rdlvl_done_reg),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h5515FFFF55155515)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3 \n (.I0(Q[5]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_5_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_6_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h000000000000005D)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .I1(complex_row_cnt_ocal_reg__0[0]),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ),\n .I3(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_7_n_0 ),\n .I5(\\stg1_wr_rd_cnt[8]_i_4_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFF888)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_5 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0 ),\n .I2(\\complex_address_reg_n_0_[0] ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ),\n .I4(prbs_rdlvl_done_reg),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFD0D0D0FF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_6 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_6_n_0 ));\n LUT2 #(\n .INIT(4'h1)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_7 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair580\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_1 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_1_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0010009000000010)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2 \n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(\\wrcal_reads[7]_i_5_n_0 ),\n .I3(Q[5]),\n .I4(Q[4]),\n .I5(Q[3]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000554000000000)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_1 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ),\n .I1(cnt_init_mr_r[0]),\n .I2(cnt_init_mr_r[1]),\n .I3(dqs_found_done_r_reg_0),\n .I4(Q[5]),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_4_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFDFFFD7DFFEFF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2 \n (.I0(Q[0]),\n .I1(Q[3]),\n .I2(Q[4]),\n .I3(Q[1]),\n .I4(\\init_state_r_reg_n_0_[3] ),\n .I5(Q[2]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair519\" *) \n LUT5 #(\n .INIT(32'h00000010)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_4 \n (.I0(Q[2]),\n .I1(Q[4]),\n .I2(Q[1]),\n .I3(Q[3]),\n .I4(Q[0]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h0004010000000000)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1 \n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(Q[2]),\n .I2(Q[5]),\n .I3(Q[3]),\n .I4(Q[4]),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2 \n (.I0(Q[0]),\n .I1(Q[1]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFFF80)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_1 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFEAEAEAFFFFFFFF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2 \n (.I0(prbs_rdlvl_done_reg),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ),\n .I2(\\complex_address_reg_n_0_[1] ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF4F44FFFF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ),\n .I3(\\complex_address_reg_n_0_[1] ),\n .I4(prbs_rdlvl_done_reg),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair540\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4 \n (.I0(reg_ctrl_cnt_r),\n .I1(reg_ctrl_cnt_r_reg__0[1]),\n .I2(reg_ctrl_cnt_r_reg__0[3]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFD0D0D0FF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h000000000000005D)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .I1(complex_row_cnt_ocal_reg__0[1]),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_7_n_0 ),\n .I4(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .I5(\\stg1_wr_rd_cnt[8]_i_4_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6_n_0 ));\n LUT2 #(\n .INIT(4'h1)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_7 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h010101FF01010101)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_1 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2_n_0 ),\n .I1(Q[5]),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h1)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_10 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'h5FF55FF50F3F0F30)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2 \n (.I0(\\gen_rnk[0].mr1_r_reg[0]_196 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000022202220222)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7_n_0 ),\n .I1(prbs_rdlvl_done_reg),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ),\n .I3(\\complex_address_reg_n_0_[2] ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF4F44FFFF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ),\n .I3(\\complex_address_reg_n_0_[2] ),\n .I4(prbs_rdlvl_done_reg),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_9_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFF8080808080)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5 \n (.I0(dqs_found_done_r_reg),\n .I1(rdlvl_stg1_done_int_reg),\n .I2(prbs_rdlvl_done_reg_rep),\n .I3(cnt_init_mr_r[0]),\n .I4(\\gen_rnk[0].mr1_r_reg[0]_196 ),\n .I5(cnt_init_mr_r[1]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair583\" *) \n LUT3 #(\n .INIT(8'hEF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6 \n (.I0(reg_ctrl_cnt_r_reg__0[3]),\n .I1(reg_ctrl_cnt_r_reg__0[1]),\n .I2(reg_ctrl_cnt_r_reg__0[2]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFD0D0D0FF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'h000000000000005D)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_9 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .I1(complex_row_cnt_ocal_reg__0[2]),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ),\n .I3(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .I4(\\stg1_wr_rd_cnt[8]_i_4_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_10_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'h000000000000AAAB)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_1 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0 ),\n .I2(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_4_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_5_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h0047FFFF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ),\n .I2(\\complex_address_reg_n_0_[3] ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ),\n .I4(prbs_rdlvl_done_reg),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h00000000D000D0D0)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_4 \n (.I0(complex_row_cnt_ocal_reg__0[3]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_7_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_8_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h00000000AAA222A2)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_5 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_9_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ),\n .I4(\\complex_address_reg_n_0_[3] ),\n .I5(prbs_rdlvl_done_reg),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FFEFFFFF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6 \n (.I0(oclk_calib_resume_level_reg_0),\n .I1(Q[5]),\n .I2(Q[4]),\n .I3(Q[3]),\n .I4(Q[0]),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_7 \n (.I0(\\stg1_wr_rd_cnt[8]_i_4_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_8 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1_n_0 ),\n .I1(burst_addr_r_reg_0),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF4044)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_9 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_8_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ),\n .I3(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hABABABABABAAABAB)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_1 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_1_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3_n_0 ),\n .I4(prbs_rdlvl_done_reg),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FEEEFEFE)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_5_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ),\n .I4(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_6_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FBFB00F3)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_7_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_8_n_0 ),\n .I5(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0014551455140014)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ),\n .I1(\\complex_address_reg_n_0_[4] ),\n .I2(\\complex_address_reg_n_0_[3] ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4_n_0 ));\n LUT3 #(\n .INIT(8'h82)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_5 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hBEFFBEAAAAAAAAAA)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_6 \n (.I0(prbs_rdlvl_done_reg),\n .I1(\\complex_address_reg_n_0_[3] ),\n .I2(\\complex_address_reg_n_0_[4] ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_8_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_6_n_0 ));\n LUT3 #(\n .INIT(8'h02)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_7 \n (.I0(complex_row_cnt_ocal_reg__0[4]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ),\n .I2(\\stg1_wr_rd_cnt[8]_i_4_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair551\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_8 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_8_n_0 ));\n LUT5 #(\n .INIT(32'h00000100)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9 \n (.I0(init_state_r1[5]),\n .I1(init_state_r1[4]),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0 ),\n .I3(init_state_r1[3]),\n .I4(init_state_r1[0]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'h0004000400045555)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_1 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFEEEF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10 \n (.I0(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .I1(\\stg1_wr_rd_cnt[8]_i_4_n_0 ),\n .I2(read_calib_reg_0),\n .I3(read_calib_i_2_n_0),\n .I4(\\calib_cmd[2]_i_8_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair499\" *) \n LUT4 #(\n .INIT(16'h802A)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_11 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ));\n LUT6 #(\n .INIT(64'hBEFFBEAAAAAAAAAA)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_13 \n (.I0(prbs_rdlvl_done_reg),\n .I1(\\complex_address_reg_n_0_[5] ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_13_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF4500FFFF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2 \n (.I0(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8_n_0 ),\n .I4(prbs_rdlvl_done_reg),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_9_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FEEEFEFE)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_11_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ),\n .I4(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_13_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair543\" *) \n LUT4 #(\n .INIT(16'h00BF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ),\n .I3(Q[5]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4_n_0 ));\n LUT2 #(\n .INIT(4'hB)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5 \n (.I0(Q[5]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_4_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FFFFEAAA)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6 \n (.I0(cnt_init_mr_r[1]),\n .I1(prbs_rdlvl_done_reg),\n .I2(rdlvl_stg1_done_int_reg),\n .I3(dqs_found_done_r_reg),\n .I4(cnt_init_mr_r[0]),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6_n_0 ));\n LUT3 #(\n .INIT(8'h6A)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hFF020202FFFFFFFF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8 \n (.I0(complex_row_cnt_ocal_reg__0[5]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ),\n .I2(\\stg1_wr_rd_cnt[8]_i_4_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'h5555154000001540)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_9 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ),\n .I1(\\complex_address_reg_n_0_[4] ),\n .I2(\\complex_address_reg_n_0_[3] ),\n .I3(\\complex_address_reg_n_0_[5] ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_9_n_0 ));\n LUT5 #(\n .INIT(32'h888F8888)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_1 \n (.I0(\\gen_rnk[0].mr1_r_reg[0]_196 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair499\" *) \n LUT5 #(\n .INIT(32'h80002AAA)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF10FF10FF10FF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_11 \n (.I0(\\stg1_wr_rd_cnt[8]_i_4_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ),\n .I2(complex_row_cnt_ocal_reg__0[6]),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'h7447474747474747)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_12 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ),\n .I2(\\complex_address_reg_n_0_[6] ),\n .I3(\\complex_address_reg_n_0_[5] ),\n .I4(\\complex_address_reg_n_0_[4] ),\n .I5(\\complex_address_reg_n_0_[3] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_12_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair580\" *) \n LUT3 #(\n .INIT(8'h01)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),\n .I1(Q[5]),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00000000AA2A222A)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9_n_0 ),\n .I5(prbs_rdlvl_done_reg),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair582\" *) \n LUT3 #(\n .INIT(8'h4F)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4 \n (.I0(Q[5]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h10FF10FF10FFFFFF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5 \n (.I0(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_11_n_0 ),\n .I3(prbs_rdlvl_done_reg),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_12_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h5555FFFFFFEF5555)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ),\n .I1(dqs_found_done_r_reg_0),\n .I2(cnt_init_mr_r[1]),\n .I3(cnt_init_mr_r[0]),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFD0D0FFD0)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair520\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair525\" *) \n LUT4 #(\n .INIT(16'h9555)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9 \n (.I0(\\complex_address_reg_n_0_[6] ),\n .I1(\\complex_address_reg_n_0_[5] ),\n .I2(\\complex_address_reg_n_0_[4] ),\n .I3(\\complex_address_reg_n_0_[3] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hAA20AAAAAA20AA20)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_1 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ),\n .I1(Q[5]),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5_n_0 ),\n .I5(prbs_rdlvl_done_reg),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair525\" *) \n LUT5 #(\n .INIT(32'h95555555)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10 \n (.I0(\\complex_address_reg_n_0_[7] ),\n .I1(\\complex_address_reg_n_0_[6] ),\n .I2(\\complex_address_reg_n_0_[3] ),\n .I3(\\complex_address_reg_n_0_[4] ),\n .I4(\\complex_address_reg_n_0_[5] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFD0D0FFD0)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF00100000)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12 \n (.I0(oclk_calib_resume_level_reg_0),\n .I1(Q[5]),\n .I2(Q[4]),\n .I3(Q[3]),\n .I4(Q[0]),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ));\n LUT4 #(\n .INIT(16'hFBAA)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_13 \n (.I0(\\stg1_wr_rd_cnt[8]_i_4_n_0 ),\n .I1(complex_row_cnt_ocal_reg__0[7]),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_13_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14 \n (.I0(\\stg1_wr_rd_cnt[8]_i_4_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ));\n LUT4 #(\n .INIT(16'h5101)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_15 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_15_n_0 ));\n LUT6 #(\n .INIT(64'h5554555555555555)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_16 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18_n_0 ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[0] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[1] ),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[2] ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_18_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_16_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair510\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_17 \n (.I0(init_state_r1[0]),\n .I1(init_state_r1[3]),\n .I2(init_state_r1[4]),\n .I3(init_state_r1[5]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000001)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_18 \n (.I0(\\stg1_wr_rd_cnt_reg_n_0_[5] ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[6] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[7] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[8] ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[4] ),\n .I5(\\stg1_wr_rd_cnt_reg_n_0_[3] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_18_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair543\" *) \n LUT4 #(\n .INIT(16'h5540)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ),\n .I3(Q[5]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0020000000000070)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3 \n (.I0(Q[2]),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .I2(Q[1]),\n .I3(Q[3]),\n .I4(Q[0]),\n .I5(Q[4]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0040444055555555)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4 \n (.I0(prbs_rdlvl_done_reg),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h00000000BBBAFFBA)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5 \n (.I0(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_13_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_15_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF6EEF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6 \n (.I0(Q[0]),\n .I1(Q[3]),\n .I2(Q[1]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[4]),\n .I5(Q[2]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hFF54000000000000)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7 \n (.I0(complex_row0_rd_done),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ),\n .I2(\\one_rank.stg1_wr_done_reg_0 ),\n .I3(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_10_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_16_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair520\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair498\" *) \n LUT5 #(\n .INIT(32'hAAA8AAAA)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9 \n (.I0(\\stg1_wr_rd_cnt[8]_i_4_n_0 ),\n .I1(init_state_r1[1]),\n .I2(init_state_r1[2]),\n .I3(init_state_r1[6]),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_17_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF111F0000)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_1 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ),\n .I4(prbs_rdlvl_done_reg),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h800000007FFFFFFF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h9555555555555555)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3 \n (.I0(\\complex_address_reg_n_0_[8] ),\n .I1(\\complex_address_reg_n_0_[7] ),\n .I2(\\complex_address_reg_n_0_[5] ),\n .I3(\\complex_address_reg_n_0_[4] ),\n .I4(\\complex_address_reg_n_0_[3] ),\n .I5(\\complex_address_reg_n_0_[6] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAABAAA)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0 ),\n .I2(cnt_init_mr_r[0]),\n .I3(cnt_init_mr_r[1]),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ),\n .I5(dqs_found_done_r_reg_0),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h0404040455045555)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5 \n (.I0(prbs_rdlvl_done_reg),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF1F110000)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_1 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0 ),\n .I4(prbs_rdlvl_done_reg),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair498\" *) \n LUT3 #(\n .INIT(8'hDF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10 \n (.I0(init_state_r1[2]),\n .I1(init_state_r1[6]),\n .I2(init_state_r1[1]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'hB)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0 ),\n .I1(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12 \n (.I0(\\complex_address_reg_n_0_[4] ),\n .I1(\\complex_address_reg_n_0_[3] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'hBBBBBBBBBBBBBBFB)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15 \n (.I0(first_wrcal_pat_r_i_2_n_0),\n .I1(Q[0]),\n .I2(wrcal_wr_cnt_reg__0[2]),\n .I3(wrcal_wr_cnt_reg__0[1]),\n .I4(wrcal_wr_cnt_reg__0[0]),\n .I5(wrcal_wr_cnt_reg__0[3]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF04000000)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16 \n (.I0(oclk_calib_resume_level_reg_0),\n .I1(Q[3]),\n .I2(Q[5]),\n .I3(Q[4]),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .I5(\\calib_cmd[2]_i_4_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAAEEEFAAAA)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18_n_0 ),\n .I1(complex_row0_rd_done),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ),\n .I3(\\one_rank.stg1_wr_done_reg_0 ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[3] ),\n .I5(\\complex_row_cnt_ocal[7]_i_7_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'h2000000000000000)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19_n_0 ),\n .I1(\\complex_num_writes[4]_i_12_n_0 ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[3] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[4] ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[6] ),\n .I5(\\stg1_wr_rd_cnt_reg_n_0_[5] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair558\" *) \n LUT3 #(\n .INIT(8'h02)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19 \n (.I0(\\stg1_wr_rd_cnt_reg_n_0_[0] ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[7] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[8] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair555\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF00010000)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0 ),\n .I1(init_state_r1[5]),\n .I2(init_state_r1[4]),\n .I3(init_state_r1[0]),\n .I4(init_state_r1[3]),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5 \n (.I0(\\complex_address_reg_n_0_[9] ),\n .I1(\\complex_address_reg_n_0_[8] ),\n .I2(\\complex_address_reg_n_0_[6] ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0 ),\n .I4(\\complex_address_reg_n_0_[5] ),\n .I5(\\complex_address_reg_n_0_[7] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAAFFABABAB)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_1_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0 ),\n .I5(prbs_rdlvl_done_reg),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0 ));\n LUT4 #(\n .INIT(16'h00FD)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7 \n (.I0(init_state_r1[3]),\n .I1(wrlvl_odt_ctl_i_3_n_0),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h00000300AAAAAAAA)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0 ),\n .I1(oclk_wr_cnt_reg__0[3]),\n .I2(oclk_wr_cnt_reg__0[1]),\n .I3(oclk_wr_cnt_reg__0[2]),\n .I4(oclk_wr_cnt_reg__0[0]),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'h7FFFFFFFFFFFFFFF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_1_n_0 ),\n .Q(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_1_n_0 ),\n .Q(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_1_n_0 ),\n .Q(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1_n_0 ),\n .Q(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_1_n_0 ),\n .Q(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_1_n_0 ),\n .Q(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_1_n_0 ),\n .Q(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_1_n_0 ),\n .Q(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_1_n_0 ),\n .Q(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_1_n_0 ),\n .Q(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_1_n_0 ),\n .Q(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_1_n_0 ),\n .Q(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_1_n_0 ),\n .Q(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h888888888888888A)) \n \\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_1 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_4_n_0 ),\n .I3(Q[4]),\n .I4(Q[3]),\n .I5(Q[0]),\n .O(bank_w[0]));\n LUT6 #(\n .INIT(64'h0D0F0F0F0F0F040F)) \n \\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2 \n (.I0(Q[3]),\n .I1(Q[4]),\n .I2(Q[5]),\n .I3(\\wrcal_reads[7]_i_5_n_0 ),\n .I4(Q[1]),\n .I5(Q[0]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h2000000028000000)) \n \\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_5_n_0 ),\n .I1(Q[2]),\n .I2(\\init_state_r_reg_n_0_[3] ),\n .I3(Q[1]),\n .I4(Q[0]),\n .I5(Q[3]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF00FFFF00F9FF)) \n \\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_4 \n (.I0(cnt_init_mr_r[0]),\n .I1(cnt_init_mr_r[1]),\n .I2(dqs_found_done_r_reg_0),\n .I3(Q[1]),\n .I4(\\init_state_r_reg_n_0_[3] ),\n .I5(Q[2]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h3030303034303030)) \n \\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_5 \n (.I0(reg_ctrl_cnt_r_reg__0[0]),\n .I1(Q[3]),\n .I2(Q[4]),\n .I3(reg_ctrl_cnt_r_reg__0[2]),\n .I4(reg_ctrl_cnt_r_reg__0[1]),\n .I5(reg_ctrl_cnt_r_reg__0[3]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair495\" *) \n LUT5 #(\n .INIT(32'h00010000)) \n \\gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_1 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),\n .I1(Q[5]),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2_n_0 ),\n .I3(Q[3]),\n .I4(Q[1]),\n .O(bank_w[1]));\n LUT6 #(\n .INIT(64'hAA55FFFFFFFFFF54)) \n \\gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2 \n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(dqs_found_done_r_reg_0),\n .I2(cnt_init_mr_r[1]),\n .I3(Q[2]),\n .I4(Q[4]),\n .I5(Q[0]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair540\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_1 \n (.I0(reg_ctrl_cnt_r_reg__0[3]),\n .I1(reg_ctrl_cnt_r_reg__0[1]),\n .I2(reg_ctrl_cnt_r),\n .I3(reg_ctrl_cnt_r_reg__0[2]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(bank_w[0]),\n .Q(phy_bank[9]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_no_mirror.div_clk_loop[0].phy_bank_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(bank_w[1]),\n .Q(phy_bank[10]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_1_n_0 ),\n .Q(phy_bank[11]),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair593\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\gen_reset_obuf.u_reset_obuf_i_1 \n (.I0(init_calib_complete_reg_rep__14),\n .I1(phy_reset_n),\n .O(mux_reset_n));\n FDRE #(\n .INIT(1'b0)) \n \\gen_rnk[0].mr1_r_reg[0][1] \n (.C(CLK),\n .CE(1'b1),\n .D(1'b1),\n .Q(\\gen_rnk[0].mr1_r_reg[0]_196 ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE #(\n .INIT(1'b0)) \n init_calib_complete_reg\n (.C(CLK),\n .CE(1'b1),\n .D(init_complete_r2),\n .Q(calib_complete),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE #(\n .INIT(1'b0)) \n init_complete_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(init_complete_r1_reg_0),\n .Q(init_complete_r1),\n .R(rstdiv0_sync_r1_reg_rep__11));\n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n init_complete_r1_timing_reg\n (.C(CLK),\n .CE(1'b1),\n .D(init_complete_r_timing),\n .Q(init_complete_r1_timing),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE #(\n .INIT(1'b0)) \n init_complete_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(init_complete_r1),\n .Q(init_complete_r2),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE #(\n .INIT(1'b0)) \n init_complete_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\init_state_r_reg[6]_0 ),\n .Q(init_complete_r1_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__12));\n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n init_complete_r_timing_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\init_state_r_reg[6]_1 ),\n .Q(init_complete_r_timing),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE #(\n .INIT(1'b0)) \n \\init_state_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(Q[0]),\n .Q(init_state_r1[0]),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE #(\n .INIT(1'b0)) \n \\init_state_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(Q[1]),\n .Q(init_state_r1[1]),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE #(\n .INIT(1'b0)) \n \\init_state_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(Q[2]),\n .Q(init_state_r1[2]),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE #(\n .INIT(1'b0)) \n \\init_state_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\init_state_r_reg_n_0_[3] ),\n .Q(init_state_r1[3]),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE #(\n .INIT(1'b0)) \n \\init_state_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(Q[3]),\n .Q(init_state_r1[4]),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE #(\n .INIT(1'b0)) \n \\init_state_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(Q[4]),\n .Q(init_state_r1[5]),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE #(\n .INIT(1'b0)) \n \\init_state_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(Q[5]),\n .Q(init_state_r1[6]),\n .R(rstdiv0_sync_r1_reg_rep__11));\n LUT6 #(\n .INIT(64'hAAAAAAAAEEEFFFFF)) \n \\init_state_r[0]_i_1 \n (.I0(\\init_state_r[0]_i_2_n_0 ),\n .I1(\\init_state_r[0]_i_3_n_0 ),\n .I2(oclk_calib_resume_level_reg_0),\n .I3(\\init_state_r[0]_i_5_n_0 ),\n .I4(\\init_state_r[0]_i_6_n_0 ),\n .I5(\\init_state_r[0]_i_7_n_0 ),\n .O(\\init_state_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFF000000FFFF1103)) \n \\init_state_r[0]_i_10 \n (.I0(\\init_state_r[0]_i_26_n_0 ),\n .I1(prech_pending_r_reg_0),\n .I2(\\init_state_r[0]_i_27_n_0 ),\n .I3(Q[0]),\n .I4(Q[1]),\n .I5(prbs_rdlvl_done_pulse0),\n .O(\\init_state_r[0]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'hEFEFEFEFFFEFEFEF)) \n \\init_state_r[0]_i_11 \n (.I0(\\init_state_r[0]_i_28_n_0 ),\n .I1(\\init_state_r[0]_i_29_n_0 ),\n .I2(Q[3]),\n .I3(\\init_state_r[0]_i_30_n_0 ),\n .I4(\\wrcal_reads[7]_i_5_n_0 ),\n .I5(\\init_state_r[0]_i_31_n_0 ),\n .O(\\init_state_r[0]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'hDDDFDDDDDDDDDDDD)) \n \\init_state_r[0]_i_13 \n (.I0(Q[3]),\n .I1(\\init_state_r_reg[5]_0 ),\n .I2(\\init_state_r[4]_i_5_n_0 ),\n .I3(Q[0]),\n .I4(cnt_cmd_done_r),\n .I5(\\init_state_r[0]_i_33_n_0 ),\n .O(\\init_state_r[0]_i_13_n_0 ));\n LUT5 #(\n .INIT(32'hAAAABBAB)) \n \\init_state_r[0]_i_14 \n (.I0(Q[1]),\n .I1(\\init_state_r[0]_i_34_n_0 ),\n .I2(rdlvl_stg1_done_int_reg),\n .I3(rdlvl_stg1_done_r1),\n .I4(rdlvl_stg1_rank_done),\n .O(\\init_state_r[0]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'h0000FF00FF00FE00)) \n \\init_state_r[0]_i_15 \n (.I0(prech_pending_r_reg_0),\n .I1(pi_dqs_found_rank_done),\n .I2(dqs_found_done_r_reg),\n .I3(Q[1]),\n .I4(cnt_cmd_done_r),\n .I5(Q[0]),\n .O(\\init_state_r[0]_i_15_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000F0FEFE)) \n \\init_state_r[0]_i_16 \n (.I0(prbs_rdlvl_done_reg_rep_2),\n .I1(wrlvl_final_mux_reg),\n .I2(cnt_init_af_done_r),\n .I3(mem_init_done_r),\n .I4(oclkdelay_calib_done_r_reg_5),\n .I5(wrlvl_byte_redo_reg_0),\n .O(\\init_state_r[0]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'h1505155515001550)) \n \\init_state_r[0]_i_17 \n (.I0(oclk_calib_resume_level_reg_0),\n .I1(cnt_cmd_done_r),\n .I2(Q[0]),\n .I3(Q[1]),\n .I4(cnt_txpr_done_r),\n .I5(delay_done_r4_reg),\n .O(\\init_state_r[0]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFDF005F00)) \n \\init_state_r[0]_i_18 \n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(cnt_cmd_done_r),\n .I3(\\init_state_r_reg[1]_0 ),\n .I4(wrlvl_done_r1),\n .I5(\\init_state_r[0]_i_40_n_0 ),\n .O(\\init_state_r[0]_i_18_n_0 ));\n LUT6 #(\n .INIT(64'hAEBBBFBBAABBBFBB)) \n \\init_state_r[0]_i_19 \n (.I0(\\init_state_r[0]_i_41_n_0 ),\n .I1(Q[1]),\n .I2(reset_rd_addr_r1),\n .I3(Q[0]),\n .I4(cnt_cmd_done_r),\n .I5(rdlvl_stg1_done_r1),\n .O(\\init_state_r[0]_i_19_n_0 ));\n LUT6 #(\n .INIT(64'hABABABABAAABAAAA)) \n \\init_state_r[0]_i_2 \n (.I0(\\init_state_r[0]_i_8_n_0 ),\n .I1(\\init_state_r[5]_i_26_n_0 ),\n .I2(\\init_state_r[0]_i_9_n_0 ),\n .I3(\\init_state_r[0]_i_10_n_0 ),\n .I4(\\init_state_r_reg[1]_0 ),\n .I5(\\init_state_r[0]_i_11_n_0 ),\n .O(\\init_state_r[0]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair483\" *) \n LUT5 #(\n .INIT(32'hFFFDDDDD)) \n \\init_state_r[0]_i_20 \n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(rdlvl_stg1_done_r1),\n .I3(complex_sample_cnt_inc_i_2_n_0),\n .I4(\\init_state_r[5]_i_32_n_0 ),\n .O(\\init_state_r[0]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFF133)) \n \\init_state_r[0]_i_21 \n (.I0(\\init_state_r[6]_i_22_n_0 ),\n .I1(write_request_r_reg),\n .I2(prech_pending_r_reg_0),\n .I3(Q[0]),\n .I4(Q[2]),\n .I5(Q[1]),\n .O(\\init_state_r[0]_i_21_n_0 ));\n LUT6 #(\n .INIT(64'hFFBFAFBFAAAAAAAA)) \n \\init_state_r[0]_i_22 \n (.I0(oclk_calib_resume_level_reg_0),\n .I1(cnt_cmd_done_r),\n .I2(Q[1]),\n .I3(Q[0]),\n .I4(burst_addr_r_reg_0),\n .I5(\\init_state_r[0]_i_42_n_0 ),\n .O(\\init_state_r[0]_i_22_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFEAEAEEEA)) \n \\init_state_r[0]_i_23 \n (.I0(\\init_state_r[0]_i_43_n_0 ),\n .I1(\\init_state_r_reg[1]_0 ),\n .I2(\\init_state_r_reg[1]_1 ),\n .I3(cnt_cmd_done_r),\n .I4(Q[0]),\n .I5(\\init_state_r[4]_i_28_n_0 ),\n .O(\\init_state_r[0]_i_23_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair574\" *) \n LUT3 #(\n .INIT(8'h10)) \n \\init_state_r[0]_i_24 \n (.I0(Q[1]),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .I2(Q[2]),\n .O(\\init_state_r[0]_i_24_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair537\" *) \n LUT4 #(\n .INIT(16'h0010)) \n \\init_state_r[0]_i_25 \n (.I0(\\wrcal_reads_reg_n_0_[4] ),\n .I1(\\wrcal_reads_reg_n_0_[6] ),\n .I2(\\wrcal_reads_reg_n_0_[0] ),\n .I3(\\init_state_r[0]_i_45_n_0 ),\n .O(\\init_state_r[0]_i_25_n_0 ));\n LUT6 #(\n .INIT(64'h0888888888888888)) \n \\init_state_r[0]_i_26 \n (.I0(complex_sample_cnt_inc_i_2_n_0),\n .I1(Q[0]),\n .I2(complex_wait_cnt_reg__0[0]),\n .I3(complex_wait_cnt_reg__0[1]),\n .I4(complex_wait_cnt_reg__0[2]),\n .I5(complex_wait_cnt_reg__0[3]),\n .O(\\init_state_r[0]_i_26_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000004)) \n \\init_state_r[0]_i_27 \n (.I0(complex_num_reads_dec_reg__0[1]),\n .I1(complex_num_reads_dec_reg__0[0]),\n .I2(prbs_rdlvl_done_reg_rep),\n .I3(complex_row0_rd_done),\n .I4(complex_num_reads_dec_reg__0[3]),\n .I5(complex_num_reads_dec_reg__0[2]),\n .O(\\init_state_r[0]_i_27_n_0 ));\n LUT6 #(\n .INIT(64'h0101010101014501)) \n \\init_state_r[0]_i_28 \n (.I0(\\init_state_r[4]_i_5_n_0 ),\n .I1(Q[1]),\n .I2(\\init_state_r[0]_i_46_n_0 ),\n .I3(prbs_rdlvl_done_reg_rep_0),\n .I4(Q[0]),\n .I5(complex_oclk_calib_resume),\n .O(\\init_state_r[0]_i_28_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000F0EFE0)) \n \\init_state_r[0]_i_29 \n (.I0(\\init_state_r[6]_i_17_n_0 ),\n .I1(oclkdelay_center_calib_start_r_reg_0),\n .I2(Q[1]),\n .I3(cnt_cmd_done_r),\n .I4(Q[0]),\n .I5(oclk_calib_resume_level_reg_0),\n .O(\\init_state_r[0]_i_29_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF000E0000)) \n \\init_state_r[0]_i_3 \n (.I0(\\init_state_r[2]_i_12_n_0 ),\n .I1(wrcal_sanity_chk_done_reg),\n .I2(Q[1]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[2]),\n .I5(\\init_state_r[0]_i_13_n_0 ),\n .O(\\init_state_r[0]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFDFDFDFDD)) \n \\init_state_r[0]_i_30 \n (.I0(prbs_gen_oclk_clk_en_i_8_n_0),\n .I1(\\init_state_r[3]_i_23_n_0 ),\n .I2(complex_oclkdelay_calib_start_r2),\n .I3(prbs_rdlvl_done_reg),\n .I4(prbs_last_byte_done_r),\n .I5(\\init_state_r[4]_i_39_n_0 ),\n .O(\\init_state_r[0]_i_30_n_0 ));\n LUT6 #(\n .INIT(64'h0004000400000004)) \n \\init_state_r[0]_i_31 \n (.I0(oclkdelay_center_calib_start_r_reg),\n .I1(prbs_gen_oclk_clk_en_i_8_n_0),\n .I2(prech_pending_r_reg_0),\n .I3(prbs_rdlvl_start_i_2_n_0),\n .I4(complex_row1_wr_done),\n .I5(\\one_rank.stg1_wr_done_reg_0 ),\n .O(\\init_state_r[0]_i_31_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair559\" *) \n LUT4 #(\n .INIT(16'hFFEF)) \n \\init_state_r[0]_i_33 \n (.I0(reg_ctrl_cnt_r_reg__0[1]),\n .I1(reg_ctrl_cnt_r_reg__0[0]),\n .I2(reg_ctrl_cnt_r_reg__0[3]),\n .I3(reg_ctrl_cnt_r_reg__0[2]),\n .O(\\init_state_r[0]_i_33_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair541\" *) \n LUT4 #(\n .INIT(16'hFFAE)) \n \\init_state_r[0]_i_34 \n (.I0(Q[0]),\n .I1(prbs_rdlvl_done_reg_rep),\n .I2(prbs_rdlvl_done_r1),\n .I3(prech_pending_r_reg_0),\n .O(\\init_state_r[0]_i_34_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\init_state_r[0]_i_4 \n (.I0(Q[2]),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .O(oclk_calib_resume_level_reg_0));\n LUT6 #(\n .INIT(64'hBAFFAAAABFFFAAAA)) \n \\init_state_r[0]_i_40 \n (.I0(Q[3]),\n .I1(wrlvl_rank_done_r7),\n .I2(Q[1]),\n .I3(Q[0]),\n .I4(\\wrcal_reads[7]_i_5_n_0 ),\n .I5(cnt_dllk_zqinit_done_r),\n .O(\\init_state_r[0]_i_40_n_0 ));\n LUT6 #(\n .INIT(64'h0000400044444444)) \n \\init_state_r[0]_i_41 \n (.I0(Q[1]),\n .I1(pi_calib_done),\n .I2(\\init_state_r[0]_i_51_n_0 ),\n .I3(wrcal_done_reg_10),\n .I4(rdlvl_stg1_done_int_reg_4),\n .I5(dqs_found_done_r_reg),\n .O(\\init_state_r[0]_i_41_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAABABB)) \n \\init_state_r[0]_i_42 \n (.I0(\\init_state_r[1]_i_20_n_0 ),\n .I1(Q[0]),\n .I2(wrcal_prech_req),\n .I3(cnt_cmd_done_r),\n .I4(wrcal_done_reg_10),\n .I5(prech_pending_r_reg_0),\n .O(\\init_state_r[0]_i_42_n_0 ));\n LUT6 #(\n .INIT(64'h000000000000F0EF)) \n \\init_state_r[0]_i_43 \n (.I0(\\init_state_r[2]_i_36_n_0 ),\n .I1(cnt_cmd_done_r_reg_1),\n .I2(Q[1]),\n .I3(Q[0]),\n .I4(\\init_state_r[4]_i_5_n_0 ),\n .I5(\\init_state_r[5]_i_57_n_0 ),\n .O(\\init_state_r[0]_i_43_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFEFF)) \n \\init_state_r[0]_i_45 \n (.I0(\\wrcal_reads_reg_n_0_[3] ),\n .I1(\\wrcal_reads_reg_n_0_[1] ),\n .I2(\\wrcal_reads_reg_n_0_[7] ),\n .I3(Q[0]),\n .I4(\\wrcal_reads_reg_n_0_[2] ),\n .I5(\\wrcal_reads_reg_n_0_[5] ),\n .O(\\init_state_r[0]_i_45_n_0 ));\n LUT6 #(\n .INIT(64'h4500FFFF4545FFFF)) \n \\init_state_r[0]_i_46 \n (.I0(prech_pending_r_reg_0),\n .I1(complex_oclkdelay_calib_done_r1),\n .I2(prbs_rdlvl_done_reg),\n .I3(prbs_gen_oclk_clk_en_i_8_n_0),\n .I4(Q[0]),\n .I5(complex_sample_cnt_inc_i_2_n_0),\n .O(\\init_state_r[0]_i_46_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FFFF1000)) \n \\init_state_r[0]_i_5 \n (.I0(num_reads[1]),\n .I1(num_reads[2]),\n .I2(num_reads[0]),\n .I3(Q[0]),\n .I4(\\init_state_r[0]_i_14_n_0 ),\n .I5(\\init_state_r[0]_i_15_n_0 ),\n .O(\\init_state_r[0]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h0155455501550055)) \n \\init_state_r[0]_i_50 \n (.I0(\\init_state_r_reg[2]_0 ),\n .I1(prbs_rdlvl_done_reg_rep),\n .I2(prbs_last_byte_done_r),\n .I3(dqs_found_done_r_reg),\n .I4(rdlvl_stg1_done_int_reg),\n .I5(wrcal_done_reg_10),\n .O(\\init_state_r_reg[0]_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFC44)) \n \\init_state_r[0]_i_51 \n (.I0(rdlvl_stg1_start_int),\n .I1(prbs_rdlvl_done_reg_rep),\n .I2(\\one_rank.stg1_wr_done_reg_0 ),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(rdlvl_last_byte_done),\n .I5(prbs_last_byte_done),\n .O(\\init_state_r[0]_i_51_n_0 ));\n LUT6 #(\n .INIT(64'hEFAFFFBFFFFFFFFF)) \n \\init_state_r[0]_i_6 \n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(cnt_cmd_done_r),\n .I3(\\init_state_r[0]_i_16_n_0 ),\n .I4(ddr2_pre_flag_r_reg_0),\n .I5(\\init_state_r_reg[1]_0 ),\n .O(\\init_state_r[0]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hABAAABABABAAABAA)) \n \\init_state_r[0]_i_7 \n (.I0(\\init_state_r[5]_i_2_n_0 ),\n .I1(\\init_state_r[0]_i_17_n_0 ),\n .I2(\\init_state_r[0]_i_18_n_0 ),\n .I3(\\init_state_r[4]_i_5_n_0 ),\n .I4(\\init_state_r[0]_i_19_n_0 ),\n .I5(\\init_state_r[0]_i_20_n_0 ),\n .O(\\init_state_r[0]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h88008A008A008A00)) \n \\init_state_r[0]_i_8 \n (.I0(\\init_state_r[0]_i_21_n_0 ),\n .I1(Q[0]),\n .I2(Q[2]),\n .I3(Q[5]),\n .I4(\\init_state_r[5]_i_36_n_0 ),\n .I5(Q[1]),\n .O(\\init_state_r[0]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'h2222222200202222)) \n \\init_state_r[0]_i_9 \n (.I0(\\init_state_r[0]_i_22_n_0 ),\n .I1(\\init_state_r[0]_i_23_n_0 ),\n .I2(wrcal_done_reg_9),\n .I3(Q[0]),\n .I4(\\init_state_r[0]_i_24_n_0 ),\n .I5(\\init_state_r[0]_i_25_n_0 ),\n .O(\\init_state_r[0]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAAEEFE)) \n \\init_state_r[1]_i_1 \n (.I0(\\init_state_r[1]_i_2_n_0 ),\n .I1(\\init_state_r[1]_i_3_n_0 ),\n .I2(\\init_state_r_reg[1]_0 ),\n .I3(\\init_state_r[1]_i_5_n_0 ),\n .I4(\\init_state_r[5]_i_2_n_0 ),\n .I5(\\init_state_r[1]_i_6_n_0 ),\n .O(\\init_state_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair501\" *) \n LUT5 #(\n .INIT(32'hFFFBAAAA)) \n \\init_state_r[1]_i_10 \n (.I0(\\init_state_r[0]_i_14_n_0 ),\n .I1(num_reads[0]),\n .I2(num_reads[2]),\n .I3(num_reads[1]),\n .I4(Q[0]),\n .O(\\init_state_r[1]_i_10_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair523\" *) \n LUT5 #(\n .INIT(32'h22222220)) \n \\init_state_r[1]_i_11 \n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(dqs_found_done_r_reg),\n .I3(pi_dqs_found_rank_done),\n .I4(prech_pending_r_reg_0),\n .O(\\init_state_r[1]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'hBBBBBBFFBBFFBBFB)) \n \\init_state_r[1]_i_12 \n (.I0(\\init_state_r[1]_i_25_n_0 ),\n .I1(Q[3]),\n .I2(cnt_cmd_done_r),\n .I3(\\init_state_r[4]_i_5_n_0 ),\n .I4(Q[0]),\n .I5(Q[1]),\n .O(\\init_state_r[1]_i_12_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF0B0B080B)) \n \\init_state_r[1]_i_13 \n (.I0(wrlvl_byte_redo_reg),\n .I1(mpr_rdlvl_done_r_reg_2),\n .I2(\\init_state_r[1]_i_26_n_0 ),\n .I3(oclkdelay_calib_done_r_reg_2),\n .I4(\\init_state_r[1]_i_27_n_0 ),\n .I5(\\init_state_r[1]_i_28_n_0 ),\n .O(\\init_state_r[1]_i_13_n_0 ));\n LUT6 #(\n .INIT(64'hFFE0FFE0FFE0FFFF)) \n \\init_state_r[1]_i_15 \n (.I0(dqs_found_done_r_reg_2),\n .I1(prbs_last_byte_done_reg),\n .I2(\\init_state_r[1]_i_33_n_0 ),\n .I3(\\init_state_r[1]_i_34_n_0 ),\n .I4(Q[0]),\n .I5(\\init_state_r[5]_i_32_n_0 ),\n .O(\\init_state_r[1]_i_15_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair563\" *) \n LUT4 #(\n .INIT(16'h0020)) \n \\init_state_r[1]_i_16 \n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(cnt_dllk_zqinit_done_r),\n .I3(mem_init_done_r),\n .O(\\init_state_r[1]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF7070FF70)) \n \\init_state_r[1]_i_17 \n (.I0(Q[0]),\n .I1(wrlvl_rank_done_r7),\n .I2(\\init_state_r[1]_i_35_n_0 ),\n .I3(\\init_state_r_reg[1]_0 ),\n .I4(\\init_state_r[1]_i_36_n_0 ),\n .I5(Q[3]),\n .O(\\init_state_r[1]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'hE0000F0FE000FFFF)) \n \\init_state_r[1]_i_18 \n (.I0(cnt_init_mr_done_r),\n .I1(dqs_found_done_r_reg_0),\n .I2(Q[0]),\n .I3(cnt_cmd_done_r),\n .I4(Q[1]),\n .I5(cnt_txpr_done_r),\n .O(\\init_state_r[1]_i_18_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair530\" *) \n LUT5 #(\n .INIT(32'hF2F2F2FF)) \n \\init_state_r[1]_i_19 \n (.I0(cnt_cmd_done_r),\n .I1(wrcal_prech_req),\n .I2(Q[0]),\n .I3(prech_pending_r_reg_0),\n .I4(wrcal_done_reg_10),\n .O(\\init_state_r[1]_i_19_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF0200)) \n \\init_state_r[1]_i_2 \n (.I0(Q[4]),\n .I1(Q[5]),\n .I2(\\init_state_r[1]_i_7_n_0 ),\n .I3(\\init_state_r[1]_i_8_n_0 ),\n .I4(\\init_state_r[1]_i_9_n_0 ),\n .I5(\\init_state_r[5]_i_19_n_0 ),\n .O(\\init_state_r[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAABAAAAAAAAAA)) \n \\init_state_r[1]_i_20 \n (.I0(Q[1]),\n .I1(wrcal_wr_cnt_reg__0[3]),\n .I2(wrcal_wr_cnt_reg__0[2]),\n .I3(wrcal_wr_cnt_reg__0[0]),\n .I4(wrcal_wr_cnt_reg__0[1]),\n .I5(Q[0]),\n .O(\\init_state_r[1]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'hFEFEFEFEFFFEFEFE)) \n \\init_state_r[1]_i_21 \n (.I0(\\init_state_r[1]_i_37_n_0 ),\n .I1(Q[3]),\n .I2(mpr_rdlvl_done_r_reg_0),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[2]),\n .I5(\\init_state_r[5]_i_57_n_0 ),\n .O(\\init_state_r[1]_i_21_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair526\" *) \n LUT5 #(\n .INIT(32'hEFEEAAAA)) \n \\init_state_r[1]_i_22 \n (.I0(Q[1]),\n .I1(prech_pending_r_reg_0),\n .I2(complex_oclkdelay_calib_done_r1),\n .I3(prbs_rdlvl_done_reg_rep),\n .I4(Q[0]),\n .O(\\init_state_r[1]_i_22_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFAABA)) \n \\init_state_r[1]_i_23 \n (.I0(\\init_state_r[1]_i_39_n_0 ),\n .I1(Q[0]),\n .I2(\\init_state_r_reg[1]_0 ),\n .I3(\\init_state_r[1]_i_40_n_0 ),\n .I4(\\init_state_r[1]_i_41_n_0 ),\n .I5(\\init_state_r[1]_i_42_n_0 ),\n .O(\\init_state_r[1]_i_23_n_0 ));\n LUT6 #(\n .INIT(64'hCCCCCC88CCCCCC08)) \n \\init_state_r[1]_i_24 \n (.I0(\\init_state_r[5]_i_13_n_0 ),\n .I1(\\init_state_r[1]_i_43_n_0 ),\n .I2(\\init_state_r[0]_i_27_n_0 ),\n .I3(prech_pending_r_reg_0),\n .I4(prbs_rdlvl_done_pulse0),\n .I5(Q[0]),\n .O(\\init_state_r[1]_i_24_n_0 ));\n LUT6 #(\n .INIT(64'h2820202028202820)) \n \\init_state_r[1]_i_25 \n (.I0(\\wrcal_reads[7]_i_5_n_0 ),\n .I1(Q[0]),\n .I2(Q[1]),\n .I3(cnt_cmd_done_r),\n .I4(wrcal_sanity_chk_done_reg_0),\n .I5(rdlvl_stg1_done_int_reg_2),\n .O(\\init_state_r[1]_i_25_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair490\" *) \n LUT5 #(\n .INIT(32'h0020FFFF)) \n \\init_state_r[1]_i_26 \n (.I0(prbs_last_byte_done_r),\n .I1(prbs_rdlvl_done_reg_rep),\n .I2(dqs_found_done_r_reg),\n .I3(\\init_state_r_reg[2]_0 ),\n .I4(mem_init_done_r),\n .O(\\init_state_r[1]_i_26_n_0 ));\n LUT6 #(\n .INIT(64'h8A8A8A88AAAAAAAA)) \n \\init_state_r[1]_i_27 \n (.I0(wrlvl_final_mux_reg_0),\n .I1(wrlvl_done_r1),\n .I2(prbs_rdlvl_done_reg_rep),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(prbs_last_byte_done_r),\n .I5(prbs_rdlvl_done_reg_rep_3),\n .O(\\init_state_r[1]_i_27_n_0 ));\n LUT6 #(\n .INIT(64'h000000F200000000)) \n \\init_state_r[1]_i_28 \n (.I0(wrcal_done_reg_10),\n .I1(\\init_state_r[1]_i_46_n_0 ),\n .I2(prbs_rdlvl_done_reg_rep_1),\n .I3(mem_init_done_r),\n .I4(cnt_init_af_done_r),\n .I5(mpr_rdlvl_done_r_reg_1),\n .O(\\init_state_r[1]_i_28_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF0000FF5D)) \n \\init_state_r[1]_i_3 \n (.I0(\\init_state_r[1]_i_10_n_0 ),\n .I1(Q[1]),\n .I2(cnt_cmd_done_r),\n .I3(\\init_state_r[1]_i_11_n_0 ),\n .I4(oclk_calib_resume_level_reg_0),\n .I5(\\init_state_r[1]_i_12_n_0 ),\n .O(\\init_state_r[1]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair578\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\init_state_r[1]_i_33 \n (.I0(pi_calib_done),\n .I1(Q[1]),\n .O(\\init_state_r[1]_i_33_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF10000FFF)) \n \\init_state_r[1]_i_34 \n (.I0(rdlvl_stg1_done_r1),\n .I1(reset_rd_addr_r1),\n .I2(Q[0]),\n .I3(cnt_cmd_done_r),\n .I4(Q[1]),\n .I5(\\init_state_r[4]_i_5_n_0 ),\n .O(\\init_state_r[1]_i_34_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair567\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\init_state_r[1]_i_35 \n (.I0(Q[1]),\n .I1(Q[2]),\n .I2(\\init_state_r_reg_n_0_[3] ),\n .O(\\init_state_r[1]_i_35_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair563\" *) \n LUT3 #(\n .INIT(8'h07)) \n \\init_state_r[1]_i_36 \n (.I0(Q[0]),\n .I1(cnt_cmd_done_r),\n .I2(Q[1]),\n .O(\\init_state_r[1]_i_36_n_0 ));\n LUT6 #(\n .INIT(64'h4444444044404440)) \n \\init_state_r[1]_i_37 \n (.I0(Q[0]),\n .I1(\\wrcal_reads[7]_i_5_n_0 ),\n .I2(\\init_state_r[5]_i_49_n_0 ),\n .I3(Q[1]),\n .I4(wrcal_final_chk),\n .I5(wrcal_resume_r),\n .O(\\init_state_r[1]_i_37_n_0 ));\n LUT6 #(\n .INIT(64'h1FFF0000FFFFFFFF)) \n \\init_state_r[1]_i_39 \n (.I0(\\one_rank.stg1_wr_done_reg_0 ),\n .I1(oclkdelay_center_calib_start_r_reg),\n .I2(prbs_gen_oclk_clk_en_i_8_n_0),\n .I3(\\init_state_r[2]_i_33_n_0 ),\n .I4(\\init_state_r[1]_i_35_n_0 ),\n .I5(Q[3]),\n .O(\\init_state_r[1]_i_39_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair538\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\init_state_r[1]_i_4 \n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(Q[2]),\n .O(\\init_state_r_reg[1]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair548\" *) \n LUT4 #(\n .INIT(16'hB0BB)) \n \\init_state_r[1]_i_40 \n (.I0(prbs_rdlvl_done_r1),\n .I1(prbs_rdlvl_done_reg_rep),\n .I2(prbs_gen_oclk_clk_en_i_8_n_0),\n .I3(Q[1]),\n .O(\\init_state_r[1]_i_40_n_0 ));\n LUT6 #(\n .INIT(64'h1515100015155444)) \n \\init_state_r[1]_i_41 \n (.I0(oclk_calib_resume_level_reg_0),\n .I1(Q[1]),\n .I2(cnt_cmd_done_r),\n .I3(oclkdelay_int_ref_req_reg_0),\n .I4(Q[0]),\n .I5(\\init_state_r[1]_i_47_n_0 ),\n .O(\\init_state_r[1]_i_41_n_0 ));\n LUT6 #(\n .INIT(64'h0000000088880080)) \n \\init_state_r[1]_i_42 \n (.I0(Q[0]),\n .I1(\\wrcal_reads[7]_i_5_n_0 ),\n .I2(prbs_gen_oclk_clk_en_i_8_n_0),\n .I3(\\init_state_r[1]_i_48_n_0 ),\n .I4(prbs_rdlvl_done_pulse0),\n .I5(Q[1]),\n .O(\\init_state_r[1]_i_42_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair567\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\init_state_r[1]_i_43 \n (.I0(Q[1]),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .I2(Q[2]),\n .O(\\init_state_r[1]_i_43_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\init_state_r[1]_i_46 \n (.I0(wrlvl_final_mux),\n .I1(wrlvl_done_r1),\n .O(\\init_state_r[1]_i_46_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000010000)) \n \\init_state_r[1]_i_47 \n (.I0(wrlvl_final_mux),\n .I1(oclkdelay_int_ref_req_reg_0),\n .I2(prech_pending_r_reg_0),\n .I3(oclkdelay_calib_done_r_reg_2),\n .I4(oclkdelay_center_calib_start_r_reg),\n .I5(\\init_state_r[6]_i_17_n_0 ),\n .O(\\init_state_r[1]_i_47_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair507\" *) \n LUT5 #(\n .INIT(32'h0000CC40)) \n \\init_state_r[1]_i_48 \n (.I0(complex_oclkdelay_calib_start_int),\n .I1(done_r_reg),\n .I2(prbs_last_byte_done_r),\n .I3(prbs_rdlvl_done_reg_rep),\n .I4(complex_oclkdelay_calib_start_r2),\n .O(\\init_state_r[1]_i_48_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF00002222F0FF)) \n \\init_state_r[1]_i_5 \n (.I0(\\init_state_r[1]_i_13_n_0 ),\n .I1(oclkdelay_calib_done_r_reg_4),\n .I2(ddr2_pre_flag_r_reg_0),\n .I3(cnt_cmd_done_r),\n .I4(Q[1]),\n .I5(Q[0]),\n .O(\\init_state_r[1]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h0000A2AA0000A0A8)) \n \\init_state_r[1]_i_6 \n (.I0(\\init_state_r[1]_i_15_n_0 ),\n .I1(Q[2]),\n .I2(\\init_state_r_reg_n_0_[3] ),\n .I3(\\init_state_r[1]_i_16_n_0 ),\n .I4(\\init_state_r[1]_i_17_n_0 ),\n .I5(\\init_state_r[1]_i_18_n_0 ),\n .O(\\init_state_r[1]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h00000000BABAFFBA)) \n \\init_state_r[1]_i_7 \n (.I0(oclk_calib_resume_level_reg_0),\n .I1(prbs_rdlvl_start_i_2_n_0),\n .I2(burst_addr_r_reg_0),\n .I3(\\init_state_r[1]_i_19_n_0 ),\n .I4(\\init_state_r[1]_i_20_n_0 ),\n .I5(\\init_state_r[1]_i_21_n_0 ),\n .O(\\init_state_r[1]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF00FD)) \n \\init_state_r[1]_i_8 \n (.I0(\\init_state_r[5]_i_42_n_0 ),\n .I1(\\init_state_r[1]_i_22_n_0 ),\n .I2(prbs_gen_oclk_clk_en_i_8_n_0),\n .I3(\\init_state_r[4]_i_5_n_0 ),\n .I4(\\init_state_r[1]_i_23_n_0 ),\n .I5(\\init_state_r[1]_i_24_n_0 ),\n .O(\\init_state_r[1]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'hFF80FFFF80808080)) \n \\init_state_r[1]_i_9 \n (.I0(Q[5]),\n .I1(Q[2]),\n .I2(Q[1]),\n .I3(prech_pending_r_reg_0),\n .I4(oclkdelay_calib_done_r_reg_2),\n .I5(\\init_state_r[6]_i_12_n_0 ),\n .O(\\init_state_r[1]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hAEAEAEAAAEAEAEAE)) \n \\init_state_r[2]_i_1 \n (.I0(\\init_state_r[2]_i_2_n_0 ),\n .I1(\\init_state_r[2]_i_3_n_0 ),\n .I2(\\init_state_r[5]_i_2_n_0 ),\n .I3(\\init_state_r[2]_i_4_n_0 ),\n .I4(\\init_state_r[2]_i_5_n_0 ),\n .I5(\\init_state_r[2]_i_6_n_0 ),\n .O(\\init_state_r[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAA0002)) \n \\init_state_r[2]_i_10 \n (.I0(\\init_state_r[2]_i_25_n_0 ),\n .I1(dqs_found_done_r_reg_0),\n .I2(cnt_init_mr_done_r),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[2]),\n .I5(\\init_state_r[2]_i_26_n_0 ),\n .O(\\init_state_r[2]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'hF2FF000000000000)) \n \\init_state_r[2]_i_11 \n (.I0(pi_calib_done),\n .I1(wrcal_done_reg_11),\n .I2(Q[1]),\n .I3(cnt_cmd_done_r),\n .I4(\\init_state_r[2]_i_27_n_0 ),\n .I5(\\init_state_r[0]_i_20_n_0 ),\n .O(\\init_state_r[2]_i_11_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair530\" *) \n LUT2 #(\n .INIT(4'h7)) \n \\init_state_r[2]_i_12 \n (.I0(Q[0]),\n .I1(cnt_cmd_done_r),\n .O(\\init_state_r[2]_i_12_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair494\" *) \n LUT5 #(\n .INIT(32'h45454500)) \n \\init_state_r[2]_i_14 \n (.I0(\\init_state_r_reg[2]_0 ),\n .I1(mem_init_done_r),\n .I2(cnt_init_af_done_r),\n .I3(prbs_rdlvl_done_reg_rep_1),\n .I4(\\init_state_r[4]_i_26_n_0 ),\n .O(\\init_state_r[2]_i_14_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair503\" *) \n LUT2 #(\n .INIT(4'h7)) \n \\init_state_r[2]_i_16 \n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(Q[1]),\n .O(\\init_state_r[2]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'hAAAABFFFAAAABBBB)) \n \\init_state_r[2]_i_17 \n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(cnt_cmd_done_r),\n .I4(Q[2]),\n .I5(\\init_state_r[5]_i_56_n_0 ),\n .O(\\init_state_r[2]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'h80AA808080AA80AA)) \n \\init_state_r[2]_i_18 \n (.I0(Q[2]),\n .I1(prbs_rdlvl_done_pulse0),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .I3(\\init_state_r[6]_i_23_n_0 ),\n .I4(\\init_state_r[2]_i_32_n_0 ),\n .I5(\\init_state_r[2]_i_33_n_0 ),\n .O(\\init_state_r[2]_i_18_n_0 ));\n LUT6 #(\n .INIT(64'hF200FFFFF200F200)) \n \\init_state_r[2]_i_2 \n (.I0(complex_pi_incdec_done),\n .I1(prbs_rdlvl_start_i_2_n_0),\n .I2(\\init_state_r[2]_i_7_n_0 ),\n .I3(Q[5]),\n .I4(\\init_state_r[2]_i_8_n_0 ),\n .I5(\\init_state_r[2]_i_9_n_0 ),\n .O(\\init_state_r[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h10111010FFFFFFFF)) \n \\init_state_r[2]_i_20 \n (.I0(\\init_state_r[2]_i_16_n_0 ),\n .I1(Q[2]),\n .I2(complex_oclkdelay_calib_start_int_reg_0),\n .I3(prbs_rdlvl_done_pulse0),\n .I4(prbs_gen_oclk_clk_en_i_8_n_0),\n .I5(Q[3]),\n .O(\\init_state_r[2]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'hF000F2F200000000)) \n \\init_state_r[2]_i_21 \n (.I0(pi_phase_locked_all_r3),\n .I1(pi_phase_locked_all_r4),\n .I2(Q[0]),\n .I3(\\init_state_r[2]_i_34_n_0 ),\n .I4(\\init_state_r_reg_n_0_[3] ),\n .I5(\\init_state_r[2]_i_35_n_0 ),\n .O(\\init_state_r[2]_i_21_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF010FFFFFFFFF)) \n \\init_state_r[2]_i_22 \n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(burst_addr_r_reg_0),\n .I2(Q[2]),\n .I3(Q[1]),\n .I4(Q[5]),\n .I5(Q[4]),\n .O(\\init_state_r[2]_i_22_n_0 ));\n LUT6 #(\n .INIT(64'hFFBFBBBBAAAAAAAA)) \n \\init_state_r[2]_i_24 \n (.I0(Q[0]),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .I2(\\init_state_r[2]_i_36_n_0 ),\n .I3(cnt_cmd_done_r_reg_1),\n .I4(Q[1]),\n .I5(Q[2]),\n .O(\\init_state_r[2]_i_24_n_0 ));\n LUT6 #(\n .INIT(64'hFF0F4F4F0F0F0F0F)) \n \\init_state_r[2]_i_25 \n (.I0(mem_init_done_r),\n .I1(cnt_dllk_zqinit_done_r),\n .I2(Q[2]),\n .I3(wrlvl_rank_done_r7),\n .I4(Q[1]),\n .I5(Q[0]),\n .O(\\init_state_r[2]_i_25_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair545\" *) \n LUT3 #(\n .INIT(8'h7F)) \n \\init_state_r[2]_i_26 \n (.I0(cnt_cmd_done_r),\n .I1(Q[0]),\n .I2(Q[1]),\n .O(\\init_state_r[2]_i_26_n_0 ));\n LUT6 #(\n .INIT(64'hEC00FFF0ECF0FFF0)) \n \\init_state_r[2]_i_27 \n (.I0(reset_rd_addr_r1),\n .I1(cnt_cmd_done_r),\n .I2(Q[1]),\n .I3(Q[0]),\n .I4(Q[2]),\n .I5(complex_sample_cnt_inc_i_2_n_0),\n .O(\\init_state_r[2]_i_27_n_0 ));\n LUT6 #(\n .INIT(64'hF0FFF1F1F3F3F3F3)) \n \\init_state_r[2]_i_3 \n (.I0(wrlvl_done_r1),\n .I1(\\init_state_r[2]_i_10_n_0 ),\n .I2(Q[3]),\n .I3(\\init_state_r[2]_i_11_n_0 ),\n .I4(Q[2]),\n .I5(\\init_state_r_reg_n_0_[3] ),\n .O(\\init_state_r[2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hAB00AB00AB00ABFF)) \n \\init_state_r[2]_i_30 \n (.I0(\\init_state_r[2]_i_37_n_0 ),\n .I1(wrlvl_done_r1),\n .I2(wrlvl_byte_redo),\n .I3(mem_init_done_r),\n .I4(wrcal_done_reg_10),\n .I5(cnt_init_af_done_r),\n .O(\\init_state_r_reg[2]_1 ));\n LUT6 #(\n .INIT(64'h8000800080000000)) \n \\init_state_r[2]_i_32 \n (.I0(complex_wait_cnt_reg__0[3]),\n .I1(complex_wait_cnt_reg__0[2]),\n .I2(complex_wait_cnt_reg__0[1]),\n .I3(complex_wait_cnt_reg__0[0]),\n .I4(oclkdelay_center_calib_start_r_reg),\n .I5(\\one_rank.stg1_wr_done_reg_0 ),\n .O(\\init_state_r[2]_i_32_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair523\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\init_state_r[2]_i_33 \n (.I0(Q[0]),\n .I1(prech_pending_r_reg_0),\n .O(\\init_state_r[2]_i_33_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair544\" *) \n LUT4 #(\n .INIT(16'h0010)) \n \\init_state_r[2]_i_34 \n (.I0(oclk_wr_cnt_reg__0[3]),\n .I1(oclk_wr_cnt_reg__0[1]),\n .I2(oclk_wr_cnt_reg__0[0]),\n .I3(oclk_wr_cnt_reg__0[2]),\n .O(\\init_state_r[2]_i_34_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair548\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\init_state_r[2]_i_35 \n (.I0(Q[2]),\n .I1(Q[1]),\n .O(\\init_state_r[2]_i_35_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair531\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\init_state_r[2]_i_36 \n (.I0(prech_pending_r_reg_0),\n .I1(oclkdelay_calib_done_r_reg_2),\n .O(\\init_state_r[2]_i_36_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair571\" *) \n LUT3 #(\n .INIT(8'hDF)) \n \\init_state_r[2]_i_37 \n (.I0(prbs_last_byte_done_r),\n .I1(prbs_rdlvl_done_reg_rep),\n .I2(dqs_found_done_r_reg),\n .O(\\init_state_r[2]_i_37_n_0 ));\n LUT6 #(\n .INIT(64'hEEFE000000000000)) \n \\init_state_r[2]_i_4 \n (.I0(wrcal_sanity_chk_done_reg_0),\n .I1(\\init_state_r[2]_i_12_n_0 ),\n .I2(ddr3_lm_done_r),\n .I3(rdlvl_stg1_done_int_reg_2),\n .I4(prbs_rdlvl_start_i_2_n_0),\n .I5(\\wrcal_reads[7]_i_5_n_0 ),\n .O(\\init_state_r[2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h5FF755555555D555)) \n \\init_state_r[2]_i_5 \n (.I0(Q[3]),\n .I1(cnt_cmd_done_r),\n .I2(Q[0]),\n .I3(Q[1]),\n .I4(Q[2]),\n .I5(\\init_state_r_reg_n_0_[3] ),\n .O(\\init_state_r[2]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF040F)) \n \\init_state_r[2]_i_6 \n (.I0(\\init_state_r[2]_i_14_n_0 ),\n .I1(cnt_init_af_done_r_reg_1),\n .I2(Q[0]),\n .I3(cnt_cmd_done_r),\n .I4(Q[2]),\n .I5(\\init_state_r[2]_i_16_n_0 ),\n .O(\\init_state_r[2]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hAAAEAAAAAAAAAAAA)) \n \\init_state_r[2]_i_7 \n (.I0(Q[2]),\n .I1(oclkdelay_calib_done_r_reg_2),\n .I2(prech_pending_r_reg_0),\n .I3(Q[1]),\n .I4(Q[0]),\n .I5(\\init_state_r[6]_i_22_n_0 ),\n .O(\\init_state_r[2]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h000E000E0000000E)) \n \\init_state_r[2]_i_8 \n (.I0(\\init_state_r[2]_i_17_n_0 ),\n .I1(\\init_state_r[2]_i_18_n_0 ),\n .I2(\\init_state_r_reg[2]_2 ),\n .I3(\\init_state_r[2]_i_20_n_0 ),\n .I4(\\init_state_r[5]_i_42_n_0 ),\n .I5(\\init_state_r[5]_i_41_n_0 ),\n .O(\\init_state_r[2]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'h11010000FFFFFFFF)) \n \\init_state_r[2]_i_9 \n (.I0(\\init_state_r[2]_i_21_n_0 ),\n .I1(\\init_state_r[2]_i_22_n_0 ),\n .I2(\\wrcal_reads[7]_i_6_n_0 ),\n .I3(wrcal_done_reg_9),\n .I4(\\init_state_r[2]_i_24_n_0 ),\n .I5(complex_oclkdelay_calib_start_int_i_2_n_0),\n .O(\\init_state_r[2]_i_9_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair481\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\init_state_r[3]_i_1 \n (.I0(\\init_state_r[3]_i_2_n_0 ),\n .O(\\init_state_r[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair562\" *) \n LUT4 #(\n .INIT(16'h0111)) \n \\init_state_r[3]_i_10 \n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(ddr2_pre_flag_r_reg_0),\n .I3(cnt_cmd_done_r),\n .O(\\init_state_r[3]_i_10_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair576\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\init_state_r[3]_i_11 \n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(cnt_cmd_done_r),\n .O(\\init_state_r[3]_i_11_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair529\" *) \n LUT5 #(\n .INIT(32'hF3FF23FF)) \n \\init_state_r[3]_i_13 \n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(cnt_cmd_done_r),\n .I2(Q[1]),\n .I3(Q[0]),\n .I4(reset_rd_addr_r1),\n .O(\\init_state_r[3]_i_13_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair491\" *) \n LUT5 #(\n .INIT(32'hFEFFFFFF)) \n \\init_state_r[3]_i_14 \n (.I0(Q[5]),\n .I1(Q[4]),\n .I2(Q[3]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[2]),\n .O(\\init_state_r[3]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF4440)) \n \\init_state_r[3]_i_15 \n (.I0(\\wrcal_reads[7]_i_5_n_0 ),\n .I1(Q[5]),\n .I2(\\init_state_r[3]_i_19_n_0 ),\n .I3(\\init_state_r[3]_i_20_n_0 ),\n .I4(\\init_state_r[3]_i_21_n_0 ),\n .I5(\\init_state_r[3]_i_22_n_0 ),\n .O(\\init_state_r[3]_i_15_n_0 ));\n LUT6 #(\n .INIT(64'h0202222202022202)) \n \\init_state_r[3]_i_16 \n (.I0(\\init_state_r[5]_i_41_n_0 ),\n .I1(\\init_state_r_reg[2]_2 ),\n .I2(\\init_state_r[5]_i_53_n_0 ),\n .I3(prbs_gen_oclk_clk_en_i_8_n_0),\n .I4(complex_oclkdelay_calib_start_int_reg_0),\n .I5(prbs_rdlvl_done_pulse0),\n .O(\\init_state_r[3]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'hFFDDFFFFF0DDFFFF)) \n \\init_state_r[3]_i_17 \n (.I0(\\init_state_r[3]_i_23_n_0 ),\n .I1(prbs_rdlvl_done_pulse0),\n .I2(prech_pending_r_reg_0),\n .I3(Q[1]),\n .I4(Q[0]),\n .I5(oclkdelay_center_calib_start_r_reg),\n .O(\\init_state_r[3]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'hCFFFAFCF00FF00CF)) \n \\init_state_r[3]_i_18 \n (.I0(oclkdelay_center_calib_start_r_reg_0),\n .I1(cnt_cmd_done_r),\n .I2(\\init_state_r_reg_n_0_[3] ),\n .I3(Q[1]),\n .I4(Q[0]),\n .I5(\\init_state_r[5]_i_56_n_0 ),\n .O(\\init_state_r[3]_i_18_n_0 ));\n LUT6 #(\n .INIT(64'h0044000000440400)) \n \\init_state_r[3]_i_19 \n (.I0(Q[1]),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .I2(prech_pending_r_reg_0),\n .I3(Q[0]),\n .I4(write_request_r_reg),\n .I5(\\init_state_r[6]_i_22_n_0 ),\n .O(\\init_state_r[3]_i_19_n_0 ));\n LUT6 #(\n .INIT(64'h00FE00FE00FE0000)) \n \\init_state_r[3]_i_2 \n (.I0(\\init_state_r[3]_i_3_n_0 ),\n .I1(\\init_state_r[3]_i_4_n_0 ),\n .I2(\\init_state_r[3]_i_5_n_0 ),\n .I3(\\init_state_r[3]_i_6_n_0 ),\n .I4(complex_oclkdelay_calib_start_int_i_2_n_0),\n .I5(\\init_state_r[3]_i_7_n_0 ),\n .O(\\init_state_r[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF08880800)) \n \\init_state_r[3]_i_20 \n (.I0(Q[1]),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .I2(complex_pi_incdec_done),\n .I3(Q[0]),\n .I4(\\init_state_r[5]_i_36_n_0 ),\n .I5(\\init_state_r[2]_i_7_n_0 ),\n .O(\\init_state_r[3]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'h0000000011014444)) \n \\init_state_r[3]_i_21 \n (.I0(rdlvl_stg1_start_int_i_2_n_0),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .I2(Q[1]),\n .I3(wrlvl_rank_done_r7),\n .I4(Q[2]),\n .I5(\\init_state_r[3]_i_24_n_0 ),\n .O(\\init_state_r[3]_i_21_n_0 ));\n LUT6 #(\n .INIT(64'h0000AFAF0000C000)) \n \\init_state_r[3]_i_22 \n (.I0(\\init_state_r[4]_i_27_n_0 ),\n .I1(Q[1]),\n .I2(Q[2]),\n .I3(Q[0]),\n .I4(read_calib_i_2_n_0),\n .I5(\\init_state_r_reg_n_0_[3] ),\n .O(\\init_state_r[3]_i_22_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair507\" *) \n LUT4 #(\n .INIT(16'h3B30)) \n \\init_state_r[3]_i_23 \n (.I0(complex_oclkdelay_calib_start_int),\n .I1(done_r_reg),\n .I2(prbs_rdlvl_done_reg_rep),\n .I3(prbs_last_byte_done_r),\n .O(\\init_state_r[3]_i_23_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF40434343)) \n \\init_state_r[3]_i_24 \n (.I0(\\init_state_r[2]_i_12_n_0 ),\n .I1(Q[1]),\n .I2(\\init_state_r_reg_n_0_[3] ),\n .I3(cnt_dllk_zqinit_done_r),\n .I4(mem_init_done_r),\n .I5(\\init_state_r[3]_i_25_n_0 ),\n .O(\\init_state_r[3]_i_24_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair521\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\init_state_r[3]_i_25 \n (.I0(Q[2]),\n .I1(Q[0]),\n .O(\\init_state_r[3]_i_25_n_0 ));\n LUT6 #(\n .INIT(64'h08AAAAAA08AA08AA)) \n \\init_state_r[3]_i_3 \n (.I0(\\init_state_r[4]_i_11_n_0 ),\n .I1(cnt_init_af_done_r),\n .I2(mem_init_done_r),\n .I3(mpr_rdlvl_done_r_reg_1),\n .I4(\\init_state_r[4]_i_26_n_0 ),\n .I5(dqs_found_done_r_reg_1),\n .O(\\init_state_r[3]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFDDDD00F0)) \n \\init_state_r[3]_i_4 \n (.I0(\\init_state_r[2]_i_16_n_0 ),\n .I1(\\init_state_r[4]_i_21_n_0 ),\n .I2(\\init_state_r[3]_i_10_n_0 ),\n .I3(\\init_state_r[3]_i_11_n_0 ),\n .I4(Q[2]),\n .I5(rdlvl_start_pre_reg_0),\n .O(\\init_state_r[3]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h0155555505555555)) \n \\init_state_r[3]_i_5 \n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(cnt_cmd_done_r),\n .I2(Q[1]),\n .I3(Q[0]),\n .I4(Q[2]),\n .I5(wrcal_sanity_chk_done_reg),\n .O(\\init_state_r[3]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF0000FF08)) \n \\init_state_r[3]_i_6 \n (.I0(wrcal_done_reg_11),\n .I1(pi_calib_done),\n .I2(Q[1]),\n .I3(\\init_state_r[3]_i_13_n_0 ),\n .I4(\\init_state_r[3]_i_14_n_0 ),\n .I5(\\init_state_r[3]_i_15_n_0 ),\n .O(\\init_state_r[3]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAA2AAAA0AA20)) \n \\init_state_r[3]_i_7 \n (.I0(\\init_state_r[3]_i_16_n_0 ),\n .I1(prbs_gen_oclk_clk_en_i_8_n_0),\n .I2(Q[2]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(\\init_state_r[3]_i_17_n_0 ),\n .I5(\\init_state_r[3]_i_18_n_0 ),\n .O(\\init_state_r[3]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF55550051)) \n \\init_state_r[4]_i_1 \n (.I0(\\init_state_r[4]_i_2_n_0 ),\n .I1(\\init_state_r[4]_i_3_n_0 ),\n .I2(\\init_state_r[4]_i_4_n_0 ),\n .I3(\\init_state_r[4]_i_5_n_0 ),\n .I4(\\init_state_r[4]_i_6_n_0 ),\n .I5(\\init_state_r[4]_i_7_n_0 ),\n .O(\\init_state_r[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAAAA88A888888888)) \n \\init_state_r[4]_i_10 \n (.I0(\\init_state_r[4]_i_22_n_0 ),\n .I1(mem_init_done_r_reg_2),\n .I2(\\init_state_r_reg[2]_0 ),\n .I3(rdlvl_stg1_done_int_reg_3),\n .I4(\\init_state_r[4]_i_26_n_0 ),\n .I5(wrlvl_byte_redo_reg),\n .O(\\init_state_r[4]_i_10_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair562\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\init_state_r[4]_i_11 \n (.I0(cnt_cmd_done_r),\n .I1(Q[1]),\n .I2(Q[0]),\n .O(\\init_state_r[4]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'h0001000DFFFFFFFF)) \n \\init_state_r[4]_i_12 \n (.I0(Q[3]),\n .I1(cnt_cmd_done_r),\n .I2(Q[1]),\n .I3(Q[0]),\n .I4(ddr2_pre_flag_r_reg_0),\n .I5(\\init_state_r_reg[1]_0 ),\n .O(\\init_state_r[4]_i_12_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair578\" *) \n LUT3 #(\n .INIT(8'h8A)) \n \\init_state_r[4]_i_13 \n (.I0(pi_calib_done),\n .I1(wrcal_done_reg_10),\n .I2(dqs_found_done_r_reg),\n .O(\\init_state_r[4]_i_13_n_0 ));\n LUT6 #(\n .INIT(64'hFF540000FF5C000C)) \n \\init_state_r[4]_i_14 \n (.I0(rdlvl_stg1_start_int),\n .I1(\\one_rank.stg1_wr_done_reg_0 ),\n .I2(rdlvl_last_byte_done),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(prbs_rdlvl_done_reg_rep),\n .I5(prbs_last_byte_done),\n .O(\\init_state_r_reg[4]_0 ));\n LUT6 #(\n .INIT(64'h0080000000000000)) \n \\init_state_r[4]_i_15 \n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(\\init_state_r_reg_n_0_[3] ),\n .I3(Q[2]),\n .I4(wrlvl_done_r1),\n .I5(cnt_cmd_done_r),\n .O(\\init_state_r[4]_i_15_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFF01FF01FF01)) \n \\init_state_r[4]_i_16 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .I1(\\init_state_r[4]_i_5_n_0 ),\n .I2(\\init_state_r[4]_i_27_n_0 ),\n .I3(\\init_state_r[4]_i_28_n_0 ),\n .I4(\\init_state_r[4]_i_29_n_0 ),\n .I5(\\init_state_r[5]_i_49_n_0 ),\n .O(\\init_state_r[4]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FF77F7F7)) \n \\init_state_r[4]_i_17 \n (.I0(Q[3]),\n .I1(Q[1]),\n .I2(cnt_cmd_done_r),\n .I3(burst_addr_r_reg_0),\n .I4(Q[0]),\n .I5(\\init_state_r[5]_i_51_n_0 ),\n .O(\\init_state_r[4]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFEAA)) \n \\init_state_r[4]_i_18 \n (.I0(\\init_state_r[4]_i_30_n_0 ),\n .I1(prech_pending_r_reg_0),\n .I2(\\init_state_r[5]_i_13_n_0 ),\n .I3(\\init_state_r_reg[1]_0 ),\n .I4(\\init_state_r[4]_i_31_n_0 ),\n .I5(\\init_state_r[4]_i_32_n_0 ),\n .O(\\init_state_r[4]_i_18_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFEA00)) \n \\init_state_r[4]_i_19 \n (.I0(Q[3]),\n .I1(complex_pi_incdec_done),\n .I2(Q[0]),\n .I3(\\init_state_r[5]_i_19_n_0 ),\n .I4(\\init_state_r[4]_i_33_n_0 ),\n .I5(\\init_state_r[6]_i_12_n_0 ),\n .O(\\init_state_r[4]_i_19_n_0 ));\n LUT6 #(\n .INIT(64'hABABABABAAABAAAA)) \n \\init_state_r[4]_i_2 \n (.I0(\\init_state_r[5]_i_2_n_0 ),\n .I1(\\init_state_r[4]_i_8_n_0 ),\n .I2(\\init_state_r[4]_i_9_n_0 ),\n .I3(\\init_state_r[4]_i_10_n_0 ),\n .I4(\\init_state_r[4]_i_11_n_0 ),\n .I5(\\init_state_r[4]_i_12_n_0 ),\n .O(\\init_state_r[4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h4000000000000000)) \n \\init_state_r[4]_i_20 \n (.I0(ddr3_lm_done_r),\n .I1(wrcal_done_reg_10),\n .I2(dqs_found_done_r_reg),\n .I3(wrlvl_done_r1),\n .I4(prbs_rdlvl_done_reg_rep),\n .I5(rdlvl_stg1_done_int_reg),\n .O(\\init_state_r[4]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000400)) \n \\init_state_r[4]_i_21 \n (.I0(Q[0]),\n .I1(cnt_cmd_done_r),\n .I2(reg_ctrl_cnt_r_reg__0[2]),\n .I3(reg_ctrl_cnt_r_reg__0[3]),\n .I4(reg_ctrl_cnt_r_reg__0[0]),\n .I5(reg_ctrl_cnt_r_reg__0[1]),\n .O(\\init_state_r[4]_i_21_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair494\" *) \n LUT2 #(\n .INIT(4'hB)) \n \\init_state_r[4]_i_22 \n (.I0(mem_init_done_r),\n .I1(cnt_init_af_done_r),\n .O(\\init_state_r[4]_i_22_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair482\" *) \n LUT4 #(\n .INIT(16'hFEFF)) \n \\init_state_r[4]_i_24 \n (.I0(num_refresh_reg__0[1]),\n .I1(num_refresh_reg__0[0]),\n .I2(num_refresh_reg__0[2]),\n .I3(num_refresh_reg__0[3]),\n .O(\\init_state_r_reg[2]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair490\" *) \n LUT4 #(\n .INIT(16'h0800)) \n \\init_state_r[4]_i_26 \n (.I0(mem_init_done_r),\n .I1(dqs_found_done_r_reg),\n .I2(prbs_rdlvl_done_reg_rep),\n .I3(prbs_last_byte_done_r),\n .O(\\init_state_r[4]_i_26_n_0 ));\n LUT6 #(\n .INIT(64'h00FF00AB00FF0000)) \n \\init_state_r[4]_i_27 \n (.I0(cnt_cmd_done_r_reg_1),\n .I1(prech_pending_r_reg_0),\n .I2(oclkdelay_calib_done_r_reg_2),\n .I3(\\init_state_r[5]_i_57_n_0 ),\n .I4(Q[0]),\n .I5(Q[1]),\n .O(\\init_state_r[4]_i_27_n_0 ));\n LUT4 #(\n .INIT(16'hABAA)) \n \\init_state_r[4]_i_28 \n (.I0(Q[3]),\n .I1(read_calib_reg_0),\n .I2(pi_phase_locked_all_r4),\n .I3(pi_phase_locked_all_r3),\n .O(\\init_state_r[4]_i_28_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair533\" *) \n LUT4 #(\n .INIT(16'h0004)) \n \\init_state_r[4]_i_29 \n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(Q[2]),\n .I2(Q[1]),\n .I3(Q[0]),\n .O(\\init_state_r[4]_i_29_n_0 ));\n LUT6 #(\n .INIT(64'h75FF75FF00FFFFFF)) \n \\init_state_r[4]_i_3 \n (.I0(\\init_state_r[4]_i_13_n_0 ),\n .I1(\\init_state_r_reg[4]_0 ),\n .I2(dqs_found_done_r_reg),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .I4(Q[3]),\n .I5(cnt_cmd_done_r),\n .O(\\init_state_r[4]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h4444454445454545)) \n \\init_state_r[4]_i_30 \n (.I0(\\init_state_r[4]_i_5_n_0 ),\n .I1(oclk_calib_resume_r_reg),\n .I2(Q[1]),\n .I3(Q[3]),\n .I4(prbs_gen_oclk_clk_en_i_8_n_0),\n .I5(\\init_state_r[4]_i_37_n_0 ),\n .O(\\init_state_r[4]_i_30_n_0 ));\n LUT6 #(\n .INIT(64'h45004545FFFFFFFF)) \n \\init_state_r[4]_i_31 \n (.I0(oclk_calib_resume_level_reg_0),\n .I1(\\init_state_r[5]_i_56_n_0 ),\n .I2(Q[1]),\n .I3(\\init_state_r[6]_i_18_n_0 ),\n .I4(oclkdelay_center_calib_start_r_reg),\n .I5(Q[3]),\n .O(\\init_state_r[4]_i_31_n_0 ));\n LUT6 #(\n .INIT(64'h2828282828282800)) \n \\init_state_r[4]_i_32 \n (.I0(\\init_state_r[4]_i_38_n_0 ),\n .I1(Q[2]),\n .I2(\\init_state_r_reg_n_0_[3] ),\n .I3(prbs_gen_oclk_clk_en_i_8_n_0),\n .I4(\\init_state_r[4]_i_39_n_0 ),\n .I5(Q[3]),\n .O(\\init_state_r[4]_i_32_n_0 ));\n LUT6 #(\n .INIT(64'hFF00060000000000)) \n \\init_state_r[4]_i_33 \n (.I0(Q[0]),\n .I1(write_request_r_reg),\n .I2(Q[1]),\n .I3(Q[3]),\n .I4(Q[2]),\n .I5(Q[5]),\n .O(\\init_state_r[4]_i_33_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair485\" *) \n LUT5 #(\n .INIT(32'h2022FFFF)) \n \\init_state_r[4]_i_37 \n (.I0(complex_sample_cnt_inc_i_2_n_0),\n .I1(prech_pending_r_reg_0),\n .I2(complex_oclkdelay_calib_done_r1),\n .I3(prbs_rdlvl_done_reg),\n .I4(Q[0]),\n .O(\\init_state_r[4]_i_37_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFD00)) \n \\init_state_r[4]_i_38 \n (.I0(\\init_state_r[5]_i_54_n_0 ),\n .I1(\\init_state_r[4]_i_40_n_0 ),\n .I2(prech_pending_r_reg_0),\n .I3(Q[0]),\n .I4(\\init_state_r[6]_i_23_n_0 ),\n .I5(\\init_state_r_reg[1]_0 ),\n .O(\\init_state_r[4]_i_38_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair545\" *) \n LUT4 #(\n .INIT(16'hF4FF)) \n \\init_state_r[4]_i_39 \n (.I0(prbs_rdlvl_done_r1),\n .I1(prbs_rdlvl_done_reg),\n .I2(Q[1]),\n .I3(Q[0]),\n .O(\\init_state_r[4]_i_39_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAFFFFAAAABBFA)) \n \\init_state_r[4]_i_4 \n (.I0(\\init_state_r[5]_i_12_n_0 ),\n .I1(rdlvl_stg1_done_r1),\n .I2(Q[3]),\n .I3(cnt_cmd_done_r),\n .I4(prbs_rdlvl_start_i_2_n_0),\n .I5(reset_rd_addr_r1),\n .O(\\init_state_r[4]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair505\" *) \n LUT5 #(\n .INIT(32'h2AAAAAAA)) \n \\init_state_r[4]_i_40 \n (.I0(Q[3]),\n .I1(complex_wait_cnt_reg__0[3]),\n .I2(complex_wait_cnt_reg__0[2]),\n .I3(complex_wait_cnt_reg__0[1]),\n .I4(complex_wait_cnt_reg__0[0]),\n .O(\\init_state_r[4]_i_40_n_0 ));\n LUT2 #(\n .INIT(4'h7)) \n \\init_state_r[4]_i_5 \n (.I0(Q[2]),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .O(\\init_state_r[4]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF0400)) \n \\init_state_r[4]_i_6 \n (.I0(oclk_calib_resume_level_reg_0),\n .I1(cnt_cmd_done_r),\n .I2(prbs_rdlvl_start_i_2_n_0),\n .I3(dqs_found_done_r_reg_0),\n .I4(\\init_state_r[4]_i_15_n_0 ),\n .I5(Q[3]),\n .O(\\init_state_r[4]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF44450000)) \n \\init_state_r[4]_i_7 \n (.I0(\\init_state_r[5]_i_26_n_0 ),\n .I1(\\init_state_r[4]_i_16_n_0 ),\n .I2(oclk_calib_resume_level_reg_0),\n .I3(\\init_state_r[4]_i_17_n_0 ),\n .I4(\\init_state_r[4]_i_18_n_0 ),\n .I5(\\init_state_r[4]_i_19_n_0 ),\n .O(\\init_state_r[4]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hA2AAA200AAAAAAAA)) \n \\init_state_r[4]_i_8 \n (.I0(\\wrcal_reads[7]_i_5_n_0 ),\n .I1(\\init_state_r[4]_i_20_n_0 ),\n .I2(wrcal_sanity_chk_done_reg_0),\n .I3(cnt_cmd_done_r),\n .I4(Q[3]),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .O(\\init_state_r[4]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'h57DF55555555FFFF)) \n \\init_state_r[4]_i_9 \n (.I0(Q[3]),\n .I1(Q[1]),\n .I2(\\init_state_r[4]_i_21_n_0 ),\n .I3(Q[0]),\n .I4(\\init_state_r_reg_n_0_[3] ),\n .I5(Q[2]),\n .O(\\init_state_r[4]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF1110)) \n \\init_state_r[5]_i_1 \n (.I0(\\init_state_r[5]_i_2_n_0 ),\n .I1(\\init_state_r[5]_i_3_n_0 ),\n .I2(\\init_state_r[5]_i_4_n_0 ),\n .I3(\\init_state_r[5]_i_5_n_0 ),\n .I4(\\init_state_r[5]_i_6_n_0 ),\n .I5(\\init_state_r[5]_i_7_n_0 ),\n .O(\\init_state_r[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF0000AA10)) \n \\init_state_r[5]_i_10 \n (.I0(Q[1]),\n .I1(cnt_cmd_done_r),\n .I2(Q[4]),\n .I3(Q[0]),\n .I4(\\init_state_r[4]_i_5_n_0 ),\n .I5(\\init_state_r[5]_i_31_n_0 ),\n .O(\\init_state_r[5]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'h00000000002A0000)) \n \\init_state_r[5]_i_11 \n (.I0(\\init_state_r[1]_i_10_n_0 ),\n .I1(cnt_cmd_done_r),\n .I2(Q[1]),\n .I3(oclk_calib_resume_level_reg_0),\n .I4(Q[4]),\n .I5(\\init_state_r[1]_i_11_n_0 ),\n .O(\\init_state_r[5]_i_11_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair483\" *) \n LUT5 #(\n .INIT(32'h02220202)) \n \\init_state_r[5]_i_12 \n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(\\init_state_r[5]_i_32_n_0 ),\n .I3(complex_sample_cnt_inc_i_2_n_0),\n .I4(rdlvl_stg1_done_r1),\n .O(\\init_state_r[5]_i_12_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair500\" *) \n LUT5 #(\n .INIT(32'h00000010)) \n \\init_state_r[5]_i_13 \n (.I0(wr_victim_inc_i_3_n_0),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[5] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[0] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[1] ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[2] ),\n .O(\\init_state_r[5]_i_13_n_0 ));\n LUT6 #(\n .INIT(64'h7500FFFF75007500)) \n \\init_state_r[5]_i_14 \n (.I0(pi_calib_done),\n .I1(wrcal_done_reg_10),\n .I2(dqs_found_done_r_reg),\n .I3(\\init_state_r[5]_i_33_n_0 ),\n .I4(prbs_rdlvl_start_i_2_n_0),\n .I5(reset_rd_addr_r1),\n .O(\\init_state_r[5]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'h00000000000FCDCD)) \n \\init_state_r[5]_i_15 \n (.I0(cnt_txpr_done_r),\n .I1(\\init_state_r[5]_i_34_n_0 ),\n .I2(\\init_state_r[5]_i_16_n_0 ),\n .I3(cnt_cmd_done_r),\n .I4(Q[1]),\n .I5(oclk_calib_resume_level_reg_0),\n .O(\\init_state_r[5]_i_15_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair524\" *) \n LUT2 #(\n .INIT(4'h7)) \n \\init_state_r[5]_i_16 \n (.I0(Q[4]),\n .I1(Q[0]),\n .O(\\init_state_r[5]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'h0000000040700000)) \n \\init_state_r[5]_i_17 \n (.I0(wrlvl_rank_done_r7),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(cnt_dllk_zqinit_done_r),\n .I4(\\init_state_r[5]_i_35_n_0 ),\n .I5(\\init_state_r_reg_n_0_[3] ),\n .O(\\init_state_r[5]_i_17_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\init_state_r[5]_i_18 \n (.I0(Q[0]),\n .I1(complex_pi_incdec_done),\n .O(\\init_state_r[5]_i_18_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair521\" *) \n LUT5 #(\n .INIT(32'h00E00000)) \n \\init_state_r[5]_i_19 \n (.I0(\\init_state_r[5]_i_36_n_0 ),\n .I1(Q[0]),\n .I2(Q[5]),\n .I3(Q[2]),\n .I4(Q[1]),\n .O(\\init_state_r[5]_i_19_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\init_state_r[5]_i_2 \n (.I0(Q[5]),\n .I1(Q[4]),\n .O(\\init_state_r[5]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hBFBF15B7FFFFFFFF)) \n \\init_state_r[5]_i_20 \n (.I0(Q[0]),\n .I1(Q[4]),\n .I2(write_request_r_reg),\n .I3(\\init_state_r[6]_i_22_n_0 ),\n .I4(prech_pending_r_reg_0),\n .I5(\\init_state_r[5]_i_38_n_0 ),\n .O(\\init_state_r[5]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'h444F44444F4F4F4F)) \n \\init_state_r[5]_i_21 \n (.I0(\\init_state_r[5]_i_39_n_0 ),\n .I1(\\init_state_r[5]_i_40_n_0 ),\n .I2(\\init_state_r[5]_i_41_n_0 ),\n .I3(prbs_gen_oclk_clk_en_i_8_n_0),\n .I4(Q[4]),\n .I5(\\init_state_r[5]_i_42_n_0 ),\n .O(\\init_state_r[5]_i_21_n_0 ));\n LUT6 #(\n .INIT(64'h0808080888888808)) \n \\init_state_r[5]_i_22 \n (.I0(\\init_state_r[5]_i_43_n_0 ),\n .I1(\\wrcal_reads[7]_i_5_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .I3(Q[4]),\n .I4(prbs_gen_oclk_clk_en_i_8_n_0),\n .I5(prbs_rdlvl_done_pulse0),\n .O(\\init_state_r[5]_i_22_n_0 ));\n LUT6 #(\n .INIT(64'h4F4F4F4FFF4F4F4F)) \n \\init_state_r[5]_i_23 \n (.I0(\\init_state_r[5]_i_44_n_0 ),\n .I1(\\init_state_r[5]_i_45_n_0 ),\n .I2(Q[3]),\n .I3(\\init_state_r_reg[5]_0 ),\n .I4(Q[4]),\n .I5(oclk_calib_resume_r_reg_0),\n .O(\\init_state_r[5]_i_23_n_0 ));\n LUT6 #(\n .INIT(64'h44455555FFFFFFFF)) \n \\init_state_r[5]_i_24 \n (.I0(\\init_state_r[5]_i_48_n_0 ),\n .I1(\\init_state_r[5]_i_49_n_0 ),\n .I2(Q[4]),\n .I3(wrcal_resume_r),\n .I4(\\wrcal_reads[7]_i_6_n_0 ),\n .I5(\\wrcal_reads[7]_i_5_n_0 ),\n .O(\\init_state_r[5]_i_24_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFEEEEEFEE)) \n \\init_state_r[5]_i_25 \n (.I0(\\init_state_r[5]_i_50_n_0 ),\n .I1(Q[3]),\n .I2(\\init_state_r[5]_i_51_n_0 ),\n .I3(Q[4]),\n .I4(oclk_calib_resume_level_reg_0),\n .I5(\\init_state_r[5]_i_52_n_0 ),\n .O(\\init_state_r[5]_i_25_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair547\" *) \n LUT2 #(\n .INIT(4'hB)) \n \\init_state_r[5]_i_26 \n (.I0(Q[5]),\n .I1(Q[4]),\n .O(\\init_state_r[5]_i_26_n_0 ));\n LUT6 #(\n .INIT(64'h00000000000000D0)) \n \\init_state_r[5]_i_27 \n (.I0(cnt_init_af_done_r),\n .I1(mem_init_done_r),\n .I2(num_refresh_reg__0[3]),\n .I3(num_refresh_reg__0[2]),\n .I4(num_refresh_reg__0[0]),\n .I5(num_refresh_reg__0[1]),\n .O(\\init_state_r[5]_i_27_n_0 ));\n LUT6 #(\n .INIT(64'h44FEFFFF44EEFFFF)) \n \\init_state_r[5]_i_29 \n (.I0(rdlvl_stg1_done_int_reg),\n .I1(wrcal_done_reg_10),\n .I2(prbs_last_byte_done_r),\n .I3(prbs_rdlvl_done_reg_rep),\n .I4(dqs_found_done_r_reg),\n .I5(mem_init_done_r),\n .O(\\init_state_r[5]_i_29_n_0 ));\n LUT6 #(\n .INIT(64'h000000000000D5DD)) \n \\init_state_r[5]_i_3 \n (.I0(\\init_state_r_reg[1]_0 ),\n .I1(\\init_state_r[5]_i_8_n_0 ),\n .I2(cnt_cmd_done_r),\n .I3(\\init_state_r[5]_i_9_n_0 ),\n .I4(\\init_state_r[5]_i_10_n_0 ),\n .I5(\\init_state_r[5]_i_11_n_0 ),\n .O(\\init_state_r[5]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h00010000FFFFFFFF)) \n \\init_state_r[5]_i_31 \n (.I0(cnt_cmd_done_r),\n .I1(\\init_state_r[5]_i_16_n_0 ),\n .I2(Q[1]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[2]),\n .I5(Q[3]),\n .O(\\init_state_r[5]_i_31_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFBFFFFFFFFFF)) \n \\init_state_r[5]_i_32 \n (.I0(\\complex_num_writes_dec[4]_i_5_n_0 ),\n .I1(rdlvl_stg1_done_r1),\n .I2(complex_row0_wr_done),\n .I3(prbs_rdlvl_done_reg_rep),\n .I4(complex_num_writes_dec_reg__0[1]),\n .I5(complex_num_writes_dec_reg__0[0]),\n .O(\\init_state_r[5]_i_32_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair529\" *) \n LUT3 #(\n .INIT(8'h20)) \n \\init_state_r[5]_i_33 \n (.I0(cnt_cmd_done_r),\n .I1(Q[1]),\n .I2(Q[0]),\n .O(\\init_state_r[5]_i_33_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair524\" *) \n LUT5 #(\n .INIT(32'h04444444)) \n \\init_state_r[5]_i_34 \n (.I0(Q[0]),\n .I1(Q[4]),\n .I2(\\mcGo_r_reg[15] ),\n .I3(cnt_pwron_cke_done_r),\n .I4(ck_addr_cmd_delay_done),\n .O(\\init_state_r[5]_i_34_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair519\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\init_state_r[5]_i_35 \n (.I0(Q[4]),\n .I1(Q[2]),\n .O(\\init_state_r[5]_i_35_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair535\" *) \n LUT4 #(\n .INIT(16'h7FFF)) \n \\init_state_r[5]_i_36 \n (.I0(ocal_act_wait_cnt_reg__0[2]),\n .I1(ocal_act_wait_cnt_reg__0[1]),\n .I2(ocal_act_wait_cnt_reg__0[0]),\n .I3(ocal_act_wait_cnt_reg__0[3]),\n .O(\\init_state_r[5]_i_36_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair574\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\init_state_r[5]_i_38 \n (.I0(Q[2]),\n .I1(Q[1]),\n .O(\\init_state_r[5]_i_38_n_0 ));\n LUT6 #(\n .INIT(64'h0000444FFFFFFFFF)) \n \\init_state_r[5]_i_39 \n (.I0(prbs_rdlvl_done_r1),\n .I1(prbs_rdlvl_done_reg),\n .I2(prbs_gen_oclk_clk_en_i_8_n_0),\n .I3(Q[4]),\n .I4(complex_oclkdelay_calib_start_int_reg_0),\n .I5(\\init_state_r[5]_i_53_n_0 ),\n .O(\\init_state_r[5]_i_39_n_0 ));\n LUT6 #(\n .INIT(64'h5555555544444544)) \n \\init_state_r[5]_i_4 \n (.I0(\\init_state_r[4]_i_5_n_0 ),\n .I1(\\init_state_r[5]_i_12_n_0 ),\n .I2(complex_oclkdelay_calib_start_int_reg_0),\n .I3(Q[4]),\n .I4(\\init_state_r[5]_i_13_n_0 ),\n .I5(\\init_state_r[5]_i_14_n_0 ),\n .O(\\init_state_r[5]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFE2)) \n \\init_state_r[5]_i_40 \n (.I0(\\init_state_r[0]_i_27_n_0 ),\n .I1(Q[0]),\n .I2(prbs_gen_oclk_clk_en_i_8_n_0),\n .I3(Q[4]),\n .I4(Q[1]),\n .I5(\\init_state_r[5]_i_13_n_0 ),\n .O(\\init_state_r[5]_i_40_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFEEEEAAEA)) \n \\init_state_r[5]_i_41 \n (.I0(\\init_state_r[4]_i_5_n_0 ),\n .I1(Q[0]),\n .I2(prbs_rdlvl_done_reg),\n .I3(complex_oclkdelay_calib_done_r1),\n .I4(prech_pending_r_reg_0),\n .I5(Q[1]),\n .O(\\init_state_r[5]_i_41_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair485\" *) \n LUT2 #(\n .INIT(4'hB)) \n \\init_state_r[5]_i_42 \n (.I0(complex_sample_cnt_inc_i_2_n_0),\n .I1(Q[0]),\n .O(\\init_state_r[5]_i_42_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAABFBBAAAA)) \n \\init_state_r[5]_i_43 \n (.I0(\\init_state_r[6]_i_23_n_0 ),\n .I1(\\init_state_r[5]_i_54_n_0 ),\n .I2(prbs_gen_oclk_clk_en_i_8_n_0),\n .I3(Q[4]),\n .I4(Q[0]),\n .I5(prech_pending_r_reg_0),\n .O(\\init_state_r[5]_i_43_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF03000101)) \n \\init_state_r[5]_i_44 \n (.I0(Q[4]),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(oclkdelay_int_ref_req_reg_0),\n .I4(cnt_cmd_done_r),\n .I5(oclk_calib_resume_level_reg_0),\n .O(\\init_state_r[5]_i_44_n_0 ));\n LUT6 #(\n .INIT(64'h3373F373FFFFFFFF)) \n \\init_state_r[5]_i_45 \n (.I0(oclkdelay_center_calib_start_r_reg_0),\n .I1(\\init_state_r[5]_i_56_n_0 ),\n .I2(Q[4]),\n .I3(Q[0]),\n .I4(cnt_cmd_done_r),\n .I5(Q[1]),\n .O(\\init_state_r[5]_i_45_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair533\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\init_state_r[5]_i_46 \n (.I0(Q[0]),\n .I1(Q[2]),\n .I2(Q[1]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .O(\\init_state_r_reg[5]_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFE8E8C8E8)) \n \\init_state_r[5]_i_48 \n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(Q[4]),\n .I3(pi_phase_locked_all_r3),\n .I4(pi_phase_locked_all_r4),\n .I5(\\init_state_r[0]_i_25_n_0 ),\n .O(\\init_state_r[5]_i_48_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair531\" *) \n LUT4 #(\n .INIT(16'h5554)) \n \\init_state_r[5]_i_49 \n (.I0(wrcal_resume_r),\n .I1(wrcal_done_reg_10),\n .I2(prech_pending_r_reg_0),\n .I3(wrlvl_byte_redo),\n .O(\\init_state_r[5]_i_49_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFEEEEEFEE)) \n \\init_state_r[5]_i_5 \n (.I0(\\init_state_r[5]_i_15_n_0 ),\n .I1(Q[3]),\n .I2(\\init_state_r[5]_i_16_n_0 ),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(cnt_cmd_done_r),\n .I5(\\init_state_r[5]_i_17_n_0 ),\n .O(\\init_state_r[5]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h00000000EEEEFEEE)) \n \\init_state_r[5]_i_50 \n (.I0(\\init_state_r[5]_i_57_n_0 ),\n .I1(\\init_state_r[5]_i_58_n_0 ),\n .I2(Q[1]),\n .I3(Q[4]),\n .I4(oclkdelay_calib_done_r_reg_3),\n .I5(\\init_state_r[5]_i_60_n_0 ),\n .O(\\init_state_r[5]_i_50_n_0 ));\n LUT6 #(\n .INIT(64'h0054000000540054)) \n \\init_state_r[5]_i_51 \n (.I0(Q[1]),\n .I1(wrcal_done_reg_10),\n .I2(prech_pending_r_reg_0),\n .I3(Q[0]),\n .I4(wrcal_prech_req),\n .I5(cnt_cmd_done_r),\n .O(\\init_state_r[5]_i_51_n_0 ));\n LUT6 #(\n .INIT(64'h00000000F2F200F2)) \n \\init_state_r[5]_i_52 \n (.I0(\\init_state_r[5]_i_61_n_0 ),\n .I1(wrcal_prech_req),\n .I2(\\init_state_r[1]_i_20_n_0 ),\n .I3(Q[1]),\n .I4(\\init_state_r[5]_i_62_n_0 ),\n .I5(oclk_calib_resume_level_reg_0),\n .O(\\init_state_r[5]_i_52_n_0 ));\n LUT6 #(\n .INIT(64'h4044404040444044)) \n \\init_state_r[5]_i_53 \n (.I0(Q[2]),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .I2(Q[1]),\n .I3(prech_pending_r_reg_0),\n .I4(prbs_rdlvl_done_r1),\n .I5(prbs_rdlvl_done_reg),\n .O(\\init_state_r[5]_i_53_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF00BFFFFFFFFF)) \n \\init_state_r[5]_i_54 \n (.I0(complex_row1_wr_done),\n .I1(complex_ocal_num_samples_done_r),\n .I2(complex_oclkdelay_calib_start_int),\n .I3(\\one_rank.stg1_wr_done_reg_0 ),\n .I4(oclkdelay_center_calib_start_r_reg),\n .I5(prbs_gen_oclk_clk_en_i_8_n_0),\n .O(\\init_state_r[5]_i_54_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair534\" *) \n LUT4 #(\n .INIT(16'hEEEF)) \n \\init_state_r[5]_i_56 \n (.I0(oclkdelay_int_ref_req_reg_0),\n .I1(Q[0]),\n .I2(complex_oclk_calib_resume),\n .I3(oclk_calib_resume_level),\n .O(\\init_state_r[5]_i_56_n_0 ));\n LUT6 #(\n .INIT(64'h0004000000000000)) \n \\init_state_r[5]_i_57 \n (.I0(oclk_wr_cnt_reg__0[2]),\n .I1(oclk_wr_cnt_reg__0[0]),\n .I2(oclk_wr_cnt_reg__0[1]),\n .I3(oclk_wr_cnt_reg__0[3]),\n .I4(Q[1]),\n .I5(Q[0]),\n .O(\\init_state_r[5]_i_57_n_0 ));\n LUT6 #(\n .INIT(64'h5D5D5D5D5D5D7D5D)) \n \\init_state_r[5]_i_58 \n (.I0(Q[2]),\n .I1(Q[0]),\n .I2(Q[1]),\n .I3(cnt_cmd_done_r),\n .I4(lim2init_prech_req),\n .I5(ocd_prech_req),\n .O(\\init_state_r[5]_i_58_n_0 ));\n LUT6 #(\n .INIT(64'hFFCF8F8FCCCC8888)) \n \\init_state_r[5]_i_6 \n (.I0(\\init_state_r[5]_i_18_n_0 ),\n .I1(\\init_state_r[5]_i_19_n_0 ),\n .I2(\\init_state_r[5]_i_20_n_0 ),\n .I3(Q[2]),\n .I4(Q[4]),\n .I5(Q[5]),\n .O(\\init_state_r[5]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h000000F1FFFFFFFF)) \n \\init_state_r[5]_i_60 \n (.I0(cnt_cmd_done_r),\n .I1(Q[0]),\n .I2(\\init_state_r_reg[1]_1 ),\n .I3(Q[4]),\n .I4(Q[2]),\n .I5(\\init_state_r_reg_n_0_[3] ),\n .O(\\init_state_r[5]_i_60_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair536\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\init_state_r[5]_i_61 \n (.I0(cnt_cmd_done_r),\n .I1(Q[0]),\n .O(\\init_state_r[5]_i_61_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair576\" *) \n LUT3 #(\n .INIT(8'hCA)) \n \\init_state_r[5]_i_62 \n (.I0(cnt_cmd_done_r),\n .I1(burst_addr_r_reg_0),\n .I2(Q[0]),\n .O(\\init_state_r[5]_i_62_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FEFE00FE)) \n \\init_state_r[5]_i_7 \n (.I0(\\init_state_r[5]_i_21_n_0 ),\n .I1(\\init_state_r[5]_i_22_n_0 ),\n .I2(\\init_state_r[5]_i_23_n_0 ),\n .I3(\\init_state_r[5]_i_24_n_0 ),\n .I4(\\init_state_r[5]_i_25_n_0 ),\n .I5(\\init_state_r[5]_i_26_n_0 ),\n .O(\\init_state_r[5]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF5FFFDFDFDFDF)) \n \\init_state_r[5]_i_8 \n (.I0(\\init_state_r[4]_i_11_n_0 ),\n .I1(oclkdelay_calib_done_r_reg_2),\n .I2(\\init_state_r[5]_i_27_n_0 ),\n .I3(wrlvl_byte_redo_reg),\n .I4(\\init_state_r[5]_i_29_n_0 ),\n .I5(mpr_rdlvl_done_r_reg_2),\n .O(\\init_state_r[5]_i_8_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair594\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\init_state_r[5]_i_9 \n (.I0(Q[4]),\n .I1(Q[0]),\n .O(\\init_state_r[5]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hAAAA20AAAAAAAAAA)) \n \\init_state_r[6]_i_10 \n (.I0(\\init_state_r[6]_i_20_n_0 ),\n .I1(prbs_rdlvl_done_r1),\n .I2(prbs_rdlvl_done_reg),\n .I3(Q[5]),\n .I4(prbs_gen_oclk_clk_en_i_8_n_0),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .O(\\init_state_r[6]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'h0100000000000000)) \n \\init_state_r[6]_i_11 \n (.I0(\\init_state_r[4]_i_5_n_0 ),\n .I1(Q[4]),\n .I2(ddr3_lm_done_r_i_2_n_0),\n .I3(\\init_state_r[6]_i_21_n_0 ),\n .I4(cnt_cmd_done_r),\n .I5(rdlvl_stg1_done_r1),\n .O(\\init_state_r[6]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'h0020002000200000)) \n \\init_state_r[6]_i_12 \n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(Q[5]),\n .I3(Q[2]),\n .I4(\\init_state_r[6]_i_22_n_0 ),\n .I5(prech_pending_r_reg_0),\n .O(\\init_state_r[6]_i_12_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair526\" *) \n LUT4 #(\n .INIT(16'hAA08)) \n \\init_state_r[6]_i_13 \n (.I0(Q[0]),\n .I1(prbs_rdlvl_done_reg_rep),\n .I2(complex_oclkdelay_calib_done_r1),\n .I3(prech_pending_r_reg_0),\n .O(\\init_state_r[6]_i_13_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair547\" *) \n LUT4 #(\n .INIT(16'hFF4F)) \n \\init_state_r[6]_i_14 \n (.I0(prbs_rdlvl_done_r1),\n .I1(prbs_rdlvl_done_reg),\n .I2(Q[5]),\n .I3(prbs_gen_oclk_clk_en_i_8_n_0),\n .O(\\init_state_r[6]_i_14_n_0 ));\n LUT4 #(\n .INIT(16'hFFAE)) \n \\init_state_r[6]_i_15 \n (.I0(\\init_state_r[5]_i_13_n_0 ),\n .I1(prbs_rdlvl_done_reg),\n .I2(prbs_rdlvl_done_r1),\n .I3(prech_pending_r_reg_0),\n .O(\\init_state_r[6]_i_15_n_0 ));\n LUT6 #(\n .INIT(64'h8000FFFF80000000)) \n \\init_state_r[6]_i_16 \n (.I0(complex_wait_cnt_reg__0[0]),\n .I1(complex_wait_cnt_reg__0[1]),\n .I2(complex_wait_cnt_reg__0[2]),\n .I3(complex_wait_cnt_reg__0[3]),\n .I4(Q[0]),\n .I5(\\init_state_r[0]_i_27_n_0 ),\n .O(\\init_state_r[6]_i_16_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair534\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\init_state_r[6]_i_17 \n (.I0(oclk_calib_resume_level),\n .I1(complex_oclk_calib_resume),\n .O(\\init_state_r[6]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFD)) \n \\init_state_r[6]_i_18 \n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(wrlvl_final_mux),\n .I3(oclkdelay_int_ref_req_reg_0),\n .I4(prech_pending_r_reg_0),\n .I5(oclkdelay_calib_done_r_reg_2),\n .O(\\init_state_r[6]_i_18_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair506\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\init_state_r[6]_i_19 \n (.I0(Q[0]),\n .I1(Q[1]),\n .O(\\init_state_r[6]_i_19_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF00D00000)) \n \\init_state_r[6]_i_2 \n (.I0(\\init_state_r[6]_i_3_n_0 ),\n .I1(\\init_state_r[6]_i_4_n_0 ),\n .I2(Q[4]),\n .I3(Q[5]),\n .I4(Q[3]),\n .I5(\\init_state_r[6]_i_5_n_0 ),\n .O(\\init_state_r[6]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFABFB0000)) \n \\init_state_r[6]_i_20 \n (.I0(prech_pending_r_reg_0),\n .I1(Q[5]),\n .I2(prbs_gen_oclk_clk_en_i_8_n_0),\n .I3(oclkdelay_center_calib_start_r_reg),\n .I4(Q[0]),\n .I5(\\init_state_r[6]_i_23_n_0 ),\n .O(\\init_state_r[6]_i_20_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair541\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\init_state_r[6]_i_21 \n (.I0(Q[0]),\n .I1(reset_rd_addr_r1),\n .O(\\init_state_r[6]_i_21_n_0 ));\n LUT4 #(\n .INIT(16'h0004)) \n \\init_state_r[6]_i_22 \n (.I0(mask_lim_done),\n .I1(done_r_reg),\n .I2(complex_mask_lim_done),\n .I3(oclkdelay_center_calib_start_r_reg),\n .O(\\init_state_r[6]_i_22_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair506\" *) \n LUT5 #(\n .INIT(32'h37773737)) \n \\init_state_r[6]_i_23 \n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(prbs_rdlvl_start_r_reg),\n .I3(num_samples_done_r),\n .I4(complex_init_pi_dec_done),\n .O(\\init_state_r[6]_i_23_n_0 ));\n LUT6 #(\n .INIT(64'hFBFBFBFAFBFBFBFB)) \n \\init_state_r[6]_i_3 \n (.I0(\\init_state_r[6]_i_6_n_0 ),\n .I1(complex_oclkdelay_calib_start_int_reg_0),\n .I2(\\init_state_r[4]_i_5_n_0 ),\n .I3(prbs_rdlvl_done_reg_rep_0),\n .I4(complex_oclk_calib_resume),\n .I5(Q[5]),\n .O(\\init_state_r[6]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0503FFFF05F3FFFF)) \n \\init_state_r[6]_i_4 \n (.I0(\\init_state_r[6]_i_8_n_0 ),\n .I1(\\init_state_r[6]_i_9_n_0 ),\n .I2(Q[2]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[3]),\n .I5(\\init_state_r[6]_i_10_n_0 ),\n .O(\\init_state_r[6]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FAFACAFA)) \n \\init_state_r[6]_i_5 \n (.I0(\\init_state_r[6]_i_11_n_0 ),\n .I1(Q[2]),\n .I2(Q[5]),\n .I3(complex_pi_incdec_done),\n .I4(prbs_rdlvl_start_i_2_n_0),\n .I5(\\init_state_r[6]_i_12_n_0 ),\n .O(\\init_state_r[6]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h5555555545455545)) \n \\init_state_r[6]_i_6 \n (.I0(Q[1]),\n .I1(prbs_gen_oclk_clk_en_i_8_n_0),\n .I2(Q[5]),\n .I3(Q[0]),\n .I4(complex_sample_cnt_inc_i_2_n_0),\n .I5(\\init_state_r[6]_i_13_n_0 ),\n .O(\\init_state_r[6]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hEEEEFFFFEEEEF0FF)) \n \\init_state_r[6]_i_8 \n (.I0(\\init_state_r[6]_i_14_n_0 ),\n .I1(Q[0]),\n .I2(\\init_state_r[6]_i_15_n_0 ),\n .I3(Q[5]),\n .I4(Q[1]),\n .I5(\\init_state_r[6]_i_16_n_0 ),\n .O(\\init_state_r[6]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'hFAFAFBFBFA00FBFB)) \n \\init_state_r[6]_i_9 \n (.I0(\\init_state_r[6]_i_17_n_0 ),\n .I1(oclkdelay_center_calib_start_r_reg),\n .I2(\\init_state_r[6]_i_18_n_0 ),\n .I3(\\init_state_r[6]_i_19_n_0 ),\n .I4(Q[5]),\n .I5(cnt_cmd_done_r),\n .O(\\init_state_r[6]_i_9_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\init_state_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\init_state_r[0]_i_1_n_0 ),\n .Q(Q[0]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE #(\n .INIT(1'b0)) \n \\init_state_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\init_state_r[1]_i_1_n_0 ),\n .Q(Q[1]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE #(\n .INIT(1'b0)) \n \\init_state_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\init_state_r[2]_i_1_n_0 ),\n .Q(Q[2]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE #(\n .INIT(1'b0)) \n \\init_state_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\init_state_r[3]_i_1_n_0 ),\n .Q(\\init_state_r_reg_n_0_[3] ),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE #(\n .INIT(1'b0)) \n \\init_state_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\init_state_r[4]_i_1_n_0 ),\n .Q(Q[3]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE #(\n .INIT(1'b0)) \n \\init_state_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\init_state_r[5]_i_1_n_0 ),\n .Q(Q[4]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE #(\n .INIT(1'b0)) \n \\init_state_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\init_state_r[6]_i_2_n_0 ),\n .Q(Q[5]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n (* SOFT_HLUTNM = \"soft_lutpair605\" *) \n LUT2 #(\n .INIT(4'h2)) \n lim_start_r_i_3\n (.I0(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .I1(oclkdelay_calib_done_r_reg_2),\n .O(lim_start_r_reg));\n LUT4 #(\n .INIT(16'h000E)) \n mask_lim_done_i_1\n (.I0(mask_lim_done),\n .I1(prech_pending_r),\n .I2(prech_done_r3),\n .I3(rstdiv0_sync_r1_reg_rep__24),\n .O(mask_lim_done_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n mask_lim_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mask_lim_done_i_1_n_0),\n .Q(mask_lim_done),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hFFFF4000)) \n mem_init_done_r_i_1\n (.I0(cnt_dllk_zqinit_done_r),\n .I1(mem_init_done_r_reg_0[1]),\n .I2(mem_init_done_r_reg_1),\n .I3(mem_init_done_r_reg_0[0]),\n .I4(mem_init_done_r),\n .O(mem_init_done_r_i_1_n_0));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n mem_init_done_r_i_2\n (.I0(cnt_dllk_zqinit_r_reg__0[5]),\n .I1(cnt_dllk_zqinit_r_reg__0[3]),\n .I2(cnt_dllk_zqinit_r_reg__0[1]),\n .I3(cnt_dllk_zqinit_r_reg__0[0]),\n .I4(cnt_dllk_zqinit_r_reg__0[2]),\n .I5(cnt_dllk_zqinit_r_reg__0[4]),\n .O(mem_init_done_r_reg_1));\n FDRE #(\n .INIT(1'b0)) \n mem_init_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mem_init_done_r_i_1_n_0),\n .Q(mem_init_done_r),\n .R(rstdiv0_sync_r1_reg_rep__11));\n LUT3 #(\n .INIT(8'hB8)) \n mem_reg_0_15_0_5_i_1\n (.I0(mc_cas_n),\n .I1(init_calib_complete_reg_rep__14),\n .I2(phy_cs_n),\n .O(\\rd_ptr_timing_reg[0]_3 [0]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_0_5_i_2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [63]),\n .I1(phy_wrdata[63]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_41 [1]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_0_5_i_3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [31]),\n .I1(phy_wrdata[31]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_41 [0]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_0_5_i_4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [127]),\n .I1(phy_wrdata[127]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_41 [3]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_0_5_i_5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [95]),\n .I1(phy_wrdata[95]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_41 [2]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_0_5_i_6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [191]),\n .I1(phy_wrdata[191]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_41 [5]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_0_5_i_7\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [159]),\n .I1(phy_wrdata[159]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_41 [4]));\n LUT3 #(\n .INIT(8'hB8)) \n mem_reg_0_15_12_17_i_1\n (.I0(mc_cas_n),\n .I1(init_calib_complete_reg_rep__14),\n .I2(phy_cas_n),\n .O(\\rd_ptr_timing_reg[0] [0]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_1__0\n (.I0(mc_address[16]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(phy_dout[5]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_1__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [167]),\n .I1(phy_wrdata[191]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_38 [5]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_1__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [175]),\n .I1(phy_wrdata[191]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_39 [5]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_1__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [183]),\n .I1(phy_wrdata[191]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_40 [5]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_1__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [190]),\n .I1(phy_wrdata[190]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_41 [13]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_2\n (.I0(mc_address[6]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),\n .I2(init_calib_complete_reg_rep__14),\n .O(phy_dout[4]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_2__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [135]),\n .I1(phy_wrdata[159]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_38 [4]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_2__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [143]),\n .I1(phy_wrdata[159]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_39 [4]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_2__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [151]),\n .I1(phy_wrdata[159]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_40 [4]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_2__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [158]),\n .I1(phy_wrdata[158]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_41 [12]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [231]),\n .I1(phy_wrdata[255]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_38 [7]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_3__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [239]),\n .I1(phy_wrdata[255]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_39 [7]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_3__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [247]),\n .I1(phy_wrdata[255]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_40 [7]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_3__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [254]),\n .I1(phy_wrdata[254]),\n .I2(init_calib_complete_reg_rep__7),\n .O(\\my_empty_reg[7]_41 [15]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [199]),\n .I1(phy_wrdata[223]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_38 [6]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_4__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [207]),\n .I1(phy_wrdata[223]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_39 [6]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_4__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [215]),\n .I1(phy_wrdata[223]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_40 [6]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_4__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [222]),\n .I1(phy_wrdata[222]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_41 [14]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [38]),\n .I1(phy_wrdata[62]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_38 [9]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_5__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [46]),\n .I1(phy_wrdata[62]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_39 [9]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_5__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [54]),\n .I1(phy_wrdata[62]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_40 [9]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_5__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [61]),\n .I1(phy_wrdata[61]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_41 [17]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [6]),\n .I1(phy_wrdata[30]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_38 [8]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_6__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [14]),\n .I1(phy_wrdata[30]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_39 [8]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_6__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [22]),\n .I1(phy_wrdata[30]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_40 [8]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_6__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [29]),\n .I1(phy_wrdata[29]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_41 [16]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [102]),\n .I1(phy_wrdata[126]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_38 [11]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_1__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [110]),\n .I1(phy_wrdata[126]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_39 [11]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_1__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [118]),\n .I1(phy_wrdata[126]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_40 [11]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_1__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [125]),\n .I1(phy_wrdata[125]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_41 [19]));\n LUT2 #(\n .INIT(4'hE)) \n mem_reg_0_15_18_23_i_1__3\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),\n .I1(init_calib_complete_reg_rep__13),\n .O(phy_dout[7]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_2\n (.I0(mc_address[27]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(phy_dout[6]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_2__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [70]),\n .I1(phy_wrdata[94]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_38 [10]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_2__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [78]),\n .I1(phy_wrdata[94]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_39 [10]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_2__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [86]),\n .I1(phy_wrdata[94]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_40 [10]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_2__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [93]),\n .I1(phy_wrdata[93]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_41 [18]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [166]),\n .I1(phy_wrdata[190]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_38 [13]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_3__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [174]),\n .I1(phy_wrdata[190]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_39 [13]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_3__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [182]),\n .I1(phy_wrdata[190]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_40 [13]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_3__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [189]),\n .I1(phy_wrdata[189]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_41 [21]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [134]),\n .I1(phy_wrdata[158]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_38 [12]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_4__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [142]),\n .I1(phy_wrdata[158]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_39 [12]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_4__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [150]),\n .I1(phy_wrdata[158]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_40 [12]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_4__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [157]),\n .I1(phy_wrdata[157]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_41 [20]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [230]),\n .I1(phy_wrdata[254]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_38 [15]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_5__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [238]),\n .I1(phy_wrdata[254]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_39 [15]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_5__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [246]),\n .I1(phy_wrdata[254]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_40 [15]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_5__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [253]),\n .I1(phy_wrdata[253]),\n .I2(init_calib_complete_reg_rep__7),\n .O(\\my_empty_reg[7]_41 [23]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [198]),\n .I1(phy_wrdata[222]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_38 [14]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_6__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [206]),\n .I1(phy_wrdata[222]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_39 [14]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_6__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [214]),\n .I1(phy_wrdata[222]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_40 [14]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_6__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [221]),\n .I1(phy_wrdata[221]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_41 [22]));\n LUT3 #(\n .INIT(8'hB8)) \n mem_reg_0_15_24_29_i_1\n (.I0(mc_ras_n),\n .I1(init_calib_complete_reg_rep__14),\n .I2(phy_ras_n),\n .O(\\rd_ptr_timing_reg[0] [1]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_1__0\n (.I0(mc_address[17]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(phy_dout[9]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_1__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [37]),\n .I1(phy_wrdata[61]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_38 [17]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_1__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [45]),\n .I1(phy_wrdata[61]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_39 [17]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_1__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [53]),\n .I1(phy_wrdata[61]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_40 [17]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_1__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [60]),\n .I1(phy_wrdata[60]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_41 [25]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_2\n (.I0(mc_address[7]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),\n .I2(init_calib_complete_reg_rep__14),\n .O(phy_dout[8]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_2__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [5]),\n .I1(phy_wrdata[29]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_38 [16]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_2__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [13]),\n .I1(phy_wrdata[29]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_39 [16]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_2__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [21]),\n .I1(phy_wrdata[29]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_40 [16]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_2__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [28]),\n .I1(phy_wrdata[28]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_41 [24]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [101]),\n .I1(phy_wrdata[125]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_38 [19]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_3__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [109]),\n .I1(phy_wrdata[125]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_39 [19]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_3__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [117]),\n .I1(phy_wrdata[125]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_40 [19]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_3__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [124]),\n .I1(phy_wrdata[124]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_41 [27]));\n LUT2 #(\n .INIT(4'hE)) \n mem_reg_0_15_24_29_i_3__3\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),\n .I1(init_calib_complete_reg_rep__13),\n .O(phy_dout[11]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_4\n (.I0(mc_address[28]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(phy_dout[10]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_4__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [69]),\n .I1(phy_wrdata[93]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_38 [18]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_4__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [77]),\n .I1(phy_wrdata[93]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_39 [18]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_4__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [85]),\n .I1(phy_wrdata[93]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_40 [18]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_4__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [92]),\n .I1(phy_wrdata[92]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_41 [26]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [165]),\n .I1(phy_wrdata[189]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_38 [21]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_5__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [173]),\n .I1(phy_wrdata[189]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_39 [21]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_5__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [181]),\n .I1(phy_wrdata[189]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_40 [21]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_5__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [188]),\n .I1(phy_wrdata[188]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_41 [29]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [133]),\n .I1(phy_wrdata[157]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_38 [20]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_6__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [141]),\n .I1(phy_wrdata[157]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_39 [20]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_6__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [149]),\n .I1(phy_wrdata[157]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_40 [20]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_6__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [156]),\n .I1(phy_wrdata[156]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_41 [28]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_1\n (.I0(mc_address[18]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(phy_dout[13]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_1__0\n (.I0(mc_bank[3]),\n .I1(phy_bank[9]),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [3]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_1__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [229]),\n .I1(phy_wrdata[253]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_38 [23]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_1__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [237]),\n .I1(phy_wrdata[253]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_39 [23]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_1__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [245]),\n .I1(phy_wrdata[253]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_40 [23]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_1__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [252]),\n .I1(phy_wrdata[252]),\n .I2(init_calib_complete_reg_rep__7),\n .O(\\my_empty_reg[7]_41 [31]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_2\n (.I0(mc_address[8]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),\n .I2(init_calib_complete_reg_rep__14),\n .O(phy_dout[12]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_2__0\n (.I0(mc_bank[0]),\n .I1(phy_bank[9]),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [2]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_2__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [197]),\n .I1(phy_wrdata[221]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_38 [22]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_2__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [205]),\n .I1(phy_wrdata[221]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_39 [22]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_2__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [213]),\n .I1(phy_wrdata[221]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_40 [22]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_2__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [220]),\n .I1(phy_wrdata[220]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_41 [30]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [36]),\n .I1(phy_wrdata[60]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_38 [25]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_3__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [44]),\n .I1(phy_wrdata[60]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_39 [25]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_3__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [52]),\n .I1(phy_wrdata[60]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_40 [25]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_3__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [59]),\n .I1(phy_wrdata[59]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_41 [33]));\n LUT2 #(\n .INIT(4'hE)) \n mem_reg_0_15_30_35_i_3__3\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),\n .I1(init_calib_complete_reg_rep__13),\n .O(phy_dout[15]));\n LUT2 #(\n .INIT(4'hE)) \n mem_reg_0_15_30_35_i_3__4\n (.I0(phy_bank[9]),\n .I1(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [5]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_4\n (.I0(mc_address[29]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(phy_dout[14]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_4__0\n (.I0(mc_bank[6]),\n .I1(phy_bank[9]),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [4]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_4__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [4]),\n .I1(phy_wrdata[28]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_38 [24]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_4__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [12]),\n .I1(phy_wrdata[28]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_39 [24]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_4__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [20]),\n .I1(phy_wrdata[28]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_40 [24]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_4__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [27]),\n .I1(phy_wrdata[27]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_41 [32]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [100]),\n .I1(phy_wrdata[124]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_38 [27]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_5__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [108]),\n .I1(phy_wrdata[124]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_39 [27]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_5__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [116]),\n .I1(phy_wrdata[124]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_40 [27]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_5__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [123]),\n .I1(phy_wrdata[123]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_41 [35]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [68]),\n .I1(phy_wrdata[92]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_38 [26]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_6__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [76]),\n .I1(phy_wrdata[92]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_39 [26]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_6__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [84]),\n .I1(phy_wrdata[92]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_40 [26]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_6__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [91]),\n .I1(phy_wrdata[91]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_41 [34]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_1\n (.I0(mc_address[14]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [7]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_1__0\n (.I0(mc_address[19]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(phy_dout[17]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_1__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [164]),\n .I1(phy_wrdata[188]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_38 [29]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_1__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [172]),\n .I1(phy_wrdata[188]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_39 [29]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_1__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [180]),\n .I1(phy_wrdata[188]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_40 [29]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_1__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [187]),\n .I1(phy_wrdata[187]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_41 [37]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_2\n (.I0(mc_address[4]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .I2(init_calib_complete_reg_rep__14),\n .O(\\rd_ptr_timing_reg[0] [6]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_2__0\n (.I0(mc_address[9]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),\n .I2(init_calib_complete_reg_rep__14),\n .O(phy_dout[16]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_2__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [132]),\n .I1(phy_wrdata[156]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_38 [28]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_2__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [140]),\n .I1(phy_wrdata[156]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_39 [28]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_2__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [148]),\n .I1(phy_wrdata[156]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_40 [28]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_2__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [155]),\n .I1(phy_wrdata[155]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_41 [36]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [228]),\n .I1(phy_wrdata[252]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_38 [31]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_3__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [236]),\n .I1(phy_wrdata[252]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_39 [31]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_3__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [244]),\n .I1(phy_wrdata[252]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_40 [31]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_3__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [251]),\n .I1(phy_wrdata[251]),\n .I2(init_calib_complete_reg_rep__7),\n .O(\\my_empty_reg[7]_41 [39]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [196]),\n .I1(phy_wrdata[220]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_38 [30]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_4__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [204]),\n .I1(phy_wrdata[220]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_39 [30]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_4__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [212]),\n .I1(phy_wrdata[220]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_40 [30]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_4__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [219]),\n .I1(phy_wrdata[219]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_41 [38]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [35]),\n .I1(phy_wrdata[59]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_38 [33]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_5__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [43]),\n .I1(phy_wrdata[59]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_39 [33]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_5__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [51]),\n .I1(phy_wrdata[59]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_40 [33]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_5__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [58]),\n .I1(phy_wrdata[58]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_41 [41]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [3]),\n .I1(phy_wrdata[27]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_38 [32]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_6__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [11]),\n .I1(phy_wrdata[27]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_39 [32]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_6__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [19]),\n .I1(phy_wrdata[27]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_40 [32]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_6__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [26]),\n .I1(phy_wrdata[26]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_41 [40]));\n LUT3 #(\n .INIT(8'hB8)) \n mem_reg_0_15_42_47_i_1\n (.I0(mc_odt),\n .I1(init_calib_complete_reg_rep__14),\n .I2(calib_odt),\n .O(\\my_full_reg[3] [0]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_1__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [99]),\n .I1(phy_wrdata[123]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_38 [35]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_1__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [107]),\n .I1(phy_wrdata[123]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_39 [35]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_1__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [115]),\n .I1(phy_wrdata[123]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_40 [35]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_1__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [122]),\n .I1(phy_wrdata[122]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_41 [43]));\n LUT2 #(\n .INIT(4'hE)) \n mem_reg_0_15_42_47_i_1__4\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .I1(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [9]));\n LUT2 #(\n .INIT(4'hE)) \n mem_reg_0_15_42_47_i_1__5\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),\n .I1(init_calib_complete_reg_rep__13),\n .O(phy_dout[19]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_2\n (.I0(mc_address[25]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [8]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_2__0\n (.I0(mc_address[30]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(phy_dout[18]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_2__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [67]),\n .I1(phy_wrdata[91]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_38 [34]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_2__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [75]),\n .I1(phy_wrdata[91]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_39 [34]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_2__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [83]),\n .I1(phy_wrdata[91]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_40 [34]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_2__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [90]),\n .I1(phy_wrdata[90]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_41 [42]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_3\n (.I0(mc_bank[5]),\n .I1(phy_bank[11]),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [11]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_3__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [163]),\n .I1(phy_wrdata[187]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_38 [37]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_3__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [171]),\n .I1(phy_wrdata[187]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_39 [37]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_3__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [179]),\n .I1(phy_wrdata[187]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_40 [37]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_3__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [186]),\n .I1(phy_wrdata[186]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_41 [45]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_4\n (.I0(mc_bank[2]),\n .I1(phy_bank[11]),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [10]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_4__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [131]),\n .I1(phy_wrdata[155]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_38 [36]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_4__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [139]),\n .I1(phy_wrdata[155]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_39 [36]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_4__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [147]),\n .I1(phy_wrdata[155]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_40 [36]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_4__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [154]),\n .I1(phy_wrdata[154]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_41 [44]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [227]),\n .I1(phy_wrdata[251]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_38 [39]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_5__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [235]),\n .I1(phy_wrdata[251]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_39 [39]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_5__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [243]),\n .I1(phy_wrdata[251]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_40 [39]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_5__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [250]),\n .I1(phy_wrdata[250]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_41 [47]));\n LUT2 #(\n .INIT(4'hE)) \n mem_reg_0_15_42_47_i_5__3\n (.I0(phy_bank[11]),\n .I1(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [13]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_6\n (.I0(mc_bank[8]),\n .I1(phy_bank[11]),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [12]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_6__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [195]),\n .I1(phy_wrdata[219]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_38 [38]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_6__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [203]),\n .I1(phy_wrdata[219]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_39 [38]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_6__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [211]),\n .I1(phy_wrdata[219]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_40 [38]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_6__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [218]),\n .I1(phy_wrdata[218]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_41 [46]));\n LUT3 #(\n .INIT(8'hB8)) \n mem_reg_0_15_48_53_i_1\n (.I0(mc_cke),\n .I1(init_calib_complete_reg_rep__14),\n .I2(calib_cke),\n .O(\\my_full_reg[3] [1]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_1__0\n (.I0(mc_cas_n),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),\n .I2(init_calib_complete_reg_rep__14),\n .O(\\rd_ptr_timing_reg[0] [15]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_1__1\n (.I0(mc_address[20]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(phy_dout[21]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_1__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [34]),\n .I1(phy_wrdata[58]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_38 [41]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_1__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [42]),\n .I1(phy_wrdata[58]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_39 [41]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_1__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [50]),\n .I1(phy_wrdata[58]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_40 [41]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_1__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [57]),\n .I1(phy_wrdata[57]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_41 [49]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_2\n (.I0(mc_address[1]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),\n .I2(init_calib_complete_reg_rep__14),\n .O(\\rd_ptr_timing_reg[0] [14]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_2__0\n (.I0(mc_address[10]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),\n .I2(init_calib_complete_reg_rep__14),\n .O(phy_dout[20]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_2__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [2]),\n .I1(phy_wrdata[26]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_38 [40]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_2__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [10]),\n .I1(phy_wrdata[26]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_39 [40]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_2__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [18]),\n .I1(phy_wrdata[26]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_40 [40]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_2__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [25]),\n .I1(phy_wrdata[25]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_41 [48]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [98]),\n .I1(phy_wrdata[122]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_38 [43]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_3__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [106]),\n .I1(phy_wrdata[122]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_39 [43]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_3__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [114]),\n .I1(phy_wrdata[122]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_40 [43]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_3__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [121]),\n .I1(phy_wrdata[121]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_41 [51]));\n LUT2 #(\n .INIT(4'hE)) \n mem_reg_0_15_48_53_i_3__3\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),\n .I1(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [17]));\n LUT2 #(\n .INIT(4'hE)) \n mem_reg_0_15_48_53_i_3__4\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),\n .I1(init_calib_complete_reg_rep__13),\n .O(phy_dout[23]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_4\n (.I0(mc_address[22]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [16]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_4__0\n (.I0(mc_address[31]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(phy_dout[22]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_4__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [66]),\n .I1(phy_wrdata[90]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_38 [42]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_4__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [74]),\n .I1(phy_wrdata[90]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_39 [42]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_4__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [82]),\n .I1(phy_wrdata[90]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_40 [42]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_4__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [89]),\n .I1(phy_wrdata[89]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_41 [50]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_5\n (.I0(mc_cas_n),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),\n .I2(init_calib_complete_reg_rep__14),\n .O(\\rd_ptr_timing_reg[0] [19]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_5__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [162]),\n .I1(phy_wrdata[186]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_38 [45]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_5__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [170]),\n .I1(phy_wrdata[186]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_39 [45]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_5__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [178]),\n .I1(phy_wrdata[186]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_40 [45]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_5__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [185]),\n .I1(phy_wrdata[185]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_41 [53]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_6\n (.I0(mc_address[0]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),\n .I2(init_calib_complete_reg_rep__14),\n .O(\\rd_ptr_timing_reg[0] [18]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_6__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [130]),\n .I1(phy_wrdata[154]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_38 [44]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_6__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [138]),\n .I1(phy_wrdata[154]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_39 [44]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_6__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [146]),\n .I1(phy_wrdata[154]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_40 [44]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_6__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [153]),\n .I1(phy_wrdata[153]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_41 [52]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_1\n (.I0(mc_cas_n),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(phy_dout[25]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_1__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [226]),\n .I1(phy_wrdata[250]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_38 [47]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_1__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [234]),\n .I1(phy_wrdata[250]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_39 [47]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_1__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [242]),\n .I1(phy_wrdata[250]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_40 [47]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_1__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [249]),\n .I1(phy_wrdata[249]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_41 [55]));\n LUT2 #(\n .INIT(4'hE)) \n mem_reg_0_15_54_59_i_1__4\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),\n .I1(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [21]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_2\n (.I0(mc_address[11]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ),\n .I2(init_calib_complete_reg_rep__14),\n .O(phy_dout[24]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_2__0\n (.I0(mc_address[21]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [20]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_2__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [194]),\n .I1(phy_wrdata[218]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_38 [46]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_2__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [202]),\n .I1(phy_wrdata[218]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_39 [46]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_2__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [210]),\n .I1(phy_wrdata[218]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_40 [46]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_2__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [217]),\n .I1(phy_wrdata[217]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_41 [54]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_3\n (.I0(mc_cas_n),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),\n .I2(init_calib_complete_reg_rep__14),\n .O(\\rd_ptr_timing_reg[0] [23]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_3__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [33]),\n .I1(phy_wrdata[57]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_38 [49]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_3__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [41]),\n .I1(phy_wrdata[57]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_39 [49]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_3__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [49]),\n .I1(phy_wrdata[57]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_40 [49]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_3__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [56]),\n .I1(phy_wrdata[56]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_41 [57]));\n LUT2 #(\n .INIT(4'hE)) \n mem_reg_0_15_54_59_i_3__4\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ),\n .I1(init_calib_complete_reg_rep__13),\n .O(phy_dout[27]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_4\n (.I0(mc_address[2]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),\n .I2(init_calib_complete_reg_rep__14),\n .O(\\rd_ptr_timing_reg[0] [22]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_4__0\n (.I0(mc_address[32]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(phy_dout[26]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_4__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [1]),\n .I1(phy_wrdata[25]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_38 [48]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_4__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [9]),\n .I1(phy_wrdata[25]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_39 [48]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_4__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [17]),\n .I1(phy_wrdata[25]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_40 [48]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_4__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [24]),\n .I1(phy_wrdata[24]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_41 [56]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [97]),\n .I1(phy_wrdata[121]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_38 [51]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_5__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [105]),\n .I1(phy_wrdata[121]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_39 [51]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_5__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [113]),\n .I1(phy_wrdata[121]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_40 [51]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_5__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [120]),\n .I1(phy_wrdata[120]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_41 [59]));\n LUT2 #(\n .INIT(4'hE)) \n mem_reg_0_15_54_59_i_5__3\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),\n .I1(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [25]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_6\n (.I0(mc_address[23]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [24]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_6__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [65]),\n .I1(phy_wrdata[89]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_38 [50]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_6__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [73]),\n .I1(phy_wrdata[89]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_39 [50]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_6__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [81]),\n .I1(phy_wrdata[89]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_40 [50]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_6__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [88]),\n .I1(phy_wrdata[88]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_41 [58]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_1\n (.I0(mc_address[13]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [27]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_1__0\n (.I0(mc_ras_n),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(phy_dout[29]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_1__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [161]),\n .I1(phy_wrdata[185]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_38 [53]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_1__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [169]),\n .I1(phy_wrdata[185]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_39 [53]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_1__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [177]),\n .I1(phy_wrdata[185]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_40 [53]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_1__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [184]),\n .I1(phy_wrdata[184]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_41 [61]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_2\n (.I0(mc_address[3]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I2(init_calib_complete_reg_rep__14),\n .O(\\rd_ptr_timing_reg[0] [26]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_2__0\n (.I0(mc_address[12]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),\n .I2(init_calib_complete_reg_rep__14),\n .O(phy_dout[28]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_2__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [129]),\n .I1(phy_wrdata[153]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_38 [52]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_2__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [137]),\n .I1(phy_wrdata[153]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_39 [52]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_2__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [145]),\n .I1(phy_wrdata[153]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_40 [52]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_2__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [152]),\n .I1(phy_wrdata[152]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_41 [60]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [225]),\n .I1(phy_wrdata[249]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_38 [55]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_3__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [233]),\n .I1(phy_wrdata[249]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_39 [55]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_3__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [241]),\n .I1(phy_wrdata[249]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_40 [55]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_3__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [248]),\n .I1(phy_wrdata[248]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_41 [63]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [193]),\n .I1(phy_wrdata[217]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_38 [54]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_4__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [201]),\n .I1(phy_wrdata[217]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_39 [54]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_4__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [209]),\n .I1(phy_wrdata[217]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_40 [54]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_4__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [216]),\n .I1(phy_wrdata[216]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_41 [62]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [32]),\n .I1(phy_wrdata[56]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_38 [57]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_5__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [40]),\n .I1(phy_wrdata[56]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_39 [57]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_5__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [48]),\n .I1(phy_wrdata[56]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_40 [57]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [0]),\n .I1(phy_wrdata[24]),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\my_empty_reg[7]_38 [56]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_6__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [8]),\n .I1(phy_wrdata[24]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_39 [56]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_6__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [16]),\n .I1(phy_wrdata[24]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_40 [56]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [96]),\n .I1(phy_wrdata[120]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_38 [59]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_1__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [104]),\n .I1(phy_wrdata[120]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_39 [59]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_1__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [112]),\n .I1(phy_wrdata[120]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_40 [59]));\n LUT2 #(\n .INIT(4'hE)) \n mem_reg_0_15_66_71_i_1__2\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I1(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [29]));\n LUT2 #(\n .INIT(4'hE)) \n mem_reg_0_15_66_71_i_1__3\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),\n .I1(init_calib_complete_reg_rep__13),\n .O(phy_dout[31]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_2\n (.I0(mc_address[24]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [28]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_2__0\n (.I0(mc_address[33]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(phy_dout[30]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_2__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [64]),\n .I1(phy_wrdata[88]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_38 [58]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_2__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [72]),\n .I1(phy_wrdata[88]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_39 [58]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_2__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [80]),\n .I1(phy_wrdata[88]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_40 [58]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [160]),\n .I1(phy_wrdata[184]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_38 [61]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_3__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [168]),\n .I1(phy_wrdata[184]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_39 [61]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_3__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [176]),\n .I1(phy_wrdata[184]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_40 [61]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [128]),\n .I1(phy_wrdata[152]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_38 [60]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_4__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [136]),\n .I1(phy_wrdata[152]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_39 [60]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_4__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [144]),\n .I1(phy_wrdata[152]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_40 [60]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [224]),\n .I1(phy_wrdata[248]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_38 [63]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_5__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [232]),\n .I1(phy_wrdata[248]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_39 [63]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_5__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [240]),\n .I1(phy_wrdata[248]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_40 [63]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [192]),\n .I1(phy_wrdata[216]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_38 [62]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_6__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [200]),\n .I1(phy_wrdata[216]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_39 [62]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_6__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [208]),\n .I1(phy_wrdata[216]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_40 [62]));\n LUT3 #(\n .INIT(8'hB8)) \n mem_reg_0_15_6_11_i_1\n (.I0(mc_we_n),\n .I1(init_calib_complete_reg_rep__14),\n .I2(phy_we_n),\n .O(\\rd_ptr_timing_reg[0]_3 [1]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_1__0\n (.I0(mc_address[15]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(phy_dout[1]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_1__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [39]),\n .I1(phy_wrdata[63]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_38 [1]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_1__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [47]),\n .I1(phy_wrdata[63]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_39 [1]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_1__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [55]),\n .I1(phy_wrdata[63]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_40 [1]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_1__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [255]),\n .I1(phy_wrdata[255]),\n .I2(init_calib_complete_reg_rep__7),\n .O(\\my_empty_reg[7]_41 [7]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_2\n (.I0(mc_address[5]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),\n .I2(init_calib_complete_reg_rep__14),\n .O(phy_dout[0]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_2__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [7]),\n .I1(phy_wrdata[31]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_38 [0]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_2__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [15]),\n .I1(phy_wrdata[31]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_39 [0]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_2__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [23]),\n .I1(phy_wrdata[31]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_40 [0]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_2__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [223]),\n .I1(phy_wrdata[223]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_41 [6]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [62]),\n .I1(phy_wrdata[62]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_41 [9]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_3__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [103]),\n .I1(phy_wrdata[127]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_38 [3]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_3__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [111]),\n .I1(phy_wrdata[127]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_39 [3]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_3__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [119]),\n .I1(phy_wrdata[127]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_40 [3]));\n LUT2 #(\n .INIT(4'hE)) \n mem_reg_0_15_6_11_i_3__3\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),\n .I1(init_calib_complete_reg_rep__13),\n .O(phy_dout[3]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_4\n (.I0(mc_address[26]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(phy_dout[2]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_4__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [30]),\n .I1(phy_wrdata[30]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_41 [8]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_4__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [71]),\n .I1(phy_wrdata[95]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_38 [2]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_4__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [79]),\n .I1(phy_wrdata[95]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_39 [2]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_4__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [87]),\n .I1(phy_wrdata[95]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_40 [2]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [126]),\n .I1(phy_wrdata[126]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_41 [11]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [94]),\n .I1(phy_wrdata[94]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_41 [10]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_72_77_i_1__0\n (.I0(mc_bank[4]),\n .I1(phy_bank[10]),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [31]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_72_77_i_2\n (.I0(mc_bank[1]),\n .I1(phy_bank[10]),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [30]));\n LUT2 #(\n .INIT(4'hE)) \n mem_reg_0_15_72_77_i_3\n (.I0(phy_bank[10]),\n .I1(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [33]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_72_77_i_4\n (.I0(mc_bank[7]),\n .I1(phy_bank[10]),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [32]));\n (* SOFT_HLUTNM = \"soft_lutpair482\" *) \n LUT5 #(\n .INIT(32'hAAAAAAA8)) \n mpr_end_if_reset_i_1\n (.I0(mpr_last_byte_done),\n .I1(num_refresh_reg__0[2]),\n .I2(num_refresh_reg__0[0]),\n .I3(num_refresh_reg__0[1]),\n .I4(num_refresh_reg__0[3]),\n .O(mpr_end_if_reset0));\n FDRE #(\n .INIT(1'b0)) \n mpr_end_if_reset_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mpr_end_if_reset0),\n .Q(mpr_end_if_reset),\n .R(rstdiv0_sync_r1_reg_rep__11));\n LUT6 #(\n .INIT(64'hFFFFFFFF00100000)) \n mpr_rdlvl_start_i_1\n (.I0(mpr_rdlvl_start_i_2_n_0),\n .I1(Q[2]),\n .I2(\\init_state_r_reg_n_0_[3] ),\n .I3(Q[1]),\n .I4(dqs_found_done_r_reg),\n .I5(mpr_rdlvl_start_r_reg),\n .O(mpr_rdlvl_start_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair522\" *) \n LUT4 #(\n .INIT(16'hFBFF)) \n mpr_rdlvl_start_i_2\n (.I0(Q[5]),\n .I1(Q[4]),\n .I2(Q[3]),\n .I3(Q[0]),\n .O(mpr_rdlvl_start_i_2_n_0));\n FDRE #(\n .INIT(1'b0)) \n mpr_rdlvl_start_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mpr_rdlvl_start_i_1_n_0),\n .Q(mpr_rdlvl_start_r_reg),\n .R(rstdiv0_sync_r1_reg_rep__12));\n (* SOFT_HLUTNM = \"soft_lutpair608\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\num_refresh[0]_i_1 \n (.I0(num_refresh_reg__0[0]),\n .O(p_0_in__4[0]));\n (* SOFT_HLUTNM = \"soft_lutpair608\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\num_refresh[1]_i_1 \n (.I0(num_refresh_reg__0[1]),\n .I1(num_refresh_reg__0[0]),\n .O(p_0_in__4[1]));\n (* SOFT_HLUTNM = \"soft_lutpair553\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\num_refresh[2]_i_1 \n (.I0(num_refresh_reg__0[2]),\n .I1(num_refresh_reg__0[0]),\n .I2(num_refresh_reg__0[1]),\n .O(p_0_in__4[2]));\n LUT6 #(\n .INIT(64'hFEFEFEFEFEFFFEFE)) \n \\num_refresh[3]_i_1 \n (.I0(\\num_refresh[3]_i_4_n_0 ),\n .I1(rstdiv0_sync_r1_reg_rep__23),\n .I2(\\num_refresh[3]_i_5_n_0 ),\n .I3(prbs_rdlvl_start_i_2_n_0),\n .I4(\\wrcal_reads[7]_i_5_n_0 ),\n .I5(read_calib_i_2_n_0),\n .O(\\num_refresh[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h22A2AAA2AAAAAAAA)) \n \\num_refresh[3]_i_2 \n (.I0(\\cnt_init_mr_r_reg[1]_0 ),\n .I1(dqs_found_done_r_reg),\n .I2(wrcal_done_reg_10),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(prbs_rdlvl_done_reg),\n .I5(oclkdelay_calib_done_r_reg_2),\n .O(num_refresh0));\n (* SOFT_HLUTNM = \"soft_lutpair553\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\num_refresh[3]_i_3 \n (.I0(num_refresh_reg__0[3]),\n .I1(num_refresh_reg__0[1]),\n .I2(num_refresh_reg__0[0]),\n .I3(num_refresh_reg__0[2]),\n .O(p_0_in__4[3]));\n (* SOFT_HLUTNM = \"soft_lutpair503\" *) \n LUT5 #(\n .INIT(32'h404000FF)) \n \\num_refresh[3]_i_4 \n (.I0(complex_oclkdelay_calib_start_int_i_2_n_0),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .I2(Q[0]),\n .I3(\\num_refresh[3]_i_6_n_0 ),\n .I4(Q[1]),\n .O(\\num_refresh[3]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000002000)) \n \\num_refresh[3]_i_5 \n (.I0(Q[4]),\n .I1(Q[5]),\n .I2(Q[3]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[2]),\n .I5(complex_oclkdelay_calib_start_int_reg_0),\n .O(\\num_refresh[3]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFBFFFFFFFEFFFFFF)) \n \\num_refresh[3]_i_6 \n (.I0(Q[5]),\n .I1(Q[4]),\n .I2(Q[3]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[2]),\n .I5(Q[0]),\n .O(\\num_refresh[3]_i_6_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\num_refresh_reg[0] \n (.C(CLK),\n .CE(num_refresh0),\n .D(p_0_in__4[0]),\n .Q(num_refresh_reg__0[0]),\n .R(\\num_refresh[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\num_refresh_reg[1] \n (.C(CLK),\n .CE(num_refresh0),\n .D(p_0_in__4[1]),\n .Q(num_refresh_reg__0[1]),\n .R(\\num_refresh[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\num_refresh_reg[2] \n (.C(CLK),\n .CE(num_refresh0),\n .D(p_0_in__4[2]),\n .Q(num_refresh_reg__0[2]),\n .R(\\num_refresh[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\num_refresh_reg[3] \n (.C(CLK),\n .CE(num_refresh0),\n .D(p_0_in__4[3]),\n .Q(num_refresh_reg__0[3]),\n .R(\\num_refresh[3]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\ocal_act_wait_cnt[0]_i_1 \n (.I0(ocal_act_wait_cnt_reg__0[0]),\n .O(p_0_in__9[0]));\n (* SOFT_HLUTNM = \"soft_lutpair600\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\ocal_act_wait_cnt[1]_i_1 \n (.I0(ocal_act_wait_cnt_reg__0[1]),\n .I1(ocal_act_wait_cnt_reg__0[0]),\n .O(p_0_in__9[1]));\n (* SOFT_HLUTNM = \"soft_lutpair600\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\ocal_act_wait_cnt[2]_i_1 \n (.I0(ocal_act_wait_cnt_reg__0[2]),\n .I1(ocal_act_wait_cnt_reg__0[1]),\n .I2(ocal_act_wait_cnt_reg__0[0]),\n .O(p_0_in__9[2]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFDFFFF)) \n \\ocal_act_wait_cnt[3]_i_1 \n (.I0(\\ocal_act_wait_cnt[3]_i_3_n_0 ),\n .I1(Q[4]),\n .I2(Q[3]),\n .I3(oclk_calib_resume_level_reg_0),\n .I4(Q[5]),\n .I5(rstdiv0_sync_r1_reg_rep__23),\n .O(\\ocal_act_wait_cnt[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair535\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\ocal_act_wait_cnt[3]_i_2 \n (.I0(ocal_act_wait_cnt_reg__0[3]),\n .I1(ocal_act_wait_cnt_reg__0[0]),\n .I2(ocal_act_wait_cnt_reg__0[1]),\n .I3(ocal_act_wait_cnt_reg__0[2]),\n .O(p_0_in__9[3]));\n LUT6 #(\n .INIT(64'h000000007FFF0000)) \n \\ocal_act_wait_cnt[3]_i_3 \n (.I0(ocal_act_wait_cnt_reg__0[3]),\n .I1(ocal_act_wait_cnt_reg__0[0]),\n .I2(ocal_act_wait_cnt_reg__0[1]),\n .I3(ocal_act_wait_cnt_reg__0[2]),\n .I4(Q[1]),\n .I5(Q[0]),\n .O(\\ocal_act_wait_cnt[3]_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\ocal_act_wait_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__9[0]),\n .Q(ocal_act_wait_cnt_reg__0[0]),\n .R(\\ocal_act_wait_cnt[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\ocal_act_wait_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__9[1]),\n .Q(ocal_act_wait_cnt_reg__0[1]),\n .R(\\ocal_act_wait_cnt[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\ocal_act_wait_cnt_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__9[2]),\n .Q(ocal_act_wait_cnt_reg__0[2]),\n .R(\\ocal_act_wait_cnt[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\ocal_act_wait_cnt_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__9[3]),\n .Q(ocal_act_wait_cnt_reg__0[3]),\n .R(\\ocal_act_wait_cnt[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n ocal_last_byte_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(oclkdelay_center_calib_done_r_reg),\n .Q(ocal_last_byte_done),\n .R(rstdiv0_sync_r1_reg_rep__11));\n LUT6 #(\n .INIT(64'h00000000EEEEEE0E)) \n oclk_calib_resume_level_i_1\n (.I0(oclk_calib_resume_level),\n .I1(complex_oclk_calib_resume),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .I3(complex_oclkdelay_calib_start_int_i_2_n_0),\n .I4(oclk_calib_resume_level_reg_0),\n .I5(rstdiv0_sync_r1_reg_rep__24),\n .O(oclk_calib_resume_level_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n oclk_calib_resume_level_reg\n (.C(CLK),\n .CE(1'b1),\n .D(oclk_calib_resume_level_i_1_n_0),\n .Q(oclk_calib_resume_level),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair604\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\oclk_wr_cnt[0]_i_1 \n (.I0(oclk_wr_cnt_reg__0[0]),\n .O(\\oclk_wr_cnt[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair604\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\oclk_wr_cnt[1]_i_1 \n (.I0(oclk_wr_cnt_reg__0[0]),\n .I1(oclk_wr_cnt_reg__0[1]),\n .O(\\oclk_wr_cnt[1]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hA9)) \n \\oclk_wr_cnt[2]_i_1 \n (.I0(oclk_wr_cnt_reg__0[2]),\n .I1(oclk_wr_cnt_reg__0[1]),\n .I2(oclk_wr_cnt_reg__0[0]),\n .O(oclk_wr_cnt0[2]));\n LUT6 #(\n .INIT(64'hFFFFFFFFAAAAAAAB)) \n \\oclk_wr_cnt[3]_i_1 \n (.I0(\\oclk_wr_cnt[3]_i_4_n_0 ),\n .I1(oclk_wr_cnt_reg__0[2]),\n .I2(oclk_wr_cnt_reg__0[0]),\n .I3(oclk_wr_cnt_reg__0[1]),\n .I4(oclk_wr_cnt_reg__0[3]),\n .I5(rstdiv0_sync_r1_reg_rep__23),\n .O(\\oclk_wr_cnt[3]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h00800000)) \n \\oclk_wr_cnt[3]_i_2 \n (.I0(Q[1]),\n .I1(Q[2]),\n .I2(Q[0]),\n .I3(read_calib_i_2_n_0),\n .I4(\\init_state_r_reg_n_0_[3] ),\n .O(p_0_in0_in));\n (* SOFT_HLUTNM = \"soft_lutpair544\" *) \n LUT4 #(\n .INIT(16'hAAA9)) \n \\oclk_wr_cnt[3]_i_3 \n (.I0(oclk_wr_cnt_reg__0[3]),\n .I1(oclk_wr_cnt_reg__0[2]),\n .I2(oclk_wr_cnt_reg__0[0]),\n .I3(oclk_wr_cnt_reg__0[1]),\n .O(oclk_wr_cnt0[3]));\n LUT6 #(\n .INIT(64'h0000000000100000)) \n \\oclk_wr_cnt[3]_i_4 \n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(Q[4]),\n .I3(Q[5]),\n .I4(Q[3]),\n .I5(oclk_calib_resume_level_reg_0),\n .O(\\oclk_wr_cnt[3]_i_4_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\oclk_wr_cnt_reg[0] \n (.C(CLK),\n .CE(p_0_in0_in),\n .D(\\oclk_wr_cnt[0]_i_1_n_0 ),\n .Q(oclk_wr_cnt_reg__0[0]),\n .R(\\oclk_wr_cnt[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\oclk_wr_cnt_reg[1] \n (.C(CLK),\n .CE(p_0_in0_in),\n .D(\\oclk_wr_cnt[1]_i_1_n_0 ),\n .Q(oclk_wr_cnt_reg__0[1]),\n .R(\\oclk_wr_cnt[3]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\oclk_wr_cnt_reg[2] \n (.C(CLK),\n .CE(p_0_in0_in),\n .D(oclk_wr_cnt0[2]),\n .Q(oclk_wr_cnt_reg__0[2]),\n .S(\\oclk_wr_cnt[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\oclk_wr_cnt_reg[3] \n (.C(CLK),\n .CE(p_0_in0_in),\n .D(oclk_wr_cnt0[3]),\n .Q(oclk_wr_cnt_reg__0[3]),\n .R(\\oclk_wr_cnt[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair605\" *) \n LUT2 #(\n .INIT(4'hE)) \n oclkdelay_calib_start_int_i_1\n (.I0(oclkdelay_start_dly_r),\n .I1(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .O(oclkdelay_calib_start_int_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n oclkdelay_calib_start_int_reg\n (.C(CLK),\n .CE(1'b1),\n .D(oclkdelay_calib_start_int_i_1_n_0),\n .Q(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .R(rstdiv0_sync_r1_reg_rep__12));\n LUT5 #(\n .INIT(32'h0000AAEA)) \n oclkdelay_int_ref_req_i_1\n (.I0(oclkdelay_int_ref_req_reg_0),\n .I1(oclkdelay_int_ref_req_i_2_n_0),\n .I2(oclkdelay_ref_cnt_reg[0]),\n .I3(oclkdelay_int_ref_req_i_3_n_0),\n .I4(oclkdelay_int_ref_req0),\n .O(oclkdelay_int_ref_req_i_1_n_0));\n LUT6 #(\n .INIT(64'h0000000000000001)) \n oclkdelay_int_ref_req_i_2\n (.I0(oclkdelay_ref_cnt_reg[12]),\n .I1(oclkdelay_ref_cnt_reg[8]),\n .I2(oclkdelay_ref_cnt_reg[11]),\n .I3(oclkdelay_ref_cnt_reg[13]),\n .I4(oclkdelay_ref_cnt_reg[10]),\n .I5(oclkdelay_ref_cnt_reg[9]),\n .O(oclkdelay_int_ref_req_i_2_n_0));\n LUT4 #(\n .INIT(16'hFFFE)) \n oclkdelay_int_ref_req_i_3\n (.I0(oclkdelay_ref_cnt_reg[5]),\n .I1(oclkdelay_ref_cnt_reg[4]),\n .I2(oclkdelay_ref_cnt_reg[6]),\n .I3(oclkdelay_int_ref_req_i_5_n_0),\n .O(oclkdelay_int_ref_req_i_3_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFF4)) \n oclkdelay_int_ref_req_i_4\n (.I0(prbs_rdlvl_start_i_2_n_0),\n .I1(\\stg1_wr_rd_cnt[4]_i_5_n_0 ),\n .I2(ocal_last_byte_done),\n .I3(oclkdelay_center_calib_done_r_reg_0),\n .I4(rstdiv0_sync_r1_reg_rep__23),\n .I5(oclkdelay_calib_done_r_reg_2),\n .O(oclkdelay_int_ref_req0));\n LUT4 #(\n .INIT(16'hFFFE)) \n oclkdelay_int_ref_req_i_5\n (.I0(oclkdelay_ref_cnt_reg[1]),\n .I1(oclkdelay_ref_cnt_reg[3]),\n .I2(oclkdelay_ref_cnt_reg[7]),\n .I3(oclkdelay_ref_cnt_reg[2]),\n .O(oclkdelay_int_ref_req_i_5_n_0));\n FDRE #(\n .INIT(1'b0)) \n oclkdelay_int_ref_req_reg\n (.C(CLK),\n .CE(1'b1),\n .D(oclkdelay_int_ref_req_i_1_n_0),\n .Q(oclkdelay_int_ref_req_reg_0),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hEEEEEFEEEEEEEEEE)) \n \\oclkdelay_ref_cnt[0]_i_1 \n (.I0(prbs_rdlvl_done_reg_0),\n .I1(\\cnt_init_mr_r_reg[1]_0 ),\n .I2(oclkdelay_int_ref_req_i_3_n_0),\n .I3(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .I4(oclkdelay_ref_cnt_reg[0]),\n .I5(oclkdelay_int_ref_req_i_2_n_0),\n .O(\\oclkdelay_ref_cnt[0]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\oclkdelay_ref_cnt[0]_i_4 \n (.I0(oclkdelay_ref_cnt_reg[3]),\n .O(\\oclkdelay_ref_cnt[0]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\oclkdelay_ref_cnt[0]_i_5 \n (.I0(oclkdelay_ref_cnt_reg[2]),\n .O(\\oclkdelay_ref_cnt[0]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\oclkdelay_ref_cnt[0]_i_6 \n (.I0(oclkdelay_ref_cnt_reg[1]),\n .O(\\oclkdelay_ref_cnt[0]_i_6_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\oclkdelay_ref_cnt[0]_i_7 \n (.I0(oclkdelay_ref_cnt_reg[0]),\n .O(\\oclkdelay_ref_cnt[0]_i_7_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\oclkdelay_ref_cnt[12]_i_2 \n (.I0(oclkdelay_ref_cnt_reg[13]),\n .O(\\oclkdelay_ref_cnt[12]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\oclkdelay_ref_cnt[12]_i_3 \n (.I0(oclkdelay_ref_cnt_reg[12]),\n .O(\\oclkdelay_ref_cnt[12]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\oclkdelay_ref_cnt[4]_i_2 \n (.I0(oclkdelay_ref_cnt_reg[7]),\n .O(\\oclkdelay_ref_cnt[4]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\oclkdelay_ref_cnt[4]_i_3 \n (.I0(oclkdelay_ref_cnt_reg[6]),\n .O(\\oclkdelay_ref_cnt[4]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\oclkdelay_ref_cnt[4]_i_4 \n (.I0(oclkdelay_ref_cnt_reg[5]),\n .O(\\oclkdelay_ref_cnt[4]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\oclkdelay_ref_cnt[4]_i_5 \n (.I0(oclkdelay_ref_cnt_reg[4]),\n .O(\\oclkdelay_ref_cnt[4]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\oclkdelay_ref_cnt[8]_i_2 \n (.I0(oclkdelay_ref_cnt_reg[11]),\n .O(\\oclkdelay_ref_cnt[8]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\oclkdelay_ref_cnt[8]_i_3 \n (.I0(oclkdelay_ref_cnt_reg[10]),\n .O(\\oclkdelay_ref_cnt[8]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\oclkdelay_ref_cnt[8]_i_4 \n (.I0(oclkdelay_ref_cnt_reg[9]),\n .O(\\oclkdelay_ref_cnt[8]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\oclkdelay_ref_cnt[8]_i_5 \n (.I0(oclkdelay_ref_cnt_reg[8]),\n .O(\\oclkdelay_ref_cnt[8]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\oclkdelay_ref_cnt_reg[0] \n (.C(CLK),\n .CE(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .D(\\oclkdelay_ref_cnt_reg[0]_i_2_n_7 ),\n .Q(oclkdelay_ref_cnt_reg[0]),\n .R(\\oclkdelay_ref_cnt[0]_i_1_n_0 ));\n CARRY4 \\oclkdelay_ref_cnt_reg[0]_i_2 \n (.CI(1'b0),\n .CO({\\oclkdelay_ref_cnt_reg[0]_i_2_n_0 ,\\oclkdelay_ref_cnt_reg[0]_i_2_n_1 ,\\oclkdelay_ref_cnt_reg[0]_i_2_n_2 ,\\oclkdelay_ref_cnt_reg[0]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b1,1'b1,1'b1,1'b1}),\n .O({\\oclkdelay_ref_cnt_reg[0]_i_2_n_4 ,\\oclkdelay_ref_cnt_reg[0]_i_2_n_5 ,\\oclkdelay_ref_cnt_reg[0]_i_2_n_6 ,\\oclkdelay_ref_cnt_reg[0]_i_2_n_7 }),\n .S({\\oclkdelay_ref_cnt[0]_i_4_n_0 ,\\oclkdelay_ref_cnt[0]_i_5_n_0 ,\\oclkdelay_ref_cnt[0]_i_6_n_0 ,\\oclkdelay_ref_cnt[0]_i_7_n_0 }));\n FDSE #(\n .INIT(1'b1)) \n \\oclkdelay_ref_cnt_reg[10] \n (.C(CLK),\n .CE(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .D(\\oclkdelay_ref_cnt_reg[8]_i_1_n_5 ),\n .Q(oclkdelay_ref_cnt_reg[10]),\n .S(\\oclkdelay_ref_cnt[0]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\oclkdelay_ref_cnt_reg[11] \n (.C(CLK),\n .CE(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .D(\\oclkdelay_ref_cnt_reg[8]_i_1_n_4 ),\n .Q(oclkdelay_ref_cnt_reg[11]),\n .R(\\oclkdelay_ref_cnt[0]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\oclkdelay_ref_cnt_reg[12] \n (.C(CLK),\n .CE(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .D(\\oclkdelay_ref_cnt_reg[12]_i_1_n_7 ),\n .Q(oclkdelay_ref_cnt_reg[12]),\n .S(\\oclkdelay_ref_cnt[0]_i_1_n_0 ));\n CARRY4 \\oclkdelay_ref_cnt_reg[12]_i_1 \n (.CI(\\oclkdelay_ref_cnt_reg[8]_i_1_n_0 ),\n .CO({\\NLW_oclkdelay_ref_cnt_reg[12]_i_1_CO_UNCONNECTED [3:1],\\oclkdelay_ref_cnt_reg[12]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b1}),\n .O({\\NLW_oclkdelay_ref_cnt_reg[12]_i_1_O_UNCONNECTED [3:2],\\oclkdelay_ref_cnt_reg[12]_i_1_n_6 ,\\oclkdelay_ref_cnt_reg[12]_i_1_n_7 }),\n .S({1'b0,1'b0,\\oclkdelay_ref_cnt[12]_i_2_n_0 ,\\oclkdelay_ref_cnt[12]_i_3_n_0 }));\n FDSE #(\n .INIT(1'b1)) \n \\oclkdelay_ref_cnt_reg[13] \n (.C(CLK),\n .CE(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .D(\\oclkdelay_ref_cnt_reg[12]_i_1_n_6 ),\n .Q(oclkdelay_ref_cnt_reg[13]),\n .S(\\oclkdelay_ref_cnt[0]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\oclkdelay_ref_cnt_reg[1] \n (.C(CLK),\n .CE(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .D(\\oclkdelay_ref_cnt_reg[0]_i_2_n_6 ),\n .Q(oclkdelay_ref_cnt_reg[1]),\n .S(\\oclkdelay_ref_cnt[0]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\oclkdelay_ref_cnt_reg[2] \n (.C(CLK),\n .CE(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .D(\\oclkdelay_ref_cnt_reg[0]_i_2_n_5 ),\n .Q(oclkdelay_ref_cnt_reg[2]),\n .S(\\oclkdelay_ref_cnt[0]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\oclkdelay_ref_cnt_reg[3] \n (.C(CLK),\n .CE(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .D(\\oclkdelay_ref_cnt_reg[0]_i_2_n_4 ),\n .Q(oclkdelay_ref_cnt_reg[3]),\n .S(\\oclkdelay_ref_cnt[0]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\oclkdelay_ref_cnt_reg[4] \n (.C(CLK),\n .CE(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .D(\\oclkdelay_ref_cnt_reg[4]_i_1_n_7 ),\n .Q(oclkdelay_ref_cnt_reg[4]),\n .S(\\oclkdelay_ref_cnt[0]_i_1_n_0 ));\n CARRY4 \\oclkdelay_ref_cnt_reg[4]_i_1 \n (.CI(\\oclkdelay_ref_cnt_reg[0]_i_2_n_0 ),\n .CO({\\oclkdelay_ref_cnt_reg[4]_i_1_n_0 ,\\oclkdelay_ref_cnt_reg[4]_i_1_n_1 ,\\oclkdelay_ref_cnt_reg[4]_i_1_n_2 ,\\oclkdelay_ref_cnt_reg[4]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b1,1'b1,1'b1,1'b1}),\n .O({\\oclkdelay_ref_cnt_reg[4]_i_1_n_4 ,\\oclkdelay_ref_cnt_reg[4]_i_1_n_5 ,\\oclkdelay_ref_cnt_reg[4]_i_1_n_6 ,\\oclkdelay_ref_cnt_reg[4]_i_1_n_7 }),\n .S({\\oclkdelay_ref_cnt[4]_i_2_n_0 ,\\oclkdelay_ref_cnt[4]_i_3_n_0 ,\\oclkdelay_ref_cnt[4]_i_4_n_0 ,\\oclkdelay_ref_cnt[4]_i_5_n_0 }));\n FDSE #(\n .INIT(1'b1)) \n \\oclkdelay_ref_cnt_reg[5] \n (.C(CLK),\n .CE(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .D(\\oclkdelay_ref_cnt_reg[4]_i_1_n_6 ),\n .Q(oclkdelay_ref_cnt_reg[5]),\n .S(\\oclkdelay_ref_cnt[0]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\oclkdelay_ref_cnt_reg[6] \n (.C(CLK),\n .CE(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .D(\\oclkdelay_ref_cnt_reg[4]_i_1_n_5 ),\n .Q(oclkdelay_ref_cnt_reg[6]),\n .R(\\oclkdelay_ref_cnt[0]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\oclkdelay_ref_cnt_reg[7] \n (.C(CLK),\n .CE(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .D(\\oclkdelay_ref_cnt_reg[4]_i_1_n_4 ),\n .Q(oclkdelay_ref_cnt_reg[7]),\n .S(\\oclkdelay_ref_cnt[0]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\oclkdelay_ref_cnt_reg[8] \n (.C(CLK),\n .CE(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .D(\\oclkdelay_ref_cnt_reg[8]_i_1_n_7 ),\n .Q(oclkdelay_ref_cnt_reg[8]),\n .S(\\oclkdelay_ref_cnt[0]_i_1_n_0 ));\n CARRY4 \\oclkdelay_ref_cnt_reg[8]_i_1 \n (.CI(\\oclkdelay_ref_cnt_reg[4]_i_1_n_0 ),\n .CO({\\oclkdelay_ref_cnt_reg[8]_i_1_n_0 ,\\oclkdelay_ref_cnt_reg[8]_i_1_n_1 ,\\oclkdelay_ref_cnt_reg[8]_i_1_n_2 ,\\oclkdelay_ref_cnt_reg[8]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b1,1'b1,1'b1,1'b1}),\n .O({\\oclkdelay_ref_cnt_reg[8]_i_1_n_4 ,\\oclkdelay_ref_cnt_reg[8]_i_1_n_5 ,\\oclkdelay_ref_cnt_reg[8]_i_1_n_6 ,\\oclkdelay_ref_cnt_reg[8]_i_1_n_7 }),\n .S({\\oclkdelay_ref_cnt[8]_i_2_n_0 ,\\oclkdelay_ref_cnt[8]_i_3_n_0 ,\\oclkdelay_ref_cnt[8]_i_4_n_0 ,\\oclkdelay_ref_cnt[8]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\oclkdelay_ref_cnt_reg[9] \n (.C(CLK),\n .CE(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .D(\\oclkdelay_ref_cnt_reg[8]_i_1_n_6 ),\n .Q(oclkdelay_ref_cnt_reg[9]),\n .R(\\oclkdelay_ref_cnt[0]_i_1_n_0 ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/oclkdelay_start_dly_r_reg \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/oclkdelay_start_dly_r_reg[4]_srl5 \" *) \n SRL16E #(\n .INIT(16'h0000)) \n \\oclkdelay_start_dly_r_reg[4]_srl5 \n (.A0(1'b0),\n .A1(1'b0),\n .A2(1'b1),\n .A3(1'b0),\n .CE(1'b1),\n .CLK(CLK),\n .D(oclkdelay_calib_start_pre),\n .Q(\\oclkdelay_start_dly_r_reg[4]_srl5_n_0 ));\n LUT6 #(\n .INIT(64'h0000000020000000)) \n \\oclkdelay_start_dly_r_reg[4]_srl5_i_1 \n (.I0(Q[4]),\n .I1(Q[5]),\n .I2(Q[3]),\n .I3(Q[2]),\n .I4(\\init_state_r_reg_n_0_[3] ),\n .I5(prbs_rdlvl_start_i_2_n_0),\n .O(oclkdelay_calib_start_pre));\n FDRE #(\n .INIT(1'b0)) \n \\oclkdelay_start_dly_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\oclkdelay_start_dly_r_reg[4]_srl5_n_0 ),\n .Q(oclkdelay_start_dly_r),\n .R(1'b0));\n LUT3 #(\n .INIT(8'h02)) \n \\odd_cwl.phy_cas_n[1]_i_1 \n (.I0(\\odd_cwl.phy_cas_n_reg[1]_0 ),\n .I1(\\odd_cwl.phy_ras_n[1]_i_2_n_0 ),\n .I2(\\cnt_init_mr_r_reg[1]_0 ),\n .O(\\odd_cwl.phy_cas_n[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\odd_cwl.phy_cas_n_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\odd_cwl.phy_cas_n[1]_i_1_n_0 ),\n .Q(phy_cas_n),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h1)) \n \\odd_cwl.phy_ras_n[1]_i_1 \n (.I0(\\DDR3_1rank.phy_int_cs_n[1]_i_6_n_0 ),\n .I1(\\odd_cwl.phy_ras_n[1]_i_2_n_0 ),\n .O(\\odd_cwl.phy_ras_n[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hEEEEEEEEEEEEEEEF)) \n \\odd_cwl.phy_ras_n[1]_i_2 \n (.I0(\\DDR3_1rank.phy_int_cs_n[1]_i_5_n_0 ),\n .I1(reg_ctrl_cnt_r),\n .I2(Q[5]),\n .I3(Q[4]),\n .I4(Q[3]),\n .I5(read_calib_reg_0),\n .O(\\odd_cwl.phy_ras_n[1]_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\odd_cwl.phy_ras_n_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\odd_cwl.phy_ras_n[1]_i_1_n_0 ),\n .Q(phy_ras_n),\n .R(1'b0));\n LUT3 #(\n .INIT(8'h04)) \n \\odd_cwl.phy_we_n[1]_i_1 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),\n .I1(\\calib_cmd[2]_i_2_n_0 ),\n .I2(\\odd_cwl.phy_ras_n[1]_i_2_n_0 ),\n .O(\\odd_cwl.phy_we_n[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\odd_cwl.phy_we_n_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\odd_cwl.phy_we_n[1]_i_1_n_0 ),\n .Q(phy_we_n),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h000000000000000E)) \n \\one_rank.stg1_wr_done_i_1 \n (.I0(\\one_rank.stg1_wr_done_reg_0 ),\n .I1(stg1_wr_done),\n .I2(\\reg_ctrl_cnt_r_reg[3]_0 ),\n .I3(rdlvl_last_byte_done),\n .I4(prbs_rdlvl_done_pulse),\n .I5(complex_byte_rd_done),\n .O(\\one_rank.stg1_wr_done_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000020)) \n \\one_rank.stg1_wr_done_i_2 \n (.I0(Q[1]),\n .I1(Q[3]),\n .I2(Q[0]),\n .I3(Q[5]),\n .I4(Q[4]),\n .I5(\\init_state_r[4]_i_5_n_0 ),\n .O(stg1_wr_done));\n FDRE #(\n .INIT(1'b0)) \n \\one_rank.stg1_wr_done_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\one_rank.stg1_wr_done_i_1_n_0 ),\n .Q(\\one_rank.stg1_wr_done_reg_0 ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000000E0E0E)) \n \\one_rank_complex.complex_wr_done_i_1 \n (.I0(complex_wr_done),\n .I1(\\one_rank_complex.complex_wr_done_i_2_n_0 ),\n .I2(\\one_rank_complex.complex_wr_done_i_3_n_0 ),\n .I3(prbs_rdlvl_done_reg),\n .I4(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .I5(\\one_rank_complex.complex_wr_done_i_4_n_0 ),\n .O(\\one_rank_complex.complex_wr_done_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000800000000000)) \n \\one_rank_complex.complex_wr_done_i_2 \n (.I0(\\one_rank_complex.complex_wr_done_i_5_n_0 ),\n .I1(complex_wait_cnt_reg__0[2]),\n .I2(complex_wait_cnt_reg__0[3]),\n .I3(complex_row1_wr_done),\n .I4(complex_wait_cnt_reg__0[1]),\n .I5(complex_wait_cnt_reg__0[0]),\n .O(\\one_rank_complex.complex_wr_done_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000080000)) \n \\one_rank_complex.complex_wr_done_i_3 \n (.I0(complex_byte_rd_done),\n .I1(Q[1]),\n .I2(\\init_state_r_reg_n_0_[3] ),\n .I3(Q[0]),\n .I4(Q[2]),\n .I5(complex_oclkdelay_calib_start_int_i_2_n_0),\n .O(\\one_rank_complex.complex_wr_done_i_3_n_0 ));\n LUT3 #(\n .INIT(8'hFE)) \n \\one_rank_complex.complex_wr_done_i_4 \n (.I0(\\reg_ctrl_cnt_r_reg[3]_0 ),\n .I1(rdlvl_last_byte_done),\n .I2(prbs_rdlvl_done_pulse),\n .O(\\one_rank_complex.complex_wr_done_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair513\" *) \n LUT5 #(\n .INIT(32'h00001800)) \n \\one_rank_complex.complex_wr_done_i_5 \n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(\\init_state_r_reg_n_0_[3] ),\n .I3(Q[2]),\n .I4(complex_oclkdelay_calib_start_int_i_2_n_0),\n .O(\\one_rank_complex.complex_wr_done_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\one_rank_complex.complex_wr_done_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\one_rank_complex.complex_wr_done_i_1_n_0 ),\n .Q(complex_wr_done),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_10__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [231]),\n .I1(phy_wrdata[255]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_2 [7]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_13 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_10__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [239]),\n .I1(phy_wrdata[255]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_3 [7]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_21 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_10__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [247]),\n .I1(phy_wrdata[255]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_4 [7]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_29 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_10__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [254]),\n .I1(phy_wrdata[254]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_5 [15]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_36 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_11__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [199]),\n .I1(phy_wrdata[223]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_2 [6]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_13 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_11__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [207]),\n .I1(phy_wrdata[223]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_3 [6]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_21 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_11__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [215]),\n .I1(phy_wrdata[223]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_4 [6]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_29 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_11__6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [222]),\n .I1(phy_wrdata[222]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_5 [14]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_36 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_12__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [167]),\n .I1(phy_wrdata[191]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_2 [5]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_13 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_12__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [175]),\n .I1(phy_wrdata[191]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_3 [5]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_21 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_12__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [183]),\n .I1(phy_wrdata[191]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_4 [5]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_29 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_12__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [190]),\n .I1(phy_wrdata[190]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_5 [13]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_36 [5]));\n LUT5 #(\n .INIT(32'hB8B8FF00)) \n out_fifo_i_13__2\n (.I0(mc_odt),\n .I1(init_calib_complete_reg_rep__6),\n .I2(calib_odt),\n .I3(\\rd_ptr_reg[3]_0 [3]),\n .I4(\\my_empty_reg[1]_1 ),\n .O(D5[3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_13__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [135]),\n .I1(phy_wrdata[159]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_2 [4]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_13 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_13__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [143]),\n .I1(phy_wrdata[159]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_3 [4]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_21 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_13__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [151]),\n .I1(phy_wrdata[159]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_4 [4]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_29 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_13__6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [158]),\n .I1(phy_wrdata[158]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_5 [12]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_36 [4]));\n LUT5 #(\n .INIT(32'hB8B8FF00)) \n out_fifo_i_14__1\n (.I0(mc_odt),\n .I1(init_calib_complete_reg_rep__6),\n .I2(calib_odt),\n .I3(\\rd_ptr_reg[3]_0 [2]),\n .I4(\\my_empty_reg[1]_1 ),\n .O(D5[2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_14__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [103]),\n .I1(phy_wrdata[127]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_2 [3]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_13 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_14__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [111]),\n .I1(phy_wrdata[127]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_3 [3]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_21 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_14__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [119]),\n .I1(phy_wrdata[127]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_4 [3]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_29 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_14__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [126]),\n .I1(phy_wrdata[126]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_5 [11]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_36 [3]));\n LUT4 #(\n .INIT(16'hEEF0)) \n out_fifo_i_14__6\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),\n .I1(init_calib_complete_reg_rep__0),\n .I2(\\rd_ptr_reg[3]_1 [3]),\n .I3(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7] [3]));\n LUT5 #(\n .INIT(32'hB8B8FF00)) \n out_fifo_i_15__0\n (.I0(mc_odt),\n .I1(init_calib_complete_reg_rep__6),\n .I2(calib_odt),\n .I3(\\rd_ptr_reg[3]_0 [1]),\n .I4(\\my_empty_reg[1]_1 ),\n .O(D5[1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_15__1\n (.I0(mc_address[26]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_1 [2]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7] [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_15__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [71]),\n .I1(phy_wrdata[95]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_2 [2]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_13 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_15__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [79]),\n .I1(phy_wrdata[95]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_3 [2]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_21 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_15__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [87]),\n .I1(phy_wrdata[95]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_4 [2]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_29 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_15__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [94]),\n .I1(phy_wrdata[94]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_5 [10]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_36 [2]));\n LUT5 #(\n .INIT(32'hB8B8FF00)) \n out_fifo_i_16__0\n (.I0(mc_odt),\n .I1(init_calib_complete_reg_rep__6),\n .I2(calib_odt),\n .I3(\\rd_ptr_reg[3]_0 [0]),\n .I4(\\my_empty_reg[1]_1 ),\n .O(D5[0]));\n LUT5 #(\n .INIT(32'hB8B8FF00)) \n out_fifo_i_16__1\n (.I0(mc_we_n),\n .I1(init_calib_complete_reg_rep__6),\n .I2(phy_we_n),\n .I3(mem_out[1]),\n .I4(\\my_empty_reg[1]_0 ),\n .O(D1));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_16__2\n (.I0(mc_address[15]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_1 [1]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7] [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_16__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [39]),\n .I1(phy_wrdata[63]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_2 [1]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_13 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_16__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [47]),\n .I1(phy_wrdata[63]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_3 [1]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_21 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_16__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [55]),\n .I1(phy_wrdata[63]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_4 [1]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_29 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_16__6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [62]),\n .I1(phy_wrdata[62]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_5 [9]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_36 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_17__0\n (.I0(mc_address[5]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),\n .I2(init_calib_complete_reg_rep__6),\n .I3(\\rd_ptr_reg[3]_1 [0]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7] [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_17__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [7]),\n .I1(phy_wrdata[31]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_2 [0]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_13 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_17__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [15]),\n .I1(phy_wrdata[31]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_3 [0]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_21 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_17__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [23]),\n .I1(phy_wrdata[31]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_4 [0]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_29 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_17__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [30]),\n .I1(phy_wrdata[30]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_5 [8]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_36 [0]));\n LUT5 #(\n .INIT(32'hB8B8FF00)) \n out_fifo_i_18__2\n (.I0(mc_cas_n),\n .I1(init_calib_complete_reg_rep__6),\n .I2(phy_cas_n),\n .I3(\\rd_ptr_reg[3] [0]),\n .I4(\\my_empty_reg[1] ),\n .O(D2));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_18__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [230]),\n .I1(phy_wrdata[254]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_2 [15]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_12 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_18__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [238]),\n .I1(phy_wrdata[254]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_3 [15]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_20 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_18__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [246]),\n .I1(phy_wrdata[254]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_4 [15]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_28 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_18__6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [253]),\n .I1(phy_wrdata[253]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_5 [23]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_35 [7]));\n LUT5 #(\n .INIT(32'hB8B8FF00)) \n out_fifo_i_19__1\n (.I0(mc_cke),\n .I1(init_calib_complete_reg_rep__6),\n .I2(calib_cke),\n .I3(\\rd_ptr_reg[3]_0 [7]),\n .I4(\\my_empty_reg[1]_1 ),\n .O(D6[3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_19__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [198]),\n .I1(phy_wrdata[222]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_2 [14]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_12 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_19__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [206]),\n .I1(phy_wrdata[222]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_3 [14]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_20 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_19__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [214]),\n .I1(phy_wrdata[222]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_4 [14]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_28 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_19__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [221]),\n .I1(phy_wrdata[221]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_5 [22]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_35 [6]));\n LUT5 #(\n .INIT(32'hB8B8FF00)) \n out_fifo_i_20__1\n (.I0(mc_cke),\n .I1(init_calib_complete_reg_rep__6),\n .I2(calib_cke),\n .I3(\\rd_ptr_reg[3]_0 [6]),\n .I4(\\my_empty_reg[1]_1 ),\n .O(D6[2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_20__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [166]),\n .I1(phy_wrdata[190]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_2 [13]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_12 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_20__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [174]),\n .I1(phy_wrdata[190]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_3 [13]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_20 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_20__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [182]),\n .I1(phy_wrdata[190]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_4 [13]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_28 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_20__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [189]),\n .I1(phy_wrdata[189]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_5 [21]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_35 [5]));\n LUT5 #(\n .INIT(32'hB8B8FF00)) \n out_fifo_i_21__1\n (.I0(mc_cke),\n .I1(init_calib_complete_reg_rep__6),\n .I2(calib_cke),\n .I3(\\rd_ptr_reg[3]_0 [5]),\n .I4(\\my_empty_reg[1]_1 ),\n .O(D6[1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_21__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [134]),\n .I1(phy_wrdata[158]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_2 [12]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_12 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_21__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [142]),\n .I1(phy_wrdata[158]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_3 [12]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_20 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_21__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [150]),\n .I1(phy_wrdata[158]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_4 [12]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_28 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_21__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [157]),\n .I1(phy_wrdata[157]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_5 [20]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_35 [4]));\n LUT5 #(\n .INIT(32'hB8B8FF00)) \n out_fifo_i_22__0\n (.I0(mc_cke),\n .I1(init_calib_complete_reg_rep__6),\n .I2(calib_cke),\n .I3(\\rd_ptr_reg[3]_0 [4]),\n .I4(\\my_empty_reg[1]_1 ),\n .O(D6[0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_22__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [102]),\n .I1(phy_wrdata[126]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_2 [11]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_12 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_22__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [110]),\n .I1(phy_wrdata[126]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_3 [11]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_20 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_22__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [118]),\n .I1(phy_wrdata[126]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_4 [11]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_28 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_22__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [125]),\n .I1(phy_wrdata[125]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_5 [19]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_35 [3]));\n LUT4 #(\n .INIT(16'hEEF0)) \n out_fifo_i_22__5\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),\n .I1(init_calib_complete_reg_rep__0),\n .I2(\\rd_ptr_reg[3]_1 [7]),\n .I3(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_0 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_23__1\n (.I0(mc_address[27]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_1 [6]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_0 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_23__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [70]),\n .I1(phy_wrdata[94]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_2 [10]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_12 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_23__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [78]),\n .I1(phy_wrdata[94]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_3 [10]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_20 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_23__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [86]),\n .I1(phy_wrdata[94]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_4 [10]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_28 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_23__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [93]),\n .I1(phy_wrdata[93]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_5 [18]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_35 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_24__1\n (.I0(mc_address[16]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_1 [5]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_0 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_24__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [38]),\n .I1(phy_wrdata[62]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_2 [9]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_12 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_24__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [46]),\n .I1(phy_wrdata[62]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_3 [9]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_20 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_24__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [54]),\n .I1(phy_wrdata[62]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_4 [9]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_28 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_24__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [61]),\n .I1(phy_wrdata[61]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_5 [17]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_35 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_25__0\n (.I0(mc_address[6]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),\n .I2(init_calib_complete_reg_rep__6),\n .I3(\\rd_ptr_reg[3]_1 [4]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_0 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_25__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [6]),\n .I1(phy_wrdata[30]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_2 [8]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_12 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_25__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [14]),\n .I1(phy_wrdata[30]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_3 [8]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_20 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_25__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [22]),\n .I1(phy_wrdata[30]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_4 [8]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_28 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_25__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [29]),\n .I1(phy_wrdata[29]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_5 [16]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_35 [0]));\n LUT5 #(\n .INIT(32'hB8B8FF00)) \n out_fifo_i_26__1\n (.I0(mc_ras_n),\n .I1(init_calib_complete_reg_rep__6),\n .I2(phy_ras_n),\n .I3(\\rd_ptr_reg[3] [1]),\n .I4(\\my_empty_reg[1] ),\n .O(D3));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_26__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [229]),\n .I1(phy_wrdata[253]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_2 [23]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_11 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_26__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [237]),\n .I1(phy_wrdata[253]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_3 [23]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_19 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_26__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [245]),\n .I1(phy_wrdata[253]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_4 [23]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_27 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_26__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [252]),\n .I1(phy_wrdata[252]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_5 [31]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_34 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_27__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [197]),\n .I1(phy_wrdata[221]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_2 [22]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_11 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_27__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [205]),\n .I1(phy_wrdata[221]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_3 [22]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_19 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_27__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [213]),\n .I1(phy_wrdata[221]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_4 [22]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_27 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_27__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [220]),\n .I1(phy_wrdata[220]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_5 [30]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_34 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_28__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [165]),\n .I1(phy_wrdata[189]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_2 [21]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_11 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_28__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [173]),\n .I1(phy_wrdata[189]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_3 [21]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_19 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_28__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [181]),\n .I1(phy_wrdata[189]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_4 [21]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_27 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_28__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [188]),\n .I1(phy_wrdata[188]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_5 [29]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_34 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_29__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [133]),\n .I1(phy_wrdata[157]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_2 [20]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_11 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_29__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [141]),\n .I1(phy_wrdata[157]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_3 [20]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_19 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_29__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [149]),\n .I1(phy_wrdata[157]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_4 [20]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_27 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_29__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [156]),\n .I1(phy_wrdata[156]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_5 [28]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_34 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_2__6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [255]),\n .I1(phy_wrdata[255]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_5 [7]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_37 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_30__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [101]),\n .I1(phy_wrdata[125]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_2 [19]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_11 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_30__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [109]),\n .I1(phy_wrdata[125]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_3 [19]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_19 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_30__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [117]),\n .I1(phy_wrdata[125]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_4 [19]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_27 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_30__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [124]),\n .I1(phy_wrdata[124]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_5 [27]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_34 [3]));\n LUT4 #(\n .INIT(16'hEEF0)) \n out_fifo_i_30__5\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),\n .I1(init_calib_complete_reg_rep__0),\n .I2(\\rd_ptr_reg[3]_1 [11]),\n .I3(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_1 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_31__0\n (.I0(mc_address[28]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_1 [10]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_1 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_31__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [69]),\n .I1(phy_wrdata[93]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_2 [18]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_11 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_31__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [77]),\n .I1(phy_wrdata[93]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_3 [18]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_19 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_31__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [85]),\n .I1(phy_wrdata[93]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_4 [18]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_27 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_31__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [92]),\n .I1(phy_wrdata[92]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_5 [26]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_34 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_32\n (.I0(mc_address[17]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_1 [9]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_1 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_32__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [37]),\n .I1(phy_wrdata[61]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_2 [17]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_11 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_32__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [45]),\n .I1(phy_wrdata[61]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_3 [17]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_19 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_32__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [53]),\n .I1(phy_wrdata[61]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_4 [17]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_27 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_32__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [60]),\n .I1(phy_wrdata[60]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_5 [25]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_34 [1]));\n LUT4 #(\n .INIT(16'hEEF0)) \n out_fifo_i_32__4\n (.I0(phy_bank[9]),\n .I1(init_calib_complete_reg_rep),\n .I2(\\rd_ptr_reg[3] [5]),\n .I3(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_2 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_33\n (.I0(mc_address[7]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),\n .I2(init_calib_complete_reg_rep__6),\n .I3(\\rd_ptr_reg[3]_1 [8]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_1 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_33__0\n (.I0(mc_bank[6]),\n .I1(phy_bank[9]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3] [4]),\n .I4(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_2 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_33__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [5]),\n .I1(phy_wrdata[29]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_2 [16]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_11 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_33__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [13]),\n .I1(phy_wrdata[29]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_3 [16]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_19 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_33__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [21]),\n .I1(phy_wrdata[29]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_4 [16]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_27 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_33__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [28]),\n .I1(phy_wrdata[28]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_5 [24]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_34 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_34__0\n (.I0(mc_bank[3]),\n .I1(phy_bank[9]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3] [3]),\n .I4(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_2 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_34__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [228]),\n .I1(phy_wrdata[252]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_2 [31]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_10 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_34__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [236]),\n .I1(phy_wrdata[252]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_3 [31]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_18 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_34__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [244]),\n .I1(phy_wrdata[252]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_4 [31]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_26 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_34__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [251]),\n .I1(phy_wrdata[251]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_5 [39]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_33 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_35__0\n (.I0(mc_bank[0]),\n .I1(phy_bank[9]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3] [2]),\n .I4(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_2 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_35__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [196]),\n .I1(phy_wrdata[220]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_2 [30]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_10 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_35__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [204]),\n .I1(phy_wrdata[220]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_3 [30]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_18 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_35__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [212]),\n .I1(phy_wrdata[220]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_4 [30]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_26 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_35__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [219]),\n .I1(phy_wrdata[219]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_5 [38]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_33 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_36__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [164]),\n .I1(phy_wrdata[188]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_2 [29]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_10 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_36__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [172]),\n .I1(phy_wrdata[188]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_3 [29]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_18 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_36__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [180]),\n .I1(phy_wrdata[188]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_4 [29]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_26 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_36__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [187]),\n .I1(phy_wrdata[187]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_5 [37]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_33 [5]));\n LUT4 #(\n .INIT(16'hEEF0)) \n out_fifo_i_36__4\n (.I0(phy_bank[11]),\n .I1(init_calib_complete_reg_rep),\n .I2(\\rd_ptr_reg[3] [13]),\n .I3(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_1 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_37__0\n (.I0(mc_bank[8]),\n .I1(phy_bank[11]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3] [12]),\n .I4(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_1 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_37__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [132]),\n .I1(phy_wrdata[156]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_2 [28]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_10 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_37__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [140]),\n .I1(phy_wrdata[156]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_3 [28]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_18 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_37__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [148]),\n .I1(phy_wrdata[156]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_4 [28]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_26 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_37__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [155]),\n .I1(phy_wrdata[155]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_5 [36]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_33 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_38\n (.I0(mc_bank[5]),\n .I1(phy_bank[11]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3] [11]),\n .I4(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_1 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_38__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [100]),\n .I1(phy_wrdata[124]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_2 [27]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_10 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_38__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [108]),\n .I1(phy_wrdata[124]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_3 [27]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_18 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_38__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [116]),\n .I1(phy_wrdata[124]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_4 [27]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_26 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_38__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [123]),\n .I1(phy_wrdata[123]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_5 [35]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_33 [3]));\n LUT4 #(\n .INIT(16'hEEF0)) \n out_fifo_i_38__4\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),\n .I1(init_calib_complete_reg_rep__0),\n .I2(\\rd_ptr_reg[3]_1 [15]),\n .I3(\\my_empty_reg[1]_2 ),\n .O(D4[3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_39\n (.I0(mc_address[29]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_1 [14]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(D4[2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_39__0\n (.I0(mc_bank[2]),\n .I1(phy_bank[11]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3] [10]),\n .I4(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_1 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_39__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [68]),\n .I1(phy_wrdata[92]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_2 [26]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_10 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_39__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [76]),\n .I1(phy_wrdata[92]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_3 [26]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_18 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_39__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [84]),\n .I1(phy_wrdata[92]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_4 [26]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_26 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_39__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [91]),\n .I1(phy_wrdata[91]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_5 [34]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_33 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_3__6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [223]),\n .I1(phy_wrdata[223]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_5 [6]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_37 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_40\n (.I0(mc_address[18]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_1 [13]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(D4[1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_40__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [36]),\n .I1(phy_wrdata[60]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_2 [25]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_10 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_40__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [44]),\n .I1(phy_wrdata[60]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_3 [25]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_18 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_40__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [52]),\n .I1(phy_wrdata[60]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_4 [25]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_26 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_40__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [59]),\n .I1(phy_wrdata[59]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_5 [33]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_33 [1]));\n (* SOFT_HLUTNM = \"soft_lutpair551\" *) \n LUT4 #(\n .INIT(16'hEEF0)) \n out_fifo_i_40__4\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .I1(init_calib_complete_reg_rep__0),\n .I2(\\rd_ptr_reg[3] [9]),\n .I3(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_1 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_41\n (.I0(mc_address[8]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),\n .I2(init_calib_complete_reg_rep__6),\n .I3(\\rd_ptr_reg[3]_1 [12]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(D4[0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_41__0\n (.I0(mc_address[25]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3] [8]),\n .I4(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_1 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_41__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [4]),\n .I1(phy_wrdata[28]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_2 [24]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_10 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_41__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [12]),\n .I1(phy_wrdata[28]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_3 [24]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_18 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_41__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [20]),\n .I1(phy_wrdata[28]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_4 [24]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_26 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_41__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [27]),\n .I1(phy_wrdata[27]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_5 [32]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_33 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_42__0\n (.I0(mc_address[14]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3] [7]),\n .I4(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_1 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_42__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [227]),\n .I1(phy_wrdata[251]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_2 [39]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_9 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_42__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [235]),\n .I1(phy_wrdata[251]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_3 [39]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_17 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_42__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [243]),\n .I1(phy_wrdata[251]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_4 [39]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_25 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_42__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [250]),\n .I1(phy_wrdata[250]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_5 [47]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_32 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_43__0\n (.I0(mc_address[4]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .I2(init_calib_complete_reg_rep__6),\n .I3(\\rd_ptr_reg[3] [6]),\n .I4(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_1 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_43__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [195]),\n .I1(phy_wrdata[219]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_2 [38]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_9 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_43__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [203]),\n .I1(phy_wrdata[219]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_3 [38]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_17 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_43__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [211]),\n .I1(phy_wrdata[219]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_4 [38]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_25 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_43__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [218]),\n .I1(phy_wrdata[218]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_5 [46]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_32 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_44__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [163]),\n .I1(phy_wrdata[187]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_2 [37]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_9 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_44__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [171]),\n .I1(phy_wrdata[187]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_3 [37]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_17 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_44__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [179]),\n .I1(phy_wrdata[187]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_4 [37]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_25 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_44__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [186]),\n .I1(phy_wrdata[186]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_5 [45]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_32 [5]));\n LUT4 #(\n .INIT(16'hEEF0)) \n out_fifo_i_44__4\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),\n .I1(init_calib_complete_reg_rep__0),\n .I2(\\rd_ptr_reg[3] [21]),\n .I3(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_0 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_45__0\n (.I0(mc_address[21]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3] [20]),\n .I4(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_0 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_45__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [131]),\n .I1(phy_wrdata[155]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_2 [36]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_9 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_45__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [139]),\n .I1(phy_wrdata[155]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_3 [36]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_17 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_45__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [147]),\n .I1(phy_wrdata[155]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_4 [36]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_25 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_45__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [154]),\n .I1(phy_wrdata[154]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_5 [44]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_32 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_46\n (.I0(mc_cas_n),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),\n .I2(init_calib_complete_reg_rep__6),\n .I3(\\rd_ptr_reg[3] [19]),\n .I4(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_0 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_46__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [99]),\n .I1(phy_wrdata[123]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_2 [35]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_9 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_46__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [107]),\n .I1(phy_wrdata[123]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_3 [35]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_17 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_46__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [115]),\n .I1(phy_wrdata[123]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_4 [35]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_25 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_46__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [122]),\n .I1(phy_wrdata[122]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_5 [43]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_32 [3]));\n (* SOFT_HLUTNM = \"soft_lutpair555\" *) \n LUT4 #(\n .INIT(16'hEEF0)) \n out_fifo_i_46__4\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),\n .I1(init_calib_complete_reg_rep__0),\n .I2(\\rd_ptr_reg[3]_1 [19]),\n .I3(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_2 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_47\n (.I0(mc_address[0]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),\n .I2(init_calib_complete_reg_rep__6),\n .I3(\\rd_ptr_reg[3] [18]),\n .I4(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_0 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_47__0\n (.I0(mc_address[30]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_1 [18]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_2 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_47__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [67]),\n .I1(phy_wrdata[91]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_2 [34]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_9 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_47__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [75]),\n .I1(phy_wrdata[91]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_3 [34]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_17 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_47__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [83]),\n .I1(phy_wrdata[91]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_4 [34]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_25 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_47__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [90]),\n .I1(phy_wrdata[90]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_5 [42]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_32 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_48\n (.I0(mc_address[19]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_1 [17]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_2 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_48__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [35]),\n .I1(phy_wrdata[59]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_2 [33]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_9 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_48__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [43]),\n .I1(phy_wrdata[59]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_3 [33]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_17 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_48__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [51]),\n .I1(phy_wrdata[59]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_4 [33]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_25 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_48__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [58]),\n .I1(phy_wrdata[58]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_5 [41]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_32 [1]));\n LUT4 #(\n .INIT(16'hEEF0)) \n out_fifo_i_48__4\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),\n .I1(init_calib_complete_reg_rep__0),\n .I2(\\rd_ptr_reg[3] [17]),\n .I3(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_0 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_49\n (.I0(mc_address[9]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),\n .I2(init_calib_complete_reg_rep__6),\n .I3(\\rd_ptr_reg[3]_1 [16]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_2 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_49__0\n (.I0(mc_address[22]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3] [16]),\n .I4(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_0 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_49__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [3]),\n .I1(phy_wrdata[27]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_2 [32]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_9 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_49__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [11]),\n .I1(phy_wrdata[27]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_3 [32]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_17 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_49__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [19]),\n .I1(phy_wrdata[27]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_4 [32]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_25 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_49__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [26]),\n .I1(phy_wrdata[26]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_5 [40]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_32 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_4__6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [191]),\n .I1(phy_wrdata[191]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_5 [5]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_37 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_50__0\n (.I0(mc_cas_n),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),\n .I2(init_calib_complete_reg_rep__6),\n .I3(\\rd_ptr_reg[3] [15]),\n .I4(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_0 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_50__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [226]),\n .I1(phy_wrdata[250]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_2 [47]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_8 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_50__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [234]),\n .I1(phy_wrdata[250]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_3 [47]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_16 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_50__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [242]),\n .I1(phy_wrdata[250]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_4 [47]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_24 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_50__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [249]),\n .I1(phy_wrdata[249]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_5 [55]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_31 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_51__0\n (.I0(mc_address[1]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),\n .I2(init_calib_complete_reg_rep__6),\n .I3(\\rd_ptr_reg[3] [14]),\n .I4(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_0 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_51__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [194]),\n .I1(phy_wrdata[218]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_2 [46]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_8 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_51__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [202]),\n .I1(phy_wrdata[218]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_3 [46]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_16 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_51__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [210]),\n .I1(phy_wrdata[218]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_4 [46]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_24 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_51__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [217]),\n .I1(phy_wrdata[217]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_5 [54]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_31 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_52__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [162]),\n .I1(phy_wrdata[186]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_2 [45]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_8 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_52__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [170]),\n .I1(phy_wrdata[186]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_3 [45]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_16 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_52__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [178]),\n .I1(phy_wrdata[186]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_4 [45]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_24 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_52__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [185]),\n .I1(phy_wrdata[185]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_5 [53]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_31 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_53__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [130]),\n .I1(phy_wrdata[154]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_2 [44]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_8 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_53__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [138]),\n .I1(phy_wrdata[154]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_3 [44]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_16 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_53__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [146]),\n .I1(phy_wrdata[154]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_4 [44]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_24 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_53__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [153]),\n .I1(phy_wrdata[153]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_5 [52]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_31 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_54__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [98]),\n .I1(phy_wrdata[122]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_2 [43]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_8 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_54__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [106]),\n .I1(phy_wrdata[122]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_3 [43]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_16 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_54__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [114]),\n .I1(phy_wrdata[122]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_4 [43]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_24 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_54__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [121]),\n .I1(phy_wrdata[121]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_5 [51]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_31 [3]));\n LUT4 #(\n .INIT(16'hEEF0)) \n out_fifo_i_54__4\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),\n .I1(init_calib_complete_reg_rep),\n .I2(\\rd_ptr_reg[3]_1 [23]),\n .I3(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_3 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_55__0\n (.I0(mc_address[31]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_1 [22]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_3 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_55__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [66]),\n .I1(phy_wrdata[90]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_2 [42]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_8 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_55__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [74]),\n .I1(phy_wrdata[90]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_3 [42]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_16 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_55__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [82]),\n .I1(phy_wrdata[90]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_4 [42]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_24 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_55__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [89]),\n .I1(phy_wrdata[89]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_5 [50]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_31 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_56\n (.I0(mc_address[20]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_1 [21]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_3 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_56__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [34]),\n .I1(phy_wrdata[58]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_2 [41]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_8 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_56__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [42]),\n .I1(phy_wrdata[58]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_3 [41]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_16 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_56__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [50]),\n .I1(phy_wrdata[58]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_4 [41]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_24 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_56__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [57]),\n .I1(phy_wrdata[57]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_5 [49]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_31 [1]));\n LUT4 #(\n .INIT(16'hEEF0)) \n out_fifo_i_56__4\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),\n .I1(init_calib_complete_reg_rep__0),\n .I2(\\rd_ptr_reg[3] [25]),\n .I3(\\my_empty_reg[1] ),\n .O(D7[3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_57\n (.I0(mc_address[10]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),\n .I2(init_calib_complete_reg_rep__6),\n .I3(\\rd_ptr_reg[3]_1 [20]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_3 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_57__0\n (.I0(mc_address[23]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3] [24]),\n .I4(\\my_empty_reg[1] ),\n .O(D7[2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_57__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [2]),\n .I1(phy_wrdata[26]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_2 [40]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_8 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_57__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [10]),\n .I1(phy_wrdata[26]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_3 [40]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_16 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_57__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [18]),\n .I1(phy_wrdata[26]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_4 [40]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_24 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_57__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [25]),\n .I1(phy_wrdata[25]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_5 [48]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_31 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_58__0\n (.I0(mc_cas_n),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),\n .I2(init_calib_complete_reg_rep__6),\n .I3(\\rd_ptr_reg[3] [23]),\n .I4(\\my_empty_reg[1] ),\n .O(D7[1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_58__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [225]),\n .I1(phy_wrdata[249]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_2 [55]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_7 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_58__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [233]),\n .I1(phy_wrdata[249]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_3 [55]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_15 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_58__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [241]),\n .I1(phy_wrdata[249]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_4 [55]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_23 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_58__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [248]),\n .I1(phy_wrdata[248]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_5 [63]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_30 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_59__0\n (.I0(mc_address[2]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),\n .I2(init_calib_complete_reg_rep__6),\n .I3(\\rd_ptr_reg[3] [22]),\n .I4(\\my_empty_reg[1] ),\n .O(D7[0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_59__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [193]),\n .I1(phy_wrdata[217]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_2 [54]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_7 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_59__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [201]),\n .I1(phy_wrdata[217]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_3 [54]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_15 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_59__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [209]),\n .I1(phy_wrdata[217]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_4 [54]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_23 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_59__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [216]),\n .I1(phy_wrdata[216]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_5 [62]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_30 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_5__6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [159]),\n .I1(phy_wrdata[159]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_5 [4]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_37 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_60__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [161]),\n .I1(phy_wrdata[185]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_2 [53]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_7 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_60__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [169]),\n .I1(phy_wrdata[185]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_3 [53]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_15 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_60__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [177]),\n .I1(phy_wrdata[185]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_4 [53]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_23 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_60__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [184]),\n .I1(phy_wrdata[184]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_5 [61]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_30 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_61__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [129]),\n .I1(phy_wrdata[153]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_2 [52]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_7 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_61__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [137]),\n .I1(phy_wrdata[153]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_3 [52]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_15 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_61__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [145]),\n .I1(phy_wrdata[153]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_4 [52]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_23 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_61__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [152]),\n .I1(phy_wrdata[152]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_5 [60]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_30 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_62__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [97]),\n .I1(phy_wrdata[121]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_2 [51]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_7 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_62__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [105]),\n .I1(phy_wrdata[121]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_3 [51]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_15 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_62__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [113]),\n .I1(phy_wrdata[121]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_4 [51]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_23 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_62__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [120]),\n .I1(phy_wrdata[120]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_5 [59]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_30 [3]));\n LUT4 #(\n .INIT(16'hEEF0)) \n out_fifo_i_62__4\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ),\n .I1(init_calib_complete_reg_rep),\n .I2(\\rd_ptr_reg[3]_1 [27]),\n .I3(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_4 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_63__0\n (.I0(mc_address[32]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_1 [26]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_4 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_63__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [65]),\n .I1(phy_wrdata[89]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_2 [50]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_7 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_63__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [73]),\n .I1(phy_wrdata[89]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_3 [50]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_15 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_63__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [81]),\n .I1(phy_wrdata[89]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_4 [50]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_23 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_63__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [88]),\n .I1(phy_wrdata[88]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_5 [58]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_30 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_64\n (.I0(mc_cas_n),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_1 [25]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_4 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_64__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [33]),\n .I1(phy_wrdata[57]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_2 [49]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_7 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_64__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [41]),\n .I1(phy_wrdata[57]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_3 [49]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_15 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_64__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [49]),\n .I1(phy_wrdata[57]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_4 [49]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_23 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_64__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [56]),\n .I1(phy_wrdata[56]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_5 [57]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_30 [1]));\n LUT4 #(\n .INIT(16'hEEF0)) \n out_fifo_i_64__4\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I1(init_calib_complete_reg_rep__0),\n .I2(\\rd_ptr_reg[3] [29]),\n .I3(\\my_empty_reg[1] ),\n .O(D8[3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_65\n (.I0(mc_address[11]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ),\n .I2(init_calib_complete_reg_rep__6),\n .I3(\\rd_ptr_reg[3]_1 [24]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_4 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_65__0\n (.I0(mc_address[24]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3] [28]),\n .I4(\\my_empty_reg[1] ),\n .O(D8[2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_65__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [1]),\n .I1(phy_wrdata[25]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_2 [48]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_7 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_65__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [9]),\n .I1(phy_wrdata[25]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_3 [48]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_15 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_65__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [17]),\n .I1(phy_wrdata[25]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_4 [48]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_23 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_65__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [24]),\n .I1(phy_wrdata[24]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_5 [56]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_30 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_66__1\n (.I0(mc_address[13]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3] [27]),\n .I4(\\my_empty_reg[1] ),\n .O(D8[1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_66__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [224]),\n .I1(phy_wrdata[248]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_2 [63]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_6 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_66__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [232]),\n .I1(phy_wrdata[248]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_3 [63]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_14 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_66__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [240]),\n .I1(phy_wrdata[248]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_4 [63]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_22 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_67__1\n (.I0(mc_address[3]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I2(init_calib_complete_reg_rep__6),\n .I3(\\rd_ptr_reg[3] [26]),\n .I4(\\my_empty_reg[1] ),\n .O(D8[0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_67__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [192]),\n .I1(phy_wrdata[216]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_2 [62]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_6 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_67__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [200]),\n .I1(phy_wrdata[216]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_3 [62]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_14 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_67__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [208]),\n .I1(phy_wrdata[216]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_4 [62]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_22 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_68__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [160]),\n .I1(phy_wrdata[184]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_2 [61]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_6 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_68__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [168]),\n .I1(phy_wrdata[184]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_3 [61]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_14 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_68__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [176]),\n .I1(phy_wrdata[184]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_4 [61]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_22 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_69__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [128]),\n .I1(phy_wrdata[152]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_2 [60]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_6 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_69__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [136]),\n .I1(phy_wrdata[152]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_3 [60]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_14 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_69__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [144]),\n .I1(phy_wrdata[152]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_4 [60]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_22 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_6__6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [127]),\n .I1(phy_wrdata[127]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_5 [3]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_37 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_70__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [96]),\n .I1(phy_wrdata[120]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_2 [59]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_6 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_70__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [104]),\n .I1(phy_wrdata[120]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_3 [59]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_14 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_70__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [112]),\n .I1(phy_wrdata[120]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_4 [59]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_22 [3]));\n LUT4 #(\n .INIT(16'hEEF0)) \n out_fifo_i_70__3\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),\n .I1(init_calib_complete_reg_rep),\n .I2(\\rd_ptr_reg[3]_1 [31]),\n .I3(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_5 [3]));\n LUT4 #(\n .INIT(16'hEEF0)) \n out_fifo_i_70__4\n (.I0(phy_bank[10]),\n .I1(init_calib_complete_reg_rep),\n .I2(\\rd_ptr_reg[3] [33]),\n .I3(\\my_empty_reg[1] ),\n .O(D9[3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_71__0\n (.I0(mc_address[33]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_1 [30]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_5 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_71__1\n (.I0(mc_bank[7]),\n .I1(phy_bank[10]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3] [32]),\n .I4(\\my_empty_reg[1] ),\n .O(D9[2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_71__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [64]),\n .I1(phy_wrdata[88]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_2 [58]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_6 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_71__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [72]),\n .I1(phy_wrdata[88]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_3 [58]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_14 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_71__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [80]),\n .I1(phy_wrdata[88]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_4 [58]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_22 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_72__0\n (.I0(mc_ras_n),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_1 [29]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_5 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_72__1\n (.I0(mc_bank[4]),\n .I1(phy_bank[10]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3] [31]),\n .I4(\\my_empty_reg[1] ),\n .O(D9[1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_72__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [32]),\n .I1(phy_wrdata[56]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_2 [57]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_6 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_72__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [40]),\n .I1(phy_wrdata[56]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_3 [57]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_14 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_72__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [48]),\n .I1(phy_wrdata[56]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_4 [57]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_22 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_73__0\n (.I0(mc_address[12]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),\n .I2(init_calib_complete_reg_rep__6),\n .I3(\\rd_ptr_reg[3]_1 [28]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_5 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_73__1\n (.I0(mc_bank[1]),\n .I1(phy_bank[10]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3] [30]),\n .I4(\\my_empty_reg[1] ),\n .O(D9[0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_73__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [0]),\n .I1(phy_wrdata[24]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_2 [56]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_6 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_73__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [8]),\n .I1(phy_wrdata[24]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_3 [56]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_14 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_73__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [16]),\n .I1(phy_wrdata[24]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_4 [56]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_22 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_7__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [95]),\n .I1(phy_wrdata[95]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_5 [2]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_37 [2]));\n LUT5 #(\n .INIT(32'hB8B8FF00)) \n out_fifo_i_8__5\n (.I0(mc_cas_n),\n .I1(init_calib_complete_reg_rep__6),\n .I2(phy_cs_n),\n .I3(mem_out[0]),\n .I4(\\my_empty_reg[1]_0 ),\n .O(D0));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_8__6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [63]),\n .I1(phy_wrdata[63]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_5 [1]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_37 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_9__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [31]),\n .I1(phy_wrdata[31]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_5 [0]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_37 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair588\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\phy_ctl_wd_i1[0]_i_1 \n (.I0(mc_cmd[0]),\n .I1(calib_cmd[0]),\n .I2(init_calib_complete_reg_rep__14),\n .O(\\phy_ctl_wd_i1_reg[24] [0]));\n (* SOFT_HLUTNM = \"soft_lutpair589\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\phy_ctl_wd_i1[17]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_reg[0] ),\n .I1(calib_data_offset_0[0]),\n .I2(init_calib_complete_reg_rep__14),\n .O(\\phy_ctl_wd_i1_reg[24] [3]));\n (* SOFT_HLUTNM = \"soft_lutpair590\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\phy_ctl_wd_i1[18]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_reg[1] ),\n .I1(calib_data_offset_0[1]),\n .I2(init_calib_complete_reg_rep__14),\n .O(\\phy_ctl_wd_i1_reg[24] [4]));\n (* SOFT_HLUTNM = \"soft_lutpair591\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\phy_ctl_wd_i1[19]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_reg[2] ),\n .I1(calib_data_offset_0[2]),\n .I2(init_calib_complete_reg_rep__14),\n .O(\\phy_ctl_wd_i1_reg[24] [5]));\n (* SOFT_HLUTNM = \"soft_lutpair585\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\phy_ctl_wd_i1[1]_i_1 \n (.I0(mc_cmd[1]),\n .I1(calib_cmd[1]),\n .I2(init_calib_complete_reg_rep__14),\n .O(\\phy_ctl_wd_i1_reg[24] [1]));\n (* SOFT_HLUTNM = \"soft_lutpair590\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\phy_ctl_wd_i1[20]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_reg[3] ),\n .I1(calib_data_offset_0[3]),\n .I2(init_calib_complete_reg_rep__14),\n .O(\\phy_ctl_wd_i1_reg[24] [6]));\n (* SOFT_HLUTNM = \"soft_lutpair593\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\phy_ctl_wd_i1[21]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_reg[4] ),\n .I1(calib_data_offset_0[4]),\n .I2(init_calib_complete_reg_rep__14),\n .O(\\phy_ctl_wd_i1_reg[24] [7]));\n (* SOFT_HLUTNM = \"soft_lutpair591\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\phy_ctl_wd_i1[22]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_reg[5] ),\n .I1(calib_data_offset_0[5]),\n .I2(init_calib_complete_reg_rep__14),\n .O(\\phy_ctl_wd_i1_reg[24] [8]));\n (* SOFT_HLUTNM = \"soft_lutpair589\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\phy_ctl_wd_i1[2]_i_1 \n (.I0(mc_cas_n),\n .I1(calib_cmd[2]),\n .I2(init_calib_complete_reg_rep__14),\n .O(\\phy_ctl_wd_i1_reg[24] [2]));\n FDCE #(\n .INIT(1'b0)) \n phy_reset_n_reg\n (.C(CLK),\n .CE(1'b1),\n .CLR(rstdiv0_sync_r1_reg_rep__11),\n .D(cnt_pwron_reset_done_r),\n .Q(phy_reset_n));\n FDRE #(\n .INIT(1'b0)) \n pi_calib_done_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_calib_done_r),\n .Q(pi_calib_done),\n .R(1'b0));\n LUT2 #(\n .INIT(4'hE)) \n pi_calib_done_r_i_1\n (.I0(pi_calib_rank_done_r),\n .I1(pi_calib_done_r),\n .O(pi_calib_done_r_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n pi_calib_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_calib_done_r_i_1_n_0),\n .Q(pi_calib_done_r),\n .R(rstdiv0_sync_r1_reg_rep__11));\n LUT2 #(\n .INIT(4'h2)) \n pi_calib_rank_done_r_i_1\n (.I0(pi_phase_locked_all_r3),\n .I1(pi_phase_locked_all_r4),\n .O(init_next_state1100_out));\n FDRE #(\n .INIT(1'b0)) \n pi_calib_rank_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(init_next_state1100_out),\n .Q(pi_calib_rank_done_r),\n .R(rstdiv0_sync_r1_reg_rep__12));\n LUT2 #(\n .INIT(4'hE)) \n \\pi_dqs_found_all_bank[1]_i_2 \n (.I0(dqs_found_start_r_reg),\n .I1(\\pi_dqs_found_all_bank_reg[1]_0 ),\n .O(\\pi_dqs_found_all_bank_reg[1] ));\n FDRE #(\n .INIT(1'b0)) \n pi_dqs_found_done_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(dqs_found_done_r_reg),\n .Q(pi_dqs_found_done_r1),\n .R(rstdiv0_sync_r1_reg_rep__11));\n LUT5 #(\n .INIT(32'h000000AE)) \n pi_dqs_found_start_i_1\n (.I0(dqs_found_start_r_reg),\n .I1(\\back_to_back_reads_4_1.num_reads[1]_i_2_n_0 ),\n .I2(dqs_found_done_r_reg),\n .I3(wrlvl_byte_redo),\n .I4(rstdiv0_sync_r1_reg_rep__23),\n .O(pi_dqs_found_start_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n pi_dqs_found_start_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_start_i_1_n_0),\n .Q(dqs_found_start_r_reg),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n pi_phase_locked_all_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(A_rst_primitives_reg),\n .Q(pi_phase_locked_all_r1),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n pi_phase_locked_all_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_phase_locked_all_r1),\n .Q(pi_phase_locked_all_r2),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n pi_phase_locked_all_r3_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_phase_locked_all_r2),\n .Q(pi_phase_locked_all_r3),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n pi_phase_locked_all_r4_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_phase_locked_all_r3),\n .Q(pi_phase_locked_all_r4),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000FFFFEEFE)) \n prbs_gen_clk_en_i_1\n (.I0(prbs_gen_clk_en),\n .I1(prbs_gen_clk_en_i_2_n_0),\n .I2(prbs_rdlvl_start_r_reg),\n .I3(prbs_gen_clk_en_i_3_n_0),\n .I4(\\stg1_wr_rd_cnt[8]_i_4_n_0 ),\n .I5(prbs_gen_clk_en040_out),\n .O(prbs_gen_clk_en_i_1_n_0));\n LUT6 #(\n .INIT(64'h20AAAAAA20AA20AA)) \n prbs_gen_clk_en_i_2\n (.I0(rdlvl_stg1_done_r1),\n .I1(prbs_gen_clk_en_i_5_n_0),\n .I2(\\complex_num_writes[3]_i_4_n_0 ),\n .I3(phy_if_empty_r_reg),\n .I4(\\stg1_wr_rd_cnt[4]_i_6_n_0 ),\n .I5(cnt_cmd_done_r_i_1_n_0),\n .O(prbs_gen_clk_en_i_2_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFEF)) \n prbs_gen_clk_en_i_3\n (.I0(prbs_rdlvl_start_i_2_n_0),\n .I1(Q[4]),\n .I2(Q[3]),\n .I3(Q[5]),\n .I4(Q[2]),\n .I5(\\init_state_r_reg_n_0_[3] ),\n .O(prbs_gen_clk_en_i_3_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair549\" *) \n LUT4 #(\n .INIT(16'hEEEF)) \n prbs_gen_clk_en_i_4\n (.I0(prbs_rdlvl_done_reg),\n .I1(rstdiv0_sync_r1_reg_rep__23),\n .I2(wr_victim_inc_i_2_n_0),\n .I3(\\one_rank.stg1_wr_done_reg_0 ),\n .O(prbs_gen_clk_en040_out));\n (* SOFT_HLUTNM = \"soft_lutpair505\" *) \n LUT4 #(\n .INIT(16'hFF7F)) \n prbs_gen_clk_en_i_5\n (.I0(complex_wait_cnt_reg__0[2]),\n .I1(complex_wait_cnt_reg__0[3]),\n .I2(complex_wait_cnt_reg__0[1]),\n .I3(complex_wait_cnt_reg__0[0]),\n .O(prbs_gen_clk_en_i_5_n_0));\n FDRE #(\n .INIT(1'b0)) \n prbs_gen_clk_en_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prbs_gen_clk_en_i_1_n_0),\n .Q(prbs_gen_clk_en),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n prbs_gen_oclk_clk_en_i_1\n (.I0(prbs_gen_oclk_clk_en_i_2_n_0),\n .I1(prbs_gen_oclk_clk_en_i_3_n_0),\n .I2(\\one_rank_complex.complex_wr_done_i_3_n_0 ),\n .I3(prbs_gen_oclk_clk_en_i_4_n_0),\n .I4(prbs_gen_oclk_clk_en_i_5_n_0),\n .I5(prbs_gen_clk_en040_out),\n .O(prbs_gen_oclk_clk_en_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFAE)) \n prbs_gen_oclk_clk_en_i_2\n (.I0(prbs_gen_oclk_clk_en_i_6_n_0),\n .I1(prbs_rdlvl_done_r1),\n .I2(phy_if_empty_r_reg),\n .I3(\\stg1_wr_rd_cnt[8]_i_4_n_0 ),\n .I4(prbs_gen_oclk_clk_en_i_7_n_0),\n .I5(prbs_gen_oclk_clk_en),\n .O(prbs_gen_oclk_clk_en_i_2_n_0));\n LUT6 #(\n .INIT(64'h0000000000002000)) \n prbs_gen_oclk_clk_en_i_3\n (.I0(Q[4]),\n .I1(Q[5]),\n .I2(Q[3]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[2]),\n .I5(prbs_rdlvl_start_i_2_n_0),\n .O(prbs_gen_oclk_clk_en_i_3_n_0));\n LUT6 #(\n .INIT(64'h0000000000000008)) \n prbs_gen_oclk_clk_en_i_4\n (.I0(prbs_gen_oclk_clk_en_i_8_n_0),\n .I1(\\complex_num_writes_reg_n_0_[0] ),\n .I2(\\complex_num_writes_reg_n_0_[1] ),\n .I3(\\complex_num_writes_reg_n_0_[2] ),\n .I4(\\complex_num_writes_reg_n_0_[4] ),\n .I5(\\complex_num_writes_reg_n_0_[3] ),\n .O(prbs_gen_oclk_clk_en_i_4_n_0));\n LUT6 #(\n .INIT(64'hAABAAAAAFFFFFFFF)) \n prbs_gen_oclk_clk_en_i_5\n (.I0(prbs_gen_oclk_clk_en_i_9_n_0),\n .I1(complex_num_writes_dec_reg__0[0]),\n .I2(complex_num_writes_dec_reg__0[1]),\n .I3(\\complex_num_writes_dec[4]_i_5_n_0 ),\n .I4(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .I5(complex_ocal_wr_start),\n .O(prbs_gen_oclk_clk_en_i_5_n_0));\n LUT6 #(\n .INIT(64'h0001101100010001)) \n prbs_gen_oclk_clk_en_i_6\n (.I0(complex_oclkdelay_calib_start_int_i_2_n_0),\n .I1(\\init_state_r[4]_i_5_n_0 ),\n .I2(Q[1]),\n .I3(prbs_gen_clk_en_i_5_n_0),\n .I4(Q[0]),\n .I5(complex_oclk_calib_resume),\n .O(prbs_gen_oclk_clk_en_i_6_n_0));\n LUT5 #(\n .INIT(32'h00000004)) \n prbs_gen_oclk_clk_en_i_7\n (.I0(prbs_gen_clk_en_i_5_n_0),\n .I1(\\complex_num_writes[3]_i_4_n_0 ),\n .I2(\\one_rank.stg1_wr_done_reg_0 ),\n .I3(complex_row1_wr_done),\n .I4(complex_ocal_num_samples_done_r),\n .O(prbs_gen_oclk_clk_en_i_7_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair502\" *) \n LUT4 #(\n .INIT(16'h8000)) \n prbs_gen_oclk_clk_en_i_8\n (.I0(complex_wait_cnt_reg__0[0]),\n .I1(complex_wait_cnt_reg__0[1]),\n .I2(complex_wait_cnt_reg__0[2]),\n .I3(complex_wait_cnt_reg__0[3]),\n .O(prbs_gen_oclk_clk_en_i_8_n_0));\n LUT6 #(\n .INIT(64'h0000D00000000000)) \n prbs_gen_oclk_clk_en_i_9\n (.I0(\\stg1_wr_rd_cnt[4]_i_5_n_0 ),\n .I1(complex_oclkdelay_calib_start_int_reg_0),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_17_n_0 ),\n .I3(init_state_r1[2]),\n .I4(init_state_r1[6]),\n .I5(init_state_r1[1]),\n .O(prbs_gen_oclk_clk_en_i_9_n_0));\n FDRE #(\n .INIT(1'b0)) \n prbs_gen_oclk_clk_en_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prbs_gen_oclk_clk_en_i_1_n_0),\n .Q(prbs_gen_oclk_clk_en),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n prbs_last_byte_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prbs_last_byte_done),\n .Q(prbs_last_byte_done_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n prbs_rdlvl_done_pulse_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prbs_rdlvl_done_pulse0),\n .Q(prbs_rdlvl_done_pulse),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n prbs_rdlvl_done_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prbs_rdlvl_done_reg_rep),\n .Q(prbs_rdlvl_done_r1),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n prbs_rdlvl_done_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prbs_rdlvl_done_r1),\n .Q(prbs_rdlvl_done_r2),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n prbs_rdlvl_done_r3_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prbs_rdlvl_done_r2),\n .Q(prbs_rdlvl_done_r3),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFFFFFFF00000020)) \n prbs_rdlvl_start_i_1\n (.I0(rdlvl_stg1_done_int_reg),\n .I1(prbs_rdlvl_done_reg),\n .I2(dqs_found_done_r_reg),\n .I3(prbs_rdlvl_start_i_2_n_0),\n .I4(prbs_rdlvl_start_i_3_n_0),\n .I5(prbs_rdlvl_start_r_reg),\n .O(prbs_rdlvl_start_i_1_n_0));\n LUT2 #(\n .INIT(4'h7)) \n prbs_rdlvl_start_i_2\n (.I0(Q[0]),\n .I1(Q[1]),\n .O(prbs_rdlvl_start_i_2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair479\" *) \n LUT5 #(\n .INIT(32'hFFFEFFFF)) \n prbs_rdlvl_start_i_3\n (.I0(Q[4]),\n .I1(Q[3]),\n .I2(Q[2]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[5]),\n .O(prbs_rdlvl_start_i_3_n_0));\n FDRE #(\n .INIT(1'b0)) \n prbs_rdlvl_start_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prbs_rdlvl_start_i_1_n_0),\n .Q(prbs_rdlvl_start_r_reg),\n .R(rstdiv0_sync_r1_reg_rep__11));\n LUT2 #(\n .INIT(4'h2)) \n \\prbs_state_r[4]_i_10 \n (.I0(prbs_rdlvl_start_r_reg),\n .I1(prbs_rdlvl_start_r),\n .O(new_cnt_dqs_r_reg));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done_dly_r_reg \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done_dly_r_reg[15]_srl16 \" *) \n SRL16E #(\n .INIT(16'h0000)) \n \\prech_done_dly_r_reg[15]_srl16 \n (.A0(1'b1),\n .A1(1'b1),\n .A2(1'b1),\n .A3(1'b1),\n .CE(1'b1),\n .CLK(CLK),\n .D(prech_done_pre),\n .Q(\\prech_done_dly_r_reg[15]_srl16_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\prech_done_dly_r_reg[15]_srl16_i_1 \n (.I0(prech_pending_r_reg_1),\n .I1(prech_pending_r_reg_0),\n .O(prech_done_pre));\n FDRE #(\n .INIT(1'b0)) \n prech_done_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prech_done),\n .Q(prech_done_r2),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n prech_done_r3_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prech_done_r2),\n .Q(prech_done_r3),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n prech_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\prech_done_dly_r_reg[15]_srl16_n_0 ),\n .Q(prech_done),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hAAAAAA8A8A8A8A8A)) \n prech_pending_r_i_2\n (.I0(prech_pending_r),\n .I1(prech_pending_r_i_3_n_0),\n .I2(prech_pending_r_i_4_n_0),\n .I3(\\complex_row_cnt_ocal[7]_i_6_n_0 ),\n .I4(prech_pending_r_i_5_n_0),\n .I5(prbs_last_byte_done_r),\n .O(prech_pending_r_reg_1));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF5D0000)) \n prech_pending_r_i_3\n (.I0(prech_pending_r_i_6_n_0),\n .I1(\\wrcal_reads[7]_i_6_n_0 ),\n .I2(first_wrcal_pat_r_i_2_n_0),\n .I3(prech_pending_r_i_7_n_0),\n .I4(cnt_cmd_done_r),\n .I5(prech_pending_r_i_8_n_0),\n .O(prech_pending_r_i_3_n_0));\n LUT6 #(\n .INIT(64'h0000FDFFFDFFFDFF)) \n prech_pending_r_i_4\n (.I0(dqs_found_prech_req),\n .I1(\\init_state_r[4]_i_5_n_0 ),\n .I2(rdlvl_stg1_start_int_i_2_n_0),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .I4(\\num_refresh[3]_i_5_n_0 ),\n .I5(complex_oclkdelay_calib_start_r1),\n .O(prech_pending_r_i_4_n_0));\n LUT6 #(\n .INIT(64'h0000000000000008)) \n prech_pending_r_i_5\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .I1(cnt_cmd_done_r),\n .I2(\\init_state_r[4]_i_5_n_0 ),\n .I3(Q[3]),\n .I4(Q[4]),\n .I5(Q[5]),\n .O(prech_pending_r_i_5_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFDFFFF)) \n prech_pending_r_i_6\n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(Q[2]),\n .I2(rdlvl_start_pre_reg_0),\n .I3(oclkdelay_calib_done_r_reg_2),\n .I4(wrlvl_final_mux),\n .I5(complex_oclkdelay_calib_start_int_reg_0),\n .O(prech_pending_r_i_6_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair489\" *) \n LUT5 #(\n .INIT(32'h00000080)) \n prech_pending_r_i_7\n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(Q[1]),\n .I2(Q[2]),\n .I3(Q[0]),\n .I4(read_calib_i_2_n_0),\n .O(prech_pending_r_i_7_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFEFFFEFFFE)) \n prech_pending_r_i_8\n (.I0(oclkdelay_calib_start_pre),\n .I1(prech_pending_r_i_9_n_0),\n .I2(stg1_wr_done),\n .I3(\\calib_cmd[2]_i_8_n_0 ),\n .I4(prech_pending_r_i_5_n_0),\n .I5(rdlvl_last_byte_done_r),\n .O(prech_pending_r_i_8_n_0));\n LUT6 #(\n .INIT(64'h0000000000040000)) \n prech_pending_r_i_9\n (.I0(prbs_rdlvl_start_i_2_n_0),\n .I1(Q[2]),\n .I2(\\init_state_r_reg_n_0_[3] ),\n .I3(Q[3]),\n .I4(Q[4]),\n .I5(Q[5]),\n .O(prech_pending_r_i_9_n_0));\n FDRE #(\n .INIT(1'b0)) \n prech_pending_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prech_req_posedge_r_reg_0),\n .Q(prech_pending_r),\n .R(rstdiv0_sync_r1_reg_rep__12));\n LUT2 #(\n .INIT(4'h1)) \n prech_req_posedge_r_i_1\n (.I0(prech_req_r),\n .I1(prech_req_posedge_r_i_2_n_0),\n .O(prech_req_posedge_r0));\n LUT6 #(\n .INIT(64'h000000000000000B)) \n prech_req_posedge_r_i_2\n (.I0(\\back_to_back_reads_4_1.num_reads_reg[1]_0 ),\n .I1(dqs_found_prech_req),\n .I2(prbs_rdlvl_prech_req_reg),\n .I3(complex_ocal_ref_req),\n .I4(wrcal_prech_req),\n .I5(rdlvl_prech_req),\n .O(prech_req_posedge_r_i_2_n_0));\n FDRE #(\n .INIT(1'b0)) \n prech_req_posedge_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prech_req_posedge_r0),\n .Q(prech_pending_r_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__12));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFEF)) \n prech_req_r_i_3\n (.I0(complex_oclkdelay_calib_start_int_reg_0),\n .I1(Q[4]),\n .I2(Q[3]),\n .I3(Q[5]),\n .I4(Q[2]),\n .I5(\\init_state_r_reg_n_0_[3] ),\n .O(\\back_to_back_reads_4_1.num_reads_reg[1]_0 ));\n FDRE #(\n .INIT(1'b0)) \n prech_req_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prech_req),\n .Q(prech_req_r),\n .R(rstdiv0_sync_r1_reg_rep__12));\n LUT5 #(\n .INIT(32'h80000000)) \n pwron_ce_r_i_2\n (.I0(cnt_pwron_ce_r_reg__0[9]),\n .I1(cnt_pwron_ce_r_reg__0[7]),\n .I2(pwron_ce_r_i_3_n_0),\n .I3(cnt_pwron_ce_r_reg__0[6]),\n .I4(cnt_pwron_ce_r_reg__0[8]),\n .O(pwron_ce_r_i_2_n_0));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n pwron_ce_r_i_3\n (.I0(cnt_pwron_ce_r_reg__0[5]),\n .I1(cnt_pwron_ce_r_reg__0[3]),\n .I2(cnt_pwron_ce_r_reg__0[1]),\n .I3(cnt_pwron_ce_r_reg__0[0]),\n .I4(cnt_pwron_ce_r_reg__0[2]),\n .I5(cnt_pwron_ce_r_reg__0[4]),\n .O(pwron_ce_r_i_3_n_0));\n FDRE #(\n .INIT(1'b0)) \n pwron_ce_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pwron_ce_r_i_2_n_0),\n .Q(pwron_ce_r),\n .R(rstdiv0_sync_r1_reg_rep__11));\n LUT6 #(\n .INIT(64'h0000BBB0FFF0FFF0)) \n \\rd_addr[7]_i_2 \n (.I0(prbs_rdlvl_done_reg_rep),\n .I1(prbs_rdlvl_start_r_reg),\n .I2(prbs_gen_clk_en),\n .I3(prbs_gen_oclk_clk_en),\n .I4(complex_wr_done),\n .I5(phy_if_empty_r_reg),\n .O(\\rd_addr_reg[0] ));\n LUT6 #(\n .INIT(64'h959595AAAAAAAAAA)) \n \\rd_addr[7]_i_7 \n (.I0(\\rd_addr_reg[3] ),\n .I1(phy_if_empty_r_reg),\n .I2(complex_wr_done),\n .I3(prbs_gen_oclk_clk_en),\n .I4(prbs_gen_clk_en),\n .I5(prbs_rdlvl_done_reg_rep),\n .O(\\rd_addr_reg_rep[7] ));\n FDRE #(\n .INIT(1'b0)) \n rdlvl_last_byte_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rdlvl_last_byte_done),\n .Q(rdlvl_last_byte_done_r),\n .R(1'b0));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[13]_srl14 \" *) \n SRL16E #(\n .INIT(16'h0000)) \n \\rdlvl_start_dly0_r_reg[13]_srl14 \n (.A0(1'b1),\n .A1(1'b0),\n .A2(1'b1),\n .A3(1'b1),\n .CE(1'b1),\n .CLK(CLK),\n .D(rdlvl_start_pre),\n .Q(\\rdlvl_start_dly0_r_reg[13]_srl14_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rdlvl_start_dly0_r_reg[14] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rdlvl_start_dly0_r_reg[13]_srl14_n_0 ),\n .Q(rdlvl_start_dly0_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair582\" *) \n LUT3 #(\n .INIT(8'hFB)) \n rdlvl_start_pre_i_2\n (.I0(Q[4]),\n .I1(Q[3]),\n .I2(Q[5]),\n .O(rdlvl_start_pre_reg_0));\n FDRE #(\n .INIT(1'b0)) \n rdlvl_start_pre_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\init_state_r_reg[0]_1 ),\n .Q(rdlvl_start_pre),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE #(\n .INIT(1'b0)) \n rdlvl_stg1_done_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rdlvl_stg1_done_int_reg),\n .Q(rdlvl_stg1_done_r1),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFFFFFFF00000080)) \n rdlvl_stg1_start_int_i_1\n (.I0(dqs_found_done_r_reg),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .I2(cnt_cmd_done_r),\n .I3(\\init_state_r[4]_i_5_n_0 ),\n .I4(rdlvl_stg1_start_int_i_2_n_0),\n .I5(rdlvl_stg1_start_int),\n .O(rdlvl_stg1_start_int_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair569\" *) \n LUT3 #(\n .INIT(8'hFE)) \n rdlvl_stg1_start_int_i_2\n (.I0(Q[3]),\n .I1(Q[4]),\n .I2(Q[5]),\n .O(rdlvl_stg1_start_int_i_2_n_0));\n FDRE #(\n .INIT(1'b0)) \n rdlvl_stg1_start_int_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rdlvl_stg1_start_int_i_1_n_0),\n .Q(rdlvl_stg1_start_int),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE #(\n .INIT(1'b0)) \n rdlvl_stg1_start_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\rdlvl_start_dly0_r_reg[14]_0 ),\n .Q(rdlvl_stg1_start_r_reg),\n .R(rstdiv0_sync_r1_reg_rep__12));\n LUT5 #(\n .INIT(32'h000000AB)) \n read_calib_i_1\n (.I0(phy_read_calib),\n .I1(read_calib_i_2_n_0),\n .I2(read_calib_reg_0),\n .I3(pi_calib_done),\n .I4(rstdiv0_sync_r1_reg_rep__23),\n .O(read_calib_i_1_n_0));\n LUT3 #(\n .INIT(8'hFB)) \n read_calib_i_2\n (.I0(Q[3]),\n .I1(Q[4]),\n .I2(Q[5]),\n .O(read_calib_i_2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair504\" *) \n LUT4 #(\n .INIT(16'hFDFF)) \n read_calib_i_3\n (.I0(Q[1]),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .I2(Q[0]),\n .I3(Q[2]),\n .O(read_calib_reg_0));\n FDRE #(\n .INIT(1'b0)) \n read_calib_reg\n (.C(CLK),\n .CE(1'b1),\n .D(read_calib_i_1_n_0),\n .Q(phy_read_calib),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair607\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\reg_ctrl_cnt_r[0]_i_1 \n (.I0(reg_ctrl_cnt_r_reg__0[0]),\n .O(\\reg_ctrl_cnt_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair607\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\reg_ctrl_cnt_r[1]_i_1 \n (.I0(reg_ctrl_cnt_r_reg__0[0]),\n .I1(reg_ctrl_cnt_r_reg__0[1]),\n .O(p_0_in__2[1]));\n (* SOFT_HLUTNM = \"soft_lutpair583\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\reg_ctrl_cnt_r[2]_i_1 \n (.I0(reg_ctrl_cnt_r_reg__0[2]),\n .I1(reg_ctrl_cnt_r_reg__0[1]),\n .I2(reg_ctrl_cnt_r_reg__0[0]),\n .O(p_0_in__2[2]));\n LUT6 #(\n .INIT(64'h0000000000000001)) \n \\reg_ctrl_cnt_r[3]_i_1 \n (.I0(Q[1]),\n .I1(Q[4]),\n .I2(Q[5]),\n .I3(oclk_calib_resume_level_reg_0),\n .I4(Q[3]),\n .I5(Q[0]),\n .O(\\reg_ctrl_cnt_r_reg[3]_0 ));\n LUT6 #(\n .INIT(64'h0000000001000000)) \n \\reg_ctrl_cnt_r[3]_i_2 \n (.I0(prbs_rdlvl_start_i_2_n_0),\n .I1(Q[2]),\n .I2(Q[4]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[3]),\n .I5(Q[5]),\n .O(reg_ctrl_cnt_r));\n (* SOFT_HLUTNM = \"soft_lutpair559\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\reg_ctrl_cnt_r[3]_i_3 \n (.I0(reg_ctrl_cnt_r_reg__0[3]),\n .I1(reg_ctrl_cnt_r_reg__0[2]),\n .I2(reg_ctrl_cnt_r_reg__0[0]),\n .I3(reg_ctrl_cnt_r_reg__0[1]),\n .O(p_0_in__2[3]));\n FDRE #(\n .INIT(1'b0)) \n \\reg_ctrl_cnt_r_reg[0] \n (.C(CLK),\n .CE(reg_ctrl_cnt_r),\n .D(\\reg_ctrl_cnt_r[0]_i_1_n_0 ),\n .Q(reg_ctrl_cnt_r_reg__0[0]),\n .R(\\reg_ctrl_cnt_r_reg[3]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\reg_ctrl_cnt_r_reg[1] \n (.C(CLK),\n .CE(reg_ctrl_cnt_r),\n .D(p_0_in__2[1]),\n .Q(reg_ctrl_cnt_r_reg__0[1]),\n .R(\\reg_ctrl_cnt_r_reg[3]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\reg_ctrl_cnt_r_reg[2] \n (.C(CLK),\n .CE(reg_ctrl_cnt_r),\n .D(p_0_in__2[2]),\n .Q(reg_ctrl_cnt_r_reg__0[2]),\n .R(\\reg_ctrl_cnt_r_reg[3]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\reg_ctrl_cnt_r_reg[3] \n (.C(CLK),\n .CE(reg_ctrl_cnt_r),\n .D(p_0_in__2[3]),\n .Q(reg_ctrl_cnt_r_reg__0[3]),\n .R(\\reg_ctrl_cnt_r_reg[3]_0 ));\n LUT3 #(\n .INIT(8'h02)) \n reset_if_i_1\n (.I0(reset_if_i_2_n_0),\n .I1(rstdiv0_sync_r1_reg_rep__24),\n .I2(reset_if_r9),\n .O(reset_if_reg));\n LUT5 #(\n .INIT(32'hFFFF22F2)) \n reset_if_i_2\n (.I0(rdlvl_stg1_done_int_reg),\n .I1(rdlvl_stg1_done_r1),\n .I2(prbs_rdlvl_done_reg),\n .I3(prbs_rdlvl_done_r1),\n .I4(reset_if),\n .O(reset_if_i_2_n_0));\n FDRE #(\n .INIT(1'b0)) \n reset_rd_addr_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(reset_rd_addr0),\n .Q(reset_rd_addr_r1),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair515\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\row_cnt_victim_rotate.complex_row_cnt[0]_i_1 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),\n .I1(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[0]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8BB8)) \n \\row_cnt_victim_rotate.complex_row_cnt[1]_i_1 \n (.I0(\\rd_victim_sel_reg[0] ),\n .I1(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ),\n .I2(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),\n .I3(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair515\" *) \n LUT5 #(\n .INIT(32'h8BB8B8B8)) \n \\row_cnt_victim_rotate.complex_row_cnt[2]_i_1 \n (.I0(\\rd_victim_sel_reg[1] ),\n .I1(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ),\n .I2(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),\n .I3(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),\n .I4(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8BB8B8B8B8B8B8B8)) \n \\row_cnt_victim_rotate.complex_row_cnt[3]_i_1 \n (.I0(\\rd_victim_sel_reg[2] ),\n .I1(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ),\n .I2(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ),\n .I3(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),\n .I4(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),\n .I5(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hEEEEFFEFAAAAAAAA)) \n \\row_cnt_victim_rotate.complex_row_cnt[4]_i_1 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0 ),\n .I1(reset_rd_addr_r1),\n .I2(complex_sample_cnt_inc_r2),\n .I3(complex_victim_inc_reg),\n .I4(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ),\n .I5(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0 ),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\row_cnt_victim_rotate.complex_row_cnt[4]_i_10 \n (.I0(\\stg1_wr_rd_cnt_reg_n_0_[3] ),\n .I1(\\complex_row_cnt_ocal[7]_i_7_n_0 ),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_10_n_0 ));\n LUT3 #(\n .INIT(8'h0E)) \n \\row_cnt_victim_rotate.complex_row_cnt[4]_i_2 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ),\n .I1(\\one_rank.stg1_wr_done_reg_0 ),\n .I2(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_7_n_0 ),\n .O(complex_row_cnt));\n LUT6 #(\n .INIT(64'h000000007FFF8000)) \n \\row_cnt_victim_rotate.complex_row_cnt[4]_i_3 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),\n .I1(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),\n .I2(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),\n .I3(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ),\n .I4(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),\n .I5(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'hFFFB)) \n \\row_cnt_victim_rotate.complex_row_cnt[4]_i_4 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt_reg[4]_0 ),\n .I1(rdlvl_stg1_done_r1),\n .I2(rstdiv0_sync_r1_reg_rep__23),\n .I3(prbs_rdlvl_done_reg),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h00000001)) \n \\row_cnt_victim_rotate.complex_row_cnt[4]_i_5 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),\n .I1(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ),\n .I2(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ),\n .I3(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ),\n .I4(\\row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 ),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair546\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\row_cnt_victim_rotate.complex_row_cnt[4]_i_6 \n (.I0(\\one_rank.stg1_wr_done_reg_0 ),\n .I1(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_7_n_0 ),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h000000000000000B)) \n \\row_cnt_victim_rotate.complex_row_cnt[4]_i_7 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_10_n_0 ),\n .I1(\\complex_row_cnt_ocal[7]_i_6_n_0 ),\n .I2(reset_rd_addr_r1),\n .I3(complex_victim_inc_reg),\n .I4(wr_victim_inc),\n .I5(complex_sample_cnt_inc_r2),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair546\" *) \n LUT4 #(\n .INIT(16'h4044)) \n \\row_cnt_victim_rotate.complex_row_cnt[4]_i_8 \n (.I0(complex_victim_inc_reg),\n .I1(complex_sample_cnt_inc_r2),\n .I2(\\one_rank.stg1_wr_done_reg_0 ),\n .I3(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'h0000000200000000)) \n \\row_cnt_victim_rotate.complex_row_cnt[4]_i_9 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 ),\n .I1(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ),\n .I2(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ),\n .I3(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ),\n .I4(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),\n .I5(wr_victim_inc),\n .O(\\row_cnt_victim_rotate.complex_row_cnt_reg[4]_0 ));\n LUT6 #(\n .INIT(64'h00000000262A2A2A)) \n \\row_cnt_victim_rotate.complex_row_cnt[5]_i_1 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ),\n .I1(complex_row_cnt),\n .I2(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ),\n .I3(\\row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 ),\n .I4(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),\n .I5(\\row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0 ),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[5]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8000)) \n \\row_cnt_victim_rotate.complex_row_cnt[5]_i_2 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),\n .I1(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),\n .I2(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),\n .I3(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h0000262A)) \n \\row_cnt_victim_rotate.complex_row_cnt[6]_i_1 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ),\n .I1(complex_row_cnt),\n .I2(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ),\n .I3(\\row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0 ),\n .I4(\\row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0 ),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[6]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00000000262A2A2A)) \n \\row_cnt_victim_rotate.complex_row_cnt[7]_i_1 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ),\n .I1(complex_row_cnt),\n .I2(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ),\n .I3(\\row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0 ),\n .I4(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ),\n .I5(\\row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0 ),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\row_cnt_victim_rotate.complex_row_cnt[7]_i_2 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ),\n .I1(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),\n .I2(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),\n .I3(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),\n .I4(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ),\n .I5(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFBBFBAAAAAAAA)) \n \\row_cnt_victim_rotate.complex_row_cnt[7]_i_3 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0 ),\n .I1(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ),\n .I2(complex_sample_cnt_inc_r2),\n .I3(complex_victim_inc_reg),\n .I4(reset_rd_addr_r1),\n .I5(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0 ),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\row_cnt_victim_rotate.complex_row_cnt_reg[0] \n (.C(CLK),\n .CE(complex_row_cnt),\n .D(\\row_cnt_victim_rotate.complex_row_cnt[0]_i_1_n_0 ),\n .Q(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),\n .R(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\row_cnt_victim_rotate.complex_row_cnt_reg[1] \n (.C(CLK),\n .CE(complex_row_cnt),\n .D(\\row_cnt_victim_rotate.complex_row_cnt[1]_i_1_n_0 ),\n .Q(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),\n .R(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\row_cnt_victim_rotate.complex_row_cnt_reg[2] \n (.C(CLK),\n .CE(complex_row_cnt),\n .D(\\row_cnt_victim_rotate.complex_row_cnt[2]_i_1_n_0 ),\n .Q(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),\n .R(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\row_cnt_victim_rotate.complex_row_cnt_reg[3] \n (.C(CLK),\n .CE(complex_row_cnt),\n .D(\\row_cnt_victim_rotate.complex_row_cnt[3]_i_1_n_0 ),\n .Q(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ),\n .R(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\row_cnt_victim_rotate.complex_row_cnt_reg[4] \n (.C(CLK),\n .CE(complex_row_cnt),\n .D(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_3_n_0 ),\n .Q(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),\n .R(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\row_cnt_victim_rotate.complex_row_cnt_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\row_cnt_victim_rotate.complex_row_cnt[5]_i_1_n_0 ),\n .Q(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\row_cnt_victim_rotate.complex_row_cnt_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\row_cnt_victim_rotate.complex_row_cnt[6]_i_1_n_0 ),\n .Q(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\row_cnt_victim_rotate.complex_row_cnt_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0 ),\n .Q(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair557\" *) \n LUT2 #(\n .INIT(4'hB)) \n \\samples_cnt_r[11]_i_1 \n (.I0(complex_sample_cnt_inc),\n .I1(\\samples_cnt_r_reg[11]_0 ),\n .O(\\samples_cnt_r_reg[11] ));\n LUT3 #(\n .INIT(8'hBA)) \n \\stg1_wr_rd_cnt[0]_i_1 \n (.I0(\\stg1_wr_rd_cnt[6]_i_2_n_0 ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[0] ),\n .I2(\\stg1_wr_rd_cnt[8]_i_3_n_0 ),\n .O(\\stg1_wr_rd_cnt[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0D00000D0D0D0D0D)) \n \\stg1_wr_rd_cnt[1]_i_1 \n (.I0(stg1_wr_done),\n .I1(rdlvl_stg1_done_int_reg),\n .I2(rstdiv0_sync_r1_reg_rep__23),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[1] ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[0] ),\n .I5(\\stg1_wr_rd_cnt[4]_i_4_n_0 ),\n .O(\\stg1_wr_rd_cnt[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair564\" *) \n LUT4 #(\n .INIT(16'hFD57)) \n \\stg1_wr_rd_cnt[2]_i_1 \n (.I0(\\stg1_wr_rd_cnt[8]_i_3_n_0 ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[1] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[0] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[2] ),\n .O(\\stg1_wr_rd_cnt[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00A8AAA8AAA800A8)) \n \\stg1_wr_rd_cnt[3]_i_1 \n (.I0(rdlvl_stg1_done_int_reg_1),\n .I1(\\stg1_wr_rd_cnt[3]_i_2_n_0 ),\n .I2(prbs_rdlvl_done_reg),\n .I3(\\stg1_wr_rd_cnt[4]_i_4_n_0 ),\n .I4(\\stg1_wr_rd_cnt[5]_i_2_n_0 ),\n .I5(\\stg1_wr_rd_cnt_reg_n_0_[3] ),\n .O(\\stg1_wr_rd_cnt[3]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFD0FF)) \n \\stg1_wr_rd_cnt[3]_i_2 \n (.I0(complex_row0_rd_done),\n .I1(complex_row1_rd_done),\n .I2(complex_row1_wr_done),\n .I3(complex_row0_wr_done),\n .I4(wr_victim_inc),\n .O(\\stg1_wr_rd_cnt[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h88888882AAAAAAAA)) \n \\stg1_wr_rd_cnt[4]_i_1 \n (.I0(rdlvl_stg1_done_int_reg_1),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[4] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[3] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[0] ),\n .I4(\\stg1_wr_rd_cnt[4]_i_3_n_0 ),\n .I5(\\stg1_wr_rd_cnt[4]_i_4_n_0 ),\n .O(\\stg1_wr_rd_cnt[4]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair603\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\stg1_wr_rd_cnt[4]_i_3 \n (.I0(\\stg1_wr_rd_cnt_reg_n_0_[1] ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[2] ),\n .O(\\stg1_wr_rd_cnt[4]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0222022200000222)) \n \\stg1_wr_rd_cnt[4]_i_4 \n (.I0(complex_sample_cnt_inc_i_2_n_0),\n .I1(rdlvl_last_byte_done),\n .I2(\\wrcal_reads[7]_i_6_n_0 ),\n .I3(\\stg1_wr_rd_cnt[4]_i_5_n_0 ),\n .I4(prbs_rdlvl_prech_req_reg),\n .I5(\\stg1_wr_rd_cnt[4]_i_6_n_0 ),\n .O(\\stg1_wr_rd_cnt[4]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair479\" *) \n LUT5 #(\n .INIT(32'h00800000)) \n \\stg1_wr_rd_cnt[4]_i_5 \n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(Q[2]),\n .I2(Q[3]),\n .I3(Q[5]),\n .I4(Q[4]),\n .O(\\stg1_wr_rd_cnt[4]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFF7FFFFFFFF)) \n \\stg1_wr_rd_cnt[4]_i_6 \n (.I0(Q[2]),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .I2(Q[3]),\n .I3(Q[4]),\n .I4(Q[5]),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .O(\\stg1_wr_rd_cnt[4]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hEEEBEEEEAAAAAAAA)) \n \\stg1_wr_rd_cnt[5]_i_1 \n (.I0(\\stg1_wr_rd_cnt[6]_i_2_n_0 ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[5] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[4] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[3] ),\n .I4(\\stg1_wr_rd_cnt[5]_i_2_n_0 ),\n .I5(\\stg1_wr_rd_cnt[8]_i_3_n_0 ),\n .O(\\stg1_wr_rd_cnt[5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair564\" *) \n LUT3 #(\n .INIT(8'h01)) \n \\stg1_wr_rd_cnt[5]_i_2 \n (.I0(\\stg1_wr_rd_cnt_reg_n_0_[0] ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[2] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[1] ),\n .O(\\stg1_wr_rd_cnt[5]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'hFF60)) \n \\stg1_wr_rd_cnt[6]_i_1 \n (.I0(\\stg1_wr_rd_cnt_reg_n_0_[6] ),\n .I1(\\stg1_wr_rd_cnt[8]_i_6_n_0 ),\n .I2(\\stg1_wr_rd_cnt[8]_i_3_n_0 ),\n .I3(\\stg1_wr_rd_cnt[6]_i_2_n_0 ),\n .O(\\stg1_wr_rd_cnt[6]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h00002022)) \n \\stg1_wr_rd_cnt[6]_i_2 \n (.I0(\\stg1_wr_rd_cnt[3]_i_2_n_0 ),\n .I1(rstdiv0_sync_r1_reg_rep__23),\n .I2(rdlvl_stg1_done_int_reg),\n .I3(stg1_wr_done),\n .I4(\\stg1_wr_rd_cnt[4]_i_4_n_0 ),\n .O(\\stg1_wr_rd_cnt[6]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair511\" *) \n LUT4 #(\n .INIT(16'hA208)) \n \\stg1_wr_rd_cnt[7]_i_1 \n (.I0(\\stg1_wr_rd_cnt[8]_i_3_n_0 ),\n .I1(\\stg1_wr_rd_cnt[8]_i_6_n_0 ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[6] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[7] ),\n .O(\\stg1_wr_rd_cnt[7]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hFFD5)) \n \\stg1_wr_rd_cnt[8]_i_1 \n (.I0(\\stg1_wr_rd_cnt[8]_i_3_n_0 ),\n .I1(\\stg1_wr_rd_cnt[8]_i_4_n_0 ),\n .I2(rdlvl_stg1_done_int_reg),\n .I3(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .O(\\stg1_wr_rd_cnt[8]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair511\" *) \n LUT5 #(\n .INIT(32'hA8AA0200)) \n \\stg1_wr_rd_cnt[8]_i_2 \n (.I0(\\stg1_wr_rd_cnt[8]_i_3_n_0 ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[7] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[6] ),\n .I3(\\stg1_wr_rd_cnt[8]_i_6_n_0 ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[8] ),\n .O(\\stg1_wr_rd_cnt[8]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'h00A2)) \n \\stg1_wr_rd_cnt[8]_i_3 \n (.I0(\\stg1_wr_rd_cnt[4]_i_4_n_0 ),\n .I1(stg1_wr_done),\n .I2(rdlvl_stg1_done_int_reg),\n .I3(rstdiv0_sync_r1_reg_rep__23),\n .O(\\stg1_wr_rd_cnt[8]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0000200000000000)) \n \\stg1_wr_rd_cnt[8]_i_4 \n (.I0(Q[4]),\n .I1(Q[5]),\n .I2(Q[3]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[2]),\n .I5(\\wrcal_reads[7]_i_6_n_0 ),\n .O(\\stg1_wr_rd_cnt[8]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000080)) \n \\stg1_wr_rd_cnt[8]_i_5 \n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(Q[1]),\n .I2(Q[2]),\n .I3(Q[0]),\n .I4(\\init_state_r[5]_i_2_n_0 ),\n .I5(Q[3]),\n .O(\\stg1_wr_rd_cnt[8]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000001)) \n \\stg1_wr_rd_cnt[8]_i_6 \n (.I0(\\stg1_wr_rd_cnt_reg_n_0_[3] ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[0] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[2] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[1] ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[4] ),\n .I5(\\stg1_wr_rd_cnt_reg_n_0_[5] ),\n .O(\\stg1_wr_rd_cnt[8]_i_6_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\stg1_wr_rd_cnt_reg[0] \n (.C(CLK),\n .CE(\\stg1_wr_rd_cnt[8]_i_1_n_0 ),\n .D(\\stg1_wr_rd_cnt[0]_i_1_n_0 ),\n .Q(\\stg1_wr_rd_cnt_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg1_wr_rd_cnt_reg[1] \n (.C(CLK),\n .CE(\\stg1_wr_rd_cnt[8]_i_1_n_0 ),\n .D(\\stg1_wr_rd_cnt[1]_i_1_n_0 ),\n .Q(\\stg1_wr_rd_cnt_reg_n_0_[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg1_wr_rd_cnt_reg[2] \n (.C(CLK),\n .CE(\\stg1_wr_rd_cnt[8]_i_1_n_0 ),\n .D(\\stg1_wr_rd_cnt[2]_i_1_n_0 ),\n .Q(\\stg1_wr_rd_cnt_reg_n_0_[2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg1_wr_rd_cnt_reg[3] \n (.C(CLK),\n .CE(\\stg1_wr_rd_cnt[8]_i_1_n_0 ),\n .D(\\stg1_wr_rd_cnt[3]_i_1_n_0 ),\n .Q(\\stg1_wr_rd_cnt_reg_n_0_[3] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg1_wr_rd_cnt_reg[4] \n (.C(CLK),\n .CE(\\stg1_wr_rd_cnt[8]_i_1_n_0 ),\n .D(\\stg1_wr_rd_cnt[4]_i_1_n_0 ),\n .Q(\\stg1_wr_rd_cnt_reg_n_0_[4] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg1_wr_rd_cnt_reg[5] \n (.C(CLK),\n .CE(\\stg1_wr_rd_cnt[8]_i_1_n_0 ),\n .D(\\stg1_wr_rd_cnt[5]_i_1_n_0 ),\n .Q(\\stg1_wr_rd_cnt_reg_n_0_[5] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg1_wr_rd_cnt_reg[6] \n (.C(CLK),\n .CE(\\stg1_wr_rd_cnt[8]_i_1_n_0 ),\n .D(\\stg1_wr_rd_cnt[6]_i_1_n_0 ),\n .Q(\\stg1_wr_rd_cnt_reg_n_0_[6] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg1_wr_rd_cnt_reg[7] \n (.C(CLK),\n .CE(\\stg1_wr_rd_cnt[8]_i_1_n_0 ),\n .D(\\stg1_wr_rd_cnt[7]_i_1_n_0 ),\n .Q(\\stg1_wr_rd_cnt_reg_n_0_[7] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg1_wr_rd_cnt_reg[8] \n (.C(CLK),\n .CE(\\stg1_wr_rd_cnt[8]_i_1_n_0 ),\n .D(\\stg1_wr_rd_cnt[8]_i_2_n_0 ),\n .Q(\\stg1_wr_rd_cnt_reg_n_0_[8] ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair579\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\victim_sel[0]_i_1 \n (.I0(\\victim_sel[0]_i_2_n_0 ),\n .I1(\\victim_sel[2]_i_3_n_0 ),\n .I2(\\victim_sel_reg_n_0_[0] ),\n .O(\\victim_sel[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\victim_sel[0]_i_2 \n (.I0(complex_ocal_rd_victim_sel[0]),\n .I1(\\rd_victim_sel_reg[0] ),\n .I2(\\victim_sel[2]_i_4_n_0 ),\n .I3(wr_victim_sel_ocal[0]),\n .I4(prbs_rdlvl_done_reg_rep),\n .I5(wr_victim_sel[0]),\n .O(\\victim_sel[0]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair581\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\victim_sel[1]_i_1 \n (.I0(\\victim_sel[1]_i_2_n_0 ),\n .I1(\\victim_sel[2]_i_3_n_0 ),\n .I2(\\victim_sel_reg_n_0_[1] ),\n .O(\\victim_sel[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\victim_sel[1]_i_2 \n (.I0(complex_ocal_rd_victim_sel[1]),\n .I1(\\rd_victim_sel_reg[1] ),\n .I2(\\victim_sel[2]_i_4_n_0 ),\n .I3(wr_victim_sel_ocal[1]),\n .I4(prbs_rdlvl_done_reg_rep),\n .I5(wr_victim_sel[1]),\n .O(\\victim_sel[1]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair579\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\victim_sel[2]_i_1 \n (.I0(\\victim_sel[2]_i_2_n_0 ),\n .I1(\\victim_sel[2]_i_3_n_0 ),\n .I2(\\victim_sel_reg_n_0_[2] ),\n .O(\\victim_sel[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\victim_sel[2]_i_2 \n (.I0(complex_ocal_rd_victim_sel[2]),\n .I1(\\rd_victim_sel_reg[2] ),\n .I2(\\victim_sel[2]_i_4_n_0 ),\n .I3(wr_victim_sel_ocal[2]),\n .I4(prbs_rdlvl_done_reg_rep),\n .I5(wr_victim_sel[2]),\n .O(\\victim_sel[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFBABF)) \n \\victim_sel[2]_i_3 \n (.I0(\\victim_sel[2]_i_5_n_0 ),\n .I1(complex_wr_done),\n .I2(prbs_rdlvl_done_reg),\n .I3(\\one_rank.stg1_wr_done_reg_0 ),\n .I4(reset_rd_addr),\n .I5(complex_ocal_reset_rd_addr),\n .O(\\victim_sel[2]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair571\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\victim_sel[2]_i_4 \n (.I0(complex_wr_done),\n .I1(prbs_rdlvl_done_reg_rep),\n .I2(\\one_rank.stg1_wr_done_reg_0 ),\n .O(\\victim_sel[2]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair513\" *) \n LUT5 #(\n .INIT(32'h00040000)) \n \\victim_sel[2]_i_5 \n (.I0(complex_oclkdelay_calib_start_int_i_2_n_0),\n .I1(Q[2]),\n .I2(Q[0]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[1]),\n .O(\\victim_sel[2]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\victim_sel_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\victim_sel[0]_i_1_n_0 ),\n .Q(\\victim_sel_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE #(\n .INIT(1'b0)) \n \\victim_sel_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\victim_sel[1]_i_1_n_0 ),\n .Q(\\victim_sel_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE #(\n .INIT(1'b0)) \n \\victim_sel_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\victim_sel[2]_i_1_n_0 ),\n .Q(\\victim_sel_reg_n_0_[2] ),\n .R(rstdiv0_sync_r1_reg_rep__12));\n (* SOFT_HLUTNM = \"soft_lutpair565\" *) \n LUT3 #(\n .INIT(8'h01)) \n \\victim_sel_rotate.sel[24]_i_1 \n (.I0(\\victim_sel_reg_n_0_[2] ),\n .I1(\\victim_sel_reg_n_0_[0] ),\n .I2(\\victim_sel_reg_n_0_[1] ),\n .O(\\victim_sel_rotate.sel_reg[31] [0]));\n (* SOFT_HLUTNM = \"soft_lutpair581\" *) \n LUT3 #(\n .INIT(8'h02)) \n \\victim_sel_rotate.sel[25]_i_1 \n (.I0(\\victim_sel_reg_n_0_[0] ),\n .I1(\\victim_sel_reg_n_0_[2] ),\n .I2(\\victim_sel_reg_n_0_[1] ),\n .O(\\victim_sel_rotate.sel_reg[31] [1]));\n (* SOFT_HLUTNM = \"soft_lutpair584\" *) \n LUT3 #(\n .INIT(8'h02)) \n \\victim_sel_rotate.sel[26]_i_1 \n (.I0(\\victim_sel_reg_n_0_[1] ),\n .I1(\\victim_sel_reg_n_0_[2] ),\n .I2(\\victim_sel_reg_n_0_[0] ),\n .O(\\victim_sel_rotate.sel_reg[31] [2]));\n LUT3 #(\n .INIT(8'h40)) \n \\victim_sel_rotate.sel[27]_i_1 \n (.I0(\\victim_sel_reg_n_0_[2] ),\n .I1(\\victim_sel_reg_n_0_[0] ),\n .I2(\\victim_sel_reg_n_0_[1] ),\n .O(\\victim_sel_rotate.sel_reg[31] [3]));\n (* SOFT_HLUTNM = \"soft_lutpair565\" *) \n LUT3 #(\n .INIT(8'h02)) \n \\victim_sel_rotate.sel[28]_i_1 \n (.I0(\\victim_sel_reg_n_0_[2] ),\n .I1(\\victim_sel_reg_n_0_[0] ),\n .I2(\\victim_sel_reg_n_0_[1] ),\n .O(\\victim_sel_rotate.sel_reg[31] [4]));\n (* SOFT_HLUTNM = \"soft_lutpair568\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\victim_sel_rotate.sel[29]_i_1 \n (.I0(\\victim_sel_reg_n_0_[0] ),\n .I1(\\victim_sel_reg_n_0_[2] ),\n .I2(\\victim_sel_reg_n_0_[1] ),\n .O(\\victim_sel_rotate.sel_reg[31] [5]));\n (* SOFT_HLUTNM = \"soft_lutpair584\" *) \n LUT3 #(\n .INIT(8'h40)) \n \\victim_sel_rotate.sel[30]_i_1 \n (.I0(\\victim_sel_reg_n_0_[0] ),\n .I1(\\victim_sel_reg_n_0_[2] ),\n .I2(\\victim_sel_reg_n_0_[1] ),\n .O(\\victim_sel_rotate.sel_reg[31] [6]));\n (* SOFT_HLUTNM = \"soft_lutpair568\" *) \n LUT3 #(\n .INIT(8'h80)) \n \\victim_sel_rotate.sel[31]_i_1 \n (.I0(\\victim_sel_reg_n_0_[1] ),\n .I1(\\victim_sel_reg_n_0_[0] ),\n .I2(\\victim_sel_reg_n_0_[2] ),\n .O(\\victim_sel_rotate.sel_reg[31] [7]));\n FDRE #(\n .INIT(1'b0)) \n wl_sm_start_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wr_level_dqs_asrt_r1),\n .Q(wl_sm_start),\n .R(rstdiv0_sync_r1_reg_rep__11));\n (* SOFT_HLUTNM = \"soft_lutpair542\" *) \n LUT4 #(\n .INIT(16'h00AE)) \n \\wr_done_victim_rotate.complex_row0_wr_done_i_1 \n (.I0(complex_row0_wr_done),\n .I1(rdlvl_stg1_done_r1),\n .I2(wr_victim_inc_i_2_n_0),\n .I3(complex_row0_wr_done0),\n .O(\\wr_done_victim_rotate.complex_row0_wr_done_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFEEFEEEEEEEEE)) \n \\wr_done_victim_rotate.complex_row0_wr_done_i_2 \n (.I0(complex_row0_rd_done1),\n .I1(complex_byte_rd_done),\n .I2(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ),\n .I3(prbs_rdlvl_done_reg),\n .I4(\\complex_row_cnt_ocal[7]_i_5_n_0 ),\n .I5(wr_victim_inc),\n .O(complex_row0_wr_done0));\n FDRE #(\n .INIT(1'b0)) \n \\wr_done_victim_rotate.complex_row0_wr_done_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_done_victim_rotate.complex_row0_wr_done_i_1_n_0 ),\n .Q(complex_row0_wr_done),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair542\" *) \n LUT4 #(\n .INIT(16'h00AE)) \n \\wr_done_victim_rotate.complex_row1_wr_done_i_1 \n (.I0(complex_row1_wr_done),\n .I1(complex_row0_wr_done),\n .I2(wr_victim_inc_i_2_n_0),\n .I3(complex_row0_wr_done0),\n .O(\\wr_done_victim_rotate.complex_row1_wr_done_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\wr_done_victim_rotate.complex_row1_wr_done_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_done_victim_rotate.complex_row1_wr_done_i_1_n_0 ),\n .Q(complex_row1_wr_done),\n .R(1'b0));\n LUT4 #(\n .INIT(16'h00E0)) \n wr_level_dqs_asrt_i_1\n (.I0(wr_level_dqs_asrt),\n .I1(wrlvl_active_r1),\n .I2(\\en_cnt_div4.wrlvl_odt_i_2_n_0 ),\n .I3(rstdiv0_sync_r1_reg_rep__24),\n .O(wr_level_dqs_asrt_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n wr_level_dqs_asrt_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wr_level_dqs_asrt),\n .Q(wr_level_dqs_asrt_r1),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n wr_level_dqs_asrt_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wr_level_dqs_asrt_i_1_n_0),\n .Q(wr_level_dqs_asrt),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h0000EA00)) \n wr_lvl_start_i_1\n (.I0(wr_level_start_r_reg),\n .I1(dqs_asrt_cnt[0]),\n .I2(dqs_asrt_cnt[1]),\n .I3(wrlvl_active),\n .I4(rstdiv0_sync_r1_reg_rep__23),\n .O(wr_lvl_start_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n wr_lvl_start_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wr_lvl_start_i_1_n_0),\n .Q(wr_level_start_r_reg),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair566\" *) \n LUT2 #(\n .INIT(4'hE)) \n wr_ptr0_i_1\n (.I0(init_calib_complete_reg_rep__14),\n .I1(calib_ctl_wren),\n .O(mux_cmd_wren));\n (* SOFT_HLUTNM = \"soft_lutpair566\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\wr_ptr[3]_i_3 \n (.I0(mc_wrdata_en),\n .I1(init_calib_complete_reg_rep__14),\n .I2(calib_wrdata_en),\n .O(mux_wrdata_en));\n (* SOFT_HLUTNM = \"soft_lutpair549\" *) \n LUT3 #(\n .INIT(8'h04)) \n wr_victim_inc_i_1\n (.I0(wr_victim_inc_i_2_n_0),\n .I1(complex_row0_wr_done),\n .I2(\\one_rank.stg1_wr_done_reg_0 ),\n .O(wr_victim_inc0));\n (* SOFT_HLUTNM = \"soft_lutpair500\" *) \n LUT5 #(\n .INIT(32'hFFFFFEFF)) \n wr_victim_inc_i_2\n (.I0(wr_victim_inc_i_3_n_0),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[5] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[0] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[1] ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[2] ),\n .O(wr_victim_inc_i_2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair514\" *) \n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n wr_victim_inc_i_3\n (.I0(\\stg1_wr_rd_cnt_reg_n_0_[3] ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[4] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[8] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[7] ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[6] ),\n .O(wr_victim_inc_i_3_n_0));\n FDRE #(\n .INIT(1'b0)) \n wr_victim_inc_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wr_victim_inc0),\n .Q(wr_victim_inc),\n .R(rstdiv0_sync_r1_reg_rep__12));\n (* SOFT_HLUTNM = \"soft_lutpair527\" *) \n LUT4 #(\n .INIT(16'h006A)) \n \\wr_victim_sel[0]_i_1 \n (.I0(wr_victim_sel[0]),\n .I1(wr_victim_inc),\n .I2(rdlvl_stg1_done_r1),\n .I3(p_81_in),\n .O(\\wr_victim_sel[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair527\" *) \n LUT5 #(\n .INIT(32'h00006AAA)) \n \\wr_victim_sel[1]_i_1 \n (.I0(wr_victim_sel[1]),\n .I1(wr_victim_inc),\n .I2(rdlvl_stg1_done_r1),\n .I3(wr_victim_sel[0]),\n .I4(p_81_in),\n .O(\\wr_victim_sel[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h000000006AAAAAAA)) \n \\wr_victim_sel[2]_i_1 \n (.I0(wr_victim_sel[2]),\n .I1(wr_victim_inc),\n .I2(rdlvl_stg1_done_r1),\n .I3(wr_victim_sel[1]),\n .I4(wr_victim_sel[0]),\n .I5(p_81_in),\n .O(\\wr_victim_sel[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair528\" *) \n LUT4 #(\n .INIT(16'h006A)) \n \\wr_victim_sel_ocal[0]_i_1 \n (.I0(wr_victim_sel_ocal[0]),\n .I1(prbs_rdlvl_done_reg),\n .I2(wr_victim_inc),\n .I3(rstdiv0_sync_r1_reg_rep__23_1),\n .O(\\wr_victim_sel_ocal[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair528\" *) \n LUT5 #(\n .INIT(32'h00006AAA)) \n \\wr_victim_sel_ocal[1]_i_1 \n (.I0(wr_victim_sel_ocal[1]),\n .I1(prbs_rdlvl_done_reg),\n .I2(wr_victim_inc),\n .I3(wr_victim_sel_ocal[0]),\n .I4(rstdiv0_sync_r1_reg_rep__23_1),\n .O(\\wr_victim_sel_ocal[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h000000006AAAAAAA)) \n \\wr_victim_sel_ocal[2]_i_1 \n (.I0(wr_victim_sel_ocal[2]),\n .I1(prbs_rdlvl_done_reg),\n .I2(wr_victim_inc),\n .I3(wr_victim_sel_ocal[1]),\n .I4(wr_victim_sel_ocal[0]),\n .I5(rstdiv0_sync_r1_reg_rep__23_1),\n .O(\\wr_victim_sel_ocal[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\wr_victim_sel_ocal_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_victim_sel_ocal[0]_i_1_n_0 ),\n .Q(wr_victim_sel_ocal[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wr_victim_sel_ocal_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_victim_sel_ocal[1]_i_1_n_0 ),\n .Q(wr_victim_sel_ocal[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wr_victim_sel_ocal_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_victim_sel_ocal[2]_i_1_n_0 ),\n .Q(wr_victim_sel_ocal[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wr_victim_sel_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_victim_sel[0]_i_1_n_0 ),\n .Q(wr_victim_sel[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wr_victim_sel_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_victim_sel[1]_i_1_n_0 ),\n .Q(wr_victim_sel[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wr_victim_sel_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_victim_sel[2]_i_1_n_0 ),\n .Q(wr_victim_sel[2]),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h2)) \n \\wrcal_dqs_cnt_r[2]_i_4 \n (.I0(wrcal_sanity_chk),\n .I1(wrcal_sanity_chk_r_reg),\n .O(\\wrcal_dqs_cnt_r_reg[0] ));\n LUT5 #(\n .INIT(32'hFFFF0080)) \n wrcal_final_chk_i_1\n (.I0(\\init_state_r[1]_i_1_n_0 ),\n .I1(\\init_state_r[0]_i_1_n_0 ),\n .I2(\\init_state_r[4]_i_1_n_0 ),\n .I3(wrcal_final_chk_i_2_n_0),\n .I4(wrcal_final_chk),\n .O(wrcal_final_chk_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair481\" *) \n LUT5 #(\n .INIT(32'hFFFFFFDF)) \n wrcal_final_chk_i_2\n (.I0(\\init_state_r[2]_i_1_n_0 ),\n .I1(\\init_state_r[5]_i_1_n_0 ),\n .I2(wrcal_done_reg_10),\n .I3(\\init_state_r[3]_i_2_n_0 ),\n .I4(\\init_state_r[6]_i_2_n_0 ),\n .O(wrcal_final_chk_i_2_n_0));\n FDRE #(\n .INIT(1'b0)) \n wrcal_final_chk_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrcal_final_chk_i_1_n_0),\n .Q(wrcal_final_chk),\n .R(rstdiv0_sync_r1_reg_rep__11));\n LUT6 #(\n .INIT(64'h0000000000100000)) \n wrcal_rd_wait_i_1\n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(\\wrcal_reads[7]_i_5_n_0 ),\n .I3(Q[5]),\n .I4(Q[4]),\n .I5(Q[3]),\n .O(wrcal_rd_wait_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n wrcal_rd_wait_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrcal_rd_wait_i_1_n_0),\n .Q(wrcal_rd_wait),\n .R(rstdiv0_sync_r1_reg_rep__12));\n (* SOFT_HLUTNM = \"soft_lutpair537\" *) \n LUT2 #(\n .INIT(4'hB)) \n \\wrcal_reads[0]_i_1 \n (.I0(wrcal_reads),\n .I1(\\wrcal_reads_reg_n_0_[0] ),\n .O(\\wrcal_reads[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair573\" *) \n LUT3 #(\n .INIT(8'hF9)) \n \\wrcal_reads[1]_i_1 \n (.I0(\\wrcal_reads_reg_n_0_[0] ),\n .I1(\\wrcal_reads_reg_n_0_[1] ),\n .I2(wrcal_reads),\n .O(\\wrcal_reads[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair496\" *) \n LUT4 #(\n .INIT(16'hFFE1)) \n \\wrcal_reads[2]_i_1 \n (.I0(\\wrcal_reads_reg_n_0_[1] ),\n .I1(\\wrcal_reads_reg_n_0_[0] ),\n .I2(\\wrcal_reads_reg_n_0_[2] ),\n .I3(wrcal_reads),\n .O(\\wrcal_reads[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair496\" *) \n LUT5 #(\n .INIT(32'hFFFFFE01)) \n \\wrcal_reads[3]_i_1 \n (.I0(\\wrcal_reads_reg_n_0_[0] ),\n .I1(\\wrcal_reads_reg_n_0_[1] ),\n .I2(\\wrcal_reads_reg_n_0_[2] ),\n .I3(\\wrcal_reads_reg_n_0_[3] ),\n .I4(wrcal_reads),\n .O(\\wrcal_reads[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFE0001)) \n \\wrcal_reads[4]_i_1 \n (.I0(\\wrcal_reads_reg_n_0_[3] ),\n .I1(\\wrcal_reads_reg_n_0_[2] ),\n .I2(\\wrcal_reads_reg_n_0_[1] ),\n .I3(\\wrcal_reads_reg_n_0_[0] ),\n .I4(\\wrcal_reads_reg_n_0_[4] ),\n .I5(wrcal_reads),\n .O(\\wrcal_reads[4]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair573\" *) \n LUT3 #(\n .INIT(8'hF6)) \n \\wrcal_reads[5]_i_1 \n (.I0(\\wrcal_reads[5]_i_2_n_0 ),\n .I1(\\wrcal_reads_reg_n_0_[5] ),\n .I2(wrcal_reads),\n .O(\\wrcal_reads[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h00000001)) \n \\wrcal_reads[5]_i_2 \n (.I0(\\wrcal_reads_reg_n_0_[4] ),\n .I1(\\wrcal_reads_reg_n_0_[0] ),\n .I2(\\wrcal_reads_reg_n_0_[1] ),\n .I3(\\wrcal_reads_reg_n_0_[2] ),\n .I4(\\wrcal_reads_reg_n_0_[3] ),\n .O(\\wrcal_reads[5]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair539\" *) \n LUT3 #(\n .INIT(8'hF6)) \n \\wrcal_reads[6]_i_1 \n (.I0(\\wrcal_reads[7]_i_7_n_0 ),\n .I1(\\wrcal_reads_reg_n_0_[6] ),\n .I2(wrcal_reads),\n .O(\\wrcal_reads[6]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAABAAAAAAAAAAAAA)) \n \\wrcal_reads[7]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__23),\n .I1(Q[3]),\n .I2(Q[4]),\n .I3(Q[5]),\n .I4(\\wrcal_reads[7]_i_5_n_0 ),\n .I5(\\wrcal_reads[7]_i_6_n_0 ),\n .O(wrcal_reads05_out));\n LUT4 #(\n .INIT(16'hFFFD)) \n \\wrcal_reads[7]_i_2 \n (.I0(\\wrcal_reads[7]_i_7_n_0 ),\n .I1(\\wrcal_reads_reg_n_0_[6] ),\n .I2(\\wrcal_reads_reg_n_0_[7] ),\n .I3(wrcal_reads),\n .O(\\wrcal_reads[7]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair539\" *) \n LUT4 #(\n .INIT(16'hFFD2)) \n \\wrcal_reads[7]_i_3 \n (.I0(\\wrcal_reads[7]_i_7_n_0 ),\n .I1(\\wrcal_reads_reg_n_0_[6] ),\n .I2(\\wrcal_reads_reg_n_0_[7] ),\n .I3(wrcal_reads),\n .O(\\wrcal_reads[7]_i_3_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\wrcal_reads[7]_i_5 \n (.I0(Q[2]),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .O(\\wrcal_reads[7]_i_5_n_0 ));\n LUT2 #(\n .INIT(4'h1)) \n \\wrcal_reads[7]_i_6 \n (.I0(Q[0]),\n .I1(Q[1]),\n .O(\\wrcal_reads[7]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000001)) \n \\wrcal_reads[7]_i_7 \n (.I0(\\wrcal_reads_reg_n_0_[3] ),\n .I1(\\wrcal_reads_reg_n_0_[2] ),\n .I2(\\wrcal_reads_reg_n_0_[1] ),\n .I3(\\wrcal_reads_reg_n_0_[0] ),\n .I4(\\wrcal_reads_reg_n_0_[4] ),\n .I5(\\wrcal_reads_reg_n_0_[5] ),\n .O(\\wrcal_reads[7]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000004000)) \n \\wrcal_reads[7]_i_8 \n (.I0(read_calib_i_2_n_0),\n .I1(\\wrcal_reads[7]_i_5_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .I3(\\wrcal_reads[7]_i_7_n_0 ),\n .I4(\\wrcal_reads_reg_n_0_[6] ),\n .I5(\\wrcal_reads_reg_n_0_[7] ),\n .O(wrcal_reads));\n FDRE #(\n .INIT(1'b0)) \n \\wrcal_reads_reg[0] \n (.C(CLK),\n .CE(\\wrcal_reads[7]_i_2_n_0 ),\n .D(\\wrcal_reads[0]_i_1_n_0 ),\n .Q(\\wrcal_reads_reg_n_0_[0] ),\n .R(wrcal_reads05_out));\n FDRE #(\n .INIT(1'b0)) \n \\wrcal_reads_reg[1] \n (.C(CLK),\n .CE(\\wrcal_reads[7]_i_2_n_0 ),\n .D(\\wrcal_reads[1]_i_1_n_0 ),\n .Q(\\wrcal_reads_reg_n_0_[1] ),\n .R(wrcal_reads05_out));\n FDRE #(\n .INIT(1'b0)) \n \\wrcal_reads_reg[2] \n (.C(CLK),\n .CE(\\wrcal_reads[7]_i_2_n_0 ),\n .D(\\wrcal_reads[2]_i_1_n_0 ),\n .Q(\\wrcal_reads_reg_n_0_[2] ),\n .R(wrcal_reads05_out));\n FDRE #(\n .INIT(1'b0)) \n \\wrcal_reads_reg[3] \n (.C(CLK),\n .CE(\\wrcal_reads[7]_i_2_n_0 ),\n .D(\\wrcal_reads[3]_i_1_n_0 ),\n .Q(\\wrcal_reads_reg_n_0_[3] ),\n .R(wrcal_reads05_out));\n FDRE #(\n .INIT(1'b0)) \n \\wrcal_reads_reg[4] \n (.C(CLK),\n .CE(\\wrcal_reads[7]_i_2_n_0 ),\n .D(\\wrcal_reads[4]_i_1_n_0 ),\n .Q(\\wrcal_reads_reg_n_0_[4] ),\n .R(wrcal_reads05_out));\n FDRE #(\n .INIT(1'b0)) \n \\wrcal_reads_reg[5] \n (.C(CLK),\n .CE(\\wrcal_reads[7]_i_2_n_0 ),\n .D(\\wrcal_reads[5]_i_1_n_0 ),\n .Q(\\wrcal_reads_reg_n_0_[5] ),\n .R(wrcal_reads05_out));\n FDRE #(\n .INIT(1'b0)) \n \\wrcal_reads_reg[6] \n (.C(CLK),\n .CE(\\wrcal_reads[7]_i_2_n_0 ),\n .D(\\wrcal_reads[6]_i_1_n_0 ),\n .Q(\\wrcal_reads_reg_n_0_[6] ),\n .R(wrcal_reads05_out));\n FDRE #(\n .INIT(1'b0)) \n \\wrcal_reads_reg[7] \n (.C(CLK),\n .CE(\\wrcal_reads[7]_i_2_n_0 ),\n .D(\\wrcal_reads[7]_i_3_n_0 ),\n .Q(\\wrcal_reads_reg_n_0_[7] ),\n .R(wrcal_reads05_out));\n FDRE #(\n .INIT(1'b0)) \n wrcal_resume_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrcal_resume_w),\n .Q(wrcal_resume_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n wrcal_sanity_chk_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrcal_final_chk),\n .Q(wrcal_sanity_chk),\n .R(1'b0));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_start_dly_r_reg \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_start_dly_r_reg[4]_srl5 \" *) \n SRL16E #(\n .INIT(16'h0000)) \n \\wrcal_start_dly_r_reg[4]_srl5 \n (.A0(1'b0),\n .A1(1'b0),\n .A2(1'b1),\n .A3(1'b0),\n .CE(1'b1),\n .CLK(CLK),\n .D(wrcal_start_pre),\n .Q(\\wrcal_start_dly_r_reg[4]_srl5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair489\" *) \n LUT5 #(\n .INIT(32'h01000400)) \n \\wrcal_start_dly_r_reg[4]_srl5_i_1 \n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(Q[2]),\n .I2(read_calib_i_2_n_0),\n .I3(Q[0]),\n .I4(Q[1]),\n .O(wrcal_start_pre));\n FDRE #(\n .INIT(1'b0)) \n \\wrcal_start_dly_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wrcal_start_dly_r_reg[4]_srl5_n_0 ),\n .Q(wrcal_start_dly_r),\n .R(1'b0));\n LUT4 #(\n .INIT(16'h000E)) \n wrcal_start_i_1\n (.I0(wrcal_start_reg_0),\n .I1(wrcal_start_dly_r),\n .I2(wrlvl_byte_redo),\n .I3(rstdiv0_sync_r1_reg_rep__23),\n .O(wrcal_start_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n wrcal_start_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrcal_start_i_1_n_0),\n .Q(wrcal_start_reg_0),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair610\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\wrcal_wr_cnt[0]_i_1 \n (.I0(wrcal_wr_cnt_reg__0[0]),\n .O(\\wrcal_wr_cnt[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair610\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\wrcal_wr_cnt[1]_i_1 \n (.I0(wrcal_wr_cnt_reg__0[0]),\n .I1(wrcal_wr_cnt_reg__0[1]),\n .O(\\wrcal_wr_cnt[1]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hA9)) \n \\wrcal_wr_cnt[2]_i_1 \n (.I0(wrcal_wr_cnt_reg__0[2]),\n .I1(wrcal_wr_cnt_reg__0[1]),\n .I2(wrcal_wr_cnt_reg__0[0]),\n .O(wrcal_wr_cnt0[2]));\n LUT6 #(\n .INIT(64'hFFFFFFFF111111F1)) \n \\wrcal_wr_cnt[3]_i_1 \n (.I0(first_wrcal_pat_r_i_2_n_0),\n .I1(complex_oclkdelay_calib_start_int_reg_0),\n .I2(\\wrcal_wr_cnt[3]_i_4_n_0 ),\n .I3(wrcal_wr_cnt_reg__0[3]),\n .I4(wrcal_wr_cnt_reg__0[2]),\n .I5(rstdiv0_sync_r1_reg_rep__23),\n .O(\\wrcal_wr_cnt[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000020)) \n \\wrcal_wr_cnt[3]_i_2 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .I1(Q[3]),\n .I2(Q[4]),\n .I3(Q[5]),\n .I4(Q[2]),\n .I5(\\init_state_r_reg_n_0_[3] ),\n .O(\\wrcal_wr_cnt[3]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair561\" *) \n LUT4 #(\n .INIT(16'hCCC9)) \n \\wrcal_wr_cnt[3]_i_3 \n (.I0(wrcal_wr_cnt_reg__0[2]),\n .I1(wrcal_wr_cnt_reg__0[3]),\n .I2(wrcal_wr_cnt_reg__0[0]),\n .I3(wrcal_wr_cnt_reg__0[1]),\n .O(wrcal_wr_cnt0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair561\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\wrcal_wr_cnt[3]_i_4 \n (.I0(wrcal_wr_cnt_reg__0[0]),\n .I1(wrcal_wr_cnt_reg__0[1]),\n .O(\\wrcal_wr_cnt[3]_i_4_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\wrcal_wr_cnt_reg[0] \n (.C(CLK),\n .CE(\\wrcal_wr_cnt[3]_i_2_n_0 ),\n .D(\\wrcal_wr_cnt[0]_i_1_n_0 ),\n .Q(wrcal_wr_cnt_reg__0[0]),\n .R(\\wrcal_wr_cnt[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\wrcal_wr_cnt_reg[1] \n (.C(CLK),\n .CE(\\wrcal_wr_cnt[3]_i_2_n_0 ),\n .D(\\wrcal_wr_cnt[1]_i_1_n_0 ),\n .Q(wrcal_wr_cnt_reg__0[1]),\n .R(\\wrcal_wr_cnt[3]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\wrcal_wr_cnt_reg[2] \n (.C(CLK),\n .CE(\\wrcal_wr_cnt[3]_i_2_n_0 ),\n .D(wrcal_wr_cnt0[2]),\n .Q(wrcal_wr_cnt_reg__0[2]),\n .S(\\wrcal_wr_cnt[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\wrcal_wr_cnt_reg[3] \n (.C(CLK),\n .CE(\\wrcal_wr_cnt[3]_i_2_n_0 ),\n .D(wrcal_wr_cnt0[3]),\n .Q(wrcal_wr_cnt_reg__0[3]),\n .R(\\wrcal_wr_cnt[3]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h2F)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1 \n (.I0(first_wrcal_pat_r),\n .I1(wrcal_done_reg_10),\n .I2(oclkdelay_calib_done_r_reg_2),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFAFF3AFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[250]_i_1 \n (.I0(first_wrcal_pat_r),\n .I1(rdlvl_stg1_done_int_reg),\n .I2(wrcal_done_reg_10),\n .I3(oclkdelay_calib_done_r_reg_2),\n .I4(\\dout_o_reg[0]_0 ),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata[250]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFAFF3AFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[254]_i_2 \n (.I0(first_wrcal_pat_r),\n .I1(rdlvl_stg1_done_int_reg),\n .I2(wrcal_done_reg_10),\n .I3(oclkdelay_calib_done_r_reg_2),\n .I4(\\dout_o_reg[0] ),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata[254]_i_2_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[120] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[12]_0 ),\n .Q(phy_wrdata[120]),\n .S(\\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[121] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(wrcal_done_reg_8),\n .Q(phy_wrdata[121]),\n .S(wrcal_done_reg_0));\n FDSE #(\n .INIT(1'b1)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[122] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[4]_0 ),\n .Q(phy_wrdata[122]),\n .S(wrcal_done_reg_2));\n FDSE #(\n .INIT(1'b1)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[123] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(wrcal_done_reg_7),\n .Q(phy_wrdata[123]),\n .S(wrcal_done_reg_0));\n FDSE #(\n .INIT(1'b1)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[124] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[12] ),\n .Q(phy_wrdata[124]),\n .S(\\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[125] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(wrcal_done_reg_6),\n .Q(phy_wrdata[125]),\n .S(wrcal_done_reg_0));\n FDSE #(\n .INIT(1'b1)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[126] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[4] ),\n .Q(phy_wrdata[126]),\n .S(wrcal_done_reg_2));\n FDSE #(\n .INIT(1'b1)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[127] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(wrcal_done_reg_5),\n .Q(phy_wrdata[127]),\n .S(wrcal_done_reg_0));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[152] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[3]_0 ),\n .Q(phy_wrdata[152]),\n .R(wrcal_done_reg_1));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[153] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[11]_0 ),\n .Q(phy_wrdata[153]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[154] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[11]_4 ),\n .Q(phy_wrdata[154]),\n .R(oclkdelay_calib_done_r_reg_1));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[155] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[11]_2 ),\n .Q(phy_wrdata[155]),\n .R(wrcal_done_reg));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[156] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[3] ),\n .Q(phy_wrdata[156]),\n .R(wrcal_done_reg_1));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[157] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[11] ),\n .Q(phy_wrdata[157]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[158] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[11]_3 ),\n .Q(phy_wrdata[158]),\n .R(oclkdelay_calib_done_r_reg_1));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[159] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[11]_1 ),\n .Q(phy_wrdata[159]),\n .R(wrcal_done_reg));\n FDSE #(\n .INIT(1'b1)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[184] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(wrcal_done_reg_4),\n .Q(phy_wrdata[184]),\n .S(wrcal_done_reg_0));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[185] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(oclkdelay_calib_done_r_reg_0),\n .Q(phy_wrdata[185]),\n .R(1'b0));\n FDSE #(\n .INIT(1'b1)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[10]_0 ),\n .Q(phy_wrdata[186]),\n .S(wrcal_done_reg_1));\n FDSE #(\n .INIT(1'b1)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[2]_0 ),\n .Q(phy_wrdata[187]),\n .S(wrcal_done_reg_2));\n FDSE #(\n .INIT(1'b1)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[188] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(wrcal_done_reg_3),\n .Q(phy_wrdata[188]),\n .S(wrcal_done_reg_0));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[189] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(oclkdelay_calib_done_r_reg),\n .Q(phy_wrdata[189]),\n .R(1'b0));\n FDSE #(\n .INIT(1'b1)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[190] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[10] ),\n .Q(phy_wrdata[190]),\n .S(wrcal_done_reg_1));\n FDSE #(\n .INIT(1'b1)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[2] ),\n .Q(phy_wrdata[191]),\n .S(wrcal_done_reg_2));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[216] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[9]_4 ),\n .Q(phy_wrdata[216]),\n .R(wrcal_done_reg_0));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[217] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[9]_0 ),\n .Q(phy_wrdata[217]),\n .R(wrcal_done_reg));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[218] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[1]_0 ),\n .Q(phy_wrdata[218]),\n .R(\\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[219] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[9]_3 ),\n .Q(phy_wrdata[219]),\n .R(wrcal_done_reg_0));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[220] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[9]_2 ),\n .Q(phy_wrdata[220]),\n .R(wrcal_done_reg_0));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[9] ),\n .Q(phy_wrdata[221]),\n .R(wrcal_done_reg));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[222] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[1] ),\n .Q(phy_wrdata[222]),\n .R(\\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[223] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[9]_1 ),\n .Q(phy_wrdata[223]),\n .R(wrcal_done_reg_0));\n FDSE #(\n .INIT(1'b1)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[248] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[8]_0 ),\n .Q(phy_wrdata[248]),\n .S(oclkdelay_calib_done_r_reg_1));\n FDSE #(\n .INIT(1'b1)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[249] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[8]_4 ),\n .Q(phy_wrdata[249]),\n .S(\\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[24] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[15]_2 ),\n .Q(phy_wrdata[24]),\n .R(oclkdelay_calib_done_r_reg_1));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[250] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\wrdq_div1_4to1_wrcal_first.phy_wrdata[250]_i_1_n_0 ),\n .Q(phy_wrdata[250]),\n .R(1'b0));\n FDSE #(\n .INIT(1'b1)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[251] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[8]_2 ),\n .Q(phy_wrdata[251]),\n .S(wrcal_done_reg_1));\n FDSE #(\n .INIT(1'b1)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[252] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[8] ),\n .Q(phy_wrdata[252]),\n .S(oclkdelay_calib_done_r_reg_1));\n FDSE #(\n .INIT(1'b1)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[253] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[8]_3 ),\n .Q(phy_wrdata[253]),\n .S(\\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[254] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\wrdq_div1_4to1_wrcal_first.phy_wrdata[254]_i_2_n_0 ),\n .Q(phy_wrdata[254]),\n .R(1'b0));\n FDSE #(\n .INIT(1'b1)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[255] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[8]_1 ),\n .Q(phy_wrdata[255]),\n .S(wrcal_done_reg_1));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[25] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[7]_0 ),\n .Q(phy_wrdata[25]),\n .R(oclkdelay_calib_done_r_reg_1));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[26] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[7]_2 ),\n .Q(phy_wrdata[26]),\n .R(wrcal_done_reg_1));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[27] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[15]_1 ),\n .Q(phy_wrdata[27]),\n .R(oclkdelay_calib_done_r_reg_1));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[28] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[15]_0 ),\n .Q(phy_wrdata[28]),\n .R(oclkdelay_calib_done_r_reg_1));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[29] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[7] ),\n .Q(phy_wrdata[29]),\n .R(oclkdelay_calib_done_r_reg_1));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[30] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[7]_1 ),\n .Q(phy_wrdata[30]),\n .R(wrcal_done_reg_1));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[31] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[15] ),\n .Q(phy_wrdata[31]),\n .R(oclkdelay_calib_done_r_reg_1));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(D[0]),\n .Q(phy_wrdata[56]),\n .R(1'b0));\n FDSE #(\n .INIT(1'b1)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(first_rdlvl_pat_r_reg_0),\n .Q(phy_wrdata[57]),\n .S(oclkdelay_calib_done_r_reg_1));\n FDSE #(\n .INIT(1'b1)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[58] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[14]_2 ),\n .Q(phy_wrdata[58]),\n .S(oclkdelay_calib_done_r_reg_1));\n FDSE #(\n .INIT(1'b1)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[59] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[14]_1 ),\n .Q(phy_wrdata[59]),\n .S(oclkdelay_calib_done_r_reg_1));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[60] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(D[1]),\n .Q(phy_wrdata[60]),\n .R(1'b0));\n FDSE #(\n .INIT(1'b1)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[61] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[6] ),\n .Q(phy_wrdata[61]),\n .S(oclkdelay_calib_done_r_reg_1));\n FDSE #(\n .INIT(1'b1)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[62] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[14]_0 ),\n .Q(phy_wrdata[62]),\n .S(oclkdelay_calib_done_r_reg_1));\n FDSE #(\n .INIT(1'b1)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[63] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[14] ),\n .Q(phy_wrdata[63]),\n .S(oclkdelay_calib_done_r_reg_1));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[88] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[13]_0 ),\n .Q(phy_wrdata[88]),\n .R(wrcal_done_reg));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[89] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[13]_6 ),\n .Q(phy_wrdata[89]),\n .R(oclkdelay_calib_done_r_reg_1));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[90] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[13]_4 ),\n .Q(phy_wrdata[90]),\n .R(\\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[13]_2 ),\n .Q(phy_wrdata[91]),\n .R(wrcal_done_reg_0));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[92] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[13] ),\n .Q(phy_wrdata[92]),\n .R(wrcal_done_reg));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[93] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[13]_5 ),\n .Q(phy_wrdata[93]),\n .R(oclkdelay_calib_done_r_reg_1));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[94] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[13]_3 ),\n .Q(phy_wrdata[94]),\n .R(\\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[95] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[13]_1 ),\n .Q(phy_wrdata[95]),\n .R(wrcal_done_reg_0));\n LUT6 #(\n .INIT(64'h000000000EEEEEEE)) \n write_calib_i_1\n (.I0(phy_write_calib),\n .I1(wrlvl_active_r1),\n .I2(done_dqs_tap_inc),\n .I3(write_calib_i_2_n_0),\n .I4(Q[1]),\n .I5(rstdiv0_sync_r1_reg_rep__23),\n .O(write_calib_i_1_n_0));\n LUT6 #(\n .INIT(64'h0000000000000004)) \n write_calib_i_2\n (.I0(Q[0]),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .I2(Q[2]),\n .I3(Q[5]),\n .I4(Q[4]),\n .I5(Q[3]),\n .O(write_calib_i_2_n_0));\n FDRE #(\n .INIT(1'b0)) \n write_calib_reg\n (.C(CLK),\n .CE(1'b1),\n .D(write_calib_i_1_n_0),\n .Q(phy_write_calib),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000000000EA)) \n wrlvl_active_i_1\n (.I0(wrlvl_active),\n .I1(\\en_cnt_div4.wrlvl_odt_i_2_n_0 ),\n .I2(wrlvl_odt),\n .I3(rstdiv0_sync_r1_reg_rep__24),\n .I4(done_dqs_tap_inc),\n .I5(wrlvl_rank_done),\n .O(wrlvl_active_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n wrlvl_active_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrlvl_active),\n .Q(wrlvl_active_r1),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n wrlvl_active_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrlvl_active_i_1_n_0),\n .Q(wrlvl_active),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n wrlvl_done_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrlvl_done_r),\n .Q(wrlvl_done_r1),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n wrlvl_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wr_level_done_reg),\n .Q(wrlvl_done_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000000000AE)) \n wrlvl_final_if_rst_i_1\n (.I0(wrlvl_final_if_rst),\n .I1(wrlvl_done_r),\n .I2(wrlvl_final_if_rst_i_2_n_0),\n .I3(rstdiv0_sync_r1_reg_rep__24),\n .I4(\\cnt_init_mr_r_reg[1]_0 ),\n .I5(\\wrcal_wr_cnt[3]_i_2_n_0 ),\n .O(wrlvl_final_if_rst_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFDFFFF)) \n wrlvl_final_if_rst_i_2\n (.I0(Q[1]),\n .I1(Q[3]),\n .I2(Q[4]),\n .I3(Q[5]),\n .I4(\\init_state_r_reg[1]_0 ),\n .I5(Q[0]),\n .O(wrlvl_final_if_rst_i_2_n_0));\n FDRE #(\n .INIT(1'b0)) \n wrlvl_final_if_rst_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrlvl_final_if_rst_i_1_n_0),\n .Q(wrlvl_final_if_rst),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h000000AE)) \n wrlvl_odt_ctl_i_1\n (.I0(wrlvl_odt_ctl),\n .I1(wrlvl_rank_done),\n .I2(wrlvl_rank_done_r1),\n .I3(wrlvl_odt_ctl_i_2_n_0),\n .I4(rstdiv0_sync_r1_reg_rep__24),\n .O(wrlvl_odt_ctl_i_1_n_0));\n LUT6 #(\n .INIT(64'h0001000100010000)) \n wrlvl_odt_ctl_i_2\n (.I0(read_calib_reg_0),\n .I1(Q[3]),\n .I2(Q[4]),\n .I3(Q[5]),\n .I4(wrlvl_odt_ctl_i_3_n_0),\n .I5(init_state_r1[3]),\n .O(wrlvl_odt_ctl_i_2_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFDF)) \n wrlvl_odt_ctl_i_3\n (.I0(init_state_r1[1]),\n .I1(init_state_r1[6]),\n .I2(init_state_r1[2]),\n .I3(init_state_r1[5]),\n .I4(init_state_r1[4]),\n .I5(init_state_r1[0]),\n .O(wrlvl_odt_ctl_i_3_n_0));\n FDRE #(\n .INIT(1'b0)) \n wrlvl_odt_ctl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrlvl_odt_ctl_i_1_n_0),\n .Q(wrlvl_odt_ctl),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n wrlvl_rank_done_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrlvl_rank_done),\n .Q(wrlvl_rank_done_r1),\n .R(1'b0));\n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrlvl_rank_done_r6_reg_srl5 \" *) \n SRL16E #(\n .INIT(16'h0000)) \n wrlvl_rank_done_r6_reg_srl5\n (.A0(1'b0),\n .A1(1'b0),\n .A2(1'b1),\n .A3(1'b0),\n .CE(1'b1),\n .CLK(CLK),\n .D(wrlvl_rank_done_r1),\n .Q(wrlvl_rank_done_r6_reg_srl5_n_0));\n FDRE #(\n .INIT(1'b0)) \n wrlvl_rank_done_r7_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrlvl_rank_done_r6_reg_srl5_n_0),\n .Q(wrlvl_rank_done_r7),\n .R(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_phy_ocd_cntlr\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_phy_ocd_cntlr\n (prech_req_r_reg,\n rd_active_r1_reg,\n lim_start,\n wrlvl_final_mux_reg,\n reset_scan,\n complex_ocal_ref_req,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ,\n \\byte_r_reg[1]_0 ,\n \\byte_r_reg[0]_0 ,\n D,\n \\simp_stg3_final_r_reg[23] ,\n \\simp_stg3_final_r_reg[11] ,\n \\simp_stg3_final_r_reg[5] ,\n \\simp_stg3_final_r_reg[17] ,\n done_r_reg,\n \\rd_victim_sel_r_reg[0] ,\n \\stg3_init_val_reg[3] ,\n sr_valid_r108_out,\n \\init_state_r_reg[2] ,\n \\init_state_r_reg[5] ,\n ocal_last_byte_done_reg,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[1] ,\n \\cal2_state_r_reg[0] ,\n ocd_cntlr2stg2_dec_r,\n rstdiv0_sync_r1_reg_rep__9,\n CLK,\n phy_rddata_en,\n rstdiv0_sync_r1_reg_rep__10,\n rstdiv0_sync_r1_reg_rep__25,\n done_r_reg_0,\n oclkdelay_calib_start_int_reg,\n prech_req_r_reg_0,\n rstdiv0_sync_r1_reg_rep__25_0,\n po_rdy,\n \\po_counter_read_val_reg[2] ,\n \\simp_stg3_final_r_reg[17]_0 ,\n \\simp_stg3_final_r_reg[16] ,\n \\simp_stg3_final_r_reg[10] ,\n \\simp_stg3_final_r_reg[2] ,\n \\simp_stg3_final_r_reg[8] ,\n \\simp_stg3_final_r_reg[19] ,\n \\simp_stg3_final_r_reg[12] ,\n lim_start_r,\n rstdiv0_sync_r1_reg_rep__24,\n \\data_cnt_r_reg[7] ,\n rstdiv0_sync_r1_reg_rep__20,\n rdlvl_stg1_start_reg,\n \\cnt_shift_r_reg[0] ,\n \\init_state_r_reg[0] ,\n \\init_state_r_reg[2]_0 ,\n prbs_rdlvl_done_reg,\n oclk_calib_resume_r_reg,\n prech_req_posedge_r_reg,\n cnt_cmd_done_r,\n oclkdelay_center_calib_done_r_reg,\n ocal_last_byte_done,\n \\po_stg2_wrcal_cnt_reg[0] ,\n wr_level_done_reg,\n oclkdelay_calib_done_r_reg_0,\n pi_stg2_rdlvl_cnt,\n \\po_stg2_wrcal_cnt_reg[1] ,\n rd_active_r1,\n wrlvl_byte_done,\n rstdiv0_sync_r1_reg_rep__2,\n prech_done,\n oclkdelay_calib_start_int_reg_0);\n output prech_req_r_reg;\n output rd_active_r1_reg;\n output lim_start;\n output wrlvl_final_mux_reg;\n output reset_scan;\n output complex_ocal_ref_req;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ;\n output \\byte_r_reg[1]_0 ;\n output \\byte_r_reg[0]_0 ;\n output [4:0]D;\n output \\simp_stg3_final_r_reg[23] ;\n output \\simp_stg3_final_r_reg[11] ;\n output \\simp_stg3_final_r_reg[5] ;\n output \\simp_stg3_final_r_reg[17] ;\n output done_r_reg;\n output \\rd_victim_sel_r_reg[0] ;\n output \\stg3_init_val_reg[3] ;\n output sr_valid_r108_out;\n output \\init_state_r_reg[2] ;\n output \\init_state_r_reg[5] ;\n output ocal_last_byte_done_reg;\n output \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ;\n output \\gen_byte_sel_div1.byte_sel_cnt_reg[1] ;\n output \\cal2_state_r_reg[0] ;\n output ocd_cntlr2stg2_dec_r;\n input rstdiv0_sync_r1_reg_rep__9;\n input CLK;\n input phy_rddata_en;\n input rstdiv0_sync_r1_reg_rep__10;\n input rstdiv0_sync_r1_reg_rep__25;\n input done_r_reg_0;\n input oclkdelay_calib_start_int_reg;\n input prech_req_r_reg_0;\n input rstdiv0_sync_r1_reg_rep__25_0;\n input po_rdy;\n input \\po_counter_read_val_reg[2] ;\n input \\simp_stg3_final_r_reg[17]_0 ;\n input \\simp_stg3_final_r_reg[16] ;\n input \\simp_stg3_final_r_reg[10] ;\n input \\simp_stg3_final_r_reg[2] ;\n input \\simp_stg3_final_r_reg[8] ;\n input \\simp_stg3_final_r_reg[19] ;\n input \\simp_stg3_final_r_reg[12] ;\n input lim_start_r;\n input rstdiv0_sync_r1_reg_rep__24;\n input \\data_cnt_r_reg[7] ;\n input rstdiv0_sync_r1_reg_rep__20;\n input rdlvl_stg1_start_reg;\n input \\cnt_shift_r_reg[0] ;\n input \\init_state_r_reg[0] ;\n input [1:0]\\init_state_r_reg[2]_0 ;\n input prbs_rdlvl_done_reg;\n input oclk_calib_resume_r_reg;\n input prech_req_posedge_r_reg;\n input cnt_cmd_done_r;\n input oclkdelay_center_calib_done_r_reg;\n input ocal_last_byte_done;\n input \\po_stg2_wrcal_cnt_reg[0] ;\n input wr_level_done_reg;\n input oclkdelay_calib_done_r_reg_0;\n input [1:0]pi_stg2_rdlvl_cnt;\n input \\po_stg2_wrcal_cnt_reg[1] ;\n input rd_active_r1;\n input wrlvl_byte_done;\n input rstdiv0_sync_r1_reg_rep__2;\n input prech_done;\n input oclkdelay_calib_start_int_reg_0;\n\n wire CLK;\n wire [4:0]D;\n wire \\FSM_sequential_sm_r[0]_i_1_n_0 ;\n wire \\FSM_sequential_sm_r[1]_i_1_n_0 ;\n wire \\FSM_sequential_sm_r[2]_i_2_n_0 ;\n wire \\FSM_sequential_sm_r[2]_i_3_n_0 ;\n wire \\FSM_sequential_sm_r[2]_i_5_n_0 ;\n wire \\FSM_sequential_sm_r[2]_i_6_n_0 ;\n wire \\FSM_sequential_sm_r_reg[2]_i_4_n_0 ;\n wire \\byte_r[0]_i_1_n_0 ;\n wire \\byte_r[0]_i_2_n_0 ;\n wire \\byte_r[1]_i_1_n_0 ;\n wire \\byte_r[1]_i_2_n_0 ;\n wire \\byte_r_reg[0]_0 ;\n wire \\byte_r_reg[1]_0 ;\n wire \\cal2_state_r_reg[0] ;\n wire cnt_cmd_done_r;\n wire \\cnt_shift_r_reg[0] ;\n wire complex_ocal_ref_req;\n wire \\data_cnt_r_reg[7] ;\n wire done_r_reg;\n wire done_r_reg_0;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[1] ;\n wire \\init_state_r_reg[0] ;\n wire \\init_state_r_reg[2] ;\n wire [1:0]\\init_state_r_reg[2]_0 ;\n wire \\init_state_r_reg[5] ;\n wire lim_start;\n wire lim_start_r;\n wire lim_start_r_i_1_n_0;\n wire lim_start_r_i_2_n_0;\n wire ocal_last_byte_done;\n wire ocal_last_byte_done_reg;\n wire ocd_cntlr2stg2_dec_r;\n wire ocd_prech_req_ns;\n wire oclk_calib_resume_r_reg;\n wire oclkdelay_calib_done_r_i_1_n_0;\n wire oclkdelay_calib_done_r_i_3_n_0;\n wire oclkdelay_calib_done_r_reg_0;\n wire oclkdelay_calib_start_int_reg;\n wire oclkdelay_calib_start_int_reg_0;\n wire oclkdelay_center_calib_done_r_reg;\n wire phy_rddata_en;\n wire [1:0]pi_stg2_rdlvl_cnt;\n wire \\po_counter_read_val_reg[2] ;\n wire [3:0]po_rd_wait_ns;\n wire \\po_rd_wait_r[0]_i_2_n_0 ;\n wire \\po_rd_wait_r[1]_i_2_n_0 ;\n wire \\po_rd_wait_r[2]_i_2_n_0 ;\n wire \\po_rd_wait_r[2]_i_3_n_0 ;\n wire \\po_rd_wait_r[3]_i_1_n_0 ;\n wire \\po_rd_wait_r[3]_i_3_n_0 ;\n wire \\po_rd_wait_r[3]_i_4_n_0 ;\n wire \\po_rd_wait_r[3]_i_5_n_0 ;\n wire \\po_rd_wait_r[3]_i_6_n_0 ;\n wire [3:0]po_rd_wait_r_reg__0;\n wire po_rdy;\n wire \\po_stg2_wrcal_cnt_reg[0] ;\n wire \\po_stg2_wrcal_cnt_reg[1] ;\n wire prbs_rdlvl_done_reg;\n wire prech_done;\n wire prech_req_posedge_r_reg;\n wire prech_req_r_reg;\n wire prech_req_r_reg_0;\n wire rd_active_r1;\n wire rd_active_r1_reg;\n wire \\rd_victim_sel_r_reg[0] ;\n wire rdlvl_stg1_start_reg;\n wire reset_scan;\n wire reset_scan_r_i_1_n_0;\n wire rstdiv0_sync_r1_reg_rep__10;\n wire rstdiv0_sync_r1_reg_rep__2;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__24;\n wire rstdiv0_sync_r1_reg_rep__25;\n wire rstdiv0_sync_r1_reg_rep__25_0;\n wire rstdiv0_sync_r1_reg_rep__9;\n wire \\simp_stg3_final_r_reg[10] ;\n wire \\simp_stg3_final_r_reg[11] ;\n wire \\simp_stg3_final_r_reg[12] ;\n wire \\simp_stg3_final_r_reg[16] ;\n wire \\simp_stg3_final_r_reg[17] ;\n wire \\simp_stg3_final_r_reg[17]_0 ;\n wire \\simp_stg3_final_r_reg[19] ;\n wire \\simp_stg3_final_r_reg[23] ;\n wire \\simp_stg3_final_r_reg[2] ;\n wire \\simp_stg3_final_r_reg[5] ;\n wire \\simp_stg3_final_r_reg[8] ;\n (* RTL_KEEP = \"yes\" *) wire [2:0]sm_r;\n wire sr_valid_r108_out;\n wire \\stg3_init_val_reg[3] ;\n wire wr_level_done_reg;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ;\n wire wrlvl_byte_done;\n wire wrlvl_final_mux_reg;\n wire wrlvl_final_r0;\n\n LUT3 #(\n .INIT(8'h74)) \n \\FSM_sequential_sm_r[0]_i_1 \n (.I0(sm_r[0]),\n .I1(\\FSM_sequential_sm_r_reg[2]_i_4_n_0 ),\n .I2(sm_r[0]),\n .O(\\FSM_sequential_sm_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8FB0FFFF8FB00000)) \n \\FSM_sequential_sm_r[1]_i_1 \n (.I0(\\FSM_sequential_sm_r[2]_i_3_n_0 ),\n .I1(sm_r[2]),\n .I2(sm_r[1]),\n .I3(sm_r[0]),\n .I4(\\FSM_sequential_sm_r_reg[2]_i_4_n_0 ),\n .I5(sm_r[1]),\n .O(\\FSM_sequential_sm_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAFC0FFFFAFC00000)) \n \\FSM_sequential_sm_r[2]_i_2 \n (.I0(\\FSM_sequential_sm_r[2]_i_3_n_0 ),\n .I1(sm_r[0]),\n .I2(sm_r[1]),\n .I3(sm_r[2]),\n .I4(\\FSM_sequential_sm_r_reg[2]_i_4_n_0 ),\n .I5(sm_r[2]),\n .O(\\FSM_sequential_sm_r[2]_i_2_n_0 ));\n LUT3 #(\n .INIT(8'h08)) \n \\FSM_sequential_sm_r[2]_i_3 \n (.I0(\\byte_r_reg[0]_0 ),\n .I1(\\byte_r_reg[1]_0 ),\n .I2(sm_r[0]),\n .O(\\FSM_sequential_sm_r[2]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hBBBBCFCC)) \n \\FSM_sequential_sm_r[2]_i_5 \n (.I0(prech_done),\n .I1(sm_r[2]),\n .I2(wrlvl_final_mux_reg),\n .I3(oclkdelay_calib_start_int_reg_0),\n .I4(sm_r[0]),\n .O(\\FSM_sequential_sm_r[2]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB8CC)) \n \\FSM_sequential_sm_r[2]_i_6 \n (.I0(oclkdelay_calib_done_r_i_3_n_0),\n .I1(sm_r[2]),\n .I2(rstdiv0_sync_r1_reg_rep__25),\n .I3(sm_r[0]),\n .I4(done_r_reg_0),\n .O(\\FSM_sequential_sm_r[2]_i_6_n_0 ));\n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\FSM_sequential_sm_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_sm_r[0]_i_1_n_0 ),\n .Q(sm_r[0]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\FSM_sequential_sm_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_sm_r[1]_i_1_n_0 ),\n .Q(sm_r[1]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\FSM_sequential_sm_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_sm_r[2]_i_2_n_0 ),\n .Q(sm_r[2]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n MUXF7 \\FSM_sequential_sm_r_reg[2]_i_4 \n (.I0(\\FSM_sequential_sm_r[2]_i_5_n_0 ),\n .I1(\\FSM_sequential_sm_r[2]_i_6_n_0 ),\n .O(\\FSM_sequential_sm_r_reg[2]_i_4_n_0 ),\n .S(sm_r[1]));\n LUT6 #(\n .INIT(64'hFFFF5EDE0000A020)) \n \\byte_r[0]_i_1 \n (.I0(sm_r[2]),\n .I1(sm_r[0]),\n .I2(sm_r[1]),\n .I3(\\byte_r[0]_i_2_n_0 ),\n .I4(rstdiv0_sync_r1_reg_rep__25_0),\n .I5(\\byte_r_reg[0]_0 ),\n .O(\\byte_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair350\" *) \n LUT5 #(\n .INIT(32'h00000444)) \n \\byte_r[0]_i_2 \n (.I0(\\po_rd_wait_r[3]_i_6_n_0 ),\n .I1(po_rdy),\n .I2(\\byte_r_reg[1]_0 ),\n .I3(\\byte_r_reg[0]_0 ),\n .I4(\\po_counter_read_val_reg[2] ),\n .O(\\byte_r[0]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'h4F80)) \n \\byte_r[1]_i_1 \n (.I0(\\byte_r_reg[0]_0 ),\n .I1(sm_r[1]),\n .I2(\\byte_r[1]_i_2_n_0 ),\n .I3(\\byte_r_reg[1]_0 ),\n .O(\\byte_r[1]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h0000A121)) \n \\byte_r[1]_i_2 \n (.I0(sm_r[2]),\n .I1(sm_r[0]),\n .I2(sm_r[1]),\n .I3(\\byte_r[0]_i_2_n_0 ),\n .I4(rstdiv0_sync_r1_reg_rep__25_0),\n .O(\\byte_r[1]_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\byte_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r[0]_i_1_n_0 ),\n .Q(\\byte_r_reg[0]_0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\byte_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r[1]_i_1_n_0 ),\n .Q(\\byte_r_reg[1]_0 ),\n .R(1'b0));\n LUT3 #(\n .INIT(8'h40)) \n \\cal2_state_r[3]_i_10 \n (.I0(rd_active_r1_reg),\n .I1(rd_active_r1),\n .I2(wrlvl_byte_done),\n .O(\\cal2_state_r_reg[0] ));\n LUT2 #(\n .INIT(4'h2)) \n done_r_i_2\n (.I0(lim_start),\n .I1(lim_start_r),\n .O(done_r_reg));\n LUT6 #(\n .INIT(64'hFF00F4000000F400)) \n \\gen_byte_sel_div1.byte_sel_cnt[0]_i_2 \n (.I0(wrlvl_final_mux_reg),\n .I1(\\byte_r_reg[0]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[0] ),\n .I3(wr_level_done_reg),\n .I4(oclkdelay_calib_done_r_reg_0),\n .I5(pi_stg2_rdlvl_cnt[0]),\n .O(\\gen_byte_sel_div1.byte_sel_cnt_reg[0] ));\n LUT6 #(\n .INIT(64'hFF00F4000000F400)) \n \\gen_byte_sel_div1.byte_sel_cnt[1]_i_2 \n (.I0(wrlvl_final_mux_reg),\n .I1(\\byte_r_reg[1]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] ),\n .I3(wr_level_done_reg),\n .I4(oclkdelay_calib_done_r_reg_0),\n .I5(pi_stg2_rdlvl_cnt[1]),\n .O(\\gen_byte_sel_div1.byte_sel_cnt_reg[1] ));\n LUT6 #(\n .INIT(64'hAAAAAAAA00000008)) \n \\init_state_r[2]_i_19 \n (.I0(\\init_state_r_reg[0] ),\n .I1(\\init_state_r_reg[2]_0 [1]),\n .I2(prech_req_r_reg),\n .I3(prech_req_r_reg_0),\n .I4(prbs_rdlvl_done_reg),\n .I5(oclk_calib_resume_r_reg),\n .O(\\init_state_r_reg[2] ));\n LUT6 #(\n .INIT(64'h00000000EEEEEE0E)) \n \\init_state_r[5]_i_59 \n (.I0(wrlvl_final_mux_reg),\n .I1(prech_req_posedge_r_reg),\n .I2(cnt_cmd_done_r),\n .I3(prech_req_r_reg_0),\n .I4(prech_req_r_reg),\n .I5(\\init_state_r_reg[2]_0 [0]),\n .O(\\init_state_r_reg[5] ));\n LUT6 #(\n .INIT(64'hFFFF777788880300)) \n lim_start_r_i_1\n (.I0(lim_start_r_i_2_n_0),\n .I1(sm_r[1]),\n .I2(sm_r[0]),\n .I3(oclkdelay_calib_start_int_reg),\n .I4(sm_r[2]),\n .I5(lim_start),\n .O(lim_start_r_i_1_n_0));\n LUT5 #(\n .INIT(32'h00007F70)) \n lim_start_r_i_2\n (.I0(\\byte_r_reg[0]_0 ),\n .I1(\\byte_r_reg[1]_0 ),\n .I2(sm_r[2]),\n .I3(done_r_reg_0),\n .I4(sm_r[0]),\n .O(lim_start_r_i_2_n_0));\n FDRE #(\n .INIT(1'b0)) \n lim_start_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(lim_start_r_i_1_n_0),\n .Q(lim_start),\n .R(rstdiv0_sync_r1_reg_rep__10));\n (* SOFT_HLUTNM = \"soft_lutpair352\" *) \n LUT4 #(\n .INIT(16'hFF80)) \n ocal_last_byte_done_i_1\n (.I0(oclkdelay_center_calib_done_r_reg),\n .I1(\\byte_r_reg[0]_0 ),\n .I2(\\byte_r_reg[1]_0 ),\n .I3(ocal_last_byte_done),\n .O(ocal_last_byte_done_reg));\n LUT3 #(\n .INIT(8'h04)) \n ocd_prech_req_r_i_1\n (.I0(sm_r[0]),\n .I1(sm_r[2]),\n .I2(sm_r[1]),\n .O(ocd_prech_req_ns));\n FDRE #(\n .INIT(1'b0)) \n ocd_prech_req_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(ocd_prech_req_ns),\n .Q(prech_req_r_reg),\n .R(rstdiv0_sync_r1_reg_rep__9));\n LUT6 #(\n .INIT(64'hBFFFFFFF80000000)) \n oclkdelay_calib_done_r_i_1\n (.I0(wrlvl_final_r0),\n .I1(sm_r[2]),\n .I2(oclkdelay_calib_done_r_i_3_n_0),\n .I3(sm_r[0]),\n .I4(sm_r[1]),\n .I5(wrlvl_final_mux_reg),\n .O(oclkdelay_calib_done_r_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair351\" *) \n LUT5 #(\n .INIT(32'h00000002)) \n oclkdelay_calib_done_r_i_2\n (.I0(po_rdy),\n .I1(po_rd_wait_r_reg__0[0]),\n .I2(po_rd_wait_r_reg__0[1]),\n .I3(po_rd_wait_r_reg__0[2]),\n .I4(po_rd_wait_r_reg__0[3]),\n .O(wrlvl_final_r0));\n (* SOFT_HLUTNM = \"soft_lutpair350\" *) \n LUT5 #(\n .INIT(32'h04000000)) \n oclkdelay_calib_done_r_i_3\n (.I0(\\po_rd_wait_r[3]_i_6_n_0 ),\n .I1(po_rdy),\n .I2(\\po_counter_read_val_reg[2] ),\n .I3(\\byte_r_reg[1]_0 ),\n .I4(\\byte_r_reg[0]_0 ),\n .O(oclkdelay_calib_done_r_i_3_n_0));\n FDRE #(\n .INIT(1'b0)) \n oclkdelay_calib_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(oclkdelay_calib_done_r_i_1_n_0),\n .Q(wrlvl_final_mux_reg),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE #(\n .INIT(1'b0)) \n phy_rddata_en_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(phy_rddata_en),\n .Q(rd_active_r1_reg),\n .R(1'b0));\n LUT4 #(\n .INIT(16'h40EF)) \n \\po_rd_wait_r[0]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__25_0),\n .I1(\\po_rd_wait_r[0]_i_2_n_0 ),\n .I2(sm_r[1]),\n .I3(po_rd_wait_r_reg__0[0]),\n .O(po_rd_wait_ns[0]));\n LUT6 #(\n .INIT(64'h000000004777FFFF)) \n \\po_rd_wait_r[0]_i_2 \n (.I0(\\byte_r[0]_i_2_n_0 ),\n .I1(sm_r[0]),\n .I2(\\byte_r_reg[0]_0 ),\n .I3(\\byte_r_reg[1]_0 ),\n .I4(sm_r[2]),\n .I5(po_rd_wait_r_reg__0[0]),\n .O(\\po_rd_wait_r[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hEFFF40004000EFFF)) \n \\po_rd_wait_r[1]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__25_0),\n .I1(\\po_rd_wait_r[1]_i_2_n_0 ),\n .I2(sm_r[2]),\n .I3(sm_r[1]),\n .I4(po_rd_wait_r_reg__0[0]),\n .I5(po_rd_wait_r_reg__0[1]),\n .O(po_rd_wait_ns[1]));\n LUT6 #(\n .INIT(64'h4777000000004777)) \n \\po_rd_wait_r[1]_i_2 \n (.I0(\\byte_r[0]_i_2_n_0 ),\n .I1(sm_r[0]),\n .I2(\\byte_r_reg[0]_0 ),\n .I3(\\byte_r_reg[1]_0 ),\n .I4(po_rd_wait_r_reg__0[0]),\n .I5(po_rd_wait_r_reg__0[1]),\n .O(\\po_rd_wait_r[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hEF40EF40EF4040EF)) \n \\po_rd_wait_r[2]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__25_0),\n .I1(\\po_rd_wait_r[2]_i_2_n_0 ),\n .I2(sm_r[1]),\n .I3(po_rd_wait_r_reg__0[2]),\n .I4(po_rd_wait_r_reg__0[0]),\n .I5(po_rd_wait_r_reg__0[1]),\n .O(po_rd_wait_ns[2]));\n LUT6 #(\n .INIT(64'h4777FFFF00000000)) \n \\po_rd_wait_r[2]_i_2 \n (.I0(\\byte_r[0]_i_2_n_0 ),\n .I1(sm_r[0]),\n .I2(\\byte_r_reg[0]_0 ),\n .I3(\\byte_r_reg[1]_0 ),\n .I4(sm_r[2]),\n .I5(\\po_rd_wait_r[2]_i_3_n_0 ),\n .O(\\po_rd_wait_r[2]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair353\" *) \n LUT3 #(\n .INIT(8'hA9)) \n \\po_rd_wait_r[2]_i_3 \n (.I0(po_rd_wait_r_reg__0[2]),\n .I1(po_rd_wait_r_reg__0[0]),\n .I2(po_rd_wait_r_reg__0[1]),\n .O(\\po_rd_wait_r[2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFEFFFFFFFE0000)) \n \\po_rd_wait_r[3]_i_1 \n (.I0(po_rd_wait_r_reg__0[3]),\n .I1(po_rd_wait_r_reg__0[2]),\n .I2(po_rd_wait_r_reg__0[1]),\n .I3(po_rd_wait_r_reg__0[0]),\n .I4(rstdiv0_sync_r1_reg_rep__25_0),\n .I5(\\po_rd_wait_r[3]_i_3_n_0 ),\n .O(\\po_rd_wait_r[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF01000000)) \n \\po_rd_wait_r[3]_i_2 \n (.I0(rstdiv0_sync_r1_reg_rep__25_0),\n .I1(sm_r[0]),\n .I2(\\po_rd_wait_r[3]_i_4_n_0 ),\n .I3(sm_r[2]),\n .I4(sm_r[1]),\n .I5(\\po_rd_wait_r[3]_i_5_n_0 ),\n .O(po_rd_wait_ns[3]));\n LUT6 #(\n .INIT(64'hFFFFFFFF8B000000)) \n \\po_rd_wait_r[3]_i_3 \n (.I0(\\byte_r[0]_i_2_n_0 ),\n .I1(sm_r[0]),\n .I2(\\po_rd_wait_r[3]_i_4_n_0 ),\n .I3(sm_r[2]),\n .I4(sm_r[1]),\n .I5(\\po_rd_wait_r[3]_i_6_n_0 ),\n .O(\\po_rd_wait_r[3]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair358\" *) \n LUT2 #(\n .INIT(4'h7)) \n \\po_rd_wait_r[3]_i_4 \n (.I0(\\byte_r_reg[1]_0 ),\n .I1(\\byte_r_reg[0]_0 ),\n .O(\\po_rd_wait_r[3]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair353\" *) \n LUT4 #(\n .INIT(16'hAAA9)) \n \\po_rd_wait_r[3]_i_5 \n (.I0(po_rd_wait_r_reg__0[3]),\n .I1(po_rd_wait_r_reg__0[2]),\n .I2(po_rd_wait_r_reg__0[1]),\n .I3(po_rd_wait_r_reg__0[0]),\n .O(\\po_rd_wait_r[3]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair351\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n \\po_rd_wait_r[3]_i_6 \n (.I0(po_rd_wait_r_reg__0[3]),\n .I1(po_rd_wait_r_reg__0[2]),\n .I2(po_rd_wait_r_reg__0[1]),\n .I3(po_rd_wait_r_reg__0[0]),\n .O(\\po_rd_wait_r[3]_i_6_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\po_rd_wait_r_reg[0] \n (.C(CLK),\n .CE(\\po_rd_wait_r[3]_i_1_n_0 ),\n .D(po_rd_wait_ns[0]),\n .Q(po_rd_wait_r_reg__0[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\po_rd_wait_r_reg[1] \n (.C(CLK),\n .CE(\\po_rd_wait_r[3]_i_1_n_0 ),\n .D(po_rd_wait_ns[1]),\n .Q(po_rd_wait_r_reg__0[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\po_rd_wait_r_reg[2] \n (.C(CLK),\n .CE(\\po_rd_wait_r[3]_i_1_n_0 ),\n .D(po_rd_wait_ns[2]),\n .Q(po_rd_wait_r_reg__0[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\po_rd_wait_r_reg[3] \n (.C(CLK),\n .CE(\\po_rd_wait_r[3]_i_1_n_0 ),\n .D(po_rd_wait_ns[3]),\n .Q(po_rd_wait_r_reg__0[3]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0080000000000000)) \n po_rdy_r_i_8\n (.I0(sm_r[2]),\n .I1(\\po_counter_read_val_reg[2] ),\n .I2(po_rdy),\n .I3(\\po_rd_wait_r[3]_i_6_n_0 ),\n .I4(sm_r[0]),\n .I5(sm_r[1]),\n .O(ocd_cntlr2stg2_dec_r));\n LUT2 #(\n .INIT(4'hE)) \n prech_req_r_i_2__0\n (.I0(prech_req_r_reg),\n .I1(prech_req_r_reg_0),\n .O(complex_ocal_ref_req));\n (* SOFT_HLUTNM = \"soft_lutpair355\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\rd_victim_sel_r[2]_i_2 \n (.I0(rstdiv0_sync_r1_reg_rep__24),\n .I1(rd_active_r1_reg),\n .I2(\\data_cnt_r_reg[7] ),\n .O(\\rd_victim_sel_r_reg[0] ));\n LUT6 #(\n .INIT(64'hFAFFFFFF40400000)) \n reset_scan_r_i_1\n (.I0(sm_r[2]),\n .I1(rstdiv0_sync_r1_reg_rep__25),\n .I2(sm_r[0]),\n .I3(done_r_reg_0),\n .I4(sm_r[1]),\n .I5(reset_scan),\n .O(reset_scan_r_i_1_n_0));\n FDSE #(\n .INIT(1'b1)) \n reset_scan_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(reset_scan_r_i_1_n_0),\n .Q(reset_scan),\n .S(rstdiv0_sync_r1_reg_rep__9));\n (* SOFT_HLUTNM = \"soft_lutpair357\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\simp_stg3_final_r[11]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__25),\n .I1(\\byte_r_reg[0]_0 ),\n .I2(\\byte_r_reg[1]_0 ),\n .O(\\simp_stg3_final_r_reg[11] ));\n (* SOFT_HLUTNM = \"soft_lutpair357\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\simp_stg3_final_r[17]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__25),\n .I1(\\byte_r_reg[1]_0 ),\n .I2(\\byte_r_reg[0]_0 ),\n .O(\\simp_stg3_final_r_reg[17] ));\n (* SOFT_HLUTNM = \"soft_lutpair352\" *) \n LUT3 #(\n .INIT(8'h80)) \n \\simp_stg3_final_r[23]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__25),\n .I1(\\byte_r_reg[0]_0 ),\n .I2(\\byte_r_reg[1]_0 ),\n .O(\\simp_stg3_final_r_reg[23] ));\n (* SOFT_HLUTNM = \"soft_lutpair358\" *) \n LUT3 #(\n .INIT(8'h02)) \n \\simp_stg3_final_r[5]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__25),\n .I1(\\byte_r_reg[0]_0 ),\n .I2(\\byte_r_reg[1]_0 ),\n .O(\\simp_stg3_final_r_reg[5] ));\n LUT4 #(\n .INIT(16'h0020)) \n sr_valid_r_i_1\n (.I0(rd_active_r1_reg),\n .I1(rstdiv0_sync_r1_reg_rep__20),\n .I2(rdlvl_stg1_start_reg),\n .I3(\\cnt_shift_r_reg[0] ),\n .O(sr_valid_r108_out));\n (* SOFT_HLUTNM = \"soft_lutpair356\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\stg3_init_val[0]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__25_0),\n .I1(wrlvl_final_mux_reg),\n .I2(\\simp_stg3_final_r_reg[12] ),\n .O(D[0]));\n (* SOFT_HLUTNM = \"soft_lutpair354\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\stg3_init_val[1]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__25_0),\n .I1(wrlvl_final_mux_reg),\n .I2(\\simp_stg3_final_r_reg[19] ),\n .O(D[1]));\n LUT6 #(\n .INIT(64'hFFFFFFFFDDDDDDFD)) \n \\stg3_init_val[2]_i_1 \n (.I0(wrlvl_final_mux_reg),\n .I1(rstdiv0_sync_r1_reg_rep__25_0),\n .I2(\\simp_stg3_final_r_reg[2] ),\n .I3(\\byte_r_reg[0]_0 ),\n .I4(\\byte_r_reg[1]_0 ),\n .I5(\\simp_stg3_final_r_reg[8] ),\n .O(D[2]));\n (* SOFT_HLUTNM = \"soft_lutpair355\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\stg3_init_val[3]_i_3 \n (.I0(wrlvl_final_mux_reg),\n .I1(rstdiv0_sync_r1_reg_rep__24),\n .O(\\stg3_init_val_reg[3] ));\n LUT6 #(\n .INIT(64'hFFFFFFFFDDDDFDDD)) \n \\stg3_init_val[4]_i_1 \n (.I0(wrlvl_final_mux_reg),\n .I1(rstdiv0_sync_r1_reg_rep__25_0),\n .I2(\\simp_stg3_final_r_reg[16] ),\n .I3(\\byte_r_reg[1]_0 ),\n .I4(\\byte_r_reg[0]_0 ),\n .I5(\\simp_stg3_final_r_reg[10] ),\n .O(D[3]));\n (* SOFT_HLUTNM = \"soft_lutpair354\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\stg3_init_val[5]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__25_0),\n .I1(wrlvl_final_mux_reg),\n .I2(\\simp_stg3_final_r_reg[17]_0 ),\n .O(D[4]));\n (* SOFT_HLUTNM = \"soft_lutpair356\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[158]_i_1 \n (.I0(wrlvl_final_mux_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_phy_ocd_data\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_phy_ocd_data\n (E,\n \\zero_r_reg[9] ,\n \\zero_r_reg[9]_0 ,\n \\rd_victim_sel_r_reg[0] ,\n agg_samp_r,\n \\byte_r_reg[0] ,\n CLK);\n output [0:0]E;\n output \\zero_r_reg[9] ;\n output \\zero_r_reg[9]_0 ;\n input \\rd_victim_sel_r_reg[0] ;\n input [1:0]agg_samp_r;\n input [63:0]\\byte_r_reg[0] ;\n input CLK;\n\n wire CLK;\n wire [0:0]E;\n wire [1:0]agg_samp_r;\n wire [63:0]\\byte_r_reg[0] ;\n wire [63:0]data_bytes_r;\n wire \\rd_victim_sel_r_reg[0] ;\n wire \\zero_r[9]_i_10_n_0 ;\n wire \\zero_r[9]_i_11_n_0 ;\n wire \\zero_r[9]_i_12_n_0 ;\n wire \\zero_r[9]_i_13_n_0 ;\n wire \\zero_r[9]_i_14_n_0 ;\n wire \\zero_r[9]_i_15_n_0 ;\n wire \\zero_r[9]_i_16_n_0 ;\n wire \\zero_r[9]_i_17_n_0 ;\n wire \\zero_r[9]_i_18_n_0 ;\n wire \\zero_r[9]_i_19_n_0 ;\n wire \\zero_r[9]_i_20_n_0 ;\n wire \\zero_r[9]_i_21_n_0 ;\n wire \\zero_r[9]_i_22_n_0 ;\n wire \\zero_r[9]_i_23_n_0 ;\n wire \\zero_r[9]_i_24_n_0 ;\n wire \\zero_r[9]_i_25_n_0 ;\n wire \\zero_r[9]_i_26_n_0 ;\n wire \\zero_r[9]_i_27_n_0 ;\n wire \\zero_r[9]_i_28_n_0 ;\n wire \\zero_r[9]_i_29_n_0 ;\n wire \\zero_r[9]_i_30_n_0 ;\n wire \\zero_r[9]_i_31_n_0 ;\n wire \\zero_r[9]_i_32_n_0 ;\n wire \\zero_r[9]_i_33_n_0 ;\n wire \\zero_r[9]_i_34_n_0 ;\n wire \\zero_r[9]_i_35_n_0 ;\n wire \\zero_r[9]_i_36_n_0 ;\n wire \\zero_r[9]_i_37_n_0 ;\n wire \\zero_r[9]_i_38_n_0 ;\n wire \\zero_r[9]_i_39_n_0 ;\n wire \\zero_r[9]_i_40_n_0 ;\n wire \\zero_r[9]_i_9_n_0 ;\n wire \\zero_r_reg[9] ;\n wire \\zero_r_reg[9]_0 ;\n\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [0]),\n .Q(data_bytes_r[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [10]),\n .Q(data_bytes_r[10]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [11]),\n .Q(data_bytes_r[11]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[12] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [12]),\n .Q(data_bytes_r[12]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[13] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [13]),\n .Q(data_bytes_r[13]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[14] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [14]),\n .Q(data_bytes_r[14]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[15] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [15]),\n .Q(data_bytes_r[15]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[16] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [16]),\n .Q(data_bytes_r[16]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[17] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [17]),\n .Q(data_bytes_r[17]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[18] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [18]),\n .Q(data_bytes_r[18]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[19] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [19]),\n .Q(data_bytes_r[19]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [1]),\n .Q(data_bytes_r[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[20] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [20]),\n .Q(data_bytes_r[20]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[21] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [21]),\n .Q(data_bytes_r[21]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[22] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [22]),\n .Q(data_bytes_r[22]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[23] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [23]),\n .Q(data_bytes_r[23]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[24] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [24]),\n .Q(data_bytes_r[24]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[25] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [25]),\n .Q(data_bytes_r[25]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[26] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [26]),\n .Q(data_bytes_r[26]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[27] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [27]),\n .Q(data_bytes_r[27]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[28] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [28]),\n .Q(data_bytes_r[28]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[29] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [29]),\n .Q(data_bytes_r[29]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [2]),\n .Q(data_bytes_r[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[30] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [30]),\n .Q(data_bytes_r[30]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[31] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [31]),\n .Q(data_bytes_r[31]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[32] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [32]),\n .Q(data_bytes_r[32]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[33] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [33]),\n .Q(data_bytes_r[33]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[34] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [34]),\n .Q(data_bytes_r[34]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[35] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [35]),\n .Q(data_bytes_r[35]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[36] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [36]),\n .Q(data_bytes_r[36]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[37] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [37]),\n .Q(data_bytes_r[37]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[38] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [38]),\n .Q(data_bytes_r[38]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[39] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [39]),\n .Q(data_bytes_r[39]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [3]),\n .Q(data_bytes_r[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[40] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [40]),\n .Q(data_bytes_r[40]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[41] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [41]),\n .Q(data_bytes_r[41]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[42] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [42]),\n .Q(data_bytes_r[42]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[43] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [43]),\n .Q(data_bytes_r[43]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[44] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [44]),\n .Q(data_bytes_r[44]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[45] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [45]),\n .Q(data_bytes_r[45]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[46] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [46]),\n .Q(data_bytes_r[46]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[47] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [47]),\n .Q(data_bytes_r[47]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[48] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [48]),\n .Q(data_bytes_r[48]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[49] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [49]),\n .Q(data_bytes_r[49]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [4]),\n .Q(data_bytes_r[4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[50] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [50]),\n .Q(data_bytes_r[50]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[51] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [51]),\n .Q(data_bytes_r[51]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[52] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [52]),\n .Q(data_bytes_r[52]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[53] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [53]),\n .Q(data_bytes_r[53]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[54] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [54]),\n .Q(data_bytes_r[54]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[55] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [55]),\n .Q(data_bytes_r[55]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[56] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [56]),\n .Q(data_bytes_r[56]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[57] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [57]),\n .Q(data_bytes_r[57]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[58] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [58]),\n .Q(data_bytes_r[58]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[59] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [59]),\n .Q(data_bytes_r[59]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [5]),\n .Q(data_bytes_r[5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[60] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [60]),\n .Q(data_bytes_r[60]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[61] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [61]),\n .Q(data_bytes_r[61]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[62] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [62]),\n .Q(data_bytes_r[62]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[63] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [63]),\n .Q(data_bytes_r[63]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [6]),\n .Q(data_bytes_r[6]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [7]),\n .Q(data_bytes_r[7]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [8]),\n .Q(data_bytes_r[8]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_bytes_r_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [9]),\n .Q(data_bytes_r[9]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0000010000000000)) \n \\zero_r[9]_i_10 \n (.I0(data_bytes_r[53]),\n .I1(data_bytes_r[52]),\n .I2(data_bytes_r[48]),\n .I3(data_bytes_r[58]),\n .I4(data_bytes_r[1]),\n .I5(data_bytes_r[59]),\n .O(\\zero_r[9]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFBFF)) \n \\zero_r[9]_i_11 \n (.I0(\\zero_r[9]_i_21_n_0 ),\n .I1(data_bytes_r[56]),\n .I2(data_bytes_r[38]),\n .I3(data_bytes_r[42]),\n .I4(data_bytes_r[35]),\n .I5(\\zero_r[9]_i_22_n_0 ),\n .O(\\zero_r[9]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFEFF)) \n \\zero_r[9]_i_12 \n (.I0(\\zero_r[9]_i_23_n_0 ),\n .I1(data_bytes_r[2]),\n .I2(data_bytes_r[3]),\n .I3(data_bytes_r[30]),\n .I4(data_bytes_r[39]),\n .I5(\\zero_r[9]_i_24_n_0 ),\n .O(\\zero_r[9]_i_12_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFFF7F)) \n \\zero_r[9]_i_13 \n (.I0(data_bytes_r[25]),\n .I1(data_bytes_r[9]),\n .I2(data_bytes_r[12]),\n .I3(\\zero_r[9]_i_25_n_0 ),\n .I4(\\zero_r[9]_i_26_n_0 ),\n .O(\\zero_r[9]_i_13_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFBFFFFFF)) \n \\zero_r[9]_i_14 \n (.I0(\\zero_r[9]_i_27_n_0 ),\n .I1(data_bytes_r[32]),\n .I2(data_bytes_r[29]),\n .I3(data_bytes_r[21]),\n .I4(data_bytes_r[19]),\n .I5(\\zero_r[9]_i_28_n_0 ),\n .O(\\zero_r[9]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'h0001000000000000)) \n \\zero_r[9]_i_15 \n (.I0(data_bytes_r[14]),\n .I1(data_bytes_r[30]),\n .I2(data_bytes_r[31]),\n .I3(data_bytes_r[46]),\n .I4(data_bytes_r[48]),\n .I5(data_bytes_r[54]),\n .O(\\zero_r[9]_i_15_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFBFF)) \n \\zero_r[9]_i_16 \n (.I0(\\zero_r[9]_i_29_n_0 ),\n .I1(data_bytes_r[49]),\n .I2(data_bytes_r[63]),\n .I3(data_bytes_r[22]),\n .I4(data_bytes_r[43]),\n .I5(\\zero_r[9]_i_30_n_0 ),\n .O(\\zero_r[9]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFBFFFFFF)) \n \\zero_r[9]_i_17 \n (.I0(\\zero_r[9]_i_31_n_0 ),\n .I1(data_bytes_r[53]),\n .I2(data_bytes_r[11]),\n .I3(data_bytes_r[7]),\n .I4(data_bytes_r[18]),\n .I5(\\zero_r[9]_i_32_n_0 ),\n .O(\\zero_r[9]_i_17_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFFFDF)) \n \\zero_r[9]_i_18 \n (.I0(data_bytes_r[36]),\n .I1(data_bytes_r[24]),\n .I2(data_bytes_r[4]),\n .I3(\\zero_r[9]_i_33_n_0 ),\n .I4(\\zero_r[9]_i_34_n_0 ),\n .O(\\zero_r[9]_i_18_n_0 ));\n LUT4 #(\n .INIT(16'hFFFD)) \n \\zero_r[9]_i_19 \n (.I0(data_bytes_r[43]),\n .I1(data_bytes_r[6]),\n .I2(data_bytes_r[54]),\n .I3(data_bytes_r[37]),\n .O(\\zero_r[9]_i_19_n_0 ));\n LUT3 #(\n .INIT(8'h08)) \n \\zero_r[9]_i_2 \n (.I0(\\zero_r_reg[9] ),\n .I1(\\rd_victim_sel_r_reg[0] ),\n .I2(\\zero_r_reg[9]_0 ),\n .O(E));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\zero_r[9]_i_20 \n (.I0(data_bytes_r[40]),\n .I1(data_bytes_r[29]),\n .I2(data_bytes_r[27]),\n .I3(data_bytes_r[60]),\n .I4(\\zero_r[9]_i_35_n_0 ),\n .O(\\zero_r[9]_i_20_n_0 ));\n LUT4 #(\n .INIT(16'hFFDF)) \n \\zero_r[9]_i_21 \n (.I0(data_bytes_r[44]),\n .I1(data_bytes_r[20]),\n .I2(agg_samp_r[0]),\n .I3(data_bytes_r[55]),\n .O(\\zero_r[9]_i_21_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFFFFB)) \n \\zero_r[9]_i_22 \n (.I0(data_bytes_r[19]),\n .I1(data_bytes_r[63]),\n .I2(data_bytes_r[5]),\n .I3(data_bytes_r[4]),\n .I4(\\zero_r[9]_i_36_n_0 ),\n .O(\\zero_r[9]_i_22_n_0 ));\n LUT4 #(\n .INIT(16'hFFF7)) \n \\zero_r[9]_i_23 \n (.I0(data_bytes_r[61]),\n .I1(data_bytes_r[31]),\n .I2(data_bytes_r[32]),\n .I3(data_bytes_r[23]),\n .O(\\zero_r[9]_i_23_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFBFFF)) \n \\zero_r[9]_i_24 \n (.I0(data_bytes_r[34]),\n .I1(data_bytes_r[41]),\n .I2(data_bytes_r[45]),\n .I3(data_bytes_r[14]),\n .I4(\\zero_r[9]_i_37_n_0 ),\n .O(\\zero_r[9]_i_24_n_0 ));\n LUT4 #(\n .INIT(16'hFFDF)) \n \\zero_r[9]_i_25 \n (.I0(data_bytes_r[57]),\n .I1(data_bytes_r[16]),\n .I2(data_bytes_r[26]),\n .I3(data_bytes_r[17]),\n .O(\\zero_r[9]_i_25_n_0 ));\n LUT4 #(\n .INIT(16'hEFFF)) \n \\zero_r[9]_i_26 \n (.I0(data_bytes_r[22]),\n .I1(data_bytes_r[51]),\n .I2(data_bytes_r[13]),\n .I3(data_bytes_r[28]),\n .O(\\zero_r[9]_i_26_n_0 ));\n LUT4 #(\n .INIT(16'hFFFD)) \n \\zero_r[9]_i_27 \n (.I0(data_bytes_r[6]),\n .I1(data_bytes_r[9]),\n .I2(data_bytes_r[12]),\n .I3(data_bytes_r[60]),\n .O(\\zero_r[9]_i_27_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFBFFF)) \n \\zero_r[9]_i_28 \n (.I0(data_bytes_r[47]),\n .I1(data_bytes_r[51]),\n .I2(data_bytes_r[55]),\n .I3(data_bytes_r[34]),\n .I4(\\zero_r[9]_i_38_n_0 ),\n .O(\\zero_r[9]_i_28_n_0 ));\n LUT4 #(\n .INIT(16'hFFFD)) \n \\zero_r[9]_i_29 \n (.I0(data_bytes_r[39]),\n .I1(data_bytes_r[13]),\n .I2(data_bytes_r[26]),\n .I3(data_bytes_r[57]),\n .O(\\zero_r[9]_i_29_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFF7FF)) \n \\zero_r[9]_i_30 \n (.I0(data_bytes_r[0]),\n .I1(data_bytes_r[5]),\n .I2(data_bytes_r[59]),\n .I3(agg_samp_r[1]),\n .I4(\\zero_r[9]_i_39_n_0 ),\n .O(\\zero_r[9]_i_30_n_0 ));\n LUT4 #(\n .INIT(16'hEFFF)) \n \\zero_r[9]_i_31 \n (.I0(data_bytes_r[25]),\n .I1(data_bytes_r[10]),\n .I2(data_bytes_r[20]),\n .I3(data_bytes_r[33]),\n .O(\\zero_r[9]_i_31_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFFEFF)) \n \\zero_r[9]_i_32 \n (.I0(data_bytes_r[27]),\n .I1(data_bytes_r[56]),\n .I2(data_bytes_r[8]),\n .I3(data_bytes_r[17]),\n .I4(\\zero_r[9]_i_40_n_0 ),\n .O(\\zero_r[9]_i_32_n_0 ));\n LUT4 #(\n .INIT(16'hFFF7)) \n \\zero_r[9]_i_33 \n (.I0(data_bytes_r[23]),\n .I1(data_bytes_r[50]),\n .I2(data_bytes_r[41]),\n .I3(data_bytes_r[44]),\n .O(\\zero_r[9]_i_33_n_0 ));\n LUT4 #(\n .INIT(16'hFF7F)) \n \\zero_r[9]_i_34 \n (.I0(data_bytes_r[16]),\n .I1(data_bytes_r[35]),\n .I2(data_bytes_r[38]),\n .I3(data_bytes_r[62]),\n .O(\\zero_r[9]_i_34_n_0 ));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\zero_r[9]_i_35 \n (.I0(data_bytes_r[49]),\n .I1(data_bytes_r[33]),\n .I2(data_bytes_r[18]),\n .I3(data_bytes_r[36]),\n .O(\\zero_r[9]_i_35_n_0 ));\n LUT4 #(\n .INIT(16'hFFDF)) \n \\zero_r[9]_i_36 \n (.I0(data_bytes_r[10]),\n .I1(data_bytes_r[7]),\n .I2(data_bytes_r[8]),\n .I3(data_bytes_r[21]),\n .O(\\zero_r[9]_i_36_n_0 ));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\zero_r[9]_i_37 \n (.I0(data_bytes_r[15]),\n .I1(data_bytes_r[47]),\n .I2(data_bytes_r[46]),\n .I3(data_bytes_r[11]),\n .O(\\zero_r[9]_i_37_n_0 ));\n LUT4 #(\n .INIT(16'hFFFD)) \n \\zero_r[9]_i_38 \n (.I0(data_bytes_r[52]),\n .I1(data_bytes_r[61]),\n .I2(data_bytes_r[15]),\n .I3(data_bytes_r[45]),\n .O(\\zero_r[9]_i_38_n_0 ));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\zero_r[9]_i_39 \n (.I0(data_bytes_r[42]),\n .I1(data_bytes_r[28]),\n .I2(data_bytes_r[40]),\n .I3(data_bytes_r[58]),\n .O(\\zero_r[9]_i_39_n_0 ));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\zero_r[9]_i_40 \n (.I0(data_bytes_r[2]),\n .I1(data_bytes_r[3]),\n .I2(data_bytes_r[1]),\n .I3(data_bytes_r[37]),\n .O(\\zero_r[9]_i_40_n_0 ));\n LUT5 #(\n .INIT(32'h00000004)) \n \\zero_r[9]_i_5 \n (.I0(\\zero_r[9]_i_9_n_0 ),\n .I1(\\zero_r[9]_i_10_n_0 ),\n .I2(\\zero_r[9]_i_11_n_0 ),\n .I3(\\zero_r[9]_i_12_n_0 ),\n .I4(\\zero_r[9]_i_13_n_0 ),\n .O(\\zero_r_reg[9] ));\n LUT5 #(\n .INIT(32'h00000004)) \n \\zero_r[9]_i_7 \n (.I0(\\zero_r[9]_i_14_n_0 ),\n .I1(\\zero_r[9]_i_15_n_0 ),\n .I2(\\zero_r[9]_i_16_n_0 ),\n .I3(\\zero_r[9]_i_17_n_0 ),\n .I4(\\zero_r[9]_i_18_n_0 ),\n .O(\\zero_r_reg[9]_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFBFF)) \n \\zero_r[9]_i_9 \n (.I0(\\zero_r[9]_i_19_n_0 ),\n .I1(data_bytes_r[24]),\n .I2(data_bytes_r[50]),\n .I3(data_bytes_r[62]),\n .I4(data_bytes_r[0]),\n .I5(\\zero_r[9]_i_20_n_0 ),\n .O(\\zero_r[9]_i_9_n_0 ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_phy_ocd_edge\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_phy_ocd_edge\n (prev_samp_valid_r,\n o2f_r_reg_0,\n \\ninety_offsets_final_r_reg[0] ,\n f2o_r_reg_0,\n scan_right,\n prev_samp_r,\n \\ninety_offsets_final_r_reg[1] ,\n dec_po_ns,\n inc_po_ns,\n \\ninety_offsets_final_r_reg[0]_0 ,\n reset_scan,\n samp_done_r_reg,\n CLK,\n scanning_right_r_reg,\n scanning_right_r_reg_0,\n \\samp_result_r_reg[1] ,\n \\samp_result_r_reg[0] ,\n rd_active_r1_reg,\n rd_active_r1_reg_0,\n scanning_right,\n ocd_ktap_left_r_reg,\n Q,\n \\stg3_left_lim_reg[5] ,\n rd_active_r1,\n samp_done,\n \\stg3_right_lim_reg[5] ,\n E,\n D,\n reset_scan_r_reg);\n output prev_samp_valid_r;\n output o2f_r_reg_0;\n output \\ninety_offsets_final_r_reg[0] ;\n output f2o_r_reg_0;\n output scan_right;\n output [1:0]prev_samp_r;\n output \\ninety_offsets_final_r_reg[1] ;\n output dec_po_ns;\n output inc_po_ns;\n output \\ninety_offsets_final_r_reg[0]_0 ;\n input reset_scan;\n input samp_done_r_reg;\n input CLK;\n input scanning_right_r_reg;\n input scanning_right_r_reg_0;\n input \\samp_result_r_reg[1] ;\n input \\samp_result_r_reg[0] ;\n input rd_active_r1_reg;\n input rd_active_r1_reg_0;\n input scanning_right;\n input ocd_ktap_left_r_reg;\n input [5:0]Q;\n input [5:0]\\stg3_left_lim_reg[5] ;\n input rd_active_r1;\n input samp_done;\n input [5:0]\\stg3_right_lim_reg[5] ;\n input [0:0]E;\n input [5:0]D;\n input [0:0]reset_scan_r_reg;\n\n wire CLK;\n wire [5:0]D;\n wire [0:0]E;\n wire [5:0]Q;\n wire dec_po_ns;\n wire dec_po_r_i_10_n_0;\n wire dec_po_r_i_11_n_0;\n wire dec_po_r_i_12_n_0;\n wire dec_po_r_i_13_n_0;\n wire dec_po_r_i_14_n_0;\n wire dec_po_r_i_15_n_0;\n wire dec_po_r_i_16_n_0;\n wire dec_po_r_i_17_n_0;\n wire dec_po_r_i_18_n_0;\n wire dec_po_r_i_20_n_0;\n wire dec_po_r_i_21_n_0;\n wire dec_po_r_i_22_n_0;\n wire dec_po_r_i_23_n_0;\n wire dec_po_r_i_24_n_0;\n wire dec_po_r_i_26_n_0;\n wire dec_po_r_i_27_n_0;\n wire dec_po_r_i_28_n_0;\n wire dec_po_r_i_29_n_0;\n wire dec_po_r_i_2_n_0;\n wire dec_po_r_i_30_n_0;\n wire dec_po_r_i_31_n_0;\n wire dec_po_r_i_32_n_0;\n wire dec_po_r_i_3_n_0;\n wire dec_po_r_i_4_n_0;\n wire dec_po_r_i_5_n_0;\n wire dec_po_r_i_6_n_0;\n wire dec_po_r_i_7_n_0;\n wire dec_po_r_i_9_n_0;\n wire dec_po_r_reg_i_19_n_0;\n wire dec_po_r_reg_i_8_n_0;\n wire f2o_r_i_1_n_0;\n wire f2o_r_reg_0;\n wire \\fuzz2oneeighty_r[5]_i_1_n_0 ;\n wire \\fuzz2oneeighty_r[5]_i_2_n_0 ;\n wire \\fuzz2oneeighty_r_reg_n_0_[0] ;\n wire \\fuzz2oneeighty_r_reg_n_0_[1] ;\n wire \\fuzz2oneeighty_r_reg_n_0_[2] ;\n wire \\fuzz2oneeighty_r_reg_n_0_[3] ;\n wire \\fuzz2oneeighty_r_reg_n_0_[4] ;\n wire \\fuzz2oneeighty_r_reg_n_0_[5] ;\n wire \\fuzz2zero_r_reg_n_0_[0] ;\n wire \\fuzz2zero_r_reg_n_0_[1] ;\n wire \\fuzz2zero_r_reg_n_0_[2] ;\n wire \\fuzz2zero_r_reg_n_0_[3] ;\n wire \\fuzz2zero_r_reg_n_0_[4] ;\n wire \\fuzz2zero_r_reg_n_0_[5] ;\n wire inc_po_ns;\n wire inc_po_r_i_2_n_0;\n wire inc_po_r_i_3_n_0;\n wire inc_po_r_i_4_n_0;\n wire \\ninety_offsets_final_r_reg[0] ;\n wire \\ninety_offsets_final_r_reg[0]_0 ;\n wire \\ninety_offsets_final_r_reg[1] ;\n wire o2f_r_reg_0;\n wire ocd_ktap_left_r_reg;\n wire \\oneeighty2fuzz_r_reg_n_0_[0] ;\n wire \\oneeighty2fuzz_r_reg_n_0_[1] ;\n wire \\oneeighty2fuzz_r_reg_n_0_[2] ;\n wire \\oneeighty2fuzz_r_reg_n_0_[3] ;\n wire \\oneeighty2fuzz_r_reg_n_0_[4] ;\n wire \\oneeighty2fuzz_r_reg_n_0_[5] ;\n wire [1:0]prev_samp_r;\n wire prev_samp_valid_r;\n wire rd_active_r1;\n wire rd_active_r1_reg;\n wire rd_active_r1_reg_0;\n wire reset_scan;\n wire [0:0]reset_scan_r_reg;\n wire samp_done;\n wire samp_done_r_reg;\n wire \\samp_result_r_reg[0] ;\n wire \\samp_result_r_reg[1] ;\n wire scan_right;\n wire scan_right_r_i_1_n_0;\n wire scanning_right;\n wire scanning_right_r_reg;\n wire scanning_right_r_reg_0;\n wire [5:0]\\stg3_left_lim_reg[5] ;\n wire [5:0]\\stg3_right_lim_reg[5] ;\n wire \\u_ocd_po_cntlr/noise ;\n wire z2f_r_i_1_n_0;\n wire z2f_r_reg_n_0;\n wire zero2fuzz_ns;\n wire \\zero2fuzz_r_reg_n_0_[0] ;\n wire \\zero2fuzz_r_reg_n_0_[1] ;\n wire \\zero2fuzz_r_reg_n_0_[2] ;\n wire \\zero2fuzz_r_reg_n_0_[3] ;\n wire \\zero2fuzz_r_reg_n_0_[4] ;\n wire \\zero2fuzz_r_reg_n_0_[5] ;\n\n LUT6 #(\n .INIT(64'hFEE00000FFFFFEE0)) \n dec_po_r_i_1\n (.I0(dec_po_r_i_2_n_0),\n .I1(dec_po_r_i_3_n_0),\n .I2(dec_po_r_i_4_n_0),\n .I3(Q[4]),\n .I4(Q[5]),\n .I5(dec_po_r_i_5_n_0),\n .O(dec_po_ns));\n (* SOFT_HLUTNM = \"soft_lutpair361\" *) \n LUT3 #(\n .INIT(8'h8A)) \n dec_po_r_i_10\n (.I0(\\ninety_offsets_final_r_reg[0] ),\n .I1(z2f_r_reg_n_0),\n .I2(f2o_r_reg_0),\n .O(dec_po_r_i_10_n_0));\n LUT5 #(\n .INIT(32'hBF8CB380)) \n dec_po_r_i_11\n (.I0(\\zero2fuzz_r_reg_n_0_[3] ),\n .I1(f2o_r_reg_0),\n .I2(z2f_r_reg_n_0),\n .I3(\\stg3_left_lim_reg[5] [3]),\n .I4(\\fuzz2oneeighty_r_reg_n_0_[3] ),\n .O(dec_po_r_i_11_n_0));\n LUT5 #(\n .INIT(32'hBF8CB380)) \n dec_po_r_i_12\n (.I0(\\zero2fuzz_r_reg_n_0_[4] ),\n .I1(f2o_r_reg_0),\n .I2(z2f_r_reg_n_0),\n .I3(\\stg3_left_lim_reg[5] [4]),\n .I4(\\fuzz2oneeighty_r_reg_n_0_[4] ),\n .O(dec_po_r_i_12_n_0));\n LUT6 #(\n .INIT(64'h1010001015155515)) \n dec_po_r_i_13\n (.I0(ocd_ktap_left_r_reg),\n .I1(\\zero2fuzz_r_reg_n_0_[4] ),\n .I2(z2f_r_reg_n_0),\n .I3(f2o_r_reg_0),\n .I4(\\ninety_offsets_final_r_reg[0] ),\n .I5(dec_po_r_i_23_n_0),\n .O(dec_po_r_i_13_n_0));\n LUT6 #(\n .INIT(64'h0000FF00AE00AE00)) \n dec_po_r_i_14\n (.I0(dec_po_r_i_24_n_0),\n .I1(\\u_ocd_po_cntlr/noise ),\n .I2(\\zero2fuzz_r_reg_n_0_[5] ),\n .I3(ocd_ktap_left_r_reg),\n .I4(\\fuzz2zero_r_reg_n_0_[5] ),\n .I5(dec_po_r_i_10_n_0),\n .O(dec_po_r_i_14_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair362\" *) \n LUT3 #(\n .INIT(8'h4F)) \n dec_po_r_i_15\n (.I0(\\ninety_offsets_final_r_reg[0] ),\n .I1(f2o_r_reg_0),\n .I2(z2f_r_reg_n_0),\n .O(dec_po_r_i_15_n_0));\n LUT6 #(\n .INIT(64'hBF8CBF80B380BF80)) \n dec_po_r_i_16\n (.I0(\\fuzz2oneeighty_r_reg_n_0_[5] ),\n .I1(f2o_r_reg_0),\n .I2(z2f_r_reg_n_0),\n .I3(\\stg3_right_lim_reg[5] [5]),\n .I4(o2f_r_reg_0),\n .I5(\\oneeighty2fuzz_r_reg_n_0_[5] ),\n .O(dec_po_r_i_16_n_0));\n LUT6 #(\n .INIT(64'h0000000035355535)) \n dec_po_r_i_17\n (.I0(dec_po_r_i_26_n_0),\n .I1(\\zero2fuzz_r_reg_n_0_[1] ),\n .I2(z2f_r_reg_n_0),\n .I3(f2o_r_reg_0),\n .I4(\\ninety_offsets_final_r_reg[0] ),\n .I5(ocd_ktap_left_r_reg),\n .O(dec_po_r_i_17_n_0));\n LUT5 #(\n .INIT(32'hBF8CB380)) \n dec_po_r_i_18\n (.I0(\\zero2fuzz_r_reg_n_0_[1] ),\n .I1(f2o_r_reg_0),\n .I2(z2f_r_reg_n_0),\n .I3(\\stg3_left_lim_reg[5] [1]),\n .I4(\\fuzz2oneeighty_r_reg_n_0_[1] ),\n .O(dec_po_r_i_18_n_0));\n LUT6 #(\n .INIT(64'h008E00FF0000008E)) \n dec_po_r_i_2\n (.I0(Q[1]),\n .I1(dec_po_r_i_6_n_0),\n .I2(dec_po_r_i_7_n_0),\n .I3(inc_po_r_i_3_n_0),\n .I4(dec_po_r_reg_i_8_n_0),\n .I5(Q[2]),\n .O(dec_po_r_i_2_n_0));\n LUT5 #(\n .INIT(32'hEFAA20AA)) \n dec_po_r_i_20\n (.I0(dec_po_r_i_29_n_0),\n .I1(\\ninety_offsets_final_r_reg[0] ),\n .I2(f2o_r_reg_0),\n .I3(z2f_r_reg_n_0),\n .I4(\\zero2fuzz_r_reg_n_0_[2] ),\n .O(dec_po_r_i_20_n_0));\n LUT5 #(\n .INIT(32'hBFBB8088)) \n dec_po_r_i_21\n (.I0(\\fuzz2zero_r_reg_n_0_[2] ),\n .I1(\\ninety_offsets_final_r_reg[0] ),\n .I2(z2f_r_reg_n_0),\n .I3(f2o_r_reg_0),\n .I4(dec_po_r_i_30_n_0),\n .O(dec_po_r_i_21_n_0));\n LUT6 #(\n .INIT(64'hBF8CBF80B380BF80)) \n dec_po_r_i_22\n (.I0(\\fuzz2oneeighty_r_reg_n_0_[3] ),\n .I1(f2o_r_reg_0),\n .I2(z2f_r_reg_n_0),\n .I3(\\stg3_right_lim_reg[5] [3]),\n .I4(o2f_r_reg_0),\n .I5(\\oneeighty2fuzz_r_reg_n_0_[3] ),\n .O(dec_po_r_i_22_n_0));\n LUT6 #(\n .INIT(64'hBF8CBF80B380BF80)) \n dec_po_r_i_23\n (.I0(\\fuzz2oneeighty_r_reg_n_0_[4] ),\n .I1(f2o_r_reg_0),\n .I2(z2f_r_reg_n_0),\n .I3(\\stg3_right_lim_reg[5] [4]),\n .I4(o2f_r_reg_0),\n .I5(\\oneeighty2fuzz_r_reg_n_0_[4] ),\n .O(dec_po_r_i_23_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair361\" *) \n LUT4 #(\n .INIT(16'h0437)) \n dec_po_r_i_24\n (.I0(\\fuzz2oneeighty_r_reg_n_0_[5] ),\n .I1(f2o_r_reg_0),\n .I2(z2f_r_reg_n_0),\n .I3(\\stg3_left_lim_reg[5] [5]),\n .O(dec_po_r_i_24_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair359\" *) \n LUT2 #(\n .INIT(4'h8)) \n dec_po_r_i_25\n (.I0(f2o_r_reg_0),\n .I1(z2f_r_reg_n_0),\n .O(\\u_ocd_po_cntlr/noise ));\n LUT6 #(\n .INIT(64'hBF8CBF80B380BF80)) \n dec_po_r_i_26\n (.I0(\\fuzz2oneeighty_r_reg_n_0_[1] ),\n .I1(f2o_r_reg_0),\n .I2(z2f_r_reg_n_0),\n .I3(\\stg3_right_lim_reg[5] [1]),\n .I4(o2f_r_reg_0),\n .I5(\\oneeighty2fuzz_r_reg_n_0_[1] ),\n .O(dec_po_r_i_26_n_0));\n LUT5 #(\n .INIT(32'h8A00BAFF)) \n dec_po_r_i_27\n (.I0(\\zero2fuzz_r_reg_n_0_[0] ),\n .I1(\\ninety_offsets_final_r_reg[0] ),\n .I2(f2o_r_reg_0),\n .I3(z2f_r_reg_n_0),\n .I4(dec_po_r_i_31_n_0),\n .O(dec_po_r_i_27_n_0));\n LUT5 #(\n .INIT(32'hBFBB8088)) \n dec_po_r_i_28\n (.I0(\\fuzz2zero_r_reg_n_0_[0] ),\n .I1(\\ninety_offsets_final_r_reg[0] ),\n .I2(z2f_r_reg_n_0),\n .I3(f2o_r_reg_0),\n .I4(dec_po_r_i_32_n_0),\n .O(dec_po_r_i_28_n_0));\n LUT6 #(\n .INIT(64'hFFAAE2AA00AAE2AA)) \n dec_po_r_i_29\n (.I0(\\stg3_right_lim_reg[5] [2]),\n .I1(o2f_r_reg_0),\n .I2(\\oneeighty2fuzz_r_reg_n_0_[2] ),\n .I3(f2o_r_reg_0),\n .I4(z2f_r_reg_n_0),\n .I5(\\fuzz2oneeighty_r_reg_n_0_[2] ),\n .O(dec_po_r_i_29_n_0));\n LUT6 #(\n .INIT(64'hAEAABFAA00000000)) \n dec_po_r_i_3\n (.I0(dec_po_r_i_9_n_0),\n .I1(dec_po_r_i_10_n_0),\n .I2(\\fuzz2zero_r_reg_n_0_[3] ),\n .I3(ocd_ktap_left_r_reg),\n .I4(dec_po_r_i_11_n_0),\n .I5(Q[3]),\n .O(dec_po_r_i_3_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair359\" *) \n LUT5 #(\n .INIT(32'hBF8CB380)) \n dec_po_r_i_30\n (.I0(\\zero2fuzz_r_reg_n_0_[2] ),\n .I1(f2o_r_reg_0),\n .I2(z2f_r_reg_n_0),\n .I3(\\stg3_left_lim_reg[5] [2]),\n .I4(\\fuzz2oneeighty_r_reg_n_0_[2] ),\n .O(dec_po_r_i_30_n_0));\n LUT6 #(\n .INIT(64'h00FF55551D1D5555)) \n dec_po_r_i_31\n (.I0(\\stg3_right_lim_reg[5] [0]),\n .I1(o2f_r_reg_0),\n .I2(\\oneeighty2fuzz_r_reg_n_0_[0] ),\n .I3(\\fuzz2oneeighty_r_reg_n_0_[0] ),\n .I4(f2o_r_reg_0),\n .I5(z2f_r_reg_n_0),\n .O(dec_po_r_i_31_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair360\" *) \n LUT5 #(\n .INIT(32'hFACA0ACA)) \n dec_po_r_i_32\n (.I0(\\stg3_left_lim_reg[5] [0]),\n .I1(\\fuzz2oneeighty_r_reg_n_0_[0] ),\n .I2(f2o_r_reg_0),\n .I3(z2f_r_reg_n_0),\n .I4(\\zero2fuzz_r_reg_n_0_[0] ),\n .O(dec_po_r_i_32_n_0));\n LUT5 #(\n .INIT(32'hFFFF2070)) \n dec_po_r_i_4\n (.I0(dec_po_r_i_10_n_0),\n .I1(\\fuzz2zero_r_reg_n_0_[4] ),\n .I2(ocd_ktap_left_r_reg),\n .I3(dec_po_r_i_12_n_0),\n .I4(dec_po_r_i_13_n_0),\n .O(dec_po_r_i_4_n_0));\n LUT5 #(\n .INIT(32'h55544544)) \n dec_po_r_i_5\n (.I0(dec_po_r_i_14_n_0),\n .I1(ocd_ktap_left_r_reg),\n .I2(dec_po_r_i_15_n_0),\n .I3(\\zero2fuzz_r_reg_n_0_[5] ),\n .I4(dec_po_r_i_16_n_0),\n .O(dec_po_r_i_5_n_0));\n LUT5 #(\n .INIT(32'hABEFAAAA)) \n dec_po_r_i_6\n (.I0(dec_po_r_i_17_n_0),\n .I1(dec_po_r_i_10_n_0),\n .I2(dec_po_r_i_18_n_0),\n .I3(\\fuzz2zero_r_reg_n_0_[1] ),\n .I4(ocd_ktap_left_r_reg),\n .O(dec_po_r_i_6_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair363\" *) \n LUT2 #(\n .INIT(4'hB)) \n dec_po_r_i_7\n (.I0(dec_po_r_reg_i_19_n_0),\n .I1(Q[0]),\n .O(dec_po_r_i_7_n_0));\n LUT6 #(\n .INIT(64'h1010001015155515)) \n dec_po_r_i_9\n (.I0(ocd_ktap_left_r_reg),\n .I1(\\zero2fuzz_r_reg_n_0_[3] ),\n .I2(z2f_r_reg_n_0),\n .I3(f2o_r_reg_0),\n .I4(\\ninety_offsets_final_r_reg[0] ),\n .I5(dec_po_r_i_22_n_0),\n .O(dec_po_r_i_9_n_0));\n MUXF7 dec_po_r_reg_i_19\n (.I0(dec_po_r_i_27_n_0),\n .I1(dec_po_r_i_28_n_0),\n .O(dec_po_r_reg_i_19_n_0),\n .S(ocd_ktap_left_r_reg));\n MUXF7 dec_po_r_reg_i_8\n (.I0(dec_po_r_i_20_n_0),\n .I1(dec_po_r_i_21_n_0),\n .O(dec_po_r_reg_i_8_n_0),\n .S(ocd_ktap_left_r_reg));\n LUT6 #(\n .INIT(64'hFFFFFFFF00000020)) \n f2o_r_i_1\n (.I0(rd_active_r1_reg),\n .I1(rd_active_r1_reg_0),\n .I2(scanning_right),\n .I3(\\fuzz2oneeighty_r[5]_i_2_n_0 ),\n .I4(prev_samp_r[1]),\n .I5(f2o_r_reg_0),\n .O(f2o_r_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n f2o_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(f2o_r_i_1_n_0),\n .Q(f2o_r_reg_0),\n .R(reset_scan));\n FDRE #(\n .INIT(1'b0)) \n f2z_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(scanning_right_r_reg_0),\n .Q(\\ninety_offsets_final_r_reg[0] ),\n .R(reset_scan));\n LUT6 #(\n .INIT(64'h0000000000100000)) \n \\fuzz2oneeighty_r[5]_i_1 \n (.I0(prev_samp_r[1]),\n .I1(\\fuzz2oneeighty_r[5]_i_2_n_0 ),\n .I2(scanning_right),\n .I3(rd_active_r1_reg_0),\n .I4(rd_active_r1_reg),\n .I5(reset_scan),\n .O(\\fuzz2oneeighty_r[5]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h7F)) \n \\fuzz2oneeighty_r[5]_i_2 \n (.I0(prev_samp_valid_r),\n .I1(rd_active_r1),\n .I2(samp_done),\n .O(\\fuzz2oneeighty_r[5]_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\fuzz2oneeighty_r_reg[0] \n (.C(CLK),\n .CE(\\fuzz2oneeighty_r[5]_i_1_n_0 ),\n .D(Q[0]),\n .Q(\\fuzz2oneeighty_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fuzz2oneeighty_r_reg[1] \n (.C(CLK),\n .CE(\\fuzz2oneeighty_r[5]_i_1_n_0 ),\n .D(Q[1]),\n .Q(\\fuzz2oneeighty_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fuzz2oneeighty_r_reg[2] \n (.C(CLK),\n .CE(\\fuzz2oneeighty_r[5]_i_1_n_0 ),\n .D(Q[2]),\n .Q(\\fuzz2oneeighty_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fuzz2oneeighty_r_reg[3] \n (.C(CLK),\n .CE(\\fuzz2oneeighty_r[5]_i_1_n_0 ),\n .D(Q[3]),\n .Q(\\fuzz2oneeighty_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fuzz2oneeighty_r_reg[4] \n (.C(CLK),\n .CE(\\fuzz2oneeighty_r[5]_i_1_n_0 ),\n .D(Q[4]),\n .Q(\\fuzz2oneeighty_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fuzz2oneeighty_r_reg[5] \n (.C(CLK),\n .CE(\\fuzz2oneeighty_r[5]_i_1_n_0 ),\n .D(Q[5]),\n .Q(\\fuzz2oneeighty_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fuzz2zero_r_reg[0] \n (.C(CLK),\n .CE(E),\n .D(Q[0]),\n .Q(\\fuzz2zero_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fuzz2zero_r_reg[1] \n (.C(CLK),\n .CE(E),\n .D(Q[1]),\n .Q(\\fuzz2zero_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fuzz2zero_r_reg[2] \n (.C(CLK),\n .CE(E),\n .D(Q[2]),\n .Q(\\fuzz2zero_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fuzz2zero_r_reg[3] \n (.C(CLK),\n .CE(E),\n .D(Q[3]),\n .Q(\\fuzz2zero_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fuzz2zero_r_reg[4] \n (.C(CLK),\n .CE(E),\n .D(Q[4]),\n .Q(\\fuzz2zero_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fuzz2zero_r_reg[5] \n (.C(CLK),\n .CE(E),\n .D(Q[5]),\n .Q(\\fuzz2zero_r_reg_n_0_[5] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h70F770F770F710F1)) \n inc_po_r_i_1\n (.I0(dec_po_r_i_4_n_0),\n .I1(Q[4]),\n .I2(dec_po_r_i_5_n_0),\n .I3(Q[5]),\n .I4(inc_po_r_i_2_n_0),\n .I5(inc_po_r_i_3_n_0),\n .O(inc_po_ns));\n LUT6 #(\n .INIT(64'h0000000071FF0071)) \n inc_po_r_i_2\n (.I0(dec_po_r_i_6_n_0),\n .I1(Q[1]),\n .I2(inc_po_r_i_4_n_0),\n .I3(Q[2]),\n .I4(dec_po_r_reg_i_8_n_0),\n .I5(dec_po_r_i_3_n_0),\n .O(inc_po_r_i_2_n_0));\n LUT6 #(\n .INIT(64'h0000000051554055)) \n inc_po_r_i_3\n (.I0(dec_po_r_i_9_n_0),\n .I1(dec_po_r_i_10_n_0),\n .I2(\\fuzz2zero_r_reg_n_0_[3] ),\n .I3(ocd_ktap_left_r_reg),\n .I4(dec_po_r_i_11_n_0),\n .I5(Q[3]),\n .O(inc_po_r_i_3_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair363\" *) \n LUT2 #(\n .INIT(4'h2)) \n inc_po_r_i_4\n (.I0(dec_po_r_reg_i_19_n_0),\n .I1(Q[0]),\n .O(inc_po_r_i_4_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair362\" *) \n LUT3 #(\n .INIT(8'h20)) \n \\ninety_offsets_final_r[0]_i_1 \n (.I0(f2o_r_reg_0),\n .I1(\\ninety_offsets_final_r_reg[0] ),\n .I2(z2f_r_reg_n_0),\n .O(\\ninety_offsets_final_r_reg[0]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair360\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\ninety_offsets_final_r[1]_i_1 \n (.I0(f2o_r_reg_0),\n .I1(z2f_r_reg_n_0),\n .O(\\ninety_offsets_final_r_reg[1] ));\n FDRE #(\n .INIT(1'b0)) \n o2f_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(scanning_right_r_reg),\n .Q(o2f_r_reg_0),\n .R(reset_scan));\n FDRE #(\n .INIT(1'b0)) \n \\oneeighty2fuzz_r_reg[0] \n (.C(CLK),\n .CE(reset_scan_r_reg),\n .D(D[0]),\n .Q(\\oneeighty2fuzz_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\oneeighty2fuzz_r_reg[1] \n (.C(CLK),\n .CE(reset_scan_r_reg),\n .D(D[1]),\n .Q(\\oneeighty2fuzz_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\oneeighty2fuzz_r_reg[2] \n (.C(CLK),\n .CE(reset_scan_r_reg),\n .D(D[2]),\n .Q(\\oneeighty2fuzz_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\oneeighty2fuzz_r_reg[3] \n (.C(CLK),\n .CE(reset_scan_r_reg),\n .D(D[3]),\n .Q(\\oneeighty2fuzz_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\oneeighty2fuzz_r_reg[4] \n (.C(CLK),\n .CE(reset_scan_r_reg),\n .D(D[4]),\n .Q(\\oneeighty2fuzz_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\oneeighty2fuzz_r_reg[5] \n (.C(CLK),\n .CE(reset_scan_r_reg),\n .D(D[5]),\n .Q(\\oneeighty2fuzz_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\prev_samp_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\samp_result_r_reg[0] ),\n .Q(prev_samp_r[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\prev_samp_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\samp_result_r_reg[1] ),\n .Q(prev_samp_r[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n prev_samp_valid_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(samp_done_r_reg),\n .Q(prev_samp_valid_r),\n .R(reset_scan));\n LUT6 #(\n .INIT(64'h0000000000000010)) \n scan_right_r_i_1\n (.I0(rd_active_r1_reg_0),\n .I1(scanning_right),\n .I2(prev_samp_r[0]),\n .I3(prev_samp_r[1]),\n .I4(\\fuzz2oneeighty_r[5]_i_2_n_0 ),\n .I5(reset_scan),\n .O(scan_right_r_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n scan_right_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(scan_right_r_i_1_n_0),\n .Q(scan_right),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFFFFFFF00000400)) \n z2f_r_i_1\n (.I0(\\fuzz2oneeighty_r[5]_i_2_n_0 ),\n .I1(scanning_right),\n .I2(rd_active_r1_reg_0),\n .I3(prev_samp_r[0]),\n .I4(prev_samp_r[1]),\n .I5(z2f_r_reg_n_0),\n .O(z2f_r_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n z2f_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(z2f_r_i_1_n_0),\n .Q(z2f_r_reg_n_0),\n .R(reset_scan));\n LUT6 #(\n .INIT(64'h0000000000000400)) \n \\zero2fuzz_r[5]_i_1 \n (.I0(prev_samp_r[1]),\n .I1(prev_samp_r[0]),\n .I2(rd_active_r1_reg_0),\n .I3(scanning_right),\n .I4(\\fuzz2oneeighty_r[5]_i_2_n_0 ),\n .I5(reset_scan),\n .O(zero2fuzz_ns));\n FDRE #(\n .INIT(1'b0)) \n \\zero2fuzz_r_reg[0] \n (.C(CLK),\n .CE(zero2fuzz_ns),\n .D(D[0]),\n .Q(\\zero2fuzz_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\zero2fuzz_r_reg[1] \n (.C(CLK),\n .CE(zero2fuzz_ns),\n .D(D[1]),\n .Q(\\zero2fuzz_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\zero2fuzz_r_reg[2] \n (.C(CLK),\n .CE(zero2fuzz_ns),\n .D(D[2]),\n .Q(\\zero2fuzz_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\zero2fuzz_r_reg[3] \n (.C(CLK),\n .CE(zero2fuzz_ns),\n .D(D[3]),\n .Q(\\zero2fuzz_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\zero2fuzz_r_reg[4] \n (.C(CLK),\n .CE(zero2fuzz_ns),\n .D(D[4]),\n .Q(\\zero2fuzz_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\zero2fuzz_r_reg[5] \n (.C(CLK),\n .CE(zero2fuzz_ns),\n .D(D[5]),\n .Q(\\zero2fuzz_r_reg_n_0_[5] ),\n .R(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_phy_ocd_lim\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_phy_ocd_lim\n (lim_start_r,\n lim2poc_ktap_right,\n prech_req_r_reg_0,\n lim2stg2_inc,\n lim2stg3_dec,\n lim2stg3_inc,\n lim2stg2_dec,\n lim2poc_rdy,\n done_r_reg_0,\n po_stg23_sel_r_reg,\n stg3_dec2init_val_r_reg_0,\n stg3_inc2init_val_r_reg_0,\n \\stg2_tap_cnt_reg[0]_0 ,\n \\stg2_tap_cnt_reg[3]_0 ,\n \\stg3_tap_cnt_reg[2]_0 ,\n scanning_right_r_reg,\n scanning_right_r_reg_0,\n oclkdelay_center_calib_start_r_reg,\n oclkdelay_center_calib_start_r_reg_0,\n \\init_state_r_reg[6] ,\n \\init_state_r_reg[5] ,\n \\init_state_r_reg[4] ,\n rstdiv0_sync_r1_reg_rep__10,\n CLK,\n lim_start,\n rstdiv0_sync_r1_reg_rep__9,\n done_r_reg_1,\n rstdiv0_sync_r1_reg_rep__25,\n \\po_wait_r_reg[0] ,\n \\sm_r_reg[2] ,\n lim_start_r_reg_0,\n prech_done,\n \\wl_po_fine_cnt_reg[17] ,\n rstdiv0_sync_r1_reg_rep__20,\n \\byte_r_reg[0] ,\n Q,\n \\stg2_tap_cnt_reg[2]_0 ,\n \\wl_po_fine_cnt_reg[3] ,\n \\wl_po_fine_cnt_reg[14] ,\n \\wl_po_fine_cnt_reg[18] ,\n \\rise_lead_r_reg[5] ,\n rstdiv0_sync_r1_reg_rep__25_0,\n po_rdy,\n scan_right,\n scanning_right,\n \\stg3_r_reg[5] ,\n o2f_r_reg,\n \\mmcm_init_trail_reg[0]_0 ,\n \\mmcm_current_reg[0]_0 ,\n prbs_rdlvl_done_reg_rep,\n ocd_prech_req_r_reg,\n oclk_center_write_resume,\n cnt_cmd_done_r,\n rstdiv0_sync_r1_reg_rep__19,\n rstdiv0_sync_r1_reg_rep__11,\n D,\n oclkdelay_calib_done_r_reg);\n output lim_start_r;\n output lim2poc_ktap_right;\n output prech_req_r_reg_0;\n output lim2stg2_inc;\n output lim2stg3_dec;\n output lim2stg3_inc;\n output lim2stg2_dec;\n output lim2poc_rdy;\n output done_r_reg_0;\n output po_stg23_sel_r_reg;\n output stg3_dec2init_val_r_reg_0;\n output stg3_inc2init_val_r_reg_0;\n output \\stg2_tap_cnt_reg[0]_0 ;\n output [2:0]\\stg2_tap_cnt_reg[3]_0 ;\n output [2:0]\\stg3_tap_cnt_reg[2]_0 ;\n output scanning_right_r_reg;\n output [5:0]scanning_right_r_reg_0;\n output oclkdelay_center_calib_start_r_reg;\n output [5:0]oclkdelay_center_calib_start_r_reg_0;\n output \\init_state_r_reg[6] ;\n output \\init_state_r_reg[5] ;\n output \\init_state_r_reg[4] ;\n input rstdiv0_sync_r1_reg_rep__10;\n input CLK;\n input lim_start;\n input rstdiv0_sync_r1_reg_rep__9;\n input done_r_reg_1;\n input rstdiv0_sync_r1_reg_rep__25;\n input \\po_wait_r_reg[0] ;\n input \\sm_r_reg[2] ;\n input lim_start_r_reg_0;\n input prech_done;\n input \\wl_po_fine_cnt_reg[17] ;\n input rstdiv0_sync_r1_reg_rep__20;\n input \\byte_r_reg[0] ;\n input [5:0]Q;\n input \\stg2_tap_cnt_reg[2]_0 ;\n input \\wl_po_fine_cnt_reg[3] ;\n input [1:0]\\wl_po_fine_cnt_reg[14] ;\n input \\wl_po_fine_cnt_reg[18] ;\n input [5:0]\\rise_lead_r_reg[5] ;\n input rstdiv0_sync_r1_reg_rep__25_0;\n input po_rdy;\n input scan_right;\n input scanning_right;\n input [5:0]\\stg3_r_reg[5] ;\n input o2f_r_reg;\n input \\mmcm_init_trail_reg[0]_0 ;\n input \\mmcm_current_reg[0]_0 ;\n input prbs_rdlvl_done_reg_rep;\n input ocd_prech_req_r_reg;\n input oclk_center_write_resume;\n input cnt_cmd_done_r;\n input [0:0]rstdiv0_sync_r1_reg_rep__19;\n input rstdiv0_sync_r1_reg_rep__11;\n input [2:0]D;\n input [5:0]oclkdelay_calib_done_r_reg;\n\n wire CLK;\n wire [2:0]D;\n wire [5:0]Q;\n wire \\byte_r_reg[0] ;\n wire cnt_cmd_done_r;\n wire detect_done_r;\n wire done_r_i_1__0_n_0;\n wire done_r_reg_0;\n wire done_r_reg_1;\n wire \\init_state_r_reg[4] ;\n wire \\init_state_r_reg[5] ;\n wire \\init_state_r_reg[6] ;\n wire ktap_right_r_i_1_n_0;\n wire ktap_right_r_i_2_n_0;\n wire lim2init_write_request;\n wire lim2poc_ktap_right;\n wire lim2poc_rdy;\n wire lim2stg2_dec;\n wire lim2stg2_inc;\n wire lim2stg3_dec;\n wire lim2stg3_inc;\n wire lim_nxt_state;\n wire lim_start;\n wire lim_start_r;\n wire lim_start_r_reg_0;\n wire [13:0]lim_state;\n wire \\lim_state[0]_i_1_n_0 ;\n wire \\lim_state[0]_i_2_n_0 ;\n wire \\lim_state[0]_i_3_n_0 ;\n wire \\lim_state[0]_i_4_n_0 ;\n wire \\lim_state[0]_i_5_n_0 ;\n wire \\lim_state[10]_i_1_n_0 ;\n wire \\lim_state[10]_i_2_n_0 ;\n wire \\lim_state[10]_i_3_n_0 ;\n wire \\lim_state[11]_i_1_n_0 ;\n wire \\lim_state[11]_i_2_n_0 ;\n wire \\lim_state[11]_i_3_n_0 ;\n wire \\lim_state[11]_i_4_n_0 ;\n wire \\lim_state[11]_i_5_n_0 ;\n wire \\lim_state[11]_i_6_n_0 ;\n wire \\lim_state[11]_i_7_n_0 ;\n wire \\lim_state[12]_i_1_n_0 ;\n wire \\lim_state[12]_i_2_n_0 ;\n wire \\lim_state[12]_i_3_n_0 ;\n wire \\lim_state[12]_i_4_n_0 ;\n wire \\lim_state[12]_i_5_n_0 ;\n wire \\lim_state[12]_i_7_n_0 ;\n wire \\lim_state[13]_i_10_n_0 ;\n wire \\lim_state[13]_i_11_n_0 ;\n wire \\lim_state[13]_i_12_n_0 ;\n wire \\lim_state[13]_i_13_n_0 ;\n wire \\lim_state[13]_i_14_n_0 ;\n wire \\lim_state[13]_i_2_n_0 ;\n wire \\lim_state[13]_i_3_n_0 ;\n wire \\lim_state[13]_i_4_n_0 ;\n wire \\lim_state[13]_i_5_n_0 ;\n wire \\lim_state[13]_i_6_n_0 ;\n wire \\lim_state[13]_i_7_n_0 ;\n wire \\lim_state[13]_i_8_n_0 ;\n wire \\lim_state[13]_i_9_n_0 ;\n wire \\lim_state[1]_i_1_n_0 ;\n wire \\lim_state[1]_i_2_n_0 ;\n wire \\lim_state[2]_i_1_n_0 ;\n wire \\lim_state[2]_i_2_n_0 ;\n wire \\lim_state[2]_i_3_n_0 ;\n wire \\lim_state[2]_i_4_n_0 ;\n wire \\lim_state[3]_i_1_n_0 ;\n wire \\lim_state[4]_i_1_n_0 ;\n wire \\lim_state[4]_i_2_n_0 ;\n wire \\lim_state[4]_i_3_n_0 ;\n wire \\lim_state[5]_i_1_n_0 ;\n wire \\lim_state[5]_i_2_n_0 ;\n wire \\lim_state[6]_i_10_n_0 ;\n wire \\lim_state[6]_i_11_n_0 ;\n wire \\lim_state[6]_i_12_n_0 ;\n wire \\lim_state[6]_i_13_n_0 ;\n wire \\lim_state[6]_i_14_n_0 ;\n wire \\lim_state[6]_i_15_n_0 ;\n wire \\lim_state[6]_i_16_n_0 ;\n wire \\lim_state[6]_i_17_n_0 ;\n wire \\lim_state[6]_i_18_n_0 ;\n wire \\lim_state[6]_i_19_n_0 ;\n wire \\lim_state[6]_i_1_n_0 ;\n wire \\lim_state[6]_i_20_n_0 ;\n wire \\lim_state[6]_i_21_n_0 ;\n wire \\lim_state[6]_i_22_n_0 ;\n wire \\lim_state[6]_i_2_n_0 ;\n wire \\lim_state[6]_i_3_n_0 ;\n wire \\lim_state[6]_i_4_n_0 ;\n wire \\lim_state[6]_i_5_n_0 ;\n wire \\lim_state[6]_i_6_n_0 ;\n wire \\lim_state[6]_i_7_n_0 ;\n wire \\lim_state[6]_i_8_n_0 ;\n wire \\lim_state[6]_i_9_n_0 ;\n wire \\lim_state[7]_i_1_n_0 ;\n wire \\lim_state[7]_i_2_n_0 ;\n wire \\lim_state[7]_i_3_n_0 ;\n wire \\lim_state[8]_i_1_n_0 ;\n wire \\lim_state[9]_i_1_n_0 ;\n wire \\lim_state[9]_i_2_n_0 ;\n wire \\lim_state[9]_i_3_n_0 ;\n wire \\mmcm_current[0]_i_1_n_0 ;\n wire \\mmcm_current[0]_i_2_n_0 ;\n wire \\mmcm_current[1]_i_1_n_0 ;\n wire \\mmcm_current[1]_i_2_n_0 ;\n wire \\mmcm_current[2]_i_1_n_0 ;\n wire \\mmcm_current[2]_i_2_n_0 ;\n wire \\mmcm_current[3]_i_1_n_0 ;\n wire \\mmcm_current[3]_i_2_n_0 ;\n wire \\mmcm_current[4]_i_1_n_0 ;\n wire \\mmcm_current[4]_i_2_n_0 ;\n wire \\mmcm_current[5]_i_1_n_0 ;\n wire \\mmcm_current[5]_i_2_n_0 ;\n wire \\mmcm_current_reg[0]_0 ;\n wire \\mmcm_current_reg_n_0_[0] ;\n wire \\mmcm_current_reg_n_0_[1] ;\n wire \\mmcm_current_reg_n_0_[2] ;\n wire \\mmcm_current_reg_n_0_[3] ;\n wire \\mmcm_current_reg_n_0_[4] ;\n wire \\mmcm_current_reg_n_0_[5] ;\n wire mmcm_init_lead;\n wire \\mmcm_init_lead[5]_i_2_n_0 ;\n wire \\mmcm_init_lead[5]_i_3_n_0 ;\n wire \\mmcm_init_lead[5]_i_4_n_0 ;\n wire \\mmcm_init_lead[5]_i_5_n_0 ;\n wire \\mmcm_init_lead[5]_i_6_n_0 ;\n wire \\mmcm_init_lead[5]_i_7_n_0 ;\n wire \\mmcm_init_lead[5]_i_8_n_0 ;\n wire \\mmcm_init_lead_reg_n_0_[0] ;\n wire \\mmcm_init_lead_reg_n_0_[1] ;\n wire \\mmcm_init_lead_reg_n_0_[2] ;\n wire \\mmcm_init_lead_reg_n_0_[3] ;\n wire \\mmcm_init_lead_reg_n_0_[4] ;\n wire \\mmcm_init_lead_reg_n_0_[5] ;\n wire mmcm_init_trail;\n wire \\mmcm_init_trail[5]_i_2_n_0 ;\n wire \\mmcm_init_trail[5]_i_3_n_0 ;\n wire \\mmcm_init_trail[5]_i_4_n_0 ;\n wire \\mmcm_init_trail_reg[0]_0 ;\n wire \\mmcm_init_trail_reg_n_0_[0] ;\n wire \\mmcm_init_trail_reg_n_0_[1] ;\n wire \\mmcm_init_trail_reg_n_0_[2] ;\n wire \\mmcm_init_trail_reg_n_0_[3] ;\n wire \\mmcm_init_trail_reg_n_0_[4] ;\n wire \\mmcm_init_trail_reg_n_0_[5] ;\n wire mod_sub0_return0__14_carry__0_i_1_n_0;\n wire mod_sub0_return0__14_carry__0_i_2_n_0;\n wire mod_sub0_return0__14_carry__0_n_1;\n wire mod_sub0_return0__14_carry__0_n_3;\n wire mod_sub0_return0__14_carry__0_n_6;\n wire mod_sub0_return0__14_carry__0_n_7;\n wire mod_sub0_return0__14_carry_i_1_n_0;\n wire mod_sub0_return0__14_carry_i_2_n_0;\n wire mod_sub0_return0__14_carry_i_3_n_0;\n wire mod_sub0_return0__14_carry_i_4_n_0;\n wire mod_sub0_return0__14_carry_n_0;\n wire mod_sub0_return0__14_carry_n_1;\n wire mod_sub0_return0__14_carry_n_2;\n wire mod_sub0_return0__14_carry_n_3;\n wire mod_sub0_return0__14_carry_n_4;\n wire mod_sub0_return0__14_carry_n_5;\n wire mod_sub0_return0__14_carry_n_6;\n wire mod_sub0_return0_carry__0_i_1_n_0;\n wire mod_sub0_return0_carry__0_i_2_n_0;\n wire mod_sub0_return0_carry__0_i_3_n_0;\n wire mod_sub0_return0_carry__0_i_4_n_0;\n wire mod_sub0_return0_carry__0_i_5_n_0;\n wire mod_sub0_return0_carry__0_n_2;\n wire mod_sub0_return0_carry__0_n_3;\n wire mod_sub0_return0_carry__0_n_5;\n wire mod_sub0_return0_carry__0_n_6;\n wire mod_sub0_return0_carry__0_n_7;\n wire mod_sub0_return0_carry_i_1_n_0;\n wire mod_sub0_return0_carry_i_2_n_0;\n wire mod_sub0_return0_carry_i_3_n_0;\n wire mod_sub0_return0_carry_i_4_n_0;\n wire mod_sub0_return0_carry_n_0;\n wire mod_sub0_return0_carry_n_1;\n wire mod_sub0_return0_carry_n_2;\n wire mod_sub0_return0_carry_n_3;\n wire mod_sub0_return0_carry_n_4;\n wire mod_sub0_return0_carry_n_5;\n wire mod_sub0_return0_carry_n_6;\n wire mod_sub0_return0_carry_n_7;\n wire mod_sub_return0__14_carry__0_i_1_n_0;\n wire mod_sub_return0__14_carry__0_i_2_n_0;\n wire mod_sub_return0__14_carry__0_n_1;\n wire mod_sub_return0__14_carry__0_n_3;\n wire mod_sub_return0__14_carry__0_n_6;\n wire mod_sub_return0__14_carry__0_n_7;\n wire mod_sub_return0__14_carry_i_1_n_0;\n wire mod_sub_return0__14_carry_i_2_n_0;\n wire mod_sub_return0__14_carry_i_3_n_0;\n wire mod_sub_return0__14_carry_i_4_n_0;\n wire mod_sub_return0__14_carry_n_0;\n wire mod_sub_return0__14_carry_n_1;\n wire mod_sub_return0__14_carry_n_2;\n wire mod_sub_return0__14_carry_n_3;\n wire mod_sub_return0__14_carry_n_4;\n wire mod_sub_return0__14_carry_n_5;\n wire mod_sub_return0__14_carry_n_6;\n wire mod_sub_return0_carry__0_i_1__0_n_0;\n wire mod_sub_return0_carry__0_i_2_n_0;\n wire mod_sub_return0_carry__0_i_3_n_0;\n wire mod_sub_return0_carry__0_i_4_n_0;\n wire mod_sub_return0_carry__0_i_5_n_0;\n wire mod_sub_return0_carry__0_n_2;\n wire mod_sub_return0_carry__0_n_3;\n wire mod_sub_return0_carry__0_n_5;\n wire mod_sub_return0_carry__0_n_6;\n wire mod_sub_return0_carry__0_n_7;\n wire mod_sub_return0_carry_i_1__0_n_0;\n wire mod_sub_return0_carry_i_2_n_0;\n wire mod_sub_return0_carry_i_3_n_0;\n wire mod_sub_return0_carry_i_4_n_0;\n wire mod_sub_return0_carry_n_0;\n wire mod_sub_return0_carry_n_1;\n wire mod_sub_return0_carry_n_2;\n wire mod_sub_return0_carry_n_3;\n wire mod_sub_return0_carry_n_4;\n wire mod_sub_return0_carry_n_5;\n wire mod_sub_return0_carry_n_6;\n wire mod_sub_return0_carry_n_7;\n wire o2f_r_reg;\n wire ocd_prech_req_r_reg;\n wire oclk_center_write_resume;\n wire [5:0]oclkdelay_calib_done_r_reg;\n wire oclkdelay_center_calib_start_r_i_3_n_0;\n wire oclkdelay_center_calib_start_r_i_4_n_0;\n wire oclkdelay_center_calib_start_r_reg;\n wire [5:0]oclkdelay_center_calib_start_r_reg_0;\n wire [3:0]p_0_in;\n wire [5:0]p_0_in__0;\n wire po_rdy;\n wire po_stg23_sel_r_reg;\n wire \\po_wait_r_reg[0] ;\n wire poc_ready_r_i_1_n_0;\n wire prbs_rdlvl_done_reg_rep;\n wire prech_done;\n wire prech_req_r_i_1__0_n_0;\n wire prech_req_r_i_2_n_0;\n wire prech_req_r_reg_0;\n wire [5:0]\\rise_lead_r_reg[5] ;\n wire rstdiv0_sync_r1_reg_rep__10;\n wire rstdiv0_sync_r1_reg_rep__11;\n wire [0:0]rstdiv0_sync_r1_reg_rep__19;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__25;\n wire rstdiv0_sync_r1_reg_rep__25_0;\n wire rstdiv0_sync_r1_reg_rep__9;\n wire scan_right;\n wire scanning_right;\n wire scanning_right_r_i_4_n_0;\n wire scanning_right_r_i_5_n_0;\n wire scanning_right_r_reg;\n wire [5:0]scanning_right_r_reg_0;\n wire \\sm_r_reg[2] ;\n wire stg2_dec_req_r_i_1_n_0;\n wire stg2_inc_r;\n wire stg2_inc_r_i_1_n_0;\n wire stg2_inc_r_i_2_n_0;\n wire stg2_inc_r_i_3_n_0;\n wire stg2_inc_r_i_4_n_0;\n wire stg2_inc_req_r_i_1_n_0;\n wire stg2_inc_req_r_i_2_n_0;\n wire stg2_tap_cnt0;\n wire \\stg2_tap_cnt[1]_i_3_n_0 ;\n wire \\stg2_tap_cnt[1]_i_4_n_0 ;\n wire \\stg2_tap_cnt[2]_i_3_n_0 ;\n wire \\stg2_tap_cnt[2]_i_4_n_0 ;\n wire \\stg2_tap_cnt[2]_i_5_n_0 ;\n wire \\stg2_tap_cnt[2]_i_6_n_0 ;\n wire \\stg2_tap_cnt[3]_i_3_n_0 ;\n wire \\stg2_tap_cnt[4]_i_3_n_0 ;\n wire \\stg2_tap_cnt[5]_i_6_n_0 ;\n wire \\stg2_tap_cnt_reg[0]_0 ;\n wire \\stg2_tap_cnt_reg[2]_0 ;\n wire [2:0]\\stg2_tap_cnt_reg[3]_0 ;\n wire [5:3]stg2_tap_cnt_reg__0;\n wire stg3_dec2init_val_r;\n wire stg3_dec2init_val_r1;\n wire stg3_dec2init_val_r_i_10_n_0;\n wire stg3_dec2init_val_r_i_12_n_0;\n wire stg3_dec2init_val_r_i_13_n_0;\n wire stg3_dec2init_val_r_i_1_n_0;\n wire stg3_dec2init_val_r_i_2_n_0;\n wire stg3_dec2init_val_r_i_3_n_0;\n wire stg3_dec2init_val_r_i_4_n_0;\n wire stg3_dec2init_val_r_i_5_n_0;\n wire stg3_dec2init_val_r_i_6_n_0;\n wire stg3_dec2init_val_r_i_7_n_0;\n wire stg3_dec2init_val_r_i_8_n_0;\n wire stg3_dec2init_val_r_i_9_n_0;\n wire stg3_dec2init_val_r_reg_0;\n wire stg3_dec_r;\n wire stg3_dec_r_i_1_n_0;\n wire stg3_dec_r_i_2_n_0;\n wire stg3_dec_r_i_3_n_0;\n wire stg3_dec_r_i_4_n_0;\n wire stg3_dec_r_i_5_n_0;\n wire stg3_dec_req_r_i_1_n_0;\n wire stg3_dec_req_r_i_2_n_0;\n wire stg3_dec_req_r_i_3_n_0;\n wire [5:0]stg3_dec_val;\n wire [4:3]stg3_dec_val00_out;\n wire \\stg3_dec_val[5]_i_1_n_0 ;\n wire \\stg3_dec_val[5]_i_2_n_0 ;\n wire \\stg3_dec_val[5]_i_3_n_0 ;\n wire stg3_inc2init_val_r;\n wire stg3_inc2init_val_r1;\n wire stg3_inc2init_val_r_i_1_n_0;\n wire stg3_inc2init_val_r_i_2_n_0;\n wire stg3_inc2init_val_r_i_3_n_0;\n wire stg3_inc2init_val_r_reg_0;\n wire stg3_inc_req_r_i_1_n_0;\n wire [5:0]stg3_inc_val;\n wire \\stg3_inc_val[0]_i_1_n_0 ;\n wire \\stg3_inc_val[1]_i_1_n_0 ;\n wire \\stg3_inc_val[2]_i_1_n_0 ;\n wire \\stg3_inc_val[2]_i_2_n_0 ;\n wire \\stg3_inc_val[3]_i_1_n_0 ;\n wire \\stg3_inc_val[3]_i_2_n_0 ;\n wire \\stg3_inc_val[4]_i_1_n_0 ;\n wire \\stg3_inc_val[5]_i_1_n_0 ;\n wire \\stg3_inc_val[5]_i_2_n_0 ;\n wire \\stg3_inc_val[5]_i_3_n_0 ;\n wire stg3_init_dec_r;\n wire stg3_init_dec_r_i_1_n_0;\n wire stg3_init_dec_r_i_2_n_0;\n wire stg3_init_dec_r_i_3_n_0;\n wire stg3_init_dec_r_i_4_n_0;\n wire [5:3]stg3_init_val;\n wire stg3_left_lim0;\n wire \\stg3_left_lim[5]_i_1_n_0 ;\n wire [5:0]\\stg3_r_reg[5] ;\n wire stg3_right_lim0;\n wire \\stg3_right_lim[5]_i_1_n_0 ;\n wire stg3_tap_cnt0;\n wire \\stg3_tap_cnt[0]_i_1_n_0 ;\n wire \\stg3_tap_cnt[1]_i_1_n_0 ;\n wire \\stg3_tap_cnt[1]_i_2_n_0 ;\n wire \\stg3_tap_cnt[2]_i_1_n_0 ;\n wire \\stg3_tap_cnt[2]_i_2_n_0 ;\n wire \\stg3_tap_cnt[3]_i_1_n_0 ;\n wire \\stg3_tap_cnt[3]_i_2_n_0 ;\n wire \\stg3_tap_cnt[3]_i_3_n_0 ;\n wire \\stg3_tap_cnt[3]_i_4_n_0 ;\n wire \\stg3_tap_cnt[4]_i_1_n_0 ;\n wire \\stg3_tap_cnt[5]_i_2_n_0 ;\n wire \\stg3_tap_cnt[5]_i_4_n_0 ;\n wire \\stg3_tap_cnt[5]_i_5_n_0 ;\n wire \\stg3_tap_cnt[5]_i_6_n_0 ;\n wire [2:0]\\stg3_tap_cnt_reg[2]_0 ;\n wire \\stg3_tap_cnt_reg_n_0_[0] ;\n wire \\stg3_tap_cnt_reg_n_0_[1] ;\n wire \\stg3_tap_cnt_reg_n_0_[2] ;\n wire \\stg3_tap_cnt_reg_n_0_[3] ;\n wire \\stg3_tap_cnt_reg_n_0_[4] ;\n wire \\stg3_tap_cnt_reg_n_0_[5] ;\n wire wait_cnt_done;\n wire wait_cnt_done_i_1_n_0;\n wire wait_cnt_en_r;\n wire wait_cnt_en_r0;\n wire wait_cnt_en_r_i_2_n_0;\n wire wait_cnt_en_r_i_3_n_0;\n wire \\wait_cnt_r[3]_i_1_n_0 ;\n wire [3:0]wait_cnt_r_reg__0;\n wire [1:0]\\wl_po_fine_cnt_reg[14] ;\n wire \\wl_po_fine_cnt_reg[17] ;\n wire \\wl_po_fine_cnt_reg[18] ;\n wire \\wl_po_fine_cnt_reg[3] ;\n wire write_request_r_i_1_n_0;\n wire write_request_r_i_2_n_0;\n wire [0:0]NLW_mod_sub0_return0__14_carry_O_UNCONNECTED;\n wire [3:1]NLW_mod_sub0_return0__14_carry__0_CO_UNCONNECTED;\n wire [3:2]NLW_mod_sub0_return0__14_carry__0_O_UNCONNECTED;\n wire [3:2]NLW_mod_sub0_return0_carry__0_CO_UNCONNECTED;\n wire [3:3]NLW_mod_sub0_return0_carry__0_O_UNCONNECTED;\n wire [0:0]NLW_mod_sub_return0__14_carry_O_UNCONNECTED;\n wire [3:1]NLW_mod_sub_return0__14_carry__0_CO_UNCONNECTED;\n wire [3:2]NLW_mod_sub_return0__14_carry__0_O_UNCONNECTED;\n wire [3:2]NLW_mod_sub_return0_carry__0_CO_UNCONNECTED;\n wire [3:3]NLW_mod_sub_return0_carry__0_O_UNCONNECTED;\n\n FDRE #(\n .INIT(1'b0)) \n detect_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(done_r_reg_1),\n .Q(detect_done_r),\n .R(rstdiv0_sync_r1_reg_rep__9));\n LUT6 #(\n .INIT(64'hFFFF7FFF00880000)) \n done_r_i_1__0\n (.I0(\\lim_state[0]_i_2_n_0 ),\n .I1(\\lim_state[4]_i_3_n_0 ),\n .I2(lim_start_r_reg_0),\n .I3(lim_state[0]),\n .I4(lim_state[13]),\n .I5(done_r_reg_0),\n .O(done_r_i_1__0_n_0));\n FDRE #(\n .INIT(1'b0)) \n done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(done_r_i_1__0_n_0),\n .Q(done_r_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__9));\n (* SOFT_HLUTNM = \"soft_lutpair388\" *) \n LUT3 #(\n .INIT(8'h02)) \n \\init_state_r[4]_i_35 \n (.I0(cnt_cmd_done_r),\n .I1(prech_req_r_reg_0),\n .I2(ocd_prech_req_r_reg),\n .O(\\init_state_r_reg[4] ));\n LUT2 #(\n .INIT(4'hE)) \n \\init_state_r[5]_i_37 \n (.I0(lim2init_write_request),\n .I1(oclk_center_write_resume),\n .O(\\init_state_r_reg[5] ));\n (* SOFT_HLUTNM = \"soft_lutpair388\" *) \n LUT3 #(\n .INIT(8'hFE)) \n \\init_state_r[6]_i_7 \n (.I0(prbs_rdlvl_done_reg_rep),\n .I1(prech_req_r_reg_0),\n .I2(ocd_prech_req_r_reg),\n .O(\\init_state_r_reg[6] ));\n LUT6 #(\n .INIT(64'hFFEFFFFF01000000)) \n ktap_right_r_i_1\n (.I0(\\lim_state[13]_i_7_n_0 ),\n .I1(lim_state[0]),\n .I2(lim_state[13]),\n .I3(lim_state[1]),\n .I4(ktap_right_r_i_2_n_0),\n .I5(lim2poc_ktap_right),\n .O(ktap_right_r_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair380\" *) \n LUT4 #(\n .INIT(16'h0001)) \n ktap_right_r_i_2\n (.I0(lim_state[9]),\n .I1(lim_state[12]),\n .I2(lim_state[10]),\n .I3(lim_state[11]),\n .O(ktap_right_r_i_2_n_0));\n FDRE #(\n .INIT(1'b0)) \n ktap_right_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(ktap_right_r_i_1_n_0),\n .Q(lim2poc_ktap_right),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE #(\n .INIT(1'b0)) \n lim_start_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(lim_start),\n .Q(lim_start_r),\n .R(rstdiv0_sync_r1_reg_rep__10));\n LUT4 #(\n .INIT(16'hFFD0)) \n \\lim_state[0]_i_1 \n (.I0(\\lim_state[0]_i_2_n_0 ),\n .I1(\\lim_state[0]_i_3_n_0 ),\n .I2(wait_cnt_en_r_i_2_n_0),\n .I3(\\lim_state[0]_i_4_n_0 ),\n .O(\\lim_state[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair375\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\lim_state[0]_i_2 \n (.I0(lim_state[1]),\n .I1(lim_state[4]),\n .I2(lim_state[2]),\n .I3(lim_state[3]),\n .O(\\lim_state[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hAAA8A880AAAAAAAA)) \n \\lim_state[0]_i_3 \n (.I0(\\lim_state[0]_i_5_n_0 ),\n .I1(lim_state[8]),\n .I2(lim_state[7]),\n .I3(lim_state[6]),\n .I4(lim_state[5]),\n .I5(\\lim_state[1]_i_2_n_0 ),\n .O(\\lim_state[0]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFDFFFCFCC2)) \n \\lim_state[0]_i_4 \n (.I0(\\lim_state[4]_i_3_n_0 ),\n .I1(lim_state[3]),\n .I2(lim_state[2]),\n .I3(lim_state[4]),\n .I4(lim_state[1]),\n .I5(lim_state[0]),\n .O(\\lim_state[0]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFEFEEC)) \n \\lim_state[0]_i_5 \n (.I0(lim_state[9]),\n .I1(lim_state[13]),\n .I2(lim_state[12]),\n .I3(lim_state[10]),\n .I4(lim_state[11]),\n .I5(wait_cnt_en_r_i_3_n_0),\n .O(\\lim_state[0]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000020200)) \n \\lim_state[10]_i_1 \n (.I0(\\lim_state[10]_i_2_n_0 ),\n .I1(lim_state[0]),\n .I2(lim_state[9]),\n .I3(lim_state[7]),\n .I4(lim_state[8]),\n .I5(\\lim_state[10]_i_3_n_0 ),\n .O(\\lim_state[10]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair366\" *) \n LUT5 #(\n .INIT(32'h00010000)) \n \\lim_state[10]_i_2 \n (.I0(lim_state[12]),\n .I1(lim_state[13]),\n .I2(lim_state[11]),\n .I3(lim_state[10]),\n .I4(\\lim_state[0]_i_2_n_0 ),\n .O(\\lim_state[10]_i_2_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\lim_state[10]_i_3 \n (.I0(lim_state[6]),\n .I1(lim_state[5]),\n .O(\\lim_state[10]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h00000000E2000000)) \n \\lim_state[11]_i_1 \n (.I0(\\lim_state[11]_i_2_n_0 ),\n .I1(lim_state[1]),\n .I2(\\lim_state[11]_i_3_n_0 ),\n .I3(\\lim_state[11]_i_4_n_0 ),\n .I4(\\lim_state[11]_i_5_n_0 ),\n .I5(lim_state[13]),\n .O(\\lim_state[11]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000FFFFA8A00000)) \n \\lim_state[11]_i_2 \n (.I0(\\lim_state[6]_i_4_n_0 ),\n .I1(stg3_inc2init_val_r),\n .I2(stg3_dec2init_val_r),\n .I3(\\lim_state[11]_i_6_n_0 ),\n .I4(lim_state[9]),\n .I5(lim_state[10]),\n .O(\\lim_state[11]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair380\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\lim_state[11]_i_3 \n (.I0(lim_state[10]),\n .I1(lim_state[9]),\n .O(\\lim_state[11]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'h00000001)) \n \\lim_state[11]_i_4 \n (.I0(lim_state[0]),\n .I1(lim_state[3]),\n .I2(lim_state[2]),\n .I3(lim_state[4]),\n .I4(wait_cnt_en_r_i_3_n_0),\n .O(\\lim_state[11]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair377\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\lim_state[11]_i_5 \n (.I0(lim_state[11]),\n .I1(lim_state[12]),\n .O(\\lim_state[11]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h444F444F444F4444)) \n \\lim_state[11]_i_6 \n (.I0(stg3_inc_val[5]),\n .I1(\\stg3_tap_cnt_reg_n_0_[5] ),\n .I2(\\mmcm_init_lead[5]_i_3_n_0 ),\n .I3(\\lim_state[11]_i_7_n_0 ),\n .I4(\\mmcm_init_lead[5]_i_6_n_0 ),\n .I5(\\mmcm_init_lead[5]_i_4_n_0 ),\n .O(\\lim_state[11]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h00B0BBBB000000B0)) \n \\lim_state[11]_i_7 \n (.I0(stg3_inc_val[4]),\n .I1(\\stg3_tap_cnt_reg_n_0_[4] ),\n .I2(stg3_inc_val[2]),\n .I3(\\stg3_tap_cnt_reg_n_0_[2] ),\n .I4(\\stg3_tap_cnt_reg_n_0_[3] ),\n .I5(stg3_inc_val[3]),\n .O(\\lim_state[11]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair365\" *) \n LUT5 #(\n .INIT(32'h00005D55)) \n \\lim_state[12]_i_1 \n (.I0(\\lim_state[12]_i_2_n_0 ),\n .I1(\\lim_state[12]_i_3_n_0 ),\n .I2(stg3_dec2init_val_r),\n .I3(stg3_inc2init_val_r),\n .I4(\\lim_state[12]_i_4_n_0 ),\n .O(\\lim_state[12]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h555F5DDF5DDF5DDF)) \n \\lim_state[12]_i_2 \n (.I0(stg3_dec2init_val_r),\n .I1(\\lim_state[12]_i_5_n_0 ),\n .I2(stg2_tap_cnt_reg__0[5]),\n .I3(\\wl_po_fine_cnt_reg[17] ),\n .I4(stg2_tap_cnt_reg__0[4]),\n .I5(\\byte_r_reg[0] ),\n .O(\\lim_state[12]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000001)) \n \\lim_state[12]_i_3 \n (.I0(\\stg2_tap_cnt_reg[3]_0 [1]),\n .I1(\\stg2_tap_cnt_reg[3]_0 [0]),\n .I2(\\stg2_tap_cnt_reg[3]_0 [2]),\n .I3(stg2_tap_cnt_reg__0[3]),\n .I4(stg2_tap_cnt_reg__0[5]),\n .I5(stg2_tap_cnt_reg__0[4]),\n .O(\\lim_state[12]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFDFFFF)) \n \\lim_state[12]_i_4 \n (.I0(lim_state[11]),\n .I1(wait_cnt_en_r_i_3_n_0),\n .I2(lim_state[0]),\n .I3(lim_state[3]),\n .I4(\\lim_state[13]_i_11_n_0 ),\n .I5(stg2_inc_r_i_2_n_0),\n .O(\\lim_state[12]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h111111FF11F1F1FF)) \n \\lim_state[12]_i_5 \n (.I0(stg2_tap_cnt_reg__0[4]),\n .I1(\\byte_r_reg[0] ),\n .I2(\\stg2_tap_cnt_reg[2]_0 ),\n .I3(\\wl_po_fine_cnt_reg[3] ),\n .I4(stg2_tap_cnt_reg__0[3]),\n .I5(\\lim_state[12]_i_7_n_0 ),\n .O(\\lim_state[12]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair370\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\lim_state[12]_i_7 \n (.I0(\\stg2_tap_cnt_reg[3]_0 [2]),\n .I1(\\wl_po_fine_cnt_reg[14] [1]),\n .O(\\lim_state[12]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFEEEEEEEA)) \n \\lim_state[13]_i_1 \n (.I0(lim_state[13]),\n .I1(\\lim_state[13]_i_3_n_0 ),\n .I2(lim_state[4]),\n .I3(\\lim_state[13]_i_4_n_0 ),\n .I4(\\lim_state[13]_i_5_n_0 ),\n .I5(\\lim_state[13]_i_6_n_0 ),\n .O(lim_nxt_state));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFF4)) \n \\lim_state[13]_i_10 \n (.I0(lim_start_r),\n .I1(lim_start),\n .I2(lim_state[3]),\n .I3(lim_state[2]),\n .I4(lim_state[4]),\n .I5(lim_state[1]),\n .O(\\lim_state[13]_i_10_n_0 ));\n LUT3 #(\n .INIT(8'h01)) \n \\lim_state[13]_i_11 \n (.I0(lim_state[2]),\n .I1(lim_state[4]),\n .I2(lim_state[1]),\n .O(\\lim_state[13]_i_11_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair376\" *) \n LUT3 #(\n .INIT(8'h01)) \n \\lim_state[13]_i_12 \n (.I0(lim_state[9]),\n .I1(lim_state[10]),\n .I2(lim_state[12]),\n .O(\\lim_state[13]_i_12_n_0 ));\n LUT6 #(\n .INIT(64'h00000000EEEEEEFE)) \n \\lim_state[13]_i_13 \n (.I0(lim_state[10]),\n .I1(lim_state[8]),\n .I2(po_rdy),\n .I3(lim2stg3_dec),\n .I4(lim2stg3_inc),\n .I5(\\lim_state[13]_i_14_n_0 ),\n .O(\\lim_state[13]_i_13_n_0 ));\n LUT5 #(\n .INIT(32'h000000FB)) \n \\lim_state[13]_i_14 \n (.I0(lim2stg2_dec),\n .I1(po_rdy),\n .I2(lim2stg2_inc),\n .I3(lim_state[8]),\n .I4(lim_state[9]),\n .O(\\lim_state[13]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'h0001000000000000)) \n \\lim_state[13]_i_2 \n (.I0(\\lim_state[13]_i_7_n_0 ),\n .I1(\\lim_state[13]_i_8_n_0 ),\n .I2(lim_state[1]),\n .I3(lim_state[13]),\n .I4(lim_state[12]),\n .I5(stg3_dec2init_val_r),\n .O(\\lim_state[13]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hAAA8A888AAAAAAAA)) \n \\lim_state[13]_i_3 \n (.I0(\\lim_state[13]_i_9_n_0 ),\n .I1(wait_cnt_done),\n .I2(lim_state[4]),\n .I3(lim_state[1]),\n .I4(lim_state[2]),\n .I5(\\lim_state[4]_i_3_n_0 ),\n .O(\\lim_state[13]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair379\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n \\lim_state[13]_i_4 \n (.I0(lim_state[10]),\n .I1(lim_state[11]),\n .I2(lim_state[8]),\n .I3(lim_state[9]),\n .O(\\lim_state[13]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFEEE)) \n \\lim_state[13]_i_5 \n (.I0(\\lim_state[10]_i_3_n_0 ),\n .I1(lim_state[7]),\n .I2(lim_state[12]),\n .I3(prech_done),\n .I4(lim_state[2]),\n .I5(lim_state[1]),\n .O(\\lim_state[13]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hC8CFCCC0FFF0FFF0)) \n \\lim_state[13]_i_6 \n (.I0(done_r_reg_1),\n .I1(\\lim_state[13]_i_10_n_0 ),\n .I2(lim_state[0]),\n .I3(lim_state[3]),\n .I4(\\lim_state[13]_i_11_n_0 ),\n .I5(\\lim_state[13]_i_12_n_0 ),\n .O(\\lim_state[13]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\lim_state[13]_i_7 \n (.I0(lim_state[8]),\n .I1(lim_state[7]),\n .I2(\\lim_state[10]_i_3_n_0 ),\n .I3(lim_state[4]),\n .I4(lim_state[2]),\n .I5(lim_state[3]),\n .O(\\lim_state[13]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair379\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n \\lim_state[13]_i_8 \n (.I0(lim_state[10]),\n .I1(lim_state[11]),\n .I2(lim_state[0]),\n .I3(lim_state[9]),\n .O(\\lim_state[13]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFEFF)) \n \\lim_state[13]_i_9 \n (.I0(\\lim_state[13]_i_13_n_0 ),\n .I1(lim_state[12]),\n .I2(lim_state[11]),\n .I3(\\lim_state[13]_i_11_n_0 ),\n .I4(lim_state[7]),\n .I5(\\lim_state[10]_i_3_n_0 ),\n .O(\\lim_state[13]_i_9_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair381\" *) \n LUT4 #(\n .INIT(16'h0040)) \n \\lim_state[1]_i_1 \n (.I0(\\lim_state[13]_i_7_n_0 ),\n .I1(\\lim_state[1]_i_2_n_0 ),\n .I2(lim_state[0]),\n .I3(lim_state[1]),\n .O(\\lim_state[1]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h00000001)) \n \\lim_state[1]_i_2 \n (.I0(lim_state[11]),\n .I1(lim_state[10]),\n .I2(lim_state[12]),\n .I3(lim_state[9]),\n .I4(lim_state[13]),\n .O(\\lim_state[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\lim_state[2]_i_1 \n (.I0(\\lim_state[2]_i_2_n_0 ),\n .I1(\\lim_state[2]_i_3_n_0 ),\n .I2(lim_state[6]),\n .I3(lim_state[5]),\n .I4(lim_state[7]),\n .I5(\\lim_state[2]_i_4_n_0 ),\n .O(\\lim_state[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00F000F000F1FFFF)) \n \\lim_state[2]_i_2 \n (.I0(stg3_inc2init_val_r),\n .I1(stg3_init_dec_r),\n .I2(\\lim_state[6]_i_3_n_0 ),\n .I3(lim_state[12]),\n .I4(lim_state[9]),\n .I5(stg3_dec2init_val_r),\n .O(\\lim_state[2]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\lim_state[2]_i_3 \n (.I0(lim_state[0]),\n .I1(lim_state[3]),\n .I2(lim_state[1]),\n .I3(lim_state[2]),\n .O(\\lim_state[2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFEFFFEFFFEFFFFFF)) \n \\lim_state[2]_i_4 \n (.I0(lim_state[10]),\n .I1(lim_state[8]),\n .I2(lim_state[11]),\n .I3(\\lim_state[4]_i_2_n_0 ),\n .I4(lim_state[12]),\n .I5(lim_state[9]),\n .O(\\lim_state[2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h0000000010000000)) \n \\lim_state[3]_i_1 \n (.I0(lim_state[0]),\n .I1(lim_state[1]),\n .I2(\\lim_state[4]_i_2_n_0 ),\n .I3(\\lim_state[4]_i_3_n_0 ),\n .I4(lim_state[2]),\n .I5(lim_state[3]),\n .O(\\lim_state[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000010000000)) \n \\lim_state[4]_i_1 \n (.I0(lim_state[0]),\n .I1(lim_state[1]),\n .I2(\\lim_state[4]_i_2_n_0 ),\n .I3(\\lim_state[4]_i_3_n_0 ),\n .I4(lim_state[3]),\n .I5(lim_state[2]),\n .O(\\lim_state[4]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair369\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\lim_state[4]_i_2 \n (.I0(lim_state[4]),\n .I1(lim_state[13]),\n .O(\\lim_state[4]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h00000001)) \n \\lim_state[4]_i_3 \n (.I0(lim_state[11]),\n .I1(lim_state[10]),\n .I2(lim_state[12]),\n .I3(lim_state[9]),\n .I4(wait_cnt_en_r_i_3_n_0),\n .O(\\lim_state[4]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'h888A)) \n \\lim_state[5]_i_1 \n (.I0(\\lim_state[6]_i_2_n_0 ),\n .I1(\\lim_state[5]_i_2_n_0 ),\n .I2(lim_state[9]),\n .I3(\\lim_state[6]_i_5_n_0 ),\n .O(\\lim_state[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h00000010)) \n \\lim_state[5]_i_2 \n (.I0(lim_state[4]),\n .I1(stg3_init_dec_r),\n .I2(stg3_inc2init_val_r),\n .I3(stg3_dec2init_val_r),\n .I4(\\lim_state[11]_i_6_n_0 ),\n .O(\\lim_state[5]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0002AAAA00020002)) \n \\lim_state[6]_i_1 \n (.I0(\\lim_state[6]_i_2_n_0 ),\n .I1(\\lim_state[6]_i_3_n_0 ),\n .I2(lim_state[4]),\n .I3(\\lim_state[6]_i_4_n_0 ),\n .I4(lim_state[9]),\n .I5(\\lim_state[6]_i_5_n_0 ),\n .O(\\lim_state[6]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h1D1D1D1D1D1D1DFF)) \n \\lim_state[6]_i_10 \n (.I0(\\lim_state[6]_i_14_n_0 ),\n .I1(\\lim_state[6]_i_15_n_0 ),\n .I2(\\lim_state[6]_i_16_n_0 ),\n .I3(\\stg3_tap_cnt_reg_n_0_[4] ),\n .I4(\\stg3_tap_cnt_reg_n_0_[5] ),\n .I5(\\lim_state[6]_i_17_n_0 ),\n .O(\\lim_state[6]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'hD0FD0000FFFFD0FD)) \n \\lim_state[6]_i_11 \n (.I0(\\stg3_tap_cnt_reg_n_0_[0] ),\n .I1(stg3_dec_val[0]),\n .I2(stg3_dec_val[1]),\n .I3(\\stg3_tap_cnt_reg_n_0_[1] ),\n .I4(stg3_dec_val[2]),\n .I5(\\stg3_tap_cnt_reg_n_0_[2] ),\n .O(\\lim_state[6]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'h0D000D00DD0D0D00)) \n \\lim_state[6]_i_12 \n (.I0(\\stg3_tap_cnt_reg[2]_0 [2]),\n .I1(\\stg3_tap_cnt_reg_n_0_[2] ),\n .I2(\\stg3_tap_cnt_reg[2]_0 [1]),\n .I3(\\stg3_tap_cnt_reg_n_0_[1] ),\n .I4(\\stg3_tap_cnt_reg_n_0_[0] ),\n .I5(\\stg3_tap_cnt_reg[2]_0 [0]),\n .O(\\lim_state[6]_i_12_n_0 ));\n LUT4 #(\n .INIT(16'h4F44)) \n \\lim_state[6]_i_13 \n (.I0(\\stg3_tap_cnt_reg_n_0_[4] ),\n .I1(stg3_init_val[4]),\n .I2(\\stg3_tap_cnt_reg_n_0_[3] ),\n .I3(stg3_init_val[3]),\n .O(\\lim_state[6]_i_13_n_0 ));\n LUT4 #(\n .INIT(16'h0002)) \n \\lim_state[6]_i_14 \n (.I0(\\lim_state[6]_i_18_n_0 ),\n .I1(mod_sub_return0_carry__0_n_6),\n .I2(mod_sub_return0_carry__0_n_5),\n .I3(mod_sub_return0_carry__0_n_7),\n .O(\\lim_state[6]_i_14_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair373\" *) \n LUT5 #(\n .INIT(32'h4D44DDDD)) \n \\lim_state[6]_i_15 \n (.I0(\\mmcm_current_reg_n_0_[5] ),\n .I1(\\mmcm_init_trail_reg_n_0_[5] ),\n .I2(\\mmcm_current_reg_n_0_[4] ),\n .I3(\\mmcm_init_trail_reg_n_0_[4] ),\n .I4(\\lim_state[6]_i_19_n_0 ),\n .O(\\lim_state[6]_i_15_n_0 ));\n LUT4 #(\n .INIT(16'h0020)) \n \\lim_state[6]_i_16 \n (.I0(\\lim_state[6]_i_20_n_0 ),\n .I1(mod_sub_return0__14_carry__0_n_7),\n .I2(mod_sub_return0__14_carry__0_n_1),\n .I3(mod_sub_return0__14_carry__0_n_6),\n .O(\\lim_state[6]_i_16_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair374\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n \\lim_state[6]_i_17 \n (.I0(\\stg3_tap_cnt_reg_n_0_[1] ),\n .I1(\\stg3_tap_cnt_reg_n_0_[0] ),\n .I2(\\stg3_tap_cnt_reg_n_0_[2] ),\n .I3(\\stg3_tap_cnt_reg_n_0_[3] ),\n .O(\\lim_state[6]_i_17_n_0 ));\n LUT4 #(\n .INIT(16'h5557)) \n \\lim_state[6]_i_18 \n (.I0(mod_sub_return0_carry_n_4),\n .I1(mod_sub_return0_carry_n_6),\n .I2(mod_sub_return0_carry_n_5),\n .I3(mod_sub_return0_carry_n_7),\n .O(\\lim_state[6]_i_18_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFB000FFB0)) \n \\lim_state[6]_i_19 \n (.I0(\\mmcm_current_reg_n_0_[2] ),\n .I1(\\mmcm_init_trail_reg_n_0_[2] ),\n .I2(\\lim_state[6]_i_21_n_0 ),\n .I3(\\mmcm_current_reg_n_0_[3] ),\n .I4(\\mmcm_init_trail_reg_n_0_[3] ),\n .I5(\\lim_state[6]_i_22_n_0 ),\n .O(\\lim_state[6]_i_19_n_0 ));\n LUT5 #(\n .INIT(32'h11100000)) \n \\lim_state[6]_i_2 \n (.I0(wait_cnt_en_r_i_3_n_0),\n .I1(\\lim_state[2]_i_3_n_0 ),\n .I2(lim_state[4]),\n .I3(lim_state[9]),\n .I4(\\lim_state[6]_i_6_n_0 ),\n .O(\\lim_state[6]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'h5557)) \n \\lim_state[6]_i_20 \n (.I0(mod_sub_return0__14_carry_n_4),\n .I1(mod_sub_return0__14_carry_n_6),\n .I2(mod_sub_return0__14_carry_n_5),\n .I3(\\mmcm_init_trail_reg[0]_0 ),\n .O(\\lim_state[6]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'h40F440F4FFFF40F4)) \n \\lim_state[6]_i_21 \n (.I0(\\mmcm_init_trail_reg_n_0_[0] ),\n .I1(\\mmcm_current_reg_n_0_[0] ),\n .I2(\\mmcm_current_reg_n_0_[1] ),\n .I3(\\mmcm_init_trail_reg_n_0_[1] ),\n .I4(\\mmcm_current_reg_n_0_[2] ),\n .I5(\\mmcm_init_trail_reg_n_0_[2] ),\n .O(\\lim_state[6]_i_21_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair373\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\lim_state[6]_i_22 \n (.I0(\\mmcm_current_reg_n_0_[4] ),\n .I1(\\mmcm_init_trail_reg_n_0_[4] ),\n .O(\\lim_state[6]_i_22_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair390\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\lim_state[6]_i_24 \n (.I0(\\mmcm_init_trail_reg_n_0_[0] ),\n .I1(\\mmcm_current_reg_n_0_[0] ),\n .O(stg3_inc2init_val_r_reg_0));\n LUT4 #(\n .INIT(16'h8A08)) \n \\lim_state[6]_i_3 \n (.I0(stg3_init_dec_r),\n .I1(stg3_dec_val[5]),\n .I2(\\stg3_tap_cnt_reg_n_0_[5] ),\n .I3(\\lim_state[6]_i_7_n_0 ),\n .O(\\lim_state[6]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h1055105510555555)) \n \\lim_state[6]_i_4 \n (.I0(stg3_init_dec_r),\n .I1(\\stg3_tap_cnt_reg_n_0_[5] ),\n .I2(stg3_init_val[5]),\n .I3(stg3_dec2init_val_r),\n .I4(\\lim_state[6]_i_8_n_0 ),\n .I5(\\lim_state[6]_i_9_n_0 ),\n .O(\\lim_state[6]_i_4_n_0 ));\n LUT3 #(\n .INIT(8'hAE)) \n \\lim_state[6]_i_5 \n (.I0(stg3_dec2init_val_r_i_2_n_0),\n .I1(stg3_dec_r),\n .I2(\\lim_state[6]_i_10_n_0 ),\n .O(\\lim_state[6]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair366\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\lim_state[6]_i_6 \n (.I0(lim_state[10]),\n .I1(lim_state[11]),\n .I2(lim_state[13]),\n .I3(lim_state[12]),\n .O(\\lim_state[6]_i_6_n_0 ));\n LUT5 #(\n .INIT(32'hD4DD44D4)) \n \\lim_state[6]_i_7 \n (.I0(\\stg3_tap_cnt_reg_n_0_[4] ),\n .I1(stg3_dec_val[4]),\n .I2(\\lim_state[6]_i_11_n_0 ),\n .I3(\\stg3_tap_cnt_reg_n_0_[3] ),\n .I4(stg3_dec_val[3]),\n .O(\\lim_state[6]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FFFF4F44)) \n \\lim_state[6]_i_8 \n (.I0(stg3_init_val[3]),\n .I1(\\stg3_tap_cnt_reg_n_0_[3] ),\n .I2(\\stg3_tap_cnt_reg[2]_0 [2]),\n .I3(\\stg3_tap_cnt_reg_n_0_[2] ),\n .I4(\\lim_state[6]_i_12_n_0 ),\n .I5(\\lim_state[6]_i_13_n_0 ),\n .O(\\lim_state[6]_i_8_n_0 ));\n LUT4 #(\n .INIT(16'h4F44)) \n \\lim_state[6]_i_9 \n (.I0(stg3_init_val[4]),\n .I1(\\stg3_tap_cnt_reg_n_0_[4] ),\n .I2(stg3_init_val[5]),\n .I3(\\stg3_tap_cnt_reg_n_0_[5] ),\n .O(\\lim_state[6]_i_9_n_0 ));\n LUT5 #(\n .INIT(32'h0000888A)) \n \\lim_state[7]_i_1 \n (.I0(\\lim_state[12]_i_2_n_0 ),\n .I1(stg3_dec2init_val_r),\n .I2(\\lim_state[7]_i_2_n_0 ),\n .I3(stg3_inc2init_val_r),\n .I4(\\lim_state[12]_i_4_n_0 ),\n .O(\\lim_state[7]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h55555555D5555555)) \n \\lim_state[7]_i_2 \n (.I0(stg2_inc_r),\n .I1(stg2_tap_cnt_reg__0[5]),\n .I2(stg2_tap_cnt_reg__0[4]),\n .I3(\\stg2_tap_cnt_reg[3]_0 [1]),\n .I4(\\stg2_tap_cnt_reg[3]_0 [0]),\n .I5(\\lim_state[7]_i_3_n_0 ),\n .O(\\lim_state[7]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair364\" *) \n LUT2 #(\n .INIT(4'h7)) \n \\lim_state[7]_i_3 \n (.I0(\\stg2_tap_cnt_reg[3]_0 [2]),\n .I1(stg2_tap_cnt_reg__0[3]),\n .O(\\lim_state[7]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair365\" *) \n LUT4 #(\n .INIT(16'h0004)) \n \\lim_state[8]_i_1 \n (.I0(\\lim_state[12]_i_4_n_0 ),\n .I1(stg3_inc2init_val_r),\n .I2(stg3_dec2init_val_r),\n .I3(\\lim_state[12]_i_3_n_0 ),\n .O(\\lim_state[8]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h17001400)) \n \\lim_state[9]_i_1 \n (.I0(lim_state[11]),\n .I1(lim_state[5]),\n .I2(lim_state[6]),\n .I3(\\lim_state[9]_i_2_n_0 ),\n .I4(\\lim_state[9]_i_3_n_0 ),\n .O(\\lim_state[9]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h00000001)) \n \\lim_state[9]_i_2 \n (.I0(stg2_inc_r_i_2_n_0),\n .I1(lim_state[4]),\n .I2(lim_state[8]),\n .I3(lim_state[7]),\n .I4(\\lim_state[2]_i_3_n_0 ),\n .O(\\lim_state[9]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair383\" *) \n LUT4 #(\n .INIT(16'h0200)) \n \\lim_state[9]_i_3 \n (.I0(\\lim_state[7]_i_2_n_0 ),\n .I1(stg3_dec2init_val_r),\n .I2(stg3_inc2init_val_r),\n .I3(lim_state[11]),\n .O(\\lim_state[9]_i_3_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\lim_state_reg[0] \n (.C(CLK),\n .CE(lim_nxt_state),\n .D(\\lim_state[0]_i_1_n_0 ),\n .Q(lim_state[0]),\n .S(rstdiv0_sync_r1_reg_rep__10));\n FDRE #(\n .INIT(1'b0)) \n \\lim_state_reg[10] \n (.C(CLK),\n .CE(lim_nxt_state),\n .D(\\lim_state[10]_i_1_n_0 ),\n .Q(lim_state[10]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE #(\n .INIT(1'b0)) \n \\lim_state_reg[11] \n (.C(CLK),\n .CE(lim_nxt_state),\n .D(\\lim_state[11]_i_1_n_0 ),\n .Q(lim_state[11]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE #(\n .INIT(1'b0)) \n \\lim_state_reg[12] \n (.C(CLK),\n .CE(lim_nxt_state),\n .D(\\lim_state[12]_i_1_n_0 ),\n .Q(lim_state[12]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE #(\n .INIT(1'b0)) \n \\lim_state_reg[13] \n (.C(CLK),\n .CE(lim_nxt_state),\n .D(\\lim_state[13]_i_2_n_0 ),\n .Q(lim_state[13]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE #(\n .INIT(1'b0)) \n \\lim_state_reg[1] \n (.C(CLK),\n .CE(lim_nxt_state),\n .D(\\lim_state[1]_i_1_n_0 ),\n .Q(lim_state[1]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE #(\n .INIT(1'b0)) \n \\lim_state_reg[2] \n (.C(CLK),\n .CE(lim_nxt_state),\n .D(\\lim_state[2]_i_1_n_0 ),\n .Q(lim_state[2]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE #(\n .INIT(1'b0)) \n \\lim_state_reg[3] \n (.C(CLK),\n .CE(lim_nxt_state),\n .D(\\lim_state[3]_i_1_n_0 ),\n .Q(lim_state[3]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE #(\n .INIT(1'b0)) \n \\lim_state_reg[4] \n (.C(CLK),\n .CE(lim_nxt_state),\n .D(\\lim_state[4]_i_1_n_0 ),\n .Q(lim_state[4]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE #(\n .INIT(1'b0)) \n \\lim_state_reg[5] \n (.C(CLK),\n .CE(lim_nxt_state),\n .D(\\lim_state[5]_i_1_n_0 ),\n .Q(lim_state[5]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE #(\n .INIT(1'b0)) \n \\lim_state_reg[6] \n (.C(CLK),\n .CE(lim_nxt_state),\n .D(\\lim_state[6]_i_1_n_0 ),\n .Q(lim_state[6]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE #(\n .INIT(1'b0)) \n \\lim_state_reg[7] \n (.C(CLK),\n .CE(lim_nxt_state),\n .D(\\lim_state[7]_i_1_n_0 ),\n .Q(lim_state[7]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE #(\n .INIT(1'b0)) \n \\lim_state_reg[8] \n (.C(CLK),\n .CE(lim_nxt_state),\n .D(\\lim_state[8]_i_1_n_0 ),\n .Q(lim_state[8]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE #(\n .INIT(1'b0)) \n \\lim_state_reg[9] \n (.C(CLK),\n .CE(lim_nxt_state),\n .D(\\lim_state[9]_i_1_n_0 ),\n .Q(lim_state[9]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\mmcm_current[0]_i_1 \n (.I0(\\mmcm_current[0]_i_2_n_0 ),\n .I1(stg3_dec_r),\n .I2(\\mmcm_init_lead_reg_n_0_[0] ),\n .I3(\\mmcm_init_lead[5]_i_2_n_0 ),\n .I4(Q[0]),\n .O(\\mmcm_current[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair384\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mmcm_current[0]_i_2 \n (.I0(\\mmcm_init_trail_reg_n_0_[0] ),\n .I1(\\mmcm_init_trail[5]_i_2_n_0 ),\n .I2(\\rise_lead_r_reg[5] [0]),\n .O(\\mmcm_current[0]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\mmcm_current[1]_i_1 \n (.I0(\\mmcm_current[1]_i_2_n_0 ),\n .I1(stg3_dec_r),\n .I2(\\mmcm_init_lead_reg_n_0_[1] ),\n .I3(\\mmcm_init_lead[5]_i_2_n_0 ),\n .I4(Q[1]),\n .O(\\mmcm_current[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair385\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mmcm_current[1]_i_2 \n (.I0(\\mmcm_init_trail_reg_n_0_[1] ),\n .I1(\\mmcm_init_trail[5]_i_2_n_0 ),\n .I2(\\rise_lead_r_reg[5] [1]),\n .O(\\mmcm_current[1]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\mmcm_current[2]_i_1 \n (.I0(\\mmcm_current[2]_i_2_n_0 ),\n .I1(stg3_dec_r),\n .I2(\\mmcm_init_lead_reg_n_0_[2] ),\n .I3(\\mmcm_init_lead[5]_i_2_n_0 ),\n .I4(Q[2]),\n .O(\\mmcm_current[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair386\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mmcm_current[2]_i_2 \n (.I0(\\mmcm_init_trail_reg_n_0_[2] ),\n .I1(\\mmcm_init_trail[5]_i_2_n_0 ),\n .I2(\\rise_lead_r_reg[5] [2]),\n .O(\\mmcm_current[2]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\mmcm_current[3]_i_1 \n (.I0(\\mmcm_current[3]_i_2_n_0 ),\n .I1(stg3_dec_r),\n .I2(\\mmcm_init_lead_reg_n_0_[3] ),\n .I3(\\mmcm_init_lead[5]_i_2_n_0 ),\n .I4(Q[3]),\n .O(\\mmcm_current[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair384\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mmcm_current[3]_i_2 \n (.I0(\\mmcm_init_trail_reg_n_0_[3] ),\n .I1(\\mmcm_init_trail[5]_i_2_n_0 ),\n .I2(\\rise_lead_r_reg[5] [3]),\n .O(\\mmcm_current[3]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\mmcm_current[4]_i_1 \n (.I0(\\mmcm_current[4]_i_2_n_0 ),\n .I1(stg3_dec_r),\n .I2(\\mmcm_init_lead_reg_n_0_[4] ),\n .I3(\\mmcm_init_lead[5]_i_2_n_0 ),\n .I4(Q[4]),\n .O(\\mmcm_current[4]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair385\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mmcm_current[4]_i_2 \n (.I0(\\mmcm_init_trail_reg_n_0_[4] ),\n .I1(\\mmcm_init_trail[5]_i_2_n_0 ),\n .I2(\\rise_lead_r_reg[5] [4]),\n .O(\\mmcm_current[4]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\mmcm_current[5]_i_1 \n (.I0(\\mmcm_current[5]_i_2_n_0 ),\n .I1(stg3_dec_r),\n .I2(\\mmcm_init_lead_reg_n_0_[5] ),\n .I3(\\mmcm_init_lead[5]_i_2_n_0 ),\n .I4(Q[5]),\n .O(\\mmcm_current[5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair386\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mmcm_current[5]_i_2 \n (.I0(\\mmcm_init_trail_reg_n_0_[5] ),\n .I1(\\mmcm_init_trail[5]_i_2_n_0 ),\n .I2(\\rise_lead_r_reg[5] [5]),\n .O(\\mmcm_current[5]_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\mmcm_current_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mmcm_current[0]_i_1_n_0 ),\n .Q(\\mmcm_current_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE #(\n .INIT(1'b0)) \n \\mmcm_current_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mmcm_current[1]_i_1_n_0 ),\n .Q(\\mmcm_current_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE #(\n .INIT(1'b0)) \n \\mmcm_current_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mmcm_current[2]_i_1_n_0 ),\n .Q(\\mmcm_current_reg_n_0_[2] ),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE #(\n .INIT(1'b0)) \n \\mmcm_current_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mmcm_current[3]_i_1_n_0 ),\n .Q(\\mmcm_current_reg_n_0_[3] ),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE #(\n .INIT(1'b0)) \n \\mmcm_current_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mmcm_current[4]_i_1_n_0 ),\n .Q(\\mmcm_current_reg_n_0_[4] ),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE #(\n .INIT(1'b0)) \n \\mmcm_current_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mmcm_current[5]_i_1_n_0 ),\n .Q(\\mmcm_current_reg_n_0_[5] ),\n .R(rstdiv0_sync_r1_reg_rep__10));\n LUT3 #(\n .INIT(8'h20)) \n \\mmcm_init_lead[5]_i_1 \n (.I0(\\mmcm_init_lead[5]_i_2_n_0 ),\n .I1(detect_done_r),\n .I2(done_r_reg_1),\n .O(mmcm_init_lead));\n LUT4 #(\n .INIT(16'h0004)) \n \\mmcm_init_lead[5]_i_2 \n (.I0(\\mmcm_init_lead[5]_i_3_n_0 ),\n .I1(\\mmcm_init_lead[5]_i_4_n_0 ),\n .I2(\\mmcm_init_lead[5]_i_5_n_0 ),\n .I3(\\mmcm_init_lead[5]_i_6_n_0 ),\n .O(\\mmcm_init_lead[5]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'h4F44)) \n \\mmcm_init_lead[5]_i_3 \n (.I0(\\stg3_tap_cnt_reg_n_0_[4] ),\n .I1(stg3_inc_val[4]),\n .I2(\\stg3_tap_cnt_reg_n_0_[5] ),\n .I3(stg3_inc_val[5]),\n .O(\\mmcm_init_lead[5]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'hD0DD)) \n \\mmcm_init_lead[5]_i_4 \n (.I0(stg3_inc_val[1]),\n .I1(\\stg3_tap_cnt_reg_n_0_[1] ),\n .I2(\\stg3_tap_cnt_reg_n_0_[0] ),\n .I3(stg3_inc_val[0]),\n .O(\\mmcm_init_lead[5]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h5D5DFF5D)) \n \\mmcm_init_lead[5]_i_5 \n (.I0(\\mmcm_init_lead[5]_i_7_n_0 ),\n .I1(\\stg3_tap_cnt_reg_n_0_[5] ),\n .I2(stg3_inc_val[5]),\n .I3(\\stg3_tap_cnt_reg_n_0_[0] ),\n .I4(stg3_inc_val[0]),\n .O(\\mmcm_init_lead[5]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'h22F2FFFF)) \n \\mmcm_init_lead[5]_i_6 \n (.I0(\\stg3_tap_cnt_reg_n_0_[1] ),\n .I1(stg3_inc_val[1]),\n .I2(\\stg3_tap_cnt_reg_n_0_[2] ),\n .I3(stg3_inc_val[2]),\n .I4(\\mmcm_init_lead[5]_i_8_n_0 ),\n .O(\\mmcm_init_lead[5]_i_6_n_0 ));\n LUT4 #(\n .INIT(16'hD0DD)) \n \\mmcm_init_lead[5]_i_7 \n (.I0(stg3_inc_val[3]),\n .I1(\\stg3_tap_cnt_reg_n_0_[3] ),\n .I2(\\stg3_tap_cnt_reg_n_0_[2] ),\n .I3(stg3_inc_val[2]),\n .O(\\mmcm_init_lead[5]_i_7_n_0 ));\n LUT4 #(\n .INIT(16'hD0DD)) \n \\mmcm_init_lead[5]_i_8 \n (.I0(\\stg3_tap_cnt_reg_n_0_[4] ),\n .I1(stg3_inc_val[4]),\n .I2(stg3_inc_val[3]),\n .I3(\\stg3_tap_cnt_reg_n_0_[3] ),\n .O(\\mmcm_init_lead[5]_i_8_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\mmcm_init_lead_reg[0] \n (.C(CLK),\n .CE(mmcm_init_lead),\n .D(\\rise_lead_r_reg[5] [0]),\n .Q(\\mmcm_init_lead_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE #(\n .INIT(1'b0)) \n \\mmcm_init_lead_reg[1] \n (.C(CLK),\n .CE(mmcm_init_lead),\n .D(\\rise_lead_r_reg[5] [1]),\n .Q(\\mmcm_init_lead_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE #(\n .INIT(1'b0)) \n \\mmcm_init_lead_reg[2] \n (.C(CLK),\n .CE(mmcm_init_lead),\n .D(\\rise_lead_r_reg[5] [2]),\n .Q(\\mmcm_init_lead_reg_n_0_[2] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE #(\n .INIT(1'b0)) \n \\mmcm_init_lead_reg[3] \n (.C(CLK),\n .CE(mmcm_init_lead),\n .D(\\rise_lead_r_reg[5] [3]),\n .Q(\\mmcm_init_lead_reg_n_0_[3] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE #(\n .INIT(1'b0)) \n \\mmcm_init_lead_reg[4] \n (.C(CLK),\n .CE(mmcm_init_lead),\n .D(\\rise_lead_r_reg[5] [4]),\n .Q(\\mmcm_init_lead_reg_n_0_[4] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE #(\n .INIT(1'b0)) \n \\mmcm_init_lead_reg[5] \n (.C(CLK),\n .CE(mmcm_init_lead),\n .D(\\rise_lead_r_reg[5] [5]),\n .Q(\\mmcm_init_lead_reg_n_0_[5] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n LUT3 #(\n .INIT(8'h40)) \n \\mmcm_init_trail[5]_i_1 \n (.I0(detect_done_r),\n .I1(done_r_reg_1),\n .I2(\\mmcm_init_trail[5]_i_2_n_0 ),\n .O(mmcm_init_trail));\n LUT6 #(\n .INIT(64'h0000000009000009)) \n \\mmcm_init_trail[5]_i_2 \n (.I0(stg3_dec_val[5]),\n .I1(\\stg3_tap_cnt_reg_n_0_[5] ),\n .I2(\\mmcm_init_trail[5]_i_3_n_0 ),\n .I3(\\stg3_tap_cnt_reg_n_0_[3] ),\n .I4(stg3_dec_val[3]),\n .I5(\\mmcm_init_trail[5]_i_4_n_0 ),\n .O(\\mmcm_init_trail[5]_i_2_n_0 ));\n LUT2 #(\n .INIT(4'h6)) \n \\mmcm_init_trail[5]_i_3 \n (.I0(\\stg3_tap_cnt_reg_n_0_[4] ),\n .I1(stg3_dec_val[4]),\n .O(\\mmcm_init_trail[5]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\mmcm_init_trail[5]_i_4 \n (.I0(\\stg3_tap_cnt_reg_n_0_[1] ),\n .I1(stg3_dec_val[1]),\n .I2(\\stg3_tap_cnt_reg_n_0_[2] ),\n .I3(stg3_dec_val[2]),\n .I4(stg3_dec_val[0]),\n .I5(\\stg3_tap_cnt_reg_n_0_[0] ),\n .O(\\mmcm_init_trail[5]_i_4_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\mmcm_init_trail_reg[0] \n (.C(CLK),\n .CE(mmcm_init_trail),\n .D(Q[0]),\n .Q(\\mmcm_init_trail_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE #(\n .INIT(1'b0)) \n \\mmcm_init_trail_reg[1] \n (.C(CLK),\n .CE(mmcm_init_trail),\n .D(Q[1]),\n .Q(\\mmcm_init_trail_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE #(\n .INIT(1'b0)) \n \\mmcm_init_trail_reg[2] \n (.C(CLK),\n .CE(mmcm_init_trail),\n .D(Q[2]),\n .Q(\\mmcm_init_trail_reg_n_0_[2] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE #(\n .INIT(1'b0)) \n \\mmcm_init_trail_reg[3] \n (.C(CLK),\n .CE(mmcm_init_trail),\n .D(Q[3]),\n .Q(\\mmcm_init_trail_reg_n_0_[3] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE #(\n .INIT(1'b0)) \n \\mmcm_init_trail_reg[4] \n (.C(CLK),\n .CE(mmcm_init_trail),\n .D(Q[4]),\n .Q(\\mmcm_init_trail_reg_n_0_[4] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE #(\n .INIT(1'b0)) \n \\mmcm_init_trail_reg[5] \n (.C(CLK),\n .CE(mmcm_init_trail),\n .D(Q[5]),\n .Q(\\mmcm_init_trail_reg_n_0_[5] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n CARRY4 mod_sub0_return0__14_carry\n (.CI(1'b0),\n .CO({mod_sub0_return0__14_carry_n_0,mod_sub0_return0__14_carry_n_1,mod_sub0_return0__14_carry_n_2,mod_sub0_return0__14_carry_n_3}),\n .CYINIT(1'b1),\n .DI({\\mmcm_current_reg_n_0_[3] ,\\mmcm_current_reg_n_0_[2] ,\\mmcm_current_reg_n_0_[1] ,\\mmcm_current_reg_n_0_[0] }),\n .O({mod_sub0_return0__14_carry_n_4,mod_sub0_return0__14_carry_n_5,mod_sub0_return0__14_carry_n_6,NLW_mod_sub0_return0__14_carry_O_UNCONNECTED[0]}),\n .S({mod_sub0_return0__14_carry_i_1_n_0,mod_sub0_return0__14_carry_i_2_n_0,mod_sub0_return0__14_carry_i_3_n_0,mod_sub0_return0__14_carry_i_4_n_0}));\n CARRY4 mod_sub0_return0__14_carry__0\n (.CI(mod_sub0_return0__14_carry_n_0),\n .CO({NLW_mod_sub0_return0__14_carry__0_CO_UNCONNECTED[3],mod_sub0_return0__14_carry__0_n_1,NLW_mod_sub0_return0__14_carry__0_CO_UNCONNECTED[1],mod_sub0_return0__14_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,\\mmcm_current_reg_n_0_[5] ,\\mmcm_current_reg_n_0_[4] }),\n .O({NLW_mod_sub0_return0__14_carry__0_O_UNCONNECTED[3:2],mod_sub0_return0__14_carry__0_n_6,mod_sub0_return0__14_carry__0_n_7}),\n .S({1'b0,1'b1,mod_sub0_return0__14_carry__0_i_1_n_0,mod_sub0_return0__14_carry__0_i_2_n_0}));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub0_return0__14_carry__0_i_1\n (.I0(\\mmcm_current_reg_n_0_[5] ),\n .I1(\\mmcm_init_lead_reg_n_0_[5] ),\n .O(mod_sub0_return0__14_carry__0_i_1_n_0));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub0_return0__14_carry__0_i_2\n (.I0(\\mmcm_current_reg_n_0_[4] ),\n .I1(\\mmcm_init_lead_reg_n_0_[4] ),\n .O(mod_sub0_return0__14_carry__0_i_2_n_0));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub0_return0__14_carry_i_1\n (.I0(\\mmcm_current_reg_n_0_[3] ),\n .I1(\\mmcm_init_lead_reg_n_0_[3] ),\n .O(mod_sub0_return0__14_carry_i_1_n_0));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub0_return0__14_carry_i_2\n (.I0(\\mmcm_current_reg_n_0_[2] ),\n .I1(\\mmcm_init_lead_reg_n_0_[2] ),\n .O(mod_sub0_return0__14_carry_i_2_n_0));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub0_return0__14_carry_i_3\n (.I0(\\mmcm_current_reg_n_0_[1] ),\n .I1(\\mmcm_init_lead_reg_n_0_[1] ),\n .O(mod_sub0_return0__14_carry_i_3_n_0));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub0_return0__14_carry_i_4\n (.I0(\\mmcm_current_reg_n_0_[0] ),\n .I1(\\mmcm_init_lead_reg_n_0_[0] ),\n .O(mod_sub0_return0__14_carry_i_4_n_0));\n CARRY4 mod_sub0_return0_carry\n (.CI(1'b0),\n .CO({mod_sub0_return0_carry_n_0,mod_sub0_return0_carry_n_1,mod_sub0_return0_carry_n_2,mod_sub0_return0_carry_n_3}),\n .CYINIT(1'b1),\n .DI({\\mmcm_init_lead_reg_n_0_[3] ,\\mmcm_current_reg_n_0_[2] ,\\mmcm_current_reg_n_0_[1] ,\\mmcm_current_reg_n_0_[0] }),\n .O({mod_sub0_return0_carry_n_4,mod_sub0_return0_carry_n_5,mod_sub0_return0_carry_n_6,mod_sub0_return0_carry_n_7}),\n .S({mod_sub0_return0_carry_i_1_n_0,mod_sub0_return0_carry_i_2_n_0,mod_sub0_return0_carry_i_3_n_0,mod_sub0_return0_carry_i_4_n_0}));\n CARRY4 mod_sub0_return0_carry__0\n (.CI(mod_sub0_return0_carry_n_0),\n .CO({NLW_mod_sub0_return0_carry__0_CO_UNCONNECTED[3:2],mod_sub0_return0_carry__0_n_2,mod_sub0_return0_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,mod_sub0_return0_carry__0_i_1_n_0,mod_sub0_return0_carry__0_i_2_n_0}),\n .O({NLW_mod_sub0_return0_carry__0_O_UNCONNECTED[3],mod_sub0_return0_carry__0_n_5,mod_sub0_return0_carry__0_n_6,mod_sub0_return0_carry__0_n_7}),\n .S({1'b0,mod_sub0_return0_carry__0_i_3_n_0,mod_sub0_return0_carry__0_i_4_n_0,mod_sub0_return0_carry__0_i_5_n_0}));\n LUT2 #(\n .INIT(4'hB)) \n mod_sub0_return0_carry__0_i_1\n (.I0(\\mmcm_current_reg_n_0_[4] ),\n .I1(\\mmcm_init_lead_reg_n_0_[4] ),\n .O(mod_sub0_return0_carry__0_i_1_n_0));\n LUT2 #(\n .INIT(4'h6)) \n mod_sub0_return0_carry__0_i_2\n (.I0(\\mmcm_init_lead_reg_n_0_[4] ),\n .I1(\\mmcm_current_reg_n_0_[4] ),\n .O(mod_sub0_return0_carry__0_i_2_n_0));\n LUT2 #(\n .INIT(4'h2)) \n mod_sub0_return0_carry__0_i_3\n (.I0(\\mmcm_init_lead_reg_n_0_[5] ),\n .I1(\\mmcm_current_reg_n_0_[5] ),\n .O(mod_sub0_return0_carry__0_i_3_n_0));\n LUT4 #(\n .INIT(16'hB44B)) \n mod_sub0_return0_carry__0_i_4\n (.I0(\\mmcm_current_reg_n_0_[4] ),\n .I1(\\mmcm_init_lead_reg_n_0_[4] ),\n .I2(\\mmcm_init_lead_reg_n_0_[5] ),\n .I3(\\mmcm_current_reg_n_0_[5] ),\n .O(mod_sub0_return0_carry__0_i_4_n_0));\n LUT3 #(\n .INIT(8'h69)) \n mod_sub0_return0_carry__0_i_5\n (.I0(\\mmcm_init_lead_reg_n_0_[4] ),\n .I1(\\mmcm_current_reg_n_0_[4] ),\n .I2(\\mmcm_init_lead_reg_n_0_[3] ),\n .O(mod_sub0_return0_carry__0_i_5_n_0));\n LUT2 #(\n .INIT(4'h6)) \n mod_sub0_return0_carry_i_1\n (.I0(\\mmcm_init_lead_reg_n_0_[3] ),\n .I1(\\mmcm_current_reg_n_0_[3] ),\n .O(mod_sub0_return0_carry_i_1_n_0));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub0_return0_carry_i_2\n (.I0(\\mmcm_current_reg_n_0_[2] ),\n .I1(\\mmcm_init_lead_reg_n_0_[2] ),\n .O(mod_sub0_return0_carry_i_2_n_0));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub0_return0_carry_i_3\n (.I0(\\mmcm_current_reg_n_0_[1] ),\n .I1(\\mmcm_init_lead_reg_n_0_[1] ),\n .O(mod_sub0_return0_carry_i_3_n_0));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub0_return0_carry_i_4\n (.I0(\\mmcm_current_reg_n_0_[0] ),\n .I1(\\mmcm_init_lead_reg_n_0_[0] ),\n .O(mod_sub0_return0_carry_i_4_n_0));\n CARRY4 mod_sub_return0__14_carry\n (.CI(1'b0),\n .CO({mod_sub_return0__14_carry_n_0,mod_sub_return0__14_carry_n_1,mod_sub_return0__14_carry_n_2,mod_sub_return0__14_carry_n_3}),\n .CYINIT(1'b1),\n .DI({\\mmcm_init_trail_reg_n_0_[3] ,\\mmcm_init_trail_reg_n_0_[2] ,\\mmcm_init_trail_reg_n_0_[1] ,\\mmcm_init_trail_reg_n_0_[0] }),\n .O({mod_sub_return0__14_carry_n_4,mod_sub_return0__14_carry_n_5,mod_sub_return0__14_carry_n_6,NLW_mod_sub_return0__14_carry_O_UNCONNECTED[0]}),\n .S({mod_sub_return0__14_carry_i_1_n_0,mod_sub_return0__14_carry_i_2_n_0,mod_sub_return0__14_carry_i_3_n_0,mod_sub_return0__14_carry_i_4_n_0}));\n CARRY4 mod_sub_return0__14_carry__0\n (.CI(mod_sub_return0__14_carry_n_0),\n .CO({NLW_mod_sub_return0__14_carry__0_CO_UNCONNECTED[3],mod_sub_return0__14_carry__0_n_1,NLW_mod_sub_return0__14_carry__0_CO_UNCONNECTED[1],mod_sub_return0__14_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,\\mmcm_init_trail_reg_n_0_[5] ,\\mmcm_init_trail_reg_n_0_[4] }),\n .O({NLW_mod_sub_return0__14_carry__0_O_UNCONNECTED[3:2],mod_sub_return0__14_carry__0_n_6,mod_sub_return0__14_carry__0_n_7}),\n .S({1'b0,1'b1,mod_sub_return0__14_carry__0_i_1_n_0,mod_sub_return0__14_carry__0_i_2_n_0}));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub_return0__14_carry__0_i_1\n (.I0(\\mmcm_init_trail_reg_n_0_[5] ),\n .I1(\\mmcm_current_reg_n_0_[5] ),\n .O(mod_sub_return0__14_carry__0_i_1_n_0));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub_return0__14_carry__0_i_2\n (.I0(\\mmcm_init_trail_reg_n_0_[4] ),\n .I1(\\mmcm_current_reg_n_0_[4] ),\n .O(mod_sub_return0__14_carry__0_i_2_n_0));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub_return0__14_carry_i_1\n (.I0(\\mmcm_init_trail_reg_n_0_[3] ),\n .I1(\\mmcm_current_reg_n_0_[3] ),\n .O(mod_sub_return0__14_carry_i_1_n_0));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub_return0__14_carry_i_2\n (.I0(\\mmcm_init_trail_reg_n_0_[2] ),\n .I1(\\mmcm_current_reg_n_0_[2] ),\n .O(mod_sub_return0__14_carry_i_2_n_0));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub_return0__14_carry_i_3\n (.I0(\\mmcm_init_trail_reg_n_0_[1] ),\n .I1(\\mmcm_current_reg_n_0_[1] ),\n .O(mod_sub_return0__14_carry_i_3_n_0));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub_return0__14_carry_i_4\n (.I0(\\mmcm_init_trail_reg_n_0_[0] ),\n .I1(\\mmcm_current_reg_n_0_[0] ),\n .O(mod_sub_return0__14_carry_i_4_n_0));\n CARRY4 mod_sub_return0_carry\n (.CI(1'b0),\n .CO({mod_sub_return0_carry_n_0,mod_sub_return0_carry_n_1,mod_sub_return0_carry_n_2,mod_sub_return0_carry_n_3}),\n .CYINIT(1'b1),\n .DI({\\mmcm_current_reg_n_0_[3] ,\\mmcm_init_trail_reg_n_0_[2] ,\\mmcm_init_trail_reg_n_0_[1] ,\\mmcm_init_trail_reg_n_0_[0] }),\n .O({mod_sub_return0_carry_n_4,mod_sub_return0_carry_n_5,mod_sub_return0_carry_n_6,mod_sub_return0_carry_n_7}),\n .S({mod_sub_return0_carry_i_1__0_n_0,mod_sub_return0_carry_i_2_n_0,mod_sub_return0_carry_i_3_n_0,mod_sub_return0_carry_i_4_n_0}));\n CARRY4 mod_sub_return0_carry__0\n (.CI(mod_sub_return0_carry_n_0),\n .CO({NLW_mod_sub_return0_carry__0_CO_UNCONNECTED[3:2],mod_sub_return0_carry__0_n_2,mod_sub_return0_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,mod_sub_return0_carry__0_i_1__0_n_0,mod_sub_return0_carry__0_i_2_n_0}),\n .O({NLW_mod_sub_return0_carry__0_O_UNCONNECTED[3],mod_sub_return0_carry__0_n_5,mod_sub_return0_carry__0_n_6,mod_sub_return0_carry__0_n_7}),\n .S({1'b0,mod_sub_return0_carry__0_i_3_n_0,mod_sub_return0_carry__0_i_4_n_0,mod_sub_return0_carry__0_i_5_n_0}));\n LUT2 #(\n .INIT(4'hB)) \n mod_sub_return0_carry__0_i_1__0\n (.I0(\\mmcm_init_trail_reg_n_0_[4] ),\n .I1(\\mmcm_current_reg_n_0_[4] ),\n .O(mod_sub_return0_carry__0_i_1__0_n_0));\n LUT2 #(\n .INIT(4'h6)) \n mod_sub_return0_carry__0_i_2\n (.I0(\\mmcm_current_reg_n_0_[4] ),\n .I1(\\mmcm_init_trail_reg_n_0_[4] ),\n .O(mod_sub_return0_carry__0_i_2_n_0));\n LUT2 #(\n .INIT(4'h2)) \n mod_sub_return0_carry__0_i_3\n (.I0(\\mmcm_current_reg_n_0_[5] ),\n .I1(\\mmcm_init_trail_reg_n_0_[5] ),\n .O(mod_sub_return0_carry__0_i_3_n_0));\n LUT4 #(\n .INIT(16'hB44B)) \n mod_sub_return0_carry__0_i_4\n (.I0(\\mmcm_init_trail_reg_n_0_[4] ),\n .I1(\\mmcm_current_reg_n_0_[4] ),\n .I2(\\mmcm_current_reg_n_0_[5] ),\n .I3(\\mmcm_init_trail_reg_n_0_[5] ),\n .O(mod_sub_return0_carry__0_i_4_n_0));\n LUT3 #(\n .INIT(8'h69)) \n mod_sub_return0_carry__0_i_5\n (.I0(\\mmcm_current_reg_n_0_[4] ),\n .I1(\\mmcm_init_trail_reg_n_0_[4] ),\n .I2(\\mmcm_current_reg_n_0_[3] ),\n .O(mod_sub_return0_carry__0_i_5_n_0));\n LUT2 #(\n .INIT(4'h6)) \n mod_sub_return0_carry_i_1__0\n (.I0(\\mmcm_current_reg_n_0_[3] ),\n .I1(\\mmcm_init_trail_reg_n_0_[3] ),\n .O(mod_sub_return0_carry_i_1__0_n_0));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub_return0_carry_i_2\n (.I0(\\mmcm_init_trail_reg_n_0_[2] ),\n .I1(\\mmcm_current_reg_n_0_[2] ),\n .O(mod_sub_return0_carry_i_2_n_0));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub_return0_carry_i_3\n (.I0(\\mmcm_init_trail_reg_n_0_[1] ),\n .I1(\\mmcm_current_reg_n_0_[1] ),\n .O(mod_sub_return0_carry_i_3_n_0));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub_return0_carry_i_4\n (.I0(\\mmcm_init_trail_reg_n_0_[0] ),\n .I1(\\mmcm_current_reg_n_0_[0] ),\n .O(mod_sub_return0_carry_i_4_n_0));\n LUT4 #(\n .INIT(16'h8A88)) \n oclkdelay_center_calib_start_r_i_2\n (.I0(scanning_right),\n .I1(o2f_r_reg),\n .I2(oclkdelay_center_calib_start_r_i_3_n_0),\n .I3(oclkdelay_center_calib_start_r_i_4_n_0),\n .O(oclkdelay_center_calib_start_r_reg));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n oclkdelay_center_calib_start_r_i_3\n (.I0(oclkdelay_center_calib_start_r_reg_0[2]),\n .I1(\\stg3_r_reg[5] [2]),\n .I2(oclkdelay_center_calib_start_r_reg_0[1]),\n .I3(\\stg3_r_reg[5] [1]),\n .I4(\\stg3_r_reg[5] [0]),\n .I5(oclkdelay_center_calib_start_r_reg_0[0]),\n .O(oclkdelay_center_calib_start_r_i_3_n_0));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n oclkdelay_center_calib_start_r_i_4\n (.I0(oclkdelay_center_calib_start_r_reg_0[5]),\n .I1(\\stg3_r_reg[5] [5]),\n .I2(oclkdelay_center_calib_start_r_reg_0[4]),\n .I3(\\stg3_r_reg[5] [4]),\n .I4(oclkdelay_center_calib_start_r_reg_0[3]),\n .I5(\\stg3_r_reg[5] [3]),\n .O(oclkdelay_center_calib_start_r_i_4_n_0));\n LUT5 #(\n .INIT(32'h55555554)) \n po_stg23_sel_r_i_1\n (.I0(rstdiv0_sync_r1_reg_rep__25),\n .I1(\\po_wait_r_reg[0] ),\n .I2(\\sm_r_reg[2] ),\n .I3(lim2stg3_dec),\n .I4(lim2stg3_inc),\n .O(po_stg23_sel_r_reg));\n LUT6 #(\n .INIT(64'hBFFFBFFF20200000)) \n poc_ready_r_i_1\n (.I0(lim_state[2]),\n .I1(lim_state[3]),\n .I2(write_request_r_i_2_n_0),\n .I3(done_r_reg_1),\n .I4(wait_cnt_done),\n .I5(lim2poc_rdy),\n .O(poc_ready_r_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n poc_ready_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(poc_ready_r_i_1_n_0),\n .Q(lim2poc_rdy),\n .R(rstdiv0_sync_r1_reg_rep__9));\n LUT5 #(\n .INIT(32'hFFF70004)) \n prech_req_r_i_1__0\n (.I0(prech_done),\n .I1(prech_req_r_i_2_n_0),\n .I2(\\lim_state[13]_i_4_n_0 ),\n .I3(\\lim_state[2]_i_3_n_0 ),\n .I4(prech_req_r_reg_0),\n .O(prech_req_r_i_1__0_n_0));\n LUT6 #(\n .INIT(64'h0000000000010000)) \n prech_req_r_i_2\n (.I0(lim_state[6]),\n .I1(lim_state[5]),\n .I2(lim_state[7]),\n .I3(lim_state[4]),\n .I4(lim_state[12]),\n .I5(lim_state[13]),\n .O(prech_req_r_i_2_n_0));\n FDRE #(\n .INIT(1'b0)) \n prech_req_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prech_req_r_i_1__0_n_0),\n .Q(prech_req_r_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__10));\n LUT4 #(\n .INIT(16'h000E)) \n scanning_right_r_i_2\n (.I0(scanning_right_r_i_4_n_0),\n .I1(scanning_right_r_i_5_n_0),\n .I2(scan_right),\n .I3(scanning_right),\n .O(scanning_right_r_reg));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n scanning_right_r_i_4\n (.I0(scanning_right_r_reg_0[0]),\n .I1(\\stg3_r_reg[5] [0]),\n .I2(\\stg3_r_reg[5] [1]),\n .I3(scanning_right_r_reg_0[1]),\n .I4(\\stg3_r_reg[5] [2]),\n .I5(scanning_right_r_reg_0[2]),\n .O(scanning_right_r_i_4_n_0));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n scanning_right_r_i_5\n (.I0(scanning_right_r_reg_0[3]),\n .I1(\\stg3_r_reg[5] [3]),\n .I2(\\stg3_r_reg[5] [4]),\n .I3(scanning_right_r_reg_0[4]),\n .I4(\\stg3_r_reg[5] [5]),\n .I5(scanning_right_r_reg_0[5]),\n .O(scanning_right_r_i_5_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFDF00000008)) \n stg2_dec_req_r_i_1\n (.I0(stg2_inc_req_r_i_2_n_0),\n .I1(lim_state[8]),\n .I2(lim_state[10]),\n .I3(lim_state[0]),\n .I4(lim_state[7]),\n .I5(lim2stg2_dec),\n .O(stg2_dec_req_r_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n stg2_dec_req_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(stg2_dec_req_r_i_1_n_0),\n .Q(lim2stg2_dec),\n .R(rstdiv0_sync_r1_reg_rep__9));\n LUT6 #(\n .INIT(64'hFFFFFFFD00003020)) \n stg2_inc_r_i_1\n (.I0(\\lim_state[9]_i_3_n_0 ),\n .I1(stg2_inc_r_i_2_n_0),\n .I2(stg2_inc_r_i_3_n_0),\n .I3(lim_state[0]),\n .I4(stg2_inc_r_i_4_n_0),\n .I5(stg2_inc_r),\n .O(stg2_inc_r_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair376\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n stg2_inc_r_i_2\n (.I0(lim_state[13]),\n .I1(lim_state[12]),\n .I2(lim_state[9]),\n .I3(lim_state[10]),\n .O(stg2_inc_r_i_2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair389\" *) \n LUT3 #(\n .INIT(8'h04)) \n stg2_inc_r_i_3\n (.I0(lim_start_r),\n .I1(lim_start),\n .I2(lim_state[11]),\n .O(stg2_inc_r_i_3_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair375\" *) \n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n stg2_inc_r_i_4\n (.I0(lim_state[1]),\n .I1(lim_state[3]),\n .I2(lim_state[2]),\n .I3(lim_state[4]),\n .I4(wait_cnt_en_r_i_3_n_0),\n .O(stg2_inc_r_i_4_n_0));\n FDRE #(\n .INIT(1'b0)) \n stg2_inc_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(stg2_inc_r_i_1_n_0),\n .Q(stg2_inc_r),\n .R(rstdiv0_sync_r1_reg_rep__10));\n LUT6 #(\n .INIT(64'hFFFFFFF700000020)) \n stg2_inc_req_r_i_1\n (.I0(stg2_inc_req_r_i_2_n_0),\n .I1(lim_state[10]),\n .I2(lim_state[7]),\n .I3(lim_state[8]),\n .I4(lim_state[0]),\n .I5(lim2stg2_inc),\n .O(stg2_inc_req_r_i_1_n_0));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n stg2_inc_req_r_i_2\n (.I0(\\lim_state[0]_i_2_n_0 ),\n .I1(lim_state[12]),\n .I2(lim_state[11]),\n .I3(lim_state[13]),\n .I4(lim_state[9]),\n .I5(\\lim_state[10]_i_3_n_0 ),\n .O(stg2_inc_req_r_i_2_n_0));\n FDRE #(\n .INIT(1'b0)) \n stg2_inc_req_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(stg2_inc_req_r_i_1_n_0),\n .Q(lim2stg2_inc),\n .R(rstdiv0_sync_r1_reg_rep__10));\n (* SOFT_HLUTNM = \"soft_lutpair387\" *) \n LUT3 #(\n .INIT(8'h47)) \n \\stg2_tap_cnt[0]_i_1 \n (.I0(\\wl_po_fine_cnt_reg[18] ),\n .I1(\\stg2_tap_cnt_reg[0]_0 ),\n .I2(\\stg2_tap_cnt_reg[3]_0 [0]),\n .O(p_0_in__0[0]));\n LUT5 #(\n .INIT(32'h8BB8B88B)) \n \\stg2_tap_cnt[1]_i_1 \n (.I0(\\wl_po_fine_cnt_reg[14] [0]),\n .I1(\\stg2_tap_cnt_reg[0]_0 ),\n .I2(\\stg2_tap_cnt[1]_i_3_n_0 ),\n .I3(\\stg2_tap_cnt_reg[3]_0 [1]),\n .I4(\\stg2_tap_cnt_reg[3]_0 [0]),\n .O(p_0_in__0[1]));\n LUT6 #(\n .INIT(64'h0000000000000100)) \n \\stg2_tap_cnt[1]_i_3 \n (.I0(\\stg2_tap_cnt[1]_i_4_n_0 ),\n .I1(lim_state[12]),\n .I2(\\lim_state[2]_i_3_n_0 ),\n .I3(lim_state[7]),\n .I4(lim_state[6]),\n .I5(lim_state[5]),\n .O(\\stg2_tap_cnt[1]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\stg2_tap_cnt[1]_i_4 \n (.I0(lim_state[9]),\n .I1(lim_state[8]),\n .I2(lim_state[11]),\n .I3(lim_state[10]),\n .I4(lim_state[13]),\n .I5(lim_state[4]),\n .O(\\stg2_tap_cnt[1]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair370\" *) \n LUT5 #(\n .INIT(32'h8B8B8BB8)) \n \\stg2_tap_cnt[2]_i_1 \n (.I0(\\wl_po_fine_cnt_reg[14] [1]),\n .I1(\\stg2_tap_cnt_reg[0]_0 ),\n .I2(\\stg2_tap_cnt_reg[3]_0 [2]),\n .I3(\\stg2_tap_cnt[2]_i_3_n_0 ),\n .I4(\\stg2_tap_cnt[2]_i_4_n_0 ),\n .O(p_0_in__0[2]));\n LUT6 #(\n .INIT(64'h0001000000000000)) \n \\stg2_tap_cnt[2]_i_3 \n (.I0(\\stg2_tap_cnt[2]_i_5_n_0 ),\n .I1(\\lim_state[13]_i_4_n_0 ),\n .I2(lim_state[12]),\n .I3(\\lim_state[2]_i_3_n_0 ),\n .I4(\\stg2_tap_cnt_reg[3]_0 [1]),\n .I5(\\stg2_tap_cnt_reg[3]_0 [0]),\n .O(\\stg2_tap_cnt[2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h1111111111101111)) \n \\stg2_tap_cnt[2]_i_4 \n (.I0(\\stg2_tap_cnt_reg[3]_0 [1]),\n .I1(\\stg2_tap_cnt_reg[3]_0 [0]),\n .I2(lim_state[5]),\n .I3(lim_state[6]),\n .I4(lim_state[7]),\n .I5(\\stg2_tap_cnt[2]_i_6_n_0 ),\n .O(\\stg2_tap_cnt[2]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFFEFF)) \n \\stg2_tap_cnt[2]_i_5 \n (.I0(lim_state[6]),\n .I1(lim_state[5]),\n .I2(lim_state[4]),\n .I3(lim_state[7]),\n .I4(lim_state[13]),\n .O(\\stg2_tap_cnt[2]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n \\stg2_tap_cnt[2]_i_6 \n (.I0(\\lim_state[2]_i_3_n_0 ),\n .I1(lim_state[12]),\n .I2(lim_state[4]),\n .I3(lim_state[13]),\n .I4(\\lim_state[13]_i_4_n_0 ),\n .O(\\stg2_tap_cnt[2]_i_6_n_0 ));\n LUT5 #(\n .INIT(32'h74474774)) \n \\stg2_tap_cnt[3]_i_1 \n (.I0(\\wl_po_fine_cnt_reg[3] ),\n .I1(\\stg2_tap_cnt[3]_i_3_n_0 ),\n .I2(\\stg2_tap_cnt[4]_i_3_n_0 ),\n .I3(stg2_tap_cnt_reg__0[3]),\n .I4(\\stg2_tap_cnt_reg[3]_0 [2]),\n .O(p_0_in__0[3]));\n LUT6 #(\n .INIT(64'h0000000000000110)) \n \\stg2_tap_cnt[3]_i_3 \n (.I0(wait_cnt_en_r_i_2_n_0),\n .I1(lim_state[3]),\n .I2(lim_state[1]),\n .I3(lim_state[0]),\n .I4(lim_state[4]),\n .I5(lim_state[2]),\n .O(\\stg2_tap_cnt[3]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h7447747474744774)) \n \\stg2_tap_cnt[4]_i_1 \n (.I0(\\byte_r_reg[0] ),\n .I1(\\stg2_tap_cnt_reg[0]_0 ),\n .I2(stg2_tap_cnt_reg__0[4]),\n .I3(\\stg2_tap_cnt[4]_i_3_n_0 ),\n .I4(stg2_tap_cnt_reg__0[3]),\n .I5(\\stg2_tap_cnt_reg[3]_0 [2]),\n .O(p_0_in__0[4]));\n LUT5 #(\n .INIT(32'h01FF0101)) \n \\stg2_tap_cnt[4]_i_3 \n (.I0(\\stg2_tap_cnt[1]_i_3_n_0 ),\n .I1(\\stg2_tap_cnt_reg[3]_0 [0]),\n .I2(\\stg2_tap_cnt_reg[3]_0 [1]),\n .I3(\\stg2_tap_cnt[2]_i_3_n_0 ),\n .I4(\\stg2_tap_cnt_reg[3]_0 [2]),\n .O(\\stg2_tap_cnt[4]_i_3_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\stg2_tap_cnt[5]_i_2 \n (.I0(\\stg2_tap_cnt_reg[0]_0 ),\n .I1(\\lim_state[10]_i_1_n_0 ),\n .O(stg2_tap_cnt0));\n (* SOFT_HLUTNM = \"soft_lutpair387\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\stg2_tap_cnt[5]_i_3 \n (.I0(\\wl_po_fine_cnt_reg[17] ),\n .I1(\\stg2_tap_cnt_reg[0]_0 ),\n .I2(\\stg2_tap_cnt[5]_i_6_n_0 ),\n .O(p_0_in__0[5]));\n LUT4 #(\n .INIT(16'h0440)) \n \\stg2_tap_cnt[5]_i_4 \n (.I0(\\lim_state[13]_i_7_n_0 ),\n .I1(\\lim_state[1]_i_2_n_0 ),\n .I2(lim_state[0]),\n .I3(lim_state[1]),\n .O(\\stg2_tap_cnt_reg[0]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair364\" *) \n LUT5 #(\n .INIT(32'hAAA96AAA)) \n \\stg2_tap_cnt[5]_i_6 \n (.I0(stg2_tap_cnt_reg__0[5]),\n .I1(stg2_tap_cnt_reg__0[4]),\n .I2(\\stg2_tap_cnt_reg[3]_0 [2]),\n .I3(stg2_tap_cnt_reg__0[3]),\n .I4(\\stg2_tap_cnt[4]_i_3_n_0 ),\n .O(\\stg2_tap_cnt[5]_i_6_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\stg2_tap_cnt_reg[0] \n (.C(CLK),\n .CE(stg2_tap_cnt0),\n .D(p_0_in__0[0]),\n .Q(\\stg2_tap_cnt_reg[3]_0 [0]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE #(\n .INIT(1'b0)) \n \\stg2_tap_cnt_reg[1] \n (.C(CLK),\n .CE(stg2_tap_cnt0),\n .D(p_0_in__0[1]),\n .Q(\\stg2_tap_cnt_reg[3]_0 [1]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE #(\n .INIT(1'b0)) \n \\stg2_tap_cnt_reg[2] \n (.C(CLK),\n .CE(stg2_tap_cnt0),\n .D(p_0_in__0[2]),\n .Q(\\stg2_tap_cnt_reg[3]_0 [2]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE #(\n .INIT(1'b0)) \n \\stg2_tap_cnt_reg[3] \n (.C(CLK),\n .CE(stg2_tap_cnt0),\n .D(p_0_in__0[3]),\n .Q(stg2_tap_cnt_reg__0[3]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE #(\n .INIT(1'b0)) \n \\stg2_tap_cnt_reg[4] \n (.C(CLK),\n .CE(stg2_tap_cnt0),\n .D(p_0_in__0[4]),\n .Q(stg2_tap_cnt_reg__0[4]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE #(\n .INIT(1'b0)) \n \\stg2_tap_cnt_reg[5] \n (.C(CLK),\n .CE(stg2_tap_cnt0),\n .D(p_0_in__0[5]),\n .Q(stg2_tap_cnt_reg__0[5]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE #(\n .INIT(1'b0)) \n stg3_dec2init_val_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(stg3_dec2init_val_r),\n .Q(stg3_dec2init_val_r1),\n .R(rstdiv0_sync_r1_reg_rep__10));\n LUT6 #(\n .INIT(64'hFFFFAFAA00000D00)) \n stg3_dec2init_val_r_i_1\n (.I0(lim_state[4]),\n .I1(stg3_dec2init_val_r_i_2_n_0),\n .I2(lim_state[13]),\n .I3(wait_cnt_done),\n .I4(stg3_dec2init_val_r_i_3_n_0),\n .I5(stg3_dec2init_val_r),\n .O(stg3_dec2init_val_r_i_1_n_0));\n LUT4 #(\n .INIT(16'h5557)) \n stg3_dec2init_val_r_i_10\n (.I0(mod_sub0_return0_carry_n_4),\n .I1(mod_sub0_return0_carry_n_6),\n .I2(mod_sub0_return0_carry_n_5),\n .I3(mod_sub0_return0_carry_n_7),\n .O(stg3_dec2init_val_r_i_10_n_0));\n LUT6 #(\n .INIT(64'h40F440F4FFFF40F4)) \n stg3_dec2init_val_r_i_12\n (.I0(\\mmcm_current_reg_n_0_[0] ),\n .I1(\\mmcm_init_lead_reg_n_0_[0] ),\n .I2(\\mmcm_init_lead_reg_n_0_[1] ),\n .I3(\\mmcm_current_reg_n_0_[1] ),\n .I4(\\mmcm_init_lead_reg_n_0_[2] ),\n .I5(\\mmcm_current_reg_n_0_[2] ),\n .O(stg3_dec2init_val_r_i_12_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair372\" *) \n LUT2 #(\n .INIT(4'h2)) \n stg3_dec2init_val_r_i_13\n (.I0(\\mmcm_init_lead_reg_n_0_[4] ),\n .I1(\\mmcm_current_reg_n_0_[4] ),\n .O(stg3_dec2init_val_r_i_13_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair390\" *) \n LUT2 #(\n .INIT(4'h9)) \n stg3_dec2init_val_r_i_14\n (.I0(\\mmcm_current_reg_n_0_[0] ),\n .I1(\\mmcm_init_lead_reg_n_0_[0] ),\n .O(stg3_dec2init_val_r_reg_0));\n LUT6 #(\n .INIT(64'h4445554544555555)) \n stg3_dec2init_val_r_i_2\n (.I0(stg3_dec_r),\n .I1(stg3_dec2init_val_r_i_4_n_0),\n .I2(stg3_dec2init_val_r_i_5_n_0),\n .I3(stg3_dec2init_val_r_i_6_n_0),\n .I4(stg3_dec2init_val_r_i_7_n_0),\n .I5(stg3_dec2init_val_r_i_8_n_0),\n .O(stg3_dec2init_val_r_i_2_n_0));\n LUT4 #(\n .INIT(16'hDDDF)) \n stg3_dec2init_val_r_i_3\n (.I0(\\lim_state[4]_i_3_n_0 ),\n .I1(\\lim_state[2]_i_3_n_0 ),\n .I2(lim_state[4]),\n .I3(lim_state[13]),\n .O(stg3_dec2init_val_r_i_3_n_0));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n stg3_dec2init_val_r_i_4\n (.I0(\\stg3_tap_cnt_reg_n_0_[4] ),\n .I1(\\stg3_tap_cnt_reg_n_0_[5] ),\n .I2(\\stg3_tap_cnt_reg_n_0_[0] ),\n .I3(\\stg3_tap_cnt_reg_n_0_[1] ),\n .I4(\\stg3_tap_cnt_reg_n_0_[3] ),\n .I5(\\stg3_tap_cnt_reg_n_0_[2] ),\n .O(stg3_dec2init_val_r_i_4_n_0));\n LUT3 #(\n .INIT(8'h04)) \n stg3_dec2init_val_r_i_5\n (.I0(mod_sub0_return0__14_carry__0_n_6),\n .I1(mod_sub0_return0__14_carry__0_n_1),\n .I2(mod_sub0_return0__14_carry__0_n_7),\n .O(stg3_dec2init_val_r_i_5_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair372\" *) \n LUT5 #(\n .INIT(32'hB2BB2222)) \n stg3_dec2init_val_r_i_6\n (.I0(\\mmcm_init_lead_reg_n_0_[5] ),\n .I1(\\mmcm_current_reg_n_0_[5] ),\n .I2(\\mmcm_init_lead_reg_n_0_[4] ),\n .I3(\\mmcm_current_reg_n_0_[4] ),\n .I4(stg3_dec2init_val_r_i_9_n_0),\n .O(stg3_dec2init_val_r_i_6_n_0));\n LUT4 #(\n .INIT(16'h0002)) \n stg3_dec2init_val_r_i_7\n (.I0(stg3_dec2init_val_r_i_10_n_0),\n .I1(mod_sub0_return0_carry__0_n_7),\n .I2(mod_sub0_return0_carry__0_n_5),\n .I3(mod_sub0_return0_carry__0_n_6),\n .O(stg3_dec2init_val_r_i_7_n_0));\n LUT4 #(\n .INIT(16'h5557)) \n stg3_dec2init_val_r_i_8\n (.I0(mod_sub0_return0__14_carry_n_4),\n .I1(mod_sub0_return0__14_carry_n_6),\n .I2(mod_sub0_return0__14_carry_n_5),\n .I3(\\mmcm_current_reg[0]_0 ),\n .O(stg3_dec2init_val_r_i_8_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFFB000FFB0)) \n stg3_dec2init_val_r_i_9\n (.I0(\\mmcm_init_lead_reg_n_0_[2] ),\n .I1(\\mmcm_current_reg_n_0_[2] ),\n .I2(stg3_dec2init_val_r_i_12_n_0),\n .I3(\\mmcm_init_lead_reg_n_0_[3] ),\n .I4(\\mmcm_current_reg_n_0_[3] ),\n .I5(stg3_dec2init_val_r_i_13_n_0),\n .O(stg3_dec2init_val_r_i_9_n_0));\n FDRE #(\n .INIT(1'b0)) \n stg3_dec2init_val_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(stg3_dec2init_val_r_i_1_n_0),\n .Q(stg3_dec2init_val_r),\n .R(rstdiv0_sync_r1_reg_rep__10));\n LUT6 #(\n .INIT(64'hFFFDFFFF30200000)) \n stg3_dec_r_i_1\n (.I0(stg3_dec_r_i_2_n_0),\n .I1(stg3_dec_r_i_3_n_0),\n .I2(stg3_dec_r_i_4_n_0),\n .I3(lim_state[0]),\n .I4(stg3_dec_r_i_5_n_0),\n .I5(stg3_dec_r),\n .O(stg3_dec_r_i_1_n_0));\n LUT4 #(\n .INIT(16'h8000)) \n stg3_dec_r_i_2\n (.I0(\\lim_state[6]_i_10_n_0 ),\n .I1(lim_state[4]),\n .I2(wait_cnt_done),\n .I3(stg3_dec_r),\n .O(stg3_dec_r_i_2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair381\" *) \n LUT2 #(\n .INIT(4'hE)) \n stg3_dec_r_i_3\n (.I0(lim_state[2]),\n .I1(lim_state[1]),\n .O(stg3_dec_r_i_3_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair389\" *) \n LUT3 #(\n .INIT(8'h04)) \n stg3_dec_r_i_4\n (.I0(lim_start_r),\n .I1(lim_start),\n .I2(lim_state[4]),\n .O(stg3_dec_r_i_4_n_0));\n LUT6 #(\n .INIT(64'h0000000000000004)) \n stg3_dec_r_i_5\n (.I0(lim_state[3]),\n .I1(\\lim_state[1]_i_2_n_0 ),\n .I2(lim_state[5]),\n .I3(lim_state[6]),\n .I4(lim_state[7]),\n .I5(lim_state[8]),\n .O(stg3_dec_r_i_5_n_0));\n FDRE #(\n .INIT(1'b0)) \n stg3_dec_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(stg3_dec_r_i_1_n_0),\n .Q(stg3_dec_r),\n .R(rstdiv0_sync_r1_reg_rep__10));\n LUT6 #(\n .INIT(64'hFFFFFDFF00000020)) \n stg3_dec_req_r_i_1\n (.I0(stg3_dec_req_r_i_2_n_0),\n .I1(lim_state[7]),\n .I2(lim_state[6]),\n .I3(lim_state[9]),\n .I4(lim_state[5]),\n .I5(lim2stg3_dec),\n .O(stg3_dec_req_r_i_1_n_0));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n stg3_dec_req_r_i_2\n (.I0(\\lim_state[0]_i_2_n_0 ),\n .I1(stg3_dec_req_r_i_3_n_0),\n .I2(lim_state[13]),\n .I3(lim_state[12]),\n .I4(lim_state[0]),\n .I5(lim_state[8]),\n .O(stg3_dec_req_r_i_2_n_0));\n LUT2 #(\n .INIT(4'hE)) \n stg3_dec_req_r_i_3\n (.I0(lim_state[11]),\n .I1(lim_state[10]),\n .O(stg3_dec_req_r_i_3_n_0));\n FDRE #(\n .INIT(1'b0)) \n stg3_dec_req_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(stg3_dec_req_r_i_1_n_0),\n .Q(lim2stg3_dec),\n .R(rstdiv0_sync_r1_reg_rep__10));\n (* SOFT_HLUTNM = \"soft_lutpair368\" *) \n LUT3 #(\n .INIT(8'h69)) \n \\stg3_dec_val[3]_i_1 \n (.I0(\\stg3_dec_val[5]_i_3_n_0 ),\n .I1(\\byte_r_reg[0] ),\n .I2(stg3_init_val[3]),\n .O(stg3_dec_val00_out[3]));\n (* SOFT_HLUTNM = \"soft_lutpair368\" *) \n LUT5 #(\n .INIT(32'h4DB2B24D)) \n \\stg3_dec_val[4]_i_1 \n (.I0(\\stg3_dec_val[5]_i_3_n_0 ),\n .I1(\\byte_r_reg[0] ),\n .I2(stg3_init_val[3]),\n .I3(\\wl_po_fine_cnt_reg[17] ),\n .I4(stg3_init_val[4]),\n .O(stg3_dec_val00_out[4]));\n LUT5 #(\n .INIT(32'hFF00FF71)) \n \\stg3_dec_val[5]_i_1 \n (.I0(\\stg3_inc_val[5]_i_2_n_0 ),\n .I1(stg3_init_val[4]),\n .I2(\\wl_po_fine_cnt_reg[17] ),\n .I3(rstdiv0_sync_r1_reg_rep__20),\n .I4(stg3_init_val[5]),\n .O(\\stg3_dec_val[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hB2FF00B24D00FF4D)) \n \\stg3_dec_val[5]_i_2 \n (.I0(\\stg3_dec_val[5]_i_3_n_0 ),\n .I1(\\byte_r_reg[0] ),\n .I2(stg3_init_val[3]),\n .I3(\\wl_po_fine_cnt_reg[17] ),\n .I4(stg3_init_val[4]),\n .I5(stg3_init_val[5]),\n .O(\\stg3_dec_val[5]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFEE0FFFF0000FEE0)) \n \\stg3_dec_val[5]_i_3 \n (.I0(\\stg3_tap_cnt_reg[2]_0 [0]),\n .I1(\\wl_po_fine_cnt_reg[14] [0]),\n .I2(\\stg3_tap_cnt_reg[2]_0 [1]),\n .I3(\\wl_po_fine_cnt_reg[14] [1]),\n .I4(\\wl_po_fine_cnt_reg[3] ),\n .I5(\\stg3_tap_cnt_reg[2]_0 [2]),\n .O(\\stg3_dec_val[5]_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_dec_val_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(D[0]),\n .Q(stg3_dec_val[0]),\n .R(\\stg3_dec_val[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_dec_val_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(D[1]),\n .Q(stg3_dec_val[1]),\n .R(\\stg3_dec_val[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_dec_val_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(D[2]),\n .Q(stg3_dec_val[2]),\n .R(\\stg3_dec_val[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_dec_val_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(stg3_dec_val00_out[3]),\n .Q(stg3_dec_val[3]),\n .R(\\stg3_dec_val[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_dec_val_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(stg3_dec_val00_out[4]),\n .Q(stg3_dec_val[4]),\n .R(\\stg3_dec_val[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_dec_val_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\stg3_dec_val[5]_i_2_n_0 ),\n .Q(stg3_dec_val[5]),\n .R(\\stg3_dec_val[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n stg3_inc2init_val_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(stg3_inc2init_val_r),\n .Q(stg3_inc2init_val_r1),\n .R(rstdiv0_sync_r1_reg_rep__9));\n LUT5 #(\n .INIT(32'hFF0B0008)) \n stg3_inc2init_val_r_i_1\n (.I0(stg3_dec_r),\n .I1(stg3_dec_r_i_2_n_0),\n .I2(lim_state[11]),\n .I3(stg3_inc2init_val_r_i_2_n_0),\n .I4(stg3_inc2init_val_r),\n .O(stg3_inc2init_val_r_i_1_n_0));\n LUT6 #(\n .INIT(64'hEEEEEEEEFFFFFFEF)) \n stg3_inc2init_val_r_i_2\n (.I0(wait_cnt_en_r_i_3_n_0),\n .I1(\\lim_state[2]_i_3_n_0 ),\n .I2(stg3_inc2init_val_r_i_3_n_0),\n .I3(stg2_inc_r_i_2_n_0),\n .I4(lim_state[4]),\n .I5(\\lim_state[1]_i_2_n_0 ),\n .O(stg3_inc2init_val_r_i_2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair383\" *) \n LUT3 #(\n .INIT(8'h20)) \n stg3_inc2init_val_r_i_3\n (.I0(\\lim_state[12]_i_3_n_0 ),\n .I1(stg3_dec2init_val_r),\n .I2(stg3_inc2init_val_r),\n .O(stg3_inc2init_val_r_i_3_n_0));\n FDRE #(\n .INIT(1'b0)) \n stg3_inc2init_val_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(stg3_inc2init_val_r_i_1_n_0),\n .Q(stg3_inc2init_val_r),\n .R(rstdiv0_sync_r1_reg_rep__9));\n LUT6 #(\n .INIT(64'hFFFFFFF700000020)) \n stg3_inc_req_r_i_1\n (.I0(stg3_dec_req_r_i_2_n_0),\n .I1(lim_state[9]),\n .I2(lim_state[5]),\n .I3(lim_state[7]),\n .I4(lim_state[6]),\n .I5(lim2stg3_inc),\n .O(stg3_inc_req_r_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n stg3_inc_req_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(stg3_inc_req_r_i_1_n_0),\n .Q(lim2stg3_inc),\n .R(rstdiv0_sync_r1_reg_rep__9));\n LUT3 #(\n .INIT(8'hF6)) \n \\stg3_inc_val[0]_i_1 \n (.I0(\\wl_po_fine_cnt_reg[14] [0]),\n .I1(\\stg3_tap_cnt_reg[2]_0 [0]),\n .I2(\\stg3_inc_val[5]_i_3_n_0 ),\n .O(\\stg3_inc_val[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair367\" *) \n LUT5 #(\n .INIT(32'hFFFF9666)) \n \\stg3_inc_val[1]_i_1 \n (.I0(\\stg3_tap_cnt_reg[2]_0 [1]),\n .I1(\\wl_po_fine_cnt_reg[14] [1]),\n .I2(\\stg3_tap_cnt_reg[2]_0 [0]),\n .I3(\\wl_po_fine_cnt_reg[14] [0]),\n .I4(\\stg3_inc_val[5]_i_3_n_0 ),\n .O(\\stg3_inc_val[1]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hFF96)) \n \\stg3_inc_val[2]_i_1 \n (.I0(\\stg3_tap_cnt_reg[2]_0 [2]),\n .I1(\\wl_po_fine_cnt_reg[3] ),\n .I2(\\stg3_inc_val[2]_i_2_n_0 ),\n .I3(\\stg3_inc_val[5]_i_3_n_0 ),\n .O(\\stg3_inc_val[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair367\" *) \n LUT4 #(\n .INIT(16'h077F)) \n \\stg3_inc_val[2]_i_2 \n (.I0(\\stg3_tap_cnt_reg[2]_0 [0]),\n .I1(\\wl_po_fine_cnt_reg[14] [0]),\n .I2(\\wl_po_fine_cnt_reg[14] [1]),\n .I3(\\stg3_tap_cnt_reg[2]_0 [1]),\n .O(\\stg3_inc_val[2]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair378\" *) \n LUT4 #(\n .INIT(16'hFF96)) \n \\stg3_inc_val[3]_i_1 \n (.I0(stg3_init_val[3]),\n .I1(\\byte_r_reg[0] ),\n .I2(\\stg3_inc_val[3]_i_2_n_0 ),\n .I3(\\stg3_inc_val[5]_i_3_n_0 ),\n .O(\\stg3_inc_val[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h077FFFFF0000077F)) \n \\stg3_inc_val[3]_i_2 \n (.I0(\\stg3_tap_cnt_reg[2]_0 [0]),\n .I1(\\wl_po_fine_cnt_reg[14] [0]),\n .I2(\\wl_po_fine_cnt_reg[14] [1]),\n .I3(\\stg3_tap_cnt_reg[2]_0 [1]),\n .I4(\\stg3_tap_cnt_reg[2]_0 [2]),\n .I5(\\wl_po_fine_cnt_reg[3] ),\n .O(\\stg3_inc_val[3]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair371\" *) \n LUT4 #(\n .INIT(16'hFF69)) \n \\stg3_inc_val[4]_i_1 \n (.I0(stg3_init_val[4]),\n .I1(\\wl_po_fine_cnt_reg[17] ),\n .I2(\\stg3_inc_val[5]_i_2_n_0 ),\n .I3(\\stg3_inc_val[5]_i_3_n_0 ),\n .O(\\stg3_inc_val[4]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair371\" *) \n LUT5 #(\n .INIT(32'hFFFF718E)) \n \\stg3_inc_val[5]_i_1 \n (.I0(\\stg3_inc_val[5]_i_2_n_0 ),\n .I1(stg3_init_val[4]),\n .I2(\\wl_po_fine_cnt_reg[17] ),\n .I3(stg3_init_val[5]),\n .I4(\\stg3_inc_val[5]_i_3_n_0 ),\n .O(\\stg3_inc_val[5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair378\" *) \n LUT3 #(\n .INIT(8'h4D)) \n \\stg3_inc_val[5]_i_2 \n (.I0(\\stg3_inc_val[3]_i_2_n_0 ),\n .I1(stg3_init_val[3]),\n .I2(\\byte_r_reg[0] ),\n .O(\\stg3_inc_val[5]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hB2FF00B200000000)) \n \\stg3_inc_val[5]_i_3 \n (.I0(\\stg3_dec_val[5]_i_3_n_0 ),\n .I1(\\byte_r_reg[0] ),\n .I2(stg3_init_val[3]),\n .I3(\\wl_po_fine_cnt_reg[17] ),\n .I4(stg3_init_val[4]),\n .I5(stg3_init_val[5]),\n .O(\\stg3_inc_val[5]_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_inc_val_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\stg3_inc_val[0]_i_1_n_0 ),\n .Q(stg3_inc_val[0]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_inc_val_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\stg3_inc_val[1]_i_1_n_0 ),\n .Q(stg3_inc_val[1]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_inc_val_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\stg3_inc_val[2]_i_1_n_0 ),\n .Q(stg3_inc_val[2]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_inc_val_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\stg3_inc_val[3]_i_1_n_0 ),\n .Q(stg3_inc_val[3]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_inc_val_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\stg3_inc_val[4]_i_1_n_0 ),\n .Q(stg3_inc_val[4]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_inc_val_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\stg3_inc_val[5]_i_1_n_0 ),\n .Q(stg3_inc_val[5]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n LUT6 #(\n .INIT(64'hFFFFFFF70000FF00)) \n stg3_init_dec_r_i_1\n (.I0(\\lim_state[6]_i_3_n_0 ),\n .I1(stg3_init_dec_r_i_2_n_0),\n .I2(lim_state[0]),\n .I3(stg3_init_dec_r_i_3_n_0),\n .I4(stg3_init_dec_r_i_4_n_0),\n .I5(stg3_init_dec_r),\n .O(stg3_init_dec_r_i_1_n_0));\n LUT3 #(\n .INIT(8'h02)) \n stg3_init_dec_r_i_2\n (.I0(po_rdy),\n .I1(lim2stg3_dec),\n .I2(lim2stg3_inc),\n .O(stg3_init_dec_r_i_2_n_0));\n LUT3 #(\n .INIT(8'h04)) \n stg3_init_dec_r_i_3\n (.I0(lim_start_r),\n .I1(lim_start),\n .I2(lim_state[9]),\n .O(stg3_init_dec_r_i_3_n_0));\n LUT5 #(\n .INIT(32'hEFEFEFFF)) \n stg3_init_dec_r_i_4\n (.I0(\\lim_state[13]_i_7_n_0 ),\n .I1(lim_state[1]),\n .I2(\\lim_state[6]_i_6_n_0 ),\n .I3(lim_state[9]),\n .I4(lim_state[0]),\n .O(stg3_init_dec_r_i_4_n_0));\n FDRE #(\n .INIT(1'b0)) \n stg3_init_dec_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(stg3_init_dec_r_i_1_n_0),\n .Q(stg3_init_dec_r),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_init_val_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(oclkdelay_calib_done_r_reg[0]),\n .Q(\\stg3_tap_cnt_reg[2]_0 [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_init_val_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(oclkdelay_calib_done_r_reg[1]),\n .Q(\\stg3_tap_cnt_reg[2]_0 [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_init_val_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(oclkdelay_calib_done_r_reg[2]),\n .Q(\\stg3_tap_cnt_reg[2]_0 [2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_init_val_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(oclkdelay_calib_done_r_reg[3]),\n .Q(stg3_init_val[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_init_val_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(oclkdelay_calib_done_r_reg[4]),\n .Q(stg3_init_val[4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_init_val_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(oclkdelay_calib_done_r_reg[5]),\n .Q(stg3_init_val[5]),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hAAAAFBAA)) \n \\stg3_left_lim[5]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__25),\n .I1(stg3_inc2init_val_r),\n .I2(stg3_inc2init_val_r1),\n .I3(lim_start),\n .I4(lim_start_r),\n .O(\\stg3_left_lim[5]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\stg3_left_lim[5]_i_2 \n (.I0(stg3_inc2init_val_r),\n .I1(stg3_inc2init_val_r1),\n .O(stg3_left_lim0));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_left_lim_reg[0] \n (.C(CLK),\n .CE(stg3_left_lim0),\n .D(\\stg3_tap_cnt_reg_n_0_[0] ),\n .Q(scanning_right_r_reg_0[0]),\n .R(\\stg3_left_lim[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_left_lim_reg[1] \n (.C(CLK),\n .CE(stg3_left_lim0),\n .D(\\stg3_tap_cnt_reg_n_0_[1] ),\n .Q(scanning_right_r_reg_0[1]),\n .R(\\stg3_left_lim[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_left_lim_reg[2] \n (.C(CLK),\n .CE(stg3_left_lim0),\n .D(\\stg3_tap_cnt_reg_n_0_[2] ),\n .Q(scanning_right_r_reg_0[2]),\n .R(\\stg3_left_lim[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_left_lim_reg[3] \n (.C(CLK),\n .CE(stg3_left_lim0),\n .D(\\stg3_tap_cnt_reg_n_0_[3] ),\n .Q(scanning_right_r_reg_0[3]),\n .R(\\stg3_left_lim[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_left_lim_reg[4] \n (.C(CLK),\n .CE(stg3_left_lim0),\n .D(\\stg3_tap_cnt_reg_n_0_[4] ),\n .Q(scanning_right_r_reg_0[4]),\n .R(\\stg3_left_lim[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_left_lim_reg[5] \n (.C(CLK),\n .CE(stg3_left_lim0),\n .D(\\stg3_tap_cnt_reg_n_0_[5] ),\n .Q(scanning_right_r_reg_0[5]),\n .R(\\stg3_left_lim[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAAAAFBAA)) \n \\stg3_right_lim[5]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__25),\n .I1(stg3_dec2init_val_r),\n .I2(stg3_dec2init_val_r1),\n .I3(lim_start),\n .I4(lim_start_r),\n .O(\\stg3_right_lim[5]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\stg3_right_lim[5]_i_2 \n (.I0(stg3_dec2init_val_r),\n .I1(stg3_dec2init_val_r1),\n .O(stg3_right_lim0));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_right_lim_reg[0] \n (.C(CLK),\n .CE(stg3_right_lim0),\n .D(\\stg3_tap_cnt_reg_n_0_[0] ),\n .Q(oclkdelay_center_calib_start_r_reg_0[0]),\n .R(\\stg3_right_lim[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_right_lim_reg[1] \n (.C(CLK),\n .CE(stg3_right_lim0),\n .D(\\stg3_tap_cnt_reg_n_0_[1] ),\n .Q(oclkdelay_center_calib_start_r_reg_0[1]),\n .R(\\stg3_right_lim[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_right_lim_reg[2] \n (.C(CLK),\n .CE(stg3_right_lim0),\n .D(\\stg3_tap_cnt_reg_n_0_[2] ),\n .Q(oclkdelay_center_calib_start_r_reg_0[2]),\n .R(\\stg3_right_lim[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_right_lim_reg[3] \n (.C(CLK),\n .CE(stg3_right_lim0),\n .D(\\stg3_tap_cnt_reg_n_0_[3] ),\n .Q(oclkdelay_center_calib_start_r_reg_0[3]),\n .R(\\stg3_right_lim[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_right_lim_reg[4] \n (.C(CLK),\n .CE(stg3_right_lim0),\n .D(\\stg3_tap_cnt_reg_n_0_[4] ),\n .Q(oclkdelay_center_calib_start_r_reg_0[4]),\n .R(\\stg3_right_lim[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_right_lim_reg[5] \n (.C(CLK),\n .CE(stg3_right_lim0),\n .D(\\stg3_tap_cnt_reg_n_0_[5] ),\n .Q(oclkdelay_center_calib_start_r_reg_0[5]),\n .R(\\stg3_right_lim[5]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h3A)) \n \\stg3_tap_cnt[0]_i_1 \n (.I0(\\stg3_tap_cnt_reg[2]_0 [0]),\n .I1(\\stg3_tap_cnt_reg_n_0_[0] ),\n .I2(rstdiv0_sync_r1_reg_rep__25_0),\n .O(\\stg3_tap_cnt[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h96FF9600)) \n \\stg3_tap_cnt[1]_i_1 \n (.I0(\\stg3_tap_cnt[1]_i_2_n_0 ),\n .I1(\\stg3_tap_cnt_reg_n_0_[1] ),\n .I2(\\stg3_tap_cnt_reg_n_0_[0] ),\n .I3(rstdiv0_sync_r1_reg_rep__25_0),\n .I4(\\stg3_tap_cnt_reg[2]_0 [1]),\n .O(\\stg3_tap_cnt[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFEFFFFFFFF)) \n \\stg3_tap_cnt[1]_i_2 \n (.I0(\\stg2_tap_cnt[1]_i_4_n_0 ),\n .I1(lim_state[12]),\n .I2(\\lim_state[2]_i_3_n_0 ),\n .I3(lim_state[7]),\n .I4(lim_state[6]),\n .I5(lim_state[5]),\n .O(\\stg3_tap_cnt[1]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'h6F60)) \n \\stg3_tap_cnt[2]_i_1 \n (.I0(\\stg3_tap_cnt_reg_n_0_[2] ),\n .I1(\\stg3_tap_cnt[2]_i_2_n_0 ),\n .I2(rstdiv0_sync_r1_reg_rep__25_0),\n .I3(\\stg3_tap_cnt_reg[2]_0 [2]),\n .O(\\stg3_tap_cnt[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h001000000000FFEF)) \n \\stg3_tap_cnt[2]_i_2 \n (.I0(\\lim_state[2]_i_3_n_0 ),\n .I1(lim_state[12]),\n .I2(lim_state[5]),\n .I3(\\stg3_tap_cnt[3]_i_4_n_0 ),\n .I4(\\stg3_tap_cnt_reg_n_0_[0] ),\n .I5(\\stg3_tap_cnt_reg_n_0_[1] ),\n .O(\\stg3_tap_cnt[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hD32CFFFFD32C0000)) \n \\stg3_tap_cnt[3]_i_1 \n (.I0(\\stg3_tap_cnt[3]_i_2_n_0 ),\n .I1(\\stg3_tap_cnt[3]_i_3_n_0 ),\n .I2(\\stg3_tap_cnt_reg_n_0_[2] ),\n .I3(\\stg3_tap_cnt_reg_n_0_[3] ),\n .I4(rstdiv0_sync_r1_reg_rep__25_0),\n .I5(stg3_init_val[3]),\n .O(\\stg3_tap_cnt[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000800)) \n \\stg3_tap_cnt[3]_i_2 \n (.I0(\\stg3_tap_cnt_reg_n_0_[1] ),\n .I1(\\stg3_tap_cnt_reg_n_0_[0] ),\n .I2(\\stg3_tap_cnt[3]_i_4_n_0 ),\n .I3(lim_state[5]),\n .I4(lim_state[12]),\n .I5(\\lim_state[2]_i_3_n_0 ),\n .O(\\stg3_tap_cnt[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h1111111111101111)) \n \\stg3_tap_cnt[3]_i_3 \n (.I0(\\stg3_tap_cnt_reg_n_0_[1] ),\n .I1(\\stg3_tap_cnt_reg_n_0_[0] ),\n .I2(\\lim_state[2]_i_3_n_0 ),\n .I3(lim_state[12]),\n .I4(lim_state[5]),\n .I5(\\stg3_tap_cnt[3]_i_4_n_0 ),\n .O(\\stg3_tap_cnt[3]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n \\stg3_tap_cnt[3]_i_4 \n (.I0(\\lim_state[13]_i_4_n_0 ),\n .I1(lim_state[7]),\n .I2(lim_state[6]),\n .I3(lim_state[4]),\n .I4(lim_state[13]),\n .O(\\stg3_tap_cnt[3]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h56FF5600)) \n \\stg3_tap_cnt[4]_i_1 \n (.I0(\\stg3_tap_cnt_reg_n_0_[4] ),\n .I1(\\stg3_tap_cnt[5]_i_4_n_0 ),\n .I2(\\stg3_tap_cnt[5]_i_5_n_0 ),\n .I3(rstdiv0_sync_r1_reg_rep__25_0),\n .I4(stg3_init_val[4]),\n .O(\\stg3_tap_cnt[4]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h1400FFFF)) \n \\stg3_tap_cnt[5]_i_1 \n (.I0(lim_state[11]),\n .I1(lim_state[5]),\n .I2(lim_state[6]),\n .I3(\\lim_state[9]_i_2_n_0 ),\n .I4(rstdiv0_sync_r1_reg_rep__25_0),\n .O(stg3_tap_cnt0));\n LUT6 #(\n .INIT(64'hD32CFFFFD32C0000)) \n \\stg3_tap_cnt[5]_i_2 \n (.I0(\\stg3_tap_cnt[5]_i_4_n_0 ),\n .I1(\\stg3_tap_cnt[5]_i_5_n_0 ),\n .I2(\\stg3_tap_cnt_reg_n_0_[4] ),\n .I3(\\stg3_tap_cnt_reg_n_0_[5] ),\n .I4(rstdiv0_sync_r1_reg_rep__25_0),\n .I5(stg3_init_val[5]),\n .O(\\stg3_tap_cnt[5]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h00008000)) \n \\stg3_tap_cnt[5]_i_4 \n (.I0(\\stg3_tap_cnt_reg_n_0_[2] ),\n .I1(\\stg3_tap_cnt_reg_n_0_[3] ),\n .I2(\\stg3_tap_cnt_reg_n_0_[0] ),\n .I3(\\stg3_tap_cnt_reg_n_0_[1] ),\n .I4(\\stg3_tap_cnt[1]_i_2_n_0 ),\n .O(\\stg3_tap_cnt[5]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair374\" *) \n LUT5 #(\n .INIT(32'h00000001)) \n \\stg3_tap_cnt[5]_i_5 \n (.I0(\\stg3_tap_cnt_reg_n_0_[3] ),\n .I1(\\stg3_tap_cnt_reg_n_0_[2] ),\n .I2(\\stg3_tap_cnt_reg_n_0_[0] ),\n .I3(\\stg3_tap_cnt_reg_n_0_[1] ),\n .I4(\\stg3_tap_cnt[5]_i_6_n_0 ),\n .O(\\stg3_tap_cnt[5]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair377\" *) \n LUT4 #(\n .INIT(16'h0004)) \n \\stg3_tap_cnt[5]_i_6 \n (.I0(\\stg3_tap_cnt[3]_i_4_n_0 ),\n .I1(lim_state[5]),\n .I2(lim_state[12]),\n .I3(\\lim_state[2]_i_3_n_0 ),\n .O(\\stg3_tap_cnt[5]_i_6_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_tap_cnt_reg[0] \n (.C(CLK),\n .CE(stg3_tap_cnt0),\n .D(\\stg3_tap_cnt[0]_i_1_n_0 ),\n .Q(\\stg3_tap_cnt_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_tap_cnt_reg[1] \n (.C(CLK),\n .CE(stg3_tap_cnt0),\n .D(\\stg3_tap_cnt[1]_i_1_n_0 ),\n .Q(\\stg3_tap_cnt_reg_n_0_[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_tap_cnt_reg[2] \n (.C(CLK),\n .CE(stg3_tap_cnt0),\n .D(\\stg3_tap_cnt[2]_i_1_n_0 ),\n .Q(\\stg3_tap_cnt_reg_n_0_[2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_tap_cnt_reg[3] \n (.C(CLK),\n .CE(stg3_tap_cnt0),\n .D(\\stg3_tap_cnt[3]_i_1_n_0 ),\n .Q(\\stg3_tap_cnt_reg_n_0_[3] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_tap_cnt_reg[4] \n (.C(CLK),\n .CE(stg3_tap_cnt0),\n .D(\\stg3_tap_cnt[4]_i_1_n_0 ),\n .Q(\\stg3_tap_cnt_reg_n_0_[4] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_tap_cnt_reg[5] \n (.C(CLK),\n .CE(stg3_tap_cnt0),\n .D(\\stg3_tap_cnt[5]_i_2_n_0 ),\n .Q(\\stg3_tap_cnt_reg_n_0_[5] ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00008000)) \n wait_cnt_done_i_1\n (.I0(wait_cnt_en_r),\n .I1(wait_cnt_r_reg__0[2]),\n .I2(wait_cnt_r_reg__0[3]),\n .I3(wait_cnt_r_reg__0[1]),\n .I4(wait_cnt_r_reg__0[0]),\n .O(wait_cnt_done_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n wait_cnt_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wait_cnt_done_i_1_n_0),\n .Q(wait_cnt_done),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0000000000010110)) \n wait_cnt_en_r_i_1\n (.I0(wait_cnt_en_r_i_2_n_0),\n .I1(lim_state[0]),\n .I2(lim_state[1]),\n .I3(lim_state[4]),\n .I4(lim_state[2]),\n .I5(lim_state[3]),\n .O(wait_cnt_en_r0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n wait_cnt_en_r_i_2\n (.I0(wait_cnt_en_r_i_3_n_0),\n .I1(lim_state[13]),\n .I2(lim_state[9]),\n .I3(lim_state[12]),\n .I4(lim_state[10]),\n .I5(lim_state[11]),\n .O(wait_cnt_en_r_i_2_n_0));\n LUT4 #(\n .INIT(16'hFFFE)) \n wait_cnt_en_r_i_3\n (.I0(lim_state[5]),\n .I1(lim_state[6]),\n .I2(lim_state[7]),\n .I3(lim_state[8]),\n .O(wait_cnt_en_r_i_3_n_0));\n FDRE #(\n .INIT(1'b0)) \n wait_cnt_en_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wait_cnt_en_r0),\n .Q(wait_cnt_en_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair391\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\wait_cnt_r[0]_i_1 \n (.I0(wait_cnt_r_reg__0[0]),\n .O(p_0_in[0]));\n (* SOFT_HLUTNM = \"soft_lutpair391\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\wait_cnt_r[1]_i_1 \n (.I0(wait_cnt_r_reg__0[0]),\n .I1(wait_cnt_r_reg__0[1]),\n .O(p_0_in[1]));\n (* SOFT_HLUTNM = \"soft_lutpair382\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\wait_cnt_r[2]_i_1 \n (.I0(wait_cnt_r_reg__0[2]),\n .I1(wait_cnt_r_reg__0[1]),\n .I2(wait_cnt_r_reg__0[0]),\n .O(p_0_in[2]));\n LUT5 #(\n .INIT(32'h0080FFFF)) \n \\wait_cnt_r[3]_i_1 \n (.I0(wait_cnt_r_reg__0[2]),\n .I1(wait_cnt_r_reg__0[3]),\n .I2(wait_cnt_r_reg__0[1]),\n .I3(wait_cnt_r_reg__0[0]),\n .I4(wait_cnt_en_r),\n .O(\\wait_cnt_r[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair382\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\wait_cnt_r[3]_i_2 \n (.I0(wait_cnt_r_reg__0[3]),\n .I1(wait_cnt_r_reg__0[0]),\n .I2(wait_cnt_r_reg__0[1]),\n .I3(wait_cnt_r_reg__0[2]),\n .O(p_0_in[3]));\n FDRE #(\n .INIT(1'b0)) \n \\wait_cnt_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in[0]),\n .Q(wait_cnt_r_reg__0[0]),\n .R(\\wait_cnt_r[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\wait_cnt_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in[1]),\n .Q(wait_cnt_r_reg__0[1]),\n .R(\\wait_cnt_r[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\wait_cnt_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in[2]),\n .Q(wait_cnt_r_reg__0[2]),\n .R(\\wait_cnt_r[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\wait_cnt_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in[3]),\n .Q(wait_cnt_r_reg__0[3]),\n .R(\\wait_cnt_r[3]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFF7F0C00)) \n write_request_r_i_1\n (.I0(done_r_reg_1),\n .I1(write_request_r_i_2_n_0),\n .I2(lim_state[3]),\n .I3(lim_state[2]),\n .I4(lim2init_write_request),\n .O(write_request_r_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair369\" *) \n LUT5 #(\n .INIT(32'h00000002)) \n write_request_r_i_2\n (.I0(\\lim_state[4]_i_3_n_0 ),\n .I1(lim_state[4]),\n .I2(lim_state[13]),\n .I3(lim_state[1]),\n .I4(lim_state[0]),\n .O(write_request_r_i_2_n_0));\n FDRE #(\n .INIT(1'b0)) \n write_request_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(write_request_r_i_1_n_0),\n .Q(lim2init_write_request),\n .R(rstdiv0_sync_r1_reg_rep__9));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_phy_ocd_mux\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_phy_ocd_mux\n (po_rdy,\n po_stg23_incdec,\n \\po_wait_r_reg[3]_0 ,\n D_po_sel_fine_oclk_delay125_out,\n \\po_counter_read_val_reg[8] ,\n \\po_counter_read_val_reg[8]_0 ,\n \\po_counter_read_val_reg[8]_1 ,\n \\po_counter_read_val_reg[8]_2 ,\n \\po_counter_read_val_reg[8]_3 ,\n \\po_counter_read_val_reg[8]_4 ,\n \\po_counter_read_val_reg[8]_5 ,\n po_stg23_sel_r_reg_0,\n CLK,\n stg3_inc_req_r_reg,\n stg3_dec_req_r_reg,\n Q,\n calib_in_common,\n \\calib_zero_inputs_reg[1] ,\n rstdiv0_sync_r1_reg_rep__24,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n ck_addr_cmd_delay_done,\n oclkdelay_calib_done_r_reg,\n mpr_rdlvl_done_r_reg,\n \\gen_byte_sel_div1.calib_in_common_reg_0 ,\n \\gen_byte_sel_div1.calib_in_common_reg_1 ,\n \\gen_byte_sel_div1.calib_in_common_reg_2 ,\n stg2_dec_req_r_reg,\n setup_po,\n rstdiv0_sync_r1_reg_rep__10);\n output po_rdy;\n output po_stg23_incdec;\n output \\po_wait_r_reg[3]_0 ;\n output D_po_sel_fine_oclk_delay125_out;\n output \\po_counter_read_val_reg[8] ;\n output \\po_counter_read_val_reg[8]_0 ;\n output \\po_counter_read_val_reg[8]_1 ;\n output \\po_counter_read_val_reg[8]_2 ;\n output \\po_counter_read_val_reg[8]_3 ;\n output \\po_counter_read_val_reg[8]_4 ;\n output \\po_counter_read_val_reg[8]_5 ;\n output po_stg23_sel_r_reg_0;\n input CLK;\n input stg3_inc_req_r_reg;\n input stg3_dec_req_r_reg;\n input [1:0]Q;\n input calib_in_common;\n input [1:0]\\calib_zero_inputs_reg[1] ;\n input rstdiv0_sync_r1_reg_rep__24;\n input \\gen_byte_sel_div1.calib_in_common_reg ;\n input ck_addr_cmd_delay_done;\n input oclkdelay_calib_done_r_reg;\n input mpr_rdlvl_done_r_reg;\n input \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n input \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n input \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n input stg2_dec_req_r_reg;\n input setup_po;\n input rstdiv0_sync_r1_reg_rep__10;\n\n wire CLK;\n wire D_po_sel_fine_oclk_delay125_out;\n wire [1:0]Q;\n wire calib_in_common;\n wire [1:0]\\calib_zero_inputs_reg[1] ;\n wire ck_addr_cmd_delay_done;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n wire mpr_rdlvl_done_r_reg;\n wire oclkdelay_calib_done_r_reg;\n wire \\po_counter_read_val_reg[8] ;\n wire \\po_counter_read_val_reg[8]_0 ;\n wire \\po_counter_read_val_reg[8]_1 ;\n wire \\po_counter_read_val_reg[8]_2 ;\n wire \\po_counter_read_val_reg[8]_3 ;\n wire \\po_counter_read_val_reg[8]_4 ;\n wire \\po_counter_read_val_reg[8]_5 ;\n wire po_en_stg23_r_i_1_n_0;\n wire po_rdy;\n wire po_rdy_ns;\n wire [0:0]po_sel_stg2stg3;\n wire [1:0]po_setup_r;\n wire po_setup_r0;\n wire \\po_setup_r[0]_i_1_n_0 ;\n wire \\po_setup_r[1]_i_1_n_0 ;\n wire po_stg23_incdec;\n wire po_stg23_sel;\n wire po_stg23_sel_r_reg_0;\n wire [3:0]po_wait_r;\n wire \\po_wait_r[0]_i_1_n_0 ;\n wire \\po_wait_r[1]_i_1_n_0 ;\n wire \\po_wait_r[2]_i_1_n_0 ;\n wire \\po_wait_r[3]_i_1_n_0 ;\n wire \\po_wait_r_reg[3]_0 ;\n wire rstdiv0_sync_r1_reg_rep__10;\n wire rstdiv0_sync_r1_reg_rep__24;\n wire setup_po;\n wire stg2_dec_req_r_reg;\n wire stg3_dec_req_r_reg;\n wire stg3_inc_req_r_reg;\n\n LUT6 #(\n .INIT(64'h0000000000800000)) \n phaser_out_i_4__3\n (.I0(\\gen_byte_sel_div1.calib_in_common_reg ),\n .I1(ck_addr_cmd_delay_done),\n .I2(po_stg23_sel),\n .I3(oclkdelay_calib_done_r_reg),\n .I4(mpr_rdlvl_done_r_reg),\n .I5(\\calib_zero_inputs_reg[1] [0]),\n .O(\\po_counter_read_val_reg[8]_2 ));\n LUT6 #(\n .INIT(64'h0000000000800000)) \n phaser_out_i_4__4\n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .I1(ck_addr_cmd_delay_done),\n .I2(po_stg23_sel),\n .I3(oclkdelay_calib_done_r_reg),\n .I4(mpr_rdlvl_done_r_reg),\n .I5(\\calib_zero_inputs_reg[1] [0]),\n .O(\\po_counter_read_val_reg[8]_3 ));\n LUT6 #(\n .INIT(64'h0000000000800000)) \n phaser_out_i_4__5\n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .I1(ck_addr_cmd_delay_done),\n .I2(po_stg23_sel),\n .I3(oclkdelay_calib_done_r_reg),\n .I4(mpr_rdlvl_done_r_reg),\n .I5(\\calib_zero_inputs_reg[1] [0]),\n .O(\\po_counter_read_val_reg[8]_4 ));\n LUT6 #(\n .INIT(64'h0000000000800000)) \n phaser_out_i_4__6\n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_2 ),\n .I1(ck_addr_cmd_delay_done),\n .I2(po_stg23_sel),\n .I3(oclkdelay_calib_done_r_reg),\n .I4(mpr_rdlvl_done_r_reg),\n .I5(\\calib_zero_inputs_reg[1] [0]),\n .O(\\po_counter_read_val_reg[8]_5 ));\n (* SOFT_HLUTNM = \"soft_lutpair392\" *) \n LUT5 #(\n .INIT(32'h00000800)) \n phaser_out_i_5\n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(calib_in_common),\n .I3(po_sel_stg2stg3),\n .I4(\\calib_zero_inputs_reg[1] [1]),\n .O(D_po_sel_fine_oclk_delay125_out));\n (* SOFT_HLUTNM = \"soft_lutpair392\" *) \n LUT5 #(\n .INIT(32'h00000100)) \n phaser_out_i_5__0\n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(calib_in_common),\n .I3(po_sel_stg2stg3),\n .I4(\\calib_zero_inputs_reg[1] [1]),\n .O(\\po_counter_read_val_reg[8] ));\n (* SOFT_HLUTNM = \"soft_lutpair393\" *) \n LUT5 #(\n .INIT(32'h00000400)) \n phaser_out_i_5__1\n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(calib_in_common),\n .I3(po_sel_stg2stg3),\n .I4(\\calib_zero_inputs_reg[1] [1]),\n .O(\\po_counter_read_val_reg[8]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair393\" *) \n LUT5 #(\n .INIT(32'h00000400)) \n phaser_out_i_5__2\n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(calib_in_common),\n .I3(po_sel_stg2stg3),\n .I4(\\calib_zero_inputs_reg[1] [1]),\n .O(\\po_counter_read_val_reg[8]_1 ));\n LUT4 #(\n .INIT(16'h0800)) \n phaser_out_i_6\n (.I0(ck_addr_cmd_delay_done),\n .I1(po_stg23_sel),\n .I2(oclkdelay_calib_done_r_reg),\n .I3(mpr_rdlvl_done_r_reg),\n .O(po_sel_stg2stg3));\n (* SOFT_HLUTNM = \"soft_lutpair394\" *) \n LUT3 #(\n .INIT(8'h04)) \n po_en_stg23_r_i_1\n (.I0(rstdiv0_sync_r1_reg_rep__24),\n .I1(po_setup_r[0]),\n .I2(po_setup_r[1]),\n .O(po_en_stg23_r_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n po_en_stg23_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(po_en_stg23_r_i_1_n_0),\n .Q(\\po_wait_r_reg[3]_0 ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0000000000000001)) \n po_rdy_r_i_1\n (.I0(setup_po),\n .I1(\\po_wait_r[3]_i_1_n_0 ),\n .I2(po_setup_r0),\n .I3(\\po_wait_r[0]_i_1_n_0 ),\n .I4(\\po_wait_r[1]_i_1_n_0 ),\n .I5(\\po_wait_r[2]_i_1_n_0 ),\n .O(po_rdy_ns));\n (* SOFT_HLUTNM = \"soft_lutpair394\" *) \n LUT2 #(\n .INIT(4'hE)) \n po_rdy_r_i_3\n (.I0(po_setup_r[0]),\n .I1(po_setup_r[1]),\n .O(po_setup_r0));\n FDRE #(\n .INIT(1'b0)) \n po_rdy_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(po_rdy_ns),\n .Q(po_rdy),\n .R(1'b0));\n LUT3 #(\n .INIT(8'hF2)) \n \\po_setup_r[0]_i_1 \n (.I0(po_setup_r[1]),\n .I1(po_setup_r[0]),\n .I2(setup_po),\n .O(\\po_setup_r[0]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hF8)) \n \\po_setup_r[1]_i_1 \n (.I0(po_setup_r[1]),\n .I1(po_setup_r[0]),\n .I2(setup_po),\n .O(\\po_setup_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\po_setup_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_setup_r[0]_i_1_n_0 ),\n .Q(po_setup_r[0]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE #(\n .INIT(1'b0)) \n \\po_setup_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_setup_r[1]_i_1_n_0 ),\n .Q(po_setup_r[1]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE #(\n .INIT(1'b0)) \n po_stg23_incdec_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(stg3_inc_req_r_reg),\n .Q(po_stg23_incdec),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h5555555100000000)) \n po_stg23_sel_r_i_2\n (.I0(stg2_dec_req_r_reg),\n .I1(po_wait_r[0]),\n .I2(po_wait_r[1]),\n .I3(po_wait_r[3]),\n .I4(po_wait_r[2]),\n .I5(po_stg23_sel),\n .O(po_stg23_sel_r_reg_0));\n FDRE #(\n .INIT(1'b0)) \n po_stg23_sel_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(stg3_dec_req_r_reg),\n .Q(po_stg23_sel),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000000000FE)) \n \\po_wait_r[0]_i_1 \n (.I0(po_wait_r[1]),\n .I1(po_wait_r[2]),\n .I2(po_wait_r[3]),\n .I3(rstdiv0_sync_r1_reg_rep__24),\n .I4(po_wait_r[0]),\n .I5(\\po_wait_r_reg[3]_0 ),\n .O(\\po_wait_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h5445544554455444)) \n \\po_wait_r[1]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__24),\n .I1(\\po_wait_r_reg[3]_0 ),\n .I2(po_wait_r[0]),\n .I3(po_wait_r[1]),\n .I4(po_wait_r[2]),\n .I5(po_wait_r[3]),\n .O(\\po_wait_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h5554444555544444)) \n \\po_wait_r[2]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__24),\n .I1(\\po_wait_r_reg[3]_0 ),\n .I2(po_wait_r[0]),\n .I3(po_wait_r[1]),\n .I4(po_wait_r[2]),\n .I5(po_wait_r[3]),\n .O(\\po_wait_r[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h5555555444444444)) \n \\po_wait_r[3]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__24),\n .I1(\\po_wait_r_reg[3]_0 ),\n .I2(po_wait_r[2]),\n .I3(po_wait_r[0]),\n .I4(po_wait_r[1]),\n .I5(po_wait_r[3]),\n .O(\\po_wait_r[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\po_wait_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_wait_r[0]_i_1_n_0 ),\n .Q(po_wait_r[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\po_wait_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_wait_r[1]_i_1_n_0 ),\n .Q(po_wait_r[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\po_wait_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_wait_r[2]_i_1_n_0 ),\n .Q(po_wait_r[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\po_wait_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_wait_r[3]_i_1_n_0 ),\n .Q(po_wait_r[3]),\n .R(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_phy_ocd_po_cntlr\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_phy_ocd_po_cntlr\n (O,\n ocal_last_byte_done_reg,\n oclk_center_write_resume,\n complex_ocal_num_samples_done_r,\n \\sm_r_reg[3]_0 ,\n oclkdelay_center_calib_start_r_reg_0,\n scanning_right,\n S,\n Q,\n po_stg23_incdec_r_reg,\n setup_po,\n \\stg2_r_reg[0]_0 ,\n \\two_r_reg[1]_0 ,\n E,\n o2f_r_reg,\n f2z_r_reg,\n \\stg2_target_r_reg[8]_0 ,\n po_stg23_incdec_r_reg_0,\n \\stg3_init_val_reg[5] ,\n \\stg3_init_val_reg[3] ,\n \\stg3_init_val_reg[4] ,\n \\stg3_init_val_reg[2] ,\n \\stg3_init_val_reg[1] ,\n \\stg3_init_val_reg[0] ,\n \\rise_trail_r_reg[5] ,\n \\run_ends_r_reg[1] ,\n \\sm_r_reg[0]_0 ,\n D,\n samp_done_ns8_out,\n ninety_offsets,\n use_noise_window,\n \\init_state_r_reg[0] ,\n poc_backup_r_reg_0,\n edge_aligned_r_reg,\n \\stg3_init_val_reg[4]_0 ,\n \\stg3_init_val_reg[2]_0 ,\n rstdiv0_sync_r1_reg_rep__10,\n CLK,\n dec_po_ns,\n inc_po_ns,\n rstdiv0_sync_r1_reg_rep__9,\n \\wl_po_fine_cnt_reg[14] ,\n \\stg3_r_reg[0]_0 ,\n f2o_r_reg,\n f2o_r_reg_0,\n rstdiv0_sync_r1_reg_rep__25,\n lim2stg3_inc,\n po_stg23_incdec,\n ocd_cntlr2stg2_dec_r,\n scanning_right_r_reg_0,\n scan_right_r_reg,\n samp_done,\n rd_active_r2,\n poc_backup_r_reg_1,\n done_r_reg,\n rstdiv0_sync_r1_reg_rep__24,\n o2f_ns1_out,\n o2f_r_reg_0,\n f2z_ns5_out,\n f2z_r_reg_0,\n rstdiv0_sync_r1_reg_rep__20,\n lim2stg3_dec,\n lim2stg2_dec,\n \\byte_r_reg[0] ,\n \\wl_po_fine_cnt_reg[3] ,\n \\wl_po_fine_cnt_reg[17] ,\n \\wl_po_fine_cnt_reg[18] ,\n \\byte_r_reg[0]_0 ,\n \\byte_r_reg[1] ,\n oclkdelay_calib_done_r_reg,\n lim2poc_ktap_right,\n lim2poc_rdy,\n po_rdy,\n lim2stg2_inc,\n edge_aligned_r_reg_0,\n \\sm_r_reg[0]_1 ,\n reset_scan,\n rstdiv0_sync_r1_reg_rep__25_0,\n samp_done_r_reg,\n wrlvl_final_mux,\n oclkdelay_int_ref_req_reg,\n prech_req_posedge_r_reg,\n oclkdelay_calib_done_r_reg_0,\n \\run_ends_r_reg[1]_0 ,\n \\run_ends_r_reg[0] ,\n \\po_counter_read_val_reg[5] ,\n \\byte_r_reg[0]_1 ,\n \\byte_r_reg[1]_0 ,\n \\byte_r_reg[0]_2 ,\n \\byte_r_reg[0]_3 ,\n \\wl_po_fine_cnt_reg[23] );\n output [3:0]O;\n output ocal_last_byte_done_reg;\n output oclk_center_write_resume;\n output complex_ocal_num_samples_done_r;\n output \\sm_r_reg[3]_0 ;\n output oclkdelay_center_calib_start_r_reg_0;\n output scanning_right;\n output [0:0]S;\n output [5:0]Q;\n output po_stg23_incdec_r_reg;\n output setup_po;\n output [0:0]\\stg2_r_reg[0]_0 ;\n output \\two_r_reg[1]_0 ;\n output [0:0]E;\n output o2f_r_reg;\n output f2z_r_reg;\n output [2:0]\\stg2_target_r_reg[8]_0 ;\n output po_stg23_incdec_r_reg_0;\n output \\stg3_init_val_reg[5] ;\n output [0:0]\\stg3_init_val_reg[3] ;\n output \\stg3_init_val_reg[4] ;\n output \\stg3_init_val_reg[2] ;\n output \\stg3_init_val_reg[1] ;\n output \\stg3_init_val_reg[0] ;\n output \\rise_trail_r_reg[5] ;\n output \\run_ends_r_reg[1] ;\n output \\sm_r_reg[0]_0 ;\n output [5:0]D;\n output samp_done_ns8_out;\n output [1:0]ninety_offsets;\n output use_noise_window;\n output \\init_state_r_reg[0] ;\n output poc_backup_r_reg_0;\n output edge_aligned_r_reg;\n output \\stg3_init_val_reg[4]_0 ;\n output \\stg3_init_val_reg[2]_0 ;\n input rstdiv0_sync_r1_reg_rep__10;\n input CLK;\n input dec_po_ns;\n input inc_po_ns;\n input rstdiv0_sync_r1_reg_rep__9;\n input [1:0]\\wl_po_fine_cnt_reg[14] ;\n input \\stg3_r_reg[0]_0 ;\n input f2o_r_reg;\n input f2o_r_reg_0;\n input rstdiv0_sync_r1_reg_rep__25;\n input lim2stg3_inc;\n input po_stg23_incdec;\n input ocd_cntlr2stg2_dec_r;\n input scanning_right_r_reg_0;\n input scan_right_r_reg;\n input samp_done;\n input rd_active_r2;\n input poc_backup_r_reg_1;\n input done_r_reg;\n input rstdiv0_sync_r1_reg_rep__24;\n input o2f_ns1_out;\n input o2f_r_reg_0;\n input f2z_ns5_out;\n input f2z_r_reg_0;\n input rstdiv0_sync_r1_reg_rep__20;\n input lim2stg3_dec;\n input lim2stg2_dec;\n input \\byte_r_reg[0] ;\n input \\wl_po_fine_cnt_reg[3] ;\n input \\wl_po_fine_cnt_reg[17] ;\n input \\wl_po_fine_cnt_reg[18] ;\n input \\byte_r_reg[0]_0 ;\n input \\byte_r_reg[1] ;\n input oclkdelay_calib_done_r_reg;\n input lim2poc_ktap_right;\n input lim2poc_rdy;\n input po_rdy;\n input lim2stg2_inc;\n input edge_aligned_r_reg_0;\n input \\sm_r_reg[0]_1 ;\n input reset_scan;\n input rstdiv0_sync_r1_reg_rep__25_0;\n input samp_done_r_reg;\n input wrlvl_final_mux;\n input oclkdelay_int_ref_req_reg;\n input prech_req_posedge_r_reg;\n input oclkdelay_calib_done_r_reg_0;\n input \\run_ends_r_reg[1]_0 ;\n input \\run_ends_r_reg[0] ;\n input [5:0]\\po_counter_read_val_reg[5] ;\n input \\byte_r_reg[0]_1 ;\n input \\byte_r_reg[1]_0 ;\n input \\byte_r_reg[0]_2 ;\n input \\byte_r_reg[0]_3 ;\n input [7:0]\\wl_po_fine_cnt_reg[23] ;\n\n wire [8:0]A;\n wire CLK;\n wire [5:0]D;\n wire [0:0]E;\n wire [3:0]O;\n wire [5:0]Q;\n wire [0:0]S;\n wire \\byte_r_reg[0] ;\n wire \\byte_r_reg[0]_0 ;\n wire \\byte_r_reg[0]_1 ;\n wire \\byte_r_reg[0]_2 ;\n wire \\byte_r_reg[0]_3 ;\n wire \\byte_r_reg[1] ;\n wire \\byte_r_reg[1]_0 ;\n wire cmplx_samples_done_r_i_2_n_0;\n wire cmplx_samples_done_r_i_3_n_0;\n wire complex_ocal_num_samples_done_r;\n wire dec_po_ns;\n wire dec_po_r;\n wire done_r_reg;\n wire edge_aligned_r_reg;\n wire edge_aligned_r_reg_0;\n wire f2o_r_reg;\n wire f2o_r_reg_0;\n wire f2z_ns5_out;\n wire f2z_r_reg;\n wire f2z_r_reg_0;\n wire inc_po_ns;\n wire inc_po_r;\n wire \\init_state_r_reg[0] ;\n wire lim2poc_ktap_right;\n wire lim2poc_rdy;\n wire lim2stg2_dec;\n wire lim2stg2_inc;\n wire lim2stg3_dec;\n wire lim2stg3_inc;\n wire [1:0]ninety_offsets;\n wire [1:0]ninety_offsets_final_r;\n wire ninety_offsets_ns;\n wire \\ninety_offsets_r[0]_i_1_n_0 ;\n wire \\ninety_offsets_r[1]_i_1_n_0 ;\n wire \\ninety_offsets_r[1]_i_3_n_0 ;\n wire \\ninety_offsets_r[1]_i_4_n_0 ;\n wire o2f_ns1_out;\n wire o2f_r_reg;\n wire o2f_r_reg_0;\n wire ocal_last_byte_done_reg;\n wire ocd2stg3_dec;\n wire ocd_cntlr2stg2_dec_r;\n wire ocd_edge_detect_rdy;\n wire ocd_edge_detect_rdy_r_i_1_n_0;\n wire ocd_ktap_left_r_i_2_n_0;\n wire ocd_ktap_left_r_i_3_n_0;\n wire ocd_ktap_left_r_i_4_n_0;\n wire ocd_ktap_right;\n wire ocd_ktap_right_r_i_1_n_0;\n wire oclk_calib_resume_r_i_5_n_0;\n wire oclk_center_write_resume;\n wire oclk_center_write_resume_r_i_2_n_0;\n wire oclk_center_write_resume_r_i_3_n_0;\n wire oclk_center_write_resume_r_i_4_n_0;\n wire oclk_center_write_resume_r_i_5_n_0;\n wire oclkdelay_calib_done_r_reg;\n wire oclkdelay_calib_done_r_reg_0;\n wire oclkdelay_center_calib_done_r_i_1_n_0;\n wire oclkdelay_center_calib_done_r_i_2_n_0;\n wire oclkdelay_center_calib_done_r_i_3_n_0;\n wire oclkdelay_center_calib_done_r_i_4_n_0;\n wire oclkdelay_center_calib_start_r_i_1_n_0;\n wire oclkdelay_center_calib_start_r_reg_0;\n wire oclkdelay_int_ref_req_reg;\n wire [8:1]out;\n wire [5:0]p_0_in;\n wire p_0_in0_carry__0_i_1_n_0;\n wire p_0_in0_carry__0_i_2_n_0;\n wire p_0_in0_carry__0_i_3_n_0;\n wire p_0_in0_carry__0_i_4_n_0;\n wire p_0_in0_carry__0_n_2;\n wire p_0_in0_carry__0_n_3;\n wire p_0_in0_carry__0_n_5;\n wire p_0_in0_carry__0_n_6;\n wire p_0_in0_carry__0_n_7;\n wire p_0_in0_carry_i_10_n_0;\n wire p_0_in0_carry_i_10_n_1;\n wire p_0_in0_carry_i_10_n_2;\n wire p_0_in0_carry_i_10_n_3;\n wire p_0_in0_carry_i_10_n_4;\n wire p_0_in0_carry_i_10_n_5;\n wire p_0_in0_carry_i_10_n_6;\n wire p_0_in0_carry_i_11_n_3;\n wire p_0_in0_carry_i_11_n_6;\n wire p_0_in0_carry_i_11_n_7;\n wire p_0_in0_carry_i_12_n_3;\n wire p_0_in0_carry_i_13_n_0;\n wire p_0_in0_carry_i_14_n_0;\n wire p_0_in0_carry_i_15_n_0;\n wire p_0_in0_carry_i_16_n_0;\n wire p_0_in0_carry_i_17_n_0;\n wire p_0_in0_carry_i_18_n_0;\n wire p_0_in0_carry_i_19_n_0;\n wire p_0_in0_carry_i_1_n_0;\n wire p_0_in0_carry_i_20_n_0;\n wire p_0_in0_carry_i_21_n_0;\n wire p_0_in0_carry_i_22_n_0;\n wire p_0_in0_carry_i_23_n_0;\n wire p_0_in0_carry_i_24_n_0;\n wire p_0_in0_carry_i_2_n_0;\n wire p_0_in0_carry_i_3_n_0;\n wire p_0_in0_carry_i_4_n_0;\n wire p_0_in0_carry_i_5_n_0;\n wire p_0_in0_carry_i_6_n_0;\n wire p_0_in0_carry_i_7_n_0;\n wire p_0_in0_carry_i_8_n_0;\n wire p_0_in0_carry_i_8_n_1;\n wire p_0_in0_carry_i_8_n_2;\n wire p_0_in0_carry_i_8_n_3;\n wire p_0_in0_carry_i_9_n_0;\n wire p_0_in0_carry_n_0;\n wire p_0_in0_carry_n_1;\n wire p_0_in0_carry_n_2;\n wire p_0_in0_carry_n_3;\n wire p_1_in;\n wire p_55_in;\n wire p_58_in;\n wire p_63_in;\n wire [5:0]po_counter_read_val_r;\n wire [5:0]\\po_counter_read_val_reg[5] ;\n wire po_done_ns;\n wire po_done_r;\n wire po_done_r_i_1_n_0;\n wire po_rdy;\n wire po_rdy_r_i_5_n_0;\n wire po_rdy_r_i_6_n_0;\n wire po_rdy_r_i_7_n_0;\n wire po_stg23_incdec;\n wire po_stg23_incdec_r_i_10_n_0;\n wire po_stg23_incdec_r_i_2_n_0;\n wire po_stg23_incdec_r_i_3_n_0;\n wire po_stg23_incdec_r_i_4_n_0;\n wire po_stg23_incdec_r_i_5_n_0;\n wire po_stg23_incdec_r_i_6_n_0;\n wire po_stg23_incdec_r_i_7_n_0;\n wire po_stg23_incdec_r_i_8_n_0;\n wire po_stg23_incdec_r_i_9_n_0;\n wire po_stg23_incdec_r_reg;\n wire po_stg23_incdec_r_reg_0;\n wire poc_backup_r;\n wire poc_backup_r_i_1__0_n_0;\n wire poc_backup_r_i_2__0_n_0;\n wire poc_backup_r_i_3_n_0;\n wire poc_backup_r_i_4_n_0;\n wire poc_backup_r_i_5_n_0;\n wire poc_backup_r_reg_0;\n wire poc_backup_r_reg_1;\n wire prech_req_posedge_r_reg;\n wire rd_active_r2;\n wire reset_scan;\n wire [9:5]resume_wait_ns0;\n wire [10:0]resume_wait_r;\n wire \\resume_wait_r[0]_i_1_n_0 ;\n wire \\resume_wait_r[10]_i_1_n_0 ;\n wire \\resume_wait_r[10]_i_2_n_0 ;\n wire \\resume_wait_r[10]_i_3_n_0 ;\n wire \\resume_wait_r[10]_i_4_n_0 ;\n wire \\resume_wait_r[1]_i_1_n_0 ;\n wire \\resume_wait_r[2]_i_1_n_0 ;\n wire \\resume_wait_r[2]_i_2_n_0 ;\n wire \\resume_wait_r[3]_i_1_n_0 ;\n wire \\resume_wait_r[4]_i_1_n_0 ;\n wire \\resume_wait_r[4]_i_2_n_0 ;\n wire \\resume_wait_r[7]_i_2_n_0 ;\n wire \\resume_wait_r[9]_i_1_n_0 ;\n wire \\resume_wait_r[9]_i_4_n_0 ;\n wire \\resume_wait_r[9]_i_5_n_0 ;\n wire \\resume_wait_r[9]_i_6_n_0 ;\n wire \\resume_wait_r[9]_i_7_n_0 ;\n wire \\resume_wait_r[9]_i_8_n_0 ;\n wire \\rise_trail_r_reg[5] ;\n wire rstdiv0_sync_r1_reg_rep__10;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__24;\n wire rstdiv0_sync_r1_reg_rep__25;\n wire rstdiv0_sync_r1_reg_rep__25_0;\n wire rstdiv0_sync_r1_reg_rep__9;\n wire \\run_ends_r_reg[0] ;\n wire \\run_ends_r_reg[1] ;\n wire \\run_ends_r_reg[1]_0 ;\n wire samp_done;\n wire samp_done_ns8_out;\n wire samp_done_r_reg;\n wire scan_right_r_reg;\n wire scanning_right;\n wire scanning_right_r_i_1_n_0;\n wire scanning_right_r_i_3_n_0;\n wire scanning_right_r_reg_0;\n wire setup_po;\n wire \\simp_stg3_final_r_reg_n_0_[0] ;\n wire \\simp_stg3_final_r_reg_n_0_[10] ;\n wire \\simp_stg3_final_r_reg_n_0_[11] ;\n wire \\simp_stg3_final_r_reg_n_0_[12] ;\n wire \\simp_stg3_final_r_reg_n_0_[13] ;\n wire \\simp_stg3_final_r_reg_n_0_[14] ;\n wire \\simp_stg3_final_r_reg_n_0_[15] ;\n wire \\simp_stg3_final_r_reg_n_0_[17] ;\n wire \\simp_stg3_final_r_reg_n_0_[18] ;\n wire \\simp_stg3_final_r_reg_n_0_[19] ;\n wire \\simp_stg3_final_r_reg_n_0_[1] ;\n wire \\simp_stg3_final_r_reg_n_0_[20] ;\n wire \\simp_stg3_final_r_reg_n_0_[21] ;\n wire \\simp_stg3_final_r_reg_n_0_[22] ;\n wire \\simp_stg3_final_r_reg_n_0_[23] ;\n wire \\simp_stg3_final_r_reg_n_0_[3] ;\n wire \\simp_stg3_final_r_reg_n_0_[4] ;\n wire \\simp_stg3_final_r_reg_n_0_[5] ;\n wire \\simp_stg3_final_r_reg_n_0_[6] ;\n wire \\simp_stg3_final_r_reg_n_0_[7] ;\n wire \\simp_stg3_final_r_reg_n_0_[8] ;\n wire \\simp_stg3_final_r_reg_n_0_[9] ;\n wire sm_ns;\n wire [3:0]sm_r;\n wire \\sm_r[0]_i_1_n_0 ;\n wire \\sm_r[0]_i_2__0_n_0 ;\n wire \\sm_r[0]_i_3_n_0 ;\n wire \\sm_r[1]_i_1_n_0 ;\n wire \\sm_r[1]_i_2_n_0 ;\n wire \\sm_r[2]_i_1_n_0 ;\n wire \\sm_r[2]_i_2_n_0 ;\n wire \\sm_r[3]_i_10_n_0 ;\n wire \\sm_r[3]_i_2_n_0 ;\n wire \\sm_r[3]_i_3_n_0 ;\n wire \\sm_r[3]_i_4_n_0 ;\n wire \\sm_r[3]_i_6_n_0 ;\n wire \\sm_r[3]_i_7_n_0 ;\n wire \\sm_r[3]_i_8_n_0 ;\n wire \\sm_r[3]_i_9_n_0 ;\n wire \\sm_r_reg[0]_0 ;\n wire \\sm_r_reg[0]_1 ;\n wire \\sm_r_reg[3]_0 ;\n wire [5:0]stg2_final_r;\n wire \\stg2_final_r[0]_i_1_n_0 ;\n wire \\stg2_final_r[1]_i_1_n_0 ;\n wire \\stg2_final_r[2]_i_1_n_0 ;\n wire \\stg2_final_r[3]_i_1_n_0 ;\n wire \\stg2_final_r[4]_i_1_n_0 ;\n wire \\stg2_final_r[5]_i_1_n_0 ;\n wire [8:0]stg2_ns;\n wire stg2_ns0_carry__0_i_1_n_0;\n wire stg2_ns0_carry__0_i_2_n_0;\n wire stg2_ns0_carry__0_i_3_n_0;\n wire stg2_ns0_carry__0_i_4_n_0;\n wire stg2_ns0_carry__0_n_1;\n wire stg2_ns0_carry__0_n_2;\n wire stg2_ns0_carry__0_n_3;\n wire stg2_ns0_carry_i_1_n_0;\n wire stg2_ns0_carry_i_2_n_0;\n wire stg2_ns0_carry_i_3_n_0;\n wire stg2_ns0_carry_i_4_n_0;\n wire stg2_ns0_carry_n_0;\n wire stg2_ns0_carry_n_1;\n wire stg2_ns0_carry_n_2;\n wire stg2_ns0_carry_n_3;\n wire \\stg2_r[8]_i_1_n_0 ;\n wire \\stg2_r[8]_i_3_n_0 ;\n wire [0:0]\\stg2_r_reg[0]_0 ;\n wire [1:1]stg2_target_ns;\n wire [2:0]\\stg2_target_r_reg[8]_0 ;\n wire \\stg2_target_r_reg_n_0_[0] ;\n wire \\stg2_target_r_reg_n_0_[1] ;\n wire \\stg2_target_r_reg_n_0_[2] ;\n wire \\stg2_target_r_reg_n_0_[3] ;\n wire \\stg2_target_r_reg_n_0_[4] ;\n wire \\stg2_target_r_reg_n_0_[5] ;\n wire \\stg2_target_r_reg_n_0_[6] ;\n wire \\stg2_target_r_reg_n_0_[7] ;\n wire \\stg3_init_val[3]_i_2_n_0 ;\n wire \\stg3_init_val_reg[0] ;\n wire \\stg3_init_val_reg[1] ;\n wire \\stg3_init_val_reg[2] ;\n wire \\stg3_init_val_reg[2]_0 ;\n wire [0:0]\\stg3_init_val_reg[3] ;\n wire \\stg3_init_val_reg[4] ;\n wire \\stg3_init_val_reg[4]_0 ;\n wire \\stg3_init_val_reg[5] ;\n wire [5:0]stg3_ns;\n wire \\stg3_r[5]_i_10_n_0 ;\n wire \\stg3_r[5]_i_11_n_0 ;\n wire \\stg3_r[5]_i_12_n_0 ;\n wire \\stg3_r[5]_i_1_n_0 ;\n wire \\stg3_r[5]_i_4_n_0 ;\n wire \\stg3_r[5]_i_5_n_0 ;\n wire \\stg3_r[5]_i_6_n_0 ;\n wire \\stg3_r[5]_i_7_n_0 ;\n wire \\stg3_r[5]_i_9_n_0 ;\n wire \\stg3_r_reg[0]_0 ;\n wire [1:0]two_r;\n wire \\two_r[0]_i_1_n_0 ;\n wire \\two_r[1]_i_1_n_0 ;\n wire \\two_r[1]_i_2_n_0 ;\n wire \\two_r_reg[1]_0 ;\n wire up_r;\n wire up_r_i_1_n_0;\n wire use_noise_window;\n wire [1:0]\\wl_po_fine_cnt_reg[14] ;\n wire \\wl_po_fine_cnt_reg[17] ;\n wire \\wl_po_fine_cnt_reg[18] ;\n wire [7:0]\\wl_po_fine_cnt_reg[23] ;\n wire \\wl_po_fine_cnt_reg[3] ;\n wire wrlvl_final_mux;\n wire [3:2]NLW_p_0_in0_carry__0_CO_UNCONNECTED;\n wire [3:3]NLW_p_0_in0_carry__0_O_UNCONNECTED;\n wire [3:1]NLW_p_0_in0_carry_i_11_CO_UNCONNECTED;\n wire [3:2]NLW_p_0_in0_carry_i_11_O_UNCONNECTED;\n wire [3:1]NLW_p_0_in0_carry_i_12_CO_UNCONNECTED;\n wire [3:2]NLW_p_0_in0_carry_i_12_O_UNCONNECTED;\n wire [0:0]NLW_p_0_in0_carry_i_8_O_UNCONNECTED;\n wire [3:3]NLW_stg2_ns0_carry__0_CO_UNCONNECTED;\n\n LUT3 #(\n .INIT(8'h04)) \n cmplx_samples_done_r_i_1\n (.I0(rstdiv0_sync_r1_reg_rep__25),\n .I1(complex_ocal_num_samples_done_r),\n .I2(cmplx_samples_done_r_i_2_n_0),\n .O(p_58_in));\n LUT5 #(\n .INIT(32'h0008AAAA)) \n cmplx_samples_done_r_i_2\n (.I0(oclk_calib_resume_r_i_5_n_0),\n .I1(cmplx_samples_done_r_i_3_n_0),\n .I2(inc_po_r),\n .I3(dec_po_r),\n .I4(sm_r[0]),\n .O(cmplx_samples_done_r_i_2_n_0));\n LUT3 #(\n .INIT(8'h08)) \n cmplx_samples_done_r_i_3\n (.I0(po_done_r),\n .I1(\\stg2_r_reg[0]_0 ),\n .I2(E),\n .O(cmplx_samples_done_r_i_3_n_0));\n FDRE #(\n .INIT(1'b0)) \n cmplx_samples_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(p_58_in),\n .Q(complex_ocal_num_samples_done_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n dec_po_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(dec_po_ns),\n .Q(dec_po_r),\n .R(1'b0));\n LUT2 #(\n .INIT(4'hE)) \n done_r_i_2__0\n (.I0(ocd_edge_detect_rdy),\n .I1(lim2poc_rdy),\n .O(\\run_ends_r_reg[1] ));\n LUT2 #(\n .INIT(4'hE)) \n edge_aligned_r_i_4\n (.I0(\\sm_r_reg[3]_0 ),\n .I1(\\rise_trail_r_reg[5] ),\n .O(edge_aligned_r_reg));\n (* SOFT_HLUTNM = \"soft_lutpair418\" *) \n LUT3 #(\n .INIT(8'hB8)) \n f2z_r_i_1\n (.I0(scanning_right),\n .I1(f2z_ns5_out),\n .I2(f2z_r_reg_0),\n .O(f2z_r_reg));\n LUT2 #(\n .INIT(4'h2)) \n i___15_i_1\n (.I0(ninety_offsets[0]),\n .I1(ninety_offsets[1]),\n .O(use_noise_window));\n (* SOFT_HLUTNM = \"soft_lutpair413\" *) \n LUT2 #(\n .INIT(4'hE)) \n i___7_i_2__0\n (.I0(ocd_ktap_right),\n .I1(lim2poc_ktap_right),\n .O(\\rise_trail_r_reg[5] ));\n FDRE #(\n .INIT(1'b0)) \n inc_po_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(inc_po_ns),\n .Q(inc_po_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n \\init_state_r[5]_i_55 \n (.I0(oclkdelay_center_calib_start_r_reg_0),\n .I1(wrlvl_final_mux),\n .I2(oclkdelay_int_ref_req_reg),\n .I3(prech_req_posedge_r_reg),\n .I4(oclkdelay_calib_done_r_reg_0),\n .O(\\init_state_r_reg[0] ));\n FDRE #(\n .INIT(1'b0)) \n \\ninety_offsets_final_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(f2o_r_reg_0),\n .Q(ninety_offsets_final_r[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\ninety_offsets_final_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(f2o_r_reg),\n .Q(ninety_offsets_final_r[1]),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hE0FFEF00)) \n \\ninety_offsets_r[0]_i_1 \n (.I0(ninety_offsets_final_r[1]),\n .I1(ninety_offsets_final_r[0]),\n .I2(sm_r[0]),\n .I3(ninety_offsets_ns),\n .I4(ninety_offsets[0]),\n .O(\\ninety_offsets_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair406\" *) \n LUT4 #(\n .INIT(16'h4F80)) \n \\ninety_offsets_r[1]_i_1 \n (.I0(ninety_offsets[0]),\n .I1(sm_r[2]),\n .I2(ninety_offsets_ns),\n .I3(ninety_offsets[1]),\n .O(\\ninety_offsets_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF00000040)) \n \\ninety_offsets_r[1]_i_2 \n (.I0(sm_r[2]),\n .I1(sm_r[0]),\n .I2(\\stg2_r_reg[0]_0 ),\n .I3(sm_r[3]),\n .I4(rstdiv0_sync_r1_reg_rep__25),\n .I5(\\ninety_offsets_r[1]_i_3_n_0 ),\n .O(ninety_offsets_ns));\n LUT6 #(\n .INIT(64'h0000000001000000)) \n \\ninety_offsets_r[1]_i_3 \n (.I0(sm_r[3]),\n .I1(rstdiv0_sync_r1_reg_rep__25),\n .I2(\\ninety_offsets_r[1]_i_4_n_0 ),\n .I3(oclk_center_write_resume_r_i_5_n_0),\n .I4(done_r_reg),\n .I5(E),\n .O(\\ninety_offsets_r[1]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair401\" *) \n LUT5 #(\n .INIT(32'hFFFFFFFB)) \n \\ninety_offsets_r[1]_i_4 \n (.I0(\\stg2_r_reg[0]_0 ),\n .I1(sm_r[2]),\n .I2(sm_r[0]),\n .I3(\\sm_r_reg[3]_0 ),\n .I4(ocd_ktap_right),\n .O(\\ninety_offsets_r[1]_i_4_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\ninety_offsets_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ninety_offsets_r[0]_i_1_n_0 ),\n .Q(ninety_offsets[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\ninety_offsets_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ninety_offsets_r[1]_i_1_n_0 ),\n .Q(ninety_offsets[1]),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair418\" *) \n LUT3 #(\n .INIT(8'hB8)) \n o2f_r_i_1\n (.I0(scanning_right),\n .I1(o2f_ns1_out),\n .I2(o2f_r_reg_0),\n .O(o2f_r_reg));\n (* SOFT_HLUTNM = \"soft_lutpair403\" *) \n LUT5 #(\n .INIT(32'hFDFF0100)) \n ocd_edge_detect_rdy_r_i_1\n (.I0(done_r_reg),\n .I1(E),\n .I2(sm_r[3]),\n .I3(\\sm_r[3]_i_6_n_0 ),\n .I4(ocd_edge_detect_rdy),\n .O(ocd_edge_detect_rdy_r_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n ocd_edge_detect_rdy_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(ocd_edge_detect_rdy_r_i_1_n_0),\n .Q(ocd_edge_detect_rdy),\n .R(rstdiv0_sync_r1_reg_rep__10));\n LUT6 #(\n .INIT(64'h00000000EEEEEEE0)) \n ocd_ktap_left_r_i_1\n (.I0(ocd_ktap_left_r_i_2_n_0),\n .I1(\\sm_r_reg[3]_0 ),\n .I2(sm_r[0]),\n .I3(\\stg2_r_reg[0]_0 ),\n .I4(ocd_ktap_left_r_i_3_n_0),\n .I5(rstdiv0_sync_r1_reg_rep__20),\n .O(p_55_in));\n LUT6 #(\n .INIT(64'h2000000000000000)) \n ocd_ktap_left_r_i_2\n (.I0(scanning_right_r_reg_0),\n .I1(\\stg2_r_reg[0]_0 ),\n .I2(rd_active_r2),\n .I3(samp_done),\n .I4(sm_r[0]),\n .I5(ocd_ktap_left_r_i_4_n_0),\n .O(ocd_ktap_left_r_i_2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair408\" *) \n LUT4 #(\n .INIT(16'hFFDF)) \n ocd_ktap_left_r_i_3\n (.I0(sm_r[2]),\n .I1(sm_r[3]),\n .I2(done_r_reg),\n .I3(E),\n .O(ocd_ktap_left_r_i_3_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair406\" *) \n LUT2 #(\n .INIT(4'h1)) \n ocd_ktap_left_r_i_4\n (.I0(sm_r[3]),\n .I1(sm_r[2]),\n .O(ocd_ktap_left_r_i_4_n_0));\n FDRE #(\n .INIT(1'b0)) \n ocd_ktap_left_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(p_55_in),\n .Q(\\sm_r_reg[3]_0 ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFFF0200FDFF0000)) \n ocd_ktap_right_r_i_1\n (.I0(\\sm_r[3]_i_6_n_0 ),\n .I1(sm_r[3]),\n .I2(E),\n .I3(done_r_reg),\n .I4(ocd_ktap_right),\n .I5(\\sm_r_reg[3]_0 ),\n .O(ocd_ktap_right_r_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n ocd_ktap_right_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(ocd_ktap_right_r_i_1_n_0),\n .Q(ocd_ktap_right),\n .R(rstdiv0_sync_r1_reg_rep__9));\n LUT4 #(\n .INIT(16'h0002)) \n oclk_calib_resume_r_i_2\n (.I0(oclk_calib_resume_r_i_5_n_0),\n .I1(rstdiv0_sync_r1_reg_rep__25),\n .I2(\\sm_r_reg[0]_1 ),\n .I3(sm_r[0]),\n .O(samp_done_ns8_out));\n LUT6 #(\n .INIT(64'h00000000000000A3)) \n oclk_calib_resume_r_i_5\n (.I0(po_done_r),\n .I1(reset_scan),\n .I2(\\stg2_r_reg[0]_0 ),\n .I3(sm_r[3]),\n .I4(sm_r[2]),\n .I5(E),\n .O(oclk_calib_resume_r_i_5_n_0));\n LUT6 #(\n .INIT(64'hFFFF008000000000)) \n oclk_center_write_resume_r_i_1\n (.I0(oclk_center_write_resume_r_i_2_n_0),\n .I1(\\stg2_r_reg[0]_0 ),\n .I2(po_done_r),\n .I3(sm_r[3]),\n .I4(oclk_center_write_resume),\n .I5(oclk_center_write_resume_r_i_3_n_0),\n .O(p_63_in));\n LUT4 #(\n .INIT(16'hAAAB)) \n oclk_center_write_resume_r_i_2\n (.I0(sm_r[2]),\n .I1(dec_po_r),\n .I2(inc_po_r),\n .I3(E),\n .O(oclk_center_write_resume_r_i_2_n_0));\n LUT5 #(\n .INIT(32'h55554044)) \n oclk_center_write_resume_r_i_3\n (.I0(rstdiv0_sync_r1_reg_rep__25),\n .I1(oclk_center_write_resume),\n .I2(ocd_ktap_left_r_i_3_n_0),\n .I3(oclk_center_write_resume_r_i_4_n_0),\n .I4(sm_r[0]),\n .O(oclk_center_write_resume_r_i_3_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair404\" *) \n LUT4 #(\n .INIT(16'h00F1)) \n oclk_center_write_resume_r_i_4\n (.I0(ocd_ktap_right),\n .I1(oclk_center_write_resume_r_i_5_n_0),\n .I2(\\sm_r_reg[3]_0 ),\n .I3(\\stg2_r_reg[0]_0 ),\n .O(oclk_center_write_resume_r_i_4_n_0));\n LUT6 #(\n .INIT(64'h0880888888880880)) \n oclk_center_write_resume_r_i_5\n (.I0(edge_aligned_r_reg_0),\n .I1(ocd_edge_detect_rdy),\n .I2(ninety_offsets[0]),\n .I3(ninety_offsets_final_r[0]),\n .I4(ninety_offsets[1]),\n .I5(ninety_offsets_final_r[1]),\n .O(oclk_center_write_resume_r_i_5_n_0));\n FDRE #(\n .INIT(1'b0)) \n oclk_center_write_resume_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(p_63_in),\n .Q(oclk_center_write_resume),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n oclkdelay_center_calib_done_r_i_1\n (.I0(oclkdelay_center_calib_done_r_i_2_n_0),\n .I1(resume_wait_r[3]),\n .I2(resume_wait_r[4]),\n .I3(resume_wait_r[5]),\n .I4(oclkdelay_center_calib_done_r_i_3_n_0),\n .I5(oclkdelay_center_calib_done_r_i_4_n_0),\n .O(oclkdelay_center_calib_done_r_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair402\" *) \n LUT5 #(\n .INIT(32'h00000004)) \n oclkdelay_center_calib_done_r_i_2\n (.I0(resume_wait_r[1]),\n .I1(resume_wait_r[0]),\n .I2(resume_wait_r[2]),\n .I3(poc_backup_r),\n .I4(resume_wait_r[10]),\n .O(oclkdelay_center_calib_done_r_i_2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair405\" *) \n LUT4 #(\n .INIT(16'hFFEF)) \n oclkdelay_center_calib_done_r_i_3\n (.I0(sm_r[2]),\n .I1(\\stg2_r_reg[0]_0 ),\n .I2(sm_r[3]),\n .I3(sm_r[0]),\n .O(oclkdelay_center_calib_done_r_i_3_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair398\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n oclkdelay_center_calib_done_r_i_4\n (.I0(resume_wait_r[8]),\n .I1(resume_wait_r[7]),\n .I2(resume_wait_r[9]),\n .I3(resume_wait_r[6]),\n .O(oclkdelay_center_calib_done_r_i_4_n_0));\n FDRE #(\n .INIT(1'b0)) \n oclkdelay_center_calib_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(oclkdelay_center_calib_done_r_i_1_n_0),\n .Q(ocal_last_byte_done_reg),\n .R(rstdiv0_sync_r1_reg_rep__10));\n LUT6 #(\n .INIT(64'hEE44EFFFEE44E000)) \n oclkdelay_center_calib_start_r_i_1\n (.I0(sm_r[0]),\n .I1(poc_backup_r),\n .I2(\\sm_r[3]_i_3_n_0 ),\n .I3(scanning_right_r_reg_0),\n .I4(oclkdelay_center_calib_done_r_i_1_n_0),\n .I5(oclkdelay_center_calib_start_r_reg_0),\n .O(oclkdelay_center_calib_start_r_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n oclkdelay_center_calib_start_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(oclkdelay_center_calib_start_r_i_1_n_0),\n .Q(oclkdelay_center_calib_start_r_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__9));\n CARRY4 p_0_in0_carry\n (.CI(1'b0),\n .CO({p_0_in0_carry_n_0,p_0_in0_carry_n_1,p_0_in0_carry_n_2,p_0_in0_carry_n_3}),\n .CYINIT(1'b0),\n .DI({p_0_in0_carry_i_1_n_0,p_0_in0_carry_i_2_n_0,p_0_in0_carry_i_3_n_0,1'b0}),\n .O(O),\n .S({p_0_in0_carry_i_4_n_0,p_0_in0_carry_i_5_n_0,p_0_in0_carry_i_6_n_0,p_0_in0_carry_i_7_n_0}));\n CARRY4 p_0_in0_carry__0\n (.CI(p_0_in0_carry_n_0),\n .CO({NLW_p_0_in0_carry__0_CO_UNCONNECTED[3:2],p_0_in0_carry__0_n_2,p_0_in0_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,p_0_in0_carry__0_i_1_n_0,p_0_in0_carry__0_i_2_n_0}),\n .O({NLW_p_0_in0_carry__0_O_UNCONNECTED[3],p_0_in0_carry__0_n_5,p_0_in0_carry__0_n_6,p_0_in0_carry__0_n_7}),\n .S({1'b0,1'b1,p_0_in0_carry__0_i_3_n_0,p_0_in0_carry__0_i_4_n_0}));\n LUT2 #(\n .INIT(4'hB)) \n p_0_in0_carry__0_i_1\n (.I0(p_0_in0_carry_i_9_n_0),\n .I1(p_0_in[5]),\n .O(p_0_in0_carry__0_i_1_n_0));\n LUT4 #(\n .INIT(16'hF404)) \n p_0_in0_carry__0_i_2\n (.I0(p_0_in[3]),\n .I1(p_0_in[4]),\n .I2(p_0_in0_carry_i_9_n_0),\n .I3(p_0_in0_carry_i_11_n_7),\n .O(p_0_in0_carry__0_i_2_n_0));\n LUT4 #(\n .INIT(16'h553F)) \n p_0_in0_carry__0_i_3\n (.I0(p_0_in0_carry_i_11_n_6),\n .I1(p_0_in[4]),\n .I2(p_0_in[5]),\n .I3(p_0_in0_carry_i_9_n_0),\n .O(p_0_in0_carry__0_i_3_n_0));\n LUT6 #(\n .INIT(64'hAAC355C3AA0F550F)) \n p_0_in0_carry__0_i_4\n (.I0(p_0_in0_carry_i_11_n_7),\n .I1(p_0_in[3]),\n .I2(p_0_in[5]),\n .I3(p_0_in0_carry_i_9_n_0),\n .I4(p_0_in0_carry_i_11_n_6),\n .I5(p_0_in[4]),\n .O(p_0_in0_carry__0_i_4_n_0));\n LUT4 #(\n .INIT(16'hF404)) \n p_0_in0_carry_i_1\n (.I0(p_0_in[2]),\n .I1(p_0_in[3]),\n .I2(p_0_in0_carry_i_9_n_0),\n .I3(p_0_in0_carry_i_10_n_4),\n .O(p_0_in0_carry_i_1_n_0));\n CARRY4 p_0_in0_carry_i_10\n (.CI(1'b0),\n .CO({p_0_in0_carry_i_10_n_0,p_0_in0_carry_i_10_n_1,p_0_in0_carry_i_10_n_2,p_0_in0_carry_i_10_n_3}),\n .CYINIT(1'b1),\n .DI({1'b1,1'b1,1'b0,1'b0}),\n .O({p_0_in0_carry_i_10_n_4,p_0_in0_carry_i_10_n_5,p_0_in0_carry_i_10_n_6,p_0_in[0]}),\n .S({p_0_in0_carry_i_17_n_0,p_0_in0_carry_i_18_n_0,p_0_in0_carry_i_19_n_0,p_0_in0_carry_i_20_n_0}));\n CARRY4 p_0_in0_carry_i_11\n (.CI(p_0_in0_carry_i_10_n_0),\n .CO({NLW_p_0_in0_carry_i_11_CO_UNCONNECTED[3:1],p_0_in0_carry_i_11_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b1}),\n .O({NLW_p_0_in0_carry_i_11_O_UNCONNECTED[3:2],p_0_in0_carry_i_11_n_6,p_0_in0_carry_i_11_n_7}),\n .S({1'b0,1'b0,p_0_in0_carry_i_21_n_0,p_0_in0_carry_i_22_n_0}));\n CARRY4 p_0_in0_carry_i_12\n (.CI(p_0_in0_carry_i_8_n_0),\n .CO({NLW_p_0_in0_carry_i_12_CO_UNCONNECTED[3:1],p_0_in0_carry_i_12_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,Q[4]}),\n .O({NLW_p_0_in0_carry_i_12_O_UNCONNECTED[3:2],p_0_in[5:4]}),\n .S({1'b0,1'b0,p_0_in0_carry_i_23_n_0,p_0_in0_carry_i_24_n_0}));\n LUT1 #(\n .INIT(2'h2)) \n p_0_in0_carry_i_13\n (.I0(Q[3]),\n .O(p_0_in0_carry_i_13_n_0));\n LUT1 #(\n .INIT(2'h2)) \n p_0_in0_carry_i_14\n (.I0(Q[2]),\n .O(p_0_in0_carry_i_14_n_0));\n LUT1 #(\n .INIT(2'h1)) \n p_0_in0_carry_i_15\n (.I0(Q[1]),\n .O(p_0_in0_carry_i_15_n_0));\n LUT1 #(\n .INIT(2'h1)) \n p_0_in0_carry_i_16\n (.I0(Q[0]),\n .O(p_0_in0_carry_i_16_n_0));\n LUT1 #(\n .INIT(2'h2)) \n p_0_in0_carry_i_17\n (.I0(Q[3]),\n .O(p_0_in0_carry_i_17_n_0));\n LUT1 #(\n .INIT(2'h2)) \n p_0_in0_carry_i_18\n (.I0(Q[2]),\n .O(p_0_in0_carry_i_18_n_0));\n LUT1 #(\n .INIT(2'h1)) \n p_0_in0_carry_i_19\n (.I0(Q[1]),\n .O(p_0_in0_carry_i_19_n_0));\n LUT4 #(\n .INIT(16'hF404)) \n p_0_in0_carry_i_2\n (.I0(p_0_in[1]),\n .I1(p_0_in[2]),\n .I2(p_0_in0_carry_i_9_n_0),\n .I3(p_0_in0_carry_i_10_n_5),\n .O(p_0_in0_carry_i_2_n_0));\n LUT1 #(\n .INIT(2'h1)) \n p_0_in0_carry_i_20\n (.I0(Q[0]),\n .O(p_0_in0_carry_i_20_n_0));\n LUT1 #(\n .INIT(2'h1)) \n p_0_in0_carry_i_21\n (.I0(Q[5]),\n .O(p_0_in0_carry_i_21_n_0));\n LUT1 #(\n .INIT(2'h2)) \n p_0_in0_carry_i_22\n (.I0(Q[4]),\n .O(p_0_in0_carry_i_22_n_0));\n LUT1 #(\n .INIT(2'h1)) \n p_0_in0_carry_i_23\n (.I0(Q[5]),\n .O(p_0_in0_carry_i_23_n_0));\n LUT1 #(\n .INIT(2'h2)) \n p_0_in0_carry_i_24\n (.I0(Q[4]),\n .O(p_0_in0_carry_i_24_n_0));\n LUT3 #(\n .INIT(8'hEF)) \n p_0_in0_carry_i_3\n (.I0(p_0_in[1]),\n .I1(p_0_in0_carry_i_9_n_0),\n .I2(p_0_in[0]),\n .O(p_0_in0_carry_i_3_n_0));\n LUT6 #(\n .INIT(64'hA5CCA533A500A5FF)) \n p_0_in0_carry_i_4\n (.I0(p_0_in0_carry_i_10_n_4),\n .I1(p_0_in[2]),\n .I2(p_0_in0_carry_i_11_n_7),\n .I3(p_0_in0_carry_i_9_n_0),\n .I4(p_0_in[4]),\n .I5(p_0_in[3]),\n .O(p_0_in0_carry_i_4_n_0));\n LUT6 #(\n .INIT(64'hAA55C3C3AA550F0F)) \n p_0_in0_carry_i_5\n (.I0(p_0_in0_carry_i_10_n_5),\n .I1(p_0_in[1]),\n .I2(p_0_in[3]),\n .I3(p_0_in0_carry_i_10_n_4),\n .I4(p_0_in0_carry_i_9_n_0),\n .I5(p_0_in[2]),\n .O(p_0_in0_carry_i_5_n_0));\n LUT5 #(\n .INIT(32'hF033F066)) \n p_0_in0_carry_i_6\n (.I0(p_0_in[0]),\n .I1(p_0_in[2]),\n .I2(p_0_in0_carry_i_10_n_5),\n .I3(p_0_in0_carry_i_9_n_0),\n .I4(p_0_in[1]),\n .O(p_0_in0_carry_i_6_n_0));\n LUT4 #(\n .INIT(16'hF606)) \n p_0_in0_carry_i_7\n (.I0(p_0_in[0]),\n .I1(p_0_in[1]),\n .I2(p_0_in0_carry_i_9_n_0),\n .I3(p_0_in0_carry_i_10_n_6),\n .O(p_0_in0_carry_i_7_n_0));\n CARRY4 p_0_in0_carry_i_8\n (.CI(1'b0),\n .CO({p_0_in0_carry_i_8_n_0,p_0_in0_carry_i_8_n_1,p_0_in0_carry_i_8_n_2,p_0_in0_carry_i_8_n_3}),\n .CYINIT(1'b1),\n .DI(Q[3:0]),\n .O({p_0_in[3:1],NLW_p_0_in0_carry_i_8_O_UNCONNECTED[0]}),\n .S({p_0_in0_carry_i_13_n_0,p_0_in0_carry_i_14_n_0,p_0_in0_carry_i_15_n_0,p_0_in0_carry_i_16_n_0}));\n LUT6 #(\n .INIT(64'h0155555555555555)) \n p_0_in0_carry_i_9\n (.I0(Q[5]),\n .I1(Q[0]),\n .I2(Q[1]),\n .I3(Q[2]),\n .I4(Q[4]),\n .I5(Q[3]),\n .O(p_0_in0_carry_i_9_n_0));\n FDRE #(\n .INIT(1'b0)) \n \\po_counter_read_val_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_counter_read_val_reg[5] [0]),\n .Q(po_counter_read_val_r[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\po_counter_read_val_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_counter_read_val_reg[5] [1]),\n .Q(po_counter_read_val_r[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\po_counter_read_val_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_counter_read_val_reg[5] [2]),\n .Q(po_counter_read_val_r[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\po_counter_read_val_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_counter_read_val_reg[5] [3]),\n .Q(po_counter_read_val_r[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\po_counter_read_val_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_counter_read_val_reg[5] [4]),\n .Q(po_counter_read_val_r[4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\po_counter_read_val_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_counter_read_val_reg[5] [5]),\n .Q(po_counter_read_val_r[5]),\n .R(1'b0));\n LUT3 #(\n .INIT(8'hDC)) \n po_done_r_i_1\n (.I0(\\two_r_reg[1]_0 ),\n .I1(po_done_ns),\n .I2(po_done_r),\n .O(po_done_r_i_1_n_0));\n LUT6 #(\n .INIT(64'hAAAAAAAABAFFAAAA)) \n po_done_r_i_2\n (.I0(rstdiv0_sync_r1_reg_rep__25),\n .I1(two_r[0]),\n .I2(two_r[1]),\n .I3(\\two_r[1]_i_2_n_0 ),\n .I4(po_rdy),\n .I5(po_done_r),\n .O(po_done_ns));\n FDRE #(\n .INIT(1'b0)) \n po_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(po_done_r_i_1_n_0),\n .Q(po_done_r),\n .R(1'b0));\n LUT4 #(\n .INIT(16'hFFFE)) \n po_rdy_r_i_2\n (.I0(po_stg23_incdec_r_reg_0),\n .I1(lim2stg3_inc),\n .I2(lim2stg3_dec),\n .I3(\\two_r_reg[1]_0 ),\n .O(setup_po));\n LUT6 #(\n .INIT(64'hFFFFFFFFEEEFEEEE)) \n po_rdy_r_i_4\n (.I0(po_stg23_incdec_r_i_2_n_0),\n .I1(lim2stg2_dec),\n .I2(up_r),\n .I3(po_rdy_r_i_5_n_0),\n .I4(po_rdy_r_i_6_n_0),\n .I5(po_rdy_r_i_7_n_0),\n .O(po_stg23_incdec_r_reg_0));\n LUT6 #(\n .INIT(64'h0000000000000001)) \n po_rdy_r_i_5\n (.I0(A[2]),\n .I1(A[5]),\n .I2(A[4]),\n .I3(A[0]),\n .I4(A[3]),\n .I5(A[1]),\n .O(po_rdy_r_i_5_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair409\" *) \n LUT4 #(\n .INIT(16'h0002)) \n po_rdy_r_i_6\n (.I0(\\stg2_r[8]_i_3_n_0 ),\n .I1(A[7]),\n .I2(A[8]),\n .I3(A[6]),\n .O(po_rdy_r_i_6_n_0));\n LUT6 #(\n .INIT(64'h4545444544444444)) \n po_rdy_r_i_7\n (.I0(rstdiv0_sync_r1_reg_rep__25),\n .I1(ocd_cntlr2stg2_dec_r),\n .I2(\\sm_r[3]_i_9_n_0 ),\n .I3(stg2_final_r[5]),\n .I4(po_counter_read_val_r[5]),\n .I5(po_stg23_incdec_r_i_4_n_0),\n .O(po_rdy_r_i_7_n_0));\n LUT6 #(\n .INIT(64'h5455555554555455)) \n po_stg23_incdec_r_i_1\n (.I0(rstdiv0_sync_r1_reg_rep__25),\n .I1(po_stg23_incdec_r_i_2_n_0),\n .I2(lim2stg3_inc),\n .I3(\\stg3_r[5]_i_6_n_0 ),\n .I4(setup_po),\n .I5(po_stg23_incdec),\n .O(po_stg23_incdec_r_reg));\n LUT6 #(\n .INIT(64'h7FFFFFFFFFFFFFFF)) \n po_stg23_incdec_r_i_10\n (.I0(A[4]),\n .I1(A[2]),\n .I2(A[5]),\n .I3(A[1]),\n .I4(A[0]),\n .I5(A[3]),\n .O(po_stg23_incdec_r_i_10_n_0));\n LUT5 #(\n .INIT(32'hFFFFFF10)) \n po_stg23_incdec_r_i_2\n (.I0(rstdiv0_sync_r1_reg_rep__25),\n .I1(po_stg23_incdec_r_i_3_n_0),\n .I2(po_stg23_incdec_r_i_4_n_0),\n .I3(po_stg23_incdec_r_i_5_n_0),\n .I4(lim2stg2_inc),\n .O(po_stg23_incdec_r_i_2_n_0));\n LUT6 #(\n .INIT(64'hD5DD0000D5DDD5DD)) \n po_stg23_incdec_r_i_3\n (.I0(po_stg23_incdec_r_i_6_n_0),\n .I1(po_stg23_incdec_r_i_7_n_0),\n .I2(po_stg23_incdec_r_i_8_n_0),\n .I3(po_stg23_incdec_r_i_9_n_0),\n .I4(po_counter_read_val_r[5]),\n .I5(stg2_final_r[5]),\n .O(po_stg23_incdec_r_i_3_n_0));\n LUT4 #(\n .INIT(16'h0002)) \n po_stg23_incdec_r_i_4\n (.I0(po_rdy),\n .I1(E),\n .I2(oclkdelay_center_calib_done_r_i_3_n_0),\n .I3(poc_backup_r),\n .O(po_stg23_incdec_r_i_4_n_0));\n LUT6 #(\n .INIT(64'h0100000000000000)) \n po_stg23_incdec_r_i_5\n (.I0(A[6]),\n .I1(A[8]),\n .I2(A[7]),\n .I3(\\stg2_r[8]_i_3_n_0 ),\n .I4(po_stg23_incdec_r_i_10_n_0),\n .I5(up_r),\n .O(po_stg23_incdec_r_i_5_n_0));\n LUT4 #(\n .INIT(16'hD0DD)) \n po_stg23_incdec_r_i_6\n (.I0(po_counter_read_val_r[5]),\n .I1(stg2_final_r[5]),\n .I2(stg2_final_r[4]),\n .I3(po_counter_read_val_r[4]),\n .O(po_stg23_incdec_r_i_6_n_0));\n LUT4 #(\n .INIT(16'hD0DD)) \n po_stg23_incdec_r_i_7\n (.I0(stg2_final_r[3]),\n .I1(po_counter_read_val_r[3]),\n .I2(po_counter_read_val_r[4]),\n .I3(stg2_final_r[4]),\n .O(po_stg23_incdec_r_i_7_n_0));\n LUT6 #(\n .INIT(64'hB0BBBBBB0000B0BB)) \n po_stg23_incdec_r_i_8\n (.I0(po_counter_read_val_r[2]),\n .I1(stg2_final_r[2]),\n .I2(po_counter_read_val_r[0]),\n .I3(stg2_final_r[0]),\n .I4(stg2_final_r[1]),\n .I5(po_counter_read_val_r[1]),\n .O(po_stg23_incdec_r_i_8_n_0));\n LUT4 #(\n .INIT(16'hD0DD)) \n po_stg23_incdec_r_i_9\n (.I0(po_counter_read_val_r[2]),\n .I1(stg2_final_r[2]),\n .I2(stg2_final_r[3]),\n .I3(po_counter_read_val_r[3]),\n .O(po_stg23_incdec_r_i_9_n_0));\n LUT6 #(\n .INIT(64'hFFFFEAFF0000EA00)) \n poc_backup_r_i_1__0\n (.I0(poc_backup_r_i_2__0_n_0),\n .I1(poc_backup_r_reg_1),\n .I2(sm_r[2]),\n .I3(poc_backup_r_i_3_n_0),\n .I4(poc_backup_r_i_4_n_0),\n .I5(poc_backup_r),\n .O(poc_backup_r_i_1__0_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFF7F)) \n poc_backup_r_i_2\n (.I0(\\run_ends_r_reg[1]_0 ),\n .I1(\\run_ends_r_reg[0] ),\n .I2(\\run_ends_r_reg[1] ),\n .I3(\\sm_r_reg[3]_0 ),\n .I4(\\rise_trail_r_reg[5] ),\n .I5(rstdiv0_sync_r1_reg_rep__20),\n .O(poc_backup_r_reg_0));\n (* SOFT_HLUTNM = \"soft_lutpair403\" *) \n LUT2 #(\n .INIT(4'h8)) \n poc_backup_r_i_2__0\n (.I0(sm_r[3]),\n .I1(E),\n .O(poc_backup_r_i_2__0_n_0));\n LUT3 #(\n .INIT(8'h01)) \n poc_backup_r_i_3\n (.I0(sm_r[0]),\n .I1(\\stg2_r_reg[0]_0 ),\n .I2(rstdiv0_sync_r1_reg_rep__24),\n .O(poc_backup_r_i_3_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFF0F700F700)) \n poc_backup_r_i_4\n (.I0(poc_backup_r),\n .I1(po_rdy),\n .I2(E),\n .I3(sm_r[3]),\n .I4(poc_backup_r_i_5_n_0),\n .I5(sm_r[2]),\n .O(poc_backup_r_i_4_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair413\" *) \n LUT4 #(\n .INIT(16'hFFF7)) \n poc_backup_r_i_5\n (.I0(\\sm_r[3]_i_7_n_0 ),\n .I1(done_r_reg),\n .I2(ocd_ktap_right),\n .I3(\\sm_r_reg[3]_0 ),\n .O(poc_backup_r_i_5_n_0));\n FDRE #(\n .INIT(1'b0)) \n poc_backup_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(poc_backup_r_i_1__0_n_0),\n .Q(poc_backup_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFFFFFFF0000FF46)) \n \\resume_wait_r[0]_i_1 \n (.I0(resume_wait_r[0]),\n .I1(E),\n .I2(rstdiv0_sync_r1_reg_rep__25),\n .I3(\\resume_wait_r[9]_i_5_n_0 ),\n .I4(\\resume_wait_r[10]_i_3_n_0 ),\n .I5(\\resume_wait_r[10]_i_4_n_0 ),\n .O(\\resume_wait_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair400\" *) \n LUT5 #(\n .INIT(32'h0000FF02)) \n \\resume_wait_r[10]_i_1 \n (.I0(resume_wait_r[10]),\n .I1(\\resume_wait_r[10]_i_2_n_0 ),\n .I2(\\resume_wait_r[9]_i_5_n_0 ),\n .I3(\\resume_wait_r[10]_i_3_n_0 ),\n .I4(\\resume_wait_r[10]_i_4_n_0 ),\n .O(\\resume_wait_r[10]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair398\" *) \n LUT5 #(\n .INIT(32'h00000001)) \n \\resume_wait_r[10]_i_2 \n (.I0(\\resume_wait_r[9]_i_6_n_0 ),\n .I1(resume_wait_r[6]),\n .I2(resume_wait_r[9]),\n .I3(resume_wait_r[7]),\n .I4(resume_wait_r[8]),\n .O(\\resume_wait_r[10]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000008000000000)) \n \\resume_wait_r[10]_i_3 \n (.I0(oclk_center_write_resume_r_i_2_n_0),\n .I1(\\stg2_r_reg[0]_0 ),\n .I2(po_done_r),\n .I3(sm_r[3]),\n .I4(oclk_center_write_resume),\n .I5(oclk_center_write_resume_r_i_3_n_0),\n .O(\\resume_wait_r[10]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0000000022222220)) \n \\resume_wait_r[10]_i_4 \n (.I0(ocd_ktap_left_r_i_2_n_0),\n .I1(\\sm_r_reg[3]_0 ),\n .I2(sm_r[0]),\n .I3(\\stg2_r_reg[0]_0 ),\n .I4(ocd_ktap_left_r_i_3_n_0),\n .I5(rstdiv0_sync_r1_reg_rep__20),\n .O(\\resume_wait_r[10]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h00000000EECEDDCE)) \n \\resume_wait_r[1]_i_1 \n (.I0(resume_wait_r[1]),\n .I1(\\resume_wait_r[9]_i_5_n_0 ),\n .I2(rstdiv0_sync_r1_reg_rep__25),\n .I3(E),\n .I4(resume_wait_r[0]),\n .I5(\\resume_wait_r[9]_i_4_n_0 ),\n .O(\\resume_wait_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00000000EECEDDCE)) \n \\resume_wait_r[2]_i_1 \n (.I0(resume_wait_r[2]),\n .I1(\\resume_wait_r[9]_i_5_n_0 ),\n .I2(rstdiv0_sync_r1_reg_rep__25),\n .I3(E),\n .I4(\\resume_wait_r[2]_i_2_n_0 ),\n .I5(\\resume_wait_r[9]_i_4_n_0 ),\n .O(\\resume_wait_r[2]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\resume_wait_r[2]_i_2 \n (.I0(resume_wait_r[0]),\n .I1(resume_wait_r[1]),\n .O(\\resume_wait_r[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00000000DDCEEECE)) \n \\resume_wait_r[3]_i_1 \n (.I0(resume_wait_r[3]),\n .I1(\\resume_wait_r[9]_i_5_n_0 ),\n .I2(rstdiv0_sync_r1_reg_rep__25),\n .I3(E),\n .I4(\\resume_wait_r[7]_i_2_n_0 ),\n .I5(\\resume_wait_r[9]_i_4_n_0 ),\n .O(\\resume_wait_r[3]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h00D0)) \n \\resume_wait_r[4]_i_1 \n (.I0(oclk_center_write_resume),\n .I1(oclk_center_write_resume_r_i_3_n_0),\n .I2(\\resume_wait_r[4]_i_2_n_0 ),\n .I3(\\resume_wait_r[9]_i_4_n_0 ),\n .O(\\resume_wait_r[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFD0DFFFFF2020)) \n \\resume_wait_r[4]_i_2 \n (.I0(\\resume_wait_r[7]_i_2_n_0 ),\n .I1(resume_wait_r[3]),\n .I2(E),\n .I3(rstdiv0_sync_r1_reg_rep__25),\n .I4(\\resume_wait_r[9]_i_8_n_0 ),\n .I5(resume_wait_r[4]),\n .O(\\resume_wait_r[4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAAAAA9)) \n \\resume_wait_r[5]_i_1 \n (.I0(resume_wait_r[5]),\n .I1(resume_wait_r[3]),\n .I2(resume_wait_r[4]),\n .I3(resume_wait_r[2]),\n .I4(resume_wait_r[1]),\n .I5(resume_wait_r[0]),\n .O(resume_wait_ns0[5]));\n (* SOFT_HLUTNM = \"soft_lutpair397\" *) \n LUT5 #(\n .INIT(32'hFEFF0100)) \n \\resume_wait_r[6]_i_1 \n (.I0(resume_wait_r[3]),\n .I1(resume_wait_r[4]),\n .I2(resume_wait_r[5]),\n .I3(\\resume_wait_r[7]_i_2_n_0 ),\n .I4(resume_wait_r[6]),\n .O(resume_wait_ns0[6]));\n LUT6 #(\n .INIT(64'hFFFFFFFB00000004)) \n \\resume_wait_r[7]_i_1 \n (.I0(resume_wait_r[6]),\n .I1(\\resume_wait_r[7]_i_2_n_0 ),\n .I2(resume_wait_r[5]),\n .I3(resume_wait_r[4]),\n .I4(resume_wait_r[3]),\n .I5(resume_wait_r[7]),\n .O(resume_wait_ns0[7]));\n (* SOFT_HLUTNM = \"soft_lutpair402\" *) \n LUT3 #(\n .INIT(8'h01)) \n \\resume_wait_r[7]_i_2 \n (.I0(resume_wait_r[2]),\n .I1(resume_wait_r[1]),\n .I2(resume_wait_r[0]),\n .O(\\resume_wait_r[7]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair412\" *) \n LUT3 #(\n .INIT(8'hE1)) \n \\resume_wait_r[8]_i_1 \n (.I0(resume_wait_r[7]),\n .I1(\\resume_wait_r[9]_i_7_n_0 ),\n .I2(resume_wait_r[8]),\n .O(resume_wait_ns0[8]));\n LUT4 #(\n .INIT(16'hEEFE)) \n \\resume_wait_r[9]_i_1 \n (.I0(\\resume_wait_r[9]_i_4_n_0 ),\n .I1(\\resume_wait_r[9]_i_5_n_0 ),\n .I2(rstdiv0_sync_r1_reg_rep__25),\n .I3(E),\n .O(\\resume_wait_r[9]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\resume_wait_r[9]_i_2 \n (.I0(resume_wait_r[10]),\n .I1(resume_wait_r[8]),\n .I2(resume_wait_r[7]),\n .I3(resume_wait_r[9]),\n .I4(resume_wait_r[6]),\n .I5(\\resume_wait_r[9]_i_6_n_0 ),\n .O(E));\n (* SOFT_HLUTNM = \"soft_lutpair412\" *) \n LUT4 #(\n .INIT(16'hAAA9)) \n \\resume_wait_r[9]_i_3 \n (.I0(resume_wait_r[9]),\n .I1(\\resume_wait_r[9]_i_7_n_0 ),\n .I2(resume_wait_r[7]),\n .I3(resume_wait_r[8]),\n .O(resume_wait_ns0[9]));\n (* SOFT_HLUTNM = \"soft_lutpair400\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\resume_wait_r[9]_i_4 \n (.I0(\\resume_wait_r[10]_i_4_n_0 ),\n .I1(\\resume_wait_r[10]_i_3_n_0 ),\n .O(\\resume_wait_r[9]_i_4_n_0 ));\n LUT3 #(\n .INIT(8'hF2)) \n \\resume_wait_r[9]_i_5 \n (.I0(oclk_center_write_resume),\n .I1(oclk_center_write_resume_r_i_3_n_0),\n .I2(\\resume_wait_r[9]_i_8_n_0 ),\n .O(\\resume_wait_r[9]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\resume_wait_r[9]_i_6 \n (.I0(resume_wait_r[3]),\n .I1(resume_wait_r[4]),\n .I2(resume_wait_r[5]),\n .I3(resume_wait_r[0]),\n .I4(resume_wait_r[1]),\n .I5(resume_wait_r[2]),\n .O(\\resume_wait_r[9]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair397\" *) \n LUT5 #(\n .INIT(32'hFFFFFFFB)) \n \\resume_wait_r[9]_i_7 \n (.I0(resume_wait_r[6]),\n .I1(\\resume_wait_r[7]_i_2_n_0 ),\n .I2(resume_wait_r[5]),\n .I3(resume_wait_r[4]),\n .I4(resume_wait_r[3]),\n .O(\\resume_wait_r[9]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\resume_wait_r[9]_i_8 \n (.I0(poc_backup_r),\n .I1(\\stg3_r[5]_i_6_n_0 ),\n .O(\\resume_wait_r[9]_i_8_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\resume_wait_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\resume_wait_r[0]_i_1_n_0 ),\n .Q(resume_wait_r[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\resume_wait_r_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(\\resume_wait_r[10]_i_1_n_0 ),\n .Q(resume_wait_r[10]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\resume_wait_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\resume_wait_r[1]_i_1_n_0 ),\n .Q(resume_wait_r[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\resume_wait_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\resume_wait_r[2]_i_1_n_0 ),\n .Q(resume_wait_r[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\resume_wait_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\resume_wait_r[3]_i_1_n_0 ),\n .Q(resume_wait_r[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\resume_wait_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\resume_wait_r[4]_i_1_n_0 ),\n .Q(resume_wait_r[4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\resume_wait_r_reg[5] \n (.C(CLK),\n .CE(E),\n .D(resume_wait_ns0[5]),\n .Q(resume_wait_r[5]),\n .R(\\resume_wait_r[9]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\resume_wait_r_reg[6] \n (.C(CLK),\n .CE(E),\n .D(resume_wait_ns0[6]),\n .Q(resume_wait_r[6]),\n .R(\\resume_wait_r[9]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\resume_wait_r_reg[7] \n (.C(CLK),\n .CE(E),\n .D(resume_wait_ns0[7]),\n .Q(resume_wait_r[7]),\n .R(\\resume_wait_r[9]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\resume_wait_r_reg[8] \n (.C(CLK),\n .CE(E),\n .D(resume_wait_ns0[8]),\n .Q(resume_wait_r[8]),\n .R(\\resume_wait_r[9]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\resume_wait_r_reg[9] \n (.C(CLK),\n .CE(E),\n .D(resume_wait_ns0[9]),\n .Q(resume_wait_r[9]),\n .R(\\resume_wait_r[9]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF7F0000004000)) \n scanning_right_r_i_1\n (.I0(scan_right_r_reg),\n .I1(samp_done),\n .I2(rd_active_r2),\n .I3(sm_r[0]),\n .I4(scanning_right_r_i_3_n_0),\n .I5(scanning_right),\n .O(scanning_right_r_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair395\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n scanning_right_r_i_3\n (.I0(sm_r[2]),\n .I1(\\stg2_r_reg[0]_0 ),\n .I2(sm_r[3]),\n .I3(rstdiv0_sync_r1_reg_rep__25),\n .O(scanning_right_r_i_3_n_0));\n FDRE #(\n .INIT(1'b0)) \n scanning_right_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(scanning_right_r_i_1_n_0),\n .Q(scanning_right),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\simp_stg3_final_r_reg[0] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_3 ),\n .D(Q[0]),\n .Q(\\simp_stg3_final_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\simp_stg3_final_r_reg[10] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_2 ),\n .D(Q[4]),\n .Q(\\simp_stg3_final_r_reg_n_0_[10] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\simp_stg3_final_r_reg[11] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_2 ),\n .D(Q[5]),\n .Q(\\simp_stg3_final_r_reg_n_0_[11] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\simp_stg3_final_r_reg[12] \n (.C(CLK),\n .CE(\\byte_r_reg[1]_0 ),\n .D(Q[0]),\n .Q(\\simp_stg3_final_r_reg_n_0_[12] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\simp_stg3_final_r_reg[13] \n (.C(CLK),\n .CE(\\byte_r_reg[1]_0 ),\n .D(Q[1]),\n .Q(\\simp_stg3_final_r_reg_n_0_[13] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\simp_stg3_final_r_reg[14] \n (.C(CLK),\n .CE(\\byte_r_reg[1]_0 ),\n .D(Q[2]),\n .Q(\\simp_stg3_final_r_reg_n_0_[14] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\simp_stg3_final_r_reg[15] \n (.C(CLK),\n .CE(\\byte_r_reg[1]_0 ),\n .D(Q[3]),\n .Q(\\simp_stg3_final_r_reg_n_0_[15] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\simp_stg3_final_r_reg[16] \n (.C(CLK),\n .CE(\\byte_r_reg[1]_0 ),\n .D(Q[4]),\n .Q(\\stg3_init_val_reg[4]_0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\simp_stg3_final_r_reg[17] \n (.C(CLK),\n .CE(\\byte_r_reg[1]_0 ),\n .D(Q[5]),\n .Q(\\simp_stg3_final_r_reg_n_0_[17] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\simp_stg3_final_r_reg[18] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_1 ),\n .D(Q[0]),\n .Q(\\simp_stg3_final_r_reg_n_0_[18] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\simp_stg3_final_r_reg[19] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_1 ),\n .D(Q[1]),\n .Q(\\simp_stg3_final_r_reg_n_0_[19] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\simp_stg3_final_r_reg[1] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_3 ),\n .D(Q[1]),\n .Q(\\simp_stg3_final_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\simp_stg3_final_r_reg[20] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_1 ),\n .D(Q[2]),\n .Q(\\simp_stg3_final_r_reg_n_0_[20] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\simp_stg3_final_r_reg[21] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_1 ),\n .D(Q[3]),\n .Q(\\simp_stg3_final_r_reg_n_0_[21] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\simp_stg3_final_r_reg[22] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_1 ),\n .D(Q[4]),\n .Q(\\simp_stg3_final_r_reg_n_0_[22] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\simp_stg3_final_r_reg[23] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_1 ),\n .D(Q[5]),\n .Q(\\simp_stg3_final_r_reg_n_0_[23] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\simp_stg3_final_r_reg[2] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_3 ),\n .D(Q[2]),\n .Q(\\stg3_init_val_reg[2]_0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\simp_stg3_final_r_reg[3] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_3 ),\n .D(Q[3]),\n .Q(\\simp_stg3_final_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\simp_stg3_final_r_reg[4] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_3 ),\n .D(Q[4]),\n .Q(\\simp_stg3_final_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\simp_stg3_final_r_reg[5] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_3 ),\n .D(Q[5]),\n .Q(\\simp_stg3_final_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\simp_stg3_final_r_reg[6] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_2 ),\n .D(Q[0]),\n .Q(\\simp_stg3_final_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\simp_stg3_final_r_reg[7] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_2 ),\n .D(Q[1]),\n .Q(\\simp_stg3_final_r_reg_n_0_[7] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\simp_stg3_final_r_reg[8] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_2 ),\n .D(Q[2]),\n .Q(\\simp_stg3_final_r_reg_n_0_[8] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\simp_stg3_final_r_reg[9] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_2 ),\n .D(Q[3]),\n .Q(\\simp_stg3_final_r_reg_n_0_[9] ),\n .R(1'b0));\n LUT3 #(\n .INIT(8'hB8)) \n \\sm_r[0]_i_1 \n (.I0(E),\n .I1(sm_r[3]),\n .I2(\\sm_r[0]_i_2__0_n_0 ),\n .O(\\sm_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h000000AAFFF3FFFF)) \n \\sm_r[0]_i_2__0 \n (.I0(scanning_right_r_reg_0),\n .I1(\\sm_r[0]_i_3_n_0 ),\n .I2(\\sm_r_reg[3]_0 ),\n .I3(\\stg2_r_reg[0]_0 ),\n .I4(sm_r[2]),\n .I5(sm_r[0]),\n .O(\\sm_r[0]_i_2__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair404\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\sm_r[0]_i_3 \n (.I0(ocd_ktap_right),\n .I1(oclk_center_write_resume_r_i_5_n_0),\n .O(\\sm_r[0]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair408\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\sm_r[1]_i_1 \n (.I0(E),\n .I1(sm_r[3]),\n .I2(\\sm_r[1]_i_2_n_0 ),\n .O(\\sm_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000EEEF55550000)) \n \\sm_r[1]_i_2 \n (.I0(\\stg2_r_reg[0]_0 ),\n .I1(\\sm_r_reg[3]_0 ),\n .I2(ocd_ktap_right),\n .I3(edge_aligned_r_reg_0),\n .I4(sm_r[0]),\n .I5(sm_r[2]),\n .O(\\sm_r[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hBBBBB88888888888)) \n \\sm_r[2]_i_1 \n (.I0(E),\n .I1(sm_r[3]),\n .I2(\\stg2_r_reg[0]_0 ),\n .I3(sm_r[0]),\n .I4(sm_r[2]),\n .I5(\\sm_r[2]_i_2_n_0 ),\n .O(\\sm_r[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF0DFFFF)) \n \\sm_r[2]_i_2 \n (.I0(\\sm_r[3]_i_7_n_0 ),\n .I1(ocd_ktap_right),\n .I2(\\sm_r_reg[3]_0 ),\n .I3(\\stg2_r_reg[0]_0 ),\n .I4(sm_r[2]),\n .I5(sm_r[0]),\n .O(\\sm_r[2]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'hFEFF)) \n \\sm_r[3]_i_1 \n (.I0(\\sm_r[3]_i_3_n_0 ),\n .I1(\\sm_r[3]_i_4_n_0 ),\n .I2(cmplx_samples_done_r_i_2_n_0),\n .I3(\\sm_r_reg[0]_0 ),\n .O(sm_ns));\n LUT6 #(\n .INIT(64'h00B0BBBB000000B0)) \n \\sm_r[3]_i_10 \n (.I0(po_counter_read_val_r[2]),\n .I1(stg2_final_r[2]),\n .I2(po_counter_read_val_r[0]),\n .I3(stg2_final_r[0]),\n .I4(stg2_final_r[1]),\n .I5(po_counter_read_val_r[1]),\n .O(\\sm_r[3]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'h888B888888888888)) \n \\sm_r[3]_i_2 \n (.I0(E),\n .I1(sm_r[3]),\n .I2(ocd_ktap_right),\n .I3(\\sm_r_reg[3]_0 ),\n .I4(\\sm_r[3]_i_6_n_0 ),\n .I5(\\sm_r[3]_i_7_n_0 ),\n .O(\\sm_r[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000010000000)) \n \\sm_r[3]_i_3 \n (.I0(sm_r[3]),\n .I1(sm_r[2]),\n .I2(sm_r[0]),\n .I3(samp_done),\n .I4(rd_active_r2),\n .I5(\\stg2_r_reg[0]_0 ),\n .O(\\sm_r[3]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h00000000F3F203F2)) \n \\sm_r[3]_i_4 \n (.I0(done_r_reg),\n .I1(E),\n .I2(sm_r[0]),\n .I3(\\stg2_r_reg[0]_0 ),\n .I4(po_done_r),\n .I5(\\sm_r[3]_i_8_n_0 ),\n .O(\\sm_r[3]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFF7FFFFFFFF)) \n \\sm_r[3]_i_5 \n (.I0(\\sm_r[3]_i_9_n_0 ),\n .I1(po_stg23_incdec_r_i_3_n_0),\n .I2(poc_backup_r),\n .I3(oclkdelay_center_calib_done_r_i_3_n_0),\n .I4(E),\n .I5(po_rdy),\n .O(\\sm_r_reg[0]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair401\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\sm_r[3]_i_6 \n (.I0(sm_r[0]),\n .I1(sm_r[2]),\n .I2(\\stg2_r_reg[0]_0 ),\n .O(\\sm_r[3]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hA22A22222222A22A)) \n \\sm_r[3]_i_7 \n (.I0(edge_aligned_r_reg_0),\n .I1(ocd_edge_detect_rdy),\n .I2(ninety_offsets[0]),\n .I3(ninety_offsets_final_r[0]),\n .I4(ninety_offsets[1]),\n .I5(ninety_offsets_final_r[1]),\n .O(\\sm_r[3]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair405\" *) \n LUT2 #(\n .INIT(4'hB)) \n \\sm_r[3]_i_8 \n (.I0(sm_r[3]),\n .I1(sm_r[2]),\n .O(\\sm_r[3]_i_8_n_0 ));\n LUT4 #(\n .INIT(16'h08AA)) \n \\sm_r[3]_i_9 \n (.I0(po_stg23_incdec_r_i_6_n_0),\n .I1(po_stg23_incdec_r_i_9_n_0),\n .I2(\\sm_r[3]_i_10_n_0 ),\n .I3(po_stg23_incdec_r_i_7_n_0),\n .O(\\sm_r[3]_i_9_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\sm_r_reg[0] \n (.C(CLK),\n .CE(sm_ns),\n .D(\\sm_r[0]_i_1_n_0 ),\n .Q(sm_r[0]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE #(\n .INIT(1'b0)) \n \\sm_r_reg[1] \n (.C(CLK),\n .CE(sm_ns),\n .D(\\sm_r[1]_i_1_n_0 ),\n .Q(\\stg2_r_reg[0]_0 ),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE #(\n .INIT(1'b0)) \n \\sm_r_reg[2] \n (.C(CLK),\n .CE(sm_ns),\n .D(\\sm_r[2]_i_1_n_0 ),\n .Q(sm_r[2]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE #(\n .INIT(1'b0)) \n \\sm_r_reg[3] \n (.C(CLK),\n .CE(sm_ns),\n .D(\\sm_r[3]_i_2_n_0 ),\n .Q(sm_r[3]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n (* SOFT_HLUTNM = \"soft_lutpair407\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n \\stg2_final_r[0]_i_1 \n (.I0(\\stg2_target_r_reg_n_0_[0] ),\n .I1(\\stg2_target_r_reg_n_0_[6] ),\n .I2(p_1_in),\n .I3(\\stg2_target_r_reg_n_0_[7] ),\n .O(\\stg2_final_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair410\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n \\stg2_final_r[1]_i_1 \n (.I0(\\stg2_target_r_reg_n_0_[1] ),\n .I1(\\stg2_target_r_reg_n_0_[6] ),\n .I2(p_1_in),\n .I3(\\stg2_target_r_reg_n_0_[7] ),\n .O(\\stg2_final_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair411\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n \\stg2_final_r[2]_i_1 \n (.I0(\\stg2_target_r_reg_n_0_[2] ),\n .I1(\\stg2_target_r_reg_n_0_[6] ),\n .I2(p_1_in),\n .I3(\\stg2_target_r_reg_n_0_[7] ),\n .O(\\stg2_final_r[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair410\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n \\stg2_final_r[3]_i_1 \n (.I0(\\stg2_target_r_reg_n_0_[3] ),\n .I1(\\stg2_target_r_reg_n_0_[6] ),\n .I2(p_1_in),\n .I3(\\stg2_target_r_reg_n_0_[7] ),\n .O(\\stg2_final_r[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair411\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n \\stg2_final_r[4]_i_1 \n (.I0(\\stg2_target_r_reg_n_0_[4] ),\n .I1(\\stg2_target_r_reg_n_0_[6] ),\n .I2(p_1_in),\n .I3(\\stg2_target_r_reg_n_0_[7] ),\n .O(\\stg2_final_r[4]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair407\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n \\stg2_final_r[5]_i_1 \n (.I0(\\stg2_target_r_reg_n_0_[5] ),\n .I1(\\stg2_target_r_reg_n_0_[6] ),\n .I2(p_1_in),\n .I3(\\stg2_target_r_reg_n_0_[7] ),\n .O(\\stg2_final_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\stg2_final_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\stg2_final_r[0]_i_1_n_0 ),\n .Q(stg2_final_r[0]),\n .R(p_1_in));\n FDRE #(\n .INIT(1'b0)) \n \\stg2_final_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\stg2_final_r[1]_i_1_n_0 ),\n .Q(stg2_final_r[1]),\n .R(p_1_in));\n FDRE #(\n .INIT(1'b0)) \n \\stg2_final_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\stg2_final_r[2]_i_1_n_0 ),\n .Q(stg2_final_r[2]),\n .R(p_1_in));\n FDRE #(\n .INIT(1'b0)) \n \\stg2_final_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\stg2_final_r[3]_i_1_n_0 ),\n .Q(stg2_final_r[3]),\n .R(p_1_in));\n FDRE #(\n .INIT(1'b0)) \n \\stg2_final_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\stg2_final_r[4]_i_1_n_0 ),\n .Q(stg2_final_r[4]),\n .R(p_1_in));\n FDRE #(\n .INIT(1'b0)) \n \\stg2_final_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\stg2_final_r[5]_i_1_n_0 ),\n .Q(stg2_final_r[5]),\n .R(p_1_in));\n (* METHODOLOGY_DRC_VIOS = \"{SYNTH-8 {cell *THIS*}}\" *) \n CARRY4 stg2_ns0_carry\n (.CI(1'b0),\n .CO({stg2_ns0_carry_n_0,stg2_ns0_carry_n_1,stg2_ns0_carry_n_2,stg2_ns0_carry_n_3}),\n .CYINIT(A[0]),\n .DI({A[3:1],up_r}),\n .O(out[4:1]),\n .S({stg2_ns0_carry_i_1_n_0,stg2_ns0_carry_i_2_n_0,stg2_ns0_carry_i_3_n_0,stg2_ns0_carry_i_4_n_0}));\n (* METHODOLOGY_DRC_VIOS = \"{SYNTH-8 {cell *THIS*}}\" *) \n CARRY4 stg2_ns0_carry__0\n (.CI(stg2_ns0_carry_n_0),\n .CO({NLW_stg2_ns0_carry__0_CO_UNCONNECTED[3],stg2_ns0_carry__0_n_1,stg2_ns0_carry__0_n_2,stg2_ns0_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,A[6:4]}),\n .O(out[8:5]),\n .S({stg2_ns0_carry__0_i_1_n_0,stg2_ns0_carry__0_i_2_n_0,stg2_ns0_carry__0_i_3_n_0,stg2_ns0_carry__0_i_4_n_0}));\n LUT2 #(\n .INIT(4'h9)) \n stg2_ns0_carry__0_i_1\n (.I0(A[7]),\n .I1(A[8]),\n .O(stg2_ns0_carry__0_i_1_n_0));\n LUT2 #(\n .INIT(4'h9)) \n stg2_ns0_carry__0_i_2\n (.I0(A[6]),\n .I1(A[7]),\n .O(stg2_ns0_carry__0_i_2_n_0));\n LUT2 #(\n .INIT(4'h9)) \n stg2_ns0_carry__0_i_3\n (.I0(A[5]),\n .I1(A[6]),\n .O(stg2_ns0_carry__0_i_3_n_0));\n LUT2 #(\n .INIT(4'h9)) \n stg2_ns0_carry__0_i_4\n (.I0(A[4]),\n .I1(A[5]),\n .O(stg2_ns0_carry__0_i_4_n_0));\n LUT2 #(\n .INIT(4'h9)) \n stg2_ns0_carry_i_1\n (.I0(A[3]),\n .I1(A[4]),\n .O(stg2_ns0_carry_i_1_n_0));\n LUT2 #(\n .INIT(4'h9)) \n stg2_ns0_carry_i_2\n (.I0(A[2]),\n .I1(A[3]),\n .O(stg2_ns0_carry_i_2_n_0));\n LUT2 #(\n .INIT(4'h9)) \n stg2_ns0_carry_i_3\n (.I0(A[1]),\n .I1(A[2]),\n .O(stg2_ns0_carry_i_3_n_0));\n LUT2 #(\n .INIT(4'h9)) \n stg2_ns0_carry_i_4\n (.I0(A[1]),\n .I1(up_r),\n .O(stg2_ns0_carry_i_4_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair416\" *) \n LUT3 #(\n .INIT(8'h35)) \n \\stg2_r[0]_i_1 \n (.I0(\\wl_po_fine_cnt_reg[18] ),\n .I1(A[0]),\n .I2(\\stg2_r[8]_i_3_n_0 ),\n .O(stg2_ns[0]));\n (* SOFT_HLUTNM = \"soft_lutpair417\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\stg2_r[1]_i_1 \n (.I0(out[1]),\n .I1(\\stg2_r[8]_i_3_n_0 ),\n .I2(\\wl_po_fine_cnt_reg[14] [0]),\n .O(stg2_ns[1]));\n (* SOFT_HLUTNM = \"soft_lutpair414\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\stg2_r[2]_i_1 \n (.I0(out[2]),\n .I1(\\stg2_r[8]_i_3_n_0 ),\n .I2(\\wl_po_fine_cnt_reg[14] [1]),\n .O(stg2_ns[2]));\n (* SOFT_HLUTNM = \"soft_lutpair416\" *) \n LUT3 #(\n .INIT(8'h8B)) \n \\stg2_r[3]_i_1 \n (.I0(out[3]),\n .I1(\\stg2_r[8]_i_3_n_0 ),\n .I2(\\wl_po_fine_cnt_reg[3] ),\n .O(stg2_ns[3]));\n (* SOFT_HLUTNM = \"soft_lutpair414\" *) \n LUT3 #(\n .INIT(8'h8B)) \n \\stg2_r[4]_i_1 \n (.I0(out[4]),\n .I1(\\stg2_r[8]_i_3_n_0 ),\n .I2(\\byte_r_reg[0] ),\n .O(stg2_ns[4]));\n (* SOFT_HLUTNM = \"soft_lutpair417\" *) \n LUT3 #(\n .INIT(8'h8B)) \n \\stg2_r[5]_i_1 \n (.I0(out[5]),\n .I1(\\stg2_r[8]_i_3_n_0 ),\n .I2(\\wl_po_fine_cnt_reg[17] ),\n .O(stg2_ns[5]));\n (* SOFT_HLUTNM = \"soft_lutpair409\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\stg2_r[6]_i_1 \n (.I0(out[6]),\n .I1(\\stg2_r[8]_i_3_n_0 ),\n .O(stg2_ns[6]));\n (* SOFT_HLUTNM = \"soft_lutpair419\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\stg2_r[7]_i_1 \n (.I0(out[7]),\n .I1(\\stg2_r[8]_i_3_n_0 ),\n .O(stg2_ns[7]));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAAAAAB)) \n \\stg2_r[8]_i_1 \n (.I0(\\stg2_r[8]_i_3_n_0 ),\n .I1(sm_r[0]),\n .I2(\\stg2_r_reg[0]_0 ),\n .I3(rstdiv0_sync_r1_reg_rep__25),\n .I4(sm_r[3]),\n .I5(sm_r[2]),\n .O(\\stg2_r[8]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair419\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\stg2_r[8]_i_2 \n (.I0(out[8]),\n .I1(\\stg2_r[8]_i_3_n_0 ),\n .O(stg2_ns[8]));\n LUT5 #(\n .INIT(32'h40400040)) \n \\stg2_r[8]_i_3 \n (.I0(po_done_r),\n .I1(po_rdy),\n .I2(\\two_r[1]_i_2_n_0 ),\n .I3(two_r[1]),\n .I4(two_r[0]),\n .O(\\stg2_r[8]_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\stg2_r_reg[0] \n (.C(CLK),\n .CE(\\stg2_r[8]_i_1_n_0 ),\n .D(stg2_ns[0]),\n .Q(A[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg2_r_reg[1] \n (.C(CLK),\n .CE(\\stg2_r[8]_i_1_n_0 ),\n .D(stg2_ns[1]),\n .Q(A[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg2_r_reg[2] \n (.C(CLK),\n .CE(\\stg2_r[8]_i_1_n_0 ),\n .D(stg2_ns[2]),\n .Q(A[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg2_r_reg[3] \n (.C(CLK),\n .CE(\\stg2_r[8]_i_1_n_0 ),\n .D(stg2_ns[3]),\n .Q(A[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg2_r_reg[4] \n (.C(CLK),\n .CE(\\stg2_r[8]_i_1_n_0 ),\n .D(stg2_ns[4]),\n .Q(A[4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg2_r_reg[5] \n (.C(CLK),\n .CE(\\stg2_r[8]_i_1_n_0 ),\n .D(stg2_ns[5]),\n .Q(A[5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg2_r_reg[6] \n (.C(CLK),\n .CE(\\stg2_r[8]_i_1_n_0 ),\n .D(stg2_ns[6]),\n .Q(A[6]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg2_r_reg[7] \n (.C(CLK),\n .CE(\\stg2_r[8]_i_1_n_0 ),\n .D(stg2_ns[7]),\n .Q(A[7]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg2_r_reg[8] \n (.C(CLK),\n .CE(\\stg2_r[8]_i_1_n_0 ),\n .D(stg2_ns[8]),\n .Q(A[8]),\n .R(1'b0));\n LUT4 #(\n .INIT(16'h56A6)) \n \\stg2_target_r[1]_i_1 \n (.I0(\\wl_po_fine_cnt_reg[14] [0]),\n .I1(p_0_in[0]),\n .I2(p_0_in0_carry_i_9_n_0),\n .I3(\\stg3_r_reg[0]_0 ),\n .O(stg2_target_ns));\n LUT4 #(\n .INIT(16'h56A6)) \n \\stg2_target_r[4]_i_7 \n (.I0(\\wl_po_fine_cnt_reg[14] [0]),\n .I1(p_0_in[0]),\n .I2(p_0_in0_carry_i_9_n_0),\n .I3(\\stg3_r_reg[0]_0 ),\n .O(S));\n LUT1 #(\n .INIT(2'h2)) \n \\stg2_target_r[8]_i_3 \n (.I0(p_0_in0_carry__0_n_5),\n .O(\\stg2_target_r_reg[8]_0 [2]));\n LUT1 #(\n .INIT(2'h2)) \n \\stg2_target_r[8]_i_4 \n (.I0(p_0_in0_carry__0_n_6),\n .O(\\stg2_target_r_reg[8]_0 [1]));\n LUT1 #(\n .INIT(2'h2)) \n \\stg2_target_r[8]_i_5 \n (.I0(p_0_in0_carry__0_n_7),\n .O(\\stg2_target_r_reg[8]_0 [0]));\n FDRE #(\n .INIT(1'b0)) \n \\stg2_target_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_po_fine_cnt_reg[23] [0]),\n .Q(\\stg2_target_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg2_target_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(stg2_target_ns),\n .Q(\\stg2_target_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg2_target_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_po_fine_cnt_reg[23] [1]),\n .Q(\\stg2_target_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg2_target_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_po_fine_cnt_reg[23] [2]),\n .Q(\\stg2_target_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg2_target_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_po_fine_cnt_reg[23] [3]),\n .Q(\\stg2_target_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg2_target_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_po_fine_cnt_reg[23] [4]),\n .Q(\\stg2_target_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg2_target_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_po_fine_cnt_reg[23] [5]),\n .Q(\\stg2_target_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg2_target_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_po_fine_cnt_reg[23] [6]),\n .Q(\\stg2_target_r_reg_n_0_[7] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg2_target_r_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_po_fine_cnt_reg[23] [7]),\n .Q(p_1_in),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00550F33FF550F33)) \n \\stg3_init_val[0]_i_2 \n (.I0(\\simp_stg3_final_r_reg_n_0_[12] ),\n .I1(\\simp_stg3_final_r_reg_n_0_[0] ),\n .I2(\\simp_stg3_final_r_reg_n_0_[6] ),\n .I3(\\byte_r_reg[0]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\simp_stg3_final_r_reg_n_0_[18] ),\n .O(\\stg3_init_val_reg[0] ));\n LUT6 #(\n .INIT(64'h5500330F55FF330F)) \n \\stg3_init_val[1]_i_2 \n (.I0(\\simp_stg3_final_r_reg_n_0_[19] ),\n .I1(\\simp_stg3_final_r_reg_n_0_[7] ),\n .I2(\\simp_stg3_final_r_reg_n_0_[1] ),\n .I3(\\byte_r_reg[0]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\simp_stg3_final_r_reg_n_0_[13] ),\n .O(\\stg3_init_val_reg[1] ));\n LUT5 #(\n .INIT(32'hFAC00AC0)) \n \\stg3_init_val[2]_i_2 \n (.I0(\\simp_stg3_final_r_reg_n_0_[8] ),\n .I1(\\simp_stg3_final_r_reg_n_0_[14] ),\n .I2(\\byte_r_reg[1] ),\n .I3(\\byte_r_reg[0]_0 ),\n .I4(\\simp_stg3_final_r_reg_n_0_[20] ),\n .O(\\stg3_init_val_reg[2] ));\n LUT6 #(\n .INIT(64'h7747FFFF7444FFFF)) \n \\stg3_init_val[3]_i_1 \n (.I0(\\stg3_init_val[3]_i_2_n_0 ),\n .I1(\\byte_r_reg[0]_0 ),\n .I2(\\byte_r_reg[1] ),\n .I3(\\simp_stg3_final_r_reg_n_0_[15] ),\n .I4(oclkdelay_calib_done_r_reg),\n .I5(\\simp_stg3_final_r_reg_n_0_[3] ),\n .O(\\stg3_init_val_reg[3] ));\n LUT5 #(\n .INIT(32'h0407C4C7)) \n \\stg3_init_val[3]_i_2 \n (.I0(\\simp_stg3_final_r_reg_n_0_[9] ),\n .I1(\\byte_r_reg[0]_0 ),\n .I2(\\byte_r_reg[1] ),\n .I3(\\simp_stg3_final_r_reg_n_0_[5] ),\n .I4(\\simp_stg3_final_r_reg_n_0_[21] ),\n .O(\\stg3_init_val[3]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hF0AC00AC)) \n \\stg3_init_val[4]_i_2 \n (.I0(\\simp_stg3_final_r_reg_n_0_[10] ),\n .I1(\\simp_stg3_final_r_reg_n_0_[4] ),\n .I2(\\byte_r_reg[0]_0 ),\n .I3(\\byte_r_reg[1] ),\n .I4(\\simp_stg3_final_r_reg_n_0_[22] ),\n .O(\\stg3_init_val_reg[4] ));\n LUT6 #(\n .INIT(64'h0FDD00CC0FDDFFCC)) \n \\stg3_init_val[5]_i_2 \n (.I0(\\simp_stg3_final_r_reg_n_0_[17] ),\n .I1(\\stg3_init_val[3]_i_2_n_0 ),\n .I2(\\simp_stg3_final_r_reg_n_0_[23] ),\n .I3(\\byte_r_reg[0]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\simp_stg3_final_r_reg_n_0_[11] ),\n .O(\\stg3_init_val_reg[5] ));\n LUT2 #(\n .INIT(4'h2)) \n \\stg3_r[0]_i_1 \n (.I0(\\two_r_reg[1]_0 ),\n .I1(Q[0]),\n .O(stg3_ns[0]));\n (* SOFT_HLUTNM = \"soft_lutpair399\" *) \n LUT4 #(\n .INIT(16'hD714)) \n \\stg3_r[1]_i_1 \n (.I0(\\stg3_r[5]_i_6_n_0 ),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(ocd2stg3_dec),\n .O(stg3_ns[1]));\n (* SOFT_HLUTNM = \"soft_lutpair399\" *) \n LUT5 #(\n .INIT(32'h8CC2BEEE)) \n \\stg3_r[2]_i_1 \n (.I0(\\stg3_r[5]_i_6_n_0 ),\n .I1(Q[2]),\n .I2(Q[0]),\n .I3(Q[1]),\n .I4(ocd2stg3_dec),\n .O(stg3_ns[2]));\n LUT6 #(\n .INIT(64'h8CCCCCC2BEEEEEEE)) \n \\stg3_r[3]_i_1 \n (.I0(\\stg3_r[5]_i_6_n_0 ),\n .I1(Q[3]),\n .I2(Q[2]),\n .I3(Q[1]),\n .I4(Q[0]),\n .I5(ocd2stg3_dec),\n .O(stg3_ns[3]));\n LUT6 #(\n .INIT(64'hFF6A0000FF6AFF6A)) \n \\stg3_r[4]_i_1 \n (.I0(Q[4]),\n .I1(Q[3]),\n .I2(\\stg3_r[5]_i_5_n_0 ),\n .I3(\\stg3_r[5]_i_6_n_0 ),\n .I4(D[4]),\n .I5(ocd2stg3_dec),\n .O(stg3_ns[4]));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAAAAAB)) \n \\stg3_r[5]_i_1 \n (.I0(\\two_r_reg[1]_0 ),\n .I1(sm_r[0]),\n .I2(\\stg2_r_reg[0]_0 ),\n .I3(rstdiv0_sync_r1_reg_rep__25),\n .I4(sm_r[3]),\n .I5(sm_r[2]),\n .O(\\stg3_r[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hEEEE0EEEEEEEEEEE)) \n \\stg3_r[5]_i_10 \n (.I0(scan_right_r_reg),\n .I1(samp_done_r_reg),\n .I2(po_done_r),\n .I3(\\stg2_r_reg[0]_0 ),\n .I4(E),\n .I5(inc_po_r),\n .O(\\stg3_r[5]_i_10_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFFFEF)) \n \\stg3_r[5]_i_11 \n (.I0(rstdiv0_sync_r1_reg_rep__25),\n .I1(sm_r[0]),\n .I2(sm_r[3]),\n .I3(\\stg2_r_reg[0]_0 ),\n .I4(sm_r[2]),\n .O(\\stg3_r[5]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'h0080AAAA00800080)) \n \\stg3_r[5]_i_12 \n (.I0(\\stg3_r[5]_i_9_n_0 ),\n .I1(cmplx_samples_done_r_i_3_n_0),\n .I2(dec_po_r),\n .I3(inc_po_r),\n .I4(samp_done_r_reg),\n .I5(scan_right_r_reg),\n .O(\\stg3_r[5]_i_12_n_0 ));\n LUT6 #(\n .INIT(64'h006AFFFF006A006A)) \n \\stg3_r[5]_i_2 \n (.I0(Q[5]),\n .I1(\\stg3_r[5]_i_4_n_0 ),\n .I2(\\stg3_r[5]_i_5_n_0 ),\n .I3(\\stg3_r[5]_i_6_n_0 ),\n .I4(\\stg3_r[5]_i_7_n_0 ),\n .I5(ocd2stg3_dec),\n .O(stg3_ns[5]));\n LUT2 #(\n .INIT(4'hB)) \n \\stg3_r[5]_i_3 \n (.I0(ocd2stg3_dec),\n .I1(\\stg3_r[5]_i_6_n_0 ),\n .O(\\two_r_reg[1]_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\stg3_r[5]_i_4 \n (.I0(Q[4]),\n .I1(Q[3]),\n .O(\\stg3_r[5]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair415\" *) \n LUT3 #(\n .INIT(8'h80)) \n \\stg3_r[5]_i_5 \n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(Q[2]),\n .O(\\stg3_r[5]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hDDDDDDDDD0DDDDDD)) \n \\stg3_r[5]_i_6 \n (.I0(\\stg3_r[5]_i_9_n_0 ),\n .I1(\\stg3_r[5]_i_10_n_0 ),\n .I2(\\stg3_r[5]_i_11_n_0 ),\n .I3(poc_backup_r),\n .I4(po_rdy),\n .I5(E),\n .O(\\stg3_r[5]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h5555555555555556)) \n \\stg3_r[5]_i_7 \n (.I0(Q[5]),\n .I1(Q[4]),\n .I2(Q[2]),\n .I3(Q[1]),\n .I4(Q[0]),\n .I5(Q[3]),\n .O(\\stg3_r[5]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAAAEAA)) \n \\stg3_r[5]_i_8 \n (.I0(\\stg3_r[5]_i_12_n_0 ),\n .I1(sm_r[2]),\n .I2(sm_r[3]),\n .I3(\\stg2_r_reg[0]_0 ),\n .I4(sm_r[0]),\n .I5(rstdiv0_sync_r1_reg_rep__25_0),\n .O(ocd2stg3_dec));\n LUT4 #(\n .INIT(16'h0100)) \n \\stg3_r[5]_i_9 \n (.I0(rstdiv0_sync_r1_reg_rep__24),\n .I1(sm_r[3]),\n .I2(sm_r[2]),\n .I3(sm_r[0]),\n .O(\\stg3_r[5]_i_9_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_r_reg[0] \n (.C(CLK),\n .CE(\\stg3_r[5]_i_1_n_0 ),\n .D(stg3_ns[0]),\n .Q(Q[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_r_reg[1] \n (.C(CLK),\n .CE(\\stg3_r[5]_i_1_n_0 ),\n .D(stg3_ns[1]),\n .Q(Q[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_r_reg[2] \n (.C(CLK),\n .CE(\\stg3_r[5]_i_1_n_0 ),\n .D(stg3_ns[2]),\n .Q(Q[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_r_reg[3] \n (.C(CLK),\n .CE(\\stg3_r[5]_i_1_n_0 ),\n .D(stg3_ns[3]),\n .Q(Q[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_r_reg[4] \n (.C(CLK),\n .CE(\\stg3_r[5]_i_1_n_0 ),\n .D(stg3_ns[4]),\n .Q(Q[4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\stg3_r_reg[5] \n (.C(CLK),\n .CE(\\stg3_r[5]_i_1_n_0 ),\n .D(stg3_ns[5]),\n .Q(Q[5]),\n .R(1'b0));\n LUT3 #(\n .INIT(8'h1C)) \n \\two_r[0]_i_1 \n (.I0(\\two_r_reg[1]_0 ),\n .I1(\\stg2_r[8]_i_3_n_0 ),\n .I2(two_r[0]),\n .O(\\two_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h505050501C505050)) \n \\two_r[1]_i_1 \n (.I0(\\two_r_reg[1]_0 ),\n .I1(two_r[0]),\n .I2(two_r[1]),\n .I3(\\two_r[1]_i_2_n_0 ),\n .I4(po_rdy),\n .I5(po_done_r),\n .O(\\two_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair395\" *) \n LUT5 #(\n .INIT(32'hFCFFFFEF)) \n \\two_r[1]_i_2 \n (.I0(sm_r[2]),\n .I1(rstdiv0_sync_r1_reg_rep__25),\n .I2(sm_r[3]),\n .I3(\\stg2_r_reg[0]_0 ),\n .I4(sm_r[0]),\n .O(\\two_r[1]_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\two_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\two_r[0]_i_1_n_0 ),\n .Q(two_r[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\two_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\two_r[1]_i_1_n_0 ),\n .Q(two_r[1]),\n .R(1'b0));\n LUT3 #(\n .INIT(8'hF8)) \n up_r_i_1\n (.I0(\\stg3_r[5]_i_6_n_0 ),\n .I1(up_r),\n .I2(ocd2stg3_dec),\n .O(up_r_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n up_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(up_r_i_1_n_0),\n .Q(up_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair420\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\zero2fuzz_r[0]_i_1 \n (.I0(Q[0]),\n .O(D[0]));\n (* SOFT_HLUTNM = \"soft_lutpair420\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\zero2fuzz_r[1]_i_1 \n (.I0(Q[0]),\n .I1(Q[1]),\n .O(D[1]));\n (* SOFT_HLUTNM = \"soft_lutpair415\" *) \n LUT3 #(\n .INIT(8'hA9)) \n \\zero2fuzz_r[2]_i_1 \n (.I0(Q[2]),\n .I1(Q[0]),\n .I2(Q[1]),\n .O(D[2]));\n (* SOFT_HLUTNM = \"soft_lutpair396\" *) \n LUT4 #(\n .INIT(16'hAAA9)) \n \\zero2fuzz_r[3]_i_1 \n (.I0(Q[3]),\n .I1(Q[2]),\n .I2(Q[1]),\n .I3(Q[0]),\n .O(D[3]));\n (* SOFT_HLUTNM = \"soft_lutpair396\" *) \n LUT5 #(\n .INIT(32'hAAAAAAA9)) \n \\zero2fuzz_r[4]_i_1 \n (.I0(Q[4]),\n .I1(Q[3]),\n .I2(Q[0]),\n .I3(Q[1]),\n .I4(Q[2]),\n .O(D[4]));\n LUT6 #(\n .INIT(64'hFFFFFFFE00000001)) \n \\zero2fuzz_r[5]_i_2 \n (.I0(Q[3]),\n .I1(Q[0]),\n .I2(Q[1]),\n .I3(Q[2]),\n .I4(Q[4]),\n .I5(Q[5]),\n .O(D[5]));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_phy_ocd_samp\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_phy_ocd_samp\n (oclk_calib_resume_level_reg,\n \\samps_r_reg[9]_0 ,\n samp_done,\n oclk_calib_resume_r_reg_0,\n prev_samp_valid_r_reg,\n D,\n \\samps_r_reg[0]_0 ,\n agg_samp_r,\n \\stg3_r_reg[1] ,\n \\rd_victim_sel_r_reg[2]_0 ,\n \\rd_victim_sel_r_reg[1]_0 ,\n \\rd_victim_sel_r_reg[1]_1 ,\n \\oneeighty2fuzz_r_reg[5] ,\n o2f_ns1_out,\n E,\n f2z_ns5_out,\n \\init_state_r_reg[4] ,\n \\init_state_r_reg[5] ,\n \\prev_samp_r_reg[0] ,\n \\prev_samp_r_reg[1] ,\n rstdiv0_sync_r1_reg_rep__10,\n CLK,\n rstdiv0_sync_r1_reg_rep__9,\n samp_done_ns8_out,\n phy_rddata_en_r1_reg,\n rstdiv0_sync_r1_reg_rep__25,\n rstdiv0_sync_r1_reg_rep__24,\n \\sm_r_reg[0]_0 ,\n rd_active_r1,\n prev_samp_valid_r,\n rstdiv0_sync_r1_reg_rep__20,\n \\data_bytes_r_reg[32] ,\n \\data_bytes_r_reg[24] ,\n rd_active_r2,\n \\sm_r_reg[1] ,\n scanning_right_r_reg,\n phy_rddata_en_r1_reg_0,\n reset_scan,\n prev_samp_r,\n f2o_r_reg,\n scanning_right,\n \\init_state_r_reg[0] ,\n prbs_rdlvl_done_reg,\n prech_req_r_reg,\n ocd_prech_req_r_reg,\n \\init_state_r_reg[4]_0 ,\n prbs_rdlvl_done_reg_rep,\n \\rd_victim_sel_r_reg[0]_0 );\n output oclk_calib_resume_level_reg;\n output \\samps_r_reg[9]_0 ;\n output samp_done;\n output oclk_calib_resume_r_reg_0;\n output prev_samp_valid_r_reg;\n output [1:0]D;\n output \\samps_r_reg[0]_0 ;\n output [1:0]agg_samp_r;\n output \\stg3_r_reg[1] ;\n output \\rd_victim_sel_r_reg[2]_0 ;\n output \\rd_victim_sel_r_reg[1]_0 ;\n output \\rd_victim_sel_r_reg[1]_1 ;\n output [0:0]\\oneeighty2fuzz_r_reg[5] ;\n output o2f_ns1_out;\n output [0:0]E;\n output f2z_ns5_out;\n output \\init_state_r_reg[4] ;\n output \\init_state_r_reg[5] ;\n output \\prev_samp_r_reg[0] ;\n output \\prev_samp_r_reg[1] ;\n input rstdiv0_sync_r1_reg_rep__10;\n input CLK;\n input rstdiv0_sync_r1_reg_rep__9;\n input samp_done_ns8_out;\n input phy_rddata_en_r1_reg;\n input rstdiv0_sync_r1_reg_rep__25;\n input rstdiv0_sync_r1_reg_rep__24;\n input [0:0]\\sm_r_reg[0]_0 ;\n input rd_active_r1;\n input prev_samp_valid_r;\n input rstdiv0_sync_r1_reg_rep__20;\n input \\data_bytes_r_reg[32] ;\n input \\data_bytes_r_reg[24] ;\n input rd_active_r2;\n input [0:0]\\sm_r_reg[1] ;\n input scanning_right_r_reg;\n input phy_rddata_en_r1_reg_0;\n input reset_scan;\n input [1:0]prev_samp_r;\n input f2o_r_reg;\n input scanning_right;\n input \\init_state_r_reg[0] ;\n input prbs_rdlvl_done_reg;\n input prech_req_r_reg;\n input ocd_prech_req_r_reg;\n input [0:0]\\init_state_r_reg[4]_0 ;\n input prbs_rdlvl_done_reg_rep;\n input [0:0]\\rd_victim_sel_r_reg[0]_0 ;\n\n wire CLK;\n wire [1:0]D;\n wire [0:0]E;\n wire agg_samp_ns;\n wire [1:0]agg_samp_r;\n wire \\agg_samp_r[0]_i_1_n_0 ;\n wire \\agg_samp_r[1]_i_1_n_0 ;\n wire \\data_bytes_r_reg[24] ;\n wire \\data_bytes_r_reg[32] ;\n wire data_cnt_ns;\n wire [7:0]data_cnt_r;\n wire \\data_cnt_r[2]_i_1_n_0 ;\n wire \\data_cnt_r[3]_i_1_n_0 ;\n wire \\data_cnt_r[4]_i_1_n_0 ;\n wire \\data_cnt_r[6]_i_3_n_0 ;\n wire \\data_cnt_r[7]_i_1_n_0 ;\n wire \\data_cnt_r[7]_i_2_n_0 ;\n wire f2o_r_reg;\n wire f2z_ns5_out;\n wire \\fuzz2zero_r[5]_i_3_n_0 ;\n wire \\init_state_r_reg[0] ;\n wire \\init_state_r_reg[4] ;\n wire [0:0]\\init_state_r_reg[4]_0 ;\n wire \\init_state_r_reg[5] ;\n wire o2f_ns1_out;\n wire ocd_prech_req_r_reg;\n wire oclk_calib_resume_level_reg;\n wire oclk_calib_resume_r_i_1_n_0;\n wire oclk_calib_resume_r_i_6_n_0;\n wire oclk_calib_resume_r_reg_0;\n wire [0:0]\\oneeighty2fuzz_r_reg[5] ;\n wire oneeighty_ge_thresh;\n wire oneeighty_ge_thresh_carry__0_i_1_n_0;\n wire oneeighty_ge_thresh_carry_i_1_n_0;\n wire oneeighty_ge_thresh_carry_i_2_n_0;\n wire oneeighty_ge_thresh_carry_i_3_n_0;\n wire oneeighty_ge_thresh_carry_i_4_n_0;\n wire oneeighty_ge_thresh_carry_i_5_n_0;\n wire oneeighty_ge_thresh_carry_i_6_n_0;\n wire oneeighty_ge_thresh_carry_n_0;\n wire oneeighty_ge_thresh_carry_n_1;\n wire oneeighty_ge_thresh_carry_n_2;\n wire oneeighty_ge_thresh_carry_n_3;\n wire oneeighty_le_half_thresh;\n wire oneeighty_le_half_thresh_carry__0_i_1_n_0;\n wire oneeighty_le_half_thresh_carry_i_1_n_0;\n wire oneeighty_le_half_thresh_carry_i_2_n_0;\n wire oneeighty_le_half_thresh_carry_i_3_n_0;\n wire oneeighty_le_half_thresh_carry_i_4_n_0;\n wire oneeighty_le_half_thresh_carry_i_5_n_0;\n wire oneeighty_le_half_thresh_carry_i_6_n_0;\n wire oneeighty_le_half_thresh_carry_i_7_n_0;\n wire oneeighty_le_half_thresh_carry_n_0;\n wire oneeighty_le_half_thresh_carry_n_1;\n wire oneeighty_le_half_thresh_carry_n_2;\n wire oneeighty_le_half_thresh_carry_n_3;\n wire oneeighty_ns;\n wire \\oneeighty_r[0]_i_1_n_0 ;\n wire \\oneeighty_r[6]_i_2_n_0 ;\n wire \\oneeighty_r[9]_i_3_n_0 ;\n wire [9:0]oneeighty_r_reg__0;\n wire [6:0]p_0_in;\n wire p_0_in11_in;\n wire [9:1]p_0_in__1;\n wire [9:1]p_0_in__2;\n wire phy_rddata_en_r1_reg;\n wire phy_rddata_en_r1_reg_0;\n wire prbs_rdlvl_done_reg;\n wire prbs_rdlvl_done_reg_rep;\n wire prech_req_r_reg;\n wire [1:0]prev_samp_r;\n wire \\prev_samp_r_reg[0] ;\n wire \\prev_samp_r_reg[1] ;\n wire prev_samp_valid_r;\n wire prev_samp_valid_r_reg;\n wire rd_active_r1;\n wire rd_active_r2;\n wire \\rd_victim_sel_r[0]_i_1_n_0 ;\n wire \\rd_victim_sel_r[1]_i_1_n_0 ;\n wire \\rd_victim_sel_r[2]_i_1_n_0 ;\n wire [0:0]\\rd_victim_sel_r_reg[0]_0 ;\n wire \\rd_victim_sel_r_reg[1]_0 ;\n wire \\rd_victim_sel_r_reg[1]_1 ;\n wire \\rd_victim_sel_r_reg[2]_0 ;\n wire reset_scan;\n wire rstdiv0_sync_r1_reg_rep__10;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__24;\n wire rstdiv0_sync_r1_reg_rep__25;\n wire rstdiv0_sync_r1_reg_rep__9;\n wire samp_done;\n wire samp_done_ns8_out;\n wire samp_done_ns9_in;\n wire samp_done_r_i_1_n_0;\n wire \\samp_result_r_reg_n_0_[0] ;\n wire samps_ns;\n wire [9:0]samps_r;\n wire [8:0]samps_r0;\n wire \\samps_r[1]_i_1_n_0 ;\n wire \\samps_r[4]_i_1_n_0 ;\n wire \\samps_r[5]_i_1_n_0 ;\n wire \\samps_r[7]_i_1_n_0 ;\n wire \\samps_r[8]_i_3_n_0 ;\n wire \\samps_r[8]_i_4_n_0 ;\n wire \\samps_r[8]_i_5_n_0 ;\n wire \\samps_r[9]_i_1_n_0 ;\n wire \\samps_r[9]_i_2_n_0 ;\n wire \\samps_r[9]_i_3_n_0 ;\n wire \\samps_r_reg[0]_0 ;\n wire \\samps_r_reg[9]_0 ;\n wire scanning_right;\n wire scanning_right_r_reg;\n wire \\sm_r[0]_i_1__0_n_0 ;\n wire [0:0]\\sm_r_reg[0]_0 ;\n wire [0:0]\\sm_r_reg[1] ;\n wire \\stg3_r_reg[1] ;\n wire \\u_ocd_edge/samp_valid ;\n wire zero_ge_thresh;\n wire zero_ge_thresh_carry__0_i_1_n_0;\n wire zero_ge_thresh_carry_i_1_n_0;\n wire zero_ge_thresh_carry_i_2_n_0;\n wire zero_ge_thresh_carry_i_3_n_0;\n wire zero_ge_thresh_carry_i_4_n_0;\n wire zero_ge_thresh_carry_i_5_n_0;\n wire zero_ge_thresh_carry_i_6_n_0;\n wire zero_ge_thresh_carry_n_0;\n wire zero_ge_thresh_carry_n_1;\n wire zero_ge_thresh_carry_n_2;\n wire zero_ge_thresh_carry_n_3;\n wire zero_le_half_thresh;\n wire zero_le_half_thresh_carry__0_i_1_n_0;\n wire zero_le_half_thresh_carry_i_1_n_0;\n wire zero_le_half_thresh_carry_i_2_n_0;\n wire zero_le_half_thresh_carry_i_3_n_0;\n wire zero_le_half_thresh_carry_i_4_n_0;\n wire zero_le_half_thresh_carry_i_5_n_0;\n wire zero_le_half_thresh_carry_i_6_n_0;\n wire zero_le_half_thresh_carry_i_7_n_0;\n wire zero_le_half_thresh_carry_n_0;\n wire zero_le_half_thresh_carry_n_1;\n wire zero_le_half_thresh_carry_n_2;\n wire zero_le_half_thresh_carry_n_3;\n wire \\zero_r[0]_i_1_n_0 ;\n wire \\zero_r[6]_i_2_n_0 ;\n wire \\zero_r[9]_i_8_n_0 ;\n wire [9:0]zero_r_reg__0;\n wire [3:0]NLW_oneeighty_ge_thresh_carry_O_UNCONNECTED;\n wire [3:1]NLW_oneeighty_ge_thresh_carry__0_CO_UNCONNECTED;\n wire [3:0]NLW_oneeighty_ge_thresh_carry__0_O_UNCONNECTED;\n wire [3:0]NLW_oneeighty_le_half_thresh_carry_O_UNCONNECTED;\n wire [3:1]NLW_oneeighty_le_half_thresh_carry__0_CO_UNCONNECTED;\n wire [3:0]NLW_oneeighty_le_half_thresh_carry__0_O_UNCONNECTED;\n wire [3:0]NLW_zero_ge_thresh_carry_O_UNCONNECTED;\n wire [3:1]NLW_zero_ge_thresh_carry__0_CO_UNCONNECTED;\n wire [3:0]NLW_zero_ge_thresh_carry__0_O_UNCONNECTED;\n wire [3:0]NLW_zero_le_half_thresh_carry_O_UNCONNECTED;\n wire [3:1]NLW_zero_le_half_thresh_carry__0_CO_UNCONNECTED;\n wire [3:0]NLW_zero_le_half_thresh_carry__0_O_UNCONNECTED;\n\n LUT6 #(\n .INIT(64'hFFFFFFF1F1F1FFF1)) \n \\agg_samp_r[0]_i_1 \n (.I0(\\samps_r_reg[9]_0 ),\n .I1(rstdiv0_sync_r1_reg_rep__20),\n .I2(\\samps_r_reg[0]_0 ),\n .I3(agg_samp_r[0]),\n .I4(agg_samp_ns),\n .I5(\\data_bytes_r_reg[24] ),\n .O(\\agg_samp_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFF1F1F1FFF1)) \n \\agg_samp_r[1]_i_1 \n (.I0(\\samps_r_reg[9]_0 ),\n .I1(rstdiv0_sync_r1_reg_rep__20),\n .I2(\\samps_r_reg[0]_0 ),\n .I3(agg_samp_r[1]),\n .I4(agg_samp_ns),\n .I5(\\data_bytes_r_reg[32] ),\n .O(\\agg_samp_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h4444444444444440)) \n \\agg_samp_r[1]_i_2 \n (.I0(rstdiv0_sync_r1_reg_rep__24),\n .I1(phy_rddata_en_r1_reg),\n .I2(\\rd_victim_sel_r_reg[2]_0 ),\n .I3(\\rd_victim_sel_r_reg[1]_0 ),\n .I4(\\rd_victim_sel_r_reg[1]_1 ),\n .I5(oclk_calib_resume_r_reg_0),\n .O(agg_samp_ns));\n FDRE #(\n .INIT(1'b0)) \n \\agg_samp_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\agg_samp_r[0]_i_1_n_0 ),\n .Q(agg_samp_r[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\agg_samp_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\agg_samp_r[1]_i_1_n_0 ),\n .Q(agg_samp_r[1]),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair432\" *) \n LUT3 #(\n .INIT(8'h7F)) \n \\data_cnt_r[0]_i_1 \n (.I0(data_cnt_r[0]),\n .I1(\\samps_r_reg[9]_0 ),\n .I2(oclk_calib_resume_r_reg_0),\n .O(p_0_in[0]));\n (* SOFT_HLUTNM = \"soft_lutpair432\" *) \n LUT3 #(\n .INIT(8'h82)) \n \\data_cnt_r[1]_i_1 \n (.I0(\\samps_r_reg[9]_0 ),\n .I1(data_cnt_r[1]),\n .I2(data_cnt_r[0]),\n .O(p_0_in[1]));\n (* SOFT_HLUTNM = \"soft_lutpair428\" *) \n LUT3 #(\n .INIT(8'hA9)) \n \\data_cnt_r[2]_i_1 \n (.I0(data_cnt_r[2]),\n .I1(data_cnt_r[1]),\n .I2(data_cnt_r[0]),\n .O(\\data_cnt_r[2]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hAAA9)) \n \\data_cnt_r[3]_i_1 \n (.I0(data_cnt_r[3]),\n .I1(data_cnt_r[2]),\n .I2(data_cnt_r[1]),\n .I3(data_cnt_r[0]),\n .O(\\data_cnt_r[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair425\" *) \n LUT5 #(\n .INIT(32'hAAAAAAA9)) \n \\data_cnt_r[4]_i_1 \n (.I0(data_cnt_r[4]),\n .I1(data_cnt_r[3]),\n .I2(data_cnt_r[0]),\n .I3(data_cnt_r[1]),\n .I4(data_cnt_r[2]),\n .O(\\data_cnt_r[4]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair429\" *) \n LUT3 #(\n .INIT(8'h28)) \n \\data_cnt_r[5]_i_1 \n (.I0(\\samps_r_reg[9]_0 ),\n .I1(\\data_cnt_r[6]_i_3_n_0 ),\n .I2(data_cnt_r[5]),\n .O(p_0_in[5]));\n LUT3 #(\n .INIT(8'h31)) \n \\data_cnt_r[6]_i_1 \n (.I0(\\samps_r_reg[9]_0 ),\n .I1(rstdiv0_sync_r1_reg_rep__24),\n .I2(phy_rddata_en_r1_reg),\n .O(data_cnt_ns));\n (* SOFT_HLUTNM = \"soft_lutpair429\" *) \n LUT4 #(\n .INIT(16'h8A20)) \n \\data_cnt_r[6]_i_2 \n (.I0(\\samps_r_reg[9]_0 ),\n .I1(data_cnt_r[5]),\n .I2(\\data_cnt_r[6]_i_3_n_0 ),\n .I3(data_cnt_r[6]),\n .O(p_0_in[6]));\n (* SOFT_HLUTNM = \"soft_lutpair425\" *) \n LUT5 #(\n .INIT(32'h00000001)) \n \\data_cnt_r[6]_i_3 \n (.I0(data_cnt_r[3]),\n .I1(data_cnt_r[0]),\n .I2(data_cnt_r[1]),\n .I3(data_cnt_r[2]),\n .I4(data_cnt_r[4]),\n .O(\\data_cnt_r[6]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'h0323)) \n \\data_cnt_r[7]_i_1 \n (.I0(phy_rddata_en_r1_reg),\n .I1(rstdiv0_sync_r1_reg_rep__24),\n .I2(\\samps_r_reg[9]_0 ),\n .I3(oclk_calib_resume_r_reg_0),\n .O(\\data_cnt_r[7]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hAAA6)) \n \\data_cnt_r[7]_i_2 \n (.I0(data_cnt_r[7]),\n .I1(\\data_cnt_r[6]_i_3_n_0 ),\n .I2(data_cnt_r[5]),\n .I3(data_cnt_r[6]),\n .O(\\data_cnt_r[7]_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\data_cnt_r_reg[0] \n (.C(CLK),\n .CE(data_cnt_ns),\n .D(p_0_in[0]),\n .Q(data_cnt_r[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_cnt_r_reg[1] \n (.C(CLK),\n .CE(data_cnt_ns),\n .D(p_0_in[1]),\n .Q(data_cnt_r[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_cnt_r_reg[2] \n (.C(CLK),\n .CE(data_cnt_ns),\n .D(\\data_cnt_r[2]_i_1_n_0 ),\n .Q(data_cnt_r[2]),\n .R(\\data_cnt_r[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\data_cnt_r_reg[3] \n (.C(CLK),\n .CE(data_cnt_ns),\n .D(\\data_cnt_r[3]_i_1_n_0 ),\n .Q(data_cnt_r[3]),\n .R(\\data_cnt_r[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\data_cnt_r_reg[4] \n (.C(CLK),\n .CE(data_cnt_ns),\n .D(\\data_cnt_r[4]_i_1_n_0 ),\n .Q(data_cnt_r[4]),\n .R(\\data_cnt_r[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\data_cnt_r_reg[5] \n (.C(CLK),\n .CE(data_cnt_ns),\n .D(p_0_in[5]),\n .Q(data_cnt_r[5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_cnt_r_reg[6] \n (.C(CLK),\n .CE(data_cnt_ns),\n .D(p_0_in[6]),\n .Q(data_cnt_r[6]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\data_cnt_r_reg[7] \n (.C(CLK),\n .CE(data_cnt_ns),\n .D(\\data_cnt_r[7]_i_2_n_0 ),\n .Q(data_cnt_r[7]),\n .R(\\data_cnt_r[7]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\fuzz2zero_r[5]_i_1 \n (.I0(f2z_ns5_out),\n .I1(reset_scan),\n .O(E));\n LUT6 #(\n .INIT(64'h0080808000000000)) \n \\fuzz2zero_r[5]_i_2 \n (.I0(\\fuzz2zero_r[5]_i_3_n_0 ),\n .I1(\\u_ocd_edge/samp_valid ),\n .I2(prev_samp_valid_r),\n .I3(f2o_r_reg),\n .I4(prev_samp_r[1]),\n .I5(D[0]),\n .O(f2z_ns5_out));\n LUT3 #(\n .INIT(8'h04)) \n \\fuzz2zero_r[5]_i_3 \n (.I0(D[1]),\n .I1(scanning_right),\n .I2(prev_samp_r[0]),\n .O(\\fuzz2zero_r[5]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h1111111111111110)) \n \\init_state_r[4]_i_36 \n (.I0(\\init_state_r_reg[0] ),\n .I1(oclk_calib_resume_level_reg),\n .I2(prbs_rdlvl_done_reg),\n .I3(prech_req_r_reg),\n .I4(ocd_prech_req_r_reg),\n .I5(\\init_state_r_reg[4]_0 ),\n .O(\\init_state_r_reg[4] ));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\init_state_r[5]_i_47 \n (.I0(oclk_calib_resume_level_reg),\n .I1(ocd_prech_req_r_reg),\n .I2(prech_req_r_reg),\n .I3(prbs_rdlvl_done_reg_rep),\n .O(\\init_state_r_reg[5] ));\n LUT5 #(\n .INIT(32'hAAAABAAA)) \n oclk_calib_resume_r_i_1\n (.I0(samp_done_ns8_out),\n .I1(oclk_calib_resume_r_reg_0),\n .I2(phy_rddata_en_r1_reg),\n .I3(\\samps_r_reg[9]_0 ),\n .I4(samp_done_ns9_in),\n .O(oclk_calib_resume_r_i_1_n_0));\n LUT5 #(\n .INIT(32'hFFFFFEFF)) \n oclk_calib_resume_r_i_3\n (.I0(data_cnt_r[7]),\n .I1(data_cnt_r[4]),\n .I2(data_cnt_r[3]),\n .I3(data_cnt_r[0]),\n .I4(oclk_calib_resume_r_i_6_n_0),\n .O(oclk_calib_resume_r_reg_0));\n LUT6 #(\n .INIT(64'hAAAAAAABAAAAAAAA)) \n oclk_calib_resume_r_i_4\n (.I0(samp_done),\n .I1(oclk_calib_resume_r_reg_0),\n .I2(\\rd_victim_sel_r_reg[1]_1 ),\n .I3(\\rd_victim_sel_r_reg[1]_0 ),\n .I4(\\rd_victim_sel_r_reg[2]_0 ),\n .I5(\\samps_r[8]_i_3_n_0 ),\n .O(samp_done_ns9_in));\n (* SOFT_HLUTNM = \"soft_lutpair428\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n oclk_calib_resume_r_i_6\n (.I0(data_cnt_r[6]),\n .I1(data_cnt_r[5]),\n .I2(data_cnt_r[1]),\n .I3(data_cnt_r[2]),\n .O(oclk_calib_resume_r_i_6_n_0));\n FDRE #(\n .INIT(1'b0)) \n oclk_calib_resume_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(oclk_calib_resume_r_i_1_n_0),\n .Q(oclk_calib_resume_level_reg),\n .R(rstdiv0_sync_r1_reg_rep__10));\n LUT2 #(\n .INIT(4'h2)) \n \\oneeighty2fuzz_r[5]_i_1 \n (.I0(o2f_ns1_out),\n .I1(reset_scan),\n .O(\\oneeighty2fuzz_r_reg[5] ));\n LUT6 #(\n .INIT(64'h8000800000008000)) \n \\oneeighty2fuzz_r[5]_i_2 \n (.I0(\\fuzz2zero_r[5]_i_3_n_0 ),\n .I1(\\u_ocd_edge/samp_valid ),\n .I2(prev_samp_valid_r),\n .I3(prev_samp_r[1]),\n .I4(D[0]),\n .I5(f2o_r_reg),\n .O(o2f_ns1_out));\n CARRY4 oneeighty_ge_thresh_carry\n (.CI(1'b0),\n .CO({oneeighty_ge_thresh_carry_n_0,oneeighty_ge_thresh_carry_n_1,oneeighty_ge_thresh_carry_n_2,oneeighty_ge_thresh_carry_n_3}),\n .CYINIT(1'b1),\n .DI({1'b0,oneeighty_ge_thresh_carry_i_1_n_0,oneeighty_r_reg__0[3],oneeighty_ge_thresh_carry_i_2_n_0}),\n .O(NLW_oneeighty_ge_thresh_carry_O_UNCONNECTED[3:0]),\n .S({oneeighty_ge_thresh_carry_i_3_n_0,oneeighty_ge_thresh_carry_i_4_n_0,oneeighty_ge_thresh_carry_i_5_n_0,oneeighty_ge_thresh_carry_i_6_n_0}));\n CARRY4 oneeighty_ge_thresh_carry__0\n (.CI(oneeighty_ge_thresh_carry_n_0),\n .CO({NLW_oneeighty_ge_thresh_carry__0_CO_UNCONNECTED[3:1],oneeighty_ge_thresh}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,oneeighty_r_reg__0[9]}),\n .O(NLW_oneeighty_ge_thresh_carry__0_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,1'b0,oneeighty_ge_thresh_carry__0_i_1_n_0}));\n LUT2 #(\n .INIT(4'h2)) \n oneeighty_ge_thresh_carry__0_i_1\n (.I0(oneeighty_r_reg__0[8]),\n .I1(oneeighty_r_reg__0[9]),\n .O(oneeighty_ge_thresh_carry__0_i_1_n_0));\n LUT2 #(\n .INIT(4'h8)) \n oneeighty_ge_thresh_carry_i_1\n (.I0(oneeighty_r_reg__0[4]),\n .I1(oneeighty_r_reg__0[5]),\n .O(oneeighty_ge_thresh_carry_i_1_n_0));\n LUT2 #(\n .INIT(4'h8)) \n oneeighty_ge_thresh_carry_i_2\n (.I0(oneeighty_r_reg__0[1]),\n .I1(oneeighty_r_reg__0[0]),\n .O(oneeighty_ge_thresh_carry_i_2_n_0));\n LUT2 #(\n .INIT(4'h8)) \n oneeighty_ge_thresh_carry_i_3\n (.I0(oneeighty_r_reg__0[7]),\n .I1(oneeighty_r_reg__0[6]),\n .O(oneeighty_ge_thresh_carry_i_3_n_0));\n LUT2 #(\n .INIT(4'h2)) \n oneeighty_ge_thresh_carry_i_4\n (.I0(oneeighty_r_reg__0[5]),\n .I1(oneeighty_r_reg__0[4]),\n .O(oneeighty_ge_thresh_carry_i_4_n_0));\n LUT2 #(\n .INIT(4'h2)) \n oneeighty_ge_thresh_carry_i_5\n (.I0(oneeighty_r_reg__0[2]),\n .I1(oneeighty_r_reg__0[3]),\n .O(oneeighty_ge_thresh_carry_i_5_n_0));\n LUT2 #(\n .INIT(4'h2)) \n oneeighty_ge_thresh_carry_i_6\n (.I0(oneeighty_r_reg__0[1]),\n .I1(oneeighty_r_reg__0[0]),\n .O(oneeighty_ge_thresh_carry_i_6_n_0));\n CARRY4 oneeighty_le_half_thresh_carry\n (.CI(1'b0),\n .CO({oneeighty_le_half_thresh_carry_n_0,oneeighty_le_half_thresh_carry_n_1,oneeighty_le_half_thresh_carry_n_2,oneeighty_le_half_thresh_carry_n_3}),\n .CYINIT(1'b1),\n .DI({oneeighty_le_half_thresh_carry_i_1_n_0,oneeighty_le_half_thresh_carry_i_2_n_0,1'b0,oneeighty_le_half_thresh_carry_i_3_n_0}),\n .O(NLW_oneeighty_le_half_thresh_carry_O_UNCONNECTED[3:0]),\n .S({oneeighty_le_half_thresh_carry_i_4_n_0,oneeighty_le_half_thresh_carry_i_5_n_0,oneeighty_le_half_thresh_carry_i_6_n_0,oneeighty_le_half_thresh_carry_i_7_n_0}));\n CARRY4 oneeighty_le_half_thresh_carry__0\n (.CI(oneeighty_le_half_thresh_carry_n_0),\n .CO({NLW_oneeighty_le_half_thresh_carry__0_CO_UNCONNECTED[3:1],oneeighty_le_half_thresh}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(NLW_oneeighty_le_half_thresh_carry__0_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,1'b0,oneeighty_le_half_thresh_carry__0_i_1_n_0}));\n LUT2 #(\n .INIT(4'h1)) \n oneeighty_le_half_thresh_carry__0_i_1\n (.I0(oneeighty_r_reg__0[8]),\n .I1(oneeighty_r_reg__0[9]),\n .O(oneeighty_le_half_thresh_carry__0_i_1_n_0));\n LUT2 #(\n .INIT(4'h7)) \n oneeighty_le_half_thresh_carry_i_1\n (.I0(oneeighty_r_reg__0[6]),\n .I1(oneeighty_r_reg__0[7]),\n .O(oneeighty_le_half_thresh_carry_i_1_n_0));\n LUT2 #(\n .INIT(4'h7)) \n oneeighty_le_half_thresh_carry_i_2\n (.I0(oneeighty_r_reg__0[5]),\n .I1(oneeighty_r_reg__0[4]),\n .O(oneeighty_le_half_thresh_carry_i_2_n_0));\n LUT2 #(\n .INIT(4'h7)) \n oneeighty_le_half_thresh_carry_i_3\n (.I0(oneeighty_r_reg__0[0]),\n .I1(oneeighty_r_reg__0[1]),\n .O(oneeighty_le_half_thresh_carry_i_3_n_0));\n LUT2 #(\n .INIT(4'h8)) \n oneeighty_le_half_thresh_carry_i_4\n (.I0(oneeighty_r_reg__0[7]),\n .I1(oneeighty_r_reg__0[6]),\n .O(oneeighty_le_half_thresh_carry_i_4_n_0));\n LUT2 #(\n .INIT(4'h8)) \n oneeighty_le_half_thresh_carry_i_5\n (.I0(oneeighty_r_reg__0[4]),\n .I1(oneeighty_r_reg__0[5]),\n .O(oneeighty_le_half_thresh_carry_i_5_n_0));\n LUT2 #(\n .INIT(4'h1)) \n oneeighty_le_half_thresh_carry_i_6\n (.I0(oneeighty_r_reg__0[2]),\n .I1(oneeighty_r_reg__0[3]),\n .O(oneeighty_le_half_thresh_carry_i_6_n_0));\n LUT2 #(\n .INIT(4'h8)) \n oneeighty_le_half_thresh_carry_i_7\n (.I0(oneeighty_r_reg__0[1]),\n .I1(oneeighty_r_reg__0[0]),\n .O(oneeighty_le_half_thresh_carry_i_7_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair437\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\oneeighty_r[0]_i_1 \n (.I0(oneeighty_r_reg__0[0]),\n .O(\\oneeighty_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair437\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\oneeighty_r[1]_i_1 \n (.I0(oneeighty_r_reg__0[1]),\n .I1(oneeighty_r_reg__0[0]),\n .O(p_0_in__2[1]));\n (* SOFT_HLUTNM = \"soft_lutpair434\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\oneeighty_r[2]_i_1 \n (.I0(oneeighty_r_reg__0[2]),\n .I1(oneeighty_r_reg__0[0]),\n .I2(oneeighty_r_reg__0[1]),\n .O(p_0_in__2[2]));\n (* SOFT_HLUTNM = \"soft_lutpair422\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\oneeighty_r[3]_i_1 \n (.I0(oneeighty_r_reg__0[3]),\n .I1(oneeighty_r_reg__0[1]),\n .I2(oneeighty_r_reg__0[0]),\n .I3(oneeighty_r_reg__0[2]),\n .O(p_0_in__2[3]));\n (* SOFT_HLUTNM = \"soft_lutpair422\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\oneeighty_r[4]_i_1 \n (.I0(oneeighty_r_reg__0[4]),\n .I1(oneeighty_r_reg__0[2]),\n .I2(oneeighty_r_reg__0[0]),\n .I3(oneeighty_r_reg__0[1]),\n .I4(oneeighty_r_reg__0[3]),\n .O(p_0_in__2[4]));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n \\oneeighty_r[5]_i_1 \n (.I0(oneeighty_r_reg__0[5]),\n .I1(oneeighty_r_reg__0[3]),\n .I2(oneeighty_r_reg__0[1]),\n .I3(oneeighty_r_reg__0[0]),\n .I4(oneeighty_r_reg__0[2]),\n .I5(oneeighty_r_reg__0[4]),\n .O(p_0_in__2[5]));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n \\oneeighty_r[6]_i_1 \n (.I0(oneeighty_r_reg__0[6]),\n .I1(oneeighty_r_reg__0[4]),\n .I2(oneeighty_r_reg__0[5]),\n .I3(oneeighty_r_reg__0[3]),\n .I4(\\oneeighty_r[6]_i_2_n_0 ),\n .I5(oneeighty_r_reg__0[2]),\n .O(p_0_in__2[6]));\n (* SOFT_HLUTNM = \"soft_lutpair434\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\oneeighty_r[6]_i_2 \n (.I0(oneeighty_r_reg__0[1]),\n .I1(oneeighty_r_reg__0[0]),\n .O(\\oneeighty_r[6]_i_2_n_0 ));\n LUT3 #(\n .INIT(8'h6A)) \n \\oneeighty_r[7]_i_1 \n (.I0(oneeighty_r_reg__0[7]),\n .I1(\\oneeighty_r[9]_i_3_n_0 ),\n .I2(oneeighty_r_reg__0[6]),\n .O(p_0_in__2[7]));\n (* SOFT_HLUTNM = \"soft_lutpair427\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\oneeighty_r[8]_i_1 \n (.I0(oneeighty_r_reg__0[8]),\n .I1(oneeighty_r_reg__0[7]),\n .I2(oneeighty_r_reg__0[6]),\n .I3(\\oneeighty_r[9]_i_3_n_0 ),\n .O(p_0_in__2[8]));\n LUT2 #(\n .INIT(4'h8)) \n \\oneeighty_r[9]_i_1 \n (.I0(\\samps_r_reg[0]_0 ),\n .I1(\\data_bytes_r_reg[32] ),\n .O(oneeighty_ns));\n (* SOFT_HLUTNM = \"soft_lutpair427\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\oneeighty_r[9]_i_2 \n (.I0(oneeighty_r_reg__0[9]),\n .I1(\\oneeighty_r[9]_i_3_n_0 ),\n .I2(oneeighty_r_reg__0[6]),\n .I3(oneeighty_r_reg__0[7]),\n .I4(oneeighty_r_reg__0[8]),\n .O(p_0_in__2[9]));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\oneeighty_r[9]_i_3 \n (.I0(oneeighty_r_reg__0[2]),\n .I1(oneeighty_r_reg__0[0]),\n .I2(oneeighty_r_reg__0[1]),\n .I3(oneeighty_r_reg__0[3]),\n .I4(oneeighty_r_reg__0[5]),\n .I5(oneeighty_r_reg__0[4]),\n .O(\\oneeighty_r[9]_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\oneeighty_r_reg[0] \n (.C(CLK),\n .CE(oneeighty_ns),\n .D(\\oneeighty_r[0]_i_1_n_0 ),\n .Q(oneeighty_r_reg__0[0]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\oneeighty_r_reg[1] \n (.C(CLK),\n .CE(oneeighty_ns),\n .D(p_0_in__2[1]),\n .Q(oneeighty_r_reg__0[1]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\oneeighty_r_reg[2] \n (.C(CLK),\n .CE(oneeighty_ns),\n .D(p_0_in__2[2]),\n .Q(oneeighty_r_reg__0[2]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\oneeighty_r_reg[3] \n (.C(CLK),\n .CE(oneeighty_ns),\n .D(p_0_in__2[3]),\n .Q(oneeighty_r_reg__0[3]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\oneeighty_r_reg[4] \n (.C(CLK),\n .CE(oneeighty_ns),\n .D(p_0_in__2[4]),\n .Q(oneeighty_r_reg__0[4]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\oneeighty_r_reg[5] \n (.C(CLK),\n .CE(oneeighty_ns),\n .D(p_0_in__2[5]),\n .Q(oneeighty_r_reg__0[5]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\oneeighty_r_reg[6] \n (.C(CLK),\n .CE(oneeighty_ns),\n .D(p_0_in__2[6]),\n .Q(oneeighty_r_reg__0[6]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\oneeighty_r_reg[7] \n (.C(CLK),\n .CE(oneeighty_ns),\n .D(p_0_in__2[7]),\n .Q(oneeighty_r_reg__0[7]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\oneeighty_r_reg[8] \n (.C(CLK),\n .CE(oneeighty_ns),\n .D(p_0_in__2[8]),\n .Q(oneeighty_r_reg__0[8]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\oneeighty_r_reg[9] \n (.C(CLK),\n .CE(oneeighty_ns),\n .D(p_0_in__2[9]),\n .Q(oneeighty_r_reg__0[9]),\n .R(\\sm_r_reg[0]_0 ));\n LUT6 #(\n .INIT(64'h003AFFFF003A0000)) \n \\prev_samp_r[0]_i_1 \n (.I0(zero_ge_thresh),\n .I1(zero_le_half_thresh),\n .I2(\\samp_result_r_reg_n_0_[0] ),\n .I3(rstdiv0_sync_r1_reg_rep__24),\n .I4(\\u_ocd_edge/samp_valid ),\n .I5(prev_samp_r[0]),\n .O(\\prev_samp_r_reg[0] ));\n LUT6 #(\n .INIT(64'h0454FFFF04540000)) \n \\prev_samp_r[1]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__24),\n .I1(oneeighty_ge_thresh),\n .I2(p_0_in11_in),\n .I3(oneeighty_le_half_thresh),\n .I4(\\u_ocd_edge/samp_valid ),\n .I5(prev_samp_r[1]),\n .O(\\prev_samp_r_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair431\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\prev_samp_r[1]_i_2 \n (.I0(samp_done),\n .I1(rd_active_r1),\n .O(\\u_ocd_edge/samp_valid ));\n (* SOFT_HLUTNM = \"soft_lutpair431\" *) \n LUT3 #(\n .INIT(8'hF8)) \n prev_samp_valid_r_i_1\n (.I0(samp_done),\n .I1(rd_active_r1),\n .I2(prev_samp_valid_r),\n .O(prev_samp_valid_r_reg));\n LUT6 #(\n .INIT(64'h6664666466640000)) \n \\rd_victim_sel_r[0]_i_1 \n (.I0(phy_rddata_en_r1_reg_0),\n .I1(\\rd_victim_sel_r_reg[1]_1 ),\n .I2(\\rd_victim_sel_r_reg[1]_0 ),\n .I3(\\rd_victim_sel_r_reg[2]_0 ),\n .I4(rstdiv0_sync_r1_reg_rep__24),\n .I5(\\samps_r_reg[9]_0 ),\n .O(\\rd_victim_sel_r[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h78787800)) \n \\rd_victim_sel_r[1]_i_1 \n (.I0(phy_rddata_en_r1_reg_0),\n .I1(\\rd_victim_sel_r_reg[1]_1 ),\n .I2(\\rd_victim_sel_r_reg[1]_0 ),\n .I3(rstdiv0_sync_r1_reg_rep__20),\n .I4(\\samps_r_reg[9]_0 ),\n .O(\\rd_victim_sel_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h7F807F807F800000)) \n \\rd_victim_sel_r[2]_i_1 \n (.I0(phy_rddata_en_r1_reg_0),\n .I1(\\rd_victim_sel_r_reg[1]_1 ),\n .I2(\\rd_victim_sel_r_reg[1]_0 ),\n .I3(\\rd_victim_sel_r_reg[2]_0 ),\n .I4(rstdiv0_sync_r1_reg_rep__24),\n .I5(\\samps_r_reg[9]_0 ),\n .O(\\rd_victim_sel_r[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rd_victim_sel_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_victim_sel_r[0]_i_1_n_0 ),\n .Q(\\rd_victim_sel_r_reg[1]_1 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rd_victim_sel_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_victim_sel_r[1]_i_1_n_0 ),\n .Q(\\rd_victim_sel_r_reg[1]_0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rd_victim_sel_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_victim_sel_r[2]_i_1_n_0 ),\n .Q(\\rd_victim_sel_r_reg[2]_0 ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000AAEAAA2A)) \n samp_done_r_i_1\n (.I0(samp_done),\n .I1(\\samps_r_reg[9]_0 ),\n .I2(phy_rddata_en_r1_reg),\n .I3(rstdiv0_sync_r1_reg_rep__25),\n .I4(samp_done_ns9_in),\n .I5(samp_done_ns8_out),\n .O(samp_done_r_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n samp_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(samp_done_r_i_1_n_0),\n .Q(samp_done),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h000000003FFF8080)) \n \\samp_result_r[0]_i_1 \n (.I0(zero_ge_thresh),\n .I1(rd_active_r1),\n .I2(samp_done),\n .I3(zero_le_half_thresh),\n .I4(\\samp_result_r_reg_n_0_[0] ),\n .I5(rstdiv0_sync_r1_reg_rep__24),\n .O(D[0]));\n LUT6 #(\n .INIT(64'h1515400055554000)) \n \\samp_result_r[1]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__24),\n .I1(rd_active_r1),\n .I2(samp_done),\n .I3(oneeighty_ge_thresh),\n .I4(p_0_in11_in),\n .I5(oneeighty_le_half_thresh),\n .O(D[1]));\n FDRE #(\n .INIT(1'b0)) \n \\samp_result_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(D[0]),\n .Q(\\samp_result_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\samp_result_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(D[1]),\n .Q(p_0_in11_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair435\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\samps_r[0]_i_1 \n (.I0(samps_r[0]),\n .O(samps_r0[0]));\n LUT4 #(\n .INIT(16'h9990)) \n \\samps_r[1]_i_1 \n (.I0(samps_r[1]),\n .I1(samps_r[0]),\n .I2(\\samps_r_reg[9]_0 ),\n .I3(rstdiv0_sync_r1_reg_rep__24),\n .O(\\samps_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair435\" *) \n LUT3 #(\n .INIT(8'hA9)) \n \\samps_r[2]_i_1 \n (.I0(samps_r[2]),\n .I1(samps_r[1]),\n .I2(samps_r[0]),\n .O(samps_r0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair424\" *) \n LUT4 #(\n .INIT(16'hAAA9)) \n \\samps_r[3]_i_1 \n (.I0(samps_r[3]),\n .I1(samps_r[2]),\n .I2(samps_r[0]),\n .I3(samps_r[1]),\n .O(samps_r0[3]));\n LUT6 #(\n .INIT(64'h00000000FFFE0001)) \n \\samps_r[4]_i_1 \n (.I0(samps_r[2]),\n .I1(samps_r[0]),\n .I2(samps_r[1]),\n .I3(samps_r[3]),\n .I4(samps_r[4]),\n .I5(\\sm_r_reg[0]_0 ),\n .O(\\samps_r[4]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h9990)) \n \\samps_r[5]_i_1 \n (.I0(\\samps_r[8]_i_4_n_0 ),\n .I1(samps_r[5]),\n .I2(\\samps_r_reg[9]_0 ),\n .I3(rstdiv0_sync_r1_reg_rep__24),\n .O(\\samps_r[5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair430\" *) \n LUT3 #(\n .INIT(8'hA9)) \n \\samps_r[6]_i_1 \n (.I0(samps_r[6]),\n .I1(\\samps_r[8]_i_4_n_0 ),\n .I2(samps_r[5]),\n .O(samps_r0[6]));\n (* SOFT_HLUTNM = \"soft_lutpair430\" *) \n LUT4 #(\n .INIT(16'hAAA9)) \n \\samps_r[7]_i_1 \n (.I0(samps_r[7]),\n .I1(samps_r[6]),\n .I2(samps_r[5]),\n .I3(\\samps_r[8]_i_4_n_0 ),\n .O(\\samps_r[7]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h1F11)) \n \\samps_r[8]_i_1 \n (.I0(\\samps_r_reg[9]_0 ),\n .I1(rstdiv0_sync_r1_reg_rep__24),\n .I2(\\samps_r[8]_i_3_n_0 ),\n .I3(\\samps_r_reg[0]_0 ),\n .O(samps_ns));\n (* SOFT_HLUTNM = \"soft_lutpair426\" *) \n LUT5 #(\n .INIT(32'hAAAAAAA9)) \n \\samps_r[8]_i_2 \n (.I0(samps_r[8]),\n .I1(\\samps_r[8]_i_4_n_0 ),\n .I2(samps_r[5]),\n .I3(samps_r[6]),\n .I4(samps_r[7]),\n .O(samps_r0[8]));\n LUT5 #(\n .INIT(32'h00000001)) \n \\samps_r[8]_i_3 \n (.I0(samps_r[2]),\n .I1(samps_r[9]),\n .I2(samps_r[6]),\n .I3(samps_r[5]),\n .I4(\\samps_r[8]_i_5_n_0 ),\n .O(\\samps_r[8]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair424\" *) \n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n \\samps_r[8]_i_4 \n (.I0(samps_r[4]),\n .I1(samps_r[3]),\n .I2(samps_r[2]),\n .I3(samps_r[0]),\n .I4(samps_r[1]),\n .O(\\samps_r[8]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFEFF)) \n \\samps_r[8]_i_5 \n (.I0(samps_r[4]),\n .I1(samps_r[3]),\n .I2(samps_r[8]),\n .I3(samps_r[0]),\n .I4(samps_r[1]),\n .I5(samps_r[7]),\n .O(\\samps_r[8]_i_5_n_0 ));\n LUT4 #(\n .INIT(16'h1F11)) \n \\samps_r[9]_i_1 \n (.I0(\\samps_r_reg[9]_0 ),\n .I1(rstdiv0_sync_r1_reg_rep__20),\n .I2(\\samps_r[8]_i_3_n_0 ),\n .I3(\\samps_r_reg[0]_0 ),\n .O(\\samps_r[9]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hD2D2D2FF)) \n \\samps_r[9]_i_2 \n (.I0(\\samps_r[9]_i_3_n_0 ),\n .I1(samps_r[8]),\n .I2(samps_r[9]),\n .I3(\\samps_r_reg[9]_0 ),\n .I4(rstdiv0_sync_r1_reg_rep__24),\n .O(\\samps_r[9]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair426\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\samps_r[9]_i_3 \n (.I0(samps_r[7]),\n .I1(samps_r[6]),\n .I2(samps_r[5]),\n .I3(\\samps_r[8]_i_4_n_0 ),\n .O(\\samps_r[9]_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\samps_r_reg[0] \n (.C(CLK),\n .CE(samps_ns),\n .D(samps_r0[0]),\n .Q(samps_r[0]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\samps_r_reg[1] \n (.C(CLK),\n .CE(\\samps_r[9]_i_1_n_0 ),\n .D(\\samps_r[1]_i_1_n_0 ),\n .Q(samps_r[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\samps_r_reg[2] \n (.C(CLK),\n .CE(samps_ns),\n .D(samps_r0[2]),\n .Q(samps_r[2]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\samps_r_reg[3] \n (.C(CLK),\n .CE(samps_ns),\n .D(samps_r0[3]),\n .Q(samps_r[3]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\samps_r_reg[4] \n (.C(CLK),\n .CE(\\samps_r[9]_i_1_n_0 ),\n .D(\\samps_r[4]_i_1_n_0 ),\n .Q(samps_r[4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\samps_r_reg[5] \n (.C(CLK),\n .CE(\\samps_r[9]_i_1_n_0 ),\n .D(\\samps_r[5]_i_1_n_0 ),\n .Q(samps_r[5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\samps_r_reg[6] \n (.C(CLK),\n .CE(samps_ns),\n .D(samps_r0[6]),\n .Q(samps_r[6]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\samps_r_reg[7] \n (.C(CLK),\n .CE(samps_ns),\n .D(\\samps_r[7]_i_1_n_0 ),\n .Q(samps_r[7]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\samps_r_reg[8] \n (.C(CLK),\n .CE(samps_ns),\n .D(samps_r0[8]),\n .Q(samps_r[8]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\samps_r_reg[9] \n (.C(CLK),\n .CE(\\samps_r[9]_i_1_n_0 ),\n .D(\\samps_r[9]_i_2_n_0 ),\n .Q(samps_r[9]),\n .R(1'b0));\n LUT4 #(\n .INIT(16'hAEEE)) \n \\sm_r[0]_i_1__0 \n (.I0(samp_done_ns8_out),\n .I1(\\samps_r_reg[9]_0 ),\n .I2(phy_rddata_en_r1_reg),\n .I3(samp_done_ns9_in),\n .O(\\sm_r[0]_i_1__0_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\sm_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\sm_r[0]_i_1__0_n_0 ),\n .Q(\\samps_r_reg[9]_0 ),\n .R(rstdiv0_sync_r1_reg_rep__9));\n LUT4 #(\n .INIT(16'hFFF7)) \n \\stg3_r[5]_i_14 \n (.I0(samp_done),\n .I1(rd_active_r2),\n .I2(\\sm_r_reg[1] ),\n .I3(scanning_right_r_reg),\n .O(\\stg3_r_reg[1] ));\n CARRY4 zero_ge_thresh_carry\n (.CI(1'b0),\n .CO({zero_ge_thresh_carry_n_0,zero_ge_thresh_carry_n_1,zero_ge_thresh_carry_n_2,zero_ge_thresh_carry_n_3}),\n .CYINIT(1'b1),\n .DI({1'b0,zero_ge_thresh_carry_i_1_n_0,zero_r_reg__0[3],zero_ge_thresh_carry_i_2_n_0}),\n .O(NLW_zero_ge_thresh_carry_O_UNCONNECTED[3:0]),\n .S({zero_ge_thresh_carry_i_3_n_0,zero_ge_thresh_carry_i_4_n_0,zero_ge_thresh_carry_i_5_n_0,zero_ge_thresh_carry_i_6_n_0}));\n CARRY4 zero_ge_thresh_carry__0\n (.CI(zero_ge_thresh_carry_n_0),\n .CO({NLW_zero_ge_thresh_carry__0_CO_UNCONNECTED[3:1],zero_ge_thresh}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,zero_r_reg__0[9]}),\n .O(NLW_zero_ge_thresh_carry__0_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,1'b0,zero_ge_thresh_carry__0_i_1_n_0}));\n LUT2 #(\n .INIT(4'h2)) \n zero_ge_thresh_carry__0_i_1\n (.I0(zero_r_reg__0[8]),\n .I1(zero_r_reg__0[9]),\n .O(zero_ge_thresh_carry__0_i_1_n_0));\n LUT2 #(\n .INIT(4'h8)) \n zero_ge_thresh_carry_i_1\n (.I0(zero_r_reg__0[4]),\n .I1(zero_r_reg__0[5]),\n .O(zero_ge_thresh_carry_i_1_n_0));\n LUT2 #(\n .INIT(4'h8)) \n zero_ge_thresh_carry_i_2\n (.I0(zero_r_reg__0[1]),\n .I1(zero_r_reg__0[0]),\n .O(zero_ge_thresh_carry_i_2_n_0));\n LUT2 #(\n .INIT(4'h8)) \n zero_ge_thresh_carry_i_3\n (.I0(zero_r_reg__0[6]),\n .I1(zero_r_reg__0[7]),\n .O(zero_ge_thresh_carry_i_3_n_0));\n LUT2 #(\n .INIT(4'h2)) \n zero_ge_thresh_carry_i_4\n (.I0(zero_r_reg__0[5]),\n .I1(zero_r_reg__0[4]),\n .O(zero_ge_thresh_carry_i_4_n_0));\n LUT2 #(\n .INIT(4'h2)) \n zero_ge_thresh_carry_i_5\n (.I0(zero_r_reg__0[2]),\n .I1(zero_r_reg__0[3]),\n .O(zero_ge_thresh_carry_i_5_n_0));\n LUT2 #(\n .INIT(4'h2)) \n zero_ge_thresh_carry_i_6\n (.I0(zero_r_reg__0[1]),\n .I1(zero_r_reg__0[0]),\n .O(zero_ge_thresh_carry_i_6_n_0));\n CARRY4 zero_le_half_thresh_carry\n (.CI(1'b0),\n .CO({zero_le_half_thresh_carry_n_0,zero_le_half_thresh_carry_n_1,zero_le_half_thresh_carry_n_2,zero_le_half_thresh_carry_n_3}),\n .CYINIT(1'b1),\n .DI({zero_le_half_thresh_carry_i_1_n_0,zero_le_half_thresh_carry_i_2_n_0,1'b0,zero_le_half_thresh_carry_i_3_n_0}),\n .O(NLW_zero_le_half_thresh_carry_O_UNCONNECTED[3:0]),\n .S({zero_le_half_thresh_carry_i_4_n_0,zero_le_half_thresh_carry_i_5_n_0,zero_le_half_thresh_carry_i_6_n_0,zero_le_half_thresh_carry_i_7_n_0}));\n CARRY4 zero_le_half_thresh_carry__0\n (.CI(zero_le_half_thresh_carry_n_0),\n .CO({NLW_zero_le_half_thresh_carry__0_CO_UNCONNECTED[3:1],zero_le_half_thresh}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(NLW_zero_le_half_thresh_carry__0_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,1'b0,zero_le_half_thresh_carry__0_i_1_n_0}));\n LUT2 #(\n .INIT(4'h1)) \n zero_le_half_thresh_carry__0_i_1\n (.I0(zero_r_reg__0[8]),\n .I1(zero_r_reg__0[9]),\n .O(zero_le_half_thresh_carry__0_i_1_n_0));\n LUT2 #(\n .INIT(4'h7)) \n zero_le_half_thresh_carry_i_1\n (.I0(zero_r_reg__0[7]),\n .I1(zero_r_reg__0[6]),\n .O(zero_le_half_thresh_carry_i_1_n_0));\n LUT2 #(\n .INIT(4'h7)) \n zero_le_half_thresh_carry_i_2\n (.I0(zero_r_reg__0[5]),\n .I1(zero_r_reg__0[4]),\n .O(zero_le_half_thresh_carry_i_2_n_0));\n LUT2 #(\n .INIT(4'h7)) \n zero_le_half_thresh_carry_i_3\n (.I0(zero_r_reg__0[0]),\n .I1(zero_r_reg__0[1]),\n .O(zero_le_half_thresh_carry_i_3_n_0));\n LUT2 #(\n .INIT(4'h8)) \n zero_le_half_thresh_carry_i_4\n (.I0(zero_r_reg__0[6]),\n .I1(zero_r_reg__0[7]),\n .O(zero_le_half_thresh_carry_i_4_n_0));\n LUT2 #(\n .INIT(4'h8)) \n zero_le_half_thresh_carry_i_5\n (.I0(zero_r_reg__0[4]),\n .I1(zero_r_reg__0[5]),\n .O(zero_le_half_thresh_carry_i_5_n_0));\n LUT2 #(\n .INIT(4'h1)) \n zero_le_half_thresh_carry_i_6\n (.I0(zero_r_reg__0[2]),\n .I1(zero_r_reg__0[3]),\n .O(zero_le_half_thresh_carry_i_6_n_0));\n LUT2 #(\n .INIT(4'h8)) \n zero_le_half_thresh_carry_i_7\n (.I0(zero_r_reg__0[1]),\n .I1(zero_r_reg__0[0]),\n .O(zero_le_half_thresh_carry_i_7_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair436\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\zero_r[0]_i_1 \n (.I0(zero_r_reg__0[0]),\n .O(\\zero_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair436\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\zero_r[1]_i_1 \n (.I0(zero_r_reg__0[1]),\n .I1(zero_r_reg__0[0]),\n .O(p_0_in__1[1]));\n (* SOFT_HLUTNM = \"soft_lutpair433\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\zero_r[2]_i_1 \n (.I0(zero_r_reg__0[2]),\n .I1(zero_r_reg__0[0]),\n .I2(zero_r_reg__0[1]),\n .O(p_0_in__1[2]));\n (* SOFT_HLUTNM = \"soft_lutpair421\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\zero_r[3]_i_1 \n (.I0(zero_r_reg__0[3]),\n .I1(zero_r_reg__0[1]),\n .I2(zero_r_reg__0[0]),\n .I3(zero_r_reg__0[2]),\n .O(p_0_in__1[3]));\n (* SOFT_HLUTNM = \"soft_lutpair421\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\zero_r[4]_i_1 \n (.I0(zero_r_reg__0[4]),\n .I1(zero_r_reg__0[2]),\n .I2(zero_r_reg__0[0]),\n .I3(zero_r_reg__0[1]),\n .I4(zero_r_reg__0[3]),\n .O(p_0_in__1[4]));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n \\zero_r[5]_i_1 \n (.I0(zero_r_reg__0[5]),\n .I1(zero_r_reg__0[3]),\n .I2(zero_r_reg__0[1]),\n .I3(zero_r_reg__0[0]),\n .I4(zero_r_reg__0[2]),\n .I5(zero_r_reg__0[4]),\n .O(p_0_in__1[5]));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n \\zero_r[6]_i_1 \n (.I0(zero_r_reg__0[6]),\n .I1(zero_r_reg__0[4]),\n .I2(zero_r_reg__0[5]),\n .I3(zero_r_reg__0[3]),\n .I4(\\zero_r[6]_i_2_n_0 ),\n .I5(zero_r_reg__0[2]),\n .O(p_0_in__1[6]));\n (* SOFT_HLUTNM = \"soft_lutpair433\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\zero_r[6]_i_2 \n (.I0(zero_r_reg__0[1]),\n .I1(zero_r_reg__0[0]),\n .O(\\zero_r[6]_i_2_n_0 ));\n LUT3 #(\n .INIT(8'h6A)) \n \\zero_r[7]_i_1 \n (.I0(zero_r_reg__0[7]),\n .I1(\\zero_r[9]_i_8_n_0 ),\n .I2(zero_r_reg__0[6]),\n .O(p_0_in__1[7]));\n (* SOFT_HLUTNM = \"soft_lutpair423\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\zero_r[8]_i_1 \n (.I0(zero_r_reg__0[8]),\n .I1(zero_r_reg__0[6]),\n .I2(zero_r_reg__0[7]),\n .I3(\\zero_r[9]_i_8_n_0 ),\n .O(p_0_in__1[8]));\n (* SOFT_HLUTNM = \"soft_lutpair423\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\zero_r[9]_i_3 \n (.I0(zero_r_reg__0[9]),\n .I1(zero_r_reg__0[7]),\n .I2(\\zero_r[9]_i_8_n_0 ),\n .I3(zero_r_reg__0[6]),\n .I4(zero_r_reg__0[8]),\n .O(p_0_in__1[9]));\n LUT4 #(\n .INIT(16'h0002)) \n \\zero_r[9]_i_6 \n (.I0(phy_rddata_en_r1_reg_0),\n .I1(\\rd_victim_sel_r_reg[1]_1 ),\n .I2(\\rd_victim_sel_r_reg[1]_0 ),\n .I3(\\rd_victim_sel_r_reg[2]_0 ),\n .O(\\samps_r_reg[0]_0 ));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\zero_r[9]_i_8 \n (.I0(zero_r_reg__0[2]),\n .I1(zero_r_reg__0[0]),\n .I2(zero_r_reg__0[1]),\n .I3(zero_r_reg__0[3]),\n .I4(zero_r_reg__0[5]),\n .I5(zero_r_reg__0[4]),\n .O(\\zero_r[9]_i_8_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\zero_r_reg[0] \n (.C(CLK),\n .CE(\\rd_victim_sel_r_reg[0]_0 ),\n .D(\\zero_r[0]_i_1_n_0 ),\n .Q(zero_r_reg__0[0]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\zero_r_reg[1] \n (.C(CLK),\n .CE(\\rd_victim_sel_r_reg[0]_0 ),\n .D(p_0_in__1[1]),\n .Q(zero_r_reg__0[1]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\zero_r_reg[2] \n (.C(CLK),\n .CE(\\rd_victim_sel_r_reg[0]_0 ),\n .D(p_0_in__1[2]),\n .Q(zero_r_reg__0[2]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\zero_r_reg[3] \n (.C(CLK),\n .CE(\\rd_victim_sel_r_reg[0]_0 ),\n .D(p_0_in__1[3]),\n .Q(zero_r_reg__0[3]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\zero_r_reg[4] \n (.C(CLK),\n .CE(\\rd_victim_sel_r_reg[0]_0 ),\n .D(p_0_in__1[4]),\n .Q(zero_r_reg__0[4]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\zero_r_reg[5] \n (.C(CLK),\n .CE(\\rd_victim_sel_r_reg[0]_0 ),\n .D(p_0_in__1[5]),\n .Q(zero_r_reg__0[5]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\zero_r_reg[6] \n (.C(CLK),\n .CE(\\rd_victim_sel_r_reg[0]_0 ),\n .D(p_0_in__1[6]),\n .Q(zero_r_reg__0[6]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\zero_r_reg[7] \n (.C(CLK),\n .CE(\\rd_victim_sel_r_reg[0]_0 ),\n .D(p_0_in__1[7]),\n .Q(zero_r_reg__0[7]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\zero_r_reg[8] \n (.C(CLK),\n .CE(\\rd_victim_sel_r_reg[0]_0 ),\n .D(p_0_in__1[8]),\n .Q(zero_r_reg__0[8]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\zero_r_reg[9] \n (.C(CLK),\n .CE(\\rd_victim_sel_r_reg[0]_0 ),\n .D(p_0_in__1[9]),\n .Q(zero_r_reg__0[9]),\n .R(\\sm_r_reg[0]_0 ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_phy_oclkdelay_cal\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_phy_oclkdelay_cal\n (O,\n ocal_last_byte_done_reg,\n complex_oclk_calib_resume,\n ocd_prech_req,\n complex_ocal_num_samples_done_r,\n po_stg23_incdec,\n po_en_stg23,\n phy_rddata_en_1,\n wrlvl_final_mux_reg,\n lim2init_prech_req,\n done_r_reg,\n \\samps_r_reg[9] ,\n oclkdelay_center_calib_start_r_reg,\n D_po_sel_fine_oclk_delay125_out,\n \\po_counter_read_val_reg[8] ,\n \\po_counter_read_val_reg[8]_0 ,\n \\po_counter_read_val_reg[8]_1 ,\n \\resume_wait_r_reg[5] ,\n \\po_counter_read_val_reg[8]_2 ,\n \\po_counter_read_val_reg[8]_3 ,\n \\po_counter_read_val_reg[8]_4 ,\n \\po_counter_read_val_reg[8]_5 ,\n complex_ocal_ref_req,\n stg3_dec2init_val_r_reg,\n stg3_inc2init_val_r_reg,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ,\n \\stg2_target_r_reg[8] ,\n \\stg3_tap_cnt_reg[2] ,\n \\byte_r_reg[1] ,\n \\byte_r_reg[0] ,\n \\stg2_tap_cnt_reg[3] ,\n \\stg2_tap_cnt_reg[0] ,\n \\sm_r_reg[0] ,\n complex_ocal_rd_victim_sel,\n \\zero2fuzz_r_reg[0] ,\n sr_valid_r108_out,\n \\init_state_r_reg[4] ,\n \\init_state_r_reg[2] ,\n \\init_state_r_reg[0] ,\n \\init_state_r_reg[5] ,\n \\init_state_r_reg[5]_0 ,\n \\init_state_r_reg[6] ,\n \\init_state_r_reg[5]_1 ,\n \\init_state_r_reg[4]_0 ,\n ocal_last_byte_done_reg_0,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[1] ,\n \\cal2_state_r_reg[0] ,\n S,\n \\qcntr_r_reg[0] ,\n CLK,\n rstdiv0_sync_r1_reg_rep__20,\n poc_sample_pd,\n rstdiv0_sync_r1_reg_rep__10,\n rstdiv0_sync_r1_reg_rep__9,\n phy_rddata_en,\n Q,\n calib_in_common,\n \\calib_zero_inputs_reg[1] ,\n rstdiv0_sync_r1_reg_rep__25,\n rstdiv0_sync_r1_reg_rep__25_0,\n oclkdelay_calib_start_int_reg,\n prech_done,\n rd_active_r2,\n rstdiv0_sync_r1_reg_rep__24,\n \\sm_r_reg[0]_0 ,\n rd_active_r1,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n ck_addr_cmd_delay_done,\n mpr_rdlvl_done_r_reg,\n \\gen_byte_sel_div1.calib_in_common_reg_0 ,\n \\gen_byte_sel_div1.calib_in_common_reg_1 ,\n \\gen_byte_sel_div1.calib_in_common_reg_2 ,\n \\wl_po_fine_cnt_reg[17] ,\n \\byte_r_reg[0]_0 ,\n D,\n \\po_counter_read_val_reg[2] ,\n \\stg2_tap_cnt_reg[2] ,\n \\wl_po_fine_cnt_reg[3] ,\n \\wl_po_fine_cnt_reg[14] ,\n \\wl_po_fine_cnt_reg[18] ,\n rstdiv0_sync_r1_reg_rep__25_1,\n rstdiv0_sync_r1_reg_rep__25_2,\n \\mmcm_init_trail_reg[0] ,\n \\mmcm_current_reg[0] ,\n rdlvl_stg1_start_reg,\n \\cnt_shift_r_reg[0] ,\n \\init_state_r_reg[0]_0 ,\n prbs_rdlvl_done_reg,\n \\init_state_r_reg[4]_1 ,\n \\init_state_r_reg[0]_1 ,\n wrlvl_final_mux,\n oclkdelay_int_ref_req_reg,\n prech_req_posedge_r_reg,\n cnt_cmd_done_r,\n prbs_rdlvl_done_reg_rep,\n ocal_last_byte_done,\n \\po_stg2_wrcal_cnt_reg[0] ,\n wr_level_done_reg,\n oclkdelay_calib_done_r_reg,\n pi_stg2_rdlvl_cnt,\n \\po_stg2_wrcal_cnt_reg[1] ,\n wrlvl_byte_done,\n \\wl_po_fine_cnt_reg[23] ,\n \\stg3_r_reg[0] ,\n psdone,\n rstdiv0_sync_r1_reg_rep,\n rstdiv0_sync_r1_reg_rep__0,\n rstdiv0_sync_r1_reg_rep__19,\n rstdiv0_sync_r1_reg_rep__11,\n \\po_counter_read_val_reg[5] ,\n \\byte_r_reg[0]_1 ,\n rstdiv0_sync_r1_reg_rep__2,\n oclkdelay_calib_start_int_reg_0,\n pd_out);\n output [3:0]O;\n output ocal_last_byte_done_reg;\n output complex_oclk_calib_resume;\n output ocd_prech_req;\n output complex_ocal_num_samples_done_r;\n output po_stg23_incdec;\n output po_en_stg23;\n output phy_rddata_en_1;\n output wrlvl_final_mux_reg;\n output lim2init_prech_req;\n output done_r_reg;\n output \\samps_r_reg[9] ;\n output oclkdelay_center_calib_start_r_reg;\n output D_po_sel_fine_oclk_delay125_out;\n output \\po_counter_read_val_reg[8] ;\n output \\po_counter_read_val_reg[8]_0 ;\n output \\po_counter_read_val_reg[8]_1 ;\n output \\resume_wait_r_reg[5] ;\n output \\po_counter_read_val_reg[8]_2 ;\n output \\po_counter_read_val_reg[8]_3 ;\n output \\po_counter_read_val_reg[8]_4 ;\n output \\po_counter_read_val_reg[8]_5 ;\n output complex_ocal_ref_req;\n output stg3_dec2init_val_r_reg;\n output stg3_inc2init_val_r_reg;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ;\n output [2:0]\\stg2_target_r_reg[8] ;\n output [2:0]\\stg3_tap_cnt_reg[2] ;\n output \\byte_r_reg[1] ;\n output \\byte_r_reg[0] ;\n output [2:0]\\stg2_tap_cnt_reg[3] ;\n output \\stg2_tap_cnt_reg[0] ;\n output \\sm_r_reg[0] ;\n output [2:0]complex_ocal_rd_victim_sel;\n output [0:0]\\zero2fuzz_r_reg[0] ;\n output sr_valid_r108_out;\n output \\init_state_r_reg[4] ;\n output \\init_state_r_reg[2] ;\n output \\init_state_r_reg[0] ;\n output \\init_state_r_reg[5] ;\n output \\init_state_r_reg[5]_0 ;\n output \\init_state_r_reg[6] ;\n output \\init_state_r_reg[5]_1 ;\n output \\init_state_r_reg[4]_0 ;\n output ocal_last_byte_done_reg_0;\n output \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ;\n output \\gen_byte_sel_div1.byte_sel_cnt_reg[1] ;\n output \\cal2_state_r_reg[0] ;\n output [0:0]S;\n output [0:0]\\qcntr_r_reg[0] ;\n input CLK;\n input rstdiv0_sync_r1_reg_rep__20;\n input poc_sample_pd;\n input rstdiv0_sync_r1_reg_rep__10;\n input rstdiv0_sync_r1_reg_rep__9;\n input phy_rddata_en;\n input [1:0]Q;\n input calib_in_common;\n input [1:0]\\calib_zero_inputs_reg[1] ;\n input rstdiv0_sync_r1_reg_rep__25;\n input rstdiv0_sync_r1_reg_rep__25_0;\n input oclkdelay_calib_start_int_reg;\n input prech_done;\n input rd_active_r2;\n input rstdiv0_sync_r1_reg_rep__24;\n input [0:0]\\sm_r_reg[0]_0 ;\n input rd_active_r1;\n input \\gen_byte_sel_div1.calib_in_common_reg ;\n input ck_addr_cmd_delay_done;\n input mpr_rdlvl_done_r_reg;\n input \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n input \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n input \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n input \\wl_po_fine_cnt_reg[17] ;\n input \\byte_r_reg[0]_0 ;\n input [2:0]D;\n input \\po_counter_read_val_reg[2] ;\n input \\stg2_tap_cnt_reg[2] ;\n input \\wl_po_fine_cnt_reg[3] ;\n input [1:0]\\wl_po_fine_cnt_reg[14] ;\n input \\wl_po_fine_cnt_reg[18] ;\n input rstdiv0_sync_r1_reg_rep__25_1;\n input rstdiv0_sync_r1_reg_rep__25_2;\n input \\mmcm_init_trail_reg[0] ;\n input \\mmcm_current_reg[0] ;\n input rdlvl_stg1_start_reg;\n input \\cnt_shift_r_reg[0] ;\n input \\init_state_r_reg[0]_0 ;\n input prbs_rdlvl_done_reg;\n input [2:0]\\init_state_r_reg[4]_1 ;\n input \\init_state_r_reg[0]_1 ;\n input wrlvl_final_mux;\n input oclkdelay_int_ref_req_reg;\n input prech_req_posedge_r_reg;\n input cnt_cmd_done_r;\n input prbs_rdlvl_done_reg_rep;\n input ocal_last_byte_done;\n input \\po_stg2_wrcal_cnt_reg[0] ;\n input wr_level_done_reg;\n input oclkdelay_calib_done_r_reg;\n input [1:0]pi_stg2_rdlvl_cnt;\n input \\po_stg2_wrcal_cnt_reg[1] ;\n input wrlvl_byte_done;\n input [7:0]\\wl_po_fine_cnt_reg[23] ;\n input \\stg3_r_reg[0] ;\n input psdone;\n input rstdiv0_sync_r1_reg_rep;\n input rstdiv0_sync_r1_reg_rep__0;\n input [0:0]rstdiv0_sync_r1_reg_rep__19;\n input rstdiv0_sync_r1_reg_rep__11;\n input [5:0]\\po_counter_read_val_reg[5] ;\n input [63:0]\\byte_r_reg[0]_1 ;\n input rstdiv0_sync_r1_reg_rep__2;\n input oclkdelay_calib_start_int_reg_0;\n input pd_out;\n\n wire CLK;\n wire [2:0]D;\n wire D_po_sel_fine_oclk_delay125_out;\n wire [3:0]O;\n wire [1:0]Q;\n wire [0:0]S;\n wire [1:0]agg_samp_r;\n wire \\byte_r_reg[0] ;\n wire \\byte_r_reg[0]_0 ;\n wire [63:0]\\byte_r_reg[0]_1 ;\n wire \\byte_r_reg[1] ;\n wire \\cal2_state_r_reg[0] ;\n wire calib_in_common;\n wire [1:0]\\calib_zero_inputs_reg[1] ;\n wire ck_addr_cmd_delay_done;\n wire cnt_cmd_done_r;\n wire \\cnt_shift_r_reg[0] ;\n wire complex_ocal_num_samples_done_r;\n wire [2:0]complex_ocal_rd_victim_sel;\n wire complex_ocal_ref_req;\n wire complex_oclk_calib_resume;\n wire dec_po_ns;\n wire done_r_reg;\n wire f2z_ns5_out;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[1] ;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n wire inc_po_ns;\n wire \\init_state_r_reg[0] ;\n wire \\init_state_r_reg[0]_0 ;\n wire \\init_state_r_reg[0]_1 ;\n wire \\init_state_r_reg[2] ;\n wire \\init_state_r_reg[4] ;\n wire \\init_state_r_reg[4]_0 ;\n wire [2:0]\\init_state_r_reg[4]_1 ;\n wire \\init_state_r_reg[5] ;\n wire \\init_state_r_reg[5]_0 ;\n wire \\init_state_r_reg[5]_1 ;\n wire \\init_state_r_reg[6] ;\n wire lim2init_prech_req;\n wire lim2poc_ktap_right;\n wire lim2poc_rdy;\n wire lim2stg2_dec;\n wire lim2stg2_inc;\n wire lim2stg3_dec;\n wire lim2stg3_inc;\n wire lim_start;\n wire lim_start_r;\n wire \\mmcm_current_reg[0] ;\n wire \\mmcm_init_trail_reg[0] ;\n wire mpr_rdlvl_done_r_reg;\n wire [1:0]ninety_offsets;\n wire o2f_ns1_out;\n wire ocal_last_byte_done;\n wire ocal_last_byte_done_reg;\n wire ocal_last_byte_done_reg_0;\n wire ocd_cntlr2stg2_dec_r;\n wire ocd_prech_req;\n wire oclk_center_write_resume;\n wire oclkdelay_calib_done_r_reg;\n wire oclkdelay_calib_start_int_reg;\n wire oclkdelay_calib_start_int_reg_0;\n wire oclkdelay_center_calib_start_r_reg;\n wire oclkdelay_int_ref_req_reg;\n wire pd_out;\n wire phy_rddata_en;\n wire phy_rddata_en_1;\n wire [1:0]pi_stg2_rdlvl_cnt;\n wire \\po_counter_read_val_reg[2] ;\n wire [5:0]\\po_counter_read_val_reg[5] ;\n wire \\po_counter_read_val_reg[8] ;\n wire \\po_counter_read_val_reg[8]_0 ;\n wire \\po_counter_read_val_reg[8]_1 ;\n wire \\po_counter_read_val_reg[8]_2 ;\n wire \\po_counter_read_val_reg[8]_3 ;\n wire \\po_counter_read_val_reg[8]_4 ;\n wire \\po_counter_read_val_reg[8]_5 ;\n wire po_en_stg23;\n wire po_rdy;\n wire po_stg23_incdec;\n wire \\po_stg2_wrcal_cnt_reg[0] ;\n wire \\po_stg2_wrcal_cnt_reg[1] ;\n wire poc_sample_pd;\n wire prbs_rdlvl_done_reg;\n wire prbs_rdlvl_done_reg_rep;\n wire prech_done;\n wire prech_req_posedge_r_reg;\n wire [1:0]prev_samp_r;\n wire prev_samp_valid_r;\n wire psdone;\n wire [0:0]\\qcntr_r_reg[0] ;\n wire rd_active_r1;\n wire rd_active_r2;\n wire rdlvl_stg1_start_reg;\n wire reset_scan;\n wire \\resume_wait_r_reg[5] ;\n wire [5:0]rise_lead_right;\n wire [5:0]rise_trail_right;\n wire rstdiv0_sync_r1_reg_rep;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__10;\n wire rstdiv0_sync_r1_reg_rep__11;\n wire [0:0]rstdiv0_sync_r1_reg_rep__19;\n wire rstdiv0_sync_r1_reg_rep__2;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__24;\n wire rstdiv0_sync_r1_reg_rep__25;\n wire rstdiv0_sync_r1_reg_rep__25_0;\n wire rstdiv0_sync_r1_reg_rep__25_1;\n wire rstdiv0_sync_r1_reg_rep__25_2;\n wire rstdiv0_sync_r1_reg_rep__9;\n wire samp_done;\n wire samp_done_ns8_out;\n wire \\samps_r_reg[9] ;\n wire scan_right;\n wire scanning_right;\n wire setup_po;\n wire [1:1]sm_r;\n wire \\sm_r_reg[0] ;\n wire [0:0]\\sm_r_reg[0]_0 ;\n wire sr_valid_r108_out;\n wire \\stg2_tap_cnt_reg[0] ;\n wire \\stg2_tap_cnt_reg[2] ;\n wire [2:0]\\stg2_tap_cnt_reg[3] ;\n wire [2:0]\\stg2_target_r_reg[8] ;\n wire stg3_dec2init_val_r_reg;\n wire stg3_inc2init_val_r_reg;\n wire \\stg3_r_reg[0] ;\n wire [2:0]\\stg3_tap_cnt_reg[2] ;\n wire u_ocd_cntlr_n_10;\n wire u_ocd_cntlr_n_11;\n wire u_ocd_cntlr_n_12;\n wire u_ocd_cntlr_n_13;\n wire u_ocd_cntlr_n_14;\n wire u_ocd_cntlr_n_15;\n wire u_ocd_cntlr_n_16;\n wire u_ocd_cntlr_n_17;\n wire u_ocd_cntlr_n_18;\n wire u_ocd_cntlr_n_19;\n wire u_ocd_cntlr_n_20;\n wire u_ocd_cntlr_n_9;\n wire u_ocd_data_n_0;\n wire u_ocd_data_n_1;\n wire u_ocd_data_n_2;\n wire u_ocd_edge_n_1;\n wire u_ocd_edge_n_10;\n wire u_ocd_edge_n_2;\n wire u_ocd_edge_n_3;\n wire u_ocd_edge_n_7;\n wire u_ocd_lim_n_19;\n wire u_ocd_lim_n_20;\n wire u_ocd_lim_n_21;\n wire u_ocd_lim_n_22;\n wire u_ocd_lim_n_23;\n wire u_ocd_lim_n_24;\n wire u_ocd_lim_n_25;\n wire u_ocd_lim_n_26;\n wire u_ocd_lim_n_27;\n wire u_ocd_lim_n_28;\n wire u_ocd_lim_n_29;\n wire u_ocd_lim_n_30;\n wire u_ocd_lim_n_31;\n wire u_ocd_lim_n_32;\n wire u_ocd_lim_n_9;\n wire u_ocd_mux_n_11;\n wire u_ocd_po_cntlr_n_11;\n wire u_ocd_po_cntlr_n_12;\n wire u_ocd_po_cntlr_n_13;\n wire u_ocd_po_cntlr_n_14;\n wire u_ocd_po_cntlr_n_15;\n wire u_ocd_po_cntlr_n_16;\n wire u_ocd_po_cntlr_n_17;\n wire u_ocd_po_cntlr_n_20;\n wire u_ocd_po_cntlr_n_22;\n wire u_ocd_po_cntlr_n_23;\n wire u_ocd_po_cntlr_n_27;\n wire u_ocd_po_cntlr_n_28;\n wire u_ocd_po_cntlr_n_29;\n wire u_ocd_po_cntlr_n_30;\n wire u_ocd_po_cntlr_n_31;\n wire u_ocd_po_cntlr_n_32;\n wire u_ocd_po_cntlr_n_33;\n wire u_ocd_po_cntlr_n_34;\n wire u_ocd_po_cntlr_n_35;\n wire u_ocd_po_cntlr_n_48;\n wire u_ocd_po_cntlr_n_49;\n wire u_ocd_po_cntlr_n_50;\n wire u_ocd_po_cntlr_n_51;\n wire u_ocd_po_cntlr_n_7;\n wire u_ocd_samp_n_10;\n wire u_ocd_samp_n_14;\n wire u_ocd_samp_n_16;\n wire u_ocd_samp_n_20;\n wire u_ocd_samp_n_21;\n wire u_ocd_samp_n_3;\n wire u_ocd_samp_n_4;\n wire u_ocd_samp_n_5;\n wire u_ocd_samp_n_6;\n wire u_ocd_samp_n_7;\n wire u_poc_n_0;\n wire u_poc_n_1;\n wire u_poc_n_16;\n wire u_poc_n_17;\n wire u_poc_n_2;\n wire use_noise_window;\n wire [1:0]\\wl_po_fine_cnt_reg[14] ;\n wire \\wl_po_fine_cnt_reg[17] ;\n wire \\wl_po_fine_cnt_reg[18] ;\n wire [7:0]\\wl_po_fine_cnt_reg[23] ;\n wire \\wl_po_fine_cnt_reg[3] ;\n wire wr_level_done_reg;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ;\n wire wrlvl_byte_done;\n wire wrlvl_final_mux;\n wire wrlvl_final_mux_reg;\n wire [5:1]zero2fuzz_r0;\n wire [0:0]\\zero2fuzz_r_reg[0] ;\n\n ddr3_ifmig_7series_v4_0_ddr_phy_ocd_cntlr u_ocd_cntlr\n (.CLK(CLK),\n .D({u_ocd_cntlr_n_9,u_ocd_cntlr_n_10,u_ocd_cntlr_n_11,u_ocd_cntlr_n_12,u_ocd_cntlr_n_13}),\n .\\byte_r_reg[0]_0 (\\byte_r_reg[0] ),\n .\\byte_r_reg[1]_0 (\\byte_r_reg[1] ),\n .\\cal2_state_r_reg[0] (\\cal2_state_r_reg[0] ),\n .cnt_cmd_done_r(cnt_cmd_done_r),\n .\\cnt_shift_r_reg[0] (\\cnt_shift_r_reg[0] ),\n .complex_ocal_ref_req(complex_ocal_ref_req),\n .\\data_cnt_r_reg[7] (u_ocd_samp_n_3),\n .done_r_reg(u_ocd_cntlr_n_18),\n .done_r_reg_0(done_r_reg),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[0] (\\gen_byte_sel_div1.byte_sel_cnt_reg[0] ),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[1] (\\gen_byte_sel_div1.byte_sel_cnt_reg[1] ),\n .\\init_state_r_reg[0] (\\init_state_r_reg[0]_1 ),\n .\\init_state_r_reg[2] (\\init_state_r_reg[2] ),\n .\\init_state_r_reg[2]_0 (\\init_state_r_reg[4]_1 [1:0]),\n .\\init_state_r_reg[5] (\\init_state_r_reg[5] ),\n .lim_start(lim_start),\n .lim_start_r(lim_start_r),\n .ocal_last_byte_done(ocal_last_byte_done),\n .ocal_last_byte_done_reg(ocal_last_byte_done_reg_0),\n .ocd_cntlr2stg2_dec_r(ocd_cntlr2stg2_dec_r),\n .oclk_calib_resume_r_reg(complex_oclk_calib_resume),\n .oclkdelay_calib_done_r_reg_0(oclkdelay_calib_done_r_reg),\n .oclkdelay_calib_start_int_reg(oclkdelay_calib_start_int_reg),\n .oclkdelay_calib_start_int_reg_0(oclkdelay_calib_start_int_reg_0),\n .oclkdelay_center_calib_done_r_reg(ocal_last_byte_done_reg),\n .phy_rddata_en(phy_rddata_en),\n .pi_stg2_rdlvl_cnt(pi_stg2_rdlvl_cnt),\n .\\po_counter_read_val_reg[2] (\\po_counter_read_val_reg[2] ),\n .po_rdy(po_rdy),\n .\\po_stg2_wrcal_cnt_reg[0] (\\po_stg2_wrcal_cnt_reg[0] ),\n .\\po_stg2_wrcal_cnt_reg[1] (\\po_stg2_wrcal_cnt_reg[1] ),\n .prbs_rdlvl_done_reg(prbs_rdlvl_done_reg),\n .prech_done(prech_done),\n .prech_req_posedge_r_reg(prech_req_posedge_r_reg),\n .prech_req_r_reg(ocd_prech_req),\n .prech_req_r_reg_0(lim2init_prech_req),\n .rd_active_r1(rd_active_r1),\n .rd_active_r1_reg(phy_rddata_en_1),\n .\\rd_victim_sel_r_reg[0] (u_ocd_cntlr_n_19),\n .rdlvl_stg1_start_reg(rdlvl_stg1_start_reg),\n .reset_scan(reset_scan),\n .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10),\n .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),\n .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25_0),\n .rstdiv0_sync_r1_reg_rep__25_0(rstdiv0_sync_r1_reg_rep__25),\n .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9),\n .\\simp_stg3_final_r_reg[10] (u_ocd_po_cntlr_n_30),\n .\\simp_stg3_final_r_reg[11] (u_ocd_cntlr_n_15),\n .\\simp_stg3_final_r_reg[12] (u_ocd_po_cntlr_n_33),\n .\\simp_stg3_final_r_reg[16] (u_ocd_po_cntlr_n_50),\n .\\simp_stg3_final_r_reg[17] (u_ocd_cntlr_n_17),\n .\\simp_stg3_final_r_reg[17]_0 (u_ocd_po_cntlr_n_28),\n .\\simp_stg3_final_r_reg[19] (u_ocd_po_cntlr_n_32),\n .\\simp_stg3_final_r_reg[23] (u_ocd_cntlr_n_14),\n .\\simp_stg3_final_r_reg[2] (u_ocd_po_cntlr_n_51),\n .\\simp_stg3_final_r_reg[5] (u_ocd_cntlr_n_16),\n .\\simp_stg3_final_r_reg[8] (u_ocd_po_cntlr_n_31),\n .sr_valid_r108_out(sr_valid_r108_out),\n .\\stg3_init_val_reg[3] (u_ocd_cntlr_n_20),\n .wr_level_done_reg(wr_level_done_reg),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] (\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ),\n .wrlvl_byte_done(wrlvl_byte_done),\n .wrlvl_final_mux_reg(wrlvl_final_mux_reg));\n ddr3_ifmig_7series_v4_0_ddr_phy_ocd_data u_ocd_data\n (.CLK(CLK),\n .E(u_ocd_data_n_0),\n .agg_samp_r(agg_samp_r),\n .\\byte_r_reg[0] (\\byte_r_reg[0]_1 ),\n .\\rd_victim_sel_r_reg[0] (u_ocd_samp_n_7),\n .\\zero_r_reg[9] (u_ocd_data_n_1),\n .\\zero_r_reg[9]_0 (u_ocd_data_n_2));\n ddr3_ifmig_7series_v4_0_ddr_phy_ocd_edge u_ocd_edge\n (.CLK(CLK),\n .D({zero2fuzz_r0,\\zero2fuzz_r_reg[0] }),\n .E(u_ocd_samp_n_16),\n .Q({u_ocd_po_cntlr_n_11,u_ocd_po_cntlr_n_12,u_ocd_po_cntlr_n_13,u_ocd_po_cntlr_n_14,u_ocd_po_cntlr_n_15,u_ocd_po_cntlr_n_16}),\n .dec_po_ns(dec_po_ns),\n .f2o_r_reg_0(u_ocd_edge_n_3),\n .inc_po_ns(inc_po_ns),\n .\\ninety_offsets_final_r_reg[0] (u_ocd_edge_n_2),\n .\\ninety_offsets_final_r_reg[0]_0 (u_ocd_edge_n_10),\n .\\ninety_offsets_final_r_reg[1] (u_ocd_edge_n_7),\n .o2f_r_reg_0(u_ocd_edge_n_1),\n .ocd_ktap_left_r_reg(u_ocd_po_cntlr_n_7),\n .prev_samp_r(prev_samp_r),\n .prev_samp_valid_r(prev_samp_valid_r),\n .rd_active_r1(rd_active_r1),\n .rd_active_r1_reg(u_ocd_samp_n_5),\n .rd_active_r1_reg_0(u_ocd_samp_n_6),\n .reset_scan(reset_scan),\n .reset_scan_r_reg(u_ocd_samp_n_14),\n .samp_done(samp_done),\n .samp_done_r_reg(u_ocd_samp_n_4),\n .\\samp_result_r_reg[0] (u_ocd_samp_n_20),\n .\\samp_result_r_reg[1] (u_ocd_samp_n_21),\n .scan_right(scan_right),\n .scanning_right(scanning_right),\n .scanning_right_r_reg(u_ocd_po_cntlr_n_22),\n .scanning_right_r_reg_0(u_ocd_po_cntlr_n_23),\n .\\stg3_left_lim_reg[5] ({u_ocd_lim_n_20,u_ocd_lim_n_21,u_ocd_lim_n_22,u_ocd_lim_n_23,u_ocd_lim_n_24,u_ocd_lim_n_25}),\n .\\stg3_right_lim_reg[5] ({u_ocd_lim_n_27,u_ocd_lim_n_28,u_ocd_lim_n_29,u_ocd_lim_n_30,u_ocd_lim_n_31,u_ocd_lim_n_32}));\n ddr3_ifmig_7series_v4_0_ddr_phy_ocd_lim u_ocd_lim\n (.CLK(CLK),\n .D(D),\n .Q(rise_trail_right),\n .\\byte_r_reg[0] (\\byte_r_reg[0]_0 ),\n .cnt_cmd_done_r(cnt_cmd_done_r),\n .done_r_reg_0(done_r_reg),\n .done_r_reg_1(u_poc_n_0),\n .\\init_state_r_reg[4] (\\init_state_r_reg[4]_0 ),\n .\\init_state_r_reg[5] (\\init_state_r_reg[5]_1 ),\n .\\init_state_r_reg[6] (\\init_state_r_reg[6] ),\n .lim2poc_ktap_right(lim2poc_ktap_right),\n .lim2poc_rdy(lim2poc_rdy),\n .lim2stg2_dec(lim2stg2_dec),\n .lim2stg2_inc(lim2stg2_inc),\n .lim2stg3_dec(lim2stg3_dec),\n .lim2stg3_inc(lim2stg3_inc),\n .lim_start(lim_start),\n .lim_start_r(lim_start_r),\n .lim_start_r_reg_0(u_ocd_cntlr_n_18),\n .\\mmcm_current_reg[0]_0 (\\mmcm_current_reg[0] ),\n .\\mmcm_init_trail_reg[0]_0 (\\mmcm_init_trail_reg[0] ),\n .o2f_r_reg(u_ocd_edge_n_1),\n .ocd_prech_req_r_reg(ocd_prech_req),\n .oclk_center_write_resume(oclk_center_write_resume),\n .oclkdelay_calib_done_r_reg({u_ocd_cntlr_n_9,u_ocd_cntlr_n_10,u_ocd_po_cntlr_n_29,u_ocd_cntlr_n_11,u_ocd_cntlr_n_12,u_ocd_cntlr_n_13}),\n .oclkdelay_center_calib_start_r_reg(u_ocd_lim_n_26),\n .oclkdelay_center_calib_start_r_reg_0({u_ocd_lim_n_27,u_ocd_lim_n_28,u_ocd_lim_n_29,u_ocd_lim_n_30,u_ocd_lim_n_31,u_ocd_lim_n_32}),\n .po_rdy(po_rdy),\n .po_stg23_sel_r_reg(u_ocd_lim_n_9),\n .\\po_wait_r_reg[0] (u_ocd_mux_n_11),\n .prbs_rdlvl_done_reg_rep(prbs_rdlvl_done_reg_rep),\n .prech_done(prech_done),\n .prech_req_r_reg_0(lim2init_prech_req),\n .\\rise_lead_r_reg[5] (rise_lead_right),\n .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10),\n .rstdiv0_sync_r1_reg_rep__11(rstdiv0_sync_r1_reg_rep__11),\n .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25),\n .rstdiv0_sync_r1_reg_rep__25_0(rstdiv0_sync_r1_reg_rep__25_1),\n .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9),\n .scan_right(scan_right),\n .scanning_right(scanning_right),\n .scanning_right_r_reg(u_ocd_lim_n_19),\n .scanning_right_r_reg_0({u_ocd_lim_n_20,u_ocd_lim_n_21,u_ocd_lim_n_22,u_ocd_lim_n_23,u_ocd_lim_n_24,u_ocd_lim_n_25}),\n .\\sm_r_reg[2] (u_ocd_po_cntlr_n_20),\n .\\stg2_tap_cnt_reg[0]_0 (\\stg2_tap_cnt_reg[0] ),\n .\\stg2_tap_cnt_reg[2]_0 (\\stg2_tap_cnt_reg[2] ),\n .\\stg2_tap_cnt_reg[3]_0 (\\stg2_tap_cnt_reg[3] ),\n .stg3_dec2init_val_r_reg_0(stg3_dec2init_val_r_reg),\n .stg3_inc2init_val_r_reg_0(stg3_inc2init_val_r_reg),\n .\\stg3_r_reg[5] ({u_ocd_po_cntlr_n_11,u_ocd_po_cntlr_n_12,u_ocd_po_cntlr_n_13,u_ocd_po_cntlr_n_14,u_ocd_po_cntlr_n_15,u_ocd_po_cntlr_n_16}),\n .\\stg3_tap_cnt_reg[2]_0 (\\stg3_tap_cnt_reg[2] ),\n .\\wl_po_fine_cnt_reg[14] (\\wl_po_fine_cnt_reg[14] ),\n .\\wl_po_fine_cnt_reg[17] (\\wl_po_fine_cnt_reg[17] ),\n .\\wl_po_fine_cnt_reg[18] (\\wl_po_fine_cnt_reg[18] ),\n .\\wl_po_fine_cnt_reg[3] (\\wl_po_fine_cnt_reg[3] ));\n ddr3_ifmig_7series_v4_0_ddr_phy_ocd_mux u_ocd_mux\n (.CLK(CLK),\n .D_po_sel_fine_oclk_delay125_out(D_po_sel_fine_oclk_delay125_out),\n .Q(Q),\n .calib_in_common(calib_in_common),\n .\\calib_zero_inputs_reg[1] (\\calib_zero_inputs_reg[1] ),\n .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\gen_byte_sel_div1.calib_in_common_reg ),\n .\\gen_byte_sel_div1.calib_in_common_reg_0 (\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_1 (\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_2 (\\gen_byte_sel_div1.calib_in_common_reg_2 ),\n .mpr_rdlvl_done_r_reg(mpr_rdlvl_done_r_reg),\n .oclkdelay_calib_done_r_reg(wrlvl_final_mux_reg),\n .\\po_counter_read_val_reg[8] (\\po_counter_read_val_reg[8] ),\n .\\po_counter_read_val_reg[8]_0 (\\po_counter_read_val_reg[8]_0 ),\n .\\po_counter_read_val_reg[8]_1 (\\po_counter_read_val_reg[8]_1 ),\n .\\po_counter_read_val_reg[8]_2 (\\po_counter_read_val_reg[8]_2 ),\n .\\po_counter_read_val_reg[8]_3 (\\po_counter_read_val_reg[8]_3 ),\n .\\po_counter_read_val_reg[8]_4 (\\po_counter_read_val_reg[8]_4 ),\n .\\po_counter_read_val_reg[8]_5 (\\po_counter_read_val_reg[8]_5 ),\n .po_rdy(po_rdy),\n .po_stg23_incdec(po_stg23_incdec),\n .po_stg23_sel_r_reg_0(u_ocd_mux_n_11),\n .\\po_wait_r_reg[3]_0 (po_en_stg23),\n .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10),\n .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),\n .setup_po(setup_po),\n .stg2_dec_req_r_reg(u_ocd_po_cntlr_n_27),\n .stg3_dec_req_r_reg(u_ocd_lim_n_9),\n .stg3_inc_req_r_reg(u_ocd_po_cntlr_n_17));\n ddr3_ifmig_7series_v4_0_ddr_phy_ocd_po_cntlr u_ocd_po_cntlr\n (.CLK(CLK),\n .D({zero2fuzz_r0,\\zero2fuzz_r_reg[0] }),\n .E(\\resume_wait_r_reg[5] ),\n .O(O),\n .Q({u_ocd_po_cntlr_n_11,u_ocd_po_cntlr_n_12,u_ocd_po_cntlr_n_13,u_ocd_po_cntlr_n_14,u_ocd_po_cntlr_n_15,u_ocd_po_cntlr_n_16}),\n .S(S),\n .\\byte_r_reg[0] (\\byte_r_reg[0]_0 ),\n .\\byte_r_reg[0]_0 (\\byte_r_reg[0] ),\n .\\byte_r_reg[0]_1 (u_ocd_cntlr_n_14),\n .\\byte_r_reg[0]_2 (u_ocd_cntlr_n_15),\n .\\byte_r_reg[0]_3 (u_ocd_cntlr_n_16),\n .\\byte_r_reg[1] (\\byte_r_reg[1] ),\n .\\byte_r_reg[1]_0 (u_ocd_cntlr_n_17),\n .complex_ocal_num_samples_done_r(complex_ocal_num_samples_done_r),\n .dec_po_ns(dec_po_ns),\n .done_r_reg(u_poc_n_0),\n .edge_aligned_r_reg(u_ocd_po_cntlr_n_49),\n .edge_aligned_r_reg_0(u_poc_n_1),\n .f2o_r_reg(u_ocd_edge_n_7),\n .f2o_r_reg_0(u_ocd_edge_n_10),\n .f2z_ns5_out(f2z_ns5_out),\n .f2z_r_reg(u_ocd_po_cntlr_n_23),\n .f2z_r_reg_0(u_ocd_edge_n_2),\n .inc_po_ns(inc_po_ns),\n .\\init_state_r_reg[0] (\\init_state_r_reg[0] ),\n .lim2poc_ktap_right(lim2poc_ktap_right),\n .lim2poc_rdy(lim2poc_rdy),\n .lim2stg2_dec(lim2stg2_dec),\n .lim2stg2_inc(lim2stg2_inc),\n .lim2stg3_dec(lim2stg3_dec),\n .lim2stg3_inc(lim2stg3_inc),\n .ninety_offsets(ninety_offsets),\n .o2f_ns1_out(o2f_ns1_out),\n .o2f_r_reg(u_ocd_po_cntlr_n_22),\n .o2f_r_reg_0(u_ocd_edge_n_1),\n .ocal_last_byte_done_reg(ocal_last_byte_done_reg),\n .ocd_cntlr2stg2_dec_r(ocd_cntlr2stg2_dec_r),\n .oclk_center_write_resume(oclk_center_write_resume),\n .oclkdelay_calib_done_r_reg(u_ocd_cntlr_n_20),\n .oclkdelay_calib_done_r_reg_0(wrlvl_final_mux_reg),\n .oclkdelay_center_calib_start_r_reg_0(oclkdelay_center_calib_start_r_reg),\n .oclkdelay_int_ref_req_reg(oclkdelay_int_ref_req_reg),\n .\\po_counter_read_val_reg[5] (\\po_counter_read_val_reg[5] ),\n .po_rdy(po_rdy),\n .po_stg23_incdec(po_stg23_incdec),\n .po_stg23_incdec_r_reg(u_ocd_po_cntlr_n_17),\n .po_stg23_incdec_r_reg_0(u_ocd_po_cntlr_n_27),\n .poc_backup_r_reg_0(u_ocd_po_cntlr_n_48),\n .poc_backup_r_reg_1(u_poc_n_2),\n .prech_req_posedge_r_reg(prech_req_posedge_r_reg),\n .rd_active_r2(rd_active_r2),\n .reset_scan(reset_scan),\n .\\rise_trail_r_reg[5] (u_ocd_po_cntlr_n_34),\n .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),\n .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25),\n .rstdiv0_sync_r1_reg_rep__25_0(rstdiv0_sync_r1_reg_rep__25_2),\n .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9),\n .\\run_ends_r_reg[0] (u_poc_n_16),\n .\\run_ends_r_reg[1] (u_ocd_po_cntlr_n_35),\n .\\run_ends_r_reg[1]_0 (u_poc_n_17),\n .samp_done(samp_done),\n .samp_done_ns8_out(samp_done_ns8_out),\n .samp_done_r_reg(u_ocd_samp_n_10),\n .scan_right_r_reg(u_ocd_lim_n_19),\n .scanning_right(scanning_right),\n .scanning_right_r_reg_0(u_ocd_lim_n_26),\n .setup_po(setup_po),\n .\\sm_r_reg[0]_0 (\\sm_r_reg[0] ),\n .\\sm_r_reg[0]_1 (\\samps_r_reg[9] ),\n .\\sm_r_reg[3]_0 (u_ocd_po_cntlr_n_7),\n .\\stg2_r_reg[0]_0 (sm_r),\n .\\stg2_target_r_reg[8]_0 (\\stg2_target_r_reg[8] ),\n .\\stg3_init_val_reg[0] (u_ocd_po_cntlr_n_33),\n .\\stg3_init_val_reg[1] (u_ocd_po_cntlr_n_32),\n .\\stg3_init_val_reg[2] (u_ocd_po_cntlr_n_31),\n .\\stg3_init_val_reg[2]_0 (u_ocd_po_cntlr_n_51),\n .\\stg3_init_val_reg[3] (u_ocd_po_cntlr_n_29),\n .\\stg3_init_val_reg[4] (u_ocd_po_cntlr_n_30),\n .\\stg3_init_val_reg[4]_0 (u_ocd_po_cntlr_n_50),\n .\\stg3_init_val_reg[5] (u_ocd_po_cntlr_n_28),\n .\\stg3_r_reg[0]_0 (\\stg3_r_reg[0] ),\n .\\two_r_reg[1]_0 (u_ocd_po_cntlr_n_20),\n .use_noise_window(use_noise_window),\n .\\wl_po_fine_cnt_reg[14] (\\wl_po_fine_cnt_reg[14] ),\n .\\wl_po_fine_cnt_reg[17] (\\wl_po_fine_cnt_reg[17] ),\n .\\wl_po_fine_cnt_reg[18] (\\wl_po_fine_cnt_reg[18] ),\n .\\wl_po_fine_cnt_reg[23] (\\wl_po_fine_cnt_reg[23] ),\n .\\wl_po_fine_cnt_reg[3] (\\wl_po_fine_cnt_reg[3] ),\n .wrlvl_final_mux(wrlvl_final_mux));\n ddr3_ifmig_7series_v4_0_ddr_phy_ocd_samp u_ocd_samp\n (.CLK(CLK),\n .D({u_ocd_samp_n_5,u_ocd_samp_n_6}),\n .E(u_ocd_samp_n_16),\n .agg_samp_r(agg_samp_r),\n .\\data_bytes_r_reg[24] (u_ocd_data_n_1),\n .\\data_bytes_r_reg[32] (u_ocd_data_n_2),\n .f2o_r_reg(u_ocd_edge_n_3),\n .f2z_ns5_out(f2z_ns5_out),\n .\\init_state_r_reg[0] (\\init_state_r_reg[0]_0 ),\n .\\init_state_r_reg[4] (\\init_state_r_reg[4] ),\n .\\init_state_r_reg[4]_0 (\\init_state_r_reg[4]_1 [2]),\n .\\init_state_r_reg[5] (\\init_state_r_reg[5]_0 ),\n .o2f_ns1_out(o2f_ns1_out),\n .ocd_prech_req_r_reg(ocd_prech_req),\n .oclk_calib_resume_level_reg(complex_oclk_calib_resume),\n .oclk_calib_resume_r_reg_0(u_ocd_samp_n_3),\n .\\oneeighty2fuzz_r_reg[5] (u_ocd_samp_n_14),\n .phy_rddata_en_r1_reg(phy_rddata_en_1),\n .phy_rddata_en_r1_reg_0(u_ocd_cntlr_n_19),\n .prbs_rdlvl_done_reg(prbs_rdlvl_done_reg),\n .prbs_rdlvl_done_reg_rep(prbs_rdlvl_done_reg_rep),\n .prech_req_r_reg(lim2init_prech_req),\n .prev_samp_r(prev_samp_r),\n .\\prev_samp_r_reg[0] (u_ocd_samp_n_20),\n .\\prev_samp_r_reg[1] (u_ocd_samp_n_21),\n .prev_samp_valid_r(prev_samp_valid_r),\n .prev_samp_valid_r_reg(u_ocd_samp_n_4),\n .rd_active_r1(rd_active_r1),\n .rd_active_r2(rd_active_r2),\n .\\rd_victim_sel_r_reg[0]_0 (u_ocd_data_n_0),\n .\\rd_victim_sel_r_reg[1]_0 (complex_ocal_rd_victim_sel[1]),\n .\\rd_victim_sel_r_reg[1]_1 (complex_ocal_rd_victim_sel[0]),\n .\\rd_victim_sel_r_reg[2]_0 (complex_ocal_rd_victim_sel[2]),\n .reset_scan(reset_scan),\n .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),\n .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25),\n .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9),\n .samp_done(samp_done),\n .samp_done_ns8_out(samp_done_ns8_out),\n .\\samps_r_reg[0]_0 (u_ocd_samp_n_7),\n .\\samps_r_reg[9]_0 (\\samps_r_reg[9] ),\n .scanning_right(scanning_right),\n .scanning_right_r_reg(u_ocd_lim_n_26),\n .\\sm_r_reg[0]_0 (\\sm_r_reg[0]_0 ),\n .\\sm_r_reg[1] (sm_r),\n .\\stg3_r_reg[1] (u_ocd_samp_n_10));\n ddr3_ifmig_7series_v4_0_poc_top u_poc\n (.CLK(CLK),\n .Q(rise_trail_right),\n .detect_done_r_reg(u_poc_n_0),\n .\\mmcm_init_lead_reg[5] (rise_lead_right),\n .ninety_offsets(ninety_offsets),\n .ocd_edge_detect_rdy_r_reg(u_ocd_po_cntlr_n_35),\n .ocd_ktap_left_r_reg(u_ocd_po_cntlr_n_7),\n .ocd_ktap_left_r_reg_0(u_ocd_po_cntlr_n_49),\n .ocd_ktap_right_r_reg(u_ocd_po_cntlr_n_34),\n .pd_out(pd_out),\n .poc_backup_r_reg(u_poc_n_2),\n .poc_sample_pd(poc_sample_pd),\n .\\prev_r_reg[0] (u_poc_n_16),\n .\\prev_r_reg[0]_0 (u_poc_n_17),\n .psdone(psdone),\n .\\qcntr_r_reg[0] (\\qcntr_r_reg[0] ),\n .rstdiv0_sync_r1_reg_rep(rstdiv0_sync_r1_reg_rep),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .\\run_ends_r_reg[1] (u_ocd_po_cntlr_n_48),\n .\\sm_r_reg[1] (u_poc_n_1),\n .use_noise_window(use_noise_window));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_phy_prbs_rdlvl\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_phy_prbs_rdlvl\n (prbs_rdlvl_start_r,\n \\row_cnt_victim_rotate.complex_row_cnt_reg[4] ,\n prech_req_r_reg,\n prbs_prech_req_r,\n pi_en_stg2_f_timing_reg_0,\n prbs_pi_stg2_f_en,\n prbs_pi_stg2_f_incdec,\n A,\n \\A[0]_0 ,\n \\A[1]_0 ,\n no_err_win_detected_latch_reg_0,\n cnt_wait_state,\n \\rdlvl_cpt_tap_cnt_reg[5]_0 ,\n prbs_found_1st_edge_r_reg_0,\n \\genblk8[0].left_loss_pb_reg[0]_0 ,\n \\genblk8[1].left_loss_pb_reg[6]_0 ,\n \\genblk8[2].left_loss_pb_reg[12]_0 ,\n \\genblk8[3].left_loss_pb_reg[18]_0 ,\n \\genblk8[4].left_loss_pb_reg[24]_0 ,\n \\genblk8[5].left_loss_pb_reg[30]_0 ,\n \\genblk8[6].left_loss_pb_reg[36]_0 ,\n \\genblk8[7].left_loss_pb_reg[42]_0 ,\n \\genblk8[0].right_edge_pb_reg[0]_0 ,\n \\genblk8[1].right_edge_pb_reg[6]_0 ,\n \\genblk8[2].right_edge_pb_reg[12]_0 ,\n \\genblk8[3].right_edge_pb_reg[18]_0 ,\n \\genblk8[4].right_edge_pb_reg[24]_0 ,\n \\genblk8[5].right_edge_pb_reg[30]_0 ,\n \\genblk8[6].right_edge_pb_reg[36]_0 ,\n \\genblk8[7].right_edge_pb_reg[42]_0 ,\n fine_delay_sel_r_reg,\n right_edge_found_reg_0,\n prbs_tap_inc_r,\n \\match_flag_or_reg[0]_0 ,\n \\largest_left_edge_reg[0]_0 ,\n D,\n prbs_rdlvl_done_reg_0,\n \\stg1_wr_rd_cnt_reg[3] ,\n prbs_last_byte_done,\n reset_rd_addr,\n complex_init_pi_dec_done,\n complex_pi_incdec_done,\n \\prbs_dqs_cnt_r_reg[2]_0 ,\n complex_oclkdelay_calib_done_r1_reg,\n p_154_out,\n p_95_out,\n \\genblk8[7].right_edge_pb_reg[42]_1 ,\n p_98_out,\n p_103_out,\n p_106_out,\n \\genblk8[5].right_edge_pb_reg[30]_1 ,\n \\genblk8[5].right_gain_pb_reg[30]_0 ,\n p_119_out,\n p_122_out,\n p_127_out,\n p_130_out,\n \\genblk8[2].right_edge_pb_reg[12]_1 ,\n \\genblk8[2].right_edge_pb_reg[12]_2 ,\n p_143_out,\n p_146_out,\n \\genblk8[0].right_edge_pb_reg[0]_1 ,\n \\genblk8[0].left_loss_pb_reg[0]_1 ,\n Q,\n num_samples_done_r,\n prbs_state_r178_out,\n bit_cnt,\n \\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ,\n right_edge_found_reg_1,\n \\prbs_dec_tap_cnt_reg[1]_0 ,\n reset_rd_addr0,\n \\genblk8[7].left_edge_updated_reg[7]_0 ,\n \\rd_victim_sel_reg[2]_0 ,\n \\oclkdelay_ref_cnt_reg[0] ,\n prbs_rdlvl_done_pulse0,\n \\init_state_r_reg[0] ,\n \\init_state_r_reg[1] ,\n \\init_state_r_reg[0]_0 ,\n \\init_state_r_reg[1]_0 ,\n \\fine_delay_mod_reg[5] ,\n \\fine_delay_mod_reg[20] ,\n \\rdlvl_cpt_tap_cnt_reg[5]_1 ,\n right_gain_pb,\n right_edge_found,\n no_err_win_detected_reg_0,\n prbs_found_1st_edge_r_reg_1,\n prbs_tap_en_r_reg_0,\n prbs_tap_en_r,\n fine_delay_sel_reg_0,\n no_err_win_detected_latch_reg_1,\n fine_delay_sel_reg_1,\n complex_pi_incdec_done_reg_0,\n num_samples_done_ind_reg_0,\n complex_pi_incdec_done_reg_1,\n fine_dly_error_reg_0,\n compare_err_latch_reg_0,\n \\prbs_dqs_cnt_r_reg[1]_0 ,\n prbs_rdlvl_done_reg_1,\n prbs_last_byte_done_reg_0,\n new_cnt_dqs_r_reg_0,\n new_cnt_dqs_r,\n \\rd_victim_sel_reg[2]_1 ,\n \\rd_victim_sel_reg[2]_2 ,\n \\rd_victim_sel_reg[2]_3 ,\n \\fine_delay_mod_reg[26] ,\n \\genblk9[1].fine_delay_incdec_pb_reg[1]_0 ,\n \\genblk9[2].fine_delay_incdec_pb_reg[2]_0 ,\n \\genblk9[3].fine_delay_incdec_pb_reg[3]_0 ,\n \\genblk9[5].fine_delay_incdec_pb_reg[5]_0 ,\n \\genblk9[6].fine_delay_incdec_pb_reg[6]_0 ,\n \\genblk9[7].fine_delay_incdec_pb_reg[7]_0 ,\n CLK,\n prbs_rdlvl_start_reg,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,\n rstdiv0_sync_r1_reg_rep__7,\n \\dout_o_reg[7] ,\n \\dout_o_reg[7]_0 ,\n \\dout_o_reg[7]_1 ,\n \\dout_o_reg[7]_2 ,\n \\dout_o_reg[7]_3 ,\n \\dout_o_reg[7]_4 ,\n \\dout_o_reg[7]_5 ,\n \\dout_o_reg[7]_6 ,\n \\A[1]_1 ,\n \\A[1]_2 ,\n \\A[1]_3 ,\n \\A[1]_4 ,\n \\A[1]_5 ,\n \\A[1]_6 ,\n \\A[1]_7 ,\n \\A[1]_8 ,\n \\dout_o_reg[6] ,\n \\dout_o_reg[6]_0 ,\n \\dout_o_reg[6]_1 ,\n \\dout_o_reg[6]_2 ,\n \\dout_o_reg[6]_3 ,\n \\dout_o_reg[6]_4 ,\n \\dout_o_reg[6]_5 ,\n \\dout_o_reg[6]_6 ,\n \\A[1]_9 ,\n \\A[1]_10 ,\n \\A[1]_11 ,\n \\A[1]_12 ,\n \\A[1]_13 ,\n \\A[1]_14 ,\n \\A[1]_15 ,\n \\A[1]_16 ,\n \\dout_o_reg[5] ,\n \\dout_o_reg[5]_0 ,\n \\dout_o_reg[5]_1 ,\n \\dout_o_reg[5]_2 ,\n \\dout_o_reg[5]_3 ,\n \\dout_o_reg[5]_4 ,\n \\dout_o_reg[5]_5 ,\n \\dout_o_reg[5]_6 ,\n \\A[1]_17 ,\n \\A[1]_18 ,\n \\A[1]_19 ,\n \\A[1]_20 ,\n \\A[1]_21 ,\n \\A[1]_22 ,\n \\A[1]_23 ,\n \\A[1]_24 ,\n \\dout_o_reg[4] ,\n \\dout_o_reg[4]_0 ,\n \\dout_o_reg[4]_1 ,\n \\dout_o_reg[4]_2 ,\n \\dout_o_reg[4]_3 ,\n \\dout_o_reg[4]_4 ,\n \\dout_o_reg[4]_5 ,\n \\dout_o_reg[4]_6 ,\n \\A[1]_25 ,\n \\A[1]_26 ,\n \\A[1]_27 ,\n \\A[1]_28 ,\n \\A[1]_29 ,\n \\A[1]_30 ,\n \\A[1]_31 ,\n \\A[1]_32 ,\n \\dout_o_reg[3] ,\n \\dout_o_reg[3]_0 ,\n \\dout_o_reg[3]_1 ,\n \\dout_o_reg[3]_2 ,\n \\dout_o_reg[3]_3 ,\n \\dout_o_reg[3]_4 ,\n \\dout_o_reg[3]_5 ,\n \\dout_o_reg[3]_6 ,\n \\A[1]_33 ,\n \\A[1]_34 ,\n \\A[1]_35 ,\n \\A[1]_36 ,\n \\A[1]_37 ,\n \\A[1]_38 ,\n \\A[1]_39 ,\n \\A[1]_40 ,\n \\dout_o_reg[2] ,\n \\dout_o_reg[2]_0 ,\n \\dout_o_reg[2]_1 ,\n \\dout_o_reg[2]_2 ,\n \\dout_o_reg[2]_3 ,\n \\dout_o_reg[2]_4 ,\n \\dout_o_reg[2]_5 ,\n \\dout_o_reg[2]_6 ,\n \\A[1]_41 ,\n \\A[1]_42 ,\n \\A[1]_43 ,\n \\A[1]_44 ,\n \\A[1]_45 ,\n \\A[1]_46 ,\n \\A[1]_47 ,\n \\A[1]_48 ,\n \\dout_o_reg[1] ,\n \\dout_o_reg[1]_0 ,\n \\dout_o_reg[1]_1 ,\n \\dout_o_reg[1]_2 ,\n \\dout_o_reg[1]_3 ,\n \\dout_o_reg[1]_4 ,\n \\dout_o_reg[1]_5 ,\n \\dout_o_reg[1]_6 ,\n \\A[1]_49 ,\n \\A[1]_50 ,\n \\A[1]_51 ,\n \\A[1]_52 ,\n \\A[1]_53 ,\n \\A[1]_54 ,\n \\A[1]_55 ,\n \\A[1]_56 ,\n \\dout_o_reg[0] ,\n \\dout_o_reg[0]_0 ,\n \\dout_o_reg[0]_1 ,\n \\dout_o_reg[0]_2 ,\n \\dout_o_reg[0]_3 ,\n \\dout_o_reg[0]_4 ,\n \\dout_o_reg[0]_5 ,\n \\dout_o_reg[0]_6 ,\n \\A[1]_57 ,\n \\A[1]_58 ,\n \\A[1]_59 ,\n \\A[1]_60 ,\n \\A[1]_61 ,\n \\A[1]_62 ,\n \\A[1]_63 ,\n \\A[1]_64 ,\n rstdiv0_sync_r1_reg_rep__8,\n rstdiv0_sync_r1_reg_rep__2,\n SR,\n \\prbs_state_r_reg[4]_0 ,\n \\prbs_state_r_reg[3]_0 ,\n \\genblk8[0].left_edge_found_pb_reg[0]_0 ,\n \\genblk8[1].left_edge_found_pb_reg[1]_0 ,\n \\genblk8[2].left_edge_found_pb_reg[2]_0 ,\n \\genblk8[3].left_edge_found_pb_reg[3]_0 ,\n \\genblk8[4].left_edge_found_pb_reg[4]_0 ,\n \\genblk8[5].left_edge_found_pb_reg[5]_0 ,\n \\genblk8[6].left_edge_found_pb_reg[6]_0 ,\n \\genblk8[7].left_edge_found_pb_reg[7]_0 ,\n \\genblk8[0].right_edge_found_pb_reg[0]_0 ,\n \\genblk8[1].right_edge_found_pb_reg[1]_0 ,\n \\genblk8[2].right_edge_found_pb_reg[2]_0 ,\n \\genblk8[3].right_edge_found_pb_reg[3]_0 ,\n \\genblk8[4].right_edge_found_pb_reg[4]_0 ,\n \\genblk8[5].right_edge_found_pb_reg[5]_0 ,\n \\genblk8[6].right_edge_found_pb_reg[6]_0 ,\n \\genblk8[7].right_edge_found_pb_reg[7]_0 ,\n \\prbs_state_r_reg[0]_0 ,\n no_err_win_detected_reg_1,\n new_cnt_dqs_r_reg_1,\n \\prbs_state_r_reg[0]_1 ,\n \\prbs_state_r_reg[0]_2 ,\n \\prbs_state_r_reg[4]_1 ,\n \\prbs_state_r_reg[3]_1 ,\n \\genblk8[0].left_edge_updated_reg[0]_0 ,\n \\genblk8[1].left_edge_updated_reg[1]_0 ,\n \\genblk8[2].left_edge_updated_reg[2]_0 ,\n \\genblk8[3].left_edge_updated_reg[3]_0 ,\n \\genblk8[4].left_edge_updated_reg[4]_0 ,\n \\genblk8[5].left_edge_updated_reg[5]_0 ,\n \\genblk8[6].left_edge_updated_reg[6]_0 ,\n \\genblk8[7].left_edge_updated_reg[7]_1 ,\n \\dec_cnt_reg[0]_0 ,\n fine_dly_error_reg_1,\n \\prbs_state_r_reg[0]_3 ,\n prech_done_reg,\n prbs_tap_inc_r_reg_0,\n rstdiv0_sync_r1_reg_rep__9,\n \\prbs_state_r_reg[4]_2 ,\n \\prbs_state_r_reg[4]_3 ,\n \\prbs_state_r_reg[0]_4 ,\n \\prbs_dqs_cnt_r_reg[0]_0 ,\n \\prbs_dqs_cnt_r_reg[0]_1 ,\n \\prbs_dqs_cnt_r_reg[0]_2 ,\n rstdiv0_sync_r1_reg_rep,\n complex_ocal_reset_rd_addr,\n \\calib_sel_reg[3] ,\n \\pi_counter_read_val_reg[5] ,\n rstdiv0_sync_r1_reg_rep__23,\n oclkdelay_center_calib_done_r_reg,\n ocal_last_byte_done,\n prbs_rdlvl_done_r1,\n rdlvl_stg1_done_int_reg,\n wrcal_done_reg,\n dqs_found_done_r_reg,\n \\num_refresh_reg[1] ,\n wrlvl_final_mux,\n rdlvl_stg1_start_int,\n rdlvl_last_byte_done,\n \\one_rank.stg1_wr_done_reg ,\n \\A[2]__2 ,\n \\calib_sel_reg[3]_0 ,\n \\calib_sel_reg[3]_1 ,\n \\calib_sel_reg[3]_2 ,\n rstdiv0_sync_r1_reg_rep__22,\n complex_act_start,\n prech_done,\n prbs_rdlvl_start_reg_0,\n E,\n \\stage_cnt_reg[1]_0 );\n output prbs_rdlvl_start_r;\n output \\row_cnt_victim_rotate.complex_row_cnt_reg[4] ;\n output prech_req_r_reg;\n output prbs_prech_req_r;\n output pi_en_stg2_f_timing_reg_0;\n output prbs_pi_stg2_f_en;\n output prbs_pi_stg2_f_incdec;\n output [1:0]A;\n output \\A[0]_0 ;\n output \\A[1]_0 ;\n output no_err_win_detected_latch_reg_0;\n output cnt_wait_state;\n output \\rdlvl_cpt_tap_cnt_reg[5]_0 ;\n output prbs_found_1st_edge_r_reg_0;\n output \\genblk8[0].left_loss_pb_reg[0]_0 ;\n output \\genblk8[1].left_loss_pb_reg[6]_0 ;\n output \\genblk8[2].left_loss_pb_reg[12]_0 ;\n output \\genblk8[3].left_loss_pb_reg[18]_0 ;\n output \\genblk8[4].left_loss_pb_reg[24]_0 ;\n output \\genblk8[5].left_loss_pb_reg[30]_0 ;\n output \\genblk8[6].left_loss_pb_reg[36]_0 ;\n output \\genblk8[7].left_loss_pb_reg[42]_0 ;\n output \\genblk8[0].right_edge_pb_reg[0]_0 ;\n output \\genblk8[1].right_edge_pb_reg[6]_0 ;\n output \\genblk8[2].right_edge_pb_reg[12]_0 ;\n output \\genblk8[3].right_edge_pb_reg[18]_0 ;\n output \\genblk8[4].right_edge_pb_reg[24]_0 ;\n output \\genblk8[5].right_edge_pb_reg[30]_0 ;\n output \\genblk8[6].right_edge_pb_reg[36]_0 ;\n output \\genblk8[7].right_edge_pb_reg[42]_0 ;\n output fine_delay_sel_r_reg;\n output right_edge_found_reg_0;\n output prbs_tap_inc_r;\n output \\match_flag_or_reg[0]_0 ;\n output \\largest_left_edge_reg[0]_0 ;\n output [7:0]D;\n output prbs_rdlvl_done_reg_0;\n output \\stg1_wr_rd_cnt_reg[3] ;\n output prbs_last_byte_done;\n output reset_rd_addr;\n output complex_init_pi_dec_done;\n output complex_pi_incdec_done;\n output \\prbs_dqs_cnt_r_reg[2]_0 ;\n output complex_oclkdelay_calib_done_r1_reg;\n output p_154_out;\n output p_95_out;\n output \\genblk8[7].right_edge_pb_reg[42]_1 ;\n output p_98_out;\n output p_103_out;\n output p_106_out;\n output \\genblk8[5].right_edge_pb_reg[30]_1 ;\n output \\genblk8[5].right_gain_pb_reg[30]_0 ;\n output p_119_out;\n output p_122_out;\n output p_127_out;\n output p_130_out;\n output \\genblk8[2].right_edge_pb_reg[12]_1 ;\n output \\genblk8[2].right_edge_pb_reg[12]_2 ;\n output p_143_out;\n output p_146_out;\n output \\genblk8[0].right_edge_pb_reg[0]_1 ;\n output \\genblk8[0].left_loss_pb_reg[0]_1 ;\n output [4:0]Q;\n output num_samples_done_r;\n output prbs_state_r178_out;\n output bit_cnt;\n output \\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ;\n output right_edge_found_reg_1;\n output [1:0]\\prbs_dec_tap_cnt_reg[1]_0 ;\n output reset_rd_addr0;\n output \\genblk8[7].left_edge_updated_reg[7]_0 ;\n output \\rd_victim_sel_reg[2]_0 ;\n output \\oclkdelay_ref_cnt_reg[0] ;\n output prbs_rdlvl_done_pulse0;\n output \\init_state_r_reg[0] ;\n output \\init_state_r_reg[1] ;\n output \\init_state_r_reg[0]_0 ;\n output \\init_state_r_reg[1]_0 ;\n output \\fine_delay_mod_reg[5] ;\n output \\fine_delay_mod_reg[20] ;\n output [2:0]\\rdlvl_cpt_tap_cnt_reg[5]_1 ;\n output right_gain_pb;\n output right_edge_found;\n output no_err_win_detected_reg_0;\n output prbs_found_1st_edge_r_reg_1;\n output prbs_tap_en_r_reg_0;\n output prbs_tap_en_r;\n output fine_delay_sel_reg_0;\n output no_err_win_detected_latch_reg_1;\n output fine_delay_sel_reg_1;\n output complex_pi_incdec_done_reg_0;\n output num_samples_done_ind_reg_0;\n output complex_pi_incdec_done_reg_1;\n output fine_dly_error_reg_0;\n output compare_err_latch_reg_0;\n output \\prbs_dqs_cnt_r_reg[1]_0 ;\n output prbs_rdlvl_done_reg_1;\n output prbs_last_byte_done_reg_0;\n output new_cnt_dqs_r_reg_0;\n output new_cnt_dqs_r;\n output \\rd_victim_sel_reg[2]_1 ;\n output \\rd_victim_sel_reg[2]_2 ;\n output \\rd_victim_sel_reg[2]_3 ;\n output \\fine_delay_mod_reg[26] ;\n output \\genblk9[1].fine_delay_incdec_pb_reg[1]_0 ;\n output \\genblk9[2].fine_delay_incdec_pb_reg[2]_0 ;\n output \\genblk9[3].fine_delay_incdec_pb_reg[3]_0 ;\n output \\genblk9[5].fine_delay_incdec_pb_reg[5]_0 ;\n output \\genblk9[6].fine_delay_incdec_pb_reg[6]_0 ;\n output \\genblk9[7].fine_delay_incdec_pb_reg[7]_0 ;\n input CLK;\n input prbs_rdlvl_start_reg;\n input \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n input [0:0]rstdiv0_sync_r1_reg_rep__7;\n input \\dout_o_reg[7] ;\n input \\dout_o_reg[7]_0 ;\n input \\dout_o_reg[7]_1 ;\n input \\dout_o_reg[7]_2 ;\n input \\dout_o_reg[7]_3 ;\n input \\dout_o_reg[7]_4 ;\n input \\dout_o_reg[7]_5 ;\n input \\dout_o_reg[7]_6 ;\n input \\A[1]_1 ;\n input \\A[1]_2 ;\n input \\A[1]_3 ;\n input \\A[1]_4 ;\n input \\A[1]_5 ;\n input \\A[1]_6 ;\n input \\A[1]_7 ;\n input \\A[1]_8 ;\n input \\dout_o_reg[6] ;\n input \\dout_o_reg[6]_0 ;\n input \\dout_o_reg[6]_1 ;\n input \\dout_o_reg[6]_2 ;\n input \\dout_o_reg[6]_3 ;\n input \\dout_o_reg[6]_4 ;\n input \\dout_o_reg[6]_5 ;\n input \\dout_o_reg[6]_6 ;\n input \\A[1]_9 ;\n input \\A[1]_10 ;\n input \\A[1]_11 ;\n input \\A[1]_12 ;\n input \\A[1]_13 ;\n input \\A[1]_14 ;\n input \\A[1]_15 ;\n input \\A[1]_16 ;\n input \\dout_o_reg[5] ;\n input \\dout_o_reg[5]_0 ;\n input \\dout_o_reg[5]_1 ;\n input \\dout_o_reg[5]_2 ;\n input \\dout_o_reg[5]_3 ;\n input \\dout_o_reg[5]_4 ;\n input \\dout_o_reg[5]_5 ;\n input \\dout_o_reg[5]_6 ;\n input \\A[1]_17 ;\n input \\A[1]_18 ;\n input \\A[1]_19 ;\n input \\A[1]_20 ;\n input \\A[1]_21 ;\n input \\A[1]_22 ;\n input \\A[1]_23 ;\n input \\A[1]_24 ;\n input \\dout_o_reg[4] ;\n input \\dout_o_reg[4]_0 ;\n input \\dout_o_reg[4]_1 ;\n input \\dout_o_reg[4]_2 ;\n input \\dout_o_reg[4]_3 ;\n input \\dout_o_reg[4]_4 ;\n input \\dout_o_reg[4]_5 ;\n input \\dout_o_reg[4]_6 ;\n input \\A[1]_25 ;\n input \\A[1]_26 ;\n input \\A[1]_27 ;\n input \\A[1]_28 ;\n input \\A[1]_29 ;\n input \\A[1]_30 ;\n input \\A[1]_31 ;\n input \\A[1]_32 ;\n input \\dout_o_reg[3] ;\n input \\dout_o_reg[3]_0 ;\n input \\dout_o_reg[3]_1 ;\n input \\dout_o_reg[3]_2 ;\n input \\dout_o_reg[3]_3 ;\n input \\dout_o_reg[3]_4 ;\n input \\dout_o_reg[3]_5 ;\n input \\dout_o_reg[3]_6 ;\n input \\A[1]_33 ;\n input \\A[1]_34 ;\n input \\A[1]_35 ;\n input \\A[1]_36 ;\n input \\A[1]_37 ;\n input \\A[1]_38 ;\n input \\A[1]_39 ;\n input \\A[1]_40 ;\n input \\dout_o_reg[2] ;\n input \\dout_o_reg[2]_0 ;\n input \\dout_o_reg[2]_1 ;\n input \\dout_o_reg[2]_2 ;\n input \\dout_o_reg[2]_3 ;\n input \\dout_o_reg[2]_4 ;\n input \\dout_o_reg[2]_5 ;\n input \\dout_o_reg[2]_6 ;\n input \\A[1]_41 ;\n input \\A[1]_42 ;\n input \\A[1]_43 ;\n input \\A[1]_44 ;\n input \\A[1]_45 ;\n input \\A[1]_46 ;\n input \\A[1]_47 ;\n input \\A[1]_48 ;\n input \\dout_o_reg[1] ;\n input \\dout_o_reg[1]_0 ;\n input \\dout_o_reg[1]_1 ;\n input \\dout_o_reg[1]_2 ;\n input \\dout_o_reg[1]_3 ;\n input \\dout_o_reg[1]_4 ;\n input \\dout_o_reg[1]_5 ;\n input \\dout_o_reg[1]_6 ;\n input \\A[1]_49 ;\n input \\A[1]_50 ;\n input \\A[1]_51 ;\n input \\A[1]_52 ;\n input \\A[1]_53 ;\n input \\A[1]_54 ;\n input \\A[1]_55 ;\n input \\A[1]_56 ;\n input \\dout_o_reg[0] ;\n input \\dout_o_reg[0]_0 ;\n input \\dout_o_reg[0]_1 ;\n input \\dout_o_reg[0]_2 ;\n input \\dout_o_reg[0]_3 ;\n input \\dout_o_reg[0]_4 ;\n input \\dout_o_reg[0]_5 ;\n input \\dout_o_reg[0]_6 ;\n input \\A[1]_57 ;\n input \\A[1]_58 ;\n input \\A[1]_59 ;\n input \\A[1]_60 ;\n input \\A[1]_61 ;\n input \\A[1]_62 ;\n input \\A[1]_63 ;\n input \\A[1]_64 ;\n input rstdiv0_sync_r1_reg_rep__8;\n input rstdiv0_sync_r1_reg_rep__2;\n input [0:0]SR;\n input \\prbs_state_r_reg[4]_0 ;\n input \\prbs_state_r_reg[3]_0 ;\n input \\genblk8[0].left_edge_found_pb_reg[0]_0 ;\n input \\genblk8[1].left_edge_found_pb_reg[1]_0 ;\n input \\genblk8[2].left_edge_found_pb_reg[2]_0 ;\n input \\genblk8[3].left_edge_found_pb_reg[3]_0 ;\n input \\genblk8[4].left_edge_found_pb_reg[4]_0 ;\n input \\genblk8[5].left_edge_found_pb_reg[5]_0 ;\n input \\genblk8[6].left_edge_found_pb_reg[6]_0 ;\n input \\genblk8[7].left_edge_found_pb_reg[7]_0 ;\n input \\genblk8[0].right_edge_found_pb_reg[0]_0 ;\n input \\genblk8[1].right_edge_found_pb_reg[1]_0 ;\n input \\genblk8[2].right_edge_found_pb_reg[2]_0 ;\n input \\genblk8[3].right_edge_found_pb_reg[3]_0 ;\n input \\genblk8[4].right_edge_found_pb_reg[4]_0 ;\n input \\genblk8[5].right_edge_found_pb_reg[5]_0 ;\n input \\genblk8[6].right_edge_found_pb_reg[6]_0 ;\n input \\genblk8[7].right_edge_found_pb_reg[7]_0 ;\n input \\prbs_state_r_reg[0]_0 ;\n input no_err_win_detected_reg_1;\n input new_cnt_dqs_r_reg_1;\n input \\prbs_state_r_reg[0]_1 ;\n input \\prbs_state_r_reg[0]_2 ;\n input \\prbs_state_r_reg[4]_1 ;\n input \\prbs_state_r_reg[3]_1 ;\n input \\genblk8[0].left_edge_updated_reg[0]_0 ;\n input \\genblk8[1].left_edge_updated_reg[1]_0 ;\n input \\genblk8[2].left_edge_updated_reg[2]_0 ;\n input \\genblk8[3].left_edge_updated_reg[3]_0 ;\n input \\genblk8[4].left_edge_updated_reg[4]_0 ;\n input \\genblk8[5].left_edge_updated_reg[5]_0 ;\n input \\genblk8[6].left_edge_updated_reg[6]_0 ;\n input \\genblk8[7].left_edge_updated_reg[7]_1 ;\n input \\dec_cnt_reg[0]_0 ;\n input fine_dly_error_reg_1;\n input \\prbs_state_r_reg[0]_3 ;\n input prech_done_reg;\n input prbs_tap_inc_r_reg_0;\n input rstdiv0_sync_r1_reg_rep__9;\n input \\prbs_state_r_reg[4]_2 ;\n input \\prbs_state_r_reg[4]_3 ;\n input \\prbs_state_r_reg[0]_4 ;\n input \\prbs_dqs_cnt_r_reg[0]_0 ;\n input \\prbs_dqs_cnt_r_reg[0]_1 ;\n input \\prbs_dqs_cnt_r_reg[0]_2 ;\n input rstdiv0_sync_r1_reg_rep;\n input complex_ocal_reset_rd_addr;\n input [0:0]\\calib_sel_reg[3] ;\n input [3:0]\\pi_counter_read_val_reg[5] ;\n input rstdiv0_sync_r1_reg_rep__23;\n input oclkdelay_center_calib_done_r_reg;\n input ocal_last_byte_done;\n input prbs_rdlvl_done_r1;\n input rdlvl_stg1_done_int_reg;\n input wrcal_done_reg;\n input dqs_found_done_r_reg;\n input \\num_refresh_reg[1] ;\n input wrlvl_final_mux;\n input rdlvl_stg1_start_int;\n input rdlvl_last_byte_done;\n input \\one_rank.stg1_wr_done_reg ;\n input \\A[2]__2 ;\n input \\calib_sel_reg[3]_0 ;\n input \\calib_sel_reg[3]_1 ;\n input \\calib_sel_reg[3]_2 ;\n input rstdiv0_sync_r1_reg_rep__22;\n input complex_act_start;\n input prech_done;\n input prbs_rdlvl_start_reg_0;\n input [0:0]E;\n input \\stage_cnt_reg[1]_0 ;\n\n wire [1:0]A;\n wire \\A[0]_0 ;\n wire \\A[1]_0 ;\n wire \\A[1]_1 ;\n wire \\A[1]_10 ;\n wire \\A[1]_11 ;\n wire \\A[1]_12 ;\n wire \\A[1]_13 ;\n wire \\A[1]_14 ;\n wire \\A[1]_15 ;\n wire \\A[1]_16 ;\n wire \\A[1]_17 ;\n wire \\A[1]_18 ;\n wire \\A[1]_19 ;\n wire \\A[1]_2 ;\n wire \\A[1]_20 ;\n wire \\A[1]_21 ;\n wire \\A[1]_22 ;\n wire \\A[1]_23 ;\n wire \\A[1]_24 ;\n wire \\A[1]_25 ;\n wire \\A[1]_26 ;\n wire \\A[1]_27 ;\n wire \\A[1]_28 ;\n wire \\A[1]_29 ;\n wire \\A[1]_3 ;\n wire \\A[1]_30 ;\n wire \\A[1]_31 ;\n wire \\A[1]_32 ;\n wire \\A[1]_33 ;\n wire \\A[1]_34 ;\n wire \\A[1]_35 ;\n wire \\A[1]_36 ;\n wire \\A[1]_37 ;\n wire \\A[1]_38 ;\n wire \\A[1]_39 ;\n wire \\A[1]_4 ;\n wire \\A[1]_40 ;\n wire \\A[1]_41 ;\n wire \\A[1]_42 ;\n wire \\A[1]_43 ;\n wire \\A[1]_44 ;\n wire \\A[1]_45 ;\n wire \\A[1]_46 ;\n wire \\A[1]_47 ;\n wire \\A[1]_48 ;\n wire \\A[1]_49 ;\n wire \\A[1]_5 ;\n wire \\A[1]_50 ;\n wire \\A[1]_51 ;\n wire \\A[1]_52 ;\n wire \\A[1]_53 ;\n wire \\A[1]_54 ;\n wire \\A[1]_55 ;\n wire \\A[1]_56 ;\n wire \\A[1]_57 ;\n wire \\A[1]_58 ;\n wire \\A[1]_59 ;\n wire \\A[1]_6 ;\n wire \\A[1]_60 ;\n wire \\A[1]_61 ;\n wire \\A[1]_62 ;\n wire \\A[1]_63 ;\n wire \\A[1]_64 ;\n wire \\A[1]_7 ;\n wire \\A[1]_8 ;\n wire \\A[1]_9 ;\n wire \\A[2]__2 ;\n wire CLK;\n wire [7:0]D;\n wire [0:0]E;\n wire [4:0]Q;\n wire [0:0]SR;\n wire bit_cnt;\n wire bit_cnt0;\n wire \\bit_cnt[7]_i_3_n_0 ;\n wire \\bit_cnt[7]_i_4_n_0 ;\n wire [7:0]bit_cnt_reg__0;\n wire [0:0]\\calib_sel_reg[3] ;\n wire \\calib_sel_reg[3]_0 ;\n wire \\calib_sel_reg[3]_1 ;\n wire \\calib_sel_reg[3]_2 ;\n wire \\cmp_err_4to1.compare_err_f0_i_2_n_0 ;\n wire \\cmp_err_4to1.compare_err_f0_i_3_n_0 ;\n wire \\cmp_err_4to1.compare_err_f0_reg_n_0 ;\n wire \\cmp_err_4to1.compare_err_f1_i_2_n_0 ;\n wire \\cmp_err_4to1.compare_err_f1_i_3_n_0 ;\n wire \\cmp_err_4to1.compare_err_f1_reg_n_0 ;\n wire \\cmp_err_4to1.compare_err_f2_i_2_n_0 ;\n wire \\cmp_err_4to1.compare_err_f2_i_3_n_0 ;\n wire \\cmp_err_4to1.compare_err_f2_reg_n_0 ;\n wire \\cmp_err_4to1.compare_err_f3_i_2_n_0 ;\n wire \\cmp_err_4to1.compare_err_f3_i_3_n_0 ;\n wire \\cmp_err_4to1.compare_err_f3_reg_n_0 ;\n wire \\cmp_err_4to1.compare_err_i_4_n_0 ;\n wire \\cmp_err_4to1.compare_err_r0_i_2_n_0 ;\n wire \\cmp_err_4to1.compare_err_r0_i_3_n_0 ;\n wire \\cmp_err_4to1.compare_err_r0_reg_n_0 ;\n wire \\cmp_err_4to1.compare_err_r1_i_2_n_0 ;\n wire \\cmp_err_4to1.compare_err_r1_i_3_n_0 ;\n wire \\cmp_err_4to1.compare_err_r1_reg_n_0 ;\n wire \\cmp_err_4to1.compare_err_r2_i_2_n_0 ;\n wire \\cmp_err_4to1.compare_err_r2_i_3_n_0 ;\n wire \\cmp_err_4to1.compare_err_r2_reg_n_0 ;\n wire \\cmp_err_4to1.compare_err_r3_i_2_n_0 ;\n wire \\cmp_err_4to1.compare_err_r3_i_3_n_0 ;\n wire \\cmp_err_4to1.compare_err_r3_reg_n_0 ;\n wire \\cmp_err_4to1.compare_err_reg_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_5_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_6_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_7_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_2_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_3_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_4_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_2_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_3_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_4_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_2_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_3_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_4_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_2_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_3_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_4_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_2_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_3_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_4_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_2_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_3_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_4_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_2_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_3_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_4_n_0 ;\n wire cnt_wait_state;\n wire cnt_wait_state_i_1_n_0;\n wire compare_err0;\n wire compare_err086_out__0;\n wire compare_err2;\n wire compare_err_f00;\n wire compare_err_f10;\n wire compare_err_f20;\n wire compare_err_f30;\n wire compare_err_latch_i_1_n_0;\n wire compare_err_latch_i_2_n_0;\n wire compare_err_latch_reg_0;\n wire compare_err_latch_reg_n_0;\n wire [7:0]compare_err_pb;\n wire compare_err_pb_and2;\n wire compare_err_pb_and_i_1_n_0;\n wire compare_err_pb_and_i_2_n_0;\n wire compare_err_pb_and_i_3_n_0;\n wire compare_err_pb_and_reg_n_0;\n wire compare_err_pb_or_i_1_n_0;\n wire compare_err_pb_or_i_2_n_0;\n wire compare_err_pb_or_i_3_n_0;\n wire compare_err_r00;\n wire compare_err_r10;\n wire compare_err_r20;\n wire compare_err_r30;\n wire complex_act_start;\n wire complex_init_pi_dec_done;\n wire complex_ocal_reset_rd_addr;\n wire complex_oclkdelay_calib_done_r1_reg;\n wire complex_pi_incdec_done;\n wire complex_pi_incdec_done_i_3_n_0;\n wire complex_pi_incdec_done_i_4_n_0;\n wire complex_pi_incdec_done_i_5_n_0;\n wire complex_pi_incdec_done_i_6_n_0;\n wire complex_pi_incdec_done_reg_0;\n wire complex_pi_incdec_done_reg_1;\n wire complex_victim_inc__0;\n wire [11:1]data0;\n wire \\dec_cnt[0]_i_11_n_0 ;\n wire \\dec_cnt[0]_i_13_n_0 ;\n wire \\dec_cnt[0]_i_14_n_0 ;\n wire \\dec_cnt[0]_i_15_n_0 ;\n wire \\dec_cnt[0]_i_16_n_0 ;\n wire \\dec_cnt[0]_i_17_n_0 ;\n wire \\dec_cnt[0]_i_1_n_0 ;\n wire \\dec_cnt[0]_i_20_n_0 ;\n wire \\dec_cnt[0]_i_21_n_0 ;\n wire \\dec_cnt[0]_i_22_n_0 ;\n wire \\dec_cnt[0]_i_23_n_0 ;\n wire \\dec_cnt[0]_i_24_n_0 ;\n wire \\dec_cnt[0]_i_25_n_0 ;\n wire \\dec_cnt[0]_i_26_n_0 ;\n wire \\dec_cnt[0]_i_29_n_0 ;\n wire \\dec_cnt[0]_i_32_n_0 ;\n wire \\dec_cnt[0]_i_33_n_0 ;\n wire \\dec_cnt[0]_i_34_n_0 ;\n wire \\dec_cnt[0]_i_35_n_0 ;\n wire \\dec_cnt[0]_i_36_n_0 ;\n wire \\dec_cnt[0]_i_37_n_0 ;\n wire \\dec_cnt[0]_i_38_n_0 ;\n wire \\dec_cnt[0]_i_39_n_0 ;\n wire \\dec_cnt[0]_i_3_n_0 ;\n wire \\dec_cnt[0]_i_40_n_0 ;\n wire \\dec_cnt[0]_i_41_n_0 ;\n wire \\dec_cnt[0]_i_42_n_0 ;\n wire \\dec_cnt[0]_i_43_n_0 ;\n wire \\dec_cnt[0]_i_44_n_0 ;\n wire \\dec_cnt[0]_i_45_n_0 ;\n wire \\dec_cnt[0]_i_46_n_0 ;\n wire \\dec_cnt[0]_i_47_n_0 ;\n wire \\dec_cnt[0]_i_4_n_0 ;\n wire \\dec_cnt[0]_i_5_n_0 ;\n wire \\dec_cnt[0]_i_6_n_0 ;\n wire \\dec_cnt[0]_i_8_n_0 ;\n wire \\dec_cnt[0]_i_9_n_0 ;\n wire \\dec_cnt[1]_i_13_n_0 ;\n wire \\dec_cnt[1]_i_15_n_0 ;\n wire \\dec_cnt[1]_i_16_n_0 ;\n wire \\dec_cnt[1]_i_19_n_0 ;\n wire \\dec_cnt[1]_i_1_n_0 ;\n wire \\dec_cnt[1]_i_20_n_0 ;\n wire \\dec_cnt[1]_i_21_n_0 ;\n wire \\dec_cnt[1]_i_22_n_0 ;\n wire \\dec_cnt[1]_i_25_n_0 ;\n wire \\dec_cnt[1]_i_26_n_0 ;\n wire \\dec_cnt[1]_i_27_n_0 ;\n wire \\dec_cnt[1]_i_28_n_0 ;\n wire \\dec_cnt[1]_i_29_n_0 ;\n wire \\dec_cnt[1]_i_2_n_0 ;\n wire \\dec_cnt[1]_i_30_n_0 ;\n wire \\dec_cnt[1]_i_31_n_0 ;\n wire \\dec_cnt[1]_i_32_n_0 ;\n wire \\dec_cnt[1]_i_33_n_0 ;\n wire \\dec_cnt[1]_i_34_n_0 ;\n wire \\dec_cnt[1]_i_35_n_0 ;\n wire \\dec_cnt[1]_i_36_n_0 ;\n wire \\dec_cnt[1]_i_37_n_0 ;\n wire \\dec_cnt[1]_i_38_n_0 ;\n wire \\dec_cnt[1]_i_3_n_0 ;\n wire \\dec_cnt[1]_i_4_n_0 ;\n wire \\dec_cnt[1]_i_5_n_0 ;\n wire \\dec_cnt[1]_i_6_n_0 ;\n wire \\dec_cnt[1]_i_8_n_0 ;\n wire \\dec_cnt[1]_i_9_n_0 ;\n wire \\dec_cnt[2]_i_10_n_0 ;\n wire \\dec_cnt[2]_i_11_n_0 ;\n wire \\dec_cnt[2]_i_12_n_0 ;\n wire \\dec_cnt[2]_i_13_n_0 ;\n wire \\dec_cnt[2]_i_14_n_0 ;\n wire \\dec_cnt[2]_i_15_n_0 ;\n wire \\dec_cnt[2]_i_17_n_0 ;\n wire \\dec_cnt[2]_i_18_n_0 ;\n wire \\dec_cnt[2]_i_19_n_0 ;\n wire \\dec_cnt[2]_i_20_n_0 ;\n wire \\dec_cnt[2]_i_21_n_0 ;\n wire \\dec_cnt[2]_i_22_n_0 ;\n wire \\dec_cnt[2]_i_23_n_0 ;\n wire \\dec_cnt[2]_i_24_n_0 ;\n wire \\dec_cnt[2]_i_25_n_0 ;\n wire \\dec_cnt[2]_i_26_n_0 ;\n wire \\dec_cnt[2]_i_27_n_0 ;\n wire \\dec_cnt[2]_i_28_n_0 ;\n wire \\dec_cnt[2]_i_29_n_0 ;\n wire \\dec_cnt[2]_i_2_n_0 ;\n wire \\dec_cnt[2]_i_30_n_0 ;\n wire \\dec_cnt[2]_i_31_n_0 ;\n wire \\dec_cnt[2]_i_32_n_0 ;\n wire \\dec_cnt[2]_i_33_n_0 ;\n wire \\dec_cnt[2]_i_34_n_0 ;\n wire \\dec_cnt[2]_i_3_n_0 ;\n wire \\dec_cnt[2]_i_5_n_0 ;\n wire \\dec_cnt[2]_i_6_n_0 ;\n wire \\dec_cnt[2]_i_7_n_0 ;\n wire \\dec_cnt[3]_i_10_n_0 ;\n wire \\dec_cnt[3]_i_11_n_0 ;\n wire \\dec_cnt[3]_i_12_n_0 ;\n wire \\dec_cnt[3]_i_13_n_0 ;\n wire \\dec_cnt[3]_i_14_n_0 ;\n wire \\dec_cnt[3]_i_15_n_0 ;\n wire \\dec_cnt[3]_i_16_n_0 ;\n wire \\dec_cnt[3]_i_17_n_0 ;\n wire \\dec_cnt[3]_i_18_n_0 ;\n wire \\dec_cnt[3]_i_19_n_0 ;\n wire \\dec_cnt[3]_i_1_n_0 ;\n wire \\dec_cnt[3]_i_20_n_0 ;\n wire \\dec_cnt[3]_i_21_n_0 ;\n wire \\dec_cnt[3]_i_22_n_0 ;\n wire \\dec_cnt[3]_i_23_n_0 ;\n wire \\dec_cnt[3]_i_24_n_0 ;\n wire \\dec_cnt[3]_i_25_n_0 ;\n wire \\dec_cnt[3]_i_26_n_0 ;\n wire \\dec_cnt[3]_i_27_n_0 ;\n wire \\dec_cnt[3]_i_2_n_0 ;\n wire \\dec_cnt[3]_i_3_n_0 ;\n wire \\dec_cnt[3]_i_4_n_0 ;\n wire \\dec_cnt[3]_i_5_n_0 ;\n wire \\dec_cnt[3]_i_6_n_0 ;\n wire \\dec_cnt[3]_i_7_n_0 ;\n wire \\dec_cnt[3]_i_8_n_0 ;\n wire \\dec_cnt[3]_i_9_n_0 ;\n wire \\dec_cnt[4]_i_10_n_0 ;\n wire \\dec_cnt[4]_i_11_n_0 ;\n wire \\dec_cnt[4]_i_12_n_0 ;\n wire \\dec_cnt[4]_i_13_n_0 ;\n wire \\dec_cnt[4]_i_14_n_0 ;\n wire \\dec_cnt[4]_i_15_n_0 ;\n wire \\dec_cnt[4]_i_16_n_0 ;\n wire \\dec_cnt[4]_i_17_n_0 ;\n wire \\dec_cnt[4]_i_1_n_0 ;\n wire \\dec_cnt[4]_i_3_n_0 ;\n wire \\dec_cnt[4]_i_4_n_0 ;\n wire \\dec_cnt[4]_i_5_n_0 ;\n wire \\dec_cnt[4]_i_6_n_0 ;\n wire \\dec_cnt[4]_i_7_n_0 ;\n wire \\dec_cnt[4]_i_8_n_0 ;\n wire \\dec_cnt[4]_i_9_n_0 ;\n wire \\dec_cnt[5]_i_1_n_0 ;\n wire \\dec_cnt[5]_i_2_n_0 ;\n wire \\dec_cnt[5]_i_3_n_0 ;\n wire \\dec_cnt[5]_i_4_n_0 ;\n wire \\dec_cnt[5]_i_5_n_0 ;\n wire \\dec_cnt[5]_i_6_n_0 ;\n wire \\dec_cnt[5]_i_7_n_0 ;\n wire [4:1]dec_cnt_reg;\n wire \\dec_cnt_reg[0]_0 ;\n wire \\dec_cnt_reg[0]_i_10_n_0 ;\n wire \\dec_cnt_reg[0]_i_12_n_0 ;\n wire \\dec_cnt_reg[0]_i_18_n_0 ;\n wire \\dec_cnt_reg[0]_i_19_n_0 ;\n wire \\dec_cnt_reg[0]_i_27_n_0 ;\n wire \\dec_cnt_reg[0]_i_28_n_0 ;\n wire \\dec_cnt_reg[0]_i_2_n_0 ;\n wire \\dec_cnt_reg[0]_i_30_n_0 ;\n wire \\dec_cnt_reg[0]_i_31_n_0 ;\n wire \\dec_cnt_reg[0]_i_7_n_0 ;\n wire \\dec_cnt_reg[1]_i_10_n_0 ;\n wire \\dec_cnt_reg[1]_i_11_n_0 ;\n wire \\dec_cnt_reg[1]_i_12_n_0 ;\n wire \\dec_cnt_reg[1]_i_14_n_0 ;\n wire \\dec_cnt_reg[1]_i_17_n_0 ;\n wire \\dec_cnt_reg[1]_i_18_n_0 ;\n wire \\dec_cnt_reg[1]_i_23_n_0 ;\n wire \\dec_cnt_reg[1]_i_24_n_0 ;\n wire \\dec_cnt_reg[1]_i_7_n_0 ;\n wire \\dec_cnt_reg[2]_i_16_n_0 ;\n wire \\dec_cnt_reg[2]_i_1_n_0 ;\n wire \\dec_cnt_reg[2]_i_4_n_0 ;\n wire \\dec_cnt_reg[2]_i_8_n_0 ;\n wire \\dec_cnt_reg[2]_i_9_n_0 ;\n wire \\dec_cnt_reg[4]_i_2_n_0 ;\n wire \\dout_o_reg[0] ;\n wire \\dout_o_reg[0]_0 ;\n wire \\dout_o_reg[0]_1 ;\n wire \\dout_o_reg[0]_2 ;\n wire \\dout_o_reg[0]_3 ;\n wire \\dout_o_reg[0]_4 ;\n wire \\dout_o_reg[0]_5 ;\n wire \\dout_o_reg[0]_6 ;\n wire \\dout_o_reg[1] ;\n wire \\dout_o_reg[1]_0 ;\n wire \\dout_o_reg[1]_1 ;\n wire \\dout_o_reg[1]_2 ;\n wire \\dout_o_reg[1]_3 ;\n wire \\dout_o_reg[1]_4 ;\n wire \\dout_o_reg[1]_5 ;\n wire \\dout_o_reg[1]_6 ;\n wire \\dout_o_reg[2] ;\n wire \\dout_o_reg[2]_0 ;\n wire \\dout_o_reg[2]_1 ;\n wire \\dout_o_reg[2]_2 ;\n wire \\dout_o_reg[2]_3 ;\n wire \\dout_o_reg[2]_4 ;\n wire \\dout_o_reg[2]_5 ;\n wire \\dout_o_reg[2]_6 ;\n wire \\dout_o_reg[3] ;\n wire \\dout_o_reg[3]_0 ;\n wire \\dout_o_reg[3]_1 ;\n wire \\dout_o_reg[3]_2 ;\n wire \\dout_o_reg[3]_3 ;\n wire \\dout_o_reg[3]_4 ;\n wire \\dout_o_reg[3]_5 ;\n wire \\dout_o_reg[3]_6 ;\n wire \\dout_o_reg[4] ;\n wire \\dout_o_reg[4]_0 ;\n wire \\dout_o_reg[4]_1 ;\n wire \\dout_o_reg[4]_2 ;\n wire \\dout_o_reg[4]_3 ;\n wire \\dout_o_reg[4]_4 ;\n wire \\dout_o_reg[4]_5 ;\n wire \\dout_o_reg[4]_6 ;\n wire \\dout_o_reg[5] ;\n wire \\dout_o_reg[5]_0 ;\n wire \\dout_o_reg[5]_1 ;\n wire \\dout_o_reg[5]_2 ;\n wire \\dout_o_reg[5]_3 ;\n wire \\dout_o_reg[5]_4 ;\n wire \\dout_o_reg[5]_5 ;\n wire \\dout_o_reg[5]_6 ;\n wire \\dout_o_reg[6] ;\n wire \\dout_o_reg[6]_0 ;\n wire \\dout_o_reg[6]_1 ;\n wire \\dout_o_reg[6]_2 ;\n wire \\dout_o_reg[6]_3 ;\n wire \\dout_o_reg[6]_4 ;\n wire \\dout_o_reg[6]_5 ;\n wire \\dout_o_reg[6]_6 ;\n wire \\dout_o_reg[7] ;\n wire \\dout_o_reg[7]_0 ;\n wire \\dout_o_reg[7]_1 ;\n wire \\dout_o_reg[7]_2 ;\n wire \\dout_o_reg[7]_3 ;\n wire \\dout_o_reg[7]_4 ;\n wire \\dout_o_reg[7]_5 ;\n wire \\dout_o_reg[7]_6 ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n wire dqs_found_done_r_reg;\n wire err_chk_invalid;\n wire err_chk_invalid_i_1_n_0;\n wire \\fine_delay_mod_reg[20] ;\n wire \\fine_delay_mod_reg[26] ;\n wire \\fine_delay_mod_reg[5] ;\n wire fine_delay_sel_i_4_n_0;\n wire fine_delay_sel_r_reg;\n wire fine_delay_sel_reg_0;\n wire fine_delay_sel_reg_1;\n wire fine_dly_error_reg_0;\n wire fine_dly_error_reg_1;\n wire fine_inc_stage_i_1_n_0;\n wire fine_inc_stage_reg_n_0;\n wire fine_pi_dec_cnt;\n wire \\fine_pi_dec_cnt[0]_i_1_n_0 ;\n wire \\fine_pi_dec_cnt[0]_i_2_n_0 ;\n wire \\fine_pi_dec_cnt[1]_i_1_n_0 ;\n wire \\fine_pi_dec_cnt[1]_i_2_n_0 ;\n wire \\fine_pi_dec_cnt[2]_i_1_n_0 ;\n wire \\fine_pi_dec_cnt[2]_i_2_n_0 ;\n wire \\fine_pi_dec_cnt[3]_i_10_n_0 ;\n wire \\fine_pi_dec_cnt[3]_i_1_n_0 ;\n wire \\fine_pi_dec_cnt[3]_i_2_n_0 ;\n wire \\fine_pi_dec_cnt[3]_i_4_n_0 ;\n wire \\fine_pi_dec_cnt[3]_i_5_n_0 ;\n wire \\fine_pi_dec_cnt[3]_i_6_n_0 ;\n wire \\fine_pi_dec_cnt[3]_i_7_n_0 ;\n wire \\fine_pi_dec_cnt[3]_i_8_n_0 ;\n wire \\fine_pi_dec_cnt[3]_i_9_n_0 ;\n wire \\fine_pi_dec_cnt[4]_i_2_n_0 ;\n wire \\fine_pi_dec_cnt[4]_i_3_n_0 ;\n wire \\fine_pi_dec_cnt[5]_i_10_n_0 ;\n wire \\fine_pi_dec_cnt[5]_i_11_n_0 ;\n wire \\fine_pi_dec_cnt[5]_i_3_n_0 ;\n wire \\fine_pi_dec_cnt[5]_i_4_n_0 ;\n wire \\fine_pi_dec_cnt[5]_i_5_n_0 ;\n wire \\fine_pi_dec_cnt[5]_i_6_n_0 ;\n wire \\fine_pi_dec_cnt[5]_i_7_n_0 ;\n wire \\fine_pi_dec_cnt[5]_i_9_n_0 ;\n wire \\fine_pi_dec_cnt_reg[3]_i_3_n_0 ;\n wire \\fine_pi_dec_cnt_reg[3]_i_3_n_1 ;\n wire \\fine_pi_dec_cnt_reg[3]_i_3_n_2 ;\n wire \\fine_pi_dec_cnt_reg[3]_i_3_n_3 ;\n wire \\fine_pi_dec_cnt_reg[3]_i_3_n_4 ;\n wire \\fine_pi_dec_cnt_reg[3]_i_3_n_5 ;\n wire \\fine_pi_dec_cnt_reg[3]_i_3_n_6 ;\n wire \\fine_pi_dec_cnt_reg[3]_i_3_n_7 ;\n wire \\fine_pi_dec_cnt_reg[4]_i_1_n_0 ;\n wire \\fine_pi_dec_cnt_reg[5]_i_2_n_0 ;\n wire \\fine_pi_dec_cnt_reg[5]_i_8_n_3 ;\n wire \\fine_pi_dec_cnt_reg[5]_i_8_n_6 ;\n wire \\fine_pi_dec_cnt_reg[5]_i_8_n_7 ;\n wire \\fine_pi_dec_cnt_reg_n_0_[0] ;\n wire \\fine_pi_dec_cnt_reg_n_0_[1] ;\n wire \\fine_pi_dec_cnt_reg_n_0_[2] ;\n wire \\fine_pi_dec_cnt_reg_n_0_[3] ;\n wire \\fine_pi_dec_cnt_reg_n_0_[4] ;\n wire \\fine_pi_dec_cnt_reg_n_0_[5] ;\n wire \\gen_mux_div4.gen_rd_4[0].mux_rd_fall0_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[0].mux_rd_fall1_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[0].mux_rd_fall2_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[0].mux_rd_fall3_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[0].mux_rd_rise0_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[0].mux_rd_rise1_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[0].mux_rd_rise2_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[0].mux_rd_rise3_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r3_reg ;\n wire \\gen_mux_rd[0].compare_data_fall0_r1_reg ;\n wire \\gen_mux_rd[0].compare_data_fall1_r1_reg ;\n wire \\gen_mux_rd[0].compare_data_fall2_r1_reg ;\n wire \\gen_mux_rd[0].compare_data_fall3_r1_reg ;\n wire \\gen_mux_rd[0].compare_data_rise0_r1_reg ;\n wire \\gen_mux_rd[0].compare_data_rise1_r1_reg ;\n wire \\gen_mux_rd[0].compare_data_rise2_r1_reg ;\n wire \\gen_mux_rd[0].compare_data_rise3_r1_reg ;\n wire \\gen_mux_rd[1].compare_data_fall0_r1_reg ;\n wire \\gen_mux_rd[1].compare_data_fall1_r1_reg ;\n wire \\gen_mux_rd[1].compare_data_fall2_r1_reg ;\n wire \\gen_mux_rd[1].compare_data_fall3_r1_reg ;\n wire \\gen_mux_rd[1].compare_data_rise0_r1_reg ;\n wire \\gen_mux_rd[1].compare_data_rise1_r1_reg ;\n wire \\gen_mux_rd[1].compare_data_rise2_r1_reg ;\n wire \\gen_mux_rd[1].compare_data_rise3_r1_reg ;\n wire \\gen_mux_rd[1].mux_rd_fall0_r1_reg ;\n wire \\gen_mux_rd[1].mux_rd_fall1_r1_reg ;\n wire \\gen_mux_rd[1].mux_rd_fall2_r1_reg ;\n wire \\gen_mux_rd[1].mux_rd_fall3_r1_reg ;\n wire \\gen_mux_rd[1].mux_rd_rise0_r1_reg ;\n wire \\gen_mux_rd[1].mux_rd_rise1_r1_reg ;\n wire \\gen_mux_rd[1].mux_rd_rise2_r1_reg ;\n wire \\gen_mux_rd[1].mux_rd_rise3_r1_reg ;\n wire \\gen_mux_rd[2].compare_data_fall0_r1_reg ;\n wire \\gen_mux_rd[2].compare_data_fall1_r1_reg ;\n wire \\gen_mux_rd[2].compare_data_fall2_r1_reg ;\n wire \\gen_mux_rd[2].compare_data_fall3_r1_reg ;\n wire \\gen_mux_rd[2].compare_data_rise0_r1_reg ;\n wire \\gen_mux_rd[2].compare_data_rise1_r1_reg ;\n wire \\gen_mux_rd[2].compare_data_rise2_r1_reg ;\n wire \\gen_mux_rd[2].compare_data_rise3_r1_reg ;\n wire \\gen_mux_rd[2].mux_rd_fall0_r1_reg ;\n wire \\gen_mux_rd[2].mux_rd_fall1_r1_reg ;\n wire \\gen_mux_rd[2].mux_rd_fall2_r1_reg ;\n wire \\gen_mux_rd[2].mux_rd_fall3_r1_reg ;\n wire \\gen_mux_rd[2].mux_rd_rise0_r1_reg ;\n wire \\gen_mux_rd[2].mux_rd_rise1_r1_reg ;\n wire \\gen_mux_rd[2].mux_rd_rise2_r1_reg ;\n wire \\gen_mux_rd[2].mux_rd_rise3_r1_reg ;\n wire \\gen_mux_rd[3].compare_data_fall0_r1_reg ;\n wire \\gen_mux_rd[3].compare_data_fall1_r1_reg ;\n wire \\gen_mux_rd[3].compare_data_fall2_r1_reg ;\n wire \\gen_mux_rd[3].compare_data_fall3_r1_reg ;\n wire \\gen_mux_rd[3].compare_data_rise0_r1_reg ;\n wire \\gen_mux_rd[3].compare_data_rise1_r1_reg ;\n wire \\gen_mux_rd[3].compare_data_rise2_r1_reg ;\n wire \\gen_mux_rd[3].compare_data_rise3_r1_reg ;\n wire \\gen_mux_rd[3].mux_rd_fall0_r1_reg ;\n wire \\gen_mux_rd[3].mux_rd_fall1_r1_reg ;\n wire \\gen_mux_rd[3].mux_rd_fall2_r1_reg ;\n wire \\gen_mux_rd[3].mux_rd_fall3_r1_reg ;\n wire \\gen_mux_rd[3].mux_rd_rise0_r1_reg ;\n wire \\gen_mux_rd[3].mux_rd_rise1_r1_reg ;\n wire \\gen_mux_rd[3].mux_rd_rise2_r1_reg ;\n wire \\gen_mux_rd[3].mux_rd_rise3_r1_reg ;\n wire \\gen_mux_rd[4].compare_data_fall0_r1_reg ;\n wire \\gen_mux_rd[4].compare_data_fall1_r1_reg ;\n wire \\gen_mux_rd[4].compare_data_fall2_r1_reg ;\n wire \\gen_mux_rd[4].compare_data_fall3_r1_reg ;\n wire \\gen_mux_rd[4].compare_data_rise0_r1_reg ;\n wire \\gen_mux_rd[4].compare_data_rise1_r1_reg ;\n wire \\gen_mux_rd[4].compare_data_rise2_r1_reg ;\n wire \\gen_mux_rd[4].compare_data_rise3_r1_reg ;\n wire \\gen_mux_rd[4].mux_rd_fall0_r1_reg ;\n wire \\gen_mux_rd[4].mux_rd_fall1_r1_reg ;\n wire \\gen_mux_rd[4].mux_rd_fall2_r1_reg ;\n wire \\gen_mux_rd[4].mux_rd_fall3_r1_reg ;\n wire \\gen_mux_rd[4].mux_rd_rise0_r1_reg ;\n wire \\gen_mux_rd[4].mux_rd_rise1_r1_reg ;\n wire \\gen_mux_rd[4].mux_rd_rise2_r1_reg ;\n wire \\gen_mux_rd[4].mux_rd_rise3_r1_reg ;\n wire \\gen_mux_rd[5].compare_data_fall0_r1_reg ;\n wire \\gen_mux_rd[5].compare_data_fall1_r1_reg ;\n wire \\gen_mux_rd[5].compare_data_fall2_r1_reg ;\n wire \\gen_mux_rd[5].compare_data_fall3_r1_reg ;\n wire \\gen_mux_rd[5].compare_data_rise0_r1_reg ;\n wire \\gen_mux_rd[5].compare_data_rise1_r1_reg ;\n wire \\gen_mux_rd[5].compare_data_rise2_r1_reg ;\n wire \\gen_mux_rd[5].compare_data_rise3_r1_reg ;\n wire \\gen_mux_rd[5].mux_rd_fall0_r1_reg ;\n wire \\gen_mux_rd[5].mux_rd_fall1_r1_reg ;\n wire \\gen_mux_rd[5].mux_rd_fall2_r1_reg ;\n wire \\gen_mux_rd[5].mux_rd_fall3_r1_reg ;\n wire \\gen_mux_rd[5].mux_rd_rise0_r1_reg ;\n wire \\gen_mux_rd[5].mux_rd_rise1_r1_reg ;\n wire \\gen_mux_rd[5].mux_rd_rise2_r1_reg ;\n wire \\gen_mux_rd[5].mux_rd_rise3_r1_reg ;\n wire \\gen_mux_rd[6].compare_data_fall0_r1_reg ;\n wire \\gen_mux_rd[6].compare_data_fall1_r1_reg ;\n wire \\gen_mux_rd[6].compare_data_fall2_r1_reg ;\n wire \\gen_mux_rd[6].compare_data_fall3_r1_reg ;\n wire \\gen_mux_rd[6].compare_data_rise0_r1_reg ;\n wire \\gen_mux_rd[6].compare_data_rise1_r1_reg ;\n wire \\gen_mux_rd[6].compare_data_rise2_r1_reg ;\n wire \\gen_mux_rd[6].compare_data_rise3_r1_reg ;\n wire \\gen_mux_rd[6].mux_rd_fall0_r1_reg ;\n wire \\gen_mux_rd[6].mux_rd_fall1_r1_reg ;\n wire \\gen_mux_rd[6].mux_rd_fall2_r1_reg ;\n wire \\gen_mux_rd[6].mux_rd_fall3_r1_reg ;\n wire \\gen_mux_rd[6].mux_rd_rise0_r1_reg ;\n wire \\gen_mux_rd[6].mux_rd_rise1_r1_reg ;\n wire \\gen_mux_rd[6].mux_rd_rise2_r1_reg ;\n wire \\gen_mux_rd[6].mux_rd_rise3_r1_reg ;\n wire \\gen_mux_rd[7].compare_data_fall0_r1_reg ;\n wire \\gen_mux_rd[7].compare_data_fall1_r1_reg ;\n wire \\gen_mux_rd[7].compare_data_fall2_r1_reg ;\n wire \\gen_mux_rd[7].compare_data_fall3_r1_reg ;\n wire \\gen_mux_rd[7].compare_data_rise0_r1_reg ;\n wire \\gen_mux_rd[7].compare_data_rise1_r1_reg ;\n wire \\gen_mux_rd[7].compare_data_rise2_r1_reg ;\n wire \\gen_mux_rd[7].compare_data_rise3_r1_reg ;\n wire \\gen_mux_rd[7].mux_rd_fall0_r1_reg ;\n wire \\gen_mux_rd[7].mux_rd_fall1_r1_reg ;\n wire \\gen_mux_rd[7].mux_rd_fall2_r1_reg ;\n wire \\gen_mux_rd[7].mux_rd_fall3_r1_reg ;\n wire \\gen_mux_rd[7].mux_rd_rise0_r1_reg ;\n wire \\gen_mux_rd[7].mux_rd_rise1_r1_reg ;\n wire \\gen_mux_rd[7].mux_rd_rise2_r1_reg ;\n wire \\gen_mux_rd[7].mux_rd_rise3_r1_reg ;\n wire \\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 ;\n wire \\genblk7[0].compare_err_pb_latch_r[0]_i_2_n_0 ;\n wire \\genblk7[0].compare_err_pb_latch_r_reg_n_0_[0] ;\n wire \\genblk7[1].compare_err_pb_latch_r[1]_i_1_n_0 ;\n wire \\genblk7[1].compare_err_pb_latch_r_reg_n_0_[1] ;\n wire \\genblk7[2].compare_err_pb_latch_r[2]_i_1_n_0 ;\n wire \\genblk7[2].compare_err_pb_latch_r_reg_n_0_[2] ;\n wire \\genblk7[3].compare_err_pb_latch_r[3]_i_1_n_0 ;\n wire \\genblk7[3].compare_err_pb_latch_r_reg_n_0_[3] ;\n wire \\genblk7[4].compare_err_pb_latch_r[4]_i_1_n_0 ;\n wire \\genblk7[4].compare_err_pb_latch_r_reg_n_0_[4] ;\n wire \\genblk7[5].compare_err_pb_latch_r[5]_i_1_n_0 ;\n wire \\genblk7[5].compare_err_pb_latch_r_reg_n_0_[5] ;\n wire \\genblk7[6].compare_err_pb_latch_r[6]_i_1_n_0 ;\n wire \\genblk7[6].compare_err_pb_latch_r_reg_n_0_[6] ;\n wire \\genblk7[7].compare_err_pb_latch_r[7]_i_1_n_0 ;\n wire \\genblk7[7].compare_err_pb_latch_r_reg_n_0_[7] ;\n wire \\genblk8[0].left_edge_found_pb_reg[0]_0 ;\n wire \\genblk8[0].left_edge_pb[0]_i_1_n_0 ;\n wire \\genblk8[0].left_edge_pb[1]_i_1_n_0 ;\n wire \\genblk8[0].left_edge_pb[2]_i_1_n_0 ;\n wire \\genblk8[0].left_edge_pb[3]_i_1_n_0 ;\n wire \\genblk8[0].left_edge_pb[4]_i_1_n_0 ;\n wire \\genblk8[0].left_edge_pb[5]_i_1_n_0 ;\n wire \\genblk8[0].left_edge_pb[5]_i_3_n_0 ;\n wire \\genblk8[0].left_edge_pb[5]_i_5_n_0 ;\n wire \\genblk8[0].left_edge_pb_reg_n_0_[0] ;\n wire \\genblk8[0].left_edge_pb_reg_n_0_[1] ;\n wire \\genblk8[0].left_edge_pb_reg_n_0_[2] ;\n wire \\genblk8[0].left_edge_pb_reg_n_0_[3] ;\n wire \\genblk8[0].left_edge_pb_reg_n_0_[4] ;\n wire \\genblk8[0].left_edge_pb_reg_n_0_[5] ;\n wire \\genblk8[0].left_edge_updated_reg[0]_0 ;\n wire \\genblk8[0].left_loss_pb[0]_i_1_n_0 ;\n wire \\genblk8[0].left_loss_pb[1]_i_1_n_0 ;\n wire \\genblk8[0].left_loss_pb[2]_i_1_n_0 ;\n wire \\genblk8[0].left_loss_pb[3]_i_1_n_0 ;\n wire \\genblk8[0].left_loss_pb[3]_i_3_n_0 ;\n wire \\genblk8[0].left_loss_pb[3]_i_4_n_0 ;\n wire \\genblk8[0].left_loss_pb[3]_i_5_n_0 ;\n wire \\genblk8[0].left_loss_pb[3]_i_6_n_0 ;\n wire \\genblk8[0].left_loss_pb[3]_i_7_n_0 ;\n wire \\genblk8[0].left_loss_pb[3]_i_8_n_0 ;\n wire \\genblk8[0].left_loss_pb[4]_i_1_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_10_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_11_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_12_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_13_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_15_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_16_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_17_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_18_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_1_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_20_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_21_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_22_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_23_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_24_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_25_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_26_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_27_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_28_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_29_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_2_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_30_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_31_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_7_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_8_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_9_n_0 ;\n wire \\genblk8[0].left_loss_pb_reg[0]_0 ;\n wire \\genblk8[0].left_loss_pb_reg[0]_1 ;\n wire \\genblk8[0].left_loss_pb_reg[3]_i_2_n_0 ;\n wire \\genblk8[0].left_loss_pb_reg[3]_i_2_n_1 ;\n wire \\genblk8[0].left_loss_pb_reg[3]_i_2_n_2 ;\n wire \\genblk8[0].left_loss_pb_reg[3]_i_2_n_3 ;\n wire \\genblk8[0].left_loss_pb_reg[3]_i_2_n_4 ;\n wire \\genblk8[0].left_loss_pb_reg[3]_i_2_n_5 ;\n wire \\genblk8[0].left_loss_pb_reg[3]_i_2_n_6 ;\n wire \\genblk8[0].left_loss_pb_reg[3]_i_2_n_7 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_14_n_0 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_14_n_1 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_14_n_2 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_14_n_3 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_19_n_0 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_19_n_1 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_19_n_2 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_19_n_3 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_4_n_0 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_4_n_1 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_4_n_2 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_4_n_3 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_5_n_3 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_5_n_6 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_5_n_7 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_6_n_0 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_6_n_1 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_6_n_2 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_6_n_3 ;\n wire [5:2]\\genblk8[0].left_loss_pb_reg__0 ;\n wire \\genblk8[0].left_loss_pb_reg_n_0_[0] ;\n wire \\genblk8[0].left_loss_pb_reg_n_0_[1] ;\n wire \\genblk8[0].match_flag_pb[7]_i_1_n_0 ;\n wire \\genblk8[0].right_edge_found_pb_reg[0]_0 ;\n wire \\genblk8[0].right_edge_pb[1]_i_1_n_0 ;\n wire \\genblk8[0].right_edge_pb[2]_i_1_n_0 ;\n wire \\genblk8[0].right_edge_pb[3]_i_1_n_0 ;\n wire \\genblk8[0].right_edge_pb[4]_i_1_n_0 ;\n wire \\genblk8[0].right_edge_pb[5]_i_1_n_0 ;\n wire \\genblk8[0].right_edge_pb[5]_i_2_n_0 ;\n wire \\genblk8[0].right_edge_pb[5]_i_3_n_0 ;\n wire \\genblk8[0].right_edge_pb_reg[0]_0 ;\n wire \\genblk8[0].right_edge_pb_reg[0]_1 ;\n wire \\genblk8[0].right_edge_pb_reg_n_0_[0] ;\n wire \\genblk8[0].right_edge_pb_reg_n_0_[1] ;\n wire \\genblk8[0].right_edge_pb_reg_n_0_[2] ;\n wire \\genblk8[0].right_edge_pb_reg_n_0_[3] ;\n wire \\genblk8[0].right_edge_pb_reg_n_0_[4] ;\n wire \\genblk8[0].right_edge_pb_reg_n_0_[5] ;\n wire \\genblk8[0].right_gain_pb[0]_i_1_n_0 ;\n wire \\genblk8[0].right_gain_pb[1]_i_1_n_0 ;\n wire \\genblk8[0].right_gain_pb[2]_i_1_n_0 ;\n wire \\genblk8[0].right_gain_pb[3]_i_10_n_0 ;\n wire \\genblk8[0].right_gain_pb[3]_i_11_n_0 ;\n wire \\genblk8[0].right_gain_pb[3]_i_1_n_0 ;\n wire \\genblk8[0].right_gain_pb[3]_i_4_n_0 ;\n wire \\genblk8[0].right_gain_pb[3]_i_5_n_0 ;\n wire \\genblk8[0].right_gain_pb[3]_i_6_n_0 ;\n wire \\genblk8[0].right_gain_pb[3]_i_7_n_0 ;\n wire \\genblk8[0].right_gain_pb[3]_i_8_n_0 ;\n wire \\genblk8[0].right_gain_pb[3]_i_9_n_0 ;\n wire \\genblk8[0].right_gain_pb[4]_i_1_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_11_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_12_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_13_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_14_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_15_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_16_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_17_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_18_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_19_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_1_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_20_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_23_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_24_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_25_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_26_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_27_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_28_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_2_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_30_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_31_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_32_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_33_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_35_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_36_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_37_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_38_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_3_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_40_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_41_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_42_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_43_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_44_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_45_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_46_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_47_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_48_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_49_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_50_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_52_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_53_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_54_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_55_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_56_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_57_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_58_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_59_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_60_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_61_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_62_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_8_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_9_n_0 ;\n wire \\genblk8[0].right_gain_pb_reg[3]_i_2_n_0 ;\n wire \\genblk8[0].right_gain_pb_reg[3]_i_2_n_1 ;\n wire \\genblk8[0].right_gain_pb_reg[3]_i_2_n_2 ;\n wire \\genblk8[0].right_gain_pb_reg[3]_i_2_n_3 ;\n wire \\genblk8[0].right_gain_pb_reg[3]_i_2_n_4 ;\n wire \\genblk8[0].right_gain_pb_reg[3]_i_2_n_5 ;\n wire \\genblk8[0].right_gain_pb_reg[3]_i_2_n_6 ;\n wire \\genblk8[0].right_gain_pb_reg[3]_i_2_n_7 ;\n wire \\genblk8[0].right_gain_pb_reg[3]_i_3_n_0 ;\n wire \\genblk8[0].right_gain_pb_reg[3]_i_3_n_1 ;\n wire \\genblk8[0].right_gain_pb_reg[3]_i_3_n_2 ;\n wire \\genblk8[0].right_gain_pb_reg[3]_i_3_n_3 ;\n wire \\genblk8[0].right_gain_pb_reg[3]_i_3_n_4 ;\n wire \\genblk8[0].right_gain_pb_reg[3]_i_3_n_5 ;\n wire \\genblk8[0].right_gain_pb_reg[3]_i_3_n_6 ;\n wire \\genblk8[0].right_gain_pb_reg[3]_i_3_n_7 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_10_n_0 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_10_n_1 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_10_n_2 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_10_n_3 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_21_n_0 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_21_n_1 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_21_n_2 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_21_n_3 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_22_n_0 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_22_n_1 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_22_n_2 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_22_n_3 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_29_n_0 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_29_n_1 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_29_n_2 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_29_n_3 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_34_n_0 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_34_n_1 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_34_n_2 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_34_n_3 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_39_n_0 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_39_n_1 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_39_n_2 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_39_n_3 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_4_n_0 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_51_n_0 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_51_n_1 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_51_n_2 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_51_n_3 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_5_n_1 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_5_n_2 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_5_n_3 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_6_n_3 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_6_n_6 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_6_n_7 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_7_n_3 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_7_n_6 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_7_n_7 ;\n wire [5:2]\\genblk8[0].right_gain_pb_reg__0 ;\n wire \\genblk8[0].right_gain_pb_reg_n_0_[0] ;\n wire \\genblk8[0].right_gain_pb_reg_n_0_[1] ;\n wire \\genblk8[1].left_edge_found_pb_reg[1]_0 ;\n wire \\genblk8[1].left_edge_pb[11]_i_1_n_0 ;\n wire \\genblk8[1].left_edge_pb[11]_i_3_n_0 ;\n wire \\genblk8[1].left_edge_pb_reg_n_0_[10] ;\n wire \\genblk8[1].left_edge_pb_reg_n_0_[11] ;\n wire \\genblk8[1].left_edge_pb_reg_n_0_[6] ;\n wire \\genblk8[1].left_edge_pb_reg_n_0_[7] ;\n wire \\genblk8[1].left_edge_pb_reg_n_0_[8] ;\n wire \\genblk8[1].left_edge_pb_reg_n_0_[9] ;\n wire \\genblk8[1].left_edge_updated_reg[1]_0 ;\n wire \\genblk8[1].left_loss_pb[11]_i_1_n_0 ;\n wire \\genblk8[1].left_loss_pb_reg[6]_0 ;\n wire [5:2]\\genblk8[1].left_loss_pb_reg__0 ;\n wire \\genblk8[1].left_loss_pb_reg_n_0_[6] ;\n wire \\genblk8[1].left_loss_pb_reg_n_0_[7] ;\n wire \\genblk8[1].right_edge_found_pb_reg[1]_0 ;\n wire \\genblk8[1].right_edge_pb[11]_i_1_n_0 ;\n wire \\genblk8[1].right_edge_pb[11]_i_2_n_0 ;\n wire \\genblk8[1].right_edge_pb_reg[6]_0 ;\n wire \\genblk8[1].right_edge_pb_reg_n_0_[10] ;\n wire \\genblk8[1].right_edge_pb_reg_n_0_[11] ;\n wire \\genblk8[1].right_edge_pb_reg_n_0_[6] ;\n wire \\genblk8[1].right_edge_pb_reg_n_0_[7] ;\n wire \\genblk8[1].right_edge_pb_reg_n_0_[8] ;\n wire \\genblk8[1].right_edge_pb_reg_n_0_[9] ;\n wire \\genblk8[1].right_gain_pb[10]_i_1_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_10_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_11_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_12_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_13_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_14_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_16_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_17_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_19_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_1_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_20_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_21_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_22_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_24_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_25_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_26_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_27_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_29_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_2_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_30_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_31_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_32_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_33_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_34_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_35_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_36_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_37_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_38_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_39_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_3_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_7_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_8_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_9_n_0 ;\n wire \\genblk8[1].right_gain_pb[6]_i_1_n_0 ;\n wire \\genblk8[1].right_gain_pb[7]_i_1_n_0 ;\n wire \\genblk8[1].right_gain_pb[8]_i_1_n_0 ;\n wire \\genblk8[1].right_gain_pb[9]_i_10_n_0 ;\n wire \\genblk8[1].right_gain_pb[9]_i_11_n_0 ;\n wire \\genblk8[1].right_gain_pb[9]_i_1_n_0 ;\n wire \\genblk8[1].right_gain_pb[9]_i_4_n_0 ;\n wire \\genblk8[1].right_gain_pb[9]_i_5_n_0 ;\n wire \\genblk8[1].right_gain_pb[9]_i_6_n_0 ;\n wire \\genblk8[1].right_gain_pb[9]_i_7_n_0 ;\n wire \\genblk8[1].right_gain_pb[9]_i_8_n_0 ;\n wire \\genblk8[1].right_gain_pb[9]_i_9_n_0 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_15_n_0 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_15_n_1 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_15_n_2 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_15_n_3 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_18_n_0 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_18_n_1 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_18_n_2 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_18_n_3 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_23_n_0 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_23_n_1 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_23_n_2 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_23_n_3 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_28_n_0 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_28_n_1 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_28_n_2 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_28_n_3 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_4_n_0 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_5_n_3 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_5_n_6 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_5_n_7 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_6_n_3 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_6_n_6 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_6_n_7 ;\n wire \\genblk8[1].right_gain_pb_reg[9]_i_2_n_0 ;\n wire \\genblk8[1].right_gain_pb_reg[9]_i_2_n_1 ;\n wire \\genblk8[1].right_gain_pb_reg[9]_i_2_n_2 ;\n wire \\genblk8[1].right_gain_pb_reg[9]_i_2_n_3 ;\n wire \\genblk8[1].right_gain_pb_reg[9]_i_2_n_4 ;\n wire \\genblk8[1].right_gain_pb_reg[9]_i_2_n_5 ;\n wire \\genblk8[1].right_gain_pb_reg[9]_i_2_n_6 ;\n wire \\genblk8[1].right_gain_pb_reg[9]_i_2_n_7 ;\n wire \\genblk8[1].right_gain_pb_reg[9]_i_3_n_0 ;\n wire \\genblk8[1].right_gain_pb_reg[9]_i_3_n_1 ;\n wire \\genblk8[1].right_gain_pb_reg[9]_i_3_n_2 ;\n wire \\genblk8[1].right_gain_pb_reg[9]_i_3_n_3 ;\n wire \\genblk8[1].right_gain_pb_reg[9]_i_3_n_4 ;\n wire \\genblk8[1].right_gain_pb_reg[9]_i_3_n_5 ;\n wire \\genblk8[1].right_gain_pb_reg[9]_i_3_n_6 ;\n wire \\genblk8[1].right_gain_pb_reg[9]_i_3_n_7 ;\n wire [5:2]\\genblk8[1].right_gain_pb_reg__0 ;\n wire \\genblk8[1].right_gain_pb_reg_n_0_[6] ;\n wire \\genblk8[1].right_gain_pb_reg_n_0_[7] ;\n wire \\genblk8[2].left_edge_found_pb_reg[2]_0 ;\n wire \\genblk8[2].left_edge_pb[17]_i_1_n_0 ;\n wire \\genblk8[2].left_edge_pb[17]_i_3_n_0 ;\n wire \\genblk8[2].left_edge_pb_reg_n_0_[12] ;\n wire \\genblk8[2].left_edge_pb_reg_n_0_[13] ;\n wire \\genblk8[2].left_edge_pb_reg_n_0_[14] ;\n wire \\genblk8[2].left_edge_pb_reg_n_0_[15] ;\n wire \\genblk8[2].left_edge_pb_reg_n_0_[16] ;\n wire \\genblk8[2].left_edge_pb_reg_n_0_[17] ;\n wire \\genblk8[2].left_edge_updated_reg[2]_0 ;\n wire \\genblk8[2].left_loss_pb[17]_i_1_n_0 ;\n wire \\genblk8[2].left_loss_pb_reg[12]_0 ;\n wire [5:2]\\genblk8[2].left_loss_pb_reg__0 ;\n wire \\genblk8[2].left_loss_pb_reg_n_0_[12] ;\n wire \\genblk8[2].left_loss_pb_reg_n_0_[13] ;\n wire \\genblk8[2].right_edge_found_pb_reg[2]_0 ;\n wire \\genblk8[2].right_edge_pb[17]_i_1_n_0 ;\n wire \\genblk8[2].right_edge_pb[17]_i_2_n_0 ;\n wire \\genblk8[2].right_edge_pb_reg[12]_0 ;\n wire \\genblk8[2].right_edge_pb_reg[12]_1 ;\n wire \\genblk8[2].right_edge_pb_reg[12]_2 ;\n wire \\genblk8[2].right_edge_pb_reg_n_0_[12] ;\n wire \\genblk8[2].right_edge_pb_reg_n_0_[13] ;\n wire \\genblk8[2].right_edge_pb_reg_n_0_[14] ;\n wire \\genblk8[2].right_edge_pb_reg_n_0_[15] ;\n wire \\genblk8[2].right_edge_pb_reg_n_0_[16] ;\n wire \\genblk8[2].right_edge_pb_reg_n_0_[17] ;\n wire \\genblk8[2].right_gain_pb[12]_i_1_n_0 ;\n wire \\genblk8[2].right_gain_pb[13]_i_1_n_0 ;\n wire \\genblk8[2].right_gain_pb[14]_i_1_n_0 ;\n wire \\genblk8[2].right_gain_pb[15]_i_10_n_0 ;\n wire \\genblk8[2].right_gain_pb[15]_i_11_n_0 ;\n wire \\genblk8[2].right_gain_pb[15]_i_1_n_0 ;\n wire \\genblk8[2].right_gain_pb[15]_i_4_n_0 ;\n wire \\genblk8[2].right_gain_pb[15]_i_5_n_0 ;\n wire \\genblk8[2].right_gain_pb[15]_i_6_n_0 ;\n wire \\genblk8[2].right_gain_pb[15]_i_7_n_0 ;\n wire \\genblk8[2].right_gain_pb[15]_i_8_n_0 ;\n wire \\genblk8[2].right_gain_pb[15]_i_9_n_0 ;\n wire \\genblk8[2].right_gain_pb[16]_i_1_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_10_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_11_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_12_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_13_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_14_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_16_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_17_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_19_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_1_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_20_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_21_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_22_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_24_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_25_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_26_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_27_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_29_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_2_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_30_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_31_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_32_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_33_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_34_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_35_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_36_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_37_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_38_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_39_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_3_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_7_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_8_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_9_n_0 ;\n wire \\genblk8[2].right_gain_pb_reg[15]_i_2_n_0 ;\n wire \\genblk8[2].right_gain_pb_reg[15]_i_2_n_1 ;\n wire \\genblk8[2].right_gain_pb_reg[15]_i_2_n_2 ;\n wire \\genblk8[2].right_gain_pb_reg[15]_i_2_n_3 ;\n wire \\genblk8[2].right_gain_pb_reg[15]_i_2_n_4 ;\n wire \\genblk8[2].right_gain_pb_reg[15]_i_2_n_5 ;\n wire \\genblk8[2].right_gain_pb_reg[15]_i_2_n_6 ;\n wire \\genblk8[2].right_gain_pb_reg[15]_i_2_n_7 ;\n wire \\genblk8[2].right_gain_pb_reg[15]_i_3_n_0 ;\n wire \\genblk8[2].right_gain_pb_reg[15]_i_3_n_1 ;\n wire \\genblk8[2].right_gain_pb_reg[15]_i_3_n_2 ;\n wire \\genblk8[2].right_gain_pb_reg[15]_i_3_n_3 ;\n wire \\genblk8[2].right_gain_pb_reg[15]_i_3_n_4 ;\n wire \\genblk8[2].right_gain_pb_reg[15]_i_3_n_5 ;\n wire \\genblk8[2].right_gain_pb_reg[15]_i_3_n_6 ;\n wire \\genblk8[2].right_gain_pb_reg[15]_i_3_n_7 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_15_n_0 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_15_n_1 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_15_n_2 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_15_n_3 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_18_n_0 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_18_n_1 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_18_n_2 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_18_n_3 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_23_n_0 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_23_n_1 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_23_n_2 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_23_n_3 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_28_n_0 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_28_n_1 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_28_n_2 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_28_n_3 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_4_n_0 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_5_n_3 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_5_n_6 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_5_n_7 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_6_n_3 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_6_n_6 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_6_n_7 ;\n wire [5:2]\\genblk8[2].right_gain_pb_reg__0 ;\n wire \\genblk8[2].right_gain_pb_reg_n_0_[12] ;\n wire \\genblk8[2].right_gain_pb_reg_n_0_[13] ;\n wire \\genblk8[3].left_edge_found_pb_reg[3]_0 ;\n wire \\genblk8[3].left_edge_pb[23]_i_1_n_0 ;\n wire \\genblk8[3].left_edge_pb[23]_i_3_n_0 ;\n wire \\genblk8[3].left_edge_pb_reg_n_0_[18] ;\n wire \\genblk8[3].left_edge_pb_reg_n_0_[19] ;\n wire \\genblk8[3].left_edge_pb_reg_n_0_[20] ;\n wire \\genblk8[3].left_edge_pb_reg_n_0_[21] ;\n wire \\genblk8[3].left_edge_pb_reg_n_0_[22] ;\n wire \\genblk8[3].left_edge_pb_reg_n_0_[23] ;\n wire \\genblk8[3].left_edge_updated_reg[3]_0 ;\n wire \\genblk8[3].left_loss_pb[23]_i_1_n_0 ;\n wire \\genblk8[3].left_loss_pb_reg[18]_0 ;\n wire [5:2]\\genblk8[3].left_loss_pb_reg__0 ;\n wire \\genblk8[3].left_loss_pb_reg_n_0_[18] ;\n wire \\genblk8[3].left_loss_pb_reg_n_0_[19] ;\n wire \\genblk8[3].right_edge_found_pb_reg[3]_0 ;\n wire \\genblk8[3].right_edge_pb[23]_i_1_n_0 ;\n wire \\genblk8[3].right_edge_pb[23]_i_2_n_0 ;\n wire \\genblk8[3].right_edge_pb_reg[18]_0 ;\n wire \\genblk8[3].right_edge_pb_reg_n_0_[18] ;\n wire \\genblk8[3].right_edge_pb_reg_n_0_[19] ;\n wire \\genblk8[3].right_edge_pb_reg_n_0_[20] ;\n wire \\genblk8[3].right_edge_pb_reg_n_0_[21] ;\n wire \\genblk8[3].right_edge_pb_reg_n_0_[22] ;\n wire \\genblk8[3].right_edge_pb_reg_n_0_[23] ;\n wire \\genblk8[3].right_gain_pb[18]_i_1_n_0 ;\n wire \\genblk8[3].right_gain_pb[19]_i_1_n_0 ;\n wire \\genblk8[3].right_gain_pb[20]_i_1_n_0 ;\n wire \\genblk8[3].right_gain_pb[21]_i_10_n_0 ;\n wire \\genblk8[3].right_gain_pb[21]_i_11_n_0 ;\n wire \\genblk8[3].right_gain_pb[21]_i_1_n_0 ;\n wire \\genblk8[3].right_gain_pb[21]_i_4_n_0 ;\n wire \\genblk8[3].right_gain_pb[21]_i_5_n_0 ;\n wire \\genblk8[3].right_gain_pb[21]_i_6_n_0 ;\n wire \\genblk8[3].right_gain_pb[21]_i_7_n_0 ;\n wire \\genblk8[3].right_gain_pb[21]_i_8_n_0 ;\n wire \\genblk8[3].right_gain_pb[21]_i_9_n_0 ;\n wire \\genblk8[3].right_gain_pb[22]_i_1_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_10_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_11_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_12_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_13_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_14_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_16_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_17_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_19_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_1_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_20_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_21_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_22_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_24_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_25_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_26_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_27_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_29_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_2_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_30_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_31_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_32_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_33_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_34_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_35_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_36_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_37_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_38_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_39_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_3_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_7_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_8_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_9_n_0 ;\n wire \\genblk8[3].right_gain_pb_reg[21]_i_2_n_0 ;\n wire \\genblk8[3].right_gain_pb_reg[21]_i_2_n_1 ;\n wire \\genblk8[3].right_gain_pb_reg[21]_i_2_n_2 ;\n wire \\genblk8[3].right_gain_pb_reg[21]_i_2_n_3 ;\n wire \\genblk8[3].right_gain_pb_reg[21]_i_2_n_4 ;\n wire \\genblk8[3].right_gain_pb_reg[21]_i_2_n_5 ;\n wire \\genblk8[3].right_gain_pb_reg[21]_i_2_n_6 ;\n wire \\genblk8[3].right_gain_pb_reg[21]_i_2_n_7 ;\n wire \\genblk8[3].right_gain_pb_reg[21]_i_3_n_0 ;\n wire \\genblk8[3].right_gain_pb_reg[21]_i_3_n_1 ;\n wire \\genblk8[3].right_gain_pb_reg[21]_i_3_n_2 ;\n wire \\genblk8[3].right_gain_pb_reg[21]_i_3_n_3 ;\n wire \\genblk8[3].right_gain_pb_reg[21]_i_3_n_4 ;\n wire \\genblk8[3].right_gain_pb_reg[21]_i_3_n_5 ;\n wire \\genblk8[3].right_gain_pb_reg[21]_i_3_n_6 ;\n wire \\genblk8[3].right_gain_pb_reg[21]_i_3_n_7 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_15_n_0 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_15_n_1 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_15_n_2 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_15_n_3 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_18_n_0 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_18_n_1 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_18_n_2 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_18_n_3 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_23_n_0 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_23_n_1 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_23_n_2 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_23_n_3 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_28_n_0 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_28_n_1 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_28_n_2 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_28_n_3 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_4_n_0 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_5_n_3 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_5_n_6 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_5_n_7 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_6_n_3 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_6_n_6 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_6_n_7 ;\n wire [5:2]\\genblk8[3].right_gain_pb_reg__0 ;\n wire \\genblk8[3].right_gain_pb_reg_n_0_[18] ;\n wire \\genblk8[3].right_gain_pb_reg_n_0_[19] ;\n wire \\genblk8[4].left_edge_found_pb_reg[4]_0 ;\n wire \\genblk8[4].left_edge_pb[29]_i_1_n_0 ;\n wire \\genblk8[4].left_edge_pb[29]_i_3_n_0 ;\n wire \\genblk8[4].left_edge_pb_reg_n_0_[24] ;\n wire \\genblk8[4].left_edge_pb_reg_n_0_[25] ;\n wire \\genblk8[4].left_edge_pb_reg_n_0_[26] ;\n wire \\genblk8[4].left_edge_pb_reg_n_0_[27] ;\n wire \\genblk8[4].left_edge_pb_reg_n_0_[28] ;\n wire \\genblk8[4].left_edge_pb_reg_n_0_[29] ;\n wire \\genblk8[4].left_edge_updated_reg[4]_0 ;\n wire \\genblk8[4].left_loss_pb[29]_i_1_n_0 ;\n wire \\genblk8[4].left_loss_pb_reg[24]_0 ;\n wire [5:2]\\genblk8[4].left_loss_pb_reg__0 ;\n wire \\genblk8[4].left_loss_pb_reg_n_0_[24] ;\n wire \\genblk8[4].left_loss_pb_reg_n_0_[25] ;\n wire \\genblk8[4].right_edge_found_pb_reg[4]_0 ;\n wire \\genblk8[4].right_edge_pb[29]_i_1_n_0 ;\n wire \\genblk8[4].right_edge_pb[29]_i_2_n_0 ;\n wire \\genblk8[4].right_edge_pb_reg[24]_0 ;\n wire \\genblk8[4].right_edge_pb_reg_n_0_[24] ;\n wire \\genblk8[4].right_edge_pb_reg_n_0_[25] ;\n wire \\genblk8[4].right_edge_pb_reg_n_0_[26] ;\n wire \\genblk8[4].right_edge_pb_reg_n_0_[27] ;\n wire \\genblk8[4].right_edge_pb_reg_n_0_[28] ;\n wire \\genblk8[4].right_edge_pb_reg_n_0_[29] ;\n wire \\genblk8[4].right_gain_pb[24]_i_1_n_0 ;\n wire \\genblk8[4].right_gain_pb[25]_i_1_n_0 ;\n wire \\genblk8[4].right_gain_pb[26]_i_1_n_0 ;\n wire \\genblk8[4].right_gain_pb[27]_i_10_n_0 ;\n wire \\genblk8[4].right_gain_pb[27]_i_11_n_0 ;\n wire \\genblk8[4].right_gain_pb[27]_i_1_n_0 ;\n wire \\genblk8[4].right_gain_pb[27]_i_4_n_0 ;\n wire \\genblk8[4].right_gain_pb[27]_i_5_n_0 ;\n wire \\genblk8[4].right_gain_pb[27]_i_6_n_0 ;\n wire \\genblk8[4].right_gain_pb[27]_i_7_n_0 ;\n wire \\genblk8[4].right_gain_pb[27]_i_8_n_0 ;\n wire \\genblk8[4].right_gain_pb[27]_i_9_n_0 ;\n wire \\genblk8[4].right_gain_pb[28]_i_1_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_10_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_11_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_12_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_13_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_14_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_16_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_17_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_19_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_1_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_20_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_21_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_22_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_24_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_25_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_26_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_27_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_29_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_2_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_30_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_31_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_32_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_33_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_34_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_35_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_36_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_37_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_38_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_39_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_3_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_7_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_8_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_9_n_0 ;\n wire \\genblk8[4].right_gain_pb_reg[27]_i_2_n_0 ;\n wire \\genblk8[4].right_gain_pb_reg[27]_i_2_n_1 ;\n wire \\genblk8[4].right_gain_pb_reg[27]_i_2_n_2 ;\n wire \\genblk8[4].right_gain_pb_reg[27]_i_2_n_3 ;\n wire \\genblk8[4].right_gain_pb_reg[27]_i_2_n_4 ;\n wire \\genblk8[4].right_gain_pb_reg[27]_i_2_n_5 ;\n wire \\genblk8[4].right_gain_pb_reg[27]_i_2_n_6 ;\n wire \\genblk8[4].right_gain_pb_reg[27]_i_2_n_7 ;\n wire \\genblk8[4].right_gain_pb_reg[27]_i_3_n_0 ;\n wire \\genblk8[4].right_gain_pb_reg[27]_i_3_n_1 ;\n wire \\genblk8[4].right_gain_pb_reg[27]_i_3_n_2 ;\n wire \\genblk8[4].right_gain_pb_reg[27]_i_3_n_3 ;\n wire \\genblk8[4].right_gain_pb_reg[27]_i_3_n_4 ;\n wire \\genblk8[4].right_gain_pb_reg[27]_i_3_n_5 ;\n wire \\genblk8[4].right_gain_pb_reg[27]_i_3_n_6 ;\n wire \\genblk8[4].right_gain_pb_reg[27]_i_3_n_7 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_15_n_0 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_15_n_1 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_15_n_2 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_15_n_3 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_18_n_0 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_18_n_1 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_18_n_2 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_18_n_3 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_23_n_0 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_23_n_1 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_23_n_2 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_23_n_3 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_28_n_0 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_28_n_1 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_28_n_2 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_28_n_3 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_4_n_0 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_5_n_3 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_5_n_6 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_5_n_7 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_6_n_3 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_6_n_6 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_6_n_7 ;\n wire [5:2]\\genblk8[4].right_gain_pb_reg__0 ;\n wire \\genblk8[4].right_gain_pb_reg_n_0_[24] ;\n wire \\genblk8[4].right_gain_pb_reg_n_0_[25] ;\n wire \\genblk8[5].left_edge_found_pb_reg[5]_0 ;\n wire \\genblk8[5].left_edge_pb[35]_i_1_n_0 ;\n wire \\genblk8[5].left_edge_pb[35]_i_3_n_0 ;\n wire \\genblk8[5].left_edge_pb_reg_n_0_[30] ;\n wire \\genblk8[5].left_edge_pb_reg_n_0_[31] ;\n wire \\genblk8[5].left_edge_pb_reg_n_0_[32] ;\n wire \\genblk8[5].left_edge_pb_reg_n_0_[33] ;\n wire \\genblk8[5].left_edge_pb_reg_n_0_[34] ;\n wire \\genblk8[5].left_edge_pb_reg_n_0_[35] ;\n wire \\genblk8[5].left_edge_updated_reg[5]_0 ;\n wire \\genblk8[5].left_loss_pb[35]_i_1_n_0 ;\n wire \\genblk8[5].left_loss_pb_reg[30]_0 ;\n wire [5:2]\\genblk8[5].left_loss_pb_reg__0 ;\n wire \\genblk8[5].left_loss_pb_reg_n_0_[30] ;\n wire \\genblk8[5].left_loss_pb_reg_n_0_[31] ;\n wire \\genblk8[5].right_edge_found_pb_reg[5]_0 ;\n wire \\genblk8[5].right_edge_pb[35]_i_1_n_0 ;\n wire \\genblk8[5].right_edge_pb[35]_i_2_n_0 ;\n wire \\genblk8[5].right_edge_pb_reg[30]_0 ;\n wire \\genblk8[5].right_edge_pb_reg[30]_1 ;\n wire \\genblk8[5].right_edge_pb_reg_n_0_[30] ;\n wire \\genblk8[5].right_edge_pb_reg_n_0_[31] ;\n wire \\genblk8[5].right_edge_pb_reg_n_0_[32] ;\n wire \\genblk8[5].right_edge_pb_reg_n_0_[33] ;\n wire \\genblk8[5].right_edge_pb_reg_n_0_[34] ;\n wire \\genblk8[5].right_edge_pb_reg_n_0_[35] ;\n wire \\genblk8[5].right_gain_pb[30]_i_1_n_0 ;\n wire \\genblk8[5].right_gain_pb[31]_i_1_n_0 ;\n wire \\genblk8[5].right_gain_pb[32]_i_1_n_0 ;\n wire \\genblk8[5].right_gain_pb[33]_i_10_n_0 ;\n wire \\genblk8[5].right_gain_pb[33]_i_11_n_0 ;\n wire \\genblk8[5].right_gain_pb[33]_i_1_n_0 ;\n wire \\genblk8[5].right_gain_pb[33]_i_4_n_0 ;\n wire \\genblk8[5].right_gain_pb[33]_i_5_n_0 ;\n wire \\genblk8[5].right_gain_pb[33]_i_6_n_0 ;\n wire \\genblk8[5].right_gain_pb[33]_i_7_n_0 ;\n wire \\genblk8[5].right_gain_pb[33]_i_8_n_0 ;\n wire \\genblk8[5].right_gain_pb[33]_i_9_n_0 ;\n wire \\genblk8[5].right_gain_pb[34]_i_1_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_10_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_11_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_12_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_13_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_14_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_16_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_17_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_19_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_1_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_20_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_21_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_22_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_24_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_25_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_26_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_27_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_29_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_2_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_30_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_31_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_32_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_33_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_34_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_35_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_36_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_37_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_38_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_39_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_3_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_7_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_8_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_9_n_0 ;\n wire \\genblk8[5].right_gain_pb_reg[30]_0 ;\n wire \\genblk8[5].right_gain_pb_reg[33]_i_2_n_0 ;\n wire \\genblk8[5].right_gain_pb_reg[33]_i_2_n_1 ;\n wire \\genblk8[5].right_gain_pb_reg[33]_i_2_n_2 ;\n wire \\genblk8[5].right_gain_pb_reg[33]_i_2_n_3 ;\n wire \\genblk8[5].right_gain_pb_reg[33]_i_2_n_4 ;\n wire \\genblk8[5].right_gain_pb_reg[33]_i_2_n_5 ;\n wire \\genblk8[5].right_gain_pb_reg[33]_i_2_n_6 ;\n wire \\genblk8[5].right_gain_pb_reg[33]_i_2_n_7 ;\n wire \\genblk8[5].right_gain_pb_reg[33]_i_3_n_0 ;\n wire \\genblk8[5].right_gain_pb_reg[33]_i_3_n_1 ;\n wire \\genblk8[5].right_gain_pb_reg[33]_i_3_n_2 ;\n wire \\genblk8[5].right_gain_pb_reg[33]_i_3_n_3 ;\n wire \\genblk8[5].right_gain_pb_reg[33]_i_3_n_4 ;\n wire \\genblk8[5].right_gain_pb_reg[33]_i_3_n_5 ;\n wire \\genblk8[5].right_gain_pb_reg[33]_i_3_n_6 ;\n wire \\genblk8[5].right_gain_pb_reg[33]_i_3_n_7 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_15_n_0 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_15_n_1 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_15_n_2 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_15_n_3 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_18_n_0 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_18_n_1 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_18_n_2 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_18_n_3 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_23_n_0 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_23_n_1 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_23_n_2 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_23_n_3 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_28_n_0 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_28_n_1 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_28_n_2 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_28_n_3 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_4_n_0 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_5_n_3 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_5_n_6 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_5_n_7 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_6_n_3 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_6_n_6 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_6_n_7 ;\n wire [5:2]\\genblk8[5].right_gain_pb_reg__0 ;\n wire \\genblk8[5].right_gain_pb_reg_n_0_[30] ;\n wire \\genblk8[5].right_gain_pb_reg_n_0_[31] ;\n wire \\genblk8[6].left_edge_found_pb_reg[6]_0 ;\n wire \\genblk8[6].left_edge_pb[41]_i_1_n_0 ;\n wire \\genblk8[6].left_edge_pb[41]_i_3_n_0 ;\n wire \\genblk8[6].left_edge_pb_reg_n_0_[36] ;\n wire \\genblk8[6].left_edge_pb_reg_n_0_[37] ;\n wire \\genblk8[6].left_edge_pb_reg_n_0_[38] ;\n wire \\genblk8[6].left_edge_pb_reg_n_0_[39] ;\n wire \\genblk8[6].left_edge_pb_reg_n_0_[40] ;\n wire \\genblk8[6].left_edge_pb_reg_n_0_[41] ;\n wire \\genblk8[6].left_edge_updated_reg[6]_0 ;\n wire \\genblk8[6].left_loss_pb[41]_i_1_n_0 ;\n wire \\genblk8[6].left_loss_pb_reg[36]_0 ;\n wire [5:2]\\genblk8[6].left_loss_pb_reg__0 ;\n wire \\genblk8[6].left_loss_pb_reg_n_0_[36] ;\n wire \\genblk8[6].left_loss_pb_reg_n_0_[37] ;\n wire \\genblk8[6].right_edge_found_pb_reg[6]_0 ;\n wire \\genblk8[6].right_edge_pb[41]_i_1_n_0 ;\n wire \\genblk8[6].right_edge_pb[41]_i_2_n_0 ;\n wire \\genblk8[6].right_edge_pb_reg[36]_0 ;\n wire \\genblk8[6].right_edge_pb_reg_n_0_[36] ;\n wire \\genblk8[6].right_edge_pb_reg_n_0_[37] ;\n wire \\genblk8[6].right_edge_pb_reg_n_0_[38] ;\n wire \\genblk8[6].right_edge_pb_reg_n_0_[39] ;\n wire \\genblk8[6].right_edge_pb_reg_n_0_[40] ;\n wire \\genblk8[6].right_edge_pb_reg_n_0_[41] ;\n wire \\genblk8[6].right_gain_pb[36]_i_1_n_0 ;\n wire \\genblk8[6].right_gain_pb[37]_i_1_n_0 ;\n wire \\genblk8[6].right_gain_pb[38]_i_1_n_0 ;\n wire \\genblk8[6].right_gain_pb[39]_i_10_n_0 ;\n wire \\genblk8[6].right_gain_pb[39]_i_11_n_0 ;\n wire \\genblk8[6].right_gain_pb[39]_i_1_n_0 ;\n wire \\genblk8[6].right_gain_pb[39]_i_4_n_0 ;\n wire \\genblk8[6].right_gain_pb[39]_i_5_n_0 ;\n wire \\genblk8[6].right_gain_pb[39]_i_6_n_0 ;\n wire \\genblk8[6].right_gain_pb[39]_i_7_n_0 ;\n wire \\genblk8[6].right_gain_pb[39]_i_8_n_0 ;\n wire \\genblk8[6].right_gain_pb[39]_i_9_n_0 ;\n wire \\genblk8[6].right_gain_pb[40]_i_1_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_10_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_11_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_12_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_13_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_14_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_16_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_17_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_19_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_1_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_20_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_21_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_22_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_24_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_25_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_26_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_27_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_29_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_2_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_30_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_31_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_32_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_33_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_34_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_35_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_36_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_37_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_38_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_39_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_3_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_7_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_8_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_9_n_0 ;\n wire \\genblk8[6].right_gain_pb_reg[39]_i_2_n_0 ;\n wire \\genblk8[6].right_gain_pb_reg[39]_i_2_n_1 ;\n wire \\genblk8[6].right_gain_pb_reg[39]_i_2_n_2 ;\n wire \\genblk8[6].right_gain_pb_reg[39]_i_2_n_3 ;\n wire \\genblk8[6].right_gain_pb_reg[39]_i_2_n_4 ;\n wire \\genblk8[6].right_gain_pb_reg[39]_i_2_n_5 ;\n wire \\genblk8[6].right_gain_pb_reg[39]_i_2_n_6 ;\n wire \\genblk8[6].right_gain_pb_reg[39]_i_2_n_7 ;\n wire \\genblk8[6].right_gain_pb_reg[39]_i_3_n_0 ;\n wire \\genblk8[6].right_gain_pb_reg[39]_i_3_n_1 ;\n wire \\genblk8[6].right_gain_pb_reg[39]_i_3_n_2 ;\n wire \\genblk8[6].right_gain_pb_reg[39]_i_3_n_3 ;\n wire \\genblk8[6].right_gain_pb_reg[39]_i_3_n_4 ;\n wire \\genblk8[6].right_gain_pb_reg[39]_i_3_n_5 ;\n wire \\genblk8[6].right_gain_pb_reg[39]_i_3_n_6 ;\n wire \\genblk8[6].right_gain_pb_reg[39]_i_3_n_7 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_15_n_0 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_15_n_1 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_15_n_2 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_15_n_3 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_18_n_0 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_18_n_1 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_18_n_2 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_18_n_3 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_23_n_0 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_23_n_1 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_23_n_2 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_23_n_3 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_28_n_0 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_28_n_1 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_28_n_2 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_28_n_3 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_4_n_0 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_5_n_3 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_5_n_6 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_5_n_7 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_6_n_3 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_6_n_6 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_6_n_7 ;\n wire [5:2]\\genblk8[6].right_gain_pb_reg__0 ;\n wire \\genblk8[6].right_gain_pb_reg_n_0_[36] ;\n wire \\genblk8[6].right_gain_pb_reg_n_0_[37] ;\n wire \\genblk8[7].left_edge_found_pb_reg[7]_0 ;\n wire \\genblk8[7].left_edge_pb[47]_i_1_n_0 ;\n wire \\genblk8[7].left_edge_pb[47]_i_3_n_0 ;\n wire \\genblk8[7].left_edge_pb_reg_n_0_[42] ;\n wire \\genblk8[7].left_edge_pb_reg_n_0_[43] ;\n wire \\genblk8[7].left_edge_pb_reg_n_0_[44] ;\n wire \\genblk8[7].left_edge_pb_reg_n_0_[45] ;\n wire \\genblk8[7].left_edge_pb_reg_n_0_[46] ;\n wire \\genblk8[7].left_edge_pb_reg_n_0_[47] ;\n wire \\genblk8[7].left_edge_updated_reg[7]_0 ;\n wire \\genblk8[7].left_edge_updated_reg[7]_1 ;\n wire \\genblk8[7].left_loss_pb[47]_i_1_n_0 ;\n wire \\genblk8[7].left_loss_pb_reg[42]_0 ;\n wire [5:2]\\genblk8[7].left_loss_pb_reg__0 ;\n wire \\genblk8[7].left_loss_pb_reg_n_0_[42] ;\n wire \\genblk8[7].left_loss_pb_reg_n_0_[43] ;\n wire \\genblk8[7].right_edge_found_pb_reg[7]_0 ;\n wire \\genblk8[7].right_edge_pb[47]_i_1_n_0 ;\n wire \\genblk8[7].right_edge_pb[47]_i_2_n_0 ;\n wire \\genblk8[7].right_edge_pb_reg[42]_0 ;\n wire \\genblk8[7].right_edge_pb_reg[42]_1 ;\n wire \\genblk8[7].right_edge_pb_reg_n_0_[42] ;\n wire \\genblk8[7].right_edge_pb_reg_n_0_[43] ;\n wire \\genblk8[7].right_edge_pb_reg_n_0_[44] ;\n wire \\genblk8[7].right_edge_pb_reg_n_0_[45] ;\n wire \\genblk8[7].right_edge_pb_reg_n_0_[46] ;\n wire \\genblk8[7].right_edge_pb_reg_n_0_[47] ;\n wire \\genblk8[7].right_gain_pb[42]_i_1_n_0 ;\n wire \\genblk8[7].right_gain_pb[43]_i_1_n_0 ;\n wire \\genblk8[7].right_gain_pb[44]_i_1_n_0 ;\n wire \\genblk8[7].right_gain_pb[45]_i_10_n_0 ;\n wire \\genblk8[7].right_gain_pb[45]_i_11_n_0 ;\n wire \\genblk8[7].right_gain_pb[45]_i_1_n_0 ;\n wire \\genblk8[7].right_gain_pb[45]_i_4_n_0 ;\n wire \\genblk8[7].right_gain_pb[45]_i_5_n_0 ;\n wire \\genblk8[7].right_gain_pb[45]_i_6_n_0 ;\n wire \\genblk8[7].right_gain_pb[45]_i_7_n_0 ;\n wire \\genblk8[7].right_gain_pb[45]_i_8_n_0 ;\n wire \\genblk8[7].right_gain_pb[45]_i_9_n_0 ;\n wire \\genblk8[7].right_gain_pb[46]_i_1_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_10_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_11_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_12_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_13_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_14_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_16_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_17_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_19_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_1_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_20_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_21_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_22_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_24_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_25_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_26_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_27_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_29_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_2_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_30_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_31_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_32_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_33_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_34_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_35_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_36_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_37_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_38_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_39_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_3_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_7_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_8_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_9_n_0 ;\n wire \\genblk8[7].right_gain_pb_reg[45]_i_2_n_0 ;\n wire \\genblk8[7].right_gain_pb_reg[45]_i_2_n_1 ;\n wire \\genblk8[7].right_gain_pb_reg[45]_i_2_n_2 ;\n wire \\genblk8[7].right_gain_pb_reg[45]_i_2_n_3 ;\n wire \\genblk8[7].right_gain_pb_reg[45]_i_2_n_4 ;\n wire \\genblk8[7].right_gain_pb_reg[45]_i_2_n_5 ;\n wire \\genblk8[7].right_gain_pb_reg[45]_i_2_n_6 ;\n wire \\genblk8[7].right_gain_pb_reg[45]_i_2_n_7 ;\n wire \\genblk8[7].right_gain_pb_reg[45]_i_3_n_0 ;\n wire \\genblk8[7].right_gain_pb_reg[45]_i_3_n_1 ;\n wire \\genblk8[7].right_gain_pb_reg[45]_i_3_n_2 ;\n wire \\genblk8[7].right_gain_pb_reg[45]_i_3_n_3 ;\n wire \\genblk8[7].right_gain_pb_reg[45]_i_3_n_4 ;\n wire \\genblk8[7].right_gain_pb_reg[45]_i_3_n_5 ;\n wire \\genblk8[7].right_gain_pb_reg[45]_i_3_n_6 ;\n wire \\genblk8[7].right_gain_pb_reg[45]_i_3_n_7 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_15_n_0 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_15_n_1 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_15_n_2 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_15_n_3 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_18_n_0 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_18_n_1 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_18_n_2 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_18_n_3 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_23_n_0 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_23_n_1 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_23_n_2 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_23_n_3 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_28_n_0 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_28_n_1 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_28_n_2 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_28_n_3 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_4_n_0 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_5_n_3 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_5_n_6 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_5_n_7 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_6_n_3 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_6_n_6 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_6_n_7 ;\n wire [5:2]\\genblk8[7].right_gain_pb_reg__0 ;\n wire \\genblk8[7].right_gain_pb_reg_n_0_[42] ;\n wire \\genblk8[7].right_gain_pb_reg_n_0_[43] ;\n wire \\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ;\n wire \\genblk9[0].fine_delay_incdec_pb[0]_i_11_n_0 ;\n wire \\genblk9[0].fine_delay_incdec_pb[0]_i_1_n_0 ;\n wire \\genblk9[0].fine_delay_incdec_pb[0]_i_2_n_0 ;\n wire \\genblk9[0].fine_delay_incdec_pb[0]_i_4_n_0 ;\n wire \\genblk9[0].fine_delay_incdec_pb[0]_i_5_n_0 ;\n wire \\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ;\n wire \\genblk9[0].fine_delay_incdec_pb[0]_i_9_n_0 ;\n wire \\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ;\n wire \\genblk9[1].fine_delay_incdec_pb[1]_i_1_n_0 ;\n wire \\genblk9[1].fine_delay_incdec_pb[1]_i_2_n_0 ;\n wire \\genblk9[1].fine_delay_incdec_pb[1]_i_3_n_0 ;\n wire \\genblk9[1].fine_delay_incdec_pb[1]_i_4_n_0 ;\n wire \\genblk9[1].fine_delay_incdec_pb[1]_i_5_n_0 ;\n wire \\genblk9[1].fine_delay_incdec_pb_reg[1]_0 ;\n wire \\genblk9[2].fine_delay_incdec_pb[2]_i_1_n_0 ;\n wire \\genblk9[2].fine_delay_incdec_pb[2]_i_2_n_0 ;\n wire \\genblk9[2].fine_delay_incdec_pb[2]_i_3_n_0 ;\n wire \\genblk9[2].fine_delay_incdec_pb[2]_i_4_n_0 ;\n wire \\genblk9[2].fine_delay_incdec_pb[2]_i_5_n_0 ;\n wire \\genblk9[2].fine_delay_incdec_pb_reg[2]_0 ;\n wire \\genblk9[3].fine_delay_incdec_pb[3]_i_1_n_0 ;\n wire \\genblk9[3].fine_delay_incdec_pb[3]_i_2_n_0 ;\n wire \\genblk9[3].fine_delay_incdec_pb[3]_i_3_n_0 ;\n wire \\genblk9[3].fine_delay_incdec_pb[3]_i_4_n_0 ;\n wire \\genblk9[3].fine_delay_incdec_pb[3]_i_5_n_0 ;\n wire \\genblk9[3].fine_delay_incdec_pb_reg[3]_0 ;\n wire \\genblk9[4].fine_delay_incdec_pb[4]_i_1_n_0 ;\n wire \\genblk9[4].fine_delay_incdec_pb[4]_i_2_n_0 ;\n wire \\genblk9[4].fine_delay_incdec_pb[4]_i_3_n_0 ;\n wire \\genblk9[4].fine_delay_incdec_pb[4]_i_4_n_0 ;\n wire \\genblk9[4].fine_delay_incdec_pb[4]_i_5_n_0 ;\n wire \\genblk9[5].fine_delay_incdec_pb[5]_i_1_n_0 ;\n wire \\genblk9[5].fine_delay_incdec_pb[5]_i_2_n_0 ;\n wire \\genblk9[5].fine_delay_incdec_pb[5]_i_3_n_0 ;\n wire \\genblk9[5].fine_delay_incdec_pb[5]_i_4_n_0 ;\n wire \\genblk9[5].fine_delay_incdec_pb[5]_i_5_n_0 ;\n wire \\genblk9[5].fine_delay_incdec_pb_reg[5]_0 ;\n wire \\genblk9[6].fine_delay_incdec_pb[6]_i_1_n_0 ;\n wire \\genblk9[6].fine_delay_incdec_pb[6]_i_2_n_0 ;\n wire \\genblk9[6].fine_delay_incdec_pb[6]_i_3_n_0 ;\n wire \\genblk9[6].fine_delay_incdec_pb[6]_i_4_n_0 ;\n wire \\genblk9[6].fine_delay_incdec_pb[6]_i_5_n_0 ;\n wire \\genblk9[6].fine_delay_incdec_pb_reg[6]_0 ;\n wire \\genblk9[7].fine_delay_incdec_pb[7]_i_1_n_0 ;\n wire \\genblk9[7].fine_delay_incdec_pb[7]_i_2_n_0 ;\n wire \\genblk9[7].fine_delay_incdec_pb[7]_i_3_n_0 ;\n wire \\genblk9[7].fine_delay_incdec_pb[7]_i_4_n_0 ;\n wire \\genblk9[7].fine_delay_incdec_pb[7]_i_5_n_0 ;\n wire \\genblk9[7].fine_delay_incdec_pb_reg[7]_0 ;\n wire \\init_state_r_reg[0] ;\n wire \\init_state_r_reg[0]_0 ;\n wire \\init_state_r_reg[1] ;\n wire \\init_state_r_reg[1]_0 ;\n wire \\largest_left_edge[0]_i_1_n_0 ;\n wire \\largest_left_edge[1]_i_1_n_0 ;\n wire \\largest_left_edge[2]_i_1_n_0 ;\n wire \\largest_left_edge[3]_i_1_n_0 ;\n wire \\largest_left_edge[4]_i_1_n_0 ;\n wire \\largest_left_edge[5]_i_1_n_0 ;\n wire \\largest_left_edge[5]_i_2_n_0 ;\n wire \\largest_left_edge[5]_i_4_n_0 ;\n wire \\largest_left_edge[5]_i_5_n_0 ;\n wire \\largest_left_edge[5]_i_6_n_0 ;\n wire \\largest_left_edge_reg[0]_0 ;\n wire \\largest_left_edge_reg_n_0_[0] ;\n wire \\largest_left_edge_reg_n_0_[1] ;\n wire \\largest_left_edge_reg_n_0_[2] ;\n wire \\largest_left_edge_reg_n_0_[3] ;\n wire \\largest_left_edge_reg_n_0_[4] ;\n wire \\largest_left_edge_reg_n_0_[5] ;\n wire left_edge_pb;\n wire [5:0]left_edge_ref;\n wire \\left_edge_ref[0]_i_1_n_0 ;\n wire \\left_edge_ref[0]_i_2_n_0 ;\n wire \\left_edge_ref[0]_i_3_n_0 ;\n wire \\left_edge_ref[1]_i_1_n_0 ;\n wire \\left_edge_ref[1]_i_2_n_0 ;\n wire \\left_edge_ref[1]_i_3_n_0 ;\n wire \\left_edge_ref[2]_i_1_n_0 ;\n wire \\left_edge_ref[2]_i_2_n_0 ;\n wire \\left_edge_ref[2]_i_3_n_0 ;\n wire \\left_edge_ref[3]_i_1_n_0 ;\n wire \\left_edge_ref[3]_i_2_n_0 ;\n wire \\left_edge_ref[3]_i_3_n_0 ;\n wire \\left_edge_ref[4]_i_11_n_0 ;\n wire \\left_edge_ref[4]_i_12_n_0 ;\n wire \\left_edge_ref[4]_i_1_n_0 ;\n wire \\left_edge_ref[4]_i_2_n_0 ;\n wire \\left_edge_ref[4]_i_4_n_0 ;\n wire \\left_edge_ref[4]_i_5_n_0 ;\n wire \\left_edge_ref[4]_i_6_n_0 ;\n wire \\left_edge_ref[4]_i_7_n_0 ;\n wire \\left_edge_ref[4]_i_8_n_0 ;\n wire \\left_edge_ref[4]_i_9_n_0 ;\n wire \\left_edge_ref[5]_i_10_n_0 ;\n wire \\left_edge_ref[5]_i_11_n_0 ;\n wire \\left_edge_ref[5]_i_12_n_0 ;\n wire \\left_edge_ref[5]_i_13_n_0 ;\n wire \\left_edge_ref[5]_i_14_n_0 ;\n wire \\left_edge_ref[5]_i_15_n_0 ;\n wire \\left_edge_ref[5]_i_17_n_0 ;\n wire \\left_edge_ref[5]_i_18_n_0 ;\n wire \\left_edge_ref[5]_i_19_n_0 ;\n wire \\left_edge_ref[5]_i_1_n_0 ;\n wire \\left_edge_ref[5]_i_2_n_0 ;\n wire \\left_edge_ref[5]_i_5_n_0 ;\n wire \\left_edge_ref[5]_i_7_n_0 ;\n wire \\left_edge_ref[5]_i_8_n_0 ;\n wire \\left_edge_ref[5]_i_9_n_0 ;\n wire \\left_edge_ref_reg[4]_i_10_n_0 ;\n wire \\left_edge_ref_reg[4]_i_3_n_0 ;\n wire \\left_edge_ref_reg[5]_i_16_n_0 ;\n wire \\left_edge_ref_reg[5]_i_3_n_0 ;\n wire \\left_edge_ref_reg[5]_i_3_n_1 ;\n wire \\left_edge_ref_reg[5]_i_3_n_2 ;\n wire \\left_edge_ref_reg[5]_i_3_n_3 ;\n wire \\left_edge_ref_reg[5]_i_3_n_4 ;\n wire \\left_edge_ref_reg[5]_i_3_n_5 ;\n wire \\left_edge_ref_reg[5]_i_3_n_6 ;\n wire \\left_edge_ref_reg[5]_i_3_n_7 ;\n wire \\left_edge_ref_reg[5]_i_4_n_0 ;\n wire \\left_edge_ref_reg[5]_i_6_n_7 ;\n wire match_flag_and;\n wire \\match_flag_and[0]_i_1_n_0 ;\n wire \\match_flag_and[1]_i_1_n_0 ;\n wire \\match_flag_and[2]_i_1_n_0 ;\n wire \\match_flag_and[3]_i_1_n_0 ;\n wire \\match_flag_and[4]_i_1_n_0 ;\n wire \\match_flag_and[5]_i_1_n_0 ;\n wire \\match_flag_and[6]_i_1_n_0 ;\n wire \\match_flag_and[7]_i_2_n_0 ;\n wire \\match_flag_and[7]_i_3_n_0 ;\n wire \\match_flag_and_reg_n_0_[0] ;\n wire \\match_flag_and_reg_n_0_[1] ;\n wire \\match_flag_and_reg_n_0_[2] ;\n wire \\match_flag_and_reg_n_0_[3] ;\n wire \\match_flag_and_reg_n_0_[4] ;\n wire \\match_flag_and_reg_n_0_[5] ;\n wire \\match_flag_and_reg_n_0_[6] ;\n wire \\match_flag_and_reg_n_0_[7] ;\n wire \\match_flag_or[0]_i_1_n_0 ;\n wire \\match_flag_or[1]_i_1_n_0 ;\n wire \\match_flag_or[2]_i_1_n_0 ;\n wire \\match_flag_or[3]_i_1_n_0 ;\n wire \\match_flag_or[4]_i_1_n_0 ;\n wire \\match_flag_or[5]_i_1_n_0 ;\n wire \\match_flag_or[6]_i_1_n_0 ;\n wire \\match_flag_or_reg[0]_0 ;\n wire [63:0]match_flag_pb;\n wire mux_rd_fall0_r1;\n wire mux_rd_fall0_r2;\n wire mux_rd_fall1_r1;\n wire mux_rd_fall1_r2;\n wire mux_rd_fall2_r1;\n wire mux_rd_fall2_r2;\n wire mux_rd_fall3_r1;\n wire mux_rd_fall3_r2;\n wire mux_rd_rise0_r1;\n wire mux_rd_rise0_r2;\n wire mux_rd_rise1_r1;\n wire mux_rd_rise1_r2;\n wire mux_rd_rise2_r1;\n wire mux_rd_rise2_r2;\n wire mux_rd_rise3_r1;\n wire mux_rd_rise3_r2;\n wire mux_rd_valid_r;\n wire new_cnt_dqs_r;\n wire new_cnt_dqs_r_reg_0;\n wire new_cnt_dqs_r_reg_1;\n wire no_err_win_detected_i_1_n_0;\n wire no_err_win_detected_i_2_n_0;\n wire no_err_win_detected_i_3_n_0;\n wire no_err_win_detected_latch_reg_0;\n wire no_err_win_detected_latch_reg_1;\n wire no_err_win_detected_reg_0;\n wire no_err_win_detected_reg_1;\n wire \\num_refresh_reg[1] ;\n wire num_samples_done_ind_reg_0;\n wire num_samples_done_r;\n wire ocal_last_byte_done;\n wire oclkdelay_center_calib_done_r_reg;\n wire \\oclkdelay_ref_cnt_reg[0] ;\n wire \\one_rank.stg1_wr_done_reg ;\n wire [3:0]p_0_in;\n wire [7:0]p_0_in__0;\n wire p_103_out;\n wire p_106_out;\n wire p_10_out;\n wire p_119_out;\n wire p_122_out;\n wire p_127_out;\n wire p_130_out;\n wire p_143_out;\n wire p_146_out;\n wire p_154_out;\n wire p_19_out;\n wire p_1_in159_in;\n wire p_28_out;\n wire p_37_out;\n wire [0:0]p_3_in;\n wire p_46_out;\n wire p_55_out;\n wire p_64_out;\n wire p_66_out;\n wire p_75_out;\n wire p_95_out;\n wire p_98_out;\n wire [3:0]\\pi_counter_read_val_reg[5] ;\n wire pi_en_stg2_f_timing;\n wire pi_en_stg2_f_timing_reg_0;\n wire pi_stg2_f_incdec_timing;\n wire [5:0]prbs_dec_tap_cnt;\n wire \\prbs_dec_tap_cnt[0]_i_1_n_0 ;\n wire \\prbs_dec_tap_cnt[1]_i_1_n_0 ;\n wire \\prbs_dec_tap_cnt[2]_i_1_n_0 ;\n wire \\prbs_dec_tap_cnt[2]_i_2_n_0 ;\n wire \\prbs_dec_tap_cnt[2]_i_3_n_0 ;\n wire \\prbs_dec_tap_cnt[2]_i_4_n_0 ;\n wire \\prbs_dec_tap_cnt[3]_i_1_n_0 ;\n wire \\prbs_dec_tap_cnt[3]_i_2_n_0 ;\n wire \\prbs_dec_tap_cnt[4]_i_2_n_0 ;\n wire \\prbs_dec_tap_cnt[4]_i_3_n_0 ;\n wire \\prbs_dec_tap_cnt[5]_i_1_n_0 ;\n wire \\prbs_dec_tap_cnt[5]_i_4_n_0 ;\n wire \\prbs_dec_tap_cnt[5]_i_5_n_0 ;\n wire [1:0]\\prbs_dec_tap_cnt_reg[1]_0 ;\n wire \\prbs_dec_tap_cnt_reg[4]_i_1_n_0 ;\n wire \\prbs_dec_tap_cnt_reg[5]_i_2_n_0 ;\n wire \\prbs_dqs_cnt_r_reg[0]_0 ;\n wire \\prbs_dqs_cnt_r_reg[0]_1 ;\n wire \\prbs_dqs_cnt_r_reg[0]_2 ;\n wire \\prbs_dqs_cnt_r_reg[1]_0 ;\n wire \\prbs_dqs_cnt_r_reg[2]_0 ;\n wire \\prbs_dqs_tap_cnt_r[0]_i_1_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[0]_rep__0_i_1_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[0]_rep_i_1_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[1]_i_1_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[1]_rep__0_i_1_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[1]_rep_i_1_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[2]_i_1_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[3]_i_1_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[3]_i_2_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[3]_i_3_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[3]_rep__0_i_1_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[3]_rep_i_1_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[4]_i_1_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[4]_i_2_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[5]_i_2_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[5]_i_3_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[5]_i_4_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ;\n wire \\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ;\n wire \\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ;\n wire \\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ;\n wire \\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ;\n wire \\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ;\n wire \\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ;\n wire \\prbs_dqs_tap_cnt_r_reg_n_0_[0] ;\n wire \\prbs_dqs_tap_cnt_r_reg_n_0_[1] ;\n wire \\prbs_dqs_tap_cnt_r_reg_n_0_[2] ;\n wire \\prbs_dqs_tap_cnt_r_reg_n_0_[3] ;\n wire \\prbs_dqs_tap_cnt_r_reg_n_0_[4] ;\n wire \\prbs_dqs_tap_cnt_r_reg_n_0_[5] ;\n wire prbs_dqs_tap_limit_r;\n wire prbs_found_1st_edge_r_i_5_n_0;\n wire prbs_found_1st_edge_r_reg_0;\n wire prbs_found_1st_edge_r_reg_1;\n wire \\prbs_inc_tap_cnt[0]_i_1_n_0 ;\n wire \\prbs_inc_tap_cnt[1]_i_1_n_0 ;\n wire \\prbs_inc_tap_cnt[1]_i_2_n_0 ;\n wire \\prbs_inc_tap_cnt[2]_i_1_n_0 ;\n wire \\prbs_inc_tap_cnt[2]_i_2_n_0 ;\n wire \\prbs_inc_tap_cnt[2]_i_3_n_0 ;\n wire \\prbs_inc_tap_cnt[3]_i_1_n_0 ;\n wire \\prbs_inc_tap_cnt[3]_i_2_n_0 ;\n wire \\prbs_inc_tap_cnt[3]_i_3_n_0 ;\n wire \\prbs_inc_tap_cnt[3]_i_4_n_0 ;\n wire \\prbs_inc_tap_cnt[4]_i_1_n_0 ;\n wire \\prbs_inc_tap_cnt[4]_i_2_n_0 ;\n wire \\prbs_inc_tap_cnt[5]_i_1_n_0 ;\n wire \\prbs_inc_tap_cnt[5]_i_2_n_0 ;\n wire \\prbs_inc_tap_cnt[5]_i_3_n_0 ;\n wire \\prbs_inc_tap_cnt[5]_i_4_n_0 ;\n wire \\prbs_inc_tap_cnt[5]_i_5_n_0 ;\n wire \\prbs_inc_tap_cnt[5]_i_6_n_0 ;\n wire \\prbs_inc_tap_cnt[5]_i_7_n_0 ;\n wire \\prbs_inc_tap_cnt[5]_i_8_n_0 ;\n wire \\prbs_inc_tap_cnt[5]_i_9_n_0 ;\n wire \\prbs_inc_tap_cnt_reg_n_0_[0] ;\n wire \\prbs_inc_tap_cnt_reg_n_0_[1] ;\n wire \\prbs_inc_tap_cnt_reg_n_0_[2] ;\n wire \\prbs_inc_tap_cnt_reg_n_0_[3] ;\n wire \\prbs_inc_tap_cnt_reg_n_0_[4] ;\n wire \\prbs_inc_tap_cnt_reg_n_0_[5] ;\n wire prbs_last_byte_done;\n wire prbs_last_byte_done_reg_0;\n wire prbs_pi_stg2_f_en;\n wire prbs_pi_stg2_f_incdec;\n wire prbs_prech_req_r;\n wire prbs_rdlvl_done_pulse0;\n wire prbs_rdlvl_done_r1;\n wire prbs_rdlvl_done_reg_0;\n wire prbs_rdlvl_done_reg_1;\n wire prbs_rdlvl_start_r;\n wire prbs_rdlvl_start_reg;\n wire prbs_rdlvl_start_reg_0;\n wire prbs_state_r1;\n wire prbs_state_r178_out;\n wire \\prbs_state_r[0]_i_1_n_0 ;\n wire \\prbs_state_r[0]_i_2_n_0 ;\n wire \\prbs_state_r[0]_i_3_n_0 ;\n wire \\prbs_state_r[0]_i_4_n_0 ;\n wire \\prbs_state_r[0]_i_5_n_0 ;\n wire \\prbs_state_r[1]_i_1_n_0 ;\n wire \\prbs_state_r[1]_i_2_n_0 ;\n wire \\prbs_state_r[1]_i_3_n_0 ;\n wire \\prbs_state_r[1]_i_4_n_0 ;\n wire \\prbs_state_r[1]_i_5_n_0 ;\n wire \\prbs_state_r[1]_i_6_n_0 ;\n wire \\prbs_state_r[2]_i_10_n_0 ;\n wire \\prbs_state_r[2]_i_11_n_0 ;\n wire \\prbs_state_r[2]_i_2_n_0 ;\n wire \\prbs_state_r[2]_i_3_n_0 ;\n wire \\prbs_state_r[2]_i_4_n_0 ;\n wire \\prbs_state_r[2]_i_6_n_0 ;\n wire \\prbs_state_r[2]_i_7_n_0 ;\n wire \\prbs_state_r[2]_i_8_n_0 ;\n wire \\prbs_state_r[2]_i_9_n_0 ;\n wire \\prbs_state_r[3]_i_1_n_0 ;\n wire \\prbs_state_r[3]_i_2_n_0 ;\n wire \\prbs_state_r[3]_i_3_n_0 ;\n wire \\prbs_state_r[3]_i_4_n_0 ;\n wire \\prbs_state_r[4]_i_11_n_0 ;\n wire \\prbs_state_r[4]_i_2_n_0 ;\n wire \\prbs_state_r[4]_i_3_n_0 ;\n wire \\prbs_state_r[4]_i_4_n_0 ;\n wire \\prbs_state_r[4]_i_5_n_0 ;\n wire \\prbs_state_r[4]_i_6_n_0 ;\n wire \\prbs_state_r[4]_i_7_n_0 ;\n wire \\prbs_state_r[4]_i_8_n_0 ;\n wire \\prbs_state_r[4]_i_9_n_0 ;\n wire \\prbs_state_r_reg[0]_0 ;\n wire \\prbs_state_r_reg[0]_1 ;\n wire \\prbs_state_r_reg[0]_2 ;\n wire \\prbs_state_r_reg[0]_3 ;\n wire \\prbs_state_r_reg[0]_4 ;\n wire \\prbs_state_r_reg[2]_i_1_n_0 ;\n wire \\prbs_state_r_reg[3]_0 ;\n wire \\prbs_state_r_reg[3]_1 ;\n wire \\prbs_state_r_reg[4]_0 ;\n wire \\prbs_state_r_reg[4]_1 ;\n wire \\prbs_state_r_reg[4]_2 ;\n wire \\prbs_state_r_reg[4]_3 ;\n wire prbs_tap_en_r;\n wire prbs_tap_en_r_reg_0;\n wire prbs_tap_inc_r;\n wire prbs_tap_inc_r_i_3_n_0;\n wire prbs_tap_inc_r_reg_0;\n wire prech_done;\n wire prech_done_reg;\n wire prech_req_r_reg;\n wire rd_valid_r1;\n wire rd_valid_r2_reg_n_0;\n wire \\rd_victim_sel[0]_i_1_n_0 ;\n wire \\rd_victim_sel[1]_i_1_n_0 ;\n wire \\rd_victim_sel[2]_i_1_n_0 ;\n wire \\rd_victim_sel_reg[2]_0 ;\n wire \\rd_victim_sel_reg[2]_1 ;\n wire \\rd_victim_sel_reg[2]_2 ;\n wire \\rd_victim_sel_reg[2]_3 ;\n wire [5:0]rdlvl_cpt_tap_cnt;\n wire \\rdlvl_cpt_tap_cnt_reg[5]_0 ;\n wire [2:0]\\rdlvl_cpt_tap_cnt_reg[5]_1 ;\n wire rdlvl_last_byte_done;\n wire rdlvl_stg1_done_int_reg;\n wire rdlvl_stg1_start_int;\n wire [7:3]ref_bit;\n wire \\ref_bit[7]_i_3_n_0 ;\n wire \\ref_bit[7]_i_4_n_0 ;\n wire \\ref_bit[7]_i_5_n_0 ;\n wire \\ref_bit[7]_i_6_n_0 ;\n wire ref_bit_per_bit;\n wire ref_bit_per_bit0;\n wire \\ref_bit_per_bit[7]_i_2_n_0 ;\n wire \\ref_bit_per_bit[7]_i_3_n_0 ;\n wire \\ref_bit_per_bit_reg_n_0_[0] ;\n wire \\ref_bit_per_bit_reg_n_0_[1] ;\n wire \\ref_bit_per_bit_reg_n_0_[2] ;\n wire \\ref_bit_per_bit_reg_n_0_[3] ;\n wire \\ref_bit_per_bit_reg_n_0_[4] ;\n wire \\ref_bit_per_bit_reg_n_0_[5] ;\n wire \\ref_bit_per_bit_reg_n_0_[6] ;\n wire \\ref_bit_per_bit_reg_n_0_[7] ;\n wire \\ref_bit_reg_n_0_[0] ;\n wire \\ref_bit_reg_n_0_[1] ;\n wire \\ref_bit_reg_n_0_[2] ;\n wire ref_right_edge;\n wire ref_right_edge125_in;\n wire \\ref_right_edge[0]_i_1_n_0 ;\n wire \\ref_right_edge[0]_i_3_n_0 ;\n wire \\ref_right_edge[0]_i_4_n_0 ;\n wire \\ref_right_edge[1]_i_1_n_0 ;\n wire \\ref_right_edge[1]_i_3_n_0 ;\n wire \\ref_right_edge[1]_i_4_n_0 ;\n wire \\ref_right_edge[1]_i_5_n_0 ;\n wire \\ref_right_edge[1]_i_6_n_0 ;\n wire \\ref_right_edge[2]_i_1_n_0 ;\n wire \\ref_right_edge[2]_i_2_n_0 ;\n wire \\ref_right_edge[2]_i_3_n_0 ;\n wire \\ref_right_edge[3]_i_1_n_0 ;\n wire \\ref_right_edge[3]_i_2_n_0 ;\n wire \\ref_right_edge[3]_i_3_n_0 ;\n wire \\ref_right_edge[4]_i_10_n_0 ;\n wire \\ref_right_edge[4]_i_11_n_0 ;\n wire \\ref_right_edge[4]_i_1_n_0 ;\n wire \\ref_right_edge[4]_i_2_n_0 ;\n wire \\ref_right_edge[4]_i_4_n_0 ;\n wire \\ref_right_edge[4]_i_5_n_0 ;\n wire \\ref_right_edge[4]_i_6_n_0 ;\n wire \\ref_right_edge[4]_i_7_n_0 ;\n wire \\ref_right_edge[4]_i_8_n_0 ;\n wire \\ref_right_edge[4]_i_9_n_0 ;\n wire \\ref_right_edge[5]_i_10_n_0 ;\n wire \\ref_right_edge[5]_i_11_n_0 ;\n wire \\ref_right_edge[5]_i_12_n_0 ;\n wire \\ref_right_edge[5]_i_13_n_0 ;\n wire \\ref_right_edge[5]_i_14_n_0 ;\n wire \\ref_right_edge[5]_i_15_n_0 ;\n wire \\ref_right_edge[5]_i_16_n_0 ;\n wire \\ref_right_edge[5]_i_1_n_0 ;\n wire \\ref_right_edge[5]_i_2_n_0 ;\n wire \\ref_right_edge[5]_i_5_n_0 ;\n wire \\ref_right_edge[5]_i_7_n_0 ;\n wire \\ref_right_edge[5]_i_8_n_0 ;\n wire \\ref_right_edge[5]_i_9_n_0 ;\n wire \\ref_right_edge_reg[0]_i_2_n_0 ;\n wire \\ref_right_edge_reg[1]_i_2_n_0 ;\n wire \\ref_right_edge_reg[4]_i_3_n_0 ;\n wire \\ref_right_edge_reg[5]_i_3_n_0 ;\n wire \\ref_right_edge_reg[5]_i_3_n_1 ;\n wire \\ref_right_edge_reg[5]_i_3_n_2 ;\n wire \\ref_right_edge_reg[5]_i_3_n_3 ;\n wire \\ref_right_edge_reg[5]_i_3_n_4 ;\n wire \\ref_right_edge_reg[5]_i_3_n_5 ;\n wire \\ref_right_edge_reg[5]_i_3_n_6 ;\n wire \\ref_right_edge_reg[5]_i_3_n_7 ;\n wire \\ref_right_edge_reg[5]_i_4_n_0 ;\n wire \\ref_right_edge_reg[5]_i_6_n_7 ;\n wire \\ref_right_edge_reg_n_0_[0] ;\n wire \\ref_right_edge_reg_n_0_[1] ;\n wire \\ref_right_edge_reg_n_0_[2] ;\n wire \\ref_right_edge_reg_n_0_[3] ;\n wire \\ref_right_edge_reg_n_0_[4] ;\n wire \\ref_right_edge_reg_n_0_[5] ;\n wire reset_rd_addr;\n wire reset_rd_addr0;\n wire right_edge_found;\n wire right_edge_found_i_4_n_0;\n wire right_edge_found_i_5_n_0;\n wire right_edge_found_reg_0;\n wire right_edge_found_reg_1;\n wire [5:0]right_edge_ref;\n wire \\right_edge_ref[0]_i_1_n_0 ;\n wire \\right_edge_ref[0]_i_2_n_0 ;\n wire \\right_edge_ref[0]_i_3_n_0 ;\n wire \\right_edge_ref[1]_i_1_n_0 ;\n wire \\right_edge_ref[1]_i_2_n_0 ;\n wire \\right_edge_ref[1]_i_3_n_0 ;\n wire \\right_edge_ref[2]_i_1_n_0 ;\n wire \\right_edge_ref[2]_i_2_n_0 ;\n wire \\right_edge_ref[2]_i_3_n_0 ;\n wire \\right_edge_ref[3]_i_1_n_0 ;\n wire \\right_edge_ref[3]_i_2_n_0 ;\n wire \\right_edge_ref[3]_i_3_n_0 ;\n wire \\right_edge_ref[4]_i_11_n_0 ;\n wire \\right_edge_ref[4]_i_12_n_0 ;\n wire \\right_edge_ref[4]_i_1_n_0 ;\n wire \\right_edge_ref[4]_i_2_n_0 ;\n wire \\right_edge_ref[4]_i_4_n_0 ;\n wire \\right_edge_ref[4]_i_5_n_0 ;\n wire \\right_edge_ref[4]_i_6_n_0 ;\n wire \\right_edge_ref[4]_i_7_n_0 ;\n wire \\right_edge_ref[4]_i_8_n_0 ;\n wire \\right_edge_ref[4]_i_9_n_0 ;\n wire \\right_edge_ref[5]_i_11_n_0 ;\n wire \\right_edge_ref[5]_i_12_n_0 ;\n wire \\right_edge_ref[5]_i_1_n_0 ;\n wire \\right_edge_ref[5]_i_2_n_0 ;\n wire \\right_edge_ref[5]_i_4_n_0 ;\n wire \\right_edge_ref[5]_i_5_n_0 ;\n wire \\right_edge_ref[5]_i_6_n_0 ;\n wire \\right_edge_ref[5]_i_7_n_0 ;\n wire \\right_edge_ref[5]_i_8_n_0 ;\n wire \\right_edge_ref[5]_i_9_n_0 ;\n wire \\right_edge_ref_reg[4]_i_10_n_0 ;\n wire \\right_edge_ref_reg[4]_i_3_n_0 ;\n wire \\right_edge_ref_reg[5]_i_10_n_0 ;\n wire \\right_edge_ref_reg[5]_i_3_n_0 ;\n wire right_gain_pb;\n wire \\row_cnt_victim_rotate.complex_row_cnt_reg[4] ;\n wire rstdiv0_sync_r1_reg_rep;\n wire rstdiv0_sync_r1_reg_rep__2;\n wire rstdiv0_sync_r1_reg_rep__22;\n wire rstdiv0_sync_r1_reg_rep__23;\n wire [0:0]rstdiv0_sync_r1_reg_rep__7;\n wire rstdiv0_sync_r1_reg_rep__8;\n wire rstdiv0_sync_r1_reg_rep__9;\n wire \\samples_cnt_r[0]_i_1_n_0 ;\n wire \\samples_cnt_r[0]_i_2_n_0 ;\n wire \\samples_cnt_r[0]_i_3_n_0 ;\n wire \\samples_cnt_r[10]_i_1_n_0 ;\n wire \\samples_cnt_r[11]_i_2_n_0 ;\n wire \\samples_cnt_r[11]_i_5_n_0 ;\n wire \\samples_cnt_r[11]_i_6_n_0 ;\n wire \\samples_cnt_r[11]_i_7_n_0 ;\n wire \\samples_cnt_r[1]_i_1_n_0 ;\n wire \\samples_cnt_r[2]_i_1_n_0 ;\n wire \\samples_cnt_r[3]_i_1_n_0 ;\n wire \\samples_cnt_r[4]_i_1_n_0 ;\n wire \\samples_cnt_r[4]_i_3_n_0 ;\n wire \\samples_cnt_r[4]_i_4_n_0 ;\n wire \\samples_cnt_r[4]_i_5_n_0 ;\n wire \\samples_cnt_r[4]_i_6_n_0 ;\n wire \\samples_cnt_r[5]_i_1_n_0 ;\n wire \\samples_cnt_r[6]_i_1_n_0 ;\n wire \\samples_cnt_r[7]_i_1_n_0 ;\n wire \\samples_cnt_r[8]_i_1_n_0 ;\n wire \\samples_cnt_r[8]_i_3_n_0 ;\n wire \\samples_cnt_r[8]_i_4_n_0 ;\n wire \\samples_cnt_r[8]_i_5_n_0 ;\n wire \\samples_cnt_r[8]_i_6_n_0 ;\n wire \\samples_cnt_r[9]_i_1_n_0 ;\n wire \\samples_cnt_r_reg[11]_i_4_n_2 ;\n wire \\samples_cnt_r_reg[11]_i_4_n_3 ;\n wire \\samples_cnt_r_reg[4]_i_2_n_0 ;\n wire \\samples_cnt_r_reg[4]_i_2_n_1 ;\n wire \\samples_cnt_r_reg[4]_i_2_n_2 ;\n wire \\samples_cnt_r_reg[4]_i_2_n_3 ;\n wire \\samples_cnt_r_reg[8]_i_2_n_0 ;\n wire \\samples_cnt_r_reg[8]_i_2_n_1 ;\n wire \\samples_cnt_r_reg[8]_i_2_n_2 ;\n wire \\samples_cnt_r_reg[8]_i_2_n_3 ;\n wire \\samples_cnt_r_reg_n_0_[0] ;\n wire \\samples_cnt_r_reg_n_0_[10] ;\n wire \\samples_cnt_r_reg_n_0_[11] ;\n wire \\samples_cnt_r_reg_n_0_[1] ;\n wire \\samples_cnt_r_reg_n_0_[2] ;\n wire \\samples_cnt_r_reg_n_0_[3] ;\n wire \\samples_cnt_r_reg_n_0_[4] ;\n wire \\samples_cnt_r_reg_n_0_[5] ;\n wire \\samples_cnt_r_reg_n_0_[6] ;\n wire \\samples_cnt_r_reg_n_0_[7] ;\n wire \\samples_cnt_r_reg_n_0_[8] ;\n wire \\samples_cnt_r_reg_n_0_[9] ;\n wire [7:0]sel0;\n wire smallest_right_edge;\n wire \\smallest_right_edge[0]_i_1_n_0 ;\n wire \\smallest_right_edge[1]_i_1_n_0 ;\n wire \\smallest_right_edge[2]_i_1_n_0 ;\n wire \\smallest_right_edge[3]_i_1_n_0 ;\n wire \\smallest_right_edge[4]_i_1_n_0 ;\n wire \\smallest_right_edge[5]_i_2_n_0 ;\n wire \\smallest_right_edge[5]_i_3_n_0 ;\n wire \\smallest_right_edge[5]_i_4_n_0 ;\n wire \\smallest_right_edge_reg_n_0_[0] ;\n wire \\smallest_right_edge_reg_n_0_[1] ;\n wire \\smallest_right_edge_reg_n_0_[2] ;\n wire \\smallest_right_edge_reg_n_0_[3] ;\n wire \\smallest_right_edge_reg_n_0_[4] ;\n wire \\smallest_right_edge_reg_n_0_[5] ;\n wire \\stage_cnt[0]_i_1_n_0 ;\n wire \\stage_cnt[1]_i_1_n_0 ;\n wire \\stage_cnt[1]_i_2_n_0 ;\n wire \\stage_cnt_reg[1]_0 ;\n wire \\stage_cnt_reg_n_0_[0] ;\n wire \\stg1_wr_rd_cnt_reg[3] ;\n wire \\victim_not_fixed.num_samples_done_r_i_1_n_0 ;\n wire \\victim_not_fixed.num_samples_done_r_i_2_n_0 ;\n wire wait_state_cnt_en_r;\n wire wait_state_cnt_en_r0;\n wire \\wait_state_cnt_r[2]_i_1_n_0 ;\n wire \\wait_state_cnt_r[3]_i_1_n_0 ;\n wire [3:0]wait_state_cnt_r_reg__0;\n wire wrcal_done_reg;\n wire wrlvl_final_mux;\n wire [3:1]\\NLW_fine_pi_dec_cnt_reg[5]_i_8_CO_UNCONNECTED ;\n wire [3:2]\\NLW_fine_pi_dec_cnt_reg[5]_i_8_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[0].left_loss_pb_reg[5]_i_14_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[0].left_loss_pb_reg[5]_i_19_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[0].left_loss_pb_reg[5]_i_4_O_UNCONNECTED ;\n wire [3:1]\\NLW_genblk8[0].left_loss_pb_reg[5]_i_5_CO_UNCONNECTED ;\n wire [3:2]\\NLW_genblk8[0].left_loss_pb_reg[5]_i_5_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[0].left_loss_pb_reg[5]_i_6_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[0].right_gain_pb_reg[5]_i_10_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[0].right_gain_pb_reg[5]_i_21_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[0].right_gain_pb_reg[5]_i_22_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[0].right_gain_pb_reg[5]_i_29_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[0].right_gain_pb_reg[5]_i_34_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[0].right_gain_pb_reg[5]_i_39_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[0].right_gain_pb_reg[5]_i_5_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[0].right_gain_pb_reg[5]_i_51_O_UNCONNECTED ;\n wire [3:1]\\NLW_genblk8[0].right_gain_pb_reg[5]_i_6_CO_UNCONNECTED ;\n wire [3:2]\\NLW_genblk8[0].right_gain_pb_reg[5]_i_6_O_UNCONNECTED ;\n wire [3:1]\\NLW_genblk8[0].right_gain_pb_reg[5]_i_7_CO_UNCONNECTED ;\n wire [3:2]\\NLW_genblk8[0].right_gain_pb_reg[5]_i_7_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[1].right_gain_pb_reg[11]_i_15_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[1].right_gain_pb_reg[11]_i_18_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[1].right_gain_pb_reg[11]_i_23_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[1].right_gain_pb_reg[11]_i_28_O_UNCONNECTED ;\n wire [3:1]\\NLW_genblk8[1].right_gain_pb_reg[11]_i_5_CO_UNCONNECTED ;\n wire [3:2]\\NLW_genblk8[1].right_gain_pb_reg[11]_i_5_O_UNCONNECTED ;\n wire [3:1]\\NLW_genblk8[1].right_gain_pb_reg[11]_i_6_CO_UNCONNECTED ;\n wire [3:2]\\NLW_genblk8[1].right_gain_pb_reg[11]_i_6_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[2].right_gain_pb_reg[17]_i_15_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[2].right_gain_pb_reg[17]_i_18_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[2].right_gain_pb_reg[17]_i_23_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[2].right_gain_pb_reg[17]_i_28_O_UNCONNECTED ;\n wire [3:1]\\NLW_genblk8[2].right_gain_pb_reg[17]_i_5_CO_UNCONNECTED ;\n wire [3:2]\\NLW_genblk8[2].right_gain_pb_reg[17]_i_5_O_UNCONNECTED ;\n wire [3:1]\\NLW_genblk8[2].right_gain_pb_reg[17]_i_6_CO_UNCONNECTED ;\n wire [3:2]\\NLW_genblk8[2].right_gain_pb_reg[17]_i_6_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[3].right_gain_pb_reg[23]_i_15_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[3].right_gain_pb_reg[23]_i_18_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[3].right_gain_pb_reg[23]_i_23_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[3].right_gain_pb_reg[23]_i_28_O_UNCONNECTED ;\n wire [3:1]\\NLW_genblk8[3].right_gain_pb_reg[23]_i_5_CO_UNCONNECTED ;\n wire [3:2]\\NLW_genblk8[3].right_gain_pb_reg[23]_i_5_O_UNCONNECTED ;\n wire [3:1]\\NLW_genblk8[3].right_gain_pb_reg[23]_i_6_CO_UNCONNECTED ;\n wire [3:2]\\NLW_genblk8[3].right_gain_pb_reg[23]_i_6_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[4].right_gain_pb_reg[29]_i_15_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[4].right_gain_pb_reg[29]_i_18_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[4].right_gain_pb_reg[29]_i_23_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[4].right_gain_pb_reg[29]_i_28_O_UNCONNECTED ;\n wire [3:1]\\NLW_genblk8[4].right_gain_pb_reg[29]_i_5_CO_UNCONNECTED ;\n wire [3:2]\\NLW_genblk8[4].right_gain_pb_reg[29]_i_5_O_UNCONNECTED ;\n wire [3:1]\\NLW_genblk8[4].right_gain_pb_reg[29]_i_6_CO_UNCONNECTED ;\n wire [3:2]\\NLW_genblk8[4].right_gain_pb_reg[29]_i_6_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[5].right_gain_pb_reg[35]_i_15_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[5].right_gain_pb_reg[35]_i_18_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[5].right_gain_pb_reg[35]_i_23_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[5].right_gain_pb_reg[35]_i_28_O_UNCONNECTED ;\n wire [3:1]\\NLW_genblk8[5].right_gain_pb_reg[35]_i_5_CO_UNCONNECTED ;\n wire [3:2]\\NLW_genblk8[5].right_gain_pb_reg[35]_i_5_O_UNCONNECTED ;\n wire [3:1]\\NLW_genblk8[5].right_gain_pb_reg[35]_i_6_CO_UNCONNECTED ;\n wire [3:2]\\NLW_genblk8[5].right_gain_pb_reg[35]_i_6_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[6].right_gain_pb_reg[41]_i_15_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[6].right_gain_pb_reg[41]_i_18_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[6].right_gain_pb_reg[41]_i_23_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[6].right_gain_pb_reg[41]_i_28_O_UNCONNECTED ;\n wire [3:1]\\NLW_genblk8[6].right_gain_pb_reg[41]_i_5_CO_UNCONNECTED ;\n wire [3:2]\\NLW_genblk8[6].right_gain_pb_reg[41]_i_5_O_UNCONNECTED ;\n wire [3:1]\\NLW_genblk8[6].right_gain_pb_reg[41]_i_6_CO_UNCONNECTED ;\n wire [3:2]\\NLW_genblk8[6].right_gain_pb_reg[41]_i_6_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[7].right_gain_pb_reg[47]_i_15_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[7].right_gain_pb_reg[47]_i_18_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[7].right_gain_pb_reg[47]_i_23_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[7].right_gain_pb_reg[47]_i_28_O_UNCONNECTED ;\n wire [3:1]\\NLW_genblk8[7].right_gain_pb_reg[47]_i_5_CO_UNCONNECTED ;\n wire [3:2]\\NLW_genblk8[7].right_gain_pb_reg[47]_i_5_O_UNCONNECTED ;\n wire [3:1]\\NLW_genblk8[7].right_gain_pb_reg[47]_i_6_CO_UNCONNECTED ;\n wire [3:2]\\NLW_genblk8[7].right_gain_pb_reg[47]_i_6_O_UNCONNECTED ;\n wire [3:0]\\NLW_left_edge_ref_reg[5]_i_6_CO_UNCONNECTED ;\n wire [3:1]\\NLW_left_edge_ref_reg[5]_i_6_O_UNCONNECTED ;\n wire [3:0]\\NLW_ref_right_edge_reg[5]_i_6_CO_UNCONNECTED ;\n wire [3:1]\\NLW_ref_right_edge_reg[5]_i_6_O_UNCONNECTED ;\n wire [3:2]\\NLW_samples_cnt_r_reg[11]_i_4_CO_UNCONNECTED ;\n wire [3:3]\\NLW_samples_cnt_r_reg[11]_i_4_O_UNCONNECTED ;\n\n FDRE #(\n .INIT(1'b0)) \n \\A[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[0]_0 ),\n .Q(A[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\A[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_0 ),\n .Q(A[1]),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair87\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\bit_cnt[0]_i_1 \n (.I0(bit_cnt_reg__0[0]),\n .O(p_0_in__0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair87\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\bit_cnt[1]_i_1 \n (.I0(bit_cnt_reg__0[0]),\n .I1(bit_cnt_reg__0[1]),\n .O(p_0_in__0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair65\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\bit_cnt[2]_i_1 \n (.I0(bit_cnt_reg__0[0]),\n .I1(bit_cnt_reg__0[1]),\n .I2(bit_cnt_reg__0[2]),\n .O(p_0_in__0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair65\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\bit_cnt[3]_i_1 \n (.I0(bit_cnt_reg__0[1]),\n .I1(bit_cnt_reg__0[0]),\n .I2(bit_cnt_reg__0[2]),\n .I3(bit_cnt_reg__0[3]),\n .O(p_0_in__0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair41\" *) \n LUT5 #(\n .INIT(32'h7FFF8000)) \n \\bit_cnt[4]_i_1 \n (.I0(bit_cnt_reg__0[2]),\n .I1(bit_cnt_reg__0[0]),\n .I2(bit_cnt_reg__0[1]),\n .I3(bit_cnt_reg__0[3]),\n .I4(bit_cnt_reg__0[4]),\n .O(p_0_in__0[4]));\n LUT6 #(\n .INIT(64'h7FFFFFFF80000000)) \n \\bit_cnt[5]_i_1 \n (.I0(bit_cnt_reg__0[3]),\n .I1(bit_cnt_reg__0[1]),\n .I2(bit_cnt_reg__0[0]),\n .I3(bit_cnt_reg__0[2]),\n .I4(bit_cnt_reg__0[4]),\n .I5(bit_cnt_reg__0[5]),\n .O(p_0_in__0[5]));\n LUT2 #(\n .INIT(4'h6)) \n \\bit_cnt[6]_i_1 \n (.I0(\\bit_cnt[7]_i_4_n_0 ),\n .I1(bit_cnt_reg__0[6]),\n .O(p_0_in__0[6]));\n LUT6 #(\n .INIT(64'h0000000000000100)) \n \\bit_cnt[7]_i_1 \n (.I0(bit_cnt_reg__0[6]),\n .I1(bit_cnt_reg__0[7]),\n .I2(\\ref_bit_per_bit[7]_i_2_n_0 ),\n .I3(\\bit_cnt[7]_i_3_n_0 ),\n .I4(bit_cnt_reg__0[5]),\n .I5(bit_cnt_reg__0[4]),\n .O(bit_cnt0));\n (* SOFT_HLUTNM = \"soft_lutpair54\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\bit_cnt[7]_i_2 \n (.I0(\\bit_cnt[7]_i_4_n_0 ),\n .I1(bit_cnt_reg__0[6]),\n .I2(bit_cnt_reg__0[7]),\n .O(p_0_in__0[7]));\n LUT6 #(\n .INIT(64'h0000000000000800)) \n \\bit_cnt[7]_i_3 \n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(Q[2]),\n .I3(Q[4]),\n .I4(Q[3]),\n .I5(bit_cnt_reg__0[3]),\n .O(\\bit_cnt[7]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\bit_cnt[7]_i_4 \n (.I0(bit_cnt_reg__0[5]),\n .I1(bit_cnt_reg__0[3]),\n .I2(bit_cnt_reg__0[1]),\n .I3(bit_cnt_reg__0[0]),\n .I4(bit_cnt_reg__0[2]),\n .I5(bit_cnt_reg__0[4]),\n .O(\\bit_cnt[7]_i_4_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\bit_cnt_reg[0] \n (.C(CLK),\n .CE(bit_cnt0),\n .D(p_0_in__0[0]),\n .Q(bit_cnt_reg__0[0]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\bit_cnt_reg[1] \n (.C(CLK),\n .CE(bit_cnt0),\n .D(p_0_in__0[1]),\n .Q(bit_cnt_reg__0[1]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\bit_cnt_reg[2] \n (.C(CLK),\n .CE(bit_cnt0),\n .D(p_0_in__0[2]),\n .Q(bit_cnt_reg__0[2]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\bit_cnt_reg[3] \n (.C(CLK),\n .CE(bit_cnt0),\n .D(p_0_in__0[3]),\n .Q(bit_cnt_reg__0[3]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\bit_cnt_reg[4] \n (.C(CLK),\n .CE(bit_cnt0),\n .D(p_0_in__0[4]),\n .Q(bit_cnt_reg__0[4]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\bit_cnt_reg[5] \n (.C(CLK),\n .CE(bit_cnt0),\n .D(p_0_in__0[5]),\n .Q(bit_cnt_reg__0[5]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\bit_cnt_reg[6] \n (.C(CLK),\n .CE(bit_cnt0),\n .D(p_0_in__0[6]),\n .Q(bit_cnt_reg__0[6]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\bit_cnt_reg[7] \n (.C(CLK),\n .CE(bit_cnt0),\n .D(p_0_in__0[7]),\n .Q(bit_cnt_reg__0[7]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_f0_i_1 \n (.I0(\\gen_mux_rd[7].compare_data_fall0_r1_reg ),\n .I1(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r3_reg ),\n .I2(\\gen_mux_rd[6].compare_data_fall0_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r3_reg ),\n .I4(\\cmp_err_4to1.compare_err_f0_i_2_n_0 ),\n .I5(\\cmp_err_4to1.compare_err_f0_i_3_n_0 ),\n .O(compare_err_f00));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_f0_i_2 \n (.I0(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r3_reg ),\n .I1(\\gen_mux_rd[3].compare_data_fall0_r1_reg ),\n .I2(\\gen_mux_rd[5].compare_data_fall0_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r3_reg ),\n .I4(\\gen_mux_rd[4].compare_data_fall0_r1_reg ),\n .I5(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r3_reg ),\n .O(\\cmp_err_4to1.compare_err_f0_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_f0_i_3 \n (.I0(\\gen_mux_div4.gen_rd_4[0].mux_rd_fall0_r3_reg ),\n .I1(\\gen_mux_rd[0].compare_data_fall0_r1_reg ),\n .I2(\\gen_mux_rd[2].compare_data_fall0_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r3_reg ),\n .I4(\\gen_mux_rd[1].compare_data_fall0_r1_reg ),\n .I5(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r3_reg ),\n .O(\\cmp_err_4to1.compare_err_f0_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cmp_err_4to1.compare_err_f0_reg \n (.C(CLK),\n .CE(rd_valid_r2_reg_n_0),\n .D(compare_err_f00),\n .Q(\\cmp_err_4to1.compare_err_f0_reg_n_0 ),\n .R(compare_err0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_f1_i_1 \n (.I0(\\gen_mux_rd[7].compare_data_fall1_r1_reg ),\n .I1(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r3_reg ),\n .I2(\\gen_mux_rd[6].compare_data_fall1_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r3_reg ),\n .I4(\\cmp_err_4to1.compare_err_f1_i_2_n_0 ),\n .I5(\\cmp_err_4to1.compare_err_f1_i_3_n_0 ),\n .O(compare_err_f10));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_f1_i_2 \n (.I0(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r3_reg ),\n .I1(\\gen_mux_rd[3].compare_data_fall1_r1_reg ),\n .I2(\\gen_mux_rd[5].compare_data_fall1_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r3_reg ),\n .I4(\\gen_mux_rd[4].compare_data_fall1_r1_reg ),\n .I5(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r3_reg ),\n .O(\\cmp_err_4to1.compare_err_f1_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_f1_i_3 \n (.I0(\\gen_mux_div4.gen_rd_4[0].mux_rd_fall1_r3_reg ),\n .I1(\\gen_mux_rd[0].compare_data_fall1_r1_reg ),\n .I2(\\gen_mux_rd[2].compare_data_fall1_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r3_reg ),\n .I4(\\gen_mux_rd[1].compare_data_fall1_r1_reg ),\n .I5(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r3_reg ),\n .O(\\cmp_err_4to1.compare_err_f1_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cmp_err_4to1.compare_err_f1_reg \n (.C(CLK),\n .CE(rd_valid_r2_reg_n_0),\n .D(compare_err_f10),\n .Q(\\cmp_err_4to1.compare_err_f1_reg_n_0 ),\n .R(compare_err0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_f2_i_1 \n (.I0(\\gen_mux_rd[7].compare_data_fall2_r1_reg ),\n .I1(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r3_reg ),\n .I2(\\gen_mux_rd[6].compare_data_fall2_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r3_reg ),\n .I4(\\cmp_err_4to1.compare_err_f2_i_2_n_0 ),\n .I5(\\cmp_err_4to1.compare_err_f2_i_3_n_0 ),\n .O(compare_err_f20));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_f2_i_2 \n (.I0(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r3_reg ),\n .I1(\\gen_mux_rd[3].compare_data_fall2_r1_reg ),\n .I2(\\gen_mux_rd[5].compare_data_fall2_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r3_reg ),\n .I4(\\gen_mux_rd[4].compare_data_fall2_r1_reg ),\n .I5(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r3_reg ),\n .O(\\cmp_err_4to1.compare_err_f2_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_f2_i_3 \n (.I0(\\gen_mux_div4.gen_rd_4[0].mux_rd_fall2_r3_reg ),\n .I1(\\gen_mux_rd[0].compare_data_fall2_r1_reg ),\n .I2(\\gen_mux_rd[2].compare_data_fall2_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r3_reg ),\n .I4(\\gen_mux_rd[1].compare_data_fall2_r1_reg ),\n .I5(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r3_reg ),\n .O(\\cmp_err_4to1.compare_err_f2_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cmp_err_4to1.compare_err_f2_reg \n (.C(CLK),\n .CE(rd_valid_r2_reg_n_0),\n .D(compare_err_f20),\n .Q(\\cmp_err_4to1.compare_err_f2_reg_n_0 ),\n .R(compare_err0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_f3_i_1 \n (.I0(\\gen_mux_rd[7].compare_data_fall3_r1_reg ),\n .I1(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r3_reg ),\n .I2(\\gen_mux_rd[6].compare_data_fall3_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r3_reg ),\n .I4(\\cmp_err_4to1.compare_err_f3_i_2_n_0 ),\n .I5(\\cmp_err_4to1.compare_err_f3_i_3_n_0 ),\n .O(compare_err_f30));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_f3_i_2 \n (.I0(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r3_reg ),\n .I1(\\gen_mux_rd[3].compare_data_fall3_r1_reg ),\n .I2(\\gen_mux_rd[5].compare_data_fall3_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r3_reg ),\n .I4(\\gen_mux_rd[4].compare_data_fall3_r1_reg ),\n .I5(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r3_reg ),\n .O(\\cmp_err_4to1.compare_err_f3_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_f3_i_3 \n (.I0(\\gen_mux_div4.gen_rd_4[0].mux_rd_fall3_r3_reg ),\n .I1(\\gen_mux_rd[0].compare_data_fall3_r1_reg ),\n .I2(\\gen_mux_rd[2].compare_data_fall3_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r3_reg ),\n .I4(\\gen_mux_rd[1].compare_data_fall3_r1_reg ),\n .I5(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r3_reg ),\n .O(\\cmp_err_4to1.compare_err_f3_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cmp_err_4to1.compare_err_f3_reg \n (.C(CLK),\n .CE(rd_valid_r2_reg_n_0),\n .D(compare_err_f30),\n .Q(\\cmp_err_4to1.compare_err_f3_reg_n_0 ),\n .R(compare_err0));\n LUT6 #(\n .INIT(64'hAAAAAAAEAAAAAEAA)) \n \\cmp_err_4to1.compare_err_i_1 \n (.I0(compare_err2),\n .I1(Q[0]),\n .I2(Q[4]),\n .I3(Q[1]),\n .I4(Q[3]),\n .I5(Q[2]),\n .O(compare_err0));\n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n \\cmp_err_4to1.compare_err_i_2 \n (.I0(\\cmp_err_4to1.compare_err_r0_reg_n_0 ),\n .I1(\\cmp_err_4to1.compare_err_f2_reg_n_0 ),\n .I2(\\cmp_err_4to1.compare_err_r2_reg_n_0 ),\n .I3(\\cmp_err_4to1.compare_err_r3_reg_n_0 ),\n .I4(\\cmp_err_4to1.compare_err_i_4_n_0 ),\n .O(compare_err086_out__0));\n LUT2 #(\n .INIT(4'hE)) \n \\cmp_err_4to1.compare_err_i_3 \n (.I0(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .I1(rstdiv0_sync_r1_reg_rep__22),\n .O(compare_err2));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\cmp_err_4to1.compare_err_i_4 \n (.I0(\\cmp_err_4to1.compare_err_r1_reg_n_0 ),\n .I1(\\cmp_err_4to1.compare_err_f1_reg_n_0 ),\n .I2(\\cmp_err_4to1.compare_err_f3_reg_n_0 ),\n .I3(\\cmp_err_4to1.compare_err_f0_reg_n_0 ),\n .O(\\cmp_err_4to1.compare_err_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_r0_i_1 \n (.I0(\\gen_mux_rd[7].compare_data_rise0_r1_reg ),\n .I1(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r3_reg ),\n .I2(\\gen_mux_rd[6].compare_data_rise0_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r3_reg ),\n .I4(\\cmp_err_4to1.compare_err_r0_i_2_n_0 ),\n .I5(\\cmp_err_4to1.compare_err_r0_i_3_n_0 ),\n .O(compare_err_r00));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_r0_i_2 \n (.I0(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r3_reg ),\n .I1(\\gen_mux_rd[3].compare_data_rise0_r1_reg ),\n .I2(\\gen_mux_rd[5].compare_data_rise0_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r3_reg ),\n .I4(\\gen_mux_rd[4].compare_data_rise0_r1_reg ),\n .I5(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r3_reg ),\n .O(\\cmp_err_4to1.compare_err_r0_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_r0_i_3 \n (.I0(\\gen_mux_div4.gen_rd_4[0].mux_rd_rise0_r3_reg ),\n .I1(\\gen_mux_rd[0].compare_data_rise0_r1_reg ),\n .I2(\\gen_mux_rd[2].compare_data_rise0_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r3_reg ),\n .I4(\\gen_mux_rd[1].compare_data_rise0_r1_reg ),\n .I5(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r3_reg ),\n .O(\\cmp_err_4to1.compare_err_r0_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cmp_err_4to1.compare_err_r0_reg \n (.C(CLK),\n .CE(rd_valid_r2_reg_n_0),\n .D(compare_err_r00),\n .Q(\\cmp_err_4to1.compare_err_r0_reg_n_0 ),\n .R(compare_err0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_r1_i_1 \n (.I0(\\gen_mux_rd[7].compare_data_rise1_r1_reg ),\n .I1(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r3_reg ),\n .I2(\\gen_mux_rd[6].compare_data_rise1_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r3_reg ),\n .I4(\\cmp_err_4to1.compare_err_r1_i_2_n_0 ),\n .I5(\\cmp_err_4to1.compare_err_r1_i_3_n_0 ),\n .O(compare_err_r10));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_r1_i_2 \n (.I0(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r3_reg ),\n .I1(\\gen_mux_rd[3].compare_data_rise1_r1_reg ),\n .I2(\\gen_mux_rd[5].compare_data_rise1_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r3_reg ),\n .I4(\\gen_mux_rd[4].compare_data_rise1_r1_reg ),\n .I5(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r3_reg ),\n .O(\\cmp_err_4to1.compare_err_r1_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_r1_i_3 \n (.I0(\\gen_mux_div4.gen_rd_4[0].mux_rd_rise1_r3_reg ),\n .I1(\\gen_mux_rd[0].compare_data_rise1_r1_reg ),\n .I2(\\gen_mux_rd[2].compare_data_rise1_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r3_reg ),\n .I4(\\gen_mux_rd[1].compare_data_rise1_r1_reg ),\n .I5(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r3_reg ),\n .O(\\cmp_err_4to1.compare_err_r1_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cmp_err_4to1.compare_err_r1_reg \n (.C(CLK),\n .CE(rd_valid_r2_reg_n_0),\n .D(compare_err_r10),\n .Q(\\cmp_err_4to1.compare_err_r1_reg_n_0 ),\n .R(compare_err0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_r2_i_1 \n (.I0(\\gen_mux_rd[7].compare_data_rise2_r1_reg ),\n .I1(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r3_reg ),\n .I2(\\gen_mux_rd[6].compare_data_rise2_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r3_reg ),\n .I4(\\cmp_err_4to1.compare_err_r2_i_2_n_0 ),\n .I5(\\cmp_err_4to1.compare_err_r2_i_3_n_0 ),\n .O(compare_err_r20));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_r2_i_2 \n (.I0(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r3_reg ),\n .I1(\\gen_mux_rd[3].compare_data_rise2_r1_reg ),\n .I2(\\gen_mux_rd[5].compare_data_rise2_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r3_reg ),\n .I4(\\gen_mux_rd[4].compare_data_rise2_r1_reg ),\n .I5(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r3_reg ),\n .O(\\cmp_err_4to1.compare_err_r2_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_r2_i_3 \n (.I0(\\gen_mux_div4.gen_rd_4[0].mux_rd_rise2_r3_reg ),\n .I1(\\gen_mux_rd[0].compare_data_rise2_r1_reg ),\n .I2(\\gen_mux_rd[2].compare_data_rise2_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r3_reg ),\n .I4(\\gen_mux_rd[1].compare_data_rise2_r1_reg ),\n .I5(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r3_reg ),\n .O(\\cmp_err_4to1.compare_err_r2_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cmp_err_4to1.compare_err_r2_reg \n (.C(CLK),\n .CE(rd_valid_r2_reg_n_0),\n .D(compare_err_r20),\n .Q(\\cmp_err_4to1.compare_err_r2_reg_n_0 ),\n .R(compare_err0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_r3_i_1 \n (.I0(\\gen_mux_rd[7].compare_data_rise3_r1_reg ),\n .I1(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r3_reg ),\n .I2(\\gen_mux_rd[6].compare_data_rise3_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r3_reg ),\n .I4(\\cmp_err_4to1.compare_err_r3_i_2_n_0 ),\n .I5(\\cmp_err_4to1.compare_err_r3_i_3_n_0 ),\n .O(compare_err_r30));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_r3_i_2 \n (.I0(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r3_reg ),\n .I1(\\gen_mux_rd[3].compare_data_rise3_r1_reg ),\n .I2(\\gen_mux_rd[5].compare_data_rise3_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r3_reg ),\n .I4(\\gen_mux_rd[4].compare_data_rise3_r1_reg ),\n .I5(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r3_reg ),\n .O(\\cmp_err_4to1.compare_err_r3_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_r3_i_3 \n (.I0(\\gen_mux_div4.gen_rd_4[0].mux_rd_rise3_r3_reg ),\n .I1(\\gen_mux_rd[0].compare_data_rise3_r1_reg ),\n .I2(\\gen_mux_rd[2].compare_data_rise3_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r3_reg ),\n .I4(\\gen_mux_rd[1].compare_data_rise3_r1_reg ),\n .I5(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r3_reg ),\n .O(\\cmp_err_4to1.compare_err_r3_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cmp_err_4to1.compare_err_r3_reg \n (.C(CLK),\n .CE(rd_valid_r2_reg_n_0),\n .D(compare_err_r30),\n .Q(\\cmp_err_4to1.compare_err_r3_reg_n_0 ),\n .R(compare_err0));\n FDRE #(\n .INIT(1'b0)) \n \\cmp_err_4to1.compare_err_reg \n (.C(CLK),\n .CE(rd_valid_r2_reg_n_0),\n .D(compare_err086_out__0),\n .Q(\\cmp_err_4to1.compare_err_reg_n_0 ),\n .R(compare_err0));\n LUT5 #(\n .INIT(32'hFFFFFFEA)) \n \\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_1 \n (.I0(\\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0 ),\n .I1(compare_err_pb_and2),\n .I2(err_chk_invalid),\n .I3(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .I4(rstdiv0_sync_r1_reg_rep__22),\n .O(p_66_out));\n LUT6 #(\n .INIT(64'hFFFFFFFFBEFFFFBE)) \n \\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_2 \n (.I0(\\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_5_n_0 ),\n .I1(\\gen_mux_div4.gen_rd_4[0].mux_rd_fall2_r3_reg ),\n .I2(\\gen_mux_rd[0].compare_data_fall2_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[0].mux_rd_rise3_r3_reg ),\n .I4(\\gen_mux_rd[0].compare_data_rise3_r1_reg ),\n .I5(\\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_6_n_0 ),\n .O(p_75_out));\n (* SOFT_HLUTNM = \"soft_lutpair51\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3 \n (.I0(Q[4]),\n .I1(Q[3]),\n .I2(Q[2]),\n .I3(Q[0]),\n .O(\\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair40\" *) \n LUT5 #(\n .INIT(32'h04000010)) \n \\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_4 \n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(Q[4]),\n .I3(Q[3]),\n .I4(Q[2]),\n .O(compare_err_pb_and2));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_5 \n (.I0(\\gen_mux_div4.gen_rd_4[0].mux_rd_fall0_r3_reg ),\n .I1(\\gen_mux_rd[0].compare_data_fall0_r1_reg ),\n .I2(\\gen_mux_div4.gen_rd_4[0].mux_rd_rise1_r3_reg ),\n .I3(\\gen_mux_rd[0].compare_data_rise1_r1_reg ),\n .O(\\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF6FF6)) \n \\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_6 \n (.I0(\\gen_mux_rd[0].compare_data_rise2_r1_reg ),\n .I1(\\gen_mux_div4.gen_rd_4[0].mux_rd_rise2_r3_reg ),\n .I2(\\gen_mux_rd[0].compare_data_fall1_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[0].mux_rd_fall1_r3_reg ),\n .I4(\\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_7_n_0 ),\n .O(\\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_6_n_0 ));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_7 \n (.I0(\\gen_mux_div4.gen_rd_4[0].mux_rd_fall3_r3_reg ),\n .I1(\\gen_mux_rd[0].compare_data_fall3_r1_reg ),\n .I2(\\gen_mux_div4.gen_rd_4[0].mux_rd_rise0_r3_reg ),\n .I3(\\gen_mux_rd[0].compare_data_rise0_r1_reg ),\n .O(\\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_7_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cmp_err_pb_4to1.(null)[0].compare_err_pb_reg[0] \n (.C(CLK),\n .CE(rd_valid_r2_reg_n_0),\n .D(p_75_out),\n .Q(compare_err_pb[0]),\n .R(p_66_out));\n LUT6 #(\n .INIT(64'hFFFFFFFFBEFFFFBE)) \n \\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_1 \n (.I0(\\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_2_n_0 ),\n .I1(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r3_reg ),\n .I2(\\gen_mux_rd[1].compare_data_rise1_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r3_reg ),\n .I4(\\gen_mux_rd[1].compare_data_fall0_r1_reg ),\n .I5(\\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_3_n_0 ),\n .O(p_64_out));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_2 \n (.I0(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r3_reg ),\n .I1(\\gen_mux_rd[1].compare_data_fall1_r1_reg ),\n .I2(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r3_reg ),\n .I3(\\gen_mux_rd[1].compare_data_rise2_r1_reg ),\n .O(\\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF6FF6)) \n \\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_3 \n (.I0(\\gen_mux_rd[1].compare_data_rise3_r1_reg ),\n .I1(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r3_reg ),\n .I2(\\gen_mux_rd[1].compare_data_fall2_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r3_reg ),\n .I4(\\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_4_n_0 ),\n .O(\\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_4 \n (.I0(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r3_reg ),\n .I1(\\gen_mux_rd[1].compare_data_fall3_r1_reg ),\n .I2(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r3_reg ),\n .I3(\\gen_mux_rd[1].compare_data_rise0_r1_reg ),\n .O(\\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_4_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cmp_err_pb_4to1.(null)[1].compare_err_pb_reg[1] \n (.C(CLK),\n .CE(rd_valid_r2_reg_n_0),\n .D(p_64_out),\n .Q(compare_err_pb[1]),\n .R(p_66_out));\n LUT6 #(\n .INIT(64'hFFFFFFFFBEFFFFBE)) \n \\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_1 \n (.I0(\\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_2_n_0 ),\n .I1(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r3_reg ),\n .I2(\\gen_mux_rd[2].compare_data_rise1_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r3_reg ),\n .I4(\\gen_mux_rd[2].compare_data_fall0_r1_reg ),\n .I5(\\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_3_n_0 ),\n .O(p_55_out));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_2 \n (.I0(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r3_reg ),\n .I1(\\gen_mux_rd[2].compare_data_fall1_r1_reg ),\n .I2(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r3_reg ),\n .I3(\\gen_mux_rd[2].compare_data_rise2_r1_reg ),\n .O(\\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF6FF6)) \n \\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_3 \n (.I0(\\gen_mux_rd[2].compare_data_fall3_r1_reg ),\n .I1(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r3_reg ),\n .I2(\\gen_mux_rd[2].compare_data_fall2_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r3_reg ),\n .I4(\\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_4_n_0 ),\n .O(\\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_4 \n (.I0(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r3_reg ),\n .I1(\\gen_mux_rd[2].compare_data_rise0_r1_reg ),\n .I2(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r3_reg ),\n .I3(\\gen_mux_rd[2].compare_data_rise3_r1_reg ),\n .O(\\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_4_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cmp_err_pb_4to1.(null)[2].compare_err_pb_reg[2] \n (.C(CLK),\n .CE(rd_valid_r2_reg_n_0),\n .D(p_55_out),\n .Q(compare_err_pb[2]),\n .R(p_66_out));\n LUT6 #(\n .INIT(64'hFFFFFFFFBEFFFFBE)) \n \\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_1 \n (.I0(\\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_2_n_0 ),\n .I1(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r3_reg ),\n .I2(\\gen_mux_rd[3].compare_data_rise1_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r3_reg ),\n .I4(\\gen_mux_rd[3].compare_data_fall0_r1_reg ),\n .I5(\\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_3_n_0 ),\n .O(p_46_out));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_2 \n (.I0(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r3_reg ),\n .I1(\\gen_mux_rd[3].compare_data_fall1_r1_reg ),\n .I2(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r3_reg ),\n .I3(\\gen_mux_rd[3].compare_data_rise2_r1_reg ),\n .O(\\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF6FF6)) \n \\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_3 \n (.I0(\\gen_mux_rd[3].compare_data_rise3_r1_reg ),\n .I1(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r3_reg ),\n .I2(\\gen_mux_rd[3].compare_data_fall2_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r3_reg ),\n .I4(\\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_4_n_0 ),\n .O(\\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_4 \n (.I0(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r3_reg ),\n .I1(\\gen_mux_rd[3].compare_data_fall3_r1_reg ),\n .I2(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r3_reg ),\n .I3(\\gen_mux_rd[3].compare_data_rise0_r1_reg ),\n .O(\\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_4_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cmp_err_pb_4to1.(null)[3].compare_err_pb_reg[3] \n (.C(CLK),\n .CE(rd_valid_r2_reg_n_0),\n .D(p_46_out),\n .Q(compare_err_pb[3]),\n .R(p_66_out));\n LUT6 #(\n .INIT(64'hFFFFFFFFBEFFFFBE)) \n \\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_1 \n (.I0(\\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_2_n_0 ),\n .I1(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r3_reg ),\n .I2(\\gen_mux_rd[4].compare_data_rise1_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r3_reg ),\n .I4(\\gen_mux_rd[4].compare_data_fall0_r1_reg ),\n .I5(\\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_3_n_0 ),\n .O(p_37_out));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_2 \n (.I0(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r3_reg ),\n .I1(\\gen_mux_rd[4].compare_data_fall1_r1_reg ),\n .I2(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r3_reg ),\n .I3(\\gen_mux_rd[4].compare_data_rise2_r1_reg ),\n .O(\\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF6FF6)) \n \\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_3 \n (.I0(\\gen_mux_rd[4].compare_data_rise3_r1_reg ),\n .I1(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r3_reg ),\n .I2(\\gen_mux_rd[4].compare_data_fall2_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r3_reg ),\n .I4(\\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_4_n_0 ),\n .O(\\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_4 \n (.I0(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r3_reg ),\n .I1(\\gen_mux_rd[4].compare_data_fall3_r1_reg ),\n .I2(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r3_reg ),\n .I3(\\gen_mux_rd[4].compare_data_rise0_r1_reg ),\n .O(\\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_4_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cmp_err_pb_4to1.(null)[4].compare_err_pb_reg[4] \n (.C(CLK),\n .CE(rd_valid_r2_reg_n_0),\n .D(p_37_out),\n .Q(compare_err_pb[4]),\n .R(p_66_out));\n LUT6 #(\n .INIT(64'hFFFFFFFFBEFFFFBE)) \n \\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_1 \n (.I0(\\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_2_n_0 ),\n .I1(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r3_reg ),\n .I2(\\gen_mux_rd[5].compare_data_rise1_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r3_reg ),\n .I4(\\gen_mux_rd[5].compare_data_fall0_r1_reg ),\n .I5(\\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_3_n_0 ),\n .O(p_28_out));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_2 \n (.I0(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r3_reg ),\n .I1(\\gen_mux_rd[5].compare_data_fall1_r1_reg ),\n .I2(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r3_reg ),\n .I3(\\gen_mux_rd[5].compare_data_rise2_r1_reg ),\n .O(\\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF6FF6)) \n \\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_3 \n (.I0(\\gen_mux_rd[5].compare_data_fall3_r1_reg ),\n .I1(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r3_reg ),\n .I2(\\gen_mux_rd[5].compare_data_rise3_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r3_reg ),\n .I4(\\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_4_n_0 ),\n .O(\\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_4 \n (.I0(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r3_reg ),\n .I1(\\gen_mux_rd[5].compare_data_rise0_r1_reg ),\n .I2(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r3_reg ),\n .I3(\\gen_mux_rd[5].compare_data_fall2_r1_reg ),\n .O(\\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_4_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cmp_err_pb_4to1.(null)[5].compare_err_pb_reg[5] \n (.C(CLK),\n .CE(rd_valid_r2_reg_n_0),\n .D(p_28_out),\n .Q(compare_err_pb[5]),\n .R(p_66_out));\n LUT6 #(\n .INIT(64'hFFFFFFFFBEFFFFBE)) \n \\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_1 \n (.I0(\\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_2_n_0 ),\n .I1(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r3_reg ),\n .I2(\\gen_mux_rd[6].compare_data_fall2_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r3_reg ),\n .I4(\\gen_mux_rd[6].compare_data_fall1_r1_reg ),\n .I5(\\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_3_n_0 ),\n .O(p_19_out));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_2 \n (.I0(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r3_reg ),\n .I1(\\gen_mux_rd[6].compare_data_rise3_r1_reg ),\n .I2(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r3_reg ),\n .I3(\\gen_mux_rd[6].compare_data_fall3_r1_reg ),\n .O(\\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF6FF6)) \n \\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_3 \n (.I0(\\gen_mux_rd[6].compare_data_fall0_r1_reg ),\n .I1(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r3_reg ),\n .I2(\\gen_mux_rd[6].compare_data_rise1_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r3_reg ),\n .I4(\\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_4_n_0 ),\n .O(\\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_4 \n (.I0(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r3_reg ),\n .I1(\\gen_mux_rd[6].compare_data_rise2_r1_reg ),\n .I2(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r3_reg ),\n .I3(\\gen_mux_rd[6].compare_data_rise0_r1_reg ),\n .O(\\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_4_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cmp_err_pb_4to1.(null)[6].compare_err_pb_reg[6] \n (.C(CLK),\n .CE(rd_valid_r2_reg_n_0),\n .D(p_19_out),\n .Q(compare_err_pb[6]),\n .R(p_66_out));\n LUT6 #(\n .INIT(64'hFFFFFFFFBEFFFFBE)) \n \\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_1 \n (.I0(\\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_2_n_0 ),\n .I1(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r3_reg ),\n .I2(\\gen_mux_rd[7].compare_data_rise1_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r3_reg ),\n .I4(\\gen_mux_rd[7].compare_data_fall1_r1_reg ),\n .I5(\\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_3_n_0 ),\n .O(p_10_out));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_2 \n (.I0(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r3_reg ),\n .I1(\\gen_mux_rd[7].compare_data_rise3_r1_reg ),\n .I2(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r3_reg ),\n .I3(\\gen_mux_rd[7].compare_data_fall0_r1_reg ),\n .O(\\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF6FF6)) \n \\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_3 \n (.I0(\\gen_mux_rd[7].compare_data_fall2_r1_reg ),\n .I1(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r3_reg ),\n .I2(\\gen_mux_rd[7].compare_data_rise2_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r3_reg ),\n .I4(\\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_4_n_0 ),\n .O(\\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_4 \n (.I0(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r3_reg ),\n .I1(\\gen_mux_rd[7].compare_data_fall3_r1_reg ),\n .I2(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r3_reg ),\n .I3(\\gen_mux_rd[7].compare_data_rise0_r1_reg ),\n .O(\\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_4_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cmp_err_pb_4to1.(null)[7].compare_err_pb_reg[7] \n (.C(CLK),\n .CE(rd_valid_r2_reg_n_0),\n .D(p_10_out),\n .Q(compare_err_pb[7]),\n .R(p_66_out));\n (* SOFT_HLUTNM = \"soft_lutpair34\" *) \n LUT5 #(\n .INIT(32'h80000000)) \n cnt_wait_state_i_1\n (.I0(wait_state_cnt_en_r),\n .I1(wait_state_cnt_r_reg__0[3]),\n .I2(wait_state_cnt_r_reg__0[2]),\n .I3(wait_state_cnt_r_reg__0[0]),\n .I4(wait_state_cnt_r_reg__0[1]),\n .O(cnt_wait_state_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n cnt_wait_state_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cnt_wait_state_i_1_n_0),\n .Q(cnt_wait_state),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hAAAAABAAAAAAAAAA)) \n compare_err_latch_i_1\n (.I0(compare_err_latch_i_2_n_0),\n .I1(compare_err_latch_reg_0),\n .I2(Q[2]),\n .I3(\\cmp_err_4to1.compare_err_reg_n_0 ),\n .I4(Q[0]),\n .I5(Q[1]),\n .O(compare_err_latch_i_1_n_0));\n LUT6 #(\n .INIT(64'h0000000200000000)) \n compare_err_latch_i_2\n (.I0(compare_err_latch_reg_n_0),\n .I1(Q[2]),\n .I2(Q[3]),\n .I3(Q[0]),\n .I4(Q[4]),\n .I5(Q[1]),\n .O(compare_err_latch_i_2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair18\" *) \n LUT2 #(\n .INIT(4'hE)) \n compare_err_latch_i_3\n (.I0(Q[3]),\n .I1(Q[4]),\n .O(compare_err_latch_reg_0));\n FDRE #(\n .INIT(1'b0)) \n compare_err_latch_reg\n (.C(CLK),\n .CE(1'b1),\n .D(compare_err_latch_i_1_n_0),\n .Q(compare_err_latch_reg_n_0),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00002022)) \n compare_err_pb_and_i_1\n (.I0(compare_err_pb_and_i_2_n_0),\n .I1(rstdiv0_sync_r1_reg_rep__22),\n .I2(cnt_wait_state),\n .I3(compare_err_pb_and2),\n .I4(\\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0 ),\n .O(compare_err_pb_and_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFF40000000)) \n compare_err_pb_and_i_2\n (.I0(compare_err_pb_and_i_3_n_0),\n .I1(compare_err_pb[5]),\n .I2(compare_err_pb[4]),\n .I3(compare_err_pb[6]),\n .I4(compare_err_pb[7]),\n .I5(compare_err_pb_and_reg_n_0),\n .O(compare_err_pb_and_i_2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair59\" *) \n LUT4 #(\n .INIT(16'h7FFF)) \n compare_err_pb_and_i_3\n (.I0(compare_err_pb[1]),\n .I1(compare_err_pb[0]),\n .I2(compare_err_pb[3]),\n .I3(compare_err_pb[2]),\n .O(compare_err_pb_and_i_3_n_0));\n FDRE #(\n .INIT(1'b0)) \n compare_err_pb_and_reg\n (.C(CLK),\n .CE(1'b1),\n .D(compare_err_pb_and_i_1_n_0),\n .Q(compare_err_pb_and_reg_n_0),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00002022)) \n compare_err_pb_or_i_1\n (.I0(compare_err_pb_or_i_2_n_0),\n .I1(rstdiv0_sync_r1_reg_rep__22),\n .I2(cnt_wait_state),\n .I3(compare_err_pb_and2),\n .I4(\\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0 ),\n .O(compare_err_pb_or_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFD)) \n compare_err_pb_or_i_2\n (.I0(compare_err_pb_or_i_3_n_0),\n .I1(compare_err_pb[3]),\n .I2(compare_err_pb[2]),\n .I3(compare_err_pb[1]),\n .I4(compare_err_pb[0]),\n .I5(sel0[0]),\n .O(compare_err_pb_or_i_2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair60\" *) \n LUT4 #(\n .INIT(16'h0001)) \n compare_err_pb_or_i_3\n (.I0(compare_err_pb[6]),\n .I1(compare_err_pb[7]),\n .I2(compare_err_pb[5]),\n .I3(compare_err_pb[4]),\n .O(compare_err_pb_or_i_3_n_0));\n FDRE #(\n .INIT(1'b0)) \n compare_err_pb_or_reg\n (.C(CLK),\n .CE(1'b1),\n .D(compare_err_pb_or_i_1_n_0),\n .Q(sel0[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n complex_init_pi_dec_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\prbs_state_r_reg[4]_3 ),\n .Q(complex_init_pi_dec_done),\n .R(rstdiv0_sync_r1_reg_rep__2));\n LUT6 #(\n .INIT(64'h88B88888B8B8B8B8)) \n complex_pi_incdec_done_i_2\n (.I0(complex_pi_incdec_done_i_3_n_0),\n .I1(complex_pi_incdec_done_i_4_n_0),\n .I2(complex_pi_incdec_done_i_5_n_0),\n .I3(\\prbs_state_r[1]_i_5_n_0 ),\n .I4(cnt_wait_state),\n .I5(complex_pi_incdec_done_i_6_n_0),\n .O(complex_pi_incdec_done_reg_0));\n LUT6 #(\n .INIT(64'hC0F07373C0F04040)) \n complex_pi_incdec_done_i_3\n (.I0(prbs_tap_en_r_reg_0),\n .I1(complex_pi_incdec_done_i_5_n_0),\n .I2(cnt_wait_state),\n .I3(p_3_in),\n .I4(complex_pi_incdec_done_i_6_n_0),\n .I5(\\prbs_state_r[3]_i_4_n_0 ),\n .O(complex_pi_incdec_done_i_3_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair50\" *) \n LUT5 #(\n .INIT(32'h04000118)) \n complex_pi_incdec_done_i_4\n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(Q[4]),\n .I3(Q[2]),\n .I4(Q[3]),\n .O(complex_pi_incdec_done_i_4_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair46\" *) \n LUT5 #(\n .INIT(32'h04040834)) \n complex_pi_incdec_done_i_5\n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(Q[4]),\n .I3(Q[3]),\n .I4(Q[2]),\n .O(complex_pi_incdec_done_i_5_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair46\" *) \n LUT5 #(\n .INIT(32'hEFDCFFF7)) \n complex_pi_incdec_done_i_6\n (.I0(Q[0]),\n .I1(Q[4]),\n .I2(Q[3]),\n .I3(Q[2]),\n .I4(Q[1]),\n .O(complex_pi_incdec_done_i_6_n_0));\n FDRE #(\n .INIT(1'b0)) \n complex_pi_incdec_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\prbs_state_r_reg[0]_4 ),\n .Q(complex_pi_incdec_done),\n .R(rstdiv0_sync_r1_reg_rep__2));\n LUT1 #(\n .INIT(2'h1)) \n complex_victim_inc_i_2\n (.I0(\\rd_victim_sel_reg[2]_0 ),\n .O(complex_victim_inc__0));\n FDRE #(\n .INIT(1'b0)) \n complex_victim_inc_reg\n (.C(CLK),\n .CE(1'b1),\n .D(complex_victim_inc__0),\n .Q(\\row_cnt_victim_rotate.complex_row_cnt_reg[4] ),\n .R(rstdiv0_sync_r1_reg_rep__7));\n LUT5 #(\n .INIT(32'hB8FFB8CC)) \n \\dec_cnt[0]_i_1 \n (.I0(\\dec_cnt_reg[0]_i_2_n_0 ),\n .I1(\\largest_left_edge_reg_n_0_[5] ),\n .I2(\\dec_cnt[0]_i_3_n_0 ),\n .I3(\\smallest_right_edge_reg_n_0_[5] ),\n .I4(\\dec_cnt[0]_i_4_n_0 ),\n .O(\\dec_cnt[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAFAFCFC0)) \n \\dec_cnt[0]_i_11 \n (.I0(\\dec_cnt[5]_i_6_n_0 ),\n .I1(\\dec_cnt[0]_i_29_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[3] ),\n .I3(\\dec_cnt[0]_i_14_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[3] ),\n .O(\\dec_cnt[0]_i_11_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFDE8E)) \n \\dec_cnt[0]_i_13 \n (.I0(\\largest_left_edge_reg_n_0_[3] ),\n .I1(\\dec_cnt[0]_i_14_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[3] ),\n .I3(\\dec_cnt[0]_i_32_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[4] ),\n .O(\\dec_cnt[0]_i_13_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFDFFDFFFF)) \n \\dec_cnt[0]_i_14 \n (.I0(\\smallest_right_edge_reg_n_0_[2] ),\n .I1(\\largest_left_edge_reg_n_0_[1] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\smallest_right_edge_reg_n_0_[1] ),\n .I5(\\largest_left_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[0]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'h7E733BEEE73EBEC3)) \n \\dec_cnt[0]_i_15 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_15_n_0 ));\n LUT6 #(\n .INIT(64'h3E432BAEE6323AC3)) \n \\dec_cnt[0]_i_16 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\dec_cnt[0]_i_17 \n (.I0(\\dec_cnt[0]_i_33_n_0 ),\n .I1(\\dec_cnt[0]_i_34_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[3] ),\n .I3(\\dec_cnt[0]_i_26_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[3] ),\n .I5(\\dec_cnt[0]_i_35_n_0 ),\n .O(\\dec_cnt[0]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'h9996966669699999)) \n \\dec_cnt[0]_i_20 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\smallest_right_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'hC29C39C323CE9C22)) \n \\dec_cnt[0]_i_21 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_21_n_0 ));\n LUT6 #(\n .INIT(64'h25B649A565A55A64)) \n \\dec_cnt[0]_i_22 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_22_n_0 ));\n LUT6 #(\n .INIT(64'h7DFEF57E08818110)) \n \\dec_cnt[0]_i_23 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_23_n_0 ));\n LUT6 #(\n .INIT(64'h9796766669899991)) \n \\dec_cnt[0]_i_24 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\smallest_right_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_24_n_0 ));\n LUT6 #(\n .INIT(64'h629C394323C69C32)) \n \\dec_cnt[0]_i_25 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_25_n_0 ));\n LUT6 #(\n .INIT(64'h6B7F6AF74AB756A6)) \n \\dec_cnt[0]_i_26 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[1] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[0]_i_26_n_0 ));\n LUT6 #(\n .INIT(64'h3E732BEEE736BEC3)) \n \\dec_cnt[0]_i_29 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_29_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\dec_cnt[0]_i_3 \n (.I0(\\dec_cnt_reg[0]_i_7_n_0 ),\n .I1(\\dec_cnt[0]_i_8_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[4] ),\n .I3(\\dec_cnt[0]_i_9_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[4] ),\n .I5(\\dec_cnt_reg[0]_i_10_n_0 ),\n .O(\\dec_cnt[0]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h3E532BEEE7323AC3)) \n \\dec_cnt[0]_i_32 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_32_n_0 ));\n LUT6 #(\n .INIT(64'h9B96966669699999)) \n \\dec_cnt[0]_i_33 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\smallest_right_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_33_n_0 ));\n LUT6 #(\n .INIT(64'hC29C39C323CE9C32)) \n \\dec_cnt[0]_i_34 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_34_n_0 ));\n LUT6 #(\n .INIT(64'h7DBEF57E08C18110)) \n \\dec_cnt[0]_i_35 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_35_n_0 ));\n LUT6 #(\n .INIT(64'hF00FE51A1ECFF00F)) \n \\dec_cnt[0]_i_36 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_36_n_0 ));\n LUT6 #(\n .INIT(64'h3A755DAAA6558A15)) \n \\dec_cnt[0]_i_37 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\largest_left_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[0]_i_37_n_0 ));\n LUT6 #(\n .INIT(64'h1CC32B8CC63238C1)) \n \\dec_cnt[0]_i_38 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_38_n_0 ));\n LUT6 #(\n .INIT(64'hFF0F00E000F0FF3F)) \n \\dec_cnt[0]_i_39 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\largest_left_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\smallest_right_edge_reg_n_0_[1] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[0]_i_39_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\dec_cnt[0]_i_4 \n (.I0(\\dec_cnt[0]_i_11_n_0 ),\n .I1(\\largest_left_edge_reg_n_0_[4] ),\n .I2(\\dec_cnt_reg[0]_i_12_n_0 ),\n .I3(\\smallest_right_edge_reg_n_0_[4] ),\n .I4(\\dec_cnt[0]_i_13_n_0 ),\n .O(\\dec_cnt[0]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hF00F87E0708FF00F)) \n \\dec_cnt[0]_i_40 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_40_n_0 ));\n LUT6 #(\n .INIT(64'h271D55AA8A55A285)) \n \\dec_cnt[0]_i_41 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\largest_left_edge_reg_n_0_[0] ),\n .I2(\\smallest_right_edge_reg_n_0_[2] ),\n .I3(\\smallest_right_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[0]_i_41_n_0 ));\n LUT6 #(\n .INIT(64'h1C532BCCC736BCC1)) \n \\dec_cnt[0]_i_42 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_42_n_0 ));\n LUT6 #(\n .INIT(64'hF00F0FF0F00BF00F)) \n \\dec_cnt[0]_i_43 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_43_n_0 ));\n LUT6 #(\n .INIT(64'h1DBED57E48C10110)) \n \\dec_cnt[0]_i_44 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_44_n_0 ));\n LUT6 #(\n .INIT(64'h6A7F6AB75AB756AE)) \n \\dec_cnt[0]_i_45 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[1] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[0]_i_45_n_0 ));\n LUT6 #(\n .INIT(64'h633C33CCDC63C63A)) \n \\dec_cnt[0]_i_46 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_46_n_0 ));\n LUT6 #(\n .INIT(64'h9796666669999995)) \n \\dec_cnt[0]_i_47 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\smallest_right_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_47_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFDE8E)) \n \\dec_cnt[0]_i_5 \n (.I0(\\largest_left_edge_reg_n_0_[3] ),\n .I1(\\dec_cnt[0]_i_14_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[3] ),\n .I3(\\dec_cnt[0]_i_15_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[4] ),\n .O(\\dec_cnt[0]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hF3B8FFFFF3B80000)) \n \\dec_cnt[0]_i_6 \n (.I0(\\dec_cnt[0]_i_16_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[0]_i_14_n_0 ),\n .I3(\\largest_left_edge_reg_n_0_[3] ),\n .I4(\\largest_left_edge_reg_n_0_[4] ),\n .I5(\\dec_cnt[0]_i_17_n_0 ),\n .O(\\dec_cnt[0]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\dec_cnt[0]_i_8 \n (.I0(\\dec_cnt[0]_i_20_n_0 ),\n .I1(\\dec_cnt[0]_i_21_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[3] ),\n .I3(\\dec_cnt[0]_i_22_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[3] ),\n .I5(\\dec_cnt[0]_i_23_n_0 ),\n .O(\\dec_cnt[0]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\dec_cnt[0]_i_9 \n (.I0(\\dec_cnt[0]_i_24_n_0 ),\n .I1(\\dec_cnt[0]_i_25_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[3] ),\n .I3(\\dec_cnt[0]_i_26_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[3] ),\n .I5(\\dec_cnt[0]_i_23_n_0 ),\n .O(\\dec_cnt[0]_i_9_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\dec_cnt[1]_i_1 \n (.I0(\\dec_cnt[1]_i_2_n_0 ),\n .I1(\\largest_left_edge_reg_n_0_[5] ),\n .I2(\\dec_cnt[1]_i_3_n_0 ),\n .I3(\\smallest_right_edge_reg_n_0_[5] ),\n .I4(\\dec_cnt[1]_i_4_n_0 ),\n .O(\\dec_cnt[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hA61AAFB6BE5BA69A)) \n \\dec_cnt[1]_i_13 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[1]_i_13_n_0 ));\n LUT6 #(\n .INIT(64'hE73BE633C673CE62)) \n \\dec_cnt[1]_i_15 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[1] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[1]_i_15_n_0 ));\n LUT6 #(\n .INIT(64'h0A7F8AFE3F017F11)) \n \\dec_cnt[1]_i_16 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[1]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'hE731E633C673CE62)) \n \\dec_cnt[1]_i_19 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[1] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[1]_i_19_n_0 ));\n LUT5 #(\n .INIT(32'hDE8EFFFF)) \n \\dec_cnt[1]_i_2 \n (.I0(\\largest_left_edge_reg_n_0_[4] ),\n .I1(\\dec_cnt[1]_i_5_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[4] ),\n .I3(\\dec_cnt[1]_i_6_n_0 ),\n .I4(\\smallest_right_edge_reg_n_0_[5] ),\n .O(\\dec_cnt[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0A7F8AFE7F017F11)) \n \\dec_cnt[1]_i_20 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[1]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'h8F8E0E1EE787878F)) \n \\dec_cnt[1]_i_21 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\smallest_right_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[1]_i_21_n_0 ));\n LUT6 #(\n .INIT(64'hE759A651AE758A64)) \n \\dec_cnt[1]_i_22 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[1] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[1]_i_22_n_0 ));\n LUT6 #(\n .INIT(64'hE579A561A6E596A4)) \n \\dec_cnt[1]_i_25 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[1]_i_25_n_0 ));\n LUT6 #(\n .INIT(64'h8F8E1E1EE787878F)) \n \\dec_cnt[1]_i_26 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\smallest_right_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[1]_i_26_n_0 ));\n LUT6 #(\n .INIT(64'h6A7FAA7E3F017F11)) \n \\dec_cnt[1]_i_27 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[1]_i_27_n_0 ));\n LUT6 #(\n .INIT(64'hDAD2DAF22F4F4F4A)) \n \\dec_cnt[1]_i_28 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[0] ),\n .I2(\\smallest_right_edge_reg_n_0_[2] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[1]_i_28_n_0 ));\n LUT6 #(\n .INIT(64'h6759A659A6758A64)) \n \\dec_cnt[1]_i_29 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[1] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[1]_i_29_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\dec_cnt[1]_i_3 \n (.I0(\\dec_cnt_reg[1]_i_7_n_0 ),\n .I1(\\dec_cnt[1]_i_8_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[4] ),\n .I3(\\dec_cnt[1]_i_9_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[4] ),\n .I5(\\dec_cnt_reg[1]_i_10_n_0 ),\n .O(\\dec_cnt[1]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h878E8E1EE7E78787)) \n \\dec_cnt[1]_i_30 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\smallest_right_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[1]_i_30_n_0 ));\n LUT6 #(\n .INIT(64'h6663866696869696)) \n \\dec_cnt[1]_i_31 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[1]_i_31_n_0 ));\n LUT6 #(\n .INIT(64'h89C991C9EC6CCC6C)) \n \\dec_cnt[1]_i_32 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\largest_left_edge_reg_n_0_[1] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[1]_i_32_n_0 ));\n LUT6 #(\n .INIT(64'h869AA5969E5BA69A)) \n \\dec_cnt[1]_i_33 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[1]_i_33_n_0 ));\n LUT6 #(\n .INIT(64'h6966696966866666)) \n \\dec_cnt[1]_i_34 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\largest_left_edge_reg_n_0_[1] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[1]_i_34_n_0 ));\n LUT6 #(\n .INIT(64'h6616666696991696)) \n \\dec_cnt[1]_i_35 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[1]_i_35_n_0 ));\n LUT6 #(\n .INIT(64'hCF00F38C8C33F700)) \n \\dec_cnt[1]_i_36 \n (.I0(\\largest_left_edge_reg_n_0_[0] ),\n .I1(\\largest_left_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[2] ),\n .I4(\\smallest_right_edge_reg_n_0_[1] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[1]_i_36_n_0 ));\n LUT6 #(\n .INIT(64'h861AA5969E5BA69A)) \n \\dec_cnt[1]_i_37 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[1]_i_37_n_0 ));\n LUT6 #(\n .INIT(64'h6669666696669296)) \n \\dec_cnt[1]_i_38 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[1]_i_38_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF00FFB8FFB800)) \n \\dec_cnt[1]_i_4 \n (.I0(\\dec_cnt_reg[1]_i_11_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt_reg[1]_i_12_n_0 ),\n .I3(\\smallest_right_edge_reg_n_0_[4] ),\n .I4(\\dec_cnt[1]_i_5_n_0 ),\n .I5(\\largest_left_edge_reg_n_0_[4] ),\n .O(\\dec_cnt[1]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair55\" *) \n LUT4 #(\n .INIT(16'hF3B8)) \n \\dec_cnt[1]_i_5 \n (.I0(\\dec_cnt[1]_i_13_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[5]_i_6_n_0 ),\n .I3(\\largest_left_edge_reg_n_0_[3] ),\n .O(\\dec_cnt[1]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\dec_cnt[1]_i_6 \n (.I0(\\dec_cnt_reg[1]_i_14_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[1]_i_15_n_0 ),\n .I3(\\largest_left_edge_reg_n_0_[3] ),\n .I4(\\dec_cnt[1]_i_16_n_0 ),\n .O(\\dec_cnt[1]_i_6_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\dec_cnt[1]_i_8 \n (.I0(\\dec_cnt_reg[1]_i_14_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[1]_i_19_n_0 ),\n .I3(\\largest_left_edge_reg_n_0_[3] ),\n .I4(\\dec_cnt[1]_i_20_n_0 ),\n .O(\\dec_cnt[1]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\dec_cnt[1]_i_9 \n (.I0(\\dec_cnt[1]_i_21_n_0 ),\n .I1(\\dec_cnt[1]_i_22_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[3] ),\n .I3(\\dec_cnt[1]_i_15_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[3] ),\n .I5(\\dec_cnt[1]_i_20_n_0 ),\n .O(\\dec_cnt[1]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'h42C444C433232323)) \n \\dec_cnt[2]_i_10 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[2]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'hDC9CC4DC9DBDDC9D)) \n \\dec_cnt[2]_i_11 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[2]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFEFEEEEF7)) \n \\dec_cnt[2]_i_12 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[1] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[2]_i_12_n_0 ));\n LUT6 #(\n .INIT(64'h26A22524AAAAA4A4)) \n \\dec_cnt[2]_i_13 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\largest_left_edge_reg_n_0_[1] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[2]_i_13_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair70\" *) \n LUT3 #(\n .INIT(8'hDF)) \n \\dec_cnt[2]_i_14 \n (.I0(\\smallest_right_edge_reg_n_0_[0] ),\n .I1(\\largest_left_edge_reg_n_0_[1] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[2]_i_14_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair57\" *) \n LUT4 #(\n .INIT(16'h00AE)) \n \\dec_cnt[2]_i_15 \n (.I0(\\largest_left_edge_reg_n_0_[1] ),\n .I1(\\largest_left_edge_reg_n_0_[0] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[2]_i_15_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFBDABEB)) \n \\dec_cnt[2]_i_17 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\largest_left_edge_reg_n_0_[0] ),\n .I2(\\largest_left_edge_reg_n_0_[1] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\smallest_right_edge_reg_n_0_[1] ),\n .I5(\\smallest_right_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[2]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'h26A225A4AAAAA4A4)) \n \\dec_cnt[2]_i_18 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\largest_left_edge_reg_n_0_[1] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[2]_i_18_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\dec_cnt[2]_i_19 \n (.I0(\\dec_cnt[2]_i_25_n_0 ),\n .I1(\\dec_cnt[2]_i_26_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[3] ),\n .I3(\\dec_cnt[2]_i_27_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[3] ),\n .I5(\\dec_cnt[2]_i_28_n_0 ),\n .O(\\dec_cnt[2]_i_19_n_0 ));\n LUT6 #(\n .INIT(64'hBBBB88BBB8BBB888)) \n \\dec_cnt[2]_i_2 \n (.I0(\\dec_cnt_reg[2]_i_4_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[5] ),\n .I2(\\dec_cnt[2]_i_5_n_0 ),\n .I3(\\smallest_right_edge_reg_n_0_[4] ),\n .I4(\\dec_cnt[2]_i_6_n_0 ),\n .I5(\\largest_left_edge_reg_n_0_[4] ),\n .O(\\dec_cnt[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\dec_cnt[2]_i_20 \n (.I0(\\dec_cnt[2]_i_10_n_0 ),\n .I1(\\dec_cnt[2]_i_29_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[3] ),\n .I3(\\dec_cnt[2]_i_17_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[3] ),\n .I5(\\dec_cnt[2]_i_30_n_0 ),\n .O(\\dec_cnt[2]_i_20_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\dec_cnt[2]_i_21 \n (.I0(\\dec_cnt_reg[2]_i_16_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[2]_i_31_n_0 ),\n .I3(\\largest_left_edge_reg_n_0_[3] ),\n .I4(\\dec_cnt[2]_i_30_n_0 ),\n .O(\\dec_cnt[2]_i_21_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\dec_cnt[2]_i_22 \n (.I0(\\dec_cnt[2]_i_32_n_0 ),\n .I1(\\dec_cnt[2]_i_33_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[3] ),\n .I3(\\dec_cnt[2]_i_27_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[3] ),\n .I5(\\dec_cnt[2]_i_34_n_0 ),\n .O(\\dec_cnt[2]_i_22_n_0 ));\n LUT6 #(\n .INIT(64'hDCC49DC49DCCB9DD)) \n \\dec_cnt[2]_i_23 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[1] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[2]_i_23_n_0 ));\n LUT6 #(\n .INIT(64'h424442C433232323)) \n \\dec_cnt[2]_i_24 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[2]_i_24_n_0 ));\n LUT6 #(\n .INIT(64'h242422242226B222)) \n \\dec_cnt[2]_i_25 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\largest_left_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[2]_i_25_n_0 ));\n LUT6 #(\n .INIT(64'hB39BB39BD9CDD9D9)) \n \\dec_cnt[2]_i_26 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\largest_left_edge_reg_n_0_[1] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[2]_i_26_n_0 ));\n LUT6 #(\n .INIT(64'hCF8FFFCFF7FFF3FF)) \n \\dec_cnt[2]_i_27 \n (.I0(\\largest_left_edge_reg_n_0_[0] ),\n .I1(\\largest_left_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[2]_i_27_n_0 ));\n LUT6 #(\n .INIT(64'h115100108808AA8A)) \n \\dec_cnt[2]_i_28 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\largest_left_edge_reg_n_0_[1] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\smallest_right_edge_reg_n_0_[1] ),\n .I5(\\smallest_right_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[2]_i_28_n_0 ));\n LUT6 #(\n .INIT(64'hDCC49DCC9DCCB9DD)) \n \\dec_cnt[2]_i_29 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[1] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[2]_i_29_n_0 ));\n LUT5 #(\n .INIT(32'hDE8EFFFF)) \n \\dec_cnt[2]_i_3 \n (.I0(\\largest_left_edge_reg_n_0_[4] ),\n .I1(\\dec_cnt[2]_i_6_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[4] ),\n .I3(\\dec_cnt[2]_i_7_n_0 ),\n .I4(\\smallest_right_edge_reg_n_0_[5] ),\n .O(\\dec_cnt[2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h22A225A4AAAAA4A4)) \n \\dec_cnt[2]_i_30 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\largest_left_edge_reg_n_0_[1] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[2]_i_30_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF77011501)) \n \\dec_cnt[2]_i_31 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\largest_left_edge_reg_n_0_[1] ),\n .I2(\\largest_left_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[2]_i_31_n_0 ));\n LUT6 #(\n .INIT(64'h00204404AAAA22A2)) \n \\dec_cnt[2]_i_32 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[1] ),\n .I2(\\largest_left_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\smallest_right_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[2]_i_32_n_0 ));\n LUT6 #(\n .INIT(64'hBB9BB39BD9CDD9D9)) \n \\dec_cnt[2]_i_33 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\largest_left_edge_reg_n_0_[1] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[2]_i_33_n_0 ));\n LUT6 #(\n .INIT(64'h2444242422223222)) \n \\dec_cnt[2]_i_34 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\largest_left_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[2]_i_34_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\dec_cnt[2]_i_5 \n (.I0(\\dec_cnt[2]_i_10_n_0 ),\n .I1(\\dec_cnt[2]_i_11_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[3] ),\n .I3(\\dec_cnt[2]_i_12_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[3] ),\n .I5(\\dec_cnt[2]_i_13_n_0 ),\n .O(\\dec_cnt[2]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hEFEAFFFFFFFFFFFF)) \n \\dec_cnt[2]_i_6 \n (.I0(\\largest_left_edge_reg_n_0_[3] ),\n .I1(\\dec_cnt[2]_i_14_n_0 ),\n .I2(\\largest_left_edge_reg_n_0_[2] ),\n .I3(\\dec_cnt[2]_i_15_n_0 ),\n .I4(\\smallest_right_edge_reg_n_0_[2] ),\n .I5(\\smallest_right_edge_reg_n_0_[3] ),\n .O(\\dec_cnt[2]_i_6_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\dec_cnt[2]_i_7 \n (.I0(\\dec_cnt_reg[2]_i_16_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[2]_i_17_n_0 ),\n .I3(\\largest_left_edge_reg_n_0_[3] ),\n .I4(\\dec_cnt[2]_i_18_n_0 ),\n .O(\\dec_cnt[2]_i_7_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB8CC)) \n \\dec_cnt[3]_i_1 \n (.I0(\\dec_cnt[3]_i_2_n_0 ),\n .I1(\\largest_left_edge_reg_n_0_[5] ),\n .I2(\\dec_cnt[3]_i_3_n_0 ),\n .I3(\\smallest_right_edge_reg_n_0_[5] ),\n .I4(\\dec_cnt[3]_i_4_n_0 ),\n .O(\\dec_cnt[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair31\" *) \n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\dec_cnt[3]_i_10 \n (.I0(\\dec_cnt[3]_i_12_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[5]_i_5_n_0 ),\n .I3(\\largest_left_edge_reg_n_0_[3] ),\n .I4(\\dec_cnt[3]_i_16_n_0 ),\n .O(\\dec_cnt[3]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\dec_cnt[3]_i_11 \n (.I0(\\dec_cnt[5]_i_5_n_0 ),\n .I1(\\dec_cnt[3]_i_21_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[3] ),\n .I3(\\dec_cnt[3]_i_19_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[3] ),\n .I5(\\dec_cnt[3]_i_22_n_0 ),\n .O(\\dec_cnt[3]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'hBBBBBBBBBB8BBBBB)) \n \\dec_cnt[3]_i_12 \n (.I0(\\dec_cnt[3]_i_23_n_0 ),\n .I1(\\largest_left_edge_reg_n_0_[3] ),\n .I2(\\smallest_right_edge_reg_n_0_[2] ),\n .I3(\\dec_cnt[4]_i_11_n_0 ),\n .I4(\\smallest_right_edge_reg_n_0_[1] ),\n .I5(\\largest_left_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[3]_i_12_n_0 ));\n LUT6 #(\n .INIT(64'hBBB888B8BBBBBBBB)) \n \\dec_cnt[3]_i_13 \n (.I0(\\dec_cnt[5]_i_5_n_0 ),\n .I1(\\largest_left_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[3]_i_24_n_0 ),\n .I3(\\smallest_right_edge_reg_n_0_[2] ),\n .I4(\\dec_cnt[3]_i_25_n_0 ),\n .I5(\\largest_left_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[3]_i_13_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair45\" *) \n LUT5 #(\n .INIT(32'hFFFFBFAA)) \n \\dec_cnt[3]_i_14 \n (.I0(\\smallest_right_edge_reg_n_0_[1] ),\n .I1(\\largest_left_edge_reg_n_0_[0] ),\n .I2(\\largest_left_edge_reg_n_0_[1] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\smallest_right_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[3]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFF775FFFF)) \n \\dec_cnt[3]_i_15 \n (.I0(\\smallest_right_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[0] ),\n .I2(\\largest_left_edge_reg_n_0_[0] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[1] ),\n .I5(\\largest_left_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[3]_i_15_n_0 ));\n LUT6 #(\n .INIT(64'hF1115111FFFFFFFF)) \n \\dec_cnt[3]_i_16 \n (.I0(\\largest_left_edge_reg_n_0_[1] ),\n .I1(\\largest_left_edge_reg_n_0_[0] ),\n .I2(\\smallest_right_edge_reg_n_0_[2] ),\n .I3(\\smallest_right_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[3]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'h6C6C66642626B226)) \n \\dec_cnt[3]_i_17 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\largest_left_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[3]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'hB8883333B8880000)) \n \\dec_cnt[3]_i_18 \n (.I0(\\dec_cnt[3]_i_26_n_0 ),\n .I1(\\largest_left_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[4]_i_15_n_0 ),\n .I3(\\smallest_right_edge_reg_n_0_[2] ),\n .I4(\\largest_left_edge_reg_n_0_[2] ),\n .I5(\\dec_cnt[3]_i_27_n_0 ),\n .O(\\dec_cnt[3]_i_18_n_0 ));\n LUT6 #(\n .INIT(64'hCF8FFFCFFFFFFFFF)) \n \\dec_cnt[3]_i_19 \n (.I0(\\largest_left_edge_reg_n_0_[0] ),\n .I1(\\largest_left_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[3]_i_19_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF00FFB8FFB800)) \n \\dec_cnt[3]_i_2 \n (.I0(\\dec_cnt[3]_i_5_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[3]_i_6_n_0 ),\n .I3(\\smallest_right_edge_reg_n_0_[4] ),\n .I4(\\dec_cnt[3]_i_7_n_0 ),\n .I5(\\largest_left_edge_reg_n_0_[4] ),\n .O(\\dec_cnt[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00000000AB2A2222)) \n \\dec_cnt[3]_i_20 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[1] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\smallest_right_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[3]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'h4444DD4500000000)) \n \\dec_cnt[3]_i_21 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[1] ),\n .I2(\\largest_left_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\smallest_right_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[3]_i_21_n_0 ));\n LUT6 #(\n .INIT(64'h5515110100000000)) \n \\dec_cnt[3]_i_22 \n (.I0(\\smallest_right_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[1] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\largest_left_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[3]_i_22_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFCDDD4CCC)) \n \\dec_cnt[3]_i_23 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[1] ),\n .I2(\\largest_left_edge_reg_n_0_[0] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[3]_i_23_n_0 ));\n LUT2 #(\n .INIT(4'h1)) \n \\dec_cnt[3]_i_24 \n (.I0(\\largest_left_edge_reg_n_0_[0] ),\n .I1(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[3]_i_24_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair56\" *) \n LUT4 #(\n .INIT(16'h8CCF)) \n \\dec_cnt[3]_i_25 \n (.I0(\\smallest_right_edge_reg_n_0_[0] ),\n .I1(\\smallest_right_edge_reg_n_0_[1] ),\n .I2(\\largest_left_edge_reg_n_0_[0] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[3]_i_25_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair33\" *) \n LUT5 #(\n .INIT(32'h445455D5)) \n \\dec_cnt[3]_i_26 \n (.I0(\\smallest_right_edge_reg_n_0_[2] ),\n .I1(\\largest_left_edge_reg_n_0_[1] ),\n .I2(\\largest_left_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[3]_i_26_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair45\" *) \n LUT5 #(\n .INIT(32'hAAFB0000)) \n \\dec_cnt[3]_i_27 \n (.I0(\\smallest_right_edge_reg_n_0_[1] ),\n .I1(\\largest_left_edge_reg_n_0_[0] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[3]_i_27_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\dec_cnt[3]_i_3 \n (.I0(\\dec_cnt[3]_i_8_n_0 ),\n .I1(\\dec_cnt[3]_i_9_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[4] ),\n .I3(\\dec_cnt[3]_i_10_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[4] ),\n .I5(\\dec_cnt[3]_i_11_n_0 ),\n .O(\\dec_cnt[3]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF00FFB8FFB800)) \n \\dec_cnt[3]_i_4 \n (.I0(\\dec_cnt[3]_i_12_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[3]_i_13_n_0 ),\n .I3(\\smallest_right_edge_reg_n_0_[4] ),\n .I4(\\dec_cnt[3]_i_7_n_0 ),\n .I5(\\largest_left_edge_reg_n_0_[4] ),\n .O(\\dec_cnt[3]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hEFE0FFFFEFE00000)) \n \\dec_cnt[3]_i_5 \n (.I0(\\dec_cnt[4]_i_16_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\largest_left_edge_reg_n_0_[2] ),\n .I3(\\dec_cnt[3]_i_14_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[3] ),\n .I5(\\dec_cnt[3]_i_15_n_0 ),\n .O(\\dec_cnt[3]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair31\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\dec_cnt[3]_i_6 \n (.I0(\\dec_cnt[5]_i_5_n_0 ),\n .I1(\\largest_left_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[3]_i_16_n_0 ),\n .O(\\dec_cnt[3]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair55\" *) \n LUT4 #(\n .INIT(16'hF3B8)) \n \\dec_cnt[3]_i_7 \n (.I0(\\dec_cnt[3]_i_17_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[5]_i_6_n_0 ),\n .I3(\\largest_left_edge_reg_n_0_[3] ),\n .O(\\dec_cnt[3]_i_7_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\dec_cnt[3]_i_8 \n (.I0(\\dec_cnt[3]_i_18_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[3]_i_19_n_0 ),\n .I3(\\largest_left_edge_reg_n_0_[3] ),\n .I4(\\dec_cnt[3]_i_20_n_0 ),\n .O(\\dec_cnt[3]_i_8_n_0 ));\n LUT4 #(\n .INIT(16'h88B8)) \n \\dec_cnt[3]_i_9 \n (.I0(\\dec_cnt[3]_i_5_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[3]_i_16_n_0 ),\n .I3(\\largest_left_edge_reg_n_0_[3] ),\n .O(\\dec_cnt[3]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hEFEAFFFF4540AAAA)) \n \\dec_cnt[4]_i_1 \n (.I0(\\largest_left_edge_reg_n_0_[5] ),\n .I1(\\dec_cnt_reg[4]_i_2_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[4] ),\n .I3(\\dec_cnt[4]_i_3_n_0 ),\n .I4(\\smallest_right_edge_reg_n_0_[5] ),\n .I5(\\dec_cnt[4]_i_4_n_0 ),\n .O(\\dec_cnt[4]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair52\" *) \n LUT4 #(\n .INIT(16'hF3B8)) \n \\dec_cnt[4]_i_10 \n (.I0(\\dec_cnt[5]_i_5_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[5]_i_6_n_0 ),\n .I3(\\largest_left_edge_reg_n_0_[3] ),\n .O(\\dec_cnt[4]_i_10_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair71\" *) \n LUT3 #(\n .INIT(8'h8E)) \n \\dec_cnt[4]_i_11 \n (.I0(\\largest_left_edge_reg_n_0_[1] ),\n .I1(\\largest_left_edge_reg_n_0_[0] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[4]_i_11_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair33\" *) \n LUT5 #(\n .INIT(32'hBABBA2AA)) \n \\dec_cnt[4]_i_12 \n (.I0(\\smallest_right_edge_reg_n_0_[2] ),\n .I1(\\largest_left_edge_reg_n_0_[1] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[4]_i_12_n_0 ));\n LUT6 #(\n .INIT(64'h3000703000000000)) \n \\dec_cnt[4]_i_13 \n (.I0(\\largest_left_edge_reg_n_0_[0] ),\n .I1(\\largest_left_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\smallest_right_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[4]_i_13_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF5D45DDDD)) \n \\dec_cnt[4]_i_14 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[1] ),\n .I2(\\largest_left_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\smallest_right_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[4]_i_14_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair56\" *) \n LUT4 #(\n .INIT(16'h0400)) \n \\dec_cnt[4]_i_15 \n (.I0(\\largest_left_edge_reg_n_0_[1] ),\n .I1(\\smallest_right_edge_reg_n_0_[0] ),\n .I2(\\largest_left_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[4]_i_15_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair70\" *) \n LUT3 #(\n .INIT(8'hD0)) \n \\dec_cnt[4]_i_16 \n (.I0(\\largest_left_edge_reg_n_0_[1] ),\n .I1(\\smallest_right_edge_reg_n_0_[0] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[4]_i_16_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair57\" *) \n LUT4 #(\n .INIT(16'h20BA)) \n \\dec_cnt[4]_i_17 \n (.I0(\\smallest_right_edge_reg_n_0_[1] ),\n .I1(\\largest_left_edge_reg_n_0_[0] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[4]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'hB8BBBBBBB8BB8888)) \n \\dec_cnt[4]_i_3 \n (.I0(\\dec_cnt[4]_i_7_n_0 ),\n .I1(\\largest_left_edge_reg_n_0_[4] ),\n .I2(\\dec_cnt[4]_i_8_n_0 ),\n .I3(\\largest_left_edge_reg_n_0_[3] ),\n .I4(\\smallest_right_edge_reg_n_0_[3] ),\n .I5(\\dec_cnt[4]_i_9_n_0 ),\n .O(\\dec_cnt[4]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'hF3B8)) \n \\dec_cnt[4]_i_4 \n (.I0(\\dec_cnt[4]_i_7_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[4] ),\n .I2(\\dec_cnt[4]_i_10_n_0 ),\n .I3(\\largest_left_edge_reg_n_0_[4] ),\n .O(\\dec_cnt[4]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFBFFFFFFFFFF)) \n \\dec_cnt[4]_i_5 \n (.I0(\\largest_left_edge_reg_n_0_[3] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\dec_cnt[4]_i_11_n_0 ),\n .I3(\\smallest_right_edge_reg_n_0_[1] ),\n .I4(\\largest_left_edge_reg_n_0_[2] ),\n .I5(\\smallest_right_edge_reg_n_0_[3] ),\n .O(\\dec_cnt[4]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hDFD0FFFFDFD0F0F0)) \n \\dec_cnt[4]_i_6 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\dec_cnt[4]_i_12_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[3] ),\n .I3(\\dec_cnt[4]_i_13_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[3] ),\n .I5(\\dec_cnt[4]_i_14_n_0 ),\n .O(\\dec_cnt[4]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair52\" *) \n LUT4 #(\n .INIT(16'hB888)) \n \\dec_cnt[4]_i_7 \n (.I0(\\dec_cnt[5]_i_4_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[5]_i_5_n_0 ),\n .I3(\\largest_left_edge_reg_n_0_[3] ),\n .O(\\dec_cnt[4]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hFFDFFFFF5545DD5D)) \n \\dec_cnt[4]_i_8 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[1] ),\n .I2(\\largest_left_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\smallest_right_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[4]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'hAF0FAF00CF0FCF0F)) \n \\dec_cnt[4]_i_9 \n (.I0(\\dec_cnt[4]_i_15_n_0 ),\n .I1(\\dec_cnt[4]_i_16_n_0 ),\n .I2(\\largest_left_edge_reg_n_0_[3] ),\n .I3(\\smallest_right_edge_reg_n_0_[2] ),\n .I4(\\dec_cnt[4]_i_17_n_0 ),\n .I5(\\largest_left_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[4]_i_9_n_0 ));\n LUT4 #(\n .INIT(16'hEF4A)) \n \\dec_cnt[5]_i_1 \n (.I0(\\largest_left_edge_reg_n_0_[5] ),\n .I1(\\dec_cnt[5]_i_2_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[5] ),\n .I3(\\dec_cnt[5]_i_3_n_0 ),\n .O(\\dec_cnt[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0300000080808080)) \n \\dec_cnt[5]_i_2 \n (.I0(\\dec_cnt[5]_i_4_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[4] ),\n .I2(\\smallest_right_edge_reg_n_0_[3] ),\n .I3(\\dec_cnt[5]_i_5_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[3] ),\n .I5(\\largest_left_edge_reg_n_0_[4] ),\n .O(\\dec_cnt[5]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hF7FDD5FD51DC4054)) \n \\dec_cnt[5]_i_3 \n (.I0(\\smallest_right_edge_reg_n_0_[4] ),\n .I1(\\largest_left_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[5]_i_6_n_0 ),\n .I3(\\smallest_right_edge_reg_n_0_[3] ),\n .I4(\\dec_cnt[5]_i_5_n_0 ),\n .I5(\\largest_left_edge_reg_n_0_[4] ),\n .O(\\dec_cnt[5]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'h00004000)) \n \\dec_cnt[5]_i_4 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[1] ),\n .I2(\\dec_cnt[5]_i_7_n_0 ),\n .I3(\\smallest_right_edge_reg_n_0_[2] ),\n .I4(\\largest_left_edge_reg_n_0_[3] ),\n .O(\\dec_cnt[5]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h02000000ABAA2A22)) \n \\dec_cnt[5]_i_5 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[1] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\smallest_right_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[5]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFDDFDFFFF)) \n \\dec_cnt[5]_i_6 \n (.I0(\\smallest_right_edge_reg_n_0_[2] ),\n .I1(\\largest_left_edge_reg_n_0_[1] ),\n .I2(\\largest_left_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\smallest_right_edge_reg_n_0_[1] ),\n .I5(\\largest_left_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[5]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair71\" *) \n LUT3 #(\n .INIT(8'h4D)) \n \\dec_cnt[5]_i_7 \n (.I0(\\largest_left_edge_reg_n_0_[1] ),\n .I1(\\smallest_right_edge_reg_n_0_[0] ),\n .I2(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[5]_i_7_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\dec_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dec_cnt[0]_i_1_n_0 ),\n .Q(\\prbs_dec_tap_cnt_reg[1]_0 [0]),\n .R(1'b0));\n MUXF8 \\dec_cnt_reg[0]_i_10 \n (.I0(\\dec_cnt_reg[0]_i_27_n_0 ),\n .I1(\\dec_cnt_reg[0]_i_28_n_0 ),\n .O(\\dec_cnt_reg[0]_i_10_n_0 ),\n .S(\\smallest_right_edge_reg_n_0_[3] ));\n MUXF8 \\dec_cnt_reg[0]_i_12 \n (.I0(\\dec_cnt_reg[0]_i_30_n_0 ),\n .I1(\\dec_cnt_reg[0]_i_31_n_0 ),\n .O(\\dec_cnt_reg[0]_i_12_n_0 ),\n .S(\\smallest_right_edge_reg_n_0_[3] ));\n MUXF7 \\dec_cnt_reg[0]_i_18 \n (.I0(\\dec_cnt[0]_i_36_n_0 ),\n .I1(\\dec_cnt[0]_i_37_n_0 ),\n .O(\\dec_cnt_reg[0]_i_18_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[3] ));\n MUXF7 \\dec_cnt_reg[0]_i_19 \n (.I0(\\dec_cnt[0]_i_38_n_0 ),\n .I1(\\dec_cnt[0]_i_39_n_0 ),\n .O(\\dec_cnt_reg[0]_i_19_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[3] ));\n MUXF7 \\dec_cnt_reg[0]_i_2 \n (.I0(\\dec_cnt[0]_i_5_n_0 ),\n .I1(\\dec_cnt[0]_i_6_n_0 ),\n .O(\\dec_cnt_reg[0]_i_2_n_0 ),\n .S(\\smallest_right_edge_reg_n_0_[4] ));\n MUXF7 \\dec_cnt_reg[0]_i_27 \n (.I0(\\dec_cnt[0]_i_40_n_0 ),\n .I1(\\dec_cnt[0]_i_41_n_0 ),\n .O(\\dec_cnt_reg[0]_i_27_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[3] ));\n MUXF7 \\dec_cnt_reg[0]_i_28 \n (.I0(\\dec_cnt[0]_i_42_n_0 ),\n .I1(\\dec_cnt[0]_i_43_n_0 ),\n .O(\\dec_cnt_reg[0]_i_28_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[3] ));\n MUXF7 \\dec_cnt_reg[0]_i_30 \n (.I0(\\dec_cnt[0]_i_44_n_0 ),\n .I1(\\dec_cnt[0]_i_45_n_0 ),\n .O(\\dec_cnt_reg[0]_i_30_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[3] ));\n MUXF7 \\dec_cnt_reg[0]_i_31 \n (.I0(\\dec_cnt[0]_i_46_n_0 ),\n .I1(\\dec_cnt[0]_i_47_n_0 ),\n .O(\\dec_cnt_reg[0]_i_31_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[3] ));\n MUXF8 \\dec_cnt_reg[0]_i_7 \n (.I0(\\dec_cnt_reg[0]_i_18_n_0 ),\n .I1(\\dec_cnt_reg[0]_i_19_n_0 ),\n .O(\\dec_cnt_reg[0]_i_7_n_0 ),\n .S(\\smallest_right_edge_reg_n_0_[3] ));\n FDRE #(\n .INIT(1'b0)) \n \\dec_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dec_cnt[1]_i_1_n_0 ),\n .Q(dec_cnt_reg[1]),\n .R(1'b0));\n MUXF8 \\dec_cnt_reg[1]_i_10 \n (.I0(\\dec_cnt_reg[1]_i_23_n_0 ),\n .I1(\\dec_cnt_reg[1]_i_24_n_0 ),\n .O(\\dec_cnt_reg[1]_i_10_n_0 ),\n .S(\\smallest_right_edge_reg_n_0_[3] ));\n MUXF7 \\dec_cnt_reg[1]_i_11 \n (.I0(\\dec_cnt[1]_i_25_n_0 ),\n .I1(\\dec_cnt[1]_i_26_n_0 ),\n .O(\\dec_cnt_reg[1]_i_11_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[3] ));\n MUXF7 \\dec_cnt_reg[1]_i_12 \n (.I0(\\dec_cnt[1]_i_27_n_0 ),\n .I1(\\dec_cnt[1]_i_28_n_0 ),\n .O(\\dec_cnt_reg[1]_i_12_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[3] ));\n MUXF7 \\dec_cnt_reg[1]_i_14 \n (.I0(\\dec_cnt[1]_i_29_n_0 ),\n .I1(\\dec_cnt[1]_i_30_n_0 ),\n .O(\\dec_cnt_reg[1]_i_14_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[3] ));\n MUXF7 \\dec_cnt_reg[1]_i_17 \n (.I0(\\dec_cnt[1]_i_31_n_0 ),\n .I1(\\dec_cnt[1]_i_32_n_0 ),\n .O(\\dec_cnt_reg[1]_i_17_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[3] ));\n MUXF7 \\dec_cnt_reg[1]_i_18 \n (.I0(\\dec_cnt[1]_i_33_n_0 ),\n .I1(\\dec_cnt[1]_i_34_n_0 ),\n .O(\\dec_cnt_reg[1]_i_18_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[3] ));\n MUXF7 \\dec_cnt_reg[1]_i_23 \n (.I0(\\dec_cnt[1]_i_35_n_0 ),\n .I1(\\dec_cnt[1]_i_36_n_0 ),\n .O(\\dec_cnt_reg[1]_i_23_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[3] ));\n MUXF7 \\dec_cnt_reg[1]_i_24 \n (.I0(\\dec_cnt[1]_i_37_n_0 ),\n .I1(\\dec_cnt[1]_i_38_n_0 ),\n .O(\\dec_cnt_reg[1]_i_24_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[3] ));\n MUXF8 \\dec_cnt_reg[1]_i_7 \n (.I0(\\dec_cnt_reg[1]_i_17_n_0 ),\n .I1(\\dec_cnt_reg[1]_i_18_n_0 ),\n .O(\\dec_cnt_reg[1]_i_7_n_0 ),\n .S(\\smallest_right_edge_reg_n_0_[3] ));\n FDRE #(\n .INIT(1'b0)) \n \\dec_cnt_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dec_cnt_reg[2]_i_1_n_0 ),\n .Q(dec_cnt_reg[2]),\n .R(1'b0));\n MUXF7 \\dec_cnt_reg[2]_i_1 \n (.I0(\\dec_cnt[2]_i_2_n_0 ),\n .I1(\\dec_cnt[2]_i_3_n_0 ),\n .O(\\dec_cnt_reg[2]_i_1_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[5] ));\n MUXF7 \\dec_cnt_reg[2]_i_16 \n (.I0(\\dec_cnt[2]_i_23_n_0 ),\n .I1(\\dec_cnt[2]_i_24_n_0 ),\n .O(\\dec_cnt_reg[2]_i_16_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[3] ));\n MUXF8 \\dec_cnt_reg[2]_i_4 \n (.I0(\\dec_cnt_reg[2]_i_8_n_0 ),\n .I1(\\dec_cnt_reg[2]_i_9_n_0 ),\n .O(\\dec_cnt_reg[2]_i_4_n_0 ),\n .S(\\smallest_right_edge_reg_n_0_[4] ));\n MUXF7 \\dec_cnt_reg[2]_i_8 \n (.I0(\\dec_cnt[2]_i_19_n_0 ),\n .I1(\\dec_cnt[2]_i_20_n_0 ),\n .O(\\dec_cnt_reg[2]_i_8_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[4] ));\n MUXF7 \\dec_cnt_reg[2]_i_9 \n (.I0(\\dec_cnt[2]_i_21_n_0 ),\n .I1(\\dec_cnt[2]_i_22_n_0 ),\n .O(\\dec_cnt_reg[2]_i_9_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[4] ));\n FDRE #(\n .INIT(1'b0)) \n \\dec_cnt_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dec_cnt[3]_i_1_n_0 ),\n .Q(dec_cnt_reg[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dec_cnt_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dec_cnt[4]_i_1_n_0 ),\n .Q(dec_cnt_reg[4]),\n .R(1'b0));\n MUXF7 \\dec_cnt_reg[4]_i_2 \n (.I0(\\dec_cnt[4]_i_5_n_0 ),\n .I1(\\dec_cnt[4]_i_6_n_0 ),\n .O(\\dec_cnt_reg[4]_i_2_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[4] ));\n FDRE #(\n .INIT(1'b0)) \n \\dec_cnt_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dec_cnt[5]_i_1_n_0 ),\n .Q(\\prbs_dec_tap_cnt_reg[1]_0 [1]),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair34\" *) \n LUT3 #(\n .INIT(8'h7F)) \n err_chk_invalid_i_1\n (.I0(wait_state_cnt_r_reg__0[3]),\n .I1(wait_state_cnt_r_reg__0[1]),\n .I2(wait_state_cnt_r_reg__0[2]),\n .O(err_chk_invalid_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n err_chk_invalid_reg\n (.C(CLK),\n .CE(1'b1),\n .D(err_chk_invalid_i_1_n_0),\n .Q(err_chk_invalid),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h2)) \n \\fine_delay_mod[11]_i_8 \n (.I0(\\fine_delay_mod_reg[20] ),\n .I1(\\A[2]__2 ),\n .O(\\fine_delay_mod_reg[5] ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFD)) \n fine_delay_sel_i_2\n (.I0(Q[4]),\n .I1(fine_delay_sel_i_4_n_0),\n .I2(bit_cnt_reg__0[7]),\n .I3(bit_cnt_reg__0[6]),\n .I4(bit_cnt_reg__0[4]),\n .I5(bit_cnt_reg__0[5]),\n .O(fine_delay_sel_reg_0));\n (* SOFT_HLUTNM = \"soft_lutpair42\" *) \n LUT3 #(\n .INIT(8'hBD)) \n fine_delay_sel_i_3\n (.I0(Q[1]),\n .I1(Q[2]),\n .I2(Q[3]),\n .O(fine_delay_sel_reg_1));\n (* SOFT_HLUTNM = \"soft_lutpair41\" *) \n LUT4 #(\n .INIT(16'hFFEF)) \n fine_delay_sel_i_4\n (.I0(bit_cnt_reg__0[2]),\n .I1(bit_cnt_reg__0[0]),\n .I2(bit_cnt_reg__0[3]),\n .I3(bit_cnt_reg__0[1]),\n .O(fine_delay_sel_i_4_n_0));\n FDRE #(\n .INIT(1'b0)) \n fine_delay_sel_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\prbs_state_r_reg[0]_0 ),\n .Q(fine_delay_sel_r_reg),\n .R(rstdiv0_sync_r1_reg_rep__8));\n LUT6 #(\n .INIT(64'h0100000022002200)) \n fine_dly_error_i_2\n (.I0(Q[2]),\n .I1(Q[3]),\n .I2(\\stage_cnt_reg_n_0_[0] ),\n .I3(\\prbs_dec_tap_cnt[2]_i_3_n_0 ),\n .I4(\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ),\n .I5(Q[4]),\n .O(fine_dly_error_reg_0));\n FDRE #(\n .INIT(1'b0)) \n fine_dly_error_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\dec_cnt_reg[0]_0 ),\n .Q(prbs_rdlvl_done_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__7));\n (* SOFT_HLUTNM = \"soft_lutpair82\" *) \n LUT2 #(\n .INIT(4'h7)) \n fine_inc_stage_i_1\n (.I0(\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ),\n .I1(\\stage_cnt_reg_n_0_[0] ),\n .O(fine_inc_stage_i_1_n_0));\n FDSE #(\n .INIT(1'b1)) \n fine_inc_stage_reg\n (.C(CLK),\n .CE(1'b1),\n .D(fine_inc_stage_i_1_n_0),\n .Q(fine_inc_stage_reg_n_0),\n .S(rstdiv0_sync_r1_reg_rep__8));\n LUT5 #(\n .INIT(32'h74777444)) \n \\fine_pi_dec_cnt[0]_i_1 \n (.I0(\\fine_pi_dec_cnt_reg_n_0_[0] ),\n .I1(Q[2]),\n .I2(\\fine_pi_dec_cnt[0]_i_2_n_0 ),\n .I3(Q[1]),\n .I4(\\rdlvl_cpt_tap_cnt_reg[5]_1 [0]),\n .O(\\fine_pi_dec_cnt[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8A8ABA8ABA8ABA8A)) \n \\fine_pi_dec_cnt[0]_i_2 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I1(\\stage_cnt_reg_n_0_[0] ),\n .I2(\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ),\n .I3(\\fine_pi_dec_cnt_reg[3]_i_3_n_7 ),\n .I4(\\prbs_dec_tap_cnt_reg[1]_0 [1]),\n .I5(\\prbs_dec_tap_cnt_reg[1]_0 [0]),\n .O(\\fine_pi_dec_cnt[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h9F909F9F9F909090)) \n \\fine_pi_dec_cnt[1]_i_1 \n (.I0(\\fine_pi_dec_cnt_reg_n_0_[0] ),\n .I1(\\fine_pi_dec_cnt_reg_n_0_[1] ),\n .I2(Q[2]),\n .I3(\\fine_pi_dec_cnt[1]_i_2_n_0 ),\n .I4(Q[1]),\n .I5(\\calib_sel_reg[3]_0 ),\n .O(\\fine_pi_dec_cnt[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8A8ABA8ABA8ABA8A)) \n \\fine_pi_dec_cnt[1]_i_2 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I1(\\stage_cnt_reg_n_0_[0] ),\n .I2(\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ),\n .I3(\\fine_pi_dec_cnt_reg[3]_i_3_n_6 ),\n .I4(\\prbs_dec_tap_cnt_reg[1]_0 [1]),\n .I5(\\prbs_dec_tap_cnt_reg[1]_0 [0]),\n .O(\\fine_pi_dec_cnt[1]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hE1FFE100)) \n \\fine_pi_dec_cnt[2]_i_1 \n (.I0(\\fine_pi_dec_cnt_reg_n_0_[1] ),\n .I1(\\fine_pi_dec_cnt_reg_n_0_[0] ),\n .I2(\\fine_pi_dec_cnt_reg_n_0_[2] ),\n .I3(Q[2]),\n .I4(\\fine_pi_dec_cnt[2]_i_2_n_0 ),\n .O(\\fine_pi_dec_cnt[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h88B8FFFF88B80000)) \n \\fine_pi_dec_cnt[2]_i_2 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I1(\\fine_pi_dec_cnt[5]_i_7_n_0 ),\n .I2(\\fine_pi_dec_cnt_reg[3]_i_3_n_5 ),\n .I3(\\prbs_dec_tap_cnt[2]_i_3_n_0 ),\n .I4(Q[1]),\n .I5(\\calib_sel_reg[3]_1 ),\n .O(\\fine_pi_dec_cnt[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFE01FFFFFE010000)) \n \\fine_pi_dec_cnt[3]_i_1 \n (.I0(\\fine_pi_dec_cnt_reg_n_0_[0] ),\n .I1(\\fine_pi_dec_cnt_reg_n_0_[1] ),\n .I2(\\fine_pi_dec_cnt_reg_n_0_[2] ),\n .I3(\\fine_pi_dec_cnt_reg_n_0_[3] ),\n .I4(Q[2]),\n .I5(\\fine_pi_dec_cnt[3]_i_2_n_0 ),\n .O(\\fine_pi_dec_cnt[3]_i_1_n_0 ));\n (* HLUTNM = \"lutpair3\" *) \n LUT3 #(\n .INIT(8'h96)) \n \\fine_pi_dec_cnt[3]_i_10 \n (.I0(\\prbs_dec_tap_cnt_reg[1]_0 [0]),\n .I1(\\smallest_right_edge_reg_n_0_[0] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .O(\\fine_pi_dec_cnt[3]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'h88B8FFFF88B80000)) \n \\fine_pi_dec_cnt[3]_i_2 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I1(\\fine_pi_dec_cnt[5]_i_7_n_0 ),\n .I2(\\fine_pi_dec_cnt_reg[3]_i_3_n_4 ),\n .I3(\\prbs_dec_tap_cnt[2]_i_3_n_0 ),\n .I4(Q[1]),\n .I5(\\rdlvl_cpt_tap_cnt_reg[5]_1 [1]),\n .O(\\fine_pi_dec_cnt[3]_i_2_n_0 ));\n (* HLUTNM = \"lutpair1\" *) \n LUT3 #(\n .INIT(8'hD4)) \n \\fine_pi_dec_cnt[3]_i_4 \n (.I0(\\smallest_right_edge_reg_n_0_[2] ),\n .I1(dec_cnt_reg[2]),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .O(\\fine_pi_dec_cnt[3]_i_4_n_0 ));\n (* HLUTNM = \"lutpair0\" *) \n LUT3 #(\n .INIT(8'hD4)) \n \\fine_pi_dec_cnt[3]_i_5 \n (.I0(\\smallest_right_edge_reg_n_0_[1] ),\n .I1(dec_cnt_reg[1]),\n .I2(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\fine_pi_dec_cnt[3]_i_5_n_0 ));\n (* HLUTNM = \"lutpair3\" *) \n LUT2 #(\n .INIT(4'hB)) \n \\fine_pi_dec_cnt[3]_i_6 \n (.I0(\\prbs_dec_tap_cnt_reg[1]_0 [0]),\n .I1(\\smallest_right_edge_reg_n_0_[0] ),\n .O(\\fine_pi_dec_cnt[3]_i_6_n_0 ));\n (* HLUTNM = \"lutpair2\" *) \n LUT4 #(\n .INIT(16'h9669)) \n \\fine_pi_dec_cnt[3]_i_7 \n (.I0(\\smallest_right_edge_reg_n_0_[3] ),\n .I1(dec_cnt_reg[3]),\n .I2(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I3(\\fine_pi_dec_cnt[3]_i_4_n_0 ),\n .O(\\fine_pi_dec_cnt[3]_i_7_n_0 ));\n (* HLUTNM = \"lutpair1\" *) \n LUT4 #(\n .INIT(16'h9669)) \n \\fine_pi_dec_cnt[3]_i_8 \n (.I0(\\smallest_right_edge_reg_n_0_[2] ),\n .I1(dec_cnt_reg[2]),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\fine_pi_dec_cnt[3]_i_5_n_0 ),\n .O(\\fine_pi_dec_cnt[3]_i_8_n_0 ));\n (* HLUTNM = \"lutpair0\" *) \n LUT4 #(\n .INIT(16'h9669)) \n \\fine_pi_dec_cnt[3]_i_9 \n (.I0(\\smallest_right_edge_reg_n_0_[1] ),\n .I1(dec_cnt_reg[1]),\n .I2(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I3(\\fine_pi_dec_cnt[3]_i_6_n_0 ),\n .O(\\fine_pi_dec_cnt[3]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'h88B8FFFF88B80000)) \n \\fine_pi_dec_cnt[4]_i_2 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\fine_pi_dec_cnt[5]_i_7_n_0 ),\n .I2(\\fine_pi_dec_cnt_reg[5]_i_8_n_7 ),\n .I3(\\prbs_dec_tap_cnt[2]_i_3_n_0 ),\n .I4(Q[1]),\n .I5(\\calib_sel_reg[3]_2 ),\n .O(\\fine_pi_dec_cnt[4]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFE0001)) \n \\fine_pi_dec_cnt[4]_i_3 \n (.I0(\\fine_pi_dec_cnt_reg_n_0_[3] ),\n .I1(\\fine_pi_dec_cnt_reg_n_0_[2] ),\n .I2(\\fine_pi_dec_cnt_reg_n_0_[1] ),\n .I3(\\fine_pi_dec_cnt_reg_n_0_[0] ),\n .I4(\\fine_pi_dec_cnt_reg_n_0_[4] ),\n .O(\\fine_pi_dec_cnt[4]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h8E71718E718E8E71)) \n \\fine_pi_dec_cnt[5]_i_10 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(dec_cnt_reg[4]),\n .I2(\\smallest_right_edge_reg_n_0_[4] ),\n .I3(\\prbs_dec_tap_cnt_reg[1]_0 [1]),\n .I4(\\smallest_right_edge_reg_n_0_[5] ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\fine_pi_dec_cnt[5]_i_10_n_0 ));\n LUT4 #(\n .INIT(16'h9669)) \n \\fine_pi_dec_cnt[5]_i_11 \n (.I0(\\fine_pi_dec_cnt[5]_i_9_n_0 ),\n .I1(dec_cnt_reg[4]),\n .I2(\\smallest_right_edge_reg_n_0_[4] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .O(\\fine_pi_dec_cnt[5]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000004)) \n \\fine_pi_dec_cnt[5]_i_3 \n (.I0(prbs_rdlvl_start_r),\n .I1(prbs_rdlvl_start_reg),\n .I2(Q[3]),\n .I3(Q[2]),\n .I4(Q[4]),\n .I5(Q[1]),\n .O(\\fine_pi_dec_cnt[5]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h1010180800001808)) \n \\fine_pi_dec_cnt[5]_i_4 \n (.I0(Q[1]),\n .I1(Q[4]),\n .I2(Q[3]),\n .I3(cnt_wait_state),\n .I4(Q[2]),\n .I5(prbs_tap_en_r_reg_0),\n .O(\\fine_pi_dec_cnt[5]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hBBB8FFFFBBB80000)) \n \\fine_pi_dec_cnt[5]_i_5 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .I1(\\fine_pi_dec_cnt[5]_i_7_n_0 ),\n .I2(\\prbs_dec_tap_cnt[2]_i_3_n_0 ),\n .I3(\\fine_pi_dec_cnt_reg[5]_i_8_n_6 ),\n .I4(Q[1]),\n .I5(\\rdlvl_cpt_tap_cnt_reg[5]_1 [2]),\n .O(\\fine_pi_dec_cnt[5]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFE00000001)) \n \\fine_pi_dec_cnt[5]_i_6 \n (.I0(\\fine_pi_dec_cnt_reg_n_0_[4] ),\n .I1(\\fine_pi_dec_cnt_reg_n_0_[0] ),\n .I2(\\fine_pi_dec_cnt_reg_n_0_[1] ),\n .I3(\\fine_pi_dec_cnt_reg_n_0_[2] ),\n .I4(\\fine_pi_dec_cnt_reg_n_0_[3] ),\n .I5(\\fine_pi_dec_cnt_reg_n_0_[5] ),\n .O(\\fine_pi_dec_cnt[5]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair82\" *) \n LUT2 #(\n .INIT(4'hB)) \n \\fine_pi_dec_cnt[5]_i_7 \n (.I0(\\stage_cnt_reg_n_0_[0] ),\n .I1(\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ),\n .O(\\fine_pi_dec_cnt[5]_i_7_n_0 ));\n (* HLUTNM = \"lutpair2\" *) \n LUT3 #(\n .INIT(8'hD4)) \n \\fine_pi_dec_cnt[5]_i_9 \n (.I0(\\smallest_right_edge_reg_n_0_[3] ),\n .I1(dec_cnt_reg[3]),\n .I2(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\fine_pi_dec_cnt[5]_i_9_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\fine_pi_dec_cnt_reg[0] \n (.C(CLK),\n .CE(fine_pi_dec_cnt),\n .D(\\fine_pi_dec_cnt[0]_i_1_n_0 ),\n .Q(\\fine_pi_dec_cnt_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE #(\n .INIT(1'b0)) \n \\fine_pi_dec_cnt_reg[1] \n (.C(CLK),\n .CE(fine_pi_dec_cnt),\n .D(\\fine_pi_dec_cnt[1]_i_1_n_0 ),\n .Q(\\fine_pi_dec_cnt_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE #(\n .INIT(1'b0)) \n \\fine_pi_dec_cnt_reg[2] \n (.C(CLK),\n .CE(fine_pi_dec_cnt),\n .D(\\fine_pi_dec_cnt[2]_i_1_n_0 ),\n .Q(\\fine_pi_dec_cnt_reg_n_0_[2] ),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE #(\n .INIT(1'b0)) \n \\fine_pi_dec_cnt_reg[3] \n (.C(CLK),\n .CE(fine_pi_dec_cnt),\n .D(\\fine_pi_dec_cnt[3]_i_1_n_0 ),\n .Q(\\fine_pi_dec_cnt_reg_n_0_[3] ),\n .R(rstdiv0_sync_r1_reg_rep__7));\n CARRY4 \\fine_pi_dec_cnt_reg[3]_i_3 \n (.CI(1'b0),\n .CO({\\fine_pi_dec_cnt_reg[3]_i_3_n_0 ,\\fine_pi_dec_cnt_reg[3]_i_3_n_1 ,\\fine_pi_dec_cnt_reg[3]_i_3_n_2 ,\\fine_pi_dec_cnt_reg[3]_i_3_n_3 }),\n .CYINIT(1'b0),\n .DI({\\fine_pi_dec_cnt[3]_i_4_n_0 ,\\fine_pi_dec_cnt[3]_i_5_n_0 ,\\fine_pi_dec_cnt[3]_i_6_n_0 ,\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }),\n .O({\\fine_pi_dec_cnt_reg[3]_i_3_n_4 ,\\fine_pi_dec_cnt_reg[3]_i_3_n_5 ,\\fine_pi_dec_cnt_reg[3]_i_3_n_6 ,\\fine_pi_dec_cnt_reg[3]_i_3_n_7 }),\n .S({\\fine_pi_dec_cnt[3]_i_7_n_0 ,\\fine_pi_dec_cnt[3]_i_8_n_0 ,\\fine_pi_dec_cnt[3]_i_9_n_0 ,\\fine_pi_dec_cnt[3]_i_10_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\fine_pi_dec_cnt_reg[4] \n (.C(CLK),\n .CE(fine_pi_dec_cnt),\n .D(\\fine_pi_dec_cnt_reg[4]_i_1_n_0 ),\n .Q(\\fine_pi_dec_cnt_reg_n_0_[4] ),\n .R(rstdiv0_sync_r1_reg_rep__7));\n MUXF7 \\fine_pi_dec_cnt_reg[4]_i_1 \n (.I0(\\fine_pi_dec_cnt[4]_i_2_n_0 ),\n .I1(\\fine_pi_dec_cnt[4]_i_3_n_0 ),\n .O(\\fine_pi_dec_cnt_reg[4]_i_1_n_0 ),\n .S(Q[2]));\n FDRE #(\n .INIT(1'b0)) \n \\fine_pi_dec_cnt_reg[5] \n (.C(CLK),\n .CE(fine_pi_dec_cnt),\n .D(\\fine_pi_dec_cnt_reg[5]_i_2_n_0 ),\n .Q(\\fine_pi_dec_cnt_reg_n_0_[5] ),\n .R(rstdiv0_sync_r1_reg_rep__7));\n MUXF7 \\fine_pi_dec_cnt_reg[5]_i_1 \n (.I0(\\fine_pi_dec_cnt[5]_i_3_n_0 ),\n .I1(\\fine_pi_dec_cnt[5]_i_4_n_0 ),\n .O(fine_pi_dec_cnt),\n .S(Q[0]));\n MUXF7 \\fine_pi_dec_cnt_reg[5]_i_2 \n (.I0(\\fine_pi_dec_cnt[5]_i_5_n_0 ),\n .I1(\\fine_pi_dec_cnt[5]_i_6_n_0 ),\n .O(\\fine_pi_dec_cnt_reg[5]_i_2_n_0 ),\n .S(Q[2]));\n CARRY4 \\fine_pi_dec_cnt_reg[5]_i_8 \n (.CI(\\fine_pi_dec_cnt_reg[3]_i_3_n_0 ),\n .CO({\\NLW_fine_pi_dec_cnt_reg[5]_i_8_CO_UNCONNECTED [3:1],\\fine_pi_dec_cnt_reg[5]_i_8_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,\\fine_pi_dec_cnt[5]_i_9_n_0 }),\n .O({\\NLW_fine_pi_dec_cnt_reg[5]_i_8_O_UNCONNECTED [3:2],\\fine_pi_dec_cnt_reg[5]_i_8_n_6 ,\\fine_pi_dec_cnt_reg[5]_i_8_n_7 }),\n .S({1'b0,1'b0,\\fine_pi_dec_cnt[5]_i_10_n_0 ,\\fine_pi_dec_cnt[5]_i_11_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[0].mux_rd_fall0_r2_reg[0] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(mux_rd_fall0_r1),\n .Q(mux_rd_fall0_r2),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[0].mux_rd_fall0_r3_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(mux_rd_fall0_r2),\n .Q(\\gen_mux_div4.gen_rd_4[0].mux_rd_fall0_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[0].mux_rd_fall1_r2_reg[0] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(mux_rd_fall1_r1),\n .Q(mux_rd_fall1_r2),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[0].mux_rd_fall1_r3_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(mux_rd_fall1_r2),\n .Q(\\gen_mux_div4.gen_rd_4[0].mux_rd_fall1_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[0].mux_rd_fall2_r2_reg[0] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(mux_rd_fall2_r1),\n .Q(mux_rd_fall2_r2),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[0].mux_rd_fall2_r3_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(mux_rd_fall2_r2),\n .Q(\\gen_mux_div4.gen_rd_4[0].mux_rd_fall2_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[0].mux_rd_fall3_r2_reg[0] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(mux_rd_fall3_r1),\n .Q(mux_rd_fall3_r2),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[0].mux_rd_fall3_r3_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(mux_rd_fall3_r2),\n .Q(\\gen_mux_div4.gen_rd_4[0].mux_rd_fall3_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[0].mux_rd_rise0_r2_reg[0] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(mux_rd_rise0_r1),\n .Q(mux_rd_rise0_r2),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[0].mux_rd_rise0_r3_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(mux_rd_rise0_r2),\n .Q(\\gen_mux_div4.gen_rd_4[0].mux_rd_rise0_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[0].mux_rd_rise1_r2_reg[0] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(mux_rd_rise1_r1),\n .Q(mux_rd_rise1_r2),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[0].mux_rd_rise1_r3_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(mux_rd_rise1_r2),\n .Q(\\gen_mux_div4.gen_rd_4[0].mux_rd_rise1_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[0].mux_rd_rise2_r2_reg[0] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(mux_rd_rise2_r1),\n .Q(mux_rd_rise2_r2),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[0].mux_rd_rise2_r3_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(mux_rd_rise2_r2),\n .Q(\\gen_mux_div4.gen_rd_4[0].mux_rd_rise2_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[0].mux_rd_rise3_r2_reg[0] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(mux_rd_rise3_r1),\n .Q(mux_rd_rise3_r2),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[0].mux_rd_rise3_r3_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(mux_rd_rise3_r2),\n .Q(\\gen_mux_div4.gen_rd_4[0].mux_rd_rise3_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r2_reg[1] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[1].mux_rd_fall0_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r3_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r2_reg[1] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[1].mux_rd_fall1_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r3_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r2_reg[1] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[1].mux_rd_fall2_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r3_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r2_reg[1] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[1].mux_rd_fall3_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r3_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r2_reg[1] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[1].mux_rd_rise0_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r3_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r2_reg[1] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[1].mux_rd_rise1_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r3_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r2_reg[1] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[1].mux_rd_rise2_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r3_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r2_reg[1] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[1].mux_rd_rise3_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r3_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r2_reg[2] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[2].mux_rd_fall0_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r3_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r2_reg[2] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[2].mux_rd_fall1_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r3_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r2_reg[2] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[2].mux_rd_fall2_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r3_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r2_reg[2] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[2].mux_rd_fall3_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r3_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r2_reg[2] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[2].mux_rd_rise0_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r3_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r2_reg[2] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[2].mux_rd_rise1_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r3_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r2_reg[2] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[2].mux_rd_rise2_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r3_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r2_reg[2] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[2].mux_rd_rise3_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r3_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r2_reg[3] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[3].mux_rd_fall0_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r3_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r2_reg[3] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[3].mux_rd_fall1_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r3_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r2_reg[3] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[3].mux_rd_fall2_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r3_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r2_reg[3] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[3].mux_rd_fall3_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r3_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r2_reg[3] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[3].mux_rd_rise0_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r3_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r2_reg[3] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[3].mux_rd_rise1_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r3_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r2_reg[3] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[3].mux_rd_rise2_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r3_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r2_reg[3] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[3].mux_rd_rise3_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r3_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r2_reg[4] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[4].mux_rd_fall0_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r3_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r2_reg[4] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[4].mux_rd_fall1_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r3_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r2_reg[4] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[4].mux_rd_fall2_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r3_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r2_reg[4] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[4].mux_rd_fall3_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r3_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r2_reg[4] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[4].mux_rd_rise0_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r3_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r2_reg[4] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[4].mux_rd_rise1_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r3_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r2_reg[4] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[4].mux_rd_rise2_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r3_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r2_reg[4] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[4].mux_rd_rise3_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r3_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r2_reg[5] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[5].mux_rd_fall0_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r3_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r2_reg[5] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[5].mux_rd_fall1_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r3_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r2_reg[5] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[5].mux_rd_fall2_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r3_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r2_reg[5] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[5].mux_rd_fall3_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r3_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r2_reg[5] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[5].mux_rd_rise0_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r3_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r2_reg[5] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[5].mux_rd_rise1_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r3_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r2_reg[5] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[5].mux_rd_rise2_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r3_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r2_reg[5] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[5].mux_rd_rise3_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r3_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r2_reg[6] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[6].mux_rd_fall0_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r3_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r2_reg[6] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[6].mux_rd_fall1_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r3_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r2_reg[6] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[6].mux_rd_fall2_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r3_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r2_reg[6] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[6].mux_rd_fall3_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r3_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r2_reg[6] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[6].mux_rd_rise0_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r3_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r2_reg[6] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[6].mux_rd_rise1_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r3_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r2_reg[6] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[6].mux_rd_rise2_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r3_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r2_reg[6] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[6].mux_rd_rise3_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r3_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r2_reg[7] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[7].mux_rd_fall0_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r3_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r2_reg[7] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[7].mux_rd_fall1_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r3_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r2_reg[7] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[7].mux_rd_fall2_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r3_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r2_reg[7] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[7].mux_rd_fall3_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r3_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r2_reg[7] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[7].mux_rd_rise0_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r3_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r2_reg[7] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[7].mux_rd_rise1_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r3_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r2_reg[7] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[7].mux_rd_rise2_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r3_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r2_reg[7] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[7].mux_rd_rise3_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r2_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r3_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r3_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[0].compare_data_fall0_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[6] ),\n .Q(\\gen_mux_rd[0].compare_data_fall0_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[0].compare_data_fall1_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[4] ),\n .Q(\\gen_mux_rd[0].compare_data_fall1_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[0].compare_data_fall2_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[2] ),\n .Q(\\gen_mux_rd[0].compare_data_fall2_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[0].compare_data_fall3_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[0] ),\n .Q(\\gen_mux_rd[0].compare_data_fall3_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[0].compare_data_rise0_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[7] ),\n .Q(\\gen_mux_rd[0].compare_data_rise0_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[0].compare_data_rise1_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[5] ),\n .Q(\\gen_mux_rd[0].compare_data_rise1_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[0].compare_data_rise2_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[3] ),\n .Q(\\gen_mux_rd[0].compare_data_rise2_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[0].compare_data_rise3_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[1] ),\n .Q(\\gen_mux_rd[0].compare_data_rise3_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_9 ),\n .Q(mux_rd_fall0_r1),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_25 ),\n .Q(mux_rd_fall1_r1),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_41 ),\n .Q(mux_rd_fall2_r1),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_57 ),\n .Q(mux_rd_fall3_r1),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_1 ),\n .Q(mux_rd_rise0_r1),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_17 ),\n .Q(mux_rd_rise1_r1),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_33 ),\n .Q(mux_rd_rise2_r1),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_49 ),\n .Q(mux_rd_rise3_r1),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[1].compare_data_fall0_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[6]_0 ),\n .Q(\\gen_mux_rd[1].compare_data_fall0_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[1].compare_data_fall1_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[4]_0 ),\n .Q(\\gen_mux_rd[1].compare_data_fall1_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[1].compare_data_fall2_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[2]_0 ),\n .Q(\\gen_mux_rd[1].compare_data_fall2_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[1].compare_data_fall3_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[0]_0 ),\n .Q(\\gen_mux_rd[1].compare_data_fall3_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[1].compare_data_rise0_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[7]_0 ),\n .Q(\\gen_mux_rd[1].compare_data_rise0_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[1].compare_data_rise1_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[5]_0 ),\n .Q(\\gen_mux_rd[1].compare_data_rise1_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[1].compare_data_rise2_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[3]_0 ),\n .Q(\\gen_mux_rd[1].compare_data_rise2_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[1].compare_data_rise3_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[1]_0 ),\n .Q(\\gen_mux_rd[1].compare_data_rise3_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_10 ),\n .Q(\\gen_mux_rd[1].mux_rd_fall0_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_26 ),\n .Q(\\gen_mux_rd[1].mux_rd_fall1_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_42 ),\n .Q(\\gen_mux_rd[1].mux_rd_fall2_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_58 ),\n .Q(\\gen_mux_rd[1].mux_rd_fall3_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_2 ),\n .Q(\\gen_mux_rd[1].mux_rd_rise0_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_18 ),\n .Q(\\gen_mux_rd[1].mux_rd_rise1_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_34 ),\n .Q(\\gen_mux_rd[1].mux_rd_rise2_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_50 ),\n .Q(\\gen_mux_rd[1].mux_rd_rise3_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[2].compare_data_fall0_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[6]_1 ),\n .Q(\\gen_mux_rd[2].compare_data_fall0_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[2].compare_data_fall1_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[4]_1 ),\n .Q(\\gen_mux_rd[2].compare_data_fall1_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[2].compare_data_fall2_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[2]_1 ),\n .Q(\\gen_mux_rd[2].compare_data_fall2_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[2].compare_data_fall3_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[0]_1 ),\n .Q(\\gen_mux_rd[2].compare_data_fall3_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[2].compare_data_rise0_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[7]_1 ),\n .Q(\\gen_mux_rd[2].compare_data_rise0_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[2].compare_data_rise1_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[5]_1 ),\n .Q(\\gen_mux_rd[2].compare_data_rise1_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[2].compare_data_rise2_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[3]_1 ),\n .Q(\\gen_mux_rd[2].compare_data_rise2_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[2].compare_data_rise3_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[1]_1 ),\n .Q(\\gen_mux_rd[2].compare_data_rise3_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_11 ),\n .Q(\\gen_mux_rd[2].mux_rd_fall0_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_27 ),\n .Q(\\gen_mux_rd[2].mux_rd_fall1_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_43 ),\n .Q(\\gen_mux_rd[2].mux_rd_fall2_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_59 ),\n .Q(\\gen_mux_rd[2].mux_rd_fall3_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_3 ),\n .Q(\\gen_mux_rd[2].mux_rd_rise0_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_19 ),\n .Q(\\gen_mux_rd[2].mux_rd_rise1_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_35 ),\n .Q(\\gen_mux_rd[2].mux_rd_rise2_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_51 ),\n .Q(\\gen_mux_rd[2].mux_rd_rise3_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[3].compare_data_fall0_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[6]_2 ),\n .Q(\\gen_mux_rd[3].compare_data_fall0_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[3].compare_data_fall1_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[4]_2 ),\n .Q(\\gen_mux_rd[3].compare_data_fall1_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[3].compare_data_fall2_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[2]_2 ),\n .Q(\\gen_mux_rd[3].compare_data_fall2_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[3].compare_data_fall3_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[0]_2 ),\n .Q(\\gen_mux_rd[3].compare_data_fall3_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[3].compare_data_rise0_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[7]_2 ),\n .Q(\\gen_mux_rd[3].compare_data_rise0_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[3].compare_data_rise1_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[5]_2 ),\n .Q(\\gen_mux_rd[3].compare_data_rise1_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[3].compare_data_rise2_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[3]_2 ),\n .Q(\\gen_mux_rd[3].compare_data_rise2_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[3].compare_data_rise3_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[1]_2 ),\n .Q(\\gen_mux_rd[3].compare_data_rise3_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_12 ),\n .Q(\\gen_mux_rd[3].mux_rd_fall0_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_28 ),\n .Q(\\gen_mux_rd[3].mux_rd_fall1_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_44 ),\n .Q(\\gen_mux_rd[3].mux_rd_fall2_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_60 ),\n .Q(\\gen_mux_rd[3].mux_rd_fall3_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_4 ),\n .Q(\\gen_mux_rd[3].mux_rd_rise0_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_20 ),\n .Q(\\gen_mux_rd[3].mux_rd_rise1_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_36 ),\n .Q(\\gen_mux_rd[3].mux_rd_rise2_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_52 ),\n .Q(\\gen_mux_rd[3].mux_rd_rise3_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[4].compare_data_fall0_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[6]_3 ),\n .Q(\\gen_mux_rd[4].compare_data_fall0_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[4].compare_data_fall1_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[4]_3 ),\n .Q(\\gen_mux_rd[4].compare_data_fall1_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[4].compare_data_fall2_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[2]_3 ),\n .Q(\\gen_mux_rd[4].compare_data_fall2_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[4].compare_data_fall3_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[0]_3 ),\n .Q(\\gen_mux_rd[4].compare_data_fall3_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[4].compare_data_rise0_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[7]_3 ),\n .Q(\\gen_mux_rd[4].compare_data_rise0_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[4].compare_data_rise1_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[5]_3 ),\n .Q(\\gen_mux_rd[4].compare_data_rise1_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[4].compare_data_rise2_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[3]_3 ),\n .Q(\\gen_mux_rd[4].compare_data_rise2_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[4].compare_data_rise3_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[1]_3 ),\n .Q(\\gen_mux_rd[4].compare_data_rise3_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_13 ),\n .Q(\\gen_mux_rd[4].mux_rd_fall0_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_29 ),\n .Q(\\gen_mux_rd[4].mux_rd_fall1_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_45 ),\n .Q(\\gen_mux_rd[4].mux_rd_fall2_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_61 ),\n .Q(\\gen_mux_rd[4].mux_rd_fall3_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_5 ),\n .Q(\\gen_mux_rd[4].mux_rd_rise0_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_21 ),\n .Q(\\gen_mux_rd[4].mux_rd_rise1_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_37 ),\n .Q(\\gen_mux_rd[4].mux_rd_rise2_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_53 ),\n .Q(\\gen_mux_rd[4].mux_rd_rise3_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[5].compare_data_fall0_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[6]_4 ),\n .Q(\\gen_mux_rd[5].compare_data_fall0_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[5].compare_data_fall1_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[4]_4 ),\n .Q(\\gen_mux_rd[5].compare_data_fall1_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[5].compare_data_fall2_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[2]_4 ),\n .Q(\\gen_mux_rd[5].compare_data_fall2_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[5].compare_data_fall3_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[0]_4 ),\n .Q(\\gen_mux_rd[5].compare_data_fall3_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[5].compare_data_rise0_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[7]_4 ),\n .Q(\\gen_mux_rd[5].compare_data_rise0_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[5].compare_data_rise1_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[5]_4 ),\n .Q(\\gen_mux_rd[5].compare_data_rise1_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[5].compare_data_rise2_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[3]_4 ),\n .Q(\\gen_mux_rd[5].compare_data_rise2_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[5].compare_data_rise3_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[1]_4 ),\n .Q(\\gen_mux_rd[5].compare_data_rise3_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_14 ),\n .Q(\\gen_mux_rd[5].mux_rd_fall0_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_30 ),\n .Q(\\gen_mux_rd[5].mux_rd_fall1_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_46 ),\n .Q(\\gen_mux_rd[5].mux_rd_fall2_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_62 ),\n .Q(\\gen_mux_rd[5].mux_rd_fall3_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_6 ),\n .Q(\\gen_mux_rd[5].mux_rd_rise0_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_22 ),\n .Q(\\gen_mux_rd[5].mux_rd_rise1_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_38 ),\n .Q(\\gen_mux_rd[5].mux_rd_rise2_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_54 ),\n .Q(\\gen_mux_rd[5].mux_rd_rise3_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[6].compare_data_fall0_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[6]_5 ),\n .Q(\\gen_mux_rd[6].compare_data_fall0_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[6].compare_data_fall1_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[4]_5 ),\n .Q(\\gen_mux_rd[6].compare_data_fall1_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[6].compare_data_fall2_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[2]_5 ),\n .Q(\\gen_mux_rd[6].compare_data_fall2_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[6].compare_data_fall3_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[0]_5 ),\n .Q(\\gen_mux_rd[6].compare_data_fall3_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[6].compare_data_rise0_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[7]_5 ),\n .Q(\\gen_mux_rd[6].compare_data_rise0_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[6].compare_data_rise1_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[5]_5 ),\n .Q(\\gen_mux_rd[6].compare_data_rise1_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[6].compare_data_rise2_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[3]_5 ),\n .Q(\\gen_mux_rd[6].compare_data_rise2_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[6].compare_data_rise3_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[1]_5 ),\n .Q(\\gen_mux_rd[6].compare_data_rise3_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_15 ),\n .Q(\\gen_mux_rd[6].mux_rd_fall0_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_31 ),\n .Q(\\gen_mux_rd[6].mux_rd_fall1_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_47 ),\n .Q(\\gen_mux_rd[6].mux_rd_fall2_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_63 ),\n .Q(\\gen_mux_rd[6].mux_rd_fall3_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_7 ),\n .Q(\\gen_mux_rd[6].mux_rd_rise0_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_23 ),\n .Q(\\gen_mux_rd[6].mux_rd_rise1_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_39 ),\n .Q(\\gen_mux_rd[6].mux_rd_rise2_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_55 ),\n .Q(\\gen_mux_rd[6].mux_rd_rise3_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[7].compare_data_fall0_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[6]_6 ),\n .Q(\\gen_mux_rd[7].compare_data_fall0_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[7].compare_data_fall1_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[4]_6 ),\n .Q(\\gen_mux_rd[7].compare_data_fall1_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[7].compare_data_fall2_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[2]_6 ),\n .Q(\\gen_mux_rd[7].compare_data_fall2_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[7].compare_data_fall3_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[0]_6 ),\n .Q(\\gen_mux_rd[7].compare_data_fall3_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[7].compare_data_rise0_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[7]_6 ),\n .Q(\\gen_mux_rd[7].compare_data_rise0_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[7].compare_data_rise1_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[5]_6 ),\n .Q(\\gen_mux_rd[7].compare_data_rise1_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[7].compare_data_rise2_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[3]_6 ),\n .Q(\\gen_mux_rd[7].compare_data_rise2_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[7].compare_data_rise3_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[1]_6 ),\n .Q(\\gen_mux_rd[7].compare_data_rise3_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_16 ),\n .Q(\\gen_mux_rd[7].mux_rd_fall0_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_32 ),\n .Q(\\gen_mux_rd[7].mux_rd_fall1_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_48 ),\n .Q(\\gen_mux_rd[7].mux_rd_fall2_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_64 ),\n .Q(\\gen_mux_rd[7].mux_rd_fall3_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_8 ),\n .Q(\\gen_mux_rd[7].mux_rd_rise0_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_24 ),\n .Q(\\gen_mux_rd[7].mux_rd_rise1_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_40 ),\n .Q(\\gen_mux_rd[7].mux_rd_rise2_r1_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_56 ),\n .Q(\\gen_mux_rd[7].mux_rd_rise3_r1_reg ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000001D000C000)) \n \\genblk7[0].compare_err_pb_latch_r[0]_i_1 \n (.I0(cnt_wait_state),\n .I1(Q[0]),\n .I2(Q[2]),\n .I3(Q[3]),\n .I4(Q[1]),\n .I5(Q[4]),\n .O(\\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\genblk7[0].compare_err_pb_latch_r[0]_i_2 \n (.I0(compare_err_pb[0]),\n .I1(\\genblk7[0].compare_err_pb_latch_r_reg_n_0_[0] ),\n .O(\\genblk7[0].compare_err_pb_latch_r[0]_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk7[0].compare_err_pb_latch_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk7[0].compare_err_pb_latch_r[0]_i_2_n_0 ),\n .Q(\\genblk7[0].compare_err_pb_latch_r_reg_n_0_[0] ),\n .R(\\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair59\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\genblk7[1].compare_err_pb_latch_r[1]_i_1 \n (.I0(compare_err_pb[1]),\n .I1(\\genblk7[1].compare_err_pb_latch_r_reg_n_0_[1] ),\n .O(\\genblk7[1].compare_err_pb_latch_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk7[1].compare_err_pb_latch_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk7[1].compare_err_pb_latch_r[1]_i_1_n_0 ),\n .Q(\\genblk7[1].compare_err_pb_latch_r_reg_n_0_[1] ),\n .R(\\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\genblk7[2].compare_err_pb_latch_r[2]_i_1 \n (.I0(compare_err_pb[2]),\n .I1(\\genblk7[2].compare_err_pb_latch_r_reg_n_0_[2] ),\n .O(\\genblk7[2].compare_err_pb_latch_r[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk7[2].compare_err_pb_latch_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk7[2].compare_err_pb_latch_r[2]_i_1_n_0 ),\n .Q(\\genblk7[2].compare_err_pb_latch_r_reg_n_0_[2] ),\n .R(\\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\genblk7[3].compare_err_pb_latch_r[3]_i_1 \n (.I0(compare_err_pb[3]),\n .I1(\\genblk7[3].compare_err_pb_latch_r_reg_n_0_[3] ),\n .O(\\genblk7[3].compare_err_pb_latch_r[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk7[3].compare_err_pb_latch_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk7[3].compare_err_pb_latch_r[3]_i_1_n_0 ),\n .Q(\\genblk7[3].compare_err_pb_latch_r_reg_n_0_[3] ),\n .R(\\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\genblk7[4].compare_err_pb_latch_r[4]_i_1 \n (.I0(compare_err_pb[4]),\n .I1(\\genblk7[4].compare_err_pb_latch_r_reg_n_0_[4] ),\n .O(\\genblk7[4].compare_err_pb_latch_r[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk7[4].compare_err_pb_latch_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk7[4].compare_err_pb_latch_r[4]_i_1_n_0 ),\n .Q(\\genblk7[4].compare_err_pb_latch_r_reg_n_0_[4] ),\n .R(\\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\genblk7[5].compare_err_pb_latch_r[5]_i_1 \n (.I0(compare_err_pb[5]),\n .I1(\\genblk7[5].compare_err_pb_latch_r_reg_n_0_[5] ),\n .O(\\genblk7[5].compare_err_pb_latch_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk7[5].compare_err_pb_latch_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk7[5].compare_err_pb_latch_r[5]_i_1_n_0 ),\n .Q(\\genblk7[5].compare_err_pb_latch_r_reg_n_0_[5] ),\n .R(\\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair60\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\genblk7[6].compare_err_pb_latch_r[6]_i_1 \n (.I0(compare_err_pb[6]),\n .I1(\\genblk7[6].compare_err_pb_latch_r_reg_n_0_[6] ),\n .O(\\genblk7[6].compare_err_pb_latch_r[6]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk7[6].compare_err_pb_latch_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk7[6].compare_err_pb_latch_r[6]_i_1_n_0 ),\n .Q(\\genblk7[6].compare_err_pb_latch_r_reg_n_0_[6] ),\n .R(\\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\genblk7[7].compare_err_pb_latch_r[7]_i_1 \n (.I0(compare_err_pb[7]),\n .I1(\\genblk7[7].compare_err_pb_latch_r_reg_n_0_[7] ),\n .O(\\genblk7[7].compare_err_pb_latch_r[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk7[7].compare_err_pb_latch_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk7[7].compare_err_pb_latch_r[7]_i_1_n_0 ),\n .Q(\\genblk7[7].compare_err_pb_latch_r_reg_n_0_[7] ),\n .R(\\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[0].left_edge_found_pb_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[0].left_edge_found_pb_reg[0]_0 ),\n .Q(\\genblk8[0].left_loss_pb_reg[0]_0 ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair43\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\genblk8[0].left_edge_pb[0]_i_1 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .O(\\genblk8[0].left_edge_pb[0]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h6)) \n \\genblk8[0].left_edge_pb[1]_i_1 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .O(\\genblk8[0].left_edge_pb[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair19\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\genblk8[0].left_edge_pb[2]_i_1 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I1(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .O(\\genblk8[0].left_edge_pb[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair64\" *) \n LUT4 #(\n .INIT(16'h9555)) \n \\genblk8[0].left_edge_pb[3]_i_1 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .O(\\genblk8[0].left_edge_pb[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair43\" *) \n LUT5 #(\n .INIT(32'hAAAA9555)) \n \\genblk8[0].left_edge_pb[4]_i_1 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),\n .O(\\genblk8[0].left_edge_pb[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF00000004)) \n \\genblk8[0].left_edge_pb[5]_i_1 \n (.I0(Q[2]),\n .I1(Q[0]),\n .I2(Q[4]),\n .I3(Q[1]),\n .I4(Q[3]),\n .I5(rstdiv0_sync_r1_reg_rep__22),\n .O(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\genblk8[0].left_edge_pb[5]_i_2 \n (.I0(p_154_out),\n .I1(\\genblk8[0].left_loss_pb_reg[0]_1 ),\n .O(left_edge_pb));\n LUT6 #(\n .INIT(64'hAAAAAAAAA9999999)) \n \\genblk8[0].left_edge_pb[5]_i_3 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .O(\\genblk8[0].left_edge_pb[5]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\genblk8[0].left_edge_pb[5]_i_4 \n (.I0(match_flag_pb[7]),\n .I1(\\genblk8[0].left_edge_pb[5]_i_5_n_0 ),\n .I2(\\genblk7[0].compare_err_pb_latch_r_reg_n_0_[0] ),\n .I3(match_flag_pb[6]),\n .I4(match_flag_pb[4]),\n .I5(match_flag_pb[5]),\n .O(\\genblk8[0].left_loss_pb_reg[0]_1 ));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\genblk8[0].left_edge_pb[5]_i_5 \n (.I0(match_flag_pb[2]),\n .I1(match_flag_pb[3]),\n .I2(match_flag_pb[0]),\n .I3(match_flag_pb[1]),\n .O(\\genblk8[0].left_edge_pb[5]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[0].left_edge_pb_reg[0] \n (.C(CLK),\n .CE(left_edge_pb),\n .D(\\genblk8[0].left_edge_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[0].left_edge_pb_reg_n_0_[0] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[0].left_edge_pb_reg[1] \n (.C(CLK),\n .CE(left_edge_pb),\n .D(\\genblk8[0].left_edge_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[0].left_edge_pb_reg_n_0_[1] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[0].left_edge_pb_reg[2] \n (.C(CLK),\n .CE(left_edge_pb),\n .D(\\genblk8[0].left_edge_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[0].left_edge_pb_reg_n_0_[2] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[0].left_edge_pb_reg[3] \n (.C(CLK),\n .CE(left_edge_pb),\n .D(\\genblk8[0].left_edge_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[0].left_edge_pb_reg_n_0_[3] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[0].left_edge_pb_reg[4] \n (.C(CLK),\n .CE(left_edge_pb),\n .D(\\genblk8[0].left_edge_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[0].left_edge_pb_reg_n_0_[4] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[0].left_edge_pb_reg[5] \n (.C(CLK),\n .CE(left_edge_pb),\n .D(\\genblk8[0].left_edge_pb[5]_i_3_n_0 ),\n .Q(\\genblk8[0].left_edge_pb_reg_n_0_[5] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair50\" *) \n LUT4 #(\n .INIT(16'h0080)) \n \\genblk8[0].left_edge_updated[0]_i_2 \n (.I0(Q[0]),\n .I1(Q[2]),\n .I2(Q[3]),\n .I3(Q[4]),\n .O(\\genblk8[7].left_edge_updated_reg[7]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[0].left_edge_updated_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[0].left_edge_updated_reg[0]_0 ),\n .Q(D[0]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair79\" *) \n LUT3 #(\n .INIT(8'h40)) \n \\genblk8[0].left_loss_pb[0]_i_1 \n (.I0(\\genblk8[0].left_loss_pb_reg[5]_i_4_n_0 ),\n .I1(p_154_out),\n .I2(\\genblk8[0].left_loss_pb_reg[3]_i_2_n_7 ),\n .O(\\genblk8[0].left_loss_pb[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair80\" *) \n LUT3 #(\n .INIT(8'h40)) \n \\genblk8[0].left_loss_pb[1]_i_1 \n (.I0(\\genblk8[0].left_loss_pb_reg[5]_i_4_n_0 ),\n .I1(p_154_out),\n .I2(\\genblk8[0].left_loss_pb_reg[3]_i_2_n_6 ),\n .O(\\genblk8[0].left_loss_pb[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair80\" *) \n LUT3 #(\n .INIT(8'h40)) \n \\genblk8[0].left_loss_pb[2]_i_1 \n (.I0(\\genblk8[0].left_loss_pb_reg[5]_i_4_n_0 ),\n .I1(p_154_out),\n .I2(\\genblk8[0].left_loss_pb_reg[3]_i_2_n_5 ),\n .O(\\genblk8[0].left_loss_pb[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair79\" *) \n LUT3 #(\n .INIT(8'h40)) \n \\genblk8[0].left_loss_pb[3]_i_1 \n (.I0(\\genblk8[0].left_loss_pb_reg[5]_i_4_n_0 ),\n .I1(p_154_out),\n .I2(\\genblk8[0].left_loss_pb_reg[3]_i_2_n_4 ),\n .O(\\genblk8[0].left_loss_pb[3]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h6)) \n \\genblk8[0].left_loss_pb[3]_i_3 \n (.I0(left_edge_ref[3]),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),\n .O(\\genblk8[0].left_loss_pb[3]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\genblk8[0].left_loss_pb[3]_i_4 \n (.I0(left_edge_ref[1]),\n .O(\\genblk8[0].left_loss_pb[3]_i_4_n_0 ));\n LUT4 #(\n .INIT(16'h6966)) \n \\genblk8[0].left_loss_pb[3]_i_5 \n (.I0(left_edge_ref[3]),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),\n .I2(left_edge_ref[2]),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .O(\\genblk8[0].left_loss_pb[3]_i_5_n_0 ));\n LUT3 #(\n .INIT(8'h96)) \n \\genblk8[0].left_loss_pb[3]_i_6 \n (.I0(left_edge_ref[1]),\n .I1(left_edge_ref[2]),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .O(\\genblk8[0].left_loss_pb[3]_i_6_n_0 ));\n LUT2 #(\n .INIT(4'h6)) \n \\genblk8[0].left_loss_pb[3]_i_7 \n (.I0(left_edge_ref[1]),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .O(\\genblk8[0].left_loss_pb[3]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[0].left_loss_pb[3]_i_8 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I1(left_edge_ref[0]),\n .O(\\genblk8[0].left_loss_pb[3]_i_8_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair77\" *) \n LUT3 #(\n .INIT(8'h40)) \n \\genblk8[0].left_loss_pb[4]_i_1 \n (.I0(\\genblk8[0].left_loss_pb_reg[5]_i_4_n_0 ),\n .I1(p_154_out),\n .I2(\\genblk8[0].left_loss_pb_reg[5]_i_5_n_7 ),\n .O(\\genblk8[0].left_loss_pb[4]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAEFEAEAE)) \n \\genblk8[0].left_loss_pb[5]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(right_gain_pb),\n .I2(p_154_out),\n .I3(\\genblk8[0].left_loss_pb_reg[0]_0 ),\n .I4(\\genblk8[0].left_loss_pb_reg[0]_1 ),\n .O(\\genblk8[0].left_loss_pb[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFEAAA)) \n \\genblk8[0].left_loss_pb[5]_i_10 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'hB)) \n \\genblk8[0].left_loss_pb[5]_i_11 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),\n .I1(left_edge_ref[3]),\n .O(\\genblk8[0].left_loss_pb[5]_i_11_n_0 ));\n LUT4 #(\n .INIT(16'hD22D)) \n \\genblk8[0].left_loss_pb[5]_i_12 \n (.I0(left_edge_ref[4]),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I2(left_edge_ref[5]),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_12_n_0 ));\n LUT4 #(\n .INIT(16'hD22D)) \n \\genblk8[0].left_loss_pb[5]_i_13 \n (.I0(left_edge_ref[3]),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),\n .I2(left_edge_ref[4]),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_13_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFEAAA)) \n \\genblk8[0].left_loss_pb[5]_i_15 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_15_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFEAAA)) \n \\genblk8[0].left_loss_pb[5]_i_16 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFEAAA)) \n \\genblk8[0].left_loss_pb[5]_i_17 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFEAAA)) \n \\genblk8[0].left_loss_pb[5]_i_18 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_18_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair77\" *) \n LUT3 #(\n .INIT(8'h40)) \n \\genblk8[0].left_loss_pb[5]_i_2 \n (.I0(\\genblk8[0].left_loss_pb_reg[5]_i_4_n_0 ),\n .I1(p_154_out),\n .I2(\\genblk8[0].left_loss_pb_reg[5]_i_5_n_6 ),\n .O(\\genblk8[0].left_loss_pb[5]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFEAAA)) \n \\genblk8[0].left_loss_pb[5]_i_20 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFEAAA)) \n \\genblk8[0].left_loss_pb[5]_i_21 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_21_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFEAAA)) \n \\genblk8[0].left_loss_pb[5]_i_22 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_22_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFEAAA)) \n \\genblk8[0].left_loss_pb[5]_i_23 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_23_n_0 ));\n LUT6 #(\n .INIT(64'h0808088CCECECEE0)) \n \\genblk8[0].left_loss_pb[5]_i_24 \n (.I0(left_edge_ref[4]),\n .I1(left_edge_ref[5]),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I3(\\genblk8[0].left_loss_pb[5]_i_31_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_24_n_0 ));\n LUT6 #(\n .INIT(64'h8CCCCEEEE0000888)) \n \\genblk8[0].left_loss_pb[5]_i_25 \n (.I0(left_edge_ref[2]),\n .I1(left_edge_ref[3]),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[0].left_loss_pb[5]_i_25_n_0 ));\n LUT4 #(\n .INIT(16'hCB80)) \n \\genblk8[0].left_loss_pb[5]_i_26 \n (.I0(left_edge_ref[0]),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I3(left_edge_ref[1]),\n .O(\\genblk8[0].left_loss_pb[5]_i_26_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFEAAA)) \n \\genblk8[0].left_loss_pb[5]_i_27 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_27_n_0 ));\n LUT6 #(\n .INIT(64'h8484844221212118)) \n \\genblk8[0].left_loss_pb[5]_i_28 \n (.I0(left_edge_ref[4]),\n .I1(left_edge_ref[5]),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I3(\\genblk8[0].left_loss_pb[5]_i_31_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_28_n_0 ));\n LUT6 #(\n .INIT(64'h4222211118888444)) \n \\genblk8[0].left_loss_pb[5]_i_29 \n (.I0(left_edge_ref[2]),\n .I1(left_edge_ref[3]),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[0].left_loss_pb[5]_i_29_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair17\" *) \n LUT5 #(\n .INIT(32'h00400000)) \n \\genblk8[0].left_loss_pb[5]_i_3 \n (.I0(Q[4]),\n .I1(Q[2]),\n .I2(Q[0]),\n .I3(Q[1]),\n .I4(Q[3]),\n .O(right_gain_pb));\n LUT4 #(\n .INIT(16'h1842)) \n \\genblk8[0].left_loss_pb[5]_i_30 \n (.I0(left_edge_ref[0]),\n .I1(left_edge_ref[1]),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_30_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair64\" *) \n LUT3 #(\n .INIT(8'h80)) \n \\genblk8[0].left_loss_pb[5]_i_31 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_31_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFEAAA)) \n \\genblk8[0].left_loss_pb[5]_i_7 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFEAAA)) \n \\genblk8[0].left_loss_pb[5]_i_8 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFEAAA)) \n \\genblk8[0].left_loss_pb[5]_i_9 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_9_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[0].left_loss_pb_reg[0] \n (.C(CLK),\n .CE(\\genblk8[0].left_loss_pb[5]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[0].left_loss_pb_reg_n_0_[0] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[0].left_loss_pb_reg[1] \n (.C(CLK),\n .CE(\\genblk8[0].left_loss_pb[5]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[0].left_loss_pb_reg_n_0_[1] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[0].left_loss_pb_reg[2] \n (.C(CLK),\n .CE(\\genblk8[0].left_loss_pb[5]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[0].left_loss_pb_reg__0 [2]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[0].left_loss_pb_reg[3] \n (.C(CLK),\n .CE(\\genblk8[0].left_loss_pb[5]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[0].left_loss_pb_reg__0 [3]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n CARRY4 \\genblk8[0].left_loss_pb_reg[3]_i_2 \n (.CI(1'b0),\n .CO({\\genblk8[0].left_loss_pb_reg[3]_i_2_n_0 ,\\genblk8[0].left_loss_pb_reg[3]_i_2_n_1 ,\\genblk8[0].left_loss_pb_reg[3]_i_2_n_2 ,\\genblk8[0].left_loss_pb_reg[3]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({\\genblk8[0].left_loss_pb[3]_i_3_n_0 ,\\genblk8[0].left_loss_pb[3]_i_4_n_0 ,left_edge_ref[1],\\prbs_dqs_tap_cnt_r_reg_n_0_[0] }),\n .O({\\genblk8[0].left_loss_pb_reg[3]_i_2_n_4 ,\\genblk8[0].left_loss_pb_reg[3]_i_2_n_5 ,\\genblk8[0].left_loss_pb_reg[3]_i_2_n_6 ,\\genblk8[0].left_loss_pb_reg[3]_i_2_n_7 }),\n .S({\\genblk8[0].left_loss_pb[3]_i_5_n_0 ,\\genblk8[0].left_loss_pb[3]_i_6_n_0 ,\\genblk8[0].left_loss_pb[3]_i_7_n_0 ,\\genblk8[0].left_loss_pb[3]_i_8_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[0].left_loss_pb_reg[4] \n (.C(CLK),\n .CE(\\genblk8[0].left_loss_pb[5]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[0].left_loss_pb_reg__0 [4]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[0].left_loss_pb_reg[5] \n (.C(CLK),\n .CE(\\genblk8[0].left_loss_pb[5]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[5]_i_2_n_0 ),\n .Q(\\genblk8[0].left_loss_pb_reg__0 [5]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n CARRY4 \\genblk8[0].left_loss_pb_reg[5]_i_14 \n (.CI(\\genblk8[0].left_loss_pb_reg[5]_i_19_n_0 ),\n .CO({\\genblk8[0].left_loss_pb_reg[5]_i_14_n_0 ,\\genblk8[0].left_loss_pb_reg[5]_i_14_n_1 ,\\genblk8[0].left_loss_pb_reg[5]_i_14_n_2 ,\\genblk8[0].left_loss_pb_reg[5]_i_14_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[0].left_loss_pb_reg[5]_i_14_O_UNCONNECTED [3:0]),\n .S({\\genblk8[0].left_loss_pb[5]_i_20_n_0 ,\\genblk8[0].left_loss_pb[5]_i_21_n_0 ,\\genblk8[0].left_loss_pb[5]_i_22_n_0 ,\\genblk8[0].left_loss_pb[5]_i_23_n_0 }));\n CARRY4 \\genblk8[0].left_loss_pb_reg[5]_i_19 \n (.CI(1'b0),\n .CO({\\genblk8[0].left_loss_pb_reg[5]_i_19_n_0 ,\\genblk8[0].left_loss_pb_reg[5]_i_19_n_1 ,\\genblk8[0].left_loss_pb_reg[5]_i_19_n_2 ,\\genblk8[0].left_loss_pb_reg[5]_i_19_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,\\genblk8[0].left_loss_pb[5]_i_24_n_0 ,\\genblk8[0].left_loss_pb[5]_i_25_n_0 ,\\genblk8[0].left_loss_pb[5]_i_26_n_0 }),\n .O(\\NLW_genblk8[0].left_loss_pb_reg[5]_i_19_O_UNCONNECTED [3:0]),\n .S({\\genblk8[0].left_loss_pb[5]_i_27_n_0 ,\\genblk8[0].left_loss_pb[5]_i_28_n_0 ,\\genblk8[0].left_loss_pb[5]_i_29_n_0 ,\\genblk8[0].left_loss_pb[5]_i_30_n_0 }));\n CARRY4 \\genblk8[0].left_loss_pb_reg[5]_i_4 \n (.CI(\\genblk8[0].left_loss_pb_reg[5]_i_6_n_0 ),\n .CO({\\genblk8[0].left_loss_pb_reg[5]_i_4_n_0 ,\\genblk8[0].left_loss_pb_reg[5]_i_4_n_1 ,\\genblk8[0].left_loss_pb_reg[5]_i_4_n_2 ,\\genblk8[0].left_loss_pb_reg[5]_i_4_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[0].left_loss_pb_reg[5]_i_4_O_UNCONNECTED [3:0]),\n .S({\\genblk8[0].left_loss_pb[5]_i_7_n_0 ,\\genblk8[0].left_loss_pb[5]_i_8_n_0 ,\\genblk8[0].left_loss_pb[5]_i_9_n_0 ,\\genblk8[0].left_loss_pb[5]_i_10_n_0 }));\n CARRY4 \\genblk8[0].left_loss_pb_reg[5]_i_5 \n (.CI(\\genblk8[0].left_loss_pb_reg[3]_i_2_n_0 ),\n .CO({\\NLW_genblk8[0].left_loss_pb_reg[5]_i_5_CO_UNCONNECTED [3:1],\\genblk8[0].left_loss_pb_reg[5]_i_5_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,\\genblk8[0].left_loss_pb[5]_i_11_n_0 }),\n .O({\\NLW_genblk8[0].left_loss_pb_reg[5]_i_5_O_UNCONNECTED [3:2],\\genblk8[0].left_loss_pb_reg[5]_i_5_n_6 ,\\genblk8[0].left_loss_pb_reg[5]_i_5_n_7 }),\n .S({1'b0,1'b0,\\genblk8[0].left_loss_pb[5]_i_12_n_0 ,\\genblk8[0].left_loss_pb[5]_i_13_n_0 }));\n CARRY4 \\genblk8[0].left_loss_pb_reg[5]_i_6 \n (.CI(\\genblk8[0].left_loss_pb_reg[5]_i_14_n_0 ),\n .CO({\\genblk8[0].left_loss_pb_reg[5]_i_6_n_0 ,\\genblk8[0].left_loss_pb_reg[5]_i_6_n_1 ,\\genblk8[0].left_loss_pb_reg[5]_i_6_n_2 ,\\genblk8[0].left_loss_pb_reg[5]_i_6_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[0].left_loss_pb_reg[5]_i_6_O_UNCONNECTED [3:0]),\n .S({\\genblk8[0].left_loss_pb[5]_i_15_n_0 ,\\genblk8[0].left_loss_pb[5]_i_16_n_0 ,\\genblk8[0].left_loss_pb[5]_i_17_n_0 ,\\genblk8[0].left_loss_pb[5]_i_18_n_0 }));\n LUT3 #(\n .INIT(8'hBA)) \n \\genblk8[0].match_flag_pb[7]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(p_154_out),\n .I2(right_gain_pb),\n .O(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0002000000000000)) \n \\genblk8[0].match_flag_pb[7]_i_2 \n (.I0(num_samples_done_r),\n .I1(Q[3]),\n .I2(Q[2]),\n .I3(Q[1]),\n .I4(Q[4]),\n .I5(Q[0]),\n .O(p_154_out));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[0].match_flag_pb_reg[0] \n (.C(CLK),\n .CE(p_154_out),\n .D(\\genblk7[0].compare_err_pb_latch_r_reg_n_0_[0] ),\n .Q(match_flag_pb[0]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[0].match_flag_pb_reg[1] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[0]),\n .Q(match_flag_pb[1]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[0].match_flag_pb_reg[2] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[1]),\n .Q(match_flag_pb[2]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[0].match_flag_pb_reg[3] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[2]),\n .Q(match_flag_pb[3]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[0].match_flag_pb_reg[4] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[3]),\n .Q(match_flag_pb[4]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[0].match_flag_pb_reg[5] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[4]),\n .Q(match_flag_pb[5]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[0].match_flag_pb_reg[6] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[5]),\n .Q(match_flag_pb[6]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[0].match_flag_pb_reg[7] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[6]),\n .Q(match_flag_pb[7]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[0].right_edge_found_pb_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[0].right_edge_found_pb_reg[0]_0 ),\n .Q(\\genblk8[0].right_edge_pb_reg[0]_0 ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair76\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[0].right_edge_pb[1]_i_1 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I1(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .O(\\genblk8[0].right_edge_pb[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair76\" *) \n LUT3 #(\n .INIT(8'hA9)) \n \\genblk8[0].right_edge_pb[2]_i_1 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .O(\\genblk8[0].right_edge_pb[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair62\" *) \n LUT4 #(\n .INIT(16'hAAA9)) \n \\genblk8[0].right_edge_pb[3]_i_1 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I1(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .O(\\genblk8[0].right_edge_pb[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair44\" *) \n LUT5 #(\n .INIT(32'hAAAAAAA9)) \n \\genblk8[0].right_edge_pb[4]_i_1 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .O(\\genblk8[0].right_edge_pb[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAABAAAAAAAAA)) \n \\genblk8[0].right_edge_pb[5]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(\\genblk8[0].left_loss_pb_reg[0]_1 ),\n .I2(p_154_out),\n .I3(\\genblk8[0].right_edge_pb_reg[0]_1 ),\n .I4(\\genblk8[0].right_edge_pb_reg[0]_0 ),\n .I5(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .O(\\genblk8[0].right_edge_pb[5]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h08)) \n \\genblk8[0].right_edge_pb[5]_i_2 \n (.I0(p_154_out),\n .I1(\\genblk8[0].right_edge_pb_reg[0]_1 ),\n .I2(\\genblk8[0].left_loss_pb_reg[0]_1 ),\n .O(\\genblk8[0].right_edge_pb[5]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAAAAA9)) \n \\genblk8[0].right_edge_pb[5]_i_3 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .O(\\genblk8[0].right_edge_pb[5]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\genblk8[0].right_edge_pb[5]_i_4 \n (.I0(\\genblk7[0].compare_err_pb_latch_r_reg_n_0_[0] ),\n .I1(\\genblk8[0].left_edge_pb[5]_i_5_n_0 ),\n .I2(match_flag_pb[7]),\n .I3(match_flag_pb[6]),\n .I4(match_flag_pb[4]),\n .I5(match_flag_pb[5]),\n .O(\\genblk8[0].right_edge_pb_reg[0]_1 ));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\genblk8[0].right_edge_pb[5]_i_5 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .O(\\genblk8[7].right_edge_pb_reg[42]_1 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[0].right_edge_pb_reg[0] \n (.C(CLK),\n .CE(\\genblk8[0].right_edge_pb[5]_i_2_n_0 ),\n .D(\\genblk8[0].left_edge_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[0].right_edge_pb_reg_n_0_[0] ),\n .S(\\genblk8[0].right_edge_pb[5]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[0].right_edge_pb_reg[1] \n (.C(CLK),\n .CE(\\genblk8[0].right_edge_pb[5]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[0].right_edge_pb_reg_n_0_[1] ),\n .S(\\genblk8[0].right_edge_pb[5]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[0].right_edge_pb_reg[2] \n (.C(CLK),\n .CE(\\genblk8[0].right_edge_pb[5]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[0].right_edge_pb_reg_n_0_[2] ),\n .S(\\genblk8[0].right_edge_pb[5]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[0].right_edge_pb_reg[3] \n (.C(CLK),\n .CE(\\genblk8[0].right_edge_pb[5]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[0].right_edge_pb_reg_n_0_[3] ),\n .S(\\genblk8[0].right_edge_pb[5]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[0].right_edge_pb_reg[4] \n (.C(CLK),\n .CE(\\genblk8[0].right_edge_pb[5]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[0].right_edge_pb_reg_n_0_[4] ),\n .S(\\genblk8[0].right_edge_pb[5]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[0].right_edge_pb_reg[5] \n (.C(CLK),\n .CE(\\genblk8[0].right_edge_pb[5]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[5]_i_3_n_0 ),\n .Q(\\genblk8[0].right_edge_pb_reg_n_0_[5] ),\n .S(\\genblk8[0].right_edge_pb[5]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[0].right_gain_pb[0]_i_1 \n (.I0(\\genblk8[0].right_edge_pb_reg[0]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[0].right_gain_pb_reg[3]_i_2_n_7 ),\n .I3(\\genblk8[0].right_gain_pb_reg[3]_i_3_n_7 ),\n .O(\\genblk8[0].right_gain_pb[0]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[0].right_gain_pb[1]_i_1 \n (.I0(\\genblk8[0].right_edge_pb_reg[0]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[0].right_gain_pb_reg[3]_i_2_n_6 ),\n .I3(\\genblk8[0].right_gain_pb_reg[3]_i_3_n_6 ),\n .O(\\genblk8[0].right_gain_pb[1]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[0].right_gain_pb[2]_i_1 \n (.I0(\\genblk8[0].right_edge_pb_reg[0]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[0].right_gain_pb_reg[3]_i_2_n_5 ),\n .I3(\\genblk8[0].right_gain_pb_reg[3]_i_3_n_5 ),\n .O(\\genblk8[0].right_gain_pb[2]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[0].right_gain_pb[3]_i_1 \n (.I0(\\genblk8[0].right_edge_pb_reg[0]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[0].right_gain_pb_reg[3]_i_2_n_4 ),\n .I3(\\genblk8[0].right_gain_pb_reg[3]_i_3_n_4 ),\n .O(\\genblk8[0].right_gain_pb[3]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[0].right_gain_pb[3]_i_10 \n (.I0(right_edge_ref[1]),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[1] ),\n .O(\\genblk8[0].right_gain_pb[3]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[0].right_gain_pb[3]_i_11 \n (.I0(right_edge_ref[0]),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[0] ),\n .O(\\genblk8[0].right_gain_pb[3]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[0].right_gain_pb[3]_i_4 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[3] ),\n .O(\\genblk8[0].right_gain_pb[3]_i_4_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[0].right_gain_pb[3]_i_5 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[2] ),\n .O(\\genblk8[0].right_gain_pb[3]_i_5_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[0].right_gain_pb[3]_i_6 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[1] ),\n .O(\\genblk8[0].right_gain_pb[3]_i_6_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[0].right_gain_pb[3]_i_7 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[0] ),\n .O(\\genblk8[0].right_gain_pb[3]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[0].right_gain_pb[3]_i_8 \n (.I0(right_edge_ref[3]),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[3] ),\n .O(\\genblk8[0].right_gain_pb[3]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[0].right_gain_pb[3]_i_9 \n (.I0(right_edge_ref[2]),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[2] ),\n .O(\\genblk8[0].right_gain_pb[3]_i_9_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[0].right_gain_pb[4]_i_1 \n (.I0(\\genblk8[0].right_edge_pb_reg[0]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[0].right_gain_pb_reg[5]_i_6_n_7 ),\n .I3(\\genblk8[0].right_gain_pb_reg[5]_i_7_n_7 ),\n .O(\\genblk8[0].right_gain_pb[4]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAEFEAEAE)) \n \\genblk8[0].right_gain_pb[5]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(right_gain_pb),\n .I2(p_154_out),\n .I3(\\genblk8[0].left_loss_pb_reg[0]_1 ),\n .I4(\\genblk8[0].right_gain_pb_reg[5]_i_4_n_0 ),\n .O(\\genblk8[0].right_gain_pb[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_11 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_12 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_12_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_13 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_13_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_14 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_14_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[0].right_gain_pb[5]_i_15 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_15_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[0].right_gain_pb[5]_i_16 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[4] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_16_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[0].right_gain_pb[5]_i_17 \n (.I0(right_edge_ref[5]),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_17_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[0].right_gain_pb[5]_i_18 \n (.I0(right_edge_ref[4]),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[4] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_18_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk8[0].right_gain_pb[5]_i_19 \n (.I0(\\genblk8[0].right_gain_pb[5]_i_27_n_0 ),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[3] ),\n .I2(right_edge_ref[3]),\n .I3(\\genblk8[0].right_edge_pb_reg_n_0_[4] ),\n .I4(right_edge_ref[4]),\n .O(\\genblk8[0].right_gain_pb[5]_i_19_n_0 ));\n LUT5 #(\n .INIT(32'h000000A8)) \n \\genblk8[0].right_gain_pb[5]_i_2 \n (.I0(p_154_out),\n .I1(\\genblk8[0].right_edge_pb_reg[0]_1 ),\n .I2(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .I3(\\genblk8[0].right_edge_pb_reg[0]_0 ),\n .I4(\\genblk8[0].left_loss_pb_reg[0]_1 ),\n .O(\\genblk8[0].right_gain_pb[5]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk8[0].right_gain_pb[5]_i_20 \n (.I0(\\genblk8[0].right_gain_pb[5]_i_28_n_0 ),\n .I1(right_edge_ref[3]),\n .I2(\\genblk8[0].right_edge_pb_reg_n_0_[3] ),\n .I3(right_edge_ref[4]),\n .I4(\\genblk8[0].right_edge_pb_reg_n_0_[4] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_23 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_23_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_24 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_24_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_25 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_25_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_26 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_26_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk8[0].right_gain_pb[5]_i_27 \n (.I0(right_edge_ref[0]),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[0] ),\n .I2(\\genblk8[0].right_edge_pb_reg_n_0_[1] ),\n .I3(right_edge_ref[1]),\n .I4(\\genblk8[0].right_edge_pb_reg_n_0_[2] ),\n .I5(right_edge_ref[2]),\n .O(\\genblk8[0].right_gain_pb[5]_i_27_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk8[0].right_gain_pb[5]_i_28 \n (.I0(\\genblk8[0].right_edge_pb_reg_n_0_[0] ),\n .I1(right_edge_ref[0]),\n .I2(right_edge_ref[1]),\n .I3(\\genblk8[0].right_edge_pb_reg_n_0_[1] ),\n .I4(right_edge_ref[2]),\n .I5(\\genblk8[0].right_edge_pb_reg_n_0_[2] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_28_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[0].right_gain_pb[5]_i_3 \n (.I0(\\genblk8[0].right_edge_pb_reg[0]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[0].right_gain_pb_reg[5]_i_6_n_6 ),\n .I3(\\genblk8[0].right_gain_pb_reg[5]_i_7_n_6 ),\n .O(\\genblk8[0].right_gain_pb[5]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_30 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_30_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_31 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_31_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_32 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_32_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_33 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_33_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_35 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_35_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_36 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_36_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_37 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_37_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_38 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_38_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_40 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_40_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_41 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_41_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_42 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_42_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_43 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_43_n_0 ));\n LUT4 #(\n .INIT(16'hF880)) \n \\genblk8[0].right_gain_pb[5]_i_44 \n (.I0(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I1(right_edge_ref[4]),\n .I2(right_edge_ref[5]),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[0].right_gain_pb[5]_i_44_n_0 ));\n LUT6 #(\n .INIT(64'h0808088CCECECEE0)) \n \\genblk8[0].right_gain_pb[5]_i_45 \n (.I0(right_edge_ref[2]),\n .I1(right_edge_ref[3]),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .O(\\genblk8[0].right_gain_pb[5]_i_45_n_0 ));\n LUT4 #(\n .INIT(16'h8CE0)) \n \\genblk8[0].right_gain_pb[5]_i_46 \n (.I0(right_edge_ref[0]),\n .I1(right_edge_ref[1]),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .O(\\genblk8[0].right_gain_pb[5]_i_46_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_47 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_47_n_0 ));\n LUT4 #(\n .INIT(16'h0660)) \n \\genblk8[0].right_gain_pb[5]_i_48 \n (.I0(right_edge_ref[4]),\n .I1(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I2(right_edge_ref[5]),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[0].right_gain_pb[5]_i_48_n_0 ));\n LUT6 #(\n .INIT(64'h8484844221212118)) \n \\genblk8[0].right_gain_pb[5]_i_49 \n (.I0(right_edge_ref[2]),\n .I1(right_edge_ref[3]),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .O(\\genblk8[0].right_gain_pb[5]_i_49_n_0 ));\n LUT4 #(\n .INIT(16'h4218)) \n \\genblk8[0].right_gain_pb[5]_i_50 \n (.I0(right_edge_ref[0]),\n .I1(right_edge_ref[1]),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .O(\\genblk8[0].right_gain_pb[5]_i_50_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_52 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_52_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_53 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_53_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_54 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_54_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_55 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_55_n_0 ));\n LUT4 #(\n .INIT(16'hF880)) \n \\genblk8[0].right_gain_pb[5]_i_56 \n (.I0(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[4] ),\n .I2(\\genblk8[0].right_edge_pb_reg_n_0_[5] ),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[0].right_gain_pb[5]_i_56_n_0 ));\n LUT6 #(\n .INIT(64'h0808088CCECECEE0)) \n \\genblk8[0].right_gain_pb[5]_i_57 \n (.I0(\\genblk8[0].right_edge_pb_reg_n_0_[2] ),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[3] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[0].right_gain_pb[5]_i_57_n_0 ));\n LUT4 #(\n .INIT(16'h8CE0)) \n \\genblk8[0].right_gain_pb[5]_i_58 \n (.I0(\\genblk8[0].right_edge_pb_reg_n_0_[0] ),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[1] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\genblk8[0].right_gain_pb[5]_i_58_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_59 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_59_n_0 ));\n LUT4 #(\n .INIT(16'h0660)) \n \\genblk8[0].right_gain_pb[5]_i_60 \n (.I0(\\genblk8[0].right_edge_pb_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I2(\\genblk8[0].right_edge_pb_reg_n_0_[5] ),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[0].right_gain_pb[5]_i_60_n_0 ));\n LUT6 #(\n .INIT(64'h8484844221212118)) \n \\genblk8[0].right_gain_pb[5]_i_61 \n (.I0(\\genblk8[0].right_edge_pb_reg_n_0_[2] ),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[3] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[0].right_gain_pb[5]_i_61_n_0 ));\n LUT4 #(\n .INIT(16'h4218)) \n \\genblk8[0].right_gain_pb[5]_i_62 \n (.I0(\\genblk8[0].right_edge_pb_reg_n_0_[0] ),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[1] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\genblk8[0].right_gain_pb[5]_i_62_n_0 ));\n LUT5 #(\n .INIT(32'h04004404)) \n \\genblk8[0].right_gain_pb[5]_i_8 \n (.I0(\\genblk8[0].right_edge_pb_reg[0]_0 ),\n .I1(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .I2(right_edge_ref[5]),\n .I3(\\genblk8[0].right_edge_pb_reg_n_0_[5] ),\n .I4(\\genblk8[0].right_gain_pb[5]_i_19_n_0 ),\n .O(\\genblk8[0].right_gain_pb[5]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FFB200B2)) \n \\genblk8[0].right_gain_pb[5]_i_9 \n (.I0(\\genblk8[0].right_edge_pb_reg_n_0_[5] ),\n .I1(right_edge_ref[5]),\n .I2(\\genblk8[0].right_gain_pb[5]_i_20_n_0 ),\n .I3(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I4(\\genblk8[0].right_gain_pb_reg[5]_i_21_n_0 ),\n .I5(\\genblk8[0].right_edge_pb_reg[0]_0 ),\n .O(\\genblk8[0].right_gain_pb[5]_i_9_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[0].right_gain_pb_reg[0] \n (.C(CLK),\n .CE(\\genblk8[0].right_gain_pb[5]_i_2_n_0 ),\n .D(\\genblk8[0].right_gain_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[0].right_gain_pb_reg_n_0_[0] ),\n .R(\\genblk8[0].right_gain_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[0].right_gain_pb_reg[1] \n (.C(CLK),\n .CE(\\genblk8[0].right_gain_pb[5]_i_2_n_0 ),\n .D(\\genblk8[0].right_gain_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[0].right_gain_pb_reg_n_0_[1] ),\n .R(\\genblk8[0].right_gain_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[0].right_gain_pb_reg[2] \n (.C(CLK),\n .CE(\\genblk8[0].right_gain_pb[5]_i_2_n_0 ),\n .D(\\genblk8[0].right_gain_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[0].right_gain_pb_reg__0 [2]),\n .R(\\genblk8[0].right_gain_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[0].right_gain_pb_reg[3] \n (.C(CLK),\n .CE(\\genblk8[0].right_gain_pb[5]_i_2_n_0 ),\n .D(\\genblk8[0].right_gain_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[0].right_gain_pb_reg__0 [3]),\n .R(\\genblk8[0].right_gain_pb[5]_i_1_n_0 ));\n CARRY4 \\genblk8[0].right_gain_pb_reg[3]_i_2 \n (.CI(1'b0),\n .CO({\\genblk8[0].right_gain_pb_reg[3]_i_2_n_0 ,\\genblk8[0].right_gain_pb_reg[3]_i_2_n_1 ,\\genblk8[0].right_gain_pb_reg[3]_i_2_n_2 ,\\genblk8[0].right_gain_pb_reg[3]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ,\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ,\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ,\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }),\n .O({\\genblk8[0].right_gain_pb_reg[3]_i_2_n_4 ,\\genblk8[0].right_gain_pb_reg[3]_i_2_n_5 ,\\genblk8[0].right_gain_pb_reg[3]_i_2_n_6 ,\\genblk8[0].right_gain_pb_reg[3]_i_2_n_7 }),\n .S({\\genblk8[0].right_gain_pb[3]_i_4_n_0 ,\\genblk8[0].right_gain_pb[3]_i_5_n_0 ,\\genblk8[0].right_gain_pb[3]_i_6_n_0 ,\\genblk8[0].right_gain_pb[3]_i_7_n_0 }));\n CARRY4 \\genblk8[0].right_gain_pb_reg[3]_i_3 \n (.CI(1'b0),\n .CO({\\genblk8[0].right_gain_pb_reg[3]_i_3_n_0 ,\\genblk8[0].right_gain_pb_reg[3]_i_3_n_1 ,\\genblk8[0].right_gain_pb_reg[3]_i_3_n_2 ,\\genblk8[0].right_gain_pb_reg[3]_i_3_n_3 }),\n .CYINIT(1'b1),\n .DI(right_edge_ref[3:0]),\n .O({\\genblk8[0].right_gain_pb_reg[3]_i_3_n_4 ,\\genblk8[0].right_gain_pb_reg[3]_i_3_n_5 ,\\genblk8[0].right_gain_pb_reg[3]_i_3_n_6 ,\\genblk8[0].right_gain_pb_reg[3]_i_3_n_7 }),\n .S({\\genblk8[0].right_gain_pb[3]_i_8_n_0 ,\\genblk8[0].right_gain_pb[3]_i_9_n_0 ,\\genblk8[0].right_gain_pb[3]_i_10_n_0 ,\\genblk8[0].right_gain_pb[3]_i_11_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[0].right_gain_pb_reg[4] \n (.C(CLK),\n .CE(\\genblk8[0].right_gain_pb[5]_i_2_n_0 ),\n .D(\\genblk8[0].right_gain_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[0].right_gain_pb_reg__0 [4]),\n .R(\\genblk8[0].right_gain_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[0].right_gain_pb_reg[5] \n (.C(CLK),\n .CE(\\genblk8[0].right_gain_pb[5]_i_2_n_0 ),\n .D(\\genblk8[0].right_gain_pb[5]_i_3_n_0 ),\n .Q(\\genblk8[0].right_gain_pb_reg__0 [5]),\n .R(\\genblk8[0].right_gain_pb[5]_i_1_n_0 ));\n CARRY4 \\genblk8[0].right_gain_pb_reg[5]_i_10 \n (.CI(\\genblk8[0].right_gain_pb_reg[5]_i_22_n_0 ),\n .CO({\\genblk8[0].right_gain_pb_reg[5]_i_10_n_0 ,\\genblk8[0].right_gain_pb_reg[5]_i_10_n_1 ,\\genblk8[0].right_gain_pb_reg[5]_i_10_n_2 ,\\genblk8[0].right_gain_pb_reg[5]_i_10_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[0].right_gain_pb_reg[5]_i_10_O_UNCONNECTED [3:0]),\n .S({\\genblk8[0].right_gain_pb[5]_i_23_n_0 ,\\genblk8[0].right_gain_pb[5]_i_24_n_0 ,\\genblk8[0].right_gain_pb[5]_i_25_n_0 ,\\genblk8[0].right_gain_pb[5]_i_26_n_0 }));\n CARRY4 \\genblk8[0].right_gain_pb_reg[5]_i_21 \n (.CI(\\genblk8[0].right_gain_pb_reg[5]_i_29_n_0 ),\n .CO({\\genblk8[0].right_gain_pb_reg[5]_i_21_n_0 ,\\genblk8[0].right_gain_pb_reg[5]_i_21_n_1 ,\\genblk8[0].right_gain_pb_reg[5]_i_21_n_2 ,\\genblk8[0].right_gain_pb_reg[5]_i_21_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[0].right_gain_pb_reg[5]_i_21_O_UNCONNECTED [3:0]),\n .S({\\genblk8[0].right_gain_pb[5]_i_30_n_0 ,\\genblk8[0].right_gain_pb[5]_i_31_n_0 ,\\genblk8[0].right_gain_pb[5]_i_32_n_0 ,\\genblk8[0].right_gain_pb[5]_i_33_n_0 }));\n CARRY4 \\genblk8[0].right_gain_pb_reg[5]_i_22 \n (.CI(\\genblk8[0].right_gain_pb_reg[5]_i_34_n_0 ),\n .CO({\\genblk8[0].right_gain_pb_reg[5]_i_22_n_0 ,\\genblk8[0].right_gain_pb_reg[5]_i_22_n_1 ,\\genblk8[0].right_gain_pb_reg[5]_i_22_n_2 ,\\genblk8[0].right_gain_pb_reg[5]_i_22_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[0].right_gain_pb_reg[5]_i_22_O_UNCONNECTED [3:0]),\n .S({\\genblk8[0].right_gain_pb[5]_i_35_n_0 ,\\genblk8[0].right_gain_pb[5]_i_36_n_0 ,\\genblk8[0].right_gain_pb[5]_i_37_n_0 ,\\genblk8[0].right_gain_pb[5]_i_38_n_0 }));\n CARRY4 \\genblk8[0].right_gain_pb_reg[5]_i_29 \n (.CI(\\genblk8[0].right_gain_pb_reg[5]_i_39_n_0 ),\n .CO({\\genblk8[0].right_gain_pb_reg[5]_i_29_n_0 ,\\genblk8[0].right_gain_pb_reg[5]_i_29_n_1 ,\\genblk8[0].right_gain_pb_reg[5]_i_29_n_2 ,\\genblk8[0].right_gain_pb_reg[5]_i_29_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[0].right_gain_pb_reg[5]_i_29_O_UNCONNECTED [3:0]),\n .S({\\genblk8[0].right_gain_pb[5]_i_40_n_0 ,\\genblk8[0].right_gain_pb[5]_i_41_n_0 ,\\genblk8[0].right_gain_pb[5]_i_42_n_0 ,\\genblk8[0].right_gain_pb[5]_i_43_n_0 }));\n CARRY4 \\genblk8[0].right_gain_pb_reg[5]_i_34 \n (.CI(1'b0),\n .CO({\\genblk8[0].right_gain_pb_reg[5]_i_34_n_0 ,\\genblk8[0].right_gain_pb_reg[5]_i_34_n_1 ,\\genblk8[0].right_gain_pb_reg[5]_i_34_n_2 ,\\genblk8[0].right_gain_pb_reg[5]_i_34_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,\\genblk8[0].right_gain_pb[5]_i_44_n_0 ,\\genblk8[0].right_gain_pb[5]_i_45_n_0 ,\\genblk8[0].right_gain_pb[5]_i_46_n_0 }),\n .O(\\NLW_genblk8[0].right_gain_pb_reg[5]_i_34_O_UNCONNECTED [3:0]),\n .S({\\genblk8[0].right_gain_pb[5]_i_47_n_0 ,\\genblk8[0].right_gain_pb[5]_i_48_n_0 ,\\genblk8[0].right_gain_pb[5]_i_49_n_0 ,\\genblk8[0].right_gain_pb[5]_i_50_n_0 }));\n CARRY4 \\genblk8[0].right_gain_pb_reg[5]_i_39 \n (.CI(\\genblk8[0].right_gain_pb_reg[5]_i_51_n_0 ),\n .CO({\\genblk8[0].right_gain_pb_reg[5]_i_39_n_0 ,\\genblk8[0].right_gain_pb_reg[5]_i_39_n_1 ,\\genblk8[0].right_gain_pb_reg[5]_i_39_n_2 ,\\genblk8[0].right_gain_pb_reg[5]_i_39_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[0].right_gain_pb_reg[5]_i_39_O_UNCONNECTED [3:0]),\n .S({\\genblk8[0].right_gain_pb[5]_i_52_n_0 ,\\genblk8[0].right_gain_pb[5]_i_53_n_0 ,\\genblk8[0].right_gain_pb[5]_i_54_n_0 ,\\genblk8[0].right_gain_pb[5]_i_55_n_0 }));\n MUXF7 \\genblk8[0].right_gain_pb_reg[5]_i_4 \n (.I0(\\genblk8[0].right_gain_pb[5]_i_8_n_0 ),\n .I1(\\genblk8[0].right_gain_pb[5]_i_9_n_0 ),\n .O(\\genblk8[0].right_gain_pb_reg[5]_i_4_n_0 ),\n .S(\\genblk8[0].right_edge_pb_reg[0]_1 ));\n CARRY4 \\genblk8[0].right_gain_pb_reg[5]_i_5 \n (.CI(\\genblk8[0].right_gain_pb_reg[5]_i_10_n_0 ),\n .CO({\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ,\\genblk8[0].right_gain_pb_reg[5]_i_5_n_1 ,\\genblk8[0].right_gain_pb_reg[5]_i_5_n_2 ,\\genblk8[0].right_gain_pb_reg[5]_i_5_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[0].right_gain_pb_reg[5]_i_5_O_UNCONNECTED [3:0]),\n .S({\\genblk8[0].right_gain_pb[5]_i_11_n_0 ,\\genblk8[0].right_gain_pb[5]_i_12_n_0 ,\\genblk8[0].right_gain_pb[5]_i_13_n_0 ,\\genblk8[0].right_gain_pb[5]_i_14_n_0 }));\n CARRY4 \\genblk8[0].right_gain_pb_reg[5]_i_51 \n (.CI(1'b0),\n .CO({\\genblk8[0].right_gain_pb_reg[5]_i_51_n_0 ,\\genblk8[0].right_gain_pb_reg[5]_i_51_n_1 ,\\genblk8[0].right_gain_pb_reg[5]_i_51_n_2 ,\\genblk8[0].right_gain_pb_reg[5]_i_51_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,\\genblk8[0].right_gain_pb[5]_i_56_n_0 ,\\genblk8[0].right_gain_pb[5]_i_57_n_0 ,\\genblk8[0].right_gain_pb[5]_i_58_n_0 }),\n .O(\\NLW_genblk8[0].right_gain_pb_reg[5]_i_51_O_UNCONNECTED [3:0]),\n .S({\\genblk8[0].right_gain_pb[5]_i_59_n_0 ,\\genblk8[0].right_gain_pb[5]_i_60_n_0 ,\\genblk8[0].right_gain_pb[5]_i_61_n_0 ,\\genblk8[0].right_gain_pb[5]_i_62_n_0 }));\n CARRY4 \\genblk8[0].right_gain_pb_reg[5]_i_6 \n (.CI(\\genblk8[0].right_gain_pb_reg[3]_i_2_n_0 ),\n .CO({\\NLW_genblk8[0].right_gain_pb_reg[5]_i_6_CO_UNCONNECTED [3:1],\\genblk8[0].right_gain_pb_reg[5]_i_6_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,\\prbs_dqs_tap_cnt_r_reg_n_0_[4] }),\n .O({\\NLW_genblk8[0].right_gain_pb_reg[5]_i_6_O_UNCONNECTED [3:2],\\genblk8[0].right_gain_pb_reg[5]_i_6_n_6 ,\\genblk8[0].right_gain_pb_reg[5]_i_6_n_7 }),\n .S({1'b0,1'b0,\\genblk8[0].right_gain_pb[5]_i_15_n_0 ,\\genblk8[0].right_gain_pb[5]_i_16_n_0 }));\n CARRY4 \\genblk8[0].right_gain_pb_reg[5]_i_7 \n (.CI(\\genblk8[0].right_gain_pb_reg[3]_i_3_n_0 ),\n .CO({\\NLW_genblk8[0].right_gain_pb_reg[5]_i_7_CO_UNCONNECTED [3:1],\\genblk8[0].right_gain_pb_reg[5]_i_7_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,right_edge_ref[4]}),\n .O({\\NLW_genblk8[0].right_gain_pb_reg[5]_i_7_O_UNCONNECTED [3:2],\\genblk8[0].right_gain_pb_reg[5]_i_7_n_6 ,\\genblk8[0].right_gain_pb_reg[5]_i_7_n_7 }),\n .S({1'b0,1'b0,\\genblk8[0].right_gain_pb[5]_i_17_n_0 ,\\genblk8[0].right_gain_pb[5]_i_18_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[1].left_edge_found_pb_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[1].left_edge_found_pb_reg[1]_0 ),\n .Q(\\genblk8[1].left_loss_pb_reg[6]_0 ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\genblk8[1].left_edge_pb[11]_i_1 \n (.I0(p_154_out),\n .I1(p_146_out),\n .O(\\genblk8[1].left_edge_pb[11]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\genblk8[1].left_edge_pb[11]_i_2 \n (.I0(match_flag_pb[15]),\n .I1(\\genblk8[1].left_edge_pb[11]_i_3_n_0 ),\n .I2(\\genblk7[1].compare_err_pb_latch_r_reg_n_0_[1] ),\n .I3(match_flag_pb[14]),\n .I4(match_flag_pb[12]),\n .I5(match_flag_pb[13]),\n .O(p_146_out));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\genblk8[1].left_edge_pb[11]_i_3 \n (.I0(match_flag_pb[10]),\n .I1(match_flag_pb[11]),\n .I2(match_flag_pb[8]),\n .I3(match_flag_pb[9]),\n .O(\\genblk8[1].left_edge_pb[11]_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[1].left_edge_pb_reg[10] \n (.C(CLK),\n .CE(\\genblk8[1].left_edge_pb[11]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[1].left_edge_pb_reg_n_0_[10] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[1].left_edge_pb_reg[11] \n (.C(CLK),\n .CE(\\genblk8[1].left_edge_pb[11]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[5]_i_3_n_0 ),\n .Q(\\genblk8[1].left_edge_pb_reg_n_0_[11] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[1].left_edge_pb_reg[6] \n (.C(CLK),\n .CE(\\genblk8[1].left_edge_pb[11]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[1].left_edge_pb_reg_n_0_[6] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[1].left_edge_pb_reg[7] \n (.C(CLK),\n .CE(\\genblk8[1].left_edge_pb[11]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[1].left_edge_pb_reg_n_0_[7] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[1].left_edge_pb_reg[8] \n (.C(CLK),\n .CE(\\genblk8[1].left_edge_pb[11]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[1].left_edge_pb_reg_n_0_[8] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[1].left_edge_pb_reg[9] \n (.C(CLK),\n .CE(\\genblk8[1].left_edge_pb[11]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[1].left_edge_pb_reg_n_0_[9] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[1].left_edge_updated_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[1].left_edge_updated_reg[1]_0 ),\n .Q(D[1]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAEFEAEAE)) \n \\genblk8[1].left_loss_pb[11]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(right_gain_pb),\n .I2(p_154_out),\n .I3(\\genblk8[1].left_loss_pb_reg[6]_0 ),\n .I4(p_146_out),\n .O(\\genblk8[1].left_loss_pb[11]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[1].left_loss_pb_reg[10] \n (.C(CLK),\n .CE(\\genblk8[1].left_loss_pb[11]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[1].left_loss_pb_reg__0 [4]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[1].left_loss_pb_reg[11] \n (.C(CLK),\n .CE(\\genblk8[1].left_loss_pb[11]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[5]_i_2_n_0 ),\n .Q(\\genblk8[1].left_loss_pb_reg__0 [5]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[1].left_loss_pb_reg[6] \n (.C(CLK),\n .CE(\\genblk8[1].left_loss_pb[11]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[1].left_loss_pb_reg_n_0_[6] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[1].left_loss_pb_reg[7] \n (.C(CLK),\n .CE(\\genblk8[1].left_loss_pb[11]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[1].left_loss_pb_reg_n_0_[7] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[1].left_loss_pb_reg[8] \n (.C(CLK),\n .CE(\\genblk8[1].left_loss_pb[11]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[1].left_loss_pb_reg__0 [2]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[1].left_loss_pb_reg[9] \n (.C(CLK),\n .CE(\\genblk8[1].left_loss_pb[11]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[1].left_loss_pb_reg__0 [3]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[1].match_flag_pb_reg[10] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[9]),\n .Q(match_flag_pb[10]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[1].match_flag_pb_reg[11] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[10]),\n .Q(match_flag_pb[11]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[1].match_flag_pb_reg[12] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[11]),\n .Q(match_flag_pb[12]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[1].match_flag_pb_reg[13] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[12]),\n .Q(match_flag_pb[13]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[1].match_flag_pb_reg[14] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[13]),\n .Q(match_flag_pb[14]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[1].match_flag_pb_reg[15] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[14]),\n .Q(match_flag_pb[15]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[1].match_flag_pb_reg[8] \n (.C(CLK),\n .CE(p_154_out),\n .D(\\genblk7[1].compare_err_pb_latch_r_reg_n_0_[1] ),\n .Q(match_flag_pb[8]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[1].match_flag_pb_reg[9] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[8]),\n .Q(match_flag_pb[9]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[1].right_edge_found_pb_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[1].right_edge_found_pb_reg[1]_0 ),\n .Q(\\genblk8[1].right_edge_pb_reg[6]_0 ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAABAAAAAAAAA)) \n \\genblk8[1].right_edge_pb[11]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(p_146_out),\n .I2(p_154_out),\n .I3(p_143_out),\n .I4(\\genblk8[1].right_edge_pb_reg[6]_0 ),\n .I5(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .O(\\genblk8[1].right_edge_pb[11]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h08)) \n \\genblk8[1].right_edge_pb[11]_i_2 \n (.I0(p_154_out),\n .I1(p_143_out),\n .I2(p_146_out),\n .O(\\genblk8[1].right_edge_pb[11]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\genblk8[1].right_edge_pb[11]_i_3 \n (.I0(\\genblk7[1].compare_err_pb_latch_r_reg_n_0_[1] ),\n .I1(\\genblk8[1].left_edge_pb[11]_i_3_n_0 ),\n .I2(match_flag_pb[15]),\n .I3(match_flag_pb[14]),\n .I4(match_flag_pb[12]),\n .I5(match_flag_pb[13]),\n .O(p_143_out));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[1].right_edge_pb_reg[10] \n (.C(CLK),\n .CE(\\genblk8[1].right_edge_pb[11]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[1].right_edge_pb_reg_n_0_[10] ),\n .S(\\genblk8[1].right_edge_pb[11]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[1].right_edge_pb_reg[11] \n (.C(CLK),\n .CE(\\genblk8[1].right_edge_pb[11]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[5]_i_3_n_0 ),\n .Q(\\genblk8[1].right_edge_pb_reg_n_0_[11] ),\n .S(\\genblk8[1].right_edge_pb[11]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[1].right_edge_pb_reg[6] \n (.C(CLK),\n .CE(\\genblk8[1].right_edge_pb[11]_i_2_n_0 ),\n .D(\\genblk8[0].left_edge_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[1].right_edge_pb_reg_n_0_[6] ),\n .S(\\genblk8[1].right_edge_pb[11]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[1].right_edge_pb_reg[7] \n (.C(CLK),\n .CE(\\genblk8[1].right_edge_pb[11]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[1].right_edge_pb_reg_n_0_[7] ),\n .S(\\genblk8[1].right_edge_pb[11]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[1].right_edge_pb_reg[8] \n (.C(CLK),\n .CE(\\genblk8[1].right_edge_pb[11]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[1].right_edge_pb_reg_n_0_[8] ),\n .S(\\genblk8[1].right_edge_pb[11]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[1].right_edge_pb_reg[9] \n (.C(CLK),\n .CE(\\genblk8[1].right_edge_pb[11]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[1].right_edge_pb_reg_n_0_[9] ),\n .S(\\genblk8[1].right_edge_pb[11]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[1].right_gain_pb[10]_i_1 \n (.I0(p_143_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[1].right_gain_pb_reg[11]_i_5_n_7 ),\n .I3(\\genblk8[1].right_gain_pb_reg[11]_i_6_n_7 ),\n .O(\\genblk8[1].right_gain_pb[10]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAEFEAEAE)) \n \\genblk8[1].right_gain_pb[11]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(right_gain_pb),\n .I2(p_154_out),\n .I3(p_146_out),\n .I4(\\genblk8[1].right_gain_pb_reg[11]_i_4_n_0 ),\n .O(\\genblk8[1].right_gain_pb[11]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[1].right_gain_pb[11]_i_10 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[10] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[1].right_gain_pb[11]_i_11 \n (.I0(right_edge_ref[5]),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[11] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[1].right_gain_pb[11]_i_12 \n (.I0(right_edge_ref[4]),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[10] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_12_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk8[1].right_gain_pb[11]_i_13 \n (.I0(\\genblk8[1].right_gain_pb[11]_i_16_n_0 ),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[9] ),\n .I2(right_edge_ref[3]),\n .I3(\\genblk8[1].right_edge_pb_reg_n_0_[10] ),\n .I4(right_edge_ref[4]),\n .O(\\genblk8[1].right_gain_pb[11]_i_13_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk8[1].right_gain_pb[11]_i_14 \n (.I0(\\genblk8[1].right_gain_pb[11]_i_17_n_0 ),\n .I1(right_edge_ref[3]),\n .I2(\\genblk8[1].right_edge_pb_reg_n_0_[9] ),\n .I3(right_edge_ref[4]),\n .I4(\\genblk8[1].right_edge_pb_reg_n_0_[10] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk8[1].right_gain_pb[11]_i_16 \n (.I0(right_edge_ref[0]),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[6] ),\n .I2(\\genblk8[1].right_edge_pb_reg_n_0_[7] ),\n .I3(right_edge_ref[1]),\n .I4(\\genblk8[1].right_edge_pb_reg_n_0_[8] ),\n .I5(right_edge_ref[2]),\n .O(\\genblk8[1].right_gain_pb[11]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk8[1].right_gain_pb[11]_i_17 \n (.I0(\\genblk8[1].right_edge_pb_reg_n_0_[6] ),\n .I1(right_edge_ref[0]),\n .I2(right_edge_ref[1]),\n .I3(\\genblk8[1].right_edge_pb_reg_n_0_[7] ),\n .I4(right_edge_ref[2]),\n .I5(\\genblk8[1].right_edge_pb_reg_n_0_[8] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[1].right_gain_pb[11]_i_19 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_19_n_0 ));\n LUT5 #(\n .INIT(32'h000000A8)) \n \\genblk8[1].right_gain_pb[11]_i_2 \n (.I0(p_154_out),\n .I1(p_143_out),\n .I2(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .I3(\\genblk8[1].right_edge_pb_reg[6]_0 ),\n .I4(p_146_out),\n .O(\\genblk8[1].right_gain_pb[11]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[1].right_gain_pb[11]_i_20 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[1].right_gain_pb[11]_i_21 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_21_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[1].right_gain_pb[11]_i_22 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_22_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[1].right_gain_pb[11]_i_24 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_24_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[1].right_gain_pb[11]_i_25 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_25_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[1].right_gain_pb[11]_i_26 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_26_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[1].right_gain_pb[11]_i_27 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_27_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[1].right_gain_pb[11]_i_29 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_29_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[1].right_gain_pb[11]_i_3 \n (.I0(p_143_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[1].right_gain_pb_reg[11]_i_5_n_6 ),\n .I3(\\genblk8[1].right_gain_pb_reg[11]_i_6_n_6 ),\n .O(\\genblk8[1].right_gain_pb[11]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[1].right_gain_pb[11]_i_30 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_30_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[1].right_gain_pb[11]_i_31 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_31_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[1].right_gain_pb[11]_i_32 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_32_n_0 ));\n LUT4 #(\n .INIT(16'hF880)) \n \\genblk8[1].right_gain_pb[11]_i_33 \n (.I0(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[10] ),\n .I2(\\genblk8[1].right_edge_pb_reg_n_0_[11] ),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[1].right_gain_pb[11]_i_33_n_0 ));\n LUT6 #(\n .INIT(64'h0808088CCECECEE0)) \n \\genblk8[1].right_gain_pb[11]_i_34 \n (.I0(\\genblk8[1].right_edge_pb_reg_n_0_[8] ),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[9] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[1].right_gain_pb[11]_i_34_n_0 ));\n LUT4 #(\n .INIT(16'h8CE0)) \n \\genblk8[1].right_gain_pb[11]_i_35 \n (.I0(\\genblk8[1].right_edge_pb_reg_n_0_[6] ),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[7] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\genblk8[1].right_gain_pb[11]_i_35_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[1].right_gain_pb[11]_i_36 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_36_n_0 ));\n LUT4 #(\n .INIT(16'h0660)) \n \\genblk8[1].right_gain_pb[11]_i_37 \n (.I0(\\genblk8[1].right_edge_pb_reg_n_0_[10] ),\n .I1(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I2(\\genblk8[1].right_edge_pb_reg_n_0_[11] ),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[1].right_gain_pb[11]_i_37_n_0 ));\n LUT6 #(\n .INIT(64'h8484844221212118)) \n \\genblk8[1].right_gain_pb[11]_i_38 \n (.I0(\\genblk8[1].right_edge_pb_reg_n_0_[8] ),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[9] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[1].right_gain_pb[11]_i_38_n_0 ));\n LUT4 #(\n .INIT(16'h4218)) \n \\genblk8[1].right_gain_pb[11]_i_39 \n (.I0(\\genblk8[1].right_edge_pb_reg_n_0_[6] ),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[7] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\genblk8[1].right_gain_pb[11]_i_39_n_0 ));\n LUT5 #(\n .INIT(32'h04004404)) \n \\genblk8[1].right_gain_pb[11]_i_7 \n (.I0(\\genblk8[1].right_edge_pb_reg[6]_0 ),\n .I1(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .I2(right_edge_ref[5]),\n .I3(\\genblk8[1].right_edge_pb_reg_n_0_[11] ),\n .I4(\\genblk8[1].right_gain_pb[11]_i_13_n_0 ),\n .O(\\genblk8[1].right_gain_pb[11]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FFB200B2)) \n \\genblk8[1].right_gain_pb[11]_i_8 \n (.I0(\\genblk8[1].right_edge_pb_reg_n_0_[11] ),\n .I1(right_edge_ref[5]),\n .I2(\\genblk8[1].right_gain_pb[11]_i_14_n_0 ),\n .I3(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I4(\\genblk8[1].right_gain_pb_reg[11]_i_15_n_0 ),\n .I5(\\genblk8[1].right_edge_pb_reg[6]_0 ),\n .O(\\genblk8[1].right_gain_pb[11]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[1].right_gain_pb[11]_i_9 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[11] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_9_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[1].right_gain_pb[6]_i_1 \n (.I0(p_143_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[1].right_gain_pb_reg[9]_i_2_n_7 ),\n .I3(\\genblk8[1].right_gain_pb_reg[9]_i_3_n_7 ),\n .O(\\genblk8[1].right_gain_pb[6]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[1].right_gain_pb[7]_i_1 \n (.I0(p_143_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[1].right_gain_pb_reg[9]_i_2_n_6 ),\n .I3(\\genblk8[1].right_gain_pb_reg[9]_i_3_n_6 ),\n .O(\\genblk8[1].right_gain_pb[7]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[1].right_gain_pb[8]_i_1 \n (.I0(p_143_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[1].right_gain_pb_reg[9]_i_2_n_5 ),\n .I3(\\genblk8[1].right_gain_pb_reg[9]_i_3_n_5 ),\n .O(\\genblk8[1].right_gain_pb[8]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[1].right_gain_pb[9]_i_1 \n (.I0(p_143_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[1].right_gain_pb_reg[9]_i_2_n_4 ),\n .I3(\\genblk8[1].right_gain_pb_reg[9]_i_3_n_4 ),\n .O(\\genblk8[1].right_gain_pb[9]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[1].right_gain_pb[9]_i_10 \n (.I0(right_edge_ref[1]),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[7] ),\n .O(\\genblk8[1].right_gain_pb[9]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[1].right_gain_pb[9]_i_11 \n (.I0(right_edge_ref[0]),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[6] ),\n .O(\\genblk8[1].right_gain_pb[9]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[1].right_gain_pb[9]_i_4 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[9] ),\n .O(\\genblk8[1].right_gain_pb[9]_i_4_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[1].right_gain_pb[9]_i_5 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[8] ),\n .O(\\genblk8[1].right_gain_pb[9]_i_5_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[1].right_gain_pb[9]_i_6 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[7] ),\n .O(\\genblk8[1].right_gain_pb[9]_i_6_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[1].right_gain_pb[9]_i_7 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[6] ),\n .O(\\genblk8[1].right_gain_pb[9]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[1].right_gain_pb[9]_i_8 \n (.I0(right_edge_ref[3]),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[9] ),\n .O(\\genblk8[1].right_gain_pb[9]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[1].right_gain_pb[9]_i_9 \n (.I0(right_edge_ref[2]),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[8] ),\n .O(\\genblk8[1].right_gain_pb[9]_i_9_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[1].right_gain_pb_reg[10] \n (.C(CLK),\n .CE(\\genblk8[1].right_gain_pb[11]_i_2_n_0 ),\n .D(\\genblk8[1].right_gain_pb[10]_i_1_n_0 ),\n .Q(\\genblk8[1].right_gain_pb_reg__0 [4]),\n .R(\\genblk8[1].right_gain_pb[11]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[1].right_gain_pb_reg[11] \n (.C(CLK),\n .CE(\\genblk8[1].right_gain_pb[11]_i_2_n_0 ),\n .D(\\genblk8[1].right_gain_pb[11]_i_3_n_0 ),\n .Q(\\genblk8[1].right_gain_pb_reg__0 [5]),\n .R(\\genblk8[1].right_gain_pb[11]_i_1_n_0 ));\n CARRY4 \\genblk8[1].right_gain_pb_reg[11]_i_15 \n (.CI(\\genblk8[1].right_gain_pb_reg[11]_i_18_n_0 ),\n .CO({\\genblk8[1].right_gain_pb_reg[11]_i_15_n_0 ,\\genblk8[1].right_gain_pb_reg[11]_i_15_n_1 ,\\genblk8[1].right_gain_pb_reg[11]_i_15_n_2 ,\\genblk8[1].right_gain_pb_reg[11]_i_15_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[1].right_gain_pb_reg[11]_i_15_O_UNCONNECTED [3:0]),\n .S({\\genblk8[1].right_gain_pb[11]_i_19_n_0 ,\\genblk8[1].right_gain_pb[11]_i_20_n_0 ,\\genblk8[1].right_gain_pb[11]_i_21_n_0 ,\\genblk8[1].right_gain_pb[11]_i_22_n_0 }));\n CARRY4 \\genblk8[1].right_gain_pb_reg[11]_i_18 \n (.CI(\\genblk8[1].right_gain_pb_reg[11]_i_23_n_0 ),\n .CO({\\genblk8[1].right_gain_pb_reg[11]_i_18_n_0 ,\\genblk8[1].right_gain_pb_reg[11]_i_18_n_1 ,\\genblk8[1].right_gain_pb_reg[11]_i_18_n_2 ,\\genblk8[1].right_gain_pb_reg[11]_i_18_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[1].right_gain_pb_reg[11]_i_18_O_UNCONNECTED [3:0]),\n .S({\\genblk8[1].right_gain_pb[11]_i_24_n_0 ,\\genblk8[1].right_gain_pb[11]_i_25_n_0 ,\\genblk8[1].right_gain_pb[11]_i_26_n_0 ,\\genblk8[1].right_gain_pb[11]_i_27_n_0 }));\n CARRY4 \\genblk8[1].right_gain_pb_reg[11]_i_23 \n (.CI(\\genblk8[1].right_gain_pb_reg[11]_i_28_n_0 ),\n .CO({\\genblk8[1].right_gain_pb_reg[11]_i_23_n_0 ,\\genblk8[1].right_gain_pb_reg[11]_i_23_n_1 ,\\genblk8[1].right_gain_pb_reg[11]_i_23_n_2 ,\\genblk8[1].right_gain_pb_reg[11]_i_23_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[1].right_gain_pb_reg[11]_i_23_O_UNCONNECTED [3:0]),\n .S({\\genblk8[1].right_gain_pb[11]_i_29_n_0 ,\\genblk8[1].right_gain_pb[11]_i_30_n_0 ,\\genblk8[1].right_gain_pb[11]_i_31_n_0 ,\\genblk8[1].right_gain_pb[11]_i_32_n_0 }));\n CARRY4 \\genblk8[1].right_gain_pb_reg[11]_i_28 \n (.CI(1'b0),\n .CO({\\genblk8[1].right_gain_pb_reg[11]_i_28_n_0 ,\\genblk8[1].right_gain_pb_reg[11]_i_28_n_1 ,\\genblk8[1].right_gain_pb_reg[11]_i_28_n_2 ,\\genblk8[1].right_gain_pb_reg[11]_i_28_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,\\genblk8[1].right_gain_pb[11]_i_33_n_0 ,\\genblk8[1].right_gain_pb[11]_i_34_n_0 ,\\genblk8[1].right_gain_pb[11]_i_35_n_0 }),\n .O(\\NLW_genblk8[1].right_gain_pb_reg[11]_i_28_O_UNCONNECTED [3:0]),\n .S({\\genblk8[1].right_gain_pb[11]_i_36_n_0 ,\\genblk8[1].right_gain_pb[11]_i_37_n_0 ,\\genblk8[1].right_gain_pb[11]_i_38_n_0 ,\\genblk8[1].right_gain_pb[11]_i_39_n_0 }));\n MUXF7 \\genblk8[1].right_gain_pb_reg[11]_i_4 \n (.I0(\\genblk8[1].right_gain_pb[11]_i_7_n_0 ),\n .I1(\\genblk8[1].right_gain_pb[11]_i_8_n_0 ),\n .O(\\genblk8[1].right_gain_pb_reg[11]_i_4_n_0 ),\n .S(p_143_out));\n CARRY4 \\genblk8[1].right_gain_pb_reg[11]_i_5 \n (.CI(\\genblk8[1].right_gain_pb_reg[9]_i_2_n_0 ),\n .CO({\\NLW_genblk8[1].right_gain_pb_reg[11]_i_5_CO_UNCONNECTED [3:1],\\genblk8[1].right_gain_pb_reg[11]_i_5_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,\\prbs_dqs_tap_cnt_r_reg_n_0_[4] }),\n .O({\\NLW_genblk8[1].right_gain_pb_reg[11]_i_5_O_UNCONNECTED [3:2],\\genblk8[1].right_gain_pb_reg[11]_i_5_n_6 ,\\genblk8[1].right_gain_pb_reg[11]_i_5_n_7 }),\n .S({1'b0,1'b0,\\genblk8[1].right_gain_pb[11]_i_9_n_0 ,\\genblk8[1].right_gain_pb[11]_i_10_n_0 }));\n CARRY4 \\genblk8[1].right_gain_pb_reg[11]_i_6 \n (.CI(\\genblk8[1].right_gain_pb_reg[9]_i_3_n_0 ),\n .CO({\\NLW_genblk8[1].right_gain_pb_reg[11]_i_6_CO_UNCONNECTED [3:1],\\genblk8[1].right_gain_pb_reg[11]_i_6_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,right_edge_ref[4]}),\n .O({\\NLW_genblk8[1].right_gain_pb_reg[11]_i_6_O_UNCONNECTED [3:2],\\genblk8[1].right_gain_pb_reg[11]_i_6_n_6 ,\\genblk8[1].right_gain_pb_reg[11]_i_6_n_7 }),\n .S({1'b0,1'b0,\\genblk8[1].right_gain_pb[11]_i_11_n_0 ,\\genblk8[1].right_gain_pb[11]_i_12_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[1].right_gain_pb_reg[6] \n (.C(CLK),\n .CE(\\genblk8[1].right_gain_pb[11]_i_2_n_0 ),\n .D(\\genblk8[1].right_gain_pb[6]_i_1_n_0 ),\n .Q(\\genblk8[1].right_gain_pb_reg_n_0_[6] ),\n .R(\\genblk8[1].right_gain_pb[11]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[1].right_gain_pb_reg[7] \n (.C(CLK),\n .CE(\\genblk8[1].right_gain_pb[11]_i_2_n_0 ),\n .D(\\genblk8[1].right_gain_pb[7]_i_1_n_0 ),\n .Q(\\genblk8[1].right_gain_pb_reg_n_0_[7] ),\n .R(\\genblk8[1].right_gain_pb[11]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[1].right_gain_pb_reg[8] \n (.C(CLK),\n .CE(\\genblk8[1].right_gain_pb[11]_i_2_n_0 ),\n .D(\\genblk8[1].right_gain_pb[8]_i_1_n_0 ),\n .Q(\\genblk8[1].right_gain_pb_reg__0 [2]),\n .R(\\genblk8[1].right_gain_pb[11]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[1].right_gain_pb_reg[9] \n (.C(CLK),\n .CE(\\genblk8[1].right_gain_pb[11]_i_2_n_0 ),\n .D(\\genblk8[1].right_gain_pb[9]_i_1_n_0 ),\n .Q(\\genblk8[1].right_gain_pb_reg__0 [3]),\n .R(\\genblk8[1].right_gain_pb[11]_i_1_n_0 ));\n CARRY4 \\genblk8[1].right_gain_pb_reg[9]_i_2 \n (.CI(1'b0),\n .CO({\\genblk8[1].right_gain_pb_reg[9]_i_2_n_0 ,\\genblk8[1].right_gain_pb_reg[9]_i_2_n_1 ,\\genblk8[1].right_gain_pb_reg[9]_i_2_n_2 ,\\genblk8[1].right_gain_pb_reg[9]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ,\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ,\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ,\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }),\n .O({\\genblk8[1].right_gain_pb_reg[9]_i_2_n_4 ,\\genblk8[1].right_gain_pb_reg[9]_i_2_n_5 ,\\genblk8[1].right_gain_pb_reg[9]_i_2_n_6 ,\\genblk8[1].right_gain_pb_reg[9]_i_2_n_7 }),\n .S({\\genblk8[1].right_gain_pb[9]_i_4_n_0 ,\\genblk8[1].right_gain_pb[9]_i_5_n_0 ,\\genblk8[1].right_gain_pb[9]_i_6_n_0 ,\\genblk8[1].right_gain_pb[9]_i_7_n_0 }));\n CARRY4 \\genblk8[1].right_gain_pb_reg[9]_i_3 \n (.CI(1'b0),\n .CO({\\genblk8[1].right_gain_pb_reg[9]_i_3_n_0 ,\\genblk8[1].right_gain_pb_reg[9]_i_3_n_1 ,\\genblk8[1].right_gain_pb_reg[9]_i_3_n_2 ,\\genblk8[1].right_gain_pb_reg[9]_i_3_n_3 }),\n .CYINIT(1'b1),\n .DI(right_edge_ref[3:0]),\n .O({\\genblk8[1].right_gain_pb_reg[9]_i_3_n_4 ,\\genblk8[1].right_gain_pb_reg[9]_i_3_n_5 ,\\genblk8[1].right_gain_pb_reg[9]_i_3_n_6 ,\\genblk8[1].right_gain_pb_reg[9]_i_3_n_7 }),\n .S({\\genblk8[1].right_gain_pb[9]_i_8_n_0 ,\\genblk8[1].right_gain_pb[9]_i_9_n_0 ,\\genblk8[1].right_gain_pb[9]_i_10_n_0 ,\\genblk8[1].right_gain_pb[9]_i_11_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[2].left_edge_found_pb_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[2].left_edge_found_pb_reg[2]_0 ),\n .Q(\\genblk8[2].left_loss_pb_reg[12]_0 ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\genblk8[2].left_edge_pb[17]_i_1 \n (.I0(p_154_out),\n .I1(\\genblk8[2].right_edge_pb_reg[12]_2 ),\n .O(\\genblk8[2].left_edge_pb[17]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\genblk8[2].left_edge_pb[17]_i_2 \n (.I0(match_flag_pb[23]),\n .I1(\\genblk8[2].left_edge_pb[17]_i_3_n_0 ),\n .I2(\\genblk7[2].compare_err_pb_latch_r_reg_n_0_[2] ),\n .I3(match_flag_pb[22]),\n .I4(match_flag_pb[20]),\n .I5(match_flag_pb[21]),\n .O(\\genblk8[2].right_edge_pb_reg[12]_2 ));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\genblk8[2].left_edge_pb[17]_i_3 \n (.I0(match_flag_pb[18]),\n .I1(match_flag_pb[19]),\n .I2(match_flag_pb[16]),\n .I3(match_flag_pb[17]),\n .O(\\genblk8[2].left_edge_pb[17]_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[2].left_edge_pb_reg[12] \n (.C(CLK),\n .CE(\\genblk8[2].left_edge_pb[17]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[2].left_edge_pb_reg_n_0_[12] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[2].left_edge_pb_reg[13] \n (.C(CLK),\n .CE(\\genblk8[2].left_edge_pb[17]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[2].left_edge_pb_reg_n_0_[13] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[2].left_edge_pb_reg[14] \n (.C(CLK),\n .CE(\\genblk8[2].left_edge_pb[17]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[2].left_edge_pb_reg_n_0_[14] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[2].left_edge_pb_reg[15] \n (.C(CLK),\n .CE(\\genblk8[2].left_edge_pb[17]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[2].left_edge_pb_reg_n_0_[15] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[2].left_edge_pb_reg[16] \n (.C(CLK),\n .CE(\\genblk8[2].left_edge_pb[17]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[2].left_edge_pb_reg_n_0_[16] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[2].left_edge_pb_reg[17] \n (.C(CLK),\n .CE(\\genblk8[2].left_edge_pb[17]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[5]_i_3_n_0 ),\n .Q(\\genblk8[2].left_edge_pb_reg_n_0_[17] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[2].left_edge_updated_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[2].left_edge_updated_reg[2]_0 ),\n .Q(D[2]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAEFEAEAE)) \n \\genblk8[2].left_loss_pb[17]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(right_gain_pb),\n .I2(p_154_out),\n .I3(\\genblk8[2].left_loss_pb_reg[12]_0 ),\n .I4(\\genblk8[2].right_edge_pb_reg[12]_2 ),\n .O(\\genblk8[2].left_loss_pb[17]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[2].left_loss_pb_reg[12] \n (.C(CLK),\n .CE(\\genblk8[2].left_loss_pb[17]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[2].left_loss_pb_reg_n_0_[12] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[2].left_loss_pb_reg[13] \n (.C(CLK),\n .CE(\\genblk8[2].left_loss_pb[17]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[2].left_loss_pb_reg_n_0_[13] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[2].left_loss_pb_reg[14] \n (.C(CLK),\n .CE(\\genblk8[2].left_loss_pb[17]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[2].left_loss_pb_reg__0 [2]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[2].left_loss_pb_reg[15] \n (.C(CLK),\n .CE(\\genblk8[2].left_loss_pb[17]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[2].left_loss_pb_reg__0 [3]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[2].left_loss_pb_reg[16] \n (.C(CLK),\n .CE(\\genblk8[2].left_loss_pb[17]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[2].left_loss_pb_reg__0 [4]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[2].left_loss_pb_reg[17] \n (.C(CLK),\n .CE(\\genblk8[2].left_loss_pb[17]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[5]_i_2_n_0 ),\n .Q(\\genblk8[2].left_loss_pb_reg__0 [5]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[2].match_flag_pb_reg[16] \n (.C(CLK),\n .CE(p_154_out),\n .D(\\genblk7[2].compare_err_pb_latch_r_reg_n_0_[2] ),\n .Q(match_flag_pb[16]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[2].match_flag_pb_reg[17] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[16]),\n .Q(match_flag_pb[17]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[2].match_flag_pb_reg[18] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[17]),\n .Q(match_flag_pb[18]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[2].match_flag_pb_reg[19] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[18]),\n .Q(match_flag_pb[19]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[2].match_flag_pb_reg[20] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[19]),\n .Q(match_flag_pb[20]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[2].match_flag_pb_reg[21] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[20]),\n .Q(match_flag_pb[21]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[2].match_flag_pb_reg[22] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[21]),\n .Q(match_flag_pb[22]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[2].match_flag_pb_reg[23] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[22]),\n .Q(match_flag_pb[23]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[2].right_edge_found_pb_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[2].right_edge_found_pb_reg[2]_0 ),\n .Q(\\genblk8[2].right_edge_pb_reg[12]_0 ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAABAAAAAAAAA)) \n \\genblk8[2].right_edge_pb[17]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(\\genblk8[2].right_edge_pb_reg[12]_2 ),\n .I2(p_154_out),\n .I3(\\genblk8[2].right_edge_pb_reg[12]_1 ),\n .I4(\\genblk8[2].right_edge_pb_reg[12]_0 ),\n .I5(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .O(\\genblk8[2].right_edge_pb[17]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h08)) \n \\genblk8[2].right_edge_pb[17]_i_2 \n (.I0(p_154_out),\n .I1(\\genblk8[2].right_edge_pb_reg[12]_1 ),\n .I2(\\genblk8[2].right_edge_pb_reg[12]_2 ),\n .O(\\genblk8[2].right_edge_pb[17]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\genblk8[2].right_edge_pb[17]_i_3 \n (.I0(\\genblk7[2].compare_err_pb_latch_r_reg_n_0_[2] ),\n .I1(\\genblk8[2].left_edge_pb[17]_i_3_n_0 ),\n .I2(match_flag_pb[23]),\n .I3(match_flag_pb[22]),\n .I4(match_flag_pb[20]),\n .I5(match_flag_pb[21]),\n .O(\\genblk8[2].right_edge_pb_reg[12]_1 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[2].right_edge_pb_reg[12] \n (.C(CLK),\n .CE(\\genblk8[2].right_edge_pb[17]_i_2_n_0 ),\n .D(\\genblk8[0].left_edge_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[2].right_edge_pb_reg_n_0_[12] ),\n .S(\\genblk8[2].right_edge_pb[17]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[2].right_edge_pb_reg[13] \n (.C(CLK),\n .CE(\\genblk8[2].right_edge_pb[17]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[2].right_edge_pb_reg_n_0_[13] ),\n .S(\\genblk8[2].right_edge_pb[17]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[2].right_edge_pb_reg[14] \n (.C(CLK),\n .CE(\\genblk8[2].right_edge_pb[17]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[2].right_edge_pb_reg_n_0_[14] ),\n .S(\\genblk8[2].right_edge_pb[17]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[2].right_edge_pb_reg[15] \n (.C(CLK),\n .CE(\\genblk8[2].right_edge_pb[17]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[2].right_edge_pb_reg_n_0_[15] ),\n .S(\\genblk8[2].right_edge_pb[17]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[2].right_edge_pb_reg[16] \n (.C(CLK),\n .CE(\\genblk8[2].right_edge_pb[17]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[2].right_edge_pb_reg_n_0_[16] ),\n .S(\\genblk8[2].right_edge_pb[17]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[2].right_edge_pb_reg[17] \n (.C(CLK),\n .CE(\\genblk8[2].right_edge_pb[17]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[5]_i_3_n_0 ),\n .Q(\\genblk8[2].right_edge_pb_reg_n_0_[17] ),\n .S(\\genblk8[2].right_edge_pb[17]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[2].right_gain_pb[12]_i_1 \n (.I0(\\genblk8[2].right_edge_pb_reg[12]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[2].right_gain_pb_reg[15]_i_2_n_7 ),\n .I3(\\genblk8[2].right_gain_pb_reg[15]_i_3_n_7 ),\n .O(\\genblk8[2].right_gain_pb[12]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[2].right_gain_pb[13]_i_1 \n (.I0(\\genblk8[2].right_edge_pb_reg[12]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[2].right_gain_pb_reg[15]_i_2_n_6 ),\n .I3(\\genblk8[2].right_gain_pb_reg[15]_i_3_n_6 ),\n .O(\\genblk8[2].right_gain_pb[13]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[2].right_gain_pb[14]_i_1 \n (.I0(\\genblk8[2].right_edge_pb_reg[12]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[2].right_gain_pb_reg[15]_i_2_n_5 ),\n .I3(\\genblk8[2].right_gain_pb_reg[15]_i_3_n_5 ),\n .O(\\genblk8[2].right_gain_pb[14]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[2].right_gain_pb[15]_i_1 \n (.I0(\\genblk8[2].right_edge_pb_reg[12]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[2].right_gain_pb_reg[15]_i_2_n_4 ),\n .I3(\\genblk8[2].right_gain_pb_reg[15]_i_3_n_4 ),\n .O(\\genblk8[2].right_gain_pb[15]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[2].right_gain_pb[15]_i_10 \n (.I0(right_edge_ref[1]),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[13] ),\n .O(\\genblk8[2].right_gain_pb[15]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[2].right_gain_pb[15]_i_11 \n (.I0(right_edge_ref[0]),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[12] ),\n .O(\\genblk8[2].right_gain_pb[15]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[2].right_gain_pb[15]_i_4 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[15] ),\n .O(\\genblk8[2].right_gain_pb[15]_i_4_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[2].right_gain_pb[15]_i_5 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[14] ),\n .O(\\genblk8[2].right_gain_pb[15]_i_5_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[2].right_gain_pb[15]_i_6 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[13] ),\n .O(\\genblk8[2].right_gain_pb[15]_i_6_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[2].right_gain_pb[15]_i_7 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[12] ),\n .O(\\genblk8[2].right_gain_pb[15]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[2].right_gain_pb[15]_i_8 \n (.I0(right_edge_ref[3]),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[15] ),\n .O(\\genblk8[2].right_gain_pb[15]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[2].right_gain_pb[15]_i_9 \n (.I0(right_edge_ref[2]),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[14] ),\n .O(\\genblk8[2].right_gain_pb[15]_i_9_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[2].right_gain_pb[16]_i_1 \n (.I0(\\genblk8[2].right_edge_pb_reg[12]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[2].right_gain_pb_reg[17]_i_5_n_7 ),\n .I3(\\genblk8[2].right_gain_pb_reg[17]_i_6_n_7 ),\n .O(\\genblk8[2].right_gain_pb[16]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAEFEAEAE)) \n \\genblk8[2].right_gain_pb[17]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(right_gain_pb),\n .I2(p_154_out),\n .I3(\\genblk8[2].right_edge_pb_reg[12]_2 ),\n .I4(\\genblk8[2].right_gain_pb_reg[17]_i_4_n_0 ),\n .O(\\genblk8[2].right_gain_pb[17]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[2].right_gain_pb[17]_i_10 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[16] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[2].right_gain_pb[17]_i_11 \n (.I0(right_edge_ref[5]),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[17] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[2].right_gain_pb[17]_i_12 \n (.I0(right_edge_ref[4]),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[16] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_12_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk8[2].right_gain_pb[17]_i_13 \n (.I0(\\genblk8[2].right_gain_pb[17]_i_16_n_0 ),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[15] ),\n .I2(right_edge_ref[3]),\n .I3(\\genblk8[2].right_edge_pb_reg_n_0_[16] ),\n .I4(right_edge_ref[4]),\n .O(\\genblk8[2].right_gain_pb[17]_i_13_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk8[2].right_gain_pb[17]_i_14 \n (.I0(\\genblk8[2].right_gain_pb[17]_i_17_n_0 ),\n .I1(right_edge_ref[3]),\n .I2(\\genblk8[2].right_edge_pb_reg_n_0_[15] ),\n .I3(right_edge_ref[4]),\n .I4(\\genblk8[2].right_edge_pb_reg_n_0_[16] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk8[2].right_gain_pb[17]_i_16 \n (.I0(right_edge_ref[0]),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[12] ),\n .I2(\\genblk8[2].right_edge_pb_reg_n_0_[13] ),\n .I3(right_edge_ref[1]),\n .I4(\\genblk8[2].right_edge_pb_reg_n_0_[14] ),\n .I5(right_edge_ref[2]),\n .O(\\genblk8[2].right_gain_pb[17]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk8[2].right_gain_pb[17]_i_17 \n (.I0(\\genblk8[2].right_edge_pb_reg_n_0_[12] ),\n .I1(right_edge_ref[0]),\n .I2(right_edge_ref[1]),\n .I3(\\genblk8[2].right_edge_pb_reg_n_0_[13] ),\n .I4(right_edge_ref[2]),\n .I5(\\genblk8[2].right_edge_pb_reg_n_0_[14] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[2].right_gain_pb[17]_i_19 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_19_n_0 ));\n LUT5 #(\n .INIT(32'h000000A8)) \n \\genblk8[2].right_gain_pb[17]_i_2 \n (.I0(p_154_out),\n .I1(\\genblk8[2].right_edge_pb_reg[12]_1 ),\n .I2(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .I3(\\genblk8[2].right_edge_pb_reg[12]_0 ),\n .I4(\\genblk8[2].right_edge_pb_reg[12]_2 ),\n .O(\\genblk8[2].right_gain_pb[17]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[2].right_gain_pb[17]_i_20 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[2].right_gain_pb[17]_i_21 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_21_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[2].right_gain_pb[17]_i_22 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_22_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[2].right_gain_pb[17]_i_24 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_24_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[2].right_gain_pb[17]_i_25 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_25_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[2].right_gain_pb[17]_i_26 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_26_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[2].right_gain_pb[17]_i_27 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_27_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[2].right_gain_pb[17]_i_29 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_29_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[2].right_gain_pb[17]_i_3 \n (.I0(\\genblk8[2].right_edge_pb_reg[12]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[2].right_gain_pb_reg[17]_i_5_n_6 ),\n .I3(\\genblk8[2].right_gain_pb_reg[17]_i_6_n_6 ),\n .O(\\genblk8[2].right_gain_pb[17]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[2].right_gain_pb[17]_i_30 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_30_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[2].right_gain_pb[17]_i_31 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_31_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[2].right_gain_pb[17]_i_32 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_32_n_0 ));\n LUT4 #(\n .INIT(16'hF880)) \n \\genblk8[2].right_gain_pb[17]_i_33 \n (.I0(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[16] ),\n .I2(\\genblk8[2].right_edge_pb_reg_n_0_[17] ),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[2].right_gain_pb[17]_i_33_n_0 ));\n LUT6 #(\n .INIT(64'h0808088CCECECEE0)) \n \\genblk8[2].right_gain_pb[17]_i_34 \n (.I0(\\genblk8[2].right_edge_pb_reg_n_0_[14] ),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[15] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[2].right_gain_pb[17]_i_34_n_0 ));\n LUT4 #(\n .INIT(16'h8CE0)) \n \\genblk8[2].right_gain_pb[17]_i_35 \n (.I0(\\genblk8[2].right_edge_pb_reg_n_0_[12] ),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[13] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\genblk8[2].right_gain_pb[17]_i_35_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[2].right_gain_pb[17]_i_36 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_36_n_0 ));\n LUT4 #(\n .INIT(16'h0660)) \n \\genblk8[2].right_gain_pb[17]_i_37 \n (.I0(\\genblk8[2].right_edge_pb_reg_n_0_[16] ),\n .I1(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I2(\\genblk8[2].right_edge_pb_reg_n_0_[17] ),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[2].right_gain_pb[17]_i_37_n_0 ));\n LUT6 #(\n .INIT(64'h8484844221212118)) \n \\genblk8[2].right_gain_pb[17]_i_38 \n (.I0(\\genblk8[2].right_edge_pb_reg_n_0_[14] ),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[15] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[2].right_gain_pb[17]_i_38_n_0 ));\n LUT4 #(\n .INIT(16'h4218)) \n \\genblk8[2].right_gain_pb[17]_i_39 \n (.I0(\\genblk8[2].right_edge_pb_reg_n_0_[12] ),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[13] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\genblk8[2].right_gain_pb[17]_i_39_n_0 ));\n LUT5 #(\n .INIT(32'h04004404)) \n \\genblk8[2].right_gain_pb[17]_i_7 \n (.I0(\\genblk8[2].right_edge_pb_reg[12]_0 ),\n .I1(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .I2(right_edge_ref[5]),\n .I3(\\genblk8[2].right_edge_pb_reg_n_0_[17] ),\n .I4(\\genblk8[2].right_gain_pb[17]_i_13_n_0 ),\n .O(\\genblk8[2].right_gain_pb[17]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FFB200B2)) \n \\genblk8[2].right_gain_pb[17]_i_8 \n (.I0(\\genblk8[2].right_edge_pb_reg_n_0_[17] ),\n .I1(right_edge_ref[5]),\n .I2(\\genblk8[2].right_gain_pb[17]_i_14_n_0 ),\n .I3(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I4(\\genblk8[2].right_gain_pb_reg[17]_i_15_n_0 ),\n .I5(\\genblk8[2].right_edge_pb_reg[12]_0 ),\n .O(\\genblk8[2].right_gain_pb[17]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[2].right_gain_pb[17]_i_9 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[17] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_9_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[2].right_gain_pb_reg[12] \n (.C(CLK),\n .CE(\\genblk8[2].right_gain_pb[17]_i_2_n_0 ),\n .D(\\genblk8[2].right_gain_pb[12]_i_1_n_0 ),\n .Q(\\genblk8[2].right_gain_pb_reg_n_0_[12] ),\n .R(\\genblk8[2].right_gain_pb[17]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[2].right_gain_pb_reg[13] \n (.C(CLK),\n .CE(\\genblk8[2].right_gain_pb[17]_i_2_n_0 ),\n .D(\\genblk8[2].right_gain_pb[13]_i_1_n_0 ),\n .Q(\\genblk8[2].right_gain_pb_reg_n_0_[13] ),\n .R(\\genblk8[2].right_gain_pb[17]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[2].right_gain_pb_reg[14] \n (.C(CLK),\n .CE(\\genblk8[2].right_gain_pb[17]_i_2_n_0 ),\n .D(\\genblk8[2].right_gain_pb[14]_i_1_n_0 ),\n .Q(\\genblk8[2].right_gain_pb_reg__0 [2]),\n .R(\\genblk8[2].right_gain_pb[17]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[2].right_gain_pb_reg[15] \n (.C(CLK),\n .CE(\\genblk8[2].right_gain_pb[17]_i_2_n_0 ),\n .D(\\genblk8[2].right_gain_pb[15]_i_1_n_0 ),\n .Q(\\genblk8[2].right_gain_pb_reg__0 [3]),\n .R(\\genblk8[2].right_gain_pb[17]_i_1_n_0 ));\n CARRY4 \\genblk8[2].right_gain_pb_reg[15]_i_2 \n (.CI(1'b0),\n .CO({\\genblk8[2].right_gain_pb_reg[15]_i_2_n_0 ,\\genblk8[2].right_gain_pb_reg[15]_i_2_n_1 ,\\genblk8[2].right_gain_pb_reg[15]_i_2_n_2 ,\\genblk8[2].right_gain_pb_reg[15]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ,\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ,\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ,\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }),\n .O({\\genblk8[2].right_gain_pb_reg[15]_i_2_n_4 ,\\genblk8[2].right_gain_pb_reg[15]_i_2_n_5 ,\\genblk8[2].right_gain_pb_reg[15]_i_2_n_6 ,\\genblk8[2].right_gain_pb_reg[15]_i_2_n_7 }),\n .S({\\genblk8[2].right_gain_pb[15]_i_4_n_0 ,\\genblk8[2].right_gain_pb[15]_i_5_n_0 ,\\genblk8[2].right_gain_pb[15]_i_6_n_0 ,\\genblk8[2].right_gain_pb[15]_i_7_n_0 }));\n CARRY4 \\genblk8[2].right_gain_pb_reg[15]_i_3 \n (.CI(1'b0),\n .CO({\\genblk8[2].right_gain_pb_reg[15]_i_3_n_0 ,\\genblk8[2].right_gain_pb_reg[15]_i_3_n_1 ,\\genblk8[2].right_gain_pb_reg[15]_i_3_n_2 ,\\genblk8[2].right_gain_pb_reg[15]_i_3_n_3 }),\n .CYINIT(1'b1),\n .DI(right_edge_ref[3:0]),\n .O({\\genblk8[2].right_gain_pb_reg[15]_i_3_n_4 ,\\genblk8[2].right_gain_pb_reg[15]_i_3_n_5 ,\\genblk8[2].right_gain_pb_reg[15]_i_3_n_6 ,\\genblk8[2].right_gain_pb_reg[15]_i_3_n_7 }),\n .S({\\genblk8[2].right_gain_pb[15]_i_8_n_0 ,\\genblk8[2].right_gain_pb[15]_i_9_n_0 ,\\genblk8[2].right_gain_pb[15]_i_10_n_0 ,\\genblk8[2].right_gain_pb[15]_i_11_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[2].right_gain_pb_reg[16] \n (.C(CLK),\n .CE(\\genblk8[2].right_gain_pb[17]_i_2_n_0 ),\n .D(\\genblk8[2].right_gain_pb[16]_i_1_n_0 ),\n .Q(\\genblk8[2].right_gain_pb_reg__0 [4]),\n .R(\\genblk8[2].right_gain_pb[17]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[2].right_gain_pb_reg[17] \n (.C(CLK),\n .CE(\\genblk8[2].right_gain_pb[17]_i_2_n_0 ),\n .D(\\genblk8[2].right_gain_pb[17]_i_3_n_0 ),\n .Q(\\genblk8[2].right_gain_pb_reg__0 [5]),\n .R(\\genblk8[2].right_gain_pb[17]_i_1_n_0 ));\n CARRY4 \\genblk8[2].right_gain_pb_reg[17]_i_15 \n (.CI(\\genblk8[2].right_gain_pb_reg[17]_i_18_n_0 ),\n .CO({\\genblk8[2].right_gain_pb_reg[17]_i_15_n_0 ,\\genblk8[2].right_gain_pb_reg[17]_i_15_n_1 ,\\genblk8[2].right_gain_pb_reg[17]_i_15_n_2 ,\\genblk8[2].right_gain_pb_reg[17]_i_15_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[2].right_gain_pb_reg[17]_i_15_O_UNCONNECTED [3:0]),\n .S({\\genblk8[2].right_gain_pb[17]_i_19_n_0 ,\\genblk8[2].right_gain_pb[17]_i_20_n_0 ,\\genblk8[2].right_gain_pb[17]_i_21_n_0 ,\\genblk8[2].right_gain_pb[17]_i_22_n_0 }));\n CARRY4 \\genblk8[2].right_gain_pb_reg[17]_i_18 \n (.CI(\\genblk8[2].right_gain_pb_reg[17]_i_23_n_0 ),\n .CO({\\genblk8[2].right_gain_pb_reg[17]_i_18_n_0 ,\\genblk8[2].right_gain_pb_reg[17]_i_18_n_1 ,\\genblk8[2].right_gain_pb_reg[17]_i_18_n_2 ,\\genblk8[2].right_gain_pb_reg[17]_i_18_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[2].right_gain_pb_reg[17]_i_18_O_UNCONNECTED [3:0]),\n .S({\\genblk8[2].right_gain_pb[17]_i_24_n_0 ,\\genblk8[2].right_gain_pb[17]_i_25_n_0 ,\\genblk8[2].right_gain_pb[17]_i_26_n_0 ,\\genblk8[2].right_gain_pb[17]_i_27_n_0 }));\n CARRY4 \\genblk8[2].right_gain_pb_reg[17]_i_23 \n (.CI(\\genblk8[2].right_gain_pb_reg[17]_i_28_n_0 ),\n .CO({\\genblk8[2].right_gain_pb_reg[17]_i_23_n_0 ,\\genblk8[2].right_gain_pb_reg[17]_i_23_n_1 ,\\genblk8[2].right_gain_pb_reg[17]_i_23_n_2 ,\\genblk8[2].right_gain_pb_reg[17]_i_23_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[2].right_gain_pb_reg[17]_i_23_O_UNCONNECTED [3:0]),\n .S({\\genblk8[2].right_gain_pb[17]_i_29_n_0 ,\\genblk8[2].right_gain_pb[17]_i_30_n_0 ,\\genblk8[2].right_gain_pb[17]_i_31_n_0 ,\\genblk8[2].right_gain_pb[17]_i_32_n_0 }));\n CARRY4 \\genblk8[2].right_gain_pb_reg[17]_i_28 \n (.CI(1'b0),\n .CO({\\genblk8[2].right_gain_pb_reg[17]_i_28_n_0 ,\\genblk8[2].right_gain_pb_reg[17]_i_28_n_1 ,\\genblk8[2].right_gain_pb_reg[17]_i_28_n_2 ,\\genblk8[2].right_gain_pb_reg[17]_i_28_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,\\genblk8[2].right_gain_pb[17]_i_33_n_0 ,\\genblk8[2].right_gain_pb[17]_i_34_n_0 ,\\genblk8[2].right_gain_pb[17]_i_35_n_0 }),\n .O(\\NLW_genblk8[2].right_gain_pb_reg[17]_i_28_O_UNCONNECTED [3:0]),\n .S({\\genblk8[2].right_gain_pb[17]_i_36_n_0 ,\\genblk8[2].right_gain_pb[17]_i_37_n_0 ,\\genblk8[2].right_gain_pb[17]_i_38_n_0 ,\\genblk8[2].right_gain_pb[17]_i_39_n_0 }));\n MUXF7 \\genblk8[2].right_gain_pb_reg[17]_i_4 \n (.I0(\\genblk8[2].right_gain_pb[17]_i_7_n_0 ),\n .I1(\\genblk8[2].right_gain_pb[17]_i_8_n_0 ),\n .O(\\genblk8[2].right_gain_pb_reg[17]_i_4_n_0 ),\n .S(\\genblk8[2].right_edge_pb_reg[12]_1 ));\n CARRY4 \\genblk8[2].right_gain_pb_reg[17]_i_5 \n (.CI(\\genblk8[2].right_gain_pb_reg[15]_i_2_n_0 ),\n .CO({\\NLW_genblk8[2].right_gain_pb_reg[17]_i_5_CO_UNCONNECTED [3:1],\\genblk8[2].right_gain_pb_reg[17]_i_5_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,\\prbs_dqs_tap_cnt_r_reg_n_0_[4] }),\n .O({\\NLW_genblk8[2].right_gain_pb_reg[17]_i_5_O_UNCONNECTED [3:2],\\genblk8[2].right_gain_pb_reg[17]_i_5_n_6 ,\\genblk8[2].right_gain_pb_reg[17]_i_5_n_7 }),\n .S({1'b0,1'b0,\\genblk8[2].right_gain_pb[17]_i_9_n_0 ,\\genblk8[2].right_gain_pb[17]_i_10_n_0 }));\n CARRY4 \\genblk8[2].right_gain_pb_reg[17]_i_6 \n (.CI(\\genblk8[2].right_gain_pb_reg[15]_i_3_n_0 ),\n .CO({\\NLW_genblk8[2].right_gain_pb_reg[17]_i_6_CO_UNCONNECTED [3:1],\\genblk8[2].right_gain_pb_reg[17]_i_6_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,right_edge_ref[4]}),\n .O({\\NLW_genblk8[2].right_gain_pb_reg[17]_i_6_O_UNCONNECTED [3:2],\\genblk8[2].right_gain_pb_reg[17]_i_6_n_6 ,\\genblk8[2].right_gain_pb_reg[17]_i_6_n_7 }),\n .S({1'b0,1'b0,\\genblk8[2].right_gain_pb[17]_i_11_n_0 ,\\genblk8[2].right_gain_pb[17]_i_12_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[3].left_edge_found_pb_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[3].left_edge_found_pb_reg[3]_0 ),\n .Q(\\genblk8[3].left_loss_pb_reg[18]_0 ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\genblk8[3].left_edge_pb[23]_i_1 \n (.I0(p_154_out),\n .I1(p_130_out),\n .O(\\genblk8[3].left_edge_pb[23]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\genblk8[3].left_edge_pb[23]_i_2 \n (.I0(match_flag_pb[31]),\n .I1(\\genblk8[3].left_edge_pb[23]_i_3_n_0 ),\n .I2(\\genblk7[3].compare_err_pb_latch_r_reg_n_0_[3] ),\n .I3(match_flag_pb[30]),\n .I4(match_flag_pb[28]),\n .I5(match_flag_pb[29]),\n .O(p_130_out));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\genblk8[3].left_edge_pb[23]_i_3 \n (.I0(match_flag_pb[26]),\n .I1(match_flag_pb[27]),\n .I2(match_flag_pb[24]),\n .I3(match_flag_pb[25]),\n .O(\\genblk8[3].left_edge_pb[23]_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[3].left_edge_pb_reg[18] \n (.C(CLK),\n .CE(\\genblk8[3].left_edge_pb[23]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[3].left_edge_pb_reg_n_0_[18] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[3].left_edge_pb_reg[19] \n (.C(CLK),\n .CE(\\genblk8[3].left_edge_pb[23]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[3].left_edge_pb_reg_n_0_[19] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[3].left_edge_pb_reg[20] \n (.C(CLK),\n .CE(\\genblk8[3].left_edge_pb[23]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[3].left_edge_pb_reg_n_0_[20] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[3].left_edge_pb_reg[21] \n (.C(CLK),\n .CE(\\genblk8[3].left_edge_pb[23]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[3].left_edge_pb_reg_n_0_[21] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[3].left_edge_pb_reg[22] \n (.C(CLK),\n .CE(\\genblk8[3].left_edge_pb[23]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[3].left_edge_pb_reg_n_0_[22] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[3].left_edge_pb_reg[23] \n (.C(CLK),\n .CE(\\genblk8[3].left_edge_pb[23]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[5]_i_3_n_0 ),\n .Q(\\genblk8[3].left_edge_pb_reg_n_0_[23] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[3].left_edge_updated_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[3].left_edge_updated_reg[3]_0 ),\n .Q(D[3]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAEFEAEAE)) \n \\genblk8[3].left_loss_pb[23]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(right_gain_pb),\n .I2(p_154_out),\n .I3(\\genblk8[3].left_loss_pb_reg[18]_0 ),\n .I4(p_130_out),\n .O(\\genblk8[3].left_loss_pb[23]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[3].left_loss_pb_reg[18] \n (.C(CLK),\n .CE(\\genblk8[3].left_loss_pb[23]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[3].left_loss_pb_reg_n_0_[18] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[3].left_loss_pb_reg[19] \n (.C(CLK),\n .CE(\\genblk8[3].left_loss_pb[23]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[3].left_loss_pb_reg_n_0_[19] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[3].left_loss_pb_reg[20] \n (.C(CLK),\n .CE(\\genblk8[3].left_loss_pb[23]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[3].left_loss_pb_reg__0 [2]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[3].left_loss_pb_reg[21] \n (.C(CLK),\n .CE(\\genblk8[3].left_loss_pb[23]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[3].left_loss_pb_reg__0 [3]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[3].left_loss_pb_reg[22] \n (.C(CLK),\n .CE(\\genblk8[3].left_loss_pb[23]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[3].left_loss_pb_reg__0 [4]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[3].left_loss_pb_reg[23] \n (.C(CLK),\n .CE(\\genblk8[3].left_loss_pb[23]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[5]_i_2_n_0 ),\n .Q(\\genblk8[3].left_loss_pb_reg__0 [5]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[3].match_flag_pb_reg[24] \n (.C(CLK),\n .CE(p_154_out),\n .D(\\genblk7[3].compare_err_pb_latch_r_reg_n_0_[3] ),\n .Q(match_flag_pb[24]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[3].match_flag_pb_reg[25] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[24]),\n .Q(match_flag_pb[25]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[3].match_flag_pb_reg[26] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[25]),\n .Q(match_flag_pb[26]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[3].match_flag_pb_reg[27] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[26]),\n .Q(match_flag_pb[27]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[3].match_flag_pb_reg[28] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[27]),\n .Q(match_flag_pb[28]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[3].match_flag_pb_reg[29] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[28]),\n .Q(match_flag_pb[29]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[3].match_flag_pb_reg[30] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[29]),\n .Q(match_flag_pb[30]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[3].match_flag_pb_reg[31] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[30]),\n .Q(match_flag_pb[31]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[3].right_edge_found_pb_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[3].right_edge_found_pb_reg[3]_0 ),\n .Q(\\genblk8[3].right_edge_pb_reg[18]_0 ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAABAAAAAAAAA)) \n \\genblk8[3].right_edge_pb[23]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(p_130_out),\n .I2(p_154_out),\n .I3(p_127_out),\n .I4(\\genblk8[3].right_edge_pb_reg[18]_0 ),\n .I5(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .O(\\genblk8[3].right_edge_pb[23]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h08)) \n \\genblk8[3].right_edge_pb[23]_i_2 \n (.I0(p_154_out),\n .I1(p_127_out),\n .I2(p_130_out),\n .O(\\genblk8[3].right_edge_pb[23]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\genblk8[3].right_edge_pb[23]_i_3 \n (.I0(\\genblk7[3].compare_err_pb_latch_r_reg_n_0_[3] ),\n .I1(\\genblk8[3].left_edge_pb[23]_i_3_n_0 ),\n .I2(match_flag_pb[31]),\n .I3(match_flag_pb[30]),\n .I4(match_flag_pb[28]),\n .I5(match_flag_pb[29]),\n .O(p_127_out));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[3].right_edge_pb_reg[18] \n (.C(CLK),\n .CE(\\genblk8[3].right_edge_pb[23]_i_2_n_0 ),\n .D(\\genblk8[0].left_edge_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[3].right_edge_pb_reg_n_0_[18] ),\n .S(\\genblk8[3].right_edge_pb[23]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[3].right_edge_pb_reg[19] \n (.C(CLK),\n .CE(\\genblk8[3].right_edge_pb[23]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[3].right_edge_pb_reg_n_0_[19] ),\n .S(\\genblk8[3].right_edge_pb[23]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[3].right_edge_pb_reg[20] \n (.C(CLK),\n .CE(\\genblk8[3].right_edge_pb[23]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[3].right_edge_pb_reg_n_0_[20] ),\n .S(\\genblk8[3].right_edge_pb[23]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[3].right_edge_pb_reg[21] \n (.C(CLK),\n .CE(\\genblk8[3].right_edge_pb[23]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[3].right_edge_pb_reg_n_0_[21] ),\n .S(\\genblk8[3].right_edge_pb[23]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[3].right_edge_pb_reg[22] \n (.C(CLK),\n .CE(\\genblk8[3].right_edge_pb[23]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[3].right_edge_pb_reg_n_0_[22] ),\n .S(\\genblk8[3].right_edge_pb[23]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[3].right_edge_pb_reg[23] \n (.C(CLK),\n .CE(\\genblk8[3].right_edge_pb[23]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[5]_i_3_n_0 ),\n .Q(\\genblk8[3].right_edge_pb_reg_n_0_[23] ),\n .S(\\genblk8[3].right_edge_pb[23]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[3].right_gain_pb[18]_i_1 \n (.I0(p_127_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[3].right_gain_pb_reg[21]_i_2_n_7 ),\n .I3(\\genblk8[3].right_gain_pb_reg[21]_i_3_n_7 ),\n .O(\\genblk8[3].right_gain_pb[18]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[3].right_gain_pb[19]_i_1 \n (.I0(p_127_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[3].right_gain_pb_reg[21]_i_2_n_6 ),\n .I3(\\genblk8[3].right_gain_pb_reg[21]_i_3_n_6 ),\n .O(\\genblk8[3].right_gain_pb[19]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[3].right_gain_pb[20]_i_1 \n (.I0(p_127_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[3].right_gain_pb_reg[21]_i_2_n_5 ),\n .I3(\\genblk8[3].right_gain_pb_reg[21]_i_3_n_5 ),\n .O(\\genblk8[3].right_gain_pb[20]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[3].right_gain_pb[21]_i_1 \n (.I0(p_127_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[3].right_gain_pb_reg[21]_i_2_n_4 ),\n .I3(\\genblk8[3].right_gain_pb_reg[21]_i_3_n_4 ),\n .O(\\genblk8[3].right_gain_pb[21]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[3].right_gain_pb[21]_i_10 \n (.I0(right_edge_ref[1]),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[19] ),\n .O(\\genblk8[3].right_gain_pb[21]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[3].right_gain_pb[21]_i_11 \n (.I0(right_edge_ref[0]),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[18] ),\n .O(\\genblk8[3].right_gain_pb[21]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[3].right_gain_pb[21]_i_4 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[21] ),\n .O(\\genblk8[3].right_gain_pb[21]_i_4_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[3].right_gain_pb[21]_i_5 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[20] ),\n .O(\\genblk8[3].right_gain_pb[21]_i_5_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[3].right_gain_pb[21]_i_6 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[19] ),\n .O(\\genblk8[3].right_gain_pb[21]_i_6_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[3].right_gain_pb[21]_i_7 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[18] ),\n .O(\\genblk8[3].right_gain_pb[21]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[3].right_gain_pb[21]_i_8 \n (.I0(right_edge_ref[3]),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[21] ),\n .O(\\genblk8[3].right_gain_pb[21]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[3].right_gain_pb[21]_i_9 \n (.I0(right_edge_ref[2]),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[20] ),\n .O(\\genblk8[3].right_gain_pb[21]_i_9_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[3].right_gain_pb[22]_i_1 \n (.I0(p_127_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[3].right_gain_pb_reg[23]_i_5_n_7 ),\n .I3(\\genblk8[3].right_gain_pb_reg[23]_i_6_n_7 ),\n .O(\\genblk8[3].right_gain_pb[22]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAEFEAEAE)) \n \\genblk8[3].right_gain_pb[23]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(right_gain_pb),\n .I2(p_154_out),\n .I3(p_130_out),\n .I4(\\genblk8[3].right_gain_pb_reg[23]_i_4_n_0 ),\n .O(\\genblk8[3].right_gain_pb[23]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[3].right_gain_pb[23]_i_10 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[22] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[3].right_gain_pb[23]_i_11 \n (.I0(right_edge_ref[5]),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[23] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[3].right_gain_pb[23]_i_12 \n (.I0(right_edge_ref[4]),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[22] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_12_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk8[3].right_gain_pb[23]_i_13 \n (.I0(\\genblk8[3].right_gain_pb[23]_i_16_n_0 ),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[21] ),\n .I2(right_edge_ref[3]),\n .I3(\\genblk8[3].right_edge_pb_reg_n_0_[22] ),\n .I4(right_edge_ref[4]),\n .O(\\genblk8[3].right_gain_pb[23]_i_13_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk8[3].right_gain_pb[23]_i_14 \n (.I0(\\genblk8[3].right_gain_pb[23]_i_17_n_0 ),\n .I1(right_edge_ref[3]),\n .I2(\\genblk8[3].right_edge_pb_reg_n_0_[21] ),\n .I3(right_edge_ref[4]),\n .I4(\\genblk8[3].right_edge_pb_reg_n_0_[22] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk8[3].right_gain_pb[23]_i_16 \n (.I0(right_edge_ref[0]),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[18] ),\n .I2(\\genblk8[3].right_edge_pb_reg_n_0_[19] ),\n .I3(right_edge_ref[1]),\n .I4(\\genblk8[3].right_edge_pb_reg_n_0_[20] ),\n .I5(right_edge_ref[2]),\n .O(\\genblk8[3].right_gain_pb[23]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk8[3].right_gain_pb[23]_i_17 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[18] ),\n .I1(right_edge_ref[0]),\n .I2(right_edge_ref[1]),\n .I3(\\genblk8[3].right_edge_pb_reg_n_0_[19] ),\n .I4(right_edge_ref[2]),\n .I5(\\genblk8[3].right_edge_pb_reg_n_0_[20] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[3].right_gain_pb[23]_i_19 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_19_n_0 ));\n LUT5 #(\n .INIT(32'h000000A8)) \n \\genblk8[3].right_gain_pb[23]_i_2 \n (.I0(p_154_out),\n .I1(p_127_out),\n .I2(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .I3(\\genblk8[3].right_edge_pb_reg[18]_0 ),\n .I4(p_130_out),\n .O(\\genblk8[3].right_gain_pb[23]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[3].right_gain_pb[23]_i_20 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[3].right_gain_pb[23]_i_21 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_21_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[3].right_gain_pb[23]_i_22 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_22_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[3].right_gain_pb[23]_i_24 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_24_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[3].right_gain_pb[23]_i_25 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_25_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[3].right_gain_pb[23]_i_26 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_26_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[3].right_gain_pb[23]_i_27 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_27_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[3].right_gain_pb[23]_i_29 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_29_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[3].right_gain_pb[23]_i_3 \n (.I0(p_127_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[3].right_gain_pb_reg[23]_i_5_n_6 ),\n .I3(\\genblk8[3].right_gain_pb_reg[23]_i_6_n_6 ),\n .O(\\genblk8[3].right_gain_pb[23]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[3].right_gain_pb[23]_i_30 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_30_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[3].right_gain_pb[23]_i_31 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_31_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[3].right_gain_pb[23]_i_32 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_32_n_0 ));\n LUT4 #(\n .INIT(16'hF880)) \n \\genblk8[3].right_gain_pb[23]_i_33 \n (.I0(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[22] ),\n .I2(\\genblk8[3].right_edge_pb_reg_n_0_[23] ),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[3].right_gain_pb[23]_i_33_n_0 ));\n LUT6 #(\n .INIT(64'h0808088CCECECEE0)) \n \\genblk8[3].right_gain_pb[23]_i_34 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[20] ),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[21] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[3].right_gain_pb[23]_i_34_n_0 ));\n LUT4 #(\n .INIT(16'h8CE0)) \n \\genblk8[3].right_gain_pb[23]_i_35 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[18] ),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[19] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\genblk8[3].right_gain_pb[23]_i_35_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[3].right_gain_pb[23]_i_36 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_36_n_0 ));\n LUT4 #(\n .INIT(16'h0660)) \n \\genblk8[3].right_gain_pb[23]_i_37 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[22] ),\n .I1(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I2(\\genblk8[3].right_edge_pb_reg_n_0_[23] ),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[3].right_gain_pb[23]_i_37_n_0 ));\n LUT6 #(\n .INIT(64'h8484844221212118)) \n \\genblk8[3].right_gain_pb[23]_i_38 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[20] ),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[21] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[3].right_gain_pb[23]_i_38_n_0 ));\n LUT4 #(\n .INIT(16'h4218)) \n \\genblk8[3].right_gain_pb[23]_i_39 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[18] ),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[19] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\genblk8[3].right_gain_pb[23]_i_39_n_0 ));\n LUT5 #(\n .INIT(32'h04004404)) \n \\genblk8[3].right_gain_pb[23]_i_7 \n (.I0(\\genblk8[3].right_edge_pb_reg[18]_0 ),\n .I1(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .I2(right_edge_ref[5]),\n .I3(\\genblk8[3].right_edge_pb_reg_n_0_[23] ),\n .I4(\\genblk8[3].right_gain_pb[23]_i_13_n_0 ),\n .O(\\genblk8[3].right_gain_pb[23]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FFB200B2)) \n \\genblk8[3].right_gain_pb[23]_i_8 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[23] ),\n .I1(right_edge_ref[5]),\n .I2(\\genblk8[3].right_gain_pb[23]_i_14_n_0 ),\n .I3(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I4(\\genblk8[3].right_gain_pb_reg[23]_i_15_n_0 ),\n .I5(\\genblk8[3].right_edge_pb_reg[18]_0 ),\n .O(\\genblk8[3].right_gain_pb[23]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[3].right_gain_pb[23]_i_9 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[23] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_9_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[3].right_gain_pb_reg[18] \n (.C(CLK),\n .CE(\\genblk8[3].right_gain_pb[23]_i_2_n_0 ),\n .D(\\genblk8[3].right_gain_pb[18]_i_1_n_0 ),\n .Q(\\genblk8[3].right_gain_pb_reg_n_0_[18] ),\n .R(\\genblk8[3].right_gain_pb[23]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[3].right_gain_pb_reg[19] \n (.C(CLK),\n .CE(\\genblk8[3].right_gain_pb[23]_i_2_n_0 ),\n .D(\\genblk8[3].right_gain_pb[19]_i_1_n_0 ),\n .Q(\\genblk8[3].right_gain_pb_reg_n_0_[19] ),\n .R(\\genblk8[3].right_gain_pb[23]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[3].right_gain_pb_reg[20] \n (.C(CLK),\n .CE(\\genblk8[3].right_gain_pb[23]_i_2_n_0 ),\n .D(\\genblk8[3].right_gain_pb[20]_i_1_n_0 ),\n .Q(\\genblk8[3].right_gain_pb_reg__0 [2]),\n .R(\\genblk8[3].right_gain_pb[23]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[3].right_gain_pb_reg[21] \n (.C(CLK),\n .CE(\\genblk8[3].right_gain_pb[23]_i_2_n_0 ),\n .D(\\genblk8[3].right_gain_pb[21]_i_1_n_0 ),\n .Q(\\genblk8[3].right_gain_pb_reg__0 [3]),\n .R(\\genblk8[3].right_gain_pb[23]_i_1_n_0 ));\n CARRY4 \\genblk8[3].right_gain_pb_reg[21]_i_2 \n (.CI(1'b0),\n .CO({\\genblk8[3].right_gain_pb_reg[21]_i_2_n_0 ,\\genblk8[3].right_gain_pb_reg[21]_i_2_n_1 ,\\genblk8[3].right_gain_pb_reg[21]_i_2_n_2 ,\\genblk8[3].right_gain_pb_reg[21]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ,\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ,\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ,\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }),\n .O({\\genblk8[3].right_gain_pb_reg[21]_i_2_n_4 ,\\genblk8[3].right_gain_pb_reg[21]_i_2_n_5 ,\\genblk8[3].right_gain_pb_reg[21]_i_2_n_6 ,\\genblk8[3].right_gain_pb_reg[21]_i_2_n_7 }),\n .S({\\genblk8[3].right_gain_pb[21]_i_4_n_0 ,\\genblk8[3].right_gain_pb[21]_i_5_n_0 ,\\genblk8[3].right_gain_pb[21]_i_6_n_0 ,\\genblk8[3].right_gain_pb[21]_i_7_n_0 }));\n CARRY4 \\genblk8[3].right_gain_pb_reg[21]_i_3 \n (.CI(1'b0),\n .CO({\\genblk8[3].right_gain_pb_reg[21]_i_3_n_0 ,\\genblk8[3].right_gain_pb_reg[21]_i_3_n_1 ,\\genblk8[3].right_gain_pb_reg[21]_i_3_n_2 ,\\genblk8[3].right_gain_pb_reg[21]_i_3_n_3 }),\n .CYINIT(1'b1),\n .DI(right_edge_ref[3:0]),\n .O({\\genblk8[3].right_gain_pb_reg[21]_i_3_n_4 ,\\genblk8[3].right_gain_pb_reg[21]_i_3_n_5 ,\\genblk8[3].right_gain_pb_reg[21]_i_3_n_6 ,\\genblk8[3].right_gain_pb_reg[21]_i_3_n_7 }),\n .S({\\genblk8[3].right_gain_pb[21]_i_8_n_0 ,\\genblk8[3].right_gain_pb[21]_i_9_n_0 ,\\genblk8[3].right_gain_pb[21]_i_10_n_0 ,\\genblk8[3].right_gain_pb[21]_i_11_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[3].right_gain_pb_reg[22] \n (.C(CLK),\n .CE(\\genblk8[3].right_gain_pb[23]_i_2_n_0 ),\n .D(\\genblk8[3].right_gain_pb[22]_i_1_n_0 ),\n .Q(\\genblk8[3].right_gain_pb_reg__0 [4]),\n .R(\\genblk8[3].right_gain_pb[23]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[3].right_gain_pb_reg[23] \n (.C(CLK),\n .CE(\\genblk8[3].right_gain_pb[23]_i_2_n_0 ),\n .D(\\genblk8[3].right_gain_pb[23]_i_3_n_0 ),\n .Q(\\genblk8[3].right_gain_pb_reg__0 [5]),\n .R(\\genblk8[3].right_gain_pb[23]_i_1_n_0 ));\n CARRY4 \\genblk8[3].right_gain_pb_reg[23]_i_15 \n (.CI(\\genblk8[3].right_gain_pb_reg[23]_i_18_n_0 ),\n .CO({\\genblk8[3].right_gain_pb_reg[23]_i_15_n_0 ,\\genblk8[3].right_gain_pb_reg[23]_i_15_n_1 ,\\genblk8[3].right_gain_pb_reg[23]_i_15_n_2 ,\\genblk8[3].right_gain_pb_reg[23]_i_15_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[3].right_gain_pb_reg[23]_i_15_O_UNCONNECTED [3:0]),\n .S({\\genblk8[3].right_gain_pb[23]_i_19_n_0 ,\\genblk8[3].right_gain_pb[23]_i_20_n_0 ,\\genblk8[3].right_gain_pb[23]_i_21_n_0 ,\\genblk8[3].right_gain_pb[23]_i_22_n_0 }));\n CARRY4 \\genblk8[3].right_gain_pb_reg[23]_i_18 \n (.CI(\\genblk8[3].right_gain_pb_reg[23]_i_23_n_0 ),\n .CO({\\genblk8[3].right_gain_pb_reg[23]_i_18_n_0 ,\\genblk8[3].right_gain_pb_reg[23]_i_18_n_1 ,\\genblk8[3].right_gain_pb_reg[23]_i_18_n_2 ,\\genblk8[3].right_gain_pb_reg[23]_i_18_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[3].right_gain_pb_reg[23]_i_18_O_UNCONNECTED [3:0]),\n .S({\\genblk8[3].right_gain_pb[23]_i_24_n_0 ,\\genblk8[3].right_gain_pb[23]_i_25_n_0 ,\\genblk8[3].right_gain_pb[23]_i_26_n_0 ,\\genblk8[3].right_gain_pb[23]_i_27_n_0 }));\n CARRY4 \\genblk8[3].right_gain_pb_reg[23]_i_23 \n (.CI(\\genblk8[3].right_gain_pb_reg[23]_i_28_n_0 ),\n .CO({\\genblk8[3].right_gain_pb_reg[23]_i_23_n_0 ,\\genblk8[3].right_gain_pb_reg[23]_i_23_n_1 ,\\genblk8[3].right_gain_pb_reg[23]_i_23_n_2 ,\\genblk8[3].right_gain_pb_reg[23]_i_23_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[3].right_gain_pb_reg[23]_i_23_O_UNCONNECTED [3:0]),\n .S({\\genblk8[3].right_gain_pb[23]_i_29_n_0 ,\\genblk8[3].right_gain_pb[23]_i_30_n_0 ,\\genblk8[3].right_gain_pb[23]_i_31_n_0 ,\\genblk8[3].right_gain_pb[23]_i_32_n_0 }));\n CARRY4 \\genblk8[3].right_gain_pb_reg[23]_i_28 \n (.CI(1'b0),\n .CO({\\genblk8[3].right_gain_pb_reg[23]_i_28_n_0 ,\\genblk8[3].right_gain_pb_reg[23]_i_28_n_1 ,\\genblk8[3].right_gain_pb_reg[23]_i_28_n_2 ,\\genblk8[3].right_gain_pb_reg[23]_i_28_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,\\genblk8[3].right_gain_pb[23]_i_33_n_0 ,\\genblk8[3].right_gain_pb[23]_i_34_n_0 ,\\genblk8[3].right_gain_pb[23]_i_35_n_0 }),\n .O(\\NLW_genblk8[3].right_gain_pb_reg[23]_i_28_O_UNCONNECTED [3:0]),\n .S({\\genblk8[3].right_gain_pb[23]_i_36_n_0 ,\\genblk8[3].right_gain_pb[23]_i_37_n_0 ,\\genblk8[3].right_gain_pb[23]_i_38_n_0 ,\\genblk8[3].right_gain_pb[23]_i_39_n_0 }));\n MUXF7 \\genblk8[3].right_gain_pb_reg[23]_i_4 \n (.I0(\\genblk8[3].right_gain_pb[23]_i_7_n_0 ),\n .I1(\\genblk8[3].right_gain_pb[23]_i_8_n_0 ),\n .O(\\genblk8[3].right_gain_pb_reg[23]_i_4_n_0 ),\n .S(p_127_out));\n CARRY4 \\genblk8[3].right_gain_pb_reg[23]_i_5 \n (.CI(\\genblk8[3].right_gain_pb_reg[21]_i_2_n_0 ),\n .CO({\\NLW_genblk8[3].right_gain_pb_reg[23]_i_5_CO_UNCONNECTED [3:1],\\genblk8[3].right_gain_pb_reg[23]_i_5_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,\\prbs_dqs_tap_cnt_r_reg_n_0_[4] }),\n .O({\\NLW_genblk8[3].right_gain_pb_reg[23]_i_5_O_UNCONNECTED [3:2],\\genblk8[3].right_gain_pb_reg[23]_i_5_n_6 ,\\genblk8[3].right_gain_pb_reg[23]_i_5_n_7 }),\n .S({1'b0,1'b0,\\genblk8[3].right_gain_pb[23]_i_9_n_0 ,\\genblk8[3].right_gain_pb[23]_i_10_n_0 }));\n CARRY4 \\genblk8[3].right_gain_pb_reg[23]_i_6 \n (.CI(\\genblk8[3].right_gain_pb_reg[21]_i_3_n_0 ),\n .CO({\\NLW_genblk8[3].right_gain_pb_reg[23]_i_6_CO_UNCONNECTED [3:1],\\genblk8[3].right_gain_pb_reg[23]_i_6_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,right_edge_ref[4]}),\n .O({\\NLW_genblk8[3].right_gain_pb_reg[23]_i_6_O_UNCONNECTED [3:2],\\genblk8[3].right_gain_pb_reg[23]_i_6_n_6 ,\\genblk8[3].right_gain_pb_reg[23]_i_6_n_7 }),\n .S({1'b0,1'b0,\\genblk8[3].right_gain_pb[23]_i_11_n_0 ,\\genblk8[3].right_gain_pb[23]_i_12_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[4].left_edge_found_pb_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[4].left_edge_found_pb_reg[4]_0 ),\n .Q(\\genblk8[4].left_loss_pb_reg[24]_0 ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\genblk8[4].left_edge_pb[29]_i_1 \n (.I0(p_154_out),\n .I1(p_122_out),\n .O(\\genblk8[4].left_edge_pb[29]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\genblk8[4].left_edge_pb[29]_i_2 \n (.I0(match_flag_pb[39]),\n .I1(\\genblk8[4].left_edge_pb[29]_i_3_n_0 ),\n .I2(\\genblk7[4].compare_err_pb_latch_r_reg_n_0_[4] ),\n .I3(match_flag_pb[38]),\n .I4(match_flag_pb[36]),\n .I5(match_flag_pb[37]),\n .O(p_122_out));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\genblk8[4].left_edge_pb[29]_i_3 \n (.I0(match_flag_pb[34]),\n .I1(match_flag_pb[35]),\n .I2(match_flag_pb[32]),\n .I3(match_flag_pb[33]),\n .O(\\genblk8[4].left_edge_pb[29]_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[4].left_edge_pb_reg[24] \n (.C(CLK),\n .CE(\\genblk8[4].left_edge_pb[29]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[4].left_edge_pb_reg_n_0_[24] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[4].left_edge_pb_reg[25] \n (.C(CLK),\n .CE(\\genblk8[4].left_edge_pb[29]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[4].left_edge_pb_reg_n_0_[25] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[4].left_edge_pb_reg[26] \n (.C(CLK),\n .CE(\\genblk8[4].left_edge_pb[29]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[4].left_edge_pb_reg_n_0_[26] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[4].left_edge_pb_reg[27] \n (.C(CLK),\n .CE(\\genblk8[4].left_edge_pb[29]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[4].left_edge_pb_reg_n_0_[27] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[4].left_edge_pb_reg[28] \n (.C(CLK),\n .CE(\\genblk8[4].left_edge_pb[29]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[4].left_edge_pb_reg_n_0_[28] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[4].left_edge_pb_reg[29] \n (.C(CLK),\n .CE(\\genblk8[4].left_edge_pb[29]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[5]_i_3_n_0 ),\n .Q(\\genblk8[4].left_edge_pb_reg_n_0_[29] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[4].left_edge_updated_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[4].left_edge_updated_reg[4]_0 ),\n .Q(D[4]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAEFEAEAE)) \n \\genblk8[4].left_loss_pb[29]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(right_gain_pb),\n .I2(p_154_out),\n .I3(\\genblk8[4].left_loss_pb_reg[24]_0 ),\n .I4(p_122_out),\n .O(\\genblk8[4].left_loss_pb[29]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[4].left_loss_pb_reg[24] \n (.C(CLK),\n .CE(\\genblk8[4].left_loss_pb[29]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[4].left_loss_pb_reg_n_0_[24] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[4].left_loss_pb_reg[25] \n (.C(CLK),\n .CE(\\genblk8[4].left_loss_pb[29]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[4].left_loss_pb_reg_n_0_[25] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[4].left_loss_pb_reg[26] \n (.C(CLK),\n .CE(\\genblk8[4].left_loss_pb[29]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[4].left_loss_pb_reg__0 [2]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[4].left_loss_pb_reg[27] \n (.C(CLK),\n .CE(\\genblk8[4].left_loss_pb[29]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[4].left_loss_pb_reg__0 [3]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[4].left_loss_pb_reg[28] \n (.C(CLK),\n .CE(\\genblk8[4].left_loss_pb[29]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[4].left_loss_pb_reg__0 [4]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[4].left_loss_pb_reg[29] \n (.C(CLK),\n .CE(\\genblk8[4].left_loss_pb[29]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[5]_i_2_n_0 ),\n .Q(\\genblk8[4].left_loss_pb_reg__0 [5]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[4].match_flag_pb_reg[32] \n (.C(CLK),\n .CE(p_154_out),\n .D(\\genblk7[4].compare_err_pb_latch_r_reg_n_0_[4] ),\n .Q(match_flag_pb[32]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[4].match_flag_pb_reg[33] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[32]),\n .Q(match_flag_pb[33]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[4].match_flag_pb_reg[34] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[33]),\n .Q(match_flag_pb[34]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[4].match_flag_pb_reg[35] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[34]),\n .Q(match_flag_pb[35]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[4].match_flag_pb_reg[36] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[35]),\n .Q(match_flag_pb[36]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[4].match_flag_pb_reg[37] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[36]),\n .Q(match_flag_pb[37]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[4].match_flag_pb_reg[38] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[37]),\n .Q(match_flag_pb[38]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[4].match_flag_pb_reg[39] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[38]),\n .Q(match_flag_pb[39]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[4].right_edge_found_pb_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[4].right_edge_found_pb_reg[4]_0 ),\n .Q(\\genblk8[4].right_edge_pb_reg[24]_0 ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAABAAAAAAAAA)) \n \\genblk8[4].right_edge_pb[29]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(p_122_out),\n .I2(p_154_out),\n .I3(p_119_out),\n .I4(\\genblk8[4].right_edge_pb_reg[24]_0 ),\n .I5(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .O(\\genblk8[4].right_edge_pb[29]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h08)) \n \\genblk8[4].right_edge_pb[29]_i_2 \n (.I0(p_154_out),\n .I1(p_119_out),\n .I2(p_122_out),\n .O(\\genblk8[4].right_edge_pb[29]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\genblk8[4].right_edge_pb[29]_i_3 \n (.I0(\\genblk7[4].compare_err_pb_latch_r_reg_n_0_[4] ),\n .I1(\\genblk8[4].left_edge_pb[29]_i_3_n_0 ),\n .I2(match_flag_pb[39]),\n .I3(match_flag_pb[38]),\n .I4(match_flag_pb[36]),\n .I5(match_flag_pb[37]),\n .O(p_119_out));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[4].right_edge_pb_reg[24] \n (.C(CLK),\n .CE(\\genblk8[4].right_edge_pb[29]_i_2_n_0 ),\n .D(\\genblk8[0].left_edge_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[4].right_edge_pb_reg_n_0_[24] ),\n .S(\\genblk8[4].right_edge_pb[29]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[4].right_edge_pb_reg[25] \n (.C(CLK),\n .CE(\\genblk8[4].right_edge_pb[29]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[4].right_edge_pb_reg_n_0_[25] ),\n .S(\\genblk8[4].right_edge_pb[29]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[4].right_edge_pb_reg[26] \n (.C(CLK),\n .CE(\\genblk8[4].right_edge_pb[29]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[4].right_edge_pb_reg_n_0_[26] ),\n .S(\\genblk8[4].right_edge_pb[29]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[4].right_edge_pb_reg[27] \n (.C(CLK),\n .CE(\\genblk8[4].right_edge_pb[29]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[4].right_edge_pb_reg_n_0_[27] ),\n .S(\\genblk8[4].right_edge_pb[29]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[4].right_edge_pb_reg[28] \n (.C(CLK),\n .CE(\\genblk8[4].right_edge_pb[29]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[4].right_edge_pb_reg_n_0_[28] ),\n .S(\\genblk8[4].right_edge_pb[29]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[4].right_edge_pb_reg[29] \n (.C(CLK),\n .CE(\\genblk8[4].right_edge_pb[29]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[5]_i_3_n_0 ),\n .Q(\\genblk8[4].right_edge_pb_reg_n_0_[29] ),\n .S(\\genblk8[4].right_edge_pb[29]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[4].right_gain_pb[24]_i_1 \n (.I0(p_119_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[4].right_gain_pb_reg[27]_i_2_n_7 ),\n .I3(\\genblk8[4].right_gain_pb_reg[27]_i_3_n_7 ),\n .O(\\genblk8[4].right_gain_pb[24]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[4].right_gain_pb[25]_i_1 \n (.I0(p_119_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[4].right_gain_pb_reg[27]_i_2_n_6 ),\n .I3(\\genblk8[4].right_gain_pb_reg[27]_i_3_n_6 ),\n .O(\\genblk8[4].right_gain_pb[25]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[4].right_gain_pb[26]_i_1 \n (.I0(p_119_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[4].right_gain_pb_reg[27]_i_2_n_5 ),\n .I3(\\genblk8[4].right_gain_pb_reg[27]_i_3_n_5 ),\n .O(\\genblk8[4].right_gain_pb[26]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[4].right_gain_pb[27]_i_1 \n (.I0(p_119_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[4].right_gain_pb_reg[27]_i_2_n_4 ),\n .I3(\\genblk8[4].right_gain_pb_reg[27]_i_3_n_4 ),\n .O(\\genblk8[4].right_gain_pb[27]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[4].right_gain_pb[27]_i_10 \n (.I0(right_edge_ref[1]),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[25] ),\n .O(\\genblk8[4].right_gain_pb[27]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[4].right_gain_pb[27]_i_11 \n (.I0(right_edge_ref[0]),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[24] ),\n .O(\\genblk8[4].right_gain_pb[27]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[4].right_gain_pb[27]_i_4 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[27] ),\n .O(\\genblk8[4].right_gain_pb[27]_i_4_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[4].right_gain_pb[27]_i_5 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[26] ),\n .O(\\genblk8[4].right_gain_pb[27]_i_5_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[4].right_gain_pb[27]_i_6 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[25] ),\n .O(\\genblk8[4].right_gain_pb[27]_i_6_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[4].right_gain_pb[27]_i_7 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[24] ),\n .O(\\genblk8[4].right_gain_pb[27]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[4].right_gain_pb[27]_i_8 \n (.I0(right_edge_ref[3]),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[27] ),\n .O(\\genblk8[4].right_gain_pb[27]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[4].right_gain_pb[27]_i_9 \n (.I0(right_edge_ref[2]),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[26] ),\n .O(\\genblk8[4].right_gain_pb[27]_i_9_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[4].right_gain_pb[28]_i_1 \n (.I0(p_119_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[4].right_gain_pb_reg[29]_i_5_n_7 ),\n .I3(\\genblk8[4].right_gain_pb_reg[29]_i_6_n_7 ),\n .O(\\genblk8[4].right_gain_pb[28]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAEFEAEAE)) \n \\genblk8[4].right_gain_pb[29]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(right_gain_pb),\n .I2(p_154_out),\n .I3(p_122_out),\n .I4(\\genblk8[4].right_gain_pb_reg[29]_i_4_n_0 ),\n .O(\\genblk8[4].right_gain_pb[29]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[4].right_gain_pb[29]_i_10 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[28] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[4].right_gain_pb[29]_i_11 \n (.I0(right_edge_ref[5]),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[29] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[4].right_gain_pb[29]_i_12 \n (.I0(right_edge_ref[4]),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[28] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_12_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk8[4].right_gain_pb[29]_i_13 \n (.I0(\\genblk8[4].right_gain_pb[29]_i_16_n_0 ),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[27] ),\n .I2(right_edge_ref[3]),\n .I3(\\genblk8[4].right_edge_pb_reg_n_0_[28] ),\n .I4(right_edge_ref[4]),\n .O(\\genblk8[4].right_gain_pb[29]_i_13_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk8[4].right_gain_pb[29]_i_14 \n (.I0(\\genblk8[4].right_gain_pb[29]_i_17_n_0 ),\n .I1(right_edge_ref[3]),\n .I2(\\genblk8[4].right_edge_pb_reg_n_0_[27] ),\n .I3(right_edge_ref[4]),\n .I4(\\genblk8[4].right_edge_pb_reg_n_0_[28] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk8[4].right_gain_pb[29]_i_16 \n (.I0(right_edge_ref[0]),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[24] ),\n .I2(\\genblk8[4].right_edge_pb_reg_n_0_[25] ),\n .I3(right_edge_ref[1]),\n .I4(\\genblk8[4].right_edge_pb_reg_n_0_[26] ),\n .I5(right_edge_ref[2]),\n .O(\\genblk8[4].right_gain_pb[29]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk8[4].right_gain_pb[29]_i_17 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[24] ),\n .I1(right_edge_ref[0]),\n .I2(right_edge_ref[1]),\n .I3(\\genblk8[4].right_edge_pb_reg_n_0_[25] ),\n .I4(right_edge_ref[2]),\n .I5(\\genblk8[4].right_edge_pb_reg_n_0_[26] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[4].right_gain_pb[29]_i_19 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_19_n_0 ));\n LUT5 #(\n .INIT(32'h000000A8)) \n \\genblk8[4].right_gain_pb[29]_i_2 \n (.I0(p_154_out),\n .I1(p_119_out),\n .I2(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .I3(\\genblk8[4].right_edge_pb_reg[24]_0 ),\n .I4(p_122_out),\n .O(\\genblk8[4].right_gain_pb[29]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[4].right_gain_pb[29]_i_20 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[4].right_gain_pb[29]_i_21 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_21_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[4].right_gain_pb[29]_i_22 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_22_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[4].right_gain_pb[29]_i_24 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_24_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[4].right_gain_pb[29]_i_25 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_25_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[4].right_gain_pb[29]_i_26 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_26_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[4].right_gain_pb[29]_i_27 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_27_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[4].right_gain_pb[29]_i_29 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_29_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[4].right_gain_pb[29]_i_3 \n (.I0(p_119_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[4].right_gain_pb_reg[29]_i_5_n_6 ),\n .I3(\\genblk8[4].right_gain_pb_reg[29]_i_6_n_6 ),\n .O(\\genblk8[4].right_gain_pb[29]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[4].right_gain_pb[29]_i_30 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_30_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[4].right_gain_pb[29]_i_31 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_31_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[4].right_gain_pb[29]_i_32 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_32_n_0 ));\n LUT4 #(\n .INIT(16'hF880)) \n \\genblk8[4].right_gain_pb[29]_i_33 \n (.I0(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[28] ),\n .I2(\\genblk8[4].right_edge_pb_reg_n_0_[29] ),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[4].right_gain_pb[29]_i_33_n_0 ));\n LUT6 #(\n .INIT(64'h0808088CCECECEE0)) \n \\genblk8[4].right_gain_pb[29]_i_34 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[26] ),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[27] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[4].right_gain_pb[29]_i_34_n_0 ));\n LUT4 #(\n .INIT(16'h8CE0)) \n \\genblk8[4].right_gain_pb[29]_i_35 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[24] ),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[25] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\genblk8[4].right_gain_pb[29]_i_35_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[4].right_gain_pb[29]_i_36 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_36_n_0 ));\n LUT4 #(\n .INIT(16'h0660)) \n \\genblk8[4].right_gain_pb[29]_i_37 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[28] ),\n .I1(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I2(\\genblk8[4].right_edge_pb_reg_n_0_[29] ),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[4].right_gain_pb[29]_i_37_n_0 ));\n LUT6 #(\n .INIT(64'h8484844221212118)) \n \\genblk8[4].right_gain_pb[29]_i_38 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[26] ),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[27] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[4].right_gain_pb[29]_i_38_n_0 ));\n LUT4 #(\n .INIT(16'h4218)) \n \\genblk8[4].right_gain_pb[29]_i_39 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[24] ),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[25] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\genblk8[4].right_gain_pb[29]_i_39_n_0 ));\n LUT5 #(\n .INIT(32'h04004404)) \n \\genblk8[4].right_gain_pb[29]_i_7 \n (.I0(\\genblk8[4].right_edge_pb_reg[24]_0 ),\n .I1(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .I2(right_edge_ref[5]),\n .I3(\\genblk8[4].right_edge_pb_reg_n_0_[29] ),\n .I4(\\genblk8[4].right_gain_pb[29]_i_13_n_0 ),\n .O(\\genblk8[4].right_gain_pb[29]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FFB200B2)) \n \\genblk8[4].right_gain_pb[29]_i_8 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[29] ),\n .I1(right_edge_ref[5]),\n .I2(\\genblk8[4].right_gain_pb[29]_i_14_n_0 ),\n .I3(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I4(\\genblk8[4].right_gain_pb_reg[29]_i_15_n_0 ),\n .I5(\\genblk8[4].right_edge_pb_reg[24]_0 ),\n .O(\\genblk8[4].right_gain_pb[29]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[4].right_gain_pb[29]_i_9 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[29] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_9_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[4].right_gain_pb_reg[24] \n (.C(CLK),\n .CE(\\genblk8[4].right_gain_pb[29]_i_2_n_0 ),\n .D(\\genblk8[4].right_gain_pb[24]_i_1_n_0 ),\n .Q(\\genblk8[4].right_gain_pb_reg_n_0_[24] ),\n .R(\\genblk8[4].right_gain_pb[29]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[4].right_gain_pb_reg[25] \n (.C(CLK),\n .CE(\\genblk8[4].right_gain_pb[29]_i_2_n_0 ),\n .D(\\genblk8[4].right_gain_pb[25]_i_1_n_0 ),\n .Q(\\genblk8[4].right_gain_pb_reg_n_0_[25] ),\n .R(\\genblk8[4].right_gain_pb[29]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[4].right_gain_pb_reg[26] \n (.C(CLK),\n .CE(\\genblk8[4].right_gain_pb[29]_i_2_n_0 ),\n .D(\\genblk8[4].right_gain_pb[26]_i_1_n_0 ),\n .Q(\\genblk8[4].right_gain_pb_reg__0 [2]),\n .R(\\genblk8[4].right_gain_pb[29]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[4].right_gain_pb_reg[27] \n (.C(CLK),\n .CE(\\genblk8[4].right_gain_pb[29]_i_2_n_0 ),\n .D(\\genblk8[4].right_gain_pb[27]_i_1_n_0 ),\n .Q(\\genblk8[4].right_gain_pb_reg__0 [3]),\n .R(\\genblk8[4].right_gain_pb[29]_i_1_n_0 ));\n CARRY4 \\genblk8[4].right_gain_pb_reg[27]_i_2 \n (.CI(1'b0),\n .CO({\\genblk8[4].right_gain_pb_reg[27]_i_2_n_0 ,\\genblk8[4].right_gain_pb_reg[27]_i_2_n_1 ,\\genblk8[4].right_gain_pb_reg[27]_i_2_n_2 ,\\genblk8[4].right_gain_pb_reg[27]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ,\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ,\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ,\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }),\n .O({\\genblk8[4].right_gain_pb_reg[27]_i_2_n_4 ,\\genblk8[4].right_gain_pb_reg[27]_i_2_n_5 ,\\genblk8[4].right_gain_pb_reg[27]_i_2_n_6 ,\\genblk8[4].right_gain_pb_reg[27]_i_2_n_7 }),\n .S({\\genblk8[4].right_gain_pb[27]_i_4_n_0 ,\\genblk8[4].right_gain_pb[27]_i_5_n_0 ,\\genblk8[4].right_gain_pb[27]_i_6_n_0 ,\\genblk8[4].right_gain_pb[27]_i_7_n_0 }));\n CARRY4 \\genblk8[4].right_gain_pb_reg[27]_i_3 \n (.CI(1'b0),\n .CO({\\genblk8[4].right_gain_pb_reg[27]_i_3_n_0 ,\\genblk8[4].right_gain_pb_reg[27]_i_3_n_1 ,\\genblk8[4].right_gain_pb_reg[27]_i_3_n_2 ,\\genblk8[4].right_gain_pb_reg[27]_i_3_n_3 }),\n .CYINIT(1'b1),\n .DI(right_edge_ref[3:0]),\n .O({\\genblk8[4].right_gain_pb_reg[27]_i_3_n_4 ,\\genblk8[4].right_gain_pb_reg[27]_i_3_n_5 ,\\genblk8[4].right_gain_pb_reg[27]_i_3_n_6 ,\\genblk8[4].right_gain_pb_reg[27]_i_3_n_7 }),\n .S({\\genblk8[4].right_gain_pb[27]_i_8_n_0 ,\\genblk8[4].right_gain_pb[27]_i_9_n_0 ,\\genblk8[4].right_gain_pb[27]_i_10_n_0 ,\\genblk8[4].right_gain_pb[27]_i_11_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[4].right_gain_pb_reg[28] \n (.C(CLK),\n .CE(\\genblk8[4].right_gain_pb[29]_i_2_n_0 ),\n .D(\\genblk8[4].right_gain_pb[28]_i_1_n_0 ),\n .Q(\\genblk8[4].right_gain_pb_reg__0 [4]),\n .R(\\genblk8[4].right_gain_pb[29]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[4].right_gain_pb_reg[29] \n (.C(CLK),\n .CE(\\genblk8[4].right_gain_pb[29]_i_2_n_0 ),\n .D(\\genblk8[4].right_gain_pb[29]_i_3_n_0 ),\n .Q(\\genblk8[4].right_gain_pb_reg__0 [5]),\n .R(\\genblk8[4].right_gain_pb[29]_i_1_n_0 ));\n CARRY4 \\genblk8[4].right_gain_pb_reg[29]_i_15 \n (.CI(\\genblk8[4].right_gain_pb_reg[29]_i_18_n_0 ),\n .CO({\\genblk8[4].right_gain_pb_reg[29]_i_15_n_0 ,\\genblk8[4].right_gain_pb_reg[29]_i_15_n_1 ,\\genblk8[4].right_gain_pb_reg[29]_i_15_n_2 ,\\genblk8[4].right_gain_pb_reg[29]_i_15_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[4].right_gain_pb_reg[29]_i_15_O_UNCONNECTED [3:0]),\n .S({\\genblk8[4].right_gain_pb[29]_i_19_n_0 ,\\genblk8[4].right_gain_pb[29]_i_20_n_0 ,\\genblk8[4].right_gain_pb[29]_i_21_n_0 ,\\genblk8[4].right_gain_pb[29]_i_22_n_0 }));\n CARRY4 \\genblk8[4].right_gain_pb_reg[29]_i_18 \n (.CI(\\genblk8[4].right_gain_pb_reg[29]_i_23_n_0 ),\n .CO({\\genblk8[4].right_gain_pb_reg[29]_i_18_n_0 ,\\genblk8[4].right_gain_pb_reg[29]_i_18_n_1 ,\\genblk8[4].right_gain_pb_reg[29]_i_18_n_2 ,\\genblk8[4].right_gain_pb_reg[29]_i_18_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[4].right_gain_pb_reg[29]_i_18_O_UNCONNECTED [3:0]),\n .S({\\genblk8[4].right_gain_pb[29]_i_24_n_0 ,\\genblk8[4].right_gain_pb[29]_i_25_n_0 ,\\genblk8[4].right_gain_pb[29]_i_26_n_0 ,\\genblk8[4].right_gain_pb[29]_i_27_n_0 }));\n CARRY4 \\genblk8[4].right_gain_pb_reg[29]_i_23 \n (.CI(\\genblk8[4].right_gain_pb_reg[29]_i_28_n_0 ),\n .CO({\\genblk8[4].right_gain_pb_reg[29]_i_23_n_0 ,\\genblk8[4].right_gain_pb_reg[29]_i_23_n_1 ,\\genblk8[4].right_gain_pb_reg[29]_i_23_n_2 ,\\genblk8[4].right_gain_pb_reg[29]_i_23_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[4].right_gain_pb_reg[29]_i_23_O_UNCONNECTED [3:0]),\n .S({\\genblk8[4].right_gain_pb[29]_i_29_n_0 ,\\genblk8[4].right_gain_pb[29]_i_30_n_0 ,\\genblk8[4].right_gain_pb[29]_i_31_n_0 ,\\genblk8[4].right_gain_pb[29]_i_32_n_0 }));\n CARRY4 \\genblk8[4].right_gain_pb_reg[29]_i_28 \n (.CI(1'b0),\n .CO({\\genblk8[4].right_gain_pb_reg[29]_i_28_n_0 ,\\genblk8[4].right_gain_pb_reg[29]_i_28_n_1 ,\\genblk8[4].right_gain_pb_reg[29]_i_28_n_2 ,\\genblk8[4].right_gain_pb_reg[29]_i_28_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,\\genblk8[4].right_gain_pb[29]_i_33_n_0 ,\\genblk8[4].right_gain_pb[29]_i_34_n_0 ,\\genblk8[4].right_gain_pb[29]_i_35_n_0 }),\n .O(\\NLW_genblk8[4].right_gain_pb_reg[29]_i_28_O_UNCONNECTED [3:0]),\n .S({\\genblk8[4].right_gain_pb[29]_i_36_n_0 ,\\genblk8[4].right_gain_pb[29]_i_37_n_0 ,\\genblk8[4].right_gain_pb[29]_i_38_n_0 ,\\genblk8[4].right_gain_pb[29]_i_39_n_0 }));\n MUXF7 \\genblk8[4].right_gain_pb_reg[29]_i_4 \n (.I0(\\genblk8[4].right_gain_pb[29]_i_7_n_0 ),\n .I1(\\genblk8[4].right_gain_pb[29]_i_8_n_0 ),\n .O(\\genblk8[4].right_gain_pb_reg[29]_i_4_n_0 ),\n .S(p_119_out));\n CARRY4 \\genblk8[4].right_gain_pb_reg[29]_i_5 \n (.CI(\\genblk8[4].right_gain_pb_reg[27]_i_2_n_0 ),\n .CO({\\NLW_genblk8[4].right_gain_pb_reg[29]_i_5_CO_UNCONNECTED [3:1],\\genblk8[4].right_gain_pb_reg[29]_i_5_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,\\prbs_dqs_tap_cnt_r_reg_n_0_[4] }),\n .O({\\NLW_genblk8[4].right_gain_pb_reg[29]_i_5_O_UNCONNECTED [3:2],\\genblk8[4].right_gain_pb_reg[29]_i_5_n_6 ,\\genblk8[4].right_gain_pb_reg[29]_i_5_n_7 }),\n .S({1'b0,1'b0,\\genblk8[4].right_gain_pb[29]_i_9_n_0 ,\\genblk8[4].right_gain_pb[29]_i_10_n_0 }));\n CARRY4 \\genblk8[4].right_gain_pb_reg[29]_i_6 \n (.CI(\\genblk8[4].right_gain_pb_reg[27]_i_3_n_0 ),\n .CO({\\NLW_genblk8[4].right_gain_pb_reg[29]_i_6_CO_UNCONNECTED [3:1],\\genblk8[4].right_gain_pb_reg[29]_i_6_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,right_edge_ref[4]}),\n .O({\\NLW_genblk8[4].right_gain_pb_reg[29]_i_6_O_UNCONNECTED [3:2],\\genblk8[4].right_gain_pb_reg[29]_i_6_n_6 ,\\genblk8[4].right_gain_pb_reg[29]_i_6_n_7 }),\n .S({1'b0,1'b0,\\genblk8[4].right_gain_pb[29]_i_11_n_0 ,\\genblk8[4].right_gain_pb[29]_i_12_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[5].left_edge_found_pb_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[5].left_edge_found_pb_reg[5]_0 ),\n .Q(\\genblk8[5].left_loss_pb_reg[30]_0 ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\genblk8[5].left_edge_pb[35]_i_1 \n (.I0(p_154_out),\n .I1(\\genblk8[5].right_gain_pb_reg[30]_0 ),\n .O(\\genblk8[5].left_edge_pb[35]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\genblk8[5].left_edge_pb[35]_i_2 \n (.I0(match_flag_pb[47]),\n .I1(\\genblk8[5].left_edge_pb[35]_i_3_n_0 ),\n .I2(\\genblk7[5].compare_err_pb_latch_r_reg_n_0_[5] ),\n .I3(match_flag_pb[46]),\n .I4(match_flag_pb[44]),\n .I5(match_flag_pb[45]),\n .O(\\genblk8[5].right_gain_pb_reg[30]_0 ));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\genblk8[5].left_edge_pb[35]_i_3 \n (.I0(match_flag_pb[42]),\n .I1(match_flag_pb[43]),\n .I2(match_flag_pb[40]),\n .I3(match_flag_pb[41]),\n .O(\\genblk8[5].left_edge_pb[35]_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[5].left_edge_pb_reg[30] \n (.C(CLK),\n .CE(\\genblk8[5].left_edge_pb[35]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[5].left_edge_pb_reg_n_0_[30] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[5].left_edge_pb_reg[31] \n (.C(CLK),\n .CE(\\genblk8[5].left_edge_pb[35]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[5].left_edge_pb_reg_n_0_[31] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[5].left_edge_pb_reg[32] \n (.C(CLK),\n .CE(\\genblk8[5].left_edge_pb[35]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[5].left_edge_pb_reg_n_0_[32] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[5].left_edge_pb_reg[33] \n (.C(CLK),\n .CE(\\genblk8[5].left_edge_pb[35]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[5].left_edge_pb_reg_n_0_[33] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[5].left_edge_pb_reg[34] \n (.C(CLK),\n .CE(\\genblk8[5].left_edge_pb[35]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[5].left_edge_pb_reg_n_0_[34] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[5].left_edge_pb_reg[35] \n (.C(CLK),\n .CE(\\genblk8[5].left_edge_pb[35]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[5]_i_3_n_0 ),\n .Q(\\genblk8[5].left_edge_pb_reg_n_0_[35] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[5].left_edge_updated_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[5].left_edge_updated_reg[5]_0 ),\n .Q(D[5]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAEFEAEAE)) \n \\genblk8[5].left_loss_pb[35]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(right_gain_pb),\n .I2(p_154_out),\n .I3(\\genblk8[5].left_loss_pb_reg[30]_0 ),\n .I4(\\genblk8[5].right_gain_pb_reg[30]_0 ),\n .O(\\genblk8[5].left_loss_pb[35]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[5].left_loss_pb_reg[30] \n (.C(CLK),\n .CE(\\genblk8[5].left_loss_pb[35]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[5].left_loss_pb_reg_n_0_[30] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[5].left_loss_pb_reg[31] \n (.C(CLK),\n .CE(\\genblk8[5].left_loss_pb[35]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[5].left_loss_pb_reg_n_0_[31] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[5].left_loss_pb_reg[32] \n (.C(CLK),\n .CE(\\genblk8[5].left_loss_pb[35]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[5].left_loss_pb_reg__0 [2]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[5].left_loss_pb_reg[33] \n (.C(CLK),\n .CE(\\genblk8[5].left_loss_pb[35]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[5].left_loss_pb_reg__0 [3]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[5].left_loss_pb_reg[34] \n (.C(CLK),\n .CE(\\genblk8[5].left_loss_pb[35]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[5].left_loss_pb_reg__0 [4]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[5].left_loss_pb_reg[35] \n (.C(CLK),\n .CE(\\genblk8[5].left_loss_pb[35]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[5]_i_2_n_0 ),\n .Q(\\genblk8[5].left_loss_pb_reg__0 [5]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[5].match_flag_pb_reg[40] \n (.C(CLK),\n .CE(p_154_out),\n .D(\\genblk7[5].compare_err_pb_latch_r_reg_n_0_[5] ),\n .Q(match_flag_pb[40]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[5].match_flag_pb_reg[41] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[40]),\n .Q(match_flag_pb[41]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[5].match_flag_pb_reg[42] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[41]),\n .Q(match_flag_pb[42]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[5].match_flag_pb_reg[43] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[42]),\n .Q(match_flag_pb[43]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[5].match_flag_pb_reg[44] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[43]),\n .Q(match_flag_pb[44]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[5].match_flag_pb_reg[45] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[44]),\n .Q(match_flag_pb[45]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[5].match_flag_pb_reg[46] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[45]),\n .Q(match_flag_pb[46]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[5].match_flag_pb_reg[47] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[46]),\n .Q(match_flag_pb[47]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[5].right_edge_found_pb_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[5].right_edge_found_pb_reg[5]_0 ),\n .Q(\\genblk8[5].right_edge_pb_reg[30]_0 ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAABAAAAAAAAA)) \n \\genblk8[5].right_edge_pb[35]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(\\genblk8[5].right_gain_pb_reg[30]_0 ),\n .I2(p_154_out),\n .I3(\\genblk8[5].right_edge_pb_reg[30]_1 ),\n .I4(\\genblk8[5].right_edge_pb_reg[30]_0 ),\n .I5(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .O(\\genblk8[5].right_edge_pb[35]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h08)) \n \\genblk8[5].right_edge_pb[35]_i_2 \n (.I0(p_154_out),\n .I1(\\genblk8[5].right_edge_pb_reg[30]_1 ),\n .I2(\\genblk8[5].right_gain_pb_reg[30]_0 ),\n .O(\\genblk8[5].right_edge_pb[35]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\genblk8[5].right_edge_pb[35]_i_3 \n (.I0(\\genblk7[5].compare_err_pb_latch_r_reg_n_0_[5] ),\n .I1(\\genblk8[5].left_edge_pb[35]_i_3_n_0 ),\n .I2(match_flag_pb[47]),\n .I3(match_flag_pb[46]),\n .I4(match_flag_pb[44]),\n .I5(match_flag_pb[45]),\n .O(\\genblk8[5].right_edge_pb_reg[30]_1 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[5].right_edge_pb_reg[30] \n (.C(CLK),\n .CE(\\genblk8[5].right_edge_pb[35]_i_2_n_0 ),\n .D(\\genblk8[0].left_edge_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[5].right_edge_pb_reg_n_0_[30] ),\n .S(\\genblk8[5].right_edge_pb[35]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[5].right_edge_pb_reg[31] \n (.C(CLK),\n .CE(\\genblk8[5].right_edge_pb[35]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[5].right_edge_pb_reg_n_0_[31] ),\n .S(\\genblk8[5].right_edge_pb[35]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[5].right_edge_pb_reg[32] \n (.C(CLK),\n .CE(\\genblk8[5].right_edge_pb[35]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[5].right_edge_pb_reg_n_0_[32] ),\n .S(\\genblk8[5].right_edge_pb[35]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[5].right_edge_pb_reg[33] \n (.C(CLK),\n .CE(\\genblk8[5].right_edge_pb[35]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[5].right_edge_pb_reg_n_0_[33] ),\n .S(\\genblk8[5].right_edge_pb[35]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[5].right_edge_pb_reg[34] \n (.C(CLK),\n .CE(\\genblk8[5].right_edge_pb[35]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[5].right_edge_pb_reg_n_0_[34] ),\n .S(\\genblk8[5].right_edge_pb[35]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[5].right_edge_pb_reg[35] \n (.C(CLK),\n .CE(\\genblk8[5].right_edge_pb[35]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[5]_i_3_n_0 ),\n .Q(\\genblk8[5].right_edge_pb_reg_n_0_[35] ),\n .S(\\genblk8[5].right_edge_pb[35]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[5].right_gain_pb[30]_i_1 \n (.I0(\\genblk8[5].right_edge_pb_reg[30]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[5].right_gain_pb_reg[33]_i_2_n_7 ),\n .I3(\\genblk8[5].right_gain_pb_reg[33]_i_3_n_7 ),\n .O(\\genblk8[5].right_gain_pb[30]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[5].right_gain_pb[31]_i_1 \n (.I0(\\genblk8[5].right_edge_pb_reg[30]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[5].right_gain_pb_reg[33]_i_2_n_6 ),\n .I3(\\genblk8[5].right_gain_pb_reg[33]_i_3_n_6 ),\n .O(\\genblk8[5].right_gain_pb[31]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[5].right_gain_pb[32]_i_1 \n (.I0(\\genblk8[5].right_edge_pb_reg[30]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[5].right_gain_pb_reg[33]_i_2_n_5 ),\n .I3(\\genblk8[5].right_gain_pb_reg[33]_i_3_n_5 ),\n .O(\\genblk8[5].right_gain_pb[32]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[5].right_gain_pb[33]_i_1 \n (.I0(\\genblk8[5].right_edge_pb_reg[30]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[5].right_gain_pb_reg[33]_i_2_n_4 ),\n .I3(\\genblk8[5].right_gain_pb_reg[33]_i_3_n_4 ),\n .O(\\genblk8[5].right_gain_pb[33]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[5].right_gain_pb[33]_i_10 \n (.I0(right_edge_ref[1]),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[31] ),\n .O(\\genblk8[5].right_gain_pb[33]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[5].right_gain_pb[33]_i_11 \n (.I0(right_edge_ref[0]),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[30] ),\n .O(\\genblk8[5].right_gain_pb[33]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[5].right_gain_pb[33]_i_4 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[33] ),\n .O(\\genblk8[5].right_gain_pb[33]_i_4_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[5].right_gain_pb[33]_i_5 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[32] ),\n .O(\\genblk8[5].right_gain_pb[33]_i_5_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[5].right_gain_pb[33]_i_6 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[31] ),\n .O(\\genblk8[5].right_gain_pb[33]_i_6_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[5].right_gain_pb[33]_i_7 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[30] ),\n .O(\\genblk8[5].right_gain_pb[33]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[5].right_gain_pb[33]_i_8 \n (.I0(right_edge_ref[3]),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[33] ),\n .O(\\genblk8[5].right_gain_pb[33]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[5].right_gain_pb[33]_i_9 \n (.I0(right_edge_ref[2]),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[32] ),\n .O(\\genblk8[5].right_gain_pb[33]_i_9_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[5].right_gain_pb[34]_i_1 \n (.I0(\\genblk8[5].right_edge_pb_reg[30]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[5].right_gain_pb_reg[35]_i_5_n_7 ),\n .I3(\\genblk8[5].right_gain_pb_reg[35]_i_6_n_7 ),\n .O(\\genblk8[5].right_gain_pb[34]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAEFEAEAE)) \n \\genblk8[5].right_gain_pb[35]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(right_gain_pb),\n .I2(p_154_out),\n .I3(\\genblk8[5].right_gain_pb_reg[30]_0 ),\n .I4(\\genblk8[5].right_gain_pb_reg[35]_i_4_n_0 ),\n .O(\\genblk8[5].right_gain_pb[35]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[5].right_gain_pb[35]_i_10 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[34] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[5].right_gain_pb[35]_i_11 \n (.I0(right_edge_ref[5]),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[35] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[5].right_gain_pb[35]_i_12 \n (.I0(right_edge_ref[4]),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[34] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_12_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk8[5].right_gain_pb[35]_i_13 \n (.I0(\\genblk8[5].right_gain_pb[35]_i_16_n_0 ),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[33] ),\n .I2(right_edge_ref[3]),\n .I3(\\genblk8[5].right_edge_pb_reg_n_0_[34] ),\n .I4(right_edge_ref[4]),\n .O(\\genblk8[5].right_gain_pb[35]_i_13_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk8[5].right_gain_pb[35]_i_14 \n (.I0(\\genblk8[5].right_gain_pb[35]_i_17_n_0 ),\n .I1(right_edge_ref[3]),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[33] ),\n .I3(right_edge_ref[4]),\n .I4(\\genblk8[5].right_edge_pb_reg_n_0_[34] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk8[5].right_gain_pb[35]_i_16 \n (.I0(right_edge_ref[0]),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[30] ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[31] ),\n .I3(right_edge_ref[1]),\n .I4(\\genblk8[5].right_edge_pb_reg_n_0_[32] ),\n .I5(right_edge_ref[2]),\n .O(\\genblk8[5].right_gain_pb[35]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk8[5].right_gain_pb[35]_i_17 \n (.I0(\\genblk8[5].right_edge_pb_reg_n_0_[30] ),\n .I1(right_edge_ref[0]),\n .I2(right_edge_ref[1]),\n .I3(\\genblk8[5].right_edge_pb_reg_n_0_[31] ),\n .I4(right_edge_ref[2]),\n .I5(\\genblk8[5].right_edge_pb_reg_n_0_[32] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[5].right_gain_pb[35]_i_19 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_19_n_0 ));\n LUT5 #(\n .INIT(32'h000000A8)) \n \\genblk8[5].right_gain_pb[35]_i_2 \n (.I0(p_154_out),\n .I1(\\genblk8[5].right_edge_pb_reg[30]_1 ),\n .I2(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .I3(\\genblk8[5].right_edge_pb_reg[30]_0 ),\n .I4(\\genblk8[5].right_gain_pb_reg[30]_0 ),\n .O(\\genblk8[5].right_gain_pb[35]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[5].right_gain_pb[35]_i_20 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[5].right_gain_pb[35]_i_21 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_21_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[5].right_gain_pb[35]_i_22 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_22_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[5].right_gain_pb[35]_i_24 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_24_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[5].right_gain_pb[35]_i_25 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_25_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[5].right_gain_pb[35]_i_26 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_26_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[5].right_gain_pb[35]_i_27 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_27_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[5].right_gain_pb[35]_i_29 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_29_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[5].right_gain_pb[35]_i_3 \n (.I0(\\genblk8[5].right_edge_pb_reg[30]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[5].right_gain_pb_reg[35]_i_5_n_6 ),\n .I3(\\genblk8[5].right_gain_pb_reg[35]_i_6_n_6 ),\n .O(\\genblk8[5].right_gain_pb[35]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[5].right_gain_pb[35]_i_30 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_30_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[5].right_gain_pb[35]_i_31 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_31_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[5].right_gain_pb[35]_i_32 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_32_n_0 ));\n LUT4 #(\n .INIT(16'hF880)) \n \\genblk8[5].right_gain_pb[35]_i_33 \n (.I0(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[34] ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[35] ),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[5].right_gain_pb[35]_i_33_n_0 ));\n LUT6 #(\n .INIT(64'h0808088CCECECEE0)) \n \\genblk8[5].right_gain_pb[35]_i_34 \n (.I0(\\genblk8[5].right_edge_pb_reg_n_0_[32] ),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[33] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[5].right_gain_pb[35]_i_34_n_0 ));\n LUT4 #(\n .INIT(16'h8CE0)) \n \\genblk8[5].right_gain_pb[35]_i_35 \n (.I0(\\genblk8[5].right_edge_pb_reg_n_0_[30] ),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[31] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\genblk8[5].right_gain_pb[35]_i_35_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[5].right_gain_pb[35]_i_36 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_36_n_0 ));\n LUT4 #(\n .INIT(16'h0660)) \n \\genblk8[5].right_gain_pb[35]_i_37 \n (.I0(\\genblk8[5].right_edge_pb_reg_n_0_[34] ),\n .I1(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[35] ),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[5].right_gain_pb[35]_i_37_n_0 ));\n LUT6 #(\n .INIT(64'h8484844221212118)) \n \\genblk8[5].right_gain_pb[35]_i_38 \n (.I0(\\genblk8[5].right_edge_pb_reg_n_0_[32] ),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[33] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[5].right_gain_pb[35]_i_38_n_0 ));\n LUT4 #(\n .INIT(16'h4218)) \n \\genblk8[5].right_gain_pb[35]_i_39 \n (.I0(\\genblk8[5].right_edge_pb_reg_n_0_[30] ),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[31] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\genblk8[5].right_gain_pb[35]_i_39_n_0 ));\n LUT5 #(\n .INIT(32'h04004404)) \n \\genblk8[5].right_gain_pb[35]_i_7 \n (.I0(\\genblk8[5].right_edge_pb_reg[30]_0 ),\n .I1(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .I2(right_edge_ref[5]),\n .I3(\\genblk8[5].right_edge_pb_reg_n_0_[35] ),\n .I4(\\genblk8[5].right_gain_pb[35]_i_13_n_0 ),\n .O(\\genblk8[5].right_gain_pb[35]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FFB200B2)) \n \\genblk8[5].right_gain_pb[35]_i_8 \n (.I0(\\genblk8[5].right_edge_pb_reg_n_0_[35] ),\n .I1(right_edge_ref[5]),\n .I2(\\genblk8[5].right_gain_pb[35]_i_14_n_0 ),\n .I3(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I4(\\genblk8[5].right_gain_pb_reg[35]_i_15_n_0 ),\n .I5(\\genblk8[5].right_edge_pb_reg[30]_0 ),\n .O(\\genblk8[5].right_gain_pb[35]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[5].right_gain_pb[35]_i_9 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[35] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_9_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[5].right_gain_pb_reg[30] \n (.C(CLK),\n .CE(\\genblk8[5].right_gain_pb[35]_i_2_n_0 ),\n .D(\\genblk8[5].right_gain_pb[30]_i_1_n_0 ),\n .Q(\\genblk8[5].right_gain_pb_reg_n_0_[30] ),\n .R(\\genblk8[5].right_gain_pb[35]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[5].right_gain_pb_reg[31] \n (.C(CLK),\n .CE(\\genblk8[5].right_gain_pb[35]_i_2_n_0 ),\n .D(\\genblk8[5].right_gain_pb[31]_i_1_n_0 ),\n .Q(\\genblk8[5].right_gain_pb_reg_n_0_[31] ),\n .R(\\genblk8[5].right_gain_pb[35]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[5].right_gain_pb_reg[32] \n (.C(CLK),\n .CE(\\genblk8[5].right_gain_pb[35]_i_2_n_0 ),\n .D(\\genblk8[5].right_gain_pb[32]_i_1_n_0 ),\n .Q(\\genblk8[5].right_gain_pb_reg__0 [2]),\n .R(\\genblk8[5].right_gain_pb[35]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[5].right_gain_pb_reg[33] \n (.C(CLK),\n .CE(\\genblk8[5].right_gain_pb[35]_i_2_n_0 ),\n .D(\\genblk8[5].right_gain_pb[33]_i_1_n_0 ),\n .Q(\\genblk8[5].right_gain_pb_reg__0 [3]),\n .R(\\genblk8[5].right_gain_pb[35]_i_1_n_0 ));\n CARRY4 \\genblk8[5].right_gain_pb_reg[33]_i_2 \n (.CI(1'b0),\n .CO({\\genblk8[5].right_gain_pb_reg[33]_i_2_n_0 ,\\genblk8[5].right_gain_pb_reg[33]_i_2_n_1 ,\\genblk8[5].right_gain_pb_reg[33]_i_2_n_2 ,\\genblk8[5].right_gain_pb_reg[33]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ,\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ,\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ,\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }),\n .O({\\genblk8[5].right_gain_pb_reg[33]_i_2_n_4 ,\\genblk8[5].right_gain_pb_reg[33]_i_2_n_5 ,\\genblk8[5].right_gain_pb_reg[33]_i_2_n_6 ,\\genblk8[5].right_gain_pb_reg[33]_i_2_n_7 }),\n .S({\\genblk8[5].right_gain_pb[33]_i_4_n_0 ,\\genblk8[5].right_gain_pb[33]_i_5_n_0 ,\\genblk8[5].right_gain_pb[33]_i_6_n_0 ,\\genblk8[5].right_gain_pb[33]_i_7_n_0 }));\n CARRY4 \\genblk8[5].right_gain_pb_reg[33]_i_3 \n (.CI(1'b0),\n .CO({\\genblk8[5].right_gain_pb_reg[33]_i_3_n_0 ,\\genblk8[5].right_gain_pb_reg[33]_i_3_n_1 ,\\genblk8[5].right_gain_pb_reg[33]_i_3_n_2 ,\\genblk8[5].right_gain_pb_reg[33]_i_3_n_3 }),\n .CYINIT(1'b1),\n .DI(right_edge_ref[3:0]),\n .O({\\genblk8[5].right_gain_pb_reg[33]_i_3_n_4 ,\\genblk8[5].right_gain_pb_reg[33]_i_3_n_5 ,\\genblk8[5].right_gain_pb_reg[33]_i_3_n_6 ,\\genblk8[5].right_gain_pb_reg[33]_i_3_n_7 }),\n .S({\\genblk8[5].right_gain_pb[33]_i_8_n_0 ,\\genblk8[5].right_gain_pb[33]_i_9_n_0 ,\\genblk8[5].right_gain_pb[33]_i_10_n_0 ,\\genblk8[5].right_gain_pb[33]_i_11_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[5].right_gain_pb_reg[34] \n (.C(CLK),\n .CE(\\genblk8[5].right_gain_pb[35]_i_2_n_0 ),\n .D(\\genblk8[5].right_gain_pb[34]_i_1_n_0 ),\n .Q(\\genblk8[5].right_gain_pb_reg__0 [4]),\n .R(\\genblk8[5].right_gain_pb[35]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[5].right_gain_pb_reg[35] \n (.C(CLK),\n .CE(\\genblk8[5].right_gain_pb[35]_i_2_n_0 ),\n .D(\\genblk8[5].right_gain_pb[35]_i_3_n_0 ),\n .Q(\\genblk8[5].right_gain_pb_reg__0 [5]),\n .R(\\genblk8[5].right_gain_pb[35]_i_1_n_0 ));\n CARRY4 \\genblk8[5].right_gain_pb_reg[35]_i_15 \n (.CI(\\genblk8[5].right_gain_pb_reg[35]_i_18_n_0 ),\n .CO({\\genblk8[5].right_gain_pb_reg[35]_i_15_n_0 ,\\genblk8[5].right_gain_pb_reg[35]_i_15_n_1 ,\\genblk8[5].right_gain_pb_reg[35]_i_15_n_2 ,\\genblk8[5].right_gain_pb_reg[35]_i_15_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[5].right_gain_pb_reg[35]_i_15_O_UNCONNECTED [3:0]),\n .S({\\genblk8[5].right_gain_pb[35]_i_19_n_0 ,\\genblk8[5].right_gain_pb[35]_i_20_n_0 ,\\genblk8[5].right_gain_pb[35]_i_21_n_0 ,\\genblk8[5].right_gain_pb[35]_i_22_n_0 }));\n CARRY4 \\genblk8[5].right_gain_pb_reg[35]_i_18 \n (.CI(\\genblk8[5].right_gain_pb_reg[35]_i_23_n_0 ),\n .CO({\\genblk8[5].right_gain_pb_reg[35]_i_18_n_0 ,\\genblk8[5].right_gain_pb_reg[35]_i_18_n_1 ,\\genblk8[5].right_gain_pb_reg[35]_i_18_n_2 ,\\genblk8[5].right_gain_pb_reg[35]_i_18_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[5].right_gain_pb_reg[35]_i_18_O_UNCONNECTED [3:0]),\n .S({\\genblk8[5].right_gain_pb[35]_i_24_n_0 ,\\genblk8[5].right_gain_pb[35]_i_25_n_0 ,\\genblk8[5].right_gain_pb[35]_i_26_n_0 ,\\genblk8[5].right_gain_pb[35]_i_27_n_0 }));\n CARRY4 \\genblk8[5].right_gain_pb_reg[35]_i_23 \n (.CI(\\genblk8[5].right_gain_pb_reg[35]_i_28_n_0 ),\n .CO({\\genblk8[5].right_gain_pb_reg[35]_i_23_n_0 ,\\genblk8[5].right_gain_pb_reg[35]_i_23_n_1 ,\\genblk8[5].right_gain_pb_reg[35]_i_23_n_2 ,\\genblk8[5].right_gain_pb_reg[35]_i_23_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[5].right_gain_pb_reg[35]_i_23_O_UNCONNECTED [3:0]),\n .S({\\genblk8[5].right_gain_pb[35]_i_29_n_0 ,\\genblk8[5].right_gain_pb[35]_i_30_n_0 ,\\genblk8[5].right_gain_pb[35]_i_31_n_0 ,\\genblk8[5].right_gain_pb[35]_i_32_n_0 }));\n CARRY4 \\genblk8[5].right_gain_pb_reg[35]_i_28 \n (.CI(1'b0),\n .CO({\\genblk8[5].right_gain_pb_reg[35]_i_28_n_0 ,\\genblk8[5].right_gain_pb_reg[35]_i_28_n_1 ,\\genblk8[5].right_gain_pb_reg[35]_i_28_n_2 ,\\genblk8[5].right_gain_pb_reg[35]_i_28_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,\\genblk8[5].right_gain_pb[35]_i_33_n_0 ,\\genblk8[5].right_gain_pb[35]_i_34_n_0 ,\\genblk8[5].right_gain_pb[35]_i_35_n_0 }),\n .O(\\NLW_genblk8[5].right_gain_pb_reg[35]_i_28_O_UNCONNECTED [3:0]),\n .S({\\genblk8[5].right_gain_pb[35]_i_36_n_0 ,\\genblk8[5].right_gain_pb[35]_i_37_n_0 ,\\genblk8[5].right_gain_pb[35]_i_38_n_0 ,\\genblk8[5].right_gain_pb[35]_i_39_n_0 }));\n MUXF7 \\genblk8[5].right_gain_pb_reg[35]_i_4 \n (.I0(\\genblk8[5].right_gain_pb[35]_i_7_n_0 ),\n .I1(\\genblk8[5].right_gain_pb[35]_i_8_n_0 ),\n .O(\\genblk8[5].right_gain_pb_reg[35]_i_4_n_0 ),\n .S(\\genblk8[5].right_edge_pb_reg[30]_1 ));\n CARRY4 \\genblk8[5].right_gain_pb_reg[35]_i_5 \n (.CI(\\genblk8[5].right_gain_pb_reg[33]_i_2_n_0 ),\n .CO({\\NLW_genblk8[5].right_gain_pb_reg[35]_i_5_CO_UNCONNECTED [3:1],\\genblk8[5].right_gain_pb_reg[35]_i_5_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,\\prbs_dqs_tap_cnt_r_reg_n_0_[4] }),\n .O({\\NLW_genblk8[5].right_gain_pb_reg[35]_i_5_O_UNCONNECTED [3:2],\\genblk8[5].right_gain_pb_reg[35]_i_5_n_6 ,\\genblk8[5].right_gain_pb_reg[35]_i_5_n_7 }),\n .S({1'b0,1'b0,\\genblk8[5].right_gain_pb[35]_i_9_n_0 ,\\genblk8[5].right_gain_pb[35]_i_10_n_0 }));\n CARRY4 \\genblk8[5].right_gain_pb_reg[35]_i_6 \n (.CI(\\genblk8[5].right_gain_pb_reg[33]_i_3_n_0 ),\n .CO({\\NLW_genblk8[5].right_gain_pb_reg[35]_i_6_CO_UNCONNECTED [3:1],\\genblk8[5].right_gain_pb_reg[35]_i_6_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,right_edge_ref[4]}),\n .O({\\NLW_genblk8[5].right_gain_pb_reg[35]_i_6_O_UNCONNECTED [3:2],\\genblk8[5].right_gain_pb_reg[35]_i_6_n_6 ,\\genblk8[5].right_gain_pb_reg[35]_i_6_n_7 }),\n .S({1'b0,1'b0,\\genblk8[5].right_gain_pb[35]_i_11_n_0 ,\\genblk8[5].right_gain_pb[35]_i_12_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[6].left_edge_found_pb_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[6].left_edge_found_pb_reg[6]_0 ),\n .Q(\\genblk8[6].left_loss_pb_reg[36]_0 ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\genblk8[6].left_edge_pb[41]_i_1 \n (.I0(p_154_out),\n .I1(p_106_out),\n .O(\\genblk8[6].left_edge_pb[41]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\genblk8[6].left_edge_pb[41]_i_2 \n (.I0(match_flag_pb[55]),\n .I1(\\genblk8[6].left_edge_pb[41]_i_3_n_0 ),\n .I2(\\genblk7[6].compare_err_pb_latch_r_reg_n_0_[6] ),\n .I3(match_flag_pb[54]),\n .I4(match_flag_pb[52]),\n .I5(match_flag_pb[53]),\n .O(p_106_out));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\genblk8[6].left_edge_pb[41]_i_3 \n (.I0(match_flag_pb[50]),\n .I1(match_flag_pb[51]),\n .I2(match_flag_pb[48]),\n .I3(match_flag_pb[49]),\n .O(\\genblk8[6].left_edge_pb[41]_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[6].left_edge_pb_reg[36] \n (.C(CLK),\n .CE(\\genblk8[6].left_edge_pb[41]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[6].left_edge_pb_reg_n_0_[36] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[6].left_edge_pb_reg[37] \n (.C(CLK),\n .CE(\\genblk8[6].left_edge_pb[41]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[6].left_edge_pb_reg_n_0_[37] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[6].left_edge_pb_reg[38] \n (.C(CLK),\n .CE(\\genblk8[6].left_edge_pb[41]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[6].left_edge_pb_reg_n_0_[38] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[6].left_edge_pb_reg[39] \n (.C(CLK),\n .CE(\\genblk8[6].left_edge_pb[41]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[6].left_edge_pb_reg_n_0_[39] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[6].left_edge_pb_reg[40] \n (.C(CLK),\n .CE(\\genblk8[6].left_edge_pb[41]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[6].left_edge_pb_reg_n_0_[40] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[6].left_edge_pb_reg[41] \n (.C(CLK),\n .CE(\\genblk8[6].left_edge_pb[41]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[5]_i_3_n_0 ),\n .Q(\\genblk8[6].left_edge_pb_reg_n_0_[41] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[6].left_edge_updated_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[6].left_edge_updated_reg[6]_0 ),\n .Q(D[6]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAEFEAEAE)) \n \\genblk8[6].left_loss_pb[41]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(right_gain_pb),\n .I2(p_154_out),\n .I3(\\genblk8[6].left_loss_pb_reg[36]_0 ),\n .I4(p_106_out),\n .O(\\genblk8[6].left_loss_pb[41]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[6].left_loss_pb_reg[36] \n (.C(CLK),\n .CE(\\genblk8[6].left_loss_pb[41]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[6].left_loss_pb_reg_n_0_[36] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[6].left_loss_pb_reg[37] \n (.C(CLK),\n .CE(\\genblk8[6].left_loss_pb[41]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[6].left_loss_pb_reg_n_0_[37] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[6].left_loss_pb_reg[38] \n (.C(CLK),\n .CE(\\genblk8[6].left_loss_pb[41]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[6].left_loss_pb_reg__0 [2]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[6].left_loss_pb_reg[39] \n (.C(CLK),\n .CE(\\genblk8[6].left_loss_pb[41]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[6].left_loss_pb_reg__0 [3]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[6].left_loss_pb_reg[40] \n (.C(CLK),\n .CE(\\genblk8[6].left_loss_pb[41]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[6].left_loss_pb_reg__0 [4]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[6].left_loss_pb_reg[41] \n (.C(CLK),\n .CE(\\genblk8[6].left_loss_pb[41]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[5]_i_2_n_0 ),\n .Q(\\genblk8[6].left_loss_pb_reg__0 [5]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[6].match_flag_pb_reg[48] \n (.C(CLK),\n .CE(p_154_out),\n .D(\\genblk7[6].compare_err_pb_latch_r_reg_n_0_[6] ),\n .Q(match_flag_pb[48]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[6].match_flag_pb_reg[49] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[48]),\n .Q(match_flag_pb[49]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[6].match_flag_pb_reg[50] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[49]),\n .Q(match_flag_pb[50]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[6].match_flag_pb_reg[51] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[50]),\n .Q(match_flag_pb[51]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[6].match_flag_pb_reg[52] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[51]),\n .Q(match_flag_pb[52]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[6].match_flag_pb_reg[53] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[52]),\n .Q(match_flag_pb[53]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[6].match_flag_pb_reg[54] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[53]),\n .Q(match_flag_pb[54]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[6].match_flag_pb_reg[55] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[54]),\n .Q(match_flag_pb[55]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[6].right_edge_found_pb_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[6].right_edge_found_pb_reg[6]_0 ),\n .Q(\\genblk8[6].right_edge_pb_reg[36]_0 ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAABAAAAAAAAA)) \n \\genblk8[6].right_edge_pb[41]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(p_106_out),\n .I2(p_154_out),\n .I3(p_103_out),\n .I4(\\genblk8[6].right_edge_pb_reg[36]_0 ),\n .I5(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .O(\\genblk8[6].right_edge_pb[41]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h08)) \n \\genblk8[6].right_edge_pb[41]_i_2 \n (.I0(p_154_out),\n .I1(p_103_out),\n .I2(p_106_out),\n .O(\\genblk8[6].right_edge_pb[41]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\genblk8[6].right_edge_pb[41]_i_3 \n (.I0(\\genblk7[6].compare_err_pb_latch_r_reg_n_0_[6] ),\n .I1(\\genblk8[6].left_edge_pb[41]_i_3_n_0 ),\n .I2(match_flag_pb[55]),\n .I3(match_flag_pb[54]),\n .I4(match_flag_pb[52]),\n .I5(match_flag_pb[53]),\n .O(p_103_out));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[6].right_edge_pb_reg[36] \n (.C(CLK),\n .CE(\\genblk8[6].right_edge_pb[41]_i_2_n_0 ),\n .D(\\genblk8[0].left_edge_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[6].right_edge_pb_reg_n_0_[36] ),\n .S(\\genblk8[6].right_edge_pb[41]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[6].right_edge_pb_reg[37] \n (.C(CLK),\n .CE(\\genblk8[6].right_edge_pb[41]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[6].right_edge_pb_reg_n_0_[37] ),\n .S(\\genblk8[6].right_edge_pb[41]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[6].right_edge_pb_reg[38] \n (.C(CLK),\n .CE(\\genblk8[6].right_edge_pb[41]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[6].right_edge_pb_reg_n_0_[38] ),\n .S(\\genblk8[6].right_edge_pb[41]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[6].right_edge_pb_reg[39] \n (.C(CLK),\n .CE(\\genblk8[6].right_edge_pb[41]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[6].right_edge_pb_reg_n_0_[39] ),\n .S(\\genblk8[6].right_edge_pb[41]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[6].right_edge_pb_reg[40] \n (.C(CLK),\n .CE(\\genblk8[6].right_edge_pb[41]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[6].right_edge_pb_reg_n_0_[40] ),\n .S(\\genblk8[6].right_edge_pb[41]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[6].right_edge_pb_reg[41] \n (.C(CLK),\n .CE(\\genblk8[6].right_edge_pb[41]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[5]_i_3_n_0 ),\n .Q(\\genblk8[6].right_edge_pb_reg_n_0_[41] ),\n .S(\\genblk8[6].right_edge_pb[41]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[6].right_gain_pb[36]_i_1 \n (.I0(p_103_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[6].right_gain_pb_reg[39]_i_2_n_7 ),\n .I3(\\genblk8[6].right_gain_pb_reg[39]_i_3_n_7 ),\n .O(\\genblk8[6].right_gain_pb[36]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[6].right_gain_pb[37]_i_1 \n (.I0(p_103_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[6].right_gain_pb_reg[39]_i_2_n_6 ),\n .I3(\\genblk8[6].right_gain_pb_reg[39]_i_3_n_6 ),\n .O(\\genblk8[6].right_gain_pb[37]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[6].right_gain_pb[38]_i_1 \n (.I0(p_103_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[6].right_gain_pb_reg[39]_i_2_n_5 ),\n .I3(\\genblk8[6].right_gain_pb_reg[39]_i_3_n_5 ),\n .O(\\genblk8[6].right_gain_pb[38]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[6].right_gain_pb[39]_i_1 \n (.I0(p_103_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[6].right_gain_pb_reg[39]_i_2_n_4 ),\n .I3(\\genblk8[6].right_gain_pb_reg[39]_i_3_n_4 ),\n .O(\\genblk8[6].right_gain_pb[39]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[6].right_gain_pb[39]_i_10 \n (.I0(right_edge_ref[1]),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[37] ),\n .O(\\genblk8[6].right_gain_pb[39]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[6].right_gain_pb[39]_i_11 \n (.I0(right_edge_ref[0]),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[36] ),\n .O(\\genblk8[6].right_gain_pb[39]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[6].right_gain_pb[39]_i_4 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[39] ),\n .O(\\genblk8[6].right_gain_pb[39]_i_4_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[6].right_gain_pb[39]_i_5 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[38] ),\n .O(\\genblk8[6].right_gain_pb[39]_i_5_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[6].right_gain_pb[39]_i_6 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[37] ),\n .O(\\genblk8[6].right_gain_pb[39]_i_6_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[6].right_gain_pb[39]_i_7 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[36] ),\n .O(\\genblk8[6].right_gain_pb[39]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[6].right_gain_pb[39]_i_8 \n (.I0(right_edge_ref[3]),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[39] ),\n .O(\\genblk8[6].right_gain_pb[39]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[6].right_gain_pb[39]_i_9 \n (.I0(right_edge_ref[2]),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[38] ),\n .O(\\genblk8[6].right_gain_pb[39]_i_9_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[6].right_gain_pb[40]_i_1 \n (.I0(p_103_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[6].right_gain_pb_reg[41]_i_5_n_7 ),\n .I3(\\genblk8[6].right_gain_pb_reg[41]_i_6_n_7 ),\n .O(\\genblk8[6].right_gain_pb[40]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAEFEAEAE)) \n \\genblk8[6].right_gain_pb[41]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(right_gain_pb),\n .I2(p_154_out),\n .I3(p_106_out),\n .I4(\\genblk8[6].right_gain_pb_reg[41]_i_4_n_0 ),\n .O(\\genblk8[6].right_gain_pb[41]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[6].right_gain_pb[41]_i_10 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[40] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[6].right_gain_pb[41]_i_11 \n (.I0(right_edge_ref[5]),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[41] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[6].right_gain_pb[41]_i_12 \n (.I0(right_edge_ref[4]),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[40] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_12_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk8[6].right_gain_pb[41]_i_13 \n (.I0(\\genblk8[6].right_gain_pb[41]_i_16_n_0 ),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[39] ),\n .I2(right_edge_ref[3]),\n .I3(\\genblk8[6].right_edge_pb_reg_n_0_[40] ),\n .I4(right_edge_ref[4]),\n .O(\\genblk8[6].right_gain_pb[41]_i_13_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk8[6].right_gain_pb[41]_i_14 \n (.I0(\\genblk8[6].right_gain_pb[41]_i_17_n_0 ),\n .I1(right_edge_ref[3]),\n .I2(\\genblk8[6].right_edge_pb_reg_n_0_[39] ),\n .I3(right_edge_ref[4]),\n .I4(\\genblk8[6].right_edge_pb_reg_n_0_[40] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk8[6].right_gain_pb[41]_i_16 \n (.I0(right_edge_ref[0]),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[36] ),\n .I2(\\genblk8[6].right_edge_pb_reg_n_0_[37] ),\n .I3(right_edge_ref[1]),\n .I4(\\genblk8[6].right_edge_pb_reg_n_0_[38] ),\n .I5(right_edge_ref[2]),\n .O(\\genblk8[6].right_gain_pb[41]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk8[6].right_gain_pb[41]_i_17 \n (.I0(\\genblk8[6].right_edge_pb_reg_n_0_[36] ),\n .I1(right_edge_ref[0]),\n .I2(right_edge_ref[1]),\n .I3(\\genblk8[6].right_edge_pb_reg_n_0_[37] ),\n .I4(right_edge_ref[2]),\n .I5(\\genblk8[6].right_edge_pb_reg_n_0_[38] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[6].right_gain_pb[41]_i_19 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_19_n_0 ));\n LUT5 #(\n .INIT(32'h000000A8)) \n \\genblk8[6].right_gain_pb[41]_i_2 \n (.I0(p_154_out),\n .I1(p_103_out),\n .I2(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .I3(\\genblk8[6].right_edge_pb_reg[36]_0 ),\n .I4(p_106_out),\n .O(\\genblk8[6].right_gain_pb[41]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[6].right_gain_pb[41]_i_20 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[6].right_gain_pb[41]_i_21 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_21_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[6].right_gain_pb[41]_i_22 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_22_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[6].right_gain_pb[41]_i_24 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_24_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[6].right_gain_pb[41]_i_25 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_25_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[6].right_gain_pb[41]_i_26 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_26_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[6].right_gain_pb[41]_i_27 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_27_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[6].right_gain_pb[41]_i_29 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_29_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[6].right_gain_pb[41]_i_3 \n (.I0(p_103_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[6].right_gain_pb_reg[41]_i_5_n_6 ),\n .I3(\\genblk8[6].right_gain_pb_reg[41]_i_6_n_6 ),\n .O(\\genblk8[6].right_gain_pb[41]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[6].right_gain_pb[41]_i_30 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_30_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[6].right_gain_pb[41]_i_31 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_31_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[6].right_gain_pb[41]_i_32 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_32_n_0 ));\n LUT4 #(\n .INIT(16'hF880)) \n \\genblk8[6].right_gain_pb[41]_i_33 \n (.I0(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[40] ),\n .I2(\\genblk8[6].right_edge_pb_reg_n_0_[41] ),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[6].right_gain_pb[41]_i_33_n_0 ));\n LUT6 #(\n .INIT(64'h0808088CCECECEE0)) \n \\genblk8[6].right_gain_pb[41]_i_34 \n (.I0(\\genblk8[6].right_edge_pb_reg_n_0_[38] ),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[39] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[6].right_gain_pb[41]_i_34_n_0 ));\n LUT4 #(\n .INIT(16'h8CE0)) \n \\genblk8[6].right_gain_pb[41]_i_35 \n (.I0(\\genblk8[6].right_edge_pb_reg_n_0_[36] ),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[37] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\genblk8[6].right_gain_pb[41]_i_35_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[6].right_gain_pb[41]_i_36 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_36_n_0 ));\n LUT4 #(\n .INIT(16'h0660)) \n \\genblk8[6].right_gain_pb[41]_i_37 \n (.I0(\\genblk8[6].right_edge_pb_reg_n_0_[40] ),\n .I1(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I2(\\genblk8[6].right_edge_pb_reg_n_0_[41] ),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[6].right_gain_pb[41]_i_37_n_0 ));\n LUT6 #(\n .INIT(64'h8484844221212118)) \n \\genblk8[6].right_gain_pb[41]_i_38 \n (.I0(\\genblk8[6].right_edge_pb_reg_n_0_[38] ),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[39] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[6].right_gain_pb[41]_i_38_n_0 ));\n LUT4 #(\n .INIT(16'h4218)) \n \\genblk8[6].right_gain_pb[41]_i_39 \n (.I0(\\genblk8[6].right_edge_pb_reg_n_0_[36] ),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[37] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\genblk8[6].right_gain_pb[41]_i_39_n_0 ));\n LUT5 #(\n .INIT(32'h04004404)) \n \\genblk8[6].right_gain_pb[41]_i_7 \n (.I0(\\genblk8[6].right_edge_pb_reg[36]_0 ),\n .I1(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .I2(right_edge_ref[5]),\n .I3(\\genblk8[6].right_edge_pb_reg_n_0_[41] ),\n .I4(\\genblk8[6].right_gain_pb[41]_i_13_n_0 ),\n .O(\\genblk8[6].right_gain_pb[41]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FFB200B2)) \n \\genblk8[6].right_gain_pb[41]_i_8 \n (.I0(\\genblk8[6].right_edge_pb_reg_n_0_[41] ),\n .I1(right_edge_ref[5]),\n .I2(\\genblk8[6].right_gain_pb[41]_i_14_n_0 ),\n .I3(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I4(\\genblk8[6].right_gain_pb_reg[41]_i_15_n_0 ),\n .I5(\\genblk8[6].right_edge_pb_reg[36]_0 ),\n .O(\\genblk8[6].right_gain_pb[41]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[6].right_gain_pb[41]_i_9 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[41] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_9_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[6].right_gain_pb_reg[36] \n (.C(CLK),\n .CE(\\genblk8[6].right_gain_pb[41]_i_2_n_0 ),\n .D(\\genblk8[6].right_gain_pb[36]_i_1_n_0 ),\n .Q(\\genblk8[6].right_gain_pb_reg_n_0_[36] ),\n .R(\\genblk8[6].right_gain_pb[41]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[6].right_gain_pb_reg[37] \n (.C(CLK),\n .CE(\\genblk8[6].right_gain_pb[41]_i_2_n_0 ),\n .D(\\genblk8[6].right_gain_pb[37]_i_1_n_0 ),\n .Q(\\genblk8[6].right_gain_pb_reg_n_0_[37] ),\n .R(\\genblk8[6].right_gain_pb[41]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[6].right_gain_pb_reg[38] \n (.C(CLK),\n .CE(\\genblk8[6].right_gain_pb[41]_i_2_n_0 ),\n .D(\\genblk8[6].right_gain_pb[38]_i_1_n_0 ),\n .Q(\\genblk8[6].right_gain_pb_reg__0 [2]),\n .R(\\genblk8[6].right_gain_pb[41]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[6].right_gain_pb_reg[39] \n (.C(CLK),\n .CE(\\genblk8[6].right_gain_pb[41]_i_2_n_0 ),\n .D(\\genblk8[6].right_gain_pb[39]_i_1_n_0 ),\n .Q(\\genblk8[6].right_gain_pb_reg__0 [3]),\n .R(\\genblk8[6].right_gain_pb[41]_i_1_n_0 ));\n CARRY4 \\genblk8[6].right_gain_pb_reg[39]_i_2 \n (.CI(1'b0),\n .CO({\\genblk8[6].right_gain_pb_reg[39]_i_2_n_0 ,\\genblk8[6].right_gain_pb_reg[39]_i_2_n_1 ,\\genblk8[6].right_gain_pb_reg[39]_i_2_n_2 ,\\genblk8[6].right_gain_pb_reg[39]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ,\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ,\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ,\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }),\n .O({\\genblk8[6].right_gain_pb_reg[39]_i_2_n_4 ,\\genblk8[6].right_gain_pb_reg[39]_i_2_n_5 ,\\genblk8[6].right_gain_pb_reg[39]_i_2_n_6 ,\\genblk8[6].right_gain_pb_reg[39]_i_2_n_7 }),\n .S({\\genblk8[6].right_gain_pb[39]_i_4_n_0 ,\\genblk8[6].right_gain_pb[39]_i_5_n_0 ,\\genblk8[6].right_gain_pb[39]_i_6_n_0 ,\\genblk8[6].right_gain_pb[39]_i_7_n_0 }));\n CARRY4 \\genblk8[6].right_gain_pb_reg[39]_i_3 \n (.CI(1'b0),\n .CO({\\genblk8[6].right_gain_pb_reg[39]_i_3_n_0 ,\\genblk8[6].right_gain_pb_reg[39]_i_3_n_1 ,\\genblk8[6].right_gain_pb_reg[39]_i_3_n_2 ,\\genblk8[6].right_gain_pb_reg[39]_i_3_n_3 }),\n .CYINIT(1'b1),\n .DI(right_edge_ref[3:0]),\n .O({\\genblk8[6].right_gain_pb_reg[39]_i_3_n_4 ,\\genblk8[6].right_gain_pb_reg[39]_i_3_n_5 ,\\genblk8[6].right_gain_pb_reg[39]_i_3_n_6 ,\\genblk8[6].right_gain_pb_reg[39]_i_3_n_7 }),\n .S({\\genblk8[6].right_gain_pb[39]_i_8_n_0 ,\\genblk8[6].right_gain_pb[39]_i_9_n_0 ,\\genblk8[6].right_gain_pb[39]_i_10_n_0 ,\\genblk8[6].right_gain_pb[39]_i_11_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[6].right_gain_pb_reg[40] \n (.C(CLK),\n .CE(\\genblk8[6].right_gain_pb[41]_i_2_n_0 ),\n .D(\\genblk8[6].right_gain_pb[40]_i_1_n_0 ),\n .Q(\\genblk8[6].right_gain_pb_reg__0 [4]),\n .R(\\genblk8[6].right_gain_pb[41]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[6].right_gain_pb_reg[41] \n (.C(CLK),\n .CE(\\genblk8[6].right_gain_pb[41]_i_2_n_0 ),\n .D(\\genblk8[6].right_gain_pb[41]_i_3_n_0 ),\n .Q(\\genblk8[6].right_gain_pb_reg__0 [5]),\n .R(\\genblk8[6].right_gain_pb[41]_i_1_n_0 ));\n CARRY4 \\genblk8[6].right_gain_pb_reg[41]_i_15 \n (.CI(\\genblk8[6].right_gain_pb_reg[41]_i_18_n_0 ),\n .CO({\\genblk8[6].right_gain_pb_reg[41]_i_15_n_0 ,\\genblk8[6].right_gain_pb_reg[41]_i_15_n_1 ,\\genblk8[6].right_gain_pb_reg[41]_i_15_n_2 ,\\genblk8[6].right_gain_pb_reg[41]_i_15_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[6].right_gain_pb_reg[41]_i_15_O_UNCONNECTED [3:0]),\n .S({\\genblk8[6].right_gain_pb[41]_i_19_n_0 ,\\genblk8[6].right_gain_pb[41]_i_20_n_0 ,\\genblk8[6].right_gain_pb[41]_i_21_n_0 ,\\genblk8[6].right_gain_pb[41]_i_22_n_0 }));\n CARRY4 \\genblk8[6].right_gain_pb_reg[41]_i_18 \n (.CI(\\genblk8[6].right_gain_pb_reg[41]_i_23_n_0 ),\n .CO({\\genblk8[6].right_gain_pb_reg[41]_i_18_n_0 ,\\genblk8[6].right_gain_pb_reg[41]_i_18_n_1 ,\\genblk8[6].right_gain_pb_reg[41]_i_18_n_2 ,\\genblk8[6].right_gain_pb_reg[41]_i_18_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[6].right_gain_pb_reg[41]_i_18_O_UNCONNECTED [3:0]),\n .S({\\genblk8[6].right_gain_pb[41]_i_24_n_0 ,\\genblk8[6].right_gain_pb[41]_i_25_n_0 ,\\genblk8[6].right_gain_pb[41]_i_26_n_0 ,\\genblk8[6].right_gain_pb[41]_i_27_n_0 }));\n CARRY4 \\genblk8[6].right_gain_pb_reg[41]_i_23 \n (.CI(\\genblk8[6].right_gain_pb_reg[41]_i_28_n_0 ),\n .CO({\\genblk8[6].right_gain_pb_reg[41]_i_23_n_0 ,\\genblk8[6].right_gain_pb_reg[41]_i_23_n_1 ,\\genblk8[6].right_gain_pb_reg[41]_i_23_n_2 ,\\genblk8[6].right_gain_pb_reg[41]_i_23_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[6].right_gain_pb_reg[41]_i_23_O_UNCONNECTED [3:0]),\n .S({\\genblk8[6].right_gain_pb[41]_i_29_n_0 ,\\genblk8[6].right_gain_pb[41]_i_30_n_0 ,\\genblk8[6].right_gain_pb[41]_i_31_n_0 ,\\genblk8[6].right_gain_pb[41]_i_32_n_0 }));\n CARRY4 \\genblk8[6].right_gain_pb_reg[41]_i_28 \n (.CI(1'b0),\n .CO({\\genblk8[6].right_gain_pb_reg[41]_i_28_n_0 ,\\genblk8[6].right_gain_pb_reg[41]_i_28_n_1 ,\\genblk8[6].right_gain_pb_reg[41]_i_28_n_2 ,\\genblk8[6].right_gain_pb_reg[41]_i_28_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,\\genblk8[6].right_gain_pb[41]_i_33_n_0 ,\\genblk8[6].right_gain_pb[41]_i_34_n_0 ,\\genblk8[6].right_gain_pb[41]_i_35_n_0 }),\n .O(\\NLW_genblk8[6].right_gain_pb_reg[41]_i_28_O_UNCONNECTED [3:0]),\n .S({\\genblk8[6].right_gain_pb[41]_i_36_n_0 ,\\genblk8[6].right_gain_pb[41]_i_37_n_0 ,\\genblk8[6].right_gain_pb[41]_i_38_n_0 ,\\genblk8[6].right_gain_pb[41]_i_39_n_0 }));\n MUXF7 \\genblk8[6].right_gain_pb_reg[41]_i_4 \n (.I0(\\genblk8[6].right_gain_pb[41]_i_7_n_0 ),\n .I1(\\genblk8[6].right_gain_pb[41]_i_8_n_0 ),\n .O(\\genblk8[6].right_gain_pb_reg[41]_i_4_n_0 ),\n .S(p_103_out));\n CARRY4 \\genblk8[6].right_gain_pb_reg[41]_i_5 \n (.CI(\\genblk8[6].right_gain_pb_reg[39]_i_2_n_0 ),\n .CO({\\NLW_genblk8[6].right_gain_pb_reg[41]_i_5_CO_UNCONNECTED [3:1],\\genblk8[6].right_gain_pb_reg[41]_i_5_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,\\prbs_dqs_tap_cnt_r_reg_n_0_[4] }),\n .O({\\NLW_genblk8[6].right_gain_pb_reg[41]_i_5_O_UNCONNECTED [3:2],\\genblk8[6].right_gain_pb_reg[41]_i_5_n_6 ,\\genblk8[6].right_gain_pb_reg[41]_i_5_n_7 }),\n .S({1'b0,1'b0,\\genblk8[6].right_gain_pb[41]_i_9_n_0 ,\\genblk8[6].right_gain_pb[41]_i_10_n_0 }));\n CARRY4 \\genblk8[6].right_gain_pb_reg[41]_i_6 \n (.CI(\\genblk8[6].right_gain_pb_reg[39]_i_3_n_0 ),\n .CO({\\NLW_genblk8[6].right_gain_pb_reg[41]_i_6_CO_UNCONNECTED [3:1],\\genblk8[6].right_gain_pb_reg[41]_i_6_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,right_edge_ref[4]}),\n .O({\\NLW_genblk8[6].right_gain_pb_reg[41]_i_6_O_UNCONNECTED [3:2],\\genblk8[6].right_gain_pb_reg[41]_i_6_n_6 ,\\genblk8[6].right_gain_pb_reg[41]_i_6_n_7 }),\n .S({1'b0,1'b0,\\genblk8[6].right_gain_pb[41]_i_11_n_0 ,\\genblk8[6].right_gain_pb[41]_i_12_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[7].left_edge_found_pb_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[7].left_edge_found_pb_reg[7]_0 ),\n .Q(\\genblk8[7].left_loss_pb_reg[42]_0 ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\genblk8[7].left_edge_pb[47]_i_1 \n (.I0(p_154_out),\n .I1(p_98_out),\n .O(\\genblk8[7].left_edge_pb[47]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\genblk8[7].left_edge_pb[47]_i_2 \n (.I0(match_flag_pb[63]),\n .I1(\\genblk8[7].left_edge_pb[47]_i_3_n_0 ),\n .I2(\\genblk7[7].compare_err_pb_latch_r_reg_n_0_[7] ),\n .I3(match_flag_pb[62]),\n .I4(match_flag_pb[60]),\n .I5(match_flag_pb[61]),\n .O(p_98_out));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\genblk8[7].left_edge_pb[47]_i_3 \n (.I0(match_flag_pb[58]),\n .I1(match_flag_pb[59]),\n .I2(match_flag_pb[56]),\n .I3(match_flag_pb[57]),\n .O(\\genblk8[7].left_edge_pb[47]_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[7].left_edge_pb_reg[42] \n (.C(CLK),\n .CE(\\genblk8[7].left_edge_pb[47]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[7].left_edge_pb_reg_n_0_[42] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[7].left_edge_pb_reg[43] \n (.C(CLK),\n .CE(\\genblk8[7].left_edge_pb[47]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[7].left_edge_pb_reg_n_0_[43] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[7].left_edge_pb_reg[44] \n (.C(CLK),\n .CE(\\genblk8[7].left_edge_pb[47]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[7].left_edge_pb_reg_n_0_[44] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[7].left_edge_pb_reg[45] \n (.C(CLK),\n .CE(\\genblk8[7].left_edge_pb[47]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[7].left_edge_pb_reg_n_0_[45] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[7].left_edge_pb_reg[46] \n (.C(CLK),\n .CE(\\genblk8[7].left_edge_pb[47]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[7].left_edge_pb_reg_n_0_[46] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[7].left_edge_pb_reg[47] \n (.C(CLK),\n .CE(\\genblk8[7].left_edge_pb[47]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[5]_i_3_n_0 ),\n .Q(\\genblk8[7].left_edge_pb_reg_n_0_[47] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[7].left_edge_updated_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[7].left_edge_updated_reg[7]_1 ),\n .Q(D[7]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAEFEAEAE)) \n \\genblk8[7].left_loss_pb[47]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(right_gain_pb),\n .I2(p_154_out),\n .I3(\\genblk8[7].left_loss_pb_reg[42]_0 ),\n .I4(p_98_out),\n .O(\\genblk8[7].left_loss_pb[47]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[7].left_loss_pb_reg[42] \n (.C(CLK),\n .CE(\\genblk8[7].left_loss_pb[47]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[7].left_loss_pb_reg_n_0_[42] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[7].left_loss_pb_reg[43] \n (.C(CLK),\n .CE(\\genblk8[7].left_loss_pb[47]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[7].left_loss_pb_reg_n_0_[43] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[7].left_loss_pb_reg[44] \n (.C(CLK),\n .CE(\\genblk8[7].left_loss_pb[47]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[7].left_loss_pb_reg__0 [2]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[7].left_loss_pb_reg[45] \n (.C(CLK),\n .CE(\\genblk8[7].left_loss_pb[47]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[7].left_loss_pb_reg__0 [3]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[7].left_loss_pb_reg[46] \n (.C(CLK),\n .CE(\\genblk8[7].left_loss_pb[47]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[7].left_loss_pb_reg__0 [4]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[7].left_loss_pb_reg[47] \n (.C(CLK),\n .CE(\\genblk8[7].left_loss_pb[47]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[5]_i_2_n_0 ),\n .Q(\\genblk8[7].left_loss_pb_reg__0 [5]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[7].match_flag_pb_reg[56] \n (.C(CLK),\n .CE(p_154_out),\n .D(\\genblk7[7].compare_err_pb_latch_r_reg_n_0_[7] ),\n .Q(match_flag_pb[56]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[7].match_flag_pb_reg[57] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[56]),\n .Q(match_flag_pb[57]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[7].match_flag_pb_reg[58] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[57]),\n .Q(match_flag_pb[58]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[7].match_flag_pb_reg[59] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[58]),\n .Q(match_flag_pb[59]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[7].match_flag_pb_reg[60] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[59]),\n .Q(match_flag_pb[60]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[7].match_flag_pb_reg[61] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[60]),\n .Q(match_flag_pb[61]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[7].match_flag_pb_reg[62] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[61]),\n .Q(match_flag_pb[62]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[7].match_flag_pb_reg[63] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[62]),\n .Q(match_flag_pb[63]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[7].right_edge_found_pb_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[7].right_edge_found_pb_reg[7]_0 ),\n .Q(\\genblk8[7].right_edge_pb_reg[42]_0 ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAABAAAAAAAAA)) \n \\genblk8[7].right_edge_pb[47]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(p_98_out),\n .I2(p_154_out),\n .I3(p_95_out),\n .I4(\\genblk8[7].right_edge_pb_reg[42]_0 ),\n .I5(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .O(\\genblk8[7].right_edge_pb[47]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h08)) \n \\genblk8[7].right_edge_pb[47]_i_2 \n (.I0(p_154_out),\n .I1(p_95_out),\n .I2(p_98_out),\n .O(\\genblk8[7].right_edge_pb[47]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\genblk8[7].right_edge_pb[47]_i_3 \n (.I0(\\genblk7[7].compare_err_pb_latch_r_reg_n_0_[7] ),\n .I1(\\genblk8[7].left_edge_pb[47]_i_3_n_0 ),\n .I2(match_flag_pb[63]),\n .I3(match_flag_pb[62]),\n .I4(match_flag_pb[60]),\n .I5(match_flag_pb[61]),\n .O(p_95_out));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[7].right_edge_pb_reg[42] \n (.C(CLK),\n .CE(\\genblk8[7].right_edge_pb[47]_i_2_n_0 ),\n .D(\\genblk8[0].left_edge_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[7].right_edge_pb_reg_n_0_[42] ),\n .S(\\genblk8[7].right_edge_pb[47]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[7].right_edge_pb_reg[43] \n (.C(CLK),\n .CE(\\genblk8[7].right_edge_pb[47]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[7].right_edge_pb_reg_n_0_[43] ),\n .S(\\genblk8[7].right_edge_pb[47]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[7].right_edge_pb_reg[44] \n (.C(CLK),\n .CE(\\genblk8[7].right_edge_pb[47]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[7].right_edge_pb_reg_n_0_[44] ),\n .S(\\genblk8[7].right_edge_pb[47]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[7].right_edge_pb_reg[45] \n (.C(CLK),\n .CE(\\genblk8[7].right_edge_pb[47]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[7].right_edge_pb_reg_n_0_[45] ),\n .S(\\genblk8[7].right_edge_pb[47]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[7].right_edge_pb_reg[46] \n (.C(CLK),\n .CE(\\genblk8[7].right_edge_pb[47]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[7].right_edge_pb_reg_n_0_[46] ),\n .S(\\genblk8[7].right_edge_pb[47]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\genblk8[7].right_edge_pb_reg[47] \n (.C(CLK),\n .CE(\\genblk8[7].right_edge_pb[47]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[5]_i_3_n_0 ),\n .Q(\\genblk8[7].right_edge_pb_reg_n_0_[47] ),\n .S(\\genblk8[7].right_edge_pb[47]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[7].right_gain_pb[42]_i_1 \n (.I0(p_95_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[7].right_gain_pb_reg[45]_i_2_n_7 ),\n .I3(\\genblk8[7].right_gain_pb_reg[45]_i_3_n_7 ),\n .O(\\genblk8[7].right_gain_pb[42]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[7].right_gain_pb[43]_i_1 \n (.I0(p_95_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[7].right_gain_pb_reg[45]_i_2_n_6 ),\n .I3(\\genblk8[7].right_gain_pb_reg[45]_i_3_n_6 ),\n .O(\\genblk8[7].right_gain_pb[43]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[7].right_gain_pb[44]_i_1 \n (.I0(p_95_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[7].right_gain_pb_reg[45]_i_2_n_5 ),\n .I3(\\genblk8[7].right_gain_pb_reg[45]_i_3_n_5 ),\n .O(\\genblk8[7].right_gain_pb[44]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[7].right_gain_pb[45]_i_1 \n (.I0(p_95_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[7].right_gain_pb_reg[45]_i_2_n_4 ),\n .I3(\\genblk8[7].right_gain_pb_reg[45]_i_3_n_4 ),\n .O(\\genblk8[7].right_gain_pb[45]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[7].right_gain_pb[45]_i_10 \n (.I0(right_edge_ref[1]),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[43] ),\n .O(\\genblk8[7].right_gain_pb[45]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[7].right_gain_pb[45]_i_11 \n (.I0(right_edge_ref[0]),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[42] ),\n .O(\\genblk8[7].right_gain_pb[45]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[7].right_gain_pb[45]_i_4 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[45] ),\n .O(\\genblk8[7].right_gain_pb[45]_i_4_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[7].right_gain_pb[45]_i_5 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[44] ),\n .O(\\genblk8[7].right_gain_pb[45]_i_5_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[7].right_gain_pb[45]_i_6 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[43] ),\n .O(\\genblk8[7].right_gain_pb[45]_i_6_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[7].right_gain_pb[45]_i_7 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[42] ),\n .O(\\genblk8[7].right_gain_pb[45]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[7].right_gain_pb[45]_i_8 \n (.I0(right_edge_ref[3]),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[45] ),\n .O(\\genblk8[7].right_gain_pb[45]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[7].right_gain_pb[45]_i_9 \n (.I0(right_edge_ref[2]),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[44] ),\n .O(\\genblk8[7].right_gain_pb[45]_i_9_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[7].right_gain_pb[46]_i_1 \n (.I0(p_95_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[7].right_gain_pb_reg[47]_i_5_n_7 ),\n .I3(\\genblk8[7].right_gain_pb_reg[47]_i_6_n_7 ),\n .O(\\genblk8[7].right_gain_pb[46]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAEFEAEAE)) \n \\genblk8[7].right_gain_pb[47]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(right_gain_pb),\n .I2(p_154_out),\n .I3(p_98_out),\n .I4(\\genblk8[7].right_gain_pb_reg[47]_i_4_n_0 ),\n .O(\\genblk8[7].right_gain_pb[47]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[7].right_gain_pb[47]_i_10 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[46] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[7].right_gain_pb[47]_i_11 \n (.I0(right_edge_ref[5]),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[47] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[7].right_gain_pb[47]_i_12 \n (.I0(right_edge_ref[4]),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[46] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_12_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk8[7].right_gain_pb[47]_i_13 \n (.I0(\\genblk8[7].right_gain_pb[47]_i_16_n_0 ),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[45] ),\n .I2(right_edge_ref[3]),\n .I3(\\genblk8[7].right_edge_pb_reg_n_0_[46] ),\n .I4(right_edge_ref[4]),\n .O(\\genblk8[7].right_gain_pb[47]_i_13_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk8[7].right_gain_pb[47]_i_14 \n (.I0(\\genblk8[7].right_gain_pb[47]_i_17_n_0 ),\n .I1(right_edge_ref[3]),\n .I2(\\genblk8[7].right_edge_pb_reg_n_0_[45] ),\n .I3(right_edge_ref[4]),\n .I4(\\genblk8[7].right_edge_pb_reg_n_0_[46] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk8[7].right_gain_pb[47]_i_16 \n (.I0(right_edge_ref[0]),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[42] ),\n .I2(\\genblk8[7].right_edge_pb_reg_n_0_[43] ),\n .I3(right_edge_ref[1]),\n .I4(\\genblk8[7].right_edge_pb_reg_n_0_[44] ),\n .I5(right_edge_ref[2]),\n .O(\\genblk8[7].right_gain_pb[47]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk8[7].right_gain_pb[47]_i_17 \n (.I0(\\genblk8[7].right_edge_pb_reg_n_0_[42] ),\n .I1(right_edge_ref[0]),\n .I2(right_edge_ref[1]),\n .I3(\\genblk8[7].right_edge_pb_reg_n_0_[43] ),\n .I4(right_edge_ref[2]),\n .I5(\\genblk8[7].right_edge_pb_reg_n_0_[44] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[7].right_gain_pb[47]_i_19 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_19_n_0 ));\n LUT5 #(\n .INIT(32'h000000A8)) \n \\genblk8[7].right_gain_pb[47]_i_2 \n (.I0(p_154_out),\n .I1(p_95_out),\n .I2(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .I3(\\genblk8[7].right_edge_pb_reg[42]_0 ),\n .I4(p_98_out),\n .O(\\genblk8[7].right_gain_pb[47]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[7].right_gain_pb[47]_i_20 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[7].right_gain_pb[47]_i_21 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_21_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[7].right_gain_pb[47]_i_22 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_22_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[7].right_gain_pb[47]_i_24 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_24_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[7].right_gain_pb[47]_i_25 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_25_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[7].right_gain_pb[47]_i_26 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_26_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[7].right_gain_pb[47]_i_27 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_27_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[7].right_gain_pb[47]_i_29 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_29_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[7].right_gain_pb[47]_i_3 \n (.I0(p_95_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[7].right_gain_pb_reg[47]_i_5_n_6 ),\n .I3(\\genblk8[7].right_gain_pb_reg[47]_i_6_n_6 ),\n .O(\\genblk8[7].right_gain_pb[47]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[7].right_gain_pb[47]_i_30 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_30_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[7].right_gain_pb[47]_i_31 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_31_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[7].right_gain_pb[47]_i_32 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_32_n_0 ));\n LUT4 #(\n .INIT(16'hF880)) \n \\genblk8[7].right_gain_pb[47]_i_33 \n (.I0(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[46] ),\n .I2(\\genblk8[7].right_edge_pb_reg_n_0_[47] ),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[7].right_gain_pb[47]_i_33_n_0 ));\n LUT6 #(\n .INIT(64'h0808088CCECECEE0)) \n \\genblk8[7].right_gain_pb[47]_i_34 \n (.I0(\\genblk8[7].right_edge_pb_reg_n_0_[44] ),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[45] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[7].right_gain_pb[47]_i_34_n_0 ));\n LUT4 #(\n .INIT(16'h8CE0)) \n \\genblk8[7].right_gain_pb[47]_i_35 \n (.I0(\\genblk8[7].right_edge_pb_reg_n_0_[42] ),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[43] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\genblk8[7].right_gain_pb[47]_i_35_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[7].right_gain_pb[47]_i_36 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_36_n_0 ));\n LUT4 #(\n .INIT(16'h0660)) \n \\genblk8[7].right_gain_pb[47]_i_37 \n (.I0(\\genblk8[7].right_edge_pb_reg_n_0_[46] ),\n .I1(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I2(\\genblk8[7].right_edge_pb_reg_n_0_[47] ),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[7].right_gain_pb[47]_i_37_n_0 ));\n LUT6 #(\n .INIT(64'h8484844221212118)) \n \\genblk8[7].right_gain_pb[47]_i_38 \n (.I0(\\genblk8[7].right_edge_pb_reg_n_0_[44] ),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[45] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[7].right_gain_pb[47]_i_38_n_0 ));\n LUT4 #(\n .INIT(16'h4218)) \n \\genblk8[7].right_gain_pb[47]_i_39 \n (.I0(\\genblk8[7].right_edge_pb_reg_n_0_[42] ),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[43] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\genblk8[7].right_gain_pb[47]_i_39_n_0 ));\n LUT5 #(\n .INIT(32'h04004404)) \n \\genblk8[7].right_gain_pb[47]_i_7 \n (.I0(\\genblk8[7].right_edge_pb_reg[42]_0 ),\n .I1(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .I2(right_edge_ref[5]),\n .I3(\\genblk8[7].right_edge_pb_reg_n_0_[47] ),\n .I4(\\genblk8[7].right_gain_pb[47]_i_13_n_0 ),\n .O(\\genblk8[7].right_gain_pb[47]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FFB200B2)) \n \\genblk8[7].right_gain_pb[47]_i_8 \n (.I0(\\genblk8[7].right_edge_pb_reg_n_0_[47] ),\n .I1(right_edge_ref[5]),\n .I2(\\genblk8[7].right_gain_pb[47]_i_14_n_0 ),\n .I3(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I4(\\genblk8[7].right_gain_pb_reg[47]_i_15_n_0 ),\n .I5(\\genblk8[7].right_edge_pb_reg[42]_0 ),\n .O(\\genblk8[7].right_gain_pb[47]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[7].right_gain_pb[47]_i_9 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[47] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_9_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[7].right_gain_pb_reg[42] \n (.C(CLK),\n .CE(\\genblk8[7].right_gain_pb[47]_i_2_n_0 ),\n .D(\\genblk8[7].right_gain_pb[42]_i_1_n_0 ),\n .Q(\\genblk8[7].right_gain_pb_reg_n_0_[42] ),\n .R(\\genblk8[7].right_gain_pb[47]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[7].right_gain_pb_reg[43] \n (.C(CLK),\n .CE(\\genblk8[7].right_gain_pb[47]_i_2_n_0 ),\n .D(\\genblk8[7].right_gain_pb[43]_i_1_n_0 ),\n .Q(\\genblk8[7].right_gain_pb_reg_n_0_[43] ),\n .R(\\genblk8[7].right_gain_pb[47]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[7].right_gain_pb_reg[44] \n (.C(CLK),\n .CE(\\genblk8[7].right_gain_pb[47]_i_2_n_0 ),\n .D(\\genblk8[7].right_gain_pb[44]_i_1_n_0 ),\n .Q(\\genblk8[7].right_gain_pb_reg__0 [2]),\n .R(\\genblk8[7].right_gain_pb[47]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[7].right_gain_pb_reg[45] \n (.C(CLK),\n .CE(\\genblk8[7].right_gain_pb[47]_i_2_n_0 ),\n .D(\\genblk8[7].right_gain_pb[45]_i_1_n_0 ),\n .Q(\\genblk8[7].right_gain_pb_reg__0 [3]),\n .R(\\genblk8[7].right_gain_pb[47]_i_1_n_0 ));\n CARRY4 \\genblk8[7].right_gain_pb_reg[45]_i_2 \n (.CI(1'b0),\n .CO({\\genblk8[7].right_gain_pb_reg[45]_i_2_n_0 ,\\genblk8[7].right_gain_pb_reg[45]_i_2_n_1 ,\\genblk8[7].right_gain_pb_reg[45]_i_2_n_2 ,\\genblk8[7].right_gain_pb_reg[45]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ,\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ,\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ,\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }),\n .O({\\genblk8[7].right_gain_pb_reg[45]_i_2_n_4 ,\\genblk8[7].right_gain_pb_reg[45]_i_2_n_5 ,\\genblk8[7].right_gain_pb_reg[45]_i_2_n_6 ,\\genblk8[7].right_gain_pb_reg[45]_i_2_n_7 }),\n .S({\\genblk8[7].right_gain_pb[45]_i_4_n_0 ,\\genblk8[7].right_gain_pb[45]_i_5_n_0 ,\\genblk8[7].right_gain_pb[45]_i_6_n_0 ,\\genblk8[7].right_gain_pb[45]_i_7_n_0 }));\n CARRY4 \\genblk8[7].right_gain_pb_reg[45]_i_3 \n (.CI(1'b0),\n .CO({\\genblk8[7].right_gain_pb_reg[45]_i_3_n_0 ,\\genblk8[7].right_gain_pb_reg[45]_i_3_n_1 ,\\genblk8[7].right_gain_pb_reg[45]_i_3_n_2 ,\\genblk8[7].right_gain_pb_reg[45]_i_3_n_3 }),\n .CYINIT(1'b1),\n .DI(right_edge_ref[3:0]),\n .O({\\genblk8[7].right_gain_pb_reg[45]_i_3_n_4 ,\\genblk8[7].right_gain_pb_reg[45]_i_3_n_5 ,\\genblk8[7].right_gain_pb_reg[45]_i_3_n_6 ,\\genblk8[7].right_gain_pb_reg[45]_i_3_n_7 }),\n .S({\\genblk8[7].right_gain_pb[45]_i_8_n_0 ,\\genblk8[7].right_gain_pb[45]_i_9_n_0 ,\\genblk8[7].right_gain_pb[45]_i_10_n_0 ,\\genblk8[7].right_gain_pb[45]_i_11_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[7].right_gain_pb_reg[46] \n (.C(CLK),\n .CE(\\genblk8[7].right_gain_pb[47]_i_2_n_0 ),\n .D(\\genblk8[7].right_gain_pb[46]_i_1_n_0 ),\n .Q(\\genblk8[7].right_gain_pb_reg__0 [4]),\n .R(\\genblk8[7].right_gain_pb[47]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk8[7].right_gain_pb_reg[47] \n (.C(CLK),\n .CE(\\genblk8[7].right_gain_pb[47]_i_2_n_0 ),\n .D(\\genblk8[7].right_gain_pb[47]_i_3_n_0 ),\n .Q(\\genblk8[7].right_gain_pb_reg__0 [5]),\n .R(\\genblk8[7].right_gain_pb[47]_i_1_n_0 ));\n CARRY4 \\genblk8[7].right_gain_pb_reg[47]_i_15 \n (.CI(\\genblk8[7].right_gain_pb_reg[47]_i_18_n_0 ),\n .CO({\\genblk8[7].right_gain_pb_reg[47]_i_15_n_0 ,\\genblk8[7].right_gain_pb_reg[47]_i_15_n_1 ,\\genblk8[7].right_gain_pb_reg[47]_i_15_n_2 ,\\genblk8[7].right_gain_pb_reg[47]_i_15_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[7].right_gain_pb_reg[47]_i_15_O_UNCONNECTED [3:0]),\n .S({\\genblk8[7].right_gain_pb[47]_i_19_n_0 ,\\genblk8[7].right_gain_pb[47]_i_20_n_0 ,\\genblk8[7].right_gain_pb[47]_i_21_n_0 ,\\genblk8[7].right_gain_pb[47]_i_22_n_0 }));\n CARRY4 \\genblk8[7].right_gain_pb_reg[47]_i_18 \n (.CI(\\genblk8[7].right_gain_pb_reg[47]_i_23_n_0 ),\n .CO({\\genblk8[7].right_gain_pb_reg[47]_i_18_n_0 ,\\genblk8[7].right_gain_pb_reg[47]_i_18_n_1 ,\\genblk8[7].right_gain_pb_reg[47]_i_18_n_2 ,\\genblk8[7].right_gain_pb_reg[47]_i_18_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[7].right_gain_pb_reg[47]_i_18_O_UNCONNECTED [3:0]),\n .S({\\genblk8[7].right_gain_pb[47]_i_24_n_0 ,\\genblk8[7].right_gain_pb[47]_i_25_n_0 ,\\genblk8[7].right_gain_pb[47]_i_26_n_0 ,\\genblk8[7].right_gain_pb[47]_i_27_n_0 }));\n CARRY4 \\genblk8[7].right_gain_pb_reg[47]_i_23 \n (.CI(\\genblk8[7].right_gain_pb_reg[47]_i_28_n_0 ),\n .CO({\\genblk8[7].right_gain_pb_reg[47]_i_23_n_0 ,\\genblk8[7].right_gain_pb_reg[47]_i_23_n_1 ,\\genblk8[7].right_gain_pb_reg[47]_i_23_n_2 ,\\genblk8[7].right_gain_pb_reg[47]_i_23_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[7].right_gain_pb_reg[47]_i_23_O_UNCONNECTED [3:0]),\n .S({\\genblk8[7].right_gain_pb[47]_i_29_n_0 ,\\genblk8[7].right_gain_pb[47]_i_30_n_0 ,\\genblk8[7].right_gain_pb[47]_i_31_n_0 ,\\genblk8[7].right_gain_pb[47]_i_32_n_0 }));\n CARRY4 \\genblk8[7].right_gain_pb_reg[47]_i_28 \n (.CI(1'b0),\n .CO({\\genblk8[7].right_gain_pb_reg[47]_i_28_n_0 ,\\genblk8[7].right_gain_pb_reg[47]_i_28_n_1 ,\\genblk8[7].right_gain_pb_reg[47]_i_28_n_2 ,\\genblk8[7].right_gain_pb_reg[47]_i_28_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,\\genblk8[7].right_gain_pb[47]_i_33_n_0 ,\\genblk8[7].right_gain_pb[47]_i_34_n_0 ,\\genblk8[7].right_gain_pb[47]_i_35_n_0 }),\n .O(\\NLW_genblk8[7].right_gain_pb_reg[47]_i_28_O_UNCONNECTED [3:0]),\n .S({\\genblk8[7].right_gain_pb[47]_i_36_n_0 ,\\genblk8[7].right_gain_pb[47]_i_37_n_0 ,\\genblk8[7].right_gain_pb[47]_i_38_n_0 ,\\genblk8[7].right_gain_pb[47]_i_39_n_0 }));\n MUXF7 \\genblk8[7].right_gain_pb_reg[47]_i_4 \n (.I0(\\genblk8[7].right_gain_pb[47]_i_7_n_0 ),\n .I1(\\genblk8[7].right_gain_pb[47]_i_8_n_0 ),\n .O(\\genblk8[7].right_gain_pb_reg[47]_i_4_n_0 ),\n .S(p_95_out));\n CARRY4 \\genblk8[7].right_gain_pb_reg[47]_i_5 \n (.CI(\\genblk8[7].right_gain_pb_reg[45]_i_2_n_0 ),\n .CO({\\NLW_genblk8[7].right_gain_pb_reg[47]_i_5_CO_UNCONNECTED [3:1],\\genblk8[7].right_gain_pb_reg[47]_i_5_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,\\prbs_dqs_tap_cnt_r_reg_n_0_[4] }),\n .O({\\NLW_genblk8[7].right_gain_pb_reg[47]_i_5_O_UNCONNECTED [3:2],\\genblk8[7].right_gain_pb_reg[47]_i_5_n_6 ,\\genblk8[7].right_gain_pb_reg[47]_i_5_n_7 }),\n .S({1'b0,1'b0,\\genblk8[7].right_gain_pb[47]_i_9_n_0 ,\\genblk8[7].right_gain_pb[47]_i_10_n_0 }));\n CARRY4 \\genblk8[7].right_gain_pb_reg[47]_i_6 \n (.CI(\\genblk8[7].right_gain_pb_reg[45]_i_3_n_0 ),\n .CO({\\NLW_genblk8[7].right_gain_pb_reg[47]_i_6_CO_UNCONNECTED [3:1],\\genblk8[7].right_gain_pb_reg[47]_i_6_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,right_edge_ref[4]}),\n .O({\\NLW_genblk8[7].right_gain_pb_reg[47]_i_6_O_UNCONNECTED [3:2],\\genblk8[7].right_gain_pb_reg[47]_i_6_n_6 ,\\genblk8[7].right_gain_pb_reg[47]_i_6_n_7 }),\n .S({1'b0,1'b0,\\genblk8[7].right_gain_pb[47]_i_11_n_0 ,\\genblk8[7].right_gain_pb[47]_i_12_n_0 }));\n LUT6 #(\n .INIT(64'h00000000AAAAAAA2)) \n \\genblk9[0].fine_delay_incdec_pb[0]_i_1 \n (.I0(\\genblk9[0].fine_delay_incdec_pb[0]_i_2_n_0 ),\n .I1(bit_cnt),\n .I2(\\genblk9[0].fine_delay_incdec_pb[0]_i_4_n_0 ),\n .I3(\\stage_cnt_reg_n_0_[0] ),\n .I4(\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ),\n .I5(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .O(\\genblk9[0].fine_delay_incdec_pb[0]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\genblk9[0].fine_delay_incdec_pb[0]_i_10 \n (.I0(ref_bit[6]),\n .I1(ref_bit[7]),\n .I2(ref_bit[4]),\n .I3(ref_bit[5]),\n .O(\\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk9[0].fine_delay_incdec_pb[0]_i_11 \n (.I0(\\genblk8[0].right_gain_pb_reg_n_0_[0] ),\n .I1(\\genblk8[0].left_loss_pb_reg_n_0_[0] ),\n .I2(\\genblk8[0].left_loss_pb_reg_n_0_[1] ),\n .I3(\\genblk8[0].right_gain_pb_reg_n_0_[1] ),\n .I4(\\genblk8[0].left_loss_pb_reg__0 [2]),\n .I5(\\genblk8[0].right_gain_pb_reg__0 [2]),\n .O(\\genblk9[0].fine_delay_incdec_pb[0]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'hFFB2FFFFFFB20000)) \n \\genblk9[0].fine_delay_incdec_pb[0]_i_2 \n (.I0(\\genblk8[0].right_gain_pb_reg__0 [5]),\n .I1(\\genblk8[0].left_loss_pb_reg__0 [5]),\n .I2(\\genblk9[0].fine_delay_incdec_pb[0]_i_5_n_0 ),\n .I3(\\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ),\n .I4(\\stage_cnt_reg[1]_0 ),\n .I5(\\fine_delay_mod_reg[26] ),\n .O(\\genblk9[0].fine_delay_incdec_pb[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000200)) \n \\genblk9[0].fine_delay_incdec_pb[0]_i_3 \n (.I0(bit_cnt_reg__0[3]),\n .I1(bit_cnt_reg__0[0]),\n .I2(bit_cnt_reg__0[4]),\n .I3(p_1_in159_in),\n .I4(bit_cnt_reg__0[2]),\n .I5(\\genblk9[0].fine_delay_incdec_pb[0]_i_9_n_0 ),\n .O(bit_cnt));\n (* SOFT_HLUTNM = \"soft_lutpair36\" *) \n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n \\genblk9[0].fine_delay_incdec_pb[0]_i_4 \n (.I0(\\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ),\n .I1(\\ref_bit_reg_n_0_[1] ),\n .I2(\\ref_bit_reg_n_0_[0] ),\n .I3(ref_bit[3]),\n .I4(\\ref_bit_reg_n_0_[2] ),\n .O(\\genblk9[0].fine_delay_incdec_pb[0]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk9[0].fine_delay_incdec_pb[0]_i_5 \n (.I0(\\genblk9[0].fine_delay_incdec_pb[0]_i_11_n_0 ),\n .I1(\\genblk8[0].left_loss_pb_reg__0 [3]),\n .I2(\\genblk8[0].right_gain_pb_reg__0 [3]),\n .I3(\\genblk8[0].left_loss_pb_reg__0 [4]),\n .I4(\\genblk8[0].right_gain_pb_reg__0 [4]),\n .O(\\genblk9[0].fine_delay_incdec_pb[0]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair74\" *) \n LUT3 #(\n .INIT(8'h02)) \n \\genblk9[0].fine_delay_incdec_pb[0]_i_6 \n (.I0(bit_cnt),\n .I1(\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ),\n .I2(\\stage_cnt_reg_n_0_[0] ),\n .O(\\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair17\" *) \n LUT5 #(\n .INIT(32'h04000000)) \n \\genblk9[0].fine_delay_incdec_pb[0]_i_8 \n (.I0(Q[3]),\n .I1(Q[4]),\n .I2(Q[2]),\n .I3(Q[0]),\n .I4(Q[1]),\n .O(p_1_in159_in));\n (* SOFT_HLUTNM = \"soft_lutpair54\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n \\genblk9[0].fine_delay_incdec_pb[0]_i_9 \n (.I0(bit_cnt_reg__0[1]),\n .I1(bit_cnt_reg__0[7]),\n .I2(bit_cnt_reg__0[5]),\n .I3(bit_cnt_reg__0[6]),\n .O(\\genblk9[0].fine_delay_incdec_pb[0]_i_9_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk9[0].fine_delay_incdec_pb_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk9[0].fine_delay_incdec_pb[0]_i_1_n_0 ),\n .Q(\\fine_delay_mod_reg[26] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000AAA8AAAA)) \n \\genblk9[1].fine_delay_incdec_pb[1]_i_1 \n (.I0(\\genblk9[1].fine_delay_incdec_pb[1]_i_2_n_0 ),\n .I1(\\genblk9[1].fine_delay_incdec_pb[1]_i_3_n_0 ),\n .I2(\\stage_cnt_reg_n_0_[0] ),\n .I3(\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ),\n .I4(bit_cnt),\n .I5(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .O(\\genblk9[1].fine_delay_incdec_pb[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFB2FFFFFFB20000)) \n \\genblk9[1].fine_delay_incdec_pb[1]_i_2 \n (.I0(\\genblk8[1].right_gain_pb_reg__0 [5]),\n .I1(\\genblk8[1].left_loss_pb_reg__0 [5]),\n .I2(\\genblk9[1].fine_delay_incdec_pb[1]_i_4_n_0 ),\n .I3(\\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ),\n .I4(\\stage_cnt_reg[1]_0 ),\n .I5(\\genblk9[1].fine_delay_incdec_pb_reg[1]_0 ),\n .O(\\genblk9[1].fine_delay_incdec_pb[1]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair37\" *) \n LUT5 #(\n .INIT(32'hFFFFFFEF)) \n \\genblk9[1].fine_delay_incdec_pb[1]_i_3 \n (.I0(\\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ),\n .I1(\\ref_bit_reg_n_0_[1] ),\n .I2(\\ref_bit_reg_n_0_[0] ),\n .I3(ref_bit[3]),\n .I4(\\ref_bit_reg_n_0_[2] ),\n .O(\\genblk9[1].fine_delay_incdec_pb[1]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk9[1].fine_delay_incdec_pb[1]_i_4 \n (.I0(\\genblk9[1].fine_delay_incdec_pb[1]_i_5_n_0 ),\n .I1(\\genblk8[1].left_loss_pb_reg__0 [3]),\n .I2(\\genblk8[1].right_gain_pb_reg__0 [3]),\n .I3(\\genblk8[1].left_loss_pb_reg__0 [4]),\n .I4(\\genblk8[1].right_gain_pb_reg__0 [4]),\n .O(\\genblk9[1].fine_delay_incdec_pb[1]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk9[1].fine_delay_incdec_pb[1]_i_5 \n (.I0(\\genblk8[1].right_gain_pb_reg_n_0_[6] ),\n .I1(\\genblk8[1].left_loss_pb_reg_n_0_[6] ),\n .I2(\\genblk8[1].left_loss_pb_reg_n_0_[7] ),\n .I3(\\genblk8[1].right_gain_pb_reg_n_0_[7] ),\n .I4(\\genblk8[1].left_loss_pb_reg__0 [2]),\n .I5(\\genblk8[1].right_gain_pb_reg__0 [2]),\n .O(\\genblk9[1].fine_delay_incdec_pb[1]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk9[1].fine_delay_incdec_pb_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk9[1].fine_delay_incdec_pb[1]_i_1_n_0 ),\n .Q(\\genblk9[1].fine_delay_incdec_pb_reg[1]_0 ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000AAA8AAAA)) \n \\genblk9[2].fine_delay_incdec_pb[2]_i_1 \n (.I0(\\genblk9[2].fine_delay_incdec_pb[2]_i_2_n_0 ),\n .I1(\\genblk9[2].fine_delay_incdec_pb[2]_i_3_n_0 ),\n .I2(\\stage_cnt_reg_n_0_[0] ),\n .I3(\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ),\n .I4(bit_cnt),\n .I5(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .O(\\genblk9[2].fine_delay_incdec_pb[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFB2FFFFFFB20000)) \n \\genblk9[2].fine_delay_incdec_pb[2]_i_2 \n (.I0(\\genblk8[2].right_gain_pb_reg__0 [5]),\n .I1(\\genblk8[2].left_loss_pb_reg__0 [5]),\n .I2(\\genblk9[2].fine_delay_incdec_pb[2]_i_4_n_0 ),\n .I3(\\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ),\n .I4(\\stage_cnt_reg[1]_0 ),\n .I5(\\genblk9[2].fine_delay_incdec_pb_reg[2]_0 ),\n .O(\\genblk9[2].fine_delay_incdec_pb[2]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair36\" *) \n LUT5 #(\n .INIT(32'hFFFFFFEF)) \n \\genblk9[2].fine_delay_incdec_pb[2]_i_3 \n (.I0(\\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ),\n .I1(\\ref_bit_reg_n_0_[0] ),\n .I2(\\ref_bit_reg_n_0_[1] ),\n .I3(ref_bit[3]),\n .I4(\\ref_bit_reg_n_0_[2] ),\n .O(\\genblk9[2].fine_delay_incdec_pb[2]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk9[2].fine_delay_incdec_pb[2]_i_4 \n (.I0(\\genblk9[2].fine_delay_incdec_pb[2]_i_5_n_0 ),\n .I1(\\genblk8[2].left_loss_pb_reg__0 [3]),\n .I2(\\genblk8[2].right_gain_pb_reg__0 [3]),\n .I3(\\genblk8[2].left_loss_pb_reg__0 [4]),\n .I4(\\genblk8[2].right_gain_pb_reg__0 [4]),\n .O(\\genblk9[2].fine_delay_incdec_pb[2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk9[2].fine_delay_incdec_pb[2]_i_5 \n (.I0(\\genblk8[2].right_gain_pb_reg_n_0_[12] ),\n .I1(\\genblk8[2].left_loss_pb_reg_n_0_[12] ),\n .I2(\\genblk8[2].left_loss_pb_reg_n_0_[13] ),\n .I3(\\genblk8[2].right_gain_pb_reg_n_0_[13] ),\n .I4(\\genblk8[2].left_loss_pb_reg__0 [2]),\n .I5(\\genblk8[2].right_gain_pb_reg__0 [2]),\n .O(\\genblk9[2].fine_delay_incdec_pb[2]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk9[2].fine_delay_incdec_pb_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk9[2].fine_delay_incdec_pb[2]_i_1_n_0 ),\n .Q(\\genblk9[2].fine_delay_incdec_pb_reg[2]_0 ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000AAA8AAAA)) \n \\genblk9[3].fine_delay_incdec_pb[3]_i_1 \n (.I0(\\genblk9[3].fine_delay_incdec_pb[3]_i_2_n_0 ),\n .I1(\\genblk9[3].fine_delay_incdec_pb[3]_i_3_n_0 ),\n .I2(\\stage_cnt_reg_n_0_[0] ),\n .I3(\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ),\n .I4(bit_cnt),\n .I5(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .O(\\genblk9[3].fine_delay_incdec_pb[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFB2FFFFFFB20000)) \n \\genblk9[3].fine_delay_incdec_pb[3]_i_2 \n (.I0(\\genblk8[3].right_gain_pb_reg__0 [5]),\n .I1(\\genblk8[3].left_loss_pb_reg__0 [5]),\n .I2(\\genblk9[3].fine_delay_incdec_pb[3]_i_4_n_0 ),\n .I3(\\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ),\n .I4(\\stage_cnt_reg[1]_0 ),\n .I5(\\genblk9[3].fine_delay_incdec_pb_reg[3]_0 ),\n .O(\\genblk9[3].fine_delay_incdec_pb[3]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair37\" *) \n LUT5 #(\n .INIT(32'hFFFFFFBF)) \n \\genblk9[3].fine_delay_incdec_pb[3]_i_3 \n (.I0(\\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ),\n .I1(\\ref_bit_reg_n_0_[1] ),\n .I2(\\ref_bit_reg_n_0_[0] ),\n .I3(ref_bit[3]),\n .I4(\\ref_bit_reg_n_0_[2] ),\n .O(\\genblk9[3].fine_delay_incdec_pb[3]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk9[3].fine_delay_incdec_pb[3]_i_4 \n (.I0(\\genblk9[3].fine_delay_incdec_pb[3]_i_5_n_0 ),\n .I1(\\genblk8[3].left_loss_pb_reg__0 [3]),\n .I2(\\genblk8[3].right_gain_pb_reg__0 [3]),\n .I3(\\genblk8[3].left_loss_pb_reg__0 [4]),\n .I4(\\genblk8[3].right_gain_pb_reg__0 [4]),\n .O(\\genblk9[3].fine_delay_incdec_pb[3]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk9[3].fine_delay_incdec_pb[3]_i_5 \n (.I0(\\genblk8[3].right_gain_pb_reg_n_0_[18] ),\n .I1(\\genblk8[3].left_loss_pb_reg_n_0_[18] ),\n .I2(\\genblk8[3].left_loss_pb_reg_n_0_[19] ),\n .I3(\\genblk8[3].right_gain_pb_reg_n_0_[19] ),\n .I4(\\genblk8[3].left_loss_pb_reg__0 [2]),\n .I5(\\genblk8[3].right_gain_pb_reg__0 [2]),\n .O(\\genblk9[3].fine_delay_incdec_pb[3]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk9[3].fine_delay_incdec_pb_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk9[3].fine_delay_incdec_pb[3]_i_1_n_0 ),\n .Q(\\genblk9[3].fine_delay_incdec_pb_reg[3]_0 ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000AAA8AAAA)) \n \\genblk9[4].fine_delay_incdec_pb[4]_i_1 \n (.I0(\\genblk9[4].fine_delay_incdec_pb[4]_i_2_n_0 ),\n .I1(\\genblk9[4].fine_delay_incdec_pb[4]_i_3_n_0 ),\n .I2(\\stage_cnt_reg_n_0_[0] ),\n .I3(\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ),\n .I4(bit_cnt),\n .I5(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .O(\\genblk9[4].fine_delay_incdec_pb[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFB2FFFFFFB20000)) \n \\genblk9[4].fine_delay_incdec_pb[4]_i_2 \n (.I0(\\genblk8[4].right_gain_pb_reg__0 [5]),\n .I1(\\genblk8[4].left_loss_pb_reg__0 [5]),\n .I2(\\genblk9[4].fine_delay_incdec_pb[4]_i_4_n_0 ),\n .I3(\\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ),\n .I4(\\stage_cnt_reg[1]_0 ),\n .I5(\\fine_delay_mod_reg[20] ),\n .O(\\genblk9[4].fine_delay_incdec_pb[4]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair35\" *) \n LUT5 #(\n .INIT(32'hFFFFFFEF)) \n \\genblk9[4].fine_delay_incdec_pb[4]_i_3 \n (.I0(\\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ),\n .I1(\\ref_bit_reg_n_0_[1] ),\n .I2(\\ref_bit_reg_n_0_[2] ),\n .I3(ref_bit[3]),\n .I4(\\ref_bit_reg_n_0_[0] ),\n .O(\\genblk9[4].fine_delay_incdec_pb[4]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk9[4].fine_delay_incdec_pb[4]_i_4 \n (.I0(\\genblk9[4].fine_delay_incdec_pb[4]_i_5_n_0 ),\n .I1(\\genblk8[4].left_loss_pb_reg__0 [3]),\n .I2(\\genblk8[4].right_gain_pb_reg__0 [3]),\n .I3(\\genblk8[4].left_loss_pb_reg__0 [4]),\n .I4(\\genblk8[4].right_gain_pb_reg__0 [4]),\n .O(\\genblk9[4].fine_delay_incdec_pb[4]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk9[4].fine_delay_incdec_pb[4]_i_5 \n (.I0(\\genblk8[4].right_gain_pb_reg_n_0_[24] ),\n .I1(\\genblk8[4].left_loss_pb_reg_n_0_[24] ),\n .I2(\\genblk8[4].left_loss_pb_reg_n_0_[25] ),\n .I3(\\genblk8[4].right_gain_pb_reg_n_0_[25] ),\n .I4(\\genblk8[4].left_loss_pb_reg__0 [2]),\n .I5(\\genblk8[4].right_gain_pb_reg__0 [2]),\n .O(\\genblk9[4].fine_delay_incdec_pb[4]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk9[4].fine_delay_incdec_pb_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk9[4].fine_delay_incdec_pb[4]_i_1_n_0 ),\n .Q(\\fine_delay_mod_reg[20] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000AAA8AAAA)) \n \\genblk9[5].fine_delay_incdec_pb[5]_i_1 \n (.I0(\\genblk9[5].fine_delay_incdec_pb[5]_i_2_n_0 ),\n .I1(\\genblk9[5].fine_delay_incdec_pb[5]_i_3_n_0 ),\n .I2(\\stage_cnt_reg_n_0_[0] ),\n .I3(\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ),\n .I4(bit_cnt),\n .I5(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .O(\\genblk9[5].fine_delay_incdec_pb[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFB2FFFFFFB20000)) \n \\genblk9[5].fine_delay_incdec_pb[5]_i_2 \n (.I0(\\genblk8[5].right_gain_pb_reg__0 [5]),\n .I1(\\genblk8[5].left_loss_pb_reg__0 [5]),\n .I2(\\genblk9[5].fine_delay_incdec_pb[5]_i_4_n_0 ),\n .I3(\\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ),\n .I4(\\stage_cnt_reg[1]_0 ),\n .I5(\\genblk9[5].fine_delay_incdec_pb_reg[5]_0 ),\n .O(\\genblk9[5].fine_delay_incdec_pb[5]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair38\" *) \n LUT5 #(\n .INIT(32'hFFFFFFBF)) \n \\genblk9[5].fine_delay_incdec_pb[5]_i_3 \n (.I0(\\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ),\n .I1(\\ref_bit_reg_n_0_[2] ),\n .I2(\\ref_bit_reg_n_0_[0] ),\n .I3(ref_bit[3]),\n .I4(\\ref_bit_reg_n_0_[1] ),\n .O(\\genblk9[5].fine_delay_incdec_pb[5]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk9[5].fine_delay_incdec_pb[5]_i_4 \n (.I0(\\genblk9[5].fine_delay_incdec_pb[5]_i_5_n_0 ),\n .I1(\\genblk8[5].left_loss_pb_reg__0 [3]),\n .I2(\\genblk8[5].right_gain_pb_reg__0 [3]),\n .I3(\\genblk8[5].left_loss_pb_reg__0 [4]),\n .I4(\\genblk8[5].right_gain_pb_reg__0 [4]),\n .O(\\genblk9[5].fine_delay_incdec_pb[5]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk9[5].fine_delay_incdec_pb[5]_i_5 \n (.I0(\\genblk8[5].right_gain_pb_reg_n_0_[30] ),\n .I1(\\genblk8[5].left_loss_pb_reg_n_0_[30] ),\n .I2(\\genblk8[5].left_loss_pb_reg_n_0_[31] ),\n .I3(\\genblk8[5].right_gain_pb_reg_n_0_[31] ),\n .I4(\\genblk8[5].left_loss_pb_reg__0 [2]),\n .I5(\\genblk8[5].right_gain_pb_reg__0 [2]),\n .O(\\genblk9[5].fine_delay_incdec_pb[5]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk9[5].fine_delay_incdec_pb_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk9[5].fine_delay_incdec_pb[5]_i_1_n_0 ),\n .Q(\\genblk9[5].fine_delay_incdec_pb_reg[5]_0 ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000AAAAAAA2)) \n \\genblk9[6].fine_delay_incdec_pb[6]_i_1 \n (.I0(\\genblk9[6].fine_delay_incdec_pb[6]_i_2_n_0 ),\n .I1(bit_cnt),\n .I2(\\genblk9[6].fine_delay_incdec_pb[6]_i_3_n_0 ),\n .I3(\\stage_cnt_reg_n_0_[0] ),\n .I4(\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ),\n .I5(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .O(\\genblk9[6].fine_delay_incdec_pb[6]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFB2FFFFFFB20000)) \n \\genblk9[6].fine_delay_incdec_pb[6]_i_2 \n (.I0(\\genblk8[6].right_gain_pb_reg__0 [5]),\n .I1(\\genblk8[6].left_loss_pb_reg__0 [5]),\n .I2(\\genblk9[6].fine_delay_incdec_pb[6]_i_4_n_0 ),\n .I3(\\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ),\n .I4(\\stage_cnt_reg[1]_0 ),\n .I5(\\genblk9[6].fine_delay_incdec_pb_reg[6]_0 ),\n .O(\\genblk9[6].fine_delay_incdec_pb[6]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair35\" *) \n LUT5 #(\n .INIT(32'hFFFFFFBF)) \n \\genblk9[6].fine_delay_incdec_pb[6]_i_3 \n (.I0(\\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ),\n .I1(\\ref_bit_reg_n_0_[2] ),\n .I2(\\ref_bit_reg_n_0_[1] ),\n .I3(ref_bit[3]),\n .I4(\\ref_bit_reg_n_0_[0] ),\n .O(\\genblk9[6].fine_delay_incdec_pb[6]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk9[6].fine_delay_incdec_pb[6]_i_4 \n (.I0(\\genblk9[6].fine_delay_incdec_pb[6]_i_5_n_0 ),\n .I1(\\genblk8[6].left_loss_pb_reg__0 [3]),\n .I2(\\genblk8[6].right_gain_pb_reg__0 [3]),\n .I3(\\genblk8[6].left_loss_pb_reg__0 [4]),\n .I4(\\genblk8[6].right_gain_pb_reg__0 [4]),\n .O(\\genblk9[6].fine_delay_incdec_pb[6]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk9[6].fine_delay_incdec_pb[6]_i_5 \n (.I0(\\genblk8[6].right_gain_pb_reg_n_0_[36] ),\n .I1(\\genblk8[6].left_loss_pb_reg_n_0_[36] ),\n .I2(\\genblk8[6].left_loss_pb_reg_n_0_[37] ),\n .I3(\\genblk8[6].right_gain_pb_reg_n_0_[37] ),\n .I4(\\genblk8[6].left_loss_pb_reg__0 [2]),\n .I5(\\genblk8[6].right_gain_pb_reg__0 [2]),\n .O(\\genblk9[6].fine_delay_incdec_pb[6]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk9[6].fine_delay_incdec_pb_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk9[6].fine_delay_incdec_pb[6]_i_1_n_0 ),\n .Q(\\genblk9[6].fine_delay_incdec_pb_reg[6]_0 ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000AAA8AAAA)) \n \\genblk9[7].fine_delay_incdec_pb[7]_i_1 \n (.I0(\\genblk9[7].fine_delay_incdec_pb[7]_i_2_n_0 ),\n .I1(\\genblk9[7].fine_delay_incdec_pb[7]_i_3_n_0 ),\n .I2(\\stage_cnt_reg_n_0_[0] ),\n .I3(\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ),\n .I4(bit_cnt),\n .I5(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .O(\\genblk9[7].fine_delay_incdec_pb[7]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFB2FFFFFFB20000)) \n \\genblk9[7].fine_delay_incdec_pb[7]_i_2 \n (.I0(\\genblk8[7].right_gain_pb_reg__0 [5]),\n .I1(\\genblk8[7].left_loss_pb_reg__0 [5]),\n .I2(\\genblk9[7].fine_delay_incdec_pb[7]_i_4_n_0 ),\n .I3(\\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ),\n .I4(\\stage_cnt_reg[1]_0 ),\n .I5(\\genblk9[7].fine_delay_incdec_pb_reg[7]_0 ),\n .O(\\genblk9[7].fine_delay_incdec_pb[7]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair38\" *) \n LUT5 #(\n .INIT(32'hFFBFFFFF)) \n \\genblk9[7].fine_delay_incdec_pb[7]_i_3 \n (.I0(\\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ),\n .I1(\\ref_bit_reg_n_0_[1] ),\n .I2(\\ref_bit_reg_n_0_[0] ),\n .I3(ref_bit[3]),\n .I4(\\ref_bit_reg_n_0_[2] ),\n .O(\\genblk9[7].fine_delay_incdec_pb[7]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk9[7].fine_delay_incdec_pb[7]_i_4 \n (.I0(\\genblk9[7].fine_delay_incdec_pb[7]_i_5_n_0 ),\n .I1(\\genblk8[7].left_loss_pb_reg__0 [3]),\n .I2(\\genblk8[7].right_gain_pb_reg__0 [3]),\n .I3(\\genblk8[7].left_loss_pb_reg__0 [4]),\n .I4(\\genblk8[7].right_gain_pb_reg__0 [4]),\n .O(\\genblk9[7].fine_delay_incdec_pb[7]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk9[7].fine_delay_incdec_pb[7]_i_5 \n (.I0(\\genblk8[7].right_gain_pb_reg_n_0_[42] ),\n .I1(\\genblk8[7].left_loss_pb_reg_n_0_[42] ),\n .I2(\\genblk8[7].left_loss_pb_reg_n_0_[43] ),\n .I3(\\genblk8[7].right_gain_pb_reg_n_0_[43] ),\n .I4(\\genblk8[7].left_loss_pb_reg__0 [2]),\n .I5(\\genblk8[7].right_gain_pb_reg__0 [2]),\n .O(\\genblk9[7].fine_delay_incdec_pb[7]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\genblk9[7].fine_delay_incdec_pb_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk9[7].fine_delay_incdec_pb[7]_i_1_n_0 ),\n .Q(\\genblk9[7].fine_delay_incdec_pb_reg[7]_0 ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair21\" *) \n LUT2 #(\n .INIT(4'h7)) \n \\init_state_r[0]_i_32 \n (.I0(complex_oclkdelay_calib_done_r1_reg),\n .I1(rdlvl_stg1_done_int_reg),\n .O(\\init_state_r_reg[0]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair21\" *) \n LUT5 #(\n .INIT(32'h000074FF)) \n \\init_state_r[0]_i_35 \n (.I0(complex_oclkdelay_calib_done_r1_reg),\n .I1(rdlvl_stg1_done_int_reg),\n .I2(wrcal_done_reg),\n .I3(dqs_found_done_r_reg),\n .I4(\\num_refresh_reg[1] ),\n .O(\\init_state_r_reg[0] ));\n LUT6 #(\n .INIT(64'h3F332F233F332020)) \n \\init_state_r[1]_i_32 \n (.I0(prbs_last_byte_done),\n .I1(complex_oclkdelay_calib_done_r1_reg),\n .I2(rdlvl_stg1_done_int_reg),\n .I3(rdlvl_stg1_start_int),\n .I4(rdlvl_last_byte_done),\n .I5(\\one_rank.stg1_wr_done_reg ),\n .O(\\init_state_r_reg[1]_0 ));\n LUT6 #(\n .INIT(64'hF0FF808080808080)) \n \\init_state_r[1]_i_45 \n (.I0(complex_oclkdelay_calib_done_r1_reg),\n .I1(oclkdelay_center_calib_done_r_reg),\n .I2(rdlvl_stg1_done_int_reg),\n .I3(wrcal_done_reg),\n .I4(dqs_found_done_r_reg),\n .I5(wrlvl_final_mux),\n .O(\\init_state_r_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair75\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\largest_left_edge[0]_i_1 \n (.I0(Q[2]),\n .I1(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .O(\\largest_left_edge[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair75\" *) \n LUT3 #(\n .INIT(8'h28)) \n \\largest_left_edge[1]_i_1 \n (.I0(Q[2]),\n .I1(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .O(\\largest_left_edge[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair30\" *) \n LUT4 #(\n .INIT(16'h2888)) \n \\largest_left_edge[2]_i_1 \n (.I0(Q[2]),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .O(\\largest_left_edge[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair30\" *) \n LUT5 #(\n .INIT(32'h82222222)) \n \\largest_left_edge[3]_i_1 \n (.I0(Q[2]),\n .I1(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\largest_left_edge[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8888888882222222)) \n \\largest_left_edge[4]_i_1 \n (.I0(Q[2]),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\largest_left_edge[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00002F0000000000)) \n \\largest_left_edge[5]_i_1 \n (.I0(ref_bit_per_bit0),\n .I1(\\largest_left_edge_reg[0]_0 ),\n .I2(Q[2]),\n .I3(Q[3]),\n .I4(Q[4]),\n .I5(\\largest_left_edge[5]_i_4_n_0 ),\n .O(\\largest_left_edge[5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair72\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\largest_left_edge[5]_i_2 \n (.I0(Q[2]),\n .I1(\\largest_left_edge[5]_i_5_n_0 ),\n .O(\\largest_left_edge[5]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFEFFFF)) \n \\largest_left_edge[5]_i_3 \n (.I0(D[0]),\n .I1(D[1]),\n .I2(D[2]),\n .I3(D[3]),\n .I4(\\largest_left_edge[5]_i_6_n_0 ),\n .O(ref_bit_per_bit0));\n (* SOFT_HLUTNM = \"soft_lutpair25\" *) \n LUT3 #(\n .INIT(8'h81)) \n \\largest_left_edge[5]_i_4 \n (.I0(Q[0]),\n .I1(Q[2]),\n .I2(Q[1]),\n .O(\\largest_left_edge[5]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h00001555FFFFEAAA)) \n \\largest_left_edge[5]_i_5 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\largest_left_edge[5]_i_5_n_0 ));\n LUT4 #(\n .INIT(16'h0001)) \n \\largest_left_edge[5]_i_6 \n (.I0(D[6]),\n .I1(D[7]),\n .I2(D[5]),\n .I3(D[4]),\n .O(\\largest_left_edge[5]_i_6_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\largest_left_edge_reg[0] \n (.C(CLK),\n .CE(\\largest_left_edge[5]_i_1_n_0 ),\n .D(\\largest_left_edge[0]_i_1_n_0 ),\n .Q(\\largest_left_edge_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE #(\n .INIT(1'b0)) \n \\largest_left_edge_reg[1] \n (.C(CLK),\n .CE(\\largest_left_edge[5]_i_1_n_0 ),\n .D(\\largest_left_edge[1]_i_1_n_0 ),\n .Q(\\largest_left_edge_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE #(\n .INIT(1'b0)) \n \\largest_left_edge_reg[2] \n (.C(CLK),\n .CE(\\largest_left_edge[5]_i_1_n_0 ),\n .D(\\largest_left_edge[2]_i_1_n_0 ),\n .Q(\\largest_left_edge_reg_n_0_[2] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE #(\n .INIT(1'b0)) \n \\largest_left_edge_reg[3] \n (.C(CLK),\n .CE(\\largest_left_edge[5]_i_1_n_0 ),\n .D(\\largest_left_edge[3]_i_1_n_0 ),\n .Q(\\largest_left_edge_reg_n_0_[3] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE #(\n .INIT(1'b0)) \n \\largest_left_edge_reg[4] \n (.C(CLK),\n .CE(\\largest_left_edge[5]_i_1_n_0 ),\n .D(\\largest_left_edge[4]_i_1_n_0 ),\n .Q(\\largest_left_edge_reg_n_0_[4] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE #(\n .INIT(1'b0)) \n \\largest_left_edge_reg[5] \n (.C(CLK),\n .CE(\\largest_left_edge[5]_i_1_n_0 ),\n .D(\\largest_left_edge[5]_i_2_n_0 ),\n .Q(\\largest_left_edge_reg_n_0_[5] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n LUT3 #(\n .INIT(8'hB8)) \n \\left_edge_ref[0]_i_1 \n (.I0(\\left_edge_ref[2]_i_2_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_7 ),\n .I2(\\left_edge_ref[0]_i_2_n_0 ),\n .O(\\left_edge_ref[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\left_edge_ref[0]_i_2 \n (.I0(\\left_edge_ref_reg[4]_i_10_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_6 ),\n .I2(\\left_edge_ref[4]_i_9_n_0 ),\n .I3(\\left_edge_ref_reg[5]_i_3_n_5 ),\n .I4(\\left_edge_ref[0]_i_3_n_0 ),\n .O(\\left_edge_ref[0]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair16\" *) \n LUT5 #(\n .INIT(32'h30BB3088)) \n \\left_edge_ref[0]_i_3 \n (.I0(\\genblk8[2].left_edge_pb_reg_n_0_[16] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].left_edge_pb_reg_n_0_[32] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].left_edge_pb_reg_n_0_[0] ),\n .O(\\left_edge_ref[0]_i_3_n_0 ));\n LUT3 #(\n .INIT(8'hB8)) \n \\left_edge_ref[1]_i_1 \n (.I0(\\left_edge_ref[3]_i_2_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_7 ),\n .I2(\\left_edge_ref[1]_i_2_n_0 ),\n .O(\\left_edge_ref[1]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\left_edge_ref[1]_i_2 \n (.I0(\\left_edge_ref_reg[5]_i_16_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_6 ),\n .I2(\\left_edge_ref[5]_i_15_n_0 ),\n .I3(\\left_edge_ref_reg[5]_i_3_n_5 ),\n .I4(\\left_edge_ref[1]_i_3_n_0 ),\n .O(\\left_edge_ref[1]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair26\" *) \n LUT5 #(\n .INIT(32'h30BB3088)) \n \\left_edge_ref[1]_i_3 \n (.I0(\\genblk8[2].left_edge_pb_reg_n_0_[17] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].left_edge_pb_reg_n_0_[33] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].left_edge_pb_reg_n_0_[1] ),\n .O(\\left_edge_ref[1]_i_3_n_0 ));\n LUT3 #(\n .INIT(8'hB8)) \n \\left_edge_ref[2]_i_1 \n (.I0(\\left_edge_ref[4]_i_4_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_7 ),\n .I2(\\left_edge_ref[2]_i_2_n_0 ),\n .O(\\left_edge_ref[2]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\left_edge_ref[2]_i_2 \n (.I0(\\left_edge_ref_reg[4]_i_3_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_6 ),\n .I2(\\left_edge_ref[4]_i_5_n_0 ),\n .I3(\\left_edge_ref_reg[5]_i_3_n_5 ),\n .I4(\\left_edge_ref[2]_i_3_n_0 ),\n .O(\\left_edge_ref[2]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\left_edge_ref[2]_i_3 \n (.I0(\\genblk8[3].left_edge_pb_reg_n_0_[18] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].left_edge_pb_reg_n_0_[34] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].left_edge_pb_reg_n_0_[2] ),\n .O(\\left_edge_ref[2]_i_3_n_0 ));\n LUT3 #(\n .INIT(8'hB8)) \n \\left_edge_ref[3]_i_1 \n (.I0(\\left_edge_ref[5]_i_5_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_7 ),\n .I2(\\left_edge_ref[3]_i_2_n_0 ),\n .O(\\left_edge_ref[3]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\left_edge_ref[3]_i_2 \n (.I0(\\left_edge_ref_reg[5]_i_4_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_6 ),\n .I2(\\left_edge_ref[5]_i_7_n_0 ),\n .I3(\\left_edge_ref_reg[5]_i_3_n_5 ),\n .I4(\\left_edge_ref[3]_i_3_n_0 ),\n .O(\\left_edge_ref[3]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\left_edge_ref[3]_i_3 \n (.I0(\\genblk8[3].left_edge_pb_reg_n_0_[19] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].left_edge_pb_reg_n_0_[35] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].left_edge_pb_reg_n_0_[3] ),\n .O(\\left_edge_ref[3]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\left_edge_ref[4]_i_1 \n (.I0(\\left_edge_ref[4]_i_2_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_6 ),\n .I2(\\left_edge_ref_reg[4]_i_3_n_0 ),\n .I3(\\left_edge_ref_reg[5]_i_3_n_7 ),\n .I4(\\left_edge_ref[4]_i_4_n_0 ),\n .O(\\left_edge_ref[4]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\left_edge_ref[4]_i_11 \n (.I0(\\genblk8[3].left_edge_pb_reg_n_0_[20] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].left_edge_pb_reg_n_0_[36] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].left_edge_pb_reg_n_0_[4] ),\n .O(\\left_edge_ref[4]_i_11_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\left_edge_ref[4]_i_12 \n (.I0(\\genblk8[4].left_edge_pb_reg_n_0_[28] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].left_edge_pb_reg_n_0_[44] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[2].left_edge_pb_reg_n_0_[12] ),\n .O(\\left_edge_ref[4]_i_12_n_0 ));\n LUT6 #(\n .INIT(64'h00E2FFFF00E20000)) \n \\left_edge_ref[4]_i_2 \n (.I0(\\genblk8[3].left_edge_pb_reg_n_0_[18] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].left_edge_pb_reg_n_0_[34] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\left_edge_ref_reg[5]_i_3_n_5 ),\n .I5(\\left_edge_ref[4]_i_5_n_0 ),\n .O(\\left_edge_ref[4]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\left_edge_ref[4]_i_4 \n (.I0(\\left_edge_ref[4]_i_8_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_5 ),\n .I2(\\left_edge_ref[4]_i_9_n_0 ),\n .I3(\\left_edge_ref_reg[5]_i_3_n_6 ),\n .I4(\\left_edge_ref_reg[4]_i_10_n_0 ),\n .O(\\left_edge_ref[4]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\left_edge_ref[4]_i_5 \n (.I0(\\genblk8[4].left_edge_pb_reg_n_0_[26] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].left_edge_pb_reg_n_0_[42] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].left_edge_pb_reg_n_0_[10] ),\n .O(\\left_edge_ref[4]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\left_edge_ref[4]_i_6 \n (.I0(\\genblk8[3].left_edge_pb_reg_n_0_[22] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].left_edge_pb_reg_n_0_[38] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].left_edge_pb_reg_n_0_[6] ),\n .O(\\left_edge_ref[4]_i_6_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\left_edge_ref[4]_i_7 \n (.I0(\\genblk8[5].left_edge_pb_reg_n_0_[30] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].left_edge_pb_reg_n_0_[46] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[2].left_edge_pb_reg_n_0_[14] ),\n .O(\\left_edge_ref[4]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair16\" *) \n LUT4 #(\n .INIT(16'h00E2)) \n \\left_edge_ref[4]_i_8 \n (.I0(\\genblk8[2].left_edge_pb_reg_n_0_[16] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].left_edge_pb_reg_n_0_[32] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .O(\\left_edge_ref[4]_i_8_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\left_edge_ref[4]_i_9 \n (.I0(\\genblk8[4].left_edge_pb_reg_n_0_[24] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].left_edge_pb_reg_n_0_[40] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].left_edge_pb_reg_n_0_[8] ),\n .O(\\left_edge_ref[4]_i_9_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\left_edge_ref[5]_i_1 \n (.I0(\\left_edge_ref[5]_i_2_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_6 ),\n .I2(\\left_edge_ref_reg[5]_i_4_n_0 ),\n .I3(\\left_edge_ref_reg[5]_i_3_n_7 ),\n .I4(\\left_edge_ref[5]_i_5_n_0 ),\n .O(\\left_edge_ref[5]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\left_edge_ref[5]_i_10 \n (.I0(\\ref_bit_reg_n_0_[1] ),\n .O(\\left_edge_ref[5]_i_10_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\left_edge_ref[5]_i_11 \n (.I0(\\ref_bit_reg_n_0_[0] ),\n .O(\\left_edge_ref[5]_i_11_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\left_edge_ref[5]_i_12 \n (.I0(\\genblk8[3].left_edge_pb_reg_n_0_[23] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].left_edge_pb_reg_n_0_[39] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].left_edge_pb_reg_n_0_[7] ),\n .O(\\left_edge_ref[5]_i_12_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\left_edge_ref[5]_i_13 \n (.I0(\\genblk8[5].left_edge_pb_reg_n_0_[31] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].left_edge_pb_reg_n_0_[47] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[2].left_edge_pb_reg_n_0_[15] ),\n .O(\\left_edge_ref[5]_i_13_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair26\" *) \n LUT4 #(\n .INIT(16'h00E2)) \n \\left_edge_ref[5]_i_14 \n (.I0(\\genblk8[2].left_edge_pb_reg_n_0_[17] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].left_edge_pb_reg_n_0_[33] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .O(\\left_edge_ref[5]_i_14_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\left_edge_ref[5]_i_15 \n (.I0(\\genblk8[4].left_edge_pb_reg_n_0_[25] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].left_edge_pb_reg_n_0_[41] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].left_edge_pb_reg_n_0_[9] ),\n .O(\\left_edge_ref[5]_i_15_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\left_edge_ref[5]_i_17 \n (.I0(\\ref_bit_reg_n_0_[2] ),\n .I1(ref_bit[4]),\n .O(\\left_edge_ref[5]_i_17_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\left_edge_ref[5]_i_18 \n (.I0(\\genblk8[3].left_edge_pb_reg_n_0_[21] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].left_edge_pb_reg_n_0_[37] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].left_edge_pb_reg_n_0_[5] ),\n .O(\\left_edge_ref[5]_i_18_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\left_edge_ref[5]_i_19 \n (.I0(\\genblk8[4].left_edge_pb_reg_n_0_[29] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].left_edge_pb_reg_n_0_[45] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[2].left_edge_pb_reg_n_0_[13] ),\n .O(\\left_edge_ref[5]_i_19_n_0 ));\n LUT6 #(\n .INIT(64'h00E2FFFF00E20000)) \n \\left_edge_ref[5]_i_2 \n (.I0(\\genblk8[3].left_edge_pb_reg_n_0_[19] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].left_edge_pb_reg_n_0_[35] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\left_edge_ref_reg[5]_i_3_n_5 ),\n .I5(\\left_edge_ref[5]_i_7_n_0 ),\n .O(\\left_edge_ref[5]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\left_edge_ref[5]_i_5 \n (.I0(\\left_edge_ref[5]_i_14_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_5 ),\n .I2(\\left_edge_ref[5]_i_15_n_0 ),\n .I3(\\left_edge_ref_reg[5]_i_3_n_6 ),\n .I4(\\left_edge_ref_reg[5]_i_16_n_0 ),\n .O(\\left_edge_ref[5]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\left_edge_ref[5]_i_7 \n (.I0(\\genblk8[4].left_edge_pb_reg_n_0_[27] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].left_edge_pb_reg_n_0_[43] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].left_edge_pb_reg_n_0_[11] ),\n .O(\\left_edge_ref[5]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\left_edge_ref[5]_i_8 \n (.I0(\\ref_bit_reg_n_0_[1] ),\n .I1(ref_bit[3]),\n .O(\\left_edge_ref[5]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\left_edge_ref[5]_i_9 \n (.I0(\\ref_bit_reg_n_0_[0] ),\n .I1(\\ref_bit_reg_n_0_[2] ),\n .O(\\left_edge_ref[5]_i_9_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\left_edge_ref_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\left_edge_ref[0]_i_1_n_0 ),\n .Q(left_edge_ref[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\left_edge_ref_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\left_edge_ref[1]_i_1_n_0 ),\n .Q(left_edge_ref[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\left_edge_ref_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\left_edge_ref[2]_i_1_n_0 ),\n .Q(left_edge_ref[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\left_edge_ref_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\left_edge_ref[3]_i_1_n_0 ),\n .Q(left_edge_ref[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\left_edge_ref_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\left_edge_ref[4]_i_1_n_0 ),\n .Q(left_edge_ref[4]),\n .R(1'b0));\n MUXF7 \\left_edge_ref_reg[4]_i_10 \n (.I0(\\left_edge_ref[4]_i_11_n_0 ),\n .I1(\\left_edge_ref[4]_i_12_n_0 ),\n .O(\\left_edge_ref_reg[4]_i_10_n_0 ),\n .S(\\left_edge_ref_reg[5]_i_3_n_5 ));\n MUXF7 \\left_edge_ref_reg[4]_i_3 \n (.I0(\\left_edge_ref[4]_i_6_n_0 ),\n .I1(\\left_edge_ref[4]_i_7_n_0 ),\n .O(\\left_edge_ref_reg[4]_i_3_n_0 ),\n .S(\\left_edge_ref_reg[5]_i_3_n_5 ));\n FDRE #(\n .INIT(1'b0)) \n \\left_edge_ref_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\left_edge_ref[5]_i_1_n_0 ),\n .Q(left_edge_ref[5]),\n .R(1'b0));\n MUXF7 \\left_edge_ref_reg[5]_i_16 \n (.I0(\\left_edge_ref[5]_i_18_n_0 ),\n .I1(\\left_edge_ref[5]_i_19_n_0 ),\n .O(\\left_edge_ref_reg[5]_i_16_n_0 ),\n .S(\\left_edge_ref_reg[5]_i_3_n_5 ));\n CARRY4 \\left_edge_ref_reg[5]_i_3 \n (.CI(1'b0),\n .CO({\\left_edge_ref_reg[5]_i_3_n_0 ,\\left_edge_ref_reg[5]_i_3_n_1 ,\\left_edge_ref_reg[5]_i_3_n_2 ,\\left_edge_ref_reg[5]_i_3_n_3 }),\n .CYINIT(1'b0),\n .DI({\\ref_bit_reg_n_0_[1] ,\\ref_bit_reg_n_0_[0] ,1'b0,1'b1}),\n .O({\\left_edge_ref_reg[5]_i_3_n_4 ,\\left_edge_ref_reg[5]_i_3_n_5 ,\\left_edge_ref_reg[5]_i_3_n_6 ,\\left_edge_ref_reg[5]_i_3_n_7 }),\n .S({\\left_edge_ref[5]_i_8_n_0 ,\\left_edge_ref[5]_i_9_n_0 ,\\left_edge_ref[5]_i_10_n_0 ,\\left_edge_ref[5]_i_11_n_0 }));\n MUXF7 \\left_edge_ref_reg[5]_i_4 \n (.I0(\\left_edge_ref[5]_i_12_n_0 ),\n .I1(\\left_edge_ref[5]_i_13_n_0 ),\n .O(\\left_edge_ref_reg[5]_i_4_n_0 ),\n .S(\\left_edge_ref_reg[5]_i_3_n_5 ));\n CARRY4 \\left_edge_ref_reg[5]_i_6 \n (.CI(\\left_edge_ref_reg[5]_i_3_n_0 ),\n .CO(\\NLW_left_edge_ref_reg[5]_i_6_CO_UNCONNECTED [3:0]),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\NLW_left_edge_ref_reg[5]_i_6_O_UNCONNECTED [3:1],\\left_edge_ref_reg[5]_i_6_n_7 }),\n .S({1'b0,1'b0,1'b0,\\left_edge_ref[5]_i_17_n_0 }));\n LUT5 #(\n .INIT(32'hEEE2FFFF)) \n \\match_flag_and[0]_i_1 \n (.I0(compare_err_pb_and_reg_n_0),\n .I1(Q[1]),\n .I2(num_samples_done_r),\n .I3(\\match_flag_or_reg[0]_0 ),\n .I4(Q[4]),\n .O(\\match_flag_and[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hEEE2FFFF)) \n \\match_flag_and[1]_i_1 \n (.I0(\\match_flag_and_reg_n_0_[0] ),\n .I1(Q[1]),\n .I2(num_samples_done_r),\n .I3(\\match_flag_or_reg[0]_0 ),\n .I4(Q[4]),\n .O(\\match_flag_and[1]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hEEE2FFFF)) \n \\match_flag_and[2]_i_1 \n (.I0(\\match_flag_and_reg_n_0_[1] ),\n .I1(Q[1]),\n .I2(num_samples_done_r),\n .I3(\\match_flag_or_reg[0]_0 ),\n .I4(Q[4]),\n .O(\\match_flag_and[2]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hEEE2FFFF)) \n \\match_flag_and[3]_i_1 \n (.I0(\\match_flag_and_reg_n_0_[2] ),\n .I1(Q[1]),\n .I2(num_samples_done_r),\n .I3(\\match_flag_or_reg[0]_0 ),\n .I4(Q[4]),\n .O(\\match_flag_and[3]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hEEE2FFFF)) \n \\match_flag_and[4]_i_1 \n (.I0(\\match_flag_and_reg_n_0_[3] ),\n .I1(Q[1]),\n .I2(num_samples_done_r),\n .I3(\\match_flag_or_reg[0]_0 ),\n .I4(Q[4]),\n .O(\\match_flag_and[4]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hEEE2FFFF)) \n \\match_flag_and[5]_i_1 \n (.I0(\\match_flag_and_reg_n_0_[4] ),\n .I1(Q[1]),\n .I2(num_samples_done_r),\n .I3(\\match_flag_or_reg[0]_0 ),\n .I4(Q[4]),\n .O(\\match_flag_and[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hEEE2FFFF)) \n \\match_flag_and[6]_i_1 \n (.I0(\\match_flag_and_reg_n_0_[5] ),\n .I1(Q[1]),\n .I2(num_samples_done_r),\n .I3(\\match_flag_or_reg[0]_0 ),\n .I4(Q[4]),\n .O(\\match_flag_and[6]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00A2FFFF00A20000)) \n \\match_flag_and[7]_i_1 \n (.I0(\\match_flag_and[7]_i_3_n_0 ),\n .I1(Q[4]),\n .I2(num_samples_done_r),\n .I3(Q[2]),\n .I4(Q[0]),\n .I5(no_err_win_detected_reg_0),\n .O(match_flag_and));\n LUT5 #(\n .INIT(32'hEEE2FFFF)) \n \\match_flag_and[7]_i_2 \n (.I0(\\match_flag_and_reg_n_0_[6] ),\n .I1(Q[1]),\n .I2(num_samples_done_r),\n .I3(\\match_flag_or_reg[0]_0 ),\n .I4(Q[4]),\n .O(\\match_flag_and[7]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair27\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\match_flag_and[7]_i_3 \n (.I0(Q[1]),\n .I1(Q[3]),\n .O(\\match_flag_and[7]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0000444000000000)) \n \\match_flag_and[7]_i_4 \n (.I0(Q[3]),\n .I1(Q[1]),\n .I2(num_samples_done_r),\n .I3(\\match_flag_or_reg[0]_0 ),\n .I4(Q[2]),\n .I5(Q[4]),\n .O(no_err_win_detected_reg_0));\n FDSE #(\n .INIT(1'b1)) \n \\match_flag_and_reg[0] \n (.C(CLK),\n .CE(match_flag_and),\n .D(\\match_flag_and[0]_i_1_n_0 ),\n .Q(\\match_flag_and_reg_n_0_[0] ),\n .S(rstdiv0_sync_r1_reg_rep__8));\n FDSE #(\n .INIT(1'b1)) \n \\match_flag_and_reg[1] \n (.C(CLK),\n .CE(match_flag_and),\n .D(\\match_flag_and[1]_i_1_n_0 ),\n .Q(\\match_flag_and_reg_n_0_[1] ),\n .S(rstdiv0_sync_r1_reg_rep__8));\n FDSE #(\n .INIT(1'b1)) \n \\match_flag_and_reg[2] \n (.C(CLK),\n .CE(match_flag_and),\n .D(\\match_flag_and[2]_i_1_n_0 ),\n .Q(\\match_flag_and_reg_n_0_[2] ),\n .S(rstdiv0_sync_r1_reg_rep__8));\n FDSE #(\n .INIT(1'b1)) \n \\match_flag_and_reg[3] \n (.C(CLK),\n .CE(match_flag_and),\n .D(\\match_flag_and[3]_i_1_n_0 ),\n .Q(\\match_flag_and_reg_n_0_[3] ),\n .S(rstdiv0_sync_r1_reg_rep__8));\n FDSE #(\n .INIT(1'b1)) \n \\match_flag_and_reg[4] \n (.C(CLK),\n .CE(match_flag_and),\n .D(\\match_flag_and[4]_i_1_n_0 ),\n .Q(\\match_flag_and_reg_n_0_[4] ),\n .S(rstdiv0_sync_r1_reg_rep__8));\n FDSE #(\n .INIT(1'b1)) \n \\match_flag_and_reg[5] \n (.C(CLK),\n .CE(match_flag_and),\n .D(\\match_flag_and[5]_i_1_n_0 ),\n .Q(\\match_flag_and_reg_n_0_[5] ),\n .S(rstdiv0_sync_r1_reg_rep__8));\n FDSE #(\n .INIT(1'b1)) \n \\match_flag_and_reg[6] \n (.C(CLK),\n .CE(match_flag_and),\n .D(\\match_flag_and[6]_i_1_n_0 ),\n .Q(\\match_flag_and_reg_n_0_[6] ),\n .S(rstdiv0_sync_r1_reg_rep__8));\n FDSE #(\n .INIT(1'b1)) \n \\match_flag_and_reg[7] \n (.C(CLK),\n .CE(match_flag_and),\n .D(\\match_flag_and[7]_i_2_n_0 ),\n .Q(\\match_flag_and_reg_n_0_[7] ),\n .S(rstdiv0_sync_r1_reg_rep__8));\n LUT5 #(\n .INIT(32'hEEE2FFFF)) \n \\match_flag_or[0]_i_1 \n (.I0(sel0[0]),\n .I1(Q[1]),\n .I2(num_samples_done_r),\n .I3(\\match_flag_or_reg[0]_0 ),\n .I4(Q[4]),\n .O(\\match_flag_or[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hEEE2FFFF)) \n \\match_flag_or[1]_i_1 \n (.I0(sel0[1]),\n .I1(Q[1]),\n .I2(num_samples_done_r),\n .I3(\\match_flag_or_reg[0]_0 ),\n .I4(Q[4]),\n .O(\\match_flag_or[1]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hEEE2FFFF)) \n \\match_flag_or[2]_i_1 \n (.I0(sel0[2]),\n .I1(Q[1]),\n .I2(num_samples_done_r),\n .I3(\\match_flag_or_reg[0]_0 ),\n .I4(Q[4]),\n .O(\\match_flag_or[2]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hEEE2FFFF)) \n \\match_flag_or[3]_i_1 \n (.I0(sel0[3]),\n .I1(Q[1]),\n .I2(num_samples_done_r),\n .I3(\\match_flag_or_reg[0]_0 ),\n .I4(Q[4]),\n .O(\\match_flag_or[3]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hEEE2FFFF)) \n \\match_flag_or[4]_i_1 \n (.I0(sel0[4]),\n .I1(Q[1]),\n .I2(num_samples_done_r),\n .I3(\\match_flag_or_reg[0]_0 ),\n .I4(Q[4]),\n .O(\\match_flag_or[4]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hEEE2FFFF)) \n \\match_flag_or[5]_i_1 \n (.I0(sel0[5]),\n .I1(Q[1]),\n .I2(num_samples_done_r),\n .I3(\\match_flag_or_reg[0]_0 ),\n .I4(Q[4]),\n .O(\\match_flag_or[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hEEE2FFFF)) \n \\match_flag_or[6]_i_1 \n (.I0(sel0[6]),\n .I1(Q[1]),\n .I2(num_samples_done_r),\n .I3(\\match_flag_or_reg[0]_0 ),\n .I4(Q[4]),\n .O(\\match_flag_or[6]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\match_flag_or_reg[0] \n (.C(CLK),\n .CE(match_flag_and),\n .D(\\match_flag_or[0]_i_1_n_0 ),\n .Q(sel0[1]),\n .S(rstdiv0_sync_r1_reg_rep__9));\n FDSE #(\n .INIT(1'b1)) \n \\match_flag_or_reg[1] \n (.C(CLK),\n .CE(match_flag_and),\n .D(\\match_flag_or[1]_i_1_n_0 ),\n .Q(sel0[2]),\n .S(rstdiv0_sync_r1_reg_rep__9));\n FDSE #(\n .INIT(1'b1)) \n \\match_flag_or_reg[2] \n (.C(CLK),\n .CE(match_flag_and),\n .D(\\match_flag_or[2]_i_1_n_0 ),\n .Q(sel0[3]),\n .S(rstdiv0_sync_r1_reg_rep__9));\n FDSE #(\n .INIT(1'b1)) \n \\match_flag_or_reg[3] \n (.C(CLK),\n .CE(match_flag_and),\n .D(\\match_flag_or[3]_i_1_n_0 ),\n .Q(sel0[4]),\n .S(rstdiv0_sync_r1_reg_rep__9));\n FDSE #(\n .INIT(1'b1)) \n \\match_flag_or_reg[4] \n (.C(CLK),\n .CE(match_flag_and),\n .D(\\match_flag_or[4]_i_1_n_0 ),\n .Q(sel0[5]),\n .S(rstdiv0_sync_r1_reg_rep__9));\n FDSE #(\n .INIT(1'b1)) \n \\match_flag_or_reg[5] \n (.C(CLK),\n .CE(match_flag_and),\n .D(\\match_flag_or[5]_i_1_n_0 ),\n .Q(sel0[6]),\n .S(rstdiv0_sync_r1_reg_rep__9));\n FDSE #(\n .INIT(1'b1)) \n \\match_flag_or_reg[6] \n (.C(CLK),\n .CE(match_flag_and),\n .D(\\match_flag_or[6]_i_1_n_0 ),\n .Q(sel0[7]),\n .S(rstdiv0_sync_r1_reg_rep__9));\n FDRE #(\n .INIT(1'b0)) \n mux_rd_valid_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .Q(mux_rd_valid_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h88888B88)) \n new_cnt_dqs_r_i_2\n (.I0(prech_done),\n .I1(Q[3]),\n .I2(prbs_rdlvl_start_r),\n .I3(prbs_rdlvl_start_reg),\n .I4(Q[0]),\n .O(new_cnt_dqs_r));\n LUT6 #(\n .INIT(64'h0030BBBB00308888)) \n new_cnt_dqs_r_i_3\n (.I0(cnt_wait_state),\n .I1(Q[0]),\n .I2(prech_done),\n .I3(prbs_last_byte_done_reg_0),\n .I4(Q[3]),\n .I5(prbs_rdlvl_start_reg_0),\n .O(new_cnt_dqs_r_reg_0));\n FDRE #(\n .INIT(1'b0)) \n new_cnt_dqs_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\prbs_state_r_reg[4]_0 ),\n .Q(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n (* SOFT_HLUTNM = \"soft_lutpair67\" *) \n LUT4 #(\n .INIT(16'h0100)) \n no_err_win_detected_i_1\n (.I0(Q[1]),\n .I1(no_err_win_detected_i_2_n_0),\n .I2(no_err_win_detected_i_3_n_0),\n .I3(Q[4]),\n .O(no_err_win_detected_i_1_n_0));\n LUT4 #(\n .INIT(16'hFFFE)) \n no_err_win_detected_i_2\n (.I0(sel0[7]),\n .I1(sel0[6]),\n .I2(sel0[4]),\n .I3(sel0[5]),\n .O(no_err_win_detected_i_2_n_0));\n LUT4 #(\n .INIT(16'hFFFE)) \n no_err_win_detected_i_3\n (.I0(sel0[2]),\n .I1(sel0[3]),\n .I2(sel0[0]),\n .I3(sel0[1]),\n .O(no_err_win_detected_i_3_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair48\" *) \n LUT5 #(\n .INIT(32'h20000003)) \n no_err_win_detected_latch_i_2\n (.I0(no_err_win_detected_latch_reg_0),\n .I1(Q[4]),\n .I2(Q[2]),\n .I3(Q[3]),\n .I4(Q[1]),\n .O(no_err_win_detected_latch_reg_1));\n FDRE #(\n .INIT(1'b0)) \n no_err_win_detected_latch_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\prbs_state_r_reg[3]_1 ),\n .Q(\\largest_left_edge_reg[0]_0 ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE #(\n .INIT(1'b0)) \n no_err_win_detected_reg\n (.C(CLK),\n .CE(match_flag_and),\n .D(no_err_win_detected_i_1_n_0),\n .Q(no_err_win_detected_latch_reg_0),\n .R(SR));\n (* SOFT_HLUTNM = \"soft_lutpair51\" *) \n LUT2 #(\n .INIT(4'hE)) \n num_samples_done_ind_i_2\n (.I0(Q[2]),\n .I1(Q[3]),\n .O(num_samples_done_ind_reg_0));\n FDRE #(\n .INIT(1'b0)) \n num_samples_done_ind_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\prbs_state_r_reg[4]_1 ),\n .Q(\\match_flag_or_reg[0]_0 ),\n .R(rstdiv0_sync_r1_reg_rep__7));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\oclkdelay_ref_cnt[0]_i_3 \n (.I0(\\stg1_wr_rd_cnt_reg[3] ),\n .I1(rstdiv0_sync_r1_reg_rep__23),\n .I2(oclkdelay_center_calib_done_r_reg),\n .I3(ocal_last_byte_done),\n .O(\\oclkdelay_ref_cnt_reg[0] ));\n FDRE #(\n .INIT(1'b0)) \n pi_en_stg2_f_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_en_stg2_f_timing),\n .Q(prbs_pi_stg2_f_en),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n pi_en_stg2_f_timing_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_en_stg2_f_timing_reg_0),\n .Q(pi_en_stg2_f_timing),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE #(\n .INIT(1'b0)) \n pi_stg2_f_incdec_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_stg2_f_incdec_timing),\n .Q(prbs_pi_stg2_f_incdec),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n pi_stg2_f_incdec_timing_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prbs_tap_inc_r_reg_0),\n .Q(pi_stg2_f_incdec_timing),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair73\" *) \n LUT3 #(\n .INIT(8'h47)) \n \\prbs_dec_tap_cnt[0]_i_1 \n (.I0(\\prbs_dec_tap_cnt_reg[1]_0 [0]),\n .I1(Q[2]),\n .I2(prbs_dec_tap_cnt[0]),\n .O(\\prbs_dec_tap_cnt[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h1AFF1A001A001AFF)) \n \\prbs_dec_tap_cnt[1]_i_1 \n (.I0(dec_cnt_reg[1]),\n .I1(\\prbs_dec_tap_cnt_reg[1]_0 [1]),\n .I2(\\prbs_dec_tap_cnt_reg[1]_0 [0]),\n .I3(Q[2]),\n .I4(prbs_dec_tap_cnt[0]),\n .I5(prbs_dec_tap_cnt[1]),\n .O(\\prbs_dec_tap_cnt[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h060006FF06FF0600)) \n \\prbs_dec_tap_cnt[2]_i_1 \n (.I0(dec_cnt_reg[2]),\n .I1(\\prbs_dec_tap_cnt[2]_i_2_n_0 ),\n .I2(\\prbs_dec_tap_cnt[2]_i_3_n_0 ),\n .I3(Q[2]),\n .I4(\\prbs_dec_tap_cnt[2]_i_4_n_0 ),\n .I5(prbs_dec_tap_cnt[2]),\n .O(\\prbs_dec_tap_cnt[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair73\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\prbs_dec_tap_cnt[2]_i_2 \n (.I0(dec_cnt_reg[1]),\n .I1(\\prbs_dec_tap_cnt_reg[1]_0 [0]),\n .O(\\prbs_dec_tap_cnt[2]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair49\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\prbs_dec_tap_cnt[2]_i_3 \n (.I0(\\prbs_dec_tap_cnt_reg[1]_0 [0]),\n .I1(\\prbs_dec_tap_cnt_reg[1]_0 [1]),\n .O(\\prbs_dec_tap_cnt[2]_i_3_n_0 ));\n LUT2 #(\n .INIT(4'h1)) \n \\prbs_dec_tap_cnt[2]_i_4 \n (.I0(prbs_dec_tap_cnt[0]),\n .I1(prbs_dec_tap_cnt[1]),\n .O(\\prbs_dec_tap_cnt[2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hBBBBBBB88888888B)) \n \\prbs_dec_tap_cnt[3]_i_1 \n (.I0(\\prbs_dec_tap_cnt[3]_i_2_n_0 ),\n .I1(Q[2]),\n .I2(prbs_dec_tap_cnt[0]),\n .I3(prbs_dec_tap_cnt[1]),\n .I4(prbs_dec_tap_cnt[2]),\n .I5(prbs_dec_tap_cnt[3]),\n .O(\\prbs_dec_tap_cnt[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair49\" *) \n LUT5 #(\n .INIT(32'h006AAAAA)) \n \\prbs_dec_tap_cnt[3]_i_2 \n (.I0(dec_cnt_reg[3]),\n .I1(dec_cnt_reg[2]),\n .I2(dec_cnt_reg[1]),\n .I3(\\prbs_dec_tap_cnt_reg[1]_0 [1]),\n .I4(\\prbs_dec_tap_cnt_reg[1]_0 [0]),\n .O(\\prbs_dec_tap_cnt[3]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFE0001)) \n \\prbs_dec_tap_cnt[4]_i_2 \n (.I0(prbs_dec_tap_cnt[3]),\n .I1(prbs_dec_tap_cnt[2]),\n .I2(prbs_dec_tap_cnt[1]),\n .I3(prbs_dec_tap_cnt[0]),\n .I4(prbs_dec_tap_cnt[4]),\n .O(\\prbs_dec_tap_cnt[4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00006AAAAAAAAAAA)) \n \\prbs_dec_tap_cnt[4]_i_3 \n (.I0(dec_cnt_reg[4]),\n .I1(dec_cnt_reg[3]),\n .I2(dec_cnt_reg[1]),\n .I3(dec_cnt_reg[2]),\n .I4(\\prbs_dec_tap_cnt_reg[1]_0 [1]),\n .I5(\\prbs_dec_tap_cnt_reg[1]_0 [0]),\n .O(\\prbs_dec_tap_cnt[4]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h1010100000000000)) \n \\prbs_dec_tap_cnt[5]_i_1 \n (.I0(Q[4]),\n .I1(Q[3]),\n .I2(Q[1]),\n .I3(p_3_in),\n .I4(Q[2]),\n .I5(Q[0]),\n .O(\\prbs_dec_tap_cnt[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\prbs_dec_tap_cnt[5]_i_3 \n (.I0(prbs_dec_tap_cnt[2]),\n .I1(prbs_dec_tap_cnt[0]),\n .I2(prbs_dec_tap_cnt[1]),\n .I3(prbs_dec_tap_cnt[4]),\n .I4(prbs_dec_tap_cnt[3]),\n .I5(prbs_dec_tap_cnt[5]),\n .O(p_3_in));\n LUT6 #(\n .INIT(64'hFFFFFFFE00000001)) \n \\prbs_dec_tap_cnt[5]_i_4 \n (.I0(prbs_dec_tap_cnt[4]),\n .I1(prbs_dec_tap_cnt[0]),\n .I2(prbs_dec_tap_cnt[1]),\n .I3(prbs_dec_tap_cnt[2]),\n .I4(prbs_dec_tap_cnt[3]),\n .I5(prbs_dec_tap_cnt[5]),\n .O(\\prbs_dec_tap_cnt[5]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hEAAAAAAAAAAAAAAA)) \n \\prbs_dec_tap_cnt[5]_i_5 \n (.I0(\\prbs_dec_tap_cnt_reg[1]_0 [1]),\n .I1(dec_cnt_reg[4]),\n .I2(dec_cnt_reg[2]),\n .I3(\\prbs_dec_tap_cnt_reg[1]_0 [0]),\n .I4(dec_cnt_reg[1]),\n .I5(dec_cnt_reg[3]),\n .O(\\prbs_dec_tap_cnt[5]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\prbs_dec_tap_cnt_reg[0] \n (.C(CLK),\n .CE(\\prbs_dec_tap_cnt[5]_i_1_n_0 ),\n .D(\\prbs_dec_tap_cnt[0]_i_1_n_0 ),\n .Q(prbs_dec_tap_cnt[0]),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE #(\n .INIT(1'b0)) \n \\prbs_dec_tap_cnt_reg[1] \n (.C(CLK),\n .CE(\\prbs_dec_tap_cnt[5]_i_1_n_0 ),\n .D(\\prbs_dec_tap_cnt[1]_i_1_n_0 ),\n .Q(prbs_dec_tap_cnt[1]),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE #(\n .INIT(1'b0)) \n \\prbs_dec_tap_cnt_reg[2] \n (.C(CLK),\n .CE(\\prbs_dec_tap_cnt[5]_i_1_n_0 ),\n .D(\\prbs_dec_tap_cnt[2]_i_1_n_0 ),\n .Q(prbs_dec_tap_cnt[2]),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE #(\n .INIT(1'b0)) \n \\prbs_dec_tap_cnt_reg[3] \n (.C(CLK),\n .CE(\\prbs_dec_tap_cnt[5]_i_1_n_0 ),\n .D(\\prbs_dec_tap_cnt[3]_i_1_n_0 ),\n .Q(prbs_dec_tap_cnt[3]),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE #(\n .INIT(1'b0)) \n \\prbs_dec_tap_cnt_reg[4] \n (.C(CLK),\n .CE(\\prbs_dec_tap_cnt[5]_i_1_n_0 ),\n .D(\\prbs_dec_tap_cnt_reg[4]_i_1_n_0 ),\n .Q(prbs_dec_tap_cnt[4]),\n .R(rstdiv0_sync_r1_reg_rep__9));\n MUXF7 \\prbs_dec_tap_cnt_reg[4]_i_1 \n (.I0(\\prbs_dec_tap_cnt[4]_i_2_n_0 ),\n .I1(\\prbs_dec_tap_cnt[4]_i_3_n_0 ),\n .O(\\prbs_dec_tap_cnt_reg[4]_i_1_n_0 ),\n .S(Q[2]));\n FDRE #(\n .INIT(1'b0)) \n \\prbs_dec_tap_cnt_reg[5] \n (.C(CLK),\n .CE(\\prbs_dec_tap_cnt[5]_i_1_n_0 ),\n .D(\\prbs_dec_tap_cnt_reg[5]_i_2_n_0 ),\n .Q(prbs_dec_tap_cnt[5]),\n .R(rstdiv0_sync_r1_reg_rep__9));\n MUXF7 \\prbs_dec_tap_cnt_reg[5]_i_2 \n (.I0(\\prbs_dec_tap_cnt[5]_i_4_n_0 ),\n .I1(\\prbs_dec_tap_cnt[5]_i_5_n_0 ),\n .O(\\prbs_dec_tap_cnt_reg[5]_i_2_n_0 ),\n .S(Q[2]));\n LUT6 #(\n .INIT(64'h0000000000000800)) \n \\prbs_dqs_cnt_r[1]_i_2 \n (.I0(prbs_rdlvl_done_reg_1),\n .I1(Q[3]),\n .I2(prbs_last_byte_done_reg_0),\n .I3(prech_done),\n .I4(Q[1]),\n .I5(Q[2]),\n .O(\\prbs_dqs_cnt_r_reg[1]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\prbs_dqs_cnt_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\prbs_dqs_cnt_r_reg[0]_1 ),\n .Q(\\A[0]_0 ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE #(\n .INIT(1'b0)) \n \\prbs_dqs_cnt_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\prbs_dqs_cnt_r_reg[0]_0 ),\n .Q(\\A[1]_0 ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE #(\n .INIT(1'b0)) \n \\prbs_dqs_cnt_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\prbs_dqs_cnt_r_reg[0]_2 ),\n .Q(\\prbs_dqs_cnt_r_reg[2]_0 ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n (* SOFT_HLUTNM = \"soft_lutpair68\" *) \n LUT4 #(\n .INIT(16'h404F)) \n \\prbs_dqs_tap_cnt_r[0]_i_1 \n (.I0(\\calib_sel_reg[3] ),\n .I1(\\pi_counter_read_val_reg[5] [0]),\n .I2(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .O(\\prbs_dqs_tap_cnt_r[0]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h404F)) \n \\prbs_dqs_tap_cnt_r[0]_rep__0_i_1 \n (.I0(\\calib_sel_reg[3] ),\n .I1(\\pi_counter_read_val_reg[5] [0]),\n .I2(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .O(\\prbs_dqs_tap_cnt_r[0]_rep__0_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h404F)) \n \\prbs_dqs_tap_cnt_r[0]_rep_i_1 \n (.I0(\\calib_sel_reg[3] ),\n .I1(\\pi_counter_read_val_reg[5] [0]),\n .I2(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .O(\\prbs_dqs_tap_cnt_r[0]_rep_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0F0066660F009999)) \n \\prbs_dqs_tap_cnt_r[1]_i_1 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I2(\\calib_sel_reg[3] ),\n .I3(\\pi_counter_read_val_reg[5] [1]),\n .I4(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .I5(prbs_tap_inc_r),\n .O(\\prbs_dqs_tap_cnt_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0F0066660F009999)) \n \\prbs_dqs_tap_cnt_r[1]_rep__0_i_1 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I2(\\calib_sel_reg[3] ),\n .I3(\\pi_counter_read_val_reg[5] [1]),\n .I4(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .I5(prbs_tap_inc_r),\n .O(\\prbs_dqs_tap_cnt_r[1]_rep__0_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0F0066660F009999)) \n \\prbs_dqs_tap_cnt_r[1]_rep_i_1 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I2(\\calib_sel_reg[3] ),\n .I3(\\pi_counter_read_val_reg[5] [1]),\n .I4(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .I5(prbs_tap_inc_r),\n .O(\\prbs_dqs_tap_cnt_r[1]_rep_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8BB8BB88BB88B88B)) \n \\prbs_dqs_tap_cnt_r[2]_i_1 \n (.I0(\\calib_sel_reg[3]_1 ),\n .I1(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .I2(prbs_tap_inc_r),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .O(\\prbs_dqs_tap_cnt_r[2]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hB888B8BB)) \n \\prbs_dqs_tap_cnt_r[3]_i_1 \n (.I0(\\rdlvl_cpt_tap_cnt_reg[5]_1 [1]),\n .I1(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .I2(\\prbs_dqs_tap_cnt_r[3]_i_2_n_0 ),\n .I3(prbs_tap_inc_r),\n .I4(\\prbs_dqs_tap_cnt_r[3]_i_3_n_0 ),\n .O(\\prbs_dqs_tap_cnt_r[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair44\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\prbs_dqs_tap_cnt_r[3]_i_2 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I1(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .O(\\prbs_dqs_tap_cnt_r[3]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair62\" *) \n LUT4 #(\n .INIT(16'h01FE)) \n \\prbs_dqs_tap_cnt_r[3]_i_3 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .O(\\prbs_dqs_tap_cnt_r[3]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hB888B8BB)) \n \\prbs_dqs_tap_cnt_r[3]_rep__0_i_1 \n (.I0(\\rdlvl_cpt_tap_cnt_reg[5]_1 [1]),\n .I1(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .I2(\\prbs_dqs_tap_cnt_r[3]_i_2_n_0 ),\n .I3(prbs_tap_inc_r),\n .I4(\\prbs_dqs_tap_cnt_r[3]_i_3_n_0 ),\n .O(\\prbs_dqs_tap_cnt_r[3]_rep__0_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hB888B8BB)) \n \\prbs_dqs_tap_cnt_r[3]_rep_i_1 \n (.I0(\\rdlvl_cpt_tap_cnt_reg[5]_1 [1]),\n .I1(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .I2(\\prbs_dqs_tap_cnt_r[3]_i_2_n_0 ),\n .I3(prbs_tap_inc_r),\n .I4(\\prbs_dqs_tap_cnt_r[3]_i_3_n_0 ),\n .O(\\prbs_dqs_tap_cnt_r[3]_rep_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8BB888888BB8BBBB)) \n \\prbs_dqs_tap_cnt_r[4]_i_1 \n (.I0(\\calib_sel_reg[3]_2 ),\n .I1(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .I2(\\prbs_dqs_tap_cnt_r[4]_i_2_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I4(prbs_tap_inc_r),\n .I5(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .O(\\prbs_dqs_tap_cnt_r[4]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8000)) \n \\prbs_dqs_tap_cnt_r[4]_i_2 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I1(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .O(\\prbs_dqs_tap_cnt_r[4]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h0001FFFE)) \n \\prbs_dqs_tap_cnt_r[4]_i_3 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I1(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .O(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'hFEAA)) \n \\prbs_dqs_tap_cnt_r[5]_i_1 \n (.I0(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .I1(prbs_tap_inc_r),\n .I2(\\prbs_dqs_tap_cnt_r[5]_i_3_n_0 ),\n .I3(pi_en_stg2_f_timing_reg_0),\n .O(\\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hB888B8BB)) \n \\prbs_dqs_tap_cnt_r[5]_i_2 \n (.I0(\\rdlvl_cpt_tap_cnt_reg[5]_1 [2]),\n .I1(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .I2(\\prbs_dqs_tap_cnt_r[5]_i_4_n_0 ),\n .I3(prbs_tap_inc_r),\n .I4(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\prbs_dqs_tap_cnt_r[5]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\prbs_dqs_tap_cnt_r[5]_i_3 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\prbs_dqs_tap_cnt_r[5]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h7FFFFFFF80000000)) \n \\prbs_dqs_tap_cnt_r[5]_i_4 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I1(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\prbs_dqs_tap_cnt_r[5]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h00000001FFFFFFFE)) \n \\prbs_dqs_tap_cnt_r[5]_i_5 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ));\n (* ORIG_CELL_NAME = \"prbs_dqs_tap_cnt_r_reg[0]\" *) \n FDRE #(\n .INIT(1'b0)) \n \\prbs_dqs_tap_cnt_r_reg[0] \n (.C(CLK),\n .CE(\\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ),\n .D(\\prbs_dqs_tap_cnt_r[0]_i_1_n_0 ),\n .Q(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n (* ORIG_CELL_NAME = \"prbs_dqs_tap_cnt_r_reg[0]\" *) \n FDRE #(\n .INIT(1'b0)) \n \\prbs_dqs_tap_cnt_r_reg[0]_rep \n (.C(CLK),\n .CE(\\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ),\n .D(\\prbs_dqs_tap_cnt_r[0]_rep_i_1_n_0 ),\n .Q(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .R(rstdiv0_sync_r1_reg_rep));\n (* ORIG_CELL_NAME = \"prbs_dqs_tap_cnt_r_reg[0]\" *) \n FDRE #(\n .INIT(1'b0)) \n \\prbs_dqs_tap_cnt_r_reg[0]_rep__0 \n (.C(CLK),\n .CE(\\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ),\n .D(\\prbs_dqs_tap_cnt_r[0]_rep__0_i_1_n_0 ),\n .Q(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .R(rstdiv0_sync_r1_reg_rep));\n (* ORIG_CELL_NAME = \"prbs_dqs_tap_cnt_r_reg[1]\" *) \n FDRE #(\n .INIT(1'b0)) \n \\prbs_dqs_tap_cnt_r_reg[1] \n (.C(CLK),\n .CE(\\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ),\n .D(\\prbs_dqs_tap_cnt_r[1]_i_1_n_0 ),\n .Q(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n (* ORIG_CELL_NAME = \"prbs_dqs_tap_cnt_r_reg[1]\" *) \n FDRE #(\n .INIT(1'b0)) \n \\prbs_dqs_tap_cnt_r_reg[1]_rep \n (.C(CLK),\n .CE(\\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ),\n .D(\\prbs_dqs_tap_cnt_r[1]_rep_i_1_n_0 ),\n .Q(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .R(rstdiv0_sync_r1_reg_rep));\n (* ORIG_CELL_NAME = \"prbs_dqs_tap_cnt_r_reg[1]\" *) \n FDRE #(\n .INIT(1'b0)) \n \\prbs_dqs_tap_cnt_r_reg[1]_rep__0 \n (.C(CLK),\n .CE(\\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ),\n .D(\\prbs_dqs_tap_cnt_r[1]_rep__0_i_1_n_0 ),\n .Q(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE #(\n .INIT(1'b0)) \n \\prbs_dqs_tap_cnt_r_reg[2] \n (.C(CLK),\n .CE(\\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ),\n .D(\\prbs_dqs_tap_cnt_r[2]_i_1_n_0 ),\n .Q(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n (* ORIG_CELL_NAME = \"prbs_dqs_tap_cnt_r_reg[3]\" *) \n FDRE #(\n .INIT(1'b0)) \n \\prbs_dqs_tap_cnt_r_reg[3] \n (.C(CLK),\n .CE(\\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ),\n .D(\\prbs_dqs_tap_cnt_r[3]_i_1_n_0 ),\n .Q(\\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n (* ORIG_CELL_NAME = \"prbs_dqs_tap_cnt_r_reg[3]\" *) \n FDRE #(\n .INIT(1'b0)) \n \\prbs_dqs_tap_cnt_r_reg[3]_rep \n (.C(CLK),\n .CE(\\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ),\n .D(\\prbs_dqs_tap_cnt_r[3]_rep_i_1_n_0 ),\n .Q(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .R(rstdiv0_sync_r1_reg_rep));\n (* ORIG_CELL_NAME = \"prbs_dqs_tap_cnt_r_reg[3]\" *) \n FDRE #(\n .INIT(1'b0)) \n \\prbs_dqs_tap_cnt_r_reg[3]_rep__0 \n (.C(CLK),\n .CE(\\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ),\n .D(\\prbs_dqs_tap_cnt_r[3]_rep__0_i_1_n_0 ),\n .Q(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE #(\n .INIT(1'b0)) \n \\prbs_dqs_tap_cnt_r_reg[4] \n (.C(CLK),\n .CE(\\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ),\n .D(\\prbs_dqs_tap_cnt_r[4]_i_1_n_0 ),\n .Q(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE #(\n .INIT(1'b0)) \n \\prbs_dqs_tap_cnt_r_reg[5] \n (.C(CLK),\n .CE(\\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ),\n .D(\\prbs_dqs_tap_cnt_r[5]_i_2_n_0 ),\n .Q(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE #(\n .INIT(1'b0)) \n prbs_dqs_tap_limit_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(new_cnt_dqs_r_reg_1),\n .Q(prbs_dqs_tap_limit_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAAAAAB)) \n prbs_found_1st_edge_r_i_2\n (.I0(compare_err_latch_reg_n_0),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I5(prbs_found_1st_edge_r_i_5_n_0),\n .O(prbs_state_r178_out));\n (* SOFT_HLUTNM = \"soft_lutpair29\" *) \n LUT2 #(\n .INIT(4'h1)) \n prbs_found_1st_edge_r_i_3\n (.I0(Q[2]),\n .I1(Q[4]),\n .O(complex_pi_incdec_done_reg_1));\n (* SOFT_HLUTNM = \"soft_lutpair27\" *) \n LUT5 #(\n .INIT(32'h00FF2000)) \n prbs_found_1st_edge_r_i_4\n (.I0(prbs_state_r178_out),\n .I1(prbs_dqs_tap_limit_r),\n .I2(num_samples_done_r),\n .I3(Q[1]),\n .I4(Q[3]),\n .O(prbs_found_1st_edge_r_reg_1));\n (* SOFT_HLUTNM = \"soft_lutpair69\" *) \n LUT2 #(\n .INIT(4'hE)) \n prbs_found_1st_edge_r_i_5\n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(prbs_found_1st_edge_r_i_5_n_0));\n FDRE #(\n .INIT(1'b0)) \n prbs_found_1st_edge_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\prbs_state_r_reg[3]_0 ),\n .Q(prbs_found_1st_edge_r_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__8));\n LUT4 #(\n .INIT(16'h06F6)) \n \\prbs_inc_tap_cnt[0]_i_1 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I1(rdlvl_cpt_tap_cnt[0]),\n .I2(Q[2]),\n .I3(\\prbs_inc_tap_cnt_reg_n_0_[0] ),\n .O(\\prbs_inc_tap_cnt[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAA3055CFAACF5530)) \n \\prbs_inc_tap_cnt[1]_i_1 \n (.I0(\\prbs_inc_tap_cnt_reg_n_0_[0] ),\n .I1(rdlvl_cpt_tap_cnt[0]),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(Q[2]),\n .I4(\\prbs_inc_tap_cnt[1]_i_2_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .O(\\prbs_inc_tap_cnt[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair72\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\prbs_inc_tap_cnt[1]_i_2 \n (.I0(\\prbs_inc_tap_cnt_reg_n_0_[1] ),\n .I1(Q[2]),\n .I2(rdlvl_cpt_tap_cnt[1]),\n .O(\\prbs_inc_tap_cnt[1]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair47\" *) \n LUT5 #(\n .INIT(32'h99699966)) \n \\prbs_inc_tap_cnt[2]_i_1 \n (.I0(\\prbs_inc_tap_cnt[2]_i_2_n_0 ),\n .I1(\\prbs_inc_tap_cnt[2]_i_3_n_0 ),\n .I2(rdlvl_cpt_tap_cnt[1]),\n .I3(Q[2]),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .O(\\prbs_inc_tap_cnt[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFCFAAFFFFFFAACF)) \n \\prbs_inc_tap_cnt[2]_i_2 \n (.I0(\\prbs_inc_tap_cnt_reg_n_0_[0] ),\n .I1(rdlvl_cpt_tap_cnt[0]),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(Q[2]),\n .I4(\\prbs_inc_tap_cnt[1]_i_2_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .O(\\prbs_inc_tap_cnt[2]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair58\" *) \n LUT4 #(\n .INIT(16'hF909)) \n \\prbs_inc_tap_cnt[2]_i_3 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I1(rdlvl_cpt_tap_cnt[2]),\n .I2(Q[2]),\n .I3(\\prbs_inc_tap_cnt_reg_n_0_[2] ),\n .O(\\prbs_inc_tap_cnt[2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h6666669699996696)) \n \\prbs_inc_tap_cnt[3]_i_1 \n (.I0(\\prbs_inc_tap_cnt[3]_i_2_n_0 ),\n .I1(\\prbs_inc_tap_cnt[3]_i_3_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(rdlvl_cpt_tap_cnt[2]),\n .I4(Q[2]),\n .I5(\\prbs_inc_tap_cnt_reg_n_0_[2] ),\n .O(\\prbs_inc_tap_cnt[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF477447740000)) \n \\prbs_inc_tap_cnt[3]_i_2 \n (.I0(\\prbs_inc_tap_cnt_reg_n_0_[2] ),\n .I1(Q[2]),\n .I2(rdlvl_cpt_tap_cnt[2]),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_inc_tap_cnt[3]_i_4_n_0 ),\n .I5(\\prbs_inc_tap_cnt[2]_i_2_n_0 ),\n .O(\\prbs_inc_tap_cnt[3]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair61\" *) \n LUT4 #(\n .INIT(16'hF909)) \n \\prbs_inc_tap_cnt[3]_i_3 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I1(rdlvl_cpt_tap_cnt[3]),\n .I2(Q[2]),\n .I3(\\prbs_inc_tap_cnt_reg_n_0_[3] ),\n .O(\\prbs_inc_tap_cnt[3]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair47\" *) \n LUT3 #(\n .INIT(8'h23)) \n \\prbs_inc_tap_cnt[3]_i_4 \n (.I0(rdlvl_cpt_tap_cnt[1]),\n .I1(Q[2]),\n .I2(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .O(\\prbs_inc_tap_cnt[3]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h6666669699996696)) \n \\prbs_inc_tap_cnt[4]_i_1 \n (.I0(\\prbs_inc_tap_cnt[5]_i_5_n_0 ),\n .I1(\\prbs_inc_tap_cnt[4]_i_2_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I3(rdlvl_cpt_tap_cnt[3]),\n .I4(Q[2]),\n .I5(\\prbs_inc_tap_cnt_reg_n_0_[3] ),\n .O(\\prbs_inc_tap_cnt[4]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair63\" *) \n LUT4 #(\n .INIT(16'hF909)) \n \\prbs_inc_tap_cnt[4]_i_2 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(rdlvl_cpt_tap_cnt[4]),\n .I2(Q[2]),\n .I3(\\prbs_inc_tap_cnt_reg_n_0_[4] ),\n .O(\\prbs_inc_tap_cnt[4]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h00004540)) \n \\prbs_inc_tap_cnt[5]_i_1 \n (.I0(Q[3]),\n .I1(\\prbs_inc_tap_cnt[5]_i_3_n_0 ),\n .I2(Q[2]),\n .I3(\\prbs_inc_tap_cnt[5]_i_4_n_0 ),\n .I4(Q[4]),\n .O(\\prbs_inc_tap_cnt[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h7878781EE1E1E178)) \n \\prbs_inc_tap_cnt[5]_i_2 \n (.I0(\\prbs_inc_tap_cnt[5]_i_5_n_0 ),\n .I1(\\prbs_inc_tap_cnt[5]_i_6_n_0 ),\n .I2(\\prbs_inc_tap_cnt[5]_i_7_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I4(Q[2]),\n .I5(\\prbs_inc_tap_cnt[5]_i_8_n_0 ),\n .O(\\prbs_inc_tap_cnt[5]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair20\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\prbs_inc_tap_cnt[5]_i_3 \n (.I0(\\prbs_state_r[1]_i_5_n_0 ),\n .I1(Q[0]),\n .I2(Q[1]),\n .O(\\prbs_inc_tap_cnt[5]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000200000)) \n \\prbs_inc_tap_cnt[5]_i_4 \n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(prbs_state_r178_out),\n .I3(prbs_found_1st_edge_r_reg_0),\n .I4(num_samples_done_r),\n .I5(prbs_dqs_tap_limit_r),\n .O(\\prbs_inc_tap_cnt[5]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF477447740000)) \n \\prbs_inc_tap_cnt[5]_i_5 \n (.I0(\\prbs_inc_tap_cnt_reg_n_0_[3] ),\n .I1(Q[2]),\n .I2(rdlvl_cpt_tap_cnt[3]),\n .I3(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I4(\\prbs_inc_tap_cnt[5]_i_9_n_0 ),\n .I5(\\prbs_inc_tap_cnt[3]_i_2_n_0 ),\n .O(\\prbs_inc_tap_cnt[5]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair61\" *) \n LUT4 #(\n .INIT(16'hFD0D)) \n \\prbs_inc_tap_cnt[5]_i_6 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),\n .I1(rdlvl_cpt_tap_cnt[3]),\n .I2(Q[2]),\n .I3(\\prbs_inc_tap_cnt_reg_n_0_[3] ),\n .O(\\prbs_inc_tap_cnt[5]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair69\" *) \n LUT4 #(\n .INIT(16'hF909)) \n \\prbs_inc_tap_cnt[5]_i_7 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .I1(rdlvl_cpt_tap_cnt[5]),\n .I2(Q[2]),\n .I3(\\prbs_inc_tap_cnt_reg_n_0_[5] ),\n .O(\\prbs_inc_tap_cnt[5]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair63\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\prbs_inc_tap_cnt[5]_i_8 \n (.I0(\\prbs_inc_tap_cnt_reg_n_0_[4] ),\n .I1(Q[2]),\n .I2(rdlvl_cpt_tap_cnt[4]),\n .O(\\prbs_inc_tap_cnt[5]_i_8_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair58\" *) \n LUT4 #(\n .INIT(16'hFD0D)) \n \\prbs_inc_tap_cnt[5]_i_9 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I1(rdlvl_cpt_tap_cnt[2]),\n .I2(Q[2]),\n .I3(\\prbs_inc_tap_cnt_reg_n_0_[2] ),\n .O(\\prbs_inc_tap_cnt[5]_i_9_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\prbs_inc_tap_cnt_reg[0] \n (.C(CLK),\n .CE(\\prbs_inc_tap_cnt[5]_i_1_n_0 ),\n .D(\\prbs_inc_tap_cnt[0]_i_1_n_0 ),\n .Q(\\prbs_inc_tap_cnt_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE #(\n .INIT(1'b0)) \n \\prbs_inc_tap_cnt_reg[1] \n (.C(CLK),\n .CE(\\prbs_inc_tap_cnt[5]_i_1_n_0 ),\n .D(\\prbs_inc_tap_cnt[1]_i_1_n_0 ),\n .Q(\\prbs_inc_tap_cnt_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE #(\n .INIT(1'b0)) \n \\prbs_inc_tap_cnt_reg[2] \n (.C(CLK),\n .CE(\\prbs_inc_tap_cnt[5]_i_1_n_0 ),\n .D(\\prbs_inc_tap_cnt[2]_i_1_n_0 ),\n .Q(\\prbs_inc_tap_cnt_reg_n_0_[2] ),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE #(\n .INIT(1'b0)) \n \\prbs_inc_tap_cnt_reg[3] \n (.C(CLK),\n .CE(\\prbs_inc_tap_cnt[5]_i_1_n_0 ),\n .D(\\prbs_inc_tap_cnt[3]_i_1_n_0 ),\n .Q(\\prbs_inc_tap_cnt_reg_n_0_[3] ),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE #(\n .INIT(1'b0)) \n \\prbs_inc_tap_cnt_reg[4] \n (.C(CLK),\n .CE(\\prbs_inc_tap_cnt[5]_i_1_n_0 ),\n .D(\\prbs_inc_tap_cnt[4]_i_1_n_0 ),\n .Q(\\prbs_inc_tap_cnt_reg_n_0_[4] ),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE #(\n .INIT(1'b0)) \n \\prbs_inc_tap_cnt_reg[5] \n (.C(CLK),\n .CE(\\prbs_inc_tap_cnt[5]_i_1_n_0 ),\n .D(\\prbs_inc_tap_cnt[5]_i_2_n_0 ),\n .Q(\\prbs_inc_tap_cnt_reg_n_0_[5] ),\n .R(rstdiv0_sync_r1_reg_rep__7));\n LUT3 #(\n .INIT(8'hEA)) \n prbs_last_byte_done_i_2\n (.I0(\\prbs_dqs_cnt_r_reg[2]_0 ),\n .I1(\\A[0]_0 ),\n .I2(\\A[1]_0 ),\n .O(prbs_last_byte_done_reg_0));\n FDRE #(\n .INIT(1'b0)) \n prbs_last_byte_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\prbs_state_r_reg[0]_3 ),\n .Q(prbs_last_byte_done),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE #(\n .INIT(1'b0)) \n prbs_prech_req_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prech_done_reg),\n .Q(prbs_prech_req_r),\n .R(rstdiv0_sync_r1_reg_rep__8));\n (* SOFT_HLUTNM = \"soft_lutpair67\" *) \n LUT2 #(\n .INIT(4'h1)) \n prbs_rdlvl_done_i_2\n (.I0(Q[4]),\n .I1(Q[0]),\n .O(prbs_rdlvl_done_reg_1));\n LUT2 #(\n .INIT(4'h2)) \n prbs_rdlvl_done_pulse_i_1\n (.I0(complex_oclkdelay_calib_done_r1_reg),\n .I1(prbs_rdlvl_done_r1),\n .O(prbs_rdlvl_done_pulse0));\n (* MAX_FANOUT = \"100\" *) \n (* ORIG_CELL_NAME = \"prbs_rdlvl_done_reg\" *) \n FDRE #(\n .INIT(1'b0)) \n prbs_rdlvl_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(fine_dly_error_reg_1),\n .Q(\\stg1_wr_rd_cnt_reg[3] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* MAX_FANOUT = \"100\" *) \n (* ORIG_CELL_NAME = \"prbs_rdlvl_done_reg\" *) \n FDRE #(\n .INIT(1'b0)) \n prbs_rdlvl_done_reg_rep\n (.C(CLK),\n .CE(1'b1),\n .D(fine_dly_error_reg_1),\n .Q(complex_oclkdelay_calib_done_r1_reg),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE #(\n .INIT(1'b0)) \n prbs_rdlvl_prech_req_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prbs_prech_req_r),\n .Q(prech_req_r_reg),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE #(\n .INIT(1'b0)) \n prbs_rdlvl_start_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prbs_rdlvl_start_reg),\n .Q(prbs_rdlvl_start_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFF0DFDFFFF0D0D0)) \n \\prbs_state_r[0]_i_1 \n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(Q[4]),\n .I3(\\prbs_state_r[0]_i_2_n_0 ),\n .I4(\\prbs_state_r[0]_i_3_n_0 ),\n .I5(\\prbs_state_r[0]_i_4_n_0 ),\n .O(\\prbs_state_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h1C1C1C1C1C1D1D1D)) \n \\prbs_state_r[0]_i_2 \n (.I0(Q[1]),\n .I1(Q[2]),\n .I2(Q[0]),\n .I3(\\A[1]_0 ),\n .I4(\\A[0]_0 ),\n .I5(\\prbs_dqs_cnt_r_reg[2]_0 ),\n .O(\\prbs_state_r[0]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair28\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\prbs_state_r[0]_i_3 \n (.I0(Q[2]),\n .I1(Q[4]),\n .I2(Q[3]),\n .O(\\prbs_state_r[0]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hCCB8FFFFCCB80000)) \n \\prbs_state_r[0]_i_4 \n (.I0(\\prbs_state_r[1]_i_5_n_0 ),\n .I1(Q[1]),\n .I2(p_3_in),\n .I3(Q[0]),\n .I4(Q[2]),\n .I5(\\prbs_state_r[0]_i_5_n_0 ),\n .O(\\prbs_state_r[0]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair24\" *) \n LUT5 #(\n .INIT(32'h5445FFFF)) \n \\prbs_state_r[0]_i_5 \n (.I0(Q[0]),\n .I1(prbs_dqs_tap_limit_r),\n .I2(prbs_state_r178_out),\n .I3(prbs_found_1st_edge_r_reg_0),\n .I4(Q[1]),\n .O(\\prbs_state_r[0]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair18\" *) \n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\prbs_state_r[1]_i_1 \n (.I0(\\prbs_state_r[1]_i_2_n_0 ),\n .I1(Q[4]),\n .I2(\\prbs_state_r[1]_i_3_n_0 ),\n .I3(Q[3]),\n .I4(\\prbs_state_r[1]_i_4_n_0 ),\n .O(\\prbs_state_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0047FFB80000FFB8)) \n \\prbs_state_r[1]_i_2 \n (.I0(Q[2]),\n .I1(Q[4]),\n .I2(Q[3]),\n .I3(Q[1]),\n .I4(Q[0]),\n .I5(prbs_state_r1),\n .O(\\prbs_state_r[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0F000F001F0F1F00)) \n \\prbs_state_r[1]_i_3 \n (.I0(prbs_tap_en_r_reg_0),\n .I1(fine_inc_stage_reg_n_0),\n .I2(Q[1]),\n .I3(Q[2]),\n .I4(prbs_last_byte_done_reg_0),\n .I5(Q[0]),\n .O(\\prbs_state_r[1]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair20\" *) \n LUT5 #(\n .INIT(32'h0C0C4C7C)) \n \\prbs_state_r[1]_i_4 \n (.I0(\\prbs_state_r[1]_i_5_n_0 ),\n .I1(Q[2]),\n .I2(Q[1]),\n .I3(\\prbs_state_r[1]_i_6_n_0 ),\n .I4(Q[0]),\n .O(\\prbs_state_r[1]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\prbs_state_r[1]_i_5 \n (.I0(\\prbs_inc_tap_cnt_reg_n_0_[2] ),\n .I1(\\prbs_inc_tap_cnt_reg_n_0_[0] ),\n .I2(\\prbs_inc_tap_cnt_reg_n_0_[1] ),\n .I3(\\prbs_inc_tap_cnt_reg_n_0_[4] ),\n .I4(\\prbs_inc_tap_cnt_reg_n_0_[3] ),\n .I5(\\prbs_inc_tap_cnt_reg_n_0_[5] ),\n .O(\\prbs_state_r[1]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair24\" *) \n LUT3 #(\n .INIT(8'h15)) \n \\prbs_state_r[1]_i_6 \n (.I0(prbs_dqs_tap_limit_r),\n .I1(prbs_state_r178_out),\n .I2(prbs_found_1st_edge_r_reg_0),\n .O(\\prbs_state_r[1]_i_6_n_0 ));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\prbs_state_r[2]_i_10 \n (.I0(\\genblk8[1].right_edge_pb_reg[6]_0 ),\n .I1(\\genblk8[0].right_edge_pb_reg[0]_0 ),\n .I2(\\genblk8[3].right_edge_pb_reg[18]_0 ),\n .I3(\\genblk8[2].right_edge_pb_reg[12]_0 ),\n .O(\\prbs_state_r[2]_i_10_n_0 ));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\prbs_state_r[2]_i_11 \n (.I0(\\match_flag_and_reg_n_0_[2] ),\n .I1(\\match_flag_and_reg_n_0_[3] ),\n .I2(\\match_flag_and_reg_n_0_[0] ),\n .I3(\\match_flag_and_reg_n_0_[1] ),\n .O(\\prbs_state_r[2]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'h4F00FFFF4F000000)) \n \\prbs_state_r[2]_i_2 \n (.I0(Q[0]),\n .I1(prbs_tap_en_r_reg_0),\n .I2(Q[1]),\n .I3(Q[2]),\n .I4(\\prbs_state_r[0]_i_3_n_0 ),\n .I5(\\prbs_state_r[2]_i_4_n_0 ),\n .O(\\prbs_state_r[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFE2E2E2FFE2E2)) \n \\prbs_state_r[2]_i_3 \n (.I0(Q[3]),\n .I1(Q[4]),\n .I2(Q[2]),\n .I3(prbs_state_r1),\n .I4(Q[0]),\n .I5(Q[1]),\n .O(\\prbs_state_r[2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFCFCFFFFBB880000)) \n \\prbs_state_r[2]_i_4 \n (.I0(\\prbs_state_r[1]_i_5_n_0 ),\n .I1(Q[2]),\n .I2(\\prbs_state_r[2]_i_6_n_0 ),\n .I3(\\prbs_state_r[1]_i_6_n_0 ),\n .I4(Q[1]),\n .I5(Q[0]),\n .O(\\prbs_state_r[2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hEAEAEAEAEAEAEAAA)) \n \\prbs_state_r[2]_i_5 \n (.I0(\\prbs_state_r[2]_i_7_n_0 ),\n .I1(\\prbs_state_r[2]_i_8_n_0 ),\n .I2(\\prbs_state_r[2]_i_9_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .O(prbs_state_r1));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFD)) \n \\prbs_state_r[2]_i_6 \n (.I0(prbs_dec_tap_cnt[0]),\n .I1(prbs_dec_tap_cnt[4]),\n .I2(prbs_dec_tap_cnt[1]),\n .I3(prbs_dec_tap_cnt[5]),\n .I4(prbs_dec_tap_cnt[3]),\n .I5(prbs_dec_tap_cnt[2]),\n .O(\\prbs_state_r[2]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hBAAAAAAAAAAAAAAA)) \n \\prbs_state_r[2]_i_7 \n (.I0(prbs_dqs_tap_limit_r),\n .I1(\\prbs_state_r[2]_i_10_n_0 ),\n .I2(\\genblk8[5].right_edge_pb_reg[30]_0 ),\n .I3(\\genblk8[4].right_edge_pb_reg[24]_0 ),\n .I4(\\genblk8[6].right_edge_pb_reg[36]_0 ),\n .I5(\\genblk8[7].right_edge_pb_reg[42]_0 ),\n .O(\\prbs_state_r[2]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair19\" *) \n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n \\prbs_state_r[2]_i_8 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\prbs_state_r[2]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\prbs_state_r[2]_i_9 \n (.I0(compare_err_pb_and_reg_n_0),\n .I1(\\prbs_state_r[2]_i_11_n_0 ),\n .I2(\\match_flag_and_reg_n_0_[6] ),\n .I3(\\match_flag_and_reg_n_0_[7] ),\n .I4(\\match_flag_and_reg_n_0_[4] ),\n .I5(\\match_flag_and_reg_n_0_[5] ),\n .O(\\prbs_state_r[2]_i_9_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair29\" *) \n LUT5 #(\n .INIT(32'hE4A5E4A0)) \n \\prbs_state_r[3]_i_1 \n (.I0(Q[4]),\n .I1(\\prbs_state_r[3]_i_2_n_0 ),\n .I2(Q[2]),\n .I3(Q[3]),\n .I4(\\prbs_state_r[3]_i_3_n_0 ),\n .O(\\prbs_state_r[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair39\" *) \n LUT5 #(\n .INIT(32'h0FF0B0FF)) \n \\prbs_state_r[3]_i_2 \n (.I0(prbs_tap_en_r_reg_0),\n .I1(fine_inc_stage_reg_n_0),\n .I2(Q[1]),\n .I3(Q[2]),\n .I4(Q[0]),\n .O(\\prbs_state_r[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAFFFFFFC00000)) \n \\prbs_state_r[3]_i_3 \n (.I0(\\prbs_state_r[3]_i_4_n_0 ),\n .I1(prbs_found_1st_edge_r_reg_0),\n .I2(prbs_state_r178_out),\n .I3(prbs_dqs_tap_limit_r),\n .I4(Q[1]),\n .I5(Q[0]),\n .O(\\prbs_state_r[3]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000100)) \n \\prbs_state_r[3]_i_4 \n (.I0(prbs_dec_tap_cnt[5]),\n .I1(prbs_dec_tap_cnt[4]),\n .I2(prbs_dec_tap_cnt[1]),\n .I3(prbs_dec_tap_cnt[0]),\n .I4(prbs_dec_tap_cnt[3]),\n .I5(prbs_dec_tap_cnt[2]),\n .O(\\prbs_state_r[3]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h00000001)) \n \\prbs_state_r[4]_i_11 \n (.I0(bit_cnt_reg__0[5]),\n .I1(bit_cnt_reg__0[4]),\n .I2(bit_cnt_reg__0[6]),\n .I3(bit_cnt_reg__0[7]),\n .I4(fine_delay_sel_i_4_n_0),\n .O(\\prbs_state_r[4]_i_11_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\prbs_state_r[4]_i_2 \n (.I0(\\prbs_state_r[4]_i_4_n_0 ),\n .I1(Q[4]),\n .I2(\\prbs_state_r[4]_i_5_n_0 ),\n .I3(Q[3]),\n .I4(\\prbs_state_r[4]_i_6_n_0 ),\n .O(\\prbs_state_r[4]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair28\" *) \n LUT5 #(\n .INIT(32'h4E5F4E0A)) \n \\prbs_state_r[4]_i_3 \n (.I0(Q[4]),\n .I1(\\prbs_state_r[4]_i_7_n_0 ),\n .I2(Q[2]),\n .I3(Q[3]),\n .I4(\\prbs_state_r[4]_i_8_n_0 ),\n .O(\\prbs_state_r[4]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0A3A3A3A0A0A0A0A)) \n \\prbs_state_r[4]_i_4 \n (.I0(\\prbs_state_r[4]_i_9_n_0 ),\n .I1(Q[1]),\n .I2(Q[2]),\n .I3(prbs_rdlvl_done_reg_0),\n .I4(Q[0]),\n .I5(complex_act_start),\n .O(\\prbs_state_r[4]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair25\" *) \n LUT5 #(\n .INIT(32'hFFF2FC32)) \n \\prbs_state_r[4]_i_5 \n (.I0(prech_done),\n .I1(Q[1]),\n .I2(Q[2]),\n .I3(Q[0]),\n .I4(cnt_wait_state),\n .O(\\prbs_state_r[4]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFFAEF45FFFAEA40)) \n \\prbs_state_r[4]_i_6 \n (.I0(Q[2]),\n .I1(num_samples_done_r),\n .I2(Q[1]),\n .I3(cnt_wait_state),\n .I4(Q[0]),\n .I5(prbs_rdlvl_start_reg_0),\n .O(\\prbs_state_r[4]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair39\" *) \n LUT5 #(\n .INIT(32'hAA080000)) \n \\prbs_state_r[4]_i_7 \n (.I0(Q[1]),\n .I1(fine_inc_stage_reg_n_0),\n .I2(prbs_tap_en_r_reg_0),\n .I3(Q[0]),\n .I4(Q[2]),\n .O(\\prbs_state_r[4]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h8080808480848084)) \n \\prbs_state_r[4]_i_8 \n (.I0(Q[2]),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(prbs_dqs_tap_limit_r),\n .I4(prbs_state_r178_out),\n .I5(prbs_found_1st_edge_r_reg_0),\n .O(\\prbs_state_r[4]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0FFCFAFA0F0C0)) \n \\prbs_state_r[4]_i_9 \n (.I0(\\prbs_state_r[4]_i_11_n_0 ),\n .I1(\\match_flag_or_reg[0]_0 ),\n .I2(Q[1]),\n .I3(num_samples_done_r),\n .I4(Q[0]),\n .I5(cnt_wait_state),\n .O(\\prbs_state_r[4]_i_9_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\prbs_state_r_reg[0] \n (.C(CLK),\n .CE(\\prbs_state_r[4]_i_2_n_0 ),\n .D(\\prbs_state_r[0]_i_1_n_0 ),\n .Q(Q[0]),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE #(\n .INIT(1'b0)) \n \\prbs_state_r_reg[1] \n (.C(CLK),\n .CE(\\prbs_state_r[4]_i_2_n_0 ),\n .D(\\prbs_state_r[1]_i_1_n_0 ),\n .Q(Q[1]),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE #(\n .INIT(1'b0)) \n \\prbs_state_r_reg[2] \n (.C(CLK),\n .CE(\\prbs_state_r[4]_i_2_n_0 ),\n .D(\\prbs_state_r_reg[2]_i_1_n_0 ),\n .Q(Q[2]),\n .R(rstdiv0_sync_r1_reg_rep__8));\n MUXF7 \\prbs_state_r_reg[2]_i_1 \n (.I0(\\prbs_state_r[2]_i_2_n_0 ),\n .I1(\\prbs_state_r[2]_i_3_n_0 ),\n .O(\\prbs_state_r_reg[2]_i_1_n_0 ),\n .S(Q[4]));\n FDRE #(\n .INIT(1'b0)) \n \\prbs_state_r_reg[3] \n (.C(CLK),\n .CE(\\prbs_state_r[4]_i_2_n_0 ),\n .D(\\prbs_state_r[3]_i_1_n_0 ),\n .Q(Q[3]),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE #(\n .INIT(1'b0)) \n \\prbs_state_r_reg[4] \n (.C(CLK),\n .CE(\\prbs_state_r[4]_i_2_n_0 ),\n .D(\\prbs_state_r[4]_i_3_n_0 ),\n .Q(Q[4]),\n .R(rstdiv0_sync_r1_reg_rep__8));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n prbs_tap_en_r_i_2\n (.I0(\\fine_pi_dec_cnt_reg_n_0_[2] ),\n .I1(\\fine_pi_dec_cnt_reg_n_0_[0] ),\n .I2(\\fine_pi_dec_cnt_reg_n_0_[1] ),\n .I3(\\fine_pi_dec_cnt_reg_n_0_[4] ),\n .I4(\\fine_pi_dec_cnt_reg_n_0_[3] ),\n .I5(\\fine_pi_dec_cnt_reg_n_0_[5] ),\n .O(prbs_tap_en_r_reg_0));\n FDRE #(\n .INIT(1'b0)) \n prbs_tap_en_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\prbs_state_r_reg[0]_2 ),\n .Q(pi_en_stg2_f_timing_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__8));\n LUT6 #(\n .INIT(64'h888888B8888B8B88)) \n prbs_tap_inc_r_i_2\n (.I0(prbs_tap_inc_r_i_3_n_0),\n .I1(Q[2]),\n .I2(Q[0]),\n .I3(Q[4]),\n .I4(Q[3]),\n .I5(Q[1]),\n .O(prbs_tap_en_r));\n LUT6 #(\n .INIT(64'h1454051504440515)) \n prbs_tap_inc_r_i_3\n (.I0(Q[4]),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(prbs_dqs_tap_limit_r),\n .I4(Q[3]),\n .I5(prbs_tap_en_r_reg_0),\n .O(prbs_tap_inc_r_i_3_n_0));\n FDRE #(\n .INIT(1'b0)) \n prbs_tap_inc_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\prbs_state_r_reg[0]_1 ),\n .Q(prbs_tap_inc_r),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE #(\n .INIT(1'b0)) \n rd_valid_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mux_rd_valid_r),\n .Q(rd_valid_r1),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n rd_valid_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rd_valid_r1),\n .Q(rd_valid_r2_reg_n_0),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h000000000000E5A5)) \n \\rd_victim_sel[0]_i_1 \n (.I0(\\rd_victim_sel_reg[2]_0 ),\n .I1(\\rd_victim_sel_reg[2]_1 ),\n .I2(\\rd_victim_sel_reg[2]_2 ),\n .I3(\\rd_victim_sel_reg[2]_3 ),\n .I4(num_samples_done_r),\n .I5(rstdiv0_sync_r1_reg_rep__22),\n .O(\\rd_victim_sel[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h000000000000DC9C)) \n \\rd_victim_sel[1]_i_1 \n (.I0(\\rd_victim_sel_reg[2]_0 ),\n .I1(\\rd_victim_sel_reg[2]_1 ),\n .I2(\\rd_victim_sel_reg[2]_2 ),\n .I3(\\rd_victim_sel_reg[2]_3 ),\n .I4(num_samples_done_r),\n .I5(rstdiv0_sync_r1_reg_rep__22),\n .O(\\rd_victim_sel[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h000000000000FF40)) \n \\rd_victim_sel[2]_i_1 \n (.I0(\\rd_victim_sel_reg[2]_0 ),\n .I1(\\rd_victim_sel_reg[2]_1 ),\n .I2(\\rd_victim_sel_reg[2]_2 ),\n .I3(\\rd_victim_sel_reg[2]_3 ),\n .I4(num_samples_done_r),\n .I5(rstdiv0_sync_r1_reg_rep__22),\n .O(\\rd_victim_sel[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rd_victim_sel_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_victim_sel[0]_i_1_n_0 ),\n .Q(\\rd_victim_sel_reg[2]_2 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rd_victim_sel_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_victim_sel[1]_i_1_n_0 ),\n .Q(\\rd_victim_sel_reg[2]_1 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rd_victim_sel_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_victim_sel[2]_i_1_n_0 ),\n .Q(\\rd_victim_sel_reg[2]_3 ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair68\" *) \n LUT2 #(\n .INIT(4'h4)) \n \\rdlvl_cpt_tap_cnt[0]_i_1 \n (.I0(\\calib_sel_reg[3] ),\n .I1(\\pi_counter_read_val_reg[5] [0]),\n .O(\\rdlvl_cpt_tap_cnt_reg[5]_1 [0]));\n LUT2 #(\n .INIT(4'h4)) \n \\rdlvl_cpt_tap_cnt[3]_i_1 \n (.I0(\\calib_sel_reg[3] ),\n .I1(\\pi_counter_read_val_reg[5] [2]),\n .O(\\rdlvl_cpt_tap_cnt_reg[5]_1 [1]));\n LUT2 #(\n .INIT(4'h4)) \n \\rdlvl_cpt_tap_cnt[5]_i_1 \n (.I0(\\calib_sel_reg[3] ),\n .I1(\\pi_counter_read_val_reg[5] [3]),\n .O(\\rdlvl_cpt_tap_cnt_reg[5]_1 [2]));\n FDRE #(\n .INIT(1'b0)) \n \\rdlvl_cpt_tap_cnt_reg[0] \n (.C(CLK),\n .CE(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .D(\\rdlvl_cpt_tap_cnt_reg[5]_1 [0]),\n .Q(rdlvl_cpt_tap_cnt[0]),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE #(\n .INIT(1'b0)) \n \\rdlvl_cpt_tap_cnt_reg[1] \n (.C(CLK),\n .CE(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .D(\\calib_sel_reg[3]_0 ),\n .Q(rdlvl_cpt_tap_cnt[1]),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE #(\n .INIT(1'b0)) \n \\rdlvl_cpt_tap_cnt_reg[2] \n (.C(CLK),\n .CE(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .D(\\calib_sel_reg[3]_1 ),\n .Q(rdlvl_cpt_tap_cnt[2]),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE #(\n .INIT(1'b0)) \n \\rdlvl_cpt_tap_cnt_reg[3] \n (.C(CLK),\n .CE(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .D(\\rdlvl_cpt_tap_cnt_reg[5]_1 [1]),\n .Q(rdlvl_cpt_tap_cnt[3]),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE #(\n .INIT(1'b0)) \n \\rdlvl_cpt_tap_cnt_reg[4] \n (.C(CLK),\n .CE(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .D(\\calib_sel_reg[3]_2 ),\n .Q(rdlvl_cpt_tap_cnt[4]),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE #(\n .INIT(1'b0)) \n \\rdlvl_cpt_tap_cnt_reg[5] \n (.C(CLK),\n .CE(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .D(\\rdlvl_cpt_tap_cnt_reg[5]_1 [2]),\n .Q(rdlvl_cpt_tap_cnt[5]),\n .R(rstdiv0_sync_r1_reg_rep__9));\n LUT5 #(\n .INIT(32'h80880080)) \n \\ref_bit[7]_i_1 \n (.I0(bit_cnt0),\n .I1(ref_right_edge125_in),\n .I2(\\ref_bit[7]_i_3_n_0 ),\n .I3(\\ref_right_edge[5]_i_1_n_0 ),\n .I4(\\ref_right_edge_reg_n_0_[5] ),\n .O(ref_right_edge));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\ref_bit[7]_i_3 \n (.I0(\\ref_bit[7]_i_6_n_0 ),\n .I1(\\ref_right_edge[3]_i_1_n_0 ),\n .I2(\\ref_right_edge_reg_n_0_[3] ),\n .I3(\\ref_right_edge[4]_i_1_n_0 ),\n .I4(\\ref_right_edge_reg_n_0_[4] ),\n .O(\\ref_bit[7]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\ref_bit[7]_i_4 \n (.I0(\\ref_bit_per_bit_reg_n_0_[3] ),\n .I1(\\ref_bit_per_bit_reg_n_0_[2] ),\n .I2(bit_cnt_reg__0[1]),\n .I3(\\ref_bit_per_bit_reg_n_0_[1] ),\n .I4(bit_cnt_reg__0[0]),\n .I5(\\ref_bit_per_bit_reg_n_0_[0] ),\n .O(\\ref_bit[7]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\ref_bit[7]_i_5 \n (.I0(\\ref_bit_per_bit_reg_n_0_[7] ),\n .I1(\\ref_bit_per_bit_reg_n_0_[6] ),\n .I2(bit_cnt_reg__0[1]),\n .I3(\\ref_bit_per_bit_reg_n_0_[5] ),\n .I4(bit_cnt_reg__0[0]),\n .I5(\\ref_bit_per_bit_reg_n_0_[4] ),\n .O(\\ref_bit[7]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hDF0DFFFF0000DF0D)) \n \\ref_bit[7]_i_6 \n (.I0(\\ref_right_edge[0]_i_1_n_0 ),\n .I1(\\ref_right_edge_reg_n_0_[0] ),\n .I2(\\ref_right_edge[1]_i_1_n_0 ),\n .I3(\\ref_right_edge_reg_n_0_[1] ),\n .I4(\\ref_right_edge[2]_i_1_n_0 ),\n .I5(\\ref_right_edge_reg_n_0_[2] ),\n .O(\\ref_bit[7]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000200000)) \n \\ref_bit_per_bit[7]_i_1 \n (.I0(ref_bit_per_bit0),\n .I1(\\ref_bit_per_bit[7]_i_2_n_0 ),\n .I2(Q[0]),\n .I3(\\ref_bit_per_bit[7]_i_3_n_0 ),\n .I4(Q[1]),\n .I5(Q[4]),\n .O(ref_bit_per_bit));\n (* SOFT_HLUTNM = \"soft_lutpair74\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\ref_bit_per_bit[7]_i_2 \n (.I0(\\stage_cnt_reg_n_0_[0] ),\n .I1(\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ),\n .O(\\ref_bit_per_bit[7]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair48\" *) \n LUT2 #(\n .INIT(4'h7)) \n \\ref_bit_per_bit[7]_i_3 \n (.I0(Q[2]),\n .I1(Q[3]),\n .O(\\ref_bit_per_bit[7]_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\ref_bit_per_bit_reg[0] \n (.C(CLK),\n .CE(ref_bit_per_bit),\n .D(D[0]),\n .Q(\\ref_bit_per_bit_reg_n_0_[0] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\ref_bit_per_bit_reg[1] \n (.C(CLK),\n .CE(ref_bit_per_bit),\n .D(D[1]),\n .Q(\\ref_bit_per_bit_reg_n_0_[1] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\ref_bit_per_bit_reg[2] \n (.C(CLK),\n .CE(ref_bit_per_bit),\n .D(D[2]),\n .Q(\\ref_bit_per_bit_reg_n_0_[2] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\ref_bit_per_bit_reg[3] \n (.C(CLK),\n .CE(ref_bit_per_bit),\n .D(D[3]),\n .Q(\\ref_bit_per_bit_reg_n_0_[3] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\ref_bit_per_bit_reg[4] \n (.C(CLK),\n .CE(ref_bit_per_bit),\n .D(D[4]),\n .Q(\\ref_bit_per_bit_reg_n_0_[4] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\ref_bit_per_bit_reg[5] \n (.C(CLK),\n .CE(ref_bit_per_bit),\n .D(D[5]),\n .Q(\\ref_bit_per_bit_reg_n_0_[5] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\ref_bit_per_bit_reg[6] \n (.C(CLK),\n .CE(ref_bit_per_bit),\n .D(D[6]),\n .Q(\\ref_bit_per_bit_reg_n_0_[6] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\ref_bit_per_bit_reg[7] \n (.C(CLK),\n .CE(ref_bit_per_bit),\n .D(D[7]),\n .Q(\\ref_bit_per_bit_reg_n_0_[7] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\ref_bit_reg[0] \n (.C(CLK),\n .CE(ref_right_edge),\n .D(bit_cnt_reg__0[0]),\n .Q(\\ref_bit_reg_n_0_[0] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\ref_bit_reg[1] \n (.C(CLK),\n .CE(ref_right_edge),\n .D(bit_cnt_reg__0[1]),\n .Q(\\ref_bit_reg_n_0_[1] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\ref_bit_reg[2] \n (.C(CLK),\n .CE(ref_right_edge),\n .D(bit_cnt_reg__0[2]),\n .Q(\\ref_bit_reg_n_0_[2] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\ref_bit_reg[3] \n (.C(CLK),\n .CE(ref_right_edge),\n .D(bit_cnt_reg__0[3]),\n .Q(ref_bit[3]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\ref_bit_reg[4] \n (.C(CLK),\n .CE(ref_right_edge),\n .D(bit_cnt_reg__0[4]),\n .Q(ref_bit[4]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\ref_bit_reg[5] \n (.C(CLK),\n .CE(ref_right_edge),\n .D(bit_cnt_reg__0[5]),\n .Q(ref_bit[5]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\ref_bit_reg[6] \n (.C(CLK),\n .CE(ref_right_edge),\n .D(bit_cnt_reg__0[6]),\n .Q(ref_bit[6]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\ref_bit_reg[7] \n (.C(CLK),\n .CE(ref_right_edge),\n .D(bit_cnt_reg__0[7]),\n .Q(ref_bit[7]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n MUXF7 \\ref_bit_reg[7]_i_2 \n (.I0(\\ref_bit[7]_i_4_n_0 ),\n .I1(\\ref_bit[7]_i_5_n_0 ),\n .O(ref_right_edge125_in),\n .S(bit_cnt_reg__0[2]));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\ref_right_edge[0]_i_1 \n (.I0(\\ref_right_edge[2]_i_2_n_0 ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_7 ),\n .I2(\\ref_right_edge_reg[0]_i_2_n_0 ),\n .I3(\\ref_right_edge_reg[5]_i_3_n_6 ),\n .I4(\\ref_right_edge[0]_i_3_n_0 ),\n .O(\\ref_right_edge[0]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hB8)) \n \\ref_right_edge[0]_i_3 \n (.I0(\\ref_right_edge[4]_i_9_n_0 ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_5 ),\n .I2(\\ref_right_edge[0]_i_4_n_0 ),\n .O(\\ref_right_edge[0]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\ref_right_edge[0]_i_4 \n (.I0(\\genblk8[2].right_edge_pb_reg_n_0_[16] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[32] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].right_edge_pb_reg_n_0_[0] ),\n .O(\\ref_right_edge[0]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\ref_right_edge[1]_i_1 \n (.I0(\\ref_right_edge[3]_i_2_n_0 ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_7 ),\n .I2(\\ref_right_edge_reg[1]_i_2_n_0 ),\n .I3(\\ref_right_edge_reg[5]_i_3_n_6 ),\n .I4(\\ref_right_edge[1]_i_3_n_0 ),\n .O(\\ref_right_edge[1]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hB8)) \n \\ref_right_edge[1]_i_3 \n (.I0(\\ref_right_edge[5]_i_15_n_0 ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_5 ),\n .I2(\\ref_right_edge[1]_i_6_n_0 ),\n .O(\\ref_right_edge[1]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\ref_right_edge[1]_i_4 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[21] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].right_edge_pb_reg_n_0_[37] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].right_edge_pb_reg_n_0_[5] ),\n .O(\\ref_right_edge[1]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\ref_right_edge[1]_i_5 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[29] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].right_edge_pb_reg_n_0_[45] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[2].right_edge_pb_reg_n_0_[13] ),\n .O(\\ref_right_edge[1]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\ref_right_edge[1]_i_6 \n (.I0(\\genblk8[2].right_edge_pb_reg_n_0_[17] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[33] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].right_edge_pb_reg_n_0_[1] ),\n .O(\\ref_right_edge[1]_i_6_n_0 ));\n LUT3 #(\n .INIT(8'hB8)) \n \\ref_right_edge[2]_i_1 \n (.I0(\\ref_right_edge[4]_i_4_n_0 ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_7 ),\n .I2(\\ref_right_edge[2]_i_2_n_0 ),\n .O(\\ref_right_edge[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\ref_right_edge[2]_i_2 \n (.I0(\\ref_right_edge[4]_i_7_n_0 ),\n .I1(\\ref_right_edge[4]_i_6_n_0 ),\n .I2(\\ref_right_edge_reg[5]_i_3_n_6 ),\n .I3(\\ref_right_edge[4]_i_5_n_0 ),\n .I4(\\ref_right_edge_reg[5]_i_3_n_5 ),\n .I5(\\ref_right_edge[2]_i_3_n_0 ),\n .O(\\ref_right_edge[2]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\ref_right_edge[2]_i_3 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[18] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[34] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].right_edge_pb_reg_n_0_[2] ),\n .O(\\ref_right_edge[2]_i_3_n_0 ));\n LUT3 #(\n .INIT(8'hB8)) \n \\ref_right_edge[3]_i_1 \n (.I0(\\ref_right_edge[5]_i_5_n_0 ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_7 ),\n .I2(\\ref_right_edge[3]_i_2_n_0 ),\n .O(\\ref_right_edge[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\ref_right_edge[3]_i_2 \n (.I0(\\ref_right_edge[5]_i_13_n_0 ),\n .I1(\\ref_right_edge[5]_i_12_n_0 ),\n .I2(\\ref_right_edge_reg[5]_i_3_n_6 ),\n .I3(\\ref_right_edge[5]_i_7_n_0 ),\n .I4(\\ref_right_edge_reg[5]_i_3_n_5 ),\n .I5(\\ref_right_edge[3]_i_3_n_0 ),\n .O(\\ref_right_edge[3]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\ref_right_edge[3]_i_3 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[19] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[35] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].right_edge_pb_reg_n_0_[3] ),\n .O(\\ref_right_edge[3]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\ref_right_edge[4]_i_1 \n (.I0(\\ref_right_edge[4]_i_2_n_0 ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_6 ),\n .I2(\\ref_right_edge_reg[4]_i_3_n_0 ),\n .I3(\\ref_right_edge_reg[5]_i_3_n_7 ),\n .I4(\\ref_right_edge[4]_i_4_n_0 ),\n .O(\\ref_right_edge[4]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\ref_right_edge[4]_i_10 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[28] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].right_edge_pb_reg_n_0_[44] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[2].right_edge_pb_reg_n_0_[12] ),\n .O(\\ref_right_edge[4]_i_10_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\ref_right_edge[4]_i_11 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[20] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].right_edge_pb_reg_n_0_[36] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].right_edge_pb_reg_n_0_[4] ),\n .O(\\ref_right_edge[4]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'h00E2FFFF00E20000)) \n \\ref_right_edge[4]_i_2 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[18] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[34] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\ref_right_edge_reg[5]_i_3_n_5 ),\n .I5(\\ref_right_edge[4]_i_5_n_0 ),\n .O(\\ref_right_edge[4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\ref_right_edge[4]_i_4 \n (.I0(\\ref_right_edge[4]_i_8_n_0 ),\n .I1(\\ref_right_edge[4]_i_9_n_0 ),\n .I2(\\ref_right_edge_reg[5]_i_3_n_6 ),\n .I3(\\ref_right_edge[4]_i_10_n_0 ),\n .I4(\\ref_right_edge_reg[5]_i_3_n_5 ),\n .I5(\\ref_right_edge[4]_i_11_n_0 ),\n .O(\\ref_right_edge[4]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\ref_right_edge[4]_i_5 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[26] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].right_edge_pb_reg_n_0_[42] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].right_edge_pb_reg_n_0_[10] ),\n .O(\\ref_right_edge[4]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\ref_right_edge[4]_i_6 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[22] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].right_edge_pb_reg_n_0_[38] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].right_edge_pb_reg_n_0_[6] ),\n .O(\\ref_right_edge[4]_i_6_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\ref_right_edge[4]_i_7 \n (.I0(\\genblk8[5].right_edge_pb_reg_n_0_[30] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].right_edge_pb_reg_n_0_[46] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[2].right_edge_pb_reg_n_0_[14] ),\n .O(\\ref_right_edge[4]_i_7_n_0 ));\n LUT4 #(\n .INIT(16'h00E2)) \n \\ref_right_edge[4]_i_8 \n (.I0(\\genblk8[2].right_edge_pb_reg_n_0_[16] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[32] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .O(\\ref_right_edge[4]_i_8_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\ref_right_edge[4]_i_9 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[24] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].right_edge_pb_reg_n_0_[40] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].right_edge_pb_reg_n_0_[8] ),\n .O(\\ref_right_edge[4]_i_9_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\ref_right_edge[5]_i_1 \n (.I0(\\ref_right_edge[5]_i_2_n_0 ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_6 ),\n .I2(\\ref_right_edge_reg[5]_i_4_n_0 ),\n .I3(\\ref_right_edge_reg[5]_i_3_n_7 ),\n .I4(\\ref_right_edge[5]_i_5_n_0 ),\n .O(\\ref_right_edge[5]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\ref_right_edge[5]_i_10 \n (.I0(bit_cnt_reg__0[1]),\n .O(\\ref_right_edge[5]_i_10_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\ref_right_edge[5]_i_11 \n (.I0(bit_cnt_reg__0[0]),\n .O(\\ref_right_edge[5]_i_11_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\ref_right_edge[5]_i_12 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[23] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].right_edge_pb_reg_n_0_[39] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].right_edge_pb_reg_n_0_[7] ),\n .O(\\ref_right_edge[5]_i_12_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\ref_right_edge[5]_i_13 \n (.I0(\\genblk8[5].right_edge_pb_reg_n_0_[31] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].right_edge_pb_reg_n_0_[47] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[2].right_edge_pb_reg_n_0_[15] ),\n .O(\\ref_right_edge[5]_i_13_n_0 ));\n LUT4 #(\n .INIT(16'h00E2)) \n \\ref_right_edge[5]_i_14 \n (.I0(\\genblk8[2].right_edge_pb_reg_n_0_[17] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[33] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .O(\\ref_right_edge[5]_i_14_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\ref_right_edge[5]_i_15 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[25] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].right_edge_pb_reg_n_0_[41] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].right_edge_pb_reg_n_0_[9] ),\n .O(\\ref_right_edge[5]_i_15_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\ref_right_edge[5]_i_16 \n (.I0(bit_cnt_reg__0[2]),\n .I1(bit_cnt_reg__0[4]),\n .O(\\ref_right_edge[5]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'h00E2FFFF00E20000)) \n \\ref_right_edge[5]_i_2 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[19] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[35] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\ref_right_edge_reg[5]_i_3_n_5 ),\n .I5(\\ref_right_edge[5]_i_7_n_0 ),\n .O(\\ref_right_edge[5]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\ref_right_edge[5]_i_5 \n (.I0(\\ref_right_edge[5]_i_14_n_0 ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_5 ),\n .I2(\\ref_right_edge[5]_i_15_n_0 ),\n .I3(\\ref_right_edge_reg[5]_i_3_n_6 ),\n .I4(\\ref_right_edge_reg[1]_i_2_n_0 ),\n .O(\\ref_right_edge[5]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\ref_right_edge[5]_i_7 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[27] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].right_edge_pb_reg_n_0_[43] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].right_edge_pb_reg_n_0_[11] ),\n .O(\\ref_right_edge[5]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\ref_right_edge[5]_i_8 \n (.I0(bit_cnt_reg__0[1]),\n .I1(bit_cnt_reg__0[3]),\n .O(\\ref_right_edge[5]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\ref_right_edge[5]_i_9 \n (.I0(bit_cnt_reg__0[0]),\n .I1(bit_cnt_reg__0[2]),\n .O(\\ref_right_edge[5]_i_9_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\ref_right_edge_reg[0] \n (.C(CLK),\n .CE(ref_right_edge),\n .D(\\ref_right_edge[0]_i_1_n_0 ),\n .Q(\\ref_right_edge_reg_n_0_[0] ),\n .S(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n MUXF7 \\ref_right_edge_reg[0]_i_2 \n (.I0(\\ref_right_edge[4]_i_11_n_0 ),\n .I1(\\ref_right_edge[4]_i_10_n_0 ),\n .O(\\ref_right_edge_reg[0]_i_2_n_0 ),\n .S(\\ref_right_edge_reg[5]_i_3_n_5 ));\n FDSE #(\n .INIT(1'b1)) \n \\ref_right_edge_reg[1] \n (.C(CLK),\n .CE(ref_right_edge),\n .D(\\ref_right_edge[1]_i_1_n_0 ),\n .Q(\\ref_right_edge_reg_n_0_[1] ),\n .S(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n MUXF7 \\ref_right_edge_reg[1]_i_2 \n (.I0(\\ref_right_edge[1]_i_4_n_0 ),\n .I1(\\ref_right_edge[1]_i_5_n_0 ),\n .O(\\ref_right_edge_reg[1]_i_2_n_0 ),\n .S(\\ref_right_edge_reg[5]_i_3_n_5 ));\n FDSE #(\n .INIT(1'b1)) \n \\ref_right_edge_reg[2] \n (.C(CLK),\n .CE(ref_right_edge),\n .D(\\ref_right_edge[2]_i_1_n_0 ),\n .Q(\\ref_right_edge_reg_n_0_[2] ),\n .S(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\ref_right_edge_reg[3] \n (.C(CLK),\n .CE(ref_right_edge),\n .D(\\ref_right_edge[3]_i_1_n_0 ),\n .Q(\\ref_right_edge_reg_n_0_[3] ),\n .S(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\ref_right_edge_reg[4] \n (.C(CLK),\n .CE(ref_right_edge),\n .D(\\ref_right_edge[4]_i_1_n_0 ),\n .Q(\\ref_right_edge_reg_n_0_[4] ),\n .S(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n MUXF7 \\ref_right_edge_reg[4]_i_3 \n (.I0(\\ref_right_edge[4]_i_6_n_0 ),\n .I1(\\ref_right_edge[4]_i_7_n_0 ),\n .O(\\ref_right_edge_reg[4]_i_3_n_0 ),\n .S(\\ref_right_edge_reg[5]_i_3_n_5 ));\n FDSE #(\n .INIT(1'b1)) \n \\ref_right_edge_reg[5] \n (.C(CLK),\n .CE(ref_right_edge),\n .D(\\ref_right_edge[5]_i_1_n_0 ),\n .Q(\\ref_right_edge_reg_n_0_[5] ),\n .S(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n CARRY4 \\ref_right_edge_reg[5]_i_3 \n (.CI(1'b0),\n .CO({\\ref_right_edge_reg[5]_i_3_n_0 ,\\ref_right_edge_reg[5]_i_3_n_1 ,\\ref_right_edge_reg[5]_i_3_n_2 ,\\ref_right_edge_reg[5]_i_3_n_3 }),\n .CYINIT(1'b0),\n .DI({bit_cnt_reg__0[1:0],1'b0,1'b1}),\n .O({\\ref_right_edge_reg[5]_i_3_n_4 ,\\ref_right_edge_reg[5]_i_3_n_5 ,\\ref_right_edge_reg[5]_i_3_n_6 ,\\ref_right_edge_reg[5]_i_3_n_7 }),\n .S({\\ref_right_edge[5]_i_8_n_0 ,\\ref_right_edge[5]_i_9_n_0 ,\\ref_right_edge[5]_i_10_n_0 ,\\ref_right_edge[5]_i_11_n_0 }));\n MUXF7 \\ref_right_edge_reg[5]_i_4 \n (.I0(\\ref_right_edge[5]_i_12_n_0 ),\n .I1(\\ref_right_edge[5]_i_13_n_0 ),\n .O(\\ref_right_edge_reg[5]_i_4_n_0 ),\n .S(\\ref_right_edge_reg[5]_i_3_n_5 ));\n CARRY4 \\ref_right_edge_reg[5]_i_6 \n (.CI(\\ref_right_edge_reg[5]_i_3_n_0 ),\n .CO(\\NLW_ref_right_edge_reg[5]_i_6_CO_UNCONNECTED [3:0]),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\NLW_ref_right_edge_reg[5]_i_6_O_UNCONNECTED [3:1],\\ref_right_edge_reg[5]_i_6_n_7 }),\n .S({1'b0,1'b0,1'b0,\\ref_right_edge[5]_i_16_n_0 }));\n LUT2 #(\n .INIT(4'hE)) \n reset_rd_addr_r1_i_1\n (.I0(reset_rd_addr),\n .I1(complex_ocal_reset_rd_addr),\n .O(reset_rd_addr0));\n FDRE #(\n .INIT(1'b0)) \n reset_rd_addr_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\prbs_state_r_reg[4]_2 ),\n .Q(reset_rd_addr),\n .R(rstdiv0_sync_r1_reg_rep__9));\n LUT6 #(\n .INIT(64'h00000000FFFFFFFD)) \n right_edge_found_i_2\n (.I0(right_edge_found_i_4_n_0),\n .I1(\\genblk8[3].right_edge_pb_reg[18]_0 ),\n .I2(\\genblk8[2].right_edge_pb_reg[12]_0 ),\n .I3(\\genblk8[1].right_edge_pb_reg[6]_0 ),\n .I4(\\genblk8[0].right_edge_pb_reg[0]_0 ),\n .I5(right_edge_found_reg_0),\n .O(right_edge_found_reg_1));\n (* SOFT_HLUTNM = \"soft_lutpair42\" *) \n LUT5 #(\n .INIT(32'h80000008)) \n right_edge_found_i_3\n (.I0(Q[1]),\n .I1(right_edge_found_i_5_n_0),\n .I2(Q[0]),\n .I3(Q[3]),\n .I4(Q[2]),\n .O(right_edge_found));\n LUT4 #(\n .INIT(16'h0001)) \n right_edge_found_i_4\n (.I0(\\genblk8[6].right_edge_pb_reg[36]_0 ),\n .I1(\\genblk8[7].right_edge_pb_reg[42]_0 ),\n .I2(\\genblk8[5].right_edge_pb_reg[30]_0 ),\n .I3(\\genblk8[4].right_edge_pb_reg[24]_0 ),\n .O(right_edge_found_i_4_n_0));\n LUT6 #(\n .INIT(64'h0FE00FE00FE000E0)) \n right_edge_found_i_5\n (.I0(right_edge_found_reg_1),\n .I1(no_err_win_detected_latch_reg_0),\n .I2(Q[3]),\n .I3(Q[4]),\n .I4(num_samples_done_r),\n .I5(\\match_flag_or_reg[0]_0 ),\n .O(right_edge_found_i_5_n_0));\n FDRE #(\n .INIT(1'b0)) \n right_edge_found_reg\n (.C(CLK),\n .CE(1'b1),\n .D(no_err_win_detected_reg_1),\n .Q(right_edge_found_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__7));\n LUT3 #(\n .INIT(8'hB8)) \n \\right_edge_ref[0]_i_1 \n (.I0(\\right_edge_ref[2]_i_2_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_7 ),\n .I2(\\right_edge_ref[0]_i_2_n_0 ),\n .O(\\right_edge_ref[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\right_edge_ref[0]_i_2 \n (.I0(\\right_edge_ref_reg[4]_i_10_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_6 ),\n .I2(\\right_edge_ref[4]_i_9_n_0 ),\n .I3(\\left_edge_ref_reg[5]_i_3_n_5 ),\n .I4(\\right_edge_ref[0]_i_3_n_0 ),\n .O(\\right_edge_ref[0]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair23\" *) \n LUT5 #(\n .INIT(32'h30BB3088)) \n \\right_edge_ref[0]_i_3 \n (.I0(\\genblk8[2].right_edge_pb_reg_n_0_[16] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[32] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].right_edge_pb_reg_n_0_[0] ),\n .O(\\right_edge_ref[0]_i_3_n_0 ));\n LUT3 #(\n .INIT(8'hB8)) \n \\right_edge_ref[1]_i_1 \n (.I0(\\right_edge_ref[3]_i_2_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_7 ),\n .I2(\\right_edge_ref[1]_i_2_n_0 ),\n .O(\\right_edge_ref[1]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\right_edge_ref[1]_i_2 \n (.I0(\\right_edge_ref_reg[5]_i_10_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_6 ),\n .I2(\\right_edge_ref[5]_i_9_n_0 ),\n .I3(\\left_edge_ref_reg[5]_i_3_n_5 ),\n .I4(\\right_edge_ref[1]_i_3_n_0 ),\n .O(\\right_edge_ref[1]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair22\" *) \n LUT5 #(\n .INIT(32'h30BB3088)) \n \\right_edge_ref[1]_i_3 \n (.I0(\\genblk8[2].right_edge_pb_reg_n_0_[17] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[33] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].right_edge_pb_reg_n_0_[1] ),\n .O(\\right_edge_ref[1]_i_3_n_0 ));\n LUT3 #(\n .INIT(8'hB8)) \n \\right_edge_ref[2]_i_1 \n (.I0(\\right_edge_ref[4]_i_4_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_7 ),\n .I2(\\right_edge_ref[2]_i_2_n_0 ),\n .O(\\right_edge_ref[2]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\right_edge_ref[2]_i_2 \n (.I0(\\right_edge_ref_reg[4]_i_3_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_6 ),\n .I2(\\right_edge_ref[4]_i_5_n_0 ),\n .I3(\\left_edge_ref_reg[5]_i_3_n_5 ),\n .I4(\\right_edge_ref[2]_i_3_n_0 ),\n .O(\\right_edge_ref[2]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\right_edge_ref[2]_i_3 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[18] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[34] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].right_edge_pb_reg_n_0_[2] ),\n .O(\\right_edge_ref[2]_i_3_n_0 ));\n LUT3 #(\n .INIT(8'hB8)) \n \\right_edge_ref[3]_i_1 \n (.I0(\\right_edge_ref[5]_i_4_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_7 ),\n .I2(\\right_edge_ref[3]_i_2_n_0 ),\n .O(\\right_edge_ref[3]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\right_edge_ref[3]_i_2 \n (.I0(\\right_edge_ref_reg[5]_i_3_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_6 ),\n .I2(\\right_edge_ref[5]_i_5_n_0 ),\n .I3(\\left_edge_ref_reg[5]_i_3_n_5 ),\n .I4(\\right_edge_ref[3]_i_3_n_0 ),\n .O(\\right_edge_ref[3]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\right_edge_ref[3]_i_3 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[19] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[35] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].right_edge_pb_reg_n_0_[3] ),\n .O(\\right_edge_ref[3]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\right_edge_ref[4]_i_1 \n (.I0(\\right_edge_ref[4]_i_2_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_6 ),\n .I2(\\right_edge_ref_reg[4]_i_3_n_0 ),\n .I3(\\left_edge_ref_reg[5]_i_3_n_7 ),\n .I4(\\right_edge_ref[4]_i_4_n_0 ),\n .O(\\right_edge_ref[4]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\right_edge_ref[4]_i_11 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[20] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].right_edge_pb_reg_n_0_[36] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].right_edge_pb_reg_n_0_[4] ),\n .O(\\right_edge_ref[4]_i_11_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\right_edge_ref[4]_i_12 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[28] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].right_edge_pb_reg_n_0_[44] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[2].right_edge_pb_reg_n_0_[12] ),\n .O(\\right_edge_ref[4]_i_12_n_0 ));\n LUT6 #(\n .INIT(64'h00E2FFFF00E20000)) \n \\right_edge_ref[4]_i_2 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[18] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[34] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\left_edge_ref_reg[5]_i_3_n_5 ),\n .I5(\\right_edge_ref[4]_i_5_n_0 ),\n .O(\\right_edge_ref[4]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\right_edge_ref[4]_i_4 \n (.I0(\\right_edge_ref[4]_i_8_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_5 ),\n .I2(\\right_edge_ref[4]_i_9_n_0 ),\n .I3(\\left_edge_ref_reg[5]_i_3_n_6 ),\n .I4(\\right_edge_ref_reg[4]_i_10_n_0 ),\n .O(\\right_edge_ref[4]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\right_edge_ref[4]_i_5 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[26] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].right_edge_pb_reg_n_0_[42] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].right_edge_pb_reg_n_0_[10] ),\n .O(\\right_edge_ref[4]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\right_edge_ref[4]_i_6 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[22] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].right_edge_pb_reg_n_0_[38] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].right_edge_pb_reg_n_0_[6] ),\n .O(\\right_edge_ref[4]_i_6_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\right_edge_ref[4]_i_7 \n (.I0(\\genblk8[5].right_edge_pb_reg_n_0_[30] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].right_edge_pb_reg_n_0_[46] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[2].right_edge_pb_reg_n_0_[14] ),\n .O(\\right_edge_ref[4]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair23\" *) \n LUT4 #(\n .INIT(16'h00E2)) \n \\right_edge_ref[4]_i_8 \n (.I0(\\genblk8[2].right_edge_pb_reg_n_0_[16] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[32] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .O(\\right_edge_ref[4]_i_8_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\right_edge_ref[4]_i_9 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[24] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].right_edge_pb_reg_n_0_[40] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].right_edge_pb_reg_n_0_[8] ),\n .O(\\right_edge_ref[4]_i_9_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\right_edge_ref[5]_i_1 \n (.I0(\\right_edge_ref[5]_i_2_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_6 ),\n .I2(\\right_edge_ref_reg[5]_i_3_n_0 ),\n .I3(\\left_edge_ref_reg[5]_i_3_n_7 ),\n .I4(\\right_edge_ref[5]_i_4_n_0 ),\n .O(\\right_edge_ref[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\right_edge_ref[5]_i_11 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[21] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].right_edge_pb_reg_n_0_[37] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].right_edge_pb_reg_n_0_[5] ),\n .O(\\right_edge_ref[5]_i_11_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\right_edge_ref[5]_i_12 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[29] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].right_edge_pb_reg_n_0_[45] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[2].right_edge_pb_reg_n_0_[13] ),\n .O(\\right_edge_ref[5]_i_12_n_0 ));\n LUT6 #(\n .INIT(64'h00E2FFFF00E20000)) \n \\right_edge_ref[5]_i_2 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[19] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[35] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\left_edge_ref_reg[5]_i_3_n_5 ),\n .I5(\\right_edge_ref[5]_i_5_n_0 ),\n .O(\\right_edge_ref[5]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\right_edge_ref[5]_i_4 \n (.I0(\\right_edge_ref[5]_i_8_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_5 ),\n .I2(\\right_edge_ref[5]_i_9_n_0 ),\n .I3(\\left_edge_ref_reg[5]_i_3_n_6 ),\n .I4(\\right_edge_ref_reg[5]_i_10_n_0 ),\n .O(\\right_edge_ref[5]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\right_edge_ref[5]_i_5 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[27] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].right_edge_pb_reg_n_0_[43] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].right_edge_pb_reg_n_0_[11] ),\n .O(\\right_edge_ref[5]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\right_edge_ref[5]_i_6 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[23] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].right_edge_pb_reg_n_0_[39] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].right_edge_pb_reg_n_0_[7] ),\n .O(\\right_edge_ref[5]_i_6_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\right_edge_ref[5]_i_7 \n (.I0(\\genblk8[5].right_edge_pb_reg_n_0_[31] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].right_edge_pb_reg_n_0_[47] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[2].right_edge_pb_reg_n_0_[15] ),\n .O(\\right_edge_ref[5]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair22\" *) \n LUT4 #(\n .INIT(16'h00E2)) \n \\right_edge_ref[5]_i_8 \n (.I0(\\genblk8[2].right_edge_pb_reg_n_0_[17] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[33] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .O(\\right_edge_ref[5]_i_8_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\right_edge_ref[5]_i_9 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[25] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].right_edge_pb_reg_n_0_[41] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].right_edge_pb_reg_n_0_[9] ),\n .O(\\right_edge_ref[5]_i_9_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\right_edge_ref_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\right_edge_ref[0]_i_1_n_0 ),\n .Q(right_edge_ref[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\right_edge_ref_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\right_edge_ref[1]_i_1_n_0 ),\n .Q(right_edge_ref[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\right_edge_ref_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\right_edge_ref[2]_i_1_n_0 ),\n .Q(right_edge_ref[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\right_edge_ref_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\right_edge_ref[3]_i_1_n_0 ),\n .Q(right_edge_ref[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\right_edge_ref_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\right_edge_ref[4]_i_1_n_0 ),\n .Q(right_edge_ref[4]),\n .R(1'b0));\n MUXF7 \\right_edge_ref_reg[4]_i_10 \n (.I0(\\right_edge_ref[4]_i_11_n_0 ),\n .I1(\\right_edge_ref[4]_i_12_n_0 ),\n .O(\\right_edge_ref_reg[4]_i_10_n_0 ),\n .S(\\left_edge_ref_reg[5]_i_3_n_5 ));\n MUXF7 \\right_edge_ref_reg[4]_i_3 \n (.I0(\\right_edge_ref[4]_i_6_n_0 ),\n .I1(\\right_edge_ref[4]_i_7_n_0 ),\n .O(\\right_edge_ref_reg[4]_i_3_n_0 ),\n .S(\\left_edge_ref_reg[5]_i_3_n_5 ));\n FDRE #(\n .INIT(1'b0)) \n \\right_edge_ref_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\right_edge_ref[5]_i_1_n_0 ),\n .Q(right_edge_ref[5]),\n .R(1'b0));\n MUXF7 \\right_edge_ref_reg[5]_i_10 \n (.I0(\\right_edge_ref[5]_i_11_n_0 ),\n .I1(\\right_edge_ref[5]_i_12_n_0 ),\n .O(\\right_edge_ref_reg[5]_i_10_n_0 ),\n .S(\\left_edge_ref_reg[5]_i_3_n_5 ));\n MUXF7 \\right_edge_ref_reg[5]_i_3 \n (.I0(\\right_edge_ref[5]_i_6_n_0 ),\n .I1(\\right_edge_ref[5]_i_7_n_0 ),\n .O(\\right_edge_ref_reg[5]_i_3_n_0 ),\n .S(\\left_edge_ref_reg[5]_i_3_n_5 ));\n LUT6 #(\n .INIT(64'h00000000FFFFFFFE)) \n \\samples_cnt_r[0]_i_1 \n (.I0(\\samples_cnt_r_reg_n_0_[11] ),\n .I1(\\samples_cnt_r_reg_n_0_[10] ),\n .I2(\\samples_cnt_r_reg_n_0_[1] ),\n .I3(\\samples_cnt_r[0]_i_2_n_0 ),\n .I4(\\samples_cnt_r[0]_i_3_n_0 ),\n .I5(\\samples_cnt_r_reg_n_0_[0] ),\n .O(\\samples_cnt_r[0]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\samples_cnt_r[0]_i_2 \n (.I0(\\samples_cnt_r_reg_n_0_[7] ),\n .I1(\\samples_cnt_r_reg_n_0_[6] ),\n .I2(\\samples_cnt_r_reg_n_0_[9] ),\n .I3(\\samples_cnt_r_reg_n_0_[8] ),\n .O(\\samples_cnt_r[0]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'hFFF7)) \n \\samples_cnt_r[0]_i_3 \n (.I0(\\samples_cnt_r_reg_n_0_[3] ),\n .I1(\\samples_cnt_r_reg_n_0_[2] ),\n .I2(\\samples_cnt_r_reg_n_0_[5] ),\n .I3(\\samples_cnt_r_reg_n_0_[4] ),\n .O(\\samples_cnt_r[0]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair81\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\samples_cnt_r[10]_i_1 \n (.I0(\\rd_victim_sel_reg[2]_0 ),\n .I1(data0[10]),\n .O(\\samples_cnt_r[10]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair84\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\samples_cnt_r[11]_i_2 \n (.I0(\\rd_victim_sel_reg[2]_0 ),\n .I1(data0[11]),\n .O(\\samples_cnt_r[11]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\samples_cnt_r[11]_i_3 \n (.I0(\\samples_cnt_r_reg_n_0_[11] ),\n .I1(\\samples_cnt_r_reg_n_0_[10] ),\n .I2(\\samples_cnt_r_reg_n_0_[1] ),\n .I3(\\samples_cnt_r[0]_i_2_n_0 ),\n .I4(\\samples_cnt_r[0]_i_3_n_0 ),\n .I5(\\samples_cnt_r_reg_n_0_[0] ),\n .O(\\rd_victim_sel_reg[2]_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samples_cnt_r[11]_i_5 \n (.I0(\\samples_cnt_r_reg_n_0_[11] ),\n .O(\\samples_cnt_r[11]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samples_cnt_r[11]_i_6 \n (.I0(\\samples_cnt_r_reg_n_0_[10] ),\n .O(\\samples_cnt_r[11]_i_6_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samples_cnt_r[11]_i_7 \n (.I0(\\samples_cnt_r_reg_n_0_[9] ),\n .O(\\samples_cnt_r[11]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair84\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\samples_cnt_r[1]_i_1 \n (.I0(\\rd_victim_sel_reg[2]_0 ),\n .I1(data0[1]),\n .O(\\samples_cnt_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair88\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\samples_cnt_r[2]_i_1 \n (.I0(\\rd_victim_sel_reg[2]_0 ),\n .I1(data0[2]),\n .O(\\samples_cnt_r[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair86\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\samples_cnt_r[3]_i_1 \n (.I0(\\rd_victim_sel_reg[2]_0 ),\n .I1(data0[3]),\n .O(\\samples_cnt_r[3]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\samples_cnt_r[4]_i_1 \n (.I0(\\rd_victim_sel_reg[2]_0 ),\n .I1(data0[4]),\n .O(\\samples_cnt_r[4]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samples_cnt_r[4]_i_3 \n (.I0(\\samples_cnt_r_reg_n_0_[4] ),\n .O(\\samples_cnt_r[4]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samples_cnt_r[4]_i_4 \n (.I0(\\samples_cnt_r_reg_n_0_[3] ),\n .O(\\samples_cnt_r[4]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samples_cnt_r[4]_i_5 \n (.I0(\\samples_cnt_r_reg_n_0_[2] ),\n .O(\\samples_cnt_r[4]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samples_cnt_r[4]_i_6 \n (.I0(\\samples_cnt_r_reg_n_0_[1] ),\n .O(\\samples_cnt_r[4]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair88\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\samples_cnt_r[5]_i_1 \n (.I0(\\rd_victim_sel_reg[2]_0 ),\n .I1(data0[5]),\n .O(\\samples_cnt_r[5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair83\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\samples_cnt_r[6]_i_1 \n (.I0(\\rd_victim_sel_reg[2]_0 ),\n .I1(data0[6]),\n .O(\\samples_cnt_r[6]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair86\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\samples_cnt_r[7]_i_1 \n (.I0(\\rd_victim_sel_reg[2]_0 ),\n .I1(data0[7]),\n .O(\\samples_cnt_r[7]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair83\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\samples_cnt_r[8]_i_1 \n (.I0(\\rd_victim_sel_reg[2]_0 ),\n .I1(data0[8]),\n .O(\\samples_cnt_r[8]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samples_cnt_r[8]_i_3 \n (.I0(\\samples_cnt_r_reg_n_0_[8] ),\n .O(\\samples_cnt_r[8]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samples_cnt_r[8]_i_4 \n (.I0(\\samples_cnt_r_reg_n_0_[7] ),\n .O(\\samples_cnt_r[8]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samples_cnt_r[8]_i_5 \n (.I0(\\samples_cnt_r_reg_n_0_[6] ),\n .O(\\samples_cnt_r[8]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samples_cnt_r[8]_i_6 \n (.I0(\\samples_cnt_r_reg_n_0_[5] ),\n .O(\\samples_cnt_r[8]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair81\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\samples_cnt_r[9]_i_1 \n (.I0(\\rd_victim_sel_reg[2]_0 ),\n .I1(data0[9]),\n .O(\\samples_cnt_r[9]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\samples_cnt_r_reg[0] \n (.C(CLK),\n .CE(E),\n .D(\\samples_cnt_r[0]_i_1_n_0 ),\n .Q(\\samples_cnt_r_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE #(\n .INIT(1'b0)) \n \\samples_cnt_r_reg[10] \n (.C(CLK),\n .CE(E),\n .D(\\samples_cnt_r[10]_i_1_n_0 ),\n .Q(\\samples_cnt_r_reg_n_0_[10] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE #(\n .INIT(1'b0)) \n \\samples_cnt_r_reg[11] \n (.C(CLK),\n .CE(E),\n .D(\\samples_cnt_r[11]_i_2_n_0 ),\n .Q(\\samples_cnt_r_reg_n_0_[11] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n CARRY4 \\samples_cnt_r_reg[11]_i_4 \n (.CI(\\samples_cnt_r_reg[8]_i_2_n_0 ),\n .CO({\\NLW_samples_cnt_r_reg[11]_i_4_CO_UNCONNECTED [3:2],\\samples_cnt_r_reg[11]_i_4_n_2 ,\\samples_cnt_r_reg[11]_i_4_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\NLW_samples_cnt_r_reg[11]_i_4_O_UNCONNECTED [3],data0[11:9]}),\n .S({1'b0,\\samples_cnt_r[11]_i_5_n_0 ,\\samples_cnt_r[11]_i_6_n_0 ,\\samples_cnt_r[11]_i_7_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\samples_cnt_r_reg[1] \n (.C(CLK),\n .CE(E),\n .D(\\samples_cnt_r[1]_i_1_n_0 ),\n .Q(\\samples_cnt_r_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE #(\n .INIT(1'b0)) \n \\samples_cnt_r_reg[2] \n (.C(CLK),\n .CE(E),\n .D(\\samples_cnt_r[2]_i_1_n_0 ),\n .Q(\\samples_cnt_r_reg_n_0_[2] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE #(\n .INIT(1'b0)) \n \\samples_cnt_r_reg[3] \n (.C(CLK),\n .CE(E),\n .D(\\samples_cnt_r[3]_i_1_n_0 ),\n .Q(\\samples_cnt_r_reg_n_0_[3] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE #(\n .INIT(1'b0)) \n \\samples_cnt_r_reg[4] \n (.C(CLK),\n .CE(E),\n .D(\\samples_cnt_r[4]_i_1_n_0 ),\n .Q(\\samples_cnt_r_reg_n_0_[4] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n CARRY4 \\samples_cnt_r_reg[4]_i_2 \n (.CI(1'b0),\n .CO({\\samples_cnt_r_reg[4]_i_2_n_0 ,\\samples_cnt_r_reg[4]_i_2_n_1 ,\\samples_cnt_r_reg[4]_i_2_n_2 ,\\samples_cnt_r_reg[4]_i_2_n_3 }),\n .CYINIT(\\samples_cnt_r_reg_n_0_[0] ),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(data0[4:1]),\n .S({\\samples_cnt_r[4]_i_3_n_0 ,\\samples_cnt_r[4]_i_4_n_0 ,\\samples_cnt_r[4]_i_5_n_0 ,\\samples_cnt_r[4]_i_6_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\samples_cnt_r_reg[5] \n (.C(CLK),\n .CE(E),\n .D(\\samples_cnt_r[5]_i_1_n_0 ),\n .Q(\\samples_cnt_r_reg_n_0_[5] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE #(\n .INIT(1'b0)) \n \\samples_cnt_r_reg[6] \n (.C(CLK),\n .CE(E),\n .D(\\samples_cnt_r[6]_i_1_n_0 ),\n .Q(\\samples_cnt_r_reg_n_0_[6] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE #(\n .INIT(1'b0)) \n \\samples_cnt_r_reg[7] \n (.C(CLK),\n .CE(E),\n .D(\\samples_cnt_r[7]_i_1_n_0 ),\n .Q(\\samples_cnt_r_reg_n_0_[7] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE #(\n .INIT(1'b0)) \n \\samples_cnt_r_reg[8] \n (.C(CLK),\n .CE(E),\n .D(\\samples_cnt_r[8]_i_1_n_0 ),\n .Q(\\samples_cnt_r_reg_n_0_[8] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n CARRY4 \\samples_cnt_r_reg[8]_i_2 \n (.CI(\\samples_cnt_r_reg[4]_i_2_n_0 ),\n .CO({\\samples_cnt_r_reg[8]_i_2_n_0 ,\\samples_cnt_r_reg[8]_i_2_n_1 ,\\samples_cnt_r_reg[8]_i_2_n_2 ,\\samples_cnt_r_reg[8]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(data0[8:5]),\n .S({\\samples_cnt_r[8]_i_3_n_0 ,\\samples_cnt_r[8]_i_4_n_0 ,\\samples_cnt_r[8]_i_5_n_0 ,\\samples_cnt_r[8]_i_6_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\samples_cnt_r_reg[9] \n (.C(CLK),\n .CE(E),\n .D(\\samples_cnt_r[9]_i_1_n_0 ),\n .Q(\\samples_cnt_r_reg_n_0_[9] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n (* SOFT_HLUTNM = \"soft_lutpair78\" *) \n LUT2 #(\n .INIT(4'h7)) \n \\smallest_right_edge[0]_i_1 \n (.I0(Q[0]),\n .I1(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .O(\\smallest_right_edge[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair78\" *) \n LUT3 #(\n .INIT(8'hD7)) \n \\smallest_right_edge[1]_i_1 \n (.I0(Q[0]),\n .I1(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .O(\\smallest_right_edge[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair32\" *) \n LUT4 #(\n .INIT(16'hDDD7)) \n \\smallest_right_edge[2]_i_1 \n (.I0(Q[0]),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\smallest_right_edge[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair32\" *) \n LUT5 #(\n .INIT(32'hDDDDDDD7)) \n \\smallest_right_edge[3]_i_1 \n (.I0(Q[0]),\n .I1(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .O(\\smallest_right_edge[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hDDDDDDDDDDDDDDD7)) \n \\smallest_right_edge[4]_i_1 \n (.I0(Q[0]),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\smallest_right_edge[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8000800000080308)) \n \\smallest_right_edge[5]_i_1 \n (.I0(\\smallest_right_edge[5]_i_3_n_0 ),\n .I1(Q[0]),\n .I2(Q[2]),\n .I3(Q[3]),\n .I4(Q[4]),\n .I5(Q[1]),\n .O(smallest_right_edge));\n LUT2 #(\n .INIT(4'h7)) \n \\smallest_right_edge[5]_i_2 \n (.I0(Q[0]),\n .I1(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\smallest_right_edge[5]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0F40004000400040)) \n \\smallest_right_edge[5]_i_3 \n (.I0(no_err_win_detected_latch_reg_0),\n .I1(right_edge_found_reg_1),\n .I2(Q[3]),\n .I3(Q[4]),\n .I4(\\smallest_right_edge[5]_i_4_n_0 ),\n .I5(prbs_state_r1),\n .O(\\smallest_right_edge[5]_i_3_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\smallest_right_edge[5]_i_4 \n (.I0(num_samples_done_r),\n .I1(right_edge_found_reg_0),\n .O(\\smallest_right_edge[5]_i_4_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\smallest_right_edge_reg[0] \n (.C(CLK),\n .CE(smallest_right_edge),\n .D(\\smallest_right_edge[0]_i_1_n_0 ),\n .Q(\\smallest_right_edge_reg_n_0_[0] ),\n .S(rstdiv0_sync_r1_reg_rep__7));\n FDSE #(\n .INIT(1'b1)) \n \\smallest_right_edge_reg[1] \n (.C(CLK),\n .CE(smallest_right_edge),\n .D(\\smallest_right_edge[1]_i_1_n_0 ),\n .Q(\\smallest_right_edge_reg_n_0_[1] ),\n .S(rstdiv0_sync_r1_reg_rep__7));\n FDSE #(\n .INIT(1'b1)) \n \\smallest_right_edge_reg[2] \n (.C(CLK),\n .CE(smallest_right_edge),\n .D(\\smallest_right_edge[2]_i_1_n_0 ),\n .Q(\\smallest_right_edge_reg_n_0_[2] ),\n .S(rstdiv0_sync_r1_reg_rep__7));\n FDSE #(\n .INIT(1'b1)) \n \\smallest_right_edge_reg[3] \n (.C(CLK),\n .CE(smallest_right_edge),\n .D(\\smallest_right_edge[3]_i_1_n_0 ),\n .Q(\\smallest_right_edge_reg_n_0_[3] ),\n .S(rstdiv0_sync_r1_reg_rep__7));\n FDSE #(\n .INIT(1'b1)) \n \\smallest_right_edge_reg[4] \n (.C(CLK),\n .CE(smallest_right_edge),\n .D(\\smallest_right_edge[4]_i_1_n_0 ),\n .Q(\\smallest_right_edge_reg_n_0_[4] ),\n .S(rstdiv0_sync_r1_reg_rep__7));\n FDSE #(\n .INIT(1'b1)) \n \\smallest_right_edge_reg[5] \n (.C(CLK),\n .CE(smallest_right_edge),\n .D(\\smallest_right_edge[5]_i_2_n_0 ),\n .Q(\\smallest_right_edge_reg_n_0_[5] ),\n .S(rstdiv0_sync_r1_reg_rep__7));\n (* SOFT_HLUTNM = \"soft_lutpair53\" *) \n LUT3 #(\n .INIT(8'h38)) \n \\stage_cnt[0]_i_1 \n (.I0(Q[4]),\n .I1(\\stage_cnt[1]_i_2_n_0 ),\n .I2(\\stage_cnt_reg_n_0_[0] ),\n .O(\\stage_cnt[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair53\" *) \n LUT4 #(\n .INIT(16'h2F80)) \n \\stage_cnt[1]_i_1 \n (.I0(Q[4]),\n .I1(\\stage_cnt_reg_n_0_[0] ),\n .I2(\\stage_cnt[1]_i_2_n_0 ),\n .I3(\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ),\n .O(\\stage_cnt[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000202020002)) \n \\stage_cnt[1]_i_2 \n (.I0(Q[0]),\n .I1(Q[2]),\n .I2(Q[3]),\n .I3(Q[4]),\n .I4(Q[1]),\n .I5(fine_delay_sel_reg_0),\n .O(\\stage_cnt[1]_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\stage_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\stage_cnt[0]_i_1_n_0 ),\n .Q(\\stage_cnt_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE #(\n .INIT(1'b0)) \n \\stage_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\stage_cnt[1]_i_1_n_0 ),\n .Q(\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ),\n .R(rstdiv0_sync_r1_reg_rep__7));\n LUT6 #(\n .INIT(64'h00000000AAAAEAAA)) \n \\victim_not_fixed.num_samples_done_r_i_1 \n (.I0(num_samples_done_r),\n .I1(\\rd_victim_sel_reg[2]_3 ),\n .I2(\\rd_victim_sel_reg[2]_2 ),\n .I3(\\rd_victim_sel_reg[2]_1 ),\n .I4(\\rd_victim_sel_reg[2]_0 ),\n .I5(\\victim_not_fixed.num_samples_done_r_i_2_n_0 ),\n .O(\\victim_not_fixed.num_samples_done_r_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAEBEEAAAAAAAA)) \n \\victim_not_fixed.num_samples_done_r_i_2 \n (.I0(rstdiv0_sync_r1_reg_rep__22),\n .I1(Q[2]),\n .I2(Q[3]),\n .I3(Q[1]),\n .I4(Q[4]),\n .I5(Q[0]),\n .O(\\victim_not_fixed.num_samples_done_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\victim_not_fixed.num_samples_done_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\victim_not_fixed.num_samples_done_r_i_1_n_0 ),\n .Q(num_samples_done_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair40\" *) \n LUT5 #(\n .INIT(32'h00050A12)) \n wait_state_cnt_en_r_i_1\n (.I0(Q[2]),\n .I1(Q[3]),\n .I2(Q[4]),\n .I3(Q[1]),\n .I4(Q[0]),\n .O(wait_state_cnt_en_r0));\n FDRE #(\n .INIT(1'b0)) \n wait_state_cnt_en_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wait_state_cnt_en_r0),\n .Q(wait_state_cnt_en_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair85\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\wait_state_cnt_r[0]_i_1 \n (.I0(wait_state_cnt_r_reg__0[0]),\n .O(p_0_in[0]));\n (* SOFT_HLUTNM = \"soft_lutpair85\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\wait_state_cnt_r[1]_i_1 \n (.I0(wait_state_cnt_r_reg__0[0]),\n .I1(wait_state_cnt_r_reg__0[1]),\n .O(p_0_in[1]));\n (* SOFT_HLUTNM = \"soft_lutpair66\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\wait_state_cnt_r[2]_i_1 \n (.I0(wait_state_cnt_r_reg__0[1]),\n .I1(wait_state_cnt_r_reg__0[0]),\n .I2(wait_state_cnt_r_reg__0[2]),\n .O(\\wait_state_cnt_r[2]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hD5555555)) \n \\wait_state_cnt_r[3]_i_1 \n (.I0(wait_state_cnt_en_r),\n .I1(wait_state_cnt_r_reg__0[3]),\n .I2(wait_state_cnt_r_reg__0[2]),\n .I3(wait_state_cnt_r_reg__0[0]),\n .I4(wait_state_cnt_r_reg__0[1]),\n .O(\\wait_state_cnt_r[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair66\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\wait_state_cnt_r[3]_i_2 \n (.I0(wait_state_cnt_r_reg__0[0]),\n .I1(wait_state_cnt_r_reg__0[1]),\n .I2(wait_state_cnt_r_reg__0[2]),\n .I3(wait_state_cnt_r_reg__0[3]),\n .O(p_0_in[3]));\n FDRE #(\n .INIT(1'b0)) \n \\wait_state_cnt_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in[0]),\n .Q(wait_state_cnt_r_reg__0[0]),\n .R(\\wait_state_cnt_r[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\wait_state_cnt_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in[1]),\n .Q(wait_state_cnt_r_reg__0[1]),\n .R(\\wait_state_cnt_r[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\wait_state_cnt_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wait_state_cnt_r[2]_i_1_n_0 ),\n .Q(wait_state_cnt_r_reg__0[2]),\n .R(\\wait_state_cnt_r[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\wait_state_cnt_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in[3]),\n .Q(wait_state_cnt_r_reg__0[3]),\n .R(\\wait_state_cnt_r[3]_i_1_n_0 ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_phy_rdlvl\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_phy_rdlvl\n (mpr_rdlvl_done_r1_reg_0,\n store_sr_r_reg_0,\n sr_valid_r1_reg_0,\n found_stable_eye_last_r_reg_0,\n found_first_edge_r_reg_0,\n mpr_rdlvl_start_r,\n mpr_valid_r1_reg_0,\n detect_edge_done_r,\n samp_edge_cnt0_en_r,\n \\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_0 ,\n p_0_in102_in,\n p_0_in99_in,\n p_0_in96_in,\n p_0_in93_in,\n p_0_in90_in,\n p_0_in87_in,\n p_0_in84_in,\n idelay_ce_int,\n idelay_inc_int,\n dqs_po_dec_done_r2,\n rdlvl_prech_req,\n pi_fine_dly_dec_done,\n pb_detect_edge_done_r,\n \\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0]_0 ,\n \\gen_track_left_edge[0].pb_found_stable_eye_r_reg ,\n \\gen_track_left_edge[1].pb_found_stable_eye_r_reg ,\n \\gen_track_left_edge[2].pb_found_stable_eye_r_reg ,\n \\gen_track_left_edge[3].pb_found_stable_eye_r_reg ,\n \\gen_track_left_edge[4].pb_found_stable_eye_r_reg ,\n \\gen_track_left_edge[5].pb_found_stable_eye_r_reg ,\n \\gen_track_left_edge[6].pb_found_stable_eye_r_reg ,\n \\gen_track_left_edge[7].pb_found_stable_eye_r_reg ,\n \\gen_track_left_edge[0].pb_found_edge_r_reg[0]_0 ,\n found_edge_r_reg_0,\n found_edge_r_reg_1,\n found_edge_r_reg_2,\n \\gen_track_left_edge[4].pb_found_edge_r_reg[4]_0 ,\n found_edge_r_reg_3,\n \\gen_track_left_edge[6].pb_found_edge_r_reg[6]_0 ,\n \\gen_track_left_edge[7].pb_found_edge_r_reg[7]_0 ,\n \\right_edge_taps_r_reg[0]_0 ,\n cal1_wait_r,\n found_stable_eye_last_r,\n mpr_rd_rise0_prev_r_reg_0,\n mpr_dec_cpt_r_reg_0,\n idel_adj_inc_reg_0,\n pi_en_stg2_f_timing_reg_0,\n mpr_last_byte_done,\n mpr_rnk_done,\n rdlvl_stg1_done_r1_reg,\n rdlvl_stg1_rank_done,\n rdlvl_last_byte_done,\n rdlvl_pi_incdec,\n \\cnt_idel_dec_cpt_r_reg[0]_0 ,\n \\pi_dqs_found_lanes_r1_reg[3] ,\n \\pi_dqs_found_lanes_r1_reg[3]_0 ,\n \\pi_dqs_found_lanes_r1_reg[3]_1 ,\n \\pi_dqs_found_lanes_r1_reg[2] ,\n \\pi_dqs_found_lanes_r1_reg[2]_0 ,\n \\pi_dqs_found_lanes_r1_reg[2]_1 ,\n \\pi_dqs_found_lanes_r1_reg[1] ,\n \\pi_dqs_found_lanes_r1_reg[1]_0 ,\n \\pi_dqs_found_lanes_r1_reg[1]_1 ,\n COUNTERLOADVAL,\n \\pi_dqs_found_lanes_r1_reg[0] ,\n \\pi_dqs_found_lanes_r1_reg[0]_0 ,\n \\pi_dqs_found_lanes_r1_reg[0]_1 ,\n \\stg1_wr_rd_cnt_reg[3] ,\n \\init_state_r_reg[0] ,\n \\init_state_r_reg[0]_0 ,\n \\init_state_r_reg[0]_1 ,\n out,\n idel_adj_inc_reg_1,\n \\wait_cnt_r_reg[0]_0 ,\n \\right_edge_taps_r_reg[0]_1 ,\n store_sr_req_r_reg_0,\n \\rdlvl_cpt_tap_cnt_reg[4] ,\n \\rdlvl_cpt_tap_cnt_reg[1] ,\n \\rdlvl_cpt_tap_cnt_reg[2] ,\n \\pi_rdval_cnt_reg[1]_0 ,\n \\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ,\n \\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ,\n \\pi_stg2_reg_l_timing_reg[0]_0 ,\n \\regl_dqs_cnt_r_reg[2]_0 ,\n \\regl_dqs_cnt_reg[0]_0 ,\n mpr_rd_rise0_prev_r_reg_1,\n \\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 ,\n cal1_cnt_cpt_r1,\n mpr_valid_r_reg_0,\n \\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 ,\n \\gen_track_left_edge[0].pb_found_edge_r_reg[0]_1 ,\n p_0_in16_in,\n \\gen_track_left_edge[1].pb_found_edge_r_reg[1]_0 ,\n p_0_in13_in,\n \\gen_track_left_edge[2].pb_found_edge_r_reg[2]_0 ,\n p_0_in10_in,\n \\gen_track_left_edge[3].pb_found_edge_r_reg[3]_0 ,\n p_0_in7_in,\n \\gen_track_left_edge[4].pb_found_edge_r_reg[4]_1 ,\n p_0_in4_in,\n \\gen_track_left_edge[5].pb_found_edge_r_reg[5]_0 ,\n p_0_in1_in,\n \\gen_track_left_edge[6].pb_found_edge_r_reg[6]_1 ,\n p_0_in,\n \\gen_track_left_edge[7].pb_found_edge_r_reg[7]_1 ,\n pb_found_stable_eye_r76_out,\n \\gen_track_left_edge[0].pb_found_stable_eye_r_reg[0]_0 ,\n pb_found_stable_eye_r72_out,\n \\gen_track_left_edge[1].pb_found_stable_eye_r_reg[1]_0 ,\n pb_found_stable_eye_r68_out,\n \\gen_track_left_edge[2].pb_found_stable_eye_r_reg[2]_0 ,\n pb_found_stable_eye_r64_out,\n \\gen_track_left_edge[3].pb_found_stable_eye_r_reg[3]_0 ,\n pb_found_stable_eye_r60_out,\n \\gen_track_left_edge[4].pb_found_stable_eye_r_reg[4]_0 ,\n pb_found_stable_eye_r56_out,\n \\gen_track_left_edge[5].pb_found_stable_eye_r_reg[5]_0 ,\n pb_found_stable_eye_r52_out,\n \\gen_track_left_edge[6].pb_found_stable_eye_r_reg[6]_0 ,\n \\gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_0 ,\n \\gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_1 ,\n \\right_edge_taps_r_reg[0]_2 ,\n idel_adj_inc_reg_2,\n pi_cnt_dec_reg_0,\n \\init_state_r_reg[1] ,\n prech_req,\n \\init_state_r_reg[2] ,\n \\init_state_r_reg[2]_0 ,\n \\init_state_r_reg[2]_1 ,\n \\init_state_r_reg[5] ,\n \\init_state_r_reg[0]_2 ,\n \\init_state_r_reg[3] ,\n \\init_state_r_reg[0]_3 ,\n \\init_state_r_reg[4] ,\n \\init_state_r_reg[0]_4 ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[254] ,\n \\init_state_r_reg[2]_2 ,\n D,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[2] ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 ,\n cmd_delay_start0,\n \\second_edge_taps_r_reg[5]_0 ,\n \\pi_dqs_found_lanes_r1_reg[1]_2 ,\n \\pi_dqs_found_lanes_r1_reg[2]_2 ,\n \\pi_dqs_found_lanes_r1_reg[3]_2 ,\n rdlvl_pi_incdec_reg_0,\n pi_stg2_rdlvl_cnt,\n mpr_last_byte_done_reg_0,\n mpr_rank_done_r_reg_0,\n rdlvl_pi_incdec_reg_1,\n \\idel_dec_cnt_reg[0]_0 ,\n rdlvl_stg1_done_int,\n rdlvl_rank_done_r_reg_0,\n mpr_rank_done_r_reg_1,\n mpr_dec_cpt_r_reg_1,\n CLK,\n rstdiv0_sync_r1_reg_rep__14,\n sr_valid_r108_out,\n \\rd_mux_sel_r_reg[1]_0 ,\n \\rd_mux_sel_r_reg[1]_1 ,\n \\rd_mux_sel_r_reg[1]_2 ,\n \\rd_mux_sel_r_reg[1]_3 ,\n \\rd_mux_sel_r_reg[1]_4 ,\n \\rd_mux_sel_r_reg[1]_5 ,\n \\rd_mux_sel_r_reg[1]_6 ,\n \\rd_mux_sel_r_reg[1]_7 ,\n \\rd_mux_sel_r_reg[1]_8 ,\n \\rd_mux_sel_r_reg[1]_9 ,\n \\rd_mux_sel_r_reg[1]_10 ,\n \\rd_mux_sel_r_reg[1]_11 ,\n \\rd_mux_sel_r_reg[1]_12 ,\n \\rd_mux_sel_r_reg[1]_13 ,\n \\rd_mux_sel_r_reg[1]_14 ,\n \\rd_mux_sel_r_reg[1]_15 ,\n \\rd_mux_sel_r_reg[1]_16 ,\n \\rd_mux_sel_r_reg[1]_17 ,\n \\rd_mux_sel_r_reg[1]_18 ,\n \\rd_mux_sel_r_reg[1]_19 ,\n \\rd_mux_sel_r_reg[1]_20 ,\n \\rd_mux_sel_r_reg[1]_21 ,\n \\rd_mux_sel_r_reg[1]_22 ,\n \\rd_mux_sel_r_reg[1]_23 ,\n \\rd_mux_sel_r_reg[1]_24 ,\n \\rd_mux_sel_r_reg[1]_25 ,\n \\rd_mux_sel_r_reg[1]_26 ,\n \\rd_mux_sel_r_reg[1]_27 ,\n \\rd_mux_sel_r_reg[1]_28 ,\n \\rd_mux_sel_r_reg[1]_29 ,\n \\rd_mux_sel_r_reg[1]_30 ,\n \\rd_mux_sel_r_reg[1]_31 ,\n \\rd_mux_sel_r_reg[1]_32 ,\n \\rd_mux_sel_r_reg[1]_33 ,\n \\rd_mux_sel_r_reg[1]_34 ,\n \\rd_mux_sel_r_reg[1]_35 ,\n \\rd_mux_sel_r_reg[1]_36 ,\n \\rd_mux_sel_r_reg[1]_37 ,\n \\rd_mux_sel_r_reg[1]_38 ,\n \\rd_mux_sel_r_reg[1]_39 ,\n \\rd_mux_sel_r_reg[1]_40 ,\n \\rd_mux_sel_r_reg[1]_41 ,\n \\rd_mux_sel_r_reg[1]_42 ,\n \\rd_mux_sel_r_reg[1]_43 ,\n \\rd_mux_sel_r_reg[1]_44 ,\n \\rd_mux_sel_r_reg[1]_45 ,\n \\rd_mux_sel_r_reg[1]_46 ,\n \\rd_mux_sel_r_reg[1]_47 ,\n \\rd_mux_sel_r_reg[1]_48 ,\n \\rd_mux_sel_r_reg[1]_49 ,\n \\rd_mux_sel_r_reg[1]_50 ,\n \\rd_mux_sel_r_reg[1]_51 ,\n \\rd_mux_sel_r_reg[1]_52 ,\n \\rd_mux_sel_r_reg[1]_53 ,\n \\rd_mux_sel_r_reg[1]_54 ,\n \\rd_mux_sel_r_reg[1]_55 ,\n \\rd_mux_sel_r_reg[1]_56 ,\n \\rd_mux_sel_r_reg[1]_57 ,\n \\rd_mux_sel_r_reg[1]_58 ,\n \\rd_mux_sel_r_reg[1]_59 ,\n \\rd_mux_sel_r_reg[1]_60 ,\n \\rd_mux_sel_r_reg[1]_61 ,\n \\rd_mux_sel_r_reg[1]_62 ,\n \\rd_mux_sel_r_reg[1]_63 ,\n mpr_rdlvl_start_reg,\n rdlvl_stg1_start_reg,\n phy_rddata_en_1,\n rstdiv0_sync_r1_reg_rep__13,\n dqs_po_dec_done,\n samp_cnt_done_r_reg_0,\n samp_cnt_done_r_reg_1,\n samp_cnt_done_r_reg_2,\n samp_cnt_done_r_reg_3,\n samp_cnt_done_r_reg_4,\n samp_cnt_done_r_reg_5,\n samp_cnt_done_r_reg_6,\n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg[0]_0 ,\n mpr_rdlvl_done_r_reg_0,\n store_sr_req_r_reg_1,\n \\gen_track_left_edge[0].pb_detect_edge_done_r_reg[0]_0 ,\n \\gen_track_left_edge[1].pb_detect_edge_done_r_reg[1]_0 ,\n \\gen_track_left_edge[2].pb_detect_edge_done_r_reg[2]_0 ,\n \\gen_track_left_edge[3].pb_detect_edge_done_r_reg[3]_0 ,\n \\gen_track_left_edge[4].pb_detect_edge_done_r_reg[4]_0 ,\n \\gen_track_left_edge[5].pb_detect_edge_done_r_reg[5]_0 ,\n \\gen_track_left_edge[6].pb_detect_edge_done_r_reg[6]_0 ,\n \\gen_track_left_edge[7].pb_detect_edge_done_r_reg[7]_0 ,\n \\gen_track_left_edge[0].pb_found_edge_r_reg[0]_2 ,\n \\gen_track_left_edge[1].pb_found_edge_r_reg[1]_1 ,\n \\gen_track_left_edge[2].pb_found_edge_r_reg[2]_1 ,\n \\gen_track_left_edge[3].pb_found_edge_r_reg[3]_1 ,\n \\gen_track_left_edge[4].pb_found_edge_r_reg[4]_2 ,\n \\gen_track_left_edge[5].pb_found_edge_r_reg[5]_1 ,\n \\gen_track_left_edge[6].pb_found_edge_r_reg[6]_2 ,\n \\gen_track_left_edge[7].pb_found_edge_r_reg[7]_2 ,\n found_edge_r_reg_4,\n found_stable_eye_r_reg_0,\n \\FSM_sequential_cal1_state_r_reg[4]_0 ,\n \\FSM_sequential_cal1_state_r_reg[3]_0 ,\n \\FSM_sequential_cal1_state_r_reg[2]_0 ,\n \\wait_cnt_r_reg[0]_1 ,\n \\FSM_sequential_cal1_state_r_reg[4]_1 ,\n \\FSM_sequential_cal1_state_r_reg[4]_2 ,\n mpr_rdlvl_done_r_reg_1,\n \\FSM_sequential_cal1_state_r_reg[4]_3 ,\n \\FSM_sequential_cal1_state_r_reg[4]_4 ,\n \\regl_dqs_cnt_reg[2]_0 ,\n \\FSM_sequential_cal1_state_r_reg[1]_0 ,\n SR,\n found_stable_eye_last_r_reg_1,\n \\gen_byte_sel_div1.calib_in_common_reg_0 ,\n prbs_pi_stg2_f_incdec,\n tempmon_pi_f_inc_r,\n Q,\n prbs_pi_stg2_f_en,\n tempmon_pi_f_en_r,\n calib_in_common,\n \\calib_sel_reg[3] ,\n \\gen_byte_sel_div1.calib_in_common_reg_1 ,\n \\gen_byte_sel_div1.calib_in_common_reg_2 ,\n \\gen_byte_sel_div1.calib_in_common_reg_3 ,\n rstdiv0_sync_r1_reg_rep__23,\n stg1_wr_done,\n wrcal_done_reg,\n dqs_found_done_r_reg,\n \\init_state_r_reg[1]_0 ,\n oclkdelay_calib_done_r_reg,\n \\one_rank.stg1_wr_done_reg ,\n cal1_state_r1535_out,\n rstdiv0_sync_r1_reg_rep__22,\n \\calib_sel_reg[3]_0 ,\n \\po_stg2_wrcal_cnt_reg[0] ,\n \\po_stg2_wrcal_cnt_reg[1] ,\n cal1_dq_idel_ce_reg_0,\n prech_done,\n \\pi_counter_read_val_reg[5] ,\n rstdiv0_sync_r1_reg_rep__20,\n \\init_state_r_reg[3]_0 ,\n wrcal_prech_req,\n complex_ocal_ref_req,\n prbs_rdlvl_prech_req_reg,\n dqs_found_prech_req,\n \\init_state_r_reg[5]_0 ,\n wrlvl_done_r1_reg,\n wrlvl_done_r1_reg_0,\n cnt_init_af_done_r,\n dqs_found_done_r_reg_0,\n prbs_rdlvl_done_reg_rep,\n wrlvl_byte_redo,\n wrlvl_final_mux,\n mem_init_done_r,\n prbs_rdlvl_done_reg_rep_0,\n \\num_refresh_reg[1] ,\n prbs_last_byte_done_r,\n wrlvl_final_mux_reg,\n prbs_rdlvl_done_reg_rep_1,\n oclkdelay_center_calib_done_r_reg,\n wrlvl_done_r1,\n wrlvl_byte_redo_reg,\n \\dout_o_reg[6] ,\n first_wrcal_pat_r,\n \\dout_o_reg[6]_0 ,\n prbs_rdlvl_done_reg,\n wr_level_done_reg,\n \\prbs_dqs_cnt_r_reg[2] ,\n \\po_stg2_wrcal_cnt_reg[2] ,\n rdlvl_stg1_start_reg_0,\n E,\n samp_edge_cnt0_en_r_reg_0,\n pi_cnt_dec_reg_1,\n rstdiv0_sync_r1_reg_rep__2);\n output mpr_rdlvl_done_r1_reg_0;\n output store_sr_r_reg_0;\n output sr_valid_r1_reg_0;\n output found_stable_eye_last_r_reg_0;\n output found_first_edge_r_reg_0;\n output mpr_rdlvl_start_r;\n output mpr_valid_r1_reg_0;\n output detect_edge_done_r;\n output samp_edge_cnt0_en_r;\n output \\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_0 ;\n output p_0_in102_in;\n output p_0_in99_in;\n output p_0_in96_in;\n output p_0_in93_in;\n output p_0_in90_in;\n output p_0_in87_in;\n output p_0_in84_in;\n output idelay_ce_int;\n output idelay_inc_int;\n output dqs_po_dec_done_r2;\n output rdlvl_prech_req;\n output pi_fine_dly_dec_done;\n output [7:0]pb_detect_edge_done_r;\n output \\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0]_0 ;\n output \\gen_track_left_edge[0].pb_found_stable_eye_r_reg ;\n output \\gen_track_left_edge[1].pb_found_stable_eye_r_reg ;\n output \\gen_track_left_edge[2].pb_found_stable_eye_r_reg ;\n output \\gen_track_left_edge[3].pb_found_stable_eye_r_reg ;\n output \\gen_track_left_edge[4].pb_found_stable_eye_r_reg ;\n output \\gen_track_left_edge[5].pb_found_stable_eye_r_reg ;\n output \\gen_track_left_edge[6].pb_found_stable_eye_r_reg ;\n output \\gen_track_left_edge[7].pb_found_stable_eye_r_reg ;\n output \\gen_track_left_edge[0].pb_found_edge_r_reg[0]_0 ;\n output found_edge_r_reg_0;\n output found_edge_r_reg_1;\n output found_edge_r_reg_2;\n output \\gen_track_left_edge[4].pb_found_edge_r_reg[4]_0 ;\n output found_edge_r_reg_3;\n output \\gen_track_left_edge[6].pb_found_edge_r_reg[6]_0 ;\n output \\gen_track_left_edge[7].pb_found_edge_r_reg[7]_0 ;\n output \\right_edge_taps_r_reg[0]_0 ;\n output cal1_wait_r;\n output found_stable_eye_last_r;\n output mpr_rd_rise0_prev_r_reg_0;\n output mpr_dec_cpt_r_reg_0;\n output idel_adj_inc_reg_0;\n output pi_en_stg2_f_timing_reg_0;\n output mpr_last_byte_done;\n output mpr_rnk_done;\n output rdlvl_stg1_done_r1_reg;\n output rdlvl_stg1_rank_done;\n output rdlvl_last_byte_done;\n output rdlvl_pi_incdec;\n output \\cnt_idel_dec_cpt_r_reg[0]_0 ;\n output \\pi_dqs_found_lanes_r1_reg[3] ;\n output \\pi_dqs_found_lanes_r1_reg[3]_0 ;\n output \\pi_dqs_found_lanes_r1_reg[3]_1 ;\n output \\pi_dqs_found_lanes_r1_reg[2] ;\n output \\pi_dqs_found_lanes_r1_reg[2]_0 ;\n output \\pi_dqs_found_lanes_r1_reg[2]_1 ;\n output \\pi_dqs_found_lanes_r1_reg[1] ;\n output \\pi_dqs_found_lanes_r1_reg[1]_0 ;\n output \\pi_dqs_found_lanes_r1_reg[1]_1 ;\n output [5:0]COUNTERLOADVAL;\n output \\pi_dqs_found_lanes_r1_reg[0] ;\n output \\pi_dqs_found_lanes_r1_reg[0]_0 ;\n output \\pi_dqs_found_lanes_r1_reg[0]_1 ;\n output \\stg1_wr_rd_cnt_reg[3] ;\n output \\init_state_r_reg[0] ;\n output \\init_state_r_reg[0]_0 ;\n output \\init_state_r_reg[0]_1 ;\n output [4:0]out;\n output idel_adj_inc_reg_1;\n output [1:0]\\wait_cnt_r_reg[0]_0 ;\n output \\right_edge_taps_r_reg[0]_1 ;\n output store_sr_req_r_reg_0;\n output \\rdlvl_cpt_tap_cnt_reg[4] ;\n output \\rdlvl_cpt_tap_cnt_reg[1] ;\n output \\rdlvl_cpt_tap_cnt_reg[2] ;\n output \\pi_rdval_cnt_reg[1]_0 ;\n output \\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ;\n output \\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ;\n output \\pi_stg2_reg_l_timing_reg[0]_0 ;\n output [0:0]\\regl_dqs_cnt_r_reg[2]_0 ;\n output \\regl_dqs_cnt_reg[0]_0 ;\n output mpr_rd_rise0_prev_r_reg_1;\n output [1:0]\\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 ;\n output cal1_cnt_cpt_r1;\n output mpr_valid_r_reg_0;\n output \\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 ;\n output \\gen_track_left_edge[0].pb_found_edge_r_reg[0]_1 ;\n output p_0_in16_in;\n output \\gen_track_left_edge[1].pb_found_edge_r_reg[1]_0 ;\n output p_0_in13_in;\n output \\gen_track_left_edge[2].pb_found_edge_r_reg[2]_0 ;\n output p_0_in10_in;\n output \\gen_track_left_edge[3].pb_found_edge_r_reg[3]_0 ;\n output p_0_in7_in;\n output \\gen_track_left_edge[4].pb_found_edge_r_reg[4]_1 ;\n output p_0_in4_in;\n output \\gen_track_left_edge[5].pb_found_edge_r_reg[5]_0 ;\n output p_0_in1_in;\n output \\gen_track_left_edge[6].pb_found_edge_r_reg[6]_1 ;\n output p_0_in;\n output \\gen_track_left_edge[7].pb_found_edge_r_reg[7]_1 ;\n output pb_found_stable_eye_r76_out;\n output \\gen_track_left_edge[0].pb_found_stable_eye_r_reg[0]_0 ;\n output pb_found_stable_eye_r72_out;\n output \\gen_track_left_edge[1].pb_found_stable_eye_r_reg[1]_0 ;\n output pb_found_stable_eye_r68_out;\n output \\gen_track_left_edge[2].pb_found_stable_eye_r_reg[2]_0 ;\n output pb_found_stable_eye_r64_out;\n output \\gen_track_left_edge[3].pb_found_stable_eye_r_reg[3]_0 ;\n output pb_found_stable_eye_r60_out;\n output \\gen_track_left_edge[4].pb_found_stable_eye_r_reg[4]_0 ;\n output pb_found_stable_eye_r56_out;\n output \\gen_track_left_edge[5].pb_found_stable_eye_r_reg[5]_0 ;\n output pb_found_stable_eye_r52_out;\n output \\gen_track_left_edge[6].pb_found_stable_eye_r_reg[6]_0 ;\n output \\gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_0 ;\n output \\gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_1 ;\n output \\right_edge_taps_r_reg[0]_2 ;\n output idel_adj_inc_reg_2;\n output pi_cnt_dec_reg_0;\n output \\init_state_r_reg[1] ;\n output prech_req;\n output \\init_state_r_reg[2] ;\n output \\init_state_r_reg[2]_0 ;\n output \\init_state_r_reg[2]_1 ;\n output \\init_state_r_reg[5] ;\n output \\init_state_r_reg[0]_2 ;\n output \\init_state_r_reg[3] ;\n output \\init_state_r_reg[0]_3 ;\n output \\init_state_r_reg[4] ;\n output \\init_state_r_reg[0]_4 ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[254] ;\n output \\init_state_r_reg[2]_2 ;\n output [1:0]D;\n output \\gen_byte_sel_div1.calib_in_common_reg ;\n output \\gen_byte_sel_div1.byte_sel_cnt_reg[2] ;\n output \\gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 ;\n output cmd_delay_start0;\n output \\second_edge_taps_r_reg[5]_0 ;\n output [5:0]\\pi_dqs_found_lanes_r1_reg[1]_2 ;\n output [5:0]\\pi_dqs_found_lanes_r1_reg[2]_2 ;\n output [5:0]\\pi_dqs_found_lanes_r1_reg[3]_2 ;\n output rdlvl_pi_incdec_reg_0;\n output [1:0]pi_stg2_rdlvl_cnt;\n output mpr_last_byte_done_reg_0;\n output mpr_rank_done_r_reg_0;\n output rdlvl_pi_incdec_reg_1;\n output \\idel_dec_cnt_reg[0]_0 ;\n output rdlvl_stg1_done_int;\n output rdlvl_rank_done_r_reg_0;\n output mpr_rank_done_r_reg_1;\n output mpr_dec_cpt_r_reg_1;\n input CLK;\n input [1:0]rstdiv0_sync_r1_reg_rep__14;\n input sr_valid_r108_out;\n input \\rd_mux_sel_r_reg[1]_0 ;\n input \\rd_mux_sel_r_reg[1]_1 ;\n input \\rd_mux_sel_r_reg[1]_2 ;\n input \\rd_mux_sel_r_reg[1]_3 ;\n input \\rd_mux_sel_r_reg[1]_4 ;\n input \\rd_mux_sel_r_reg[1]_5 ;\n input \\rd_mux_sel_r_reg[1]_6 ;\n input \\rd_mux_sel_r_reg[1]_7 ;\n input \\rd_mux_sel_r_reg[1]_8 ;\n input \\rd_mux_sel_r_reg[1]_9 ;\n input \\rd_mux_sel_r_reg[1]_10 ;\n input \\rd_mux_sel_r_reg[1]_11 ;\n input \\rd_mux_sel_r_reg[1]_12 ;\n input \\rd_mux_sel_r_reg[1]_13 ;\n input \\rd_mux_sel_r_reg[1]_14 ;\n input \\rd_mux_sel_r_reg[1]_15 ;\n input \\rd_mux_sel_r_reg[1]_16 ;\n input \\rd_mux_sel_r_reg[1]_17 ;\n input \\rd_mux_sel_r_reg[1]_18 ;\n input \\rd_mux_sel_r_reg[1]_19 ;\n input \\rd_mux_sel_r_reg[1]_20 ;\n input \\rd_mux_sel_r_reg[1]_21 ;\n input \\rd_mux_sel_r_reg[1]_22 ;\n input \\rd_mux_sel_r_reg[1]_23 ;\n input \\rd_mux_sel_r_reg[1]_24 ;\n input \\rd_mux_sel_r_reg[1]_25 ;\n input \\rd_mux_sel_r_reg[1]_26 ;\n input \\rd_mux_sel_r_reg[1]_27 ;\n input \\rd_mux_sel_r_reg[1]_28 ;\n input \\rd_mux_sel_r_reg[1]_29 ;\n input \\rd_mux_sel_r_reg[1]_30 ;\n input \\rd_mux_sel_r_reg[1]_31 ;\n input \\rd_mux_sel_r_reg[1]_32 ;\n input \\rd_mux_sel_r_reg[1]_33 ;\n input \\rd_mux_sel_r_reg[1]_34 ;\n input \\rd_mux_sel_r_reg[1]_35 ;\n input \\rd_mux_sel_r_reg[1]_36 ;\n input \\rd_mux_sel_r_reg[1]_37 ;\n input \\rd_mux_sel_r_reg[1]_38 ;\n input \\rd_mux_sel_r_reg[1]_39 ;\n input \\rd_mux_sel_r_reg[1]_40 ;\n input \\rd_mux_sel_r_reg[1]_41 ;\n input \\rd_mux_sel_r_reg[1]_42 ;\n input \\rd_mux_sel_r_reg[1]_43 ;\n input \\rd_mux_sel_r_reg[1]_44 ;\n input \\rd_mux_sel_r_reg[1]_45 ;\n input \\rd_mux_sel_r_reg[1]_46 ;\n input \\rd_mux_sel_r_reg[1]_47 ;\n input \\rd_mux_sel_r_reg[1]_48 ;\n input \\rd_mux_sel_r_reg[1]_49 ;\n input \\rd_mux_sel_r_reg[1]_50 ;\n input \\rd_mux_sel_r_reg[1]_51 ;\n input \\rd_mux_sel_r_reg[1]_52 ;\n input \\rd_mux_sel_r_reg[1]_53 ;\n input \\rd_mux_sel_r_reg[1]_54 ;\n input \\rd_mux_sel_r_reg[1]_55 ;\n input \\rd_mux_sel_r_reg[1]_56 ;\n input \\rd_mux_sel_r_reg[1]_57 ;\n input \\rd_mux_sel_r_reg[1]_58 ;\n input \\rd_mux_sel_r_reg[1]_59 ;\n input \\rd_mux_sel_r_reg[1]_60 ;\n input \\rd_mux_sel_r_reg[1]_61 ;\n input \\rd_mux_sel_r_reg[1]_62 ;\n input \\rd_mux_sel_r_reg[1]_63 ;\n input mpr_rdlvl_start_reg;\n input rdlvl_stg1_start_reg;\n input phy_rddata_en_1;\n input rstdiv0_sync_r1_reg_rep__13;\n input dqs_po_dec_done;\n input samp_cnt_done_r_reg_0;\n input samp_cnt_done_r_reg_1;\n input samp_cnt_done_r_reg_2;\n input samp_cnt_done_r_reg_3;\n input samp_cnt_done_r_reg_4;\n input samp_cnt_done_r_reg_5;\n input samp_cnt_done_r_reg_6;\n input \\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg[0]_0 ;\n input mpr_rdlvl_done_r_reg_0;\n input store_sr_req_r_reg_1;\n input \\gen_track_left_edge[0].pb_detect_edge_done_r_reg[0]_0 ;\n input \\gen_track_left_edge[1].pb_detect_edge_done_r_reg[1]_0 ;\n input \\gen_track_left_edge[2].pb_detect_edge_done_r_reg[2]_0 ;\n input \\gen_track_left_edge[3].pb_detect_edge_done_r_reg[3]_0 ;\n input \\gen_track_left_edge[4].pb_detect_edge_done_r_reg[4]_0 ;\n input \\gen_track_left_edge[5].pb_detect_edge_done_r_reg[5]_0 ;\n input \\gen_track_left_edge[6].pb_detect_edge_done_r_reg[6]_0 ;\n input \\gen_track_left_edge[7].pb_detect_edge_done_r_reg[7]_0 ;\n input \\gen_track_left_edge[0].pb_found_edge_r_reg[0]_2 ;\n input \\gen_track_left_edge[1].pb_found_edge_r_reg[1]_1 ;\n input \\gen_track_left_edge[2].pb_found_edge_r_reg[2]_1 ;\n input \\gen_track_left_edge[3].pb_found_edge_r_reg[3]_1 ;\n input \\gen_track_left_edge[4].pb_found_edge_r_reg[4]_2 ;\n input \\gen_track_left_edge[5].pb_found_edge_r_reg[5]_1 ;\n input \\gen_track_left_edge[6].pb_found_edge_r_reg[6]_2 ;\n input \\gen_track_left_edge[7].pb_found_edge_r_reg[7]_2 ;\n input found_edge_r_reg_4;\n input found_stable_eye_r_reg_0;\n input \\FSM_sequential_cal1_state_r_reg[4]_0 ;\n input \\FSM_sequential_cal1_state_r_reg[3]_0 ;\n input \\FSM_sequential_cal1_state_r_reg[2]_0 ;\n input \\wait_cnt_r_reg[0]_1 ;\n input \\FSM_sequential_cal1_state_r_reg[4]_1 ;\n input \\FSM_sequential_cal1_state_r_reg[4]_2 ;\n input mpr_rdlvl_done_r_reg_1;\n input \\FSM_sequential_cal1_state_r_reg[4]_3 ;\n input \\FSM_sequential_cal1_state_r_reg[4]_4 ;\n input \\regl_dqs_cnt_reg[2]_0 ;\n input \\FSM_sequential_cal1_state_r_reg[1]_0 ;\n input [0:0]SR;\n input found_stable_eye_last_r_reg_1;\n input \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n input prbs_pi_stg2_f_incdec;\n input tempmon_pi_f_inc_r;\n input [0:0]Q;\n input prbs_pi_stg2_f_en;\n input tempmon_pi_f_en_r;\n input calib_in_common;\n input [2:0]\\calib_sel_reg[3] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n input \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n input \\gen_byte_sel_div1.calib_in_common_reg_3 ;\n input rstdiv0_sync_r1_reg_rep__23;\n input stg1_wr_done;\n input wrcal_done_reg;\n input dqs_found_done_r_reg;\n input [1:0]\\init_state_r_reg[1]_0 ;\n input oclkdelay_calib_done_r_reg;\n input \\one_rank.stg1_wr_done_reg ;\n input cal1_state_r1535_out;\n input rstdiv0_sync_r1_reg_rep__22;\n input [2:0]\\calib_sel_reg[3]_0 ;\n input \\po_stg2_wrcal_cnt_reg[0] ;\n input [0:0]\\po_stg2_wrcal_cnt_reg[1] ;\n input cal1_dq_idel_ce_reg_0;\n input prech_done;\n input [4:0]\\pi_counter_read_val_reg[5] ;\n input rstdiv0_sync_r1_reg_rep__20;\n input \\init_state_r_reg[3]_0 ;\n input wrcal_prech_req;\n input complex_ocal_ref_req;\n input prbs_rdlvl_prech_req_reg;\n input dqs_found_prech_req;\n input \\init_state_r_reg[5]_0 ;\n input wrlvl_done_r1_reg;\n input wrlvl_done_r1_reg_0;\n input cnt_init_af_done_r;\n input dqs_found_done_r_reg_0;\n input prbs_rdlvl_done_reg_rep;\n input wrlvl_byte_redo;\n input wrlvl_final_mux;\n input mem_init_done_r;\n input prbs_rdlvl_done_reg_rep_0;\n input \\num_refresh_reg[1] ;\n input prbs_last_byte_done_r;\n input wrlvl_final_mux_reg;\n input prbs_rdlvl_done_reg_rep_1;\n input oclkdelay_center_calib_done_r_reg;\n input wrlvl_done_r1;\n input wrlvl_byte_redo_reg;\n input \\dout_o_reg[6] ;\n input first_wrcal_pat_r;\n input \\dout_o_reg[6]_0 ;\n input prbs_rdlvl_done_reg;\n input wr_level_done_reg;\n input \\prbs_dqs_cnt_r_reg[2] ;\n input \\po_stg2_wrcal_cnt_reg[2] ;\n input [0:0]rdlvl_stg1_start_reg_0;\n input [0:0]E;\n input samp_edge_cnt0_en_r_reg_0;\n input [0:0]pi_cnt_dec_reg_1;\n input rstdiv0_sync_r1_reg_rep__2;\n\n wire CLK;\n wire [5:0]COUNTERLOADVAL;\n wire [1:0]D;\n wire [0:0]E;\n wire \\FSM_sequential_cal1_state_r[0]_i_11_n_0 ;\n wire \\FSM_sequential_cal1_state_r[0]_i_12_n_0 ;\n wire \\FSM_sequential_cal1_state_r[0]_i_14_n_0 ;\n wire \\FSM_sequential_cal1_state_r[0]_i_1_n_0 ;\n wire \\FSM_sequential_cal1_state_r[0]_i_2_n_0 ;\n wire \\FSM_sequential_cal1_state_r[0]_i_3_n_0 ;\n wire \\FSM_sequential_cal1_state_r[0]_i_4_n_0 ;\n wire \\FSM_sequential_cal1_state_r[0]_i_5_n_0 ;\n wire \\FSM_sequential_cal1_state_r[0]_i_6_n_0 ;\n wire \\FSM_sequential_cal1_state_r[0]_i_7_n_0 ;\n wire \\FSM_sequential_cal1_state_r[0]_i_8_n_0 ;\n wire \\FSM_sequential_cal1_state_r[0]_i_9_n_0 ;\n wire \\FSM_sequential_cal1_state_r[1]_i_10_n_0 ;\n wire \\FSM_sequential_cal1_state_r[1]_i_11_n_0 ;\n wire \\FSM_sequential_cal1_state_r[1]_i_12_n_0 ;\n wire \\FSM_sequential_cal1_state_r[1]_i_13_n_0 ;\n wire \\FSM_sequential_cal1_state_r[1]_i_1_n_0 ;\n wire \\FSM_sequential_cal1_state_r[1]_i_2_n_0 ;\n wire \\FSM_sequential_cal1_state_r[1]_i_3_n_0 ;\n wire \\FSM_sequential_cal1_state_r[1]_i_4_n_0 ;\n wire \\FSM_sequential_cal1_state_r[1]_i_6_n_0 ;\n wire \\FSM_sequential_cal1_state_r[1]_i_7_n_0 ;\n wire \\FSM_sequential_cal1_state_r[1]_i_8_n_0 ;\n wire \\FSM_sequential_cal1_state_r[1]_i_9_n_0 ;\n wire \\FSM_sequential_cal1_state_r[2]_i_1_n_0 ;\n wire \\FSM_sequential_cal1_state_r[2]_i_3_n_0 ;\n wire \\FSM_sequential_cal1_state_r[2]_i_4_n_0 ;\n wire \\FSM_sequential_cal1_state_r[2]_i_5_n_0 ;\n wire \\FSM_sequential_cal1_state_r[3]_i_1_n_0 ;\n wire \\FSM_sequential_cal1_state_r[3]_i_2_n_0 ;\n wire \\FSM_sequential_cal1_state_r[3]_i_3_n_0 ;\n wire \\FSM_sequential_cal1_state_r[4]_i_1_n_0 ;\n wire \\FSM_sequential_cal1_state_r[4]_i_2_n_0 ;\n wire \\FSM_sequential_cal1_state_r[4]_i_3_n_0 ;\n wire \\FSM_sequential_cal1_state_r[4]_i_4_n_0 ;\n wire \\FSM_sequential_cal1_state_r[4]_i_5_n_0 ;\n wire \\FSM_sequential_cal1_state_r[4]_i_6_n_0 ;\n wire \\FSM_sequential_cal1_state_r[4]_i_7_n_0 ;\n wire \\FSM_sequential_cal1_state_r[5]_i_11_n_0 ;\n wire \\FSM_sequential_cal1_state_r[5]_i_1_n_0 ;\n wire \\FSM_sequential_cal1_state_r[5]_i_2_n_0 ;\n wire \\FSM_sequential_cal1_state_r[5]_i_3_n_0 ;\n wire \\FSM_sequential_cal1_state_r[5]_i_4_n_0 ;\n wire \\FSM_sequential_cal1_state_r[5]_i_5_n_0 ;\n wire \\FSM_sequential_cal1_state_r[5]_i_6_n_0 ;\n wire \\FSM_sequential_cal1_state_r[5]_i_7_n_0 ;\n wire \\FSM_sequential_cal1_state_r[5]_i_8_n_0 ;\n wire \\FSM_sequential_cal1_state_r[5]_i_9_n_0 ;\n wire \\FSM_sequential_cal1_state_r_reg[1]_0 ;\n wire \\FSM_sequential_cal1_state_r_reg[1]_i_5_n_0 ;\n wire \\FSM_sequential_cal1_state_r_reg[2]_0 ;\n wire \\FSM_sequential_cal1_state_r_reg[2]_i_2_n_0 ;\n wire \\FSM_sequential_cal1_state_r_reg[3]_0 ;\n wire \\FSM_sequential_cal1_state_r_reg[4]_0 ;\n wire \\FSM_sequential_cal1_state_r_reg[4]_1 ;\n wire \\FSM_sequential_cal1_state_r_reg[4]_2 ;\n wire \\FSM_sequential_cal1_state_r_reg[4]_3 ;\n wire \\FSM_sequential_cal1_state_r_reg[4]_4 ;\n wire [0:0]Q;\n wire [0:0]SR;\n wire cal1_cnt_cpt_r1;\n wire \\cal1_cnt_cpt_r[0]_i_1_n_0 ;\n wire \\cal1_cnt_cpt_r[1]_i_2_n_0 ;\n wire \\cal1_cnt_cpt_r[1]_i_3_n_0 ;\n wire \\cal1_cnt_cpt_r[1]_i_4_n_0 ;\n wire \\cal1_cnt_cpt_r[1]_i_5_n_0 ;\n wire \\cal1_cnt_cpt_r_reg_n_0_[0] ;\n wire \\cal1_cnt_cpt_r_reg_n_0_[1] ;\n wire cal1_dlyce_cpt_r;\n wire cal1_dlyce_cpt_r_i_2_n_0;\n wire cal1_dlyce_cpt_r_reg_n_0;\n wire cal1_dlyinc_cpt_r;\n wire cal1_dlyinc_cpt_r_i_2_n_0;\n wire cal1_dlyinc_cpt_r_reg_n_0;\n wire cal1_dq_idel_ce;\n wire cal1_dq_idel_ce_reg_0;\n wire cal1_dq_idel_inc;\n wire cal1_prech_req_r;\n wire cal1_prech_req_r_reg_n_0;\n (* RTL_KEEP = \"yes\" *) wire [5:5]cal1_state_r;\n wire cal1_state_r1;\n wire cal1_state_r1533_out;\n wire cal1_state_r1535_out;\n wire \\cal1_state_r1[0]_i_1_n_0 ;\n wire \\cal1_state_r1[1]_i_1_n_0 ;\n wire \\cal1_state_r1[2]_i_1_n_0 ;\n wire \\cal1_state_r1[3]_i_1_n_0 ;\n wire \\cal1_state_r1[4]_i_1_n_0 ;\n wire \\cal1_state_r1[5]_i_1_n_0 ;\n wire \\cal1_state_r1_reg_n_0_[0] ;\n wire \\cal1_state_r1_reg_n_0_[1] ;\n wire \\cal1_state_r1_reg_n_0_[2] ;\n wire \\cal1_state_r1_reg_n_0_[3] ;\n wire \\cal1_state_r1_reg_n_0_[4] ;\n wire \\cal1_state_r1_reg_n_0_[5] ;\n wire cal1_state_r2;\n wire cal1_wait_cnt_en_r;\n wire cal1_wait_cnt_en_r0;\n wire \\cal1_wait_cnt_r[4]_i_1_n_0 ;\n wire [4:0]cal1_wait_cnt_r_reg__0;\n wire cal1_wait_r;\n wire cal1_wait_r_i_1_n_0;\n wire calib_in_common;\n wire [2:0]\\calib_sel_reg[3] ;\n wire [2:0]\\calib_sel_reg[3]_0 ;\n wire cmd_delay_start0;\n wire [5:0]cnt_idel_dec_cpt_r;\n wire [5:1]cnt_idel_dec_cpt_r2;\n wire \\cnt_idel_dec_cpt_r[0]_i_2_n_0 ;\n wire \\cnt_idel_dec_cpt_r[0]_i_3_n_0 ;\n wire \\cnt_idel_dec_cpt_r[1]_i_10_n_0 ;\n wire \\cnt_idel_dec_cpt_r[1]_i_11_n_0 ;\n wire \\cnt_idel_dec_cpt_r[1]_i_12_n_0 ;\n wire \\cnt_idel_dec_cpt_r[1]_i_13_n_0 ;\n wire \\cnt_idel_dec_cpt_r[1]_i_14_n_0 ;\n wire \\cnt_idel_dec_cpt_r[1]_i_3_n_0 ;\n wire \\cnt_idel_dec_cpt_r[1]_i_4_n_0 ;\n wire \\cnt_idel_dec_cpt_r[1]_i_5_n_0 ;\n wire \\cnt_idel_dec_cpt_r[1]_i_6_n_0 ;\n wire \\cnt_idel_dec_cpt_r[1]_i_7_n_0 ;\n wire \\cnt_idel_dec_cpt_r[1]_i_8_n_0 ;\n wire \\cnt_idel_dec_cpt_r[2]_i_2_n_0 ;\n wire \\cnt_idel_dec_cpt_r[2]_i_3_n_0 ;\n wire \\cnt_idel_dec_cpt_r[2]_i_4_n_0 ;\n wire \\cnt_idel_dec_cpt_r[2]_i_5_n_0 ;\n wire \\cnt_idel_dec_cpt_r[3]_i_2_n_0 ;\n wire \\cnt_idel_dec_cpt_r[3]_i_3_n_0 ;\n wire \\cnt_idel_dec_cpt_r[3]_i_4_n_0 ;\n wire \\cnt_idel_dec_cpt_r[3]_i_5_n_0 ;\n wire \\cnt_idel_dec_cpt_r[4]_i_3_n_0 ;\n wire \\cnt_idel_dec_cpt_r[4]_i_4_n_0 ;\n wire \\cnt_idel_dec_cpt_r[4]_i_5_n_0 ;\n wire \\cnt_idel_dec_cpt_r[4]_i_7_n_0 ;\n wire \\cnt_idel_dec_cpt_r[4]_i_8_n_0 ;\n wire \\cnt_idel_dec_cpt_r[4]_i_9_n_0 ;\n wire \\cnt_idel_dec_cpt_r[5]_i_10_n_0 ;\n wire \\cnt_idel_dec_cpt_r[5]_i_11_n_0 ;\n wire \\cnt_idel_dec_cpt_r[5]_i_12_n_0 ;\n wire \\cnt_idel_dec_cpt_r[5]_i_13_n_0 ;\n wire \\cnt_idel_dec_cpt_r[5]_i_1_n_0 ;\n wire \\cnt_idel_dec_cpt_r[5]_i_3_n_0 ;\n wire \\cnt_idel_dec_cpt_r[5]_i_5_n_0 ;\n wire \\cnt_idel_dec_cpt_r[5]_i_6_n_0 ;\n wire \\cnt_idel_dec_cpt_r[5]_i_7_n_0 ;\n wire \\cnt_idel_dec_cpt_r[5]_i_8_n_0 ;\n wire \\cnt_idel_dec_cpt_r_reg[0]_0 ;\n wire \\cnt_idel_dec_cpt_r_reg[1]_i_2_n_0 ;\n wire \\cnt_idel_dec_cpt_r_reg[1]_i_2_n_1 ;\n wire \\cnt_idel_dec_cpt_r_reg[1]_i_2_n_2 ;\n wire \\cnt_idel_dec_cpt_r_reg[1]_i_2_n_3 ;\n wire \\cnt_idel_dec_cpt_r_reg[1]_i_9_n_0 ;\n wire \\cnt_idel_dec_cpt_r_reg[1]_i_9_n_1 ;\n wire \\cnt_idel_dec_cpt_r_reg[1]_i_9_n_2 ;\n wire \\cnt_idel_dec_cpt_r_reg[1]_i_9_n_3 ;\n wire \\cnt_idel_dec_cpt_r_reg[1]_i_9_n_4 ;\n wire \\cnt_idel_dec_cpt_r_reg[1]_i_9_n_5 ;\n wire \\cnt_idel_dec_cpt_r_reg[1]_i_9_n_6 ;\n wire \\cnt_idel_dec_cpt_r_reg[4]_i_2_n_0 ;\n wire \\cnt_idel_dec_cpt_r_reg[4]_i_6_n_3 ;\n wire \\cnt_idel_dec_cpt_r_reg[4]_i_6_n_6 ;\n wire \\cnt_idel_dec_cpt_r_reg[4]_i_6_n_7 ;\n wire \\cnt_idel_dec_cpt_r_reg[5]_i_9_n_1 ;\n wire \\cnt_idel_dec_cpt_r_reg[5]_i_9_n_3 ;\n wire \\cnt_idel_dec_cpt_r_reg_n_0_[0] ;\n wire \\cnt_idel_dec_cpt_r_reg_n_0_[1] ;\n wire \\cnt_idel_dec_cpt_r_reg_n_0_[2] ;\n wire \\cnt_idel_dec_cpt_r_reg_n_0_[3] ;\n wire \\cnt_idel_dec_cpt_r_reg_n_0_[4] ;\n wire \\cnt_idel_dec_cpt_r_reg_n_0_[5] ;\n wire cnt_init_af_done_r;\n wire [3:0]cnt_shift_r_reg__0;\n wire complex_ocal_ref_req;\n wire detect_edge_done_r;\n wire detect_edge_done_r_i_1_n_0;\n wire detect_edge_done_r_i_2_n_0;\n wire [3:0]done_cnt;\n wire done_cnt1;\n wire \\done_cnt[0]_i_1_n_0 ;\n wire \\done_cnt[1]_i_1_n_0 ;\n wire \\done_cnt[2]_i_1_n_0 ;\n wire \\done_cnt[3]_i_1_n_0 ;\n wire \\done_cnt[3]_i_3_n_0 ;\n wire \\done_cnt[3]_i_4_n_0 ;\n wire \\dout_o_reg[6] ;\n wire \\dout_o_reg[6]_0 ;\n wire dqs_found_done_r_reg;\n wire dqs_found_done_r_reg_0;\n wire dqs_found_prech_req;\n wire dqs_po_dec_done;\n wire dqs_po_dec_done_r1;\n wire dqs_po_dec_done_r2;\n wire fine_dly_dec_done_r1;\n wire fine_dly_dec_done_r1_i_1_n_0;\n wire fine_dly_dec_done_r1_i_2_n_0;\n wire fine_dly_dec_done_r1_i_3_n_0;\n wire fine_dly_dec_done_r2;\n wire \\first_edge_taps_r[5]_i_1_n_0 ;\n wire \\first_edge_taps_r[5]_i_2_n_0 ;\n wire \\first_edge_taps_r_reg_n_0_[0] ;\n wire \\first_edge_taps_r_reg_n_0_[1] ;\n wire \\first_edge_taps_r_reg_n_0_[2] ;\n wire \\first_edge_taps_r_reg_n_0_[3] ;\n wire \\first_edge_taps_r_reg_n_0_[4] ;\n wire \\first_edge_taps_r_reg_n_0_[5] ;\n wire first_wrcal_pat_r;\n wire found_edge_r_i_1_n_0;\n wire found_edge_r_i_2_n_0;\n wire found_edge_r_reg_0;\n wire found_edge_r_reg_1;\n wire found_edge_r_reg_2;\n wire found_edge_r_reg_3;\n wire found_edge_r_reg_4;\n wire found_first_edge_r_reg_0;\n wire found_stable_eye_last_r;\n wire found_stable_eye_last_r_reg_0;\n wire found_stable_eye_last_r_reg_1;\n wire found_stable_eye_r_i_1_n_0;\n wire found_stable_eye_r_i_2_n_0;\n wire found_stable_eye_r_reg_0;\n wire \\gen_byte_sel_div1.byte_sel_cnt[2]_i_5_n_0 ;\n wire \\gen_byte_sel_div1.byte_sel_cnt[2]_i_8_n_0 ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[2] ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_3 ;\n wire \\gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ;\n wire \\gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ;\n wire \\gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ;\n wire \\gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3] ;\n wire \\gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ;\n wire \\gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ;\n wire \\gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ;\n wire \\gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7] ;\n wire \\gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0]_140 ;\n wire \\gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0]_132 ;\n wire \\gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0]_164 ;\n wire \\gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0]_172 ;\n wire \\gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0]_180 ;\n wire \\gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0]_148 ;\n wire \\gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0]_156 ;\n wire \\gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0]_188 ;\n wire \\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0]_68 ;\n wire \\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0]_108 ;\n wire \\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0]_124 ;\n wire \\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0]_100 ;\n wire \\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0]_92 ;\n wire \\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0]_76 ;\n wire \\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0]_84 ;\n wire \\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0]_116 ;\n wire \\gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1]_141 ;\n wire \\gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1]_133 ;\n wire \\gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1]_165 ;\n wire \\gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1]_173 ;\n wire \\gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1]_181 ;\n wire \\gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1]_149 ;\n wire \\gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1]_157 ;\n wire \\gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1]_189 ;\n wire \\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1]_69 ;\n wire \\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1]_109 ;\n wire \\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1]_125 ;\n wire \\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1]_101 ;\n wire \\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1]_93 ;\n wire \\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1]_77 ;\n wire \\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1]_85 ;\n wire \\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1]_117 ;\n wire \\gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2]_142 ;\n wire \\gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2]_134 ;\n wire \\gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2]_166 ;\n wire \\gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2]_174 ;\n wire \\gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2]_182 ;\n wire \\gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2]_150 ;\n wire \\gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2]_158 ;\n wire \\gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2]_190 ;\n wire \\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2]_70 ;\n wire \\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2]_110 ;\n wire \\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2]_126 ;\n wire \\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2]_102 ;\n wire \\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2]_94 ;\n wire \\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2]_78 ;\n wire \\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2]_86 ;\n wire \\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2]_118 ;\n wire \\gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3]_143 ;\n wire \\gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3]_135 ;\n wire \\gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3]_167 ;\n wire \\gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3]_175 ;\n wire \\gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3]_183 ;\n wire \\gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3]_151 ;\n wire \\gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3]_159 ;\n wire \\gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3]_191 ;\n wire \\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3]_71 ;\n wire \\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3]_111 ;\n wire \\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3]_127 ;\n wire \\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3]_103 ;\n wire \\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3]_95 ;\n wire \\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3]_79 ;\n wire \\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3]_87 ;\n wire \\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3]_119 ;\n wire \\gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4]_144 ;\n wire \\gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4]_136 ;\n wire \\gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4]_168 ;\n wire \\gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4]_176 ;\n wire \\gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4]_184 ;\n wire \\gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4]_152 ;\n wire \\gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4]_160 ;\n wire \\gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4]_192 ;\n wire \\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4]_72 ;\n wire \\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4]_112 ;\n wire \\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4]_128 ;\n wire \\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4]_104 ;\n wire \\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4]_96 ;\n wire \\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4]_80 ;\n wire \\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4]_88 ;\n wire \\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4]_120 ;\n wire \\gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5]_145 ;\n wire \\gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5]_137 ;\n wire \\gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5]_169 ;\n wire \\gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5]_177 ;\n wire \\gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5]_185 ;\n wire \\gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5]_153 ;\n wire \\gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5]_161 ;\n wire \\gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5]_193 ;\n wire \\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5]_73 ;\n wire \\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5]_113 ;\n wire \\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5]_129 ;\n wire \\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5]_105 ;\n wire \\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5]_97 ;\n wire \\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5]_81 ;\n wire \\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5]_89 ;\n wire \\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5]_121 ;\n wire \\gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6]_146 ;\n wire \\gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6]_138 ;\n wire \\gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6]_170 ;\n wire \\gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6]_178 ;\n wire \\gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6]_186 ;\n wire \\gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6]_154 ;\n wire \\gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6]_162 ;\n wire \\gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6]_194 ;\n wire \\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6]_74 ;\n wire \\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6]_114 ;\n wire \\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6]_130 ;\n wire \\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6]_106 ;\n wire \\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6]_98 ;\n wire \\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6]_82 ;\n wire \\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6]_90 ;\n wire \\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6]_122 ;\n wire \\gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7]_147 ;\n wire \\gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7]_139 ;\n wire \\gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7]_171 ;\n wire \\gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7]_179 ;\n wire \\gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7]_187 ;\n wire \\gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7]_155 ;\n wire \\gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7]_163 ;\n wire \\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0]_0 ;\n wire \\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7]_195 ;\n wire \\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7]_75 ;\n wire \\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7]_115 ;\n wire \\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7]_131 ;\n wire \\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7]_107 ;\n wire \\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7]_99 ;\n wire \\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7]_83 ;\n wire \\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7]_91 ;\n wire \\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7]_123 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.idel_pat0_data_match_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ;\n wire \\gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.idel_pat1_data_match_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ;\n wire \\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat0_data_match_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ;\n wire \\gen_pat_match_div4.pat0_match_fall0_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat0_match_fall0_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat0_match_fall1_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat0_match_fall1_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat0_match_fall2_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat0_match_fall3_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat0_match_rise0_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat0_match_rise1_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat0_match_rise2_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat0_match_rise2_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat0_match_rise3_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat1_data_match_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ;\n wire \\gen_pat_match_div4.pat1_match_fall0_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat1_match_fall1_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat1_match_fall2_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat1_match_fall2_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat1_match_fall3_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat1_match_fall3_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat1_match_rise0_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat1_match_rise1_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat1_match_rise2_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat1_match_rise3_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_52 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_36 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_20 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_12 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_4 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_44 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_28 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_60 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_53 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_37 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_21 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_13 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_5 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_45 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_29 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_61 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_54 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_38 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_22 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_14 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_6 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_46 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_30 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_62 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_55 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_39 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_23 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_15 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_7 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_47 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_31 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_63 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_56 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_40 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_24 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_16 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_8 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_48 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_32 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_64 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_57 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_41 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_25 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_17 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_9 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_49 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_33 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_65 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_58 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_42 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_26 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_18 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_10 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_50 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_34 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_66 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_59 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_43 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_27 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_19 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_11 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_51 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_35 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_67 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0] ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0] ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0] ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0] ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0] ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0] ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0] ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0] ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0] ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg[0]_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0] ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0] ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0] ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0] ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0] ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0] ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0] ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0] ;\n wire \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7] ;\n wire \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r_reg_n_0_[7] ;\n wire \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg_n_0_[7] ;\n wire \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg_n_0_[7] ;\n wire \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r_reg_n_0_[7] ;\n wire \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1_n_0 ;\n wire \\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ;\n wire \\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0 ;\n wire \\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0 ;\n wire [4:0]\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 ;\n wire \\gen_track_left_edge[0].pb_detect_edge_done_r_reg[0]_0 ;\n wire \\gen_track_left_edge[0].pb_found_edge_r_reg[0]_0 ;\n wire \\gen_track_left_edge[0].pb_found_edge_r_reg[0]_1 ;\n wire \\gen_track_left_edge[0].pb_found_edge_r_reg[0]_2 ;\n wire \\gen_track_left_edge[0].pb_found_stable_eye_r_reg ;\n wire \\gen_track_left_edge[0].pb_found_stable_eye_r_reg[0]_0 ;\n wire \\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1_n_0 ;\n wire \\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_0 ;\n wire \\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 ;\n wire \\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ;\n wire \\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ;\n wire \\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0 ;\n wire \\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0 ;\n wire [4:0]\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 ;\n wire \\gen_track_left_edge[1].pb_detect_edge_done_r_reg[1]_0 ;\n wire \\gen_track_left_edge[1].pb_found_edge_r_reg[1]_0 ;\n wire \\gen_track_left_edge[1].pb_found_edge_r_reg[1]_1 ;\n wire \\gen_track_left_edge[1].pb_found_stable_eye_r_reg ;\n wire \\gen_track_left_edge[1].pb_found_stable_eye_r_reg[1]_0 ;\n wire \\gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1_n_0 ;\n wire \\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ;\n wire \\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ;\n wire \\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0 ;\n wire \\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0 ;\n wire [4:0]\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 ;\n wire \\gen_track_left_edge[2].pb_detect_edge_done_r_reg[2]_0 ;\n wire \\gen_track_left_edge[2].pb_found_edge_r_reg[2]_0 ;\n wire \\gen_track_left_edge[2].pb_found_edge_r_reg[2]_1 ;\n wire \\gen_track_left_edge[2].pb_found_stable_eye_r_reg ;\n wire \\gen_track_left_edge[2].pb_found_stable_eye_r_reg[2]_0 ;\n wire \\gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1_n_0 ;\n wire \\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ;\n wire \\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ;\n wire \\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0 ;\n wire \\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0 ;\n wire [4:0]\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 ;\n wire \\gen_track_left_edge[3].pb_detect_edge_done_r_reg[3]_0 ;\n wire \\gen_track_left_edge[3].pb_found_edge_r_reg[3]_0 ;\n wire \\gen_track_left_edge[3].pb_found_edge_r_reg[3]_1 ;\n wire \\gen_track_left_edge[3].pb_found_stable_eye_r_reg ;\n wire \\gen_track_left_edge[3].pb_found_stable_eye_r_reg[3]_0 ;\n wire \\gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1_n_0 ;\n wire \\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ;\n wire \\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ;\n wire \\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0 ;\n wire \\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0 ;\n wire [4:0]\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 ;\n wire \\gen_track_left_edge[4].pb_detect_edge_done_r_reg[4]_0 ;\n wire \\gen_track_left_edge[4].pb_found_edge_r_reg[4]_0 ;\n wire \\gen_track_left_edge[4].pb_found_edge_r_reg[4]_1 ;\n wire \\gen_track_left_edge[4].pb_found_edge_r_reg[4]_2 ;\n wire \\gen_track_left_edge[4].pb_found_stable_eye_r_reg ;\n wire \\gen_track_left_edge[4].pb_found_stable_eye_r_reg[4]_0 ;\n wire \\gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1_n_0 ;\n wire \\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ;\n wire \\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ;\n wire \\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0 ;\n wire \\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0 ;\n wire [4:0]\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 ;\n wire \\gen_track_left_edge[5].pb_detect_edge_done_r_reg[5]_0 ;\n wire \\gen_track_left_edge[5].pb_found_edge_r_reg[5]_0 ;\n wire \\gen_track_left_edge[5].pb_found_edge_r_reg[5]_1 ;\n wire \\gen_track_left_edge[5].pb_found_stable_eye_r_reg ;\n wire \\gen_track_left_edge[5].pb_found_stable_eye_r_reg[5]_0 ;\n wire \\gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1_n_0 ;\n wire \\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ;\n wire \\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ;\n wire \\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0 ;\n wire \\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0 ;\n wire [4:0]\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 ;\n wire \\gen_track_left_edge[6].pb_detect_edge_done_r_reg[6]_0 ;\n wire \\gen_track_left_edge[6].pb_found_edge_r_reg[6]_0 ;\n wire \\gen_track_left_edge[6].pb_found_edge_r_reg[6]_1 ;\n wire \\gen_track_left_edge[6].pb_found_edge_r_reg[6]_2 ;\n wire \\gen_track_left_edge[6].pb_found_stable_eye_r_reg ;\n wire \\gen_track_left_edge[6].pb_found_stable_eye_r_reg[6]_0 ;\n wire \\gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1_n_0 ;\n wire \\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ;\n wire \\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ;\n wire \\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0 ;\n wire \\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0 ;\n wire [4:0]\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 ;\n wire \\gen_track_left_edge[7].pb_detect_edge_done_r_reg[7]_0 ;\n wire \\gen_track_left_edge[7].pb_found_edge_r_reg[7]_0 ;\n wire \\gen_track_left_edge[7].pb_found_edge_r_reg[7]_1 ;\n wire \\gen_track_left_edge[7].pb_found_edge_r_reg[7]_2 ;\n wire \\gen_track_left_edge[7].pb_found_stable_eye_r_reg ;\n wire \\gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_0 ;\n wire \\gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_1 ;\n wire \\gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1_n_0 ;\n wire \\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ;\n wire \\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ;\n wire idel_adj_inc_reg_0;\n wire idel_adj_inc_reg_1;\n wire idel_adj_inc_reg_2;\n wire [0:0]idel_dec_cnt;\n wire \\idel_dec_cnt[0]_i_2_n_0 ;\n wire \\idel_dec_cnt[1]_i_1_n_0 ;\n wire \\idel_dec_cnt[2]_i_1_n_0 ;\n wire \\idel_dec_cnt[3]_i_1_n_0 ;\n wire \\idel_dec_cnt[3]_i_2_n_0 ;\n wire \\idel_dec_cnt[4]_i_1_n_0 ;\n wire \\idel_dec_cnt[4]_i_2_n_0 ;\n wire \\idel_dec_cnt[4]_i_4_n_0 ;\n wire \\idel_dec_cnt[4]_i_5_n_0 ;\n wire \\idel_dec_cnt[4]_i_7_n_0 ;\n wire \\idel_dec_cnt[4]_i_8_n_0 ;\n wire \\idel_dec_cnt[4]_i_9_n_0 ;\n wire [4:0]idel_dec_cnt__0;\n wire \\idel_dec_cnt_reg[0]_0 ;\n wire idel_mpr_pat_detect_r;\n wire idel_pat0_data_match_r0__0;\n wire idel_pat0_match_fall0_and_r;\n wire idel_pat0_match_fall1_and_r;\n wire idel_pat0_match_fall2_and_r;\n wire idel_pat0_match_fall3_and_r;\n wire idel_pat0_match_rise0_and_r;\n wire idel_pat0_match_rise1_and_r;\n wire idel_pat0_match_rise2_and_r;\n wire idel_pat0_match_rise3_and_r;\n wire idel_pat1_data_match_r0__0;\n wire idel_pat1_match_fall0_and_r;\n wire idel_pat1_match_fall1_and_r;\n wire idel_pat1_match_fall2_and_r;\n wire idel_pat1_match_fall3_and_r;\n wire idel_pat1_match_rise0_and_r;\n wire idel_pat1_match_rise1_and_r;\n wire idel_pat1_match_rise2_and_r;\n wire idel_pat1_match_rise3_and_r;\n wire idelay_ce_int;\n wire idelay_inc_int;\n wire [4:0]idelay_tap_cnt_r;\n wire \\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ;\n wire \\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ;\n wire \\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ;\n wire \\idelay_tap_cnt_r[0][0][3]_i_1_n_0 ;\n wire \\idelay_tap_cnt_r[0][0][3]_i_2_n_0 ;\n wire \\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ;\n wire \\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ;\n wire \\idelay_tap_cnt_r[0][0][4]_i_4_n_0 ;\n wire \\idelay_tap_cnt_r[0][0][4]_i_5_n_0 ;\n wire \\idelay_tap_cnt_r[0][1][4]_i_1_n_0 ;\n wire \\idelay_tap_cnt_r[0][2][4]_i_1_n_0 ;\n wire \\idelay_tap_cnt_r[0][3][4]_i_1_n_0 ;\n wire \\idelay_tap_cnt_r[0][3][4]_i_2_n_0 ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][0][0] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][0][1] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][0][2] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][0][3] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][0][4] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][1][0] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][1][1] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][1][2] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][1][3] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][1][4] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][2][0] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][2][1] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][2][2] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][2][3] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][2][4] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][3][0] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][3][1] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][3][2] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][3][3] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][3][4] ;\n wire [4:0]idelay_tap_cnt_slice_r;\n wire idelay_tap_limit_r_i_1_n_0;\n wire idelay_tap_limit_r_i_2_n_0;\n wire idelay_tap_limit_r_reg_n_0;\n wire inhibit_edge_detect_r;\n wire inhibit_edge_detect_r0;\n wire \\init_state_r[0]_i_48_n_0 ;\n wire \\init_state_r[0]_i_49_n_0 ;\n wire \\init_state_r[0]_i_53_n_0 ;\n wire \\init_state_r[0]_i_54_n_0 ;\n wire \\init_state_r_reg[0] ;\n wire \\init_state_r_reg[0]_0 ;\n wire \\init_state_r_reg[0]_1 ;\n wire \\init_state_r_reg[0]_2 ;\n wire \\init_state_r_reg[0]_3 ;\n wire \\init_state_r_reg[0]_4 ;\n wire \\init_state_r_reg[1] ;\n wire [1:0]\\init_state_r_reg[1]_0 ;\n wire \\init_state_r_reg[2] ;\n wire \\init_state_r_reg[2]_0 ;\n wire \\init_state_r_reg[2]_1 ;\n wire \\init_state_r_reg[2]_2 ;\n wire \\init_state_r_reg[3] ;\n wire \\init_state_r_reg[3]_0 ;\n wire \\init_state_r_reg[4] ;\n wire \\init_state_r_reg[5] ;\n wire \\init_state_r_reg[5]_0 ;\n wire mem_init_done_r;\n wire \\mpr_4to1.idel_mpr_pat_detect_r_i_1_n_0 ;\n wire \\mpr_4to1.idel_mpr_pat_detect_r_i_2_n_0 ;\n wire \\mpr_4to1.idel_mpr_pat_detect_r_i_3_n_0 ;\n wire \\mpr_4to1.inhibit_edge_detect_r_i_1_n_0 ;\n wire \\mpr_4to1.inhibit_edge_detect_r_i_2_n_0 ;\n wire \\mpr_4to1.inhibit_edge_detect_r_i_3_n_0 ;\n wire \\mpr_4to1.inhibit_edge_detect_r_i_4_n_0 ;\n wire \\mpr_4to1.inhibit_edge_detect_r_i_6_n_0 ;\n wire \\mpr_4to1.inhibit_edge_detect_r_i_7_n_0 ;\n wire \\mpr_4to1.stable_idel_cnt[0]_i_1_n_0 ;\n wire \\mpr_4to1.stable_idel_cnt[1]_i_1_n_0 ;\n wire \\mpr_4to1.stable_idel_cnt[2]_i_1_n_0 ;\n wire \\mpr_4to1.stable_idel_cnt[2]_i_4_n_0 ;\n wire \\mpr_4to1.stable_idel_cnt[2]_i_5_n_0 ;\n wire \\mpr_4to1.stable_idel_cnt[2]_i_6_n_0 ;\n wire \\mpr_4to1.stable_idel_cnt[2]_i_7_n_0 ;\n wire \\mpr_4to1.stable_idel_cnt[2]_i_8_n_0 ;\n wire \\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ;\n wire \\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ;\n wire \\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ;\n wire mpr_dec_cpt_r_reg_0;\n wire mpr_dec_cpt_r_reg_1;\n wire mpr_last_byte_done;\n wire mpr_last_byte_done_reg_0;\n wire mpr_rank_done_r_reg_0;\n wire mpr_rank_done_r_reg_1;\n wire mpr_rd_fall0_prev_r;\n wire mpr_rd_fall1_prev_r;\n wire mpr_rd_fall2_prev_r;\n wire mpr_rd_fall3_prev_r;\n wire mpr_rd_rise0_prev_r;\n wire mpr_rd_rise0_prev_r0;\n wire mpr_rd_rise0_prev_r_reg_0;\n wire mpr_rd_rise0_prev_r_reg_1;\n wire mpr_rd_rise1_prev_r;\n wire mpr_rd_rise2_prev_r;\n wire mpr_rd_rise3_prev_r;\n wire mpr_rdlvl_done_r1;\n wire mpr_rdlvl_done_r1_reg_0;\n wire mpr_rdlvl_done_r2;\n wire mpr_rdlvl_done_r_reg_0;\n wire mpr_rdlvl_done_r_reg_1;\n wire mpr_rdlvl_start_r;\n wire mpr_rdlvl_start_reg;\n wire mpr_rnk_done;\n wire mpr_valid_r;\n wire mpr_valid_r1;\n wire mpr_valid_r1_reg_0;\n wire mpr_valid_r2;\n wire mpr_valid_r_reg_0;\n wire new_cnt_cpt_r;\n wire new_cnt_cpt_r82_out;\n wire new_cnt_cpt_r_i_2_n_0;\n wire new_cnt_cpt_r_reg_n_0;\n wire \\num_refresh_reg[1] ;\n wire oclkdelay_calib_done_r_reg;\n wire oclkdelay_center_calib_done_r_reg;\n wire \\one_rank.stg1_wr_done_reg ;\n (* RTL_KEEP = \"yes\" *) wire [4:0]out;\n wire p_0_in;\n wire p_0_in102_in;\n wire p_0_in10_in;\n wire p_0_in134_in;\n wire p_0_in13_in;\n wire p_0_in155_in;\n wire p_0_in16_in;\n wire p_0_in180_in;\n wire p_0_in1_in;\n wire p_0_in205_in;\n wire p_0_in230_in;\n wire p_0_in255_in;\n wire p_0_in280_in;\n wire p_0_in305_in;\n wire p_0_in330_in;\n wire p_0_in355_in;\n wire p_0_in380_in;\n wire p_0_in405_in;\n wire p_0_in430_in;\n wire p_0_in455_in;\n wire p_0_in4_in;\n wire p_0_in539_in;\n wire p_0_in7_in;\n wire p_0_in84_in;\n wire p_0_in87_in;\n wire p_0_in90_in;\n wire p_0_in93_in;\n wire p_0_in96_in;\n wire p_0_in99_in;\n wire [5:2]p_0_in__0;\n wire [4:0]p_0_in__0__0;\n wire [3:0]p_0_in__1;\n wire [4:0]p_0_in__2;\n wire [4:0]p_0_in__3;\n wire [4:0]p_0_in__4;\n wire [4:0]p_0_in__5;\n wire [4:0]p_0_in__6;\n wire [4:0]p_0_in__7;\n wire [4:0]p_0_in__8;\n wire [4:0]p_0_in__9;\n wire p_137_out__0;\n wire p_163_out__0;\n wire p_188_out__0;\n wire p_1_in11_in;\n wire p_1_in14_in;\n wire p_1_in162_in;\n wire p_1_in17_in;\n wire p_1_in187_in;\n wire p_1_in212_in;\n wire p_1_in237_in;\n wire p_1_in262_in;\n wire p_1_in26_in;\n wire p_1_in287_in;\n wire p_1_in2_in;\n wire p_1_in312_in;\n wire p_1_in337_in;\n wire p_1_in362_in;\n wire p_1_in387_in;\n wire p_1_in412_in;\n wire p_1_in437_in;\n wire p_1_in462_in;\n wire p_1_in5_in;\n wire p_1_in8_in;\n wire p_213_out__0;\n wire p_238_out__0;\n wire p_263_out__0;\n wire p_288_out__0;\n wire p_2_in156_in;\n wire p_2_in181_in;\n wire p_2_in206_in;\n wire p_2_in231_in;\n wire p_2_in256_in;\n wire p_2_in281_in;\n wire p_2_in306_in;\n wire p_2_in331_in;\n wire p_2_in356_in;\n wire p_2_in381_in;\n wire p_2_in406_in;\n wire p_2_in431_in;\n wire p_2_in456_in;\n wire p_313_out__0;\n wire p_338_out__0;\n wire p_363_out__0;\n wire p_388_out__0;\n wire p_3_in135_in;\n wire p_3_in157_in;\n wire p_3_in182_in;\n wire p_3_in207_in;\n wire p_3_in232_in;\n wire p_3_in257_in;\n wire p_3_in282_in;\n wire p_3_in307_in;\n wire p_3_in332_in;\n wire p_3_in357_in;\n wire p_3_in382_in;\n wire p_3_in407_in;\n wire p_3_in432_in;\n wire p_3_in457_in;\n wire p_413_out__0;\n wire p_438_out__0;\n wire p_463_out__0;\n wire p_488_out__0;\n wire p_4_in158_in;\n wire p_4_in183_in;\n wire p_4_in208_in;\n wire p_4_in233_in;\n wire p_4_in258_in;\n wire p_4_in283_in;\n wire p_4_in308_in;\n wire p_4_in333_in;\n wire p_4_in358_in;\n wire p_4_in383_in;\n wire p_4_in408_in;\n wire p_4_in433_in;\n wire p_4_in458_in;\n wire p_513_out__0;\n wire p_5_in136_in;\n wire p_5_in159_in;\n wire p_5_in184_in;\n wire p_5_in209_in;\n wire p_5_in234_in;\n wire p_5_in259_in;\n wire p_5_in284_in;\n wire p_5_in309_in;\n wire p_5_in334_in;\n wire p_5_in359_in;\n wire p_5_in384_in;\n wire p_5_in409_in;\n wire p_5_in434_in;\n wire p_5_in459_in;\n wire p_6_in160_in;\n wire p_6_in185_in;\n wire p_6_in210_in;\n wire p_6_in235_in;\n wire p_6_in260_in;\n wire p_6_in285_in;\n wire p_6_in310_in;\n wire p_6_in335_in;\n wire p_6_in360_in;\n wire p_6_in385_in;\n wire p_6_in410_in;\n wire p_6_in435_in;\n wire p_6_in460_in;\n wire p_7_in;\n wire p_7_in161_in;\n wire p_7_in186_in;\n wire p_7_in211_in;\n wire p_7_in236_in;\n wire p_7_in261_in;\n wire p_7_in286_in;\n wire p_7_in311_in;\n wire p_7_in336_in;\n wire p_7_in361_in;\n wire p_7_in386_in;\n wire p_7_in411_in;\n wire p_7_in436_in;\n wire p_7_in461_in;\n wire pat0_data_match_r0__0;\n wire pat0_match_fall0_and_r;\n wire pat0_match_fall1_and_r;\n wire pat0_match_fall2_and_r;\n wire pat0_match_fall3_and_r;\n wire pat0_match_rise0_and_r;\n wire pat0_match_rise1_and_r;\n wire pat0_match_rise2_and_r;\n wire pat0_match_rise3_and_r;\n wire pat1_data_match_r0__0;\n wire pat1_match_fall0_and_r;\n wire pat1_match_fall1_and_r;\n wire pat1_match_fall2_and_r;\n wire pat1_match_fall3_and_r;\n wire pat1_match_rise0_and_r;\n wire pat1_match_rise1_and_r;\n wire pat1_match_rise2_and_r;\n wire pat1_match_rise3_and_r;\n wire pb_cnt_eye_size_r;\n wire pb_detect_edge;\n wire [7:0]pb_detect_edge_done_r;\n wire pb_detect_edge_setup;\n wire pb_found_stable_eye_r52_out;\n wire pb_found_stable_eye_r56_out;\n wire pb_found_stable_eye_r60_out;\n wire pb_found_stable_eye_r64_out;\n wire pb_found_stable_eye_r68_out;\n wire pb_found_stable_eye_r72_out;\n wire pb_found_stable_eye_r76_out;\n wire phy_rddata_en_1;\n wire pi_cnt_dec_reg_0;\n wire [0:0]pi_cnt_dec_reg_1;\n wire pi_counter_load_en;\n wire [5:0]pi_counter_load_val;\n wire [4:0]\\pi_counter_read_val_reg[5] ;\n wire \\pi_dqs_found_lanes_r1_reg[0] ;\n wire \\pi_dqs_found_lanes_r1_reg[0]_0 ;\n wire \\pi_dqs_found_lanes_r1_reg[0]_1 ;\n wire \\pi_dqs_found_lanes_r1_reg[1] ;\n wire \\pi_dqs_found_lanes_r1_reg[1]_0 ;\n wire \\pi_dqs_found_lanes_r1_reg[1]_1 ;\n wire [5:0]\\pi_dqs_found_lanes_r1_reg[1]_2 ;\n wire \\pi_dqs_found_lanes_r1_reg[2] ;\n wire \\pi_dqs_found_lanes_r1_reg[2]_0 ;\n wire \\pi_dqs_found_lanes_r1_reg[2]_1 ;\n wire [5:0]\\pi_dqs_found_lanes_r1_reg[2]_2 ;\n wire \\pi_dqs_found_lanes_r1_reg[3] ;\n wire \\pi_dqs_found_lanes_r1_reg[3]_0 ;\n wire \\pi_dqs_found_lanes_r1_reg[3]_1 ;\n wire [5:0]\\pi_dqs_found_lanes_r1_reg[3]_2 ;\n wire pi_en_stg2_f_timing;\n wire pi_en_stg2_f_timing_i_1_n_0;\n wire pi_en_stg2_f_timing_reg_0;\n wire pi_fine_dly_dec_done;\n wire [5:0]pi_rdval_cnt;\n wire \\pi_rdval_cnt[0]_i_1_n_0 ;\n wire \\pi_rdval_cnt[1]_i_1_n_0 ;\n wire \\pi_rdval_cnt[2]_i_1_n_0 ;\n wire \\pi_rdval_cnt[3]_i_1_n_0 ;\n wire \\pi_rdval_cnt[3]_i_2_n_0 ;\n wire \\pi_rdval_cnt[4]_i_1_n_0 ;\n wire \\pi_rdval_cnt[4]_i_2_n_0 ;\n wire \\pi_rdval_cnt[5]_i_1_n_0 ;\n wire \\pi_rdval_cnt[5]_i_2_n_0 ;\n wire \\pi_rdval_cnt[5]_i_4_n_0 ;\n wire \\pi_rdval_cnt[5]_i_5_n_0 ;\n wire \\pi_rdval_cnt_reg[1]_0 ;\n wire pi_stg2_f_incdec_timing;\n wire pi_stg2_f_incdec_timing0;\n wire pi_stg2_load_timing;\n wire [1:0]pi_stg2_rdlvl_cnt;\n wire [5:0]pi_stg2_reg_l_timing;\n wire \\pi_stg2_reg_l_timing[0]_i_1_n_0 ;\n wire \\pi_stg2_reg_l_timing[1]_i_1_n_0 ;\n wire \\pi_stg2_reg_l_timing[2]_i_1_n_0 ;\n wire \\pi_stg2_reg_l_timing[3]_i_1_n_0 ;\n wire \\pi_stg2_reg_l_timing[4]_i_1_n_0 ;\n wire \\pi_stg2_reg_l_timing[5]_i_1_n_0 ;\n wire \\pi_stg2_reg_l_timing[5]_i_2_n_0 ;\n wire \\pi_stg2_reg_l_timing_reg[0]_0 ;\n wire \\po_stg2_wrcal_cnt_reg[0] ;\n wire [0:0]\\po_stg2_wrcal_cnt_reg[1] ;\n wire \\po_stg2_wrcal_cnt_reg[2] ;\n wire \\prbs_dqs_cnt_r_reg[2] ;\n wire prbs_last_byte_done_r;\n wire prbs_pi_stg2_f_en;\n wire prbs_pi_stg2_f_incdec;\n wire prbs_rdlvl_done_reg;\n wire prbs_rdlvl_done_reg_rep;\n wire prbs_rdlvl_done_reg_rep_0;\n wire prbs_rdlvl_done_reg_rep_1;\n wire prbs_rdlvl_prech_req_reg;\n wire prech_done;\n wire prech_req;\n wire \\rd_mux_sel_r_reg[1]_0 ;\n wire \\rd_mux_sel_r_reg[1]_1 ;\n wire \\rd_mux_sel_r_reg[1]_10 ;\n wire \\rd_mux_sel_r_reg[1]_11 ;\n wire \\rd_mux_sel_r_reg[1]_12 ;\n wire \\rd_mux_sel_r_reg[1]_13 ;\n wire \\rd_mux_sel_r_reg[1]_14 ;\n wire \\rd_mux_sel_r_reg[1]_15 ;\n wire \\rd_mux_sel_r_reg[1]_16 ;\n wire \\rd_mux_sel_r_reg[1]_17 ;\n wire \\rd_mux_sel_r_reg[1]_18 ;\n wire \\rd_mux_sel_r_reg[1]_19 ;\n wire \\rd_mux_sel_r_reg[1]_2 ;\n wire \\rd_mux_sel_r_reg[1]_20 ;\n wire \\rd_mux_sel_r_reg[1]_21 ;\n wire \\rd_mux_sel_r_reg[1]_22 ;\n wire \\rd_mux_sel_r_reg[1]_23 ;\n wire \\rd_mux_sel_r_reg[1]_24 ;\n wire \\rd_mux_sel_r_reg[1]_25 ;\n wire \\rd_mux_sel_r_reg[1]_26 ;\n wire \\rd_mux_sel_r_reg[1]_27 ;\n wire \\rd_mux_sel_r_reg[1]_28 ;\n wire \\rd_mux_sel_r_reg[1]_29 ;\n wire \\rd_mux_sel_r_reg[1]_3 ;\n wire \\rd_mux_sel_r_reg[1]_30 ;\n wire \\rd_mux_sel_r_reg[1]_31 ;\n wire \\rd_mux_sel_r_reg[1]_32 ;\n wire \\rd_mux_sel_r_reg[1]_33 ;\n wire \\rd_mux_sel_r_reg[1]_34 ;\n wire \\rd_mux_sel_r_reg[1]_35 ;\n wire \\rd_mux_sel_r_reg[1]_36 ;\n wire \\rd_mux_sel_r_reg[1]_37 ;\n wire \\rd_mux_sel_r_reg[1]_38 ;\n wire \\rd_mux_sel_r_reg[1]_39 ;\n wire \\rd_mux_sel_r_reg[1]_4 ;\n wire \\rd_mux_sel_r_reg[1]_40 ;\n wire \\rd_mux_sel_r_reg[1]_41 ;\n wire \\rd_mux_sel_r_reg[1]_42 ;\n wire \\rd_mux_sel_r_reg[1]_43 ;\n wire \\rd_mux_sel_r_reg[1]_44 ;\n wire \\rd_mux_sel_r_reg[1]_45 ;\n wire \\rd_mux_sel_r_reg[1]_46 ;\n wire \\rd_mux_sel_r_reg[1]_47 ;\n wire \\rd_mux_sel_r_reg[1]_48 ;\n wire \\rd_mux_sel_r_reg[1]_49 ;\n wire \\rd_mux_sel_r_reg[1]_5 ;\n wire \\rd_mux_sel_r_reg[1]_50 ;\n wire \\rd_mux_sel_r_reg[1]_51 ;\n wire \\rd_mux_sel_r_reg[1]_52 ;\n wire \\rd_mux_sel_r_reg[1]_53 ;\n wire \\rd_mux_sel_r_reg[1]_54 ;\n wire \\rd_mux_sel_r_reg[1]_55 ;\n wire \\rd_mux_sel_r_reg[1]_56 ;\n wire \\rd_mux_sel_r_reg[1]_57 ;\n wire \\rd_mux_sel_r_reg[1]_58 ;\n wire \\rd_mux_sel_r_reg[1]_59 ;\n wire \\rd_mux_sel_r_reg[1]_6 ;\n wire \\rd_mux_sel_r_reg[1]_60 ;\n wire \\rd_mux_sel_r_reg[1]_61 ;\n wire \\rd_mux_sel_r_reg[1]_62 ;\n wire \\rd_mux_sel_r_reg[1]_63 ;\n wire \\rd_mux_sel_r_reg[1]_7 ;\n wire \\rd_mux_sel_r_reg[1]_8 ;\n wire \\rd_mux_sel_r_reg[1]_9 ;\n wire \\rdlvl_cpt_tap_cnt_reg[1] ;\n wire \\rdlvl_cpt_tap_cnt_reg[2] ;\n wire \\rdlvl_cpt_tap_cnt_reg[4] ;\n wire rdlvl_dqs_tap_cnt_r;\n wire \\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ;\n wire \\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ;\n wire \\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ;\n wire \\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ;\n wire [1:0]\\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][0] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][1] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][2] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][3] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][4] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][5] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][0] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][1] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][2] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][3] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][4] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][5] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][0] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][1] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][2] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][3] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][4] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][5] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][0] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][1] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][2] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][3] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][4] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][5] ;\n wire rdlvl_last_byte_done;\n wire rdlvl_pi_incdec;\n wire rdlvl_pi_incdec_i_4_n_0;\n wire rdlvl_pi_incdec_i_5_n_0;\n wire rdlvl_pi_incdec_i_6_n_0;\n wire rdlvl_pi_incdec_reg_0;\n wire rdlvl_pi_incdec_reg_1;\n wire rdlvl_pi_stg2_f_en;\n wire rdlvl_pi_stg2_f_incdec;\n wire rdlvl_prech_req;\n wire rdlvl_rank_done_r_reg_0;\n wire rdlvl_stg1_done_int;\n wire rdlvl_stg1_done_r1_reg;\n wire rdlvl_stg1_rank_done;\n wire rdlvl_stg1_start_r;\n wire rdlvl_stg1_start_reg;\n wire [0:0]rdlvl_stg1_start_reg_0;\n wire [1:0]regl_dqs_cnt;\n wire \\regl_dqs_cnt[0]_i_1_n_0 ;\n wire \\regl_dqs_cnt[1]_i_1_n_0 ;\n wire \\regl_dqs_cnt[1]_i_2_n_0 ;\n wire \\regl_dqs_cnt[2]_i_1_n_0 ;\n wire [2:0]regl_dqs_cnt_r;\n wire [0:0]\\regl_dqs_cnt_r_reg[2]_0 ;\n wire \\regl_dqs_cnt_reg[0]_0 ;\n wire \\regl_dqs_cnt_reg[2]_0 ;\n wire [1:0]regl_rank_cnt;\n wire \\regl_rank_cnt[0]_i_1_n_0 ;\n wire \\regl_rank_cnt[1]_i_1_n_0 ;\n wire \\right_edge_taps_r[0]_i_1_n_0 ;\n wire \\right_edge_taps_r[1]_i_1_n_0 ;\n wire \\right_edge_taps_r[2]_i_1_n_0 ;\n wire \\right_edge_taps_r[3]_i_1_n_0 ;\n wire \\right_edge_taps_r[4]_i_1_n_0 ;\n wire \\right_edge_taps_r[5]_i_1_n_0 ;\n wire \\right_edge_taps_r[5]_i_2_n_0 ;\n wire [5:0]right_edge_taps_r__0;\n wire \\right_edge_taps_r_reg[0]_0 ;\n wire \\right_edge_taps_r_reg[0]_1 ;\n wire \\right_edge_taps_r_reg[0]_2 ;\n wire \\rnk_cnt_r[0]_i_1__0_n_0 ;\n wire \\rnk_cnt_r[1]_i_1__0_n_0 ;\n wire \\rnk_cnt_r[1]_i_2_n_0 ;\n wire \\rnk_cnt_r[1]_i_3_n_0 ;\n wire \\rnk_cnt_r_reg_n_0_[0] ;\n wire \\rnk_cnt_r_reg_n_0_[1] ;\n wire rstdiv0_sync_r1_reg_rep__13;\n wire [1:0]rstdiv0_sync_r1_reg_rep__14;\n wire rstdiv0_sync_r1_reg_rep__2;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__22;\n wire rstdiv0_sync_r1_reg_rep__23;\n wire samp_cnt_done_r_i_1_n_0;\n wire samp_cnt_done_r_i_2_n_0;\n wire samp_cnt_done_r_i_3_n_0;\n wire samp_cnt_done_r_i_4_n_0;\n wire samp_cnt_done_r_reg_0;\n wire samp_cnt_done_r_reg_1;\n wire samp_cnt_done_r_reg_2;\n wire samp_cnt_done_r_reg_3;\n wire samp_cnt_done_r_reg_4;\n wire samp_cnt_done_r_reg_5;\n wire samp_cnt_done_r_reg_6;\n wire samp_edge_cnt0_en_r;\n wire samp_edge_cnt0_en_r_reg_0;\n wire samp_edge_cnt0_r0;\n wire \\samp_edge_cnt0_r[0]_i_4_n_0 ;\n wire \\samp_edge_cnt0_r[0]_i_5_n_0 ;\n wire \\samp_edge_cnt0_r[0]_i_6_n_0 ;\n wire \\samp_edge_cnt0_r[0]_i_7_n_0 ;\n wire \\samp_edge_cnt0_r[4]_i_2_n_0 ;\n wire \\samp_edge_cnt0_r[4]_i_3_n_0 ;\n wire \\samp_edge_cnt0_r[4]_i_4_n_0 ;\n wire \\samp_edge_cnt0_r[4]_i_5_n_0 ;\n wire \\samp_edge_cnt0_r[8]_i_2_n_0 ;\n wire \\samp_edge_cnt0_r[8]_i_3_n_0 ;\n wire \\samp_edge_cnt0_r[8]_i_4_n_0 ;\n wire \\samp_edge_cnt0_r[8]_i_5_n_0 ;\n wire [11:0]samp_edge_cnt0_r_reg;\n wire \\samp_edge_cnt0_r_reg[0]_i_3_n_0 ;\n wire \\samp_edge_cnt0_r_reg[0]_i_3_n_1 ;\n wire \\samp_edge_cnt0_r_reg[0]_i_3_n_2 ;\n wire \\samp_edge_cnt0_r_reg[0]_i_3_n_3 ;\n wire \\samp_edge_cnt0_r_reg[0]_i_3_n_4 ;\n wire \\samp_edge_cnt0_r_reg[0]_i_3_n_5 ;\n wire \\samp_edge_cnt0_r_reg[0]_i_3_n_6 ;\n wire \\samp_edge_cnt0_r_reg[0]_i_3_n_7 ;\n wire \\samp_edge_cnt0_r_reg[4]_i_1_n_0 ;\n wire \\samp_edge_cnt0_r_reg[4]_i_1_n_1 ;\n wire \\samp_edge_cnt0_r_reg[4]_i_1_n_2 ;\n wire \\samp_edge_cnt0_r_reg[4]_i_1_n_3 ;\n wire \\samp_edge_cnt0_r_reg[4]_i_1_n_4 ;\n wire \\samp_edge_cnt0_r_reg[4]_i_1_n_5 ;\n wire \\samp_edge_cnt0_r_reg[4]_i_1_n_6 ;\n wire \\samp_edge_cnt0_r_reg[4]_i_1_n_7 ;\n wire \\samp_edge_cnt0_r_reg[8]_i_1_n_1 ;\n wire \\samp_edge_cnt0_r_reg[8]_i_1_n_2 ;\n wire \\samp_edge_cnt0_r_reg[8]_i_1_n_3 ;\n wire \\samp_edge_cnt0_r_reg[8]_i_1_n_4 ;\n wire \\samp_edge_cnt0_r_reg[8]_i_1_n_5 ;\n wire \\samp_edge_cnt0_r_reg[8]_i_1_n_6 ;\n wire \\samp_edge_cnt0_r_reg[8]_i_1_n_7 ;\n wire samp_edge_cnt1_en_r;\n wire samp_edge_cnt1_en_r0;\n wire samp_edge_cnt1_en_r_i_2_n_0;\n wire samp_edge_cnt1_en_r_i_3_n_0;\n wire \\samp_edge_cnt1_r[0]_i_2_n_0 ;\n wire \\samp_edge_cnt1_r[0]_i_3_n_0 ;\n wire \\samp_edge_cnt1_r[0]_i_4_n_0 ;\n wire \\samp_edge_cnt1_r[0]_i_5_n_0 ;\n wire \\samp_edge_cnt1_r[4]_i_2_n_0 ;\n wire \\samp_edge_cnt1_r[4]_i_3_n_0 ;\n wire \\samp_edge_cnt1_r[4]_i_4_n_0 ;\n wire \\samp_edge_cnt1_r[4]_i_5_n_0 ;\n wire \\samp_edge_cnt1_r[8]_i_2_n_0 ;\n wire \\samp_edge_cnt1_r[8]_i_3_n_0 ;\n wire \\samp_edge_cnt1_r[8]_i_4_n_0 ;\n wire \\samp_edge_cnt1_r[8]_i_5_n_0 ;\n wire [11:0]samp_edge_cnt1_r_reg;\n wire \\samp_edge_cnt1_r_reg[0]_i_1_n_0 ;\n wire \\samp_edge_cnt1_r_reg[0]_i_1_n_1 ;\n wire \\samp_edge_cnt1_r_reg[0]_i_1_n_2 ;\n wire \\samp_edge_cnt1_r_reg[0]_i_1_n_3 ;\n wire \\samp_edge_cnt1_r_reg[0]_i_1_n_4 ;\n wire \\samp_edge_cnt1_r_reg[0]_i_1_n_5 ;\n wire \\samp_edge_cnt1_r_reg[0]_i_1_n_6 ;\n wire \\samp_edge_cnt1_r_reg[0]_i_1_n_7 ;\n wire \\samp_edge_cnt1_r_reg[4]_i_1_n_0 ;\n wire \\samp_edge_cnt1_r_reg[4]_i_1_n_1 ;\n wire \\samp_edge_cnt1_r_reg[4]_i_1_n_2 ;\n wire \\samp_edge_cnt1_r_reg[4]_i_1_n_3 ;\n wire \\samp_edge_cnt1_r_reg[4]_i_1_n_4 ;\n wire \\samp_edge_cnt1_r_reg[4]_i_1_n_5 ;\n wire \\samp_edge_cnt1_r_reg[4]_i_1_n_6 ;\n wire \\samp_edge_cnt1_r_reg[4]_i_1_n_7 ;\n wire \\samp_edge_cnt1_r_reg[8]_i_1_n_1 ;\n wire \\samp_edge_cnt1_r_reg[8]_i_1_n_2 ;\n wire \\samp_edge_cnt1_r_reg[8]_i_1_n_3 ;\n wire \\samp_edge_cnt1_r_reg[8]_i_1_n_4 ;\n wire \\samp_edge_cnt1_r_reg[8]_i_1_n_5 ;\n wire \\samp_edge_cnt1_r_reg[8]_i_1_n_6 ;\n wire \\samp_edge_cnt1_r_reg[8]_i_1_n_7 ;\n wire \\second_edge_taps_r[0]_i_1_n_0 ;\n wire \\second_edge_taps_r[1]_i_1_n_0 ;\n wire \\second_edge_taps_r[2]_i_1_n_0 ;\n wire \\second_edge_taps_r[3]_i_1_n_0 ;\n wire \\second_edge_taps_r[4]_i_1_n_0 ;\n wire \\second_edge_taps_r[5]_i_1_n_0 ;\n wire \\second_edge_taps_r[5]_i_3_n_0 ;\n wire \\second_edge_taps_r_reg[5]_0 ;\n wire \\second_edge_taps_r_reg_n_0_[0] ;\n wire \\second_edge_taps_r_reg_n_0_[1] ;\n wire \\second_edge_taps_r_reg_n_0_[2] ;\n wire \\second_edge_taps_r_reg_n_0_[3] ;\n wire \\second_edge_taps_r_reg_n_0_[4] ;\n wire \\second_edge_taps_r_reg_n_0_[5] ;\n wire sr_valid_r1;\n wire sr_valid_r108_out;\n wire sr_valid_r1_reg_0;\n wire sr_valid_r2;\n wire stable_idel_cnt;\n wire stable_idel_cnt0;\n wire stable_idel_cnt22_in;\n wire stg1_wr_done;\n wire \\stg1_wr_rd_cnt_reg[3] ;\n wire store_sr_r0;\n wire store_sr_r1;\n wire store_sr_r_reg_0;\n wire store_sr_req_pulsed_r;\n wire store_sr_req_pulsed_r_reg_n_0;\n wire store_sr_req_r;\n wire store_sr_req_r_i_2_n_0;\n wire store_sr_req_r_reg_0;\n wire store_sr_req_r_reg_1;\n wire tap_cnt_cpt_r;\n wire tap_cnt_cpt_r0;\n wire \\tap_cnt_cpt_r[1]_i_1_n_0 ;\n wire \\tap_cnt_cpt_r[5]_i_4_n_0 ;\n wire \\tap_cnt_cpt_r_reg_n_0_[0] ;\n wire \\tap_cnt_cpt_r_reg_n_0_[1] ;\n wire \\tap_cnt_cpt_r_reg_n_0_[2] ;\n wire \\tap_cnt_cpt_r_reg_n_0_[3] ;\n wire \\tap_cnt_cpt_r_reg_n_0_[4] ;\n wire \\tap_cnt_cpt_r_reg_n_0_[5] ;\n wire tap_limit_cpt_r;\n wire tap_limit_cpt_r_i_1_n_0;\n wire tap_limit_cpt_r_i_2_n_0;\n wire tap_limit_cpt_r_i_3_n_0;\n wire tempmon_pi_f_en_r;\n wire tempmon_pi_f_inc_r;\n wire wait_cnt_r0;\n wire [3:0]wait_cnt_r0__0;\n wire \\wait_cnt_r[1]_i_1__1_n_0 ;\n wire [1:0]\\wait_cnt_r_reg[0]_0 ;\n wire \\wait_cnt_r_reg[0]_1 ;\n wire [3:2]wait_cnt_r_reg__0;\n wire wr_level_done_reg;\n wire wrcal_done_reg;\n wire wrcal_prech_req;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[254] ;\n wire wrlvl_byte_redo;\n wire wrlvl_byte_redo_reg;\n wire wrlvl_done_r1;\n wire wrlvl_done_r1_reg;\n wire wrlvl_done_r1_reg_0;\n wire wrlvl_final_mux;\n wire wrlvl_final_mux_reg;\n wire [0:0]\\NLW_cnt_idel_dec_cpt_r_reg[1]_i_2_O_UNCONNECTED ;\n wire [0:0]\\NLW_cnt_idel_dec_cpt_r_reg[1]_i_9_O_UNCONNECTED ;\n wire [3:1]\\NLW_cnt_idel_dec_cpt_r_reg[4]_i_6_CO_UNCONNECTED ;\n wire [3:2]\\NLW_cnt_idel_dec_cpt_r_reg[4]_i_6_O_UNCONNECTED ;\n wire [3:1]\\NLW_cnt_idel_dec_cpt_r_reg[5]_i_9_CO_UNCONNECTED ;\n wire [3:2]\\NLW_cnt_idel_dec_cpt_r_reg[5]_i_9_O_UNCONNECTED ;\n wire [3:3]\\NLW_samp_edge_cnt0_r_reg[8]_i_1_CO_UNCONNECTED ;\n wire [3:3]\\NLW_samp_edge_cnt1_r_reg[8]_i_1_CO_UNCONNECTED ;\n\n LUT6 #(\n .INIT(64'hFFFFFEAEAAAAFEAE)) \n \\FSM_sequential_cal1_state_r[0]_i_1 \n (.I0(\\FSM_sequential_cal1_state_r[0]_i_2_n_0 ),\n .I1(\\FSM_sequential_cal1_state_r[0]_i_3_n_0 ),\n .I2(out[0]),\n .I3(\\FSM_sequential_cal1_state_r[0]_i_4_n_0 ),\n .I4(out[1]),\n .I5(\\FSM_sequential_cal1_state_r[0]_i_5_n_0 ),\n .O(\\FSM_sequential_cal1_state_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000002000000)) \n \\FSM_sequential_cal1_state_r[0]_i_10 \n (.I0(\\done_cnt[3]_i_3_n_0 ),\n .I1(regl_rank_cnt[1]),\n .I2(regl_rank_cnt[0]),\n .I3(regl_dqs_cnt[0]),\n .I4(regl_dqs_cnt[1]),\n .I5(\\regl_dqs_cnt_r_reg[2]_0 ),\n .O(cal1_state_r1));\n LUT5 #(\n .INIT(32'hBFFFFF00)) \n \\FSM_sequential_cal1_state_r[0]_i_11 \n (.I0(mpr_rdlvl_done_r1_reg_0),\n .I1(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I2(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .I3(out[0]),\n .I4(out[2]),\n .O(\\FSM_sequential_cal1_state_r[0]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'h0000150000000000)) \n \\FSM_sequential_cal1_state_r[0]_i_12 \n (.I0(\\FSM_sequential_cal1_state_r[0]_i_14_n_0 ),\n .I1(mpr_dec_cpt_r_reg_0),\n .I2(stable_idel_cnt22_in),\n .I3(\\cnt_idel_dec_cpt_r_reg_n_0_[0] ),\n .I4(\\cnt_idel_dec_cpt_r_reg_n_0_[1] ),\n .I5(out[2]),\n .O(\\FSM_sequential_cal1_state_r[0]_i_12_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair226\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\FSM_sequential_cal1_state_r[0]_i_13 \n (.I0(\\right_edge_taps_r_reg[0]_0 ),\n .I1(found_stable_eye_last_r),\n .O(cal1_state_r1533_out));\n (* SOFT_HLUTNM = \"soft_lutpair204\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n \\FSM_sequential_cal1_state_r[0]_i_14 \n (.I0(\\cnt_idel_dec_cpt_r_reg_n_0_[5] ),\n .I1(\\cnt_idel_dec_cpt_r_reg_n_0_[4] ),\n .I2(\\cnt_idel_dec_cpt_r_reg_n_0_[2] ),\n .I3(\\cnt_idel_dec_cpt_r_reg_n_0_[3] ),\n .O(\\FSM_sequential_cal1_state_r[0]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'hBBBB88B888B8BBB8)) \n \\FSM_sequential_cal1_state_r[0]_i_2 \n (.I0(\\FSM_sequential_cal1_state_r[0]_i_6_n_0 ),\n .I1(\\idel_dec_cnt_reg[0]_0 ),\n .I2(\\FSM_sequential_cal1_state_r[0]_i_7_n_0 ),\n .I3(out[4]),\n .I4(out[2]),\n .I5(out[0]),\n .O(\\FSM_sequential_cal1_state_r[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h8988898889998988)) \n \\FSM_sequential_cal1_state_r[0]_i_3 \n (.I0(out[2]),\n .I1(out[4]),\n .I2(mpr_rdlvl_done_r1_reg_0),\n .I3(cal1_state_r),\n .I4(mpr_rdlvl_start_reg),\n .I5(mpr_rdlvl_start_r),\n .O(\\FSM_sequential_cal1_state_r[0]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h1110101011111111)) \n \\FSM_sequential_cal1_state_r[0]_i_4 \n (.I0(out[2]),\n .I1(cal1_state_r),\n .I2(out[3]),\n .I3(idelay_tap_limit_r_reg_n_0),\n .I4(\\FSM_sequential_cal1_state_r[0]_i_8_n_0 ),\n .I5(out[4]),\n .O(\\FSM_sequential_cal1_state_r[0]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hEEAFEEAAEEAFEEAF)) \n \\FSM_sequential_cal1_state_r[0]_i_5 \n (.I0(\\FSM_sequential_cal1_state_r[0]_i_9_n_0 ),\n .I1(cal1_state_r1),\n .I2(\\FSM_sequential_cal1_state_r[0]_i_11_n_0 ),\n .I3(cal1_state_r),\n .I4(out[3]),\n .I5(store_sr_req_r_reg_0),\n .O(\\FSM_sequential_cal1_state_r[0]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'h11040004)) \n \\FSM_sequential_cal1_state_r[0]_i_6 \n (.I0(out[2]),\n .I1(out[3]),\n .I2(\\FSM_sequential_cal1_state_r[1]_i_7_n_0 ),\n .I3(out[0]),\n .I4(mpr_rdlvl_done_r1_reg_0),\n .O(\\FSM_sequential_cal1_state_r[0]_i_6_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFA800)) \n \\FSM_sequential_cal1_state_r[0]_i_7 \n (.I0(mpr_rd_rise0_prev_r_reg_0),\n .I1(idelay_tap_limit_r_reg_n_0),\n .I2(idel_mpr_pat_detect_r),\n .I3(out[0]),\n .I4(\\FSM_sequential_cal1_state_r[0]_i_12_n_0 ),\n .O(\\FSM_sequential_cal1_state_r[0]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h1)) \n \\FSM_sequential_cal1_state_r[0]_i_8 \n (.I0(\\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ),\n .I1(\\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ),\n .O(\\FSM_sequential_cal1_state_r[0]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'h2220202000000000)) \n \\FSM_sequential_cal1_state_r[0]_i_9 \n (.I0(out[0]),\n .I1(out[3]),\n .I2(tap_limit_cpt_r),\n .I3(found_first_edge_r_reg_0),\n .I4(cal1_state_r1533_out),\n .I5(out[4]),\n .O(\\FSM_sequential_cal1_state_r[0]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF2EEE2222)) \n \\FSM_sequential_cal1_state_r[1]_i_1 \n (.I0(\\FSM_sequential_cal1_state_r[1]_i_2_n_0 ),\n .I1(out[0]),\n .I2(out[4]),\n .I3(\\FSM_sequential_cal1_state_r[1]_i_3_n_0 ),\n .I4(\\FSM_sequential_cal1_state_r[1]_i_4_n_0 ),\n .I5(\\FSM_sequential_cal1_state_r_reg[1]_i_5_n_0 ),\n .O(\\FSM_sequential_cal1_state_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair202\" *) \n LUT4 #(\n .INIT(16'hFEFF)) \n \\FSM_sequential_cal1_state_r[1]_i_10 \n (.I0(\\cnt_idel_dec_cpt_r_reg_n_0_[1] ),\n .I1(\\cnt_idel_dec_cpt_r_reg_n_0_[2] ),\n .I2(\\cnt_idel_dec_cpt_r_reg_n_0_[4] ),\n .I3(mpr_dec_cpt_r_reg_0),\n .O(\\FSM_sequential_cal1_state_r[1]_i_10_n_0 ));\n LUT4 #(\n .INIT(16'h4474)) \n \\FSM_sequential_cal1_state_r[1]_i_11 \n (.I0(mpr_rdlvl_done_r1_reg_0),\n .I1(cal1_state_r),\n .I2(mpr_rdlvl_start_reg),\n .I3(mpr_rdlvl_start_r),\n .O(\\FSM_sequential_cal1_state_r[1]_i_11_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair226\" *) \n LUT3 #(\n .INIT(8'h7F)) \n \\FSM_sequential_cal1_state_r[1]_i_12 \n (.I0(found_stable_eye_last_r),\n .I1(\\right_edge_taps_r_reg[0]_0 ),\n .I2(found_first_edge_r_reg_0),\n .O(\\FSM_sequential_cal1_state_r[1]_i_12_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\FSM_sequential_cal1_state_r[1]_i_13 \n (.I0(out[3]),\n .I1(out[2]),\n .O(\\FSM_sequential_cal1_state_r[1]_i_13_n_0 ));\n LUT6 #(\n .INIT(64'h0C0C0C0C88888088)) \n \\FSM_sequential_cal1_state_r[1]_i_2 \n (.I0(out[4]),\n .I1(\\FSM_sequential_cal1_state_r[1]_i_6_n_0 ),\n .I2(out[1]),\n .I3(mpr_dec_cpt_r_reg_0),\n .I4(\\FSM_sequential_cal1_state_r[1]_i_7_n_0 ),\n .I5(out[2]),\n .O(\\FSM_sequential_cal1_state_r[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hEF00FF00EFFFFF00)) \n \\FSM_sequential_cal1_state_r[1]_i_3 \n (.I0(\\rnk_cnt_r_reg_n_0_[0] ),\n .I1(\\rnk_cnt_r_reg_n_0_[1] ),\n .I2(cal1_cnt_cpt_r1),\n .I3(out[3]),\n .I4(mpr_rdlvl_done_r1_reg_0),\n .I5(idel_adj_inc_reg_0),\n .O(\\FSM_sequential_cal1_state_r[1]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h5500000055510055)) \n \\FSM_sequential_cal1_state_r[1]_i_4 \n (.I0(cal1_state_r),\n .I1(mpr_rd_rise0_prev_r_reg_0),\n .I2(idel_mpr_pat_detect_r),\n .I3(out[2]),\n .I4(out[1]),\n .I5(out[4]),\n .O(\\FSM_sequential_cal1_state_r[1]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFD)) \n \\FSM_sequential_cal1_state_r[1]_i_6 \n (.I0(\\cnt_idel_dec_cpt_r_reg_n_0_[0] ),\n .I1(out[4]),\n .I2(stable_idel_cnt22_in),\n .I3(\\cnt_idel_dec_cpt_r_reg_n_0_[5] ),\n .I4(\\cnt_idel_dec_cpt_r_reg_n_0_[3] ),\n .I5(\\FSM_sequential_cal1_state_r[1]_i_10_n_0 ),\n .O(\\FSM_sequential_cal1_state_r[1]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\FSM_sequential_cal1_state_r[1]_i_7 \n (.I0(\\pi_rdval_cnt_reg[1]_0 ),\n .I1(idel_dec_cnt__0[2]),\n .I2(idel_dec_cnt__0[1]),\n .I3(idel_dec_cnt__0[0]),\n .I4(idel_dec_cnt__0[3]),\n .I5(idel_dec_cnt__0[4]),\n .O(\\FSM_sequential_cal1_state_r[1]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h0101010151515101)) \n \\FSM_sequential_cal1_state_r[1]_i_8 \n (.I0(out[2]),\n .I1(\\FSM_sequential_cal1_state_r[1]_i_11_n_0 ),\n .I2(out[4]),\n .I3(\\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ),\n .I4(\\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ),\n .I5(out[3]),\n .O(\\FSM_sequential_cal1_state_r[1]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'h000000004040FF40)) \n \\FSM_sequential_cal1_state_r[1]_i_9 \n (.I0(tap_limit_cpt_r),\n .I1(\\FSM_sequential_cal1_state_r[1]_i_12_n_0 ),\n .I2(out[4]),\n .I3(cal1_state_r),\n .I4(cal1_state_r1),\n .I5(\\FSM_sequential_cal1_state_r[1]_i_13_n_0 ),\n .O(\\FSM_sequential_cal1_state_r[1]_i_9_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF3404)) \n \\FSM_sequential_cal1_state_r[2]_i_1 \n (.I0(out[4]),\n .I1(out[2]),\n .I2(out[0]),\n .I3(out[3]),\n .I4(\\FSM_sequential_cal1_state_r_reg[2]_i_2_n_0 ),\n .O(\\FSM_sequential_cal1_state_r[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8888AAA8AAAAAAAA)) \n \\FSM_sequential_cal1_state_r[2]_i_3 \n (.I0(out[4]),\n .I1(out[0]),\n .I2(\\FSM_sequential_cal1_state_r[1]_i_7_n_0 ),\n .I3(mpr_dec_cpt_r_reg_0),\n .I4(out[2]),\n .I5(out[3]),\n .O(\\FSM_sequential_cal1_state_r[2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h00AB00AB03AB00AB)) \n \\FSM_sequential_cal1_state_r[2]_i_4 \n (.I0(\\FSM_sequential_cal1_state_r[2]_i_5_n_0 ),\n .I1(out[4]),\n .I2(cal1_state_r),\n .I3(out[0]),\n .I4(mpr_rd_rise0_prev_r_reg_0),\n .I5(idel_mpr_pat_detect_r),\n .O(\\FSM_sequential_cal1_state_r[2]_i_4_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\FSM_sequential_cal1_state_r[2]_i_5 \n (.I0(out[2]),\n .I1(out[3]),\n .O(\\FSM_sequential_cal1_state_r[2]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h303030003008CC08)) \n \\FSM_sequential_cal1_state_r[3]_i_1 \n (.I0(\\FSM_sequential_cal1_state_r[3]_i_2_n_0 ),\n .I1(out[2]),\n .I2(out[4]),\n .I3(out[1]),\n .I4(out[3]),\n .I5(out[0]),\n .O(\\FSM_sequential_cal1_state_r[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFDF)) \n \\FSM_sequential_cal1_state_r[3]_i_2 \n (.I0(mpr_dec_cpt_r_reg_0),\n .I1(\\cnt_idel_dec_cpt_r_reg_n_0_[4] ),\n .I2(\\cnt_idel_dec_cpt_r_reg_n_0_[0] ),\n .I3(\\cnt_idel_dec_cpt_r_reg_n_0_[3] ),\n .I4(\\cnt_idel_dec_cpt_r_reg_n_0_[5] ),\n .I5(\\FSM_sequential_cal1_state_r[3]_i_3_n_0 ),\n .O(\\FSM_sequential_cal1_state_r[3]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair202\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\FSM_sequential_cal1_state_r[3]_i_3 \n (.I0(\\cnt_idel_dec_cpt_r_reg_n_0_[2] ),\n .I1(\\cnt_idel_dec_cpt_r_reg_n_0_[1] ),\n .O(\\FSM_sequential_cal1_state_r[3]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'h0C0C0C8C)) \n \\FSM_sequential_cal1_state_r[4]_i_1 \n (.I0(out[2]),\n .I1(\\FSM_sequential_cal1_state_r[4]_i_2_n_0 ),\n .I2(\\FSM_sequential_cal1_state_r[4]_i_3_n_0 ),\n .I3(\\FSM_sequential_cal1_state_r[4]_i_4_n_0 ),\n .I4(out[0]),\n .O(\\FSM_sequential_cal1_state_r[4]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hEFFFFFFF)) \n \\FSM_sequential_cal1_state_r[4]_i_2 \n (.I0(idel_adj_inc_reg_0),\n .I1(mpr_rdlvl_done_r1_reg_0),\n .I2(out[0]),\n .I3(out[2]),\n .I4(out[1]),\n .O(\\FSM_sequential_cal1_state_r[4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h000000000000AFEF)) \n \\FSM_sequential_cal1_state_r[4]_i_3 \n (.I0(out[3]),\n .I1(mpr_dec_cpt_r_reg_0),\n .I2(out[2]),\n .I3(out[0]),\n .I4(\\FSM_sequential_cal1_state_r[4]_i_5_n_0 ),\n .I5(\\FSM_sequential_cal1_state_r[4]_i_6_n_0 ),\n .O(\\FSM_sequential_cal1_state_r[4]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hA0A0A0A0A0A0A0A1)) \n \\FSM_sequential_cal1_state_r[4]_i_4 \n (.I0(out[1]),\n .I1(\\FSM_sequential_cal1_state_r[4]_i_7_n_0 ),\n .I2(out[3]),\n .I3(stable_idel_cnt22_in),\n .I4(\\cnt_idel_dec_cpt_r_reg_n_0_[2] ),\n .I5(\\cnt_idel_dec_cpt_r_reg_n_0_[1] ),\n .O(\\FSM_sequential_cal1_state_r[4]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h1000101010101010)) \n \\FSM_sequential_cal1_state_r[4]_i_5 \n (.I0(out[0]),\n .I1(out[1]),\n .I2(out[4]),\n .I3(\\FSM_sequential_cal1_state_r[1]_i_7_n_0 ),\n .I4(out[3]),\n .I5(mpr_dec_cpt_r_reg_0),\n .O(\\FSM_sequential_cal1_state_r[4]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'h55404440)) \n \\FSM_sequential_cal1_state_r[4]_i_6 \n (.I0(out[2]),\n .I1(out[1]),\n .I2(out[3]),\n .I3(out[0]),\n .I4(out[4]),\n .O(\\FSM_sequential_cal1_state_r[4]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair204\" *) \n LUT4 #(\n .INIT(16'hFFFD)) \n \\FSM_sequential_cal1_state_r[4]_i_7 \n (.I0(\\cnt_idel_dec_cpt_r_reg_n_0_[0] ),\n .I1(\\cnt_idel_dec_cpt_r_reg_n_0_[5] ),\n .I2(\\cnt_idel_dec_cpt_r_reg_n_0_[3] ),\n .I3(\\cnt_idel_dec_cpt_r_reg_n_0_[4] ),\n .O(\\FSM_sequential_cal1_state_r[4]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair109\" *) \n LUT5 #(\n .INIT(32'hFFFEFFFF)) \n \\FSM_sequential_cal1_state_r[4]_i_8 \n (.I0(idelay_tap_cnt_r[4]),\n .I1(idelay_tap_cnt_r[3]),\n .I2(idelay_tap_cnt_r[2]),\n .I3(idelay_tap_cnt_r[1]),\n .I4(\\idel_dec_cnt[0]_i_2_n_0 ),\n .O(stable_idel_cnt22_in));\n LUT6 #(\n .INIT(64'h101F101F101F1010)) \n \\FSM_sequential_cal1_state_r[5]_i_1 \n (.I0(cal1_state_r),\n .I1(\\FSM_sequential_cal1_state_r[5]_i_3_n_0 ),\n .I2(out[4]),\n .I3(out[3]),\n .I4(\\FSM_sequential_cal1_state_r[5]_i_4_n_0 ),\n .I5(\\FSM_sequential_cal1_state_r[5]_i_5_n_0 ),\n .O(\\FSM_sequential_cal1_state_r[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0FF00FF050005FC0)) \n \\FSM_sequential_cal1_state_r[5]_i_11 \n (.I0(mpr_rdlvl_done_r1_reg_0),\n .I1(mpr_valid_r1_reg_0),\n .I2(out[0]),\n .I3(cal1_state_r),\n .I4(cal1_wait_r),\n .I5(out[1]),\n .O(\\FSM_sequential_cal1_state_r[5]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'h00005400FC00FC00)) \n \\FSM_sequential_cal1_state_r[5]_i_2 \n (.I0(\\rnk_cnt_r_reg_n_0_[0] ),\n .I1(out[3]),\n .I2(cal1_state_r),\n .I3(\\FSM_sequential_cal1_state_r[5]_i_6_n_0 ),\n .I4(\\rnk_cnt_r_reg_n_0_[1] ),\n .I5(\\FSM_sequential_cal1_state_r[5]_i_7_n_0 ),\n .O(\\FSM_sequential_cal1_state_r[5]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000B0B1FBF5B0B1)) \n \\FSM_sequential_cal1_state_r[5]_i_3 \n (.I0(out[3]),\n .I1(out[2]),\n .I2(cal1_wait_r),\n .I3(out[1]),\n .I4(out[0]),\n .I5(\\FSM_sequential_cal1_state_r[5]_i_8_n_0 ),\n .O(\\FSM_sequential_cal1_state_r[5]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0007FFFF00070000)) \n \\FSM_sequential_cal1_state_r[5]_i_4 \n (.I0(cal1_wait_r),\n .I1(out[0]),\n .I2(cal1_state_r),\n .I3(out[1]),\n .I4(out[2]),\n .I5(\\FSM_sequential_cal1_state_r[5]_i_9_n_0 ),\n .O(\\FSM_sequential_cal1_state_r[5]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h0000000010111010)) \n \\FSM_sequential_cal1_state_r[5]_i_5 \n (.I0(out[0]),\n .I1(cal1_state_r),\n .I2(cal1_state_r1535_out),\n .I3(rdlvl_stg1_start_r),\n .I4(rdlvl_stg1_start_reg),\n .I5(out[1]),\n .O(\\FSM_sequential_cal1_state_r[5]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'hC0FE00CC)) \n \\FSM_sequential_cal1_state_r[5]_i_6 \n (.I0(mpr_rdlvl_done_r1_reg_0),\n .I1(out[1]),\n .I2(out[2]),\n .I3(out[4]),\n .I4(out[0]),\n .O(\\FSM_sequential_cal1_state_r[5]_i_6_n_0 ));\n LUT5 #(\n .INIT(32'h80000000)) \n \\FSM_sequential_cal1_state_r[5]_i_7 \n (.I0(mpr_rdlvl_done_r1_reg_0),\n .I1(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I2(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .I3(out[1]),\n .I4(out[0]),\n .O(\\FSM_sequential_cal1_state_r[5]_i_7_n_0 ));\n LUT5 #(\n .INIT(32'hC000EEEE)) \n \\FSM_sequential_cal1_state_r[5]_i_8 \n (.I0(detect_edge_done_r),\n .I1(out[3]),\n .I2(out[1]),\n .I3(prech_done),\n .I4(out[2]),\n .O(\\FSM_sequential_cal1_state_r[5]_i_8_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF00D0)) \n \\FSM_sequential_cal1_state_r[5]_i_9 \n (.I0(cal1_wait_r),\n .I1(store_sr_req_r_reg_0),\n .I2(out[1]),\n .I3(cal1_state_r),\n .I4(\\FSM_sequential_cal1_state_r[5]_i_11_n_0 ),\n .O(\\FSM_sequential_cal1_state_r[5]_i_9_n_0 ));\n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\FSM_sequential_cal1_state_r_reg[0] \n (.C(CLK),\n .CE(\\FSM_sequential_cal1_state_r[5]_i_1_n_0 ),\n .D(\\FSM_sequential_cal1_state_r[0]_i_1_n_0 ),\n .Q(out[0]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\FSM_sequential_cal1_state_r_reg[1] \n (.C(CLK),\n .CE(\\FSM_sequential_cal1_state_r[5]_i_1_n_0 ),\n .D(\\FSM_sequential_cal1_state_r[1]_i_1_n_0 ),\n .Q(out[1]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n MUXF7 \\FSM_sequential_cal1_state_r_reg[1]_i_5 \n (.I0(\\FSM_sequential_cal1_state_r[1]_i_8_n_0 ),\n .I1(\\FSM_sequential_cal1_state_r[1]_i_9_n_0 ),\n .O(\\FSM_sequential_cal1_state_r_reg[1]_i_5_n_0 ),\n .S(out[1]));\n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\FSM_sequential_cal1_state_r_reg[2] \n (.C(CLK),\n .CE(\\FSM_sequential_cal1_state_r[5]_i_1_n_0 ),\n .D(\\FSM_sequential_cal1_state_r[2]_i_1_n_0 ),\n .Q(out[2]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n MUXF7 \\FSM_sequential_cal1_state_r_reg[2]_i_2 \n (.I0(\\FSM_sequential_cal1_state_r[2]_i_3_n_0 ),\n .I1(\\FSM_sequential_cal1_state_r[2]_i_4_n_0 ),\n .O(\\FSM_sequential_cal1_state_r_reg[2]_i_2_n_0 ),\n .S(out[1]));\n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\FSM_sequential_cal1_state_r_reg[3] \n (.C(CLK),\n .CE(\\FSM_sequential_cal1_state_r[5]_i_1_n_0 ),\n .D(\\FSM_sequential_cal1_state_r[3]_i_1_n_0 ),\n .Q(out[3]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\FSM_sequential_cal1_state_r_reg[4] \n (.C(CLK),\n .CE(\\FSM_sequential_cal1_state_r[5]_i_1_n_0 ),\n .D(\\FSM_sequential_cal1_state_r[4]_i_1_n_0 ),\n .Q(out[4]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\FSM_sequential_cal1_state_r_reg[5] \n (.C(CLK),\n .CE(\\FSM_sequential_cal1_state_r[5]_i_1_n_0 ),\n .D(\\FSM_sequential_cal1_state_r[5]_i_2_n_0 ),\n .Q(cal1_state_r),\n .R(rstdiv0_sync_r1_reg_rep__2));\n LUT3 #(\n .INIT(8'h34)) \n \\cal1_cnt_cpt_r[0]_i_1 \n (.I0(cal1_state_r),\n .I1(\\cal1_cnt_cpt_r[1]_i_3_n_0 ),\n .I2(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .O(\\cal1_cnt_cpt_r[0]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h1F20)) \n \\cal1_cnt_cpt_r[1]_i_2 \n (.I0(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .I1(cal1_state_r),\n .I2(\\cal1_cnt_cpt_r[1]_i_3_n_0 ),\n .I3(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .O(\\cal1_cnt_cpt_r[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00800A0000000000)) \n \\cal1_cnt_cpt_r[1]_i_3 \n (.I0(out[1]),\n .I1(\\cal1_cnt_cpt_r[1]_i_4_n_0 ),\n .I2(out[3]),\n .I3(cal1_state_r),\n .I4(out[4]),\n .I5(\\cal1_cnt_cpt_r[1]_i_5_n_0 ),\n .O(\\cal1_cnt_cpt_r[1]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAA2AAAAAAAAA)) \n \\cal1_cnt_cpt_r[1]_i_4 \n (.I0(prech_done),\n .I1(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .I2(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I3(\\rnk_cnt_r_reg_n_0_[0] ),\n .I4(\\rnk_cnt_r_reg_n_0_[1] ),\n .I5(mpr_rdlvl_done_r1_reg_0),\n .O(\\cal1_cnt_cpt_r[1]_i_4_n_0 ));\n LUT3 #(\n .INIT(8'h81)) \n \\cal1_cnt_cpt_r[1]_i_5 \n (.I0(out[0]),\n .I1(out[2]),\n .I2(out[3]),\n .O(\\cal1_cnt_cpt_r[1]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cal1_cnt_cpt_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cal1_cnt_cpt_r[0]_i_1_n_0 ),\n .Q(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE #(\n .INIT(1'b0)) \n \\cal1_cnt_cpt_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cal1_cnt_cpt_r[1]_i_2_n_0 ),\n .Q(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n LUT6 #(\n .INIT(64'h0010000000003000)) \n cal1_dlyce_cpt_r_i_1\n (.I0(tap_limit_cpt_r),\n .I1(cal1_state_r),\n .I2(cal1_dlyce_cpt_r_i_2_n_0),\n .I3(out[2]),\n .I4(out[4]),\n .I5(out[3]),\n .O(cal1_dlyce_cpt_r));\n LUT3 #(\n .INIT(8'h24)) \n cal1_dlyce_cpt_r_i_2\n (.I0(out[0]),\n .I1(out[2]),\n .I2(out[1]),\n .O(cal1_dlyce_cpt_r_i_2_n_0));\n FDRE #(\n .INIT(1'b0)) \n cal1_dlyce_cpt_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cal1_dlyce_cpt_r),\n .Q(cal1_dlyce_cpt_r_reg_n_0),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n LUT6 #(\n .INIT(64'h0000000001000000)) \n cal1_dlyinc_cpt_r_i_1\n (.I0(out[2]),\n .I1(tap_limit_cpt_r),\n .I2(cal1_state_r),\n .I3(out[1]),\n .I4(out[0]),\n .I5(cal1_dlyinc_cpt_r_i_2_n_0),\n .O(cal1_dlyinc_cpt_r));\n LUT2 #(\n .INIT(4'h7)) \n cal1_dlyinc_cpt_r_i_2\n (.I0(out[3]),\n .I1(out[4]),\n .O(cal1_dlyinc_cpt_r_i_2_n_0));\n FDRE #(\n .INIT(1'b0)) \n cal1_dlyinc_cpt_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cal1_dlyinc_cpt_r),\n .Q(cal1_dlyinc_cpt_r_reg_n_0),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n LUT5 #(\n .INIT(32'h00000020)) \n cal1_dq_idel_ce_i_1\n (.I0(out[2]),\n .I1(out[3]),\n .I2(out[4]),\n .I3(out[0]),\n .I4(cal1_state_r),\n .O(cal1_dq_idel_ce));\n FDRE #(\n .INIT(1'b0)) \n cal1_dq_idel_ce_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cal1_dq_idel_ce),\n .Q(idelay_ce_int),\n .R(rstdiv0_sync_r1_reg_rep__13));\n LUT6 #(\n .INIT(64'h0000000000001000)) \n cal1_dq_idel_inc_i_1\n (.I0(cal1_state_r),\n .I1(out[1]),\n .I2(out[4]),\n .I3(out[2]),\n .I4(out[3]),\n .I5(out[0]),\n .O(cal1_dq_idel_inc));\n FDRE #(\n .INIT(1'b0)) \n cal1_dq_idel_inc_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cal1_dq_idel_inc),\n .Q(idelay_inc_int),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n LUT6 #(\n .INIT(64'h2000000000000000)) \n cal1_prech_req_r_i_1\n (.I0(out[4]),\n .I1(cal1_state_r),\n .I2(out[2]),\n .I3(out[3]),\n .I4(out[1]),\n .I5(out[0]),\n .O(cal1_prech_req_r));\n FDRE #(\n .INIT(1'b0)) \n cal1_prech_req_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cal1_prech_req_r),\n .Q(cal1_prech_req_r_reg_n_0),\n .R(rstdiv0_sync_r1_reg_rep__13));\n LUT6 #(\n .INIT(64'h00404000501F500C)) \n \\cal1_state_r1[0]_i_1 \n (.I0(cal1_state_r),\n .I1(out[1]),\n .I2(out[4]),\n .I3(out[3]),\n .I4(out[0]),\n .I5(out[2]),\n .O(\\cal1_state_r1[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h090A010E00045440)) \n \\cal1_state_r1[1]_i_1 \n (.I0(out[3]),\n .I1(out[0]),\n .I2(cal1_state_r),\n .I3(out[1]),\n .I4(out[2]),\n .I5(out[4]),\n .O(\\cal1_state_r1[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000CA0F1102C)) \n \\cal1_state_r1[2]_i_1 \n (.I0(out[1]),\n .I1(out[0]),\n .I2(out[4]),\n .I3(out[3]),\n .I4(out[2]),\n .I5(cal1_state_r),\n .O(\\cal1_state_r1[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0101C54901008482)) \n \\cal1_state_r1[3]_i_1 \n (.I0(out[2]),\n .I1(out[4]),\n .I2(out[3]),\n .I3(out[1]),\n .I4(cal1_state_r),\n .I5(out[0]),\n .O(\\cal1_state_r1[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0100004500000440)) \n \\cal1_state_r1[4]_i_1 \n (.I0(out[3]),\n .I1(out[1]),\n .I2(cal1_state_r),\n .I3(out[4]),\n .I4(out[2]),\n .I5(out[0]),\n .O(\\cal1_state_r1[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h1000000800004002)) \n \\cal1_state_r1[5]_i_1 \n (.I0(cal1_state_r),\n .I1(out[1]),\n .I2(out[4]),\n .I3(out[3]),\n .I4(out[2]),\n .I5(out[0]),\n .O(\\cal1_state_r1[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cal1_state_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cal1_state_r1[0]_i_1_n_0 ),\n .Q(\\cal1_state_r1_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cal1_state_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cal1_state_r1[1]_i_1_n_0 ),\n .Q(\\cal1_state_r1_reg_n_0_[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cal1_state_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cal1_state_r1[2]_i_1_n_0 ),\n .Q(\\cal1_state_r1_reg_n_0_[2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cal1_state_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cal1_state_r1[3]_i_1_n_0 ),\n .Q(\\cal1_state_r1_reg_n_0_[3] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cal1_state_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cal1_state_r1[4]_i_1_n_0 ),\n .Q(\\cal1_state_r1_reg_n_0_[4] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cal1_state_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cal1_state_r1[5]_i_1_n_0 ),\n .Q(\\cal1_state_r1_reg_n_0_[5] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h06090C0600090F12)) \n cal1_wait_cnt_en_r_i_1\n (.I0(out[1]),\n .I1(out[3]),\n .I2(cal1_state_r),\n .I3(out[4]),\n .I4(out[0]),\n .I5(out[2]),\n .O(cal1_wait_cnt_en_r0));\n FDRE #(\n .INIT(1'b0)) \n cal1_wait_cnt_en_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cal1_wait_cnt_en_r0),\n .Q(cal1_wait_cnt_en_r),\n .R(1'b0));\n LUT1 #(\n .INIT(2'h1)) \n \\cal1_wait_cnt_r[0]_i_1 \n (.I0(cal1_wait_cnt_r_reg__0[0]),\n .O(p_0_in__0__0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair237\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\cal1_wait_cnt_r[1]_i_1 \n (.I0(cal1_wait_cnt_r_reg__0[1]),\n .I1(cal1_wait_cnt_r_reg__0[0]),\n .O(p_0_in__0__0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair237\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\cal1_wait_cnt_r[2]_i_1 \n (.I0(cal1_wait_cnt_r_reg__0[2]),\n .I1(cal1_wait_cnt_r_reg__0[0]),\n .I2(cal1_wait_cnt_r_reg__0[1]),\n .O(p_0_in__0__0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair192\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\cal1_wait_cnt_r[3]_i_1 \n (.I0(cal1_wait_cnt_r_reg__0[3]),\n .I1(cal1_wait_cnt_r_reg__0[1]),\n .I2(cal1_wait_cnt_r_reg__0[0]),\n .I3(cal1_wait_cnt_r_reg__0[2]),\n .O(p_0_in__0__0[3]));\n LUT6 #(\n .INIT(64'h40000000FFFFFFFF)) \n \\cal1_wait_cnt_r[4]_i_1 \n (.I0(cal1_wait_cnt_r_reg__0[4]),\n .I1(cal1_wait_cnt_r_reg__0[3]),\n .I2(cal1_wait_cnt_r_reg__0[1]),\n .I3(cal1_wait_cnt_r_reg__0[0]),\n .I4(cal1_wait_cnt_r_reg__0[2]),\n .I5(cal1_wait_cnt_en_r),\n .O(\\cal1_wait_cnt_r[4]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair192\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\cal1_wait_cnt_r[4]_i_2 \n (.I0(cal1_wait_cnt_r_reg__0[4]),\n .I1(cal1_wait_cnt_r_reg__0[2]),\n .I2(cal1_wait_cnt_r_reg__0[0]),\n .I3(cal1_wait_cnt_r_reg__0[1]),\n .I4(cal1_wait_cnt_r_reg__0[3]),\n .O(p_0_in__0__0[4]));\n FDRE #(\n .INIT(1'b0)) \n \\cal1_wait_cnt_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0__0[0]),\n .Q(cal1_wait_cnt_r_reg__0[0]),\n .R(\\cal1_wait_cnt_r[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cal1_wait_cnt_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0__0[1]),\n .Q(cal1_wait_cnt_r_reg__0[1]),\n .R(\\cal1_wait_cnt_r[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cal1_wait_cnt_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0__0[2]),\n .Q(cal1_wait_cnt_r_reg__0[2]),\n .R(\\cal1_wait_cnt_r[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cal1_wait_cnt_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0__0[3]),\n .Q(cal1_wait_cnt_r_reg__0[3]),\n .R(\\cal1_wait_cnt_r[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cal1_wait_cnt_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0__0[4]),\n .Q(cal1_wait_cnt_r_reg__0[4]),\n .R(\\cal1_wait_cnt_r[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hBFFFFFFFFFFFFFFF)) \n cal1_wait_r_i_1\n (.I0(cal1_wait_cnt_r_reg__0[4]),\n .I1(cal1_wait_cnt_r_reg__0[3]),\n .I2(cal1_wait_cnt_r_reg__0[1]),\n .I3(cal1_wait_cnt_r_reg__0[0]),\n .I4(cal1_wait_cnt_r_reg__0[2]),\n .I5(cal1_wait_cnt_en_r),\n .O(cal1_wait_r_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n cal1_wait_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cal1_wait_r_i_1_n_0),\n .Q(cal1_wait_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h74FF7400)) \n \\cnt_idel_dec_cpt_r[0]_i_1 \n (.I0(cnt_idel_dec_cpt_r2[1]),\n .I1(\\cnt_idel_dec_cpt_r_reg[0]_0 ),\n .I2(\\cnt_idel_dec_cpt_r[0]_i_2_n_0 ),\n .I3(out[0]),\n .I4(\\cnt_idel_dec_cpt_r[0]_i_3_n_0 ),\n .O(cnt_idel_dec_cpt_r[0]));\n LUT6 #(\n .INIT(64'hB800B8FFB8FFB800)) \n \\cnt_idel_dec_cpt_r[0]_i_2 \n (.I0(\\cnt_idel_dec_cpt_r_reg[1]_i_9_n_6 ),\n .I1(\\right_edge_taps_r_reg[0]_0 ),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .I3(\\cnt_idel_dec_cpt_r[5]_i_8_n_0 ),\n .I4(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .I5(right_edge_taps_r__0[1]),\n .O(\\cnt_idel_dec_cpt_r[0]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'h404F)) \n \\cnt_idel_dec_cpt_r[0]_i_3 \n (.I0(\\calib_sel_reg[3] [2]),\n .I1(\\pi_counter_read_val_reg[5] [0]),\n .I2(out[1]),\n .I3(\\cnt_idel_dec_cpt_r_reg_n_0_[0] ),\n .O(\\cnt_idel_dec_cpt_r[0]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h6F60FFFF6F600000)) \n \\cnt_idel_dec_cpt_r[1]_i_1 \n (.I0(cnt_idel_dec_cpt_r2[2]),\n .I1(cnt_idel_dec_cpt_r2[1]),\n .I2(\\cnt_idel_dec_cpt_r_reg[0]_0 ),\n .I3(\\cnt_idel_dec_cpt_r[1]_i_3_n_0 ),\n .I4(out[0]),\n .I5(\\cnt_idel_dec_cpt_r[1]_i_4_n_0 ),\n .O(cnt_idel_dec_cpt_r[1]));\n (* SOFT_HLUTNM = \"soft_lutpair207\" *) \n LUT4 #(\n .INIT(16'h4BB4)) \n \\cnt_idel_dec_cpt_r[1]_i_10 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .I1(right_edge_taps_r__0[1]),\n .I2(right_edge_taps_r__0[2]),\n .I3(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .O(\\cnt_idel_dec_cpt_r[1]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\cnt_idel_dec_cpt_r[1]_i_11 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .I1(\\first_edge_taps_r_reg_n_0_[3] ),\n .O(\\cnt_idel_dec_cpt_r[1]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\cnt_idel_dec_cpt_r[1]_i_12 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .I1(\\first_edge_taps_r_reg_n_0_[2] ),\n .O(\\cnt_idel_dec_cpt_r[1]_i_12_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\cnt_idel_dec_cpt_r[1]_i_13 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .I1(\\first_edge_taps_r_reg_n_0_[1] ),\n .O(\\cnt_idel_dec_cpt_r[1]_i_13_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\cnt_idel_dec_cpt_r[1]_i_14 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .I1(\\first_edge_taps_r_reg_n_0_[0] ),\n .O(\\cnt_idel_dec_cpt_r[1]_i_14_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\cnt_idel_dec_cpt_r[1]_i_3 \n (.I0(\\cnt_idel_dec_cpt_r_reg[1]_i_9_n_5 ),\n .I1(\\right_edge_taps_r_reg[0]_0 ),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .I3(\\cnt_idel_dec_cpt_r[5]_i_8_n_0 ),\n .I4(\\cnt_idel_dec_cpt_r[1]_i_10_n_0 ),\n .O(\\cnt_idel_dec_cpt_r[1]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'h4F40404F)) \n \\cnt_idel_dec_cpt_r[1]_i_4 \n (.I0(\\calib_sel_reg[3] [2]),\n .I1(\\pi_counter_read_val_reg[5] [1]),\n .I2(out[1]),\n .I3(\\cnt_idel_dec_cpt_r_reg_n_0_[0] ),\n .I4(\\cnt_idel_dec_cpt_r_reg_n_0_[1] ),\n .O(\\cnt_idel_dec_cpt_r[1]_i_4_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\cnt_idel_dec_cpt_r[1]_i_5 \n (.I0(\\second_edge_taps_r_reg_n_0_[3] ),\n .I1(\\first_edge_taps_r_reg_n_0_[3] ),\n .O(\\cnt_idel_dec_cpt_r[1]_i_5_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\cnt_idel_dec_cpt_r[1]_i_6 \n (.I0(\\second_edge_taps_r_reg_n_0_[2] ),\n .I1(\\first_edge_taps_r_reg_n_0_[2] ),\n .O(\\cnt_idel_dec_cpt_r[1]_i_6_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\cnt_idel_dec_cpt_r[1]_i_7 \n (.I0(\\second_edge_taps_r_reg_n_0_[1] ),\n .I1(\\first_edge_taps_r_reg_n_0_[1] ),\n .O(\\cnt_idel_dec_cpt_r[1]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\cnt_idel_dec_cpt_r[1]_i_8 \n (.I0(\\second_edge_taps_r_reg_n_0_[0] ),\n .I1(\\first_edge_taps_r_reg_n_0_[0] ),\n .O(\\cnt_idel_dec_cpt_r[1]_i_8_n_0 ));\n LUT5 #(\n .INIT(32'hB8B8B88B)) \n \\cnt_idel_dec_cpt_r[2]_i_2 \n (.I0(\\rdlvl_cpt_tap_cnt_reg[2] ),\n .I1(out[1]),\n .I2(\\cnt_idel_dec_cpt_r_reg_n_0_[2] ),\n .I3(\\cnt_idel_dec_cpt_r_reg_n_0_[1] ),\n .I4(\\cnt_idel_dec_cpt_r_reg_n_0_[0] ),\n .O(\\cnt_idel_dec_cpt_r[2]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h6AFF6A00)) \n \\cnt_idel_dec_cpt_r[2]_i_3 \n (.I0(cnt_idel_dec_cpt_r2[3]),\n .I1(cnt_idel_dec_cpt_r2[1]),\n .I2(cnt_idel_dec_cpt_r2[2]),\n .I3(\\cnt_idel_dec_cpt_r_reg[0]_0 ),\n .I4(\\cnt_idel_dec_cpt_r[2]_i_4_n_0 ),\n .O(\\cnt_idel_dec_cpt_r[2]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\cnt_idel_dec_cpt_r[2]_i_4 \n (.I0(\\cnt_idel_dec_cpt_r_reg[1]_i_9_n_4 ),\n .I1(\\right_edge_taps_r_reg[0]_0 ),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .I3(\\cnt_idel_dec_cpt_r[5]_i_8_n_0 ),\n .I4(\\cnt_idel_dec_cpt_r[2]_i_5_n_0 ),\n .O(\\cnt_idel_dec_cpt_r[2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h40F4BF0BBF0B40F4)) \n \\cnt_idel_dec_cpt_r[2]_i_5 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .I1(right_edge_taps_r__0[1]),\n .I2(right_edge_taps_r__0[2]),\n .I3(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .I4(right_edge_taps_r__0[3]),\n .I5(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .O(\\cnt_idel_dec_cpt_r[2]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hB8B8B8B8B8B8B88B)) \n \\cnt_idel_dec_cpt_r[3]_i_2 \n (.I0(\\calib_sel_reg[3]_0 [1]),\n .I1(out[1]),\n .I2(\\cnt_idel_dec_cpt_r_reg_n_0_[3] ),\n .I3(\\cnt_idel_dec_cpt_r_reg_n_0_[2] ),\n .I4(\\cnt_idel_dec_cpt_r_reg_n_0_[0] ),\n .I5(\\cnt_idel_dec_cpt_r_reg_n_0_[1] ),\n .O(\\cnt_idel_dec_cpt_r[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h6AAAFFFF6AAA0000)) \n \\cnt_idel_dec_cpt_r[3]_i_3 \n (.I0(cnt_idel_dec_cpt_r2[4]),\n .I1(cnt_idel_dec_cpt_r2[2]),\n .I2(cnt_idel_dec_cpt_r2[1]),\n .I3(cnt_idel_dec_cpt_r2[3]),\n .I4(\\cnt_idel_dec_cpt_r_reg[0]_0 ),\n .I5(\\cnt_idel_dec_cpt_r[3]_i_4_n_0 ),\n .O(\\cnt_idel_dec_cpt_r[3]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\cnt_idel_dec_cpt_r[3]_i_4 \n (.I0(\\cnt_idel_dec_cpt_r_reg[4]_i_6_n_7 ),\n .I1(\\right_edge_taps_r_reg[0]_0 ),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[4] ),\n .I3(\\cnt_idel_dec_cpt_r[5]_i_8_n_0 ),\n .I4(\\cnt_idel_dec_cpt_r[3]_i_5_n_0 ),\n .O(\\cnt_idel_dec_cpt_r[3]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair107\" *) \n LUT3 #(\n .INIT(8'h96)) \n \\cnt_idel_dec_cpt_r[3]_i_5 \n (.I0(\\cnt_idel_dec_cpt_r[5]_i_11_n_0 ),\n .I1(right_edge_taps_r__0[4]),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .O(\\cnt_idel_dec_cpt_r[3]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hB888B8BBB8BBB888)) \n \\cnt_idel_dec_cpt_r[4]_i_1 \n (.I0(\\cnt_idel_dec_cpt_r_reg[4]_i_2_n_0 ),\n .I1(out[0]),\n .I2(\\rdlvl_cpt_tap_cnt_reg[4] ),\n .I3(out[1]),\n .I4(\\cnt_idel_dec_cpt_r_reg_n_0_[4] ),\n .I5(\\cnt_idel_dec_cpt_r[4]_i_3_n_0 ),\n .O(cnt_idel_dec_cpt_r[4]));\n (* SOFT_HLUTNM = \"soft_lutpair205\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\cnt_idel_dec_cpt_r[4]_i_3 \n (.I0(\\cnt_idel_dec_cpt_r_reg_n_0_[2] ),\n .I1(\\cnt_idel_dec_cpt_r_reg_n_0_[0] ),\n .I2(\\cnt_idel_dec_cpt_r_reg_n_0_[1] ),\n .I3(\\cnt_idel_dec_cpt_r_reg_n_0_[3] ),\n .O(\\cnt_idel_dec_cpt_r[4]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\cnt_idel_dec_cpt_r[4]_i_4 \n (.I0(\\cnt_idel_dec_cpt_r_reg[4]_i_6_n_6 ),\n .I1(\\right_edge_taps_r_reg[0]_0 ),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[5] ),\n .I3(\\cnt_idel_dec_cpt_r[5]_i_8_n_0 ),\n .I4(\\cnt_idel_dec_cpt_r[4]_i_7_n_0 ),\n .O(\\cnt_idel_dec_cpt_r[4]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\cnt_idel_dec_cpt_r[4]_i_5 \n (.I0(cnt_idel_dec_cpt_r2[5]),\n .I1(cnt_idel_dec_cpt_r2[3]),\n .I2(cnt_idel_dec_cpt_r2[1]),\n .I3(cnt_idel_dec_cpt_r2[2]),\n .I4(cnt_idel_dec_cpt_r2[4]),\n .O(\\cnt_idel_dec_cpt_r[4]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair107\" *) \n LUT5 #(\n .INIT(32'hB24D4DB2)) \n \\cnt_idel_dec_cpt_r[4]_i_7 \n (.I0(\\cnt_idel_dec_cpt_r[5]_i_11_n_0 ),\n .I1(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .I2(right_edge_taps_r__0[4]),\n .I3(right_edge_taps_r__0[5]),\n .I4(\\tap_cnt_cpt_r_reg_n_0_[4] ),\n .O(\\cnt_idel_dec_cpt_r[4]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\cnt_idel_dec_cpt_r[4]_i_8 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[5] ),\n .I1(\\first_edge_taps_r_reg_n_0_[5] ),\n .O(\\cnt_idel_dec_cpt_r[4]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\cnt_idel_dec_cpt_r[4]_i_9 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[4] ),\n .I1(\\first_edge_taps_r_reg_n_0_[4] ),\n .O(\\cnt_idel_dec_cpt_r[4]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'h0000008800222000)) \n \\cnt_idel_dec_cpt_r[5]_i_1 \n (.I0(\\cnt_idel_dec_cpt_r[5]_i_3_n_0 ),\n .I1(out[3]),\n .I2(store_sr_req_r_reg_0),\n .I3(out[1]),\n .I4(out[2]),\n .I5(out[0]),\n .O(\\cnt_idel_dec_cpt_r[5]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8000)) \n \\cnt_idel_dec_cpt_r[5]_i_10 \n (.I0(cnt_idel_dec_cpt_r2[4]),\n .I1(cnt_idel_dec_cpt_r2[2]),\n .I2(cnt_idel_dec_cpt_r2[1]),\n .I3(cnt_idel_dec_cpt_r2[3]),\n .O(\\cnt_idel_dec_cpt_r[5]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'h2B222222BBBB2B22)) \n \\cnt_idel_dec_cpt_r[5]_i_11 \n (.I0(right_edge_taps_r__0[3]),\n .I1(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .I3(right_edge_taps_r__0[1]),\n .I4(right_edge_taps_r__0[2]),\n .I5(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .O(\\cnt_idel_dec_cpt_r[5]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\cnt_idel_dec_cpt_r[5]_i_12 \n (.I0(\\second_edge_taps_r_reg_n_0_[5] ),\n .I1(\\first_edge_taps_r_reg_n_0_[5] ),\n .O(\\cnt_idel_dec_cpt_r[5]_i_12_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\cnt_idel_dec_cpt_r[5]_i_13 \n (.I0(\\second_edge_taps_r_reg_n_0_[4] ),\n .I1(\\first_edge_taps_r_reg_n_0_[4] ),\n .O(\\cnt_idel_dec_cpt_r[5]_i_13_n_0 ));\n LUT3 #(\n .INIT(8'h41)) \n \\cnt_idel_dec_cpt_r[5]_i_3 \n (.I0(cal1_state_r),\n .I1(out[4]),\n .I2(out[3]),\n .O(\\cnt_idel_dec_cpt_r[5]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\cnt_idel_dec_cpt_r[5]_i_4 \n (.I0(\\rdlvl_cpt_tap_cnt_reg[4] ),\n .I1(\\rdlvl_cpt_tap_cnt_reg[1] ),\n .I2(\\rdlvl_cpt_tap_cnt_reg[2] ),\n .I3(\\calib_sel_reg[3]_0 [1]),\n .I4(\\calib_sel_reg[3]_0 [0]),\n .I5(\\calib_sel_reg[3]_0 [2]),\n .O(store_sr_req_r_reg_0));\n LUT5 #(\n .INIT(32'hB88BB8B8)) \n \\cnt_idel_dec_cpt_r[5]_i_5 \n (.I0(\\calib_sel_reg[3]_0 [2]),\n .I1(out[1]),\n .I2(\\cnt_idel_dec_cpt_r_reg_n_0_[5] ),\n .I3(\\cnt_idel_dec_cpt_r_reg_n_0_[4] ),\n .I4(\\cnt_idel_dec_cpt_r[4]_i_3_n_0 ),\n .O(\\cnt_idel_dec_cpt_r[5]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hF00F0F0F11111111)) \n \\cnt_idel_dec_cpt_r[5]_i_6 \n (.I0(\\cnt_idel_dec_cpt_r[5]_i_7_n_0 ),\n .I1(\\cnt_idel_dec_cpt_r[5]_i_8_n_0 ),\n .I2(\\cnt_idel_dec_cpt_r_reg[5]_i_9_n_1 ),\n .I3(\\cnt_idel_dec_cpt_r[5]_i_10_n_0 ),\n .I4(cnt_idel_dec_cpt_r2[5]),\n .I5(\\cnt_idel_dec_cpt_r_reg[0]_0 ),\n .O(\\cnt_idel_dec_cpt_r[5]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h9A59AAAA55559A59)) \n \\cnt_idel_dec_cpt_r[5]_i_7 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[5] ),\n .I1(right_edge_taps_r__0[4]),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .I3(\\cnt_idel_dec_cpt_r[5]_i_11_n_0 ),\n .I4(\\tap_cnt_cpt_r_reg_n_0_[4] ),\n .I5(right_edge_taps_r__0[5]),\n .O(\\cnt_idel_dec_cpt_r[5]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000001)) \n \\cnt_idel_dec_cpt_r[5]_i_8 \n (.I0(right_edge_taps_r__0[2]),\n .I1(right_edge_taps_r__0[3]),\n .I2(right_edge_taps_r__0[1]),\n .I3(right_edge_taps_r__0[0]),\n .I4(right_edge_taps_r__0[5]),\n .I5(right_edge_taps_r__0[4]),\n .O(\\cnt_idel_dec_cpt_r[5]_i_8_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_idel_dec_cpt_r_reg[0] \n (.C(CLK),\n .CE(\\cnt_idel_dec_cpt_r[5]_i_1_n_0 ),\n .D(cnt_idel_dec_cpt_r[0]),\n .Q(\\cnt_idel_dec_cpt_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_idel_dec_cpt_r_reg[1] \n (.C(CLK),\n .CE(\\cnt_idel_dec_cpt_r[5]_i_1_n_0 ),\n .D(cnt_idel_dec_cpt_r[1]),\n .Q(\\cnt_idel_dec_cpt_r_reg_n_0_[1] ),\n .R(1'b0));\n CARRY4 \\cnt_idel_dec_cpt_r_reg[1]_i_2 \n (.CI(1'b0),\n .CO({\\cnt_idel_dec_cpt_r_reg[1]_i_2_n_0 ,\\cnt_idel_dec_cpt_r_reg[1]_i_2_n_1 ,\\cnt_idel_dec_cpt_r_reg[1]_i_2_n_2 ,\\cnt_idel_dec_cpt_r_reg[1]_i_2_n_3 }),\n .CYINIT(1'b1),\n .DI({\\second_edge_taps_r_reg_n_0_[3] ,\\second_edge_taps_r_reg_n_0_[2] ,\\second_edge_taps_r_reg_n_0_[1] ,\\second_edge_taps_r_reg_n_0_[0] }),\n .O({cnt_idel_dec_cpt_r2[3:1],\\NLW_cnt_idel_dec_cpt_r_reg[1]_i_2_O_UNCONNECTED [0]}),\n .S({\\cnt_idel_dec_cpt_r[1]_i_5_n_0 ,\\cnt_idel_dec_cpt_r[1]_i_6_n_0 ,\\cnt_idel_dec_cpt_r[1]_i_7_n_0 ,\\cnt_idel_dec_cpt_r[1]_i_8_n_0 }));\n CARRY4 \\cnt_idel_dec_cpt_r_reg[1]_i_9 \n (.CI(1'b0),\n .CO({\\cnt_idel_dec_cpt_r_reg[1]_i_9_n_0 ,\\cnt_idel_dec_cpt_r_reg[1]_i_9_n_1 ,\\cnt_idel_dec_cpt_r_reg[1]_i_9_n_2 ,\\cnt_idel_dec_cpt_r_reg[1]_i_9_n_3 }),\n .CYINIT(1'b1),\n .DI({\\tap_cnt_cpt_r_reg_n_0_[3] ,\\tap_cnt_cpt_r_reg_n_0_[2] ,\\tap_cnt_cpt_r_reg_n_0_[1] ,\\tap_cnt_cpt_r_reg_n_0_[0] }),\n .O({\\cnt_idel_dec_cpt_r_reg[1]_i_9_n_4 ,\\cnt_idel_dec_cpt_r_reg[1]_i_9_n_5 ,\\cnt_idel_dec_cpt_r_reg[1]_i_9_n_6 ,\\NLW_cnt_idel_dec_cpt_r_reg[1]_i_9_O_UNCONNECTED [0]}),\n .S({\\cnt_idel_dec_cpt_r[1]_i_11_n_0 ,\\cnt_idel_dec_cpt_r[1]_i_12_n_0 ,\\cnt_idel_dec_cpt_r[1]_i_13_n_0 ,\\cnt_idel_dec_cpt_r[1]_i_14_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_idel_dec_cpt_r_reg[2] \n (.C(CLK),\n .CE(\\cnt_idel_dec_cpt_r[5]_i_1_n_0 ),\n .D(cnt_idel_dec_cpt_r[2]),\n .Q(\\cnt_idel_dec_cpt_r_reg_n_0_[2] ),\n .R(1'b0));\n MUXF7 \\cnt_idel_dec_cpt_r_reg[2]_i_1 \n (.I0(\\cnt_idel_dec_cpt_r[2]_i_2_n_0 ),\n .I1(\\cnt_idel_dec_cpt_r[2]_i_3_n_0 ),\n .O(cnt_idel_dec_cpt_r[2]),\n .S(out[0]));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_idel_dec_cpt_r_reg[3] \n (.C(CLK),\n .CE(\\cnt_idel_dec_cpt_r[5]_i_1_n_0 ),\n .D(cnt_idel_dec_cpt_r[3]),\n .Q(\\cnt_idel_dec_cpt_r_reg_n_0_[3] ),\n .R(1'b0));\n MUXF7 \\cnt_idel_dec_cpt_r_reg[3]_i_1 \n (.I0(\\cnt_idel_dec_cpt_r[3]_i_2_n_0 ),\n .I1(\\cnt_idel_dec_cpt_r[3]_i_3_n_0 ),\n .O(cnt_idel_dec_cpt_r[3]),\n .S(out[0]));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_idel_dec_cpt_r_reg[4] \n (.C(CLK),\n .CE(\\cnt_idel_dec_cpt_r[5]_i_1_n_0 ),\n .D(cnt_idel_dec_cpt_r[4]),\n .Q(\\cnt_idel_dec_cpt_r_reg_n_0_[4] ),\n .R(1'b0));\n MUXF7 \\cnt_idel_dec_cpt_r_reg[4]_i_2 \n (.I0(\\cnt_idel_dec_cpt_r[4]_i_4_n_0 ),\n .I1(\\cnt_idel_dec_cpt_r[4]_i_5_n_0 ),\n .O(\\cnt_idel_dec_cpt_r_reg[4]_i_2_n_0 ),\n .S(\\cnt_idel_dec_cpt_r_reg[0]_0 ));\n CARRY4 \\cnt_idel_dec_cpt_r_reg[4]_i_6 \n (.CI(\\cnt_idel_dec_cpt_r_reg[1]_i_9_n_0 ),\n .CO({\\NLW_cnt_idel_dec_cpt_r_reg[4]_i_6_CO_UNCONNECTED [3:1],\\cnt_idel_dec_cpt_r_reg[4]_i_6_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,\\tap_cnt_cpt_r_reg_n_0_[4] }),\n .O({\\NLW_cnt_idel_dec_cpt_r_reg[4]_i_6_O_UNCONNECTED [3:2],\\cnt_idel_dec_cpt_r_reg[4]_i_6_n_6 ,\\cnt_idel_dec_cpt_r_reg[4]_i_6_n_7 }),\n .S({1'b0,1'b0,\\cnt_idel_dec_cpt_r[4]_i_8_n_0 ,\\cnt_idel_dec_cpt_r[4]_i_9_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_idel_dec_cpt_r_reg[5] \n (.C(CLK),\n .CE(\\cnt_idel_dec_cpt_r[5]_i_1_n_0 ),\n .D(cnt_idel_dec_cpt_r[5]),\n .Q(\\cnt_idel_dec_cpt_r_reg_n_0_[5] ),\n .R(1'b0));\n MUXF7 \\cnt_idel_dec_cpt_r_reg[5]_i_2 \n (.I0(\\cnt_idel_dec_cpt_r[5]_i_5_n_0 ),\n .I1(\\cnt_idel_dec_cpt_r[5]_i_6_n_0 ),\n .O(cnt_idel_dec_cpt_r[5]),\n .S(out[0]));\n CARRY4 \\cnt_idel_dec_cpt_r_reg[5]_i_9 \n (.CI(\\cnt_idel_dec_cpt_r_reg[1]_i_2_n_0 ),\n .CO({\\NLW_cnt_idel_dec_cpt_r_reg[5]_i_9_CO_UNCONNECTED [3],\\cnt_idel_dec_cpt_r_reg[5]_i_9_n_1 ,\\NLW_cnt_idel_dec_cpt_r_reg[5]_i_9_CO_UNCONNECTED [1],\\cnt_idel_dec_cpt_r_reg[5]_i_9_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,\\second_edge_taps_r_reg_n_0_[5] ,\\second_edge_taps_r_reg_n_0_[4] }),\n .O({\\NLW_cnt_idel_dec_cpt_r_reg[5]_i_9_O_UNCONNECTED [3:2],cnt_idel_dec_cpt_r2[5:4]}),\n .S({1'b0,1'b1,\\cnt_idel_dec_cpt_r[5]_i_12_n_0 ,\\cnt_idel_dec_cpt_r[5]_i_13_n_0 }));\n LUT6 #(\n .INIT(64'h00000000FFFFFFF7)) \n \\cnt_shift_r[0]_i_1 \n (.I0(rdlvl_stg1_start_reg),\n .I1(phy_rddata_en_1),\n .I2(cnt_shift_r_reg__0[1]),\n .I3(cnt_shift_r_reg__0[3]),\n .I4(cnt_shift_r_reg__0[2]),\n .I5(cnt_shift_r_reg__0[0]),\n .O(p_0_in__1[0]));\n (* SOFT_HLUTNM = \"soft_lutpair236\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\cnt_shift_r[1]_i_1 \n (.I0(cnt_shift_r_reg__0[1]),\n .I1(cnt_shift_r_reg__0[0]),\n .O(p_0_in__1[1]));\n (* SOFT_HLUTNM = \"soft_lutpair236\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\cnt_shift_r[2]_i_1 \n (.I0(cnt_shift_r_reg__0[2]),\n .I1(cnt_shift_r_reg__0[0]),\n .I2(cnt_shift_r_reg__0[1]),\n .O(p_0_in__1[2]));\n (* SOFT_HLUTNM = \"soft_lutpair198\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\cnt_shift_r[3]_i_3 \n (.I0(cnt_shift_r_reg__0[3]),\n .I1(cnt_shift_r_reg__0[1]),\n .I2(cnt_shift_r_reg__0[0]),\n .I3(cnt_shift_r_reg__0[2]),\n .O(p_0_in__1[3]));\n FDSE #(\n .INIT(1'b1)) \n \\cnt_shift_r_reg[0] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__1[0]),\n .Q(cnt_shift_r_reg__0[0]),\n .S(rdlvl_stg1_start_reg_0));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_shift_r_reg[1] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__1[1]),\n .Q(cnt_shift_r_reg__0[1]),\n .R(rdlvl_stg1_start_reg_0));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_shift_r_reg[2] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__1[2]),\n .Q(cnt_shift_r_reg__0[2]),\n .R(rdlvl_stg1_start_reg_0));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_shift_r_reg[3] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__1[3]),\n .Q(cnt_shift_r_reg__0[3]),\n .R(rdlvl_stg1_start_reg_0));\n LUT2 #(\n .INIT(4'h8)) \n \\ctl_lane_cnt[1]_i_2 \n (.I0(pi_fine_dly_dec_done),\n .I1(dqs_po_dec_done),\n .O(cmd_delay_start0));\n LUT5 #(\n .INIT(32'h00008000)) \n detect_edge_done_r_i_1\n (.I0(pb_detect_edge_done_r[6]),\n .I1(pb_detect_edge_done_r[7]),\n .I2(pb_detect_edge_done_r[4]),\n .I3(pb_detect_edge_done_r[5]),\n .I4(detect_edge_done_r_i_2_n_0),\n .O(detect_edge_done_r_i_1_n_0));\n LUT4 #(\n .INIT(16'h7FFF)) \n detect_edge_done_r_i_2\n (.I0(pb_detect_edge_done_r[1]),\n .I1(pb_detect_edge_done_r[0]),\n .I2(pb_detect_edge_done_r[3]),\n .I3(pb_detect_edge_done_r[2]),\n .O(detect_edge_done_r_i_2_n_0));\n FDRE #(\n .INIT(1'b0)) \n detect_edge_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(detect_edge_done_r_i_1_n_0),\n .Q(detect_edge_done_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0000000000005554)) \n \\done_cnt[0]_i_1 \n (.I0(done_cnt[0]),\n .I1(done_cnt[1]),\n .I2(done_cnt[3]),\n .I3(done_cnt[2]),\n .I4(done_cnt1),\n .I5(rstdiv0_sync_r1_reg_rep__22),\n .O(\\done_cnt[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair193\" *) \n LUT5 #(\n .INIT(32'hFFAAAAFE)) \n \\done_cnt[1]_i_1 \n (.I0(done_cnt1),\n .I1(done_cnt[2]),\n .I2(done_cnt[3]),\n .I3(done_cnt[1]),\n .I4(done_cnt[0]),\n .O(\\done_cnt[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h000000000000EE10)) \n \\done_cnt[2]_i_1 \n (.I0(done_cnt[0]),\n .I1(done_cnt[1]),\n .I2(done_cnt[3]),\n .I3(done_cnt[2]),\n .I4(done_cnt1),\n .I5(rstdiv0_sync_r1_reg_rep__22),\n .O(\\done_cnt[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair193\" *) \n LUT5 #(\n .INIT(32'hFAFAFAEA)) \n \\done_cnt[3]_i_1 \n (.I0(done_cnt1),\n .I1(done_cnt[2]),\n .I2(done_cnt[3]),\n .I3(done_cnt[1]),\n .I4(done_cnt[0]),\n .O(\\done_cnt[3]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8F88)) \n \\done_cnt[3]_i_2 \n (.I0(\\done_cnt[3]_i_3_n_0 ),\n .I1(\\done_cnt[3]_i_4_n_0 ),\n .I2(\\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ),\n .I3(p_0_in539_in),\n .O(done_cnt1));\n (* SOFT_HLUTNM = \"soft_lutpair91\" *) \n LUT4 #(\n .INIT(16'h0004)) \n \\done_cnt[3]_i_3 \n (.I0(done_cnt[1]),\n .I1(done_cnt[0]),\n .I2(done_cnt[3]),\n .I3(done_cnt[2]),\n .O(\\done_cnt[3]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFF7)) \n \\done_cnt[3]_i_4 \n (.I0(cal1_state_r),\n .I1(out[0]),\n .I2(out[1]),\n .I3(out[3]),\n .I4(out[4]),\n .I5(out[2]),\n .O(\\done_cnt[3]_i_4_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\done_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\done_cnt[0]_i_1_n_0 ),\n .Q(done_cnt[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\done_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\done_cnt[1]_i_1_n_0 ),\n .Q(done_cnt[1]),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n \\done_cnt_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\done_cnt[2]_i_1_n_0 ),\n .Q(done_cnt[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\done_cnt_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\done_cnt[3]_i_1_n_0 ),\n .Q(done_cnt[3]),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n dqs_po_dec_done_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(dqs_po_dec_done),\n .Q(dqs_po_dec_done_r1),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n dqs_po_dec_done_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(dqs_po_dec_done_r1),\n .Q(dqs_po_dec_done_r2),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hFFFF22F2)) \n fine_dly_dec_done_r1_i_1\n (.I0(fine_dly_dec_done_r1_i_2_n_0),\n .I1(fine_dly_dec_done_r1_i_3_n_0),\n .I2(dqs_po_dec_done_r2),\n .I3(\\pi_rdval_cnt_reg[1]_0 ),\n .I4(fine_dly_dec_done_r1),\n .O(fine_dly_dec_done_r1_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair201\" *) \n LUT4 #(\n .INIT(16'h0010)) \n fine_dly_dec_done_r1_i_2\n (.I0(pi_rdval_cnt[1]),\n .I1(pi_rdval_cnt[2]),\n .I2(pi_rdval_cnt[0]),\n .I3(pi_rdval_cnt[4]),\n .O(fine_dly_dec_done_r1_i_2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair234\" *) \n LUT3 #(\n .INIT(8'hFB)) \n fine_dly_dec_done_r1_i_3\n (.I0(pi_rdval_cnt[5]),\n .I1(pi_en_stg2_f_timing_reg_0),\n .I2(pi_rdval_cnt[3]),\n .O(fine_dly_dec_done_r1_i_3_n_0));\n FDRE #(\n .INIT(1'b0)) \n fine_dly_dec_done_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(fine_dly_dec_done_r1_i_1_n_0),\n .Q(fine_dly_dec_done_r1),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE #(\n .INIT(1'b0)) \n fine_dly_dec_done_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(fine_dly_dec_done_r1),\n .Q(fine_dly_dec_done_r2),\n .R(1'b0));\n LUT3 #(\n .INIT(8'h80)) \n \\first_edge_taps_r[5]_i_1 \n (.I0(\\right_edge_taps_r_reg[0]_1 ),\n .I1(out[3]),\n .I2(out[2]),\n .O(\\first_edge_taps_r[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8888888800202020)) \n \\first_edge_taps_r[5]_i_2 \n (.I0(\\right_edge_taps_r_reg[0]_1 ),\n .I1(out[3]),\n .I2(\\right_edge_taps_r_reg[0]_2 ),\n .I3(found_stable_eye_last_r),\n .I4(\\right_edge_taps_r_reg[0]_0 ),\n .I5(out[2]),\n .O(\\first_edge_taps_r[5]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'h2000)) \n \\first_edge_taps_r[5]_i_3 \n (.I0(out[4]),\n .I1(cal1_state_r),\n .I2(out[0]),\n .I3(out[1]),\n .O(\\right_edge_taps_r_reg[0]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair222\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\first_edge_taps_r[5]_i_4 \n (.I0(detect_edge_done_r),\n .I1(found_first_edge_r_reg_0),\n .I2(tap_limit_cpt_r),\n .O(\\right_edge_taps_r_reg[0]_2 ));\n FDRE #(\n .INIT(1'b0)) \n \\first_edge_taps_r_reg[0] \n (.C(CLK),\n .CE(\\first_edge_taps_r[5]_i_2_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .Q(\\first_edge_taps_r_reg_n_0_[0] ),\n .R(\\first_edge_taps_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\first_edge_taps_r_reg[1] \n (.C(CLK),\n .CE(\\first_edge_taps_r[5]_i_2_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .Q(\\first_edge_taps_r_reg_n_0_[1] ),\n .R(\\first_edge_taps_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\first_edge_taps_r_reg[2] \n (.C(CLK),\n .CE(\\first_edge_taps_r[5]_i_2_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .Q(\\first_edge_taps_r_reg_n_0_[2] ),\n .R(\\first_edge_taps_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\first_edge_taps_r_reg[3] \n (.C(CLK),\n .CE(\\first_edge_taps_r[5]_i_2_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .Q(\\first_edge_taps_r_reg_n_0_[3] ),\n .R(\\first_edge_taps_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\first_edge_taps_r_reg[4] \n (.C(CLK),\n .CE(\\first_edge_taps_r[5]_i_2_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[4] ),\n .Q(\\first_edge_taps_r_reg_n_0_[4] ),\n .R(\\first_edge_taps_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\first_edge_taps_r_reg[5] \n (.C(CLK),\n .CE(\\first_edge_taps_r[5]_i_2_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[5] ),\n .Q(\\first_edge_taps_r_reg_n_0_[5] ),\n .R(\\first_edge_taps_r[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n found_edge_r_i_1\n (.I0(found_edge_r_reg_1),\n .I1(found_edge_r_reg_2),\n .I2(found_edge_r_reg_0),\n .I3(found_edge_r_reg_3),\n .I4(found_edge_r_i_2_n_0),\n .O(found_edge_r_i_1_n_0));\n LUT4 #(\n .INIT(16'hFFFE)) \n found_edge_r_i_2\n (.I0(\\gen_track_left_edge[7].pb_found_edge_r_reg[7]_0 ),\n .I1(\\gen_track_left_edge[4].pb_found_edge_r_reg[4]_0 ),\n .I2(\\gen_track_left_edge[6].pb_found_edge_r_reg[6]_0 ),\n .I3(\\gen_track_left_edge[0].pb_found_edge_r_reg[0]_0 ),\n .O(found_edge_r_i_2_n_0));\n FDRE #(\n .INIT(1'b0)) \n found_edge_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(found_edge_r_i_1_n_0),\n .Q(found_first_edge_r_reg_0),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n found_first_edge_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(found_edge_r_reg_4),\n .Q(\\right_edge_taps_r_reg[0]_0 ),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE #(\n .INIT(1'b0)) \n found_second_edge_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(found_stable_eye_last_r_reg_1),\n .Q(\\cnt_idel_dec_cpt_r_reg[0]_0 ),\n .R(SR));\n FDRE #(\n .INIT(1'b0)) \n found_stable_eye_last_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(found_stable_eye_r_reg_0),\n .Q(found_stable_eye_last_r),\n .R(pb_detect_edge_setup));\n LUT5 #(\n .INIT(32'h00008000)) \n found_stable_eye_r_i_1\n (.I0(\\gen_track_left_edge[7].pb_found_stable_eye_r_reg ),\n .I1(\\gen_track_left_edge[6].pb_found_stable_eye_r_reg ),\n .I2(\\gen_track_left_edge[4].pb_found_stable_eye_r_reg ),\n .I3(\\gen_track_left_edge[5].pb_found_stable_eye_r_reg ),\n .I4(found_stable_eye_r_i_2_n_0),\n .O(found_stable_eye_r_i_1_n_0));\n LUT4 #(\n .INIT(16'h7FFF)) \n found_stable_eye_r_i_2\n (.I0(\\gen_track_left_edge[1].pb_found_stable_eye_r_reg ),\n .I1(\\gen_track_left_edge[0].pb_found_stable_eye_r_reg ),\n .I2(\\gen_track_left_edge[3].pb_found_stable_eye_r_reg ),\n .I3(\\gen_track_left_edge[2].pb_found_stable_eye_r_reg ),\n .O(found_stable_eye_r_i_2_n_0));\n FDRE #(\n .INIT(1'b0)) \n found_stable_eye_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(found_stable_eye_r_i_1_n_0),\n .Q(found_stable_eye_last_r_reg_0),\n .R(1'b0));\n LUT3 #(\n .INIT(8'hB8)) \n \\gen_byte_sel_div1.byte_sel_cnt[0]_i_4 \n (.I0(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .I1(\\gen_byte_sel_div1.byte_sel_cnt[2]_i_8_n_0 ),\n .I2(regl_dqs_cnt_r[0]),\n .O(pi_stg2_rdlvl_cnt[0]));\n (* SOFT_HLUTNM = \"soft_lutpair230\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_byte_sel_div1.byte_sel_cnt[1]_i_4 \n (.I0(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I1(\\gen_byte_sel_div1.byte_sel_cnt[2]_i_8_n_0 ),\n .I2(regl_dqs_cnt_r[1]),\n .O(pi_stg2_rdlvl_cnt[1]));\n LUT6 #(\n .INIT(64'hF0F4F0F4FFF4F0F4)) \n \\gen_byte_sel_div1.byte_sel_cnt[2]_i_3 \n (.I0(\\gen_byte_sel_div1.byte_sel_cnt[2]_i_5_n_0 ),\n .I1(\\prbs_dqs_cnt_r_reg[2] ),\n .I2(\\po_stg2_wrcal_cnt_reg[2] ),\n .I3(\\gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 ),\n .I4(regl_dqs_cnt_r[2]),\n .I5(\\gen_byte_sel_div1.byte_sel_cnt[2]_i_8_n_0 ),\n .O(\\gen_byte_sel_div1.byte_sel_cnt_reg[2] ));\n (* SOFT_HLUTNM = \"soft_lutpair197\" *) \n LUT4 #(\n .INIT(16'hDFFF)) \n \\gen_byte_sel_div1.byte_sel_cnt[2]_i_5 \n (.I0(rdlvl_stg1_done_r1_reg),\n .I1(prbs_rdlvl_done_reg),\n .I2(wrcal_done_reg),\n .I3(oclkdelay_calib_done_r_reg),\n .O(\\gen_byte_sel_div1.byte_sel_cnt[2]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair206\" *) \n LUT4 #(\n .INIT(16'h08FF)) \n \\gen_byte_sel_div1.byte_sel_cnt[2]_i_7 \n (.I0(oclkdelay_calib_done_r_reg),\n .I1(wrcal_done_reg),\n .I2(rdlvl_stg1_done_r1_reg),\n .I3(mpr_rdlvl_done_r1_reg_0),\n .O(\\gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFF7)) \n \\gen_byte_sel_div1.byte_sel_cnt[2]_i_8 \n (.I0(cal1_state_r),\n .I1(out[1]),\n .I2(out[3]),\n .I3(out[0]),\n .I4(out[4]),\n .I5(out[2]),\n .O(\\gen_byte_sel_div1.byte_sel_cnt[2]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'h7FFFFFFFFFFFFFFF)) \n \\gen_byte_sel_div1.calib_in_common_i_3 \n (.I0(oclkdelay_calib_done_r_reg),\n .I1(wrcal_done_reg),\n .I2(prbs_rdlvl_done_reg),\n .I3(rdlvl_stg1_done_r1_reg),\n .I4(wr_level_done_reg),\n .I5(mpr_rdlvl_done_r1_reg_0),\n .O(\\gen_byte_sel_div1.calib_in_common_reg ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[0].mux_rd_fall0_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_8 ),\n .Q(\\gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[0].mux_rd_fall1_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_24 ),\n .Q(\\gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[0].mux_rd_fall2_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_40 ),\n .Q(\\gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[0].mux_rd_fall3_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_56 ),\n .Q(\\gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[0].mux_rd_rise0_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_0 ),\n .Q(\\gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[0].mux_rd_rise1_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_16 ),\n .Q(\\gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[0].mux_rd_rise2_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_32 ),\n .Q(\\gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[0].mux_rd_rise3_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_48 ),\n .Q(\\gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[1].mux_rd_fall0_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_9 ),\n .Q(\\gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[1].mux_rd_fall1_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_25 ),\n .Q(\\gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[1].mux_rd_fall2_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_41 ),\n .Q(\\gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[1].mux_rd_fall3_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_57 ),\n .Q(\\gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[1].mux_rd_rise0_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_1 ),\n .Q(\\gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[1].mux_rd_rise1_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_17 ),\n .Q(\\gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[1].mux_rd_rise2_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_33 ),\n .Q(\\gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[1].mux_rd_rise3_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_49 ),\n .Q(\\gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[2].mux_rd_fall0_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_10 ),\n .Q(\\gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[2].mux_rd_fall1_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_26 ),\n .Q(\\gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[2].mux_rd_fall2_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_42 ),\n .Q(\\gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[2].mux_rd_fall3_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_58 ),\n .Q(\\gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[2].mux_rd_rise0_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_2 ),\n .Q(\\gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[2].mux_rd_rise1_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_18 ),\n .Q(\\gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[2].mux_rd_rise2_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_34 ),\n .Q(\\gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[2].mux_rd_rise3_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_50 ),\n .Q(\\gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[3].mux_rd_fall0_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_11 ),\n .Q(\\gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[3].mux_rd_fall1_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_27 ),\n .Q(\\gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[3].mux_rd_fall2_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_43 ),\n .Q(\\gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[3].mux_rd_fall3_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_59 ),\n .Q(\\gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[3].mux_rd_rise0_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_3 ),\n .Q(\\gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[3].mux_rd_rise1_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_19 ),\n .Q(\\gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[3].mux_rd_rise2_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_35 ),\n .Q(\\gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[3].mux_rd_rise3_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_51 ),\n .Q(\\gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[4].mux_rd_fall0_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_12 ),\n .Q(\\gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[4].mux_rd_fall1_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_28 ),\n .Q(\\gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[4].mux_rd_fall2_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_44 ),\n .Q(\\gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[4].mux_rd_fall3_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_60 ),\n .Q(\\gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[4].mux_rd_rise0_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_4 ),\n .Q(\\gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[4].mux_rd_rise1_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_20 ),\n .Q(\\gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[4].mux_rd_rise2_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_36 ),\n .Q(\\gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[4].mux_rd_rise3_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_52 ),\n .Q(\\gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[5].mux_rd_fall0_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_13 ),\n .Q(\\gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[5].mux_rd_fall1_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_29 ),\n .Q(\\gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[5].mux_rd_fall2_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_45 ),\n .Q(\\gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[5].mux_rd_fall3_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_61 ),\n .Q(\\gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[5].mux_rd_rise0_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_5 ),\n .Q(\\gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[5].mux_rd_rise1_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_21 ),\n .Q(\\gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[5].mux_rd_rise2_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_37 ),\n .Q(\\gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[5].mux_rd_rise3_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_53 ),\n .Q(\\gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[6].mux_rd_fall0_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_14 ),\n .Q(\\gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[6].mux_rd_fall1_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_30 ),\n .Q(\\gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[6].mux_rd_fall2_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_46 ),\n .Q(\\gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[6].mux_rd_fall3_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_62 ),\n .Q(\\gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[6].mux_rd_rise0_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_6 ),\n .Q(\\gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[6].mux_rd_rise1_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_22 ),\n .Q(\\gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[6].mux_rd_rise2_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_38 ),\n .Q(\\gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[6].mux_rd_rise3_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_54 ),\n .Q(\\gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[7].mux_rd_fall0_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_15 ),\n .Q(\\gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[7].mux_rd_fall1_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_31 ),\n .Q(\\gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[7].mux_rd_fall2_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_47 ),\n .Q(\\gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[7].mux_rd_fall3_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_63 ),\n .Q(\\gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[7].mux_rd_rise0_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_7 ),\n .Q(\\gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[7].mux_rd_rise1_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_23 ),\n .Q(\\gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[7].mux_rd_rise2_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_39 ),\n .Q(\\gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd[7].mux_rd_rise3_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_55 ),\n .Q(\\gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_52 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0]_140 ),\n .R(1'b0));\n LUT3 #(\n .INIT(8'hA8)) \n \\gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r[0][0]_i_1 \n (.I0(\\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0]_0 ),\n .I1(sr_valid_r1_reg_0),\n .I2(mpr_valid_r1_reg_0),\n .O(store_sr_r0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_36 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0]_132 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_20 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0]_164 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_12 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0]_172 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_4 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0]_180 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_44 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0]_148 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_28 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0]_156 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_60 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0]_188 ),\n .R(1'b0));\n LUT2 #(\n .INIT(4'hE)) \n \\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r[0][0]_i_1 \n (.I0(sr_valid_r1_reg_0),\n .I1(mpr_valid_r1_reg_0),\n .O(store_sr_r1));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_52 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0]_68 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_36 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0]_108 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_20 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0]_124 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_12 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0]_100 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_4 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0]_92 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_44 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0]_76 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_28 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0]_84 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_60 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0]_116 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_53 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1]_141 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_37 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1]_133 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_21 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1]_165 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_13 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1]_173 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_5 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1]_181 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_45 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1]_149 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_29 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1]_157 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_61 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1]_189 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_53 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1]_69 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_37 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1]_109 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_21 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1]_125 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_13 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1]_101 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_5 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1]_93 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_45 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1]_77 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_29 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1]_85 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_61 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1]_117 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_54 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2]_142 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_38 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2]_134 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_22 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2]_166 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_14 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2]_174 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_6 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2]_182 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_46 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2]_150 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_30 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2]_158 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_62 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2]_190 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_54 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2]_70 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_38 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2]_110 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_22 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2]_126 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_14 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2]_102 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_6 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2]_94 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_46 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2]_78 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_30 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2]_86 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_62 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2]_118 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_55 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3]_143 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_39 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3]_135 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_23 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3]_167 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_15 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3]_175 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_7 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3]_183 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_47 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3]_151 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_31 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3]_159 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_63 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3]_191 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_55 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3]_71 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_39 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3]_111 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_23 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3]_127 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_15 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3]_103 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_7 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3]_95 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_47 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3]_79 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_31 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3]_87 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_63 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3]_119 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_56 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4]_144 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_40 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4]_136 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_24 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4]_168 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_16 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4]_176 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_8 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4]_184 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_48 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4]_152 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_32 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4]_160 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_64 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4]_192 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_56 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4]_72 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_40 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4]_112 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_24 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4]_128 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_16 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4]_104 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_8 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4]_96 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_48 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4]_80 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_32 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4]_88 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_64 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4]_120 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_57 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5]_145 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_41 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5]_137 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_25 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5]_169 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_17 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5]_177 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_9 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5]_185 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_49 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5]_153 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_33 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5]_161 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_65 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5]_193 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_57 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5]_73 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_41 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5]_113 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_25 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5]_129 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_17 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5]_105 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_9 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5]_97 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_49 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5]_81 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_33 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5]_89 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_65 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5]_121 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_58 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6]_146 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_42 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6]_138 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_26 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6]_170 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_18 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6]_178 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_10 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6]_186 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_50 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6]_154 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_34 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6]_162 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_66 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6]_194 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_58 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6]_74 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_42 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6]_114 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_26 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6]_130 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_18 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6]_106 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_10 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6]_98 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_50 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6]_82 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_34 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6]_90 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_66 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6]_122 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_59 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7]_147 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_43 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7]_139 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_27 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7]_171 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_19 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7]_179 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_11 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7]_187 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_51 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7]_155 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_35 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7]_163 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_67 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7]_195 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_59 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7]_75 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_43 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7]_115 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_27 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7]_131 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_19 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7]_107 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_11 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7]_99 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_51 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7]_83 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_35 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7]_91 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_67 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7]_123 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_52 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair150\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_36 ),\n .O(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair166\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_20 ),\n .O(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall3_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_12 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall3_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise0_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_4 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise0_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair118\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_44 ),\n .O(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_28 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair158\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_60 ),\n .O(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall1_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_36 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall1_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair142\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_12 ),\n .O(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair134\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_4 ),\n .O(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise1_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_44 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise1_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair126\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_28 ),\n .O(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise3_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_60 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair111\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_52 ),\n .O(\\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_20 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall0_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_53 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall0_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair151\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_37 ),\n .O(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_21 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_13 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair135\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_5 ),\n .O(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise1_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_45 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise1_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair127\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_29 ),\n .O(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair159\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_61 ),\n .O(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair112\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_53 ),\n .O(\\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_37 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair167\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_21 ),\n .O(\\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_rise2_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_29 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_rise2_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair143\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_13 ),\n .O(\\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise0_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_5 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise0_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair119\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_45 ),\n .O(\\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise3_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_61 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise3_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall0_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_54 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_38 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair168\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_22 ),\n .O(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair144\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_14 ),\n .O(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair136\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_6 ),\n .O(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise1_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_46 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise1_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair128\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_30 ),\n .O(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise3_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_62 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair113\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_54 ),\n .O(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall2_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_22 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise0_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_6 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise0_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair120\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_46 ),\n .O(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_30 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair160\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_62 ),\n .O(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair152\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_38 ),\n .O(\\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_14 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair114\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_55 ),\n .O(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall1_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_39 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall1_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair169\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_23 ),\n .O(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_15 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair137\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_7 ),\n .O(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise1_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_47 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise1_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_31 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair161\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_63 ),\n .O(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall0_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_55 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall0_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair153\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_39 ),\n .O(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_23 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair145\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_15 ),\n .O(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair174\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_47 ),\n .O(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise3_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_63 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair129\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_31 ),\n .O(\\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_7 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_56 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair154\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_40 ),\n .O(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair170\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_24 ),\n .O(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall3_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_16 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall3_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise0_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_8 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise0_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair122\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_48 ),\n .O(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_32 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair162\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_64 ),\n .O(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall1_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_40 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall1_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair146\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_16 ),\n .O(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair138\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_8 ),\n .O(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise1_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_48 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise1_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair130\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_32 ),\n .O(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise3_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_64 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair115\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_56 ),\n .O(\\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_24 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_57 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair155\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_41 ),\n .O(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_25 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_17 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair139\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_9 ),\n .O(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise1_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_49 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise1_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair131\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_33 ),\n .O(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair163\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_65 ),\n .O(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair116\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_57 ),\n .O(\\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_41 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair171\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_25 ),\n .O(\\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_rise2_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_33 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_rise2_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair147\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_17 ),\n .O(\\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise0_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_9 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise0_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair123\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_49 ),\n .O(\\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise3_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_65 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise3_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall0_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_58 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_42 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair172\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_26 ),\n .O(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair148\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_18 ),\n .O(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair140\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_10 ),\n .O(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise1_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_50 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise1_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair132\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_34 ),\n .O(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise3_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_66 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair121\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_58 ),\n .O(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall2_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_26 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise0_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_10 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise0_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair124\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_50 ),\n .O(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_34 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair164\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_66 ),\n .O(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair156\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_42 ),\n .O(\\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_18 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair117\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_59 ),\n .O(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_43 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair173\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_27 ),\n .O(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_19 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair141\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_11 ),\n .O(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise1_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_51 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise1_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_35 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair165\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_67 ),\n .O(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall0_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_59 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall0_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair157\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_43 ),\n .O(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_27 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair149\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_19 ),\n .O(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair125\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_51 ),\n .O(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise3_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_67 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair133\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_35 ),\n .O(\\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_11 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_pat_match_div4.idel_pat0_data_match_r_i_1 \n (.I0(idel_pat0_match_rise2_and_r),\n .I1(idel_pat0_match_fall2_and_r),\n .I2(idel_pat0_match_fall3_and_r),\n .I3(idel_pat0_match_rise0_and_r),\n .I4(\\gen_pat_match_div4.idel_pat0_data_match_r_i_2_n_0 ),\n .O(idel_pat0_data_match_r0__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_pat_match_div4.idel_pat0_data_match_r_i_2 \n (.I0(idel_pat0_match_fall0_and_r),\n .I1(idel_pat0_match_fall1_and_r),\n .I2(idel_pat0_match_rise3_and_r),\n .I3(idel_pat0_match_rise1_and_r),\n .O(\\gen_pat_match_div4.idel_pat0_data_match_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.idel_pat0_data_match_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(idel_pat0_data_match_r0__0),\n .Q(\\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg ),\n .I2(\\gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0 ),\n .I3(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall0_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg ),\n .I5(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall0_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.idel_pat0_match_fall0_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1_n_0 ),\n .Q(idel_pat0_match_fall0_and_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg ),\n .I2(\\gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0 ),\n .I3(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r_reg ),\n .I5(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.idel_pat0_match_fall1_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1_n_0 ),\n .Q(idel_pat0_match_fall1_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1 \n (.I0(\\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair185\" *) \n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.idel_pat0_match_fall2_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1_n_0 ),\n .Q(idel_pat0_match_fall2_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall3_r_reg ),\n .I4(\\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2_n_0 ),\n .O(\\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall3_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.idel_pat0_match_fall3_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1_n_0 ),\n .Q(idel_pat0_match_fall3_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1 \n (.I0(\\gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.idel_pat0_match_rise0_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1_n_0 ),\n .Q(idel_pat0_match_rise0_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1 \n (.I0(\\gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise1_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise1_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.idel_pat0_match_rise1_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1_n_0 ),\n .Q(idel_pat0_match_rise1_and_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair219\" *) \n LUT3 #(\n .INIT(8'h80)) \n \\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r_reg ),\n .I1(\\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2_n_0 ),\n .I2(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg ),\n .I5(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.idel_pat0_match_rise2_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1_n_0 ),\n .Q(idel_pat0_match_rise2_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1 \n (.I0(\\gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.idel_pat0_match_rise3_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1_n_0 ),\n .Q(idel_pat0_match_rise3_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_pat_match_div4.idel_pat1_data_match_r_i_1 \n (.I0(idel_pat1_match_rise2_and_r),\n .I1(idel_pat1_match_fall2_and_r),\n .I2(idel_pat1_match_fall3_and_r),\n .I3(idel_pat1_match_rise0_and_r),\n .I4(\\gen_pat_match_div4.idel_pat1_data_match_r_i_2_n_0 ),\n .O(idel_pat1_data_match_r0__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_pat_match_div4.idel_pat1_data_match_r_i_2 \n (.I0(idel_pat1_match_rise1_and_r),\n .I1(idel_pat1_match_fall1_and_r),\n .I2(idel_pat1_match_rise3_and_r),\n .I3(idel_pat1_match_fall0_and_r),\n .O(\\gen_pat_match_div4.idel_pat1_data_match_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.idel_pat1_data_match_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(idel_pat1_data_match_r0__0),\n .Q(\\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair223\" *) \n LUT3 #(\n .INIT(8'h80)) \n \\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg ),\n .I1(\\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2_n_0 ),\n .I2(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall0_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg__0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall0_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg__0 ),\n .I4(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg ),\n .I5(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.idel_pat1_match_fall0_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1_n_0 ),\n .Q(idel_pat1_match_fall0_and_r),\n .R(1'b0));\n LUT3 #(\n .INIT(8'h80)) \n \\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg ),\n .I1(\\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2_n_0 ),\n .I2(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg__0 ),\n .O(\\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall1_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall1_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg__0 ),\n .I4(\\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg ),\n .I5(\\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.idel_pat1_match_fall1_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1_n_0 ),\n .Q(idel_pat1_match_fall1_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1 \n (.I0(\\gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.idel_pat1_match_fall2_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1_n_0 ),\n .Q(idel_pat1_match_fall2_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1 \n (.I0(\\gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.idel_pat1_match_fall3_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1_n_0 ),\n .Q(idel_pat1_match_fall3_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1 \n (.I0(\\gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg__0 ),\n .I2(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg__0 ),\n .I3(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.idel_pat1_match_rise0_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1_n_0 ),\n .Q(idel_pat1_match_rise0_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1 \n (.I0(\\gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r_reg__0 ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r_reg__0 ),\n .I3(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.idel_pat1_match_rise1_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1_n_0 ),\n .Q(idel_pat1_match_rise1_and_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg ),\n .I2(\\gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0 ),\n .I3(\\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_rise2_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_rise2_r_reg ),\n .I5(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.idel_pat1_match_rise2_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1_n_0 ),\n .Q(idel_pat1_match_rise2_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1 \n (.I0(\\gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.idel_pat1_match_rise3_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1_n_0 ),\n .Q(idel_pat1_match_rise3_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_pat_match_div4.pat0_data_match_r_i_1 \n (.I0(pat0_match_fall2_and_r),\n .I1(pat0_match_rise2_and_r),\n .I2(pat0_match_fall3_and_r),\n .I3(pat0_match_rise0_and_r),\n .I4(\\gen_pat_match_div4.pat0_data_match_r_i_2_n_0 ),\n .O(pat0_data_match_r0__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_pat_match_div4.pat0_data_match_r_i_2 \n (.I0(pat0_match_rise1_and_r),\n .I1(pat0_match_fall1_and_r),\n .I2(pat0_match_rise3_and_r),\n .I3(pat0_match_fall0_and_r),\n .O(\\gen_pat_match_div4.pat0_data_match_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.pat0_data_match_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(pat0_data_match_r0__0),\n .Q(\\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair223\" *) \n LUT3 #(\n .INIT(8'h80)) \n \\gen_pat_match_div4.pat0_match_fall0_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall0_r_reg ),\n .I1(\\gen_pat_match_div4.pat0_match_fall0_and_r_i_2_n_0 ),\n .I2(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall0_r_reg ),\n .O(\\gen_pat_match_div4.pat0_match_fall0_and_r_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\gen_pat_match_div4.pat0_match_fall0_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r_reg__0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall0_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r_reg__0 ),\n .I3(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall0_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall0_r_reg ),\n .I5(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg ),\n .O(\\gen_pat_match_div4.pat0_match_fall0_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.pat0_match_fall0_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat0_match_fall0_and_r_i_1_n_0 ),\n .Q(pat0_match_fall0_and_r),\n .R(1'b0));\n LUT3 #(\n .INIT(8'h80)) \n \\gen_pat_match_div4.pat0_match_fall1_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r_reg__0 ),\n .I1(\\gen_pat_match_div4.pat0_match_fall1_and_r_i_2_n_0 ),\n .I2(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg ),\n .O(\\gen_pat_match_div4.pat0_match_fall1_and_r_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\gen_pat_match_div4.pat0_match_fall1_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall1_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall1_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r_reg__0 ),\n .I4(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall1_r_reg ),\n .I5(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r_reg ),\n .O(\\gen_pat_match_div4.pat0_match_fall1_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.pat0_match_fall1_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat0_match_fall1_and_r_i_1_n_0 ),\n .Q(pat0_match_fall1_and_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair185\" *) \n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.pat0_match_fall2_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r_reg ),\n .I4(\\gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0 ),\n .O(\\gen_pat_match_div4.pat0_match_fall2_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.pat0_match_fall2_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall2_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r_reg ),\n .O(\\gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.pat0_match_fall2_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat0_match_fall2_and_r_i_1_n_0 ),\n .Q(pat0_match_fall2_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.pat0_match_fall3_and_r_i_1 \n (.I0(\\gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall3_r_reg ),\n .O(\\gen_pat_match_div4.pat0_match_fall3_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.pat0_match_fall3_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r_reg ),\n .O(\\gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.pat0_match_fall3_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat0_match_fall3_and_r_i_1_n_0 ),\n .Q(pat0_match_fall3_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.pat0_match_rise0_and_r_i_1 \n (.I0(\\gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise0_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise0_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise0_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise0_r_reg ),\n .O(\\gen_pat_match_div4.pat0_match_rise0_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.pat0_match_rise0_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise0_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise0_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r_reg ),\n .O(\\gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.pat0_match_rise0_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat0_match_rise0_and_r_i_1_n_0 ),\n .Q(pat0_match_rise0_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.pat0_match_rise1_and_r_i_1 \n (.I0(\\gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r_reg__0 ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r_reg__0 ),\n .I3(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r_reg ),\n .O(\\gen_pat_match_div4.pat0_match_rise1_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.pat0_match_rise1_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise1_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise1_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise1_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise1_r_reg ),\n .O(\\gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.pat0_match_rise1_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat0_match_rise1_and_r_i_1_n_0 ),\n .Q(pat0_match_rise1_and_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair219\" *) \n LUT3 #(\n .INIT(8'h80)) \n \\gen_pat_match_div4.pat0_match_rise2_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r_reg__0 ),\n .I1(\\gen_pat_match_div4.pat0_match_rise2_and_r_i_2_n_0 ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r_reg ),\n .O(\\gen_pat_match_div4.pat0_match_rise2_and_r_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\gen_pat_match_div4.pat0_match_rise2_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_rise2_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r_reg__0 ),\n .I5(\\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_rise2_r_reg ),\n .O(\\gen_pat_match_div4.pat0_match_rise2_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.pat0_match_rise2_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat0_match_rise2_and_r_i_1_n_0 ),\n .Q(pat0_match_rise2_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.pat0_match_rise3_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise3_r_reg ),\n .I4(\\gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0 ),\n .O(\\gen_pat_match_div4.pat0_match_rise3_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.pat0_match_rise3_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise3_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise3_r_reg ),\n .O(\\gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.pat0_match_rise3_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat0_match_rise3_and_r_i_1_n_0 ),\n .Q(pat0_match_rise3_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_pat_match_div4.pat1_data_match_r_i_1 \n (.I0(pat1_match_rise2_and_r),\n .I1(pat1_match_fall1_and_r),\n .I2(pat1_match_fall3_and_r),\n .I3(pat1_match_rise0_and_r),\n .I4(\\gen_pat_match_div4.pat1_data_match_r_i_2_n_0 ),\n .O(pat1_data_match_r0__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_pat_match_div4.pat1_data_match_r_i_2 \n (.I0(pat1_match_fall0_and_r),\n .I1(pat1_match_rise1_and_r),\n .I2(pat1_match_rise3_and_r),\n .I3(pat1_match_fall2_and_r),\n .O(\\gen_pat_match_div4.pat1_data_match_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.pat1_data_match_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(pat1_data_match_r0__0),\n .Q(\\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\gen_pat_match_div4.pat1_match_fall0_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg ),\n .I2(\\gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0 ),\n .I3(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg ),\n .I5(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg ),\n .O(\\gen_pat_match_div4.pat1_match_fall0_and_r_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h80)) \n \\gen_pat_match_div4.pat1_match_fall0_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall0_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg ),\n .O(\\gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.pat1_match_fall0_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat1_match_fall0_and_r_i_1_n_0 ),\n .Q(pat1_match_fall0_and_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\gen_pat_match_div4.pat1_match_fall1_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg ),\n .I2(\\gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0 ),\n .I3(\\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg ),\n .I5(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg ),\n .O(\\gen_pat_match_div4.pat1_match_fall1_and_r_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h80)) \n \\gen_pat_match_div4.pat1_match_fall1_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall1_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg ),\n .O(\\gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.pat1_match_fall1_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat1_match_fall1_and_r_i_1_n_0 ),\n .Q(pat1_match_fall1_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_pat_match_div4.pat1_match_fall2_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg ),\n .I4(\\gen_pat_match_div4.pat1_match_fall2_and_r_i_2_n_0 ),\n .O(\\gen_pat_match_div4.pat1_match_fall2_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_pat_match_div4.pat1_match_fall2_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg ),\n .O(\\gen_pat_match_div4.pat1_match_fall2_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.pat1_match_fall2_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat1_match_fall2_and_r_i_1_n_0 ),\n .Q(pat1_match_fall2_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_pat_match_div4.pat1_match_fall3_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r_reg ),\n .I4(\\gen_pat_match_div4.pat1_match_fall3_and_r_i_2_n_0 ),\n .O(\\gen_pat_match_div4.pat1_match_fall3_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_pat_match_div4.pat1_match_fall3_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg ),\n .O(\\gen_pat_match_div4.pat1_match_fall3_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.pat1_match_fall3_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat1_match_fall3_and_r_i_1_n_0 ),\n .Q(pat1_match_fall3_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.pat1_match_rise0_and_r_i_1 \n (.I0(\\gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg ),\n .O(\\gen_pat_match_div4.pat1_match_rise0_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.pat1_match_rise0_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise0_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise0_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg ),\n .O(\\gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.pat1_match_rise0_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat1_match_rise0_and_r_i_1_n_0 ),\n .Q(pat1_match_rise0_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.pat1_match_rise1_and_r_i_1 \n (.I0(\\gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise1_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise1_r_reg ),\n .O(\\gen_pat_match_div4.pat1_match_rise1_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.pat1_match_rise1_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise1_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise1_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise1_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise1_r_reg ),\n .O(\\gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.pat1_match_rise1_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat1_match_rise1_and_r_i_1_n_0 ),\n .Q(pat1_match_rise1_and_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\gen_pat_match_div4.pat1_match_rise2_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg ),\n .I2(\\gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0 ),\n .I3(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg ),\n .I5(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg ),\n .O(\\gen_pat_match_div4.pat1_match_rise2_and_r_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h80)) \n \\gen_pat_match_div4.pat1_match_rise2_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r_reg ),\n .O(\\gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.pat1_match_rise2_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat1_match_rise2_and_r_i_1_n_0 ),\n .Q(pat1_match_rise2_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.pat1_match_rise3_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise3_r_reg ),\n .I4(\\gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0 ),\n .O(\\gen_pat_match_div4.pat1_match_rise3_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.pat1_match_rise3_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r_reg ),\n .O(\\gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.pat1_match_rise3_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat1_match_rise3_and_r_i_1_n_0 ),\n .Q(pat1_match_rise3_and_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_52 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_36 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_20 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_12 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_4 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_44 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_28 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_60 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_53 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_37 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_21 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_13 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_5 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_45 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_29 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_61 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_54 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_38 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_22 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_14 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_6 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_46 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_30 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_62 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_55 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_39 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_23 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_15 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_7 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_47 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_31 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_63 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_56 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_40 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_24 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_16 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_8 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_48 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_32 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_64 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_57 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_41 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_25 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_17 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_9 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_49 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_33 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_65 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_58 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_42 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_26 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_18 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_10 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_50 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_34 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_66 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_59 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_43 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_27 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_19 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_11 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_51 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_35 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_67 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0] ),\n .R(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0] ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0] ),\n .I2(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0] ),\n .I3(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0] ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2_n_0 ),\n .O(p_488_out__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0] ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0] ),\n .I2(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0] ),\n .I3(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0] ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2_n_0 ));\n FDRE #(\n .INIT(1'b1)) \n \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv \n (.C(CLK),\n .CE(1'b1),\n .D(p_488_out__0),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv_n_0 ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0] ),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_52 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0]_140 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0] ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0] ),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_36 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0]_132 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0] ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0] ),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_20 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0]_164 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0] ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0] ),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_12 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0]_172 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0] ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0] ),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_4 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0]_180 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0] ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0] ),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_44 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0]_148 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0] ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0] ),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_28 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0]_156 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0] ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0] ),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_60 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0]_188 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0] ),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h1)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1 \n (.I0(mpr_valid_r2),\n .I1(sr_valid_r2),\n .O(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv_n_0 ),\n .Q(\\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_0 ),\n .R(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0] ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0] ),\n .I2(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0] ),\n .I3(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0] ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2_n_0 ),\n .O(p_513_out__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0] ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0] ),\n .I2(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0] ),\n .I3(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0] ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2_n_0 ));\n FDRE #(\n .INIT(1'b1)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv \n (.C(CLK),\n .CE(1'b1),\n .D(p_513_out__0),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv_n_0 ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair111\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0] ),\n .I2(\\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0]_68 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_52 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hFB)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2 \n (.I0(mpr_valid_r1),\n .I1(mpr_rdlvl_start_reg),\n .I2(mpr_rdlvl_done_r1_reg_0),\n .O(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ));\n LUT3 #(\n .INIT(8'hFE)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3 \n (.I0(mpr_valid_r1),\n .I1(\\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),\n .I2(\\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0] ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair150\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0] ),\n .I2(\\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0]_108 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_36 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0] ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair166\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0] ),\n .I2(\\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0]_124 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_20 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0] ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair142\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0] ),\n .I2(\\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0]_100 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_12 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0] ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair134\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0] ),\n .I2(\\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0]_92 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_4 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0] ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair118\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0] ),\n .I2(\\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0]_76 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_44 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0] ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair126\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0] ),\n .I2(\\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0]_84 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_28 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0] ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair158\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0] ),\n .I2(\\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0]_116 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_60 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[1].old_sr_diff_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv_n_0 ),\n .Q(p_1_in17_in),\n .R(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_1 \n (.I0(p_2_in431_in),\n .I1(p_4_in433_in),\n .I2(p_0_in430_in),\n .I3(p_3_in432_in),\n .I4(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2_n_0 ),\n .O(p_438_out__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2 \n (.I0(p_7_in436_in),\n .I1(p_5_in434_in),\n .I2(p_6_in435_in),\n .I3(p_1_in437_in),\n .O(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2_n_0 ));\n FDRE #(\n .INIT(1'b1)) \n \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv \n (.C(CLK),\n .CE(1'b1),\n .D(p_438_out__0),\n .Q(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv_n_0 ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_0_in430_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_53 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1]_141 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1_n_0 ),\n .Q(p_0_in430_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_3_in432_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_37 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1]_133 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1_n_0 ),\n .Q(p_3_in432_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_5_in434_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_21 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1]_165 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1_n_0 ),\n .Q(p_5_in434_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_7_in436_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_13 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1]_173 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1_n_0 ),\n .Q(p_7_in436_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_1_in437_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_5 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1]_181 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1_n_0 ),\n .Q(p_1_in437_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_2_in431_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_45 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1]_149 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1_n_0 ),\n .Q(p_2_in431_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_4_in433_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_29 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1]_157 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1_n_0 ),\n .Q(p_4_in433_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_6_in435_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_61 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1]_189 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1_n_0 ),\n .Q(p_6_in435_in),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[1].prev_sr_diff_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv_n_0 ),\n .Q(p_0_in102_in),\n .R(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_1 \n (.I0(p_2_in456_in),\n .I1(p_4_in458_in),\n .I2(p_0_in455_in),\n .I3(p_3_in457_in),\n .I4(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2_n_0 ),\n .O(p_463_out__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2 \n (.I0(p_7_in461_in),\n .I1(p_6_in460_in),\n .I2(p_5_in459_in),\n .I3(p_1_in462_in),\n .O(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2_n_0 ));\n FDRE #(\n .INIT(1'b1)) \n \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv \n (.C(CLK),\n .CE(1'b1),\n .D(p_463_out__0),\n .Q(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv_n_0 ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair112\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_0_in455_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1]_69 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_53 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1_n_0 ),\n .Q(p_0_in455_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair151\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_3_in457_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1]_109 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_37 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1_n_0 ),\n .Q(p_3_in457_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair167\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_5_in459_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1]_125 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_21 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1_n_0 ),\n .Q(p_5_in459_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair143\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_7_in461_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1]_101 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_13 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1_n_0 ),\n .Q(p_7_in461_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair135\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_1_in462_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1]_93 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_5 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1_n_0 ),\n .Q(p_1_in462_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair119\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_2_in456_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1]_77 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_45 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1_n_0 ),\n .Q(p_2_in456_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair127\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_4_in458_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1]_85 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_29 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1_n_0 ),\n .Q(p_4_in458_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair159\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_6_in460_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1]_117 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_61 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1_n_0 ),\n .Q(p_6_in460_in),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[2].old_sr_diff_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv_n_0 ),\n .Q(p_1_in14_in),\n .R(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_1 \n (.I0(p_3_in382_in),\n .I1(p_4_in383_in),\n .I2(p_2_in381_in),\n .I3(p_0_in380_in),\n .I4(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2_n_0 ),\n .O(p_388_out__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2 \n (.I0(p_7_in386_in),\n .I1(p_5_in384_in),\n .I2(p_6_in385_in),\n .I3(p_1_in387_in),\n .O(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2_n_0 ));\n FDRE #(\n .INIT(1'b1)) \n \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv \n (.C(CLK),\n .CE(1'b1),\n .D(p_388_out__0),\n .Q(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv_n_0 ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_0_in380_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_54 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2]_142 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1_n_0 ),\n .Q(p_0_in380_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_3_in382_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_38 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2]_134 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1_n_0 ),\n .Q(p_3_in382_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_5_in384_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_22 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2]_166 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1_n_0 ),\n .Q(p_5_in384_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_7_in386_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_14 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2]_174 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1_n_0 ),\n .Q(p_7_in386_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_1_in387_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_6 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2]_182 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1_n_0 ),\n .Q(p_1_in387_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_2_in381_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_46 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2]_150 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1_n_0 ),\n .Q(p_2_in381_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_4_in383_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_30 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2]_158 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1_n_0 ),\n .Q(p_4_in383_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_6_in385_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_62 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2]_190 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1_n_0 ),\n .Q(p_6_in385_in),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[2].prev_sr_diff_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv_n_0 ),\n .Q(p_0_in99_in),\n .R(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_1 \n (.I0(p_2_in406_in),\n .I1(p_4_in408_in),\n .I2(p_0_in405_in),\n .I3(p_3_in407_in),\n .I4(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2_n_0 ),\n .O(p_413_out__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2 \n (.I0(p_7_in411_in),\n .I1(p_5_in409_in),\n .I2(p_6_in410_in),\n .I3(p_1_in412_in),\n .O(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2_n_0 ));\n FDRE #(\n .INIT(1'b1)) \n \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv \n (.C(CLK),\n .CE(1'b1),\n .D(p_413_out__0),\n .Q(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv_n_0 ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair113\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_0_in405_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2]_70 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_54 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1_n_0 ),\n .Q(p_0_in405_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair152\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_3_in407_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2]_110 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_38 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1_n_0 ),\n .Q(p_3_in407_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair168\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_5_in409_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2]_126 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_22 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1_n_0 ),\n .Q(p_5_in409_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair144\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_7_in411_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2]_102 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_14 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1_n_0 ),\n .Q(p_7_in411_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair136\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_1_in412_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2]_94 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_6 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1_n_0 ),\n .Q(p_1_in412_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair120\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_2_in406_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2]_78 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_46 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1_n_0 ),\n .Q(p_2_in406_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair128\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_4_in408_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2]_86 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_30 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1_n_0 ),\n .Q(p_4_in408_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair160\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_6_in410_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2]_118 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_62 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1_n_0 ),\n .Q(p_6_in410_in),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[3].old_sr_diff_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv_n_0 ),\n .Q(p_1_in11_in),\n .R(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_1 \n (.I0(p_3_in332_in),\n .I1(p_4_in333_in),\n .I2(p_2_in331_in),\n .I3(p_0_in330_in),\n .I4(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2_n_0 ),\n .O(p_338_out__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2 \n (.I0(p_6_in335_in),\n .I1(p_5_in334_in),\n .I2(p_7_in336_in),\n .I3(p_1_in337_in),\n .O(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2_n_0 ));\n FDRE #(\n .INIT(1'b1)) \n \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv \n (.C(CLK),\n .CE(1'b1),\n .D(p_338_out__0),\n .Q(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv_n_0 ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_0_in330_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_55 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3]_143 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1_n_0 ),\n .Q(p_0_in330_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_3_in332_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_39 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3]_135 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1_n_0 ),\n .Q(p_3_in332_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_5_in334_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_23 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3]_167 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1_n_0 ),\n .Q(p_5_in334_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_7_in336_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_15 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3]_175 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1_n_0 ),\n .Q(p_7_in336_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_1_in337_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_7 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3]_183 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1_n_0 ),\n .Q(p_1_in337_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair174\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_2_in331_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_47 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3]_151 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1_n_0 ),\n .Q(p_2_in331_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_4_in333_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_31 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3]_159 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1_n_0 ),\n .Q(p_4_in333_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_6_in335_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_63 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3]_191 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1_n_0 ),\n .Q(p_6_in335_in),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[3].prev_sr_diff_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv_n_0 ),\n .Q(p_0_in96_in),\n .R(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_1 \n (.I0(p_4_in358_in),\n .I1(p_5_in359_in),\n .I2(p_3_in357_in),\n .I3(p_0_in355_in),\n .I4(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2_n_0 ),\n .O(p_363_out__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2 \n (.I0(p_7_in361_in),\n .I1(p_6_in360_in),\n .I2(p_2_in356_in),\n .I3(p_1_in362_in),\n .O(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2_n_0 ));\n FDRE #(\n .INIT(1'b1)) \n \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv \n (.C(CLK),\n .CE(1'b1),\n .D(p_363_out__0),\n .Q(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv_n_0 ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair114\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_0_in355_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3]_71 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_55 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1_n_0 ),\n .Q(p_0_in355_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair153\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_3_in357_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3]_111 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_39 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1_n_0 ),\n .Q(p_3_in357_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair169\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_5_in359_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3]_127 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_23 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1_n_0 ),\n .Q(p_5_in359_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair145\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_7_in361_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3]_103 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_15 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1_n_0 ),\n .Q(p_7_in361_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair137\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_1_in362_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3]_95 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_7 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1_n_0 ),\n .Q(p_1_in362_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_2_in356_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3]_79 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_47 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1_n_0 ),\n .Q(p_2_in356_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair129\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_4_in358_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3]_87 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_31 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1_n_0 ),\n .Q(p_4_in358_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair161\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_6_in360_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3]_119 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_63 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1_n_0 ),\n .Q(p_6_in360_in),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[4].old_sr_diff_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv_n_0 ),\n .Q(p_1_in8_in),\n .R(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_1 \n (.I0(p_4_in283_in),\n .I1(p_5_in284_in),\n .I2(p_3_in282_in),\n .I3(p_2_in281_in),\n .I4(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2_n_0 ),\n .O(p_288_out__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2 \n (.I0(p_7_in286_in),\n .I1(p_6_in285_in),\n .I2(p_0_in280_in),\n .I3(p_1_in287_in),\n .O(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2_n_0 ));\n FDRE #(\n .INIT(1'b1)) \n \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv \n (.C(CLK),\n .CE(1'b1),\n .D(p_288_out__0),\n .Q(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv_n_0 ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_0_in280_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_56 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4]_144 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1_n_0 ),\n .Q(p_0_in280_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_3_in282_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_40 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4]_136 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1_n_0 ),\n .Q(p_3_in282_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_5_in284_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_24 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4]_168 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1_n_0 ),\n .Q(p_5_in284_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_7_in286_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_16 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4]_176 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1_n_0 ),\n .Q(p_7_in286_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_1_in287_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_8 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4]_184 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1_n_0 ),\n .Q(p_1_in287_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_2_in281_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_48 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4]_152 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1_n_0 ),\n .Q(p_2_in281_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_4_in283_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_32 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4]_160 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1_n_0 ),\n .Q(p_4_in283_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_6_in285_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_64 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4]_192 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1_n_0 ),\n .Q(p_6_in285_in),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[4].prev_sr_diff_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv_n_0 ),\n .Q(p_0_in93_in),\n .R(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_1 \n (.I0(p_4_in308_in),\n .I1(p_5_in309_in),\n .I2(p_3_in307_in),\n .I3(p_2_in306_in),\n .I4(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2_n_0 ),\n .O(p_313_out__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2 \n (.I0(p_7_in311_in),\n .I1(p_6_in310_in),\n .I2(p_0_in305_in),\n .I3(p_1_in312_in),\n .O(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2_n_0 ));\n FDRE #(\n .INIT(1'b1)) \n \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv \n (.C(CLK),\n .CE(1'b1),\n .D(p_313_out__0),\n .Q(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv_n_0 ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair115\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_0_in305_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4]_72 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_56 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1_n_0 ),\n .Q(p_0_in305_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair154\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_3_in307_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4]_112 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_40 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1_n_0 ),\n .Q(p_3_in307_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair170\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_5_in309_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4]_128 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_24 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1_n_0 ),\n .Q(p_5_in309_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair146\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_7_in311_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4]_104 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_16 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1_n_0 ),\n .Q(p_7_in311_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair138\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_1_in312_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4]_96 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_8 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1_n_0 ),\n .Q(p_1_in312_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair122\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_2_in306_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4]_80 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_48 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1_n_0 ),\n .Q(p_2_in306_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair130\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_4_in308_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4]_88 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_32 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1_n_0 ),\n .Q(p_4_in308_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair162\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_6_in310_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4]_120 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_64 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1_n_0 ),\n .Q(p_6_in310_in),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[5].old_sr_diff_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv_n_0 ),\n .Q(p_1_in5_in),\n .R(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_1 \n (.I0(p_4_in233_in),\n .I1(p_5_in234_in),\n .I2(p_3_in232_in),\n .I3(p_2_in231_in),\n .I4(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2_n_0 ),\n .O(p_238_out__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2 \n (.I0(p_7_in236_in),\n .I1(p_6_in235_in),\n .I2(p_0_in230_in),\n .I3(p_1_in237_in),\n .O(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2_n_0 ));\n FDRE #(\n .INIT(1'b1)) \n \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv \n (.C(CLK),\n .CE(1'b1),\n .D(p_238_out__0),\n .Q(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv_n_0 ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_0_in230_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_57 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5]_145 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1_n_0 ),\n .Q(p_0_in230_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_3_in232_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_41 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5]_137 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1_n_0 ),\n .Q(p_3_in232_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_5_in234_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_25 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5]_169 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1_n_0 ),\n .Q(p_5_in234_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_7_in236_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_17 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5]_177 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1_n_0 ),\n .Q(p_7_in236_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_1_in237_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_9 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5]_185 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1_n_0 ),\n .Q(p_1_in237_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_2_in231_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_49 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5]_153 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1_n_0 ),\n .Q(p_2_in231_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_4_in233_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_33 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5]_161 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1_n_0 ),\n .Q(p_4_in233_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_6_in235_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_65 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5]_193 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1_n_0 ),\n .Q(p_6_in235_in),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[5].prev_sr_diff_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv_n_0 ),\n .Q(p_0_in90_in),\n .R(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_1 \n (.I0(p_4_in258_in),\n .I1(p_5_in259_in),\n .I2(p_3_in257_in),\n .I3(p_2_in256_in),\n .I4(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2_n_0 ),\n .O(p_263_out__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2 \n (.I0(p_7_in261_in),\n .I1(p_6_in260_in),\n .I2(p_0_in255_in),\n .I3(p_1_in262_in),\n .O(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2_n_0 ));\n FDRE #(\n .INIT(1'b1)) \n \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv \n (.C(CLK),\n .CE(1'b1),\n .D(p_263_out__0),\n .Q(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv_n_0 ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair116\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_0_in255_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5]_73 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_57 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1_n_0 ),\n .Q(p_0_in255_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair155\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_3_in257_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5]_113 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_41 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1_n_0 ),\n .Q(p_3_in257_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair171\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_5_in259_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5]_129 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_25 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1_n_0 ),\n .Q(p_5_in259_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair147\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_7_in261_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5]_105 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_17 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1_n_0 ),\n .Q(p_7_in261_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair139\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_1_in262_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5]_97 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_9 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1_n_0 ),\n .Q(p_1_in262_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair123\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_2_in256_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5]_81 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_49 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1_n_0 ),\n .Q(p_2_in256_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair131\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_4_in258_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5]_89 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_33 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1_n_0 ),\n .Q(p_4_in258_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair163\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_6_in260_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5]_121 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_65 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1_n_0 ),\n .Q(p_6_in260_in),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[6].old_sr_diff_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv_n_0 ),\n .Q(p_1_in2_in),\n .R(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_1 \n (.I0(p_4_in183_in),\n .I1(p_5_in184_in),\n .I2(p_3_in182_in),\n .I3(p_2_in181_in),\n .I4(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2_n_0 ),\n .O(p_188_out__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2 \n (.I0(p_7_in186_in),\n .I1(p_6_in185_in),\n .I2(p_0_in180_in),\n .I3(p_1_in187_in),\n .O(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2_n_0 ));\n FDRE #(\n .INIT(1'b1)) \n \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv \n (.C(CLK),\n .CE(1'b1),\n .D(p_188_out__0),\n .Q(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv_n_0 ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_0_in180_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_58 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6]_146 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1_n_0 ),\n .Q(p_0_in180_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_3_in182_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_42 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6]_138 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1_n_0 ),\n .Q(p_3_in182_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_5_in184_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_26 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6]_170 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1_n_0 ),\n .Q(p_5_in184_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_7_in186_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_18 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6]_178 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1_n_0 ),\n .Q(p_7_in186_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_1_in187_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_10 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6]_186 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1_n_0 ),\n .Q(p_1_in187_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_2_in181_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_50 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6]_154 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1_n_0 ),\n .Q(p_2_in181_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_4_in183_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_34 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6]_162 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1_n_0 ),\n .Q(p_4_in183_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_6_in185_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_66 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6]_194 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1_n_0 ),\n .Q(p_6_in185_in),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[6].prev_sr_diff_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv_n_0 ),\n .Q(p_0_in87_in),\n .R(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_1 \n (.I0(p_4_in208_in),\n .I1(p_5_in209_in),\n .I2(p_3_in207_in),\n .I3(p_2_in206_in),\n .I4(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2_n_0 ),\n .O(p_213_out__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2 \n (.I0(p_7_in211_in),\n .I1(p_6_in210_in),\n .I2(p_0_in205_in),\n .I3(p_1_in212_in),\n .O(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2_n_0 ));\n FDRE #(\n .INIT(1'b1)) \n \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv \n (.C(CLK),\n .CE(1'b1),\n .D(p_213_out__0),\n .Q(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv_n_0 ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair121\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_0_in205_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6]_74 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_58 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1_n_0 ),\n .Q(p_0_in205_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair156\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_3_in207_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6]_114 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_42 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1_n_0 ),\n .Q(p_3_in207_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair172\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_5_in209_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6]_130 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_26 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1_n_0 ),\n .Q(p_5_in209_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair148\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_7_in211_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6]_106 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_18 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1_n_0 ),\n .Q(p_7_in211_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair140\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_1_in212_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6]_98 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_10 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1_n_0 ),\n .Q(p_1_in212_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair124\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_2_in206_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6]_82 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_50 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1_n_0 ),\n .Q(p_2_in206_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair132\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_4_in208_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6]_90 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_34 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1_n_0 ),\n .Q(p_4_in208_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair164\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_6_in210_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6]_122 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_66 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1_n_0 ),\n .Q(p_6_in210_in),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7] ),\n .R(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg_n_0_[7] ),\n .I1(p_5_in136_in),\n .I2(p_3_in135_in),\n .I3(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg_n_0_[7] ),\n .I4(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2_n_0 ),\n .O(p_137_out__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2 \n (.I0(p_7_in),\n .I1(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r_reg_n_0_[7] ),\n .I2(p_0_in134_in),\n .I3(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r_reg_n_0_[7] ),\n .O(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2_n_0 ));\n FDRE #(\n .INIT(1'b1)) \n \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv \n (.C(CLK),\n .CE(1'b1),\n .D(p_137_out__0),\n .Q(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv_n_0 ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_0_in134_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_59 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7]_147 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1_n_0 ),\n .Q(p_0_in134_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_3_in135_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_43 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7]_139 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1_n_0 ),\n .Q(p_3_in135_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_5_in136_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_27 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7]_171 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1_n_0 ),\n .Q(p_5_in136_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_7_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_19 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7]_179 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1_n_0 ),\n .Q(p_7_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r_reg_n_0_[7] ),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_11 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7]_187 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r_reg_n_0_[7] ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg_n_0_[7] ),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_51 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7]_155 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg_n_0_[7] ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg_n_0_[7] ),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_35 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7]_163 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg_n_0_[7] ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r_reg_n_0_[7] ),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_67 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7]_195 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r_reg_n_0_[7] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv_n_0 ),\n .Q(p_0_in84_in),\n .R(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_1 \n (.I0(p_4_in158_in),\n .I1(p_5_in159_in),\n .I2(p_3_in157_in),\n .I3(p_2_in156_in),\n .I4(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2_n_0 ),\n .O(p_163_out__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2 \n (.I0(p_7_in161_in),\n .I1(p_6_in160_in),\n .I2(p_0_in155_in),\n .I3(p_1_in162_in),\n .O(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2_n_0 ));\n FDRE #(\n .INIT(1'b1)) \n \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv \n (.C(CLK),\n .CE(1'b1),\n .D(p_163_out__0),\n .Q(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv_n_0 ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair117\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_0_in155_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7]_75 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_59 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1_n_0 ),\n .Q(p_0_in155_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair157\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_3_in157_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7]_115 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_43 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1_n_0 ),\n .Q(p_3_in157_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair173\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_5_in159_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7]_131 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_27 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1_n_0 ),\n .Q(p_5_in159_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair149\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_7_in161_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7]_107 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_19 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1_n_0 ),\n .Q(p_7_in161_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair141\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_1_in162_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7]_99 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_11 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1_n_0 ),\n .Q(p_1_in162_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair125\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_2_in156_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7]_83 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_51 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1_n_0 ),\n .Q(p_2_in156_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair133\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_4_in158_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7]_91 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_35 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1_n_0 ),\n .Q(p_4_in158_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair165\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_6_in160_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7]_123 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_67 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1_n_0 ),\n .Q(p_6_in160_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair244\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_track_left_edge[0].pb_cnt_eye_size_r[0][0]_i_1 \n (.I0(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]),\n .O(p_0_in__2[0]));\n (* SOFT_HLUTNM = \"soft_lutpair244\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gen_track_left_edge[0].pb_cnt_eye_size_r[0][1]_i_1 \n (.I0(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]),\n .I1(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]),\n .O(p_0_in__2[1]));\n (* SOFT_HLUTNM = \"soft_lutpair215\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\gen_track_left_edge[0].pb_cnt_eye_size_r[0][2]_i_1 \n (.I0(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [2]),\n .I1(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]),\n .I2(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]),\n .O(p_0_in__2[2]));\n (* SOFT_HLUTNM = \"soft_lutpair215\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\gen_track_left_edge[0].pb_cnt_eye_size_r[0][3]_i_1 \n (.I0(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [3]),\n .I1(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]),\n .I2(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]),\n .I3(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [2]),\n .O(p_0_in__2[3]));\n LUT4 #(\n .INIT(16'hAAAB)) \n \\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1 \n (.I0(pb_detect_edge_setup),\n .I1(\\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0 ),\n .I2(pb_detect_edge_done_r[0]),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .O(\\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8AAAAAAAAAAAAAAA)) \n \\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_2 \n (.I0(\\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0 ),\n .I1(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [4]),\n .I2(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [3]),\n .I3(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]),\n .I4(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]),\n .I5(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [2]),\n .O(pb_cnt_eye_size_r));\n (* SOFT_HLUTNM = \"soft_lutpair187\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_3 \n (.I0(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [4]),\n .I1(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [2]),\n .I2(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]),\n .I3(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]),\n .I4(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [3]),\n .O(p_0_in__2[4]));\n (* SOFT_HLUTNM = \"soft_lutpair177\" *) \n LUT5 #(\n .INIT(32'h00000F11)) \n \\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0] ),\n .I1(\\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_0 ),\n .I2(\\gen_track_left_edge[0].pb_found_edge_r_reg[0]_0 ),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I4(\\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 ),\n .O(\\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair232\" *) \n LUT3 #(\n .INIT(8'h02)) \n \\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5 \n (.I0(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .I2(pb_detect_edge_done_r[0]),\n .O(\\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][0] \n (.C(CLK),\n .CE(pb_cnt_eye_size_r),\n .D(p_0_in__2[0]),\n .Q(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]),\n .R(\\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][1] \n (.C(CLK),\n .CE(pb_cnt_eye_size_r),\n .D(p_0_in__2[1]),\n .Q(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]),\n .R(\\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][2] \n (.C(CLK),\n .CE(pb_cnt_eye_size_r),\n .D(p_0_in__2[2]),\n .Q(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [2]),\n .R(\\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][3] \n (.C(CLK),\n .CE(pb_cnt_eye_size_r),\n .D(p_0_in__2[3]),\n .Q(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [3]),\n .R(\\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][4] \n (.C(CLK),\n .CE(pb_cnt_eye_size_r),\n .D(p_0_in__2[4]),\n .Q(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [4]),\n .R(\\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[0].pb_detect_edge_done_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg[0]_0 ),\n .Q(pb_detect_edge_done_r[0]),\n .R(pb_detect_edge_setup));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[0].pb_found_edge_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[0].pb_found_edge_r_reg[0]_2 ),\n .Q(\\gen_track_left_edge[0].pb_found_edge_r_reg[0]_0 ),\n .R(pb_detect_edge_setup));\n (* SOFT_HLUTNM = \"soft_lutpair177\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_2 \n (.I0(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I1(\\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_0 ),\n .I2(\\gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0] ),\n .I3(\\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 ),\n .O(\\gen_track_left_edge[0].pb_found_edge_r_reg[0]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair187\" *) \n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3 \n (.I0(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [2]),\n .I1(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]),\n .I2(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]),\n .I3(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [3]),\n .I4(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [4]),\n .O(\\gen_track_left_edge[0].pb_found_stable_eye_r_reg[0]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair225\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_4 \n (.I0(\\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 ),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I2(\\gen_track_left_edge[0].pb_found_edge_r_reg[0]_0 ),\n .O(pb_found_stable_eye_r76_out));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[0].pb_found_stable_eye_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[0].pb_detect_edge_done_r_reg[0]_0 ),\n .Q(\\gen_track_left_edge[0].pb_found_stable_eye_r_reg ),\n .R(pb_detect_edge_setup));\n LUT6 #(\n .INIT(64'h00000000AAAAAA0E)) \n \\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1 \n (.I0(\\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 ),\n .I1(\\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_0 ),\n .I2(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .I4(pb_detect_edge_done_r[0]),\n .I5(pb_detect_edge_setup),\n .O(\\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFEFBFFFFFEF7F)) \n \\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_2 \n (.I0(out[3]),\n .I1(out[2]),\n .I2(out[0]),\n .I3(out[4]),\n .I4(cal1_state_r),\n .I5(out[1]),\n .O(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1_n_0 ),\n .Q(\\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair243\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_track_left_edge[1].pb_cnt_eye_size_r[1][0]_i_1 \n (.I0(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]),\n .O(p_0_in__3[0]));\n (* SOFT_HLUTNM = \"soft_lutpair243\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gen_track_left_edge[1].pb_cnt_eye_size_r[1][1]_i_1 \n (.I0(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]),\n .I1(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]),\n .O(p_0_in__3[1]));\n (* SOFT_HLUTNM = \"soft_lutpair212\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\gen_track_left_edge[1].pb_cnt_eye_size_r[1][2]_i_1 \n (.I0(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [2]),\n .I1(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]),\n .I2(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]),\n .O(p_0_in__3[2]));\n (* SOFT_HLUTNM = \"soft_lutpair212\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\gen_track_left_edge[1].pb_cnt_eye_size_r[1][3]_i_1 \n (.I0(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [3]),\n .I1(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]),\n .I2(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]),\n .I3(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [2]),\n .O(p_0_in__3[3]));\n LUT4 #(\n .INIT(16'hAAAB)) \n \\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1 \n (.I0(pb_detect_edge_setup),\n .I1(\\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0 ),\n .I2(pb_detect_edge_done_r[1]),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .O(\\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8AAAAAAAAAAAAAAA)) \n \\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2 \n (.I0(\\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0 ),\n .I1(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [4]),\n .I2(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [3]),\n .I3(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]),\n .I4(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]),\n .I5(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [2]),\n .O(\\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair176\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_3 \n (.I0(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [4]),\n .I1(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [2]),\n .I2(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]),\n .I3(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]),\n .I4(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [3]),\n .O(p_0_in__3[4]));\n (* SOFT_HLUTNM = \"soft_lutpair178\" *) \n LUT5 #(\n .INIT(32'h00000F11)) \n \\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4 \n (.I0(p_1_in17_in),\n .I1(p_0_in102_in),\n .I2(found_edge_r_reg_0),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I4(p_0_in16_in),\n .O(\\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair232\" *) \n LUT3 #(\n .INIT(8'h02)) \n \\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5 \n (.I0(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .I2(pb_detect_edge_done_r[1]),\n .O(\\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][0] \n (.C(CLK),\n .CE(\\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ),\n .D(p_0_in__3[0]),\n .Q(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]),\n .R(\\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][1] \n (.C(CLK),\n .CE(\\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ),\n .D(p_0_in__3[1]),\n .Q(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]),\n .R(\\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][2] \n (.C(CLK),\n .CE(\\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ),\n .D(p_0_in__3[2]),\n .Q(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [2]),\n .R(\\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][3] \n (.C(CLK),\n .CE(\\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ),\n .D(p_0_in__3[3]),\n .Q(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [3]),\n .R(\\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][4] \n (.C(CLK),\n .CE(\\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ),\n .D(p_0_in__3[4]),\n .Q(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [4]),\n .R(\\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[1].pb_detect_edge_done_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(samp_cnt_done_r_reg_6),\n .Q(pb_detect_edge_done_r[1]),\n .R(pb_detect_edge_setup));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[1].pb_found_edge_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[1].pb_found_edge_r_reg[1]_1 ),\n .Q(found_edge_r_reg_0),\n .R(pb_detect_edge_setup));\n (* SOFT_HLUTNM = \"soft_lutpair178\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_2 \n (.I0(p_0_in102_in),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I2(p_1_in17_in),\n .I3(p_0_in16_in),\n .O(\\gen_track_left_edge[1].pb_found_edge_r_reg[1]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair176\" *) \n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_3 \n (.I0(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [2]),\n .I1(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]),\n .I2(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]),\n .I3(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [3]),\n .I4(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [4]),\n .O(\\gen_track_left_edge[1].pb_found_stable_eye_r_reg[1]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair233\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_4 \n (.I0(p_0_in16_in),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I2(found_edge_r_reg_0),\n .O(pb_found_stable_eye_r72_out));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[1].pb_found_stable_eye_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[1].pb_detect_edge_done_r_reg[1]_0 ),\n .Q(\\gen_track_left_edge[1].pb_found_stable_eye_r_reg ),\n .R(pb_detect_edge_setup));\n LUT6 #(\n .INIT(64'h00000000AAAAAA0E)) \n \\gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1 \n (.I0(p_0_in16_in),\n .I1(p_0_in102_in),\n .I2(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .I4(pb_detect_edge_done_r[1]),\n .I5(pb_detect_edge_setup),\n .O(\\gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[1].pb_last_tap_jitter_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1_n_0 ),\n .Q(p_0_in16_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair242\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_track_left_edge[2].pb_cnt_eye_size_r[2][0]_i_1 \n (.I0(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]),\n .O(p_0_in__4[0]));\n (* SOFT_HLUTNM = \"soft_lutpair242\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gen_track_left_edge[2].pb_cnt_eye_size_r[2][1]_i_1 \n (.I0(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]),\n .I1(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]),\n .O(p_0_in__4[1]));\n (* SOFT_HLUTNM = \"soft_lutpair209\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\gen_track_left_edge[2].pb_cnt_eye_size_r[2][2]_i_1 \n (.I0(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [2]),\n .I1(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]),\n .I2(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]),\n .O(p_0_in__4[2]));\n (* SOFT_HLUTNM = \"soft_lutpair209\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\gen_track_left_edge[2].pb_cnt_eye_size_r[2][3]_i_1 \n (.I0(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [3]),\n .I1(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]),\n .I2(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]),\n .I3(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [2]),\n .O(p_0_in__4[3]));\n LUT4 #(\n .INIT(16'hAAAB)) \n \\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1 \n (.I0(pb_detect_edge_setup),\n .I1(\\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0 ),\n .I2(pb_detect_edge_done_r[2]),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .O(\\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8AAAAAAAAAAAAAAA)) \n \\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2 \n (.I0(\\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0 ),\n .I1(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [4]),\n .I2(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [3]),\n .I3(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]),\n .I4(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]),\n .I5(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [2]),\n .O(\\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair190\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_3 \n (.I0(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [4]),\n .I1(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [2]),\n .I2(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]),\n .I3(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]),\n .I4(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [3]),\n .O(p_0_in__4[4]));\n (* SOFT_HLUTNM = \"soft_lutpair179\" *) \n LUT5 #(\n .INIT(32'h00000F11)) \n \\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4 \n (.I0(p_1_in14_in),\n .I1(p_0_in99_in),\n .I2(found_edge_r_reg_1),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I4(p_0_in13_in),\n .O(\\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair231\" *) \n LUT3 #(\n .INIT(8'h02)) \n \\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5 \n (.I0(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .I2(pb_detect_edge_done_r[2]),\n .O(\\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][0] \n (.C(CLK),\n .CE(\\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ),\n .D(p_0_in__4[0]),\n .Q(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]),\n .R(\\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][1] \n (.C(CLK),\n .CE(\\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ),\n .D(p_0_in__4[1]),\n .Q(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]),\n .R(\\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][2] \n (.C(CLK),\n .CE(\\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ),\n .D(p_0_in__4[2]),\n .Q(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [2]),\n .R(\\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][3] \n (.C(CLK),\n .CE(\\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ),\n .D(p_0_in__4[3]),\n .Q(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [3]),\n .R(\\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][4] \n (.C(CLK),\n .CE(\\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ),\n .D(p_0_in__4[4]),\n .Q(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [4]),\n .R(\\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[2].pb_detect_edge_done_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(samp_cnt_done_r_reg_5),\n .Q(pb_detect_edge_done_r[2]),\n .R(pb_detect_edge_setup));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[2].pb_found_edge_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[2].pb_found_edge_r_reg[2]_1 ),\n .Q(found_edge_r_reg_1),\n .R(pb_detect_edge_setup));\n (* SOFT_HLUTNM = \"soft_lutpair179\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_2 \n (.I0(p_0_in99_in),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I2(p_1_in14_in),\n .I3(p_0_in13_in),\n .O(\\gen_track_left_edge[2].pb_found_edge_r_reg[2]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair190\" *) \n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_3 \n (.I0(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [2]),\n .I1(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]),\n .I2(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]),\n .I3(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [3]),\n .I4(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [4]),\n .O(\\gen_track_left_edge[2].pb_found_stable_eye_r_reg[2]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair233\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_4 \n (.I0(p_0_in13_in),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I2(found_edge_r_reg_1),\n .O(pb_found_stable_eye_r68_out));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[2].pb_found_stable_eye_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[2].pb_detect_edge_done_r_reg[2]_0 ),\n .Q(\\gen_track_left_edge[2].pb_found_stable_eye_r_reg ),\n .R(pb_detect_edge_setup));\n LUT6 #(\n .INIT(64'h00000000AAAAAA0E)) \n \\gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1 \n (.I0(p_0_in13_in),\n .I1(p_0_in99_in),\n .I2(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .I4(pb_detect_edge_done_r[2]),\n .I5(pb_detect_edge_setup),\n .O(\\gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[2].pb_last_tap_jitter_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1_n_0 ),\n .Q(p_0_in13_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair241\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_track_left_edge[3].pb_cnt_eye_size_r[3][0]_i_1 \n (.I0(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]),\n .O(p_0_in__5[0]));\n (* SOFT_HLUTNM = \"soft_lutpair241\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gen_track_left_edge[3].pb_cnt_eye_size_r[3][1]_i_1 \n (.I0(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]),\n .I1(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]),\n .O(p_0_in__5[1]));\n (* SOFT_HLUTNM = \"soft_lutpair211\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\gen_track_left_edge[3].pb_cnt_eye_size_r[3][2]_i_1 \n (.I0(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [2]),\n .I1(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]),\n .I2(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]),\n .O(p_0_in__5[2]));\n (* SOFT_HLUTNM = \"soft_lutpair211\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\gen_track_left_edge[3].pb_cnt_eye_size_r[3][3]_i_1 \n (.I0(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [3]),\n .I1(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]),\n .I2(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]),\n .I3(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [2]),\n .O(p_0_in__5[3]));\n LUT4 #(\n .INIT(16'hAAAB)) \n \\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1 \n (.I0(pb_detect_edge_setup),\n .I1(\\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0 ),\n .I2(pb_detect_edge_done_r[3]),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .O(\\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8AAAAAAAAAAAAAAA)) \n \\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2 \n (.I0(\\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0 ),\n .I1(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [4]),\n .I2(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [3]),\n .I3(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]),\n .I4(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]),\n .I5(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [2]),\n .O(\\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair195\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_3 \n (.I0(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [4]),\n .I1(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [2]),\n .I2(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]),\n .I3(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]),\n .I4(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [3]),\n .O(p_0_in__5[4]));\n (* SOFT_HLUTNM = \"soft_lutpair180\" *) \n LUT5 #(\n .INIT(32'h00000F11)) \n \\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4 \n (.I0(p_1_in11_in),\n .I1(p_0_in96_in),\n .I2(found_edge_r_reg_2),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I4(p_0_in10_in),\n .O(\\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair228\" *) \n LUT3 #(\n .INIT(8'h02)) \n \\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5 \n (.I0(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .I2(pb_detect_edge_done_r[3]),\n .O(\\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][0] \n (.C(CLK),\n .CE(\\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ),\n .D(p_0_in__5[0]),\n .Q(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]),\n .R(\\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][1] \n (.C(CLK),\n .CE(\\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ),\n .D(p_0_in__5[1]),\n .Q(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]),\n .R(\\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][2] \n (.C(CLK),\n .CE(\\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ),\n .D(p_0_in__5[2]),\n .Q(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [2]),\n .R(\\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][3] \n (.C(CLK),\n .CE(\\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ),\n .D(p_0_in__5[3]),\n .Q(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [3]),\n .R(\\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][4] \n (.C(CLK),\n .CE(\\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ),\n .D(p_0_in__5[4]),\n .Q(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [4]),\n .R(\\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[3].pb_detect_edge_done_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(samp_cnt_done_r_reg_4),\n .Q(pb_detect_edge_done_r[3]),\n .R(pb_detect_edge_setup));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[3].pb_found_edge_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[3].pb_found_edge_r_reg[3]_1 ),\n .Q(found_edge_r_reg_2),\n .R(pb_detect_edge_setup));\n (* SOFT_HLUTNM = \"soft_lutpair180\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_2 \n (.I0(p_0_in96_in),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I2(p_1_in11_in),\n .I3(p_0_in10_in),\n .O(\\gen_track_left_edge[3].pb_found_edge_r_reg[3]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair195\" *) \n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_3 \n (.I0(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [2]),\n .I1(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]),\n .I2(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]),\n .I3(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [3]),\n .I4(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [4]),\n .O(\\gen_track_left_edge[3].pb_found_stable_eye_r_reg[3]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair231\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_4 \n (.I0(p_0_in10_in),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I2(found_edge_r_reg_2),\n .O(pb_found_stable_eye_r64_out));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[3].pb_found_stable_eye_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[3].pb_detect_edge_done_r_reg[3]_0 ),\n .Q(\\gen_track_left_edge[3].pb_found_stable_eye_r_reg ),\n .R(pb_detect_edge_setup));\n LUT6 #(\n .INIT(64'h00000000AAAAAA0E)) \n \\gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1 \n (.I0(p_0_in10_in),\n .I1(p_0_in96_in),\n .I2(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .I4(pb_detect_edge_done_r[3]),\n .I5(pb_detect_edge_setup),\n .O(\\gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[3].pb_last_tap_jitter_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1_n_0 ),\n .Q(p_0_in10_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair240\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_track_left_edge[4].pb_cnt_eye_size_r[4][0]_i_1 \n (.I0(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]),\n .O(p_0_in__6[0]));\n (* SOFT_HLUTNM = \"soft_lutpair240\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gen_track_left_edge[4].pb_cnt_eye_size_r[4][1]_i_1 \n (.I0(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]),\n .I1(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]),\n .O(p_0_in__6[1]));\n (* SOFT_HLUTNM = \"soft_lutpair216\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\gen_track_left_edge[4].pb_cnt_eye_size_r[4][2]_i_1 \n (.I0(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [2]),\n .I1(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]),\n .I2(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]),\n .O(p_0_in__6[2]));\n (* SOFT_HLUTNM = \"soft_lutpair216\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\gen_track_left_edge[4].pb_cnt_eye_size_r[4][3]_i_1 \n (.I0(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [3]),\n .I1(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]),\n .I2(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]),\n .I3(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [2]),\n .O(p_0_in__6[3]));\n LUT4 #(\n .INIT(16'hAAAB)) \n \\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1 \n (.I0(pb_detect_edge_setup),\n .I1(\\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0 ),\n .I2(pb_detect_edge_done_r[4]),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .O(\\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8AAAAAAAAAAAAAAA)) \n \\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2 \n (.I0(\\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0 ),\n .I1(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [4]),\n .I2(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [3]),\n .I3(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]),\n .I4(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]),\n .I5(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [2]),\n .O(\\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair196\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_3 \n (.I0(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [4]),\n .I1(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [2]),\n .I2(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]),\n .I3(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]),\n .I4(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [3]),\n .O(p_0_in__6[4]));\n (* SOFT_HLUTNM = \"soft_lutpair181\" *) \n LUT5 #(\n .INIT(32'h00000F11)) \n \\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4 \n (.I0(p_1_in8_in),\n .I1(p_0_in93_in),\n .I2(\\gen_track_left_edge[4].pb_found_edge_r_reg[4]_0 ),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I4(p_0_in7_in),\n .O(\\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair225\" *) \n LUT3 #(\n .INIT(8'h02)) \n \\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5 \n (.I0(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .I2(pb_detect_edge_done_r[4]),\n .O(\\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][0] \n (.C(CLK),\n .CE(\\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ),\n .D(p_0_in__6[0]),\n .Q(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]),\n .R(\\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][1] \n (.C(CLK),\n .CE(\\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ),\n .D(p_0_in__6[1]),\n .Q(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]),\n .R(\\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][2] \n (.C(CLK),\n .CE(\\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ),\n .D(p_0_in__6[2]),\n .Q(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [2]),\n .R(\\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][3] \n (.C(CLK),\n .CE(\\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ),\n .D(p_0_in__6[3]),\n .Q(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [3]),\n .R(\\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][4] \n (.C(CLK),\n .CE(\\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ),\n .D(p_0_in__6[4]),\n .Q(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [4]),\n .R(\\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[4].pb_detect_edge_done_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(samp_cnt_done_r_reg_3),\n .Q(pb_detect_edge_done_r[4]),\n .R(pb_detect_edge_setup));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[4].pb_found_edge_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[4].pb_found_edge_r_reg[4]_2 ),\n .Q(\\gen_track_left_edge[4].pb_found_edge_r_reg[4]_0 ),\n .R(pb_detect_edge_setup));\n (* SOFT_HLUTNM = \"soft_lutpair181\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_2 \n (.I0(p_0_in93_in),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I2(p_1_in8_in),\n .I3(p_0_in7_in),\n .O(\\gen_track_left_edge[4].pb_found_edge_r_reg[4]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair196\" *) \n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_3 \n (.I0(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [2]),\n .I1(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]),\n .I2(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]),\n .I3(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [3]),\n .I4(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [4]),\n .O(\\gen_track_left_edge[4].pb_found_stable_eye_r_reg[4]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair228\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_4 \n (.I0(p_0_in7_in),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I2(\\gen_track_left_edge[4].pb_found_edge_r_reg[4]_0 ),\n .O(pb_found_stable_eye_r60_out));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[4].pb_found_stable_eye_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[4].pb_detect_edge_done_r_reg[4]_0 ),\n .Q(\\gen_track_left_edge[4].pb_found_stable_eye_r_reg ),\n .R(pb_detect_edge_setup));\n LUT6 #(\n .INIT(64'h00000000AAAAAA0E)) \n \\gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1 \n (.I0(p_0_in7_in),\n .I1(p_0_in93_in),\n .I2(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .I4(pb_detect_edge_done_r[4]),\n .I5(pb_detect_edge_setup),\n .O(\\gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[4].pb_last_tap_jitter_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1_n_0 ),\n .Q(p_0_in7_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair239\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_track_left_edge[5].pb_cnt_eye_size_r[5][0]_i_1 \n (.I0(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]),\n .O(p_0_in__7[0]));\n (* SOFT_HLUTNM = \"soft_lutpair239\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gen_track_left_edge[5].pb_cnt_eye_size_r[5][1]_i_1 \n (.I0(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]),\n .I1(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]),\n .O(p_0_in__7[1]));\n (* SOFT_HLUTNM = \"soft_lutpair214\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\gen_track_left_edge[5].pb_cnt_eye_size_r[5][2]_i_1 \n (.I0(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [2]),\n .I1(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]),\n .I2(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]),\n .O(p_0_in__7[2]));\n (* SOFT_HLUTNM = \"soft_lutpair214\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\gen_track_left_edge[5].pb_cnt_eye_size_r[5][3]_i_1 \n (.I0(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [3]),\n .I1(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]),\n .I2(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]),\n .I3(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [2]),\n .O(p_0_in__7[3]));\n LUT4 #(\n .INIT(16'hAAAB)) \n \\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1 \n (.I0(pb_detect_edge_setup),\n .I1(\\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0 ),\n .I2(pb_detect_edge_done_r[5]),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .O(\\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8AAAAAAAAAAAAAAA)) \n \\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2 \n (.I0(\\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0 ),\n .I1(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [4]),\n .I2(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [3]),\n .I3(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]),\n .I4(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]),\n .I5(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [2]),\n .O(\\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair191\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_3 \n (.I0(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [4]),\n .I1(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [2]),\n .I2(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]),\n .I3(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]),\n .I4(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [3]),\n .O(p_0_in__7[4]));\n (* SOFT_HLUTNM = \"soft_lutpair182\" *) \n LUT5 #(\n .INIT(32'h00000F11)) \n \\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4 \n (.I0(p_1_in5_in),\n .I1(p_0_in90_in),\n .I2(found_edge_r_reg_3),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I4(p_0_in4_in),\n .O(\\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair221\" *) \n LUT3 #(\n .INIT(8'h02)) \n \\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5 \n (.I0(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .I2(pb_detect_edge_done_r[5]),\n .O(\\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][0] \n (.C(CLK),\n .CE(\\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ),\n .D(p_0_in__7[0]),\n .Q(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]),\n .R(\\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][1] \n (.C(CLK),\n .CE(\\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ),\n .D(p_0_in__7[1]),\n .Q(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]),\n .R(\\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][2] \n (.C(CLK),\n .CE(\\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ),\n .D(p_0_in__7[2]),\n .Q(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [2]),\n .R(\\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][3] \n (.C(CLK),\n .CE(\\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ),\n .D(p_0_in__7[3]),\n .Q(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [3]),\n .R(\\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][4] \n (.C(CLK),\n .CE(\\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ),\n .D(p_0_in__7[4]),\n .Q(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [4]),\n .R(\\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[5].pb_detect_edge_done_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(samp_cnt_done_r_reg_2),\n .Q(pb_detect_edge_done_r[5]),\n .R(pb_detect_edge_setup));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[5].pb_found_edge_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[5].pb_found_edge_r_reg[5]_1 ),\n .Q(found_edge_r_reg_3),\n .R(pb_detect_edge_setup));\n (* SOFT_HLUTNM = \"soft_lutpair182\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_2 \n (.I0(p_0_in90_in),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I2(p_1_in5_in),\n .I3(p_0_in4_in),\n .O(\\gen_track_left_edge[5].pb_found_edge_r_reg[5]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair191\" *) \n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_3 \n (.I0(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [2]),\n .I1(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]),\n .I2(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]),\n .I3(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [3]),\n .I4(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [4]),\n .O(\\gen_track_left_edge[5].pb_found_stable_eye_r_reg[5]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair218\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_4 \n (.I0(p_0_in4_in),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I2(found_edge_r_reg_3),\n .O(pb_found_stable_eye_r56_out));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[5].pb_found_stable_eye_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[5].pb_detect_edge_done_r_reg[5]_0 ),\n .Q(\\gen_track_left_edge[5].pb_found_stable_eye_r_reg ),\n .R(pb_detect_edge_setup));\n LUT6 #(\n .INIT(64'h00000000AAAAAA0E)) \n \\gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1 \n (.I0(p_0_in4_in),\n .I1(p_0_in90_in),\n .I2(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .I4(pb_detect_edge_done_r[5]),\n .I5(pb_detect_edge_setup),\n .O(\\gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[5].pb_last_tap_jitter_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1_n_0 ),\n .Q(p_0_in4_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair246\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_track_left_edge[6].pb_cnt_eye_size_r[6][0]_i_1 \n (.I0(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]),\n .O(p_0_in__8[0]));\n (* SOFT_HLUTNM = \"soft_lutpair246\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gen_track_left_edge[6].pb_cnt_eye_size_r[6][1]_i_1 \n (.I0(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]),\n .I1(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]),\n .O(p_0_in__8[1]));\n (* SOFT_HLUTNM = \"soft_lutpair199\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\gen_track_left_edge[6].pb_cnt_eye_size_r[6][2]_i_1 \n (.I0(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [2]),\n .I1(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]),\n .I2(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]),\n .O(p_0_in__8[2]));\n (* SOFT_HLUTNM = \"soft_lutpair199\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\gen_track_left_edge[6].pb_cnt_eye_size_r[6][3]_i_1 \n (.I0(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [3]),\n .I1(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]),\n .I2(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]),\n .I3(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [2]),\n .O(p_0_in__8[3]));\n LUT4 #(\n .INIT(16'hAAAB)) \n \\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1 \n (.I0(pb_detect_edge_setup),\n .I1(\\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0 ),\n .I2(pb_detect_edge_done_r[6]),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .O(\\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8AAAAAAAAAAAAAAA)) \n \\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2 \n (.I0(\\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0 ),\n .I1(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [4]),\n .I2(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [3]),\n .I3(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]),\n .I4(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]),\n .I5(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [2]),\n .O(\\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair175\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_3 \n (.I0(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [4]),\n .I1(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [2]),\n .I2(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]),\n .I3(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]),\n .I4(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [3]),\n .O(p_0_in__8[4]));\n (* SOFT_HLUTNM = \"soft_lutpair183\" *) \n LUT5 #(\n .INIT(32'h00000F11)) \n \\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4 \n (.I0(p_1_in2_in),\n .I1(p_0_in87_in),\n .I2(\\gen_track_left_edge[6].pb_found_edge_r_reg[6]_0 ),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I4(p_0_in1_in),\n .O(\\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair218\" *) \n LUT3 #(\n .INIT(8'h02)) \n \\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5 \n (.I0(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .I2(pb_detect_edge_done_r[6]),\n .O(\\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][0] \n (.C(CLK),\n .CE(\\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ),\n .D(p_0_in__8[0]),\n .Q(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]),\n .R(\\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][1] \n (.C(CLK),\n .CE(\\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ),\n .D(p_0_in__8[1]),\n .Q(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]),\n .R(\\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][2] \n (.C(CLK),\n .CE(\\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ),\n .D(p_0_in__8[2]),\n .Q(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [2]),\n .R(\\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][3] \n (.C(CLK),\n .CE(\\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ),\n .D(p_0_in__8[3]),\n .Q(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [3]),\n .R(\\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][4] \n (.C(CLK),\n .CE(\\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ),\n .D(p_0_in__8[4]),\n .Q(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [4]),\n .R(\\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[6].pb_detect_edge_done_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(samp_cnt_done_r_reg_1),\n .Q(pb_detect_edge_done_r[6]),\n .R(pb_detect_edge_setup));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[6].pb_found_edge_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[6].pb_found_edge_r_reg[6]_2 ),\n .Q(\\gen_track_left_edge[6].pb_found_edge_r_reg[6]_0 ),\n .R(pb_detect_edge_setup));\n (* SOFT_HLUTNM = \"soft_lutpair183\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_2 \n (.I0(p_0_in87_in),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I2(p_1_in2_in),\n .I3(p_0_in1_in),\n .O(\\gen_track_left_edge[6].pb_found_edge_r_reg[6]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair175\" *) \n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_3 \n (.I0(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [2]),\n .I1(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]),\n .I2(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]),\n .I3(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [3]),\n .I4(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [4]),\n .O(\\gen_track_left_edge[6].pb_found_stable_eye_r_reg[6]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair221\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_4 \n (.I0(p_0_in1_in),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I2(\\gen_track_left_edge[6].pb_found_edge_r_reg[6]_0 ),\n .O(pb_found_stable_eye_r52_out));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[6].pb_found_stable_eye_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[6].pb_detect_edge_done_r_reg[6]_0 ),\n .Q(\\gen_track_left_edge[6].pb_found_stable_eye_r_reg ),\n .R(pb_detect_edge_setup));\n LUT6 #(\n .INIT(64'h00000000AAAAAA0E)) \n \\gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1 \n (.I0(p_0_in1_in),\n .I1(p_0_in87_in),\n .I2(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .I4(pb_detect_edge_done_r[6]),\n .I5(pb_detect_edge_setup),\n .O(\\gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[6].pb_last_tap_jitter_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1_n_0 ),\n .Q(p_0_in1_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair245\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_track_left_edge[7].pb_cnt_eye_size_r[7][0]_i_1 \n (.I0(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]),\n .O(p_0_in__9[0]));\n (* SOFT_HLUTNM = \"soft_lutpair245\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gen_track_left_edge[7].pb_cnt_eye_size_r[7][1]_i_1 \n (.I0(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]),\n .I1(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]),\n .O(p_0_in__9[1]));\n (* SOFT_HLUTNM = \"soft_lutpair203\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\gen_track_left_edge[7].pb_cnt_eye_size_r[7][2]_i_1 \n (.I0(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [2]),\n .I1(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]),\n .I2(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]),\n .O(p_0_in__9[2]));\n (* SOFT_HLUTNM = \"soft_lutpair203\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\gen_track_left_edge[7].pb_cnt_eye_size_r[7][3]_i_1 \n (.I0(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [3]),\n .I1(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]),\n .I2(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]),\n .I3(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [2]),\n .O(p_0_in__9[3]));\n LUT4 #(\n .INIT(16'hAAAB)) \n \\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1 \n (.I0(pb_detect_edge_setup),\n .I1(\\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0 ),\n .I2(pb_detect_edge_done_r[7]),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .O(\\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8AAAAAAAAAAAAAAA)) \n \\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2 \n (.I0(\\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0 ),\n .I1(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [4]),\n .I2(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [3]),\n .I3(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]),\n .I4(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]),\n .I5(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [2]),\n .O(\\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair194\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_3 \n (.I0(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [4]),\n .I1(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [2]),\n .I2(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]),\n .I3(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]),\n .I4(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [3]),\n .O(p_0_in__9[4]));\n (* SOFT_HLUTNM = \"soft_lutpair184\" *) \n LUT5 #(\n .INIT(32'h00000F11)) \n \\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4 \n (.I0(\\gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7] ),\n .I1(p_0_in84_in),\n .I2(\\gen_track_left_edge[7].pb_found_edge_r_reg[7]_0 ),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I4(p_0_in),\n .O(\\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair217\" *) \n LUT3 #(\n .INIT(8'h02)) \n \\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5 \n (.I0(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .I2(pb_detect_edge_done_r[7]),\n .O(\\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][0] \n (.C(CLK),\n .CE(\\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ),\n .D(p_0_in__9[0]),\n .Q(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]),\n .R(\\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][1] \n (.C(CLK),\n .CE(\\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ),\n .D(p_0_in__9[1]),\n .Q(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]),\n .R(\\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][2] \n (.C(CLK),\n .CE(\\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ),\n .D(p_0_in__9[2]),\n .Q(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [2]),\n .R(\\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][3] \n (.C(CLK),\n .CE(\\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ),\n .D(p_0_in__9[3]),\n .Q(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [3]),\n .R(\\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][4] \n (.C(CLK),\n .CE(\\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ),\n .D(p_0_in__9[4]),\n .Q(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [4]),\n .R(\\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000400040008)) \n \\gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_1 \n (.I0(out[3]),\n .I1(out[2]),\n .I2(cal1_state_r),\n .I3(out[4]),\n .I4(out[0]),\n .I5(out[1]),\n .O(pb_detect_edge_setup));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[7].pb_detect_edge_done_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(samp_cnt_done_r_reg_0),\n .Q(pb_detect_edge_done_r[7]),\n .R(pb_detect_edge_setup));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[7].pb_found_edge_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[7].pb_found_edge_r_reg[7]_2 ),\n .Q(\\gen_track_left_edge[7].pb_found_edge_r_reg[7]_0 ),\n .R(pb_detect_edge_setup));\n (* SOFT_HLUTNM = \"soft_lutpair184\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_2 \n (.I0(p_0_in84_in),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I2(\\gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7] ),\n .I3(p_0_in),\n .O(\\gen_track_left_edge[7].pb_found_edge_r_reg[7]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair194\" *) \n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_3 \n (.I0(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [2]),\n .I1(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]),\n .I2(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]),\n .I3(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [3]),\n .I4(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [4]),\n .O(\\gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair217\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_4 \n (.I0(p_0_in),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I2(\\gen_track_left_edge[7].pb_found_edge_r_reg[7]_0 ),\n .O(\\gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[7].pb_found_stable_eye_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[7].pb_detect_edge_done_r_reg[7]_0 ),\n .Q(\\gen_track_left_edge[7].pb_found_stable_eye_r_reg ),\n .R(pb_detect_edge_setup));\n LUT6 #(\n .INIT(64'h00000000AAAAAA0E)) \n \\gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1 \n (.I0(p_0_in),\n .I1(p_0_in84_in),\n .I2(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .I4(pb_detect_edge_done_r[7]),\n .I5(pb_detect_edge_setup),\n .O(\\gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1_n_0 ),\n .Q(p_0_in),\n .R(1'b0));\n LUT4 #(\n .INIT(16'h0008)) \n idel_adj_inc_i_2\n (.I0(out[4]),\n .I1(out[0]),\n .I2(cal1_state_r),\n .I3(out[3]),\n .O(idel_adj_inc_reg_1));\n (* SOFT_HLUTNM = \"soft_lutpair222\" *) \n LUT3 #(\n .INIT(8'hA8)) \n idel_adj_inc_i_3\n (.I0(detect_edge_done_r),\n .I1(\\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ),\n .I2(\\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ),\n .O(idel_adj_inc_reg_2));\n FDRE #(\n .INIT(1'b0)) \n idel_adj_inc_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_cal1_state_r_reg[2]_0 ),\n .Q(idel_adj_inc_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n LUT4 #(\n .INIT(16'h4373)) \n \\idel_dec_cnt[0]_i_1 \n (.I0(idel_dec_cnt__0[0]),\n .I1(out[1]),\n .I2(out[2]),\n .I3(\\idel_dec_cnt[0]_i_2_n_0 ),\n .O(idel_dec_cnt));\n LUT6 #(\n .INIT(64'h505F3030505F3F3F)) \n \\idel_dec_cnt[0]_i_2 \n (.I0(\\idelay_tap_cnt_r_reg_n_0_[0][3][0] ),\n .I1(\\idelay_tap_cnt_r_reg_n_0_[0][1][0] ),\n .I2(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .I3(\\idelay_tap_cnt_r_reg_n_0_[0][2][0] ),\n .I4(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I5(\\idelay_tap_cnt_r_reg_n_0_[0][0][0] ),\n .O(\\idel_dec_cnt[0]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h0000E22E)) \n \\idel_dec_cnt[1]_i_1 \n (.I0(idelay_tap_cnt_r[1]),\n .I1(out[4]),\n .I2(idel_dec_cnt__0[0]),\n .I3(idel_dec_cnt__0[1]),\n .I4(out[0]),\n .O(\\idel_dec_cnt[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00000000EEE2222E)) \n \\idel_dec_cnt[2]_i_1 \n (.I0(idelay_tap_cnt_r[2]),\n .I1(out[4]),\n .I2(idel_dec_cnt__0[1]),\n .I3(idel_dec_cnt__0[0]),\n .I4(idel_dec_cnt__0[2]),\n .I5(out[0]),\n .O(\\idel_dec_cnt[2]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h00002EE2)) \n \\idel_dec_cnt[3]_i_1 \n (.I0(idelay_tap_cnt_r[3]),\n .I1(out[4]),\n .I2(\\idel_dec_cnt[3]_i_2_n_0 ),\n .I3(idel_dec_cnt__0[3]),\n .I4(out[0]),\n .O(\\idel_dec_cnt[3]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h01)) \n \\idel_dec_cnt[3]_i_2 \n (.I0(idel_dec_cnt__0[0]),\n .I1(idel_dec_cnt__0[1]),\n .I2(idel_dec_cnt__0[2]),\n .O(\\idel_dec_cnt[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h1000001000404000)) \n \\idel_dec_cnt[4]_i_1 \n (.I0(\\idel_dec_cnt_reg[0]_0 ),\n .I1(out[0]),\n .I2(\\idel_dec_cnt[4]_i_4_n_0 ),\n .I3(out[1]),\n .I4(out[4]),\n .I5(out[2]),\n .O(\\idel_dec_cnt[4]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h00002EE2)) \n \\idel_dec_cnt[4]_i_2 \n (.I0(idelay_tap_cnt_r[4]),\n .I1(out[4]),\n .I2(\\idel_dec_cnt[4]_i_5_n_0 ),\n .I3(idel_dec_cnt__0[4]),\n .I4(out[0]),\n .O(\\idel_dec_cnt[4]_i_2_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\idel_dec_cnt[4]_i_3 \n (.I0(out[3]),\n .I1(cal1_state_r),\n .O(\\idel_dec_cnt_reg[0]_0 ));\n LUT6 #(\n .INIT(64'hB888FFFFB8880000)) \n \\idel_dec_cnt[4]_i_4 \n (.I0(cal1_state_r2),\n .I1(out[4]),\n .I2(mpr_rd_rise0_prev_r_reg_0),\n .I3(idel_mpr_pat_detect_r),\n .I4(out[1]),\n .I5(\\idel_dec_cnt[4]_i_7_n_0 ),\n .O(\\idel_dec_cnt[4]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair92\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\idel_dec_cnt[4]_i_5 \n (.I0(idel_dec_cnt__0[2]),\n .I1(idel_dec_cnt__0[1]),\n .I2(idel_dec_cnt__0[0]),\n .I3(idel_dec_cnt__0[3]),\n .O(\\idel_dec_cnt[4]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair92\" *) \n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n \\idel_dec_cnt[4]_i_6 \n (.I0(idel_dec_cnt__0[4]),\n .I1(idel_dec_cnt__0[3]),\n .I2(idel_dec_cnt__0[0]),\n .I3(idel_dec_cnt__0[1]),\n .I4(idel_dec_cnt__0[2]),\n .O(cal1_state_r2));\n LUT6 #(\n .INIT(64'hA800A800A8FFA800)) \n \\idel_dec_cnt[4]_i_7 \n (.I0(detect_edge_done_r),\n .I1(\\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ),\n .I2(\\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ),\n .I3(out[4]),\n .I4(stable_idel_cnt22_in),\n .I5(\\idel_dec_cnt[4]_i_8_n_0 ),\n .O(\\idel_dec_cnt[4]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFB)) \n \\idel_dec_cnt[4]_i_8 \n (.I0(\\cnt_idel_dec_cpt_r_reg_n_0_[5] ),\n .I1(mpr_dec_cpt_r_reg_0),\n .I2(\\cnt_idel_dec_cpt_r_reg_n_0_[2] ),\n .I3(\\cnt_idel_dec_cpt_r_reg_n_0_[3] ),\n .I4(\\cnt_idel_dec_cpt_r_reg_n_0_[4] ),\n .I5(\\idel_dec_cnt[4]_i_9_n_0 ),\n .O(\\idel_dec_cnt[4]_i_8_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair205\" *) \n LUT2 #(\n .INIT(4'hB)) \n \\idel_dec_cnt[4]_i_9 \n (.I0(\\cnt_idel_dec_cpt_r_reg_n_0_[1] ),\n .I1(\\cnt_idel_dec_cpt_r_reg_n_0_[0] ),\n .O(\\idel_dec_cnt[4]_i_9_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\idel_dec_cnt_reg[0] \n (.C(CLK),\n .CE(\\idel_dec_cnt[4]_i_1_n_0 ),\n .D(idel_dec_cnt),\n .Q(idel_dec_cnt__0[0]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE #(\n .INIT(1'b0)) \n \\idel_dec_cnt_reg[1] \n (.C(CLK),\n .CE(\\idel_dec_cnt[4]_i_1_n_0 ),\n .D(\\idel_dec_cnt[1]_i_1_n_0 ),\n .Q(idel_dec_cnt__0[1]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE #(\n .INIT(1'b0)) \n \\idel_dec_cnt_reg[2] \n (.C(CLK),\n .CE(\\idel_dec_cnt[4]_i_1_n_0 ),\n .D(\\idel_dec_cnt[2]_i_1_n_0 ),\n .Q(idel_dec_cnt__0[2]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE #(\n .INIT(1'b0)) \n \\idel_dec_cnt_reg[3] \n (.C(CLK),\n .CE(\\idel_dec_cnt[4]_i_1_n_0 ),\n .D(\\idel_dec_cnt[3]_i_1_n_0 ),\n .Q(idel_dec_cnt__0[3]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE #(\n .INIT(1'b0)) \n \\idel_dec_cnt_reg[4] \n (.C(CLK),\n .CE(\\idel_dec_cnt[4]_i_1_n_0 ),\n .D(\\idel_dec_cnt[4]_i_2_n_0 ),\n .Q(idel_dec_cnt__0[4]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE #(\n .INIT(1'b0)) \n idel_pat_detect_valid_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_cal1_state_r_reg[4]_0 ),\n .Q(mpr_rd_rise0_prev_r_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n (* SOFT_HLUTNM = \"soft_lutpair106\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\idelay_tap_cnt_r[0][0][0]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__22),\n .I1(idelay_ce_int),\n .I2(idelay_tap_cnt_slice_r[0]),\n .O(\\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair106\" *) \n LUT5 #(\n .INIT(32'h04404004)) \n \\idelay_tap_cnt_r[0][0][1]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__22),\n .I1(idelay_ce_int),\n .I2(idelay_tap_cnt_slice_r[0]),\n .I3(idelay_tap_cnt_slice_r[1]),\n .I4(idelay_inc_int),\n .O(\\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0444400044400004)) \n \\idelay_tap_cnt_r[0][0][2]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__22),\n .I1(idelay_ce_int),\n .I2(idelay_inc_int),\n .I3(idelay_tap_cnt_slice_r[0]),\n .I4(idelay_tap_cnt_slice_r[2]),\n .I5(idelay_tap_cnt_slice_r[1]),\n .O(\\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h28A0A0A0A0A0A082)) \n \\idelay_tap_cnt_r[0][0][3]_i_1 \n (.I0(\\idelay_tap_cnt_r[0][0][3]_i_2_n_0 ),\n .I1(idelay_tap_cnt_slice_r[2]),\n .I2(idelay_tap_cnt_slice_r[3]),\n .I3(idelay_tap_cnt_slice_r[0]),\n .I4(idelay_inc_int),\n .I5(idelay_tap_cnt_slice_r[1]),\n .O(\\idelay_tap_cnt_r[0][0][3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair200\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\idelay_tap_cnt_r[0][0][3]_i_2 \n (.I0(idelay_ce_int),\n .I1(rstdiv0_sync_r1_reg_rep__22),\n .O(\\idelay_tap_cnt_r[0][0][3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF111111F1)) \n \\idelay_tap_cnt_r[0][0][4]_i_1 \n (.I0(\\po_stg2_wrcal_cnt_reg[0] ),\n .I1(\\po_stg2_wrcal_cnt_reg[1] ),\n .I2(\\idelay_tap_cnt_r[0][0][4]_i_4_n_0 ),\n .I3(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .I4(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I5(rstdiv0_sync_r1_reg_rep__22),\n .O(\\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair227\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\idelay_tap_cnt_r[0][0][4]_i_2 \n (.I0(rstdiv0_sync_r1_reg_rep__22),\n .I1(idelay_ce_int),\n .I2(\\idelay_tap_cnt_r[0][0][4]_i_5_n_0 ),\n .O(\\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair220\" *) \n LUT3 #(\n .INIT(8'h10)) \n \\idelay_tap_cnt_r[0][0][4]_i_4 \n (.I0(\\rnk_cnt_r_reg_n_0_[0] ),\n .I1(\\rnk_cnt_r_reg_n_0_[1] ),\n .I2(idelay_ce_int),\n .O(\\idelay_tap_cnt_r[0][0][4]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h9555555555555556)) \n \\idelay_tap_cnt_r[0][0][4]_i_5 \n (.I0(idelay_tap_cnt_slice_r[4]),\n .I1(idelay_tap_cnt_slice_r[0]),\n .I2(idelay_inc_int),\n .I3(idelay_tap_cnt_slice_r[1]),\n .I4(idelay_tap_cnt_slice_r[3]),\n .I5(idelay_tap_cnt_slice_r[2]),\n .O(\\idelay_tap_cnt_r[0][0][4]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF1111F111)) \n \\idelay_tap_cnt_r[0][1][4]_i_1 \n (.I0(cal1_dq_idel_ce_reg_0),\n .I1(\\po_stg2_wrcal_cnt_reg[1] ),\n .I2(\\idelay_tap_cnt_r[0][0][4]_i_4_n_0 ),\n .I3(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .I4(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I5(rstdiv0_sync_r1_reg_rep__22),\n .O(\\idelay_tap_cnt_r[0][1][4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF4F444444)) \n \\idelay_tap_cnt_r[0][2][4]_i_1 \n (.I0(\\po_stg2_wrcal_cnt_reg[0] ),\n .I1(\\po_stg2_wrcal_cnt_reg[1] ),\n .I2(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .I3(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I4(\\idelay_tap_cnt_r[0][0][4]_i_4_n_0 ),\n .I5(rstdiv0_sync_r1_reg_rep__22),\n .O(\\idelay_tap_cnt_r[0][2][4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFF4444444)) \n \\idelay_tap_cnt_r[0][3][4]_i_1 \n (.I0(cal1_dq_idel_ce_reg_0),\n .I1(\\po_stg2_wrcal_cnt_reg[1] ),\n .I2(idelay_ce_int),\n .I3(\\idelay_tap_cnt_r[0][3][4]_i_2_n_0 ),\n .I4(cal1_cnt_cpt_r1),\n .I5(rstdiv0_sync_r1_reg_rep__22),\n .O(\\idelay_tap_cnt_r[0][3][4]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair220\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\idelay_tap_cnt_r[0][3][4]_i_2 \n (.I0(\\rnk_cnt_r_reg_n_0_[1] ),\n .I1(\\rnk_cnt_r_reg_n_0_[0] ),\n .O(\\idelay_tap_cnt_r[0][3][4]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair230\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\idelay_tap_cnt_r[0][3][4]_i_3 \n (.I0(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I1(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .O(cal1_cnt_cpt_r1));\n FDRE #(\n .INIT(1'b0)) \n \\idelay_tap_cnt_r_reg[0][0][0] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][0][0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\idelay_tap_cnt_r_reg[0][0][1] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][0][1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\idelay_tap_cnt_r_reg[0][0][2] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][0][2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\idelay_tap_cnt_r_reg[0][0][3] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][3]_i_1_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][0][3] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\idelay_tap_cnt_r_reg[0][0][4] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][0][4] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\idelay_tap_cnt_r_reg[0][1][0] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][1][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][1][0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\idelay_tap_cnt_r_reg[0][1][1] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][1][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][1][1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\idelay_tap_cnt_r_reg[0][1][2] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][1][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][1][2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\idelay_tap_cnt_r_reg[0][1][3] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][1][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][3]_i_1_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][1][3] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\idelay_tap_cnt_r_reg[0][1][4] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][1][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][1][4] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\idelay_tap_cnt_r_reg[0][2][0] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][2][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][2][0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\idelay_tap_cnt_r_reg[0][2][1] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][2][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][2][1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\idelay_tap_cnt_r_reg[0][2][2] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][2][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][2][2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\idelay_tap_cnt_r_reg[0][2][3] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][2][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][3]_i_1_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][2][3] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\idelay_tap_cnt_r_reg[0][2][4] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][2][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][2][4] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\idelay_tap_cnt_r_reg[0][3][0] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][3][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][3][0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\idelay_tap_cnt_r_reg[0][3][1] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][3][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][3][1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\idelay_tap_cnt_r_reg[0][3][2] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][3][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][3][2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\idelay_tap_cnt_r_reg[0][3][3] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][3][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][3]_i_1_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][3][3] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\idelay_tap_cnt_r_reg[0][3][4] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][3][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][3][4] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFE2CCE233E200E2)) \n \\idelay_tap_cnt_slice_r[0]_i_1 \n (.I0(\\idelay_tap_cnt_r_reg_n_0_[0][0][0] ),\n .I1(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I2(\\idelay_tap_cnt_r_reg_n_0_[0][2][0] ),\n .I3(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .I4(\\idelay_tap_cnt_r_reg_n_0_[0][1][0] ),\n .I5(\\idelay_tap_cnt_r_reg_n_0_[0][3][0] ),\n .O(idelay_tap_cnt_r[0]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\idelay_tap_cnt_slice_r[1]_i_1 \n (.I0(\\idelay_tap_cnt_r_reg_n_0_[0][3][1] ),\n .I1(\\idelay_tap_cnt_r_reg_n_0_[0][1][1] ),\n .I2(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .I3(\\idelay_tap_cnt_r_reg_n_0_[0][2][1] ),\n .I4(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I5(\\idelay_tap_cnt_r_reg_n_0_[0][0][1] ),\n .O(idelay_tap_cnt_r[1]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\idelay_tap_cnt_slice_r[2]_i_1 \n (.I0(\\idelay_tap_cnt_r_reg_n_0_[0][3][2] ),\n .I1(\\idelay_tap_cnt_r_reg_n_0_[0][1][2] ),\n .I2(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .I3(\\idelay_tap_cnt_r_reg_n_0_[0][2][2] ),\n .I4(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I5(\\idelay_tap_cnt_r_reg_n_0_[0][0][2] ),\n .O(idelay_tap_cnt_r[2]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\idelay_tap_cnt_slice_r[3]_i_1 \n (.I0(\\idelay_tap_cnt_r_reg_n_0_[0][3][3] ),\n .I1(\\idelay_tap_cnt_r_reg_n_0_[0][1][3] ),\n .I2(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .I3(\\idelay_tap_cnt_r_reg_n_0_[0][2][3] ),\n .I4(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I5(\\idelay_tap_cnt_r_reg_n_0_[0][0][3] ),\n .O(idelay_tap_cnt_r[3]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\idelay_tap_cnt_slice_r[4]_i_1 \n (.I0(\\idelay_tap_cnt_r_reg_n_0_[0][3][4] ),\n .I1(\\idelay_tap_cnt_r_reg_n_0_[0][1][4] ),\n .I2(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .I3(\\idelay_tap_cnt_r_reg_n_0_[0][2][4] ),\n .I4(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I5(\\idelay_tap_cnt_r_reg_n_0_[0][0][4] ),\n .O(idelay_tap_cnt_r[4]));\n FDRE #(\n .INIT(1'b0)) \n \\idelay_tap_cnt_slice_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(idelay_tap_cnt_r[0]),\n .Q(idelay_tap_cnt_slice_r[0]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE #(\n .INIT(1'b0)) \n \\idelay_tap_cnt_slice_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(idelay_tap_cnt_r[1]),\n .Q(idelay_tap_cnt_slice_r[1]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE #(\n .INIT(1'b0)) \n \\idelay_tap_cnt_slice_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(idelay_tap_cnt_r[2]),\n .Q(idelay_tap_cnt_slice_r[2]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE #(\n .INIT(1'b0)) \n \\idelay_tap_cnt_slice_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(idelay_tap_cnt_r[3]),\n .Q(idelay_tap_cnt_slice_r[3]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE #(\n .INIT(1'b0)) \n \\idelay_tap_cnt_slice_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(idelay_tap_cnt_r[4]),\n .Q(idelay_tap_cnt_slice_r[4]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n LUT3 #(\n .INIT(8'h02)) \n idelay_tap_limit_r_i_1\n (.I0(idelay_tap_limit_r_i_2_n_0),\n .I1(new_cnt_cpt_r_reg_n_0),\n .I2(rstdiv0_sync_r1_reg_rep__22),\n .O(idelay_tap_limit_r_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFF40000000)) \n idelay_tap_limit_r_i_2\n (.I0(\\idel_dec_cnt[0]_i_2_n_0 ),\n .I1(idelay_tap_cnt_r[3]),\n .I2(idelay_tap_cnt_r[4]),\n .I3(idelay_tap_cnt_r[2]),\n .I4(idelay_tap_cnt_r[1]),\n .I5(idelay_tap_limit_r_reg_n_0),\n .O(idelay_tap_limit_r_i_2_n_0));\n FDRE #(\n .INIT(1'b0)) \n idelay_tap_limit_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(idelay_tap_limit_r_i_1_n_0),\n .Q(idelay_tap_limit_r_reg_n_0),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair206\" *) \n LUT3 #(\n .INIT(8'h54)) \n \\init_state_r[0]_i_37 \n (.I0(oclkdelay_calib_done_r_reg),\n .I1(mpr_last_byte_done),\n .I2(mpr_rdlvl_done_r1_reg_0),\n .O(\\init_state_r_reg[0]_0 ));\n LUT6 #(\n .INIT(64'h00000000AAFE0000)) \n \\init_state_r[0]_i_38 \n (.I0(\\init_state_r[0]_i_48_n_0 ),\n .I1(wrlvl_byte_redo),\n .I2(wrlvl_final_mux),\n .I3(\\init_state_r[0]_i_49_n_0 ),\n .I4(mem_init_done_r),\n .I5(prbs_rdlvl_done_reg_rep_0),\n .O(\\init_state_r_reg[0]_2 ));\n LUT5 #(\n .INIT(32'h00010000)) \n \\init_state_r[0]_i_44 \n (.I0(\\init_state_r_reg[1]_0 [1]),\n .I1(mpr_rdlvl_done_r1_reg_0),\n .I2(mpr_rnk_done),\n .I3(rdlvl_prech_req),\n .I4(\\init_state_r_reg[1]_0 [0]),\n .O(\\init_state_r_reg[0] ));\n LUT6 #(\n .INIT(64'h55FF55FF51FF51F1)) \n \\init_state_r[0]_i_47 \n (.I0(\\init_state_r[0]_i_53_n_0 ),\n .I1(oclkdelay_calib_done_r_reg),\n .I2(\\init_state_r[0]_i_54_n_0 ),\n .I3(prbs_rdlvl_done_reg_rep),\n .I4(rdlvl_stg1_done_r1_reg),\n .I5(\\init_state_r_reg[5] ),\n .O(\\init_state_r_reg[0]_3 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF001F0000)) \n \\init_state_r[0]_i_48 \n (.I0(mpr_rdlvl_done_r1_reg_0),\n .I1(mpr_last_byte_done),\n .I2(oclkdelay_calib_done_r_reg),\n .I3(\\init_state_r[0]_i_53_n_0 ),\n .I4(wrlvl_final_mux_reg),\n .I5(prbs_rdlvl_done_reg_rep_1),\n .O(\\init_state_r[0]_i_48_n_0 ));\n LUT6 #(\n .INIT(64'hFF00FF000000FF54)) \n \\init_state_r[0]_i_49 \n (.I0(prbs_last_byte_done_r),\n .I1(mpr_last_byte_done),\n .I2(mpr_rdlvl_done_r1_reg_0),\n .I3(prbs_rdlvl_done_reg_rep),\n .I4(wrcal_done_reg),\n .I5(rdlvl_stg1_done_r1_reg),\n .O(\\init_state_r[0]_i_49_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair224\" *) \n LUT3 #(\n .INIT(8'h01)) \n \\init_state_r[0]_i_52 \n (.I0(rdlvl_stg1_done_r1_reg),\n .I1(rdlvl_last_byte_done),\n .I2(\\one_rank.stg1_wr_done_reg ),\n .O(\\init_state_r_reg[0]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair213\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\init_state_r[0]_i_53 \n (.I0(rdlvl_stg1_done_r1_reg),\n .I1(oclkdelay_center_calib_done_r_reg),\n .I2(wrlvl_done_r1),\n .O(\\init_state_r[0]_i_53_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair93\" *) \n LUT3 #(\n .INIT(8'h4F)) \n \\init_state_r[0]_i_54 \n (.I0(rdlvl_stg1_done_r1_reg),\n .I1(wrcal_done_reg),\n .I2(dqs_found_done_r_reg),\n .O(\\init_state_r[0]_i_54_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair213\" *) \n LUT4 #(\n .INIT(16'h0080)) \n \\init_state_r[0]_i_57 \n (.I0(rdlvl_stg1_done_r1_reg),\n .I1(prbs_rdlvl_done_reg_rep),\n .I2(oclkdelay_center_calib_done_r_reg),\n .I3(wrlvl_done_r1),\n .O(\\init_state_r_reg[0]_4 ));\n LUT6 #(\n .INIT(64'h00FFFE0000000000)) \n \\init_state_r[1]_i_38 \n (.I0(mpr_rdlvl_done_r1_reg_0),\n .I1(mpr_rnk_done),\n .I2(rdlvl_prech_req),\n .I3(\\init_state_r_reg[1]_0 [0]),\n .I4(\\init_state_r_reg[1]_0 [1]),\n .I5(\\init_state_r_reg[3]_0 ),\n .O(\\init_state_r_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair93\" *) \n LUT5 #(\n .INIT(32'h7FFFFFFF)) \n \\init_state_r[2]_i_13 \n (.I0(rdlvl_stg1_done_r1_reg),\n .I1(prbs_rdlvl_done_reg_rep),\n .I2(wrlvl_done_r1),\n .I3(dqs_found_done_r_reg),\n .I4(wrcal_done_reg),\n .O(\\init_state_r_reg[2]_2 ));\n LUT6 #(\n .INIT(64'hD0FFD0FFD0FFD0D0)) \n \\init_state_r[2]_i_15 \n (.I0(wrlvl_done_r1_reg),\n .I1(\\init_state_r_reg[2]_0 ),\n .I2(\\init_state_r_reg[2]_1 ),\n .I3(wrlvl_done_r1_reg_0),\n .I4(cnt_init_af_done_r),\n .I5(dqs_found_done_r_reg_0),\n .O(\\init_state_r_reg[2] ));\n LUT6 #(\n .INIT(64'hFFFFFFFF74FFFFFF)) \n \\init_state_r[2]_i_28 \n (.I0(prbs_rdlvl_done_reg_rep),\n .I1(rdlvl_stg1_done_r1_reg),\n .I2(wrcal_done_reg),\n .I3(dqs_found_done_r_reg),\n .I4(oclkdelay_calib_done_r_reg),\n .I5(\\init_state_r_reg[5] ),\n .O(\\init_state_r_reg[2]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair210\" *) \n LUT4 #(\n .INIT(16'hAAFE)) \n \\init_state_r[3]_i_8 \n (.I0(wrlvl_byte_redo_reg),\n .I1(mpr_rdlvl_done_r1_reg_0),\n .I2(mpr_last_byte_done),\n .I3(oclkdelay_calib_done_r_reg),\n .O(\\init_state_r_reg[2]_1 ));\n LUT6 #(\n .INIT(64'h4040004000000040)) \n \\init_state_r[3]_i_9 \n (.I0(\\num_refresh_reg[1] ),\n .I1(\\init_state_r_reg[5] ),\n .I2(dqs_found_done_r_reg),\n .I3(wrcal_done_reg),\n .I4(rdlvl_stg1_done_r1_reg),\n .I5(prbs_rdlvl_done_reg_rep),\n .O(\\init_state_r_reg[3] ));\n LUT6 #(\n .INIT(64'hB010B010B0100000)) \n \\init_state_r[4]_i_25 \n (.I0(rdlvl_stg1_done_r1_reg),\n .I1(wrcal_done_reg),\n .I2(dqs_found_done_r_reg),\n .I3(prbs_rdlvl_done_reg_rep),\n .I4(mpr_last_byte_done),\n .I5(mpr_rdlvl_done_r1_reg_0),\n .O(\\init_state_r_reg[4] ));\n (* SOFT_HLUTNM = \"soft_lutpair210\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\init_state_r[5]_i_30 \n (.I0(mpr_rdlvl_done_r1_reg_0),\n .I1(mpr_last_byte_done),\n .O(\\init_state_r_reg[5] ));\n LUT5 #(\n .INIT(32'h00000002)) \n \\mpr_4to1.idel_mpr_pat_detect_r_i_1 \n (.I0(\\mpr_4to1.idel_mpr_pat_detect_r_i_2_n_0 ),\n .I1(\\mpr_4to1.idel_mpr_pat_detect_r_i_3_n_0 ),\n .I2(inhibit_edge_detect_r),\n .I3(p_1_in26_in),\n .I4(inhibit_edge_detect_r0),\n .O(\\mpr_4to1.idel_mpr_pat_detect_r_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF00100000)) \n \\mpr_4to1.idel_mpr_pat_detect_r_i_2 \n (.I0(\\mpr_4to1.inhibit_edge_detect_r_i_2_n_0 ),\n .I1(\\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ),\n .I2(\\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ),\n .I3(\\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ),\n .I4(\\mpr_4to1.stable_idel_cnt[2]_i_4_n_0 ),\n .I5(idel_mpr_pat_detect_r),\n .O(\\mpr_4to1.idel_mpr_pat_detect_r_i_2_n_0 ));\n LUT4 #(\n .INIT(16'h0008)) \n \\mpr_4to1.idel_mpr_pat_detect_r_i_3 \n (.I0(\\mpr_4to1.inhibit_edge_detect_r_i_3_n_0 ),\n .I1(mpr_rd_rise0_prev_r_reg_0),\n .I2(\\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ),\n .I3(\\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ),\n .O(\\mpr_4to1.idel_mpr_pat_detect_r_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000100)) \n \\mpr_4to1.idel_mpr_pat_detect_r_i_4 \n (.I0(out[3]),\n .I1(cal1_state_r),\n .I2(out[4]),\n .I3(out[0]),\n .I4(out[2]),\n .I5(out[1]),\n .O(p_1_in26_in));\n FDRE #(\n .INIT(1'b0)) \n \\mpr_4to1.idel_mpr_pat_detect_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\mpr_4to1.idel_mpr_pat_detect_r_i_1_n_0 ),\n .Q(idel_mpr_pat_detect_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hFFFFFB00)) \n \\mpr_4to1.inhibit_edge_detect_r_i_1 \n (.I0(\\mpr_4to1.inhibit_edge_detect_r_i_2_n_0 ),\n .I1(\\mpr_4to1.inhibit_edge_detect_r_i_3_n_0 ),\n .I2(\\mpr_4to1.inhibit_edge_detect_r_i_4_n_0 ),\n .I3(inhibit_edge_detect_r),\n .I4(inhibit_edge_detect_r0),\n .O(\\mpr_4to1.inhibit_edge_detect_r_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFFEFF)) \n \\mpr_4to1.inhibit_edge_detect_r_i_2 \n (.I0(mpr_rd_rise2_prev_r),\n .I1(mpr_rd_rise1_prev_r),\n .I2(mpr_rd_rise3_prev_r),\n .I3(mpr_rd_fall1_prev_r),\n .I4(\\mpr_4to1.inhibit_edge_detect_r_i_6_n_0 ),\n .O(\\mpr_4to1.inhibit_edge_detect_r_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000020000)) \n \\mpr_4to1.inhibit_edge_detect_r_i_3 \n (.I0(out[1]),\n .I1(out[3]),\n .I2(cal1_state_r),\n .I3(out[4]),\n .I4(out[0]),\n .I5(out[2]),\n .O(\\mpr_4to1.inhibit_edge_detect_r_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair109\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\mpr_4to1.inhibit_edge_detect_r_i_4 \n (.I0(idelay_tap_cnt_r[1]),\n .I1(idelay_tap_cnt_r[2]),\n .I2(idelay_tap_cnt_r[3]),\n .I3(idelay_tap_cnt_r[4]),\n .O(\\mpr_4to1.inhibit_edge_detect_r_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAAABAAAAAA)) \n \\mpr_4to1.inhibit_edge_detect_r_i_5 \n (.I0(rstdiv0_sync_r1_reg_rep__22),\n .I1(\\mpr_4to1.inhibit_edge_detect_r_i_7_n_0 ),\n .I2(mpr_rd_fall2_prev_r),\n .I3(mpr_rd_rise2_prev_r),\n .I4(mpr_rd_rise1_prev_r),\n .I5(mpr_rd_fall0_prev_r),\n .O(inhibit_edge_detect_r0));\n LUT4 #(\n .INIT(16'hFF7F)) \n \\mpr_4to1.inhibit_edge_detect_r_i_6 \n (.I0(mpr_rd_fall2_prev_r),\n .I1(mpr_rd_fall0_prev_r),\n .I2(mpr_rd_fall3_prev_r),\n .I3(mpr_rd_rise0_prev_r),\n .O(\\mpr_4to1.inhibit_edge_detect_r_i_6_n_0 ));\n LUT4 #(\n .INIT(16'hFFDF)) \n \\mpr_4to1.inhibit_edge_detect_r_i_7 \n (.I0(mpr_rd_rise0_prev_r),\n .I1(mpr_rd_fall1_prev_r),\n .I2(mpr_rd_rise3_prev_r),\n .I3(mpr_rd_fall3_prev_r),\n .O(\\mpr_4to1.inhibit_edge_detect_r_i_7_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\mpr_4to1.inhibit_edge_detect_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\mpr_4to1.inhibit_edge_detect_r_i_1_n_0 ),\n .Q(inhibit_edge_detect_r),\n .R(1'b0));\n LUT3 #(\n .INIT(8'h06)) \n \\mpr_4to1.stable_idel_cnt[0]_i_1 \n (.I0(\\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ),\n .I1(stable_idel_cnt),\n .I2(stable_idel_cnt0),\n .O(\\mpr_4to1.stable_idel_cnt[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair108\" *) \n LUT4 #(\n .INIT(16'h006A)) \n \\mpr_4to1.stable_idel_cnt[1]_i_1 \n (.I0(\\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ),\n .I1(stable_idel_cnt),\n .I2(\\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ),\n .I3(stable_idel_cnt0),\n .O(\\mpr_4to1.stable_idel_cnt[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair108\" *) \n LUT5 #(\n .INIT(32'h00006AAA)) \n \\mpr_4to1.stable_idel_cnt[2]_i_1 \n (.I0(\\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ),\n .I1(stable_idel_cnt),\n .I2(\\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ),\n .I3(\\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ),\n .I4(stable_idel_cnt0),\n .O(\\mpr_4to1.stable_idel_cnt[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000080)) \n \\mpr_4to1.stable_idel_cnt[2]_i_2 \n (.I0(stable_idel_cnt22_in),\n .I1(\\mpr_4to1.inhibit_edge_detect_r_i_3_n_0 ),\n .I2(mpr_rd_rise0_prev_r_reg_0),\n .I3(\\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ),\n .I4(\\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ),\n .I5(\\mpr_4to1.stable_idel_cnt[2]_i_4_n_0 ),\n .O(stable_idel_cnt));\n (* SOFT_HLUTNM = \"soft_lutpair227\" *) \n LUT3 #(\n .INIT(8'hFE)) \n \\mpr_4to1.stable_idel_cnt[2]_i_3 \n (.I0(\\mpr_4to1.stable_idel_cnt[2]_i_4_n_0 ),\n .I1(\\mpr_4to1.stable_idel_cnt[2]_i_5_n_0 ),\n .I2(rstdiv0_sync_r1_reg_rep__22),\n .O(stable_idel_cnt0));\n LUT6 #(\n .INIT(64'hFFFFFFFFBEFFFFBE)) \n \\mpr_4to1.stable_idel_cnt[2]_i_4 \n (.I0(\\mpr_4to1.stable_idel_cnt[2]_i_6_n_0 ),\n .I1(\\gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ),\n .I2(mpr_rd_fall0_prev_r),\n .I3(\\gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ),\n .I4(mpr_rd_rise2_prev_r),\n .I5(\\mpr_4to1.stable_idel_cnt[2]_i_7_n_0 ),\n .O(\\mpr_4to1.stable_idel_cnt[2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000004)) \n \\mpr_4to1.stable_idel_cnt[2]_i_5 \n (.I0(out[3]),\n .I1(cal1_state_r),\n .I2(out[2]),\n .I3(out[0]),\n .I4(out[4]),\n .I5(out[1]),\n .O(\\mpr_4to1.stable_idel_cnt[2]_i_5_n_0 ));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\mpr_4to1.stable_idel_cnt[2]_i_6 \n (.I0(\\gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ),\n .I1(mpr_rd_fall2_prev_r),\n .I2(\\gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ),\n .I3(mpr_rd_rise1_prev_r),\n .O(\\mpr_4to1.stable_idel_cnt[2]_i_6_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF6FF6)) \n \\mpr_4to1.stable_idel_cnt[2]_i_7 \n (.I0(mpr_rd_rise0_prev_r),\n .I1(\\gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ),\n .I2(mpr_rd_fall3_prev_r),\n .I3(\\gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ),\n .I4(\\mpr_4to1.stable_idel_cnt[2]_i_8_n_0 ),\n .O(\\mpr_4to1.stable_idel_cnt[2]_i_7_n_0 ));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\mpr_4to1.stable_idel_cnt[2]_i_8 \n (.I0(\\gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ),\n .I1(mpr_rd_fall1_prev_r),\n .I2(\\gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ),\n .I3(mpr_rd_rise3_prev_r),\n .O(\\mpr_4to1.stable_idel_cnt[2]_i_8_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\mpr_4to1.stable_idel_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mpr_4to1.stable_idel_cnt[0]_i_1_n_0 ),\n .Q(\\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mpr_4to1.stable_idel_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mpr_4to1.stable_idel_cnt[1]_i_1_n_0 ),\n .Q(\\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\mpr_4to1.stable_idel_cnt_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mpr_4to1.stable_idel_cnt[2]_i_1_n_0 ),\n .Q(\\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ),\n .R(1'b0));\n LUT3 #(\n .INIT(8'h24)) \n mpr_dec_cpt_r_i_2\n (.I0(out[0]),\n .I1(out[1]),\n .I2(out[2]),\n .O(mpr_dec_cpt_r_reg_1));\n FDRE #(\n .INIT(1'b0)) \n mpr_dec_cpt_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_cal1_state_r_reg[3]_0 ),\n .Q(mpr_dec_cpt_r_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__13));\n LUT6 #(\n .INIT(64'h0300000000002323)) \n mpr_last_byte_done_i_2\n (.I0(cal1_state_r1),\n .I1(mpr_rank_done_r_reg_0),\n .I2(cal1_state_r),\n .I3(cal1_cnt_cpt_r1),\n .I4(out[3]),\n .I5(out[4]),\n .O(mpr_last_byte_done_reg_0));\n FDRE #(\n .INIT(1'b0)) \n mpr_last_byte_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_cal1_state_r_reg[4]_1 ),\n .Q(mpr_last_byte_done),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n LUT6 #(\n .INIT(64'hFBFFFFFFFFFFFFFF)) \n mpr_rank_done_r_i_2\n (.I0(cal1_state_r),\n .I1(out[4]),\n .I2(mpr_rdlvl_done_r1_reg_0),\n .I3(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I4(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .I5(prech_done),\n .O(mpr_rank_done_r_reg_1));\n LUT5 #(\n .INIT(32'h7E7EFFFE)) \n mpr_rank_done_r_i_3\n (.I0(out[0]),\n .I1(out[2]),\n .I2(out[3]),\n .I3(cal1_state_r),\n .I4(out[1]),\n .O(mpr_rank_done_r_reg_0));\n FDRE #(\n .INIT(1'b0)) \n mpr_rank_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_cal1_state_r_reg[4]_2 ),\n .Q(mpr_rnk_done),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n mpr_rd_fall0_prev_r_reg\n (.C(CLK),\n .CE(mpr_rd_rise0_prev_r0),\n .D(\\gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ),\n .Q(mpr_rd_fall0_prev_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n mpr_rd_fall1_prev_r_reg\n (.C(CLK),\n .CE(mpr_rd_rise0_prev_r0),\n .D(\\gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ),\n .Q(mpr_rd_fall1_prev_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n mpr_rd_fall2_prev_r_reg\n (.C(CLK),\n .CE(mpr_rd_rise0_prev_r0),\n .D(\\gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ),\n .Q(mpr_rd_fall2_prev_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n mpr_rd_fall3_prev_r_reg\n (.C(CLK),\n .CE(mpr_rd_rise0_prev_r0),\n .D(\\gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ),\n .Q(mpr_rd_fall3_prev_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n mpr_rd_rise0_prev_r_reg\n (.C(CLK),\n .CE(mpr_rd_rise0_prev_r0),\n .D(\\gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ),\n .Q(mpr_rd_rise0_prev_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0000300000001000)) \n mpr_rd_rise1_prev_r_i_1\n (.I0(out[1]),\n .I1(out[3]),\n .I2(mpr_rd_rise0_prev_r_reg_1),\n .I3(out[0]),\n .I4(out[2]),\n .I5(mpr_rd_rise0_prev_r_reg_0),\n .O(mpr_rd_rise0_prev_r0));\n LUT2 #(\n .INIT(4'h1)) \n mpr_rd_rise1_prev_r_i_2\n (.I0(cal1_state_r),\n .I1(out[4]),\n .O(mpr_rd_rise0_prev_r_reg_1));\n FDRE #(\n .INIT(1'b0)) \n mpr_rd_rise1_prev_r_reg\n (.C(CLK),\n .CE(mpr_rd_rise0_prev_r0),\n .D(\\gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ),\n .Q(mpr_rd_rise1_prev_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n mpr_rd_rise2_prev_r_reg\n (.C(CLK),\n .CE(mpr_rd_rise0_prev_r0),\n .D(\\gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ),\n .Q(mpr_rd_rise2_prev_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n mpr_rd_rise3_prev_r_reg\n (.C(CLK),\n .CE(mpr_rd_rise0_prev_r0),\n .D(\\gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ),\n .Q(mpr_rd_rise3_prev_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n mpr_rdlvl_done_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mpr_rdlvl_done_r1_reg_0),\n .Q(mpr_rdlvl_done_r1),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n mpr_rdlvl_done_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mpr_rdlvl_done_r1),\n .Q(mpr_rdlvl_done_r2),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0000000000001000)) \n mpr_rdlvl_done_r_i_2\n (.I0(out[1]),\n .I1(out[4]),\n .I2(cal1_state_r),\n .I3(out[0]),\n .I4(out[3]),\n .I5(out[2]),\n .O(rdlvl_stg1_done_int));\n FDRE #(\n .INIT(1'b0)) \n mpr_rdlvl_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mpr_rdlvl_done_r_reg_0),\n .Q(mpr_rdlvl_done_r1_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE #(\n .INIT(1'b0)) \n mpr_rdlvl_start_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mpr_rdlvl_start_reg),\n .Q(mpr_rdlvl_start_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n mpr_valid_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mpr_valid_r1_reg_0),\n .Q(mpr_valid_r1),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n mpr_valid_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mpr_valid_r1),\n .Q(mpr_valid_r2),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00000008)) \n mpr_valid_r_i_1\n (.I0(mpr_rdlvl_start_reg),\n .I1(phy_rddata_en_1),\n .I2(rstdiv0_sync_r1_reg_rep__20),\n .I3(mpr_rdlvl_done_r1_reg_0),\n .I4(mpr_valid_r_reg_0),\n .O(mpr_valid_r));\n FDRE #(\n .INIT(1'b0)) \n mpr_valid_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mpr_valid_r),\n .Q(mpr_valid_r1_reg_0),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h4000000000000001)) \n new_cnt_cpt_r_i_1\n (.I0(new_cnt_cpt_r_i_2_n_0),\n .I1(out[2]),\n .I2(out[3]),\n .I3(out[4]),\n .I4(out[0]),\n .I5(out[1]),\n .O(new_cnt_cpt_r));\n LUT6 #(\n .INIT(64'hAAAAFFEFFFFFFFEF)) \n new_cnt_cpt_r_i_2\n (.I0(cal1_state_r),\n .I1(cal1_state_r1535_out),\n .I2(rdlvl_stg1_start_reg),\n .I3(rdlvl_stg1_start_r),\n .I4(out[4]),\n .I5(new_cnt_cpt_r82_out),\n .O(new_cnt_cpt_r_i_2_n_0));\n LUT6 #(\n .INIT(64'h8880AAAAAAAAAAAA)) \n new_cnt_cpt_r_i_3\n (.I0(prech_done),\n .I1(mpr_rdlvl_done_r1_reg_0),\n .I2(\\rnk_cnt_r_reg_n_0_[0] ),\n .I3(\\rnk_cnt_r_reg_n_0_[1] ),\n .I4(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I5(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .O(new_cnt_cpt_r82_out));\n FDRE #(\n .INIT(1'b0)) \n new_cnt_cpt_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(new_cnt_cpt_r),\n .Q(new_cnt_cpt_r_reg_n_0),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n (* SOFT_HLUTNM = \"soft_lutpair89\" *) \n LUT5 #(\n .INIT(32'h0000EA00)) \n \\phaser_in_gen.phaser_in_i_1 \n (.I0(calib_in_common),\n .I1(\\calib_sel_reg[3] [1]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(pi_counter_load_en),\n .I4(Q),\n .O(\\pi_dqs_found_lanes_r1_reg[3]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair98\" *) \n LUT5 #(\n .INIT(32'h44440040)) \n \\phaser_in_gen.phaser_in_i_10 \n (.I0(Q),\n .I1(pi_counter_load_val[1]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[1]_2 [1]));\n (* SOFT_HLUTNM = \"soft_lutpair104\" *) \n LUT5 #(\n .INIT(32'h44440040)) \n \\phaser_in_gen.phaser_in_i_10__0 \n (.I0(Q),\n .I1(pi_counter_load_val[1]),\n .I2(\\calib_sel_reg[3] [1]),\n .I3(\\calib_sel_reg[3] [0]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[2]_2 [1]));\n (* SOFT_HLUTNM = \"soft_lutpair104\" *) \n LUT5 #(\n .INIT(32'h44444000)) \n \\phaser_in_gen.phaser_in_i_10__1 \n (.I0(Q),\n .I1(pi_counter_load_val[1]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[3]_2 [1]));\n (* SOFT_HLUTNM = \"soft_lutpair98\" *) \n LUT5 #(\n .INIT(32'h44440004)) \n \\phaser_in_gen.phaser_in_i_10__2 \n (.I0(Q),\n .I1(pi_counter_load_val[1]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(COUNTERLOADVAL[1]));\n (* SOFT_HLUTNM = \"soft_lutpair99\" *) \n LUT5 #(\n .INIT(32'h44440040)) \n \\phaser_in_gen.phaser_in_i_11 \n (.I0(Q),\n .I1(pi_counter_load_val[0]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[1]_2 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair105\" *) \n LUT5 #(\n .INIT(32'h44440040)) \n \\phaser_in_gen.phaser_in_i_11__0 \n (.I0(Q),\n .I1(pi_counter_load_val[0]),\n .I2(\\calib_sel_reg[3] [1]),\n .I3(\\calib_sel_reg[3] [0]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[2]_2 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair105\" *) \n LUT5 #(\n .INIT(32'h44444000)) \n \\phaser_in_gen.phaser_in_i_11__1 \n (.I0(Q),\n .I1(pi_counter_load_val[0]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[3]_2 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair99\" *) \n LUT5 #(\n .INIT(32'h44440004)) \n \\phaser_in_gen.phaser_in_i_11__2 \n (.I0(Q),\n .I1(pi_counter_load_val[0]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(COUNTERLOADVAL[0]));\n (* SOFT_HLUTNM = \"soft_lutpair110\" *) \n LUT5 #(\n .INIT(32'h0000BA00)) \n \\phaser_in_gen.phaser_in_i_1__0 \n (.I0(calib_in_common),\n .I1(\\calib_sel_reg[3] [0]),\n .I2(\\calib_sel_reg[3] [1]),\n .I3(pi_counter_load_en),\n .I4(Q),\n .O(\\pi_dqs_found_lanes_r1_reg[2]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair89\" *) \n LUT5 #(\n .INIT(32'h0000BA00)) \n \\phaser_in_gen.phaser_in_i_1__1 \n (.I0(calib_in_common),\n .I1(\\calib_sel_reg[3] [1]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(pi_counter_load_en),\n .I4(Q),\n .O(\\pi_dqs_found_lanes_r1_reg[1]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair110\" *) \n LUT5 #(\n .INIT(32'h0000AB00)) \n \\phaser_in_gen.phaser_in_i_1__2 \n (.I0(calib_in_common),\n .I1(\\calib_sel_reg[3] [1]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(pi_counter_load_en),\n .I4(Q),\n .O(\\pi_dqs_found_lanes_r1_reg[0]_1 ));\n LUT5 #(\n .INIT(32'h0000AAA8)) \n \\phaser_in_gen.phaser_in_i_3 \n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .I1(rdlvl_pi_stg2_f_en),\n .I2(prbs_pi_stg2_f_en),\n .I3(tempmon_pi_f_en_r),\n .I4(Q),\n .O(\\pi_dqs_found_lanes_r1_reg[3]_0 ));\n LUT5 #(\n .INIT(32'h0000AAA8)) \n \\phaser_in_gen.phaser_in_i_3__0 \n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .I1(rdlvl_pi_stg2_f_en),\n .I2(prbs_pi_stg2_f_en),\n .I3(tempmon_pi_f_en_r),\n .I4(Q),\n .O(\\pi_dqs_found_lanes_r1_reg[2]_0 ));\n LUT5 #(\n .INIT(32'h0000AAA8)) \n \\phaser_in_gen.phaser_in_i_3__1 \n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_2 ),\n .I1(rdlvl_pi_stg2_f_en),\n .I2(prbs_pi_stg2_f_en),\n .I3(tempmon_pi_f_en_r),\n .I4(Q),\n .O(\\pi_dqs_found_lanes_r1_reg[1]_0 ));\n LUT5 #(\n .INIT(32'h0000AAA8)) \n \\phaser_in_gen.phaser_in_i_3__2 \n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_3 ),\n .I1(rdlvl_pi_stg2_f_en),\n .I2(prbs_pi_stg2_f_en),\n .I3(tempmon_pi_f_en_r),\n .I4(Q),\n .O(\\pi_dqs_found_lanes_r1_reg[0]_0 ));\n LUT5 #(\n .INIT(32'h0000AAA8)) \n \\phaser_in_gen.phaser_in_i_4 \n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .I1(rdlvl_pi_stg2_f_incdec),\n .I2(prbs_pi_stg2_f_incdec),\n .I3(tempmon_pi_f_inc_r),\n .I4(Q),\n .O(\\pi_dqs_found_lanes_r1_reg[3] ));\n LUT5 #(\n .INIT(32'h0000AAA8)) \n \\phaser_in_gen.phaser_in_i_4__0 \n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .I1(rdlvl_pi_stg2_f_incdec),\n .I2(prbs_pi_stg2_f_incdec),\n .I3(tempmon_pi_f_inc_r),\n .I4(Q),\n .O(\\pi_dqs_found_lanes_r1_reg[2] ));\n LUT5 #(\n .INIT(32'h0000AAA8)) \n \\phaser_in_gen.phaser_in_i_4__1 \n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_2 ),\n .I1(rdlvl_pi_stg2_f_incdec),\n .I2(prbs_pi_stg2_f_incdec),\n .I3(tempmon_pi_f_inc_r),\n .I4(Q),\n .O(\\pi_dqs_found_lanes_r1_reg[1] ));\n LUT5 #(\n .INIT(32'h0000AAA8)) \n \\phaser_in_gen.phaser_in_i_4__2 \n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_3 ),\n .I1(rdlvl_pi_stg2_f_incdec),\n .I2(prbs_pi_stg2_f_incdec),\n .I3(tempmon_pi_f_inc_r),\n .I4(Q),\n .O(\\pi_dqs_found_lanes_r1_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair94\" *) \n LUT5 #(\n .INIT(32'h44440040)) \n \\phaser_in_gen.phaser_in_i_6 \n (.I0(Q),\n .I1(pi_counter_load_val[5]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[1]_2 [5]));\n (* SOFT_HLUTNM = \"soft_lutpair100\" *) \n LUT5 #(\n .INIT(32'h44440040)) \n \\phaser_in_gen.phaser_in_i_6__0 \n (.I0(Q),\n .I1(pi_counter_load_val[5]),\n .I2(\\calib_sel_reg[3] [1]),\n .I3(\\calib_sel_reg[3] [0]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[2]_2 [5]));\n (* SOFT_HLUTNM = \"soft_lutpair100\" *) \n LUT5 #(\n .INIT(32'h44444000)) \n \\phaser_in_gen.phaser_in_i_6__1 \n (.I0(Q),\n .I1(pi_counter_load_val[5]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[3]_2 [5]));\n (* SOFT_HLUTNM = \"soft_lutpair94\" *) \n LUT5 #(\n .INIT(32'h44440004)) \n \\phaser_in_gen.phaser_in_i_6__2 \n (.I0(Q),\n .I1(pi_counter_load_val[5]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(COUNTERLOADVAL[5]));\n (* SOFT_HLUTNM = \"soft_lutpair95\" *) \n LUT5 #(\n .INIT(32'h44440040)) \n \\phaser_in_gen.phaser_in_i_7 \n (.I0(Q),\n .I1(pi_counter_load_val[4]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[1]_2 [4]));\n (* SOFT_HLUTNM = \"soft_lutpair101\" *) \n LUT5 #(\n .INIT(32'h44440040)) \n \\phaser_in_gen.phaser_in_i_7__0 \n (.I0(Q),\n .I1(pi_counter_load_val[4]),\n .I2(\\calib_sel_reg[3] [1]),\n .I3(\\calib_sel_reg[3] [0]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[2]_2 [4]));\n (* SOFT_HLUTNM = \"soft_lutpair101\" *) \n LUT5 #(\n .INIT(32'h44444000)) \n \\phaser_in_gen.phaser_in_i_7__1 \n (.I0(Q),\n .I1(pi_counter_load_val[4]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[3]_2 [4]));\n (* SOFT_HLUTNM = \"soft_lutpair95\" *) \n LUT5 #(\n .INIT(32'h44440004)) \n \\phaser_in_gen.phaser_in_i_7__2 \n (.I0(Q),\n .I1(pi_counter_load_val[4]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(COUNTERLOADVAL[4]));\n (* SOFT_HLUTNM = \"soft_lutpair96\" *) \n LUT5 #(\n .INIT(32'h44440040)) \n \\phaser_in_gen.phaser_in_i_8 \n (.I0(Q),\n .I1(pi_counter_load_val[3]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[1]_2 [3]));\n (* SOFT_HLUTNM = \"soft_lutpair102\" *) \n LUT5 #(\n .INIT(32'h44440040)) \n \\phaser_in_gen.phaser_in_i_8__0 \n (.I0(Q),\n .I1(pi_counter_load_val[3]),\n .I2(\\calib_sel_reg[3] [1]),\n .I3(\\calib_sel_reg[3] [0]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[2]_2 [3]));\n (* SOFT_HLUTNM = \"soft_lutpair102\" *) \n LUT5 #(\n .INIT(32'h44444000)) \n \\phaser_in_gen.phaser_in_i_8__1 \n (.I0(Q),\n .I1(pi_counter_load_val[3]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[3]_2 [3]));\n (* SOFT_HLUTNM = \"soft_lutpair96\" *) \n LUT5 #(\n .INIT(32'h44440004)) \n \\phaser_in_gen.phaser_in_i_8__2 \n (.I0(Q),\n .I1(pi_counter_load_val[3]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(COUNTERLOADVAL[3]));\n (* SOFT_HLUTNM = \"soft_lutpair97\" *) \n LUT5 #(\n .INIT(32'h44440040)) \n \\phaser_in_gen.phaser_in_i_9 \n (.I0(Q),\n .I1(pi_counter_load_val[2]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[1]_2 [2]));\n (* SOFT_HLUTNM = \"soft_lutpair103\" *) \n LUT5 #(\n .INIT(32'h44440040)) \n \\phaser_in_gen.phaser_in_i_9__0 \n (.I0(Q),\n .I1(pi_counter_load_val[2]),\n .I2(\\calib_sel_reg[3] [1]),\n .I3(\\calib_sel_reg[3] [0]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[2]_2 [2]));\n (* SOFT_HLUTNM = \"soft_lutpair103\" *) \n LUT5 #(\n .INIT(32'h44444000)) \n \\phaser_in_gen.phaser_in_i_9__1 \n (.I0(Q),\n .I1(pi_counter_load_val[2]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[3]_2 [2]));\n (* SOFT_HLUTNM = \"soft_lutpair97\" *) \n LUT5 #(\n .INIT(32'h44440004)) \n \\phaser_in_gen.phaser_in_i_9__2 \n (.I0(Q),\n .I1(pi_counter_load_val[2]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(COUNTERLOADVAL[2]));\n (* SOFT_HLUTNM = \"soft_lutpair208\" *) \n LUT2 #(\n .INIT(4'hE)) \n pi_cnt_dec_i_2\n (.I0(wait_cnt_r_reg__0[2]),\n .I1(wait_cnt_r_reg__0[3]),\n .O(pi_cnt_dec_reg_0));\n FDRE #(\n .INIT(1'b0)) \n pi_cnt_dec_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\wait_cnt_r_reg[0]_1 ),\n .Q(pi_en_stg2_f_timing_reg_0),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n pi_en_stg2_f_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_en_stg2_f_timing),\n .Q(rdlvl_pi_stg2_f_en),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair234\" *) \n LUT2 #(\n .INIT(4'hE)) \n pi_en_stg2_f_timing_i_1\n (.I0(cal1_dlyce_cpt_r_reg_n_0),\n .I1(pi_en_stg2_f_timing_reg_0),\n .O(pi_en_stg2_f_timing_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n pi_en_stg2_f_timing_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_en_stg2_f_timing_i_1_n_0),\n .Q(pi_en_stg2_f_timing),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n pi_fine_dly_dec_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(fine_dly_dec_done_r2),\n .Q(pi_fine_dly_dec_done),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h40404F40)) \n \\pi_rdval_cnt[0]_i_1 \n (.I0(\\calib_sel_reg[3] [2]),\n .I1(\\pi_counter_read_val_reg[5] [0]),\n .I2(\\pi_rdval_cnt[5]_i_4_n_0 ),\n .I3(\\pi_rdval_cnt_reg[1]_0 ),\n .I4(pi_rdval_cnt[0]),\n .O(\\pi_rdval_cnt[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFB0808FBFB08FB08)) \n \\pi_rdval_cnt[1]_i_1 \n (.I0(\\rdlvl_cpt_tap_cnt_reg[1] ),\n .I1(dqs_po_dec_done_r1),\n .I2(dqs_po_dec_done_r2),\n .I3(pi_rdval_cnt[1]),\n .I4(pi_rdval_cnt[0]),\n .I5(\\pi_rdval_cnt_reg[1]_0 ),\n .O(\\pi_rdval_cnt[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hB8B8B888888888B8)) \n \\pi_rdval_cnt[2]_i_1 \n (.I0(\\rdlvl_cpt_tap_cnt_reg[2] ),\n .I1(\\pi_rdval_cnt[5]_i_4_n_0 ),\n .I2(\\pi_rdval_cnt_reg[1]_0 ),\n .I3(pi_rdval_cnt[1]),\n .I4(pi_rdval_cnt[0]),\n .I5(pi_rdval_cnt[2]),\n .O(\\pi_rdval_cnt[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0808FB08FB080808)) \n \\pi_rdval_cnt[3]_i_1 \n (.I0(\\calib_sel_reg[3]_0 [1]),\n .I1(dqs_po_dec_done_r1),\n .I2(dqs_po_dec_done_r2),\n .I3(\\pi_rdval_cnt_reg[1]_0 ),\n .I4(\\pi_rdval_cnt[3]_i_2_n_0 ),\n .I5(pi_rdval_cnt[3]),\n .O(\\pi_rdval_cnt[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair201\" *) \n LUT3 #(\n .INIT(8'h01)) \n \\pi_rdval_cnt[3]_i_2 \n (.I0(pi_rdval_cnt[0]),\n .I1(pi_rdval_cnt[1]),\n .I2(pi_rdval_cnt[2]),\n .O(\\pi_rdval_cnt[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0808FBFBFB080808)) \n \\pi_rdval_cnt[4]_i_1 \n (.I0(\\rdlvl_cpt_tap_cnt_reg[4] ),\n .I1(dqs_po_dec_done_r1),\n .I2(dqs_po_dec_done_r2),\n .I3(pi_rdval_cnt[5]),\n .I4(\\pi_rdval_cnt[4]_i_2_n_0 ),\n .I5(pi_rdval_cnt[4]),\n .O(\\pi_rdval_cnt[4]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair186\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\pi_rdval_cnt[4]_i_2 \n (.I0(pi_rdval_cnt[2]),\n .I1(pi_rdval_cnt[1]),\n .I2(pi_rdval_cnt[0]),\n .I3(pi_rdval_cnt[3]),\n .O(\\pi_rdval_cnt[4]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'hBBFB)) \n \\pi_rdval_cnt[5]_i_1 \n (.I0(pi_en_stg2_f_timing_reg_0),\n .I1(\\pi_rdval_cnt_reg[1]_0 ),\n .I2(dqs_po_dec_done_r1),\n .I3(dqs_po_dec_done_r2),\n .O(\\pi_rdval_cnt[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h40404F40)) \n \\pi_rdval_cnt[5]_i_2 \n (.I0(\\calib_sel_reg[3] [2]),\n .I1(\\pi_counter_read_val_reg[5] [4]),\n .I2(\\pi_rdval_cnt[5]_i_4_n_0 ),\n .I3(pi_rdval_cnt[5]),\n .I4(\\pi_rdval_cnt[5]_i_5_n_0 ),\n .O(\\pi_rdval_cnt[5]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\pi_rdval_cnt[5]_i_3 \n (.I0(pi_rdval_cnt[5]),\n .I1(pi_rdval_cnt[4]),\n .I2(pi_rdval_cnt[2]),\n .I3(pi_rdval_cnt[1]),\n .I4(pi_rdval_cnt[0]),\n .I5(pi_rdval_cnt[3]),\n .O(\\pi_rdval_cnt_reg[1]_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\pi_rdval_cnt[5]_i_4 \n (.I0(dqs_po_dec_done_r1),\n .I1(dqs_po_dec_done_r2),\n .O(\\pi_rdval_cnt[5]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair186\" *) \n LUT5 #(\n .INIT(32'h00000001)) \n \\pi_rdval_cnt[5]_i_5 \n (.I0(pi_rdval_cnt[3]),\n .I1(pi_rdval_cnt[0]),\n .I2(pi_rdval_cnt[1]),\n .I3(pi_rdval_cnt[2]),\n .I4(pi_rdval_cnt[4]),\n .O(\\pi_rdval_cnt[5]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\pi_rdval_cnt_reg[0] \n (.C(CLK),\n .CE(\\pi_rdval_cnt[5]_i_1_n_0 ),\n .D(\\pi_rdval_cnt[0]_i_1_n_0 ),\n .Q(pi_rdval_cnt[0]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE #(\n .INIT(1'b0)) \n \\pi_rdval_cnt_reg[1] \n (.C(CLK),\n .CE(\\pi_rdval_cnt[5]_i_1_n_0 ),\n .D(\\pi_rdval_cnt[1]_i_1_n_0 ),\n .Q(pi_rdval_cnt[1]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE #(\n .INIT(1'b0)) \n \\pi_rdval_cnt_reg[2] \n (.C(CLK),\n .CE(\\pi_rdval_cnt[5]_i_1_n_0 ),\n .D(\\pi_rdval_cnt[2]_i_1_n_0 ),\n .Q(pi_rdval_cnt[2]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE #(\n .INIT(1'b0)) \n \\pi_rdval_cnt_reg[3] \n (.C(CLK),\n .CE(\\pi_rdval_cnt[5]_i_1_n_0 ),\n .D(\\pi_rdval_cnt[3]_i_1_n_0 ),\n .Q(pi_rdval_cnt[3]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE #(\n .INIT(1'b0)) \n \\pi_rdval_cnt_reg[4] \n (.C(CLK),\n .CE(\\pi_rdval_cnt[5]_i_1_n_0 ),\n .D(\\pi_rdval_cnt[4]_i_1_n_0 ),\n .Q(pi_rdval_cnt[4]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE #(\n .INIT(1'b0)) \n \\pi_rdval_cnt_reg[5] \n (.C(CLK),\n .CE(\\pi_rdval_cnt[5]_i_1_n_0 ),\n .D(\\pi_rdval_cnt[5]_i_2_n_0 ),\n .Q(pi_rdval_cnt[5]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE #(\n .INIT(1'b0)) \n pi_stg2_f_incdec_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_stg2_f_incdec_timing),\n .Q(rdlvl_pi_stg2_f_incdec),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair200\" *) \n LUT4 #(\n .INIT(16'h0008)) \n pi_stg2_f_incdec_timing_i_1__0\n (.I0(cal1_dlyce_cpt_r_reg_n_0),\n .I1(cal1_dlyinc_cpt_r_reg_n_0),\n .I2(pi_en_stg2_f_timing_reg_0),\n .I3(rstdiv0_sync_r1_reg_rep__22),\n .O(pi_stg2_f_incdec_timing0));\n FDRE #(\n .INIT(1'b0)) \n pi_stg2_f_incdec_timing_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_stg2_f_incdec_timing0),\n .Q(pi_stg2_f_incdec_timing),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n pi_stg2_load_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_stg2_load_timing),\n .Q(pi_counter_load_en),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n pi_stg2_load_timing_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\regl_dqs_cnt_reg[2]_0 ),\n .Q(pi_stg2_load_timing),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\pi_stg2_reg_l_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_stg2_reg_l_timing[0]),\n .Q(pi_counter_load_val[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\pi_stg2_reg_l_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_stg2_reg_l_timing[1]),\n .Q(pi_counter_load_val[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\pi_stg2_reg_l_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_stg2_reg_l_timing[2]),\n .Q(pi_counter_load_val[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\pi_stg2_reg_l_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_stg2_reg_l_timing[3]),\n .Q(pi_counter_load_val[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\pi_stg2_reg_l_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_stg2_reg_l_timing[4]),\n .Q(pi_counter_load_val[4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\pi_stg2_reg_l_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_stg2_reg_l_timing[5]),\n .Q(pi_counter_load_val[5]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\pi_stg2_reg_l_timing[0]_i_1 \n (.I0(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][0] ),\n .I1(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][0] ),\n .I2(regl_dqs_cnt[0]),\n .I3(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][0] ),\n .I4(regl_dqs_cnt[1]),\n .I5(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][0] ),\n .O(\\pi_stg2_reg_l_timing[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\pi_stg2_reg_l_timing[1]_i_1 \n (.I0(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][1] ),\n .I1(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][1] ),\n .I2(regl_dqs_cnt[0]),\n .I3(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][1] ),\n .I4(regl_dqs_cnt[1]),\n .I5(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][1] ),\n .O(\\pi_stg2_reg_l_timing[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\pi_stg2_reg_l_timing[2]_i_1 \n (.I0(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][2] ),\n .I1(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][2] ),\n .I2(regl_dqs_cnt[0]),\n .I3(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][2] ),\n .I4(regl_dqs_cnt[1]),\n .I5(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][2] ),\n .O(\\pi_stg2_reg_l_timing[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\pi_stg2_reg_l_timing[3]_i_1 \n (.I0(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][3] ),\n .I1(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][3] ),\n .I2(regl_dqs_cnt[0]),\n .I3(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][3] ),\n .I4(regl_dqs_cnt[1]),\n .I5(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][3] ),\n .O(\\pi_stg2_reg_l_timing[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\pi_stg2_reg_l_timing[4]_i_1 \n (.I0(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][4] ),\n .I1(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][4] ),\n .I2(regl_dqs_cnt[0]),\n .I3(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][4] ),\n .I4(regl_dqs_cnt[1]),\n .I5(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][4] ),\n .O(\\pi_stg2_reg_l_timing[4]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hEF)) \n \\pi_stg2_reg_l_timing[5]_i_1 \n (.I0(\\pi_stg2_reg_l_timing_reg[0]_0 ),\n .I1(\\regl_dqs_cnt_r_reg[2]_0 ),\n .I2(\\regl_dqs_cnt_reg[0]_0 ),\n .O(\\pi_stg2_reg_l_timing[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\pi_stg2_reg_l_timing[5]_i_2 \n (.I0(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][5] ),\n .I1(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][5] ),\n .I2(regl_dqs_cnt[0]),\n .I3(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][5] ),\n .I4(regl_dqs_cnt[1]),\n .I5(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][5] ),\n .O(\\pi_stg2_reg_l_timing[5]_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\pi_stg2_reg_l_timing_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\pi_stg2_reg_l_timing[0]_i_1_n_0 ),\n .Q(pi_stg2_reg_l_timing[0]),\n .R(\\pi_stg2_reg_l_timing[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\pi_stg2_reg_l_timing_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\pi_stg2_reg_l_timing[1]_i_1_n_0 ),\n .Q(pi_stg2_reg_l_timing[1]),\n .R(\\pi_stg2_reg_l_timing[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\pi_stg2_reg_l_timing_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\pi_stg2_reg_l_timing[2]_i_1_n_0 ),\n .Q(pi_stg2_reg_l_timing[2]),\n .R(\\pi_stg2_reg_l_timing[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\pi_stg2_reg_l_timing_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\pi_stg2_reg_l_timing[3]_i_1_n_0 ),\n .Q(pi_stg2_reg_l_timing[3]),\n .R(\\pi_stg2_reg_l_timing[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\pi_stg2_reg_l_timing_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\pi_stg2_reg_l_timing[4]_i_1_n_0 ),\n .Q(pi_stg2_reg_l_timing[4]),\n .R(\\pi_stg2_reg_l_timing[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\pi_stg2_reg_l_timing_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\pi_stg2_reg_l_timing[5]_i_2_n_0 ),\n .Q(pi_stg2_reg_l_timing[5]),\n .R(\\pi_stg2_reg_l_timing[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFEFFFEFFFFFFFE)) \n prech_req_r_i_1\n (.I0(rdlvl_prech_req),\n .I1(wrcal_prech_req),\n .I2(complex_ocal_ref_req),\n .I3(prbs_rdlvl_prech_req_reg),\n .I4(dqs_found_prech_req),\n .I5(\\init_state_r_reg[5]_0 ),\n .O(prech_req));\n FDRE #(\n .INIT(1'b0)) \n \\rd_mux_sel_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rd_mux_sel_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [1]),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair238\" *) \n LUT2 #(\n .INIT(4'h4)) \n \\rdlvl_cpt_tap_cnt[1]_i_1 \n (.I0(\\calib_sel_reg[3] [2]),\n .I1(\\pi_counter_read_val_reg[5] [1]),\n .O(\\rdlvl_cpt_tap_cnt_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair238\" *) \n LUT2 #(\n .INIT(4'h4)) \n \\rdlvl_cpt_tap_cnt[2]_i_1 \n (.I0(\\calib_sel_reg[3] [2]),\n .I1(\\pi_counter_read_val_reg[5] [2]),\n .O(\\rdlvl_cpt_tap_cnt_reg[2] ));\n LUT2 #(\n .INIT(4'h4)) \n \\rdlvl_cpt_tap_cnt[4]_i_1 \n (.I0(\\calib_sel_reg[3] [2]),\n .I1(\\pi_counter_read_val_reg[5] [3]),\n .O(\\rdlvl_cpt_tap_cnt_reg[4] ));\n LUT5 #(\n .INIT(32'h00000001)) \n \\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1 \n (.I0(\\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ),\n .I1(\\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [0]),\n .I2(\\rnk_cnt_r_reg_n_0_[1] ),\n .I3(\\rnk_cnt_r_reg_n_0_[0] ),\n .I4(\\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [1]),\n .O(\\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFEFFFFFFFFFFFFF)) \n \\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2 \n (.I0(\\cal1_state_r1_reg_n_0_[5] ),\n .I1(\\cal1_state_r1_reg_n_0_[4] ),\n .I2(\\cal1_state_r1_reg_n_0_[2] ),\n .I3(\\cal1_state_r1_reg_n_0_[0] ),\n .I4(\\cal1_state_r1_reg_n_0_[3] ),\n .I5(\\cal1_state_r1_reg_n_0_[1] ),\n .O(\\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h00000004)) \n \\rdlvl_dqs_tap_cnt_r[0][1][5]_i_1 \n (.I0(\\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ),\n .I1(\\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [0]),\n .I2(\\rnk_cnt_r_reg_n_0_[1] ),\n .I3(\\rnk_cnt_r_reg_n_0_[0] ),\n .I4(\\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [1]),\n .O(rdlvl_dqs_tap_cnt_r));\n LUT5 #(\n .INIT(32'h00000002)) \n \\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1 \n (.I0(\\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [1]),\n .I1(\\rnk_cnt_r_reg_n_0_[1] ),\n .I2(\\rnk_cnt_r_reg_n_0_[0] ),\n .I3(\\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ),\n .I4(\\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [0]),\n .O(\\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h00020000)) \n \\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1 \n (.I0(\\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [1]),\n .I1(\\rnk_cnt_r_reg_n_0_[1] ),\n .I2(\\rnk_cnt_r_reg_n_0_[0] ),\n .I3(\\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ),\n .I4(\\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [0]),\n .O(\\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rdlvl_dqs_tap_cnt_r_reg[0][0][0] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][0] ),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE #(\n .INIT(1'b0)) \n \\rdlvl_dqs_tap_cnt_r_reg[0][0][1] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][1] ),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE #(\n .INIT(1'b0)) \n \\rdlvl_dqs_tap_cnt_r_reg[0][0][2] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][2] ),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE #(\n .INIT(1'b0)) \n \\rdlvl_dqs_tap_cnt_r_reg[0][0][3] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][3] ),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE #(\n .INIT(1'b0)) \n \\rdlvl_dqs_tap_cnt_r_reg[0][0][4] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[4] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][4] ),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE #(\n .INIT(1'b0)) \n \\rdlvl_dqs_tap_cnt_r_reg[0][0][5] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[5] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][5] ),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE #(\n .INIT(1'b0)) \n \\rdlvl_dqs_tap_cnt_r_reg[0][1][0] \n (.C(CLK),\n .CE(rdlvl_dqs_tap_cnt_r),\n .D(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][0] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n \\rdlvl_dqs_tap_cnt_r_reg[0][1][1] \n (.C(CLK),\n .CE(rdlvl_dqs_tap_cnt_r),\n .D(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][1] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n \\rdlvl_dqs_tap_cnt_r_reg[0][1][2] \n (.C(CLK),\n .CE(rdlvl_dqs_tap_cnt_r),\n .D(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][2] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n \\rdlvl_dqs_tap_cnt_r_reg[0][1][3] \n (.C(CLK),\n .CE(rdlvl_dqs_tap_cnt_r),\n .D(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][3] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n \\rdlvl_dqs_tap_cnt_r_reg[0][1][4] \n (.C(CLK),\n .CE(rdlvl_dqs_tap_cnt_r),\n .D(\\tap_cnt_cpt_r_reg_n_0_[4] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][4] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n \\rdlvl_dqs_tap_cnt_r_reg[0][1][5] \n (.C(CLK),\n .CE(rdlvl_dqs_tap_cnt_r),\n .D(\\tap_cnt_cpt_r_reg_n_0_[5] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][5] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n \\rdlvl_dqs_tap_cnt_r_reg[0][2][0] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][0] ),\n .R(rstdiv0_sync_r1_reg_rep__14[0]));\n FDRE #(\n .INIT(1'b0)) \n \\rdlvl_dqs_tap_cnt_r_reg[0][2][1] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][1] ),\n .R(rstdiv0_sync_r1_reg_rep__14[0]));\n FDRE #(\n .INIT(1'b0)) \n \\rdlvl_dqs_tap_cnt_r_reg[0][2][2] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][2] ),\n .R(rstdiv0_sync_r1_reg_rep__14[0]));\n FDRE #(\n .INIT(1'b0)) \n \\rdlvl_dqs_tap_cnt_r_reg[0][2][3] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][3] ),\n .R(rstdiv0_sync_r1_reg_rep__14[0]));\n FDRE #(\n .INIT(1'b0)) \n \\rdlvl_dqs_tap_cnt_r_reg[0][2][4] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[4] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][4] ),\n .R(rstdiv0_sync_r1_reg_rep__14[0]));\n FDRE #(\n .INIT(1'b0)) \n \\rdlvl_dqs_tap_cnt_r_reg[0][2][5] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[5] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][5] ),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE #(\n .INIT(1'b0)) \n \\rdlvl_dqs_tap_cnt_r_reg[0][3][0] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][0] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n \\rdlvl_dqs_tap_cnt_r_reg[0][3][1] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][1] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n \\rdlvl_dqs_tap_cnt_r_reg[0][3][2] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][2] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n \\rdlvl_dqs_tap_cnt_r_reg[0][3][3] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][3] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n \\rdlvl_dqs_tap_cnt_r_reg[0][3][4] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[4] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][4] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n \\rdlvl_dqs_tap_cnt_r_reg[0][3][5] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[5] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][5] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE #(\n .INIT(1'b0)) \n rdlvl_last_byte_done_int_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_cal1_state_r_reg[4]_4 ),\n .Q(rdlvl_last_byte_done),\n .R(rstdiv0_sync_r1_reg_rep__13));\n LUT6 #(\n .INIT(64'hFFFFFFFFCC88FEAA)) \n rdlvl_pi_incdec_i_2\n (.I0(out[3]),\n .I1(cal1_wait_r),\n .I2(store_sr_req_r_reg_0),\n .I3(out[1]),\n .I4(out[2]),\n .I5(rdlvl_pi_incdec_i_4_n_0),\n .O(rdlvl_pi_incdec_reg_0));\n LUT6 #(\n .INIT(64'h000000000000FD0D)) \n rdlvl_pi_incdec_i_4\n (.I0(mpr_rdlvl_start_reg),\n .I1(mpr_rdlvl_start_r),\n .I2(cal1_state_r),\n .I3(cal1_wait_r),\n .I4(out[1]),\n .I5(out[4]),\n .O(rdlvl_pi_incdec_i_4_n_0));\n LUT6 #(\n .INIT(64'h0000000105A5AA05)) \n rdlvl_pi_incdec_i_5\n (.I0(out[4]),\n .I1(cal1_wait_r),\n .I2(out[3]),\n .I3(out[0]),\n .I4(out[1]),\n .I5(cal1_state_r),\n .O(rdlvl_pi_incdec_i_5_n_0));\n LUT6 #(\n .INIT(64'h0000000000001000)) \n rdlvl_pi_incdec_i_6\n (.I0(out[1]),\n .I1(cal1_state_r),\n .I2(out[3]),\n .I3(out[4]),\n .I4(out[0]),\n .I5(cal1_wait_r),\n .O(rdlvl_pi_incdec_i_6_n_0));\n FDRE #(\n .INIT(1'b0)) \n rdlvl_pi_incdec_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_cal1_state_r_reg[1]_0 ),\n .Q(rdlvl_pi_incdec),\n .R(rstdiv0_sync_r1_reg_rep__14[0]));\n MUXF7 rdlvl_pi_incdec_reg_i_3\n (.I0(rdlvl_pi_incdec_i_5_n_0),\n .I1(rdlvl_pi_incdec_i_6_n_0),\n .O(rdlvl_pi_incdec_reg_1),\n .S(out[2]));\n FDRE #(\n .INIT(1'b0)) \n rdlvl_prech_req_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cal1_prech_req_r_reg_n_0),\n .Q(rdlvl_prech_req),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n LUT6 #(\n .INIT(64'hBFFFFFFFFFFFFFFF)) \n rdlvl_rank_done_r_i_2\n (.I0(cal1_state_r),\n .I1(out[4]),\n .I2(mpr_rdlvl_done_r1_reg_0),\n .I3(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I4(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .I5(prech_done),\n .O(rdlvl_rank_done_r_reg_0));\n FDRE #(\n .INIT(1'b0)) \n rdlvl_rank_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_cal1_state_r_reg[4]_3 ),\n .Q(rdlvl_stg1_rank_done),\n .R(rstdiv0_sync_r1_reg_rep__13));\n (* syn_maxfan = \"30\" *) \n FDRE #(\n .INIT(1'b0)) \n rdlvl_stg1_done_int_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mpr_rdlvl_done_r_reg_1),\n .Q(rdlvl_stg1_done_r1_reg),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE #(\n .INIT(1'b0)) \n rdlvl_stg1_start_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rdlvl_stg1_start_reg),\n .Q(rdlvl_stg1_start_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0004FFFFFFFF0000)) \n \\regl_dqs_cnt[0]_i_1 \n (.I0(\\regl_dqs_cnt_r_reg[2]_0 ),\n .I1(regl_dqs_cnt[1]),\n .I2(regl_rank_cnt[0]),\n .I3(regl_rank_cnt[1]),\n .I4(\\regl_dqs_cnt_reg[0]_0 ),\n .I5(regl_dqs_cnt[0]),\n .O(\\regl_dqs_cnt[0]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hBA)) \n \\regl_dqs_cnt[1]_i_1 \n (.I0(\\pi_stg2_reg_l_timing_reg[0]_0 ),\n .I1(mpr_rdlvl_done_r2),\n .I2(mpr_rdlvl_done_r1),\n .O(\\regl_dqs_cnt[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h3337FFFFCCCC0000)) \n \\regl_dqs_cnt[1]_i_2 \n (.I0(\\regl_dqs_cnt_r_reg[2]_0 ),\n .I1(regl_dqs_cnt[0]),\n .I2(regl_rank_cnt[0]),\n .I3(regl_rank_cnt[1]),\n .I4(\\regl_dqs_cnt_reg[0]_0 ),\n .I5(regl_dqs_cnt[1]),\n .O(\\regl_dqs_cnt[1]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hAAAAAAAB)) \n \\regl_dqs_cnt[1]_i_3 \n (.I0(rstdiv0_sync_r1_reg_rep__22),\n .I1(done_cnt[2]),\n .I2(done_cnt[3]),\n .I3(done_cnt[1]),\n .I4(done_cnt[0]),\n .O(\\pi_stg2_reg_l_timing_reg[0]_0 ));\n LUT5 #(\n .INIT(32'h04444444)) \n \\regl_dqs_cnt[2]_i_1 \n (.I0(\\regl_dqs_cnt[1]_i_1_n_0 ),\n .I1(\\regl_dqs_cnt_r_reg[2]_0 ),\n .I2(regl_dqs_cnt[1]),\n .I3(regl_dqs_cnt[0]),\n .I4(\\regl_dqs_cnt_reg[0]_0 ),\n .O(\\regl_dqs_cnt[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair91\" *) \n LUT5 #(\n .INIT(32'h00000200)) \n \\regl_dqs_cnt[2]_i_2 \n (.I0(p_0_in539_in),\n .I1(done_cnt[2]),\n .I2(done_cnt[3]),\n .I3(done_cnt[0]),\n .I4(done_cnt[1]),\n .O(\\regl_dqs_cnt_reg[0]_0 ));\n LUT6 #(\n .INIT(64'h0000000000020000)) \n \\regl_dqs_cnt[2]_i_3 \n (.I0(out[1]),\n .I1(out[0]),\n .I2(out[4]),\n .I3(out[3]),\n .I4(cal1_state_r),\n .I5(out[2]),\n .O(p_0_in539_in));\n FDRE #(\n .INIT(1'b0)) \n \\regl_dqs_cnt_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(regl_dqs_cnt[0]),\n .Q(regl_dqs_cnt_r[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\regl_dqs_cnt_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(regl_dqs_cnt[1]),\n .Q(regl_dqs_cnt_r[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\regl_dqs_cnt_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\regl_dqs_cnt_r_reg[2]_0 ),\n .Q(regl_dqs_cnt_r[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\regl_dqs_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\regl_dqs_cnt[0]_i_1_n_0 ),\n .Q(regl_dqs_cnt[0]),\n .R(\\regl_dqs_cnt[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\regl_dqs_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\regl_dqs_cnt[1]_i_2_n_0 ),\n .Q(regl_dqs_cnt[1]),\n .R(\\regl_dqs_cnt[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\regl_dqs_cnt_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\regl_dqs_cnt[2]_i_1_n_0 ),\n .Q(\\regl_dqs_cnt_r_reg[2]_0 ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hCFFFFFFF20000000)) \n \\regl_rank_cnt[0]_i_1 \n (.I0(regl_rank_cnt[1]),\n .I1(\\regl_dqs_cnt_r_reg[2]_0 ),\n .I2(regl_dqs_cnt[1]),\n .I3(regl_dqs_cnt[0]),\n .I4(\\regl_dqs_cnt_reg[0]_0 ),\n .I5(regl_rank_cnt[0]),\n .O(\\regl_rank_cnt[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hDFFFFFFF20000000)) \n \\regl_rank_cnt[1]_i_1 \n (.I0(regl_rank_cnt[0]),\n .I1(\\regl_dqs_cnt_r_reg[2]_0 ),\n .I2(regl_dqs_cnt[1]),\n .I3(regl_dqs_cnt[0]),\n .I4(\\regl_dqs_cnt_reg[0]_0 ),\n .I5(regl_rank_cnt[1]),\n .O(\\regl_rank_cnt[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\regl_rank_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\regl_rank_cnt[0]_i_1_n_0 ),\n .Q(regl_rank_cnt[0]),\n .R(\\regl_dqs_cnt[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\regl_rank_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\regl_rank_cnt[1]_i_1_n_0 ),\n .Q(regl_rank_cnt[1]),\n .R(\\regl_dqs_cnt[1]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\right_edge_taps_r[0]_i_1 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .I1(out[3]),\n .O(\\right_edge_taps_r[0]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\right_edge_taps_r[1]_i_1 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .I1(out[3]),\n .O(\\right_edge_taps_r[1]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\right_edge_taps_r[2]_i_1 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .I1(out[3]),\n .O(\\right_edge_taps_r[2]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\right_edge_taps_r[3]_i_1 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .I1(out[3]),\n .O(\\right_edge_taps_r[3]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\right_edge_taps_r[4]_i_1 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[4] ),\n .I1(out[3]),\n .O(\\right_edge_taps_r[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8888888800002000)) \n \\right_edge_taps_r[5]_i_1 \n (.I0(\\right_edge_taps_r_reg[0]_1 ),\n .I1(out[3]),\n .I2(\\right_edge_taps_r_reg[0]_2 ),\n .I3(found_stable_eye_last_r),\n .I4(\\right_edge_taps_r_reg[0]_0 ),\n .I5(out[2]),\n .O(\\right_edge_taps_r[5]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\right_edge_taps_r[5]_i_2 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[5] ),\n .I1(out[3]),\n .O(\\right_edge_taps_r[5]_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\right_edge_taps_r_reg[0] \n (.C(CLK),\n .CE(\\right_edge_taps_r[5]_i_1_n_0 ),\n .D(\\right_edge_taps_r[0]_i_1_n_0 ),\n .Q(right_edge_taps_r__0[0]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE #(\n .INIT(1'b0)) \n \\right_edge_taps_r_reg[1] \n (.C(CLK),\n .CE(\\right_edge_taps_r[5]_i_1_n_0 ),\n .D(\\right_edge_taps_r[1]_i_1_n_0 ),\n .Q(right_edge_taps_r__0[1]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE #(\n .INIT(1'b0)) \n \\right_edge_taps_r_reg[2] \n (.C(CLK),\n .CE(\\right_edge_taps_r[5]_i_1_n_0 ),\n .D(\\right_edge_taps_r[2]_i_1_n_0 ),\n .Q(right_edge_taps_r__0[2]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE #(\n .INIT(1'b0)) \n \\right_edge_taps_r_reg[3] \n (.C(CLK),\n .CE(\\right_edge_taps_r[5]_i_1_n_0 ),\n .D(\\right_edge_taps_r[3]_i_1_n_0 ),\n .Q(right_edge_taps_r__0[3]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE #(\n .INIT(1'b0)) \n \\right_edge_taps_r_reg[4] \n (.C(CLK),\n .CE(\\right_edge_taps_r[5]_i_1_n_0 ),\n .D(\\right_edge_taps_r[4]_i_1_n_0 ),\n .Q(right_edge_taps_r__0[4]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE #(\n .INIT(1'b0)) \n \\right_edge_taps_r_reg[5] \n (.C(CLK),\n .CE(\\right_edge_taps_r[5]_i_1_n_0 ),\n .D(\\right_edge_taps_r[5]_i_2_n_0 ),\n .Q(right_edge_taps_r__0[5]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n LUT3 #(\n .INIT(8'h34)) \n \\rnk_cnt_r[0]_i_1__0 \n (.I0(cal1_state_r),\n .I1(\\rnk_cnt_r[1]_i_2_n_0 ),\n .I2(\\rnk_cnt_r_reg_n_0_[0] ),\n .O(\\rnk_cnt_r[0]_i_1__0_n_0 ));\n LUT4 #(\n .INIT(16'h1F20)) \n \\rnk_cnt_r[1]_i_1__0 \n (.I0(\\rnk_cnt_r_reg_n_0_[0] ),\n .I1(cal1_state_r),\n .I2(\\rnk_cnt_r[1]_i_2_n_0 ),\n .I3(\\rnk_cnt_r_reg_n_0_[1] ),\n .O(\\rnk_cnt_r[1]_i_1__0_n_0 ));\n LUT6 #(\n .INIT(64'h00800A0000000000)) \n \\rnk_cnt_r[1]_i_2 \n (.I0(out[1]),\n .I1(\\rnk_cnt_r[1]_i_3_n_0 ),\n .I2(out[3]),\n .I3(cal1_state_r),\n .I4(out[4]),\n .I5(\\cal1_cnt_cpt_r[1]_i_5_n_0 ),\n .O(\\rnk_cnt_r[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hE000000000000000)) \n \\rnk_cnt_r[1]_i_3 \n (.I0(\\rnk_cnt_r_reg_n_0_[1] ),\n .I1(\\rnk_cnt_r_reg_n_0_[0] ),\n .I2(mpr_rdlvl_done_r1_reg_0),\n .I3(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I4(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .I5(prech_done),\n .O(\\rnk_cnt_r[1]_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rnk_cnt_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rnk_cnt_r[0]_i_1__0_n_0 ),\n .Q(\\rnk_cnt_r_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE #(\n .INIT(1'b0)) \n \\rnk_cnt_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rnk_cnt_r[1]_i_1__0_n_0 ),\n .Q(\\rnk_cnt_r_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n LUT6 #(\n .INIT(64'h00000000AAAE0000)) \n samp_cnt_done_r_i_1\n (.I0(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I1(samp_cnt_done_r_i_2_n_0),\n .I2(samp_cnt_done_r_i_3_n_0),\n .I3(samp_cnt_done_r_i_4_n_0),\n .I4(samp_edge_cnt0_en_r),\n .I5(rstdiv0_sync_r1_reg_rep__22),\n .O(samp_cnt_done_r_i_1_n_0));\n LUT4 #(\n .INIT(16'h0010)) \n samp_cnt_done_r_i_2\n (.I0(samp_edge_cnt1_r_reg[11]),\n .I1(samp_edge_cnt1_r_reg[7]),\n .I2(samp_edge_cnt1_r_reg[0]),\n .I3(samp_edge_cnt1_r_reg[6]),\n .O(samp_cnt_done_r_i_2_n_0));\n LUT4 #(\n .INIT(16'hFFFE)) \n samp_cnt_done_r_i_3\n (.I0(samp_edge_cnt1_r_reg[8]),\n .I1(samp_edge_cnt1_r_reg[3]),\n .I2(samp_edge_cnt1_r_reg[1]),\n .I3(samp_edge_cnt1_r_reg[10]),\n .O(samp_cnt_done_r_i_3_n_0));\n LUT4 #(\n .INIT(16'hFFFE)) \n samp_cnt_done_r_i_4\n (.I0(samp_edge_cnt1_r_reg[4]),\n .I1(samp_edge_cnt1_r_reg[9]),\n .I2(samp_edge_cnt1_r_reg[2]),\n .I3(samp_edge_cnt1_r_reg[5]),\n .O(samp_cnt_done_r_i_4_n_0));\n FDRE #(\n .INIT(1'b0)) \n samp_cnt_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(samp_cnt_done_r_i_1_n_0),\n .Q(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0100000002003000)) \n samp_edge_cnt0_en_r_i_1\n (.I0(out[1]),\n .I1(cal1_state_r),\n .I2(out[4]),\n .I3(out[0]),\n .I4(out[2]),\n .I5(out[3]),\n .O(pb_detect_edge));\n FDRE #(\n .INIT(1'b0)) \n samp_edge_cnt0_en_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pb_detect_edge),\n .Q(samp_edge_cnt0_en_r),\n .R(1'b0));\n LUT2 #(\n .INIT(4'hE)) \n \\samp_edge_cnt0_r[0]_i_2 \n (.I0(sr_valid_r2),\n .I1(mpr_valid_r2),\n .O(samp_edge_cnt0_r0));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt0_r[0]_i_4 \n (.I0(samp_edge_cnt0_r_reg[3]),\n .O(\\samp_edge_cnt0_r[0]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt0_r[0]_i_5 \n (.I0(samp_edge_cnt0_r_reg[2]),\n .O(\\samp_edge_cnt0_r[0]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt0_r[0]_i_6 \n (.I0(samp_edge_cnt0_r_reg[1]),\n .O(\\samp_edge_cnt0_r[0]_i_6_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\samp_edge_cnt0_r[0]_i_7 \n (.I0(samp_edge_cnt0_r_reg[0]),\n .O(\\samp_edge_cnt0_r[0]_i_7_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt0_r[4]_i_2 \n (.I0(samp_edge_cnt0_r_reg[7]),\n .O(\\samp_edge_cnt0_r[4]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt0_r[4]_i_3 \n (.I0(samp_edge_cnt0_r_reg[6]),\n .O(\\samp_edge_cnt0_r[4]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt0_r[4]_i_4 \n (.I0(samp_edge_cnt0_r_reg[5]),\n .O(\\samp_edge_cnt0_r[4]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt0_r[4]_i_5 \n (.I0(samp_edge_cnt0_r_reg[4]),\n .O(\\samp_edge_cnt0_r[4]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt0_r[8]_i_2 \n (.I0(samp_edge_cnt0_r_reg[11]),\n .O(\\samp_edge_cnt0_r[8]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt0_r[8]_i_3 \n (.I0(samp_edge_cnt0_r_reg[10]),\n .O(\\samp_edge_cnt0_r[8]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt0_r[8]_i_4 \n (.I0(samp_edge_cnt0_r_reg[9]),\n .O(\\samp_edge_cnt0_r[8]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt0_r[8]_i_5 \n (.I0(samp_edge_cnt0_r_reg[8]),\n .O(\\samp_edge_cnt0_r[8]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\samp_edge_cnt0_r_reg[0] \n (.C(CLK),\n .CE(samp_edge_cnt0_r0),\n .D(\\samp_edge_cnt0_r_reg[0]_i_3_n_7 ),\n .Q(samp_edge_cnt0_r_reg[0]),\n .R(samp_edge_cnt0_en_r_reg_0));\n CARRY4 \\samp_edge_cnt0_r_reg[0]_i_3 \n (.CI(1'b0),\n .CO({\\samp_edge_cnt0_r_reg[0]_i_3_n_0 ,\\samp_edge_cnt0_r_reg[0]_i_3_n_1 ,\\samp_edge_cnt0_r_reg[0]_i_3_n_2 ,\\samp_edge_cnt0_r_reg[0]_i_3_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b1}),\n .O({\\samp_edge_cnt0_r_reg[0]_i_3_n_4 ,\\samp_edge_cnt0_r_reg[0]_i_3_n_5 ,\\samp_edge_cnt0_r_reg[0]_i_3_n_6 ,\\samp_edge_cnt0_r_reg[0]_i_3_n_7 }),\n .S({\\samp_edge_cnt0_r[0]_i_4_n_0 ,\\samp_edge_cnt0_r[0]_i_5_n_0 ,\\samp_edge_cnt0_r[0]_i_6_n_0 ,\\samp_edge_cnt0_r[0]_i_7_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\samp_edge_cnt0_r_reg[10] \n (.C(CLK),\n .CE(samp_edge_cnt0_r0),\n .D(\\samp_edge_cnt0_r_reg[8]_i_1_n_5 ),\n .Q(samp_edge_cnt0_r_reg[10]),\n .R(samp_edge_cnt0_en_r_reg_0));\n FDRE #(\n .INIT(1'b0)) \n \\samp_edge_cnt0_r_reg[11] \n (.C(CLK),\n .CE(samp_edge_cnt0_r0),\n .D(\\samp_edge_cnt0_r_reg[8]_i_1_n_4 ),\n .Q(samp_edge_cnt0_r_reg[11]),\n .R(samp_edge_cnt0_en_r_reg_0));\n FDRE #(\n .INIT(1'b0)) \n \\samp_edge_cnt0_r_reg[1] \n (.C(CLK),\n .CE(samp_edge_cnt0_r0),\n .D(\\samp_edge_cnt0_r_reg[0]_i_3_n_6 ),\n .Q(samp_edge_cnt0_r_reg[1]),\n .R(samp_edge_cnt0_en_r_reg_0));\n FDRE #(\n .INIT(1'b0)) \n \\samp_edge_cnt0_r_reg[2] \n (.C(CLK),\n .CE(samp_edge_cnt0_r0),\n .D(\\samp_edge_cnt0_r_reg[0]_i_3_n_5 ),\n .Q(samp_edge_cnt0_r_reg[2]),\n .R(samp_edge_cnt0_en_r_reg_0));\n FDRE #(\n .INIT(1'b0)) \n \\samp_edge_cnt0_r_reg[3] \n (.C(CLK),\n .CE(samp_edge_cnt0_r0),\n .D(\\samp_edge_cnt0_r_reg[0]_i_3_n_4 ),\n .Q(samp_edge_cnt0_r_reg[3]),\n .R(samp_edge_cnt0_en_r_reg_0));\n FDRE #(\n .INIT(1'b0)) \n \\samp_edge_cnt0_r_reg[4] \n (.C(CLK),\n .CE(samp_edge_cnt0_r0),\n .D(\\samp_edge_cnt0_r_reg[4]_i_1_n_7 ),\n .Q(samp_edge_cnt0_r_reg[4]),\n .R(samp_edge_cnt0_en_r_reg_0));\n CARRY4 \\samp_edge_cnt0_r_reg[4]_i_1 \n (.CI(\\samp_edge_cnt0_r_reg[0]_i_3_n_0 ),\n .CO({\\samp_edge_cnt0_r_reg[4]_i_1_n_0 ,\\samp_edge_cnt0_r_reg[4]_i_1_n_1 ,\\samp_edge_cnt0_r_reg[4]_i_1_n_2 ,\\samp_edge_cnt0_r_reg[4]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\samp_edge_cnt0_r_reg[4]_i_1_n_4 ,\\samp_edge_cnt0_r_reg[4]_i_1_n_5 ,\\samp_edge_cnt0_r_reg[4]_i_1_n_6 ,\\samp_edge_cnt0_r_reg[4]_i_1_n_7 }),\n .S({\\samp_edge_cnt0_r[4]_i_2_n_0 ,\\samp_edge_cnt0_r[4]_i_3_n_0 ,\\samp_edge_cnt0_r[4]_i_4_n_0 ,\\samp_edge_cnt0_r[4]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\samp_edge_cnt0_r_reg[5] \n (.C(CLK),\n .CE(samp_edge_cnt0_r0),\n .D(\\samp_edge_cnt0_r_reg[4]_i_1_n_6 ),\n .Q(samp_edge_cnt0_r_reg[5]),\n .R(samp_edge_cnt0_en_r_reg_0));\n FDRE #(\n .INIT(1'b0)) \n \\samp_edge_cnt0_r_reg[6] \n (.C(CLK),\n .CE(samp_edge_cnt0_r0),\n .D(\\samp_edge_cnt0_r_reg[4]_i_1_n_5 ),\n .Q(samp_edge_cnt0_r_reg[6]),\n .R(samp_edge_cnt0_en_r_reg_0));\n FDRE #(\n .INIT(1'b0)) \n \\samp_edge_cnt0_r_reg[7] \n (.C(CLK),\n .CE(samp_edge_cnt0_r0),\n .D(\\samp_edge_cnt0_r_reg[4]_i_1_n_4 ),\n .Q(samp_edge_cnt0_r_reg[7]),\n .R(samp_edge_cnt0_en_r_reg_0));\n FDRE #(\n .INIT(1'b0)) \n \\samp_edge_cnt0_r_reg[8] \n (.C(CLK),\n .CE(samp_edge_cnt0_r0),\n .D(\\samp_edge_cnt0_r_reg[8]_i_1_n_7 ),\n .Q(samp_edge_cnt0_r_reg[8]),\n .R(samp_edge_cnt0_en_r_reg_0));\n CARRY4 \\samp_edge_cnt0_r_reg[8]_i_1 \n (.CI(\\samp_edge_cnt0_r_reg[4]_i_1_n_0 ),\n .CO({\\NLW_samp_edge_cnt0_r_reg[8]_i_1_CO_UNCONNECTED [3],\\samp_edge_cnt0_r_reg[8]_i_1_n_1 ,\\samp_edge_cnt0_r_reg[8]_i_1_n_2 ,\\samp_edge_cnt0_r_reg[8]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\samp_edge_cnt0_r_reg[8]_i_1_n_4 ,\\samp_edge_cnt0_r_reg[8]_i_1_n_5 ,\\samp_edge_cnt0_r_reg[8]_i_1_n_6 ,\\samp_edge_cnt0_r_reg[8]_i_1_n_7 }),\n .S({\\samp_edge_cnt0_r[8]_i_2_n_0 ,\\samp_edge_cnt0_r[8]_i_3_n_0 ,\\samp_edge_cnt0_r[8]_i_4_n_0 ,\\samp_edge_cnt0_r[8]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\samp_edge_cnt0_r_reg[9] \n (.C(CLK),\n .CE(samp_edge_cnt0_r0),\n .D(\\samp_edge_cnt0_r_reg[8]_i_1_n_6 ),\n .Q(samp_edge_cnt0_r_reg[9]),\n .R(samp_edge_cnt0_en_r_reg_0));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n samp_edge_cnt1_en_r_i_1\n (.I0(samp_edge_cnt1_en_r_i_2_n_0),\n .I1(samp_edge_cnt1_en_r_i_3_n_0),\n .I2(samp_edge_cnt0_r_reg[8]),\n .I3(samp_edge_cnt0_r_reg[7]),\n .I4(samp_edge_cnt0_r_reg[6]),\n .I5(samp_edge_cnt0_r_reg[2]),\n .O(samp_edge_cnt1_en_r0));\n LUT6 #(\n .INIT(64'h0000000000000E00)) \n samp_edge_cnt1_en_r_i_2\n (.I0(sr_valid_r2),\n .I1(mpr_valid_r2),\n .I2(samp_edge_cnt0_r_reg[3]),\n .I3(samp_edge_cnt0_r_reg[0]),\n .I4(samp_edge_cnt0_r_reg[5]),\n .I5(samp_edge_cnt0_r_reg[1]),\n .O(samp_edge_cnt1_en_r_i_2_n_0));\n LUT4 #(\n .INIT(16'hFFFE)) \n samp_edge_cnt1_en_r_i_3\n (.I0(samp_edge_cnt0_r_reg[11]),\n .I1(samp_edge_cnt0_r_reg[4]),\n .I2(samp_edge_cnt0_r_reg[10]),\n .I3(samp_edge_cnt0_r_reg[9]),\n .O(samp_edge_cnt1_en_r_i_3_n_0));\n FDRE #(\n .INIT(1'b0)) \n samp_edge_cnt1_en_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(samp_edge_cnt1_en_r0),\n .Q(samp_edge_cnt1_en_r),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt1_r[0]_i_2 \n (.I0(samp_edge_cnt1_r_reg[3]),\n .O(\\samp_edge_cnt1_r[0]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt1_r[0]_i_3 \n (.I0(samp_edge_cnt1_r_reg[2]),\n .O(\\samp_edge_cnt1_r[0]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt1_r[0]_i_4 \n (.I0(samp_edge_cnt1_r_reg[1]),\n .O(\\samp_edge_cnt1_r[0]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\samp_edge_cnt1_r[0]_i_5 \n (.I0(samp_edge_cnt1_r_reg[0]),\n .O(\\samp_edge_cnt1_r[0]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt1_r[4]_i_2 \n (.I0(samp_edge_cnt1_r_reg[7]),\n .O(\\samp_edge_cnt1_r[4]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt1_r[4]_i_3 \n (.I0(samp_edge_cnt1_r_reg[6]),\n .O(\\samp_edge_cnt1_r[4]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt1_r[4]_i_4 \n (.I0(samp_edge_cnt1_r_reg[5]),\n .O(\\samp_edge_cnt1_r[4]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt1_r[4]_i_5 \n (.I0(samp_edge_cnt1_r_reg[4]),\n .O(\\samp_edge_cnt1_r[4]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt1_r[8]_i_2 \n (.I0(samp_edge_cnt1_r_reg[11]),\n .O(\\samp_edge_cnt1_r[8]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt1_r[8]_i_3 \n (.I0(samp_edge_cnt1_r_reg[10]),\n .O(\\samp_edge_cnt1_r[8]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt1_r[8]_i_4 \n (.I0(samp_edge_cnt1_r_reg[9]),\n .O(\\samp_edge_cnt1_r[8]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt1_r[8]_i_5 \n (.I0(samp_edge_cnt1_r_reg[8]),\n .O(\\samp_edge_cnt1_r[8]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\samp_edge_cnt1_r_reg[0] \n (.C(CLK),\n .CE(samp_edge_cnt1_en_r),\n .D(\\samp_edge_cnt1_r_reg[0]_i_1_n_7 ),\n .Q(samp_edge_cnt1_r_reg[0]),\n .R(samp_edge_cnt0_en_r_reg_0));\n CARRY4 \\samp_edge_cnt1_r_reg[0]_i_1 \n (.CI(1'b0),\n .CO({\\samp_edge_cnt1_r_reg[0]_i_1_n_0 ,\\samp_edge_cnt1_r_reg[0]_i_1_n_1 ,\\samp_edge_cnt1_r_reg[0]_i_1_n_2 ,\\samp_edge_cnt1_r_reg[0]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b1}),\n .O({\\samp_edge_cnt1_r_reg[0]_i_1_n_4 ,\\samp_edge_cnt1_r_reg[0]_i_1_n_5 ,\\samp_edge_cnt1_r_reg[0]_i_1_n_6 ,\\samp_edge_cnt1_r_reg[0]_i_1_n_7 }),\n .S({\\samp_edge_cnt1_r[0]_i_2_n_0 ,\\samp_edge_cnt1_r[0]_i_3_n_0 ,\\samp_edge_cnt1_r[0]_i_4_n_0 ,\\samp_edge_cnt1_r[0]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\samp_edge_cnt1_r_reg[10] \n (.C(CLK),\n .CE(samp_edge_cnt1_en_r),\n .D(\\samp_edge_cnt1_r_reg[8]_i_1_n_5 ),\n .Q(samp_edge_cnt1_r_reg[10]),\n .R(samp_edge_cnt0_en_r_reg_0));\n FDRE #(\n .INIT(1'b0)) \n \\samp_edge_cnt1_r_reg[11] \n (.C(CLK),\n .CE(samp_edge_cnt1_en_r),\n .D(\\samp_edge_cnt1_r_reg[8]_i_1_n_4 ),\n .Q(samp_edge_cnt1_r_reg[11]),\n .R(samp_edge_cnt0_en_r_reg_0));\n FDRE #(\n .INIT(1'b0)) \n \\samp_edge_cnt1_r_reg[1] \n (.C(CLK),\n .CE(samp_edge_cnt1_en_r),\n .D(\\samp_edge_cnt1_r_reg[0]_i_1_n_6 ),\n .Q(samp_edge_cnt1_r_reg[1]),\n .R(samp_edge_cnt0_en_r_reg_0));\n FDRE #(\n .INIT(1'b0)) \n \\samp_edge_cnt1_r_reg[2] \n (.C(CLK),\n .CE(samp_edge_cnt1_en_r),\n .D(\\samp_edge_cnt1_r_reg[0]_i_1_n_5 ),\n .Q(samp_edge_cnt1_r_reg[2]),\n .R(samp_edge_cnt0_en_r_reg_0));\n FDRE #(\n .INIT(1'b0)) \n \\samp_edge_cnt1_r_reg[3] \n (.C(CLK),\n .CE(samp_edge_cnt1_en_r),\n .D(\\samp_edge_cnt1_r_reg[0]_i_1_n_4 ),\n .Q(samp_edge_cnt1_r_reg[3]),\n .R(samp_edge_cnt0_en_r_reg_0));\n FDRE #(\n .INIT(1'b0)) \n \\samp_edge_cnt1_r_reg[4] \n (.C(CLK),\n .CE(samp_edge_cnt1_en_r),\n .D(\\samp_edge_cnt1_r_reg[4]_i_1_n_7 ),\n .Q(samp_edge_cnt1_r_reg[4]),\n .R(samp_edge_cnt0_en_r_reg_0));\n CARRY4 \\samp_edge_cnt1_r_reg[4]_i_1 \n (.CI(\\samp_edge_cnt1_r_reg[0]_i_1_n_0 ),\n .CO({\\samp_edge_cnt1_r_reg[4]_i_1_n_0 ,\\samp_edge_cnt1_r_reg[4]_i_1_n_1 ,\\samp_edge_cnt1_r_reg[4]_i_1_n_2 ,\\samp_edge_cnt1_r_reg[4]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\samp_edge_cnt1_r_reg[4]_i_1_n_4 ,\\samp_edge_cnt1_r_reg[4]_i_1_n_5 ,\\samp_edge_cnt1_r_reg[4]_i_1_n_6 ,\\samp_edge_cnt1_r_reg[4]_i_1_n_7 }),\n .S({\\samp_edge_cnt1_r[4]_i_2_n_0 ,\\samp_edge_cnt1_r[4]_i_3_n_0 ,\\samp_edge_cnt1_r[4]_i_4_n_0 ,\\samp_edge_cnt1_r[4]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\samp_edge_cnt1_r_reg[5] \n (.C(CLK),\n .CE(samp_edge_cnt1_en_r),\n .D(\\samp_edge_cnt1_r_reg[4]_i_1_n_6 ),\n .Q(samp_edge_cnt1_r_reg[5]),\n .R(samp_edge_cnt0_en_r_reg_0));\n FDRE #(\n .INIT(1'b0)) \n \\samp_edge_cnt1_r_reg[6] \n (.C(CLK),\n .CE(samp_edge_cnt1_en_r),\n .D(\\samp_edge_cnt1_r_reg[4]_i_1_n_5 ),\n .Q(samp_edge_cnt1_r_reg[6]),\n .R(samp_edge_cnt0_en_r_reg_0));\n FDRE #(\n .INIT(1'b0)) \n \\samp_edge_cnt1_r_reg[7] \n (.C(CLK),\n .CE(samp_edge_cnt1_en_r),\n .D(\\samp_edge_cnt1_r_reg[4]_i_1_n_4 ),\n .Q(samp_edge_cnt1_r_reg[7]),\n .R(samp_edge_cnt0_en_r_reg_0));\n FDRE #(\n .INIT(1'b0)) \n \\samp_edge_cnt1_r_reg[8] \n (.C(CLK),\n .CE(samp_edge_cnt1_en_r),\n .D(\\samp_edge_cnt1_r_reg[8]_i_1_n_7 ),\n .Q(samp_edge_cnt1_r_reg[8]),\n .R(samp_edge_cnt0_en_r_reg_0));\n CARRY4 \\samp_edge_cnt1_r_reg[8]_i_1 \n (.CI(\\samp_edge_cnt1_r_reg[4]_i_1_n_0 ),\n .CO({\\NLW_samp_edge_cnt1_r_reg[8]_i_1_CO_UNCONNECTED [3],\\samp_edge_cnt1_r_reg[8]_i_1_n_1 ,\\samp_edge_cnt1_r_reg[8]_i_1_n_2 ,\\samp_edge_cnt1_r_reg[8]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\samp_edge_cnt1_r_reg[8]_i_1_n_4 ,\\samp_edge_cnt1_r_reg[8]_i_1_n_5 ,\\samp_edge_cnt1_r_reg[8]_i_1_n_6 ,\\samp_edge_cnt1_r_reg[8]_i_1_n_7 }),\n .S({\\samp_edge_cnt1_r[8]_i_2_n_0 ,\\samp_edge_cnt1_r[8]_i_3_n_0 ,\\samp_edge_cnt1_r[8]_i_4_n_0 ,\\samp_edge_cnt1_r[8]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\samp_edge_cnt1_r_reg[9] \n (.C(CLK),\n .CE(samp_edge_cnt1_en_r),\n .D(\\samp_edge_cnt1_r_reg[8]_i_1_n_6 ),\n .Q(samp_edge_cnt1_r_reg[9]),\n .R(samp_edge_cnt0_en_r_reg_0));\n LUT1 #(\n .INIT(2'h1)) \n \\second_edge_taps_r[0]_i_1 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .O(\\second_edge_taps_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair229\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\second_edge_taps_r[1]_i_1 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .I1(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .O(\\second_edge_taps_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair229\" *) \n LUT3 #(\n .INIT(8'hA9)) \n \\second_edge_taps_r[2]_i_1 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .I1(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .O(\\second_edge_taps_r[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair188\" *) \n LUT4 #(\n .INIT(16'hAAA9)) \n \\second_edge_taps_r[3]_i_1 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .I1(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .I3(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .O(\\second_edge_taps_r[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair188\" *) \n LUT5 #(\n .INIT(32'hAAAAAAA9)) \n \\second_edge_taps_r[4]_i_1 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[4] ),\n .I1(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .I3(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .I4(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .O(\\second_edge_taps_r[4]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\second_edge_taps_r[5]_i_1 \n (.I0(out[3]),\n .I1(\\second_edge_taps_r_reg[5]_0 ),\n .O(\\second_edge_taps_r[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8888888820000000)) \n \\second_edge_taps_r[5]_i_2 \n (.I0(\\right_edge_taps_r_reg[0]_1 ),\n .I1(out[3]),\n .I2(\\right_edge_taps_r_reg[0]_2 ),\n .I3(found_stable_eye_last_r),\n .I4(\\right_edge_taps_r_reg[0]_0 ),\n .I5(out[2]),\n .O(\\second_edge_taps_r_reg[5]_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAAAAA9)) \n \\second_edge_taps_r[5]_i_3 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[5] ),\n .I1(\\tap_cnt_cpt_r_reg_n_0_[4] ),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .I3(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .I4(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .I5(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .O(\\second_edge_taps_r[5]_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\second_edge_taps_r_reg[0] \n (.C(CLK),\n .CE(\\second_edge_taps_r_reg[5]_0 ),\n .D(\\second_edge_taps_r[0]_i_1_n_0 ),\n .Q(\\second_edge_taps_r_reg_n_0_[0] ),\n .R(\\second_edge_taps_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\second_edge_taps_r_reg[1] \n (.C(CLK),\n .CE(\\second_edge_taps_r_reg[5]_0 ),\n .D(\\second_edge_taps_r[1]_i_1_n_0 ),\n .Q(\\second_edge_taps_r_reg_n_0_[1] ),\n .R(\\second_edge_taps_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\second_edge_taps_r_reg[2] \n (.C(CLK),\n .CE(\\second_edge_taps_r_reg[5]_0 ),\n .D(\\second_edge_taps_r[2]_i_1_n_0 ),\n .Q(\\second_edge_taps_r_reg_n_0_[2] ),\n .R(\\second_edge_taps_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\second_edge_taps_r_reg[3] \n (.C(CLK),\n .CE(\\second_edge_taps_r_reg[5]_0 ),\n .D(\\second_edge_taps_r[3]_i_1_n_0 ),\n .Q(\\second_edge_taps_r_reg_n_0_[3] ),\n .R(\\second_edge_taps_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\second_edge_taps_r_reg[4] \n (.C(CLK),\n .CE(\\second_edge_taps_r_reg[5]_0 ),\n .D(\\second_edge_taps_r[4]_i_1_n_0 ),\n .Q(\\second_edge_taps_r_reg_n_0_[4] ),\n .R(\\second_edge_taps_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\second_edge_taps_r_reg[5] \n (.C(CLK),\n .CE(\\second_edge_taps_r_reg[5]_0 ),\n .D(\\second_edge_taps_r[5]_i_3_n_0 ),\n .Q(\\second_edge_taps_r_reg_n_0_[5] ),\n .R(\\second_edge_taps_r[5]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n sr_valid_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(sr_valid_r1_reg_0),\n .Q(sr_valid_r1),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n sr_valid_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(sr_valid_r1),\n .Q(sr_valid_r2),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair198\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n sr_valid_r_i_2\n (.I0(cnt_shift_r_reg__0[0]),\n .I1(cnt_shift_r_reg__0[1]),\n .I2(cnt_shift_r_reg__0[3]),\n .I3(cnt_shift_r_reg__0[2]),\n .O(mpr_valid_r_reg_0));\n FDRE #(\n .INIT(1'b0)) \n sr_valid_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(sr_valid_r108_out),\n .Q(sr_valid_r1_reg_0),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair224\" *) \n LUT3 #(\n .INIT(8'h45)) \n \\stg1_wr_rd_cnt[4]_i_2 \n (.I0(rstdiv0_sync_r1_reg_rep__23),\n .I1(rdlvl_stg1_done_r1_reg),\n .I2(stg1_wr_done),\n .O(\\stg1_wr_rd_cnt_reg[3] ));\n FDRE #(\n .INIT(1'b0)) \n store_sr_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(store_sr_req_r_reg_1),\n .Q(\\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0]_0 ),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n LUT6 #(\n .INIT(64'h0000100000000000)) \n store_sr_req_pulsed_r_i_1\n (.I0(cal1_state_r),\n .I1(out[2]),\n .I2(out[1]),\n .I3(out[0]),\n .I4(out[3]),\n .I5(out[4]),\n .O(store_sr_req_pulsed_r));\n FDRE #(\n .INIT(1'b0)) \n store_sr_req_pulsed_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(store_sr_req_pulsed_r),\n .Q(store_sr_req_pulsed_r_reg_n_0),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n LUT6 #(\n .INIT(64'h0000000288880002)) \n store_sr_req_r_i_1\n (.I0(store_sr_req_r_i_2_n_0),\n .I1(out[4]),\n .I2(cal1_wait_r),\n .I3(store_sr_req_r_reg_0),\n .I4(out[0]),\n .I5(store_sr_req_pulsed_r_reg_n_0),\n .O(store_sr_req_r));\n LUT4 #(\n .INIT(16'h0010)) \n store_sr_req_r_i_2\n (.I0(cal1_state_r),\n .I1(out[3]),\n .I2(out[1]),\n .I3(out[2]),\n .O(store_sr_req_r_i_2_n_0));\n FDRE #(\n .INIT(1'b0)) \n store_sr_req_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(store_sr_req_r),\n .Q(store_sr_r_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n (* SOFT_HLUTNM = \"soft_lutpair207\" *) \n LUT3 #(\n .INIT(8'h69)) \n \\tap_cnt_cpt_r[1]_i_1 \n (.I0(cal1_dlyinc_cpt_r_reg_n_0),\n .I1(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .O(\\tap_cnt_cpt_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair189\" *) \n LUT4 #(\n .INIT(16'h6CC9)) \n \\tap_cnt_cpt_r[2]_i_1 \n (.I0(cal1_dlyinc_cpt_r_reg_n_0),\n .I1(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .I3(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .O(p_0_in__0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair189\" *) \n LUT5 #(\n .INIT(32'h6CCCCCC9)) \n \\tap_cnt_cpt_r[3]_i_1 \n (.I0(cal1_dlyinc_cpt_r_reg_n_0),\n .I1(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .I3(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .I4(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .O(p_0_in__0[3]));\n LUT6 #(\n .INIT(64'h6CCCCCCCCCCCCCC9)) \n \\tap_cnt_cpt_r[4]_i_1 \n (.I0(cal1_dlyinc_cpt_r_reg_n_0),\n .I1(\\tap_cnt_cpt_r_reg_n_0_[4] ),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .I3(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .I4(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .I5(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .O(p_0_in__0[4]));\n LUT4 #(\n .INIT(16'hFFF4)) \n \\tap_cnt_cpt_r[5]_i_1 \n (.I0(mpr_rdlvl_done_r2),\n .I1(mpr_rdlvl_done_r1),\n .I2(new_cnt_cpt_r_reg_n_0),\n .I3(rstdiv0_sync_r1_reg_rep__22),\n .O(tap_cnt_cpt_r0));\n LUT4 #(\n .INIT(16'hAA8A)) \n \\tap_cnt_cpt_r[5]_i_2 \n (.I0(cal1_dlyce_cpt_r_reg_n_0),\n .I1(\\tap_cnt_cpt_r_reg_n_0_[5] ),\n .I2(\\tap_cnt_cpt_r[5]_i_4_n_0 ),\n .I3(cal1_dlyinc_cpt_r_reg_n_0),\n .O(tap_cnt_cpt_r));\n LUT4 #(\n .INIT(16'h6F60)) \n \\tap_cnt_cpt_r[5]_i_3 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[5] ),\n .I1(tap_limit_cpt_r_i_2_n_0),\n .I2(cal1_dlyinc_cpt_r_reg_n_0),\n .I3(\\second_edge_taps_r[5]_i_3_n_0 ),\n .O(p_0_in__0[5]));\n (* SOFT_HLUTNM = \"soft_lutpair90\" *) \n LUT5 #(\n .INIT(32'h00000001)) \n \\tap_cnt_cpt_r[5]_i_4 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .I1(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .I3(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .I4(\\tap_cnt_cpt_r_reg_n_0_[4] ),\n .O(\\tap_cnt_cpt_r[5]_i_4_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\tap_cnt_cpt_r_reg[0] \n (.C(CLK),\n .CE(tap_cnt_cpt_r),\n .D(\\second_edge_taps_r[0]_i_1_n_0 ),\n .Q(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .R(tap_cnt_cpt_r0));\n FDRE #(\n .INIT(1'b0)) \n \\tap_cnt_cpt_r_reg[1] \n (.C(CLK),\n .CE(tap_cnt_cpt_r),\n .D(\\tap_cnt_cpt_r[1]_i_1_n_0 ),\n .Q(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .R(tap_cnt_cpt_r0));\n FDRE #(\n .INIT(1'b0)) \n \\tap_cnt_cpt_r_reg[2] \n (.C(CLK),\n .CE(tap_cnt_cpt_r),\n .D(p_0_in__0[2]),\n .Q(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .R(tap_cnt_cpt_r0));\n FDRE #(\n .INIT(1'b0)) \n \\tap_cnt_cpt_r_reg[3] \n (.C(CLK),\n .CE(tap_cnt_cpt_r),\n .D(p_0_in__0[3]),\n .Q(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .R(tap_cnt_cpt_r0));\n FDRE #(\n .INIT(1'b0)) \n \\tap_cnt_cpt_r_reg[4] \n (.C(CLK),\n .CE(tap_cnt_cpt_r),\n .D(p_0_in__0[4]),\n .Q(\\tap_cnt_cpt_r_reg_n_0_[4] ),\n .R(tap_cnt_cpt_r0));\n FDRE #(\n .INIT(1'b0)) \n \\tap_cnt_cpt_r_reg[5] \n (.C(CLK),\n .CE(tap_cnt_cpt_r),\n .D(p_0_in__0[5]),\n .Q(\\tap_cnt_cpt_r_reg_n_0_[5] ),\n .R(tap_cnt_cpt_r0));\n LUT5 #(\n .INIT(32'h000000EA)) \n tap_limit_cpt_r_i_1\n (.I0(tap_limit_cpt_r),\n .I1(tap_limit_cpt_r_i_2_n_0),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[5] ),\n .I3(tap_limit_cpt_r_i_3_n_0),\n .I4(tap_cnt_cpt_r0),\n .O(tap_limit_cpt_r_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair90\" *) \n LUT5 #(\n .INIT(32'h80000000)) \n tap_limit_cpt_r_i_2\n (.I0(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .I1(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .I3(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .I4(\\tap_cnt_cpt_r_reg_n_0_[4] ),\n .O(tap_limit_cpt_r_i_2_n_0));\n LUT6 #(\n .INIT(64'h0000000000000010)) \n tap_limit_cpt_r_i_3\n (.I0(\\cal1_state_r1_reg_n_0_[5] ),\n .I1(\\cal1_state_r1_reg_n_0_[4] ),\n .I2(\\cal1_state_r1_reg_n_0_[2] ),\n .I3(\\cal1_state_r1_reg_n_0_[0] ),\n .I4(\\cal1_state_r1_reg_n_0_[3] ),\n .I5(\\cal1_state_r1_reg_n_0_[1] ),\n .O(tap_limit_cpt_r_i_3_n_0));\n FDRE #(\n .INIT(1'b0)) \n tap_limit_cpt_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(tap_limit_cpt_r_i_1_n_0),\n .Q(tap_limit_cpt_r),\n .R(1'b0));\n LUT1 #(\n .INIT(2'h1)) \n \\wait_cnt_r[0]_i_1__1 \n (.I0(\\wait_cnt_r_reg[0]_0 [0]),\n .O(wait_cnt_r0__0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair235\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\wait_cnt_r[1]_i_1__1 \n (.I0(\\wait_cnt_r_reg[0]_0 [1]),\n .I1(\\wait_cnt_r_reg[0]_0 [0]),\n .O(\\wait_cnt_r[1]_i_1__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair235\" *) \n LUT3 #(\n .INIT(8'hA9)) \n \\wait_cnt_r[2]_i_1__0 \n (.I0(wait_cnt_r_reg__0[2]),\n .I1(\\wait_cnt_r_reg[0]_0 [0]),\n .I2(\\wait_cnt_r_reg[0]_0 [1]),\n .O(wait_cnt_r0__0[2]));\n LUT5 #(\n .INIT(32'hAAAAAAA8)) \n \\wait_cnt_r[3]_i_2__1 \n (.I0(dqs_po_dec_done_r2),\n .I1(wait_cnt_r_reg__0[2]),\n .I2(wait_cnt_r_reg__0[3]),\n .I3(\\wait_cnt_r_reg[0]_0 [1]),\n .I4(\\wait_cnt_r_reg[0]_0 [0]),\n .O(wait_cnt_r0));\n (* SOFT_HLUTNM = \"soft_lutpair208\" *) \n LUT4 #(\n .INIT(16'hAAA9)) \n \\wait_cnt_r[3]_i_3 \n (.I0(wait_cnt_r_reg__0[3]),\n .I1(wait_cnt_r_reg__0[2]),\n .I2(\\wait_cnt_r_reg[0]_0 [1]),\n .I3(\\wait_cnt_r_reg[0]_0 [0]),\n .O(wait_cnt_r0__0[3]));\n FDRE #(\n .INIT(1'b0)) \n \\wait_cnt_r_reg[0] \n (.C(CLK),\n .CE(wait_cnt_r0),\n .D(wait_cnt_r0__0[0]),\n .Q(\\wait_cnt_r_reg[0]_0 [0]),\n .R(pi_cnt_dec_reg_1));\n FDRE #(\n .INIT(1'b0)) \n \\wait_cnt_r_reg[1] \n (.C(CLK),\n .CE(wait_cnt_r0),\n .D(\\wait_cnt_r[1]_i_1__1_n_0 ),\n .Q(\\wait_cnt_r_reg[0]_0 [1]),\n .R(pi_cnt_dec_reg_1));\n FDRE #(\n .INIT(1'b0)) \n \\wait_cnt_r_reg[2] \n (.C(CLK),\n .CE(wait_cnt_r0),\n .D(wait_cnt_r0__0[2]),\n .Q(wait_cnt_r_reg__0[2]),\n .R(pi_cnt_dec_reg_1));\n FDSE #(\n .INIT(1'b1)) \n \\wait_cnt_r_reg[3] \n (.C(CLK),\n .CE(wait_cnt_r0),\n .D(wait_cnt_r0__0[3]),\n .Q(wait_cnt_r_reg__0[3]),\n .S(pi_cnt_dec_reg_1));\n (* SOFT_HLUTNM = \"soft_lutpair197\" *) \n LUT4 #(\n .INIT(16'h7FFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[254]_i_1 \n (.I0(rdlvl_stg1_done_r1_reg),\n .I1(prbs_rdlvl_done_reg_rep),\n .I2(oclkdelay_calib_done_r_reg),\n .I3(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[254] ));\n LUT5 #(\n .INIT(32'hDFDF0FFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[56]_i_1 \n (.I0(rdlvl_stg1_done_r1_reg),\n .I1(\\dout_o_reg[6]_0 ),\n .I2(oclkdelay_calib_done_r_reg),\n .I3(first_wrcal_pat_r),\n .I4(wrcal_done_reg),\n .O(D[0]));\n LUT5 #(\n .INIT(32'hDFDF0FFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[60]_i_1 \n (.I0(rdlvl_stg1_done_r1_reg),\n .I1(\\dout_o_reg[6] ),\n .I2(oclkdelay_calib_done_r_reg),\n .I3(first_wrcal_pat_r),\n .I4(wrcal_done_reg),\n .O(D[1]));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_phy_tempmon\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_phy_tempmon\n (tempmon_pi_f_inc,\n tempmon_sel_pi_incdec,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ,\n D,\n \\calib_zero_inputs_reg[1] ,\n \\calib_zero_inputs_reg[1]_0 ,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n CLK,\n SS,\n tempmon_sample_en,\n rstdiv0_sync_r1_reg_rep__2,\n rstdiv0_sync_r1_reg_rep__6,\n oclkdelay_calib_done_r_reg,\n ck_addr_cmd_delay_done,\n ctl_lane_sel,\n rstdiv0_sync_r1_reg_rep__24,\n calib_complete,\n cmd_delay_start0,\n delay_done_r4_reg,\n calib_in_common,\n fine_adjust_done_r_reg,\n rd_data_offset_cal_done,\n rstdiv0_sync_r1_reg_rep__4,\n rstdiv0_sync_r1_reg_rep__5,\n \\device_temp_r_reg[11] ,\n rstdiv0_sync_r1_reg_rep__7);\n output tempmon_pi_f_inc;\n output tempmon_sel_pi_incdec;\n output \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ;\n output [0:0]D;\n output [0:0]\\calib_zero_inputs_reg[1] ;\n output \\calib_zero_inputs_reg[1]_0 ;\n output \\gen_byte_sel_div1.calib_in_common_reg ;\n input CLK;\n input [0:0]SS;\n input tempmon_sample_en;\n input rstdiv0_sync_r1_reg_rep__2;\n input rstdiv0_sync_r1_reg_rep__6;\n input oclkdelay_calib_done_r_reg;\n input ck_addr_cmd_delay_done;\n input ctl_lane_sel;\n input rstdiv0_sync_r1_reg_rep__24;\n input calib_complete;\n input cmd_delay_start0;\n input delay_done_r4_reg;\n input calib_in_common;\n input fine_adjust_done_r_reg;\n input rd_data_offset_cal_done;\n input [0:0]rstdiv0_sync_r1_reg_rep__4;\n input rstdiv0_sync_r1_reg_rep__5;\n input [11:0]\\device_temp_r_reg[11] ;\n input [0:0]rstdiv0_sync_r1_reg_rep__7;\n\n wire CLK;\n wire [0:0]D;\n wire [0:0]SS;\n wire calib_complete;\n wire calib_in_common;\n wire [0:0]\\calib_zero_inputs_reg[1] ;\n wire \\calib_zero_inputs_reg[1]_0 ;\n wire ck_addr_cmd_delay_done;\n wire cmd_delay_start0;\n wire ctl_lane_sel;\n wire delay_done_r4_reg;\n wire [11:0]device_temp_101;\n wire [11:0]device_temp_init;\n wire \\device_temp_init[11]_i_2_n_0 ;\n wire \\device_temp_init[11]_i_3_n_0 ;\n wire [11:0]\\device_temp_r_reg[11] ;\n wire fine_adjust_done_r_reg;\n wire [11:0]four_dec_min_limit;\n wire \\four_dec_min_limit[11]_i_2_n_0 ;\n wire \\four_dec_min_limit[11]_i_3_n_0 ;\n wire \\four_dec_min_limit[5]_i_2_n_0 ;\n wire \\four_dec_min_limit[5]_i_3_n_0 ;\n wire \\four_dec_min_limit[5]_i_4_n_0 ;\n wire \\four_dec_min_limit[5]_i_5_n_0 ;\n wire \\four_dec_min_limit[9]_i_2_n_0 ;\n wire \\four_dec_min_limit[9]_i_3_n_0 ;\n wire \\four_dec_min_limit[9]_i_4_n_0 ;\n wire \\four_dec_min_limit[9]_i_5_n_0 ;\n wire [11:2]four_dec_min_limit_nxt;\n wire \\four_dec_min_limit_reg[11]_i_1_n_3 ;\n wire \\four_dec_min_limit_reg[5]_i_1_n_0 ;\n wire \\four_dec_min_limit_reg[5]_i_1_n_1 ;\n wire \\four_dec_min_limit_reg[5]_i_1_n_2 ;\n wire \\four_dec_min_limit_reg[5]_i_1_n_3 ;\n wire \\four_dec_min_limit_reg[9]_i_1_n_0 ;\n wire \\four_dec_min_limit_reg[9]_i_1_n_1 ;\n wire \\four_dec_min_limit_reg[9]_i_1_n_2 ;\n wire \\four_dec_min_limit_reg[9]_i_1_n_3 ;\n wire [11:1]four_inc_max_limit;\n wire \\four_inc_max_limit[11]_i_2_n_0 ;\n wire \\four_inc_max_limit[11]_i_3_n_0 ;\n wire \\four_inc_max_limit[11]_i_4_n_0 ;\n wire \\four_inc_max_limit[1]_i_2_n_0 ;\n wire \\four_inc_max_limit[4]_i_2_n_0 ;\n wire \\four_inc_max_limit[4]_i_3_n_0 ;\n wire \\four_inc_max_limit[4]_i_4_n_0 ;\n wire \\four_inc_max_limit[4]_i_5_n_0 ;\n wire \\four_inc_max_limit[8]_i_2_n_0 ;\n wire \\four_inc_max_limit[8]_i_3_n_0 ;\n wire \\four_inc_max_limit[8]_i_4_n_0 ;\n wire \\four_inc_max_limit[8]_i_5_n_0 ;\n wire [11:1]four_inc_max_limit_nxt;\n wire \\four_inc_max_limit_reg[11]_i_1_n_2 ;\n wire \\four_inc_max_limit_reg[11]_i_1_n_3 ;\n wire \\four_inc_max_limit_reg[4]_i_1_n_0 ;\n wire \\four_inc_max_limit_reg[4]_i_1_n_1 ;\n wire \\four_inc_max_limit_reg[4]_i_1_n_2 ;\n wire \\four_inc_max_limit_reg[4]_i_1_n_3 ;\n wire \\four_inc_max_limit_reg[8]_i_1_n_0 ;\n wire \\four_inc_max_limit_reg[8]_i_1_n_1 ;\n wire \\four_inc_max_limit_reg[8]_i_1_n_2 ;\n wire \\four_inc_max_limit_reg[8]_i_1_n_3 ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire [11:1]neutral_max_limit;\n wire \\neutral_max_limit[11]_i_2_n_0 ;\n wire \\neutral_max_limit[11]_i_3_n_0 ;\n wire \\neutral_max_limit[11]_i_4_n_0 ;\n wire \\neutral_max_limit[4]_i_2_n_0 ;\n wire \\neutral_max_limit[4]_i_3_n_0 ;\n wire \\neutral_max_limit[4]_i_4_n_0 ;\n wire \\neutral_max_limit[4]_i_5_n_0 ;\n wire \\neutral_max_limit[8]_i_2_n_0 ;\n wire \\neutral_max_limit[8]_i_3_n_0 ;\n wire \\neutral_max_limit[8]_i_4_n_0 ;\n wire \\neutral_max_limit[8]_i_5_n_0 ;\n wire [11:1]neutral_max_limit_nxt;\n wire \\neutral_max_limit_reg[11]_i_1_n_2 ;\n wire \\neutral_max_limit_reg[11]_i_1_n_3 ;\n wire \\neutral_max_limit_reg[4]_i_1_n_0 ;\n wire \\neutral_max_limit_reg[4]_i_1_n_1 ;\n wire \\neutral_max_limit_reg[4]_i_1_n_2 ;\n wire \\neutral_max_limit_reg[4]_i_1_n_3 ;\n wire \\neutral_max_limit_reg[8]_i_1_n_0 ;\n wire \\neutral_max_limit_reg[8]_i_1_n_1 ;\n wire \\neutral_max_limit_reg[8]_i_1_n_2 ;\n wire \\neutral_max_limit_reg[8]_i_1_n_3 ;\n wire [11:1]neutral_min_limit;\n wire \\neutral_min_limit[11]_i_2_n_0 ;\n wire \\neutral_min_limit[11]_i_3_n_0 ;\n wire \\neutral_min_limit[5]_i_2_n_0 ;\n wire \\neutral_min_limit[5]_i_3_n_0 ;\n wire \\neutral_min_limit[5]_i_4_n_0 ;\n wire \\neutral_min_limit[5]_i_5_n_0 ;\n wire \\neutral_min_limit[9]_i_2_n_0 ;\n wire \\neutral_min_limit[9]_i_3_n_0 ;\n wire \\neutral_min_limit[9]_i_4_n_0 ;\n wire \\neutral_min_limit[9]_i_5_n_0 ;\n wire [11:2]neutral_min_limit_nxt;\n wire \\neutral_min_limit_reg[11]_i_1_n_3 ;\n wire \\neutral_min_limit_reg[5]_i_1_n_0 ;\n wire \\neutral_min_limit_reg[5]_i_1_n_1 ;\n wire \\neutral_min_limit_reg[5]_i_1_n_2 ;\n wire \\neutral_min_limit_reg[5]_i_1_n_3 ;\n wire \\neutral_min_limit_reg[9]_i_1_n_0 ;\n wire \\neutral_min_limit_reg[9]_i_1_n_1 ;\n wire \\neutral_min_limit_reg[9]_i_1_n_2 ;\n wire \\neutral_min_limit_reg[9]_i_1_n_3 ;\n wire oclkdelay_calib_done_r_reg;\n wire [11:1]one_dec_max_limit;\n wire \\one_dec_max_limit[11]_i_2_n_0 ;\n wire \\one_dec_max_limit[11]_i_3_n_0 ;\n wire \\one_dec_max_limit[11]_i_4_n_0 ;\n wire \\one_dec_max_limit[4]_i_2_n_0 ;\n wire \\one_dec_max_limit[4]_i_3_n_0 ;\n wire \\one_dec_max_limit[4]_i_4_n_0 ;\n wire \\one_dec_max_limit[4]_i_5_n_0 ;\n wire \\one_dec_max_limit[8]_i_2_n_0 ;\n wire \\one_dec_max_limit[8]_i_3_n_0 ;\n wire \\one_dec_max_limit[8]_i_4_n_0 ;\n wire \\one_dec_max_limit[8]_i_5_n_0 ;\n wire [11:1]one_dec_max_limit_nxt;\n wire \\one_dec_max_limit_reg[11]_i_1_n_2 ;\n wire \\one_dec_max_limit_reg[11]_i_1_n_3 ;\n wire \\one_dec_max_limit_reg[4]_i_1_n_0 ;\n wire \\one_dec_max_limit_reg[4]_i_1_n_1 ;\n wire \\one_dec_max_limit_reg[4]_i_1_n_2 ;\n wire \\one_dec_max_limit_reg[4]_i_1_n_3 ;\n wire \\one_dec_max_limit_reg[8]_i_1_n_0 ;\n wire \\one_dec_max_limit_reg[8]_i_1_n_1 ;\n wire \\one_dec_max_limit_reg[8]_i_1_n_2 ;\n wire \\one_dec_max_limit_reg[8]_i_1_n_3 ;\n wire [11:1]one_dec_min_limit;\n wire \\one_dec_min_limit[11]_i_2_n_0 ;\n wire \\one_dec_min_limit[11]_i_3_n_0 ;\n wire \\one_dec_min_limit[5]_i_2_n_0 ;\n wire \\one_dec_min_limit[5]_i_3_n_0 ;\n wire \\one_dec_min_limit[5]_i_4_n_0 ;\n wire \\one_dec_min_limit[5]_i_5_n_0 ;\n wire \\one_dec_min_limit[9]_i_2_n_0 ;\n wire \\one_dec_min_limit[9]_i_3_n_0 ;\n wire \\one_dec_min_limit[9]_i_4_n_0 ;\n wire \\one_dec_min_limit[9]_i_5_n_0 ;\n wire [11:2]one_dec_min_limit_nxt;\n wire \\one_dec_min_limit_reg[11]_i_1_n_3 ;\n wire \\one_dec_min_limit_reg[5]_i_1_n_0 ;\n wire \\one_dec_min_limit_reg[5]_i_1_n_1 ;\n wire \\one_dec_min_limit_reg[5]_i_1_n_2 ;\n wire \\one_dec_min_limit_reg[5]_i_1_n_3 ;\n wire \\one_dec_min_limit_reg[9]_i_1_n_0 ;\n wire \\one_dec_min_limit_reg[9]_i_1_n_1 ;\n wire \\one_dec_min_limit_reg[9]_i_1_n_2 ;\n wire \\one_dec_min_limit_reg[9]_i_1_n_3 ;\n wire [11:1]one_inc_max_limit;\n wire \\one_inc_max_limit[11]_i_2_n_0 ;\n wire \\one_inc_max_limit[11]_i_3_n_0 ;\n wire \\one_inc_max_limit[11]_i_4_n_0 ;\n wire \\one_inc_max_limit[4]_i_2_n_0 ;\n wire \\one_inc_max_limit[4]_i_3_n_0 ;\n wire \\one_inc_max_limit[4]_i_4_n_0 ;\n wire \\one_inc_max_limit[4]_i_5_n_0 ;\n wire \\one_inc_max_limit[8]_i_2_n_0 ;\n wire \\one_inc_max_limit[8]_i_3_n_0 ;\n wire \\one_inc_max_limit[8]_i_4_n_0 ;\n wire \\one_inc_max_limit[8]_i_5_n_0 ;\n wire [11:1]one_inc_max_limit_nxt;\n wire \\one_inc_max_limit_reg[11]_i_1_n_2 ;\n wire \\one_inc_max_limit_reg[11]_i_1_n_3 ;\n wire \\one_inc_max_limit_reg[4]_i_1_n_0 ;\n wire \\one_inc_max_limit_reg[4]_i_1_n_1 ;\n wire \\one_inc_max_limit_reg[4]_i_1_n_2 ;\n wire \\one_inc_max_limit_reg[4]_i_1_n_3 ;\n wire \\one_inc_max_limit_reg[8]_i_1_n_0 ;\n wire \\one_inc_max_limit_reg[8]_i_1_n_1 ;\n wire \\one_inc_max_limit_reg[8]_i_1_n_2 ;\n wire \\one_inc_max_limit_reg[8]_i_1_n_3 ;\n wire [11:1]one_inc_min_limit;\n wire \\one_inc_min_limit[11]_i_2_n_0 ;\n wire \\one_inc_min_limit[11]_i_3_n_0 ;\n wire \\one_inc_min_limit[5]_i_2_n_0 ;\n wire \\one_inc_min_limit[5]_i_3_n_0 ;\n wire \\one_inc_min_limit[5]_i_4_n_0 ;\n wire \\one_inc_min_limit[5]_i_5_n_0 ;\n wire \\one_inc_min_limit[9]_i_2_n_0 ;\n wire \\one_inc_min_limit[9]_i_3_n_0 ;\n wire \\one_inc_min_limit[9]_i_4_n_0 ;\n wire \\one_inc_min_limit[9]_i_5_n_0 ;\n wire [11:2]one_inc_min_limit_nxt;\n wire \\one_inc_min_limit_reg[11]_i_1_n_3 ;\n wire \\one_inc_min_limit_reg[5]_i_1_n_0 ;\n wire \\one_inc_min_limit_reg[5]_i_1_n_1 ;\n wire \\one_inc_min_limit_reg[5]_i_1_n_2 ;\n wire \\one_inc_min_limit_reg[5]_i_1_n_3 ;\n wire \\one_inc_min_limit_reg[9]_i_1_n_0 ;\n wire \\one_inc_min_limit_reg[9]_i_1_n_1 ;\n wire \\one_inc_min_limit_reg[9]_i_1_n_2 ;\n wire \\one_inc_min_limit_reg[9]_i_1_n_3 ;\n wire p_0_in;\n wire pi_f_dec_i_2_n_0;\n wire pi_f_dec_nxt;\n wire pi_f_inc_i_10_n_0;\n wire pi_f_inc_i_2_n_0;\n wire pi_f_inc_i_3_n_0;\n wire pi_f_inc_i_5_n_0;\n wire pi_f_inc_i_6_n_0;\n wire pi_f_inc_i_7_n_0;\n wire pi_f_inc_i_8_n_0;\n wire pi_f_inc_i_9_n_0;\n wire pi_f_inc_nxt;\n wire rd_data_offset_cal_done;\n wire rstdiv0_sync_r1_reg_rep__2;\n wire rstdiv0_sync_r1_reg_rep__24;\n wire [0:0]rstdiv0_sync_r1_reg_rep__4;\n wire rstdiv0_sync_r1_reg_rep__5;\n wire rstdiv0_sync_r1_reg_rep__6;\n wire [0:0]rstdiv0_sync_r1_reg_rep__7;\n wire temp_cmp_four_dec_min_101;\n wire temp_cmp_four_dec_min_102;\n wire temp_cmp_four_dec_min_102_i_10_n_0;\n wire temp_cmp_four_dec_min_102_i_11_n_0;\n wire temp_cmp_four_dec_min_102_i_12_n_0;\n wire temp_cmp_four_dec_min_102_i_13_n_0;\n wire temp_cmp_four_dec_min_102_i_14_n_0;\n wire temp_cmp_four_dec_min_102_i_3_n_0;\n wire temp_cmp_four_dec_min_102_i_4_n_0;\n wire temp_cmp_four_dec_min_102_i_5_n_0;\n wire temp_cmp_four_dec_min_102_i_6_n_0;\n wire temp_cmp_four_dec_min_102_i_7_n_0;\n wire temp_cmp_four_dec_min_102_i_8_n_0;\n wire temp_cmp_four_dec_min_102_i_9_n_0;\n wire temp_cmp_four_dec_min_102_reg_i_1_n_3;\n wire temp_cmp_four_dec_min_102_reg_i_2_n_0;\n wire temp_cmp_four_dec_min_102_reg_i_2_n_1;\n wire temp_cmp_four_dec_min_102_reg_i_2_n_2;\n wire temp_cmp_four_dec_min_102_reg_i_2_n_3;\n wire temp_cmp_four_inc_max_101;\n wire temp_cmp_four_inc_max_102;\n wire temp_cmp_four_inc_max_102_i_10_n_0;\n wire temp_cmp_four_inc_max_102_i_11_n_0;\n wire temp_cmp_four_inc_max_102_i_12_n_0;\n wire temp_cmp_four_inc_max_102_i_13_n_0;\n wire temp_cmp_four_inc_max_102_i_14_n_0;\n wire temp_cmp_four_inc_max_102_i_3_n_0;\n wire temp_cmp_four_inc_max_102_i_4_n_0;\n wire temp_cmp_four_inc_max_102_i_5_n_0;\n wire temp_cmp_four_inc_max_102_i_6_n_0;\n wire temp_cmp_four_inc_max_102_i_7_n_0;\n wire temp_cmp_four_inc_max_102_i_8_n_0;\n wire temp_cmp_four_inc_max_102_i_9_n_0;\n wire temp_cmp_four_inc_max_102_reg_i_1_n_3;\n wire temp_cmp_four_inc_max_102_reg_i_2_n_0;\n wire temp_cmp_four_inc_max_102_reg_i_2_n_1;\n wire temp_cmp_four_inc_max_102_reg_i_2_n_2;\n wire temp_cmp_four_inc_max_102_reg_i_2_n_3;\n wire temp_cmp_neutral_max_101;\n wire temp_cmp_neutral_max_102;\n wire temp_cmp_neutral_max_102_i_10_n_0;\n wire temp_cmp_neutral_max_102_i_11_n_0;\n wire temp_cmp_neutral_max_102_i_12_n_0;\n wire temp_cmp_neutral_max_102_i_13_n_0;\n wire temp_cmp_neutral_max_102_i_14_n_0;\n wire temp_cmp_neutral_max_102_i_3_n_0;\n wire temp_cmp_neutral_max_102_i_4_n_0;\n wire temp_cmp_neutral_max_102_i_5_n_0;\n wire temp_cmp_neutral_max_102_i_6_n_0;\n wire temp_cmp_neutral_max_102_i_7_n_0;\n wire temp_cmp_neutral_max_102_i_8_n_0;\n wire temp_cmp_neutral_max_102_i_9_n_0;\n wire temp_cmp_neutral_max_102_reg_i_1_n_3;\n wire temp_cmp_neutral_max_102_reg_i_2_n_0;\n wire temp_cmp_neutral_max_102_reg_i_2_n_1;\n wire temp_cmp_neutral_max_102_reg_i_2_n_2;\n wire temp_cmp_neutral_max_102_reg_i_2_n_3;\n wire temp_cmp_neutral_min_101;\n wire temp_cmp_neutral_min_102;\n wire temp_cmp_neutral_min_102_i_10_n_0;\n wire temp_cmp_neutral_min_102_i_11_n_0;\n wire temp_cmp_neutral_min_102_i_12_n_0;\n wire temp_cmp_neutral_min_102_i_13_n_0;\n wire temp_cmp_neutral_min_102_i_14_n_0;\n wire temp_cmp_neutral_min_102_i_3_n_0;\n wire temp_cmp_neutral_min_102_i_4_n_0;\n wire temp_cmp_neutral_min_102_i_5_n_0;\n wire temp_cmp_neutral_min_102_i_6_n_0;\n wire temp_cmp_neutral_min_102_i_7_n_0;\n wire temp_cmp_neutral_min_102_i_8_n_0;\n wire temp_cmp_neutral_min_102_i_9_n_0;\n wire temp_cmp_neutral_min_102_reg_i_1_n_3;\n wire temp_cmp_neutral_min_102_reg_i_2_n_0;\n wire temp_cmp_neutral_min_102_reg_i_2_n_1;\n wire temp_cmp_neutral_min_102_reg_i_2_n_2;\n wire temp_cmp_neutral_min_102_reg_i_2_n_3;\n wire temp_cmp_one_dec_max_101;\n wire temp_cmp_one_dec_max_102;\n wire temp_cmp_one_dec_max_102_i_10_n_0;\n wire temp_cmp_one_dec_max_102_i_11_n_0;\n wire temp_cmp_one_dec_max_102_i_12_n_0;\n wire temp_cmp_one_dec_max_102_i_13_n_0;\n wire temp_cmp_one_dec_max_102_i_14_n_0;\n wire temp_cmp_one_dec_max_102_i_3_n_0;\n wire temp_cmp_one_dec_max_102_i_4_n_0;\n wire temp_cmp_one_dec_max_102_i_5_n_0;\n wire temp_cmp_one_dec_max_102_i_6_n_0;\n wire temp_cmp_one_dec_max_102_i_7_n_0;\n wire temp_cmp_one_dec_max_102_i_8_n_0;\n wire temp_cmp_one_dec_max_102_i_9_n_0;\n wire temp_cmp_one_dec_max_102_reg_i_1_n_3;\n wire temp_cmp_one_dec_max_102_reg_i_2_n_0;\n wire temp_cmp_one_dec_max_102_reg_i_2_n_1;\n wire temp_cmp_one_dec_max_102_reg_i_2_n_2;\n wire temp_cmp_one_dec_max_102_reg_i_2_n_3;\n wire temp_cmp_one_dec_min_101;\n wire temp_cmp_one_dec_min_102;\n wire temp_cmp_one_dec_min_102_i_10_n_0;\n wire temp_cmp_one_dec_min_102_i_11_n_0;\n wire temp_cmp_one_dec_min_102_i_12_n_0;\n wire temp_cmp_one_dec_min_102_i_13_n_0;\n wire temp_cmp_one_dec_min_102_i_14_n_0;\n wire temp_cmp_one_dec_min_102_i_3_n_0;\n wire temp_cmp_one_dec_min_102_i_4_n_0;\n wire temp_cmp_one_dec_min_102_i_5_n_0;\n wire temp_cmp_one_dec_min_102_i_6_n_0;\n wire temp_cmp_one_dec_min_102_i_7_n_0;\n wire temp_cmp_one_dec_min_102_i_8_n_0;\n wire temp_cmp_one_dec_min_102_i_9_n_0;\n wire temp_cmp_one_dec_min_102_reg_i_1_n_3;\n wire temp_cmp_one_dec_min_102_reg_i_2_n_0;\n wire temp_cmp_one_dec_min_102_reg_i_2_n_1;\n wire temp_cmp_one_dec_min_102_reg_i_2_n_2;\n wire temp_cmp_one_dec_min_102_reg_i_2_n_3;\n wire temp_cmp_one_inc_max_101;\n wire temp_cmp_one_inc_max_102;\n wire temp_cmp_one_inc_max_102_i_10_n_0;\n wire temp_cmp_one_inc_max_102_i_11_n_0;\n wire temp_cmp_one_inc_max_102_i_12_n_0;\n wire temp_cmp_one_inc_max_102_i_13_n_0;\n wire temp_cmp_one_inc_max_102_i_14_n_0;\n wire temp_cmp_one_inc_max_102_i_3_n_0;\n wire temp_cmp_one_inc_max_102_i_4_n_0;\n wire temp_cmp_one_inc_max_102_i_5_n_0;\n wire temp_cmp_one_inc_max_102_i_6_n_0;\n wire temp_cmp_one_inc_max_102_i_7_n_0;\n wire temp_cmp_one_inc_max_102_i_8_n_0;\n wire temp_cmp_one_inc_max_102_i_9_n_0;\n wire temp_cmp_one_inc_max_102_reg_i_1_n_3;\n wire temp_cmp_one_inc_max_102_reg_i_2_n_0;\n wire temp_cmp_one_inc_max_102_reg_i_2_n_1;\n wire temp_cmp_one_inc_max_102_reg_i_2_n_2;\n wire temp_cmp_one_inc_max_102_reg_i_2_n_3;\n wire temp_cmp_one_inc_min_101;\n wire temp_cmp_one_inc_min_102;\n wire temp_cmp_one_inc_min_102_i_10_n_0;\n wire temp_cmp_one_inc_min_102_i_11_n_0;\n wire temp_cmp_one_inc_min_102_i_12_n_0;\n wire temp_cmp_one_inc_min_102_i_13_n_0;\n wire temp_cmp_one_inc_min_102_i_14_n_0;\n wire temp_cmp_one_inc_min_102_i_3_n_0;\n wire temp_cmp_one_inc_min_102_i_4_n_0;\n wire temp_cmp_one_inc_min_102_i_5_n_0;\n wire temp_cmp_one_inc_min_102_i_6_n_0;\n wire temp_cmp_one_inc_min_102_i_7_n_0;\n wire temp_cmp_one_inc_min_102_i_8_n_0;\n wire temp_cmp_one_inc_min_102_i_9_n_0;\n wire temp_cmp_one_inc_min_102_reg_i_1_n_3;\n wire temp_cmp_one_inc_min_102_reg_i_2_n_0;\n wire temp_cmp_one_inc_min_102_reg_i_2_n_1;\n wire temp_cmp_one_inc_min_102_reg_i_2_n_2;\n wire temp_cmp_one_inc_min_102_reg_i_2_n_3;\n wire temp_cmp_three_dec_max_101;\n wire temp_cmp_three_dec_max_102;\n wire temp_cmp_three_dec_max_102_i_10_n_0;\n wire temp_cmp_three_dec_max_102_i_11_n_0;\n wire temp_cmp_three_dec_max_102_i_12_n_0;\n wire temp_cmp_three_dec_max_102_i_13_n_0;\n wire temp_cmp_three_dec_max_102_i_14_n_0;\n wire temp_cmp_three_dec_max_102_i_3_n_0;\n wire temp_cmp_three_dec_max_102_i_4_n_0;\n wire temp_cmp_three_dec_max_102_i_5_n_0;\n wire temp_cmp_three_dec_max_102_i_6_n_0;\n wire temp_cmp_three_dec_max_102_i_7_n_0;\n wire temp_cmp_three_dec_max_102_i_8_n_0;\n wire temp_cmp_three_dec_max_102_i_9_n_0;\n wire temp_cmp_three_dec_max_102_reg_i_1_n_3;\n wire temp_cmp_three_dec_max_102_reg_i_2_n_0;\n wire temp_cmp_three_dec_max_102_reg_i_2_n_1;\n wire temp_cmp_three_dec_max_102_reg_i_2_n_2;\n wire temp_cmp_three_dec_max_102_reg_i_2_n_3;\n wire temp_cmp_three_dec_min_101;\n wire temp_cmp_three_dec_min_102;\n wire temp_cmp_three_dec_min_102_i_10_n_0;\n wire temp_cmp_three_dec_min_102_i_11_n_0;\n wire temp_cmp_three_dec_min_102_i_12_n_0;\n wire temp_cmp_three_dec_min_102_i_13_n_0;\n wire temp_cmp_three_dec_min_102_i_14_n_0;\n wire temp_cmp_three_dec_min_102_i_3_n_0;\n wire temp_cmp_three_dec_min_102_i_4_n_0;\n wire temp_cmp_three_dec_min_102_i_5_n_0;\n wire temp_cmp_three_dec_min_102_i_6_n_0;\n wire temp_cmp_three_dec_min_102_i_7_n_0;\n wire temp_cmp_three_dec_min_102_i_8_n_0;\n wire temp_cmp_three_dec_min_102_i_9_n_0;\n wire temp_cmp_three_dec_min_102_reg_i_1_n_3;\n wire temp_cmp_three_dec_min_102_reg_i_2_n_0;\n wire temp_cmp_three_dec_min_102_reg_i_2_n_1;\n wire temp_cmp_three_dec_min_102_reg_i_2_n_2;\n wire temp_cmp_three_dec_min_102_reg_i_2_n_3;\n wire temp_cmp_three_inc_max_101;\n wire temp_cmp_three_inc_max_102;\n wire temp_cmp_three_inc_max_102_i_10_n_0;\n wire temp_cmp_three_inc_max_102_i_11_n_0;\n wire temp_cmp_three_inc_max_102_i_12_n_0;\n wire temp_cmp_three_inc_max_102_i_13_n_0;\n wire temp_cmp_three_inc_max_102_i_14_n_0;\n wire temp_cmp_three_inc_max_102_i_3_n_0;\n wire temp_cmp_three_inc_max_102_i_4_n_0;\n wire temp_cmp_three_inc_max_102_i_5_n_0;\n wire temp_cmp_three_inc_max_102_i_6_n_0;\n wire temp_cmp_three_inc_max_102_i_7_n_0;\n wire temp_cmp_three_inc_max_102_i_8_n_0;\n wire temp_cmp_three_inc_max_102_i_9_n_0;\n wire temp_cmp_three_inc_max_102_reg_i_1_n_3;\n wire temp_cmp_three_inc_max_102_reg_i_2_n_0;\n wire temp_cmp_three_inc_max_102_reg_i_2_n_1;\n wire temp_cmp_three_inc_max_102_reg_i_2_n_2;\n wire temp_cmp_three_inc_max_102_reg_i_2_n_3;\n wire temp_cmp_three_inc_min_101;\n wire temp_cmp_three_inc_min_102;\n wire temp_cmp_three_inc_min_102_i_10_n_0;\n wire temp_cmp_three_inc_min_102_i_11_n_0;\n wire temp_cmp_three_inc_min_102_i_12_n_0;\n wire temp_cmp_three_inc_min_102_i_13_n_0;\n wire temp_cmp_three_inc_min_102_i_14_n_0;\n wire temp_cmp_three_inc_min_102_i_3_n_0;\n wire temp_cmp_three_inc_min_102_i_4_n_0;\n wire temp_cmp_three_inc_min_102_i_5_n_0;\n wire temp_cmp_three_inc_min_102_i_6_n_0;\n wire temp_cmp_three_inc_min_102_i_7_n_0;\n wire temp_cmp_three_inc_min_102_i_8_n_0;\n wire temp_cmp_three_inc_min_102_i_9_n_0;\n wire temp_cmp_three_inc_min_102_reg_i_1_n_3;\n wire temp_cmp_three_inc_min_102_reg_i_2_n_0;\n wire temp_cmp_three_inc_min_102_reg_i_2_n_1;\n wire temp_cmp_three_inc_min_102_reg_i_2_n_2;\n wire temp_cmp_three_inc_min_102_reg_i_2_n_3;\n wire temp_cmp_two_dec_max_101;\n wire temp_cmp_two_dec_max_102;\n wire temp_cmp_two_dec_max_102_i_10_n_0;\n wire temp_cmp_two_dec_max_102_i_11_n_0;\n wire temp_cmp_two_dec_max_102_i_12_n_0;\n wire temp_cmp_two_dec_max_102_i_13_n_0;\n wire temp_cmp_two_dec_max_102_i_14_n_0;\n wire temp_cmp_two_dec_max_102_i_3_n_0;\n wire temp_cmp_two_dec_max_102_i_4_n_0;\n wire temp_cmp_two_dec_max_102_i_5_n_0;\n wire temp_cmp_two_dec_max_102_i_6_n_0;\n wire temp_cmp_two_dec_max_102_i_7_n_0;\n wire temp_cmp_two_dec_max_102_i_8_n_0;\n wire temp_cmp_two_dec_max_102_i_9_n_0;\n wire temp_cmp_two_dec_max_102_reg_i_1_n_3;\n wire temp_cmp_two_dec_max_102_reg_i_2_n_0;\n wire temp_cmp_two_dec_max_102_reg_i_2_n_1;\n wire temp_cmp_two_dec_max_102_reg_i_2_n_2;\n wire temp_cmp_two_dec_max_102_reg_i_2_n_3;\n wire temp_cmp_two_dec_min_101;\n wire temp_cmp_two_dec_min_102;\n wire temp_cmp_two_dec_min_102_i_10_n_0;\n wire temp_cmp_two_dec_min_102_i_11_n_0;\n wire temp_cmp_two_dec_min_102_i_12_n_0;\n wire temp_cmp_two_dec_min_102_i_13_n_0;\n wire temp_cmp_two_dec_min_102_i_14_n_0;\n wire temp_cmp_two_dec_min_102_i_3_n_0;\n wire temp_cmp_two_dec_min_102_i_4_n_0;\n wire temp_cmp_two_dec_min_102_i_5_n_0;\n wire temp_cmp_two_dec_min_102_i_6_n_0;\n wire temp_cmp_two_dec_min_102_i_7_n_0;\n wire temp_cmp_two_dec_min_102_i_8_n_0;\n wire temp_cmp_two_dec_min_102_i_9_n_0;\n wire temp_cmp_two_dec_min_102_reg_i_1_n_3;\n wire temp_cmp_two_dec_min_102_reg_i_2_n_0;\n wire temp_cmp_two_dec_min_102_reg_i_2_n_1;\n wire temp_cmp_two_dec_min_102_reg_i_2_n_2;\n wire temp_cmp_two_dec_min_102_reg_i_2_n_3;\n wire temp_cmp_two_inc_max_101;\n wire temp_cmp_two_inc_max_102;\n wire temp_cmp_two_inc_max_102_i_10_n_0;\n wire temp_cmp_two_inc_max_102_i_11_n_0;\n wire temp_cmp_two_inc_max_102_i_12_n_0;\n wire temp_cmp_two_inc_max_102_i_13_n_0;\n wire temp_cmp_two_inc_max_102_i_14_n_0;\n wire temp_cmp_two_inc_max_102_i_3_n_0;\n wire temp_cmp_two_inc_max_102_i_4_n_0;\n wire temp_cmp_two_inc_max_102_i_5_n_0;\n wire temp_cmp_two_inc_max_102_i_6_n_0;\n wire temp_cmp_two_inc_max_102_i_7_n_0;\n wire temp_cmp_two_inc_max_102_i_8_n_0;\n wire temp_cmp_two_inc_max_102_i_9_n_0;\n wire temp_cmp_two_inc_max_102_reg_i_1_n_3;\n wire temp_cmp_two_inc_max_102_reg_i_2_n_0;\n wire temp_cmp_two_inc_max_102_reg_i_2_n_1;\n wire temp_cmp_two_inc_max_102_reg_i_2_n_2;\n wire temp_cmp_two_inc_max_102_reg_i_2_n_3;\n wire temp_cmp_two_inc_min_101;\n wire temp_cmp_two_inc_min_102;\n wire temp_cmp_two_inc_min_102_i_10_n_0;\n wire temp_cmp_two_inc_min_102_i_11_n_0;\n wire temp_cmp_two_inc_min_102_i_12_n_0;\n wire temp_cmp_two_inc_min_102_i_13_n_0;\n wire temp_cmp_two_inc_min_102_i_14_n_0;\n wire temp_cmp_two_inc_min_102_i_3_n_0;\n wire temp_cmp_two_inc_min_102_i_4_n_0;\n wire temp_cmp_two_inc_min_102_i_5_n_0;\n wire temp_cmp_two_inc_min_102_i_6_n_0;\n wire temp_cmp_two_inc_min_102_i_7_n_0;\n wire temp_cmp_two_inc_min_102_i_8_n_0;\n wire temp_cmp_two_inc_min_102_i_9_n_0;\n wire temp_cmp_two_inc_min_102_reg_i_1_n_3;\n wire temp_cmp_two_inc_min_102_reg_i_2_n_0;\n wire temp_cmp_two_inc_min_102_reg_i_2_n_1;\n wire temp_cmp_two_inc_min_102_reg_i_2_n_2;\n wire temp_cmp_two_inc_min_102_reg_i_2_n_3;\n wire temp_gte_three_dec_max;\n wire tempmon_init_complete;\n wire tempmon_pi_f_dec;\n wire tempmon_pi_f_inc;\n wire tempmon_sample_en;\n wire tempmon_sample_en_101;\n wire tempmon_sample_en_102;\n wire tempmon_sel_pi_incdec;\n wire [10:0]tempmon_state;\n wire \\tempmon_state[0]_i_2_n_0 ;\n wire \\tempmon_state[10]_i_10_n_0 ;\n wire \\tempmon_state[10]_i_11_n_0 ;\n wire \\tempmon_state[10]_i_12_n_0 ;\n wire \\tempmon_state[10]_i_13_n_0 ;\n wire \\tempmon_state[10]_i_14_n_0 ;\n wire \\tempmon_state[10]_i_15_n_0 ;\n wire \\tempmon_state[10]_i_16_n_0 ;\n wire \\tempmon_state[10]_i_2_n_0 ;\n wire \\tempmon_state[10]_i_3_n_0 ;\n wire \\tempmon_state[10]_i_4_n_0 ;\n wire \\tempmon_state[10]_i_5_n_0 ;\n wire \\tempmon_state[10]_i_6_n_0 ;\n wire \\tempmon_state[10]_i_7_n_0 ;\n wire \\tempmon_state[10]_i_8_n_0 ;\n wire \\tempmon_state[10]_i_9_n_0 ;\n wire \\tempmon_state[1]_i_1_n_0 ;\n wire \\tempmon_state[2]_i_1_n_0 ;\n wire \\tempmon_state[3]_i_1_n_0 ;\n wire \\tempmon_state[4]_i_1_n_0 ;\n wire \\tempmon_state[5]_i_1_n_0 ;\n wire \\tempmon_state[6]_i_1_n_0 ;\n wire \\tempmon_state[6]_i_2_n_0 ;\n wire \\tempmon_state[7]_i_1_n_0 ;\n wire \\tempmon_state[8]_i_1_n_0 ;\n wire \\tempmon_state[9]_i_1_n_0 ;\n wire tempmon_state_init;\n wire tempmon_state_nxt;\n wire [11:0]three_dec_max_limit;\n wire \\three_dec_max_limit[0]_i_1_n_0 ;\n wire \\three_dec_max_limit[10]_i_1_n_0 ;\n wire \\three_dec_max_limit[11]_i_1_n_0 ;\n wire \\three_dec_max_limit[11]_i_3_n_0 ;\n wire \\three_dec_max_limit[11]_i_4_n_0 ;\n wire \\three_dec_max_limit[11]_i_5_n_0 ;\n wire \\three_dec_max_limit[1]_i_1_n_0 ;\n wire \\three_dec_max_limit[2]_i_1_n_0 ;\n wire \\three_dec_max_limit[3]_i_1_n_0 ;\n wire \\three_dec_max_limit[4]_i_1_n_0 ;\n wire \\three_dec_max_limit[4]_i_3_n_0 ;\n wire \\three_dec_max_limit[4]_i_4_n_0 ;\n wire \\three_dec_max_limit[4]_i_5_n_0 ;\n wire \\three_dec_max_limit[4]_i_6_n_0 ;\n wire \\three_dec_max_limit[5]_i_1_n_0 ;\n wire \\three_dec_max_limit[6]_i_1_n_0 ;\n wire \\three_dec_max_limit[7]_i_1_n_0 ;\n wire \\three_dec_max_limit[8]_i_1_n_0 ;\n wire \\three_dec_max_limit[8]_i_3_n_0 ;\n wire \\three_dec_max_limit[8]_i_4_n_0 ;\n wire \\three_dec_max_limit[8]_i_5_n_0 ;\n wire \\three_dec_max_limit[8]_i_6_n_0 ;\n wire \\three_dec_max_limit[9]_i_1_n_0 ;\n wire \\three_dec_max_limit_reg[11]_i_2_n_2 ;\n wire \\three_dec_max_limit_reg[11]_i_2_n_3 ;\n wire \\three_dec_max_limit_reg[11]_i_2_n_5 ;\n wire \\three_dec_max_limit_reg[11]_i_2_n_6 ;\n wire \\three_dec_max_limit_reg[11]_i_2_n_7 ;\n wire \\three_dec_max_limit_reg[1]_i_2_n_0 ;\n wire \\three_dec_max_limit_reg[4]_i_2_n_0 ;\n wire \\three_dec_max_limit_reg[4]_i_2_n_1 ;\n wire \\three_dec_max_limit_reg[4]_i_2_n_2 ;\n wire \\three_dec_max_limit_reg[4]_i_2_n_3 ;\n wire \\three_dec_max_limit_reg[4]_i_2_n_4 ;\n wire \\three_dec_max_limit_reg[4]_i_2_n_5 ;\n wire \\three_dec_max_limit_reg[4]_i_2_n_6 ;\n wire \\three_dec_max_limit_reg[8]_i_2_n_0 ;\n wire \\three_dec_max_limit_reg[8]_i_2_n_1 ;\n wire \\three_dec_max_limit_reg[8]_i_2_n_2 ;\n wire \\three_dec_max_limit_reg[8]_i_2_n_3 ;\n wire \\three_dec_max_limit_reg[8]_i_2_n_4 ;\n wire \\three_dec_max_limit_reg[8]_i_2_n_5 ;\n wire \\three_dec_max_limit_reg[8]_i_2_n_6 ;\n wire \\three_dec_max_limit_reg[8]_i_2_n_7 ;\n wire [11:0]three_dec_min_limit;\n wire \\three_dec_min_limit[11]_i_2_n_0 ;\n wire \\three_dec_min_limit[11]_i_3_n_0 ;\n wire \\three_dec_min_limit[5]_i_2_n_0 ;\n wire \\three_dec_min_limit[5]_i_3_n_0 ;\n wire \\three_dec_min_limit[5]_i_4_n_0 ;\n wire \\three_dec_min_limit[5]_i_5_n_0 ;\n wire \\three_dec_min_limit[9]_i_2_n_0 ;\n wire \\three_dec_min_limit[9]_i_3_n_0 ;\n wire \\three_dec_min_limit[9]_i_4_n_0 ;\n wire \\three_dec_min_limit[9]_i_5_n_0 ;\n wire [11:2]three_dec_min_limit_nxt;\n wire \\three_dec_min_limit_reg[11]_i_1_n_3 ;\n wire \\three_dec_min_limit_reg[5]_i_1_n_0 ;\n wire \\three_dec_min_limit_reg[5]_i_1_n_1 ;\n wire \\three_dec_min_limit_reg[5]_i_1_n_2 ;\n wire \\three_dec_min_limit_reg[5]_i_1_n_3 ;\n wire \\three_dec_min_limit_reg[9]_i_1_n_0 ;\n wire \\three_dec_min_limit_reg[9]_i_1_n_1 ;\n wire \\three_dec_min_limit_reg[9]_i_1_n_2 ;\n wire \\three_dec_min_limit_reg[9]_i_1_n_3 ;\n wire [11:1]three_inc_max_limit;\n wire \\three_inc_max_limit[11]_i_2_n_0 ;\n wire \\three_inc_max_limit[11]_i_3_n_0 ;\n wire \\three_inc_max_limit[11]_i_4_n_0 ;\n wire \\three_inc_max_limit[4]_i_2_n_0 ;\n wire \\three_inc_max_limit[4]_i_3_n_0 ;\n wire \\three_inc_max_limit[4]_i_4_n_0 ;\n wire \\three_inc_max_limit[4]_i_5_n_0 ;\n wire \\three_inc_max_limit[8]_i_2_n_0 ;\n wire \\three_inc_max_limit[8]_i_3_n_0 ;\n wire \\three_inc_max_limit[8]_i_4_n_0 ;\n wire \\three_inc_max_limit[8]_i_5_n_0 ;\n wire [11:1]three_inc_max_limit_nxt;\n wire \\three_inc_max_limit_reg[11]_i_1_n_2 ;\n wire \\three_inc_max_limit_reg[11]_i_1_n_3 ;\n wire \\three_inc_max_limit_reg[4]_i_1_n_0 ;\n wire \\three_inc_max_limit_reg[4]_i_1_n_1 ;\n wire \\three_inc_max_limit_reg[4]_i_1_n_2 ;\n wire \\three_inc_max_limit_reg[4]_i_1_n_3 ;\n wire \\three_inc_max_limit_reg[8]_i_1_n_0 ;\n wire \\three_inc_max_limit_reg[8]_i_1_n_1 ;\n wire \\three_inc_max_limit_reg[8]_i_1_n_2 ;\n wire \\three_inc_max_limit_reg[8]_i_1_n_3 ;\n wire [11:1]three_inc_min_limit;\n wire \\three_inc_min_limit[11]_i_2_n_0 ;\n wire \\three_inc_min_limit[11]_i_3_n_0 ;\n wire \\three_inc_min_limit[5]_i_2_n_0 ;\n wire \\three_inc_min_limit[5]_i_3_n_0 ;\n wire \\three_inc_min_limit[5]_i_4_n_0 ;\n wire \\three_inc_min_limit[5]_i_5_n_0 ;\n wire \\three_inc_min_limit[9]_i_2_n_0 ;\n wire \\three_inc_min_limit[9]_i_3_n_0 ;\n wire \\three_inc_min_limit[9]_i_4_n_0 ;\n wire \\three_inc_min_limit[9]_i_5_n_0 ;\n wire [11:2]three_inc_min_limit_nxt;\n wire \\three_inc_min_limit_reg[11]_i_1_n_3 ;\n wire \\three_inc_min_limit_reg[5]_i_1_n_0 ;\n wire \\three_inc_min_limit_reg[5]_i_1_n_1 ;\n wire \\three_inc_min_limit_reg[5]_i_1_n_2 ;\n wire \\three_inc_min_limit_reg[5]_i_1_n_3 ;\n wire \\three_inc_min_limit_reg[9]_i_1_n_0 ;\n wire \\three_inc_min_limit_reg[9]_i_1_n_1 ;\n wire \\three_inc_min_limit_reg[9]_i_1_n_2 ;\n wire \\three_inc_min_limit_reg[9]_i_1_n_3 ;\n wire [11:0]two_dec_max_limit;\n wire \\two_dec_max_limit[0]_i_1_n_0 ;\n wire \\two_dec_max_limit[11]_i_2_n_0 ;\n wire \\two_dec_max_limit[11]_i_3_n_0 ;\n wire \\two_dec_max_limit[11]_i_4_n_0 ;\n wire \\two_dec_max_limit[4]_i_2_n_0 ;\n wire \\two_dec_max_limit[4]_i_3_n_0 ;\n wire \\two_dec_max_limit[4]_i_4_n_0 ;\n wire \\two_dec_max_limit[4]_i_5_n_0 ;\n wire \\two_dec_max_limit[8]_i_2_n_0 ;\n wire \\two_dec_max_limit[8]_i_3_n_0 ;\n wire \\two_dec_max_limit[8]_i_4_n_0 ;\n wire \\two_dec_max_limit[8]_i_5_n_0 ;\n wire [11:1]two_dec_max_limit_nxt;\n wire \\two_dec_max_limit_reg[11]_i_1_n_2 ;\n wire \\two_dec_max_limit_reg[11]_i_1_n_3 ;\n wire \\two_dec_max_limit_reg[4]_i_1_n_0 ;\n wire \\two_dec_max_limit_reg[4]_i_1_n_1 ;\n wire \\two_dec_max_limit_reg[4]_i_1_n_2 ;\n wire \\two_dec_max_limit_reg[4]_i_1_n_3 ;\n wire \\two_dec_max_limit_reg[8]_i_1_n_0 ;\n wire \\two_dec_max_limit_reg[8]_i_1_n_1 ;\n wire \\two_dec_max_limit_reg[8]_i_1_n_2 ;\n wire \\two_dec_max_limit_reg[8]_i_1_n_3 ;\n wire [11:1]two_dec_min_limit;\n wire \\two_dec_min_limit[11]_i_2_n_0 ;\n wire \\two_dec_min_limit[11]_i_3_n_0 ;\n wire \\two_dec_min_limit[5]_i_2_n_0 ;\n wire \\two_dec_min_limit[5]_i_3_n_0 ;\n wire \\two_dec_min_limit[5]_i_4_n_0 ;\n wire \\two_dec_min_limit[5]_i_5_n_0 ;\n wire \\two_dec_min_limit[9]_i_2_n_0 ;\n wire \\two_dec_min_limit[9]_i_3_n_0 ;\n wire \\two_dec_min_limit[9]_i_4_n_0 ;\n wire \\two_dec_min_limit[9]_i_5_n_0 ;\n wire [11:2]two_dec_min_limit_nxt;\n wire \\two_dec_min_limit_reg[11]_i_1_n_3 ;\n wire \\two_dec_min_limit_reg[5]_i_1_n_0 ;\n wire \\two_dec_min_limit_reg[5]_i_1_n_1 ;\n wire \\two_dec_min_limit_reg[5]_i_1_n_2 ;\n wire \\two_dec_min_limit_reg[5]_i_1_n_3 ;\n wire \\two_dec_min_limit_reg[9]_i_1_n_0 ;\n wire \\two_dec_min_limit_reg[9]_i_1_n_1 ;\n wire \\two_dec_min_limit_reg[9]_i_1_n_2 ;\n wire \\two_dec_min_limit_reg[9]_i_1_n_3 ;\n wire [11:1]two_inc_max_limit;\n wire \\two_inc_max_limit[11]_i_2_n_0 ;\n wire \\two_inc_max_limit[11]_i_3_n_0 ;\n wire \\two_inc_max_limit[11]_i_4_n_0 ;\n wire \\two_inc_max_limit[4]_i_2_n_0 ;\n wire \\two_inc_max_limit[4]_i_3_n_0 ;\n wire \\two_inc_max_limit[4]_i_4_n_0 ;\n wire \\two_inc_max_limit[4]_i_5_n_0 ;\n wire \\two_inc_max_limit[8]_i_2_n_0 ;\n wire \\two_inc_max_limit[8]_i_3_n_0 ;\n wire \\two_inc_max_limit[8]_i_4_n_0 ;\n wire \\two_inc_max_limit[8]_i_5_n_0 ;\n wire [11:1]two_inc_max_limit_nxt;\n wire \\two_inc_max_limit_reg[11]_i_1_n_2 ;\n wire \\two_inc_max_limit_reg[11]_i_1_n_3 ;\n wire \\two_inc_max_limit_reg[4]_i_1_n_0 ;\n wire \\two_inc_max_limit_reg[4]_i_1_n_1 ;\n wire \\two_inc_max_limit_reg[4]_i_1_n_2 ;\n wire \\two_inc_max_limit_reg[4]_i_1_n_3 ;\n wire \\two_inc_max_limit_reg[8]_i_1_n_0 ;\n wire \\two_inc_max_limit_reg[8]_i_1_n_1 ;\n wire \\two_inc_max_limit_reg[8]_i_1_n_2 ;\n wire \\two_inc_max_limit_reg[8]_i_1_n_3 ;\n wire [11:1]two_inc_min_limit;\n wire \\two_inc_min_limit[11]_i_2_n_0 ;\n wire \\two_inc_min_limit[11]_i_3_n_0 ;\n wire \\two_inc_min_limit[5]_i_2_n_0 ;\n wire \\two_inc_min_limit[5]_i_3_n_0 ;\n wire \\two_inc_min_limit[5]_i_4_n_0 ;\n wire \\two_inc_min_limit[5]_i_5_n_0 ;\n wire \\two_inc_min_limit[9]_i_2_n_0 ;\n wire \\two_inc_min_limit[9]_i_3_n_0 ;\n wire \\two_inc_min_limit[9]_i_4_n_0 ;\n wire \\two_inc_min_limit[9]_i_5_n_0 ;\n wire [11:2]two_inc_min_limit_nxt;\n wire \\two_inc_min_limit_reg[11]_i_1_n_3 ;\n wire \\two_inc_min_limit_reg[5]_i_1_n_0 ;\n wire \\two_inc_min_limit_reg[5]_i_1_n_1 ;\n wire \\two_inc_min_limit_reg[5]_i_1_n_2 ;\n wire \\two_inc_min_limit_reg[5]_i_1_n_3 ;\n wire \\two_inc_min_limit_reg[9]_i_1_n_0 ;\n wire \\two_inc_min_limit_reg[9]_i_1_n_1 ;\n wire \\two_inc_min_limit_reg[9]_i_1_n_2 ;\n wire \\two_inc_min_limit_reg[9]_i_1_n_3 ;\n wire update_temp_101__0;\n wire update_temp_102;\n wire [3:1]\\NLW_four_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED ;\n wire [3:2]\\NLW_four_dec_min_limit_reg[11]_i_1_O_UNCONNECTED ;\n wire [3:2]\\NLW_four_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED ;\n wire [3:3]\\NLW_four_inc_max_limit_reg[11]_i_1_O_UNCONNECTED ;\n wire [3:0]\\NLW_four_inc_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED ;\n wire [3:0]\\NLW_four_inc_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED ;\n wire [3:1]\\NLW_four_inc_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED ;\n wire [3:1]\\NLW_four_inc_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED ;\n wire [3:2]\\NLW_neutral_max_limit_reg[11]_i_1_CO_UNCONNECTED ;\n wire [3:3]\\NLW_neutral_max_limit_reg[11]_i_1_O_UNCONNECTED ;\n wire [3:0]\\NLW_neutral_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED ;\n wire [3:0]\\NLW_neutral_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED ;\n wire [3:1]\\NLW_neutral_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED ;\n wire [3:1]\\NLW_neutral_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED ;\n wire [0:0]\\NLW_neutral_max_limit_reg[4]_i_1_O_UNCONNECTED ;\n wire [3:1]\\NLW_neutral_min_limit_reg[11]_i_1_CO_UNCONNECTED ;\n wire [3:2]\\NLW_neutral_min_limit_reg[11]_i_1_O_UNCONNECTED ;\n wire [3:2]\\NLW_one_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED ;\n wire [3:3]\\NLW_one_dec_max_limit_reg[11]_i_1_O_UNCONNECTED ;\n wire [3:0]\\NLW_one_dec_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED ;\n wire [3:0]\\NLW_one_dec_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED ;\n wire [3:1]\\NLW_one_dec_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED ;\n wire [3:1]\\NLW_one_dec_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED ;\n wire [0:0]\\NLW_one_dec_max_limit_reg[4]_i_1_O_UNCONNECTED ;\n wire [3:1]\\NLW_one_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED ;\n wire [3:2]\\NLW_one_dec_min_limit_reg[11]_i_1_O_UNCONNECTED ;\n wire [3:2]\\NLW_one_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED ;\n wire [3:3]\\NLW_one_inc_max_limit_reg[11]_i_1_O_UNCONNECTED ;\n wire [3:0]\\NLW_one_inc_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED ;\n wire [3:0]\\NLW_one_inc_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED ;\n wire [3:1]\\NLW_one_inc_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED ;\n wire [3:1]\\NLW_one_inc_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED ;\n wire [0:0]\\NLW_one_inc_max_limit_reg[4]_i_1_O_UNCONNECTED ;\n wire [3:1]\\NLW_one_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED ;\n wire [3:2]\\NLW_one_inc_min_limit_reg[11]_i_1_O_UNCONNECTED ;\n wire [3:2]NLW_temp_cmp_four_dec_min_102_reg_i_1_CO_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_four_dec_min_102_reg_i_1_O_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_four_dec_min_102_reg_i_2_O_UNCONNECTED;\n wire [3:2]NLW_temp_cmp_four_inc_max_102_reg_i_1_CO_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_four_inc_max_102_reg_i_1_O_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_four_inc_max_102_reg_i_2_O_UNCONNECTED;\n wire [3:2]NLW_temp_cmp_neutral_max_102_reg_i_1_CO_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_neutral_max_102_reg_i_1_O_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_neutral_max_102_reg_i_2_O_UNCONNECTED;\n wire [3:2]NLW_temp_cmp_neutral_min_102_reg_i_1_CO_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_neutral_min_102_reg_i_1_O_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_neutral_min_102_reg_i_2_O_UNCONNECTED;\n wire [3:2]NLW_temp_cmp_one_dec_max_102_reg_i_1_CO_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_one_dec_max_102_reg_i_1_O_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_one_dec_max_102_reg_i_2_O_UNCONNECTED;\n wire [3:2]NLW_temp_cmp_one_dec_min_102_reg_i_1_CO_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_one_dec_min_102_reg_i_1_O_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_one_dec_min_102_reg_i_2_O_UNCONNECTED;\n wire [3:2]NLW_temp_cmp_one_inc_max_102_reg_i_1_CO_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_one_inc_max_102_reg_i_1_O_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_one_inc_max_102_reg_i_2_O_UNCONNECTED;\n wire [3:2]NLW_temp_cmp_one_inc_min_102_reg_i_1_CO_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_one_inc_min_102_reg_i_1_O_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_one_inc_min_102_reg_i_2_O_UNCONNECTED;\n wire [3:2]NLW_temp_cmp_three_dec_max_102_reg_i_1_CO_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_three_dec_max_102_reg_i_1_O_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_three_dec_max_102_reg_i_2_O_UNCONNECTED;\n wire [3:2]NLW_temp_cmp_three_dec_min_102_reg_i_1_CO_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_three_dec_min_102_reg_i_1_O_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_three_dec_min_102_reg_i_2_O_UNCONNECTED;\n wire [3:2]NLW_temp_cmp_three_inc_max_102_reg_i_1_CO_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_three_inc_max_102_reg_i_1_O_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_three_inc_max_102_reg_i_2_O_UNCONNECTED;\n wire [3:2]NLW_temp_cmp_three_inc_min_102_reg_i_1_CO_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_three_inc_min_102_reg_i_1_O_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_three_inc_min_102_reg_i_2_O_UNCONNECTED;\n wire [3:2]NLW_temp_cmp_two_dec_max_102_reg_i_1_CO_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_two_dec_max_102_reg_i_1_O_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_two_dec_max_102_reg_i_2_O_UNCONNECTED;\n wire [3:2]NLW_temp_cmp_two_dec_min_102_reg_i_1_CO_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_two_dec_min_102_reg_i_1_O_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_two_dec_min_102_reg_i_2_O_UNCONNECTED;\n wire [3:2]NLW_temp_cmp_two_inc_max_102_reg_i_1_CO_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_two_inc_max_102_reg_i_1_O_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_two_inc_max_102_reg_i_2_O_UNCONNECTED;\n wire [3:2]NLW_temp_cmp_two_inc_min_102_reg_i_1_CO_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_two_inc_min_102_reg_i_1_O_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_two_inc_min_102_reg_i_2_O_UNCONNECTED;\n wire [2:2]\\NLW_three_dec_max_limit_reg[11]_i_2_CO_UNCONNECTED ;\n wire [3:3]\\NLW_three_dec_max_limit_reg[11]_i_2_O_UNCONNECTED ;\n wire [3:0]\\NLW_three_dec_max_limit_reg[1]_i_2_CARRY4_CO_UNCONNECTED ;\n wire [3:0]\\NLW_three_dec_max_limit_reg[1]_i_2_CARRY4_DI_UNCONNECTED ;\n wire [3:1]\\NLW_three_dec_max_limit_reg[1]_i_2_CARRY4_O_UNCONNECTED ;\n wire [3:1]\\NLW_three_dec_max_limit_reg[1]_i_2_CARRY4_S_UNCONNECTED ;\n wire [0:0]\\NLW_three_dec_max_limit_reg[4]_i_2_O_UNCONNECTED ;\n wire [3:1]\\NLW_three_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED ;\n wire [3:2]\\NLW_three_dec_min_limit_reg[11]_i_1_O_UNCONNECTED ;\n wire [3:2]\\NLW_three_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED ;\n wire [3:3]\\NLW_three_inc_max_limit_reg[11]_i_1_O_UNCONNECTED ;\n wire [3:1]\\NLW_three_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED ;\n wire [3:2]\\NLW_three_inc_min_limit_reg[11]_i_1_O_UNCONNECTED ;\n wire [3:2]\\NLW_two_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED ;\n wire [3:3]\\NLW_two_dec_max_limit_reg[11]_i_1_O_UNCONNECTED ;\n wire [3:0]\\NLW_two_dec_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED ;\n wire [3:0]\\NLW_two_dec_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED ;\n wire [3:1]\\NLW_two_dec_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED ;\n wire [3:1]\\NLW_two_dec_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED ;\n wire [0:0]\\NLW_two_dec_max_limit_reg[4]_i_1_O_UNCONNECTED ;\n wire [3:1]\\NLW_two_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED ;\n wire [3:2]\\NLW_two_dec_min_limit_reg[11]_i_1_O_UNCONNECTED ;\n wire [3:2]\\NLW_two_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED ;\n wire [3:3]\\NLW_two_inc_max_limit_reg[11]_i_1_O_UNCONNECTED ;\n wire [0:0]\\NLW_two_inc_max_limit_reg[4]_i_1_O_UNCONNECTED ;\n wire [3:1]\\NLW_two_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED ;\n wire [3:2]\\NLW_two_inc_min_limit_reg[11]_i_1_O_UNCONNECTED ;\n\n (* SOFT_HLUTNM = \"soft_lutpair247\" *) \n LUT4 #(\n .INIT(16'h3331)) \n \\calib_sel[1]_i_2 \n (.I0(calib_complete),\n .I1(rstdiv0_sync_r1_reg_rep__24),\n .I2(tempmon_pi_f_inc),\n .I3(tempmon_pi_f_dec),\n .O(\\calib_zero_inputs_reg[1]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair247\" *) \n LUT5 #(\n .INIT(32'h00A800AA)) \n \\calib_sel[3]_i_1 \n (.I0(ctl_lane_sel),\n .I1(tempmon_pi_f_dec),\n .I2(tempmon_pi_f_inc),\n .I3(rstdiv0_sync_r1_reg_rep__24),\n .I4(calib_complete),\n .O(D));\n LUT6 #(\n .INIT(64'h00000200FFFFFFFF)) \n \\calib_zero_inputs[1]_i_1 \n (.I0(cmd_delay_start0),\n .I1(tempmon_pi_f_inc),\n .I2(tempmon_pi_f_dec),\n .I3(delay_done_r4_reg),\n .I4(calib_in_common),\n .I5(\\calib_zero_inputs_reg[1]_0 ),\n .O(\\calib_zero_inputs_reg[1] ));\n FDRE #(\n .INIT(1'b0)) \n \\device_temp_101_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\device_temp_r_reg[11] [0]),\n .Q(device_temp_101[0]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE #(\n .INIT(1'b0)) \n \\device_temp_101_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(\\device_temp_r_reg[11] [10]),\n .Q(device_temp_101[10]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE #(\n .INIT(1'b0)) \n \\device_temp_101_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(\\device_temp_r_reg[11] [11]),\n .Q(device_temp_101[11]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE #(\n .INIT(1'b0)) \n \\device_temp_101_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\device_temp_r_reg[11] [1]),\n .Q(device_temp_101[1]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE #(\n .INIT(1'b0)) \n \\device_temp_101_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\device_temp_r_reg[11] [2]),\n .Q(device_temp_101[2]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE #(\n .INIT(1'b0)) \n \\device_temp_101_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\device_temp_r_reg[11] [3]),\n .Q(device_temp_101[3]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE #(\n .INIT(1'b0)) \n \\device_temp_101_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\device_temp_r_reg[11] [4]),\n .Q(device_temp_101[4]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE #(\n .INIT(1'b0)) \n \\device_temp_101_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\device_temp_r_reg[11] [5]),\n .Q(device_temp_101[5]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE #(\n .INIT(1'b0)) \n \\device_temp_101_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\device_temp_r_reg[11] [6]),\n .Q(device_temp_101[6]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE #(\n .INIT(1'b0)) \n \\device_temp_101_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\device_temp_r_reg[11] [7]),\n .Q(device_temp_101[7]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE #(\n .INIT(1'b0)) \n \\device_temp_101_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(\\device_temp_r_reg[11] [8]),\n .Q(device_temp_101[8]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE #(\n .INIT(1'b0)) \n \\device_temp_101_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(\\device_temp_r_reg[11] [9]),\n .Q(device_temp_101[9]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n LUT5 #(\n .INIT(32'h00000800)) \n \\device_temp_init[11]_i_1 \n (.I0(\\device_temp_init[11]_i_2_n_0 ),\n .I1(\\device_temp_init[11]_i_3_n_0 ),\n .I2(tempmon_state[0]),\n .I3(tempmon_state[1]),\n .I4(tempmon_state[2]),\n .O(tempmon_state_init));\n (* SOFT_HLUTNM = \"soft_lutpair253\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\device_temp_init[11]_i_2 \n (.I0(tempmon_state[6]),\n .I1(tempmon_state[5]),\n .I2(tempmon_state[4]),\n .I3(tempmon_state[3]),\n .O(\\device_temp_init[11]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'h0001)) \n \\device_temp_init[11]_i_3 \n (.I0(tempmon_state[10]),\n .I1(tempmon_state[9]),\n .I2(tempmon_state[8]),\n .I3(tempmon_state[7]),\n .O(\\device_temp_init[11]_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\device_temp_init_reg[0] \n (.C(CLK),\n .CE(tempmon_state_init),\n .D(device_temp_101[0]),\n .Q(device_temp_init[0]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\device_temp_init_reg[10] \n (.C(CLK),\n .CE(tempmon_state_init),\n .D(device_temp_101[10]),\n .Q(device_temp_init[10]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\device_temp_init_reg[11] \n (.C(CLK),\n .CE(tempmon_state_init),\n .D(device_temp_101[11]),\n .Q(device_temp_init[11]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\device_temp_init_reg[1] \n (.C(CLK),\n .CE(tempmon_state_init),\n .D(device_temp_101[1]),\n .Q(device_temp_init[1]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\device_temp_init_reg[2] \n (.C(CLK),\n .CE(tempmon_state_init),\n .D(device_temp_101[2]),\n .Q(device_temp_init[2]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\device_temp_init_reg[3] \n (.C(CLK),\n .CE(tempmon_state_init),\n .D(device_temp_101[3]),\n .Q(device_temp_init[3]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\device_temp_init_reg[4] \n (.C(CLK),\n .CE(tempmon_state_init),\n .D(device_temp_101[4]),\n .Q(device_temp_init[4]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\device_temp_init_reg[5] \n (.C(CLK),\n .CE(tempmon_state_init),\n .D(device_temp_101[5]),\n .Q(device_temp_init[5]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\device_temp_init_reg[6] \n (.C(CLK),\n .CE(tempmon_state_init),\n .D(device_temp_101[6]),\n .Q(device_temp_init[6]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\device_temp_init_reg[7] \n (.C(CLK),\n .CE(tempmon_state_init),\n .D(device_temp_101[7]),\n .Q(device_temp_init[7]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\device_temp_init_reg[8] \n (.C(CLK),\n .CE(tempmon_state_init),\n .D(device_temp_101[8]),\n .Q(device_temp_init[8]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\device_temp_init_reg[9] \n (.C(CLK),\n .CE(tempmon_state_init),\n .D(device_temp_101[9]),\n .Q(device_temp_init[9]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n LUT1 #(\n .INIT(2'h1)) \n \\four_dec_min_limit[11]_i_2 \n (.I0(three_dec_max_limit[11]),\n .O(\\four_dec_min_limit[11]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\four_dec_min_limit[11]_i_3 \n (.I0(three_dec_max_limit[10]),\n .O(\\four_dec_min_limit[11]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\four_dec_min_limit[5]_i_2 \n (.I0(three_dec_max_limit[5]),\n .O(\\four_dec_min_limit[5]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\four_dec_min_limit[5]_i_3 \n (.I0(three_dec_max_limit[4]),\n .O(\\four_dec_min_limit[5]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\four_dec_min_limit[5]_i_4 \n (.I0(three_dec_max_limit[3]),\n .O(\\four_dec_min_limit[5]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\four_dec_min_limit[5]_i_5 \n (.I0(three_dec_max_limit[2]),\n .O(\\four_dec_min_limit[5]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\four_dec_min_limit[9]_i_2 \n (.I0(three_dec_max_limit[9]),\n .O(\\four_dec_min_limit[9]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\four_dec_min_limit[9]_i_3 \n (.I0(three_dec_max_limit[8]),\n .O(\\four_dec_min_limit[9]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\four_dec_min_limit[9]_i_4 \n (.I0(three_dec_max_limit[7]),\n .O(\\four_dec_min_limit[9]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\four_dec_min_limit[9]_i_5 \n (.I0(three_dec_max_limit[6]),\n .O(\\four_dec_min_limit[9]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\four_dec_min_limit_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(three_dec_max_limit[0]),\n .Q(four_dec_min_limit[0]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE #(\n .INIT(1'b0)) \n \\four_dec_min_limit_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(four_dec_min_limit_nxt[10]),\n .Q(four_dec_min_limit[10]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE #(\n .INIT(1'b0)) \n \\four_dec_min_limit_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(four_dec_min_limit_nxt[11]),\n .Q(four_dec_min_limit[11]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n CARRY4 \\four_dec_min_limit_reg[11]_i_1 \n (.CI(\\four_dec_min_limit_reg[9]_i_1_n_0 ),\n .CO({\\NLW_four_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\\four_dec_min_limit_reg[11]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,three_dec_max_limit[10]}),\n .O({\\NLW_four_dec_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],four_dec_min_limit_nxt[11:10]}),\n .S({1'b0,1'b0,\\four_dec_min_limit[11]_i_2_n_0 ,\\four_dec_min_limit[11]_i_3_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\four_dec_min_limit_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(three_dec_max_limit[1]),\n .Q(four_dec_min_limit[1]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE #(\n .INIT(1'b0)) \n \\four_dec_min_limit_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(four_dec_min_limit_nxt[2]),\n .Q(four_dec_min_limit[2]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE #(\n .INIT(1'b0)) \n \\four_dec_min_limit_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(four_dec_min_limit_nxt[3]),\n .Q(four_dec_min_limit[3]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE #(\n .INIT(1'b0)) \n \\four_dec_min_limit_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(four_dec_min_limit_nxt[4]),\n .Q(four_dec_min_limit[4]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE #(\n .INIT(1'b0)) \n \\four_dec_min_limit_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(four_dec_min_limit_nxt[5]),\n .Q(four_dec_min_limit[5]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n CARRY4 \\four_dec_min_limit_reg[5]_i_1 \n (.CI(1'b0),\n .CO({\\four_dec_min_limit_reg[5]_i_1_n_0 ,\\four_dec_min_limit_reg[5]_i_1_n_1 ,\\four_dec_min_limit_reg[5]_i_1_n_2 ,\\four_dec_min_limit_reg[5]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({three_dec_max_limit[5:3],1'b0}),\n .O(four_dec_min_limit_nxt[5:2]),\n .S({\\four_dec_min_limit[5]_i_2_n_0 ,\\four_dec_min_limit[5]_i_3_n_0 ,\\four_dec_min_limit[5]_i_4_n_0 ,\\four_dec_min_limit[5]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\four_dec_min_limit_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(four_dec_min_limit_nxt[6]),\n .Q(four_dec_min_limit[6]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE #(\n .INIT(1'b0)) \n \\four_dec_min_limit_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(four_dec_min_limit_nxt[7]),\n .Q(four_dec_min_limit[7]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE #(\n .INIT(1'b0)) \n \\four_dec_min_limit_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(four_dec_min_limit_nxt[8]),\n .Q(four_dec_min_limit[8]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE #(\n .INIT(1'b0)) \n \\four_dec_min_limit_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(four_dec_min_limit_nxt[9]),\n .Q(four_dec_min_limit[9]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n CARRY4 \\four_dec_min_limit_reg[9]_i_1 \n (.CI(\\four_dec_min_limit_reg[5]_i_1_n_0 ),\n .CO({\\four_dec_min_limit_reg[9]_i_1_n_0 ,\\four_dec_min_limit_reg[9]_i_1_n_1 ,\\four_dec_min_limit_reg[9]_i_1_n_2 ,\\four_dec_min_limit_reg[9]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI(three_dec_max_limit[9:6]),\n .O(four_dec_min_limit_nxt[9:6]),\n .S({\\four_dec_min_limit[9]_i_2_n_0 ,\\four_dec_min_limit[9]_i_3_n_0 ,\\four_dec_min_limit[9]_i_4_n_0 ,\\four_dec_min_limit[9]_i_5_n_0 }));\n LUT1 #(\n .INIT(2'h1)) \n \\four_inc_max_limit[11]_i_2 \n (.I0(device_temp_init[11]),\n .O(\\four_inc_max_limit[11]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\four_inc_max_limit[11]_i_3 \n (.I0(device_temp_init[10]),\n .O(\\four_inc_max_limit[11]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\four_inc_max_limit[11]_i_4 \n (.I0(device_temp_init[9]),\n .O(\\four_inc_max_limit[11]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\four_inc_max_limit[1]_i_2 \n (.I0(device_temp_init[1]),\n .O(\\four_inc_max_limit[1]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\four_inc_max_limit[4]_i_2 \n (.I0(device_temp_init[4]),\n .O(\\four_inc_max_limit[4]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\four_inc_max_limit[4]_i_3 \n (.I0(device_temp_init[3]),\n .O(\\four_inc_max_limit[4]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\four_inc_max_limit[4]_i_4 \n (.I0(device_temp_init[2]),\n .O(\\four_inc_max_limit[4]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\four_inc_max_limit[4]_i_5 \n (.I0(device_temp_init[1]),\n .O(\\four_inc_max_limit[4]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\four_inc_max_limit[8]_i_2 \n (.I0(device_temp_init[8]),\n .O(\\four_inc_max_limit[8]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\four_inc_max_limit[8]_i_3 \n (.I0(device_temp_init[7]),\n .O(\\four_inc_max_limit[8]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\four_inc_max_limit[8]_i_4 \n (.I0(device_temp_init[6]),\n .O(\\four_inc_max_limit[8]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\four_inc_max_limit[8]_i_5 \n (.I0(device_temp_init[5]),\n .O(\\four_inc_max_limit[8]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\four_inc_max_limit_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(four_inc_max_limit_nxt[10]),\n .Q(four_inc_max_limit[10]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE #(\n .INIT(1'b0)) \n \\four_inc_max_limit_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(four_inc_max_limit_nxt[11]),\n .Q(four_inc_max_limit[11]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n CARRY4 \\four_inc_max_limit_reg[11]_i_1 \n (.CI(\\four_inc_max_limit_reg[8]_i_1_n_0 ),\n .CO({\\NLW_four_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\\four_inc_max_limit_reg[11]_i_1_n_2 ,\\four_inc_max_limit_reg[11]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,device_temp_init[10],1'b0}),\n .O({\\NLW_four_inc_max_limit_reg[11]_i_1_O_UNCONNECTED [3],four_inc_max_limit_nxt[11:9]}),\n .S({1'b0,\\four_inc_max_limit[11]_i_2_n_0 ,\\four_inc_max_limit[11]_i_3_n_0 ,\\four_inc_max_limit[11]_i_4_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\four_inc_max_limit_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(four_inc_max_limit_nxt[1]),\n .Q(four_inc_max_limit[1]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n (* XILINX_LEGACY_PRIM = \"(MUXCY,XORCY)\" *) \n CARRY4 \\four_inc_max_limit_reg[1]_i_1_CARRY4 \n (.CI(1'b0),\n .CO(\\NLW_four_inc_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED [3:0]),\n .CYINIT(device_temp_init[0]),\n .DI(\\NLW_four_inc_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED [3:0]),\n .O({\\NLW_four_inc_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED [3:1],four_inc_max_limit_nxt[1]}),\n .S({\\NLW_four_inc_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED [3:1],\\four_inc_max_limit[1]_i_2_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\four_inc_max_limit_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(four_inc_max_limit_nxt[2]),\n .Q(four_inc_max_limit[2]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE #(\n .INIT(1'b0)) \n \\four_inc_max_limit_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(four_inc_max_limit_nxt[3]),\n .Q(four_inc_max_limit[3]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE #(\n .INIT(1'b0)) \n \\four_inc_max_limit_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(four_inc_max_limit_nxt[4]),\n .Q(four_inc_max_limit[4]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n CARRY4 \\four_inc_max_limit_reg[4]_i_1 \n (.CI(1'b0),\n .CO({\\four_inc_max_limit_reg[4]_i_1_n_0 ,\\four_inc_max_limit_reg[4]_i_1_n_1 ,\\four_inc_max_limit_reg[4]_i_1_n_2 ,\\four_inc_max_limit_reg[4]_i_1_n_3 }),\n .CYINIT(device_temp_init[0]),\n .DI(device_temp_init[4:1]),\n .O({four_inc_max_limit_nxt[4:2],two_inc_max_limit_nxt[1]}),\n .S({\\four_inc_max_limit[4]_i_2_n_0 ,\\four_inc_max_limit[4]_i_3_n_0 ,\\four_inc_max_limit[4]_i_4_n_0 ,\\four_inc_max_limit[4]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\four_inc_max_limit_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(four_inc_max_limit_nxt[5]),\n .Q(four_inc_max_limit[5]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE #(\n .INIT(1'b0)) \n \\four_inc_max_limit_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(four_inc_max_limit_nxt[6]),\n .Q(four_inc_max_limit[6]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE #(\n .INIT(1'b0)) \n \\four_inc_max_limit_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(four_inc_max_limit_nxt[7]),\n .Q(four_inc_max_limit[7]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE #(\n .INIT(1'b0)) \n \\four_inc_max_limit_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(four_inc_max_limit_nxt[8]),\n .Q(four_inc_max_limit[8]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n CARRY4 \\four_inc_max_limit_reg[8]_i_1 \n (.CI(\\four_inc_max_limit_reg[4]_i_1_n_0 ),\n .CO({\\four_inc_max_limit_reg[8]_i_1_n_0 ,\\four_inc_max_limit_reg[8]_i_1_n_1 ,\\four_inc_max_limit_reg[8]_i_1_n_2 ,\\four_inc_max_limit_reg[8]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,device_temp_init[7],1'b0,device_temp_init[5]}),\n .O(four_inc_max_limit_nxt[8:5]),\n .S({\\four_inc_max_limit[8]_i_2_n_0 ,\\four_inc_max_limit[8]_i_3_n_0 ,\\four_inc_max_limit[8]_i_4_n_0 ,\\four_inc_max_limit[8]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\four_inc_max_limit_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(four_inc_max_limit_nxt[9]),\n .Q(four_inc_max_limit[9]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n (* SOFT_HLUTNM = \"soft_lutpair254\" *) \n LUT4 #(\n .INIT(16'hFE00)) \n \\gen_byte_sel_div1.byte_sel_cnt[2]_i_2 \n (.I0(tempmon_pi_f_inc),\n .I1(tempmon_pi_f_dec),\n .I2(oclkdelay_calib_done_r_reg),\n .I3(ck_addr_cmd_delay_done),\n .O(\\gen_byte_sel_div1.byte_sel_cnt_reg[0] ));\n LUT6 #(\n .INIT(64'hFDFFFDFDFFFFFFFF)) \n \\gen_byte_sel_div1.calib_in_common_i_4 \n (.I0(cmd_delay_start0),\n .I1(tempmon_pi_f_inc),\n .I2(tempmon_pi_f_dec),\n .I3(fine_adjust_done_r_reg),\n .I4(rd_data_offset_cal_done),\n .I5(ck_addr_cmd_delay_done),\n .O(\\gen_byte_sel_div1.calib_in_common_reg ));\n LUT1 #(\n .INIT(2'h2)) \n \\neutral_max_limit[11]_i_2 \n (.I0(device_temp_init[11]),\n .O(\\neutral_max_limit[11]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\neutral_max_limit[11]_i_3 \n (.I0(device_temp_init[10]),\n .O(\\neutral_max_limit[11]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\neutral_max_limit[11]_i_4 \n (.I0(device_temp_init[9]),\n .O(\\neutral_max_limit[11]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\neutral_max_limit[4]_i_2 \n (.I0(device_temp_init[4]),\n .O(\\neutral_max_limit[4]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\neutral_max_limit[4]_i_3 \n (.I0(device_temp_init[3]),\n .O(\\neutral_max_limit[4]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\neutral_max_limit[4]_i_4 \n (.I0(device_temp_init[2]),\n .O(\\neutral_max_limit[4]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\neutral_max_limit[4]_i_5 \n (.I0(device_temp_init[1]),\n .O(\\neutral_max_limit[4]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\neutral_max_limit[8]_i_2 \n (.I0(device_temp_init[8]),\n .O(\\neutral_max_limit[8]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\neutral_max_limit[8]_i_3 \n (.I0(device_temp_init[7]),\n .O(\\neutral_max_limit[8]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\neutral_max_limit[8]_i_4 \n (.I0(device_temp_init[6]),\n .O(\\neutral_max_limit[8]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\neutral_max_limit[8]_i_5 \n (.I0(device_temp_init[5]),\n .O(\\neutral_max_limit[8]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\neutral_max_limit_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_max_limit_nxt[10]),\n .Q(neutral_max_limit[10]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE #(\n .INIT(1'b0)) \n \\neutral_max_limit_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_max_limit_nxt[11]),\n .Q(neutral_max_limit[11]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n CARRY4 \\neutral_max_limit_reg[11]_i_1 \n (.CI(\\neutral_max_limit_reg[8]_i_1_n_0 ),\n .CO({\\NLW_neutral_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\\neutral_max_limit_reg[11]_i_1_n_2 ,\\neutral_max_limit_reg[11]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\NLW_neutral_max_limit_reg[11]_i_1_O_UNCONNECTED [3],neutral_max_limit_nxt[11:9]}),\n .S({1'b0,\\neutral_max_limit[11]_i_2_n_0 ,\\neutral_max_limit[11]_i_3_n_0 ,\\neutral_max_limit[11]_i_4_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\neutral_max_limit_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_max_limit_nxt[1]),\n .Q(neutral_max_limit[1]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n (* XILINX_LEGACY_PRIM = \"(MUXCY,XORCY)\" *) \n CARRY4 \\neutral_max_limit_reg[1]_i_1_CARRY4 \n (.CI(1'b0),\n .CO(\\NLW_neutral_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED [3:0]),\n .CYINIT(device_temp_init[0]),\n .DI(\\NLW_neutral_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED [3:0]),\n .O({\\NLW_neutral_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED [3:1],neutral_max_limit_nxt[1]}),\n .S({\\NLW_neutral_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED [3:1],\\four_inc_max_limit[1]_i_2_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\neutral_max_limit_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_max_limit_nxt[2]),\n .Q(neutral_max_limit[2]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE #(\n .INIT(1'b0)) \n \\neutral_max_limit_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_max_limit_nxt[3]),\n .Q(neutral_max_limit[3]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE #(\n .INIT(1'b0)) \n \\neutral_max_limit_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_max_limit_nxt[4]),\n .Q(neutral_max_limit[4]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n CARRY4 \\neutral_max_limit_reg[4]_i_1 \n (.CI(1'b0),\n .CO({\\neutral_max_limit_reg[4]_i_1_n_0 ,\\neutral_max_limit_reg[4]_i_1_n_1 ,\\neutral_max_limit_reg[4]_i_1_n_2 ,\\neutral_max_limit_reg[4]_i_1_n_3 }),\n .CYINIT(device_temp_init[0]),\n .DI({device_temp_init[4],1'b0,device_temp_init[2:1]}),\n .O({neutral_max_limit_nxt[4:2],\\NLW_neutral_max_limit_reg[4]_i_1_O_UNCONNECTED [0]}),\n .S({\\neutral_max_limit[4]_i_2_n_0 ,\\neutral_max_limit[4]_i_3_n_0 ,\\neutral_max_limit[4]_i_4_n_0 ,\\neutral_max_limit[4]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\neutral_max_limit_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_max_limit_nxt[5]),\n .Q(neutral_max_limit[5]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE #(\n .INIT(1'b0)) \n \\neutral_max_limit_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_max_limit_nxt[6]),\n .Q(neutral_max_limit[6]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE #(\n .INIT(1'b0)) \n \\neutral_max_limit_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_max_limit_nxt[7]),\n .Q(neutral_max_limit[7]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE #(\n .INIT(1'b0)) \n \\neutral_max_limit_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_max_limit_nxt[8]),\n .Q(neutral_max_limit[8]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n CARRY4 \\neutral_max_limit_reg[8]_i_1 \n (.CI(\\neutral_max_limit_reg[4]_i_1_n_0 ),\n .CO({\\neutral_max_limit_reg[8]_i_1_n_0 ,\\neutral_max_limit_reg[8]_i_1_n_1 ,\\neutral_max_limit_reg[8]_i_1_n_2 ,\\neutral_max_limit_reg[8]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,device_temp_init[6:5]}),\n .O(neutral_max_limit_nxt[8:5]),\n .S({\\neutral_max_limit[8]_i_2_n_0 ,\\neutral_max_limit[8]_i_3_n_0 ,\\neutral_max_limit[8]_i_4_n_0 ,\\neutral_max_limit[8]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\neutral_max_limit_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_max_limit_nxt[9]),\n .Q(neutral_max_limit[9]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n LUT1 #(\n .INIT(2'h1)) \n \\neutral_min_limit[11]_i_2 \n (.I0(one_inc_max_limit[11]),\n .O(\\neutral_min_limit[11]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\neutral_min_limit[11]_i_3 \n (.I0(one_inc_max_limit[10]),\n .O(\\neutral_min_limit[11]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\neutral_min_limit[5]_i_2 \n (.I0(one_inc_max_limit[5]),\n .O(\\neutral_min_limit[5]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\neutral_min_limit[5]_i_3 \n (.I0(one_inc_max_limit[4]),\n .O(\\neutral_min_limit[5]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\neutral_min_limit[5]_i_4 \n (.I0(one_inc_max_limit[3]),\n .O(\\neutral_min_limit[5]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\neutral_min_limit[5]_i_5 \n (.I0(one_inc_max_limit[2]),\n .O(\\neutral_min_limit[5]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\neutral_min_limit[9]_i_2 \n (.I0(one_inc_max_limit[9]),\n .O(\\neutral_min_limit[9]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\neutral_min_limit[9]_i_3 \n (.I0(one_inc_max_limit[8]),\n .O(\\neutral_min_limit[9]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\neutral_min_limit[9]_i_4 \n (.I0(one_inc_max_limit[7]),\n .O(\\neutral_min_limit[9]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\neutral_min_limit[9]_i_5 \n (.I0(one_inc_max_limit[6]),\n .O(\\neutral_min_limit[9]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\neutral_min_limit_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_min_limit_nxt[10]),\n .Q(neutral_min_limit[10]),\n .R(SS));\n FDRE #(\n .INIT(1'b0)) \n \\neutral_min_limit_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_min_limit_nxt[11]),\n .Q(neutral_min_limit[11]),\n .R(SS));\n CARRY4 \\neutral_min_limit_reg[11]_i_1 \n (.CI(\\neutral_min_limit_reg[9]_i_1_n_0 ),\n .CO({\\NLW_neutral_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\\neutral_min_limit_reg[11]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,one_inc_max_limit[10]}),\n .O({\\NLW_neutral_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],neutral_min_limit_nxt[11:10]}),\n .S({1'b0,1'b0,\\neutral_min_limit[11]_i_2_n_0 ,\\neutral_min_limit[11]_i_3_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\neutral_min_limit_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_max_limit[1]),\n .Q(neutral_min_limit[1]),\n .R(SS));\n FDRE #(\n .INIT(1'b0)) \n \\neutral_min_limit_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_min_limit_nxt[2]),\n .Q(neutral_min_limit[2]),\n .R(SS));\n FDRE #(\n .INIT(1'b0)) \n \\neutral_min_limit_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_min_limit_nxt[3]),\n .Q(neutral_min_limit[3]),\n .R(SS));\n FDRE #(\n .INIT(1'b0)) \n \\neutral_min_limit_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_min_limit_nxt[4]),\n .Q(neutral_min_limit[4]),\n .R(SS));\n FDRE #(\n .INIT(1'b0)) \n \\neutral_min_limit_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_min_limit_nxt[5]),\n .Q(neutral_min_limit[5]),\n .R(SS));\n CARRY4 \\neutral_min_limit_reg[5]_i_1 \n (.CI(1'b0),\n .CO({\\neutral_min_limit_reg[5]_i_1_n_0 ,\\neutral_min_limit_reg[5]_i_1_n_1 ,\\neutral_min_limit_reg[5]_i_1_n_2 ,\\neutral_min_limit_reg[5]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({one_inc_max_limit[5:3],1'b0}),\n .O(neutral_min_limit_nxt[5:2]),\n .S({\\neutral_min_limit[5]_i_2_n_0 ,\\neutral_min_limit[5]_i_3_n_0 ,\\neutral_min_limit[5]_i_4_n_0 ,\\neutral_min_limit[5]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\neutral_min_limit_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_min_limit_nxt[6]),\n .Q(neutral_min_limit[6]),\n .R(SS));\n FDRE #(\n .INIT(1'b0)) \n \\neutral_min_limit_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_min_limit_nxt[7]),\n .Q(neutral_min_limit[7]),\n .R(SS));\n FDRE #(\n .INIT(1'b0)) \n \\neutral_min_limit_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_min_limit_nxt[8]),\n .Q(neutral_min_limit[8]),\n .R(SS));\n FDRE #(\n .INIT(1'b0)) \n \\neutral_min_limit_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_min_limit_nxt[9]),\n .Q(neutral_min_limit[9]),\n .R(SS));\n CARRY4 \\neutral_min_limit_reg[9]_i_1 \n (.CI(\\neutral_min_limit_reg[5]_i_1_n_0 ),\n .CO({\\neutral_min_limit_reg[9]_i_1_n_0 ,\\neutral_min_limit_reg[9]_i_1_n_1 ,\\neutral_min_limit_reg[9]_i_1_n_2 ,\\neutral_min_limit_reg[9]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI(one_inc_max_limit[9:6]),\n .O(neutral_min_limit_nxt[9:6]),\n .S({\\neutral_min_limit[9]_i_2_n_0 ,\\neutral_min_limit[9]_i_3_n_0 ,\\neutral_min_limit[9]_i_4_n_0 ,\\neutral_min_limit[9]_i_5_n_0 }));\n LUT1 #(\n .INIT(2'h2)) \n \\one_dec_max_limit[11]_i_2 \n (.I0(device_temp_init[11]),\n .O(\\one_dec_max_limit[11]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\one_dec_max_limit[11]_i_3 \n (.I0(device_temp_init[10]),\n .O(\\one_dec_max_limit[11]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\one_dec_max_limit[11]_i_4 \n (.I0(device_temp_init[9]),\n .O(\\one_dec_max_limit[11]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\one_dec_max_limit[4]_i_2 \n (.I0(device_temp_init[4]),\n .O(\\one_dec_max_limit[4]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\one_dec_max_limit[4]_i_3 \n (.I0(device_temp_init[3]),\n .O(\\one_dec_max_limit[4]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_dec_max_limit[4]_i_4 \n (.I0(device_temp_init[2]),\n .O(\\one_dec_max_limit[4]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\one_dec_max_limit[4]_i_5 \n (.I0(device_temp_init[1]),\n .O(\\one_dec_max_limit[4]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_dec_max_limit[8]_i_2 \n (.I0(device_temp_init[8]),\n .O(\\one_dec_max_limit[8]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\one_dec_max_limit[8]_i_3 \n (.I0(device_temp_init[7]),\n .O(\\one_dec_max_limit[8]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_dec_max_limit[8]_i_4 \n (.I0(device_temp_init[6]),\n .O(\\one_dec_max_limit[8]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_dec_max_limit[8]_i_5 \n (.I0(device_temp_init[5]),\n .O(\\one_dec_max_limit[8]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\one_dec_max_limit_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_max_limit_nxt[10]),\n .Q(one_dec_max_limit[10]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE #(\n .INIT(1'b0)) \n \\one_dec_max_limit_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_max_limit_nxt[11]),\n .Q(one_dec_max_limit[11]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n CARRY4 \\one_dec_max_limit_reg[11]_i_1 \n (.CI(\\one_dec_max_limit_reg[8]_i_1_n_0 ),\n .CO({\\NLW_one_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\\one_dec_max_limit_reg[11]_i_1_n_2 ,\\one_dec_max_limit_reg[11]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\NLW_one_dec_max_limit_reg[11]_i_1_O_UNCONNECTED [3],one_dec_max_limit_nxt[11:9]}),\n .S({1'b0,\\one_dec_max_limit[11]_i_2_n_0 ,\\one_dec_max_limit[11]_i_3_n_0 ,\\one_dec_max_limit[11]_i_4_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\one_dec_max_limit_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_max_limit_nxt[1]),\n .Q(one_dec_max_limit[1]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n (* XILINX_LEGACY_PRIM = \"(MUXCY,XORCY)\" *) \n CARRY4 \\one_dec_max_limit_reg[1]_i_1_CARRY4 \n (.CI(1'b0),\n .CO(\\NLW_one_dec_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED [3:0]),\n .CYINIT(device_temp_init[0]),\n .DI(\\NLW_one_dec_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED [3:0]),\n .O({\\NLW_one_dec_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED [3:1],one_dec_max_limit_nxt[1]}),\n .S({\\NLW_one_dec_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED [3:1],device_temp_init[1]}));\n FDRE #(\n .INIT(1'b0)) \n \\one_dec_max_limit_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_max_limit_nxt[2]),\n .Q(one_dec_max_limit[2]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE #(\n .INIT(1'b0)) \n \\one_dec_max_limit_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_max_limit_nxt[3]),\n .Q(one_dec_max_limit[3]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE #(\n .INIT(1'b0)) \n \\one_dec_max_limit_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_max_limit_nxt[4]),\n .Q(one_dec_max_limit[4]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n CARRY4 \\one_dec_max_limit_reg[4]_i_1 \n (.CI(1'b0),\n .CO({\\one_dec_max_limit_reg[4]_i_1_n_0 ,\\one_dec_max_limit_reg[4]_i_1_n_1 ,\\one_dec_max_limit_reg[4]_i_1_n_2 ,\\one_dec_max_limit_reg[4]_i_1_n_3 }),\n .CYINIT(device_temp_init[0]),\n .DI({1'b0,1'b0,device_temp_init[2],1'b0}),\n .O({one_dec_max_limit_nxt[4:2],\\NLW_one_dec_max_limit_reg[4]_i_1_O_UNCONNECTED [0]}),\n .S({\\one_dec_max_limit[4]_i_2_n_0 ,\\one_dec_max_limit[4]_i_3_n_0 ,\\one_dec_max_limit[4]_i_4_n_0 ,\\one_dec_max_limit[4]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\one_dec_max_limit_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_max_limit_nxt[5]),\n .Q(one_dec_max_limit[5]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE #(\n .INIT(1'b0)) \n \\one_dec_max_limit_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_max_limit_nxt[6]),\n .Q(one_dec_max_limit[6]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE #(\n .INIT(1'b0)) \n \\one_dec_max_limit_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_max_limit_nxt[7]),\n .Q(one_dec_max_limit[7]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE #(\n .INIT(1'b0)) \n \\one_dec_max_limit_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_max_limit_nxt[8]),\n .Q(one_dec_max_limit[8]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n CARRY4 \\one_dec_max_limit_reg[8]_i_1 \n (.CI(\\one_dec_max_limit_reg[4]_i_1_n_0 ),\n .CO({\\one_dec_max_limit_reg[8]_i_1_n_0 ,\\one_dec_max_limit_reg[8]_i_1_n_1 ,\\one_dec_max_limit_reg[8]_i_1_n_2 ,\\one_dec_max_limit_reg[8]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({device_temp_init[8],1'b0,device_temp_init[6:5]}),\n .O(one_dec_max_limit_nxt[8:5]),\n .S({\\one_dec_max_limit[8]_i_2_n_0 ,\\one_dec_max_limit[8]_i_3_n_0 ,\\one_dec_max_limit[8]_i_4_n_0 ,\\one_dec_max_limit[8]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\one_dec_max_limit_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_max_limit_nxt[9]),\n .Q(one_dec_max_limit[9]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n LUT1 #(\n .INIT(2'h1)) \n \\one_dec_min_limit[11]_i_2 \n (.I0(neutral_max_limit[11]),\n .O(\\one_dec_min_limit[11]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_dec_min_limit[11]_i_3 \n (.I0(neutral_max_limit[10]),\n .O(\\one_dec_min_limit[11]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_dec_min_limit[5]_i_2 \n (.I0(neutral_max_limit[5]),\n .O(\\one_dec_min_limit[5]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_dec_min_limit[5]_i_3 \n (.I0(neutral_max_limit[4]),\n .O(\\one_dec_min_limit[5]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_dec_min_limit[5]_i_4 \n (.I0(neutral_max_limit[3]),\n .O(\\one_dec_min_limit[5]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\one_dec_min_limit[5]_i_5 \n (.I0(neutral_max_limit[2]),\n .O(\\one_dec_min_limit[5]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_dec_min_limit[9]_i_2 \n (.I0(neutral_max_limit[9]),\n .O(\\one_dec_min_limit[9]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_dec_min_limit[9]_i_3 \n (.I0(neutral_max_limit[8]),\n .O(\\one_dec_min_limit[9]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_dec_min_limit[9]_i_4 \n (.I0(neutral_max_limit[7]),\n .O(\\one_dec_min_limit[9]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_dec_min_limit[9]_i_5 \n (.I0(neutral_max_limit[6]),\n .O(\\one_dec_min_limit[9]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\one_dec_min_limit_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_min_limit_nxt[10]),\n .Q(one_dec_min_limit[10]),\n .R(SS));\n FDRE #(\n .INIT(1'b0)) \n \\one_dec_min_limit_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_min_limit_nxt[11]),\n .Q(one_dec_min_limit[11]),\n .R(SS));\n CARRY4 \\one_dec_min_limit_reg[11]_i_1 \n (.CI(\\one_dec_min_limit_reg[9]_i_1_n_0 ),\n .CO({\\NLW_one_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\\one_dec_min_limit_reg[11]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,neutral_max_limit[10]}),\n .O({\\NLW_one_dec_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],one_dec_min_limit_nxt[11:10]}),\n .S({1'b0,1'b0,\\one_dec_min_limit[11]_i_2_n_0 ,\\one_dec_min_limit[11]_i_3_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\one_dec_min_limit_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_max_limit[1]),\n .Q(one_dec_min_limit[1]),\n .R(SS));\n FDRE #(\n .INIT(1'b0)) \n \\one_dec_min_limit_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_min_limit_nxt[2]),\n .Q(one_dec_min_limit[2]),\n .R(SS));\n FDRE #(\n .INIT(1'b0)) \n \\one_dec_min_limit_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_min_limit_nxt[3]),\n .Q(one_dec_min_limit[3]),\n .R(SS));\n FDRE #(\n .INIT(1'b0)) \n \\one_dec_min_limit_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_min_limit_nxt[4]),\n .Q(one_dec_min_limit[4]),\n .R(SS));\n FDRE #(\n .INIT(1'b0)) \n \\one_dec_min_limit_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_min_limit_nxt[5]),\n .Q(one_dec_min_limit[5]),\n .R(SS));\n CARRY4 \\one_dec_min_limit_reg[5]_i_1 \n (.CI(1'b0),\n .CO({\\one_dec_min_limit_reg[5]_i_1_n_0 ,\\one_dec_min_limit_reg[5]_i_1_n_1 ,\\one_dec_min_limit_reg[5]_i_1_n_2 ,\\one_dec_min_limit_reg[5]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({neutral_max_limit[5:3],1'b0}),\n .O(one_dec_min_limit_nxt[5:2]),\n .S({\\one_dec_min_limit[5]_i_2_n_0 ,\\one_dec_min_limit[5]_i_3_n_0 ,\\one_dec_min_limit[5]_i_4_n_0 ,\\one_dec_min_limit[5]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\one_dec_min_limit_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_min_limit_nxt[6]),\n .Q(one_dec_min_limit[6]),\n .R(SS));\n FDRE #(\n .INIT(1'b0)) \n \\one_dec_min_limit_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_min_limit_nxt[7]),\n .Q(one_dec_min_limit[7]),\n .R(SS));\n FDRE #(\n .INIT(1'b0)) \n \\one_dec_min_limit_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_min_limit_nxt[8]),\n .Q(one_dec_min_limit[8]),\n .R(SS));\n FDRE #(\n .INIT(1'b0)) \n \\one_dec_min_limit_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_min_limit_nxt[9]),\n .Q(one_dec_min_limit[9]),\n .R(SS));\n CARRY4 \\one_dec_min_limit_reg[9]_i_1 \n (.CI(\\one_dec_min_limit_reg[5]_i_1_n_0 ),\n .CO({\\one_dec_min_limit_reg[9]_i_1_n_0 ,\\one_dec_min_limit_reg[9]_i_1_n_1 ,\\one_dec_min_limit_reg[9]_i_1_n_2 ,\\one_dec_min_limit_reg[9]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI(neutral_max_limit[9:6]),\n .O(one_dec_min_limit_nxt[9:6]),\n .S({\\one_dec_min_limit[9]_i_2_n_0 ,\\one_dec_min_limit[9]_i_3_n_0 ,\\one_dec_min_limit[9]_i_4_n_0 ,\\one_dec_min_limit[9]_i_5_n_0 }));\n LUT1 #(\n .INIT(2'h1)) \n \\one_inc_max_limit[11]_i_2 \n (.I0(device_temp_init[11]),\n .O(\\one_inc_max_limit[11]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_inc_max_limit[11]_i_3 \n (.I0(device_temp_init[10]),\n .O(\\one_inc_max_limit[11]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_inc_max_limit[11]_i_4 \n (.I0(device_temp_init[9]),\n .O(\\one_inc_max_limit[11]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\one_inc_max_limit[4]_i_2 \n (.I0(device_temp_init[4]),\n .O(\\one_inc_max_limit[4]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_inc_max_limit[4]_i_3 \n (.I0(device_temp_init[3]),\n .O(\\one_inc_max_limit[4]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\one_inc_max_limit[4]_i_4 \n (.I0(device_temp_init[2]),\n .O(\\one_inc_max_limit[4]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\one_inc_max_limit[4]_i_5 \n (.I0(device_temp_init[1]),\n .O(\\one_inc_max_limit[4]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_inc_max_limit[8]_i_2 \n (.I0(device_temp_init[8]),\n .O(\\one_inc_max_limit[8]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_inc_max_limit[8]_i_3 \n (.I0(device_temp_init[7]),\n .O(\\one_inc_max_limit[8]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\one_inc_max_limit[8]_i_4 \n (.I0(device_temp_init[6]),\n .O(\\one_inc_max_limit[8]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\one_inc_max_limit[8]_i_5 \n (.I0(device_temp_init[5]),\n .O(\\one_inc_max_limit[8]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\one_inc_max_limit_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_max_limit_nxt[10]),\n .Q(one_inc_max_limit[10]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE #(\n .INIT(1'b0)) \n \\one_inc_max_limit_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_max_limit_nxt[11]),\n .Q(one_inc_max_limit[11]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n CARRY4 \\one_inc_max_limit_reg[11]_i_1 \n (.CI(\\one_inc_max_limit_reg[8]_i_1_n_0 ),\n .CO({\\NLW_one_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\\one_inc_max_limit_reg[11]_i_1_n_2 ,\\one_inc_max_limit_reg[11]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,device_temp_init[10:9]}),\n .O({\\NLW_one_inc_max_limit_reg[11]_i_1_O_UNCONNECTED [3],one_inc_max_limit_nxt[11:9]}),\n .S({1'b0,\\one_inc_max_limit[11]_i_2_n_0 ,\\one_inc_max_limit[11]_i_3_n_0 ,\\one_inc_max_limit[11]_i_4_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\one_inc_max_limit_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_max_limit_nxt[1]),\n .Q(one_inc_max_limit[1]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n (* XILINX_LEGACY_PRIM = \"(MUXCY,XORCY)\" *) \n CARRY4 \\one_inc_max_limit_reg[1]_i_1_CARRY4 \n (.CI(1'b0),\n .CO(\\NLW_one_inc_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED [3:0]),\n .CYINIT(device_temp_init[0]),\n .DI(\\NLW_one_inc_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED [3:0]),\n .O({\\NLW_one_inc_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED [3:1],one_inc_max_limit_nxt[1]}),\n .S({\\NLW_one_inc_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED [3:1],device_temp_init[1]}));\n FDRE #(\n .INIT(1'b0)) \n \\one_inc_max_limit_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_max_limit_nxt[2]),\n .Q(one_inc_max_limit[2]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE #(\n .INIT(1'b0)) \n \\one_inc_max_limit_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_max_limit_nxt[3]),\n .Q(one_inc_max_limit[3]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE #(\n .INIT(1'b0)) \n \\one_inc_max_limit_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_max_limit_nxt[4]),\n .Q(one_inc_max_limit[4]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n CARRY4 \\one_inc_max_limit_reg[4]_i_1 \n (.CI(1'b0),\n .CO({\\one_inc_max_limit_reg[4]_i_1_n_0 ,\\one_inc_max_limit_reg[4]_i_1_n_1 ,\\one_inc_max_limit_reg[4]_i_1_n_2 ,\\one_inc_max_limit_reg[4]_i_1_n_3 }),\n .CYINIT(device_temp_init[0]),\n .DI({1'b0,device_temp_init[3],1'b0,1'b0}),\n .O({one_inc_max_limit_nxt[4:2],\\NLW_one_inc_max_limit_reg[4]_i_1_O_UNCONNECTED [0]}),\n .S({\\one_inc_max_limit[4]_i_2_n_0 ,\\one_inc_max_limit[4]_i_3_n_0 ,\\one_inc_max_limit[4]_i_4_n_0 ,\\one_inc_max_limit[4]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\one_inc_max_limit_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_max_limit_nxt[5]),\n .Q(one_inc_max_limit[5]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE #(\n .INIT(1'b0)) \n \\one_inc_max_limit_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_max_limit_nxt[6]),\n .Q(one_inc_max_limit[6]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE #(\n .INIT(1'b0)) \n \\one_inc_max_limit_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_max_limit_nxt[7]),\n .Q(one_inc_max_limit[7]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE #(\n .INIT(1'b0)) \n \\one_inc_max_limit_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_max_limit_nxt[8]),\n .Q(one_inc_max_limit[8]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n CARRY4 \\one_inc_max_limit_reg[8]_i_1 \n (.CI(\\one_inc_max_limit_reg[4]_i_1_n_0 ),\n .CO({\\one_inc_max_limit_reg[8]_i_1_n_0 ,\\one_inc_max_limit_reg[8]_i_1_n_1 ,\\one_inc_max_limit_reg[8]_i_1_n_2 ,\\one_inc_max_limit_reg[8]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({device_temp_init[8:7],1'b0,1'b0}),\n .O(one_inc_max_limit_nxt[8:5]),\n .S({\\one_inc_max_limit[8]_i_2_n_0 ,\\one_inc_max_limit[8]_i_3_n_0 ,\\one_inc_max_limit[8]_i_4_n_0 ,\\one_inc_max_limit[8]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\one_inc_max_limit_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_max_limit_nxt[9]),\n .Q(one_inc_max_limit[9]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n LUT1 #(\n .INIT(2'h1)) \n \\one_inc_min_limit[11]_i_2 \n (.I0(two_inc_max_limit[11]),\n .O(\\one_inc_min_limit[11]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_inc_min_limit[11]_i_3 \n (.I0(two_inc_max_limit[10]),\n .O(\\one_inc_min_limit[11]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_inc_min_limit[5]_i_2 \n (.I0(two_inc_max_limit[5]),\n .O(\\one_inc_min_limit[5]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_inc_min_limit[5]_i_3 \n (.I0(two_inc_max_limit[4]),\n .O(\\one_inc_min_limit[5]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_inc_min_limit[5]_i_4 \n (.I0(two_inc_max_limit[3]),\n .O(\\one_inc_min_limit[5]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\one_inc_min_limit[5]_i_5 \n (.I0(two_inc_max_limit[2]),\n .O(\\one_inc_min_limit[5]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_inc_min_limit[9]_i_2 \n (.I0(two_inc_max_limit[9]),\n .O(\\one_inc_min_limit[9]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_inc_min_limit[9]_i_3 \n (.I0(two_inc_max_limit[8]),\n .O(\\one_inc_min_limit[9]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_inc_min_limit[9]_i_4 \n (.I0(two_inc_max_limit[7]),\n .O(\\one_inc_min_limit[9]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_inc_min_limit[9]_i_5 \n (.I0(two_inc_max_limit[6]),\n .O(\\one_inc_min_limit[9]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\one_inc_min_limit_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_min_limit_nxt[10]),\n .Q(one_inc_min_limit[10]),\n .R(SS));\n FDRE #(\n .INIT(1'b0)) \n \\one_inc_min_limit_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_min_limit_nxt[11]),\n .Q(one_inc_min_limit[11]),\n .R(SS));\n CARRY4 \\one_inc_min_limit_reg[11]_i_1 \n (.CI(\\one_inc_min_limit_reg[9]_i_1_n_0 ),\n .CO({\\NLW_one_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\\one_inc_min_limit_reg[11]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,two_inc_max_limit[10]}),\n .O({\\NLW_one_inc_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],one_inc_min_limit_nxt[11:10]}),\n .S({1'b0,1'b0,\\one_inc_min_limit[11]_i_2_n_0 ,\\one_inc_min_limit[11]_i_3_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\one_inc_min_limit_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_max_limit[1]),\n .Q(one_inc_min_limit[1]),\n .R(SS));\n FDRE #(\n .INIT(1'b0)) \n \\one_inc_min_limit_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_min_limit_nxt[2]),\n .Q(one_inc_min_limit[2]),\n .R(SS));\n FDRE #(\n .INIT(1'b0)) \n \\one_inc_min_limit_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_min_limit_nxt[3]),\n .Q(one_inc_min_limit[3]),\n .R(SS));\n FDRE #(\n .INIT(1'b0)) \n \\one_inc_min_limit_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_min_limit_nxt[4]),\n .Q(one_inc_min_limit[4]),\n .R(SS));\n FDRE #(\n .INIT(1'b0)) \n \\one_inc_min_limit_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_min_limit_nxt[5]),\n .Q(one_inc_min_limit[5]),\n .R(SS));\n CARRY4 \\one_inc_min_limit_reg[5]_i_1 \n (.CI(1'b0),\n .CO({\\one_inc_min_limit_reg[5]_i_1_n_0 ,\\one_inc_min_limit_reg[5]_i_1_n_1 ,\\one_inc_min_limit_reg[5]_i_1_n_2 ,\\one_inc_min_limit_reg[5]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({two_inc_max_limit[5:3],1'b0}),\n .O(one_inc_min_limit_nxt[5:2]),\n .S({\\one_inc_min_limit[5]_i_2_n_0 ,\\one_inc_min_limit[5]_i_3_n_0 ,\\one_inc_min_limit[5]_i_4_n_0 ,\\one_inc_min_limit[5]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\one_inc_min_limit_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_min_limit_nxt[6]),\n .Q(one_inc_min_limit[6]),\n .R(SS));\n FDRE #(\n .INIT(1'b0)) \n \\one_inc_min_limit_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_min_limit_nxt[7]),\n .Q(one_inc_min_limit[7]),\n .R(SS));\n FDRE #(\n .INIT(1'b0)) \n \\one_inc_min_limit_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_min_limit_nxt[8]),\n .Q(one_inc_min_limit[8]),\n .R(SS));\n FDRE #(\n .INIT(1'b0)) \n \\one_inc_min_limit_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_min_limit_nxt[9]),\n .Q(one_inc_min_limit[9]),\n .R(SS));\n CARRY4 \\one_inc_min_limit_reg[9]_i_1 \n (.CI(\\one_inc_min_limit_reg[5]_i_1_n_0 ),\n .CO({\\one_inc_min_limit_reg[9]_i_1_n_0 ,\\one_inc_min_limit_reg[9]_i_1_n_1 ,\\one_inc_min_limit_reg[9]_i_1_n_2 ,\\one_inc_min_limit_reg[9]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI(two_inc_max_limit[9:6]),\n .O(one_inc_min_limit_nxt[9:6]),\n .S({\\one_inc_min_limit[9]_i_2_n_0 ,\\one_inc_min_limit[9]_i_3_n_0 ,\\one_inc_min_limit[9]_i_4_n_0 ,\\one_inc_min_limit[9]_i_5_n_0 }));\n LUT4 #(\n .INIT(16'hF080)) \n pi_f_dec_i_1\n (.I0(update_temp_102),\n .I1(pi_f_dec_i_2_n_0),\n .I2(\\tempmon_state[10]_i_7_n_0 ),\n .I3(\\tempmon_state[10]_i_3_n_0 ),\n .O(pi_f_dec_nxt));\n LUT6 #(\n .INIT(64'hFFFFF888F888F888)) \n pi_f_dec_i_2\n (.I0(temp_cmp_three_inc_max_102),\n .I1(tempmon_state[3]),\n .I2(tempmon_state[5]),\n .I3(temp_cmp_one_inc_max_102),\n .I4(tempmon_state[4]),\n .I5(temp_cmp_two_inc_max_102),\n .O(pi_f_dec_i_2_n_0));\n FDRE #(\n .INIT(1'b0)) \n pi_f_dec_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_f_dec_nxt),\n .Q(tempmon_pi_f_dec),\n .R(SS));\n LUT6 #(\n .INIT(64'hEFEEEEEEEEEEEEEE)) \n pi_f_inc_i_1\n (.I0(pi_f_inc_i_2_n_0),\n .I1(pi_f_inc_i_3_n_0),\n .I2(temp_gte_three_dec_max),\n .I3(tempmon_state[9]),\n .I4(temp_cmp_three_dec_min_102),\n .I5(pi_f_inc_i_5_n_0),\n .O(pi_f_inc_nxt));\n LUT4 #(\n .INIT(16'h0800)) \n pi_f_inc_i_10\n (.I0(tempmon_state[5]),\n .I1(update_temp_102),\n .I2(temp_cmp_one_inc_max_102),\n .I3(temp_cmp_one_inc_min_102),\n .O(pi_f_inc_i_10_n_0));\n LUT6 #(\n .INIT(64'hFAEAEAEAEAEAEAEA)) \n pi_f_inc_i_2\n (.I0(pi_f_inc_i_6_n_0),\n .I1(pi_f_inc_i_7_n_0),\n .I2(\\tempmon_state[10]_i_7_n_0 ),\n .I3(tempmon_state[10]),\n .I4(temp_cmp_four_dec_min_102),\n .I5(update_temp_102),\n .O(pi_f_inc_i_2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair252\" *) \n LUT5 #(\n .INIT(32'h40000000)) \n pi_f_inc_i_3\n (.I0(temp_cmp_two_dec_max_102),\n .I1(tempmon_state[8]),\n .I2(temp_cmp_two_dec_min_102),\n .I3(update_temp_102),\n .I4(\\tempmon_state[10]_i_7_n_0 ),\n .O(pi_f_inc_i_3_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair251\" *) \n LUT2 #(\n .INIT(4'h8)) \n pi_f_inc_i_4\n (.I0(update_temp_102),\n .I1(temp_cmp_three_dec_max_102),\n .O(temp_gte_three_dec_max));\n (* SOFT_HLUTNM = \"soft_lutpair248\" *) \n LUT2 #(\n .INIT(4'h8)) \n pi_f_inc_i_5\n (.I0(\\tempmon_state[10]_i_7_n_0 ),\n .I1(update_temp_102),\n .O(pi_f_inc_i_5_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFF00008000)) \n pi_f_inc_i_6\n (.I0(\\tempmon_state[10]_i_7_n_0 ),\n .I1(update_temp_102),\n .I2(temp_cmp_one_dec_min_102),\n .I3(tempmon_state[7]),\n .I4(temp_cmp_one_dec_max_102),\n .I5(pi_f_inc_i_8_n_0),\n .O(pi_f_inc_i_6_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFFAAEAAAAA)) \n pi_f_inc_i_7\n (.I0(pi_f_inc_i_9_n_0),\n .I1(tempmon_state[4]),\n .I2(update_temp_102),\n .I3(temp_cmp_two_inc_max_102),\n .I4(temp_cmp_two_inc_min_102),\n .I5(pi_f_inc_i_10_n_0),\n .O(pi_f_inc_i_7_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair249\" *) \n LUT5 #(\n .INIT(32'h40000000)) \n pi_f_inc_i_8\n (.I0(temp_cmp_neutral_max_102),\n .I1(tempmon_state[6]),\n .I2(temp_cmp_neutral_min_102),\n .I3(update_temp_102),\n .I4(\\tempmon_state[10]_i_7_n_0 ),\n .O(pi_f_inc_i_8_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair255\" *) \n LUT4 #(\n .INIT(16'h0800)) \n pi_f_inc_i_9\n (.I0(tempmon_state[3]),\n .I1(update_temp_102),\n .I2(temp_cmp_three_inc_max_102),\n .I3(temp_cmp_three_inc_min_102),\n .O(pi_f_inc_i_9_n_0));\n FDRE #(\n .INIT(1'b0)) \n pi_f_inc_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_f_inc_nxt),\n .Q(tempmon_pi_f_inc),\n .R(rstdiv0_sync_r1_reg_rep__2));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_four_dec_min_102_i_10\n (.I0(four_dec_min_limit[0]),\n .I1(device_temp_101[0]),\n .I2(device_temp_101[1]),\n .I3(four_dec_min_limit[1]),\n .O(temp_cmp_four_dec_min_102_i_10_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_four_dec_min_102_i_11\n (.I0(four_dec_min_limit[6]),\n .I1(device_temp_101[6]),\n .I2(four_dec_min_limit[7]),\n .I3(device_temp_101[7]),\n .O(temp_cmp_four_dec_min_102_i_11_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_four_dec_min_102_i_12\n (.I0(four_dec_min_limit[4]),\n .I1(device_temp_101[4]),\n .I2(four_dec_min_limit[5]),\n .I3(device_temp_101[5]),\n .O(temp_cmp_four_dec_min_102_i_12_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_four_dec_min_102_i_13\n (.I0(four_dec_min_limit[2]),\n .I1(device_temp_101[2]),\n .I2(four_dec_min_limit[3]),\n .I3(device_temp_101[3]),\n .O(temp_cmp_four_dec_min_102_i_13_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_four_dec_min_102_i_14\n (.I0(four_dec_min_limit[0]),\n .I1(device_temp_101[0]),\n .I2(four_dec_min_limit[1]),\n .I3(device_temp_101[1]),\n .O(temp_cmp_four_dec_min_102_i_14_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_four_dec_min_102_i_3\n (.I0(four_dec_min_limit[10]),\n .I1(device_temp_101[10]),\n .I2(device_temp_101[11]),\n .I3(four_dec_min_limit[11]),\n .O(temp_cmp_four_dec_min_102_i_3_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_four_dec_min_102_i_4\n (.I0(four_dec_min_limit[8]),\n .I1(device_temp_101[8]),\n .I2(device_temp_101[9]),\n .I3(four_dec_min_limit[9]),\n .O(temp_cmp_four_dec_min_102_i_4_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_four_dec_min_102_i_5\n (.I0(four_dec_min_limit[10]),\n .I1(device_temp_101[10]),\n .I2(four_dec_min_limit[11]),\n .I3(device_temp_101[11]),\n .O(temp_cmp_four_dec_min_102_i_5_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_four_dec_min_102_i_6\n (.I0(four_dec_min_limit[8]),\n .I1(device_temp_101[8]),\n .I2(four_dec_min_limit[9]),\n .I3(device_temp_101[9]),\n .O(temp_cmp_four_dec_min_102_i_6_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_four_dec_min_102_i_7\n (.I0(four_dec_min_limit[6]),\n .I1(device_temp_101[6]),\n .I2(device_temp_101[7]),\n .I3(four_dec_min_limit[7]),\n .O(temp_cmp_four_dec_min_102_i_7_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_four_dec_min_102_i_8\n (.I0(four_dec_min_limit[4]),\n .I1(device_temp_101[4]),\n .I2(device_temp_101[5]),\n .I3(four_dec_min_limit[5]),\n .O(temp_cmp_four_dec_min_102_i_8_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_four_dec_min_102_i_9\n (.I0(four_dec_min_limit[2]),\n .I1(device_temp_101[2]),\n .I2(device_temp_101[3]),\n .I3(four_dec_min_limit[3]),\n .O(temp_cmp_four_dec_min_102_i_9_n_0));\n FDRE #(\n .INIT(1'b0)) \n temp_cmp_four_dec_min_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(temp_cmp_four_dec_min_101),\n .Q(temp_cmp_four_dec_min_102),\n .R(1'b0));\n CARRY4 temp_cmp_four_dec_min_102_reg_i_1\n (.CI(temp_cmp_four_dec_min_102_reg_i_2_n_0),\n .CO({NLW_temp_cmp_four_dec_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_four_dec_min_101,temp_cmp_four_dec_min_102_reg_i_1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,temp_cmp_four_dec_min_102_i_3_n_0,temp_cmp_four_dec_min_102_i_4_n_0}),\n .O(NLW_temp_cmp_four_dec_min_102_reg_i_1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,temp_cmp_four_dec_min_102_i_5_n_0,temp_cmp_four_dec_min_102_i_6_n_0}));\n CARRY4 temp_cmp_four_dec_min_102_reg_i_2\n (.CI(1'b0),\n .CO({temp_cmp_four_dec_min_102_reg_i_2_n_0,temp_cmp_four_dec_min_102_reg_i_2_n_1,temp_cmp_four_dec_min_102_reg_i_2_n_2,temp_cmp_four_dec_min_102_reg_i_2_n_3}),\n .CYINIT(1'b0),\n .DI({temp_cmp_four_dec_min_102_i_7_n_0,temp_cmp_four_dec_min_102_i_8_n_0,temp_cmp_four_dec_min_102_i_9_n_0,temp_cmp_four_dec_min_102_i_10_n_0}),\n .O(NLW_temp_cmp_four_dec_min_102_reg_i_2_O_UNCONNECTED[3:0]),\n .S({temp_cmp_four_dec_min_102_i_11_n_0,temp_cmp_four_dec_min_102_i_12_n_0,temp_cmp_four_dec_min_102_i_13_n_0,temp_cmp_four_dec_min_102_i_14_n_0}));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_four_inc_max_102_i_10\n (.I0(device_temp_101[0]),\n .I1(two_dec_max_limit[0]),\n .I2(four_inc_max_limit[1]),\n .I3(device_temp_101[1]),\n .O(temp_cmp_four_inc_max_102_i_10_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_four_inc_max_102_i_11\n (.I0(device_temp_101[6]),\n .I1(four_inc_max_limit[6]),\n .I2(device_temp_101[7]),\n .I3(four_inc_max_limit[7]),\n .O(temp_cmp_four_inc_max_102_i_11_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_four_inc_max_102_i_12\n (.I0(device_temp_101[4]),\n .I1(four_inc_max_limit[4]),\n .I2(device_temp_101[5]),\n .I3(four_inc_max_limit[5]),\n .O(temp_cmp_four_inc_max_102_i_12_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_four_inc_max_102_i_13\n (.I0(device_temp_101[2]),\n .I1(four_inc_max_limit[2]),\n .I2(device_temp_101[3]),\n .I3(four_inc_max_limit[3]),\n .O(temp_cmp_four_inc_max_102_i_13_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_four_inc_max_102_i_14\n (.I0(device_temp_101[0]),\n .I1(two_dec_max_limit[0]),\n .I2(device_temp_101[1]),\n .I3(four_inc_max_limit[1]),\n .O(temp_cmp_four_inc_max_102_i_14_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_four_inc_max_102_i_3\n (.I0(device_temp_101[10]),\n .I1(four_inc_max_limit[10]),\n .I2(four_inc_max_limit[11]),\n .I3(device_temp_101[11]),\n .O(temp_cmp_four_inc_max_102_i_3_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_four_inc_max_102_i_4\n (.I0(device_temp_101[8]),\n .I1(four_inc_max_limit[8]),\n .I2(four_inc_max_limit[9]),\n .I3(device_temp_101[9]),\n .O(temp_cmp_four_inc_max_102_i_4_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_four_inc_max_102_i_5\n (.I0(device_temp_101[10]),\n .I1(four_inc_max_limit[10]),\n .I2(device_temp_101[11]),\n .I3(four_inc_max_limit[11]),\n .O(temp_cmp_four_inc_max_102_i_5_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_four_inc_max_102_i_6\n (.I0(device_temp_101[8]),\n .I1(four_inc_max_limit[8]),\n .I2(device_temp_101[9]),\n .I3(four_inc_max_limit[9]),\n .O(temp_cmp_four_inc_max_102_i_6_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_four_inc_max_102_i_7\n (.I0(device_temp_101[6]),\n .I1(four_inc_max_limit[6]),\n .I2(four_inc_max_limit[7]),\n .I3(device_temp_101[7]),\n .O(temp_cmp_four_inc_max_102_i_7_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_four_inc_max_102_i_8\n (.I0(device_temp_101[4]),\n .I1(four_inc_max_limit[4]),\n .I2(four_inc_max_limit[5]),\n .I3(device_temp_101[5]),\n .O(temp_cmp_four_inc_max_102_i_8_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_four_inc_max_102_i_9\n (.I0(device_temp_101[2]),\n .I1(four_inc_max_limit[2]),\n .I2(four_inc_max_limit[3]),\n .I3(device_temp_101[3]),\n .O(temp_cmp_four_inc_max_102_i_9_n_0));\n FDRE #(\n .INIT(1'b0)) \n temp_cmp_four_inc_max_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(temp_cmp_four_inc_max_101),\n .Q(temp_cmp_four_inc_max_102),\n .R(1'b0));\n CARRY4 temp_cmp_four_inc_max_102_reg_i_1\n (.CI(temp_cmp_four_inc_max_102_reg_i_2_n_0),\n .CO({NLW_temp_cmp_four_inc_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_four_inc_max_101,temp_cmp_four_inc_max_102_reg_i_1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,temp_cmp_four_inc_max_102_i_3_n_0,temp_cmp_four_inc_max_102_i_4_n_0}),\n .O(NLW_temp_cmp_four_inc_max_102_reg_i_1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,temp_cmp_four_inc_max_102_i_5_n_0,temp_cmp_four_inc_max_102_i_6_n_0}));\n CARRY4 temp_cmp_four_inc_max_102_reg_i_2\n (.CI(1'b0),\n .CO({temp_cmp_four_inc_max_102_reg_i_2_n_0,temp_cmp_four_inc_max_102_reg_i_2_n_1,temp_cmp_four_inc_max_102_reg_i_2_n_2,temp_cmp_four_inc_max_102_reg_i_2_n_3}),\n .CYINIT(1'b1),\n .DI({temp_cmp_four_inc_max_102_i_7_n_0,temp_cmp_four_inc_max_102_i_8_n_0,temp_cmp_four_inc_max_102_i_9_n_0,temp_cmp_four_inc_max_102_i_10_n_0}),\n .O(NLW_temp_cmp_four_inc_max_102_reg_i_2_O_UNCONNECTED[3:0]),\n .S({temp_cmp_four_inc_max_102_i_11_n_0,temp_cmp_four_inc_max_102_i_12_n_0,temp_cmp_four_inc_max_102_i_13_n_0,temp_cmp_four_inc_max_102_i_14_n_0}));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_neutral_max_102_i_10\n (.I0(device_temp_101[0]),\n .I1(two_dec_max_limit[0]),\n .I2(neutral_max_limit[1]),\n .I3(device_temp_101[1]),\n .O(temp_cmp_neutral_max_102_i_10_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_neutral_max_102_i_11\n (.I0(device_temp_101[6]),\n .I1(neutral_max_limit[6]),\n .I2(device_temp_101[7]),\n .I3(neutral_max_limit[7]),\n .O(temp_cmp_neutral_max_102_i_11_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_neutral_max_102_i_12\n (.I0(device_temp_101[4]),\n .I1(neutral_max_limit[4]),\n .I2(device_temp_101[5]),\n .I3(neutral_max_limit[5]),\n .O(temp_cmp_neutral_max_102_i_12_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_neutral_max_102_i_13\n (.I0(device_temp_101[2]),\n .I1(neutral_max_limit[2]),\n .I2(device_temp_101[3]),\n .I3(neutral_max_limit[3]),\n .O(temp_cmp_neutral_max_102_i_13_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_neutral_max_102_i_14\n (.I0(device_temp_101[0]),\n .I1(two_dec_max_limit[0]),\n .I2(device_temp_101[1]),\n .I3(neutral_max_limit[1]),\n .O(temp_cmp_neutral_max_102_i_14_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_neutral_max_102_i_3\n (.I0(device_temp_101[10]),\n .I1(neutral_max_limit[10]),\n .I2(neutral_max_limit[11]),\n .I3(device_temp_101[11]),\n .O(temp_cmp_neutral_max_102_i_3_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_neutral_max_102_i_4\n (.I0(device_temp_101[8]),\n .I1(neutral_max_limit[8]),\n .I2(neutral_max_limit[9]),\n .I3(device_temp_101[9]),\n .O(temp_cmp_neutral_max_102_i_4_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_neutral_max_102_i_5\n (.I0(device_temp_101[10]),\n .I1(neutral_max_limit[10]),\n .I2(device_temp_101[11]),\n .I3(neutral_max_limit[11]),\n .O(temp_cmp_neutral_max_102_i_5_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_neutral_max_102_i_6\n (.I0(device_temp_101[8]),\n .I1(neutral_max_limit[8]),\n .I2(device_temp_101[9]),\n .I3(neutral_max_limit[9]),\n .O(temp_cmp_neutral_max_102_i_6_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_neutral_max_102_i_7\n (.I0(device_temp_101[6]),\n .I1(neutral_max_limit[6]),\n .I2(neutral_max_limit[7]),\n .I3(device_temp_101[7]),\n .O(temp_cmp_neutral_max_102_i_7_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_neutral_max_102_i_8\n (.I0(device_temp_101[4]),\n .I1(neutral_max_limit[4]),\n .I2(neutral_max_limit[5]),\n .I3(device_temp_101[5]),\n .O(temp_cmp_neutral_max_102_i_8_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_neutral_max_102_i_9\n (.I0(device_temp_101[2]),\n .I1(neutral_max_limit[2]),\n .I2(neutral_max_limit[3]),\n .I3(device_temp_101[3]),\n .O(temp_cmp_neutral_max_102_i_9_n_0));\n FDRE #(\n .INIT(1'b0)) \n temp_cmp_neutral_max_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(temp_cmp_neutral_max_101),\n .Q(temp_cmp_neutral_max_102),\n .R(1'b0));\n CARRY4 temp_cmp_neutral_max_102_reg_i_1\n (.CI(temp_cmp_neutral_max_102_reg_i_2_n_0),\n .CO({NLW_temp_cmp_neutral_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_neutral_max_101,temp_cmp_neutral_max_102_reg_i_1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,temp_cmp_neutral_max_102_i_3_n_0,temp_cmp_neutral_max_102_i_4_n_0}),\n .O(NLW_temp_cmp_neutral_max_102_reg_i_1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,temp_cmp_neutral_max_102_i_5_n_0,temp_cmp_neutral_max_102_i_6_n_0}));\n CARRY4 temp_cmp_neutral_max_102_reg_i_2\n (.CI(1'b0),\n .CO({temp_cmp_neutral_max_102_reg_i_2_n_0,temp_cmp_neutral_max_102_reg_i_2_n_1,temp_cmp_neutral_max_102_reg_i_2_n_2,temp_cmp_neutral_max_102_reg_i_2_n_3}),\n .CYINIT(1'b1),\n .DI({temp_cmp_neutral_max_102_i_7_n_0,temp_cmp_neutral_max_102_i_8_n_0,temp_cmp_neutral_max_102_i_9_n_0,temp_cmp_neutral_max_102_i_10_n_0}),\n .O(NLW_temp_cmp_neutral_max_102_reg_i_2_O_UNCONNECTED[3:0]),\n .S({temp_cmp_neutral_max_102_i_11_n_0,temp_cmp_neutral_max_102_i_12_n_0,temp_cmp_neutral_max_102_i_13_n_0,temp_cmp_neutral_max_102_i_14_n_0}));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_neutral_min_102_i_10\n (.I0(three_dec_min_limit[0]),\n .I1(device_temp_101[0]),\n .I2(device_temp_101[1]),\n .I3(neutral_min_limit[1]),\n .O(temp_cmp_neutral_min_102_i_10_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_neutral_min_102_i_11\n (.I0(neutral_min_limit[6]),\n .I1(device_temp_101[6]),\n .I2(neutral_min_limit[7]),\n .I3(device_temp_101[7]),\n .O(temp_cmp_neutral_min_102_i_11_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_neutral_min_102_i_12\n (.I0(neutral_min_limit[4]),\n .I1(device_temp_101[4]),\n .I2(neutral_min_limit[5]),\n .I3(device_temp_101[5]),\n .O(temp_cmp_neutral_min_102_i_12_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_neutral_min_102_i_13\n (.I0(neutral_min_limit[2]),\n .I1(device_temp_101[2]),\n .I2(neutral_min_limit[3]),\n .I3(device_temp_101[3]),\n .O(temp_cmp_neutral_min_102_i_13_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_neutral_min_102_i_14\n (.I0(three_dec_min_limit[0]),\n .I1(device_temp_101[0]),\n .I2(neutral_min_limit[1]),\n .I3(device_temp_101[1]),\n .O(temp_cmp_neutral_min_102_i_14_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_neutral_min_102_i_3\n (.I0(neutral_min_limit[10]),\n .I1(device_temp_101[10]),\n .I2(device_temp_101[11]),\n .I3(neutral_min_limit[11]),\n .O(temp_cmp_neutral_min_102_i_3_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_neutral_min_102_i_4\n (.I0(neutral_min_limit[8]),\n .I1(device_temp_101[8]),\n .I2(device_temp_101[9]),\n .I3(neutral_min_limit[9]),\n .O(temp_cmp_neutral_min_102_i_4_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_neutral_min_102_i_5\n (.I0(neutral_min_limit[10]),\n .I1(device_temp_101[10]),\n .I2(neutral_min_limit[11]),\n .I3(device_temp_101[11]),\n .O(temp_cmp_neutral_min_102_i_5_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_neutral_min_102_i_6\n (.I0(neutral_min_limit[8]),\n .I1(device_temp_101[8]),\n .I2(neutral_min_limit[9]),\n .I3(device_temp_101[9]),\n .O(temp_cmp_neutral_min_102_i_6_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_neutral_min_102_i_7\n (.I0(neutral_min_limit[6]),\n .I1(device_temp_101[6]),\n .I2(device_temp_101[7]),\n .I3(neutral_min_limit[7]),\n .O(temp_cmp_neutral_min_102_i_7_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_neutral_min_102_i_8\n (.I0(neutral_min_limit[4]),\n .I1(device_temp_101[4]),\n .I2(device_temp_101[5]),\n .I3(neutral_min_limit[5]),\n .O(temp_cmp_neutral_min_102_i_8_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_neutral_min_102_i_9\n (.I0(neutral_min_limit[2]),\n .I1(device_temp_101[2]),\n .I2(device_temp_101[3]),\n .I3(neutral_min_limit[3]),\n .O(temp_cmp_neutral_min_102_i_9_n_0));\n FDRE #(\n .INIT(1'b0)) \n temp_cmp_neutral_min_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(temp_cmp_neutral_min_101),\n .Q(temp_cmp_neutral_min_102),\n .R(1'b0));\n CARRY4 temp_cmp_neutral_min_102_reg_i_1\n (.CI(temp_cmp_neutral_min_102_reg_i_2_n_0),\n .CO({NLW_temp_cmp_neutral_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_neutral_min_101,temp_cmp_neutral_min_102_reg_i_1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,temp_cmp_neutral_min_102_i_3_n_0,temp_cmp_neutral_min_102_i_4_n_0}),\n .O(NLW_temp_cmp_neutral_min_102_reg_i_1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,temp_cmp_neutral_min_102_i_5_n_0,temp_cmp_neutral_min_102_i_6_n_0}));\n CARRY4 temp_cmp_neutral_min_102_reg_i_2\n (.CI(1'b0),\n .CO({temp_cmp_neutral_min_102_reg_i_2_n_0,temp_cmp_neutral_min_102_reg_i_2_n_1,temp_cmp_neutral_min_102_reg_i_2_n_2,temp_cmp_neutral_min_102_reg_i_2_n_3}),\n .CYINIT(1'b0),\n .DI({temp_cmp_neutral_min_102_i_7_n_0,temp_cmp_neutral_min_102_i_8_n_0,temp_cmp_neutral_min_102_i_9_n_0,temp_cmp_neutral_min_102_i_10_n_0}),\n .O(NLW_temp_cmp_neutral_min_102_reg_i_2_O_UNCONNECTED[3:0]),\n .S({temp_cmp_neutral_min_102_i_11_n_0,temp_cmp_neutral_min_102_i_12_n_0,temp_cmp_neutral_min_102_i_13_n_0,temp_cmp_neutral_min_102_i_14_n_0}));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_dec_max_102_i_10\n (.I0(device_temp_101[0]),\n .I1(two_dec_max_limit[0]),\n .I2(one_dec_max_limit[1]),\n .I3(device_temp_101[1]),\n .O(temp_cmp_one_dec_max_102_i_10_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_dec_max_102_i_11\n (.I0(device_temp_101[6]),\n .I1(one_dec_max_limit[6]),\n .I2(device_temp_101[7]),\n .I3(one_dec_max_limit[7]),\n .O(temp_cmp_one_dec_max_102_i_11_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_dec_max_102_i_12\n (.I0(device_temp_101[4]),\n .I1(one_dec_max_limit[4]),\n .I2(device_temp_101[5]),\n .I3(one_dec_max_limit[5]),\n .O(temp_cmp_one_dec_max_102_i_12_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_dec_max_102_i_13\n (.I0(device_temp_101[2]),\n .I1(one_dec_max_limit[2]),\n .I2(device_temp_101[3]),\n .I3(one_dec_max_limit[3]),\n .O(temp_cmp_one_dec_max_102_i_13_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_dec_max_102_i_14\n (.I0(device_temp_101[0]),\n .I1(two_dec_max_limit[0]),\n .I2(device_temp_101[1]),\n .I3(one_dec_max_limit[1]),\n .O(temp_cmp_one_dec_max_102_i_14_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_dec_max_102_i_3\n (.I0(device_temp_101[10]),\n .I1(one_dec_max_limit[10]),\n .I2(one_dec_max_limit[11]),\n .I3(device_temp_101[11]),\n .O(temp_cmp_one_dec_max_102_i_3_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_dec_max_102_i_4\n (.I0(device_temp_101[8]),\n .I1(one_dec_max_limit[8]),\n .I2(one_dec_max_limit[9]),\n .I3(device_temp_101[9]),\n .O(temp_cmp_one_dec_max_102_i_4_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_dec_max_102_i_5\n (.I0(device_temp_101[10]),\n .I1(one_dec_max_limit[10]),\n .I2(device_temp_101[11]),\n .I3(one_dec_max_limit[11]),\n .O(temp_cmp_one_dec_max_102_i_5_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_dec_max_102_i_6\n (.I0(device_temp_101[8]),\n .I1(one_dec_max_limit[8]),\n .I2(device_temp_101[9]),\n .I3(one_dec_max_limit[9]),\n .O(temp_cmp_one_dec_max_102_i_6_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_dec_max_102_i_7\n (.I0(device_temp_101[6]),\n .I1(one_dec_max_limit[6]),\n .I2(one_dec_max_limit[7]),\n .I3(device_temp_101[7]),\n .O(temp_cmp_one_dec_max_102_i_7_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_dec_max_102_i_8\n (.I0(device_temp_101[4]),\n .I1(one_dec_max_limit[4]),\n .I2(one_dec_max_limit[5]),\n .I3(device_temp_101[5]),\n .O(temp_cmp_one_dec_max_102_i_8_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_dec_max_102_i_9\n (.I0(device_temp_101[2]),\n .I1(one_dec_max_limit[2]),\n .I2(one_dec_max_limit[3]),\n .I3(device_temp_101[3]),\n .O(temp_cmp_one_dec_max_102_i_9_n_0));\n FDRE #(\n .INIT(1'b0)) \n temp_cmp_one_dec_max_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(temp_cmp_one_dec_max_101),\n .Q(temp_cmp_one_dec_max_102),\n .R(1'b0));\n CARRY4 temp_cmp_one_dec_max_102_reg_i_1\n (.CI(temp_cmp_one_dec_max_102_reg_i_2_n_0),\n .CO({NLW_temp_cmp_one_dec_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_one_dec_max_101,temp_cmp_one_dec_max_102_reg_i_1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,temp_cmp_one_dec_max_102_i_3_n_0,temp_cmp_one_dec_max_102_i_4_n_0}),\n .O(NLW_temp_cmp_one_dec_max_102_reg_i_1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,temp_cmp_one_dec_max_102_i_5_n_0,temp_cmp_one_dec_max_102_i_6_n_0}));\n CARRY4 temp_cmp_one_dec_max_102_reg_i_2\n (.CI(1'b0),\n .CO({temp_cmp_one_dec_max_102_reg_i_2_n_0,temp_cmp_one_dec_max_102_reg_i_2_n_1,temp_cmp_one_dec_max_102_reg_i_2_n_2,temp_cmp_one_dec_max_102_reg_i_2_n_3}),\n .CYINIT(1'b1),\n .DI({temp_cmp_one_dec_max_102_i_7_n_0,temp_cmp_one_dec_max_102_i_8_n_0,temp_cmp_one_dec_max_102_i_9_n_0,temp_cmp_one_dec_max_102_i_10_n_0}),\n .O(NLW_temp_cmp_one_dec_max_102_reg_i_2_O_UNCONNECTED[3:0]),\n .S({temp_cmp_one_dec_max_102_i_11_n_0,temp_cmp_one_dec_max_102_i_12_n_0,temp_cmp_one_dec_max_102_i_13_n_0,temp_cmp_one_dec_max_102_i_14_n_0}));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_dec_min_102_i_10\n (.I0(three_dec_min_limit[0]),\n .I1(device_temp_101[0]),\n .I2(device_temp_101[1]),\n .I3(one_dec_min_limit[1]),\n .O(temp_cmp_one_dec_min_102_i_10_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_dec_min_102_i_11\n (.I0(one_dec_min_limit[6]),\n .I1(device_temp_101[6]),\n .I2(one_dec_min_limit[7]),\n .I3(device_temp_101[7]),\n .O(temp_cmp_one_dec_min_102_i_11_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_dec_min_102_i_12\n (.I0(one_dec_min_limit[4]),\n .I1(device_temp_101[4]),\n .I2(one_dec_min_limit[5]),\n .I3(device_temp_101[5]),\n .O(temp_cmp_one_dec_min_102_i_12_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_dec_min_102_i_13\n (.I0(one_dec_min_limit[2]),\n .I1(device_temp_101[2]),\n .I2(one_dec_min_limit[3]),\n .I3(device_temp_101[3]),\n .O(temp_cmp_one_dec_min_102_i_13_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_dec_min_102_i_14\n (.I0(three_dec_min_limit[0]),\n .I1(device_temp_101[0]),\n .I2(one_dec_min_limit[1]),\n .I3(device_temp_101[1]),\n .O(temp_cmp_one_dec_min_102_i_14_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_dec_min_102_i_3\n (.I0(one_dec_min_limit[10]),\n .I1(device_temp_101[10]),\n .I2(device_temp_101[11]),\n .I3(one_dec_min_limit[11]),\n .O(temp_cmp_one_dec_min_102_i_3_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_dec_min_102_i_4\n (.I0(one_dec_min_limit[8]),\n .I1(device_temp_101[8]),\n .I2(device_temp_101[9]),\n .I3(one_dec_min_limit[9]),\n .O(temp_cmp_one_dec_min_102_i_4_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_dec_min_102_i_5\n (.I0(one_dec_min_limit[10]),\n .I1(device_temp_101[10]),\n .I2(one_dec_min_limit[11]),\n .I3(device_temp_101[11]),\n .O(temp_cmp_one_dec_min_102_i_5_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_dec_min_102_i_6\n (.I0(one_dec_min_limit[8]),\n .I1(device_temp_101[8]),\n .I2(one_dec_min_limit[9]),\n .I3(device_temp_101[9]),\n .O(temp_cmp_one_dec_min_102_i_6_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_dec_min_102_i_7\n (.I0(one_dec_min_limit[6]),\n .I1(device_temp_101[6]),\n .I2(device_temp_101[7]),\n .I3(one_dec_min_limit[7]),\n .O(temp_cmp_one_dec_min_102_i_7_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_dec_min_102_i_8\n (.I0(one_dec_min_limit[4]),\n .I1(device_temp_101[4]),\n .I2(device_temp_101[5]),\n .I3(one_dec_min_limit[5]),\n .O(temp_cmp_one_dec_min_102_i_8_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_dec_min_102_i_9\n (.I0(one_dec_min_limit[2]),\n .I1(device_temp_101[2]),\n .I2(device_temp_101[3]),\n .I3(one_dec_min_limit[3]),\n .O(temp_cmp_one_dec_min_102_i_9_n_0));\n FDRE #(\n .INIT(1'b0)) \n temp_cmp_one_dec_min_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(temp_cmp_one_dec_min_101),\n .Q(temp_cmp_one_dec_min_102),\n .R(1'b0));\n CARRY4 temp_cmp_one_dec_min_102_reg_i_1\n (.CI(temp_cmp_one_dec_min_102_reg_i_2_n_0),\n .CO({NLW_temp_cmp_one_dec_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_one_dec_min_101,temp_cmp_one_dec_min_102_reg_i_1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,temp_cmp_one_dec_min_102_i_3_n_0,temp_cmp_one_dec_min_102_i_4_n_0}),\n .O(NLW_temp_cmp_one_dec_min_102_reg_i_1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,temp_cmp_one_dec_min_102_i_5_n_0,temp_cmp_one_dec_min_102_i_6_n_0}));\n CARRY4 temp_cmp_one_dec_min_102_reg_i_2\n (.CI(1'b0),\n .CO({temp_cmp_one_dec_min_102_reg_i_2_n_0,temp_cmp_one_dec_min_102_reg_i_2_n_1,temp_cmp_one_dec_min_102_reg_i_2_n_2,temp_cmp_one_dec_min_102_reg_i_2_n_3}),\n .CYINIT(1'b0),\n .DI({temp_cmp_one_dec_min_102_i_7_n_0,temp_cmp_one_dec_min_102_i_8_n_0,temp_cmp_one_dec_min_102_i_9_n_0,temp_cmp_one_dec_min_102_i_10_n_0}),\n .O(NLW_temp_cmp_one_dec_min_102_reg_i_2_O_UNCONNECTED[3:0]),\n .S({temp_cmp_one_dec_min_102_i_11_n_0,temp_cmp_one_dec_min_102_i_12_n_0,temp_cmp_one_dec_min_102_i_13_n_0,temp_cmp_one_dec_min_102_i_14_n_0}));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_inc_max_102_i_10\n (.I0(device_temp_101[0]),\n .I1(two_dec_max_limit[0]),\n .I2(one_inc_max_limit[1]),\n .I3(device_temp_101[1]),\n .O(temp_cmp_one_inc_max_102_i_10_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_inc_max_102_i_11\n (.I0(device_temp_101[6]),\n .I1(one_inc_max_limit[6]),\n .I2(device_temp_101[7]),\n .I3(one_inc_max_limit[7]),\n .O(temp_cmp_one_inc_max_102_i_11_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_inc_max_102_i_12\n (.I0(device_temp_101[4]),\n .I1(one_inc_max_limit[4]),\n .I2(device_temp_101[5]),\n .I3(one_inc_max_limit[5]),\n .O(temp_cmp_one_inc_max_102_i_12_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_inc_max_102_i_13\n (.I0(device_temp_101[2]),\n .I1(one_inc_max_limit[2]),\n .I2(device_temp_101[3]),\n .I3(one_inc_max_limit[3]),\n .O(temp_cmp_one_inc_max_102_i_13_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_inc_max_102_i_14\n (.I0(device_temp_101[0]),\n .I1(two_dec_max_limit[0]),\n .I2(device_temp_101[1]),\n .I3(one_inc_max_limit[1]),\n .O(temp_cmp_one_inc_max_102_i_14_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_inc_max_102_i_3\n (.I0(device_temp_101[10]),\n .I1(one_inc_max_limit[10]),\n .I2(one_inc_max_limit[11]),\n .I3(device_temp_101[11]),\n .O(temp_cmp_one_inc_max_102_i_3_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_inc_max_102_i_4\n (.I0(device_temp_101[8]),\n .I1(one_inc_max_limit[8]),\n .I2(one_inc_max_limit[9]),\n .I3(device_temp_101[9]),\n .O(temp_cmp_one_inc_max_102_i_4_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_inc_max_102_i_5\n (.I0(device_temp_101[10]),\n .I1(one_inc_max_limit[10]),\n .I2(device_temp_101[11]),\n .I3(one_inc_max_limit[11]),\n .O(temp_cmp_one_inc_max_102_i_5_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_inc_max_102_i_6\n (.I0(device_temp_101[8]),\n .I1(one_inc_max_limit[8]),\n .I2(device_temp_101[9]),\n .I3(one_inc_max_limit[9]),\n .O(temp_cmp_one_inc_max_102_i_6_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_inc_max_102_i_7\n (.I0(device_temp_101[6]),\n .I1(one_inc_max_limit[6]),\n .I2(one_inc_max_limit[7]),\n .I3(device_temp_101[7]),\n .O(temp_cmp_one_inc_max_102_i_7_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_inc_max_102_i_8\n (.I0(device_temp_101[4]),\n .I1(one_inc_max_limit[4]),\n .I2(one_inc_max_limit[5]),\n .I3(device_temp_101[5]),\n .O(temp_cmp_one_inc_max_102_i_8_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_inc_max_102_i_9\n (.I0(device_temp_101[2]),\n .I1(one_inc_max_limit[2]),\n .I2(one_inc_max_limit[3]),\n .I3(device_temp_101[3]),\n .O(temp_cmp_one_inc_max_102_i_9_n_0));\n FDRE #(\n .INIT(1'b0)) \n temp_cmp_one_inc_max_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(temp_cmp_one_inc_max_101),\n .Q(temp_cmp_one_inc_max_102),\n .R(1'b0));\n CARRY4 temp_cmp_one_inc_max_102_reg_i_1\n (.CI(temp_cmp_one_inc_max_102_reg_i_2_n_0),\n .CO({NLW_temp_cmp_one_inc_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_one_inc_max_101,temp_cmp_one_inc_max_102_reg_i_1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,temp_cmp_one_inc_max_102_i_3_n_0,temp_cmp_one_inc_max_102_i_4_n_0}),\n .O(NLW_temp_cmp_one_inc_max_102_reg_i_1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,temp_cmp_one_inc_max_102_i_5_n_0,temp_cmp_one_inc_max_102_i_6_n_0}));\n CARRY4 temp_cmp_one_inc_max_102_reg_i_2\n (.CI(1'b0),\n .CO({temp_cmp_one_inc_max_102_reg_i_2_n_0,temp_cmp_one_inc_max_102_reg_i_2_n_1,temp_cmp_one_inc_max_102_reg_i_2_n_2,temp_cmp_one_inc_max_102_reg_i_2_n_3}),\n .CYINIT(1'b1),\n .DI({temp_cmp_one_inc_max_102_i_7_n_0,temp_cmp_one_inc_max_102_i_8_n_0,temp_cmp_one_inc_max_102_i_9_n_0,temp_cmp_one_inc_max_102_i_10_n_0}),\n .O(NLW_temp_cmp_one_inc_max_102_reg_i_2_O_UNCONNECTED[3:0]),\n .S({temp_cmp_one_inc_max_102_i_11_n_0,temp_cmp_one_inc_max_102_i_12_n_0,temp_cmp_one_inc_max_102_i_13_n_0,temp_cmp_one_inc_max_102_i_14_n_0}));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_inc_min_102_i_10\n (.I0(three_dec_min_limit[0]),\n .I1(device_temp_101[0]),\n .I2(device_temp_101[1]),\n .I3(one_inc_min_limit[1]),\n .O(temp_cmp_one_inc_min_102_i_10_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_inc_min_102_i_11\n (.I0(one_inc_min_limit[6]),\n .I1(device_temp_101[6]),\n .I2(one_inc_min_limit[7]),\n .I3(device_temp_101[7]),\n .O(temp_cmp_one_inc_min_102_i_11_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_inc_min_102_i_12\n (.I0(one_inc_min_limit[4]),\n .I1(device_temp_101[4]),\n .I2(one_inc_min_limit[5]),\n .I3(device_temp_101[5]),\n .O(temp_cmp_one_inc_min_102_i_12_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_inc_min_102_i_13\n (.I0(one_inc_min_limit[2]),\n .I1(device_temp_101[2]),\n .I2(one_inc_min_limit[3]),\n .I3(device_temp_101[3]),\n .O(temp_cmp_one_inc_min_102_i_13_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_inc_min_102_i_14\n (.I0(three_dec_min_limit[0]),\n .I1(device_temp_101[0]),\n .I2(one_inc_min_limit[1]),\n .I3(device_temp_101[1]),\n .O(temp_cmp_one_inc_min_102_i_14_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_inc_min_102_i_3\n (.I0(one_inc_min_limit[10]),\n .I1(device_temp_101[10]),\n .I2(device_temp_101[11]),\n .I3(one_inc_min_limit[11]),\n .O(temp_cmp_one_inc_min_102_i_3_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_inc_min_102_i_4\n (.I0(one_inc_min_limit[8]),\n .I1(device_temp_101[8]),\n .I2(device_temp_101[9]),\n .I3(one_inc_min_limit[9]),\n .O(temp_cmp_one_inc_min_102_i_4_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_inc_min_102_i_5\n (.I0(one_inc_min_limit[10]),\n .I1(device_temp_101[10]),\n .I2(one_inc_min_limit[11]),\n .I3(device_temp_101[11]),\n .O(temp_cmp_one_inc_min_102_i_5_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_inc_min_102_i_6\n (.I0(one_inc_min_limit[8]),\n .I1(device_temp_101[8]),\n .I2(one_inc_min_limit[9]),\n .I3(device_temp_101[9]),\n .O(temp_cmp_one_inc_min_102_i_6_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_inc_min_102_i_7\n (.I0(one_inc_min_limit[6]),\n .I1(device_temp_101[6]),\n .I2(device_temp_101[7]),\n .I3(one_inc_min_limit[7]),\n .O(temp_cmp_one_inc_min_102_i_7_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_inc_min_102_i_8\n (.I0(one_inc_min_limit[4]),\n .I1(device_temp_101[4]),\n .I2(device_temp_101[5]),\n .I3(one_inc_min_limit[5]),\n .O(temp_cmp_one_inc_min_102_i_8_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_inc_min_102_i_9\n (.I0(one_inc_min_limit[2]),\n .I1(device_temp_101[2]),\n .I2(device_temp_101[3]),\n .I3(one_inc_min_limit[3]),\n .O(temp_cmp_one_inc_min_102_i_9_n_0));\n FDRE #(\n .INIT(1'b0)) \n temp_cmp_one_inc_min_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(temp_cmp_one_inc_min_101),\n .Q(temp_cmp_one_inc_min_102),\n .R(1'b0));\n CARRY4 temp_cmp_one_inc_min_102_reg_i_1\n (.CI(temp_cmp_one_inc_min_102_reg_i_2_n_0),\n .CO({NLW_temp_cmp_one_inc_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_one_inc_min_101,temp_cmp_one_inc_min_102_reg_i_1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,temp_cmp_one_inc_min_102_i_3_n_0,temp_cmp_one_inc_min_102_i_4_n_0}),\n .O(NLW_temp_cmp_one_inc_min_102_reg_i_1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,temp_cmp_one_inc_min_102_i_5_n_0,temp_cmp_one_inc_min_102_i_6_n_0}));\n CARRY4 temp_cmp_one_inc_min_102_reg_i_2\n (.CI(1'b0),\n .CO({temp_cmp_one_inc_min_102_reg_i_2_n_0,temp_cmp_one_inc_min_102_reg_i_2_n_1,temp_cmp_one_inc_min_102_reg_i_2_n_2,temp_cmp_one_inc_min_102_reg_i_2_n_3}),\n .CYINIT(1'b0),\n .DI({temp_cmp_one_inc_min_102_i_7_n_0,temp_cmp_one_inc_min_102_i_8_n_0,temp_cmp_one_inc_min_102_i_9_n_0,temp_cmp_one_inc_min_102_i_10_n_0}),\n .O(NLW_temp_cmp_one_inc_min_102_reg_i_2_O_UNCONNECTED[3:0]),\n .S({temp_cmp_one_inc_min_102_i_11_n_0,temp_cmp_one_inc_min_102_i_12_n_0,temp_cmp_one_inc_min_102_i_13_n_0,temp_cmp_one_inc_min_102_i_14_n_0}));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_dec_max_102_i_10\n (.I0(device_temp_101[0]),\n .I1(three_dec_max_limit[0]),\n .I2(three_dec_max_limit[1]),\n .I3(device_temp_101[1]),\n .O(temp_cmp_three_dec_max_102_i_10_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_dec_max_102_i_11\n (.I0(device_temp_101[6]),\n .I1(three_dec_max_limit[6]),\n .I2(device_temp_101[7]),\n .I3(three_dec_max_limit[7]),\n .O(temp_cmp_three_dec_max_102_i_11_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_dec_max_102_i_12\n (.I0(device_temp_101[4]),\n .I1(three_dec_max_limit[4]),\n .I2(device_temp_101[5]),\n .I3(three_dec_max_limit[5]),\n .O(temp_cmp_three_dec_max_102_i_12_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_dec_max_102_i_13\n (.I0(device_temp_101[2]),\n .I1(three_dec_max_limit[2]),\n .I2(device_temp_101[3]),\n .I3(three_dec_max_limit[3]),\n .O(temp_cmp_three_dec_max_102_i_13_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_dec_max_102_i_14\n (.I0(device_temp_101[0]),\n .I1(three_dec_max_limit[0]),\n .I2(device_temp_101[1]),\n .I3(three_dec_max_limit[1]),\n .O(temp_cmp_three_dec_max_102_i_14_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_dec_max_102_i_3\n (.I0(device_temp_101[10]),\n .I1(three_dec_max_limit[10]),\n .I2(three_dec_max_limit[11]),\n .I3(device_temp_101[11]),\n .O(temp_cmp_three_dec_max_102_i_3_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_dec_max_102_i_4\n (.I0(device_temp_101[8]),\n .I1(three_dec_max_limit[8]),\n .I2(three_dec_max_limit[9]),\n .I3(device_temp_101[9]),\n .O(temp_cmp_three_dec_max_102_i_4_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_dec_max_102_i_5\n (.I0(device_temp_101[10]),\n .I1(three_dec_max_limit[10]),\n .I2(device_temp_101[11]),\n .I3(three_dec_max_limit[11]),\n .O(temp_cmp_three_dec_max_102_i_5_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_dec_max_102_i_6\n (.I0(device_temp_101[8]),\n .I1(three_dec_max_limit[8]),\n .I2(device_temp_101[9]),\n .I3(three_dec_max_limit[9]),\n .O(temp_cmp_three_dec_max_102_i_6_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_dec_max_102_i_7\n (.I0(device_temp_101[6]),\n .I1(three_dec_max_limit[6]),\n .I2(three_dec_max_limit[7]),\n .I3(device_temp_101[7]),\n .O(temp_cmp_three_dec_max_102_i_7_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_dec_max_102_i_8\n (.I0(device_temp_101[4]),\n .I1(three_dec_max_limit[4]),\n .I2(three_dec_max_limit[5]),\n .I3(device_temp_101[5]),\n .O(temp_cmp_three_dec_max_102_i_8_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_dec_max_102_i_9\n (.I0(device_temp_101[2]),\n .I1(three_dec_max_limit[2]),\n .I2(three_dec_max_limit[3]),\n .I3(device_temp_101[3]),\n .O(temp_cmp_three_dec_max_102_i_9_n_0));\n FDRE #(\n .INIT(1'b0)) \n temp_cmp_three_dec_max_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(temp_cmp_three_dec_max_101),\n .Q(temp_cmp_three_dec_max_102),\n .R(1'b0));\n CARRY4 temp_cmp_three_dec_max_102_reg_i_1\n (.CI(temp_cmp_three_dec_max_102_reg_i_2_n_0),\n .CO({NLW_temp_cmp_three_dec_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_three_dec_max_101,temp_cmp_three_dec_max_102_reg_i_1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,temp_cmp_three_dec_max_102_i_3_n_0,temp_cmp_three_dec_max_102_i_4_n_0}),\n .O(NLW_temp_cmp_three_dec_max_102_reg_i_1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,temp_cmp_three_dec_max_102_i_5_n_0,temp_cmp_three_dec_max_102_i_6_n_0}));\n CARRY4 temp_cmp_three_dec_max_102_reg_i_2\n (.CI(1'b0),\n .CO({temp_cmp_three_dec_max_102_reg_i_2_n_0,temp_cmp_three_dec_max_102_reg_i_2_n_1,temp_cmp_three_dec_max_102_reg_i_2_n_2,temp_cmp_three_dec_max_102_reg_i_2_n_3}),\n .CYINIT(1'b1),\n .DI({temp_cmp_three_dec_max_102_i_7_n_0,temp_cmp_three_dec_max_102_i_8_n_0,temp_cmp_three_dec_max_102_i_9_n_0,temp_cmp_three_dec_max_102_i_10_n_0}),\n .O(NLW_temp_cmp_three_dec_max_102_reg_i_2_O_UNCONNECTED[3:0]),\n .S({temp_cmp_three_dec_max_102_i_11_n_0,temp_cmp_three_dec_max_102_i_12_n_0,temp_cmp_three_dec_max_102_i_13_n_0,temp_cmp_three_dec_max_102_i_14_n_0}));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_dec_min_102_i_10\n (.I0(three_dec_min_limit[0]),\n .I1(device_temp_101[0]),\n .I2(device_temp_101[1]),\n .I3(three_dec_min_limit[1]),\n .O(temp_cmp_three_dec_min_102_i_10_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_dec_min_102_i_11\n (.I0(three_dec_min_limit[6]),\n .I1(device_temp_101[6]),\n .I2(three_dec_min_limit[7]),\n .I3(device_temp_101[7]),\n .O(temp_cmp_three_dec_min_102_i_11_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_dec_min_102_i_12\n (.I0(three_dec_min_limit[4]),\n .I1(device_temp_101[4]),\n .I2(three_dec_min_limit[5]),\n .I3(device_temp_101[5]),\n .O(temp_cmp_three_dec_min_102_i_12_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_dec_min_102_i_13\n (.I0(three_dec_min_limit[2]),\n .I1(device_temp_101[2]),\n .I2(three_dec_min_limit[3]),\n .I3(device_temp_101[3]),\n .O(temp_cmp_three_dec_min_102_i_13_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_dec_min_102_i_14\n (.I0(three_dec_min_limit[0]),\n .I1(device_temp_101[0]),\n .I2(three_dec_min_limit[1]),\n .I3(device_temp_101[1]),\n .O(temp_cmp_three_dec_min_102_i_14_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_dec_min_102_i_3\n (.I0(three_dec_min_limit[10]),\n .I1(device_temp_101[10]),\n .I2(device_temp_101[11]),\n .I3(three_dec_min_limit[11]),\n .O(temp_cmp_three_dec_min_102_i_3_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_dec_min_102_i_4\n (.I0(three_dec_min_limit[8]),\n .I1(device_temp_101[8]),\n .I2(device_temp_101[9]),\n .I3(three_dec_min_limit[9]),\n .O(temp_cmp_three_dec_min_102_i_4_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_dec_min_102_i_5\n (.I0(three_dec_min_limit[10]),\n .I1(device_temp_101[10]),\n .I2(three_dec_min_limit[11]),\n .I3(device_temp_101[11]),\n .O(temp_cmp_three_dec_min_102_i_5_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_dec_min_102_i_6\n (.I0(three_dec_min_limit[8]),\n .I1(device_temp_101[8]),\n .I2(three_dec_min_limit[9]),\n .I3(device_temp_101[9]),\n .O(temp_cmp_three_dec_min_102_i_6_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_dec_min_102_i_7\n (.I0(three_dec_min_limit[6]),\n .I1(device_temp_101[6]),\n .I2(device_temp_101[7]),\n .I3(three_dec_min_limit[7]),\n .O(temp_cmp_three_dec_min_102_i_7_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_dec_min_102_i_8\n (.I0(three_dec_min_limit[4]),\n .I1(device_temp_101[4]),\n .I2(device_temp_101[5]),\n .I3(three_dec_min_limit[5]),\n .O(temp_cmp_three_dec_min_102_i_8_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_dec_min_102_i_9\n (.I0(three_dec_min_limit[2]),\n .I1(device_temp_101[2]),\n .I2(device_temp_101[3]),\n .I3(three_dec_min_limit[3]),\n .O(temp_cmp_three_dec_min_102_i_9_n_0));\n FDRE #(\n .INIT(1'b0)) \n temp_cmp_three_dec_min_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(temp_cmp_three_dec_min_101),\n .Q(temp_cmp_three_dec_min_102),\n .R(1'b0));\n CARRY4 temp_cmp_three_dec_min_102_reg_i_1\n (.CI(temp_cmp_three_dec_min_102_reg_i_2_n_0),\n .CO({NLW_temp_cmp_three_dec_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_three_dec_min_101,temp_cmp_three_dec_min_102_reg_i_1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,temp_cmp_three_dec_min_102_i_3_n_0,temp_cmp_three_dec_min_102_i_4_n_0}),\n .O(NLW_temp_cmp_three_dec_min_102_reg_i_1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,temp_cmp_three_dec_min_102_i_5_n_0,temp_cmp_three_dec_min_102_i_6_n_0}));\n CARRY4 temp_cmp_three_dec_min_102_reg_i_2\n (.CI(1'b0),\n .CO({temp_cmp_three_dec_min_102_reg_i_2_n_0,temp_cmp_three_dec_min_102_reg_i_2_n_1,temp_cmp_three_dec_min_102_reg_i_2_n_2,temp_cmp_three_dec_min_102_reg_i_2_n_3}),\n .CYINIT(1'b0),\n .DI({temp_cmp_three_dec_min_102_i_7_n_0,temp_cmp_three_dec_min_102_i_8_n_0,temp_cmp_three_dec_min_102_i_9_n_0,temp_cmp_three_dec_min_102_i_10_n_0}),\n .O(NLW_temp_cmp_three_dec_min_102_reg_i_2_O_UNCONNECTED[3:0]),\n .S({temp_cmp_three_dec_min_102_i_11_n_0,temp_cmp_three_dec_min_102_i_12_n_0,temp_cmp_three_dec_min_102_i_13_n_0,temp_cmp_three_dec_min_102_i_14_n_0}));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_inc_max_102_i_10\n (.I0(device_temp_101[0]),\n .I1(two_dec_max_limit[0]),\n .I2(three_inc_max_limit[1]),\n .I3(device_temp_101[1]),\n .O(temp_cmp_three_inc_max_102_i_10_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_inc_max_102_i_11\n (.I0(device_temp_101[6]),\n .I1(three_inc_max_limit[6]),\n .I2(device_temp_101[7]),\n .I3(three_inc_max_limit[7]),\n .O(temp_cmp_three_inc_max_102_i_11_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_inc_max_102_i_12\n (.I0(device_temp_101[4]),\n .I1(three_inc_max_limit[4]),\n .I2(device_temp_101[5]),\n .I3(three_inc_max_limit[5]),\n .O(temp_cmp_three_inc_max_102_i_12_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_inc_max_102_i_13\n (.I0(device_temp_101[2]),\n .I1(three_inc_max_limit[2]),\n .I2(device_temp_101[3]),\n .I3(three_inc_max_limit[3]),\n .O(temp_cmp_three_inc_max_102_i_13_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_inc_max_102_i_14\n (.I0(device_temp_101[0]),\n .I1(two_dec_max_limit[0]),\n .I2(device_temp_101[1]),\n .I3(three_inc_max_limit[1]),\n .O(temp_cmp_three_inc_max_102_i_14_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_inc_max_102_i_3\n (.I0(device_temp_101[10]),\n .I1(three_inc_max_limit[10]),\n .I2(three_inc_max_limit[11]),\n .I3(device_temp_101[11]),\n .O(temp_cmp_three_inc_max_102_i_3_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_inc_max_102_i_4\n (.I0(device_temp_101[8]),\n .I1(three_inc_max_limit[8]),\n .I2(three_inc_max_limit[9]),\n .I3(device_temp_101[9]),\n .O(temp_cmp_three_inc_max_102_i_4_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_inc_max_102_i_5\n (.I0(device_temp_101[10]),\n .I1(three_inc_max_limit[10]),\n .I2(device_temp_101[11]),\n .I3(three_inc_max_limit[11]),\n .O(temp_cmp_three_inc_max_102_i_5_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_inc_max_102_i_6\n (.I0(device_temp_101[8]),\n .I1(three_inc_max_limit[8]),\n .I2(device_temp_101[9]),\n .I3(three_inc_max_limit[9]),\n .O(temp_cmp_three_inc_max_102_i_6_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_inc_max_102_i_7\n (.I0(device_temp_101[6]),\n .I1(three_inc_max_limit[6]),\n .I2(three_inc_max_limit[7]),\n .I3(device_temp_101[7]),\n .O(temp_cmp_three_inc_max_102_i_7_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_inc_max_102_i_8\n (.I0(device_temp_101[4]),\n .I1(three_inc_max_limit[4]),\n .I2(three_inc_max_limit[5]),\n .I3(device_temp_101[5]),\n .O(temp_cmp_three_inc_max_102_i_8_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_inc_max_102_i_9\n (.I0(device_temp_101[2]),\n .I1(three_inc_max_limit[2]),\n .I2(three_inc_max_limit[3]),\n .I3(device_temp_101[3]),\n .O(temp_cmp_three_inc_max_102_i_9_n_0));\n FDRE #(\n .INIT(1'b0)) \n temp_cmp_three_inc_max_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(temp_cmp_three_inc_max_101),\n .Q(temp_cmp_three_inc_max_102),\n .R(1'b0));\n CARRY4 temp_cmp_three_inc_max_102_reg_i_1\n (.CI(temp_cmp_three_inc_max_102_reg_i_2_n_0),\n .CO({NLW_temp_cmp_three_inc_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_three_inc_max_101,temp_cmp_three_inc_max_102_reg_i_1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,temp_cmp_three_inc_max_102_i_3_n_0,temp_cmp_three_inc_max_102_i_4_n_0}),\n .O(NLW_temp_cmp_three_inc_max_102_reg_i_1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,temp_cmp_three_inc_max_102_i_5_n_0,temp_cmp_three_inc_max_102_i_6_n_0}));\n CARRY4 temp_cmp_three_inc_max_102_reg_i_2\n (.CI(1'b0),\n .CO({temp_cmp_three_inc_max_102_reg_i_2_n_0,temp_cmp_three_inc_max_102_reg_i_2_n_1,temp_cmp_three_inc_max_102_reg_i_2_n_2,temp_cmp_three_inc_max_102_reg_i_2_n_3}),\n .CYINIT(1'b1),\n .DI({temp_cmp_three_inc_max_102_i_7_n_0,temp_cmp_three_inc_max_102_i_8_n_0,temp_cmp_three_inc_max_102_i_9_n_0,temp_cmp_three_inc_max_102_i_10_n_0}),\n .O(NLW_temp_cmp_three_inc_max_102_reg_i_2_O_UNCONNECTED[3:0]),\n .S({temp_cmp_three_inc_max_102_i_11_n_0,temp_cmp_three_inc_max_102_i_12_n_0,temp_cmp_three_inc_max_102_i_13_n_0,temp_cmp_three_inc_max_102_i_14_n_0}));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_inc_min_102_i_10\n (.I0(three_dec_min_limit[0]),\n .I1(device_temp_101[0]),\n .I2(device_temp_101[1]),\n .I3(three_inc_min_limit[1]),\n .O(temp_cmp_three_inc_min_102_i_10_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_inc_min_102_i_11\n (.I0(three_inc_min_limit[6]),\n .I1(device_temp_101[6]),\n .I2(three_inc_min_limit[7]),\n .I3(device_temp_101[7]),\n .O(temp_cmp_three_inc_min_102_i_11_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_inc_min_102_i_12\n (.I0(three_inc_min_limit[4]),\n .I1(device_temp_101[4]),\n .I2(three_inc_min_limit[5]),\n .I3(device_temp_101[5]),\n .O(temp_cmp_three_inc_min_102_i_12_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_inc_min_102_i_13\n (.I0(three_inc_min_limit[2]),\n .I1(device_temp_101[2]),\n .I2(three_inc_min_limit[3]),\n .I3(device_temp_101[3]),\n .O(temp_cmp_three_inc_min_102_i_13_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_inc_min_102_i_14\n (.I0(three_dec_min_limit[0]),\n .I1(device_temp_101[0]),\n .I2(three_inc_min_limit[1]),\n .I3(device_temp_101[1]),\n .O(temp_cmp_three_inc_min_102_i_14_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_inc_min_102_i_3\n (.I0(three_inc_min_limit[10]),\n .I1(device_temp_101[10]),\n .I2(device_temp_101[11]),\n .I3(three_inc_min_limit[11]),\n .O(temp_cmp_three_inc_min_102_i_3_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_inc_min_102_i_4\n (.I0(three_inc_min_limit[8]),\n .I1(device_temp_101[8]),\n .I2(device_temp_101[9]),\n .I3(three_inc_min_limit[9]),\n .O(temp_cmp_three_inc_min_102_i_4_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_inc_min_102_i_5\n (.I0(three_inc_min_limit[10]),\n .I1(device_temp_101[10]),\n .I2(three_inc_min_limit[11]),\n .I3(device_temp_101[11]),\n .O(temp_cmp_three_inc_min_102_i_5_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_inc_min_102_i_6\n (.I0(three_inc_min_limit[8]),\n .I1(device_temp_101[8]),\n .I2(three_inc_min_limit[9]),\n .I3(device_temp_101[9]),\n .O(temp_cmp_three_inc_min_102_i_6_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_inc_min_102_i_7\n (.I0(three_inc_min_limit[6]),\n .I1(device_temp_101[6]),\n .I2(device_temp_101[7]),\n .I3(three_inc_min_limit[7]),\n .O(temp_cmp_three_inc_min_102_i_7_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_inc_min_102_i_8\n (.I0(three_inc_min_limit[4]),\n .I1(device_temp_101[4]),\n .I2(device_temp_101[5]),\n .I3(three_inc_min_limit[5]),\n .O(temp_cmp_three_inc_min_102_i_8_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_inc_min_102_i_9\n (.I0(three_inc_min_limit[2]),\n .I1(device_temp_101[2]),\n .I2(device_temp_101[3]),\n .I3(three_inc_min_limit[3]),\n .O(temp_cmp_three_inc_min_102_i_9_n_0));\n FDRE #(\n .INIT(1'b0)) \n temp_cmp_three_inc_min_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(temp_cmp_three_inc_min_101),\n .Q(temp_cmp_three_inc_min_102),\n .R(1'b0));\n CARRY4 temp_cmp_three_inc_min_102_reg_i_1\n (.CI(temp_cmp_three_inc_min_102_reg_i_2_n_0),\n .CO({NLW_temp_cmp_three_inc_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_three_inc_min_101,temp_cmp_three_inc_min_102_reg_i_1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,temp_cmp_three_inc_min_102_i_3_n_0,temp_cmp_three_inc_min_102_i_4_n_0}),\n .O(NLW_temp_cmp_three_inc_min_102_reg_i_1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,temp_cmp_three_inc_min_102_i_5_n_0,temp_cmp_three_inc_min_102_i_6_n_0}));\n CARRY4 temp_cmp_three_inc_min_102_reg_i_2\n (.CI(1'b0),\n .CO({temp_cmp_three_inc_min_102_reg_i_2_n_0,temp_cmp_three_inc_min_102_reg_i_2_n_1,temp_cmp_three_inc_min_102_reg_i_2_n_2,temp_cmp_three_inc_min_102_reg_i_2_n_3}),\n .CYINIT(1'b0),\n .DI({temp_cmp_three_inc_min_102_i_7_n_0,temp_cmp_three_inc_min_102_i_8_n_0,temp_cmp_three_inc_min_102_i_9_n_0,temp_cmp_three_inc_min_102_i_10_n_0}),\n .O(NLW_temp_cmp_three_inc_min_102_reg_i_2_O_UNCONNECTED[3:0]),\n .S({temp_cmp_three_inc_min_102_i_11_n_0,temp_cmp_three_inc_min_102_i_12_n_0,temp_cmp_three_inc_min_102_i_13_n_0,temp_cmp_three_inc_min_102_i_14_n_0}));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_dec_max_102_i_10\n (.I0(device_temp_101[0]),\n .I1(two_dec_max_limit[0]),\n .I2(two_dec_max_limit[1]),\n .I3(device_temp_101[1]),\n .O(temp_cmp_two_dec_max_102_i_10_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_dec_max_102_i_11\n (.I0(device_temp_101[6]),\n .I1(two_dec_max_limit[6]),\n .I2(device_temp_101[7]),\n .I3(two_dec_max_limit[7]),\n .O(temp_cmp_two_dec_max_102_i_11_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_dec_max_102_i_12\n (.I0(device_temp_101[4]),\n .I1(two_dec_max_limit[4]),\n .I2(device_temp_101[5]),\n .I3(two_dec_max_limit[5]),\n .O(temp_cmp_two_dec_max_102_i_12_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_dec_max_102_i_13\n (.I0(device_temp_101[2]),\n .I1(two_dec_max_limit[2]),\n .I2(device_temp_101[3]),\n .I3(two_dec_max_limit[3]),\n .O(temp_cmp_two_dec_max_102_i_13_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_dec_max_102_i_14\n (.I0(device_temp_101[0]),\n .I1(two_dec_max_limit[0]),\n .I2(device_temp_101[1]),\n .I3(two_dec_max_limit[1]),\n .O(temp_cmp_two_dec_max_102_i_14_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_dec_max_102_i_3\n (.I0(device_temp_101[10]),\n .I1(two_dec_max_limit[10]),\n .I2(two_dec_max_limit[11]),\n .I3(device_temp_101[11]),\n .O(temp_cmp_two_dec_max_102_i_3_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_dec_max_102_i_4\n (.I0(device_temp_101[8]),\n .I1(two_dec_max_limit[8]),\n .I2(two_dec_max_limit[9]),\n .I3(device_temp_101[9]),\n .O(temp_cmp_two_dec_max_102_i_4_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_dec_max_102_i_5\n (.I0(device_temp_101[10]),\n .I1(two_dec_max_limit[10]),\n .I2(device_temp_101[11]),\n .I3(two_dec_max_limit[11]),\n .O(temp_cmp_two_dec_max_102_i_5_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_dec_max_102_i_6\n (.I0(device_temp_101[8]),\n .I1(two_dec_max_limit[8]),\n .I2(device_temp_101[9]),\n .I3(two_dec_max_limit[9]),\n .O(temp_cmp_two_dec_max_102_i_6_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_dec_max_102_i_7\n (.I0(device_temp_101[6]),\n .I1(two_dec_max_limit[6]),\n .I2(two_dec_max_limit[7]),\n .I3(device_temp_101[7]),\n .O(temp_cmp_two_dec_max_102_i_7_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_dec_max_102_i_8\n (.I0(device_temp_101[4]),\n .I1(two_dec_max_limit[4]),\n .I2(two_dec_max_limit[5]),\n .I3(device_temp_101[5]),\n .O(temp_cmp_two_dec_max_102_i_8_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_dec_max_102_i_9\n (.I0(device_temp_101[2]),\n .I1(two_dec_max_limit[2]),\n .I2(two_dec_max_limit[3]),\n .I3(device_temp_101[3]),\n .O(temp_cmp_two_dec_max_102_i_9_n_0));\n FDRE #(\n .INIT(1'b0)) \n temp_cmp_two_dec_max_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(temp_cmp_two_dec_max_101),\n .Q(temp_cmp_two_dec_max_102),\n .R(1'b0));\n CARRY4 temp_cmp_two_dec_max_102_reg_i_1\n (.CI(temp_cmp_two_dec_max_102_reg_i_2_n_0),\n .CO({NLW_temp_cmp_two_dec_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_two_dec_max_101,temp_cmp_two_dec_max_102_reg_i_1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,temp_cmp_two_dec_max_102_i_3_n_0,temp_cmp_two_dec_max_102_i_4_n_0}),\n .O(NLW_temp_cmp_two_dec_max_102_reg_i_1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,temp_cmp_two_dec_max_102_i_5_n_0,temp_cmp_two_dec_max_102_i_6_n_0}));\n CARRY4 temp_cmp_two_dec_max_102_reg_i_2\n (.CI(1'b0),\n .CO({temp_cmp_two_dec_max_102_reg_i_2_n_0,temp_cmp_two_dec_max_102_reg_i_2_n_1,temp_cmp_two_dec_max_102_reg_i_2_n_2,temp_cmp_two_dec_max_102_reg_i_2_n_3}),\n .CYINIT(1'b1),\n .DI({temp_cmp_two_dec_max_102_i_7_n_0,temp_cmp_two_dec_max_102_i_8_n_0,temp_cmp_two_dec_max_102_i_9_n_0,temp_cmp_two_dec_max_102_i_10_n_0}),\n .O(NLW_temp_cmp_two_dec_max_102_reg_i_2_O_UNCONNECTED[3:0]),\n .S({temp_cmp_two_dec_max_102_i_11_n_0,temp_cmp_two_dec_max_102_i_12_n_0,temp_cmp_two_dec_max_102_i_13_n_0,temp_cmp_two_dec_max_102_i_14_n_0}));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_dec_min_102_i_10\n (.I0(three_dec_min_limit[0]),\n .I1(device_temp_101[0]),\n .I2(device_temp_101[1]),\n .I3(two_dec_min_limit[1]),\n .O(temp_cmp_two_dec_min_102_i_10_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_dec_min_102_i_11\n (.I0(two_dec_min_limit[6]),\n .I1(device_temp_101[6]),\n .I2(two_dec_min_limit[7]),\n .I3(device_temp_101[7]),\n .O(temp_cmp_two_dec_min_102_i_11_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_dec_min_102_i_12\n (.I0(two_dec_min_limit[4]),\n .I1(device_temp_101[4]),\n .I2(two_dec_min_limit[5]),\n .I3(device_temp_101[5]),\n .O(temp_cmp_two_dec_min_102_i_12_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_dec_min_102_i_13\n (.I0(two_dec_min_limit[2]),\n .I1(device_temp_101[2]),\n .I2(two_dec_min_limit[3]),\n .I3(device_temp_101[3]),\n .O(temp_cmp_two_dec_min_102_i_13_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_dec_min_102_i_14\n (.I0(three_dec_min_limit[0]),\n .I1(device_temp_101[0]),\n .I2(two_dec_min_limit[1]),\n .I3(device_temp_101[1]),\n .O(temp_cmp_two_dec_min_102_i_14_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_dec_min_102_i_3\n (.I0(two_dec_min_limit[10]),\n .I1(device_temp_101[10]),\n .I2(device_temp_101[11]),\n .I3(two_dec_min_limit[11]),\n .O(temp_cmp_two_dec_min_102_i_3_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_dec_min_102_i_4\n (.I0(two_dec_min_limit[8]),\n .I1(device_temp_101[8]),\n .I2(device_temp_101[9]),\n .I3(two_dec_min_limit[9]),\n .O(temp_cmp_two_dec_min_102_i_4_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_dec_min_102_i_5\n (.I0(two_dec_min_limit[10]),\n .I1(device_temp_101[10]),\n .I2(two_dec_min_limit[11]),\n .I3(device_temp_101[11]),\n .O(temp_cmp_two_dec_min_102_i_5_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_dec_min_102_i_6\n (.I0(two_dec_min_limit[8]),\n .I1(device_temp_101[8]),\n .I2(two_dec_min_limit[9]),\n .I3(device_temp_101[9]),\n .O(temp_cmp_two_dec_min_102_i_6_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_dec_min_102_i_7\n (.I0(two_dec_min_limit[6]),\n .I1(device_temp_101[6]),\n .I2(device_temp_101[7]),\n .I3(two_dec_min_limit[7]),\n .O(temp_cmp_two_dec_min_102_i_7_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_dec_min_102_i_8\n (.I0(two_dec_min_limit[4]),\n .I1(device_temp_101[4]),\n .I2(device_temp_101[5]),\n .I3(two_dec_min_limit[5]),\n .O(temp_cmp_two_dec_min_102_i_8_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_dec_min_102_i_9\n (.I0(two_dec_min_limit[2]),\n .I1(device_temp_101[2]),\n .I2(device_temp_101[3]),\n .I3(two_dec_min_limit[3]),\n .O(temp_cmp_two_dec_min_102_i_9_n_0));\n FDRE #(\n .INIT(1'b0)) \n temp_cmp_two_dec_min_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(temp_cmp_two_dec_min_101),\n .Q(temp_cmp_two_dec_min_102),\n .R(1'b0));\n CARRY4 temp_cmp_two_dec_min_102_reg_i_1\n (.CI(temp_cmp_two_dec_min_102_reg_i_2_n_0),\n .CO({NLW_temp_cmp_two_dec_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_two_dec_min_101,temp_cmp_two_dec_min_102_reg_i_1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,temp_cmp_two_dec_min_102_i_3_n_0,temp_cmp_two_dec_min_102_i_4_n_0}),\n .O(NLW_temp_cmp_two_dec_min_102_reg_i_1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,temp_cmp_two_dec_min_102_i_5_n_0,temp_cmp_two_dec_min_102_i_6_n_0}));\n CARRY4 temp_cmp_two_dec_min_102_reg_i_2\n (.CI(1'b0),\n .CO({temp_cmp_two_dec_min_102_reg_i_2_n_0,temp_cmp_two_dec_min_102_reg_i_2_n_1,temp_cmp_two_dec_min_102_reg_i_2_n_2,temp_cmp_two_dec_min_102_reg_i_2_n_3}),\n .CYINIT(1'b0),\n .DI({temp_cmp_two_dec_min_102_i_7_n_0,temp_cmp_two_dec_min_102_i_8_n_0,temp_cmp_two_dec_min_102_i_9_n_0,temp_cmp_two_dec_min_102_i_10_n_0}),\n .O(NLW_temp_cmp_two_dec_min_102_reg_i_2_O_UNCONNECTED[3:0]),\n .S({temp_cmp_two_dec_min_102_i_11_n_0,temp_cmp_two_dec_min_102_i_12_n_0,temp_cmp_two_dec_min_102_i_13_n_0,temp_cmp_two_dec_min_102_i_14_n_0}));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_inc_max_102_i_10\n (.I0(device_temp_101[0]),\n .I1(two_dec_max_limit[0]),\n .I2(two_inc_max_limit[1]),\n .I3(device_temp_101[1]),\n .O(temp_cmp_two_inc_max_102_i_10_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_inc_max_102_i_11\n (.I0(device_temp_101[6]),\n .I1(two_inc_max_limit[6]),\n .I2(device_temp_101[7]),\n .I3(two_inc_max_limit[7]),\n .O(temp_cmp_two_inc_max_102_i_11_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_inc_max_102_i_12\n (.I0(device_temp_101[4]),\n .I1(two_inc_max_limit[4]),\n .I2(device_temp_101[5]),\n .I3(two_inc_max_limit[5]),\n .O(temp_cmp_two_inc_max_102_i_12_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_inc_max_102_i_13\n (.I0(device_temp_101[2]),\n .I1(two_inc_max_limit[2]),\n .I2(device_temp_101[3]),\n .I3(two_inc_max_limit[3]),\n .O(temp_cmp_two_inc_max_102_i_13_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_inc_max_102_i_14\n (.I0(device_temp_101[0]),\n .I1(two_dec_max_limit[0]),\n .I2(device_temp_101[1]),\n .I3(two_inc_max_limit[1]),\n .O(temp_cmp_two_inc_max_102_i_14_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_inc_max_102_i_3\n (.I0(device_temp_101[10]),\n .I1(two_inc_max_limit[10]),\n .I2(two_inc_max_limit[11]),\n .I3(device_temp_101[11]),\n .O(temp_cmp_two_inc_max_102_i_3_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_inc_max_102_i_4\n (.I0(device_temp_101[8]),\n .I1(two_inc_max_limit[8]),\n .I2(two_inc_max_limit[9]),\n .I3(device_temp_101[9]),\n .O(temp_cmp_two_inc_max_102_i_4_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_inc_max_102_i_5\n (.I0(device_temp_101[10]),\n .I1(two_inc_max_limit[10]),\n .I2(device_temp_101[11]),\n .I3(two_inc_max_limit[11]),\n .O(temp_cmp_two_inc_max_102_i_5_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_inc_max_102_i_6\n (.I0(device_temp_101[8]),\n .I1(two_inc_max_limit[8]),\n .I2(device_temp_101[9]),\n .I3(two_inc_max_limit[9]),\n .O(temp_cmp_two_inc_max_102_i_6_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_inc_max_102_i_7\n (.I0(device_temp_101[6]),\n .I1(two_inc_max_limit[6]),\n .I2(two_inc_max_limit[7]),\n .I3(device_temp_101[7]),\n .O(temp_cmp_two_inc_max_102_i_7_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_inc_max_102_i_8\n (.I0(device_temp_101[4]),\n .I1(two_inc_max_limit[4]),\n .I2(two_inc_max_limit[5]),\n .I3(device_temp_101[5]),\n .O(temp_cmp_two_inc_max_102_i_8_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_inc_max_102_i_9\n (.I0(device_temp_101[2]),\n .I1(two_inc_max_limit[2]),\n .I2(two_inc_max_limit[3]),\n .I3(device_temp_101[3]),\n .O(temp_cmp_two_inc_max_102_i_9_n_0));\n FDRE #(\n .INIT(1'b0)) \n temp_cmp_two_inc_max_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(temp_cmp_two_inc_max_101),\n .Q(temp_cmp_two_inc_max_102),\n .R(1'b0));\n CARRY4 temp_cmp_two_inc_max_102_reg_i_1\n (.CI(temp_cmp_two_inc_max_102_reg_i_2_n_0),\n .CO({NLW_temp_cmp_two_inc_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_two_inc_max_101,temp_cmp_two_inc_max_102_reg_i_1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,temp_cmp_two_inc_max_102_i_3_n_0,temp_cmp_two_inc_max_102_i_4_n_0}),\n .O(NLW_temp_cmp_two_inc_max_102_reg_i_1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,temp_cmp_two_inc_max_102_i_5_n_0,temp_cmp_two_inc_max_102_i_6_n_0}));\n CARRY4 temp_cmp_two_inc_max_102_reg_i_2\n (.CI(1'b0),\n .CO({temp_cmp_two_inc_max_102_reg_i_2_n_0,temp_cmp_two_inc_max_102_reg_i_2_n_1,temp_cmp_two_inc_max_102_reg_i_2_n_2,temp_cmp_two_inc_max_102_reg_i_2_n_3}),\n .CYINIT(1'b1),\n .DI({temp_cmp_two_inc_max_102_i_7_n_0,temp_cmp_two_inc_max_102_i_8_n_0,temp_cmp_two_inc_max_102_i_9_n_0,temp_cmp_two_inc_max_102_i_10_n_0}),\n .O(NLW_temp_cmp_two_inc_max_102_reg_i_2_O_UNCONNECTED[3:0]),\n .S({temp_cmp_two_inc_max_102_i_11_n_0,temp_cmp_two_inc_max_102_i_12_n_0,temp_cmp_two_inc_max_102_i_13_n_0,temp_cmp_two_inc_max_102_i_14_n_0}));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_inc_min_102_i_10\n (.I0(three_dec_min_limit[0]),\n .I1(device_temp_101[0]),\n .I2(device_temp_101[1]),\n .I3(two_inc_min_limit[1]),\n .O(temp_cmp_two_inc_min_102_i_10_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_inc_min_102_i_11\n (.I0(two_inc_min_limit[6]),\n .I1(device_temp_101[6]),\n .I2(two_inc_min_limit[7]),\n .I3(device_temp_101[7]),\n .O(temp_cmp_two_inc_min_102_i_11_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_inc_min_102_i_12\n (.I0(two_inc_min_limit[4]),\n .I1(device_temp_101[4]),\n .I2(two_inc_min_limit[5]),\n .I3(device_temp_101[5]),\n .O(temp_cmp_two_inc_min_102_i_12_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_inc_min_102_i_13\n (.I0(two_inc_min_limit[2]),\n .I1(device_temp_101[2]),\n .I2(two_inc_min_limit[3]),\n .I3(device_temp_101[3]),\n .O(temp_cmp_two_inc_min_102_i_13_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_inc_min_102_i_14\n (.I0(three_dec_min_limit[0]),\n .I1(device_temp_101[0]),\n .I2(two_inc_min_limit[1]),\n .I3(device_temp_101[1]),\n .O(temp_cmp_two_inc_min_102_i_14_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_inc_min_102_i_3\n (.I0(two_inc_min_limit[10]),\n .I1(device_temp_101[10]),\n .I2(device_temp_101[11]),\n .I3(two_inc_min_limit[11]),\n .O(temp_cmp_two_inc_min_102_i_3_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_inc_min_102_i_4\n (.I0(two_inc_min_limit[8]),\n .I1(device_temp_101[8]),\n .I2(device_temp_101[9]),\n .I3(two_inc_min_limit[9]),\n .O(temp_cmp_two_inc_min_102_i_4_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_inc_min_102_i_5\n (.I0(two_inc_min_limit[10]),\n .I1(device_temp_101[10]),\n .I2(two_inc_min_limit[11]),\n .I3(device_temp_101[11]),\n .O(temp_cmp_two_inc_min_102_i_5_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_inc_min_102_i_6\n (.I0(two_inc_min_limit[8]),\n .I1(device_temp_101[8]),\n .I2(two_inc_min_limit[9]),\n .I3(device_temp_101[9]),\n .O(temp_cmp_two_inc_min_102_i_6_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_inc_min_102_i_7\n (.I0(two_inc_min_limit[6]),\n .I1(device_temp_101[6]),\n .I2(device_temp_101[7]),\n .I3(two_inc_min_limit[7]),\n .O(temp_cmp_two_inc_min_102_i_7_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_inc_min_102_i_8\n (.I0(two_inc_min_limit[4]),\n .I1(device_temp_101[4]),\n .I2(device_temp_101[5]),\n .I3(two_inc_min_limit[5]),\n .O(temp_cmp_two_inc_min_102_i_8_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_inc_min_102_i_9\n (.I0(two_inc_min_limit[2]),\n .I1(device_temp_101[2]),\n .I2(device_temp_101[3]),\n .I3(two_inc_min_limit[3]),\n .O(temp_cmp_two_inc_min_102_i_9_n_0));\n FDRE #(\n .INIT(1'b0)) \n temp_cmp_two_inc_min_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(temp_cmp_two_inc_min_101),\n .Q(temp_cmp_two_inc_min_102),\n .R(1'b0));\n CARRY4 temp_cmp_two_inc_min_102_reg_i_1\n (.CI(temp_cmp_two_inc_min_102_reg_i_2_n_0),\n .CO({NLW_temp_cmp_two_inc_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_two_inc_min_101,temp_cmp_two_inc_min_102_reg_i_1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,temp_cmp_two_inc_min_102_i_3_n_0,temp_cmp_two_inc_min_102_i_4_n_0}),\n .O(NLW_temp_cmp_two_inc_min_102_reg_i_1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,temp_cmp_two_inc_min_102_i_5_n_0,temp_cmp_two_inc_min_102_i_6_n_0}));\n CARRY4 temp_cmp_two_inc_min_102_reg_i_2\n (.CI(1'b0),\n .CO({temp_cmp_two_inc_min_102_reg_i_2_n_0,temp_cmp_two_inc_min_102_reg_i_2_n_1,temp_cmp_two_inc_min_102_reg_i_2_n_2,temp_cmp_two_inc_min_102_reg_i_2_n_3}),\n .CYINIT(1'b0),\n .DI({temp_cmp_two_inc_min_102_i_7_n_0,temp_cmp_two_inc_min_102_i_8_n_0,temp_cmp_two_inc_min_102_i_9_n_0,temp_cmp_two_inc_min_102_i_10_n_0}),\n .O(NLW_temp_cmp_two_inc_min_102_reg_i_2_O_UNCONNECTED[3:0]),\n .S({temp_cmp_two_inc_min_102_i_11_n_0,temp_cmp_two_inc_min_102_i_12_n_0,temp_cmp_two_inc_min_102_i_13_n_0,temp_cmp_two_inc_min_102_i_14_n_0}));\n FDRE #(\n .INIT(1'b0)) \n tempmon_init_complete_reg\n (.C(CLK),\n .CE(tempmon_state_init),\n .D(tempmon_state_init),\n .Q(tempmon_init_complete),\n .R(SS));\n (* SOFT_HLUTNM = \"soft_lutpair254\" *) \n LUT2 #(\n .INIT(4'hE)) \n tempmon_pi_f_en_r_i_1\n (.I0(tempmon_pi_f_inc),\n .I1(tempmon_pi_f_dec),\n .O(tempmon_sel_pi_incdec));\n FDRE #(\n .INIT(1'b0)) \n tempmon_sample_en_101_reg\n (.C(CLK),\n .CE(1'b1),\n .D(tempmon_sample_en),\n .Q(tempmon_sample_en_101),\n .R(SS));\n FDRE #(\n .INIT(1'b0)) \n tempmon_sample_en_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(tempmon_sample_en_101),\n .Q(tempmon_sample_en_102),\n .R(SS));\n (* SOFT_HLUTNM = \"soft_lutpair252\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\tempmon_state[0]_i_2 \n (.I0(\\tempmon_state[10]_i_7_n_0 ),\n .O(\\tempmon_state[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFEAFFFFFFFF)) \n \\tempmon_state[10]_i_1 \n (.I0(\\tempmon_state[10]_i_3_n_0 ),\n .I1(\\tempmon_state[10]_i_4_n_0 ),\n .I2(update_temp_102),\n .I3(\\tempmon_state[10]_i_5_n_0 ),\n .I4(\\tempmon_state[10]_i_6_n_0 ),\n .I5(\\tempmon_state[10]_i_7_n_0 ),\n .O(tempmon_state_nxt));\n LUT3 #(\n .INIT(8'h80)) \n \\tempmon_state[10]_i_10 \n (.I0(update_temp_102),\n .I1(temp_cmp_four_dec_min_102),\n .I2(tempmon_state[10]),\n .O(\\tempmon_state[10]_i_10_n_0 ));\n LUT5 #(\n .INIT(32'hF0808080)) \n \\tempmon_state[10]_i_11 \n (.I0(tempmon_state[5]),\n .I1(temp_cmp_one_inc_min_102),\n .I2(update_temp_102),\n .I3(tempmon_state[4]),\n .I4(temp_cmp_two_inc_min_102),\n .O(\\tempmon_state[10]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'hFFEAEAEAEAEAEAEA)) \n \\tempmon_state[10]_i_12 \n (.I0(tempmon_state[1]),\n .I1(calib_complete),\n .I2(tempmon_state[0]),\n .I3(update_temp_102),\n .I4(tempmon_state[9]),\n .I5(temp_cmp_three_dec_min_102),\n .O(\\tempmon_state[10]_i_12_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair250\" *) \n LUT5 #(\n .INIT(32'h00010116)) \n \\tempmon_state[10]_i_13 \n (.I0(tempmon_state[0]),\n .I1(tempmon_state[1]),\n .I2(tempmon_state[2]),\n .I3(tempmon_state[3]),\n .I4(tempmon_state[4]),\n .O(\\tempmon_state[10]_i_13_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair250\" *) \n LUT5 #(\n .INIT(32'hFFFEFEE8)) \n \\tempmon_state[10]_i_14 \n (.I0(tempmon_state[0]),\n .I1(tempmon_state[1]),\n .I2(tempmon_state[2]),\n .I3(tempmon_state[3]),\n .I4(tempmon_state[4]),\n .O(\\tempmon_state[10]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'h0000000100010116)) \n \\tempmon_state[10]_i_15 \n (.I0(tempmon_state[5]),\n .I1(tempmon_state[6]),\n .I2(tempmon_state[7]),\n .I3(tempmon_state[8]),\n .I4(tempmon_state[9]),\n .I5(tempmon_state[10]),\n .O(\\tempmon_state[10]_i_15_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFEFFFEFEE8)) \n \\tempmon_state[10]_i_16 \n (.I0(tempmon_state[5]),\n .I1(tempmon_state[6]),\n .I2(tempmon_state[7]),\n .I3(tempmon_state[8]),\n .I4(tempmon_state[9]),\n .I5(tempmon_state[10]),\n .O(\\tempmon_state[10]_i_16_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair256\" *) \n LUT4 #(\n .INIT(16'h8000)) \n \\tempmon_state[10]_i_2 \n (.I0(tempmon_state[9]),\n .I1(\\tempmon_state[10]_i_7_n_0 ),\n .I2(temp_cmp_three_dec_max_102),\n .I3(update_temp_102),\n .O(\\tempmon_state[10]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFFF80)) \n \\tempmon_state[10]_i_3 \n (.I0(temp_cmp_four_inc_max_102),\n .I1(update_temp_102),\n .I2(tempmon_state[2]),\n .I3(\\tempmon_state[10]_i_8_n_0 ),\n .I4(\\tempmon_state[10]_i_9_n_0 ),\n .O(\\tempmon_state[10]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair249\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\tempmon_state[10]_i_4 \n (.I0(tempmon_state[6]),\n .I1(temp_cmp_neutral_min_102),\n .O(\\tempmon_state[10]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFAAEAAA)) \n \\tempmon_state[10]_i_5 \n (.I0(\\tempmon_state[10]_i_10_n_0 ),\n .I1(tempmon_state[3]),\n .I2(temp_cmp_three_inc_min_102),\n .I3(update_temp_102),\n .I4(pi_f_dec_i_2_n_0),\n .I5(\\tempmon_state[10]_i_11_n_0 ),\n .O(\\tempmon_state[10]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFAAEAAAEAAAEAAA)) \n \\tempmon_state[10]_i_6 \n (.I0(\\tempmon_state[10]_i_12_n_0 ),\n .I1(temp_cmp_one_dec_min_102),\n .I2(tempmon_state[7]),\n .I3(update_temp_102),\n .I4(temp_cmp_two_dec_min_102),\n .I5(tempmon_state[8]),\n .O(\\tempmon_state[10]_i_6_n_0 ));\n LUT4 #(\n .INIT(16'h0012)) \n \\tempmon_state[10]_i_7 \n (.I0(\\tempmon_state[10]_i_13_n_0 ),\n .I1(\\tempmon_state[10]_i_14_n_0 ),\n .I2(\\tempmon_state[10]_i_15_n_0 ),\n .I3(\\tempmon_state[10]_i_16_n_0 ),\n .O(\\tempmon_state[10]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair251\" *) \n LUT5 #(\n .INIT(32'hF0808080)) \n \\tempmon_state[10]_i_8 \n (.I0(temp_cmp_two_dec_max_102),\n .I1(tempmon_state[8]),\n .I2(update_temp_102),\n .I3(temp_cmp_three_dec_max_102),\n .I4(tempmon_state[9]),\n .O(\\tempmon_state[10]_i_8_n_0 ));\n LUT5 #(\n .INIT(32'hF0808080)) \n \\tempmon_state[10]_i_9 \n (.I0(temp_cmp_neutral_max_102),\n .I1(tempmon_state[6]),\n .I2(update_temp_102),\n .I3(temp_cmp_one_dec_max_102),\n .I4(tempmon_state[7]),\n .O(\\tempmon_state[10]_i_9_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair256\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\tempmon_state[1]_i_1 \n (.I0(\\tempmon_state[10]_i_7_n_0 ),\n .I1(tempmon_state[0]),\n .O(\\tempmon_state[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair255\" *) \n LUT4 #(\n .INIT(16'h0888)) \n \\tempmon_state[2]_i_1 \n (.I0(tempmon_state[3]),\n .I1(\\tempmon_state[10]_i_7_n_0 ),\n .I2(update_temp_102),\n .I3(temp_cmp_three_inc_max_102),\n .O(\\tempmon_state[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair248\" *) \n LUT5 #(\n .INIT(32'hFF007000)) \n \\tempmon_state[3]_i_1 \n (.I0(temp_cmp_two_inc_max_102),\n .I1(update_temp_102),\n .I2(tempmon_state[4]),\n .I3(\\tempmon_state[10]_i_7_n_0 ),\n .I4(tempmon_state[2]),\n .O(\\tempmon_state[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8FFF000088000000)) \n \\tempmon_state[4]_i_1 \n (.I0(tempmon_state[3]),\n .I1(temp_cmp_three_inc_max_102),\n .I2(temp_cmp_one_inc_max_102),\n .I3(update_temp_102),\n .I4(\\tempmon_state[10]_i_7_n_0 ),\n .I5(tempmon_state[5]),\n .O(\\tempmon_state[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8FFF000080800000)) \n \\tempmon_state[5]_i_1 \n (.I0(tempmon_state[4]),\n .I1(temp_cmp_two_inc_max_102),\n .I2(update_temp_102),\n .I3(temp_cmp_neutral_max_102),\n .I4(\\tempmon_state[10]_i_7_n_0 ),\n .I5(tempmon_state[6]),\n .O(\\tempmon_state[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFF00EE00AE00EE00)) \n \\tempmon_state[6]_i_1 \n (.I0(tempmon_state[1]),\n .I1(tempmon_state[7]),\n .I2(temp_cmp_one_dec_max_102),\n .I3(\\tempmon_state[10]_i_7_n_0 ),\n .I4(update_temp_102),\n .I5(\\tempmon_state[6]_i_2_n_0 ),\n .O(\\tempmon_state[6]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair253\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\tempmon_state[6]_i_2 \n (.I0(tempmon_state[5]),\n .I1(temp_cmp_one_inc_max_102),\n .O(\\tempmon_state[6]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFC4C00004C4C0000)) \n \\tempmon_state[7]_i_1 \n (.I0(temp_cmp_two_dec_max_102),\n .I1(tempmon_state[8]),\n .I2(update_temp_102),\n .I3(temp_cmp_neutral_max_102),\n .I4(\\tempmon_state[10]_i_7_n_0 ),\n .I5(tempmon_state[6]),\n .O(\\tempmon_state[7]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFC4C00004C4C0000)) \n \\tempmon_state[8]_i_1 \n (.I0(temp_cmp_three_dec_max_102),\n .I1(tempmon_state[9]),\n .I2(update_temp_102),\n .I3(temp_cmp_one_dec_max_102),\n .I4(\\tempmon_state[10]_i_7_n_0 ),\n .I5(tempmon_state[7]),\n .O(\\tempmon_state[8]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFF800000)) \n \\tempmon_state[9]_i_1 \n (.I0(update_temp_102),\n .I1(temp_cmp_two_dec_max_102),\n .I2(tempmon_state[8]),\n .I3(tempmon_state[10]),\n .I4(\\tempmon_state[10]_i_7_n_0 ),\n .O(\\tempmon_state[9]_i_1_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\tempmon_state_reg[0] \n (.C(CLK),\n .CE(tempmon_state_nxt),\n .D(\\tempmon_state[0]_i_2_n_0 ),\n .Q(tempmon_state[0]),\n .S(SS));\n FDRE #(\n .INIT(1'b0)) \n \\tempmon_state_reg[10] \n (.C(CLK),\n .CE(tempmon_state_nxt),\n .D(\\tempmon_state[10]_i_2_n_0 ),\n .Q(tempmon_state[10]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\tempmon_state_reg[1] \n (.C(CLK),\n .CE(tempmon_state_nxt),\n .D(\\tempmon_state[1]_i_1_n_0 ),\n .Q(tempmon_state[1]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\tempmon_state_reg[2] \n (.C(CLK),\n .CE(tempmon_state_nxt),\n .D(\\tempmon_state[2]_i_1_n_0 ),\n .Q(tempmon_state[2]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\tempmon_state_reg[3] \n (.C(CLK),\n .CE(tempmon_state_nxt),\n .D(\\tempmon_state[3]_i_1_n_0 ),\n .Q(tempmon_state[3]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\tempmon_state_reg[4] \n (.C(CLK),\n .CE(tempmon_state_nxt),\n .D(\\tempmon_state[4]_i_1_n_0 ),\n .Q(tempmon_state[4]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\tempmon_state_reg[5] \n (.C(CLK),\n .CE(tempmon_state_nxt),\n .D(\\tempmon_state[5]_i_1_n_0 ),\n .Q(tempmon_state[5]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\tempmon_state_reg[6] \n (.C(CLK),\n .CE(tempmon_state_nxt),\n .D(\\tempmon_state[6]_i_1_n_0 ),\n .Q(tempmon_state[6]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\tempmon_state_reg[7] \n (.C(CLK),\n .CE(tempmon_state_nxt),\n .D(\\tempmon_state[7]_i_1_n_0 ),\n .Q(tempmon_state[7]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\tempmon_state_reg[8] \n (.C(CLK),\n .CE(tempmon_state_nxt),\n .D(\\tempmon_state[8]_i_1_n_0 ),\n .Q(tempmon_state[8]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\tempmon_state_reg[9] \n (.C(CLK),\n .CE(tempmon_state_nxt),\n .D(\\tempmon_state[9]_i_1_n_0 ),\n .Q(tempmon_state[9]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n (* SOFT_HLUTNM = \"soft_lutpair257\" *) \n LUT2 #(\n .INIT(4'hB)) \n \\three_dec_max_limit[0]_i_1 \n (.I0(p_0_in),\n .I1(device_temp_init[0]),\n .O(\\three_dec_max_limit[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair257\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\three_dec_max_limit[10]_i_1 \n (.I0(\\three_dec_max_limit_reg[11]_i_2_n_6 ),\n .I1(p_0_in),\n .O(\\three_dec_max_limit[10]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair259\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\three_dec_max_limit[11]_i_1 \n (.I0(\\three_dec_max_limit_reg[11]_i_2_n_5 ),\n .I1(p_0_in),\n .O(\\three_dec_max_limit[11]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\three_dec_max_limit[11]_i_3 \n (.I0(device_temp_init[11]),\n .O(\\three_dec_max_limit[11]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\three_dec_max_limit[11]_i_4 \n (.I0(device_temp_init[10]),\n .O(\\three_dec_max_limit[11]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_dec_max_limit[11]_i_5 \n (.I0(device_temp_init[9]),\n .O(\\three_dec_max_limit[11]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair262\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\three_dec_max_limit[1]_i_1 \n (.I0(\\three_dec_max_limit_reg[1]_i_2_n_0 ),\n .I1(p_0_in),\n .O(\\three_dec_max_limit[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair262\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\three_dec_max_limit[2]_i_1 \n (.I0(\\three_dec_max_limit_reg[4]_i_2_n_6 ),\n .I1(p_0_in),\n .O(\\three_dec_max_limit[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair258\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\three_dec_max_limit[3]_i_1 \n (.I0(\\three_dec_max_limit_reg[4]_i_2_n_5 ),\n .I1(p_0_in),\n .O(\\three_dec_max_limit[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair261\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\three_dec_max_limit[4]_i_1 \n (.I0(\\three_dec_max_limit_reg[4]_i_2_n_4 ),\n .I1(p_0_in),\n .O(\\three_dec_max_limit[4]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\three_dec_max_limit[4]_i_3 \n (.I0(device_temp_init[4]),\n .O(\\three_dec_max_limit[4]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\three_dec_max_limit[4]_i_4 \n (.I0(device_temp_init[3]),\n .O(\\three_dec_max_limit[4]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\three_dec_max_limit[4]_i_5 \n (.I0(device_temp_init[2]),\n .O(\\three_dec_max_limit[4]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\three_dec_max_limit[4]_i_6 \n (.I0(device_temp_init[1]),\n .O(\\three_dec_max_limit[4]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair261\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\three_dec_max_limit[5]_i_1 \n (.I0(\\three_dec_max_limit_reg[8]_i_2_n_7 ),\n .I1(p_0_in),\n .O(\\three_dec_max_limit[5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair258\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\three_dec_max_limit[6]_i_1 \n (.I0(\\three_dec_max_limit_reg[8]_i_2_n_6 ),\n .I1(p_0_in),\n .O(\\three_dec_max_limit[6]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair260\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\three_dec_max_limit[7]_i_1 \n (.I0(\\three_dec_max_limit_reg[8]_i_2_n_5 ),\n .I1(p_0_in),\n .O(\\three_dec_max_limit[7]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair259\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\three_dec_max_limit[8]_i_1 \n (.I0(\\three_dec_max_limit_reg[8]_i_2_n_4 ),\n .I1(p_0_in),\n .O(\\three_dec_max_limit[8]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_dec_max_limit[8]_i_3 \n (.I0(device_temp_init[8]),\n .O(\\three_dec_max_limit[8]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\three_dec_max_limit[8]_i_4 \n (.I0(device_temp_init[7]),\n .O(\\three_dec_max_limit[8]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_dec_max_limit[8]_i_5 \n (.I0(device_temp_init[6]),\n .O(\\three_dec_max_limit[8]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\three_dec_max_limit[8]_i_6 \n (.I0(device_temp_init[5]),\n .O(\\three_dec_max_limit[8]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair260\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\three_dec_max_limit[9]_i_1 \n (.I0(\\three_dec_max_limit_reg[11]_i_2_n_7 ),\n .I1(p_0_in),\n .O(\\three_dec_max_limit[9]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\three_dec_max_limit_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\three_dec_max_limit[0]_i_1_n_0 ),\n .Q(three_dec_max_limit[0]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE #(\n .INIT(1'b0)) \n \\three_dec_max_limit_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(\\three_dec_max_limit[10]_i_1_n_0 ),\n .Q(three_dec_max_limit[10]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE #(\n .INIT(1'b0)) \n \\three_dec_max_limit_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(\\three_dec_max_limit[11]_i_1_n_0 ),\n .Q(three_dec_max_limit[11]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n CARRY4 \\three_dec_max_limit_reg[11]_i_2 \n (.CI(\\three_dec_max_limit_reg[8]_i_2_n_0 ),\n .CO({p_0_in,\\NLW_three_dec_max_limit_reg[11]_i_2_CO_UNCONNECTED [2],\\three_dec_max_limit_reg[11]_i_2_n_2 ,\\three_dec_max_limit_reg[11]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,device_temp_init[9]}),\n .O({\\NLW_three_dec_max_limit_reg[11]_i_2_O_UNCONNECTED [3],\\three_dec_max_limit_reg[11]_i_2_n_5 ,\\three_dec_max_limit_reg[11]_i_2_n_6 ,\\three_dec_max_limit_reg[11]_i_2_n_7 }),\n .S({1'b1,\\three_dec_max_limit[11]_i_3_n_0 ,\\three_dec_max_limit[11]_i_4_n_0 ,\\three_dec_max_limit[11]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\three_dec_max_limit_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\three_dec_max_limit[1]_i_1_n_0 ),\n .Q(three_dec_max_limit[1]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n (* XILINX_LEGACY_PRIM = \"(MUXCY,XORCY)\" *) \n CARRY4 \\three_dec_max_limit_reg[1]_i_2_CARRY4 \n (.CI(1'b0),\n .CO(\\NLW_three_dec_max_limit_reg[1]_i_2_CARRY4_CO_UNCONNECTED [3:0]),\n .CYINIT(device_temp_init[0]),\n .DI(\\NLW_three_dec_max_limit_reg[1]_i_2_CARRY4_DI_UNCONNECTED [3:0]),\n .O({\\NLW_three_dec_max_limit_reg[1]_i_2_CARRY4_O_UNCONNECTED [3:1],\\three_dec_max_limit_reg[1]_i_2_n_0 }),\n .S({\\NLW_three_dec_max_limit_reg[1]_i_2_CARRY4_S_UNCONNECTED [3:1],device_temp_init[1]}));\n FDRE #(\n .INIT(1'b0)) \n \\three_dec_max_limit_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\three_dec_max_limit[2]_i_1_n_0 ),\n .Q(three_dec_max_limit[2]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE #(\n .INIT(1'b0)) \n \\three_dec_max_limit_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\three_dec_max_limit[3]_i_1_n_0 ),\n .Q(three_dec_max_limit[3]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE #(\n .INIT(1'b0)) \n \\three_dec_max_limit_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\three_dec_max_limit[4]_i_1_n_0 ),\n .Q(three_dec_max_limit[4]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n CARRY4 \\three_dec_max_limit_reg[4]_i_2 \n (.CI(1'b0),\n .CO({\\three_dec_max_limit_reg[4]_i_2_n_0 ,\\three_dec_max_limit_reg[4]_i_2_n_1 ,\\three_dec_max_limit_reg[4]_i_2_n_2 ,\\three_dec_max_limit_reg[4]_i_2_n_3 }),\n .CYINIT(device_temp_init[0]),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\three_dec_max_limit_reg[4]_i_2_n_4 ,\\three_dec_max_limit_reg[4]_i_2_n_5 ,\\three_dec_max_limit_reg[4]_i_2_n_6 ,\\NLW_three_dec_max_limit_reg[4]_i_2_O_UNCONNECTED [0]}),\n .S({\\three_dec_max_limit[4]_i_3_n_0 ,\\three_dec_max_limit[4]_i_4_n_0 ,\\three_dec_max_limit[4]_i_5_n_0 ,\\three_dec_max_limit[4]_i_6_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\three_dec_max_limit_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\three_dec_max_limit[5]_i_1_n_0 ),\n .Q(three_dec_max_limit[5]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE #(\n .INIT(1'b0)) \n \\three_dec_max_limit_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\three_dec_max_limit[6]_i_1_n_0 ),\n .Q(three_dec_max_limit[6]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE #(\n .INIT(1'b0)) \n \\three_dec_max_limit_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\three_dec_max_limit[7]_i_1_n_0 ),\n .Q(three_dec_max_limit[7]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE #(\n .INIT(1'b0)) \n \\three_dec_max_limit_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(\\three_dec_max_limit[8]_i_1_n_0 ),\n .Q(three_dec_max_limit[8]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n CARRY4 \\three_dec_max_limit_reg[8]_i_2 \n (.CI(\\three_dec_max_limit_reg[4]_i_2_n_0 ),\n .CO({\\three_dec_max_limit_reg[8]_i_2_n_0 ,\\three_dec_max_limit_reg[8]_i_2_n_1 ,\\three_dec_max_limit_reg[8]_i_2_n_2 ,\\three_dec_max_limit_reg[8]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({device_temp_init[8],1'b0,device_temp_init[6],1'b0}),\n .O({\\three_dec_max_limit_reg[8]_i_2_n_4 ,\\three_dec_max_limit_reg[8]_i_2_n_5 ,\\three_dec_max_limit_reg[8]_i_2_n_6 ,\\three_dec_max_limit_reg[8]_i_2_n_7 }),\n .S({\\three_dec_max_limit[8]_i_3_n_0 ,\\three_dec_max_limit[8]_i_4_n_0 ,\\three_dec_max_limit[8]_i_5_n_0 ,\\three_dec_max_limit[8]_i_6_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\three_dec_max_limit_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(\\three_dec_max_limit[9]_i_1_n_0 ),\n .Q(three_dec_max_limit[9]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n LUT1 #(\n .INIT(2'h1)) \n \\three_dec_min_limit[11]_i_2 \n (.I0(two_dec_max_limit[11]),\n .O(\\three_dec_min_limit[11]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_dec_min_limit[11]_i_3 \n (.I0(two_dec_max_limit[10]),\n .O(\\three_dec_min_limit[11]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_dec_min_limit[5]_i_2 \n (.I0(two_dec_max_limit[5]),\n .O(\\three_dec_min_limit[5]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_dec_min_limit[5]_i_3 \n (.I0(two_dec_max_limit[4]),\n .O(\\three_dec_min_limit[5]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_dec_min_limit[5]_i_4 \n (.I0(two_dec_max_limit[3]),\n .O(\\three_dec_min_limit[5]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\three_dec_min_limit[5]_i_5 \n (.I0(two_dec_max_limit[2]),\n .O(\\three_dec_min_limit[5]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_dec_min_limit[9]_i_2 \n (.I0(two_dec_max_limit[9]),\n .O(\\three_dec_min_limit[9]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_dec_min_limit[9]_i_3 \n (.I0(two_dec_max_limit[8]),\n .O(\\three_dec_min_limit[9]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_dec_min_limit[9]_i_4 \n (.I0(two_dec_max_limit[7]),\n .O(\\three_dec_min_limit[9]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_dec_min_limit[9]_i_5 \n (.I0(two_dec_max_limit[6]),\n .O(\\three_dec_min_limit[9]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\three_dec_min_limit_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_max_limit[0]),\n .Q(three_dec_min_limit[0]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE #(\n .INIT(1'b0)) \n \\three_dec_min_limit_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(three_dec_min_limit_nxt[10]),\n .Q(three_dec_min_limit[10]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE #(\n .INIT(1'b0)) \n \\three_dec_min_limit_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(three_dec_min_limit_nxt[11]),\n .Q(three_dec_min_limit[11]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n CARRY4 \\three_dec_min_limit_reg[11]_i_1 \n (.CI(\\three_dec_min_limit_reg[9]_i_1_n_0 ),\n .CO({\\NLW_three_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\\three_dec_min_limit_reg[11]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,two_dec_max_limit[10]}),\n .O({\\NLW_three_dec_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],three_dec_min_limit_nxt[11:10]}),\n .S({1'b0,1'b0,\\three_dec_min_limit[11]_i_2_n_0 ,\\three_dec_min_limit[11]_i_3_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\three_dec_min_limit_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_max_limit[1]),\n .Q(three_dec_min_limit[1]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE #(\n .INIT(1'b0)) \n \\three_dec_min_limit_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(three_dec_min_limit_nxt[2]),\n .Q(three_dec_min_limit[2]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE #(\n .INIT(1'b0)) \n \\three_dec_min_limit_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(three_dec_min_limit_nxt[3]),\n .Q(three_dec_min_limit[3]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE #(\n .INIT(1'b0)) \n \\three_dec_min_limit_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(three_dec_min_limit_nxt[4]),\n .Q(three_dec_min_limit[4]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE #(\n .INIT(1'b0)) \n \\three_dec_min_limit_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(three_dec_min_limit_nxt[5]),\n .Q(three_dec_min_limit[5]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n CARRY4 \\three_dec_min_limit_reg[5]_i_1 \n (.CI(1'b0),\n .CO({\\three_dec_min_limit_reg[5]_i_1_n_0 ,\\three_dec_min_limit_reg[5]_i_1_n_1 ,\\three_dec_min_limit_reg[5]_i_1_n_2 ,\\three_dec_min_limit_reg[5]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({two_dec_max_limit[5:3],1'b0}),\n .O(three_dec_min_limit_nxt[5:2]),\n .S({\\three_dec_min_limit[5]_i_2_n_0 ,\\three_dec_min_limit[5]_i_3_n_0 ,\\three_dec_min_limit[5]_i_4_n_0 ,\\three_dec_min_limit[5]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\three_dec_min_limit_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(three_dec_min_limit_nxt[6]),\n .Q(three_dec_min_limit[6]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE #(\n .INIT(1'b0)) \n \\three_dec_min_limit_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(three_dec_min_limit_nxt[7]),\n .Q(three_dec_min_limit[7]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE #(\n .INIT(1'b0)) \n \\three_dec_min_limit_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(three_dec_min_limit_nxt[8]),\n .Q(three_dec_min_limit[8]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE #(\n .INIT(1'b0)) \n \\three_dec_min_limit_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(three_dec_min_limit_nxt[9]),\n .Q(three_dec_min_limit[9]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n CARRY4 \\three_dec_min_limit_reg[9]_i_1 \n (.CI(\\three_dec_min_limit_reg[5]_i_1_n_0 ),\n .CO({\\three_dec_min_limit_reg[9]_i_1_n_0 ,\\three_dec_min_limit_reg[9]_i_1_n_1 ,\\three_dec_min_limit_reg[9]_i_1_n_2 ,\\three_dec_min_limit_reg[9]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI(two_dec_max_limit[9:6]),\n .O(three_dec_min_limit_nxt[9:6]),\n .S({\\three_dec_min_limit[9]_i_2_n_0 ,\\three_dec_min_limit[9]_i_3_n_0 ,\\three_dec_min_limit[9]_i_4_n_0 ,\\three_dec_min_limit[9]_i_5_n_0 }));\n LUT1 #(\n .INIT(2'h1)) \n \\three_inc_max_limit[11]_i_2 \n (.I0(device_temp_init[11]),\n .O(\\three_inc_max_limit[11]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_inc_max_limit[11]_i_3 \n (.I0(device_temp_init[10]),\n .O(\\three_inc_max_limit[11]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\three_inc_max_limit[11]_i_4 \n (.I0(device_temp_init[9]),\n .O(\\three_inc_max_limit[11]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\three_inc_max_limit[4]_i_2 \n (.I0(device_temp_init[4]),\n .O(\\three_inc_max_limit[4]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_inc_max_limit[4]_i_3 \n (.I0(device_temp_init[3]),\n .O(\\three_inc_max_limit[4]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_inc_max_limit[4]_i_4 \n (.I0(device_temp_init[2]),\n .O(\\three_inc_max_limit[4]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\three_inc_max_limit[4]_i_5 \n (.I0(device_temp_init[1]),\n .O(\\three_inc_max_limit[4]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_inc_max_limit[8]_i_2 \n (.I0(device_temp_init[8]),\n .O(\\three_inc_max_limit[8]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_inc_max_limit[8]_i_3 \n (.I0(device_temp_init[7]),\n .O(\\three_inc_max_limit[8]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\three_inc_max_limit[8]_i_4 \n (.I0(device_temp_init[6]),\n .O(\\three_inc_max_limit[8]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_inc_max_limit[8]_i_5 \n (.I0(device_temp_init[5]),\n .O(\\three_inc_max_limit[8]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\three_inc_max_limit_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_max_limit_nxt[10]),\n .Q(three_inc_max_limit[10]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE #(\n .INIT(1'b0)) \n \\three_inc_max_limit_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_max_limit_nxt[11]),\n .Q(three_inc_max_limit[11]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n CARRY4 \\three_inc_max_limit_reg[11]_i_1 \n (.CI(\\three_inc_max_limit_reg[8]_i_1_n_0 ),\n .CO({\\NLW_three_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\\three_inc_max_limit_reg[11]_i_1_n_2 ,\\three_inc_max_limit_reg[11]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,device_temp_init[10],1'b0}),\n .O({\\NLW_three_inc_max_limit_reg[11]_i_1_O_UNCONNECTED [3],three_inc_max_limit_nxt[11:9]}),\n .S({1'b0,\\three_inc_max_limit[11]_i_2_n_0 ,\\three_inc_max_limit[11]_i_3_n_0 ,\\three_inc_max_limit[11]_i_4_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\three_inc_max_limit_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_max_limit_nxt[1]),\n .Q(three_inc_max_limit[1]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE #(\n .INIT(1'b0)) \n \\three_inc_max_limit_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_max_limit_nxt[2]),\n .Q(three_inc_max_limit[2]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE #(\n .INIT(1'b0)) \n \\three_inc_max_limit_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_max_limit_nxt[3]),\n .Q(three_inc_max_limit[3]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE #(\n .INIT(1'b0)) \n \\three_inc_max_limit_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_max_limit_nxt[4]),\n .Q(three_inc_max_limit[4]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n CARRY4 \\three_inc_max_limit_reg[4]_i_1 \n (.CI(1'b0),\n .CO({\\three_inc_max_limit_reg[4]_i_1_n_0 ,\\three_inc_max_limit_reg[4]_i_1_n_1 ,\\three_inc_max_limit_reg[4]_i_1_n_2 ,\\three_inc_max_limit_reg[4]_i_1_n_3 }),\n .CYINIT(device_temp_init[0]),\n .DI({1'b0,device_temp_init[3:2],1'b0}),\n .O(three_inc_max_limit_nxt[4:1]),\n .S({\\three_inc_max_limit[4]_i_2_n_0 ,\\three_inc_max_limit[4]_i_3_n_0 ,\\three_inc_max_limit[4]_i_4_n_0 ,\\three_inc_max_limit[4]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\three_inc_max_limit_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_max_limit_nxt[5]),\n .Q(three_inc_max_limit[5]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE #(\n .INIT(1'b0)) \n \\three_inc_max_limit_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_max_limit_nxt[6]),\n .Q(three_inc_max_limit[6]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE #(\n .INIT(1'b0)) \n \\three_inc_max_limit_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_max_limit_nxt[7]),\n .Q(three_inc_max_limit[7]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE #(\n .INIT(1'b0)) \n \\three_inc_max_limit_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_max_limit_nxt[8]),\n .Q(three_inc_max_limit[8]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n CARRY4 \\three_inc_max_limit_reg[8]_i_1 \n (.CI(\\three_inc_max_limit_reg[4]_i_1_n_0 ),\n .CO({\\three_inc_max_limit_reg[8]_i_1_n_0 ,\\three_inc_max_limit_reg[8]_i_1_n_1 ,\\three_inc_max_limit_reg[8]_i_1_n_2 ,\\three_inc_max_limit_reg[8]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({device_temp_init[8:7],1'b0,device_temp_init[5]}),\n .O(three_inc_max_limit_nxt[8:5]),\n .S({\\three_inc_max_limit[8]_i_2_n_0 ,\\three_inc_max_limit[8]_i_3_n_0 ,\\three_inc_max_limit[8]_i_4_n_0 ,\\three_inc_max_limit[8]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\three_inc_max_limit_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_max_limit_nxt[9]),\n .Q(three_inc_max_limit[9]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n LUT1 #(\n .INIT(2'h1)) \n \\three_inc_min_limit[11]_i_2 \n (.I0(four_inc_max_limit[11]),\n .O(\\three_inc_min_limit[11]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_inc_min_limit[11]_i_3 \n (.I0(four_inc_max_limit[10]),\n .O(\\three_inc_min_limit[11]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_inc_min_limit[5]_i_2 \n (.I0(four_inc_max_limit[5]),\n .O(\\three_inc_min_limit[5]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_inc_min_limit[5]_i_3 \n (.I0(four_inc_max_limit[4]),\n .O(\\three_inc_min_limit[5]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_inc_min_limit[5]_i_4 \n (.I0(four_inc_max_limit[3]),\n .O(\\three_inc_min_limit[5]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\three_inc_min_limit[5]_i_5 \n (.I0(four_inc_max_limit[2]),\n .O(\\three_inc_min_limit[5]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_inc_min_limit[9]_i_2 \n (.I0(four_inc_max_limit[9]),\n .O(\\three_inc_min_limit[9]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_inc_min_limit[9]_i_3 \n (.I0(four_inc_max_limit[8]),\n .O(\\three_inc_min_limit[9]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_inc_min_limit[9]_i_4 \n (.I0(four_inc_max_limit[7]),\n .O(\\three_inc_min_limit[9]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_inc_min_limit[9]_i_5 \n (.I0(four_inc_max_limit[6]),\n .O(\\three_inc_min_limit[9]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\three_inc_min_limit_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_min_limit_nxt[10]),\n .Q(three_inc_min_limit[10]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE #(\n .INIT(1'b0)) \n \\three_inc_min_limit_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_min_limit_nxt[11]),\n .Q(three_inc_min_limit[11]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n CARRY4 \\three_inc_min_limit_reg[11]_i_1 \n (.CI(\\three_inc_min_limit_reg[9]_i_1_n_0 ),\n .CO({\\NLW_three_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\\three_inc_min_limit_reg[11]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,four_inc_max_limit[10]}),\n .O({\\NLW_three_inc_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],three_inc_min_limit_nxt[11:10]}),\n .S({1'b0,1'b0,\\three_inc_min_limit[11]_i_2_n_0 ,\\three_inc_min_limit[11]_i_3_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\three_inc_min_limit_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(four_inc_max_limit[1]),\n .Q(three_inc_min_limit[1]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE #(\n .INIT(1'b0)) \n \\three_inc_min_limit_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_min_limit_nxt[2]),\n .Q(three_inc_min_limit[2]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE #(\n .INIT(1'b0)) \n \\three_inc_min_limit_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_min_limit_nxt[3]),\n .Q(three_inc_min_limit[3]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE #(\n .INIT(1'b0)) \n \\three_inc_min_limit_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_min_limit_nxt[4]),\n .Q(three_inc_min_limit[4]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE #(\n .INIT(1'b0)) \n \\three_inc_min_limit_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_min_limit_nxt[5]),\n .Q(three_inc_min_limit[5]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n CARRY4 \\three_inc_min_limit_reg[5]_i_1 \n (.CI(1'b0),\n .CO({\\three_inc_min_limit_reg[5]_i_1_n_0 ,\\three_inc_min_limit_reg[5]_i_1_n_1 ,\\three_inc_min_limit_reg[5]_i_1_n_2 ,\\three_inc_min_limit_reg[5]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({four_inc_max_limit[5:3],1'b0}),\n .O(three_inc_min_limit_nxt[5:2]),\n .S({\\three_inc_min_limit[5]_i_2_n_0 ,\\three_inc_min_limit[5]_i_3_n_0 ,\\three_inc_min_limit[5]_i_4_n_0 ,\\three_inc_min_limit[5]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\three_inc_min_limit_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_min_limit_nxt[6]),\n .Q(three_inc_min_limit[6]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE #(\n .INIT(1'b0)) \n \\three_inc_min_limit_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_min_limit_nxt[7]),\n .Q(three_inc_min_limit[7]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE #(\n .INIT(1'b0)) \n \\three_inc_min_limit_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_min_limit_nxt[8]),\n .Q(three_inc_min_limit[8]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE #(\n .INIT(1'b0)) \n \\three_inc_min_limit_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_min_limit_nxt[9]),\n .Q(three_inc_min_limit[9]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n CARRY4 \\three_inc_min_limit_reg[9]_i_1 \n (.CI(\\three_inc_min_limit_reg[5]_i_1_n_0 ),\n .CO({\\three_inc_min_limit_reg[9]_i_1_n_0 ,\\three_inc_min_limit_reg[9]_i_1_n_1 ,\\three_inc_min_limit_reg[9]_i_1_n_2 ,\\three_inc_min_limit_reg[9]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI(four_inc_max_limit[9:6]),\n .O(three_inc_min_limit_nxt[9:6]),\n .S({\\three_inc_min_limit[9]_i_2_n_0 ,\\three_inc_min_limit[9]_i_3_n_0 ,\\three_inc_min_limit[9]_i_4_n_0 ,\\three_inc_min_limit[9]_i_5_n_0 }));\n LUT1 #(\n .INIT(2'h1)) \n \\two_dec_max_limit[0]_i_1 \n (.I0(device_temp_init[0]),\n .O(\\two_dec_max_limit[0]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\two_dec_max_limit[11]_i_2 \n (.I0(device_temp_init[11]),\n .O(\\two_dec_max_limit[11]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\two_dec_max_limit[11]_i_3 \n (.I0(device_temp_init[10]),\n .O(\\two_dec_max_limit[11]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_dec_max_limit[11]_i_4 \n (.I0(device_temp_init[9]),\n .O(\\two_dec_max_limit[11]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_dec_max_limit[4]_i_2 \n (.I0(device_temp_init[4]),\n .O(\\two_dec_max_limit[4]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\two_dec_max_limit[4]_i_3 \n (.I0(device_temp_init[3]),\n .O(\\two_dec_max_limit[4]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\two_dec_max_limit[4]_i_4 \n (.I0(device_temp_init[2]),\n .O(\\two_dec_max_limit[4]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_dec_max_limit[4]_i_5 \n (.I0(device_temp_init[1]),\n .O(\\two_dec_max_limit[4]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\two_dec_max_limit[8]_i_2 \n (.I0(device_temp_init[8]),\n .O(\\two_dec_max_limit[8]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\two_dec_max_limit[8]_i_3 \n (.I0(device_temp_init[7]),\n .O(\\two_dec_max_limit[8]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_dec_max_limit[8]_i_4 \n (.I0(device_temp_init[6]),\n .O(\\two_dec_max_limit[8]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\two_dec_max_limit[8]_i_5 \n (.I0(device_temp_init[5]),\n .O(\\two_dec_max_limit[8]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\two_dec_max_limit_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\two_dec_max_limit[0]_i_1_n_0 ),\n .Q(two_dec_max_limit[0]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE #(\n .INIT(1'b0)) \n \\two_dec_max_limit_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_max_limit_nxt[10]),\n .Q(two_dec_max_limit[10]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE #(\n .INIT(1'b0)) \n \\two_dec_max_limit_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_max_limit_nxt[11]),\n .Q(two_dec_max_limit[11]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n CARRY4 \\two_dec_max_limit_reg[11]_i_1 \n (.CI(\\two_dec_max_limit_reg[8]_i_1_n_0 ),\n .CO({\\NLW_two_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\\two_dec_max_limit_reg[11]_i_1_n_2 ,\\two_dec_max_limit_reg[11]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,device_temp_init[9]}),\n .O({\\NLW_two_dec_max_limit_reg[11]_i_1_O_UNCONNECTED [3],two_dec_max_limit_nxt[11:9]}),\n .S({1'b0,\\two_dec_max_limit[11]_i_2_n_0 ,\\two_dec_max_limit[11]_i_3_n_0 ,\\two_dec_max_limit[11]_i_4_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\two_dec_max_limit_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_max_limit_nxt[1]),\n .Q(two_dec_max_limit[1]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n (* XILINX_LEGACY_PRIM = \"(MUXCY,XORCY)\" *) \n CARRY4 \\two_dec_max_limit_reg[1]_i_1_CARRY4 \n (.CI(1'b0),\n .CO(\\NLW_two_dec_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED [3:0]),\n .CYINIT(device_temp_init[0]),\n .DI(\\NLW_two_dec_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED [3:0]),\n .O({\\NLW_two_dec_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED [3:1],two_dec_max_limit_nxt[1]}),\n .S({\\NLW_two_dec_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED [3:1],\\four_inc_max_limit[1]_i_2_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\two_dec_max_limit_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_max_limit_nxt[2]),\n .Q(two_dec_max_limit[2]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE #(\n .INIT(1'b0)) \n \\two_dec_max_limit_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_max_limit_nxt[3]),\n .Q(two_dec_max_limit[3]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE #(\n .INIT(1'b0)) \n \\two_dec_max_limit_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_max_limit_nxt[4]),\n .Q(two_dec_max_limit[4]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n CARRY4 \\two_dec_max_limit_reg[4]_i_1 \n (.CI(1'b0),\n .CO({\\two_dec_max_limit_reg[4]_i_1_n_0 ,\\two_dec_max_limit_reg[4]_i_1_n_1 ,\\two_dec_max_limit_reg[4]_i_1_n_2 ,\\two_dec_max_limit_reg[4]_i_1_n_3 }),\n .CYINIT(device_temp_init[0]),\n .DI({device_temp_init[4],1'b0,1'b0,device_temp_init[1]}),\n .O({two_dec_max_limit_nxt[4:2],\\NLW_two_dec_max_limit_reg[4]_i_1_O_UNCONNECTED [0]}),\n .S({\\two_dec_max_limit[4]_i_2_n_0 ,\\two_dec_max_limit[4]_i_3_n_0 ,\\two_dec_max_limit[4]_i_4_n_0 ,\\two_dec_max_limit[4]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\two_dec_max_limit_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_max_limit_nxt[5]),\n .Q(two_dec_max_limit[5]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE #(\n .INIT(1'b0)) \n \\two_dec_max_limit_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_max_limit_nxt[6]),\n .Q(two_dec_max_limit[6]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE #(\n .INIT(1'b0)) \n \\two_dec_max_limit_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_max_limit_nxt[7]),\n .Q(two_dec_max_limit[7]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE #(\n .INIT(1'b0)) \n \\two_dec_max_limit_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_max_limit_nxt[8]),\n .Q(two_dec_max_limit[8]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n CARRY4 \\two_dec_max_limit_reg[8]_i_1 \n (.CI(\\two_dec_max_limit_reg[4]_i_1_n_0 ),\n .CO({\\two_dec_max_limit_reg[8]_i_1_n_0 ,\\two_dec_max_limit_reg[8]_i_1_n_1 ,\\two_dec_max_limit_reg[8]_i_1_n_2 ,\\two_dec_max_limit_reg[8]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,device_temp_init[6],1'b0}),\n .O(two_dec_max_limit_nxt[8:5]),\n .S({\\two_dec_max_limit[8]_i_2_n_0 ,\\two_dec_max_limit[8]_i_3_n_0 ,\\two_dec_max_limit[8]_i_4_n_0 ,\\two_dec_max_limit[8]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\two_dec_max_limit_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_max_limit_nxt[9]),\n .Q(two_dec_max_limit[9]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n LUT1 #(\n .INIT(2'h1)) \n \\two_dec_min_limit[11]_i_2 \n (.I0(one_dec_max_limit[11]),\n .O(\\two_dec_min_limit[11]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_dec_min_limit[11]_i_3 \n (.I0(one_dec_max_limit[10]),\n .O(\\two_dec_min_limit[11]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_dec_min_limit[5]_i_2 \n (.I0(one_dec_max_limit[5]),\n .O(\\two_dec_min_limit[5]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_dec_min_limit[5]_i_3 \n (.I0(one_dec_max_limit[4]),\n .O(\\two_dec_min_limit[5]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_dec_min_limit[5]_i_4 \n (.I0(one_dec_max_limit[3]),\n .O(\\two_dec_min_limit[5]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\two_dec_min_limit[5]_i_5 \n (.I0(one_dec_max_limit[2]),\n .O(\\two_dec_min_limit[5]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_dec_min_limit[9]_i_2 \n (.I0(one_dec_max_limit[9]),\n .O(\\two_dec_min_limit[9]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_dec_min_limit[9]_i_3 \n (.I0(one_dec_max_limit[8]),\n .O(\\two_dec_min_limit[9]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_dec_min_limit[9]_i_4 \n (.I0(one_dec_max_limit[7]),\n .O(\\two_dec_min_limit[9]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_dec_min_limit[9]_i_5 \n (.I0(one_dec_max_limit[6]),\n .O(\\two_dec_min_limit[9]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\two_dec_min_limit_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_min_limit_nxt[10]),\n .Q(two_dec_min_limit[10]),\n .R(SS));\n FDRE #(\n .INIT(1'b0)) \n \\two_dec_min_limit_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_min_limit_nxt[11]),\n .Q(two_dec_min_limit[11]),\n .R(SS));\n CARRY4 \\two_dec_min_limit_reg[11]_i_1 \n (.CI(\\two_dec_min_limit_reg[9]_i_1_n_0 ),\n .CO({\\NLW_two_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\\two_dec_min_limit_reg[11]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,one_dec_max_limit[10]}),\n .O({\\NLW_two_dec_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],two_dec_min_limit_nxt[11:10]}),\n .S({1'b0,1'b0,\\two_dec_min_limit[11]_i_2_n_0 ,\\two_dec_min_limit[11]_i_3_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\two_dec_min_limit_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_max_limit[1]),\n .Q(two_dec_min_limit[1]),\n .R(SS));\n FDRE #(\n .INIT(1'b0)) \n \\two_dec_min_limit_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_min_limit_nxt[2]),\n .Q(two_dec_min_limit[2]),\n .R(SS));\n FDRE #(\n .INIT(1'b0)) \n \\two_dec_min_limit_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_min_limit_nxt[3]),\n .Q(two_dec_min_limit[3]),\n .R(SS));\n FDRE #(\n .INIT(1'b0)) \n \\two_dec_min_limit_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_min_limit_nxt[4]),\n .Q(two_dec_min_limit[4]),\n .R(SS));\n FDRE #(\n .INIT(1'b0)) \n \\two_dec_min_limit_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_min_limit_nxt[5]),\n .Q(two_dec_min_limit[5]),\n .R(SS));\n CARRY4 \\two_dec_min_limit_reg[5]_i_1 \n (.CI(1'b0),\n .CO({\\two_dec_min_limit_reg[5]_i_1_n_0 ,\\two_dec_min_limit_reg[5]_i_1_n_1 ,\\two_dec_min_limit_reg[5]_i_1_n_2 ,\\two_dec_min_limit_reg[5]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({one_dec_max_limit[5:3],1'b0}),\n .O(two_dec_min_limit_nxt[5:2]),\n .S({\\two_dec_min_limit[5]_i_2_n_0 ,\\two_dec_min_limit[5]_i_3_n_0 ,\\two_dec_min_limit[5]_i_4_n_0 ,\\two_dec_min_limit[5]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\two_dec_min_limit_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_min_limit_nxt[6]),\n .Q(two_dec_min_limit[6]),\n .R(SS));\n FDRE #(\n .INIT(1'b0)) \n \\two_dec_min_limit_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_min_limit_nxt[7]),\n .Q(two_dec_min_limit[7]),\n .R(SS));\n FDRE #(\n .INIT(1'b0)) \n \\two_dec_min_limit_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_min_limit_nxt[8]),\n .Q(two_dec_min_limit[8]),\n .R(SS));\n FDRE #(\n .INIT(1'b0)) \n \\two_dec_min_limit_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_min_limit_nxt[9]),\n .Q(two_dec_min_limit[9]),\n .R(SS));\n CARRY4 \\two_dec_min_limit_reg[9]_i_1 \n (.CI(\\two_dec_min_limit_reg[5]_i_1_n_0 ),\n .CO({\\two_dec_min_limit_reg[9]_i_1_n_0 ,\\two_dec_min_limit_reg[9]_i_1_n_1 ,\\two_dec_min_limit_reg[9]_i_1_n_2 ,\\two_dec_min_limit_reg[9]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI(one_dec_max_limit[9:6]),\n .O(two_dec_min_limit_nxt[9:6]),\n .S({\\two_dec_min_limit[9]_i_2_n_0 ,\\two_dec_min_limit[9]_i_3_n_0 ,\\two_dec_min_limit[9]_i_4_n_0 ,\\two_dec_min_limit[9]_i_5_n_0 }));\n LUT1 #(\n .INIT(2'h1)) \n \\two_inc_max_limit[11]_i_2 \n (.I0(device_temp_init[11]),\n .O(\\two_inc_max_limit[11]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_inc_max_limit[11]_i_3 \n (.I0(device_temp_init[10]),\n .O(\\two_inc_max_limit[11]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_inc_max_limit[11]_i_4 \n (.I0(device_temp_init[9]),\n .O(\\two_inc_max_limit[11]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_inc_max_limit[4]_i_2 \n (.I0(device_temp_init[4]),\n .O(\\two_inc_max_limit[4]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_inc_max_limit[4]_i_3 \n (.I0(device_temp_init[3]),\n .O(\\two_inc_max_limit[4]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\two_inc_max_limit[4]_i_4 \n (.I0(device_temp_init[2]),\n .O(\\two_inc_max_limit[4]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_inc_max_limit[4]_i_5 \n (.I0(device_temp_init[1]),\n .O(\\two_inc_max_limit[4]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\two_inc_max_limit[8]_i_2 \n (.I0(device_temp_init[8]),\n .O(\\two_inc_max_limit[8]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_inc_max_limit[8]_i_3 \n (.I0(device_temp_init[7]),\n .O(\\two_inc_max_limit[8]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\two_inc_max_limit[8]_i_4 \n (.I0(device_temp_init[6]),\n .O(\\two_inc_max_limit[8]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\two_inc_max_limit[8]_i_5 \n (.I0(device_temp_init[5]),\n .O(\\two_inc_max_limit[8]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\two_inc_max_limit_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_max_limit_nxt[10]),\n .Q(two_inc_max_limit[10]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\two_inc_max_limit_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_max_limit_nxt[11]),\n .Q(two_inc_max_limit[11]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n CARRY4 \\two_inc_max_limit_reg[11]_i_1 \n (.CI(\\two_inc_max_limit_reg[8]_i_1_n_0 ),\n .CO({\\NLW_two_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\\two_inc_max_limit_reg[11]_i_1_n_2 ,\\two_inc_max_limit_reg[11]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,device_temp_init[10:9]}),\n .O({\\NLW_two_inc_max_limit_reg[11]_i_1_O_UNCONNECTED [3],two_inc_max_limit_nxt[11:9]}),\n .S({1'b0,\\two_inc_max_limit[11]_i_2_n_0 ,\\two_inc_max_limit[11]_i_3_n_0 ,\\two_inc_max_limit[11]_i_4_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\two_inc_max_limit_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_max_limit_nxt[1]),\n .Q(two_inc_max_limit[1]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\two_inc_max_limit_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_max_limit_nxt[2]),\n .Q(two_inc_max_limit[2]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\two_inc_max_limit_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_max_limit_nxt[3]),\n .Q(two_inc_max_limit[3]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\two_inc_max_limit_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_max_limit_nxt[4]),\n .Q(two_inc_max_limit[4]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n CARRY4 \\two_inc_max_limit_reg[4]_i_1 \n (.CI(1'b0),\n .CO({\\two_inc_max_limit_reg[4]_i_1_n_0 ,\\two_inc_max_limit_reg[4]_i_1_n_1 ,\\two_inc_max_limit_reg[4]_i_1_n_2 ,\\two_inc_max_limit_reg[4]_i_1_n_3 }),\n .CYINIT(device_temp_init[0]),\n .DI({device_temp_init[4:3],1'b0,device_temp_init[1]}),\n .O({two_inc_max_limit_nxt[4:2],\\NLW_two_inc_max_limit_reg[4]_i_1_O_UNCONNECTED [0]}),\n .S({\\two_inc_max_limit[4]_i_2_n_0 ,\\two_inc_max_limit[4]_i_3_n_0 ,\\two_inc_max_limit[4]_i_4_n_0 ,\\two_inc_max_limit[4]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\two_inc_max_limit_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_max_limit_nxt[5]),\n .Q(two_inc_max_limit[5]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\two_inc_max_limit_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_max_limit_nxt[6]),\n .Q(two_inc_max_limit[6]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\two_inc_max_limit_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_max_limit_nxt[7]),\n .Q(two_inc_max_limit[7]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\two_inc_max_limit_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_max_limit_nxt[8]),\n .Q(two_inc_max_limit[8]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n CARRY4 \\two_inc_max_limit_reg[8]_i_1 \n (.CI(\\two_inc_max_limit_reg[4]_i_1_n_0 ),\n .CO({\\two_inc_max_limit_reg[8]_i_1_n_0 ,\\two_inc_max_limit_reg[8]_i_1_n_1 ,\\two_inc_max_limit_reg[8]_i_1_n_2 ,\\two_inc_max_limit_reg[8]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,device_temp_init[7],1'b0,1'b0}),\n .O(two_inc_max_limit_nxt[8:5]),\n .S({\\two_inc_max_limit[8]_i_2_n_0 ,\\two_inc_max_limit[8]_i_3_n_0 ,\\two_inc_max_limit[8]_i_4_n_0 ,\\two_inc_max_limit[8]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\two_inc_max_limit_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_max_limit_nxt[9]),\n .Q(two_inc_max_limit[9]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n LUT1 #(\n .INIT(2'h1)) \n \\two_inc_min_limit[11]_i_2 \n (.I0(three_inc_max_limit[11]),\n .O(\\two_inc_min_limit[11]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_inc_min_limit[11]_i_3 \n (.I0(three_inc_max_limit[10]),\n .O(\\two_inc_min_limit[11]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_inc_min_limit[5]_i_2 \n (.I0(three_inc_max_limit[5]),\n .O(\\two_inc_min_limit[5]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_inc_min_limit[5]_i_3 \n (.I0(three_inc_max_limit[4]),\n .O(\\two_inc_min_limit[5]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_inc_min_limit[5]_i_4 \n (.I0(three_inc_max_limit[3]),\n .O(\\two_inc_min_limit[5]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\two_inc_min_limit[5]_i_5 \n (.I0(three_inc_max_limit[2]),\n .O(\\two_inc_min_limit[5]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_inc_min_limit[9]_i_2 \n (.I0(three_inc_max_limit[9]),\n .O(\\two_inc_min_limit[9]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_inc_min_limit[9]_i_3 \n (.I0(three_inc_max_limit[8]),\n .O(\\two_inc_min_limit[9]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_inc_min_limit[9]_i_4 \n (.I0(three_inc_max_limit[7]),\n .O(\\two_inc_min_limit[9]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_inc_min_limit[9]_i_5 \n (.I0(three_inc_max_limit[6]),\n .O(\\two_inc_min_limit[9]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\two_inc_min_limit_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_min_limit_nxt[10]),\n .Q(two_inc_min_limit[10]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\two_inc_min_limit_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_min_limit_nxt[11]),\n .Q(two_inc_min_limit[11]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n CARRY4 \\two_inc_min_limit_reg[11]_i_1 \n (.CI(\\two_inc_min_limit_reg[9]_i_1_n_0 ),\n .CO({\\NLW_two_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\\two_inc_min_limit_reg[11]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,three_inc_max_limit[10]}),\n .O({\\NLW_two_inc_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],two_inc_min_limit_nxt[11:10]}),\n .S({1'b0,1'b0,\\two_inc_min_limit[11]_i_2_n_0 ,\\two_inc_min_limit[11]_i_3_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\two_inc_min_limit_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_max_limit[1]),\n .Q(two_inc_min_limit[1]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\two_inc_min_limit_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_min_limit_nxt[2]),\n .Q(two_inc_min_limit[2]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\two_inc_min_limit_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_min_limit_nxt[3]),\n .Q(two_inc_min_limit[3]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\two_inc_min_limit_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_min_limit_nxt[4]),\n .Q(two_inc_min_limit[4]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\two_inc_min_limit_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_min_limit_nxt[5]),\n .Q(two_inc_min_limit[5]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n CARRY4 \\two_inc_min_limit_reg[5]_i_1 \n (.CI(1'b0),\n .CO({\\two_inc_min_limit_reg[5]_i_1_n_0 ,\\two_inc_min_limit_reg[5]_i_1_n_1 ,\\two_inc_min_limit_reg[5]_i_1_n_2 ,\\two_inc_min_limit_reg[5]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({three_inc_max_limit[5:3],1'b0}),\n .O(two_inc_min_limit_nxt[5:2]),\n .S({\\two_inc_min_limit[5]_i_2_n_0 ,\\two_inc_min_limit[5]_i_3_n_0 ,\\two_inc_min_limit[5]_i_4_n_0 ,\\two_inc_min_limit[5]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\two_inc_min_limit_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_min_limit_nxt[6]),\n .Q(two_inc_min_limit[6]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\two_inc_min_limit_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_min_limit_nxt[7]),\n .Q(two_inc_min_limit[7]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\two_inc_min_limit_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_min_limit_nxt[8]),\n .Q(two_inc_min_limit[8]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\two_inc_min_limit_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_min_limit_nxt[9]),\n .Q(two_inc_min_limit[9]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n CARRY4 \\two_inc_min_limit_reg[9]_i_1 \n (.CI(\\two_inc_min_limit_reg[5]_i_1_n_0 ),\n .CO({\\two_inc_min_limit_reg[9]_i_1_n_0 ,\\two_inc_min_limit_reg[9]_i_1_n_1 ,\\two_inc_min_limit_reg[9]_i_1_n_2 ,\\two_inc_min_limit_reg[9]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI(three_inc_max_limit[9:6]),\n .O(two_inc_min_limit_nxt[9:6]),\n .S({\\two_inc_min_limit[9]_i_2_n_0 ,\\two_inc_min_limit[9]_i_3_n_0 ,\\two_inc_min_limit[9]_i_4_n_0 ,\\two_inc_min_limit[9]_i_5_n_0 }));\n LUT3 #(\n .INIT(8'h40)) \n update_temp_101\n (.I0(tempmon_sample_en_102),\n .I1(tempmon_init_complete),\n .I2(tempmon_sample_en_101),\n .O(update_temp_101__0));\n FDRE #(\n .INIT(1'b0)) \n update_temp_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(update_temp_101__0),\n .Q(update_temp_102),\n .R(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_phy_top\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_phy_top\n (ddr3_reset_n,\n ddr3_cas_n,\n ddr3_ras_n,\n ddr3_we_n,\n ddr3_addr,\n ddr3_ba,\n ddr3_cs_n,\n ddr3_odt,\n ddr3_cke,\n ddr3_dm,\n \\rd_ptr_timing_reg[2] ,\n \\rd_ptr_timing_reg[2]_0 ,\n \\rd_ptr_timing_reg[2]_1 ,\n \\rd_ptr_timing_reg[2]_2 ,\n \\rd_ptr_timing_reg[2]_3 ,\n \\rd_ptr_timing_reg[2]_4 ,\n \\rd_ptr_timing_reg[2]_5 ,\n \\rd_ptr_timing_reg[2]_6 ,\n \\rd_ptr_timing_reg[2]_7 ,\n \\rd_ptr_timing_reg[2]_8 ,\n \\rd_ptr_timing_reg[2]_9 ,\n \\rd_ptr_timing_reg[2]_10 ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,\n phy_dout,\n \\samps_r_reg[9] ,\n app_zq_r_reg,\n \\periodic_rd_generation.periodic_rd_timer_r_reg[1] ,\n init_calib_complete_r_reg,\n \\calib_seq_reg[0] ,\n \\pi_rst_stg1_cal_r_reg[0] ,\n samp_edge_cnt0_en_r,\n pi_en_stg2_f_timing_reg,\n dqs_po_en_stg2_f_reg,\n \\rd_ptr_timing_reg[0] ,\n \\resume_wait_r_reg[5] ,\n phy_mc_ctl_full,\n stg3_dec2init_val_r_reg,\n stg3_inc2init_val_r_reg,\n rd_buf_we,\n \\not_strict_mode.status_ram.rd_buf_we_r1_reg ,\n rst_sync_r1_reg,\n \\stg2_tap_cnt_reg[0] ,\n \\sm_r_reg[0] ,\n D,\n \\not_strict_mode.app_rd_data_reg[255] ,\n \\not_strict_mode.app_rd_data_reg[239] ,\n \\not_strict_mode.app_rd_data_reg[247] ,\n \\not_strict_mode.app_rd_data_reg[231] ,\n \\not_strict_mode.app_rd_data_reg[254] ,\n \\not_strict_mode.app_rd_data_reg[238] ,\n \\not_strict_mode.app_rd_data_reg[246] ,\n \\not_strict_mode.app_rd_data_reg[230] ,\n \\not_strict_mode.app_rd_data_reg[253] ,\n \\not_strict_mode.app_rd_data_reg[237] ,\n \\not_strict_mode.app_rd_data_reg[245] ,\n \\not_strict_mode.app_rd_data_reg[229] ,\n \\not_strict_mode.app_rd_data_reg[252] ,\n \\not_strict_mode.app_rd_data_reg[236] ,\n \\not_strict_mode.app_rd_data_reg[244] ,\n \\not_strict_mode.app_rd_data_reg[228] ,\n \\not_strict_mode.app_rd_data_reg[251] ,\n \\not_strict_mode.app_rd_data_reg[235] ,\n \\not_strict_mode.app_rd_data_reg[243] ,\n \\not_strict_mode.app_rd_data_reg[227] ,\n \\not_strict_mode.app_rd_data_reg[250] ,\n \\not_strict_mode.app_rd_data_reg[234] ,\n \\not_strict_mode.app_rd_data_reg[242] ,\n \\not_strict_mode.app_rd_data_reg[226] ,\n \\not_strict_mode.app_rd_data_reg[249] ,\n \\not_strict_mode.app_rd_data_reg[233] ,\n \\not_strict_mode.app_rd_data_reg[241] ,\n \\not_strict_mode.app_rd_data_reg[225] ,\n \\not_strict_mode.app_rd_data_reg[248] ,\n \\not_strict_mode.app_rd_data_reg[232] ,\n \\not_strict_mode.app_rd_data_reg[240] ,\n \\not_strict_mode.app_rd_data_reg[224] ,\n \\not_strict_mode.app_rd_data_reg[223] ,\n \\not_strict_mode.app_rd_data_reg[207] ,\n \\not_strict_mode.app_rd_data_reg[215] ,\n \\not_strict_mode.app_rd_data_reg[199] ,\n \\not_strict_mode.app_rd_data_reg[222] ,\n \\not_strict_mode.app_rd_data_reg[206] ,\n \\not_strict_mode.app_rd_data_reg[214] ,\n \\not_strict_mode.app_rd_data_reg[198] ,\n \\not_strict_mode.app_rd_data_reg[221] ,\n \\not_strict_mode.app_rd_data_reg[205] ,\n \\not_strict_mode.app_rd_data_reg[213] ,\n \\not_strict_mode.app_rd_data_reg[197] ,\n \\not_strict_mode.app_rd_data_reg[220] ,\n \\not_strict_mode.app_rd_data_reg[204] ,\n \\not_strict_mode.app_rd_data_reg[212] ,\n \\not_strict_mode.app_rd_data_reg[196] ,\n \\not_strict_mode.app_rd_data_reg[219] ,\n \\not_strict_mode.app_rd_data_reg[203] ,\n \\not_strict_mode.app_rd_data_reg[211] ,\n \\not_strict_mode.app_rd_data_reg[195] ,\n \\not_strict_mode.app_rd_data_reg[218] ,\n \\not_strict_mode.app_rd_data_reg[202] ,\n \\not_strict_mode.app_rd_data_reg[210] ,\n \\not_strict_mode.app_rd_data_reg[194] ,\n \\not_strict_mode.app_rd_data_reg[217] ,\n \\not_strict_mode.app_rd_data_reg[201] ,\n \\not_strict_mode.app_rd_data_reg[209] ,\n \\not_strict_mode.app_rd_data_reg[193] ,\n \\not_strict_mode.app_rd_data_reg[216] ,\n \\not_strict_mode.app_rd_data_reg[200] ,\n \\not_strict_mode.app_rd_data_reg[208] ,\n \\not_strict_mode.app_rd_data_reg[192] ,\n \\not_strict_mode.app_rd_data_reg[191] ,\n \\not_strict_mode.app_rd_data_reg[175] ,\n \\not_strict_mode.app_rd_data_reg[183] ,\n \\not_strict_mode.app_rd_data_reg[167] ,\n \\not_strict_mode.app_rd_data_reg[190] ,\n \\not_strict_mode.app_rd_data_reg[174] ,\n \\not_strict_mode.app_rd_data_reg[182] ,\n \\not_strict_mode.app_rd_data_reg[166] ,\n \\not_strict_mode.app_rd_data_reg[189] ,\n \\not_strict_mode.app_rd_data_reg[173] ,\n \\not_strict_mode.app_rd_data_reg[181] ,\n \\not_strict_mode.app_rd_data_reg[165] ,\n \\not_strict_mode.app_rd_data_reg[188] ,\n \\not_strict_mode.app_rd_data_reg[172] ,\n \\not_strict_mode.app_rd_data_reg[180] ,\n \\not_strict_mode.app_rd_data_reg[164] ,\n \\not_strict_mode.app_rd_data_reg[187] ,\n \\not_strict_mode.app_rd_data_reg[171] ,\n \\not_strict_mode.app_rd_data_reg[179] ,\n \\not_strict_mode.app_rd_data_reg[163] ,\n \\not_strict_mode.app_rd_data_reg[186] ,\n \\not_strict_mode.app_rd_data_reg[170] ,\n \\not_strict_mode.app_rd_data_reg[178] ,\n \\not_strict_mode.app_rd_data_reg[162] ,\n \\not_strict_mode.app_rd_data_reg[185] ,\n \\not_strict_mode.app_rd_data_reg[169] ,\n \\not_strict_mode.app_rd_data_reg[177] ,\n \\not_strict_mode.app_rd_data_reg[161] ,\n \\not_strict_mode.app_rd_data_reg[184] ,\n \\not_strict_mode.app_rd_data_reg[168] ,\n \\not_strict_mode.app_rd_data_reg[176] ,\n \\not_strict_mode.app_rd_data_reg[160] ,\n \\not_strict_mode.app_rd_data_reg[159] ,\n \\not_strict_mode.app_rd_data_reg[143] ,\n \\not_strict_mode.app_rd_data_reg[151] ,\n \\not_strict_mode.app_rd_data_reg[135] ,\n \\not_strict_mode.app_rd_data_reg[158] ,\n \\not_strict_mode.app_rd_data_reg[142] ,\n \\not_strict_mode.app_rd_data_reg[150] ,\n \\not_strict_mode.app_rd_data_reg[134] ,\n \\not_strict_mode.app_rd_data_reg[157] ,\n \\not_strict_mode.app_rd_data_reg[141] ,\n \\not_strict_mode.app_rd_data_reg[149] ,\n \\not_strict_mode.app_rd_data_reg[133] ,\n \\not_strict_mode.app_rd_data_reg[156] ,\n \\not_strict_mode.app_rd_data_reg[140] ,\n \\not_strict_mode.app_rd_data_reg[148] ,\n \\not_strict_mode.app_rd_data_reg[132] ,\n \\not_strict_mode.app_rd_data_reg[155] ,\n \\not_strict_mode.app_rd_data_reg[139] ,\n \\not_strict_mode.app_rd_data_reg[147] ,\n \\not_strict_mode.app_rd_data_reg[131] ,\n \\not_strict_mode.app_rd_data_reg[154] ,\n \\not_strict_mode.app_rd_data_reg[138] ,\n \\not_strict_mode.app_rd_data_reg[146] ,\n \\not_strict_mode.app_rd_data_reg[130] ,\n \\not_strict_mode.app_rd_data_reg[153] ,\n \\not_strict_mode.app_rd_data_reg[137] ,\n \\not_strict_mode.app_rd_data_reg[145] ,\n \\not_strict_mode.app_rd_data_reg[129] ,\n \\not_strict_mode.app_rd_data_reg[152] ,\n \\not_strict_mode.app_rd_data_reg[136] ,\n \\not_strict_mode.app_rd_data_reg[144] ,\n \\not_strict_mode.app_rd_data_reg[128] ,\n \\not_strict_mode.app_rd_data_reg[127] ,\n \\not_strict_mode.app_rd_data_reg[111] ,\n \\not_strict_mode.app_rd_data_reg[119] ,\n \\not_strict_mode.app_rd_data_reg[103] ,\n \\not_strict_mode.app_rd_data_reg[126] ,\n \\not_strict_mode.app_rd_data_reg[110] ,\n \\not_strict_mode.app_rd_data_reg[118] ,\n \\not_strict_mode.app_rd_data_reg[102] ,\n \\not_strict_mode.app_rd_data_reg[125] ,\n \\not_strict_mode.app_rd_data_reg[109] ,\n \\not_strict_mode.app_rd_data_reg[117] ,\n \\not_strict_mode.app_rd_data_reg[101] ,\n \\not_strict_mode.app_rd_data_reg[124] ,\n \\not_strict_mode.app_rd_data_reg[108] ,\n \\not_strict_mode.app_rd_data_reg[116] ,\n \\not_strict_mode.app_rd_data_reg[100] ,\n \\not_strict_mode.app_rd_data_reg[123] ,\n \\not_strict_mode.app_rd_data_reg[107] ,\n \\not_strict_mode.app_rd_data_reg[115] ,\n \\not_strict_mode.app_rd_data_reg[99] ,\n \\not_strict_mode.app_rd_data_reg[122] ,\n \\not_strict_mode.app_rd_data_reg[106] ,\n \\not_strict_mode.app_rd_data_reg[114] ,\n \\not_strict_mode.app_rd_data_reg[98] ,\n \\not_strict_mode.app_rd_data_reg[121] ,\n \\not_strict_mode.app_rd_data_reg[105] ,\n \\not_strict_mode.app_rd_data_reg[113] ,\n \\not_strict_mode.app_rd_data_reg[97] ,\n \\not_strict_mode.app_rd_data_reg[120] ,\n \\not_strict_mode.app_rd_data_reg[104] ,\n \\not_strict_mode.app_rd_data_reg[112] ,\n \\not_strict_mode.app_rd_data_reg[96] ,\n \\not_strict_mode.app_rd_data_reg[95] ,\n \\not_strict_mode.app_rd_data_reg[79] ,\n \\not_strict_mode.app_rd_data_reg[87] ,\n \\not_strict_mode.app_rd_data_reg[71] ,\n \\not_strict_mode.app_rd_data_reg[94] ,\n \\not_strict_mode.app_rd_data_reg[78] ,\n \\not_strict_mode.app_rd_data_reg[86] ,\n \\not_strict_mode.app_rd_data_reg[70] ,\n \\not_strict_mode.app_rd_data_reg[93] ,\n \\not_strict_mode.app_rd_data_reg[77] ,\n \\not_strict_mode.app_rd_data_reg[85] ,\n \\not_strict_mode.app_rd_data_reg[69] ,\n \\not_strict_mode.app_rd_data_reg[92] ,\n \\not_strict_mode.app_rd_data_reg[76] ,\n \\not_strict_mode.app_rd_data_reg[84] ,\n \\not_strict_mode.app_rd_data_reg[68] ,\n \\not_strict_mode.app_rd_data_reg[91] ,\n \\not_strict_mode.app_rd_data_reg[75] ,\n \\not_strict_mode.app_rd_data_reg[83] ,\n \\not_strict_mode.app_rd_data_reg[67] ,\n \\not_strict_mode.app_rd_data_reg[90] ,\n \\not_strict_mode.app_rd_data_reg[74] ,\n \\not_strict_mode.app_rd_data_reg[82] ,\n \\not_strict_mode.app_rd_data_reg[66] ,\n \\not_strict_mode.app_rd_data_reg[89] ,\n \\not_strict_mode.app_rd_data_reg[73] ,\n \\not_strict_mode.app_rd_data_reg[81] ,\n \\not_strict_mode.app_rd_data_reg[65] ,\n \\not_strict_mode.app_rd_data_reg[88] ,\n \\not_strict_mode.app_rd_data_reg[72] ,\n \\not_strict_mode.app_rd_data_reg[80] ,\n \\not_strict_mode.app_rd_data_reg[64] ,\n \\not_strict_mode.app_rd_data_reg[63] ,\n \\not_strict_mode.app_rd_data_reg[47] ,\n \\not_strict_mode.app_rd_data_reg[55] ,\n \\not_strict_mode.app_rd_data_reg[39] ,\n \\not_strict_mode.app_rd_data_reg[62] ,\n \\not_strict_mode.app_rd_data_reg[46] ,\n \\not_strict_mode.app_rd_data_reg[54] ,\n \\not_strict_mode.app_rd_data_reg[38] ,\n \\not_strict_mode.app_rd_data_reg[61] ,\n \\not_strict_mode.app_rd_data_reg[45] ,\n \\not_strict_mode.app_rd_data_reg[53] ,\n \\not_strict_mode.app_rd_data_reg[37] ,\n \\not_strict_mode.app_rd_data_reg[60] ,\n \\not_strict_mode.app_rd_data_reg[44] ,\n \\not_strict_mode.app_rd_data_reg[52] ,\n \\not_strict_mode.app_rd_data_reg[36] ,\n \\not_strict_mode.app_rd_data_reg[59] ,\n \\not_strict_mode.app_rd_data_reg[43] ,\n \\not_strict_mode.app_rd_data_reg[51] ,\n \\not_strict_mode.app_rd_data_reg[35] ,\n \\not_strict_mode.app_rd_data_reg[58] ,\n \\not_strict_mode.app_rd_data_reg[42] ,\n \\not_strict_mode.app_rd_data_reg[50] ,\n \\not_strict_mode.app_rd_data_reg[34] ,\n \\not_strict_mode.app_rd_data_reg[57] ,\n \\not_strict_mode.app_rd_data_reg[41] ,\n \\not_strict_mode.app_rd_data_reg[49] ,\n \\not_strict_mode.app_rd_data_reg[33] ,\n \\not_strict_mode.app_rd_data_reg[56] ,\n \\not_strict_mode.app_rd_data_reg[40] ,\n \\not_strict_mode.app_rd_data_reg[48] ,\n \\not_strict_mode.app_rd_data_reg[32] ,\n \\not_strict_mode.app_rd_data_reg[31] ,\n \\not_strict_mode.app_rd_data_reg[15] ,\n \\not_strict_mode.app_rd_data_reg[23] ,\n \\not_strict_mode.app_rd_data_reg[7] ,\n \\not_strict_mode.app_rd_data_reg[30] ,\n \\not_strict_mode.app_rd_data_reg[14] ,\n \\not_strict_mode.app_rd_data_reg[22] ,\n \\not_strict_mode.app_rd_data_reg[6] ,\n \\not_strict_mode.app_rd_data_reg[29] ,\n \\not_strict_mode.app_rd_data_reg[13] ,\n \\not_strict_mode.app_rd_data_reg[21] ,\n \\not_strict_mode.app_rd_data_reg[5] ,\n \\not_strict_mode.app_rd_data_reg[28] ,\n \\not_strict_mode.app_rd_data_reg[12] ,\n \\not_strict_mode.app_rd_data_reg[20] ,\n \\not_strict_mode.app_rd_data_reg[4] ,\n \\not_strict_mode.app_rd_data_reg[27] ,\n \\not_strict_mode.app_rd_data_reg[11] ,\n \\not_strict_mode.app_rd_data_reg[19] ,\n \\not_strict_mode.app_rd_data_reg[3] ,\n \\not_strict_mode.app_rd_data_reg[26] ,\n \\not_strict_mode.app_rd_data_reg[10] ,\n \\not_strict_mode.app_rd_data_reg[18] ,\n \\not_strict_mode.app_rd_data_reg[2] ,\n \\not_strict_mode.app_rd_data_reg[25] ,\n \\not_strict_mode.app_rd_data_reg[9] ,\n \\not_strict_mode.app_rd_data_reg[17] ,\n \\not_strict_mode.app_rd_data_reg[1] ,\n \\not_strict_mode.app_rd_data_reg[24] ,\n \\not_strict_mode.app_rd_data_reg[8] ,\n \\not_strict_mode.app_rd_data_reg[16] ,\n \\not_strict_mode.app_rd_data_reg[0] ,\n maint_prescaler_r1,\n \\cmd_pipe_plus.mc_data_offset_reg[4] ,\n \\cmd_pipe_plus.mc_data_offset_reg[5] ,\n \\cmd_pipe_plus.mc_data_offset_reg[1] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[4] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[5] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[1] ,\n \\read_fifo.tail_r_reg[0] ,\n \\cmd_pipe_plus.mc_data_offset_reg[0] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[0] ,\n \\en_cnt_div4.enable_wrlvl_cnt_reg[3] ,\n \\complex_row_cnt_ocal_reg[0] ,\n \\row_cnt_victim_rotate.complex_row_cnt_reg[4] ,\n \\not_strict_mode.app_rd_data_reg[255]_0 ,\n ofs_rdy_r_reg,\n ofs_rdy_r_reg_0,\n \\wr_ptr_timing_reg[2] ,\n \\wr_ptr_timing_reg[2]_0 ,\n \\wr_ptr_timing_reg[2]_1 ,\n \\rd_ptr_timing_reg[0]_0 ,\n wr_en,\n wr_en_5,\n wr_en_6,\n of_ctl_full_v,\n ddr_ck_out,\n \\qcntr_r_reg[0] ,\n ddr3_dq,\n ddr3_dqs_p,\n ddr3_dqs_n,\n idle,\n mmcm_ps_clk,\n rst_sync_r1,\n CLK,\n rstdiv0_sync_r1_reg_rep__20,\n poc_sample_pd,\n freq_refclk,\n mem_refclk,\n sync_pulse,\n pll_locked,\n in0,\n CLKB0,\n CLKB0_7,\n CLKB0_8,\n CLKB0_9,\n RST0,\n rstdiv0_sync_r1_reg_rep__9,\n rstdiv0_sync_r1_reg_rep__10,\n rstdiv0_sync_r1_reg_rep__12,\n SR,\n rstdiv0_sync_r1_reg_rep__23,\n rstdiv0_sync_r1_reg_rep__13,\n rstdiv0_sync_r1_reg_rep__14,\n rstdiv0_sync_r1_reg_rep__22,\n rstdiv0_sync_r1_reg_rep__11,\n cnt_pwron_reset_done_r0,\n rstdiv0_sync_r1_reg_rep__17,\n rstdiv0_sync_r1_reg_rep__16,\n SS,\n tempmon_sample_en,\n rstdiv0_sync_r1_reg_rep__2,\n rstdiv0_sync_r1_reg_rep__6,\n \\cmd_pipe_plus.mc_address_reg[43] ,\n Q,\n mem_out,\n \\rd_ptr_reg[3] ,\n rstdiv0_sync_r1_reg_rep__25,\n rstdiv0_sync_r1_reg_rep__25_0,\n rstdiv0_sync_r1_reg_rep__24,\n \\sm_r_reg[0]_0 ,\n \\rd_ptr_reg[3]_0 ,\n \\read_fifo.fifo_out_data_r_reg[6] ,\n ram_init_done_r,\n mc_cas_n,\n mc_ras_n,\n mc_odt,\n mc_cke,\n mc_we_n,\n mc_address,\n mc_bank,\n mc_cs_n,\n sys_rst,\n \\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ,\n mmcm_locked,\n rstdiv0_sync_r1_reg_rep__25_1,\n rstdiv0_sync_r1_reg_rep__25_2,\n \\mmcm_init_trail_reg[0] ,\n \\mmcm_current_reg[0] ,\n tail_r,\n \\read_fifo.fifo_out_data_r_reg[6]_0 ,\n DOC,\n DOB,\n DOA,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ,\n psdone,\n rstdiv0_sync_r1_reg_rep__0,\n rstdiv0_sync_r1_reg_rep__19,\n fine_adjust_reg,\n samp_edge_cnt0_en_r_reg,\n pi_cnt_dec_reg,\n rstdiv0_sync_r1_reg_rep__23_0,\n p_81_in,\n rstdiv0_sync_r1_reg_rep__23_1,\n po_cnt_dec_reg,\n rstdiv0_sync_r1_reg_rep__4,\n rstdiv0_sync_r1_reg_rep__5,\n \\device_temp_r_reg[11] ,\n rstdiv0_sync_r1_reg_rep__7,\n mc_wrdata_en,\n \\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[2] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[3] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ,\n mc_cmd,\n \\cmd_pipe_plus.mc_data_offset_reg[0]_0 ,\n \\cmd_pipe_plus.mc_data_offset_reg[1]_0 ,\n \\cmd_pipe_plus.mc_data_offset_reg[2] ,\n \\cmd_pipe_plus.mc_data_offset_reg[3] ,\n \\cmd_pipe_plus.mc_data_offset_reg[4]_0 ,\n \\cmd_pipe_plus.mc_data_offset_reg[5]_0 ,\n \\stg3_r_reg[0] ,\n rstdiv0_sync_r1_reg_rep__8);\n output ddr3_reset_n;\n output ddr3_cas_n;\n output ddr3_ras_n;\n output ddr3_we_n;\n output [14:0]ddr3_addr;\n output [2:0]ddr3_ba;\n output [0:0]ddr3_cs_n;\n output [0:0]ddr3_odt;\n output [0:0]ddr3_cke;\n output [3:0]ddr3_dm;\n output \\rd_ptr_timing_reg[2] ;\n output \\rd_ptr_timing_reg[2]_0 ;\n output \\rd_ptr_timing_reg[2]_1 ;\n output \\rd_ptr_timing_reg[2]_2 ;\n output \\rd_ptr_timing_reg[2]_3 ;\n output \\rd_ptr_timing_reg[2]_4 ;\n output \\rd_ptr_timing_reg[2]_5 ;\n output \\rd_ptr_timing_reg[2]_6 ;\n output \\rd_ptr_timing_reg[2]_7 ;\n output \\rd_ptr_timing_reg[2]_8 ;\n output \\rd_ptr_timing_reg[2]_9 ;\n output \\rd_ptr_timing_reg[2]_10 ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;\n output [3:0]phy_dout;\n output \\samps_r_reg[9] ;\n output app_zq_r_reg;\n output \\periodic_rd_generation.periodic_rd_timer_r_reg[1] ;\n output init_calib_complete_r_reg;\n output \\calib_seq_reg[0] ;\n output \\pi_rst_stg1_cal_r_reg[0] ;\n output samp_edge_cnt0_en_r;\n output pi_en_stg2_f_timing_reg;\n output dqs_po_en_stg2_f_reg;\n output [33:0]\\rd_ptr_timing_reg[0] ;\n output \\resume_wait_r_reg[5] ;\n output phy_mc_ctl_full;\n output stg3_dec2init_val_r_reg;\n output stg3_inc2init_val_r_reg;\n output rd_buf_we;\n output \\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n output rst_sync_r1_reg;\n output \\stg2_tap_cnt_reg[0] ;\n output \\sm_r_reg[0] ;\n output [0:0]D;\n output \\not_strict_mode.app_rd_data_reg[255] ;\n output \\not_strict_mode.app_rd_data_reg[239] ;\n output \\not_strict_mode.app_rd_data_reg[247] ;\n output \\not_strict_mode.app_rd_data_reg[231] ;\n output \\not_strict_mode.app_rd_data_reg[254] ;\n output \\not_strict_mode.app_rd_data_reg[238] ;\n output \\not_strict_mode.app_rd_data_reg[246] ;\n output \\not_strict_mode.app_rd_data_reg[230] ;\n output \\not_strict_mode.app_rd_data_reg[253] ;\n output \\not_strict_mode.app_rd_data_reg[237] ;\n output \\not_strict_mode.app_rd_data_reg[245] ;\n output \\not_strict_mode.app_rd_data_reg[229] ;\n output \\not_strict_mode.app_rd_data_reg[252] ;\n output \\not_strict_mode.app_rd_data_reg[236] ;\n output \\not_strict_mode.app_rd_data_reg[244] ;\n output \\not_strict_mode.app_rd_data_reg[228] ;\n output \\not_strict_mode.app_rd_data_reg[251] ;\n output \\not_strict_mode.app_rd_data_reg[235] ;\n output \\not_strict_mode.app_rd_data_reg[243] ;\n output \\not_strict_mode.app_rd_data_reg[227] ;\n output \\not_strict_mode.app_rd_data_reg[250] ;\n output \\not_strict_mode.app_rd_data_reg[234] ;\n output \\not_strict_mode.app_rd_data_reg[242] ;\n output \\not_strict_mode.app_rd_data_reg[226] ;\n output \\not_strict_mode.app_rd_data_reg[249] ;\n output \\not_strict_mode.app_rd_data_reg[233] ;\n output \\not_strict_mode.app_rd_data_reg[241] ;\n output \\not_strict_mode.app_rd_data_reg[225] ;\n output \\not_strict_mode.app_rd_data_reg[248] ;\n output \\not_strict_mode.app_rd_data_reg[232] ;\n output \\not_strict_mode.app_rd_data_reg[240] ;\n output \\not_strict_mode.app_rd_data_reg[224] ;\n output \\not_strict_mode.app_rd_data_reg[223] ;\n output \\not_strict_mode.app_rd_data_reg[207] ;\n output \\not_strict_mode.app_rd_data_reg[215] ;\n output \\not_strict_mode.app_rd_data_reg[199] ;\n output \\not_strict_mode.app_rd_data_reg[222] ;\n output \\not_strict_mode.app_rd_data_reg[206] ;\n output \\not_strict_mode.app_rd_data_reg[214] ;\n output \\not_strict_mode.app_rd_data_reg[198] ;\n output \\not_strict_mode.app_rd_data_reg[221] ;\n output \\not_strict_mode.app_rd_data_reg[205] ;\n output \\not_strict_mode.app_rd_data_reg[213] ;\n output \\not_strict_mode.app_rd_data_reg[197] ;\n output \\not_strict_mode.app_rd_data_reg[220] ;\n output \\not_strict_mode.app_rd_data_reg[204] ;\n output \\not_strict_mode.app_rd_data_reg[212] ;\n output \\not_strict_mode.app_rd_data_reg[196] ;\n output \\not_strict_mode.app_rd_data_reg[219] ;\n output \\not_strict_mode.app_rd_data_reg[203] ;\n output \\not_strict_mode.app_rd_data_reg[211] ;\n output \\not_strict_mode.app_rd_data_reg[195] ;\n output \\not_strict_mode.app_rd_data_reg[218] ;\n output \\not_strict_mode.app_rd_data_reg[202] ;\n output \\not_strict_mode.app_rd_data_reg[210] ;\n output \\not_strict_mode.app_rd_data_reg[194] ;\n output \\not_strict_mode.app_rd_data_reg[217] ;\n output \\not_strict_mode.app_rd_data_reg[201] ;\n output \\not_strict_mode.app_rd_data_reg[209] ;\n output \\not_strict_mode.app_rd_data_reg[193] ;\n output \\not_strict_mode.app_rd_data_reg[216] ;\n output \\not_strict_mode.app_rd_data_reg[200] ;\n output \\not_strict_mode.app_rd_data_reg[208] ;\n output \\not_strict_mode.app_rd_data_reg[192] ;\n output \\not_strict_mode.app_rd_data_reg[191] ;\n output \\not_strict_mode.app_rd_data_reg[175] ;\n output \\not_strict_mode.app_rd_data_reg[183] ;\n output \\not_strict_mode.app_rd_data_reg[167] ;\n output \\not_strict_mode.app_rd_data_reg[190] ;\n output \\not_strict_mode.app_rd_data_reg[174] ;\n output \\not_strict_mode.app_rd_data_reg[182] ;\n output \\not_strict_mode.app_rd_data_reg[166] ;\n output \\not_strict_mode.app_rd_data_reg[189] ;\n output \\not_strict_mode.app_rd_data_reg[173] ;\n output \\not_strict_mode.app_rd_data_reg[181] ;\n output \\not_strict_mode.app_rd_data_reg[165] ;\n output \\not_strict_mode.app_rd_data_reg[188] ;\n output \\not_strict_mode.app_rd_data_reg[172] ;\n output \\not_strict_mode.app_rd_data_reg[180] ;\n output \\not_strict_mode.app_rd_data_reg[164] ;\n output \\not_strict_mode.app_rd_data_reg[187] ;\n output \\not_strict_mode.app_rd_data_reg[171] ;\n output \\not_strict_mode.app_rd_data_reg[179] ;\n output \\not_strict_mode.app_rd_data_reg[163] ;\n output \\not_strict_mode.app_rd_data_reg[186] ;\n output \\not_strict_mode.app_rd_data_reg[170] ;\n output \\not_strict_mode.app_rd_data_reg[178] ;\n output \\not_strict_mode.app_rd_data_reg[162] ;\n output \\not_strict_mode.app_rd_data_reg[185] ;\n output \\not_strict_mode.app_rd_data_reg[169] ;\n output \\not_strict_mode.app_rd_data_reg[177] ;\n output \\not_strict_mode.app_rd_data_reg[161] ;\n output \\not_strict_mode.app_rd_data_reg[184] ;\n output \\not_strict_mode.app_rd_data_reg[168] ;\n output \\not_strict_mode.app_rd_data_reg[176] ;\n output \\not_strict_mode.app_rd_data_reg[160] ;\n output \\not_strict_mode.app_rd_data_reg[159] ;\n output \\not_strict_mode.app_rd_data_reg[143] ;\n output \\not_strict_mode.app_rd_data_reg[151] ;\n output \\not_strict_mode.app_rd_data_reg[135] ;\n output \\not_strict_mode.app_rd_data_reg[158] ;\n output \\not_strict_mode.app_rd_data_reg[142] ;\n output \\not_strict_mode.app_rd_data_reg[150] ;\n output \\not_strict_mode.app_rd_data_reg[134] ;\n output \\not_strict_mode.app_rd_data_reg[157] ;\n output \\not_strict_mode.app_rd_data_reg[141] ;\n output \\not_strict_mode.app_rd_data_reg[149] ;\n output \\not_strict_mode.app_rd_data_reg[133] ;\n output \\not_strict_mode.app_rd_data_reg[156] ;\n output \\not_strict_mode.app_rd_data_reg[140] ;\n output \\not_strict_mode.app_rd_data_reg[148] ;\n output \\not_strict_mode.app_rd_data_reg[132] ;\n output \\not_strict_mode.app_rd_data_reg[155] ;\n output \\not_strict_mode.app_rd_data_reg[139] ;\n output \\not_strict_mode.app_rd_data_reg[147] ;\n output \\not_strict_mode.app_rd_data_reg[131] ;\n output \\not_strict_mode.app_rd_data_reg[154] ;\n output \\not_strict_mode.app_rd_data_reg[138] ;\n output \\not_strict_mode.app_rd_data_reg[146] ;\n output \\not_strict_mode.app_rd_data_reg[130] ;\n output \\not_strict_mode.app_rd_data_reg[153] ;\n output \\not_strict_mode.app_rd_data_reg[137] ;\n output \\not_strict_mode.app_rd_data_reg[145] ;\n output \\not_strict_mode.app_rd_data_reg[129] ;\n output \\not_strict_mode.app_rd_data_reg[152] ;\n output \\not_strict_mode.app_rd_data_reg[136] ;\n output \\not_strict_mode.app_rd_data_reg[144] ;\n output \\not_strict_mode.app_rd_data_reg[128] ;\n output \\not_strict_mode.app_rd_data_reg[127] ;\n output \\not_strict_mode.app_rd_data_reg[111] ;\n output \\not_strict_mode.app_rd_data_reg[119] ;\n output \\not_strict_mode.app_rd_data_reg[103] ;\n output \\not_strict_mode.app_rd_data_reg[126] ;\n output \\not_strict_mode.app_rd_data_reg[110] ;\n output \\not_strict_mode.app_rd_data_reg[118] ;\n output \\not_strict_mode.app_rd_data_reg[102] ;\n output \\not_strict_mode.app_rd_data_reg[125] ;\n output \\not_strict_mode.app_rd_data_reg[109] ;\n output \\not_strict_mode.app_rd_data_reg[117] ;\n output \\not_strict_mode.app_rd_data_reg[101] ;\n output \\not_strict_mode.app_rd_data_reg[124] ;\n output \\not_strict_mode.app_rd_data_reg[108] ;\n output \\not_strict_mode.app_rd_data_reg[116] ;\n output \\not_strict_mode.app_rd_data_reg[100] ;\n output \\not_strict_mode.app_rd_data_reg[123] ;\n output \\not_strict_mode.app_rd_data_reg[107] ;\n output \\not_strict_mode.app_rd_data_reg[115] ;\n output \\not_strict_mode.app_rd_data_reg[99] ;\n output \\not_strict_mode.app_rd_data_reg[122] ;\n output \\not_strict_mode.app_rd_data_reg[106] ;\n output \\not_strict_mode.app_rd_data_reg[114] ;\n output \\not_strict_mode.app_rd_data_reg[98] ;\n output \\not_strict_mode.app_rd_data_reg[121] ;\n output \\not_strict_mode.app_rd_data_reg[105] ;\n output \\not_strict_mode.app_rd_data_reg[113] ;\n output \\not_strict_mode.app_rd_data_reg[97] ;\n output \\not_strict_mode.app_rd_data_reg[120] ;\n output \\not_strict_mode.app_rd_data_reg[104] ;\n output \\not_strict_mode.app_rd_data_reg[112] ;\n output \\not_strict_mode.app_rd_data_reg[96] ;\n output \\not_strict_mode.app_rd_data_reg[95] ;\n output \\not_strict_mode.app_rd_data_reg[79] ;\n output \\not_strict_mode.app_rd_data_reg[87] ;\n output \\not_strict_mode.app_rd_data_reg[71] ;\n output \\not_strict_mode.app_rd_data_reg[94] ;\n output \\not_strict_mode.app_rd_data_reg[78] ;\n output \\not_strict_mode.app_rd_data_reg[86] ;\n output \\not_strict_mode.app_rd_data_reg[70] ;\n output \\not_strict_mode.app_rd_data_reg[93] ;\n output \\not_strict_mode.app_rd_data_reg[77] ;\n output \\not_strict_mode.app_rd_data_reg[85] ;\n output \\not_strict_mode.app_rd_data_reg[69] ;\n output \\not_strict_mode.app_rd_data_reg[92] ;\n output \\not_strict_mode.app_rd_data_reg[76] ;\n output \\not_strict_mode.app_rd_data_reg[84] ;\n output \\not_strict_mode.app_rd_data_reg[68] ;\n output \\not_strict_mode.app_rd_data_reg[91] ;\n output \\not_strict_mode.app_rd_data_reg[75] ;\n output \\not_strict_mode.app_rd_data_reg[83] ;\n output \\not_strict_mode.app_rd_data_reg[67] ;\n output \\not_strict_mode.app_rd_data_reg[90] ;\n output \\not_strict_mode.app_rd_data_reg[74] ;\n output \\not_strict_mode.app_rd_data_reg[82] ;\n output \\not_strict_mode.app_rd_data_reg[66] ;\n output \\not_strict_mode.app_rd_data_reg[89] ;\n output \\not_strict_mode.app_rd_data_reg[73] ;\n output \\not_strict_mode.app_rd_data_reg[81] ;\n output \\not_strict_mode.app_rd_data_reg[65] ;\n output \\not_strict_mode.app_rd_data_reg[88] ;\n output \\not_strict_mode.app_rd_data_reg[72] ;\n output \\not_strict_mode.app_rd_data_reg[80] ;\n output \\not_strict_mode.app_rd_data_reg[64] ;\n output \\not_strict_mode.app_rd_data_reg[63] ;\n output \\not_strict_mode.app_rd_data_reg[47] ;\n output \\not_strict_mode.app_rd_data_reg[55] ;\n output \\not_strict_mode.app_rd_data_reg[39] ;\n output \\not_strict_mode.app_rd_data_reg[62] ;\n output \\not_strict_mode.app_rd_data_reg[46] ;\n output \\not_strict_mode.app_rd_data_reg[54] ;\n output \\not_strict_mode.app_rd_data_reg[38] ;\n output \\not_strict_mode.app_rd_data_reg[61] ;\n output \\not_strict_mode.app_rd_data_reg[45] ;\n output \\not_strict_mode.app_rd_data_reg[53] ;\n output \\not_strict_mode.app_rd_data_reg[37] ;\n output \\not_strict_mode.app_rd_data_reg[60] ;\n output \\not_strict_mode.app_rd_data_reg[44] ;\n output \\not_strict_mode.app_rd_data_reg[52] ;\n output \\not_strict_mode.app_rd_data_reg[36] ;\n output \\not_strict_mode.app_rd_data_reg[59] ;\n output \\not_strict_mode.app_rd_data_reg[43] ;\n output \\not_strict_mode.app_rd_data_reg[51] ;\n output \\not_strict_mode.app_rd_data_reg[35] ;\n output \\not_strict_mode.app_rd_data_reg[58] ;\n output \\not_strict_mode.app_rd_data_reg[42] ;\n output \\not_strict_mode.app_rd_data_reg[50] ;\n output \\not_strict_mode.app_rd_data_reg[34] ;\n output \\not_strict_mode.app_rd_data_reg[57] ;\n output \\not_strict_mode.app_rd_data_reg[41] ;\n output \\not_strict_mode.app_rd_data_reg[49] ;\n output \\not_strict_mode.app_rd_data_reg[33] ;\n output \\not_strict_mode.app_rd_data_reg[56] ;\n output \\not_strict_mode.app_rd_data_reg[40] ;\n output \\not_strict_mode.app_rd_data_reg[48] ;\n output \\not_strict_mode.app_rd_data_reg[32] ;\n output \\not_strict_mode.app_rd_data_reg[31] ;\n output \\not_strict_mode.app_rd_data_reg[15] ;\n output \\not_strict_mode.app_rd_data_reg[23] ;\n output \\not_strict_mode.app_rd_data_reg[7] ;\n output \\not_strict_mode.app_rd_data_reg[30] ;\n output \\not_strict_mode.app_rd_data_reg[14] ;\n output \\not_strict_mode.app_rd_data_reg[22] ;\n output \\not_strict_mode.app_rd_data_reg[6] ;\n output \\not_strict_mode.app_rd_data_reg[29] ;\n output \\not_strict_mode.app_rd_data_reg[13] ;\n output \\not_strict_mode.app_rd_data_reg[21] ;\n output \\not_strict_mode.app_rd_data_reg[5] ;\n output \\not_strict_mode.app_rd_data_reg[28] ;\n output \\not_strict_mode.app_rd_data_reg[12] ;\n output \\not_strict_mode.app_rd_data_reg[20] ;\n output \\not_strict_mode.app_rd_data_reg[4] ;\n output \\not_strict_mode.app_rd_data_reg[27] ;\n output \\not_strict_mode.app_rd_data_reg[11] ;\n output \\not_strict_mode.app_rd_data_reg[19] ;\n output \\not_strict_mode.app_rd_data_reg[3] ;\n output \\not_strict_mode.app_rd_data_reg[26] ;\n output \\not_strict_mode.app_rd_data_reg[10] ;\n output \\not_strict_mode.app_rd_data_reg[18] ;\n output \\not_strict_mode.app_rd_data_reg[2] ;\n output \\not_strict_mode.app_rd_data_reg[25] ;\n output \\not_strict_mode.app_rd_data_reg[9] ;\n output \\not_strict_mode.app_rd_data_reg[17] ;\n output \\not_strict_mode.app_rd_data_reg[1] ;\n output \\not_strict_mode.app_rd_data_reg[24] ;\n output \\not_strict_mode.app_rd_data_reg[8] ;\n output \\not_strict_mode.app_rd_data_reg[16] ;\n output \\not_strict_mode.app_rd_data_reg[0] ;\n output maint_prescaler_r1;\n output \\cmd_pipe_plus.mc_data_offset_reg[4] ;\n output [5:0]\\cmd_pipe_plus.mc_data_offset_reg[5] ;\n output \\cmd_pipe_plus.mc_data_offset_reg[1] ;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[4] ;\n output [5:0]\\cmd_pipe_plus.mc_data_offset_1_reg[5] ;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[1] ;\n output \\read_fifo.tail_r_reg[0] ;\n output \\cmd_pipe_plus.mc_data_offset_reg[0] ;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[0] ;\n output \\en_cnt_div4.enable_wrlvl_cnt_reg[3] ;\n output \\complex_row_cnt_ocal_reg[0] ;\n output \\row_cnt_victim_rotate.complex_row_cnt_reg[4] ;\n output [255:0]\\not_strict_mode.app_rd_data_reg[255]_0 ;\n output ofs_rdy_r_reg;\n output ofs_rdy_r_reg_0;\n output [3:0]\\wr_ptr_timing_reg[2] ;\n output [3:0]\\wr_ptr_timing_reg[2]_0 ;\n output [3:0]\\wr_ptr_timing_reg[2]_1 ;\n output [1:0]\\rd_ptr_timing_reg[0]_0 ;\n output wr_en;\n output wr_en_5;\n output wr_en_6;\n output [0:0]of_ctl_full_v;\n output [1:0]ddr_ck_out;\n output [0:0]\\qcntr_r_reg[0] ;\n inout [31:0]ddr3_dq;\n inout [3:0]ddr3_dqs_p;\n inout [3:0]ddr3_dqs_n;\n input idle;\n input mmcm_ps_clk;\n input rst_sync_r1;\n input CLK;\n input rstdiv0_sync_r1_reg_rep__20;\n input poc_sample_pd;\n input freq_refclk;\n input mem_refclk;\n input sync_pulse;\n input pll_locked;\n input in0;\n input CLKB0;\n input CLKB0_7;\n input CLKB0_8;\n input CLKB0_9;\n input RST0;\n input rstdiv0_sync_r1_reg_rep__9;\n input rstdiv0_sync_r1_reg_rep__10;\n input [0:0]rstdiv0_sync_r1_reg_rep__12;\n input [0:0]SR;\n input rstdiv0_sync_r1_reg_rep__23;\n input rstdiv0_sync_r1_reg_rep__13;\n input [1:0]rstdiv0_sync_r1_reg_rep__14;\n input rstdiv0_sync_r1_reg_rep__22;\n input rstdiv0_sync_r1_reg_rep__11;\n input cnt_pwron_reset_done_r0;\n input [1:0]rstdiv0_sync_r1_reg_rep__17;\n input [0:0]rstdiv0_sync_r1_reg_rep__16;\n input [0:0]SS;\n input tempmon_sample_en;\n input rstdiv0_sync_r1_reg_rep__2;\n input rstdiv0_sync_r1_reg_rep__6;\n input [1:0]\\cmd_pipe_plus.mc_address_reg[43] ;\n input [287:0]Q;\n input [17:0]mem_out;\n input [71:0]\\rd_ptr_reg[3] ;\n input rstdiv0_sync_r1_reg_rep__25;\n input rstdiv0_sync_r1_reg_rep__25_0;\n input rstdiv0_sync_r1_reg_rep__24;\n input [0:0]\\sm_r_reg[0]_0 ;\n input [29:0]\\rd_ptr_reg[3]_0 ;\n input [0:0]\\read_fifo.fifo_out_data_r_reg[6] ;\n input ram_init_done_r;\n input [2:0]mc_cas_n;\n input [2:0]mc_ras_n;\n input [0:0]mc_odt;\n input [0:0]mc_cke;\n input [2:0]mc_we_n;\n input [37:0]mc_address;\n input [8:0]mc_bank;\n input [0:0]mc_cs_n;\n input sys_rst;\n input [0:0]\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ;\n input mmcm_locked;\n input rstdiv0_sync_r1_reg_rep__25_1;\n input rstdiv0_sync_r1_reg_rep__25_2;\n input \\mmcm_init_trail_reg[0] ;\n input \\mmcm_current_reg[0] ;\n input [0:0]tail_r;\n input \\read_fifo.fifo_out_data_r_reg[6]_0 ;\n input [1:0]DOC;\n input [1:0]DOB;\n input [1:0]DOA;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ;\n input psdone;\n input rstdiv0_sync_r1_reg_rep__0;\n input [0:0]rstdiv0_sync_r1_reg_rep__19;\n input fine_adjust_reg;\n input samp_edge_cnt0_en_r_reg;\n input [0:0]pi_cnt_dec_reg;\n input rstdiv0_sync_r1_reg_rep__23_0;\n input p_81_in;\n input rstdiv0_sync_r1_reg_rep__23_1;\n input [0:0]po_cnt_dec_reg;\n input [0:0]rstdiv0_sync_r1_reg_rep__4;\n input rstdiv0_sync_r1_reg_rep__5;\n input [11:0]\\device_temp_r_reg[11] ;\n input [0:0]rstdiv0_sync_r1_reg_rep__7;\n input mc_wrdata_en;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[2] ;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[3] ;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ;\n input [1:0]mc_cmd;\n input \\cmd_pipe_plus.mc_data_offset_reg[0]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_reg[1]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_reg[2] ;\n input \\cmd_pipe_plus.mc_data_offset_reg[3] ;\n input \\cmd_pipe_plus.mc_data_offset_reg[4]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_reg[5]_0 ;\n input \\stg3_r_reg[0] ;\n input rstdiv0_sync_r1_reg_rep__8;\n\n wire CLK;\n wire CLKB0;\n wire CLKB0_7;\n wire CLKB0_8;\n wire CLKB0_9;\n wire [0:0]D;\n wire [1:0]DOA;\n wire [1:0]DOB;\n wire [1:0]DOC;\n wire [287:0]Q;\n wire RST0;\n wire [0:0]SR;\n wire [0:0]SS;\n wire app_zq_r_reg;\n wire [1:0]byte_sel_cnt;\n wire [1:0]calib_sel;\n wire [3:3]calib_sel__0;\n wire [1:0]calib_seq;\n wire \\calib_seq_reg[0] ;\n wire [1:0]\\cmd_pipe_plus.mc_address_reg[43] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[0] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[1] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[2] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[3] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[4] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ;\n wire [5:0]\\cmd_pipe_plus.mc_data_offset_1_reg[5] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[0] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[0]_0 ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[1] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[1]_0 ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[2] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[3] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[4] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[4]_0 ;\n wire [5:0]\\cmd_pipe_plus.mc_data_offset_reg[5] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[5]_0 ;\n wire cnt_pwron_reset_done_r0;\n wire \\complex_row_cnt_ocal_reg[0] ;\n wire [14:0]ddr3_addr;\n wire [2:0]ddr3_ba;\n wire ddr3_cas_n;\n wire [0:0]ddr3_cke;\n wire [0:0]ddr3_cs_n;\n wire [3:0]ddr3_dm;\n wire [31:0]ddr3_dq;\n wire [3:0]ddr3_dqs_n;\n wire [3:0]ddr3_dqs_p;\n wire [0:0]ddr3_odt;\n wire ddr3_ras_n;\n wire ddr3_reset_n;\n wire ddr3_we_n;\n wire [1:0]ddr_ck_out;\n wire [1:0]\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl/A ;\n wire [11:0]\\device_temp_r_reg[11] ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;\n wire dqs_po_en_stg2_f_reg;\n wire \\en_cnt_div4.enable_wrlvl_cnt_reg[3] ;\n wire fine_adjust_reg;\n wire [26:2]fine_delay_mod;\n wire fine_delay_sel_r;\n wire freq_refclk;\n wire idelay_inc;\n wire idle;\n wire in0;\n wire init_calib_complete_r_reg;\n wire maint_prescaler_r1;\n wire [37:0]mc_address;\n wire [8:0]mc_bank;\n wire [2:0]mc_cas_n;\n wire [0:0]mc_cke;\n wire [1:0]mc_cmd;\n wire [0:0]mc_cs_n;\n wire [0:0]mc_odt;\n wire [2:0]mc_ras_n;\n wire [2:0]mc_we_n;\n wire mc_wrdata_en;\n wire [17:0]mem_out;\n wire mem_refclk;\n wire \\mmcm_current_reg[0] ;\n wire \\mmcm_init_trail_reg[0] ;\n wire mmcm_locked;\n wire mmcm_ps_clk;\n wire [57:5]mux_address;\n wire mux_cmd_wren;\n wire [5:0]mux_data_offset_1;\n wire mux_reset_n;\n wire [255:0]mux_wrdata;\n wire mux_wrdata_en;\n wire [31:0]mux_wrdata_mask;\n wire \\not_strict_mode.app_rd_data_reg[0] ;\n wire \\not_strict_mode.app_rd_data_reg[100] ;\n wire \\not_strict_mode.app_rd_data_reg[101] ;\n wire \\not_strict_mode.app_rd_data_reg[102] ;\n wire \\not_strict_mode.app_rd_data_reg[103] ;\n wire \\not_strict_mode.app_rd_data_reg[104] ;\n wire \\not_strict_mode.app_rd_data_reg[105] ;\n wire \\not_strict_mode.app_rd_data_reg[106] ;\n wire \\not_strict_mode.app_rd_data_reg[107] ;\n wire \\not_strict_mode.app_rd_data_reg[108] ;\n wire \\not_strict_mode.app_rd_data_reg[109] ;\n wire \\not_strict_mode.app_rd_data_reg[10] ;\n wire \\not_strict_mode.app_rd_data_reg[110] ;\n wire \\not_strict_mode.app_rd_data_reg[111] ;\n wire \\not_strict_mode.app_rd_data_reg[112] ;\n wire \\not_strict_mode.app_rd_data_reg[113] ;\n wire \\not_strict_mode.app_rd_data_reg[114] ;\n wire \\not_strict_mode.app_rd_data_reg[115] ;\n wire \\not_strict_mode.app_rd_data_reg[116] ;\n wire \\not_strict_mode.app_rd_data_reg[117] ;\n wire \\not_strict_mode.app_rd_data_reg[118] ;\n wire \\not_strict_mode.app_rd_data_reg[119] ;\n wire \\not_strict_mode.app_rd_data_reg[11] ;\n wire \\not_strict_mode.app_rd_data_reg[120] ;\n wire \\not_strict_mode.app_rd_data_reg[121] ;\n wire \\not_strict_mode.app_rd_data_reg[122] ;\n wire \\not_strict_mode.app_rd_data_reg[123] ;\n wire \\not_strict_mode.app_rd_data_reg[124] ;\n wire \\not_strict_mode.app_rd_data_reg[125] ;\n wire \\not_strict_mode.app_rd_data_reg[126] ;\n wire \\not_strict_mode.app_rd_data_reg[127] ;\n wire \\not_strict_mode.app_rd_data_reg[128] ;\n wire \\not_strict_mode.app_rd_data_reg[129] ;\n wire \\not_strict_mode.app_rd_data_reg[12] ;\n wire \\not_strict_mode.app_rd_data_reg[130] ;\n wire \\not_strict_mode.app_rd_data_reg[131] ;\n wire \\not_strict_mode.app_rd_data_reg[132] ;\n wire \\not_strict_mode.app_rd_data_reg[133] ;\n wire \\not_strict_mode.app_rd_data_reg[134] ;\n wire \\not_strict_mode.app_rd_data_reg[135] ;\n wire \\not_strict_mode.app_rd_data_reg[136] ;\n wire \\not_strict_mode.app_rd_data_reg[137] ;\n wire \\not_strict_mode.app_rd_data_reg[138] ;\n wire \\not_strict_mode.app_rd_data_reg[139] ;\n wire \\not_strict_mode.app_rd_data_reg[13] ;\n wire \\not_strict_mode.app_rd_data_reg[140] ;\n wire \\not_strict_mode.app_rd_data_reg[141] ;\n wire \\not_strict_mode.app_rd_data_reg[142] ;\n wire \\not_strict_mode.app_rd_data_reg[143] ;\n wire \\not_strict_mode.app_rd_data_reg[144] ;\n wire \\not_strict_mode.app_rd_data_reg[145] ;\n wire \\not_strict_mode.app_rd_data_reg[146] ;\n wire \\not_strict_mode.app_rd_data_reg[147] ;\n wire \\not_strict_mode.app_rd_data_reg[148] ;\n wire \\not_strict_mode.app_rd_data_reg[149] ;\n wire \\not_strict_mode.app_rd_data_reg[14] ;\n wire \\not_strict_mode.app_rd_data_reg[150] ;\n wire \\not_strict_mode.app_rd_data_reg[151] ;\n wire \\not_strict_mode.app_rd_data_reg[152] ;\n wire \\not_strict_mode.app_rd_data_reg[153] ;\n wire \\not_strict_mode.app_rd_data_reg[154] ;\n wire \\not_strict_mode.app_rd_data_reg[155] ;\n wire \\not_strict_mode.app_rd_data_reg[156] ;\n wire \\not_strict_mode.app_rd_data_reg[157] ;\n wire \\not_strict_mode.app_rd_data_reg[158] ;\n wire \\not_strict_mode.app_rd_data_reg[159] ;\n wire \\not_strict_mode.app_rd_data_reg[15] ;\n wire \\not_strict_mode.app_rd_data_reg[160] ;\n wire \\not_strict_mode.app_rd_data_reg[161] ;\n wire \\not_strict_mode.app_rd_data_reg[162] ;\n wire \\not_strict_mode.app_rd_data_reg[163] ;\n wire \\not_strict_mode.app_rd_data_reg[164] ;\n wire \\not_strict_mode.app_rd_data_reg[165] ;\n wire \\not_strict_mode.app_rd_data_reg[166] ;\n wire \\not_strict_mode.app_rd_data_reg[167] ;\n wire \\not_strict_mode.app_rd_data_reg[168] ;\n wire \\not_strict_mode.app_rd_data_reg[169] ;\n wire \\not_strict_mode.app_rd_data_reg[16] ;\n wire \\not_strict_mode.app_rd_data_reg[170] ;\n wire \\not_strict_mode.app_rd_data_reg[171] ;\n wire \\not_strict_mode.app_rd_data_reg[172] ;\n wire \\not_strict_mode.app_rd_data_reg[173] ;\n wire \\not_strict_mode.app_rd_data_reg[174] ;\n wire \\not_strict_mode.app_rd_data_reg[175] ;\n wire \\not_strict_mode.app_rd_data_reg[176] ;\n wire \\not_strict_mode.app_rd_data_reg[177] ;\n wire \\not_strict_mode.app_rd_data_reg[178] ;\n wire \\not_strict_mode.app_rd_data_reg[179] ;\n wire \\not_strict_mode.app_rd_data_reg[17] ;\n wire \\not_strict_mode.app_rd_data_reg[180] ;\n wire \\not_strict_mode.app_rd_data_reg[181] ;\n wire \\not_strict_mode.app_rd_data_reg[182] ;\n wire \\not_strict_mode.app_rd_data_reg[183] ;\n wire \\not_strict_mode.app_rd_data_reg[184] ;\n wire \\not_strict_mode.app_rd_data_reg[185] ;\n wire \\not_strict_mode.app_rd_data_reg[186] ;\n wire \\not_strict_mode.app_rd_data_reg[187] ;\n wire \\not_strict_mode.app_rd_data_reg[188] ;\n wire \\not_strict_mode.app_rd_data_reg[189] ;\n wire \\not_strict_mode.app_rd_data_reg[18] ;\n wire \\not_strict_mode.app_rd_data_reg[190] ;\n wire \\not_strict_mode.app_rd_data_reg[191] ;\n wire \\not_strict_mode.app_rd_data_reg[192] ;\n wire \\not_strict_mode.app_rd_data_reg[193] ;\n wire \\not_strict_mode.app_rd_data_reg[194] ;\n wire \\not_strict_mode.app_rd_data_reg[195] ;\n wire \\not_strict_mode.app_rd_data_reg[196] ;\n wire \\not_strict_mode.app_rd_data_reg[197] ;\n wire \\not_strict_mode.app_rd_data_reg[198] ;\n wire \\not_strict_mode.app_rd_data_reg[199] ;\n wire \\not_strict_mode.app_rd_data_reg[19] ;\n wire \\not_strict_mode.app_rd_data_reg[1] ;\n wire \\not_strict_mode.app_rd_data_reg[200] ;\n wire \\not_strict_mode.app_rd_data_reg[201] ;\n wire \\not_strict_mode.app_rd_data_reg[202] ;\n wire \\not_strict_mode.app_rd_data_reg[203] ;\n wire \\not_strict_mode.app_rd_data_reg[204] ;\n wire \\not_strict_mode.app_rd_data_reg[205] ;\n wire \\not_strict_mode.app_rd_data_reg[206] ;\n wire \\not_strict_mode.app_rd_data_reg[207] ;\n wire \\not_strict_mode.app_rd_data_reg[208] ;\n wire \\not_strict_mode.app_rd_data_reg[209] ;\n wire \\not_strict_mode.app_rd_data_reg[20] ;\n wire \\not_strict_mode.app_rd_data_reg[210] ;\n wire \\not_strict_mode.app_rd_data_reg[211] ;\n wire \\not_strict_mode.app_rd_data_reg[212] ;\n wire \\not_strict_mode.app_rd_data_reg[213] ;\n wire \\not_strict_mode.app_rd_data_reg[214] ;\n wire \\not_strict_mode.app_rd_data_reg[215] ;\n wire \\not_strict_mode.app_rd_data_reg[216] ;\n wire \\not_strict_mode.app_rd_data_reg[217] ;\n wire \\not_strict_mode.app_rd_data_reg[218] ;\n wire \\not_strict_mode.app_rd_data_reg[219] ;\n wire \\not_strict_mode.app_rd_data_reg[21] ;\n wire \\not_strict_mode.app_rd_data_reg[220] ;\n wire \\not_strict_mode.app_rd_data_reg[221] ;\n wire \\not_strict_mode.app_rd_data_reg[222] ;\n wire \\not_strict_mode.app_rd_data_reg[223] ;\n wire \\not_strict_mode.app_rd_data_reg[224] ;\n wire \\not_strict_mode.app_rd_data_reg[225] ;\n wire \\not_strict_mode.app_rd_data_reg[226] ;\n wire \\not_strict_mode.app_rd_data_reg[227] ;\n wire \\not_strict_mode.app_rd_data_reg[228] ;\n wire \\not_strict_mode.app_rd_data_reg[229] ;\n wire \\not_strict_mode.app_rd_data_reg[22] ;\n wire \\not_strict_mode.app_rd_data_reg[230] ;\n wire \\not_strict_mode.app_rd_data_reg[231] ;\n wire \\not_strict_mode.app_rd_data_reg[232] ;\n wire \\not_strict_mode.app_rd_data_reg[233] ;\n wire \\not_strict_mode.app_rd_data_reg[234] ;\n wire \\not_strict_mode.app_rd_data_reg[235] ;\n wire \\not_strict_mode.app_rd_data_reg[236] ;\n wire \\not_strict_mode.app_rd_data_reg[237] ;\n wire \\not_strict_mode.app_rd_data_reg[238] ;\n wire \\not_strict_mode.app_rd_data_reg[239] ;\n wire \\not_strict_mode.app_rd_data_reg[23] ;\n wire \\not_strict_mode.app_rd_data_reg[240] ;\n wire \\not_strict_mode.app_rd_data_reg[241] ;\n wire \\not_strict_mode.app_rd_data_reg[242] ;\n wire \\not_strict_mode.app_rd_data_reg[243] ;\n wire \\not_strict_mode.app_rd_data_reg[244] ;\n wire \\not_strict_mode.app_rd_data_reg[245] ;\n wire \\not_strict_mode.app_rd_data_reg[246] ;\n wire \\not_strict_mode.app_rd_data_reg[247] ;\n wire \\not_strict_mode.app_rd_data_reg[248] ;\n wire \\not_strict_mode.app_rd_data_reg[249] ;\n wire \\not_strict_mode.app_rd_data_reg[24] ;\n wire \\not_strict_mode.app_rd_data_reg[250] ;\n wire \\not_strict_mode.app_rd_data_reg[251] ;\n wire \\not_strict_mode.app_rd_data_reg[252] ;\n wire \\not_strict_mode.app_rd_data_reg[253] ;\n wire \\not_strict_mode.app_rd_data_reg[254] ;\n wire \\not_strict_mode.app_rd_data_reg[255] ;\n wire [255:0]\\not_strict_mode.app_rd_data_reg[255]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[25] ;\n wire \\not_strict_mode.app_rd_data_reg[26] ;\n wire \\not_strict_mode.app_rd_data_reg[27] ;\n wire \\not_strict_mode.app_rd_data_reg[28] ;\n wire \\not_strict_mode.app_rd_data_reg[29] ;\n wire \\not_strict_mode.app_rd_data_reg[2] ;\n wire \\not_strict_mode.app_rd_data_reg[30] ;\n wire \\not_strict_mode.app_rd_data_reg[31] ;\n wire \\not_strict_mode.app_rd_data_reg[32] ;\n wire \\not_strict_mode.app_rd_data_reg[33] ;\n wire \\not_strict_mode.app_rd_data_reg[34] ;\n wire \\not_strict_mode.app_rd_data_reg[35] ;\n wire \\not_strict_mode.app_rd_data_reg[36] ;\n wire \\not_strict_mode.app_rd_data_reg[37] ;\n wire \\not_strict_mode.app_rd_data_reg[38] ;\n wire \\not_strict_mode.app_rd_data_reg[39] ;\n wire \\not_strict_mode.app_rd_data_reg[3] ;\n wire \\not_strict_mode.app_rd_data_reg[40] ;\n wire \\not_strict_mode.app_rd_data_reg[41] ;\n wire \\not_strict_mode.app_rd_data_reg[42] ;\n wire \\not_strict_mode.app_rd_data_reg[43] ;\n wire \\not_strict_mode.app_rd_data_reg[44] ;\n wire \\not_strict_mode.app_rd_data_reg[45] ;\n wire \\not_strict_mode.app_rd_data_reg[46] ;\n wire \\not_strict_mode.app_rd_data_reg[47] ;\n wire \\not_strict_mode.app_rd_data_reg[48] ;\n wire \\not_strict_mode.app_rd_data_reg[49] ;\n wire \\not_strict_mode.app_rd_data_reg[4] ;\n wire \\not_strict_mode.app_rd_data_reg[50] ;\n wire \\not_strict_mode.app_rd_data_reg[51] ;\n wire \\not_strict_mode.app_rd_data_reg[52] ;\n wire \\not_strict_mode.app_rd_data_reg[53] ;\n wire \\not_strict_mode.app_rd_data_reg[54] ;\n wire \\not_strict_mode.app_rd_data_reg[55] ;\n wire \\not_strict_mode.app_rd_data_reg[56] ;\n wire \\not_strict_mode.app_rd_data_reg[57] ;\n wire \\not_strict_mode.app_rd_data_reg[58] ;\n wire \\not_strict_mode.app_rd_data_reg[59] ;\n wire \\not_strict_mode.app_rd_data_reg[5] ;\n wire \\not_strict_mode.app_rd_data_reg[60] ;\n wire \\not_strict_mode.app_rd_data_reg[61] ;\n wire \\not_strict_mode.app_rd_data_reg[62] ;\n wire \\not_strict_mode.app_rd_data_reg[63] ;\n wire \\not_strict_mode.app_rd_data_reg[64] ;\n wire \\not_strict_mode.app_rd_data_reg[65] ;\n wire \\not_strict_mode.app_rd_data_reg[66] ;\n wire \\not_strict_mode.app_rd_data_reg[67] ;\n wire \\not_strict_mode.app_rd_data_reg[68] ;\n wire \\not_strict_mode.app_rd_data_reg[69] ;\n wire \\not_strict_mode.app_rd_data_reg[6] ;\n wire \\not_strict_mode.app_rd_data_reg[70] ;\n wire \\not_strict_mode.app_rd_data_reg[71] ;\n wire \\not_strict_mode.app_rd_data_reg[72] ;\n wire \\not_strict_mode.app_rd_data_reg[73] ;\n wire \\not_strict_mode.app_rd_data_reg[74] ;\n wire \\not_strict_mode.app_rd_data_reg[75] ;\n wire \\not_strict_mode.app_rd_data_reg[76] ;\n wire \\not_strict_mode.app_rd_data_reg[77] ;\n wire \\not_strict_mode.app_rd_data_reg[78] ;\n wire \\not_strict_mode.app_rd_data_reg[79] ;\n wire \\not_strict_mode.app_rd_data_reg[7] ;\n wire \\not_strict_mode.app_rd_data_reg[80] ;\n wire \\not_strict_mode.app_rd_data_reg[81] ;\n wire \\not_strict_mode.app_rd_data_reg[82] ;\n wire \\not_strict_mode.app_rd_data_reg[83] ;\n wire \\not_strict_mode.app_rd_data_reg[84] ;\n wire \\not_strict_mode.app_rd_data_reg[85] ;\n wire \\not_strict_mode.app_rd_data_reg[86] ;\n wire \\not_strict_mode.app_rd_data_reg[87] ;\n wire \\not_strict_mode.app_rd_data_reg[88] ;\n wire \\not_strict_mode.app_rd_data_reg[89] ;\n wire \\not_strict_mode.app_rd_data_reg[8] ;\n wire \\not_strict_mode.app_rd_data_reg[90] ;\n wire \\not_strict_mode.app_rd_data_reg[91] ;\n wire \\not_strict_mode.app_rd_data_reg[92] ;\n wire \\not_strict_mode.app_rd_data_reg[93] ;\n wire \\not_strict_mode.app_rd_data_reg[94] ;\n wire \\not_strict_mode.app_rd_data_reg[95] ;\n wire \\not_strict_mode.app_rd_data_reg[96] ;\n wire \\not_strict_mode.app_rd_data_reg[97] ;\n wire \\not_strict_mode.app_rd_data_reg[98] ;\n wire \\not_strict_mode.app_rd_data_reg[99] ;\n wire \\not_strict_mode.app_rd_data_reg[9] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ;\n wire \\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n wire [55:0]\\oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_data/data_bytes_ns ;\n wire [7:0]\\oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_data/data_bytes_r0 ;\n wire [0:0]of_ctl_full_v;\n wire ofs_rdy_r_reg;\n wire ofs_rdy_r_reg_0;\n wire [22:0]p_1_out;\n wire p_81_in;\n wire pd_out;\n wire \\periodic_rd_generation.periodic_rd_timer_r_reg[1] ;\n wire [3:0]phy_dout;\n wire phy_if_reset;\n wire phy_mc_ctl_full;\n wire phy_rddata_en;\n wire phy_read_calib;\n wire phy_write_calib;\n wire [0:0]pi_cnt_dec_reg;\n wire pi_en_stg2_f_timing_reg;\n wire \\pi_rst_stg1_cal_r_reg[0] ;\n wire pll_locked;\n wire [0:0]po_cnt_dec_reg;\n wire [1:0]po_stg2_wrcal_cnt;\n wire poc_sample_pd;\n wire psdone;\n wire [0:0]\\qcntr_r_reg[0] ;\n wire ram_init_done_r;\n wire rd_buf_we;\n wire [71:0]\\rd_ptr_reg[3] ;\n wire [29:0]\\rd_ptr_reg[3]_0 ;\n wire [33:0]\\rd_ptr_timing_reg[0] ;\n wire [1:0]\\rd_ptr_timing_reg[0]_0 ;\n wire \\rd_ptr_timing_reg[2] ;\n wire \\rd_ptr_timing_reg[2]_0 ;\n wire \\rd_ptr_timing_reg[2]_1 ;\n wire \\rd_ptr_timing_reg[2]_10 ;\n wire \\rd_ptr_timing_reg[2]_2 ;\n wire \\rd_ptr_timing_reg[2]_3 ;\n wire \\rd_ptr_timing_reg[2]_4 ;\n wire \\rd_ptr_timing_reg[2]_5 ;\n wire \\rd_ptr_timing_reg[2]_6 ;\n wire \\rd_ptr_timing_reg[2]_7 ;\n wire \\rd_ptr_timing_reg[2]_8 ;\n wire \\rd_ptr_timing_reg[2]_9 ;\n wire [0:0]\\read_fifo.fifo_out_data_r_reg[6] ;\n wire \\read_fifo.fifo_out_data_r_reg[6]_0 ;\n wire \\read_fifo.tail_r_reg[0] ;\n wire \\resume_wait_r_reg[5] ;\n wire \\row_cnt_victim_rotate.complex_row_cnt_reg[4] ;\n wire [0:0]\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ;\n wire rst_sync_r1;\n wire rst_sync_r1_reg;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__10;\n wire rstdiv0_sync_r1_reg_rep__11;\n wire [0:0]rstdiv0_sync_r1_reg_rep__12;\n wire rstdiv0_sync_r1_reg_rep__13;\n wire [1:0]rstdiv0_sync_r1_reg_rep__14;\n wire [0:0]rstdiv0_sync_r1_reg_rep__16;\n wire [1:0]rstdiv0_sync_r1_reg_rep__17;\n wire [0:0]rstdiv0_sync_r1_reg_rep__19;\n wire rstdiv0_sync_r1_reg_rep__2;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__22;\n wire rstdiv0_sync_r1_reg_rep__23;\n wire rstdiv0_sync_r1_reg_rep__23_0;\n wire rstdiv0_sync_r1_reg_rep__23_1;\n wire rstdiv0_sync_r1_reg_rep__24;\n wire rstdiv0_sync_r1_reg_rep__25;\n wire rstdiv0_sync_r1_reg_rep__25_0;\n wire rstdiv0_sync_r1_reg_rep__25_1;\n wire rstdiv0_sync_r1_reg_rep__25_2;\n wire [0:0]rstdiv0_sync_r1_reg_rep__4;\n wire rstdiv0_sync_r1_reg_rep__5;\n wire rstdiv0_sync_r1_reg_rep__6;\n wire [0:0]rstdiv0_sync_r1_reg_rep__7;\n wire rstdiv0_sync_r1_reg_rep__8;\n wire rstdiv0_sync_r1_reg_rep__9;\n wire samp_edge_cnt0_en_r;\n wire samp_edge_cnt0_en_r_reg;\n wire \\samps_r_reg[9] ;\n wire \\sm_r_reg[0] ;\n wire [0:0]\\sm_r_reg[0]_0 ;\n wire \\stg2_tap_cnt_reg[0] ;\n wire stg3_dec2init_val_r_reg;\n wire stg3_inc2init_val_r_reg;\n wire \\stg3_r_reg[0] ;\n wire sync_pulse;\n wire sys_rst;\n wire [0:0]tail_r;\n wire tempmon_sample_en;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire u_ddr_calib_top_n_37;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire u_ddr_calib_top_n_38;\n wire u_ddr_calib_top_n_385;\n wire u_ddr_calib_top_n_386;\n wire u_ddr_calib_top_n_387;\n wire u_ddr_calib_top_n_388;\n wire u_ddr_calib_top_n_389;\n wire u_ddr_calib_top_n_390;\n wire u_ddr_calib_top_n_391;\n wire u_ddr_calib_top_n_392;\n wire u_ddr_calib_top_n_393;\n wire u_ddr_calib_top_n_394;\n wire u_ddr_calib_top_n_395;\n wire u_ddr_calib_top_n_396;\n wire u_ddr_calib_top_n_397;\n wire u_ddr_calib_top_n_399;\n wire u_ddr_calib_top_n_400;\n wire u_ddr_calib_top_n_401;\n wire u_ddr_calib_top_n_402;\n wire u_ddr_calib_top_n_403;\n wire u_ddr_calib_top_n_404;\n wire u_ddr_calib_top_n_405;\n wire u_ddr_calib_top_n_406;\n wire u_ddr_calib_top_n_407;\n wire u_ddr_calib_top_n_408;\n wire u_ddr_calib_top_n_409;\n wire u_ddr_calib_top_n_410;\n wire u_ddr_calib_top_n_411;\n wire u_ddr_calib_top_n_412;\n wire u_ddr_calib_top_n_413;\n wire u_ddr_calib_top_n_414;\n wire u_ddr_calib_top_n_415;\n wire u_ddr_calib_top_n_416;\n wire u_ddr_calib_top_n_417;\n wire u_ddr_calib_top_n_418;\n wire u_ddr_calib_top_n_419;\n wire u_ddr_calib_top_n_420;\n wire u_ddr_calib_top_n_421;\n wire u_ddr_calib_top_n_422;\n wire u_ddr_calib_top_n_423;\n wire u_ddr_calib_top_n_424;\n wire u_ddr_calib_top_n_425;\n wire u_ddr_calib_top_n_426;\n wire u_ddr_calib_top_n_427;\n wire u_ddr_calib_top_n_428;\n wire u_ddr_calib_top_n_429;\n wire u_ddr_calib_top_n_430;\n wire u_ddr_calib_top_n_431;\n wire u_ddr_calib_top_n_432;\n wire u_ddr_calib_top_n_433;\n wire u_ddr_calib_top_n_434;\n wire u_ddr_calib_top_n_435;\n wire u_ddr_calib_top_n_436;\n wire u_ddr_calib_top_n_437;\n wire u_ddr_calib_top_n_438;\n wire u_ddr_calib_top_n_439;\n wire u_ddr_calib_top_n_441;\n wire u_ddr_calib_top_n_442;\n wire u_ddr_calib_top_n_443;\n wire u_ddr_calib_top_n_444;\n wire u_ddr_calib_top_n_445;\n wire u_ddr_calib_top_n_446;\n wire u_ddr_calib_top_n_447;\n wire u_ddr_calib_top_n_448;\n wire u_ddr_calib_top_n_449;\n wire u_ddr_calib_top_n_45;\n wire u_ddr_calib_top_n_450;\n wire u_ddr_calib_top_n_451;\n wire u_ddr_calib_top_n_452;\n wire u_ddr_calib_top_n_453;\n wire u_ddr_calib_top_n_454;\n wire u_ddr_calib_top_n_455;\n wire u_ddr_calib_top_n_456;\n wire u_ddr_calib_top_n_457;\n wire u_ddr_calib_top_n_458;\n wire u_ddr_calib_top_n_461;\n wire u_ddr_calib_top_n_464;\n wire u_ddr_calib_top_n_47;\n wire u_ddr_calib_top_n_50;\n wire u_ddr_calib_top_n_809;\n wire u_ddr_calib_top_n_810;\n wire u_ddr_calib_top_n_833;\n wire u_ddr_calib_top_n_834;\n wire u_ddr_calib_top_n_840;\n wire u_ddr_calib_top_n_841;\n wire u_ddr_calib_top_n_855;\n wire u_ddr_calib_top_n_856;\n wire u_ddr_calib_top_n_857;\n wire u_ddr_calib_top_n_858;\n wire u_ddr_calib_top_n_859;\n wire u_ddr_calib_top_n_860;\n wire u_ddr_calib_top_n_861;\n wire u_ddr_calib_top_n_875;\n wire u_ddr_calib_top_n_876;\n wire u_ddr_calib_top_n_877;\n wire u_ddr_calib_top_n_878;\n wire u_ddr_calib_top_n_879;\n wire u_ddr_calib_top_n_880;\n wire u_ddr_calib_top_n_881;\n wire u_ddr_calib_top_n_882;\n wire [2:2]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_fine_delay ;\n wire [26:5]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay ;\n wire [5:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_pi_counter_load_val ;\n wire [26:5]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay ;\n wire [5:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_counter_load_val ;\n wire [26:5]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay ;\n wire [5:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_counter_load_val ;\n wire \\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0 ;\n wire \\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst ;\n wire [4:4]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ;\n wire [0:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7 ;\n wire [0:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r ;\n wire \\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/LD0 ;\n wire \\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/idelay_ld_rst ;\n wire [4:4]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ;\n wire [8:8]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8 ;\n wire [8:8]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r ;\n wire \\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0 ;\n wire \\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst ;\n wire [4:4]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ;\n wire [8:8]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ;\n wire [8:8]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r ;\n wire \\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/LD0 ;\n wire \\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/idelay_ld_rst ;\n wire [4:4]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ;\n wire [8:8]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ;\n wire [8:8]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r ;\n wire \\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_coarse_enable110_out ;\n wire \\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_counter_read_en122_out ;\n wire \\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_enable107_out ;\n wire \\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_inc113_out ;\n wire \\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_sel_fine_oclk_delay125_out ;\n wire [2:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0 ;\n wire [2:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ;\n wire [3:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ;\n wire [7:4]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ;\n wire [7:4]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ;\n wire [2:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ;\n wire [2:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ;\n wire [3:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ;\n wire [3:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ;\n wire [3:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ;\n wire [3:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9 ;\n wire [67:8]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out ;\n wire [3:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 ;\n wire [3:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ;\n wire [3:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ;\n wire [3:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ;\n wire [3:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ;\n wire [3:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ;\n wire [3:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ;\n wire [3:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ;\n wire [5:0]\\u_ddr_mc_phy/pi_counter_read_val_w[0]_1 ;\n wire [8:0]\\u_ddr_mc_phy/po_counter_read_val_w[0]_0 ;\n wire [8:0]\\u_ddr_mc_phy/po_counter_read_val_w[1]_2 ;\n wire u_ddr_mc_phy_wrapper_n_1000;\n wire u_ddr_mc_phy_wrapper_n_1001;\n wire u_ddr_mc_phy_wrapper_n_1002;\n wire u_ddr_mc_phy_wrapper_n_1003;\n wire u_ddr_mc_phy_wrapper_n_1004;\n wire u_ddr_mc_phy_wrapper_n_1005;\n wire u_ddr_mc_phy_wrapper_n_1006;\n wire u_ddr_mc_phy_wrapper_n_1007;\n wire u_ddr_mc_phy_wrapper_n_1008;\n wire u_ddr_mc_phy_wrapper_n_1009;\n wire u_ddr_mc_phy_wrapper_n_1010;\n wire u_ddr_mc_phy_wrapper_n_1011;\n wire u_ddr_mc_phy_wrapper_n_1012;\n wire u_ddr_mc_phy_wrapper_n_1013;\n wire u_ddr_mc_phy_wrapper_n_1014;\n wire u_ddr_mc_phy_wrapper_n_1015;\n wire u_ddr_mc_phy_wrapper_n_1016;\n wire u_ddr_mc_phy_wrapper_n_1017;\n wire u_ddr_mc_phy_wrapper_n_1018;\n wire u_ddr_mc_phy_wrapper_n_1019;\n wire u_ddr_mc_phy_wrapper_n_102;\n wire u_ddr_mc_phy_wrapper_n_1020;\n wire u_ddr_mc_phy_wrapper_n_1021;\n wire u_ddr_mc_phy_wrapper_n_1022;\n wire u_ddr_mc_phy_wrapper_n_1023;\n wire u_ddr_mc_phy_wrapper_n_1024;\n wire u_ddr_mc_phy_wrapper_n_1025;\n wire u_ddr_mc_phy_wrapper_n_1026;\n wire u_ddr_mc_phy_wrapper_n_1027;\n wire u_ddr_mc_phy_wrapper_n_1028;\n wire u_ddr_mc_phy_wrapper_n_1029;\n wire u_ddr_mc_phy_wrapper_n_1030;\n wire u_ddr_mc_phy_wrapper_n_1033;\n wire u_ddr_mc_phy_wrapper_n_1034;\n wire u_ddr_mc_phy_wrapper_n_1035;\n wire u_ddr_mc_phy_wrapper_n_1036;\n wire u_ddr_mc_phy_wrapper_n_1037;\n wire u_ddr_mc_phy_wrapper_n_1038;\n wire u_ddr_mc_phy_wrapper_n_1039;\n wire u_ddr_mc_phy_wrapper_n_104;\n wire u_ddr_mc_phy_wrapper_n_1040;\n wire u_ddr_mc_phy_wrapper_n_1041;\n wire u_ddr_mc_phy_wrapper_n_1042;\n wire u_ddr_mc_phy_wrapper_n_1043;\n wire u_ddr_mc_phy_wrapper_n_1044;\n wire u_ddr_mc_phy_wrapper_n_1045;\n wire u_ddr_mc_phy_wrapper_n_1046;\n wire u_ddr_mc_phy_wrapper_n_1047;\n wire u_ddr_mc_phy_wrapper_n_1048;\n wire u_ddr_mc_phy_wrapper_n_1049;\n wire u_ddr_mc_phy_wrapper_n_1050;\n wire u_ddr_mc_phy_wrapper_n_1051;\n wire u_ddr_mc_phy_wrapper_n_1052;\n wire u_ddr_mc_phy_wrapper_n_1053;\n wire u_ddr_mc_phy_wrapper_n_1054;\n wire u_ddr_mc_phy_wrapper_n_1055;\n wire u_ddr_mc_phy_wrapper_n_1056;\n wire u_ddr_mc_phy_wrapper_n_1057;\n wire u_ddr_mc_phy_wrapper_n_1058;\n wire u_ddr_mc_phy_wrapper_n_1059;\n wire u_ddr_mc_phy_wrapper_n_106;\n wire u_ddr_mc_phy_wrapper_n_1060;\n wire u_ddr_mc_phy_wrapper_n_1061;\n wire u_ddr_mc_phy_wrapper_n_1062;\n wire u_ddr_mc_phy_wrapper_n_1063;\n wire u_ddr_mc_phy_wrapper_n_1064;\n wire u_ddr_mc_phy_wrapper_n_1065;\n wire u_ddr_mc_phy_wrapper_n_1066;\n wire u_ddr_mc_phy_wrapper_n_1067;\n wire u_ddr_mc_phy_wrapper_n_1068;\n wire u_ddr_mc_phy_wrapper_n_1069;\n wire u_ddr_mc_phy_wrapper_n_107;\n wire u_ddr_mc_phy_wrapper_n_1070;\n wire u_ddr_mc_phy_wrapper_n_1071;\n wire u_ddr_mc_phy_wrapper_n_1072;\n wire u_ddr_mc_phy_wrapper_n_1073;\n wire u_ddr_mc_phy_wrapper_n_1074;\n wire u_ddr_mc_phy_wrapper_n_1075;\n wire u_ddr_mc_phy_wrapper_n_1076;\n wire u_ddr_mc_phy_wrapper_n_1077;\n wire u_ddr_mc_phy_wrapper_n_1078;\n wire u_ddr_mc_phy_wrapper_n_1079;\n wire u_ddr_mc_phy_wrapper_n_108;\n wire u_ddr_mc_phy_wrapper_n_1080;\n wire u_ddr_mc_phy_wrapper_n_1081;\n wire u_ddr_mc_phy_wrapper_n_1082;\n wire u_ddr_mc_phy_wrapper_n_1083;\n wire u_ddr_mc_phy_wrapper_n_1084;\n wire u_ddr_mc_phy_wrapper_n_1085;\n wire u_ddr_mc_phy_wrapper_n_1086;\n wire u_ddr_mc_phy_wrapper_n_1087;\n wire u_ddr_mc_phy_wrapper_n_1088;\n wire u_ddr_mc_phy_wrapper_n_1089;\n wire u_ddr_mc_phy_wrapper_n_109;\n wire u_ddr_mc_phy_wrapper_n_1090;\n wire u_ddr_mc_phy_wrapper_n_1091;\n wire u_ddr_mc_phy_wrapper_n_1092;\n wire u_ddr_mc_phy_wrapper_n_1093;\n wire u_ddr_mc_phy_wrapper_n_1094;\n wire u_ddr_mc_phy_wrapper_n_1095;\n wire u_ddr_mc_phy_wrapper_n_1096;\n wire u_ddr_mc_phy_wrapper_n_110;\n wire u_ddr_mc_phy_wrapper_n_111;\n wire u_ddr_mc_phy_wrapper_n_112;\n wire u_ddr_mc_phy_wrapper_n_1127;\n wire u_ddr_mc_phy_wrapper_n_1129;\n wire u_ddr_mc_phy_wrapper_n_1130;\n wire u_ddr_mc_phy_wrapper_n_1131;\n wire u_ddr_mc_phy_wrapper_n_1132;\n wire u_ddr_mc_phy_wrapper_n_1133;\n wire u_ddr_mc_phy_wrapper_n_1134;\n wire u_ddr_mc_phy_wrapper_n_1135;\n wire u_ddr_mc_phy_wrapper_n_1136;\n wire u_ddr_mc_phy_wrapper_n_1137;\n wire u_ddr_mc_phy_wrapper_n_1138;\n wire u_ddr_mc_phy_wrapper_n_1139;\n wire u_ddr_mc_phy_wrapper_n_1140;\n wire u_ddr_mc_phy_wrapper_n_1141;\n wire u_ddr_mc_phy_wrapper_n_1142;\n wire u_ddr_mc_phy_wrapper_n_1143;\n wire u_ddr_mc_phy_wrapper_n_1144;\n wire u_ddr_mc_phy_wrapper_n_1145;\n wire u_ddr_mc_phy_wrapper_n_1146;\n wire u_ddr_mc_phy_wrapper_n_1147;\n wire u_ddr_mc_phy_wrapper_n_1148;\n wire u_ddr_mc_phy_wrapper_n_1149;\n wire u_ddr_mc_phy_wrapper_n_1150;\n wire u_ddr_mc_phy_wrapper_n_1151;\n wire u_ddr_mc_phy_wrapper_n_1152;\n wire u_ddr_mc_phy_wrapper_n_1153;\n wire u_ddr_mc_phy_wrapper_n_1154;\n wire u_ddr_mc_phy_wrapper_n_1155;\n wire u_ddr_mc_phy_wrapper_n_1156;\n wire u_ddr_mc_phy_wrapper_n_1157;\n wire u_ddr_mc_phy_wrapper_n_1158;\n wire u_ddr_mc_phy_wrapper_n_1159;\n wire u_ddr_mc_phy_wrapper_n_1160;\n wire u_ddr_mc_phy_wrapper_n_1161;\n wire u_ddr_mc_phy_wrapper_n_1162;\n wire u_ddr_mc_phy_wrapper_n_1163;\n wire u_ddr_mc_phy_wrapper_n_1164;\n wire u_ddr_mc_phy_wrapper_n_1165;\n wire u_ddr_mc_phy_wrapper_n_1166;\n wire u_ddr_mc_phy_wrapper_n_1167;\n wire u_ddr_mc_phy_wrapper_n_1168;\n wire u_ddr_mc_phy_wrapper_n_1169;\n wire u_ddr_mc_phy_wrapper_n_1170;\n wire u_ddr_mc_phy_wrapper_n_1171;\n wire u_ddr_mc_phy_wrapper_n_1172;\n wire u_ddr_mc_phy_wrapper_n_1173;\n wire u_ddr_mc_phy_wrapper_n_1174;\n wire u_ddr_mc_phy_wrapper_n_1175;\n wire u_ddr_mc_phy_wrapper_n_1176;\n wire u_ddr_mc_phy_wrapper_n_1177;\n wire u_ddr_mc_phy_wrapper_n_1178;\n wire u_ddr_mc_phy_wrapper_n_1179;\n wire u_ddr_mc_phy_wrapper_n_1180;\n wire u_ddr_mc_phy_wrapper_n_1181;\n wire u_ddr_mc_phy_wrapper_n_1182;\n wire u_ddr_mc_phy_wrapper_n_1183;\n wire u_ddr_mc_phy_wrapper_n_1184;\n wire u_ddr_mc_phy_wrapper_n_1185;\n wire u_ddr_mc_phy_wrapper_n_1186;\n wire u_ddr_mc_phy_wrapper_n_1187;\n wire u_ddr_mc_phy_wrapper_n_1188;\n wire u_ddr_mc_phy_wrapper_n_1189;\n wire u_ddr_mc_phy_wrapper_n_1190;\n wire u_ddr_mc_phy_wrapper_n_1191;\n wire u_ddr_mc_phy_wrapper_n_30;\n wire u_ddr_mc_phy_wrapper_n_43;\n wire u_ddr_mc_phy_wrapper_n_434;\n wire u_ddr_mc_phy_wrapper_n_435;\n wire u_ddr_mc_phy_wrapper_n_436;\n wire u_ddr_mc_phy_wrapper_n_437;\n wire u_ddr_mc_phy_wrapper_n_438;\n wire u_ddr_mc_phy_wrapper_n_439;\n wire u_ddr_mc_phy_wrapper_n_44;\n wire u_ddr_mc_phy_wrapper_n_440;\n wire u_ddr_mc_phy_wrapper_n_441;\n wire u_ddr_mc_phy_wrapper_n_442;\n wire u_ddr_mc_phy_wrapper_n_443;\n wire u_ddr_mc_phy_wrapper_n_444;\n wire u_ddr_mc_phy_wrapper_n_445;\n wire u_ddr_mc_phy_wrapper_n_446;\n wire u_ddr_mc_phy_wrapper_n_447;\n wire u_ddr_mc_phy_wrapper_n_448;\n wire u_ddr_mc_phy_wrapper_n_449;\n wire u_ddr_mc_phy_wrapper_n_45;\n wire u_ddr_mc_phy_wrapper_n_450;\n wire u_ddr_mc_phy_wrapper_n_451;\n wire u_ddr_mc_phy_wrapper_n_452;\n wire u_ddr_mc_phy_wrapper_n_453;\n wire u_ddr_mc_phy_wrapper_n_454;\n wire u_ddr_mc_phy_wrapper_n_455;\n wire u_ddr_mc_phy_wrapper_n_456;\n wire u_ddr_mc_phy_wrapper_n_457;\n wire u_ddr_mc_phy_wrapper_n_458;\n wire u_ddr_mc_phy_wrapper_n_459;\n wire u_ddr_mc_phy_wrapper_n_46;\n wire u_ddr_mc_phy_wrapper_n_460;\n wire u_ddr_mc_phy_wrapper_n_461;\n wire u_ddr_mc_phy_wrapper_n_462;\n wire u_ddr_mc_phy_wrapper_n_463;\n wire u_ddr_mc_phy_wrapper_n_464;\n wire u_ddr_mc_phy_wrapper_n_465;\n wire u_ddr_mc_phy_wrapper_n_466;\n wire u_ddr_mc_phy_wrapper_n_467;\n wire u_ddr_mc_phy_wrapper_n_468;\n wire u_ddr_mc_phy_wrapper_n_469;\n wire u_ddr_mc_phy_wrapper_n_470;\n wire u_ddr_mc_phy_wrapper_n_471;\n wire u_ddr_mc_phy_wrapper_n_472;\n wire u_ddr_mc_phy_wrapper_n_473;\n wire u_ddr_mc_phy_wrapper_n_474;\n wire u_ddr_mc_phy_wrapper_n_475;\n wire u_ddr_mc_phy_wrapper_n_476;\n wire u_ddr_mc_phy_wrapper_n_477;\n wire u_ddr_mc_phy_wrapper_n_478;\n wire u_ddr_mc_phy_wrapper_n_479;\n wire u_ddr_mc_phy_wrapper_n_480;\n wire u_ddr_mc_phy_wrapper_n_481;\n wire u_ddr_mc_phy_wrapper_n_482;\n wire u_ddr_mc_phy_wrapper_n_483;\n wire u_ddr_mc_phy_wrapper_n_484;\n wire u_ddr_mc_phy_wrapper_n_485;\n wire u_ddr_mc_phy_wrapper_n_486;\n wire u_ddr_mc_phy_wrapper_n_487;\n wire u_ddr_mc_phy_wrapper_n_488;\n wire u_ddr_mc_phy_wrapper_n_489;\n wire u_ddr_mc_phy_wrapper_n_490;\n wire u_ddr_mc_phy_wrapper_n_491;\n wire u_ddr_mc_phy_wrapper_n_492;\n wire u_ddr_mc_phy_wrapper_n_493;\n wire u_ddr_mc_phy_wrapper_n_494;\n wire u_ddr_mc_phy_wrapper_n_495;\n wire u_ddr_mc_phy_wrapper_n_496;\n wire u_ddr_mc_phy_wrapper_n_497;\n wire u_ddr_mc_phy_wrapper_n_60;\n wire u_ddr_mc_phy_wrapper_n_61;\n wire u_ddr_mc_phy_wrapper_n_63;\n wire u_ddr_mc_phy_wrapper_n_64;\n wire u_ddr_mc_phy_wrapper_n_65;\n wire u_ddr_mc_phy_wrapper_n_66;\n wire u_ddr_mc_phy_wrapper_n_67;\n wire u_ddr_mc_phy_wrapper_n_756;\n wire u_ddr_mc_phy_wrapper_n_757;\n wire u_ddr_mc_phy_wrapper_n_758;\n wire u_ddr_mc_phy_wrapper_n_759;\n wire u_ddr_mc_phy_wrapper_n_760;\n wire u_ddr_mc_phy_wrapper_n_761;\n wire u_ddr_mc_phy_wrapper_n_762;\n wire u_ddr_mc_phy_wrapper_n_763;\n wire u_ddr_mc_phy_wrapper_n_764;\n wire u_ddr_mc_phy_wrapper_n_765;\n wire u_ddr_mc_phy_wrapper_n_766;\n wire u_ddr_mc_phy_wrapper_n_767;\n wire u_ddr_mc_phy_wrapper_n_768;\n wire u_ddr_mc_phy_wrapper_n_769;\n wire u_ddr_mc_phy_wrapper_n_770;\n wire u_ddr_mc_phy_wrapper_n_771;\n wire u_ddr_mc_phy_wrapper_n_772;\n wire u_ddr_mc_phy_wrapper_n_773;\n wire u_ddr_mc_phy_wrapper_n_774;\n wire u_ddr_mc_phy_wrapper_n_775;\n wire u_ddr_mc_phy_wrapper_n_776;\n wire u_ddr_mc_phy_wrapper_n_777;\n wire u_ddr_mc_phy_wrapper_n_778;\n wire u_ddr_mc_phy_wrapper_n_779;\n wire u_ddr_mc_phy_wrapper_n_780;\n wire u_ddr_mc_phy_wrapper_n_781;\n wire u_ddr_mc_phy_wrapper_n_782;\n wire u_ddr_mc_phy_wrapper_n_783;\n wire u_ddr_mc_phy_wrapper_n_784;\n wire u_ddr_mc_phy_wrapper_n_785;\n wire u_ddr_mc_phy_wrapper_n_786;\n wire u_ddr_mc_phy_wrapper_n_787;\n wire u_ddr_mc_phy_wrapper_n_788;\n wire u_ddr_mc_phy_wrapper_n_789;\n wire u_ddr_mc_phy_wrapper_n_790;\n wire u_ddr_mc_phy_wrapper_n_791;\n wire u_ddr_mc_phy_wrapper_n_792;\n wire u_ddr_mc_phy_wrapper_n_793;\n wire u_ddr_mc_phy_wrapper_n_794;\n wire u_ddr_mc_phy_wrapper_n_795;\n wire u_ddr_mc_phy_wrapper_n_796;\n wire u_ddr_mc_phy_wrapper_n_797;\n wire u_ddr_mc_phy_wrapper_n_798;\n wire u_ddr_mc_phy_wrapper_n_799;\n wire u_ddr_mc_phy_wrapper_n_800;\n wire u_ddr_mc_phy_wrapper_n_801;\n wire u_ddr_mc_phy_wrapper_n_802;\n wire u_ddr_mc_phy_wrapper_n_803;\n wire u_ddr_mc_phy_wrapper_n_804;\n wire u_ddr_mc_phy_wrapper_n_805;\n wire u_ddr_mc_phy_wrapper_n_806;\n wire u_ddr_mc_phy_wrapper_n_807;\n wire u_ddr_mc_phy_wrapper_n_808;\n wire u_ddr_mc_phy_wrapper_n_809;\n wire u_ddr_mc_phy_wrapper_n_810;\n wire u_ddr_mc_phy_wrapper_n_811;\n wire u_ddr_mc_phy_wrapper_n_812;\n wire u_ddr_mc_phy_wrapper_n_813;\n wire u_ddr_mc_phy_wrapper_n_814;\n wire u_ddr_mc_phy_wrapper_n_815;\n wire u_ddr_mc_phy_wrapper_n_816;\n wire u_ddr_mc_phy_wrapper_n_817;\n wire u_ddr_mc_phy_wrapper_n_818;\n wire u_ddr_mc_phy_wrapper_n_819;\n wire u_ddr_mc_phy_wrapper_n_820;\n wire u_ddr_mc_phy_wrapper_n_835;\n wire u_ddr_mc_phy_wrapper_n_836;\n wire u_ddr_mc_phy_wrapper_n_837;\n wire u_ddr_mc_phy_wrapper_n_838;\n wire u_ddr_mc_phy_wrapper_n_839;\n wire u_ddr_mc_phy_wrapper_n_840;\n wire u_ddr_mc_phy_wrapper_n_841;\n wire u_ddr_mc_phy_wrapper_n_842;\n wire u_ddr_mc_phy_wrapper_n_843;\n wire u_ddr_mc_phy_wrapper_n_844;\n wire u_ddr_mc_phy_wrapper_n_845;\n wire u_ddr_mc_phy_wrapper_n_846;\n wire u_ddr_mc_phy_wrapper_n_847;\n wire u_ddr_mc_phy_wrapper_n_848;\n wire u_ddr_mc_phy_wrapper_n_849;\n wire u_ddr_mc_phy_wrapper_n_850;\n wire u_ddr_mc_phy_wrapper_n_851;\n wire u_ddr_mc_phy_wrapper_n_852;\n wire u_ddr_mc_phy_wrapper_n_853;\n wire u_ddr_mc_phy_wrapper_n_854;\n wire u_ddr_mc_phy_wrapper_n_855;\n wire u_ddr_mc_phy_wrapper_n_856;\n wire u_ddr_mc_phy_wrapper_n_857;\n wire u_ddr_mc_phy_wrapper_n_858;\n wire u_ddr_mc_phy_wrapper_n_859;\n wire u_ddr_mc_phy_wrapper_n_860;\n wire u_ddr_mc_phy_wrapper_n_861;\n wire u_ddr_mc_phy_wrapper_n_862;\n wire u_ddr_mc_phy_wrapper_n_863;\n wire u_ddr_mc_phy_wrapper_n_864;\n wire u_ddr_mc_phy_wrapper_n_865;\n wire u_ddr_mc_phy_wrapper_n_866;\n wire u_ddr_mc_phy_wrapper_n_867;\n wire u_ddr_mc_phy_wrapper_n_868;\n wire u_ddr_mc_phy_wrapper_n_869;\n wire u_ddr_mc_phy_wrapper_n_870;\n wire u_ddr_mc_phy_wrapper_n_871;\n wire u_ddr_mc_phy_wrapper_n_872;\n wire u_ddr_mc_phy_wrapper_n_873;\n wire u_ddr_mc_phy_wrapper_n_874;\n wire u_ddr_mc_phy_wrapper_n_875;\n wire u_ddr_mc_phy_wrapper_n_876;\n wire u_ddr_mc_phy_wrapper_n_877;\n wire u_ddr_mc_phy_wrapper_n_878;\n wire u_ddr_mc_phy_wrapper_n_879;\n wire u_ddr_mc_phy_wrapper_n_880;\n wire u_ddr_mc_phy_wrapper_n_881;\n wire u_ddr_mc_phy_wrapper_n_882;\n wire u_ddr_mc_phy_wrapper_n_883;\n wire u_ddr_mc_phy_wrapper_n_884;\n wire u_ddr_mc_phy_wrapper_n_885;\n wire u_ddr_mc_phy_wrapper_n_886;\n wire u_ddr_mc_phy_wrapper_n_887;\n wire u_ddr_mc_phy_wrapper_n_888;\n wire u_ddr_mc_phy_wrapper_n_889;\n wire u_ddr_mc_phy_wrapper_n_890;\n wire u_ddr_mc_phy_wrapper_n_891;\n wire u_ddr_mc_phy_wrapper_n_892;\n wire u_ddr_mc_phy_wrapper_n_893;\n wire u_ddr_mc_phy_wrapper_n_894;\n wire u_ddr_mc_phy_wrapper_n_895;\n wire u_ddr_mc_phy_wrapper_n_896;\n wire u_ddr_mc_phy_wrapper_n_897;\n wire u_ddr_mc_phy_wrapper_n_898;\n wire u_ddr_mc_phy_wrapper_n_901;\n wire u_ddr_mc_phy_wrapper_n_902;\n wire u_ddr_mc_phy_wrapper_n_903;\n wire u_ddr_mc_phy_wrapper_n_904;\n wire u_ddr_mc_phy_wrapper_n_905;\n wire u_ddr_mc_phy_wrapper_n_906;\n wire u_ddr_mc_phy_wrapper_n_907;\n wire u_ddr_mc_phy_wrapper_n_908;\n wire u_ddr_mc_phy_wrapper_n_909;\n wire u_ddr_mc_phy_wrapper_n_910;\n wire u_ddr_mc_phy_wrapper_n_911;\n wire u_ddr_mc_phy_wrapper_n_912;\n wire u_ddr_mc_phy_wrapper_n_913;\n wire u_ddr_mc_phy_wrapper_n_914;\n wire u_ddr_mc_phy_wrapper_n_915;\n wire u_ddr_mc_phy_wrapper_n_916;\n wire u_ddr_mc_phy_wrapper_n_917;\n wire u_ddr_mc_phy_wrapper_n_918;\n wire u_ddr_mc_phy_wrapper_n_919;\n wire u_ddr_mc_phy_wrapper_n_920;\n wire u_ddr_mc_phy_wrapper_n_921;\n wire u_ddr_mc_phy_wrapper_n_922;\n wire u_ddr_mc_phy_wrapper_n_923;\n wire u_ddr_mc_phy_wrapper_n_924;\n wire u_ddr_mc_phy_wrapper_n_925;\n wire u_ddr_mc_phy_wrapper_n_926;\n wire u_ddr_mc_phy_wrapper_n_927;\n wire u_ddr_mc_phy_wrapper_n_928;\n wire u_ddr_mc_phy_wrapper_n_929;\n wire u_ddr_mc_phy_wrapper_n_930;\n wire u_ddr_mc_phy_wrapper_n_931;\n wire u_ddr_mc_phy_wrapper_n_932;\n wire u_ddr_mc_phy_wrapper_n_933;\n wire u_ddr_mc_phy_wrapper_n_934;\n wire u_ddr_mc_phy_wrapper_n_935;\n wire u_ddr_mc_phy_wrapper_n_936;\n wire u_ddr_mc_phy_wrapper_n_937;\n wire u_ddr_mc_phy_wrapper_n_938;\n wire u_ddr_mc_phy_wrapper_n_939;\n wire u_ddr_mc_phy_wrapper_n_940;\n wire u_ddr_mc_phy_wrapper_n_941;\n wire u_ddr_mc_phy_wrapper_n_942;\n wire u_ddr_mc_phy_wrapper_n_943;\n wire u_ddr_mc_phy_wrapper_n_944;\n wire u_ddr_mc_phy_wrapper_n_945;\n wire u_ddr_mc_phy_wrapper_n_946;\n wire u_ddr_mc_phy_wrapper_n_947;\n wire u_ddr_mc_phy_wrapper_n_948;\n wire u_ddr_mc_phy_wrapper_n_949;\n wire u_ddr_mc_phy_wrapper_n_950;\n wire u_ddr_mc_phy_wrapper_n_951;\n wire u_ddr_mc_phy_wrapper_n_952;\n wire u_ddr_mc_phy_wrapper_n_953;\n wire u_ddr_mc_phy_wrapper_n_954;\n wire u_ddr_mc_phy_wrapper_n_955;\n wire u_ddr_mc_phy_wrapper_n_956;\n wire u_ddr_mc_phy_wrapper_n_957;\n wire u_ddr_mc_phy_wrapper_n_958;\n wire u_ddr_mc_phy_wrapper_n_959;\n wire u_ddr_mc_phy_wrapper_n_960;\n wire u_ddr_mc_phy_wrapper_n_961;\n wire u_ddr_mc_phy_wrapper_n_962;\n wire u_ddr_mc_phy_wrapper_n_963;\n wire u_ddr_mc_phy_wrapper_n_964;\n wire u_ddr_mc_phy_wrapper_n_967;\n wire u_ddr_mc_phy_wrapper_n_968;\n wire u_ddr_mc_phy_wrapper_n_969;\n wire u_ddr_mc_phy_wrapper_n_970;\n wire u_ddr_mc_phy_wrapper_n_971;\n wire u_ddr_mc_phy_wrapper_n_972;\n wire u_ddr_mc_phy_wrapper_n_973;\n wire u_ddr_mc_phy_wrapper_n_974;\n wire u_ddr_mc_phy_wrapper_n_975;\n wire u_ddr_mc_phy_wrapper_n_976;\n wire u_ddr_mc_phy_wrapper_n_977;\n wire u_ddr_mc_phy_wrapper_n_978;\n wire u_ddr_mc_phy_wrapper_n_979;\n wire u_ddr_mc_phy_wrapper_n_980;\n wire u_ddr_mc_phy_wrapper_n_981;\n wire u_ddr_mc_phy_wrapper_n_982;\n wire u_ddr_mc_phy_wrapper_n_983;\n wire u_ddr_mc_phy_wrapper_n_984;\n wire u_ddr_mc_phy_wrapper_n_985;\n wire u_ddr_mc_phy_wrapper_n_986;\n wire u_ddr_mc_phy_wrapper_n_987;\n wire u_ddr_mc_phy_wrapper_n_988;\n wire u_ddr_mc_phy_wrapper_n_989;\n wire u_ddr_mc_phy_wrapper_n_990;\n wire u_ddr_mc_phy_wrapper_n_991;\n wire u_ddr_mc_phy_wrapper_n_992;\n wire u_ddr_mc_phy_wrapper_n_993;\n wire u_ddr_mc_phy_wrapper_n_994;\n wire u_ddr_mc_phy_wrapper_n_995;\n wire u_ddr_mc_phy_wrapper_n_996;\n wire u_ddr_mc_phy_wrapper_n_997;\n wire u_ddr_mc_phy_wrapper_n_998;\n wire u_ddr_mc_phy_wrapper_n_999;\n wire \\u_ddr_phy_wrcal/p_0_out ;\n wire wr_en;\n wire wr_en_5;\n wire wr_en_6;\n wire [3:0]\\wr_ptr_timing_reg[2] ;\n wire [3:0]\\wr_ptr_timing_reg[2]_0 ;\n wire [3:0]\\wr_ptr_timing_reg[2]_1 ;\n\n ddr3_ifmig_7series_v4_0_ddr_calib_top u_ddr_calib_top\n (.A(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl/A ),\n .\\A[0]__0 (u_ddr_calib_top_n_877),\n .\\A[0]__4 (u_ddr_calib_top_n_876),\n .\\A[1]_0 (u_ddr_mc_phy_wrapper_n_813),\n .\\A[1]_1 (u_ddr_mc_phy_wrapper_n_805),\n .\\A[1]_10 (u_ddr_mc_phy_wrapper_n_798),\n .\\A[1]_11 (u_ddr_mc_phy_wrapper_n_790),\n .\\A[1]_12 (u_ddr_mc_phy_wrapper_n_782),\n .\\A[1]_13 (u_ddr_mc_phy_wrapper_n_774),\n .\\A[1]_14 (u_ddr_mc_phy_wrapper_n_766),\n .\\A[1]_15 (u_ddr_mc_phy_wrapper_n_758),\n .\\A[1]_16 (u_ddr_mc_phy_wrapper_n_815),\n .\\A[1]_17 (u_ddr_mc_phy_wrapper_n_807),\n .\\A[1]_18 (u_ddr_mc_phy_wrapper_n_799),\n .\\A[1]_19 (u_ddr_mc_phy_wrapper_n_791),\n .\\A[1]_2 (u_ddr_mc_phy_wrapper_n_797),\n .\\A[1]_20 (u_ddr_mc_phy_wrapper_n_783),\n .\\A[1]_21 (u_ddr_mc_phy_wrapper_n_775),\n .\\A[1]_22 (u_ddr_mc_phy_wrapper_n_767),\n .\\A[1]_23 (u_ddr_mc_phy_wrapper_n_759),\n .\\A[1]_24 (u_ddr_mc_phy_wrapper_n_816),\n .\\A[1]_25 (u_ddr_mc_phy_wrapper_n_808),\n .\\A[1]_26 (u_ddr_mc_phy_wrapper_n_800),\n .\\A[1]_27 (u_ddr_mc_phy_wrapper_n_792),\n .\\A[1]_28 (u_ddr_mc_phy_wrapper_n_784),\n .\\A[1]_29 (u_ddr_mc_phy_wrapper_n_776),\n .\\A[1]_3 (u_ddr_mc_phy_wrapper_n_789),\n .\\A[1]_30 (u_ddr_mc_phy_wrapper_n_768),\n .\\A[1]_31 (u_ddr_mc_phy_wrapper_n_760),\n .\\A[1]_32 (u_ddr_mc_phy_wrapper_n_817),\n .\\A[1]_33 (u_ddr_mc_phy_wrapper_n_809),\n .\\A[1]_34 (u_ddr_mc_phy_wrapper_n_801),\n .\\A[1]_35 (u_ddr_mc_phy_wrapper_n_793),\n .\\A[1]_36 (u_ddr_mc_phy_wrapper_n_785),\n .\\A[1]_37 (u_ddr_mc_phy_wrapper_n_777),\n .\\A[1]_38 (u_ddr_mc_phy_wrapper_n_769),\n .\\A[1]_39 (u_ddr_mc_phy_wrapper_n_761),\n .\\A[1]_4 (u_ddr_mc_phy_wrapper_n_781),\n .\\A[1]_40 (u_ddr_mc_phy_wrapper_n_818),\n .\\A[1]_41 (u_ddr_mc_phy_wrapper_n_810),\n .\\A[1]_42 (u_ddr_mc_phy_wrapper_n_802),\n .\\A[1]_43 (u_ddr_mc_phy_wrapper_n_794),\n .\\A[1]_44 (u_ddr_mc_phy_wrapper_n_786),\n .\\A[1]_45 (u_ddr_mc_phy_wrapper_n_778),\n .\\A[1]_46 (u_ddr_mc_phy_wrapper_n_770),\n .\\A[1]_47 (u_ddr_mc_phy_wrapper_n_762),\n .\\A[1]_48 (u_ddr_mc_phy_wrapper_n_819),\n .\\A[1]_49 (u_ddr_mc_phy_wrapper_n_811),\n .\\A[1]_5 (u_ddr_mc_phy_wrapper_n_773),\n .\\A[1]_50 (u_ddr_mc_phy_wrapper_n_803),\n .\\A[1]_51 (u_ddr_mc_phy_wrapper_n_795),\n .\\A[1]_52 (u_ddr_mc_phy_wrapper_n_787),\n .\\A[1]_53 (u_ddr_mc_phy_wrapper_n_779),\n .\\A[1]_54 (u_ddr_mc_phy_wrapper_n_771),\n .\\A[1]_55 (u_ddr_mc_phy_wrapper_n_763),\n .\\A[1]_56 (u_ddr_mc_phy_wrapper_n_820),\n .\\A[1]_57 (u_ddr_mc_phy_wrapper_n_812),\n .\\A[1]_58 (u_ddr_mc_phy_wrapper_n_804),\n .\\A[1]_59 (u_ddr_mc_phy_wrapper_n_796),\n .\\A[1]_6 (u_ddr_mc_phy_wrapper_n_765),\n .\\A[1]_60 (u_ddr_mc_phy_wrapper_n_788),\n .\\A[1]_61 (u_ddr_mc_phy_wrapper_n_780),\n .\\A[1]_62 (u_ddr_mc_phy_wrapper_n_772),\n .\\A[1]_63 (u_ddr_mc_phy_wrapper_n_764),\n .\\A[1]_7 (u_ddr_mc_phy_wrapper_n_757),\n .\\A[1]_8 (u_ddr_mc_phy_wrapper_n_814),\n .\\A[1]_9 (u_ddr_mc_phy_wrapper_n_806),\n .\\A[1]__0 (u_ddr_calib_top_n_879),\n .\\A[1]__3 (u_ddr_calib_top_n_881),\n .\\A[1]__4 (u_ddr_calib_top_n_464),\n .\\A[1]__4_0 (u_ddr_calib_top_n_880),\n .\\A[2]__1 (u_ddr_calib_top_n_882),\n .\\A[2]__2 (u_ddr_calib_top_n_878),\n .\\A[2]__2_0 (u_ddr_mc_phy_wrapper_n_30),\n .A_1__s_port_(u_ddr_calib_top_n_461),\n .A_rst_primitives_reg(u_ddr_mc_phy_wrapper_n_756),\n .CLK(CLK),\n .COUNTERLOADVAL({u_ddr_calib_top_n_441,u_ddr_calib_top_n_442,u_ddr_calib_top_n_443,u_ddr_calib_top_n_444,u_ddr_calib_top_n_445,u_ddr_calib_top_n_446}),\n .D({u_ddr_calib_top_n_433,u_ddr_calib_top_n_434,u_ddr_calib_top_n_435,u_ddr_calib_top_n_436,u_ddr_calib_top_n_437,u_ddr_calib_top_n_438,u_ddr_calib_top_n_439,\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_fine_delay }),\n .D0(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0 ),\n .D1(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ),\n .D2(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ),\n .D3(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ),\n .D4(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ),\n .D5(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ),\n .D6(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ),\n .D7(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ),\n .D8(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ),\n .D9(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9 ),\n .D_po_coarse_enable110_out(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_coarse_enable110_out ),\n .D_po_counter_read_en122_out(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_counter_read_en122_out ),\n .D_po_fine_enable107_out(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_enable107_out ),\n .D_po_fine_inc113_out(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_inc113_out ),\n .D_po_sel_fine_oclk_delay125_out(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_sel_fine_oclk_delay125_out ),\n .E(\\resume_wait_r_reg[5] ),\n .LD0(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0 ),\n .LD0_0(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/LD0 ),\n .LD0_1(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0 ),\n .LD0_2(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/LD0 ),\n .Q(Q),\n .SR(SR),\n .SS(SS),\n .app_zq_r_reg(app_zq_r_reg),\n .\\byte_r_reg[0] (u_ddr_calib_top_n_809),\n .\\byte_r_reg[0]_0 ({\\oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_data/data_bytes_r0 ,\\oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_data/data_bytes_ns }),\n .\\byte_r_reg[1] (u_ddr_calib_top_n_810),\n .\\byte_sel_data_map_reg[1] (u_ddr_calib_top_n_875),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[0] (\\cmd_pipe_plus.mc_data_offset_1_reg[0] ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 (\\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[1] (\\cmd_pipe_plus.mc_data_offset_1_reg[1] ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[1]_0 (\\cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[2] (\\cmd_pipe_plus.mc_data_offset_1_reg[2] ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[3] (\\cmd_pipe_plus.mc_data_offset_1_reg[3] ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[4] (\\cmd_pipe_plus.mc_data_offset_1_reg[4] ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[4]_0 (\\cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[5] (\\cmd_pipe_plus.mc_data_offset_1_reg[5] ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[5]_0 (\\cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_reg[0] (\\cmd_pipe_plus.mc_data_offset_reg[0] ),\n .\\cmd_pipe_plus.mc_data_offset_reg[0]_0 (\\cmd_pipe_plus.mc_data_offset_reg[0]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_reg[1] (\\cmd_pipe_plus.mc_data_offset_reg[1] ),\n .\\cmd_pipe_plus.mc_data_offset_reg[1]_0 (\\cmd_pipe_plus.mc_data_offset_reg[1]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_reg[2] (\\cmd_pipe_plus.mc_data_offset_reg[2] ),\n .\\cmd_pipe_plus.mc_data_offset_reg[3] (\\cmd_pipe_plus.mc_data_offset_reg[3] ),\n .\\cmd_pipe_plus.mc_data_offset_reg[4] (\\cmd_pipe_plus.mc_data_offset_reg[4] ),\n .\\cmd_pipe_plus.mc_data_offset_reg[4]_0 (\\cmd_pipe_plus.mc_data_offset_reg[4]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_reg[5] (\\cmd_pipe_plus.mc_data_offset_reg[5] ),\n .\\cmd_pipe_plus.mc_data_offset_reg[5]_0 (\\cmd_pipe_plus.mc_data_offset_reg[5]_0 ),\n .cnt_pwron_reset_done_r0(cnt_pwron_reset_done_r0),\n .\\complex_row_cnt_ocal_reg[0] (\\complex_row_cnt_ocal_reg[0] ),\n .\\data_offset_1_i1_reg[5] (mux_data_offset_1),\n .\\device_temp_r_reg[11] (\\device_temp_r_reg[11] ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (u_ddr_calib_top_n_405),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (u_ddr_calib_top_n_415),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (u_ddr_calib_top_n_425),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (u_ddr_calib_top_n_449),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 (u_ddr_mc_phy_wrapper_n_1127),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 (u_ddr_mc_phy_wrapper_n_104),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\\not_strict_mode.app_rd_data_reg[6] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\\not_strict_mode.app_rd_data_reg[14] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 (\\not_strict_mode.app_rd_data_reg[22] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 (\\not_strict_mode.app_rd_data_reg[29] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\\not_strict_mode.app_rd_data_reg[5] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\\not_strict_mode.app_rd_data_reg[13] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 (\\not_strict_mode.app_rd_data_reg[21] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 (\\not_strict_mode.app_rd_data_reg[28] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\\not_strict_mode.app_rd_data_reg[4] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\\not_strict_mode.app_rd_data_reg[12] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 (\\not_strict_mode.app_rd_data_reg[20] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 (\\not_strict_mode.app_rd_data_reg[27] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\\not_strict_mode.app_rd_data_reg[3] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\\not_strict_mode.app_rd_data_reg[11] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 (\\not_strict_mode.app_rd_data_reg[19] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 (\\not_strict_mode.app_rd_data_reg[26] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\\not_strict_mode.app_rd_data_reg[2] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\\not_strict_mode.app_rd_data_reg[10] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 (\\not_strict_mode.app_rd_data_reg[18] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 (\\not_strict_mode.app_rd_data_reg[25] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\\not_strict_mode.app_rd_data_reg[1] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\\not_strict_mode.app_rd_data_reg[9] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 (\\not_strict_mode.app_rd_data_reg[17] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 (\\not_strict_mode.app_rd_data_reg[24] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (\\not_strict_mode.app_rd_data_reg[0] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (\\not_strict_mode.app_rd_data_reg[8] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 (\\not_strict_mode.app_rd_data_reg[16] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 (\\not_strict_mode.app_rd_data_reg[30] ),\n .dqs_po_en_stg2_f_reg(dqs_po_en_stg2_f_reg),\n .\\en_cnt_div4.enable_wrlvl_cnt_reg[3] (\\en_cnt_div4.enable_wrlvl_cnt_reg[3] ),\n .fine_adjust_reg(fine_adjust_reg),\n .fine_delay_mod({fine_delay_mod[26],fine_delay_mod[23],fine_delay_mod[20],fine_delay_mod[17],fine_delay_mod[14],fine_delay_mod[11],fine_delay_mod[8],fine_delay_mod[5],fine_delay_mod[2]}),\n .\\fine_delay_mod_reg[20] (u_ddr_calib_top_n_841),\n .\\fine_delay_mod_reg[26] (u_ddr_calib_top_n_855),\n .\\fine_delay_mod_reg[5] (u_ddr_calib_top_n_840),\n .\\fine_delay_r_reg[26] ({\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [26],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [23],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [20],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [17],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [14],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [11],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [8],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [5]}),\n .\\fine_delay_r_reg[26]_0 ({\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [26],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [23],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [20],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [17],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [14],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [11],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [8],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [5]}),\n .\\fine_delay_r_reg[26]_1 ({\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [26],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [23],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [20],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [17],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [14],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [11],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [8],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [5]}),\n .\\fine_delay_r_reg[2] (u_ddr_calib_top_n_448),\n .\\fine_delay_r_reg[5] (u_ddr_calib_top_n_404),\n .\\fine_delay_r_reg[5]_0 (u_ddr_calib_top_n_414),\n .\\fine_delay_r_reg[5]_1 (u_ddr_calib_top_n_424),\n .fine_delay_sel_r(fine_delay_sel_r),\n .fine_delay_sel_r_reg(u_ddr_calib_top_n_50),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 (byte_sel_cnt),\n .\\genblk9[1].fine_delay_incdec_pb_reg[1] (u_ddr_calib_top_n_856),\n .\\genblk9[2].fine_delay_incdec_pb_reg[2] (u_ddr_calib_top_n_857),\n .\\genblk9[3].fine_delay_incdec_pb_reg[3] (u_ddr_calib_top_n_858),\n .\\genblk9[5].fine_delay_incdec_pb_reg[5] (u_ddr_calib_top_n_859),\n .\\genblk9[6].fine_delay_incdec_pb_reg[6] (u_ddr_calib_top_n_860),\n .\\genblk9[7].fine_delay_incdec_pb_reg[7] (u_ddr_calib_top_n_861),\n .idelay_inc(idelay_inc),\n .idelay_ld_rst(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst ),\n .idelay_ld_rst_3(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/idelay_ld_rst ),\n .idelay_ld_rst_4(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst ),\n .idelay_ld_rst_5(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/idelay_ld_rst ),\n .\\idelay_tap_cnt_r_reg[0][3][0] (po_stg2_wrcal_cnt),\n .ififo_rst_reg(u_ddr_calib_top_n_409),\n .ififo_rst_reg_0(u_ddr_calib_top_n_419),\n .ififo_rst_reg_1(u_ddr_calib_top_n_429),\n .ififo_rst_reg_2(u_ddr_calib_top_n_453),\n .in0({u_ddr_mc_phy_wrapper_n_43,u_ddr_mc_phy_wrapper_n_44,u_ddr_mc_phy_wrapper_n_45,u_ddr_mc_phy_wrapper_n_46}),\n .init_calib_complete_r_reg(init_calib_complete_r_reg),\n .maint_prescaler_r1(maint_prescaler_r1),\n .\\mcGo_r_reg[15] (\\calib_seq_reg[0] ),\n .mc_address({mc_address[37],mc_address[35:14],mc_address[12:0]}),\n .mc_bank(mc_bank),\n .mc_cas_n(mc_cas_n),\n .mc_cke(mc_cke),\n .mc_cmd(mc_cmd),\n .mc_cs_n(mc_cs_n),\n .mc_odt(mc_odt),\n .mc_ras_n(mc_ras_n),\n .mc_we_n(mc_we_n),\n .mc_wrdata_en(mc_wrdata_en),\n .mem_out({mem_out[10:8],mem_out[2:0]}),\n .\\mmcm_current_reg[0] (\\mmcm_current_reg[0] ),\n .\\mmcm_init_trail_reg[0] (\\mmcm_init_trail_reg[0] ),\n .mux_cmd_wren(mux_cmd_wren),\n .mux_reset_n(mux_reset_n),\n .mux_wrdata_en(mux_wrdata_en),\n .my_empty(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ),\n .my_empty_6(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ),\n .my_empty_7(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ),\n .my_empty_8(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ),\n .\\my_empty_reg[1] (u_ddr_mc_phy_wrapper_n_61),\n .\\my_empty_reg[1]_0 (u_ddr_mc_phy_wrapper_n_60),\n .\\my_empty_reg[1]_1 (u_ddr_mc_phy_wrapper_n_63),\n .\\my_empty_reg[1]_2 (u_ddr_mc_phy_wrapper_n_102),\n .\\my_empty_reg[1]_3 (u_ddr_mc_phy_wrapper_n_67),\n .\\my_empty_reg[1]_4 (u_ddr_mc_phy_wrapper_n_66),\n .\\my_empty_reg[1]_5 (u_ddr_mc_phy_wrapper_n_65),\n .\\my_empty_reg[1]_6 (u_ddr_mc_phy_wrapper_n_64),\n .\\my_empty_reg[7] (u_ddr_calib_top_n_37),\n .\\my_empty_reg[7]_0 ({mux_wrdata_mask[28],mux_wrdata_mask[24],mux_wrdata_mask[20],mux_wrdata_mask[16],mux_wrdata_mask[12],mux_wrdata_mask[8],mux_wrdata_mask[4],mux_wrdata_mask[0],mux_wrdata[224],mux_wrdata[192],mux_wrdata[160],mux_wrdata[128],mux_wrdata[96],mux_wrdata[64],mux_wrdata[32],mux_wrdata[0],mux_wrdata[225],mux_wrdata[193],mux_wrdata[161],mux_wrdata[129],mux_wrdata[97],mux_wrdata[65],mux_wrdata[33],mux_wrdata[1],mux_wrdata[226],mux_wrdata[194],mux_wrdata[162],mux_wrdata[130],mux_wrdata[98],mux_wrdata[66],mux_wrdata[34],mux_wrdata[2],mux_wrdata[227],mux_wrdata[195],mux_wrdata[163],mux_wrdata[131],mux_wrdata[99],mux_wrdata[67],mux_wrdata[35],mux_wrdata[3],mux_wrdata[228],mux_wrdata[196],mux_wrdata[164],mux_wrdata[132],mux_wrdata[100],mux_wrdata[68],mux_wrdata[36],mux_wrdata[4],mux_wrdata[229],mux_wrdata[197],mux_wrdata[165],mux_wrdata[133],mux_wrdata[101],mux_wrdata[69],mux_wrdata[37],mux_wrdata[5],mux_wrdata[230],mux_wrdata[198],mux_wrdata[166],mux_wrdata[134],mux_wrdata[102],mux_wrdata[70],mux_wrdata[38],mux_wrdata[6],mux_wrdata[231],mux_wrdata[199],mux_wrdata[167],mux_wrdata[135],mux_wrdata[103],mux_wrdata[71],mux_wrdata[39],mux_wrdata[7]}),\n .\\my_empty_reg[7]_1 ({mux_wrdata_mask[29],mux_wrdata_mask[25],mux_wrdata_mask[21],mux_wrdata_mask[17],mux_wrdata_mask[13],mux_wrdata_mask[9],mux_wrdata_mask[5],mux_wrdata_mask[1],mux_wrdata[232],mux_wrdata[200],mux_wrdata[168],mux_wrdata[136],mux_wrdata[104],mux_wrdata[72],mux_wrdata[40],mux_wrdata[8],mux_wrdata[233],mux_wrdata[201],mux_wrdata[169],mux_wrdata[137],mux_wrdata[105],mux_wrdata[73],mux_wrdata[41],mux_wrdata[9],mux_wrdata[234],mux_wrdata[202],mux_wrdata[170],mux_wrdata[138],mux_wrdata[106],mux_wrdata[74],mux_wrdata[42],mux_wrdata[10],mux_wrdata[235],mux_wrdata[203],mux_wrdata[171],mux_wrdata[139],mux_wrdata[107],mux_wrdata[75],mux_wrdata[43],mux_wrdata[11],mux_wrdata[236],mux_wrdata[204],mux_wrdata[172],mux_wrdata[140],mux_wrdata[108],mux_wrdata[76],mux_wrdata[44],mux_wrdata[12],mux_wrdata[237],mux_wrdata[205],mux_wrdata[173],mux_wrdata[141],mux_wrdata[109],mux_wrdata[77],mux_wrdata[45],mux_wrdata[13],mux_wrdata[238],mux_wrdata[206],mux_wrdata[174],mux_wrdata[142],mux_wrdata[110],mux_wrdata[78],mux_wrdata[46],mux_wrdata[14],mux_wrdata[239],mux_wrdata[207],mux_wrdata[175],mux_wrdata[143],mux_wrdata[111],mux_wrdata[79],mux_wrdata[47],mux_wrdata[15]}),\n .\\my_empty_reg[7]_10 (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ),\n .\\my_empty_reg[7]_11 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ),\n .\\my_empty_reg[7]_12 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ),\n .\\my_empty_reg[7]_13 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ),\n .\\my_empty_reg[7]_14 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ),\n .\\my_empty_reg[7]_15 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ),\n .\\my_empty_reg[7]_16 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ),\n .\\my_empty_reg[7]_17 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ),\n .\\my_empty_reg[7]_18 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 ),\n .\\my_empty_reg[7]_19 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ),\n .\\my_empty_reg[7]_2 ({mux_wrdata_mask[30],mux_wrdata_mask[26],mux_wrdata_mask[22],mux_wrdata_mask[18],mux_wrdata_mask[14],mux_wrdata_mask[10],mux_wrdata_mask[6],mux_wrdata_mask[2],mux_wrdata[240],mux_wrdata[208],mux_wrdata[176],mux_wrdata[144],mux_wrdata[112],mux_wrdata[80],mux_wrdata[48],mux_wrdata[16],mux_wrdata[241],mux_wrdata[209],mux_wrdata[177],mux_wrdata[145],mux_wrdata[113],mux_wrdata[81],mux_wrdata[49],mux_wrdata[17],mux_wrdata[242],mux_wrdata[210],mux_wrdata[178],mux_wrdata[146],mux_wrdata[114],mux_wrdata[82],mux_wrdata[50],mux_wrdata[18],mux_wrdata[243],mux_wrdata[211],mux_wrdata[179],mux_wrdata[147],mux_wrdata[115],mux_wrdata[83],mux_wrdata[51],mux_wrdata[19],mux_wrdata[244],mux_wrdata[212],mux_wrdata[180],mux_wrdata[148],mux_wrdata[116],mux_wrdata[84],mux_wrdata[52],mux_wrdata[20],mux_wrdata[245],mux_wrdata[213],mux_wrdata[181],mux_wrdata[149],mux_wrdata[117],mux_wrdata[85],mux_wrdata[53],mux_wrdata[21],mux_wrdata[246],mux_wrdata[214],mux_wrdata[182],mux_wrdata[150],mux_wrdata[118],mux_wrdata[86],mux_wrdata[54],mux_wrdata[22],mux_wrdata[247],mux_wrdata[215],mux_wrdata[183],mux_wrdata[151],mux_wrdata[119],mux_wrdata[87],mux_wrdata[55],mux_wrdata[23]}),\n .\\my_empty_reg[7]_20 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ),\n .\\my_empty_reg[7]_21 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ),\n .\\my_empty_reg[7]_22 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ),\n .\\my_empty_reg[7]_23 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ),\n .\\my_empty_reg[7]_24 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ),\n .\\my_empty_reg[7]_25 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ),\n .\\my_empty_reg[7]_26 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1 ),\n .\\my_empty_reg[7]_27 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8 ),\n .\\my_empty_reg[7]_28 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7 ),\n .\\my_empty_reg[7]_29 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ),\n .\\my_empty_reg[7]_3 ({mux_wrdata_mask[31],mux_wrdata_mask[27],mux_wrdata_mask[23],mux_wrdata_mask[19],mux_wrdata_mask[15],mux_wrdata_mask[11],mux_wrdata_mask[7],mux_wrdata_mask[3],mux_wrdata[248],mux_wrdata[216],mux_wrdata[184],mux_wrdata[152],mux_wrdata[120],mux_wrdata[88],mux_wrdata[56],mux_wrdata[24],mux_wrdata[249],mux_wrdata[217],mux_wrdata[185],mux_wrdata[153],mux_wrdata[121],mux_wrdata[89],mux_wrdata[57],mux_wrdata[25],mux_wrdata[250],mux_wrdata[218],mux_wrdata[186],mux_wrdata[154],mux_wrdata[122],mux_wrdata[90],mux_wrdata[58],mux_wrdata[26],mux_wrdata[251],mux_wrdata[219],mux_wrdata[187],mux_wrdata[155],mux_wrdata[123],mux_wrdata[91],mux_wrdata[59],mux_wrdata[27],mux_wrdata[252],mux_wrdata[220],mux_wrdata[188],mux_wrdata[156],mux_wrdata[124],mux_wrdata[92],mux_wrdata[60],mux_wrdata[28],mux_wrdata[253],mux_wrdata[221],mux_wrdata[189],mux_wrdata[157],mux_wrdata[125],mux_wrdata[93],mux_wrdata[61],mux_wrdata[29],mux_wrdata[254],mux_wrdata[222],mux_wrdata[190],mux_wrdata[158],mux_wrdata[126],mux_wrdata[94],mux_wrdata[62],mux_wrdata[30],mux_wrdata[255],mux_wrdata[223],mux_wrdata[191],mux_wrdata[159],mux_wrdata[127],mux_wrdata[95],mux_wrdata[63],mux_wrdata[31]}),\n .\\my_empty_reg[7]_30 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ),\n .\\my_empty_reg[7]_31 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ),\n .\\my_empty_reg[7]_32 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3 ),\n .\\my_empty_reg[7]_33 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2 ),\n .\\my_empty_reg[7]_34 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1 ),\n .\\my_empty_reg[7]_35 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7 ),\n .\\my_empty_reg[7]_36 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6 ),\n .\\my_empty_reg[7]_37 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5 ),\n .\\my_empty_reg[7]_38 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4 ),\n .\\my_empty_reg[7]_39 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3 ),\n .\\my_empty_reg[7]_4 (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 ),\n .\\my_empty_reg[7]_40 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2 ),\n .\\my_empty_reg[7]_41 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ),\n .\\my_empty_reg[7]_42 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0 ),\n .\\my_empty_reg[7]_5 (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ),\n .\\my_empty_reg[7]_6 (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ),\n .\\my_empty_reg[7]_7 (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ),\n .\\my_empty_reg[7]_8 (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ),\n .\\my_empty_reg[7]_9 (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ),\n .\\my_full_reg[3] (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ),\n .\\my_full_reg[3]_0 (phy_dout[3:2]),\n .out(u_ddr_calib_top_n_45),\n .p_0_out(\\u_ddr_phy_wrcal/p_0_out ),\n .p_81_in(p_81_in),\n .pd_out(pd_out),\n .\\periodic_rd_generation.periodic_rd_timer_r_reg[1] (\\periodic_rd_generation.periodic_rd_timer_r_reg[1] ),\n .\\phy_ctl_wd_i1_reg[24] ({calib_seq,p_1_out[22:17],p_1_out[2:0]}),\n .phy_dout({phy_dout[1:0],mux_address[57],mux_address[42],mux_address[27],mux_address[12],mux_address[56],mux_address[41],mux_address[26],mux_address[11],mux_address[55],mux_address[40],mux_address[25],mux_address[10],mux_address[54],mux_address[39],mux_address[24],mux_address[9],mux_address[53],mux_address[38],mux_address[23],mux_address[8],mux_address[52],mux_address[37],mux_address[22],mux_address[7],mux_address[51],mux_address[36],mux_address[21],mux_address[6],mux_address[50],mux_address[35],mux_address[20],mux_address[5]}),\n .phy_if_reset(phy_if_reset),\n .phy_rddata_en(phy_rddata_en),\n .phy_read_calib(phy_read_calib),\n .phy_write_calib(phy_write_calib),\n .pi_cnt_dec_reg(pi_cnt_dec_reg),\n .\\pi_counter_read_val_reg[5] (\\u_ddr_mc_phy/pi_counter_read_val_w[0]_1 ),\n .\\pi_dqs_found_lanes_r1_reg[0] (u_ddr_calib_top_n_447),\n .\\pi_dqs_found_lanes_r1_reg[0]_0 (u_ddr_calib_top_n_454),\n .\\pi_dqs_found_lanes_r1_reg[0]_1 (u_ddr_calib_top_n_455),\n .\\pi_dqs_found_lanes_r1_reg[0]_2 (u_ddr_calib_top_n_456),\n .\\pi_dqs_found_lanes_r1_reg[1] (u_ddr_calib_top_n_423),\n .\\pi_dqs_found_lanes_r1_reg[1]_0 (u_ddr_calib_top_n_430),\n .\\pi_dqs_found_lanes_r1_reg[1]_1 (u_ddr_calib_top_n_431),\n .\\pi_dqs_found_lanes_r1_reg[1]_2 (u_ddr_calib_top_n_432),\n .\\pi_dqs_found_lanes_r1_reg[1]_3 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_pi_counter_load_val ),\n .\\pi_dqs_found_lanes_r1_reg[2] (u_ddr_calib_top_n_413),\n .\\pi_dqs_found_lanes_r1_reg[2]_0 (u_ddr_calib_top_n_420),\n .\\pi_dqs_found_lanes_r1_reg[2]_1 (u_ddr_calib_top_n_421),\n .\\pi_dqs_found_lanes_r1_reg[2]_2 (u_ddr_calib_top_n_422),\n .\\pi_dqs_found_lanes_r1_reg[2]_3 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_counter_load_val ),\n .\\pi_dqs_found_lanes_r1_reg[3] (u_ddr_calib_top_n_403),\n .\\pi_dqs_found_lanes_r1_reg[3]_0 (u_ddr_calib_top_n_410),\n .\\pi_dqs_found_lanes_r1_reg[3]_1 (u_ddr_calib_top_n_411),\n .\\pi_dqs_found_lanes_r1_reg[3]_2 (u_ddr_calib_top_n_412),\n .\\pi_dqs_found_lanes_r1_reg[3]_3 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_counter_load_val ),\n .pi_en_stg2_f_timing_reg(pi_en_stg2_f_timing_reg),\n .\\pi_rst_stg1_cal_r_reg[0] (\\pi_rst_stg1_cal_r_reg[0] ),\n .po_cnt_dec_reg(po_cnt_dec_reg),\n .\\po_counter_read_val_reg[2] (u_ddr_mc_phy_wrapper_n_106),\n .\\po_counter_read_val_reg[5] ({u_ddr_mc_phy_wrapper_n_107,u_ddr_mc_phy_wrapper_n_108,u_ddr_mc_phy_wrapper_n_109,u_ddr_mc_phy_wrapper_n_110,u_ddr_mc_phy_wrapper_n_111,u_ddr_mc_phy_wrapper_n_112}),\n .\\po_counter_read_val_reg[8] (u_ddr_calib_top_n_385),\n .\\po_counter_read_val_reg[8]_0 (u_ddr_calib_top_n_386),\n .\\po_counter_read_val_reg[8]_1 (u_ddr_calib_top_n_387),\n .\\po_counter_read_val_reg[8]_10 (u_ddr_calib_top_n_396),\n .\\po_counter_read_val_reg[8]_11 (u_ddr_calib_top_n_397),\n .\\po_counter_read_val_reg[8]_12 (u_ddr_calib_top_n_399),\n .\\po_counter_read_val_reg[8]_13 (u_ddr_calib_top_n_400),\n .\\po_counter_read_val_reg[8]_14 (u_ddr_calib_top_n_401),\n .\\po_counter_read_val_reg[8]_15 (u_ddr_calib_top_n_402),\n .\\po_counter_read_val_reg[8]_16 (u_ddr_calib_top_n_406),\n .\\po_counter_read_val_reg[8]_17 (u_ddr_calib_top_n_407),\n .\\po_counter_read_val_reg[8]_18 (u_ddr_calib_top_n_408),\n .\\po_counter_read_val_reg[8]_19 (u_ddr_calib_top_n_416),\n .\\po_counter_read_val_reg[8]_2 (u_ddr_calib_top_n_388),\n .\\po_counter_read_val_reg[8]_20 (u_ddr_calib_top_n_417),\n .\\po_counter_read_val_reg[8]_21 (u_ddr_calib_top_n_418),\n .\\po_counter_read_val_reg[8]_22 (u_ddr_calib_top_n_426),\n .\\po_counter_read_val_reg[8]_23 (u_ddr_calib_top_n_427),\n .\\po_counter_read_val_reg[8]_24 (u_ddr_calib_top_n_428),\n .\\po_counter_read_val_reg[8]_25 (u_ddr_calib_top_n_450),\n .\\po_counter_read_val_reg[8]_26 (u_ddr_calib_top_n_451),\n .\\po_counter_read_val_reg[8]_27 (u_ddr_calib_top_n_452),\n .\\po_counter_read_val_reg[8]_28 (u_ddr_calib_top_n_457),\n .\\po_counter_read_val_reg[8]_29 (u_ddr_calib_top_n_458),\n .\\po_counter_read_val_reg[8]_3 (u_ddr_calib_top_n_389),\n .\\po_counter_read_val_reg[8]_30 ({\\u_ddr_mc_phy/po_counter_read_val_w[1]_2 [8:6],\\u_ddr_mc_phy/po_counter_read_val_w[1]_2 [3],\\u_ddr_mc_phy/po_counter_read_val_w[1]_2 [0]}),\n .\\po_counter_read_val_reg[8]_31 ({\\u_ddr_mc_phy/po_counter_read_val_w[0]_0 [8:6],\\u_ddr_mc_phy/po_counter_read_val_w[0]_0 [3],\\u_ddr_mc_phy/po_counter_read_val_w[0]_0 [0]}),\n .\\po_counter_read_val_reg[8]_4 (u_ddr_calib_top_n_390),\n .\\po_counter_read_val_reg[8]_5 (u_ddr_calib_top_n_391),\n .\\po_counter_read_val_reg[8]_6 (u_ddr_calib_top_n_392),\n .\\po_counter_read_val_reg[8]_7 (u_ddr_calib_top_n_393),\n .\\po_counter_read_val_reg[8]_8 (u_ddr_calib_top_n_394),\n .\\po_counter_read_val_reg[8]_9 (u_ddr_calib_top_n_395),\n .\\po_rdval_cnt_reg[8] ({calib_sel__0,calib_sel}),\n .\\po_stg2_wrcal_cnt_reg[1] (u_ddr_mc_phy_wrapper_n_1152),\n .\\po_stg2_wrcal_cnt_reg[1]_0 (u_ddr_mc_phy_wrapper_n_1156),\n .\\po_stg2_wrcal_cnt_reg[1]_1 (u_ddr_mc_phy_wrapper_n_1171),\n .\\po_stg2_wrcal_cnt_reg[1]_10 (u_ddr_mc_phy_wrapper_n_1136),\n .\\po_stg2_wrcal_cnt_reg[1]_11 (u_ddr_mc_phy_wrapper_n_1137),\n .\\po_stg2_wrcal_cnt_reg[1]_12 (u_ddr_mc_phy_wrapper_n_1138),\n .\\po_stg2_wrcal_cnt_reg[1]_13 (u_ddr_mc_phy_wrapper_n_1139),\n .\\po_stg2_wrcal_cnt_reg[1]_14 (u_ddr_mc_phy_wrapper_n_1140),\n .\\po_stg2_wrcal_cnt_reg[1]_15 (u_ddr_mc_phy_wrapper_n_1141),\n .\\po_stg2_wrcal_cnt_reg[1]_16 (u_ddr_mc_phy_wrapper_n_1142),\n .\\po_stg2_wrcal_cnt_reg[1]_17 (u_ddr_mc_phy_wrapper_n_1143),\n .\\po_stg2_wrcal_cnt_reg[1]_18 (u_ddr_mc_phy_wrapper_n_1144),\n .\\po_stg2_wrcal_cnt_reg[1]_19 (u_ddr_mc_phy_wrapper_n_1145),\n .\\po_stg2_wrcal_cnt_reg[1]_2 (u_ddr_mc_phy_wrapper_n_1175),\n .\\po_stg2_wrcal_cnt_reg[1]_20 (u_ddr_mc_phy_wrapper_n_1146),\n .\\po_stg2_wrcal_cnt_reg[1]_21 (u_ddr_mc_phy_wrapper_n_1147),\n .\\po_stg2_wrcal_cnt_reg[1]_22 (u_ddr_mc_phy_wrapper_n_1148),\n .\\po_stg2_wrcal_cnt_reg[1]_23 (u_ddr_mc_phy_wrapper_n_1149),\n .\\po_stg2_wrcal_cnt_reg[1]_24 (u_ddr_mc_phy_wrapper_n_1150),\n .\\po_stg2_wrcal_cnt_reg[1]_25 (u_ddr_mc_phy_wrapper_n_1151),\n .\\po_stg2_wrcal_cnt_reg[1]_26 (u_ddr_mc_phy_wrapper_n_1153),\n .\\po_stg2_wrcal_cnt_reg[1]_27 (u_ddr_mc_phy_wrapper_n_1154),\n .\\po_stg2_wrcal_cnt_reg[1]_28 (u_ddr_mc_phy_wrapper_n_1155),\n .\\po_stg2_wrcal_cnt_reg[1]_29 (u_ddr_mc_phy_wrapper_n_1157),\n .\\po_stg2_wrcal_cnt_reg[1]_3 (u_ddr_mc_phy_wrapper_n_1129),\n .\\po_stg2_wrcal_cnt_reg[1]_30 (u_ddr_mc_phy_wrapper_n_1158),\n .\\po_stg2_wrcal_cnt_reg[1]_31 (u_ddr_mc_phy_wrapper_n_1159),\n .\\po_stg2_wrcal_cnt_reg[1]_32 (u_ddr_mc_phy_wrapper_n_1160),\n .\\po_stg2_wrcal_cnt_reg[1]_33 (u_ddr_mc_phy_wrapper_n_1161),\n .\\po_stg2_wrcal_cnt_reg[1]_34 (u_ddr_mc_phy_wrapper_n_1162),\n .\\po_stg2_wrcal_cnt_reg[1]_35 (u_ddr_mc_phy_wrapper_n_1163),\n .\\po_stg2_wrcal_cnt_reg[1]_36 (u_ddr_mc_phy_wrapper_n_1164),\n .\\po_stg2_wrcal_cnt_reg[1]_37 (u_ddr_mc_phy_wrapper_n_1165),\n .\\po_stg2_wrcal_cnt_reg[1]_38 (u_ddr_mc_phy_wrapper_n_1166),\n .\\po_stg2_wrcal_cnt_reg[1]_39 (u_ddr_mc_phy_wrapper_n_1167),\n .\\po_stg2_wrcal_cnt_reg[1]_4 (u_ddr_mc_phy_wrapper_n_1130),\n .\\po_stg2_wrcal_cnt_reg[1]_40 (u_ddr_mc_phy_wrapper_n_1168),\n .\\po_stg2_wrcal_cnt_reg[1]_41 (u_ddr_mc_phy_wrapper_n_1169),\n .\\po_stg2_wrcal_cnt_reg[1]_42 (u_ddr_mc_phy_wrapper_n_1170),\n .\\po_stg2_wrcal_cnt_reg[1]_43 (u_ddr_mc_phy_wrapper_n_1172),\n .\\po_stg2_wrcal_cnt_reg[1]_44 (u_ddr_mc_phy_wrapper_n_1173),\n .\\po_stg2_wrcal_cnt_reg[1]_45 (u_ddr_mc_phy_wrapper_n_1174),\n .\\po_stg2_wrcal_cnt_reg[1]_46 (u_ddr_mc_phy_wrapper_n_1176),\n .\\po_stg2_wrcal_cnt_reg[1]_47 (u_ddr_mc_phy_wrapper_n_1177),\n .\\po_stg2_wrcal_cnt_reg[1]_48 (u_ddr_mc_phy_wrapper_n_1178),\n .\\po_stg2_wrcal_cnt_reg[1]_49 (u_ddr_mc_phy_wrapper_n_1179),\n .\\po_stg2_wrcal_cnt_reg[1]_5 (u_ddr_mc_phy_wrapper_n_1131),\n .\\po_stg2_wrcal_cnt_reg[1]_50 (u_ddr_mc_phy_wrapper_n_1180),\n .\\po_stg2_wrcal_cnt_reg[1]_51 (u_ddr_mc_phy_wrapper_n_1181),\n .\\po_stg2_wrcal_cnt_reg[1]_52 (u_ddr_mc_phy_wrapper_n_1182),\n .\\po_stg2_wrcal_cnt_reg[1]_53 (u_ddr_mc_phy_wrapper_n_1183),\n .\\po_stg2_wrcal_cnt_reg[1]_54 (u_ddr_mc_phy_wrapper_n_1184),\n .\\po_stg2_wrcal_cnt_reg[1]_55 (u_ddr_mc_phy_wrapper_n_1185),\n .\\po_stg2_wrcal_cnt_reg[1]_56 (u_ddr_mc_phy_wrapper_n_1186),\n .\\po_stg2_wrcal_cnt_reg[1]_57 (u_ddr_mc_phy_wrapper_n_1187),\n .\\po_stg2_wrcal_cnt_reg[1]_58 (u_ddr_mc_phy_wrapper_n_1188),\n .\\po_stg2_wrcal_cnt_reg[1]_59 (u_ddr_mc_phy_wrapper_n_1189),\n .\\po_stg2_wrcal_cnt_reg[1]_6 (u_ddr_mc_phy_wrapper_n_1132),\n .\\po_stg2_wrcal_cnt_reg[1]_60 (u_ddr_mc_phy_wrapper_n_1190),\n .\\po_stg2_wrcal_cnt_reg[1]_61 (u_ddr_mc_phy_wrapper_n_1191),\n .\\po_stg2_wrcal_cnt_reg[1]_7 (u_ddr_mc_phy_wrapper_n_1133),\n .\\po_stg2_wrcal_cnt_reg[1]_8 (u_ddr_mc_phy_wrapper_n_1134),\n .\\po_stg2_wrcal_cnt_reg[1]_9 (u_ddr_mc_phy_wrapper_n_1135),\n .poc_sample_pd(poc_sample_pd),\n .prbs_rdlvl_start_r_reg(u_ddr_calib_top_n_47),\n .psdone(psdone),\n .\\qcntr_r_reg[0] (\\qcntr_r_reg[0] ),\n .\\rd_mux_sel_r_reg[1] (u_ddr_mc_phy_wrapper_n_490),\n .\\rd_mux_sel_r_reg[1]_0 (u_ddr_mc_phy_wrapper_n_482),\n .\\rd_mux_sel_r_reg[1]_1 (u_ddr_mc_phy_wrapper_n_474),\n .\\rd_mux_sel_r_reg[1]_10 (u_ddr_mc_phy_wrapper_n_467),\n .\\rd_mux_sel_r_reg[1]_11 (u_ddr_mc_phy_wrapper_n_459),\n .\\rd_mux_sel_r_reg[1]_12 (u_ddr_mc_phy_wrapper_n_451),\n .\\rd_mux_sel_r_reg[1]_13 (u_ddr_mc_phy_wrapper_n_443),\n .\\rd_mux_sel_r_reg[1]_14 (u_ddr_mc_phy_wrapper_n_435),\n .\\rd_mux_sel_r_reg[1]_15 (u_ddr_mc_phy_wrapper_n_492),\n .\\rd_mux_sel_r_reg[1]_16 (u_ddr_mc_phy_wrapper_n_484),\n .\\rd_mux_sel_r_reg[1]_17 (u_ddr_mc_phy_wrapper_n_476),\n .\\rd_mux_sel_r_reg[1]_18 (u_ddr_mc_phy_wrapper_n_468),\n .\\rd_mux_sel_r_reg[1]_19 (u_ddr_mc_phy_wrapper_n_460),\n .\\rd_mux_sel_r_reg[1]_2 (u_ddr_mc_phy_wrapper_n_466),\n .\\rd_mux_sel_r_reg[1]_20 (u_ddr_mc_phy_wrapper_n_452),\n .\\rd_mux_sel_r_reg[1]_21 (u_ddr_mc_phy_wrapper_n_444),\n .\\rd_mux_sel_r_reg[1]_22 (u_ddr_mc_phy_wrapper_n_436),\n .\\rd_mux_sel_r_reg[1]_23 (u_ddr_mc_phy_wrapper_n_493),\n .\\rd_mux_sel_r_reg[1]_24 (u_ddr_mc_phy_wrapper_n_485),\n .\\rd_mux_sel_r_reg[1]_25 (u_ddr_mc_phy_wrapper_n_477),\n .\\rd_mux_sel_r_reg[1]_26 (u_ddr_mc_phy_wrapper_n_469),\n .\\rd_mux_sel_r_reg[1]_27 (u_ddr_mc_phy_wrapper_n_461),\n .\\rd_mux_sel_r_reg[1]_28 (u_ddr_mc_phy_wrapper_n_453),\n .\\rd_mux_sel_r_reg[1]_29 (u_ddr_mc_phy_wrapper_n_445),\n .\\rd_mux_sel_r_reg[1]_3 (u_ddr_mc_phy_wrapper_n_458),\n .\\rd_mux_sel_r_reg[1]_30 (u_ddr_mc_phy_wrapper_n_437),\n .\\rd_mux_sel_r_reg[1]_31 (u_ddr_mc_phy_wrapper_n_494),\n .\\rd_mux_sel_r_reg[1]_32 (u_ddr_mc_phy_wrapper_n_486),\n .\\rd_mux_sel_r_reg[1]_33 (u_ddr_mc_phy_wrapper_n_478),\n .\\rd_mux_sel_r_reg[1]_34 (u_ddr_mc_phy_wrapper_n_470),\n .\\rd_mux_sel_r_reg[1]_35 (u_ddr_mc_phy_wrapper_n_462),\n .\\rd_mux_sel_r_reg[1]_36 (u_ddr_mc_phy_wrapper_n_454),\n .\\rd_mux_sel_r_reg[1]_37 (u_ddr_mc_phy_wrapper_n_446),\n .\\rd_mux_sel_r_reg[1]_38 (u_ddr_mc_phy_wrapper_n_438),\n .\\rd_mux_sel_r_reg[1]_39 (u_ddr_mc_phy_wrapper_n_495),\n .\\rd_mux_sel_r_reg[1]_4 (u_ddr_mc_phy_wrapper_n_450),\n .\\rd_mux_sel_r_reg[1]_40 (u_ddr_mc_phy_wrapper_n_487),\n .\\rd_mux_sel_r_reg[1]_41 (u_ddr_mc_phy_wrapper_n_479),\n .\\rd_mux_sel_r_reg[1]_42 (u_ddr_mc_phy_wrapper_n_471),\n .\\rd_mux_sel_r_reg[1]_43 (u_ddr_mc_phy_wrapper_n_463),\n .\\rd_mux_sel_r_reg[1]_44 (u_ddr_mc_phy_wrapper_n_455),\n .\\rd_mux_sel_r_reg[1]_45 (u_ddr_mc_phy_wrapper_n_447),\n .\\rd_mux_sel_r_reg[1]_46 (u_ddr_mc_phy_wrapper_n_439),\n .\\rd_mux_sel_r_reg[1]_47 (u_ddr_mc_phy_wrapper_n_496),\n .\\rd_mux_sel_r_reg[1]_48 (u_ddr_mc_phy_wrapper_n_488),\n .\\rd_mux_sel_r_reg[1]_49 (u_ddr_mc_phy_wrapper_n_480),\n .\\rd_mux_sel_r_reg[1]_5 (u_ddr_mc_phy_wrapper_n_442),\n .\\rd_mux_sel_r_reg[1]_50 (u_ddr_mc_phy_wrapper_n_472),\n .\\rd_mux_sel_r_reg[1]_51 (u_ddr_mc_phy_wrapper_n_464),\n .\\rd_mux_sel_r_reg[1]_52 (u_ddr_mc_phy_wrapper_n_456),\n .\\rd_mux_sel_r_reg[1]_53 (u_ddr_mc_phy_wrapper_n_448),\n .\\rd_mux_sel_r_reg[1]_54 (u_ddr_mc_phy_wrapper_n_440),\n .\\rd_mux_sel_r_reg[1]_55 (u_ddr_mc_phy_wrapper_n_497),\n .\\rd_mux_sel_r_reg[1]_56 (u_ddr_mc_phy_wrapper_n_489),\n .\\rd_mux_sel_r_reg[1]_57 (u_ddr_mc_phy_wrapper_n_481),\n .\\rd_mux_sel_r_reg[1]_58 (u_ddr_mc_phy_wrapper_n_473),\n .\\rd_mux_sel_r_reg[1]_59 (u_ddr_mc_phy_wrapper_n_465),\n .\\rd_mux_sel_r_reg[1]_6 (u_ddr_mc_phy_wrapper_n_434),\n .\\rd_mux_sel_r_reg[1]_60 (u_ddr_mc_phy_wrapper_n_457),\n .\\rd_mux_sel_r_reg[1]_61 (u_ddr_mc_phy_wrapper_n_449),\n .\\rd_mux_sel_r_reg[1]_62 (u_ddr_mc_phy_wrapper_n_441),\n .\\rd_mux_sel_r_reg[1]_7 (u_ddr_mc_phy_wrapper_n_491),\n .\\rd_mux_sel_r_reg[1]_8 (u_ddr_mc_phy_wrapper_n_483),\n .\\rd_mux_sel_r_reg[1]_9 (u_ddr_mc_phy_wrapper_n_475),\n .\\rd_ptr_reg[3] ({\\rd_ptr_reg[3] [69:66],\\rd_ptr_reg[3] [61:58],\\rd_ptr_reg[3] [53:34],\\rd_ptr_reg[3] [29:26],\\rd_ptr_reg[3] [20:18],\\rd_ptr_reg[3] [12:10]}),\n .\\rd_ptr_reg[3]_0 ({\\rd_ptr_reg[3]_0 [25:22],\\rd_ptr_reg[3]_0 [17:14],\\rd_ptr_reg[3]_0 [11:8]}),\n .\\rd_ptr_reg[3]_1 ({\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [67:64],\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [59:56],\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [51:48],\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [43:40],\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [35:32],\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [27:24],\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [19:16],\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [11:8]}),\n .\\rd_ptr_reg[3]_2 ({u_ddr_mc_phy_wrapper_n_1033,u_ddr_mc_phy_wrapper_n_1034,u_ddr_mc_phy_wrapper_n_1035,u_ddr_mc_phy_wrapper_n_1036,u_ddr_mc_phy_wrapper_n_1037,u_ddr_mc_phy_wrapper_n_1038,u_ddr_mc_phy_wrapper_n_1039,u_ddr_mc_phy_wrapper_n_1040,u_ddr_mc_phy_wrapper_n_1041,u_ddr_mc_phy_wrapper_n_1042,u_ddr_mc_phy_wrapper_n_1043,u_ddr_mc_phy_wrapper_n_1044,u_ddr_mc_phy_wrapper_n_1045,u_ddr_mc_phy_wrapper_n_1046,u_ddr_mc_phy_wrapper_n_1047,u_ddr_mc_phy_wrapper_n_1048,u_ddr_mc_phy_wrapper_n_1049,u_ddr_mc_phy_wrapper_n_1050,u_ddr_mc_phy_wrapper_n_1051,u_ddr_mc_phy_wrapper_n_1052,u_ddr_mc_phy_wrapper_n_1053,u_ddr_mc_phy_wrapper_n_1054,u_ddr_mc_phy_wrapper_n_1055,u_ddr_mc_phy_wrapper_n_1056,u_ddr_mc_phy_wrapper_n_1057,u_ddr_mc_phy_wrapper_n_1058,u_ddr_mc_phy_wrapper_n_1059,u_ddr_mc_phy_wrapper_n_1060,u_ddr_mc_phy_wrapper_n_1061,u_ddr_mc_phy_wrapper_n_1062,u_ddr_mc_phy_wrapper_n_1063,u_ddr_mc_phy_wrapper_n_1064,u_ddr_mc_phy_wrapper_n_1065,u_ddr_mc_phy_wrapper_n_1066,u_ddr_mc_phy_wrapper_n_1067,u_ddr_mc_phy_wrapper_n_1068,u_ddr_mc_phy_wrapper_n_1069,u_ddr_mc_phy_wrapper_n_1070,u_ddr_mc_phy_wrapper_n_1071,u_ddr_mc_phy_wrapper_n_1072,u_ddr_mc_phy_wrapper_n_1073,u_ddr_mc_phy_wrapper_n_1074,u_ddr_mc_phy_wrapper_n_1075,u_ddr_mc_phy_wrapper_n_1076,u_ddr_mc_phy_wrapper_n_1077,u_ddr_mc_phy_wrapper_n_1078,u_ddr_mc_phy_wrapper_n_1079,u_ddr_mc_phy_wrapper_n_1080,u_ddr_mc_phy_wrapper_n_1081,u_ddr_mc_phy_wrapper_n_1082,u_ddr_mc_phy_wrapper_n_1083,u_ddr_mc_phy_wrapper_n_1084,u_ddr_mc_phy_wrapper_n_1085,u_ddr_mc_phy_wrapper_n_1086,u_ddr_mc_phy_wrapper_n_1087,u_ddr_mc_phy_wrapper_n_1088,u_ddr_mc_phy_wrapper_n_1089,u_ddr_mc_phy_wrapper_n_1090,u_ddr_mc_phy_wrapper_n_1091,u_ddr_mc_phy_wrapper_n_1092,u_ddr_mc_phy_wrapper_n_1093,u_ddr_mc_phy_wrapper_n_1094,u_ddr_mc_phy_wrapper_n_1095,u_ddr_mc_phy_wrapper_n_1096}),\n .\\rd_ptr_reg[3]_3 ({u_ddr_mc_phy_wrapper_n_967,u_ddr_mc_phy_wrapper_n_968,u_ddr_mc_phy_wrapper_n_969,u_ddr_mc_phy_wrapper_n_970,u_ddr_mc_phy_wrapper_n_971,u_ddr_mc_phy_wrapper_n_972,u_ddr_mc_phy_wrapper_n_973,u_ddr_mc_phy_wrapper_n_974,u_ddr_mc_phy_wrapper_n_975,u_ddr_mc_phy_wrapper_n_976,u_ddr_mc_phy_wrapper_n_977,u_ddr_mc_phy_wrapper_n_978,u_ddr_mc_phy_wrapper_n_979,u_ddr_mc_phy_wrapper_n_980,u_ddr_mc_phy_wrapper_n_981,u_ddr_mc_phy_wrapper_n_982,u_ddr_mc_phy_wrapper_n_983,u_ddr_mc_phy_wrapper_n_984,u_ddr_mc_phy_wrapper_n_985,u_ddr_mc_phy_wrapper_n_986,u_ddr_mc_phy_wrapper_n_987,u_ddr_mc_phy_wrapper_n_988,u_ddr_mc_phy_wrapper_n_989,u_ddr_mc_phy_wrapper_n_990,u_ddr_mc_phy_wrapper_n_991,u_ddr_mc_phy_wrapper_n_992,u_ddr_mc_phy_wrapper_n_993,u_ddr_mc_phy_wrapper_n_994,u_ddr_mc_phy_wrapper_n_995,u_ddr_mc_phy_wrapper_n_996,u_ddr_mc_phy_wrapper_n_997,u_ddr_mc_phy_wrapper_n_998,u_ddr_mc_phy_wrapper_n_999,u_ddr_mc_phy_wrapper_n_1000,u_ddr_mc_phy_wrapper_n_1001,u_ddr_mc_phy_wrapper_n_1002,u_ddr_mc_phy_wrapper_n_1003,u_ddr_mc_phy_wrapper_n_1004,u_ddr_mc_phy_wrapper_n_1005,u_ddr_mc_phy_wrapper_n_1006,u_ddr_mc_phy_wrapper_n_1007,u_ddr_mc_phy_wrapper_n_1008,u_ddr_mc_phy_wrapper_n_1009,u_ddr_mc_phy_wrapper_n_1010,u_ddr_mc_phy_wrapper_n_1011,u_ddr_mc_phy_wrapper_n_1012,u_ddr_mc_phy_wrapper_n_1013,u_ddr_mc_phy_wrapper_n_1014,u_ddr_mc_phy_wrapper_n_1015,u_ddr_mc_phy_wrapper_n_1016,u_ddr_mc_phy_wrapper_n_1017,u_ddr_mc_phy_wrapper_n_1018,u_ddr_mc_phy_wrapper_n_1019,u_ddr_mc_phy_wrapper_n_1020,u_ddr_mc_phy_wrapper_n_1021,u_ddr_mc_phy_wrapper_n_1022,u_ddr_mc_phy_wrapper_n_1023,u_ddr_mc_phy_wrapper_n_1024,u_ddr_mc_phy_wrapper_n_1025,u_ddr_mc_phy_wrapper_n_1026,u_ddr_mc_phy_wrapper_n_1027,u_ddr_mc_phy_wrapper_n_1028,u_ddr_mc_phy_wrapper_n_1029,u_ddr_mc_phy_wrapper_n_1030}),\n .\\rd_ptr_reg[3]_4 ({u_ddr_mc_phy_wrapper_n_901,u_ddr_mc_phy_wrapper_n_902,u_ddr_mc_phy_wrapper_n_903,u_ddr_mc_phy_wrapper_n_904,u_ddr_mc_phy_wrapper_n_905,u_ddr_mc_phy_wrapper_n_906,u_ddr_mc_phy_wrapper_n_907,u_ddr_mc_phy_wrapper_n_908,u_ddr_mc_phy_wrapper_n_909,u_ddr_mc_phy_wrapper_n_910,u_ddr_mc_phy_wrapper_n_911,u_ddr_mc_phy_wrapper_n_912,u_ddr_mc_phy_wrapper_n_913,u_ddr_mc_phy_wrapper_n_914,u_ddr_mc_phy_wrapper_n_915,u_ddr_mc_phy_wrapper_n_916,u_ddr_mc_phy_wrapper_n_917,u_ddr_mc_phy_wrapper_n_918,u_ddr_mc_phy_wrapper_n_919,u_ddr_mc_phy_wrapper_n_920,u_ddr_mc_phy_wrapper_n_921,u_ddr_mc_phy_wrapper_n_922,u_ddr_mc_phy_wrapper_n_923,u_ddr_mc_phy_wrapper_n_924,u_ddr_mc_phy_wrapper_n_925,u_ddr_mc_phy_wrapper_n_926,u_ddr_mc_phy_wrapper_n_927,u_ddr_mc_phy_wrapper_n_928,u_ddr_mc_phy_wrapper_n_929,u_ddr_mc_phy_wrapper_n_930,u_ddr_mc_phy_wrapper_n_931,u_ddr_mc_phy_wrapper_n_932,u_ddr_mc_phy_wrapper_n_933,u_ddr_mc_phy_wrapper_n_934,u_ddr_mc_phy_wrapper_n_935,u_ddr_mc_phy_wrapper_n_936,u_ddr_mc_phy_wrapper_n_937,u_ddr_mc_phy_wrapper_n_938,u_ddr_mc_phy_wrapper_n_939,u_ddr_mc_phy_wrapper_n_940,u_ddr_mc_phy_wrapper_n_941,u_ddr_mc_phy_wrapper_n_942,u_ddr_mc_phy_wrapper_n_943,u_ddr_mc_phy_wrapper_n_944,u_ddr_mc_phy_wrapper_n_945,u_ddr_mc_phy_wrapper_n_946,u_ddr_mc_phy_wrapper_n_947,u_ddr_mc_phy_wrapper_n_948,u_ddr_mc_phy_wrapper_n_949,u_ddr_mc_phy_wrapper_n_950,u_ddr_mc_phy_wrapper_n_951,u_ddr_mc_phy_wrapper_n_952,u_ddr_mc_phy_wrapper_n_953,u_ddr_mc_phy_wrapper_n_954,u_ddr_mc_phy_wrapper_n_955,u_ddr_mc_phy_wrapper_n_956,u_ddr_mc_phy_wrapper_n_957,u_ddr_mc_phy_wrapper_n_958,u_ddr_mc_phy_wrapper_n_959,u_ddr_mc_phy_wrapper_n_960,u_ddr_mc_phy_wrapper_n_961,u_ddr_mc_phy_wrapper_n_962,u_ddr_mc_phy_wrapper_n_963,u_ddr_mc_phy_wrapper_n_964}),\n .\\rd_ptr_reg[3]_5 ({u_ddr_mc_phy_wrapper_n_835,u_ddr_mc_phy_wrapper_n_836,u_ddr_mc_phy_wrapper_n_837,u_ddr_mc_phy_wrapper_n_838,u_ddr_mc_phy_wrapper_n_839,u_ddr_mc_phy_wrapper_n_840,u_ddr_mc_phy_wrapper_n_841,u_ddr_mc_phy_wrapper_n_842,u_ddr_mc_phy_wrapper_n_843,u_ddr_mc_phy_wrapper_n_844,u_ddr_mc_phy_wrapper_n_845,u_ddr_mc_phy_wrapper_n_846,u_ddr_mc_phy_wrapper_n_847,u_ddr_mc_phy_wrapper_n_848,u_ddr_mc_phy_wrapper_n_849,u_ddr_mc_phy_wrapper_n_850,u_ddr_mc_phy_wrapper_n_851,u_ddr_mc_phy_wrapper_n_852,u_ddr_mc_phy_wrapper_n_853,u_ddr_mc_phy_wrapper_n_854,u_ddr_mc_phy_wrapper_n_855,u_ddr_mc_phy_wrapper_n_856,u_ddr_mc_phy_wrapper_n_857,u_ddr_mc_phy_wrapper_n_858,u_ddr_mc_phy_wrapper_n_859,u_ddr_mc_phy_wrapper_n_860,u_ddr_mc_phy_wrapper_n_861,u_ddr_mc_phy_wrapper_n_862,u_ddr_mc_phy_wrapper_n_863,u_ddr_mc_phy_wrapper_n_864,u_ddr_mc_phy_wrapper_n_865,u_ddr_mc_phy_wrapper_n_866,u_ddr_mc_phy_wrapper_n_867,u_ddr_mc_phy_wrapper_n_868,u_ddr_mc_phy_wrapper_n_869,u_ddr_mc_phy_wrapper_n_870,u_ddr_mc_phy_wrapper_n_871,u_ddr_mc_phy_wrapper_n_872,u_ddr_mc_phy_wrapper_n_873,u_ddr_mc_phy_wrapper_n_874,u_ddr_mc_phy_wrapper_n_875,u_ddr_mc_phy_wrapper_n_876,u_ddr_mc_phy_wrapper_n_877,u_ddr_mc_phy_wrapper_n_878,u_ddr_mc_phy_wrapper_n_879,u_ddr_mc_phy_wrapper_n_880,u_ddr_mc_phy_wrapper_n_881,u_ddr_mc_phy_wrapper_n_882,u_ddr_mc_phy_wrapper_n_883,u_ddr_mc_phy_wrapper_n_884,u_ddr_mc_phy_wrapper_n_885,u_ddr_mc_phy_wrapper_n_886,u_ddr_mc_phy_wrapper_n_887,u_ddr_mc_phy_wrapper_n_888,u_ddr_mc_phy_wrapper_n_889,u_ddr_mc_phy_wrapper_n_890,u_ddr_mc_phy_wrapper_n_891,u_ddr_mc_phy_wrapper_n_892,u_ddr_mc_phy_wrapper_n_893,u_ddr_mc_phy_wrapper_n_894,u_ddr_mc_phy_wrapper_n_895,u_ddr_mc_phy_wrapper_n_896,u_ddr_mc_phy_wrapper_n_897,u_ddr_mc_phy_wrapper_n_898}),\n .\\rd_ptr_timing_reg[0] (u_ddr_calib_top_n_38),\n .\\rd_ptr_timing_reg[0]_0 (\\rd_ptr_timing_reg[0] ),\n .\\rd_ptr_timing_reg[0]_1 (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ),\n .\\rd_ptr_timing_reg[0]_2 (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ),\n .\\rd_ptr_timing_reg[0]_3 (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ),\n .\\rd_ptr_timing_reg[0]_4 (\\rd_ptr_timing_reg[0]_0 ),\n .\\rdlvl_dqs_tap_cnt_r_reg[0][3][0] ({u_ddr_calib_top_n_833,u_ddr_calib_top_n_834}),\n .\\row_cnt_victim_rotate.complex_row_cnt_reg[4] (\\row_cnt_victim_rotate.complex_row_cnt_reg[4] ),\n .rstdiv0_sync_r1_reg_rep(in0),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10),\n .rstdiv0_sync_r1_reg_rep__11(rstdiv0_sync_r1_reg_rep__11),\n .rstdiv0_sync_r1_reg_rep__12(rstdiv0_sync_r1_reg_rep__12),\n .rstdiv0_sync_r1_reg_rep__13(rstdiv0_sync_r1_reg_rep__13),\n .rstdiv0_sync_r1_reg_rep__14(rstdiv0_sync_r1_reg_rep__14),\n .rstdiv0_sync_r1_reg_rep__16(rstdiv0_sync_r1_reg_rep__16),\n .rstdiv0_sync_r1_reg_rep__17(rstdiv0_sync_r1_reg_rep__17),\n .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),\n .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22),\n .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23),\n .rstdiv0_sync_r1_reg_rep__23_0(rstdiv0_sync_r1_reg_rep__23_0),\n .rstdiv0_sync_r1_reg_rep__23_1(rstdiv0_sync_r1_reg_rep__23_1),\n .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),\n .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25),\n .rstdiv0_sync_r1_reg_rep__25_0(rstdiv0_sync_r1_reg_rep__25_0),\n .rstdiv0_sync_r1_reg_rep__25_1(rstdiv0_sync_r1_reg_rep__25_1),\n .rstdiv0_sync_r1_reg_rep__25_2(rstdiv0_sync_r1_reg_rep__25_2),\n .rstdiv0_sync_r1_reg_rep__4(rstdiv0_sync_r1_reg_rep__4),\n .rstdiv0_sync_r1_reg_rep__5(rstdiv0_sync_r1_reg_rep__5),\n .rstdiv0_sync_r1_reg_rep__6(rstdiv0_sync_r1_reg_rep__6),\n .rstdiv0_sync_r1_reg_rep__7(rstdiv0_sync_r1_reg_rep__7),\n .rstdiv0_sync_r1_reg_rep__8(rstdiv0_sync_r1_reg_rep__8),\n .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9),\n .samp_edge_cnt0_en_r(samp_edge_cnt0_en_r),\n .samp_edge_cnt0_en_r_reg(samp_edge_cnt0_en_r_reg),\n .\\samps_r_reg[9] (\\samps_r_reg[9] ),\n .\\sm_r_reg[0] (\\sm_r_reg[0] ),\n .\\sm_r_reg[0]_0 (\\sm_r_reg[0]_0 ),\n .\\stg2_tap_cnt_reg[0] (\\stg2_tap_cnt_reg[0] ),\n .stg3_dec2init_val_r_reg(stg3_dec2init_val_r_reg),\n .stg3_inc2init_val_r_reg(stg3_inc2init_val_r_reg),\n .\\stg3_r_reg[0] (\\stg3_r_reg[0] ),\n .tempmon_sample_en(tempmon_sample_en),\n .\\zero2fuzz_r_reg[0] (D));\n ddr3_ifmig_7series_v4_0_ddr_mc_phy_wrapper u_ddr_mc_phy_wrapper\n (.A(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl/A ),\n .CLK(CLK),\n .CLKB0(CLKB0),\n .CLKB0_7(CLKB0_7),\n .CLKB0_8(CLKB0_8),\n .CLKB0_9(CLKB0_9),\n .COUNTERLOADVAL({u_ddr_calib_top_n_441,u_ddr_calib_top_n_442,u_ddr_calib_top_n_443,u_ddr_calib_top_n_444,u_ddr_calib_top_n_445,u_ddr_calib_top_n_446}),\n .D({calib_seq,p_1_out[22:17],p_1_out[2:0]}),\n .D0(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0 ),\n .D1(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ),\n .D2(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ),\n .D3(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ),\n .D4(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ),\n .D5(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ),\n .D6(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ),\n .D7(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ),\n .D8(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ),\n .D9(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9 ),\n .DOA(DOA),\n .DOB(DOB),\n .DOC(DOC),\n .D_po_coarse_enable110_out(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_coarse_enable110_out ),\n .D_po_counter_read_en122_out(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_counter_read_en122_out ),\n .D_po_fine_enable107_out(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_enable107_out ),\n .D_po_fine_inc113_out(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_inc113_out ),\n .D_po_sel_fine_oclk_delay125_out(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_sel_fine_oclk_delay125_out ),\n .E(u_ddr_calib_top_n_448),\n .LD0(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0 ),\n .LD0_3(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/LD0 ),\n .LD0_4(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0 ),\n .LD0_5(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/LD0 ),\n .Q(Q[287:256]),\n .RST0(RST0),\n .SR(SR),\n .\\byte_r_reg[0] (u_ddr_mc_phy_wrapper_n_106),\n .\\byte_r_reg[0]_0 (u_ddr_calib_top_n_809),\n .\\byte_r_reg[1] (u_ddr_calib_top_n_810),\n .\\calib_sel_reg[0] (u_ddr_calib_top_n_390),\n .\\calib_sel_reg[0]_0 (u_ddr_calib_top_n_395),\n .\\calib_sel_reg[0]_1 (u_ddr_calib_top_n_396),\n .\\calib_sel_reg[0]_2 (u_ddr_calib_top_n_397),\n .\\calib_sel_reg[0]_3 (u_ddr_calib_top_n_447),\n .\\calib_sel_reg[0]_4 (u_ddr_calib_top_n_423),\n .\\calib_sel_reg[0]_5 (u_ddr_calib_top_n_403),\n .\\calib_sel_reg[0]_6 ({\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [26],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [23],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [20],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [17],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [14],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [11],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [8],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [5]}),\n .\\calib_sel_reg[0]_7 ({\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [26],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [23],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [20],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [17],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [14],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [11],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [8],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [5]}),\n .\\calib_sel_reg[1] (u_ddr_calib_top_n_386),\n .\\calib_sel_reg[1]_0 (u_ddr_calib_top_n_387),\n .\\calib_sel_reg[1]_1 (u_ddr_calib_top_n_388),\n .\\calib_sel_reg[1]_2 (u_ddr_calib_top_n_389),\n .\\calib_sel_reg[1]_3 (u_ddr_calib_top_n_391),\n .\\calib_sel_reg[1]_4 (u_ddr_calib_top_n_392),\n .\\calib_sel_reg[1]_5 (u_ddr_calib_top_n_393),\n .\\calib_sel_reg[1]_6 (u_ddr_calib_top_n_394),\n .\\calib_sel_reg[1]_7 (u_ddr_calib_top_n_413),\n .\\calib_sel_reg[1]_8 ({\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [26],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [23],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [20],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [17],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [14],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [11],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [8],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [5]}),\n .\\calib_sel_reg[3] ({calib_sel__0,calib_sel}),\n .\\calib_seq_reg[0] (\\calib_seq_reg[0] ),\n .\\calib_zero_inputs_reg[0] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_pi_counter_load_val ),\n .\\calib_zero_inputs_reg[0]_0 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_counter_load_val ),\n .\\calib_zero_inputs_reg[0]_1 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_counter_load_val ),\n .ck_po_stg2_f_en_reg(u_ddr_calib_top_n_451),\n .ck_po_stg2_f_en_reg_0(u_ddr_calib_top_n_427),\n .ck_po_stg2_f_en_reg_1(u_ddr_calib_top_n_417),\n .ck_po_stg2_f_en_reg_2(u_ddr_calib_top_n_407),\n .ck_po_stg2_f_indec_reg(u_ddr_calib_top_n_450),\n .ck_po_stg2_f_indec_reg_0(u_ddr_calib_top_n_426),\n .ck_po_stg2_f_indec_reg_1(u_ddr_calib_top_n_416),\n .ck_po_stg2_f_indec_reg_2(u_ddr_calib_top_n_406),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[5] (mux_data_offset_1),\n .\\data_bytes_r_reg[63] ({\\oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_data/data_bytes_r0 ,\\oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_data/data_bytes_ns }),\n .ddr3_addr(ddr3_addr),\n .ddr3_ba(ddr3_ba),\n .ddr3_cas_n(ddr3_cas_n),\n .ddr3_cke(ddr3_cke),\n .ddr3_cs_n(ddr3_cs_n),\n .ddr3_dm(ddr3_dm),\n .ddr3_dq(ddr3_dq),\n .ddr3_dqs_n(ddr3_dqs_n),\n .ddr3_dqs_p(ddr3_dqs_p),\n .ddr3_odt(ddr3_odt),\n .ddr3_ras_n(ddr3_ras_n),\n .ddr3_reset_n(ddr3_reset_n),\n .ddr3_we_n(ddr3_we_n),\n .ddr_ck_out(ddr_ck_out),\n .delay_done_r4_reg(u_ddr_calib_top_n_400),\n .delay_done_r4_reg_0(u_ddr_calib_top_n_401),\n .delay_done_r4_reg_1(u_ddr_calib_top_n_399),\n .delay_done_r4_reg_2(u_ddr_calib_top_n_402),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ),\n .fine_delay_mod({fine_delay_mod[26],fine_delay_mod[23],fine_delay_mod[20],fine_delay_mod[17],fine_delay_mod[14],fine_delay_mod[11],fine_delay_mod[8],fine_delay_mod[5],fine_delay_mod[2]}),\n .\\fine_delay_mod_reg[23]_0 ({u_ddr_calib_top_n_433,u_ddr_calib_top_n_434,u_ddr_calib_top_n_435,u_ddr_calib_top_n_436,u_ddr_calib_top_n_437,u_ddr_calib_top_n_438,u_ddr_calib_top_n_439,\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_fine_delay }),\n .\\fine_delay_mod_reg[26]_0 (u_ddr_mc_phy_wrapper_n_30),\n .fine_delay_sel_r(fine_delay_sel_r),\n .fine_delay_sel_reg(u_ddr_calib_top_n_50),\n .freq_refclk(freq_refclk),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[0] (u_ddr_calib_top_n_878),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 (u_ddr_calib_top_n_877),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[0]_1 (u_ddr_calib_top_n_876),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[0]_2 (u_ddr_calib_top_n_879),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[0]_3 (u_ddr_calib_top_n_881),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[0]_4 (u_ddr_calib_top_n_880),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[1] (byte_sel_cnt),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[2] (u_ddr_calib_top_n_464),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 (u_ddr_calib_top_n_461),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[2]_1 (u_ddr_calib_top_n_882),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[2]_2 (u_ddr_calib_top_n_875),\n .\\gen_byte_sel_div1.calib_in_common_reg (u_ddr_calib_top_n_457),\n .\\gen_byte_sel_div1.calib_in_common_reg_0 (u_ddr_calib_top_n_385),\n .\\gen_byte_sel_div1.calib_in_common_reg_1 (u_ddr_calib_top_n_458),\n .\\gen_byte_sel_div1.calib_in_common_reg_10 (u_ddr_calib_top_n_422),\n .\\gen_byte_sel_div1.calib_in_common_reg_11 (u_ddr_calib_top_n_419),\n .\\gen_byte_sel_div1.calib_in_common_reg_12 (u_ddr_calib_top_n_418),\n .\\gen_byte_sel_div1.calib_in_common_reg_13 (u_ddr_calib_top_n_415),\n .\\gen_byte_sel_div1.calib_in_common_reg_14 (u_ddr_calib_top_n_412),\n .\\gen_byte_sel_div1.calib_in_common_reg_15 (u_ddr_calib_top_n_409),\n .\\gen_byte_sel_div1.calib_in_common_reg_16 (u_ddr_calib_top_n_408),\n .\\gen_byte_sel_div1.calib_in_common_reg_17 (u_ddr_calib_top_n_405),\n .\\gen_byte_sel_div1.calib_in_common_reg_18 (u_ddr_calib_top_n_424),\n .\\gen_byte_sel_div1.calib_in_common_reg_19 (u_ddr_calib_top_n_414),\n .\\gen_byte_sel_div1.calib_in_common_reg_2 (u_ddr_calib_top_n_456),\n .\\gen_byte_sel_div1.calib_in_common_reg_20 (u_ddr_calib_top_n_404),\n .\\gen_byte_sel_div1.calib_in_common_reg_3 (u_ddr_calib_top_n_453),\n .\\gen_byte_sel_div1.calib_in_common_reg_4 (u_ddr_calib_top_n_452),\n .\\gen_byte_sel_div1.calib_in_common_reg_5 (u_ddr_calib_top_n_449),\n .\\gen_byte_sel_div1.calib_in_common_reg_6 (u_ddr_calib_top_n_432),\n .\\gen_byte_sel_div1.calib_in_common_reg_7 (u_ddr_calib_top_n_429),\n .\\gen_byte_sel_div1.calib_in_common_reg_8 (u_ddr_calib_top_n_428),\n .\\gen_byte_sel_div1.calib_in_common_reg_9 (u_ddr_calib_top_n_425),\n .\\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] (u_ddr_mc_phy_wrapper_n_814),\n .\\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (u_ddr_mc_phy_wrapper_n_491),\n .\\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] (u_ddr_mc_phy_wrapper_n_816),\n .\\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (u_ddr_mc_phy_wrapper_n_493),\n .\\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] (u_ddr_mc_phy_wrapper_n_818),\n .\\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (u_ddr_mc_phy_wrapper_n_495),\n .\\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] (u_ddr_mc_phy_wrapper_n_820),\n .\\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (u_ddr_mc_phy_wrapper_n_497),\n .\\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] (u_ddr_mc_phy_wrapper_n_813),\n .\\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (u_ddr_mc_phy_wrapper_n_490),\n .\\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] (u_ddr_mc_phy_wrapper_n_815),\n .\\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (u_ddr_mc_phy_wrapper_n_492),\n .\\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] (u_ddr_mc_phy_wrapper_n_817),\n .\\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (u_ddr_mc_phy_wrapper_n_494),\n .\\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] (u_ddr_mc_phy_wrapper_n_819),\n .\\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (u_ddr_mc_phy_wrapper_n_496),\n .\\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] (u_ddr_mc_phy_wrapper_n_806),\n .\\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (u_ddr_mc_phy_wrapper_n_483),\n .\\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] (u_ddr_mc_phy_wrapper_n_808),\n .\\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (u_ddr_mc_phy_wrapper_n_485),\n .\\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] (u_ddr_mc_phy_wrapper_n_810),\n .\\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (u_ddr_mc_phy_wrapper_n_487),\n .\\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] (u_ddr_mc_phy_wrapper_n_812),\n .\\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (u_ddr_mc_phy_wrapper_n_489),\n .\\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] (u_ddr_mc_phy_wrapper_n_805),\n .\\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (u_ddr_mc_phy_wrapper_n_482),\n .\\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] (u_ddr_mc_phy_wrapper_n_807),\n .\\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (u_ddr_mc_phy_wrapper_n_484),\n .\\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] (u_ddr_mc_phy_wrapper_n_809),\n .\\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (u_ddr_mc_phy_wrapper_n_486),\n .\\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] (u_ddr_mc_phy_wrapper_n_811),\n .\\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (u_ddr_mc_phy_wrapper_n_488),\n .\\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] (u_ddr_mc_phy_wrapper_n_798),\n .\\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (u_ddr_mc_phy_wrapper_n_475),\n .\\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] (u_ddr_mc_phy_wrapper_n_800),\n .\\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (u_ddr_mc_phy_wrapper_n_477),\n .\\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] (u_ddr_mc_phy_wrapper_n_802),\n .\\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (u_ddr_mc_phy_wrapper_n_479),\n .\\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] (u_ddr_mc_phy_wrapper_n_804),\n .\\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (u_ddr_mc_phy_wrapper_n_481),\n .\\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] (u_ddr_mc_phy_wrapper_n_797),\n .\\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (u_ddr_mc_phy_wrapper_n_474),\n .\\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] (u_ddr_mc_phy_wrapper_n_799),\n .\\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (u_ddr_mc_phy_wrapper_n_476),\n .\\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] (u_ddr_mc_phy_wrapper_n_801),\n .\\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (u_ddr_mc_phy_wrapper_n_478),\n .\\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] (u_ddr_mc_phy_wrapper_n_803),\n .\\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (u_ddr_mc_phy_wrapper_n_480),\n .\\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] (u_ddr_mc_phy_wrapper_n_790),\n .\\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (u_ddr_mc_phy_wrapper_n_467),\n .\\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] (u_ddr_mc_phy_wrapper_n_792),\n .\\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (u_ddr_mc_phy_wrapper_n_469),\n .\\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] (u_ddr_mc_phy_wrapper_n_794),\n .\\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (u_ddr_mc_phy_wrapper_n_471),\n .\\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] (u_ddr_mc_phy_wrapper_n_796),\n .\\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (u_ddr_mc_phy_wrapper_n_473),\n .\\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] (u_ddr_mc_phy_wrapper_n_789),\n .\\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (u_ddr_mc_phy_wrapper_n_466),\n .\\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] (u_ddr_mc_phy_wrapper_n_791),\n .\\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (u_ddr_mc_phy_wrapper_n_468),\n .\\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] (u_ddr_mc_phy_wrapper_n_793),\n .\\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (u_ddr_mc_phy_wrapper_n_470),\n .\\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] (u_ddr_mc_phy_wrapper_n_795),\n .\\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (u_ddr_mc_phy_wrapper_n_472),\n .\\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] (u_ddr_mc_phy_wrapper_n_782),\n .\\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (u_ddr_mc_phy_wrapper_n_459),\n .\\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] (u_ddr_mc_phy_wrapper_n_784),\n .\\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (u_ddr_mc_phy_wrapper_n_461),\n .\\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] (u_ddr_mc_phy_wrapper_n_786),\n .\\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (u_ddr_mc_phy_wrapper_n_463),\n .\\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] (u_ddr_mc_phy_wrapper_n_788),\n .\\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (u_ddr_mc_phy_wrapper_n_465),\n .\\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] (u_ddr_mc_phy_wrapper_n_781),\n .\\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (u_ddr_mc_phy_wrapper_n_458),\n .\\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] (u_ddr_mc_phy_wrapper_n_783),\n .\\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (u_ddr_mc_phy_wrapper_n_460),\n .\\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] (u_ddr_mc_phy_wrapper_n_785),\n .\\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (u_ddr_mc_phy_wrapper_n_462),\n .\\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] (u_ddr_mc_phy_wrapper_n_787),\n .\\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (u_ddr_mc_phy_wrapper_n_464),\n .\\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] (u_ddr_mc_phy_wrapper_n_774),\n .\\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (u_ddr_mc_phy_wrapper_n_451),\n .\\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] (u_ddr_mc_phy_wrapper_n_776),\n .\\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (u_ddr_mc_phy_wrapper_n_453),\n .\\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] (u_ddr_mc_phy_wrapper_n_778),\n .\\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (u_ddr_mc_phy_wrapper_n_455),\n .\\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] (u_ddr_mc_phy_wrapper_n_780),\n .\\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (u_ddr_mc_phy_wrapper_n_457),\n .\\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] (u_ddr_mc_phy_wrapper_n_773),\n .\\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (u_ddr_mc_phy_wrapper_n_450),\n .\\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] (u_ddr_mc_phy_wrapper_n_775),\n .\\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (u_ddr_mc_phy_wrapper_n_452),\n .\\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] (u_ddr_mc_phy_wrapper_n_777),\n .\\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (u_ddr_mc_phy_wrapper_n_454),\n .\\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] (u_ddr_mc_phy_wrapper_n_779),\n .\\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (u_ddr_mc_phy_wrapper_n_456),\n .\\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] (u_ddr_mc_phy_wrapper_n_766),\n .\\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (u_ddr_mc_phy_wrapper_n_443),\n .\\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] (u_ddr_mc_phy_wrapper_n_768),\n .\\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (u_ddr_mc_phy_wrapper_n_445),\n .\\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] (u_ddr_mc_phy_wrapper_n_770),\n .\\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (u_ddr_mc_phy_wrapper_n_447),\n .\\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] (u_ddr_mc_phy_wrapper_n_772),\n .\\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (u_ddr_mc_phy_wrapper_n_449),\n .\\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] (u_ddr_mc_phy_wrapper_n_765),\n .\\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (u_ddr_mc_phy_wrapper_n_442),\n .\\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] (u_ddr_mc_phy_wrapper_n_767),\n .\\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (u_ddr_mc_phy_wrapper_n_444),\n .\\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] (u_ddr_mc_phy_wrapper_n_769),\n .\\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (u_ddr_mc_phy_wrapper_n_446),\n .\\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] (u_ddr_mc_phy_wrapper_n_771),\n .\\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (u_ddr_mc_phy_wrapper_n_448),\n .\\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] (u_ddr_mc_phy_wrapper_n_758),\n .\\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (u_ddr_mc_phy_wrapper_n_435),\n .\\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] (u_ddr_mc_phy_wrapper_n_760),\n .\\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (u_ddr_mc_phy_wrapper_n_437),\n .\\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] (u_ddr_mc_phy_wrapper_n_762),\n .\\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (u_ddr_mc_phy_wrapper_n_439),\n .\\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] (u_ddr_mc_phy_wrapper_n_764),\n .\\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (u_ddr_mc_phy_wrapper_n_441),\n .\\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] (u_ddr_mc_phy_wrapper_n_757),\n .\\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (u_ddr_mc_phy_wrapper_n_434),\n .\\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] (u_ddr_mc_phy_wrapper_n_759),\n .\\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (u_ddr_mc_phy_wrapper_n_436),\n .\\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] (u_ddr_mc_phy_wrapper_n_761),\n .\\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (u_ddr_mc_phy_wrapper_n_438),\n .\\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] (u_ddr_mc_phy_wrapper_n_763),\n .\\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (u_ddr_mc_phy_wrapper_n_440),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (u_ddr_mc_phy_wrapper_n_1144),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (u_ddr_mc_phy_wrapper_n_1184),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (u_ddr_mc_phy_wrapper_n_1160),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (u_ddr_mc_phy_wrapper_n_1136),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (u_ddr_mc_phy_wrapper_n_1176),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (u_ddr_mc_phy_wrapper_n_1168),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (u_ddr_mc_phy_wrapper_n_1145),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (u_ddr_mc_phy_wrapper_n_1185),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (u_ddr_mc_phy_wrapper_n_1161),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (u_ddr_mc_phy_wrapper_n_1137),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (u_ddr_mc_phy_wrapper_n_1177),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (u_ddr_mc_phy_wrapper_n_1129),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (u_ddr_mc_phy_wrapper_n_1153),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (u_ddr_mc_phy_wrapper_n_1169),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (u_ddr_mc_phy_wrapper_n_1146),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (u_ddr_mc_phy_wrapper_n_1186),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (u_ddr_mc_phy_wrapper_n_1162),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (u_ddr_mc_phy_wrapper_n_1138),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (u_ddr_mc_phy_wrapper_n_1178),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (u_ddr_mc_phy_wrapper_n_1130),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (u_ddr_mc_phy_wrapper_n_1154),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (u_ddr_mc_phy_wrapper_n_1170),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (u_ddr_mc_phy_wrapper_n_1147),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (u_ddr_mc_phy_wrapper_n_1187),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (u_ddr_mc_phy_wrapper_n_1163),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (u_ddr_mc_phy_wrapper_n_1139),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (u_ddr_mc_phy_wrapper_n_1179),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (u_ddr_mc_phy_wrapper_n_1131),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (u_ddr_mc_phy_wrapper_n_1155),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (u_ddr_mc_phy_wrapper_n_1148),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (u_ddr_mc_phy_wrapper_n_1188),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (u_ddr_mc_phy_wrapper_n_1164),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (u_ddr_mc_phy_wrapper_n_1140),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (u_ddr_mc_phy_wrapper_n_1180),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (u_ddr_mc_phy_wrapper_n_1132),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (u_ddr_mc_phy_wrapper_n_1172),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (u_ddr_mc_phy_wrapper_n_1149),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (u_ddr_mc_phy_wrapper_n_1189),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (u_ddr_mc_phy_wrapper_n_1165),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (u_ddr_mc_phy_wrapper_n_1141),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (u_ddr_mc_phy_wrapper_n_1181),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (u_ddr_mc_phy_wrapper_n_1133),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (u_ddr_mc_phy_wrapper_n_1157),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (u_ddr_mc_phy_wrapper_n_1173),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (u_ddr_mc_phy_wrapper_n_1150),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (u_ddr_mc_phy_wrapper_n_1190),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (u_ddr_mc_phy_wrapper_n_1166),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (u_ddr_mc_phy_wrapper_n_1142),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (u_ddr_mc_phy_wrapper_n_1182),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (u_ddr_mc_phy_wrapper_n_1134),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (u_ddr_mc_phy_wrapper_n_1158),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (u_ddr_mc_phy_wrapper_n_1174),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (u_ddr_mc_phy_wrapper_n_1151),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (u_ddr_mc_phy_wrapper_n_1191),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (u_ddr_mc_phy_wrapper_n_1167),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (u_ddr_mc_phy_wrapper_n_1143),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (u_ddr_mc_phy_wrapper_n_1183),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (u_ddr_mc_phy_wrapper_n_1135),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (u_ddr_mc_phy_wrapper_n_1159),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ),\n .\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ),\n .\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ),\n .\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] (u_ddr_mc_phy_wrapper_n_1152),\n .\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] (u_ddr_mc_phy_wrapper_n_1171),\n .\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] (u_ddr_mc_phy_wrapper_n_1156),\n .\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] (u_ddr_mc_phy_wrapper_n_1175),\n .\\genblk9[0].fine_delay_incdec_pb_reg[0] (u_ddr_calib_top_n_855),\n .\\genblk9[1].fine_delay_incdec_pb_reg[1] (u_ddr_calib_top_n_856),\n .\\genblk9[2].fine_delay_incdec_pb_reg[2] (u_ddr_calib_top_n_857),\n .\\genblk9[3].fine_delay_incdec_pb_reg[3] (u_ddr_calib_top_n_858),\n .\\genblk9[4].fine_delay_incdec_pb_reg[4] (u_ddr_calib_top_n_840),\n .\\genblk9[4].fine_delay_incdec_pb_reg[4]_0 (u_ddr_calib_top_n_841),\n .\\genblk9[5].fine_delay_incdec_pb_reg[5] (u_ddr_calib_top_n_859),\n .\\genblk9[6].fine_delay_incdec_pb_reg[6] (u_ddr_calib_top_n_860),\n .\\genblk9[7].fine_delay_incdec_pb_reg[7] (u_ddr_calib_top_n_861),\n .idelay_inc(idelay_inc),\n .idelay_ld_rst(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst ),\n .idelay_ld_rst_0(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/idelay_ld_rst ),\n .idelay_ld_rst_1(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst ),\n .idelay_ld_rst_2(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/idelay_ld_rst ),\n .idle(idle),\n .in0(in0),\n .init_calib_complete_reg_rep(u_ddr_calib_top_n_37),\n .init_calib_complete_reg_rep__5(u_ddr_calib_top_n_38),\n .init_calib_complete_reg_rep__6(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ),\n .init_calib_complete_reg_rep__6_0(app_zq_r_reg),\n .mc_address({mc_address[36],mc_address[13]}),\n .mc_cas_n(mc_cas_n[1]),\n .mem_out({mem_out[17:11],mem_out[7:3]}),\n .mem_refclk(mem_refclk),\n .mmcm_locked(mmcm_locked),\n .mmcm_ps_clk(mmcm_ps_clk),\n .mux_cmd_wren(mux_cmd_wren),\n .mux_rd_valid_r_reg(u_ddr_mc_phy_wrapper_n_104),\n .mux_reset_n(mux_reset_n),\n .mux_wrdata(mux_wrdata),\n .mux_wrdata_en(mux_wrdata_en),\n .mux_wrdata_mask(mux_wrdata_mask),\n .\\my_empty_reg[1] (u_ddr_mc_phy_wrapper_n_60),\n .\\my_empty_reg[1]_0 (u_ddr_mc_phy_wrapper_n_61),\n .\\my_empty_reg[1]_1 (u_ddr_mc_phy_wrapper_n_63),\n .\\my_empty_reg[1]_2 (u_ddr_mc_phy_wrapper_n_64),\n .\\my_empty_reg[1]_3 (u_ddr_mc_phy_wrapper_n_65),\n .\\my_empty_reg[1]_4 (u_ddr_mc_phy_wrapper_n_66),\n .\\my_empty_reg[1]_5 (u_ddr_mc_phy_wrapper_n_67),\n .\\my_empty_reg[1]_6 (u_ddr_mc_phy_wrapper_n_102),\n .\\my_empty_reg[7] ({\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [67:64],\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [59:56],\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [51:48],\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [43:40],\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [35:32],\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [27:24],\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [19:16],\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [11:8]}),\n .\\my_empty_reg[7]_0 ({u_ddr_mc_phy_wrapper_n_835,u_ddr_mc_phy_wrapper_n_836,u_ddr_mc_phy_wrapper_n_837,u_ddr_mc_phy_wrapper_n_838,u_ddr_mc_phy_wrapper_n_839,u_ddr_mc_phy_wrapper_n_840,u_ddr_mc_phy_wrapper_n_841,u_ddr_mc_phy_wrapper_n_842,u_ddr_mc_phy_wrapper_n_843,u_ddr_mc_phy_wrapper_n_844,u_ddr_mc_phy_wrapper_n_845,u_ddr_mc_phy_wrapper_n_846,u_ddr_mc_phy_wrapper_n_847,u_ddr_mc_phy_wrapper_n_848,u_ddr_mc_phy_wrapper_n_849,u_ddr_mc_phy_wrapper_n_850,u_ddr_mc_phy_wrapper_n_851,u_ddr_mc_phy_wrapper_n_852,u_ddr_mc_phy_wrapper_n_853,u_ddr_mc_phy_wrapper_n_854,u_ddr_mc_phy_wrapper_n_855,u_ddr_mc_phy_wrapper_n_856,u_ddr_mc_phy_wrapper_n_857,u_ddr_mc_phy_wrapper_n_858,u_ddr_mc_phy_wrapper_n_859,u_ddr_mc_phy_wrapper_n_860,u_ddr_mc_phy_wrapper_n_861,u_ddr_mc_phy_wrapper_n_862,u_ddr_mc_phy_wrapper_n_863,u_ddr_mc_phy_wrapper_n_864,u_ddr_mc_phy_wrapper_n_865,u_ddr_mc_phy_wrapper_n_866,u_ddr_mc_phy_wrapper_n_867,u_ddr_mc_phy_wrapper_n_868,u_ddr_mc_phy_wrapper_n_869,u_ddr_mc_phy_wrapper_n_870,u_ddr_mc_phy_wrapper_n_871,u_ddr_mc_phy_wrapper_n_872,u_ddr_mc_phy_wrapper_n_873,u_ddr_mc_phy_wrapper_n_874,u_ddr_mc_phy_wrapper_n_875,u_ddr_mc_phy_wrapper_n_876,u_ddr_mc_phy_wrapper_n_877,u_ddr_mc_phy_wrapper_n_878,u_ddr_mc_phy_wrapper_n_879,u_ddr_mc_phy_wrapper_n_880,u_ddr_mc_phy_wrapper_n_881,u_ddr_mc_phy_wrapper_n_882,u_ddr_mc_phy_wrapper_n_883,u_ddr_mc_phy_wrapper_n_884,u_ddr_mc_phy_wrapper_n_885,u_ddr_mc_phy_wrapper_n_886,u_ddr_mc_phy_wrapper_n_887,u_ddr_mc_phy_wrapper_n_888,u_ddr_mc_phy_wrapper_n_889,u_ddr_mc_phy_wrapper_n_890,u_ddr_mc_phy_wrapper_n_891,u_ddr_mc_phy_wrapper_n_892,u_ddr_mc_phy_wrapper_n_893,u_ddr_mc_phy_wrapper_n_894,u_ddr_mc_phy_wrapper_n_895,u_ddr_mc_phy_wrapper_n_896,u_ddr_mc_phy_wrapper_n_897,u_ddr_mc_phy_wrapper_n_898}),\n .\\my_empty_reg[7]_1 ({u_ddr_mc_phy_wrapper_n_901,u_ddr_mc_phy_wrapper_n_902,u_ddr_mc_phy_wrapper_n_903,u_ddr_mc_phy_wrapper_n_904,u_ddr_mc_phy_wrapper_n_905,u_ddr_mc_phy_wrapper_n_906,u_ddr_mc_phy_wrapper_n_907,u_ddr_mc_phy_wrapper_n_908,u_ddr_mc_phy_wrapper_n_909,u_ddr_mc_phy_wrapper_n_910,u_ddr_mc_phy_wrapper_n_911,u_ddr_mc_phy_wrapper_n_912,u_ddr_mc_phy_wrapper_n_913,u_ddr_mc_phy_wrapper_n_914,u_ddr_mc_phy_wrapper_n_915,u_ddr_mc_phy_wrapper_n_916,u_ddr_mc_phy_wrapper_n_917,u_ddr_mc_phy_wrapper_n_918,u_ddr_mc_phy_wrapper_n_919,u_ddr_mc_phy_wrapper_n_920,u_ddr_mc_phy_wrapper_n_921,u_ddr_mc_phy_wrapper_n_922,u_ddr_mc_phy_wrapper_n_923,u_ddr_mc_phy_wrapper_n_924,u_ddr_mc_phy_wrapper_n_925,u_ddr_mc_phy_wrapper_n_926,u_ddr_mc_phy_wrapper_n_927,u_ddr_mc_phy_wrapper_n_928,u_ddr_mc_phy_wrapper_n_929,u_ddr_mc_phy_wrapper_n_930,u_ddr_mc_phy_wrapper_n_931,u_ddr_mc_phy_wrapper_n_932,u_ddr_mc_phy_wrapper_n_933,u_ddr_mc_phy_wrapper_n_934,u_ddr_mc_phy_wrapper_n_935,u_ddr_mc_phy_wrapper_n_936,u_ddr_mc_phy_wrapper_n_937,u_ddr_mc_phy_wrapper_n_938,u_ddr_mc_phy_wrapper_n_939,u_ddr_mc_phy_wrapper_n_940,u_ddr_mc_phy_wrapper_n_941,u_ddr_mc_phy_wrapper_n_942,u_ddr_mc_phy_wrapper_n_943,u_ddr_mc_phy_wrapper_n_944,u_ddr_mc_phy_wrapper_n_945,u_ddr_mc_phy_wrapper_n_946,u_ddr_mc_phy_wrapper_n_947,u_ddr_mc_phy_wrapper_n_948,u_ddr_mc_phy_wrapper_n_949,u_ddr_mc_phy_wrapper_n_950,u_ddr_mc_phy_wrapper_n_951,u_ddr_mc_phy_wrapper_n_952,u_ddr_mc_phy_wrapper_n_953,u_ddr_mc_phy_wrapper_n_954,u_ddr_mc_phy_wrapper_n_955,u_ddr_mc_phy_wrapper_n_956,u_ddr_mc_phy_wrapper_n_957,u_ddr_mc_phy_wrapper_n_958,u_ddr_mc_phy_wrapper_n_959,u_ddr_mc_phy_wrapper_n_960,u_ddr_mc_phy_wrapper_n_961,u_ddr_mc_phy_wrapper_n_962,u_ddr_mc_phy_wrapper_n_963,u_ddr_mc_phy_wrapper_n_964}),\n .\\my_empty_reg[7]_2 ({u_ddr_mc_phy_wrapper_n_967,u_ddr_mc_phy_wrapper_n_968,u_ddr_mc_phy_wrapper_n_969,u_ddr_mc_phy_wrapper_n_970,u_ddr_mc_phy_wrapper_n_971,u_ddr_mc_phy_wrapper_n_972,u_ddr_mc_phy_wrapper_n_973,u_ddr_mc_phy_wrapper_n_974,u_ddr_mc_phy_wrapper_n_975,u_ddr_mc_phy_wrapper_n_976,u_ddr_mc_phy_wrapper_n_977,u_ddr_mc_phy_wrapper_n_978,u_ddr_mc_phy_wrapper_n_979,u_ddr_mc_phy_wrapper_n_980,u_ddr_mc_phy_wrapper_n_981,u_ddr_mc_phy_wrapper_n_982,u_ddr_mc_phy_wrapper_n_983,u_ddr_mc_phy_wrapper_n_984,u_ddr_mc_phy_wrapper_n_985,u_ddr_mc_phy_wrapper_n_986,u_ddr_mc_phy_wrapper_n_987,u_ddr_mc_phy_wrapper_n_988,u_ddr_mc_phy_wrapper_n_989,u_ddr_mc_phy_wrapper_n_990,u_ddr_mc_phy_wrapper_n_991,u_ddr_mc_phy_wrapper_n_992,u_ddr_mc_phy_wrapper_n_993,u_ddr_mc_phy_wrapper_n_994,u_ddr_mc_phy_wrapper_n_995,u_ddr_mc_phy_wrapper_n_996,u_ddr_mc_phy_wrapper_n_997,u_ddr_mc_phy_wrapper_n_998,u_ddr_mc_phy_wrapper_n_999,u_ddr_mc_phy_wrapper_n_1000,u_ddr_mc_phy_wrapper_n_1001,u_ddr_mc_phy_wrapper_n_1002,u_ddr_mc_phy_wrapper_n_1003,u_ddr_mc_phy_wrapper_n_1004,u_ddr_mc_phy_wrapper_n_1005,u_ddr_mc_phy_wrapper_n_1006,u_ddr_mc_phy_wrapper_n_1007,u_ddr_mc_phy_wrapper_n_1008,u_ddr_mc_phy_wrapper_n_1009,u_ddr_mc_phy_wrapper_n_1010,u_ddr_mc_phy_wrapper_n_1011,u_ddr_mc_phy_wrapper_n_1012,u_ddr_mc_phy_wrapper_n_1013,u_ddr_mc_phy_wrapper_n_1014,u_ddr_mc_phy_wrapper_n_1015,u_ddr_mc_phy_wrapper_n_1016,u_ddr_mc_phy_wrapper_n_1017,u_ddr_mc_phy_wrapper_n_1018,u_ddr_mc_phy_wrapper_n_1019,u_ddr_mc_phy_wrapper_n_1020,u_ddr_mc_phy_wrapper_n_1021,u_ddr_mc_phy_wrapper_n_1022,u_ddr_mc_phy_wrapper_n_1023,u_ddr_mc_phy_wrapper_n_1024,u_ddr_mc_phy_wrapper_n_1025,u_ddr_mc_phy_wrapper_n_1026,u_ddr_mc_phy_wrapper_n_1027,u_ddr_mc_phy_wrapper_n_1028,u_ddr_mc_phy_wrapper_n_1029,u_ddr_mc_phy_wrapper_n_1030}),\n .\\my_empty_reg[7]_3 ({u_ddr_mc_phy_wrapper_n_1033,u_ddr_mc_phy_wrapper_n_1034,u_ddr_mc_phy_wrapper_n_1035,u_ddr_mc_phy_wrapper_n_1036,u_ddr_mc_phy_wrapper_n_1037,u_ddr_mc_phy_wrapper_n_1038,u_ddr_mc_phy_wrapper_n_1039,u_ddr_mc_phy_wrapper_n_1040,u_ddr_mc_phy_wrapper_n_1041,u_ddr_mc_phy_wrapper_n_1042,u_ddr_mc_phy_wrapper_n_1043,u_ddr_mc_phy_wrapper_n_1044,u_ddr_mc_phy_wrapper_n_1045,u_ddr_mc_phy_wrapper_n_1046,u_ddr_mc_phy_wrapper_n_1047,u_ddr_mc_phy_wrapper_n_1048,u_ddr_mc_phy_wrapper_n_1049,u_ddr_mc_phy_wrapper_n_1050,u_ddr_mc_phy_wrapper_n_1051,u_ddr_mc_phy_wrapper_n_1052,u_ddr_mc_phy_wrapper_n_1053,u_ddr_mc_phy_wrapper_n_1054,u_ddr_mc_phy_wrapper_n_1055,u_ddr_mc_phy_wrapper_n_1056,u_ddr_mc_phy_wrapper_n_1057,u_ddr_mc_phy_wrapper_n_1058,u_ddr_mc_phy_wrapper_n_1059,u_ddr_mc_phy_wrapper_n_1060,u_ddr_mc_phy_wrapper_n_1061,u_ddr_mc_phy_wrapper_n_1062,u_ddr_mc_phy_wrapper_n_1063,u_ddr_mc_phy_wrapper_n_1064,u_ddr_mc_phy_wrapper_n_1065,u_ddr_mc_phy_wrapper_n_1066,u_ddr_mc_phy_wrapper_n_1067,u_ddr_mc_phy_wrapper_n_1068,u_ddr_mc_phy_wrapper_n_1069,u_ddr_mc_phy_wrapper_n_1070,u_ddr_mc_phy_wrapper_n_1071,u_ddr_mc_phy_wrapper_n_1072,u_ddr_mc_phy_wrapper_n_1073,u_ddr_mc_phy_wrapper_n_1074,u_ddr_mc_phy_wrapper_n_1075,u_ddr_mc_phy_wrapper_n_1076,u_ddr_mc_phy_wrapper_n_1077,u_ddr_mc_phy_wrapper_n_1078,u_ddr_mc_phy_wrapper_n_1079,u_ddr_mc_phy_wrapper_n_1080,u_ddr_mc_phy_wrapper_n_1081,u_ddr_mc_phy_wrapper_n_1082,u_ddr_mc_phy_wrapper_n_1083,u_ddr_mc_phy_wrapper_n_1084,u_ddr_mc_phy_wrapper_n_1085,u_ddr_mc_phy_wrapper_n_1086,u_ddr_mc_phy_wrapper_n_1087,u_ddr_mc_phy_wrapper_n_1088,u_ddr_mc_phy_wrapper_n_1089,u_ddr_mc_phy_wrapper_n_1090,u_ddr_mc_phy_wrapper_n_1091,u_ddr_mc_phy_wrapper_n_1092,u_ddr_mc_phy_wrapper_n_1093,u_ddr_mc_phy_wrapper_n_1094,u_ddr_mc_phy_wrapper_n_1095,u_ddr_mc_phy_wrapper_n_1096}),\n .\\not_strict_mode.app_rd_data_reg[0] (\\not_strict_mode.app_rd_data_reg[0] ),\n .\\not_strict_mode.app_rd_data_reg[100] (\\not_strict_mode.app_rd_data_reg[100] ),\n .\\not_strict_mode.app_rd_data_reg[101] (\\not_strict_mode.app_rd_data_reg[101] ),\n .\\not_strict_mode.app_rd_data_reg[102] (\\not_strict_mode.app_rd_data_reg[102] ),\n .\\not_strict_mode.app_rd_data_reg[103] (\\not_strict_mode.app_rd_data_reg[103] ),\n .\\not_strict_mode.app_rd_data_reg[104] (\\not_strict_mode.app_rd_data_reg[104] ),\n .\\not_strict_mode.app_rd_data_reg[105] (\\not_strict_mode.app_rd_data_reg[105] ),\n .\\not_strict_mode.app_rd_data_reg[106] (\\not_strict_mode.app_rd_data_reg[106] ),\n .\\not_strict_mode.app_rd_data_reg[107] (\\not_strict_mode.app_rd_data_reg[107] ),\n .\\not_strict_mode.app_rd_data_reg[108] (\\not_strict_mode.app_rd_data_reg[108] ),\n .\\not_strict_mode.app_rd_data_reg[109] (\\not_strict_mode.app_rd_data_reg[109] ),\n .\\not_strict_mode.app_rd_data_reg[10] (\\not_strict_mode.app_rd_data_reg[10] ),\n .\\not_strict_mode.app_rd_data_reg[110] (\\not_strict_mode.app_rd_data_reg[110] ),\n .\\not_strict_mode.app_rd_data_reg[111] (\\not_strict_mode.app_rd_data_reg[111] ),\n .\\not_strict_mode.app_rd_data_reg[112] (\\not_strict_mode.app_rd_data_reg[112] ),\n .\\not_strict_mode.app_rd_data_reg[113] (\\not_strict_mode.app_rd_data_reg[113] ),\n .\\not_strict_mode.app_rd_data_reg[114] (\\not_strict_mode.app_rd_data_reg[114] ),\n .\\not_strict_mode.app_rd_data_reg[115] (\\not_strict_mode.app_rd_data_reg[115] ),\n .\\not_strict_mode.app_rd_data_reg[116] (\\not_strict_mode.app_rd_data_reg[116] ),\n .\\not_strict_mode.app_rd_data_reg[117] (\\not_strict_mode.app_rd_data_reg[117] ),\n .\\not_strict_mode.app_rd_data_reg[118] (\\not_strict_mode.app_rd_data_reg[118] ),\n .\\not_strict_mode.app_rd_data_reg[119] (\\not_strict_mode.app_rd_data_reg[119] ),\n .\\not_strict_mode.app_rd_data_reg[11] (\\not_strict_mode.app_rd_data_reg[11] ),\n .\\not_strict_mode.app_rd_data_reg[120] (\\not_strict_mode.app_rd_data_reg[120] ),\n .\\not_strict_mode.app_rd_data_reg[121] (\\not_strict_mode.app_rd_data_reg[121] ),\n .\\not_strict_mode.app_rd_data_reg[122] (\\not_strict_mode.app_rd_data_reg[122] ),\n .\\not_strict_mode.app_rd_data_reg[123] (\\not_strict_mode.app_rd_data_reg[123] ),\n .\\not_strict_mode.app_rd_data_reg[124] (\\not_strict_mode.app_rd_data_reg[124] ),\n .\\not_strict_mode.app_rd_data_reg[125] (\\not_strict_mode.app_rd_data_reg[125] ),\n .\\not_strict_mode.app_rd_data_reg[126] (\\not_strict_mode.app_rd_data_reg[126] ),\n .\\not_strict_mode.app_rd_data_reg[127] (\\not_strict_mode.app_rd_data_reg[127] ),\n .\\not_strict_mode.app_rd_data_reg[128] (\\not_strict_mode.app_rd_data_reg[128] ),\n .\\not_strict_mode.app_rd_data_reg[129] (\\not_strict_mode.app_rd_data_reg[129] ),\n .\\not_strict_mode.app_rd_data_reg[12] (\\not_strict_mode.app_rd_data_reg[12] ),\n .\\not_strict_mode.app_rd_data_reg[130] (\\not_strict_mode.app_rd_data_reg[130] ),\n .\\not_strict_mode.app_rd_data_reg[131] (\\not_strict_mode.app_rd_data_reg[131] ),\n .\\not_strict_mode.app_rd_data_reg[132] (\\not_strict_mode.app_rd_data_reg[132] ),\n .\\not_strict_mode.app_rd_data_reg[133] (\\not_strict_mode.app_rd_data_reg[133] ),\n .\\not_strict_mode.app_rd_data_reg[134] (\\not_strict_mode.app_rd_data_reg[134] ),\n .\\not_strict_mode.app_rd_data_reg[135] (\\not_strict_mode.app_rd_data_reg[135] ),\n .\\not_strict_mode.app_rd_data_reg[136] (\\not_strict_mode.app_rd_data_reg[136] ),\n .\\not_strict_mode.app_rd_data_reg[137] (\\not_strict_mode.app_rd_data_reg[137] ),\n .\\not_strict_mode.app_rd_data_reg[138] (\\not_strict_mode.app_rd_data_reg[138] ),\n .\\not_strict_mode.app_rd_data_reg[139] (\\not_strict_mode.app_rd_data_reg[139] ),\n .\\not_strict_mode.app_rd_data_reg[13] (\\not_strict_mode.app_rd_data_reg[13] ),\n .\\not_strict_mode.app_rd_data_reg[140] (\\not_strict_mode.app_rd_data_reg[140] ),\n .\\not_strict_mode.app_rd_data_reg[141] (\\not_strict_mode.app_rd_data_reg[141] ),\n .\\not_strict_mode.app_rd_data_reg[142] (\\not_strict_mode.app_rd_data_reg[142] ),\n .\\not_strict_mode.app_rd_data_reg[143] (\\not_strict_mode.app_rd_data_reg[143] ),\n .\\not_strict_mode.app_rd_data_reg[144] (\\not_strict_mode.app_rd_data_reg[144] ),\n .\\not_strict_mode.app_rd_data_reg[145] (\\not_strict_mode.app_rd_data_reg[145] ),\n .\\not_strict_mode.app_rd_data_reg[146] (\\not_strict_mode.app_rd_data_reg[146] ),\n .\\not_strict_mode.app_rd_data_reg[147] (\\not_strict_mode.app_rd_data_reg[147] ),\n .\\not_strict_mode.app_rd_data_reg[148] (\\not_strict_mode.app_rd_data_reg[148] ),\n .\\not_strict_mode.app_rd_data_reg[149] (\\not_strict_mode.app_rd_data_reg[149] ),\n .\\not_strict_mode.app_rd_data_reg[14] (\\not_strict_mode.app_rd_data_reg[14] ),\n .\\not_strict_mode.app_rd_data_reg[150] (\\not_strict_mode.app_rd_data_reg[150] ),\n .\\not_strict_mode.app_rd_data_reg[151] (\\not_strict_mode.app_rd_data_reg[151] ),\n .\\not_strict_mode.app_rd_data_reg[152] (\\not_strict_mode.app_rd_data_reg[152] ),\n .\\not_strict_mode.app_rd_data_reg[153] (\\not_strict_mode.app_rd_data_reg[153] ),\n .\\not_strict_mode.app_rd_data_reg[154] (\\not_strict_mode.app_rd_data_reg[154] ),\n .\\not_strict_mode.app_rd_data_reg[155] (\\not_strict_mode.app_rd_data_reg[155] ),\n .\\not_strict_mode.app_rd_data_reg[156] (\\not_strict_mode.app_rd_data_reg[156] ),\n .\\not_strict_mode.app_rd_data_reg[157] (\\not_strict_mode.app_rd_data_reg[157] ),\n .\\not_strict_mode.app_rd_data_reg[158] (\\not_strict_mode.app_rd_data_reg[158] ),\n .\\not_strict_mode.app_rd_data_reg[159] (\\not_strict_mode.app_rd_data_reg[159] ),\n .\\not_strict_mode.app_rd_data_reg[15] (\\not_strict_mode.app_rd_data_reg[15] ),\n .\\not_strict_mode.app_rd_data_reg[15]_0 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r ),\n .\\not_strict_mode.app_rd_data_reg[15]_1 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out ),\n .\\not_strict_mode.app_rd_data_reg[160] (\\not_strict_mode.app_rd_data_reg[160] ),\n .\\not_strict_mode.app_rd_data_reg[161] (\\not_strict_mode.app_rd_data_reg[161] ),\n .\\not_strict_mode.app_rd_data_reg[162] (\\not_strict_mode.app_rd_data_reg[162] ),\n .\\not_strict_mode.app_rd_data_reg[163] (\\not_strict_mode.app_rd_data_reg[163] ),\n .\\not_strict_mode.app_rd_data_reg[164] (\\not_strict_mode.app_rd_data_reg[164] ),\n .\\not_strict_mode.app_rd_data_reg[165] (\\not_strict_mode.app_rd_data_reg[165] ),\n .\\not_strict_mode.app_rd_data_reg[166] (\\not_strict_mode.app_rd_data_reg[166] ),\n .\\not_strict_mode.app_rd_data_reg[167] (\\not_strict_mode.app_rd_data_reg[167] ),\n .\\not_strict_mode.app_rd_data_reg[168] (\\not_strict_mode.app_rd_data_reg[168] ),\n .\\not_strict_mode.app_rd_data_reg[169] (\\not_strict_mode.app_rd_data_reg[169] ),\n .\\not_strict_mode.app_rd_data_reg[16] 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(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out ),\n .\\not_strict_mode.app_rd_data_reg[80] (\\not_strict_mode.app_rd_data_reg[80] ),\n .\\not_strict_mode.app_rd_data_reg[81] (\\not_strict_mode.app_rd_data_reg[81] ),\n .\\not_strict_mode.app_rd_data_reg[82] (\\not_strict_mode.app_rd_data_reg[82] ),\n .\\not_strict_mode.app_rd_data_reg[83] (\\not_strict_mode.app_rd_data_reg[83] ),\n .\\not_strict_mode.app_rd_data_reg[84] (\\not_strict_mode.app_rd_data_reg[84] ),\n .\\not_strict_mode.app_rd_data_reg[85] (\\not_strict_mode.app_rd_data_reg[85] ),\n .\\not_strict_mode.app_rd_data_reg[86] (\\not_strict_mode.app_rd_data_reg[86] ),\n .\\not_strict_mode.app_rd_data_reg[87] (\\not_strict_mode.app_rd_data_reg[87] ),\n .\\not_strict_mode.app_rd_data_reg[88] (\\not_strict_mode.app_rd_data_reg[88] ),\n .\\not_strict_mode.app_rd_data_reg[89] (\\not_strict_mode.app_rd_data_reg[89] ),\n .\\not_strict_mode.app_rd_data_reg[8] (\\not_strict_mode.app_rd_data_reg[8] ),\n .\\not_strict_mode.app_rd_data_reg[90] (\\not_strict_mode.app_rd_data_reg[90] ),\n .\\not_strict_mode.app_rd_data_reg[91] (\\not_strict_mode.app_rd_data_reg[91] ),\n .\\not_strict_mode.app_rd_data_reg[92] (\\not_strict_mode.app_rd_data_reg[92] ),\n .\\not_strict_mode.app_rd_data_reg[93] (\\not_strict_mode.app_rd_data_reg[93] ),\n .\\not_strict_mode.app_rd_data_reg[94] (\\not_strict_mode.app_rd_data_reg[94] ),\n .\\not_strict_mode.app_rd_data_reg[95] (\\not_strict_mode.app_rd_data_reg[95] ),\n .\\not_strict_mode.app_rd_data_reg[96] (\\not_strict_mode.app_rd_data_reg[96] ),\n .\\not_strict_mode.app_rd_data_reg[97] (\\not_strict_mode.app_rd_data_reg[97] ),\n .\\not_strict_mode.app_rd_data_reg[98] (\\not_strict_mode.app_rd_data_reg[98] ),\n .\\not_strict_mode.app_rd_data_reg[99] (\\not_strict_mode.app_rd_data_reg[99] ),\n .\\not_strict_mode.app_rd_data_reg[9] (\\not_strict_mode.app_rd_data_reg[9] ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ),\n 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(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ),\n .\\not_strict_mode.status_ram.rd_buf_we_r1_reg (\\not_strict_mode.status_ram.rd_buf_we_r1_reg ),\n .of_ctl_full_v(of_ctl_full_v),\n .ofs_rdy_r_reg(ofs_rdy_r_reg),\n .ofs_rdy_r_reg_0(ofs_rdy_r_reg_0),\n .out(u_ddr_calib_top_n_45),\n .p_0_out(\\u_ddr_phy_wrcal/p_0_out ),\n .pd_out(pd_out),\n .phy_dout({phy_dout[1],\\cmd_pipe_plus.mc_address_reg[43] [1],phy_dout[0],\\cmd_pipe_plus.mc_address_reg[43] [0],mux_address[57],mux_address[42],mux_address[27],mux_address[12],mux_address[56],mux_address[41],mux_address[26],mux_address[11],mux_address[55],mux_address[40],mux_address[25],mux_address[10],mux_address[54],mux_address[39],mux_address[24],mux_address[9],mux_address[53],mux_address[38],mux_address[23],mux_address[8],mux_address[52],mux_address[37],mux_address[22],mux_address[7],mux_address[51],mux_address[36],mux_address[21],mux_address[6],mux_address[50],mux_address[35],mux_address[20],mux_address[5]}),\n .phy_if_empty_r_reg(u_ddr_mc_phy_wrapper_n_1127),\n .phy_if_reset(phy_if_reset),\n .phy_mc_ctl_full(phy_mc_ctl_full),\n .phy_rddata_en(phy_rddata_en),\n .phy_read_calib(phy_read_calib),\n .phy_write_calib(phy_write_calib),\n .\\pi_dqs_found_lanes_r1_reg[3] ({u_ddr_mc_phy_wrapper_n_43,u_ddr_mc_phy_wrapper_n_44,u_ddr_mc_phy_wrapper_n_45,u_ddr_mc_phy_wrapper_n_46}),\n .pi_en_stg2_f_reg(u_ddr_calib_top_n_455),\n .pi_en_stg2_f_reg_0(u_ddr_calib_top_n_431),\n .pi_en_stg2_f_reg_1(u_ddr_calib_top_n_421),\n .pi_en_stg2_f_reg_2(u_ddr_calib_top_n_411),\n .pi_phase_locked_all_r1_reg(u_ddr_mc_phy_wrapper_n_756),\n .\\pi_rdval_cnt_reg[5] (\\u_ddr_mc_phy/pi_counter_read_val_w[0]_1 ),\n .pi_stg2_f_incdec_reg(u_ddr_calib_top_n_454),\n .pi_stg2_f_incdec_reg_0(u_ddr_calib_top_n_430),\n .pi_stg2_f_incdec_reg_1(u_ddr_calib_top_n_420),\n .pi_stg2_f_incdec_reg_2(u_ddr_calib_top_n_410),\n .pll_locked(pll_locked),\n .\\po_counter_read_val_r_reg[5] ({u_ddr_mc_phy_wrapper_n_107,u_ddr_mc_phy_wrapper_n_108,u_ddr_mc_phy_wrapper_n_109,u_ddr_mc_phy_wrapper_n_110,u_ddr_mc_phy_wrapper_n_111,u_ddr_mc_phy_wrapper_n_112}),\n .\\po_rdval_cnt_reg[8] ({\\u_ddr_mc_phy/po_counter_read_val_w[0]_0 [8:6],\\u_ddr_mc_phy/po_counter_read_val_w[0]_0 [3],\\u_ddr_mc_phy/po_counter_read_val_w[0]_0 [0]}),\n .\\po_rdval_cnt_reg[8]_0 ({\\u_ddr_mc_phy/po_counter_read_val_w[1]_2 [8:6],\\u_ddr_mc_phy/po_counter_read_val_w[1]_2 [3],\\u_ddr_mc_phy/po_counter_read_val_w[1]_2 [0]}),\n .\\po_stg2_wrcal_cnt_reg[1] (po_stg2_wrcal_cnt),\n .prbs_rdlvl_start_reg(u_ddr_calib_top_n_47),\n .ram_init_done_r(ram_init_done_r),\n .rd_buf_we(rd_buf_we),\n .\\rd_mux_sel_r_reg[1] ({u_ddr_calib_top_n_833,u_ddr_calib_top_n_834}),\n .\\rd_ptr_reg[3] ({\\rd_ptr_reg[3] [71:70],\\rd_ptr_reg[3] [65:62],\\rd_ptr_reg[3] [57:54],\\rd_ptr_reg[3] [33:30],\\rd_ptr_reg[3] [25:21],\\rd_ptr_reg[3] [17:13],\\rd_ptr_reg[3] [9:0]}),\n .\\rd_ptr_reg[3]_0 ({\\rd_ptr_reg[3]_0 [29:26],\\rd_ptr_reg[3]_0 [21:18],\\rd_ptr_reg[3]_0 [13:12],\\rd_ptr_reg[3]_0 [7:0]}),\n .\\rd_ptr_timing_reg[2] (\\rd_ptr_timing_reg[2] ),\n .\\rd_ptr_timing_reg[2]_0 (\\rd_ptr_timing_reg[2]_0 ),\n .\\rd_ptr_timing_reg[2]_1 (\\rd_ptr_timing_reg[2]_1 ),\n .\\rd_ptr_timing_reg[2]_10 (\\rd_ptr_timing_reg[2]_10 ),\n .\\rd_ptr_timing_reg[2]_2 (\\rd_ptr_timing_reg[2]_2 ),\n .\\rd_ptr_timing_reg[2]_3 (\\rd_ptr_timing_reg[2]_3 ),\n .\\rd_ptr_timing_reg[2]_4 (\\rd_ptr_timing_reg[2]_4 ),\n .\\rd_ptr_timing_reg[2]_5 (\\rd_ptr_timing_reg[2]_5 ),\n .\\rd_ptr_timing_reg[2]_6 (\\rd_ptr_timing_reg[2]_6 ),\n .\\rd_ptr_timing_reg[2]_7 (\\rd_ptr_timing_reg[2]_7 ),\n .\\rd_ptr_timing_reg[2]_8 (\\rd_ptr_timing_reg[2]_8 ),\n .\\rd_ptr_timing_reg[2]_9 (\\rd_ptr_timing_reg[2]_9 ),\n .\\read_fifo.fifo_out_data_r_reg[6] (\\read_fifo.fifo_out_data_r_reg[6] ),\n .\\read_fifo.fifo_out_data_r_reg[6]_0 (\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .\\read_fifo.tail_r_reg[0] (\\read_fifo.tail_r_reg[0] ),\n .\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] (\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .rst_sync_r1(rst_sync_r1),\n .rst_sync_r1_reg(rst_sync_r1_reg),\n .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9),\n .sync_pulse(sync_pulse),\n .sys_rst(sys_rst),\n .tail_r(tail_r),\n .wr_en(wr_en),\n .wr_en_5(wr_en_5),\n .wr_en_6(wr_en_6),\n .\\wr_ptr_timing_reg[2] (\\wr_ptr_timing_reg[2] ),\n .\\wr_ptr_timing_reg[2]_0 (\\wr_ptr_timing_reg[2]_0 ),\n .\\wr_ptr_timing_reg[2]_1 (\\wr_ptr_timing_reg[2]_1 ),\n .\\write_buffer.wr_buf_out_data_reg[224] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ),\n .\\write_buffer.wr_buf_out_data_reg[225] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ),\n .\\write_buffer.wr_buf_out_data_reg[226] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ),\n .\\write_buffer.wr_buf_out_data_reg[227] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ),\n .\\write_buffer.wr_buf_out_data_reg[228] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ),\n .\\write_buffer.wr_buf_out_data_reg[229] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ),\n .\\write_buffer.wr_buf_out_data_reg[230] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ),\n .\\write_buffer.wr_buf_out_data_reg[231] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 ),\n .\\write_buffer.wr_buf_out_data_reg[232] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ),\n .\\write_buffer.wr_buf_out_data_reg[233] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ),\n .\\write_buffer.wr_buf_out_data_reg[234] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ),\n .\\write_buffer.wr_buf_out_data_reg[235] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ),\n .\\write_buffer.wr_buf_out_data_reg[236] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ),\n .\\write_buffer.wr_buf_out_data_reg[237] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ),\n .\\write_buffer.wr_buf_out_data_reg[238] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ),\n .\\write_buffer.wr_buf_out_data_reg[239] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1 ),\n .\\write_buffer.wr_buf_out_data_reg[240] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8 ),\n .\\write_buffer.wr_buf_out_data_reg[241] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7 ),\n .\\write_buffer.wr_buf_out_data_reg[242] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ),\n .\\write_buffer.wr_buf_out_data_reg[243] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ),\n .\\write_buffer.wr_buf_out_data_reg[244] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ),\n .\\write_buffer.wr_buf_out_data_reg[245] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3 ),\n .\\write_buffer.wr_buf_out_data_reg[246] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2 ),\n .\\write_buffer.wr_buf_out_data_reg[247] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1 ),\n .\\write_buffer.wr_buf_out_data_reg[248] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7 ),\n .\\write_buffer.wr_buf_out_data_reg[249] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6 ),\n .\\write_buffer.wr_buf_out_data_reg[250] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5 ),\n .\\write_buffer.wr_buf_out_data_reg[251] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4 ),\n .\\write_buffer.wr_buf_out_data_reg[252] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3 ),\n .\\write_buffer.wr_buf_out_data_reg[253] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2 ),\n .\\write_buffer.wr_buf_out_data_reg[254] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ),\n .\\write_buffer.wr_buf_out_data_reg[255] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0 ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_phy_wrcal\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_phy_wrcal\n (rd_active_r1,\n rd_active_r2,\n wrcal_pat_resume_r,\n wrcal_resume_w,\n idelay_ld_reg_0,\n wrcal_done_reg_0,\n \\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 ,\n \\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 ,\n \\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 ,\n \\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 ,\n \\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 ,\n \\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 ,\n \\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 ,\n \\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 ,\n \\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 ,\n \\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 ,\n \\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 ,\n \\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_208 ,\n \\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 ,\n \\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 ,\n \\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 ,\n \\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_212 ,\n \\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 ,\n \\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 ,\n \\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 ,\n \\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 ,\n \\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 ,\n \\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 ,\n \\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 ,\n \\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 ,\n \\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 ,\n \\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 ,\n \\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 ,\n \\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 ,\n \\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 ,\n \\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 ,\n \\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 ,\n \\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 ,\n \\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 ,\n \\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 ,\n \\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 ,\n \\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 ,\n \\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 ,\n \\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 ,\n \\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 ,\n \\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 ,\n \\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 ,\n \\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 ,\n \\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 ,\n \\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 ,\n \\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 ,\n \\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 ,\n \\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 ,\n \\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 ,\n \\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 ,\n \\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 ,\n \\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 ,\n \\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 ,\n \\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 ,\n \\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 ,\n \\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 ,\n \\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 ,\n \\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 ,\n \\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 ,\n \\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 ,\n \\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 ,\n early2_data_reg_0,\n early1_data_reg_0,\n wrcal_prech_req,\n wrcal_pat_resume_r_reg_0,\n cal2_done_r,\n wrcal_sanity_chk_done_reg_0,\n wrlvl_byte_redo,\n early1_data_reg_1,\n early2_data_reg_1,\n idelay_ld,\n phy_if_reset_w,\n LD0,\n LD0_0,\n LD0_1,\n LD0_2,\n \\init_state_r_reg[3] ,\n wrcal_done_reg_1,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] ,\n \\idelay_tap_cnt_r_reg[0][2][0] ,\n \\idelay_tap_cnt_r_reg[0][2][0]_0 ,\n \\idelay_tap_cnt_r_reg[0][1][0] ,\n \\init_state_r_reg[0] ,\n \\init_state_r_reg[2] ,\n \\init_state_r_reg[4] ,\n \\init_state_r_reg[0]_0 ,\n \\init_state_r_reg[0]_1 ,\n \\init_state_r_reg[5] ,\n \\init_state_r_reg[0]_2 ,\n \\corse_cnt_reg[1][2] ,\n \\corse_cnt_reg[2][2] ,\n done_dqs_dec239_out,\n \\corse_cnt_reg[0][2] ,\n \\wrlvl_redo_corse_inc_reg[2] ,\n \\FSM_sequential_wl_state_r_reg[0] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[1] ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[2] ,\n \\not_empty_wait_cnt_reg[0]_0 ,\n wrcal_pat_resume_r_reg_1,\n idelay_ld_done_reg_0,\n cal2_if_reset_reg_0,\n cal2_if_reset_reg_1,\n idelay_ld_reg_1,\n cal2_done_r_reg_0,\n wrlvl_byte_redo_reg_0,\n early1_data_reg_2,\n cal2_if_reset_reg_2,\n phy_rddata_en_1,\n CLK,\n \\po_stg2_wrcal_cnt_reg[1]_0 ,\n \\po_stg2_wrcal_cnt_reg[1]_1 ,\n \\po_stg2_wrcal_cnt_reg[1]_2 ,\n \\po_stg2_wrcal_cnt_reg[1]_3 ,\n wrcal_sanity_chk,\n p_0_out,\n \\po_stg2_wrcal_cnt_reg[1]_4 ,\n \\po_stg2_wrcal_cnt_reg[1]_5 ,\n \\po_stg2_wrcal_cnt_reg[1]_6 ,\n \\po_stg2_wrcal_cnt_reg[1]_7 ,\n \\po_stg2_wrcal_cnt_reg[1]_8 ,\n \\po_stg2_wrcal_cnt_reg[1]_9 ,\n \\po_stg2_wrcal_cnt_reg[1]_10 ,\n \\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1][0]_0 ,\n \\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2][0]_0 ,\n \\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5][0]_0 ,\n \\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6][0]_0 ,\n \\po_stg2_wrcal_cnt_reg[1]_11 ,\n \\po_stg2_wrcal_cnt_reg[1]_12 ,\n \\po_stg2_wrcal_cnt_reg[1]_13 ,\n \\po_stg2_wrcal_cnt_reg[1]_14 ,\n \\po_stg2_wrcal_cnt_reg[1]_15 ,\n \\po_stg2_wrcal_cnt_reg[1]_16 ,\n \\po_stg2_wrcal_cnt_reg[1]_17 ,\n \\po_stg2_wrcal_cnt_reg[1]_18 ,\n \\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0][0]_0 ,\n \\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1][0]_0 ,\n \\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3][0]_0 ,\n \\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4][0]_0 ,\n \\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5][0]_0 ,\n \\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7][0]_0 ,\n \\po_stg2_wrcal_cnt_reg[1]_19 ,\n \\po_stg2_wrcal_cnt_reg[1]_20 ,\n \\po_stg2_wrcal_cnt_reg[1]_21 ,\n \\po_stg2_wrcal_cnt_reg[1]_22 ,\n \\po_stg2_wrcal_cnt_reg[1]_23 ,\n \\po_stg2_wrcal_cnt_reg[1]_24 ,\n \\po_stg2_wrcal_cnt_reg[1]_25 ,\n \\po_stg2_wrcal_cnt_reg[1]_26 ,\n \\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0][0]_0 ,\n \\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2][0]_0 ,\n \\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4][0]_0 ,\n \\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6][0]_0 ,\n \\po_stg2_wrcal_cnt_reg[1]_27 ,\n \\po_stg2_wrcal_cnt_reg[1]_28 ,\n \\po_stg2_wrcal_cnt_reg[1]_29 ,\n \\po_stg2_wrcal_cnt_reg[1]_30 ,\n \\po_stg2_wrcal_cnt_reg[1]_31 ,\n \\po_stg2_wrcal_cnt_reg[1]_32 ,\n \\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2][0]_0 ,\n \\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6][0]_0 ,\n \\po_stg2_wrcal_cnt_reg[1]_33 ,\n \\po_stg2_wrcal_cnt_reg[1]_34 ,\n \\po_stg2_wrcal_cnt_reg[1]_35 ,\n \\po_stg2_wrcal_cnt_reg[1]_36 ,\n \\po_stg2_wrcal_cnt_reg[1]_37 ,\n \\po_stg2_wrcal_cnt_reg[1]_38 ,\n \\po_stg2_wrcal_cnt_reg[1]_39 ,\n \\po_stg2_wrcal_cnt_reg[1]_40 ,\n \\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2][0]_0 ,\n \\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3][0]_0 ,\n \\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6][0]_0 ,\n \\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7][0]_0 ,\n \\po_stg2_wrcal_cnt_reg[1]_41 ,\n \\po_stg2_wrcal_cnt_reg[1]_42 ,\n \\po_stg2_wrcal_cnt_reg[1]_43 ,\n \\po_stg2_wrcal_cnt_reg[1]_44 ,\n \\po_stg2_wrcal_cnt_reg[1]_45 ,\n \\po_stg2_wrcal_cnt_reg[1]_46 ,\n \\po_stg2_wrcal_cnt_reg[1]_47 ,\n \\po_stg2_wrcal_cnt_reg[1]_48 ,\n \\po_stg2_wrcal_cnt_reg[1]_49 ,\n \\po_stg2_wrcal_cnt_reg[1]_50 ,\n \\po_stg2_wrcal_cnt_reg[1]_51 ,\n \\po_stg2_wrcal_cnt_reg[1]_52 ,\n \\po_stg2_wrcal_cnt_reg[1]_53 ,\n \\po_stg2_wrcal_cnt_reg[1]_54 ,\n \\po_stg2_wrcal_cnt_reg[1]_55 ,\n \\po_stg2_wrcal_cnt_reg[1]_56 ,\n \\po_stg2_wrcal_cnt_reg[1]_57 ,\n \\po_stg2_wrcal_cnt_reg[1]_58 ,\n \\po_stg2_wrcal_cnt_reg[1]_59 ,\n \\po_stg2_wrcal_cnt_reg[1]_60 ,\n \\po_stg2_wrcal_cnt_reg[1]_61 ,\n \\po_stg2_wrcal_cnt_reg[1]_62 ,\n \\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0][0]_0 ,\n \\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3][0]_0 ,\n \\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4][0]_0 ,\n \\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7][0]_0 ,\n \\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1][0]_0 ,\n \\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5][0]_0 ,\n \\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2][0]_0 ,\n \\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6][0]_0 ,\n \\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0][0]_0 ,\n \\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4][0]_0 ,\n \\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1][0]_0 ,\n \\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3][0]_0 ,\n \\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5][0]_0 ,\n \\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7][0]_0 ,\n rstdiv0_sync_r1_reg_rep__6,\n wrlvl_byte_done,\n rstdiv0_sync_r1_reg_rep__4,\n \\cal2_state_r_reg[0]_0 ,\n \\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1][0]_0 ,\n \\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5][0]_0 ,\n \\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0][0]_0 ,\n \\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4][0]_0 ,\n \\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1][0]_0 ,\n \\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3][0]_0 ,\n \\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5][0]_0 ,\n \\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7][0]_0 ,\n \\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3][0]_0 ,\n \\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7][0]_0 ,\n \\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2][0]_0 ,\n \\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6][0]_0 ,\n \\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2][0]_0 ,\n \\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6][0]_0 ,\n \\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0][0]_0 ,\n \\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2][0]_0 ,\n \\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4][0]_0 ,\n \\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6][0]_0 ,\n \\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1][0]_0 ,\n \\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5][0]_0 ,\n \\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3][0]_0 ,\n \\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7][0]_0 ,\n \\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1][0]_0 ,\n \\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5][0]_0 ,\n \\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0][0]_0 ,\n \\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4][0]_0 ,\n wrcal_sanity_chk_r_reg_0,\n rstdiv0_sync_r1_reg_rep__5,\n \\cal2_state_r_reg[3]_0 ,\n \\gen_pat_match_div4.early2_data_match_r_reg_0 ,\n \\gen_pat_match_div4.early1_data_match_r_reg_0 ,\n rstdiv0_sync_r1_reg_rep__2,\n \\gen_pat_match_div4.early1_data_match_r_reg_1 ,\n \\gen_pat_match_div4.pat_data_match_valid_r_reg_0 ,\n \\cal2_state_r_reg[2]_0 ,\n \\cal2_state_r_reg[0]_1 ,\n Q,\n \\calib_sel_reg[1] ,\n calib_in_common,\n idelay_ld_rst,\n idelay_ld_rst_3,\n idelay_ld_rst_4,\n idelay_ld_rst_5,\n dqs_found_done_r_reg,\n rdlvl_stg1_start_int_reg,\n rdlvl_stg1_done_int_reg,\n oclkdelay_calib_done_r_reg,\n first_wrcal_pat_r,\n idelay_ce_int,\n oclkdelay_calib_done_r_reg_0,\n wrlvl_final_mux,\n mem_init_done_r,\n dqs_found_done_r_reg_0,\n mpr_rdlvl_done_r_reg,\n mpr_last_byte_done,\n prbs_rdlvl_done_reg_rep,\n prech_req_posedge_r_reg,\n wrcal_resume_r,\n wrlvl_done_r1,\n rdlvl_stg1_done_int_reg_0,\n oclkdelay_center_calib_done_r_reg,\n prbs_rdlvl_done_reg_rep_0,\n ddr3_lm_done_r,\n wrlvl_byte_redo_r,\n \\final_coarse_tap_reg[3][2] ,\n wl_sm_start,\n prbs_rdlvl_done_reg,\n \\prbs_dqs_cnt_r_reg[0] ,\n \\prbs_dqs_cnt_r_reg[1] ,\n rstdiv0_sync_r1_reg_rep__22,\n wrcal_rd_wait,\n wrcal_start_reg,\n prech_done,\n wrcal_sanity_chk_reg,\n phy_rddata_en_r1_reg);\n output rd_active_r1;\n output rd_active_r2;\n output wrcal_pat_resume_r;\n output wrcal_resume_w;\n output idelay_ld_reg_0;\n output wrcal_done_reg_0;\n output \\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 ;\n output \\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 ;\n output \\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 ;\n output \\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 ;\n output \\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 ;\n output \\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 ;\n output \\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 ;\n output \\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 ;\n output \\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 ;\n output \\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 ;\n output \\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 ;\n output \\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_208 ;\n output \\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 ;\n output \\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 ;\n output \\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 ;\n output \\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_212 ;\n output \\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 ;\n output \\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 ;\n output \\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 ;\n output \\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 ;\n output \\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 ;\n output \\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 ;\n output \\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 ;\n output \\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 ;\n output \\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 ;\n output \\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 ;\n output \\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 ;\n output \\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 ;\n output \\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 ;\n output \\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 ;\n output \\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 ;\n output \\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 ;\n output \\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 ;\n output \\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 ;\n output \\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 ;\n output \\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 ;\n output \\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 ;\n output \\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 ;\n output \\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 ;\n output \\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 ;\n output \\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 ;\n output \\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 ;\n output \\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 ;\n output \\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 ;\n output \\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 ;\n output \\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 ;\n output \\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 ;\n output \\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 ;\n output \\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 ;\n output \\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 ;\n output \\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 ;\n output \\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 ;\n output \\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 ;\n output \\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 ;\n output \\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 ;\n output \\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 ;\n output \\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 ;\n output \\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 ;\n output \\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 ;\n output \\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 ;\n output early2_data_reg_0;\n output early1_data_reg_0;\n output wrcal_prech_req;\n output wrcal_pat_resume_r_reg_0;\n output cal2_done_r;\n output wrcal_sanity_chk_done_reg_0;\n output wrlvl_byte_redo;\n output early1_data_reg_1;\n output early2_data_reg_1;\n output idelay_ld;\n output phy_if_reset_w;\n output LD0;\n output LD0_0;\n output LD0_1;\n output LD0_2;\n output \\init_state_r_reg[3] ;\n output wrcal_done_reg_1;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] ;\n output \\idelay_tap_cnt_r_reg[0][2][0] ;\n output [2:0]\\idelay_tap_cnt_r_reg[0][2][0]_0 ;\n output \\idelay_tap_cnt_r_reg[0][1][0] ;\n output \\init_state_r_reg[0] ;\n output \\init_state_r_reg[2] ;\n output \\init_state_r_reg[4] ;\n output \\init_state_r_reg[0]_0 ;\n output \\init_state_r_reg[0]_1 ;\n output \\init_state_r_reg[5] ;\n output \\init_state_r_reg[0]_2 ;\n output \\corse_cnt_reg[1][2] ;\n output \\corse_cnt_reg[2][2] ;\n output done_dqs_dec239_out;\n output \\corse_cnt_reg[0][2] ;\n output \\wrlvl_redo_corse_inc_reg[2] ;\n output \\FSM_sequential_wl_state_r_reg[0] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] ;\n output \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ;\n output \\gen_byte_sel_div1.byte_sel_cnt_reg[1] ;\n output \\gen_byte_sel_div1.byte_sel_cnt_reg[2] ;\n output [3:0]\\not_empty_wait_cnt_reg[0]_0 ;\n output wrcal_pat_resume_r_reg_1;\n output idelay_ld_done_reg_0;\n output cal2_if_reset_reg_0;\n output cal2_if_reset_reg_1;\n output idelay_ld_reg_1;\n output cal2_done_r_reg_0;\n output wrlvl_byte_redo_reg_0;\n output early1_data_reg_2;\n output cal2_if_reset_reg_2;\n input phy_rddata_en_1;\n input CLK;\n input \\po_stg2_wrcal_cnt_reg[1]_0 ;\n input \\po_stg2_wrcal_cnt_reg[1]_1 ;\n input \\po_stg2_wrcal_cnt_reg[1]_2 ;\n input \\po_stg2_wrcal_cnt_reg[1]_3 ;\n input wrcal_sanity_chk;\n input p_0_out;\n input \\po_stg2_wrcal_cnt_reg[1]_4 ;\n input \\po_stg2_wrcal_cnt_reg[1]_5 ;\n input \\po_stg2_wrcal_cnt_reg[1]_6 ;\n input \\po_stg2_wrcal_cnt_reg[1]_7 ;\n input \\po_stg2_wrcal_cnt_reg[1]_8 ;\n input \\po_stg2_wrcal_cnt_reg[1]_9 ;\n input \\po_stg2_wrcal_cnt_reg[1]_10 ;\n input \\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1][0]_0 ;\n input \\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2][0]_0 ;\n input \\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5][0]_0 ;\n input \\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6][0]_0 ;\n input \\po_stg2_wrcal_cnt_reg[1]_11 ;\n input \\po_stg2_wrcal_cnt_reg[1]_12 ;\n input \\po_stg2_wrcal_cnt_reg[1]_13 ;\n input \\po_stg2_wrcal_cnt_reg[1]_14 ;\n input \\po_stg2_wrcal_cnt_reg[1]_15 ;\n input \\po_stg2_wrcal_cnt_reg[1]_16 ;\n input \\po_stg2_wrcal_cnt_reg[1]_17 ;\n input \\po_stg2_wrcal_cnt_reg[1]_18 ;\n input \\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0][0]_0 ;\n input \\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1][0]_0 ;\n input \\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3][0]_0 ;\n input \\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4][0]_0 ;\n input \\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5][0]_0 ;\n input \\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7][0]_0 ;\n input \\po_stg2_wrcal_cnt_reg[1]_19 ;\n input \\po_stg2_wrcal_cnt_reg[1]_20 ;\n input \\po_stg2_wrcal_cnt_reg[1]_21 ;\n input \\po_stg2_wrcal_cnt_reg[1]_22 ;\n input \\po_stg2_wrcal_cnt_reg[1]_23 ;\n input \\po_stg2_wrcal_cnt_reg[1]_24 ;\n input \\po_stg2_wrcal_cnt_reg[1]_25 ;\n input \\po_stg2_wrcal_cnt_reg[1]_26 ;\n input \\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0][0]_0 ;\n input \\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2][0]_0 ;\n input \\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4][0]_0 ;\n input \\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6][0]_0 ;\n input \\po_stg2_wrcal_cnt_reg[1]_27 ;\n input \\po_stg2_wrcal_cnt_reg[1]_28 ;\n input \\po_stg2_wrcal_cnt_reg[1]_29 ;\n input \\po_stg2_wrcal_cnt_reg[1]_30 ;\n input \\po_stg2_wrcal_cnt_reg[1]_31 ;\n input \\po_stg2_wrcal_cnt_reg[1]_32 ;\n input \\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2][0]_0 ;\n input \\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6][0]_0 ;\n input \\po_stg2_wrcal_cnt_reg[1]_33 ;\n input \\po_stg2_wrcal_cnt_reg[1]_34 ;\n input \\po_stg2_wrcal_cnt_reg[1]_35 ;\n input \\po_stg2_wrcal_cnt_reg[1]_36 ;\n input \\po_stg2_wrcal_cnt_reg[1]_37 ;\n input \\po_stg2_wrcal_cnt_reg[1]_38 ;\n input \\po_stg2_wrcal_cnt_reg[1]_39 ;\n input \\po_stg2_wrcal_cnt_reg[1]_40 ;\n input \\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2][0]_0 ;\n input \\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3][0]_0 ;\n input \\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6][0]_0 ;\n input \\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7][0]_0 ;\n input \\po_stg2_wrcal_cnt_reg[1]_41 ;\n input \\po_stg2_wrcal_cnt_reg[1]_42 ;\n input \\po_stg2_wrcal_cnt_reg[1]_43 ;\n input \\po_stg2_wrcal_cnt_reg[1]_44 ;\n input \\po_stg2_wrcal_cnt_reg[1]_45 ;\n input \\po_stg2_wrcal_cnt_reg[1]_46 ;\n input \\po_stg2_wrcal_cnt_reg[1]_47 ;\n input \\po_stg2_wrcal_cnt_reg[1]_48 ;\n input \\po_stg2_wrcal_cnt_reg[1]_49 ;\n input \\po_stg2_wrcal_cnt_reg[1]_50 ;\n input \\po_stg2_wrcal_cnt_reg[1]_51 ;\n input \\po_stg2_wrcal_cnt_reg[1]_52 ;\n input \\po_stg2_wrcal_cnt_reg[1]_53 ;\n input \\po_stg2_wrcal_cnt_reg[1]_54 ;\n input \\po_stg2_wrcal_cnt_reg[1]_55 ;\n input \\po_stg2_wrcal_cnt_reg[1]_56 ;\n input \\po_stg2_wrcal_cnt_reg[1]_57 ;\n input \\po_stg2_wrcal_cnt_reg[1]_58 ;\n input \\po_stg2_wrcal_cnt_reg[1]_59 ;\n input \\po_stg2_wrcal_cnt_reg[1]_60 ;\n input \\po_stg2_wrcal_cnt_reg[1]_61 ;\n input \\po_stg2_wrcal_cnt_reg[1]_62 ;\n input \\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0][0]_0 ;\n input \\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3][0]_0 ;\n input \\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4][0]_0 ;\n input \\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7][0]_0 ;\n input \\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1][0]_0 ;\n input \\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5][0]_0 ;\n input \\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2][0]_0 ;\n input \\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6][0]_0 ;\n input \\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0][0]_0 ;\n input \\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4][0]_0 ;\n input \\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1][0]_0 ;\n input \\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3][0]_0 ;\n input \\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5][0]_0 ;\n input \\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7][0]_0 ;\n input rstdiv0_sync_r1_reg_rep__6;\n input wrlvl_byte_done;\n input [0:0]rstdiv0_sync_r1_reg_rep__4;\n input \\cal2_state_r_reg[0]_0 ;\n input \\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1][0]_0 ;\n input \\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5][0]_0 ;\n input \\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0][0]_0 ;\n input \\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4][0]_0 ;\n input \\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1][0]_0 ;\n input \\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3][0]_0 ;\n input \\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5][0]_0 ;\n input \\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7][0]_0 ;\n input \\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3][0]_0 ;\n input \\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7][0]_0 ;\n input \\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2][0]_0 ;\n input \\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6][0]_0 ;\n input \\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2][0]_0 ;\n input \\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6][0]_0 ;\n input \\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0][0]_0 ;\n input \\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2][0]_0 ;\n input \\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4][0]_0 ;\n input \\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6][0]_0 ;\n input \\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1][0]_0 ;\n input \\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5][0]_0 ;\n input \\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3][0]_0 ;\n input \\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7][0]_0 ;\n input \\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1][0]_0 ;\n input \\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5][0]_0 ;\n input \\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0][0]_0 ;\n input \\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4][0]_0 ;\n input wrcal_sanity_chk_r_reg_0;\n input rstdiv0_sync_r1_reg_rep__5;\n input \\cal2_state_r_reg[3]_0 ;\n input \\gen_pat_match_div4.early2_data_match_r_reg_0 ;\n input \\gen_pat_match_div4.early1_data_match_r_reg_0 ;\n input rstdiv0_sync_r1_reg_rep__2;\n input \\gen_pat_match_div4.early1_data_match_r_reg_1 ;\n input \\gen_pat_match_div4.pat_data_match_valid_r_reg_0 ;\n input \\cal2_state_r_reg[2]_0 ;\n input \\cal2_state_r_reg[0]_1 ;\n input [0:0]Q;\n input [1:0]\\calib_sel_reg[1] ;\n input calib_in_common;\n input idelay_ld_rst;\n input idelay_ld_rst_3;\n input idelay_ld_rst_4;\n input idelay_ld_rst_5;\n input dqs_found_done_r_reg;\n input rdlvl_stg1_start_int_reg;\n input rdlvl_stg1_done_int_reg;\n input oclkdelay_calib_done_r_reg;\n input first_wrcal_pat_r;\n input idelay_ce_int;\n input oclkdelay_calib_done_r_reg_0;\n input wrlvl_final_mux;\n input mem_init_done_r;\n input dqs_found_done_r_reg_0;\n input mpr_rdlvl_done_r_reg;\n input mpr_last_byte_done;\n input prbs_rdlvl_done_reg_rep;\n input prech_req_posedge_r_reg;\n input wrcal_resume_r;\n input wrlvl_done_r1;\n input rdlvl_stg1_done_int_reg_0;\n input oclkdelay_center_calib_done_r_reg;\n input prbs_rdlvl_done_reg_rep_0;\n input ddr3_lm_done_r;\n input wrlvl_byte_redo_r;\n input [1:0]\\final_coarse_tap_reg[3][2] ;\n input wl_sm_start;\n input prbs_rdlvl_done_reg;\n input \\prbs_dqs_cnt_r_reg[0] ;\n input \\prbs_dqs_cnt_r_reg[1] ;\n input rstdiv0_sync_r1_reg_rep__22;\n input wrcal_rd_wait;\n input wrcal_start_reg;\n input prech_done;\n input wrcal_sanity_chk_reg;\n input phy_rddata_en_r1_reg;\n\n wire CLK;\n wire \\FSM_sequential_wl_state_r_reg[0] ;\n wire LD0;\n wire LD0_0;\n wire LD0_1;\n wire LD0_2;\n wire [0:0]Q;\n wire cal2_done_r;\n wire cal2_done_r_reg_0;\n wire cal2_if_reset_i_5_n_0;\n wire cal2_if_reset_reg_0;\n wire cal2_if_reset_reg_1;\n wire cal2_if_reset_reg_2;\n wire cal2_prech_req_r;\n wire cal2_prech_req_r_i_2_n_0;\n wire cal2_prech_req_r_i_3_n_0;\n wire cal2_state_r;\n wire \\cal2_state_r[0]_i_1_n_0 ;\n wire \\cal2_state_r[0]_i_2_n_0 ;\n wire \\cal2_state_r[0]_i_3_n_0 ;\n wire \\cal2_state_r[0]_i_4_n_0 ;\n wire \\cal2_state_r[0]_i_5_n_0 ;\n wire \\cal2_state_r[1]_i_1_n_0 ;\n wire \\cal2_state_r[1]_i_2_n_0 ;\n wire \\cal2_state_r[1]_i_3_n_0 ;\n wire \\cal2_state_r[2]_i_1_n_0 ;\n wire \\cal2_state_r[2]_i_2_n_0 ;\n wire \\cal2_state_r[2]_i_3_n_0 ;\n wire \\cal2_state_r[3]_i_11_n_0 ;\n wire \\cal2_state_r[3]_i_3_n_0 ;\n wire \\cal2_state_r[3]_i_4_n_0 ;\n wire \\cal2_state_r[3]_i_5_n_0 ;\n wire \\cal2_state_r[3]_i_6_n_0 ;\n wire \\cal2_state_r[3]_i_7_n_0 ;\n wire \\cal2_state_r[3]_i_8_n_0 ;\n wire \\cal2_state_r[3]_i_9_n_0 ;\n wire \\cal2_state_r_reg[0]_0 ;\n wire \\cal2_state_r_reg[0]_1 ;\n wire \\cal2_state_r_reg[2]_0 ;\n wire \\cal2_state_r_reg[3]_0 ;\n wire calib_in_common;\n wire [1:0]\\calib_sel_reg[1] ;\n wire \\corse_cnt_reg[0][2] ;\n wire \\corse_cnt_reg[1][2] ;\n wire \\corse_cnt_reg[2][2] ;\n wire ddr3_lm_done_r;\n wire done_dqs_dec239_out;\n wire dqs_found_done_r_reg;\n wire dqs_found_done_r_reg_0;\n wire early1_data_i_3_n_0;\n wire early1_data_match_r0__0;\n wire early1_data_reg_0;\n wire early1_data_reg_1;\n wire early1_data_reg_2;\n wire early1_match_fall0_and_r;\n wire early1_match_fall1_and_r;\n wire early1_match_fall2_and_r;\n wire early1_match_fall3_and_r;\n wire early1_match_rise0_and_r;\n wire early1_match_rise1_and_r;\n wire early1_match_rise2_and_r;\n wire early1_match_rise3_and_r;\n wire early2_data_match_r0__0;\n wire early2_data_reg_0;\n wire early2_data_reg_1;\n wire early2_match_fall0_and_r;\n wire early2_match_fall1_and_r;\n wire early2_match_fall2_and_r;\n wire early2_match_fall3_and_r;\n wire early2_match_rise0_and_r;\n wire early2_match_rise1_and_r;\n wire early2_match_rise2_and_r;\n wire early2_match_rise3_and_r;\n wire [1:0]\\final_coarse_tap_reg[3][2] ;\n wire first_wrcal_pat_r;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[1] ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ;\n wire \\gen_pat_match_div4.early1_data_match_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.early1_data_match_r_reg_0 ;\n wire \\gen_pat_match_div4.early1_data_match_r_reg_1 ;\n wire \\gen_pat_match_div4.early1_match_fall0_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.early1_match_fall1_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.early1_match_fall1_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.early1_match_fall2_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.early1_match_fall3_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.early1_match_fall3_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.early1_match_rise0_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.early1_match_rise1_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.early1_match_rise1_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.early1_match_rise2_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.early1_match_rise3_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.early2_data_match_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.early2_data_match_r_reg_0 ;\n wire \\gen_pat_match_div4.early2_match_fall0_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.early2_match_fall0_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.early2_match_fall1_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.early2_match_fall2_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.early2_match_fall2_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.early2_match_fall3_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.early2_match_rise0_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.early2_match_rise0_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.early2_match_rise1_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.early2_match_rise2_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.early2_match_rise2_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.early2_match_rise3_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.early2_match_rise3_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].early1_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].early1_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].early2_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].early1_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].early1_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].early2_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].early2_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].early1_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].early2_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].pat_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].pat_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].pat_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].early1_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].early2_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].early1_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].early1_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].early2_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].early1_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].early1_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].early2_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].early2_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].early1_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].early2_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].pat_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].pat_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].pat_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].early1_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].early2_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.pat_data_match_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat_data_match_r_reg_n_0 ;\n wire \\gen_pat_match_div4.pat_data_match_valid_r_reg_0 ;\n wire \\gen_pat_match_div4.pat_match_fall0_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat_match_fall1_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat_match_fall2_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat_match_fall3_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat_match_rise0_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat_match_rise1_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat_match_rise2_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat_match_rise3_and_r_i_1_n_0 ;\n wire \\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0][0]_0 ;\n wire \\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 ;\n wire \\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0][0]_0 ;\n wire \\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 ;\n wire \\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0][0]_0 ;\n wire \\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 ;\n wire \\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0][0]_0 ;\n wire \\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 ;\n wire \\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0][0]_0 ;\n wire \\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 ;\n wire \\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0][0]_0 ;\n wire \\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 ;\n wire \\gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2_n_0 ;\n wire \\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0][0]_0 ;\n wire \\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 ;\n wire \\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1][0]_0 ;\n wire \\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 ;\n wire \\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1][0]_0 ;\n wire \\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 ;\n wire \\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1][0]_0 ;\n wire \\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 ;\n wire \\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1][0]_0 ;\n wire \\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 ;\n wire \\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1][0]_0 ;\n wire \\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 ;\n wire \\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1][0]_0 ;\n wire \\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 ;\n wire \\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1][0]_0 ;\n wire \\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 ;\n wire \\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1][0]_0 ;\n wire \\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 ;\n wire \\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2][0]_0 ;\n wire \\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 ;\n wire \\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2][0]_0 ;\n wire \\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 ;\n wire \\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2][0]_0 ;\n wire \\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 ;\n wire \\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2][0]_0 ;\n wire \\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 ;\n wire \\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2][0]_0 ;\n wire \\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 ;\n wire \\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2][0]_0 ;\n wire \\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 ;\n wire \\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2][0]_0 ;\n wire \\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 ;\n wire \\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2][0]_0 ;\n wire \\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 ;\n wire \\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3][0]_0 ;\n wire \\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 ;\n wire \\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3][0]_0 ;\n wire \\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 ;\n wire \\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3][0]_0 ;\n wire \\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 ;\n wire \\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3][0]_0 ;\n wire \\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_208 ;\n wire \\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3][0]_0 ;\n wire \\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 ;\n wire \\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3][0]_0 ;\n wire \\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 ;\n wire \\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3][0]_0 ;\n wire \\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 ;\n wire \\gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2_n_0 ;\n wire \\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4][0]_0 ;\n wire \\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 ;\n wire \\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4][0]_0 ;\n wire \\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 ;\n wire \\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4][0]_0 ;\n wire \\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 ;\n wire \\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4][0]_0 ;\n wire \\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 ;\n wire \\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4][0]_0 ;\n wire \\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 ;\n wire \\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4][0]_0 ;\n wire \\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 ;\n wire \\gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2_n_0 ;\n wire \\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4][0]_0 ;\n wire \\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 ;\n wire \\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5][0]_0 ;\n wire \\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 ;\n wire \\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5][0]_0 ;\n wire \\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 ;\n wire \\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5][0]_0 ;\n wire \\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 ;\n wire \\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5][0]_0 ;\n wire \\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 ;\n wire \\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5][0]_0 ;\n wire \\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 ;\n wire \\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5][0]_0 ;\n wire \\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 ;\n wire \\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5][0]_0 ;\n wire \\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 ;\n wire \\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5][0]_0 ;\n wire \\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 ;\n wire \\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6][0]_0 ;\n wire \\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 ;\n wire \\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6][0]_0 ;\n wire \\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 ;\n wire \\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6][0]_0 ;\n wire \\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 ;\n wire \\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6][0]_0 ;\n wire \\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 ;\n wire \\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6][0]_0 ;\n wire \\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 ;\n wire \\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6][0]_0 ;\n wire \\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 ;\n wire \\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6][0]_0 ;\n wire \\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 ;\n wire \\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6][0]_0 ;\n wire \\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 ;\n wire \\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7][0]_0 ;\n wire \\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 ;\n wire \\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7][0]_0 ;\n wire \\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 ;\n wire \\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7][0]_0 ;\n wire \\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 ;\n wire \\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7][0]_0 ;\n wire \\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_212 ;\n wire \\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7][0]_0 ;\n wire \\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 ;\n wire \\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7][0]_0 ;\n wire \\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 ;\n wire \\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7][0]_0 ;\n wire \\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 ;\n wire \\gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2_n_0 ;\n wire idelay_ce_int;\n wire idelay_ld;\n wire idelay_ld_done_reg_0;\n wire idelay_ld_reg_0;\n wire idelay_ld_reg_1;\n wire idelay_ld_rst;\n wire idelay_ld_rst_3;\n wire idelay_ld_rst_4;\n wire idelay_ld_rst_5;\n wire \\idelay_tap_cnt_r_reg[0][1][0] ;\n wire \\idelay_tap_cnt_r_reg[0][2][0] ;\n wire [2:0]\\idelay_tap_cnt_r_reg[0][2][0]_0 ;\n wire \\init_state_r[0]_i_56_n_0 ;\n wire \\init_state_r[4]_i_34_n_0 ;\n wire \\init_state_r_reg[0] ;\n wire \\init_state_r_reg[0]_0 ;\n wire \\init_state_r_reg[0]_1 ;\n wire \\init_state_r_reg[0]_2 ;\n wire \\init_state_r_reg[2] ;\n wire \\init_state_r_reg[3] ;\n wire \\init_state_r_reg[4] ;\n wire \\init_state_r_reg[5] ;\n wire mem_init_done_r;\n wire mpr_last_byte_done;\n wire mpr_rdlvl_done_r_reg;\n wire \\not_empty_wait_cnt[4]_i_1_n_0 ;\n wire [3:0]\\not_empty_wait_cnt_reg[0]_0 ;\n wire \\not_empty_wait_cnt_reg_n_0_[0] ;\n wire \\not_empty_wait_cnt_reg_n_0_[1] ;\n wire \\not_empty_wait_cnt_reg_n_0_[2] ;\n wire \\not_empty_wait_cnt_reg_n_0_[3] ;\n wire \\not_empty_wait_cnt_reg_n_0_[4] ;\n wire oclkdelay_calib_done_r_reg;\n wire oclkdelay_calib_done_r_reg_0;\n wire oclkdelay_center_calib_done_r_reg;\n wire [4:0]p_0_in;\n wire [3:0]p_0_in__0;\n wire p_0_out;\n wire pat_data_match_r0__0;\n wire pat_match_fall0_and_r;\n wire pat_match_fall1_and_r;\n wire pat_match_fall2_and_r;\n wire pat_match_fall3_and_r;\n wire pat_match_rise0_and_r;\n wire pat_match_rise1_and_r;\n wire pat_match_rise2_and_r;\n wire pat_match_rise3_and_r;\n wire phy_if_reset_w;\n wire phy_rddata_en_1;\n wire phy_rddata_en_r1_reg;\n wire \\po_stg2_wrcal_cnt_reg[1]_0 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_1 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_10 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_11 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_12 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_13 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_14 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_15 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_16 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_17 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_18 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_19 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_2 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_20 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_21 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_22 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_23 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_24 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_25 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_26 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_27 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_28 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_29 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_3 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_30 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_31 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_32 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_33 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_34 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_35 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_36 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_37 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_38 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_39 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_4 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_40 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_41 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_42 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_43 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_44 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_45 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_46 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_47 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_48 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_49 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_5 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_50 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_51 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_52 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_53 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_54 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_55 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_56 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_57 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_58 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_59 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_6 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_60 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_61 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_62 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_7 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_8 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_9 ;\n wire \\prbs_dqs_cnt_r_reg[0] ;\n wire \\prbs_dqs_cnt_r_reg[1] ;\n wire prbs_rdlvl_done_reg;\n wire prbs_rdlvl_done_reg_rep;\n wire prbs_rdlvl_done_reg_rep_0;\n wire prech_done;\n wire prech_req_posedge_r_reg;\n wire rd_active_r1;\n wire rd_active_r2;\n wire rd_active_r3;\n wire rdlvl_stg1_done_int_reg;\n wire rdlvl_stg1_done_int_reg_0;\n wire rdlvl_stg1_start_int_reg;\n wire rstdiv0_sync_r1_reg_rep__2;\n wire rstdiv0_sync_r1_reg_rep__22;\n wire [0:0]rstdiv0_sync_r1_reg_rep__4;\n wire rstdiv0_sync_r1_reg_rep__5;\n wire rstdiv0_sync_r1_reg_rep__6;\n wire \\tap_inc_wait_cnt[3]_i_1_n_0 ;\n wire [3:0]tap_inc_wait_cnt_reg__0;\n wire wl_sm_start;\n wire wrcal_done_i_1_n_0;\n wire wrcal_done_reg_0;\n wire wrcal_done_reg_1;\n wire [2:2]wrcal_dqs_cnt_r;\n wire \\wrcal_dqs_cnt_r[0]_i_1_n_0 ;\n wire \\wrcal_dqs_cnt_r[1]_i_1_n_0 ;\n wire \\wrcal_dqs_cnt_r[2]_i_1_n_0 ;\n wire \\wrcal_dqs_cnt_r[2]_i_2_n_0 ;\n wire \\wrcal_dqs_cnt_r[2]_i_3_n_0 ;\n wire \\wrcal_dqs_cnt_r_reg_n_0_[0] ;\n wire \\wrcal_dqs_cnt_r_reg_n_0_[1] ;\n wire wrcal_pat_resume_r;\n wire wrcal_pat_resume_r2_reg_srl2_n_0;\n wire wrcal_pat_resume_r_i_3_n_0;\n wire wrcal_pat_resume_r_reg_0;\n wire wrcal_pat_resume_r_reg_1;\n wire wrcal_prech_req;\n wire wrcal_rd_wait;\n wire wrcal_resume_r;\n wire wrcal_resume_w;\n wire wrcal_sanity_chk;\n wire wrcal_sanity_chk_done_reg_0;\n wire wrcal_sanity_chk_r_reg_0;\n wire wrcal_sanity_chk_reg;\n wire wrcal_start_reg;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] ;\n wire wrlvl_byte_done;\n wire wrlvl_byte_done_r;\n wire wrlvl_byte_redo;\n wire wrlvl_byte_redo_i_3_n_0;\n wire wrlvl_byte_redo_r;\n wire wrlvl_byte_redo_reg_0;\n wire wrlvl_done_r1;\n wire wrlvl_final_mux;\n wire \\wrlvl_redo_corse_inc_reg[2] ;\n\n (* SOFT_HLUTNM = \"soft_lutpair632\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\FSM_sequential_wl_state_r[4]_i_13 \n (.I0(wrlvl_byte_redo),\n .I1(wl_sm_start),\n .O(\\FSM_sequential_wl_state_r_reg[0] ));\n LUT4 #(\n .INIT(16'hDD45)) \n \\FSM_sequential_wl_state_r[4]_i_6 \n (.I0(early1_data_reg_1),\n .I1(\\final_coarse_tap_reg[3][2] [0]),\n .I2(early2_data_reg_1),\n .I3(\\final_coarse_tap_reg[3][2] [1]),\n .O(\\wrlvl_redo_corse_inc_reg[2] ));\n LUT4 #(\n .INIT(16'h0040)) \n cal2_done_r_i_2\n (.I0(\\not_empty_wait_cnt_reg[0]_0 [3]),\n .I1(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I2(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I3(\\not_empty_wait_cnt_reg[0]_0 [0]),\n .O(cal2_done_r_reg_0));\n FDRE #(\n .INIT(1'b0)) \n cal2_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrcal_sanity_chk_r_reg_0),\n .Q(cal2_done_r),\n .R(rstdiv0_sync_r1_reg_rep__6));\n LUT6 #(\n .INIT(64'h004F0040F000F000)) \n cal2_if_reset_i_2\n (.I0(phy_rddata_en_1),\n .I1(rd_active_r1),\n .I2(\\not_empty_wait_cnt_reg[0]_0 [0]),\n .I3(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I4(wrcal_done_reg_0),\n .I5(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .O(cal2_if_reset_reg_2));\n LUT6 #(\n .INIT(64'h00FF000008FF08FF)) \n cal2_if_reset_i_3\n (.I0(wrlvl_byte_done),\n .I1(rd_active_r1),\n .I2(phy_rddata_en_1),\n .I3(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I4(idelay_ld_done_reg_0),\n .I5(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .O(cal2_if_reset_reg_1));\n LUT6 #(\n .INIT(64'hFF80FFFFFF800000)) \n cal2_if_reset_i_4\n (.I0(prech_done),\n .I1(cal2_prech_req_r_i_3_n_0),\n .I2(wrcal_done_reg_0),\n .I3(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I4(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I5(cal2_if_reset_i_5_n_0),\n .O(cal2_if_reset_reg_0));\n LUT6 #(\n .INIT(64'h8000FFFF80000000)) \n cal2_if_reset_i_5\n (.I0(tap_inc_wait_cnt_reg__0[2]),\n .I1(tap_inc_wait_cnt_reg__0[0]),\n .I2(tap_inc_wait_cnt_reg__0[1]),\n .I3(tap_inc_wait_cnt_reg__0[3]),\n .I4(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I5(wrcal_start_reg),\n .O(cal2_if_reset_i_5_n_0));\n FDRE #(\n .INIT(1'b0)) \n cal2_if_reset_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\cal2_state_r_reg[0]_1 ),\n .Q(phy_if_reset_w),\n .R(rstdiv0_sync_r1_reg_rep__5));\n LUT6 #(\n .INIT(64'h0000000010110000)) \n cal2_prech_req_r_i_2\n (.I0(\\not_empty_wait_cnt_reg[0]_0 [3]),\n .I1(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I2(cal2_prech_req_r_i_3_n_0),\n .I3(wrcal_done_reg_0),\n .I4(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I5(\\not_empty_wait_cnt_reg[0]_0 [0]),\n .O(cal2_prech_req_r_i_2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair631\" *) \n LUT3 #(\n .INIT(8'h08)) \n cal2_prech_req_r_i_3\n (.I0(\\wrcal_dqs_cnt_r_reg_n_0_[1] ),\n .I1(\\wrcal_dqs_cnt_r_reg_n_0_[0] ),\n .I2(wrcal_dqs_cnt_r),\n .O(cal2_prech_req_r_i_3_n_0));\n FDRE #(\n .INIT(1'b0)) \n cal2_prech_req_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cal2_prech_req_r_i_2_n_0),\n .Q(cal2_prech_req_r),\n .R(rstdiv0_sync_r1_reg_rep__6));\n LUT6 #(\n .INIT(64'h00000000E2FFE200)) \n \\cal2_state_r[0]_i_1 \n (.I0(\\cal2_state_r[0]_i_2_n_0 ),\n .I1(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I2(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I3(\\not_empty_wait_cnt_reg[0]_0 [0]),\n .I4(\\cal2_state_r[0]_i_3_n_0 ),\n .I5(\\not_empty_wait_cnt_reg[0]_0 [3]),\n .O(\\cal2_state_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hBBB8BBBB88888888)) \n \\cal2_state_r[0]_i_2 \n (.I0(tap_inc_wait_cnt_reg__0[0]),\n .I1(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I2(early2_data_reg_0),\n .I3(early1_data_reg_0),\n .I4(wrcal_pat_resume_r_reg_0),\n .I5(\\cal2_state_r[0]_i_4_n_0 ),\n .O(\\cal2_state_r[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h000F0000DFDFDFDF)) \n \\cal2_state_r[0]_i_3 \n (.I0(prech_done),\n .I1(\\cal2_state_r[0]_i_5_n_0 ),\n .I2(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I3(wrcal_done_reg_0),\n .I4(wrcal_pat_resume_r_reg_0),\n .I5(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .O(\\cal2_state_r[0]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair615\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\cal2_state_r[0]_i_4 \n (.I0(\\gen_pat_match_div4.pat_data_match_r_reg_n_0 ),\n .I1(idelay_ld_reg_0),\n .I2(wrcal_done_reg_0),\n .O(\\cal2_state_r[0]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair614\" *) \n LUT3 #(\n .INIT(8'hF7)) \n \\cal2_state_r[0]_i_5 \n (.I0(\\wrcal_dqs_cnt_r_reg_n_0_[1] ),\n .I1(\\wrcal_dqs_cnt_r_reg_n_0_[0] ),\n .I2(wrcal_dqs_cnt_r),\n .O(\\cal2_state_r[0]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h00E2FFFF00E20000)) \n \\cal2_state_r[1]_i_1 \n (.I0(\\cal2_state_r[1]_i_2_n_0 ),\n .I1(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I2(tap_inc_wait_cnt_reg__0[1]),\n .I3(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I4(\\not_empty_wait_cnt_reg[0]_0 [0]),\n .I5(\\cal2_state_r[1]_i_3_n_0 ),\n .O(\\cal2_state_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair615\" *) \n LUT5 #(\n .INIT(32'hFF003200)) \n \\cal2_state_r[1]_i_2 \n (.I0(early2_data_reg_0),\n .I1(wrcal_done_reg_0),\n .I2(early1_data_reg_0),\n .I3(idelay_ld_reg_0),\n .I4(\\gen_pat_match_div4.pat_data_match_r_reg_n_0 ),\n .O(\\cal2_state_r[1]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair616\" *) \n LUT5 #(\n .INIT(32'h0F0050D0)) \n \\cal2_state_r[1]_i_3 \n (.I0(prech_done),\n .I1(cal2_prech_req_r_i_3_n_0),\n .I2(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I3(wrcal_done_reg_0),\n .I4(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .O(\\cal2_state_r[1]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h4F4AFFFF4F4A0000)) \n \\cal2_state_r[2]_i_1 \n (.I0(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I1(tap_inc_wait_cnt_reg__0[2]),\n .I2(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I3(\\cal2_state_r[2]_i_2_n_0 ),\n .I4(\\not_empty_wait_cnt_reg[0]_0 [0]),\n .I5(\\cal2_state_r[2]_i_3_n_0 ),\n .O(\\cal2_state_r[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000010)) \n \\cal2_state_r[2]_i_2 \n (.I0(early2_data_reg_0),\n .I1(wrcal_done_reg_0),\n .I2(idelay_ld_reg_0),\n .I3(\\gen_pat_match_div4.pat_data_match_r_reg_n_0 ),\n .I4(early1_data_reg_0),\n .I5(wrcal_pat_resume_r_reg_0),\n .O(\\cal2_state_r[2]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair616\" *) \n LUT5 #(\n .INIT(32'h0F00D0D0)) \n \\cal2_state_r[2]_i_3 \n (.I0(prech_done),\n .I1(cal2_prech_req_r_i_3_n_0),\n .I2(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I3(wrcal_done_reg_0),\n .I4(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .O(\\cal2_state_r[2]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair612\" *) \n LUT4 #(\n .INIT(16'h8000)) \n \\cal2_state_r[3]_i_11 \n (.I0(\\not_empty_wait_cnt_reg_n_0_[2] ),\n .I1(\\not_empty_wait_cnt_reg_n_0_[1] ),\n .I2(\\not_empty_wait_cnt_reg_n_0_[0] ),\n .I3(\\not_empty_wait_cnt_reg_n_0_[3] ),\n .O(\\cal2_state_r[3]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'h00E2FFFF00E20000)) \n \\cal2_state_r[3]_i_3 \n (.I0(\\cal2_state_r[3]_i_6_n_0 ),\n .I1(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I2(tap_inc_wait_cnt_reg__0[3]),\n .I3(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I4(\\not_empty_wait_cnt_reg[0]_0 [0]),\n .I5(\\not_empty_wait_cnt_reg[0]_0 [3]),\n .O(\\cal2_state_r[3]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h45404F4F45404A4A)) \n \\cal2_state_r[3]_i_4 \n (.I0(\\not_empty_wait_cnt_reg[0]_0 [3]),\n .I1(\\cal2_state_r[3]_i_7_n_0 ),\n .I2(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I3(\\cal2_state_r[3]_i_8_n_0 ),\n .I4(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I5(wrcal_start_reg),\n .O(\\cal2_state_r[3]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h00000000EEE222E2)) \n \\cal2_state_r[3]_i_5 \n (.I0(\\cal2_state_r[3]_i_9_n_0 ),\n .I1(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I2(phy_rddata_en_r1_reg),\n .I3(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I4(\\cal2_state_r[3]_i_8_n_0 ),\n .I5(\\not_empty_wait_cnt_reg[0]_0 [3]),\n .O(\\cal2_state_r[3]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h00FF0010FFFFFFFF)) \n \\cal2_state_r[3]_i_6 \n (.I0(early2_data_reg_0),\n .I1(early1_data_reg_0),\n .I2(wrcal_pat_resume_r_reg_0),\n .I3(\\gen_pat_match_div4.pat_data_match_r_reg_n_0 ),\n .I4(wrcal_done_reg_0),\n .I5(idelay_ld_reg_0),\n .O(\\cal2_state_r[3]_i_6_n_0 ));\n LUT5 #(\n .INIT(32'h3B3B3808)) \n \\cal2_state_r[3]_i_7 \n (.I0(wrcal_sanity_chk),\n .I1(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I2(wrcal_done_reg_0),\n .I3(\\cal2_state_r[0]_i_5_n_0 ),\n .I4(prech_done),\n .O(\\cal2_state_r[3]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair627\" *) \n LUT4 #(\n .INIT(16'h8000)) \n \\cal2_state_r[3]_i_8 \n (.I0(tap_inc_wait_cnt_reg__0[2]),\n .I1(tap_inc_wait_cnt_reg__0[0]),\n .I2(tap_inc_wait_cnt_reg__0[1]),\n .I3(tap_inc_wait_cnt_reg__0[3]),\n .O(\\cal2_state_r[3]_i_8_n_0 ));\n LUT5 #(\n .INIT(32'hBBBBB888)) \n \\cal2_state_r[3]_i_9 \n (.I0(idelay_ld_done_reg_0),\n .I1(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I2(\\cal2_state_r[3]_i_11_n_0 ),\n .I3(\\not_empty_wait_cnt_reg_n_0_[4] ),\n .I4(idelay_ld_reg_0),\n .O(\\cal2_state_r[3]_i_9_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cal2_state_r_reg[0] \n (.C(CLK),\n .CE(cal2_state_r),\n .D(\\cal2_state_r[0]_i_1_n_0 ),\n .Q(\\not_empty_wait_cnt_reg[0]_0 [0]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\cal2_state_r_reg[1] \n (.C(CLK),\n .CE(cal2_state_r),\n .D(\\cal2_state_r[1]_i_1_n_0 ),\n .Q(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\cal2_state_r_reg[2] \n (.C(CLK),\n .CE(cal2_state_r),\n .D(\\cal2_state_r[2]_i_1_n_0 ),\n .Q(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE #(\n .INIT(1'b0)) \n \\cal2_state_r_reg[3] \n (.C(CLK),\n .CE(cal2_state_r),\n .D(\\cal2_state_r[3]_i_3_n_0 ),\n .Q(\\not_empty_wait_cnt_reg[0]_0 [3]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n MUXF7 \\cal2_state_r_reg[3]_i_2 \n (.I0(\\cal2_state_r[3]_i_4_n_0 ),\n .I1(\\cal2_state_r[3]_i_5_n_0 ),\n .O(cal2_state_r),\n .S(\\not_empty_wait_cnt_reg[0]_0 [0]));\n LUT2 #(\n .INIT(4'h1)) \n \\corse_cnt[0][2]_i_11 \n (.I0(\\idelay_tap_cnt_r_reg[0][2][0]_0 [0]),\n .I1(\\idelay_tap_cnt_r_reg[0][2][0]_0 [2]),\n .O(\\corse_cnt_reg[0][2] ));\n (* SOFT_HLUTNM = \"soft_lutpair622\" *) \n LUT4 #(\n .INIT(16'hFBFF)) \n \\corse_cnt[1][2]_i_5 \n (.I0(\\idelay_tap_cnt_r_reg[0][2][0]_0 [2]),\n .I1(wrlvl_byte_redo),\n .I2(wrlvl_byte_redo_r),\n .I3(\\idelay_tap_cnt_r_reg[0][2][0]_0 [0]),\n .O(\\corse_cnt_reg[1][2] ));\n (* SOFT_HLUTNM = \"soft_lutpair632\" *) \n LUT3 #(\n .INIT(8'hDF)) \n \\corse_cnt[2][2]_i_5 \n (.I0(\\idelay_tap_cnt_r_reg[0][2][0]_0 [1]),\n .I1(wrlvl_byte_redo_r),\n .I2(wrlvl_byte_redo),\n .O(\\corse_cnt_reg[2][2] ));\n LUT5 #(\n .INIT(32'h45400000)) \n early1_data_i_2\n (.I0(\\not_empty_wait_cnt_reg[0]_0 [3]),\n .I1(early1_data_i_3_n_0),\n .I2(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I3(wrlvl_byte_redo_i_3_n_0),\n .I4(\\not_empty_wait_cnt_reg[0]_0 [0]),\n .O(early1_data_reg_2));\n LUT4 #(\n .INIT(16'h0008)) \n early1_data_i_3\n (.I0(wrlvl_byte_done),\n .I1(rd_active_r1),\n .I2(phy_rddata_en_1),\n .I3(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .O(early1_data_i_3_n_0));\n FDRE #(\n .INIT(1'b0)) \n early1_data_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early1_data_match_r_reg_0 ),\n .Q(early1_data_reg_1),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE #(\n .INIT(1'b0)) \n early2_data_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early1_data_match_r_reg_1 ),\n .Q(early2_data_reg_1),\n .R(rstdiv0_sync_r1_reg_rep__2));\n LUT6 #(\n .INIT(64'h0CAA000000AA0000)) \n \\gen_byte_sel_div1.byte_sel_cnt[0]_i_3 \n (.I0(\\idelay_tap_cnt_r_reg[0][2][0]_0 [0]),\n .I1(rdlvl_stg1_done_int_reg),\n .I2(prbs_rdlvl_done_reg),\n .I3(wrcal_done_reg_1),\n .I4(oclkdelay_calib_done_r_reg),\n .I5(\\prbs_dqs_cnt_r_reg[0] ),\n .O(\\gen_byte_sel_div1.byte_sel_cnt_reg[0] ));\n LUT6 #(\n .INIT(64'h0CAA000000AA0000)) \n \\gen_byte_sel_div1.byte_sel_cnt[1]_i_3 \n (.I0(\\idelay_tap_cnt_r_reg[0][2][0]_0 [1]),\n .I1(rdlvl_stg1_done_int_reg),\n .I2(prbs_rdlvl_done_reg),\n .I3(wrcal_done_reg_1),\n .I4(oclkdelay_calib_done_r_reg),\n .I5(\\prbs_dqs_cnt_r_reg[1] ),\n .O(\\gen_byte_sel_div1.byte_sel_cnt_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair629\" *) \n LUT4 #(\n .INIT(16'h0800)) \n \\gen_byte_sel_div1.byte_sel_cnt[2]_i_6 \n (.I0(\\idelay_tap_cnt_r_reg[0][2][0]_0 [2]),\n .I1(mpr_rdlvl_done_r_reg),\n .I2(wrcal_done_reg_1),\n .I3(oclkdelay_calib_done_r_reg),\n .O(\\gen_byte_sel_div1.byte_sel_cnt_reg[2] ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_19 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_55 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_33 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_11 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_47 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_out),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_41 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_20 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_56 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_34 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_12 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_48 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_4 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_27 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_42 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_21 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_57 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_35 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_13 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_49 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_5 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_28 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_43 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_22 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_58 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_36 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_14 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_50 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_6 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_29 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_23 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_59 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_37 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_15 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_51 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_7 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_44 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_24 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_60 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_38 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_16 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_52 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_8 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_30 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_45 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_25 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_61 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_39 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_17 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_53 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_9 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_31 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_46 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_26 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_62 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_40 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_18 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_54 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_10 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_32 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_pat_match_div4.early1_data_match_r_i_1 \n (.I0(early1_match_rise2_and_r),\n .I1(early1_match_rise3_and_r),\n .I2(early1_match_fall1_and_r),\n .I3(early1_match_rise1_and_r),\n .I4(\\gen_pat_match_div4.early1_data_match_r_i_2_n_0 ),\n .O(early1_data_match_r0__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_pat_match_div4.early1_data_match_r_i_2 \n (.I0(early1_match_rise0_and_r),\n .I1(early1_match_fall3_and_r),\n .I2(early1_match_fall0_and_r),\n .I3(early1_match_fall2_and_r),\n .O(\\gen_pat_match_div4.early1_data_match_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.early1_data_match_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(early1_data_match_r0__0),\n .Q(early1_data_reg_0),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_pat_match_div4.early1_match_fall0_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[0].early1_match_fall0_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[6].early1_match_fall0_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[2].early1_match_fall0_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[4].early1_match_fall0_r_reg ),\n .I4(\\gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0 ),\n .O(\\gen_pat_match_div4.early1_match_fall0_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_pat_match_div4.early1_match_fall0_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r_reg ),\n .O(\\gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.early1_match_fall0_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early1_match_fall0_and_r_i_1_n_0 ),\n .Q(early1_match_fall0_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.early1_match_fall1_and_r_i_1 \n (.I0(\\gen_pat_match_div4.early1_match_fall1_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg__0 ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg__0 ),\n .I3(\\gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg ),\n .O(\\gen_pat_match_div4.early1_match_fall1_and_r_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair613\" *) \n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.early1_match_fall1_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].early1_match_fall1_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].early1_match_fall1_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r_reg ),\n .O(\\gen_pat_match_div4.early1_match_fall1_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.early1_match_fall1_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early1_match_fall1_and_r_i_1_n_0 ),\n .Q(early1_match_fall1_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.early1_match_fall2_and_r_i_1 \n (.I0(\\gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r_reg ),\n .O(\\gen_pat_match_div4.early1_match_fall2_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.early1_match_fall2_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg ),\n .O(\\gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.early1_match_fall2_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early1_match_fall2_and_r_i_1_n_0 ),\n .Q(early1_match_fall2_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.early1_match_fall3_and_r_i_1 \n (.I0(\\gen_pat_match_div4.early1_match_fall3_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg__0 ),\n .I3(\\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg__0 ),\n .I4(\\gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg ),\n .O(\\gen_pat_match_div4.early1_match_fall3_and_r_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair619\" *) \n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.early1_match_fall3_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg ),\n .O(\\gen_pat_match_div4.early1_match_fall3_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.early1_match_fall3_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early1_match_fall3_and_r_i_1_n_0 ),\n .Q(early1_match_fall3_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_pat_match_div4.early1_match_rise0_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r_reg__0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r_reg__0 ),\n .I2(\\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r_reg__0 ),\n .I3(\\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r_reg__0 ),\n .I4(\\gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0 ),\n .O(\\gen_pat_match_div4.early1_match_rise0_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_pat_match_div4.early1_match_rise0_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise0_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].pat_match_rise0_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].pat_match_rise0_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise0_r_reg ),\n .O(\\gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.early1_match_rise0_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early1_match_rise0_and_r_i_1_n_0 ),\n .Q(early1_match_rise0_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.early1_match_rise1_and_r_i_1 \n (.I0(\\gen_pat_match_div4.early1_match_rise1_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg__0 ),\n .I4(\\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg__0 ),\n .O(\\gen_pat_match_div4.early1_match_rise1_and_r_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair621\" *) \n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.early1_match_rise1_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[4].early1_match_rise1_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[0].early1_match_rise1_r_reg ),\n .O(\\gen_pat_match_div4.early1_match_rise1_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.early1_match_rise1_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early1_match_rise1_and_r_i_1_n_0 ),\n .Q(early1_match_rise1_and_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair617\" *) \n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.early1_match_rise2_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[3].early1_match_rise2_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[7].early1_match_rise2_r_reg ),\n .I4(\\gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0 ),\n .O(\\gen_pat_match_div4.early1_match_rise2_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.early1_match_rise2_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg ),\n .O(\\gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.early1_match_rise2_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early1_match_rise2_and_r_i_1_n_0 ),\n .Q(early1_match_rise2_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.early1_match_rise3_and_r_i_1 \n (.I0(\\gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].early1_match_rise3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].early1_match_rise3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg ),\n .O(\\gen_pat_match_div4.early1_match_rise3_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.early1_match_rise3_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg ),\n .O(\\gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.early1_match_rise3_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early1_match_rise3_and_r_i_1_n_0 ),\n .Q(early1_match_rise3_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_pat_match_div4.early2_data_match_r_i_1 \n (.I0(early2_match_fall0_and_r),\n .I1(early2_match_rise2_and_r),\n .I2(early2_match_fall3_and_r),\n .I3(early2_match_rise1_and_r),\n .I4(\\gen_pat_match_div4.early2_data_match_r_i_2_n_0 ),\n .O(early2_data_match_r0__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_pat_match_div4.early2_data_match_r_i_2 \n (.I0(early2_match_rise3_and_r),\n .I1(early2_match_fall2_and_r),\n .I2(early2_match_fall1_and_r),\n .I3(early2_match_rise0_and_r),\n .O(\\gen_pat_match_div4.early2_data_match_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.early2_data_match_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(early2_data_match_r0__0),\n .Q(early2_data_reg_0),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.early2_match_fall0_and_r_i_1 \n (.I0(\\gen_pat_match_div4.early2_match_fall0_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].early2_match_fall0_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[7].early2_match_fall0_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[3].early2_match_fall0_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[5].early2_match_fall0_r_reg ),\n .O(\\gen_pat_match_div4.early2_match_fall0_and_r_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair618\" *) \n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.early2_match_fall0_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r_reg ),\n .O(\\gen_pat_match_div4.early2_match_fall0_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.early2_match_fall0_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early2_match_fall0_and_r_i_1_n_0 ),\n .Q(early2_match_fall0_and_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair613\" *) \n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.early2_match_fall1_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[5].early1_match_fall1_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[1].early1_match_fall1_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r_reg ),\n .I4(\\gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0 ),\n .O(\\gen_pat_match_div4.early2_match_fall1_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.early2_match_fall1_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].pat_match_fall1_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[2].pat_match_fall1_r_reg ),\n .O(\\gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.early2_match_fall1_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early2_match_fall1_and_r_i_1_n_0 ),\n .Q(early2_match_fall1_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_pat_match_div4.early2_match_fall2_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r_reg__0 ),\n .I2(\\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[4].early2_match_fall2_r_reg ),\n .I4(\\gen_pat_match_div4.early2_match_fall2_and_r_i_2_n_0 ),\n .O(\\gen_pat_match_div4.early2_match_fall2_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_pat_match_div4.early2_match_fall2_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r_reg__0 ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[0].early2_match_fall2_r_reg ),\n .O(\\gen_pat_match_div4.early2_match_fall2_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.early2_match_fall2_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early2_match_fall2_and_r_i_1_n_0 ),\n .Q(early2_match_fall2_and_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair619\" *) \n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.early2_match_fall3_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r_reg ),\n .I4(\\gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0 ),\n .O(\\gen_pat_match_div4.early2_match_fall3_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.early2_match_fall3_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[2].pat_match_fall3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[6].pat_match_fall3_r_reg ),\n .O(\\gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.early2_match_fall3_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early2_match_fall3_and_r_i_1_n_0 ),\n .Q(early2_match_fall3_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.early2_match_rise0_and_r_i_1 \n (.I0(\\gen_pat_match_div4.early2_match_rise0_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r_reg__0 ),\n .I2(\\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r_reg__0 ),\n .I3(\\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r_reg__0 ),\n .I4(\\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r_reg__0 ),\n .O(\\gen_pat_match_div4.early2_match_rise0_and_r_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair611\" *) \n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.early2_match_rise0_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise0_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[2].pat_match_rise0_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].pat_match_rise0_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise0_r_reg ),\n .O(\\gen_pat_match_div4.early2_match_rise0_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.early2_match_rise0_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early2_match_rise0_and_r_i_1_n_0 ),\n .Q(early2_match_rise0_and_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair621\" *) \n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.early2_match_rise1_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[0].early1_match_rise1_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[4].early1_match_rise1_r_reg ),\n .I4(\\gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0 ),\n .O(\\gen_pat_match_div4.early2_match_rise1_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.early2_match_rise1_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise1_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise1_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r_reg ),\n .O(\\gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.early2_match_rise1_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early2_match_rise1_and_r_i_1_n_0 ),\n .Q(early2_match_rise1_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.early2_match_rise2_and_r_i_1 \n (.I0(\\gen_pat_match_div4.early2_match_rise2_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[1].early2_match_rise2_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[5].early2_match_rise2_r_reg ),\n .O(\\gen_pat_match_div4.early2_match_rise2_and_r_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair617\" *) \n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.early2_match_rise2_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[7].early1_match_rise2_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[3].early1_match_rise2_r_reg ),\n .O(\\gen_pat_match_div4.early2_match_rise2_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.early2_match_rise2_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early2_match_rise2_and_r_i_1_n_0 ),\n .Q(early2_match_rise2_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_pat_match_div4.early2_match_rise3_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[2].early2_match_rise3_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].early1_match_rise3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r_reg__0 ),\n .I4(\\gen_pat_match_div4.early2_match_rise3_and_r_i_2_n_0 ),\n .O(\\gen_pat_match_div4.early2_match_rise3_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_pat_match_div4.early2_match_rise3_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r_reg__0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].early1_match_rise3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[6].early2_match_rise3_r_reg ),\n .O(\\gen_pat_match_div4.early2_match_rise3_and_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.early2_match_rise3_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early2_match_rise3_and_r_i_1_n_0 ),\n .Q(early2_match_rise3_and_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[0].early1_match_fall0_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].early1_match_fall0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[0].early1_match_rise1_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].early1_match_rise1_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[0].early2_match_fall2_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].early2_match_fall2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise0_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[1].early1_match_fall1_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].early1_match_fall1_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[1].early1_match_rise3_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].early1_match_rise3_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[1].early2_match_fall0_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].early2_match_fall0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[1].early2_match_rise2_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].early2_match_rise2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[1].pat_match_rise0_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].pat_match_rise0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[2].early1_match_fall0_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].early1_match_fall0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[2].early2_match_rise3_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].early2_match_rise3_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[2].pat_match_fall1_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].pat_match_fall1_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[2].pat_match_fall3_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].pat_match_fall3_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[2].pat_match_rise0_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].pat_match_rise0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[3].early1_match_rise2_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].early1_match_rise2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[3].early2_match_fall0_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].early2_match_fall0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise0_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise1_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise1_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[4].early1_match_fall0_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].early1_match_fall0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[4].early1_match_rise1_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].early1_match_rise1_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[4].early2_match_fall2_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].early2_match_fall2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise0_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[5].early1_match_fall1_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].early1_match_fall1_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[5].early1_match_rise3_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].early1_match_rise3_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[5].early2_match_fall0_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].early2_match_fall0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[5].early2_match_rise2_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].early2_match_rise2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[5].pat_match_rise0_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].pat_match_rise0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[6].early1_match_fall0_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].early1_match_fall0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[6].early2_match_rise3_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].early2_match_rise3_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[6].pat_match_fall1_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].pat_match_fall1_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[6].pat_match_fall3_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].pat_match_fall3_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[6].pat_match_rise0_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].pat_match_rise0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[7].early1_match_rise2_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].early1_match_rise2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[7].early2_match_fall0_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].early2_match_fall0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise0_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise0_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise1_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise1_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg__0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_pat_match_div4.pat_data_match_r_i_1 \n (.I0(pat_match_rise0_and_r),\n .I1(pat_match_rise3_and_r),\n .I2(pat_match_fall2_and_r),\n .I3(pat_match_fall3_and_r),\n .I4(\\gen_pat_match_div4.pat_data_match_r_i_2_n_0 ),\n .O(pat_data_match_r0__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_pat_match_div4.pat_data_match_r_i_2 \n (.I0(pat_match_fall0_and_r),\n .I1(pat_match_rise2_and_r),\n .I2(pat_match_rise1_and_r),\n .I3(pat_match_fall1_and_r),\n .O(\\gen_pat_match_div4.pat_data_match_r_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.pat_data_match_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(pat_data_match_r0__0),\n .Q(\\gen_pat_match_div4.pat_data_match_r_reg_n_0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.pat_data_match_valid_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(rd_active_r3),\n .Q(idelay_ld_reg_0),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair618\" *) \n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_pat_match_div4.pat_match_fall0_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r_reg ),\n .I4(\\gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0 ),\n .O(\\gen_pat_match_div4.pat_match_fall0_and_r_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.pat_match_fall0_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat_match_fall0_and_r_i_1_n_0 ),\n .Q(pat_match_fall0_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.pat_match_fall1_and_r_i_1 \n (.I0(\\gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg__0 ),\n .I3(\\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg__0 ),\n .I4(\\gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg ),\n .O(\\gen_pat_match_div4.pat_match_fall1_and_r_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.pat_match_fall1_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat_match_fall1_and_r_i_1_n_0 ),\n .Q(pat_match_fall1_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.pat_match_fall2_and_r_i_1 \n (.I0(\\gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r_reg ),\n .O(\\gen_pat_match_div4.pat_match_fall2_and_r_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.pat_match_fall2_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat_match_fall2_and_r_i_1_n_0 ),\n .Q(pat_match_fall2_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.pat_match_fall3_and_r_i_1 \n (.I0(\\gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg ),\n .O(\\gen_pat_match_div4.pat_match_fall3_and_r_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.pat_match_fall3_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat_match_fall3_and_r_i_1_n_0 ),\n .Q(pat_match_fall3_and_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair611\" *) \n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_pat_match_div4.pat_match_rise0_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise0_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[6].pat_match_rise0_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[2].pat_match_rise0_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise0_r_reg ),\n .I4(\\gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0 ),\n .O(\\gen_pat_match_div4.pat_match_rise0_and_r_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.pat_match_rise0_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat_match_rise0_and_r_i_1_n_0 ),\n .Q(pat_match_rise0_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.pat_match_rise1_and_r_i_1 \n (.I0(\\gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg__0 ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg__0 ),\n .O(\\gen_pat_match_div4.pat_match_rise1_and_r_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.pat_match_rise1_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat_match_rise1_and_r_i_1_n_0 ),\n .Q(pat_match_rise1_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.pat_match_rise2_and_r_i_1 \n (.I0(\\gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg__0 ),\n .I4(\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg__0 ),\n .O(\\gen_pat_match_div4.pat_match_rise2_and_r_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.pat_match_rise2_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat_match_rise2_and_r_i_1_n_0 ),\n .Q(pat_match_rise2_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.pat_match_rise3_and_r_i_1 \n (.I0(\\gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg__0 ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg__0 ),\n .I3(\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg ),\n .O(\\gen_pat_match_div4.pat_match_rise3_and_r_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_pat_match_div4.pat_match_rise3_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat_match_rise3_and_r_i_1_n_0 ),\n .Q(pat_match_rise3_and_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ),\n .Q(\\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ),\n .Q(\\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ),\n .Q(\\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ),\n .Q(\\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ),\n .Q(\\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ),\n .Q(\\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 ),\n .R(1'b0));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2 \" *) \n SRL16E #(\n .INIT(16'h0000)) \n \\gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2 \n (.A0(1'b1),\n .A1(1'b0),\n .A2(1'b0),\n .A3(1'b0),\n .CE(1'b1),\n .CLK(CLK),\n .D(\\po_stg2_wrcal_cnt_reg[1]_0 ),\n .Q(\\gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ),\n .Q(\\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ),\n .Q(\\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ),\n .Q(\\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ),\n .Q(\\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ),\n .Q(\\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ),\n .Q(\\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ),\n .Q(\\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ),\n .Q(\\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ),\n .Q(\\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ),\n .Q(\\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ),\n .Q(\\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ),\n .Q(\\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ),\n .Q(\\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ),\n .Q(\\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ),\n .Q(\\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ),\n .Q(\\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ),\n .Q(\\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ),\n .Q(\\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ),\n .Q(\\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ),\n .Q(\\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ),\n .Q(\\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_208 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ),\n .Q(\\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ),\n .Q(\\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ),\n .Q(\\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 ),\n .R(1'b0));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2 \" *) \n SRL16E #(\n .INIT(16'h0000)) \n \\gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2 \n (.A0(1'b1),\n .A1(1'b0),\n .A2(1'b0),\n .A3(1'b0),\n .CE(1'b1),\n .CLK(CLK),\n .D(\\po_stg2_wrcal_cnt_reg[1]_2 ),\n .Q(\\gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ),\n .Q(\\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ),\n .Q(\\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ),\n .Q(\\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ),\n .Q(\\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ),\n .Q(\\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ),\n .Q(\\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 ),\n .R(1'b0));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2 \" *) \n SRL16E #(\n .INIT(16'h0000)) \n \\gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2 \n (.A0(1'b1),\n .A1(1'b0),\n .A2(1'b0),\n .A3(1'b0),\n .CE(1'b1),\n .CLK(CLK),\n .D(\\po_stg2_wrcal_cnt_reg[1]_1 ),\n .Q(\\gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ),\n .Q(\\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ),\n .Q(\\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ),\n .Q(\\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ),\n .Q(\\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ),\n .Q(\\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ),\n .Q(\\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ),\n .Q(\\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ),\n .Q(\\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ),\n .Q(\\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ),\n .Q(\\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ),\n .Q(\\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ),\n .Q(\\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ),\n .Q(\\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ),\n .Q(\\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ),\n .Q(\\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ),\n .Q(\\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ),\n .Q(\\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ),\n .Q(\\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ),\n .Q(\\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ),\n .Q(\\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ),\n .Q(\\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_212 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ),\n .Q(\\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ),\n .Q(\\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ),\n .Q(\\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 ),\n .R(1'b0));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2 \" *) \n SRL16E #(\n .INIT(16'h0000)) \n \\gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2 \n (.A0(1'b1),\n .A1(1'b0),\n .A2(1'b0),\n .A3(1'b0),\n .CE(1'b1),\n .CLK(CLK),\n .D(\\po_stg2_wrcal_cnt_reg[1]_3 ),\n .Q(\\gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair625\" *) \n LUT4 #(\n .INIT(16'h0002)) \n idelay_ld_done_i_2\n (.I0(tap_inc_wait_cnt_reg__0[2]),\n .I1(tap_inc_wait_cnt_reg__0[0]),\n .I2(tap_inc_wait_cnt_reg__0[1]),\n .I3(tap_inc_wait_cnt_reg__0[3]),\n .O(idelay_ld_done_reg_0));\n FDRE #(\n .INIT(1'b0)) \n idelay_ld_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\cal2_state_r_reg[0]_0 ),\n .Q(wrcal_pat_resume_r_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__4));\n LUT6 #(\n .INIT(64'h0000540400000000)) \n idelay_ld_i_2\n (.I0(\\not_empty_wait_cnt_reg[0]_0 [3]),\n .I1(\\cal2_state_r[2]_i_2_n_0 ),\n .I2(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I3(idelay_ld_done_reg_0),\n .I4(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I5(\\not_empty_wait_cnt_reg[0]_0 [0]),\n .O(idelay_ld_reg_1));\n FDRE #(\n .INIT(1'b0)) \n idelay_ld_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat_data_match_valid_r_reg_0 ),\n .Q(idelay_ld),\n .R(rstdiv0_sync_r1_reg_rep__5));\n (* SOFT_HLUTNM = \"soft_lutpair624\" *) \n LUT4 #(\n .INIT(16'hFFEF)) \n \\idelay_tap_cnt_r[0][0][4]_i_3 \n (.I0(\\idelay_tap_cnt_r_reg[0][2][0]_0 [0]),\n .I1(idelay_ce_int),\n .I2(idelay_ld),\n .I3(\\idelay_tap_cnt_r_reg[0][2][0]_0 [2]),\n .O(\\idelay_tap_cnt_r_reg[0][2][0] ));\n (* SOFT_HLUTNM = \"soft_lutpair624\" *) \n LUT4 #(\n .INIT(16'hFBFF)) \n \\idelay_tap_cnt_r[0][1][4]_i_2 \n (.I0(idelay_ce_int),\n .I1(idelay_ld),\n .I2(\\idelay_tap_cnt_r_reg[0][2][0]_0 [2]),\n .I3(\\idelay_tap_cnt_r_reg[0][2][0]_0 [0]),\n .O(\\idelay_tap_cnt_r_reg[0][1][0] ));\n LUT6 #(\n .INIT(64'h5555555545555555)) \n \\init_state_r[0]_i_12 \n (.I0(wrcal_sanity_chk_done_reg_0),\n .I1(prbs_rdlvl_done_reg_rep_0),\n .I2(wrlvl_done_r1),\n .I3(dqs_found_done_r_reg),\n .I4(wrcal_done_reg_1),\n .I5(ddr3_lm_done_r),\n .O(\\init_state_r_reg[0]_2 ));\n LUT6 #(\n .INIT(64'h5700575757575757)) \n \\init_state_r[0]_i_36 \n (.I0(oclkdelay_calib_done_r_reg_0),\n .I1(wrlvl_final_mux),\n .I2(wrlvl_byte_redo),\n .I3(mem_init_done_r),\n .I4(\\init_state_r_reg[2] ),\n .I5(dqs_found_done_r_reg_0),\n .O(\\init_state_r_reg[0] ));\n LUT6 #(\n .INIT(64'h00D000D000D0FFFF)) \n \\init_state_r[0]_i_55 \n (.I0(prbs_rdlvl_done_reg_rep),\n .I1(\\init_state_r[0]_i_56_n_0 ),\n .I2(wrlvl_done_r1),\n .I3(wrlvl_byte_redo),\n .I4(rdlvl_stg1_done_int_reg_0),\n .I5(dqs_found_done_r_reg),\n .O(\\init_state_r_reg[0]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair623\" *) \n LUT2 #(\n .INIT(4'h7)) \n \\init_state_r[0]_i_56 \n (.I0(wrcal_done_reg_1),\n .I1(rdlvl_stg1_done_int_reg),\n .O(\\init_state_r[0]_i_56_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair626\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\init_state_r[2]_i_23 \n (.I0(wrcal_done_reg_1),\n .I1(prech_req_posedge_r_reg),\n .I2(wrlvl_byte_redo),\n .I3(wrcal_resume_r),\n .O(\\init_state_r_reg[0]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair623\" *) \n LUT4 #(\n .INIT(16'hB0BB)) \n \\init_state_r[2]_i_29 \n (.I0(wrlvl_done_r1),\n .I1(wrlvl_final_mux),\n .I2(wrcal_done_reg_1),\n .I3(wrlvl_byte_redo),\n .O(\\init_state_r_reg[2] ));\n LUT3 #(\n .INIT(8'h08)) \n \\init_state_r[3]_i_12 \n (.I0(wrcal_done_reg_1),\n .I1(dqs_found_done_r_reg),\n .I2(rdlvl_stg1_start_int_reg),\n .O(\\init_state_r_reg[3] ));\n LUT6 #(\n .INIT(64'h2FAF2FAF2FAF0000)) \n \\init_state_r[4]_i_23 \n (.I0(\\init_state_r[4]_i_34_n_0 ),\n .I1(mem_init_done_r),\n .I2(oclkdelay_calib_done_r_reg),\n .I3(wrcal_done_reg_1),\n .I4(mpr_rdlvl_done_r_reg),\n .I5(mpr_last_byte_done),\n .O(\\init_state_r_reg[4] ));\n LUT6 #(\n .INIT(64'hB010000000000000)) \n \\init_state_r[4]_i_34 \n (.I0(rdlvl_stg1_done_int_reg),\n .I1(wrcal_done_reg_1),\n .I2(dqs_found_done_r_reg),\n .I3(prbs_rdlvl_done_reg_rep),\n .I4(\\init_state_r_reg[2] ),\n .I5(dqs_found_done_r_reg_0),\n .O(\\init_state_r[4]_i_34_n_0 ));\n LUT6 #(\n .INIT(64'hFFFBFFFBFF00FFFB)) \n \\init_state_r[5]_i_28 \n (.I0(wrlvl_byte_redo),\n .I1(dqs_found_done_r_reg),\n .I2(wrlvl_final_mux),\n .I3(wrlvl_done_r1),\n .I4(oclkdelay_center_calib_done_r_reg),\n .I5(prbs_rdlvl_done_reg_rep_0),\n .O(\\init_state_r_reg[5] ));\n LUT6 #(\n .INIT(64'hFFFFFFFF44440004)) \n \\input_[0].iserdes_dq_.idelay_finedelay_dq.idelaye2_i_2 \n (.I0(Q),\n .I1(idelay_ld),\n .I2(\\calib_sel_reg[1] [0]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(calib_in_common),\n .I5(idelay_ld_rst),\n .O(LD0));\n LUT6 #(\n .INIT(64'hFFFFFFFF44440040)) \n \\input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_i_2 \n (.I0(Q),\n .I1(idelay_ld),\n .I2(\\calib_sel_reg[1] [0]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(calib_in_common),\n .I5(idelay_ld_rst_3),\n .O(LD0_0));\n LUT6 #(\n .INIT(64'hFFFFFFFF44440040)) \n \\input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_i_2__0 \n (.I0(Q),\n .I1(idelay_ld),\n .I2(\\calib_sel_reg[1] [1]),\n .I3(\\calib_sel_reg[1] [0]),\n .I4(calib_in_common),\n .I5(idelay_ld_rst_4),\n .O(LD0_1));\n LUT6 #(\n .INIT(64'hFFFFFFFF44444000)) \n \\input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_i_2__1 \n (.I0(Q),\n .I1(idelay_ld),\n .I2(\\calib_sel_reg[1] [0]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(calib_in_common),\n .I5(idelay_ld_rst_5),\n .O(LD0_2));\n (* SOFT_HLUTNM = \"soft_lutpair633\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\not_empty_wait_cnt[0]_i_1 \n (.I0(\\not_empty_wait_cnt_reg_n_0_[0] ),\n .O(p_0_in[0]));\n (* SOFT_HLUTNM = \"soft_lutpair633\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\not_empty_wait_cnt[1]_i_1 \n (.I0(\\not_empty_wait_cnt_reg_n_0_[0] ),\n .I1(\\not_empty_wait_cnt_reg_n_0_[1] ),\n .O(p_0_in[1]));\n (* SOFT_HLUTNM = \"soft_lutpair628\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\not_empty_wait_cnt[2]_i_1 \n (.I0(\\not_empty_wait_cnt_reg_n_0_[2] ),\n .I1(\\not_empty_wait_cnt_reg_n_0_[1] ),\n .I2(\\not_empty_wait_cnt_reg_n_0_[0] ),\n .O(p_0_in[2]));\n (* SOFT_HLUTNM = \"soft_lutpair628\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\not_empty_wait_cnt[3]_i_1 \n (.I0(\\not_empty_wait_cnt_reg_n_0_[3] ),\n .I1(\\not_empty_wait_cnt_reg_n_0_[0] ),\n .I2(\\not_empty_wait_cnt_reg_n_0_[1] ),\n .I3(\\not_empty_wait_cnt_reg_n_0_[2] ),\n .O(p_0_in[3]));\n LUT6 #(\n .INIT(64'hFFFEFFFFFFFFFFFF)) \n \\not_empty_wait_cnt[4]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__22),\n .I1(\\not_empty_wait_cnt_reg[0]_0 [3]),\n .I2(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I3(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I4(\\not_empty_wait_cnt_reg[0]_0 [0]),\n .I5(wrcal_rd_wait),\n .O(\\not_empty_wait_cnt[4]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair612\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\not_empty_wait_cnt[4]_i_2 \n (.I0(\\not_empty_wait_cnt_reg_n_0_[4] ),\n .I1(\\not_empty_wait_cnt_reg_n_0_[2] ),\n .I2(\\not_empty_wait_cnt_reg_n_0_[1] ),\n .I3(\\not_empty_wait_cnt_reg_n_0_[0] ),\n .I4(\\not_empty_wait_cnt_reg_n_0_[3] ),\n .O(p_0_in[4]));\n FDRE #(\n .INIT(1'b0)) \n \\not_empty_wait_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in[0]),\n .Q(\\not_empty_wait_cnt_reg_n_0_[0] ),\n .R(\\not_empty_wait_cnt[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\not_empty_wait_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in[1]),\n .Q(\\not_empty_wait_cnt_reg_n_0_[1] ),\n .R(\\not_empty_wait_cnt[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\not_empty_wait_cnt_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in[2]),\n .Q(\\not_empty_wait_cnt_reg_n_0_[2] ),\n .R(\\not_empty_wait_cnt[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\not_empty_wait_cnt_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in[3]),\n .Q(\\not_empty_wait_cnt_reg_n_0_[3] ),\n .R(\\not_empty_wait_cnt[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\not_empty_wait_cnt_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in[4]),\n .Q(\\not_empty_wait_cnt_reg_n_0_[4] ),\n .R(\\not_empty_wait_cnt[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\po_stg2_wrcal_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wrcal_dqs_cnt_r_reg_n_0_[0] ),\n .Q(\\idelay_tap_cnt_r_reg[0][2][0]_0 [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\po_stg2_wrcal_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wrcal_dqs_cnt_r_reg_n_0_[1] ),\n .Q(\\idelay_tap_cnt_r_reg[0][2][0]_0 [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\po_stg2_wrcal_cnt_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(wrcal_dqs_cnt_r),\n .Q(\\idelay_tap_cnt_r_reg[0][2][0]_0 [2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n rd_active_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(phy_rddata_en_1),\n .Q(rd_active_r1),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n rd_active_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rd_active_r1),\n .Q(rd_active_r2),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n rd_active_r3_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rd_active_r2),\n .Q(rd_active_r3),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair634\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\tap_inc_wait_cnt[0]_i_1 \n (.I0(tap_inc_wait_cnt_reg__0[0]),\n .O(p_0_in__0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair634\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\tap_inc_wait_cnt[1]_i_1 \n (.I0(tap_inc_wait_cnt_reg__0[1]),\n .I1(tap_inc_wait_cnt_reg__0[0]),\n .O(p_0_in__0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair627\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\tap_inc_wait_cnt[2]_i_1 \n (.I0(tap_inc_wait_cnt_reg__0[2]),\n .I1(tap_inc_wait_cnt_reg__0[0]),\n .I2(tap_inc_wait_cnt_reg__0[1]),\n .O(p_0_in__0[2]));\n LUT5 #(\n .INIT(32'hFFFFAFEF)) \n \\tap_inc_wait_cnt[3]_i_1 \n (.I0(\\not_empty_wait_cnt_reg[0]_0 [3]),\n .I1(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I2(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I3(\\not_empty_wait_cnt_reg[0]_0 [0]),\n .I4(rstdiv0_sync_r1_reg_rep__22),\n .O(\\tap_inc_wait_cnt[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair625\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\tap_inc_wait_cnt[3]_i_2 \n (.I0(tap_inc_wait_cnt_reg__0[3]),\n .I1(tap_inc_wait_cnt_reg__0[1]),\n .I2(tap_inc_wait_cnt_reg__0[0]),\n .I3(tap_inc_wait_cnt_reg__0[2]),\n .O(p_0_in__0[3]));\n FDRE #(\n .INIT(1'b0)) \n \\tap_inc_wait_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0[0]),\n .Q(tap_inc_wait_cnt_reg__0[0]),\n .R(\\tap_inc_wait_cnt[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\tap_inc_wait_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0[1]),\n .Q(tap_inc_wait_cnt_reg__0[1]),\n .R(\\tap_inc_wait_cnt[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\tap_inc_wait_cnt_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0[2]),\n .Q(tap_inc_wait_cnt_reg__0[2]),\n .R(\\tap_inc_wait_cnt[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\tap_inc_wait_cnt_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0[3]),\n .Q(tap_inc_wait_cnt_reg__0[3]),\n .R(\\tap_inc_wait_cnt[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair622\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\wl_tap_count_r[5]_i_3 \n (.I0(wrlvl_byte_redo),\n .I1(wrlvl_byte_redo_r),\n .O(done_dqs_dec239_out));\n LUT5 #(\n .INIT(32'h0E0E000E)) \n wrcal_done_i_1\n (.I0(wrcal_done_reg_1),\n .I1(cal2_done_r),\n .I2(rstdiv0_sync_r1_reg_rep__22),\n .I3(wrcal_sanity_chk),\n .I4(wrcal_done_reg_0),\n .O(wrcal_done_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n wrcal_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrcal_done_i_1_n_0),\n .Q(wrcal_done_reg_1),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair631\" *) \n LUT3 #(\n .INIT(8'h34)) \n \\wrcal_dqs_cnt_r[0]_i_1 \n (.I0(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I1(\\wrcal_dqs_cnt_r[2]_i_2_n_0 ),\n .I2(\\wrcal_dqs_cnt_r_reg_n_0_[0] ),\n .O(\\wrcal_dqs_cnt_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair620\" *) \n LUT4 #(\n .INIT(16'h1F20)) \n \\wrcal_dqs_cnt_r[1]_i_1 \n (.I0(\\wrcal_dqs_cnt_r_reg_n_0_[0] ),\n .I1(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I2(\\wrcal_dqs_cnt_r[2]_i_2_n_0 ),\n .I3(\\wrcal_dqs_cnt_r_reg_n_0_[1] ),\n .O(\\wrcal_dqs_cnt_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair620\" *) \n LUT5 #(\n .INIT(32'h07FF0800)) \n \\wrcal_dqs_cnt_r[2]_i_1 \n (.I0(\\wrcal_dqs_cnt_r_reg_n_0_[1] ),\n .I1(\\wrcal_dqs_cnt_r_reg_n_0_[0] ),\n .I2(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I3(\\wrcal_dqs_cnt_r[2]_i_2_n_0 ),\n .I4(wrcal_dqs_cnt_r),\n .O(\\wrcal_dqs_cnt_r[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000054040000)) \n \\wrcal_dqs_cnt_r[2]_i_2 \n (.I0(\\not_empty_wait_cnt_reg[0]_0 [3]),\n .I1(\\wrcal_dqs_cnt_r[2]_i_3_n_0 ),\n .I2(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I3(wrcal_sanity_chk_reg),\n .I4(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I5(\\not_empty_wait_cnt_reg[0]_0 [0]),\n .O(\\wrcal_dqs_cnt_r[2]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair614\" *) \n LUT5 #(\n .INIT(32'hCFFF8AAA)) \n \\wrcal_dqs_cnt_r[2]_i_3 \n (.I0(prech_done),\n .I1(wrcal_dqs_cnt_r),\n .I2(\\wrcal_dqs_cnt_r_reg_n_0_[0] ),\n .I3(\\wrcal_dqs_cnt_r_reg_n_0_[1] ),\n .I4(wrcal_done_reg_0),\n .O(\\wrcal_dqs_cnt_r[2]_i_3_n_0 ));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wrcal_dqs_cnt_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wrcal_dqs_cnt_r[0]_i_1_n_0 ),\n .Q(\\wrcal_dqs_cnt_r_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__2));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wrcal_dqs_cnt_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wrcal_dqs_cnt_r[1]_i_1_n_0 ),\n .Q(\\wrcal_dqs_cnt_r_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__2));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\wrcal_dqs_cnt_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wrcal_dqs_cnt_r[2]_i_1_n_0 ),\n .Q(wrcal_dqs_cnt_r),\n .R(rstdiv0_sync_r1_reg_rep__2));\n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/wrcal_pat_resume_r2_reg_srl2 \" *) \n SRL16E #(\n .INIT(16'h0000)) \n wrcal_pat_resume_r2_reg_srl2\n (.A0(1'b1),\n .A1(1'b0),\n .A2(1'b0),\n .A3(1'b0),\n .CE(1'b1),\n .CLK(CLK),\n .D(wrcal_pat_resume_r),\n .Q(wrcal_pat_resume_r2_reg_srl2_n_0));\n LUT6 #(\n .INIT(64'h08000800033C003C)) \n wrcal_pat_resume_r_i_2\n (.I0(\\cal2_state_r[3]_i_8_n_0 ),\n .I1(\\not_empty_wait_cnt_reg[0]_0 [0]),\n .I2(\\not_empty_wait_cnt_reg[0]_0 [3]),\n .I3(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I4(wrcal_pat_resume_r_i_3_n_0),\n .I5(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .O(wrcal_pat_resume_r_reg_1));\n LUT6 #(\n .INIT(64'h0000800000000000)) \n wrcal_pat_resume_r_i_3\n (.I0(wrcal_pat_resume_r_reg_0),\n .I1(tap_inc_wait_cnt_reg__0[2]),\n .I2(tap_inc_wait_cnt_reg__0[0]),\n .I3(tap_inc_wait_cnt_reg__0[1]),\n .I4(wrcal_done_reg_0),\n .I5(tap_inc_wait_cnt_reg__0[3]),\n .O(wrcal_pat_resume_r_i_3_n_0));\n FDRE #(\n .INIT(1'b0)) \n wrcal_pat_resume_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\cal2_state_r_reg[2]_0 ),\n .Q(wrcal_pat_resume_r),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE #(\n .INIT(1'b0)) \n wrcal_pat_resume_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrcal_pat_resume_r2_reg_srl2_n_0),\n .Q(wrcal_resume_w),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n wrcal_prech_req_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cal2_prech_req_r),\n .Q(wrcal_prech_req),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE #(\n .INIT(1'b0)) \n wrcal_sanity_chk_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\cal2_state_r_reg[3]_0 ),\n .Q(wrcal_sanity_chk_done_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE #(\n .INIT(1'b0)) \n wrcal_sanity_chk_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrcal_sanity_chk),\n .Q(wrcal_done_reg_0),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair630\" *) \n LUT3 #(\n .INIT(8'h1F)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[156]_i_1 \n (.I0(wrcal_done_reg_1),\n .I1(first_wrcal_pat_r),\n .I2(oclkdelay_calib_done_r_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] ));\n (* SOFT_HLUTNM = \"soft_lutpair630\" *) \n LUT3 #(\n .INIT(8'h7F)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[191]_i_1 \n (.I0(wrcal_done_reg_1),\n .I1(oclkdelay_calib_done_r_reg),\n .I2(rdlvl_stg1_done_int_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] ));\n (* SOFT_HLUTNM = \"soft_lutpair626\" *) \n LUT2 #(\n .INIT(4'h7)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[221]_i_1 \n (.I0(wrcal_done_reg_1),\n .I1(oclkdelay_calib_done_r_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] ));\n (* SOFT_HLUTNM = \"soft_lutpair629\" *) \n LUT3 #(\n .INIT(8'h2F)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[223]_i_1 \n (.I0(wrcal_done_reg_1),\n .I1(rdlvl_stg1_done_int_reg),\n .I2(oclkdelay_calib_done_r_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] ));\n FDRE #(\n .INIT(1'b0)) \n wrlvl_byte_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrlvl_byte_done),\n .Q(wrlvl_byte_done_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0000000022222E22)) \n wrlvl_byte_redo_i_2\n (.I0(wrlvl_byte_redo_i_3_n_0),\n .I1(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I2(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I3(wrlvl_byte_done),\n .I4(wrlvl_byte_done_r),\n .I5(\\not_empty_wait_cnt_reg[0]_0 [3]),\n .O(wrlvl_byte_redo_reg_0));\n LUT6 #(\n .INIT(64'h0000000000300020)) \n wrlvl_byte_redo_i_3\n (.I0(early1_data_reg_0),\n .I1(\\gen_pat_match_div4.pat_data_match_r_reg_n_0 ),\n .I2(idelay_ld_reg_0),\n .I3(wrcal_done_reg_0),\n .I4(early2_data_reg_0),\n .I5(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .O(wrlvl_byte_redo_i_3_n_0));\n FDRE #(\n .INIT(1'b0)) \n wrlvl_byte_redo_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early2_data_match_r_reg_0 ),\n .Q(wrlvl_byte_redo),\n .R(rstdiv0_sync_r1_reg_rep__6));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_phy_wrlvl\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_phy_wrlvl\n (wr_level_done_r1_reg_0,\n wrlvl_byte_redo_r,\n wrlvl_final_r,\n dqs_po_dec_done,\n dqs_po_stg2_f_incdec,\n dqs_po_en_stg2_f,\n dqs_wl_po_stg2_c_incdec,\n \\rd_data_edge_detect_r_reg[0]_0 ,\n \\FSM_sequential_wl_state_r_reg[0]_0 ,\n p_0_in,\n \\rd_data_edge_detect_r_reg[0]_1 ,\n dqs_po_en_stg2_f_reg_0,\n wrlvl_done_r_reg,\n wrlvl_rank_done,\n D,\n \\stg2_target_r_reg[4] ,\n \\stg2_r_reg[4] ,\n \\stg3_dec_val_reg[2] ,\n \\stg2_r_reg[5] ,\n out,\n stable_cnt227_in,\n \\stg3_dec_val_reg[2]_0 ,\n \\lim_state_reg[12] ,\n \\stg2_r_reg[0] ,\n \\po_rdval_cnt_reg[0]_0 ,\n flag_ck_negedge09_out,\n \\stable_cnt_reg[3]_0 ,\n \\rank_cnt_r_reg[0]_0 ,\n \\rank_cnt_r_reg[0]_1 ,\n stable_cnt1,\n \\wrlvl_redo_corse_inc_reg[2]_0 ,\n po_cnt_dec_reg_0,\n flag_ck_negedge_reg_0,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[1] ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[2] ,\n p_1_in,\n wrlvl_byte_done,\n done_dqs_tap_inc,\n wr_level_done_r_reg_0,\n wrlvl_rank_done_r_reg_0,\n dq_cnt_inc_reg_0,\n inhibit_edge_detect_r,\n inhibit_edge_detect_r_reg_0,\n \\mcGo_r_reg[15] ,\n CLK,\n wrlvl_byte_redo,\n wrlvl_final_mux,\n wr_lvl_start_reg,\n rstdiv0_sync_r1_reg_rep__17,\n SR,\n flag_ck_negedge_reg_1,\n \\FSM_sequential_wl_state_r_reg[2]_0 ,\n \\FSM_sequential_wl_state_r_reg[0]_1 ,\n \\FSM_sequential_wl_state_r_reg[1]_0 ,\n inhibit_edge_detect_r_reg_1,\n \\wait_cnt_reg[0]_0 ,\n \\single_rank.done_dqs_dec_reg_0 ,\n \\FSM_sequential_wl_state_r_reg[2]_1 ,\n S,\n \\stg3_r_reg[5] ,\n O,\n wl_sm_start,\n \\byte_r_reg[0] ,\n \\byte_r_reg[1] ,\n Q,\n \\stg2_tap_cnt_reg[2] ,\n \\po_counter_read_val_reg[8] ,\n \\po_counter_read_val_reg[8]_0 ,\n \\calib_sel_reg[3] ,\n \\po_counter_read_val_reg[5] ,\n rstdiv0_sync_r1_reg_rep__22,\n oclkdelay_calib_done_r_reg,\n \\po_stg2_wrcal_cnt_reg[2] ,\n early1_data_reg,\n early1_data_reg_0,\n rstdiv0_sync_r1_reg_rep__20,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ,\n pi_f_inc_reg,\n oclkdelay_calib_done_r_reg_0,\n delay_done_r4_reg,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 ,\n oclkdelay_calib_done_r_reg_1,\n byte_sel_cnt,\n \\prbs_dqs_cnt_r_reg[2] ,\n rstdiv0_sync_r1_reg_rep__24,\n pi_fine_dly_dec_done,\n rstdiv0_sync_r1_reg_rep,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ,\n my_empty,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ,\n my_empty_6,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ,\n my_empty_7,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ,\n my_empty_8,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ,\n po_cnt_dec_reg_1,\n rstdiv0_sync_r1_reg_rep__19,\n done_dqs_dec239_out,\n \\po_stg2_wrcal_cnt_reg[0] ,\n \\po_stg2_wrcal_cnt_reg[2]_0 ,\n \\po_stg2_wrcal_cnt_reg[1] ,\n wrlvl_byte_redo_reg);\n output wr_level_done_r1_reg_0;\n output wrlvl_byte_redo_r;\n output wrlvl_final_r;\n output dqs_po_dec_done;\n output dqs_po_stg2_f_incdec;\n output dqs_po_en_stg2_f;\n output dqs_wl_po_stg2_c_incdec;\n output \\rd_data_edge_detect_r_reg[0]_0 ;\n output \\FSM_sequential_wl_state_r_reg[0]_0 ;\n output p_0_in;\n output \\rd_data_edge_detect_r_reg[0]_1 ;\n output dqs_po_en_stg2_f_reg_0;\n output wrlvl_done_r_reg;\n output wrlvl_rank_done;\n output [7:0]D;\n output [1:0]\\stg2_target_r_reg[4] ;\n output \\stg2_r_reg[4] ;\n output \\stg3_dec_val_reg[2] ;\n output \\stg2_r_reg[5] ;\n output [4:0]out;\n output stable_cnt227_in;\n output [2:0]\\stg3_dec_val_reg[2]_0 ;\n output \\lim_state_reg[12] ;\n output \\stg2_r_reg[0] ;\n output \\po_rdval_cnt_reg[0]_0 ;\n output flag_ck_negedge09_out;\n output [0:0]\\stable_cnt_reg[3]_0 ;\n output \\rank_cnt_r_reg[0]_0 ;\n output \\rank_cnt_r_reg[0]_1 ;\n output stable_cnt1;\n output [1:0]\\wrlvl_redo_corse_inc_reg[2]_0 ;\n output po_cnt_dec_reg_0;\n output flag_ck_negedge_reg_0;\n output \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ;\n output \\gen_byte_sel_div1.byte_sel_cnt_reg[1] ;\n output \\gen_byte_sel_div1.byte_sel_cnt_reg[2] ;\n output p_1_in;\n output wrlvl_byte_done;\n output done_dqs_tap_inc;\n output wr_level_done_r_reg_0;\n output wrlvl_rank_done_r_reg_0;\n output dq_cnt_inc_reg_0;\n output inhibit_edge_detect_r;\n output inhibit_edge_detect_r_reg_0;\n input \\mcGo_r_reg[15] ;\n input CLK;\n input wrlvl_byte_redo;\n input wrlvl_final_mux;\n input wr_lvl_start_reg;\n input [1:0]rstdiv0_sync_r1_reg_rep__17;\n input [1:0]SR;\n input flag_ck_negedge_reg_1;\n input \\FSM_sequential_wl_state_r_reg[2]_0 ;\n input \\FSM_sequential_wl_state_r_reg[0]_1 ;\n input \\FSM_sequential_wl_state_r_reg[1]_0 ;\n input inhibit_edge_detect_r_reg_1;\n input \\wait_cnt_reg[0]_0 ;\n input \\single_rank.done_dqs_dec_reg_0 ;\n input \\FSM_sequential_wl_state_r_reg[2]_1 ;\n input [0:0]S;\n input [2:0]\\stg3_r_reg[5] ;\n input [3:0]O;\n input wl_sm_start;\n input \\byte_r_reg[0] ;\n input \\byte_r_reg[1] ;\n input [2:0]Q;\n input [2:0]\\stg2_tap_cnt_reg[2] ;\n input [4:0]\\po_counter_read_val_reg[8] ;\n input [4:0]\\po_counter_read_val_reg[8]_0 ;\n input [0:0]\\calib_sel_reg[3] ;\n input [3:0]\\po_counter_read_val_reg[5] ;\n input rstdiv0_sync_r1_reg_rep__22;\n input oclkdelay_calib_done_r_reg;\n input [2:0]\\po_stg2_wrcal_cnt_reg[2] ;\n input early1_data_reg;\n input early1_data_reg_0;\n input rstdiv0_sync_r1_reg_rep__20;\n input \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ;\n input pi_f_inc_reg;\n input oclkdelay_calib_done_r_reg_0;\n input delay_done_r4_reg;\n input \\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 ;\n input oclkdelay_calib_done_r_reg_1;\n input [0:0]byte_sel_cnt;\n input \\prbs_dqs_cnt_r_reg[2] ;\n input rstdiv0_sync_r1_reg_rep__24;\n input pi_fine_dly_dec_done;\n input rstdiv0_sync_r1_reg_rep;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;\n input [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;\n input [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ;\n input [0:0]my_empty;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;\n input [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;\n input [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ;\n input [0:0]my_empty_6;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;\n input [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;\n input [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ;\n input [0:0]my_empty_7;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ;\n input [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ;\n input [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ;\n input [0:0]my_empty_8;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;\n input [0:0]po_cnt_dec_reg_1;\n input [0:0]rstdiv0_sync_r1_reg_rep__19;\n input done_dqs_dec239_out;\n input \\po_stg2_wrcal_cnt_reg[0] ;\n input \\po_stg2_wrcal_cnt_reg[2]_0 ;\n input \\po_stg2_wrcal_cnt_reg[1] ;\n input wrlvl_byte_redo_reg;\n\n wire CLK;\n wire [7:0]D;\n wire \\FSM_sequential_wl_state_r[0]_i_10_n_0 ;\n wire \\FSM_sequential_wl_state_r[0]_i_11_n_0 ;\n wire \\FSM_sequential_wl_state_r[0]_i_13_n_0 ;\n wire \\FSM_sequential_wl_state_r[0]_i_14_n_0 ;\n wire \\FSM_sequential_wl_state_r[0]_i_15_n_0 ;\n wire \\FSM_sequential_wl_state_r[0]_i_16_n_0 ;\n wire \\FSM_sequential_wl_state_r[0]_i_1_n_0 ;\n wire \\FSM_sequential_wl_state_r[0]_i_2_n_0 ;\n wire \\FSM_sequential_wl_state_r[0]_i_3_n_0 ;\n wire \\FSM_sequential_wl_state_r[0]_i_4_n_0 ;\n wire \\FSM_sequential_wl_state_r[0]_i_5_n_0 ;\n wire \\FSM_sequential_wl_state_r[0]_i_6_n_0 ;\n wire \\FSM_sequential_wl_state_r[0]_i_7_n_0 ;\n wire \\FSM_sequential_wl_state_r[0]_i_8_n_0 ;\n wire \\FSM_sequential_wl_state_r[0]_i_9_n_0 ;\n wire \\FSM_sequential_wl_state_r[1]_i_10_n_0 ;\n wire \\FSM_sequential_wl_state_r[1]_i_11_n_0 ;\n wire \\FSM_sequential_wl_state_r[1]_i_1_n_0 ;\n wire \\FSM_sequential_wl_state_r[1]_i_2_n_0 ;\n wire \\FSM_sequential_wl_state_r[1]_i_3_n_0 ;\n wire \\FSM_sequential_wl_state_r[1]_i_4_n_0 ;\n wire \\FSM_sequential_wl_state_r[1]_i_5_n_0 ;\n wire \\FSM_sequential_wl_state_r[1]_i_6_n_0 ;\n wire \\FSM_sequential_wl_state_r[1]_i_7_n_0 ;\n wire \\FSM_sequential_wl_state_r[1]_i_8_n_0 ;\n wire \\FSM_sequential_wl_state_r[1]_i_9_n_0 ;\n wire \\FSM_sequential_wl_state_r[2]_i_10_n_0 ;\n wire \\FSM_sequential_wl_state_r[2]_i_11_n_0 ;\n wire \\FSM_sequential_wl_state_r[2]_i_12_n_0 ;\n wire \\FSM_sequential_wl_state_r[2]_i_13_n_0 ;\n wire \\FSM_sequential_wl_state_r[2]_i_14_n_0 ;\n wire \\FSM_sequential_wl_state_r[2]_i_15_n_0 ;\n wire \\FSM_sequential_wl_state_r[2]_i_1_n_0 ;\n wire \\FSM_sequential_wl_state_r[2]_i_2_n_0 ;\n wire \\FSM_sequential_wl_state_r[2]_i_3_n_0 ;\n wire \\FSM_sequential_wl_state_r[2]_i_5_n_0 ;\n wire \\FSM_sequential_wl_state_r[2]_i_6_n_0 ;\n wire \\FSM_sequential_wl_state_r[2]_i_7_n_0 ;\n wire \\FSM_sequential_wl_state_r[2]_i_8_n_0 ;\n wire \\FSM_sequential_wl_state_r[2]_i_9_n_0 ;\n wire \\FSM_sequential_wl_state_r[3]_i_10_n_0 ;\n wire \\FSM_sequential_wl_state_r[3]_i_1_n_0 ;\n wire \\FSM_sequential_wl_state_r[3]_i_2_n_0 ;\n wire \\FSM_sequential_wl_state_r[3]_i_3_n_0 ;\n wire \\FSM_sequential_wl_state_r[3]_i_4_n_0 ;\n wire \\FSM_sequential_wl_state_r[3]_i_5_n_0 ;\n wire \\FSM_sequential_wl_state_r[3]_i_6_n_0 ;\n wire \\FSM_sequential_wl_state_r[3]_i_7_n_0 ;\n wire \\FSM_sequential_wl_state_r[3]_i_8_n_0 ;\n wire \\FSM_sequential_wl_state_r[3]_i_9_n_0 ;\n wire \\FSM_sequential_wl_state_r[4]_i_10_n_0 ;\n wire \\FSM_sequential_wl_state_r[4]_i_11_n_0 ;\n wire \\FSM_sequential_wl_state_r[4]_i_12_n_0 ;\n wire \\FSM_sequential_wl_state_r[4]_i_1_n_0 ;\n wire \\FSM_sequential_wl_state_r[4]_i_2_n_0 ;\n wire \\FSM_sequential_wl_state_r[4]_i_3_n_0 ;\n wire \\FSM_sequential_wl_state_r[4]_i_5_n_0 ;\n wire \\FSM_sequential_wl_state_r[4]_i_7_n_0 ;\n wire \\FSM_sequential_wl_state_r[4]_i_8_n_0 ;\n wire \\FSM_sequential_wl_state_r[4]_i_9_n_0 ;\n wire \\FSM_sequential_wl_state_r_reg[0]_0 ;\n wire \\FSM_sequential_wl_state_r_reg[0]_1 ;\n wire \\FSM_sequential_wl_state_r_reg[0]_i_12_n_0 ;\n wire \\FSM_sequential_wl_state_r_reg[1]_0 ;\n wire \\FSM_sequential_wl_state_r_reg[2]_0 ;\n wire \\FSM_sequential_wl_state_r_reg[2]_1 ;\n wire \\FSM_sequential_wl_state_r_reg[2]_i_4_n_0 ;\n wire \\FSM_sequential_wl_state_r_reg[4]_i_4_n_0 ;\n wire [3:0]O;\n wire [2:0]Q;\n wire [0:0]S;\n wire [1:0]SR;\n wire \\byte_r_reg[0] ;\n wire \\byte_r_reg[1] ;\n wire [0:0]byte_sel_cnt;\n wire [0:0]\\calib_sel_reg[3] ;\n wire [2:0]corse_cnt;\n wire \\corse_cnt[0][0]_i_1_n_0 ;\n wire \\corse_cnt[0][0]_i_3_n_0 ;\n wire \\corse_cnt[0][0]_i_4_n_0 ;\n wire \\corse_cnt[0][1]_i_1_n_0 ;\n wire \\corse_cnt[0][1]_i_3_n_0 ;\n wire \\corse_cnt[0][1]_i_4_n_0 ;\n wire \\corse_cnt[0][1]_i_5_n_0 ;\n wire \\corse_cnt[0][2]_i_10_n_0 ;\n wire \\corse_cnt[0][2]_i_1_n_0 ;\n wire \\corse_cnt[0][2]_i_3_n_0 ;\n wire \\corse_cnt[0][2]_i_4_n_0 ;\n wire \\corse_cnt[0][2]_i_5_n_0 ;\n wire \\corse_cnt[0][2]_i_6_n_0 ;\n wire \\corse_cnt[0][2]_i_7_n_0 ;\n wire \\corse_cnt[0][2]_i_8_n_0 ;\n wire \\corse_cnt[0][2]_i_9_n_0 ;\n wire \\corse_cnt[1][0]_i_1_n_0 ;\n wire \\corse_cnt[1][1]_i_1_n_0 ;\n wire \\corse_cnt[1][2]_i_1_n_0 ;\n wire \\corse_cnt[1][2]_i_2_n_0 ;\n wire \\corse_cnt[1][2]_i_3_n_0 ;\n wire \\corse_cnt[1][2]_i_4_n_0 ;\n wire \\corse_cnt[2][0]_i_1_n_0 ;\n wire \\corse_cnt[2][1]_i_1_n_0 ;\n wire \\corse_cnt[2][2]_i_1_n_0 ;\n wire \\corse_cnt[2][2]_i_2_n_0 ;\n wire \\corse_cnt[2][2]_i_3_n_0 ;\n wire \\corse_cnt[2][2]_i_4_n_0 ;\n wire \\corse_cnt[3][0]_i_1_n_0 ;\n wire \\corse_cnt[3][1]_i_1_n_0 ;\n wire \\corse_cnt[3][2]_i_1_n_0 ;\n wire \\corse_cnt[3][2]_i_2_n_0 ;\n wire \\corse_cnt[3][2]_i_3_n_0 ;\n wire \\corse_cnt[3][2]_i_4_n_0 ;\n wire \\corse_cnt_reg_n_0_[0][0] ;\n wire \\corse_cnt_reg_n_0_[0][1] ;\n wire \\corse_cnt_reg_n_0_[0][2] ;\n wire \\corse_cnt_reg_n_0_[1][0] ;\n wire \\corse_cnt_reg_n_0_[1][1] ;\n wire \\corse_cnt_reg_n_0_[1][2] ;\n wire \\corse_cnt_reg_n_0_[2][0] ;\n wire \\corse_cnt_reg_n_0_[2][1] ;\n wire \\corse_cnt_reg_n_0_[2][2] ;\n wire \\corse_cnt_reg_n_0_[3][0] ;\n wire \\corse_cnt_reg_n_0_[3][1] ;\n wire \\corse_cnt_reg_n_0_[3][2] ;\n wire \\corse_dec[0][0]_i_1_n_0 ;\n wire \\corse_dec[0][1]_i_1_n_0 ;\n wire \\corse_dec[0][2]_i_1_n_0 ;\n wire \\corse_dec[0][2]_i_2_n_0 ;\n wire \\corse_dec[1][0]_i_1_n_0 ;\n wire \\corse_dec[1][1]_i_1_n_0 ;\n wire \\corse_dec[1][2]_i_1_n_0 ;\n wire \\corse_dec[1][2]_i_2_n_0 ;\n wire \\corse_dec[2][0]_i_1_n_0 ;\n wire \\corse_dec[2][1]_i_1_n_0 ;\n wire \\corse_dec[2][2]_i_1_n_0 ;\n wire \\corse_dec[2][2]_i_2_n_0 ;\n wire \\corse_dec[3][0]_i_1_n_0 ;\n wire \\corse_dec[3][1]_i_1_n_0 ;\n wire \\corse_dec[3][2]_i_1_n_0 ;\n wire \\corse_dec[3][2]_i_2_n_0 ;\n wire \\corse_dec[3][2]_i_3_n_0 ;\n wire \\corse_dec[3][2]_i_4_n_0 ;\n wire \\corse_dec[3][2]_i_5_n_0 ;\n wire \\corse_dec_reg_n_0_[0][0] ;\n wire \\corse_dec_reg_n_0_[0][1] ;\n wire \\corse_dec_reg_n_0_[0][2] ;\n wire \\corse_dec_reg_n_0_[1][0] ;\n wire \\corse_dec_reg_n_0_[1][1] ;\n wire \\corse_dec_reg_n_0_[1][2] ;\n wire \\corse_dec_reg_n_0_[2][0] ;\n wire \\corse_dec_reg_n_0_[2][1] ;\n wire \\corse_dec_reg_n_0_[2][2] ;\n wire \\corse_dec_reg_n_0_[3][0] ;\n wire \\corse_dec_reg_n_0_[3][1] ;\n wire \\corse_dec_reg_n_0_[3][2] ;\n wire \\corse_inc[0][0]_i_1_n_0 ;\n wire \\corse_inc[0][1]_i_1_n_0 ;\n wire \\corse_inc[0][2]_i_1_n_0 ;\n wire \\corse_inc[0][2]_i_2_n_0 ;\n wire \\corse_inc[0][2]_i_3_n_0 ;\n wire \\corse_inc[1][0]_i_1_n_0 ;\n wire \\corse_inc[1][1]_i_1_n_0 ;\n wire \\corse_inc[1][2]_i_1_n_0 ;\n wire \\corse_inc[1][2]_i_2_n_0 ;\n wire \\corse_inc[1][2]_i_3_n_0 ;\n wire \\corse_inc[2][0]_i_1_n_0 ;\n wire \\corse_inc[2][1]_i_1_n_0 ;\n wire \\corse_inc[2][2]_i_1_n_0 ;\n wire \\corse_inc[2][2]_i_2_n_0 ;\n wire \\corse_inc[2][2]_i_3_n_0 ;\n wire \\corse_inc[3][0]_i_1_n_0 ;\n wire \\corse_inc[3][0]_i_2_n_0 ;\n wire \\corse_inc[3][1]_i_1_n_0 ;\n wire \\corse_inc[3][1]_i_2_n_0 ;\n wire \\corse_inc[3][2]_i_1_n_0 ;\n wire \\corse_inc[3][2]_i_2_n_0 ;\n wire \\corse_inc[3][2]_i_3_n_0 ;\n wire \\corse_inc[3][2]_i_4_n_0 ;\n wire \\corse_inc[3][2]_i_5_n_0 ;\n wire \\corse_inc[3][2]_i_6_n_0 ;\n wire \\corse_inc[3][2]_i_7_n_0 ;\n wire \\corse_inc_reg_n_0_[0][0] ;\n wire \\corse_inc_reg_n_0_[0][1] ;\n wire \\corse_inc_reg_n_0_[0][2] ;\n wire \\corse_inc_reg_n_0_[1][0] ;\n wire \\corse_inc_reg_n_0_[1][1] ;\n wire \\corse_inc_reg_n_0_[1][2] ;\n wire \\corse_inc_reg_n_0_[2][0] ;\n wire \\corse_inc_reg_n_0_[2][1] ;\n wire \\corse_inc_reg_n_0_[2][2] ;\n wire \\corse_inc_reg_n_0_[3][0] ;\n wire \\corse_inc_reg_n_0_[3][1] ;\n wire \\corse_inc_reg_n_0_[3][2] ;\n wire delay_done_r4_reg;\n wire done_dqs_dec;\n wire done_dqs_dec239_out;\n wire done_dqs_tap_inc;\n wire dq_cnt_inc_reg_0;\n wire [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ;\n wire [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;\n wire [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ;\n wire [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ;\n wire [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ;\n wire [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;\n wire [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;\n wire [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ;\n wire [2:0]dqs_count_r;\n wire dqs_count_r140_out;\n wire \\dqs_count_r[0]_i_1_n_0 ;\n wire \\dqs_count_r[0]_i_4_n_0 ;\n wire \\dqs_count_r[0]_i_5_n_0 ;\n wire \\dqs_count_r[0]_i_6_n_0 ;\n wire \\dqs_count_r[0]_i_7_n_0 ;\n wire \\dqs_count_r[0]_i_8_n_0 ;\n wire \\dqs_count_r[1]_i_1_n_0 ;\n wire \\dqs_count_r[1]_i_4_n_0 ;\n wire \\dqs_count_r[1]_i_5_n_0 ;\n wire \\dqs_count_r[1]_i_6_n_0 ;\n wire \\dqs_count_r[1]_i_7_n_0 ;\n wire \\dqs_count_r[1]_i_8_n_0 ;\n wire \\dqs_count_r[2]_i_10_n_0 ;\n wire \\dqs_count_r[2]_i_11_n_0 ;\n wire \\dqs_count_r[2]_i_2_n_0 ;\n wire \\dqs_count_r[2]_i_5_n_0 ;\n wire \\dqs_count_r[2]_i_6_n_0 ;\n wire \\dqs_count_r[2]_i_7_n_0 ;\n wire \\dqs_count_r[2]_i_8_n_0 ;\n wire \\dqs_count_r[2]_i_9_n_0 ;\n wire \\dqs_count_r_reg[0]_i_2_n_0 ;\n wire \\dqs_count_r_reg[0]_i_3_n_0 ;\n wire \\dqs_count_r_reg[0]_rep_n_0 ;\n wire \\dqs_count_r_reg[1]_i_2_n_0 ;\n wire \\dqs_count_r_reg[1]_i_3_n_0 ;\n wire \\dqs_count_r_reg[1]_rep_n_0 ;\n wire \\dqs_count_r_reg[2]_i_3_n_0 ;\n wire \\dqs_count_r_reg[2]_i_4_n_0 ;\n wire dqs_po_dec_done;\n wire dqs_po_en_stg2_f;\n wire dqs_po_en_stg2_f_i_1_n_0;\n wire dqs_po_en_stg2_f_reg_0;\n wire dqs_po_stg2_f_incdec;\n wire dqs_po_stg2_f_incdec0;\n wire dqs_po_stg2_f_incdec_i_2_n_0;\n wire dqs_po_stg2_f_incdec_i_3_n_0;\n wire dqs_wl_po_stg2_c_incdec;\n wire dqs_wl_po_stg2_c_incdec_i_1_n_0;\n wire early1_data_reg;\n wire early1_data_reg_0;\n wire [0:0]final_coarse_tap;\n wire \\final_coarse_tap_reg_n_0_[0][0] ;\n wire \\final_coarse_tap_reg_n_0_[0][1] ;\n wire \\final_coarse_tap_reg_n_0_[0][2] ;\n wire \\final_coarse_tap_reg_n_0_[1][0] ;\n wire \\final_coarse_tap_reg_n_0_[1][1] ;\n wire \\final_coarse_tap_reg_n_0_[1][2] ;\n wire \\final_coarse_tap_reg_n_0_[2][0] ;\n wire \\final_coarse_tap_reg_n_0_[2][1] ;\n wire \\final_coarse_tap_reg_n_0_[2][2] ;\n wire \\final_coarse_tap_reg_n_0_[3][0] ;\n wire \\final_coarse_tap_reg_n_0_[3][1] ;\n wire \\final_coarse_tap_reg_n_0_[3][2] ;\n wire [5:0]fine_dec_cnt;\n wire \\fine_dec_cnt[1]_i_2_n_0 ;\n wire \\fine_dec_cnt[2]_i_2_n_0 ;\n wire \\fine_dec_cnt[3]_i_2_n_0 ;\n wire \\fine_dec_cnt[4]_i_2_n_0 ;\n wire \\fine_dec_cnt[5]_i_3_n_0 ;\n wire \\fine_dec_cnt[5]_i_4_n_0 ;\n wire \\fine_dec_cnt[5]_i_5_n_0 ;\n wire \\fine_dec_cnt[5]_i_6_n_0 ;\n wire \\fine_dec_cnt[5]_i_7_n_0 ;\n wire \\fine_dec_cnt[5]_i_8_n_0 ;\n wire [5:0]fine_dec_cnt__0;\n wire \\fine_dec_cnt_reg[5]_i_1_n_0 ;\n wire [5:0]fine_inc;\n wire \\fine_inc[0][5]_i_1_n_0 ;\n wire \\fine_inc[0][5]_i_3_n_0 ;\n wire \\fine_inc[1][0]_i_1_n_0 ;\n wire \\fine_inc[1][1]_i_1_n_0 ;\n wire \\fine_inc[1][2]_i_1_n_0 ;\n wire \\fine_inc[1][3]_i_1_n_0 ;\n wire \\fine_inc[1][4]_i_1_n_0 ;\n wire \\fine_inc[1][5]_i_1_n_0 ;\n wire \\fine_inc[1][5]_i_2_n_0 ;\n wire \\fine_inc[1][5]_i_3_n_0 ;\n wire \\fine_inc[2][0]_i_1_n_0 ;\n wire \\fine_inc[2][1]_i_1_n_0 ;\n wire \\fine_inc[2][2]_i_1_n_0 ;\n wire \\fine_inc[2][3]_i_1_n_0 ;\n wire \\fine_inc[2][4]_i_1_n_0 ;\n wire \\fine_inc[2][5]_i_1_n_0 ;\n wire \\fine_inc[2][5]_i_2_n_0 ;\n wire \\fine_inc[2][5]_i_3_n_0 ;\n wire \\fine_inc[3][0]_i_1_n_0 ;\n wire \\fine_inc[3][1]_i_1_n_0 ;\n wire \\fine_inc[3][2]_i_1_n_0 ;\n wire \\fine_inc[3][2]_i_2_n_0 ;\n wire \\fine_inc[3][2]_i_3_n_0 ;\n wire \\fine_inc[3][2]_i_4_n_0 ;\n wire \\fine_inc[3][3]_i_1_n_0 ;\n wire \\fine_inc[3][4]_i_1_n_0 ;\n wire \\fine_inc[3][4]_i_2_n_0 ;\n wire \\fine_inc[3][4]_i_3_n_0 ;\n wire \\fine_inc[3][4]_i_4_n_0 ;\n wire \\fine_inc[3][5]_i_1_n_0 ;\n wire \\fine_inc[3][5]_i_2_n_0 ;\n wire \\fine_inc[3][5]_i_3_n_0 ;\n wire \\fine_inc[3][5]_i_5_n_0 ;\n wire \\fine_inc[3][5]_i_6_n_0 ;\n wire \\fine_inc[3][5]_i_7_n_0 ;\n wire \\fine_inc[3][5]_i_8_n_0 ;\n wire \\fine_inc_reg_n_0_[0][0] ;\n wire \\fine_inc_reg_n_0_[0][1] ;\n wire \\fine_inc_reg_n_0_[0][2] ;\n wire \\fine_inc_reg_n_0_[0][3] ;\n wire \\fine_inc_reg_n_0_[0][4] ;\n wire \\fine_inc_reg_n_0_[0][5] ;\n wire \\fine_inc_reg_n_0_[1][0] ;\n wire \\fine_inc_reg_n_0_[1][1] ;\n wire \\fine_inc_reg_n_0_[1][2] ;\n wire \\fine_inc_reg_n_0_[1][3] ;\n wire \\fine_inc_reg_n_0_[1][4] ;\n wire \\fine_inc_reg_n_0_[1][5] ;\n wire \\fine_inc_reg_n_0_[2][0] ;\n wire \\fine_inc_reg_n_0_[2][1] ;\n wire \\fine_inc_reg_n_0_[2][2] ;\n wire \\fine_inc_reg_n_0_[2][3] ;\n wire \\fine_inc_reg_n_0_[2][4] ;\n wire \\fine_inc_reg_n_0_[2][5] ;\n wire \\fine_inc_reg_n_0_[3][0] ;\n wire \\fine_inc_reg_n_0_[3][1] ;\n wire \\fine_inc_reg_n_0_[3][2] ;\n wire \\fine_inc_reg_n_0_[3][3] ;\n wire \\fine_inc_reg_n_0_[3][4] ;\n wire \\fine_inc_reg_n_0_[3][5] ;\n wire flag_ck_negedge09_out;\n wire flag_ck_negedge_i_10_n_0;\n wire flag_ck_negedge_i_6_n_0;\n wire flag_ck_negedge_i_7_n_0;\n wire flag_ck_negedge_i_8_n_0;\n wire flag_ck_negedge_reg_0;\n wire flag_ck_negedge_reg_1;\n wire flag_init;\n wire flag_init_i_1_n_0;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[1] ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[2] ;\n wire \\gen_final_tap[0].final_val_reg_n_0_[0][0] ;\n wire \\gen_final_tap[0].final_val_reg_n_0_[0][1] ;\n wire \\gen_final_tap[0].final_val_reg_n_0_[0][2] ;\n wire \\gen_final_tap[0].final_val_reg_n_0_[0][3] ;\n wire \\gen_final_tap[0].final_val_reg_n_0_[0][4] ;\n wire \\gen_final_tap[0].final_val_reg_n_0_[0][5] ;\n wire \\gen_final_tap[1].final_val_reg_n_0_[1][0] ;\n wire \\gen_final_tap[1].final_val_reg_n_0_[1][1] ;\n wire \\gen_final_tap[1].final_val_reg_n_0_[1][2] ;\n wire \\gen_final_tap[1].final_val_reg_n_0_[1][3] ;\n wire \\gen_final_tap[1].final_val_reg_n_0_[1][4] ;\n wire \\gen_final_tap[1].final_val_reg_n_0_[1][5] ;\n wire \\gen_final_tap[2].final_val_reg_n_0_[2][0] ;\n wire \\gen_final_tap[2].final_val_reg_n_0_[2][1] ;\n wire \\gen_final_tap[2].final_val_reg_n_0_[2][2] ;\n wire \\gen_final_tap[2].final_val_reg_n_0_[2][3] ;\n wire \\gen_final_tap[2].final_val_reg_n_0_[2][4] ;\n wire \\gen_final_tap[2].final_val_reg_n_0_[2][5] ;\n wire \\gen_final_tap[3].final_val_reg_n_0_[3][0] ;\n wire \\gen_final_tap[3].final_val_reg_n_0_[3][1] ;\n wire \\gen_final_tap[3].final_val_reg_n_0_[3][2] ;\n wire \\gen_final_tap[3].final_val_reg_n_0_[3][3] ;\n wire \\gen_final_tap[3].final_val_reg_n_0_[3][4] ;\n wire \\gen_final_tap[3].final_val_reg_n_0_[3][5] ;\n wire \\gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ;\n wire \\gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ;\n wire \\gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2] ;\n wire \\gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3] ;\n wire \\incdec_wait_cnt[3]_i_1_n_0 ;\n wire [3:0]incdec_wait_cnt_reg__0;\n wire inhibit_edge_detect_r;\n wire inhibit_edge_detect_r_i_4_n_0;\n wire inhibit_edge_detect_r_reg_0;\n wire inhibit_edge_detect_r_reg_1;\n wire [5:0]largest;\n wire \\lim_state_reg[12] ;\n wire \\mcGo_r_reg[15] ;\n wire [0:0]my_empty;\n wire [0:0]my_empty_6;\n wire [0:0]my_empty_7;\n wire [0:0]my_empty_8;\n wire [5:3]\\oclk_calib.u_ddr_phy_oclkdelay_cal/wl_po_fine_cnt_sel_0__0 ;\n wire oclkdelay_calib_done_r_reg;\n wire oclkdelay_calib_done_r_reg_0;\n wire oclkdelay_calib_done_r_reg_1;\n (* RTL_KEEP = \"yes\" *) wire [4:0]out;\n wire p_0_in;\n wire p_0_in32_in;\n wire [3:0]p_0_in__0;\n wire [3:0]p_0_in__0__0;\n wire \\p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_1_n_0 ;\n wire \\p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_2_n_0 ;\n wire \\p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_1_n_0 ;\n wire \\p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_2_n_0 ;\n wire \\p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_1_n_0 ;\n wire \\p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_2_n_0 ;\n wire \\p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_1_n_0 ;\n wire \\p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_2_n_0 ;\n wire p_1_in;\n wire p_1_in1_in;\n wire p_1_in28_in;\n wire p_1_in_0;\n wire p_21_out;\n wire phy_ctl_ready_r4_reg_srl4_n_0;\n wire phy_ctl_ready_r5;\n wire phy_ctl_ready_r6_reg_n_0;\n wire pi_f_inc_reg;\n wire pi_fine_dly_dec_done;\n wire po_cnt_dec_reg_0;\n wire [0:0]po_cnt_dec_reg_1;\n wire [3:0]\\po_counter_read_val_reg[5] ;\n wire [4:0]\\po_counter_read_val_reg[8] ;\n wire [4:0]\\po_counter_read_val_reg[8]_0 ;\n wire po_dec_done;\n wire po_dec_done_i_1_n_0;\n wire po_dec_done_i_2_n_0;\n wire po_dec_done_i_3_n_0;\n wire [8:0]po_rdval_cnt;\n wire \\po_rdval_cnt[0]_i_1_n_0 ;\n wire \\po_rdval_cnt[1]_i_1_n_0 ;\n wire \\po_rdval_cnt[2]_i_1_n_0 ;\n wire \\po_rdval_cnt[3]_i_1_n_0 ;\n wire \\po_rdval_cnt[4]_i_1_n_0 ;\n wire \\po_rdval_cnt[4]_i_2_n_0 ;\n wire \\po_rdval_cnt[5]_i_1_n_0 ;\n wire \\po_rdval_cnt[5]_i_2_n_0 ;\n wire \\po_rdval_cnt[6]_i_1_n_0 ;\n wire \\po_rdval_cnt[6]_i_2_n_0 ;\n wire \\po_rdval_cnt[7]_i_1_n_0 ;\n wire \\po_rdval_cnt[7]_i_2_n_0 ;\n wire \\po_rdval_cnt[8]_i_1_n_0 ;\n wire \\po_rdval_cnt[8]_i_2_n_0 ;\n wire \\po_rdval_cnt[8]_i_4_n_0 ;\n wire \\po_rdval_cnt[8]_i_5_n_0 ;\n wire \\po_rdval_cnt[8]_i_6_n_0 ;\n wire \\po_rdval_cnt[8]_i_7_n_0 ;\n wire \\po_rdval_cnt_reg[0]_0 ;\n wire \\po_stg2_wrcal_cnt_reg[0] ;\n wire \\po_stg2_wrcal_cnt_reg[1] ;\n wire [2:0]\\po_stg2_wrcal_cnt_reg[2] ;\n wire \\po_stg2_wrcal_cnt_reg[2]_0 ;\n wire \\prbs_dqs_cnt_r_reg[2] ;\n wire rank_cnt_r;\n wire \\rank_cnt_r[0]_i_1_n_0 ;\n wire \\rank_cnt_r[1]_i_1_n_0 ;\n wire \\rank_cnt_r_reg[0]_0 ;\n wire \\rank_cnt_r_reg[0]_1 ;\n wire rd_data_edge_detect_r0;\n wire \\rd_data_edge_detect_r[0]_i_1_n_0 ;\n wire \\rd_data_edge_detect_r[1]_i_1_n_0 ;\n wire \\rd_data_edge_detect_r[2]_i_1_n_0 ;\n wire \\rd_data_edge_detect_r[3]_i_2_n_0 ;\n wire \\rd_data_edge_detect_r[3]_i_3_n_0 ;\n wire \\rd_data_edge_detect_r[3]_i_4_n_0 ;\n wire \\rd_data_edge_detect_r[3]_i_5_n_0 ;\n wire \\rd_data_edge_detect_r[3]_i_6_n_0 ;\n wire \\rd_data_edge_detect_r_reg[0]_0 ;\n wire \\rd_data_edge_detect_r_reg[0]_1 ;\n wire \\rd_data_edge_detect_r_reg_n_0_[0] ;\n wire \\rd_data_edge_detect_r_reg_n_0_[1] ;\n wire \\rd_data_edge_detect_r_reg_n_0_[2] ;\n wire \\rd_data_edge_detect_r_reg_n_0_[3] ;\n wire rd_data_previous_r0;\n wire \\rd_data_previous_r[3]_i_2_n_0 ;\n wire \\rd_data_previous_r[3]_i_3_n_0 ;\n wire \\rd_data_previous_r[3]_i_4_n_0 ;\n wire \\rd_data_previous_r_reg_n_0_[0] ;\n wire \\rd_data_previous_r_reg_n_0_[1] ;\n wire \\rd_data_previous_r_reg_n_0_[2] ;\n wire \\rd_data_previous_r_reg_n_0_[3] ;\n wire rstdiv0_sync_r1_reg_rep;\n wire [1:0]rstdiv0_sync_r1_reg_rep__17;\n wire [0:0]rstdiv0_sync_r1_reg_rep__19;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__22;\n wire rstdiv0_sync_r1_reg_rep__24;\n wire \\single_rank.done_dqs_dec_i_1_n_0 ;\n wire \\single_rank.done_dqs_dec_reg_0 ;\n wire \\smallest[0][0]_i_2_n_0 ;\n wire \\smallest[0][1]_i_2_n_0 ;\n wire \\smallest[0][2]_i_2_n_0 ;\n wire \\smallest[0][3]_i_2_n_0 ;\n wire \\smallest[0][4]_i_2_n_0 ;\n wire \\smallest[0][5]_i_2_n_0 ;\n wire \\smallest[0][5]_i_4_n_0 ;\n wire \\smallest[0][5]_i_5_n_0 ;\n wire \\smallest[1][0]_i_1_n_0 ;\n wire \\smallest[1][1]_i_1_n_0 ;\n wire \\smallest[1][2]_i_1_n_0 ;\n wire \\smallest[1][3]_i_1_n_0 ;\n wire \\smallest[1][4]_i_1_n_0 ;\n wire \\smallest[1][5]_i_1_n_0 ;\n wire \\smallest[1][5]_i_2_n_0 ;\n wire \\smallest[2][0]_i_1_n_0 ;\n wire \\smallest[2][1]_i_1_n_0 ;\n wire \\smallest[2][2]_i_1_n_0 ;\n wire \\smallest[2][3]_i_1_n_0 ;\n wire \\smallest[2][4]_i_1_n_0 ;\n wire \\smallest[2][5]_i_1_n_0 ;\n wire \\smallest[2][5]_i_2_n_0 ;\n wire \\smallest[3][0]_i_1_n_0 ;\n wire \\smallest[3][1]_i_1_n_0 ;\n wire \\smallest[3][2]_i_1_n_0 ;\n wire \\smallest[3][3]_i_1_n_0 ;\n wire \\smallest[3][4]_i_1_n_0 ;\n wire \\smallest[3][5]_i_1_n_0 ;\n wire \\smallest[3][5]_i_2_n_0 ;\n wire [5:0]\\smallest_reg[0]__0 ;\n wire [5:0]\\smallest_reg[1]__0 ;\n wire [5:0]\\smallest_reg[2]__0 ;\n wire [5:0]\\smallest_reg[3]__0 ;\n wire stable_cnt;\n wire stable_cnt0;\n wire stable_cnt1;\n wire stable_cnt227_in;\n wire \\stable_cnt[3]_i_4_n_0 ;\n wire \\stable_cnt[3]_i_6_n_0 ;\n wire \\stable_cnt[3]_i_7_n_0 ;\n wire [0:0]\\stable_cnt_reg[3]_0 ;\n wire \\stable_cnt_reg_n_0_[1] ;\n wire \\stable_cnt_reg_n_0_[2] ;\n wire \\stable_cnt_reg_n_0_[3] ;\n wire \\stg2_r_reg[0] ;\n wire \\stg2_r_reg[4] ;\n wire \\stg2_r_reg[5] ;\n wire \\stg2_tap_cnt[3]_i_4_n_0 ;\n wire [2:0]\\stg2_tap_cnt_reg[2] ;\n wire \\stg2_target_r[4]_i_4_n_0 ;\n wire \\stg2_target_r[4]_i_5_n_0 ;\n wire \\stg2_target_r[8]_i_6_n_0 ;\n wire [1:0]\\stg2_target_r_reg[4] ;\n wire \\stg2_target_r_reg[4]_i_1_n_0 ;\n wire \\stg2_target_r_reg[4]_i_1_n_1 ;\n wire \\stg2_target_r_reg[4]_i_1_n_2 ;\n wire \\stg2_target_r_reg[4]_i_1_n_3 ;\n wire \\stg2_target_r_reg[8]_i_1_n_1 ;\n wire \\stg2_target_r_reg[8]_i_1_n_2 ;\n wire \\stg2_target_r_reg[8]_i_1_n_3 ;\n wire \\stg3_dec_val_reg[2] ;\n wire [2:0]\\stg3_dec_val_reg[2]_0 ;\n wire [2:0]\\stg3_r_reg[5] ;\n wire \\u_ocd_po_cntlr/stg2_target_r[4]_i_6_n_0 ;\n wire wait_cnt0;\n wire [3:0]wait_cnt0__0;\n wire \\wait_cnt[1]_i_1_n_0 ;\n wire \\wait_cnt_reg[0]_0 ;\n wire [3:0]wait_cnt_reg__0;\n wire wl_corse_cnt;\n wire \\wl_corse_cnt[0][0][0]_i_1_n_0 ;\n wire \\wl_corse_cnt[0][0][1]_i_1_n_0 ;\n wire \\wl_corse_cnt[0][0][2]_i_2_n_0 ;\n wire \\wl_corse_cnt[0][0][2]_i_3_n_0 ;\n wire \\wl_corse_cnt[0][0][2]_i_4_n_0 ;\n wire \\wl_corse_cnt[0][1][2]_i_1_n_0 ;\n wire \\wl_corse_cnt[0][2][2]_i_1_n_0 ;\n wire \\wl_corse_cnt[0][3][2]_i_1_n_0 ;\n wire [2:0]\\wl_corse_cnt_reg[0][0]__0 ;\n wire [2:0]\\wl_corse_cnt_reg[0][1]__0 ;\n wire [2:0]\\wl_corse_cnt_reg[0][2]__0 ;\n wire [2:0]\\wl_corse_cnt_reg[0][3]__0 ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][0][0] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][0][1] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][0][2] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][0][3] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][0][4] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][0][5] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][1][0] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][1][1] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][1][2] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][1][3] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][1][4] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][1][5] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][2][0] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][2][1] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][2][2] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][2][3] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][2][4] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][2][5] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][3][0] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][3][1] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][3][2] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][3][3] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][3][4] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][3][5] ;\n wire [23:0]wl_po_fine_cnt;\n wire wl_sm_start;\n wire wl_state_r1;\n wire \\wl_state_r1[0]_i_1_n_0 ;\n wire \\wl_state_r1[1]_i_1_n_0 ;\n wire \\wl_state_r1[2]_i_1_n_0 ;\n wire \\wl_state_r1[3]_i_1_n_0 ;\n wire \\wl_state_r1[4]_i_1_n_0 ;\n wire \\wl_state_r1_reg_n_0_[0] ;\n wire \\wl_state_r1_reg_n_0_[1] ;\n wire \\wl_state_r1_reg_n_0_[2] ;\n wire \\wl_state_r1_reg_n_0_[3] ;\n wire \\wl_state_r1_reg_n_0_[4] ;\n wire [5:0]wl_tap_count_r;\n wire \\wl_tap_count_r[0]_i_2_n_0 ;\n wire \\wl_tap_count_r[0]_i_3_n_0 ;\n wire \\wl_tap_count_r[1]_i_2_n_0 ;\n wire \\wl_tap_count_r[1]_i_3_n_0 ;\n wire \\wl_tap_count_r[1]_i_4_n_0 ;\n wire \\wl_tap_count_r[2]_i_2_n_0 ;\n wire \\wl_tap_count_r[2]_i_3_n_0 ;\n wire \\wl_tap_count_r[2]_i_4_n_0 ;\n wire \\wl_tap_count_r[3]_i_2_n_0 ;\n wire \\wl_tap_count_r[3]_i_3_n_0 ;\n wire \\wl_tap_count_r[3]_i_4_n_0 ;\n wire \\wl_tap_count_r[4]_i_2_n_0 ;\n wire \\wl_tap_count_r[4]_i_3_n_0 ;\n wire \\wl_tap_count_r[4]_i_4_n_0 ;\n wire \\wl_tap_count_r[5]_i_1_n_0 ;\n wire \\wl_tap_count_r[5]_i_4_n_0 ;\n wire \\wl_tap_count_r[5]_i_5_n_0 ;\n wire \\wl_tap_count_r[5]_i_6_n_0 ;\n wire \\wl_tap_count_r_reg_n_0_[0] ;\n wire \\wl_tap_count_r_reg_n_0_[1] ;\n wire \\wl_tap_count_r_reg_n_0_[2] ;\n wire \\wl_tap_count_r_reg_n_0_[3] ;\n wire \\wl_tap_count_r_reg_n_0_[4] ;\n wire \\wl_tap_count_r_reg_n_0_[5] ;\n wire wr_level_done0;\n wire wr_level_done_r1;\n wire wr_level_done_r1_reg_0;\n wire wr_level_done_r2;\n wire wr_level_done_r3;\n wire wr_level_done_r4;\n wire wr_level_done_r5;\n wire wr_level_done_r_reg_0;\n wire wr_level_start_r;\n wire wr_lvl_start_reg;\n wire wrlvl_byte_done;\n wire wrlvl_byte_done_i_1_n_0;\n wire wrlvl_byte_redo;\n wire wrlvl_byte_redo_r;\n wire wrlvl_byte_redo_reg;\n wire wrlvl_done_r_reg;\n wire wrlvl_final_mux;\n wire wrlvl_final_r;\n wire wrlvl_rank_done;\n wire wrlvl_rank_done_r_reg_0;\n wire \\wrlvl_redo_corse_inc[0]_i_1_n_0 ;\n wire \\wrlvl_redo_corse_inc[1]_i_1_n_0 ;\n wire \\wrlvl_redo_corse_inc[2]_i_1_n_0 ;\n wire \\wrlvl_redo_corse_inc[2]_i_2_n_0 ;\n wire \\wrlvl_redo_corse_inc[2]_i_3_n_0 ;\n wire \\wrlvl_redo_corse_inc[2]_i_4_n_0 ;\n wire \\wrlvl_redo_corse_inc[2]_i_7_n_0 ;\n wire [2:0]wrlvl_redo_corse_inc__0;\n wire [1:0]\\wrlvl_redo_corse_inc_reg[2]_0 ;\n wire [0:0]\\NLW_stg2_target_r_reg[4]_i_1_O_UNCONNECTED ;\n wire [3:3]\\NLW_stg2_target_r_reg[8]_i_1_CO_UNCONNECTED ;\n\n LUT6 #(\n .INIT(64'hFFFFFFBF00000000)) \n \\FSM_sequential_wl_state_r[0]_i_1 \n (.I0(\\FSM_sequential_wl_state_r[0]_i_2_n_0 ),\n .I1(out[4]),\n .I2(\\FSM_sequential_wl_state_r_reg[0]_0 ),\n .I3(out[1]),\n .I4(\\FSM_sequential_wl_state_r[0]_i_3_n_0 ),\n .I5(\\FSM_sequential_wl_state_r[0]_i_4_n_0 ),\n .O(\\FSM_sequential_wl_state_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hEEAEEEAEEEAEEFAF)) \n \\FSM_sequential_wl_state_r[0]_i_10 \n (.I0(out[4]),\n .I1(out[3]),\n .I2(out[0]),\n .I3(\\FSM_sequential_wl_state_r[3]_i_10_n_0 ),\n .I4(stable_cnt227_in),\n .I5(stable_cnt1),\n .O(\\FSM_sequential_wl_state_r[0]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\FSM_sequential_wl_state_r[0]_i_11 \n (.I0(out[3]),\n .I1(out[0]),\n .O(\\FSM_sequential_wl_state_r[0]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\FSM_sequential_wl_state_r[0]_i_13 \n (.I0(p_0_in),\n .I1(out[3]),\n .O(\\FSM_sequential_wl_state_r[0]_i_13_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair344\" *) \n LUT3 #(\n .INIT(8'hF4)) \n \\FSM_sequential_wl_state_r[0]_i_14 \n (.I0(wr_level_done_r5),\n .I1(wl_sm_start),\n .I2(wrlvl_byte_redo),\n .O(\\FSM_sequential_wl_state_r[0]_i_14_n_0 ));\n LUT5 #(\n .INIT(32'hFC7FFC7C)) \n \\FSM_sequential_wl_state_r[0]_i_15 \n (.I0(\\FSM_sequential_wl_state_r[3]_i_10_n_0 ),\n .I1(out[1]),\n .I2(out[3]),\n .I3(out[4]),\n .I4(wl_state_r1),\n .O(\\FSM_sequential_wl_state_r[0]_i_15_n_0 ));\n LUT6 #(\n .INIT(64'h3434343430333030)) \n \\FSM_sequential_wl_state_r[0]_i_16 \n (.I0(wr_level_done_r5),\n .I1(out[1]),\n .I2(out[4]),\n .I3(\\rd_data_edge_detect_r[3]_i_4_n_0 ),\n .I4(wrlvl_byte_redo),\n .I5(out[3]),\n .O(\\FSM_sequential_wl_state_r[0]_i_16_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair344\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\FSM_sequential_wl_state_r[0]_i_17 \n (.I0(wr_level_start_r),\n .I1(wl_sm_start),\n .I2(wr_level_done_r1_reg_0),\n .O(wl_state_r1));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\FSM_sequential_wl_state_r[0]_i_2 \n (.I0(\\rd_data_edge_detect_r[3]_i_5_n_0 ),\n .I1(out[0]),\n .I2(\\FSM_sequential_wl_state_r[0]_i_5_n_0 ),\n .I3(out[2]),\n .O(\\FSM_sequential_wl_state_r[0]_i_2_n_0 ));\n LUT3 #(\n .INIT(8'h7F)) \n \\FSM_sequential_wl_state_r[0]_i_3 \n (.I0(\\wl_corse_cnt[0][0][2]_i_2_n_0 ),\n .I1(\\wl_corse_cnt[0][0][0]_i_1_n_0 ),\n .I2(\\wl_corse_cnt[0][0][1]_i_1_n_0 ),\n .O(\\FSM_sequential_wl_state_r[0]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFAEAAAAAA)) \n \\FSM_sequential_wl_state_r[0]_i_4 \n (.I0(\\FSM_sequential_wl_state_r[0]_i_6_n_0 ),\n .I1(out[2]),\n .I2(out[0]),\n .I3(\\FSM_sequential_wl_state_r[3]_i_7_n_0 ),\n .I4(out[3]),\n .I5(\\FSM_sequential_wl_state_r[0]_i_7_n_0 ),\n .O(\\FSM_sequential_wl_state_r[0]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair310\" *) \n LUT3 #(\n .INIT(8'h7F)) \n \\FSM_sequential_wl_state_r[0]_i_5 \n (.I0(\\wl_tap_count_r_reg_n_0_[5] ),\n .I1(\\wl_tap_count_r_reg_n_0_[4] ),\n .I2(\\wl_tap_count_r_reg_n_0_[3] ),\n .O(\\FSM_sequential_wl_state_r[0]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hEA00000000000000)) \n \\FSM_sequential_wl_state_r[0]_i_6 \n (.I0(out[2]),\n .I1(out[3]),\n .I2(p_0_in),\n .I3(out[4]),\n .I4(\\FSM_sequential_wl_state_r[0]_i_8_n_0 ),\n .I5(\\FSM_sequential_wl_state_r[0]_i_9_n_0 ),\n .O(\\FSM_sequential_wl_state_r[0]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hB888FFFFB8880000)) \n \\FSM_sequential_wl_state_r[0]_i_7 \n (.I0(\\FSM_sequential_wl_state_r[0]_i_10_n_0 ),\n .I1(out[1]),\n .I2(\\FSM_sequential_wl_state_r[3]_i_9_n_0 ),\n .I3(\\FSM_sequential_wl_state_r[0]_i_11_n_0 ),\n .I4(out[2]),\n .I5(\\FSM_sequential_wl_state_r_reg[0]_i_12_n_0 ),\n .O(\\FSM_sequential_wl_state_r[0]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFF7FFFFFFFF)) \n \\FSM_sequential_wl_state_r[0]_i_8 \n (.I0(out[0]),\n .I1(dqs_count_r[0]),\n .I2(dqs_count_r[2]),\n .I3(\\FSM_sequential_wl_state_r[0]_i_13_n_0 ),\n .I4(\\FSM_sequential_wl_state_r[2]_i_10_n_0 ),\n .I5(dqs_count_r[1]),\n .O(\\FSM_sequential_wl_state_r[0]_i_8_n_0 ));\n LUT5 #(\n .INIT(32'hFF5D5D5D)) \n \\FSM_sequential_wl_state_r[0]_i_9 \n (.I0(out[0]),\n .I1(\\FSM_sequential_wl_state_r[3]_i_9_n_0 ),\n .I2(\\FSM_sequential_wl_state_r[0]_i_14_n_0 ),\n .I3(p_0_in),\n .I4(out[3]),\n .O(\\FSM_sequential_wl_state_r[0]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hA888A88888A88888)) \n \\FSM_sequential_wl_state_r[1]_i_1 \n (.I0(\\FSM_sequential_wl_state_r[1]_i_2_n_0 ),\n .I1(\\FSM_sequential_wl_state_r[1]_i_3_n_0 ),\n .I2(\\FSM_sequential_wl_state_r[1]_i_4_n_0 ),\n .I3(out[1]),\n .I4(out[4]),\n .I5(out[2]),\n .O(\\FSM_sequential_wl_state_r[1]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFA200)) \n \\FSM_sequential_wl_state_r[1]_i_10 \n (.I0(out[2]),\n .I1(out[4]),\n .I2(\\FSM_sequential_wl_state_r[2]_i_10_n_0 ),\n .I3(\\FSM_sequential_wl_state_r[3]_i_9_n_0 ),\n .I4(\\FSM_sequential_wl_state_r[1]_i_11_n_0 ),\n .O(\\FSM_sequential_wl_state_r[1]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'h00BB00BBFF0BFFBB)) \n \\FSM_sequential_wl_state_r[1]_i_11 \n (.I0(\\FSM_sequential_wl_state_r[0]_i_14_n_0 ),\n .I1(out[4]),\n .I2(\\rd_data_edge_detect_r[3]_i_4_n_0 ),\n .I3(out[3]),\n .I4(wrlvl_byte_redo),\n .I5(out[2]),\n .O(\\FSM_sequential_wl_state_r[1]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFDFFF)) \n \\FSM_sequential_wl_state_r[1]_i_2 \n (.I0(out[3]),\n .I1(\\FSM_sequential_wl_state_r[0]_i_3_n_0 ),\n .I2(\\FSM_sequential_wl_state_r_reg[0]_0 ),\n .I3(\\FSM_sequential_wl_state_r[1]_i_5_n_0 ),\n .I4(out[0]),\n .I5(out[1]),\n .O(\\FSM_sequential_wl_state_r[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h8F8F8F8F8F808080)) \n \\FSM_sequential_wl_state_r[1]_i_3 \n (.I0(\\FSM_sequential_wl_state_r[1]_i_6_n_0 ),\n .I1(\\FSM_sequential_wl_state_r[1]_i_7_n_0 ),\n .I2(out[0]),\n .I3(\\FSM_sequential_wl_state_r[1]_i_8_n_0 ),\n .I4(out[1]),\n .I5(\\FSM_sequential_wl_state_r[1]_i_9_n_0 ),\n .O(\\FSM_sequential_wl_state_r[1]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'h3FAAFF00)) \n \\FSM_sequential_wl_state_r[1]_i_4 \n (.I0(\\FSM_sequential_wl_state_r[3]_i_10_n_0 ),\n .I1(\\FSM_sequential_wl_state_r_reg[0]_0 ),\n .I2(\\rd_data_edge_detect_r[3]_i_5_n_0 ),\n .I3(out[4]),\n .I4(out[3]),\n .O(\\FSM_sequential_wl_state_r[1]_i_4_n_0 ));\n LUT4 #(\n .INIT(16'h4000)) \n \\FSM_sequential_wl_state_r[1]_i_5 \n (.I0(out[2]),\n .I1(\\wl_tap_count_r_reg_n_0_[3] ),\n .I2(\\wl_tap_count_r_reg_n_0_[4] ),\n .I3(\\wl_tap_count_r_reg_n_0_[5] ),\n .O(\\FSM_sequential_wl_state_r[1]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h7F7F7F7F7F7F7FFF)) \n \\FSM_sequential_wl_state_r[1]_i_6 \n (.I0(out[4]),\n .I1(wrlvl_byte_redo),\n .I2(out[2]),\n .I3(wrlvl_redo_corse_inc__0[1]),\n .I4(wrlvl_redo_corse_inc__0[0]),\n .I5(wrlvl_redo_corse_inc__0[2]),\n .O(\\FSM_sequential_wl_state_r[1]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h0007FFFF00070000)) \n \\FSM_sequential_wl_state_r[1]_i_7 \n (.I0(out[3]),\n .I1(wr_level_done_r5),\n .I2(out[4]),\n .I3(out[2]),\n .I4(out[1]),\n .I5(\\FSM_sequential_wl_state_r[1]_i_10_n_0 ),\n .O(\\FSM_sequential_wl_state_r[1]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hAAA8FFFFAAA8AAA8)) \n \\FSM_sequential_wl_state_r[1]_i_8 \n (.I0(out[4]),\n .I1(\\corse_dec[3][2]_i_2_n_0 ),\n .I2(\\corse_dec[3][2]_i_3_n_0 ),\n .I3(\\corse_dec[3][2]_i_4_n_0 ),\n .I4(\\FSM_sequential_wl_state_r[3]_i_10_n_0 ),\n .I5(out[3]),\n .O(\\FSM_sequential_wl_state_r[1]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'hAAA2A0A0AAA20000)) \n \\FSM_sequential_wl_state_r[1]_i_9 \n (.I0(out[2]),\n .I1(stable_cnt227_in),\n .I2(out[3]),\n .I3(stable_cnt1),\n .I4(out[1]),\n .I5(\\FSM_sequential_wl_state_r[2]_i_10_n_0 ),\n .O(\\FSM_sequential_wl_state_r[1]_i_9_n_0 ));\n LUT5 #(\n .INIT(32'hAAA8A8A8)) \n \\FSM_sequential_wl_state_r[2]_i_1 \n (.I0(\\FSM_sequential_wl_state_r[2]_i_2_n_0 ),\n .I1(\\FSM_sequential_wl_state_r[2]_i_3_n_0 ),\n .I2(\\FSM_sequential_wl_state_r_reg[2]_i_4_n_0 ),\n .I3(\\FSM_sequential_wl_state_r[2]_i_5_n_0 ),\n .I4(out[2]),\n .O(\\FSM_sequential_wl_state_r[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\FSM_sequential_wl_state_r[2]_i_10 \n (.I0(\\fine_inc[3][2]_i_3_n_0 ),\n .I1(\\fine_inc[3][2]_i_2_n_0 ),\n .I2(\\fine_inc[3][2]_i_4_n_0 ),\n .I3(\\fine_inc[3][5]_i_8_n_0 ),\n .I4(\\fine_inc[3][4]_i_3_n_0 ),\n .I5(\\fine_inc[3][4]_i_4_n_0 ),\n .O(\\FSM_sequential_wl_state_r[2]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'h1000100010001010)) \n \\FSM_sequential_wl_state_r[2]_i_11 \n (.I0(out[3]),\n .I1(out[0]),\n .I2(out[2]),\n .I3(out[4]),\n .I4(stable_cnt227_in),\n .I5(stable_cnt1),\n .O(\\FSM_sequential_wl_state_r[2]_i_11_n_0 ));\n LUT5 #(\n .INIT(32'h00200000)) \n \\FSM_sequential_wl_state_r[2]_i_12 \n (.I0(\\rd_data_edge_detect_r[3]_i_4_n_0 ),\n .I1(out[1]),\n .I2(out[0]),\n .I3(out[4]),\n .I4(wrlvl_byte_redo),\n .O(\\FSM_sequential_wl_state_r[2]_i_12_n_0 ));\n LUT5 #(\n .INIT(32'h10101F10)) \n \\FSM_sequential_wl_state_r[2]_i_13 \n (.I0(\\FSM_sequential_wl_state_r_reg[0]_0 ),\n .I1(out[0]),\n .I2(out[4]),\n .I3(out[1]),\n .I4(\\FSM_sequential_wl_state_r[3]_i_10_n_0 ),\n .O(\\FSM_sequential_wl_state_r[2]_i_13_n_0 ));\n LUT6 #(\n .INIT(64'h0B3B0B0B3B3B3B3B)) \n \\FSM_sequential_wl_state_r[2]_i_14 \n (.I0(out[0]),\n .I1(out[3]),\n .I2(\\FSM_sequential_wl_state_r[3]_i_9_n_0 ),\n .I3(wr_level_done_r5),\n .I4(wl_sm_start),\n .I5(out[4]),\n .O(\\FSM_sequential_wl_state_r[2]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'h011F077F077F077F)) \n \\FSM_sequential_wl_state_r[2]_i_15 \n (.I0(\\wl_corse_cnt[0][0][1]_i_1_n_0 ),\n .I1(wrlvl_redo_corse_inc__0[1]),\n .I2(\\wl_corse_cnt[0][0][2]_i_2_n_0 ),\n .I3(wrlvl_redo_corse_inc__0[2]),\n .I4(wrlvl_redo_corse_inc__0[0]),\n .I5(\\wl_corse_cnt[0][0][0]_i_1_n_0 ),\n .O(\\FSM_sequential_wl_state_r[2]_i_15_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF7FFF00000000)) \n \\FSM_sequential_wl_state_r[2]_i_2 \n (.I0(\\FSM_sequential_wl_state_r[2]_i_6_n_0 ),\n .I1(out[4]),\n .I2(out[0]),\n .I3(wrlvl_byte_redo),\n .I4(out[1]),\n .I5(\\FSM_sequential_wl_state_r[2]_i_7_n_0 ),\n .O(\\FSM_sequential_wl_state_r[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFAAAAAAAE)) \n \\FSM_sequential_wl_state_r[2]_i_3 \n (.I0(\\FSM_sequential_wl_state_r[2]_i_8_n_0 ),\n .I1(out[2]),\n .I2(\\FSM_sequential_wl_state_r[2]_i_9_n_0 ),\n .I3(out[1]),\n .I4(\\FSM_sequential_wl_state_r[2]_i_10_n_0 ),\n .I5(\\FSM_sequential_wl_state_r[2]_i_11_n_0 ),\n .O(\\FSM_sequential_wl_state_r[2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hBFAFBFAFB0AFB0A0)) \n \\FSM_sequential_wl_state_r[2]_i_5 \n (.I0(out[4]),\n .I1(out[0]),\n .I2(out[1]),\n .I3(out[3]),\n .I4(wrlvl_byte_redo),\n .I5(\\FSM_sequential_wl_state_r[2]_i_14_n_0 ),\n .O(\\FSM_sequential_wl_state_r[2]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair333\" *) \n LUT3 #(\n .INIT(8'h01)) \n \\FSM_sequential_wl_state_r[2]_i_6 \n (.I0(wrlvl_redo_corse_inc__0[1]),\n .I1(wrlvl_redo_corse_inc__0[0]),\n .I2(wrlvl_redo_corse_inc__0[2]),\n .O(\\FSM_sequential_wl_state_r[2]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFDFFDFFFFFFFF)) \n \\FSM_sequential_wl_state_r[2]_i_7 \n (.I0(out[0]),\n .I1(\\FSM_sequential_wl_state_r[2]_i_15_n_0 ),\n .I2(out[2]),\n .I3(out[1]),\n .I4(out[4]),\n .I5(wrlvl_byte_redo),\n .O(\\FSM_sequential_wl_state_r[2]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h0500000035330000)) \n \\FSM_sequential_wl_state_r[2]_i_8 \n (.I0(\\FSM_sequential_wl_state_r[3]_i_10_n_0 ),\n .I1(out[4]),\n .I2(out[0]),\n .I3(out[3]),\n .I4(out[1]),\n .I5(out[2]),\n .O(\\FSM_sequential_wl_state_r[2]_i_8_n_0 ));\n LUT5 #(\n .INIT(32'h8888F888)) \n \\FSM_sequential_wl_state_r[2]_i_9 \n (.I0(out[0]),\n .I1(out[3]),\n .I2(dqs_count_r[1]),\n .I3(dqs_count_r[0]),\n .I4(dqs_count_r[2]),\n .O(\\FSM_sequential_wl_state_r[2]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFEFEAEFEAEFEA)) \n \\FSM_sequential_wl_state_r[3]_i_1 \n (.I0(\\FSM_sequential_wl_state_r[3]_i_2_n_0 ),\n .I1(\\FSM_sequential_wl_state_r[3]_i_3_n_0 ),\n .I2(out[0]),\n .I3(\\FSM_sequential_wl_state_r[3]_i_4_n_0 ),\n .I4(out[3]),\n .I5(\\FSM_sequential_wl_state_r[3]_i_5_n_0 ),\n .O(\\FSM_sequential_wl_state_r[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\FSM_sequential_wl_state_r[3]_i_10 \n (.I0(fine_dec_cnt__0[5]),\n .I1(fine_dec_cnt__0[3]),\n .I2(fine_dec_cnt__0[1]),\n .I3(fine_dec_cnt__0[0]),\n .I4(fine_dec_cnt__0[2]),\n .I5(fine_dec_cnt__0[4]),\n .O(\\FSM_sequential_wl_state_r[3]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'h0100010005AA0500)) \n \\FSM_sequential_wl_state_r[3]_i_2 \n (.I0(out[1]),\n .I1(\\FSM_sequential_wl_state_r[3]_i_6_n_0 ),\n .I2(out[2]),\n .I3(out[3]),\n .I4(out[0]),\n .I5(out[4]),\n .O(\\FSM_sequential_wl_state_r[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h6200000062626262)) \n \\FSM_sequential_wl_state_r[3]_i_3 \n (.I0(out[4]),\n .I1(out[1]),\n .I2(wr_level_done_r5),\n .I3(\\FSM_sequential_wl_state_r[3]_i_7_n_0 ),\n .I4(\\FSM_sequential_wl_state_r[3]_i_8_n_0 ),\n .I5(out[2]),\n .O(\\FSM_sequential_wl_state_r[3]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'h00400000)) \n \\FSM_sequential_wl_state_r[3]_i_4 \n (.I0(stable_cnt1),\n .I1(out[1]),\n .I2(out[2]),\n .I3(out[4]),\n .I4(stable_cnt227_in),\n .O(\\FSM_sequential_wl_state_r[3]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h33BB338830883088)) \n \\FSM_sequential_wl_state_r[3]_i_5 \n (.I0(\\FSM_sequential_wl_state_r[3]_i_9_n_0 ),\n .I1(out[0]),\n .I2(\\FSM_sequential_wl_state_r[3]_i_10_n_0 ),\n .I3(out[1]),\n .I4(\\FSM_sequential_wl_state_r[3]_i_7_n_0 ),\n .I5(out[2]),\n .O(\\FSM_sequential_wl_state_r[3]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair310\" *) \n LUT5 #(\n .INIT(32'h5555D555)) \n \\FSM_sequential_wl_state_r[3]_i_6 \n (.I0(\\FSM_sequential_wl_state_r_reg[0]_0 ),\n .I1(\\wl_tap_count_r_reg_n_0_[5] ),\n .I2(\\wl_tap_count_r_reg_n_0_[4] ),\n .I3(\\wl_tap_count_r_reg_n_0_[3] ),\n .I4(\\rd_data_edge_detect_r[3]_i_5_n_0 ),\n .O(\\FSM_sequential_wl_state_r[3]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair315\" *) \n LUT4 #(\n .INIT(16'hFFF7)) \n \\FSM_sequential_wl_state_r[3]_i_7 \n (.I0(dqs_count_r[0]),\n .I1(dqs_count_r[1]),\n .I2(\\FSM_sequential_wl_state_r[2]_i_10_n_0 ),\n .I3(dqs_count_r[2]),\n .O(\\FSM_sequential_wl_state_r[3]_i_7_n_0 ));\n LUT5 #(\n .INIT(32'h00005100)) \n \\FSM_sequential_wl_state_r[3]_i_8 \n (.I0(wrlvl_byte_redo),\n .I1(wl_sm_start),\n .I2(wr_level_done_r5),\n .I3(\\FSM_sequential_wl_state_r[3]_i_9_n_0 ),\n .I4(out[1]),\n .O(\\FSM_sequential_wl_state_r[3]_i_8_n_0 ));\n LUT3 #(\n .INIT(8'h01)) \n \\FSM_sequential_wl_state_r[3]_i_9 \n (.I0(\\corse_inc[3][0]_i_2_n_0 ),\n .I1(\\corse_inc[3][2]_i_4_n_0 ),\n .I2(\\corse_inc[3][2]_i_5_n_0 ),\n .O(\\FSM_sequential_wl_state_r[3]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF03031D1C)) \n \\FSM_sequential_wl_state_r[4]_i_1 \n (.I0(out[0]),\n .I1(out[4]),\n .I2(out[2]),\n .I3(\\FSM_sequential_wl_state_r[4]_i_3_n_0 ),\n .I4(out[1]),\n .I5(\\FSM_sequential_wl_state_r_reg[4]_i_4_n_0 ),\n .O(\\FSM_sequential_wl_state_r[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hE0FFFF00E000FF00)) \n \\FSM_sequential_wl_state_r[4]_i_10 \n (.I0(wr_level_done_r5),\n .I1(wrlvl_byte_redo_reg),\n .I2(out[4]),\n .I3(out[0]),\n .I4(out[2]),\n .I5(\\FSM_sequential_wl_state_r[4]_i_12_n_0 ),\n .O(\\FSM_sequential_wl_state_r[4]_i_10_n_0 ));\n LUT4 #(\n .INIT(16'hF8FA)) \n \\FSM_sequential_wl_state_r[4]_i_11 \n (.I0(wr_level_done_r5),\n .I1(\\FSM_sequential_wl_state_r[2]_i_10_n_0 ),\n .I2(out[1]),\n .I3(\\FSM_sequential_wl_state_r[3]_i_9_n_0 ),\n .O(\\FSM_sequential_wl_state_r[4]_i_11_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair318\" *) \n LUT4 #(\n .INIT(16'h0010)) \n \\FSM_sequential_wl_state_r[4]_i_12 \n (.I0(incdec_wait_cnt_reg__0[1]),\n .I1(incdec_wait_cnt_reg__0[0]),\n .I2(incdec_wait_cnt_reg__0[3]),\n .I3(incdec_wait_cnt_reg__0[2]),\n .O(\\FSM_sequential_wl_state_r[4]_i_12_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF080403070804)) \n \\FSM_sequential_wl_state_r[4]_i_2 \n (.I0(out[0]),\n .I1(out[2]),\n .I2(out[3]),\n .I3(out[1]),\n .I4(out[4]),\n .I5(\\FSM_sequential_wl_state_r[4]_i_5_n_0 ),\n .O(\\FSM_sequential_wl_state_r[4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h08FF080808080808)) \n \\FSM_sequential_wl_state_r[4]_i_3 \n (.I0(early1_data_reg),\n .I1(wrlvl_byte_redo),\n .I2(wrlvl_byte_redo_r),\n .I3(wr_level_done_r1_reg_0),\n .I4(wl_sm_start),\n .I5(wr_level_start_r),\n .O(\\FSM_sequential_wl_state_r[4]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h000000000F0FBBB0)) \n \\FSM_sequential_wl_state_r[4]_i_5 \n (.I0(\\rd_data_edge_detect_r[3]_i_5_n_0 ),\n .I1(out[3]),\n .I2(out[1]),\n .I3(\\FSM_sequential_wl_state_r_reg[0]_0 ),\n .I4(out[0]),\n .I5(\\FSM_sequential_wl_state_r[4]_i_9_n_0 ),\n .O(\\FSM_sequential_wl_state_r[4]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hF0F0FFFCF0F02020)) \n \\FSM_sequential_wl_state_r[4]_i_7 \n (.I0(out[2]),\n .I1(out[4]),\n .I2(wl_sm_start),\n .I3(wrlvl_byte_redo),\n .I4(out[1]),\n .I5(\\FSM_sequential_wl_state_r[4]_i_10_n_0 ),\n .O(\\FSM_sequential_wl_state_r[4]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h22222020FFF000FF)) \n \\FSM_sequential_wl_state_r[4]_i_8 \n (.I0(\\FSM_sequential_wl_state_r[4]_i_11_n_0 ),\n .I1(out[4]),\n .I2(\\FSM_sequential_wl_state_r[4]_i_12_n_0 ),\n .I3(out[1]),\n .I4(out[0]),\n .I5(out[2]),\n .O(\\FSM_sequential_wl_state_r[4]_i_8_n_0 ));\n LUT5 #(\n .INIT(32'h00005545)) \n \\FSM_sequential_wl_state_r[4]_i_9 \n (.I0(out[3]),\n .I1(wr_level_done_r5),\n .I2(wl_sm_start),\n .I3(wrlvl_byte_redo),\n .I4(out[1]),\n .O(\\FSM_sequential_wl_state_r[4]_i_9_n_0 ));\n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\FSM_sequential_wl_state_r_reg[0] \n (.C(CLK),\n .CE(\\FSM_sequential_wl_state_r[4]_i_1_n_0 ),\n .D(\\FSM_sequential_wl_state_r[0]_i_1_n_0 ),\n .Q(out[0]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n MUXF7 \\FSM_sequential_wl_state_r_reg[0]_i_12 \n (.I0(\\FSM_sequential_wl_state_r[0]_i_15_n_0 ),\n .I1(\\FSM_sequential_wl_state_r[0]_i_16_n_0 ),\n .O(\\FSM_sequential_wl_state_r_reg[0]_i_12_n_0 ),\n .S(out[0]));\n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\FSM_sequential_wl_state_r_reg[1] \n (.C(CLK),\n .CE(\\FSM_sequential_wl_state_r[4]_i_1_n_0 ),\n .D(\\FSM_sequential_wl_state_r[1]_i_1_n_0 ),\n .Q(out[1]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\FSM_sequential_wl_state_r_reg[2] \n (.C(CLK),\n .CE(\\FSM_sequential_wl_state_r[4]_i_1_n_0 ),\n .D(\\FSM_sequential_wl_state_r[2]_i_1_n_0 ),\n .Q(out[2]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n MUXF7 \\FSM_sequential_wl_state_r_reg[2]_i_4 \n (.I0(\\FSM_sequential_wl_state_r[2]_i_12_n_0 ),\n .I1(\\FSM_sequential_wl_state_r[2]_i_13_n_0 ),\n .O(\\FSM_sequential_wl_state_r_reg[2]_i_4_n_0 ),\n .S(out[3]));\n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\FSM_sequential_wl_state_r_reg[3] \n (.C(CLK),\n .CE(\\FSM_sequential_wl_state_r[4]_i_1_n_0 ),\n .D(\\FSM_sequential_wl_state_r[3]_i_1_n_0 ),\n .Q(out[3]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\FSM_sequential_wl_state_r_reg[4] \n (.C(CLK),\n .CE(\\FSM_sequential_wl_state_r[4]_i_1_n_0 ),\n .D(\\FSM_sequential_wl_state_r[4]_i_2_n_0 ),\n .Q(out[4]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n MUXF7 \\FSM_sequential_wl_state_r_reg[4]_i_4 \n (.I0(\\FSM_sequential_wl_state_r[4]_i_7_n_0 ),\n .I1(\\FSM_sequential_wl_state_r[4]_i_8_n_0 ),\n .O(\\FSM_sequential_wl_state_r_reg[4]_i_4_n_0 ),\n .S(out[3]));\n (* SOFT_HLUTNM = \"soft_lutpair345\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\corse_cnt[0][0]_i_1 \n (.I0(corse_cnt[0]),\n .I1(\\corse_cnt[0][2]_i_3_n_0 ),\n .I2(\\corse_cnt_reg_n_0_[0][0] ),\n .O(\\corse_cnt[0][0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00F000F088F8FFF8)) \n \\corse_cnt[0][0]_i_2 \n (.I0(\\corse_cnt[0][0]_i_3_n_0 ),\n .I1(out[0]),\n .I2(\\corse_cnt[0][0]_i_4_n_0 ),\n .I3(out[2]),\n .I4(\\wl_corse_cnt[0][0][0]_i_1_n_0 ),\n .I5(out[3]),\n .O(corse_cnt[0]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\corse_cnt[0][0]_i_3 \n (.I0(\\final_coarse_tap_reg_n_0_[3][0] ),\n .I1(\\final_coarse_tap_reg_n_0_[1][0] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\final_coarse_tap_reg_n_0_[2][0] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\final_coarse_tap_reg_n_0_[0][0] ),\n .O(\\corse_cnt[0][0]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'h8830)) \n \\corse_cnt[0][0]_i_4 \n (.I0(p_0_in),\n .I1(out[0]),\n .I2(final_coarse_tap),\n .I3(out[1]),\n .O(\\corse_cnt[0][0]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\corse_cnt[0][0]_i_5 \n (.I0(\\final_coarse_tap_reg_n_0_[3][0] ),\n .I1(\\final_coarse_tap_reg_n_0_[1][0] ),\n .I2(\\po_stg2_wrcal_cnt_reg[2] [0]),\n .I3(\\final_coarse_tap_reg_n_0_[2][0] ),\n .I4(\\po_stg2_wrcal_cnt_reg[2] [1]),\n .I5(\\final_coarse_tap_reg_n_0_[0][0] ),\n .O(final_coarse_tap));\n (* SOFT_HLUTNM = \"soft_lutpair334\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\corse_cnt[0][1]_i_1 \n (.I0(corse_cnt[1]),\n .I1(\\corse_cnt[0][2]_i_3_n_0 ),\n .I2(\\corse_cnt_reg_n_0_[0][1] ),\n .O(\\corse_cnt[0][1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFF080808FF08)) \n \\corse_cnt[0][1]_i_2 \n (.I0(\\corse_cnt[0][1]_i_3_n_0 ),\n .I1(out[0]),\n .I2(out[3]),\n .I3(\\corse_cnt[0][1]_i_4_n_0 ),\n .I4(out[2]),\n .I5(\\corse_cnt[0][1]_i_5_n_0 ),\n .O(corse_cnt[1]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\corse_cnt[0][1]_i_3 \n (.I0(\\final_coarse_tap_reg_n_0_[3][1] ),\n .I1(\\final_coarse_tap_reg_n_0_[1][1] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\final_coarse_tap_reg_n_0_[2][1] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\final_coarse_tap_reg_n_0_[0][1] ),\n .O(\\corse_cnt[0][1]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'h8830)) \n \\corse_cnt[0][1]_i_4 \n (.I0(p_0_in),\n .I1(out[0]),\n .I2(\\wrlvl_redo_corse_inc_reg[2]_0 [0]),\n .I3(out[1]),\n .O(\\corse_cnt[0][1]_i_4_n_0 ));\n LUT3 #(\n .INIT(8'h06)) \n \\corse_cnt[0][1]_i_5 \n (.I0(\\wl_corse_cnt[0][0][0]_i_1_n_0 ),\n .I1(\\wl_corse_cnt[0][0][1]_i_1_n_0 ),\n .I2(out[3]),\n .O(\\corse_cnt[0][1]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair335\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\corse_cnt[0][2]_i_1 \n (.I0(corse_cnt[2]),\n .I1(\\corse_cnt[0][2]_i_3_n_0 ),\n .I2(\\corse_cnt_reg_n_0_[0][2] ),\n .O(\\corse_cnt[0][2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAA00010000)) \n \\corse_cnt[0][2]_i_10 \n (.I0(out[1]),\n .I1(dqs_count_r[2]),\n .I2(dqs_count_r[1]),\n .I3(dqs_count_r[0]),\n .I4(wrlvl_final_mux),\n .I5(out[3]),\n .O(\\corse_cnt[0][2]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFF080808FF08)) \n \\corse_cnt[0][2]_i_2 \n (.I0(\\corse_cnt[0][2]_i_4_n_0 ),\n .I1(out[0]),\n .I2(out[3]),\n .I3(\\corse_cnt[0][2]_i_5_n_0 ),\n .I4(out[2]),\n .I5(\\corse_cnt[0][2]_i_6_n_0 ),\n .O(corse_cnt[2]));\n LUT6 #(\n .INIT(64'h0040004055400040)) \n \\corse_cnt[0][2]_i_3 \n (.I0(\\corse_cnt[0][2]_i_7_n_0 ),\n .I1(\\corse_cnt[0][2]_i_8_n_0 ),\n .I2(\\corse_cnt[0][2]_i_9_n_0 ),\n .I3(out[0]),\n .I4(\\corse_cnt[0][2]_i_10_n_0 ),\n .I5(out[2]),\n .O(\\corse_cnt[0][2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\corse_cnt[0][2]_i_4 \n (.I0(\\final_coarse_tap_reg_n_0_[3][2] ),\n .I1(\\final_coarse_tap_reg_n_0_[1][2] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\final_coarse_tap_reg_n_0_[2][2] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\final_coarse_tap_reg_n_0_[0][2] ),\n .O(\\corse_cnt[0][2]_i_4_n_0 ));\n LUT4 #(\n .INIT(16'h8830)) \n \\corse_cnt[0][2]_i_5 \n (.I0(p_0_in),\n .I1(out[0]),\n .I2(\\wrlvl_redo_corse_inc_reg[2]_0 [1]),\n .I3(out[1]),\n .O(\\corse_cnt[0][2]_i_5_n_0 ));\n LUT4 #(\n .INIT(16'h0078)) \n \\corse_cnt[0][2]_i_6 \n (.I0(\\wl_corse_cnt[0][0][1]_i_1_n_0 ),\n .I1(\\wl_corse_cnt[0][0][0]_i_1_n_0 ),\n .I2(\\wl_corse_cnt[0][0][2]_i_2_n_0 ),\n .I3(out[3]),\n .O(\\corse_cnt[0][2]_i_6_n_0 ));\n LUT3 #(\n .INIT(8'hBC)) \n \\corse_cnt[0][2]_i_7 \n (.I0(p_0_in),\n .I1(out[3]),\n .I2(out[4]),\n .O(\\corse_cnt[0][2]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h202020202F202020)) \n \\corse_cnt[0][2]_i_8 \n (.I0(\\fine_inc[0][5]_i_3_n_0 ),\n .I1(\\dqs_count_r[0]_i_8_n_0 ),\n .I2(out[2]),\n .I3(\\po_stg2_wrcal_cnt_reg[0] ),\n .I4(done_dqs_dec239_out),\n .I5(\\po_stg2_wrcal_cnt_reg[2] [1]),\n .O(\\corse_cnt[0][2]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h1)) \n \\corse_cnt[0][2]_i_9 \n (.I0(out[3]),\n .I1(out[1]),\n .O(\\corse_cnt[0][2]_i_9_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair332\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\corse_cnt[1][0]_i_1 \n (.I0(corse_cnt[0]),\n .I1(\\corse_cnt[1][2]_i_2_n_0 ),\n .I2(\\corse_cnt_reg_n_0_[1][0] ),\n .O(\\corse_cnt[1][0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair336\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\corse_cnt[1][1]_i_1 \n (.I0(corse_cnt[1]),\n .I1(\\corse_cnt[1][2]_i_2_n_0 ),\n .I2(\\corse_cnt_reg_n_0_[1][1] ),\n .O(\\corse_cnt[1][1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair337\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\corse_cnt[1][2]_i_1 \n (.I0(corse_cnt[2]),\n .I1(\\corse_cnt[1][2]_i_2_n_0 ),\n .I2(\\corse_cnt_reg_n_0_[1][2] ),\n .O(\\corse_cnt[1][2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0040004055400040)) \n \\corse_cnt[1][2]_i_2 \n (.I0(\\corse_cnt[0][2]_i_7_n_0 ),\n .I1(\\corse_cnt[1][2]_i_3_n_0 ),\n .I2(\\corse_cnt[0][2]_i_9_n_0 ),\n .I3(out[0]),\n .I4(\\corse_cnt[1][2]_i_4_n_0 ),\n .I5(out[2]),\n .O(\\corse_cnt[1][2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h8A008A008A008AFF)) \n \\corse_cnt[1][2]_i_3 \n (.I0(\\fine_inc[1][5]_i_3_n_0 ),\n .I1(wrlvl_byte_redo),\n .I2(wr_level_done_r5),\n .I3(out[2]),\n .I4(\\po_stg2_wrcal_cnt_reg[2] [1]),\n .I5(\\po_stg2_wrcal_cnt_reg[2]_0 ),\n .O(\\corse_cnt[1][2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAA00100000)) \n \\corse_cnt[1][2]_i_4 \n (.I0(out[1]),\n .I1(dqs_count_r[2]),\n .I2(dqs_count_r[0]),\n .I3(dqs_count_r[1]),\n .I4(wrlvl_final_mux),\n .I5(out[3]),\n .O(\\corse_cnt[1][2]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair345\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\corse_cnt[2][0]_i_1 \n (.I0(corse_cnt[0]),\n .I1(\\corse_cnt[2][2]_i_2_n_0 ),\n .I2(\\corse_cnt_reg_n_0_[2][0] ),\n .O(\\corse_cnt[2][0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair336\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\corse_cnt[2][1]_i_1 \n (.I0(corse_cnt[1]),\n .I1(\\corse_cnt[2][2]_i_2_n_0 ),\n .I2(\\corse_cnt_reg_n_0_[2][1] ),\n .O(\\corse_cnt[2][1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair335\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\corse_cnt[2][2]_i_1 \n (.I0(corse_cnt[2]),\n .I1(\\corse_cnt[2][2]_i_2_n_0 ),\n .I2(\\corse_cnt_reg_n_0_[2][2] ),\n .O(\\corse_cnt[2][2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0040004055400040)) \n \\corse_cnt[2][2]_i_2 \n (.I0(\\corse_cnt[0][2]_i_7_n_0 ),\n .I1(\\corse_cnt[2][2]_i_3_n_0 ),\n .I2(\\corse_cnt[0][2]_i_9_n_0 ),\n .I3(out[0]),\n .I4(\\corse_cnt[2][2]_i_4_n_0 ),\n .I5(out[2]),\n .O(\\corse_cnt[2][2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h202020202020202F)) \n \\corse_cnt[2][2]_i_3 \n (.I0(\\fine_inc[2][5]_i_3_n_0 ),\n .I1(\\dqs_count_r[0]_i_8_n_0 ),\n .I2(out[2]),\n .I3(\\po_stg2_wrcal_cnt_reg[2] [2]),\n .I4(\\po_stg2_wrcal_cnt_reg[2] [0]),\n .I5(\\po_stg2_wrcal_cnt_reg[1] ),\n .O(\\corse_cnt[2][2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAA00100000)) \n \\corse_cnt[2][2]_i_4 \n (.I0(out[1]),\n .I1(dqs_count_r[2]),\n .I2(dqs_count_r[1]),\n .I3(dqs_count_r[0]),\n .I4(wrlvl_final_mux),\n .I5(out[3]),\n .O(\\corse_cnt[2][2]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair332\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\corse_cnt[3][0]_i_1 \n (.I0(corse_cnt[0]),\n .I1(\\corse_cnt[3][2]_i_2_n_0 ),\n .I2(\\corse_cnt_reg_n_0_[3][0] ),\n .O(\\corse_cnt[3][0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair334\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\corse_cnt[3][1]_i_1 \n (.I0(corse_cnt[1]),\n .I1(\\corse_cnt[3][2]_i_2_n_0 ),\n .I2(\\corse_cnt_reg_n_0_[3][1] ),\n .O(\\corse_cnt[3][1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair337\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\corse_cnt[3][2]_i_1 \n (.I0(corse_cnt[2]),\n .I1(\\corse_cnt[3][2]_i_2_n_0 ),\n .I2(\\corse_cnt_reg_n_0_[3][2] ),\n .O(\\corse_cnt[3][2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000455550004)) \n \\corse_cnt[3][2]_i_2 \n (.I0(\\corse_cnt[0][2]_i_7_n_0 ),\n .I1(\\corse_cnt[3][2]_i_3_n_0 ),\n .I2(out[3]),\n .I3(out[1]),\n .I4(out[0]),\n .I5(\\corse_cnt[3][2]_i_4_n_0 ),\n .O(\\corse_cnt[3][2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h8A008A008AFF8A00)) \n \\corse_cnt[3][2]_i_3 \n (.I0(\\fine_inc[3][5]_i_5_n_0 ),\n .I1(wrlvl_byte_redo),\n .I2(wr_level_done_r5),\n .I3(out[2]),\n .I4(\\po_stg2_wrcal_cnt_reg[2] [1]),\n .I5(\\po_stg2_wrcal_cnt_reg[2]_0 ),\n .O(\\corse_cnt[3][2]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hBBBBEFFF)) \n \\corse_cnt[3][2]_i_4 \n (.I0(out[2]),\n .I1(out[3]),\n .I2(wrlvl_final_mux),\n .I3(\\fine_inc[3][5]_i_5_n_0 ),\n .I4(out[1]),\n .O(\\corse_cnt[3][2]_i_4_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\corse_cnt_reg[0][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_cnt[0][0]_i_1_n_0 ),\n .Q(\\corse_cnt_reg_n_0_[0][0] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\corse_cnt_reg[0][1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_cnt[0][1]_i_1_n_0 ),\n .Q(\\corse_cnt_reg_n_0_[0][1] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\corse_cnt_reg[0][2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_cnt[0][2]_i_1_n_0 ),\n .Q(\\corse_cnt_reg_n_0_[0][2] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\corse_cnt_reg[1][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_cnt[1][0]_i_1_n_0 ),\n .Q(\\corse_cnt_reg_n_0_[1][0] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\corse_cnt_reg[1][1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_cnt[1][1]_i_1_n_0 ),\n .Q(\\corse_cnt_reg_n_0_[1][1] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\corse_cnt_reg[1][2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_cnt[1][2]_i_1_n_0 ),\n .Q(\\corse_cnt_reg_n_0_[1][2] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\corse_cnt_reg[2][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_cnt[2][0]_i_1_n_0 ),\n .Q(\\corse_cnt_reg_n_0_[2][0] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\corse_cnt_reg[2][1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_cnt[2][1]_i_1_n_0 ),\n .Q(\\corse_cnt_reg_n_0_[2][1] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\corse_cnt_reg[2][2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_cnt[2][2]_i_1_n_0 ),\n .Q(\\corse_cnt_reg_n_0_[2][2] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\corse_cnt_reg[3][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_cnt[3][0]_i_1_n_0 ),\n .Q(\\corse_cnt_reg_n_0_[3][0] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\corse_cnt_reg[3][1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_cnt[3][1]_i_1_n_0 ),\n .Q(\\corse_cnt_reg_n_0_[3][1] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\corse_cnt_reg[3][2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_cnt[3][2]_i_1_n_0 ),\n .Q(\\corse_cnt_reg_n_0_[3][2] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n LUT6 #(\n .INIT(64'h000EFFFF000E0000)) \n \\corse_dec[0][0]_i_1 \n (.I0(\\corse_dec[3][2]_i_3_n_0 ),\n .I1(\\corse_dec[3][2]_i_4_n_0 ),\n .I2(\\corse_dec[3][2]_i_2_n_0 ),\n .I3(out[3]),\n .I4(\\corse_dec[0][2]_i_2_n_0 ),\n .I5(\\corse_dec_reg_n_0_[0][0] ),\n .O(\\corse_dec[0][0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00C2FFFF00C20000)) \n \\corse_dec[0][1]_i_1 \n (.I0(\\corse_dec[3][2]_i_3_n_0 ),\n .I1(\\corse_dec[3][2]_i_4_n_0 ),\n .I2(\\corse_dec[3][2]_i_2_n_0 ),\n .I3(out[3]),\n .I4(\\corse_dec[0][2]_i_2_n_0 ),\n .I5(\\corse_dec_reg_n_0_[0][1] ),\n .O(\\corse_dec[0][1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00C8FFFF00C80000)) \n \\corse_dec[0][2]_i_1 \n (.I0(\\corse_dec[3][2]_i_2_n_0 ),\n .I1(\\corse_dec[3][2]_i_3_n_0 ),\n .I2(\\corse_dec[3][2]_i_4_n_0 ),\n .I3(out[3]),\n .I4(\\corse_dec[0][2]_i_2_n_0 ),\n .I5(\\corse_dec_reg_n_0_[0][2] ),\n .O(\\corse_dec[0][2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0001000000000000)) \n \\corse_dec[0][2]_i_2 \n (.I0(out[0]),\n .I1(out[1]),\n .I2(out[2]),\n .I3(out[3]),\n .I4(out[4]),\n .I5(\\fine_inc[0][5]_i_3_n_0 ),\n .O(\\corse_dec[0][2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h000EFFFF000E0000)) \n \\corse_dec[1][0]_i_1 \n (.I0(\\corse_dec[3][2]_i_3_n_0 ),\n .I1(\\corse_dec[3][2]_i_4_n_0 ),\n .I2(\\corse_dec[3][2]_i_2_n_0 ),\n .I3(out[3]),\n .I4(\\corse_dec[1][2]_i_2_n_0 ),\n .I5(\\corse_dec_reg_n_0_[1][0] ),\n .O(\\corse_dec[1][0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00C2FFFF00C20000)) \n \\corse_dec[1][1]_i_1 \n (.I0(\\corse_dec[3][2]_i_3_n_0 ),\n .I1(\\corse_dec[3][2]_i_4_n_0 ),\n .I2(\\corse_dec[3][2]_i_2_n_0 ),\n .I3(out[3]),\n .I4(\\corse_dec[1][2]_i_2_n_0 ),\n .I5(\\corse_dec_reg_n_0_[1][1] ),\n .O(\\corse_dec[1][1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00C8FFFF00C80000)) \n \\corse_dec[1][2]_i_1 \n (.I0(\\corse_dec[3][2]_i_2_n_0 ),\n .I1(\\corse_dec[3][2]_i_3_n_0 ),\n .I2(\\corse_dec[3][2]_i_4_n_0 ),\n .I3(out[3]),\n .I4(\\corse_dec[1][2]_i_2_n_0 ),\n .I5(\\corse_dec_reg_n_0_[1][2] ),\n .O(\\corse_dec[1][2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0001000000000000)) \n \\corse_dec[1][2]_i_2 \n (.I0(out[0]),\n .I1(out[1]),\n .I2(out[2]),\n .I3(out[3]),\n .I4(out[4]),\n .I5(\\fine_inc[1][5]_i_3_n_0 ),\n .O(\\corse_dec[1][2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h000EFFFF000E0000)) \n \\corse_dec[2][0]_i_1 \n (.I0(\\corse_dec[3][2]_i_3_n_0 ),\n .I1(\\corse_dec[3][2]_i_4_n_0 ),\n .I2(\\corse_dec[3][2]_i_2_n_0 ),\n .I3(out[3]),\n .I4(\\corse_dec[2][2]_i_2_n_0 ),\n .I5(\\corse_dec_reg_n_0_[2][0] ),\n .O(\\corse_dec[2][0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00C2FFFF00C20000)) \n \\corse_dec[2][1]_i_1 \n (.I0(\\corse_dec[3][2]_i_3_n_0 ),\n .I1(\\corse_dec[3][2]_i_4_n_0 ),\n .I2(\\corse_dec[3][2]_i_2_n_0 ),\n .I3(out[3]),\n .I4(\\corse_dec[2][2]_i_2_n_0 ),\n .I5(\\corse_dec_reg_n_0_[2][1] ),\n .O(\\corse_dec[2][1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00C8FFFF00C80000)) \n \\corse_dec[2][2]_i_1 \n (.I0(\\corse_dec[3][2]_i_2_n_0 ),\n .I1(\\corse_dec[3][2]_i_3_n_0 ),\n .I2(\\corse_dec[3][2]_i_4_n_0 ),\n .I3(out[3]),\n .I4(\\corse_dec[2][2]_i_2_n_0 ),\n .I5(\\corse_dec_reg_n_0_[2][2] ),\n .O(\\corse_dec[2][2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0001000000000000)) \n \\corse_dec[2][2]_i_2 \n (.I0(out[0]),\n .I1(out[1]),\n .I2(out[2]),\n .I3(out[3]),\n .I4(out[4]),\n .I5(\\fine_inc[2][5]_i_3_n_0 ),\n .O(\\corse_dec[2][2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h000EFFFF000E0000)) \n \\corse_dec[3][0]_i_1 \n (.I0(\\corse_dec[3][2]_i_3_n_0 ),\n .I1(\\corse_dec[3][2]_i_4_n_0 ),\n .I2(\\corse_dec[3][2]_i_2_n_0 ),\n .I3(out[3]),\n .I4(\\corse_dec[3][2]_i_5_n_0 ),\n .I5(\\corse_dec_reg_n_0_[3][0] ),\n .O(\\corse_dec[3][0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00C2FFFF00C20000)) \n \\corse_dec[3][1]_i_1 \n (.I0(\\corse_dec[3][2]_i_3_n_0 ),\n .I1(\\corse_dec[3][2]_i_4_n_0 ),\n .I2(\\corse_dec[3][2]_i_2_n_0 ),\n .I3(out[3]),\n .I4(\\corse_dec[3][2]_i_5_n_0 ),\n .I5(\\corse_dec_reg_n_0_[3][1] ),\n .O(\\corse_dec[3][1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00C8FFFF00C80000)) \n \\corse_dec[3][2]_i_1 \n (.I0(\\corse_dec[3][2]_i_2_n_0 ),\n .I1(\\corse_dec[3][2]_i_3_n_0 ),\n .I2(\\corse_dec[3][2]_i_4_n_0 ),\n .I3(out[3]),\n .I4(\\corse_dec[3][2]_i_5_n_0 ),\n .I5(\\corse_dec_reg_n_0_[3][2] ),\n .O(\\corse_dec[3][2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\corse_dec[3][2]_i_2 \n (.I0(\\corse_dec_reg_n_0_[3][0] ),\n .I1(\\corse_dec_reg_n_0_[1][0] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\corse_dec_reg_n_0_[2][0] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\corse_dec_reg_n_0_[0][0] ),\n .O(\\corse_dec[3][2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\corse_dec[3][2]_i_3 \n (.I0(\\corse_dec_reg_n_0_[3][2] ),\n .I1(\\corse_dec_reg_n_0_[1][2] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\corse_dec_reg_n_0_[2][2] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\corse_dec_reg_n_0_[0][2] ),\n .O(\\corse_dec[3][2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\corse_dec[3][2]_i_4 \n (.I0(\\corse_dec_reg_n_0_[3][1] ),\n .I1(\\corse_dec_reg_n_0_[1][1] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\corse_dec_reg_n_0_[2][1] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\corse_dec_reg_n_0_[0][1] ),\n .O(\\corse_dec[3][2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h0001000000000000)) \n \\corse_dec[3][2]_i_5 \n (.I0(out[0]),\n .I1(out[1]),\n .I2(out[2]),\n .I3(out[3]),\n .I4(out[4]),\n .I5(\\fine_inc[3][5]_i_5_n_0 ),\n .O(\\corse_dec[3][2]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\corse_dec_reg[0][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_dec[0][0]_i_1_n_0 ),\n .Q(\\corse_dec_reg_n_0_[0][0] ),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\corse_dec_reg[0][1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_dec[0][1]_i_1_n_0 ),\n .Q(\\corse_dec_reg_n_0_[0][1] ),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\corse_dec_reg[0][2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_dec[0][2]_i_1_n_0 ),\n .Q(\\corse_dec_reg_n_0_[0][2] ),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\corse_dec_reg[1][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_dec[1][0]_i_1_n_0 ),\n .Q(\\corse_dec_reg_n_0_[1][0] ),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\corse_dec_reg[1][1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_dec[1][1]_i_1_n_0 ),\n .Q(\\corse_dec_reg_n_0_[1][1] ),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\corse_dec_reg[1][2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_dec[1][2]_i_1_n_0 ),\n .Q(\\corse_dec_reg_n_0_[1][2] ),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\corse_dec_reg[2][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_dec[2][0]_i_1_n_0 ),\n .Q(\\corse_dec_reg_n_0_[2][0] ),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\corse_dec_reg[2][1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_dec[2][1]_i_1_n_0 ),\n .Q(\\corse_dec_reg_n_0_[2][1] ),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\corse_dec_reg[2][2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_dec[2][2]_i_1_n_0 ),\n .Q(\\corse_dec_reg_n_0_[2][2] ),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\corse_dec_reg[3][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_dec[3][0]_i_1_n_0 ),\n .Q(\\corse_dec_reg_n_0_[3][0] ),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\corse_dec_reg[3][1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_dec[3][1]_i_1_n_0 ),\n .Q(\\corse_dec_reg_n_0_[3][1] ),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\corse_dec_reg[3][2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_dec[3][2]_i_1_n_0 ),\n .Q(\\corse_dec_reg_n_0_[3][2] ),\n .R(SR[0]));\n LUT6 #(\n .INIT(64'h5011FFFF50110000)) \n \\corse_inc[0][0]_i_1 \n (.I0(out[4]),\n .I1(\\corse_inc[3][0]_i_2_n_0 ),\n .I2(\\final_coarse_tap_reg_n_0_[0][0] ),\n .I3(out[0]),\n .I4(\\corse_inc[0][2]_i_2_n_0 ),\n .I5(\\corse_inc_reg_n_0_[0][0] ),\n .O(\\corse_inc[0][0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h2F20FFFF2F200000)) \n \\corse_inc[0][1]_i_1 \n (.I0(\\final_coarse_tap_reg_n_0_[0][1] ),\n .I1(out[4]),\n .I2(out[0]),\n .I3(\\corse_inc[3][1]_i_2_n_0 ),\n .I4(\\corse_inc[0][2]_i_2_n_0 ),\n .I5(\\corse_inc_reg_n_0_[0][1] ),\n .O(\\corse_inc[0][1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h2F20FFFF2F200000)) \n \\corse_inc[0][2]_i_1 \n (.I0(\\final_coarse_tap_reg_n_0_[0][2] ),\n .I1(out[4]),\n .I2(out[0]),\n .I3(\\corse_inc[3][2]_i_2_n_0 ),\n .I4(\\corse_inc[0][2]_i_2_n_0 ),\n .I5(\\corse_inc_reg_n_0_[0][2] ),\n .O(\\corse_inc[0][2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0020002088200020)) \n \\corse_inc[0][2]_i_2 \n (.I0(\\corse_inc[3][2]_i_6_n_0 ),\n .I1(out[3]),\n .I2(\\corse_inc[0][2]_i_3_n_0 ),\n .I3(out[0]),\n .I4(wr_level_done_r4),\n .I5(wr_level_done_r5),\n .O(\\corse_inc[0][2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\corse_inc[0][2]_i_3 \n (.I0(wr_level_done_r5),\n .I1(wrlvl_byte_redo),\n .I2(dqs_count_r[2]),\n .I3(dqs_count_r[1]),\n .I4(dqs_count_r[0]),\n .I5(\\FSM_sequential_wl_state_r[3]_i_9_n_0 ),\n .O(\\corse_inc[0][2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h5011FFFF50110000)) \n \\corse_inc[1][0]_i_1 \n (.I0(out[4]),\n .I1(\\corse_inc[3][0]_i_2_n_0 ),\n .I2(\\final_coarse_tap_reg_n_0_[1][0] ),\n .I3(out[0]),\n .I4(\\corse_inc[1][2]_i_2_n_0 ),\n .I5(\\corse_inc_reg_n_0_[1][0] ),\n .O(\\corse_inc[1][0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h2F20FFFF2F200000)) \n \\corse_inc[1][1]_i_1 \n (.I0(\\final_coarse_tap_reg_n_0_[1][1] ),\n .I1(out[4]),\n .I2(out[0]),\n .I3(\\corse_inc[3][1]_i_2_n_0 ),\n .I4(\\corse_inc[1][2]_i_2_n_0 ),\n .I5(\\corse_inc_reg_n_0_[1][1] ),\n .O(\\corse_inc[1][1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h2F20FFFF2F200000)) \n \\corse_inc[1][2]_i_1 \n (.I0(\\final_coarse_tap_reg_n_0_[1][2] ),\n .I1(out[4]),\n .I2(out[0]),\n .I3(\\corse_inc[3][2]_i_2_n_0 ),\n .I4(\\corse_inc[1][2]_i_2_n_0 ),\n .I5(\\corse_inc_reg_n_0_[1][2] ),\n .O(\\corse_inc[1][2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0020002088200020)) \n \\corse_inc[1][2]_i_2 \n (.I0(\\corse_inc[3][2]_i_6_n_0 ),\n .I1(out[3]),\n .I2(\\corse_inc[1][2]_i_3_n_0 ),\n .I3(out[0]),\n .I4(wr_level_done_r4),\n .I5(wr_level_done_r5),\n .O(\\corse_inc[1][2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000200)) \n \\corse_inc[1][2]_i_3 \n (.I0(wr_level_done_r5),\n .I1(wrlvl_byte_redo),\n .I2(dqs_count_r[2]),\n .I3(dqs_count_r[0]),\n .I4(dqs_count_r[1]),\n .I5(\\FSM_sequential_wl_state_r[3]_i_9_n_0 ),\n .O(\\corse_inc[1][2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h5011FFFF50110000)) \n \\corse_inc[2][0]_i_1 \n (.I0(out[4]),\n .I1(\\corse_inc[3][0]_i_2_n_0 ),\n .I2(\\final_coarse_tap_reg_n_0_[2][0] ),\n .I3(out[0]),\n .I4(\\corse_inc[2][2]_i_2_n_0 ),\n .I5(\\corse_inc_reg_n_0_[2][0] ),\n .O(\\corse_inc[2][0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h2F20FFFF2F200000)) \n \\corse_inc[2][1]_i_1 \n (.I0(\\final_coarse_tap_reg_n_0_[2][1] ),\n .I1(out[4]),\n .I2(out[0]),\n .I3(\\corse_inc[3][1]_i_2_n_0 ),\n .I4(\\corse_inc[2][2]_i_2_n_0 ),\n .I5(\\corse_inc_reg_n_0_[2][1] ),\n .O(\\corse_inc[2][1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h2F20FFFF2F200000)) \n \\corse_inc[2][2]_i_1 \n (.I0(\\final_coarse_tap_reg_n_0_[2][2] ),\n .I1(out[4]),\n .I2(out[0]),\n .I3(\\corse_inc[3][2]_i_2_n_0 ),\n .I4(\\corse_inc[2][2]_i_2_n_0 ),\n .I5(\\corse_inc_reg_n_0_[2][2] ),\n .O(\\corse_inc[2][2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0020002088200020)) \n \\corse_inc[2][2]_i_2 \n (.I0(\\corse_inc[3][2]_i_6_n_0 ),\n .I1(out[3]),\n .I2(\\corse_inc[2][2]_i_3_n_0 ),\n .I3(out[0]),\n .I4(wr_level_done_r4),\n .I5(wr_level_done_r5),\n .O(\\corse_inc[2][2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000200)) \n \\corse_inc[2][2]_i_3 \n (.I0(wr_level_done_r5),\n .I1(wrlvl_byte_redo),\n .I2(dqs_count_r[2]),\n .I3(dqs_count_r[1]),\n .I4(dqs_count_r[0]),\n .I5(\\FSM_sequential_wl_state_r[3]_i_9_n_0 ),\n .O(\\corse_inc[2][2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h5011FFFF50110000)) \n \\corse_inc[3][0]_i_1 \n (.I0(out[4]),\n .I1(\\corse_inc[3][0]_i_2_n_0 ),\n .I2(\\final_coarse_tap_reg_n_0_[3][0] ),\n .I3(out[0]),\n .I4(\\corse_inc[3][2]_i_3_n_0 ),\n .I5(\\corse_inc_reg_n_0_[3][0] ),\n .O(\\corse_inc[3][0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hF0FFF000AACCAACC)) \n \\corse_inc[3][0]_i_2 \n (.I0(\\corse_inc_reg_n_0_[2][0] ),\n .I1(\\corse_inc_reg_n_0_[0][0] ),\n .I2(\\corse_inc_reg_n_0_[3][0] ),\n .I3(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I4(\\corse_inc_reg_n_0_[1][0] ),\n .I5(\\dqs_count_r_reg[0]_rep_n_0 ),\n .O(\\corse_inc[3][0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h2F20FFFF2F200000)) \n \\corse_inc[3][1]_i_1 \n (.I0(\\final_coarse_tap_reg_n_0_[3][1] ),\n .I1(out[4]),\n .I2(out[0]),\n .I3(\\corse_inc[3][1]_i_2_n_0 ),\n .I4(\\corse_inc[3][2]_i_3_n_0 ),\n .I5(\\corse_inc_reg_n_0_[3][1] ),\n .O(\\corse_inc[3][1]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h09)) \n \\corse_inc[3][1]_i_2 \n (.I0(\\corse_inc[3][0]_i_2_n_0 ),\n .I1(\\corse_inc[3][2]_i_4_n_0 ),\n .I2(out[4]),\n .O(\\corse_inc[3][1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h2F20FFFF2F200000)) \n \\corse_inc[3][2]_i_1 \n (.I0(\\final_coarse_tap_reg_n_0_[3][2] ),\n .I1(out[4]),\n .I2(out[0]),\n .I3(\\corse_inc[3][2]_i_2_n_0 ),\n .I4(\\corse_inc[3][2]_i_3_n_0 ),\n .I5(\\corse_inc_reg_n_0_[3][2] ),\n .O(\\corse_inc[3][2]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h00E1)) \n \\corse_inc[3][2]_i_2 \n (.I0(\\corse_inc[3][2]_i_4_n_0 ),\n .I1(\\corse_inc[3][0]_i_2_n_0 ),\n .I2(\\corse_inc[3][2]_i_5_n_0 ),\n .I3(out[4]),\n .O(\\corse_inc[3][2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0020002088200020)) \n \\corse_inc[3][2]_i_3 \n (.I0(\\corse_inc[3][2]_i_6_n_0 ),\n .I1(out[3]),\n .I2(\\corse_inc[3][2]_i_7_n_0 ),\n .I3(out[0]),\n .I4(wr_level_done_r4),\n .I5(wr_level_done_r5),\n .O(\\corse_inc[3][2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\corse_inc[3][2]_i_4 \n (.I0(\\corse_inc_reg_n_0_[3][1] ),\n .I1(\\corse_inc_reg_n_0_[1][1] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\corse_inc_reg_n_0_[2][1] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\corse_inc_reg_n_0_[0][1] ),\n .O(\\corse_inc[3][2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\corse_inc[3][2]_i_5 \n (.I0(\\corse_inc_reg_n_0_[3][2] ),\n .I1(\\corse_inc_reg_n_0_[1][2] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\corse_inc_reg_n_0_[2][2] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\corse_inc_reg_n_0_[0][2] ),\n .O(\\corse_inc[3][2]_i_5_n_0 ));\n LUT3 #(\n .INIT(8'h02)) \n \\corse_inc[3][2]_i_6 \n (.I0(out[2]),\n .I1(out[4]),\n .I2(out[1]),\n .O(\\corse_inc[3][2]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h0000000002000000)) \n \\corse_inc[3][2]_i_7 \n (.I0(wr_level_done_r5),\n .I1(wrlvl_byte_redo),\n .I2(dqs_count_r[2]),\n .I3(dqs_count_r[1]),\n .I4(dqs_count_r[0]),\n .I5(\\FSM_sequential_wl_state_r[3]_i_9_n_0 ),\n .O(\\corse_inc[3][2]_i_7_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\corse_inc_reg[0][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_inc[0][0]_i_1_n_0 ),\n .Q(\\corse_inc_reg_n_0_[0][0] ),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\corse_inc_reg[0][1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_inc[0][1]_i_1_n_0 ),\n .Q(\\corse_inc_reg_n_0_[0][1] ),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\corse_inc_reg[0][2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_inc[0][2]_i_1_n_0 ),\n .Q(\\corse_inc_reg_n_0_[0][2] ),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\corse_inc_reg[1][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_inc[1][0]_i_1_n_0 ),\n .Q(\\corse_inc_reg_n_0_[1][0] ),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\corse_inc_reg[1][1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_inc[1][1]_i_1_n_0 ),\n .Q(\\corse_inc_reg_n_0_[1][1] ),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\corse_inc_reg[1][2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_inc[1][2]_i_1_n_0 ),\n .Q(\\corse_inc_reg_n_0_[1][2] ),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\corse_inc_reg[2][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_inc[2][0]_i_1_n_0 ),\n .Q(\\corse_inc_reg_n_0_[2][0] ),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\corse_inc_reg[2][1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_inc[2][1]_i_1_n_0 ),\n .Q(\\corse_inc_reg_n_0_[2][1] ),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\corse_inc_reg[2][2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_inc[2][2]_i_1_n_0 ),\n .Q(\\corse_inc_reg_n_0_[2][2] ),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\corse_inc_reg[3][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_inc[3][0]_i_1_n_0 ),\n .Q(\\corse_inc_reg_n_0_[3][0] ),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\corse_inc_reg[3][1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_inc[3][1]_i_1_n_0 ),\n .Q(\\corse_inc_reg_n_0_[3][1] ),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\corse_inc_reg[3][2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_inc[3][2]_i_1_n_0 ),\n .Q(\\corse_inc_reg_n_0_[3][2] ),\n .R(SR[0]));\n LUT3 #(\n .INIT(8'hBF)) \n \\ctl_lane_cnt[2]_i_2 \n (.I0(rstdiv0_sync_r1_reg_rep__24),\n .I1(dqs_po_dec_done),\n .I2(pi_fine_dly_dec_done),\n .O(p_1_in));\n LUT5 #(\n .INIT(32'h77770777)) \n dq_cnt_inc_i_2\n (.I0(wrlvl_byte_redo),\n .I1(out[3]),\n .I2(dqs_count_r[0]),\n .I3(dqs_count_r[1]),\n .I4(dqs_count_r[2]),\n .O(dq_cnt_inc_reg_0));\n FDSE #(\n .INIT(1'b1)) \n dq_cnt_inc_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_wl_state_r_reg[1]_0 ),\n .Q(p_0_in),\n .S(SR[0]));\n LUT6 #(\n .INIT(64'hF444FFFFF4440000)) \n \\dqs_count_r[0]_i_1 \n (.I0(out[4]),\n .I1(\\dqs_count_r_reg[0]_i_2_n_0 ),\n .I2(\\dqs_count_r_reg[0]_i_3_n_0 ),\n .I3(out[0]),\n .I4(\\dqs_count_r[2]_i_5_n_0 ),\n .I5(\\dqs_count_r_reg[0]_rep_n_0 ),\n .O(\\dqs_count_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hCACC0A00CACCCACC)) \n \\dqs_count_r[0]_i_4 \n (.I0(\\po_stg2_wrcal_cnt_reg[2] [0]),\n .I1(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I2(wrlvl_byte_redo_r),\n .I3(wrlvl_byte_redo),\n .I4(wrlvl_final_r),\n .I5(wrlvl_final_mux),\n .O(\\dqs_count_r[0]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hBFBFBFB0000F000F)) \n \\dqs_count_r[0]_i_5 \n (.I0(wr_level_done_r5),\n .I1(wr_level_done_r4),\n .I2(out[0]),\n .I3(\\FSM_sequential_wl_state_r[2]_i_10_n_0 ),\n .I4(\\fine_inc[3][5]_i_5_n_0 ),\n .I5(dqs_count_r[0]),\n .O(\\dqs_count_r[0]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFBFFF80000FF03FF)) \n \\dqs_count_r[0]_i_6 \n (.I0(p_0_in),\n .I1(out[1]),\n .I2(wrlvl_byte_redo),\n .I3(out[3]),\n .I4(\\fine_inc[3][5]_i_5_n_0 ),\n .I5(dqs_count_r[0]),\n .O(\\dqs_count_r[0]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h00000000ADAAAAAA)) \n \\dqs_count_r[0]_i_7 \n (.I0(dqs_count_r[0]),\n .I1(\\fine_inc[3][5]_i_5_n_0 ),\n .I2(\\FSM_sequential_wl_state_r[2]_i_10_n_0 ),\n .I3(\\FSM_sequential_wl_state_r[3]_i_9_n_0 ),\n .I4(\\dqs_count_r[0]_i_8_n_0 ),\n .I5(out[3]),\n .O(\\dqs_count_r[0]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair319\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\dqs_count_r[0]_i_8 \n (.I0(wr_level_done_r5),\n .I1(wrlvl_byte_redo),\n .O(\\dqs_count_r[0]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'hF444FFFFF4440000)) \n \\dqs_count_r[1]_i_1 \n (.I0(out[4]),\n .I1(\\dqs_count_r_reg[1]_i_2_n_0 ),\n .I2(\\dqs_count_r_reg[1]_i_3_n_0 ),\n .I3(out[0]),\n .I4(\\dqs_count_r[2]_i_5_n_0 ),\n .I5(\\dqs_count_r_reg[1]_rep_n_0 ),\n .O(\\dqs_count_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hCACC0A00CACCCACC)) \n \\dqs_count_r[1]_i_4 \n (.I0(\\po_stg2_wrcal_cnt_reg[2] [1]),\n .I1(dqs_count_r[1]),\n .I2(wrlvl_byte_redo_r),\n .I3(wrlvl_byte_redo),\n .I4(wrlvl_final_r),\n .I5(wrlvl_final_mux),\n .O(\\dqs_count_r[1]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h7477030377770000)) \n \\dqs_count_r[1]_i_5 \n (.I0(dqs_count_r140_out),\n .I1(out[0]),\n .I2(\\FSM_sequential_wl_state_r[2]_i_10_n_0 ),\n .I3(dqs_count_r[2]),\n .I4(dqs_count_r[1]),\n .I5(dqs_count_r[0]),\n .O(\\dqs_count_r[1]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'h8BBBBB88)) \n \\dqs_count_r[1]_i_6 \n (.I0(\\dqs_count_r[1]_i_8_n_0 ),\n .I1(out[3]),\n .I2(dqs_count_r[2]),\n .I3(dqs_count_r[1]),\n .I4(dqs_count_r[0]),\n .O(\\dqs_count_r[1]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h00000000CCCCCC6E)) \n \\dqs_count_r[1]_i_7 \n (.I0(dqs_count_r[0]),\n .I1(dqs_count_r[1]),\n .I2(dqs_count_r[2]),\n .I3(\\FSM_sequential_wl_state_r[2]_i_10_n_0 ),\n .I4(\\dqs_count_r[2]_i_11_n_0 ),\n .I5(out[3]),\n .O(\\dqs_count_r[1]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hF8FB0300FBFB0300)) \n \\dqs_count_r[1]_i_8 \n (.I0(p_0_in),\n .I1(out[1]),\n .I2(wrlvl_byte_redo),\n .I3(dqs_count_r[0]),\n .I4(dqs_count_r[1]),\n .I5(dqs_count_r[2]),\n .O(\\dqs_count_r[1]_i_8_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair339\" *) \n LUT2 #(\n .INIT(4'h7)) \n \\dqs_count_r[2]_i_10 \n (.I0(dqs_count_r[0]),\n .I1(dqs_count_r[1]),\n .O(\\dqs_count_r[2]_i_10_n_0 ));\n LUT3 #(\n .INIT(8'hBF)) \n \\dqs_count_r[2]_i_11 \n (.I0(wrlvl_byte_redo),\n .I1(wr_level_done_r5),\n .I2(\\FSM_sequential_wl_state_r[3]_i_9_n_0 ),\n .O(\\dqs_count_r[2]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'hF444FFFFF4440000)) \n \\dqs_count_r[2]_i_2 \n (.I0(out[4]),\n .I1(\\dqs_count_r_reg[2]_i_3_n_0 ),\n .I2(\\dqs_count_r_reg[2]_i_4_n_0 ),\n .I3(out[0]),\n .I4(\\dqs_count_r[2]_i_5_n_0 ),\n .I5(dqs_count_r[2]),\n .O(\\dqs_count_r[2]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h00805889)) \n \\dqs_count_r[2]_i_5 \n (.I0(out[4]),\n .I1(out[0]),\n .I2(out[3]),\n .I3(out[2]),\n .I4(out[1]),\n .O(\\dqs_count_r[2]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFB080808FB08FB08)) \n \\dqs_count_r[2]_i_6 \n (.I0(\\po_stg2_wrcal_cnt_reg[2] [2]),\n .I1(wrlvl_byte_redo),\n .I2(wrlvl_byte_redo_r),\n .I3(dqs_count_r[2]),\n .I4(wrlvl_final_r),\n .I5(wrlvl_final_mux),\n .O(\\dqs_count_r[2]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h7040707070707070)) \n \\dqs_count_r[2]_i_7 \n (.I0(dqs_count_r140_out),\n .I1(out[0]),\n .I2(dqs_count_r[2]),\n .I3(\\FSM_sequential_wl_state_r[2]_i_10_n_0 ),\n .I4(dqs_count_r[0]),\n .I5(dqs_count_r[1]),\n .O(\\dqs_count_r[2]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hFBFFF80000000000)) \n \\dqs_count_r[2]_i_8 \n (.I0(p_0_in),\n .I1(out[1]),\n .I2(wrlvl_byte_redo),\n .I3(out[3]),\n .I4(\\dqs_count_r[2]_i_10_n_0 ),\n .I5(dqs_count_r[2]),\n .O(\\dqs_count_r[2]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FFBF0000)) \n \\dqs_count_r[2]_i_9 \n (.I0(\\FSM_sequential_wl_state_r[2]_i_10_n_0 ),\n .I1(dqs_count_r[0]),\n .I2(dqs_count_r[1]),\n .I3(\\dqs_count_r[2]_i_11_n_0 ),\n .I4(dqs_count_r[2]),\n .I5(out[3]),\n .O(\\dqs_count_r[2]_i_9_n_0 ));\n (* MAX_FANOUT = \"50\" *) \n (* ORIG_CELL_NAME = \"dqs_count_r_reg[0]\" *) \n FDRE #(\n .INIT(1'b0)) \n \\dqs_count_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dqs_count_r[0]_i_1_n_0 ),\n .Q(dqs_count_r[0]),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n MUXF7 \\dqs_count_r_reg[0]_i_2 \n (.I0(\\dqs_count_r[0]_i_4_n_0 ),\n .I1(\\dqs_count_r[0]_i_5_n_0 ),\n .O(\\dqs_count_r_reg[0]_i_2_n_0 ),\n .S(out[3]));\n MUXF7 \\dqs_count_r_reg[0]_i_3 \n (.I0(\\dqs_count_r[0]_i_6_n_0 ),\n .I1(\\dqs_count_r[0]_i_7_n_0 ),\n .O(\\dqs_count_r_reg[0]_i_3_n_0 ),\n .S(out[2]));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* MAX_FANOUT = \"50\" *) \n (* ORIG_CELL_NAME = \"dqs_count_r_reg[0]\" *) \n FDRE #(\n .INIT(1'b0)) \n \\dqs_count_r_reg[0]_rep \n (.C(CLK),\n .CE(1'b1),\n .D(\\dqs_count_r[0]_i_1_n_0 ),\n .Q(\\dqs_count_r_reg[0]_rep_n_0 ),\n .R(rstdiv0_sync_r1_reg_rep));\n (* MAX_FANOUT = \"50\" *) \n (* ORIG_CELL_NAME = \"dqs_count_r_reg[1]\" *) \n FDRE #(\n .INIT(1'b0)) \n \\dqs_count_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dqs_count_r[1]_i_1_n_0 ),\n .Q(dqs_count_r[1]),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n MUXF7 \\dqs_count_r_reg[1]_i_2 \n (.I0(\\dqs_count_r[1]_i_4_n_0 ),\n .I1(\\dqs_count_r[1]_i_5_n_0 ),\n .O(\\dqs_count_r_reg[1]_i_2_n_0 ),\n .S(out[3]));\n MUXF7 \\dqs_count_r_reg[1]_i_3 \n (.I0(\\dqs_count_r[1]_i_6_n_0 ),\n .I1(\\dqs_count_r[1]_i_7_n_0 ),\n .O(\\dqs_count_r_reg[1]_i_3_n_0 ),\n .S(out[2]));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* MAX_FANOUT = \"50\" *) \n (* ORIG_CELL_NAME = \"dqs_count_r_reg[1]\" *) \n FDRE #(\n .INIT(1'b0)) \n \\dqs_count_r_reg[1]_rep \n (.C(CLK),\n .CE(1'b1),\n .D(\\dqs_count_r[1]_i_1_n_0 ),\n .Q(\\dqs_count_r_reg[1]_rep_n_0 ),\n .R(rstdiv0_sync_r1_reg_rep));\n (* MAX_FANOUT = \"50\" *) \n FDRE #(\n .INIT(1'b0)) \n \\dqs_count_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dqs_count_r[2]_i_2_n_0 ),\n .Q(dqs_count_r[2]),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n MUXF7 \\dqs_count_r_reg[2]_i_3 \n (.I0(\\dqs_count_r[2]_i_6_n_0 ),\n .I1(\\dqs_count_r[2]_i_7_n_0 ),\n .O(\\dqs_count_r_reg[2]_i_3_n_0 ),\n .S(out[3]));\n MUXF7 \\dqs_count_r_reg[2]_i_4 \n (.I0(\\dqs_count_r[2]_i_8_n_0 ),\n .I1(\\dqs_count_r[2]_i_9_n_0 ),\n .O(\\dqs_count_r_reg[2]_i_4_n_0 ),\n .S(out[2]));\n (* syn_maxfan = \"2\" *) \n FDRE #(\n .INIT(1'b0)) \n dqs_po_dec_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(po_dec_done),\n .Q(dqs_po_dec_done),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hAAAABBABAAAAAABA)) \n dqs_po_en_stg2_f_i_1\n (.I0(dqs_po_en_stg2_f_reg_0),\n .I1(out[2]),\n .I2(out[3]),\n .I3(out[0]),\n .I4(out[4]),\n .I5(out[1]),\n .O(dqs_po_en_stg2_f_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n dqs_po_en_stg2_f_reg\n (.C(CLK),\n .CE(1'b1),\n .D(dqs_po_en_stg2_f_i_1_n_0),\n .Q(dqs_po_en_stg2_f),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n LUT3 #(\n .INIT(8'h02)) \n dqs_po_stg2_f_incdec_i_1\n (.I0(dqs_po_stg2_f_incdec_i_2_n_0),\n .I1(dqs_po_stg2_f_incdec_i_3_n_0),\n .I2(rstdiv0_sync_r1_reg_rep__22),\n .O(dqs_po_stg2_f_incdec0));\n LUT6 #(\n .INIT(64'h00000000FFFFFEDF)) \n dqs_po_stg2_f_incdec_i_2\n (.I0(out[1]),\n .I1(out[4]),\n .I2(out[0]),\n .I3(out[3]),\n .I4(out[2]),\n .I5(dqs_po_en_stg2_f_reg_0),\n .O(dqs_po_stg2_f_incdec_i_2_n_0));\n LUT5 #(\n .INIT(32'hFBFEFFFF)) \n dqs_po_stg2_f_incdec_i_3\n (.I0(out[2]),\n .I1(out[0]),\n .I2(out[4]),\n .I3(out[3]),\n .I4(out[1]),\n .O(dqs_po_stg2_f_incdec_i_3_n_0));\n FDRE #(\n .INIT(1'b0)) \n dqs_po_stg2_f_incdec_reg\n (.C(CLK),\n .CE(1'b1),\n .D(dqs_po_stg2_f_incdec0),\n .Q(dqs_po_stg2_f_incdec),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00000002)) \n dqs_wl_po_stg2_c_incdec_i_1\n (.I0(out[2]),\n .I1(out[0]),\n .I2(out[1]),\n .I3(out[3]),\n .I4(out[4]),\n .O(dqs_wl_po_stg2_c_incdec_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n dqs_wl_po_stg2_c_incdec_reg\n (.C(CLK),\n .CE(1'b1),\n .D(dqs_wl_po_stg2_c_incdec_i_1_n_0),\n .Q(dqs_wl_po_stg2_c_incdec),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\final_coarse_tap_reg[0][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_corse_cnt_reg[0][0]__0 [0]),\n .Q(\\final_coarse_tap_reg_n_0_[0][0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\final_coarse_tap_reg[0][1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_corse_cnt_reg[0][0]__0 [1]),\n .Q(\\final_coarse_tap_reg_n_0_[0][1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\final_coarse_tap_reg[0][2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_corse_cnt_reg[0][0]__0 [2]),\n .Q(\\final_coarse_tap_reg_n_0_[0][2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\final_coarse_tap_reg[1][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_corse_cnt_reg[0][1]__0 [0]),\n .Q(\\final_coarse_tap_reg_n_0_[1][0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\final_coarse_tap_reg[1][1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_corse_cnt_reg[0][1]__0 [1]),\n .Q(\\final_coarse_tap_reg_n_0_[1][1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\final_coarse_tap_reg[1][2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_corse_cnt_reg[0][1]__0 [2]),\n .Q(\\final_coarse_tap_reg_n_0_[1][2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\final_coarse_tap_reg[2][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_corse_cnt_reg[0][2]__0 [0]),\n .Q(\\final_coarse_tap_reg_n_0_[2][0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\final_coarse_tap_reg[2][1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_corse_cnt_reg[0][2]__0 [1]),\n .Q(\\final_coarse_tap_reg_n_0_[2][1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\final_coarse_tap_reg[2][2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_corse_cnt_reg[0][2]__0 [2]),\n .Q(\\final_coarse_tap_reg_n_0_[2][2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\final_coarse_tap_reg[3][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_corse_cnt_reg[0][3]__0 [0]),\n .Q(\\final_coarse_tap_reg_n_0_[3][0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\final_coarse_tap_reg[3][1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_corse_cnt_reg[0][3]__0 [1]),\n .Q(\\final_coarse_tap_reg_n_0_[3][1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\final_coarse_tap_reg[3][2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_corse_cnt_reg[0][3]__0 [2]),\n .Q(\\final_coarse_tap_reg_n_0_[3][2] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h303F000035370504)) \n \\fine_dec_cnt[0]_i_1 \n (.I0(fine_dec_cnt__0[0]),\n .I1(out[3]),\n .I2(out[2]),\n .I3(out[1]),\n .I4(\\wl_tap_count_r_reg_n_0_[0] ),\n .I5(out[4]),\n .O(fine_dec_cnt[0]));\n LUT6 #(\n .INIT(64'hBABFAAAABABBAAAA)) \n \\fine_dec_cnt[1]_i_1 \n (.I0(\\fine_dec_cnt[1]_i_2_n_0 ),\n .I1(out[3]),\n .I2(out[2]),\n .I3(out[1]),\n .I4(\\wl_tap_count_r_reg_n_0_[1] ),\n .I5(out[4]),\n .O(fine_dec_cnt[1]));\n LUT6 #(\n .INIT(64'h1001100110010000)) \n \\fine_dec_cnt[1]_i_2 \n (.I0(out[4]),\n .I1(out[2]),\n .I2(fine_dec_cnt__0[1]),\n .I3(fine_dec_cnt__0[0]),\n .I4(out[1]),\n .I5(out[3]),\n .O(\\fine_dec_cnt[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h303F000035370505)) \n \\fine_dec_cnt[2]_i_1 \n (.I0(\\fine_dec_cnt[2]_i_2_n_0 ),\n .I1(out[3]),\n .I2(out[2]),\n .I3(out[1]),\n .I4(\\wl_tap_count_r_reg_n_0_[2] ),\n .I5(out[4]),\n .O(fine_dec_cnt[2]));\n LUT5 #(\n .INIT(32'h1F1F1FF1)) \n \\fine_dec_cnt[2]_i_2 \n (.I0(out[3]),\n .I1(out[1]),\n .I2(fine_dec_cnt__0[2]),\n .I3(fine_dec_cnt__0[0]),\n .I4(fine_dec_cnt__0[1]),\n .O(\\fine_dec_cnt[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h303F000035370505)) \n \\fine_dec_cnt[3]_i_1 \n (.I0(\\fine_dec_cnt[3]_i_2_n_0 ),\n .I1(out[3]),\n .I2(out[2]),\n .I3(out[1]),\n .I4(\\wl_tap_count_r_reg_n_0_[3] ),\n .I5(out[4]),\n .O(fine_dec_cnt[3]));\n LUT6 #(\n .INIT(64'h1F1F1F1F1F1F1FF1)) \n \\fine_dec_cnt[3]_i_2 \n (.I0(out[3]),\n .I1(out[1]),\n .I2(fine_dec_cnt__0[3]),\n .I3(fine_dec_cnt__0[1]),\n .I4(fine_dec_cnt__0[0]),\n .I5(fine_dec_cnt__0[2]),\n .O(\\fine_dec_cnt[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h303F00003A3B0A08)) \n \\fine_dec_cnt[4]_i_1 \n (.I0(\\fine_dec_cnt[4]_i_2_n_0 ),\n .I1(out[3]),\n .I2(out[2]),\n .I3(out[1]),\n .I4(\\wl_tap_count_r_reg_n_0_[4] ),\n .I5(out[4]),\n .O(fine_dec_cnt[4]));\n LUT5 #(\n .INIT(32'hFFFE0001)) \n \\fine_dec_cnt[4]_i_2 \n (.I0(fine_dec_cnt__0[3]),\n .I1(fine_dec_cnt__0[1]),\n .I2(fine_dec_cnt__0[0]),\n .I3(fine_dec_cnt__0[2]),\n .I4(fine_dec_cnt__0[4]),\n .O(\\fine_dec_cnt[4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h303F00003A3B0A08)) \n \\fine_dec_cnt[5]_i_2 \n (.I0(\\fine_dec_cnt[5]_i_5_n_0 ),\n .I1(out[3]),\n .I2(out[2]),\n .I3(out[1]),\n .I4(\\wl_tap_count_r_reg_n_0_[5] ),\n .I5(out[4]),\n .O(fine_dec_cnt[5]));\n LUT5 #(\n .INIT(32'h11800080)) \n \\fine_dec_cnt[5]_i_3 \n (.I0(out[2]),\n .I1(out[1]),\n .I2(\\fine_dec_cnt[5]_i_6_n_0 ),\n .I3(out[3]),\n .I4(\\fine_dec_cnt[5]_i_7_n_0 ),\n .O(\\fine_dec_cnt[5]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h4444040000000400)) \n \\fine_dec_cnt[5]_i_4 \n (.I0(out[3]),\n .I1(\\fine_dec_cnt[5]_i_8_n_0 ),\n .I2(\\rd_data_edge_detect_r[3]_i_4_n_0 ),\n .I3(wrlvl_byte_redo),\n .I4(out[1]),\n .I5(\\FSM_sequential_wl_state_r[3]_i_10_n_0 ),\n .O(\\fine_dec_cnt[5]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAAAAA9)) \n \\fine_dec_cnt[5]_i_5 \n (.I0(fine_dec_cnt__0[5]),\n .I1(fine_dec_cnt__0[3]),\n .I2(fine_dec_cnt__0[1]),\n .I3(fine_dec_cnt__0[0]),\n .I4(fine_dec_cnt__0[2]),\n .I5(fine_dec_cnt__0[4]),\n .O(\\fine_dec_cnt[5]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h0000000080000000)) \n \\fine_dec_cnt[5]_i_6 \n (.I0(\\stable_cnt_reg_n_0_[1] ),\n .I1(\\stable_cnt_reg_n_0_[2] ),\n .I2(\\stable_cnt_reg_n_0_[3] ),\n .I3(wl_sm_start),\n .I4(stable_cnt227_in),\n .I5(out[4]),\n .O(\\fine_dec_cnt[5]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h0020FFFF00200000)) \n \\fine_dec_cnt[5]_i_7 \n (.I0(\\FSM_sequential_wl_state_r[0]_i_3_n_0 ),\n .I1(\\FSM_sequential_wl_state_r[0]_i_5_n_0 ),\n .I2(\\FSM_sequential_wl_state_r_reg[0]_0 ),\n .I3(\\rd_data_edge_detect_r[3]_i_5_n_0 ),\n .I4(out[4]),\n .I5(\\FSM_sequential_wl_state_r[3]_i_10_n_0 ),\n .O(\\fine_dec_cnt[5]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h1)) \n \\fine_dec_cnt[5]_i_8 \n (.I0(out[2]),\n .I1(out[4]),\n .O(\\fine_dec_cnt[5]_i_8_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\fine_dec_cnt_reg[0] \n (.C(CLK),\n .CE(\\fine_dec_cnt_reg[5]_i_1_n_0 ),\n .D(fine_dec_cnt[0]),\n .Q(fine_dec_cnt__0[0]),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\fine_dec_cnt_reg[1] \n (.C(CLK),\n .CE(\\fine_dec_cnt_reg[5]_i_1_n_0 ),\n .D(fine_dec_cnt[1]),\n .Q(fine_dec_cnt__0[1]),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\fine_dec_cnt_reg[2] \n (.C(CLK),\n .CE(\\fine_dec_cnt_reg[5]_i_1_n_0 ),\n .D(fine_dec_cnt[2]),\n .Q(fine_dec_cnt__0[2]),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\fine_dec_cnt_reg[3] \n (.C(CLK),\n .CE(\\fine_dec_cnt_reg[5]_i_1_n_0 ),\n .D(fine_dec_cnt[3]),\n .Q(fine_dec_cnt__0[3]),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\fine_dec_cnt_reg[4] \n (.C(CLK),\n .CE(\\fine_dec_cnt_reg[5]_i_1_n_0 ),\n .D(fine_dec_cnt[4]),\n .Q(fine_dec_cnt__0[4]),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\fine_dec_cnt_reg[5] \n (.C(CLK),\n .CE(\\fine_dec_cnt_reg[5]_i_1_n_0 ),\n .D(fine_dec_cnt[5]),\n .Q(fine_dec_cnt__0[5]),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n MUXF7 \\fine_dec_cnt_reg[5]_i_1 \n (.I0(\\fine_dec_cnt[5]_i_3_n_0 ),\n .I1(\\fine_dec_cnt[5]_i_4_n_0 ),\n .O(\\fine_dec_cnt_reg[5]_i_1_n_0 ),\n .S(out[0]));\n LUT4 #(\n .INIT(16'h0074)) \n \\fine_inc[0][0]_i_1 \n (.I0(\\fine_inc[3][2]_i_3_n_0 ),\n .I1(out[1]),\n .I2(\\gen_final_tap[0].final_val_reg_n_0_[0][0] ),\n .I3(out[4]),\n .O(fine_inc[0]));\n LUT5 #(\n .INIT(32'h090F0900)) \n \\fine_inc[0][1]_i_1 \n (.I0(\\fine_inc[3][2]_i_3_n_0 ),\n .I1(\\fine_inc[3][2]_i_2_n_0 ),\n .I2(out[4]),\n .I3(out[1]),\n .I4(\\gen_final_tap[0].final_val_reg_n_0_[0][1] ),\n .O(fine_inc[1]));\n LUT6 #(\n .INIT(64'h00E100FF00E10000)) \n \\fine_inc[0][2]_i_1 \n (.I0(\\fine_inc[3][2]_i_2_n_0 ),\n .I1(\\fine_inc[3][2]_i_3_n_0 ),\n .I2(\\fine_inc[3][2]_i_4_n_0 ),\n .I3(out[4]),\n .I4(out[1]),\n .I5(\\gen_final_tap[0].final_val_reg_n_0_[0][2] ),\n .O(fine_inc[2]));\n LUT5 #(\n .INIT(32'h060F0600)) \n \\fine_inc[0][3]_i_1 \n (.I0(\\fine_inc[3][4]_i_3_n_0 ),\n .I1(\\fine_inc[3][4]_i_2_n_0 ),\n .I2(out[4]),\n .I3(out[1]),\n .I4(\\gen_final_tap[0].final_val_reg_n_0_[0][3] ),\n .O(fine_inc[3]));\n LUT6 #(\n .INIT(64'h00D200FF00D20000)) \n \\fine_inc[0][4]_i_1 \n (.I0(\\fine_inc[3][4]_i_2_n_0 ),\n .I1(\\fine_inc[3][4]_i_3_n_0 ),\n .I2(\\fine_inc[3][4]_i_4_n_0 ),\n .I3(out[4]),\n .I4(out[1]),\n .I5(\\gen_final_tap[0].final_val_reg_n_0_[0][4] ),\n .O(fine_inc[4]));\n LUT6 #(\n .INIT(64'h008000800A800080)) \n \\fine_inc[0][5]_i_1 \n (.I0(\\fine_inc[3][5]_i_3_n_0 ),\n .I1(dqs_count_r140_out),\n .I2(out[2]),\n .I3(out[1]),\n .I4(\\fine_inc[0][5]_i_3_n_0 ),\n .I5(\\fine_inc[3][5]_i_6_n_0 ),\n .O(\\fine_inc[0][5]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h88B8)) \n \\fine_inc[0][5]_i_2 \n (.I0(\\fine_inc[3][5]_i_7_n_0 ),\n .I1(out[1]),\n .I2(\\gen_final_tap[0].final_val_reg_n_0_[0][5] ),\n .I3(out[4]),\n .O(fine_inc[5]));\n (* SOFT_HLUTNM = \"soft_lutpair338\" *) \n LUT3 #(\n .INIT(8'h01)) \n \\fine_inc[0][5]_i_3 \n (.I0(dqs_count_r[2]),\n .I1(dqs_count_r[1]),\n .I2(dqs_count_r[0]),\n .O(\\fine_inc[0][5]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'h0074)) \n \\fine_inc[1][0]_i_1 \n (.I0(\\fine_inc[3][2]_i_3_n_0 ),\n .I1(out[1]),\n .I2(\\gen_final_tap[1].final_val_reg_n_0_[1][0] ),\n .I3(out[4]),\n .O(\\fine_inc[1][0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h090F0900)) \n \\fine_inc[1][1]_i_1 \n (.I0(\\fine_inc[3][2]_i_3_n_0 ),\n .I1(\\fine_inc[3][2]_i_2_n_0 ),\n .I2(out[4]),\n .I3(out[1]),\n .I4(\\gen_final_tap[1].final_val_reg_n_0_[1][1] ),\n .O(\\fine_inc[1][1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00E100FF00E10000)) \n \\fine_inc[1][2]_i_1 \n (.I0(\\fine_inc[3][2]_i_2_n_0 ),\n .I1(\\fine_inc[3][2]_i_3_n_0 ),\n .I2(\\fine_inc[3][2]_i_4_n_0 ),\n .I3(out[4]),\n .I4(out[1]),\n .I5(\\gen_final_tap[1].final_val_reg_n_0_[1][2] ),\n .O(\\fine_inc[1][2]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h060F0600)) \n \\fine_inc[1][3]_i_1 \n (.I0(\\fine_inc[3][4]_i_3_n_0 ),\n .I1(\\fine_inc[3][4]_i_2_n_0 ),\n .I2(out[4]),\n .I3(out[1]),\n .I4(\\gen_final_tap[1].final_val_reg_n_0_[1][3] ),\n .O(\\fine_inc[1][3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00D200FF00D20000)) \n \\fine_inc[1][4]_i_1 \n (.I0(\\fine_inc[3][4]_i_2_n_0 ),\n .I1(\\fine_inc[3][4]_i_3_n_0 ),\n .I2(\\fine_inc[3][4]_i_4_n_0 ),\n .I3(out[4]),\n .I4(out[1]),\n .I5(\\gen_final_tap[1].final_val_reg_n_0_[1][4] ),\n .O(\\fine_inc[1][4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h008000800A800080)) \n \\fine_inc[1][5]_i_1 \n (.I0(\\fine_inc[3][5]_i_3_n_0 ),\n .I1(dqs_count_r140_out),\n .I2(out[2]),\n .I3(out[1]),\n .I4(\\fine_inc[1][5]_i_3_n_0 ),\n .I5(\\fine_inc[3][5]_i_6_n_0 ),\n .O(\\fine_inc[1][5]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h88B8)) \n \\fine_inc[1][5]_i_2 \n (.I0(\\fine_inc[3][5]_i_7_n_0 ),\n .I1(out[1]),\n .I2(\\gen_final_tap[1].final_val_reg_n_0_[1][5] ),\n .I3(out[4]),\n .O(\\fine_inc[1][5]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair338\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\fine_inc[1][5]_i_3 \n (.I0(dqs_count_r[2]),\n .I1(dqs_count_r[0]),\n .I2(dqs_count_r[1]),\n .O(\\fine_inc[1][5]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'h0074)) \n \\fine_inc[2][0]_i_1 \n (.I0(\\fine_inc[3][2]_i_3_n_0 ),\n .I1(out[1]),\n .I2(\\gen_final_tap[2].final_val_reg_n_0_[2][0] ),\n .I3(out[4]),\n .O(\\fine_inc[2][0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h090F0900)) \n \\fine_inc[2][1]_i_1 \n (.I0(\\fine_inc[3][2]_i_3_n_0 ),\n .I1(\\fine_inc[3][2]_i_2_n_0 ),\n .I2(out[4]),\n .I3(out[1]),\n .I4(\\gen_final_tap[2].final_val_reg_n_0_[2][1] ),\n .O(\\fine_inc[2][1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00E100FF00E10000)) \n \\fine_inc[2][2]_i_1 \n (.I0(\\fine_inc[3][2]_i_2_n_0 ),\n .I1(\\fine_inc[3][2]_i_3_n_0 ),\n .I2(\\fine_inc[3][2]_i_4_n_0 ),\n .I3(out[4]),\n .I4(out[1]),\n .I5(\\gen_final_tap[2].final_val_reg_n_0_[2][2] ),\n .O(\\fine_inc[2][2]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h060F0600)) \n \\fine_inc[2][3]_i_1 \n (.I0(\\fine_inc[3][4]_i_3_n_0 ),\n .I1(\\fine_inc[3][4]_i_2_n_0 ),\n .I2(out[4]),\n .I3(out[1]),\n .I4(\\gen_final_tap[2].final_val_reg_n_0_[2][3] ),\n .O(\\fine_inc[2][3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00D200FF00D20000)) \n \\fine_inc[2][4]_i_1 \n (.I0(\\fine_inc[3][4]_i_2_n_0 ),\n .I1(\\fine_inc[3][4]_i_3_n_0 ),\n .I2(\\fine_inc[3][4]_i_4_n_0 ),\n .I3(out[4]),\n .I4(out[1]),\n .I5(\\gen_final_tap[2].final_val_reg_n_0_[2][4] ),\n .O(\\fine_inc[2][4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h008000800A800080)) \n \\fine_inc[2][5]_i_1 \n (.I0(\\fine_inc[3][5]_i_3_n_0 ),\n .I1(dqs_count_r140_out),\n .I2(out[2]),\n .I3(out[1]),\n .I4(\\fine_inc[2][5]_i_3_n_0 ),\n .I5(\\fine_inc[3][5]_i_6_n_0 ),\n .O(\\fine_inc[2][5]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h88B8)) \n \\fine_inc[2][5]_i_2 \n (.I0(\\fine_inc[3][5]_i_7_n_0 ),\n .I1(out[1]),\n .I2(\\gen_final_tap[2].final_val_reg_n_0_[2][5] ),\n .I3(out[4]),\n .O(\\fine_inc[2][5]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair339\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\fine_inc[2][5]_i_3 \n (.I0(dqs_count_r[2]),\n .I1(dqs_count_r[1]),\n .I2(dqs_count_r[0]),\n .O(\\fine_inc[2][5]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'h0074)) \n \\fine_inc[3][0]_i_1 \n (.I0(\\fine_inc[3][2]_i_3_n_0 ),\n .I1(out[1]),\n .I2(\\gen_final_tap[3].final_val_reg_n_0_[3][0] ),\n .I3(out[4]),\n .O(\\fine_inc[3][0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h090F0900)) \n \\fine_inc[3][1]_i_1 \n (.I0(\\fine_inc[3][2]_i_3_n_0 ),\n .I1(\\fine_inc[3][2]_i_2_n_0 ),\n .I2(out[4]),\n .I3(out[1]),\n .I4(\\gen_final_tap[3].final_val_reg_n_0_[3][1] ),\n .O(\\fine_inc[3][1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00E100FF00E10000)) \n \\fine_inc[3][2]_i_1 \n (.I0(\\fine_inc[3][2]_i_2_n_0 ),\n .I1(\\fine_inc[3][2]_i_3_n_0 ),\n .I2(\\fine_inc[3][2]_i_4_n_0 ),\n .I3(out[4]),\n .I4(out[1]),\n .I5(\\gen_final_tap[3].final_val_reg_n_0_[3][2] ),\n .O(\\fine_inc[3][2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\fine_inc[3][2]_i_2 \n (.I0(\\fine_inc_reg_n_0_[3][1] ),\n .I1(\\fine_inc_reg_n_0_[1][1] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\fine_inc_reg_n_0_[2][1] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\fine_inc_reg_n_0_[0][1] ),\n .O(\\fine_inc[3][2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\fine_inc[3][2]_i_3 \n (.I0(\\fine_inc_reg_n_0_[3][0] ),\n .I1(\\fine_inc_reg_n_0_[1][0] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\fine_inc_reg_n_0_[2][0] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\fine_inc_reg_n_0_[0][0] ),\n .O(\\fine_inc[3][2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\fine_inc[3][2]_i_4 \n (.I0(\\fine_inc_reg_n_0_[3][2] ),\n .I1(\\fine_inc_reg_n_0_[1][2] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\fine_inc_reg_n_0_[2][2] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\fine_inc_reg_n_0_[0][2] ),\n .O(\\fine_inc[3][2]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h060F0600)) \n \\fine_inc[3][3]_i_1 \n (.I0(\\fine_inc[3][4]_i_3_n_0 ),\n .I1(\\fine_inc[3][4]_i_2_n_0 ),\n .I2(out[4]),\n .I3(out[1]),\n .I4(\\gen_final_tap[3].final_val_reg_n_0_[3][3] ),\n .O(\\fine_inc[3][3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00D200FF00D20000)) \n \\fine_inc[3][4]_i_1 \n (.I0(\\fine_inc[3][4]_i_2_n_0 ),\n .I1(\\fine_inc[3][4]_i_3_n_0 ),\n .I2(\\fine_inc[3][4]_i_4_n_0 ),\n .I3(out[4]),\n .I4(out[1]),\n .I5(\\gen_final_tap[3].final_val_reg_n_0_[3][4] ),\n .O(\\fine_inc[3][4]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h01)) \n \\fine_inc[3][4]_i_2 \n (.I0(\\fine_inc[3][2]_i_3_n_0 ),\n .I1(\\fine_inc[3][2]_i_2_n_0 ),\n .I2(\\fine_inc[3][2]_i_4_n_0 ),\n .O(\\fine_inc[3][4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\fine_inc[3][4]_i_3 \n (.I0(\\fine_inc_reg_n_0_[3][3] ),\n .I1(\\fine_inc_reg_n_0_[1][3] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\fine_inc_reg_n_0_[2][3] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\fine_inc_reg_n_0_[0][3] ),\n .O(\\fine_inc[3][4]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\fine_inc[3][4]_i_4 \n (.I0(\\fine_inc_reg_n_0_[3][4] ),\n .I1(\\fine_inc_reg_n_0_[1][4] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\fine_inc_reg_n_0_[2][4] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\fine_inc_reg_n_0_[0][4] ),\n .O(\\fine_inc[3][4]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h008000800A800080)) \n \\fine_inc[3][5]_i_1 \n (.I0(\\fine_inc[3][5]_i_3_n_0 ),\n .I1(dqs_count_r140_out),\n .I2(out[2]),\n .I3(out[1]),\n .I4(\\fine_inc[3][5]_i_5_n_0 ),\n .I5(\\fine_inc[3][5]_i_6_n_0 ),\n .O(\\fine_inc[3][5]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h88B8)) \n \\fine_inc[3][5]_i_2 \n (.I0(\\fine_inc[3][5]_i_7_n_0 ),\n .I1(out[1]),\n .I2(\\gen_final_tap[3].final_val_reg_n_0_[3][5] ),\n .I3(out[4]),\n .O(\\fine_inc[3][5]_i_2_n_0 ));\n LUT3 #(\n .INIT(8'h08)) \n \\fine_inc[3][5]_i_3 \n (.I0(out[0]),\n .I1(out[3]),\n .I2(out[4]),\n .O(\\fine_inc[3][5]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair342\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\fine_inc[3][5]_i_4 \n (.I0(wr_level_done_r4),\n .I1(wr_level_done_r5),\n .O(dqs_count_r140_out));\n (* SOFT_HLUTNM = \"soft_lutpair315\" *) \n LUT3 #(\n .INIT(8'h40)) \n \\fine_inc[3][5]_i_5 \n (.I0(dqs_count_r[2]),\n .I1(dqs_count_r[1]),\n .I2(dqs_count_r[0]),\n .O(\\fine_inc[3][5]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'h0100FFFF)) \n \\fine_inc[3][5]_i_6 \n (.I0(\\fine_inc[3][5]_i_8_n_0 ),\n .I1(\\fine_inc[3][4]_i_3_n_0 ),\n .I2(\\fine_inc[3][4]_i_4_n_0 ),\n .I3(\\fine_inc[3][4]_i_2_n_0 ),\n .I4(wr_level_done_r5),\n .O(\\fine_inc[3][5]_i_6_n_0 ));\n LUT5 #(\n .INIT(32'h0000FD02)) \n \\fine_inc[3][5]_i_7 \n (.I0(\\fine_inc[3][4]_i_2_n_0 ),\n .I1(\\fine_inc[3][4]_i_3_n_0 ),\n .I2(\\fine_inc[3][4]_i_4_n_0 ),\n .I3(\\fine_inc[3][5]_i_8_n_0 ),\n .I4(out[4]),\n .O(\\fine_inc[3][5]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\fine_inc[3][5]_i_8 \n (.I0(\\fine_inc_reg_n_0_[3][5] ),\n .I1(\\fine_inc_reg_n_0_[1][5] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\fine_inc_reg_n_0_[2][5] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\fine_inc_reg_n_0_[0][5] ),\n .O(\\fine_inc[3][5]_i_8_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\fine_inc_reg[0][0] \n (.C(CLK),\n .CE(\\fine_inc[0][5]_i_1_n_0 ),\n .D(fine_inc[0]),\n .Q(\\fine_inc_reg_n_0_[0][0] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\fine_inc_reg[0][1] \n (.C(CLK),\n .CE(\\fine_inc[0][5]_i_1_n_0 ),\n .D(fine_inc[1]),\n .Q(\\fine_inc_reg_n_0_[0][1] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\fine_inc_reg[0][2] \n (.C(CLK),\n .CE(\\fine_inc[0][5]_i_1_n_0 ),\n .D(fine_inc[2]),\n .Q(\\fine_inc_reg_n_0_[0][2] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\fine_inc_reg[0][3] \n (.C(CLK),\n .CE(\\fine_inc[0][5]_i_1_n_0 ),\n .D(fine_inc[3]),\n .Q(\\fine_inc_reg_n_0_[0][3] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\fine_inc_reg[0][4] \n (.C(CLK),\n .CE(\\fine_inc[0][5]_i_1_n_0 ),\n .D(fine_inc[4]),\n .Q(\\fine_inc_reg_n_0_[0][4] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\fine_inc_reg[0][5] \n (.C(CLK),\n .CE(\\fine_inc[0][5]_i_1_n_0 ),\n .D(fine_inc[5]),\n .Q(\\fine_inc_reg_n_0_[0][5] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\fine_inc_reg[1][0] \n (.C(CLK),\n .CE(\\fine_inc[1][5]_i_1_n_0 ),\n .D(\\fine_inc[1][0]_i_1_n_0 ),\n .Q(\\fine_inc_reg_n_0_[1][0] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\fine_inc_reg[1][1] \n (.C(CLK),\n .CE(\\fine_inc[1][5]_i_1_n_0 ),\n .D(\\fine_inc[1][1]_i_1_n_0 ),\n .Q(\\fine_inc_reg_n_0_[1][1] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\fine_inc_reg[1][2] \n (.C(CLK),\n .CE(\\fine_inc[1][5]_i_1_n_0 ),\n .D(\\fine_inc[1][2]_i_1_n_0 ),\n .Q(\\fine_inc_reg_n_0_[1][2] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\fine_inc_reg[1][3] \n (.C(CLK),\n .CE(\\fine_inc[1][5]_i_1_n_0 ),\n .D(\\fine_inc[1][3]_i_1_n_0 ),\n .Q(\\fine_inc_reg_n_0_[1][3] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\fine_inc_reg[1][4] \n (.C(CLK),\n .CE(\\fine_inc[1][5]_i_1_n_0 ),\n .D(\\fine_inc[1][4]_i_1_n_0 ),\n .Q(\\fine_inc_reg_n_0_[1][4] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\fine_inc_reg[1][5] \n (.C(CLK),\n .CE(\\fine_inc[1][5]_i_1_n_0 ),\n .D(\\fine_inc[1][5]_i_2_n_0 ),\n .Q(\\fine_inc_reg_n_0_[1][5] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\fine_inc_reg[2][0] \n (.C(CLK),\n .CE(\\fine_inc[2][5]_i_1_n_0 ),\n .D(\\fine_inc[2][0]_i_1_n_0 ),\n .Q(\\fine_inc_reg_n_0_[2][0] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\fine_inc_reg[2][1] \n (.C(CLK),\n .CE(\\fine_inc[2][5]_i_1_n_0 ),\n .D(\\fine_inc[2][1]_i_1_n_0 ),\n .Q(\\fine_inc_reg_n_0_[2][1] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\fine_inc_reg[2][2] \n (.C(CLK),\n .CE(\\fine_inc[2][5]_i_1_n_0 ),\n .D(\\fine_inc[2][2]_i_1_n_0 ),\n .Q(\\fine_inc_reg_n_0_[2][2] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\fine_inc_reg[2][3] \n (.C(CLK),\n .CE(\\fine_inc[2][5]_i_1_n_0 ),\n .D(\\fine_inc[2][3]_i_1_n_0 ),\n .Q(\\fine_inc_reg_n_0_[2][3] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\fine_inc_reg[2][4] \n (.C(CLK),\n .CE(\\fine_inc[2][5]_i_1_n_0 ),\n .D(\\fine_inc[2][4]_i_1_n_0 ),\n .Q(\\fine_inc_reg_n_0_[2][4] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\fine_inc_reg[2][5] \n (.C(CLK),\n .CE(\\fine_inc[2][5]_i_1_n_0 ),\n .D(\\fine_inc[2][5]_i_2_n_0 ),\n .Q(\\fine_inc_reg_n_0_[2][5] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\fine_inc_reg[3][0] \n (.C(CLK),\n .CE(\\fine_inc[3][5]_i_1_n_0 ),\n .D(\\fine_inc[3][0]_i_1_n_0 ),\n .Q(\\fine_inc_reg_n_0_[3][0] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\fine_inc_reg[3][1] \n (.C(CLK),\n .CE(\\fine_inc[3][5]_i_1_n_0 ),\n .D(\\fine_inc[3][1]_i_1_n_0 ),\n .Q(\\fine_inc_reg_n_0_[3][1] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\fine_inc_reg[3][2] \n (.C(CLK),\n .CE(\\fine_inc[3][5]_i_1_n_0 ),\n .D(\\fine_inc[3][2]_i_1_n_0 ),\n .Q(\\fine_inc_reg_n_0_[3][2] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\fine_inc_reg[3][3] \n (.C(CLK),\n .CE(\\fine_inc[3][5]_i_1_n_0 ),\n .D(\\fine_inc[3][3]_i_1_n_0 ),\n .Q(\\fine_inc_reg_n_0_[3][3] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\fine_inc_reg[3][4] \n (.C(CLK),\n .CE(\\fine_inc[3][5]_i_1_n_0 ),\n .D(\\fine_inc[3][4]_i_1_n_0 ),\n .Q(\\fine_inc_reg_n_0_[3][4] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\fine_inc_reg[3][5] \n (.C(CLK),\n .CE(\\fine_inc[3][5]_i_1_n_0 ),\n .D(\\fine_inc[3][5]_i_2_n_0 ),\n .Q(\\fine_inc_reg_n_0_[3][5] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n LUT5 #(\n .INIT(32'h00820000)) \n flag_ck_negedge_i_10\n (.I0(out[1]),\n .I1(out[2]),\n .I2(out[3]),\n .I3(out[4]),\n .I4(out[0]),\n .O(flag_ck_negedge_i_10_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair311\" *) \n LUT3 #(\n .INIT(8'h7F)) \n flag_ck_negedge_i_2\n (.I0(\\stable_cnt_reg_n_0_[3] ),\n .I1(\\stable_cnt_reg_n_0_[2] ),\n .I2(\\stable_cnt_reg_n_0_[1] ),\n .O(stable_cnt1));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n flag_ck_negedge_i_3\n (.I0(\\rd_data_previous_r_reg_n_0_[3] ),\n .I1(\\rd_data_previous_r_reg_n_0_[2] ),\n .I2(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I3(\\rd_data_previous_r_reg_n_0_[1] ),\n .I4(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I5(\\rd_data_previous_r_reg_n_0_[0] ),\n .O(stable_cnt227_in));\n LUT6 #(\n .INIT(64'h0040FFFF00400040)) \n flag_ck_negedge_i_4\n (.I0(out[1]),\n .I1(out[2]),\n .I2(flag_ck_negedge_i_6_n_0),\n .I3(out[3]),\n .I4(flag_ck_negedge_i_7_n_0),\n .I5(stable_cnt227_in),\n .O(flag_ck_negedge09_out));\n LUT4 #(\n .INIT(16'hFFFE)) \n flag_ck_negedge_i_5\n (.I0(\\stable_cnt[3]_i_6_n_0 ),\n .I1(wr_level_done_r1_reg_0),\n .I2(flag_ck_negedge_i_8_n_0),\n .I3(rstdiv0_sync_r1_reg_rep__20),\n .O(flag_ck_negedge_reg_0));\n LUT2 #(\n .INIT(4'h1)) \n flag_ck_negedge_i_6\n (.I0(out[4]),\n .I1(out[0]),\n .O(flag_ck_negedge_i_6_n_0));\n LUT6 #(\n .INIT(64'h0000000000000001)) \n flag_ck_negedge_i_7\n (.I0(\\stable_cnt_reg_n_0_[2] ),\n .I1(\\stable_cnt_reg_n_0_[3] ),\n .I2(p_1_in_0),\n .I3(flag_ck_negedge_i_10_n_0),\n .I4(\\stable_cnt_reg[3]_0 ),\n .I5(\\stable_cnt_reg_n_0_[1] ),\n .O(flag_ck_negedge_i_7_n_0));\n LUT4 #(\n .INIT(16'h4000)) \n flag_ck_negedge_i_8\n (.I0(out[2]),\n .I1(out[3]),\n .I2(out[0]),\n .I3(out[4]),\n .O(flag_ck_negedge_i_8_n_0));\n LUT5 #(\n .INIT(32'h10000000)) \n flag_ck_negedge_i_9\n (.I0(out[4]),\n .I1(out[0]),\n .I2(out[3]),\n .I3(out[2]),\n .I4(out[1]),\n .O(p_1_in_0));\n FDRE #(\n .INIT(1'b0)) \n flag_ck_negedge_reg\n (.C(CLK),\n .CE(1'b1),\n .D(flag_ck_negedge_reg_1),\n .Q(\\rd_data_edge_detect_r_reg[0]_0 ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hAAAAAAAAAA8AAAAA)) \n flag_init_i_1\n (.I0(flag_init),\n .I1(\\wl_state_r1_reg_n_0_[0] ),\n .I2(p_1_in28_in),\n .I3(\\wl_state_r1_reg_n_0_[4] ),\n .I4(\\wl_state_r1_reg_n_0_[2] ),\n .I5(\\wl_state_r1_reg_n_0_[3] ),\n .O(flag_init_i_1_n_0));\n LUT5 #(\n .INIT(32'h04000000)) \n flag_init_i_2\n (.I0(out[3]),\n .I1(out[0]),\n .I2(out[4]),\n .I3(out[2]),\n .I4(out[1]),\n .O(p_1_in28_in));\n FDSE #(\n .INIT(1'b1)) \n flag_init_reg\n (.C(CLK),\n .CE(1'b1),\n .D(flag_init_i_1_n_0),\n .Q(flag_init),\n .S(rstdiv0_sync_r1_reg_rep__17[0]));\n LUT6 #(\n .INIT(64'h00000000EEEE22E2)) \n \\gen_byte_sel_div1.byte_sel_cnt[0]_i_1 \n (.I0(\\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ),\n .I1(pi_f_inc_reg),\n .I2(dqs_count_r[0]),\n .I3(wrlvl_done_r_reg),\n .I4(oclkdelay_calib_done_r_reg_0),\n .I5(delay_done_r4_reg),\n .O(\\gen_byte_sel_div1.byte_sel_cnt_reg[0] ));\n LUT6 #(\n .INIT(64'h00000000EEEE22E2)) \n \\gen_byte_sel_div1.byte_sel_cnt[1]_i_1 \n (.I0(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 ),\n .I1(pi_f_inc_reg),\n .I2(dqs_count_r[1]),\n .I3(wrlvl_done_r_reg),\n .I4(oclkdelay_calib_done_r_reg_1),\n .I5(delay_done_r4_reg),\n .O(\\gen_byte_sel_div1.byte_sel_cnt_reg[1] ));\n LUT6 #(\n .INIT(64'h00000000EEE222E2)) \n \\gen_byte_sel_div1.byte_sel_cnt[2]_i_1 \n (.I0(byte_sel_cnt),\n .I1(pi_f_inc_reg),\n .I2(dqs_count_r[2]),\n .I3(wrlvl_done_r_reg),\n .I4(\\prbs_dqs_cnt_r_reg[2] ),\n .I5(delay_done_r4_reg),\n .O(\\gen_byte_sel_div1.byte_sel_cnt_reg[2] ));\n LUT2 #(\n .INIT(4'h2)) \n \\gen_final_tap[0].final_val[0][5]_i_1 \n (.I0(wr_level_done_r2),\n .I1(wr_level_done_r3),\n .O(p_21_out));\n FDRE #(\n .INIT(1'b0)) \n \\gen_final_tap[0].final_val_reg[0][0] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[0]__0 [0]),\n .Q(\\gen_final_tap[0].final_val_reg_n_0_[0][0] ),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\gen_final_tap[0].final_val_reg[0][1] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[0]__0 [1]),\n .Q(\\gen_final_tap[0].final_val_reg_n_0_[0][1] ),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\gen_final_tap[0].final_val_reg[0][2] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[0]__0 [2]),\n .Q(\\gen_final_tap[0].final_val_reg_n_0_[0][2] ),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\gen_final_tap[0].final_val_reg[0][3] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[0]__0 [3]),\n .Q(\\gen_final_tap[0].final_val_reg_n_0_[0][3] ),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\gen_final_tap[0].final_val_reg[0][4] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[0]__0 [4]),\n .Q(\\gen_final_tap[0].final_val_reg_n_0_[0][4] ),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\gen_final_tap[0].final_val_reg[0][5] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[0]__0 [5]),\n .Q(\\gen_final_tap[0].final_val_reg_n_0_[0][5] ),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\gen_final_tap[1].final_val_reg[1][0] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[1]__0 [0]),\n .Q(\\gen_final_tap[1].final_val_reg_n_0_[1][0] ),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\gen_final_tap[1].final_val_reg[1][1] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[1]__0 [1]),\n .Q(\\gen_final_tap[1].final_val_reg_n_0_[1][1] ),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\gen_final_tap[1].final_val_reg[1][2] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[1]__0 [2]),\n .Q(\\gen_final_tap[1].final_val_reg_n_0_[1][2] ),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\gen_final_tap[1].final_val_reg[1][3] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[1]__0 [3]),\n .Q(\\gen_final_tap[1].final_val_reg_n_0_[1][3] ),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\gen_final_tap[1].final_val_reg[1][4] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[1]__0 [4]),\n .Q(\\gen_final_tap[1].final_val_reg_n_0_[1][4] ),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\gen_final_tap[1].final_val_reg[1][5] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[1]__0 [5]),\n .Q(\\gen_final_tap[1].final_val_reg_n_0_[1][5] ),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\gen_final_tap[2].final_val_reg[2][0] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[2]__0 [0]),\n .Q(\\gen_final_tap[2].final_val_reg_n_0_[2][0] ),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\gen_final_tap[2].final_val_reg[2][1] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[2]__0 [1]),\n .Q(\\gen_final_tap[2].final_val_reg_n_0_[2][1] ),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\gen_final_tap[2].final_val_reg[2][2] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[2]__0 [2]),\n .Q(\\gen_final_tap[2].final_val_reg_n_0_[2][2] ),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\gen_final_tap[2].final_val_reg[2][3] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[2]__0 [3]),\n .Q(\\gen_final_tap[2].final_val_reg_n_0_[2][3] ),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\gen_final_tap[2].final_val_reg[2][4] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[2]__0 [4]),\n .Q(\\gen_final_tap[2].final_val_reg_n_0_[2][4] ),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\gen_final_tap[2].final_val_reg[2][5] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[2]__0 [5]),\n .Q(\\gen_final_tap[2].final_val_reg_n_0_[2][5] ),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\gen_final_tap[3].final_val_reg[3][0] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[3]__0 [0]),\n .Q(\\gen_final_tap[3].final_val_reg_n_0_[3][0] ),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\gen_final_tap[3].final_val_reg[3][1] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[3]__0 [1]),\n .Q(\\gen_final_tap[3].final_val_reg_n_0_[3][1] ),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\gen_final_tap[3].final_val_reg[3][2] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[3]__0 [2]),\n .Q(\\gen_final_tap[3].final_val_reg_n_0_[3][2] ),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\gen_final_tap[3].final_val_reg[3][3] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[3]__0 [3]),\n .Q(\\gen_final_tap[3].final_val_reg_n_0_[3][3] ),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\gen_final_tap[3].final_val_reg[3][4] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[3]__0 [4]),\n .Q(\\gen_final_tap[3].final_val_reg_n_0_[3][4] ),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\gen_final_tap[3].final_val_reg[3][5] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[3]__0 [5]),\n .Q(\\gen_final_tap[3].final_val_reg_n_0_[3][5] ),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\gen_rd[0].rd_data_rise_wl_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_1_n_0 ),\n .Q(\\gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_rd[1].rd_data_rise_wl_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_1_n_0 ),\n .Q(\\gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_rd[2].rd_data_rise_wl_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_1_n_0 ),\n .Q(\\gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\gen_rd[3].rd_data_rise_wl_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_1_n_0 ),\n .Q(\\gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3] ),\n .R(1'b0));\n LUT1 #(\n .INIT(2'h1)) \n \\incdec_wait_cnt[0]_i_1 \n (.I0(incdec_wait_cnt_reg__0[0]),\n .O(p_0_in__0__0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair347\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\incdec_wait_cnt[1]_i_1 \n (.I0(incdec_wait_cnt_reg__0[0]),\n .I1(incdec_wait_cnt_reg__0[1]),\n .O(p_0_in__0__0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair347\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\incdec_wait_cnt[2]_i_1 \n (.I0(incdec_wait_cnt_reg__0[2]),\n .I1(incdec_wait_cnt_reg__0[1]),\n .I2(incdec_wait_cnt_reg__0[0]),\n .O(p_0_in__0__0[2]));\n LUT6 #(\n .INIT(64'hFFFBFFEFFEFFFFFF)) \n \\incdec_wait_cnt[3]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__22),\n .I1(out[1]),\n .I2(out[0]),\n .I3(out[4]),\n .I4(out[2]),\n .I5(out[3]),\n .O(\\incdec_wait_cnt[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair318\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\incdec_wait_cnt[3]_i_2 \n (.I0(incdec_wait_cnt_reg__0[3]),\n .I1(incdec_wait_cnt_reg__0[0]),\n .I2(incdec_wait_cnt_reg__0[1]),\n .I3(incdec_wait_cnt_reg__0[2]),\n .O(p_0_in__0__0[3]));\n FDRE #(\n .INIT(1'b0)) \n \\incdec_wait_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0__0[0]),\n .Q(incdec_wait_cnt_reg__0[0]),\n .R(\\incdec_wait_cnt[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\incdec_wait_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0__0[1]),\n .Q(incdec_wait_cnt_reg__0[1]),\n .R(\\incdec_wait_cnt[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\incdec_wait_cnt_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0__0[2]),\n .Q(incdec_wait_cnt_reg__0[2]),\n .R(\\incdec_wait_cnt[3]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\incdec_wait_cnt_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0__0[3]),\n .Q(incdec_wait_cnt_reg__0[3]),\n .R(\\incdec_wait_cnt[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h2F203F3F2F203333)) \n inhibit_edge_detect_r_i_2\n (.I0(wrlvl_byte_redo),\n .I1(out[3]),\n .I2(out[4]),\n .I3(stable_cnt227_in),\n .I4(out[2]),\n .I5(\\FSM_sequential_wl_state_r[3]_i_10_n_0 ),\n .O(inhibit_edge_detect_r));\n LUT6 #(\n .INIT(64'h0000008303080003)) \n inhibit_edge_detect_r_i_3\n (.I0(inhibit_edge_detect_r_i_4_n_0),\n .I1(out[2]),\n .I2(out[4]),\n .I3(out[3]),\n .I4(out[1]),\n .I5(out[0]),\n .O(inhibit_edge_detect_r_reg_0));\n LUT6 #(\n .INIT(64'h8080808080808F80)) \n inhibit_edge_detect_r_i_4\n (.I0(wrlvl_byte_redo),\n .I1(\\FSM_sequential_wl_state_r[2]_i_6_n_0 ),\n .I2(out[4]),\n .I3(wl_sm_start),\n .I4(stable_cnt1),\n .I5(stable_cnt227_in),\n .O(inhibit_edge_detect_r_i_4_n_0));\n FDSE #(\n .INIT(1'b1)) \n inhibit_edge_detect_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(inhibit_edge_detect_r_reg_1),\n .Q(\\rd_data_edge_detect_r_reg[0]_1 ),\n .S(SR[0]));\n LUT6 #(\n .INIT(64'h222222F2F2F2F2FF)) \n \\lim_state[12]_i_6 \n (.I0(\\stg2_target_r_reg[4] [1]),\n .I1(\\stg2_tap_cnt_reg[2] [2]),\n .I2(\\stg2_target_r_reg[4] [0]),\n .I3(\\stg2_r_reg[0] ),\n .I4(\\stg2_tap_cnt_reg[2] [0]),\n .I5(\\stg2_tap_cnt_reg[2] [1]),\n .O(\\lim_state_reg[12] ));\n LUT5 #(\n .INIT(32'hFFFEFFFF)) \n \\p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_1 \n (.I0(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),\n .I2(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),\n .I4(\\p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_2_n_0 ),\n .O(\\p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000001105)) \n \\p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_2 \n (.I0(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),\n .I2(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ),\n .I3(my_empty),\n .I4(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),\n .O(\\p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFEFFFF)) \n \\p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_1 \n (.I0(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),\n .I2(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),\n .I4(\\p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_2_n_0 ),\n .O(\\p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000001105)) \n \\p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_2 \n (.I0(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),\n .I2(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ),\n .I3(my_empty_6),\n .I4(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),\n .O(\\p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFEFFFF)) \n \\p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_1 \n (.I0(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ),\n .I2(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ),\n .I4(\\p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_2_n_0 ),\n .O(\\p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000001105)) \n \\p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_2 \n (.I0(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ),\n .I2(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ),\n .I3(my_empty_7),\n .I4(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),\n .O(\\p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFEFFFF)) \n \\p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_1 \n (.I0(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ),\n .I2(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ),\n .I4(\\p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_2_n_0 ),\n .O(\\p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000001105)) \n \\p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_2 \n (.I0(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ),\n .I2(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ),\n .I3(my_empty_8),\n .I4(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ),\n .O(\\p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_2_n_0 ));\n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/phy_ctl_ready_r4_reg_srl4 \" *) \n SRL16E #(\n .INIT(16'h0000)) \n phy_ctl_ready_r4_reg_srl4\n (.A0(1'b1),\n .A1(1'b1),\n .A2(1'b0),\n .A3(1'b0),\n .CE(1'b1),\n .CLK(CLK),\n .D(\\mcGo_r_reg[15] ),\n .Q(phy_ctl_ready_r4_reg_srl4_n_0));\n FDRE #(\n .INIT(1'b0)) \n phy_ctl_ready_r5_reg\n (.C(CLK),\n .CE(1'b1),\n .D(phy_ctl_ready_r4_reg_srl4_n_0),\n .Q(phy_ctl_ready_r5),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n phy_ctl_ready_r6_reg\n (.C(CLK),\n .CE(1'b1),\n .D(phy_ctl_ready_r5),\n .Q(phy_ctl_ready_r6_reg_n_0),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair313\" *) \n LUT5 #(\n .INIT(32'hFFFFFDFF)) \n po_cnt_dec_i_2\n (.I0(wait_cnt_reg__0[0]),\n .I1(wait_cnt_reg__0[1]),\n .I2(wait_cnt_reg__0[3]),\n .I3(phy_ctl_ready_r6_reg_n_0),\n .I4(wait_cnt_reg__0[2]),\n .O(po_cnt_dec_reg_0));\n FDRE #(\n .INIT(1'b0)) \n po_cnt_dec_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\wait_cnt_reg[0]_0 ),\n .Q(dqs_po_en_stg2_f_reg_0),\n .R(1'b0));\n LUT3 #(\n .INIT(8'hF4)) \n po_dec_done_i_1\n (.I0(po_dec_done_i_2_n_0),\n .I1(po_dec_done_i_3_n_0),\n .I2(po_dec_done),\n .O(po_dec_done_i_1_n_0));\n LUT5 #(\n .INIT(32'hEEEFFFEF)) \n po_dec_done_i_2\n (.I0(po_rdval_cnt[2]),\n .I1(po_rdval_cnt[1]),\n .I2(phy_ctl_ready_r6_reg_n_0),\n .I3(po_rdval_cnt[0]),\n .I4(dqs_po_en_stg2_f_reg_0),\n .O(po_dec_done_i_2_n_0));\n LUT6 #(\n .INIT(64'h0000000000000001)) \n po_dec_done_i_3\n (.I0(po_rdval_cnt[7]),\n .I1(po_rdval_cnt[3]),\n .I2(po_rdval_cnt[4]),\n .I3(po_rdval_cnt[5]),\n .I4(po_rdval_cnt[6]),\n .I5(po_rdval_cnt[8]),\n .O(po_dec_done_i_3_n_0));\n FDRE #(\n .INIT(1'b0)) \n po_dec_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(po_dec_done_i_1_n_0),\n .Q(po_dec_done),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n LUT6 #(\n .INIT(64'hAC00AC00ACFFAC00)) \n \\po_rdval_cnt[0]_i_1 \n (.I0(\\po_counter_read_val_reg[8] [0]),\n .I1(\\po_counter_read_val_reg[8]_0 [0]),\n .I2(\\calib_sel_reg[3] ),\n .I3(\\po_rdval_cnt[8]_i_4_n_0 ),\n .I4(\\po_rdval_cnt_reg[0]_0 ),\n .I5(po_rdval_cnt[0]),\n .O(\\po_rdval_cnt[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFB0808080808FB08)) \n \\po_rdval_cnt[1]_i_1 \n (.I0(\\po_counter_read_val_reg[5] [0]),\n .I1(phy_ctl_ready_r5),\n .I2(phy_ctl_ready_r6_reg_n_0),\n .I3(\\po_rdval_cnt_reg[0]_0 ),\n .I4(po_rdval_cnt[0]),\n .I5(po_rdval_cnt[1]),\n .O(\\po_rdval_cnt[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hB8B8B888888888B8)) \n \\po_rdval_cnt[2]_i_1 \n (.I0(\\po_counter_read_val_reg[5] [1]),\n .I1(\\po_rdval_cnt[8]_i_4_n_0 ),\n .I2(\\po_rdval_cnt_reg[0]_0 ),\n .I3(po_rdval_cnt[1]),\n .I4(po_rdval_cnt[0]),\n .I5(po_rdval_cnt[2]),\n .O(\\po_rdval_cnt[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAC00ACFFACFFAC00)) \n \\po_rdval_cnt[3]_i_1 \n (.I0(\\po_counter_read_val_reg[8] [1]),\n .I1(\\po_counter_read_val_reg[8]_0 [1]),\n .I2(\\calib_sel_reg[3] ),\n .I3(\\po_rdval_cnt[8]_i_4_n_0 ),\n .I4(po_rdval_cnt[3]),\n .I5(\\po_rdval_cnt[4]_i_2_n_0 ),\n .O(\\po_rdval_cnt[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFB0808FBFB08FB08)) \n \\po_rdval_cnt[4]_i_1 \n (.I0(\\po_counter_read_val_reg[5] [2]),\n .I1(phy_ctl_ready_r5),\n .I2(phy_ctl_ready_r6_reg_n_0),\n .I3(po_rdval_cnt[4]),\n .I4(po_rdval_cnt[3]),\n .I5(\\po_rdval_cnt[4]_i_2_n_0 ),\n .O(\\po_rdval_cnt[4]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h0001)) \n \\po_rdval_cnt[4]_i_2 \n (.I0(po_rdval_cnt[1]),\n .I1(po_rdval_cnt[0]),\n .I2(po_rdval_cnt[2]),\n .I3(po_dec_done_i_3_n_0),\n .O(\\po_rdval_cnt[4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFB0808080808FB08)) \n \\po_rdval_cnt[5]_i_1 \n (.I0(\\po_counter_read_val_reg[5] [3]),\n .I1(phy_ctl_ready_r5),\n .I2(phy_ctl_ready_r6_reg_n_0),\n .I3(\\po_rdval_cnt_reg[0]_0 ),\n .I4(\\po_rdval_cnt[5]_i_2_n_0 ),\n .I5(po_rdval_cnt[5]),\n .O(\\po_rdval_cnt[5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair312\" *) \n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n \\po_rdval_cnt[5]_i_2 \n (.I0(po_rdval_cnt[3]),\n .I1(po_rdval_cnt[4]),\n .I2(po_rdval_cnt[1]),\n .I3(po_rdval_cnt[0]),\n .I4(po_rdval_cnt[2]),\n .O(\\po_rdval_cnt[5]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFACFF0000AC00)) \n \\po_rdval_cnt[6]_i_1 \n (.I0(\\po_counter_read_val_reg[8] [2]),\n .I1(\\po_counter_read_val_reg[8]_0 [2]),\n .I2(\\calib_sel_reg[3] ),\n .I3(phy_ctl_ready_r5),\n .I4(phy_ctl_ready_r6_reg_n_0),\n .I5(\\po_rdval_cnt[6]_i_2_n_0 ),\n .O(\\po_rdval_cnt[6]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAA8A00000020)) \n \\po_rdval_cnt[6]_i_2 \n (.I0(\\po_rdval_cnt_reg[0]_0 ),\n .I1(po_rdval_cnt[5]),\n .I2(\\po_rdval_cnt[8]_i_7_n_0 ),\n .I3(po_rdval_cnt[4]),\n .I4(po_rdval_cnt[3]),\n .I5(po_rdval_cnt[6]),\n .O(\\po_rdval_cnt[6]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFACFF0000AC00)) \n \\po_rdval_cnt[7]_i_1 \n (.I0(\\po_counter_read_val_reg[8] [3]),\n .I1(\\po_counter_read_val_reg[8]_0 [3]),\n .I2(\\calib_sel_reg[3] ),\n .I3(phy_ctl_ready_r5),\n .I4(phy_ctl_ready_r6_reg_n_0),\n .I5(\\po_rdval_cnt[7]_i_2_n_0 ),\n .O(\\po_rdval_cnt[7]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFC00000002)) \n \\po_rdval_cnt[7]_i_2 \n (.I0(po_rdval_cnt[8]),\n .I1(po_rdval_cnt[1]),\n .I2(po_rdval_cnt[0]),\n .I3(po_rdval_cnt[2]),\n .I4(\\po_rdval_cnt[8]_i_6_n_0 ),\n .I5(po_rdval_cnt[7]),\n .O(\\po_rdval_cnt[7]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'hAEFF)) \n \\po_rdval_cnt[8]_i_1 \n (.I0(dqs_po_en_stg2_f_reg_0),\n .I1(phy_ctl_ready_r5),\n .I2(phy_ctl_ready_r6_reg_n_0),\n .I3(\\po_rdval_cnt_reg[0]_0 ),\n .O(\\po_rdval_cnt[8]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hACFFAC00AC00AC00)) \n \\po_rdval_cnt[8]_i_2 \n (.I0(\\po_counter_read_val_reg[8] [4]),\n .I1(\\po_counter_read_val_reg[8]_0 [4]),\n .I2(\\calib_sel_reg[3] ),\n .I3(\\po_rdval_cnt[8]_i_4_n_0 ),\n .I4(po_rdval_cnt[8]),\n .I5(\\po_rdval_cnt[8]_i_5_n_0 ),\n .O(\\po_rdval_cnt[8]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\po_rdval_cnt[8]_i_3 \n (.I0(po_rdval_cnt[8]),\n .I1(po_rdval_cnt[1]),\n .I2(po_rdval_cnt[0]),\n .I3(po_rdval_cnt[2]),\n .I4(\\po_rdval_cnt[8]_i_6_n_0 ),\n .I5(po_rdval_cnt[7]),\n .O(\\po_rdval_cnt_reg[0]_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\po_rdval_cnt[8]_i_4 \n (.I0(phy_ctl_ready_r5),\n .I1(phy_ctl_ready_r6_reg_n_0),\n .O(\\po_rdval_cnt[8]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFEFFFFFFFF)) \n \\po_rdval_cnt[8]_i_5 \n (.I0(po_rdval_cnt[7]),\n .I1(po_rdval_cnt[3]),\n .I2(po_rdval_cnt[4]),\n .I3(po_rdval_cnt[5]),\n .I4(po_rdval_cnt[6]),\n .I5(\\po_rdval_cnt[8]_i_7_n_0 ),\n .O(\\po_rdval_cnt[8]_i_5_n_0 ));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\po_rdval_cnt[8]_i_6 \n (.I0(po_rdval_cnt[3]),\n .I1(po_rdval_cnt[4]),\n .I2(po_rdval_cnt[5]),\n .I3(po_rdval_cnt[6]),\n .O(\\po_rdval_cnt[8]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair312\" *) \n LUT3 #(\n .INIT(8'h01)) \n \\po_rdval_cnt[8]_i_7 \n (.I0(po_rdval_cnt[2]),\n .I1(po_rdval_cnt[0]),\n .I2(po_rdval_cnt[1]),\n .O(\\po_rdval_cnt[8]_i_7_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\po_rdval_cnt_reg[0] \n (.C(CLK),\n .CE(\\po_rdval_cnt[8]_i_1_n_0 ),\n .D(\\po_rdval_cnt[0]_i_1_n_0 ),\n .Q(po_rdval_cnt[0]),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\po_rdval_cnt_reg[1] \n (.C(CLK),\n .CE(\\po_rdval_cnt[8]_i_1_n_0 ),\n .D(\\po_rdval_cnt[1]_i_1_n_0 ),\n .Q(po_rdval_cnt[1]),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\po_rdval_cnt_reg[2] \n (.C(CLK),\n .CE(\\po_rdval_cnt[8]_i_1_n_0 ),\n .D(\\po_rdval_cnt[2]_i_1_n_0 ),\n .Q(po_rdval_cnt[2]),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\po_rdval_cnt_reg[3] \n (.C(CLK),\n .CE(\\po_rdval_cnt[8]_i_1_n_0 ),\n .D(\\po_rdval_cnt[3]_i_1_n_0 ),\n .Q(po_rdval_cnt[3]),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\po_rdval_cnt_reg[4] \n (.C(CLK),\n .CE(\\po_rdval_cnt[8]_i_1_n_0 ),\n .D(\\po_rdval_cnt[4]_i_1_n_0 ),\n .Q(po_rdval_cnt[4]),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\po_rdval_cnt_reg[5] \n (.C(CLK),\n .CE(\\po_rdval_cnt[8]_i_1_n_0 ),\n .D(\\po_rdval_cnt[5]_i_1_n_0 ),\n .Q(po_rdval_cnt[5]),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\po_rdval_cnt_reg[6] \n (.C(CLK),\n .CE(\\po_rdval_cnt[8]_i_1_n_0 ),\n .D(\\po_rdval_cnt[6]_i_1_n_0 ),\n .Q(po_rdval_cnt[6]),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\po_rdval_cnt_reg[7] \n (.C(CLK),\n .CE(\\po_rdval_cnt[8]_i_1_n_0 ),\n .D(\\po_rdval_cnt[7]_i_1_n_0 ),\n .Q(po_rdval_cnt[7]),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\po_rdval_cnt_reg[8] \n (.C(CLK),\n .CE(\\po_rdval_cnt[8]_i_1_n_0 ),\n .D(\\po_rdval_cnt[8]_i_2_n_0 ),\n .Q(po_rdval_cnt[8]),\n .R(SR[0]));\n (* SOFT_HLUTNM = \"soft_lutpair346\" *) \n LUT3 #(\n .INIT(8'h38)) \n \\rank_cnt_r[0]_i_1 \n (.I0(\\rank_cnt_r_reg[0]_0 ),\n .I1(rank_cnt_r),\n .I2(\\rank_cnt_r_reg[0]_1 ),\n .O(\\rank_cnt_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair346\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\rank_cnt_r[1]_i_1 \n (.I0(\\rank_cnt_r_reg[0]_1 ),\n .I1(rank_cnt_r),\n .I2(\\rank_cnt_r_reg[0]_0 ),\n .O(\\rank_cnt_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000200000000000)) \n \\rank_cnt_r[1]_i_2 \n (.I0(out[4]),\n .I1(out[2]),\n .I2(out[1]),\n .I3(out[0]),\n .I4(p_0_in),\n .I5(out[3]),\n .O(rank_cnt_r));\n FDRE #(\n .INIT(1'b0)) \n \\rank_cnt_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rank_cnt_r[0]_i_1_n_0 ),\n .Q(\\rank_cnt_r_reg[0]_1 ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\rank_cnt_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rank_cnt_r[1]_i_1_n_0 ),\n .Q(\\rank_cnt_r_reg[0]_0 ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n (* SOFT_HLUTNM = \"soft_lutpair341\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\rd_data_edge_detect_r[0]_i_1 \n (.I0(\\rd_data_edge_detect_r[3]_i_6_n_0 ),\n .I1(\\gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ),\n .I2(\\rd_data_previous_r_reg_n_0_[0] ),\n .O(\\rd_data_edge_detect_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair341\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\rd_data_edge_detect_r[1]_i_1 \n (.I0(\\rd_data_edge_detect_r[3]_i_6_n_0 ),\n .I1(\\gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ),\n .I2(\\rd_data_previous_r_reg_n_0_[1] ),\n .O(\\rd_data_edge_detect_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair343\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\rd_data_edge_detect_r[2]_i_1 \n (.I0(\\rd_data_edge_detect_r[3]_i_6_n_0 ),\n .I1(\\gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2] ),\n .I2(\\rd_data_previous_r_reg_n_0_[2] ),\n .O(\\rd_data_edge_detect_r[2]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n \\rd_data_edge_detect_r[3]_i_1 \n (.I0(\\rd_data_edge_detect_r[3]_i_4_n_0 ),\n .I1(\\rd_data_edge_detect_r_reg[0]_1 ),\n .I2(flag_init),\n .I3(rstdiv0_sync_r1_reg_rep__22),\n .I4(\\rd_data_edge_detect_r_reg[0]_0 ),\n .O(rd_data_edge_detect_r0));\n LUT6 #(\n .INIT(64'h49484044FFFFFFFF)) \n \\rd_data_edge_detect_r[3]_i_2 \n (.I0(out[3]),\n .I1(out[2]),\n .I2(out[4]),\n .I3(out[0]),\n .I4(out[1]),\n .I5(\\rd_data_edge_detect_r[3]_i_5_n_0 ),\n .O(\\rd_data_edge_detect_r[3]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair343\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\rd_data_edge_detect_r[3]_i_3 \n (.I0(\\rd_data_edge_detect_r[3]_i_6_n_0 ),\n .I1(\\gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3] ),\n .I2(\\rd_data_previous_r_reg_n_0_[3] ),\n .O(\\rd_data_edge_detect_r[3]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000001)) \n \\rd_data_edge_detect_r[3]_i_4 \n (.I0(\\wl_tap_count_r_reg_n_0_[0] ),\n .I1(\\wl_tap_count_r_reg_n_0_[1] ),\n .I2(\\wl_tap_count_r_reg_n_0_[2] ),\n .I3(\\wl_tap_count_r_reg_n_0_[3] ),\n .I4(\\wl_tap_count_r_reg_n_0_[5] ),\n .I5(\\wl_tap_count_r_reg_n_0_[4] ),\n .O(\\rd_data_edge_detect_r[3]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\rd_data_edge_detect_r[3]_i_5 \n (.I0(\\rd_data_edge_detect_r_reg_n_0_[3] ),\n .I1(\\rd_data_edge_detect_r_reg_n_0_[2] ),\n .I2(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I3(\\rd_data_edge_detect_r_reg_n_0_[1] ),\n .I4(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I5(\\rd_data_edge_detect_r_reg_n_0_[0] ),\n .O(\\rd_data_edge_detect_r[3]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair311\" *) \n LUT5 #(\n .INIT(32'h000080FF)) \n \\rd_data_edge_detect_r[3]_i_6 \n (.I0(\\stable_cnt_reg_n_0_[3] ),\n .I1(\\stable_cnt_reg_n_0_[2] ),\n .I2(\\stable_cnt_reg_n_0_[1] ),\n .I3(stable_cnt227_in),\n .I4(\\rd_data_edge_detect_r[3]_i_5_n_0 ),\n .O(\\rd_data_edge_detect_r[3]_i_6_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rd_data_edge_detect_r_reg[0] \n (.C(CLK),\n .CE(\\rd_data_edge_detect_r[3]_i_2_n_0 ),\n .D(\\rd_data_edge_detect_r[0]_i_1_n_0 ),\n .Q(\\rd_data_edge_detect_r_reg_n_0_[0] ),\n .R(rd_data_edge_detect_r0));\n FDRE #(\n .INIT(1'b0)) \n \\rd_data_edge_detect_r_reg[1] \n (.C(CLK),\n .CE(\\rd_data_edge_detect_r[3]_i_2_n_0 ),\n .D(\\rd_data_edge_detect_r[1]_i_1_n_0 ),\n .Q(\\rd_data_edge_detect_r_reg_n_0_[1] ),\n .R(rd_data_edge_detect_r0));\n FDRE #(\n .INIT(1'b0)) \n \\rd_data_edge_detect_r_reg[2] \n (.C(CLK),\n .CE(\\rd_data_edge_detect_r[3]_i_2_n_0 ),\n .D(\\rd_data_edge_detect_r[2]_i_1_n_0 ),\n .Q(\\rd_data_edge_detect_r_reg_n_0_[2] ),\n .R(rd_data_edge_detect_r0));\n FDRE #(\n .INIT(1'b0)) \n \\rd_data_edge_detect_r_reg[3] \n (.C(CLK),\n .CE(\\rd_data_edge_detect_r[3]_i_2_n_0 ),\n .D(\\rd_data_edge_detect_r[3]_i_3_n_0 ),\n .Q(\\rd_data_edge_detect_r_reg_n_0_[3] ),\n .R(rd_data_edge_detect_r0));\n LUT6 #(\n .INIT(64'hAAEEAAAAFFABAAFA)) \n \\rd_data_previous_r[3]_i_1 \n (.I0(\\rd_data_previous_r[3]_i_2_n_0 ),\n .I1(out[1]),\n .I2(out[0]),\n .I3(out[4]),\n .I4(out[2]),\n .I5(out[3]),\n .O(rd_data_previous_r0));\n LUT6 #(\n .INIT(64'hFFFFFFFF00000020)) \n \\rd_data_previous_r[3]_i_2 \n (.I0(\\FSM_sequential_wl_state_r_reg[0]_0 ),\n .I1(\\rd_data_previous_r[3]_i_3_n_0 ),\n .I2(out[3]),\n .I3(out[2]),\n .I4(out[1]),\n .I5(\\rd_data_previous_r[3]_i_4_n_0 ),\n .O(\\rd_data_previous_r[3]_i_2_n_0 ));\n LUT2 #(\n .INIT(4'hB)) \n \\rd_data_previous_r[3]_i_3 \n (.I0(out[0]),\n .I1(out[4]),\n .O(\\rd_data_previous_r[3]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000400)) \n \\rd_data_previous_r[3]_i_4 \n (.I0(\\wl_state_r1_reg_n_0_[0] ),\n .I1(p_0_in32_in),\n .I2(\\wl_state_r1_reg_n_0_[4] ),\n .I3(\\wl_state_r1_reg_n_0_[2] ),\n .I4(\\wl_state_r1_reg_n_0_[3] ),\n .I5(\\wl_state_r1_reg_n_0_[1] ),\n .O(\\rd_data_previous_r[3]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h00000100)) \n \\rd_data_previous_r[3]_i_5 \n (.I0(out[3]),\n .I1(out[4]),\n .I2(out[0]),\n .I3(out[1]),\n .I4(out[2]),\n .O(p_0_in32_in));\n FDRE #(\n .INIT(1'b0)) \n \\rd_data_previous_r_reg[0] \n (.C(CLK),\n .CE(rd_data_previous_r0),\n .D(\\gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ),\n .Q(\\rd_data_previous_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rd_data_previous_r_reg[1] \n (.C(CLK),\n .CE(rd_data_previous_r0),\n .D(\\gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ),\n .Q(\\rd_data_previous_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rd_data_previous_r_reg[2] \n (.C(CLK),\n .CE(rd_data_previous_r0),\n .D(\\gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2] ),\n .Q(\\rd_data_previous_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rd_data_previous_r_reg[3] \n (.C(CLK),\n .CE(rd_data_previous_r0),\n .D(\\gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3] ),\n .Q(\\rd_data_previous_r_reg_n_0_[3] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h000000000000FBF8)) \n \\single_rank.done_dqs_dec_i_1 \n (.I0(done_dqs_tap_inc),\n .I1(oclkdelay_calib_done_r_reg),\n .I2(done_dqs_dec),\n .I3(wr_level_done_r1_reg_0),\n .I4(wr_level_done0),\n .I5(rstdiv0_sync_r1_reg_rep__22),\n .O(\\single_rank.done_dqs_dec_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair342\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\single_rank.done_dqs_dec_i_2 \n (.I0(oclkdelay_calib_done_r_reg),\n .I1(wr_level_done_r3),\n .I2(wr_level_done_r4),\n .O(done_dqs_dec));\n (* SOFT_HLUTNM = \"soft_lutpair319\" *) \n LUT4 #(\n .INIT(16'h4F44)) \n \\single_rank.done_dqs_dec_i_3 \n (.I0(wrlvl_byte_redo_r),\n .I1(wrlvl_byte_redo),\n .I2(wrlvl_final_r),\n .I3(wrlvl_final_mux),\n .O(wr_level_done0));\n FDRE #(\n .INIT(1'b0)) \n \\single_rank.done_dqs_dec_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\single_rank.done_dqs_dec_i_1_n_0 ),\n .Q(done_dqs_tap_inc),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair329\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[0][0]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][0][0] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][0]_i_2_n_0 ),\n .O(largest[0]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\smallest[0][0]_i_2 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][3][0] ),\n .I1(\\wl_dqs_tap_count_r_reg_n_0_[0][1][0] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\wl_dqs_tap_count_r_reg_n_0_[0][2][0] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\wl_dqs_tap_count_r_reg_n_0_[0][0][0] ),\n .O(\\smallest[0][0]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair330\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[0][1]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][0][1] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][1]_i_2_n_0 ),\n .O(largest[1]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\smallest[0][1]_i_2 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][3][1] ),\n .I1(\\wl_dqs_tap_count_r_reg_n_0_[0][1][1] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\wl_dqs_tap_count_r_reg_n_0_[0][2][1] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\wl_dqs_tap_count_r_reg_n_0_[0][0][1] ),\n .O(\\smallest[0][1]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair329\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[0][2]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][0][2] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][2]_i_2_n_0 ),\n .O(largest[2]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\smallest[0][2]_i_2 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][3][2] ),\n .I1(\\wl_dqs_tap_count_r_reg_n_0_[0][1][2] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\wl_dqs_tap_count_r_reg_n_0_[0][2][2] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\wl_dqs_tap_count_r_reg_n_0_[0][0][2] ),\n .O(\\smallest[0][2]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair331\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[0][3]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][0][3] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][3]_i_2_n_0 ),\n .O(largest[3]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\smallest[0][3]_i_2 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][3][3] ),\n .I1(\\wl_dqs_tap_count_r_reg_n_0_[0][1][3] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\wl_dqs_tap_count_r_reg_n_0_[0][2][3] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\wl_dqs_tap_count_r_reg_n_0_[0][0][3] ),\n .O(\\smallest[0][3]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair330\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[0][4]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][0][4] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][4]_i_2_n_0 ),\n .O(largest[4]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\smallest[0][4]_i_2 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][3][4] ),\n .I1(\\wl_dqs_tap_count_r_reg_n_0_[0][1][4] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\wl_dqs_tap_count_r_reg_n_0_[0][2][4] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\wl_dqs_tap_count_r_reg_n_0_[0][0][4] ),\n .O(\\smallest[0][4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0010FFFF00100000)) \n \\smallest[0][5]_i_2 \n (.I0(wr_level_done_r2),\n .I1(oclkdelay_calib_done_r_reg),\n .I2(wr_level_done_r1),\n .I3(wrlvl_byte_redo),\n .I4(\\smallest[0][5]_i_4_n_0 ),\n .I5(\\fine_inc[0][5]_i_3_n_0 ),\n .O(\\smallest[0][5]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair331\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[0][5]_i_3 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][0][5] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][5]_i_5_n_0 ),\n .O(largest[5]));\n LUT5 #(\n .INIT(32'hFDFFF7FF)) \n \\smallest[0][5]_i_4 \n (.I0(out[4]),\n .I1(out[0]),\n .I2(out[2]),\n .I3(out[3]),\n .I4(out[1]),\n .O(\\smallest[0][5]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\smallest[0][5]_i_5 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][3][5] ),\n .I1(\\wl_dqs_tap_count_r_reg_n_0_[0][1][5] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\wl_dqs_tap_count_r_reg_n_0_[0][2][5] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\wl_dqs_tap_count_r_reg_n_0_[0][0][5] ),\n .O(\\smallest[0][5]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair324\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[1][0]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][1][0] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][0]_i_2_n_0 ),\n .O(\\smallest[1][0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair324\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[1][1]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][1][1] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][1]_i_2_n_0 ),\n .O(\\smallest[1][1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair327\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[1][2]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][1][2] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][2]_i_2_n_0 ),\n .O(\\smallest[1][2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair327\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[1][3]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][1][3] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][3]_i_2_n_0 ),\n .O(\\smallest[1][3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair328\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[1][4]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][1][4] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][4]_i_2_n_0 ),\n .O(\\smallest[1][4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0010FFFF00100000)) \n \\smallest[1][5]_i_1 \n (.I0(wr_level_done_r2),\n .I1(oclkdelay_calib_done_r_reg),\n .I2(wr_level_done_r1),\n .I3(wrlvl_byte_redo),\n .I4(\\smallest[0][5]_i_4_n_0 ),\n .I5(\\fine_inc[1][5]_i_3_n_0 ),\n .O(\\smallest[1][5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair328\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[1][5]_i_2 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][1][5] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][5]_i_5_n_0 ),\n .O(\\smallest[1][5]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair321\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[2][0]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][2][0] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][0]_i_2_n_0 ),\n .O(\\smallest[2][0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair321\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[2][1]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][2][1] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][1]_i_2_n_0 ),\n .O(\\smallest[2][1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair322\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[2][2]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][2][2] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][2]_i_2_n_0 ),\n .O(\\smallest[2][2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair322\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[2][3]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][2][3] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][3]_i_2_n_0 ),\n .O(\\smallest[2][3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair326\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[2][4]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][2][4] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][4]_i_2_n_0 ),\n .O(\\smallest[2][4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0010FFFF00100000)) \n \\smallest[2][5]_i_1 \n (.I0(wr_level_done_r2),\n .I1(oclkdelay_calib_done_r_reg),\n .I2(wr_level_done_r1),\n .I3(wrlvl_byte_redo),\n .I4(\\smallest[0][5]_i_4_n_0 ),\n .I5(\\fine_inc[2][5]_i_3_n_0 ),\n .O(\\smallest[2][5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair326\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[2][5]_i_2 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][2][5] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][5]_i_5_n_0 ),\n .O(\\smallest[2][5]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair320\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[3][0]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][3][0] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][0]_i_2_n_0 ),\n .O(\\smallest[3][0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair323\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[3][1]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][3][1] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][1]_i_2_n_0 ),\n .O(\\smallest[3][1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair325\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[3][2]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][3][2] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][2]_i_2_n_0 ),\n .O(\\smallest[3][2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair325\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[3][3]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][3][3] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][3]_i_2_n_0 ),\n .O(\\smallest[3][3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair323\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[3][4]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][3][4] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][4]_i_2_n_0 ),\n .O(\\smallest[3][4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0010FFFF00100000)) \n \\smallest[3][5]_i_1 \n (.I0(wr_level_done_r2),\n .I1(oclkdelay_calib_done_r_reg),\n .I2(wr_level_done_r1),\n .I3(wrlvl_byte_redo),\n .I4(\\smallest[0][5]_i_4_n_0 ),\n .I5(\\fine_inc[3][5]_i_5_n_0 ),\n .O(\\smallest[3][5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair320\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[3][5]_i_2 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][3][5] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][5]_i_5_n_0 ),\n .O(\\smallest[3][5]_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\smallest_reg[0][0] \n (.C(CLK),\n .CE(\\smallest[0][5]_i_2_n_0 ),\n .D(largest[0]),\n .Q(\\smallest_reg[0]__0 [0]),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\smallest_reg[0][1] \n (.C(CLK),\n .CE(\\smallest[0][5]_i_2_n_0 ),\n .D(largest[1]),\n .Q(\\smallest_reg[0]__0 [1]),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\smallest_reg[0][2] \n (.C(CLK),\n .CE(\\smallest[0][5]_i_2_n_0 ),\n .D(largest[2]),\n .Q(\\smallest_reg[0]__0 [2]),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\smallest_reg[0][3] \n (.C(CLK),\n .CE(\\smallest[0][5]_i_2_n_0 ),\n .D(largest[3]),\n .Q(\\smallest_reg[0]__0 [3]),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\smallest_reg[0][4] \n (.C(CLK),\n .CE(\\smallest[0][5]_i_2_n_0 ),\n .D(largest[4]),\n .Q(\\smallest_reg[0]__0 [4]),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\smallest_reg[0][5] \n (.C(CLK),\n .CE(\\smallest[0][5]_i_2_n_0 ),\n .D(largest[5]),\n .Q(\\smallest_reg[0]__0 [5]),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\smallest_reg[1][0] \n (.C(CLK),\n .CE(\\smallest[1][5]_i_1_n_0 ),\n .D(\\smallest[1][0]_i_1_n_0 ),\n .Q(\\smallest_reg[1]__0 [0]),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\smallest_reg[1][1] \n (.C(CLK),\n .CE(\\smallest[1][5]_i_1_n_0 ),\n .D(\\smallest[1][1]_i_1_n_0 ),\n .Q(\\smallest_reg[1]__0 [1]),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\smallest_reg[1][2] \n (.C(CLK),\n .CE(\\smallest[1][5]_i_1_n_0 ),\n .D(\\smallest[1][2]_i_1_n_0 ),\n .Q(\\smallest_reg[1]__0 [2]),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\smallest_reg[1][3] \n (.C(CLK),\n .CE(\\smallest[1][5]_i_1_n_0 ),\n .D(\\smallest[1][3]_i_1_n_0 ),\n .Q(\\smallest_reg[1]__0 [3]),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\smallest_reg[1][4] \n (.C(CLK),\n .CE(\\smallest[1][5]_i_1_n_0 ),\n .D(\\smallest[1][4]_i_1_n_0 ),\n .Q(\\smallest_reg[1]__0 [4]),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\smallest_reg[1][5] \n (.C(CLK),\n .CE(\\smallest[1][5]_i_1_n_0 ),\n .D(\\smallest[1][5]_i_2_n_0 ),\n .Q(\\smallest_reg[1]__0 [5]),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\smallest_reg[2][0] \n (.C(CLK),\n .CE(\\smallest[2][5]_i_1_n_0 ),\n .D(\\smallest[2][0]_i_1_n_0 ),\n .Q(\\smallest_reg[2]__0 [0]),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\smallest_reg[2][1] \n (.C(CLK),\n .CE(\\smallest[2][5]_i_1_n_0 ),\n .D(\\smallest[2][1]_i_1_n_0 ),\n .Q(\\smallest_reg[2]__0 [1]),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\smallest_reg[2][2] \n (.C(CLK),\n .CE(\\smallest[2][5]_i_1_n_0 ),\n .D(\\smallest[2][2]_i_1_n_0 ),\n .Q(\\smallest_reg[2]__0 [2]),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\smallest_reg[2][3] \n (.C(CLK),\n .CE(\\smallest[2][5]_i_1_n_0 ),\n .D(\\smallest[2][3]_i_1_n_0 ),\n .Q(\\smallest_reg[2]__0 [3]),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\smallest_reg[2][4] \n (.C(CLK),\n .CE(\\smallest[2][5]_i_1_n_0 ),\n .D(\\smallest[2][4]_i_1_n_0 ),\n .Q(\\smallest_reg[2]__0 [4]),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\smallest_reg[2][5] \n (.C(CLK),\n .CE(\\smallest[2][5]_i_1_n_0 ),\n .D(\\smallest[2][5]_i_2_n_0 ),\n .Q(\\smallest_reg[2]__0 [5]),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\smallest_reg[3][0] \n (.C(CLK),\n .CE(\\smallest[3][5]_i_1_n_0 ),\n .D(\\smallest[3][0]_i_1_n_0 ),\n .Q(\\smallest_reg[3]__0 [0]),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\smallest_reg[3][1] \n (.C(CLK),\n .CE(\\smallest[3][5]_i_1_n_0 ),\n .D(\\smallest[3][1]_i_1_n_0 ),\n .Q(\\smallest_reg[3]__0 [1]),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\smallest_reg[3][2] \n (.C(CLK),\n .CE(\\smallest[3][5]_i_1_n_0 ),\n .D(\\smallest[3][2]_i_1_n_0 ),\n .Q(\\smallest_reg[3]__0 [2]),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\smallest_reg[3][3] \n (.C(CLK),\n .CE(\\smallest[3][5]_i_1_n_0 ),\n .D(\\smallest[3][3]_i_1_n_0 ),\n .Q(\\smallest_reg[3]__0 [3]),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\smallest_reg[3][4] \n (.C(CLK),\n .CE(\\smallest[3][5]_i_1_n_0 ),\n .D(\\smallest[3][4]_i_1_n_0 ),\n .Q(\\smallest_reg[3]__0 [4]),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\smallest_reg[3][5] \n (.C(CLK),\n .CE(\\smallest[3][5]_i_1_n_0 ),\n .D(\\smallest[3][5]_i_2_n_0 ),\n .Q(\\smallest_reg[3]__0 [5]),\n .R(SR[1]));\n (* SOFT_HLUTNM = \"soft_lutpair349\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\stable_cnt[0]_i_1 \n (.I0(\\stable_cnt_reg[3]_0 ),\n .O(p_0_in__0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair349\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\stable_cnt[1]_i_1 \n (.I0(\\stable_cnt_reg[3]_0 ),\n .I1(\\stable_cnt_reg_n_0_[1] ),\n .O(p_0_in__0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair317\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\stable_cnt[2]_i_1 \n (.I0(\\stable_cnt_reg_n_0_[2] ),\n .I1(\\stable_cnt_reg_n_0_[1] ),\n .I2(\\stable_cnt_reg[3]_0 ),\n .O(p_0_in__0[2]));\n LUT5 #(\n .INIT(32'hFFFFFFFB)) \n \\stable_cnt[3]_i_1 \n (.I0(\\stable_cnt[3]_i_4_n_0 ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(p_1_in1_in),\n .I3(rstdiv0_sync_r1_reg_rep__22),\n .I4(\\stable_cnt[3]_i_6_n_0 ),\n .O(stable_cnt0));\n LUT6 #(\n .INIT(64'h0000000015550000)) \n \\stable_cnt[3]_i_2 \n (.I0(\\rd_data_edge_detect_r[3]_i_4_n_0 ),\n .I1(\\stable_cnt_reg_n_0_[1] ),\n .I2(\\stable_cnt_reg_n_0_[2] ),\n .I3(\\stable_cnt_reg_n_0_[3] ),\n .I4(\\rd_data_previous_r[3]_i_2_n_0 ),\n .I5(\\stable_cnt[3]_i_4_n_0 ),\n .O(stable_cnt));\n (* SOFT_HLUTNM = \"soft_lutpair317\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\stable_cnt[3]_i_3 \n (.I0(\\stable_cnt_reg_n_0_[3] ),\n .I1(\\stable_cnt_reg[3]_0 ),\n .I2(\\stable_cnt_reg_n_0_[1] ),\n .I3(\\stable_cnt_reg_n_0_[2] ),\n .O(p_0_in__0[3]));\n LUT2 #(\n .INIT(4'h6)) \n \\stable_cnt[3]_i_4 \n (.I0(stable_cnt227_in),\n .I1(\\stable_cnt[3]_i_7_n_0 ),\n .O(\\stable_cnt[3]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h00000020)) \n \\stable_cnt[3]_i_5 \n (.I0(out[1]),\n .I1(out[4]),\n .I2(out[0]),\n .I3(out[3]),\n .I4(out[2]),\n .O(p_1_in1_in));\n LUT5 #(\n .INIT(32'h00000020)) \n \\stable_cnt[3]_i_6 \n (.I0(\\wl_state_r1_reg_n_0_[0] ),\n .I1(\\wl_state_r1_reg_n_0_[4] ),\n .I2(\\wl_state_r1_reg_n_0_[2] ),\n .I3(\\wl_state_r1_reg_n_0_[3] ),\n .I4(\\wl_state_r1_reg_n_0_[1] ),\n .O(\\stable_cnt[3]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\stable_cnt[3]_i_7 \n (.I0(\\gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3] ),\n .I1(\\gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2] ),\n .I2(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I3(\\gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ),\n .I4(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I5(\\gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ),\n .O(\\stable_cnt[3]_i_7_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\stable_cnt_reg[0] \n (.C(CLK),\n .CE(stable_cnt),\n .D(p_0_in__0[0]),\n .Q(\\stable_cnt_reg[3]_0 ),\n .R(stable_cnt0));\n FDRE #(\n .INIT(1'b0)) \n \\stable_cnt_reg[1] \n (.C(CLK),\n .CE(stable_cnt),\n .D(p_0_in__0[1]),\n .Q(\\stable_cnt_reg_n_0_[1] ),\n .R(stable_cnt0));\n FDRE #(\n .INIT(1'b0)) \n \\stable_cnt_reg[2] \n (.C(CLK),\n .CE(stable_cnt),\n .D(p_0_in__0[2]),\n .Q(\\stable_cnt_reg_n_0_[2] ),\n .R(stable_cnt0));\n FDRE #(\n .INIT(1'b0)) \n \\stable_cnt_reg[3] \n (.C(CLK),\n .CE(stable_cnt),\n .D(p_0_in__0[3]),\n .Q(\\stable_cnt_reg_n_0_[3] ),\n .R(stable_cnt0));\n LUT6 #(\n .INIT(64'h55330F0055330FFF)) \n \\stg2_tap_cnt[0]_i_2 \n (.I0(wl_po_fine_cnt[18]),\n .I1(wl_po_fine_cnt[12]),\n .I2(wl_po_fine_cnt[6]),\n .I3(\\byte_r_reg[0] ),\n .I4(\\byte_r_reg[1] ),\n .I5(wl_po_fine_cnt[0]),\n .O(\\stg2_r_reg[0] ));\n LUT6 #(\n .INIT(64'h55FFDDF05500DDF0)) \n \\stg2_tap_cnt[1]_i_2 \n (.I0(\\stg2_tap_cnt[3]_i_4_n_0 ),\n .I1(wl_po_fine_cnt[7]),\n .I2(wl_po_fine_cnt[1]),\n .I3(\\byte_r_reg[0] ),\n .I4(\\byte_r_reg[1] ),\n .I5(wl_po_fine_cnt[13]),\n .O(\\stg2_target_r_reg[4] [0]));\n LUT6 #(\n .INIT(64'hFFAAF0CC00AAF0CC)) \n \\stg2_tap_cnt[2]_i_2 \n (.I0(wl_po_fine_cnt[14]),\n .I1(wl_po_fine_cnt[2]),\n .I2(wl_po_fine_cnt[8]),\n .I3(\\byte_r_reg[0] ),\n .I4(\\byte_r_reg[1] ),\n .I5(wl_po_fine_cnt[20]),\n .O(\\stg2_target_r_reg[4] [1]));\n LUT6 #(\n .INIT(64'h00AA0F22FFAA0F22)) \n \\stg2_tap_cnt[3]_i_2 \n (.I0(\\stg2_tap_cnt[3]_i_4_n_0 ),\n .I1(wl_po_fine_cnt[3]),\n .I2(wl_po_fine_cnt[9]),\n .I3(\\byte_r_reg[0] ),\n .I4(\\byte_r_reg[1] ),\n .I5(wl_po_fine_cnt[21]),\n .O(\\stg3_dec_val_reg[2] ));\n LUT4 #(\n .INIT(16'h4F7F)) \n \\stg2_tap_cnt[3]_i_4 \n (.I0(wl_po_fine_cnt[19]),\n .I1(\\byte_r_reg[0] ),\n .I2(\\byte_r_reg[1] ),\n .I3(wl_po_fine_cnt[15]),\n .O(\\stg2_tap_cnt[3]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h0511AF1105BBAFBB)) \n \\stg2_tap_cnt[4]_i_2 \n (.I0(\\byte_r_reg[0] ),\n .I1(wl_po_fine_cnt[4]),\n .I2(wl_po_fine_cnt[16]),\n .I3(\\byte_r_reg[1] ),\n .I4(wl_po_fine_cnt[22]),\n .I5(wl_po_fine_cnt[10]),\n .O(\\stg2_r_reg[4] ));\n LUT6 #(\n .INIT(64'h00550F33FF550F33)) \n \\stg2_tap_cnt[5]_i_5 \n (.I0(wl_po_fine_cnt[17]),\n .I1(wl_po_fine_cnt[5]),\n .I2(wl_po_fine_cnt[11]),\n .I3(\\byte_r_reg[0] ),\n .I4(\\byte_r_reg[1] ),\n .I5(wl_po_fine_cnt[23]),\n .O(\\stg2_r_reg[5] ));\n LUT6 #(\n .INIT(64'hFECEF2C23E0E3202)) \n \\stg2_target_r[0]_i_1 \n (.I0(wl_po_fine_cnt[0]),\n .I1(\\byte_r_reg[1] ),\n .I2(\\byte_r_reg[0] ),\n .I3(wl_po_fine_cnt[6]),\n .I4(wl_po_fine_cnt[12]),\n .I5(wl_po_fine_cnt[18]),\n .O(D[0]));\n LUT1 #(\n .INIT(2'h1)) \n \\stg2_target_r[4]_i_2 \n (.I0(\\stg2_r_reg[4] ),\n .O(\\oclk_calib.u_ddr_phy_oclkdelay_cal/wl_po_fine_cnt_sel_0__0 [4]));\n LUT1 #(\n .INIT(2'h1)) \n \\stg2_target_r[4]_i_3 \n (.I0(\\stg3_dec_val_reg[2] ),\n .O(\\oclk_calib.u_ddr_phy_oclkdelay_cal/wl_po_fine_cnt_sel_0__0 [3]));\n LUT2 #(\n .INIT(4'h9)) \n \\stg2_target_r[4]_i_4 \n (.I0(\\stg2_r_reg[4] ),\n .I1(O[2]),\n .O(\\stg2_target_r[4]_i_4_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\stg2_target_r[4]_i_5 \n (.I0(\\stg3_dec_val_reg[2] ),\n .I1(O[1]),\n .O(\\stg2_target_r[4]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hBF8FBC8CB383B080)) \n \\stg2_target_r[8]_i_2 \n (.I0(wl_po_fine_cnt[23]),\n .I1(\\byte_r_reg[1] ),\n .I2(\\byte_r_reg[0] ),\n .I3(wl_po_fine_cnt[11]),\n .I4(wl_po_fine_cnt[5]),\n .I5(wl_po_fine_cnt[17]),\n .O(\\oclk_calib.u_ddr_phy_oclkdelay_cal/wl_po_fine_cnt_sel_0__0 [5]));\n LUT2 #(\n .INIT(4'h9)) \n \\stg2_target_r[8]_i_6 \n (.I0(\\stg2_r_reg[5] ),\n .I1(O[3]),\n .O(\\stg2_target_r[8]_i_6_n_0 ));\n CARRY4 \\stg2_target_r_reg[4]_i_1 \n (.CI(1'b0),\n .CO({\\stg2_target_r_reg[4]_i_1_n_0 ,\\stg2_target_r_reg[4]_i_1_n_1 ,\\stg2_target_r_reg[4]_i_1_n_2 ,\\stg2_target_r_reg[4]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({\\oclk_calib.u_ddr_phy_oclkdelay_cal/wl_po_fine_cnt_sel_0__0 [4:3],\\stg2_target_r_reg[4] }),\n .O({D[3:1],\\NLW_stg2_target_r_reg[4]_i_1_O_UNCONNECTED [0]}),\n .S({\\stg2_target_r[4]_i_4_n_0 ,\\stg2_target_r[4]_i_5_n_0 ,\\u_ocd_po_cntlr/stg2_target_r[4]_i_6_n_0 ,S}));\n CARRY4 \\stg2_target_r_reg[8]_i_1 \n (.CI(\\stg2_target_r_reg[4]_i_1_n_0 ),\n .CO({\\NLW_stg2_target_r_reg[8]_i_1_CO_UNCONNECTED [3],\\stg2_target_r_reg[8]_i_1_n_1 ,\\stg2_target_r_reg[8]_i_1_n_2 ,\\stg2_target_r_reg[8]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,\\oclk_calib.u_ddr_phy_oclkdelay_cal/wl_po_fine_cnt_sel_0__0 [5]}),\n .O(D[7:4]),\n .S({\\stg3_r_reg[5] ,\\stg2_target_r[8]_i_6_n_0 }));\n (* SOFT_HLUTNM = \"soft_lutpair316\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\stg3_dec_val[0]_i_1 \n (.I0(\\stg2_target_r_reg[4] [0]),\n .I1(Q[0]),\n .O(\\stg3_dec_val_reg[2]_0 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair316\" *) \n LUT4 #(\n .INIT(16'hE11E)) \n \\stg3_dec_val[1]_i_1 \n (.I0(\\stg2_target_r_reg[4] [0]),\n .I1(Q[0]),\n .I2(\\stg2_target_r_reg[4] [1]),\n .I3(Q[1]),\n .O(\\stg3_dec_val_reg[2]_0 [1]));\n LUT6 #(\n .INIT(64'h1117EEE8EEE81117)) \n \\stg3_dec_val[2]_i_1 \n (.I0(\\stg2_target_r_reg[4] [1]),\n .I1(Q[1]),\n .I2(\\stg2_target_r_reg[4] [0]),\n .I3(Q[0]),\n .I4(\\stg3_dec_val_reg[2] ),\n .I5(Q[2]),\n .O(\\stg3_dec_val_reg[2]_0 [2]));\n LUT2 #(\n .INIT(4'h6)) \n \\u_ocd_po_cntlr/stg2_target_r[4]_i_6 \n (.I0(\\stg2_target_r_reg[4] [1]),\n .I1(O[0]),\n .O(\\u_ocd_po_cntlr/stg2_target_r[4]_i_6_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\wait_cnt[0]_i_1 \n (.I0(wait_cnt_reg__0[0]),\n .O(wait_cnt0__0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair348\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\wait_cnt[1]_i_1 \n (.I0(wait_cnt_reg__0[0]),\n .I1(wait_cnt_reg__0[1]),\n .O(\\wait_cnt[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair348\" *) \n LUT3 #(\n .INIT(8'hA9)) \n \\wait_cnt[2]_i_1 \n (.I0(wait_cnt_reg__0[2]),\n .I1(wait_cnt_reg__0[1]),\n .I2(wait_cnt_reg__0[0]),\n .O(wait_cnt0__0[2]));\n LUT5 #(\n .INIT(32'hAAAAAAA8)) \n \\wait_cnt[3]_i_2 \n (.I0(phy_ctl_ready_r6_reg_n_0),\n .I1(wait_cnt_reg__0[3]),\n .I2(wait_cnt_reg__0[1]),\n .I3(wait_cnt_reg__0[0]),\n .I4(wait_cnt_reg__0[2]),\n .O(wait_cnt0));\n (* SOFT_HLUTNM = \"soft_lutpair313\" *) \n LUT4 #(\n .INIT(16'hAAA9)) \n \\wait_cnt[3]_i_3 \n (.I0(wait_cnt_reg__0[3]),\n .I1(wait_cnt_reg__0[2]),\n .I2(wait_cnt_reg__0[0]),\n .I3(wait_cnt_reg__0[1]),\n .O(wait_cnt0__0[3]));\n FDRE #(\n .INIT(1'b0)) \n \\wait_cnt_reg[0] \n (.C(CLK),\n .CE(wait_cnt0),\n .D(wait_cnt0__0[0]),\n .Q(wait_cnt_reg__0[0]),\n .R(po_cnt_dec_reg_1));\n FDRE #(\n .INIT(1'b0)) \n \\wait_cnt_reg[1] \n (.C(CLK),\n .CE(wait_cnt0),\n .D(\\wait_cnt[1]_i_1_n_0 ),\n .Q(wait_cnt_reg__0[1]),\n .R(po_cnt_dec_reg_1));\n FDRE #(\n .INIT(1'b0)) \n \\wait_cnt_reg[2] \n (.C(CLK),\n .CE(wait_cnt0),\n .D(wait_cnt0__0[2]),\n .Q(wait_cnt_reg__0[2]),\n .R(po_cnt_dec_reg_1));\n FDSE #(\n .INIT(1'b1)) \n \\wait_cnt_reg[3] \n (.C(CLK),\n .CE(wait_cnt0),\n .D(wait_cnt0__0[3]),\n .Q(wait_cnt_reg__0[3]),\n .S(po_cnt_dec_reg_1));\n LUT6 #(\n .INIT(64'hF0FFF000AACCAACC)) \n \\wl_corse_cnt[0][0][0]_i_1 \n (.I0(\\corse_cnt_reg_n_0_[2][0] ),\n .I1(\\corse_cnt_reg_n_0_[0][0] ),\n .I2(\\corse_cnt_reg_n_0_[3][0] ),\n .I3(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I4(\\corse_cnt_reg_n_0_[1][0] ),\n .I5(\\dqs_count_r_reg[0]_rep_n_0 ),\n .O(\\wl_corse_cnt[0][0][0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\wl_corse_cnt[0][0][1]_i_1 \n (.I0(\\corse_cnt_reg_n_0_[3][1] ),\n .I1(\\corse_cnt_reg_n_0_[1][1] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\corse_cnt_reg_n_0_[2][1] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\corse_cnt_reg_n_0_[0][1] ),\n .O(\\wl_corse_cnt[0][0][1]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h0100)) \n \\wl_corse_cnt[0][0][2]_i_1 \n (.I0(dqs_count_r[0]),\n .I1(dqs_count_r[1]),\n .I2(dqs_count_r[2]),\n .I3(\\wl_corse_cnt[0][0][2]_i_3_n_0 ),\n .O(wl_corse_cnt));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\wl_corse_cnt[0][0][2]_i_2 \n (.I0(\\corse_cnt_reg_n_0_[3][2] ),\n .I1(\\corse_cnt_reg_n_0_[1][2] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\corse_cnt_reg_n_0_[2][2] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\corse_cnt_reg_n_0_[0][2] ),\n .O(\\wl_corse_cnt[0][0][2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0200088000800000)) \n \\wl_corse_cnt[0][0][2]_i_3 \n (.I0(\\wl_corse_cnt[0][0][2]_i_4_n_0 ),\n .I1(out[1]),\n .I2(out[2]),\n .I3(out[4]),\n .I4(out[0]),\n .I5(out[3]),\n .O(\\wl_corse_cnt[0][0][2]_i_3_n_0 ));\n LUT2 #(\n .INIT(4'h1)) \n \\wl_corse_cnt[0][0][2]_i_4 \n (.I0(\\rank_cnt_r_reg[0]_0 ),\n .I1(\\rank_cnt_r_reg[0]_1 ),\n .O(\\wl_corse_cnt[0][0][2]_i_4_n_0 ));\n LUT4 #(\n .INIT(16'h0020)) \n \\wl_corse_cnt[0][1][2]_i_1 \n (.I0(\\wl_corse_cnt[0][0][2]_i_3_n_0 ),\n .I1(dqs_count_r[1]),\n .I2(dqs_count_r[0]),\n .I3(dqs_count_r[2]),\n .O(\\wl_corse_cnt[0][1][2]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h0020)) \n \\wl_corse_cnt[0][2][2]_i_1 \n (.I0(\\wl_corse_cnt[0][0][2]_i_3_n_0 ),\n .I1(dqs_count_r[0]),\n .I2(dqs_count_r[1]),\n .I3(dqs_count_r[2]),\n .O(\\wl_corse_cnt[0][2][2]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h0080)) \n \\wl_corse_cnt[0][3][2]_i_1 \n (.I0(\\wl_corse_cnt[0][0][2]_i_3_n_0 ),\n .I1(dqs_count_r[0]),\n .I2(dqs_count_r[1]),\n .I3(dqs_count_r[2]),\n .O(\\wl_corse_cnt[0][3][2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\wl_corse_cnt_reg[0][0][0] \n (.C(CLK),\n .CE(wl_corse_cnt),\n .D(\\wl_corse_cnt[0][0][0]_i_1_n_0 ),\n .Q(\\wl_corse_cnt_reg[0][0]__0 [0]),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_corse_cnt_reg[0][0][1] \n (.C(CLK),\n .CE(wl_corse_cnt),\n .D(\\wl_corse_cnt[0][0][1]_i_1_n_0 ),\n .Q(\\wl_corse_cnt_reg[0][0]__0 [1]),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_corse_cnt_reg[0][0][2] \n (.C(CLK),\n .CE(wl_corse_cnt),\n .D(\\wl_corse_cnt[0][0][2]_i_2_n_0 ),\n .Q(\\wl_corse_cnt_reg[0][0]__0 [2]),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_corse_cnt_reg[0][1][0] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][1][2]_i_1_n_0 ),\n .D(\\wl_corse_cnt[0][0][0]_i_1_n_0 ),\n .Q(\\wl_corse_cnt_reg[0][1]__0 [0]),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_corse_cnt_reg[0][1][1] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][1][2]_i_1_n_0 ),\n .D(\\wl_corse_cnt[0][0][1]_i_1_n_0 ),\n .Q(\\wl_corse_cnt_reg[0][1]__0 [1]),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_corse_cnt_reg[0][1][2] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][1][2]_i_1_n_0 ),\n .D(\\wl_corse_cnt[0][0][2]_i_2_n_0 ),\n .Q(\\wl_corse_cnt_reg[0][1]__0 [2]),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_corse_cnt_reg[0][2][0] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][2][2]_i_1_n_0 ),\n .D(\\wl_corse_cnt[0][0][0]_i_1_n_0 ),\n .Q(\\wl_corse_cnt_reg[0][2]__0 [0]),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_corse_cnt_reg[0][2][1] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][2][2]_i_1_n_0 ),\n .D(\\wl_corse_cnt[0][0][1]_i_1_n_0 ),\n .Q(\\wl_corse_cnt_reg[0][2]__0 [1]),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_corse_cnt_reg[0][2][2] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][2][2]_i_1_n_0 ),\n .D(\\wl_corse_cnt[0][0][2]_i_2_n_0 ),\n .Q(\\wl_corse_cnt_reg[0][2]__0 [2]),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_corse_cnt_reg[0][3][0] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][3][2]_i_1_n_0 ),\n .D(\\wl_corse_cnt[0][0][0]_i_1_n_0 ),\n .Q(\\wl_corse_cnt_reg[0][3]__0 [0]),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_corse_cnt_reg[0][3][1] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][3][2]_i_1_n_0 ),\n .D(\\wl_corse_cnt[0][0][1]_i_1_n_0 ),\n .Q(\\wl_corse_cnt_reg[0][3]__0 [1]),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_corse_cnt_reg[0][3][2] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][3][2]_i_1_n_0 ),\n .D(\\wl_corse_cnt[0][0][2]_i_2_n_0 ),\n .Q(\\wl_corse_cnt_reg[0][3]__0 [2]),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_dqs_tap_count_r_reg[0][0][0] \n (.C(CLK),\n .CE(wl_corse_cnt),\n .D(\\wl_tap_count_r_reg_n_0_[0] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][0][0] ),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_dqs_tap_count_r_reg[0][0][1] \n (.C(CLK),\n .CE(wl_corse_cnt),\n .D(\\wl_tap_count_r_reg_n_0_[1] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][0][1] ),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_dqs_tap_count_r_reg[0][0][2] \n (.C(CLK),\n .CE(wl_corse_cnt),\n .D(\\wl_tap_count_r_reg_n_0_[2] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][0][2] ),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_dqs_tap_count_r_reg[0][0][3] \n (.C(CLK),\n .CE(wl_corse_cnt),\n .D(\\wl_tap_count_r_reg_n_0_[3] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][0][3] ),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_dqs_tap_count_r_reg[0][0][4] \n (.C(CLK),\n .CE(wl_corse_cnt),\n .D(\\wl_tap_count_r_reg_n_0_[4] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][0][4] ),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_dqs_tap_count_r_reg[0][0][5] \n (.C(CLK),\n .CE(wl_corse_cnt),\n .D(\\wl_tap_count_r_reg_n_0_[5] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][0][5] ),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_dqs_tap_count_r_reg[0][1][0] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][1][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[0] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][1][0] ),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_dqs_tap_count_r_reg[0][1][1] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][1][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[1] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][1][1] ),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_dqs_tap_count_r_reg[0][1][2] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][1][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[2] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][1][2] ),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_dqs_tap_count_r_reg[0][1][3] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][1][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[3] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][1][3] ),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_dqs_tap_count_r_reg[0][1][4] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][1][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[4] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][1][4] ),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_dqs_tap_count_r_reg[0][1][5] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][1][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[5] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][1][5] ),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_dqs_tap_count_r_reg[0][2][0] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][2][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[0] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][2][0] ),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_dqs_tap_count_r_reg[0][2][1] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][2][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[1] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][2][1] ),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_dqs_tap_count_r_reg[0][2][2] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][2][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[2] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][2][2] ),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_dqs_tap_count_r_reg[0][2][3] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][2][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[3] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][2][3] ),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_dqs_tap_count_r_reg[0][2][4] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][2][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[4] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][2][4] ),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_dqs_tap_count_r_reg[0][2][5] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][2][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[5] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][2][5] ),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_dqs_tap_count_r_reg[0][3][0] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][3][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[0] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][3][0] ),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_dqs_tap_count_r_reg[0][3][1] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][3][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[1] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][3][1] ),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_dqs_tap_count_r_reg[0][3][2] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][3][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[2] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][3][2] ),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_dqs_tap_count_r_reg[0][3][3] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][3][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[3] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][3][3] ),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_dqs_tap_count_r_reg[0][3][4] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][3][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[4] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][3][4] ),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_dqs_tap_count_r_reg[0][3][5] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][3][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[5] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][3][5] ),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n wl_edge_detect_valid_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_wl_state_r_reg[2]_0 ),\n .Q(\\FSM_sequential_wl_state_r_reg[0]_0 ),\n .R(SR[1]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_po_fine_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[0]__0 [0]),\n .Q(wl_po_fine_cnt[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wl_po_fine_cnt_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[1]__0 [4]),\n .Q(wl_po_fine_cnt[10]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wl_po_fine_cnt_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[1]__0 [5]),\n .Q(wl_po_fine_cnt[11]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wl_po_fine_cnt_reg[12] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[2]__0 [0]),\n .Q(wl_po_fine_cnt[12]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wl_po_fine_cnt_reg[13] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[2]__0 [1]),\n .Q(wl_po_fine_cnt[13]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wl_po_fine_cnt_reg[14] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[2]__0 [2]),\n .Q(wl_po_fine_cnt[14]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wl_po_fine_cnt_reg[15] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[2]__0 [3]),\n .Q(wl_po_fine_cnt[15]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wl_po_fine_cnt_reg[16] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[2]__0 [4]),\n .Q(wl_po_fine_cnt[16]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wl_po_fine_cnt_reg[17] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[2]__0 [5]),\n .Q(wl_po_fine_cnt[17]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wl_po_fine_cnt_reg[18] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[3]__0 [0]),\n .Q(wl_po_fine_cnt[18]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wl_po_fine_cnt_reg[19] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[3]__0 [1]),\n .Q(wl_po_fine_cnt[19]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wl_po_fine_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[0]__0 [1]),\n .Q(wl_po_fine_cnt[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wl_po_fine_cnt_reg[20] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[3]__0 [2]),\n .Q(wl_po_fine_cnt[20]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wl_po_fine_cnt_reg[21] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[3]__0 [3]),\n .Q(wl_po_fine_cnt[21]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wl_po_fine_cnt_reg[22] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[3]__0 [4]),\n .Q(wl_po_fine_cnt[22]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wl_po_fine_cnt_reg[23] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[3]__0 [5]),\n .Q(wl_po_fine_cnt[23]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wl_po_fine_cnt_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[0]__0 [2]),\n .Q(wl_po_fine_cnt[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wl_po_fine_cnt_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[0]__0 [3]),\n .Q(wl_po_fine_cnt[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wl_po_fine_cnt_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[0]__0 [4]),\n .Q(wl_po_fine_cnt[4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wl_po_fine_cnt_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[0]__0 [5]),\n .Q(wl_po_fine_cnt[5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wl_po_fine_cnt_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[1]__0 [0]),\n .Q(wl_po_fine_cnt[6]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wl_po_fine_cnt_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[1]__0 [1]),\n .Q(wl_po_fine_cnt[7]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wl_po_fine_cnt_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[1]__0 [2]),\n .Q(wl_po_fine_cnt[8]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wl_po_fine_cnt_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[1]__0 [3]),\n .Q(wl_po_fine_cnt[9]),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h1B15D560)) \n \\wl_state_r1[0]_i_1 \n (.I0(out[1]),\n .I1(out[2]),\n .I2(out[4]),\n .I3(out[0]),\n .I4(out[3]),\n .O(\\wl_state_r1[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h293CEA22)) \n \\wl_state_r1[1]_i_1 \n (.I0(out[1]),\n .I1(out[4]),\n .I2(out[3]),\n .I3(out[0]),\n .I4(out[2]),\n .O(\\wl_state_r1[1]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h0505C478)) \n \\wl_state_r1[2]_i_1 \n (.I0(out[2]),\n .I1(out[1]),\n .I2(out[3]),\n .I3(out[0]),\n .I4(out[4]),\n .O(\\wl_state_r1[2]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h67425208)) \n \\wl_state_r1[3]_i_1 \n (.I0(out[4]),\n .I1(out[2]),\n .I2(out[1]),\n .I3(out[0]),\n .I4(out[3]),\n .O(\\wl_state_r1[3]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h55512B08)) \n \\wl_state_r1[4]_i_1 \n (.I0(out[3]),\n .I1(out[0]),\n .I2(out[1]),\n .I3(out[2]),\n .I4(out[4]),\n .O(\\wl_state_r1[4]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\wl_state_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_state_r1[0]_i_1_n_0 ),\n .Q(\\wl_state_r1_reg_n_0_[0] ),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_state_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_state_r1[1]_i_1_n_0 ),\n .Q(\\wl_state_r1_reg_n_0_[1] ),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_state_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_state_r1[2]_i_1_n_0 ),\n .Q(\\wl_state_r1_reg_n_0_[2] ),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_state_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_state_r1[3]_i_1_n_0 ),\n .Q(\\wl_state_r1_reg_n_0_[3] ),\n .R(SR[0]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_state_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_state_r1[4]_i_1_n_0 ),\n .Q(\\wl_state_r1_reg_n_0_[4] ),\n .R(SR[0]));\n LUT4 #(\n .INIT(16'hFF10)) \n \\wl_tap_count_r[0]_i_1 \n (.I0(out[3]),\n .I1(out[1]),\n .I2(\\wl_tap_count_r[0]_i_2_n_0 ),\n .I3(\\wl_tap_count_r[0]_i_3_n_0 ),\n .O(wl_tap_count_r[0]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\wl_tap_count_r[0]_i_2 \n (.I0(\\smallest_reg[3]__0 [0]),\n .I1(\\smallest_reg[1]__0 [0]),\n .I2(\\po_stg2_wrcal_cnt_reg[2] [0]),\n .I3(\\smallest_reg[2]__0 [0]),\n .I4(\\po_stg2_wrcal_cnt_reg[2] [1]),\n .I5(\\smallest_reg[0]__0 [0]),\n .O(\\wl_tap_count_r[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0003000005050000)) \n \\wl_tap_count_r[0]_i_3 \n (.I0(out[0]),\n .I1(out[4]),\n .I2(\\wl_tap_count_r_reg_n_0_[0] ),\n .I3(wr_level_done_r5),\n .I4(out[1]),\n .I5(out[3]),\n .O(\\wl_tap_count_r[0]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hCCCFCCEECCCCCCEE)) \n \\wl_tap_count_r[1]_i_1 \n (.I0(\\wl_tap_count_r[1]_i_2_n_0 ),\n .I1(\\wl_tap_count_r[1]_i_3_n_0 ),\n .I2(out[0]),\n .I3(out[3]),\n .I4(out[1]),\n .I5(\\wl_tap_count_r[1]_i_4_n_0 ),\n .O(wl_tap_count_r[1]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\wl_tap_count_r[1]_i_2 \n (.I0(\\smallest_reg[3]__0 [1]),\n .I1(\\smallest_reg[1]__0 [1]),\n .I2(\\po_stg2_wrcal_cnt_reg[2] [0]),\n .I3(\\smallest_reg[2]__0 [1]),\n .I4(\\po_stg2_wrcal_cnt_reg[2] [1]),\n .I5(\\smallest_reg[0]__0 [1]),\n .O(\\wl_tap_count_r[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000880)) \n \\wl_tap_count_r[1]_i_3 \n (.I0(out[3]),\n .I1(out[1]),\n .I2(\\wl_tap_count_r_reg_n_0_[0] ),\n .I3(\\wl_tap_count_r_reg_n_0_[1] ),\n .I4(wr_level_done_r5),\n .I5(out[4]),\n .O(\\wl_tap_count_r[1]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair340\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\wl_tap_count_r[1]_i_4 \n (.I0(\\wl_tap_count_r_reg_n_0_[1] ),\n .I1(\\wl_tap_count_r_reg_n_0_[0] ),\n .O(\\wl_tap_count_r[1]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h02C232F202C202C2)) \n \\wl_tap_count_r[2]_i_1 \n (.I0(\\wl_tap_count_r[2]_i_2_n_0 ),\n .I1(out[3]),\n .I2(out[1]),\n .I3(\\wl_tap_count_r[2]_i_3_n_0 ),\n .I4(out[0]),\n .I5(\\wl_tap_count_r[2]_i_4_n_0 ),\n .O(wl_tap_count_r[2]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\wl_tap_count_r[2]_i_2 \n (.I0(\\smallest_reg[3]__0 [2]),\n .I1(\\smallest_reg[1]__0 [2]),\n .I2(\\po_stg2_wrcal_cnt_reg[2] [0]),\n .I3(\\smallest_reg[2]__0 [2]),\n .I4(\\po_stg2_wrcal_cnt_reg[2] [1]),\n .I5(\\smallest_reg[0]__0 [2]),\n .O(\\wl_tap_count_r[2]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFEEFEFEF)) \n \\wl_tap_count_r[2]_i_3 \n (.I0(out[4]),\n .I1(wr_level_done_r5),\n .I2(\\wl_tap_count_r_reg_n_0_[2] ),\n .I3(\\wl_tap_count_r_reg_n_0_[0] ),\n .I4(\\wl_tap_count_r_reg_n_0_[1] ),\n .O(\\wl_tap_count_r[2]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair340\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\wl_tap_count_r[2]_i_4 \n (.I0(\\wl_tap_count_r_reg_n_0_[2] ),\n .I1(\\wl_tap_count_r_reg_n_0_[0] ),\n .I2(\\wl_tap_count_r_reg_n_0_[1] ),\n .O(\\wl_tap_count_r[2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h02C202C202C232F2)) \n \\wl_tap_count_r[3]_i_1 \n (.I0(\\wl_tap_count_r[3]_i_2_n_0 ),\n .I1(out[3]),\n .I2(out[1]),\n .I3(\\wl_tap_count_r[3]_i_3_n_0 ),\n .I4(out[0]),\n .I5(\\wl_tap_count_r[3]_i_4_n_0 ),\n .O(wl_tap_count_r[3]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\wl_tap_count_r[3]_i_2 \n (.I0(\\smallest_reg[3]__0 [3]),\n .I1(\\smallest_reg[1]__0 [3]),\n .I2(\\po_stg2_wrcal_cnt_reg[2] [0]),\n .I3(\\smallest_reg[2]__0 [3]),\n .I4(\\po_stg2_wrcal_cnt_reg[2] [1]),\n .I5(\\smallest_reg[0]__0 [3]),\n .O(\\wl_tap_count_r[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFEBBBBBBB)) \n \\wl_tap_count_r[3]_i_3 \n (.I0(out[4]),\n .I1(\\wl_tap_count_r_reg_n_0_[3] ),\n .I2(\\wl_tap_count_r_reg_n_0_[2] ),\n .I3(\\wl_tap_count_r_reg_n_0_[1] ),\n .I4(\\wl_tap_count_r_reg_n_0_[0] ),\n .I5(wr_level_done_r5),\n .O(\\wl_tap_count_r[3]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair314\" *) \n LUT4 #(\n .INIT(16'h9555)) \n \\wl_tap_count_r[3]_i_4 \n (.I0(\\wl_tap_count_r_reg_n_0_[3] ),\n .I1(\\wl_tap_count_r_reg_n_0_[2] ),\n .I2(\\wl_tap_count_r_reg_n_0_[1] ),\n .I3(\\wl_tap_count_r_reg_n_0_[0] ),\n .O(\\wl_tap_count_r[3]_i_4_n_0 ));\n LUT4 #(\n .INIT(16'hFF10)) \n \\wl_tap_count_r[4]_i_1 \n (.I0(out[3]),\n .I1(out[1]),\n .I2(\\wl_tap_count_r[4]_i_2_n_0 ),\n .I3(\\wl_tap_count_r[4]_i_3_n_0 ),\n .O(wl_tap_count_r[4]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\wl_tap_count_r[4]_i_2 \n (.I0(\\smallest_reg[3]__0 [4]),\n .I1(\\smallest_reg[1]__0 [4]),\n .I2(\\po_stg2_wrcal_cnt_reg[2] [0]),\n .I3(\\smallest_reg[2]__0 [4]),\n .I4(\\po_stg2_wrcal_cnt_reg[2] [1]),\n .I5(\\smallest_reg[0]__0 [4]),\n .O(\\wl_tap_count_r[4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0003000005050000)) \n \\wl_tap_count_r[4]_i_3 \n (.I0(out[0]),\n .I1(out[4]),\n .I2(\\wl_tap_count_r[4]_i_4_n_0 ),\n .I3(wr_level_done_r5),\n .I4(out[1]),\n .I5(out[3]),\n .O(\\wl_tap_count_r[4]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair314\" *) \n LUT5 #(\n .INIT(32'h95555555)) \n \\wl_tap_count_r[4]_i_4 \n (.I0(\\wl_tap_count_r_reg_n_0_[4] ),\n .I1(\\wl_tap_count_r_reg_n_0_[0] ),\n .I2(\\wl_tap_count_r_reg_n_0_[1] ),\n .I3(\\wl_tap_count_r_reg_n_0_[2] ),\n .I4(\\wl_tap_count_r_reg_n_0_[3] ),\n .O(\\wl_tap_count_r[4]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h4400000044551110)) \n \\wl_tap_count_r[5]_i_1 \n (.I0(out[2]),\n .I1(out[0]),\n .I2(done_dqs_dec239_out),\n .I3(out[3]),\n .I4(out[1]),\n .I5(out[4]),\n .O(\\wl_tap_count_r[5]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hFF10)) \n \\wl_tap_count_r[5]_i_2 \n (.I0(out[3]),\n .I1(out[1]),\n .I2(\\wl_tap_count_r[5]_i_4_n_0 ),\n .I3(\\wl_tap_count_r[5]_i_5_n_0 ),\n .O(wl_tap_count_r[5]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\wl_tap_count_r[5]_i_4 \n (.I0(\\smallest_reg[3]__0 [5]),\n .I1(\\smallest_reg[1]__0 [5]),\n .I2(\\po_stg2_wrcal_cnt_reg[2] [0]),\n .I3(\\smallest_reg[2]__0 [5]),\n .I4(\\po_stg2_wrcal_cnt_reg[2] [1]),\n .I5(\\smallest_reg[0]__0 [5]),\n .O(\\wl_tap_count_r[5]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h0300000055000000)) \n \\wl_tap_count_r[5]_i_5 \n (.I0(out[0]),\n .I1(out[4]),\n .I2(wr_level_done_r5),\n .I3(\\wl_tap_count_r[5]_i_6_n_0 ),\n .I4(out[1]),\n .I5(out[3]),\n .O(\\wl_tap_count_r[5]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n \\wl_tap_count_r[5]_i_6 \n (.I0(\\wl_tap_count_r_reg_n_0_[5] ),\n .I1(\\wl_tap_count_r_reg_n_0_[4] ),\n .I2(\\wl_tap_count_r_reg_n_0_[3] ),\n .I3(\\wl_tap_count_r_reg_n_0_[2] ),\n .I4(\\wl_tap_count_r_reg_n_0_[1] ),\n .I5(\\wl_tap_count_r_reg_n_0_[0] ),\n .O(\\wl_tap_count_r[5]_i_6_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\wl_tap_count_r_reg[0] \n (.C(CLK),\n .CE(\\wl_tap_count_r[5]_i_1_n_0 ),\n .D(wl_tap_count_r[0]),\n .Q(\\wl_tap_count_r_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_tap_count_r_reg[1] \n (.C(CLK),\n .CE(\\wl_tap_count_r[5]_i_1_n_0 ),\n .D(wl_tap_count_r[1]),\n .Q(\\wl_tap_count_r_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_tap_count_r_reg[2] \n (.C(CLK),\n .CE(\\wl_tap_count_r[5]_i_1_n_0 ),\n .D(wl_tap_count_r[2]),\n .Q(\\wl_tap_count_r_reg_n_0_[2] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_tap_count_r_reg[3] \n (.C(CLK),\n .CE(\\wl_tap_count_r[5]_i_1_n_0 ),\n .D(wl_tap_count_r[3]),\n .Q(\\wl_tap_count_r_reg_n_0_[3] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_tap_count_r_reg[4] \n (.C(CLK),\n .CE(\\wl_tap_count_r[5]_i_1_n_0 ),\n .D(wl_tap_count_r[4]),\n .Q(\\wl_tap_count_r_reg_n_0_[4] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n \\wl_tap_count_r_reg[5] \n (.C(CLK),\n .CE(\\wl_tap_count_r[5]_i_1_n_0 ),\n .D(wl_tap_count_r[5]),\n .Q(\\wl_tap_count_r_reg_n_0_[5] ),\n .R(rstdiv0_sync_r1_reg_rep__17[1]));\n FDRE #(\n .INIT(1'b0)) \n wr_level_done_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wr_level_done_r1_reg_0),\n .Q(wr_level_done_r1),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n wr_level_done_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wr_level_done_r1),\n .Q(wr_level_done_r2),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n wr_level_done_r3_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wr_level_done_r2),\n .Q(wr_level_done_r3),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n wr_level_done_r4_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wr_level_done_r3),\n .Q(wr_level_done_r4),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n wr_level_done_r5_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wr_level_done_r4),\n .Q(wr_level_done_r5),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hF5FFFFFFFFFFFFBB)) \n wr_level_done_r_i_2\n (.I0(out[4]),\n .I1(wr_level_done0),\n .I2(p_0_in),\n .I3(out[3]),\n .I4(out[1]),\n .I5(out[0]),\n .O(wr_level_done_r_reg_0));\n FDRE #(\n .INIT(1'b0)) \n wr_level_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_wl_state_r_reg[0]_1 ),\n .Q(wr_level_done_r1_reg_0),\n .R(SR[1]));\n (* syn_maxfan = \"2\" *) \n FDRE #(\n .INIT(1'b0)) \n wr_level_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\single_rank.done_dqs_dec_reg_0 ),\n .Q(wrlvl_done_r_reg),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n wr_level_start_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wr_lvl_start_reg),\n .Q(wr_level_start_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000AEAA00AA)) \n wrlvl_byte_done_i_1\n (.I0(wrlvl_byte_done),\n .I1(wr_level_done_r3),\n .I2(wr_level_done_r4),\n .I3(wrlvl_byte_redo),\n .I4(wrlvl_byte_redo_r),\n .I5(rstdiv0_sync_r1_reg_rep__22),\n .O(wrlvl_byte_done_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n wrlvl_byte_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrlvl_byte_done_i_1_n_0),\n .Q(wrlvl_byte_done),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n wrlvl_byte_redo_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrlvl_byte_redo),\n .Q(wrlvl_byte_redo_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n wrlvl_final_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrlvl_final_mux),\n .Q(wrlvl_final_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0000400000050005)) \n wrlvl_rank_done_r_i_2\n (.I0(out[2]),\n .I1(out[0]),\n .I2(out[1]),\n .I3(out[3]),\n .I4(p_0_in),\n .I5(out[4]),\n .O(wrlvl_rank_done_r_reg_0));\n FDRE #(\n .INIT(1'b0)) \n wrlvl_rank_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_wl_state_r_reg[2]_1 ),\n .Q(wrlvl_rank_done),\n .R(SR[0]));\n LUT4 #(\n .INIT(16'h0F40)) \n \\wrlvl_redo_corse_inc[0]_i_1 \n (.I0(out[4]),\n .I1(out[2]),\n .I2(\\wrlvl_redo_corse_inc[2]_i_4_n_0 ),\n .I3(wrlvl_redo_corse_inc__0[0]),\n .O(\\wrlvl_redo_corse_inc[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h45FF1500)) \n \\wrlvl_redo_corse_inc[1]_i_1 \n (.I0(out[4]),\n .I1(wrlvl_redo_corse_inc__0[0]),\n .I2(out[2]),\n .I3(\\wrlvl_redo_corse_inc[2]_i_4_n_0 ),\n .I4(wrlvl_redo_corse_inc__0[1]),\n .O(\\wrlvl_redo_corse_inc[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0074FFFF00B80000)) \n \\wrlvl_redo_corse_inc[2]_i_1 \n (.I0(\\wrlvl_redo_corse_inc[2]_i_2_n_0 ),\n .I1(out[2]),\n .I2(\\wrlvl_redo_corse_inc[2]_i_3_n_0 ),\n .I3(out[4]),\n .I4(\\wrlvl_redo_corse_inc[2]_i_4_n_0 ),\n .I5(wrlvl_redo_corse_inc__0[2]),\n .O(\\wrlvl_redo_corse_inc[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair333\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\wrlvl_redo_corse_inc[2]_i_2 \n (.I0(wrlvl_redo_corse_inc__0[0]),\n .I1(wrlvl_redo_corse_inc__0[1]),\n .O(\\wrlvl_redo_corse_inc[2]_i_2_n_0 ));\n LUT3 #(\n .INIT(8'hD5)) \n \\wrlvl_redo_corse_inc[2]_i_3 \n (.I0(early1_data_reg_0),\n .I1(\\wrlvl_redo_corse_inc_reg[2]_0 [0]),\n .I2(\\wrlvl_redo_corse_inc_reg[2]_0 [1]),\n .O(\\wrlvl_redo_corse_inc[2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h00000020A0A00020)) \n \\wrlvl_redo_corse_inc[2]_i_4 \n (.I0(\\wrlvl_redo_corse_inc[2]_i_7_n_0 ),\n .I1(early1_data_reg),\n .I2(wrlvl_byte_redo),\n .I3(wrlvl_byte_redo_r),\n .I4(out[2]),\n .I5(\\FSM_sequential_wl_state_r[2]_i_6_n_0 ),\n .O(\\wrlvl_redo_corse_inc[2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\wrlvl_redo_corse_inc[2]_i_5 \n (.I0(\\final_coarse_tap_reg_n_0_[3][1] ),\n .I1(\\final_coarse_tap_reg_n_0_[1][1] ),\n .I2(\\po_stg2_wrcal_cnt_reg[2] [0]),\n .I3(\\final_coarse_tap_reg_n_0_[2][1] ),\n .I4(\\po_stg2_wrcal_cnt_reg[2] [1]),\n .I5(\\final_coarse_tap_reg_n_0_[0][1] ),\n .O(\\wrlvl_redo_corse_inc_reg[2]_0 [0]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\wrlvl_redo_corse_inc[2]_i_6 \n (.I0(\\final_coarse_tap_reg_n_0_[3][2] ),\n .I1(\\final_coarse_tap_reg_n_0_[1][2] ),\n .I2(\\po_stg2_wrcal_cnt_reg[2] [0]),\n .I3(\\final_coarse_tap_reg_n_0_[2][2] ),\n .I4(\\po_stg2_wrcal_cnt_reg[2] [1]),\n .I5(\\final_coarse_tap_reg_n_0_[0][2] ),\n .O(\\wrlvl_redo_corse_inc_reg[2]_0 [1]));\n LUT4 #(\n .INIT(16'h0001)) \n \\wrlvl_redo_corse_inc[2]_i_7 \n (.I0(out[4]),\n .I1(out[3]),\n .I2(out[0]),\n .I3(out[1]),\n .O(\\wrlvl_redo_corse_inc[2]_i_7_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\wrlvl_redo_corse_inc_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wrlvl_redo_corse_inc[0]_i_1_n_0 ),\n .Q(wrlvl_redo_corse_inc__0[0]),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\wrlvl_redo_corse_inc_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wrlvl_redo_corse_inc[1]_i_1_n_0 ),\n .Q(wrlvl_redo_corse_inc__0[1]),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\n FDRE #(\n .INIT(1'b0)) \n \\wrlvl_redo_corse_inc_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wrlvl_redo_corse_inc[2]_i_1_n_0 ),\n .Q(wrlvl_redo_corse_inc__0[2]),\n .R(rstdiv0_sync_r1_reg_rep__17[0]));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_prbs_gen\" *) \nmodule ddr3_ifmig_7series_v4_0_ddr_prbs_gen\n (\\rd_addr_reg[0]_0 ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[120] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[124] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[249] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[253] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[190] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[251] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[255] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[24] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[27] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[28] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[31] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[89] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[93] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[154] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[158] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[90] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[94] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[222] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[218] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[156] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[152] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[25] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[29] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[30] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[26] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[95] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[121] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[123] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[125] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[127] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[184] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[188] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[216] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[219] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[220] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[223] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[185] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[189] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[157] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[153] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[58] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[59] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[62] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[63] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[248] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[252] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[217] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[159] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[155] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[92] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[88] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[61] ,\n Q,\n \\gen_mux_rd[0].compare_data_rise0_r1_reg[0] ,\n \\gen_mux_rd[1].compare_data_rise0_r1_reg[1] ,\n \\gen_mux_rd[2].compare_data_rise0_r1_reg[2] ,\n \\gen_mux_rd[3].compare_data_rise0_r1_reg[3] ,\n \\gen_mux_rd[4].compare_data_rise0_r1_reg[4] ,\n \\gen_mux_rd[5].compare_data_rise0_r1_reg[5] ,\n \\gen_mux_rd[6].compare_data_rise0_r1_reg[6] ,\n \\gen_mux_rd[7].compare_data_rise0_r1_reg[7] ,\n \\gen_mux_rd[0].compare_data_fall0_r1_reg[0] ,\n \\gen_mux_rd[1].compare_data_fall0_r1_reg[1] ,\n \\gen_mux_rd[2].compare_data_fall0_r1_reg[2] ,\n \\gen_mux_rd[3].compare_data_fall0_r1_reg[3] ,\n \\gen_mux_rd[4].compare_data_fall0_r1_reg[4] ,\n \\gen_mux_rd[5].compare_data_fall0_r1_reg[5] ,\n \\gen_mux_rd[6].compare_data_fall0_r1_reg[6] ,\n \\gen_mux_rd[7].compare_data_fall0_r1_reg[7] ,\n \\gen_mux_rd[0].compare_data_rise1_r1_reg[0] ,\n \\gen_mux_rd[1].compare_data_rise1_r1_reg[1] ,\n \\gen_mux_rd[2].compare_data_rise1_r1_reg[2] ,\n \\gen_mux_rd[3].compare_data_rise1_r1_reg[3] ,\n \\gen_mux_rd[4].compare_data_rise1_r1_reg[4] ,\n \\gen_mux_rd[5].compare_data_rise1_r1_reg[5] ,\n \\gen_mux_rd[6].compare_data_rise1_r1_reg[6] ,\n \\gen_mux_rd[7].compare_data_rise1_r1_reg[7] ,\n \\gen_mux_rd[0].compare_data_fall1_r1_reg[0] ,\n \\gen_mux_rd[1].compare_data_fall1_r1_reg[1] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[122] ,\n \\gen_mux_rd[3].compare_data_fall1_r1_reg[3] ,\n \\gen_mux_rd[4].compare_data_fall1_r1_reg[4] ,\n \\gen_mux_rd[5].compare_data_fall1_r1_reg[5] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[126] ,\n \\gen_mux_rd[7].compare_data_fall1_r1_reg[7] ,\n \\gen_mux_rd[0].compare_data_rise2_r1_reg[0] ,\n \\gen_mux_rd[1].compare_data_rise2_r1_reg[1] ,\n \\gen_mux_rd[2].compare_data_rise2_r1_reg[2] ,\n \\gen_mux_rd[3].compare_data_rise2_r1_reg[3] ,\n \\gen_mux_rd[4].compare_data_rise2_r1_reg[4] ,\n \\gen_mux_rd[5].compare_data_rise2_r1_reg[5] ,\n \\gen_mux_rd[6].compare_data_rise2_r1_reg[6] ,\n \\gen_mux_rd[7].compare_data_rise2_r1_reg[7] ,\n \\gen_mux_rd[0].compare_data_fall2_r1_reg[0] ,\n \\gen_mux_rd[1].compare_data_fall2_r1_reg[1] ,\n \\gen_mux_rd[2].compare_data_fall2_r1_reg[2] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187] ,\n \\gen_mux_rd[4].compare_data_fall2_r1_reg[4] ,\n \\gen_mux_rd[5].compare_data_fall2_r1_reg[5] ,\n \\gen_mux_rd[6].compare_data_fall2_r1_reg[6] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] ,\n \\gen_mux_rd[0].compare_data_rise3_r1_reg[0] ,\n \\gen_mux_rd[1].compare_data_rise3_r1_reg[1] ,\n \\gen_mux_rd[2].compare_data_rise3_r1_reg[2] ,\n \\gen_mux_rd[3].compare_data_rise3_r1_reg[3] ,\n \\gen_mux_rd[4].compare_data_rise3_r1_reg[4] ,\n \\gen_mux_rd[5].compare_data_rise3_r1_reg[5] ,\n \\gen_mux_rd[6].compare_data_rise3_r1_reg[6] ,\n \\gen_mux_rd[7].compare_data_rise3_r1_reg[7] ,\n \\gen_mux_rd[0].compare_data_fall3_r1_reg[0] ,\n \\gen_mux_rd[1].compare_data_fall3_r1_reg[1] ,\n \\gen_mux_rd[2].compare_data_fall3_r1_reg[2] ,\n \\gen_mux_rd[3].compare_data_fall3_r1_reg[3] ,\n \\gen_mux_rd[4].compare_data_fall3_r1_reg[4] ,\n \\gen_mux_rd[5].compare_data_fall3_r1_reg[5] ,\n \\gen_mux_rd[6].compare_data_fall3_r1_reg[6] ,\n \\gen_mux_rd[7].compare_data_fall3_r1_reg[7] ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,\n CLK,\n rdlvl_stg1_done_int_reg,\n wrcal_done_reg,\n first_rdlvl_pat_r,\n oclkdelay_calib_done_r_reg,\n \\rd_addr_reg[3]_0 ,\n rstdiv0_sync_r1_reg_rep__19,\n D,\n SR,\n E);\n output \\rd_addr_reg[0]_0 ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[120] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[124] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[249] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[253] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[190] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[251] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[255] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[24] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[27] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[28] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[31] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[89] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[93] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[154] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[158] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[90] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[94] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[222] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[218] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[156] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[152] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[25] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[29] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[30] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[26] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[95] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[121] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[123] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[125] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[127] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[184] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[188] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[216] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[219] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[220] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[223] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[185] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[189] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[157] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[153] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[58] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[59] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[62] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[63] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[248] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[252] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[217] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[159] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[155] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[92] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[88] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[61] ;\n output [0:0]Q;\n output \\gen_mux_rd[0].compare_data_rise0_r1_reg[0] ;\n output \\gen_mux_rd[1].compare_data_rise0_r1_reg[1] ;\n output \\gen_mux_rd[2].compare_data_rise0_r1_reg[2] ;\n output \\gen_mux_rd[3].compare_data_rise0_r1_reg[3] ;\n output \\gen_mux_rd[4].compare_data_rise0_r1_reg[4] ;\n output \\gen_mux_rd[5].compare_data_rise0_r1_reg[5] ;\n output \\gen_mux_rd[6].compare_data_rise0_r1_reg[6] ;\n output \\gen_mux_rd[7].compare_data_rise0_r1_reg[7] ;\n output \\gen_mux_rd[0].compare_data_fall0_r1_reg[0] ;\n output \\gen_mux_rd[1].compare_data_fall0_r1_reg[1] ;\n output \\gen_mux_rd[2].compare_data_fall0_r1_reg[2] ;\n output \\gen_mux_rd[3].compare_data_fall0_r1_reg[3] ;\n output \\gen_mux_rd[4].compare_data_fall0_r1_reg[4] ;\n output \\gen_mux_rd[5].compare_data_fall0_r1_reg[5] ;\n output \\gen_mux_rd[6].compare_data_fall0_r1_reg[6] ;\n output \\gen_mux_rd[7].compare_data_fall0_r1_reg[7] ;\n output \\gen_mux_rd[0].compare_data_rise1_r1_reg[0] ;\n output \\gen_mux_rd[1].compare_data_rise1_r1_reg[1] ;\n output \\gen_mux_rd[2].compare_data_rise1_r1_reg[2] ;\n output \\gen_mux_rd[3].compare_data_rise1_r1_reg[3] ;\n output \\gen_mux_rd[4].compare_data_rise1_r1_reg[4] ;\n output \\gen_mux_rd[5].compare_data_rise1_r1_reg[5] ;\n output \\gen_mux_rd[6].compare_data_rise1_r1_reg[6] ;\n output \\gen_mux_rd[7].compare_data_rise1_r1_reg[7] ;\n output \\gen_mux_rd[0].compare_data_fall1_r1_reg[0] ;\n output \\gen_mux_rd[1].compare_data_fall1_r1_reg[1] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[122] ;\n output \\gen_mux_rd[3].compare_data_fall1_r1_reg[3] ;\n output \\gen_mux_rd[4].compare_data_fall1_r1_reg[4] ;\n output \\gen_mux_rd[5].compare_data_fall1_r1_reg[5] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[126] ;\n output \\gen_mux_rd[7].compare_data_fall1_r1_reg[7] ;\n output \\gen_mux_rd[0].compare_data_rise2_r1_reg[0] ;\n output \\gen_mux_rd[1].compare_data_rise2_r1_reg[1] ;\n output \\gen_mux_rd[2].compare_data_rise2_r1_reg[2] ;\n output \\gen_mux_rd[3].compare_data_rise2_r1_reg[3] ;\n output \\gen_mux_rd[4].compare_data_rise2_r1_reg[4] ;\n output \\gen_mux_rd[5].compare_data_rise2_r1_reg[5] ;\n output \\gen_mux_rd[6].compare_data_rise2_r1_reg[6] ;\n output \\gen_mux_rd[7].compare_data_rise2_r1_reg[7] ;\n output \\gen_mux_rd[0].compare_data_fall2_r1_reg[0] ;\n output \\gen_mux_rd[1].compare_data_fall2_r1_reg[1] ;\n output \\gen_mux_rd[2].compare_data_fall2_r1_reg[2] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187] ;\n output \\gen_mux_rd[4].compare_data_fall2_r1_reg[4] ;\n output \\gen_mux_rd[5].compare_data_fall2_r1_reg[5] ;\n output \\gen_mux_rd[6].compare_data_fall2_r1_reg[6] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] ;\n output \\gen_mux_rd[0].compare_data_rise3_r1_reg[0] ;\n output \\gen_mux_rd[1].compare_data_rise3_r1_reg[1] ;\n output \\gen_mux_rd[2].compare_data_rise3_r1_reg[2] ;\n output \\gen_mux_rd[3].compare_data_rise3_r1_reg[3] ;\n output \\gen_mux_rd[4].compare_data_rise3_r1_reg[4] ;\n output \\gen_mux_rd[5].compare_data_rise3_r1_reg[5] ;\n output \\gen_mux_rd[6].compare_data_rise3_r1_reg[6] ;\n output \\gen_mux_rd[7].compare_data_rise3_r1_reg[7] ;\n output \\gen_mux_rd[0].compare_data_fall3_r1_reg[0] ;\n output \\gen_mux_rd[1].compare_data_fall3_r1_reg[1] ;\n output \\gen_mux_rd[2].compare_data_fall3_r1_reg[2] ;\n output \\gen_mux_rd[3].compare_data_fall3_r1_reg[3] ;\n output \\gen_mux_rd[4].compare_data_fall3_r1_reg[4] ;\n output \\gen_mux_rd[5].compare_data_fall3_r1_reg[5] ;\n output \\gen_mux_rd[6].compare_data_fall3_r1_reg[6] ;\n output \\gen_mux_rd[7].compare_data_fall3_r1_reg[7] ;\n input \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n input CLK;\n input rdlvl_stg1_done_int_reg;\n input wrcal_done_reg;\n input first_rdlvl_pat_r;\n input oclkdelay_calib_done_r_reg;\n input \\rd_addr_reg[3]_0 ;\n input [0:0]rstdiv0_sync_r1_reg_rep__19;\n input [7:0]D;\n input [0:0]SR;\n input [0:0]E;\n\n wire CLK;\n wire [7:0]D;\n wire [0:0]E;\n wire [0:0]Q;\n wire [0:0]SR;\n wire \\dout_o[0]_i_1_n_0 ;\n wire \\dout_o[0]_i_2_n_0 ;\n wire \\dout_o[0]_i_3_n_0 ;\n wire \\dout_o[0]_i_4_n_0 ;\n wire \\dout_o[10]_i_1_n_0 ;\n wire \\dout_o[10]_i_2_n_0 ;\n wire \\dout_o[10]_i_3_n_0 ;\n wire \\dout_o[11]_i_1_n_0 ;\n wire \\dout_o[11]_i_2_n_0 ;\n wire \\dout_o[11]_i_3_n_0 ;\n wire \\dout_o[11]_i_4_n_0 ;\n wire \\dout_o[12]_i_1_n_0 ;\n wire \\dout_o[12]_i_2_n_0 ;\n wire \\dout_o[12]_i_3_n_0 ;\n wire \\dout_o[12]_i_4_n_0 ;\n wire \\dout_o[13]_i_1_n_0 ;\n wire \\dout_o[13]_i_2_n_0 ;\n wire \\dout_o[13]_i_3_n_0 ;\n wire \\dout_o[13]_i_4_n_0 ;\n wire \\dout_o[14]_i_1_n_0 ;\n wire \\dout_o[14]_i_2_n_0 ;\n wire \\dout_o[14]_i_3_n_0 ;\n wire \\dout_o[14]_i_4_n_0 ;\n wire \\dout_o[15]_i_1_n_0 ;\n wire \\dout_o[15]_i_2_n_0 ;\n wire \\dout_o[15]_i_3_n_0 ;\n wire \\dout_o[15]_i_4_n_0 ;\n wire \\dout_o[1]_i_1_n_0 ;\n wire \\dout_o[1]_i_2_n_0 ;\n wire \\dout_o[1]_i_3_n_0 ;\n wire \\dout_o[1]_i_4_n_0 ;\n wire \\dout_o[2]_i_1_n_0 ;\n wire \\dout_o[2]_i_2_n_0 ;\n wire \\dout_o[2]_i_3_n_0 ;\n wire \\dout_o[2]_i_4_n_0 ;\n wire \\dout_o[3]_i_1_n_0 ;\n wire \\dout_o[3]_i_2_n_0 ;\n wire \\dout_o[3]_i_3_n_0 ;\n wire \\dout_o[3]_i_4_n_0 ;\n wire \\dout_o[4]_i_1_n_0 ;\n wire \\dout_o[4]_i_2_n_0 ;\n wire \\dout_o[4]_i_3_n_0 ;\n wire \\dout_o[4]_i_4_n_0 ;\n wire \\dout_o[5]_i_1_n_0 ;\n wire \\dout_o[5]_i_2_n_0 ;\n wire \\dout_o[5]_i_3_n_0 ;\n wire \\dout_o[5]_i_4_n_0 ;\n wire \\dout_o[6]_i_1_n_0 ;\n wire \\dout_o[6]_i_2_n_0 ;\n wire \\dout_o[6]_i_3_n_0 ;\n wire \\dout_o[6]_i_4_n_0 ;\n wire \\dout_o[7]_i_1_n_0 ;\n wire \\dout_o[7]_i_2_n_0 ;\n wire \\dout_o[7]_i_3_n_0 ;\n wire \\dout_o[7]_i_4_n_0 ;\n wire \\dout_o[8]_i_1_n_0 ;\n wire \\dout_o[8]_i_2_n_0 ;\n wire \\dout_o[8]_i_3_n_0 ;\n wire \\dout_o[8]_i_4_n_0 ;\n wire \\dout_o[9]_i_1_n_0 ;\n wire \\dout_o[9]_i_2_n_0 ;\n wire \\dout_o[9]_i_3_n_0 ;\n wire \\dout_o[9]_i_4_n_0 ;\n wire \\dout_o_reg_n_0_[0] ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n wire first_rdlvl_pat_r;\n wire \\gen_mux_rd[0].compare_data_fall0_r1_reg[0] ;\n wire \\gen_mux_rd[0].compare_data_fall1_r1_reg[0] ;\n wire \\gen_mux_rd[0].compare_data_fall2_r1_reg[0] ;\n wire \\gen_mux_rd[0].compare_data_fall3_r1_reg[0] ;\n wire \\gen_mux_rd[0].compare_data_rise0_r1_reg[0] ;\n wire \\gen_mux_rd[0].compare_data_rise1_r1_reg[0] ;\n wire \\gen_mux_rd[0].compare_data_rise2_r1_reg[0] ;\n wire \\gen_mux_rd[0].compare_data_rise3_r1_reg[0] ;\n wire \\gen_mux_rd[1].compare_data_fall0_r1_reg[1] ;\n wire \\gen_mux_rd[1].compare_data_fall1_r1_reg[1] ;\n wire \\gen_mux_rd[1].compare_data_fall2_r1_reg[1] ;\n wire \\gen_mux_rd[1].compare_data_fall3_r1_reg[1] ;\n wire \\gen_mux_rd[1].compare_data_rise0_r1_reg[1] ;\n wire \\gen_mux_rd[1].compare_data_rise1_r1_reg[1] ;\n wire \\gen_mux_rd[1].compare_data_rise2_r1_reg[1] ;\n wire \\gen_mux_rd[1].compare_data_rise3_r1_reg[1] ;\n wire \\gen_mux_rd[2].compare_data_fall0_r1_reg[2] ;\n wire \\gen_mux_rd[2].compare_data_fall2_r1_reg[2] ;\n wire \\gen_mux_rd[2].compare_data_fall3_r1_reg[2] ;\n wire \\gen_mux_rd[2].compare_data_rise0_r1_reg[2] ;\n wire \\gen_mux_rd[2].compare_data_rise1_r1_reg[2] ;\n wire \\gen_mux_rd[2].compare_data_rise2_r1_reg[2] ;\n wire \\gen_mux_rd[2].compare_data_rise3_r1_reg[2] ;\n wire \\gen_mux_rd[3].compare_data_fall0_r1_reg[3] ;\n wire \\gen_mux_rd[3].compare_data_fall1_r1_reg[3] ;\n wire \\gen_mux_rd[3].compare_data_fall3_r1_reg[3] ;\n wire \\gen_mux_rd[3].compare_data_rise0_r1_reg[3] ;\n wire \\gen_mux_rd[3].compare_data_rise1_r1_reg[3] ;\n wire \\gen_mux_rd[3].compare_data_rise2_r1_reg[3] ;\n wire \\gen_mux_rd[3].compare_data_rise3_r1_reg[3] ;\n wire \\gen_mux_rd[4].compare_data_fall0_r1_reg[4] ;\n wire \\gen_mux_rd[4].compare_data_fall1_r1_reg[4] ;\n wire \\gen_mux_rd[4].compare_data_fall2_r1_reg[4] ;\n wire \\gen_mux_rd[4].compare_data_fall3_r1_reg[4] ;\n wire \\gen_mux_rd[4].compare_data_rise0_r1_reg[4] ;\n wire \\gen_mux_rd[4].compare_data_rise1_r1_reg[4] ;\n wire \\gen_mux_rd[4].compare_data_rise2_r1_reg[4] ;\n wire \\gen_mux_rd[4].compare_data_rise3_r1_reg[4] ;\n wire \\gen_mux_rd[5].compare_data_fall0_r1_reg[5] ;\n wire \\gen_mux_rd[5].compare_data_fall1_r1_reg[5] ;\n wire \\gen_mux_rd[5].compare_data_fall2_r1_reg[5] ;\n wire \\gen_mux_rd[5].compare_data_fall3_r1_reg[5] ;\n wire \\gen_mux_rd[5].compare_data_rise0_r1_reg[5] ;\n wire \\gen_mux_rd[5].compare_data_rise1_r1_reg[5] ;\n wire \\gen_mux_rd[5].compare_data_rise2_r1_reg[5] ;\n wire \\gen_mux_rd[5].compare_data_rise3_r1_reg[5] ;\n wire \\gen_mux_rd[6].compare_data_fall0_r1_reg[6] ;\n wire \\gen_mux_rd[6].compare_data_fall2_r1_reg[6] ;\n wire \\gen_mux_rd[6].compare_data_fall3_r1_reg[6] ;\n wire \\gen_mux_rd[6].compare_data_rise0_r1_reg[6] ;\n wire \\gen_mux_rd[6].compare_data_rise1_r1_reg[6] ;\n wire \\gen_mux_rd[6].compare_data_rise2_r1_reg[6] ;\n wire \\gen_mux_rd[6].compare_data_rise3_r1_reg[6] ;\n wire \\gen_mux_rd[7].compare_data_fall0_r1_reg[7] ;\n wire \\gen_mux_rd[7].compare_data_fall1_r1_reg[7] ;\n wire \\gen_mux_rd[7].compare_data_fall3_r1_reg[7] ;\n wire \\gen_mux_rd[7].compare_data_rise0_r1_reg[7] ;\n wire \\gen_mux_rd[7].compare_data_rise1_r1_reg[7] ;\n wire \\gen_mux_rd[7].compare_data_rise2_r1_reg[7] ;\n wire \\gen_mux_rd[7].compare_data_rise3_r1_reg[7] ;\n wire oclkdelay_calib_done_r_reg;\n wire p_0_in102_in;\n wire p_0_in106_in;\n wire p_0_in110_in;\n wire p_0_in114_in;\n wire p_0_in118_in;\n wire p_0_in122_in;\n wire p_0_in94_in;\n wire p_0_in98_in;\n wire p_1_in;\n wire p_1_in124_in;\n wire p_1_in190_in;\n wire p_1_in256_in;\n wire p_1_in322_in;\n wire p_1_in388_in;\n wire p_1_in454_in;\n wire p_1_in520_in;\n wire [7:0]p_1_in__0;\n wire p_2_in;\n wire p_2_in126_in;\n wire p_2_in192_in;\n wire p_2_in258_in;\n wire p_2_in324_in;\n wire p_2_in390_in;\n wire p_2_in456_in;\n wire \\rd_addr[7]_i_4_n_0 ;\n wire \\rd_addr[7]_i_5_n_0 ;\n wire \\rd_addr[7]_i_6_n_0 ;\n wire \\rd_addr_reg[0]_0 ;\n wire \\rd_addr_reg[3]_0 ;\n wire \\rd_addr_reg_n_0_[0] ;\n wire \\rd_addr_reg_n_0_[1] ;\n wire \\rd_addr_reg_n_0_[2] ;\n wire \\rd_addr_reg_n_0_[4] ;\n wire \\rd_addr_reg_n_0_[5] ;\n wire \\rd_addr_reg_n_0_[6] ;\n wire \\rd_addr_reg_n_0_[7] ;\n wire \\rd_addr_reg_rep_n_0_[0] ;\n wire \\rd_addr_reg_rep_n_0_[1] ;\n wire \\rd_addr_reg_rep_n_0_[2] ;\n wire \\rd_addr_reg_rep_n_0_[3] ;\n wire \\rd_addr_reg_rep_n_0_[4] ;\n wire \\rd_addr_reg_rep_n_0_[5] ;\n wire \\rd_addr_reg_rep_n_0_[6] ;\n wire \\rd_addr_reg_rep_n_0_[7] ;\n wire rdlvl_stg1_done_int_reg;\n wire [0:0]rstdiv0_sync_r1_reg_rep__19;\n wire wrcal_done_reg;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[120] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[121] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[122] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[123] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[124] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[125] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[126] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[127] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[152] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[153] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[154] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[155] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[156] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[157] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[158] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[159] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[184] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[185] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[188] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[189] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[190] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[216] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[217] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[218] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[219] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[220] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[222] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[223] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[248] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[249] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[24] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[251] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[252] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[253] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[255] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[25] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[26] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[27] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[28] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[29] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[30] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[31] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[58] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[59] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[61] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[62] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[63] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[88] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[89] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[90] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[92] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[93] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[94] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[95] ;\n\n LUT5 #(\n .INIT(32'hFCBBFC88)) \n \\dout_o[0]_i_1 \n (.I0(\\dout_o[0]_i_2_n_0 ),\n .I1(\\rd_addr_reg_rep_n_0_[6] ),\n .I2(\\dout_o[0]_i_3_n_0 ),\n .I3(\\rd_addr_reg_rep_n_0_[7] ),\n .I4(\\dout_o[0]_i_4_n_0 ),\n .O(\\dout_o[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFBA702DC40FD7BA7)) \n \\dout_o[0]_i_2 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[1] ),\n .I5(\\rd_addr_reg_rep_n_0_[4] ),\n .O(\\dout_o[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFF941DDE1)) \n \\dout_o[0]_i_3 \n (.I0(\\rd_addr_reg_rep_n_0_[4] ),\n .I1(\\rd_addr_reg_rep_n_0_[1] ),\n .I2(\\rd_addr_reg_rep_n_0_[0] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[3] ),\n .I5(\\rd_addr_reg_rep_n_0_[5] ),\n .O(\\dout_o[0]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h5F74ABA8D4EB4862)) \n \\dout_o[0]_i_4 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[4] ),\n .I5(\\rd_addr_reg_rep_n_0_[1] ),\n .O(\\dout_o[0]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\dout_o[10]_i_1 \n (.I0(\\dout_o[12]_i_2_n_0 ),\n .I1(\\rd_addr_reg_rep_n_0_[6] ),\n .I2(\\dout_o[10]_i_2_n_0 ),\n .I3(\\rd_addr_reg_rep_n_0_[7] ),\n .I4(\\dout_o[10]_i_3_n_0 ),\n .O(\\dout_o[10]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h000000004599CD27)) \n \\dout_o[10]_i_2 \n (.I0(\\rd_addr_reg_rep_n_0_[4] ),\n .I1(\\rd_addr_reg_rep_n_0_[1] ),\n .I2(\\rd_addr_reg_rep_n_0_[0] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[3] ),\n .I5(\\rd_addr_reg_rep_n_0_[5] ),\n .O(\\dout_o[10]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h139126016C0923FA)) \n \\dout_o[10]_i_3 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[1] ),\n .I5(\\rd_addr_reg_rep_n_0_[4] ),\n .O(\\dout_o[10]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\dout_o[11]_i_1 \n (.I0(\\dout_o[11]_i_2_n_0 ),\n .I1(\\rd_addr_reg_rep_n_0_[6] ),\n .I2(\\dout_o[11]_i_3_n_0 ),\n .I3(\\rd_addr_reg_rep_n_0_[7] ),\n .I4(\\dout_o[11]_i_4_n_0 ),\n .O(\\dout_o[11]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h713DD3CC4AE43A65)) \n \\dout_o[11]_i_2 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[4] ),\n .I5(\\rd_addr_reg_rep_n_0_[1] ),\n .O(\\dout_o[11]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00000000322002AD)) \n \\dout_o[11]_i_3 \n (.I0(\\rd_addr_reg_rep_n_0_[1] ),\n .I1(\\rd_addr_reg_rep_n_0_[4] ),\n .I2(\\rd_addr_reg_rep_n_0_[0] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[3] ),\n .I5(\\rd_addr_reg_rep_n_0_[5] ),\n .O(\\dout_o[11]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h7BB6E4333589857B)) \n \\dout_o[11]_i_4 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[1] ),\n .I4(\\rd_addr_reg_rep_n_0_[4] ),\n .I5(\\rd_addr_reg_rep_n_0_[0] ),\n .O(\\dout_o[11]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\dout_o[12]_i_1 \n (.I0(\\dout_o[12]_i_2_n_0 ),\n .I1(\\rd_addr_reg_rep_n_0_[6] ),\n .I2(\\dout_o[12]_i_3_n_0 ),\n .I3(\\rd_addr_reg_rep_n_0_[7] ),\n .I4(\\dout_o[12]_i_4_n_0 ),\n .O(\\dout_o[12]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h9100E82800132190)) \n \\dout_o[12]_i_2 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[4] ),\n .I5(\\rd_addr_reg_rep_n_0_[1] ),\n .O(\\dout_o[12]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000031C1E208)) \n \\dout_o[12]_i_3 \n (.I0(\\rd_addr_reg_rep_n_0_[0] ),\n .I1(\\rd_addr_reg_rep_n_0_[4] ),\n .I2(\\rd_addr_reg_rep_n_0_[1] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[3] ),\n .I5(\\rd_addr_reg_rep_n_0_[5] ),\n .O(\\dout_o[12]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h447C4014C71C60A6)) \n \\dout_o[12]_i_4 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[4] ),\n .I4(\\rd_addr_reg_rep_n_0_[1] ),\n .I5(\\rd_addr_reg_rep_n_0_[0] ),\n .O(\\dout_o[12]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\dout_o[13]_i_1 \n (.I0(\\dout_o[13]_i_2_n_0 ),\n .I1(\\rd_addr_reg_rep_n_0_[6] ),\n .I2(\\dout_o[13]_i_3_n_0 ),\n .I3(\\rd_addr_reg_rep_n_0_[7] ),\n .I4(\\dout_o[13]_i_4_n_0 ),\n .O(\\dout_o[13]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h5D37E7F8E29A3F4D)) \n \\dout_o[13]_i_2 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[2] ),\n .I2(\\rd_addr_reg_rep_n_0_[3] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[4] ),\n .I5(\\rd_addr_reg_rep_n_0_[1] ),\n .O(\\dout_o[13]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000040055161)) \n \\dout_o[13]_i_3 \n (.I0(\\rd_addr_reg_rep_n_0_[4] ),\n .I1(\\rd_addr_reg_rep_n_0_[1] ),\n .I2(\\rd_addr_reg_rep_n_0_[0] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[3] ),\n .I5(\\rd_addr_reg_rep_n_0_[5] ),\n .O(\\dout_o[13]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h6EEDFF5CF2C694A7)) \n \\dout_o[13]_i_4 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[4] ),\n .I5(\\rd_addr_reg_rep_n_0_[1] ),\n .O(\\dout_o[13]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\dout_o[14]_i_1 \n (.I0(\\dout_o[14]_i_2_n_0 ),\n .I1(\\rd_addr_reg_rep_n_0_[6] ),\n .I2(\\dout_o[14]_i_3_n_0 ),\n .I3(\\rd_addr_reg_rep_n_0_[7] ),\n .I4(\\dout_o[14]_i_4_n_0 ),\n .O(\\dout_o[14]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h9100682100130190)) \n \\dout_o[14]_i_2 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[4] ),\n .I5(\\rd_addr_reg_rep_n_0_[1] ),\n .O(\\dout_o[14]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00000000118A8B19)) \n \\dout_o[14]_i_3 \n (.I0(\\rd_addr_reg_rep_n_0_[1] ),\n .I1(\\rd_addr_reg_rep_n_0_[4] ),\n .I2(\\rd_addr_reg_rep_n_0_[0] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[3] ),\n .I5(\\rd_addr_reg_rep_n_0_[5] ),\n .O(\\dout_o[14]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hD473D375410D7424)) \n \\dout_o[14]_i_4 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[4] ),\n .I4(\\rd_addr_reg_rep_n_0_[0] ),\n .I5(\\rd_addr_reg_rep_n_0_[1] ),\n .O(\\dout_o[14]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\dout_o[15]_i_1 \n (.I0(\\dout_o[15]_i_2_n_0 ),\n .I1(\\rd_addr_reg_rep_n_0_[6] ),\n .I2(\\dout_o[15]_i_3_n_0 ),\n .I3(\\rd_addr_reg_rep_n_0_[7] ),\n .I4(\\dout_o[15]_i_4_n_0 ),\n .O(\\dout_o[15]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h5D27F5EADA9A3F4D)) \n \\dout_o[15]_i_2 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[2] ),\n .I2(\\rd_addr_reg_rep_n_0_[3] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[4] ),\n .I5(\\rd_addr_reg_rep_n_0_[1] ),\n .O(\\dout_o[15]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h000000004115533E)) \n \\dout_o[15]_i_3 \n (.I0(\\rd_addr_reg_rep_n_0_[4] ),\n .I1(\\rd_addr_reg_rep_n_0_[1] ),\n .I2(\\rd_addr_reg_rep_n_0_[0] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[3] ),\n .I5(\\rd_addr_reg_rep_n_0_[5] ),\n .O(\\dout_o[15]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h5EF9FF567BFFCDB5)) \n \\dout_o[15]_i_4 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[1] ),\n .I5(\\rd_addr_reg_rep_n_0_[4] ),\n .O(\\dout_o[15]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\dout_o[1]_i_1 \n (.I0(\\dout_o[1]_i_2_n_0 ),\n .I1(\\rd_addr_reg_rep_n_0_[6] ),\n .I2(\\dout_o[1]_i_3_n_0 ),\n .I3(\\rd_addr_reg_rep_n_0_[7] ),\n .I4(\\dout_o[1]_i_4_n_0 ),\n .O(\\dout_o[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hE7E55AE75A58865A)) \n \\dout_o[1]_i_2 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[4] ),\n .I4(\\rd_addr_reg_rep_n_0_[1] ),\n .I5(\\rd_addr_reg_rep_n_0_[0] ),\n .O(\\dout_o[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000051880521)) \n \\dout_o[1]_i_3 \n (.I0(\\rd_addr_reg_rep_n_0_[4] ),\n .I1(\\rd_addr_reg_rep_n_0_[1] ),\n .I2(\\rd_addr_reg_rep_n_0_[0] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[3] ),\n .I5(\\rd_addr_reg_rep_n_0_[5] ),\n .O(\\dout_o[1]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h7ADF52E8C4A8E711)) \n \\dout_o[1]_i_4 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[4] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[0] ),\n .I5(\\rd_addr_reg_rep_n_0_[1] ),\n .O(\\dout_o[1]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\dout_o[2]_i_1 \n (.I0(\\dout_o[2]_i_2_n_0 ),\n .I1(\\rd_addr_reg_rep_n_0_[6] ),\n .I2(\\dout_o[2]_i_3_n_0 ),\n .I3(\\rd_addr_reg_rep_n_0_[7] ),\n .I4(\\dout_o[2]_i_4_n_0 ),\n .O(\\dout_o[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFB02235842E57B02)) \n \\dout_o[2]_i_2 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[1] ),\n .I5(\\rd_addr_reg_rep_n_0_[4] ),\n .O(\\dout_o[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00000000020DCBD5)) \n \\dout_o[2]_i_3 \n (.I0(\\rd_addr_reg_rep_n_0_[0] ),\n .I1(\\rd_addr_reg_rep_n_0_[1] ),\n .I2(\\rd_addr_reg_rep_n_0_[4] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[3] ),\n .I5(\\rd_addr_reg_rep_n_0_[5] ),\n .O(\\dout_o[2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hCF45D0CFCE2B8950)) \n \\dout_o[2]_i_4 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[1] ),\n .I5(\\rd_addr_reg_rep_n_0_[4] ),\n .O(\\dout_o[2]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\dout_o[3]_i_1 \n (.I0(\\dout_o[3]_i_2_n_0 ),\n .I1(\\rd_addr_reg_rep_n_0_[6] ),\n .I2(\\dout_o[3]_i_3_n_0 ),\n .I3(\\rd_addr_reg_rep_n_0_[7] ),\n .I4(\\dout_o[3]_i_4_n_0 ),\n .O(\\dout_o[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h46E55AC658188658)) \n \\dout_o[3]_i_2 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[4] ),\n .I4(\\rd_addr_reg_rep_n_0_[1] ),\n .I5(\\rd_addr_reg_rep_n_0_[0] ),\n .O(\\dout_o[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00000000019C0421)) \n \\dout_o[3]_i_3 \n (.I0(\\rd_addr_reg_rep_n_0_[4] ),\n .I1(\\rd_addr_reg_rep_n_0_[1] ),\n .I2(\\rd_addr_reg_rep_n_0_[0] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[3] ),\n .I5(\\rd_addr_reg_rep_n_0_[5] ),\n .O(\\dout_o[3]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h2DCA4E194B652751)) \n \\dout_o[3]_i_4 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[1] ),\n .I4(\\rd_addr_reg_rep_n_0_[4] ),\n .I5(\\rd_addr_reg_rep_n_0_[0] ),\n .O(\\dout_o[3]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\dout_o[4]_i_1 \n (.I0(\\dout_o[4]_i_2_n_0 ),\n .I1(\\rd_addr_reg_rep_n_0_[6] ),\n .I2(\\dout_o[4]_i_3_n_0 ),\n .I3(\\rd_addr_reg_rep_n_0_[7] ),\n .I4(\\dout_o[4]_i_4_n_0 ),\n .O(\\dout_o[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hD87BBD58DE86587B)) \n \\dout_o[4]_i_2 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[4] ),\n .I5(\\rd_addr_reg_rep_n_0_[1] ),\n .O(\\dout_o[4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h000000000455F0E2)) \n \\dout_o[4]_i_3 \n (.I0(\\rd_addr_reg_rep_n_0_[4] ),\n .I1(\\rd_addr_reg_rep_n_0_[0] ),\n .I2(\\rd_addr_reg_rep_n_0_[1] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[3] ),\n .I5(\\rd_addr_reg_rep_n_0_[5] ),\n .O(\\dout_o[4]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h1A563E3E1BBEA40C)) \n \\dout_o[4]_i_4 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[4] ),\n .I4(\\rd_addr_reg_rep_n_0_[1] ),\n .I5(\\rd_addr_reg_rep_n_0_[0] ),\n .O(\\dout_o[4]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\dout_o[5]_i_1 \n (.I0(\\dout_o[5]_i_2_n_0 ),\n .I1(\\rd_addr_reg_rep_n_0_[6] ),\n .I2(\\dout_o[5]_i_3_n_0 ),\n .I3(\\rd_addr_reg_rep_n_0_[7] ),\n .I4(\\dout_o[5]_i_4_n_0 ),\n .O(\\dout_o[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h42588642FDA55AFD)) \n \\dout_o[5]_i_2 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[4] ),\n .I4(\\rd_addr_reg_rep_n_0_[1] ),\n .I5(\\rd_addr_reg_rep_n_0_[0] ),\n .O(\\dout_o[5]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000013A810A9)) \n \\dout_o[5]_i_3 \n (.I0(\\rd_addr_reg_rep_n_0_[1] ),\n .I1(\\rd_addr_reg_rep_n_0_[4] ),\n .I2(\\rd_addr_reg_rep_n_0_[0] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[3] ),\n .I5(\\rd_addr_reg_rep_n_0_[5] ),\n .O(\\dout_o[5]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h183B5DF6A40A3E0D)) \n \\dout_o[5]_i_4 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[4] ),\n .I5(\\rd_addr_reg_rep_n_0_[1] ),\n .O(\\dout_o[5]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\dout_o[6]_i_1 \n (.I0(\\dout_o[6]_i_2_n_0 ),\n .I1(\\rd_addr_reg_rep_n_0_[6] ),\n .I2(\\dout_o[6]_i_3_n_0 ),\n .I3(\\rd_addr_reg_rep_n_0_[7] ),\n .I4(\\dout_o[6]_i_4_n_0 ),\n .O(\\dout_o[6]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hA35A585A84A7235A)) \n \\dout_o[6]_i_2 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[4] ),\n .I5(\\rd_addr_reg_rep_n_0_[1] ),\n .O(\\dout_o[6]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h000000004441C9B1)) \n \\dout_o[6]_i_3 \n (.I0(\\rd_addr_reg_rep_n_0_[4] ),\n .I1(\\rd_addr_reg_rep_n_0_[1] ),\n .I2(\\rd_addr_reg_rep_n_0_[0] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[3] ),\n .I5(\\rd_addr_reg_rep_n_0_[5] ),\n .O(\\dout_o[6]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h00D98F5FB527B08E)) \n \\dout_o[6]_i_4 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[4] ),\n .I4(\\rd_addr_reg_rep_n_0_[0] ),\n .I5(\\rd_addr_reg_rep_n_0_[1] ),\n .O(\\dout_o[6]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\dout_o[7]_i_1 \n (.I0(\\dout_o[7]_i_2_n_0 ),\n .I1(\\rd_addr_reg_rep_n_0_[6] ),\n .I2(\\dout_o[7]_i_3_n_0 ),\n .I3(\\rd_addr_reg_rep_n_0_[7] ),\n .I4(\\dout_o[7]_i_4_n_0 ),\n .O(\\dout_o[7]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h5C00BF1AFFA5DC00)) \n \\dout_o[7]_i_2 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[4] ),\n .I5(\\rd_addr_reg_rep_n_0_[1] ),\n .O(\\dout_o[7]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000016D00494)) \n \\dout_o[7]_i_3 \n (.I0(\\rd_addr_reg_rep_n_0_[4] ),\n .I1(\\rd_addr_reg_rep_n_0_[1] ),\n .I2(\\rd_addr_reg_rep_n_0_[0] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[3] ),\n .I5(\\rd_addr_reg_rep_n_0_[5] ),\n .O(\\dout_o[7]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hAA852B305155E79F)) \n \\dout_o[7]_i_4 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[1] ),\n .I5(\\rd_addr_reg_rep_n_0_[4] ),\n .O(\\dout_o[7]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'hFCBBFC88)) \n \\dout_o[8]_i_1 \n (.I0(\\dout_o[8]_i_2_n_0 ),\n .I1(\\rd_addr_reg_rep_n_0_[6] ),\n .I2(\\dout_o[8]_i_3_n_0 ),\n .I3(\\rd_addr_reg_rep_n_0_[7] ),\n .I4(\\dout_o[8]_i_4_n_0 ),\n .O(\\dout_o[8]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h91C9002800211311)) \n \\dout_o[8]_i_2 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[4] ),\n .I4(\\rd_addr_reg_rep_n_0_[0] ),\n .I5(\\rd_addr_reg_rep_n_0_[1] ),\n .O(\\dout_o[8]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFD8D3F245)) \n \\dout_o[8]_i_3 \n (.I0(\\rd_addr_reg_rep_n_0_[0] ),\n .I1(\\rd_addr_reg_rep_n_0_[4] ),\n .I2(\\rd_addr_reg_rep_n_0_[1] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[3] ),\n .I5(\\rd_addr_reg_rep_n_0_[5] ),\n .O(\\dout_o[8]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0A06800432120528)) \n \\dout_o[8]_i_4 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[1] ),\n .I3(\\rd_addr_reg_rep_n_0_[4] ),\n .I4(\\rd_addr_reg_rep_n_0_[0] ),\n .I5(\\rd_addr_reg_rep_n_0_[2] ),\n .O(\\dout_o[8]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\dout_o[9]_i_1 \n (.I0(\\dout_o[9]_i_2_n_0 ),\n .I1(\\rd_addr_reg_rep_n_0_[6] ),\n .I2(\\dout_o[9]_i_3_n_0 ),\n .I3(\\rd_addr_reg_rep_n_0_[7] ),\n .I4(\\dout_o[9]_i_4_n_0 ),\n .O(\\dout_o[9]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hF3F5C3DC0AE47A65)) \n \\dout_o[9]_i_2 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[4] ),\n .I5(\\rd_addr_reg_rep_n_0_[1] ),\n .O(\\dout_o[9]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00000000040E06D5)) \n \\dout_o[9]_i_3 \n (.I0(\\rd_addr_reg_rep_n_0_[0] ),\n .I1(\\rd_addr_reg_rep_n_0_[1] ),\n .I2(\\rd_addr_reg_rep_n_0_[4] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[3] ),\n .I5(\\rd_addr_reg_rep_n_0_[5] ),\n .O(\\dout_o[9]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h20350802BEE285FB)) \n \\dout_o[9]_i_4 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[4] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[0] ),\n .I5(\\rd_addr_reg_rep_n_0_[1] ),\n .O(\\dout_o[9]_i_4_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\dout_o_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o[0]_i_1_n_0 ),\n .Q(\\dout_o_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dout_o_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o[10]_i_1_n_0 ),\n .Q(p_1_in388_in),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dout_o_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o[11]_i_1_n_0 ),\n .Q(p_1_in322_in),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dout_o_reg[12] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o[12]_i_1_n_0 ),\n .Q(p_1_in256_in),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dout_o_reg[13] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o[13]_i_1_n_0 ),\n .Q(p_1_in190_in),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dout_o_reg[14] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o[14]_i_1_n_0 ),\n .Q(p_1_in124_in),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dout_o_reg[15] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o[15]_i_1_n_0 ),\n .Q(p_1_in),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dout_o_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o[1]_i_1_n_0 ),\n .Q(p_2_in456_in),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dout_o_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o[2]_i_1_n_0 ),\n .Q(p_2_in390_in),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dout_o_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o[3]_i_1_n_0 ),\n .Q(p_2_in324_in),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dout_o_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o[4]_i_1_n_0 ),\n .Q(p_2_in258_in),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dout_o_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o[5]_i_1_n_0 ),\n .Q(p_2_in192_in),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dout_o_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o[6]_i_1_n_0 ),\n .Q(p_2_in126_in),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dout_o_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o[7]_i_1_n_0 ),\n .Q(p_2_in),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dout_o_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o[8]_i_1_n_0 ),\n .Q(p_1_in520_in),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\dout_o_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o[9]_i_1_n_0 ),\n .Q(p_1_in454_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair683\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[0].compare_data_fall0_r1[0]_i_1 \n (.I0(p_2_in126_in),\n .I1(p_0_in94_in),\n .I2(p_1_in124_in),\n .O(\\gen_mux_rd[0].compare_data_fall0_r1_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair636\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[0].compare_data_fall1_r1[0]_i_1 \n (.I0(p_2_in258_in),\n .I1(p_0_in94_in),\n .I2(p_1_in256_in),\n .O(\\gen_mux_rd[0].compare_data_fall1_r1_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair690\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[0].compare_data_fall2_r1[0]_i_1 \n (.I0(p_2_in390_in),\n .I1(p_0_in94_in),\n .I2(p_1_in388_in),\n .O(\\gen_mux_rd[0].compare_data_fall2_r1_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair659\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[0].compare_data_fall3_r1[0]_i_1 \n (.I0(\\dout_o_reg_n_0_[0] ),\n .I1(p_0_in94_in),\n .I2(p_1_in520_in),\n .O(\\gen_mux_rd[0].compare_data_fall3_r1_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair644\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[0].compare_data_rise0_r1[0]_i_1 \n (.I0(p_2_in),\n .I1(p_0_in94_in),\n .I2(p_1_in),\n .O(\\gen_mux_rd[0].compare_data_rise0_r1_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair679\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[0].compare_data_rise1_r1[0]_i_1 \n (.I0(p_2_in192_in),\n .I1(p_0_in94_in),\n .I2(p_1_in190_in),\n .O(\\gen_mux_rd[0].compare_data_rise1_r1_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair635\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[0].compare_data_rise2_r1[0]_i_1 \n (.I0(p_2_in324_in),\n .I1(p_0_in94_in),\n .I2(p_1_in322_in),\n .O(\\gen_mux_rd[0].compare_data_rise2_r1_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair672\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[0].compare_data_rise3_r1[0]_i_1 \n (.I0(p_2_in456_in),\n .I1(p_0_in94_in),\n .I2(p_1_in454_in),\n .O(\\gen_mux_rd[0].compare_data_rise3_r1_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair688\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[1].compare_data_fall0_r1[1]_i_1 \n (.I0(p_2_in126_in),\n .I1(p_0_in98_in),\n .I2(p_1_in124_in),\n .O(\\gen_mux_rd[1].compare_data_fall0_r1_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair685\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[1].compare_data_fall1_r1[1]_i_1 \n (.I0(p_2_in258_in),\n .I1(p_0_in98_in),\n .I2(p_1_in256_in),\n .O(\\gen_mux_rd[1].compare_data_fall1_r1_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair692\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[1].compare_data_fall2_r1[1]_i_1 \n (.I0(p_2_in390_in),\n .I1(p_0_in98_in),\n .I2(p_1_in388_in),\n .O(\\gen_mux_rd[1].compare_data_fall2_r1_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair638\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[1].compare_data_fall3_r1[1]_i_1 \n (.I0(\\dout_o_reg_n_0_[0] ),\n .I1(p_0_in98_in),\n .I2(p_1_in520_in),\n .O(\\gen_mux_rd[1].compare_data_fall3_r1_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair687\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[1].compare_data_rise0_r1[1]_i_1 \n (.I0(p_2_in),\n .I1(p_0_in98_in),\n .I2(p_1_in),\n .O(\\gen_mux_rd[1].compare_data_rise0_r1_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair648\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[1].compare_data_rise1_r1[1]_i_1 \n (.I0(p_2_in192_in),\n .I1(p_0_in98_in),\n .I2(p_1_in190_in),\n .O(\\gen_mux_rd[1].compare_data_rise1_r1_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair691\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[1].compare_data_rise2_r1[1]_i_1 \n (.I0(p_2_in324_in),\n .I1(p_0_in98_in),\n .I2(p_1_in322_in),\n .O(\\gen_mux_rd[1].compare_data_rise2_r1_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair677\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[1].compare_data_rise3_r1[1]_i_1 \n (.I0(p_2_in456_in),\n .I1(p_0_in98_in),\n .I2(p_1_in454_in),\n .O(\\gen_mux_rd[1].compare_data_rise3_r1_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair662\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[2].compare_data_fall0_r1[2]_i_1 \n (.I0(p_2_in126_in),\n .I1(p_0_in102_in),\n .I2(p_1_in124_in),\n .O(\\gen_mux_rd[2].compare_data_fall0_r1_reg[2] ));\n (* SOFT_HLUTNM = \"soft_lutpair640\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[2].compare_data_fall2_r1[2]_i_1 \n (.I0(p_2_in390_in),\n .I1(p_0_in102_in),\n .I2(p_1_in388_in),\n .O(\\gen_mux_rd[2].compare_data_fall2_r1_reg[2] ));\n (* SOFT_HLUTNM = \"soft_lutpair684\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[2].compare_data_fall3_r1[2]_i_1 \n (.I0(\\dout_o_reg_n_0_[0] ),\n .I1(p_0_in102_in),\n .I2(p_1_in520_in),\n .O(\\gen_mux_rd[2].compare_data_fall3_r1_reg[2] ));\n (* SOFT_HLUTNM = \"soft_lutpair661\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[2].compare_data_rise0_r1[2]_i_1 \n (.I0(p_2_in),\n .I1(p_0_in102_in),\n .I2(p_1_in),\n .O(\\gen_mux_rd[2].compare_data_rise0_r1_reg[2] ));\n (* SOFT_HLUTNM = \"soft_lutpair652\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[2].compare_data_rise1_r1[2]_i_1 \n (.I0(p_2_in192_in),\n .I1(p_0_in102_in),\n .I2(p_1_in190_in),\n .O(\\gen_mux_rd[2].compare_data_rise1_r1_reg[2] ));\n (* SOFT_HLUTNM = \"soft_lutpair650\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[2].compare_data_rise2_r1[2]_i_1 \n (.I0(p_2_in324_in),\n .I1(p_0_in102_in),\n .I2(p_1_in322_in),\n .O(\\gen_mux_rd[2].compare_data_rise2_r1_reg[2] ));\n (* SOFT_HLUTNM = \"soft_lutpair655\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[2].compare_data_rise3_r1[2]_i_1 \n (.I0(p_2_in456_in),\n .I1(p_0_in102_in),\n .I2(p_1_in454_in),\n .O(\\gen_mux_rd[2].compare_data_rise3_r1_reg[2] ));\n (* SOFT_HLUTNM = \"soft_lutpair664\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[3].compare_data_fall0_r1[3]_i_1 \n (.I0(p_2_in126_in),\n .I1(p_0_in106_in),\n .I2(p_1_in124_in),\n .O(\\gen_mux_rd[3].compare_data_fall0_r1_reg[3] ));\n (* SOFT_HLUTNM = \"soft_lutpair689\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[3].compare_data_fall1_r1[3]_i_1 \n (.I0(p_2_in258_in),\n .I1(p_0_in106_in),\n .I2(p_1_in256_in),\n .O(\\gen_mux_rd[3].compare_data_fall1_r1_reg[3] ));\n (* SOFT_HLUTNM = \"soft_lutpair642\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[3].compare_data_fall3_r1[3]_i_1 \n (.I0(\\dout_o_reg_n_0_[0] ),\n .I1(p_0_in106_in),\n .I2(p_1_in520_in),\n .O(\\gen_mux_rd[3].compare_data_fall3_r1_reg[3] ));\n (* SOFT_HLUTNM = \"soft_lutpair645\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[3].compare_data_rise0_r1[3]_i_1 \n (.I0(p_2_in),\n .I1(p_0_in106_in),\n .I2(p_1_in),\n .O(\\gen_mux_rd[3].compare_data_rise0_r1_reg[3] ));\n (* SOFT_HLUTNM = \"soft_lutpair676\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[3].compare_data_rise1_r1[3]_i_1 \n (.I0(p_2_in192_in),\n .I1(p_0_in106_in),\n .I2(p_1_in190_in),\n .O(\\gen_mux_rd[3].compare_data_rise1_r1_reg[3] ));\n (* SOFT_HLUTNM = \"soft_lutpair682\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[3].compare_data_rise2_r1[3]_i_1 \n (.I0(p_2_in324_in),\n .I1(p_0_in106_in),\n .I2(p_1_in322_in),\n .O(\\gen_mux_rd[3].compare_data_rise2_r1_reg[3] ));\n (* SOFT_HLUTNM = \"soft_lutpair675\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[3].compare_data_rise3_r1[3]_i_1 \n (.I0(p_2_in456_in),\n .I1(p_0_in106_in),\n .I2(p_1_in454_in),\n .O(\\gen_mux_rd[3].compare_data_rise3_r1_reg[3] ));\n (* SOFT_HLUTNM = \"soft_lutpair683\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[4].compare_data_fall0_r1[4]_i_1 \n (.I0(p_2_in126_in),\n .I1(p_0_in110_in),\n .I2(p_1_in124_in),\n .O(\\gen_mux_rd[4].compare_data_fall0_r1_reg[4] ));\n (* SOFT_HLUTNM = \"soft_lutpair637\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[4].compare_data_fall1_r1[4]_i_1 \n (.I0(p_2_in258_in),\n .I1(p_0_in110_in),\n .I2(p_1_in256_in),\n .O(\\gen_mux_rd[4].compare_data_fall1_r1_reg[4] ));\n (* SOFT_HLUTNM = \"soft_lutpair693\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[4].compare_data_fall2_r1[4]_i_1 \n (.I0(p_2_in390_in),\n .I1(p_0_in110_in),\n .I2(p_1_in388_in),\n .O(\\gen_mux_rd[4].compare_data_fall2_r1_reg[4] ));\n (* SOFT_HLUTNM = \"soft_lutpair658\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[4].compare_data_fall3_r1[4]_i_1 \n (.I0(\\dout_o_reg_n_0_[0] ),\n .I1(p_0_in110_in),\n .I2(p_1_in520_in),\n .O(\\gen_mux_rd[4].compare_data_fall3_r1_reg[4] ));\n (* SOFT_HLUTNM = \"soft_lutpair646\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[4].compare_data_rise0_r1[4]_i_1 \n (.I0(p_2_in),\n .I1(p_0_in110_in),\n .I2(p_1_in),\n .O(\\gen_mux_rd[4].compare_data_rise0_r1_reg[4] ));\n (* SOFT_HLUTNM = \"soft_lutpair681\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[4].compare_data_rise1_r1[4]_i_1 \n (.I0(p_2_in192_in),\n .I1(p_0_in110_in),\n .I2(p_1_in190_in),\n .O(\\gen_mux_rd[4].compare_data_rise1_r1_reg[4] ));\n (* SOFT_HLUTNM = \"soft_lutpair656\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[4].compare_data_rise2_r1[4]_i_1 \n (.I0(p_2_in324_in),\n .I1(p_0_in110_in),\n .I2(p_1_in322_in),\n .O(\\gen_mux_rd[4].compare_data_rise2_r1_reg[4] ));\n (* SOFT_HLUTNM = \"soft_lutpair669\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[4].compare_data_rise3_r1[4]_i_1 \n (.I0(p_2_in456_in),\n .I1(p_0_in110_in),\n .I2(p_1_in454_in),\n .O(\\gen_mux_rd[4].compare_data_rise3_r1_reg[4] ));\n (* SOFT_HLUTNM = \"soft_lutpair688\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[5].compare_data_fall0_r1[5]_i_1 \n (.I0(p_2_in126_in),\n .I1(p_0_in114_in),\n .I2(p_1_in124_in),\n .O(\\gen_mux_rd[5].compare_data_fall0_r1_reg[5] ));\n (* SOFT_HLUTNM = \"soft_lutpair689\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[5].compare_data_fall1_r1[5]_i_1 \n (.I0(p_2_in258_in),\n .I1(p_0_in114_in),\n .I2(p_1_in256_in),\n .O(\\gen_mux_rd[5].compare_data_fall1_r1_reg[5] ));\n (* SOFT_HLUTNM = \"soft_lutpair690\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[5].compare_data_fall2_r1[5]_i_1 \n (.I0(p_2_in390_in),\n .I1(p_0_in114_in),\n .I2(p_1_in388_in),\n .O(\\gen_mux_rd[5].compare_data_fall2_r1_reg[5] ));\n (* SOFT_HLUTNM = \"soft_lutpair639\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[5].compare_data_fall3_r1[5]_i_1 \n (.I0(\\dout_o_reg_n_0_[0] ),\n .I1(p_0_in114_in),\n .I2(p_1_in520_in),\n .O(\\gen_mux_rd[5].compare_data_fall3_r1_reg[5] ));\n (* SOFT_HLUTNM = \"soft_lutpair687\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[5].compare_data_rise0_r1[5]_i_1 \n (.I0(p_2_in),\n .I1(p_0_in114_in),\n .I2(p_1_in),\n .O(\\gen_mux_rd[5].compare_data_rise0_r1_reg[5] ));\n (* SOFT_HLUTNM = \"soft_lutpair649\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[5].compare_data_rise1_r1[5]_i_1 \n (.I0(p_2_in192_in),\n .I1(p_0_in114_in),\n .I2(p_1_in190_in),\n .O(\\gen_mux_rd[5].compare_data_rise1_r1_reg[5] ));\n (* SOFT_HLUTNM = \"soft_lutpair691\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[5].compare_data_rise2_r1[5]_i_1 \n (.I0(p_2_in324_in),\n .I1(p_0_in114_in),\n .I2(p_1_in322_in),\n .O(\\gen_mux_rd[5].compare_data_rise2_r1_reg[5] ));\n (* SOFT_HLUTNM = \"soft_lutpair680\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[5].compare_data_rise3_r1[5]_i_1 \n (.I0(p_2_in456_in),\n .I1(p_0_in114_in),\n .I2(p_1_in454_in),\n .O(\\gen_mux_rd[5].compare_data_rise3_r1_reg[5] ));\n (* SOFT_HLUTNM = \"soft_lutpair665\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[6].compare_data_fall0_r1[6]_i_1 \n (.I0(p_2_in126_in),\n .I1(p_0_in118_in),\n .I2(p_1_in124_in),\n .O(\\gen_mux_rd[6].compare_data_fall0_r1_reg[6] ));\n (* SOFT_HLUTNM = \"soft_lutpair641\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[6].compare_data_fall2_r1[6]_i_1 \n (.I0(p_2_in390_in),\n .I1(p_0_in118_in),\n .I2(p_1_in388_in),\n .O(\\gen_mux_rd[6].compare_data_fall2_r1_reg[6] ));\n (* SOFT_HLUTNM = \"soft_lutpair684\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[6].compare_data_fall3_r1[6]_i_1 \n (.I0(\\dout_o_reg_n_0_[0] ),\n .I1(p_0_in118_in),\n .I2(p_1_in520_in),\n .O(\\gen_mux_rd[6].compare_data_fall3_r1_reg[6] ));\n (* SOFT_HLUTNM = \"soft_lutpair660\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[6].compare_data_rise0_r1[6]_i_1 \n (.I0(p_2_in),\n .I1(p_0_in118_in),\n .I2(p_1_in),\n .O(\\gen_mux_rd[6].compare_data_rise0_r1_reg[6] ));\n (* SOFT_HLUTNM = \"soft_lutpair653\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[6].compare_data_rise1_r1[6]_i_1 \n (.I0(p_2_in192_in),\n .I1(p_0_in118_in),\n .I2(p_1_in190_in),\n .O(\\gen_mux_rd[6].compare_data_rise1_r1_reg[6] ));\n (* SOFT_HLUTNM = \"soft_lutpair651\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[6].compare_data_rise2_r1[6]_i_1 \n (.I0(p_2_in324_in),\n .I1(p_0_in118_in),\n .I2(p_1_in322_in),\n .O(\\gen_mux_rd[6].compare_data_rise2_r1_reg[6] ));\n (* SOFT_HLUTNM = \"soft_lutpair654\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[6].compare_data_rise3_r1[6]_i_1 \n (.I0(p_2_in456_in),\n .I1(p_0_in118_in),\n .I2(p_1_in454_in),\n .O(\\gen_mux_rd[6].compare_data_rise3_r1_reg[6] ));\n (* SOFT_HLUTNM = \"soft_lutpair663\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[7].compare_data_fall0_r1[7]_i_1 \n (.I0(p_2_in126_in),\n .I1(p_0_in122_in),\n .I2(p_1_in124_in),\n .O(\\gen_mux_rd[7].compare_data_fall0_r1_reg[7] ));\n (* SOFT_HLUTNM = \"soft_lutpair685\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[7].compare_data_fall1_r1[7]_i_1 \n (.I0(p_2_in258_in),\n .I1(p_0_in122_in),\n .I2(p_1_in256_in),\n .O(\\gen_mux_rd[7].compare_data_fall1_r1_reg[7] ));\n (* SOFT_HLUTNM = \"soft_lutpair643\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[7].compare_data_fall3_r1[7]_i_1 \n (.I0(\\dout_o_reg_n_0_[0] ),\n .I1(p_0_in122_in),\n .I2(p_1_in520_in),\n .O(\\gen_mux_rd[7].compare_data_fall3_r1_reg[7] ));\n (* SOFT_HLUTNM = \"soft_lutpair647\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[7].compare_data_rise0_r1[7]_i_1 \n (.I0(p_2_in),\n .I1(p_0_in122_in),\n .I2(p_1_in),\n .O(\\gen_mux_rd[7].compare_data_rise0_r1_reg[7] ));\n (* SOFT_HLUTNM = \"soft_lutpair671\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[7].compare_data_rise1_r1[7]_i_1 \n (.I0(p_2_in192_in),\n .I1(p_0_in122_in),\n .I2(p_1_in190_in),\n .O(\\gen_mux_rd[7].compare_data_rise1_r1_reg[7] ));\n (* SOFT_HLUTNM = \"soft_lutpair678\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[7].compare_data_rise2_r1[7]_i_1 \n (.I0(p_2_in324_in),\n .I1(p_0_in122_in),\n .I2(p_1_in322_in),\n .O(\\gen_mux_rd[7].compare_data_rise2_r1_reg[7] ));\n (* SOFT_HLUTNM = \"soft_lutpair670\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[7].compare_data_rise3_r1[7]_i_1 \n (.I0(p_2_in456_in),\n .I1(p_0_in122_in),\n .I2(p_1_in454_in),\n .O(\\gen_mux_rd[7].compare_data_rise3_r1_reg[7] ));\n FDRE #(\n .INIT(1'b0)) \n phy_if_empty_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .Q(\\rd_addr_reg[0]_0 ),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h1)) \n \\rd_addr[0]_i_1 \n (.I0(\\rd_addr_reg_n_0_[0] ),\n .I1(\\rd_addr[7]_i_5_n_0 ),\n .O(p_1_in__0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair673\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\rd_addr[1]_i_1 \n (.I0(\\rd_addr_reg_n_0_[0] ),\n .I1(\\rd_addr_reg_n_0_[1] ),\n .O(p_1_in__0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair657\" *) \n LUT4 #(\n .INIT(16'h1540)) \n \\rd_addr[2]_i_1 \n (.I0(\\rd_addr[7]_i_5_n_0 ),\n .I1(\\rd_addr_reg_n_0_[0] ),\n .I2(\\rd_addr_reg_n_0_[1] ),\n .I3(\\rd_addr_reg_n_0_[2] ),\n .O(p_1_in__0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair657\" *) \n LUT5 #(\n .INIT(32'h15554000)) \n \\rd_addr[3]_i_1 \n (.I0(\\rd_addr[7]_i_5_n_0 ),\n .I1(\\rd_addr_reg_n_0_[1] ),\n .I2(\\rd_addr_reg_n_0_[0] ),\n .I3(\\rd_addr_reg_n_0_[2] ),\n .I4(Q),\n .O(p_1_in__0[3]));\n LUT6 #(\n .INIT(64'h1555555540000000)) \n \\rd_addr[4]_i_1 \n (.I0(\\rd_addr[7]_i_5_n_0 ),\n .I1(\\rd_addr_reg_n_0_[2] ),\n .I2(\\rd_addr_reg_n_0_[0] ),\n .I3(\\rd_addr_reg_n_0_[1] ),\n .I4(Q),\n .I5(\\rd_addr_reg_n_0_[4] ),\n .O(p_1_in__0[4]));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n \\rd_addr[5]_i_1 \n (.I0(\\rd_addr_reg_n_0_[5] ),\n .I1(Q),\n .I2(\\rd_addr_reg_n_0_[1] ),\n .I3(\\rd_addr_reg_n_0_[0] ),\n .I4(\\rd_addr_reg_n_0_[2] ),\n .I5(\\rd_addr_reg_n_0_[4] ),\n .O(p_1_in__0[5]));\n (* SOFT_HLUTNM = \"soft_lutpair674\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\rd_addr[6]_i_1 \n (.I0(\\rd_addr_reg_n_0_[6] ),\n .I1(\\rd_addr[7]_i_4_n_0 ),\n .O(p_1_in__0[6]));\n (* SOFT_HLUTNM = \"soft_lutpair674\" *) \n LUT4 #(\n .INIT(16'h006A)) \n \\rd_addr[7]_i_3 \n (.I0(\\rd_addr_reg_n_0_[7] ),\n .I1(\\rd_addr[7]_i_4_n_0 ),\n .I2(\\rd_addr_reg_n_0_[6] ),\n .I3(\\rd_addr[7]_i_5_n_0 ),\n .O(p_1_in__0[7]));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\rd_addr[7]_i_4 \n (.I0(\\rd_addr_reg_n_0_[5] ),\n .I1(\\rd_addr_reg_n_0_[4] ),\n .I2(\\rd_addr_reg_n_0_[2] ),\n .I3(\\rd_addr_reg_n_0_[0] ),\n .I4(\\rd_addr_reg_n_0_[1] ),\n .I5(Q),\n .O(\\rd_addr[7]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h00000010)) \n \\rd_addr[7]_i_5 \n (.I0(\\rd_addr[7]_i_6_n_0 ),\n .I1(\\rd_addr_reg_n_0_[5] ),\n .I2(\\rd_addr_reg_n_0_[7] ),\n .I3(\\rd_addr_reg_n_0_[6] ),\n .I4(\\rd_addr_reg[3]_0 ),\n .O(\\rd_addr[7]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair673\" *) \n LUT4 #(\n .INIT(16'hEFFF)) \n \\rd_addr[7]_i_6 \n (.I0(\\rd_addr_reg_n_0_[1] ),\n .I1(\\rd_addr_reg_n_0_[0] ),\n .I2(\\rd_addr_reg_n_0_[4] ),\n .I3(\\rd_addr_reg_n_0_[2] ),\n .O(\\rd_addr[7]_i_6_n_0 ));\n (* RAM_STYLE = \"distributed\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_addr_reg[0] \n (.C(CLK),\n .CE(E),\n .D(p_1_in__0[0]),\n .Q(\\rd_addr_reg_n_0_[0] ),\n .R(SR));\n (* RAM_STYLE = \"distributed\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_addr_reg[1] \n (.C(CLK),\n .CE(E),\n .D(p_1_in__0[1]),\n .Q(\\rd_addr_reg_n_0_[1] ),\n .R(SR));\n (* RAM_STYLE = \"distributed\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_addr_reg[2] \n (.C(CLK),\n .CE(E),\n .D(p_1_in__0[2]),\n .Q(\\rd_addr_reg_n_0_[2] ),\n .R(SR));\n (* RAM_STYLE = \"distributed\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_addr_reg[3] \n (.C(CLK),\n .CE(E),\n .D(p_1_in__0[3]),\n .Q(Q),\n .R(SR));\n (* RAM_STYLE = \"distributed\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_addr_reg[4] \n (.C(CLK),\n .CE(E),\n .D(p_1_in__0[4]),\n .Q(\\rd_addr_reg_n_0_[4] ),\n .R(SR));\n (* RAM_STYLE = \"distributed\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_addr_reg[5] \n (.C(CLK),\n .CE(E),\n .D(p_1_in__0[5]),\n .Q(\\rd_addr_reg_n_0_[5] ),\n .R(SR));\n (* RAM_STYLE = \"distributed\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_addr_reg[6] \n (.C(CLK),\n .CE(E),\n .D(p_1_in__0[6]),\n .Q(\\rd_addr_reg_n_0_[6] ),\n .R(SR));\n (* RAM_STYLE = \"distributed\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_addr_reg[7] \n (.C(CLK),\n .CE(E),\n .D(p_1_in__0[7]),\n .Q(\\rd_addr_reg_n_0_[7] ),\n .R(SR));\n (* equivalent_register_removal = \"no\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_addr_reg_rep[0] \n (.C(CLK),\n .CE(E),\n .D(p_1_in__0[0]),\n .Q(\\rd_addr_reg_rep_n_0_[0] ),\n .R(SR));\n (* equivalent_register_removal = \"no\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_addr_reg_rep[1] \n (.C(CLK),\n .CE(E),\n .D(p_1_in__0[1]),\n .Q(\\rd_addr_reg_rep_n_0_[1] ),\n .R(SR));\n (* equivalent_register_removal = \"no\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_addr_reg_rep[2] \n (.C(CLK),\n .CE(E),\n .D(p_1_in__0[2]),\n .Q(\\rd_addr_reg_rep_n_0_[2] ),\n .R(SR));\n (* equivalent_register_removal = \"no\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_addr_reg_rep[3] \n (.C(CLK),\n .CE(E),\n .D(p_1_in__0[3]),\n .Q(\\rd_addr_reg_rep_n_0_[3] ),\n .R(SR));\n (* equivalent_register_removal = \"no\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_addr_reg_rep[4] \n (.C(CLK),\n .CE(E),\n .D(p_1_in__0[4]),\n .Q(\\rd_addr_reg_rep_n_0_[4] ),\n .R(SR));\n (* equivalent_register_removal = \"no\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_addr_reg_rep[5] \n (.C(CLK),\n .CE(E),\n .D(p_1_in__0[5]),\n .Q(\\rd_addr_reg_rep_n_0_[5] ),\n .R(SR));\n (* equivalent_register_removal = \"no\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_addr_reg_rep[6] \n (.C(CLK),\n .CE(E),\n .D(p_1_in__0[6]),\n .Q(\\rd_addr_reg_rep_n_0_[6] ),\n .R(SR));\n (* equivalent_register_removal = \"no\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_addr_reg_rep[7] \n (.C(CLK),\n .CE(E),\n .D(p_1_in__0[7]),\n .Q(\\rd_addr_reg_rep_n_0_[7] ),\n .R(SR));\n FDRE #(\n .INIT(1'b0)) \n \\victim_sel_rotate.sel_reg[24] \n (.C(CLK),\n .CE(1'b1),\n .D(D[0]),\n .Q(p_0_in94_in),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE #(\n .INIT(1'b0)) \n \\victim_sel_rotate.sel_reg[25] \n (.C(CLK),\n .CE(1'b1),\n .D(D[1]),\n .Q(p_0_in98_in),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE #(\n .INIT(1'b0)) \n \\victim_sel_rotate.sel_reg[26] \n (.C(CLK),\n .CE(1'b1),\n .D(D[2]),\n .Q(p_0_in102_in),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE #(\n .INIT(1'b0)) \n \\victim_sel_rotate.sel_reg[27] \n (.C(CLK),\n .CE(1'b1),\n .D(D[3]),\n .Q(p_0_in106_in),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE #(\n .INIT(1'b0)) \n \\victim_sel_rotate.sel_reg[28] \n (.C(CLK),\n .CE(1'b1),\n .D(D[4]),\n .Q(p_0_in110_in),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE #(\n .INIT(1'b0)) \n \\victim_sel_rotate.sel_reg[29] \n (.C(CLK),\n .CE(1'b1),\n .D(D[5]),\n .Q(p_0_in114_in),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE #(\n .INIT(1'b0)) \n \\victim_sel_rotate.sel_reg[30] \n (.C(CLK),\n .CE(1'b1),\n .D(D[6]),\n .Q(p_0_in118_in),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE #(\n .INIT(1'b0)) \n \\victim_sel_rotate.sel_reg[31] \n (.C(CLK),\n .CE(1'b1),\n .D(D[7]),\n .Q(p_0_in122_in),\n .R(rstdiv0_sync_r1_reg_rep__19));\n (* SOFT_HLUTNM = \"soft_lutpair636\" *) \n LUT5 #(\n .INIT(32'hE2000000)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[120]_i_1 \n (.I0(p_1_in256_in),\n .I1(p_0_in94_in),\n .I2(p_2_in258_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[120] ));\n (* SOFT_HLUTNM = \"soft_lutpair666\" *) \n LUT4 #(\n .INIT(16'hA808)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[121]_i_1 \n (.I0(wrcal_done_reg),\n .I1(p_1_in256_in),\n .I2(p_0_in98_in),\n .I3(p_2_in258_in),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[121] ));\n (* SOFT_HLUTNM = \"soft_lutpair686\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[122]_i_1 \n (.I0(p_2_in258_in),\n .I1(p_0_in102_in),\n .I2(p_1_in256_in),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[122] ));\n (* SOFT_HLUTNM = \"soft_lutpair666\" *) \n LUT4 #(\n .INIT(16'hA808)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[123]_i_1 \n (.I0(wrcal_done_reg),\n .I1(p_1_in256_in),\n .I2(p_0_in106_in),\n .I3(p_2_in258_in),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[123] ));\n (* SOFT_HLUTNM = \"soft_lutpair637\" *) \n LUT5 #(\n .INIT(32'hE2000000)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[124]_i_1 \n (.I0(p_1_in256_in),\n .I1(p_0_in110_in),\n .I2(p_2_in258_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[124] ));\n (* SOFT_HLUTNM = \"soft_lutpair667\" *) \n LUT4 #(\n .INIT(16'hA808)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[125]_i_1 \n (.I0(wrcal_done_reg),\n .I1(p_1_in256_in),\n .I2(p_0_in114_in),\n .I3(p_2_in258_in),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[125] ));\n (* SOFT_HLUTNM = \"soft_lutpair686\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[126]_i_1 \n (.I0(p_2_in258_in),\n .I1(p_0_in118_in),\n .I2(p_1_in256_in),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[126] ));\n (* SOFT_HLUTNM = \"soft_lutpair667\" *) \n LUT4 #(\n .INIT(16'hA808)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[127]_i_1 \n (.I0(wrcal_done_reg),\n .I1(p_1_in256_in),\n .I2(p_0_in122_in),\n .I3(p_2_in258_in),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[127] ));\n (* SOFT_HLUTNM = \"soft_lutpair635\" *) \n LUT5 #(\n .INIT(32'hB800FFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[152]_i_1 \n (.I0(p_2_in324_in),\n .I1(p_0_in94_in),\n .I2(p_1_in322_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[152] ));\n LUT6 #(\n .INIT(64'hE200000000000000)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[153]_i_1 \n (.I0(p_1_in322_in),\n .I1(p_0_in98_in),\n .I2(p_2_in324_in),\n .I3(oclkdelay_calib_done_r_reg),\n .I4(wrcal_done_reg),\n .I5(rdlvl_stg1_done_int_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[153] ));\n (* SOFT_HLUTNM = \"soft_lutpair650\" *) \n LUT5 #(\n .INIT(32'hE2FFFFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[154]_i_1 \n (.I0(p_1_in322_in),\n .I1(p_0_in102_in),\n .I2(p_2_in324_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[154] ));\n (* SOFT_HLUTNM = \"soft_lutpair682\" *) \n LUT4 #(\n .INIT(16'hE2FF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[155]_i_1 \n (.I0(p_1_in322_in),\n .I1(p_0_in106_in),\n .I2(p_2_in324_in),\n .I3(rdlvl_stg1_done_int_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[155] ));\n (* SOFT_HLUTNM = \"soft_lutpair656\" *) \n LUT5 #(\n .INIT(32'hB800FFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[156]_i_2 \n (.I0(p_2_in324_in),\n .I1(p_0_in110_in),\n .I2(p_1_in322_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[156] ));\n LUT6 #(\n .INIT(64'hE200000000000000)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[157]_i_1 \n (.I0(p_1_in322_in),\n .I1(p_0_in114_in),\n .I2(p_2_in324_in),\n .I3(oclkdelay_calib_done_r_reg),\n .I4(wrcal_done_reg),\n .I5(rdlvl_stg1_done_int_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[157] ));\n (* SOFT_HLUTNM = \"soft_lutpair651\" *) \n LUT5 #(\n .INIT(32'hE2FFFFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[158]_i_2 \n (.I0(p_1_in322_in),\n .I1(p_0_in118_in),\n .I2(p_2_in324_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[158] ));\n (* SOFT_HLUTNM = \"soft_lutpair678\" *) \n LUT4 #(\n .INIT(16'hE2FF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[159]_i_1 \n (.I0(p_1_in322_in),\n .I1(p_0_in122_in),\n .I2(p_2_in324_in),\n .I3(rdlvl_stg1_done_int_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[159] ));\n (* SOFT_HLUTNM = \"soft_lutpair668\" *) \n LUT4 #(\n .INIT(16'hA808)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[184]_i_1 \n (.I0(wrcal_done_reg),\n .I1(p_1_in388_in),\n .I2(p_0_in94_in),\n .I3(p_2_in390_in),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[184] ));\n LUT6 #(\n .INIT(64'hF7FFF77777777777)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[185]_i_1 \n (.I0(oclkdelay_calib_done_r_reg),\n .I1(wrcal_done_reg),\n .I2(p_2_in390_in),\n .I3(p_0_in98_in),\n .I4(p_1_in388_in),\n .I5(rdlvl_stg1_done_int_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[185] ));\n (* SOFT_HLUTNM = \"soft_lutpair640\" *) \n LUT5 #(\n .INIT(32'hE2000000)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[186]_i_1 \n (.I0(p_1_in388_in),\n .I1(p_0_in102_in),\n .I2(p_2_in390_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] ));\n (* SOFT_HLUTNM = \"soft_lutpair692\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[187]_i_1 \n (.I0(p_2_in390_in),\n .I1(p_0_in106_in),\n .I2(p_1_in388_in),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187] ));\n (* SOFT_HLUTNM = \"soft_lutpair668\" *) \n LUT4 #(\n .INIT(16'hA808)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[188]_i_1 \n (.I0(wrcal_done_reg),\n .I1(p_1_in388_in),\n .I2(p_0_in110_in),\n .I3(p_2_in390_in),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[188] ));\n LUT6 #(\n .INIT(64'hF7FFF77777777777)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[189]_i_1 \n (.I0(oclkdelay_calib_done_r_reg),\n .I1(wrcal_done_reg),\n .I2(p_2_in390_in),\n .I3(p_0_in114_in),\n .I4(p_1_in388_in),\n .I5(rdlvl_stg1_done_int_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[189] ));\n (* SOFT_HLUTNM = \"soft_lutpair641\" *) \n LUT5 #(\n .INIT(32'hE2000000)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_1 \n (.I0(p_1_in388_in),\n .I1(p_0_in118_in),\n .I2(p_2_in390_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[190] ));\n (* SOFT_HLUTNM = \"soft_lutpair693\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[191]_i_2 \n (.I0(p_2_in390_in),\n .I1(p_0_in122_in),\n .I2(p_1_in388_in),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] ));\n (* SOFT_HLUTNM = \"soft_lutpair672\" *) \n LUT4 #(\n .INIT(16'hE2FF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[216]_i_1 \n (.I0(p_1_in454_in),\n .I1(p_0_in94_in),\n .I2(p_2_in456_in),\n .I3(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[216] ));\n (* SOFT_HLUTNM = \"soft_lutpair677\" *) \n LUT4 #(\n .INIT(16'hE2FF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[217]_i_1 \n (.I0(p_1_in454_in),\n .I1(p_0_in98_in),\n .I2(p_2_in456_in),\n .I3(rdlvl_stg1_done_int_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[217] ));\n (* SOFT_HLUTNM = \"soft_lutpair655\" *) \n LUT5 #(\n .INIT(32'hB800FFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[218]_i_1 \n (.I0(p_2_in456_in),\n .I1(p_0_in102_in),\n .I2(p_1_in454_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[218] ));\n (* SOFT_HLUTNM = \"soft_lutpair675\" *) \n LUT4 #(\n .INIT(16'hE2FF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[219]_i_1 \n (.I0(p_1_in454_in),\n .I1(p_0_in106_in),\n .I2(p_2_in456_in),\n .I3(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[219] ));\n (* SOFT_HLUTNM = \"soft_lutpair669\" *) \n LUT4 #(\n .INIT(16'hE2FF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[220]_i_1 \n (.I0(p_1_in454_in),\n .I1(p_0_in110_in),\n .I2(p_2_in456_in),\n .I3(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[220] ));\n (* SOFT_HLUTNM = \"soft_lutpair680\" *) \n LUT4 #(\n .INIT(16'hE2FF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[221]_i_2 \n (.I0(p_1_in454_in),\n .I1(p_0_in114_in),\n .I2(p_2_in456_in),\n .I3(rdlvl_stg1_done_int_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] ));\n (* SOFT_HLUTNM = \"soft_lutpair654\" *) \n LUT5 #(\n .INIT(32'hB800FFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_2 \n (.I0(p_2_in456_in),\n .I1(p_0_in118_in),\n .I2(p_1_in454_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[222] ));\n (* SOFT_HLUTNM = \"soft_lutpair670\" *) \n LUT4 #(\n .INIT(16'hE2FF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[223]_i_2 \n (.I0(p_1_in454_in),\n .I1(p_0_in122_in),\n .I2(p_2_in456_in),\n .I3(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[223] ));\n (* SOFT_HLUTNM = \"soft_lutpair659\" *) \n LUT5 #(\n .INIT(32'hE2000000)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[248]_i_1 \n (.I0(p_1_in520_in),\n .I1(p_0_in94_in),\n .I2(\\dout_o_reg_n_0_[0] ),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[248] ));\n (* SOFT_HLUTNM = \"soft_lutpair638\" *) \n LUT5 #(\n .INIT(32'hE2000000)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[249]_i_1 \n (.I0(p_1_in520_in),\n .I1(p_0_in98_in),\n .I2(\\dout_o_reg_n_0_[0] ),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[249] ));\n (* SOFT_HLUTNM = \"soft_lutpair644\" *) \n LUT5 #(\n .INIT(32'hE2FFFFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[24]_i_1 \n (.I0(p_1_in),\n .I1(p_0_in94_in),\n .I2(p_2_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[24] ));\n (* SOFT_HLUTNM = \"soft_lutpair642\" *) \n LUT5 #(\n .INIT(32'hE2000000)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[251]_i_1 \n (.I0(p_1_in520_in),\n .I1(p_0_in106_in),\n .I2(\\dout_o_reg_n_0_[0] ),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[251] ));\n (* SOFT_HLUTNM = \"soft_lutpair658\" *) \n LUT5 #(\n .INIT(32'hE2000000)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[252]_i_1 \n (.I0(p_1_in520_in),\n .I1(p_0_in110_in),\n .I2(\\dout_o_reg_n_0_[0] ),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[252] ));\n (* SOFT_HLUTNM = \"soft_lutpair639\" *) \n LUT5 #(\n .INIT(32'hE2000000)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[253]_i_1 \n (.I0(p_1_in520_in),\n .I1(p_0_in114_in),\n .I2(\\dout_o_reg_n_0_[0] ),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[253] ));\n (* SOFT_HLUTNM = \"soft_lutpair643\" *) \n LUT5 #(\n .INIT(32'hE2000000)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[255]_i_1 \n (.I0(p_1_in520_in),\n .I1(p_0_in122_in),\n .I2(\\dout_o_reg_n_0_[0] ),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[255] ));\n LUT6 #(\n .INIT(64'hB800B8FFFFFFFFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[25]_i_1 \n (.I0(p_2_in),\n .I1(p_0_in98_in),\n .I2(p_1_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(first_rdlvl_pat_r),\n .I5(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[25] ));\n (* SOFT_HLUTNM = \"soft_lutpair661\" *) \n LUT5 #(\n .INIT(32'hB800FFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[26]_i_1 \n (.I0(p_2_in),\n .I1(p_0_in102_in),\n .I2(p_1_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[26] ));\n (* SOFT_HLUTNM = \"soft_lutpair645\" *) \n LUT5 #(\n .INIT(32'hE2FFFFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[27]_i_1 \n (.I0(p_1_in),\n .I1(p_0_in106_in),\n .I2(p_2_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[27] ));\n (* SOFT_HLUTNM = \"soft_lutpair646\" *) \n LUT5 #(\n .INIT(32'hE2FFFFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[28]_i_1 \n (.I0(p_1_in),\n .I1(p_0_in110_in),\n .I2(p_2_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[28] ));\n LUT6 #(\n .INIT(64'hB800B8FFFFFFFFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[29]_i_1 \n (.I0(p_2_in),\n .I1(p_0_in114_in),\n .I2(p_1_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(first_rdlvl_pat_r),\n .I5(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[29] ));\n (* SOFT_HLUTNM = \"soft_lutpair660\" *) \n LUT5 #(\n .INIT(32'hB800FFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[30]_i_1 \n (.I0(p_2_in),\n .I1(p_0_in118_in),\n .I2(p_1_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[30] ));\n (* SOFT_HLUTNM = \"soft_lutpair647\" *) \n LUT5 #(\n .INIT(32'hE2FFFFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[31]_i_1 \n (.I0(p_1_in),\n .I1(p_0_in122_in),\n .I2(p_2_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[31] ));\n LUT6 #(\n .INIT(64'hC0CCC00088888888)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[57]_i_1 \n (.I0(first_rdlvl_pat_r),\n .I1(wrcal_done_reg),\n .I2(p_2_in126_in),\n .I3(p_0_in98_in),\n .I4(p_1_in124_in),\n .I5(rdlvl_stg1_done_int_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ));\n (* SOFT_HLUTNM = \"soft_lutpair662\" *) \n LUT5 #(\n .INIT(32'hE2000000)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[58]_i_1 \n (.I0(p_1_in124_in),\n .I1(p_0_in102_in),\n .I2(p_2_in126_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[58] ));\n (* SOFT_HLUTNM = \"soft_lutpair664\" *) \n LUT5 #(\n .INIT(32'hE2000000)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[59]_i_1 \n (.I0(p_1_in124_in),\n .I1(p_0_in106_in),\n .I2(p_2_in126_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[59] ));\n LUT6 #(\n .INIT(64'hB8FFB80000000000)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[61]_i_1 \n (.I0(p_2_in126_in),\n .I1(p_0_in114_in),\n .I2(p_1_in124_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(first_rdlvl_pat_r),\n .I5(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[61] ));\n (* SOFT_HLUTNM = \"soft_lutpair665\" *) \n LUT5 #(\n .INIT(32'hE2000000)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[62]_i_1 \n (.I0(p_1_in124_in),\n .I1(p_0_in118_in),\n .I2(p_2_in126_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[62] ));\n (* SOFT_HLUTNM = \"soft_lutpair663\" *) \n LUT5 #(\n .INIT(32'hE2000000)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[63]_i_1 \n (.I0(p_1_in124_in),\n .I1(p_0_in122_in),\n .I2(p_2_in126_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[63] ));\n (* SOFT_HLUTNM = \"soft_lutpair679\" *) \n LUT4 #(\n .INIT(16'hE2FF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[88]_i_1 \n (.I0(p_1_in190_in),\n .I1(p_0_in94_in),\n .I2(p_2_in192_in),\n .I3(rdlvl_stg1_done_int_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[88] ));\n (* SOFT_HLUTNM = \"soft_lutpair648\" *) \n LUT5 #(\n .INIT(32'hE2FFFFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[89]_i_1 \n (.I0(p_1_in190_in),\n .I1(p_0_in98_in),\n .I2(p_2_in192_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[89] ));\n (* SOFT_HLUTNM = \"soft_lutpair652\" *) \n LUT5 #(\n .INIT(32'hE2FFFFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[90]_i_1 \n (.I0(p_1_in190_in),\n .I1(p_0_in102_in),\n .I2(p_2_in192_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[90] ));\n (* SOFT_HLUTNM = \"soft_lutpair676\" *) \n LUT4 #(\n .INIT(16'hE2FF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[91]_i_1 \n (.I0(p_1_in190_in),\n .I1(p_0_in106_in),\n .I2(p_2_in192_in),\n .I3(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] ));\n (* SOFT_HLUTNM = \"soft_lutpair681\" *) \n LUT4 #(\n .INIT(16'hE2FF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[92]_i_1 \n (.I0(p_1_in190_in),\n .I1(p_0_in110_in),\n .I2(p_2_in192_in),\n .I3(rdlvl_stg1_done_int_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[92] ));\n (* SOFT_HLUTNM = \"soft_lutpair649\" *) \n LUT5 #(\n .INIT(32'hE2FFFFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[93]_i_1 \n (.I0(p_1_in190_in),\n .I1(p_0_in114_in),\n .I2(p_2_in192_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[93] ));\n (* SOFT_HLUTNM = \"soft_lutpair653\" *) \n LUT5 #(\n .INIT(32'hE2FFFFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[94]_i_1 \n (.I0(p_1_in190_in),\n .I1(p_0_in118_in),\n .I2(p_2_in192_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[94] ));\n (* SOFT_HLUTNM = \"soft_lutpair671\" *) \n LUT4 #(\n .INIT(16'hE2FF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[95]_i_1 \n (.I0(p_1_in190_in),\n .I1(p_0_in122_in),\n .I2(p_2_in192_in),\n .I3(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[95] ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_infrastructure\" *) \nmodule ddr3_ifmig_7series_v4_0_infrastructure\n (mmcm_locked,\n psdone,\n CLK,\n mmcm_ps_clk,\n freq_refclk,\n mem_refclk,\n sync_pulse,\n poc_sample_pd,\n rst_sync_r1,\n \\stg3_tap_cnt_reg[0] ,\n reset_reg,\n \\simp_stg3_final_r_reg[17] ,\n in0,\n \\read_fifo.head_r_reg[0] ,\n SR,\n \\wrcal_dqs_cnt_r_reg[2] ,\n SS,\n \\cal2_state_r_reg[0] ,\n cal2_if_reset_reg,\n cal2_prech_req_r_reg,\n \\three_dec_max_limit_reg[11] ,\n prbs_found_1st_edge_r_reg,\n rst_out_reg,\n \\en_cnt_div4.enable_wrlvl_cnt_reg[2] ,\n \\complex_address_reg[0] ,\n \\init_state_r_reg[6] ,\n \\first_fail_taps_reg[0] ,\n \\pi_rdval_cnt_reg[0] ,\n \\gen_final_tap[2].final_val_reg[2][1] ,\n \\wl_tap_count_r_reg[0] ,\n \\victim_sel_rotate.sel_reg[31] ,\n \\last_master_r_reg[2] ,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ,\n \\wait_cnt_reg[3] ,\n \\wrcal_reads_reg[0] ,\n \\oneeighty_r_reg[0] ,\n RST0,\n \\stg3_r_reg[1] ,\n \\oneeighty_r_reg[0]_0 ,\n pll_locked,\n pre_wait_r_reg,\n rtp_timer_ns1,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ,\n ras_timer_zero_r_reg,\n ras_timer_zero_r_reg_0,\n \\pi_rst_stg1_cal_r_reg[1] ,\n \\samp_edge_cnt0_r_reg[11] ,\n \\wait_cnt_r_reg[3] ,\n \\en_cnt_div4.enable_wrlvl_cnt_reg[4] ,\n p_81_in,\n \\wr_victim_sel_ocal_reg[2] ,\n cnt_pwron_reset_done_r0,\n \\wait_cnt_reg[3]_0 ,\n E,\n mmcm_clk,\n AS,\n \\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ,\n \\lim_state_reg[0] ,\n poc_backup_r_reg,\n \\resume_wait_r_reg[10] ,\n sm_r,\n pass_open_bank_r,\n pass_open_bank_r_0,\n insert_maint_r,\n bm_end_r1,\n bm_end_r1_1,\n fine_adjust_reg,\n samp_edge_cnt0_en_r,\n pi_cnt_dec,\n \\en_cnt_div4.wrlvl_odt_reg ,\n \\row_cnt_victim_rotate.complex_row_cnt_reg[7] ,\n wr_victim_inc_reg,\n phy_mc_go,\n po_cnt_dec);\n output mmcm_locked;\n output psdone;\n output CLK;\n output mmcm_ps_clk;\n output freq_refclk;\n output mem_refclk;\n output sync_pulse;\n output poc_sample_pd;\n output rst_sync_r1;\n output \\stg3_tap_cnt_reg[0] ;\n output reset_reg;\n output \\simp_stg3_final_r_reg[17] ;\n output in0;\n output \\read_fifo.head_r_reg[0] ;\n output [0:0]SR;\n output \\wrcal_dqs_cnt_r_reg[2] ;\n output [0:0]SS;\n output [0:0]\\cal2_state_r_reg[0] ;\n output cal2_if_reset_reg;\n output cal2_prech_req_r_reg;\n output [0:0]\\three_dec_max_limit_reg[11] ;\n output prbs_found_1st_edge_r_reg;\n output rst_out_reg;\n output \\en_cnt_div4.enable_wrlvl_cnt_reg[2] ;\n output \\complex_address_reg[0] ;\n output [0:0]\\init_state_r_reg[6] ;\n output \\first_fail_taps_reg[0] ;\n output [1:0]\\pi_rdval_cnt_reg[0] ;\n output [0:0]\\gen_final_tap[2].final_val_reg[2][1] ;\n output [1:0]\\wl_tap_count_r_reg[0] ;\n output [0:0]\\victim_sel_rotate.sel_reg[31] ;\n output \\last_master_r_reg[2] ;\n output \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ;\n output \\wait_cnt_reg[3] ;\n output \\wrcal_reads_reg[0] ;\n output \\oneeighty_r_reg[0] ;\n output RST0;\n output \\stg3_r_reg[1] ;\n output [0:0]\\oneeighty_r_reg[0]_0 ;\n output pll_locked;\n output pre_wait_r_reg;\n output rtp_timer_ns1;\n output \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ;\n output ras_timer_zero_r_reg;\n output ras_timer_zero_r_reg_0;\n output \\pi_rst_stg1_cal_r_reg[1] ;\n output \\samp_edge_cnt0_r_reg[11] ;\n output [0:0]\\wait_cnt_r_reg[3] ;\n output \\en_cnt_div4.enable_wrlvl_cnt_reg[4] ;\n output p_81_in;\n output \\wr_victim_sel_ocal_reg[2] ;\n output cnt_pwron_reset_done_r0;\n output [0:0]\\wait_cnt_reg[3]_0 ;\n input [0:0]E;\n input mmcm_clk;\n input [0:0]AS;\n input \\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ;\n input \\lim_state_reg[0] ;\n input poc_backup_r_reg;\n input \\resume_wait_r_reg[10] ;\n input sm_r;\n input pass_open_bank_r;\n input pass_open_bank_r_0;\n input insert_maint_r;\n input bm_end_r1;\n input bm_end_r1_1;\n input fine_adjust_reg;\n input samp_edge_cnt0_en_r;\n input pi_cnt_dec;\n input \\en_cnt_div4.wrlvl_odt_reg ;\n input \\row_cnt_victim_rotate.complex_row_cnt_reg[7] ;\n input wr_victim_inc_reg;\n input phy_mc_go;\n input po_cnt_dec;\n\n wire [0:0]AS;\n wire CLK;\n wire [0:0]E;\n wire RST0;\n wire RST0_0;\n wire [0:0]SR;\n wire [0:0]SS;\n wire bm_end_r1;\n wire bm_end_r1_1;\n wire cal2_if_reset_reg;\n wire cal2_prech_req_r_reg;\n wire [0:0]\\cal2_state_r_reg[0] ;\n wire clk_div2_bufg_in;\n wire clk_pll_i;\n wire cnt_pwron_reset_done_r0;\n wire \\complex_address_reg[0] ;\n wire \\en_cnt_div4.enable_wrlvl_cnt_reg[2] ;\n wire \\en_cnt_div4.enable_wrlvl_cnt_reg[4] ;\n wire \\en_cnt_div4.wrlvl_odt_reg ;\n wire fine_adjust_reg;\n wire \\first_fail_taps_reg[0] ;\n wire first_rising_ps_clk_ns;\n wire first_rising_ps_clk_r;\n wire freq_refclk;\n wire [0:0]\\gen_final_tap[2].final_val_reg[2][1] ;\n wire \\gen_mmcm.u_bufg_clk_div2_n_0 ;\n wire in0;\n wire [0:0]\\init_state_r_reg[6] ;\n wire insert_maint_r;\n wire inv_poc_sample_ns0_out;\n wire inv_poc_sample_r;\n wire inv_poc_sample_r_i_2_n_0;\n wire \\last_master_r_reg[2] ;\n wire \\lim_state_reg[0] ;\n wire mem_refclk;\n wire mmcm_clk;\n wire mmcm_hi0_r;\n wire mmcm_hi0_r_i_1_n_0;\n wire mmcm_locked;\n wire mmcm_ps_clk;\n wire mmcm_ps_clk_bufg_in;\n wire \\oneeighty_r_reg[0] ;\n wire [0:0]\\oneeighty_r_reg[0]_0 ;\n wire [7:0]p_0_in__2;\n wire p_81_in;\n wire pass_open_bank_r;\n wire pass_open_bank_r_0;\n wire phy_mc_go;\n wire pi_cnt_dec;\n wire [1:0]\\pi_rdval_cnt_reg[0] ;\n wire \\pi_rst_stg1_cal_r_reg[1] ;\n wire pll_clk3;\n wire pll_clk3_out;\n wire pll_clkfbout;\n wire pll_locked;\n wire pll_locked_i;\n wire po_cnt_dec;\n wire poc_backup_r_reg;\n wire poc_sample_pd;\n wire poc_sample_pd_ns;\n wire poc_sample_pd_r_i_2_n_0;\n wire prbs_found_1st_edge_r_reg;\n wire pre_wait_r_reg;\n wire psdone;\n wire qcntr_ns;\n wire \\qcntr_r[2]_i_1_n_0 ;\n wire \\qcntr_r[3]_i_1_n_0 ;\n wire \\qcntr_r[4]_i_1_n_0 ;\n wire \\qcntr_r[5]_i_1_n_0 ;\n wire \\qcntr_r[7]_i_3_n_0 ;\n wire [7:0]qcntr_r_reg__0;\n wire ras_timer_zero_r_reg;\n wire ras_timer_zero_r_reg_0;\n wire \\read_fifo.head_r_reg[0] ;\n wire reset_reg;\n wire \\resume_wait_r_reg[10] ;\n wire \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ;\n wire \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ;\n wire \\row_cnt_victim_rotate.complex_row_cnt_reg[7] ;\n wire rst_out_reg;\n wire \\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ;\n wire [11:0]rst_sync_r;\n wire rst_sync_r1;\n wire [11:0]rstdiv0_sync_r;\n wire rstdiv0_sync_r1_reg_rep__0_n_0;\n wire rstdiv0_sync_r1_reg_rep__10_n_0;\n wire rstdiv0_sync_r1_reg_rep__11_n_0;\n wire rstdiv0_sync_r1_reg_rep__12_n_0;\n wire rstdiv0_sync_r1_reg_rep__13_n_0;\n wire rstdiv0_sync_r1_reg_rep__14_n_0;\n wire rstdiv0_sync_r1_reg_rep__15_n_0;\n wire rstdiv0_sync_r1_reg_rep__16_n_0;\n wire rstdiv0_sync_r1_reg_rep__17_n_0;\n wire rstdiv0_sync_r1_reg_rep__18_n_0;\n wire rstdiv0_sync_r1_reg_rep__19_n_0;\n wire rstdiv0_sync_r1_reg_rep__1_n_0;\n wire rstdiv0_sync_r1_reg_rep__20_n_0;\n wire rstdiv0_sync_r1_reg_rep__21_n_0;\n wire rstdiv0_sync_r1_reg_rep__22_n_0;\n wire rstdiv0_sync_r1_reg_rep__23_n_0;\n wire rstdiv0_sync_r1_reg_rep__24_n_0;\n wire rstdiv0_sync_r1_reg_rep__25_n_0;\n wire rstdiv0_sync_r1_reg_rep__2_n_0;\n wire rstdiv0_sync_r1_reg_rep__3_n_0;\n wire rstdiv0_sync_r1_reg_rep__4_n_0;\n wire rstdiv0_sync_r1_reg_rep__5_n_0;\n wire rstdiv0_sync_r1_reg_rep__6_n_0;\n wire rstdiv0_sync_r1_reg_rep__7_n_0;\n wire rstdiv0_sync_r1_reg_rep__8_n_0;\n wire rstdiv0_sync_r1_reg_rep__9_n_0;\n wire rstdiv0_sync_r1_reg_rep_n_0;\n wire [11:0]rstdiv2_sync_r;\n (* MAX_FANOUT = \"10\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire rstdiv2_sync_r1;\n wire rtp_timer_ns1;\n wire samp_edge_cnt0_en_r;\n wire \\samp_edge_cnt0_r_reg[11] ;\n wire \\simp_stg3_final_r_reg[17] ;\n wire sm_r;\n wire \\stg3_r_reg[1] ;\n wire \\stg3_tap_cnt_reg[0] ;\n wire sync_pulse;\n wire [0:0]\\three_dec_max_limit_reg[11] ;\n wire [0:0]\\victim_sel_rotate.sel_reg[31] ;\n wire [0:0]\\wait_cnt_r_reg[3] ;\n wire \\wait_cnt_reg[3] ;\n wire [0:0]\\wait_cnt_reg[3]_0 ;\n wire [1:0]\\wl_tap_count_r_reg[0] ;\n wire wr_victim_inc_reg;\n wire \\wr_victim_sel_ocal_reg[2] ;\n wire \\wrcal_dqs_cnt_r_reg[2] ;\n wire \\wrcal_reads_reg[0] ;\n wire \\NLW_gen_mmcm.mmcm_i_CLKFBOUTB_UNCONNECTED ;\n wire \\NLW_gen_mmcm.mmcm_i_CLKFBSTOPPED_UNCONNECTED ;\n wire \\NLW_gen_mmcm.mmcm_i_CLKINSTOPPED_UNCONNECTED ;\n wire \\NLW_gen_mmcm.mmcm_i_CLKOUT0B_UNCONNECTED ;\n wire \\NLW_gen_mmcm.mmcm_i_CLKOUT1B_UNCONNECTED ;\n wire \\NLW_gen_mmcm.mmcm_i_CLKOUT2_UNCONNECTED ;\n wire \\NLW_gen_mmcm.mmcm_i_CLKOUT2B_UNCONNECTED ;\n wire \\NLW_gen_mmcm.mmcm_i_CLKOUT3_UNCONNECTED ;\n wire \\NLW_gen_mmcm.mmcm_i_CLKOUT3B_UNCONNECTED ;\n wire \\NLW_gen_mmcm.mmcm_i_CLKOUT4_UNCONNECTED ;\n wire \\NLW_gen_mmcm.mmcm_i_CLKOUT5_UNCONNECTED ;\n wire \\NLW_gen_mmcm.mmcm_i_CLKOUT6_UNCONNECTED ;\n wire \\NLW_gen_mmcm.mmcm_i_DRDY_UNCONNECTED ;\n wire [15:0]\\NLW_gen_mmcm.mmcm_i_DO_UNCONNECTED ;\n wire NLW_plle2_i_CLKOUT4_UNCONNECTED;\n wire NLW_plle2_i_CLKOUT5_UNCONNECTED;\n wire NLW_plle2_i_DRDY_UNCONNECTED;\n wire [15:0]NLW_plle2_i_DO_UNCONNECTED;\n\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\FSM_sequential_sm_r[2]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__2_n_0),\n .O(\\wrcal_dqs_cnt_r_reg[2] ));\n (* SOFT_HLUTNM = \"soft_lutpair9\" *) \n LUT2 #(\n .INIT(4'hE)) \n act_wait_r_lcl_i_2__0\n (.I0(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ),\n .I1(bm_end_r1_1),\n .O(ras_timer_zero_r_reg_0));\n (* SOFT_HLUTNM = \"soft_lutpair9\" *) \n LUT2 #(\n .INIT(4'hE)) \n act_wait_r_lcl_i_3__0\n (.I0(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ),\n .I1(bm_end_r1),\n .O(ras_timer_zero_r_reg));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\cal1_cnt_cpt_r[1]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__14_n_0),\n .O(\\pi_rdval_cnt_reg[0] [1]));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n cal2_prech_req_r_i_1\n (.I0(rstdiv0_sync_r1_reg_rep__6_n_0),\n .O(cal2_prech_req_r_reg));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\cal2_state_r[3]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__4_n_0),\n .O(\\cal2_state_r_reg[0] ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n cke_r_i_1\n (.I0(rstdiv0_sync_r1_reg_rep__1_n_0),\n .O(SR));\n LUT2 #(\n .INIT(4'hB)) \n cnt_pwron_cke_done_r_i_3\n (.I0(\\wrcal_reads_reg[0] ),\n .I1(phy_mc_go),\n .O(cnt_pwron_reset_done_r0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\complex_num_reads_dec[0]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__18_n_0),\n .O(\\wl_tap_count_r_reg[0] [0]));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n complex_victim_inc_i_1\n (.I0(rstdiv0_sync_r1_reg_rep__7_n_0),\n .O(\\three_dec_max_limit_reg[11] ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\dqs_count_r[2]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__17_n_0),\n .O(\\wl_tap_count_r_reg[0] [1]));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\en_cnt_div4.enable_wrlvl_cnt[3]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__10_n_0),\n .O(\\en_cnt_div4.enable_wrlvl_cnt_reg[2] ));\n (* SOFT_HLUTNM = \"soft_lutpair10\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\en_cnt_div4.enable_wrlvl_cnt[4]_i_2 \n (.I0(\\wrcal_reads_reg[0] ),\n .I1(\\en_cnt_div4.wrlvl_odt_reg ),\n .O(\\en_cnt_div4.enable_wrlvl_cnt_reg[4] ));\n LUT1 #(\n .INIT(2'h1)) \n first_rising_ps_clk_r_i_1\n (.I0(reset_reg),\n .O(first_rising_ps_clk_ns));\n FDRE #(\n .INIT(1'b0)) \n first_rising_ps_clk_r_reg\n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(first_rising_ps_clk_ns),\n .Q(first_rising_ps_clk_r),\n .R(1'b0));\n (* box_type = \"PRIMITIVE\" *) \n MMCME2_ADV #(\n .BANDWIDTH(\"HIGH\"),\n .CLKFBOUT_MULT_F(4.000000),\n .CLKFBOUT_PHASE(0.000000),\n .CLKFBOUT_USE_FINE_PS(\"FALSE\"),\n .CLKIN1_PERIOD(4.444444),\n .CLKIN2_PERIOD(0.000000),\n .CLKOUT0_DIVIDE_F(8.000000),\n .CLKOUT0_DUTY_CYCLE(0.500000),\n .CLKOUT0_PHASE(0.000000),\n .CLKOUT0_USE_FINE_PS(\"TRUE\"),\n .CLKOUT1_DIVIDE(2),\n .CLKOUT1_DUTY_CYCLE(0.500000),\n .CLKOUT1_PHASE(0.000000),\n .CLKOUT1_USE_FINE_PS(\"FALSE\"),\n .CLKOUT2_DIVIDE(1),\n .CLKOUT2_DUTY_CYCLE(0.500000),\n .CLKOUT2_PHASE(0.000000),\n .CLKOUT2_USE_FINE_PS(\"FALSE\"),\n .CLKOUT3_DIVIDE(1),\n .CLKOUT3_DUTY_CYCLE(0.500000),\n .CLKOUT3_PHASE(0.000000),\n .CLKOUT3_USE_FINE_PS(\"FALSE\"),\n .CLKOUT4_CASCADE(\"FALSE\"),\n .CLKOUT4_DIVIDE(1),\n .CLKOUT4_DUTY_CYCLE(0.500000),\n .CLKOUT4_PHASE(0.000000),\n .CLKOUT4_USE_FINE_PS(\"FALSE\"),\n .CLKOUT5_DIVIDE(1),\n .CLKOUT5_DUTY_CYCLE(0.500000),\n .CLKOUT5_PHASE(0.000000),\n .CLKOUT5_USE_FINE_PS(\"FALSE\"),\n .CLKOUT6_DIVIDE(1),\n .CLKOUT6_DUTY_CYCLE(0.500000),\n .CLKOUT6_PHASE(0.000000),\n .CLKOUT6_USE_FINE_PS(\"FALSE\"),\n .COMPENSATION(\"BUF_IN\"),\n .DIVCLK_DIVIDE(1),\n .IS_CLKINSEL_INVERTED(1'b0),\n .IS_PSEN_INVERTED(1'b0),\n .IS_PSINCDEC_INVERTED(1'b0),\n .IS_PWRDWN_INVERTED(1'b0),\n .IS_RST_INVERTED(1'b0),\n .REF_JITTER1(0.000000),\n .REF_JITTER2(0.010000),\n .SS_EN(\"FALSE\"),\n .SS_MODE(\"CENTER_HIGH\"),\n .SS_MOD_PERIOD(10000),\n .STARTUP_WAIT(\"FALSE\")) \n \\gen_mmcm.mmcm_i \n (.CLKFBIN(CLK),\n .CLKFBOUT(clk_pll_i),\n .CLKFBOUTB(\\NLW_gen_mmcm.mmcm_i_CLKFBOUTB_UNCONNECTED ),\n .CLKFBSTOPPED(\\NLW_gen_mmcm.mmcm_i_CLKFBSTOPPED_UNCONNECTED ),\n .CLKIN1(pll_clk3),\n .CLKIN2(1'b0),\n .CLKINSEL(1'b1),\n .CLKINSTOPPED(\\NLW_gen_mmcm.mmcm_i_CLKINSTOPPED_UNCONNECTED ),\n .CLKOUT0(mmcm_ps_clk_bufg_in),\n .CLKOUT0B(\\NLW_gen_mmcm.mmcm_i_CLKOUT0B_UNCONNECTED ),\n .CLKOUT1(clk_div2_bufg_in),\n .CLKOUT1B(\\NLW_gen_mmcm.mmcm_i_CLKOUT1B_UNCONNECTED ),\n .CLKOUT2(\\NLW_gen_mmcm.mmcm_i_CLKOUT2_UNCONNECTED ),\n .CLKOUT2B(\\NLW_gen_mmcm.mmcm_i_CLKOUT2B_UNCONNECTED ),\n .CLKOUT3(\\NLW_gen_mmcm.mmcm_i_CLKOUT3_UNCONNECTED ),\n .CLKOUT3B(\\NLW_gen_mmcm.mmcm_i_CLKOUT3B_UNCONNECTED ),\n .CLKOUT4(\\NLW_gen_mmcm.mmcm_i_CLKOUT4_UNCONNECTED ),\n .CLKOUT5(\\NLW_gen_mmcm.mmcm_i_CLKOUT5_UNCONNECTED ),\n .CLKOUT6(\\NLW_gen_mmcm.mmcm_i_CLKOUT6_UNCONNECTED ),\n .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DCLK(1'b0),\n .DEN(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DO(\\NLW_gen_mmcm.mmcm_i_DO_UNCONNECTED [15:0]),\n .DRDY(\\NLW_gen_mmcm.mmcm_i_DRDY_UNCONNECTED ),\n .DWE(1'b0),\n .LOCKED(mmcm_locked),\n .PSCLK(CLK),\n .PSDONE(psdone),\n .PSEN(E),\n .PSINCDEC(1'b1),\n .PWRDWN(1'b0),\n .RST(RST0_0));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_mmcm.mmcm_i_i_2 \n (.I0(pll_locked_i),\n .O(RST0_0));\n (* box_type = \"PRIMITIVE\" *) \n BUFG \\gen_mmcm.u_bufg_clk_div2 \n (.I(clk_div2_bufg_in),\n .O(\\gen_mmcm.u_bufg_clk_div2_n_0 ));\n (* box_type = \"PRIMITIVE\" *) \n BUFG \\gen_mmcm.u_bufg_mmcm_ps_clk \n (.I(mmcm_ps_clk_bufg_in),\n .O(mmcm_ps_clk));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n i___0_i_1\n (.I0(rstdiv0_sync_r1_reg_rep__20_n_0),\n .O(\\last_master_r_reg[2] ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n i___35_i_1\n (.I0(rstdiv0_sync_r1_reg_rep__21_n_0),\n .O(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n i___56_i_1\n (.I0(rstdiv0_sync_r1_reg_rep__22_n_0),\n .O(\\wait_cnt_reg[3] ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\init_state_r[6]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__12_n_0),\n .O(\\init_state_r_reg[6] ));\n LUT6 #(\n .INIT(64'h000000007FFF8000)) \n inv_poc_sample_r_i_1\n (.I0(qcntr_r_reg__0[7]),\n .I1(qcntr_r_reg__0[6]),\n .I2(inv_poc_sample_r_i_2_n_0),\n .I3(E),\n .I4(inv_poc_sample_r),\n .I5(reset_reg),\n .O(inv_poc_sample_ns0_out));\n LUT6 #(\n .INIT(64'hEAAAAAAAAAAAAAAA)) \n inv_poc_sample_r_i_2\n (.I0(qcntr_r_reg__0[5]),\n .I1(qcntr_r_reg__0[4]),\n .I2(qcntr_r_reg__0[2]),\n .I3(qcntr_r_reg__0[0]),\n .I4(qcntr_r_reg__0[1]),\n .I5(qcntr_r_reg__0[3]),\n .O(inv_poc_sample_r_i_2_n_0));\n FDRE #(\n .INIT(1'b0)) \n inv_poc_sample_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(inv_poc_sample_ns0_out),\n .Q(inv_poc_sample_r),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h7)) \n mmcm_hi0_r_i_1\n (.I0(mmcm_hi0_r),\n .I1(first_rising_ps_clk_r),\n .O(mmcm_hi0_r_i_1_n_0));\n FDRE #(\n .INIT(1'b0)) \n mmcm_hi0_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mmcm_hi0_r_i_1_n_0),\n .Q(mmcm_hi0_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair15\" *) \n LUT2 #(\n .INIT(4'h7)) \n phaser_ref_i_i_1\n (.I0(pll_locked_i),\n .I1(mmcm_locked),\n .O(RST0));\n (* SOFT_HLUTNM = \"soft_lutpair15\" *) \n LUT2 #(\n .INIT(4'h8)) \n phy_control_i_i_1\n (.I0(pll_locked_i),\n .I1(mmcm_locked),\n .O(pll_locked));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\pi_dqs_found_all_bank[1]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__13_n_0),\n .O(\\first_fail_taps_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair10\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\pi_rst_stg1_cal_r[1]_i_3 \n (.I0(\\wrcal_reads_reg[0] ),\n .I1(fine_adjust_reg),\n .O(\\pi_rst_stg1_cal_r_reg[1] ));\n (* box_type = \"PRIMITIVE\" *) \n PLLE2_ADV #(\n .BANDWIDTH(\"OPTIMIZED\"),\n .CLKFBOUT_MULT(9),\n .CLKFBOUT_PHASE(0.000000),\n .CLKIN1_PERIOD(5.000000),\n .CLKIN2_PERIOD(0.000000),\n .CLKOUT0_DIVIDE(2),\n .CLKOUT0_DUTY_CYCLE(0.500000),\n .CLKOUT0_PHASE(337.500000),\n .CLKOUT1_DIVIDE(2),\n .CLKOUT1_DUTY_CYCLE(0.500000),\n .CLKOUT1_PHASE(0.000000),\n .CLKOUT2_DIVIDE(32),\n .CLKOUT2_DUTY_CYCLE(0.062500),\n .CLKOUT2_PHASE(9.843750),\n .CLKOUT3_DIVIDE(8),\n .CLKOUT3_DUTY_CYCLE(0.500000),\n .CLKOUT3_PHASE(0.000000),\n .CLKOUT4_DIVIDE(4),\n .CLKOUT4_DUTY_CYCLE(0.500000),\n .CLKOUT4_PHASE(168.750000),\n .CLKOUT5_DIVIDE(1),\n .CLKOUT5_DUTY_CYCLE(0.500000),\n .CLKOUT5_PHASE(0.000000),\n .COMPENSATION(\"INTERNAL\"),\n .DIVCLK_DIVIDE(1),\n .IS_CLKINSEL_INVERTED(1'b0),\n .IS_PWRDWN_INVERTED(1'b0),\n .IS_RST_INVERTED(1'b0),\n .REF_JITTER1(0.010000),\n .REF_JITTER2(0.010000),\n .STARTUP_WAIT(\"FALSE\")) \n plle2_i\n (.CLKFBIN(pll_clkfbout),\n .CLKFBOUT(pll_clkfbout),\n .CLKIN1(mmcm_clk),\n .CLKIN2(1'b0),\n .CLKINSEL(1'b1),\n .CLKOUT0(freq_refclk),\n .CLKOUT1(mem_refclk),\n .CLKOUT2(sync_pulse),\n .CLKOUT3(pll_clk3_out),\n .CLKOUT4(NLW_plle2_i_CLKOUT4_UNCONNECTED),\n .CLKOUT5(NLW_plle2_i_CLKOUT5_UNCONNECTED),\n .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DCLK(1'b0),\n .DEN(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DO(NLW_plle2_i_DO_UNCONNECTED[15:0]),\n .DRDY(NLW_plle2_i_DRDY_UNCONNECTED),\n .DWE(1'b0),\n .LOCKED(pll_locked_i),\n .PWRDWN(1'b0),\n .RST(AS));\n LUT6 #(\n .INIT(64'hBBBBEBBB44441444)) \n poc_sample_pd_r_i_1\n (.I0(reset_reg),\n .I1(inv_poc_sample_r),\n .I2(E),\n .I3(inv_poc_sample_r_i_2_n_0),\n .I4(poc_sample_pd_r_i_2_n_0),\n .I5(mmcm_hi0_r),\n .O(poc_sample_pd_ns));\n LUT2 #(\n .INIT(4'h7)) \n poc_sample_pd_r_i_2\n (.I0(qcntr_r_reg__0[6]),\n .I1(qcntr_r_reg__0[7]),\n .O(poc_sample_pd_r_i_2_n_0));\n FDRE #(\n .INIT(1'b0)) \n poc_sample_pd_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(poc_sample_pd_ns),\n .Q(poc_sample_pd),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\prbs_state_r[4]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__8_n_0),\n .O(prbs_found_1st_edge_r_reg));\n (* SOFT_HLUTNM = \"soft_lutpair11\" *) \n LUT2 #(\n .INIT(4'h1)) \n pre_wait_r_i_2\n (.I0(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ),\n .I1(pass_open_bank_r),\n .O(pre_wait_r_reg));\n (* SOFT_HLUTNM = \"soft_lutpair11\" *) \n LUT2 #(\n .INIT(4'hE)) \n pre_wait_r_i_3__0\n (.I0(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ),\n .I1(pass_open_bank_r_0),\n .O(rtp_timer_ns1));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n pwron_ce_r_i_1\n (.I0(rstdiv0_sync_r1_reg_rep__11_n_0),\n .O(\\complex_address_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair14\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\qcntr_r[0]_i_1 \n (.I0(qcntr_r_reg__0[0]),\n .O(p_0_in__2[0]));\n (* SOFT_HLUTNM = \"soft_lutpair14\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\qcntr_r[1]_i_1 \n (.I0(qcntr_r_reg__0[0]),\n .I1(qcntr_r_reg__0[1]),\n .O(p_0_in__2[1]));\n (* SOFT_HLUTNM = \"soft_lutpair7\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\qcntr_r[2]_i_1 \n (.I0(qcntr_r_reg__0[1]),\n .I1(qcntr_r_reg__0[0]),\n .I2(qcntr_r_reg__0[2]),\n .O(\\qcntr_r[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair7\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\qcntr_r[3]_i_1 \n (.I0(qcntr_r_reg__0[2]),\n .I1(qcntr_r_reg__0[0]),\n .I2(qcntr_r_reg__0[1]),\n .I3(qcntr_r_reg__0[3]),\n .O(\\qcntr_r[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair6\" *) \n LUT5 #(\n .INIT(32'h7FFF8000)) \n \\qcntr_r[4]_i_1 \n (.I0(qcntr_r_reg__0[3]),\n .I1(qcntr_r_reg__0[1]),\n .I2(qcntr_r_reg__0[0]),\n .I3(qcntr_r_reg__0[2]),\n .I4(qcntr_r_reg__0[4]),\n .O(\\qcntr_r[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h7FFFFFFF80000000)) \n \\qcntr_r[5]_i_1 \n (.I0(qcntr_r_reg__0[4]),\n .I1(qcntr_r_reg__0[2]),\n .I2(qcntr_r_reg__0[0]),\n .I3(qcntr_r_reg__0[1]),\n .I4(qcntr_r_reg__0[3]),\n .I5(qcntr_r_reg__0[5]),\n .O(\\qcntr_r[5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair8\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\qcntr_r[6]_i_1 \n (.I0(\\qcntr_r[7]_i_3_n_0 ),\n .I1(qcntr_r_reg__0[5]),\n .I2(qcntr_r_reg__0[6]),\n .O(p_0_in__2[6]));\n LUT6 #(\n .INIT(64'hFFFFFFFFB0000000)) \n \\qcntr_r[7]_i_1 \n (.I0(qcntr_r_reg__0[5]),\n .I1(\\qcntr_r[7]_i_3_n_0 ),\n .I2(E),\n .I3(qcntr_r_reg__0[7]),\n .I4(qcntr_r_reg__0[6]),\n .I5(reset_reg),\n .O(qcntr_ns));\n (* SOFT_HLUTNM = \"soft_lutpair8\" *) \n LUT4 #(\n .INIT(16'hBF40)) \n \\qcntr_r[7]_i_2 \n (.I0(\\qcntr_r[7]_i_3_n_0 ),\n .I1(qcntr_r_reg__0[5]),\n .I2(qcntr_r_reg__0[6]),\n .I3(qcntr_r_reg__0[7]),\n .O(p_0_in__2[7]));\n (* SOFT_HLUTNM = \"soft_lutpair6\" *) \n LUT5 #(\n .INIT(32'h7FFFFFFF)) \n \\qcntr_r[7]_i_3 \n (.I0(qcntr_r_reg__0[3]),\n .I1(qcntr_r_reg__0[1]),\n .I2(qcntr_r_reg__0[0]),\n .I3(qcntr_r_reg__0[2]),\n .I4(qcntr_r_reg__0[4]),\n .O(\\qcntr_r[7]_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\qcntr_r_reg[0] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__2[0]),\n .Q(qcntr_r_reg__0[0]),\n .R(qcntr_ns));\n FDRE #(\n .INIT(1'b0)) \n \\qcntr_r_reg[1] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__2[1]),\n .Q(qcntr_r_reg__0[1]),\n .R(qcntr_ns));\n FDRE #(\n .INIT(1'b0)) \n \\qcntr_r_reg[2] \n (.C(CLK),\n .CE(E),\n .D(\\qcntr_r[2]_i_1_n_0 ),\n .Q(qcntr_r_reg__0[2]),\n .R(qcntr_ns));\n FDRE #(\n .INIT(1'b0)) \n \\qcntr_r_reg[3] \n (.C(CLK),\n .CE(E),\n .D(\\qcntr_r[3]_i_1_n_0 ),\n .Q(qcntr_r_reg__0[3]),\n .R(qcntr_ns));\n FDRE #(\n .INIT(1'b0)) \n \\qcntr_r_reg[4] \n (.C(CLK),\n .CE(E),\n .D(\\qcntr_r[4]_i_1_n_0 ),\n .Q(qcntr_r_reg__0[4]),\n .R(qcntr_ns));\n FDRE #(\n .INIT(1'b0)) \n \\qcntr_r_reg[5] \n (.C(CLK),\n .CE(E),\n .D(\\qcntr_r[5]_i_1_n_0 ),\n .Q(qcntr_r_reg__0[5]),\n .R(qcntr_ns));\n FDRE #(\n .INIT(1'b0)) \n \\qcntr_r_reg[6] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__2[6]),\n .Q(qcntr_r_reg__0[6]),\n .R(qcntr_ns));\n FDRE #(\n .INIT(1'b0)) \n \\qcntr_r_reg[7] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__2[7]),\n .Q(qcntr_r_reg__0[7]),\n .R(qcntr_ns));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\rdlvl_dqs_tap_cnt_r[0][2][4]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__15_n_0),\n .O(\\pi_rdval_cnt_reg[0] [0]));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n reset_i_1\n (.I0(rstdiv0_sync_r1_reg_rep__25_n_0),\n .O(reset_reg));\n LUT2 #(\n .INIT(4'h1)) \n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_2 \n (.I0(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ),\n .I1(insert_maint_r),\n .O(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\rp_timer.rp_timer_r[1]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__0_n_0),\n .O(\\read_fifo.head_r_reg[0] ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n rst_out_i_2\n (.I0(rstdiv0_sync_r1_reg_rep__9_n_0),\n .O(rst_out_reg));\n FDPE #(\n .INIT(1'b1)) \n rst_sync_r1_reg\n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(rst_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rst_sync_r1));\n FDPE #(\n .INIT(1'b1)) \n \\rst_sync_r_reg[0] \n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(1'b0),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rst_sync_r[0]));\n FDPE #(\n .INIT(1'b1)) \n \\rst_sync_r_reg[10] \n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(rst_sync_r[9]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rst_sync_r[10]));\n FDPE #(\n .INIT(1'b1)) \n \\rst_sync_r_reg[11] \n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(rst_sync_r[10]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rst_sync_r[11]));\n FDPE #(\n .INIT(1'b1)) \n \\rst_sync_r_reg[1] \n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(rst_sync_r[0]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rst_sync_r[1]));\n FDPE #(\n .INIT(1'b1)) \n \\rst_sync_r_reg[2] \n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(rst_sync_r[1]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rst_sync_r[2]));\n FDPE #(\n .INIT(1'b1)) \n \\rst_sync_r_reg[3] \n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(rst_sync_r[2]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rst_sync_r[3]));\n FDPE #(\n .INIT(1'b1)) \n \\rst_sync_r_reg[4] \n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(rst_sync_r[3]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rst_sync_r[4]));\n FDPE #(\n .INIT(1'b1)) \n \\rst_sync_r_reg[5] \n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(rst_sync_r[4]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rst_sync_r[5]));\n FDPE #(\n .INIT(1'b1)) \n \\rst_sync_r_reg[6] \n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(rst_sync_r[5]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rst_sync_r[6]));\n FDPE #(\n .INIT(1'b1)) \n \\rst_sync_r_reg[7] \n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(rst_sync_r[6]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rst_sync_r[7]));\n FDPE #(\n .INIT(1'b1)) \n \\rst_sync_r_reg[8] \n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(rst_sync_r[7]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rst_sync_r[8]));\n FDPE #(\n .INIT(1'b1)) \n \\rst_sync_r_reg[9] \n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(rst_sync_r[8]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rst_sync_r[9]));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE #(\n .INIT(1'b1)) \n rstdiv0_sync_r1_reg_rep\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE #(\n .INIT(1'b1)) \n rstdiv0_sync_r1_reg_rep__0\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__0_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE #(\n .INIT(1'b1)) \n rstdiv0_sync_r1_reg_rep__1\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__1_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE #(\n .INIT(1'b1)) \n rstdiv0_sync_r1_reg_rep__10\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__10_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE #(\n .INIT(1'b1)) \n rstdiv0_sync_r1_reg_rep__11\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__11_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE #(\n .INIT(1'b1)) \n rstdiv0_sync_r1_reg_rep__12\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__12_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE #(\n .INIT(1'b1)) \n rstdiv0_sync_r1_reg_rep__13\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__13_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE #(\n .INIT(1'b1)) \n rstdiv0_sync_r1_reg_rep__14\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__14_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE #(\n .INIT(1'b1)) \n rstdiv0_sync_r1_reg_rep__15\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__15_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE #(\n .INIT(1'b1)) \n rstdiv0_sync_r1_reg_rep__16\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__16_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE #(\n .INIT(1'b1)) \n rstdiv0_sync_r1_reg_rep__17\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__17_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE #(\n .INIT(1'b1)) \n rstdiv0_sync_r1_reg_rep__18\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__18_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE #(\n .INIT(1'b1)) \n rstdiv0_sync_r1_reg_rep__19\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__19_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE #(\n .INIT(1'b1)) \n rstdiv0_sync_r1_reg_rep__2\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__2_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE #(\n .INIT(1'b1)) \n rstdiv0_sync_r1_reg_rep__20\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__20_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE #(\n .INIT(1'b1)) \n rstdiv0_sync_r1_reg_rep__21\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__21_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE #(\n .INIT(1'b1)) \n rstdiv0_sync_r1_reg_rep__22\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__22_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE #(\n .INIT(1'b1)) \n rstdiv0_sync_r1_reg_rep__23\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__23_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE #(\n .INIT(1'b1)) \n rstdiv0_sync_r1_reg_rep__24\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__24_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE #(\n .INIT(1'b1)) \n rstdiv0_sync_r1_reg_rep__25\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__25_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE #(\n .INIT(1'b1)) \n rstdiv0_sync_r1_reg_rep__3\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__3_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE #(\n .INIT(1'b1)) \n rstdiv0_sync_r1_reg_rep__4\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__4_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE #(\n .INIT(1'b1)) \n rstdiv0_sync_r1_reg_rep__5\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__5_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE #(\n .INIT(1'b1)) \n rstdiv0_sync_r1_reg_rep__6\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__6_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE #(\n .INIT(1'b1)) \n rstdiv0_sync_r1_reg_rep__7\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__7_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE #(\n .INIT(1'b1)) \n rstdiv0_sync_r1_reg_rep__8\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__8_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE #(\n .INIT(1'b1)) \n rstdiv0_sync_r1_reg_rep__9\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__9_n_0));\n FDPE #(\n .INIT(1'b1)) \n \\rstdiv0_sync_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(1'b0),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r[0]));\n FDPE #(\n .INIT(1'b1)) \n \\rstdiv0_sync_r_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[9]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r[10]));\n FDPE #(\n .INIT(1'b1)) \n \\rstdiv0_sync_r_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[10]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r[11]));\n FDPE #(\n .INIT(1'b1)) \n \\rstdiv0_sync_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[0]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r[1]));\n FDPE #(\n .INIT(1'b1)) \n \\rstdiv0_sync_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[1]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r[2]));\n FDPE #(\n .INIT(1'b1)) \n \\rstdiv0_sync_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[2]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r[3]));\n FDPE #(\n .INIT(1'b1)) \n \\rstdiv0_sync_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[3]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r[4]));\n FDPE #(\n .INIT(1'b1)) \n \\rstdiv0_sync_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[4]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r[5]));\n FDPE #(\n .INIT(1'b1)) \n \\rstdiv0_sync_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[5]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r[6]));\n FDPE #(\n .INIT(1'b1)) \n \\rstdiv0_sync_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[6]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r[7]));\n FDPE #(\n .INIT(1'b1)) \n \\rstdiv0_sync_r_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[7]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r[8]));\n FDPE #(\n .INIT(1'b1)) \n \\rstdiv0_sync_r_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[8]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r[9]));\n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDPE #(\n .INIT(1'b1)) \n rstdiv2_sync_r1_reg\n (.C(\\gen_mmcm.u_bufg_clk_div2_n_0 ),\n .CE(1'b1),\n .D(rstdiv2_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv2_sync_r1));\n FDPE #(\n .INIT(1'b1)) \n \\rstdiv2_sync_r_reg[0] \n (.C(\\gen_mmcm.u_bufg_clk_div2_n_0 ),\n .CE(1'b1),\n .D(1'b0),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv2_sync_r[0]));\n FDPE #(\n .INIT(1'b1)) \n \\rstdiv2_sync_r_reg[10] \n (.C(\\gen_mmcm.u_bufg_clk_div2_n_0 ),\n .CE(1'b1),\n .D(rstdiv2_sync_r[9]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv2_sync_r[10]));\n FDPE #(\n .INIT(1'b1)) \n \\rstdiv2_sync_r_reg[11] \n (.C(\\gen_mmcm.u_bufg_clk_div2_n_0 ),\n .CE(1'b1),\n .D(rstdiv2_sync_r[10]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv2_sync_r[11]));\n FDPE #(\n .INIT(1'b1)) \n \\rstdiv2_sync_r_reg[1] \n (.C(\\gen_mmcm.u_bufg_clk_div2_n_0 ),\n .CE(1'b1),\n .D(rstdiv2_sync_r[0]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv2_sync_r[1]));\n FDPE #(\n .INIT(1'b1)) \n \\rstdiv2_sync_r_reg[2] \n (.C(\\gen_mmcm.u_bufg_clk_div2_n_0 ),\n .CE(1'b1),\n .D(rstdiv2_sync_r[1]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv2_sync_r[2]));\n FDPE #(\n .INIT(1'b1)) \n \\rstdiv2_sync_r_reg[3] \n (.C(\\gen_mmcm.u_bufg_clk_div2_n_0 ),\n .CE(1'b1),\n .D(rstdiv2_sync_r[2]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv2_sync_r[3]));\n FDPE #(\n .INIT(1'b1)) \n \\rstdiv2_sync_r_reg[4] \n (.C(\\gen_mmcm.u_bufg_clk_div2_n_0 ),\n .CE(1'b1),\n .D(rstdiv2_sync_r[3]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv2_sync_r[4]));\n FDPE #(\n .INIT(1'b1)) \n \\rstdiv2_sync_r_reg[5] \n (.C(\\gen_mmcm.u_bufg_clk_div2_n_0 ),\n .CE(1'b1),\n .D(rstdiv2_sync_r[4]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv2_sync_r[5]));\n FDPE #(\n .INIT(1'b1)) \n \\rstdiv2_sync_r_reg[6] \n (.C(\\gen_mmcm.u_bufg_clk_div2_n_0 ),\n .CE(1'b1),\n .D(rstdiv2_sync_r[5]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv2_sync_r[6]));\n FDPE #(\n .INIT(1'b1)) \n \\rstdiv2_sync_r_reg[7] \n (.C(\\gen_mmcm.u_bufg_clk_div2_n_0 ),\n .CE(1'b1),\n .D(rstdiv2_sync_r[6]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv2_sync_r[7]));\n FDPE #(\n .INIT(1'b1)) \n \\rstdiv2_sync_r_reg[8] \n (.C(\\gen_mmcm.u_bufg_clk_div2_n_0 ),\n .CE(1'b1),\n .D(rstdiv2_sync_r[7]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv2_sync_r[8]));\n FDPE #(\n .INIT(1'b1)) \n \\rstdiv2_sync_r_reg[9] \n (.C(\\gen_mmcm.u_bufg_clk_div2_n_0 ),\n .CE(1'b1),\n .D(rstdiv2_sync_r[8]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv2_sync_r[9]));\n (* SOFT_HLUTNM = \"soft_lutpair12\" *) \n LUT2 #(\n .INIT(4'hB)) \n \\samp_edge_cnt0_r[0]_i_1 \n (.I0(\\wait_cnt_reg[3] ),\n .I1(samp_edge_cnt0_en_r),\n .O(\\samp_edge_cnt0_r_reg[11] ));\n LUT2 #(\n .INIT(4'h1)) \n \\simp_stg3_final_r[23]_i_2 \n (.I0(reset_reg),\n .I1(poc_backup_r_reg),\n .O(\\simp_stg3_final_r_reg[17] ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\smallest[0][5]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__16_n_0),\n .O(\\gen_final_tap[2].final_val_reg[2][1] ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\stg2_tap_cnt[5]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__19_n_0),\n .O(\\victim_sel_rotate.sel_reg[31] ));\n LUT2 #(\n .INIT(4'hE)) \n \\stg3_r[5]_i_13 \n (.I0(reset_reg),\n .I1(\\resume_wait_r_reg[10] ),\n .O(\\stg3_r_reg[1] ));\n LUT2 #(\n .INIT(4'h1)) \n \\stg3_tap_cnt[5]_i_3 \n (.I0(reset_reg),\n .I1(\\lim_state_reg[0] ),\n .O(\\stg3_tap_cnt_reg[0] ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\tempmon_state[0]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__3_n_0),\n .O(SS));\n (* box_type = \"PRIMITIVE\" *) \n BUFG u_bufg_clkdiv0\n (.I(clk_pll_i),\n .O(CLK));\n (* box_type = \"PRIMITIVE\" *) \n BUFH u_bufh_pll_clk3\n (.I(pll_clk3_out),\n .O(pll_clk3));\n LUT1 #(\n .INIT(2'h2)) \n ui_clk_sync_rst_INST_0\n (.I0(rstdiv0_sync_r1_reg_rep_n_0),\n .O(in0));\n (* SOFT_HLUTNM = \"soft_lutpair12\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\wait_cnt[3]_i_1 \n (.I0(\\wait_cnt_reg[3] ),\n .I1(po_cnt_dec),\n .O(\\wait_cnt_reg[3]_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\wait_cnt_r[3]_i_1__1 \n (.I0(\\wait_cnt_reg[3] ),\n .I1(pi_cnt_dec),\n .O(\\wait_cnt_r_reg[3] ));\n (* SOFT_HLUTNM = \"soft_lutpair13\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\wr_victim_sel[2]_i_2 \n (.I0(\\wrcal_reads_reg[0] ),\n .I1(\\row_cnt_victim_rotate.complex_row_cnt_reg[7] ),\n .O(p_81_in));\n (* SOFT_HLUTNM = \"soft_lutpair13\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\wr_victim_sel_ocal[2]_i_2 \n (.I0(\\wrcal_reads_reg[0] ),\n .I1(wr_victim_inc_reg),\n .O(\\wr_victim_sel_ocal_reg[2] ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\wrcal_reads[7]_i_4 \n (.I0(rstdiv0_sync_r1_reg_rep__23_n_0),\n .O(\\wrcal_reads_reg[0] ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n wrcal_sanity_chk_done_i_1\n (.I0(rstdiv0_sync_r1_reg_rep__5_n_0),\n .O(cal2_if_reset_reg));\n LUT2 #(\n .INIT(4'h1)) \n \\zero_r[9]_i_1 \n (.I0(\\oneeighty_r_reg[0] ),\n .I1(sm_r),\n .O(\\oneeighty_r_reg[0]_0 ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\zero_r[9]_i_4 \n (.I0(rstdiv0_sync_r1_reg_rep__24_n_0),\n .O(\\oneeighty_r_reg[0] ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_iodelay_ctrl\" *) \nmodule ddr3_ifmig_7series_v4_0_iodelay_ctrl\n (AS,\n rst_sync_r1_reg,\n mmcm_clk,\n sys_rst);\n output [0:0]AS;\n output [0:0]rst_sync_r1_reg;\n input mmcm_clk;\n input sys_rst;\n\n wire [0:0]AS;\n wire \\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ;\n wire clk_ref_mmcm_400;\n wire [0:0]iodelay_ctrl_rdy;\n wire mmcm_clk;\n wire mmcm_clkfbout;\n wire rst_ref_0;\n wire rst_ref_1;\n wire \\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][0] ;\n wire \\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][10] ;\n wire \\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][11] ;\n wire \\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][12] ;\n wire \\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][13] ;\n wire \\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][1] ;\n wire \\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][2] ;\n wire \\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][3] ;\n wire \\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][4] ;\n wire \\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][5] ;\n wire \\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][6] ;\n wire \\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][7] ;\n wire \\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][8] ;\n wire \\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][9] ;\n wire \\rst_ref_sync_r_reg_n_0_[0][0] ;\n wire \\rst_ref_sync_r_reg_n_0_[0][10] ;\n wire \\rst_ref_sync_r_reg_n_0_[0][11] ;\n wire \\rst_ref_sync_r_reg_n_0_[0][12] ;\n wire \\rst_ref_sync_r_reg_n_0_[0][13] ;\n wire \\rst_ref_sync_r_reg_n_0_[0][1] ;\n wire \\rst_ref_sync_r_reg_n_0_[0][2] ;\n wire \\rst_ref_sync_r_reg_n_0_[0][3] ;\n wire \\rst_ref_sync_r_reg_n_0_[0][4] ;\n wire \\rst_ref_sync_r_reg_n_0_[0][5] ;\n wire \\rst_ref_sync_r_reg_n_0_[0][6] ;\n wire \\rst_ref_sync_r_reg_n_0_[0][7] ;\n wire \\rst_ref_sync_r_reg_n_0_[0][8] ;\n wire \\rst_ref_sync_r_reg_n_0_[0][9] ;\n wire [0:0]rst_sync_r1_reg;\n wire sys_rst;\n wire \\NLW_clk_ref_mmcm_gen.mmcm_i_CLKFBOUTB_UNCONNECTED ;\n wire \\NLW_clk_ref_mmcm_gen.mmcm_i_CLKFBSTOPPED_UNCONNECTED ;\n wire \\NLW_clk_ref_mmcm_gen.mmcm_i_CLKINSTOPPED_UNCONNECTED ;\n wire \\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT0_UNCONNECTED ;\n wire \\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT0B_UNCONNECTED ;\n wire \\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT1B_UNCONNECTED ;\n wire \\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT2_UNCONNECTED ;\n wire \\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT2B_UNCONNECTED ;\n wire \\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT3_UNCONNECTED ;\n wire \\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT3B_UNCONNECTED ;\n wire \\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT4_UNCONNECTED ;\n wire \\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT5_UNCONNECTED ;\n wire \\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT6_UNCONNECTED ;\n wire \\NLW_clk_ref_mmcm_gen.mmcm_i_DRDY_UNCONNECTED ;\n wire \\NLW_clk_ref_mmcm_gen.mmcm_i_LOCKED_UNCONNECTED ;\n wire \\NLW_clk_ref_mmcm_gen.mmcm_i_PSDONE_UNCONNECTED ;\n wire [15:0]\\NLW_clk_ref_mmcm_gen.mmcm_i_DO_UNCONNECTED ;\n\n (* box_type = \"PRIMITIVE\" *) \n BUFG \\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400 \n (.I(clk_ref_mmcm_400),\n .O(\\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ));\n (* box_type = \"PRIMITIVE\" *) \n MMCME2_ADV #(\n .BANDWIDTH(\"HIGH\"),\n .CLKFBOUT_MULT_F(6.000000),\n .CLKFBOUT_PHASE(0.000000),\n .CLKFBOUT_USE_FINE_PS(\"FALSE\"),\n .CLKIN1_PERIOD(5.000000),\n .CLKIN2_PERIOD(0.000000),\n .CLKOUT0_DIVIDE_F(4.000000),\n .CLKOUT0_DUTY_CYCLE(0.500000),\n .CLKOUT0_PHASE(0.000000),\n .CLKOUT0_USE_FINE_PS(\"FALSE\"),\n .CLKOUT1_DIVIDE(3),\n .CLKOUT1_DUTY_CYCLE(0.500000),\n .CLKOUT1_PHASE(0.000000),\n .CLKOUT1_USE_FINE_PS(\"FALSE\"),\n .CLKOUT2_DIVIDE(1),\n .CLKOUT2_DUTY_CYCLE(0.500000),\n .CLKOUT2_PHASE(0.000000),\n .CLKOUT2_USE_FINE_PS(\"FALSE\"),\n .CLKOUT3_DIVIDE(1),\n .CLKOUT3_DUTY_CYCLE(0.500000),\n .CLKOUT3_PHASE(0.000000),\n .CLKOUT3_USE_FINE_PS(\"FALSE\"),\n .CLKOUT4_CASCADE(\"FALSE\"),\n .CLKOUT4_DIVIDE(1),\n .CLKOUT4_DUTY_CYCLE(0.500000),\n .CLKOUT4_PHASE(0.000000),\n .CLKOUT4_USE_FINE_PS(\"FALSE\"),\n .CLKOUT5_DIVIDE(1),\n .CLKOUT5_DUTY_CYCLE(0.500000),\n .CLKOUT5_PHASE(0.000000),\n .CLKOUT5_USE_FINE_PS(\"FALSE\"),\n .CLKOUT6_DIVIDE(1),\n .CLKOUT6_DUTY_CYCLE(0.500000),\n .CLKOUT6_PHASE(0.000000),\n .CLKOUT6_USE_FINE_PS(\"FALSE\"),\n .COMPENSATION(\"INTERNAL\"),\n .DIVCLK_DIVIDE(1),\n .IS_CLKINSEL_INVERTED(1'b0),\n .IS_PSEN_INVERTED(1'b0),\n .IS_PSINCDEC_INVERTED(1'b0),\n .IS_PWRDWN_INVERTED(1'b0),\n .IS_RST_INVERTED(1'b0),\n .REF_JITTER1(0.000000),\n .REF_JITTER2(0.010000),\n .SS_EN(\"FALSE\"),\n .SS_MODE(\"CENTER_HIGH\"),\n .SS_MOD_PERIOD(10000),\n .STARTUP_WAIT(\"FALSE\")) \n \\clk_ref_mmcm_gen.mmcm_i \n (.CLKFBIN(mmcm_clkfbout),\n .CLKFBOUT(mmcm_clkfbout),\n .CLKFBOUTB(\\NLW_clk_ref_mmcm_gen.mmcm_i_CLKFBOUTB_UNCONNECTED ),\n .CLKFBSTOPPED(\\NLW_clk_ref_mmcm_gen.mmcm_i_CLKFBSTOPPED_UNCONNECTED ),\n .CLKIN1(mmcm_clk),\n .CLKIN2(1'b0),\n .CLKINSEL(1'b1),\n .CLKINSTOPPED(\\NLW_clk_ref_mmcm_gen.mmcm_i_CLKINSTOPPED_UNCONNECTED ),\n .CLKOUT0(\\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT0_UNCONNECTED ),\n .CLKOUT0B(\\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT0B_UNCONNECTED ),\n .CLKOUT1(clk_ref_mmcm_400),\n .CLKOUT1B(\\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT1B_UNCONNECTED ),\n .CLKOUT2(\\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT2_UNCONNECTED ),\n .CLKOUT2B(\\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT2B_UNCONNECTED ),\n .CLKOUT3(\\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT3_UNCONNECTED ),\n .CLKOUT3B(\\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT3B_UNCONNECTED ),\n .CLKOUT4(\\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT4_UNCONNECTED ),\n .CLKOUT5(\\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT5_UNCONNECTED ),\n .CLKOUT6(\\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT6_UNCONNECTED ),\n .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DCLK(1'b0),\n .DEN(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DO(\\NLW_clk_ref_mmcm_gen.mmcm_i_DO_UNCONNECTED [15:0]),\n .DRDY(\\NLW_clk_ref_mmcm_gen.mmcm_i_DRDY_UNCONNECTED ),\n .DWE(1'b0),\n .LOCKED(\\NLW_clk_ref_mmcm_gen.mmcm_i_LOCKED_UNCONNECTED ),\n .PSCLK(1'b0),\n .PSDONE(\\NLW_clk_ref_mmcm_gen.mmcm_i_PSDONE_UNCONNECTED ),\n .PSEN(1'b0),\n .PSINCDEC(1'b0),\n .PWRDWN(1'b0),\n .RST(AS));\n LUT1 #(\n .INIT(2'h1)) \n \\clk_ref_mmcm_gen.mmcm_i_i_1 \n (.I0(sys_rst),\n .O(AS));\n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDELAYCTRL #(\n .SIM_DEVICE(\"7SERIES\")) \n \\idelayctrl_gen_1.u_idelayctrl_300_400 \n (.RDY(rst_sync_r1_reg),\n .REFCLK(\\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ),\n .RST(rst_ref_1));\n (* syn_maxfan = \"10\" *) \n FDPE #(\n .INIT(1'b1)) \n \\rst_ref_gen_1.rst_ref_sync_r_reg[1][0] \n (.C(\\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ),\n .CE(1'b1),\n .D(1'b0),\n .PRE(AS),\n .Q(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][0] ));\n (* syn_maxfan = \"10\" *) \n FDPE #(\n .INIT(1'b1)) \n \\rst_ref_gen_1.rst_ref_sync_r_reg[1][10] \n (.C(\\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ),\n .CE(1'b1),\n .D(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][9] ),\n .PRE(AS),\n .Q(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][10] ));\n (* syn_maxfan = \"10\" *) \n FDPE #(\n .INIT(1'b1)) \n \\rst_ref_gen_1.rst_ref_sync_r_reg[1][11] \n (.C(\\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ),\n .CE(1'b1),\n .D(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][10] ),\n .PRE(AS),\n .Q(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][11] ));\n (* syn_maxfan = \"10\" *) \n FDPE #(\n .INIT(1'b1)) \n \\rst_ref_gen_1.rst_ref_sync_r_reg[1][12] \n (.C(\\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ),\n .CE(1'b1),\n .D(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][11] ),\n .PRE(AS),\n .Q(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][12] ));\n (* syn_maxfan = \"10\" *) \n FDPE #(\n .INIT(1'b1)) \n \\rst_ref_gen_1.rst_ref_sync_r_reg[1][13] \n (.C(\\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ),\n .CE(1'b1),\n .D(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][12] ),\n .PRE(AS),\n .Q(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][13] ));\n (* syn_maxfan = \"10\" *) \n FDPE #(\n .INIT(1'b1)) \n \\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] \n (.C(\\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ),\n .CE(1'b1),\n .D(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][13] ),\n .PRE(AS),\n .Q(rst_ref_1));\n (* syn_maxfan = \"10\" *) \n FDPE #(\n .INIT(1'b1)) \n \\rst_ref_gen_1.rst_ref_sync_r_reg[1][1] \n (.C(\\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ),\n .CE(1'b1),\n .D(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][0] ),\n .PRE(AS),\n .Q(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][1] ));\n (* syn_maxfan = \"10\" *) \n FDPE #(\n .INIT(1'b1)) \n \\rst_ref_gen_1.rst_ref_sync_r_reg[1][2] \n (.C(\\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ),\n .CE(1'b1),\n .D(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][1] ),\n .PRE(AS),\n .Q(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][2] ));\n (* syn_maxfan = \"10\" *) \n FDPE #(\n .INIT(1'b1)) \n \\rst_ref_gen_1.rst_ref_sync_r_reg[1][3] \n (.C(\\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ),\n .CE(1'b1),\n .D(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][2] ),\n .PRE(AS),\n .Q(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][3] ));\n (* syn_maxfan = \"10\" *) \n FDPE #(\n .INIT(1'b1)) \n \\rst_ref_gen_1.rst_ref_sync_r_reg[1][4] \n (.C(\\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ),\n .CE(1'b1),\n .D(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][3] ),\n .PRE(AS),\n .Q(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][4] ));\n (* syn_maxfan = \"10\" *) \n FDPE #(\n .INIT(1'b1)) \n \\rst_ref_gen_1.rst_ref_sync_r_reg[1][5] \n (.C(\\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ),\n .CE(1'b1),\n .D(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][4] ),\n .PRE(AS),\n .Q(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][5] ));\n (* syn_maxfan = \"10\" *) \n FDPE #(\n .INIT(1'b1)) \n \\rst_ref_gen_1.rst_ref_sync_r_reg[1][6] \n (.C(\\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ),\n .CE(1'b1),\n .D(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][5] ),\n .PRE(AS),\n .Q(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][6] ));\n (* syn_maxfan = \"10\" *) \n FDPE #(\n .INIT(1'b1)) \n \\rst_ref_gen_1.rst_ref_sync_r_reg[1][7] \n (.C(\\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ),\n .CE(1'b1),\n .D(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][6] ),\n .PRE(AS),\n .Q(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][7] ));\n (* syn_maxfan = \"10\" *) \n FDPE #(\n .INIT(1'b1)) \n \\rst_ref_gen_1.rst_ref_sync_r_reg[1][8] \n (.C(\\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ),\n .CE(1'b1),\n .D(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][7] ),\n .PRE(AS),\n .Q(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][8] ));\n (* syn_maxfan = \"10\" *) \n FDPE #(\n .INIT(1'b1)) \n \\rst_ref_gen_1.rst_ref_sync_r_reg[1][9] \n (.C(\\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ),\n .CE(1'b1),\n .D(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][8] ),\n .PRE(AS),\n .Q(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][9] ));\n (* syn_maxfan = \"10\" *) \n FDPE #(\n .INIT(1'b1)) \n \\rst_ref_sync_r_reg[0][0] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(1'b0),\n .PRE(AS),\n .Q(\\rst_ref_sync_r_reg_n_0_[0][0] ));\n (* syn_maxfan = \"10\" *) \n FDPE #(\n .INIT(1'b1)) \n \\rst_ref_sync_r_reg[0][10] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(\\rst_ref_sync_r_reg_n_0_[0][9] ),\n .PRE(AS),\n .Q(\\rst_ref_sync_r_reg_n_0_[0][10] ));\n (* syn_maxfan = \"10\" *) \n FDPE #(\n .INIT(1'b1)) \n \\rst_ref_sync_r_reg[0][11] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(\\rst_ref_sync_r_reg_n_0_[0][10] ),\n .PRE(AS),\n .Q(\\rst_ref_sync_r_reg_n_0_[0][11] ));\n (* syn_maxfan = \"10\" *) \n FDPE #(\n .INIT(1'b1)) \n \\rst_ref_sync_r_reg[0][12] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(\\rst_ref_sync_r_reg_n_0_[0][11] ),\n .PRE(AS),\n .Q(\\rst_ref_sync_r_reg_n_0_[0][12] ));\n (* syn_maxfan = \"10\" *) \n FDPE #(\n .INIT(1'b1)) \n \\rst_ref_sync_r_reg[0][13] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(\\rst_ref_sync_r_reg_n_0_[0][12] ),\n .PRE(AS),\n .Q(\\rst_ref_sync_r_reg_n_0_[0][13] ));\n (* syn_maxfan = \"10\" *) \n FDPE #(\n .INIT(1'b1)) \n \\rst_ref_sync_r_reg[0][14] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(\\rst_ref_sync_r_reg_n_0_[0][13] ),\n .PRE(AS),\n .Q(rst_ref_0));\n (* syn_maxfan = \"10\" *) \n FDPE #(\n .INIT(1'b1)) \n \\rst_ref_sync_r_reg[0][1] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(\\rst_ref_sync_r_reg_n_0_[0][0] ),\n .PRE(AS),\n .Q(\\rst_ref_sync_r_reg_n_0_[0][1] ));\n (* syn_maxfan = \"10\" *) \n FDPE #(\n .INIT(1'b1)) \n \\rst_ref_sync_r_reg[0][2] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(\\rst_ref_sync_r_reg_n_0_[0][1] ),\n .PRE(AS),\n .Q(\\rst_ref_sync_r_reg_n_0_[0][2] ));\n (* syn_maxfan = \"10\" *) \n FDPE #(\n .INIT(1'b1)) \n \\rst_ref_sync_r_reg[0][3] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(\\rst_ref_sync_r_reg_n_0_[0][2] ),\n .PRE(AS),\n .Q(\\rst_ref_sync_r_reg_n_0_[0][3] ));\n (* syn_maxfan = \"10\" *) \n FDPE #(\n .INIT(1'b1)) \n \\rst_ref_sync_r_reg[0][4] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(\\rst_ref_sync_r_reg_n_0_[0][3] ),\n .PRE(AS),\n .Q(\\rst_ref_sync_r_reg_n_0_[0][4] ));\n (* syn_maxfan = \"10\" *) \n FDPE #(\n .INIT(1'b1)) \n \\rst_ref_sync_r_reg[0][5] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(\\rst_ref_sync_r_reg_n_0_[0][4] ),\n .PRE(AS),\n .Q(\\rst_ref_sync_r_reg_n_0_[0][5] ));\n (* syn_maxfan = \"10\" *) \n FDPE #(\n .INIT(1'b1)) \n \\rst_ref_sync_r_reg[0][6] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(\\rst_ref_sync_r_reg_n_0_[0][5] ),\n .PRE(AS),\n .Q(\\rst_ref_sync_r_reg_n_0_[0][6] ));\n (* syn_maxfan = \"10\" *) \n FDPE #(\n .INIT(1'b1)) \n \\rst_ref_sync_r_reg[0][7] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(\\rst_ref_sync_r_reg_n_0_[0][6] ),\n .PRE(AS),\n .Q(\\rst_ref_sync_r_reg_n_0_[0][7] ));\n (* syn_maxfan = \"10\" *) \n FDPE #(\n .INIT(1'b1)) \n \\rst_ref_sync_r_reg[0][8] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(\\rst_ref_sync_r_reg_n_0_[0][7] ),\n .PRE(AS),\n .Q(\\rst_ref_sync_r_reg_n_0_[0][8] ));\n (* syn_maxfan = \"10\" *) \n FDPE #(\n .INIT(1'b1)) \n \\rst_ref_sync_r_reg[0][9] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(\\rst_ref_sync_r_reg_n_0_[0][8] ),\n .PRE(AS),\n .Q(\\rst_ref_sync_r_reg_n_0_[0][9] ));\n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG0\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDELAYCTRL #(\n .SIM_DEVICE(\"7SERIES\")) \n u_idelayctrl_200\n (.RDY(iodelay_ctrl_rdy),\n .REFCLK(mmcm_clk),\n .RST(rst_ref_0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_mc\" *) \nmodule ddr3_ifmig_7series_v4_0_mc\n (insert_maint_r1_lcl_reg,\n app_ref_ack,\n app_zq_ack,\n accept_ns,\n E,\n idle_r_lcl_reg,\n bm_end_r1,\n bm_end_r1_reg,\n bm_end_r1_0,\n bm_end_r1_reg_0,\n mc_cmd,\n \\read_data_indx.rd_data_indx_r_reg[0] ,\n tempmon_sample_en,\n mc_ras_n,\n mc_cs_n,\n mc_odt,\n mc_cke,\n mc_wrdata_en,\n mc_cas_n,\n idle,\n app_sr_active,\n \\read_fifo.tail_r_reg[1] ,\n \\rd_ptr_timing_reg[0] ,\n mc_we_n,\n \\rd_ptr_timing_reg[0]_0 ,\n phy_dout,\n mc_address,\n \\my_empty_reg[7] ,\n bypass__0,\n Q,\n \\cmd_pipe_plus.mc_bank_reg[2]_0 ,\n \\cmd_pipe_plus.mc_bank_reg[2]_1 ,\n pointer_we,\n app_rd_data_end_ns,\n \\write_buffer.wr_buf_out_data_reg[287] ,\n mc_bank,\n \\phy_ctl_wd_i1_reg[22] ,\n \\phy_ctl_wd_i1_reg[21] ,\n \\phy_ctl_wd_i1_reg[18] ,\n \\phy_ctl_wd_i1_reg[17] ,\n \\phy_ctl_wd_i1_reg[20] ,\n \\phy_ctl_wd_i1_reg[19] ,\n \\data_offset_1_i1_reg[5] ,\n \\data_offset_1_i1_reg[4] ,\n \\data_offset_1_i1_reg[1] ,\n \\data_offset_1_i1_reg[0] ,\n \\data_offset_1_i1_reg[3] ,\n \\data_offset_1_i1_reg[2] ,\n CLK,\n p_67_out,\n p_28_out,\n SR,\n hi_priority,\n rstdiv0_sync_r1_reg_rep__0,\n phy_mc_ctl_full,\n of_ctl_full_v,\n maint_prescaler_r1,\n rstdiv0_sync_r1_reg_rep__20,\n init_calib_complete_reg_rep__6,\n app_ref_req,\n app_zq_req,\n \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ,\n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ,\n rstdiv0_sync_r1_reg_rep__21,\n app_hi_pri_r2,\n app_sr_req,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,\n rstdiv0_sync_r1_reg_rep__22,\n \\req_bank_r_lcl_reg[0] ,\n init_calib_complete_reg_rep__7,\n \\req_bank_r_lcl_reg[0]_0 ,\n \\rd_buf_indx.rd_buf_indx_r_reg[4] ,\n \\entry_cnt_reg[2] ,\n \\entry_cnt_reg[2]_0 ,\n cmd,\n use_addr,\n bm_end_r1_reg_1,\n bm_end_r1_reg_2,\n rtp_timer_ns1,\n pass_open_bank_r_lcl_reg,\n \\generate_maint_cmds.insert_maint_r_lcl_reg ,\n \\app_addr_r1_reg[27] ,\n ram_init_done_r,\n \\not_strict_mode.status_ram.rd_buf_we_r1_reg ,\n \\app_addr_r1_reg[12] ,\n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ,\n \\app_addr_r1_reg[9] ,\n \\read_fifo.tail_r_reg[0] ,\n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4] ,\n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ,\n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 ,\n \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10] ,\n \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] ,\n \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0 );\n output insert_maint_r1_lcl_reg;\n output app_ref_ack;\n output app_zq_ack;\n output accept_ns;\n output [0:0]E;\n output [0:0]idle_r_lcl_reg;\n output bm_end_r1;\n output bm_end_r1_reg;\n output bm_end_r1_0;\n output bm_end_r1_reg_0;\n output [1:0]mc_cmd;\n output [0:0]\\read_data_indx.rd_data_indx_r_reg[0] ;\n output tempmon_sample_en;\n output [2:0]mc_ras_n;\n output [0:0]mc_cs_n;\n output [0:0]mc_odt;\n output [0:0]mc_cke;\n output mc_wrdata_en;\n output [2:0]mc_cas_n;\n output idle;\n output app_sr_active;\n output [0:0]\\read_fifo.tail_r_reg[1] ;\n output [2:0]\\rd_ptr_timing_reg[0] ;\n output [2:0]mc_we_n;\n output [3:0]\\rd_ptr_timing_reg[0]_0 ;\n output [1:0]phy_dout;\n output [37:0]mc_address;\n output [1:0]\\my_empty_reg[7] ;\n output bypass__0;\n output [7:0]Q;\n output [2:0]\\cmd_pipe_plus.mc_bank_reg[2]_0 ;\n output [2:0]\\cmd_pipe_plus.mc_bank_reg[2]_1 ;\n output pointer_we;\n output app_rd_data_end_ns;\n output [3:0]\\write_buffer.wr_buf_out_data_reg[287] ;\n output [8:0]mc_bank;\n output \\phy_ctl_wd_i1_reg[22] ;\n output \\phy_ctl_wd_i1_reg[21] ;\n output \\phy_ctl_wd_i1_reg[18] ;\n output \\phy_ctl_wd_i1_reg[17] ;\n output \\phy_ctl_wd_i1_reg[20] ;\n output \\phy_ctl_wd_i1_reg[19] ;\n output \\data_offset_1_i1_reg[5] ;\n output \\data_offset_1_i1_reg[4] ;\n output \\data_offset_1_i1_reg[1] ;\n output \\data_offset_1_i1_reg[0] ;\n output \\data_offset_1_i1_reg[3] ;\n output \\data_offset_1_i1_reg[2] ;\n input CLK;\n input p_67_out;\n input p_28_out;\n input [0:0]SR;\n input hi_priority;\n input rstdiv0_sync_r1_reg_rep__0;\n input phy_mc_ctl_full;\n input [0:0]of_ctl_full_v;\n input maint_prescaler_r1;\n input rstdiv0_sync_r1_reg_rep__20;\n input init_calib_complete_reg_rep__6;\n input app_ref_req;\n input app_zq_req;\n input [5:0]\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ;\n input [5:0]\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ;\n input rstdiv0_sync_r1_reg_rep__21;\n input app_hi_pri_r2;\n input app_sr_req;\n input \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n input rstdiv0_sync_r1_reg_rep__22;\n input \\req_bank_r_lcl_reg[0] ;\n input init_calib_complete_reg_rep__7;\n input \\req_bank_r_lcl_reg[0]_0 ;\n input [4:0]\\rd_buf_indx.rd_buf_indx_r_reg[4] ;\n input \\entry_cnt_reg[2] ;\n input \\entry_cnt_reg[2]_0 ;\n input [1:0]cmd;\n input use_addr;\n input bm_end_r1_reg_1;\n input bm_end_r1_reg_2;\n input rtp_timer_ns1;\n input pass_open_bank_r_lcl_reg;\n input \\generate_maint_cmds.insert_maint_r_lcl_reg ;\n input [14:0]\\app_addr_r1_reg[27] ;\n input ram_init_done_r;\n input [0:0]\\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n input [2:0]\\app_addr_r1_reg[12] ;\n input [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n input [6:0]\\app_addr_r1_reg[9] ;\n input \\read_fifo.tail_r_reg[0] ;\n input \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4] ;\n input \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ;\n input \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 ;\n input \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10] ;\n input \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] ;\n input \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0 ;\n\n wire CLK;\n wire [0:0]E;\n wire [7:0]Q;\n wire [0:0]SR;\n wire accept_ns;\n wire [2:0]\\app_addr_r1_reg[12] ;\n wire [14:0]\\app_addr_r1_reg[27] ;\n wire [6:0]\\app_addr_r1_reg[9] ;\n wire app_hi_pri_r2;\n wire app_rd_data_end_ns;\n wire app_ref_ack;\n wire app_ref_req;\n wire app_sr_active;\n wire app_sr_req;\n wire app_zq_ack;\n wire app_zq_req;\n wire \\arb_mux0/arb_select0/cke_r ;\n wire \\bank_cntrl[0].bank0/auto_pre_r ;\n wire \\bank_cntrl[0].bank0/bank_queue0/order_q_r ;\n wire \\bank_cntrl[0].bank0/bank_queue0/pre_bm_end_r ;\n wire \\bank_cntrl[0].bank0/bank_queue0/q_entry_r ;\n wire \\bank_cntrl[0].bank0/bank_queue0/set_order_q ;\n wire \\bank_cntrl[0].bank0/bank_state0/override_demand_ns ;\n wire \\bank_cntrl[0].bank0/bank_state0/req_bank_rdy_ns ;\n wire [1:0]\\bank_cntrl[0].bank0/bank_state0/rtp_timer_r ;\n wire \\bank_cntrl[0].bank0/pre_wait_r ;\n wire \\bank_cntrl[0].bank0/row_hit_r ;\n wire \\bank_cntrl[0].bank0/tail_r ;\n wire \\bank_cntrl[0].bank0/wait_for_maint_r ;\n wire \\bank_cntrl[1].bank0/auto_pre_r ;\n wire \\bank_cntrl[1].bank0/bank_queue0/clear_req ;\n wire \\bank_cntrl[1].bank0/bank_queue0/order_q_r ;\n wire \\bank_cntrl[1].bank0/bank_queue0/q_entry_r ;\n wire \\bank_cntrl[1].bank0/bank_queue0/set_order_q ;\n wire [2:0]\\bank_cntrl[1].bank0/bank_state0/ras_timer_r ;\n wire \\bank_cntrl[1].bank0/bank_state0/req_bank_rdy_ns ;\n wire \\bank_cntrl[1].bank0/q_has_priority ;\n wire \\bank_cntrl[1].bank0/q_has_rd ;\n wire [2:2]\\bank_cntrl[1].bank0/rb_hit_busies_r ;\n wire \\bank_cntrl[1].bank0/row_hit_r ;\n wire \\bank_cntrl[1].bank0/tail_r ;\n wire \\bank_cntrl[1].bank0/wait_for_maint_r ;\n wire \\bank_common0/periodic_rd_cntr_r ;\n wire [4:0]\\bank_common0/rfc_zq_xsdll_timer_r ;\n wire bank_mach0_n_128;\n wire bank_mach0_n_129;\n wire bank_mach0_n_130;\n wire bank_mach0_n_134;\n wire bank_mach0_n_135;\n wire bank_mach0_n_136;\n wire bank_mach0_n_140;\n wire bank_mach0_n_141;\n wire bank_mach0_n_142;\n wire bank_mach0_n_144;\n wire bank_mach0_n_145;\n wire bank_mach0_n_146;\n wire bank_mach0_n_147;\n wire bank_mach0_n_148;\n wire bank_mach0_n_149;\n wire bank_mach0_n_150;\n wire bank_mach0_n_151;\n wire bank_mach0_n_152;\n wire bank_mach0_n_153;\n wire bank_mach0_n_154;\n wire bank_mach0_n_155;\n wire bank_mach0_n_156;\n wire bank_mach0_n_157;\n wire bank_mach0_n_158;\n wire bank_mach0_n_159;\n wire bank_mach0_n_160;\n wire bank_mach0_n_161;\n wire bank_mach0_n_162;\n wire bank_mach0_n_163;\n wire bank_mach0_n_164;\n wire bank_mach0_n_165;\n wire bank_mach0_n_166;\n wire bank_mach0_n_44;\n wire bank_mach0_n_52;\n wire bank_mach0_n_59;\n wire bank_mach0_n_65;\n wire bank_mach0_n_69;\n wire bank_mach0_n_71;\n wire bank_mach0_n_72;\n wire bank_mach0_n_73;\n wire bank_mach0_n_74;\n wire bank_mach0_n_76;\n wire bank_mach0_n_77;\n wire bank_mach0_n_78;\n wire bank_mach0_n_82;\n wire bank_mach0_n_83;\n wire bank_mach0_n_86;\n wire bank_mach0_n_87;\n wire bm_end_r1;\n wire bm_end_r1_0;\n wire bm_end_r1_reg;\n wire bm_end_r1_reg_0;\n wire bm_end_r1_reg_1;\n wire bm_end_r1_reg_2;\n wire bypass__0;\n wire [1:0]cmd;\n wire [2:0]\\cmd_pipe_plus.mc_bank_reg[2]_0 ;\n wire [2:0]\\cmd_pipe_plus.mc_bank_reg[2]_1 ;\n wire \\cmd_pipe_plus.mc_data_offset_2_reg_n_0_[3] ;\n wire [4:0]col_data_buf_addr;\n wire col_mach0_n_16;\n wire col_mach0_n_22;\n wire col_periodic_rd;\n wire col_rd_wr;\n wire col_rd_wr_r1;\n wire col_rd_wr_r2;\n wire [3:0]col_wr_data_buf_addr_r;\n wire \\data_offset_1_i1_reg[0] ;\n wire \\data_offset_1_i1_reg[1] ;\n wire \\data_offset_1_i1_reg[2] ;\n wire \\data_offset_1_i1_reg[3] ;\n wire \\data_offset_1_i1_reg[4] ;\n wire \\data_offset_1_i1_reg[5] ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n wire \\entry_cnt_reg[2] ;\n wire \\entry_cnt_reg[2]_0 ;\n wire [2:0]faw_cnt_r;\n wire \\generate_maint_cmds.insert_maint_r_lcl_reg ;\n wire [1:0]head_r;\n wire hi_priority;\n wire i___0_n_0;\n wire i___10_n_0;\n wire i___11_n_0;\n wire i___12_n_0;\n wire i___13_n_0;\n wire i___14_n_0;\n wire i___15_n_0;\n wire i___16_n_0;\n wire i___17_n_0;\n wire i___18_n_0;\n wire i___19_n_0;\n wire i___1_n_0;\n wire i___20_n_0;\n wire i___21_n_0;\n wire i___22_n_0;\n wire i___23_n_0;\n wire i___24_n_0;\n wire i___25_n_0;\n wire i___26_n_0;\n wire i___27_n_0;\n wire i___28_n_0;\n wire i___29_n_0;\n wire i___2_n_0;\n wire i___30_n_0;\n wire i___31_n_0;\n wire i___32_n_0;\n wire i___33_n_0;\n wire i___34_n_0;\n wire i___35_n_0;\n wire i___36_n_0;\n wire i___37_n_0;\n wire i___38_n_0;\n wire i___39_n_0;\n wire i___3_n_0;\n wire i___40_n_0;\n wire i___41_n_0;\n wire i___42_n_0;\n wire i___43_n_0;\n wire i___44_n_0;\n wire i___45_n_0;\n wire i___46_n_0;\n wire i___47_n_0;\n wire i___48_n_0;\n wire i___49_n_0;\n wire i___4_n_0;\n wire i___50_n_0;\n wire i___51_n_0;\n wire i___52_n_0;\n wire i___53_n_0;\n wire i___54_n_0;\n wire i___55_n_0;\n wire i___56_n_0;\n wire i___57_n_0;\n wire i___58_n_0;\n wire i___59_n_0;\n wire i___5_n_0;\n wire i___60_n_0;\n wire i___6_n_0;\n wire i___7_n_0;\n wire i___8_n_0;\n wire i___9_n_0;\n wire idle;\n wire [1:0]idle_r;\n wire [0:0]idle_r_lcl_reg;\n wire inhbt_act_faw_r;\n wire init_calib_complete_reg_rep__6;\n wire init_calib_complete_reg_rep__7;\n wire insert_maint_r1;\n wire insert_maint_r1_lcl_reg;\n wire maint_prescaler_r1;\n wire maint_ref_zq_wip;\n wire maint_req_r;\n wire maint_sre_r;\n wire maint_srx_r;\n wire maint_wip_r;\n wire maint_zq_r;\n wire [37:0]mc_address;\n wire [25:0]mc_address_ns;\n wire [8:0]mc_bank;\n wire [5:0]mc_bank_ns;\n wire [2:0]mc_cas_n;\n wire [1:0]mc_cas_n_ns;\n wire [0:0]mc_cke;\n wire [1:1]mc_cke_ns;\n wire [1:0]mc_cmd;\n wire [0:0]mc_cs_n;\n wire [0:0]mc_cs_n_ns;\n wire [3:3]mc_data_offset_2_ns;\n wire [0:0]mc_odt;\n wire [0:0]mc_odt_ns;\n wire [2:0]mc_ras_n;\n wire [2:0]mc_ras_n_ns;\n wire mc_ref_zq_wip_ns;\n wire [2:0]mc_we_n;\n wire [1:0]mc_we_n_ns;\n wire mc_wrdata_en;\n wire [1:0]\\my_empty_reg[7] ;\n wire [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n wire [0:0]\\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n wire [0:0]of_ctl_full_v;\n wire ordered_r_lcl;\n wire p_13_out;\n wire p_28_out;\n wire p_52_out;\n wire p_67_out;\n wire pass_open_bank_r_lcl_reg;\n wire periodic_rd_ack_r;\n wire periodic_rd_r;\n wire \\phy_ctl_wd_i1_reg[17] ;\n wire \\phy_ctl_wd_i1_reg[18] ;\n wire \\phy_ctl_wd_i1_reg[19] ;\n wire \\phy_ctl_wd_i1_reg[20] ;\n wire \\phy_ctl_wd_i1_reg[21] ;\n wire \\phy_ctl_wd_i1_reg[22] ;\n wire [1:0]phy_dout;\n wire phy_mc_ctl_full;\n wire pointer_we;\n wire ram_init_done_r;\n wire \\rank_cntrl[0].rank_cntrl0/act_delayed ;\n wire \\rank_cntrl[0].rank_cntrl0/act_this_rank ;\n wire \\rank_cntrl[0].rank_cntrl0/periodic_rd_cntr1_r ;\n wire \\rank_cntrl[0].rank_cntrl0/periodic_rd_request_r ;\n wire \\rank_cntrl[0].rank_cntrl0/read_this_rank ;\n wire \\rank_cntrl[0].rank_cntrl0/read_this_rank_r ;\n wire \\rank_cntrl[0].rank_cntrl0/refresh_bank_r ;\n wire \\rank_common0/app_ref_r ;\n wire \\rank_common0/app_zq_r ;\n wire [2:0]\\rank_common0/maint_grant_r ;\n wire [1:0]\\rank_common0/maint_prescaler.maint_prescaler_r_reg__0 ;\n wire \\rank_common0/maint_prescaler_tick_ns ;\n wire [2:0]\\rank_common0/maintenance_request.maint_arb0/last_master_r ;\n wire \\rank_common0/new_maint_rank_r ;\n wire \\rank_common0/periodic_rd_grant_r ;\n wire \\rank_common0/periodic_rd_r_cnt ;\n wire [1:0]\\rank_common0/refresh_timer.refresh_timer_r_reg__0 ;\n wire \\rank_common0/sre_request_r ;\n wire \\rank_common0/upd_last_master_r ;\n wire \\rank_common0/zq_request_r ;\n wire \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ;\n wire \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 ;\n wire \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4] ;\n wire [5:0]\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ;\n wire \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10] ;\n wire [5:0]\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ;\n wire \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] ;\n wire \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0 ;\n wire rank_mach0_n_27;\n wire rank_mach0_n_30;\n wire rank_mach0_n_34;\n wire rank_mach0_n_40;\n wire rank_mach0_n_42;\n wire rank_mach0_n_43;\n wire rank_mach0_n_44;\n wire rank_mach0_n_45;\n wire rank_mach0_n_46;\n wire rank_mach0_n_47;\n wire rank_mach0_n_48;\n wire rank_mach0_n_49;\n wire rank_mach0_n_5;\n wire rank_mach0_n_50;\n wire rank_mach0_n_51;\n wire rank_mach0_n_52;\n wire rank_mach0_n_53;\n wire rank_mach0_n_54;\n wire rank_mach0_n_55;\n wire rank_mach0_n_56;\n wire rank_mach0_n_57;\n wire rank_mach0_n_58;\n wire rank_mach0_n_59;\n wire rank_mach0_n_60;\n wire rank_mach0_n_61;\n wire rank_mach0_n_62;\n wire rank_mach0_n_63;\n wire rank_mach0_n_64;\n wire rank_mach0_n_68;\n wire [1:1]rb_hit_busy_r;\n wire [4:0]\\rd_buf_indx.rd_buf_indx_r_reg[4] ;\n wire [2:0]\\rd_ptr_timing_reg[0] ;\n wire [3:0]\\rd_ptr_timing_reg[0]_0 ;\n wire [1:0]rd_wr_r;\n wire [0:0]\\read_data_indx.rd_data_indx_r_reg[0] ;\n wire \\read_fifo.tail_r_reg[0] ;\n wire [0:0]\\read_fifo.tail_r_reg[1] ;\n wire \\req_bank_r_lcl_reg[0] ;\n wire \\req_bank_r_lcl_reg[0]_0 ;\n wire [1:0]req_wr_r;\n wire [0:0]rfc_zq_xsdll_timer_ns;\n wire rnk_config_valid_r;\n wire [0:0]row_cmd_wr;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire rstdiv0_sync_r1_reg_rep__22;\n wire rtp_timer_ns1;\n wire [1:1]rtw_cnt_r;\n wire [1:0]sending_col;\n wire [1:0]sending_row;\n wire sent_col;\n wire sent_col_r2;\n wire [2:1]tail_r;\n wire tempmon_sample_en;\n wire use_addr;\n wire was_wr;\n wire wr_data_en_ns;\n wire [1:0]wr_this_rank_r;\n wire [3:0]\\write_buffer.wr_buf_out_data_reg[287] ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_0 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_1 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_2 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_3 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_4 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_5 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_6 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_7 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_0 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_1 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_2 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_3 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_4 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_5 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_6 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_7 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_1 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_2 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_3 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_4 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_5 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_6 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_7 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_0 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_1 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_2 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_3 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_4 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_5 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_6 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_7 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_0 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_1 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_2 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_3 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_4 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_5 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_6 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_7 ;\n wire [3:3]\\NLW_zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_CO_UNCONNECTED ;\n\n ddr3_ifmig_7series_v4_0_bank_mach bank_mach0\n (.CLK(CLK),\n .D(mc_we_n_ns),\n .DIC(col_periodic_rd),\n .E(bank_mach0_n_145),\n .Q(sending_col),\n .SR(SR),\n .accept_ns(accept_ns),\n .act_this_rank(\\rank_cntrl[0].rank_cntrl0/act_this_rank ),\n .\\act_this_rank_r_reg[0] (row_cmd_wr),\n .\\app_addr_r1_reg[12] (\\app_addr_r1_reg[12] ),\n .\\app_addr_r1_reg[27] (\\app_addr_r1_reg[27] ),\n .\\app_addr_r1_reg[9] (\\app_addr_r1_reg[9] ),\n .app_hi_pri_r2(app_hi_pri_r2),\n .auto_pre_r(\\bank_cntrl[0].bank0/auto_pre_r ),\n .auto_pre_r_5(\\bank_cntrl[1].bank0/auto_pre_r ),\n .auto_pre_r_lcl_reg(bank_mach0_n_135),\n .auto_pre_r_lcl_reg_0(bank_mach0_n_136),\n .auto_pre_r_lcl_reg_1(i___36_n_0),\n .auto_pre_r_lcl_reg_2(i___13_n_0),\n .bm_end_r1(bm_end_r1),\n .bm_end_r1_0(bm_end_r1_0),\n .bm_end_r1_reg(bm_end_r1_reg),\n .bm_end_r1_reg_0(bm_end_r1_reg_0),\n .bm_end_r1_reg_1(bm_end_r1_reg_1),\n .bm_end_r1_reg_2(bm_end_r1_reg_2),\n .cke_r(\\arb_mux0/arb_select0/cke_r ),\n .clear_req(\\bank_cntrl[1].bank0/bank_queue0/clear_req ),\n .cmd(cmd),\n .\\cmd_pipe_plus.mc_address_reg[0] (sending_row),\n .\\cmd_pipe_plus.mc_address_reg[25] ({mc_address_ns[25:18],mc_address_ns[14:0]}),\n .\\cmd_pipe_plus.mc_address_reg[30] (bank_mach0_n_163),\n .\\cmd_pipe_plus.mc_address_reg[31] (bank_mach0_n_162),\n .\\cmd_pipe_plus.mc_address_reg[32] (bank_mach0_n_161),\n .\\cmd_pipe_plus.mc_address_reg[33] (bank_mach0_n_160),\n .\\cmd_pipe_plus.mc_address_reg[34] (bank_mach0_n_159),\n .\\cmd_pipe_plus.mc_address_reg[35] (bank_mach0_n_158),\n .\\cmd_pipe_plus.mc_address_reg[36] (bank_mach0_n_157),\n .\\cmd_pipe_plus.mc_address_reg[37] (bank_mach0_n_156),\n .\\cmd_pipe_plus.mc_address_reg[38] (bank_mach0_n_155),\n .\\cmd_pipe_plus.mc_address_reg[39] (bank_mach0_n_154),\n .\\cmd_pipe_plus.mc_address_reg[40] (bank_mach0_n_146),\n .\\cmd_pipe_plus.mc_address_reg[41] (bank_mach0_n_153),\n .\\cmd_pipe_plus.mc_address_reg[42] (bank_mach0_n_152),\n .\\cmd_pipe_plus.mc_address_reg[43] (bank_mach0_n_151),\n .\\cmd_pipe_plus.mc_address_reg[44] (bank_mach0_n_150),\n .\\cmd_pipe_plus.mc_bank_reg[2] (\\cmd_pipe_plus.mc_bank_reg[2]_0 ),\n .\\cmd_pipe_plus.mc_bank_reg[2]_0 (\\cmd_pipe_plus.mc_bank_reg[2]_1 ),\n .\\cmd_pipe_plus.mc_bank_reg[5] (mc_bank_ns),\n .\\cmd_pipe_plus.mc_bank_reg[6] (bank_mach0_n_149),\n .\\cmd_pipe_plus.mc_bank_reg[7] (bank_mach0_n_148),\n .\\cmd_pipe_plus.mc_bank_reg[8] (bank_mach0_n_147),\n .\\cmd_pipe_plus.mc_cas_n_reg[2] (bank_mach0_n_165),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[0] (bank_mach0_n_166),\n .\\cmd_pipe_plus.mc_data_offset_2_reg[3] (\\cmd_pipe_plus.mc_data_offset_2_reg_n_0_[3] ),\n .\\cmd_pipe_plus.mc_we_n_reg[2] (bank_mach0_n_164),\n .col_data_buf_addr(col_data_buf_addr),\n .col_rd_wr(col_rd_wr),\n .col_rd_wr_r1(col_rd_wr_r1),\n .\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] (col_wr_data_buf_addr_r),\n .\\entry_cnt_reg[2] (\\entry_cnt_reg[2] ),\n .\\entry_cnt_reg[2]_0 (\\entry_cnt_reg[2]_0 ),\n .\\generate_maint_cmds.insert_maint_r_lcl_reg (rank_mach0_n_40),\n .\\generate_maint_cmds.insert_maint_r_lcl_reg_0 (\\generate_maint_cmds.insert_maint_r_lcl_reg ),\n .\\grant_r_reg[1] (i___41_n_0),\n .head_r(head_r),\n .head_r_lcl_reg(bank_mach0_n_71),\n .head_r_lcl_reg_0(bank_mach0_n_77),\n .head_r_lcl_reg_1(bank_mach0_n_78),\n .head_r_lcl_reg_2(bank_mach0_n_134),\n .head_r_lcl_reg_3(i___6_n_0),\n .head_r_lcl_reg_4(i___7_n_0),\n .hi_priority(hi_priority),\n .idle_r(idle_r),\n .idle_r_lcl_reg(E),\n .idle_r_lcl_reg_0(idle_r_lcl_reg),\n .idle_r_lcl_reg_1(i___4_n_0),\n .idle_r_lcl_reg_2(i___11_n_0),\n .\\inhbt_act_faw.inhbt_act_faw_r_reg (bank_mach0_n_144),\n .inhbt_act_faw_r(inhbt_act_faw_r),\n .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6),\n .insert_maint_r1(insert_maint_r1),\n .insert_maint_r1_lcl_reg(insert_maint_r1_lcl_reg),\n .\\maint_controller.maint_wip_r_lcl_reg (i___45_n_0),\n .maint_req_r(maint_req_r),\n .maint_srx_r(maint_srx_r),\n .maint_wip_r(maint_wip_r),\n .maint_zq_r(maint_zq_r),\n .\\maintenance_request.maint_zq_r_lcl_reg (rank_mach0_n_42),\n .mc_cas_n_ns(mc_cas_n_ns),\n .mc_cke_ns(mc_cke_ns),\n .mc_cs_n_ns(mc_cs_n_ns),\n .mc_data_offset_2_ns(mc_data_offset_2_ns),\n .mc_odt_ns(mc_odt_ns),\n .mc_ras_n_ns({mc_ras_n_ns[2],mc_ras_n_ns[0]}),\n .\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),\n .of_ctl_full_v(of_ctl_full_v),\n .order_q_r(\\bank_cntrl[0].bank0/bank_queue0/order_q_r ),\n .order_q_r_6(\\bank_cntrl[1].bank0/bank_queue0/order_q_r ),\n .\\order_q_r_reg[0] (bank_mach0_n_52),\n .ordered_r_lcl(ordered_r_lcl),\n .ordered_r_lcl_reg(i___8_n_0),\n .ordered_r_lcl_reg_0(i___9_n_0),\n .ordered_r_lcl_reg_1(i___10_n_0),\n .ordered_r_lcl_reg_2(i___14_n_0),\n .override_demand_ns(\\bank_cntrl[0].bank0/bank_state0/override_demand_ns ),\n .p_13_out(p_13_out),\n .p_28_out(p_28_out),\n .p_52_out(p_52_out),\n .p_67_out(p_67_out),\n .pass_open_bank_r_lcl_reg(bank_mach0_n_82),\n .pass_open_bank_r_lcl_reg_0(bank_mach0_n_141),\n .pass_open_bank_r_lcl_reg_1(i___37_n_0),\n .pass_open_bank_r_lcl_reg_2(pass_open_bank_r_lcl_reg),\n .pass_open_bank_r_lcl_reg_3(i___0_n_0),\n .periodic_rd_ack_r(periodic_rd_ack_r),\n .periodic_rd_cntr_r(\\bank_common0/periodic_rd_cntr_r ),\n .\\periodic_rd_generation.periodic_rd_timer_r_reg[0] (bank_mach0_n_59),\n .periodic_rd_r(periodic_rd_r),\n .\\periodic_read_request.periodic_rd_r_lcl_reg (i___40_n_0),\n .phy_mc_ctl_full(phy_mc_ctl_full),\n .pre_bm_end_r(\\bank_cntrl[0].bank0/bank_queue0/pre_bm_end_r ),\n .pre_wait_r(\\bank_cntrl[0].bank0/pre_wait_r ),\n .q_entry_r(\\bank_cntrl[0].bank0/bank_queue0/q_entry_r ),\n .q_entry_r_4(\\bank_cntrl[1].bank0/bank_queue0/q_entry_r ),\n .\\q_entry_r_reg[0] (bank_mach0_n_73),\n .\\q_entry_r_reg[0]_0 (bank_mach0_n_74),\n .\\q_entry_r_reg[0]_1 (bank_mach0_n_83),\n .\\q_entry_r_reg[0]_2 (bank_mach0_n_87),\n .\\q_entry_r_reg[0]_3 (i___5_n_0),\n .\\q_entry_r_reg[0]_4 (i___12_n_0),\n .q_has_priority(\\bank_cntrl[1].bank0/q_has_priority ),\n .q_has_priority_r_reg(rb_hit_busy_r),\n .q_has_priority_r_reg_0(bank_mach0_n_72),\n .q_has_priority_r_reg_1(i___35_n_0),\n .q_has_rd(\\bank_cntrl[1].bank0/q_has_rd ),\n .q_has_rd_r_reg(bank_mach0_n_86),\n .q_has_rd_r_reg_0(i___34_n_0),\n .\\ras_timer_r_reg[2] (i___44_n_0),\n .ras_timer_zero_r_reg(\\bank_cntrl[1].bank0/bank_state0/ras_timer_r ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] (i___33_n_0),\n .rb_hit_busies_r(\\bank_cntrl[1].bank0/rb_hit_busies_r ),\n .\\rcd_timer_gt_2.rcd_timer_r_reg[0] (bank_mach0_n_44),\n .rd_wr_r(rd_wr_r),\n .read_this_rank(\\rank_cntrl[0].rank_cntrl0/read_this_rank ),\n .read_this_rank_r(\\rank_cntrl[0].rank_cntrl0/read_this_rank_r ),\n .\\req_bank_r_lcl_reg[0] (\\req_bank_r_lcl_reg[0]_0 ),\n .req_bank_rdy_ns(\\bank_cntrl[0].bank0/bank_state0/req_bank_rdy_ns ),\n .req_bank_rdy_ns_1(\\bank_cntrl[1].bank0/bank_state0/req_bank_rdy_ns ),\n .req_bank_rdy_r_reg(bank_mach0_n_128),\n .req_wr_r(req_wr_r),\n .req_wr_r_lcl_reg(i___38_n_0),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ({i___20_n_0,i___19_n_0,rfc_zq_xsdll_timer_ns}),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6] ({\\bank_common0/rfc_zq_xsdll_timer_r [4],\\bank_common0/rfc_zq_xsdll_timer_r [1:0]}),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 (bank_mach0_n_140),\n .\\rnk_config_strobe_r_reg[0] (bank_mach0_n_129),\n .\\rnk_config_strobe_r_reg[0]_0 (bank_mach0_n_130),\n .rnk_config_valid_r(rnk_config_valid_r),\n .rnk_config_valid_r_lcl_reg(i___43_n_0),\n .row_hit_r(\\bank_cntrl[0].bank0/row_hit_r ),\n .row_hit_r_0(\\bank_cntrl[1].bank0/row_hit_r ),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .rtp_timer_ns1(rtp_timer_ns1),\n .rtp_timer_r(\\bank_cntrl[0].bank0/bank_state0/rtp_timer_r ),\n .\\rtw_timer.rtw_cnt_r_reg[1] (bank_mach0_n_65),\n .\\rtw_timer.rtw_cnt_r_reg[1]_0 (rtw_cnt_r),\n .sent_col(sent_col),\n .set_order_q(\\bank_cntrl[1].bank0/bank_queue0/set_order_q ),\n .set_order_q_7(\\bank_cntrl[0].bank0/bank_queue0/set_order_q ),\n .tail_r(\\bank_cntrl[0].bank0/tail_r ),\n .tail_r_3(\\bank_cntrl[1].bank0/tail_r ),\n .use_addr(use_addr),\n .wait_for_maint_r(\\bank_cntrl[0].bank0/wait_for_maint_r ),\n .wait_for_maint_r_2(\\bank_cntrl[1].bank0/wait_for_maint_r ),\n .wait_for_maint_r_lcl_reg(bank_mach0_n_69),\n .wait_for_maint_r_lcl_reg_0(bank_mach0_n_76),\n .was_wr(was_wr),\n .wr_this_rank_r(wr_this_rank_r),\n .\\wtr_timer.wtr_cnt_r_reg[1] (rank_mach0_n_68),\n .\\wtr_timer.wtr_cnt_r_reg[2] (bank_mach0_n_142));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_address_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[0]),\n .Q(mc_address[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_address_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[10]),\n .Q(mc_address[10]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_address_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[11]),\n .Q(mc_address[11]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_address_reg[12] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[12]),\n .Q(mc_address[12]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_address_reg[13] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[13]),\n .Q(mc_address[13]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_address_reg[14] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[14]),\n .Q(mc_address[14]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_address_reg[18] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[18]),\n .Q(mc_address[15]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_address_reg[19] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[19]),\n .Q(mc_address[16]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_address_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[1]),\n .Q(mc_address[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_address_reg[20] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[20]),\n .Q(mc_address[17]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_address_reg[21] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[21]),\n .Q(mc_address[18]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_address_reg[22] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[22]),\n .Q(mc_address[19]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_address_reg[23] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[23]),\n .Q(mc_address[20]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_address_reg[24] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[24]),\n .Q(mc_address[21]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_address_reg[25] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[25]),\n .Q(mc_address[22]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_address_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[2]),\n .Q(mc_address[2]),\n .R(1'b0));\n FDSE #(\n .INIT(1'b1)) \n \\cmd_pipe_plus.mc_address_reg[30] \n (.C(CLK),\n .CE(1'b1),\n .D(bank_mach0_n_163),\n .Q(mc_address[23]),\n .S(mc_ras_n_ns[2]));\n FDSE #(\n .INIT(1'b1)) \n \\cmd_pipe_plus.mc_address_reg[31] \n (.C(CLK),\n .CE(1'b1),\n .D(bank_mach0_n_162),\n .Q(mc_address[24]),\n .S(mc_ras_n_ns[2]));\n FDSE #(\n .INIT(1'b1)) \n \\cmd_pipe_plus.mc_address_reg[32] \n (.C(CLK),\n .CE(1'b1),\n .D(bank_mach0_n_161),\n .Q(mc_address[25]),\n .S(mc_ras_n_ns[2]));\n FDSE #(\n .INIT(1'b1)) \n \\cmd_pipe_plus.mc_address_reg[33] \n (.C(CLK),\n .CE(1'b1),\n .D(bank_mach0_n_160),\n .Q(mc_address[26]),\n .S(mc_ras_n_ns[2]));\n FDSE #(\n .INIT(1'b1)) \n \\cmd_pipe_plus.mc_address_reg[34] \n (.C(CLK),\n .CE(1'b1),\n .D(bank_mach0_n_159),\n .Q(mc_address[27]),\n .S(mc_ras_n_ns[2]));\n FDSE #(\n .INIT(1'b1)) \n \\cmd_pipe_plus.mc_address_reg[35] \n (.C(CLK),\n .CE(1'b1),\n .D(bank_mach0_n_158),\n .Q(mc_address[28]),\n .S(mc_ras_n_ns[2]));\n FDSE #(\n .INIT(1'b1)) \n \\cmd_pipe_plus.mc_address_reg[36] \n (.C(CLK),\n .CE(1'b1),\n .D(bank_mach0_n_157),\n .Q(mc_address[29]),\n .S(mc_ras_n_ns[2]));\n FDSE #(\n .INIT(1'b1)) \n \\cmd_pipe_plus.mc_address_reg[37] \n (.C(CLK),\n .CE(1'b1),\n .D(bank_mach0_n_156),\n .Q(mc_address[30]),\n .S(mc_ras_n_ns[2]));\n FDSE #(\n .INIT(1'b1)) \n \\cmd_pipe_plus.mc_address_reg[38] \n (.C(CLK),\n .CE(1'b1),\n .D(bank_mach0_n_155),\n .Q(mc_address[31]),\n .S(mc_ras_n_ns[2]));\n FDSE #(\n .INIT(1'b1)) \n \\cmd_pipe_plus.mc_address_reg[39] \n (.C(CLK),\n .CE(1'b1),\n .D(bank_mach0_n_154),\n .Q(mc_address[32]),\n .S(mc_ras_n_ns[2]));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_address_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[3]),\n .Q(mc_address[3]),\n .R(1'b0));\n FDSE #(\n .INIT(1'b1)) \n \\cmd_pipe_plus.mc_address_reg[40] \n (.C(CLK),\n .CE(1'b1),\n .D(bank_mach0_n_146),\n .Q(mc_address[33]),\n .S(mc_ras_n_ns[2]));\n FDSE #(\n .INIT(1'b1)) \n \\cmd_pipe_plus.mc_address_reg[41] \n (.C(CLK),\n .CE(1'b1),\n .D(bank_mach0_n_153),\n .Q(mc_address[34]),\n .S(mc_ras_n_ns[2]));\n FDSE #(\n .INIT(1'b1)) \n \\cmd_pipe_plus.mc_address_reg[42] \n (.C(CLK),\n .CE(1'b1),\n .D(bank_mach0_n_152),\n .Q(mc_address[35]),\n .S(mc_ras_n_ns[2]));\n FDSE #(\n .INIT(1'b1)) \n \\cmd_pipe_plus.mc_address_reg[43] \n (.C(CLK),\n .CE(1'b1),\n .D(bank_mach0_n_151),\n .Q(mc_address[36]),\n .S(mc_ras_n_ns[2]));\n FDSE #(\n .INIT(1'b1)) \n \\cmd_pipe_plus.mc_address_reg[44] \n (.C(CLK),\n .CE(1'b1),\n .D(bank_mach0_n_150),\n .Q(mc_address[37]),\n .S(mc_ras_n_ns[2]));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_address_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[4]),\n .Q(mc_address[4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_address_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[5]),\n .Q(mc_address[5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_address_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[6]),\n .Q(mc_address[6]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_address_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[7]),\n .Q(mc_address[7]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_address_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[8]),\n .Q(mc_address[8]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_address_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[9]),\n .Q(mc_address[9]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_bank_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_bank_ns[0]),\n .Q(mc_bank[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_bank_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_bank_ns[1]),\n .Q(mc_bank[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_bank_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_bank_ns[2]),\n .Q(mc_bank[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_bank_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_bank_ns[3]),\n .Q(mc_bank[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_bank_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_bank_ns[4]),\n .Q(mc_bank[4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_bank_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_bank_ns[5]),\n .Q(mc_bank[5]),\n .R(1'b0));\n FDSE #(\n .INIT(1'b1)) \n \\cmd_pipe_plus.mc_bank_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(bank_mach0_n_149),\n .Q(mc_bank[6]),\n .S(mc_ras_n_ns[2]));\n FDSE #(\n .INIT(1'b1)) \n \\cmd_pipe_plus.mc_bank_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(bank_mach0_n_148),\n .Q(mc_bank[7]),\n .S(mc_ras_n_ns[2]));\n FDSE #(\n .INIT(1'b1)) \n \\cmd_pipe_plus.mc_bank_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(bank_mach0_n_147),\n .Q(mc_bank[8]),\n .S(mc_ras_n_ns[2]));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_cas_n_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_cas_n_ns[0]),\n .Q(mc_cas_n[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_cas_n_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_cas_n_ns[1]),\n .Q(mc_cas_n[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_cas_n_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(bank_mach0_n_165),\n .Q(mc_cas_n[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_cke_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_cke_ns),\n .Q(mc_cke),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_cmd_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(sent_col),\n .Q(mc_cmd[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_cmd_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(i___32_n_0),\n .Q(mc_cmd[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_cs_n_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_cs_n_ns),\n .Q(mc_cs_n),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_data_offset_1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0 ),\n .Q(\\data_offset_1_i1_reg[0] ),\n .R(bank_mach0_n_166));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_data_offset_1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] ),\n .Q(\\data_offset_1_i1_reg[1] ),\n .R(bank_mach0_n_166));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_data_offset_1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(i___28_n_0),\n .Q(\\data_offset_1_i1_reg[2] ),\n .R(mc_cas_n_ns[1]));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_data_offset_1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(i___29_n_0),\n .Q(\\data_offset_1_i1_reg[3] ),\n .R(mc_cas_n_ns[1]));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_data_offset_1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10] ),\n .Q(\\data_offset_1_i1_reg[4] ),\n .R(bank_mach0_n_166));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_data_offset_1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(i___54_n_0),\n .Q(\\data_offset_1_i1_reg[5] ),\n .R(bank_mach0_n_166));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_data_offset_2_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_data_offset_2_ns),\n .Q(\\cmd_pipe_plus.mc_data_offset_2_reg_n_0_[3] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_data_offset_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 ),\n .Q(\\phy_ctl_wd_i1_reg[17] ),\n .R(bank_mach0_n_166));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_data_offset_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ),\n .Q(\\phy_ctl_wd_i1_reg[18] ),\n .R(bank_mach0_n_166));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_data_offset_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(i___30_n_0),\n .Q(\\phy_ctl_wd_i1_reg[19] ),\n .R(mc_cas_n_ns[1]));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_data_offset_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(i___31_n_0),\n .Q(\\phy_ctl_wd_i1_reg[20] ),\n .R(mc_cas_n_ns[1]));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_data_offset_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4] ),\n .Q(\\phy_ctl_wd_i1_reg[21] ),\n .R(bank_mach0_n_166));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_data_offset_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(i___53_n_0),\n .Q(\\phy_ctl_wd_i1_reg[22] ),\n .R(bank_mach0_n_166));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_odt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_odt_ns),\n .Q(mc_odt),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_ras_n_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_ras_n_ns[0]),\n .Q(mc_ras_n[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_ras_n_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(i___27_n_0),\n .Q(mc_ras_n[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_ras_n_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_ras_n_ns[2]),\n .Q(mc_ras_n[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_we_n_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_we_n_ns[0]),\n .Q(mc_we_n[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_we_n_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_we_n_ns[1]),\n .Q(mc_we_n[1]),\n .R(1'b0));\n FDSE #(\n .INIT(1'b1)) \n \\cmd_pipe_plus.mc_we_n_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(bank_mach0_n_164),\n .Q(mc_we_n[2]),\n .S(mc_ras_n_ns[2]));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.mc_wrdata_en_reg \n (.C(CLK),\n .CE(1'b1),\n .D(i___58_n_0),\n .Q(mc_wrdata_en),\n .R(1'b0));\n (* syn_maxfan = \"30\" *) \n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.wr_data_addr_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(col_wr_data_buf_addr_r[0]),\n .Q(\\write_buffer.wr_buf_out_data_reg[287] [0]),\n .R(1'b0));\n (* syn_maxfan = \"30\" *) \n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.wr_data_addr_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(col_wr_data_buf_addr_r[1]),\n .Q(\\write_buffer.wr_buf_out_data_reg[287] [1]),\n .R(1'b0));\n (* syn_maxfan = \"30\" *) \n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.wr_data_addr_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(col_wr_data_buf_addr_r[2]),\n .Q(\\write_buffer.wr_buf_out_data_reg[287] [2]),\n .R(1'b0));\n (* syn_maxfan = \"30\" *) \n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.wr_data_addr_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(col_wr_data_buf_addr_r[3]),\n .Q(\\write_buffer.wr_buf_out_data_reg[287] [3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\cmd_pipe_plus.wr_data_en_reg \n (.C(CLK),\n .CE(1'b1),\n .D(wr_data_en_ns),\n .Q(\\read_data_indx.rd_data_indx_r_reg[0] ),\n .R(1'b0));\n ddr3_ifmig_7series_v4_0_col_mach col_mach0\n (.ADDRA({i___56_n_0,i___55_n_0,i___57_n_0}),\n .CLK(CLK),\n .D(col_wr_data_buf_addr_r),\n .DIC(col_periodic_rd),\n .E(i___32_n_0),\n .Q(Q),\n .SR(SR),\n .app_rd_data_end_ns(app_rd_data_end_ns),\n .bypass__0(bypass__0),\n .col_data_buf_addr(col_data_buf_addr),\n .col_rd_wr(col_rd_wr),\n .col_rd_wr_r1(col_rd_wr_r1),\n .col_rd_wr_r2(col_rd_wr_r2),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .maint_ref_zq_wip(maint_ref_zq_wip),\n .mc_cmd(mc_cmd[0]),\n .mc_read_idle_r_reg(col_mach0_n_16),\n .mc_ref_zq_wip_ns(mc_ref_zq_wip_ns),\n .\\not_strict_mode.status_ram.rd_buf_we_r1_reg (\\not_strict_mode.status_ram.rd_buf_we_r1_reg ),\n .\\rd_buf_indx.rd_buf_indx_r_reg[4] (\\rd_buf_indx.rd_buf_indx_r_reg[4] ),\n .\\read_fifo.fifo_out_data_r_reg[7]_0 (col_mach0_n_22),\n .\\read_fifo.tail_r_reg[0]_0 (\\read_fifo.tail_r_reg[0] ),\n .\\read_fifo.tail_r_reg[1]_0 (\\read_fifo.tail_r_reg[1] ),\n .\\read_fifo.tail_r_reg[2]_0 (tail_r),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22),\n .sent_col_r2(sent_col_r2),\n .wr_data_en_ns(wr_data_en_ns));\n LUT5 #(\n .INIT(32'h11000010)) \n i___0\n (.I0(bm_end_r1_reg),\n .I1(rstdiv0_sync_r1_reg_rep__20),\n .I2(sending_col[0]),\n .I3(\\bank_cntrl[0].bank0/bank_state0/rtp_timer_r [1]),\n .I4(\\bank_cntrl[0].bank0/bank_state0/rtp_timer_r [0]),\n .O(i___0_n_0));\n LUT5 #(\n .INIT(32'hFFFF0008)) \n i___1\n (.I0(\\rank_cntrl[0].rank_cntrl0/periodic_rd_request_r ),\n .I1(init_calib_complete_reg_rep__6),\n .I2(rank_mach0_n_5),\n .I3(periodic_rd_r),\n .I4(\\rank_common0/periodic_rd_grant_r ),\n .O(i___1_n_0));\n LUT6 #(\n .INIT(64'h1BB100000AA0A00A)) \n i___10\n (.I0(\\bank_cntrl[0].bank0/bank_queue0/set_order_q ),\n .I1(rstdiv0_sync_r1_reg_rep__20),\n .I2(ordered_r_lcl),\n .I3(bank_mach0_n_52),\n .I4(bank_mach0_n_128),\n .I5(\\bank_cntrl[0].bank0/bank_queue0/order_q_r ),\n .O(i___10_n_0));\n LUT6 #(\n .INIT(64'hCFFFCCEECCEECCEE)) \n i___11\n (.I0(p_13_out),\n .I1(bank_mach0_n_69),\n .I2(idle_r[1]),\n .I3(p_52_out),\n .I4(bank_mach0_n_82),\n .I5(\\bank_cntrl[1].bank0/tail_r ),\n .O(i___11_n_0));\n LUT6 #(\n .INIT(64'hF404FFFFF7070000)) \n i___12\n (.I0(bank_mach0_n_73),\n .I1(bank_mach0_n_69),\n .I2(p_13_out),\n .I3(bank_mach0_n_87),\n .I4(bank_mach0_n_74),\n .I5(\\bank_cntrl[1].bank0/bank_queue0/q_entry_r ),\n .O(i___12_n_0));\n LUT6 #(\n .INIT(64'h00000000AAAEEEEE)) \n i___13\n (.I0(\\bank_cntrl[1].bank0/auto_pre_r ),\n .I1(bank_mach0_n_135),\n .I2(\\bank_cntrl[1].bank0/wait_for_maint_r ),\n .I3(i___45_n_0),\n .I4(\\bank_cntrl[1].bank0/row_hit_r ),\n .I5(\\bank_cntrl[1].bank0/bank_queue0/clear_req ),\n .O(i___13_n_0));\n LUT6 #(\n .INIT(64'h1BB100000AA0A00A)) \n i___14\n (.I0(\\bank_cntrl[1].bank0/bank_queue0/set_order_q ),\n .I1(rstdiv0_sync_r1_reg_rep__20),\n .I2(ordered_r_lcl),\n .I3(bank_mach0_n_52),\n .I4(bank_mach0_n_128),\n .I5(\\bank_cntrl[1].bank0/bank_queue0/order_q_r ),\n .O(i___14_n_0));\n LUT2 #(\n .INIT(4'hB)) \n i___15\n (.I0(\\rank_common0/maint_prescaler_tick_ns ),\n .I1(init_calib_complete_reg_rep__6),\n .O(i___15_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1081\" *) \n LUT5 #(\n .INIT(32'h88820008)) \n i___16\n (.I0(init_calib_complete_reg_rep__6),\n .I1(\\rank_cntrl[0].rank_cntrl0/refresh_bank_r ),\n .I2(app_ref_req),\n .I3(rank_mach0_n_27),\n .I4(rank_mach0_n_43),\n .O(i___16_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1081\" *) \n LUT2 #(\n .INIT(4'hB)) \n i___17\n (.I0(rank_mach0_n_27),\n .I1(init_calib_complete_reg_rep__6),\n .O(i___17_n_0));\n LUT5 #(\n .INIT(32'hFF2AFFFF)) \n i___18\n (.I0(\\rank_common0/zq_request_r ),\n .I1(insert_maint_r1),\n .I2(maint_zq_r),\n .I3(app_zq_req),\n .I4(rank_mach0_n_30),\n .O(i___18_n_0));\n LUT5 #(\n .INIT(32'h00415541)) \n i___19\n (.I0(rstdiv0_sync_r1_reg_rep__20),\n .I1(\\bank_common0/rfc_zq_xsdll_timer_r [1]),\n .I2(\\bank_common0/rfc_zq_xsdll_timer_r [0]),\n .I3(insert_maint_r1_lcl_reg),\n .I4(rank_mach0_n_34),\n .O(i___19_n_0));\n LUT4 #(\n .INIT(16'h2F20)) \n i___2\n (.I0(maint_sre_r),\n .I1(maint_srx_r),\n .I2(insert_maint_r1),\n .I3(app_sr_active),\n .O(i___2_n_0));\n LUT5 #(\n .INIT(32'h00415541)) \n i___20\n (.I0(rstdiv0_sync_r1_reg_rep__20),\n .I1(bank_mach0_n_140),\n .I2(\\bank_common0/rfc_zq_xsdll_timer_r [4]),\n .I3(insert_maint_r1_lcl_reg),\n .I4(rank_mach0_n_34),\n .O(i___20_n_0));\n LUT5 #(\n .INIT(32'h45444044)) \n i___21\n (.I0(rstdiv0_sync_r1_reg_rep__20),\n .I1(\\rank_common0/maintenance_request.maint_arb0/last_master_r [0]),\n .I2(\\rank_common0/new_maint_rank_r ),\n .I3(\\rank_common0/upd_last_master_r ),\n .I4(\\rank_common0/maint_grant_r [0]),\n .O(i___21_n_0));\n LUT5 #(\n .INIT(32'h45444044)) \n i___22\n (.I0(rstdiv0_sync_r1_reg_rep__20),\n .I1(\\rank_common0/maintenance_request.maint_arb0/last_master_r [1]),\n .I2(\\rank_common0/new_maint_rank_r ),\n .I3(\\rank_common0/upd_last_master_r ),\n .I4(\\rank_common0/maint_grant_r [1]),\n .O(i___22_n_0));\n LUT5 #(\n .INIT(32'h10111511)) \n i___23\n (.I0(rstdiv0_sync_r1_reg_rep__20),\n .I1(\\rank_common0/maintenance_request.maint_arb0/last_master_r [2]),\n .I2(\\rank_common0/new_maint_rank_r ),\n .I3(\\rank_common0/upd_last_master_r ),\n .I4(\\rank_common0/maint_grant_r [2]),\n .O(i___23_n_0));\n LUT5 #(\n .INIT(32'h54005500)) \n i___24\n (.I0(maint_wip_r),\n .I1(\\rank_common0/zq_request_r ),\n .I2(\\rank_common0/sre_request_r ),\n .I3(init_calib_complete_reg_rep__6),\n .I4(\\rank_cntrl[0].rank_cntrl0/refresh_bank_r ),\n .O(i___24_n_0));\n LUT6 #(\n .INIT(64'h00001555FFFFFFFF)) \n i___25\n (.I0(bank_mach0_n_59),\n .I1(periodic_rd_ack_r),\n .I2(\\rank_common0/periodic_rd_grant_r ),\n .I3(\\rank_cntrl[0].rank_cntrl0/periodic_rd_cntr1_r ),\n .I4(rank_mach0_n_64),\n .I5(init_calib_complete_reg_rep__6),\n .O(i___25_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1085\" *) \n LUT3 #(\n .INIT(8'h78)) \n i___26\n (.I0(\\rank_common0/periodic_rd_grant_r ),\n .I1(periodic_rd_ack_r),\n .I2(\\rank_cntrl[0].rank_cntrl0/periodic_rd_cntr1_r ),\n .O(i___26_n_0));\n LUT3 #(\n .INIT(8'hEF)) \n i___27\n (.I0(sending_col[1]),\n .I1(sending_col[0]),\n .I2(sent_col),\n .O(i___27_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1082\" *) \n LUT4 #(\n .INIT(16'h78FF)) \n i___28\n (.I0(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [0]),\n .I1(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [1]),\n .I2(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [2]),\n .I3(col_rd_wr),\n .O(i___28_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1082\" *) \n LUT5 #(\n .INIT(32'h7F80FFFF)) \n i___29\n (.I0(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [2]),\n .I1(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [1]),\n .I2(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [0]),\n .I3(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [3]),\n .I4(col_rd_wr),\n .O(i___29_n_0));\n LUT6 #(\n .INIT(64'hFFFFC400C400C400)) \n i___3\n (.I0(\\rank_cntrl[0].rank_cntrl0/refresh_bank_r ),\n .I1(init_calib_complete_reg_rep__6),\n .I2(\\rank_common0/zq_request_r ),\n .I3(insert_maint_r1),\n .I4(maint_wip_r),\n .I5(maint_ref_zq_wip),\n .O(i___3_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1083\" *) \n LUT4 #(\n .INIT(16'h78FF)) \n i___30\n (.I0(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [0]),\n .I1(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [1]),\n .I2(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [2]),\n .I3(col_rd_wr),\n .O(i___30_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1083\" *) \n LUT5 #(\n .INIT(32'h7F80FFFF)) \n i___31\n (.I0(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [2]),\n .I1(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [1]),\n .I2(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [0]),\n .I3(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [3]),\n .I4(col_rd_wr),\n .O(i___31_n_0));\n LUT6 #(\n .INIT(64'hFECE320200000000)) \n i___32\n (.I0(col_rd_wr_r1),\n .I1(sending_col[1]),\n .I2(sending_col[0]),\n .I3(rd_wr_r[0]),\n .I4(rd_wr_r[1]),\n .I5(sent_col),\n .O(i___32_n_0));\n LUT6 #(\n .INIT(64'h00000000000022F0)) \n i___33\n (.I0(\\req_bank_r_lcl_reg[0] ),\n .I1(E),\n .I2(\\bank_cntrl[1].bank0/rb_hit_busies_r ),\n .I3(idle_r_lcl_reg),\n .I4(p_52_out),\n .I5(rstdiv0_sync_r1_reg_rep__20),\n .O(i___33_n_0));\n LUT6 #(\n .INIT(64'h4454445444545555)) \n i___34\n (.I0(\\bank_cntrl[1].bank0/bank_queue0/clear_req ),\n .I1(\\bank_cntrl[1].bank0/q_has_rd ),\n .I2(maint_req_r),\n .I3(idle_r[1]),\n .I4(was_wr),\n .I5(bank_mach0_n_82),\n .O(i___34_n_0));\n LUT6 #(\n .INIT(64'h1010111010101010)) \n i___35\n (.I0(p_13_out),\n .I1(rstdiv0_sync_r1_reg_rep__21),\n .I2(\\bank_cntrl[1].bank0/q_has_priority ),\n .I3(rb_hit_busy_r),\n .I4(bank_mach0_n_72),\n .I5(app_hi_pri_r2),\n .O(i___35_n_0));\n LUT6 #(\n .INIT(64'h888888A8A8A8A8A8)) \n i___36\n (.I0(i___38_n_0),\n .I1(\\bank_cntrl[0].bank0/auto_pre_r ),\n .I2(bank_mach0_n_136),\n .I3(\\bank_cntrl[0].bank0/wait_for_maint_r ),\n .I4(i___45_n_0),\n .I5(\\bank_cntrl[0].bank0/row_hit_r ),\n .O(i___36_n_0));\n LUT6 #(\n .INIT(64'h88888A8888888888)) \n i___37\n (.I0(i___38_n_0),\n .I1(bm_end_r1_reg),\n .I2(bank_mach0_n_86),\n .I3(\\bank_cntrl[0].bank0/tail_r ),\n .I4(\\bank_cntrl[0].bank0/pre_wait_r ),\n .I5(bank_mach0_n_141),\n .O(i___37_n_0));\n LUT6 #(\n .INIT(64'h0000000040555555)) \n i___38\n (.I0(rstdiv0_sync_r1_reg_rep__21),\n .I1(req_wr_r[0]),\n .I2(rd_wr_r[0]),\n .I3(bm_end_r1_reg),\n .I4(sending_col[0]),\n .I5(\\bank_cntrl[0].bank0/bank_queue0/pre_bm_end_r ),\n .O(i___38_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1084\" *) \n LUT3 #(\n .INIT(8'h78)) \n i___39\n (.I0(periodic_rd_r),\n .I1(periodic_rd_ack_r),\n .I2(\\rank_common0/periodic_rd_r_cnt ),\n .O(i___39_n_0));\n LUT6 #(\n .INIT(64'hCFFFCCEECCEECCEE)) \n i___4\n (.I0(p_52_out),\n .I1(bank_mach0_n_76),\n .I2(idle_r[0]),\n .I3(p_13_out),\n .I4(bank_mach0_n_86),\n .I5(\\bank_cntrl[0].bank0/tail_r ),\n .O(i___4_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1085\" *) \n LUT3 #(\n .INIT(8'h78)) \n i___40\n (.I0(periodic_rd_r),\n .I1(periodic_rd_ack_r),\n .I2(\\bank_common0/periodic_rd_cntr_r ),\n .O(i___40_n_0));\n LUT6 #(\n .INIT(64'h4040404040454040)) \n i___41\n (.I0(sending_row[1]),\n .I1(row_cmd_wr),\n .I2(sending_row[0]),\n .I3(maint_zq_r),\n .I4(insert_maint_r1),\n .I5(rstdiv0_sync_r1_reg_rep__21),\n .O(i___41_n_0));\n LUT5 #(\n .INIT(32'h00F0F8F8)) \n i___42\n (.I0(app_sr_req),\n .I1(init_calib_complete_reg_rep__6),\n .I2(\\rank_common0/sre_request_r ),\n .I3(insert_maint_r1),\n .I4(maint_sre_r),\n .O(i___42_n_0));\n LUT6 #(\n .INIT(64'hFF00FF4FFF00FF44)) \n i___43\n (.I0(bank_mach0_n_129),\n .I1(\\bank_cntrl[1].bank0/bank_state0/req_bank_rdy_ns ),\n .I2(bank_mach0_n_130),\n .I3(rnk_config_valid_r),\n .I4(\\bank_cntrl[0].bank0/bank_state0/override_demand_ns ),\n .I5(\\bank_cntrl[0].bank0/bank_state0/req_bank_rdy_ns ),\n .O(i___43_n_0));\n LUT6 #(\n .INIT(64'h01000100FFFF0100)) \n i___44\n (.I0(\\bank_cntrl[1].bank0/bank_state0/ras_timer_r [2]),\n .I1(\\bank_cntrl[1].bank0/bank_state0/ras_timer_r [1]),\n .I2(\\bank_cntrl[1].bank0/bank_state0/ras_timer_r [0]),\n .I3(bank_mach0_n_44),\n .I4(sending_col[1]),\n .I5(rd_wr_r[1]),\n .O(i___44_n_0));\n LUT3 #(\n .INIT(8'h45)) \n i___45\n (.I0(maint_wip_r),\n .I1(\\bank_common0/periodic_rd_cntr_r ),\n .I2(maint_req_r),\n .O(i___45_n_0));\n LUT5 #(\n .INIT(32'h00151515)) \n i___46\n (.I0(rstdiv0_sync_r1_reg_rep__21),\n .I1(sending_col[1]),\n .I2(wr_this_rank_r[1]),\n .I3(sending_col[0]),\n .I4(wr_this_rank_r[0]),\n .O(i___46_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1084\" *) \n LUT4 #(\n .INIT(16'hFF4C)) \n i___47\n (.I0(periodic_rd_ack_r),\n .I1(periodic_rd_r),\n .I2(\\rank_common0/periodic_rd_r_cnt ),\n .I3(rank_mach0_n_5),\n .O(i___47_n_0));\n LUT3 #(\n .INIT(8'hBA)) \n i___48\n (.I0(app_ref_req),\n .I1(\\rank_cntrl[0].rank_cntrl0/refresh_bank_r ),\n .I2(\\rank_common0/app_ref_r ),\n .O(i___48_n_0));\n LUT3 #(\n .INIT(8'hEA)) \n i___49\n (.I0(app_zq_req),\n .I1(\\rank_common0/app_zq_r ),\n .I2(\\rank_common0/zq_request_r ),\n .O(i___49_n_0));\n LUT6 #(\n .INIT(64'hB888FFFFB8BB0000)) \n i___5\n (.I0(bank_mach0_n_134),\n .I1(p_52_out),\n .I2(bank_mach0_n_83),\n .I3(bank_mach0_n_76),\n .I4(bank_mach0_n_78),\n .I5(\\bank_cntrl[0].bank0/bank_queue0/q_entry_r ),\n .O(i___5_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1080\" *) \n LUT4 #(\n .INIT(16'h1441)) \n i___50\n (.I0(rstdiv0_sync_r1_reg_rep__21),\n .I1(\\rank_cntrl[0].rank_cntrl0/act_delayed ),\n .I2(bank_mach0_n_144),\n .I3(faw_cnt_r[0]),\n .O(i___50_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1080\" *) \n LUT5 #(\n .INIT(32'h44411444)) \n i___51\n (.I0(rstdiv0_sync_r1_reg_rep__21),\n .I1(faw_cnt_r[1]),\n .I2(bank_mach0_n_144),\n .I3(\\rank_cntrl[0].rank_cntrl0/act_delayed ),\n .I4(faw_cnt_r[0]),\n .O(i___51_n_0));\n LUT6 #(\n .INIT(64'h5551455500041000)) \n i___52\n (.I0(rstdiv0_sync_r1_reg_rep__21),\n .I1(faw_cnt_r[1]),\n .I2(\\rank_cntrl[0].rank_cntrl0/act_delayed ),\n .I3(bank_mach0_n_144),\n .I4(faw_cnt_r[0]),\n .I5(faw_cnt_r[2]),\n .O(i___52_n_0));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n i___53\n (.I0(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [5]),\n .I1(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [3]),\n .I2(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [0]),\n .I3(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [1]),\n .I4(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [2]),\n .I5(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [4]),\n .O(i___53_n_0));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n i___54\n (.I0(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [5]),\n .I1(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [3]),\n .I2(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [0]),\n .I3(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [1]),\n .I4(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [2]),\n .I5(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [4]),\n .O(i___54_n_0));\n LUT5 #(\n .INIT(32'h15554000)) \n i___55\n (.I0(rstdiv0_sync_r1_reg_rep__21),\n .I1(\\read_fifo.tail_r_reg[1] ),\n .I2(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I3(tail_r[1]),\n .I4(tail_r[2]),\n .O(i___55_n_0));\n LUT2 #(\n .INIT(4'h1)) \n i___56\n (.I0(rstdiv0_sync_r1_reg_rep__22),\n .I1(col_mach0_n_22),\n .O(i___56_n_0));\n LUT4 #(\n .INIT(16'h1540)) \n i___57\n (.I0(rstdiv0_sync_r1_reg_rep__22),\n .I1(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I2(\\read_fifo.tail_r_reg[1] ),\n .I3(tail_r[1]),\n .O(i___57_n_0));\n LUT2 #(\n .INIT(4'h2)) \n i___58\n (.I0(sent_col_r2),\n .I1(col_rd_wr_r2),\n .O(i___58_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___59\n (.I0(\\rank_common0/maint_prescaler.maint_prescaler_r_reg__0 [0]),\n .I1(\\rank_common0/maint_prescaler.maint_prescaler_r_reg__0 [1]),\n .O(i___59_n_0));\n LUT5 #(\n .INIT(32'h5CFF5C00)) \n i___6\n (.I0(bank_mach0_n_134),\n .I1(bank_mach0_n_77),\n .I2(p_52_out),\n .I3(bank_mach0_n_78),\n .I4(head_r[0]),\n .O(i___6_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___60\n (.I0(\\rank_common0/refresh_timer.refresh_timer_r_reg__0 [0]),\n .I1(\\rank_common0/refresh_timer.refresh_timer_r_reg__0 [1]),\n .O(i___60_n_0));\n LUT6 #(\n .INIT(64'h1F10FFFF1F100000)) \n i___7\n (.I0(p_52_out),\n .I1(bank_mach0_n_134),\n .I2(p_13_out),\n .I3(bank_mach0_n_71),\n .I4(bank_mach0_n_74),\n .I5(head_r[1]),\n .O(i___7_n_0));\n LUT6 #(\n .INIT(64'h00000000EAEA0AEA)) \n i___8\n (.I0(bank_mach0_n_52),\n .I1(bank_mach0_n_69),\n .I2(req_wr_r[1]),\n .I3(sending_col[1]),\n .I4(rd_wr_r[1]),\n .I5(rstdiv0_sync_r1_reg_rep__20),\n .O(i___8_n_0));\n LUT6 #(\n .INIT(64'h00000000EAEA0AEA)) \n i___9\n (.I0(ordered_r_lcl),\n .I1(bank_mach0_n_76),\n .I2(req_wr_r[0]),\n .I3(sending_col[0]),\n .I4(rd_wr_r[0]),\n .I5(rstdiv0_sync_r1_reg_rep__20),\n .O(i___9_n_0));\n FDRE #(\n .INIT(1'b0)) \n mc_read_idle_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(col_mach0_n_16),\n .Q(idle),\n .R(maint_prescaler_r1));\n FDRE #(\n .INIT(1'b0)) \n mc_ref_zq_wip_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mc_ref_zq_wip_ns),\n .Q(tempmon_sample_en),\n .R(1'b0));\n LUT2 #(\n .INIT(4'hB)) \n mem_reg_0_15_0_5_i_2__0\n (.I0(mc_cs_n),\n .I1(init_calib_complete_reg_rep__7),\n .O(\\rd_ptr_timing_reg[0] [0]));\n LUT2 #(\n .INIT(4'hB)) \n mem_reg_0_15_0_5_i_3__0\n (.I0(mc_ras_n[2]),\n .I1(init_calib_complete_reg_rep__7),\n .O(\\rd_ptr_timing_reg[0]_0 [3]));\n LUT2 #(\n .INIT(4'hB)) \n mem_reg_0_15_12_17_i_2__4\n (.I0(mc_cas_n[0]),\n .I1(init_calib_complete_reg_rep__7),\n .O(\\rd_ptr_timing_reg[0]_0 [0]));\n LUT2 #(\n .INIT(4'hB)) \n mem_reg_0_15_18_23_i_1__4\n (.I0(mc_cas_n[2]),\n .I1(init_calib_complete_reg_rep__7),\n .O(\\rd_ptr_timing_reg[0]_0 [1]));\n LUT2 #(\n .INIT(4'hB)) \n mem_reg_0_15_24_29_i_2__4\n (.I0(mc_ras_n[0]),\n .I1(init_calib_complete_reg_rep__7),\n .O(\\rd_ptr_timing_reg[0]_0 [2]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_30_35_i_1__5\n (.I0(mc_address[14]),\n .I1(init_calib_complete_reg_rep__7),\n .O(phy_dout[0]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_30_35_i_2__5\n (.I0(mc_address[37]),\n .I1(init_calib_complete_reg_rep__7),\n .O(phy_dout[1]));\n LUT2 #(\n .INIT(4'hB)) \n mem_reg_0_15_6_11_i_2__4\n (.I0(mc_we_n[0]),\n .I1(init_calib_complete_reg_rep__7),\n .O(\\rd_ptr_timing_reg[0] [1]));\n LUT2 #(\n .INIT(4'hB)) \n mem_reg_0_15_6_11_i_3__4\n (.I0(mc_we_n[2]),\n .I1(init_calib_complete_reg_rep__7),\n .O(\\rd_ptr_timing_reg[0] [2]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_2__0\n (.I0(mc_address[13]),\n .I1(init_calib_complete_reg_rep__7),\n .O(\\my_empty_reg[7] [0]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_3__0\n (.I0(mc_address[36]),\n .I1(init_calib_complete_reg_rep__7),\n .O(\\my_empty_reg[7] [1]));\n LUT2 #(\n .INIT(4'hB)) \n \\pointer_ram.rams[0].RAM32M0_i_1 \n (.I0(\\read_data_indx.rd_data_indx_r_reg[0] ),\n .I1(ram_init_done_r),\n .O(pointer_we));\n ddr3_ifmig_7series_v4_0_rank_mach rank_mach0\n (.CLK(CLK),\n .D({i___22_n_0,i___21_n_0}),\n .E(bank_mach0_n_145),\n .O({\\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_4 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_5 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_6 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_7 }),\n .Q(\\rank_common0/maint_prescaler.maint_prescaler_r_reg__0 ),\n .S({rank_mach0_n_44,rank_mach0_n_45,rank_mach0_n_46,rank_mach0_n_47}),\n .SR(SR),\n .SS(i___15_n_0),\n .act_delayed(\\rank_cntrl[0].rank_cntrl0/act_delayed ),\n .act_this_rank(\\rank_cntrl[0].rank_cntrl0/act_this_rank ),\n .\\act_this_rank_r_reg[0] (bank_mach0_n_144),\n .app_ref_ack(app_ref_ack),\n .app_ref_r(\\rank_common0/app_ref_r ),\n .app_sr_active(app_sr_active),\n .app_sr_req(app_sr_req),\n .app_zq_ack(app_zq_ack),\n .app_zq_r(\\rank_common0/app_zq_r ),\n .app_zq_r_reg(i___49_n_0),\n .cke_r(\\arb_mux0/arb_select0/cke_r ),\n .\\generate_maint_cmds.insert_maint_r_lcl_reg (insert_maint_r1_lcl_reg),\n .\\grant_r_reg[0] (bank_mach0_n_65),\n .\\grant_r_reg[1] (i___46_n_0),\n .granted_col_r_reg(rank_mach0_n_68),\n .\\inhbt_act_faw.faw_cnt_r_reg[1] ({i___52_n_0,i___51_n_0,i___50_n_0}),\n .\\inhbt_act_faw.inhbt_act_faw_r_reg (faw_cnt_r),\n .inhbt_act_faw_r(inhbt_act_faw_r),\n .init_calib_complete_reg_rep__6(i___42_n_0),\n .init_calib_complete_reg_rep__6_0(i___16_n_0),\n .init_calib_complete_reg_rep__6_1(init_calib_complete_reg_rep__6),\n .init_calib_complete_reg_rep__6_2(i___17_n_0),\n .init_calib_complete_reg_rep__7(init_calib_complete_reg_rep__7),\n .insert_maint_r1(insert_maint_r1),\n .\\last_master_r_reg[2] (\\rank_common0/maintenance_request.maint_arb0/last_master_r ),\n .\\last_master_r_reg[2]_0 (i___23_n_0),\n .\\maint_controller.maint_wip_r_lcl_reg (i___24_n_0),\n .\\maint_prescaler.maint_prescaler_r_reg[0] (i___59_n_0),\n .maint_prescaler_r1(maint_prescaler_r1),\n .maint_prescaler_tick_ns(\\rank_common0/maint_prescaler_tick_ns ),\n .maint_ref_zq_wip(maint_ref_zq_wip),\n .maint_req_r(maint_req_r),\n .maint_sre_r(maint_sre_r),\n .maint_srx_r(maint_srx_r),\n .maint_zq_r(maint_zq_r),\n .\\maintenance_request.maint_sre_r_lcl_reg (\\rank_common0/maint_grant_r ),\n .\\maintenance_request.maint_sre_r_lcl_reg_0 (i___2_n_0),\n .mc_cke_ns(mc_cke_ns),\n .new_maint_rank_r(\\rank_common0/new_maint_rank_r ),\n .periodic_rd_ack_r_lcl_reg(i___25_n_0),\n .periodic_rd_ack_r_lcl_reg_0(i___47_n_0),\n .periodic_rd_cntr1_r(\\rank_cntrl[0].rank_cntrl0/periodic_rd_cntr1_r ),\n .\\periodic_rd_generation.periodic_rd_request_r_reg (rank_mach0_n_64),\n .\\periodic_rd_generation.periodic_rd_request_r_reg_0 (i___1_n_0),\n .\\periodic_rd_generation.read_this_rank_r_reg (bank_mach0_n_59),\n .periodic_rd_grant_r(\\rank_common0/periodic_rd_grant_r ),\n .periodic_rd_r(periodic_rd_r),\n .periodic_rd_r_cnt(\\rank_common0/periodic_rd_r_cnt ),\n .periodic_rd_request_r(\\rank_cntrl[0].rank_cntrl0/periodic_rd_request_r ),\n .\\periodic_read_request.periodic_rd_grant_r_reg[0] (i___26_n_0),\n .\\periodic_read_request.periodic_rd_r_lcl_reg (i___39_n_0),\n .\\periodic_read_request.upd_last_master_r_reg (rank_mach0_n_5),\n .read_this_rank(\\rank_cntrl[0].rank_cntrl0/read_this_rank ),\n .read_this_rank_r(\\rank_cntrl[0].rank_cntrl0/read_this_rank_r ),\n .refresh_bank_r(\\rank_cntrl[0].rank_cntrl0/refresh_bank_r ),\n .\\refresh_generation.refresh_bank_r_reg[0] (rank_mach0_n_43),\n .\\refresh_generation.refresh_bank_r_reg[0]_0 (i___48_n_0),\n .\\refresh_generation.refresh_bank_r_reg[0]_1 (i___3_n_0),\n .\\refresh_timer.refresh_timer_r_reg[0] (i___60_n_0),\n .\\refresh_timer.refresh_timer_r_reg[4] (\\rank_common0/refresh_timer.refresh_timer_r_reg__0 ),\n .\\refresh_timer.refresh_timer_r_reg[5] (rank_mach0_n_27),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] (rfc_zq_xsdll_timer_ns),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 (\\bank_common0/rfc_zq_xsdll_timer_r [0]),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] (rank_mach0_n_34),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] (rank_mach0_n_42),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] (rank_mach0_n_40),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .\\rtw_timer.rtw_cnt_r_reg[1] (rtw_cnt_r),\n .sre_request_r(\\rank_common0/sre_request_r ),\n .upd_last_master_r(\\rank_common0/upd_last_master_r ),\n .\\wr_this_rank_r_reg[0] (bank_mach0_n_142),\n .\\zq_cntrl.zq_request_logic.zq_request_r_reg (i___18_n_0),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[0] (rank_mach0_n_30),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[11] ({rank_mach0_n_52,rank_mach0_n_53,rank_mach0_n_54,rank_mach0_n_55}),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ({\\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_4 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_5 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_6 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_7 }),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[15] ({rank_mach0_n_56,rank_mach0_n_57,rank_mach0_n_58,rank_mach0_n_59}),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ({\\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_4 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_5 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_6 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_7 }),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[19] ({rank_mach0_n_60,rank_mach0_n_61,rank_mach0_n_62,rank_mach0_n_63}),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ({\\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_4 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_5 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_6 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_7 }),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[7] ({rank_mach0_n_48,rank_mach0_n_49,rank_mach0_n_50,rank_mach0_n_51}),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ({\\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_4 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_5 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_6 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_7 }),\n .zq_request_r(\\rank_common0/zq_request_r ));\n CARRY4 \\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3 \n (.CI(1'b0),\n .CO({\\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_0 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_1 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_2 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b1,1'b1,1'b1,1'b1}),\n .O({\\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_4 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_5 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_6 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_7 }),\n .S({rank_mach0_n_44,rank_mach0_n_45,rank_mach0_n_46,rank_mach0_n_47}));\n CARRY4 \\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1 \n (.CI(\\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_0 ),\n .CO({\\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_0 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_1 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_2 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b1,1'b1,1'b1,1'b1}),\n .O({\\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_4 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_5 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_6 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_7 }),\n .S({rank_mach0_n_56,rank_mach0_n_57,rank_mach0_n_58,rank_mach0_n_59}));\n CARRY4 \\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1 \n (.CI(\\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_0 ),\n .CO({\\NLW_zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_CO_UNCONNECTED [3],\\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_1 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_2 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b1,1'b1,1'b1}),\n .O({\\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_4 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_5 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_6 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_7 }),\n .S({rank_mach0_n_60,rank_mach0_n_61,rank_mach0_n_62,rank_mach0_n_63}));\n CARRY4 \\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1 \n (.CI(\\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_0 ),\n .CO({\\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_0 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_1 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_2 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b1,1'b1,1'b1,1'b1}),\n .O({\\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_4 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_5 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_6 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_7 }),\n .S({rank_mach0_n_48,rank_mach0_n_49,rank_mach0_n_50,rank_mach0_n_51}));\n CARRY4 \\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1 \n (.CI(\\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_0 ),\n .CO({\\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_0 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_1 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_2 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b1,1'b1,1'b1,1'b1}),\n .O({\\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_4 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_5 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_6 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_7 }),\n .S({rank_mach0_n_52,rank_mach0_n_53,rank_mach0_n_54,rank_mach0_n_55}));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_mem_intfc\" *) \nmodule ddr3_ifmig_7series_v4_0_mem_intfc\n (insert_maint_r1_lcl_reg,\n app_ref_ack,\n app_zq_ack,\n accept_ns,\n idle_ns,\n bm_end_r1,\n bm_end_r1_reg,\n bm_end_r1_0,\n bm_end_r1_reg_0,\n E,\n app_sr_active,\n ddr3_reset_n,\n ddr3_cas_n,\n ddr3_ras_n,\n ddr3_we_n,\n ddr3_addr,\n ddr3_ba,\n ddr3_cs_n,\n ddr3_odt,\n ddr3_cke,\n ddr3_dm,\n \\rd_ptr_timing_reg[2] ,\n \\rd_ptr_timing_reg[2]_0 ,\n \\rd_ptr_timing_reg[2]_1 ,\n \\rd_ptr_timing_reg[2]_2 ,\n \\rd_ptr_timing_reg[2]_3 ,\n \\rd_ptr_timing_reg[2]_4 ,\n \\rd_ptr_timing_reg[2]_5 ,\n \\rd_ptr_timing_reg[2]_6 ,\n \\rd_ptr_timing_reg[2]_7 ,\n \\rd_ptr_timing_reg[2]_8 ,\n \\rd_ptr_timing_reg[2]_9 ,\n \\rd_ptr_timing_reg[2]_10 ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,\n phy_dout,\n \\samps_r_reg[9] ,\n init_calib_complete_r_reg,\n \\calib_seq_reg[0] ,\n \\pi_rst_stg1_cal_r_reg[0] ,\n samp_edge_cnt0_en_r,\n pi_en_stg2_f_timing_reg,\n dqs_po_en_stg2_f_reg,\n \\rd_ptr_timing_reg[0] ,\n \\rd_ptr_timing_reg[0]_0 ,\n \\resume_wait_r_reg[5] ,\n stg3_dec2init_val_r_reg,\n stg3_inc2init_val_r_reg,\n bypass__0,\n \\not_strict_mode.app_rd_data_end_reg ,\n rd_buf_we,\n rst_sync_r1_reg,\n \\stg2_tap_cnt_reg[0] ,\n \\sm_r_reg[0] ,\n D,\n \\not_strict_mode.app_rd_data_reg[255] ,\n \\not_strict_mode.app_rd_data_reg[239] ,\n \\not_strict_mode.app_rd_data_reg[247] ,\n \\not_strict_mode.app_rd_data_reg[231] ,\n \\not_strict_mode.app_rd_data_reg[254] ,\n \\not_strict_mode.app_rd_data_reg[238] ,\n \\not_strict_mode.app_rd_data_reg[246] ,\n \\not_strict_mode.app_rd_data_reg[230] ,\n \\not_strict_mode.app_rd_data_reg[253] ,\n \\not_strict_mode.app_rd_data_reg[237] ,\n \\not_strict_mode.app_rd_data_reg[245] ,\n \\not_strict_mode.app_rd_data_reg[229] ,\n \\not_strict_mode.app_rd_data_reg[252] ,\n \\not_strict_mode.app_rd_data_reg[236] ,\n \\not_strict_mode.app_rd_data_reg[244] ,\n \\not_strict_mode.app_rd_data_reg[228] ,\n \\not_strict_mode.app_rd_data_reg[251] ,\n \\not_strict_mode.app_rd_data_reg[235] ,\n \\not_strict_mode.app_rd_data_reg[243] ,\n \\not_strict_mode.app_rd_data_reg[227] ,\n \\not_strict_mode.app_rd_data_reg[250] ,\n \\not_strict_mode.app_rd_data_reg[234] ,\n \\not_strict_mode.app_rd_data_reg[242] ,\n \\not_strict_mode.app_rd_data_reg[226] ,\n \\not_strict_mode.app_rd_data_reg[249] ,\n \\not_strict_mode.app_rd_data_reg[233] ,\n \\not_strict_mode.app_rd_data_reg[241] ,\n \\not_strict_mode.app_rd_data_reg[225] ,\n \\not_strict_mode.app_rd_data_reg[248] ,\n \\not_strict_mode.app_rd_data_reg[232] ,\n \\not_strict_mode.app_rd_data_reg[240] ,\n \\not_strict_mode.app_rd_data_reg[224] ,\n \\not_strict_mode.app_rd_data_reg[223] ,\n \\not_strict_mode.app_rd_data_reg[207] ,\n \\not_strict_mode.app_rd_data_reg[215] ,\n \\not_strict_mode.app_rd_data_reg[199] ,\n \\not_strict_mode.app_rd_data_reg[222] ,\n \\not_strict_mode.app_rd_data_reg[206] ,\n \\not_strict_mode.app_rd_data_reg[214] ,\n \\not_strict_mode.app_rd_data_reg[198] ,\n \\not_strict_mode.app_rd_data_reg[221] ,\n \\not_strict_mode.app_rd_data_reg[205] ,\n \\not_strict_mode.app_rd_data_reg[213] ,\n \\not_strict_mode.app_rd_data_reg[197] ,\n \\not_strict_mode.app_rd_data_reg[220] ,\n \\not_strict_mode.app_rd_data_reg[204] ,\n \\not_strict_mode.app_rd_data_reg[212] ,\n \\not_strict_mode.app_rd_data_reg[196] ,\n \\not_strict_mode.app_rd_data_reg[219] ,\n \\not_strict_mode.app_rd_data_reg[203] ,\n \\not_strict_mode.app_rd_data_reg[211] ,\n \\not_strict_mode.app_rd_data_reg[195] ,\n \\not_strict_mode.app_rd_data_reg[218] ,\n \\not_strict_mode.app_rd_data_reg[202] ,\n \\not_strict_mode.app_rd_data_reg[210] ,\n \\not_strict_mode.app_rd_data_reg[194] ,\n \\not_strict_mode.app_rd_data_reg[217] ,\n \\not_strict_mode.app_rd_data_reg[201] ,\n \\not_strict_mode.app_rd_data_reg[209] ,\n \\not_strict_mode.app_rd_data_reg[193] ,\n \\not_strict_mode.app_rd_data_reg[216] ,\n \\not_strict_mode.app_rd_data_reg[200] ,\n \\not_strict_mode.app_rd_data_reg[208] ,\n \\not_strict_mode.app_rd_data_reg[192] ,\n \\not_strict_mode.app_rd_data_reg[191] ,\n \\not_strict_mode.app_rd_data_reg[175] ,\n \\not_strict_mode.app_rd_data_reg[183] ,\n \\not_strict_mode.app_rd_data_reg[167] ,\n \\not_strict_mode.app_rd_data_reg[190] ,\n \\not_strict_mode.app_rd_data_reg[174] ,\n \\not_strict_mode.app_rd_data_reg[182] ,\n \\not_strict_mode.app_rd_data_reg[166] ,\n \\not_strict_mode.app_rd_data_reg[189] ,\n \\not_strict_mode.app_rd_data_reg[173] ,\n \\not_strict_mode.app_rd_data_reg[181] ,\n \\not_strict_mode.app_rd_data_reg[165] ,\n \\not_strict_mode.app_rd_data_reg[188] ,\n \\not_strict_mode.app_rd_data_reg[172] ,\n \\not_strict_mode.app_rd_data_reg[180] ,\n \\not_strict_mode.app_rd_data_reg[164] ,\n \\not_strict_mode.app_rd_data_reg[187] ,\n \\not_strict_mode.app_rd_data_reg[171] ,\n \\not_strict_mode.app_rd_data_reg[179] ,\n \\not_strict_mode.app_rd_data_reg[163] ,\n \\not_strict_mode.app_rd_data_reg[186] ,\n \\not_strict_mode.app_rd_data_reg[170] ,\n \\not_strict_mode.app_rd_data_reg[178] ,\n \\not_strict_mode.app_rd_data_reg[162] ,\n \\not_strict_mode.app_rd_data_reg[185] ,\n \\not_strict_mode.app_rd_data_reg[169] ,\n \\not_strict_mode.app_rd_data_reg[177] ,\n \\not_strict_mode.app_rd_data_reg[161] ,\n \\not_strict_mode.app_rd_data_reg[184] ,\n \\not_strict_mode.app_rd_data_reg[168] ,\n \\not_strict_mode.app_rd_data_reg[176] ,\n \\not_strict_mode.app_rd_data_reg[160] ,\n \\not_strict_mode.app_rd_data_reg[159] ,\n \\not_strict_mode.app_rd_data_reg[143] ,\n \\not_strict_mode.app_rd_data_reg[151] ,\n \\not_strict_mode.app_rd_data_reg[135] ,\n \\not_strict_mode.app_rd_data_reg[158] ,\n \\not_strict_mode.app_rd_data_reg[142] ,\n \\not_strict_mode.app_rd_data_reg[150] ,\n \\not_strict_mode.app_rd_data_reg[134] ,\n \\not_strict_mode.app_rd_data_reg[157] ,\n \\not_strict_mode.app_rd_data_reg[141] ,\n \\not_strict_mode.app_rd_data_reg[149] ,\n \\not_strict_mode.app_rd_data_reg[133] ,\n \\not_strict_mode.app_rd_data_reg[156] ,\n \\not_strict_mode.app_rd_data_reg[140] ,\n \\not_strict_mode.app_rd_data_reg[148] ,\n \\not_strict_mode.app_rd_data_reg[132] ,\n \\not_strict_mode.app_rd_data_reg[155] ,\n \\not_strict_mode.app_rd_data_reg[139] ,\n \\not_strict_mode.app_rd_data_reg[147] ,\n \\not_strict_mode.app_rd_data_reg[131] ,\n \\not_strict_mode.app_rd_data_reg[154] ,\n \\not_strict_mode.app_rd_data_reg[138] ,\n \\not_strict_mode.app_rd_data_reg[146] ,\n \\not_strict_mode.app_rd_data_reg[130] ,\n \\not_strict_mode.app_rd_data_reg[153] ,\n \\not_strict_mode.app_rd_data_reg[137] ,\n \\not_strict_mode.app_rd_data_reg[145] ,\n \\not_strict_mode.app_rd_data_reg[129] ,\n \\not_strict_mode.app_rd_data_reg[152] ,\n \\not_strict_mode.app_rd_data_reg[136] ,\n \\not_strict_mode.app_rd_data_reg[144] ,\n \\not_strict_mode.app_rd_data_reg[128] ,\n \\not_strict_mode.app_rd_data_reg[127] ,\n \\not_strict_mode.app_rd_data_reg[111] ,\n \\not_strict_mode.app_rd_data_reg[119] ,\n \\not_strict_mode.app_rd_data_reg[103] ,\n \\not_strict_mode.app_rd_data_reg[126] ,\n \\not_strict_mode.app_rd_data_reg[110] ,\n \\not_strict_mode.app_rd_data_reg[118] ,\n \\not_strict_mode.app_rd_data_reg[102] ,\n \\not_strict_mode.app_rd_data_reg[125] ,\n \\not_strict_mode.app_rd_data_reg[109] ,\n \\not_strict_mode.app_rd_data_reg[117] ,\n \\not_strict_mode.app_rd_data_reg[101] ,\n \\not_strict_mode.app_rd_data_reg[124] ,\n \\not_strict_mode.app_rd_data_reg[108] ,\n \\not_strict_mode.app_rd_data_reg[116] ,\n \\not_strict_mode.app_rd_data_reg[100] ,\n \\not_strict_mode.app_rd_data_reg[123] ,\n \\not_strict_mode.app_rd_data_reg[107] ,\n \\not_strict_mode.app_rd_data_reg[115] ,\n \\not_strict_mode.app_rd_data_reg[99] ,\n \\not_strict_mode.app_rd_data_reg[122] ,\n \\not_strict_mode.app_rd_data_reg[106] ,\n \\not_strict_mode.app_rd_data_reg[114] ,\n \\not_strict_mode.app_rd_data_reg[98] ,\n \\not_strict_mode.app_rd_data_reg[121] ,\n \\not_strict_mode.app_rd_data_reg[105] ,\n \\not_strict_mode.app_rd_data_reg[113] ,\n \\not_strict_mode.app_rd_data_reg[97] ,\n \\not_strict_mode.app_rd_data_reg[120] ,\n \\not_strict_mode.app_rd_data_reg[104] ,\n \\not_strict_mode.app_rd_data_reg[112] ,\n \\not_strict_mode.app_rd_data_reg[96] ,\n \\not_strict_mode.app_rd_data_reg[95] ,\n \\not_strict_mode.app_rd_data_reg[79] ,\n \\not_strict_mode.app_rd_data_reg[87] ,\n \\not_strict_mode.app_rd_data_reg[71] ,\n \\not_strict_mode.app_rd_data_reg[94] ,\n \\not_strict_mode.app_rd_data_reg[78] ,\n \\not_strict_mode.app_rd_data_reg[86] ,\n \\not_strict_mode.app_rd_data_reg[70] ,\n \\not_strict_mode.app_rd_data_reg[93] ,\n \\not_strict_mode.app_rd_data_reg[77] ,\n \\not_strict_mode.app_rd_data_reg[85] ,\n \\not_strict_mode.app_rd_data_reg[69] ,\n \\not_strict_mode.app_rd_data_reg[92] ,\n \\not_strict_mode.app_rd_data_reg[76] ,\n \\not_strict_mode.app_rd_data_reg[84] ,\n \\not_strict_mode.app_rd_data_reg[68] ,\n \\not_strict_mode.app_rd_data_reg[91] ,\n \\not_strict_mode.app_rd_data_reg[75] ,\n \\not_strict_mode.app_rd_data_reg[83] ,\n \\not_strict_mode.app_rd_data_reg[67] ,\n \\not_strict_mode.app_rd_data_reg[90] ,\n \\not_strict_mode.app_rd_data_reg[74] ,\n \\not_strict_mode.app_rd_data_reg[82] ,\n \\not_strict_mode.app_rd_data_reg[66] ,\n \\not_strict_mode.app_rd_data_reg[89] ,\n \\not_strict_mode.app_rd_data_reg[73] ,\n \\not_strict_mode.app_rd_data_reg[81] ,\n \\not_strict_mode.app_rd_data_reg[65] ,\n \\not_strict_mode.app_rd_data_reg[88] ,\n \\not_strict_mode.app_rd_data_reg[72] ,\n \\not_strict_mode.app_rd_data_reg[80] ,\n \\not_strict_mode.app_rd_data_reg[64] ,\n \\not_strict_mode.app_rd_data_reg[63] ,\n \\not_strict_mode.app_rd_data_reg[47] ,\n \\not_strict_mode.app_rd_data_reg[55] ,\n \\not_strict_mode.app_rd_data_reg[39] ,\n \\not_strict_mode.app_rd_data_reg[62] ,\n \\not_strict_mode.app_rd_data_reg[46] ,\n \\not_strict_mode.app_rd_data_reg[54] ,\n \\not_strict_mode.app_rd_data_reg[38] ,\n \\not_strict_mode.app_rd_data_reg[61] ,\n \\not_strict_mode.app_rd_data_reg[45] ,\n \\not_strict_mode.app_rd_data_reg[53] ,\n \\not_strict_mode.app_rd_data_reg[37] ,\n \\not_strict_mode.app_rd_data_reg[60] ,\n \\not_strict_mode.app_rd_data_reg[44] ,\n \\not_strict_mode.app_rd_data_reg[52] ,\n \\not_strict_mode.app_rd_data_reg[36] ,\n \\not_strict_mode.app_rd_data_reg[59] ,\n \\not_strict_mode.app_rd_data_reg[43] ,\n \\not_strict_mode.app_rd_data_reg[51] ,\n \\not_strict_mode.app_rd_data_reg[35] ,\n \\not_strict_mode.app_rd_data_reg[58] ,\n \\not_strict_mode.app_rd_data_reg[42] ,\n \\not_strict_mode.app_rd_data_reg[50] ,\n \\not_strict_mode.app_rd_data_reg[34] ,\n \\not_strict_mode.app_rd_data_reg[57] ,\n \\not_strict_mode.app_rd_data_reg[41] ,\n \\not_strict_mode.app_rd_data_reg[49] ,\n \\not_strict_mode.app_rd_data_reg[33] ,\n \\not_strict_mode.app_rd_data_reg[56] ,\n \\not_strict_mode.app_rd_data_reg[40] ,\n \\not_strict_mode.app_rd_data_reg[48] ,\n \\not_strict_mode.app_rd_data_reg[32] ,\n \\not_strict_mode.app_rd_data_reg[31] ,\n \\not_strict_mode.app_rd_data_reg[15] ,\n \\not_strict_mode.app_rd_data_reg[23] ,\n \\not_strict_mode.app_rd_data_reg[7] ,\n \\not_strict_mode.app_rd_data_reg[30] ,\n \\not_strict_mode.app_rd_data_reg[14] ,\n \\not_strict_mode.app_rd_data_reg[22] ,\n \\not_strict_mode.app_rd_data_reg[6] ,\n \\not_strict_mode.app_rd_data_reg[29] ,\n \\not_strict_mode.app_rd_data_reg[13] ,\n \\not_strict_mode.app_rd_data_reg[21] ,\n \\not_strict_mode.app_rd_data_reg[5] ,\n \\not_strict_mode.app_rd_data_reg[28] ,\n \\not_strict_mode.app_rd_data_reg[12] ,\n \\not_strict_mode.app_rd_data_reg[20] ,\n \\not_strict_mode.app_rd_data_reg[4] ,\n \\not_strict_mode.app_rd_data_reg[27] ,\n \\not_strict_mode.app_rd_data_reg[11] ,\n \\not_strict_mode.app_rd_data_reg[19] ,\n \\not_strict_mode.app_rd_data_reg[3] ,\n \\not_strict_mode.app_rd_data_reg[26] ,\n \\not_strict_mode.app_rd_data_reg[10] ,\n \\not_strict_mode.app_rd_data_reg[18] ,\n \\not_strict_mode.app_rd_data_reg[2] ,\n \\not_strict_mode.app_rd_data_reg[25] ,\n \\not_strict_mode.app_rd_data_reg[9] ,\n \\not_strict_mode.app_rd_data_reg[17] ,\n \\not_strict_mode.app_rd_data_reg[1] ,\n \\not_strict_mode.app_rd_data_reg[24] ,\n \\not_strict_mode.app_rd_data_reg[8] ,\n \\not_strict_mode.app_rd_data_reg[16] ,\n \\not_strict_mode.app_rd_data_reg[0] ,\n \\cmd_pipe_plus.mc_bank_reg[2] ,\n \\cmd_pipe_plus.mc_bank_reg[2]_0 ,\n \\en_cnt_div4.enable_wrlvl_cnt_reg[3] ,\n \\complex_row_cnt_ocal_reg[0] ,\n \\row_cnt_victim_rotate.complex_row_cnt_reg[4] ,\n pointer_we,\n \\not_strict_mode.app_rd_data_reg[255]_0 ,\n app_rd_data_end_ns,\n \\write_buffer.wr_buf_out_data_reg[287] ,\n \\wr_ptr_timing_reg[2] ,\n \\wr_ptr_timing_reg[2]_0 ,\n \\wr_ptr_timing_reg[2]_1 ,\n wr_en,\n wr_en_5,\n wr_en_6,\n ddr_ck_out,\n \\qcntr_r_reg[0] ,\n ddr3_dq,\n ddr3_dqs_p,\n ddr3_dqs_n,\n CLK,\n p_67_out,\n p_28_out,\n SR,\n hi_priority,\n rstdiv0_sync_r1_reg_rep__0,\n rstdiv0_sync_r1_reg_rep__20,\n app_ref_req,\n app_zq_req,\n rstdiv0_sync_r1_reg_rep__21,\n app_hi_pri_r2,\n app_sr_req,\n rstdiv0_sync_r1_reg_rep__22,\n mmcm_ps_clk,\n rst_sync_r1,\n poc_sample_pd,\n freq_refclk,\n mem_refclk,\n sync_pulse,\n pll_locked,\n in0,\n CLKB0,\n CLKB0_7,\n CLKB0_8,\n CLKB0_9,\n RST0,\n rstdiv0_sync_r1_reg_rep__9,\n rstdiv0_sync_r1_reg_rep__10,\n \\req_bank_r_lcl_reg[0] ,\n rstdiv0_sync_r1_reg_rep__12,\n rstdiv0_sync_r1_reg_rep__23,\n rstdiv0_sync_r1_reg_rep__13,\n rstdiv0_sync_r1_reg_rep__14,\n rstdiv0_sync_r1_reg_rep__11,\n cnt_pwron_reset_done_r0,\n rstdiv0_sync_r1_reg_rep__17,\n rstdiv0_sync_r1_reg_rep__16,\n SS,\n rstdiv0_sync_r1_reg_rep__2,\n rstdiv0_sync_r1_reg_rep__6,\n Q,\n mem_out,\n \\rd_ptr_reg[3] ,\n rstdiv0_sync_r1_reg_rep__25,\n rstdiv0_sync_r1_reg_rep__25_0,\n rstdiv0_sync_r1_reg_rep__24,\n \\sm_r_reg[0]_0 ,\n \\rd_ptr_reg[3]_0 ,\n \\req_bank_r_lcl_reg[0]_0 ,\n \\rd_buf_indx.rd_buf_indx_r_reg[4] ,\n ram_init_done_r,\n sys_rst,\n \\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ,\n mmcm_locked,\n rstdiv0_sync_r1_reg_rep__25_1,\n rstdiv0_sync_r1_reg_rep__25_2,\n \\mmcm_init_trail_reg[0] ,\n \\mmcm_current_reg[0] ,\n cmd,\n use_addr,\n bm_end_r1_reg_1,\n bm_end_r1_reg_2,\n rtp_timer_ns1,\n pass_open_bank_r_lcl_reg,\n \\generate_maint_cmds.insert_maint_r_lcl_reg ,\n \\app_addr_r1_reg[27] ,\n DOC,\n DOB,\n DOA,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ,\n \\not_strict_mode.status_ram.rd_buf_we_r1_reg ,\n \\app_addr_r1_reg[12] ,\n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ,\n \\app_addr_r1_reg[9] ,\n psdone,\n rstdiv0_sync_r1_reg_rep__19,\n fine_adjust_reg,\n samp_edge_cnt0_en_r_reg,\n pi_cnt_dec_reg,\n rstdiv0_sync_r1_reg_rep__23_0,\n p_81_in,\n rstdiv0_sync_r1_reg_rep__23_1,\n po_cnt_dec_reg,\n rstdiv0_sync_r1_reg_rep__4,\n rstdiv0_sync_r1_reg_rep__5,\n \\device_temp_r_reg[11] ,\n rstdiv0_sync_r1_reg_rep__7,\n \\stg3_r_reg[0] ,\n rstdiv0_sync_r1_reg_rep__8);\n output insert_maint_r1_lcl_reg;\n output app_ref_ack;\n output app_zq_ack;\n output accept_ns;\n output [1:0]idle_ns;\n output bm_end_r1;\n output bm_end_r1_reg;\n output bm_end_r1_0;\n output bm_end_r1_reg_0;\n output [0:0]E;\n output app_sr_active;\n output ddr3_reset_n;\n output ddr3_cas_n;\n output ddr3_ras_n;\n output ddr3_we_n;\n output [14:0]ddr3_addr;\n output [2:0]ddr3_ba;\n output [0:0]ddr3_cs_n;\n output [0:0]ddr3_odt;\n output [0:0]ddr3_cke;\n output [3:0]ddr3_dm;\n output \\rd_ptr_timing_reg[2] ;\n output \\rd_ptr_timing_reg[2]_0 ;\n output \\rd_ptr_timing_reg[2]_1 ;\n output \\rd_ptr_timing_reg[2]_2 ;\n output \\rd_ptr_timing_reg[2]_3 ;\n output \\rd_ptr_timing_reg[2]_4 ;\n output \\rd_ptr_timing_reg[2]_5 ;\n output \\rd_ptr_timing_reg[2]_6 ;\n output \\rd_ptr_timing_reg[2]_7 ;\n output \\rd_ptr_timing_reg[2]_8 ;\n output \\rd_ptr_timing_reg[2]_9 ;\n output \\rd_ptr_timing_reg[2]_10 ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;\n output [5:0]phy_dout;\n output \\samps_r_reg[9] ;\n output init_calib_complete_r_reg;\n output \\calib_seq_reg[0] ;\n output \\pi_rst_stg1_cal_r_reg[0] ;\n output samp_edge_cnt0_en_r;\n output pi_en_stg2_f_timing_reg;\n output dqs_po_en_stg2_f_reg;\n output [37:0]\\rd_ptr_timing_reg[0] ;\n output [4:0]\\rd_ptr_timing_reg[0]_0 ;\n output [0:0]\\resume_wait_r_reg[5] ;\n output stg3_dec2init_val_r_reg;\n output stg3_inc2init_val_r_reg;\n output bypass__0;\n output [6:0]\\not_strict_mode.app_rd_data_end_reg ;\n output rd_buf_we;\n output rst_sync_r1_reg;\n output \\stg2_tap_cnt_reg[0] ;\n output \\sm_r_reg[0] ;\n output [0:0]D;\n output \\not_strict_mode.app_rd_data_reg[255] ;\n output \\not_strict_mode.app_rd_data_reg[239] ;\n output \\not_strict_mode.app_rd_data_reg[247] ;\n output \\not_strict_mode.app_rd_data_reg[231] ;\n output \\not_strict_mode.app_rd_data_reg[254] ;\n output \\not_strict_mode.app_rd_data_reg[238] ;\n output \\not_strict_mode.app_rd_data_reg[246] ;\n output \\not_strict_mode.app_rd_data_reg[230] ;\n output \\not_strict_mode.app_rd_data_reg[253] ;\n output \\not_strict_mode.app_rd_data_reg[237] ;\n output \\not_strict_mode.app_rd_data_reg[245] ;\n output \\not_strict_mode.app_rd_data_reg[229] ;\n output \\not_strict_mode.app_rd_data_reg[252] ;\n output \\not_strict_mode.app_rd_data_reg[236] ;\n output \\not_strict_mode.app_rd_data_reg[244] ;\n output \\not_strict_mode.app_rd_data_reg[228] ;\n output \\not_strict_mode.app_rd_data_reg[251] ;\n output \\not_strict_mode.app_rd_data_reg[235] ;\n output \\not_strict_mode.app_rd_data_reg[243] ;\n output \\not_strict_mode.app_rd_data_reg[227] ;\n output \\not_strict_mode.app_rd_data_reg[250] ;\n output \\not_strict_mode.app_rd_data_reg[234] ;\n output \\not_strict_mode.app_rd_data_reg[242] ;\n output \\not_strict_mode.app_rd_data_reg[226] ;\n output \\not_strict_mode.app_rd_data_reg[249] ;\n output \\not_strict_mode.app_rd_data_reg[233] ;\n output \\not_strict_mode.app_rd_data_reg[241] ;\n output \\not_strict_mode.app_rd_data_reg[225] ;\n output \\not_strict_mode.app_rd_data_reg[248] ;\n output \\not_strict_mode.app_rd_data_reg[232] ;\n output \\not_strict_mode.app_rd_data_reg[240] ;\n output \\not_strict_mode.app_rd_data_reg[224] ;\n output \\not_strict_mode.app_rd_data_reg[223] ;\n output \\not_strict_mode.app_rd_data_reg[207] ;\n output \\not_strict_mode.app_rd_data_reg[215] ;\n output \\not_strict_mode.app_rd_data_reg[199] ;\n output \\not_strict_mode.app_rd_data_reg[222] ;\n output \\not_strict_mode.app_rd_data_reg[206] ;\n output \\not_strict_mode.app_rd_data_reg[214] ;\n output \\not_strict_mode.app_rd_data_reg[198] ;\n output \\not_strict_mode.app_rd_data_reg[221] ;\n output \\not_strict_mode.app_rd_data_reg[205] ;\n output \\not_strict_mode.app_rd_data_reg[213] ;\n output \\not_strict_mode.app_rd_data_reg[197] ;\n output \\not_strict_mode.app_rd_data_reg[220] ;\n output \\not_strict_mode.app_rd_data_reg[204] ;\n output \\not_strict_mode.app_rd_data_reg[212] ;\n output \\not_strict_mode.app_rd_data_reg[196] ;\n output \\not_strict_mode.app_rd_data_reg[219] ;\n output \\not_strict_mode.app_rd_data_reg[203] ;\n output \\not_strict_mode.app_rd_data_reg[211] ;\n output \\not_strict_mode.app_rd_data_reg[195] ;\n output \\not_strict_mode.app_rd_data_reg[218] ;\n output \\not_strict_mode.app_rd_data_reg[202] ;\n output \\not_strict_mode.app_rd_data_reg[210] ;\n output \\not_strict_mode.app_rd_data_reg[194] ;\n output \\not_strict_mode.app_rd_data_reg[217] ;\n output \\not_strict_mode.app_rd_data_reg[201] ;\n output \\not_strict_mode.app_rd_data_reg[209] ;\n output \\not_strict_mode.app_rd_data_reg[193] ;\n output \\not_strict_mode.app_rd_data_reg[216] ;\n output \\not_strict_mode.app_rd_data_reg[200] ;\n output \\not_strict_mode.app_rd_data_reg[208] ;\n output \\not_strict_mode.app_rd_data_reg[192] ;\n output \\not_strict_mode.app_rd_data_reg[191] ;\n output \\not_strict_mode.app_rd_data_reg[175] ;\n output \\not_strict_mode.app_rd_data_reg[183] ;\n output \\not_strict_mode.app_rd_data_reg[167] ;\n output \\not_strict_mode.app_rd_data_reg[190] ;\n output \\not_strict_mode.app_rd_data_reg[174] ;\n output \\not_strict_mode.app_rd_data_reg[182] ;\n output \\not_strict_mode.app_rd_data_reg[166] ;\n output \\not_strict_mode.app_rd_data_reg[189] ;\n output \\not_strict_mode.app_rd_data_reg[173] ;\n output \\not_strict_mode.app_rd_data_reg[181] ;\n output \\not_strict_mode.app_rd_data_reg[165] ;\n output \\not_strict_mode.app_rd_data_reg[188] ;\n output \\not_strict_mode.app_rd_data_reg[172] ;\n output \\not_strict_mode.app_rd_data_reg[180] ;\n output \\not_strict_mode.app_rd_data_reg[164] ;\n output \\not_strict_mode.app_rd_data_reg[187] ;\n output \\not_strict_mode.app_rd_data_reg[171] ;\n output \\not_strict_mode.app_rd_data_reg[179] ;\n output \\not_strict_mode.app_rd_data_reg[163] ;\n output \\not_strict_mode.app_rd_data_reg[186] ;\n output \\not_strict_mode.app_rd_data_reg[170] ;\n output \\not_strict_mode.app_rd_data_reg[178] ;\n output \\not_strict_mode.app_rd_data_reg[162] ;\n output \\not_strict_mode.app_rd_data_reg[185] ;\n output \\not_strict_mode.app_rd_data_reg[169] ;\n output \\not_strict_mode.app_rd_data_reg[177] ;\n output \\not_strict_mode.app_rd_data_reg[161] ;\n output \\not_strict_mode.app_rd_data_reg[184] ;\n output \\not_strict_mode.app_rd_data_reg[168] ;\n output \\not_strict_mode.app_rd_data_reg[176] ;\n output \\not_strict_mode.app_rd_data_reg[160] ;\n output \\not_strict_mode.app_rd_data_reg[159] ;\n output \\not_strict_mode.app_rd_data_reg[143] ;\n output \\not_strict_mode.app_rd_data_reg[151] ;\n output \\not_strict_mode.app_rd_data_reg[135] ;\n output \\not_strict_mode.app_rd_data_reg[158] ;\n output \\not_strict_mode.app_rd_data_reg[142] ;\n output \\not_strict_mode.app_rd_data_reg[150] ;\n output \\not_strict_mode.app_rd_data_reg[134] ;\n output \\not_strict_mode.app_rd_data_reg[157] ;\n output \\not_strict_mode.app_rd_data_reg[141] ;\n output \\not_strict_mode.app_rd_data_reg[149] ;\n output \\not_strict_mode.app_rd_data_reg[133] ;\n output \\not_strict_mode.app_rd_data_reg[156] ;\n output \\not_strict_mode.app_rd_data_reg[140] ;\n output \\not_strict_mode.app_rd_data_reg[148] ;\n output \\not_strict_mode.app_rd_data_reg[132] ;\n output \\not_strict_mode.app_rd_data_reg[155] ;\n output \\not_strict_mode.app_rd_data_reg[139] ;\n output \\not_strict_mode.app_rd_data_reg[147] ;\n output \\not_strict_mode.app_rd_data_reg[131] ;\n output \\not_strict_mode.app_rd_data_reg[154] ;\n output \\not_strict_mode.app_rd_data_reg[138] ;\n output \\not_strict_mode.app_rd_data_reg[146] ;\n output \\not_strict_mode.app_rd_data_reg[130] ;\n output \\not_strict_mode.app_rd_data_reg[153] ;\n output \\not_strict_mode.app_rd_data_reg[137] ;\n output \\not_strict_mode.app_rd_data_reg[145] ;\n output \\not_strict_mode.app_rd_data_reg[129] ;\n output \\not_strict_mode.app_rd_data_reg[152] ;\n output \\not_strict_mode.app_rd_data_reg[136] ;\n output \\not_strict_mode.app_rd_data_reg[144] ;\n output \\not_strict_mode.app_rd_data_reg[128] ;\n output \\not_strict_mode.app_rd_data_reg[127] ;\n output \\not_strict_mode.app_rd_data_reg[111] ;\n output \\not_strict_mode.app_rd_data_reg[119] ;\n output \\not_strict_mode.app_rd_data_reg[103] ;\n output \\not_strict_mode.app_rd_data_reg[126] ;\n output \\not_strict_mode.app_rd_data_reg[110] ;\n output \\not_strict_mode.app_rd_data_reg[118] ;\n output \\not_strict_mode.app_rd_data_reg[102] ;\n output \\not_strict_mode.app_rd_data_reg[125] ;\n output \\not_strict_mode.app_rd_data_reg[109] ;\n output \\not_strict_mode.app_rd_data_reg[117] ;\n output \\not_strict_mode.app_rd_data_reg[101] ;\n output \\not_strict_mode.app_rd_data_reg[124] ;\n output \\not_strict_mode.app_rd_data_reg[108] ;\n output \\not_strict_mode.app_rd_data_reg[116] ;\n output \\not_strict_mode.app_rd_data_reg[100] ;\n output \\not_strict_mode.app_rd_data_reg[123] ;\n output \\not_strict_mode.app_rd_data_reg[107] ;\n output \\not_strict_mode.app_rd_data_reg[115] ;\n output \\not_strict_mode.app_rd_data_reg[99] ;\n output \\not_strict_mode.app_rd_data_reg[122] ;\n output \\not_strict_mode.app_rd_data_reg[106] ;\n output \\not_strict_mode.app_rd_data_reg[114] ;\n output \\not_strict_mode.app_rd_data_reg[98] ;\n output \\not_strict_mode.app_rd_data_reg[121] ;\n output \\not_strict_mode.app_rd_data_reg[105] ;\n output \\not_strict_mode.app_rd_data_reg[113] ;\n output \\not_strict_mode.app_rd_data_reg[97] ;\n output \\not_strict_mode.app_rd_data_reg[120] ;\n output \\not_strict_mode.app_rd_data_reg[104] ;\n output \\not_strict_mode.app_rd_data_reg[112] ;\n output \\not_strict_mode.app_rd_data_reg[96] ;\n output \\not_strict_mode.app_rd_data_reg[95] ;\n output \\not_strict_mode.app_rd_data_reg[79] ;\n output \\not_strict_mode.app_rd_data_reg[87] ;\n output \\not_strict_mode.app_rd_data_reg[71] ;\n output \\not_strict_mode.app_rd_data_reg[94] ;\n output \\not_strict_mode.app_rd_data_reg[78] ;\n output \\not_strict_mode.app_rd_data_reg[86] ;\n output \\not_strict_mode.app_rd_data_reg[70] ;\n output \\not_strict_mode.app_rd_data_reg[93] ;\n output \\not_strict_mode.app_rd_data_reg[77] ;\n output \\not_strict_mode.app_rd_data_reg[85] ;\n output \\not_strict_mode.app_rd_data_reg[69] ;\n output \\not_strict_mode.app_rd_data_reg[92] ;\n output \\not_strict_mode.app_rd_data_reg[76] ;\n output \\not_strict_mode.app_rd_data_reg[84] ;\n output \\not_strict_mode.app_rd_data_reg[68] ;\n output \\not_strict_mode.app_rd_data_reg[91] ;\n output \\not_strict_mode.app_rd_data_reg[75] ;\n output \\not_strict_mode.app_rd_data_reg[83] ;\n output \\not_strict_mode.app_rd_data_reg[67] ;\n output \\not_strict_mode.app_rd_data_reg[90] ;\n output \\not_strict_mode.app_rd_data_reg[74] ;\n output \\not_strict_mode.app_rd_data_reg[82] ;\n output \\not_strict_mode.app_rd_data_reg[66] ;\n output \\not_strict_mode.app_rd_data_reg[89] ;\n output \\not_strict_mode.app_rd_data_reg[73] ;\n output \\not_strict_mode.app_rd_data_reg[81] ;\n output \\not_strict_mode.app_rd_data_reg[65] ;\n output \\not_strict_mode.app_rd_data_reg[88] ;\n output \\not_strict_mode.app_rd_data_reg[72] ;\n output \\not_strict_mode.app_rd_data_reg[80] ;\n output \\not_strict_mode.app_rd_data_reg[64] ;\n output \\not_strict_mode.app_rd_data_reg[63] ;\n output \\not_strict_mode.app_rd_data_reg[47] ;\n output \\not_strict_mode.app_rd_data_reg[55] ;\n output \\not_strict_mode.app_rd_data_reg[39] ;\n output \\not_strict_mode.app_rd_data_reg[62] ;\n output \\not_strict_mode.app_rd_data_reg[46] ;\n output \\not_strict_mode.app_rd_data_reg[54] ;\n output \\not_strict_mode.app_rd_data_reg[38] ;\n output \\not_strict_mode.app_rd_data_reg[61] ;\n output \\not_strict_mode.app_rd_data_reg[45] ;\n output \\not_strict_mode.app_rd_data_reg[53] ;\n output \\not_strict_mode.app_rd_data_reg[37] ;\n output \\not_strict_mode.app_rd_data_reg[60] ;\n output \\not_strict_mode.app_rd_data_reg[44] ;\n output \\not_strict_mode.app_rd_data_reg[52] ;\n output \\not_strict_mode.app_rd_data_reg[36] ;\n output \\not_strict_mode.app_rd_data_reg[59] ;\n output \\not_strict_mode.app_rd_data_reg[43] ;\n output \\not_strict_mode.app_rd_data_reg[51] ;\n output \\not_strict_mode.app_rd_data_reg[35] ;\n output \\not_strict_mode.app_rd_data_reg[58] ;\n output \\not_strict_mode.app_rd_data_reg[42] ;\n output \\not_strict_mode.app_rd_data_reg[50] ;\n output \\not_strict_mode.app_rd_data_reg[34] ;\n output \\not_strict_mode.app_rd_data_reg[57] ;\n output \\not_strict_mode.app_rd_data_reg[41] ;\n output \\not_strict_mode.app_rd_data_reg[49] ;\n output \\not_strict_mode.app_rd_data_reg[33] ;\n output \\not_strict_mode.app_rd_data_reg[56] ;\n output \\not_strict_mode.app_rd_data_reg[40] ;\n output \\not_strict_mode.app_rd_data_reg[48] ;\n output \\not_strict_mode.app_rd_data_reg[32] ;\n output \\not_strict_mode.app_rd_data_reg[31] ;\n output \\not_strict_mode.app_rd_data_reg[15] ;\n output \\not_strict_mode.app_rd_data_reg[23] ;\n output \\not_strict_mode.app_rd_data_reg[7] ;\n output \\not_strict_mode.app_rd_data_reg[30] ;\n output \\not_strict_mode.app_rd_data_reg[14] ;\n output \\not_strict_mode.app_rd_data_reg[22] ;\n output \\not_strict_mode.app_rd_data_reg[6] ;\n output \\not_strict_mode.app_rd_data_reg[29] ;\n output \\not_strict_mode.app_rd_data_reg[13] ;\n output \\not_strict_mode.app_rd_data_reg[21] ;\n output \\not_strict_mode.app_rd_data_reg[5] ;\n output \\not_strict_mode.app_rd_data_reg[28] ;\n output \\not_strict_mode.app_rd_data_reg[12] ;\n output \\not_strict_mode.app_rd_data_reg[20] ;\n output \\not_strict_mode.app_rd_data_reg[4] ;\n output \\not_strict_mode.app_rd_data_reg[27] ;\n output \\not_strict_mode.app_rd_data_reg[11] ;\n output \\not_strict_mode.app_rd_data_reg[19] ;\n output \\not_strict_mode.app_rd_data_reg[3] ;\n output \\not_strict_mode.app_rd_data_reg[26] ;\n output \\not_strict_mode.app_rd_data_reg[10] ;\n output \\not_strict_mode.app_rd_data_reg[18] ;\n output \\not_strict_mode.app_rd_data_reg[2] ;\n output \\not_strict_mode.app_rd_data_reg[25] ;\n output \\not_strict_mode.app_rd_data_reg[9] ;\n output \\not_strict_mode.app_rd_data_reg[17] ;\n output \\not_strict_mode.app_rd_data_reg[1] ;\n output \\not_strict_mode.app_rd_data_reg[24] ;\n output \\not_strict_mode.app_rd_data_reg[8] ;\n output \\not_strict_mode.app_rd_data_reg[16] ;\n output \\not_strict_mode.app_rd_data_reg[0] ;\n output [2:0]\\cmd_pipe_plus.mc_bank_reg[2] ;\n output [2:0]\\cmd_pipe_plus.mc_bank_reg[2]_0 ;\n output \\en_cnt_div4.enable_wrlvl_cnt_reg[3] ;\n output \\complex_row_cnt_ocal_reg[0] ;\n output \\row_cnt_victim_rotate.complex_row_cnt_reg[4] ;\n output pointer_we;\n output [255:0]\\not_strict_mode.app_rd_data_reg[255]_0 ;\n output app_rd_data_end_ns;\n output [3:0]\\write_buffer.wr_buf_out_data_reg[287] ;\n output [3:0]\\wr_ptr_timing_reg[2] ;\n output [3:0]\\wr_ptr_timing_reg[2]_0 ;\n output [3:0]\\wr_ptr_timing_reg[2]_1 ;\n output wr_en;\n output wr_en_5;\n output wr_en_6;\n output [1:0]ddr_ck_out;\n output [0:0]\\qcntr_r_reg[0] ;\n inout [31:0]ddr3_dq;\n inout [3:0]ddr3_dqs_p;\n inout [3:0]ddr3_dqs_n;\n input CLK;\n input p_67_out;\n input p_28_out;\n input [0:0]SR;\n input hi_priority;\n input rstdiv0_sync_r1_reg_rep__0;\n input rstdiv0_sync_r1_reg_rep__20;\n input app_ref_req;\n input app_zq_req;\n input rstdiv0_sync_r1_reg_rep__21;\n input app_hi_pri_r2;\n input app_sr_req;\n input rstdiv0_sync_r1_reg_rep__22;\n input mmcm_ps_clk;\n input rst_sync_r1;\n input poc_sample_pd;\n input freq_refclk;\n input mem_refclk;\n input sync_pulse;\n input pll_locked;\n input in0;\n input CLKB0;\n input CLKB0_7;\n input CLKB0_8;\n input CLKB0_9;\n input RST0;\n input rstdiv0_sync_r1_reg_rep__9;\n input rstdiv0_sync_r1_reg_rep__10;\n input \\req_bank_r_lcl_reg[0] ;\n input [0:0]rstdiv0_sync_r1_reg_rep__12;\n input rstdiv0_sync_r1_reg_rep__23;\n input rstdiv0_sync_r1_reg_rep__13;\n input [1:0]rstdiv0_sync_r1_reg_rep__14;\n input rstdiv0_sync_r1_reg_rep__11;\n input cnt_pwron_reset_done_r0;\n input [1:0]rstdiv0_sync_r1_reg_rep__17;\n input [0:0]rstdiv0_sync_r1_reg_rep__16;\n input [0:0]SS;\n input rstdiv0_sync_r1_reg_rep__2;\n input rstdiv0_sync_r1_reg_rep__6;\n input [287:0]Q;\n input [17:0]mem_out;\n input [71:0]\\rd_ptr_reg[3] ;\n input rstdiv0_sync_r1_reg_rep__25;\n input rstdiv0_sync_r1_reg_rep__25_0;\n input rstdiv0_sync_r1_reg_rep__24;\n input [0:0]\\sm_r_reg[0]_0 ;\n input [29:0]\\rd_ptr_reg[3]_0 ;\n input \\req_bank_r_lcl_reg[0]_0 ;\n input [4:0]\\rd_buf_indx.rd_buf_indx_r_reg[4] ;\n input ram_init_done_r;\n input sys_rst;\n input [0:0]\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ;\n input mmcm_locked;\n input rstdiv0_sync_r1_reg_rep__25_1;\n input rstdiv0_sync_r1_reg_rep__25_2;\n input \\mmcm_init_trail_reg[0] ;\n input \\mmcm_current_reg[0] ;\n input [1:0]cmd;\n input use_addr;\n input bm_end_r1_reg_1;\n input bm_end_r1_reg_2;\n input rtp_timer_ns1;\n input pass_open_bank_r_lcl_reg;\n input \\generate_maint_cmds.insert_maint_r_lcl_reg ;\n input [14:0]\\app_addr_r1_reg[27] ;\n input [1:0]DOC;\n input [1:0]DOB;\n input [1:0]DOA;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ;\n input [0:0]\\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n input [2:0]\\app_addr_r1_reg[12] ;\n input [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n input [6:0]\\app_addr_r1_reg[9] ;\n input psdone;\n input [0:0]rstdiv0_sync_r1_reg_rep__19;\n input fine_adjust_reg;\n input samp_edge_cnt0_en_r_reg;\n input [0:0]pi_cnt_dec_reg;\n input rstdiv0_sync_r1_reg_rep__23_0;\n input p_81_in;\n input rstdiv0_sync_r1_reg_rep__23_1;\n input [0:0]po_cnt_dec_reg;\n input [0:0]rstdiv0_sync_r1_reg_rep__4;\n input rstdiv0_sync_r1_reg_rep__5;\n input [11:0]\\device_temp_r_reg[11] ;\n input [0:0]rstdiv0_sync_r1_reg_rep__7;\n input \\stg3_r_reg[0] ;\n input rstdiv0_sync_r1_reg_rep__8;\n\n wire CLK;\n wire CLKB0;\n wire CLKB0_7;\n wire CLKB0_8;\n wire CLKB0_9;\n wire [0:0]D;\n wire [1:0]DOA;\n wire [1:0]DOB;\n wire [1:0]DOC;\n wire [0:0]E;\n wire [287:0]Q;\n wire RST0;\n wire [0:0]SR;\n wire [0:0]SS;\n wire accept_ns;\n wire [2:0]\\app_addr_r1_reg[12] ;\n wire [14:0]\\app_addr_r1_reg[27] ;\n wire [6:0]\\app_addr_r1_reg[9] ;\n wire app_hi_pri_r2;\n wire app_rd_data_end_ns;\n wire app_ref_ack;\n wire app_ref_req;\n wire app_sr_active;\n wire app_sr_req;\n wire app_zq_ack;\n wire app_zq_req;\n wire bm_end_r1;\n wire bm_end_r1_0;\n wire bm_end_r1_reg;\n wire bm_end_r1_reg_0;\n wire bm_end_r1_reg_1;\n wire bm_end_r1_reg_2;\n wire bypass__0;\n wire \\calib_seq_reg[0] ;\n wire [1:0]cmd;\n wire [2:0]\\cmd_pipe_plus.mc_bank_reg[2] ;\n wire [2:0]\\cmd_pipe_plus.mc_bank_reg[2]_0 ;\n wire cnt_pwron_reset_done_r0;\n wire \\col_mach0/p_0_in ;\n wire \\complex_row_cnt_ocal_reg[0] ;\n wire [14:0]ddr3_addr;\n wire [2:0]ddr3_ba;\n wire ddr3_cas_n;\n wire [0:0]ddr3_cke;\n wire [0:0]ddr3_cs_n;\n wire [3:0]ddr3_dm;\n wire [31:0]ddr3_dq;\n wire [3:0]ddr3_dqs_n;\n wire [3:0]ddr3_dqs_p;\n wire [0:0]ddr3_odt;\n wire ddr3_ras_n;\n wire ddr3_reset_n;\n wire ddr3_we_n;\n wire [1:0]ddr_ck_out;\n wire ddr_phy_top0_n_359;\n wire ddr_phy_top0_n_360;\n wire ddr_phy_top0_n_361;\n wire ddr_phy_top0_n_362;\n wire ddr_phy_top0_n_363;\n wire ddr_phy_top0_n_364;\n wire ddr_phy_top0_n_365;\n wire ddr_phy_top0_n_366;\n wire ddr_phy_top0_n_367;\n wire ddr_phy_top0_n_368;\n wire ddr_phy_top0_n_369;\n wire ddr_phy_top0_n_370;\n wire ddr_phy_top0_n_371;\n wire ddr_phy_top0_n_372;\n wire ddr_phy_top0_n_373;\n wire ddr_phy_top0_n_374;\n wire ddr_phy_top0_n_375;\n wire ddr_phy_top0_n_376;\n wire ddr_phy_top0_n_377;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire ddr_phy_top0_n_50;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire ddr_phy_top0_n_51;\n wire ddr_phy_top0_n_637;\n wire ddr_phy_top0_n_638;\n wire ddr_phy_top0_n_97;\n wire [11:0]\\device_temp_r_reg[11] ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;\n wire dqs_po_en_stg2_f_reg;\n wire \\en_cnt_div4.enable_wrlvl_cnt_reg[3] ;\n wire fine_adjust_reg;\n wire freq_refclk;\n wire \\generate_maint_cmds.insert_maint_r_lcl_reg ;\n wire hi_priority;\n wire idle;\n wire [1:0]idle_ns;\n wire in0;\n wire init_calib_complete_r_reg;\n wire insert_maint_r1_lcl_reg;\n wire mc0_n_109;\n wire mc0_n_110;\n wire mc0_n_111;\n wire mc0_n_112;\n wire mc0_n_113;\n wire mc0_n_114;\n wire mc0_n_115;\n wire mc0_n_116;\n wire mc0_n_117;\n wire mc0_n_118;\n wire mc0_n_119;\n wire mc0_n_120;\n wire [44:0]mc_address;\n wire [8:0]mc_bank;\n wire [2:0]mc_cas_n;\n wire [3:3]mc_cke;\n wire [1:0]mc_cmd;\n wire [0:0]mc_cs_n;\n wire [0:0]mc_odt;\n wire [2:0]mc_ras_n;\n wire [2:0]mc_we_n;\n wire mc_wrdata_en;\n wire [17:0]mem_out;\n wire mem_refclk;\n wire \\mmcm_current_reg[0] ;\n wire \\mmcm_init_trail_reg[0] ;\n wire mmcm_locked;\n wire mmcm_ps_clk;\n wire [43:13]mux_address;\n wire [6:0]\\not_strict_mode.app_rd_data_end_reg ;\n wire \\not_strict_mode.app_rd_data_reg[0] ;\n wire \\not_strict_mode.app_rd_data_reg[100] ;\n wire \\not_strict_mode.app_rd_data_reg[101] ;\n wire \\not_strict_mode.app_rd_data_reg[102] ;\n wire \\not_strict_mode.app_rd_data_reg[103] ;\n wire \\not_strict_mode.app_rd_data_reg[104] ;\n wire \\not_strict_mode.app_rd_data_reg[105] ;\n wire \\not_strict_mode.app_rd_data_reg[106] ;\n wire \\not_strict_mode.app_rd_data_reg[107] ;\n wire \\not_strict_mode.app_rd_data_reg[108] ;\n wire \\not_strict_mode.app_rd_data_reg[109] ;\n wire \\not_strict_mode.app_rd_data_reg[10] ;\n wire \\not_strict_mode.app_rd_data_reg[110] ;\n wire \\not_strict_mode.app_rd_data_reg[111] ;\n wire \\not_strict_mode.app_rd_data_reg[112] ;\n wire \\not_strict_mode.app_rd_data_reg[113] ;\n wire \\not_strict_mode.app_rd_data_reg[114] ;\n wire \\not_strict_mode.app_rd_data_reg[115] ;\n wire \\not_strict_mode.app_rd_data_reg[116] ;\n wire \\not_strict_mode.app_rd_data_reg[117] ;\n wire \\not_strict_mode.app_rd_data_reg[118] ;\n wire \\not_strict_mode.app_rd_data_reg[119] ;\n wire \\not_strict_mode.app_rd_data_reg[11] ;\n wire \\not_strict_mode.app_rd_data_reg[120] ;\n wire \\not_strict_mode.app_rd_data_reg[121] ;\n wire \\not_strict_mode.app_rd_data_reg[122] ;\n wire \\not_strict_mode.app_rd_data_reg[123] ;\n wire \\not_strict_mode.app_rd_data_reg[124] ;\n wire \\not_strict_mode.app_rd_data_reg[125] ;\n wire \\not_strict_mode.app_rd_data_reg[126] ;\n wire \\not_strict_mode.app_rd_data_reg[127] ;\n wire \\not_strict_mode.app_rd_data_reg[128] ;\n wire \\not_strict_mode.app_rd_data_reg[129] ;\n wire \\not_strict_mode.app_rd_data_reg[12] ;\n wire \\not_strict_mode.app_rd_data_reg[130] ;\n wire \\not_strict_mode.app_rd_data_reg[131] ;\n wire \\not_strict_mode.app_rd_data_reg[132] ;\n wire \\not_strict_mode.app_rd_data_reg[133] ;\n wire \\not_strict_mode.app_rd_data_reg[134] ;\n wire \\not_strict_mode.app_rd_data_reg[135] ;\n wire \\not_strict_mode.app_rd_data_reg[136] ;\n wire \\not_strict_mode.app_rd_data_reg[137] ;\n wire \\not_strict_mode.app_rd_data_reg[138] ;\n wire \\not_strict_mode.app_rd_data_reg[139] ;\n wire \\not_strict_mode.app_rd_data_reg[13] ;\n wire \\not_strict_mode.app_rd_data_reg[140] ;\n wire \\not_strict_mode.app_rd_data_reg[141] ;\n wire \\not_strict_mode.app_rd_data_reg[142] ;\n wire \\not_strict_mode.app_rd_data_reg[143] ;\n wire \\not_strict_mode.app_rd_data_reg[144] ;\n wire \\not_strict_mode.app_rd_data_reg[145] ;\n wire \\not_strict_mode.app_rd_data_reg[146] ;\n wire \\not_strict_mode.app_rd_data_reg[147] ;\n wire \\not_strict_mode.app_rd_data_reg[148] ;\n wire \\not_strict_mode.app_rd_data_reg[149] ;\n wire \\not_strict_mode.app_rd_data_reg[14] ;\n wire \\not_strict_mode.app_rd_data_reg[150] ;\n wire \\not_strict_mode.app_rd_data_reg[151] ;\n wire \\not_strict_mode.app_rd_data_reg[152] ;\n wire \\not_strict_mode.app_rd_data_reg[153] ;\n wire \\not_strict_mode.app_rd_data_reg[154] ;\n wire \\not_strict_mode.app_rd_data_reg[155] ;\n wire \\not_strict_mode.app_rd_data_reg[156] ;\n wire \\not_strict_mode.app_rd_data_reg[157] ;\n wire \\not_strict_mode.app_rd_data_reg[158] ;\n wire \\not_strict_mode.app_rd_data_reg[159] ;\n wire \\not_strict_mode.app_rd_data_reg[15] ;\n wire \\not_strict_mode.app_rd_data_reg[160] ;\n wire \\not_strict_mode.app_rd_data_reg[161] ;\n wire \\not_strict_mode.app_rd_data_reg[162] ;\n wire \\not_strict_mode.app_rd_data_reg[163] ;\n wire \\not_strict_mode.app_rd_data_reg[164] ;\n wire \\not_strict_mode.app_rd_data_reg[165] ;\n wire \\not_strict_mode.app_rd_data_reg[166] ;\n wire \\not_strict_mode.app_rd_data_reg[167] ;\n wire \\not_strict_mode.app_rd_data_reg[168] ;\n wire \\not_strict_mode.app_rd_data_reg[169] ;\n wire \\not_strict_mode.app_rd_data_reg[16] ;\n wire \\not_strict_mode.app_rd_data_reg[170] ;\n wire \\not_strict_mode.app_rd_data_reg[171] ;\n wire \\not_strict_mode.app_rd_data_reg[172] ;\n wire \\not_strict_mode.app_rd_data_reg[173] ;\n wire \\not_strict_mode.app_rd_data_reg[174] ;\n wire \\not_strict_mode.app_rd_data_reg[175] ;\n wire \\not_strict_mode.app_rd_data_reg[176] ;\n wire \\not_strict_mode.app_rd_data_reg[177] ;\n wire \\not_strict_mode.app_rd_data_reg[178] ;\n wire \\not_strict_mode.app_rd_data_reg[179] ;\n wire \\not_strict_mode.app_rd_data_reg[17] ;\n wire \\not_strict_mode.app_rd_data_reg[180] ;\n wire \\not_strict_mode.app_rd_data_reg[181] ;\n wire \\not_strict_mode.app_rd_data_reg[182] ;\n wire \\not_strict_mode.app_rd_data_reg[183] ;\n wire \\not_strict_mode.app_rd_data_reg[184] ;\n wire \\not_strict_mode.app_rd_data_reg[185] ;\n wire \\not_strict_mode.app_rd_data_reg[186] ;\n wire \\not_strict_mode.app_rd_data_reg[187] ;\n wire \\not_strict_mode.app_rd_data_reg[188] ;\n wire \\not_strict_mode.app_rd_data_reg[189] ;\n wire \\not_strict_mode.app_rd_data_reg[18] ;\n wire \\not_strict_mode.app_rd_data_reg[190] ;\n wire \\not_strict_mode.app_rd_data_reg[191] ;\n wire \\not_strict_mode.app_rd_data_reg[192] ;\n wire \\not_strict_mode.app_rd_data_reg[193] ;\n wire \\not_strict_mode.app_rd_data_reg[194] ;\n wire \\not_strict_mode.app_rd_data_reg[195] ;\n wire \\not_strict_mode.app_rd_data_reg[196] ;\n wire \\not_strict_mode.app_rd_data_reg[197] ;\n wire \\not_strict_mode.app_rd_data_reg[198] ;\n wire \\not_strict_mode.app_rd_data_reg[199] ;\n wire \\not_strict_mode.app_rd_data_reg[19] ;\n wire \\not_strict_mode.app_rd_data_reg[1] ;\n wire \\not_strict_mode.app_rd_data_reg[200] ;\n wire \\not_strict_mode.app_rd_data_reg[201] ;\n wire \\not_strict_mode.app_rd_data_reg[202] ;\n wire \\not_strict_mode.app_rd_data_reg[203] ;\n wire \\not_strict_mode.app_rd_data_reg[204] ;\n wire \\not_strict_mode.app_rd_data_reg[205] ;\n wire \\not_strict_mode.app_rd_data_reg[206] ;\n wire \\not_strict_mode.app_rd_data_reg[207] ;\n wire \\not_strict_mode.app_rd_data_reg[208] ;\n wire \\not_strict_mode.app_rd_data_reg[209] ;\n wire \\not_strict_mode.app_rd_data_reg[20] ;\n wire \\not_strict_mode.app_rd_data_reg[210] ;\n wire \\not_strict_mode.app_rd_data_reg[211] ;\n wire \\not_strict_mode.app_rd_data_reg[212] ;\n wire \\not_strict_mode.app_rd_data_reg[213] ;\n wire \\not_strict_mode.app_rd_data_reg[214] ;\n wire \\not_strict_mode.app_rd_data_reg[215] ;\n wire \\not_strict_mode.app_rd_data_reg[216] ;\n wire \\not_strict_mode.app_rd_data_reg[217] ;\n wire \\not_strict_mode.app_rd_data_reg[218] ;\n wire \\not_strict_mode.app_rd_data_reg[219] ;\n wire \\not_strict_mode.app_rd_data_reg[21] ;\n wire \\not_strict_mode.app_rd_data_reg[220] ;\n wire \\not_strict_mode.app_rd_data_reg[221] ;\n wire \\not_strict_mode.app_rd_data_reg[222] ;\n wire \\not_strict_mode.app_rd_data_reg[223] ;\n wire \\not_strict_mode.app_rd_data_reg[224] ;\n wire \\not_strict_mode.app_rd_data_reg[225] ;\n wire \\not_strict_mode.app_rd_data_reg[226] ;\n wire \\not_strict_mode.app_rd_data_reg[227] ;\n wire \\not_strict_mode.app_rd_data_reg[228] ;\n wire \\not_strict_mode.app_rd_data_reg[229] ;\n wire \\not_strict_mode.app_rd_data_reg[22] ;\n wire \\not_strict_mode.app_rd_data_reg[230] ;\n wire \\not_strict_mode.app_rd_data_reg[231] ;\n wire \\not_strict_mode.app_rd_data_reg[232] ;\n wire \\not_strict_mode.app_rd_data_reg[233] ;\n wire \\not_strict_mode.app_rd_data_reg[234] ;\n wire \\not_strict_mode.app_rd_data_reg[235] ;\n wire \\not_strict_mode.app_rd_data_reg[236] ;\n wire \\not_strict_mode.app_rd_data_reg[237] ;\n wire \\not_strict_mode.app_rd_data_reg[238] ;\n wire \\not_strict_mode.app_rd_data_reg[239] ;\n wire \\not_strict_mode.app_rd_data_reg[23] ;\n wire \\not_strict_mode.app_rd_data_reg[240] ;\n wire \\not_strict_mode.app_rd_data_reg[241] ;\n wire \\not_strict_mode.app_rd_data_reg[242] ;\n wire \\not_strict_mode.app_rd_data_reg[243] ;\n wire \\not_strict_mode.app_rd_data_reg[244] ;\n wire \\not_strict_mode.app_rd_data_reg[245] ;\n wire \\not_strict_mode.app_rd_data_reg[246] ;\n wire \\not_strict_mode.app_rd_data_reg[247] ;\n wire \\not_strict_mode.app_rd_data_reg[248] ;\n wire \\not_strict_mode.app_rd_data_reg[249] ;\n wire \\not_strict_mode.app_rd_data_reg[24] ;\n wire \\not_strict_mode.app_rd_data_reg[250] ;\n wire \\not_strict_mode.app_rd_data_reg[251] ;\n wire \\not_strict_mode.app_rd_data_reg[252] ;\n wire \\not_strict_mode.app_rd_data_reg[253] ;\n wire \\not_strict_mode.app_rd_data_reg[254] ;\n wire \\not_strict_mode.app_rd_data_reg[255] ;\n wire [255:0]\\not_strict_mode.app_rd_data_reg[255]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[25] ;\n wire \\not_strict_mode.app_rd_data_reg[26] ;\n wire \\not_strict_mode.app_rd_data_reg[27] ;\n wire \\not_strict_mode.app_rd_data_reg[28] ;\n wire \\not_strict_mode.app_rd_data_reg[29] ;\n wire \\not_strict_mode.app_rd_data_reg[2] ;\n wire \\not_strict_mode.app_rd_data_reg[30] ;\n wire \\not_strict_mode.app_rd_data_reg[31] ;\n wire \\not_strict_mode.app_rd_data_reg[32] ;\n wire \\not_strict_mode.app_rd_data_reg[33] ;\n wire \\not_strict_mode.app_rd_data_reg[34] ;\n wire \\not_strict_mode.app_rd_data_reg[35] ;\n wire \\not_strict_mode.app_rd_data_reg[36] ;\n wire \\not_strict_mode.app_rd_data_reg[37] ;\n wire \\not_strict_mode.app_rd_data_reg[38] ;\n wire \\not_strict_mode.app_rd_data_reg[39] ;\n wire \\not_strict_mode.app_rd_data_reg[3] ;\n wire \\not_strict_mode.app_rd_data_reg[40] ;\n wire \\not_strict_mode.app_rd_data_reg[41] ;\n wire \\not_strict_mode.app_rd_data_reg[42] ;\n wire \\not_strict_mode.app_rd_data_reg[43] ;\n wire \\not_strict_mode.app_rd_data_reg[44] ;\n wire \\not_strict_mode.app_rd_data_reg[45] ;\n wire \\not_strict_mode.app_rd_data_reg[46] ;\n wire \\not_strict_mode.app_rd_data_reg[47] ;\n wire \\not_strict_mode.app_rd_data_reg[48] ;\n wire \\not_strict_mode.app_rd_data_reg[49] ;\n wire \\not_strict_mode.app_rd_data_reg[4] ;\n wire \\not_strict_mode.app_rd_data_reg[50] ;\n wire \\not_strict_mode.app_rd_data_reg[51] ;\n wire \\not_strict_mode.app_rd_data_reg[52] ;\n wire \\not_strict_mode.app_rd_data_reg[53] ;\n wire \\not_strict_mode.app_rd_data_reg[54] ;\n wire \\not_strict_mode.app_rd_data_reg[55] ;\n wire \\not_strict_mode.app_rd_data_reg[56] ;\n wire \\not_strict_mode.app_rd_data_reg[57] ;\n wire \\not_strict_mode.app_rd_data_reg[58] ;\n wire \\not_strict_mode.app_rd_data_reg[59] ;\n wire \\not_strict_mode.app_rd_data_reg[5] ;\n wire \\not_strict_mode.app_rd_data_reg[60] ;\n wire \\not_strict_mode.app_rd_data_reg[61] ;\n wire \\not_strict_mode.app_rd_data_reg[62] ;\n wire \\not_strict_mode.app_rd_data_reg[63] ;\n wire \\not_strict_mode.app_rd_data_reg[64] ;\n wire \\not_strict_mode.app_rd_data_reg[65] ;\n wire \\not_strict_mode.app_rd_data_reg[66] ;\n wire \\not_strict_mode.app_rd_data_reg[67] ;\n wire \\not_strict_mode.app_rd_data_reg[68] ;\n wire \\not_strict_mode.app_rd_data_reg[69] ;\n wire \\not_strict_mode.app_rd_data_reg[6] ;\n wire \\not_strict_mode.app_rd_data_reg[70] ;\n wire \\not_strict_mode.app_rd_data_reg[71] ;\n wire \\not_strict_mode.app_rd_data_reg[72] ;\n wire \\not_strict_mode.app_rd_data_reg[73] ;\n wire \\not_strict_mode.app_rd_data_reg[74] ;\n wire \\not_strict_mode.app_rd_data_reg[75] ;\n wire \\not_strict_mode.app_rd_data_reg[76] ;\n wire \\not_strict_mode.app_rd_data_reg[77] ;\n wire \\not_strict_mode.app_rd_data_reg[78] ;\n wire \\not_strict_mode.app_rd_data_reg[79] ;\n wire \\not_strict_mode.app_rd_data_reg[7] ;\n wire \\not_strict_mode.app_rd_data_reg[80] ;\n wire \\not_strict_mode.app_rd_data_reg[81] ;\n wire \\not_strict_mode.app_rd_data_reg[82] ;\n wire \\not_strict_mode.app_rd_data_reg[83] ;\n wire \\not_strict_mode.app_rd_data_reg[84] ;\n wire \\not_strict_mode.app_rd_data_reg[85] ;\n wire \\not_strict_mode.app_rd_data_reg[86] ;\n wire \\not_strict_mode.app_rd_data_reg[87] ;\n wire \\not_strict_mode.app_rd_data_reg[88] ;\n wire \\not_strict_mode.app_rd_data_reg[89] ;\n wire \\not_strict_mode.app_rd_data_reg[8] ;\n wire \\not_strict_mode.app_rd_data_reg[90] ;\n wire \\not_strict_mode.app_rd_data_reg[91] ;\n wire \\not_strict_mode.app_rd_data_reg[92] ;\n wire \\not_strict_mode.app_rd_data_reg[93] ;\n wire \\not_strict_mode.app_rd_data_reg[94] ;\n wire \\not_strict_mode.app_rd_data_reg[95] ;\n wire \\not_strict_mode.app_rd_data_reg[96] ;\n wire \\not_strict_mode.app_rd_data_reg[97] ;\n wire \\not_strict_mode.app_rd_data_reg[98] ;\n wire \\not_strict_mode.app_rd_data_reg[99] ;\n wire \\not_strict_mode.app_rd_data_reg[9] ;\n wire [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ;\n wire [0:0]\\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n wire p_28_out;\n wire p_67_out;\n wire p_81_in;\n wire pass_open_bank_r_lcl_reg;\n wire [5:0]phy_dout;\n wire phy_mc_ctl_full;\n wire [0:0]pi_cnt_dec_reg;\n wire pi_en_stg2_f_timing_reg;\n wire \\pi_rst_stg1_cal_r_reg[0] ;\n wire pll_locked;\n wire [0:0]po_cnt_dec_reg;\n wire poc_sample_pd;\n wire pointer_we;\n wire psdone;\n wire [0:0]\\qcntr_r_reg[0] ;\n wire ram_init_done_r;\n wire \\rank_mach0/rank_common0/maint_prescaler_r1 ;\n wire [4:0]\\rd_buf_indx.rd_buf_indx_r_reg[4] ;\n wire rd_buf_we;\n wire [71:0]\\rd_ptr_reg[3] ;\n wire [29:0]\\rd_ptr_reg[3]_0 ;\n wire [37:0]\\rd_ptr_timing_reg[0] ;\n wire [4:0]\\rd_ptr_timing_reg[0]_0 ;\n wire \\rd_ptr_timing_reg[2] ;\n wire \\rd_ptr_timing_reg[2]_0 ;\n wire \\rd_ptr_timing_reg[2]_1 ;\n wire \\rd_ptr_timing_reg[2]_10 ;\n wire \\rd_ptr_timing_reg[2]_2 ;\n wire \\rd_ptr_timing_reg[2]_3 ;\n wire \\rd_ptr_timing_reg[2]_4 ;\n wire \\rd_ptr_timing_reg[2]_5 ;\n wire \\rd_ptr_timing_reg[2]_6 ;\n wire \\rd_ptr_timing_reg[2]_7 ;\n wire \\rd_ptr_timing_reg[2]_8 ;\n wire \\rd_ptr_timing_reg[2]_9 ;\n wire \\req_bank_r_lcl_reg[0] ;\n wire \\req_bank_r_lcl_reg[0]_0 ;\n wire [0:0]\\resume_wait_r_reg[5] ;\n wire \\row_cnt_victim_rotate.complex_row_cnt_reg[4] ;\n wire [0:0]\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ;\n wire rst_sync_r1;\n wire rst_sync_r1_reg;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__10;\n wire rstdiv0_sync_r1_reg_rep__11;\n wire [0:0]rstdiv0_sync_r1_reg_rep__12;\n wire rstdiv0_sync_r1_reg_rep__13;\n wire [1:0]rstdiv0_sync_r1_reg_rep__14;\n wire [0:0]rstdiv0_sync_r1_reg_rep__16;\n wire [1:0]rstdiv0_sync_r1_reg_rep__17;\n wire [0:0]rstdiv0_sync_r1_reg_rep__19;\n wire rstdiv0_sync_r1_reg_rep__2;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire rstdiv0_sync_r1_reg_rep__22;\n wire rstdiv0_sync_r1_reg_rep__23;\n wire rstdiv0_sync_r1_reg_rep__23_0;\n wire rstdiv0_sync_r1_reg_rep__23_1;\n wire rstdiv0_sync_r1_reg_rep__24;\n wire rstdiv0_sync_r1_reg_rep__25;\n wire rstdiv0_sync_r1_reg_rep__25_0;\n wire rstdiv0_sync_r1_reg_rep__25_1;\n wire rstdiv0_sync_r1_reg_rep__25_2;\n wire [0:0]rstdiv0_sync_r1_reg_rep__4;\n wire rstdiv0_sync_r1_reg_rep__5;\n wire rstdiv0_sync_r1_reg_rep__6;\n wire [0:0]rstdiv0_sync_r1_reg_rep__7;\n wire rstdiv0_sync_r1_reg_rep__8;\n wire rstdiv0_sync_r1_reg_rep__9;\n wire rtp_timer_ns1;\n wire samp_edge_cnt0_en_r;\n wire samp_edge_cnt0_en_r_reg;\n wire \\samps_r_reg[9] ;\n wire \\sm_r_reg[0] ;\n wire [0:0]\\sm_r_reg[0]_0 ;\n wire \\stg2_tap_cnt_reg[0] ;\n wire stg3_dec2init_val_r_reg;\n wire stg3_inc2init_val_r_reg;\n wire \\stg3_r_reg[0] ;\n wire sync_pulse;\n wire sys_rst;\n wire [0:0]tail_r;\n wire tempmon_sample_en;\n wire [1:1]\\u_ddr_mc_phy_wrapper/u_ddr_mc_phy/of_ctl_full_v ;\n wire use_addr;\n wire wr_en;\n wire wr_en_5;\n wire wr_en_6;\n wire [3:0]\\wr_ptr_timing_reg[2] ;\n wire [3:0]\\wr_ptr_timing_reg[2]_0 ;\n wire [3:0]\\wr_ptr_timing_reg[2]_1 ;\n wire [3:0]\\write_buffer.wr_buf_out_data_reg[287] ;\n\n ddr3_ifmig_7series_v4_0_ddr_phy_top ddr_phy_top0\n (.CLK(CLK),\n .CLKB0(CLKB0),\n .CLKB0_7(CLKB0_7),\n .CLKB0_8(CLKB0_8),\n .CLKB0_9(CLKB0_9),\n .D(D),\n .DOA(DOA),\n .DOB(DOB),\n .DOC(DOC),\n .Q(Q),\n .RST0(RST0),\n .SR(SR),\n .SS(SS),\n .app_zq_r_reg(ddr_phy_top0_n_50),\n .\\calib_seq_reg[0] (\\calib_seq_reg[0] ),\n .\\cmd_pipe_plus.mc_address_reg[43] ({mux_address[43],mux_address[13]}),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[0] (ddr_phy_top0_n_377),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 (mc0_n_118),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[1] (ddr_phy_top0_n_374),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[1]_0 (mc0_n_117),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[2] (mc0_n_120),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[3] (mc0_n_119),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[4] (ddr_phy_top0_n_367),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[4]_0 (mc0_n_116),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[5] ({ddr_phy_top0_n_368,ddr_phy_top0_n_369,ddr_phy_top0_n_370,ddr_phy_top0_n_371,ddr_phy_top0_n_372,ddr_phy_top0_n_373}),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[5]_0 (mc0_n_115),\n .\\cmd_pipe_plus.mc_data_offset_reg[0] (ddr_phy_top0_n_376),\n .\\cmd_pipe_plus.mc_data_offset_reg[0]_0 (mc0_n_112),\n .\\cmd_pipe_plus.mc_data_offset_reg[1] (ddr_phy_top0_n_366),\n .\\cmd_pipe_plus.mc_data_offset_reg[1]_0 (mc0_n_111),\n .\\cmd_pipe_plus.mc_data_offset_reg[2] (mc0_n_114),\n .\\cmd_pipe_plus.mc_data_offset_reg[3] (mc0_n_113),\n .\\cmd_pipe_plus.mc_data_offset_reg[4] (ddr_phy_top0_n_359),\n .\\cmd_pipe_plus.mc_data_offset_reg[4]_0 (mc0_n_110),\n .\\cmd_pipe_plus.mc_data_offset_reg[5] ({ddr_phy_top0_n_360,ddr_phy_top0_n_361,ddr_phy_top0_n_362,ddr_phy_top0_n_363,ddr_phy_top0_n_364,ddr_phy_top0_n_365}),\n .\\cmd_pipe_plus.mc_data_offset_reg[5]_0 (mc0_n_109),\n .cnt_pwron_reset_done_r0(cnt_pwron_reset_done_r0),\n .\\complex_row_cnt_ocal_reg[0] (\\complex_row_cnt_ocal_reg[0] ),\n .ddr3_addr(ddr3_addr),\n .ddr3_ba(ddr3_ba),\n .ddr3_cas_n(ddr3_cas_n),\n .ddr3_cke(ddr3_cke),\n .ddr3_cs_n(ddr3_cs_n),\n .ddr3_dm(ddr3_dm),\n .ddr3_dq(ddr3_dq),\n .ddr3_dqs_n(ddr3_dqs_n),\n .ddr3_dqs_p(ddr3_dqs_p),\n .ddr3_odt(ddr3_odt),\n .ddr3_ras_n(ddr3_ras_n),\n .ddr3_reset_n(ddr3_reset_n),\n .ddr3_we_n(ddr3_we_n),\n .ddr_ck_out(ddr_ck_out),\n .\\device_temp_r_reg[11] (\\device_temp_r_reg[11] ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ),\n .dqs_po_en_stg2_f_reg(dqs_po_en_stg2_f_reg),\n .\\en_cnt_div4.enable_wrlvl_cnt_reg[3] (\\en_cnt_div4.enable_wrlvl_cnt_reg[3] ),\n .fine_adjust_reg(fine_adjust_reg),\n .freq_refclk(freq_refclk),\n .idle(idle),\n .in0(in0),\n .init_calib_complete_r_reg(init_calib_complete_r_reg),\n .maint_prescaler_r1(\\rank_mach0/rank_common0/maint_prescaler_r1 ),\n .mc_address({mc_address[44:30],mc_address[25:18],mc_address[14:0]}),\n .mc_bank(mc_bank),\n .mc_cas_n(mc_cas_n),\n .mc_cke(mc_cke),\n .mc_cmd(mc_cmd),\n .mc_cs_n(mc_cs_n),\n .mc_odt(mc_odt),\n .mc_ras_n(mc_ras_n),\n .mc_we_n(mc_we_n),\n .mc_wrdata_en(mc_wrdata_en),\n .mem_out(mem_out),\n .mem_refclk(mem_refclk),\n .\\mmcm_current_reg[0] (\\mmcm_current_reg[0] ),\n .\\mmcm_init_trail_reg[0] (\\mmcm_init_trail_reg[0] ),\n .mmcm_locked(mmcm_locked),\n .mmcm_ps_clk(mmcm_ps_clk),\n .\\not_strict_mode.app_rd_data_reg[0] (\\not_strict_mode.app_rd_data_reg[0] ),\n .\\not_strict_mode.app_rd_data_reg[100] (\\not_strict_mode.app_rd_data_reg[100] ),\n .\\not_strict_mode.app_rd_data_reg[101] (\\not_strict_mode.app_rd_data_reg[101] ),\n .\\not_strict_mode.app_rd_data_reg[102] (\\not_strict_mode.app_rd_data_reg[102] ),\n .\\not_strict_mode.app_rd_data_reg[103] (\\not_strict_mode.app_rd_data_reg[103] ),\n .\\not_strict_mode.app_rd_data_reg[104] (\\not_strict_mode.app_rd_data_reg[104] ),\n .\\not_strict_mode.app_rd_data_reg[105] (\\not_strict_mode.app_rd_data_reg[105] ),\n .\\not_strict_mode.app_rd_data_reg[106] (\\not_strict_mode.app_rd_data_reg[106] ),\n .\\not_strict_mode.app_rd_data_reg[107] (\\not_strict_mode.app_rd_data_reg[107] ),\n .\\not_strict_mode.app_rd_data_reg[108] (\\not_strict_mode.app_rd_data_reg[108] ),\n .\\not_strict_mode.app_rd_data_reg[109] (\\not_strict_mode.app_rd_data_reg[109] ),\n .\\not_strict_mode.app_rd_data_reg[10] (\\not_strict_mode.app_rd_data_reg[10] ),\n .\\not_strict_mode.app_rd_data_reg[110] (\\not_strict_mode.app_rd_data_reg[110] ),\n .\\not_strict_mode.app_rd_data_reg[111] (\\not_strict_mode.app_rd_data_reg[111] ),\n .\\not_strict_mode.app_rd_data_reg[112] (\\not_strict_mode.app_rd_data_reg[112] ),\n .\\not_strict_mode.app_rd_data_reg[113] (\\not_strict_mode.app_rd_data_reg[113] ),\n .\\not_strict_mode.app_rd_data_reg[114] (\\not_strict_mode.app_rd_data_reg[114] ),\n .\\not_strict_mode.app_rd_data_reg[115] (\\not_strict_mode.app_rd_data_reg[115] ),\n .\\not_strict_mode.app_rd_data_reg[116] (\\not_strict_mode.app_rd_data_reg[116] ),\n .\\not_strict_mode.app_rd_data_reg[117] (\\not_strict_mode.app_rd_data_reg[117] ),\n .\\not_strict_mode.app_rd_data_reg[118] (\\not_strict_mode.app_rd_data_reg[118] ),\n .\\not_strict_mode.app_rd_data_reg[119] (\\not_strict_mode.app_rd_data_reg[119] ),\n .\\not_strict_mode.app_rd_data_reg[11] (\\not_strict_mode.app_rd_data_reg[11] ),\n .\\not_strict_mode.app_rd_data_reg[120] (\\not_strict_mode.app_rd_data_reg[120] ),\n .\\not_strict_mode.app_rd_data_reg[121] (\\not_strict_mode.app_rd_data_reg[121] ),\n .\\not_strict_mode.app_rd_data_reg[122] (\\not_strict_mode.app_rd_data_reg[122] ),\n .\\not_strict_mode.app_rd_data_reg[123] (\\not_strict_mode.app_rd_data_reg[123] ),\n .\\not_strict_mode.app_rd_data_reg[124] (\\not_strict_mode.app_rd_data_reg[124] ),\n .\\not_strict_mode.app_rd_data_reg[125] (\\not_strict_mode.app_rd_data_reg[125] ),\n .\\not_strict_mode.app_rd_data_reg[126] (\\not_strict_mode.app_rd_data_reg[126] ),\n .\\not_strict_mode.app_rd_data_reg[127] (\\not_strict_mode.app_rd_data_reg[127] ),\n .\\not_strict_mode.app_rd_data_reg[128] (\\not_strict_mode.app_rd_data_reg[128] ),\n .\\not_strict_mode.app_rd_data_reg[129] (\\not_strict_mode.app_rd_data_reg[129] ),\n .\\not_strict_mode.app_rd_data_reg[12] (\\not_strict_mode.app_rd_data_reg[12] ),\n .\\not_strict_mode.app_rd_data_reg[130] (\\not_strict_mode.app_rd_data_reg[130] ),\n .\\not_strict_mode.app_rd_data_reg[131] (\\not_strict_mode.app_rd_data_reg[131] ),\n .\\not_strict_mode.app_rd_data_reg[132] (\\not_strict_mode.app_rd_data_reg[132] ),\n .\\not_strict_mode.app_rd_data_reg[133] (\\not_strict_mode.app_rd_data_reg[133] ),\n .\\not_strict_mode.app_rd_data_reg[134] (\\not_strict_mode.app_rd_data_reg[134] ),\n .\\not_strict_mode.app_rd_data_reg[135] (\\not_strict_mode.app_rd_data_reg[135] ),\n .\\not_strict_mode.app_rd_data_reg[136] (\\not_strict_mode.app_rd_data_reg[136] ),\n .\\not_strict_mode.app_rd_data_reg[137] (\\not_strict_mode.app_rd_data_reg[137] ),\n .\\not_strict_mode.app_rd_data_reg[138] (\\not_strict_mode.app_rd_data_reg[138] ),\n .\\not_strict_mode.app_rd_data_reg[139] (\\not_strict_mode.app_rd_data_reg[139] ),\n .\\not_strict_mode.app_rd_data_reg[13] (\\not_strict_mode.app_rd_data_reg[13] ),\n .\\not_strict_mode.app_rd_data_reg[140] (\\not_strict_mode.app_rd_data_reg[140] ),\n .\\not_strict_mode.app_rd_data_reg[141] (\\not_strict_mode.app_rd_data_reg[141] ),\n .\\not_strict_mode.app_rd_data_reg[142] (\\not_strict_mode.app_rd_data_reg[142] ),\n .\\not_strict_mode.app_rd_data_reg[143] (\\not_strict_mode.app_rd_data_reg[143] ),\n .\\not_strict_mode.app_rd_data_reg[144] (\\not_strict_mode.app_rd_data_reg[144] ),\n .\\not_strict_mode.app_rd_data_reg[145] (\\not_strict_mode.app_rd_data_reg[145] ),\n .\\not_strict_mode.app_rd_data_reg[146] (\\not_strict_mode.app_rd_data_reg[146] ),\n .\\not_strict_mode.app_rd_data_reg[147] (\\not_strict_mode.app_rd_data_reg[147] ),\n .\\not_strict_mode.app_rd_data_reg[148] (\\not_strict_mode.app_rd_data_reg[148] ),\n .\\not_strict_mode.app_rd_data_reg[149] (\\not_strict_mode.app_rd_data_reg[149] ),\n .\\not_strict_mode.app_rd_data_reg[14] (\\not_strict_mode.app_rd_data_reg[14] ),\n .\\not_strict_mode.app_rd_data_reg[150] (\\not_strict_mode.app_rd_data_reg[150] ),\n .\\not_strict_mode.app_rd_data_reg[151] (\\not_strict_mode.app_rd_data_reg[151] ),\n .\\not_strict_mode.app_rd_data_reg[152] (\\not_strict_mode.app_rd_data_reg[152] ),\n .\\not_strict_mode.app_rd_data_reg[153] (\\not_strict_mode.app_rd_data_reg[153] ),\n .\\not_strict_mode.app_rd_data_reg[154] (\\not_strict_mode.app_rd_data_reg[154] ),\n .\\not_strict_mode.app_rd_data_reg[155] (\\not_strict_mode.app_rd_data_reg[155] ),\n .\\not_strict_mode.app_rd_data_reg[156] (\\not_strict_mode.app_rd_data_reg[156] ),\n .\\not_strict_mode.app_rd_data_reg[157] (\\not_strict_mode.app_rd_data_reg[157] ),\n .\\not_strict_mode.app_rd_data_reg[158] (\\not_strict_mode.app_rd_data_reg[158] ),\n .\\not_strict_mode.app_rd_data_reg[159] (\\not_strict_mode.app_rd_data_reg[159] ),\n .\\not_strict_mode.app_rd_data_reg[15] (\\not_strict_mode.app_rd_data_reg[15] ),\n .\\not_strict_mode.app_rd_data_reg[160] (\\not_strict_mode.app_rd_data_reg[160] ),\n .\\not_strict_mode.app_rd_data_reg[161] (\\not_strict_mode.app_rd_data_reg[161] ),\n .\\not_strict_mode.app_rd_data_reg[162] (\\not_strict_mode.app_rd_data_reg[162] ),\n .\\not_strict_mode.app_rd_data_reg[163] (\\not_strict_mode.app_rd_data_reg[163] ),\n .\\not_strict_mode.app_rd_data_reg[164] (\\not_strict_mode.app_rd_data_reg[164] ),\n .\\not_strict_mode.app_rd_data_reg[165] (\\not_strict_mode.app_rd_data_reg[165] ),\n .\\not_strict_mode.app_rd_data_reg[166] (\\not_strict_mode.app_rd_data_reg[166] ),\n .\\not_strict_mode.app_rd_data_reg[167] (\\not_strict_mode.app_rd_data_reg[167] ),\n .\\not_strict_mode.app_rd_data_reg[168] (\\not_strict_mode.app_rd_data_reg[168] ),\n .\\not_strict_mode.app_rd_data_reg[169] (\\not_strict_mode.app_rd_data_reg[169] ),\n .\\not_strict_mode.app_rd_data_reg[16] (\\not_strict_mode.app_rd_data_reg[16] ),\n .\\not_strict_mode.app_rd_data_reg[170] (\\not_strict_mode.app_rd_data_reg[170] ),\n .\\not_strict_mode.app_rd_data_reg[171] (\\not_strict_mode.app_rd_data_reg[171] ),\n .\\not_strict_mode.app_rd_data_reg[172] (\\not_strict_mode.app_rd_data_reg[172] ),\n .\\not_strict_mode.app_rd_data_reg[173] (\\not_strict_mode.app_rd_data_reg[173] ),\n .\\not_strict_mode.app_rd_data_reg[174] (\\not_strict_mode.app_rd_data_reg[174] ),\n .\\not_strict_mode.app_rd_data_reg[175] (\\not_strict_mode.app_rd_data_reg[175] ),\n .\\not_strict_mode.app_rd_data_reg[176] (\\not_strict_mode.app_rd_data_reg[176] ),\n .\\not_strict_mode.app_rd_data_reg[177] (\\not_strict_mode.app_rd_data_reg[177] ),\n .\\not_strict_mode.app_rd_data_reg[178] (\\not_strict_mode.app_rd_data_reg[178] ),\n .\\not_strict_mode.app_rd_data_reg[179] (\\not_strict_mode.app_rd_data_reg[179] ),\n .\\not_strict_mode.app_rd_data_reg[17] (\\not_strict_mode.app_rd_data_reg[17] ),\n .\\not_strict_mode.app_rd_data_reg[180] (\\not_strict_mode.app_rd_data_reg[180] ),\n .\\not_strict_mode.app_rd_data_reg[181] (\\not_strict_mode.app_rd_data_reg[181] ),\n .\\not_strict_mode.app_rd_data_reg[182] (\\not_strict_mode.app_rd_data_reg[182] ),\n .\\not_strict_mode.app_rd_data_reg[183] (\\not_strict_mode.app_rd_data_reg[183] ),\n .\\not_strict_mode.app_rd_data_reg[184] (\\not_strict_mode.app_rd_data_reg[184] ),\n .\\not_strict_mode.app_rd_data_reg[185] (\\not_strict_mode.app_rd_data_reg[185] ),\n .\\not_strict_mode.app_rd_data_reg[186] (\\not_strict_mode.app_rd_data_reg[186] ),\n .\\not_strict_mode.app_rd_data_reg[187] (\\not_strict_mode.app_rd_data_reg[187] ),\n .\\not_strict_mode.app_rd_data_reg[188] (\\not_strict_mode.app_rd_data_reg[188] ),\n .\\not_strict_mode.app_rd_data_reg[189] (\\not_strict_mode.app_rd_data_reg[189] ),\n .\\not_strict_mode.app_rd_data_reg[18] (\\not_strict_mode.app_rd_data_reg[18] ),\n .\\not_strict_mode.app_rd_data_reg[190] (\\not_strict_mode.app_rd_data_reg[190] ),\n .\\not_strict_mode.app_rd_data_reg[191] (\\not_strict_mode.app_rd_data_reg[191] ),\n .\\not_strict_mode.app_rd_data_reg[192] (\\not_strict_mode.app_rd_data_reg[192] ),\n .\\not_strict_mode.app_rd_data_reg[193] (\\not_strict_mode.app_rd_data_reg[193] ),\n .\\not_strict_mode.app_rd_data_reg[194] (\\not_strict_mode.app_rd_data_reg[194] ),\n .\\not_strict_mode.app_rd_data_reg[195] (\\not_strict_mode.app_rd_data_reg[195] ),\n .\\not_strict_mode.app_rd_data_reg[196] (\\not_strict_mode.app_rd_data_reg[196] ),\n .\\not_strict_mode.app_rd_data_reg[197] (\\not_strict_mode.app_rd_data_reg[197] ),\n .\\not_strict_mode.app_rd_data_reg[198] (\\not_strict_mode.app_rd_data_reg[198] ),\n .\\not_strict_mode.app_rd_data_reg[199] (\\not_strict_mode.app_rd_data_reg[199] ),\n .\\not_strict_mode.app_rd_data_reg[19] (\\not_strict_mode.app_rd_data_reg[19] ),\n .\\not_strict_mode.app_rd_data_reg[1] (\\not_strict_mode.app_rd_data_reg[1] ),\n .\\not_strict_mode.app_rd_data_reg[200] (\\not_strict_mode.app_rd_data_reg[200] ),\n .\\not_strict_mode.app_rd_data_reg[201] (\\not_strict_mode.app_rd_data_reg[201] ),\n .\\not_strict_mode.app_rd_data_reg[202] (\\not_strict_mode.app_rd_data_reg[202] ),\n .\\not_strict_mode.app_rd_data_reg[203] (\\not_strict_mode.app_rd_data_reg[203] ),\n .\\not_strict_mode.app_rd_data_reg[204] (\\not_strict_mode.app_rd_data_reg[204] ),\n .\\not_strict_mode.app_rd_data_reg[205] (\\not_strict_mode.app_rd_data_reg[205] ),\n .\\not_strict_mode.app_rd_data_reg[206] (\\not_strict_mode.app_rd_data_reg[206] ),\n .\\not_strict_mode.app_rd_data_reg[207] (\\not_strict_mode.app_rd_data_reg[207] ),\n .\\not_strict_mode.app_rd_data_reg[208] (\\not_strict_mode.app_rd_data_reg[208] ),\n .\\not_strict_mode.app_rd_data_reg[209] (\\not_strict_mode.app_rd_data_reg[209] ),\n .\\not_strict_mode.app_rd_data_reg[20] (\\not_strict_mode.app_rd_data_reg[20] ),\n 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.\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ),\n .\\not_strict_mode.status_ram.rd_buf_we_r1_reg (ddr_phy_top0_n_97),\n .of_ctl_full_v(\\u_ddr_mc_phy_wrapper/u_ddr_mc_phy/of_ctl_full_v ),\n .ofs_rdy_r_reg(ddr_phy_top0_n_637),\n .ofs_rdy_r_reg_0(ddr_phy_top0_n_638),\n .p_81_in(p_81_in),\n .\\periodic_rd_generation.periodic_rd_timer_r_reg[1] (ddr_phy_top0_n_51),\n .phy_dout({phy_dout[5:3],phy_dout[1]}),\n .phy_mc_ctl_full(phy_mc_ctl_full),\n .pi_cnt_dec_reg(pi_cnt_dec_reg),\n .pi_en_stg2_f_timing_reg(pi_en_stg2_f_timing_reg),\n .\\pi_rst_stg1_cal_r_reg[0] (\\pi_rst_stg1_cal_r_reg[0] ),\n .pll_locked(pll_locked),\n .po_cnt_dec_reg(po_cnt_dec_reg),\n .poc_sample_pd(poc_sample_pd),\n .psdone(psdone),\n .\\qcntr_r_reg[0] (\\qcntr_r_reg[0] ),\n .ram_init_done_r(ram_init_done_r),\n .rd_buf_we(rd_buf_we),\n .\\rd_ptr_reg[3] (\\rd_ptr_reg[3] ),\n .\\rd_ptr_reg[3]_0 (\\rd_ptr_reg[3]_0 ),\n .\\rd_ptr_timing_reg[0] ({\\rd_ptr_timing_reg[0] [37:6],\\rd_ptr_timing_reg[0] [4],\\rd_ptr_timing_reg[0] [1]}),\n .\\rd_ptr_timing_reg[0]_0 ({\\rd_ptr_timing_reg[0]_0 [3],\\rd_ptr_timing_reg[0]_0 [1]}),\n .\\rd_ptr_timing_reg[2] (\\rd_ptr_timing_reg[2] ),\n .\\rd_ptr_timing_reg[2]_0 (\\rd_ptr_timing_reg[2]_0 ),\n .\\rd_ptr_timing_reg[2]_1 (\\rd_ptr_timing_reg[2]_1 ),\n .\\rd_ptr_timing_reg[2]_10 (\\rd_ptr_timing_reg[2]_10 ),\n .\\rd_ptr_timing_reg[2]_2 (\\rd_ptr_timing_reg[2]_2 ),\n .\\rd_ptr_timing_reg[2]_3 (\\rd_ptr_timing_reg[2]_3 ),\n .\\rd_ptr_timing_reg[2]_4 (\\rd_ptr_timing_reg[2]_4 ),\n .\\rd_ptr_timing_reg[2]_5 (\\rd_ptr_timing_reg[2]_5 ),\n .\\rd_ptr_timing_reg[2]_6 (\\rd_ptr_timing_reg[2]_6 ),\n .\\rd_ptr_timing_reg[2]_7 (\\rd_ptr_timing_reg[2]_7 ),\n .\\rd_ptr_timing_reg[2]_8 (\\rd_ptr_timing_reg[2]_8 ),\n .\\rd_ptr_timing_reg[2]_9 (\\rd_ptr_timing_reg[2]_9 ),\n .\\read_fifo.fifo_out_data_r_reg[6] (\\col_mach0/p_0_in ),\n .\\read_fifo.fifo_out_data_r_reg[6]_0 (bypass__0),\n .\\read_fifo.tail_r_reg[0] (ddr_phy_top0_n_375),\n .\\resume_wait_r_reg[5] (\\resume_wait_r_reg[5] ),\n .\\row_cnt_victim_rotate.complex_row_cnt_reg[4] (\\row_cnt_victim_rotate.complex_row_cnt_reg[4] ),\n .\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] (\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .rst_sync_r1(rst_sync_r1),\n .rst_sync_r1_reg(rst_sync_r1_reg),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10),\n .rstdiv0_sync_r1_reg_rep__11(rstdiv0_sync_r1_reg_rep__11),\n .rstdiv0_sync_r1_reg_rep__12(rstdiv0_sync_r1_reg_rep__12),\n .rstdiv0_sync_r1_reg_rep__13(rstdiv0_sync_r1_reg_rep__13),\n .rstdiv0_sync_r1_reg_rep__14(rstdiv0_sync_r1_reg_rep__14),\n .rstdiv0_sync_r1_reg_rep__16(rstdiv0_sync_r1_reg_rep__16),\n .rstdiv0_sync_r1_reg_rep__17(rstdiv0_sync_r1_reg_rep__17),\n .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),\n .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22),\n .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23),\n .rstdiv0_sync_r1_reg_rep__23_0(rstdiv0_sync_r1_reg_rep__23_0),\n .rstdiv0_sync_r1_reg_rep__23_1(rstdiv0_sync_r1_reg_rep__23_1),\n .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),\n .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25),\n .rstdiv0_sync_r1_reg_rep__25_0(rstdiv0_sync_r1_reg_rep__25_0),\n .rstdiv0_sync_r1_reg_rep__25_1(rstdiv0_sync_r1_reg_rep__25_1),\n .rstdiv0_sync_r1_reg_rep__25_2(rstdiv0_sync_r1_reg_rep__25_2),\n .rstdiv0_sync_r1_reg_rep__4(rstdiv0_sync_r1_reg_rep__4),\n .rstdiv0_sync_r1_reg_rep__5(rstdiv0_sync_r1_reg_rep__5),\n .rstdiv0_sync_r1_reg_rep__6(rstdiv0_sync_r1_reg_rep__6),\n .rstdiv0_sync_r1_reg_rep__7(rstdiv0_sync_r1_reg_rep__7),\n .rstdiv0_sync_r1_reg_rep__8(rstdiv0_sync_r1_reg_rep__8),\n .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9),\n .samp_edge_cnt0_en_r(samp_edge_cnt0_en_r),\n .samp_edge_cnt0_en_r_reg(samp_edge_cnt0_en_r_reg),\n .\\samps_r_reg[9] (\\samps_r_reg[9] ),\n .\\sm_r_reg[0] (\\sm_r_reg[0] ),\n .\\sm_r_reg[0]_0 (\\sm_r_reg[0]_0 ),\n .\\stg2_tap_cnt_reg[0] (\\stg2_tap_cnt_reg[0] ),\n .stg3_dec2init_val_r_reg(stg3_dec2init_val_r_reg),\n .stg3_inc2init_val_r_reg(stg3_inc2init_val_r_reg),\n .\\stg3_r_reg[0] (\\stg3_r_reg[0] ),\n .sync_pulse(sync_pulse),\n .sys_rst(sys_rst),\n .tail_r(tail_r),\n .tempmon_sample_en(tempmon_sample_en),\n .wr_en(wr_en),\n .wr_en_5(wr_en_5),\n .wr_en_6(wr_en_6),\n .\\wr_ptr_timing_reg[2] (\\wr_ptr_timing_reg[2] ),\n .\\wr_ptr_timing_reg[2]_0 (\\wr_ptr_timing_reg[2]_0 ),\n .\\wr_ptr_timing_reg[2]_1 (\\wr_ptr_timing_reg[2]_1 ));\n ddr3_ifmig_7series_v4_0_mc mc0\n (.CLK(CLK),\n .E(idle_ns[0]),\n .Q({\\not_strict_mode.app_rd_data_end_reg [6],\\col_mach0/p_0_in ,\\not_strict_mode.app_rd_data_end_reg [5:0]}),\n .SR(SR),\n .accept_ns(accept_ns),\n .\\app_addr_r1_reg[12] (\\app_addr_r1_reg[12] ),\n .\\app_addr_r1_reg[27] (\\app_addr_r1_reg[27] ),\n .\\app_addr_r1_reg[9] (\\app_addr_r1_reg[9] ),\n .app_hi_pri_r2(app_hi_pri_r2),\n .app_rd_data_end_ns(app_rd_data_end_ns),\n .app_ref_ack(app_ref_ack),\n .app_ref_req(app_ref_req),\n .app_sr_active(app_sr_active),\n .app_sr_req(app_sr_req),\n .app_zq_ack(app_zq_ack),\n .app_zq_req(app_zq_req),\n .bm_end_r1(bm_end_r1),\n .bm_end_r1_0(bm_end_r1_0),\n .bm_end_r1_reg(bm_end_r1_reg),\n .bm_end_r1_reg_0(bm_end_r1_reg_0),\n .bm_end_r1_reg_1(bm_end_r1_reg_1),\n .bm_end_r1_reg_2(bm_end_r1_reg_2),\n .bypass__0(bypass__0),\n .cmd(cmd),\n .\\cmd_pipe_plus.mc_bank_reg[2]_0 (\\cmd_pipe_plus.mc_bank_reg[2] ),\n .\\cmd_pipe_plus.mc_bank_reg[2]_1 (\\cmd_pipe_plus.mc_bank_reg[2]_0 ),\n .\\data_offset_1_i1_reg[0] (mc0_n_118),\n .\\data_offset_1_i1_reg[1] (mc0_n_117),\n .\\data_offset_1_i1_reg[2] (mc0_n_120),\n .\\data_offset_1_i1_reg[3] (mc0_n_119),\n .\\data_offset_1_i1_reg[4] (mc0_n_116),\n .\\data_offset_1_i1_reg[5] (mc0_n_115),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (ddr_phy_top0_n_97),\n .\\entry_cnt_reg[2] (ddr_phy_top0_n_638),\n .\\entry_cnt_reg[2]_0 (ddr_phy_top0_n_637),\n .\\generate_maint_cmds.insert_maint_r_lcl_reg (\\generate_maint_cmds.insert_maint_r_lcl_reg ),\n .hi_priority(hi_priority),\n .idle(idle),\n .idle_r_lcl_reg(idle_ns[1]),\n .init_calib_complete_reg_rep__6(ddr_phy_top0_n_50),\n .init_calib_complete_reg_rep__7(ddr_phy_top0_n_51),\n .insert_maint_r1_lcl_reg(insert_maint_r1_lcl_reg),\n .maint_prescaler_r1(\\rank_mach0/rank_common0/maint_prescaler_r1 ),\n .mc_address({mc_address[44:30],mc_address[25:18],mc_address[14:0]}),\n .mc_bank(mc_bank),\n .mc_cas_n(mc_cas_n),\n .mc_cke(mc_cke),\n .mc_cmd(mc_cmd),\n .mc_cs_n(mc_cs_n),\n .mc_odt(mc_odt),\n .mc_ras_n(mc_ras_n),\n .mc_we_n(mc_we_n),\n .mc_wrdata_en(mc_wrdata_en),\n .\\my_empty_reg[7] ({mux_address[43],mux_address[13]}),\n .\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),\n .\\not_strict_mode.status_ram.rd_buf_we_r1_reg (\\not_strict_mode.status_ram.rd_buf_we_r1_reg ),\n .of_ctl_full_v(\\u_ddr_mc_phy_wrapper/u_ddr_mc_phy/of_ctl_full_v ),\n .p_28_out(p_28_out),\n .p_67_out(p_67_out),\n .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg),\n .\\phy_ctl_wd_i1_reg[17] (mc0_n_112),\n .\\phy_ctl_wd_i1_reg[18] (mc0_n_111),\n .\\phy_ctl_wd_i1_reg[19] (mc0_n_114),\n .\\phy_ctl_wd_i1_reg[20] (mc0_n_113),\n .\\phy_ctl_wd_i1_reg[21] (mc0_n_110),\n .\\phy_ctl_wd_i1_reg[22] (mc0_n_109),\n .phy_dout({phy_dout[2],phy_dout[0]}),\n .phy_mc_ctl_full(phy_mc_ctl_full),\n .pointer_we(pointer_we),\n .ram_init_done_r(ram_init_done_r),\n .\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] (ddr_phy_top0_n_366),\n .\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 (ddr_phy_top0_n_376),\n .\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4] (ddr_phy_top0_n_359),\n .\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ({ddr_phy_top0_n_360,ddr_phy_top0_n_361,ddr_phy_top0_n_362,ddr_phy_top0_n_363,ddr_phy_top0_n_364,ddr_phy_top0_n_365}),\n .\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10] (ddr_phy_top0_n_367),\n .\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ({ddr_phy_top0_n_368,ddr_phy_top0_n_369,ddr_phy_top0_n_370,ddr_phy_top0_n_371,ddr_phy_top0_n_372,ddr_phy_top0_n_373}),\n .\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] (ddr_phy_top0_n_374),\n .\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0 (ddr_phy_top0_n_377),\n .\\rd_buf_indx.rd_buf_indx_r_reg[4] (\\rd_buf_indx.rd_buf_indx_r_reg[4] ),\n .\\rd_ptr_timing_reg[0] ({\\rd_ptr_timing_reg[0]_0 [4],\\rd_ptr_timing_reg[0]_0 [2],\\rd_ptr_timing_reg[0]_0 [0]}),\n .\\rd_ptr_timing_reg[0]_0 ({\\rd_ptr_timing_reg[0] [5],\\rd_ptr_timing_reg[0] [3:2],\\rd_ptr_timing_reg[0] [0]}),\n .\\read_data_indx.rd_data_indx_r_reg[0] (E),\n .\\read_fifo.tail_r_reg[0] (ddr_phy_top0_n_375),\n .\\read_fifo.tail_r_reg[1] (tail_r),\n .\\req_bank_r_lcl_reg[0] (\\req_bank_r_lcl_reg[0] ),\n .\\req_bank_r_lcl_reg[0]_0 (\\req_bank_r_lcl_reg[0]_0 ),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22),\n .rtp_timer_ns1(rtp_timer_ns1),\n .tempmon_sample_en(tempmon_sample_en),\n .use_addr(use_addr),\n .\\write_buffer.wr_buf_out_data_reg[287] (\\write_buffer.wr_buf_out_data_reg[287] ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_memc_ui_top_axi\" *) \nmodule ddr3_ifmig_7series_v4_0_memc_ui_top_axi\n (insert_maint_r,\n app_ref_ack,\n app_zq_ack,\n bm_end_r1,\n pass_open_bank_r,\n bm_end_r1_0,\n pass_open_bank_r_1,\n app_sr_active,\n ddr3_reset_n,\n ddr3_cas_n,\n ddr3_ras_n,\n ddr3_we_n,\n ddr3_addr,\n ddr3_ba,\n ddr3_cs_n,\n ddr3_odt,\n ddr3_cke,\n ddr3_dm,\n \\rd_ptr_timing_reg[2] ,\n \\rd_ptr_timing_reg[2]_0 ,\n \\rd_ptr_timing_reg[2]_1 ,\n \\rd_ptr_timing_reg[2]_2 ,\n \\rd_ptr_timing_reg[2]_3 ,\n \\rd_ptr_timing_reg[2]_4 ,\n \\rd_ptr_timing_reg[2]_5 ,\n \\rd_ptr_timing_reg[2]_6 ,\n \\rd_ptr_timing_reg[2]_7 ,\n \\rd_ptr_timing_reg[2]_8 ,\n \\rd_ptr_timing_reg[2]_9 ,\n \\rd_ptr_timing_reg[2]_10 ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,\n phy_dout,\n sm_r,\n phy_mc_go,\n \\pi_rst_stg1_cal_r_reg[0] ,\n samp_edge_cnt0_en_r,\n pi_cnt_dec,\n po_cnt_dec,\n \\rd_ptr_timing_reg[0] ,\n \\rd_ptr_timing_reg[0]_0 ,\n \\resume_wait_r_reg[5] ,\n stg3_dec2init_val_r_reg,\n stg3_inc2init_val_r_reg,\n rst_sync_r1_reg,\n s_axi_arready,\n \\stg2_tap_cnt_reg[0] ,\n \\sm_r_reg[0] ,\n D,\n \\en_cnt_div4.enable_wrlvl_cnt_reg[3] ,\n \\complex_row_cnt_ocal_reg[0] ,\n \\row_cnt_victim_rotate.complex_row_cnt_reg[4] ,\n Q,\n \\wr_ptr_timing_reg[2] ,\n \\wr_ptr_timing_reg[2]_0 ,\n wr_en,\n wr_en_5,\n wr_en_6,\n ddr_ck_out,\n E,\n s_axi_awready,\n s_axi_wready,\n out,\n s_axi_rid,\n s_axi_bid,\n s_axi_bvalid,\n s_axi_rvalid,\n s_axi_rlast,\n ddr3_dq,\n ddr3_dqs_p,\n ddr3_dqs_n,\n CLK,\n SR,\n rstdiv0_sync_r1_reg_rep__0,\n rstdiv0_sync_r1_reg_rep__20,\n app_ref_req,\n app_zq_req,\n rstdiv0_sync_r1_reg_rep__21,\n app_sr_req,\n rstdiv0_sync_r1_reg_rep__22,\n mmcm_ps_clk,\n rst_sync_r1,\n poc_sample_pd,\n freq_refclk,\n mem_refclk,\n sync_pulse,\n pll_locked,\n in0,\n CLKB0,\n CLKB0_7,\n CLKB0_8,\n CLKB0_9,\n RST0,\n rstdiv0_sync_r1_reg_rep__9,\n rstdiv0_sync_r1_reg_rep__10,\n rstdiv0_sync_r1_reg_rep__25,\n rstdiv0_sync_r1_reg_rep__12,\n rstdiv0_sync_r1_reg_rep__23,\n rstdiv0_sync_r1_reg_rep__13,\n rstdiv0_sync_r1_reg_rep__14,\n rstdiv0_sync_r1_reg_rep__11,\n cnt_pwron_reset_done_r0,\n rstdiv0_sync_r1_reg_rep__17,\n rstdiv0_sync_r1_reg_rep__16,\n SS,\n rstdiv0_sync_r1_reg_rep__2,\n rstdiv0_sync_r1_reg_rep__6,\n mem_out,\n \\rd_ptr_reg[3] ,\n rstdiv0_sync_r1_reg_rep__25_0,\n rstdiv0_sync_r1_reg_rep__24,\n \\sm_r_reg[0]_0 ,\n \\rd_ptr_reg[3]_0 ,\n sys_rst,\n \\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ,\n mmcm_locked,\n s_axi_arvalid,\n rstdiv0_sync_r1_reg_rep__25_1,\n rstdiv0_sync_r1_reg_rep__25_2,\n \\mmcm_init_trail_reg[0] ,\n \\mmcm_current_reg[0] ,\n bm_end_r1_reg,\n bm_end_r1_reg_0,\n rtp_timer_ns1,\n pass_open_bank_r_lcl_reg,\n \\generate_maint_cmds.insert_maint_r_lcl_reg ,\n psdone,\n rstdiv0_sync_r1_reg_rep__19,\n fine_adjust_reg,\n samp_edge_cnt0_en_r_reg,\n pi_cnt_dec_reg,\n rstdiv0_sync_r1_reg_rep__23_0,\n p_81_in,\n rstdiv0_sync_r1_reg_rep__23_1,\n po_cnt_dec_reg,\n rstdiv0_sync_r1_reg_rep__4,\n rstdiv0_sync_r1_reg_rep__5,\n \\device_temp_r_reg[11] ,\n rstdiv0_sync_r1_reg_rep__7,\n \\stg3_r_reg[0] ,\n rstdiv0_sync_r1_reg_rep__8,\n s_axi_awlen,\n s_axi_bready,\n s_axi_awvalid,\n s_axi_awaddr,\n s_axi_awburst,\n s_axi_wvalid,\n s_axi_awid,\n s_axi_arlen,\n s_axi_araddr,\n s_axi_arburst,\n s_axi_rready,\n s_axi_wstrb,\n s_axi_wdata,\n aresetn,\n s_axi_arid);\n output insert_maint_r;\n output app_ref_ack;\n output app_zq_ack;\n output bm_end_r1;\n output pass_open_bank_r;\n output bm_end_r1_0;\n output pass_open_bank_r_1;\n output app_sr_active;\n output ddr3_reset_n;\n output ddr3_cas_n;\n output ddr3_ras_n;\n output ddr3_we_n;\n output [14:0]ddr3_addr;\n output [2:0]ddr3_ba;\n output [0:0]ddr3_cs_n;\n output [0:0]ddr3_odt;\n output [0:0]ddr3_cke;\n output [3:0]ddr3_dm;\n output \\rd_ptr_timing_reg[2] ;\n output \\rd_ptr_timing_reg[2]_0 ;\n output \\rd_ptr_timing_reg[2]_1 ;\n output \\rd_ptr_timing_reg[2]_2 ;\n output \\rd_ptr_timing_reg[2]_3 ;\n output \\rd_ptr_timing_reg[2]_4 ;\n output \\rd_ptr_timing_reg[2]_5 ;\n output \\rd_ptr_timing_reg[2]_6 ;\n output \\rd_ptr_timing_reg[2]_7 ;\n output \\rd_ptr_timing_reg[2]_8 ;\n output \\rd_ptr_timing_reg[2]_9 ;\n output \\rd_ptr_timing_reg[2]_10 ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;\n output [5:0]phy_dout;\n output sm_r;\n output phy_mc_go;\n output \\pi_rst_stg1_cal_r_reg[0] ;\n output samp_edge_cnt0_en_r;\n output pi_cnt_dec;\n output po_cnt_dec;\n output [37:0]\\rd_ptr_timing_reg[0] ;\n output [4:0]\\rd_ptr_timing_reg[0]_0 ;\n output \\resume_wait_r_reg[5] ;\n output stg3_dec2init_val_r_reg;\n output stg3_inc2init_val_r_reg;\n output rst_sync_r1_reg;\n output s_axi_arready;\n output \\stg2_tap_cnt_reg[0] ;\n output \\sm_r_reg[0] ;\n output [0:0]D;\n output \\en_cnt_div4.enable_wrlvl_cnt_reg[3] ;\n output \\complex_row_cnt_ocal_reg[0] ;\n output \\row_cnt_victim_rotate.complex_row_cnt_reg[4] ;\n output [3:0]Q;\n output [3:0]\\wr_ptr_timing_reg[2] ;\n output [3:0]\\wr_ptr_timing_reg[2]_0 ;\n output wr_en;\n output wr_en_5;\n output wr_en_6;\n output [1:0]ddr_ck_out;\n output [0:0]E;\n output s_axi_awready;\n output s_axi_wready;\n output [256:0]out;\n output [0:0]s_axi_rid;\n output [0:0]s_axi_bid;\n output s_axi_bvalid;\n output s_axi_rvalid;\n output s_axi_rlast;\n inout [31:0]ddr3_dq;\n inout [3:0]ddr3_dqs_p;\n inout [3:0]ddr3_dqs_n;\n input CLK;\n input [0:0]SR;\n input rstdiv0_sync_r1_reg_rep__0;\n input rstdiv0_sync_r1_reg_rep__20;\n input app_ref_req;\n input app_zq_req;\n input rstdiv0_sync_r1_reg_rep__21;\n input app_sr_req;\n input rstdiv0_sync_r1_reg_rep__22;\n input mmcm_ps_clk;\n input rst_sync_r1;\n input poc_sample_pd;\n input freq_refclk;\n input mem_refclk;\n input sync_pulse;\n input pll_locked;\n input in0;\n input CLKB0;\n input CLKB0_7;\n input CLKB0_8;\n input CLKB0_9;\n input RST0;\n input rstdiv0_sync_r1_reg_rep__9;\n input rstdiv0_sync_r1_reg_rep__10;\n input rstdiv0_sync_r1_reg_rep__25;\n input [0:0]rstdiv0_sync_r1_reg_rep__12;\n input rstdiv0_sync_r1_reg_rep__23;\n input rstdiv0_sync_r1_reg_rep__13;\n input [1:0]rstdiv0_sync_r1_reg_rep__14;\n input rstdiv0_sync_r1_reg_rep__11;\n input cnt_pwron_reset_done_r0;\n input [1:0]rstdiv0_sync_r1_reg_rep__17;\n input [0:0]rstdiv0_sync_r1_reg_rep__16;\n input [0:0]SS;\n input rstdiv0_sync_r1_reg_rep__2;\n input rstdiv0_sync_r1_reg_rep__6;\n input [17:0]mem_out;\n input [71:0]\\rd_ptr_reg[3] ;\n input rstdiv0_sync_r1_reg_rep__25_0;\n input rstdiv0_sync_r1_reg_rep__24;\n input [0:0]\\sm_r_reg[0]_0 ;\n input [29:0]\\rd_ptr_reg[3]_0 ;\n input sys_rst;\n input [0:0]\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ;\n input mmcm_locked;\n input s_axi_arvalid;\n input rstdiv0_sync_r1_reg_rep__25_1;\n input rstdiv0_sync_r1_reg_rep__25_2;\n input \\mmcm_init_trail_reg[0] ;\n input \\mmcm_current_reg[0] ;\n input bm_end_r1_reg;\n input bm_end_r1_reg_0;\n input rtp_timer_ns1;\n input pass_open_bank_r_lcl_reg;\n input \\generate_maint_cmds.insert_maint_r_lcl_reg ;\n input psdone;\n input [0:0]rstdiv0_sync_r1_reg_rep__19;\n input fine_adjust_reg;\n input samp_edge_cnt0_en_r_reg;\n input [0:0]pi_cnt_dec_reg;\n input rstdiv0_sync_r1_reg_rep__23_0;\n input p_81_in;\n input rstdiv0_sync_r1_reg_rep__23_1;\n input [0:0]po_cnt_dec_reg;\n input [0:0]rstdiv0_sync_r1_reg_rep__4;\n input rstdiv0_sync_r1_reg_rep__5;\n input [11:0]\\device_temp_r_reg[11] ;\n input [0:0]rstdiv0_sync_r1_reg_rep__7;\n input \\stg3_r_reg[0] ;\n input rstdiv0_sync_r1_reg_rep__8;\n input [7:0]s_axi_awlen;\n input s_axi_bready;\n input s_axi_awvalid;\n input [29:0]s_axi_awaddr;\n input [0:0]s_axi_awburst;\n input s_axi_wvalid;\n input [0:0]s_axi_awid;\n input [7:0]s_axi_arlen;\n input [29:0]s_axi_araddr;\n input [0:0]s_axi_arburst;\n input s_axi_rready;\n input [31:0]s_axi_wstrb;\n input [255:0]s_axi_wdata;\n input aresetn;\n input [0:0]s_axi_arid;\n\n wire CLK;\n wire CLKB0;\n wire CLKB0_7;\n wire CLKB0_8;\n wire CLKB0_9;\n wire [0:0]D;\n wire [0:0]E;\n wire [3:0]Q;\n wire RST0;\n wire [0:0]SR;\n wire [0:0]SS;\n wire accept_ns;\n wire [27:3]app_addr;\n wire [0:0]app_cmd;\n wire [255:0]app_rd_data;\n wire [255:0]app_rd_data_ns;\n wire app_rd_data_valid;\n wire app_rdy;\n wire app_ref_ack;\n wire app_ref_req;\n wire app_sr_active;\n wire app_sr_req;\n wire [255:0]app_wdf_data;\n wire [31:0]app_wdf_mask;\n wire app_wdf_rdy;\n wire app_zq_ack;\n wire app_zq_req;\n wire aresetn;\n wire [255:0]\\axi_mc_w_channel_0/mc_app_wdf_data_reg ;\n wire [31:0]\\axi_mc_w_channel_0/mc_app_wdf_mask_reg ;\n wire \\axi_mc_w_channel_0/mc_app_wdf_wren_reg ;\n wire [255:0]\\axi_mc_w_channel_0/next_wdf_data ;\n wire [31:0]\\axi_mc_w_channel_0/next_wdf_mask ;\n wire [2:0]bank;\n wire bm_end_r1;\n wire bm_end_r1_0;\n wire bm_end_r1_reg;\n wire bm_end_r1_reg_0;\n wire [1:0]cmd;\n wire cnt_pwron_reset_done_r0;\n wire [9:3]col;\n wire \\complex_row_cnt_ocal_reg[0] ;\n wire [4:0]data_buf_addr;\n wire [14:0]ddr3_addr;\n wire [2:0]ddr3_ba;\n wire ddr3_cas_n;\n wire [0:0]ddr3_cke;\n wire [0:0]ddr3_cs_n;\n wire [3:0]ddr3_dm;\n wire [31:0]ddr3_dq;\n wire [3:0]ddr3_dqs_n;\n wire [3:0]ddr3_dqs_p;\n wire [0:0]ddr3_odt;\n wire ddr3_ras_n;\n wire ddr3_reset_n;\n wire ddr3_we_n;\n wire [1:0]ddr_ck_out;\n wire [11:0]\\device_temp_r_reg[11] ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;\n wire \\en_cnt_div4.enable_wrlvl_cnt_reg[3] ;\n wire fine_adjust_reg;\n wire freq_refclk;\n wire \\generate_maint_cmds.insert_maint_r_lcl_reg ;\n wire hi_priority;\n wire in0;\n wire init_calib_complete_r;\n wire insert_maint_r;\n wire [1:0]\\mc0/bank_mach0/idle_ns ;\n wire \\mc0/bank_mach0/p_28_out ;\n wire \\mc0/bank_mach0/p_67_out ;\n wire [20:18]\\mc0/p_2_in ;\n wire [2:0]\\mc0/req_bank_r_lcl ;\n wire mem_intfc0_n_129;\n wire mem_intfc0_n_130;\n wire mem_intfc0_n_131;\n wire mem_intfc0_n_132;\n wire mem_intfc0_n_133;\n wire mem_intfc0_n_134;\n wire mem_intfc0_n_135;\n wire mem_intfc0_n_136;\n wire mem_intfc0_n_137;\n wire mem_intfc0_n_138;\n wire mem_intfc0_n_139;\n wire mem_intfc0_n_140;\n wire mem_intfc0_n_141;\n wire mem_intfc0_n_142;\n wire mem_intfc0_n_143;\n wire mem_intfc0_n_144;\n wire mem_intfc0_n_145;\n wire mem_intfc0_n_146;\n wire mem_intfc0_n_147;\n wire mem_intfc0_n_148;\n wire mem_intfc0_n_149;\n wire mem_intfc0_n_150;\n wire mem_intfc0_n_151;\n wire mem_intfc0_n_152;\n wire mem_intfc0_n_153;\n wire mem_intfc0_n_154;\n wire mem_intfc0_n_155;\n wire mem_intfc0_n_156;\n wire mem_intfc0_n_157;\n wire mem_intfc0_n_158;\n wire mem_intfc0_n_159;\n wire mem_intfc0_n_160;\n wire mem_intfc0_n_161;\n wire mem_intfc0_n_162;\n wire mem_intfc0_n_163;\n wire mem_intfc0_n_164;\n wire mem_intfc0_n_165;\n wire mem_intfc0_n_166;\n wire mem_intfc0_n_167;\n wire mem_intfc0_n_168;\n wire mem_intfc0_n_169;\n wire mem_intfc0_n_170;\n wire mem_intfc0_n_171;\n wire mem_intfc0_n_172;\n wire mem_intfc0_n_173;\n wire mem_intfc0_n_174;\n wire mem_intfc0_n_175;\n wire mem_intfc0_n_176;\n wire mem_intfc0_n_177;\n wire mem_intfc0_n_178;\n wire mem_intfc0_n_179;\n wire mem_intfc0_n_180;\n wire mem_intfc0_n_181;\n wire mem_intfc0_n_182;\n wire mem_intfc0_n_183;\n wire mem_intfc0_n_184;\n wire mem_intfc0_n_185;\n wire mem_intfc0_n_186;\n wire mem_intfc0_n_187;\n wire mem_intfc0_n_188;\n wire mem_intfc0_n_189;\n wire mem_intfc0_n_190;\n wire mem_intfc0_n_191;\n wire mem_intfc0_n_192;\n wire mem_intfc0_n_193;\n wire mem_intfc0_n_194;\n wire mem_intfc0_n_195;\n wire mem_intfc0_n_196;\n wire mem_intfc0_n_197;\n wire mem_intfc0_n_198;\n wire mem_intfc0_n_199;\n wire mem_intfc0_n_200;\n wire mem_intfc0_n_201;\n wire mem_intfc0_n_202;\n wire mem_intfc0_n_203;\n wire mem_intfc0_n_204;\n wire mem_intfc0_n_205;\n wire mem_intfc0_n_206;\n wire mem_intfc0_n_207;\n wire mem_intfc0_n_208;\n wire mem_intfc0_n_209;\n wire mem_intfc0_n_210;\n wire mem_intfc0_n_211;\n wire mem_intfc0_n_212;\n wire mem_intfc0_n_213;\n wire mem_intfc0_n_214;\n wire mem_intfc0_n_215;\n wire mem_intfc0_n_216;\n wire mem_intfc0_n_217;\n wire mem_intfc0_n_218;\n wire mem_intfc0_n_219;\n wire mem_intfc0_n_220;\n wire mem_intfc0_n_221;\n wire mem_intfc0_n_222;\n wire mem_intfc0_n_223;\n wire mem_intfc0_n_224;\n wire mem_intfc0_n_225;\n wire mem_intfc0_n_226;\n wire mem_intfc0_n_227;\n wire mem_intfc0_n_228;\n wire mem_intfc0_n_229;\n wire mem_intfc0_n_230;\n wire mem_intfc0_n_231;\n wire mem_intfc0_n_232;\n wire mem_intfc0_n_233;\n wire mem_intfc0_n_234;\n wire mem_intfc0_n_235;\n wire mem_intfc0_n_236;\n wire mem_intfc0_n_237;\n wire mem_intfc0_n_238;\n wire mem_intfc0_n_239;\n wire mem_intfc0_n_240;\n wire mem_intfc0_n_241;\n wire mem_intfc0_n_242;\n wire mem_intfc0_n_243;\n wire mem_intfc0_n_244;\n wire mem_intfc0_n_245;\n wire mem_intfc0_n_246;\n wire mem_intfc0_n_247;\n wire mem_intfc0_n_248;\n wire mem_intfc0_n_249;\n wire mem_intfc0_n_250;\n wire mem_intfc0_n_251;\n wire mem_intfc0_n_252;\n wire mem_intfc0_n_253;\n wire mem_intfc0_n_254;\n wire mem_intfc0_n_255;\n wire mem_intfc0_n_256;\n wire mem_intfc0_n_257;\n wire mem_intfc0_n_258;\n wire mem_intfc0_n_259;\n wire mem_intfc0_n_260;\n wire mem_intfc0_n_261;\n wire mem_intfc0_n_262;\n wire mem_intfc0_n_263;\n wire mem_intfc0_n_264;\n wire mem_intfc0_n_265;\n wire mem_intfc0_n_266;\n wire mem_intfc0_n_267;\n wire mem_intfc0_n_268;\n wire mem_intfc0_n_269;\n wire mem_intfc0_n_270;\n wire mem_intfc0_n_271;\n wire mem_intfc0_n_272;\n wire mem_intfc0_n_273;\n wire mem_intfc0_n_274;\n wire mem_intfc0_n_275;\n wire mem_intfc0_n_276;\n wire mem_intfc0_n_277;\n wire mem_intfc0_n_278;\n wire mem_intfc0_n_279;\n wire mem_intfc0_n_280;\n wire mem_intfc0_n_281;\n wire mem_intfc0_n_282;\n wire mem_intfc0_n_283;\n wire mem_intfc0_n_284;\n wire mem_intfc0_n_285;\n wire mem_intfc0_n_286;\n wire mem_intfc0_n_287;\n wire mem_intfc0_n_288;\n wire mem_intfc0_n_289;\n wire mem_intfc0_n_290;\n wire mem_intfc0_n_291;\n wire mem_intfc0_n_292;\n wire mem_intfc0_n_293;\n wire mem_intfc0_n_294;\n wire mem_intfc0_n_295;\n wire mem_intfc0_n_296;\n wire mem_intfc0_n_297;\n wire mem_intfc0_n_298;\n wire mem_intfc0_n_299;\n wire mem_intfc0_n_300;\n wire mem_intfc0_n_301;\n wire mem_intfc0_n_302;\n wire mem_intfc0_n_303;\n wire mem_intfc0_n_304;\n wire mem_intfc0_n_305;\n wire mem_intfc0_n_306;\n wire mem_intfc0_n_307;\n wire mem_intfc0_n_308;\n wire mem_intfc0_n_309;\n wire mem_intfc0_n_310;\n wire mem_intfc0_n_311;\n wire mem_intfc0_n_312;\n wire mem_intfc0_n_313;\n wire mem_intfc0_n_314;\n wire mem_intfc0_n_315;\n wire mem_intfc0_n_316;\n wire mem_intfc0_n_317;\n wire mem_intfc0_n_318;\n wire mem_intfc0_n_319;\n wire mem_intfc0_n_320;\n wire mem_intfc0_n_321;\n wire mem_intfc0_n_322;\n wire mem_intfc0_n_323;\n wire mem_intfc0_n_324;\n wire mem_intfc0_n_325;\n wire mem_intfc0_n_326;\n wire mem_intfc0_n_327;\n wire mem_intfc0_n_328;\n wire mem_intfc0_n_329;\n wire mem_intfc0_n_330;\n wire mem_intfc0_n_331;\n wire mem_intfc0_n_332;\n wire mem_intfc0_n_333;\n wire mem_intfc0_n_334;\n wire mem_intfc0_n_335;\n wire mem_intfc0_n_336;\n wire mem_intfc0_n_337;\n wire mem_intfc0_n_338;\n wire mem_intfc0_n_339;\n wire mem_intfc0_n_340;\n wire mem_intfc0_n_341;\n wire mem_intfc0_n_342;\n wire mem_intfc0_n_343;\n wire mem_intfc0_n_344;\n wire mem_intfc0_n_345;\n wire mem_intfc0_n_346;\n wire mem_intfc0_n_347;\n wire mem_intfc0_n_348;\n wire mem_intfc0_n_349;\n wire mem_intfc0_n_350;\n wire mem_intfc0_n_351;\n wire mem_intfc0_n_352;\n wire mem_intfc0_n_353;\n wire mem_intfc0_n_354;\n wire mem_intfc0_n_355;\n wire mem_intfc0_n_356;\n wire mem_intfc0_n_357;\n wire mem_intfc0_n_358;\n wire mem_intfc0_n_359;\n wire mem_intfc0_n_360;\n wire mem_intfc0_n_361;\n wire mem_intfc0_n_362;\n wire mem_intfc0_n_363;\n wire mem_intfc0_n_364;\n wire mem_intfc0_n_365;\n wire mem_intfc0_n_366;\n wire mem_intfc0_n_367;\n wire mem_intfc0_n_368;\n wire mem_intfc0_n_369;\n wire mem_intfc0_n_370;\n wire mem_intfc0_n_371;\n wire mem_intfc0_n_372;\n wire mem_intfc0_n_373;\n wire mem_intfc0_n_374;\n wire mem_intfc0_n_375;\n wire mem_intfc0_n_376;\n wire mem_intfc0_n_377;\n wire mem_intfc0_n_378;\n wire mem_intfc0_n_379;\n wire mem_intfc0_n_380;\n wire mem_intfc0_n_381;\n wire mem_intfc0_n_382;\n wire mem_intfc0_n_383;\n wire mem_intfc0_n_384;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire mem_intfc0_n_64;\n wire [17:0]mem_out;\n wire mem_refclk;\n wire \\mmcm_current_reg[0] ;\n wire \\mmcm_init_trail_reg[0] ;\n wire mmcm_locked;\n wire mmcm_ps_clk;\n wire [256:0]out;\n wire p_81_in;\n wire pass_open_bank_r;\n wire pass_open_bank_r_1;\n wire pass_open_bank_r_lcl_reg;\n wire [5:0]phy_dout;\n wire phy_mc_go;\n wire pi_cnt_dec;\n wire [0:0]pi_cnt_dec_reg;\n wire \\pi_rst_stg1_cal_r_reg[0] ;\n wire pll_locked;\n wire po_cnt_dec;\n wire [0:0]po_cnt_dec_reg;\n wire poc_sample_pd;\n wire psdone;\n wire [3:0]ram_init_addr;\n wire ram_init_done_r;\n wire [4:0]rd_data_addr;\n wire rd_data_end;\n wire rd_data_offset;\n wire [71:0]\\rd_ptr_reg[3] ;\n wire [29:0]\\rd_ptr_reg[3]_0 ;\n wire [37:0]\\rd_ptr_timing_reg[0] ;\n wire [4:0]\\rd_ptr_timing_reg[0]_0 ;\n wire \\rd_ptr_timing_reg[2] ;\n wire \\rd_ptr_timing_reg[2]_0 ;\n wire \\rd_ptr_timing_reg[2]_1 ;\n wire \\rd_ptr_timing_reg[2]_10 ;\n wire \\rd_ptr_timing_reg[2]_2 ;\n wire \\rd_ptr_timing_reg[2]_3 ;\n wire \\rd_ptr_timing_reg[2]_4 ;\n wire \\rd_ptr_timing_reg[2]_5 ;\n wire \\rd_ptr_timing_reg[2]_6 ;\n wire \\rd_ptr_timing_reg[2]_7 ;\n wire \\rd_ptr_timing_reg[2]_8 ;\n wire \\rd_ptr_timing_reg[2]_9 ;\n wire reset_reg_n_0;\n wire \\resume_wait_r_reg[5] ;\n wire [14:0]row;\n wire \\row_cnt_victim_rotate.complex_row_cnt_reg[4] ;\n wire [0:0]\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ;\n wire rst_sync_r1;\n wire rst_sync_r1_reg;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__10;\n wire rstdiv0_sync_r1_reg_rep__11;\n wire [0:0]rstdiv0_sync_r1_reg_rep__12;\n wire rstdiv0_sync_r1_reg_rep__13;\n wire [1:0]rstdiv0_sync_r1_reg_rep__14;\n wire [0:0]rstdiv0_sync_r1_reg_rep__16;\n wire [1:0]rstdiv0_sync_r1_reg_rep__17;\n wire [0:0]rstdiv0_sync_r1_reg_rep__19;\n wire rstdiv0_sync_r1_reg_rep__2;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire rstdiv0_sync_r1_reg_rep__22;\n wire rstdiv0_sync_r1_reg_rep__23;\n wire rstdiv0_sync_r1_reg_rep__23_0;\n wire rstdiv0_sync_r1_reg_rep__23_1;\n wire rstdiv0_sync_r1_reg_rep__24;\n wire rstdiv0_sync_r1_reg_rep__25;\n wire rstdiv0_sync_r1_reg_rep__25_0;\n wire rstdiv0_sync_r1_reg_rep__25_1;\n wire rstdiv0_sync_r1_reg_rep__25_2;\n wire [0:0]rstdiv0_sync_r1_reg_rep__4;\n wire rstdiv0_sync_r1_reg_rep__5;\n wire rstdiv0_sync_r1_reg_rep__6;\n wire [0:0]rstdiv0_sync_r1_reg_rep__7;\n wire rstdiv0_sync_r1_reg_rep__8;\n wire rstdiv0_sync_r1_reg_rep__9;\n wire rtp_timer_ns1;\n wire [29:0]s_axi_araddr;\n wire [0:0]s_axi_arburst;\n wire [0:0]s_axi_arid;\n wire [7:0]s_axi_arlen;\n wire s_axi_arready;\n wire s_axi_arvalid;\n wire [29:0]s_axi_awaddr;\n wire [0:0]s_axi_awburst;\n wire [0:0]s_axi_awid;\n wire [7:0]s_axi_awlen;\n wire s_axi_awready;\n wire s_axi_awvalid;\n wire [0:0]s_axi_bid;\n wire s_axi_bready;\n wire s_axi_bvalid;\n wire [0:0]s_axi_rid;\n wire s_axi_rlast;\n wire s_axi_rready;\n wire s_axi_rvalid;\n wire [255:0]s_axi_wdata;\n wire s_axi_wready;\n wire [31:0]s_axi_wstrb;\n wire s_axi_wvalid;\n wire samp_edge_cnt0_en_r;\n wire samp_edge_cnt0_en_r_reg;\n wire sm_r;\n wire \\sm_r_reg[0] ;\n wire [0:0]\\sm_r_reg[0]_0 ;\n wire \\stg2_tap_cnt_reg[0] ;\n wire stg3_dec2init_val_r_reg;\n wire stg3_inc2init_val_r_reg;\n wire \\stg3_r_reg[0] ;\n wire sync_pulse;\n wire sys_rst;\n wire u_ui_top_n_1;\n wire u_ui_top_n_260;\n wire u_ui_top_n_261;\n wire u_ui_top_n_272;\n wire u_ui_top_n_274;\n wire \\ui_cmd0/app_addr_r10 ;\n wire \\ui_cmd0/app_en_ns1 ;\n wire \\ui_cmd0/app_en_r1 ;\n wire \\ui_cmd0/app_hi_pri_r2 ;\n wire \\ui_rd_data0/app_rd_data_end_ns ;\n wire \\ui_rd_data0/bypass__0 ;\n wire [1:0]\\ui_rd_data0/p_100_out ;\n wire [1:0]\\ui_rd_data0/p_101_out ;\n wire [1:0]\\ui_rd_data0/p_102_out ;\n wire [1:0]\\ui_rd_data0/p_103_out ;\n wire [1:0]\\ui_rd_data0/p_104_out ;\n wire [1:0]\\ui_rd_data0/p_105_out ;\n wire [1:0]\\ui_rd_data0/p_106_out ;\n wire [1:0]\\ui_rd_data0/p_107_out ;\n wire [1:0]\\ui_rd_data0/p_108_out ;\n wire [1:0]\\ui_rd_data0/p_109_out ;\n wire [1:0]\\ui_rd_data0/p_10_out ;\n wire [1:0]\\ui_rd_data0/p_110_out ;\n wire [1:0]\\ui_rd_data0/p_111_out ;\n wire [1:0]\\ui_rd_data0/p_112_out ;\n wire [1:0]\\ui_rd_data0/p_113_out ;\n wire [1:0]\\ui_rd_data0/p_114_out ;\n wire [1:0]\\ui_rd_data0/p_115_out ;\n wire [1:0]\\ui_rd_data0/p_116_out ;\n wire [1:0]\\ui_rd_data0/p_117_out ;\n wire [1:0]\\ui_rd_data0/p_118_out ;\n wire [1:0]\\ui_rd_data0/p_119_out ;\n wire [1:0]\\ui_rd_data0/p_11_out ;\n wire [1:0]\\ui_rd_data0/p_120_out ;\n wire [1:0]\\ui_rd_data0/p_121_out ;\n wire [1:0]\\ui_rd_data0/p_122_out ;\n wire [1:0]\\ui_rd_data0/p_123_out ;\n wire [1:0]\\ui_rd_data0/p_124_out ;\n wire [1:0]\\ui_rd_data0/p_125_out ;\n wire [1:0]\\ui_rd_data0/p_127_out ;\n wire [1:0]\\ui_rd_data0/p_128_out ;\n wire [1:0]\\ui_rd_data0/p_129_out ;\n wire [1:0]\\ui_rd_data0/p_12_out ;\n wire [1:0]\\ui_rd_data0/p_13_out ;\n wire [1:0]\\ui_rd_data0/p_14_out ;\n wire [1:0]\\ui_rd_data0/p_15_out ;\n wire [1:0]\\ui_rd_data0/p_16_out ;\n wire [1:0]\\ui_rd_data0/p_17_out ;\n wire [1:0]\\ui_rd_data0/p_18_out ;\n wire [1:0]\\ui_rd_data0/p_19_out ;\n wire [1:0]\\ui_rd_data0/p_1_out ;\n wire [1:0]\\ui_rd_data0/p_20_out ;\n wire [1:0]\\ui_rd_data0/p_21_out ;\n wire [1:0]\\ui_rd_data0/p_22_out ;\n wire [1:0]\\ui_rd_data0/p_23_out ;\n wire [1:0]\\ui_rd_data0/p_24_out ;\n wire [1:0]\\ui_rd_data0/p_25_out ;\n wire [1:0]\\ui_rd_data0/p_26_out ;\n wire [1:0]\\ui_rd_data0/p_27_out ;\n wire [1:0]\\ui_rd_data0/p_28_out ;\n wire [1:0]\\ui_rd_data0/p_29_out ;\n wire [1:0]\\ui_rd_data0/p_30_out ;\n wire [1:0]\\ui_rd_data0/p_31_out ;\n wire [1:0]\\ui_rd_data0/p_32_out ;\n wire [1:0]\\ui_rd_data0/p_33_out ;\n wire [1:0]\\ui_rd_data0/p_34_out ;\n wire [1:0]\\ui_rd_data0/p_35_out ;\n wire [1:0]\\ui_rd_data0/p_36_out ;\n wire [1:0]\\ui_rd_data0/p_37_out ;\n wire [1:0]\\ui_rd_data0/p_38_out ;\n wire [1:0]\\ui_rd_data0/p_39_out ;\n wire [1:0]\\ui_rd_data0/p_3_out ;\n wire [1:0]\\ui_rd_data0/p_40_out ;\n wire [1:0]\\ui_rd_data0/p_41_out ;\n wire [1:0]\\ui_rd_data0/p_42_out ;\n wire [1:0]\\ui_rd_data0/p_43_out ;\n wire [1:0]\\ui_rd_data0/p_44_out ;\n wire [1:0]\\ui_rd_data0/p_45_out ;\n wire [1:0]\\ui_rd_data0/p_46_out ;\n wire [1:0]\\ui_rd_data0/p_47_out ;\n wire [1:0]\\ui_rd_data0/p_48_out ;\n wire [1:0]\\ui_rd_data0/p_49_out ;\n wire [1:0]\\ui_rd_data0/p_4_out ;\n wire [1:0]\\ui_rd_data0/p_50_out ;\n wire [1:0]\\ui_rd_data0/p_51_out ;\n wire [1:0]\\ui_rd_data0/p_52_out ;\n wire [1:0]\\ui_rd_data0/p_53_out ;\n wire [1:0]\\ui_rd_data0/p_54_out ;\n wire [1:0]\\ui_rd_data0/p_55_out ;\n wire [1:0]\\ui_rd_data0/p_56_out ;\n wire [1:0]\\ui_rd_data0/p_57_out ;\n wire [1:0]\\ui_rd_data0/p_58_out ;\n wire [1:0]\\ui_rd_data0/p_59_out ;\n wire [1:0]\\ui_rd_data0/p_5_out ;\n wire [1:0]\\ui_rd_data0/p_60_out ;\n wire [1:0]\\ui_rd_data0/p_61_out ;\n wire [1:0]\\ui_rd_data0/p_62_out ;\n wire [1:0]\\ui_rd_data0/p_63_out ;\n wire [1:0]\\ui_rd_data0/p_64_out ;\n wire [1:0]\\ui_rd_data0/p_65_out ;\n wire [1:0]\\ui_rd_data0/p_66_out ;\n wire [1:0]\\ui_rd_data0/p_67_out ;\n wire [1:0]\\ui_rd_data0/p_68_out ;\n wire [1:0]\\ui_rd_data0/p_69_out ;\n wire [1:0]\\ui_rd_data0/p_6_out ;\n wire [1:0]\\ui_rd_data0/p_70_out ;\n wire [1:0]\\ui_rd_data0/p_71_out ;\n wire [1:0]\\ui_rd_data0/p_72_out ;\n wire [1:0]\\ui_rd_data0/p_73_out ;\n wire [1:0]\\ui_rd_data0/p_74_out ;\n wire [1:0]\\ui_rd_data0/p_75_out ;\n wire [1:0]\\ui_rd_data0/p_76_out ;\n wire [1:0]\\ui_rd_data0/p_77_out ;\n wire [1:0]\\ui_rd_data0/p_78_out ;\n wire [1:0]\\ui_rd_data0/p_79_out ;\n wire [1:0]\\ui_rd_data0/p_7_out ;\n wire [1:0]\\ui_rd_data0/p_80_out ;\n wire [1:0]\\ui_rd_data0/p_81_out ;\n wire [1:0]\\ui_rd_data0/p_82_out ;\n wire [1:0]\\ui_rd_data0/p_83_out ;\n wire [1:0]\\ui_rd_data0/p_84_out ;\n wire [1:0]\\ui_rd_data0/p_85_out ;\n wire [1:0]\\ui_rd_data0/p_86_out ;\n wire [1:0]\\ui_rd_data0/p_87_out ;\n wire [1:0]\\ui_rd_data0/p_88_out ;\n wire [1:0]\\ui_rd_data0/p_89_out ;\n wire [1:0]\\ui_rd_data0/p_8_out ;\n wire [1:0]\\ui_rd_data0/p_90_out ;\n wire [1:0]\\ui_rd_data0/p_91_out ;\n wire [1:0]\\ui_rd_data0/p_92_out ;\n wire [1:0]\\ui_rd_data0/p_93_out ;\n wire [1:0]\\ui_rd_data0/p_94_out ;\n wire [1:0]\\ui_rd_data0/p_95_out ;\n wire [1:0]\\ui_rd_data0/p_96_out ;\n wire [1:0]\\ui_rd_data0/p_97_out ;\n wire [1:0]\\ui_rd_data0/p_98_out ;\n wire [1:0]\\ui_rd_data0/p_99_out ;\n wire [1:0]\\ui_rd_data0/p_9_out ;\n wire \\ui_rd_data0/rd_buf_we ;\n wire [1:1]\\ui_rd_data0/rd_status ;\n wire \\ui_wr_data0/pointer_we ;\n wire use_addr;\n wire w_cmd_rdy;\n wire [255:0]wr_data;\n wire [3:0]wr_data_addr;\n wire wr_data_en;\n wire [31:0]wr_data_mask;\n wire wr_en;\n wire wr_en_5;\n wire wr_en_6;\n wire [3:0]\\wr_ptr_timing_reg[2] ;\n wire [3:0]\\wr_ptr_timing_reg[2]_0 ;\n\n FDRE #(\n .INIT(1'b0)) \n init_calib_complete_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mem_intfc0_n_64),\n .Q(init_calib_complete_r),\n .R(1'b0));\n ddr3_ifmig_7series_v4_0_mem_intfc mem_intfc0\n (.CLK(CLK),\n .CLKB0(CLKB0),\n .CLKB0_7(CLKB0_7),\n .CLKB0_8(CLKB0_8),\n .CLKB0_9(CLKB0_9),\n .D(D),\n .DOA(\\ui_rd_data0/p_129_out ),\n .DOB(\\ui_rd_data0/p_128_out ),\n .DOC(\\ui_rd_data0/p_127_out ),\n .E(wr_data_en),\n .Q({wr_data_mask,wr_data}),\n .RST0(RST0),\n .SR(SR),\n .SS(SS),\n .accept_ns(accept_ns),\n .\\app_addr_r1_reg[12] (bank),\n .\\app_addr_r1_reg[27] (row),\n .\\app_addr_r1_reg[9] (col),\n .app_hi_pri_r2(\\ui_cmd0/app_hi_pri_r2 ),\n .app_rd_data_end_ns(\\ui_rd_data0/app_rd_data_end_ns ),\n .app_ref_ack(app_ref_ack),\n .app_ref_req(app_ref_req),\n .app_sr_active(app_sr_active),\n .app_sr_req(app_sr_req),\n .app_zq_ack(app_zq_ack),\n .app_zq_req(app_zq_req),\n .bm_end_r1(bm_end_r1),\n .bm_end_r1_0(bm_end_r1_0),\n .bm_end_r1_reg(pass_open_bank_r),\n .bm_end_r1_reg_0(pass_open_bank_r_1),\n .bm_end_r1_reg_1(bm_end_r1_reg),\n .bm_end_r1_reg_2(bm_end_r1_reg_0),\n .bypass__0(\\ui_rd_data0/bypass__0 ),\n .\\calib_seq_reg[0] (phy_mc_go),\n .cmd(cmd),\n .\\cmd_pipe_plus.mc_bank_reg[2] (\\mc0/req_bank_r_lcl ),\n .\\cmd_pipe_plus.mc_bank_reg[2]_0 (\\mc0/p_2_in ),\n .cnt_pwron_reset_done_r0(cnt_pwron_reset_done_r0),\n .\\complex_row_cnt_ocal_reg[0] (\\complex_row_cnt_ocal_reg[0] ),\n .ddr3_addr(ddr3_addr),\n .ddr3_ba(ddr3_ba),\n .ddr3_cas_n(ddr3_cas_n),\n .ddr3_cke(ddr3_cke),\n .ddr3_cs_n(ddr3_cs_n),\n .ddr3_dm(ddr3_dm),\n .ddr3_dq(ddr3_dq),\n .ddr3_dqs_n(ddr3_dqs_n),\n .ddr3_dqs_p(ddr3_dqs_p),\n .ddr3_odt(ddr3_odt),\n .ddr3_ras_n(ddr3_ras_n),\n .ddr3_reset_n(ddr3_reset_n),\n .ddr3_we_n(ddr3_we_n),\n .ddr_ck_out(ddr_ck_out),\n .\\device_temp_r_reg[11] (\\device_temp_r_reg[11] ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ),\n .dqs_po_en_stg2_f_reg(po_cnt_dec),\n .\\en_cnt_div4.enable_wrlvl_cnt_reg[3] (\\en_cnt_div4.enable_wrlvl_cnt_reg[3] ),\n .fine_adjust_reg(fine_adjust_reg),\n .freq_refclk(freq_refclk),\n .\\generate_maint_cmds.insert_maint_r_lcl_reg (\\generate_maint_cmds.insert_maint_r_lcl_reg ),\n .hi_priority(hi_priority),\n .idle_ns(\\mc0/bank_mach0/idle_ns ),\n .in0(in0),\n .init_calib_complete_r_reg(mem_intfc0_n_64),\n .insert_maint_r1_lcl_reg(insert_maint_r),\n .mem_out(mem_out),\n .mem_refclk(mem_refclk),\n .\\mmcm_current_reg[0] (\\mmcm_current_reg[0] ),\n .\\mmcm_init_trail_reg[0] (\\mmcm_init_trail_reg[0] ),\n .mmcm_locked(mmcm_locked),\n .mmcm_ps_clk(mmcm_ps_clk),\n .\\not_strict_mode.app_rd_data_end_reg ({rd_data_end,rd_data_addr,rd_data_offset}),\n .\\not_strict_mode.app_rd_data_reg[0] (mem_intfc0_n_384),\n .\\not_strict_mode.app_rd_data_reg[100] (mem_intfc0_n_272),\n .\\not_strict_mode.app_rd_data_reg[101] (mem_intfc0_n_268),\n .\\not_strict_mode.app_rd_data_reg[102] (mem_intfc0_n_264),\n .\\not_strict_mode.app_rd_data_reg[103] (mem_intfc0_n_260),\n .\\not_strict_mode.app_rd_data_reg[104] (mem_intfc0_n_286),\n .\\not_strict_mode.app_rd_data_reg[105] (mem_intfc0_n_282),\n .\\not_strict_mode.app_rd_data_reg[106] (mem_intfc0_n_278),\n .\\not_strict_mode.app_rd_data_reg[107] (mem_intfc0_n_274),\n .\\not_strict_mode.app_rd_data_reg[108] (mem_intfc0_n_270),\n .\\not_strict_mode.app_rd_data_reg[109] (mem_intfc0_n_266),\n .\\not_strict_mode.app_rd_data_reg[10] (mem_intfc0_n_374),\n .\\not_strict_mode.app_rd_data_reg[110] (mem_intfc0_n_262),\n .\\not_strict_mode.app_rd_data_reg[111] (mem_intfc0_n_258),\n .\\not_strict_mode.app_rd_data_reg[112] (mem_intfc0_n_287),\n .\\not_strict_mode.app_rd_data_reg[113] (mem_intfc0_n_283),\n .\\not_strict_mode.app_rd_data_reg[114] (mem_intfc0_n_279),\n .\\not_strict_mode.app_rd_data_reg[115] (mem_intfc0_n_275),\n .\\not_strict_mode.app_rd_data_reg[116] (mem_intfc0_n_271),\n .\\not_strict_mode.app_rd_data_reg[117] (mem_intfc0_n_267),\n .\\not_strict_mode.app_rd_data_reg[118] (mem_intfc0_n_263),\n .\\not_strict_mode.app_rd_data_reg[119] (mem_intfc0_n_259),\n .\\not_strict_mode.app_rd_data_reg[11] (mem_intfc0_n_370),\n .\\not_strict_mode.app_rd_data_reg[120] (mem_intfc0_n_285),\n .\\not_strict_mode.app_rd_data_reg[121] (mem_intfc0_n_281),\n .\\not_strict_mode.app_rd_data_reg[122] (mem_intfc0_n_277),\n .\\not_strict_mode.app_rd_data_reg[123] (mem_intfc0_n_273),\n .\\not_strict_mode.app_rd_data_reg[124] (mem_intfc0_n_269),\n .\\not_strict_mode.app_rd_data_reg[125] (mem_intfc0_n_265),\n .\\not_strict_mode.app_rd_data_reg[126] (mem_intfc0_n_261),\n .\\not_strict_mode.app_rd_data_reg[127] (mem_intfc0_n_257),\n .\\not_strict_mode.app_rd_data_reg[128] (mem_intfc0_n_256),\n .\\not_strict_mode.app_rd_data_reg[129] (mem_intfc0_n_252),\n .\\not_strict_mode.app_rd_data_reg[12] (mem_intfc0_n_366),\n .\\not_strict_mode.app_rd_data_reg[130] (mem_intfc0_n_248),\n .\\not_strict_mode.app_rd_data_reg[131] (mem_intfc0_n_244),\n .\\not_strict_mode.app_rd_data_reg[132] (mem_intfc0_n_240),\n .\\not_strict_mode.app_rd_data_reg[133] (mem_intfc0_n_236),\n .\\not_strict_mode.app_rd_data_reg[134] (mem_intfc0_n_232),\n .\\not_strict_mode.app_rd_data_reg[135] (mem_intfc0_n_228),\n .\\not_strict_mode.app_rd_data_reg[136] (mem_intfc0_n_254),\n .\\not_strict_mode.app_rd_data_reg[137] (mem_intfc0_n_250),\n .\\not_strict_mode.app_rd_data_reg[138] (mem_intfc0_n_246),\n .\\not_strict_mode.app_rd_data_reg[139] (mem_intfc0_n_242),\n .\\not_strict_mode.app_rd_data_reg[13] (mem_intfc0_n_362),\n .\\not_strict_mode.app_rd_data_reg[140] (mem_intfc0_n_238),\n .\\not_strict_mode.app_rd_data_reg[141] (mem_intfc0_n_234),\n .\\not_strict_mode.app_rd_data_reg[142] (mem_intfc0_n_230),\n .\\not_strict_mode.app_rd_data_reg[143] (mem_intfc0_n_226),\n .\\not_strict_mode.app_rd_data_reg[144] (mem_intfc0_n_255),\n .\\not_strict_mode.app_rd_data_reg[145] (mem_intfc0_n_251),\n .\\not_strict_mode.app_rd_data_reg[146] (mem_intfc0_n_247),\n .\\not_strict_mode.app_rd_data_reg[147] (mem_intfc0_n_243),\n .\\not_strict_mode.app_rd_data_reg[148] (mem_intfc0_n_239),\n .\\not_strict_mode.app_rd_data_reg[149] (mem_intfc0_n_235),\n .\\not_strict_mode.app_rd_data_reg[14] (mem_intfc0_n_358),\n .\\not_strict_mode.app_rd_data_reg[150] (mem_intfc0_n_231),\n .\\not_strict_mode.app_rd_data_reg[151] (mem_intfc0_n_227),\n .\\not_strict_mode.app_rd_data_reg[152] (mem_intfc0_n_253),\n .\\not_strict_mode.app_rd_data_reg[153] (mem_intfc0_n_249),\n .\\not_strict_mode.app_rd_data_reg[154] (mem_intfc0_n_245),\n .\\not_strict_mode.app_rd_data_reg[155] (mem_intfc0_n_241),\n .\\not_strict_mode.app_rd_data_reg[156] (mem_intfc0_n_237),\n .\\not_strict_mode.app_rd_data_reg[157] (mem_intfc0_n_233),\n .\\not_strict_mode.app_rd_data_reg[158] (mem_intfc0_n_229),\n .\\not_strict_mode.app_rd_data_reg[159] (mem_intfc0_n_225),\n .\\not_strict_mode.app_rd_data_reg[15] (mem_intfc0_n_354),\n .\\not_strict_mode.app_rd_data_reg[160] (mem_intfc0_n_224),\n .\\not_strict_mode.app_rd_data_reg[161] (mem_intfc0_n_220),\n .\\not_strict_mode.app_rd_data_reg[162] (mem_intfc0_n_216),\n .\\not_strict_mode.app_rd_data_reg[163] (mem_intfc0_n_212),\n .\\not_strict_mode.app_rd_data_reg[164] (mem_intfc0_n_208),\n .\\not_strict_mode.app_rd_data_reg[165] (mem_intfc0_n_204),\n .\\not_strict_mode.app_rd_data_reg[166] (mem_intfc0_n_200),\n .\\not_strict_mode.app_rd_data_reg[167] (mem_intfc0_n_196),\n .\\not_strict_mode.app_rd_data_reg[168] (mem_intfc0_n_222),\n .\\not_strict_mode.app_rd_data_reg[169] (mem_intfc0_n_218),\n .\\not_strict_mode.app_rd_data_reg[16] (mem_intfc0_n_383),\n .\\not_strict_mode.app_rd_data_reg[170] (mem_intfc0_n_214),\n .\\not_strict_mode.app_rd_data_reg[171] (mem_intfc0_n_210),\n .\\not_strict_mode.app_rd_data_reg[172] (mem_intfc0_n_206),\n .\\not_strict_mode.app_rd_data_reg[173] (mem_intfc0_n_202),\n .\\not_strict_mode.app_rd_data_reg[174] (mem_intfc0_n_198),\n .\\not_strict_mode.app_rd_data_reg[175] (mem_intfc0_n_194),\n .\\not_strict_mode.app_rd_data_reg[176] (mem_intfc0_n_223),\n .\\not_strict_mode.app_rd_data_reg[177] (mem_intfc0_n_219),\n .\\not_strict_mode.app_rd_data_reg[178] (mem_intfc0_n_215),\n .\\not_strict_mode.app_rd_data_reg[179] (mem_intfc0_n_211),\n .\\not_strict_mode.app_rd_data_reg[17] (mem_intfc0_n_379),\n .\\not_strict_mode.app_rd_data_reg[180] (mem_intfc0_n_207),\n .\\not_strict_mode.app_rd_data_reg[181] (mem_intfc0_n_203),\n .\\not_strict_mode.app_rd_data_reg[182] (mem_intfc0_n_199),\n .\\not_strict_mode.app_rd_data_reg[183] (mem_intfc0_n_195),\n .\\not_strict_mode.app_rd_data_reg[184] (mem_intfc0_n_221),\n .\\not_strict_mode.app_rd_data_reg[185] (mem_intfc0_n_217),\n .\\not_strict_mode.app_rd_data_reg[186] (mem_intfc0_n_213),\n .\\not_strict_mode.app_rd_data_reg[187] (mem_intfc0_n_209),\n .\\not_strict_mode.app_rd_data_reg[188] (mem_intfc0_n_205),\n .\\not_strict_mode.app_rd_data_reg[189] (mem_intfc0_n_201),\n .\\not_strict_mode.app_rd_data_reg[18] (mem_intfc0_n_375),\n .\\not_strict_mode.app_rd_data_reg[190] (mem_intfc0_n_197),\n .\\not_strict_mode.app_rd_data_reg[191] (mem_intfc0_n_193),\n .\\not_strict_mode.app_rd_data_reg[192] (mem_intfc0_n_192),\n .\\not_strict_mode.app_rd_data_reg[193] (mem_intfc0_n_188),\n .\\not_strict_mode.app_rd_data_reg[194] (mem_intfc0_n_184),\n .\\not_strict_mode.app_rd_data_reg[195] (mem_intfc0_n_180),\n .\\not_strict_mode.app_rd_data_reg[196] (mem_intfc0_n_176),\n .\\not_strict_mode.app_rd_data_reg[197] (mem_intfc0_n_172),\n .\\not_strict_mode.app_rd_data_reg[198] (mem_intfc0_n_168),\n .\\not_strict_mode.app_rd_data_reg[199] (mem_intfc0_n_164),\n .\\not_strict_mode.app_rd_data_reg[19] (mem_intfc0_n_371),\n .\\not_strict_mode.app_rd_data_reg[1] (mem_intfc0_n_380),\n .\\not_strict_mode.app_rd_data_reg[200] (mem_intfc0_n_190),\n .\\not_strict_mode.app_rd_data_reg[201] (mem_intfc0_n_186),\n .\\not_strict_mode.app_rd_data_reg[202] (mem_intfc0_n_182),\n .\\not_strict_mode.app_rd_data_reg[203] (mem_intfc0_n_178),\n .\\not_strict_mode.app_rd_data_reg[204] (mem_intfc0_n_174),\n .\\not_strict_mode.app_rd_data_reg[205] (mem_intfc0_n_170),\n .\\not_strict_mode.app_rd_data_reg[206] (mem_intfc0_n_166),\n .\\not_strict_mode.app_rd_data_reg[207] (mem_intfc0_n_162),\n .\\not_strict_mode.app_rd_data_reg[208] (mem_intfc0_n_191),\n .\\not_strict_mode.app_rd_data_reg[209] (mem_intfc0_n_187),\n .\\not_strict_mode.app_rd_data_reg[20] (mem_intfc0_n_367),\n .\\not_strict_mode.app_rd_data_reg[210] (mem_intfc0_n_183),\n .\\not_strict_mode.app_rd_data_reg[211] (mem_intfc0_n_179),\n .\\not_strict_mode.app_rd_data_reg[212] (mem_intfc0_n_175),\n .\\not_strict_mode.app_rd_data_reg[213] (mem_intfc0_n_171),\n .\\not_strict_mode.app_rd_data_reg[214] (mem_intfc0_n_167),\n .\\not_strict_mode.app_rd_data_reg[215] (mem_intfc0_n_163),\n .\\not_strict_mode.app_rd_data_reg[216] (mem_intfc0_n_189),\n .\\not_strict_mode.app_rd_data_reg[217] (mem_intfc0_n_185),\n .\\not_strict_mode.app_rd_data_reg[218] (mem_intfc0_n_181),\n .\\not_strict_mode.app_rd_data_reg[219] (mem_intfc0_n_177),\n .\\not_strict_mode.app_rd_data_reg[21] (mem_intfc0_n_363),\n .\\not_strict_mode.app_rd_data_reg[220] (mem_intfc0_n_173),\n .\\not_strict_mode.app_rd_data_reg[221] (mem_intfc0_n_169),\n .\\not_strict_mode.app_rd_data_reg[222] (mem_intfc0_n_165),\n .\\not_strict_mode.app_rd_data_reg[223] (mem_intfc0_n_161),\n .\\not_strict_mode.app_rd_data_reg[224] (mem_intfc0_n_160),\n .\\not_strict_mode.app_rd_data_reg[225] (mem_intfc0_n_156),\n .\\not_strict_mode.app_rd_data_reg[226] (mem_intfc0_n_152),\n .\\not_strict_mode.app_rd_data_reg[227] (mem_intfc0_n_148),\n .\\not_strict_mode.app_rd_data_reg[228] (mem_intfc0_n_144),\n .\\not_strict_mode.app_rd_data_reg[229] (mem_intfc0_n_140),\n .\\not_strict_mode.app_rd_data_reg[22] (mem_intfc0_n_359),\n .\\not_strict_mode.app_rd_data_reg[230] (mem_intfc0_n_136),\n .\\not_strict_mode.app_rd_data_reg[231] (mem_intfc0_n_132),\n .\\not_strict_mode.app_rd_data_reg[232] (mem_intfc0_n_158),\n .\\not_strict_mode.app_rd_data_reg[233] (mem_intfc0_n_154),\n .\\not_strict_mode.app_rd_data_reg[234] (mem_intfc0_n_150),\n .\\not_strict_mode.app_rd_data_reg[235] (mem_intfc0_n_146),\n .\\not_strict_mode.app_rd_data_reg[236] (mem_intfc0_n_142),\n .\\not_strict_mode.app_rd_data_reg[237] (mem_intfc0_n_138),\n .\\not_strict_mode.app_rd_data_reg[238] (mem_intfc0_n_134),\n .\\not_strict_mode.app_rd_data_reg[239] (mem_intfc0_n_130),\n .\\not_strict_mode.app_rd_data_reg[23] (mem_intfc0_n_355),\n .\\not_strict_mode.app_rd_data_reg[240] (mem_intfc0_n_159),\n .\\not_strict_mode.app_rd_data_reg[241] (mem_intfc0_n_155),\n .\\not_strict_mode.app_rd_data_reg[242] (mem_intfc0_n_151),\n .\\not_strict_mode.app_rd_data_reg[243] (mem_intfc0_n_147),\n .\\not_strict_mode.app_rd_data_reg[244] (mem_intfc0_n_143),\n .\\not_strict_mode.app_rd_data_reg[245] (mem_intfc0_n_139),\n .\\not_strict_mode.app_rd_data_reg[246] (mem_intfc0_n_135),\n .\\not_strict_mode.app_rd_data_reg[247] (mem_intfc0_n_131),\n .\\not_strict_mode.app_rd_data_reg[248] (mem_intfc0_n_157),\n .\\not_strict_mode.app_rd_data_reg[249] (mem_intfc0_n_153),\n .\\not_strict_mode.app_rd_data_reg[24] (mem_intfc0_n_381),\n .\\not_strict_mode.app_rd_data_reg[250] (mem_intfc0_n_149),\n .\\not_strict_mode.app_rd_data_reg[251] (mem_intfc0_n_145),\n .\\not_strict_mode.app_rd_data_reg[252] (mem_intfc0_n_141),\n .\\not_strict_mode.app_rd_data_reg[253] (mem_intfc0_n_137),\n .\\not_strict_mode.app_rd_data_reg[254] (mem_intfc0_n_133),\n .\\not_strict_mode.app_rd_data_reg[255] (mem_intfc0_n_129),\n .\\not_strict_mode.app_rd_data_reg[255]_0 (app_rd_data_ns),\n .\\not_strict_mode.app_rd_data_reg[25] (mem_intfc0_n_377),\n .\\not_strict_mode.app_rd_data_reg[26] (mem_intfc0_n_373),\n .\\not_strict_mode.app_rd_data_reg[27] (mem_intfc0_n_369),\n .\\not_strict_mode.app_rd_data_reg[28] (mem_intfc0_n_365),\n .\\not_strict_mode.app_rd_data_reg[29] (mem_intfc0_n_361),\n .\\not_strict_mode.app_rd_data_reg[2] (mem_intfc0_n_376),\n .\\not_strict_mode.app_rd_data_reg[30] (mem_intfc0_n_357),\n .\\not_strict_mode.app_rd_data_reg[31] (mem_intfc0_n_353),\n .\\not_strict_mode.app_rd_data_reg[32] (mem_intfc0_n_352),\n .\\not_strict_mode.app_rd_data_reg[33] (mem_intfc0_n_348),\n .\\not_strict_mode.app_rd_data_reg[34] (mem_intfc0_n_344),\n .\\not_strict_mode.app_rd_data_reg[35] (mem_intfc0_n_340),\n .\\not_strict_mode.app_rd_data_reg[36] (mem_intfc0_n_336),\n .\\not_strict_mode.app_rd_data_reg[37] (mem_intfc0_n_332),\n .\\not_strict_mode.app_rd_data_reg[38] (mem_intfc0_n_328),\n .\\not_strict_mode.app_rd_data_reg[39] (mem_intfc0_n_324),\n .\\not_strict_mode.app_rd_data_reg[3] (mem_intfc0_n_372),\n .\\not_strict_mode.app_rd_data_reg[40] (mem_intfc0_n_350),\n .\\not_strict_mode.app_rd_data_reg[41] (mem_intfc0_n_346),\n .\\not_strict_mode.app_rd_data_reg[42] (mem_intfc0_n_342),\n .\\not_strict_mode.app_rd_data_reg[43] (mem_intfc0_n_338),\n .\\not_strict_mode.app_rd_data_reg[44] (mem_intfc0_n_334),\n .\\not_strict_mode.app_rd_data_reg[45] (mem_intfc0_n_330),\n .\\not_strict_mode.app_rd_data_reg[46] (mem_intfc0_n_326),\n .\\not_strict_mode.app_rd_data_reg[47] (mem_intfc0_n_322),\n .\\not_strict_mode.app_rd_data_reg[48] (mem_intfc0_n_351),\n .\\not_strict_mode.app_rd_data_reg[49] (mem_intfc0_n_347),\n .\\not_strict_mode.app_rd_data_reg[4] (mem_intfc0_n_368),\n .\\not_strict_mode.app_rd_data_reg[50] (mem_intfc0_n_343),\n .\\not_strict_mode.app_rd_data_reg[51] (mem_intfc0_n_339),\n .\\not_strict_mode.app_rd_data_reg[52] (mem_intfc0_n_335),\n .\\not_strict_mode.app_rd_data_reg[53] (mem_intfc0_n_331),\n .\\not_strict_mode.app_rd_data_reg[54] (mem_intfc0_n_327),\n .\\not_strict_mode.app_rd_data_reg[55] (mem_intfc0_n_323),\n .\\not_strict_mode.app_rd_data_reg[56] (mem_intfc0_n_349),\n .\\not_strict_mode.app_rd_data_reg[57] (mem_intfc0_n_345),\n .\\not_strict_mode.app_rd_data_reg[58] (mem_intfc0_n_341),\n .\\not_strict_mode.app_rd_data_reg[59] (mem_intfc0_n_337),\n .\\not_strict_mode.app_rd_data_reg[5] (mem_intfc0_n_364),\n .\\not_strict_mode.app_rd_data_reg[60] (mem_intfc0_n_333),\n .\\not_strict_mode.app_rd_data_reg[61] (mem_intfc0_n_329),\n .\\not_strict_mode.app_rd_data_reg[62] (mem_intfc0_n_325),\n .\\not_strict_mode.app_rd_data_reg[63] (mem_intfc0_n_321),\n .\\not_strict_mode.app_rd_data_reg[64] (mem_intfc0_n_320),\n .\\not_strict_mode.app_rd_data_reg[65] (mem_intfc0_n_316),\n .\\not_strict_mode.app_rd_data_reg[66] (mem_intfc0_n_312),\n .\\not_strict_mode.app_rd_data_reg[67] (mem_intfc0_n_308),\n .\\not_strict_mode.app_rd_data_reg[68] (mem_intfc0_n_304),\n .\\not_strict_mode.app_rd_data_reg[69] (mem_intfc0_n_300),\n .\\not_strict_mode.app_rd_data_reg[6] (mem_intfc0_n_360),\n .\\not_strict_mode.app_rd_data_reg[70] (mem_intfc0_n_296),\n .\\not_strict_mode.app_rd_data_reg[71] (mem_intfc0_n_292),\n .\\not_strict_mode.app_rd_data_reg[72] (mem_intfc0_n_318),\n .\\not_strict_mode.app_rd_data_reg[73] (mem_intfc0_n_314),\n .\\not_strict_mode.app_rd_data_reg[74] (mem_intfc0_n_310),\n .\\not_strict_mode.app_rd_data_reg[75] (mem_intfc0_n_306),\n .\\not_strict_mode.app_rd_data_reg[76] (mem_intfc0_n_302),\n .\\not_strict_mode.app_rd_data_reg[77] (mem_intfc0_n_298),\n .\\not_strict_mode.app_rd_data_reg[78] (mem_intfc0_n_294),\n .\\not_strict_mode.app_rd_data_reg[79] (mem_intfc0_n_290),\n .\\not_strict_mode.app_rd_data_reg[7] (mem_intfc0_n_356),\n .\\not_strict_mode.app_rd_data_reg[80] (mem_intfc0_n_319),\n .\\not_strict_mode.app_rd_data_reg[81] (mem_intfc0_n_315),\n .\\not_strict_mode.app_rd_data_reg[82] (mem_intfc0_n_311),\n .\\not_strict_mode.app_rd_data_reg[83] (mem_intfc0_n_307),\n .\\not_strict_mode.app_rd_data_reg[84] (mem_intfc0_n_303),\n .\\not_strict_mode.app_rd_data_reg[85] (mem_intfc0_n_299),\n .\\not_strict_mode.app_rd_data_reg[86] (mem_intfc0_n_295),\n .\\not_strict_mode.app_rd_data_reg[87] (mem_intfc0_n_291),\n .\\not_strict_mode.app_rd_data_reg[88] (mem_intfc0_n_317),\n .\\not_strict_mode.app_rd_data_reg[89] (mem_intfc0_n_313),\n .\\not_strict_mode.app_rd_data_reg[8] (mem_intfc0_n_382),\n .\\not_strict_mode.app_rd_data_reg[90] (mem_intfc0_n_309),\n .\\not_strict_mode.app_rd_data_reg[91] (mem_intfc0_n_305),\n .\\not_strict_mode.app_rd_data_reg[92] (mem_intfc0_n_301),\n .\\not_strict_mode.app_rd_data_reg[93] (mem_intfc0_n_297),\n .\\not_strict_mode.app_rd_data_reg[94] (mem_intfc0_n_293),\n .\\not_strict_mode.app_rd_data_reg[95] (mem_intfc0_n_289),\n .\\not_strict_mode.app_rd_data_reg[96] (mem_intfc0_n_288),\n .\\not_strict_mode.app_rd_data_reg[97] (mem_intfc0_n_284),\n .\\not_strict_mode.app_rd_data_reg[98] (mem_intfc0_n_280),\n .\\not_strict_mode.app_rd_data_reg[99] (mem_intfc0_n_276),\n .\\not_strict_mode.app_rd_data_reg[9] (mem_intfc0_n_378),\n .\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (data_buf_addr),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\\ui_rd_data0/p_123_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\\ui_rd_data0/p_124_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\\ui_rd_data0/p_125_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\\ui_rd_data0/p_116_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 (\\ui_rd_data0/p_26_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 (\\ui_rd_data0/p_21_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 (\\ui_rd_data0/p_22_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 (\\ui_rd_data0/p_23_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 (\\ui_rd_data0/p_18_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 (\\ui_rd_data0/p_19_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 (\\ui_rd_data0/p_20_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 (\\ui_rd_data0/p_15_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 (\\ui_rd_data0/p_16_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 (\\ui_rd_data0/p_17_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\\ui_rd_data0/p_111_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 (\\ui_rd_data0/p_12_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 (\\ui_rd_data0/p_13_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 (\\ui_rd_data0/p_14_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 (\\ui_rd_data0/p_9_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 (\\ui_rd_data0/p_10_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 (\\ui_rd_data0/p_11_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 (\\ui_rd_data0/p_6_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 (\\ui_rd_data0/p_7_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 (\\ui_rd_data0/p_8_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 (\\ui_rd_data0/p_3_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\\ui_rd_data0/p_112_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 (\\ui_rd_data0/p_4_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 (\\ui_rd_data0/p_5_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ({u_ui_top_n_260,u_ui_top_n_261}),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 (\\ui_rd_data0/p_1_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\\ui_rd_data0/p_113_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\\ui_rd_data0/p_108_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\\ui_rd_data0/p_109_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\\ui_rd_data0/p_110_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\\ui_rd_data0/p_105_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\\ui_rd_data0/p_106_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\\ui_rd_data0/p_107_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\\ui_rd_data0/p_120_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\\ui_rd_data0/p_102_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\\ui_rd_data0/p_103_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\\ui_rd_data0/p_104_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\\ui_rd_data0/p_99_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\\ui_rd_data0/p_100_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\\ui_rd_data0/p_101_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\\ui_rd_data0/p_96_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\\ui_rd_data0/p_97_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\\ui_rd_data0/p_98_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\\ui_rd_data0/p_93_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\\ui_rd_data0/p_121_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\\ui_rd_data0/p_94_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 (\\ui_rd_data0/p_95_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 (\\ui_rd_data0/p_90_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 (\\ui_rd_data0/p_91_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 (\\ui_rd_data0/p_92_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 (\\ui_rd_data0/p_87_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 (\\ui_rd_data0/p_88_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 (\\ui_rd_data0/p_89_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 (\\ui_rd_data0/p_84_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 (\\ui_rd_data0/p_85_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\\ui_rd_data0/p_122_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 (\\ui_rd_data0/p_86_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 (\\ui_rd_data0/p_81_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 (\\ui_rd_data0/p_82_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 (\\ui_rd_data0/p_83_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 (\\ui_rd_data0/p_78_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 (\\ui_rd_data0/p_79_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 (\\ui_rd_data0/p_80_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 (\\ui_rd_data0/p_75_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 (\\ui_rd_data0/p_76_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 (\\ui_rd_data0/p_77_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\\ui_rd_data0/p_117_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 (\\ui_rd_data0/p_72_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 (\\ui_rd_data0/p_73_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 (\\ui_rd_data0/p_74_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 (\\ui_rd_data0/p_69_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 (\\ui_rd_data0/p_70_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 (\\ui_rd_data0/p_71_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 (\\ui_rd_data0/p_66_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 (\\ui_rd_data0/p_67_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 (\\ui_rd_data0/p_68_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 (\\ui_rd_data0/p_63_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\\ui_rd_data0/p_118_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 (\\ui_rd_data0/p_64_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 (\\ui_rd_data0/p_65_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 (\\ui_rd_data0/p_60_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 (\\ui_rd_data0/p_61_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 (\\ui_rd_data0/p_62_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 (\\ui_rd_data0/p_57_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 (\\ui_rd_data0/p_58_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 (\\ui_rd_data0/p_59_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 (\\ui_rd_data0/p_54_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 (\\ui_rd_data0/p_55_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\\ui_rd_data0/p_119_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 (\\ui_rd_data0/p_56_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 (\\ui_rd_data0/p_51_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 (\\ui_rd_data0/p_52_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 (\\ui_rd_data0/p_53_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 (\\ui_rd_data0/p_48_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 (\\ui_rd_data0/p_49_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 (\\ui_rd_data0/p_50_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 (\\ui_rd_data0/p_45_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 (\\ui_rd_data0/p_46_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 (\\ui_rd_data0/p_47_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\\ui_rd_data0/p_114_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 (\\ui_rd_data0/p_42_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 (\\ui_rd_data0/p_43_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 (\\ui_rd_data0/p_44_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 (\\ui_rd_data0/p_39_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 (\\ui_rd_data0/p_40_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 (\\ui_rd_data0/p_41_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 (\\ui_rd_data0/p_36_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 (\\ui_rd_data0/p_37_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 (\\ui_rd_data0/p_38_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 (\\ui_rd_data0/p_33_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\\ui_rd_data0/p_115_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 (\\ui_rd_data0/p_34_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 (\\ui_rd_data0/p_35_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 (\\ui_rd_data0/p_30_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 (\\ui_rd_data0/p_31_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 (\\ui_rd_data0/p_32_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 (\\ui_rd_data0/p_27_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 (\\ui_rd_data0/p_28_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 (\\ui_rd_data0/p_29_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 (\\ui_rd_data0/p_24_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 (\\ui_rd_data0/p_25_out ),\n .\\not_strict_mode.status_ram.rd_buf_we_r1_reg (\\ui_rd_data0/rd_status ),\n .p_28_out(\\mc0/bank_mach0/p_28_out ),\n .p_67_out(\\mc0/bank_mach0/p_67_out ),\n .p_81_in(p_81_in),\n .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg),\n .phy_dout(phy_dout),\n .pi_cnt_dec_reg(pi_cnt_dec_reg),\n .pi_en_stg2_f_timing_reg(pi_cnt_dec),\n .\\pi_rst_stg1_cal_r_reg[0] (\\pi_rst_stg1_cal_r_reg[0] ),\n .pll_locked(pll_locked),\n .po_cnt_dec_reg(po_cnt_dec_reg),\n .poc_sample_pd(poc_sample_pd),\n .pointer_we(\\ui_wr_data0/pointer_we ),\n .psdone(psdone),\n .\\qcntr_r_reg[0] (E),\n .ram_init_done_r(ram_init_done_r),\n .\\rd_buf_indx.rd_buf_indx_r_reg[4] ({u_ui_top_n_1,ram_init_addr}),\n .rd_buf_we(\\ui_rd_data0/rd_buf_we ),\n .\\rd_ptr_reg[3] (\\rd_ptr_reg[3] ),\n .\\rd_ptr_reg[3]_0 (\\rd_ptr_reg[3]_0 ),\n .\\rd_ptr_timing_reg[0] (\\rd_ptr_timing_reg[0] ),\n .\\rd_ptr_timing_reg[0]_0 (\\rd_ptr_timing_reg[0]_0 ),\n .\\rd_ptr_timing_reg[2] (\\rd_ptr_timing_reg[2] ),\n .\\rd_ptr_timing_reg[2]_0 (\\rd_ptr_timing_reg[2]_0 ),\n .\\rd_ptr_timing_reg[2]_1 (\\rd_ptr_timing_reg[2]_1 ),\n .\\rd_ptr_timing_reg[2]_10 (\\rd_ptr_timing_reg[2]_10 ),\n .\\rd_ptr_timing_reg[2]_2 (\\rd_ptr_timing_reg[2]_2 ),\n .\\rd_ptr_timing_reg[2]_3 (\\rd_ptr_timing_reg[2]_3 ),\n .\\rd_ptr_timing_reg[2]_4 (\\rd_ptr_timing_reg[2]_4 ),\n .\\rd_ptr_timing_reg[2]_5 (\\rd_ptr_timing_reg[2]_5 ),\n .\\rd_ptr_timing_reg[2]_6 (\\rd_ptr_timing_reg[2]_6 ),\n .\\rd_ptr_timing_reg[2]_7 (\\rd_ptr_timing_reg[2]_7 ),\n .\\rd_ptr_timing_reg[2]_8 (\\rd_ptr_timing_reg[2]_8 ),\n .\\rd_ptr_timing_reg[2]_9 (\\rd_ptr_timing_reg[2]_9 ),\n .\\req_bank_r_lcl_reg[0] (u_ui_top_n_274),\n .\\req_bank_r_lcl_reg[0]_0 (u_ui_top_n_272),\n .\\resume_wait_r_reg[5] (\\resume_wait_r_reg[5] ),\n .\\row_cnt_victim_rotate.complex_row_cnt_reg[4] (\\row_cnt_victim_rotate.complex_row_cnt_reg[4] ),\n .\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] (\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .rst_sync_r1(rst_sync_r1),\n .rst_sync_r1_reg(rst_sync_r1_reg),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10),\n .rstdiv0_sync_r1_reg_rep__11(rstdiv0_sync_r1_reg_rep__11),\n .rstdiv0_sync_r1_reg_rep__12(rstdiv0_sync_r1_reg_rep__12),\n .rstdiv0_sync_r1_reg_rep__13(rstdiv0_sync_r1_reg_rep__13),\n .rstdiv0_sync_r1_reg_rep__14(rstdiv0_sync_r1_reg_rep__14),\n .rstdiv0_sync_r1_reg_rep__16(rstdiv0_sync_r1_reg_rep__16),\n .rstdiv0_sync_r1_reg_rep__17(rstdiv0_sync_r1_reg_rep__17),\n .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),\n .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22),\n .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23),\n .rstdiv0_sync_r1_reg_rep__23_0(rstdiv0_sync_r1_reg_rep__23_0),\n .rstdiv0_sync_r1_reg_rep__23_1(rstdiv0_sync_r1_reg_rep__23_1),\n .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),\n .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25),\n .rstdiv0_sync_r1_reg_rep__25_0(rstdiv0_sync_r1_reg_rep__25_0),\n .rstdiv0_sync_r1_reg_rep__25_1(rstdiv0_sync_r1_reg_rep__25_1),\n .rstdiv0_sync_r1_reg_rep__25_2(rstdiv0_sync_r1_reg_rep__25_2),\n .rstdiv0_sync_r1_reg_rep__4(rstdiv0_sync_r1_reg_rep__4),\n .rstdiv0_sync_r1_reg_rep__5(rstdiv0_sync_r1_reg_rep__5),\n .rstdiv0_sync_r1_reg_rep__6(rstdiv0_sync_r1_reg_rep__6),\n .rstdiv0_sync_r1_reg_rep__7(rstdiv0_sync_r1_reg_rep__7),\n .rstdiv0_sync_r1_reg_rep__8(rstdiv0_sync_r1_reg_rep__8),\n .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9),\n .rtp_timer_ns1(rtp_timer_ns1),\n .samp_edge_cnt0_en_r(samp_edge_cnt0_en_r),\n .samp_edge_cnt0_en_r_reg(samp_edge_cnt0_en_r_reg),\n .\\samps_r_reg[9] (sm_r),\n .\\sm_r_reg[0] (\\sm_r_reg[0] ),\n .\\sm_r_reg[0]_0 (\\sm_r_reg[0]_0 ),\n .\\stg2_tap_cnt_reg[0] (\\stg2_tap_cnt_reg[0] ),\n .stg3_dec2init_val_r_reg(stg3_dec2init_val_r_reg),\n .stg3_inc2init_val_r_reg(stg3_inc2init_val_r_reg),\n .\\stg3_r_reg[0] (\\stg3_r_reg[0] ),\n .sync_pulse(sync_pulse),\n .sys_rst(sys_rst),\n .use_addr(use_addr),\n .wr_en(wr_en),\n .wr_en_5(wr_en_5),\n .wr_en_6(wr_en_6),\n .\\wr_ptr_timing_reg[2] (Q),\n .\\wr_ptr_timing_reg[2]_0 (\\wr_ptr_timing_reg[2] ),\n .\\wr_ptr_timing_reg[2]_1 (\\wr_ptr_timing_reg[2]_0 ),\n .\\write_buffer.wr_buf_out_data_reg[287] (wr_data_addr));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n reset_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r1_reg_rep__25),\n .Q(reset_reg_n_0),\n .R(1'b0));\n ddr3_ifmig_7series_v4_0_axi_mc u_axi_mc\n (.CLK(CLK),\n .D(\\axi_mc_w_channel_0/next_wdf_mask ),\n .E(\\ui_cmd0/app_addr_r10 ),\n .Q(app_rd_data),\n .\\app_addr_r1_reg[27] (app_addr),\n .app_en_ns1(\\ui_cmd0/app_en_ns1 ),\n .app_en_r1(\\ui_cmd0/app_en_r1 ),\n .app_rd_data_valid(app_rd_data_valid),\n .app_rdy(app_rdy),\n .app_wdf_data(app_wdf_data),\n .app_wdf_mask(app_wdf_mask),\n .app_wdf_rdy(app_wdf_rdy),\n .aresetn(aresetn),\n .mc_app_cmd(app_cmd),\n .mc_app_wdf_data_reg(\\axi_mc_w_channel_0/mc_app_wdf_data_reg ),\n .\\mc_app_wdf_data_reg_reg[255] (\\axi_mc_w_channel_0/next_wdf_data ),\n .mc_app_wdf_mask_reg(\\axi_mc_w_channel_0/mc_app_wdf_mask_reg ),\n .mc_app_wdf_wren_reg(\\axi_mc_w_channel_0/mc_app_wdf_wren_reg ),\n .mc_init_complete(init_calib_complete_r),\n .out(out),\n .reset_reg(reset_reg_n_0),\n .s_axi_araddr(s_axi_araddr),\n .s_axi_arburst(s_axi_arburst),\n .s_axi_arid(s_axi_arid),\n .s_axi_arlen(s_axi_arlen),\n .s_axi_arready(s_axi_arready),\n .s_axi_arvalid(s_axi_arvalid),\n .s_axi_awaddr(s_axi_awaddr),\n .s_axi_awburst(s_axi_awburst),\n .s_axi_awid(s_axi_awid),\n .s_axi_awlen(s_axi_awlen),\n .s_axi_awready(s_axi_awready),\n .s_axi_awvalid(s_axi_awvalid),\n .s_axi_bid(s_axi_bid),\n .s_axi_bready(s_axi_bready),\n .s_axi_bvalid(s_axi_bvalid),\n .s_axi_rid(s_axi_rid),\n .s_axi_rlast(s_axi_rlast),\n .s_axi_rready(s_axi_rready),\n .s_axi_rvalid(s_axi_rvalid),\n .s_axi_wdata(s_axi_wdata),\n .s_axi_wready(s_axi_wready),\n .s_axi_wstrb(s_axi_wstrb),\n .s_axi_wvalid(s_axi_wvalid),\n .w_cmd_rdy(w_cmd_rdy));\n ddr3_ifmig_7series_v4_0_ui_top u_ui_top\n (.CLK(CLK),\n .D(\\axi_mc_w_channel_0/next_wdf_mask ),\n .DIA({mem_intfc0_n_364,mem_intfc0_n_368}),\n .DIB({mem_intfc0_n_372,mem_intfc0_n_376}),\n .DIC({mem_intfc0_n_380,mem_intfc0_n_384}),\n .DOA(\\ui_rd_data0/p_129_out ),\n .DOB(\\ui_rd_data0/p_128_out ),\n .DOC(\\ui_rd_data0/p_127_out ),\n .E(wr_data_en),\n .Q({u_ui_top_n_1,ram_init_addr}),\n .accept_ns(accept_ns),\n .app_en_ns1(\\ui_cmd0/app_en_ns1 ),\n .app_en_r1(\\ui_cmd0/app_en_r1 ),\n .app_hi_pri_r2(\\ui_cmd0/app_hi_pri_r2 ),\n .app_rd_data_end_ns(\\ui_rd_data0/app_rd_data_end_ns ),\n .app_rd_data_valid(app_rd_data_valid),\n .app_rdy(app_rdy),\n .app_rdy_r_reg(\\ui_cmd0/app_addr_r10 ),\n .app_wdf_data(app_wdf_data),\n .app_wdf_mask(app_wdf_mask),\n .app_wdf_rdy(app_wdf_rdy),\n .\\axaddr_incr_reg[29] (app_addr),\n .bypass__0(\\ui_rd_data0/bypass__0 ),\n .cmd(cmd),\n .\\cmd_pipe_plus.wr_data_addr_reg[3] (wr_data_addr),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ({mem_intfc0_n_353,mem_intfc0_n_357}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ({mem_intfc0_n_292,mem_intfc0_n_296}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ({mem_intfc0_n_290,mem_intfc0_n_294}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ({mem_intfc0_n_291,mem_intfc0_n_295}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ({mem_intfc0_n_260,mem_intfc0_n_264}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ({mem_intfc0_n_258,mem_intfc0_n_262}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ({mem_intfc0_n_259,mem_intfc0_n_263}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ({mem_intfc0_n_228,mem_intfc0_n_232}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ({mem_intfc0_n_226,mem_intfc0_n_230}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ({mem_intfc0_n_227,mem_intfc0_n_231}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ({mem_intfc0_n_196,mem_intfc0_n_200}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ({mem_intfc0_n_194,mem_intfc0_n_198}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ({mem_intfc0_n_195,mem_intfc0_n_199}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ({mem_intfc0_n_164,mem_intfc0_n_168}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ({mem_intfc0_n_162,mem_intfc0_n_166}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ({mem_intfc0_n_163,mem_intfc0_n_167}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ({mem_intfc0_n_132,mem_intfc0_n_136}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ({mem_intfc0_n_130,mem_intfc0_n_134}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ({mem_intfc0_n_131,mem_intfc0_n_135}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ({mem_intfc0_n_361,mem_intfc0_n_365}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ({mem_intfc0_n_329,mem_intfc0_n_333}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ({mem_intfc0_n_297,mem_intfc0_n_301}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ({mem_intfc0_n_265,mem_intfc0_n_269}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ({mem_intfc0_n_321,mem_intfc0_n_325}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ({mem_intfc0_n_233,mem_intfc0_n_237}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ({mem_intfc0_n_201,mem_intfc0_n_205}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ({mem_intfc0_n_169,mem_intfc0_n_173}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ({mem_intfc0_n_137,mem_intfc0_n_141}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ({mem_intfc0_n_362,mem_intfc0_n_366}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ({mem_intfc0_n_363,mem_intfc0_n_367}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ({mem_intfc0_n_332,mem_intfc0_n_336}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ({mem_intfc0_n_330,mem_intfc0_n_334}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ({mem_intfc0_n_331,mem_intfc0_n_335}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ({mem_intfc0_n_300,mem_intfc0_n_304}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ({mem_intfc0_n_298,mem_intfc0_n_302}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ({mem_intfc0_n_299,mem_intfc0_n_303}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ({mem_intfc0_n_268,mem_intfc0_n_272}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ({mem_intfc0_n_266,mem_intfc0_n_270}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ({mem_intfc0_n_267,mem_intfc0_n_271}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ({mem_intfc0_n_236,mem_intfc0_n_240}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ({mem_intfc0_n_234,mem_intfc0_n_238}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ({mem_intfc0_n_235,mem_intfc0_n_239}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ({mem_intfc0_n_204,mem_intfc0_n_208}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ({mem_intfc0_n_202,mem_intfc0_n_206}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ({mem_intfc0_n_203,mem_intfc0_n_207}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ({mem_intfc0_n_289,mem_intfc0_n_293}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ({mem_intfc0_n_172,mem_intfc0_n_176}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ({mem_intfc0_n_170,mem_intfc0_n_174}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ({mem_intfc0_n_171,mem_intfc0_n_175}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ({mem_intfc0_n_140,mem_intfc0_n_144}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ({mem_intfc0_n_138,mem_intfc0_n_142}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ({mem_intfc0_n_139,mem_intfc0_n_143}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ({mem_intfc0_n_369,mem_intfc0_n_373}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ({mem_intfc0_n_337,mem_intfc0_n_341}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ({mem_intfc0_n_305,mem_intfc0_n_309}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ({mem_intfc0_n_273,mem_intfc0_n_277}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ({mem_intfc0_n_241,mem_intfc0_n_245}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ({mem_intfc0_n_209,mem_intfc0_n_213}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ({mem_intfc0_n_177,mem_intfc0_n_181}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ({mem_intfc0_n_145,mem_intfc0_n_149}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ({mem_intfc0_n_257,mem_intfc0_n_261}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ({mem_intfc0_n_370,mem_intfc0_n_374}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ({mem_intfc0_n_371,mem_intfc0_n_375}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ({mem_intfc0_n_340,mem_intfc0_n_344}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ({mem_intfc0_n_338,mem_intfc0_n_342}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ({mem_intfc0_n_339,mem_intfc0_n_343}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ({mem_intfc0_n_308,mem_intfc0_n_312}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ({mem_intfc0_n_306,mem_intfc0_n_310}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ({mem_intfc0_n_307,mem_intfc0_n_311}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ({mem_intfc0_n_276,mem_intfc0_n_280}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ({mem_intfc0_n_274,mem_intfc0_n_278}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ({mem_intfc0_n_275,mem_intfc0_n_279}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ({mem_intfc0_n_244,mem_intfc0_n_248}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ({mem_intfc0_n_242,mem_intfc0_n_246}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ({mem_intfc0_n_243,mem_intfc0_n_247}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ({mem_intfc0_n_212,mem_intfc0_n_216}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ({mem_intfc0_n_210,mem_intfc0_n_214}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ({mem_intfc0_n_211,mem_intfc0_n_215}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ({mem_intfc0_n_180,mem_intfc0_n_184}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ({mem_intfc0_n_178,mem_intfc0_n_182}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ({mem_intfc0_n_179,mem_intfc0_n_183}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ({mem_intfc0_n_148,mem_intfc0_n_152}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ({mem_intfc0_n_146,mem_intfc0_n_150}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ({mem_intfc0_n_147,mem_intfc0_n_151}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ({mem_intfc0_n_377,mem_intfc0_n_381}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ({mem_intfc0_n_345,mem_intfc0_n_349}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ({mem_intfc0_n_225,mem_intfc0_n_229}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ({mem_intfc0_n_313,mem_intfc0_n_317}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ({mem_intfc0_n_281,mem_intfc0_n_285}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ({mem_intfc0_n_249,mem_intfc0_n_253}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ({mem_intfc0_n_217,mem_intfc0_n_221}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ({mem_intfc0_n_185,mem_intfc0_n_189}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ({mem_intfc0_n_153,mem_intfc0_n_157}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ({mem_intfc0_n_378,mem_intfc0_n_382}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ({mem_intfc0_n_379,mem_intfc0_n_383}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ({mem_intfc0_n_348,mem_intfc0_n_352}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ({mem_intfc0_n_346,mem_intfc0_n_350}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ({mem_intfc0_n_347,mem_intfc0_n_351}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ({mem_intfc0_n_316,mem_intfc0_n_320}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ({mem_intfc0_n_314,mem_intfc0_n_318}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ({mem_intfc0_n_315,mem_intfc0_n_319}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ({mem_intfc0_n_284,mem_intfc0_n_288}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ({mem_intfc0_n_282,mem_intfc0_n_286}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ({mem_intfc0_n_283,mem_intfc0_n_287}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ({mem_intfc0_n_193,mem_intfc0_n_197}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ({mem_intfc0_n_252,mem_intfc0_n_256}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ({mem_intfc0_n_250,mem_intfc0_n_254}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ({mem_intfc0_n_251,mem_intfc0_n_255}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ({mem_intfc0_n_220,mem_intfc0_n_224}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ({mem_intfc0_n_218,mem_intfc0_n_222}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ({mem_intfc0_n_219,mem_intfc0_n_223}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ({mem_intfc0_n_188,mem_intfc0_n_192}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ({mem_intfc0_n_186,mem_intfc0_n_190}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ({mem_intfc0_n_187,mem_intfc0_n_191}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ({mem_intfc0_n_156,mem_intfc0_n_160}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ({mem_intfc0_n_154,mem_intfc0_n_158}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ({mem_intfc0_n_155,mem_intfc0_n_159}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ({mem_intfc0_n_161,mem_intfc0_n_165}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ({mem_intfc0_n_129,mem_intfc0_n_133}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 (app_rd_data_ns),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ({mem_intfc0_n_356,mem_intfc0_n_360}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ({mem_intfc0_n_354,mem_intfc0_n_358}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ({mem_intfc0_n_355,mem_intfc0_n_359}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ({mem_intfc0_n_324,mem_intfc0_n_328}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ({mem_intfc0_n_322,mem_intfc0_n_326}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ({mem_intfc0_n_323,mem_intfc0_n_327}),\n .hi_priority(hi_priority),\n .idle_ns(\\mc0/bank_mach0/idle_ns ),\n .mc_app_cmd(app_cmd),\n .mc_app_wdf_data_reg(\\axi_mc_w_channel_0/mc_app_wdf_data_reg ),\n .mc_app_wdf_mask_reg(\\axi_mc_w_channel_0/mc_app_wdf_mask_reg ),\n .mc_app_wdf_wren_reg(\\axi_mc_w_channel_0/mc_app_wdf_wren_reg ),\n .\\my_empty_reg[7] ({wr_data_mask,wr_data}),\n .\\not_strict_mode.app_rd_data_end_reg (\\ui_rd_data0/rd_status ),\n .\\not_strict_mode.app_rd_data_reg[101] (\\ui_rd_data0/p_80_out ),\n .\\not_strict_mode.app_rd_data_reg[103] (\\ui_rd_data0/p_75_out ),\n .\\not_strict_mode.app_rd_data_reg[105] (\\ui_rd_data0/p_76_out ),\n .\\not_strict_mode.app_rd_data_reg[107] (\\ui_rd_data0/p_77_out ),\n .\\not_strict_mode.app_rd_data_reg[109] (\\ui_rd_data0/p_72_out ),\n .\\not_strict_mode.app_rd_data_reg[111] (\\ui_rd_data0/p_73_out ),\n .\\not_strict_mode.app_rd_data_reg[113] (\\ui_rd_data0/p_74_out ),\n .\\not_strict_mode.app_rd_data_reg[115] (\\ui_rd_data0/p_69_out ),\n .\\not_strict_mode.app_rd_data_reg[117] (\\ui_rd_data0/p_70_out ),\n .\\not_strict_mode.app_rd_data_reg[119] (\\ui_rd_data0/p_71_out ),\n .\\not_strict_mode.app_rd_data_reg[11] (\\ui_rd_data0/p_125_out ),\n .\\not_strict_mode.app_rd_data_reg[121] (\\ui_rd_data0/p_66_out ),\n .\\not_strict_mode.app_rd_data_reg[123] (\\ui_rd_data0/p_67_out ),\n .\\not_strict_mode.app_rd_data_reg[125] (\\ui_rd_data0/p_68_out ),\n .\\not_strict_mode.app_rd_data_reg[127] (\\ui_rd_data0/p_63_out ),\n .\\not_strict_mode.app_rd_data_reg[129] (\\ui_rd_data0/p_64_out ),\n .\\not_strict_mode.app_rd_data_reg[131] (\\ui_rd_data0/p_65_out ),\n .\\not_strict_mode.app_rd_data_reg[133] (\\ui_rd_data0/p_60_out ),\n .\\not_strict_mode.app_rd_data_reg[135] (\\ui_rd_data0/p_61_out ),\n .\\not_strict_mode.app_rd_data_reg[137] (\\ui_rd_data0/p_62_out ),\n .\\not_strict_mode.app_rd_data_reg[139] (\\ui_rd_data0/p_57_out ),\n .\\not_strict_mode.app_rd_data_reg[13] (\\ui_rd_data0/p_120_out ),\n .\\not_strict_mode.app_rd_data_reg[141] (\\ui_rd_data0/p_58_out ),\n .\\not_strict_mode.app_rd_data_reg[143] (\\ui_rd_data0/p_59_out ),\n .\\not_strict_mode.app_rd_data_reg[145] (\\ui_rd_data0/p_54_out ),\n .\\not_strict_mode.app_rd_data_reg[147] (\\ui_rd_data0/p_55_out ),\n .\\not_strict_mode.app_rd_data_reg[149] (\\ui_rd_data0/p_56_out ),\n .\\not_strict_mode.app_rd_data_reg[151] (\\ui_rd_data0/p_51_out ),\n .\\not_strict_mode.app_rd_data_reg[153] (\\ui_rd_data0/p_52_out ),\n .\\not_strict_mode.app_rd_data_reg[155] (\\ui_rd_data0/p_53_out ),\n .\\not_strict_mode.app_rd_data_reg[157] (\\ui_rd_data0/p_48_out ),\n .\\not_strict_mode.app_rd_data_reg[159] (\\ui_rd_data0/p_49_out ),\n .\\not_strict_mode.app_rd_data_reg[15] (\\ui_rd_data0/p_121_out ),\n .\\not_strict_mode.app_rd_data_reg[161] (\\ui_rd_data0/p_50_out ),\n .\\not_strict_mode.app_rd_data_reg[163] (\\ui_rd_data0/p_45_out ),\n .\\not_strict_mode.app_rd_data_reg[165] (\\ui_rd_data0/p_46_out ),\n .\\not_strict_mode.app_rd_data_reg[167] (\\ui_rd_data0/p_47_out ),\n .\\not_strict_mode.app_rd_data_reg[169] (\\ui_rd_data0/p_42_out ),\n .\\not_strict_mode.app_rd_data_reg[171] (\\ui_rd_data0/p_43_out ),\n .\\not_strict_mode.app_rd_data_reg[173] (\\ui_rd_data0/p_44_out ),\n .\\not_strict_mode.app_rd_data_reg[175] (\\ui_rd_data0/p_39_out ),\n .\\not_strict_mode.app_rd_data_reg[177] (\\ui_rd_data0/p_40_out ),\n .\\not_strict_mode.app_rd_data_reg[179] (\\ui_rd_data0/p_41_out ),\n .\\not_strict_mode.app_rd_data_reg[17] (\\ui_rd_data0/p_122_out ),\n .\\not_strict_mode.app_rd_data_reg[181] (\\ui_rd_data0/p_36_out ),\n .\\not_strict_mode.app_rd_data_reg[183] (\\ui_rd_data0/p_37_out ),\n .\\not_strict_mode.app_rd_data_reg[185] (\\ui_rd_data0/p_38_out ),\n .\\not_strict_mode.app_rd_data_reg[187] (\\ui_rd_data0/p_33_out ),\n .\\not_strict_mode.app_rd_data_reg[189] (\\ui_rd_data0/p_34_out ),\n .\\not_strict_mode.app_rd_data_reg[191] (\\ui_rd_data0/p_35_out ),\n .\\not_strict_mode.app_rd_data_reg[193] (\\ui_rd_data0/p_30_out ),\n .\\not_strict_mode.app_rd_data_reg[195] (\\ui_rd_data0/p_31_out ),\n .\\not_strict_mode.app_rd_data_reg[197] (\\ui_rd_data0/p_32_out ),\n .\\not_strict_mode.app_rd_data_reg[199] (\\ui_rd_data0/p_27_out ),\n .\\not_strict_mode.app_rd_data_reg[19] (\\ui_rd_data0/p_117_out ),\n .\\not_strict_mode.app_rd_data_reg[201] (\\ui_rd_data0/p_28_out ),\n .\\not_strict_mode.app_rd_data_reg[203] (\\ui_rd_data0/p_29_out ),\n .\\not_strict_mode.app_rd_data_reg[205] (\\ui_rd_data0/p_24_out ),\n .\\not_strict_mode.app_rd_data_reg[207] (\\ui_rd_data0/p_25_out ),\n .\\not_strict_mode.app_rd_data_reg[209] (\\ui_rd_data0/p_26_out ),\n .\\not_strict_mode.app_rd_data_reg[211] (\\ui_rd_data0/p_21_out ),\n .\\not_strict_mode.app_rd_data_reg[213] (\\ui_rd_data0/p_22_out ),\n .\\not_strict_mode.app_rd_data_reg[215] (\\ui_rd_data0/p_23_out ),\n .\\not_strict_mode.app_rd_data_reg[217] (\\ui_rd_data0/p_18_out ),\n .\\not_strict_mode.app_rd_data_reg[219] (\\ui_rd_data0/p_19_out ),\n .\\not_strict_mode.app_rd_data_reg[21] (\\ui_rd_data0/p_118_out ),\n .\\not_strict_mode.app_rd_data_reg[221] (\\ui_rd_data0/p_20_out ),\n .\\not_strict_mode.app_rd_data_reg[223] (\\ui_rd_data0/p_15_out ),\n .\\not_strict_mode.app_rd_data_reg[225] (\\ui_rd_data0/p_16_out ),\n .\\not_strict_mode.app_rd_data_reg[227] (\\ui_rd_data0/p_17_out ),\n .\\not_strict_mode.app_rd_data_reg[229] (\\ui_rd_data0/p_12_out ),\n .\\not_strict_mode.app_rd_data_reg[231] (\\ui_rd_data0/p_13_out ),\n .\\not_strict_mode.app_rd_data_reg[233] (\\ui_rd_data0/p_14_out ),\n .\\not_strict_mode.app_rd_data_reg[235] (\\ui_rd_data0/p_9_out ),\n .\\not_strict_mode.app_rd_data_reg[237] (\\ui_rd_data0/p_10_out ),\n .\\not_strict_mode.app_rd_data_reg[239] (\\ui_rd_data0/p_11_out ),\n .\\not_strict_mode.app_rd_data_reg[23] (\\ui_rd_data0/p_119_out ),\n .\\not_strict_mode.app_rd_data_reg[241] (\\ui_rd_data0/p_6_out ),\n .\\not_strict_mode.app_rd_data_reg[243] (\\ui_rd_data0/p_7_out ),\n .\\not_strict_mode.app_rd_data_reg[245] (\\ui_rd_data0/p_8_out ),\n .\\not_strict_mode.app_rd_data_reg[247] (\\ui_rd_data0/p_3_out ),\n .\\not_strict_mode.app_rd_data_reg[249] (\\ui_rd_data0/p_4_out ),\n .\\not_strict_mode.app_rd_data_reg[251] (\\ui_rd_data0/p_5_out ),\n .\\not_strict_mode.app_rd_data_reg[253] ({u_ui_top_n_260,u_ui_top_n_261}),\n .\\not_strict_mode.app_rd_data_reg[255] (\\ui_rd_data0/p_1_out ),\n .\\not_strict_mode.app_rd_data_reg[25] (\\ui_rd_data0/p_114_out ),\n .\\not_strict_mode.app_rd_data_reg[27] (\\ui_rd_data0/p_115_out ),\n .\\not_strict_mode.app_rd_data_reg[29] (\\ui_rd_data0/p_116_out ),\n .\\not_strict_mode.app_rd_data_reg[31] (\\ui_rd_data0/p_111_out ),\n .\\not_strict_mode.app_rd_data_reg[33] (\\ui_rd_data0/p_112_out ),\n .\\not_strict_mode.app_rd_data_reg[35] (\\ui_rd_data0/p_113_out ),\n .\\not_strict_mode.app_rd_data_reg[37] (\\ui_rd_data0/p_108_out ),\n .\\not_strict_mode.app_rd_data_reg[39] (\\ui_rd_data0/p_109_out ),\n .\\not_strict_mode.app_rd_data_reg[41] (\\ui_rd_data0/p_110_out ),\n .\\not_strict_mode.app_rd_data_reg[43] (\\ui_rd_data0/p_105_out ),\n .\\not_strict_mode.app_rd_data_reg[45] (\\ui_rd_data0/p_106_out ),\n .\\not_strict_mode.app_rd_data_reg[47] (\\ui_rd_data0/p_107_out ),\n .\\not_strict_mode.app_rd_data_reg[49] (\\ui_rd_data0/p_102_out ),\n .\\not_strict_mode.app_rd_data_reg[51] (\\ui_rd_data0/p_103_out ),\n .\\not_strict_mode.app_rd_data_reg[53] (\\ui_rd_data0/p_104_out ),\n .\\not_strict_mode.app_rd_data_reg[55] (\\ui_rd_data0/p_99_out ),\n .\\not_strict_mode.app_rd_data_reg[57] (\\ui_rd_data0/p_100_out ),\n .\\not_strict_mode.app_rd_data_reg[59] (\\ui_rd_data0/p_101_out ),\n .\\not_strict_mode.app_rd_data_reg[61] (\\ui_rd_data0/p_96_out ),\n .\\not_strict_mode.app_rd_data_reg[63] (\\ui_rd_data0/p_97_out ),\n .\\not_strict_mode.app_rd_data_reg[65] (\\ui_rd_data0/p_98_out ),\n .\\not_strict_mode.app_rd_data_reg[67] (\\ui_rd_data0/p_93_out ),\n .\\not_strict_mode.app_rd_data_reg[69] (\\ui_rd_data0/p_94_out ),\n .\\not_strict_mode.app_rd_data_reg[71] (\\ui_rd_data0/p_95_out ),\n .\\not_strict_mode.app_rd_data_reg[73] (\\ui_rd_data0/p_90_out ),\n .\\not_strict_mode.app_rd_data_reg[75] (\\ui_rd_data0/p_91_out ),\n .\\not_strict_mode.app_rd_data_reg[77] (\\ui_rd_data0/p_92_out ),\n .\\not_strict_mode.app_rd_data_reg[79] (\\ui_rd_data0/p_87_out ),\n .\\not_strict_mode.app_rd_data_reg[7] (\\ui_rd_data0/p_123_out ),\n .\\not_strict_mode.app_rd_data_reg[81] (\\ui_rd_data0/p_88_out ),\n .\\not_strict_mode.app_rd_data_reg[83] (\\ui_rd_data0/p_89_out ),\n .\\not_strict_mode.app_rd_data_reg[85] (\\ui_rd_data0/p_84_out ),\n .\\not_strict_mode.app_rd_data_reg[87] (\\ui_rd_data0/p_85_out ),\n .\\not_strict_mode.app_rd_data_reg[89] (\\ui_rd_data0/p_86_out ),\n .\\not_strict_mode.app_rd_data_reg[91] (\\ui_rd_data0/p_81_out ),\n .\\not_strict_mode.app_rd_data_reg[93] (\\ui_rd_data0/p_82_out ),\n .\\not_strict_mode.app_rd_data_reg[95] (\\ui_rd_data0/p_83_out ),\n .\\not_strict_mode.app_rd_data_reg[97] (\\ui_rd_data0/p_78_out ),\n .\\not_strict_mode.app_rd_data_reg[99] (\\ui_rd_data0/p_79_out ),\n .\\not_strict_mode.app_rd_data_reg[9] (\\ui_rd_data0/p_124_out ),\n .p_28_out(\\mc0/bank_mach0/p_28_out ),\n .p_67_out(\\mc0/bank_mach0/p_67_out ),\n .pointer_we(\\ui_wr_data0/pointer_we ),\n .ram_init_done_r(ram_init_done_r),\n .rb_hit_busy_r_reg(u_ui_top_n_272),\n .rb_hit_busy_r_reg_0(u_ui_top_n_274),\n .rd_buf_we(\\ui_rd_data0/rd_buf_we ),\n .\\read_fifo.fifo_out_data_r_reg[7] ({rd_data_end,rd_data_addr,rd_data_offset}),\n .\\req_bank_r_lcl_reg[2] (bank),\n .\\req_bank_r_lcl_reg[2]_0 (\\mc0/p_2_in ),\n .\\req_bank_r_lcl_reg[2]_1 (\\mc0/req_bank_r_lcl ),\n .\\req_col_r_reg[9] (col),\n .\\req_data_buf_addr_r_reg[4] (data_buf_addr),\n .\\req_row_r_lcl_reg[14] (row),\n .reset_reg(reset_reg_n_0),\n .\\s_axi_rdata[255] (app_rd_data),\n .use_addr(use_addr),\n .w_cmd_rdy(w_cmd_rdy),\n .wready_reg_rep__1(\\axi_mc_w_channel_0/next_wdf_data ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_poc_edge_store\" *) \nmodule ddr3_ifmig_7series_v4_0_poc_edge_store\n (Q,\n \\rise_trail_center_offset_r_reg[3] ,\n E,\n \\tap_r_reg[5] ,\n CLK,\n run_polarity_r_reg,\n D);\n output [5:0]Q;\n output [5:0]\\rise_trail_center_offset_r_reg[3] ;\n input [0:0]E;\n input [5:0]\\tap_r_reg[5] ;\n input CLK;\n input [0:0]run_polarity_r_reg;\n input [5:0]D;\n\n wire CLK;\n wire [5:0]D;\n wire [0:0]E;\n wire [5:0]Q;\n wire [5:0]\\rise_trail_center_offset_r_reg[3] ;\n wire [0:0]run_polarity_r_reg;\n wire [5:0]\\tap_r_reg[5] ;\n\n FDRE #(\n .INIT(1'b0)) \n \\rise_lead_r_reg[0] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [0]),\n .Q(Q[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_lead_r_reg[1] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [1]),\n .Q(Q[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_lead_r_reg[2] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [2]),\n .Q(Q[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_lead_r_reg[3] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [3]),\n .Q(Q[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_lead_r_reg[4] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [4]),\n .Q(Q[4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_lead_r_reg[5] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [5]),\n .Q(Q[5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_trail_r_reg[0] \n (.C(CLK),\n .CE(run_polarity_r_reg),\n .D(D[0]),\n .Q(\\rise_trail_center_offset_r_reg[3] [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_trail_r_reg[1] \n (.C(CLK),\n .CE(run_polarity_r_reg),\n .D(D[1]),\n .Q(\\rise_trail_center_offset_r_reg[3] [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_trail_r_reg[2] \n (.C(CLK),\n .CE(run_polarity_r_reg),\n .D(D[2]),\n .Q(\\rise_trail_center_offset_r_reg[3] [2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_trail_r_reg[3] \n (.C(CLK),\n .CE(run_polarity_r_reg),\n .D(D[3]),\n .Q(\\rise_trail_center_offset_r_reg[3] [3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_trail_r_reg[4] \n (.C(CLK),\n .CE(run_polarity_r_reg),\n .D(D[4]),\n .Q(\\rise_trail_center_offset_r_reg[3] [4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_trail_r_reg[5] \n (.C(CLK),\n .CE(run_polarity_r_reg),\n .D(D[5]),\n .Q(\\rise_trail_center_offset_r_reg[3] [5]),\n .R(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_poc_edge_store\" *) \nmodule ddr3_ifmig_7series_v4_0_poc_edge_store_7\n (DI,\n \\center_diff_r_reg[5] ,\n \\window_center_r_reg[6] ,\n \\window_center_r_reg[6]_0 ,\n S,\n D,\n \\center_diff_r_reg[0] ,\n \\center_diff_r_reg[0]_0 ,\n \\center_diff_r_reg[0]_1 ,\n \\center_diff_r_reg[5]_0 ,\n \\center_diff_r_reg[1] ,\n \\window_center_r_reg[6]_1 ,\n \\window_center_r_reg[3] ,\n \\window_center_r_reg[0] ,\n \\window_center_r_reg[6]_2 ,\n \\center_diff_r_reg[3] ,\n \\center_diff_r_reg[3]_0 ,\n Q,\n center0_return3,\n use_noise_window,\n \\rise_trail_r_reg[5]_0 ,\n \\rise_lead_r_reg[5]_0 ,\n O,\n \\rise_trail_r_reg[3]_0 ,\n \\rise_lead_r_reg[0]_0 ,\n \\rise_lead_r_reg[4]_0 ,\n \\rise_trail_r_reg[4]_0 ,\n \\rise_trail_r_reg[1]_0 ,\n \\rise_trail_r_reg[2]_0 ,\n E,\n \\tap_r_reg[5] ,\n CLK,\n samps_zero_r_reg,\n \\tap_r_reg[4] );\n output [1:0]DI;\n output [0:0]\\center_diff_r_reg[5] ;\n output [5:0]\\window_center_r_reg[6] ;\n output [5:0]\\window_center_r_reg[6]_0 ;\n output [0:0]S;\n output [2:0]D;\n output \\center_diff_r_reg[0] ;\n output \\center_diff_r_reg[0]_0 ;\n output \\center_diff_r_reg[0]_1 ;\n output [0:0]\\center_diff_r_reg[5]_0 ;\n output \\center_diff_r_reg[1] ;\n output [0:0]\\window_center_r_reg[6]_1 ;\n output [2:0]\\window_center_r_reg[3] ;\n output [2:0]\\window_center_r_reg[0] ;\n output [1:0]\\window_center_r_reg[6]_2 ;\n output [0:0]\\center_diff_r_reg[3] ;\n output [0:0]\\center_diff_r_reg[3]_0 ;\n input [1:0]Q;\n input [3:0]center0_return3;\n input use_noise_window;\n input [3:0]\\rise_trail_r_reg[5]_0 ;\n input [3:0]\\rise_lead_r_reg[5]_0 ;\n input [0:0]O;\n input \\rise_trail_r_reg[3]_0 ;\n input \\rise_lead_r_reg[0]_0 ;\n input [1:0]\\rise_lead_r_reg[4]_0 ;\n input [1:0]\\rise_trail_r_reg[4]_0 ;\n input \\rise_trail_r_reg[1]_0 ;\n input \\rise_trail_r_reg[2]_0 ;\n input [0:0]E;\n input [5:0]\\tap_r_reg[5] ;\n input CLK;\n input [0:0]samps_zero_r_reg;\n input [5:0]\\tap_r_reg[4] ;\n\n wire CLK;\n wire [2:0]D;\n wire [1:0]DI;\n wire [0:0]E;\n wire [0:0]O;\n wire [1:0]Q;\n wire [0:0]S;\n wire [3:0]center0_return3;\n wire \\center_diff_r[5]_i_11_n_0 ;\n wire \\center_diff_r[5]_i_6_n_0 ;\n wire \\center_diff_r[5]_i_8_n_0 ;\n wire \\center_diff_r[5]_i_9_n_0 ;\n wire \\center_diff_r_reg[0] ;\n wire \\center_diff_r_reg[0]_0 ;\n wire \\center_diff_r_reg[0]_1 ;\n wire \\center_diff_r_reg[1] ;\n wire [0:0]\\center_diff_r_reg[3] ;\n wire [0:0]\\center_diff_r_reg[3]_0 ;\n wire [0:0]\\center_diff_r_reg[5] ;\n wire [0:0]\\center_diff_r_reg[5]_0 ;\n wire mod_sub1_return0_carry__0_i_3_n_0;\n wire \\rise_lead_r_reg[0]_0 ;\n wire [1:0]\\rise_lead_r_reg[4]_0 ;\n wire [3:0]\\rise_lead_r_reg[5]_0 ;\n wire \\rise_trail_r_reg[1]_0 ;\n wire \\rise_trail_r_reg[2]_0 ;\n wire \\rise_trail_r_reg[3]_0 ;\n wire [1:0]\\rise_trail_r_reg[4]_0 ;\n wire [3:0]\\rise_trail_r_reg[5]_0 ;\n wire [0:0]samps_zero_r_reg;\n wire [5:0]\\tap_r_reg[4] ;\n wire [5:0]\\tap_r_reg[5] ;\n wire use_noise_window;\n wire [2:0]\\window_center_r_reg[0] ;\n wire [2:0]\\window_center_r_reg[3] ;\n wire [5:0]\\window_center_r_reg[6] ;\n wire [5:0]\\window_center_r_reg[6]_0 ;\n wire [0:0]\\window_center_r_reg[6]_1 ;\n wire [1:0]\\window_center_r_reg[6]_2 ;\n\n LUT5 #(\n .INIT(32'hAAAA8000)) \n center0_return1__0_carry__0_i_1\n (.I0(Q[0]),\n .I1(center0_return3[2]),\n .I2(center0_return3[1]),\n .I3(center0_return3[0]),\n .I4(center0_return3[3]),\n .O(DI[1]));\n LUT3 #(\n .INIT(8'hB8)) \n center0_return1__0_carry__0_i_2\n (.I0(\\window_center_r_reg[6] [3]),\n .I1(use_noise_window),\n .I2(\\window_center_r_reg[6]_0 [3]),\n .O(DI[0]));\n LUT6 #(\n .INIT(64'h5F5F3FC0A0A03FC0)) \n center0_return1__0_carry__0_i_3\n (.I0(\\window_center_r_reg[6] [4]),\n .I1(\\window_center_r_reg[6]_0 [4]),\n .I2(Q[1]),\n .I3(\\window_center_r_reg[6]_0 [5]),\n .I4(use_noise_window),\n .I5(\\window_center_r_reg[6] [5]),\n .O(S));\n LUT3 #(\n .INIT(8'hB8)) \n center0_return1__0_carry_i_1\n (.I0(\\window_center_r_reg[6] [2]),\n .I1(use_noise_window),\n .I2(\\window_center_r_reg[6]_0 [2]),\n .O(\\window_center_r_reg[3] [2]));\n LUT3 #(\n .INIT(8'hB8)) \n center0_return1__0_carry_i_2\n (.I0(\\window_center_r_reg[6] [1]),\n .I1(use_noise_window),\n .I2(\\window_center_r_reg[6]_0 [1]),\n .O(\\window_center_r_reg[3] [1]));\n LUT3 #(\n .INIT(8'hB8)) \n center0_return1__0_carry_i_3\n (.I0(\\window_center_r_reg[6] [0]),\n .I1(use_noise_window),\n .I2(\\window_center_r_reg[6]_0 [0]),\n .O(\\window_center_r_reg[3] [0]));\n LUT3 #(\n .INIT(8'hB8)) \n center0_return1__1_carry__0_i_1\n (.I0(\\window_center_r_reg[6] [4]),\n .I1(use_noise_window),\n .I2(\\window_center_r_reg[6]_0 [4]),\n .O(\\window_center_r_reg[6]_2 [1]));\n LUT3 #(\n .INIT(8'hB8)) \n center0_return1__1_carry__0_i_2\n (.I0(\\window_center_r_reg[6] [3]),\n .I1(use_noise_window),\n .I2(\\window_center_r_reg[6]_0 [3]),\n .O(\\window_center_r_reg[6]_2 [0]));\n LUT3 #(\n .INIT(8'hB8)) \n center0_return1__1_carry__0_i_3\n (.I0(\\window_center_r_reg[6] [5]),\n .I1(use_noise_window),\n .I2(\\window_center_r_reg[6]_0 [5]),\n .O(\\window_center_r_reg[6]_1 ));\n LUT3 #(\n .INIT(8'hB8)) \n center0_return1__1_carry_i_1\n (.I0(\\window_center_r_reg[6] [2]),\n .I1(use_noise_window),\n .I2(\\window_center_r_reg[6]_0 [2]),\n .O(\\window_center_r_reg[0] [2]));\n LUT3 #(\n .INIT(8'hB8)) \n center0_return1__1_carry_i_2\n (.I0(\\window_center_r_reg[6] [1]),\n .I1(use_noise_window),\n .I2(\\window_center_r_reg[6]_0 [1]),\n .O(\\window_center_r_reg[0] [1]));\n LUT3 #(\n .INIT(8'hB8)) \n center0_return1__1_carry_i_3\n (.I0(\\window_center_r_reg[6] [0]),\n .I1(use_noise_window),\n .I2(\\window_center_r_reg[6]_0 [0]),\n .O(\\window_center_r_reg[0] [0]));\n LUT6 #(\n .INIT(64'hFFBFBBBB00808888)) \n \\center_diff_r[0]_i_1 \n (.I0(O),\n .I1(\\center_diff_r_reg[0] ),\n .I2(\\center_diff_r_reg[0]_0 ),\n .I3(\\rise_trail_r_reg[3]_0 ),\n .I4(\\center_diff_r_reg[0]_1 ),\n .I5(\\rise_lead_r_reg[0]_0 ),\n .O(D[0]));\n LUT6 #(\n .INIT(64'hFFBFBBBB00808888)) \n \\center_diff_r[4]_i_1 \n (.I0(\\rise_lead_r_reg[4]_0 [0]),\n .I1(\\center_diff_r_reg[0] ),\n .I2(\\center_diff_r_reg[0]_0 ),\n .I3(\\rise_trail_r_reg[3]_0 ),\n .I4(\\center_diff_r_reg[0]_1 ),\n .I5(\\rise_trail_r_reg[4]_0 [0]),\n .O(D[1]));\n LUT6 #(\n .INIT(64'hFFBFBBBB00808888)) \n \\center_diff_r[5]_i_1 \n (.I0(\\rise_lead_r_reg[4]_0 [1]),\n .I1(\\center_diff_r_reg[0] ),\n .I2(\\center_diff_r_reg[0]_0 ),\n .I3(\\rise_trail_r_reg[3]_0 ),\n .I4(\\center_diff_r_reg[0]_1 ),\n .I5(\\rise_trail_r_reg[4]_0 [1]),\n .O(D[2]));\n LUT5 #(\n .INIT(32'h335ACC5A)) \n \\center_diff_r[5]_i_11 \n (.I0(\\window_center_r_reg[6]_0 [3]),\n .I1(\\window_center_r_reg[6] [3]),\n .I2(\\rise_lead_r_reg[5]_0 [1]),\n .I3(use_noise_window),\n .I4(\\rise_trail_r_reg[5]_0 [1]),\n .O(\\center_diff_r[5]_i_11_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair439\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\center_diff_r[5]_i_12 \n (.I0(\\window_center_r_reg[6] [4]),\n .I1(use_noise_window),\n .I2(\\window_center_r_reg[6]_0 [4]),\n .O(\\center_diff_r_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair438\" *) \n LUT5 #(\n .INIT(32'hCCAFFFAF)) \n \\center_diff_r[5]_i_2 \n (.I0(\\window_center_r_reg[6]_0 [5]),\n .I1(\\window_center_r_reg[6] [5]),\n .I2(\\rise_lead_r_reg[5]_0 [3]),\n .I3(use_noise_window),\n .I4(\\rise_trail_r_reg[5]_0 [3]),\n .O(\\center_diff_r_reg[0] ));\n LUT6 #(\n .INIT(64'hFFFFFFFFB200FFB2)) \n \\center_diff_r[5]_i_3 \n (.I0(\\center_diff_r[5]_i_6_n_0 ),\n .I1(\\rise_trail_r_reg[1]_0 ),\n .I2(\\center_diff_r[5]_i_8_n_0 ),\n .I3(\\center_diff_r[5]_i_9_n_0 ),\n .I4(\\rise_trail_r_reg[2]_0 ),\n .I5(\\center_diff_r[5]_i_11_n_0 ),\n .O(\\center_diff_r_reg[0]_0 ));\n LUT6 #(\n .INIT(64'h00000000FF77CF47)) \n \\center_diff_r[5]_i_5 \n (.I0(\\window_center_r_reg[6] [4]),\n .I1(use_noise_window),\n .I2(\\window_center_r_reg[6]_0 [4]),\n .I3(\\rise_trail_r_reg[5]_0 [2]),\n .I4(\\rise_lead_r_reg[5]_0 [2]),\n .I5(mod_sub1_return0_carry__0_i_3_n_0),\n .O(\\center_diff_r_reg[0]_1 ));\n LUT3 #(\n .INIT(8'hB8)) \n \\center_diff_r[5]_i_6 \n (.I0(\\window_center_r_reg[6] [1]),\n .I1(use_noise_window),\n .I2(\\window_center_r_reg[6]_0 [1]),\n .O(\\center_diff_r[5]_i_6_n_0 ));\n LUT5 #(\n .INIT(32'h000ACC0A)) \n \\center_diff_r[5]_i_8 \n (.I0(\\window_center_r_reg[6]_0 [0]),\n .I1(\\window_center_r_reg[6] [0]),\n .I2(\\rise_lead_r_reg[5]_0 [0]),\n .I3(use_noise_window),\n .I4(\\rise_trail_r_reg[5]_0 [0]),\n .O(\\center_diff_r[5]_i_8_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair439\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\center_diff_r[5]_i_9 \n (.I0(\\window_center_r_reg[6] [2]),\n .I1(use_noise_window),\n .I2(\\window_center_r_reg[6]_0 [2]),\n .O(\\center_diff_r[5]_i_9_n_0 ));\n LUT5 #(\n .INIT(32'h478B74B8)) \n mod_sub1_return0_carry__0_i_1\n (.I0(\\window_center_r_reg[6] [4]),\n .I1(use_noise_window),\n .I2(\\window_center_r_reg[6]_0 [4]),\n .I3(\\rise_trail_r_reg[5]_0 [2]),\n .I4(\\rise_lead_r_reg[5]_0 [2]),\n .O(\\center_diff_r_reg[5] ));\n LUT6 #(\n .INIT(64'h555595955A559A95)) \n mod_sub1_return0_carry__0_i_2\n (.I0(mod_sub1_return0_carry__0_i_3_n_0),\n .I1(\\window_center_r_reg[6] [4]),\n .I2(use_noise_window),\n .I3(\\window_center_r_reg[6]_0 [4]),\n .I4(\\rise_trail_r_reg[5]_0 [2]),\n .I5(\\rise_lead_r_reg[5]_0 [2]),\n .O(\\center_diff_r_reg[5]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair438\" *) \n LUT5 #(\n .INIT(32'h335ACC5A)) \n mod_sub1_return0_carry__0_i_3\n (.I0(\\window_center_r_reg[6]_0 [5]),\n .I1(\\window_center_r_reg[6] [5]),\n .I2(\\rise_lead_r_reg[5]_0 [3]),\n .I3(use_noise_window),\n .I4(\\rise_trail_r_reg[5]_0 [3]),\n .O(mod_sub1_return0_carry__0_i_3_n_0));\n LUT3 #(\n .INIT(8'hB8)) \n mod_sub1_return0_carry_i_1\n (.I0(\\window_center_r_reg[6] [3]),\n .I1(use_noise_window),\n .I2(\\window_center_r_reg[6]_0 [3]),\n .O(\\center_diff_r_reg[3]_0 ));\n LUT5 #(\n .INIT(32'h335ACC5A)) \n mod_sub1_return0_carry_i_5\n (.I0(\\window_center_r_reg[6]_0 [3]),\n .I1(\\window_center_r_reg[6] [3]),\n .I2(\\rise_lead_r_reg[5]_0 [1]),\n .I3(use_noise_window),\n .I4(\\rise_trail_r_reg[5]_0 [1]),\n .O(\\center_diff_r_reg[3] ));\n FDRE #(\n .INIT(1'b0)) \n \\rise_lead_r_reg[0] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [0]),\n .Q(\\window_center_r_reg[6] [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_lead_r_reg[1] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [1]),\n .Q(\\window_center_r_reg[6] [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_lead_r_reg[2] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [2]),\n .Q(\\window_center_r_reg[6] [2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_lead_r_reg[3] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [3]),\n .Q(\\window_center_r_reg[6] [3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_lead_r_reg[4] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [4]),\n .Q(\\window_center_r_reg[6] [4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_lead_r_reg[5] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [5]),\n .Q(\\window_center_r_reg[6] [5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_trail_r_reg[0] \n (.C(CLK),\n .CE(samps_zero_r_reg),\n .D(\\tap_r_reg[4] [0]),\n .Q(\\window_center_r_reg[6]_0 [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_trail_r_reg[1] \n (.C(CLK),\n .CE(samps_zero_r_reg),\n .D(\\tap_r_reg[4] [1]),\n .Q(\\window_center_r_reg[6]_0 [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_trail_r_reg[2] \n (.C(CLK),\n .CE(samps_zero_r_reg),\n .D(\\tap_r_reg[4] [2]),\n .Q(\\window_center_r_reg[6]_0 [2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_trail_r_reg[3] \n (.C(CLK),\n .CE(samps_zero_r_reg),\n .D(\\tap_r_reg[4] [3]),\n .Q(\\window_center_r_reg[6]_0 [3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_trail_r_reg[4] \n (.C(CLK),\n .CE(samps_zero_r_reg),\n .D(\\tap_r_reg[4] [4]),\n .Q(\\window_center_r_reg[6]_0 [4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_trail_r_reg[5] \n (.C(CLK),\n .CE(samps_zero_r_reg),\n .D(\\tap_r_reg[4] [5]),\n .Q(\\window_center_r_reg[6]_0 [5]),\n .R(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_poc_edge_store\" *) \nmodule ddr3_ifmig_7series_v4_0_poc_edge_store_8\n (trailing_edge00_in,\n D,\n \\center_diff_r_reg[1] ,\n \\mmcm_init_trail_reg[5] ,\n \\mmcm_init_lead_reg[5] ,\n \\center_diff_r_reg[5] ,\n \\center_diff_r_reg[3] ,\n \\center_diff_r_reg[0] ,\n \\center_diff_r_reg[0]_0 ,\n \\center_diff_r_reg[3]_0 ,\n \\center_diff_r_reg[5]_0 ,\n Q,\n \\tap_r_reg[5] ,\n S,\n DI,\n \\tap_r_reg[5]_0 ,\n O,\n \\rise_trail_r_reg[5]_0 ,\n \\rise_lead_r_reg[1]_0 ,\n \\rise_lead_r_reg[4]_0 ,\n \\rise_trail_r_reg[3]_0 ,\n \\rise_lead_r_reg[3]_0 ,\n use_noise_window,\n \\rise_lead_r_reg[4]_1 ,\n \\rise_lead_r_reg[5]_0 ,\n \\rise_trail_r_reg[5]_1 ,\n E,\n CLK,\n samps_zero_r_reg,\n \\tap_r_reg[4] );\n output [4:0]trailing_edge00_in;\n output [2:0]D;\n output \\center_diff_r_reg[1] ;\n output [5:0]\\mmcm_init_trail_reg[5] ;\n output [5:0]\\mmcm_init_lead_reg[5] ;\n output [0:0]\\center_diff_r_reg[5] ;\n output [3:0]\\center_diff_r_reg[3] ;\n output \\center_diff_r_reg[0] ;\n output \\center_diff_r_reg[0]_0 ;\n output [2:0]\\center_diff_r_reg[3]_0 ;\n output [0:0]\\center_diff_r_reg[5]_0 ;\n input [0:0]Q;\n input [5:0]\\tap_r_reg[5] ;\n input [3:0]S;\n input [0:0]DI;\n input [1:0]\\tap_r_reg[5]_0 ;\n input [2:0]O;\n input \\rise_trail_r_reg[5]_0 ;\n input \\rise_lead_r_reg[1]_0 ;\n input \\rise_lead_r_reg[4]_0 ;\n input [2:0]\\rise_trail_r_reg[3]_0 ;\n input [0:0]\\rise_lead_r_reg[3]_0 ;\n input use_noise_window;\n input \\rise_lead_r_reg[4]_1 ;\n input [0:0]\\rise_lead_r_reg[5]_0 ;\n input [0:0]\\rise_trail_r_reg[5]_1 ;\n input [0:0]E;\n input CLK;\n input [0:0]samps_zero_r_reg;\n input [5:0]\\tap_r_reg[4] ;\n\n wire CLK;\n wire [2:0]D;\n wire [0:0]DI;\n wire [0:0]E;\n wire [2:0]O;\n wire [0:0]Q;\n wire [3:0]S;\n wire \\center_diff_r[5]_i_13_n_0 ;\n wire \\center_diff_r_reg[0] ;\n wire \\center_diff_r_reg[0]_0 ;\n wire \\center_diff_r_reg[1] ;\n wire [3:0]\\center_diff_r_reg[3] ;\n wire [2:0]\\center_diff_r_reg[3]_0 ;\n wire [0:0]\\center_diff_r_reg[5] ;\n wire [0:0]\\center_diff_r_reg[5]_0 ;\n wire [5:0]\\mmcm_init_lead_reg[5] ;\n wire [5:0]\\mmcm_init_trail_reg[5] ;\n wire \\rise_lead_r_reg[1]_0 ;\n wire [0:0]\\rise_lead_r_reg[3]_0 ;\n wire \\rise_lead_r_reg[4]_0 ;\n wire \\rise_lead_r_reg[4]_1 ;\n wire [0:0]\\rise_lead_r_reg[5]_0 ;\n wire [2:0]\\rise_trail_r_reg[3]_0 ;\n wire \\rise_trail_r_reg[5]_0 ;\n wire [0:0]\\rise_trail_r_reg[5]_1 ;\n wire [0:0]samps_zero_r_reg;\n wire [5:0]\\tap_r_reg[4] ;\n wire [5:0]\\tap_r_reg[5] ;\n wire [1:0]\\tap_r_reg[5]_0 ;\n wire [4:0]trailing_edge00_in;\n wire \\trailing_edge0_inferred__0/i__carry__0_n_3 ;\n wire \\trailing_edge0_inferred__0/i__carry_n_0 ;\n wire \\trailing_edge0_inferred__0/i__carry_n_1 ;\n wire \\trailing_edge0_inferred__0/i__carry_n_2 ;\n wire \\trailing_edge0_inferred__0/i__carry_n_3 ;\n wire use_noise_window;\n wire [0:0]\\NLW_trailing_edge0_inferred__0/i__carry_O_UNCONNECTED ;\n wire [3:1]\\NLW_trailing_edge0_inferred__0/i__carry__0_CO_UNCONNECTED ;\n wire [3:2]\\NLW_trailing_edge0_inferred__0/i__carry__0_O_UNCONNECTED ;\n\n LUT6 #(\n .INIT(64'hFFBFBBBB00808888)) \n \\center_diff_r[1]_i_1 \n (.I0(O[0]),\n .I1(\\rise_trail_r_reg[5]_0 ),\n .I2(\\rise_lead_r_reg[1]_0 ),\n .I3(\\center_diff_r_reg[1] ),\n .I4(\\rise_lead_r_reg[4]_0 ),\n .I5(\\rise_trail_r_reg[3]_0 [0]),\n .O(D[0]));\n LUT6 #(\n .INIT(64'hFFBFBBBB00808888)) \n \\center_diff_r[2]_i_1 \n (.I0(O[1]),\n .I1(\\rise_trail_r_reg[5]_0 ),\n .I2(\\rise_lead_r_reg[1]_0 ),\n .I3(\\center_diff_r_reg[1] ),\n .I4(\\rise_lead_r_reg[4]_0 ),\n .I5(\\rise_trail_r_reg[3]_0 [1]),\n .O(D[1]));\n LUT6 #(\n .INIT(64'hFFBFBBBB00808888)) \n \\center_diff_r[3]_i_1 \n (.I0(O[2]),\n .I1(\\rise_trail_r_reg[5]_0 ),\n .I2(\\rise_lead_r_reg[1]_0 ),\n .I3(\\center_diff_r_reg[1] ),\n .I4(\\rise_lead_r_reg[4]_0 ),\n .I5(\\rise_trail_r_reg[3]_0 [2]),\n .O(D[2]));\n (* SOFT_HLUTNM = \"soft_lutpair440\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\center_diff_r[5]_i_10 \n (.I0(\\mmcm_init_trail_reg[5] [2]),\n .I1(use_noise_window),\n .I2(\\mmcm_init_lead_reg[5] [2]),\n .O(\\center_diff_r_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair440\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\center_diff_r[5]_i_13 \n (.I0(\\mmcm_init_trail_reg[5] [4]),\n .I1(use_noise_window),\n .I2(\\mmcm_init_lead_reg[5] [4]),\n .O(\\center_diff_r[5]_i_13_n_0 ));\n LUT6 #(\n .INIT(64'h4540FFFF45404540)) \n \\center_diff_r[5]_i_4 \n (.I0(\\rise_lead_r_reg[3]_0 ),\n .I1(\\mmcm_init_trail_reg[5] [3]),\n .I2(use_noise_window),\n .I3(\\mmcm_init_lead_reg[5] [3]),\n .I4(\\rise_lead_r_reg[4]_1 ),\n .I5(\\center_diff_r[5]_i_13_n_0 ),\n .O(\\center_diff_r_reg[1] ));\n LUT3 #(\n .INIT(8'hB8)) \n \\center_diff_r[5]_i_7 \n (.I0(\\mmcm_init_trail_reg[5] [1]),\n .I1(use_noise_window),\n .I2(\\mmcm_init_lead_reg[5] [1]),\n .O(\\center_diff_r_reg[0]_0 ));\n LUT3 #(\n .INIT(8'hB8)) \n mod_sub1_return0__0_carry__0_i_1\n (.I0(\\mmcm_init_trail_reg[5] [4]),\n .I1(use_noise_window),\n .I2(\\mmcm_init_lead_reg[5] [4]),\n .O(\\center_diff_r_reg[5]_0 ));\n LUT5 #(\n .INIT(32'hB8748B47)) \n mod_sub1_return0__0_carry__0_i_2\n (.I0(\\mmcm_init_trail_reg[5] [5]),\n .I1(use_noise_window),\n .I2(\\mmcm_init_lead_reg[5] [5]),\n .I3(\\rise_lead_r_reg[5]_0 ),\n .I4(\\rise_trail_r_reg[5]_1 ),\n .O(\\center_diff_r_reg[5] ));\n LUT3 #(\n .INIT(8'hB8)) \n mod_sub1_return0__0_carry_i_1\n (.I0(\\mmcm_init_trail_reg[5] [3]),\n .I1(use_noise_window),\n .I2(\\mmcm_init_lead_reg[5] [3]),\n .O(\\center_diff_r_reg[3] [3]));\n LUT3 #(\n .INIT(8'hB8)) \n mod_sub1_return0__0_carry_i_2\n (.I0(\\mmcm_init_trail_reg[5] [2]),\n .I1(use_noise_window),\n .I2(\\mmcm_init_lead_reg[5] [2]),\n .O(\\center_diff_r_reg[3] [2]));\n LUT3 #(\n .INIT(8'hB8)) \n mod_sub1_return0__0_carry_i_3\n (.I0(\\mmcm_init_trail_reg[5] [1]),\n .I1(use_noise_window),\n .I2(\\mmcm_init_lead_reg[5] [1]),\n .O(\\center_diff_r_reg[3] [1]));\n LUT3 #(\n .INIT(8'hB8)) \n mod_sub1_return0__0_carry_i_4\n (.I0(\\mmcm_init_trail_reg[5] [0]),\n .I1(use_noise_window),\n .I2(\\mmcm_init_lead_reg[5] [0]),\n .O(\\center_diff_r_reg[3] [0]));\n LUT3 #(\n .INIT(8'hB8)) \n mod_sub1_return0_carry_i_2\n (.I0(\\mmcm_init_trail_reg[5] [2]),\n .I1(use_noise_window),\n .I2(\\mmcm_init_lead_reg[5] [2]),\n .O(\\center_diff_r_reg[3]_0 [2]));\n LUT3 #(\n .INIT(8'hB8)) \n mod_sub1_return0_carry_i_3\n (.I0(\\mmcm_init_trail_reg[5] [1]),\n .I1(use_noise_window),\n .I2(\\mmcm_init_lead_reg[5] [1]),\n .O(\\center_diff_r_reg[3]_0 [1]));\n LUT3 #(\n .INIT(8'hB8)) \n mod_sub1_return0_carry_i_4\n (.I0(\\mmcm_init_trail_reg[5] [0]),\n .I1(use_noise_window),\n .I2(\\mmcm_init_lead_reg[5] [0]),\n .O(\\center_diff_r_reg[3]_0 [0]));\n FDRE #(\n .INIT(1'b0)) \n \\rise_lead_r_reg[0] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [0]),\n .Q(\\mmcm_init_lead_reg[5] [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_lead_r_reg[1] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [1]),\n .Q(\\mmcm_init_lead_reg[5] [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_lead_r_reg[2] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [2]),\n .Q(\\mmcm_init_lead_reg[5] [2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_lead_r_reg[3] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [3]),\n .Q(\\mmcm_init_lead_reg[5] [3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_lead_r_reg[4] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [4]),\n .Q(\\mmcm_init_lead_reg[5] [4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_lead_r_reg[5] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [5]),\n .Q(\\mmcm_init_lead_reg[5] [5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_trail_r_reg[0] \n (.C(CLK),\n .CE(samps_zero_r_reg),\n .D(\\tap_r_reg[4] [0]),\n .Q(\\mmcm_init_trail_reg[5] [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_trail_r_reg[1] \n (.C(CLK),\n .CE(samps_zero_r_reg),\n .D(\\tap_r_reg[4] [1]),\n .Q(\\mmcm_init_trail_reg[5] [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_trail_r_reg[2] \n (.C(CLK),\n .CE(samps_zero_r_reg),\n .D(\\tap_r_reg[4] [2]),\n .Q(\\mmcm_init_trail_reg[5] [2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_trail_r_reg[3] \n (.C(CLK),\n .CE(samps_zero_r_reg),\n .D(\\tap_r_reg[4] [3]),\n .Q(\\mmcm_init_trail_reg[5] [3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_trail_r_reg[4] \n (.C(CLK),\n .CE(samps_zero_r_reg),\n .D(\\tap_r_reg[4] [4]),\n .Q(\\mmcm_init_trail_reg[5] [4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_trail_r_reg[5] \n (.C(CLK),\n .CE(samps_zero_r_reg),\n .D(\\tap_r_reg[4] [5]),\n .Q(\\mmcm_init_trail_reg[5] [5]),\n .R(1'b0));\n CARRY4 \\trailing_edge0_inferred__0/i__carry \n (.CI(1'b0),\n .CO({\\trailing_edge0_inferred__0/i__carry_n_0 ,\\trailing_edge0_inferred__0/i__carry_n_1 ,\\trailing_edge0_inferred__0/i__carry_n_2 ,\\trailing_edge0_inferred__0/i__carry_n_3 }),\n .CYINIT(1'b1),\n .DI({Q,\\tap_r_reg[5] [2:0]}),\n .O({trailing_edge00_in[2:0],\\NLW_trailing_edge0_inferred__0/i__carry_O_UNCONNECTED [0]}),\n .S(S));\n CARRY4 \\trailing_edge0_inferred__0/i__carry__0 \n (.CI(\\trailing_edge0_inferred__0/i__carry_n_0 ),\n .CO({\\NLW_trailing_edge0_inferred__0/i__carry__0_CO_UNCONNECTED [3:1],\\trailing_edge0_inferred__0/i__carry__0_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,DI}),\n .O({\\NLW_trailing_edge0_inferred__0/i__carry__0_O_UNCONNECTED [3:2],trailing_edge00_in[4:3]}),\n .S({1'b0,1'b0,\\tap_r_reg[5]_0 }));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_poc_meta\" *) \nmodule ddr3_ifmig_7series_v4_0_poc_meta\n (detect_done_r_reg,\n \\sm_r_reg[1] ,\n poc_backup_r_reg_0,\n run_polarity_held_r,\n Q,\n center_return3,\n \\edge_diff_r_reg[0]_0 ,\n center0_return3,\n O,\n \\center_diff_r_reg[5]_0 ,\n \\center_diff_r_reg[3]_0 ,\n \\center_diff_r_reg[5]_1 ,\n \\diff_r_reg[7]_0 ,\n \\diff_r_reg[7]_1 ,\n \\edge_center_r_reg[6]_0 ,\n \\prev_r_reg[0]_0 ,\n \\prev_r_reg[0]_1 ,\n \\prev_r_reg[2]_0 ,\n \\window_center_r_reg[6]_0 ,\n CLK,\n samps_zero_r_reg,\n samps_zero_r_reg_0,\n S,\n \\rise_lead_center_offset_r_reg[4]_0 ,\n \\rise_lead_center_offset_r_reg[2]_0 ,\n DI,\n \\edge_diff_r_reg[4]_0 ,\n \\rise_trail_center_offset_r_reg[2]_0 ,\n \\rise_lead_center_offset_r_reg[4]_1 ,\n \\rise_trail_center_offset_r_reg[3]_0 ,\n \\rise_trail_center_offset_r_reg[5]_0 ,\n \\rise_lead_r_reg[2] ,\n \\rise_trail_r_reg[2] ,\n \\rise_lead_r_reg[4] ,\n \\rise_lead_r_reg[5] ,\n \\rise_lead_r_reg[2]_0 ,\n \\rise_trail_r_reg[2]_0 ,\n \\center_diff_r_reg[4]_0 ,\n \\rise_lead_r_reg[4]_0 ,\n \\rise_lead_r_reg[3] ,\n \\rise_trail_r_reg[3] ,\n \\rise_lead_r_reg[4]_1 ,\n \\rise_lead_r_reg[4]_2 ,\n \\rise_trail_r_reg[3]_0 ,\n \\rise_lead_r_reg[3]_0 ,\n \\rise_trail_r_reg[4] ,\n \\rise_trail_r_reg[5] ,\n \\edge_center_r_reg[6]_1 ,\n \\window_center_r_reg[6]_1 ,\n \\edge_center_r_reg[3]_0 ,\n \\edge_center_r_reg[5]_0 ,\n \\window_center_r_reg[6]_2 ,\n \\edge_center_r_reg[0]_0 ,\n \\edge_center_r_reg[3]_1 ,\n \\edge_center_r_reg[6]_2 ,\n ocd_ktap_right_r_reg,\n ocd_ktap_left_r_reg,\n \\run_ends_r_reg[1]_0 ,\n rstdiv0_sync_r1_reg_rep__20,\n ocd_ktap_left_r_reg_0,\n ocd_edge_detect_rdy_r_reg,\n \\diff_r_reg[2]_0 ,\n run_too_small_r_reg,\n D,\n \\rise_lead_r_reg[3]_1 ,\n \\rise_trail_r_reg[3]_1 ,\n \\rise_trail_center_offset_r_reg[0]_0 );\n output detect_done_r_reg;\n output \\sm_r_reg[1] ;\n output poc_backup_r_reg_0;\n output run_polarity_held_r;\n output [5:0]Q;\n output [3:0]center_return3;\n output [5:0]\\edge_diff_r_reg[0]_0 ;\n output [3:0]center0_return3;\n output [3:0]O;\n output [1:0]\\center_diff_r_reg[5]_0 ;\n output [2:0]\\center_diff_r_reg[3]_0 ;\n output [1:0]\\center_diff_r_reg[5]_1 ;\n output [6:0]\\diff_r_reg[7]_0 ;\n output [6:0]\\diff_r_reg[7]_1 ;\n output [4:0]\\edge_center_r_reg[6]_0 ;\n output \\prev_r_reg[0]_0 ;\n output \\prev_r_reg[0]_1 ;\n output [2:0]\\prev_r_reg[2]_0 ;\n output [4:0]\\window_center_r_reg[6]_0 ;\n input CLK;\n input samps_zero_r_reg;\n input samps_zero_r_reg_0;\n input [2:0]S;\n input [1:0]\\rise_lead_center_offset_r_reg[4]_0 ;\n input [2:0]\\rise_lead_center_offset_r_reg[2]_0 ;\n input [0:0]DI;\n input [1:0]\\edge_diff_r_reg[4]_0 ;\n input [2:0]\\rise_trail_center_offset_r_reg[2]_0 ;\n input [1:0]\\rise_lead_center_offset_r_reg[4]_1 ;\n input [3:0]\\rise_trail_center_offset_r_reg[3]_0 ;\n input [1:0]\\rise_trail_center_offset_r_reg[5]_0 ;\n input [2:0]\\rise_lead_r_reg[2] ;\n input [2:0]\\rise_trail_r_reg[2] ;\n input [1:0]\\rise_lead_r_reg[4] ;\n input [2:0]\\rise_lead_r_reg[5] ;\n input [2:0]\\rise_lead_r_reg[2]_0 ;\n input [2:0]\\rise_trail_r_reg[2]_0 ;\n input [1:0]\\center_diff_r_reg[4]_0 ;\n input [2:0]\\rise_lead_r_reg[4]_0 ;\n input [3:0]\\rise_lead_r_reg[3] ;\n input [3:0]\\rise_trail_r_reg[3] ;\n input [0:0]\\rise_lead_r_reg[4]_1 ;\n input [1:0]\\rise_lead_r_reg[4]_2 ;\n input [3:0]\\rise_trail_r_reg[3]_0 ;\n input [3:0]\\rise_lead_r_reg[3]_0 ;\n input [0:0]\\rise_trail_r_reg[4] ;\n input [1:0]\\rise_trail_r_reg[5] ;\n input [3:0]\\edge_center_r_reg[6]_1 ;\n input [3:0]\\window_center_r_reg[6]_1 ;\n input [3:0]\\edge_center_r_reg[3]_0 ;\n input [1:0]\\edge_center_r_reg[5]_0 ;\n input [3:0]\\window_center_r_reg[6]_2 ;\n input [0:0]\\edge_center_r_reg[0]_0 ;\n input [3:0]\\edge_center_r_reg[3]_1 ;\n input [2:0]\\edge_center_r_reg[6]_2 ;\n input ocd_ktap_right_r_reg;\n input ocd_ktap_left_r_reg;\n input \\run_ends_r_reg[1]_0 ;\n input rstdiv0_sync_r1_reg_rep__20;\n input ocd_ktap_left_r_reg_0;\n input ocd_edge_detect_rdy_r_reg;\n input \\diff_r_reg[2]_0 ;\n input run_too_small_r_reg;\n input [5:0]D;\n input [5:0]\\rise_lead_r_reg[3]_1 ;\n input [5:0]\\rise_trail_r_reg[3]_1 ;\n input \\rise_trail_center_offset_r_reg[0]_0 ;\n\n wire CLK;\n wire [5:0]D;\n wire [0:0]DI;\n wire [3:0]O;\n wire [5:0]Q;\n wire [2:0]S;\n wire [6:0]center0_return0;\n wire center0_return1__0_carry__0_n_2;\n wire center0_return1__0_carry__0_n_3;\n wire center0_return1__0_carry_i_7_n_0;\n wire center0_return1__0_carry_n_0;\n wire center0_return1__0_carry_n_1;\n wire center0_return1__0_carry_n_2;\n wire center0_return1__0_carry_n_3;\n wire center0_return1__1_carry__0_n_2;\n wire center0_return1__1_carry__0_n_3;\n wire center0_return1__1_carry_i_7_n_0;\n wire center0_return1__1_carry_n_0;\n wire center0_return1__1_carry_n_1;\n wire center0_return1__1_carry_n_2;\n wire center0_return1__1_carry_n_3;\n wire [3:0]center0_return3;\n wire [2:0]\\center_diff_r_reg[3]_0 ;\n wire [1:0]\\center_diff_r_reg[4]_0 ;\n wire [1:0]\\center_diff_r_reg[5]_0 ;\n wire [1:0]\\center_diff_r_reg[5]_1 ;\n wire \\center_diff_r_reg_n_0_[0] ;\n wire [6:0]center_return0;\n wire center_return1__0_carry__0_i_1_n_0;\n wire center_return1__0_carry__0_n_2;\n wire center_return1__0_carry__0_n_3;\n wire center_return1__0_carry_i_4_n_0;\n wire center_return1__0_carry_n_0;\n wire center_return1__0_carry_n_1;\n wire center_return1__0_carry_n_2;\n wire center_return1__0_carry_n_3;\n wire center_return1__1_carry__0_i_1_n_0;\n wire center_return1__1_carry__0_n_2;\n wire center_return1__1_carry__0_n_3;\n wire center_return1__1_carry_i_4_n_0;\n wire center_return1__1_carry_n_0;\n wire center_return1__1_carry_n_1;\n wire center_return1__1_carry_n_2;\n wire center_return1__1_carry_n_3;\n wire [3:0]center_return3;\n wire detect_done_r_reg;\n wire [0:0]diff;\n wire [7:0]diff_ns;\n wire [7:0]diff_ns0;\n wire [6:1]diff_ns00_in;\n wire diff_ns0_carry__0_n_1;\n wire diff_ns0_carry__0_n_2;\n wire diff_ns0_carry__0_n_3;\n wire diff_ns0_carry_n_0;\n wire diff_ns0_carry_n_1;\n wire diff_ns0_carry_n_2;\n wire diff_ns0_carry_n_3;\n wire \\diff_ns0_inferred__0/i__carry__0_n_0 ;\n wire \\diff_ns0_inferred__0/i__carry__0_n_2 ;\n wire \\diff_ns0_inferred__0/i__carry__0_n_3 ;\n wire \\diff_ns0_inferred__0/i__carry_n_0 ;\n wire \\diff_ns0_inferred__0/i__carry_n_1 ;\n wire \\diff_ns0_inferred__0/i__carry_n_2 ;\n wire \\diff_ns0_inferred__0/i__carry_n_3 ;\n wire diff_ns1;\n wire diff_ns1_carry_n_1;\n wire diff_ns1_carry_n_2;\n wire diff_ns1_carry_n_3;\n wire \\diff_r_reg[2]_0 ;\n wire [6:0]\\diff_r_reg[7]_0 ;\n wire [6:0]\\diff_r_reg[7]_1 ;\n wire \\diff_r_reg_n_0_[3] ;\n wire \\diff_r_reg_n_0_[4] ;\n wire \\diff_r_reg_n_0_[5] ;\n wire \\diff_r_reg_n_0_[6] ;\n wire \\diff_r_reg_n_0_[7] ;\n wire diffs_eq_ns;\n wire diffs_eq_r;\n wire done_ns;\n wire edge_aligned_ns;\n wire edge_aligned_r_i_2_n_0;\n wire edge_aligned_r_i_3_n_0;\n wire [0:0]\\edge_center_r_reg[0]_0 ;\n wire [3:0]\\edge_center_r_reg[3]_0 ;\n wire [3:0]\\edge_center_r_reg[3]_1 ;\n wire [1:0]\\edge_center_r_reg[5]_0 ;\n wire [4:0]\\edge_center_r_reg[6]_0 ;\n wire [3:0]\\edge_center_r_reg[6]_1 ;\n wire [2:0]\\edge_center_r_reg[6]_2 ;\n wire \\edge_diff_r[5]_i_2_n_0 ;\n wire \\edge_diff_r[5]_i_3_n_0 ;\n wire [5:0]\\edge_diff_r_reg[0]_0 ;\n wire [1:0]\\edge_diff_r_reg[4]_0 ;\n wire mod_sub1_return0__0_carry__0_n_3;\n wire mod_sub1_return0__0_carry_n_0;\n wire mod_sub1_return0__0_carry_n_1;\n wire mod_sub1_return0__0_carry_n_2;\n wire mod_sub1_return0__0_carry_n_3;\n wire mod_sub1_return0_carry__0_n_3;\n wire mod_sub1_return0_carry_n_0;\n wire mod_sub1_return0_carry_n_1;\n wire mod_sub1_return0_carry_n_2;\n wire mod_sub1_return0_carry_n_3;\n wire [5:0]mod_sub_return;\n wire mod_sub_return0__0_carry__0_n_3;\n wire mod_sub_return0__0_carry__0_n_6;\n wire mod_sub_return0__0_carry__0_n_7;\n wire mod_sub_return0__0_carry_n_0;\n wire mod_sub_return0__0_carry_n_1;\n wire mod_sub_return0__0_carry_n_2;\n wire mod_sub_return0__0_carry_n_3;\n wire mod_sub_return0__0_carry_n_4;\n wire mod_sub_return0__0_carry_n_5;\n wire mod_sub_return0__0_carry_n_6;\n wire mod_sub_return0_carry__0_i_1_n_0;\n wire mod_sub_return0_carry__0_n_3;\n wire mod_sub_return0_carry__0_n_6;\n wire mod_sub_return0_carry__0_n_7;\n wire mod_sub_return0_carry_i_1_n_0;\n wire mod_sub_return0_carry_n_0;\n wire mod_sub_return0_carry_n_1;\n wire mod_sub_return0_carry_n_2;\n wire mod_sub_return0_carry_n_3;\n wire mod_sub_return0_carry_n_4;\n wire mod_sub_return0_carry_n_5;\n wire mod_sub_return0_carry_n_6;\n wire mod_sub_return0_carry_n_7;\n wire ocd_edge_detect_rdy_r_reg;\n wire ocd_ktap_left_r_reg;\n wire ocd_ktap_left_r_reg_0;\n wire ocd_ktap_right_r_reg;\n wire poc_backup_ns;\n wire poc_backup_ns0;\n wire poc_backup_ns0_carry_i_10_n_0;\n wire poc_backup_ns0_carry_i_11_n_0;\n wire poc_backup_ns0_carry_i_12_n_0;\n wire poc_backup_ns0_carry_i_13_n_0;\n wire poc_backup_ns0_carry_i_14_n_0;\n wire poc_backup_ns0_carry_i_15_n_0;\n wire poc_backup_ns0_carry_i_16_n_0;\n wire poc_backup_ns0_carry_i_1_n_0;\n wire poc_backup_ns0_carry_i_2_n_0;\n wire poc_backup_ns0_carry_i_3_n_0;\n wire poc_backup_ns0_carry_i_4_n_0;\n wire poc_backup_ns0_carry_i_5_n_0;\n wire poc_backup_ns0_carry_i_6_n_0;\n wire poc_backup_ns0_carry_i_7_n_0;\n wire poc_backup_ns0_carry_i_8_n_0;\n wire poc_backup_ns0_carry_i_9_n_0;\n wire poc_backup_ns0_carry_n_1;\n wire poc_backup_ns0_carry_n_2;\n wire poc_backup_ns0_carry_n_3;\n wire poc_backup_r_reg_0;\n wire [7:0]prev_r;\n wire \\prev_r_reg[0]_0 ;\n wire \\prev_r_reg[0]_1 ;\n wire [2:0]\\prev_r_reg[2]_0 ;\n wire reset_run_ends;\n wire [2:0]\\rise_lead_center_offset_r_reg[2]_0 ;\n wire [1:0]\\rise_lead_center_offset_r_reg[4]_0 ;\n wire [1:0]\\rise_lead_center_offset_r_reg[4]_1 ;\n wire [2:0]\\rise_lead_r_reg[2] ;\n wire [2:0]\\rise_lead_r_reg[2]_0 ;\n wire [3:0]\\rise_lead_r_reg[3] ;\n wire [3:0]\\rise_lead_r_reg[3]_0 ;\n wire [5:0]\\rise_lead_r_reg[3]_1 ;\n wire [1:0]\\rise_lead_r_reg[4] ;\n wire [2:0]\\rise_lead_r_reg[4]_0 ;\n wire [0:0]\\rise_lead_r_reg[4]_1 ;\n wire [1:0]\\rise_lead_r_reg[4]_2 ;\n wire [2:0]\\rise_lead_r_reg[5] ;\n wire \\rise_trail_center_offset_r_reg[0]_0 ;\n wire [2:0]\\rise_trail_center_offset_r_reg[2]_0 ;\n wire [3:0]\\rise_trail_center_offset_r_reg[3]_0 ;\n wire [1:0]\\rise_trail_center_offset_r_reg[5]_0 ;\n wire [2:0]\\rise_trail_r_reg[2] ;\n wire [2:0]\\rise_trail_r_reg[2]_0 ;\n wire [3:0]\\rise_trail_r_reg[3] ;\n wire [3:0]\\rise_trail_r_reg[3]_0 ;\n wire [5:0]\\rise_trail_r_reg[3]_1 ;\n wire [0:0]\\rise_trail_r_reg[4] ;\n wire [1:0]\\rise_trail_r_reg[5] ;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire run_end_r2_reg_srl3_n_0;\n wire run_end_r3;\n wire \\run_ends_r[0]_i_1_n_0 ;\n wire \\run_ends_r[1]_i_1_n_0 ;\n wire \\run_ends_r_reg[1]_0 ;\n wire run_polarity_held_r;\n wire run_too_small_r10;\n wire run_too_small_r2_reg_srl2_n_0;\n wire run_too_small_r3;\n wire run_too_small_r_reg;\n wire samps_zero_r_reg;\n wire samps_zero_r_reg_0;\n wire \\sm_r_reg[1] ;\n wire [4:0]\\window_center_r_reg[6]_0 ;\n wire [3:0]\\window_center_r_reg[6]_1 ;\n wire [3:0]\\window_center_r_reg[6]_2 ;\n wire [0:0]NLW_center0_return1__0_carry_O_UNCONNECTED;\n wire [3:2]NLW_center0_return1__0_carry__0_CO_UNCONNECTED;\n wire [3:3]NLW_center0_return1__0_carry__0_O_UNCONNECTED;\n wire [3:1]NLW_center0_return1__1_carry_O_UNCONNECTED;\n wire [2:2]NLW_center0_return1__1_carry__0_CO_UNCONNECTED;\n wire [3:3]NLW_center0_return1__1_carry__0_O_UNCONNECTED;\n wire [0:0]NLW_center_return1__0_carry_O_UNCONNECTED;\n wire [3:2]NLW_center_return1__0_carry__0_CO_UNCONNECTED;\n wire [3:3]NLW_center_return1__0_carry__0_O_UNCONNECTED;\n wire [3:1]NLW_center_return1__1_carry_O_UNCONNECTED;\n wire [2:2]NLW_center_return1__1_carry__0_CO_UNCONNECTED;\n wire [3:3]NLW_center_return1__1_carry__0_O_UNCONNECTED;\n wire [3:3]NLW_diff_ns0_carry__0_CO_UNCONNECTED;\n wire [0:0]\\NLW_diff_ns0_inferred__0/i__carry_O_UNCONNECTED ;\n wire [2:2]\\NLW_diff_ns0_inferred__0/i__carry__0_CO_UNCONNECTED ;\n wire [3:3]\\NLW_diff_ns0_inferred__0/i__carry__0_O_UNCONNECTED ;\n wire [3:0]NLW_diff_ns1_carry_O_UNCONNECTED;\n wire [0:0]NLW_mod_sub1_return0__0_carry_O_UNCONNECTED;\n wire [3:1]NLW_mod_sub1_return0__0_carry__0_CO_UNCONNECTED;\n wire [3:2]NLW_mod_sub1_return0__0_carry__0_O_UNCONNECTED;\n wire [3:1]NLW_mod_sub1_return0_carry__0_CO_UNCONNECTED;\n wire [3:2]NLW_mod_sub1_return0_carry__0_O_UNCONNECTED;\n wire [0:0]NLW_mod_sub_return0__0_carry_O_UNCONNECTED;\n wire [3:1]NLW_mod_sub_return0__0_carry__0_CO_UNCONNECTED;\n wire [3:2]NLW_mod_sub_return0__0_carry__0_O_UNCONNECTED;\n wire [3:1]NLW_mod_sub_return0_carry__0_CO_UNCONNECTED;\n wire [3:2]NLW_mod_sub_return0_carry__0_O_UNCONNECTED;\n wire [3:0]NLW_poc_backup_ns0_carry_O_UNCONNECTED;\n\n CARRY4 center0_return1__0_carry\n (.CI(1'b0),\n .CO({center0_return1__0_carry_n_0,center0_return1__0_carry_n_1,center0_return1__0_carry_n_2,center0_return1__0_carry_n_3}),\n .CYINIT(1'b0),\n .DI({\\rise_lead_r_reg[2]_0 ,1'b0}),\n .O({center0_return0[3:1],NLW_center0_return1__0_carry_O_UNCONNECTED[0]}),\n .S({\\rise_trail_r_reg[2]_0 ,center0_return1__0_carry_i_7_n_0}));\n CARRY4 center0_return1__0_carry__0\n (.CI(center0_return1__0_carry_n_0),\n .CO({NLW_center0_return1__0_carry__0_CO_UNCONNECTED[3:2],center0_return1__0_carry__0_n_2,center0_return1__0_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,\\center_diff_r_reg[4]_0 }),\n .O({NLW_center0_return1__0_carry__0_O_UNCONNECTED[3],center0_return0[6:4]}),\n .S({1'b0,\\rise_lead_r_reg[4]_0 }));\n LUT1 #(\n .INIT(2'h2)) \n center0_return1__0_carry_i_7\n (.I0(\\center_diff_r_reg_n_0_[0] ),\n .O(center0_return1__0_carry_i_7_n_0));\n CARRY4 center0_return1__1_carry\n (.CI(1'b0),\n .CO({center0_return1__1_carry_n_0,center0_return1__1_carry_n_1,center0_return1__1_carry_n_2,center0_return1__1_carry_n_3}),\n .CYINIT(1'b0),\n .DI({\\rise_lead_r_reg[2] ,1'b0}),\n .O({NLW_center0_return1__1_carry_O_UNCONNECTED[3:1],center0_return0[0]}),\n .S({\\rise_trail_r_reg[2] ,center0_return1__1_carry_i_7_n_0}));\n CARRY4 center0_return1__1_carry__0\n (.CI(center0_return1__1_carry_n_0),\n .CO({center0_return3[3],NLW_center0_return1__1_carry__0_CO_UNCONNECTED[2],center0_return1__1_carry__0_n_2,center0_return1__1_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,\\rise_lead_r_reg[4] }),\n .O({NLW_center0_return1__1_carry__0_O_UNCONNECTED[3],center0_return3[2:0]}),\n .S({1'b1,\\rise_lead_r_reg[5] }));\n LUT1 #(\n .INIT(2'h2)) \n center0_return1__1_carry_i_7\n (.I0(\\center_diff_r_reg_n_0_[0] ),\n .O(center0_return1__1_carry_i_7_n_0));\n FDRE #(\n .INIT(1'b0)) \n \\center_diff_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(D[0]),\n .Q(\\center_diff_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\center_diff_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(D[1]),\n .Q(\\window_center_r_reg[6]_0 [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\center_diff_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(D[2]),\n .Q(\\window_center_r_reg[6]_0 [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\center_diff_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(D[3]),\n .Q(\\window_center_r_reg[6]_0 [2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\center_diff_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(D[4]),\n .Q(\\window_center_r_reg[6]_0 [3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\center_diff_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(D[5]),\n .Q(\\window_center_r_reg[6]_0 [4]),\n .R(1'b0));\n CARRY4 center_return1__0_carry\n (.CI(1'b0),\n .CO({center_return1__0_carry_n_0,center_return1__0_carry_n_1,center_return1__0_carry_n_2,center_return1__0_carry_n_3}),\n .CYINIT(1'b0),\n .DI({Q[2:0],1'b0}),\n .O({center_return0[3:1],NLW_center_return1__0_carry_O_UNCONNECTED[0]}),\n .S({\\rise_lead_center_offset_r_reg[2]_0 ,center_return1__0_carry_i_4_n_0}));\n CARRY4 center_return1__0_carry__0\n (.CI(center_return1__0_carry_n_0),\n .CO({NLW_center_return1__0_carry__0_CO_UNCONNECTED[3:2],center_return1__0_carry__0_n_2,center_return1__0_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,DI,Q[3]}),\n .O({NLW_center_return1__0_carry__0_O_UNCONNECTED[3],center_return0[6:4]}),\n .S({1'b0,center_return1__0_carry__0_i_1_n_0,\\edge_diff_r_reg[4]_0 }));\n LUT3 #(\n .INIT(8'h78)) \n center_return1__0_carry__0_i_1\n (.I0(Q[4]),\n .I1(\\edge_center_r_reg[6]_0 [4]),\n .I2(Q[5]),\n .O(center_return1__0_carry__0_i_1_n_0));\n LUT1 #(\n .INIT(2'h2)) \n center_return1__0_carry_i_4\n (.I0(diff),\n .O(center_return1__0_carry_i_4_n_0));\n CARRY4 center_return1__1_carry\n (.CI(1'b0),\n .CO({center_return1__1_carry_n_0,center_return1__1_carry_n_1,center_return1__1_carry_n_2,center_return1__1_carry_n_3}),\n .CYINIT(1'b0),\n .DI({Q[2:0],1'b0}),\n .O({NLW_center_return1__1_carry_O_UNCONNECTED[3:1],center_return0[0]}),\n .S({S,center_return1__1_carry_i_4_n_0}));\n CARRY4 center_return1__1_carry__0\n (.CI(center_return1__1_carry_n_0),\n .CO({center_return3[3],NLW_center_return1__1_carry__0_CO_UNCONNECTED[2],center_return1__1_carry__0_n_2,center_return1__1_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,Q[4:3]}),\n .O({NLW_center_return1__1_carry__0_O_UNCONNECTED[3],center_return3[2:0]}),\n .S({1'b1,center_return1__1_carry__0_i_1_n_0,\\rise_lead_center_offset_r_reg[4]_0 }));\n LUT1 #(\n .INIT(2'h2)) \n center_return1__1_carry__0_i_1\n (.I0(Q[5]),\n .O(center_return1__1_carry__0_i_1_n_0));\n LUT1 #(\n .INIT(2'h2)) \n center_return1__1_carry_i_4\n (.I0(diff),\n .O(center_return1__1_carry_i_4_n_0));\n CARRY4 diff_ns0_carry\n (.CI(1'b0),\n .CO({diff_ns0_carry_n_0,diff_ns0_carry_n_1,diff_ns0_carry_n_2,diff_ns0_carry_n_3}),\n .CYINIT(1'b1),\n .DI(\\diff_r_reg[7]_0 [3:0]),\n .O(diff_ns0[3:0]),\n .S(\\edge_center_r_reg[3]_0 ));\n CARRY4 diff_ns0_carry__0\n (.CI(diff_ns0_carry_n_0),\n .CO({NLW_diff_ns0_carry__0_CO_UNCONNECTED[3],diff_ns0_carry__0_n_1,diff_ns0_carry__0_n_2,diff_ns0_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,\\edge_center_r_reg[5]_0 ,\\diff_r_reg[7]_1 [4]}),\n .O(diff_ns0[7:4]),\n .S(\\window_center_r_reg[6]_2 ));\n CARRY4 \\diff_ns0_inferred__0/i__carry \n (.CI(1'b0),\n .CO({\\diff_ns0_inferred__0/i__carry_n_0 ,\\diff_ns0_inferred__0/i__carry_n_1 ,\\diff_ns0_inferred__0/i__carry_n_2 ,\\diff_ns0_inferred__0/i__carry_n_3 }),\n .CYINIT(1'b1),\n .DI(\\diff_r_reg[7]_0 [3:0]),\n .O({diff_ns00_in[3:1],\\NLW_diff_ns0_inferred__0/i__carry_O_UNCONNECTED [0]}),\n .S(\\edge_center_r_reg[3]_1 ));\n CARRY4 \\diff_ns0_inferred__0/i__carry__0 \n (.CI(\\diff_ns0_inferred__0/i__carry_n_0 ),\n .CO({\\diff_ns0_inferred__0/i__carry__0_n_0 ,\\NLW_diff_ns0_inferred__0/i__carry__0_CO_UNCONNECTED [2],\\diff_ns0_inferred__0/i__carry__0_n_2 ,\\diff_ns0_inferred__0/i__carry__0_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,\\diff_r_reg[7]_0 [6:4]}),\n .O({\\NLW_diff_ns0_inferred__0/i__carry__0_O_UNCONNECTED [3],diff_ns00_in[6:4]}),\n .S({1'b1,\\edge_center_r_reg[6]_2 }));\n CARRY4 diff_ns1_carry\n (.CI(1'b0),\n .CO({diff_ns1,diff_ns1_carry_n_1,diff_ns1_carry_n_2,diff_ns1_carry_n_3}),\n .CYINIT(1'b1),\n .DI(\\edge_center_r_reg[6]_1 ),\n .O(NLW_diff_ns1_carry_O_UNCONNECTED[3:0]),\n .S(\\window_center_r_reg[6]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair444\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\diff_r[0]_i_1 \n (.I0(\\edge_center_r_reg[0]_0 ),\n .I1(diff_ns0[0]),\n .I2(diff_ns1),\n .O(diff_ns[0]));\n (* SOFT_HLUTNM = \"soft_lutpair445\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\diff_r[1]_i_1 \n (.I0(diff_ns00_in[1]),\n .I1(diff_ns0[1]),\n .I2(diff_ns1),\n .O(diff_ns[1]));\n (* SOFT_HLUTNM = \"soft_lutpair443\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\diff_r[2]_i_1 \n (.I0(diff_ns00_in[2]),\n .I1(diff_ns0[2]),\n .I2(diff_ns1),\n .O(diff_ns[2]));\n (* SOFT_HLUTNM = \"soft_lutpair446\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\diff_r[3]_i_1 \n (.I0(diff_ns00_in[3]),\n .I1(diff_ns0[3]),\n .I2(diff_ns1),\n .O(diff_ns[3]));\n (* SOFT_HLUTNM = \"soft_lutpair446\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\diff_r[4]_i_1 \n (.I0(diff_ns00_in[4]),\n .I1(diff_ns0[4]),\n .I2(diff_ns1),\n .O(diff_ns[4]));\n (* SOFT_HLUTNM = \"soft_lutpair443\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\diff_r[5]_i_1 \n (.I0(diff_ns00_in[5]),\n .I1(diff_ns0[5]),\n .I2(diff_ns1),\n .O(diff_ns[5]));\n (* SOFT_HLUTNM = \"soft_lutpair445\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\diff_r[6]_i_1 \n (.I0(diff_ns00_in[6]),\n .I1(diff_ns0[6]),\n .I2(diff_ns1),\n .O(diff_ns[6]));\n (* SOFT_HLUTNM = \"soft_lutpair444\" *) \n LUT3 #(\n .INIT(8'h5C)) \n \\diff_r[7]_i_1 \n (.I0(\\diff_ns0_inferred__0/i__carry__0_n_0 ),\n .I1(diff_ns0[7]),\n .I2(diff_ns1),\n .O(diff_ns[7]));\n FDRE #(\n .INIT(1'b0)) \n \\diff_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(diff_ns[0]),\n .Q(\\prev_r_reg[2]_0 [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\diff_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(diff_ns[1]),\n .Q(\\prev_r_reg[2]_0 [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\diff_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(diff_ns[2]),\n .Q(\\prev_r_reg[2]_0 [2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\diff_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(diff_ns[3]),\n .Q(\\diff_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\diff_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(diff_ns[4]),\n .Q(\\diff_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\diff_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(diff_ns[5]),\n .Q(\\diff_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\diff_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(diff_ns[6]),\n .Q(\\diff_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\diff_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(diff_ns[7]),\n .Q(\\diff_r_reg_n_0_[7] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h000000000000BF80)) \n diffs_eq_r_i_1\n (.I0(edge_aligned_r_i_2_n_0),\n .I1(done_ns),\n .I2(detect_done_r_reg),\n .I3(diffs_eq_r),\n .I4(ocd_ktap_right_r_reg),\n .I5(ocd_ktap_left_r_reg),\n .O(diffs_eq_ns));\n FDRE #(\n .INIT(1'b0)) \n diffs_eq_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(diffs_eq_ns),\n .Q(diffs_eq_r),\n .R(1'b0));\n LUT3 #(\n .INIT(8'h80)) \n done_r_i_1\n (.I0(ocd_edge_detect_rdy_r_reg),\n .I1(\\prev_r_reg[0]_0 ),\n .I2(\\prev_r_reg[0]_1 ),\n .O(done_ns));\n FDRE #(\n .INIT(1'b0)) \n done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(done_ns),\n .Q(detect_done_r_reg),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h000000F400000000)) \n edge_aligned_r_i_1\n (.I0(edge_aligned_r_i_2_n_0),\n .I1(diffs_eq_r),\n .I2(edge_aligned_r_i_3_n_0),\n .I3(rstdiv0_sync_r1_reg_rep__20),\n .I4(ocd_ktap_left_r_reg_0),\n .I5(done_ns),\n .O(edge_aligned_ns));\n LUT6 #(\n .INIT(64'h4000000055551555)) \n edge_aligned_r_i_2\n (.I0(\\diff_r_reg_n_0_[6] ),\n .I1(\\diff_r_reg_n_0_[5] ),\n .I2(\\diff_r_reg_n_0_[4] ),\n .I3(\\diff_r_reg_n_0_[3] ),\n .I4(\\diff_r_reg[2]_0 ),\n .I5(\\diff_r_reg_n_0_[7] ),\n .O(edge_aligned_r_i_2_n_0));\n LUT6 #(\n .INIT(64'h0000000000000004)) \n edge_aligned_r_i_3\n (.I0(\\diff_r_reg_n_0_[3] ),\n .I1(\\diff_r_reg[2]_0 ),\n .I2(\\diff_r_reg_n_0_[4] ),\n .I3(\\diff_r_reg_n_0_[5] ),\n .I4(\\diff_r_reg_n_0_[6] ),\n .I5(\\diff_r_reg_n_0_[7] ),\n .O(edge_aligned_r_i_3_n_0));\n FDRE #(\n .INIT(1'b0)) \n edge_aligned_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(edge_aligned_ns),\n .Q(\\sm_r_reg[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\edge_center_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(center_return0[0]),\n .Q(\\diff_r_reg[7]_0 [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\edge_center_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(center_return0[1]),\n .Q(\\diff_r_reg[7]_0 [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\edge_center_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(center_return0[2]),\n .Q(\\diff_r_reg[7]_0 [2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\edge_center_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(center_return0[3]),\n .Q(\\diff_r_reg[7]_0 [3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\edge_center_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(center_return0[4]),\n .Q(\\diff_r_reg[7]_0 [4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\edge_center_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(center_return0[5]),\n .Q(\\diff_r_reg[7]_0 [5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\edge_center_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(center_return0[6]),\n .Q(\\diff_r_reg[7]_0 [6]),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hBAFB8A08)) \n \\edge_diff_r[0]_i_1 \n (.I0(\\rise_trail_center_offset_r_reg[0]_0 ),\n .I1(\\edge_diff_r[5]_i_2_n_0 ),\n .I2(Q[5]),\n .I3(\\edge_diff_r_reg[0]_0 [5]),\n .I4(mod_sub_return0_carry_n_7),\n .O(mod_sub_return[0]));\n LUT5 #(\n .INIT(32'hBAFB8A08)) \n \\edge_diff_r[1]_i_1 \n (.I0(mod_sub_return0__0_carry_n_6),\n .I1(\\edge_diff_r[5]_i_2_n_0 ),\n .I2(Q[5]),\n .I3(\\edge_diff_r_reg[0]_0 [5]),\n .I4(mod_sub_return0_carry_n_6),\n .O(mod_sub_return[1]));\n LUT5 #(\n .INIT(32'hBAFB8A08)) \n \\edge_diff_r[2]_i_1 \n (.I0(mod_sub_return0__0_carry_n_5),\n .I1(\\edge_diff_r[5]_i_2_n_0 ),\n .I2(Q[5]),\n .I3(\\edge_diff_r_reg[0]_0 [5]),\n .I4(mod_sub_return0_carry_n_5),\n .O(mod_sub_return[2]));\n LUT5 #(\n .INIT(32'hBAFB8A08)) \n \\edge_diff_r[3]_i_1 \n (.I0(mod_sub_return0__0_carry_n_4),\n .I1(\\edge_diff_r[5]_i_2_n_0 ),\n .I2(Q[5]),\n .I3(\\edge_diff_r_reg[0]_0 [5]),\n .I4(mod_sub_return0_carry_n_4),\n .O(mod_sub_return[3]));\n LUT5 #(\n .INIT(32'hBAFB8A08)) \n \\edge_diff_r[4]_i_1 \n (.I0(mod_sub_return0__0_carry__0_n_7),\n .I1(\\edge_diff_r[5]_i_2_n_0 ),\n .I2(Q[5]),\n .I3(\\edge_diff_r_reg[0]_0 [5]),\n .I4(mod_sub_return0_carry__0_n_7),\n .O(mod_sub_return[4]));\n LUT5 #(\n .INIT(32'hBAFB8A08)) \n \\edge_diff_r[5]_i_1 \n (.I0(mod_sub_return0__0_carry__0_n_6),\n .I1(\\edge_diff_r[5]_i_2_n_0 ),\n .I2(Q[5]),\n .I3(\\edge_diff_r_reg[0]_0 [5]),\n .I4(mod_sub_return0_carry__0_n_6),\n .O(mod_sub_return[5]));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\edge_diff_r[5]_i_2 \n (.I0(\\edge_diff_r[5]_i_3_n_0 ),\n .I1(Q[3]),\n .I2(\\edge_diff_r_reg[0]_0 [3]),\n .I3(Q[4]),\n .I4(\\edge_diff_r_reg[0]_0 [4]),\n .O(\\edge_diff_r[5]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hDF0DFFFF0000DF0D)) \n \\edge_diff_r[5]_i_3 \n (.I0(Q[0]),\n .I1(\\edge_diff_r_reg[0]_0 [0]),\n .I2(Q[1]),\n .I3(\\edge_diff_r_reg[0]_0 [1]),\n .I4(Q[2]),\n .I5(\\edge_diff_r_reg[0]_0 [2]),\n .O(\\edge_diff_r[5]_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\edge_diff_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(mod_sub_return[0]),\n .Q(diff),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\edge_diff_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(mod_sub_return[1]),\n .Q(\\edge_center_r_reg[6]_0 [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\edge_diff_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(mod_sub_return[2]),\n .Q(\\edge_center_r_reg[6]_0 [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\edge_diff_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(mod_sub_return[3]),\n .Q(\\edge_center_r_reg[6]_0 [2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\edge_diff_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(mod_sub_return[4]),\n .Q(\\edge_center_r_reg[6]_0 [3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\edge_diff_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(mod_sub_return[5]),\n .Q(\\edge_center_r_reg[6]_0 [4]),\n .R(1'b0));\n CARRY4 mod_sub1_return0__0_carry\n (.CI(1'b0),\n .CO({mod_sub1_return0__0_carry_n_0,mod_sub1_return0__0_carry_n_1,mod_sub1_return0__0_carry_n_2,mod_sub1_return0__0_carry_n_3}),\n .CYINIT(1'b1),\n .DI(\\rise_trail_r_reg[3]_0 ),\n .O({\\center_diff_r_reg[3]_0 ,NLW_mod_sub1_return0__0_carry_O_UNCONNECTED[0]}),\n .S(\\rise_lead_r_reg[3]_0 ));\n CARRY4 mod_sub1_return0__0_carry__0\n (.CI(mod_sub1_return0__0_carry_n_0),\n .CO({NLW_mod_sub1_return0__0_carry__0_CO_UNCONNECTED[3:1],mod_sub1_return0__0_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,\\rise_trail_r_reg[4] }),\n .O({NLW_mod_sub1_return0__0_carry__0_O_UNCONNECTED[3:2],\\center_diff_r_reg[5]_1 }),\n .S({1'b0,1'b0,\\rise_trail_r_reg[5] }));\n CARRY4 mod_sub1_return0_carry\n (.CI(1'b0),\n .CO({mod_sub1_return0_carry_n_0,mod_sub1_return0_carry_n_1,mod_sub1_return0_carry_n_2,mod_sub1_return0_carry_n_3}),\n .CYINIT(1'b1),\n .DI(\\rise_lead_r_reg[3] ),\n .O(O),\n .S(\\rise_trail_r_reg[3] ));\n CARRY4 mod_sub1_return0_carry__0\n (.CI(mod_sub1_return0_carry_n_0),\n .CO({NLW_mod_sub1_return0_carry__0_CO_UNCONNECTED[3:1],mod_sub1_return0_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,\\rise_lead_r_reg[4]_1 }),\n .O({NLW_mod_sub1_return0_carry__0_O_UNCONNECTED[3:2],\\center_diff_r_reg[5]_0 }),\n .S({1'b0,1'b0,\\rise_lead_r_reg[4]_2 }));\n CARRY4 mod_sub_return0__0_carry\n (.CI(1'b0),\n .CO({mod_sub_return0__0_carry_n_0,mod_sub_return0__0_carry_n_1,mod_sub_return0__0_carry_n_2,mod_sub_return0__0_carry_n_3}),\n .CYINIT(1'b1),\n .DI(\\edge_diff_r_reg[0]_0 [3:0]),\n .O({mod_sub_return0__0_carry_n_4,mod_sub_return0__0_carry_n_5,mod_sub_return0__0_carry_n_6,NLW_mod_sub_return0__0_carry_O_UNCONNECTED[0]}),\n .S(\\rise_trail_center_offset_r_reg[3]_0 ));\n CARRY4 mod_sub_return0__0_carry__0\n (.CI(mod_sub_return0__0_carry_n_0),\n .CO({NLW_mod_sub_return0__0_carry__0_CO_UNCONNECTED[3:1],mod_sub_return0__0_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,\\edge_diff_r_reg[0]_0 [4]}),\n .O({NLW_mod_sub_return0__0_carry__0_O_UNCONNECTED[3:2],mod_sub_return0__0_carry__0_n_6,mod_sub_return0__0_carry__0_n_7}),\n .S({1'b0,1'b0,\\rise_trail_center_offset_r_reg[5]_0 }));\n CARRY4 mod_sub_return0_carry\n (.CI(1'b0),\n .CO({mod_sub_return0_carry_n_0,mod_sub_return0_carry_n_1,mod_sub_return0_carry_n_2,mod_sub_return0_carry_n_3}),\n .CYINIT(1'b1),\n .DI({Q[3],\\edge_diff_r_reg[0]_0 [2:0]}),\n .O({mod_sub_return0_carry_n_4,mod_sub_return0_carry_n_5,mod_sub_return0_carry_n_6,mod_sub_return0_carry_n_7}),\n .S({mod_sub_return0_carry_i_1_n_0,\\rise_trail_center_offset_r_reg[2]_0 }));\n CARRY4 mod_sub_return0_carry__0\n (.CI(mod_sub_return0_carry_n_0),\n .CO({NLW_mod_sub_return0_carry__0_CO_UNCONNECTED[3:1],mod_sub_return0_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,mod_sub_return0_carry__0_i_1_n_0}),\n .O({NLW_mod_sub_return0_carry__0_O_UNCONNECTED[3:2],mod_sub_return0_carry__0_n_6,mod_sub_return0_carry__0_n_7}),\n .S({1'b0,1'b0,\\rise_lead_center_offset_r_reg[4]_1 }));\n LUT2 #(\n .INIT(4'h6)) \n mod_sub_return0_carry__0_i_1\n (.I0(Q[4]),\n .I1(\\edge_diff_r_reg[0]_0 [4]),\n .O(mod_sub_return0_carry__0_i_1_n_0));\n LUT2 #(\n .INIT(4'h6)) \n mod_sub_return0_carry_i_1\n (.I0(\\edge_diff_r_reg[0]_0 [3]),\n .I1(Q[3]),\n .O(mod_sub_return0_carry_i_1_n_0));\n CARRY4 poc_backup_ns0_carry\n (.CI(1'b0),\n .CO({poc_backup_ns0,poc_backup_ns0_carry_n_1,poc_backup_ns0_carry_n_2,poc_backup_ns0_carry_n_3}),\n .CYINIT(1'b0),\n .DI({poc_backup_ns0_carry_i_1_n_0,poc_backup_ns0_carry_i_2_n_0,poc_backup_ns0_carry_i_3_n_0,poc_backup_ns0_carry_i_4_n_0}),\n .O(NLW_poc_backup_ns0_carry_O_UNCONNECTED[3:0]),\n .S({poc_backup_ns0_carry_i_5_n_0,poc_backup_ns0_carry_i_6_n_0,poc_backup_ns0_carry_i_7_n_0,poc_backup_ns0_carry_i_8_n_0}));\n LUT6 #(\n .INIT(64'h154015407FD51540)) \n poc_backup_ns0_carry_i_1\n (.I0(prev_r[7]),\n .I1(\\diff_r_reg_n_0_[6] ),\n .I2(poc_backup_ns0_carry_i_9_n_0),\n .I3(\\diff_r_reg_n_0_[7] ),\n .I4(poc_backup_ns0_carry_i_10_n_0),\n .I5(prev_r[6]),\n .O(poc_backup_ns0_carry_i_1_n_0));\n LUT6 #(\n .INIT(64'hF00C0C0C580C0C0C)) \n poc_backup_ns0_carry_i_10\n (.I0(\\diff_r_reg[2]_0 ),\n .I1(\\diff_r_reg_n_0_[7] ),\n .I2(\\diff_r_reg_n_0_[6] ),\n .I3(\\diff_r_reg_n_0_[4] ),\n .I4(\\diff_r_reg_n_0_[5] ),\n .I5(\\diff_r_reg_n_0_[3] ),\n .O(poc_backup_ns0_carry_i_10_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair441\" *) \n LUT2 #(\n .INIT(4'h1)) \n poc_backup_ns0_carry_i_11\n (.I0(\\diff_r_reg_n_0_[6] ),\n .I1(\\diff_r_reg_n_0_[7] ),\n .O(poc_backup_ns0_carry_i_11_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair442\" *) \n LUT4 #(\n .INIT(16'h0001)) \n poc_backup_ns0_carry_i_12\n (.I0(\\prev_r_reg[2]_0 [1]),\n .I1(\\prev_r_reg[2]_0 [0]),\n .I2(\\prev_r_reg[2]_0 [2]),\n .I3(\\diff_r_reg_n_0_[3] ),\n .O(poc_backup_ns0_carry_i_12_n_0));\n LUT6 #(\n .INIT(64'h0FF00FF00FF00F8F)) \n poc_backup_ns0_carry_i_13\n (.I0(\\diff_r_reg_n_0_[4] ),\n .I1(\\diff_r_reg_n_0_[5] ),\n .I2(\\diff_r_reg_n_0_[3] ),\n .I3(\\diff_r_reg[2]_0 ),\n .I4(\\diff_r_reg_n_0_[6] ),\n .I5(\\diff_r_reg_n_0_[7] ),\n .O(poc_backup_ns0_carry_i_13_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair442\" *) \n LUT4 #(\n .INIT(16'h6663)) \n poc_backup_ns0_carry_i_14\n (.I0(poc_backup_ns0_carry_i_15_n_0),\n .I1(\\prev_r_reg[2]_0 [2]),\n .I2(\\prev_r_reg[2]_0 [0]),\n .I3(\\prev_r_reg[2]_0 [1]),\n .O(poc_backup_ns0_carry_i_14_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair441\" *) \n LUT5 #(\n .INIT(32'h01111111)) \n poc_backup_ns0_carry_i_15\n (.I0(\\diff_r_reg_n_0_[7] ),\n .I1(\\diff_r_reg_n_0_[6] ),\n .I2(\\diff_r_reg_n_0_[4] ),\n .I3(\\diff_r_reg_n_0_[5] ),\n .I4(\\diff_r_reg_n_0_[3] ),\n .O(poc_backup_ns0_carry_i_15_n_0));\n LUT6 #(\n .INIT(64'hA556A956A956A956)) \n poc_backup_ns0_carry_i_16\n (.I0(prev_r[3]),\n .I1(poc_backup_ns0_carry_i_11_n_0),\n .I2(\\diff_r_reg[2]_0 ),\n .I3(\\diff_r_reg_n_0_[3] ),\n .I4(\\diff_r_reg_n_0_[5] ),\n .I5(\\diff_r_reg_n_0_[4] ),\n .O(poc_backup_ns0_carry_i_16_n_0));\n LUT6 #(\n .INIT(64'h44541101C5F45351)) \n poc_backup_ns0_carry_i_2\n (.I0(prev_r[5]),\n .I1(poc_backup_ns0_carry_i_11_n_0),\n .I2(\\diff_r_reg_n_0_[4] ),\n .I3(poc_backup_ns0_carry_i_12_n_0),\n .I4(\\diff_r_reg_n_0_[5] ),\n .I5(prev_r[4]),\n .O(poc_backup_ns0_carry_i_2_n_0));\n LUT4 #(\n .INIT(16'h1117)) \n poc_backup_ns0_carry_i_3\n (.I0(prev_r[3]),\n .I1(poc_backup_ns0_carry_i_13_n_0),\n .I2(prev_r[2]),\n .I3(poc_backup_ns0_carry_i_14_n_0),\n .O(poc_backup_ns0_carry_i_3_n_0));\n LUT5 #(\n .INIT(32'h5014D45C)) \n poc_backup_ns0_carry_i_4\n (.I0(prev_r[1]),\n .I1(\\prev_r_reg[2]_0 [0]),\n .I2(\\prev_r_reg[2]_0 [1]),\n .I3(poc_backup_ns0_carry_i_15_n_0),\n .I4(prev_r[0]),\n .O(poc_backup_ns0_carry_i_4_n_0));\n LUT6 #(\n .INIT(64'h6A95000000006A95)) \n poc_backup_ns0_carry_i_5\n (.I0(\\diff_r_reg_n_0_[7] ),\n .I1(poc_backup_ns0_carry_i_9_n_0),\n .I2(\\diff_r_reg_n_0_[6] ),\n .I3(prev_r[7]),\n .I4(poc_backup_ns0_carry_i_10_n_0),\n .I5(prev_r[6]),\n .O(poc_backup_ns0_carry_i_5_n_0));\n LUT6 #(\n .INIT(64'h9006990006900096)) \n poc_backup_ns0_carry_i_6\n (.I0(\\diff_r_reg_n_0_[5] ),\n .I1(prev_r[5]),\n .I2(poc_backup_ns0_carry_i_11_n_0),\n .I3(\\diff_r_reg_n_0_[4] ),\n .I4(poc_backup_ns0_carry_i_12_n_0),\n .I5(prev_r[4]),\n .O(poc_backup_ns0_carry_i_6_n_0));\n LUT6 #(\n .INIT(64'h828282A02828280A)) \n poc_backup_ns0_carry_i_7\n (.I0(poc_backup_ns0_carry_i_16_n_0),\n .I1(poc_backup_ns0_carry_i_15_n_0),\n .I2(\\prev_r_reg[2]_0 [2]),\n .I3(\\prev_r_reg[2]_0 [0]),\n .I4(\\prev_r_reg[2]_0 [1]),\n .I5(prev_r[2]),\n .O(poc_backup_ns0_carry_i_7_n_0));\n LUT5 #(\n .INIT(32'h960000C3)) \n poc_backup_ns0_carry_i_8\n (.I0(poc_backup_ns0_carry_i_15_n_0),\n .I1(\\prev_r_reg[2]_0 [1]),\n .I2(prev_r[1]),\n .I3(\\prev_r_reg[2]_0 [0]),\n .I4(prev_r[0]),\n .O(poc_backup_ns0_carry_i_8_n_0));\n LUT6 #(\n .INIT(64'h8888888888888880)) \n poc_backup_ns0_carry_i_9\n (.I0(\\diff_r_reg_n_0_[5] ),\n .I1(\\diff_r_reg_n_0_[4] ),\n .I2(\\diff_r_reg_n_0_[3] ),\n .I3(\\prev_r_reg[2]_0 [2]),\n .I4(\\prev_r_reg[2]_0 [0]),\n .I5(\\prev_r_reg[2]_0 [1]),\n .O(poc_backup_ns0_carry_i_9_n_0));\n LUT5 #(\n .INIT(32'h20202220)) \n poc_backup_r_i_1\n (.I0(poc_backup_ns0),\n .I1(\\run_ends_r_reg[1]_0 ),\n .I2(edge_aligned_r_i_3_n_0),\n .I3(diffs_eq_r),\n .I4(edge_aligned_r_i_2_n_0),\n .O(poc_backup_ns));\n FDRE #(\n .INIT(1'b0)) \n poc_backup_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(poc_backup_ns),\n .Q(poc_backup_r_reg_0),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\prev_r_reg[0] \n (.C(CLK),\n .CE(done_ns),\n .D(\\prev_r_reg[2]_0 [0]),\n .Q(prev_r[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\prev_r_reg[1] \n (.C(CLK),\n .CE(done_ns),\n .D(\\prev_r_reg[2]_0 [1]),\n .Q(prev_r[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\prev_r_reg[2] \n (.C(CLK),\n .CE(done_ns),\n .D(\\prev_r_reg[2]_0 [2]),\n .Q(prev_r[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\prev_r_reg[3] \n (.C(CLK),\n .CE(done_ns),\n .D(\\diff_r_reg_n_0_[3] ),\n .Q(prev_r[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\prev_r_reg[4] \n (.C(CLK),\n .CE(done_ns),\n .D(\\diff_r_reg_n_0_[4] ),\n .Q(prev_r[4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\prev_r_reg[5] \n (.C(CLK),\n .CE(done_ns),\n .D(\\diff_r_reg_n_0_[5] ),\n .Q(prev_r[5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\prev_r_reg[6] \n (.C(CLK),\n .CE(done_ns),\n .D(\\diff_r_reg_n_0_[6] ),\n .Q(prev_r[6]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\prev_r_reg[7] \n (.C(CLK),\n .CE(done_ns),\n .D(\\diff_r_reg_n_0_[7] ),\n .Q(prev_r[7]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_lead_center_offset_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rise_lead_r_reg[3]_1 [0]),\n .Q(Q[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_lead_center_offset_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rise_lead_r_reg[3]_1 [1]),\n .Q(Q[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_lead_center_offset_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rise_lead_r_reg[3]_1 [2]),\n .Q(Q[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_lead_center_offset_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rise_lead_r_reg[3]_1 [3]),\n .Q(Q[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_lead_center_offset_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rise_lead_r_reg[3]_1 [4]),\n .Q(Q[4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_lead_center_offset_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rise_lead_r_reg[3]_1 [5]),\n .Q(Q[5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_trail_center_offset_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rise_trail_r_reg[3]_1 [0]),\n .Q(\\edge_diff_r_reg[0]_0 [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_trail_center_offset_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rise_trail_r_reg[3]_1 [1]),\n .Q(\\edge_diff_r_reg[0]_0 [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_trail_center_offset_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rise_trail_r_reg[3]_1 [2]),\n .Q(\\edge_diff_r_reg[0]_0 [2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_trail_center_offset_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rise_trail_r_reg[3]_1 [3]),\n .Q(\\edge_diff_r_reg[0]_0 [3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_trail_center_offset_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rise_trail_r_reg[3]_1 [4]),\n .Q(\\edge_diff_r_reg[0]_0 [4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rise_trail_center_offset_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rise_trail_r_reg[3]_1 [5]),\n .Q(\\edge_diff_r_reg[0]_0 [5]),\n .R(1'b0));\n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_poc/u_poc_meta/run_end_r2_reg_srl3 \" *) \n SRL16E #(\n .INIT(16'h0000)) \n run_end_r2_reg_srl3\n (.A0(1'b0),\n .A1(1'b1),\n .A2(1'b0),\n .A3(1'b0),\n .CE(1'b1),\n .CLK(CLK),\n .D(samps_zero_r_reg_0),\n .Q(run_end_r2_reg_srl3_n_0));\n FDRE #(\n .INIT(1'b0)) \n run_end_r3_reg\n (.C(CLK),\n .CE(1'b1),\n .D(run_end_r2_reg_srl3_n_0),\n .Q(run_end_r3),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h0000DACA)) \n \\run_ends_r[0]_i_1 \n (.I0(\\prev_r_reg[0]_0 ),\n .I1(\\prev_r_reg[0]_1 ),\n .I2(run_end_r3),\n .I3(run_polarity_held_r),\n .I4(reset_run_ends),\n .O(\\run_ends_r[0]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hFB)) \n \\run_ends_r[0]_i_2 \n (.I0(run_too_small_r3),\n .I1(ocd_edge_detect_rdy_r_reg),\n .I2(rstdiv0_sync_r1_reg_rep__20),\n .O(reset_run_ends));\n LUT6 #(\n .INIT(64'h0000000000EC0000)) \n \\run_ends_r[1]_i_1 \n (.I0(\\prev_r_reg[0]_0 ),\n .I1(\\prev_r_reg[0]_1 ),\n .I2(run_end_r3),\n .I3(rstdiv0_sync_r1_reg_rep__20),\n .I4(ocd_edge_detect_rdy_r_reg),\n .I5(run_too_small_r3),\n .O(\\run_ends_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\run_ends_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\run_ends_r[0]_i_1_n_0 ),\n .Q(\\prev_r_reg[0]_0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\run_ends_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\run_ends_r[1]_i_1_n_0 ),\n .Q(\\prev_r_reg[0]_1 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n run_polarity_held_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(samps_zero_r_reg),\n .Q(run_polarity_held_r),\n .R(1'b0));\n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_poc/u_poc_meta/run_too_small_r2_reg_srl2 \" *) \n SRL16E #(\n .INIT(16'h0000)) \n run_too_small_r2_reg_srl2\n (.A0(1'b1),\n .A1(1'b0),\n .A2(1'b0),\n .A3(1'b0),\n .CE(1'b1),\n .CLK(CLK),\n .D(run_too_small_r10),\n .Q(run_too_small_r2_reg_srl2_n_0));\n LUT3 #(\n .INIT(8'h08)) \n run_too_small_r2_reg_srl2_i_1\n (.I0(run_too_small_r_reg),\n .I1(\\prev_r_reg[0]_0 ),\n .I2(\\prev_r_reg[0]_1 ),\n .O(run_too_small_r10));\n FDRE #(\n .INIT(1'b0)) \n run_too_small_r3_reg\n (.C(CLK),\n .CE(1'b1),\n .D(run_too_small_r2_reg_srl2_n_0),\n .Q(run_too_small_r3),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\window_center_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(center0_return0[0]),\n .Q(\\diff_r_reg[7]_1 [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\window_center_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(center0_return0[1]),\n .Q(\\diff_r_reg[7]_1 [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\window_center_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(center0_return0[2]),\n .Q(\\diff_r_reg[7]_1 [2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\window_center_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(center0_return0[3]),\n .Q(\\diff_r_reg[7]_1 [3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\window_center_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(center0_return0[4]),\n .Q(\\diff_r_reg[7]_1 [4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\window_center_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(center0_return0[5]),\n .Q(\\diff_r_reg[7]_1 [5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\window_center_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(center0_return0[6]),\n .Q(\\diff_r_reg[7]_1 [6]),\n .R(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_poc_pd\" *) \nmodule ddr3_ifmig_7series_v4_0_poc_pd\n (pd_out_pre,\n mmcm_ps_clk,\n in_dqs_lpbk_to_iddr_0,\n rst_sync_r1,\n CLK);\n output [0:0]pd_out_pre;\n input mmcm_ps_clk;\n input in_dqs_lpbk_to_iddr_0;\n input rst_sync_r1;\n input CLK;\n\n wire CLK;\n wire in_dqs_lpbk_to_iddr_0;\n wire mmcm_ps_clk;\n wire [0:0]pd_out_pre;\n wire pos_edge_samp;\n wire q1;\n wire rst_sync_r1;\n wire NLW_u_phase_detector_Q2_UNCONNECTED;\n\n FDRE #(\n .INIT(1'b0)) \n \\no_eXes.pos_edge_samp_reg \n (.C(CLK),\n .CE(1'b1),\n .D(q1),\n .Q(pos_edge_samp),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n pd_out_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pos_edge_samp),\n .Q(pd_out_pre),\n .R(1'b0));\n (* __SRVAL = \"FALSE\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDDR #(\n .DDR_CLK_EDGE(\"OPPOSITE_EDGE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .IS_C_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .SRTYPE(\"SYNC\")) \n u_phase_detector\n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(in_dqs_lpbk_to_iddr_0),\n .Q1(q1),\n .Q2(NLW_u_phase_detector_Q2_UNCONNECTED),\n .R(rst_sync_r1),\n .S(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_poc_pd\" *) \nmodule ddr3_ifmig_7series_v4_0_poc_pd_1\n (pd_out_pre,\n mmcm_ps_clk,\n in_dqs_lpbk_to_iddr_1,\n rst_sync_r1,\n CLK);\n output [0:0]pd_out_pre;\n input mmcm_ps_clk;\n input in_dqs_lpbk_to_iddr_1;\n input rst_sync_r1;\n input CLK;\n\n wire CLK;\n wire in_dqs_lpbk_to_iddr_1;\n wire mmcm_ps_clk;\n wire \\no_eXes.pos_edge_samp_reg_n_0 ;\n wire [0:0]pd_out_pre;\n wire q1;\n wire rst_sync_r1;\n wire NLW_u_phase_detector_Q2_UNCONNECTED;\n\n FDRE #(\n .INIT(1'b0)) \n \\no_eXes.pos_edge_samp_reg \n (.C(CLK),\n .CE(1'b1),\n .D(q1),\n .Q(\\no_eXes.pos_edge_samp_reg_n_0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n pd_out_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\no_eXes.pos_edge_samp_reg_n_0 ),\n .Q(pd_out_pre),\n .R(1'b0));\n (* __SRVAL = \"FALSE\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDDR #(\n .DDR_CLK_EDGE(\"OPPOSITE_EDGE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .IS_C_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .SRTYPE(\"SYNC\")) \n u_phase_detector\n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(in_dqs_lpbk_to_iddr_1),\n .Q1(q1),\n .Q2(NLW_u_phase_detector_Q2_UNCONNECTED),\n .R(rst_sync_r1),\n .S(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_poc_pd\" *) \nmodule ddr3_ifmig_7series_v4_0_poc_pd_2\n (pd_out_pre,\n mmcm_ps_clk,\n in_dqs_lpbk_to_iddr_2,\n rst_sync_r1,\n CLK);\n output [0:0]pd_out_pre;\n input mmcm_ps_clk;\n input in_dqs_lpbk_to_iddr_2;\n input rst_sync_r1;\n input CLK;\n\n wire CLK;\n wire in_dqs_lpbk_to_iddr_2;\n wire mmcm_ps_clk;\n wire \\no_eXes.pos_edge_samp_reg_n_0 ;\n wire [0:0]pd_out_pre;\n wire q1;\n wire rst_sync_r1;\n wire NLW_u_phase_detector_Q2_UNCONNECTED;\n\n FDRE #(\n .INIT(1'b0)) \n \\no_eXes.pos_edge_samp_reg \n (.C(CLK),\n .CE(1'b1),\n .D(q1),\n .Q(\\no_eXes.pos_edge_samp_reg_n_0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n pd_out_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\no_eXes.pos_edge_samp_reg_n_0 ),\n .Q(pd_out_pre),\n .R(1'b0));\n (* __SRVAL = \"FALSE\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDDR #(\n .DDR_CLK_EDGE(\"OPPOSITE_EDGE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .IS_C_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .SRTYPE(\"SYNC\")) \n u_phase_detector\n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(in_dqs_lpbk_to_iddr_2),\n .Q1(q1),\n .Q2(NLW_u_phase_detector_Q2_UNCONNECTED),\n .R(rst_sync_r1),\n .S(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_poc_pd\" *) \nmodule ddr3_ifmig_7series_v4_0_poc_pd_3\n (pd_out,\n mmcm_ps_clk,\n in_dqs_lpbk_to_iddr_3,\n rst_sync_r1,\n CLK,\n pd_out_r_reg_0,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[1] );\n output pd_out;\n input mmcm_ps_clk;\n input in_dqs_lpbk_to_iddr_3;\n input rst_sync_r1;\n input CLK;\n input [2:0]pd_out_r_reg_0;\n input [1:0]\\gen_byte_sel_div1.byte_sel_cnt_reg[1] ;\n\n wire CLK;\n wire [1:0]\\gen_byte_sel_div1.byte_sel_cnt_reg[1] ;\n wire in_dqs_lpbk_to_iddr_3;\n wire mmcm_ps_clk;\n wire \\no_eXes.pos_edge_samp_reg_n_0 ;\n wire pd_out;\n wire [3:3]pd_out_pre;\n wire [2:0]pd_out_r_reg_0;\n wire q1;\n wire rst_sync_r1;\n wire NLW_u_phase_detector_Q2_UNCONNECTED;\n\n FDRE #(\n .INIT(1'b0)) \n \\no_eXes.pos_edge_samp_reg \n (.C(CLK),\n .CE(1'b1),\n .D(q1),\n .Q(\\no_eXes.pos_edge_samp_reg_n_0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n pd_out_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\no_eXes.pos_edge_samp_reg_n_0 ),\n .Q(pd_out_pre),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\samps_hi_r[3]_i_7 \n (.I0(pd_out_pre),\n .I1(pd_out_r_reg_0[2]),\n .I2(\\gen_byte_sel_div1.byte_sel_cnt_reg[1] [1]),\n .I3(pd_out_r_reg_0[1]),\n .I4(\\gen_byte_sel_div1.byte_sel_cnt_reg[1] [0]),\n .I5(pd_out_r_reg_0[0]),\n .O(pd_out));\n (* __SRVAL = \"FALSE\" *) \n (* box_type = \"PRIMITIVE\" *) \n IDDR #(\n .DDR_CLK_EDGE(\"OPPOSITE_EDGE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .IS_C_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .SRTYPE(\"SYNC\")) \n u_phase_detector\n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(in_dqs_lpbk_to_iddr_3),\n .Q1(q1),\n .Q2(NLW_u_phase_detector_Q2_UNCONNECTED),\n .R(rst_sync_r1),\n .S(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_poc_tap_base\" *) \nmodule ddr3_ifmig_7series_v4_0_poc_tap_base\n (\\run_r_reg[0]_0 ,\n run_too_small_r3_reg,\n \\run_r_reg[0]_1 ,\n \\run_r_reg[0]_2 ,\n Q,\n S,\n \\samp_cntr_r_reg[8]_0 ,\n \\samp_cntr_r_reg[12]_0 ,\n \\samp_cntr_r_reg[16]_0 ,\n \\samps_hi_r_reg[3]_0 ,\n \\samps_hi_r_reg[7]_0 ,\n \\samps_hi_r_reg[11]_0 ,\n \\samps_hi_r_reg[15]_0 ,\n \\samps_hi_r_reg[17]_0 ,\n samps_zero_r_reg_0,\n \\tap_r_reg[0]_0 ,\n \\run_r_reg[4]_0 ,\n run_too_small_r_reg_0,\n \\rise_trail_r_reg[0] ,\n \\sm_r_reg[0]_0 ,\n \\sm_r_reg[0]_1 ,\n \\qcntr_r_reg[0] ,\n \\rise_lead_r_reg[5] ,\n DI,\n samps_zero_r_reg_1,\n samps_zero_r_reg_2,\n samps_zero_r_reg_3,\n samps_zero_r_reg_4,\n samps_zero_r_reg_5,\n \\samp_cntr_r_reg[0]_0 ,\n \\rise_trail_r_reg[5] ,\n \\rise_trail_r_reg[5]_0 ,\n \\rise_trail_r_reg[5]_1 ,\n \\rise_trail_r_reg[3] ,\n \\samp_wait_r_reg[6]_0 ,\n \\samp_wait_r_reg[7]_0 ,\n \\rise_trail_r_reg[5]_2 ,\n \\rise_trail_r_reg[5]_3 ,\n CLK,\n samps_lo,\n rstdiv0_sync_r1_reg_rep__20,\n \\run_r_reg[2]_0 ,\n ocd_ktap_left_r_reg,\n ocd_ktap_right_r_reg,\n trailing_edge0,\n trailing_edge00_in,\n poc_sample_pd,\n \\samp_wait_r_reg[4]_0 ,\n samp_cntr_ns0,\n samps_hi_ns0,\n psdone,\n rstdiv0_sync_r1_reg_rep,\n D,\n rstdiv0_sync_r1_reg_rep__0,\n E);\n output \\run_r_reg[0]_0 ;\n output run_too_small_r3_reg;\n output \\run_r_reg[0]_1 ;\n output \\run_r_reg[0]_2 ;\n output [4:0]Q;\n output [3:0]S;\n output [3:0]\\samp_cntr_r_reg[8]_0 ;\n output [3:0]\\samp_cntr_r_reg[12]_0 ;\n output [3:0]\\samp_cntr_r_reg[16]_0 ;\n output [2:0]\\samps_hi_r_reg[3]_0 ;\n output [3:0]\\samps_hi_r_reg[7]_0 ;\n output [3:0]\\samps_hi_r_reg[11]_0 ;\n output [3:0]\\samps_hi_r_reg[15]_0 ;\n output [1:0]\\samps_hi_r_reg[17]_0 ;\n output [3:0]samps_zero_r_reg_0;\n output \\tap_r_reg[0]_0 ;\n output [4:0]\\run_r_reg[4]_0 ;\n output run_too_small_r_reg_0;\n output [0:0]\\rise_trail_r_reg[0] ;\n output \\sm_r_reg[0]_0 ;\n output \\sm_r_reg[0]_1 ;\n output [0:0]\\qcntr_r_reg[0] ;\n output [5:0]\\rise_lead_r_reg[5] ;\n output [0:0]DI;\n output [3:0]samps_zero_r_reg_1;\n output [2:0]samps_zero_r_reg_2;\n output [2:0]samps_zero_r_reg_3;\n output [0:0]samps_zero_r_reg_4;\n output [0:0]samps_zero_r_reg_5;\n output [0:0]\\samp_cntr_r_reg[0]_0 ;\n output [5:0]\\rise_trail_r_reg[5] ;\n output [0:0]\\rise_trail_r_reg[5]_0 ;\n output [0:0]\\rise_trail_r_reg[5]_1 ;\n output [0:0]\\rise_trail_r_reg[3] ;\n output \\samp_wait_r_reg[6]_0 ;\n output [6:0]\\samp_wait_r_reg[7]_0 ;\n output [0:0]\\rise_trail_r_reg[5]_2 ;\n output [0:0]\\rise_trail_r_reg[5]_3 ;\n input CLK;\n input [14:0]samps_lo;\n input rstdiv0_sync_r1_reg_rep__20;\n input \\run_r_reg[2]_0 ;\n input ocd_ktap_left_r_reg;\n input ocd_ktap_right_r_reg;\n input [5:0]trailing_edge0;\n input [5:0]trailing_edge00_in;\n input poc_sample_pd;\n input \\samp_wait_r_reg[4]_0 ;\n input [15:0]samp_cntr_ns0;\n input [17:0]samps_hi_ns0;\n input psdone;\n input rstdiv0_sync_r1_reg_rep;\n input [1:0]D;\n input rstdiv0_sync_r1_reg_rep__0;\n input [0:0]E;\n\n wire CLK;\n wire [1:0]D;\n wire [0:0]DI;\n wire [0:0]E;\n wire [4:0]Q;\n wire [3:0]S;\n wire ocd_ktap_left_r_reg;\n wire ocd_ktap_right_r_reg;\n wire [5:0]p_0_in;\n wire [5:0]p_0_in__0;\n wire [7:0]p_1_in;\n wire poc_sample_pd;\n wire psdone;\n wire [0:0]\\qcntr_r_reg[0] ;\n wire [5:0]\\rise_lead_r_reg[5] ;\n wire \\rise_trail_r[5]_i_4_n_0 ;\n wire \\rise_trail_r[5]_i_6_n_0 ;\n wire \\rise_trail_r[5]_i_7_n_0 ;\n wire \\rise_trail_r[5]_i_8_n_0 ;\n wire \\rise_trail_r[5]_i_9_n_0 ;\n wire [0:0]\\rise_trail_r_reg[0] ;\n wire [0:0]\\rise_trail_r_reg[3] ;\n wire [5:0]\\rise_trail_r_reg[5] ;\n wire [0:0]\\rise_trail_r_reg[5]_0 ;\n wire [0:0]\\rise_trail_r_reg[5]_1 ;\n wire [0:0]\\rise_trail_r_reg[5]_2 ;\n wire [0:0]\\rise_trail_r_reg[5]_3 ;\n wire rstdiv0_sync_r1_reg_rep;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire run_polarity_ns2_out;\n wire \\run_r[5]_i_2_n_0 ;\n wire \\run_r_reg[0]_0 ;\n wire \\run_r_reg[0]_1 ;\n wire \\run_r_reg[0]_2 ;\n wire \\run_r_reg[2]_0 ;\n wire [4:0]\\run_r_reg[4]_0 ;\n wire \\run_r_reg_n_0_[5] ;\n wire run_too_small_ns;\n wire run_too_small_r3_reg;\n wire run_too_small_r_reg_0;\n wire [16:16]samp_cntr;\n wire [15:0]samp_cntr_ns0;\n wire \\samp_cntr_r[0]_i_1_n_0 ;\n wire \\samp_cntr_r[10]_i_1_n_0 ;\n wire \\samp_cntr_r[11]_i_1_n_0 ;\n wire \\samp_cntr_r[12]_i_1_n_0 ;\n wire \\samp_cntr_r[13]_i_1_n_0 ;\n wire \\samp_cntr_r[14]_i_1_n_0 ;\n wire \\samp_cntr_r[15]_i_1_n_0 ;\n wire \\samp_cntr_r[16]_i_1_n_0 ;\n wire \\samp_cntr_r[1]_i_1_n_0 ;\n wire \\samp_cntr_r[2]_i_1_n_0 ;\n wire \\samp_cntr_r[3]_i_1_n_0 ;\n wire \\samp_cntr_r[4]_i_1_n_0 ;\n wire \\samp_cntr_r[5]_i_1_n_0 ;\n wire \\samp_cntr_r[6]_i_1_n_0 ;\n wire \\samp_cntr_r[7]_i_1_n_0 ;\n wire \\samp_cntr_r[8]_i_1_n_0 ;\n wire \\samp_cntr_r[9]_i_1_n_0 ;\n wire [0:0]\\samp_cntr_r_reg[0]_0 ;\n wire [3:0]\\samp_cntr_r_reg[12]_0 ;\n wire [3:0]\\samp_cntr_r_reg[16]_0 ;\n wire [3:0]\\samp_cntr_r_reg[8]_0 ;\n wire \\samp_cntr_r_reg_n_0_[10] ;\n wire \\samp_cntr_r_reg_n_0_[11] ;\n wire \\samp_cntr_r_reg_n_0_[12] ;\n wire \\samp_cntr_r_reg_n_0_[13] ;\n wire \\samp_cntr_r_reg_n_0_[14] ;\n wire \\samp_cntr_r_reg_n_0_[15] ;\n wire \\samp_cntr_r_reg_n_0_[1] ;\n wire \\samp_cntr_r_reg_n_0_[2] ;\n wire \\samp_cntr_r_reg_n_0_[3] ;\n wire \\samp_cntr_r_reg_n_0_[4] ;\n wire \\samp_cntr_r_reg_n_0_[5] ;\n wire \\samp_cntr_r_reg_n_0_[6] ;\n wire \\samp_cntr_r_reg_n_0_[7] ;\n wire \\samp_cntr_r_reg_n_0_[8] ;\n wire \\samp_cntr_r_reg_n_0_[9] ;\n wire [5:5]samp_wait_r;\n wire \\samp_wait_r[4]_i_2_n_0 ;\n wire \\samp_wait_r[7]_i_1_n_0 ;\n wire \\samp_wait_r_reg[4]_0 ;\n wire \\samp_wait_r_reg[6]_0 ;\n wire [6:0]\\samp_wait_r_reg[7]_0 ;\n wire [17:17]samps_hi;\n wire [17:0]samps_hi_ns0;\n wire \\samps_hi_r[0]_i_1_n_0 ;\n wire \\samps_hi_r[10]_i_1_n_0 ;\n wire \\samps_hi_r[11]_i_1_n_0 ;\n wire \\samps_hi_r[12]_i_1_n_0 ;\n wire \\samps_hi_r[13]_i_1_n_0 ;\n wire \\samps_hi_r[14]_i_1_n_0 ;\n wire \\samps_hi_r[15]_i_1_n_0 ;\n wire \\samps_hi_r[16]_i_1_n_0 ;\n wire \\samps_hi_r[17]_i_1_n_0 ;\n wire \\samps_hi_r[1]_i_1_n_0 ;\n wire \\samps_hi_r[2]_i_1_n_0 ;\n wire \\samps_hi_r[3]_i_1_n_0 ;\n wire \\samps_hi_r[4]_i_1_n_0 ;\n wire \\samps_hi_r[5]_i_1_n_0 ;\n wire \\samps_hi_r[6]_i_1_n_0 ;\n wire \\samps_hi_r[7]_i_1_n_0 ;\n wire \\samps_hi_r[8]_i_1_n_0 ;\n wire \\samps_hi_r[9]_i_1_n_0 ;\n wire [3:0]\\samps_hi_r_reg[11]_0 ;\n wire [3:0]\\samps_hi_r_reg[15]_0 ;\n wire [1:0]\\samps_hi_r_reg[17]_0 ;\n wire [2:0]\\samps_hi_r_reg[3]_0 ;\n wire [3:0]\\samps_hi_r_reg[7]_0 ;\n wire \\samps_hi_r_reg_n_0_[11] ;\n wire \\samps_hi_r_reg_n_0_[12] ;\n wire \\samps_hi_r_reg_n_0_[13] ;\n wire \\samps_hi_r_reg_n_0_[14] ;\n wire \\samps_hi_r_reg_n_0_[15] ;\n wire \\samps_hi_r_reg_n_0_[16] ;\n wire \\samps_hi_r_reg_n_0_[3] ;\n wire \\samps_hi_r_reg_n_0_[4] ;\n wire \\samps_hi_r_reg_n_0_[5] ;\n wire \\samps_hi_r_reg_n_0_[6] ;\n wire \\samps_hi_r_reg_n_0_[7] ;\n wire \\samps_hi_r_reg_n_0_[8] ;\n wire [14:0]samps_lo;\n wire samps_one_ns;\n wire samps_one_r0_carry__0_i_1_n_0;\n wire samps_one_r0_carry__0_i_2_n_0;\n wire samps_one_r0_carry__0_i_3_n_0;\n wire samps_one_r0_carry__0_i_4_n_0;\n wire samps_one_r0_carry__0_i_5_n_0;\n wire samps_one_r0_carry__0_i_6_n_0;\n wire samps_one_r0_carry__0_i_7_n_0;\n wire samps_one_r0_carry__0_n_0;\n wire samps_one_r0_carry__0_n_1;\n wire samps_one_r0_carry__0_n_2;\n wire samps_one_r0_carry__0_n_3;\n wire samps_one_r0_carry__1_i_1_n_0;\n wire samps_one_r0_carry__1_i_2_n_0;\n wire samps_one_r0_carry_i_1_n_0;\n wire samps_one_r0_carry_i_2_n_0;\n wire samps_one_r0_carry_i_3_n_0;\n wire samps_one_r0_carry_i_4_n_0;\n wire samps_one_r0_carry_i_5_n_0;\n wire samps_one_r0_carry_i_6_n_0;\n wire samps_one_r0_carry_i_7_n_0;\n wire samps_one_r0_carry_n_0;\n wire samps_one_r0_carry_n_1;\n wire samps_one_r0_carry_n_2;\n wire samps_one_r0_carry_n_3;\n wire samps_zero_ns;\n wire samps_zero_r0_carry__0_i_1_n_0;\n wire samps_zero_r0_carry__0_i_2_n_0;\n wire samps_zero_r0_carry__0_i_3_n_0;\n wire samps_zero_r0_carry__0_i_5_n_0;\n wire samps_zero_r0_carry__0_i_6_n_0;\n wire samps_zero_r0_carry__0_i_7_n_0;\n wire samps_zero_r0_carry__0_i_8_n_0;\n wire samps_zero_r0_carry__0_n_0;\n wire samps_zero_r0_carry__0_n_1;\n wire samps_zero_r0_carry__0_n_2;\n wire samps_zero_r0_carry__0_n_3;\n wire samps_zero_r0_carry__1_i_1_n_0;\n wire samps_zero_r0_carry__1_i_2_n_0;\n wire samps_zero_r0_carry_i_1_n_0;\n wire samps_zero_r0_carry_i_3_n_0;\n wire samps_zero_r0_carry_i_4_n_0;\n wire samps_zero_r0_carry_i_5_n_0;\n wire samps_zero_r0_carry_i_6_n_0;\n wire samps_zero_r0_carry_i_7_n_0;\n wire samps_zero_r0_carry_i_8_n_0;\n wire samps_zero_r0_carry_n_0;\n wire samps_zero_r0_carry_n_1;\n wire samps_zero_r0_carry_n_2;\n wire samps_zero_r0_carry_n_3;\n wire [3:0]samps_zero_r_reg_0;\n wire [3:0]samps_zero_r_reg_1;\n wire [2:0]samps_zero_r_reg_2;\n wire [2:0]samps_zero_r_reg_3;\n wire [0:0]samps_zero_r_reg_4;\n wire [0:0]samps_zero_r_reg_5;\n wire sm_ns0_carry__0_i_1_n_0;\n wire sm_ns0_carry__0_i_2_n_0;\n wire sm_ns0_carry__0_n_2;\n wire sm_ns0_carry__0_n_3;\n wire sm_ns0_carry_i_1_n_0;\n wire sm_ns0_carry_i_2_n_0;\n wire sm_ns0_carry_i_3_n_0;\n wire sm_ns0_carry_i_4_n_0;\n wire sm_ns0_carry_n_0;\n wire sm_ns0_carry_n_1;\n wire sm_ns0_carry_n_2;\n wire sm_ns0_carry_n_3;\n wire \\sm_r[0]_i_1_n_0 ;\n wire \\sm_r[0]_i_2_n_0 ;\n wire \\sm_r[1]_i_1_n_0 ;\n wire \\sm_r_reg[0]_0 ;\n wire \\sm_r_reg[0]_1 ;\n wire \\tap_r_reg[0]_0 ;\n wire [5:0]trailing_edge0;\n wire [5:0]trailing_edge00_in;\n wire [3:0]NLW_samps_one_r0_carry_O_UNCONNECTED;\n wire [3:0]NLW_samps_one_r0_carry__0_O_UNCONNECTED;\n wire [3:1]NLW_samps_one_r0_carry__1_CO_UNCONNECTED;\n wire [3:0]NLW_samps_one_r0_carry__1_O_UNCONNECTED;\n wire [3:0]NLW_samps_zero_r0_carry_O_UNCONNECTED;\n wire [3:0]NLW_samps_zero_r0_carry__0_O_UNCONNECTED;\n wire [3:1]NLW_samps_zero_r0_carry__1_CO_UNCONNECTED;\n wire [3:0]NLW_samps_zero_r0_carry__1_O_UNCONNECTED;\n wire [3:0]NLW_sm_ns0_carry_O_UNCONNECTED;\n wire [3:2]NLW_sm_ns0_carry__0_CO_UNCONNECTED;\n wire [3:0]NLW_sm_ns0_carry__0_O_UNCONNECTED;\n\n (* SOFT_HLUTNM = \"soft_lutpair450\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\gen_mmcm.mmcm_i_i_1 \n (.I0(\\sm_r_reg[0]_0 ),\n .I1(\\sm_r_reg[0]_1 ),\n .I2(rstdiv0_sync_r1_reg_rep__20),\n .O(\\qcntr_r_reg[0] ));\n LUT6 #(\n .INIT(64'h0000000000000001)) \n i___12_i_1__0\n (.I0(\\samp_wait_r_reg[7]_0 [3]),\n .I1(\\samp_wait_r_reg[7]_0 [0]),\n .I2(\\samp_wait_r_reg[7]_0 [1]),\n .I3(\\samp_wait_r_reg[7]_0 [2]),\n .I4(\\samp_wait_r_reg[7]_0 [4]),\n .I5(samp_wait_r),\n .O(\\samp_wait_r_reg[6]_0 ));\n LUT6 #(\n .INIT(64'h0000000000B80000)) \n i___7_i_1__0\n (.I0(\\run_r_reg[0]_1 ),\n .I1(\\run_r_reg[0]_0 ),\n .I2(\\run_r_reg[0]_2 ),\n .I3(\\sm_r_reg[0]_0 ),\n .I4(\\sm_r_reg[0]_1 ),\n .I5(rstdiv0_sync_r1_reg_rep__20),\n .O(run_too_small_r_reg_0));\n LUT1 #(\n .INIT(2'h1)) \n i__carry__0_i_1\n (.I0(\\run_r_reg[4]_0 [3]),\n .O(DI));\n LUT4 #(\n .INIT(16'h9699)) \n i__carry__0_i_2\n (.I0(\\rise_lead_r_reg[5] [5]),\n .I1(\\run_r_reg_n_0_[5] ),\n .I2(\\rise_lead_r_reg[5] [4]),\n .I3(\\run_r_reg[4]_0 [4]),\n .O(\\rise_trail_r_reg[5]_0 ));\n LUT2 #(\n .INIT(4'h6)) \n i__carry_i_1\n (.I0(\\rise_lead_r_reg[5] [3]),\n .I1(\\run_r_reg[4]_0 [3]),\n .O(\\rise_trail_r_reg[3] ));\n (* SOFT_HLUTNM = \"soft_lutpair457\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\rise_trail_r[0]_i_1 \n (.I0(trailing_edge0[0]),\n .I1(\\rise_trail_r[5]_i_4_n_0 ),\n .I2(trailing_edge00_in[0]),\n .O(\\rise_trail_r_reg[5] [0]));\n (* SOFT_HLUTNM = \"soft_lutpair457\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\rise_trail_r[1]_i_1 \n (.I0(trailing_edge0[1]),\n .I1(\\rise_trail_r[5]_i_4_n_0 ),\n .I2(trailing_edge00_in[1]),\n .O(\\rise_trail_r_reg[5] [1]));\n (* SOFT_HLUTNM = \"soft_lutpair456\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\rise_trail_r[2]_i_1 \n (.I0(trailing_edge0[2]),\n .I1(\\rise_trail_r[5]_i_4_n_0 ),\n .I2(trailing_edge00_in[2]),\n .O(\\rise_trail_r_reg[5] [2]));\n (* SOFT_HLUTNM = \"soft_lutpair456\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\rise_trail_r[3]_i_1 \n (.I0(trailing_edge0[3]),\n .I1(\\rise_trail_r[5]_i_4_n_0 ),\n .I2(trailing_edge00_in[3]),\n .O(\\rise_trail_r_reg[5] [3]));\n (* SOFT_HLUTNM = \"soft_lutpair455\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\rise_trail_r[4]_i_1 \n (.I0(trailing_edge0[4]),\n .I1(\\rise_trail_r[5]_i_4_n_0 ),\n .I2(trailing_edge00_in[4]),\n .O(\\rise_trail_r_reg[5] [4]));\n LUT4 #(\n .INIT(16'h0008)) \n \\rise_trail_r[5]_i_1 \n (.I0(\\run_r_reg[0]_0 ),\n .I1(run_too_small_r_reg_0),\n .I2(ocd_ktap_left_r_reg),\n .I3(ocd_ktap_right_r_reg),\n .O(\\rise_trail_r_reg[0] ));\n LUT5 #(\n .INIT(32'h00800000)) \n \\rise_trail_r[5]_i_1__0 \n (.I0(\\run_r_reg[0]_1 ),\n .I1(\\run_r_reg[0]_0 ),\n .I2(\\tap_r_reg[0]_0 ),\n .I3(rstdiv0_sync_r1_reg_rep__20),\n .I4(ocd_ktap_right_r_reg),\n .O(\\rise_trail_r_reg[5]_2 ));\n LUT5 #(\n .INIT(32'h00800000)) \n \\rise_trail_r[5]_i_1__1 \n (.I0(\\run_r_reg[0]_1 ),\n .I1(\\run_r_reg[0]_0 ),\n .I2(\\tap_r_reg[0]_0 ),\n .I3(rstdiv0_sync_r1_reg_rep__20),\n .I4(ocd_ktap_left_r_reg),\n .O(\\rise_trail_r_reg[5]_3 ));\n (* SOFT_HLUTNM = \"soft_lutpair455\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\rise_trail_r[5]_i_2 \n (.I0(trailing_edge0[5]),\n .I1(\\rise_trail_r[5]_i_4_n_0 ),\n .I2(trailing_edge00_in[5]),\n .O(\\rise_trail_r_reg[5] [5]));\n LUT6 #(\n .INIT(64'h88888888A8AA88A8)) \n \\rise_trail_r[5]_i_4 \n (.I0(\\rise_trail_r[5]_i_6_n_0 ),\n .I1(\\rise_trail_r[5]_i_7_n_0 ),\n .I2(\\rise_trail_r[5]_i_8_n_0 ),\n .I3(\\run_r_reg[4]_0 [3]),\n .I4(\\rise_lead_r_reg[5] [3]),\n .I5(\\rise_trail_r[5]_i_9_n_0 ),\n .O(\\rise_trail_r[5]_i_4_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\rise_trail_r[5]_i_5 \n (.I0(\\run_r_reg_n_0_[5] ),\n .I1(\\rise_lead_r_reg[5] [5]),\n .O(\\rise_trail_r_reg[5]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair451\" *) \n LUT2 #(\n .INIT(4'hB)) \n \\rise_trail_r[5]_i_6 \n (.I0(\\rise_lead_r_reg[5] [5]),\n .I1(\\run_r_reg_n_0_[5] ),\n .O(\\rise_trail_r[5]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair451\" *) \n LUT4 #(\n .INIT(16'h4F44)) \n \\rise_trail_r[5]_i_7 \n (.I0(\\run_r_reg_n_0_[5] ),\n .I1(\\rise_lead_r_reg[5] [5]),\n .I2(\\run_r_reg[4]_0 [4]),\n .I3(\\rise_lead_r_reg[5] [4]),\n .O(\\rise_trail_r[5]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hDF0D4F04DF0DDF0D)) \n \\rise_trail_r[5]_i_8 \n (.I0(\\run_r_reg[4]_0 [1]),\n .I1(\\rise_lead_r_reg[5] [1]),\n .I2(\\run_r_reg[4]_0 [2]),\n .I3(\\rise_lead_r_reg[5] [2]),\n .I4(\\rise_lead_r_reg[5] [0]),\n .I5(\\run_r_reg[4]_0 [0]),\n .O(\\rise_trail_r[5]_i_8_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair454\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\rise_trail_r[5]_i_9 \n (.I0(\\run_r_reg[4]_0 [4]),\n .I1(\\rise_lead_r_reg[5] [4]),\n .O(\\rise_trail_r[5]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'h5151040055550400)) \n run_polarity_r_i_1\n (.I0(rstdiv0_sync_r1_reg_rep__20),\n .I1(\\sm_r_reg[0]_1 ),\n .I2(\\sm_r_reg[0]_0 ),\n .I3(\\run_r_reg[0]_2 ),\n .I4(\\run_r_reg[0]_0 ),\n .I5(\\run_r_reg[0]_1 ),\n .O(run_polarity_ns2_out));\n FDRE #(\n .INIT(1'b0)) \n run_polarity_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(run_polarity_ns2_out),\n .Q(\\run_r_reg[0]_0 ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000333347FF)) \n \\run_r[0]_i_1 \n (.I0(\\run_r_reg[0]_1 ),\n .I1(\\run_r_reg[0]_0 ),\n .I2(\\run_r_reg[0]_2 ),\n .I3(\\tap_r_reg[0]_0 ),\n .I4(rstdiv0_sync_r1_reg_rep__20),\n .I5(\\run_r_reg[4]_0 [0]),\n .O(p_0_in__0[0]));\n LUT3 #(\n .INIT(8'h28)) \n \\run_r[1]_i_1 \n (.I0(\\run_r[5]_i_2_n_0 ),\n .I1(\\run_r_reg[4]_0 [0]),\n .I2(\\run_r_reg[4]_0 [1]),\n .O(p_0_in__0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair448\" *) \n LUT4 #(\n .INIT(16'h2A80)) \n \\run_r[2]_i_1 \n (.I0(\\run_r[5]_i_2_n_0 ),\n .I1(\\run_r_reg[4]_0 [1]),\n .I2(\\run_r_reg[4]_0 [0]),\n .I3(\\run_r_reg[4]_0 [2]),\n .O(p_0_in__0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair448\" *) \n LUT5 #(\n .INIT(32'h2AAA8000)) \n \\run_r[3]_i_1 \n (.I0(\\run_r[5]_i_2_n_0 ),\n .I1(\\run_r_reg[4]_0 [0]),\n .I2(\\run_r_reg[4]_0 [1]),\n .I3(\\run_r_reg[4]_0 [2]),\n .I4(\\run_r_reg[4]_0 [3]),\n .O(p_0_in__0[3]));\n LUT6 #(\n .INIT(64'h2AAAAAAA80000000)) \n \\run_r[4]_i_1 \n (.I0(\\run_r[5]_i_2_n_0 ),\n .I1(\\run_r_reg[4]_0 [2]),\n .I2(\\run_r_reg[4]_0 [1]),\n .I3(\\run_r_reg[4]_0 [0]),\n .I4(\\run_r_reg[4]_0 [3]),\n .I5(\\run_r_reg[4]_0 [4]),\n .O(p_0_in__0[4]));\n (* SOFT_HLUTNM = \"soft_lutpair454\" *) \n LUT4 #(\n .INIT(16'h8A20)) \n \\run_r[5]_i_1 \n (.I0(\\run_r[5]_i_2_n_0 ),\n .I1(\\run_r_reg[2]_0 ),\n .I2(\\run_r_reg[4]_0 [4]),\n .I3(\\run_r_reg_n_0_[5] ),\n .O(p_0_in__0[5]));\n LUT6 #(\n .INIT(64'h5151FBFF5555FBFF)) \n \\run_r[5]_i_2 \n (.I0(rstdiv0_sync_r1_reg_rep__20),\n .I1(\\sm_r_reg[0]_1 ),\n .I2(\\sm_r_reg[0]_0 ),\n .I3(\\run_r_reg[0]_2 ),\n .I4(\\run_r_reg[0]_0 ),\n .I5(\\run_r_reg[0]_1 ),\n .O(\\run_r[5]_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\run_r_reg[0] \n (.C(CLK),\n .CE(\\tap_r_reg[0]_0 ),\n .D(p_0_in__0[0]),\n .Q(\\run_r_reg[4]_0 [0]),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE #(\n .INIT(1'b0)) \n \\run_r_reg[1] \n (.C(CLK),\n .CE(\\tap_r_reg[0]_0 ),\n .D(p_0_in__0[1]),\n .Q(\\run_r_reg[4]_0 [1]),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE #(\n .INIT(1'b0)) \n \\run_r_reg[2] \n (.C(CLK),\n .CE(\\tap_r_reg[0]_0 ),\n .D(p_0_in__0[2]),\n .Q(\\run_r_reg[4]_0 [2]),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE #(\n .INIT(1'b0)) \n \\run_r_reg[3] \n (.C(CLK),\n .CE(\\tap_r_reg[0]_0 ),\n .D(p_0_in__0[3]),\n .Q(\\run_r_reg[4]_0 [3]),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE #(\n .INIT(1'b0)) \n \\run_r_reg[4] \n (.C(CLK),\n .CE(\\tap_r_reg[0]_0 ),\n .D(p_0_in__0[4]),\n .Q(\\run_r_reg[4]_0 [4]),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE #(\n .INIT(1'b0)) \n \\run_r_reg[5] \n (.C(CLK),\n .CE(\\tap_r_reg[0]_0 ),\n .D(p_0_in__0[5]),\n .Q(\\run_r_reg_n_0_[5] ),\n .R(rstdiv0_sync_r1_reg_rep));\n LUT6 #(\n .INIT(64'h0002020202020202)) \n run_too_small_r_i_1\n (.I0(run_too_small_r_reg_0),\n .I1(\\run_r_reg[4]_0 [4]),\n .I2(\\run_r_reg_n_0_[5] ),\n .I3(\\run_r_reg[4]_0 [3]),\n .I4(\\run_r_reg[4]_0 [2]),\n .I5(\\run_r_reg[4]_0 [1]),\n .O(run_too_small_ns));\n FDRE #(\n .INIT(1'b0)) \n run_too_small_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(run_too_small_ns),\n .Q(run_too_small_r3_reg),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h1)) \n \\samp_cntr_r[0]_i_1 \n (.I0(\\sm_r_reg[0]_1 ),\n .I1(\\samp_cntr_r_reg[0]_0 ),\n .O(\\samp_cntr_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair474\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samp_cntr_r[10]_i_1 \n (.I0(samp_cntr_ns0[9]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samp_cntr_r[10]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair466\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samp_cntr_r[11]_i_1 \n (.I0(samp_cntr_ns0[10]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samp_cntr_r[11]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair469\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samp_cntr_r[12]_i_1 \n (.I0(samp_cntr_ns0[11]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samp_cntr_r[12]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_cntr_r[12]_i_3 \n (.I0(\\samp_cntr_r_reg_n_0_[12] ),\n .O(\\samp_cntr_r_reg[12]_0 [3]));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_cntr_r[12]_i_4 \n (.I0(\\samp_cntr_r_reg_n_0_[11] ),\n .O(\\samp_cntr_r_reg[12]_0 [2]));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_cntr_r[12]_i_5 \n (.I0(\\samp_cntr_r_reg_n_0_[10] ),\n .O(\\samp_cntr_r_reg[12]_0 [1]));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_cntr_r[12]_i_6 \n (.I0(\\samp_cntr_r_reg_n_0_[9] ),\n .O(\\samp_cntr_r_reg[12]_0 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair470\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samp_cntr_r[13]_i_1 \n (.I0(samp_cntr_ns0[12]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samp_cntr_r[13]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair470\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samp_cntr_r[14]_i_1 \n (.I0(samp_cntr_ns0[13]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samp_cntr_r[14]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair473\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samp_cntr_r[15]_i_1 \n (.I0(samp_cntr_ns0[14]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samp_cntr_r[15]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair471\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samp_cntr_r[16]_i_1 \n (.I0(samp_cntr_ns0[15]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samp_cntr_r[16]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_cntr_r[16]_i_3 \n (.I0(samp_cntr),\n .O(\\samp_cntr_r_reg[16]_0 [3]));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_cntr_r[16]_i_4 \n (.I0(\\samp_cntr_r_reg_n_0_[15] ),\n .O(\\samp_cntr_r_reg[16]_0 [2]));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_cntr_r[16]_i_5 \n (.I0(\\samp_cntr_r_reg_n_0_[14] ),\n .O(\\samp_cntr_r_reg[16]_0 [1]));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_cntr_r[16]_i_6 \n (.I0(\\samp_cntr_r_reg_n_0_[13] ),\n .O(\\samp_cntr_r_reg[16]_0 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair463\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samp_cntr_r[1]_i_1 \n (.I0(samp_cntr_ns0[0]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samp_cntr_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair461\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samp_cntr_r[2]_i_1 \n (.I0(samp_cntr_ns0[1]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samp_cntr_r[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair465\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samp_cntr_r[3]_i_1 \n (.I0(samp_cntr_ns0[2]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samp_cntr_r[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair474\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samp_cntr_r[4]_i_1 \n (.I0(samp_cntr_ns0[3]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samp_cntr_r[4]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_cntr_r[4]_i_3 \n (.I0(\\samp_cntr_r_reg_n_0_[4] ),\n .O(S[3]));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_cntr_r[4]_i_4 \n (.I0(\\samp_cntr_r_reg_n_0_[3] ),\n .O(S[2]));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_cntr_r[4]_i_5 \n (.I0(\\samp_cntr_r_reg_n_0_[2] ),\n .O(S[1]));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_cntr_r[4]_i_6 \n (.I0(\\samp_cntr_r_reg_n_0_[1] ),\n .O(S[0]));\n (* SOFT_HLUTNM = \"soft_lutpair464\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samp_cntr_r[5]_i_1 \n (.I0(samp_cntr_ns0[4]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samp_cntr_r[5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair468\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samp_cntr_r[6]_i_1 \n (.I0(samp_cntr_ns0[5]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samp_cntr_r[6]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair472\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samp_cntr_r[7]_i_1 \n (.I0(samp_cntr_ns0[6]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samp_cntr_r[7]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair459\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samp_cntr_r[8]_i_1 \n (.I0(samp_cntr_ns0[7]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samp_cntr_r[8]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_cntr_r[8]_i_3 \n (.I0(\\samp_cntr_r_reg_n_0_[8] ),\n .O(\\samp_cntr_r_reg[8]_0 [3]));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_cntr_r[8]_i_4 \n (.I0(\\samp_cntr_r_reg_n_0_[7] ),\n .O(\\samp_cntr_r_reg[8]_0 [2]));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_cntr_r[8]_i_5 \n (.I0(\\samp_cntr_r_reg_n_0_[6] ),\n .O(\\samp_cntr_r_reg[8]_0 [1]));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_cntr_r[8]_i_6 \n (.I0(\\samp_cntr_r_reg_n_0_[5] ),\n .O(\\samp_cntr_r_reg[8]_0 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair462\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samp_cntr_r[9]_i_1 \n (.I0(samp_cntr_ns0[8]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samp_cntr_r[9]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\samp_cntr_r_reg[0] \n (.C(CLK),\n .CE(E),\n .D(\\samp_cntr_r[0]_i_1_n_0 ),\n .Q(\\samp_cntr_r_reg[0]_0 ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\samp_cntr_r_reg[10] \n (.C(CLK),\n .CE(E),\n .D(\\samp_cntr_r[10]_i_1_n_0 ),\n .Q(\\samp_cntr_r_reg_n_0_[10] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\samp_cntr_r_reg[11] \n (.C(CLK),\n .CE(E),\n .D(\\samp_cntr_r[11]_i_1_n_0 ),\n .Q(\\samp_cntr_r_reg_n_0_[11] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\samp_cntr_r_reg[12] \n (.C(CLK),\n .CE(E),\n .D(\\samp_cntr_r[12]_i_1_n_0 ),\n .Q(\\samp_cntr_r_reg_n_0_[12] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\samp_cntr_r_reg[13] \n (.C(CLK),\n .CE(E),\n .D(\\samp_cntr_r[13]_i_1_n_0 ),\n .Q(\\samp_cntr_r_reg_n_0_[13] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\samp_cntr_r_reg[14] \n (.C(CLK),\n .CE(E),\n .D(\\samp_cntr_r[14]_i_1_n_0 ),\n .Q(\\samp_cntr_r_reg_n_0_[14] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\samp_cntr_r_reg[15] \n (.C(CLK),\n .CE(E),\n .D(\\samp_cntr_r[15]_i_1_n_0 ),\n .Q(\\samp_cntr_r_reg_n_0_[15] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\samp_cntr_r_reg[16] \n (.C(CLK),\n .CE(E),\n .D(\\samp_cntr_r[16]_i_1_n_0 ),\n .Q(samp_cntr),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\samp_cntr_r_reg[1] \n (.C(CLK),\n .CE(E),\n .D(\\samp_cntr_r[1]_i_1_n_0 ),\n .Q(\\samp_cntr_r_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\samp_cntr_r_reg[2] \n (.C(CLK),\n .CE(E),\n .D(\\samp_cntr_r[2]_i_1_n_0 ),\n .Q(\\samp_cntr_r_reg_n_0_[2] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\samp_cntr_r_reg[3] \n (.C(CLK),\n .CE(E),\n .D(\\samp_cntr_r[3]_i_1_n_0 ),\n .Q(\\samp_cntr_r_reg_n_0_[3] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\samp_cntr_r_reg[4] \n (.C(CLK),\n .CE(E),\n .D(\\samp_cntr_r[4]_i_1_n_0 ),\n .Q(\\samp_cntr_r_reg_n_0_[4] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\samp_cntr_r_reg[5] \n (.C(CLK),\n .CE(E),\n .D(\\samp_cntr_r[5]_i_1_n_0 ),\n .Q(\\samp_cntr_r_reg_n_0_[5] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\samp_cntr_r_reg[6] \n (.C(CLK),\n .CE(E),\n .D(\\samp_cntr_r[6]_i_1_n_0 ),\n .Q(\\samp_cntr_r_reg_n_0_[6] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\samp_cntr_r_reg[7] \n (.C(CLK),\n .CE(E),\n .D(\\samp_cntr_r[7]_i_1_n_0 ),\n .Q(\\samp_cntr_r_reg_n_0_[7] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\samp_cntr_r_reg[8] \n (.C(CLK),\n .CE(E),\n .D(\\samp_cntr_r[8]_i_1_n_0 ),\n .Q(\\samp_cntr_r_reg_n_0_[8] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\samp_cntr_r_reg[9] \n (.C(CLK),\n .CE(E),\n .D(\\samp_cntr_r[9]_i_1_n_0 ),\n .Q(\\samp_cntr_r_reg_n_0_[9] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n (* SOFT_HLUTNM = \"soft_lutpair453\" *) \n LUT3 #(\n .INIT(8'h8F)) \n \\samp_wait_r[0]_i_1 \n (.I0(\\sm_r_reg[0]_1 ),\n .I1(\\sm_r_reg[0]_0 ),\n .I2(\\samp_wait_r_reg[7]_0 [0]),\n .O(p_1_in[0]));\n (* SOFT_HLUTNM = \"soft_lutpair453\" *) \n LUT4 #(\n .INIT(16'hF88F)) \n \\samp_wait_r[1]_i_1 \n (.I0(\\sm_r_reg[0]_1 ),\n .I1(\\sm_r_reg[0]_0 ),\n .I2(\\samp_wait_r_reg[7]_0 [1]),\n .I3(\\samp_wait_r_reg[7]_0 [0]),\n .O(p_1_in[1]));\n LUT6 #(\n .INIT(64'hFFFFFFFEAAAAAAAB)) \n \\samp_wait_r[4]_i_1 \n (.I0(\\samp_wait_r[4]_i_2_n_0 ),\n .I1(\\samp_wait_r_reg[7]_0 [3]),\n .I2(\\samp_wait_r_reg[7]_0 [0]),\n .I3(\\samp_wait_r_reg[7]_0 [1]),\n .I4(\\samp_wait_r_reg[7]_0 [2]),\n .I5(\\samp_wait_r_reg[7]_0 [4]),\n .O(p_1_in[4]));\n (* SOFT_HLUTNM = \"soft_lutpair452\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\samp_wait_r[4]_i_2 \n (.I0(\\sm_r_reg[0]_0 ),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samp_wait_r[4]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair452\" *) \n LUT4 #(\n .INIT(16'h8FF8)) \n \\samp_wait_r[5]_i_1 \n (.I0(\\sm_r_reg[0]_1 ),\n .I1(\\sm_r_reg[0]_0 ),\n .I2(\\samp_wait_r_reg[4]_0 ),\n .I3(samp_wait_r),\n .O(p_1_in[5]));\n (* SOFT_HLUTNM = \"soft_lutpair447\" *) \n LUT4 #(\n .INIT(16'h8FF8)) \n \\samp_wait_r[6]_i_1 \n (.I0(\\sm_r_reg[0]_1 ),\n .I1(\\sm_r_reg[0]_0 ),\n .I2(\\samp_wait_r_reg[6]_0 ),\n .I3(\\samp_wait_r_reg[7]_0 [5]),\n .O(p_1_in[6]));\n LUT5 #(\n .INIT(32'hFFFFFF8F)) \n \\samp_wait_r[7]_i_1 \n (.I0(\\sm_r_reg[0]_1 ),\n .I1(\\sm_r_reg[0]_0 ),\n .I2(\\samp_wait_r_reg[6]_0 ),\n .I3(\\samp_wait_r_reg[7]_0 [5]),\n .I4(\\samp_wait_r_reg[7]_0 [6]),\n .O(\\samp_wait_r[7]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair447\" *) \n LUT5 #(\n .INIT(32'hFF8F88F8)) \n \\samp_wait_r[7]_i_2 \n (.I0(\\sm_r_reg[0]_1 ),\n .I1(\\sm_r_reg[0]_0 ),\n .I2(\\samp_wait_r_reg[6]_0 ),\n .I3(\\samp_wait_r_reg[7]_0 [5]),\n .I4(\\samp_wait_r_reg[7]_0 [6]),\n .O(p_1_in[7]));\n FDRE #(\n .INIT(1'b0)) \n \\samp_wait_r_reg[0] \n (.C(CLK),\n .CE(\\samp_wait_r[7]_i_1_n_0 ),\n .D(p_1_in[0]),\n .Q(\\samp_wait_r_reg[7]_0 [0]),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE #(\n .INIT(1'b0)) \n \\samp_wait_r_reg[1] \n (.C(CLK),\n .CE(\\samp_wait_r[7]_i_1_n_0 ),\n .D(p_1_in[1]),\n .Q(\\samp_wait_r_reg[7]_0 [1]),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE #(\n .INIT(1'b0)) \n \\samp_wait_r_reg[2] \n (.C(CLK),\n .CE(\\samp_wait_r[7]_i_1_n_0 ),\n .D(D[0]),\n .Q(\\samp_wait_r_reg[7]_0 [2]),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE #(\n .INIT(1'b0)) \n \\samp_wait_r_reg[3] \n (.C(CLK),\n .CE(\\samp_wait_r[7]_i_1_n_0 ),\n .D(D[1]),\n .Q(\\samp_wait_r_reg[7]_0 [3]),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE #(\n .INIT(1'b0)) \n \\samp_wait_r_reg[4] \n (.C(CLK),\n .CE(\\samp_wait_r[7]_i_1_n_0 ),\n .D(p_1_in[4]),\n .Q(\\samp_wait_r_reg[7]_0 [4]),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE #(\n .INIT(1'b0)) \n \\samp_wait_r_reg[5] \n (.C(CLK),\n .CE(\\samp_wait_r[7]_i_1_n_0 ),\n .D(p_1_in[5]),\n .Q(samp_wait_r),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE #(\n .INIT(1'b0)) \n \\samp_wait_r_reg[6] \n (.C(CLK),\n .CE(\\samp_wait_r[7]_i_1_n_0 ),\n .D(p_1_in[6]),\n .Q(\\samp_wait_r_reg[7]_0 [5]),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE #(\n .INIT(1'b0)) \n \\samp_wait_r_reg[7] \n (.C(CLK),\n .CE(\\samp_wait_r[7]_i_1_n_0 ),\n .D(p_1_in[7]),\n .Q(\\samp_wait_r_reg[7]_0 [6]),\n .R(rstdiv0_sync_r1_reg_rep));\n (* SOFT_HLUTNM = \"soft_lutpair471\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[0]_i_1 \n (.I0(samps_hi_ns0[0]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair467\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[10]_i_1 \n (.I0(samps_hi_ns0[10]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[10]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair465\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[11]_i_1 \n (.I0(samps_hi_ns0[11]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[11]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samps_hi_r[11]_i_3 \n (.I0(\\samps_hi_r_reg_n_0_[11] ),\n .O(\\samps_hi_r_reg[11]_0 [3]));\n LUT1 #(\n .INIT(2'h2)) \n \\samps_hi_r[11]_i_4 \n (.I0(Q[4]),\n .O(\\samps_hi_r_reg[11]_0 [2]));\n LUT1 #(\n .INIT(2'h2)) \n \\samps_hi_r[11]_i_5 \n (.I0(Q[3]),\n .O(\\samps_hi_r_reg[11]_0 [1]));\n LUT1 #(\n .INIT(2'h2)) \n \\samps_hi_r[11]_i_6 \n (.I0(\\samps_hi_r_reg_n_0_[8] ),\n .O(\\samps_hi_r_reg[11]_0 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair464\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[12]_i_1 \n (.I0(samps_hi_ns0[12]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[12]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair459\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[13]_i_1 \n (.I0(samps_hi_ns0[13]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[13]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair463\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[14]_i_1 \n (.I0(samps_hi_ns0[14]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[14]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair461\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[15]_i_1 \n (.I0(samps_hi_ns0[15]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[15]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samps_hi_r[15]_i_3 \n (.I0(\\samps_hi_r_reg_n_0_[15] ),\n .O(\\samps_hi_r_reg[15]_0 [3]));\n LUT1 #(\n .INIT(2'h2)) \n \\samps_hi_r[15]_i_4 \n (.I0(\\samps_hi_r_reg_n_0_[14] ),\n .O(\\samps_hi_r_reg[15]_0 [2]));\n LUT1 #(\n .INIT(2'h2)) \n \\samps_hi_r[15]_i_5 \n (.I0(\\samps_hi_r_reg_n_0_[13] ),\n .O(\\samps_hi_r_reg[15]_0 [1]));\n LUT1 #(\n .INIT(2'h2)) \n \\samps_hi_r[15]_i_6 \n (.I0(\\samps_hi_r_reg_n_0_[12] ),\n .O(\\samps_hi_r_reg[15]_0 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair460\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[16]_i_1 \n (.I0(samps_hi_ns0[16]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[16]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair458\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[17]_i_1 \n (.I0(samps_hi_ns0[17]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[17]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samps_hi_r[17]_i_3 \n (.I0(samps_hi),\n .O(\\samps_hi_r_reg[17]_0 [1]));\n LUT1 #(\n .INIT(2'h2)) \n \\samps_hi_r[17]_i_4 \n (.I0(\\samps_hi_r_reg_n_0_[16] ),\n .O(\\samps_hi_r_reg[17]_0 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair460\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[1]_i_1 \n (.I0(samps_hi_ns0[1]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair458\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[2]_i_1 \n (.I0(samps_hi_ns0[2]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair467\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[3]_i_1 \n (.I0(samps_hi_ns0[3]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[3]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samps_hi_r[3]_i_3 \n (.I0(\\samps_hi_r_reg_n_0_[3] ),\n .O(\\samps_hi_r_reg[3]_0 [2]));\n LUT1 #(\n .INIT(2'h2)) \n \\samps_hi_r[3]_i_4 \n (.I0(Q[2]),\n .O(\\samps_hi_r_reg[3]_0 [1]));\n LUT1 #(\n .INIT(2'h2)) \n \\samps_hi_r[3]_i_5 \n (.I0(Q[1]),\n .O(\\samps_hi_r_reg[3]_0 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair473\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[4]_i_1 \n (.I0(samps_hi_ns0[4]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[4]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair466\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[5]_i_1 \n (.I0(samps_hi_ns0[5]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair472\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[6]_i_1 \n (.I0(samps_hi_ns0[6]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[6]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair469\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[7]_i_1 \n (.I0(samps_hi_ns0[7]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[7]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samps_hi_r[7]_i_3 \n (.I0(\\samps_hi_r_reg_n_0_[7] ),\n .O(\\samps_hi_r_reg[7]_0 [3]));\n LUT1 #(\n .INIT(2'h2)) \n \\samps_hi_r[7]_i_4 \n (.I0(\\samps_hi_r_reg_n_0_[6] ),\n .O(\\samps_hi_r_reg[7]_0 [2]));\n LUT1 #(\n .INIT(2'h2)) \n \\samps_hi_r[7]_i_5 \n (.I0(\\samps_hi_r_reg_n_0_[5] ),\n .O(\\samps_hi_r_reg[7]_0 [1]));\n LUT1 #(\n .INIT(2'h2)) \n \\samps_hi_r[7]_i_6 \n (.I0(\\samps_hi_r_reg_n_0_[4] ),\n .O(\\samps_hi_r_reg[7]_0 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair468\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[8]_i_1 \n (.I0(samps_hi_ns0[8]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[8]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair462\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[9]_i_1 \n (.I0(samps_hi_ns0[9]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[9]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\samps_hi_r_reg[0] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[0]_i_1_n_0 ),\n .Q(Q[0]),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\samps_hi_r_reg[10] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[10]_i_1_n_0 ),\n .Q(Q[4]),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\samps_hi_r_reg[11] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[11]_i_1_n_0 ),\n .Q(\\samps_hi_r_reg_n_0_[11] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\samps_hi_r_reg[12] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[12]_i_1_n_0 ),\n .Q(\\samps_hi_r_reg_n_0_[12] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\samps_hi_r_reg[13] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[13]_i_1_n_0 ),\n .Q(\\samps_hi_r_reg_n_0_[13] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\samps_hi_r_reg[14] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[14]_i_1_n_0 ),\n .Q(\\samps_hi_r_reg_n_0_[14] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\samps_hi_r_reg[15] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[15]_i_1_n_0 ),\n .Q(\\samps_hi_r_reg_n_0_[15] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\samps_hi_r_reg[16] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[16]_i_1_n_0 ),\n .Q(\\samps_hi_r_reg_n_0_[16] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\samps_hi_r_reg[17] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[17]_i_1_n_0 ),\n .Q(samps_hi),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\samps_hi_r_reg[1] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[1]_i_1_n_0 ),\n .Q(Q[1]),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\samps_hi_r_reg[2] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[2]_i_1_n_0 ),\n .Q(Q[2]),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\samps_hi_r_reg[3] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[3]_i_1_n_0 ),\n .Q(\\samps_hi_r_reg_n_0_[3] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\samps_hi_r_reg[4] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[4]_i_1_n_0 ),\n .Q(\\samps_hi_r_reg_n_0_[4] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\samps_hi_r_reg[5] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[5]_i_1_n_0 ),\n .Q(\\samps_hi_r_reg_n_0_[5] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\samps_hi_r_reg[6] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[6]_i_1_n_0 ),\n .Q(\\samps_hi_r_reg_n_0_[6] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\samps_hi_r_reg[7] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[7]_i_1_n_0 ),\n .Q(\\samps_hi_r_reg_n_0_[7] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\samps_hi_r_reg[8] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[8]_i_1_n_0 ),\n .Q(\\samps_hi_r_reg_n_0_[8] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n \\samps_hi_r_reg[9] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[9]_i_1_n_0 ),\n .Q(Q[3]),\n .R(rstdiv0_sync_r1_reg_rep__0));\n CARRY4 samps_one_r0_carry\n (.CI(1'b0),\n .CO({samps_one_r0_carry_n_0,samps_one_r0_carry_n_1,samps_one_r0_carry_n_2,samps_one_r0_carry_n_3}),\n .CYINIT(1'b1),\n .DI({samps_one_r0_carry_i_1_n_0,\\samps_hi_r_reg_n_0_[5] ,samps_one_r0_carry_i_2_n_0,samps_one_r0_carry_i_3_n_0}),\n .O(NLW_samps_one_r0_carry_O_UNCONNECTED[3:0]),\n .S({samps_one_r0_carry_i_4_n_0,samps_one_r0_carry_i_5_n_0,samps_one_r0_carry_i_6_n_0,samps_one_r0_carry_i_7_n_0}));\n CARRY4 samps_one_r0_carry__0\n (.CI(samps_one_r0_carry_n_0),\n .CO({samps_one_r0_carry__0_n_0,samps_one_r0_carry__0_n_1,samps_one_r0_carry__0_n_2,samps_one_r0_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({samps_one_r0_carry__0_i_1_n_0,samps_one_r0_carry__0_i_2_n_0,samps_one_r0_carry__0_i_3_n_0,Q[3]}),\n .O(NLW_samps_one_r0_carry__0_O_UNCONNECTED[3:0]),\n .S({samps_one_r0_carry__0_i_4_n_0,samps_one_r0_carry__0_i_5_n_0,samps_one_r0_carry__0_i_6_n_0,samps_one_r0_carry__0_i_7_n_0}));\n LUT2 #(\n .INIT(4'hE)) \n samps_one_r0_carry__0_i_1\n (.I0(\\samps_hi_r_reg_n_0_[15] ),\n .I1(\\samps_hi_r_reg_n_0_[14] ),\n .O(samps_one_r0_carry__0_i_1_n_0));\n LUT2 #(\n .INIT(4'hE)) \n samps_one_r0_carry__0_i_2\n (.I0(\\samps_hi_r_reg_n_0_[13] ),\n .I1(\\samps_hi_r_reg_n_0_[12] ),\n .O(samps_one_r0_carry__0_i_2_n_0));\n LUT2 #(\n .INIT(4'hE)) \n samps_one_r0_carry__0_i_3\n (.I0(\\samps_hi_r_reg_n_0_[11] ),\n .I1(Q[4]),\n .O(samps_one_r0_carry__0_i_3_n_0));\n LUT2 #(\n .INIT(4'h1)) \n samps_one_r0_carry__0_i_4\n (.I0(\\samps_hi_r_reg_n_0_[14] ),\n .I1(\\samps_hi_r_reg_n_0_[15] ),\n .O(samps_one_r0_carry__0_i_4_n_0));\n LUT2 #(\n .INIT(4'h1)) \n samps_one_r0_carry__0_i_5\n (.I0(\\samps_hi_r_reg_n_0_[12] ),\n .I1(\\samps_hi_r_reg_n_0_[13] ),\n .O(samps_one_r0_carry__0_i_5_n_0));\n LUT2 #(\n .INIT(4'h1)) \n samps_one_r0_carry__0_i_6\n (.I0(Q[4]),\n .I1(\\samps_hi_r_reg_n_0_[11] ),\n .O(samps_one_r0_carry__0_i_6_n_0));\n LUT2 #(\n .INIT(4'h2)) \n samps_one_r0_carry__0_i_7\n (.I0(\\samps_hi_r_reg_n_0_[8] ),\n .I1(Q[3]),\n .O(samps_one_r0_carry__0_i_7_n_0));\n CARRY4 samps_one_r0_carry__1\n (.CI(samps_one_r0_carry__0_n_0),\n .CO({NLW_samps_one_r0_carry__1_CO_UNCONNECTED[3:1],samps_one_ns}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,samps_one_r0_carry__1_i_1_n_0}),\n .O(NLW_samps_one_r0_carry__1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,1'b0,samps_one_r0_carry__1_i_2_n_0}));\n LUT2 #(\n .INIT(4'hE)) \n samps_one_r0_carry__1_i_1\n (.I0(samps_hi),\n .I1(\\samps_hi_r_reg_n_0_[16] ),\n .O(samps_one_r0_carry__1_i_1_n_0));\n LUT2 #(\n .INIT(4'h1)) \n samps_one_r0_carry__1_i_2\n (.I0(\\samps_hi_r_reg_n_0_[16] ),\n .I1(samps_hi),\n .O(samps_one_r0_carry__1_i_2_n_0));\n LUT2 #(\n .INIT(4'h8)) \n samps_one_r0_carry_i_1\n (.I0(\\samps_hi_r_reg_n_0_[7] ),\n .I1(\\samps_hi_r_reg_n_0_[6] ),\n .O(samps_one_r0_carry_i_1_n_0));\n LUT2 #(\n .INIT(4'h8)) \n samps_one_r0_carry_i_2\n (.I0(\\samps_hi_r_reg_n_0_[3] ),\n .I1(Q[2]),\n .O(samps_one_r0_carry_i_2_n_0));\n LUT2 #(\n .INIT(4'h8)) \n samps_one_r0_carry_i_3\n (.I0(Q[0]),\n .I1(Q[1]),\n .O(samps_one_r0_carry_i_3_n_0));\n LUT2 #(\n .INIT(4'h2)) \n samps_one_r0_carry_i_4\n (.I0(\\samps_hi_r_reg_n_0_[7] ),\n .I1(\\samps_hi_r_reg_n_0_[6] ),\n .O(samps_one_r0_carry_i_4_n_0));\n LUT2 #(\n .INIT(4'h2)) \n samps_one_r0_carry_i_5\n (.I0(\\samps_hi_r_reg_n_0_[4] ),\n .I1(\\samps_hi_r_reg_n_0_[5] ),\n .O(samps_one_r0_carry_i_5_n_0));\n LUT2 #(\n .INIT(4'h2)) \n samps_one_r0_carry_i_6\n (.I0(\\samps_hi_r_reg_n_0_[3] ),\n .I1(Q[2]),\n .O(samps_one_r0_carry_i_6_n_0));\n LUT2 #(\n .INIT(4'h2)) \n samps_one_r0_carry_i_7\n (.I0(Q[1]),\n .I1(Q[0]),\n .O(samps_one_r0_carry_i_7_n_0));\n FDRE #(\n .INIT(1'b0)) \n samps_one_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(samps_one_ns),\n .Q(\\run_r_reg[0]_2 ),\n .R(1'b0));\n CARRY4 samps_zero_r0_carry\n (.CI(1'b0),\n .CO({samps_zero_r0_carry_n_0,samps_zero_r0_carry_n_1,samps_zero_r0_carry_n_2,samps_zero_r0_carry_n_3}),\n .CYINIT(1'b1),\n .DI({samps_zero_r0_carry_i_1_n_0,samps_lo[2],samps_zero_r0_carry_i_3_n_0,samps_zero_r0_carry_i_4_n_0}),\n .O(NLW_samps_zero_r0_carry_O_UNCONNECTED[3:0]),\n .S({samps_zero_r0_carry_i_5_n_0,samps_zero_r0_carry_i_6_n_0,samps_zero_r0_carry_i_7_n_0,samps_zero_r0_carry_i_8_n_0}));\n CARRY4 samps_zero_r0_carry__0\n (.CI(samps_zero_r0_carry_n_0),\n .CO({samps_zero_r0_carry__0_n_0,samps_zero_r0_carry__0_n_1,samps_zero_r0_carry__0_n_2,samps_zero_r0_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({samps_zero_r0_carry__0_i_1_n_0,samps_zero_r0_carry__0_i_2_n_0,samps_zero_r0_carry__0_i_3_n_0,samps_lo[6]}),\n .O(NLW_samps_zero_r0_carry__0_O_UNCONNECTED[3:0]),\n .S({samps_zero_r0_carry__0_i_5_n_0,samps_zero_r0_carry__0_i_6_n_0,samps_zero_r0_carry__0_i_7_n_0,samps_zero_r0_carry__0_i_8_n_0}));\n LUT2 #(\n .INIT(4'hE)) \n samps_zero_r0_carry__0_i_1\n (.I0(samps_lo[12]),\n .I1(samps_lo[11]),\n .O(samps_zero_r0_carry__0_i_1_n_0));\n LUT1 #(\n .INIT(2'h2)) \n samps_zero_r0_carry__0_i_11\n (.I0(Q[3]),\n .O(samps_zero_r_reg_0[3]));\n LUT1 #(\n .INIT(2'h1)) \n samps_zero_r0_carry__0_i_12\n (.I0(\\samps_hi_r_reg_n_0_[8] ),\n .O(samps_zero_r_reg_0[2]));\n LUT1 #(\n .INIT(2'h1)) \n samps_zero_r0_carry__0_i_13\n (.I0(\\samps_hi_r_reg_n_0_[7] ),\n .O(samps_zero_r_reg_0[1]));\n LUT1 #(\n .INIT(2'h1)) \n samps_zero_r0_carry__0_i_14\n (.I0(\\samps_hi_r_reg_n_0_[6] ),\n .O(samps_zero_r_reg_0[0]));\n LUT1 #(\n .INIT(2'h1)) \n samps_zero_r0_carry__0_i_15\n (.I0(samps_hi),\n .O(samps_zero_r_reg_1[3]));\n LUT1 #(\n .INIT(2'h1)) \n samps_zero_r0_carry__0_i_16\n (.I0(\\samps_hi_r_reg_n_0_[16] ),\n .O(samps_zero_r_reg_1[2]));\n LUT1 #(\n .INIT(2'h1)) \n samps_zero_r0_carry__0_i_17\n (.I0(\\samps_hi_r_reg_n_0_[15] ),\n .O(samps_zero_r_reg_1[1]));\n LUT1 #(\n .INIT(2'h1)) \n samps_zero_r0_carry__0_i_18\n (.I0(\\samps_hi_r_reg_n_0_[14] ),\n .O(samps_zero_r_reg_1[0]));\n LUT1 #(\n .INIT(2'h1)) \n samps_zero_r0_carry__0_i_19\n (.I0(Q[3]),\n .O(samps_zero_r_reg_5));\n LUT2 #(\n .INIT(4'hE)) \n samps_zero_r0_carry__0_i_2\n (.I0(samps_lo[10]),\n .I1(samps_lo[9]),\n .O(samps_zero_r0_carry__0_i_2_n_0));\n LUT1 #(\n .INIT(2'h1)) \n samps_zero_r0_carry__0_i_20\n (.I0(\\samps_hi_r_reg_n_0_[13] ),\n .O(samps_zero_r_reg_2[2]));\n LUT1 #(\n .INIT(2'h1)) \n samps_zero_r0_carry__0_i_21\n (.I0(\\samps_hi_r_reg_n_0_[12] ),\n .O(samps_zero_r_reg_2[1]));\n LUT1 #(\n .INIT(2'h1)) \n samps_zero_r0_carry__0_i_22\n (.I0(\\samps_hi_r_reg_n_0_[11] ),\n .O(samps_zero_r_reg_2[0]));\n LUT2 #(\n .INIT(4'hE)) \n samps_zero_r0_carry__0_i_3\n (.I0(samps_lo[8]),\n .I1(samps_lo[7]),\n .O(samps_zero_r0_carry__0_i_3_n_0));\n LUT2 #(\n .INIT(4'h1)) \n samps_zero_r0_carry__0_i_5\n (.I0(samps_lo[11]),\n .I1(samps_lo[12]),\n .O(samps_zero_r0_carry__0_i_5_n_0));\n LUT2 #(\n .INIT(4'h1)) \n samps_zero_r0_carry__0_i_6\n (.I0(samps_lo[9]),\n .I1(samps_lo[10]),\n .O(samps_zero_r0_carry__0_i_6_n_0));\n LUT2 #(\n .INIT(4'h1)) \n samps_zero_r0_carry__0_i_7\n (.I0(samps_lo[7]),\n .I1(samps_lo[8]),\n .O(samps_zero_r0_carry__0_i_7_n_0));\n LUT2 #(\n .INIT(4'h2)) \n samps_zero_r0_carry__0_i_8\n (.I0(samps_lo[5]),\n .I1(samps_lo[6]),\n .O(samps_zero_r0_carry__0_i_8_n_0));\n CARRY4 samps_zero_r0_carry__1\n (.CI(samps_zero_r0_carry__0_n_0),\n .CO({NLW_samps_zero_r0_carry__1_CO_UNCONNECTED[3:1],samps_zero_ns}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,samps_zero_r0_carry__1_i_1_n_0}),\n .O(NLW_samps_zero_r0_carry__1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,1'b0,samps_zero_r0_carry__1_i_2_n_0}));\n LUT2 #(\n .INIT(4'hE)) \n samps_zero_r0_carry__1_i_1\n (.I0(samps_lo[14]),\n .I1(samps_lo[13]),\n .O(samps_zero_r0_carry__1_i_1_n_0));\n LUT2 #(\n .INIT(4'h1)) \n samps_zero_r0_carry__1_i_2\n (.I0(samps_lo[13]),\n .I1(samps_lo[14]),\n .O(samps_zero_r0_carry__1_i_2_n_0));\n LUT2 #(\n .INIT(4'h8)) \n samps_zero_r0_carry_i_1\n (.I0(samps_lo[4]),\n .I1(samps_lo[3]),\n .O(samps_zero_r0_carry_i_1_n_0));\n LUT1 #(\n .INIT(2'h1)) \n samps_zero_r0_carry_i_10\n (.I0(\\samps_hi_r_reg_n_0_[5] ),\n .O(samps_zero_r_reg_3[2]));\n LUT1 #(\n .INIT(2'h1)) \n samps_zero_r0_carry_i_11\n (.I0(\\samps_hi_r_reg_n_0_[4] ),\n .O(samps_zero_r_reg_3[1]));\n LUT1 #(\n .INIT(2'h1)) \n samps_zero_r0_carry_i_12\n (.I0(\\samps_hi_r_reg_n_0_[3] ),\n .O(samps_zero_r_reg_3[0]));\n LUT3 #(\n .INIT(8'h28)) \n samps_zero_r0_carry_i_3\n (.I0(samps_lo[0]),\n .I1(Q[2]),\n .I2(Q[1]),\n .O(samps_zero_r0_carry_i_3_n_0));\n LUT2 #(\n .INIT(4'h2)) \n samps_zero_r0_carry_i_4\n (.I0(Q[1]),\n .I1(Q[0]),\n .O(samps_zero_r0_carry_i_4_n_0));\n LUT2 #(\n .INIT(4'h2)) \n samps_zero_r0_carry_i_5\n (.I0(samps_lo[4]),\n .I1(samps_lo[3]),\n .O(samps_zero_r0_carry_i_5_n_0));\n LUT2 #(\n .INIT(4'h2)) \n samps_zero_r0_carry_i_6\n (.I0(samps_lo[1]),\n .I1(samps_lo[2]),\n .O(samps_zero_r0_carry_i_6_n_0));\n LUT3 #(\n .INIT(8'h82)) \n samps_zero_r0_carry_i_7\n (.I0(samps_lo[0]),\n .I1(Q[2]),\n .I2(Q[1]),\n .O(samps_zero_r0_carry_i_7_n_0));\n LUT2 #(\n .INIT(4'h8)) \n samps_zero_r0_carry_i_8\n (.I0(Q[0]),\n .I1(Q[1]),\n .O(samps_zero_r0_carry_i_8_n_0));\n LUT1 #(\n .INIT(2'h1)) \n samps_zero_r0_carry_i_9\n (.I0(Q[1]),\n .O(samps_zero_r_reg_4));\n FDRE #(\n .INIT(1'b0)) \n samps_zero_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(samps_zero_ns),\n .Q(\\run_r_reg[0]_1 ),\n .R(1'b0));\n CARRY4 sm_ns0_carry\n (.CI(1'b0),\n .CO({sm_ns0_carry_n_0,sm_ns0_carry_n_1,sm_ns0_carry_n_2,sm_ns0_carry_n_3}),\n .CYINIT(1'b1),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(NLW_sm_ns0_carry_O_UNCONNECTED[3:0]),\n .S({sm_ns0_carry_i_1_n_0,sm_ns0_carry_i_2_n_0,sm_ns0_carry_i_3_n_0,sm_ns0_carry_i_4_n_0}));\n CARRY4 sm_ns0_carry__0\n (.CI(sm_ns0_carry_n_0),\n .CO({NLW_sm_ns0_carry__0_CO_UNCONNECTED[3:2],sm_ns0_carry__0_n_2,sm_ns0_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(NLW_sm_ns0_carry__0_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,sm_ns0_carry__0_i_1_n_0,sm_ns0_carry__0_i_2_n_0}));\n LUT2 #(\n .INIT(4'h1)) \n sm_ns0_carry__0_i_1\n (.I0(samp_cntr),\n .I1(\\samp_cntr_r_reg_n_0_[15] ),\n .O(sm_ns0_carry__0_i_1_n_0));\n LUT3 #(\n .INIT(8'h01)) \n sm_ns0_carry__0_i_2\n (.I0(\\samp_cntr_r_reg_n_0_[13] ),\n .I1(\\samp_cntr_r_reg_n_0_[14] ),\n .I2(\\samp_cntr_r_reg_n_0_[12] ),\n .O(sm_ns0_carry__0_i_2_n_0));\n LUT3 #(\n .INIT(8'h04)) \n sm_ns0_carry_i_1\n (.I0(\\samp_cntr_r_reg_n_0_[11] ),\n .I1(\\samp_cntr_r_reg_n_0_[9] ),\n .I2(\\samp_cntr_r_reg_n_0_[10] ),\n .O(sm_ns0_carry_i_1_n_0));\n LUT3 #(\n .INIT(8'h01)) \n sm_ns0_carry_i_2\n (.I0(\\samp_cntr_r_reg_n_0_[7] ),\n .I1(\\samp_cntr_r_reg_n_0_[8] ),\n .I2(\\samp_cntr_r_reg_n_0_[6] ),\n .O(sm_ns0_carry_i_2_n_0));\n LUT3 #(\n .INIT(8'h01)) \n sm_ns0_carry_i_3\n (.I0(\\samp_cntr_r_reg_n_0_[4] ),\n .I1(\\samp_cntr_r_reg_n_0_[5] ),\n .I2(\\samp_cntr_r_reg_n_0_[3] ),\n .O(sm_ns0_carry_i_3_n_0));\n LUT3 #(\n .INIT(8'h01)) \n sm_ns0_carry_i_4\n (.I0(\\samp_cntr_r_reg_n_0_[1] ),\n .I1(\\samp_cntr_r_reg_n_0_[2] ),\n .I2(\\samp_cntr_r_reg[0]_0 ),\n .O(sm_ns0_carry_i_4_n_0));\n LUT6 #(\n .INIT(64'h000000002F2A2A2A)) \n \\sm_r[0]_i_1 \n (.I0(\\sm_r_reg[0]_1 ),\n .I1(psdone),\n .I2(\\sm_r_reg[0]_0 ),\n .I3(\\sm_r[0]_i_2_n_0 ),\n .I4(sm_ns0_carry__0_n_2),\n .I5(rstdiv0_sync_r1_reg_rep__20),\n .O(\\sm_r[0]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h0008)) \n \\sm_r[0]_i_2 \n (.I0(poc_sample_pd),\n .I1(\\samp_wait_r_reg[6]_0 ),\n .I2(\\samp_wait_r_reg[7]_0 [5]),\n .I3(\\samp_wait_r_reg[7]_0 [6]),\n .O(\\sm_r[0]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair450\" *) \n LUT4 #(\n .INIT(16'h007A)) \n \\sm_r[1]_i_1 \n (.I0(\\sm_r_reg[0]_1 ),\n .I1(psdone),\n .I2(\\sm_r_reg[0]_0 ),\n .I3(rstdiv0_sync_r1_reg_rep__20),\n .O(\\sm_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\sm_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\sm_r[0]_i_1_n_0 ),\n .Q(\\sm_r_reg[0]_0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\sm_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\sm_r[1]_i_1_n_0 ),\n .Q(\\sm_r_reg[0]_1 ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair449\" *) \n LUT4 #(\n .INIT(16'h070F)) \n \\tap_r[0]_i_1 \n (.I0(\\rise_lead_r_reg[5] [4]),\n .I1(\\rise_lead_r_reg[5] [5]),\n .I2(\\rise_lead_r_reg[5] [0]),\n .I3(\\rise_lead_r_reg[5] [3]),\n .O(p_0_in[0]));\n (* SOFT_HLUTNM = \"soft_lutpair449\" *) \n LUT5 #(\n .INIT(32'h07700FF0)) \n \\tap_r[1]_i_1 \n (.I0(\\rise_lead_r_reg[5] [4]),\n .I1(\\rise_lead_r_reg[5] [5]),\n .I2(\\rise_lead_r_reg[5] [1]),\n .I3(\\rise_lead_r_reg[5] [0]),\n .I4(\\rise_lead_r_reg[5] [3]),\n .O(p_0_in[1]));\n LUT6 #(\n .INIT(64'h077070700FF0F0F0)) \n \\tap_r[2]_i_1 \n (.I0(\\rise_lead_r_reg[5] [4]),\n .I1(\\rise_lead_r_reg[5] [5]),\n .I2(\\rise_lead_r_reg[5] [2]),\n .I3(\\rise_lead_r_reg[5] [1]),\n .I4(\\rise_lead_r_reg[5] [0]),\n .I5(\\rise_lead_r_reg[5] [3]),\n .O(p_0_in[2]));\n LUT6 #(\n .INIT(64'h0770707070707070)) \n \\tap_r[3]_i_1 \n (.I0(\\rise_lead_r_reg[5] [4]),\n .I1(\\rise_lead_r_reg[5] [5]),\n .I2(\\rise_lead_r_reg[5] [3]),\n .I3(\\rise_lead_r_reg[5] [0]),\n .I4(\\rise_lead_r_reg[5] [1]),\n .I5(\\rise_lead_r_reg[5] [2]),\n .O(p_0_in[3]));\n LUT6 #(\n .INIT(64'h15557FFFC0000000)) \n \\tap_r[4]_i_1 \n (.I0(\\rise_lead_r_reg[5] [5]),\n .I1(\\rise_lead_r_reg[5] [2]),\n .I2(\\rise_lead_r_reg[5] [1]),\n .I3(\\rise_lead_r_reg[5] [0]),\n .I4(\\rise_lead_r_reg[5] [3]),\n .I5(\\rise_lead_r_reg[5] [4]),\n .O(p_0_in[4]));\n LUT2 #(\n .INIT(4'h2)) \n \\tap_r[5]_i_1 \n (.I0(\\sm_r_reg[0]_1 ),\n .I1(\\sm_r_reg[0]_0 ),\n .O(\\tap_r_reg[0]_0 ));\n LUT6 #(\n .INIT(64'h644444444CCCCCCC)) \n \\tap_r[5]_i_2 \n (.I0(\\rise_lead_r_reg[5] [4]),\n .I1(\\rise_lead_r_reg[5] [5]),\n .I2(\\rise_lead_r_reg[5] [2]),\n .I3(\\rise_lead_r_reg[5] [1]),\n .I4(\\rise_lead_r_reg[5] [0]),\n .I5(\\rise_lead_r_reg[5] [3]),\n .O(p_0_in[5]));\n FDRE #(\n .INIT(1'b0)) \n \\tap_r_reg[0] \n (.C(CLK),\n .CE(\\tap_r_reg[0]_0 ),\n .D(p_0_in[0]),\n .Q(\\rise_lead_r_reg[5] [0]),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE #(\n .INIT(1'b0)) \n \\tap_r_reg[1] \n (.C(CLK),\n .CE(\\tap_r_reg[0]_0 ),\n .D(p_0_in[1]),\n .Q(\\rise_lead_r_reg[5] [1]),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE #(\n .INIT(1'b0)) \n \\tap_r_reg[2] \n (.C(CLK),\n .CE(\\tap_r_reg[0]_0 ),\n .D(p_0_in[2]),\n .Q(\\rise_lead_r_reg[5] [2]),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE #(\n .INIT(1'b0)) \n \\tap_r_reg[3] \n (.C(CLK),\n .CE(\\tap_r_reg[0]_0 ),\n .D(p_0_in[3]),\n .Q(\\rise_lead_r_reg[5] [3]),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE #(\n .INIT(1'b0)) \n \\tap_r_reg[4] \n (.C(CLK),\n .CE(\\tap_r_reg[0]_0 ),\n .D(p_0_in[4]),\n .Q(\\rise_lead_r_reg[5] [4]),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE #(\n .INIT(1'b0)) \n \\tap_r_reg[5] \n (.C(CLK),\n .CE(\\tap_r_reg[0]_0 ),\n .D(p_0_in[5]),\n .Q(\\rise_lead_r_reg[5] [5]),\n .R(rstdiv0_sync_r1_reg_rep));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_poc_top\" *) \nmodule ddr3_ifmig_7series_v4_0_poc_top\n (detect_done_r_reg,\n \\sm_r_reg[1] ,\n poc_backup_r_reg,\n Q,\n \\mmcm_init_lead_reg[5] ,\n \\qcntr_r_reg[0] ,\n \\prev_r_reg[0] ,\n \\prev_r_reg[0]_0 ,\n CLK,\n rstdiv0_sync_r1_reg_rep__20,\n ocd_ktap_left_r_reg,\n ocd_ktap_right_r_reg,\n poc_sample_pd,\n use_noise_window,\n pd_out,\n \\run_ends_r_reg[1] ,\n ocd_ktap_left_r_reg_0,\n ocd_edge_detect_rdy_r_reg,\n psdone,\n rstdiv0_sync_r1_reg_rep,\n rstdiv0_sync_r1_reg_rep__0,\n ninety_offsets);\n output detect_done_r_reg;\n output \\sm_r_reg[1] ;\n output poc_backup_r_reg;\n output [5:0]Q;\n output [5:0]\\mmcm_init_lead_reg[5] ;\n output [0:0]\\qcntr_r_reg[0] ;\n output \\prev_r_reg[0] ;\n output \\prev_r_reg[0]_0 ;\n input CLK;\n input rstdiv0_sync_r1_reg_rep__20;\n input ocd_ktap_left_r_reg;\n input ocd_ktap_right_r_reg;\n input poc_sample_pd;\n input use_noise_window;\n input pd_out;\n input \\run_ends_r_reg[1] ;\n input ocd_ktap_left_r_reg_0;\n input ocd_edge_detect_rdy_r_reg;\n input psdone;\n input rstdiv0_sync_r1_reg_rep;\n input rstdiv0_sync_r1_reg_rep__0;\n input [1:0]ninety_offsets;\n\n wire CLK;\n wire [5:0]Q;\n wire center0_return1__0_carry__0_i_4_n_0;\n wire center0_return1__0_carry__0_i_5_n_0;\n wire center0_return1__0_carry__0_i_6_n_0;\n wire center0_return1__0_carry_i_4_n_0;\n wire center0_return1__0_carry_i_5_n_0;\n wire center0_return1__0_carry_i_6_n_0;\n wire center0_return1__1_carry__0_i_4_n_0;\n wire center0_return1__1_carry__0_i_5_n_0;\n wire center0_return1__1_carry_i_4_n_0;\n wire center0_return1__1_carry_i_5_n_0;\n wire center0_return1__1_carry_i_6_n_0;\n wire [7:4]center0_return3;\n wire \\center_diff_r_reg[0]_i_2_n_0 ;\n wire center_return1__0_carry__0_i_2_n_0;\n wire center_return1__0_carry__0_i_3_n_0;\n wire center_return1__0_carry__0_i_4_n_0;\n wire center_return1__0_carry_i_1_n_0;\n wire center_return1__0_carry_i_2_n_0;\n wire center_return1__0_carry_i_3_n_0;\n wire center_return1__1_carry__0_i_2_n_0;\n wire center_return1__1_carry__0_i_3_n_0;\n wire center_return1__1_carry_i_1_n_0;\n wire center_return1__1_carry_i_2_n_0;\n wire center_return1__1_carry_i_3_n_0;\n wire [7:4]center_return3;\n wire detect_done_r_reg;\n wire [5:1]diff;\n wire [0:0]diff_ns00_in;\n wire diff_ns0_carry__0_i_1_n_0;\n wire diff_ns0_carry__0_i_2_n_0;\n wire diff_ns1_carry_i_1_n_0;\n wire diff_ns1_carry_i_2_n_0;\n wire diff_ns1_carry_i_3_n_0;\n wire diff_ns1_carry_i_4_n_0;\n wire diff_ns1_carry_i_5_n_0;\n wire diff_ns1_carry_i_6_n_0;\n wire diff_ns1_carry_i_7_n_0;\n wire [6:0]edge_center;\n wire \\edge_diff_r_reg[0]_i_2_n_0 ;\n wire fall_lead_r0;\n wire i___10_n_0;\n wire i___11_n_0;\n wire i___12_n_0;\n wire i___13_n_0;\n wire i___14_n_0;\n wire i___15_n_0;\n wire i___16_n_0;\n wire i___17_n_0;\n wire i___18_n_0;\n wire i___18_rep_n_0;\n wire i___19_n_0;\n wire i___19_rep_n_0;\n wire i___20_n_0;\n wire i___20_rep__0_n_0;\n wire i___20_rep_n_0;\n wire i___21_n_0;\n wire i___21_rep_n_0;\n wire i___22_n_0;\n wire i___23_n_0;\n wire i___24_n_0;\n wire i___25_n_0;\n wire i___25_rep_n_0;\n wire i___26_n_0;\n wire i___26_rep__0_n_0;\n wire i___26_rep_n_0;\n wire i___27_n_0;\n wire i___28_n_0;\n wire i___29_n_0;\n wire i___30_n_0;\n wire i___31_n_0;\n wire i___32_n_0;\n wire i___33_n_0;\n wire i___34_n_0;\n wire i___34_rep_n_0;\n wire i___35_n_0;\n wire i___35_rep_n_0;\n wire i___36_n_0;\n wire i___36_rep__0_n_0;\n wire i___36_rep_n_0;\n wire i___37_n_0;\n wire i___38_n_0;\n wire i___38_rep_n_0;\n wire i___39_n_0;\n wire i___39_rep_n_0;\n wire i___40_n_0;\n wire i___41_n_0;\n wire i___42_n_0;\n wire i___43_n_0;\n wire i___44_n_0;\n wire i___45_n_0;\n wire i___46_n_0;\n wire i___47_n_0;\n wire i___47_rep_n_0;\n wire i___48_n_0;\n wire i___48_rep__0_n_0;\n wire i___48_rep_n_0;\n wire i___4_n_0;\n wire i___5_n_0;\n wire i___6_n_0;\n wire i___7_n_0;\n wire i___8_n_0;\n wire i___9_n_0;\n wire [5:0]\\mmcm_init_lead_reg[5] ;\n wire [5:0]mod_sub1_return;\n wire [1:0]ninety_offsets;\n wire ocd_edge_detect_rdy_r_reg;\n wire ocd_ktap_left_r_reg;\n wire ocd_ktap_left_r_reg_0;\n wire ocd_ktap_right_r_reg;\n wire [5:1]offset0_return0;\n wire [5:1]offset_return0;\n wire [6:1]p_0_in1_in;\n wire pd_out;\n wire poc_backup_r_reg;\n wire poc_sample_pd;\n wire \\prev_r_reg[0] ;\n wire \\prev_r_reg[0]_0 ;\n wire psdone;\n wire [0:0]\\qcntr_r_reg[0] ;\n wire [5:0]rise_lead_center_0;\n wire \\rise_lead_center_offset_r[5]_i_2_n_0 ;\n wire [5:0]rise_lead_left_0;\n wire [5:0]rise_trail_center_0;\n wire \\rise_trail_center_offset_r[5]_i_2_n_0 ;\n wire [5:0]rise_trail_left_0;\n wire \\rise_trail_r_reg[3]_i_2_n_0 ;\n wire \\rise_trail_r_reg[3]_i_2_n_1 ;\n wire \\rise_trail_r_reg[3]_i_2_n_2 ;\n wire \\rise_trail_r_reg[3]_i_2_n_3 ;\n wire \\rise_trail_r_reg[5]_i_3_n_3 ;\n wire rstdiv0_sync_r1_reg_rep;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire \\run_ends_r_reg[1] ;\n wire run_polarity_held_r;\n wire [16:1]samp_cntr_ns0;\n wire \\samp_cntr_r_reg[12]_i_2_n_0 ;\n wire \\samp_cntr_r_reg[12]_i_2_n_1 ;\n wire \\samp_cntr_r_reg[12]_i_2_n_2 ;\n wire \\samp_cntr_r_reg[12]_i_2_n_3 ;\n wire \\samp_cntr_r_reg[16]_i_2_n_1 ;\n wire \\samp_cntr_r_reg[16]_i_2_n_2 ;\n wire \\samp_cntr_r_reg[16]_i_2_n_3 ;\n wire \\samp_cntr_r_reg[4]_i_2_n_0 ;\n wire \\samp_cntr_r_reg[4]_i_2_n_1 ;\n wire \\samp_cntr_r_reg[4]_i_2_n_2 ;\n wire \\samp_cntr_r_reg[4]_i_2_n_3 ;\n wire \\samp_cntr_r_reg[8]_i_2_n_0 ;\n wire \\samp_cntr_r_reg[8]_i_2_n_1 ;\n wire \\samp_cntr_r_reg[8]_i_2_n_2 ;\n wire \\samp_cntr_r_reg[8]_i_2_n_3 ;\n wire [7:0]samp_wait_r;\n wire [17:0]samps_hi_ns0;\n wire \\samps_hi_r[3]_i_6_n_0 ;\n wire \\samps_hi_r_reg[11]_i_2_n_0 ;\n wire \\samps_hi_r_reg[11]_i_2_n_1 ;\n wire \\samps_hi_r_reg[11]_i_2_n_2 ;\n wire \\samps_hi_r_reg[11]_i_2_n_3 ;\n wire \\samps_hi_r_reg[15]_i_2_n_0 ;\n wire \\samps_hi_r_reg[15]_i_2_n_1 ;\n wire \\samps_hi_r_reg[15]_i_2_n_2 ;\n wire \\samps_hi_r_reg[15]_i_2_n_3 ;\n wire \\samps_hi_r_reg[17]_i_2_n_3 ;\n wire \\samps_hi_r_reg[3]_i_2_n_0 ;\n wire \\samps_hi_r_reg[3]_i_2_n_1 ;\n wire \\samps_hi_r_reg[3]_i_2_n_2 ;\n wire \\samps_hi_r_reg[3]_i_2_n_3 ;\n wire \\samps_hi_r_reg[7]_i_2_n_0 ;\n wire \\samps_hi_r_reg[7]_i_2_n_1 ;\n wire \\samps_hi_r_reg[7]_i_2_n_2 ;\n wire \\samps_hi_r_reg[7]_i_2_n_3 ;\n wire [17:3]samps_lo;\n wire samps_zero_r0_carry__0_i_10_n_0;\n wire samps_zero_r0_carry__0_i_10_n_1;\n wire samps_zero_r0_carry__0_i_10_n_2;\n wire samps_zero_r0_carry__0_i_10_n_3;\n wire samps_zero_r0_carry__0_i_4_n_0;\n wire samps_zero_r0_carry__0_i_4_n_1;\n wire samps_zero_r0_carry__0_i_4_n_2;\n wire samps_zero_r0_carry__0_i_4_n_3;\n wire samps_zero_r0_carry__0_i_9_n_1;\n wire samps_zero_r0_carry__0_i_9_n_2;\n wire samps_zero_r0_carry__0_i_9_n_3;\n wire samps_zero_r0_carry_i_2_n_0;\n wire samps_zero_r0_carry_i_2_n_1;\n wire samps_zero_r0_carry_i_2_n_2;\n wire samps_zero_r0_carry_i_2_n_3;\n wire \\sm_r_reg[1] ;\n wire [5:0]trailing_edge;\n wire [5:0]trailing_edge0;\n wire [5:0]trailing_edge00_in;\n wire u_edge_left_n_0;\n wire u_edge_left_n_1;\n wire u_edge_left_n_15;\n wire u_edge_left_n_19;\n wire u_edge_left_n_2;\n wire u_edge_left_n_20;\n wire u_edge_left_n_21;\n wire u_edge_left_n_22;\n wire u_edge_left_n_23;\n wire u_edge_left_n_24;\n wire u_edge_left_n_25;\n wire u_edge_left_n_26;\n wire u_edge_left_n_27;\n wire u_edge_left_n_28;\n wire u_edge_left_n_29;\n wire u_edge_left_n_30;\n wire u_edge_left_n_31;\n wire u_edge_left_n_32;\n wire u_edge_left_n_33;\n wire u_edge_left_n_34;\n wire u_edge_right_n_21;\n wire u_edge_right_n_22;\n wire u_edge_right_n_23;\n wire u_edge_right_n_24;\n wire u_edge_right_n_25;\n wire u_edge_right_n_26;\n wire u_edge_right_n_27;\n wire u_edge_right_n_28;\n wire u_edge_right_n_29;\n wire u_edge_right_n_30;\n wire u_edge_right_n_31;\n wire u_edge_right_n_8;\n wire u_poc_meta_n_14;\n wire u_poc_meta_n_15;\n wire u_poc_meta_n_16;\n wire u_poc_meta_n_17;\n wire u_poc_meta_n_18;\n wire u_poc_meta_n_19;\n wire u_poc_meta_n_24;\n wire u_poc_meta_n_25;\n wire u_poc_meta_n_26;\n wire u_poc_meta_n_27;\n wire u_poc_meta_n_28;\n wire u_poc_meta_n_29;\n wire u_poc_meta_n_30;\n wire u_poc_meta_n_31;\n wire u_poc_meta_n_32;\n wire u_poc_meta_n_33;\n wire u_poc_meta_n_34;\n wire u_poc_meta_n_56;\n wire u_poc_meta_n_57;\n wire u_poc_meta_n_58;\n wire u_poc_meta_n_59;\n wire u_poc_meta_n_60;\n wire u_poc_meta_n_61;\n wire u_poc_meta_n_62;\n wire u_poc_meta_n_63;\n wire u_poc_tap_base_n_0;\n wire u_poc_tap_base_n_1;\n wire u_poc_tap_base_n_10;\n wire u_poc_tap_base_n_11;\n wire u_poc_tap_base_n_12;\n wire u_poc_tap_base_n_13;\n wire u_poc_tap_base_n_14;\n wire u_poc_tap_base_n_15;\n wire u_poc_tap_base_n_16;\n wire u_poc_tap_base_n_17;\n wire u_poc_tap_base_n_18;\n wire u_poc_tap_base_n_19;\n wire u_poc_tap_base_n_2;\n wire u_poc_tap_base_n_20;\n wire u_poc_tap_base_n_21;\n wire u_poc_tap_base_n_22;\n wire u_poc_tap_base_n_23;\n wire u_poc_tap_base_n_24;\n wire u_poc_tap_base_n_25;\n wire u_poc_tap_base_n_26;\n wire u_poc_tap_base_n_27;\n wire u_poc_tap_base_n_28;\n wire u_poc_tap_base_n_29;\n wire u_poc_tap_base_n_3;\n wire u_poc_tap_base_n_30;\n wire u_poc_tap_base_n_31;\n wire u_poc_tap_base_n_32;\n wire u_poc_tap_base_n_33;\n wire u_poc_tap_base_n_34;\n wire u_poc_tap_base_n_35;\n wire u_poc_tap_base_n_36;\n wire u_poc_tap_base_n_37;\n wire u_poc_tap_base_n_38;\n wire u_poc_tap_base_n_39;\n wire u_poc_tap_base_n_4;\n wire u_poc_tap_base_n_40;\n wire u_poc_tap_base_n_41;\n wire u_poc_tap_base_n_42;\n wire u_poc_tap_base_n_43;\n wire u_poc_tap_base_n_44;\n wire u_poc_tap_base_n_45;\n wire u_poc_tap_base_n_46;\n wire u_poc_tap_base_n_47;\n wire u_poc_tap_base_n_48;\n wire u_poc_tap_base_n_49;\n wire u_poc_tap_base_n_5;\n wire u_poc_tap_base_n_50;\n wire u_poc_tap_base_n_51;\n wire u_poc_tap_base_n_52;\n wire u_poc_tap_base_n_53;\n wire u_poc_tap_base_n_54;\n wire u_poc_tap_base_n_55;\n wire u_poc_tap_base_n_57;\n wire u_poc_tap_base_n_58;\n wire u_poc_tap_base_n_59;\n wire u_poc_tap_base_n_6;\n wire u_poc_tap_base_n_60;\n wire u_poc_tap_base_n_61;\n wire u_poc_tap_base_n_62;\n wire u_poc_tap_base_n_63;\n wire u_poc_tap_base_n_64;\n wire u_poc_tap_base_n_65;\n wire u_poc_tap_base_n_66;\n wire u_poc_tap_base_n_67;\n wire u_poc_tap_base_n_68;\n wire u_poc_tap_base_n_69;\n wire u_poc_tap_base_n_7;\n wire u_poc_tap_base_n_70;\n wire u_poc_tap_base_n_71;\n wire u_poc_tap_base_n_72;\n wire u_poc_tap_base_n_73;\n wire u_poc_tap_base_n_74;\n wire u_poc_tap_base_n_75;\n wire u_poc_tap_base_n_76;\n wire u_poc_tap_base_n_8;\n wire u_poc_tap_base_n_83;\n wire u_poc_tap_base_n_84;\n wire u_poc_tap_base_n_85;\n wire u_poc_tap_base_n_86;\n wire u_poc_tap_base_n_9;\n wire u_poc_tap_base_n_95;\n wire use_noise_window;\n wire [6:0]window_center;\n wire [3:1]\\NLW_rise_trail_r_reg[5]_i_3_CO_UNCONNECTED ;\n wire [3:2]\\NLW_rise_trail_r_reg[5]_i_3_O_UNCONNECTED ;\n wire [3:3]\\NLW_samp_cntr_r_reg[16]_i_2_CO_UNCONNECTED ;\n wire [3:1]\\NLW_samps_hi_r_reg[17]_i_2_CO_UNCONNECTED ;\n wire [3:2]\\NLW_samps_hi_r_reg[17]_i_2_O_UNCONNECTED ;\n wire [3:3]NLW_samps_zero_r0_carry__0_i_9_CO_UNCONNECTED;\n wire [0:0]NLW_samps_zero_r0_carry_i_2_O_UNCONNECTED;\n\n LUT6 #(\n .INIT(64'h1555FFFFEAAA0000)) \n center0_return1__0_carry__0_i_4\n (.I0(center0_return3[7]),\n .I1(center0_return3[4]),\n .I2(center0_return3[5]),\n .I3(center0_return3[6]),\n .I4(u_poc_meta_n_60),\n .I5(center0_return1__0_carry__0_i_6_n_0),\n .O(center0_return1__0_carry__0_i_4_n_0));\n LUT6 #(\n .INIT(64'hA999999956666666)) \n center0_return1__0_carry__0_i_5\n (.I0(u_poc_meta_n_60),\n .I1(center0_return3[7]),\n .I2(center0_return3[4]),\n .I3(center0_return3[5]),\n .I4(center0_return3[6]),\n .I5(u_edge_left_n_1),\n .O(center0_return1__0_carry__0_i_5_n_0));\n LUT4 #(\n .INIT(16'h1DE2)) \n center0_return1__0_carry__0_i_6\n (.I0(rise_trail_left_0[4]),\n .I1(use_noise_window),\n .I2(rise_lead_left_0[4]),\n .I3(u_poc_meta_n_59),\n .O(center0_return1__0_carry__0_i_6_n_0));\n LUT4 #(\n .INIT(16'h1DE2)) \n center0_return1__0_carry_i_4\n (.I0(rise_trail_left_0[2]),\n .I1(use_noise_window),\n .I2(rise_lead_left_0[2]),\n .I3(u_poc_meta_n_61),\n .O(center0_return1__0_carry_i_4_n_0));\n LUT4 #(\n .INIT(16'h1DE2)) \n center0_return1__0_carry_i_5\n (.I0(rise_trail_left_0[1]),\n .I1(use_noise_window),\n .I2(rise_lead_left_0[1]),\n .I3(u_poc_meta_n_62),\n .O(center0_return1__0_carry_i_5_n_0));\n LUT4 #(\n .INIT(16'h1DE2)) \n center0_return1__0_carry_i_6\n (.I0(rise_trail_left_0[0]),\n .I1(use_noise_window),\n .I2(rise_lead_left_0[0]),\n .I3(u_poc_meta_n_63),\n .O(center0_return1__0_carry_i_6_n_0));\n LUT4 #(\n .INIT(16'h1DE2)) \n center0_return1__1_carry__0_i_4\n (.I0(rise_trail_left_0[4]),\n .I1(use_noise_window),\n .I2(rise_lead_left_0[4]),\n .I3(u_poc_meta_n_59),\n .O(center0_return1__1_carry__0_i_4_n_0));\n LUT4 #(\n .INIT(16'h1DE2)) \n center0_return1__1_carry__0_i_5\n (.I0(rise_trail_left_0[3]),\n .I1(use_noise_window),\n .I2(rise_lead_left_0[3]),\n .I3(u_poc_meta_n_60),\n .O(center0_return1__1_carry__0_i_5_n_0));\n LUT4 #(\n .INIT(16'h1DE2)) \n center0_return1__1_carry_i_4\n (.I0(rise_trail_left_0[2]),\n .I1(use_noise_window),\n .I2(rise_lead_left_0[2]),\n .I3(u_poc_meta_n_61),\n .O(center0_return1__1_carry_i_4_n_0));\n LUT4 #(\n .INIT(16'h1DE2)) \n center0_return1__1_carry_i_5\n (.I0(rise_trail_left_0[1]),\n .I1(use_noise_window),\n .I2(rise_lead_left_0[1]),\n .I3(u_poc_meta_n_62),\n .O(center0_return1__1_carry_i_5_n_0));\n LUT4 #(\n .INIT(16'h1DE2)) \n center0_return1__1_carry_i_6\n (.I0(rise_trail_left_0[0]),\n .I1(use_noise_window),\n .I2(rise_lead_left_0[0]),\n .I3(u_poc_meta_n_63),\n .O(center0_return1__1_carry_i_6_n_0));\n LUT1 #(\n .INIT(2'h1)) \n \\center_diff_r_reg[0]_i_2 \n (.I0(i___20_n_0),\n .O(\\center_diff_r_reg[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h007FFFFFFF800000)) \n center_return1__0_carry__0_i_2\n (.I0(center_return3[5]),\n .I1(center_return3[4]),\n .I2(center_return3[6]),\n .I3(center_return3[7]),\n .I4(diff[4]),\n .I5(center_return1__0_carry__0_i_4_n_0),\n .O(center_return1__0_carry__0_i_2_n_0));\n LUT6 #(\n .INIT(64'hAAAA955555556AAA)) \n center_return1__0_carry__0_i_3\n (.I0(diff[4]),\n .I1(center_return3[5]),\n .I2(center_return3[4]),\n .I3(center_return3[6]),\n .I4(center_return3[7]),\n .I5(p_0_in1_in[4]),\n .O(center_return1__0_carry__0_i_3_n_0));\n LUT2 #(\n .INIT(4'h6)) \n center_return1__0_carry__0_i_4\n (.I0(p_0_in1_in[5]),\n .I1(diff[5]),\n .O(center_return1__0_carry__0_i_4_n_0));\n LUT2 #(\n .INIT(4'h6)) \n center_return1__0_carry_i_1\n (.I0(p_0_in1_in[3]),\n .I1(diff[3]),\n .O(center_return1__0_carry_i_1_n_0));\n LUT2 #(\n .INIT(4'h6)) \n center_return1__0_carry_i_2\n (.I0(p_0_in1_in[2]),\n .I1(diff[2]),\n .O(center_return1__0_carry_i_2_n_0));\n LUT2 #(\n .INIT(4'h6)) \n center_return1__0_carry_i_3\n (.I0(p_0_in1_in[1]),\n .I1(diff[1]),\n .O(center_return1__0_carry_i_3_n_0));\n LUT2 #(\n .INIT(4'h6)) \n center_return1__1_carry__0_i_2\n (.I0(p_0_in1_in[5]),\n .I1(diff[5]),\n .O(center_return1__1_carry__0_i_2_n_0));\n LUT2 #(\n .INIT(4'h6)) \n center_return1__1_carry__0_i_3\n (.I0(p_0_in1_in[4]),\n .I1(diff[4]),\n .O(center_return1__1_carry__0_i_3_n_0));\n LUT2 #(\n .INIT(4'h6)) \n center_return1__1_carry_i_1\n (.I0(p_0_in1_in[3]),\n .I1(diff[3]),\n .O(center_return1__1_carry_i_1_n_0));\n LUT2 #(\n .INIT(4'h6)) \n center_return1__1_carry_i_2\n (.I0(p_0_in1_in[2]),\n .I1(diff[2]),\n .O(center_return1__1_carry_i_2_n_0));\n LUT2 #(\n .INIT(4'h6)) \n center_return1__1_carry_i_3\n (.I0(p_0_in1_in[1]),\n .I1(diff[1]),\n .O(center_return1__1_carry_i_3_n_0));\n LUT2 #(\n .INIT(4'h6)) \n diff_ns0_carry__0_i_1\n (.I0(window_center[5]),\n .I1(edge_center[5]),\n .O(diff_ns0_carry__0_i_1_n_0));\n LUT2 #(\n .INIT(4'h6)) \n diff_ns0_carry__0_i_2\n (.I0(edge_center[4]),\n .I1(window_center[4]),\n .O(diff_ns0_carry__0_i_2_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n diff_ns1_carry_i_1\n (.I0(edge_center[4]),\n .I1(window_center[4]),\n .I2(window_center[5]),\n .I3(edge_center[5]),\n .O(diff_ns1_carry_i_1_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n diff_ns1_carry_i_2\n (.I0(edge_center[2]),\n .I1(window_center[2]),\n .I2(window_center[3]),\n .I3(edge_center[3]),\n .O(diff_ns1_carry_i_2_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n diff_ns1_carry_i_3\n (.I0(edge_center[0]),\n .I1(window_center[0]),\n .I2(window_center[1]),\n .I3(edge_center[1]),\n .O(diff_ns1_carry_i_3_n_0));\n LUT2 #(\n .INIT(4'h9)) \n diff_ns1_carry_i_4\n (.I0(window_center[6]),\n .I1(edge_center[6]),\n .O(diff_ns1_carry_i_4_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n diff_ns1_carry_i_5\n (.I0(edge_center[4]),\n .I1(window_center[4]),\n .I2(edge_center[5]),\n .I3(window_center[5]),\n .O(diff_ns1_carry_i_5_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n diff_ns1_carry_i_6\n (.I0(edge_center[2]),\n .I1(window_center[2]),\n .I2(edge_center[3]),\n .I3(window_center[3]),\n .O(diff_ns1_carry_i_6_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n diff_ns1_carry_i_7\n (.I0(edge_center[0]),\n .I1(window_center[0]),\n .I2(edge_center[1]),\n .I3(window_center[1]),\n .O(diff_ns1_carry_i_7_n_0));\n LUT1 #(\n .INIT(2'h1)) \n \\diff_r_reg[0]_i_2 \n (.I0(i___48_n_0),\n .O(diff_ns00_in));\n LUT1 #(\n .INIT(2'h1)) \n \\edge_diff_r_reg[0]_i_2 \n (.I0(i___36_n_0),\n .O(\\edge_diff_r_reg[0]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFF8888F)) \n i___10\n (.I0(u_poc_tap_base_n_55),\n .I1(u_poc_tap_base_n_54),\n .I2(samp_wait_r[0]),\n .I3(samp_wait_r[1]),\n .I4(samp_wait_r[2]),\n .O(i___10_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFF88888888F)) \n i___11\n (.I0(u_poc_tap_base_n_55),\n .I1(u_poc_tap_base_n_54),\n .I2(samp_wait_r[2]),\n .I3(samp_wait_r[1]),\n .I4(samp_wait_r[0]),\n .I5(samp_wait_r[3]),\n .O(i___11_n_0));\n LUT6 #(\n .INIT(64'h5555555500000040)) \n i___12\n (.I0(u_poc_tap_base_n_54),\n .I1(poc_sample_pd),\n .I2(u_poc_tap_base_n_86),\n .I3(samp_wait_r[6]),\n .I4(samp_wait_r[7]),\n .I5(u_poc_tap_base_n_55),\n .O(i___12_n_0));\n LUT5 #(\n .INIT(32'h00000001)) \n i___13\n (.I0(samp_wait_r[4]),\n .I1(samp_wait_r[2]),\n .I2(samp_wait_r[1]),\n .I3(samp_wait_r[0]),\n .I4(samp_wait_r[3]),\n .O(i___13_n_0));\n LUT5 #(\n .INIT(32'hA8888888)) \n i___14\n (.I0(diff[4]),\n .I1(center_return3[7]),\n .I2(center_return3[6]),\n .I3(center_return3[4]),\n .I4(center_return3[5]),\n .O(i___14_n_0));\n LUT6 #(\n .INIT(64'h478B74B8B8748B47)) \n i___15\n (.I0(rise_lead_left_0[4]),\n .I1(use_noise_window),\n .I2(rise_trail_left_0[4]),\n .I3(Q[4]),\n .I4(\\mmcm_init_lead_reg[5] [4]),\n .I5(u_edge_left_n_1),\n .O(i___15_n_0));\n LUT5 #(\n .INIT(32'hCCA533A5)) \n i___16\n (.I0(\\mmcm_init_lead_reg[5] [4]),\n .I1(Q[4]),\n .I2(rise_trail_left_0[4]),\n .I3(use_noise_window),\n .I4(rise_lead_left_0[4]),\n .O(i___16_n_0));\n LUT5 #(\n .INIT(32'hCCA533A5)) \n i___17\n (.I0(\\mmcm_init_lead_reg[5] [3]),\n .I1(Q[3]),\n .I2(rise_trail_left_0[3]),\n .I3(use_noise_window),\n .I4(rise_lead_left_0[3]),\n .O(i___17_n_0));\n LUT5 #(\n .INIT(32'hCCA533A5)) \n i___18\n (.I0(\\mmcm_init_lead_reg[5] [2]),\n .I1(Q[2]),\n .I2(rise_trail_left_0[2]),\n .I3(use_noise_window),\n .I4(rise_lead_left_0[2]),\n .O(i___18_n_0));\n LUT5 #(\n .INIT(32'hCCA533A5)) \n i___18_rep\n (.I0(\\mmcm_init_lead_reg[5] [2]),\n .I1(Q[2]),\n .I2(rise_trail_left_0[2]),\n .I3(use_noise_window),\n .I4(rise_lead_left_0[2]),\n .O(i___18_rep_n_0));\n LUT5 #(\n .INIT(32'hCCA533A5)) \n i___19\n (.I0(\\mmcm_init_lead_reg[5] [1]),\n .I1(Q[1]),\n .I2(rise_trail_left_0[1]),\n .I3(use_noise_window),\n .I4(rise_lead_left_0[1]),\n .O(i___19_n_0));\n LUT5 #(\n .INIT(32'hCCA533A5)) \n i___19_rep\n (.I0(\\mmcm_init_lead_reg[5] [1]),\n .I1(Q[1]),\n .I2(rise_trail_left_0[1]),\n .I3(use_noise_window),\n .I4(rise_lead_left_0[1]),\n .O(i___19_rep_n_0));\n LUT5 #(\n .INIT(32'hCCA533A5)) \n i___20\n (.I0(\\mmcm_init_lead_reg[5] [0]),\n .I1(Q[0]),\n .I2(rise_trail_left_0[0]),\n .I3(use_noise_window),\n .I4(rise_lead_left_0[0]),\n .O(i___20_n_0));\n LUT5 #(\n .INIT(32'hCCA533A5)) \n i___20_rep\n (.I0(\\mmcm_init_lead_reg[5] [0]),\n .I1(Q[0]),\n .I2(rise_trail_left_0[0]),\n .I3(use_noise_window),\n .I4(rise_lead_left_0[0]),\n .O(i___20_rep_n_0));\n LUT5 #(\n .INIT(32'hCCA533A5)) \n i___20_rep__0\n (.I0(\\mmcm_init_lead_reg[5] [0]),\n .I1(Q[0]),\n .I2(rise_trail_left_0[0]),\n .I3(use_noise_window),\n .I4(rise_lead_left_0[0]),\n .O(i___20_rep__0_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___21\n (.I0(u_poc_tap_base_n_60),\n .I1(u_poc_tap_base_n_49),\n .O(i___21_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___21_rep\n (.I0(u_poc_tap_base_n_60),\n .I1(u_poc_tap_base_n_49),\n .O(i___21_rep_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___22\n (.I0(u_poc_tap_base_n_59),\n .I1(u_poc_tap_base_n_48),\n .O(i___22_n_0));\n LUT3 #(\n .INIT(8'h69)) \n i___23\n (.I0(u_poc_tap_base_n_47),\n .I1(u_poc_tap_base_n_58),\n .I2(u_poc_tap_base_n_48),\n .O(i___23_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___24\n (.I0(u_poc_tap_base_n_58),\n .I1(u_poc_tap_base_n_47),\n .O(i___24_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___25\n (.I0(u_poc_tap_base_n_61),\n .I1(u_poc_tap_base_n_50),\n .O(i___25_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___25_rep\n (.I0(u_poc_tap_base_n_61),\n .I1(u_poc_tap_base_n_50),\n .O(i___25_rep_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair475\" *) \n LUT2 #(\n .INIT(4'h9)) \n i___26\n (.I0(u_poc_tap_base_n_62),\n .I1(u_poc_tap_base_n_51),\n .O(i___26_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___26_rep\n (.I0(u_poc_tap_base_n_62),\n .I1(u_poc_tap_base_n_51),\n .O(i___26_rep_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___26_rep__0\n (.I0(u_poc_tap_base_n_62),\n .I1(u_poc_tap_base_n_51),\n .O(i___26_rep__0_n_0));\n LUT2 #(\n .INIT(4'h6)) \n i___27\n (.I0(u_poc_tap_base_n_7),\n .I1(u_poc_tap_base_n_6),\n .O(i___27_n_0));\n LUT2 #(\n .INIT(4'h6)) \n i___28\n (.I0(u_poc_tap_base_n_5),\n .I1(u_poc_tap_base_n_4),\n .O(i___28_n_0));\n LUT4 #(\n .INIT(16'hD22D)) \n i___29\n (.I0(p_0_in1_in[5]),\n .I1(u_poc_meta_n_15),\n .I2(p_0_in1_in[6]),\n .I3(u_poc_meta_n_14),\n .O(i___29_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___30\n (.I0(u_poc_meta_n_14),\n .I1(p_0_in1_in[6]),\n .O(i___30_n_0));\n LUT3 #(\n .INIT(8'h69)) \n i___31\n (.I0(p_0_in1_in[5]),\n .I1(u_poc_meta_n_15),\n .I2(p_0_in1_in[4]),\n .O(i___31_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___32\n (.I0(u_poc_meta_n_15),\n .I1(p_0_in1_in[5]),\n .O(i___32_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___33\n (.I0(u_poc_meta_n_16),\n .I1(p_0_in1_in[4]),\n .O(i___33_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___34\n (.I0(u_poc_meta_n_17),\n .I1(p_0_in1_in[3]),\n .O(i___34_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___34_rep\n (.I0(u_poc_meta_n_17),\n .I1(p_0_in1_in[3]),\n .O(i___34_rep_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___35\n (.I0(u_poc_meta_n_18),\n .I1(p_0_in1_in[2]),\n .O(i___35_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___35_rep\n (.I0(u_poc_meta_n_18),\n .I1(p_0_in1_in[2]),\n .O(i___35_rep_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___36\n (.I0(u_poc_meta_n_19),\n .I1(p_0_in1_in[1]),\n .O(i___36_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___36_rep\n (.I0(u_poc_meta_n_19),\n .I1(p_0_in1_in[1]),\n .O(i___36_rep_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___36_rep__0\n (.I0(u_poc_meta_n_19),\n .I1(p_0_in1_in[1]),\n .O(i___36_rep__0_n_0));\n LUT4 #(\n .INIT(16'hD22D)) \n i___37\n (.I0(window_center[5]),\n .I1(edge_center[5]),\n .I2(window_center[6]),\n .I3(edge_center[6]),\n .O(i___37_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___38\n (.I0(edge_center[2]),\n .I1(window_center[2]),\n .O(i___38_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___38_rep\n (.I0(edge_center[2]),\n .I1(window_center[2]),\n .O(i___38_rep_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___39\n (.I0(edge_center[1]),\n .I1(window_center[1]),\n .O(i___39_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___39_rep\n (.I0(edge_center[1]),\n .I1(window_center[1]),\n .O(i___39_rep_n_0));\n LUT6 #(\n .INIT(64'hFFFFCFFF00008800)) \n i___4\n (.I0(u_poc_tap_base_n_2),\n .I1(u_poc_tap_base_n_0),\n .I2(u_poc_tap_base_n_3),\n .I3(u_poc_tap_base_n_46),\n .I4(rstdiv0_sync_r1_reg_rep__20),\n .I5(run_polarity_held_r),\n .O(i___4_n_0));\n LUT2 #(\n .INIT(4'h2)) \n i___40\n (.I0(window_center[6]),\n .I1(edge_center[6]),\n .O(i___40_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___41\n (.I0(edge_center[6]),\n .I1(window_center[6]),\n .O(i___41_n_0));\n LUT2 #(\n .INIT(4'h2)) \n i___42\n (.I0(edge_center[6]),\n .I1(window_center[6]),\n .O(i___42_n_0));\n LUT3 #(\n .INIT(8'h69)) \n i___43\n (.I0(window_center[5]),\n .I1(edge_center[5]),\n .I2(window_center[4]),\n .O(i___43_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___44\n (.I0(edge_center[5]),\n .I1(window_center[5]),\n .O(i___44_n_0));\n LUT2 #(\n .INIT(4'hB)) \n i___45\n (.I0(edge_center[5]),\n .I1(window_center[5]),\n .O(i___45_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___46\n (.I0(edge_center[4]),\n .I1(window_center[4]),\n .O(i___46_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___47\n (.I0(edge_center[3]),\n .I1(window_center[3]),\n .O(i___47_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___47_rep\n (.I0(edge_center[3]),\n .I1(window_center[3]),\n .O(i___47_rep_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___48\n (.I0(edge_center[0]),\n .I1(window_center[0]),\n .O(i___48_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___48_rep\n (.I0(edge_center[0]),\n .I1(window_center[0]),\n .O(i___48_rep_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___48_rep__0\n (.I0(edge_center[0]),\n .I1(window_center[0]),\n .O(i___48_rep__0_n_0));\n LUT5 #(\n .INIT(32'h00400000)) \n i___5\n (.I0(u_poc_tap_base_n_0),\n .I1(u_poc_tap_base_n_3),\n .I2(u_poc_tap_base_n_46),\n .I3(rstdiv0_sync_r1_reg_rep__20),\n .I4(ocd_ktap_right_r_reg),\n .O(i___5_n_0));\n LUT5 #(\n .INIT(32'h00400000)) \n i___6\n (.I0(u_poc_tap_base_n_0),\n .I1(u_poc_tap_base_n_3),\n .I2(u_poc_tap_base_n_46),\n .I3(rstdiv0_sync_r1_reg_rep__20),\n .I4(ocd_ktap_left_r_reg),\n .O(i___6_n_0));\n LUT4 #(\n .INIT(16'h0004)) \n i___7\n (.I0(u_poc_tap_base_n_0),\n .I1(u_poc_tap_base_n_52),\n .I2(ocd_ktap_left_r_reg),\n .I3(ocd_ktap_right_r_reg),\n .O(i___7_n_0));\n LUT3 #(\n .INIT(8'h01)) \n i___8\n (.I0(u_poc_meta_n_56),\n .I1(u_poc_meta_n_58),\n .I2(u_poc_meta_n_57),\n .O(i___8_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair475\" *) \n LUT4 #(\n .INIT(16'h7FFF)) \n i___9\n (.I0(u_poc_tap_base_n_49),\n .I1(u_poc_tap_base_n_50),\n .I2(u_poc_tap_base_n_51),\n .I3(u_poc_tap_base_n_48),\n .O(i___9_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair478\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\rise_lead_center_offset_r[1]_i_1 \n (.I0(rise_lead_center_0[1]),\n .I1(ninety_offsets[0]),\n .O(offset_return0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair476\" *) \n LUT4 #(\n .INIT(16'h4BB4)) \n \\rise_lead_center_offset_r[2]_i_1 \n (.I0(rise_lead_center_0[1]),\n .I1(ninety_offsets[0]),\n .I2(ninety_offsets[1]),\n .I3(rise_lead_center_0[2]),\n .O(offset_return0[2]));\n LUT6 #(\n .INIT(64'h5A4969254969925A)) \n \\rise_lead_center_offset_r[3]_i_1 \n (.I0(rise_lead_center_0[3]),\n .I1(rise_lead_center_0[5]),\n .I2(\\rise_lead_center_offset_r[5]_i_2_n_0 ),\n .I3(rise_lead_center_0[4]),\n .I4(ninety_offsets[1]),\n .I5(ninety_offsets[0]),\n .O(offset_return0[3]));\n LUT6 #(\n .INIT(64'h998564666466621A)) \n \\rise_lead_center_offset_r[4]_i_1 \n (.I0(rise_lead_center_0[4]),\n .I1(ninety_offsets[0]),\n .I2(ninety_offsets[1]),\n .I3(rise_lead_center_0[5]),\n .I4(rise_lead_center_0[3]),\n .I5(\\rise_lead_center_offset_r[5]_i_2_n_0 ),\n .O(offset_return0[4]));\n LUT6 #(\n .INIT(64'hF00E871887700EF0)) \n \\rise_lead_center_offset_r[5]_i_1 \n (.I0(rise_lead_center_0[3]),\n .I1(\\rise_lead_center_offset_r[5]_i_2_n_0 ),\n .I2(rise_lead_center_0[5]),\n .I3(ninety_offsets[1]),\n .I4(ninety_offsets[0]),\n .I5(rise_lead_center_0[4]),\n .O(offset_return0[5]));\n (* SOFT_HLUTNM = \"soft_lutpair476\" *) \n LUT4 #(\n .INIT(16'hE460)) \n \\rise_lead_center_offset_r[5]_i_2 \n (.I0(ninety_offsets[1]),\n .I1(ninety_offsets[0]),\n .I2(rise_lead_center_0[2]),\n .I3(rise_lead_center_0[1]),\n .O(\\rise_lead_center_offset_r[5]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair478\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\rise_trail_center_offset_r[1]_i_1 \n (.I0(rise_trail_center_0[1]),\n .I1(ninety_offsets[0]),\n .O(offset0_return0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair477\" *) \n LUT4 #(\n .INIT(16'h4BB4)) \n \\rise_trail_center_offset_r[2]_i_1 \n (.I0(rise_trail_center_0[1]),\n .I1(ninety_offsets[0]),\n .I2(ninety_offsets[1]),\n .I3(rise_trail_center_0[2]),\n .O(offset0_return0[2]));\n LUT6 #(\n .INIT(64'h5A4969254969925A)) \n \\rise_trail_center_offset_r[3]_i_1 \n (.I0(rise_trail_center_0[3]),\n .I1(rise_trail_center_0[5]),\n .I2(\\rise_trail_center_offset_r[5]_i_2_n_0 ),\n .I3(rise_trail_center_0[4]),\n .I4(ninety_offsets[1]),\n .I5(ninety_offsets[0]),\n .O(offset0_return0[3]));\n LUT6 #(\n .INIT(64'h998564666466621A)) \n \\rise_trail_center_offset_r[4]_i_1 \n (.I0(rise_trail_center_0[4]),\n .I1(ninety_offsets[0]),\n .I2(ninety_offsets[1]),\n .I3(rise_trail_center_0[5]),\n .I4(rise_trail_center_0[3]),\n .I5(\\rise_trail_center_offset_r[5]_i_2_n_0 ),\n .O(offset0_return0[4]));\n LUT6 #(\n .INIT(64'hF00E871887700EF0)) \n \\rise_trail_center_offset_r[5]_i_1 \n (.I0(rise_trail_center_0[3]),\n .I1(\\rise_trail_center_offset_r[5]_i_2_n_0 ),\n .I2(rise_trail_center_0[5]),\n .I3(ninety_offsets[1]),\n .I4(ninety_offsets[0]),\n .I5(rise_trail_center_0[4]),\n .O(offset0_return0[5]));\n (* SOFT_HLUTNM = \"soft_lutpair477\" *) \n LUT4 #(\n .INIT(16'hE460)) \n \\rise_trail_center_offset_r[5]_i_2 \n (.I0(ninety_offsets[1]),\n .I1(ninety_offsets[0]),\n .I2(rise_trail_center_0[2]),\n .I3(rise_trail_center_0[1]),\n .O(\\rise_trail_center_offset_r[5]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\rise_trail_r_reg[0]_i_2 \n (.I0(i___26_n_0),\n .O(trailing_edge00_in[0]));\n CARRY4 \\rise_trail_r_reg[3]_i_2 \n (.CI(1'b0),\n .CO({\\rise_trail_r_reg[3]_i_2_n_0 ,\\rise_trail_r_reg[3]_i_2_n_1 ,\\rise_trail_r_reg[3]_i_2_n_2 ,\\rise_trail_r_reg[3]_i_2_n_3 }),\n .CYINIT(1'b1),\n .DI({u_poc_tap_base_n_59,u_poc_tap_base_n_60,u_poc_tap_base_n_61,u_poc_tap_base_n_62}),\n .O(trailing_edge0[3:0]),\n .S({i___22_n_0,i___21_rep_n_0,i___25_rep_n_0,i___26_rep_n_0}));\n CARRY4 \\rise_trail_r_reg[5]_i_3 \n (.CI(\\rise_trail_r_reg[3]_i_2_n_0 ),\n .CO({\\NLW_rise_trail_r_reg[5]_i_3_CO_UNCONNECTED [3:1],\\rise_trail_r_reg[5]_i_3_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,u_poc_tap_base_n_58}),\n .O({\\NLW_rise_trail_r_reg[5]_i_3_O_UNCONNECTED [3:2],trailing_edge0[5:4]}),\n .S({1'b0,1'b0,u_poc_tap_base_n_84,i___24_n_0}));\n CARRY4 \\samp_cntr_r_reg[12]_i_2 \n (.CI(\\samp_cntr_r_reg[8]_i_2_n_0 ),\n .CO({\\samp_cntr_r_reg[12]_i_2_n_0 ,\\samp_cntr_r_reg[12]_i_2_n_1 ,\\samp_cntr_r_reg[12]_i_2_n_2 ,\\samp_cntr_r_reg[12]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(samp_cntr_ns0[12:9]),\n .S({u_poc_tap_base_n_17,u_poc_tap_base_n_18,u_poc_tap_base_n_19,u_poc_tap_base_n_20}));\n CARRY4 \\samp_cntr_r_reg[16]_i_2 \n (.CI(\\samp_cntr_r_reg[12]_i_2_n_0 ),\n .CO({\\NLW_samp_cntr_r_reg[16]_i_2_CO_UNCONNECTED [3],\\samp_cntr_r_reg[16]_i_2_n_1 ,\\samp_cntr_r_reg[16]_i_2_n_2 ,\\samp_cntr_r_reg[16]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(samp_cntr_ns0[16:13]),\n .S({u_poc_tap_base_n_21,u_poc_tap_base_n_22,u_poc_tap_base_n_23,u_poc_tap_base_n_24}));\n CARRY4 \\samp_cntr_r_reg[4]_i_2 \n (.CI(1'b0),\n .CO({\\samp_cntr_r_reg[4]_i_2_n_0 ,\\samp_cntr_r_reg[4]_i_2_n_1 ,\\samp_cntr_r_reg[4]_i_2_n_2 ,\\samp_cntr_r_reg[4]_i_2_n_3 }),\n .CYINIT(u_poc_tap_base_n_76),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(samp_cntr_ns0[4:1]),\n .S({u_poc_tap_base_n_9,u_poc_tap_base_n_10,u_poc_tap_base_n_11,u_poc_tap_base_n_12}));\n CARRY4 \\samp_cntr_r_reg[8]_i_2 \n (.CI(\\samp_cntr_r_reg[4]_i_2_n_0 ),\n .CO({\\samp_cntr_r_reg[8]_i_2_n_0 ,\\samp_cntr_r_reg[8]_i_2_n_1 ,\\samp_cntr_r_reg[8]_i_2_n_2 ,\\samp_cntr_r_reg[8]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(samp_cntr_ns0[8:5]),\n .S({u_poc_tap_base_n_13,u_poc_tap_base_n_14,u_poc_tap_base_n_15,u_poc_tap_base_n_16}));\n LUT2 #(\n .INIT(4'h6)) \n \\samps_hi_r[3]_i_6 \n (.I0(u_poc_tap_base_n_8),\n .I1(pd_out),\n .O(\\samps_hi_r[3]_i_6_n_0 ));\n CARRY4 \\samps_hi_r_reg[11]_i_2 \n (.CI(\\samps_hi_r_reg[7]_i_2_n_0 ),\n .CO({\\samps_hi_r_reg[11]_i_2_n_0 ,\\samps_hi_r_reg[11]_i_2_n_1 ,\\samps_hi_r_reg[11]_i_2_n_2 ,\\samps_hi_r_reg[11]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(samps_hi_ns0[11:8]),\n .S({u_poc_tap_base_n_32,u_poc_tap_base_n_33,u_poc_tap_base_n_34,u_poc_tap_base_n_35}));\n CARRY4 \\samps_hi_r_reg[15]_i_2 \n (.CI(\\samps_hi_r_reg[11]_i_2_n_0 ),\n .CO({\\samps_hi_r_reg[15]_i_2_n_0 ,\\samps_hi_r_reg[15]_i_2_n_1 ,\\samps_hi_r_reg[15]_i_2_n_2 ,\\samps_hi_r_reg[15]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(samps_hi_ns0[15:12]),\n .S({u_poc_tap_base_n_36,u_poc_tap_base_n_37,u_poc_tap_base_n_38,u_poc_tap_base_n_39}));\n CARRY4 \\samps_hi_r_reg[17]_i_2 \n (.CI(\\samps_hi_r_reg[15]_i_2_n_0 ),\n .CO({\\NLW_samps_hi_r_reg[17]_i_2_CO_UNCONNECTED [3:1],\\samps_hi_r_reg[17]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\NLW_samps_hi_r_reg[17]_i_2_O_UNCONNECTED [3:2],samps_hi_ns0[17:16]}),\n .S({1'b0,1'b0,u_poc_tap_base_n_40,u_poc_tap_base_n_41}));\n CARRY4 \\samps_hi_r_reg[3]_i_2 \n (.CI(1'b0),\n .CO({\\samps_hi_r_reg[3]_i_2_n_0 ,\\samps_hi_r_reg[3]_i_2_n_1 ,\\samps_hi_r_reg[3]_i_2_n_2 ,\\samps_hi_r_reg[3]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,u_poc_tap_base_n_8}),\n .O(samps_hi_ns0[3:0]),\n .S({u_poc_tap_base_n_25,u_poc_tap_base_n_26,u_poc_tap_base_n_27,\\samps_hi_r[3]_i_6_n_0 }));\n CARRY4 \\samps_hi_r_reg[7]_i_2 \n (.CI(\\samps_hi_r_reg[3]_i_2_n_0 ),\n .CO({\\samps_hi_r_reg[7]_i_2_n_0 ,\\samps_hi_r_reg[7]_i_2_n_1 ,\\samps_hi_r_reg[7]_i_2_n_2 ,\\samps_hi_r_reg[7]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(samps_hi_ns0[7:4]),\n .S({u_poc_tap_base_n_28,u_poc_tap_base_n_29,u_poc_tap_base_n_30,u_poc_tap_base_n_31}));\n CARRY4 samps_zero_r0_carry__0_i_10\n (.CI(samps_zero_r0_carry__0_i_4_n_0),\n .CO({samps_zero_r0_carry__0_i_10_n_0,samps_zero_r0_carry__0_i_10_n_1,samps_zero_r0_carry__0_i_10_n_2,samps_zero_r0_carry__0_i_10_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,u_poc_tap_base_n_75}),\n .O(samps_lo[13:10]),\n .S({u_poc_tap_base_n_68,u_poc_tap_base_n_69,u_poc_tap_base_n_70,i___28_n_0}));\n CARRY4 samps_zero_r0_carry__0_i_4\n (.CI(samps_zero_r0_carry_i_2_n_0),\n .CO({samps_zero_r0_carry__0_i_4_n_0,samps_zero_r0_carry__0_i_4_n_1,samps_zero_r0_carry__0_i_4_n_2,samps_zero_r0_carry__0_i_4_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(samps_lo[9:6]),\n .S({u_poc_tap_base_n_42,u_poc_tap_base_n_43,u_poc_tap_base_n_44,u_poc_tap_base_n_45}));\n CARRY4 samps_zero_r0_carry__0_i_9\n (.CI(samps_zero_r0_carry__0_i_10_n_0),\n .CO({NLW_samps_zero_r0_carry__0_i_9_CO_UNCONNECTED[3],samps_zero_r0_carry__0_i_9_n_1,samps_zero_r0_carry__0_i_9_n_2,samps_zero_r0_carry__0_i_9_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(samps_lo[17:14]),\n .S({u_poc_tap_base_n_64,u_poc_tap_base_n_65,u_poc_tap_base_n_66,u_poc_tap_base_n_67}));\n CARRY4 samps_zero_r0_carry_i_2\n (.CI(1'b0),\n .CO({samps_zero_r0_carry_i_2_n_0,samps_zero_r0_carry_i_2_n_1,samps_zero_r0_carry_i_2_n_2,samps_zero_r0_carry_i_2_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,u_poc_tap_base_n_74}),\n .O({samps_lo[5:3],NLW_samps_zero_r0_carry_i_2_O_UNCONNECTED[0]}),\n .S({u_poc_tap_base_n_71,u_poc_tap_base_n_72,u_poc_tap_base_n_73,i___27_n_0}));\n ddr3_ifmig_7series_v4_0_poc_edge_store u_edge_center\n (.CLK(CLK),\n .D(trailing_edge),\n .E(i___7_n_0),\n .Q(rise_lead_center_0),\n .\\rise_trail_center_offset_r_reg[3] (rise_trail_center_0),\n .run_polarity_r_reg(u_poc_tap_base_n_53),\n .\\tap_r_reg[5] ({u_poc_tap_base_n_57,u_poc_tap_base_n_58,u_poc_tap_base_n_59,u_poc_tap_base_n_60,u_poc_tap_base_n_61,u_poc_tap_base_n_62}));\n ddr3_ifmig_7series_v4_0_poc_edge_store_7 u_edge_left\n (.CLK(CLK),\n .D({mod_sub1_return[5:4],mod_sub1_return[0]}),\n .DI({u_edge_left_n_0,u_edge_left_n_1}),\n .E(i___6_n_0),\n .O(u_poc_meta_n_27),\n .Q({u_poc_meta_n_59,u_poc_meta_n_60}),\n .S(u_edge_left_n_15),\n .center0_return3(center0_return3),\n .\\center_diff_r_reg[0] (u_edge_left_n_19),\n .\\center_diff_r_reg[0]_0 (u_edge_left_n_20),\n .\\center_diff_r_reg[0]_1 (u_edge_left_n_21),\n .\\center_diff_r_reg[1] (u_edge_left_n_23),\n .\\center_diff_r_reg[3] (u_edge_left_n_33),\n .\\center_diff_r_reg[3]_0 (u_edge_left_n_34),\n .\\center_diff_r_reg[5] (u_edge_left_n_2),\n .\\center_diff_r_reg[5]_0 (u_edge_left_n_22),\n .\\rise_lead_r_reg[0]_0 (\\center_diff_r_reg[0]_i_2_n_0 ),\n .\\rise_lead_r_reg[4]_0 ({u_poc_meta_n_28,u_poc_meta_n_29}),\n .\\rise_lead_r_reg[5]_0 ({\\mmcm_init_lead_reg[5] [5:3],\\mmcm_init_lead_reg[5] [0]}),\n .\\rise_trail_r_reg[1]_0 (u_edge_right_n_27),\n .\\rise_trail_r_reg[2]_0 (u_edge_right_n_26),\n .\\rise_trail_r_reg[3]_0 (u_edge_right_n_8),\n .\\rise_trail_r_reg[4]_0 ({u_poc_meta_n_33,u_poc_meta_n_34}),\n .\\rise_trail_r_reg[5]_0 ({Q[5:3],Q[0]}),\n .samps_zero_r_reg(u_poc_tap_base_n_95),\n .\\tap_r_reg[4] (trailing_edge),\n .\\tap_r_reg[5] ({u_poc_tap_base_n_57,u_poc_tap_base_n_58,u_poc_tap_base_n_59,u_poc_tap_base_n_60,u_poc_tap_base_n_61,u_poc_tap_base_n_62}),\n .use_noise_window(use_noise_window),\n .\\window_center_r_reg[0] ({u_edge_left_n_28,u_edge_left_n_29,u_edge_left_n_30}),\n .\\window_center_r_reg[3] ({u_edge_left_n_25,u_edge_left_n_26,u_edge_left_n_27}),\n .\\window_center_r_reg[6] (rise_lead_left_0),\n .\\window_center_r_reg[6]_0 (rise_trail_left_0),\n .\\window_center_r_reg[6]_1 (u_edge_left_n_24),\n .\\window_center_r_reg[6]_2 ({u_edge_left_n_31,u_edge_left_n_32}));\n ddr3_ifmig_7series_v4_0_poc_edge_store_8 u_edge_right\n (.CLK(CLK),\n .D(mod_sub1_return[3:1]),\n .DI(u_poc_tap_base_n_63),\n .E(i___5_n_0),\n .O({u_poc_meta_n_24,u_poc_meta_n_25,u_poc_meta_n_26}),\n .Q(u_poc_tap_base_n_48),\n .S({u_poc_tap_base_n_85,i___21_n_0,i___25_n_0,i___26_rep__0_n_0}),\n .\\center_diff_r_reg[0] (u_edge_right_n_26),\n .\\center_diff_r_reg[0]_0 (u_edge_right_n_27),\n .\\center_diff_r_reg[1] (u_edge_right_n_8),\n .\\center_diff_r_reg[3] ({u_edge_right_n_22,u_edge_right_n_23,u_edge_right_n_24,u_edge_right_n_25}),\n .\\center_diff_r_reg[3]_0 ({u_edge_right_n_28,u_edge_right_n_29,u_edge_right_n_30}),\n .\\center_diff_r_reg[5] (u_edge_right_n_21),\n .\\center_diff_r_reg[5]_0 (u_edge_right_n_31),\n .\\mmcm_init_lead_reg[5] (\\mmcm_init_lead_reg[5] ),\n .\\mmcm_init_trail_reg[5] (Q),\n .\\rise_lead_r_reg[1]_0 (u_edge_left_n_20),\n .\\rise_lead_r_reg[3]_0 (u_edge_left_n_1),\n .\\rise_lead_r_reg[4]_0 (u_edge_left_n_21),\n .\\rise_lead_r_reg[4]_1 (u_edge_left_n_23),\n .\\rise_lead_r_reg[5]_0 (rise_lead_left_0[5]),\n .\\rise_trail_r_reg[3]_0 ({u_poc_meta_n_30,u_poc_meta_n_31,u_poc_meta_n_32}),\n .\\rise_trail_r_reg[5]_0 (u_edge_left_n_19),\n .\\rise_trail_r_reg[5]_1 (rise_trail_left_0[5]),\n .samps_zero_r_reg(fall_lead_r0),\n .\\tap_r_reg[4] (trailing_edge),\n .\\tap_r_reg[5] ({u_poc_tap_base_n_57,u_poc_tap_base_n_58,u_poc_tap_base_n_59,u_poc_tap_base_n_60,u_poc_tap_base_n_61,u_poc_tap_base_n_62}),\n .\\tap_r_reg[5]_0 ({u_poc_tap_base_n_83,i___23_n_0}),\n .trailing_edge00_in(trailing_edge00_in[5:1]),\n .use_noise_window(use_noise_window));\n ddr3_ifmig_7series_v4_0_poc_meta u_poc_meta\n (.CLK(CLK),\n .D(mod_sub1_return),\n .DI(i___14_n_0),\n .O({u_poc_meta_n_24,u_poc_meta_n_25,u_poc_meta_n_26,u_poc_meta_n_27}),\n .Q(p_0_in1_in),\n .S({center_return1__1_carry_i_1_n_0,center_return1__1_carry_i_2_n_0,center_return1__1_carry_i_3_n_0}),\n .center0_return3(center0_return3),\n .\\center_diff_r_reg[3]_0 ({u_poc_meta_n_30,u_poc_meta_n_31,u_poc_meta_n_32}),\n .\\center_diff_r_reg[4]_0 ({u_edge_left_n_0,u_edge_left_n_1}),\n .\\center_diff_r_reg[5]_0 ({u_poc_meta_n_28,u_poc_meta_n_29}),\n .\\center_diff_r_reg[5]_1 ({u_poc_meta_n_33,u_poc_meta_n_34}),\n .center_return3(center_return3),\n .detect_done_r_reg(detect_done_r_reg),\n .\\diff_r_reg[2]_0 (i___8_n_0),\n .\\diff_r_reg[7]_0 (edge_center),\n .\\diff_r_reg[7]_1 (window_center),\n .\\edge_center_r_reg[0]_0 (diff_ns00_in),\n .\\edge_center_r_reg[3]_0 ({i___47_rep_n_0,i___38_rep_n_0,i___39_rep_n_0,i___48_rep_n_0}),\n .\\edge_center_r_reg[3]_1 ({i___47_n_0,i___38_n_0,i___39_n_0,i___48_rep__0_n_0}),\n .\\edge_center_r_reg[5]_0 ({i___45_n_0,diff_ns0_carry__0_i_1_n_0}),\n .\\edge_center_r_reg[6]_0 (diff),\n .\\edge_center_r_reg[6]_1 ({i___42_n_0,diff_ns1_carry_i_1_n_0,diff_ns1_carry_i_2_n_0,diff_ns1_carry_i_3_n_0}),\n .\\edge_center_r_reg[6]_2 ({i___41_n_0,i___44_n_0,i___46_n_0}),\n .\\edge_diff_r_reg[0]_0 ({u_poc_meta_n_14,u_poc_meta_n_15,u_poc_meta_n_16,u_poc_meta_n_17,u_poc_meta_n_18,u_poc_meta_n_19}),\n .\\edge_diff_r_reg[4]_0 ({center_return1__0_carry__0_i_2_n_0,center_return1__0_carry__0_i_3_n_0}),\n .ocd_edge_detect_rdy_r_reg(ocd_edge_detect_rdy_r_reg),\n .ocd_ktap_left_r_reg(ocd_ktap_left_r_reg),\n .ocd_ktap_left_r_reg_0(ocd_ktap_left_r_reg_0),\n .ocd_ktap_right_r_reg(ocd_ktap_right_r_reg),\n .poc_backup_r_reg_0(poc_backup_r_reg),\n .\\prev_r_reg[0]_0 (\\prev_r_reg[0] ),\n .\\prev_r_reg[0]_1 (\\prev_r_reg[0]_0 ),\n .\\prev_r_reg[2]_0 ({u_poc_meta_n_56,u_poc_meta_n_57,u_poc_meta_n_58}),\n .\\rise_lead_center_offset_r_reg[2]_0 ({center_return1__0_carry_i_1_n_0,center_return1__0_carry_i_2_n_0,center_return1__0_carry_i_3_n_0}),\n .\\rise_lead_center_offset_r_reg[4]_0 ({center_return1__1_carry__0_i_2_n_0,center_return1__1_carry__0_i_3_n_0}),\n .\\rise_lead_center_offset_r_reg[4]_1 ({i___29_n_0,i___31_n_0}),\n .\\rise_lead_r_reg[2] ({u_edge_left_n_28,u_edge_left_n_29,u_edge_left_n_30}),\n .\\rise_lead_r_reg[2]_0 ({u_edge_left_n_25,u_edge_left_n_26,u_edge_left_n_27}),\n .\\rise_lead_r_reg[3] ({u_edge_left_n_34,u_edge_right_n_28,u_edge_right_n_29,u_edge_right_n_30}),\n .\\rise_lead_r_reg[3]_0 ({i___17_n_0,i___18_n_0,i___19_n_0,i___20_rep__0_n_0}),\n .\\rise_lead_r_reg[3]_1 ({offset_return0,rise_lead_center_0[0]}),\n .\\rise_lead_r_reg[4] ({u_edge_left_n_31,u_edge_left_n_32}),\n .\\rise_lead_r_reg[4]_0 ({u_edge_left_n_15,center0_return1__0_carry__0_i_4_n_0,center0_return1__0_carry__0_i_5_n_0}),\n .\\rise_lead_r_reg[4]_1 (u_edge_left_n_2),\n .\\rise_lead_r_reg[4]_2 ({u_edge_left_n_22,i___15_n_0}),\n .\\rise_lead_r_reg[5] ({u_edge_left_n_24,center0_return1__1_carry__0_i_4_n_0,center0_return1__1_carry__0_i_5_n_0}),\n .\\rise_trail_center_offset_r_reg[0]_0 (\\edge_diff_r_reg[0]_i_2_n_0 ),\n .\\rise_trail_center_offset_r_reg[2]_0 ({i___34_rep_n_0,i___35_rep_n_0,i___36_rep_n_0}),\n .\\rise_trail_center_offset_r_reg[3]_0 ({i___33_n_0,i___34_n_0,i___35_n_0,i___36_rep__0_n_0}),\n .\\rise_trail_center_offset_r_reg[5]_0 ({i___30_n_0,i___32_n_0}),\n .\\rise_trail_r_reg[2] ({center0_return1__1_carry_i_4_n_0,center0_return1__1_carry_i_5_n_0,center0_return1__1_carry_i_6_n_0}),\n .\\rise_trail_r_reg[2]_0 ({center0_return1__0_carry_i_4_n_0,center0_return1__0_carry_i_5_n_0,center0_return1__0_carry_i_6_n_0}),\n .\\rise_trail_r_reg[3] ({u_edge_left_n_33,i___18_rep_n_0,i___19_rep_n_0,i___20_rep_n_0}),\n .\\rise_trail_r_reg[3]_0 ({u_edge_right_n_22,u_edge_right_n_23,u_edge_right_n_24,u_edge_right_n_25}),\n .\\rise_trail_r_reg[3]_1 ({offset0_return0,rise_trail_center_0[0]}),\n .\\rise_trail_r_reg[4] (u_edge_right_n_31),\n .\\rise_trail_r_reg[5] ({u_edge_right_n_21,i___16_n_0}),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .\\run_ends_r_reg[1]_0 (\\run_ends_r_reg[1] ),\n .run_polarity_held_r(run_polarity_held_r),\n .run_too_small_r_reg(u_poc_tap_base_n_1),\n .samps_zero_r_reg(i___4_n_0),\n .samps_zero_r_reg_0(u_poc_tap_base_n_52),\n .\\sm_r_reg[1] (\\sm_r_reg[1] ),\n .\\window_center_r_reg[6]_0 ({u_poc_meta_n_59,u_poc_meta_n_60,u_poc_meta_n_61,u_poc_meta_n_62,u_poc_meta_n_63}),\n .\\window_center_r_reg[6]_1 ({diff_ns1_carry_i_4_n_0,diff_ns1_carry_i_5_n_0,diff_ns1_carry_i_6_n_0,diff_ns1_carry_i_7_n_0}),\n .\\window_center_r_reg[6]_2 ({i___40_n_0,i___37_n_0,i___43_n_0,diff_ns0_carry__0_i_2_n_0}));\n ddr3_ifmig_7series_v4_0_poc_tap_base u_poc_tap_base\n (.CLK(CLK),\n .D({i___11_n_0,i___10_n_0}),\n .DI(u_poc_tap_base_n_63),\n .E(i___12_n_0),\n .Q({u_poc_tap_base_n_4,u_poc_tap_base_n_5,u_poc_tap_base_n_6,u_poc_tap_base_n_7,u_poc_tap_base_n_8}),\n .S({u_poc_tap_base_n_9,u_poc_tap_base_n_10,u_poc_tap_base_n_11,u_poc_tap_base_n_12}),\n .ocd_ktap_left_r_reg(ocd_ktap_left_r_reg),\n .ocd_ktap_right_r_reg(ocd_ktap_right_r_reg),\n .poc_sample_pd(poc_sample_pd),\n .psdone(psdone),\n .\\qcntr_r_reg[0] (\\qcntr_r_reg[0] ),\n .\\rise_lead_r_reg[5] ({u_poc_tap_base_n_57,u_poc_tap_base_n_58,u_poc_tap_base_n_59,u_poc_tap_base_n_60,u_poc_tap_base_n_61,u_poc_tap_base_n_62}),\n .\\rise_trail_r_reg[0] (u_poc_tap_base_n_53),\n .\\rise_trail_r_reg[3] (u_poc_tap_base_n_85),\n .\\rise_trail_r_reg[5] (trailing_edge),\n .\\rise_trail_r_reg[5]_0 (u_poc_tap_base_n_83),\n .\\rise_trail_r_reg[5]_1 (u_poc_tap_base_n_84),\n .\\rise_trail_r_reg[5]_2 (fall_lead_r0),\n .\\rise_trail_r_reg[5]_3 (u_poc_tap_base_n_95),\n .rstdiv0_sync_r1_reg_rep(rstdiv0_sync_r1_reg_rep),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .\\run_r_reg[0]_0 (u_poc_tap_base_n_0),\n .\\run_r_reg[0]_1 (u_poc_tap_base_n_2),\n .\\run_r_reg[0]_2 (u_poc_tap_base_n_3),\n .\\run_r_reg[2]_0 (i___9_n_0),\n .\\run_r_reg[4]_0 ({u_poc_tap_base_n_47,u_poc_tap_base_n_48,u_poc_tap_base_n_49,u_poc_tap_base_n_50,u_poc_tap_base_n_51}),\n .run_too_small_r3_reg(u_poc_tap_base_n_1),\n .run_too_small_r_reg_0(u_poc_tap_base_n_52),\n .samp_cntr_ns0(samp_cntr_ns0),\n .\\samp_cntr_r_reg[0]_0 (u_poc_tap_base_n_76),\n .\\samp_cntr_r_reg[12]_0 ({u_poc_tap_base_n_17,u_poc_tap_base_n_18,u_poc_tap_base_n_19,u_poc_tap_base_n_20}),\n .\\samp_cntr_r_reg[16]_0 ({u_poc_tap_base_n_21,u_poc_tap_base_n_22,u_poc_tap_base_n_23,u_poc_tap_base_n_24}),\n .\\samp_cntr_r_reg[8]_0 ({u_poc_tap_base_n_13,u_poc_tap_base_n_14,u_poc_tap_base_n_15,u_poc_tap_base_n_16}),\n .\\samp_wait_r_reg[4]_0 (i___13_n_0),\n .\\samp_wait_r_reg[6]_0 (u_poc_tap_base_n_86),\n .\\samp_wait_r_reg[7]_0 ({samp_wait_r[7:6],samp_wait_r[4:0]}),\n .samps_hi_ns0(samps_hi_ns0),\n .\\samps_hi_r_reg[11]_0 ({u_poc_tap_base_n_32,u_poc_tap_base_n_33,u_poc_tap_base_n_34,u_poc_tap_base_n_35}),\n .\\samps_hi_r_reg[15]_0 ({u_poc_tap_base_n_36,u_poc_tap_base_n_37,u_poc_tap_base_n_38,u_poc_tap_base_n_39}),\n .\\samps_hi_r_reg[17]_0 ({u_poc_tap_base_n_40,u_poc_tap_base_n_41}),\n .\\samps_hi_r_reg[3]_0 ({u_poc_tap_base_n_25,u_poc_tap_base_n_26,u_poc_tap_base_n_27}),\n .\\samps_hi_r_reg[7]_0 ({u_poc_tap_base_n_28,u_poc_tap_base_n_29,u_poc_tap_base_n_30,u_poc_tap_base_n_31}),\n .samps_lo(samps_lo),\n .samps_zero_r_reg_0({u_poc_tap_base_n_42,u_poc_tap_base_n_43,u_poc_tap_base_n_44,u_poc_tap_base_n_45}),\n .samps_zero_r_reg_1({u_poc_tap_base_n_64,u_poc_tap_base_n_65,u_poc_tap_base_n_66,u_poc_tap_base_n_67}),\n .samps_zero_r_reg_2({u_poc_tap_base_n_68,u_poc_tap_base_n_69,u_poc_tap_base_n_70}),\n .samps_zero_r_reg_3({u_poc_tap_base_n_71,u_poc_tap_base_n_72,u_poc_tap_base_n_73}),\n .samps_zero_r_reg_4(u_poc_tap_base_n_74),\n .samps_zero_r_reg_5(u_poc_tap_base_n_75),\n .\\sm_r_reg[0]_0 (u_poc_tap_base_n_54),\n .\\sm_r_reg[0]_1 (u_poc_tap_base_n_55),\n .\\tap_r_reg[0]_0 (u_poc_tap_base_n_46),\n .trailing_edge0(trailing_edge0),\n .trailing_edge00_in(trailing_edge00_in));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_rank_cntrl\" *) \nmodule ddr3_ifmig_7series_v4_0_rank_cntrl\n (act_delayed,\n read_this_rank_r,\n inhbt_act_faw_r,\n periodic_rd_request_r,\n periodic_rd_cntr1_r,\n \\grant_r_reg[0] ,\n \\rtw_timer.rtw_cnt_r_reg[1]_0 ,\n \\periodic_rd_generation.periodic_rd_request_r_reg_0 ,\n \\inhbt_act_faw.inhbt_act_faw_r_reg_0 ,\n granted_col_r_reg,\n act_this_rank,\n CLK,\n read_this_rank,\n SR,\n periodic_rd_ack_r_lcl_reg,\n \\periodic_read_request.periodic_rd_grant_r_reg[0] ,\n init_calib_complete_reg_rep__6,\n \\grant_r_reg[0]_0 ,\n rstdiv0_sync_r1_reg_rep__20,\n rstdiv0_sync_r1_reg_rep__21,\n \\grant_r_reg[1] ,\n \\wr_this_rank_r_reg[0] ,\n maint_prescaler_tick_r,\n \\act_this_rank_r_reg[0] ,\n init_calib_complete_reg_rep__7,\n \\periodic_rd_generation.read_this_rank_r_reg_0 ,\n init_calib_complete_reg_rep__6_0,\n \\inhbt_act_faw.faw_cnt_r_reg[1]_0 );\n output act_delayed;\n output read_this_rank_r;\n output inhbt_act_faw_r;\n output periodic_rd_request_r;\n output periodic_rd_cntr1_r;\n output \\grant_r_reg[0] ;\n output [0:0]\\rtw_timer.rtw_cnt_r_reg[1]_0 ;\n output \\periodic_rd_generation.periodic_rd_request_r_reg_0 ;\n output [2:0]\\inhbt_act_faw.inhbt_act_faw_r_reg_0 ;\n output granted_col_r_reg;\n input act_this_rank;\n input CLK;\n input read_this_rank;\n input [0:0]SR;\n input periodic_rd_ack_r_lcl_reg;\n input \\periodic_read_request.periodic_rd_grant_r_reg[0] ;\n input init_calib_complete_reg_rep__6;\n input \\grant_r_reg[0]_0 ;\n input rstdiv0_sync_r1_reg_rep__20;\n input rstdiv0_sync_r1_reg_rep__21;\n input \\grant_r_reg[1] ;\n input \\wr_this_rank_r_reg[0] ;\n input maint_prescaler_tick_r;\n input \\act_this_rank_r_reg[0] ;\n input init_calib_complete_reg_rep__7;\n input \\periodic_rd_generation.read_this_rank_r_reg_0 ;\n input init_calib_complete_reg_rep__6_0;\n input [2:0]\\inhbt_act_faw.faw_cnt_r_reg[1]_0 ;\n\n wire CLK;\n wire [0:0]SR;\n wire act_delayed;\n wire act_this_rank;\n wire \\act_this_rank_r_reg[0] ;\n wire \\grant_r_reg[0] ;\n wire \\grant_r_reg[0]_0 ;\n wire \\grant_r_reg[1] ;\n wire granted_col_r_reg;\n wire [2:0]\\inhbt_act_faw.faw_cnt_r_reg[1]_0 ;\n wire \\inhbt_act_faw.inhbt_act_faw_r_i_1_n_0 ;\n wire [2:0]\\inhbt_act_faw.inhbt_act_faw_r_reg_0 ;\n wire inhbt_act_faw_r;\n wire init_calib_complete_reg_rep__6;\n wire init_calib_complete_reg_rep__6_0;\n wire init_calib_complete_reg_rep__7;\n wire maint_prescaler_tick_r;\n wire periodic_rd_ack_r_lcl_reg;\n wire periodic_rd_cntr1_r;\n wire \\periodic_rd_generation.periodic_rd_request_r_reg_0 ;\n wire \\periodic_rd_generation.periodic_rd_timer_r[0]_i_1_n_0 ;\n wire \\periodic_rd_generation.periodic_rd_timer_r[1]_i_1_n_0 ;\n wire \\periodic_rd_generation.periodic_rd_timer_r[2]_i_1_n_0 ;\n wire \\periodic_rd_generation.read_this_rank_r_reg_0 ;\n wire periodic_rd_request_r;\n wire [2:0]periodic_rd_timer_r;\n wire \\periodic_read_request.periodic_rd_grant_r_reg[0] ;\n wire read_this_rank;\n wire read_this_rank_r;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire [1:0]rtw_cnt_ns;\n wire [0:0]rtw_cnt_r;\n wire [0:0]\\rtw_timer.rtw_cnt_r_reg[1]_0 ;\n wire \\wr_this_rank_r_reg[0] ;\n wire [2:0]wtr_cnt_ns;\n wire [2:0]wtr_cnt_r;\n\n LUT4 #(\n .INIT(16'hCCCD)) \n \\grant_r[1]_i_4__0 \n (.I0(\\wr_this_rank_r_reg[0] ),\n .I1(rstdiv0_sync_r1_reg_rep__20),\n .I2(wtr_cnt_r[1]),\n .I3(wtr_cnt_r[2]),\n .O(granted_col_r_reg));\n LUT5 #(\n .INIT(32'h55554555)) \n i___25_i_2\n (.I0(periodic_rd_request_r),\n .I1(periodic_rd_timer_r[2]),\n .I2(maint_prescaler_tick_r),\n .I3(periodic_rd_timer_r[0]),\n .I4(periodic_rd_timer_r[1]),\n .O(\\periodic_rd_generation.periodic_rd_request_r_reg_0 ));\n (* XILINX_LEGACY_PRIM = \"SRLC32E\" *) \n (* box_type = \"PRIMITIVE\" *) \n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/mc0/rank_mach0/rank_cntrl \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/mc0/rank_mach0/rank_cntrl[0].rank_cntrl0/inhbt_act_faw.SRLC32E0 \" *) \n SRL16E #(\n .INIT(16'h0000),\n .IS_CLK_INVERTED(1'b0)) \n \\inhbt_act_faw.SRLC32E0 \n (.A0(1'b1),\n .A1(1'b0),\n .A2(1'b1),\n .A3(1'b0),\n .CE(1'b1),\n .CLK(CLK),\n .D(act_this_rank),\n .Q(act_delayed));\n FDRE #(\n .INIT(1'b0)) \n \\inhbt_act_faw.faw_cnt_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\inhbt_act_faw.faw_cnt_r_reg[1]_0 [0]),\n .Q(\\inhbt_act_faw.inhbt_act_faw_r_reg_0 [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\inhbt_act_faw.faw_cnt_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\inhbt_act_faw.faw_cnt_r_reg[1]_0 [1]),\n .Q(\\inhbt_act_faw.inhbt_act_faw_r_reg_0 [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\inhbt_act_faw.faw_cnt_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\inhbt_act_faw.faw_cnt_r_reg[1]_0 [2]),\n .Q(\\inhbt_act_faw.inhbt_act_faw_r_reg_0 [2]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0001000020000220)) \n \\inhbt_act_faw.inhbt_act_faw_r_i_1 \n (.I0(\\inhbt_act_faw.inhbt_act_faw_r_reg_0 [2]),\n .I1(rstdiv0_sync_r1_reg_rep__21),\n .I2(act_delayed),\n .I3(\\act_this_rank_r_reg[0] ),\n .I4(\\inhbt_act_faw.inhbt_act_faw_r_reg_0 [0]),\n .I5(\\inhbt_act_faw.inhbt_act_faw_r_reg_0 [1]),\n .O(\\inhbt_act_faw.inhbt_act_faw_r_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\inhbt_act_faw.inhbt_act_faw_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\inhbt_act_faw.inhbt_act_faw_r_i_1_n_0 ),\n .Q(inhbt_act_faw_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\periodic_rd_generation.periodic_rd_cntr1_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\periodic_read_request.periodic_rd_grant_r_reg[0] ),\n .Q(periodic_rd_cntr1_r),\n .R(SR));\n FDRE #(\n .INIT(1'b0)) \n \\periodic_rd_generation.periodic_rd_request_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(periodic_rd_ack_r_lcl_reg),\n .Q(periodic_rd_request_r),\n .R(SR));\n LUT6 #(\n .INIT(64'hFFFFFFFF3C78FFFF)) \n \\periodic_rd_generation.periodic_rd_timer_r[0]_i_1 \n (.I0(periodic_rd_timer_r[2]),\n .I1(maint_prescaler_tick_r),\n .I2(periodic_rd_timer_r[0]),\n .I3(periodic_rd_timer_r[1]),\n .I4(init_calib_complete_reg_rep__6_0),\n .I5(\\periodic_rd_generation.read_this_rank_r_reg_0 ),\n .O(\\periodic_rd_generation.periodic_rd_timer_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00000000F3080000)) \n \\periodic_rd_generation.periodic_rd_timer_r[1]_i_1 \n (.I0(periodic_rd_timer_r[2]),\n .I1(maint_prescaler_tick_r),\n .I2(periodic_rd_timer_r[0]),\n .I3(periodic_rd_timer_r[1]),\n .I4(init_calib_complete_reg_rep__7),\n .I5(\\periodic_rd_generation.read_this_rank_r_reg_0 ),\n .O(\\periodic_rd_generation.periodic_rd_timer_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFAAE2FFFF)) \n \\periodic_rd_generation.periodic_rd_timer_r[2]_i_1 \n (.I0(periodic_rd_timer_r[2]),\n .I1(maint_prescaler_tick_r),\n .I2(periodic_rd_timer_r[0]),\n .I3(periodic_rd_timer_r[1]),\n .I4(init_calib_complete_reg_rep__7),\n .I5(\\periodic_rd_generation.read_this_rank_r_reg_0 ),\n .O(\\periodic_rd_generation.periodic_rd_timer_r[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\periodic_rd_generation.periodic_rd_timer_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\periodic_rd_generation.periodic_rd_timer_r[0]_i_1_n_0 ),\n .Q(periodic_rd_timer_r[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\periodic_rd_generation.periodic_rd_timer_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\periodic_rd_generation.periodic_rd_timer_r[1]_i_1_n_0 ),\n .Q(periodic_rd_timer_r[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\periodic_rd_generation.periodic_rd_timer_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\periodic_rd_generation.periodic_rd_timer_r[2]_i_1_n_0 ),\n .Q(periodic_rd_timer_r[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\periodic_rd_generation.read_this_rank_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(read_this_rank),\n .Q(read_this_rank_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\refresh_generation.refresh_bank_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(init_calib_complete_reg_rep__6),\n .Q(\\grant_r_reg[0] ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1069\" *) \n LUT4 #(\n .INIT(16'h0008)) \n \\rtw_timer.rtw_cnt_r[0]_i_1 \n (.I0(\\grant_r_reg[0]_0 ),\n .I1(\\rtw_timer.rtw_cnt_r_reg[1]_0 ),\n .I2(rstdiv0_sync_r1_reg_rep__20),\n .I3(rtw_cnt_r),\n .O(rtw_cnt_ns[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1069\" *) \n LUT4 #(\n .INIT(16'h0D05)) \n \\rtw_timer.rtw_cnt_r[1]_i_1 \n (.I0(\\grant_r_reg[0]_0 ),\n .I1(\\rtw_timer.rtw_cnt_r_reg[1]_0 ),\n .I2(rstdiv0_sync_r1_reg_rep__21),\n .I3(rtw_cnt_r),\n .O(rtw_cnt_ns[1]));\n FDRE #(\n .INIT(1'b0)) \n \\rtw_timer.rtw_cnt_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(rtw_cnt_ns[0]),\n .Q(rtw_cnt_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rtw_timer.rtw_cnt_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(rtw_cnt_ns[1]),\n .Q(\\rtw_timer.rtw_cnt_r_reg[1]_0 ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1070\" *) \n LUT4 #(\n .INIT(16'h5400)) \n \\wtr_timer.wtr_cnt_r[0]_i_1 \n (.I0(wtr_cnt_r[0]),\n .I1(wtr_cnt_r[2]),\n .I2(wtr_cnt_r[1]),\n .I3(\\grant_r_reg[1] ),\n .O(wtr_cnt_ns[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1070\" *) \n LUT4 #(\n .INIT(16'h8820)) \n \\wtr_timer.wtr_cnt_r[1]_i_1 \n (.I0(\\grant_r_reg[1] ),\n .I1(wtr_cnt_r[1]),\n .I2(wtr_cnt_r[2]),\n .I3(wtr_cnt_r[0]),\n .O(wtr_cnt_ns[1]));\n LUT5 #(\n .INIT(32'h0000FFA8)) \n \\wtr_timer.wtr_cnt_r[2]_i_1 \n (.I0(wtr_cnt_r[2]),\n .I1(wtr_cnt_r[0]),\n .I2(wtr_cnt_r[1]),\n .I3(\\wr_this_rank_r_reg[0] ),\n .I4(rstdiv0_sync_r1_reg_rep__21),\n .O(wtr_cnt_ns[2]));\n FDRE #(\n .INIT(1'b0)) \n \\wtr_timer.wtr_cnt_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(wtr_cnt_ns[0]),\n .Q(wtr_cnt_r[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wtr_timer.wtr_cnt_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(wtr_cnt_ns[1]),\n .Q(wtr_cnt_r[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wtr_timer.wtr_cnt_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(wtr_cnt_ns[2]),\n .Q(wtr_cnt_r[2]),\n .R(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_rank_common\" *) \nmodule ddr3_ifmig_7series_v4_0_rank_common\n (maint_prescaler_tick_r,\n maint_prescaler_tick_ns,\n \\maintenance_request.new_maint_rank_r_reg_0 ,\n \\maintenance_request.maint_req_r_lcl_reg_0 ,\n maint_req_r,\n \\periodic_read_request.upd_last_master_r_reg_0 ,\n app_ref_ack,\n app_zq_ack,\n \\maint_controller.maint_srx_r1_reg ,\n \\maintenance_request.maint_sre_r_lcl_reg_0 ,\n \\grant_r_reg[0] ,\n \\grant_r_reg[0]_0 ,\n \\maintenance_request.maint_zq_r_lcl_reg_0 ,\n periodic_rd_r,\n app_ref_r,\n app_zq_r,\n periodic_rd_r_cnt,\n periodic_rd_grant_r,\n app_sr_active,\n maint_ref_zq_wip,\n Q,\n \\refresh_timer.refresh_timer_r_reg[5]_0 ,\n \\refresh_timer.refresh_timer_r_reg[4]_0 ,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[0]_0 ,\n \\maintenance_request.maint_sre_r_lcl_reg_1 ,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ,\n \\last_master_r_reg[2] ,\n mc_cke_ns,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] ,\n \\refresh_generation.refresh_bank_r_reg[0] ,\n S,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ,\n CLK,\n \\maint_controller.maint_wip_r_lcl_reg ,\n SR,\n \\zq_cntrl.zq_request_logic.zq_request_r_reg_0 ,\n init_calib_complete_reg_rep__6,\n maint_prescaler_r1,\n periodic_rd_ack_r_lcl_reg,\n \\refresh_generation.refresh_bank_r_reg[0]_0 ,\n app_zq_r_reg_0,\n \\periodic_read_request.periodic_rd_r_lcl_reg_0 ,\n \\periodic_rd_generation.periodic_rd_request_r_reg ,\n \\maintenance_request.maint_sre_r_lcl_reg_2 ,\n \\refresh_generation.refresh_bank_r_reg[0]_1 ,\n O,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 ,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 ,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 ,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 ,\n init_calib_complete_reg_rep__6_0,\n app_sr_req,\n D,\n \\refresh_generation.refresh_bank_r_reg[0]_2 ,\n \\last_master_r_reg[2]_0 ,\n rstdiv0_sync_r1_reg_rep__20,\n periodic_rd_request_r,\n cke_r,\n insert_maint_r1,\n E,\n \\generate_maint_cmds.insert_maint_r_lcl_reg ,\n rstdiv0_sync_r1_reg_rep__21,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ,\n SS,\n \\maint_prescaler.maint_prescaler_r_reg[0]_0 ,\n init_calib_complete_reg_rep__6_1,\n \\refresh_timer.refresh_timer_r_reg[0]_0 );\n output maint_prescaler_tick_r;\n output maint_prescaler_tick_ns;\n output \\maintenance_request.new_maint_rank_r_reg_0 ;\n output \\maintenance_request.maint_req_r_lcl_reg_0 ;\n output maint_req_r;\n output \\periodic_read_request.upd_last_master_r_reg_0 ;\n output app_ref_ack;\n output app_zq_ack;\n output \\maint_controller.maint_srx_r1_reg ;\n output \\maintenance_request.maint_sre_r_lcl_reg_0 ;\n output \\grant_r_reg[0] ;\n output \\grant_r_reg[0]_0 ;\n output \\maintenance_request.maint_zq_r_lcl_reg_0 ;\n output periodic_rd_r;\n output app_ref_r;\n output app_zq_r;\n output periodic_rd_r_cnt;\n output periodic_rd_grant_r;\n output app_sr_active;\n output maint_ref_zq_wip;\n output [1:0]Q;\n output \\refresh_timer.refresh_timer_r_reg[5]_0 ;\n output [1:0]\\refresh_timer.refresh_timer_r_reg[4]_0 ;\n output \\zq_cntrl.zq_timer.zq_timer_r_reg[0]_0 ;\n output [2:0]\\maintenance_request.maint_sre_r_lcl_reg_1 ;\n output \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ;\n output [2:0]\\last_master_r_reg[2] ;\n output [0:0]mc_cke_ns;\n output \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ;\n output [0:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ;\n output \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] ;\n output \\refresh_generation.refresh_bank_r_reg[0] ;\n output [3:0]S;\n output [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ;\n output [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ;\n output [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ;\n output [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ;\n input CLK;\n input \\maint_controller.maint_wip_r_lcl_reg ;\n input [0:0]SR;\n input \\zq_cntrl.zq_request_logic.zq_request_r_reg_0 ;\n input init_calib_complete_reg_rep__6;\n input maint_prescaler_r1;\n input periodic_rd_ack_r_lcl_reg;\n input \\refresh_generation.refresh_bank_r_reg[0]_0 ;\n input app_zq_r_reg_0;\n input \\periodic_read_request.periodic_rd_r_lcl_reg_0 ;\n input \\periodic_rd_generation.periodic_rd_request_r_reg ;\n input \\maintenance_request.maint_sre_r_lcl_reg_2 ;\n input \\refresh_generation.refresh_bank_r_reg[0]_1 ;\n input [3:0]O;\n input [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 ;\n input [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 ;\n input [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 ;\n input [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 ;\n input init_calib_complete_reg_rep__6_0;\n input app_sr_req;\n input [1:0]D;\n input \\refresh_generation.refresh_bank_r_reg[0]_2 ;\n input \\last_master_r_reg[2]_0 ;\n input rstdiv0_sync_r1_reg_rep__20;\n input periodic_rd_request_r;\n input cke_r;\n input insert_maint_r1;\n input [0:0]E;\n input \\generate_maint_cmds.insert_maint_r_lcl_reg ;\n input rstdiv0_sync_r1_reg_rep__21;\n input [0:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ;\n input [0:0]SS;\n input [0:0]\\maint_prescaler.maint_prescaler_r_reg[0]_0 ;\n input [0:0]init_calib_complete_reg_rep__6_1;\n input [0:0]\\refresh_timer.refresh_timer_r_reg[0]_0 ;\n\n wire CLK;\n wire [1:0]D;\n wire [0:0]E;\n wire [3:0]O;\n wire [1:0]Q;\n wire [3:0]S;\n wire [0:0]SR;\n wire [0:0]SS;\n wire app_ref_ack;\n wire app_ref_ack_ns;\n wire app_ref_r;\n wire app_sr_active;\n wire app_sr_req;\n wire app_zq_ack;\n wire app_zq_ack_ns;\n wire app_zq_r;\n wire app_zq_r_reg_0;\n wire cke_r;\n wire [1:0]ckesr_timer_r;\n wire \\generate_maint_cmds.insert_maint_r_lcl_reg ;\n wire \\grant_r_reg[0] ;\n wire \\grant_r_reg[0]_0 ;\n wire i___16_i_3_n_0;\n wire i___18_i_2_n_0;\n wire inhbt_srx;\n wire init_calib_complete_reg_rep__6;\n wire init_calib_complete_reg_rep__6_0;\n wire [0:0]init_calib_complete_reg_rep__6_1;\n wire insert_maint_r1;\n wire [2:0]\\last_master_r_reg[2] ;\n wire \\last_master_r_reg[2]_0 ;\n wire \\maint_controller.maint_srx_r1_reg ;\n wire \\maint_controller.maint_wip_r_lcl_reg ;\n wire [0:0]\\maint_prescaler.maint_prescaler_r_reg[0]_0 ;\n wire [5:2]\\maint_prescaler.maint_prescaler_r_reg__0 ;\n wire [5:0]maint_prescaler_r0;\n wire maint_prescaler_r1;\n wire maint_prescaler_tick_ns;\n wire maint_prescaler_tick_r;\n wire maint_ref_zq_wip;\n wire maint_req_r;\n wire \\maintenance_request.maint_arb0_n_0 ;\n wire \\maintenance_request.maint_arb0_n_4 ;\n wire \\maintenance_request.maint_arb0_n_8 ;\n wire \\maintenance_request.maint_req_r_lcl_reg_0 ;\n wire \\maintenance_request.maint_sre_r_lcl_reg_0 ;\n wire [2:0]\\maintenance_request.maint_sre_r_lcl_reg_1 ;\n wire \\maintenance_request.maint_sre_r_lcl_reg_2 ;\n wire \\maintenance_request.maint_srx_r_lcl_i_2_n_0 ;\n wire \\maintenance_request.maint_zq_r_lcl_reg_0 ;\n wire \\maintenance_request.new_maint_rank_r_reg_0 ;\n wire [0:0]mc_cke_ns;\n wire periodic_rd_ack_r_lcl_reg;\n wire \\periodic_rd_generation.periodic_rd_request_r_reg ;\n wire periodic_rd_grant_r;\n wire periodic_rd_r;\n wire periodic_rd_r_cnt;\n wire periodic_rd_request_r;\n wire \\periodic_read_request.periodic_rd_r_lcl_reg_0 ;\n wire \\periodic_read_request.upd_last_master_r_reg_0 ;\n wire \\refresh_generation.refresh_bank_r_reg[0] ;\n wire \\refresh_generation.refresh_bank_r_reg[0]_0 ;\n wire \\refresh_generation.refresh_bank_r_reg[0]_1 ;\n wire \\refresh_generation.refresh_bank_r_reg[0]_2 ;\n wire \\refresh_timer.refresh_timer_r[5]_i_3_n_0 ;\n wire [0:0]\\refresh_timer.refresh_timer_r_reg[0]_0 ;\n wire [1:0]\\refresh_timer.refresh_timer_r_reg[4]_0 ;\n wire \\refresh_timer.refresh_timer_r_reg[5]_0 ;\n wire [5:2]\\refresh_timer.refresh_timer_r_reg__0 ;\n wire [5:0]refresh_timer_r0;\n wire refresh_timer_r0_0;\n wire [0:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ;\n wire [0:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ;\n wire \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ;\n wire \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] ;\n wire \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire sel;\n wire \\sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1_n_0 ;\n wire \\sr_cntrl.ckesr_timer.ckesr_timer_r[1]_i_1_n_0 ;\n wire upd_last_master_ns;\n wire \\zq_cntrl.zq_request_logic.zq_request_r_reg_0 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r[0]_i_12_n_0 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r[0]_i_5_n_0 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r[0]_i_6_n_0 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r[0]_i_7_n_0 ;\n wire [19:0]\\zq_cntrl.zq_timer.zq_timer_r_reg ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[0]_0 ;\n wire [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ;\n wire [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 ;\n wire [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ;\n wire [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 ;\n wire [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ;\n wire [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 ;\n wire [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ;\n wire [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 ;\n wire zq_timer_r0;\n\n (* SOFT_HLUTNM = \"soft_lutpair1079\" *) \n LUT3 #(\n .INIT(8'h8A)) \n app_ref_ack_r_i_1\n (.I0(app_ref_r),\n .I1(\\refresh_generation.refresh_bank_r_reg[0]_2 ),\n .I2(init_calib_complete_reg_rep__6_0),\n .O(app_ref_ack_ns));\n FDRE #(\n .INIT(1'b0)) \n app_ref_ack_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(app_ref_ack_ns),\n .Q(app_ref_ack),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n app_ref_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\refresh_generation.refresh_bank_r_reg[0]_0 ),\n .Q(app_ref_r),\n .R(maint_prescaler_r1));\n FDRE #(\n .INIT(1'b0)) \n app_sr_active_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\maintenance_request.maint_sre_r_lcl_reg_2 ),\n .Q(app_sr_active),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1079\" *) \n LUT3 #(\n .INIT(8'h2A)) \n app_zq_ack_r_i_1\n (.I0(app_zq_r),\n .I1(init_calib_complete_reg_rep__6_0),\n .I2(\\grant_r_reg[0] ),\n .O(app_zq_ack_ns));\n FDRE #(\n .INIT(1'b0)) \n app_zq_ack_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(app_zq_ack_ns),\n .Q(app_zq_ack),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n app_zq_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(app_zq_r_reg_0),\n .Q(app_zq_r),\n .R(maint_prescaler_r1));\n (* SOFT_HLUTNM = \"soft_lutpair1075\" *) \n LUT4 #(\n .INIT(16'h0ECC)) \n cke_r_i_2\n (.I0(\\maint_controller.maint_srx_r1_reg ),\n .I1(cke_r),\n .I2(\\maintenance_request.maint_sre_r_lcl_reg_0 ),\n .I3(insert_maint_r1),\n .O(mc_cke_ns));\n LUT6 #(\n .INIT(64'h0000000000100000)) \n i___16_i_1\n (.I0(\\refresh_timer.refresh_timer_r_reg__0 [2]),\n .I1(\\refresh_timer.refresh_timer_r_reg__0 [5]),\n .I2(maint_prescaler_tick_r),\n .I3(\\refresh_timer.refresh_timer_r_reg[4]_0 [1]),\n .I4(\\refresh_timer.refresh_timer_r_reg[4]_0 [0]),\n .I5(i___16_i_3_n_0),\n .O(\\refresh_timer.refresh_timer_r_reg[5]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1075\" *) \n LUT4 #(\n .INIT(16'h0100)) \n i___16_i_2\n (.I0(\\maintenance_request.maint_zq_r_lcl_reg_0 ),\n .I1(\\maintenance_request.maint_sre_r_lcl_reg_0 ),\n .I2(\\maint_controller.maint_srx_r1_reg ),\n .I3(insert_maint_r1),\n .O(\\refresh_generation.refresh_bank_r_reg[0] ));\n LUT2 #(\n .INIT(4'hE)) \n i___16_i_3\n (.I0(\\refresh_timer.refresh_timer_r_reg__0 [3]),\n .I1(\\refresh_timer.refresh_timer_r_reg__0 [4]),\n .O(i___16_i_3_n_0));\n LUT4 #(\n .INIT(16'hA8AA)) \n i___18_i_1\n (.I0(init_calib_complete_reg_rep__6_0),\n .I1(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0 ),\n .I2(i___18_i_2_n_0),\n .I3(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_7_n_0 ),\n .O(\\zq_cntrl.zq_timer.zq_timer_r_reg[0]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1074\" *) \n LUT5 #(\n .INIT(32'hFFFFFFBF)) \n i___18_i_2\n (.I0(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_6_n_0 ),\n .I1(maint_prescaler_tick_r),\n .I2(\\zq_cntrl.zq_timer.zq_timer_r_reg [0]),\n .I3(\\zq_cntrl.zq_timer.zq_timer_r_reg [2]),\n .I4(\\zq_cntrl.zq_timer.zq_timer_r_reg [9]),\n .O(i___18_i_2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1073\" *) \n LUT3 #(\n .INIT(8'h54)) \n i___19_i_1\n (.I0(\\maintenance_request.maint_zq_r_lcl_reg_0 ),\n .I1(\\maint_controller.maint_srx_r1_reg ),\n .I2(\\maintenance_request.maint_sre_r_lcl_reg_0 ),\n .O(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ));\n (* SOFT_HLUTNM = \"soft_lutpair1071\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\maint_prescaler.maint_prescaler_r[0]_i_1 \n (.I0(Q[0]),\n .O(maint_prescaler_r0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1077\" *) \n LUT3 #(\n .INIT(8'hA9)) \n \\maint_prescaler.maint_prescaler_r[2]_i_1 \n (.I0(\\maint_prescaler.maint_prescaler_r_reg__0 [2]),\n .I1(Q[1]),\n .I2(Q[0]),\n .O(maint_prescaler_r0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1077\" *) \n LUT4 #(\n .INIT(16'hAAA9)) \n \\maint_prescaler.maint_prescaler_r[3]_i_1 \n (.I0(\\maint_prescaler.maint_prescaler_r_reg__0 [3]),\n .I1(\\maint_prescaler.maint_prescaler_r_reg__0 [2]),\n .I2(Q[0]),\n .I3(Q[1]),\n .O(maint_prescaler_r0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1071\" *) \n LUT5 #(\n .INIT(32'hAAAAAAA9)) \n \\maint_prescaler.maint_prescaler_r[4]_i_1 \n (.I0(\\maint_prescaler.maint_prescaler_r_reg__0 [4]),\n .I1(\\maint_prescaler.maint_prescaler_r_reg__0 [3]),\n .I2(Q[1]),\n .I3(Q[0]),\n .I4(\\maint_prescaler.maint_prescaler_r_reg__0 [2]),\n .O(maint_prescaler_r0[4]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\maint_prescaler.maint_prescaler_r[5]_i_1 \n (.I0(\\maint_prescaler.maint_prescaler_r_reg__0 [5]),\n .I1(\\maint_prescaler.maint_prescaler_r_reg__0 [3]),\n .I2(\\maint_prescaler.maint_prescaler_r_reg__0 [4]),\n .I3(\\maint_prescaler.maint_prescaler_r_reg__0 [2]),\n .I4(Q[0]),\n .I5(Q[1]),\n .O(sel));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAAAAA9)) \n \\maint_prescaler.maint_prescaler_r[5]_i_2 \n (.I0(\\maint_prescaler.maint_prescaler_r_reg__0 [5]),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(\\maint_prescaler.maint_prescaler_r_reg__0 [2]),\n .I4(\\maint_prescaler.maint_prescaler_r_reg__0 [3]),\n .I5(\\maint_prescaler.maint_prescaler_r_reg__0 [4]),\n .O(maint_prescaler_r0[5]));\n FDRE #(\n .INIT(1'b0)) \n \\maint_prescaler.maint_prescaler_r_reg[0] \n (.C(CLK),\n .CE(sel),\n .D(maint_prescaler_r0[0]),\n .Q(Q[0]),\n .R(SS));\n FDRE #(\n .INIT(1'b0)) \n \\maint_prescaler.maint_prescaler_r_reg[1] \n (.C(CLK),\n .CE(sel),\n .D(\\maint_prescaler.maint_prescaler_r_reg[0]_0 ),\n .Q(Q[1]),\n .R(SS));\n FDSE #(\n .INIT(1'b1)) \n \\maint_prescaler.maint_prescaler_r_reg[2] \n (.C(CLK),\n .CE(sel),\n .D(maint_prescaler_r0[2]),\n .Q(\\maint_prescaler.maint_prescaler_r_reg__0 [2]),\n .S(SS));\n FDSE #(\n .INIT(1'b1)) \n \\maint_prescaler.maint_prescaler_r_reg[3] \n (.C(CLK),\n .CE(sel),\n .D(maint_prescaler_r0[3]),\n .Q(\\maint_prescaler.maint_prescaler_r_reg__0 [3]),\n .S(SS));\n FDRE #(\n .INIT(1'b0)) \n \\maint_prescaler.maint_prescaler_r_reg[4] \n (.C(CLK),\n .CE(sel),\n .D(maint_prescaler_r0[4]),\n .Q(\\maint_prescaler.maint_prescaler_r_reg__0 [4]),\n .R(SS));\n FDSE #(\n .INIT(1'b1)) \n \\maint_prescaler.maint_prescaler_r_reg[5] \n (.C(CLK),\n .CE(sel),\n .D(maint_prescaler_r0[5]),\n .Q(\\maint_prescaler.maint_prescaler_r_reg__0 [5]),\n .S(SS));\n LUT6 #(\n .INIT(64'h0000000000010000)) \n \\maint_prescaler.maint_prescaler_tick_r_lcl_i_1 \n (.I0(\\maint_prescaler.maint_prescaler_r_reg__0 [5]),\n .I1(\\maint_prescaler.maint_prescaler_r_reg__0 [3]),\n .I2(\\maint_prescaler.maint_prescaler_r_reg__0 [4]),\n .I3(Q[1]),\n .I4(Q[0]),\n .I5(\\maint_prescaler.maint_prescaler_r_reg__0 [2]),\n .O(maint_prescaler_tick_ns));\n FDRE #(\n .INIT(1'b0)) \n \\maint_prescaler.maint_prescaler_tick_r_lcl_reg \n (.C(CLK),\n .CE(1'b1),\n .D(maint_prescaler_tick_ns),\n .Q(maint_prescaler_tick_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n maint_ref_zq_wip_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\refresh_generation.refresh_bank_r_reg[0]_1 ),\n .Q(maint_ref_zq_wip),\n .R(SR));\n ddr3_ifmig_7series_v4_0_round_robin_arb \\maintenance_request.maint_arb0 \n (.CLK(CLK),\n .D(D),\n .Q(\\maintenance_request.maint_sre_r_lcl_reg_1 ),\n .app_sr_req(app_sr_req),\n .ckesr_timer_r(ckesr_timer_r),\n .inhbt_srx(inhbt_srx),\n .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6_0),\n .\\last_master_r_reg[2]_0 (\\last_master_r_reg[2] ),\n .\\last_master_r_reg[2]_1 (\\last_master_r_reg[2]_0 ),\n .\\maintenance_request.maint_sre_r_lcl_reg (\\maintenance_request.maint_arb0_n_0 ),\n .\\maintenance_request.maint_sre_r_lcl_reg_0 (\\maintenance_request.maint_sre_r_lcl_reg_0 ),\n .\\maintenance_request.maint_srx_r_lcl_reg (\\maintenance_request.maint_arb0_n_4 ),\n .\\maintenance_request.maint_srx_r_lcl_reg_0 (\\maint_controller.maint_srx_r1_reg ),\n .\\maintenance_request.maint_zq_r_lcl_reg (\\maintenance_request.maint_arb0_n_8 ),\n .\\maintenance_request.maint_zq_r_lcl_reg_0 (\\maintenance_request.maint_zq_r_lcl_reg_0 ),\n .\\maintenance_request.new_maint_rank_r_reg (\\maintenance_request.maint_req_r_lcl_reg_0 ),\n .\\maintenance_request.upd_last_master_r_reg (\\maintenance_request.maint_srx_r_lcl_i_2_n_0 ),\n .\\maintenance_request.upd_last_master_r_reg_0 (\\maintenance_request.new_maint_rank_r_reg_0 ),\n .\\refresh_generation.refresh_bank_r_reg[0] (\\refresh_generation.refresh_bank_r_reg[0]_2 ),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .\\sr_cntrl.sre_request_logic.sre_request_r_reg (\\grant_r_reg[0]_0 ),\n .\\zq_cntrl.zq_request_logic.zq_request_r_reg (\\grant_r_reg[0] ));\n FDRE #(\n .INIT(1'b0)) \n \\maintenance_request.maint_req_r_lcl_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\maintenance_request.maint_req_r_lcl_reg_0 ),\n .Q(maint_req_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\maintenance_request.maint_sre_r_lcl_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\maintenance_request.maint_arb0_n_0 ),\n .Q(\\maintenance_request.maint_sre_r_lcl_reg_0 ),\n .R(SR));\n LUT2 #(\n .INIT(4'h2)) \n \\maintenance_request.maint_srx_r_lcl_i_2 \n (.I0(\\maintenance_request.new_maint_rank_r_reg_0 ),\n .I1(\\maintenance_request.maint_req_r_lcl_reg_0 ),\n .O(\\maintenance_request.maint_srx_r_lcl_i_2_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\maintenance_request.maint_srx_r_lcl_i_3 \n (.I0(ckesr_timer_r[0]),\n .I1(ckesr_timer_r[1]),\n .O(inhbt_srx));\n FDRE #(\n .INIT(1'b0)) \n \\maintenance_request.maint_srx_r_lcl_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\maintenance_request.maint_arb0_n_4 ),\n .Q(\\maint_controller.maint_srx_r1_reg ),\n .R(SR));\n FDRE #(\n .INIT(1'b0)) \n \\maintenance_request.maint_zq_r_lcl_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\maintenance_request.maint_arb0_n_8 ),\n .Q(\\maintenance_request.maint_zq_r_lcl_reg_0 ),\n .R(SR));\n FDRE #(\n .INIT(1'b0)) \n \\maintenance_request.new_maint_rank_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\maintenance_request.new_maint_rank_r_reg_0 ),\n .Q(\\maintenance_request.maint_req_r_lcl_reg_0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\maintenance_request.upd_last_master_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\maint_controller.maint_wip_r_lcl_reg ),\n .Q(\\maintenance_request.new_maint_rank_r_reg_0 ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\periodic_read_request.periodic_rd_grant_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\periodic_rd_generation.periodic_rd_request_r_reg ),\n .Q(periodic_rd_grant_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\periodic_read_request.periodic_rd_r_cnt_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\periodic_read_request.periodic_rd_r_lcl_reg_0 ),\n .Q(periodic_rd_r_cnt),\n .R(SR));\n FDRE #(\n .INIT(1'b0)) \n \\periodic_read_request.periodic_rd_r_lcl_reg \n (.C(CLK),\n .CE(1'b1),\n .D(periodic_rd_ack_r_lcl_reg),\n .Q(periodic_rd_r),\n .R(maint_prescaler_r1));\n LUT4 #(\n .INIT(16'h0008)) \n \\periodic_read_request.upd_last_master_r_i_1 \n (.I0(periodic_rd_request_r),\n .I1(init_calib_complete_reg_rep__6_0),\n .I2(\\periodic_read_request.upd_last_master_r_reg_0 ),\n .I3(periodic_rd_r),\n .O(upd_last_master_ns));\n FDRE #(\n .INIT(1'b0)) \n \\periodic_read_request.upd_last_master_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(upd_last_master_ns),\n .Q(\\periodic_read_request.upd_last_master_r_reg_0 ),\n .R(1'b0));\n LUT1 #(\n .INIT(2'h1)) \n \\refresh_timer.refresh_timer_r[0]_i_1 \n (.I0(\\refresh_timer.refresh_timer_r_reg[4]_0 [0]),\n .O(refresh_timer_r0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1078\" *) \n LUT3 #(\n .INIT(8'hA9)) \n \\refresh_timer.refresh_timer_r[2]_i_1 \n (.I0(\\refresh_timer.refresh_timer_r_reg__0 [2]),\n .I1(\\refresh_timer.refresh_timer_r_reg[4]_0 [1]),\n .I2(\\refresh_timer.refresh_timer_r_reg[4]_0 [0]),\n .O(refresh_timer_r0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1072\" *) \n LUT4 #(\n .INIT(16'hAAA9)) \n \\refresh_timer.refresh_timer_r[3]_i_1 \n (.I0(\\refresh_timer.refresh_timer_r_reg__0 [3]),\n .I1(\\refresh_timer.refresh_timer_r_reg__0 [2]),\n .I2(\\refresh_timer.refresh_timer_r_reg[4]_0 [0]),\n .I3(\\refresh_timer.refresh_timer_r_reg[4]_0 [1]),\n .O(refresh_timer_r0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1072\" *) \n LUT5 #(\n .INIT(32'hAAAAAAA9)) \n \\refresh_timer.refresh_timer_r[4]_i_1 \n (.I0(\\refresh_timer.refresh_timer_r_reg__0 [4]),\n .I1(\\refresh_timer.refresh_timer_r_reg__0 [3]),\n .I2(\\refresh_timer.refresh_timer_r_reg[4]_0 [1]),\n .I3(\\refresh_timer.refresh_timer_r_reg[4]_0 [0]),\n .I4(\\refresh_timer.refresh_timer_r_reg__0 [2]),\n .O(refresh_timer_r0[4]));\n LUT5 #(\n .INIT(32'hAAAAAA8A)) \n \\refresh_timer.refresh_timer_r[5]_i_1 \n (.I0(maint_prescaler_tick_r),\n .I1(\\refresh_timer.refresh_timer_r_reg__0 [5]),\n .I2(\\refresh_timer.refresh_timer_r[5]_i_3_n_0 ),\n .I3(\\refresh_timer.refresh_timer_r_reg__0 [4]),\n .I4(\\refresh_timer.refresh_timer_r_reg__0 [3]),\n .O(refresh_timer_r0_0));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAAAAA9)) \n \\refresh_timer.refresh_timer_r[5]_i_2 \n (.I0(\\refresh_timer.refresh_timer_r_reg__0 [5]),\n .I1(\\refresh_timer.refresh_timer_r_reg__0 [3]),\n .I2(\\refresh_timer.refresh_timer_r_reg__0 [4]),\n .I3(\\refresh_timer.refresh_timer_r_reg[4]_0 [1]),\n .I4(\\refresh_timer.refresh_timer_r_reg[4]_0 [0]),\n .I5(\\refresh_timer.refresh_timer_r_reg__0 [2]),\n .O(refresh_timer_r0[5]));\n (* SOFT_HLUTNM = \"soft_lutpair1078\" *) \n LUT3 #(\n .INIT(8'h01)) \n \\refresh_timer.refresh_timer_r[5]_i_3 \n (.I0(\\refresh_timer.refresh_timer_r_reg[4]_0 [1]),\n .I1(\\refresh_timer.refresh_timer_r_reg[4]_0 [0]),\n .I2(\\refresh_timer.refresh_timer_r_reg__0 [2]),\n .O(\\refresh_timer.refresh_timer_r[5]_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\refresh_timer.refresh_timer_r_reg[0] \n (.C(CLK),\n .CE(refresh_timer_r0_0),\n .D(refresh_timer_r0[0]),\n .Q(\\refresh_timer.refresh_timer_r_reg[4]_0 [0]),\n .R(init_calib_complete_reg_rep__6_1));\n FDSE #(\n .INIT(1'b1)) \n \\refresh_timer.refresh_timer_r_reg[1] \n (.C(CLK),\n .CE(refresh_timer_r0_0),\n .D(\\refresh_timer.refresh_timer_r_reg[0]_0 ),\n .Q(\\refresh_timer.refresh_timer_r_reg[4]_0 [1]),\n .S(init_calib_complete_reg_rep__6_1));\n FDSE #(\n .INIT(1'b1)) \n \\refresh_timer.refresh_timer_r_reg[2] \n (.C(CLK),\n .CE(refresh_timer_r0_0),\n .D(refresh_timer_r0[2]),\n .Q(\\refresh_timer.refresh_timer_r_reg__0 [2]),\n .S(init_calib_complete_reg_rep__6_1));\n FDRE #(\n .INIT(1'b0)) \n \\refresh_timer.refresh_timer_r_reg[3] \n (.C(CLK),\n .CE(refresh_timer_r0_0),\n .D(refresh_timer_r0[3]),\n .Q(\\refresh_timer.refresh_timer_r_reg__0 [3]),\n .R(init_calib_complete_reg_rep__6_1));\n FDRE #(\n .INIT(1'b0)) \n \\refresh_timer.refresh_timer_r_reg[4] \n (.C(CLK),\n .CE(refresh_timer_r0_0),\n .D(refresh_timer_r0[4]),\n .Q(\\refresh_timer.refresh_timer_r_reg__0 [4]),\n .R(init_calib_complete_reg_rep__6_1));\n FDSE #(\n .INIT(1'b1)) \n \\refresh_timer.refresh_timer_r_reg[5] \n (.C(CLK),\n .CE(refresh_timer_r0_0),\n .D(refresh_timer_r0[5]),\n .Q(\\refresh_timer.refresh_timer_r_reg__0 [5]),\n .S(init_calib_complete_reg_rep__6_1));\n LUT6 #(\n .INIT(64'h00000101000000FF)) \n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[0]_i_1 \n (.I0(\\maint_controller.maint_srx_r1_reg ),\n .I1(\\maintenance_request.maint_sre_r_lcl_reg_0 ),\n .I2(\\maintenance_request.maint_zq_r_lcl_reg_0 ),\n .I3(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ),\n .I4(rstdiv0_sync_r1_reg_rep__21),\n .I5(\\generate_maint_cmds.insert_maint_r_lcl_reg ),\n .O(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair1073\" *) \n LUT5 #(\n .INIT(32'h00000100)) \n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[5]_i_2 \n (.I0(\\maintenance_request.maint_zq_r_lcl_reg_0 ),\n .I1(\\maintenance_request.maint_sre_r_lcl_reg_0 ),\n .I2(\\maint_controller.maint_srx_r1_reg ),\n .I3(\\generate_maint_cmds.insert_maint_r_lcl_reg ),\n .I4(rstdiv0_sync_r1_reg_rep__21),\n .O(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] ));\n LUT6 #(\n .INIT(64'h5555555555555D55)) \n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_4 \n (.I0(E),\n .I1(\\generate_maint_cmds.insert_maint_r_lcl_reg ),\n .I2(rstdiv0_sync_r1_reg_rep__21),\n .I3(\\maint_controller.maint_srx_r1_reg ),\n .I4(\\maintenance_request.maint_zq_r_lcl_reg_0 ),\n .I5(\\maintenance_request.maint_sre_r_lcl_reg_0 ),\n .O(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ));\n (* SOFT_HLUTNM = \"soft_lutpair1076\" *) \n LUT4 #(\n .INIT(16'h0222)) \n \\sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1 \n (.I0(ckesr_timer_r[1]),\n .I1(ckesr_timer_r[0]),\n .I2(\\maintenance_request.maint_sre_r_lcl_reg_0 ),\n .I3(insert_maint_r1),\n .O(\\sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1076\" *) \n LUT4 #(\n .INIT(16'hF888)) \n \\sr_cntrl.ckesr_timer.ckesr_timer_r[1]_i_1 \n (.I0(ckesr_timer_r[1]),\n .I1(ckesr_timer_r[0]),\n .I2(\\maintenance_request.maint_sre_r_lcl_reg_0 ),\n .I3(insert_maint_r1),\n .O(\\sr_cntrl.ckesr_timer.ckesr_timer_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\sr_cntrl.ckesr_timer.ckesr_timer_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1_n_0 ),\n .Q(ckesr_timer_r[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\sr_cntrl.ckesr_timer.ckesr_timer_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\sr_cntrl.ckesr_timer.ckesr_timer_r[1]_i_1_n_0 ),\n .Q(ckesr_timer_r[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\sr_cntrl.sre_request_logic.sre_request_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(init_calib_complete_reg_rep__6),\n .Q(\\grant_r_reg[0]_0 ),\n .R(SR));\n FDRE #(\n .INIT(1'b0)) \n \\zq_cntrl.zq_request_logic.zq_request_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\zq_cntrl.zq_request_logic.zq_request_r_reg_0 ),\n .Q(\\grant_r_reg[0] ),\n .R(SR));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[0]_i_1 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg[0]_0 ),\n .O(zq_timer_r0));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[0]_i_10 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [1]),\n .O(S[1]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[0]_i_11 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [0]),\n .O(S[0]));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\zq_cntrl.zq_timer.zq_timer_r[0]_i_12 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [18]),\n .I1(\\zq_cntrl.zq_timer.zq_timer_r_reg [3]),\n .I2(\\zq_cntrl.zq_timer.zq_timer_r_reg [5]),\n .I3(\\zq_cntrl.zq_timer.zq_timer_r_reg [4]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_12_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAA8AAAAAAAA)) \n \\zq_cntrl.zq_timer.zq_timer_r[0]_i_2 \n (.I0(maint_prescaler_tick_r),\n .I1(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0 ),\n .I2(\\zq_cntrl.zq_timer.zq_timer_r_reg [0]),\n .I3(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_5_n_0 ),\n .I4(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_6_n_0 ),\n .I5(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_7_n_0 ),\n .O(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n \\zq_cntrl.zq_timer.zq_timer_r[0]_i_4 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [6]),\n .I1(\\zq_cntrl.zq_timer.zq_timer_r_reg [8]),\n .I2(\\zq_cntrl.zq_timer.zq_timer_r_reg [7]),\n .I3(\\zq_cntrl.zq_timer.zq_timer_r_reg [17]),\n .I4(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_12_n_0 ),\n .O(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1074\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\zq_cntrl.zq_timer.zq_timer_r[0]_i_5 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [2]),\n .I1(\\zq_cntrl.zq_timer.zq_timer_r_reg [9]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_5_n_0 ));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\zq_cntrl.zq_timer.zq_timer_r[0]_i_6 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [19]),\n .I1(\\zq_cntrl.zq_timer.zq_timer_r_reg [1]),\n .I2(\\zq_cntrl.zq_timer.zq_timer_r_reg [16]),\n .I3(\\zq_cntrl.zq_timer.zq_timer_r_reg [15]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_6_n_0 ));\n LUT5 #(\n .INIT(32'h00000001)) \n \\zq_cntrl.zq_timer.zq_timer_r[0]_i_7 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [13]),\n .I1(\\zq_cntrl.zq_timer.zq_timer_r_reg [10]),\n .I2(\\zq_cntrl.zq_timer.zq_timer_r_reg [11]),\n .I3(\\zq_cntrl.zq_timer.zq_timer_r_reg [12]),\n .I4(\\zq_cntrl.zq_timer.zq_timer_r_reg [14]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_7_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[0]_i_8 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [3]),\n .O(S[3]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[0]_i_9 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [2]),\n .O(S[2]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[12]_i_2 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [15]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 [3]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[12]_i_3 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [14]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 [2]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[12]_i_4 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [13]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 [1]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[12]_i_5 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [12]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 [0]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[16]_i_2 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [19]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 [3]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[16]_i_3 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [18]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 [2]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[16]_i_4 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [17]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 [1]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[16]_i_5 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [16]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 [0]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[4]_i_2 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [7]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 [3]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[4]_i_3 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [6]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 [2]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[4]_i_4 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [5]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 [1]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[4]_i_5 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [4]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 [0]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[8]_i_2 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [11]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 [3]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[8]_i_3 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [10]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 [2]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[8]_i_4 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [9]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 [1]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[8]_i_5 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [8]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 [0]));\n FDRE #(\n .INIT(1'b0)) \n \\zq_cntrl.zq_timer.zq_timer_r_reg[0] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(O[0]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [0]),\n .R(zq_timer_r0));\n FDSE #(\n .INIT(1'b1)) \n \\zq_cntrl.zq_timer.zq_timer_r_reg[10] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 [2]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [10]),\n .S(zq_timer_r0));\n FDRE #(\n .INIT(1'b0)) \n \\zq_cntrl.zq_timer.zq_timer_r_reg[11] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 [3]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [11]),\n .R(zq_timer_r0));\n FDRE #(\n .INIT(1'b0)) \n \\zq_cntrl.zq_timer.zq_timer_r_reg[12] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 [0]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [12]),\n .R(zq_timer_r0));\n FDRE #(\n .INIT(1'b0)) \n \\zq_cntrl.zq_timer.zq_timer_r_reg[13] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 [1]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [13]),\n .R(zq_timer_r0));\n FDSE #(\n .INIT(1'b1)) \n \\zq_cntrl.zq_timer.zq_timer_r_reg[14] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 [2]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [14]),\n .S(zq_timer_r0));\n FDSE #(\n .INIT(1'b1)) \n \\zq_cntrl.zq_timer.zq_timer_r_reg[15] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 [3]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [15]),\n .S(zq_timer_r0));\n FDSE #(\n .INIT(1'b1)) \n \\zq_cntrl.zq_timer.zq_timer_r_reg[16] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 [0]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [16]),\n .S(zq_timer_r0));\n FDRE #(\n .INIT(1'b0)) \n \\zq_cntrl.zq_timer.zq_timer_r_reg[17] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 [1]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [17]),\n .R(zq_timer_r0));\n FDRE #(\n .INIT(1'b0)) \n \\zq_cntrl.zq_timer.zq_timer_r_reg[18] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 [2]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [18]),\n .R(zq_timer_r0));\n FDSE #(\n .INIT(1'b1)) \n \\zq_cntrl.zq_timer.zq_timer_r_reg[19] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 [3]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [19]),\n .S(zq_timer_r0));\n FDRE #(\n .INIT(1'b0)) \n \\zq_cntrl.zq_timer.zq_timer_r_reg[1] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(O[1]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [1]),\n .R(zq_timer_r0));\n FDRE #(\n .INIT(1'b0)) \n \\zq_cntrl.zq_timer.zq_timer_r_reg[2] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(O[2]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [2]),\n .R(zq_timer_r0));\n FDRE #(\n .INIT(1'b0)) \n \\zq_cntrl.zq_timer.zq_timer_r_reg[3] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(O[3]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [3]),\n .R(zq_timer_r0));\n FDRE #(\n .INIT(1'b0)) \n \\zq_cntrl.zq_timer.zq_timer_r_reg[4] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 [0]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [4]),\n .R(zq_timer_r0));\n FDRE #(\n .INIT(1'b0)) \n \\zq_cntrl.zq_timer.zq_timer_r_reg[5] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 [1]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [5]),\n .R(zq_timer_r0));\n FDRE #(\n .INIT(1'b0)) \n \\zq_cntrl.zq_timer.zq_timer_r_reg[6] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 [2]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [6]),\n .R(zq_timer_r0));\n FDRE #(\n .INIT(1'b0)) \n \\zq_cntrl.zq_timer.zq_timer_r_reg[7] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 [3]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [7]),\n .R(zq_timer_r0));\n FDRE #(\n .INIT(1'b0)) \n \\zq_cntrl.zq_timer.zq_timer_r_reg[8] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 [0]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [8]),\n .R(zq_timer_r0));\n FDRE #(\n .INIT(1'b0)) \n \\zq_cntrl.zq_timer.zq_timer_r_reg[9] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 [1]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [9]),\n .R(zq_timer_r0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_rank_mach\" *) \nmodule ddr3_ifmig_7series_v4_0_rank_mach\n (act_delayed,\n maint_prescaler_tick_ns,\n upd_last_master_r,\n new_maint_rank_r,\n maint_req_r,\n \\periodic_read_request.upd_last_master_r_reg ,\n app_ref_ack,\n app_zq_ack,\n read_this_rank_r,\n inhbt_act_faw_r,\n maint_srx_r,\n maint_sre_r,\n zq_request_r,\n sre_request_r,\n maint_zq_r,\n periodic_rd_request_r,\n periodic_rd_r,\n app_ref_r,\n app_zq_r,\n periodic_rd_r_cnt,\n periodic_rd_grant_r,\n app_sr_active,\n maint_ref_zq_wip,\n periodic_rd_cntr1_r,\n refresh_bank_r,\n Q,\n \\refresh_timer.refresh_timer_r_reg[5] ,\n \\refresh_timer.refresh_timer_r_reg[4] ,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[0] ,\n \\maintenance_request.maint_sre_r_lcl_reg ,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ,\n \\last_master_r_reg[2] ,\n \\rtw_timer.rtw_cnt_r_reg[1] ,\n mc_cke_ns,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] ,\n \\refresh_generation.refresh_bank_r_reg[0] ,\n S,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[7] ,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[11] ,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[15] ,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[19] ,\n \\periodic_rd_generation.periodic_rd_request_r_reg ,\n \\inhbt_act_faw.inhbt_act_faw_r_reg ,\n granted_col_r_reg,\n act_this_rank,\n CLK,\n \\maint_controller.maint_wip_r_lcl_reg ,\n read_this_rank,\n SR,\n \\zq_cntrl.zq_request_logic.zq_request_r_reg ,\n init_calib_complete_reg_rep__6,\n periodic_rd_ack_r_lcl_reg,\n maint_prescaler_r1,\n periodic_rd_ack_r_lcl_reg_0,\n \\refresh_generation.refresh_bank_r_reg[0]_0 ,\n app_zq_r_reg,\n \\periodic_read_request.periodic_rd_r_lcl_reg ,\n \\periodic_rd_generation.periodic_rd_request_r_reg_0 ,\n \\maintenance_request.maint_sre_r_lcl_reg_0 ,\n \\refresh_generation.refresh_bank_r_reg[0]_1 ,\n \\periodic_read_request.periodic_rd_grant_r_reg[0] ,\n init_calib_complete_reg_rep__6_0,\n O,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ,\n init_calib_complete_reg_rep__6_1,\n app_sr_req,\n D,\n \\last_master_r_reg[2]_0 ,\n rstdiv0_sync_r1_reg_rep__20,\n \\grant_r_reg[0] ,\n rstdiv0_sync_r1_reg_rep__21,\n cke_r,\n insert_maint_r1,\n E,\n \\generate_maint_cmds.insert_maint_r_lcl_reg ,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ,\n \\grant_r_reg[1] ,\n \\wr_this_rank_r_reg[0] ,\n \\act_this_rank_r_reg[0] ,\n init_calib_complete_reg_rep__7,\n \\periodic_rd_generation.read_this_rank_r_reg ,\n \\inhbt_act_faw.faw_cnt_r_reg[1] ,\n SS,\n \\maint_prescaler.maint_prescaler_r_reg[0] ,\n init_calib_complete_reg_rep__6_2,\n \\refresh_timer.refresh_timer_r_reg[0] );\n output act_delayed;\n output maint_prescaler_tick_ns;\n output upd_last_master_r;\n output new_maint_rank_r;\n output maint_req_r;\n output \\periodic_read_request.upd_last_master_r_reg ;\n output app_ref_ack;\n output app_zq_ack;\n output read_this_rank_r;\n output inhbt_act_faw_r;\n output maint_srx_r;\n output maint_sre_r;\n output zq_request_r;\n output sre_request_r;\n output maint_zq_r;\n output periodic_rd_request_r;\n output periodic_rd_r;\n output app_ref_r;\n output app_zq_r;\n output periodic_rd_r_cnt;\n output periodic_rd_grant_r;\n output app_sr_active;\n output maint_ref_zq_wip;\n output periodic_rd_cntr1_r;\n output refresh_bank_r;\n output [1:0]Q;\n output \\refresh_timer.refresh_timer_r_reg[5] ;\n output [1:0]\\refresh_timer.refresh_timer_r_reg[4] ;\n output \\zq_cntrl.zq_timer.zq_timer_r_reg[0] ;\n output [2:0]\\maintenance_request.maint_sre_r_lcl_reg ;\n output \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ;\n output [2:0]\\last_master_r_reg[2] ;\n output [0:0]\\rtw_timer.rtw_cnt_r_reg[1] ;\n output [0:0]mc_cke_ns;\n output \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ;\n output [0:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ;\n output \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] ;\n output \\refresh_generation.refresh_bank_r_reg[0] ;\n output [3:0]S;\n output [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[7] ;\n output [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[11] ;\n output [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[15] ;\n output [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[19] ;\n output \\periodic_rd_generation.periodic_rd_request_r_reg ;\n output [2:0]\\inhbt_act_faw.inhbt_act_faw_r_reg ;\n output granted_col_r_reg;\n input act_this_rank;\n input CLK;\n input \\maint_controller.maint_wip_r_lcl_reg ;\n input read_this_rank;\n input [0:0]SR;\n input \\zq_cntrl.zq_request_logic.zq_request_r_reg ;\n input init_calib_complete_reg_rep__6;\n input periodic_rd_ack_r_lcl_reg;\n input maint_prescaler_r1;\n input periodic_rd_ack_r_lcl_reg_0;\n input \\refresh_generation.refresh_bank_r_reg[0]_0 ;\n input app_zq_r_reg;\n input \\periodic_read_request.periodic_rd_r_lcl_reg ;\n input \\periodic_rd_generation.periodic_rd_request_r_reg_0 ;\n input \\maintenance_request.maint_sre_r_lcl_reg_0 ;\n input \\refresh_generation.refresh_bank_r_reg[0]_1 ;\n input \\periodic_read_request.periodic_rd_grant_r_reg[0] ;\n input init_calib_complete_reg_rep__6_0;\n input [3:0]O;\n input [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ;\n input [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ;\n input [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ;\n input [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ;\n input init_calib_complete_reg_rep__6_1;\n input app_sr_req;\n input [1:0]D;\n input \\last_master_r_reg[2]_0 ;\n input rstdiv0_sync_r1_reg_rep__20;\n input \\grant_r_reg[0] ;\n input rstdiv0_sync_r1_reg_rep__21;\n input cke_r;\n input insert_maint_r1;\n input [0:0]E;\n input \\generate_maint_cmds.insert_maint_r_lcl_reg ;\n input [0:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ;\n input \\grant_r_reg[1] ;\n input \\wr_this_rank_r_reg[0] ;\n input \\act_this_rank_r_reg[0] ;\n input init_calib_complete_reg_rep__7;\n input \\periodic_rd_generation.read_this_rank_r_reg ;\n input [2:0]\\inhbt_act_faw.faw_cnt_r_reg[1] ;\n input [0:0]SS;\n input [0:0]\\maint_prescaler.maint_prescaler_r_reg[0] ;\n input [0:0]init_calib_complete_reg_rep__6_2;\n input [0:0]\\refresh_timer.refresh_timer_r_reg[0] ;\n\n wire CLK;\n wire [1:0]D;\n wire [0:0]E;\n wire [3:0]O;\n wire [1:0]Q;\n wire [3:0]S;\n wire [0:0]SR;\n wire [0:0]SS;\n wire act_delayed;\n wire act_this_rank;\n wire \\act_this_rank_r_reg[0] ;\n wire app_ref_ack;\n wire app_ref_r;\n wire app_sr_active;\n wire app_sr_req;\n wire app_zq_ack;\n wire app_zq_r;\n wire app_zq_r_reg;\n wire cke_r;\n wire \\generate_maint_cmds.insert_maint_r_lcl_reg ;\n wire \\grant_r_reg[0] ;\n wire \\grant_r_reg[1] ;\n wire granted_col_r_reg;\n wire [2:0]\\inhbt_act_faw.faw_cnt_r_reg[1] ;\n wire [2:0]\\inhbt_act_faw.inhbt_act_faw_r_reg ;\n wire inhbt_act_faw_r;\n wire init_calib_complete_reg_rep__6;\n wire init_calib_complete_reg_rep__6_0;\n wire init_calib_complete_reg_rep__6_1;\n wire [0:0]init_calib_complete_reg_rep__6_2;\n wire init_calib_complete_reg_rep__7;\n wire insert_maint_r1;\n wire [2:0]\\last_master_r_reg[2] ;\n wire \\last_master_r_reg[2]_0 ;\n wire \\maint_controller.maint_wip_r_lcl_reg ;\n wire [0:0]\\maint_prescaler.maint_prescaler_r_reg[0] ;\n wire maint_prescaler_r1;\n wire maint_prescaler_tick_ns;\n wire maint_prescaler_tick_r;\n wire maint_ref_zq_wip;\n wire maint_req_r;\n wire maint_sre_r;\n wire maint_srx_r;\n wire maint_zq_r;\n wire [2:0]\\maintenance_request.maint_sre_r_lcl_reg ;\n wire \\maintenance_request.maint_sre_r_lcl_reg_0 ;\n wire [0:0]mc_cke_ns;\n wire new_maint_rank_r;\n wire periodic_rd_ack_r_lcl_reg;\n wire periodic_rd_ack_r_lcl_reg_0;\n wire periodic_rd_cntr1_r;\n wire \\periodic_rd_generation.periodic_rd_request_r_reg ;\n wire \\periodic_rd_generation.periodic_rd_request_r_reg_0 ;\n wire \\periodic_rd_generation.read_this_rank_r_reg ;\n wire periodic_rd_grant_r;\n wire periodic_rd_r;\n wire periodic_rd_r_cnt;\n wire periodic_rd_request_r;\n wire \\periodic_read_request.periodic_rd_grant_r_reg[0] ;\n wire \\periodic_read_request.periodic_rd_r_lcl_reg ;\n wire \\periodic_read_request.upd_last_master_r_reg ;\n wire read_this_rank;\n wire read_this_rank_r;\n wire refresh_bank_r;\n wire \\refresh_generation.refresh_bank_r_reg[0] ;\n wire \\refresh_generation.refresh_bank_r_reg[0]_0 ;\n wire \\refresh_generation.refresh_bank_r_reg[0]_1 ;\n wire [0:0]\\refresh_timer.refresh_timer_r_reg[0] ;\n wire [1:0]\\refresh_timer.refresh_timer_r_reg[4] ;\n wire \\refresh_timer.refresh_timer_r_reg[5] ;\n wire [0:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ;\n wire [0:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ;\n wire \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ;\n wire \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] ;\n wire \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire [0:0]\\rtw_timer.rtw_cnt_r_reg[1] ;\n wire sre_request_r;\n wire upd_last_master_r;\n wire \\wr_this_rank_r_reg[0] ;\n wire \\zq_cntrl.zq_request_logic.zq_request_r_reg ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[0] ;\n wire [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[11] ;\n wire [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ;\n wire [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[15] ;\n wire [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ;\n wire [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[19] ;\n wire [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ;\n wire [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[7] ;\n wire [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ;\n wire zq_request_r;\n\n ddr3_ifmig_7series_v4_0_rank_cntrl \\rank_cntrl[0].rank_cntrl0 \n (.CLK(CLK),\n .SR(SR),\n .act_delayed(act_delayed),\n .act_this_rank(act_this_rank),\n .\\act_this_rank_r_reg[0] (\\act_this_rank_r_reg[0] ),\n .\\grant_r_reg[0] (refresh_bank_r),\n .\\grant_r_reg[0]_0 (\\grant_r_reg[0] ),\n .\\grant_r_reg[1] (\\grant_r_reg[1] ),\n .granted_col_r_reg(granted_col_r_reg),\n .\\inhbt_act_faw.faw_cnt_r_reg[1]_0 (\\inhbt_act_faw.faw_cnt_r_reg[1] ),\n .\\inhbt_act_faw.inhbt_act_faw_r_reg_0 (\\inhbt_act_faw.inhbt_act_faw_r_reg ),\n .inhbt_act_faw_r(inhbt_act_faw_r),\n .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6_0),\n .init_calib_complete_reg_rep__6_0(init_calib_complete_reg_rep__6_1),\n .init_calib_complete_reg_rep__7(init_calib_complete_reg_rep__7),\n .maint_prescaler_tick_r(maint_prescaler_tick_r),\n .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg),\n .periodic_rd_cntr1_r(periodic_rd_cntr1_r),\n .\\periodic_rd_generation.periodic_rd_request_r_reg_0 (\\periodic_rd_generation.periodic_rd_request_r_reg ),\n .\\periodic_rd_generation.read_this_rank_r_reg_0 (\\periodic_rd_generation.read_this_rank_r_reg ),\n .periodic_rd_request_r(periodic_rd_request_r),\n .\\periodic_read_request.periodic_rd_grant_r_reg[0] (\\periodic_read_request.periodic_rd_grant_r_reg[0] ),\n .read_this_rank(read_this_rank),\n .read_this_rank_r(read_this_rank_r),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .\\rtw_timer.rtw_cnt_r_reg[1]_0 (\\rtw_timer.rtw_cnt_r_reg[1] ),\n .\\wr_this_rank_r_reg[0] (\\wr_this_rank_r_reg[0] ));\n ddr3_ifmig_7series_v4_0_rank_common rank_common0\n (.CLK(CLK),\n .D(D),\n .E(E),\n .O(O),\n .Q(Q),\n .S(S),\n .SR(SR),\n .SS(SS),\n .app_ref_ack(app_ref_ack),\n .app_ref_r(app_ref_r),\n .app_sr_active(app_sr_active),\n .app_sr_req(app_sr_req),\n .app_zq_ack(app_zq_ack),\n .app_zq_r(app_zq_r),\n .app_zq_r_reg_0(app_zq_r_reg),\n .cke_r(cke_r),\n .\\generate_maint_cmds.insert_maint_r_lcl_reg (\\generate_maint_cmds.insert_maint_r_lcl_reg ),\n .\\grant_r_reg[0] (zq_request_r),\n .\\grant_r_reg[0]_0 (sre_request_r),\n .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6),\n .init_calib_complete_reg_rep__6_0(init_calib_complete_reg_rep__6_1),\n .init_calib_complete_reg_rep__6_1(init_calib_complete_reg_rep__6_2),\n .insert_maint_r1(insert_maint_r1),\n .\\last_master_r_reg[2] (\\last_master_r_reg[2] ),\n .\\last_master_r_reg[2]_0 (\\last_master_r_reg[2]_0 ),\n .\\maint_controller.maint_srx_r1_reg (maint_srx_r),\n .\\maint_controller.maint_wip_r_lcl_reg (\\maint_controller.maint_wip_r_lcl_reg ),\n .\\maint_prescaler.maint_prescaler_r_reg[0]_0 (\\maint_prescaler.maint_prescaler_r_reg[0] ),\n .maint_prescaler_r1(maint_prescaler_r1),\n .maint_prescaler_tick_ns(maint_prescaler_tick_ns),\n .maint_prescaler_tick_r(maint_prescaler_tick_r),\n .maint_ref_zq_wip(maint_ref_zq_wip),\n .maint_req_r(maint_req_r),\n .\\maintenance_request.maint_req_r_lcl_reg_0 (new_maint_rank_r),\n .\\maintenance_request.maint_sre_r_lcl_reg_0 (maint_sre_r),\n .\\maintenance_request.maint_sre_r_lcl_reg_1 (\\maintenance_request.maint_sre_r_lcl_reg ),\n .\\maintenance_request.maint_sre_r_lcl_reg_2 (\\maintenance_request.maint_sre_r_lcl_reg_0 ),\n .\\maintenance_request.maint_zq_r_lcl_reg_0 (maint_zq_r),\n .\\maintenance_request.new_maint_rank_r_reg_0 (upd_last_master_r),\n .mc_cke_ns(mc_cke_ns),\n .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg_0),\n .\\periodic_rd_generation.periodic_rd_request_r_reg (\\periodic_rd_generation.periodic_rd_request_r_reg_0 ),\n .periodic_rd_grant_r(periodic_rd_grant_r),\n .periodic_rd_r(periodic_rd_r),\n .periodic_rd_r_cnt(periodic_rd_r_cnt),\n .periodic_rd_request_r(periodic_rd_request_r),\n .\\periodic_read_request.periodic_rd_r_lcl_reg_0 (\\periodic_read_request.periodic_rd_r_lcl_reg ),\n .\\periodic_read_request.upd_last_master_r_reg_0 (\\periodic_read_request.upd_last_master_r_reg ),\n .\\refresh_generation.refresh_bank_r_reg[0] (\\refresh_generation.refresh_bank_r_reg[0] ),\n .\\refresh_generation.refresh_bank_r_reg[0]_0 (\\refresh_generation.refresh_bank_r_reg[0]_0 ),\n .\\refresh_generation.refresh_bank_r_reg[0]_1 (\\refresh_generation.refresh_bank_r_reg[0]_1 ),\n .\\refresh_generation.refresh_bank_r_reg[0]_2 (refresh_bank_r),\n .\\refresh_timer.refresh_timer_r_reg[0]_0 (\\refresh_timer.refresh_timer_r_reg[0] ),\n .\\refresh_timer.refresh_timer_r_reg[4]_0 (\\refresh_timer.refresh_timer_r_reg[4] ),\n .\\refresh_timer.refresh_timer_r_reg[5]_0 (\\refresh_timer.refresh_timer_r_reg[5] ),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] (\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 (\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] (\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] (\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] ),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] (\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .\\zq_cntrl.zq_request_logic.zq_request_r_reg_0 (\\zq_cntrl.zq_request_logic.zq_request_r_reg ),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[0]_0 (\\zq_cntrl.zq_timer.zq_timer_r_reg[0] ),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 (\\zq_cntrl.zq_timer.zq_timer_r_reg[11] ),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 (\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 (\\zq_cntrl.zq_timer.zq_timer_r_reg[15] ),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 (\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 (\\zq_cntrl.zq_timer.zq_timer_r_reg[19] ),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 (\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 (\\zq_cntrl.zq_timer.zq_timer_r_reg[7] ),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 (\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_round_robin_arb\" *) \nmodule ddr3_ifmig_7series_v4_0_round_robin_arb\n (\\maintenance_request.maint_sre_r_lcl_reg ,\n Q,\n \\maintenance_request.maint_srx_r_lcl_reg ,\n \\last_master_r_reg[2]_0 ,\n \\maintenance_request.maint_zq_r_lcl_reg ,\n \\maintenance_request.upd_last_master_r_reg ,\n \\maintenance_request.maint_sre_r_lcl_reg_0 ,\n ckesr_timer_r,\n app_sr_req,\n \\maintenance_request.maint_srx_r_lcl_reg_0 ,\n inhbt_srx,\n D,\n init_calib_complete_reg_rep__6,\n \\refresh_generation.refresh_bank_r_reg[0] ,\n \\sr_cntrl.sre_request_logic.sre_request_r_reg ,\n \\zq_cntrl.zq_request_logic.zq_request_r_reg ,\n \\last_master_r_reg[2]_1 ,\n \\maintenance_request.upd_last_master_r_reg_0 ,\n \\maintenance_request.new_maint_rank_r_reg ,\n rstdiv0_sync_r1_reg_rep__20,\n \\maintenance_request.maint_zq_r_lcl_reg_0 ,\n CLK);\n output \\maintenance_request.maint_sre_r_lcl_reg ;\n output [2:0]Q;\n output \\maintenance_request.maint_srx_r_lcl_reg ;\n output [2:0]\\last_master_r_reg[2]_0 ;\n output \\maintenance_request.maint_zq_r_lcl_reg ;\n input \\maintenance_request.upd_last_master_r_reg ;\n input \\maintenance_request.maint_sre_r_lcl_reg_0 ;\n input [1:0]ckesr_timer_r;\n input app_sr_req;\n input \\maintenance_request.maint_srx_r_lcl_reg_0 ;\n input inhbt_srx;\n input [1:0]D;\n input init_calib_complete_reg_rep__6;\n input \\refresh_generation.refresh_bank_r_reg[0] ;\n input \\sr_cntrl.sre_request_logic.sre_request_r_reg ;\n input \\zq_cntrl.zq_request_logic.zq_request_r_reg ;\n input \\last_master_r_reg[2]_1 ;\n input \\maintenance_request.upd_last_master_r_reg_0 ;\n input \\maintenance_request.new_maint_rank_r_reg ;\n input rstdiv0_sync_r1_reg_rep__20;\n input \\maintenance_request.maint_zq_r_lcl_reg_0 ;\n input CLK;\n\n wire CLK;\n wire [1:0]D;\n wire [2:0]Q;\n wire app_sr_req;\n wire [1:0]ckesr_timer_r;\n wire \\grant_r[0]_i_1_n_0 ;\n wire \\grant_r[1]_i_1_n_0 ;\n wire \\grant_r[2]_i_1_n_0 ;\n wire inhbt_srx;\n wire init_calib_complete_reg_rep__6;\n wire \\last_master_r[2]_i_1_n_0 ;\n wire [2:0]\\last_master_r_reg[2]_0 ;\n wire \\last_master_r_reg[2]_1 ;\n wire \\maintenance_request.maint_sre_r_lcl_reg ;\n wire \\maintenance_request.maint_sre_r_lcl_reg_0 ;\n wire \\maintenance_request.maint_srx_r_lcl_reg ;\n wire \\maintenance_request.maint_srx_r_lcl_reg_0 ;\n wire \\maintenance_request.maint_zq_r_lcl_reg ;\n wire \\maintenance_request.maint_zq_r_lcl_reg_0 ;\n wire \\maintenance_request.new_maint_rank_r_reg ;\n wire \\maintenance_request.upd_last_master_r_reg ;\n wire \\maintenance_request.upd_last_master_r_reg_0 ;\n wire \\refresh_generation.refresh_bank_r_reg[0] ;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire \\sr_cntrl.sre_request_logic.sre_request_r_reg ;\n wire \\zq_cntrl.zq_request_logic.zq_request_r_reg ;\n\n LUT6 #(\n .INIT(64'h0000000C040C040C)) \n \\grant_r[0]_i_1 \n (.I0(D[1]),\n .I1(init_calib_complete_reg_rep__6),\n .I2(\\refresh_generation.refresh_bank_r_reg[0] ),\n .I3(\\sr_cntrl.sre_request_logic.sre_request_r_reg ),\n .I4(\\zq_cntrl.zq_request_logic.zq_request_r_reg ),\n .I5(D[0]),\n .O(\\grant_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000A0808080A080)) \n \\grant_r[1]_i_1 \n (.I0(\\zq_cntrl.zq_request_logic.zq_request_r_reg ),\n .I1(\\refresh_generation.refresh_bank_r_reg[0] ),\n .I2(init_calib_complete_reg_rep__6),\n .I3(\\last_master_r_reg[2]_1 ),\n .I4(D[1]),\n .I5(\\sr_cntrl.sre_request_logic.sre_request_r_reg ),\n .O(\\grant_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0EAE000000000000)) \n \\grant_r[2]_i_1 \n (.I0(\\last_master_r_reg[2]_1 ),\n .I1(\\refresh_generation.refresh_bank_r_reg[0] ),\n .I2(\\zq_cntrl.zq_request_logic.zq_request_r_reg ),\n .I3(D[0]),\n .I4(init_calib_complete_reg_rep__6),\n .I5(\\sr_cntrl.sre_request_logic.sre_request_r_reg ),\n .O(\\grant_r[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\grant_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\grant_r[0]_i_1_n_0 ),\n .Q(Q[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\grant_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\grant_r[1]_i_1_n_0 ),\n .Q(Q[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\grant_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\grant_r[2]_i_1_n_0 ),\n .Q(Q[2]),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hFFFFFB08)) \n \\last_master_r[2]_i_1 \n (.I0(Q[2]),\n .I1(\\maintenance_request.upd_last_master_r_reg_0 ),\n .I2(\\maintenance_request.new_maint_rank_r_reg ),\n .I3(\\last_master_r_reg[2]_0 [2]),\n .I4(rstdiv0_sync_r1_reg_rep__20),\n .O(\\last_master_r[2]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\last_master_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(D[0]),\n .Q(\\last_master_r_reg[2]_0 [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\last_master_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(D[1]),\n .Q(\\last_master_r_reg[2]_0 [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\last_master_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\last_master_r[2]_i_1_n_0 ),\n .Q(\\last_master_r_reg[2]_0 [2]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hB8B8B8B8B8B8B888)) \n \\maintenance_request.maint_sre_r_lcl_i_1 \n (.I0(Q[2]),\n .I1(\\maintenance_request.upd_last_master_r_reg ),\n .I2(\\maintenance_request.maint_sre_r_lcl_reg_0 ),\n .I3(ckesr_timer_r[0]),\n .I4(ckesr_timer_r[1]),\n .I5(app_sr_req),\n .O(\\maintenance_request.maint_sre_r_lcl_reg ));\n LUT6 #(\n .INIT(64'h000000FFA2A2A2A2)) \n \\maintenance_request.maint_srx_r_lcl_i_1 \n (.I0(\\maintenance_request.maint_srx_r_lcl_reg_0 ),\n .I1(\\maintenance_request.upd_last_master_r_reg ),\n .I2(Q[2]),\n .I3(app_sr_req),\n .I4(inhbt_srx),\n .I5(\\maintenance_request.maint_sre_r_lcl_reg_0 ),\n .O(\\maintenance_request.maint_srx_r_lcl_reg ));\n LUT4 #(\n .INIT(16'hBA8A)) \n \\maintenance_request.maint_zq_r_lcl_i_1 \n (.I0(\\maintenance_request.maint_zq_r_lcl_reg_0 ),\n .I1(\\maintenance_request.new_maint_rank_r_reg ),\n .I2(\\maintenance_request.upd_last_master_r_reg_0 ),\n .I3(Q[1]),\n .O(\\maintenance_request.maint_zq_r_lcl_reg ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_round_robin_arb\" *) \nmodule ddr3_ifmig_7series_v4_0_round_robin_arb__parameterized1\n (Q,\n \\cmd_pipe_plus.mc_bank_reg[8] ,\n \\cmd_pipe_plus.mc_bank_reg[7] ,\n \\cmd_pipe_plus.mc_bank_reg[6] ,\n \\cmd_pipe_plus.mc_address_reg[44] ,\n \\cmd_pipe_plus.mc_address_reg[43] ,\n \\cmd_pipe_plus.mc_address_reg[42] ,\n \\cmd_pipe_plus.mc_address_reg[41] ,\n \\cmd_pipe_plus.mc_address_reg[39] ,\n \\cmd_pipe_plus.mc_address_reg[38] ,\n \\cmd_pipe_plus.mc_address_reg[37] ,\n \\cmd_pipe_plus.mc_address_reg[36] ,\n \\cmd_pipe_plus.mc_address_reg[35] ,\n \\cmd_pipe_plus.mc_address_reg[34] ,\n \\cmd_pipe_plus.mc_address_reg[33] ,\n \\cmd_pipe_plus.mc_address_reg[32] ,\n \\cmd_pipe_plus.mc_address_reg[31] ,\n \\cmd_pipe_plus.mc_address_reg[30] ,\n \\cmd_pipe_plus.mc_we_n_reg[2] ,\n \\cmd_pipe_plus.mc_cas_n_reg[2] ,\n auto_pre_r_lcl_reg,\n auto_pre_r_lcl_reg_0,\n rstdiv0_sync_r1_reg_rep__21,\n cs_en2,\n \\req_bank_r_lcl_reg[2] ,\n \\req_bank_r_lcl_reg[2]_0 ,\n req_row_r,\n row_cmd_wr,\n act_wait_r_lcl_reg,\n CLK);\n output [1:0]Q;\n output \\cmd_pipe_plus.mc_bank_reg[8] ;\n output \\cmd_pipe_plus.mc_bank_reg[7] ;\n output \\cmd_pipe_plus.mc_bank_reg[6] ;\n output \\cmd_pipe_plus.mc_address_reg[44] ;\n output \\cmd_pipe_plus.mc_address_reg[43] ;\n output \\cmd_pipe_plus.mc_address_reg[42] ;\n output \\cmd_pipe_plus.mc_address_reg[41] ;\n output \\cmd_pipe_plus.mc_address_reg[39] ;\n output \\cmd_pipe_plus.mc_address_reg[38] ;\n output \\cmd_pipe_plus.mc_address_reg[37] ;\n output \\cmd_pipe_plus.mc_address_reg[36] ;\n output \\cmd_pipe_plus.mc_address_reg[35] ;\n output \\cmd_pipe_plus.mc_address_reg[34] ;\n output \\cmd_pipe_plus.mc_address_reg[33] ;\n output \\cmd_pipe_plus.mc_address_reg[32] ;\n output \\cmd_pipe_plus.mc_address_reg[31] ;\n output \\cmd_pipe_plus.mc_address_reg[30] ;\n output \\cmd_pipe_plus.mc_we_n_reg[2] ;\n output \\cmd_pipe_plus.mc_cas_n_reg[2] ;\n input auto_pre_r_lcl_reg;\n input auto_pre_r_lcl_reg_0;\n input rstdiv0_sync_r1_reg_rep__21;\n input cs_en2;\n input [2:0]\\req_bank_r_lcl_reg[2] ;\n input [2:0]\\req_bank_r_lcl_reg[2]_0 ;\n input [27:0]req_row_r;\n input [0:0]row_cmd_wr;\n input act_wait_r_lcl_reg;\n input CLK;\n\n wire CLK;\n wire [1:0]Q;\n wire act_wait_r_lcl_reg;\n wire auto_pre_r_lcl_reg;\n wire auto_pre_r_lcl_reg_0;\n wire \\cmd_pipe_plus.mc_address_reg[30] ;\n wire \\cmd_pipe_plus.mc_address_reg[31] ;\n wire \\cmd_pipe_plus.mc_address_reg[32] ;\n wire \\cmd_pipe_plus.mc_address_reg[33] ;\n wire \\cmd_pipe_plus.mc_address_reg[34] ;\n wire \\cmd_pipe_plus.mc_address_reg[35] ;\n wire \\cmd_pipe_plus.mc_address_reg[36] ;\n wire \\cmd_pipe_plus.mc_address_reg[37] ;\n wire \\cmd_pipe_plus.mc_address_reg[38] ;\n wire \\cmd_pipe_plus.mc_address_reg[39] ;\n wire \\cmd_pipe_plus.mc_address_reg[41] ;\n wire \\cmd_pipe_plus.mc_address_reg[42] ;\n wire \\cmd_pipe_plus.mc_address_reg[43] ;\n wire \\cmd_pipe_plus.mc_address_reg[44] ;\n wire \\cmd_pipe_plus.mc_bank_reg[6] ;\n wire \\cmd_pipe_plus.mc_bank_reg[7] ;\n wire \\cmd_pipe_plus.mc_bank_reg[8] ;\n wire \\cmd_pipe_plus.mc_cas_n_reg[2] ;\n wire \\cmd_pipe_plus.mc_we_n_reg[2] ;\n wire cs_en2;\n wire \\grant_r[0]_i_1__1_n_0 ;\n wire \\grant_r[1]_i_1__1_n_0 ;\n wire [1:0]last_master_r;\n wire \\last_master_r[0]_i_1_n_0 ;\n wire \\last_master_r[1]_i_1_n_0 ;\n wire [2:0]\\req_bank_r_lcl_reg[2] ;\n wire [2:0]\\req_bank_r_lcl_reg[2]_0 ;\n wire [27:0]req_row_r;\n wire [0:0]row_cmd_wr;\n wire rstdiv0_sync_r1_reg_rep__21;\n\n LUT4 #(\n .INIT(16'hB888)) \n \\cmd_pipe_plus.mc_address[30]_i_1 \n (.I0(req_row_r[14]),\n .I1(Q[1]),\n .I2(req_row_r[0]),\n .I3(Q[0]),\n .O(\\cmd_pipe_plus.mc_address_reg[30] ));\n LUT4 #(\n .INIT(16'hB888)) \n \\cmd_pipe_plus.mc_address[31]_i_1 \n (.I0(req_row_r[15]),\n .I1(Q[1]),\n .I2(req_row_r[1]),\n .I3(Q[0]),\n .O(\\cmd_pipe_plus.mc_address_reg[31] ));\n LUT4 #(\n .INIT(16'hB888)) \n \\cmd_pipe_plus.mc_address[32]_i_1 \n (.I0(req_row_r[16]),\n .I1(Q[1]),\n .I2(req_row_r[2]),\n .I3(Q[0]),\n .O(\\cmd_pipe_plus.mc_address_reg[32] ));\n LUT4 #(\n .INIT(16'hB888)) \n \\cmd_pipe_plus.mc_address[33]_i_1 \n (.I0(req_row_r[17]),\n .I1(Q[1]),\n .I2(req_row_r[3]),\n .I3(Q[0]),\n .O(\\cmd_pipe_plus.mc_address_reg[33] ));\n LUT4 #(\n .INIT(16'hB888)) \n \\cmd_pipe_plus.mc_address[34]_i_1 \n (.I0(req_row_r[18]),\n .I1(Q[1]),\n .I2(req_row_r[4]),\n .I3(Q[0]),\n .O(\\cmd_pipe_plus.mc_address_reg[34] ));\n LUT4 #(\n .INIT(16'hB888)) \n \\cmd_pipe_plus.mc_address[35]_i_1 \n (.I0(req_row_r[19]),\n .I1(Q[1]),\n .I2(req_row_r[5]),\n .I3(Q[0]),\n .O(\\cmd_pipe_plus.mc_address_reg[35] ));\n LUT4 #(\n .INIT(16'hB888)) \n \\cmd_pipe_plus.mc_address[36]_i_1 \n (.I0(req_row_r[20]),\n .I1(Q[1]),\n .I2(req_row_r[6]),\n .I3(Q[0]),\n .O(\\cmd_pipe_plus.mc_address_reg[36] ));\n LUT4 #(\n .INIT(16'hB888)) \n \\cmd_pipe_plus.mc_address[37]_i_1 \n (.I0(req_row_r[21]),\n .I1(Q[1]),\n .I2(req_row_r[7]),\n .I3(Q[0]),\n .O(\\cmd_pipe_plus.mc_address_reg[37] ));\n LUT4 #(\n .INIT(16'hB888)) \n \\cmd_pipe_plus.mc_address[38]_i_1 \n (.I0(req_row_r[22]),\n .I1(Q[1]),\n .I2(req_row_r[8]),\n .I3(Q[0]),\n .O(\\cmd_pipe_plus.mc_address_reg[38] ));\n LUT4 #(\n .INIT(16'hB888)) \n \\cmd_pipe_plus.mc_address[39]_i_1 \n (.I0(req_row_r[23]),\n .I1(Q[1]),\n .I2(req_row_r[9]),\n .I3(Q[0]),\n .O(\\cmd_pipe_plus.mc_address_reg[39] ));\n LUT4 #(\n .INIT(16'hB888)) \n \\cmd_pipe_plus.mc_address[41]_i_1 \n (.I0(req_row_r[24]),\n .I1(Q[1]),\n .I2(req_row_r[10]),\n .I3(Q[0]),\n .O(\\cmd_pipe_plus.mc_address_reg[41] ));\n LUT4 #(\n .INIT(16'hB888)) \n \\cmd_pipe_plus.mc_address[42]_i_1 \n (.I0(req_row_r[25]),\n .I1(Q[1]),\n .I2(req_row_r[11]),\n .I3(Q[0]),\n .O(\\cmd_pipe_plus.mc_address_reg[42] ));\n LUT4 #(\n .INIT(16'hB888)) \n \\cmd_pipe_plus.mc_address[43]_i_1 \n (.I0(req_row_r[26]),\n .I1(Q[1]),\n .I2(req_row_r[12]),\n .I3(Q[0]),\n .O(\\cmd_pipe_plus.mc_address_reg[43] ));\n LUT4 #(\n .INIT(16'hB888)) \n \\cmd_pipe_plus.mc_address[44]_i_1 \n (.I0(req_row_r[27]),\n .I1(Q[1]),\n .I2(req_row_r[13]),\n .I3(Q[0]),\n .O(\\cmd_pipe_plus.mc_address_reg[44] ));\n LUT4 #(\n .INIT(16'hB888)) \n \\cmd_pipe_plus.mc_bank[6]_i_1 \n (.I0(\\req_bank_r_lcl_reg[2] [0]),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(\\req_bank_r_lcl_reg[2]_0 [0]),\n .O(\\cmd_pipe_plus.mc_bank_reg[6] ));\n LUT4 #(\n .INIT(16'hB888)) \n \\cmd_pipe_plus.mc_bank[7]_i_1 \n (.I0(\\req_bank_r_lcl_reg[2] [1]),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(\\req_bank_r_lcl_reg[2]_0 [1]),\n .O(\\cmd_pipe_plus.mc_bank_reg[7] ));\n LUT4 #(\n .INIT(16'hB888)) \n \\cmd_pipe_plus.mc_bank[8]_i_1 \n (.I0(\\req_bank_r_lcl_reg[2] [2]),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(\\req_bank_r_lcl_reg[2]_0 [2]),\n .O(\\cmd_pipe_plus.mc_bank_reg[8] ));\n (* SOFT_HLUTNM = \"soft_lutpair1045\" *) \n LUT3 #(\n .INIT(8'hFD)) \n \\cmd_pipe_plus.mc_cas_n[2]_i_1 \n (.I0(cs_en2),\n .I1(Q[0]),\n .I2(Q[1]),\n .O(\\cmd_pipe_plus.mc_cas_n_reg[2] ));\n LUT4 #(\n .INIT(16'hB888)) \n \\cmd_pipe_plus.mc_we_n[2]_i_2 \n (.I0(row_cmd_wr),\n .I1(Q[1]),\n .I2(act_wait_r_lcl_reg),\n .I3(Q[0]),\n .O(\\cmd_pipe_plus.mc_we_n_reg[2] ));\n LUT6 #(\n .INIT(64'hAAAAAAAA222AAA2A)) \n \\grant_r[0]_i_1__1 \n (.I0(auto_pre_r_lcl_reg_0),\n .I1(auto_pre_r_lcl_reg),\n .I2(last_master_r[0]),\n .I3(cs_en2),\n .I4(Q[0]),\n .I5(rstdiv0_sync_r1_reg_rep__21),\n .O(\\grant_r[0]_i_1__1_n_0 ));\n LUT6 #(\n .INIT(64'h2222222A2A2A222A)) \n \\grant_r[1]_i_1__1 \n (.I0(auto_pre_r_lcl_reg),\n .I1(auto_pre_r_lcl_reg_0),\n .I2(rstdiv0_sync_r1_reg_rep__21),\n .I3(last_master_r[1]),\n .I4(cs_en2),\n .I5(Q[1]),\n .O(\\grant_r[1]_i_1__1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\grant_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\grant_r[0]_i_1__1_n_0 ),\n .Q(Q[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\grant_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\grant_r[1]_i_1__1_n_0 ),\n .Q(Q[1]),\n .R(1'b0));\n LUT4 #(\n .INIT(16'h00E2)) \n \\last_master_r[0]_i_1 \n (.I0(last_master_r[0]),\n .I1(cs_en2),\n .I2(Q[0]),\n .I3(rstdiv0_sync_r1_reg_rep__21),\n .O(\\last_master_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1045\" *) \n LUT4 #(\n .INIT(16'hFEAE)) \n \\last_master_r[1]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__21),\n .I1(last_master_r[1]),\n .I2(cs_en2),\n .I3(Q[1]),\n .O(\\last_master_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\last_master_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\last_master_r[0]_i_1_n_0 ),\n .Q(last_master_r[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\last_master_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\last_master_r[1]_i_1_n_0 ),\n .Q(last_master_r[1]),\n .R(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_round_robin_arb\" *) \nmodule ddr3_ifmig_7series_v4_0_round_robin_arb__parameterized2\n (Q,\n mc_cas_n_ns,\n mc_ras_n_ns,\n D,\n \\cmd_pipe_plus.mc_bank_reg[2] ,\n \\cmd_pipe_plus.mc_address_reg[14] ,\n granted_row_r_reg,\n granted_row_r_reg_0,\n act_this_rank,\n \\inhbt_act_faw.inhbt_act_faw_r_reg ,\n \\cmd_pipe_plus.mc_address_reg[10] ,\n head_r_lcl_reg,\n head_r_lcl_reg_0,\n rstdiv0_sync_r1_reg_rep__21,\n sent_row,\n maint_zq_r,\n maint_srx_r,\n insert_maint_r1_lcl_reg,\n insert_maint_r1_lcl_reg_0,\n \\grant_r_reg[1]_0 ,\n row_cmd_wr,\n insert_maint_r1_lcl_reg_1,\n \\req_bank_r_lcl_reg[2] ,\n \\req_bank_r_lcl_reg[2]_0 ,\n req_row_r,\n act_wait_r_lcl_reg,\n \\generate_maint_cmds.insert_maint_r_lcl_reg ,\n inhbt_act_faw_r,\n act_this_rank_r,\n CLK);\n output [1:0]Q;\n output [0:0]mc_cas_n_ns;\n output [0:0]mc_ras_n_ns;\n output [0:0]D;\n output [2:0]\\cmd_pipe_plus.mc_bank_reg[2] ;\n output [13:0]\\cmd_pipe_plus.mc_address_reg[14] ;\n output granted_row_r_reg;\n output granted_row_r_reg_0;\n output act_this_rank;\n output \\inhbt_act_faw.inhbt_act_faw_r_reg ;\n output \\cmd_pipe_plus.mc_address_reg[10] ;\n input head_r_lcl_reg;\n input head_r_lcl_reg_0;\n input rstdiv0_sync_r1_reg_rep__21;\n input sent_row;\n input maint_zq_r;\n input maint_srx_r;\n input insert_maint_r1_lcl_reg;\n input insert_maint_r1_lcl_reg_0;\n input \\grant_r_reg[1]_0 ;\n input [0:0]row_cmd_wr;\n input insert_maint_r1_lcl_reg_1;\n input [2:0]\\req_bank_r_lcl_reg[2] ;\n input [2:0]\\req_bank_r_lcl_reg[2]_0 ;\n input [27:0]req_row_r;\n input act_wait_r_lcl_reg;\n input \\generate_maint_cmds.insert_maint_r_lcl_reg ;\n input inhbt_act_faw_r;\n input [1:0]act_this_rank_r;\n input CLK;\n\n wire CLK;\n wire [0:0]D;\n wire [1:0]Q;\n wire act_this_rank;\n wire [1:0]act_this_rank_r;\n wire act_wait_r_lcl_reg;\n wire \\cmd_pipe_plus.mc_address_reg[10] ;\n wire [13:0]\\cmd_pipe_plus.mc_address_reg[14] ;\n wire [2:0]\\cmd_pipe_plus.mc_bank_reg[2] ;\n wire \\generate_maint_cmds.insert_maint_r_lcl_reg ;\n wire \\grant_r[0]_i_1__2_n_0 ;\n wire \\grant_r[1]_i_1__2_n_0 ;\n wire \\grant_r_reg[1]_0 ;\n wire granted_row_r_reg;\n wire granted_row_r_reg_0;\n wire head_r_lcl_reg;\n wire head_r_lcl_reg_0;\n wire \\inhbt_act_faw.inhbt_act_faw_r_reg ;\n wire inhbt_act_faw_r;\n wire insert_maint_r1_lcl_reg;\n wire insert_maint_r1_lcl_reg_0;\n wire insert_maint_r1_lcl_reg_1;\n wire [1:0]last_master_r;\n wire \\last_master_r[0]_i_1__0_n_0 ;\n wire \\last_master_r[1]_i_1__0_n_0 ;\n wire maint_srx_r;\n wire maint_zq_r;\n wire [0:0]mc_cas_n_ns;\n wire [0:0]mc_ras_n_ns;\n wire [2:0]\\req_bank_r_lcl_reg[2] ;\n wire [2:0]\\req_bank_r_lcl_reg[2]_0 ;\n wire [27:0]req_row_r;\n wire [0:0]row_cmd_wr;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire sent_row;\n\n LUT6 #(\n .INIT(64'hF808F808F808FFFF)) \n \\cmd_pipe_plus.mc_address[0]_i_1 \n (.I0(Q[0]),\n .I1(req_row_r[0]),\n .I2(Q[1]),\n .I3(req_row_r[14]),\n .I4(insert_maint_r1_lcl_reg_1),\n .I5(sent_row),\n .O(\\cmd_pipe_plus.mc_address_reg[14] [0]));\n (* SOFT_HLUTNM = \"soft_lutpair1046\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\cmd_pipe_plus.mc_address[10]_i_2 \n (.I0(Q[0]),\n .I1(Q[1]),\n .O(\\cmd_pipe_plus.mc_address_reg[10] ));\n LUT6 #(\n .INIT(64'hF808F808F808FFFF)) \n \\cmd_pipe_plus.mc_address[11]_i_1 \n (.I0(Q[0]),\n .I1(req_row_r[10]),\n .I2(Q[1]),\n .I3(req_row_r[24]),\n .I4(insert_maint_r1_lcl_reg_1),\n .I5(sent_row),\n .O(\\cmd_pipe_plus.mc_address_reg[14] [10]));\n LUT6 #(\n .INIT(64'hF808F808F808FFFF)) \n \\cmd_pipe_plus.mc_address[12]_i_1 \n (.I0(Q[0]),\n .I1(req_row_r[11]),\n .I2(Q[1]),\n .I3(req_row_r[25]),\n .I4(insert_maint_r1_lcl_reg_1),\n .I5(sent_row),\n .O(\\cmd_pipe_plus.mc_address_reg[14] [11]));\n LUT6 #(\n .INIT(64'hF808F808F808FFFF)) \n \\cmd_pipe_plus.mc_address[13]_i_1 \n (.I0(Q[0]),\n .I1(req_row_r[12]),\n .I2(Q[1]),\n .I3(req_row_r[26]),\n .I4(insert_maint_r1_lcl_reg_1),\n .I5(sent_row),\n .O(\\cmd_pipe_plus.mc_address_reg[14] [12]));\n LUT6 #(\n .INIT(64'hF808F808F808FFFF)) \n \\cmd_pipe_plus.mc_address[14]_i_1 \n (.I0(Q[0]),\n .I1(req_row_r[13]),\n .I2(Q[1]),\n .I3(req_row_r[27]),\n .I4(insert_maint_r1_lcl_reg_1),\n .I5(sent_row),\n .O(\\cmd_pipe_plus.mc_address_reg[14] [13]));\n LUT6 #(\n .INIT(64'hF808F808F808FFFF)) \n \\cmd_pipe_plus.mc_address[1]_i_1 \n (.I0(Q[0]),\n .I1(req_row_r[1]),\n .I2(Q[1]),\n .I3(req_row_r[15]),\n .I4(insert_maint_r1_lcl_reg_1),\n .I5(sent_row),\n .O(\\cmd_pipe_plus.mc_address_reg[14] [1]));\n LUT6 #(\n .INIT(64'hF808F808F808FFFF)) \n \\cmd_pipe_plus.mc_address[2]_i_1 \n (.I0(Q[0]),\n .I1(req_row_r[2]),\n .I2(Q[1]),\n .I3(req_row_r[16]),\n .I4(insert_maint_r1_lcl_reg_1),\n .I5(sent_row),\n .O(\\cmd_pipe_plus.mc_address_reg[14] [2]));\n LUT6 #(\n .INIT(64'hF808F808F808FFFF)) \n \\cmd_pipe_plus.mc_address[3]_i_1 \n (.I0(Q[0]),\n .I1(req_row_r[3]),\n .I2(Q[1]),\n .I3(req_row_r[17]),\n .I4(insert_maint_r1_lcl_reg_1),\n .I5(sent_row),\n .O(\\cmd_pipe_plus.mc_address_reg[14] [3]));\n LUT6 #(\n .INIT(64'hF808F808F808FFFF)) \n \\cmd_pipe_plus.mc_address[4]_i_1 \n (.I0(Q[0]),\n .I1(req_row_r[4]),\n .I2(Q[1]),\n .I3(req_row_r[18]),\n .I4(insert_maint_r1_lcl_reg_1),\n .I5(sent_row),\n .O(\\cmd_pipe_plus.mc_address_reg[14] [4]));\n LUT6 #(\n .INIT(64'hF808F808F808FFFF)) \n \\cmd_pipe_plus.mc_address[5]_i_1 \n (.I0(Q[0]),\n .I1(req_row_r[5]),\n .I2(Q[1]),\n .I3(req_row_r[19]),\n .I4(insert_maint_r1_lcl_reg_1),\n .I5(sent_row),\n .O(\\cmd_pipe_plus.mc_address_reg[14] [5]));\n LUT6 #(\n .INIT(64'hF808F808F808FFFF)) \n \\cmd_pipe_plus.mc_address[6]_i_1 \n (.I0(Q[0]),\n .I1(req_row_r[6]),\n .I2(Q[1]),\n .I3(req_row_r[20]),\n .I4(insert_maint_r1_lcl_reg_1),\n .I5(sent_row),\n .O(\\cmd_pipe_plus.mc_address_reg[14] [6]));\n LUT6 #(\n .INIT(64'hF808F808F808FFFF)) \n \\cmd_pipe_plus.mc_address[7]_i_1 \n (.I0(Q[0]),\n .I1(req_row_r[7]),\n .I2(Q[1]),\n .I3(req_row_r[21]),\n .I4(insert_maint_r1_lcl_reg_1),\n .I5(sent_row),\n .O(\\cmd_pipe_plus.mc_address_reg[14] [7]));\n LUT6 #(\n .INIT(64'hF808F808F808FFFF)) \n \\cmd_pipe_plus.mc_address[8]_i_1 \n (.I0(Q[0]),\n .I1(req_row_r[8]),\n .I2(Q[1]),\n .I3(req_row_r[22]),\n .I4(insert_maint_r1_lcl_reg_1),\n .I5(sent_row),\n .O(\\cmd_pipe_plus.mc_address_reg[14] [8]));\n LUT6 #(\n .INIT(64'hF808F808F808FFFF)) \n \\cmd_pipe_plus.mc_address[9]_i_1 \n (.I0(Q[0]),\n .I1(req_row_r[9]),\n .I2(Q[1]),\n .I3(req_row_r[23]),\n .I4(insert_maint_r1_lcl_reg_1),\n .I5(sent_row),\n .O(\\cmd_pipe_plus.mc_address_reg[14] [9]));\n LUT6 #(\n .INIT(64'hF808F808F808FFFF)) \n \\cmd_pipe_plus.mc_bank[0]_i_1 \n (.I0(Q[0]),\n .I1(\\req_bank_r_lcl_reg[2] [0]),\n .I2(Q[1]),\n .I3(\\req_bank_r_lcl_reg[2]_0 [0]),\n .I4(insert_maint_r1_lcl_reg_1),\n .I5(sent_row),\n .O(\\cmd_pipe_plus.mc_bank_reg[2] [0]));\n LUT6 #(\n .INIT(64'hF808F808F808FFFF)) \n \\cmd_pipe_plus.mc_bank[1]_i_1 \n (.I0(Q[0]),\n .I1(\\req_bank_r_lcl_reg[2] [1]),\n .I2(Q[1]),\n .I3(\\req_bank_r_lcl_reg[2]_0 [1]),\n .I4(insert_maint_r1_lcl_reg_1),\n .I5(sent_row),\n .O(\\cmd_pipe_plus.mc_bank_reg[2] [1]));\n LUT6 #(\n .INIT(64'hF808F808F808FFFF)) \n \\cmd_pipe_plus.mc_bank[2]_i_1 \n (.I0(Q[0]),\n .I1(\\req_bank_r_lcl_reg[2] [2]),\n .I2(Q[1]),\n .I3(\\req_bank_r_lcl_reg[2]_0 [2]),\n .I4(insert_maint_r1_lcl_reg_1),\n .I5(sent_row),\n .O(\\cmd_pipe_plus.mc_bank_reg[2] [2]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFE0)) \n \\cmd_pipe_plus.mc_cas_n[0]_i_1 \n (.I0(maint_zq_r),\n .I1(maint_srx_r),\n .I2(insert_maint_r1_lcl_reg),\n .I3(Q[0]),\n .I4(Q[1]),\n .I5(insert_maint_r1_lcl_reg_0),\n .O(mc_cas_n_ns));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAAFEAA)) \n \\cmd_pipe_plus.mc_ras_n[0]_i_1 \n (.I0(insert_maint_r1_lcl_reg_0),\n .I1(maint_zq_r),\n .I2(maint_srx_r),\n .I3(insert_maint_r1_lcl_reg),\n .I4(Q[1]),\n .I5(Q[0]),\n .O(mc_ras_n_ns));\n LUT5 #(\n .INIT(32'hEAEAEAFF)) \n \\cmd_pipe_plus.mc_we_n[0]_i_1 \n (.I0(\\grant_r_reg[1]_0 ),\n .I1(row_cmd_wr),\n .I2(Q[1]),\n .I3(insert_maint_r1_lcl_reg_1),\n .I4(sent_row),\n .O(D));\n LUT6 #(\n .INIT(64'hAAAAAAAA222AAA2A)) \n \\grant_r[0]_i_1__2 \n (.I0(head_r_lcl_reg_0),\n .I1(head_r_lcl_reg),\n .I2(last_master_r[0]),\n .I3(sent_row),\n .I4(Q[0]),\n .I5(rstdiv0_sync_r1_reg_rep__21),\n .O(\\grant_r[0]_i_1__2_n_0 ));\n LUT6 #(\n .INIT(64'h2222222A2A2A222A)) \n \\grant_r[1]_i_1__2 \n (.I0(head_r_lcl_reg),\n .I1(head_r_lcl_reg_0),\n .I2(rstdiv0_sync_r1_reg_rep__21),\n .I3(last_master_r[1]),\n .I4(sent_row),\n .I5(Q[1]),\n .O(\\grant_r[1]_i_1__2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFFFF8)) \n \\grant_r[1]_i_4 \n (.I0(Q[0]),\n .I1(act_wait_r_lcl_reg),\n .I2(\\generate_maint_cmds.insert_maint_r_lcl_reg ),\n .I3(inhbt_act_faw_r),\n .I4(Q[1]),\n .O(granted_row_r_reg));\n (* SOFT_HLUTNM = \"soft_lutpair1046\" *) \n LUT5 #(\n .INIT(32'hFFFFFFF8)) \n \\grant_r[1]_i_5__0 \n (.I0(Q[1]),\n .I1(row_cmd_wr),\n .I2(\\generate_maint_cmds.insert_maint_r_lcl_reg ),\n .I3(inhbt_act_faw_r),\n .I4(Q[0]),\n .O(granted_row_r_reg_0));\n FDRE #(\n .INIT(1'b0)) \n \\grant_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\grant_r[0]_i_1__2_n_0 ),\n .Q(Q[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\grant_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\grant_r[1]_i_1__2_n_0 ),\n .Q(Q[1]),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1047\" *) \n LUT4 #(\n .INIT(16'h0777)) \n i___50_i_1\n (.I0(act_this_rank_r[1]),\n .I1(Q[1]),\n .I2(act_this_rank_r[0]),\n .I3(Q[0]),\n .O(\\inhbt_act_faw.inhbt_act_faw_r_reg ));\n (* SOFT_HLUTNM = \"soft_lutpair1047\" *) \n LUT4 #(\n .INIT(16'hF888)) \n \\inhbt_act_faw.SRLC32E0_i_1 \n (.I0(Q[0]),\n .I1(act_this_rank_r[0]),\n .I2(Q[1]),\n .I3(act_this_rank_r[1]),\n .O(act_this_rank));\n LUT4 #(\n .INIT(16'h00E2)) \n \\last_master_r[0]_i_1__0 \n (.I0(last_master_r[0]),\n .I1(sent_row),\n .I2(Q[0]),\n .I3(rstdiv0_sync_r1_reg_rep__21),\n .O(\\last_master_r[0]_i_1__0_n_0 ));\n LUT4 #(\n .INIT(16'hFEAE)) \n \\last_master_r[1]_i_1__0 \n (.I0(rstdiv0_sync_r1_reg_rep__21),\n .I1(last_master_r[1]),\n .I2(sent_row),\n .I3(Q[1]),\n .O(\\last_master_r[1]_i_1__0_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\last_master_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\last_master_r[0]_i_1__0_n_0 ),\n .Q(last_master_r[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\last_master_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\last_master_r[1]_i_1__0_n_0 ),\n .Q(last_master_r[1]),\n .R(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_round_robin_arb\" *) \nmodule ddr3_ifmig_7series_v4_0_round_robin_arb__parameterized4\n (\\periodic_rd_generation.periodic_rd_timer_r_reg[0] ,\n Q,\n read_this_rank,\n D,\n granted_col_r_reg,\n \\rtw_timer.rtw_cnt_r_reg[1] ,\n mc_odt_ns,\n col_rd_wr,\n mc_data_offset_2_ns,\n granted_col_r_reg_0,\n granted_col_r_reg_1,\n \\wtr_timer.wtr_cnt_r_reg[2] ,\n col_data_buf_addr,\n DIC,\n demand_priority_r_reg,\n \\cmd_pipe_plus.mc_bank_reg[5] ,\n demand_priority_r_reg_0,\n \\cmd_pipe_plus.mc_address_reg[25] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[0] ,\n read_this_rank_r,\n rd_this_rank_r,\n granted_col_r_reg_2,\n rd_wr_r_lcl_reg,\n rd_wr_r_lcl_reg_0,\n col_wait_r_reg,\n col_wait_r_reg_0,\n rstdiv0_sync_r1_reg_rep__20,\n rstdiv0_sync_r1_reg_rep__21,\n \\rtw_timer.rtw_cnt_r_reg[1]_0 ,\n \\cmd_pipe_plus.mc_data_offset_2_reg[3] ,\n col_rd_wr_r1,\n rnk_config_strobe,\n \\genblk3[2].rnk_config_strobe_r_reg ,\n \\genblk3[1].rnk_config_strobe_r_reg ,\n ofs_rdy_r,\n ofs_rdy_r_0,\n wr_this_rank_r,\n req_data_buf_addr_r,\n col_data_buf_addr_r,\n \\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ,\n req_periodic_rd_r,\n col_periodic_rd_r,\n req_bank_rdy_r,\n \\req_bank_r_lcl_reg[2] ,\n \\req_bank_r_lcl_reg[2]_0 ,\n req_bank_rdy_r_1,\n \\req_col_r_reg[9] ,\n \\req_col_r_reg[9]_0 ,\n auto_pre_r_lcl_reg,\n auto_pre_r_lcl_reg_0,\n CLK);\n output \\periodic_rd_generation.periodic_rd_timer_r_reg[0] ;\n output [1:0]Q;\n output read_this_rank;\n output [0:0]D;\n output granted_col_r_reg;\n output \\rtw_timer.rtw_cnt_r_reg[1] ;\n output [0:0]mc_odt_ns;\n output col_rd_wr;\n output [0:0]mc_data_offset_2_ns;\n output granted_col_r_reg_0;\n output granted_col_r_reg_1;\n output \\wtr_timer.wtr_cnt_r_reg[2] ;\n output [4:0]col_data_buf_addr;\n output [0:0]DIC;\n output demand_priority_r_reg;\n output [2:0]\\cmd_pipe_plus.mc_bank_reg[5] ;\n output demand_priority_r_reg_0;\n output [7:0]\\cmd_pipe_plus.mc_address_reg[25] ;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[0] ;\n input read_this_rank_r;\n input [1:0]rd_this_rank_r;\n input granted_col_r_reg_2;\n input rd_wr_r_lcl_reg;\n input rd_wr_r_lcl_reg_0;\n input col_wait_r_reg;\n input col_wait_r_reg_0;\n input rstdiv0_sync_r1_reg_rep__20;\n input rstdiv0_sync_r1_reg_rep__21;\n input [0:0]\\rtw_timer.rtw_cnt_r_reg[1]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_2_reg[3] ;\n input col_rd_wr_r1;\n input rnk_config_strobe;\n input \\genblk3[2].rnk_config_strobe_r_reg ;\n input \\genblk3[1].rnk_config_strobe_r_reg ;\n input ofs_rdy_r;\n input ofs_rdy_r_0;\n input [1:0]wr_this_rank_r;\n input [9:0]req_data_buf_addr_r;\n input [0:0]col_data_buf_addr_r;\n input [3:0]\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ;\n input [1:0]req_periodic_rd_r;\n input col_periodic_rd_r;\n input req_bank_rdy_r;\n input [2:0]\\req_bank_r_lcl_reg[2] ;\n input [2:0]\\req_bank_r_lcl_reg[2]_0 ;\n input req_bank_rdy_r_1;\n input [6:0]\\req_col_r_reg[9] ;\n input [6:0]\\req_col_r_reg[9]_0 ;\n input auto_pre_r_lcl_reg;\n input auto_pre_r_lcl_reg_0;\n input CLK;\n\n wire CLK;\n wire [0:0]D;\n wire [0:0]DIC;\n wire [1:0]Q;\n wire auto_pre_r_lcl_reg;\n wire auto_pre_r_lcl_reg_0;\n wire [7:0]\\cmd_pipe_plus.mc_address_reg[25] ;\n wire [2:0]\\cmd_pipe_plus.mc_bank_reg[5] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[0] ;\n wire \\cmd_pipe_plus.mc_data_offset_2_reg[3] ;\n wire [4:0]col_data_buf_addr;\n wire [0:0]col_data_buf_addr_r;\n wire col_periodic_rd_r;\n wire col_rd_wr;\n wire col_rd_wr_r1;\n wire col_wait_r_reg;\n wire col_wait_r_reg_0;\n wire [3:0]\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ;\n wire demand_priority_r_reg;\n wire demand_priority_r_reg_0;\n wire \\genblk3[1].rnk_config_strobe_r_reg ;\n wire \\genblk3[2].rnk_config_strobe_r_reg ;\n wire \\grant_r[0]_i_1__0_n_0 ;\n wire \\grant_r[1]_i_1__0_n_0 ;\n wire granted_col_r_reg;\n wire granted_col_r_reg_0;\n wire granted_col_r_reg_1;\n wire granted_col_r_reg_2;\n wire [1:0]last_master_r;\n wire \\last_master_r[0]_i_1__1_n_0 ;\n wire \\last_master_r[1]_i_1__1_n_0 ;\n wire [0:0]mc_data_offset_2_ns;\n wire [0:0]mc_odt_ns;\n wire ofs_rdy_r;\n wire ofs_rdy_r_0;\n wire \\periodic_rd_generation.periodic_rd_timer_r_reg[0] ;\n wire [1:0]rd_this_rank_r;\n wire rd_wr_r_lcl_reg;\n wire rd_wr_r_lcl_reg_0;\n wire read_this_rank;\n wire read_this_rank_r;\n wire [2:0]\\req_bank_r_lcl_reg[2] ;\n wire [2:0]\\req_bank_r_lcl_reg[2]_0 ;\n wire req_bank_rdy_r;\n wire req_bank_rdy_r_1;\n wire [6:0]\\req_col_r_reg[9] ;\n wire [6:0]\\req_col_r_reg[9]_0 ;\n wire [9:0]req_data_buf_addr_r;\n wire [1:0]req_periodic_rd_r;\n wire rnk_config_strobe;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire \\rtw_timer.rtw_cnt_r_reg[1] ;\n wire [0:0]\\rtw_timer.rtw_cnt_r_reg[1]_0 ;\n wire [1:0]wr_this_rank_r;\n wire \\wtr_timer.wtr_cnt_r_reg[2] ;\n\n LUT5 #(\n .INIT(32'hFF8F0F8F)) \n \\cmd_pipe_plus.mc_address[18]_i_1 \n (.I0(Q[0]),\n .I1(\\req_col_r_reg[9] [0]),\n .I2(granted_col_r_reg_2),\n .I3(Q[1]),\n .I4(\\req_col_r_reg[9]_0 [0]),\n .O(\\cmd_pipe_plus.mc_address_reg[25] [0]));\n LUT5 #(\n .INIT(32'hFF8F0F8F)) \n \\cmd_pipe_plus.mc_address[19]_i_1 \n (.I0(Q[0]),\n .I1(\\req_col_r_reg[9] [1]),\n .I2(granted_col_r_reg_2),\n .I3(Q[1]),\n .I4(\\req_col_r_reg[9]_0 [1]),\n .O(\\cmd_pipe_plus.mc_address_reg[25] [1]));\n LUT5 #(\n .INIT(32'hFF8F0F8F)) \n \\cmd_pipe_plus.mc_address[20]_i_1 \n (.I0(Q[0]),\n .I1(\\req_col_r_reg[9] [2]),\n .I2(granted_col_r_reg_2),\n .I3(Q[1]),\n .I4(\\req_col_r_reg[9]_0 [2]),\n .O(\\cmd_pipe_plus.mc_address_reg[25] [2]));\n LUT5 #(\n .INIT(32'hFF8F0F8F)) \n \\cmd_pipe_plus.mc_address[21]_i_1 \n (.I0(Q[0]),\n .I1(\\req_col_r_reg[9] [3]),\n .I2(granted_col_r_reg_2),\n .I3(Q[1]),\n .I4(\\req_col_r_reg[9]_0 [3]),\n .O(\\cmd_pipe_plus.mc_address_reg[25] [3]));\n LUT5 #(\n .INIT(32'hFF8F0F8F)) \n \\cmd_pipe_plus.mc_address[22]_i_1 \n (.I0(Q[0]),\n .I1(\\req_col_r_reg[9] [4]),\n .I2(granted_col_r_reg_2),\n .I3(Q[1]),\n .I4(\\req_col_r_reg[9]_0 [4]),\n .O(\\cmd_pipe_plus.mc_address_reg[25] [4]));\n LUT5 #(\n .INIT(32'hFF8F0F8F)) \n \\cmd_pipe_plus.mc_address[23]_i_1 \n (.I0(Q[0]),\n .I1(\\req_col_r_reg[9] [5]),\n .I2(granted_col_r_reg_2),\n .I3(Q[1]),\n .I4(\\req_col_r_reg[9]_0 [5]),\n .O(\\cmd_pipe_plus.mc_address_reg[25] [5]));\n LUT5 #(\n .INIT(32'hFF8F0F8F)) \n \\cmd_pipe_plus.mc_address[24]_i_1 \n (.I0(Q[0]),\n .I1(\\req_col_r_reg[9] [6]),\n .I2(granted_col_r_reg_2),\n .I3(Q[1]),\n .I4(\\req_col_r_reg[9]_0 [6]),\n .O(\\cmd_pipe_plus.mc_address_reg[25] [6]));\n LUT5 #(\n .INIT(32'hFF8F0F8F)) \n \\cmd_pipe_plus.mc_address[25]_i_1 \n (.I0(Q[0]),\n .I1(auto_pre_r_lcl_reg),\n .I2(granted_col_r_reg_2),\n .I3(Q[1]),\n .I4(auto_pre_r_lcl_reg_0),\n .O(\\cmd_pipe_plus.mc_address_reg[25] [7]));\n LUT5 #(\n .INIT(32'hFF0F8F8F)) \n \\cmd_pipe_plus.mc_bank[3]_i_1 \n (.I0(Q[0]),\n .I1(\\req_bank_r_lcl_reg[2] [0]),\n .I2(granted_col_r_reg_2),\n .I3(\\req_bank_r_lcl_reg[2]_0 [0]),\n .I4(Q[1]),\n .O(\\cmd_pipe_plus.mc_bank_reg[5] [0]));\n LUT5 #(\n .INIT(32'hFF0F8F8F)) \n \\cmd_pipe_plus.mc_bank[4]_i_1 \n (.I0(Q[0]),\n .I1(\\req_bank_r_lcl_reg[2] [1]),\n .I2(granted_col_r_reg_2),\n .I3(\\req_bank_r_lcl_reg[2]_0 [1]),\n .I4(Q[1]),\n .O(\\cmd_pipe_plus.mc_bank_reg[5] [1]));\n LUT5 #(\n .INIT(32'hFF0F8F8F)) \n \\cmd_pipe_plus.mc_bank[5]_i_1 \n (.I0(Q[0]),\n .I1(\\req_bank_r_lcl_reg[2] [2]),\n .I2(granted_col_r_reg_2),\n .I3(\\req_bank_r_lcl_reg[2]_0 [2]),\n .I4(Q[1]),\n .O(\\cmd_pipe_plus.mc_bank_reg[5] [2]));\n LUT6 #(\n .INIT(64'h77775F5577775FFF)) \n \\cmd_pipe_plus.mc_data_offset[5]_i_1 \n (.I0(granted_col_r_reg_2),\n .I1(rd_wr_r_lcl_reg),\n .I2(rd_wr_r_lcl_reg_0),\n .I3(Q[0]),\n .I4(Q[1]),\n .I5(col_rd_wr_r1),\n .O(\\cmd_pipe_plus.mc_data_offset_1_reg[0] ));\n LUT6 #(\n .INIT(64'h00020A02A0A2AAA2)) \n \\cmd_pipe_plus.mc_data_offset_2[3]_i_1 \n (.I0(granted_col_r_reg_2),\n .I1(col_rd_wr_r1),\n .I2(Q[1]),\n .I3(Q[0]),\n .I4(rd_wr_r_lcl_reg_0),\n .I5(rd_wr_r_lcl_reg),\n .O(mc_data_offset_2_ns));\n LUT3 #(\n .INIT(8'hBA)) \n \\cmd_pipe_plus.mc_odt[0]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_2_reg[3] ),\n .I1(col_rd_wr),\n .I2(granted_col_r_reg_2),\n .O(mc_odt_ns));\n LUT5 #(\n .INIT(32'hDFD5D5D5)) \n \\cmd_pipe_plus.mc_we_n[1]_i_1 \n (.I0(granted_col_r_reg_2),\n .I1(rd_wr_r_lcl_reg),\n .I2(Q[1]),\n .I3(rd_wr_r_lcl_reg_0),\n .I4(Q[0]),\n .O(D));\n (* SOFT_HLUTNM = \"soft_lutpair1043\" *) \n LUT3 #(\n .INIT(8'h08)) \n demand_priority_r_i_5\n (.I0(req_bank_rdy_r),\n .I1(granted_col_r_reg_2),\n .I2(Q[0]),\n .O(demand_priority_r_reg));\n (* SOFT_HLUTNM = \"soft_lutpair1044\" *) \n LUT3 #(\n .INIT(8'h08)) \n demand_priority_r_i_5__0\n (.I0(req_bank_rdy_r_1),\n .I1(granted_col_r_reg_2),\n .I2(Q[1]),\n .O(demand_priority_r_reg_0));\n LUT6 #(\n .INIT(64'hAAAAAAAA222AAA2A)) \n \\grant_r[0]_i_1__0 \n (.I0(col_wait_r_reg),\n .I1(col_wait_r_reg_0),\n .I2(last_master_r[0]),\n .I3(granted_col_r_reg_2),\n .I4(Q[0]),\n .I5(rstdiv0_sync_r1_reg_rep__20),\n .O(\\grant_r[0]_i_1__0_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFFEFF)) \n \\grant_r[1]_i_11 \n (.I0(rnk_config_strobe),\n .I1(\\genblk3[2].rnk_config_strobe_r_reg ),\n .I2(\\genblk3[1].rnk_config_strobe_r_reg ),\n .I3(ofs_rdy_r_0),\n .I4(Q[0]),\n .O(granted_col_r_reg_1));\n LUT6 #(\n .INIT(64'h2222222A2A2A222A)) \n \\grant_r[1]_i_1__0 \n (.I0(col_wait_r_reg_0),\n .I1(col_wait_r_reg),\n .I2(rstdiv0_sync_r1_reg_rep__21),\n .I3(last_master_r[1]),\n .I4(granted_col_r_reg_2),\n .I5(Q[1]),\n .O(\\grant_r[1]_i_1__0_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF0000FFFF07F7)) \n \\grant_r[1]_i_6 \n (.I0(Q[0]),\n .I1(rd_wr_r_lcl_reg_0),\n .I2(Q[1]),\n .I3(rd_wr_r_lcl_reg),\n .I4(rstdiv0_sync_r1_reg_rep__21),\n .I5(\\rtw_timer.rtw_cnt_r_reg[1]_0 ),\n .O(granted_col_r_reg));\n LUT5 #(\n .INIT(32'hFFFFFEFF)) \n \\grant_r[1]_i_9 \n (.I0(rnk_config_strobe),\n .I1(\\genblk3[2].rnk_config_strobe_r_reg ),\n .I2(\\genblk3[1].rnk_config_strobe_r_reg ),\n .I3(ofs_rdy_r),\n .I4(Q[1]),\n .O(granted_col_r_reg_0));\n FDRE #(\n .INIT(1'b0)) \n \\grant_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\grant_r[0]_i_1__0_n_0 ),\n .Q(Q[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\grant_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\grant_r[1]_i_1__0_n_0 ),\n .Q(Q[1]),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1042\" *) \n LUT5 #(\n .INIT(32'hAA808080)) \n i___25_i_1\n (.I0(read_this_rank_r),\n .I1(Q[0]),\n .I2(rd_this_rank_r[0]),\n .I3(Q[1]),\n .I4(rd_this_rank_r[1]),\n .O(\\periodic_rd_generation.periodic_rd_timer_r_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair1043\" *) \n LUT4 #(\n .INIT(16'h00E2)) \n \\last_master_r[0]_i_1__1 \n (.I0(last_master_r[0]),\n .I1(granted_col_r_reg_2),\n .I2(Q[0]),\n .I3(rstdiv0_sync_r1_reg_rep__21),\n .O(\\last_master_r[0]_i_1__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1044\" *) \n LUT4 #(\n .INIT(16'hFEAE)) \n \\last_master_r[1]_i_1__1 \n (.I0(rstdiv0_sync_r1_reg_rep__21),\n .I1(last_master_r[1]),\n .I2(granted_col_r_reg_2),\n .I3(Q[1]),\n .O(\\last_master_r[1]_i_1__1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\last_master_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\last_master_r[0]_i_1__1_n_0 ),\n .Q(last_master_r[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\last_master_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\last_master_r[1]_i_1__1_n_0 ),\n .Q(last_master_r[1]),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1041\" *) \n LUT5 #(\n .INIT(32'hAACFAAC0)) \n \\offset_pipe_0.col_rd_wr_r1_i_1 \n (.I0(rd_wr_r_lcl_reg),\n .I1(rd_wr_r_lcl_reg_0),\n .I2(Q[0]),\n .I3(Q[1]),\n .I4(col_rd_wr_r1),\n .O(col_rd_wr));\n (* SOFT_HLUTNM = \"soft_lutpair1042\" *) \n LUT4 #(\n .INIT(16'hF888)) \n \\periodic_rd_generation.read_this_rank_r_i_1 \n (.I0(Q[0]),\n .I1(rd_this_rank_r[0]),\n .I2(Q[1]),\n .I3(rd_this_rank_r[1]),\n .O(read_this_rank));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\read_fifo.fifo_ram[0].RAM32M0_i_1 \n (.I0(req_data_buf_addr_r[9]),\n .I1(Q[1]),\n .I2(req_data_buf_addr_r[4]),\n .I3(Q[0]),\n .I4(col_data_buf_addr_r),\n .O(col_data_buf_addr[4]));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\read_fifo.fifo_ram[0].RAM32M0_i_2 \n (.I0(req_data_buf_addr_r[8]),\n .I1(Q[1]),\n .I2(req_data_buf_addr_r[3]),\n .I3(Q[0]),\n .I4(\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] [3]),\n .O(col_data_buf_addr[3]));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\read_fifo.fifo_ram[0].RAM32M0_i_3 \n (.I0(req_data_buf_addr_r[7]),\n .I1(Q[1]),\n .I2(req_data_buf_addr_r[2]),\n .I3(Q[0]),\n .I4(\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] [2]),\n .O(col_data_buf_addr[2]));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\read_fifo.fifo_ram[0].RAM32M0_i_4 \n (.I0(req_data_buf_addr_r[6]),\n .I1(Q[1]),\n .I2(req_data_buf_addr_r[1]),\n .I3(Q[0]),\n .I4(\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] [1]),\n .O(col_data_buf_addr[1]));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\read_fifo.fifo_ram[0].RAM32M0_i_5 \n (.I0(req_data_buf_addr_r[5]),\n .I1(Q[1]),\n .I2(req_data_buf_addr_r[0]),\n .I3(Q[0]),\n .I4(\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] [0]),\n .O(col_data_buf_addr[0]));\n LUT6 #(\n .INIT(64'hB888B888B8BBB888)) \n \\read_fifo.fifo_ram[1].RAM32M0_i_1 \n (.I0(req_periodic_rd_r[1]),\n .I1(Q[1]),\n .I2(req_periodic_rd_r[0]),\n .I3(Q[0]),\n .I4(col_periodic_rd_r),\n .I5(rstdiv0_sync_r1_reg_rep__21),\n .O(DIC));\n (* SOFT_HLUTNM = \"soft_lutpair1041\" *) \n LUT4 #(\n .INIT(16'h07F7)) \n \\rtw_timer.rtw_cnt_r[1]_i_2 \n (.I0(Q[0]),\n .I1(rd_wr_r_lcl_reg_0),\n .I2(Q[1]),\n .I3(rd_wr_r_lcl_reg),\n .O(\\rtw_timer.rtw_cnt_r_reg[1] ));\n LUT4 #(\n .INIT(16'hF888)) \n \\wtr_timer.wtr_cnt_r[2]_i_2 \n (.I0(wr_this_rank_r[0]),\n .I1(Q[0]),\n .I2(wr_this_rank_r[1]),\n .I3(Q[1]),\n .O(\\wtr_timer.wtr_cnt_r_reg[2] ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_tempmon\" *) \nmodule ddr3_ifmig_7series_v4_0_tempmon\n (out,\n D,\n mmcm_clk,\n in0,\n CLK);\n output [11:0]out;\n output [11:0]D;\n input mmcm_clk;\n input in0;\n input CLK;\n\n wire CLK;\n wire [11:0]D;\n wire \\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 ;\n (* RTL_KEEP = \"yes\" *) wire \\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ;\n (* RTL_KEEP = \"yes\" *) wire \\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[1] ;\n (* RTL_KEEP = \"yes\" *) wire \\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2] ;\n wire \\device_temp_101[11]_i_4_n_0 ;\n wire \\device_temp_101[11]_i_5_n_0 ;\n wire \\device_temp_101[11]_i_6_n_0 ;\n wire \\device_temp_101[11]_i_7_n_0 ;\n wire \\device_temp_101[11]_i_8_n_0 ;\n wire [11:0]device_temp_lcl;\n (* async_reg = \"true\" *) wire [11:0]device_temp_r;\n wire \\device_temp_r[11]_i_1_n_0 ;\n (* async_reg = \"true\" *) wire [11:0]device_temp_sync_r1;\n (* async_reg = \"true\" *) wire [11:0]device_temp_sync_r2;\n (* async_reg = \"true\" *) (* syn_srlstyle = \"registers\" *) wire [11:0]device_temp_sync_r3;\n (* async_reg = \"true\" *) wire [11:0]device_temp_sync_r4;\n wire device_temp_sync_r4_neq_r3;\n wire device_temp_sync_r4_neq_r3_i_2_n_0;\n wire device_temp_sync_r4_neq_r3_i_3_n_0;\n wire device_temp_sync_r4_neq_r3_i_4_n_0;\n wire device_temp_sync_r4_neq_r3_i_5_n_0;\n wire device_temp_sync_r4_neq_r3_reg_i_1_n_0;\n wire device_temp_sync_r4_neq_r3_reg_i_1_n_1;\n wire device_temp_sync_r4_neq_r3_reg_i_1_n_2;\n wire device_temp_sync_r4_neq_r3_reg_i_1_n_3;\n (* async_reg = \"true\" *) wire [11:0]device_temp_sync_r5;\n wire in0;\n wire mmcm_clk;\n wire [11:0]p_0_in;\n wire [10:1]p_0_in__0;\n wire [1:0]p_0_in__1;\n (* async_reg = \"true\" *) wire rst_r1;\n (* async_reg = \"true\" *) wire rst_r2;\n wire sample_en;\n wire sample_en0;\n wire sample_timer0;\n wire sample_timer_en;\n wire sync_cntr0;\n wire \\sync_cntr[2]_i_1_n_0 ;\n wire \\sync_cntr[3]_i_2_n_0 ;\n wire \\sync_cntr[3]_i_3_n_0 ;\n wire [3:0]sync_cntr_reg__0;\n (* RTL_KEEP = \"yes\" *) wire temperature;\n wire \\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ;\n wire \\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ;\n wire xadc_den;\n wire [15:0]xadc_do;\n wire xadc_drdy;\n wire xadc_drdy_r;\n wire \\xadc_supplied_temperature.sample_en_i_2_n_0 ;\n wire \\xadc_supplied_temperature.sample_timer[0]_i_1_n_0 ;\n wire \\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ;\n wire \\xadc_supplied_temperature.sample_timer_clr_i_1_n_0 ;\n wire \\xadc_supplied_temperature.sample_timer_en_i_1_n_0 ;\n wire [10:0]\\xadc_supplied_temperature.sample_timer_reg__0 ;\n wire [3:0]NLW_device_temp_sync_r4_neq_r3_reg_i_1_O_UNCONNECTED;\n wire \\NLW_xadc_supplied_temperature.XADC_inst_BUSY_UNCONNECTED ;\n wire \\NLW_xadc_supplied_temperature.XADC_inst_EOC_UNCONNECTED ;\n wire \\NLW_xadc_supplied_temperature.XADC_inst_EOS_UNCONNECTED ;\n wire \\NLW_xadc_supplied_temperature.XADC_inst_JTAGBUSY_UNCONNECTED ;\n wire \\NLW_xadc_supplied_temperature.XADC_inst_JTAGLOCKED_UNCONNECTED ;\n wire \\NLW_xadc_supplied_temperature.XADC_inst_JTAGMODIFIED_UNCONNECTED ;\n wire \\NLW_xadc_supplied_temperature.XADC_inst_OT_UNCONNECTED ;\n wire [7:0]\\NLW_xadc_supplied_temperature.XADC_inst_ALM_UNCONNECTED ;\n wire [4:0]\\NLW_xadc_supplied_temperature.XADC_inst_CHANNEL_UNCONNECTED ;\n wire [4:0]\\NLW_xadc_supplied_temperature.XADC_inst_MUXADDR_UNCONNECTED ;\n\n assign out[11:0] = device_temp_r;\n LUT6 #(\n .INIT(64'hFFFFFEEEFEEEFEEE)) \n \\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1 \n (.I0(\\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[1] ),\n .I1(temperature),\n .I2(\\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ),\n .I3(sample_en),\n .I4(\\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2] ),\n .I5(xadc_drdy_r),\n .O(\\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 ));\n (* KEEP = \"yes\" *) \n FDSE #(\n .INIT(1'b1)) \n \\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[0] \n (.C(mmcm_clk),\n .CE(\\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 ),\n .D(temperature),\n .Q(\\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ),\n .S(rst_r2));\n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[1] \n (.C(mmcm_clk),\n .CE(\\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 ),\n .D(\\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ),\n .Q(\\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[1] ),\n .R(rst_r2));\n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[2] \n (.C(mmcm_clk),\n .CE(\\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 ),\n .D(\\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[1] ),\n .Q(\\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2] ),\n .R(rst_r2));\n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[3] \n (.C(mmcm_clk),\n .CE(\\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 ),\n .D(\\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2] ),\n .Q(temperature),\n .R(rst_r2));\n LUT3 #(\n .INIT(8'h10)) \n \\device_temp_101[0]_i_1 \n (.I0(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),\n .I1(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),\n .I2(device_temp_r[0]),\n .O(D[0]));\n LUT3 #(\n .INIT(8'hBA)) \n \\device_temp_101[10]_i_1 \n (.I0(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),\n .I1(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),\n .I2(device_temp_r[10]),\n .O(D[10]));\n LUT3 #(\n .INIT(8'hFE)) \n \\device_temp_101[11]_i_1 \n (.I0(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),\n .I1(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),\n .I2(device_temp_r[11]),\n .O(D[11]));\n LUT6 #(\n .INIT(64'h0000000011111115)) \n \\device_temp_101[11]_i_2 \n (.I0(\\device_temp_101[11]_i_4_n_0 ),\n .I1(device_temp_r[11]),\n .I2(device_temp_r[8]),\n .I3(device_temp_r[10]),\n .I4(device_temp_r[9]),\n .I5(\\device_temp_101[11]_i_5_n_0 ),\n .O(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ));\n LUT5 #(\n .INIT(32'h0000FD55)) \n \\device_temp_101[11]_i_3 \n (.I0(\\device_temp_101[11]_i_6_n_0 ),\n .I1(device_temp_r[1]),\n .I2(device_temp_r[0]),\n .I3(device_temp_r[2]),\n .I4(\\device_temp_101[11]_i_7_n_0 ),\n .O(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ));\n LUT4 #(\n .INIT(16'h8000)) \n \\device_temp_101[11]_i_4 \n (.I0(device_temp_r[4]),\n .I1(device_temp_r[11]),\n .I2(device_temp_r[7]),\n .I3(device_temp_r[5]),\n .O(\\device_temp_101[11]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hE000A000A000A000)) \n \\device_temp_101[11]_i_5 \n (.I0(device_temp_r[6]),\n .I1(device_temp_r[5]),\n .I2(device_temp_r[7]),\n .I3(device_temp_r[11]),\n .I4(device_temp_r[2]),\n .I5(device_temp_r[3]),\n .O(\\device_temp_101[11]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'h00000001)) \n \\device_temp_101[11]_i_6 \n (.I0(device_temp_r[6]),\n .I1(device_temp_r[9]),\n .I2(device_temp_r[8]),\n .I3(device_temp_r[4]),\n .I4(device_temp_r[3]),\n .O(\\device_temp_101[11]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h7F777F777F77FF77)) \n \\device_temp_101[11]_i_7 \n (.I0(device_temp_r[11]),\n .I1(device_temp_r[10]),\n .I2(device_temp_r[7]),\n .I3(\\device_temp_101[11]_i_8_n_0 ),\n .I4(device_temp_r[6]),\n .I5(device_temp_r[5]),\n .O(\\device_temp_101[11]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h1)) \n \\device_temp_101[11]_i_8 \n (.I0(device_temp_r[9]),\n .I1(device_temp_r[8]),\n .O(\\device_temp_101[11]_i_8_n_0 ));\n LUT3 #(\n .INIT(8'h10)) \n \\device_temp_101[1]_i_1 \n (.I0(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),\n .I1(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),\n .I2(device_temp_r[1]),\n .O(D[1]));\n LUT3 #(\n .INIT(8'hFE)) \n \\device_temp_101[2]_i_1 \n (.I0(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),\n .I1(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),\n .I2(device_temp_r[2]),\n .O(D[2]));\n LUT3 #(\n .INIT(8'hDC)) \n \\device_temp_101[3]_i_1 \n (.I0(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),\n .I1(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),\n .I2(device_temp_r[3]),\n .O(D[3]));\n LUT3 #(\n .INIT(8'h10)) \n \\device_temp_101[4]_i_1 \n (.I0(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),\n .I1(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),\n .I2(device_temp_r[4]),\n .O(D[4]));\n LUT3 #(\n .INIT(8'hFE)) \n \\device_temp_101[5]_i_1 \n (.I0(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),\n .I1(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),\n .I2(device_temp_r[5]),\n .O(D[5]));\n LUT3 #(\n .INIT(8'h10)) \n \\device_temp_101[6]_i_1 \n (.I0(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),\n .I1(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),\n .I2(device_temp_r[6]),\n .O(D[6]));\n LUT3 #(\n .INIT(8'hFE)) \n \\device_temp_101[7]_i_1 \n (.I0(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),\n .I1(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),\n .I2(device_temp_r[7]),\n .O(D[7]));\n LUT3 #(\n .INIT(8'h10)) \n \\device_temp_101[8]_i_1 \n (.I0(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),\n .I1(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),\n .I2(device_temp_r[8]),\n .O(D[8]));\n LUT3 #(\n .INIT(8'h10)) \n \\device_temp_101[9]_i_1 \n (.I0(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),\n .I1(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),\n .I2(device_temp_r[9]),\n .O(D[9]));\n LUT4 #(\n .INIT(16'h8000)) \n \\device_temp_r[11]_i_1 \n (.I0(sync_cntr_reg__0[3]),\n .I1(sync_cntr_reg__0[2]),\n .I2(sync_cntr_reg__0[0]),\n .I3(sync_cntr_reg__0[1]),\n .O(\\device_temp_r[11]_i_1_n_0 ));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_r_reg[0] \n (.C(CLK),\n .CE(\\device_temp_r[11]_i_1_n_0 ),\n .D(device_temp_sync_r5[0]),\n .Q(device_temp_r[0]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_r_reg[10] \n (.C(CLK),\n .CE(\\device_temp_r[11]_i_1_n_0 ),\n .D(device_temp_sync_r5[10]),\n .Q(device_temp_r[10]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_r_reg[11] \n (.C(CLK),\n .CE(\\device_temp_r[11]_i_1_n_0 ),\n .D(device_temp_sync_r5[11]),\n .Q(device_temp_r[11]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_r_reg[1] \n (.C(CLK),\n .CE(\\device_temp_r[11]_i_1_n_0 ),\n .D(device_temp_sync_r5[1]),\n .Q(device_temp_r[1]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_r_reg[2] \n (.C(CLK),\n .CE(\\device_temp_r[11]_i_1_n_0 ),\n .D(device_temp_sync_r5[2]),\n .Q(device_temp_r[2]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_r_reg[3] \n (.C(CLK),\n .CE(\\device_temp_r[11]_i_1_n_0 ),\n .D(device_temp_sync_r5[3]),\n .Q(device_temp_r[3]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_r_reg[4] \n (.C(CLK),\n .CE(\\device_temp_r[11]_i_1_n_0 ),\n .D(device_temp_sync_r5[4]),\n .Q(device_temp_r[4]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_r_reg[5] \n (.C(CLK),\n .CE(\\device_temp_r[11]_i_1_n_0 ),\n .D(device_temp_sync_r5[5]),\n .Q(device_temp_r[5]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_r_reg[6] \n (.C(CLK),\n .CE(\\device_temp_r[11]_i_1_n_0 ),\n .D(device_temp_sync_r5[6]),\n .Q(device_temp_r[6]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_r_reg[7] \n (.C(CLK),\n .CE(\\device_temp_r[11]_i_1_n_0 ),\n .D(device_temp_sync_r5[7]),\n .Q(device_temp_r[7]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_r_reg[8] \n (.C(CLK),\n .CE(\\device_temp_r[11]_i_1_n_0 ),\n .D(device_temp_sync_r5[8]),\n .Q(device_temp_r[8]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_r_reg[9] \n (.C(CLK),\n .CE(\\device_temp_r[11]_i_1_n_0 ),\n .D(device_temp_sync_r5[9]),\n .Q(device_temp_r[9]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_lcl[0]),\n .Q(device_temp_sync_r1[0]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r1_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_lcl[10]),\n .Q(device_temp_sync_r1[10]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r1_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_lcl[11]),\n .Q(device_temp_sync_r1[11]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_lcl[1]),\n .Q(device_temp_sync_r1[1]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_lcl[2]),\n .Q(device_temp_sync_r1[2]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_lcl[3]),\n .Q(device_temp_sync_r1[3]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_lcl[4]),\n .Q(device_temp_sync_r1[4]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_lcl[5]),\n .Q(device_temp_sync_r1[5]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_lcl[6]),\n .Q(device_temp_sync_r1[6]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_lcl[7]),\n .Q(device_temp_sync_r1[7]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r1_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_lcl[8]),\n .Q(device_temp_sync_r1[8]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r1_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_lcl[9]),\n .Q(device_temp_sync_r1[9]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r2_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r1[0]),\n .Q(device_temp_sync_r2[0]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r2_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r1[10]),\n .Q(device_temp_sync_r2[10]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r2_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r1[11]),\n .Q(device_temp_sync_r2[11]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r2_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r1[1]),\n .Q(device_temp_sync_r2[1]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r2_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r1[2]),\n .Q(device_temp_sync_r2[2]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r2_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r1[3]),\n .Q(device_temp_sync_r2[3]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r2_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r1[4]),\n .Q(device_temp_sync_r2[4]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r2_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r1[5]),\n .Q(device_temp_sync_r2[5]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r2_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r1[6]),\n .Q(device_temp_sync_r2[6]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r2_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r1[7]),\n .Q(device_temp_sync_r2[7]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r2_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r1[8]),\n .Q(device_temp_sync_r2[8]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r2_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r1[9]),\n .Q(device_temp_sync_r2[9]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* syn_srlstyle = \"registers\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r3_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r2[0]),\n .Q(device_temp_sync_r3[0]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* syn_srlstyle = \"registers\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r3_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r2[10]),\n .Q(device_temp_sync_r3[10]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* syn_srlstyle = \"registers\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r3_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r2[11]),\n .Q(device_temp_sync_r3[11]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* syn_srlstyle = \"registers\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r3_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r2[1]),\n .Q(device_temp_sync_r3[1]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* syn_srlstyle = \"registers\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r3_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r2[2]),\n .Q(device_temp_sync_r3[2]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* syn_srlstyle = \"registers\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r3_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r2[3]),\n .Q(device_temp_sync_r3[3]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* syn_srlstyle = \"registers\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r3_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r2[4]),\n .Q(device_temp_sync_r3[4]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* syn_srlstyle = \"registers\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r3_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r2[5]),\n .Q(device_temp_sync_r3[5]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* syn_srlstyle = \"registers\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r3_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r2[6]),\n .Q(device_temp_sync_r3[6]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* syn_srlstyle = \"registers\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r3_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r2[7]),\n .Q(device_temp_sync_r3[7]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* syn_srlstyle = \"registers\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r3_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r2[8]),\n .Q(device_temp_sync_r3[8]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* syn_srlstyle = \"registers\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r3_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r2[9]),\n .Q(device_temp_sync_r3[9]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n device_temp_sync_r4_neq_r3_i_2\n (.I0(device_temp_sync_r4[9]),\n .I1(device_temp_sync_r3[9]),\n .I2(device_temp_sync_r3[11]),\n .I3(device_temp_sync_r4[11]),\n .I4(device_temp_sync_r3[10]),\n .I5(device_temp_sync_r4[10]),\n .O(device_temp_sync_r4_neq_r3_i_2_n_0));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n device_temp_sync_r4_neq_r3_i_3\n (.I0(device_temp_sync_r4[6]),\n .I1(device_temp_sync_r3[6]),\n .I2(device_temp_sync_r3[8]),\n .I3(device_temp_sync_r4[8]),\n .I4(device_temp_sync_r3[7]),\n .I5(device_temp_sync_r4[7]),\n .O(device_temp_sync_r4_neq_r3_i_3_n_0));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n device_temp_sync_r4_neq_r3_i_4\n (.I0(device_temp_sync_r4[3]),\n .I1(device_temp_sync_r3[3]),\n .I2(device_temp_sync_r3[5]),\n .I3(device_temp_sync_r4[5]),\n .I4(device_temp_sync_r3[4]),\n .I5(device_temp_sync_r4[4]),\n .O(device_temp_sync_r4_neq_r3_i_4_n_0));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n device_temp_sync_r4_neq_r3_i_5\n (.I0(device_temp_sync_r4[0]),\n .I1(device_temp_sync_r3[0]),\n .I2(device_temp_sync_r3[2]),\n .I3(device_temp_sync_r4[2]),\n .I4(device_temp_sync_r3[1]),\n .I5(device_temp_sync_r4[1]),\n .O(device_temp_sync_r4_neq_r3_i_5_n_0));\n FDRE #(\n .INIT(1'b0)) \n device_temp_sync_r4_neq_r3_reg\n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r4_neq_r3_reg_i_1_n_0),\n .Q(device_temp_sync_r4_neq_r3),\n .R(1'b0));\n CARRY4 device_temp_sync_r4_neq_r3_reg_i_1\n (.CI(1'b0),\n .CO({device_temp_sync_r4_neq_r3_reg_i_1_n_0,device_temp_sync_r4_neq_r3_reg_i_1_n_1,device_temp_sync_r4_neq_r3_reg_i_1_n_2,device_temp_sync_r4_neq_r3_reg_i_1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b1,1'b1,1'b1,1'b1}),\n .O(NLW_device_temp_sync_r4_neq_r3_reg_i_1_O_UNCONNECTED[3:0]),\n .S({device_temp_sync_r4_neq_r3_i_2_n_0,device_temp_sync_r4_neq_r3_i_3_n_0,device_temp_sync_r4_neq_r3_i_4_n_0,device_temp_sync_r4_neq_r3_i_5_n_0}));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r4_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r3[0]),\n .Q(device_temp_sync_r4[0]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r4_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r3[10]),\n .Q(device_temp_sync_r4[10]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r4_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r3[11]),\n .Q(device_temp_sync_r4[11]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r4_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r3[1]),\n .Q(device_temp_sync_r4[1]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r4_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r3[2]),\n .Q(device_temp_sync_r4[2]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r4_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r3[3]),\n .Q(device_temp_sync_r4[3]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r4_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r3[4]),\n .Q(device_temp_sync_r4[4]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r4_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r3[5]),\n .Q(device_temp_sync_r4[5]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r4_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r3[6]),\n .Q(device_temp_sync_r4[6]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r4_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r3[7]),\n .Q(device_temp_sync_r4[7]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r4_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r3[8]),\n .Q(device_temp_sync_r4[8]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r4_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r3[9]),\n .Q(device_temp_sync_r4[9]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r5_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r4[0]),\n .Q(device_temp_sync_r5[0]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r5_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r4[10]),\n .Q(device_temp_sync_r5[10]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r5_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r4[11]),\n .Q(device_temp_sync_r5[11]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r5_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r4[1]),\n .Q(device_temp_sync_r5[1]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r5_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r4[2]),\n .Q(device_temp_sync_r5[2]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r5_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r4[3]),\n .Q(device_temp_sync_r5[3]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r5_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r4[4]),\n .Q(device_temp_sync_r5[4]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r5_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r4[5]),\n .Q(device_temp_sync_r5[5]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r5_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r4[6]),\n .Q(device_temp_sync_r5[6]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r5_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r4[7]),\n .Q(device_temp_sync_r5[7]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r5_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r4[8]),\n .Q(device_temp_sync_r5[8]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\device_temp_sync_r5_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r4[9]),\n .Q(device_temp_sync_r5[9]),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair5\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\sync_cntr[0]_i_1 \n (.I0(sync_cntr_reg__0[0]),\n .O(p_0_in__1[0]));\n (* SOFT_HLUTNM = \"soft_lutpair5\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\sync_cntr[1]_i_1 \n (.I0(sync_cntr_reg__0[0]),\n .I1(sync_cntr_reg__0[1]),\n .O(p_0_in__1[1]));\n (* SOFT_HLUTNM = \"soft_lutpair2\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\sync_cntr[2]_i_1 \n (.I0(sync_cntr_reg__0[1]),\n .I1(sync_cntr_reg__0[0]),\n .I2(sync_cntr_reg__0[2]),\n .O(\\sync_cntr[2]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\sync_cntr[3]_i_1 \n (.I0(in0),\n .I1(device_temp_sync_r4_neq_r3),\n .O(sync_cntr0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\sync_cntr[3]_i_2 \n (.I0(sync_cntr_reg__0[1]),\n .I1(sync_cntr_reg__0[0]),\n .I2(sync_cntr_reg__0[2]),\n .I3(sync_cntr_reg__0[3]),\n .O(\\sync_cntr[3]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair2\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\sync_cntr[3]_i_3 \n (.I0(sync_cntr_reg__0[2]),\n .I1(sync_cntr_reg__0[0]),\n .I2(sync_cntr_reg__0[1]),\n .I3(sync_cntr_reg__0[3]),\n .O(\\sync_cntr[3]_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\sync_cntr_reg[0] \n (.C(CLK),\n .CE(\\sync_cntr[3]_i_2_n_0 ),\n .D(p_0_in__1[0]),\n .Q(sync_cntr_reg__0[0]),\n .R(sync_cntr0));\n FDRE #(\n .INIT(1'b0)) \n \\sync_cntr_reg[1] \n (.C(CLK),\n .CE(\\sync_cntr[3]_i_2_n_0 ),\n .D(p_0_in__1[1]),\n .Q(sync_cntr_reg__0[1]),\n .R(sync_cntr0));\n FDRE #(\n .INIT(1'b0)) \n \\sync_cntr_reg[2] \n (.C(CLK),\n .CE(\\sync_cntr[3]_i_2_n_0 ),\n .D(\\sync_cntr[2]_i_1_n_0 ),\n .Q(sync_cntr_reg__0[2]),\n .R(sync_cntr0));\n FDRE #(\n .INIT(1'b0)) \n \\sync_cntr_reg[3] \n (.C(CLK),\n .CE(\\sync_cntr[3]_i_2_n_0 ),\n .D(\\sync_cntr[3]_i_3_n_0 ),\n .Q(sync_cntr_reg__0[3]),\n .R(sync_cntr0));\n (* box_type = \"PRIMITIVE\" *) \n XADC #(\n .INIT_40(16'h1000),\n .INIT_41(16'h2FFF),\n .INIT_42(16'h0800),\n .INIT_43(16'h0000),\n .INIT_44(16'h0000),\n .INIT_45(16'h0000),\n .INIT_46(16'h0000),\n .INIT_47(16'h0000),\n .INIT_48(16'h0101),\n .INIT_49(16'h0000),\n .INIT_4A(16'h0100),\n .INIT_4B(16'h0000),\n .INIT_4C(16'h0000),\n .INIT_4D(16'h0000),\n .INIT_4E(16'h0000),\n .INIT_4F(16'h0000),\n .INIT_50(16'hB5ED),\n .INIT_51(16'h57E4),\n .INIT_52(16'hA147),\n .INIT_53(16'hCA33),\n .INIT_54(16'hA93A),\n .INIT_55(16'h52C6),\n .INIT_56(16'h9555),\n .INIT_57(16'hAE4E),\n .INIT_58(16'h5999),\n .INIT_59(16'h0000),\n .INIT_5A(16'h0000),\n .INIT_5B(16'h0000),\n .INIT_5C(16'h5111),\n .INIT_5D(16'h0000),\n .INIT_5E(16'h0000),\n .INIT_5F(16'h0000),\n .IS_CONVSTCLK_INVERTED(1'b0),\n .IS_DCLK_INVERTED(1'b0),\n .SIM_DEVICE(\"7SERIES\"),\n .SIM_MONITOR_FILE(\"design.txt\")) \n \\xadc_supplied_temperature.XADC_inst \n (.ALM(\\NLW_xadc_supplied_temperature.XADC_inst_ALM_UNCONNECTED [7:0]),\n .BUSY(\\NLW_xadc_supplied_temperature.XADC_inst_BUSY_UNCONNECTED ),\n .CHANNEL(\\NLW_xadc_supplied_temperature.XADC_inst_CHANNEL_UNCONNECTED [4:0]),\n .CONVST(1'b0),\n .CONVSTCLK(1'b0),\n .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DCLK(mmcm_clk),\n .DEN(xadc_den),\n .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DO(xadc_do),\n .DRDY(xadc_drdy),\n .DWE(1'b0),\n .EOC(\\NLW_xadc_supplied_temperature.XADC_inst_EOC_UNCONNECTED ),\n .EOS(\\NLW_xadc_supplied_temperature.XADC_inst_EOS_UNCONNECTED ),\n .JTAGBUSY(\\NLW_xadc_supplied_temperature.XADC_inst_JTAGBUSY_UNCONNECTED ),\n .JTAGLOCKED(\\NLW_xadc_supplied_temperature.XADC_inst_JTAGLOCKED_UNCONNECTED ),\n .JTAGMODIFIED(\\NLW_xadc_supplied_temperature.XADC_inst_JTAGMODIFIED_UNCONNECTED ),\n .MUXADDR(\\NLW_xadc_supplied_temperature.XADC_inst_MUXADDR_UNCONNECTED [4:0]),\n .OT(\\NLW_xadc_supplied_temperature.XADC_inst_OT_UNCONNECTED ),\n .RESET(1'b0),\n .VAUXN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .VAUXP({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .VN(1'b0),\n .VP(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.rst_r1_reg \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(in0),\n .Q(rst_r1),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.rst_r2_reg \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(rst_r1),\n .Q(rst_r2),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0000020000000000)) \n \\xadc_supplied_temperature.sample_en_i_1 \n (.I0(\\xadc_supplied_temperature.sample_timer_reg__0 [3]),\n .I1(\\xadc_supplied_temperature.sample_timer_reg__0 [4]),\n .I2(\\xadc_supplied_temperature.sample_timer_reg__0 [2]),\n .I3(\\xadc_supplied_temperature.sample_timer_reg__0 [1]),\n .I4(\\xadc_supplied_temperature.sample_timer_reg__0 [0]),\n .I5(\\xadc_supplied_temperature.sample_en_i_2_n_0 ),\n .O(sample_en0));\n LUT6 #(\n .INIT(64'h0080000000000000)) \n \\xadc_supplied_temperature.sample_en_i_2 \n (.I0(\\xadc_supplied_temperature.sample_timer_reg__0 [7]),\n .I1(\\xadc_supplied_temperature.sample_timer_reg__0 [8]),\n .I2(\\xadc_supplied_temperature.sample_timer_reg__0 [6]),\n .I3(\\xadc_supplied_temperature.sample_timer_reg__0 [5]),\n .I4(\\xadc_supplied_temperature.sample_timer_reg__0 [10]),\n .I5(\\xadc_supplied_temperature.sample_timer_reg__0 [9]),\n .O(\\xadc_supplied_temperature.sample_en_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.sample_en_reg \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(sample_en0),\n .Q(sample_en),\n .R(1'b0));\n LUT1 #(\n .INIT(2'h1)) \n \\xadc_supplied_temperature.sample_timer[0]_i_1 \n (.I0(\\xadc_supplied_temperature.sample_timer_reg__0 [0]),\n .O(\\xadc_supplied_temperature.sample_timer[0]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\xadc_supplied_temperature.sample_timer[10]_i_1 \n (.I0(rst_r2),\n .I1(xadc_den),\n .O(sample_timer0));\n LUT6 #(\n .INIT(64'hF7FFFFFF08000000)) \n \\xadc_supplied_temperature.sample_timer[10]_i_2 \n (.I0(\\xadc_supplied_temperature.sample_timer_reg__0 [9]),\n .I1(\\xadc_supplied_temperature.sample_timer_reg__0 [7]),\n .I2(\\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ),\n .I3(\\xadc_supplied_temperature.sample_timer_reg__0 [6]),\n .I4(\\xadc_supplied_temperature.sample_timer_reg__0 [8]),\n .I5(\\xadc_supplied_temperature.sample_timer_reg__0 [10]),\n .O(p_0_in__0[10]));\n LUT6 #(\n .INIT(64'h7FFFFFFFFFFFFFFF)) \n \\xadc_supplied_temperature.sample_timer[10]_i_3 \n (.I0(\\xadc_supplied_temperature.sample_timer_reg__0 [4]),\n .I1(\\xadc_supplied_temperature.sample_timer_reg__0 [2]),\n .I2(\\xadc_supplied_temperature.sample_timer_reg__0 [0]),\n .I3(\\xadc_supplied_temperature.sample_timer_reg__0 [1]),\n .I4(\\xadc_supplied_temperature.sample_timer_reg__0 [3]),\n .I5(\\xadc_supplied_temperature.sample_timer_reg__0 [5]),\n .O(\\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair4\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\xadc_supplied_temperature.sample_timer[1]_i_1 \n (.I0(\\xadc_supplied_temperature.sample_timer_reg__0 [0]),\n .I1(\\xadc_supplied_temperature.sample_timer_reg__0 [1]),\n .O(p_0_in__0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair4\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\xadc_supplied_temperature.sample_timer[2]_i_1 \n (.I0(\\xadc_supplied_temperature.sample_timer_reg__0 [1]),\n .I1(\\xadc_supplied_temperature.sample_timer_reg__0 [0]),\n .I2(\\xadc_supplied_temperature.sample_timer_reg__0 [2]),\n .O(p_0_in__0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair0\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\xadc_supplied_temperature.sample_timer[3]_i_1 \n (.I0(\\xadc_supplied_temperature.sample_timer_reg__0 [2]),\n .I1(\\xadc_supplied_temperature.sample_timer_reg__0 [0]),\n .I2(\\xadc_supplied_temperature.sample_timer_reg__0 [1]),\n .I3(\\xadc_supplied_temperature.sample_timer_reg__0 [3]),\n .O(p_0_in__0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair0\" *) \n LUT5 #(\n .INIT(32'h7FFF8000)) \n \\xadc_supplied_temperature.sample_timer[4]_i_1 \n (.I0(\\xadc_supplied_temperature.sample_timer_reg__0 [3]),\n .I1(\\xadc_supplied_temperature.sample_timer_reg__0 [1]),\n .I2(\\xadc_supplied_temperature.sample_timer_reg__0 [0]),\n .I3(\\xadc_supplied_temperature.sample_timer_reg__0 [2]),\n .I4(\\xadc_supplied_temperature.sample_timer_reg__0 [4]),\n .O(p_0_in__0[4]));\n LUT6 #(\n .INIT(64'h7FFFFFFF80000000)) \n \\xadc_supplied_temperature.sample_timer[5]_i_1 \n (.I0(\\xadc_supplied_temperature.sample_timer_reg__0 [4]),\n .I1(\\xadc_supplied_temperature.sample_timer_reg__0 [2]),\n .I2(\\xadc_supplied_temperature.sample_timer_reg__0 [0]),\n .I3(\\xadc_supplied_temperature.sample_timer_reg__0 [1]),\n .I4(\\xadc_supplied_temperature.sample_timer_reg__0 [3]),\n .I5(\\xadc_supplied_temperature.sample_timer_reg__0 [5]),\n .O(p_0_in__0[5]));\n (* SOFT_HLUTNM = \"soft_lutpair3\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\xadc_supplied_temperature.sample_timer[6]_i_1 \n (.I0(\\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ),\n .I1(\\xadc_supplied_temperature.sample_timer_reg__0 [6]),\n .O(p_0_in__0[6]));\n (* SOFT_HLUTNM = \"soft_lutpair3\" *) \n LUT3 #(\n .INIT(8'hD2)) \n \\xadc_supplied_temperature.sample_timer[7]_i_1 \n (.I0(\\xadc_supplied_temperature.sample_timer_reg__0 [6]),\n .I1(\\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ),\n .I2(\\xadc_supplied_temperature.sample_timer_reg__0 [7]),\n .O(p_0_in__0[7]));\n (* SOFT_HLUTNM = \"soft_lutpair1\" *) \n LUT4 #(\n .INIT(16'hDF20)) \n \\xadc_supplied_temperature.sample_timer[8]_i_1 \n (.I0(\\xadc_supplied_temperature.sample_timer_reg__0 [7]),\n .I1(\\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ),\n .I2(\\xadc_supplied_temperature.sample_timer_reg__0 [6]),\n .I3(\\xadc_supplied_temperature.sample_timer_reg__0 [8]),\n .O(p_0_in__0[8]));\n (* SOFT_HLUTNM = \"soft_lutpair1\" *) \n LUT5 #(\n .INIT(32'hF7FF0800)) \n \\xadc_supplied_temperature.sample_timer[9]_i_1 \n (.I0(\\xadc_supplied_temperature.sample_timer_reg__0 [8]),\n .I1(\\xadc_supplied_temperature.sample_timer_reg__0 [6]),\n .I2(\\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ),\n .I3(\\xadc_supplied_temperature.sample_timer_reg__0 [7]),\n .I4(\\xadc_supplied_temperature.sample_timer_reg__0 [9]),\n .O(p_0_in__0[9]));\n LUT4 #(\n .INIT(16'h000E)) \n \\xadc_supplied_temperature.sample_timer_clr_i_1 \n (.I0(xadc_den),\n .I1(\\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[1] ),\n .I2(\\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2] ),\n .I3(rst_r2),\n .O(\\xadc_supplied_temperature.sample_timer_clr_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.sample_timer_clr_reg \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(\\xadc_supplied_temperature.sample_timer_clr_i_1_n_0 ),\n .Q(xadc_den),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h000000FE)) \n \\xadc_supplied_temperature.sample_timer_en_i_1 \n (.I0(sample_timer_en),\n .I1(\\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ),\n .I2(temperature),\n .I3(\\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[1] ),\n .I4(rst_r2),\n .O(\\xadc_supplied_temperature.sample_timer_en_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.sample_timer_en_reg \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(\\xadc_supplied_temperature.sample_timer_en_i_1_n_0 ),\n .Q(sample_timer_en),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.sample_timer_reg[0] \n (.C(mmcm_clk),\n .CE(sample_timer_en),\n .D(\\xadc_supplied_temperature.sample_timer[0]_i_1_n_0 ),\n .Q(\\xadc_supplied_temperature.sample_timer_reg__0 [0]),\n .R(sample_timer0));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.sample_timer_reg[10] \n (.C(mmcm_clk),\n .CE(sample_timer_en),\n .D(p_0_in__0[10]),\n .Q(\\xadc_supplied_temperature.sample_timer_reg__0 [10]),\n .R(sample_timer0));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.sample_timer_reg[1] \n (.C(mmcm_clk),\n .CE(sample_timer_en),\n .D(p_0_in__0[1]),\n .Q(\\xadc_supplied_temperature.sample_timer_reg__0 [1]),\n .R(sample_timer0));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.sample_timer_reg[2] \n (.C(mmcm_clk),\n .CE(sample_timer_en),\n .D(p_0_in__0[2]),\n .Q(\\xadc_supplied_temperature.sample_timer_reg__0 [2]),\n .R(sample_timer0));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.sample_timer_reg[3] \n (.C(mmcm_clk),\n .CE(sample_timer_en),\n .D(p_0_in__0[3]),\n .Q(\\xadc_supplied_temperature.sample_timer_reg__0 [3]),\n .R(sample_timer0));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.sample_timer_reg[4] \n (.C(mmcm_clk),\n .CE(sample_timer_en),\n .D(p_0_in__0[4]),\n .Q(\\xadc_supplied_temperature.sample_timer_reg__0 [4]),\n .R(sample_timer0));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.sample_timer_reg[5] \n (.C(mmcm_clk),\n .CE(sample_timer_en),\n .D(p_0_in__0[5]),\n .Q(\\xadc_supplied_temperature.sample_timer_reg__0 [5]),\n .R(sample_timer0));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.sample_timer_reg[6] \n (.C(mmcm_clk),\n .CE(sample_timer_en),\n .D(p_0_in__0[6]),\n .Q(\\xadc_supplied_temperature.sample_timer_reg__0 [6]),\n .R(sample_timer0));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.sample_timer_reg[7] \n (.C(mmcm_clk),\n .CE(sample_timer_en),\n .D(p_0_in__0[7]),\n .Q(\\xadc_supplied_temperature.sample_timer_reg__0 [7]),\n .R(sample_timer0));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.sample_timer_reg[8] \n (.C(mmcm_clk),\n .CE(sample_timer_en),\n .D(p_0_in__0[8]),\n .Q(\\xadc_supplied_temperature.sample_timer_reg__0 [8]),\n .R(sample_timer0));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.sample_timer_reg[9] \n (.C(mmcm_clk),\n .CE(sample_timer_en),\n .D(p_0_in__0[9]),\n .Q(\\xadc_supplied_temperature.sample_timer_reg__0 [9]),\n .R(sample_timer0));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.temperature_reg[0] \n (.C(mmcm_clk),\n .CE(temperature),\n .D(p_0_in[0]),\n .Q(device_temp_lcl[0]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.temperature_reg[10] \n (.C(mmcm_clk),\n .CE(temperature),\n .D(p_0_in[10]),\n .Q(device_temp_lcl[10]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.temperature_reg[11] \n (.C(mmcm_clk),\n .CE(temperature),\n .D(p_0_in[11]),\n .Q(device_temp_lcl[11]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.temperature_reg[1] \n (.C(mmcm_clk),\n .CE(temperature),\n .D(p_0_in[1]),\n .Q(device_temp_lcl[1]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.temperature_reg[2] \n (.C(mmcm_clk),\n .CE(temperature),\n .D(p_0_in[2]),\n .Q(device_temp_lcl[2]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.temperature_reg[3] \n (.C(mmcm_clk),\n .CE(temperature),\n .D(p_0_in[3]),\n .Q(device_temp_lcl[3]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.temperature_reg[4] \n (.C(mmcm_clk),\n .CE(temperature),\n .D(p_0_in[4]),\n .Q(device_temp_lcl[4]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.temperature_reg[5] \n (.C(mmcm_clk),\n .CE(temperature),\n .D(p_0_in[5]),\n .Q(device_temp_lcl[5]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.temperature_reg[6] \n (.C(mmcm_clk),\n .CE(temperature),\n .D(p_0_in[6]),\n .Q(device_temp_lcl[6]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.temperature_reg[7] \n (.C(mmcm_clk),\n .CE(temperature),\n .D(p_0_in[7]),\n .Q(device_temp_lcl[7]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.temperature_reg[8] \n (.C(mmcm_clk),\n .CE(temperature),\n .D(p_0_in[8]),\n .Q(device_temp_lcl[8]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.temperature_reg[9] \n (.C(mmcm_clk),\n .CE(temperature),\n .D(p_0_in[9]),\n .Q(device_temp_lcl[9]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.xadc_do_r_reg[10] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(xadc_do[10]),\n .Q(p_0_in[6]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.xadc_do_r_reg[11] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(xadc_do[11]),\n .Q(p_0_in[7]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.xadc_do_r_reg[12] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(xadc_do[12]),\n .Q(p_0_in[8]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.xadc_do_r_reg[13] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(xadc_do[13]),\n .Q(p_0_in[9]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.xadc_do_r_reg[14] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(xadc_do[14]),\n .Q(p_0_in[10]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.xadc_do_r_reg[15] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(xadc_do[15]),\n .Q(p_0_in[11]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.xadc_do_r_reg[4] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(xadc_do[4]),\n .Q(p_0_in[0]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.xadc_do_r_reg[5] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(xadc_do[5]),\n .Q(p_0_in[1]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.xadc_do_r_reg[6] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(xadc_do[6]),\n .Q(p_0_in[2]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.xadc_do_r_reg[7] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(xadc_do[7]),\n .Q(p_0_in[3]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.xadc_do_r_reg[8] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(xadc_do[8]),\n .Q(p_0_in[4]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.xadc_do_r_reg[9] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(xadc_do[9]),\n .Q(p_0_in[5]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.xadc_drdy_r_reg \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(xadc_drdy),\n .Q(xadc_drdy_r),\n .R(rst_r2));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ui_cmd\" *) \nmodule ddr3_ifmig_7series_v4_0_ui_cmd\n (E,\n app_en_r1,\n app_hi_pri_r2,\n hi_priority,\n cmd,\n p_28_out,\n rb_hit_busy_r_reg,\n p_67_out,\n rb_hit_busy_r_reg_0,\n \\req_bank_r_lcl_reg[2] ,\n \\wr_req_counter.wr_req_cnt_r_reg[4] ,\n \\wr_req_counter.wr_req_cnt_r_reg[3] ,\n wr_accepted,\n \\not_strict_mode.occupied_counter.occ_cnt_r_reg[3] ,\n rd_accepted,\n use_addr,\n \\req_data_buf_addr_r_reg[4] ,\n \\req_row_r_lcl_reg[14] ,\n \\req_col_r_reg[9] ,\n app_rdy_ns,\n CLK,\n app_en_ns1,\n mc_app_cmd,\n idle_ns,\n \\req_bank_r_lcl_reg[2]_0 ,\n \\req_bank_r_lcl_reg[2]_1 ,\n reset_reg,\n p_0_in,\n wr_req_cnt_r,\n Q,\n wr_data_buf_addr,\n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ,\n app_rdy_r_reg_0,\n \\axaddr_incr_reg[29] );\n output [0:0]E;\n output app_en_r1;\n output app_hi_pri_r2;\n output hi_priority;\n output [1:0]cmd;\n output p_28_out;\n output rb_hit_busy_r_reg;\n output p_67_out;\n output rb_hit_busy_r_reg_0;\n output [2:0]\\req_bank_r_lcl_reg[2] ;\n output \\wr_req_counter.wr_req_cnt_r_reg[4] ;\n output \\wr_req_counter.wr_req_cnt_r_reg[3] ;\n output wr_accepted;\n output \\not_strict_mode.occupied_counter.occ_cnt_r_reg[3] ;\n output rd_accepted;\n output use_addr;\n output [4:0]\\req_data_buf_addr_r_reg[4] ;\n output [14:0]\\req_row_r_lcl_reg[14] ;\n output [6:0]\\req_col_r_reg[9] ;\n input app_rdy_ns;\n input CLK;\n input app_en_ns1;\n input [0:0]mc_app_cmd;\n input [1:0]idle_ns;\n input [2:0]\\req_bank_r_lcl_reg[2]_0 ;\n input [2:0]\\req_bank_r_lcl_reg[2]_1 ;\n input reset_reg;\n input [0:0]p_0_in;\n input [1:0]wr_req_cnt_r;\n input [1:0]Q;\n input [3:0]wr_data_buf_addr;\n input [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n input [0:0]app_rdy_r_reg_0;\n input [24:0]\\axaddr_incr_reg[29] ;\n\n wire CLK;\n wire [0:0]E;\n wire [1:0]Q;\n wire \\app_addr_r1_reg_n_0_[13] ;\n wire \\app_addr_r1_reg_n_0_[14] ;\n wire \\app_addr_r1_reg_n_0_[15] ;\n wire \\app_addr_r1_reg_n_0_[16] ;\n wire \\app_addr_r1_reg_n_0_[17] ;\n wire \\app_addr_r1_reg_n_0_[18] ;\n wire \\app_addr_r1_reg_n_0_[19] ;\n wire \\app_addr_r1_reg_n_0_[20] ;\n wire \\app_addr_r1_reg_n_0_[21] ;\n wire \\app_addr_r1_reg_n_0_[22] ;\n wire \\app_addr_r1_reg_n_0_[23] ;\n wire \\app_addr_r1_reg_n_0_[24] ;\n wire \\app_addr_r1_reg_n_0_[25] ;\n wire \\app_addr_r1_reg_n_0_[26] ;\n wire \\app_addr_r1_reg_n_0_[27] ;\n wire \\app_addr_r1_reg_n_0_[3] ;\n wire \\app_addr_r1_reg_n_0_[4] ;\n wire \\app_addr_r1_reg_n_0_[5] ;\n wire \\app_addr_r1_reg_n_0_[6] ;\n wire \\app_addr_r1_reg_n_0_[7] ;\n wire \\app_addr_r1_reg_n_0_[8] ;\n wire \\app_addr_r1_reg_n_0_[9] ;\n wire \\app_addr_r2_reg_n_0_[13] ;\n wire \\app_addr_r2_reg_n_0_[14] ;\n wire \\app_addr_r2_reg_n_0_[15] ;\n wire \\app_addr_r2_reg_n_0_[16] ;\n wire \\app_addr_r2_reg_n_0_[17] ;\n wire \\app_addr_r2_reg_n_0_[18] ;\n wire \\app_addr_r2_reg_n_0_[19] ;\n wire \\app_addr_r2_reg_n_0_[20] ;\n wire \\app_addr_r2_reg_n_0_[21] ;\n wire \\app_addr_r2_reg_n_0_[22] ;\n wire \\app_addr_r2_reg_n_0_[23] ;\n wire \\app_addr_r2_reg_n_0_[24] ;\n wire \\app_addr_r2_reg_n_0_[25] ;\n wire \\app_addr_r2_reg_n_0_[26] ;\n wire \\app_addr_r2_reg_n_0_[27] ;\n wire \\app_addr_r2_reg_n_0_[3] ;\n wire \\app_addr_r2_reg_n_0_[4] ;\n wire \\app_addr_r2_reg_n_0_[5] ;\n wire \\app_addr_r2_reg_n_0_[6] ;\n wire \\app_addr_r2_reg_n_0_[7] ;\n wire \\app_addr_r2_reg_n_0_[8] ;\n wire \\app_addr_r2_reg_n_0_[9] ;\n wire [0:0]app_cmd_r1;\n wire \\app_cmd_r1[0]_i_1_n_0 ;\n wire [1:0]app_cmd_r2;\n wire app_en_ns1;\n wire app_en_ns2;\n wire app_en_r1;\n wire app_en_r2;\n wire app_hi_pri_r2;\n wire app_rdy_ns;\n wire [0:0]app_rdy_r_reg_0;\n wire [24:0]\\axaddr_incr_reg[29] ;\n wire [1:0]cmd;\n wire hi_priority;\n wire [1:0]idle_ns;\n wire [0:0]mc_app_cmd;\n wire [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n wire \\not_strict_mode.occupied_counter.occ_cnt_r_reg[3] ;\n wire [0:0]p_0_in;\n wire [2:0]p_0_in_0;\n wire [2:0]p_1_in;\n wire p_28_out;\n wire p_67_out;\n wire rb_hit_busy_r_reg;\n wire rb_hit_busy_r_reg_0;\n wire rd_accepted;\n wire [2:0]\\req_bank_r_lcl_reg[2] ;\n wire [2:0]\\req_bank_r_lcl_reg[2]_0 ;\n wire [2:0]\\req_bank_r_lcl_reg[2]_1 ;\n wire [6:0]\\req_col_r_reg[9] ;\n wire [4:0]\\req_data_buf_addr_r_reg[4] ;\n wire [14:0]\\req_row_r_lcl_reg[14] ;\n wire reset_reg;\n wire use_addr;\n wire wr_accepted;\n wire [3:0]wr_data_buf_addr;\n wire [1:0]wr_req_cnt_r;\n wire \\wr_req_counter.wr_req_cnt_r_reg[3] ;\n wire \\wr_req_counter.wr_req_cnt_r_reg[4] ;\n\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[10] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [7]),\n .Q(p_1_in[0]),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[11] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [8]),\n .Q(p_1_in[1]),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[12] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [9]),\n .Q(p_1_in[2]),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[13] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [10]),\n .Q(\\app_addr_r1_reg_n_0_[13] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[14] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [11]),\n .Q(\\app_addr_r1_reg_n_0_[14] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[15] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [12]),\n .Q(\\app_addr_r1_reg_n_0_[15] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[16] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [13]),\n .Q(\\app_addr_r1_reg_n_0_[16] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[17] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [14]),\n .Q(\\app_addr_r1_reg_n_0_[17] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[18] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [15]),\n .Q(\\app_addr_r1_reg_n_0_[18] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[19] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [16]),\n .Q(\\app_addr_r1_reg_n_0_[19] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[20] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [17]),\n .Q(\\app_addr_r1_reg_n_0_[20] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[21] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [18]),\n .Q(\\app_addr_r1_reg_n_0_[21] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[22] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [19]),\n .Q(\\app_addr_r1_reg_n_0_[22] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[23] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [20]),\n .Q(\\app_addr_r1_reg_n_0_[23] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[24] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [21]),\n .Q(\\app_addr_r1_reg_n_0_[24] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[25] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [22]),\n .Q(\\app_addr_r1_reg_n_0_[25] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[26] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [23]),\n .Q(\\app_addr_r1_reg_n_0_[26] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[27] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [24]),\n .Q(\\app_addr_r1_reg_n_0_[27] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[3] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [0]),\n .Q(\\app_addr_r1_reg_n_0_[3] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[4] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [1]),\n .Q(\\app_addr_r1_reg_n_0_[4] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[5] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [2]),\n .Q(\\app_addr_r1_reg_n_0_[5] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[6] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [3]),\n .Q(\\app_addr_r1_reg_n_0_[6] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[7] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [4]),\n .Q(\\app_addr_r1_reg_n_0_[7] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[8] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [5]),\n .Q(\\app_addr_r1_reg_n_0_[8] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[9] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [6]),\n .Q(\\app_addr_r1_reg_n_0_[9] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[10] \n (.C(CLK),\n .CE(E),\n .D(p_1_in[0]),\n .Q(p_0_in_0[0]),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[11] \n (.C(CLK),\n .CE(E),\n .D(p_1_in[1]),\n .Q(p_0_in_0[1]),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[12] \n (.C(CLK),\n .CE(E),\n .D(p_1_in[2]),\n .Q(p_0_in_0[2]),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[13] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[13] ),\n .Q(\\app_addr_r2_reg_n_0_[13] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[14] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[14] ),\n .Q(\\app_addr_r2_reg_n_0_[14] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[15] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[15] ),\n .Q(\\app_addr_r2_reg_n_0_[15] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[16] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[16] ),\n .Q(\\app_addr_r2_reg_n_0_[16] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[17] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[17] ),\n .Q(\\app_addr_r2_reg_n_0_[17] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[18] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[18] ),\n .Q(\\app_addr_r2_reg_n_0_[18] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[19] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[19] ),\n .Q(\\app_addr_r2_reg_n_0_[19] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[20] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[20] ),\n .Q(\\app_addr_r2_reg_n_0_[20] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[21] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[21] ),\n .Q(\\app_addr_r2_reg_n_0_[21] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[22] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[22] ),\n .Q(\\app_addr_r2_reg_n_0_[22] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[23] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[23] ),\n .Q(\\app_addr_r2_reg_n_0_[23] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[24] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[24] ),\n .Q(\\app_addr_r2_reg_n_0_[24] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[25] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[25] ),\n .Q(\\app_addr_r2_reg_n_0_[25] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[26] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[26] ),\n .Q(\\app_addr_r2_reg_n_0_[26] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[27] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[27] ),\n .Q(\\app_addr_r2_reg_n_0_[27] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[3] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[3] ),\n .Q(\\app_addr_r2_reg_n_0_[3] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[4] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[4] ),\n .Q(\\app_addr_r2_reg_n_0_[4] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[5] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[5] ),\n .Q(\\app_addr_r2_reg_n_0_[5] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[6] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[6] ),\n .Q(\\app_addr_r2_reg_n_0_[6] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[7] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[7] ),\n .Q(\\app_addr_r2_reg_n_0_[7] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[8] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[8] ),\n .Q(\\app_addr_r2_reg_n_0_[8] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[9] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[9] ),\n .Q(\\app_addr_r2_reg_n_0_[9] ),\n .R(reset_reg));\n (* SOFT_HLUTNM = \"soft_lutpair1461\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\app_cmd_r1[0]_i_1 \n (.I0(mc_app_cmd),\n .I1(E),\n .I2(app_cmd_r1),\n .O(\\app_cmd_r1[0]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\app_cmd_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\app_cmd_r1[0]_i_1_n_0 ),\n .Q(app_cmd_r1),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1461\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\app_cmd_r2[0]_i_1 \n (.I0(app_cmd_r1),\n .I1(E),\n .I2(app_cmd_r2[0]),\n .O(cmd[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1456\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\app_cmd_r2[1]_i_1 \n (.I0(app_cmd_r2[1]),\n .I1(E),\n .O(cmd[1]));\n FDRE #(\n .INIT(1'b0)) \n \\app_cmd_r2_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(cmd[0]),\n .Q(app_cmd_r2[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_cmd_r2_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(cmd[1]),\n .Q(app_cmd_r2[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n app_en_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(app_en_ns1),\n .Q(app_en_r1),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1457\" *) \n LUT4 #(\n .INIT(16'h2230)) \n app_en_r2_i_1\n (.I0(app_en_r1),\n .I1(reset_reg),\n .I2(app_en_r2),\n .I3(E),\n .O(app_en_ns2));\n FDRE #(\n .INIT(1'b0)) \n app_en_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(app_en_ns2),\n .Q(app_en_r2),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n app_hi_pri_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(hi_priority),\n .Q(app_hi_pri_r2),\n .R(1'b0));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n app_rdy_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(app_rdy_ns),\n .Q(E),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1454\" *) \n LUT4 #(\n .INIT(16'h8008)) \n \\data_buf_address_counter.data_buf_addr_cnt_r[3]_i_1 \n (.I0(E),\n .I1(app_en_r2),\n .I2(app_cmd_r2[0]),\n .I3(app_cmd_r2[1]),\n .O(wr_accepted));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n i___33_i_1\n (.I0(\\req_bank_r_lcl_reg[2] [0]),\n .I1(\\req_bank_r_lcl_reg[2]_1 [0]),\n .I2(\\req_bank_r_lcl_reg[2]_1 [1]),\n .I3(\\req_bank_r_lcl_reg[2] [1]),\n .I4(\\req_bank_r_lcl_reg[2]_1 [2]),\n .I5(\\req_bank_r_lcl_reg[2] [2]),\n .O(rb_hit_busy_r_reg_0));\n (* SOFT_HLUTNM = \"soft_lutpair1454\" *) \n LUT2 #(\n .INIT(4'h8)) \n idle_r_lcl_i_2\n (.I0(app_en_r2),\n .I1(E),\n .O(use_addr));\n (* SOFT_HLUTNM = \"soft_lutpair1453\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[4]_i_1 \n (.I0(app_cmd_r2[1]),\n .I1(app_cmd_r2[0]),\n .I2(E),\n .I3(app_en_r2),\n .O(rd_accepted));\n LUT6 #(\n .INIT(64'h7555555510000000)) \n \\not_strict_mode.occupied_counter.occ_cnt_r[3]_i_2 \n (.I0(Q[1]),\n .I1(app_cmd_r2[1]),\n .I2(app_cmd_r2[0]),\n .I3(E),\n .I4(app_en_r2),\n .I5(Q[0]),\n .O(\\not_strict_mode.occupied_counter.occ_cnt_r_reg[3] ));\n LUT2 #(\n .INIT(4'h2)) \n rb_hit_busy_r_i_1\n (.I0(rb_hit_busy_r_reg),\n .I1(idle_ns[1]),\n .O(p_28_out));\n LUT2 #(\n .INIT(4'h2)) \n rb_hit_busy_r_i_1__0\n (.I0(rb_hit_busy_r_reg_0),\n .I1(idle_ns[0]),\n .O(p_67_out));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n rb_hit_busy_r_i_2\n (.I0(\\req_bank_r_lcl_reg[2] [0]),\n .I1(\\req_bank_r_lcl_reg[2]_0 [0]),\n .I2(\\req_bank_r_lcl_reg[2]_0 [1]),\n .I3(\\req_bank_r_lcl_reg[2] [1]),\n .I4(\\req_bank_r_lcl_reg[2]_0 [2]),\n .I5(\\req_bank_r_lcl_reg[2] [2]),\n .O(rb_hit_busy_r_reg));\n (* SOFT_HLUTNM = \"soft_lutpair1467\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_bank_r_lcl[0]_i_1 \n (.I0(p_1_in[0]),\n .I1(E),\n .I2(p_0_in_0[0]),\n .O(\\req_bank_r_lcl_reg[2] [0]));\n (* SOFT_HLUTNM = \"soft_lutpair1467\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_bank_r_lcl[1]_i_1 \n (.I0(p_1_in[1]),\n .I1(E),\n .I2(p_0_in_0[1]),\n .O(\\req_bank_r_lcl_reg[2] [1]));\n (* SOFT_HLUTNM = \"soft_lutpair1466\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_bank_r_lcl[2]_i_1 \n (.I0(p_1_in[2]),\n .I1(E),\n .I2(p_0_in_0[2]),\n .O(\\req_bank_r_lcl_reg[2] [2]));\n (* SOFT_HLUTNM = \"soft_lutpair1470\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_col_r[3]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[3] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[3] ),\n .O(\\req_col_r_reg[9] [0]));\n LUT3 #(\n .INIT(8'hB8)) \n \\req_col_r[4]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[4] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[4] ),\n .O(\\req_col_r_reg[9] [1]));\n (* SOFT_HLUTNM = \"soft_lutpair1470\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_col_r[5]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[5] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[5] ),\n .O(\\req_col_r_reg[9] [2]));\n (* SOFT_HLUTNM = \"soft_lutpair1469\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_col_r[6]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[6] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[6] ),\n .O(\\req_col_r_reg[9] [3]));\n (* SOFT_HLUTNM = \"soft_lutpair1469\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_col_r[7]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[7] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[7] ),\n .O(\\req_col_r_reg[9] [4]));\n (* SOFT_HLUTNM = \"soft_lutpair1468\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_col_r[8]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[8] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[8] ),\n .O(\\req_col_r_reg[9] [5]));\n (* SOFT_HLUTNM = \"soft_lutpair1468\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_col_r[9]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[9] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[9] ),\n .O(\\req_col_r_reg[9] [6]));\n LUT4 #(\n .INIT(16'hBE82)) \n \\req_data_buf_addr_r[0]_i_1 \n (.I0(wr_data_buf_addr[0]),\n .I1(app_cmd_r2[1]),\n .I2(app_cmd_r2[0]),\n .I3(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [0]),\n .O(\\req_data_buf_addr_r_reg[4] [0]));\n (* SOFT_HLUTNM = \"soft_lutpair1456\" *) \n LUT4 #(\n .INIT(16'hBE82)) \n \\req_data_buf_addr_r[1]_i_1 \n (.I0(wr_data_buf_addr[1]),\n .I1(app_cmd_r2[1]),\n .I2(app_cmd_r2[0]),\n .I3(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [1]),\n .O(\\req_data_buf_addr_r_reg[4] [1]));\n (* SOFT_HLUTNM = \"soft_lutpair1455\" *) \n LUT4 #(\n .INIT(16'hBE82)) \n \\req_data_buf_addr_r[2]_i_1 \n (.I0(wr_data_buf_addr[2]),\n .I1(app_cmd_r2[1]),\n .I2(app_cmd_r2[0]),\n .I3(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [2]),\n .O(\\req_data_buf_addr_r_reg[4] [2]));\n LUT4 #(\n .INIT(16'hBE82)) \n \\req_data_buf_addr_r[3]_i_1 \n (.I0(wr_data_buf_addr[3]),\n .I1(app_cmd_r2[1]),\n .I2(app_cmd_r2[0]),\n .I3(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [3]),\n .O(\\req_data_buf_addr_r_reg[4] [3]));\n (* SOFT_HLUTNM = \"soft_lutpair1455\" *) \n LUT3 #(\n .INIT(8'h28)) \n \\req_data_buf_addr_r[4]_i_1 \n (.I0(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [4]),\n .I1(app_cmd_r2[0]),\n .I2(app_cmd_r2[1]),\n .O(\\req_data_buf_addr_r_reg[4] [4]));\n (* SOFT_HLUTNM = \"soft_lutpair1457\" *) \n LUT2 #(\n .INIT(4'h2)) \n req_priority_r_i_1\n (.I0(app_hi_pri_r2),\n .I1(E),\n .O(hi_priority));\n (* SOFT_HLUTNM = \"soft_lutpair1460\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_row_r_lcl[0]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[13] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[13] ),\n .O(\\req_row_r_lcl_reg[14] [0]));\n (* SOFT_HLUTNM = \"soft_lutpair1464\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_row_r_lcl[10]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[23] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[23] ),\n .O(\\req_row_r_lcl_reg[14] [10]));\n (* SOFT_HLUTNM = \"soft_lutpair1463\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_row_r_lcl[11]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[24] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[24] ),\n .O(\\req_row_r_lcl_reg[14] [11]));\n (* SOFT_HLUTNM = \"soft_lutpair1466\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_row_r_lcl[12]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[25] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[25] ),\n .O(\\req_row_r_lcl_reg[14] [12]));\n (* SOFT_HLUTNM = \"soft_lutpair1465\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_row_r_lcl[13]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[26] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[26] ),\n .O(\\req_row_r_lcl_reg[14] [13]));\n (* SOFT_HLUTNM = \"soft_lutpair1465\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_row_r_lcl[14]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[27] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[27] ),\n .O(\\req_row_r_lcl_reg[14] [14]));\n (* SOFT_HLUTNM = \"soft_lutpair1460\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_row_r_lcl[1]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[14] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[14] ),\n .O(\\req_row_r_lcl_reg[14] [1]));\n (* SOFT_HLUTNM = \"soft_lutpair1458\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_row_r_lcl[2]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[15] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[15] ),\n .O(\\req_row_r_lcl_reg[14] [2]));\n (* SOFT_HLUTNM = \"soft_lutpair1459\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_row_r_lcl[3]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[16] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[16] ),\n .O(\\req_row_r_lcl_reg[14] [3]));\n (* SOFT_HLUTNM = \"soft_lutpair1459\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_row_r_lcl[4]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[17] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[17] ),\n .O(\\req_row_r_lcl_reg[14] [4]));\n (* SOFT_HLUTNM = \"soft_lutpair1458\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_row_r_lcl[5]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[18] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[18] ),\n .O(\\req_row_r_lcl_reg[14] [5]));\n (* SOFT_HLUTNM = \"soft_lutpair1463\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_row_r_lcl[6]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[19] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[19] ),\n .O(\\req_row_r_lcl_reg[14] [6]));\n (* SOFT_HLUTNM = \"soft_lutpair1462\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_row_r_lcl[7]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[20] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[20] ),\n .O(\\req_row_r_lcl_reg[14] [7]));\n (* SOFT_HLUTNM = \"soft_lutpair1462\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_row_r_lcl[8]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[21] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[21] ),\n .O(\\req_row_r_lcl_reg[14] [8]));\n (* SOFT_HLUTNM = \"soft_lutpair1464\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_row_r_lcl[9]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[22] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[22] ),\n .O(\\req_row_r_lcl_reg[14] [9]));\n LUT6 #(\n .INIT(64'hD55555D540000040)) \n \\wr_req_counter.wr_req_cnt_r[3]_i_2 \n (.I0(wr_req_cnt_r[1]),\n .I1(E),\n .I2(app_en_r2),\n .I3(app_cmd_r2[0]),\n .I4(app_cmd_r2[1]),\n .I5(wr_req_cnt_r[0]),\n .O(\\wr_req_counter.wr_req_cnt_r_reg[3] ));\n (* SOFT_HLUTNM = \"soft_lutpair1453\" *) \n LUT5 #(\n .INIT(32'h96555555)) \n \\wr_req_counter.wr_req_cnt_r[3]_i_3 \n (.I0(p_0_in),\n .I1(app_cmd_r2[1]),\n .I2(app_cmd_r2[0]),\n .I3(app_en_r2),\n .I4(E),\n .O(\\wr_req_counter.wr_req_cnt_r_reg[4] ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ui_rd_data\" *) \nmodule ddr3_ifmig_7series_v4_0_ui_rd_data\n (\\not_strict_mode.app_rd_data_end_reg_0 ,\n Q,\n DOA,\n DOB,\n DOC,\n \\not_strict_mode.app_rd_data_reg[11]_0 ,\n \\not_strict_mode.app_rd_data_reg[9]_0 ,\n \\not_strict_mode.app_rd_data_reg[7]_0 ,\n \\not_strict_mode.app_rd_data_reg[17]_0 ,\n \\not_strict_mode.app_rd_data_reg[15]_0 ,\n \\not_strict_mode.app_rd_data_reg[13]_0 ,\n \\not_strict_mode.app_rd_data_reg[23]_0 ,\n \\not_strict_mode.app_rd_data_reg[21]_0 ,\n \\not_strict_mode.app_rd_data_reg[19]_0 ,\n \\not_strict_mode.app_rd_data_reg[29]_0 ,\n \\not_strict_mode.app_rd_data_reg[27]_0 ,\n \\not_strict_mode.app_rd_data_reg[25]_0 ,\n \\not_strict_mode.app_rd_data_reg[35]_0 ,\n \\not_strict_mode.app_rd_data_reg[33]_0 ,\n \\not_strict_mode.app_rd_data_reg[31]_0 ,\n \\not_strict_mode.app_rd_data_reg[41]_0 ,\n \\not_strict_mode.app_rd_data_reg[39]_0 ,\n \\not_strict_mode.app_rd_data_reg[37]_0 ,\n \\not_strict_mode.app_rd_data_reg[47]_0 ,\n \\not_strict_mode.app_rd_data_reg[45]_0 ,\n \\not_strict_mode.app_rd_data_reg[43]_0 ,\n \\not_strict_mode.app_rd_data_reg[53]_0 ,\n \\not_strict_mode.app_rd_data_reg[51]_0 ,\n \\not_strict_mode.app_rd_data_reg[49]_0 ,\n \\not_strict_mode.app_rd_data_reg[59]_0 ,\n \\not_strict_mode.app_rd_data_reg[57]_0 ,\n \\not_strict_mode.app_rd_data_reg[55]_0 ,\n \\not_strict_mode.app_rd_data_reg[65]_0 ,\n \\not_strict_mode.app_rd_data_reg[63]_0 ,\n \\not_strict_mode.app_rd_data_reg[61]_0 ,\n \\not_strict_mode.app_rd_data_reg[71]_0 ,\n \\not_strict_mode.app_rd_data_reg[69]_0 ,\n \\not_strict_mode.app_rd_data_reg[67]_0 ,\n \\not_strict_mode.app_rd_data_reg[77]_0 ,\n \\not_strict_mode.app_rd_data_reg[75]_0 ,\n \\not_strict_mode.app_rd_data_reg[73]_0 ,\n \\not_strict_mode.app_rd_data_reg[83]_0 ,\n \\not_strict_mode.app_rd_data_reg[81]_0 ,\n \\not_strict_mode.app_rd_data_reg[79]_0 ,\n \\not_strict_mode.app_rd_data_reg[89]_0 ,\n \\not_strict_mode.app_rd_data_reg[87]_0 ,\n \\not_strict_mode.app_rd_data_reg[85]_0 ,\n \\not_strict_mode.app_rd_data_reg[95]_0 ,\n \\not_strict_mode.app_rd_data_reg[93]_0 ,\n \\not_strict_mode.app_rd_data_reg[91]_0 ,\n \\not_strict_mode.app_rd_data_reg[101]_0 ,\n \\not_strict_mode.app_rd_data_reg[99]_0 ,\n \\not_strict_mode.app_rd_data_reg[97]_0 ,\n \\not_strict_mode.app_rd_data_reg[107]_0 ,\n \\not_strict_mode.app_rd_data_reg[105]_0 ,\n \\not_strict_mode.app_rd_data_reg[103]_0 ,\n \\not_strict_mode.app_rd_data_reg[113]_0 ,\n \\not_strict_mode.app_rd_data_reg[111]_0 ,\n \\not_strict_mode.app_rd_data_reg[109]_0 ,\n \\not_strict_mode.app_rd_data_reg[119]_0 ,\n \\not_strict_mode.app_rd_data_reg[117]_0 ,\n \\not_strict_mode.app_rd_data_reg[115]_0 ,\n \\not_strict_mode.app_rd_data_reg[125]_0 ,\n \\not_strict_mode.app_rd_data_reg[123]_0 ,\n \\not_strict_mode.app_rd_data_reg[121]_0 ,\n \\not_strict_mode.app_rd_data_reg[131]_0 ,\n \\not_strict_mode.app_rd_data_reg[129]_0 ,\n \\not_strict_mode.app_rd_data_reg[127]_0 ,\n \\not_strict_mode.app_rd_data_reg[137]_0 ,\n \\not_strict_mode.app_rd_data_reg[135]_0 ,\n \\not_strict_mode.app_rd_data_reg[133]_0 ,\n \\not_strict_mode.app_rd_data_reg[143]_0 ,\n \\not_strict_mode.app_rd_data_reg[141]_0 ,\n \\not_strict_mode.app_rd_data_reg[139]_0 ,\n \\not_strict_mode.app_rd_data_reg[149]_0 ,\n \\not_strict_mode.app_rd_data_reg[147]_0 ,\n \\not_strict_mode.app_rd_data_reg[145]_0 ,\n \\not_strict_mode.app_rd_data_reg[155]_0 ,\n \\not_strict_mode.app_rd_data_reg[153]_0 ,\n \\not_strict_mode.app_rd_data_reg[151]_0 ,\n \\not_strict_mode.app_rd_data_reg[161]_0 ,\n \\not_strict_mode.app_rd_data_reg[159]_0 ,\n \\not_strict_mode.app_rd_data_reg[157]_0 ,\n \\not_strict_mode.app_rd_data_reg[167]_0 ,\n \\not_strict_mode.app_rd_data_reg[165]_0 ,\n \\not_strict_mode.app_rd_data_reg[163]_0 ,\n \\not_strict_mode.app_rd_data_reg[173]_0 ,\n \\not_strict_mode.app_rd_data_reg[171]_0 ,\n \\not_strict_mode.app_rd_data_reg[169]_0 ,\n \\not_strict_mode.app_rd_data_reg[179]_0 ,\n \\not_strict_mode.app_rd_data_reg[177]_0 ,\n \\not_strict_mode.app_rd_data_reg[175]_0 ,\n \\not_strict_mode.app_rd_data_reg[185]_0 ,\n \\not_strict_mode.app_rd_data_reg[183]_0 ,\n \\not_strict_mode.app_rd_data_reg[181]_0 ,\n \\not_strict_mode.app_rd_data_reg[191]_0 ,\n \\not_strict_mode.app_rd_data_reg[189]_0 ,\n \\not_strict_mode.app_rd_data_reg[187]_0 ,\n \\not_strict_mode.app_rd_data_reg[197]_0 ,\n \\not_strict_mode.app_rd_data_reg[195]_0 ,\n \\not_strict_mode.app_rd_data_reg[193]_0 ,\n \\not_strict_mode.app_rd_data_reg[203]_0 ,\n \\not_strict_mode.app_rd_data_reg[201]_0 ,\n \\not_strict_mode.app_rd_data_reg[199]_0 ,\n \\not_strict_mode.app_rd_data_reg[209]_0 ,\n \\not_strict_mode.app_rd_data_reg[207]_0 ,\n \\not_strict_mode.app_rd_data_reg[205]_0 ,\n \\not_strict_mode.app_rd_data_reg[215]_0 ,\n \\not_strict_mode.app_rd_data_reg[213]_0 ,\n \\not_strict_mode.app_rd_data_reg[211]_0 ,\n \\not_strict_mode.app_rd_data_reg[221]_0 ,\n \\not_strict_mode.app_rd_data_reg[219]_0 ,\n \\not_strict_mode.app_rd_data_reg[217]_0 ,\n \\not_strict_mode.app_rd_data_reg[227]_0 ,\n \\not_strict_mode.app_rd_data_reg[225]_0 ,\n \\not_strict_mode.app_rd_data_reg[223]_0 ,\n \\not_strict_mode.app_rd_data_reg[233]_0 ,\n \\not_strict_mode.app_rd_data_reg[231]_0 ,\n \\not_strict_mode.app_rd_data_reg[229]_0 ,\n \\not_strict_mode.app_rd_data_reg[239]_0 ,\n \\not_strict_mode.app_rd_data_reg[237]_0 ,\n \\not_strict_mode.app_rd_data_reg[235]_0 ,\n \\not_strict_mode.app_rd_data_reg[245]_0 ,\n \\not_strict_mode.app_rd_data_reg[243]_0 ,\n \\not_strict_mode.app_rd_data_reg[241]_0 ,\n \\not_strict_mode.app_rd_data_reg[251]_0 ,\n \\not_strict_mode.app_rd_data_reg[249]_0 ,\n \\not_strict_mode.app_rd_data_reg[247]_0 ,\n \\not_strict_mode.app_rd_data_reg[255]_0 ,\n \\not_strict_mode.app_rd_data_reg[253]_0 ,\n \\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ,\n app_rd_data_valid,\n D,\n \\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 ,\n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 ,\n \\rd_buf_indx.ram_init_done_r_lcl_reg_0 ,\n ADDRD,\n pointer_wr_data,\n \\s_axi_rdata[255] ,\n CLK,\n rd_buf_we,\n DIA,\n DIB,\n DIC,\n \\read_fifo.fifo_out_data_r_reg[7] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ,\n app_rd_data_end_ns,\n rd_accepted,\n reset_reg,\n \\not_strict_mode.occupied_counter.occ_cnt_r_reg[1]_0 ,\n bypass__0,\n \\read_data_indx.rd_data_indx_r_reg[3] ,\n \\cmd_pipe_plus.wr_data_addr_reg[3] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 );\n output [0:0]\\not_strict_mode.app_rd_data_end_reg_0 ;\n output [4:0]Q;\n output [1:0]DOA;\n output [1:0]DOB;\n output [1:0]DOC;\n output [1:0]\\not_strict_mode.app_rd_data_reg[11]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[9]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[7]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[17]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[15]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[13]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[23]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[21]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[19]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[29]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[27]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[25]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[35]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[33]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[31]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[41]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[39]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[37]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[47]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[45]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[43]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[53]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[51]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[49]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[59]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[57]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[55]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[65]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[63]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[61]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[71]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[69]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[67]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[77]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[75]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[73]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[83]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[81]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[79]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[89]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[87]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[85]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[95]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[93]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[91]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[101]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[99]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[97]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[107]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[105]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[103]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[113]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[111]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[109]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[119]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[117]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[115]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[125]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[123]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[121]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[131]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[129]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[127]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[137]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[135]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[133]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[143]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[141]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[139]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[149]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[147]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[145]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[155]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[153]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[151]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[161]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[159]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[157]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[167]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[165]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[163]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[173]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[171]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[169]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[179]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[177]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[175]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[185]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[183]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[181]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[191]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[189]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[187]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[197]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[195]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[193]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[203]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[201]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[199]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[209]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[207]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[205]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[215]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[213]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[211]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[221]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[219]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[217]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[227]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[225]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[223]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[233]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[231]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[229]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[239]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[237]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[235]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[245]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[243]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[241]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[251]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[249]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[247]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[255]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[253]_0 ;\n output \\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ;\n output app_rd_data_valid;\n output [0:0]D;\n output [1:0]\\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 ;\n output [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 ;\n output \\rd_buf_indx.ram_init_done_r_lcl_reg_0 ;\n output [3:0]ADDRD;\n output [3:0]pointer_wr_data;\n output [255:0]\\s_axi_rdata[255] ;\n input CLK;\n input rd_buf_we;\n input [1:0]DIA;\n input [1:0]DIB;\n input [1:0]DIC;\n input [6:0]\\read_fifo.fifo_out_data_r_reg[7] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;\n input app_rd_data_end_ns;\n input rd_accepted;\n input reset_reg;\n input \\not_strict_mode.occupied_counter.occ_cnt_r_reg[1]_0 ;\n input bypass__0;\n input [3:0]\\read_data_indx.rd_data_indx_r_reg[3] ;\n input [3:0]\\cmd_pipe_plus.wr_data_addr_reg[3] ;\n input [255:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ;\n\n wire [3:0]ADDRD;\n wire CLK;\n wire [0:0]D;\n wire [1:0]DIA;\n wire [1:0]DIB;\n wire [1:0]DIC;\n wire [1:0]DOA;\n wire [1:0]DOB;\n wire [1:0]DOC;\n wire [4:0]Q;\n wire app_rd_data_end;\n wire app_rd_data_end_ns;\n wire app_rd_data_valid;\n wire app_rd_data_valid_copy;\n wire app_rd_data_valid_ns;\n wire bypass__0;\n wire [3:0]\\cmd_pipe_plus.wr_data_addr_reg[3] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ;\n wire [255:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ;\n wire [0:0]\\not_strict_mode.app_rd_data_end_reg_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[101]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[103]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[105]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[107]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[109]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[111]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[113]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[115]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[117]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[119]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[11]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[121]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[123]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[125]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[127]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[129]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[131]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[133]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[135]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[137]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[139]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[13]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[141]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[143]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[145]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[147]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[149]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[151]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[153]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[155]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[157]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[159]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[15]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[161]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[163]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[165]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[167]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[169]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[171]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[173]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[175]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[177]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[179]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[17]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[181]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[183]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[185]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[187]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[189]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[191]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[193]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[195]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[197]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[199]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[19]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[201]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[203]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[205]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[207]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[209]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[211]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[213]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[215]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[217]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[219]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[21]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[221]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[223]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[225]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[227]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[229]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[231]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[233]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[235]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[237]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[239]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[23]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[241]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[243]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[245]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[247]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[249]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[251]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[253]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[255]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[25]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[27]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[29]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[31]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[33]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[35]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[37]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[39]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[41]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[43]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[45]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[47]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[49]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[51]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[53]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[55]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[57]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[59]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[61]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[63]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[65]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[67]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[69]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[71]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[73]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[75]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[77]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[79]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[7]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[81]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[83]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[85]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[87]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[89]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[91]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[93]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[95]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[97]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[99]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[9]_0 ;\n wire [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 ;\n wire \\not_strict_mode.occupied_counter.occ_cnt_r[0]_i_1_n_0 ;\n wire \\not_strict_mode.occupied_counter.occ_cnt_r[1]_i_1_n_0 ;\n wire \\not_strict_mode.occupied_counter.occ_cnt_r[2]_i_1_n_0 ;\n wire \\not_strict_mode.occupied_counter.occ_cnt_r[3]_i_1_n_0 ;\n wire \\not_strict_mode.occupied_counter.occ_cnt_r[4]_i_1_n_0 ;\n wire \\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_2_n_0 ;\n wire \\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_3_n_0 ;\n wire \\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_4_n_0 ;\n wire \\not_strict_mode.occupied_counter.occ_cnt_r_reg[1]_0 ;\n wire [1:0]\\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 ;\n wire \\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ;\n wire [5:2]occ_cnt_r;\n wire [4:0]p_0_in__2;\n wire [3:0]pointer_wr_data;\n wire ram_init_done_ns;\n wire rd_accepted;\n wire \\rd_buf_indx.ram_init_done_r_lcl_i_2_n_0 ;\n wire \\rd_buf_indx.ram_init_done_r_lcl_reg_0 ;\n wire \\rd_buf_indx.rd_buf_indx_r[1]_i_2_n_0 ;\n wire \\rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0 ;\n wire \\rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ;\n (* RTL_KEEP = \"true\" *) (* syn_keep = \"true\" *) wire [4:0]rd_buf_indx_copy_r;\n wire [5:0]rd_buf_indx_ns;\n wire rd_buf_we;\n wire rd_buf_we_r1;\n wire [0:0]rd_status;\n wire [3:0]\\read_data_indx.rd_data_indx_r_reg[3] ;\n wire [6:0]\\read_fifo.fifo_out_data_r_reg[7] ;\n wire reset_reg;\n wire [255:0]\\s_axi_rdata[255] ;\n wire [4:0]status_ram_wr_addr_ns;\n wire [4:0]status_ram_wr_addr_r;\n wire [1:0]status_ram_wr_data_ns;\n wire [1:0]status_ram_wr_data_r;\n wire wr_status;\n wire wr_status_r1;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_DOA_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.status_ram.RAM32M0_DOB_UNCONNECTED ;\n wire [1:1]\\NLW_not_strict_mode.status_ram.RAM32M0_DOC_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.status_ram.RAM32M0_DOD_UNCONNECTED ;\n\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_end_reg \n (.C(CLK),\n .CE(1'b1),\n .D(app_rd_data_end_ns),\n .Q(app_rd_data_end),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [0]),\n .Q(\\s_axi_rdata[255] [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[100] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [100]),\n .Q(\\s_axi_rdata[255] [100]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[101] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [101]),\n .Q(\\s_axi_rdata[255] [101]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[102] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [102]),\n .Q(\\s_axi_rdata[255] [102]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[103] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [103]),\n .Q(\\s_axi_rdata[255] [103]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[104] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [104]),\n .Q(\\s_axi_rdata[255] [104]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[105] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [105]),\n .Q(\\s_axi_rdata[255] [105]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[106] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [106]),\n .Q(\\s_axi_rdata[255] [106]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[107] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [107]),\n .Q(\\s_axi_rdata[255] [107]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[108] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [108]),\n .Q(\\s_axi_rdata[255] [108]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[109] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [109]),\n .Q(\\s_axi_rdata[255] [109]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [10]),\n .Q(\\s_axi_rdata[255] [10]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[110] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [110]),\n .Q(\\s_axi_rdata[255] [110]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[111] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [111]),\n .Q(\\s_axi_rdata[255] [111]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[112] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [112]),\n .Q(\\s_axi_rdata[255] [112]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[113] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [113]),\n .Q(\\s_axi_rdata[255] [113]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[114] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [114]),\n .Q(\\s_axi_rdata[255] [114]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[115] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [115]),\n .Q(\\s_axi_rdata[255] [115]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[116] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [116]),\n .Q(\\s_axi_rdata[255] [116]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[117] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [117]),\n .Q(\\s_axi_rdata[255] [117]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[118] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [118]),\n .Q(\\s_axi_rdata[255] [118]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[119] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [119]),\n .Q(\\s_axi_rdata[255] [119]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [11]),\n .Q(\\s_axi_rdata[255] [11]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[120] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [120]),\n .Q(\\s_axi_rdata[255] [120]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[121] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [121]),\n .Q(\\s_axi_rdata[255] [121]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[122] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [122]),\n .Q(\\s_axi_rdata[255] [122]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[123] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [123]),\n .Q(\\s_axi_rdata[255] [123]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[124] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [124]),\n .Q(\\s_axi_rdata[255] [124]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[125] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [125]),\n .Q(\\s_axi_rdata[255] [125]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[126] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [126]),\n .Q(\\s_axi_rdata[255] [126]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[127] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [127]),\n .Q(\\s_axi_rdata[255] [127]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[128] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [128]),\n .Q(\\s_axi_rdata[255] [128]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[129] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [129]),\n .Q(\\s_axi_rdata[255] [129]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[12] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [12]),\n .Q(\\s_axi_rdata[255] [12]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[130] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [130]),\n .Q(\\s_axi_rdata[255] [130]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[131] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [131]),\n .Q(\\s_axi_rdata[255] [131]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[132] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [132]),\n .Q(\\s_axi_rdata[255] [132]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[133] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [133]),\n .Q(\\s_axi_rdata[255] [133]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[134] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [134]),\n .Q(\\s_axi_rdata[255] [134]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[135] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [135]),\n .Q(\\s_axi_rdata[255] [135]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[136] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [136]),\n .Q(\\s_axi_rdata[255] [136]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[137] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [137]),\n .Q(\\s_axi_rdata[255] [137]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[138] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [138]),\n .Q(\\s_axi_rdata[255] [138]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[139] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [139]),\n .Q(\\s_axi_rdata[255] [139]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[13] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [13]),\n .Q(\\s_axi_rdata[255] [13]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[140] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [140]),\n .Q(\\s_axi_rdata[255] [140]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[141] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [141]),\n .Q(\\s_axi_rdata[255] [141]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[142] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [142]),\n .Q(\\s_axi_rdata[255] [142]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[143] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [143]),\n .Q(\\s_axi_rdata[255] [143]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[144] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [144]),\n .Q(\\s_axi_rdata[255] [144]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[145] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [145]),\n .Q(\\s_axi_rdata[255] [145]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[146] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [146]),\n .Q(\\s_axi_rdata[255] [146]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[147] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [147]),\n .Q(\\s_axi_rdata[255] [147]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[148] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [148]),\n .Q(\\s_axi_rdata[255] [148]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[149] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [149]),\n .Q(\\s_axi_rdata[255] [149]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[14] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [14]),\n .Q(\\s_axi_rdata[255] [14]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[150] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [150]),\n .Q(\\s_axi_rdata[255] [150]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[151] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [151]),\n .Q(\\s_axi_rdata[255] [151]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[152] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [152]),\n .Q(\\s_axi_rdata[255] [152]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[153] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [153]),\n .Q(\\s_axi_rdata[255] [153]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[154] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [154]),\n .Q(\\s_axi_rdata[255] [154]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[155] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [155]),\n .Q(\\s_axi_rdata[255] [155]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[156] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [156]),\n .Q(\\s_axi_rdata[255] [156]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[157] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [157]),\n .Q(\\s_axi_rdata[255] [157]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[158] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [158]),\n .Q(\\s_axi_rdata[255] [158]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[159] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [159]),\n .Q(\\s_axi_rdata[255] [159]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[15] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [15]),\n .Q(\\s_axi_rdata[255] [15]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[160] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [160]),\n .Q(\\s_axi_rdata[255] [160]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[161] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [161]),\n .Q(\\s_axi_rdata[255] [161]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[162] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [162]),\n .Q(\\s_axi_rdata[255] [162]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[163] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [163]),\n .Q(\\s_axi_rdata[255] [163]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[164] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [164]),\n .Q(\\s_axi_rdata[255] [164]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[165] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [165]),\n .Q(\\s_axi_rdata[255] [165]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[166] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [166]),\n .Q(\\s_axi_rdata[255] [166]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[167] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [167]),\n .Q(\\s_axi_rdata[255] [167]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[168] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [168]),\n .Q(\\s_axi_rdata[255] [168]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[169] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [169]),\n .Q(\\s_axi_rdata[255] [169]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[16] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [16]),\n .Q(\\s_axi_rdata[255] [16]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[170] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [170]),\n .Q(\\s_axi_rdata[255] [170]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[171] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [171]),\n .Q(\\s_axi_rdata[255] [171]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[172] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [172]),\n .Q(\\s_axi_rdata[255] [172]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[173] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [173]),\n .Q(\\s_axi_rdata[255] [173]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[174] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [174]),\n .Q(\\s_axi_rdata[255] [174]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[175] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [175]),\n .Q(\\s_axi_rdata[255] [175]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[176] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [176]),\n .Q(\\s_axi_rdata[255] [176]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[177] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [177]),\n .Q(\\s_axi_rdata[255] [177]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[178] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [178]),\n .Q(\\s_axi_rdata[255] [178]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[179] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [179]),\n .Q(\\s_axi_rdata[255] [179]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[17] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [17]),\n .Q(\\s_axi_rdata[255] [17]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[180] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [180]),\n .Q(\\s_axi_rdata[255] [180]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[181] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [181]),\n .Q(\\s_axi_rdata[255] [181]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[182] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [182]),\n .Q(\\s_axi_rdata[255] [182]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[183] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [183]),\n .Q(\\s_axi_rdata[255] [183]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[184] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [184]),\n .Q(\\s_axi_rdata[255] [184]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[185] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [185]),\n .Q(\\s_axi_rdata[255] [185]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[186] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [186]),\n .Q(\\s_axi_rdata[255] [186]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[187] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [187]),\n .Q(\\s_axi_rdata[255] [187]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[188] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [188]),\n .Q(\\s_axi_rdata[255] [188]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[189] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [189]),\n .Q(\\s_axi_rdata[255] [189]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[18] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [18]),\n .Q(\\s_axi_rdata[255] [18]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[190] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [190]),\n .Q(\\s_axi_rdata[255] [190]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[191] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [191]),\n .Q(\\s_axi_rdata[255] [191]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[192] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [192]),\n .Q(\\s_axi_rdata[255] [192]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[193] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [193]),\n .Q(\\s_axi_rdata[255] [193]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[194] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [194]),\n .Q(\\s_axi_rdata[255] [194]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[195] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [195]),\n .Q(\\s_axi_rdata[255] [195]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[196] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [196]),\n .Q(\\s_axi_rdata[255] [196]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[197] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [197]),\n .Q(\\s_axi_rdata[255] [197]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[198] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [198]),\n .Q(\\s_axi_rdata[255] [198]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[199] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [199]),\n .Q(\\s_axi_rdata[255] [199]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[19] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [19]),\n .Q(\\s_axi_rdata[255] [19]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [1]),\n .Q(\\s_axi_rdata[255] [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[200] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [200]),\n .Q(\\s_axi_rdata[255] [200]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[201] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [201]),\n .Q(\\s_axi_rdata[255] [201]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[202] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [202]),\n .Q(\\s_axi_rdata[255] [202]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[203] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [203]),\n .Q(\\s_axi_rdata[255] [203]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[204] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [204]),\n .Q(\\s_axi_rdata[255] [204]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[205] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [205]),\n .Q(\\s_axi_rdata[255] [205]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[206] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [206]),\n .Q(\\s_axi_rdata[255] [206]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[207] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [207]),\n .Q(\\s_axi_rdata[255] [207]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[208] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [208]),\n .Q(\\s_axi_rdata[255] [208]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[209] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [209]),\n .Q(\\s_axi_rdata[255] [209]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[20] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [20]),\n .Q(\\s_axi_rdata[255] [20]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[210] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [210]),\n .Q(\\s_axi_rdata[255] [210]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[211] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [211]),\n .Q(\\s_axi_rdata[255] [211]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[212] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [212]),\n .Q(\\s_axi_rdata[255] [212]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[213] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [213]),\n .Q(\\s_axi_rdata[255] [213]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[214] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [214]),\n .Q(\\s_axi_rdata[255] [214]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[215] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [215]),\n .Q(\\s_axi_rdata[255] [215]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[216] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [216]),\n .Q(\\s_axi_rdata[255] [216]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[217] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [217]),\n .Q(\\s_axi_rdata[255] [217]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[218] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [218]),\n .Q(\\s_axi_rdata[255] [218]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[219] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [219]),\n .Q(\\s_axi_rdata[255] [219]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[21] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [21]),\n .Q(\\s_axi_rdata[255] [21]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[220] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [220]),\n .Q(\\s_axi_rdata[255] [220]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[221] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [221]),\n .Q(\\s_axi_rdata[255] [221]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[222] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [222]),\n .Q(\\s_axi_rdata[255] [222]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[223] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [223]),\n .Q(\\s_axi_rdata[255] [223]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[224] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [224]),\n .Q(\\s_axi_rdata[255] [224]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[225] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [225]),\n .Q(\\s_axi_rdata[255] [225]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[226] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [226]),\n .Q(\\s_axi_rdata[255] [226]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[227] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [227]),\n .Q(\\s_axi_rdata[255] [227]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[228] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [228]),\n .Q(\\s_axi_rdata[255] [228]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[229] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [229]),\n .Q(\\s_axi_rdata[255] [229]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[22] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [22]),\n .Q(\\s_axi_rdata[255] [22]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[230] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [230]),\n .Q(\\s_axi_rdata[255] [230]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[231] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [231]),\n .Q(\\s_axi_rdata[255] [231]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[232] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [232]),\n .Q(\\s_axi_rdata[255] [232]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[233] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [233]),\n .Q(\\s_axi_rdata[255] [233]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[234] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [234]),\n .Q(\\s_axi_rdata[255] [234]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[235] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [235]),\n .Q(\\s_axi_rdata[255] [235]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[236] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [236]),\n .Q(\\s_axi_rdata[255] [236]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[237] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [237]),\n .Q(\\s_axi_rdata[255] [237]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[238] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [238]),\n .Q(\\s_axi_rdata[255] [238]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[239] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [239]),\n .Q(\\s_axi_rdata[255] [239]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[23] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [23]),\n .Q(\\s_axi_rdata[255] [23]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[240] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [240]),\n .Q(\\s_axi_rdata[255] [240]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[241] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [241]),\n .Q(\\s_axi_rdata[255] [241]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[242] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [242]),\n .Q(\\s_axi_rdata[255] [242]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[243] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [243]),\n .Q(\\s_axi_rdata[255] [243]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[244] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [244]),\n .Q(\\s_axi_rdata[255] [244]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[245] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [245]),\n .Q(\\s_axi_rdata[255] [245]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[246] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [246]),\n .Q(\\s_axi_rdata[255] [246]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[247] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [247]),\n .Q(\\s_axi_rdata[255] [247]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[248] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [248]),\n .Q(\\s_axi_rdata[255] [248]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[249] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [249]),\n .Q(\\s_axi_rdata[255] [249]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[24] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [24]),\n .Q(\\s_axi_rdata[255] [24]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[250] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [250]),\n .Q(\\s_axi_rdata[255] [250]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[251] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [251]),\n .Q(\\s_axi_rdata[255] [251]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[252] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [252]),\n .Q(\\s_axi_rdata[255] [252]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[253] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [253]),\n .Q(\\s_axi_rdata[255] [253]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[254] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [254]),\n .Q(\\s_axi_rdata[255] [254]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[255] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [255]),\n .Q(\\s_axi_rdata[255] [255]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[25] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [25]),\n .Q(\\s_axi_rdata[255] [25]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[26] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [26]),\n .Q(\\s_axi_rdata[255] [26]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[27] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [27]),\n .Q(\\s_axi_rdata[255] [27]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[28] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [28]),\n .Q(\\s_axi_rdata[255] [28]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[29] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [29]),\n .Q(\\s_axi_rdata[255] [29]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [2]),\n .Q(\\s_axi_rdata[255] [2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[30] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [30]),\n .Q(\\s_axi_rdata[255] [30]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[31] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [31]),\n .Q(\\s_axi_rdata[255] [31]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[32] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [32]),\n .Q(\\s_axi_rdata[255] [32]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[33] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [33]),\n .Q(\\s_axi_rdata[255] [33]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[34] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [34]),\n .Q(\\s_axi_rdata[255] [34]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[35] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [35]),\n .Q(\\s_axi_rdata[255] [35]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[36] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [36]),\n .Q(\\s_axi_rdata[255] [36]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[37] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [37]),\n .Q(\\s_axi_rdata[255] [37]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[38] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [38]),\n .Q(\\s_axi_rdata[255] [38]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[39] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [39]),\n .Q(\\s_axi_rdata[255] [39]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [3]),\n .Q(\\s_axi_rdata[255] [3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[40] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [40]),\n .Q(\\s_axi_rdata[255] [40]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[41] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [41]),\n .Q(\\s_axi_rdata[255] [41]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[42] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [42]),\n .Q(\\s_axi_rdata[255] [42]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[43] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [43]),\n .Q(\\s_axi_rdata[255] [43]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[44] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [44]),\n .Q(\\s_axi_rdata[255] [44]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[45] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [45]),\n .Q(\\s_axi_rdata[255] [45]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[46] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [46]),\n .Q(\\s_axi_rdata[255] [46]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[47] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [47]),\n .Q(\\s_axi_rdata[255] [47]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[48] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [48]),\n .Q(\\s_axi_rdata[255] [48]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[49] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [49]),\n .Q(\\s_axi_rdata[255] [49]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [4]),\n .Q(\\s_axi_rdata[255] [4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[50] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [50]),\n .Q(\\s_axi_rdata[255] [50]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[51] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [51]),\n .Q(\\s_axi_rdata[255] [51]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[52] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [52]),\n .Q(\\s_axi_rdata[255] [52]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[53] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [53]),\n .Q(\\s_axi_rdata[255] [53]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[54] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [54]),\n .Q(\\s_axi_rdata[255] [54]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[55] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [55]),\n .Q(\\s_axi_rdata[255] [55]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[56] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [56]),\n .Q(\\s_axi_rdata[255] [56]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[57] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [57]),\n .Q(\\s_axi_rdata[255] [57]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[58] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [58]),\n .Q(\\s_axi_rdata[255] [58]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[59] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [59]),\n .Q(\\s_axi_rdata[255] [59]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [5]),\n .Q(\\s_axi_rdata[255] [5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[60] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [60]),\n .Q(\\s_axi_rdata[255] [60]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[61] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [61]),\n .Q(\\s_axi_rdata[255] [61]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[62] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [62]),\n .Q(\\s_axi_rdata[255] [62]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[63] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [63]),\n .Q(\\s_axi_rdata[255] [63]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[64] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [64]),\n .Q(\\s_axi_rdata[255] [64]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[65] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [65]),\n .Q(\\s_axi_rdata[255] [65]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[66] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [66]),\n .Q(\\s_axi_rdata[255] [66]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[67] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [67]),\n .Q(\\s_axi_rdata[255] [67]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[68] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [68]),\n .Q(\\s_axi_rdata[255] [68]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[69] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [69]),\n .Q(\\s_axi_rdata[255] [69]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [6]),\n .Q(\\s_axi_rdata[255] [6]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[70] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [70]),\n .Q(\\s_axi_rdata[255] [70]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[71] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [71]),\n .Q(\\s_axi_rdata[255] [71]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[72] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [72]),\n .Q(\\s_axi_rdata[255] [72]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[73] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [73]),\n .Q(\\s_axi_rdata[255] [73]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[74] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [74]),\n .Q(\\s_axi_rdata[255] [74]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[75] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [75]),\n .Q(\\s_axi_rdata[255] [75]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[76] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [76]),\n .Q(\\s_axi_rdata[255] [76]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[77] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [77]),\n .Q(\\s_axi_rdata[255] [77]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[78] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [78]),\n .Q(\\s_axi_rdata[255] [78]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[79] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [79]),\n .Q(\\s_axi_rdata[255] [79]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [7]),\n .Q(\\s_axi_rdata[255] [7]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[80] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [80]),\n .Q(\\s_axi_rdata[255] [80]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[81] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [81]),\n .Q(\\s_axi_rdata[255] [81]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[82] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [82]),\n .Q(\\s_axi_rdata[255] [82]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[83] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [83]),\n .Q(\\s_axi_rdata[255] [83]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[84] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [84]),\n .Q(\\s_axi_rdata[255] [84]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[85] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [85]),\n .Q(\\s_axi_rdata[255] [85]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[86] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [86]),\n .Q(\\s_axi_rdata[255] [86]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[87] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [87]),\n .Q(\\s_axi_rdata[255] [87]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[88] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [88]),\n .Q(\\s_axi_rdata[255] [88]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[89] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [89]),\n .Q(\\s_axi_rdata[255] [89]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [8]),\n .Q(\\s_axi_rdata[255] [8]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[90] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [90]),\n .Q(\\s_axi_rdata[255] [90]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[91] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [91]),\n .Q(\\s_axi_rdata[255] [91]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[92] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [92]),\n .Q(\\s_axi_rdata[255] [92]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[93] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [93]),\n .Q(\\s_axi_rdata[255] [93]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[94] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [94]),\n .Q(\\s_axi_rdata[255] [94]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[95] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [95]),\n .Q(\\s_axi_rdata[255] [95]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[96] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [96]),\n .Q(\\s_axi_rdata[255] [96]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[97] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [97]),\n .Q(\\s_axi_rdata[255] [97]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[98] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [98]),\n .Q(\\s_axi_rdata[255] [98]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[99] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [99]),\n .Q(\\s_axi_rdata[255] [99]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [9]),\n .Q(\\s_axi_rdata[255] [9]),\n .R(1'b0));\n (* equivalent_register_removal = \"no\" *) \n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_valid_copy_reg \n (.C(CLK),\n .CE(1'b1),\n .D(app_rd_data_valid_ns),\n .Q(app_rd_data_valid_copy),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1472\" *) \n LUT4 #(\n .INIT(16'hEB00)) \n \\not_strict_mode.app_rd_data_valid_i_1 \n (.I0(bypass__0),\n .I1(\\rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ),\n .I2(rd_status),\n .I3(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .O(app_rd_data_valid_ns));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.app_rd_data_valid_reg \n (.C(CLK),\n .CE(1'b1),\n .D(app_rd_data_valid_ns),\n .Q(app_rd_data_valid),\n .R(1'b0));\n LUT1 #(\n .INIT(2'h1)) \n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[0]_i_1 \n (.I0(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [0]),\n .O(p_0_in__2[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1478\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[1]_i_1 \n (.I0(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [0]),\n .I1(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [1]),\n .O(p_0_in__2[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1478\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[2]_i_1 \n (.I0(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [0]),\n .I1(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [1]),\n .I2(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [2]),\n .O(p_0_in__2[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1473\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[3]_i_1 \n (.I0(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [1]),\n .I1(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [0]),\n .I2(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [2]),\n .I3(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [3]),\n .O(p_0_in__2[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1473\" *) \n LUT5 #(\n .INIT(32'h7FFF8000)) \n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[4]_i_2 \n (.I0(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [2]),\n .I1(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [0]),\n .I2(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [1]),\n .I3(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [3]),\n .I4(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [4]),\n .O(p_0_in__2[4]));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[0] \n (.C(CLK),\n .CE(rd_accepted),\n .D(p_0_in__2[0]),\n .Q(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [0]),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[1] \n (.C(CLK),\n .CE(rd_accepted),\n .D(p_0_in__2[1]),\n .Q(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [1]),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[2] \n (.C(CLK),\n .CE(rd_accepted),\n .D(p_0_in__2[2]),\n .Q(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [2]),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[3] \n (.C(CLK),\n .CE(rd_accepted),\n .D(p_0_in__2[3]),\n .Q(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [3]),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] \n (.C(CLK),\n .CE(rd_accepted),\n .D(p_0_in__2[4]),\n .Q(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [4]),\n .R(reset_reg));\n (* SOFT_HLUTNM = \"soft_lutpair1474\" *) \n LUT5 #(\n .INIT(32'h00009666)) \n \\not_strict_mode.occupied_counter.occ_cnt_r[0]_i_1 \n (.I0(\\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [0]),\n .I1(rd_accepted),\n .I2(app_rd_data_valid_copy),\n .I3(app_rd_data_end),\n .I4(reset_reg),\n .O(\\not_strict_mode.occupied_counter.occ_cnt_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00000000C96C6C6C)) \n \\not_strict_mode.occupied_counter.occ_cnt_r[1]_i_1 \n (.I0(\\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [0]),\n .I1(\\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [1]),\n .I2(rd_accepted),\n .I3(app_rd_data_valid_copy),\n .I4(app_rd_data_end),\n .I5(reset_reg),\n .O(\\not_strict_mode.occupied_counter.occ_cnt_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF81007E008100)) \n \\not_strict_mode.occupied_counter.occ_cnt_r[2]_i_1 \n (.I0(\\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [0]),\n .I1(rd_accepted),\n .I2(\\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [1]),\n .I3(\\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_3_n_0 ),\n .I4(occ_cnt_r[2]),\n .I5(\\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_4_n_0 ),\n .O(\\not_strict_mode.occupied_counter.occ_cnt_r[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF81007E008100)) \n \\not_strict_mode.occupied_counter.occ_cnt_r[3]_i_1 \n (.I0(occ_cnt_r[2]),\n .I1(\\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [1]),\n .I2(\\not_strict_mode.occupied_counter.occ_cnt_r_reg[1]_0 ),\n .I3(\\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_3_n_0 ),\n .I4(occ_cnt_r[3]),\n .I5(\\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_4_n_0 ),\n .O(\\not_strict_mode.occupied_counter.occ_cnt_r[3]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFF906090)) \n \\not_strict_mode.occupied_counter.occ_cnt_r[4]_i_1 \n (.I0(occ_cnt_r[3]),\n .I1(\\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_2_n_0 ),\n .I2(\\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_3_n_0 ),\n .I3(occ_cnt_r[4]),\n .I4(\\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_4_n_0 ),\n .O(\\not_strict_mode.occupied_counter.occ_cnt_r[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF81007E008100)) \n \\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_1 \n (.I0(occ_cnt_r[4]),\n .I1(occ_cnt_r[3]),\n .I2(\\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_2_n_0 ),\n .I3(\\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_3_n_0 ),\n .I4(occ_cnt_r[5]),\n .I5(\\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_4_n_0 ),\n .O(D));\n LUT5 #(\n .INIT(32'h8000FFFE)) \n \\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_2 \n (.I0(\\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [1]),\n .I1(rd_accepted),\n .I2(\\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [0]),\n .I3(occ_cnt_r[2]),\n .I4(occ_cnt_r[3]),\n .O(\\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1474\" *) \n LUT4 #(\n .INIT(16'h006A)) \n \\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_3 \n (.I0(rd_accepted),\n .I1(app_rd_data_valid_copy),\n .I2(app_rd_data_end),\n .I3(reset_reg),\n .O(\\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1475\" *) \n LUT4 #(\n .INIT(16'h0095)) \n \\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_4 \n (.I0(rd_accepted),\n .I1(app_rd_data_valid_copy),\n .I2(app_rd_data_end),\n .I3(reset_reg),\n .O(\\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_4_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.occupied_counter.occ_cnt_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\not_strict_mode.occupied_counter.occ_cnt_r[0]_i_1_n_0 ),\n .Q(\\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.occupied_counter.occ_cnt_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\not_strict_mode.occupied_counter.occ_cnt_r[1]_i_1_n_0 ),\n .Q(\\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.occupied_counter.occ_cnt_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\not_strict_mode.occupied_counter.occ_cnt_r[2]_i_1_n_0 ),\n .Q(occ_cnt_r[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.occupied_counter.occ_cnt_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\not_strict_mode.occupied_counter.occ_cnt_r[3]_i_1_n_0 ),\n .Q(occ_cnt_r[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.occupied_counter.occ_cnt_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\not_strict_mode.occupied_counter.occ_cnt_r[4]_i_1_n_0 ),\n .Q(occ_cnt_r[4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.occupied_counter.occ_cnt_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(D),\n .Q(occ_cnt_r[5]),\n .R(1'b0));\n (* KEEP = \"yes\" *) \n (* syn_keep = \"true\" *) \n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_buf_indx_ns[0]),\n .Q(rd_buf_indx_copy_r[0]),\n .R(1'b0));\n (* KEEP = \"yes\" *) \n (* syn_keep = \"true\" *) \n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_buf_indx_ns[1]),\n .Q(rd_buf_indx_copy_r[1]),\n .R(1'b0));\n (* KEEP = \"yes\" *) \n (* syn_keep = \"true\" *) \n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_buf_indx_ns[2]),\n .Q(rd_buf_indx_copy_r[2]),\n .R(1'b0));\n (* KEEP = \"yes\" *) \n (* syn_keep = \"true\" *) \n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_buf_indx_ns[3]),\n .Q(rd_buf_indx_copy_r[3]),\n .R(1'b0));\n (* KEEP = \"yes\" *) \n (* syn_keep = \"true\" *) \n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_buf_indx_ns[4]),\n .Q(rd_buf_indx_copy_r[4]),\n .R(1'b0));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(DIA),\n .DIB(DIB),\n .DIC(DIC),\n .DID({1'b0,1'b0}),\n .DOA(DOA),\n .DOB(DOB),\n .DOC(DOC),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[65]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[63]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[61]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[71]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[69]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[67]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[77]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[75]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[73]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[83]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[81]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[79]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[89]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[87]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[85]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[95]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[93]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[91]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[101]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[99]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[97]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[107]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[105]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[103]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[113]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[111]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[109]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[119]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[117]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[115]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[11]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[9]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[7]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[125]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[123]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[121]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[131]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[129]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[127]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[137]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[135]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[133]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[143]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[141]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[139]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[149]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[147]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[145]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[155]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[153]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[151]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[161]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[159]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[157]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[167]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[165]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[163]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[173]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[171]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[169]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[179]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[177]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[175]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[17]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[15]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[13]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[185]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[183]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[181]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[191]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[189]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[187]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[197]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[195]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[193]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[203]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[201]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[199]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[209]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[207]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[205]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[215]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[213]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[211]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[221]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[219]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[217]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[227]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[225]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[223]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[233]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[231]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[229]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[239]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[237]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[235]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[23]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[21]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[19]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[245]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[243]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[241]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[251]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[249]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[247]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA({1'b0,1'b0}),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ),\n .DID({1'b0,1'b0}),\n .DOA(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_DOA_UNCONNECTED [1:0]),\n .DOB(\\not_strict_mode.app_rd_data_reg[255]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[253]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[29]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[27]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[25]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[35]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[33]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[31]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[41]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[39]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[37]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[47]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[45]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[43]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[53]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[51]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[49]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[59]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[57]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[55]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.status_ram.RAM32M0 \n (.ADDRA(Q),\n .ADDRB({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .ADDRC(status_ram_wr_addr_ns),\n .ADDRD(status_ram_wr_addr_r),\n .DIA(status_ram_wr_data_r),\n .DIB({1'b0,1'b0}),\n .DIC(status_ram_wr_data_r),\n .DID(status_ram_wr_data_r),\n .DOA({\\not_strict_mode.app_rd_data_end_reg_0 ,rd_status}),\n .DOB(\\NLW_not_strict_mode.status_ram.RAM32M0_DOB_UNCONNECTED [1:0]),\n .DOC({\\NLW_not_strict_mode.status_ram.RAM32M0_DOC_UNCONNECTED [1],wr_status}),\n .DOD(\\NLW_not_strict_mode.status_ram.RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we_r1));\n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.status_ram.RAM32M0_i_1 \n (.I0(\\read_fifo.fifo_out_data_r_reg[7] [5]),\n .I1(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I2(Q[4]),\n .O(status_ram_wr_addr_ns[4]));\n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.status_ram.RAM32M0_i_2 \n (.I0(\\read_fifo.fifo_out_data_r_reg[7] [4]),\n .I1(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I2(Q[3]),\n .O(status_ram_wr_addr_ns[3]));\n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.status_ram.RAM32M0_i_3 \n (.I0(\\read_fifo.fifo_out_data_r_reg[7] [3]),\n .I1(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I2(Q[2]),\n .O(status_ram_wr_addr_ns[2]));\n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.status_ram.RAM32M0_i_4 \n (.I0(\\read_fifo.fifo_out_data_r_reg[7] [2]),\n .I1(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I2(Q[1]),\n .O(status_ram_wr_addr_ns[1]));\n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.status_ram.RAM32M0_i_5 \n (.I0(\\read_fifo.fifo_out_data_r_reg[7] [1]),\n .I1(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I2(Q[0]),\n .O(status_ram_wr_addr_ns[0]));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.status_ram.rd_buf_we_r1_reg \n (.C(CLK),\n .CE(1'b1),\n .D(rd_buf_we),\n .Q(rd_buf_we_r1),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.status_ram.status_ram_wr_addr_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(status_ram_wr_addr_ns[0]),\n .Q(status_ram_wr_addr_r[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.status_ram.status_ram_wr_addr_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(status_ram_wr_addr_ns[1]),\n .Q(status_ram_wr_addr_r[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.status_ram.status_ram_wr_addr_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(status_ram_wr_addr_ns[2]),\n .Q(status_ram_wr_addr_r[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.status_ram.status_ram_wr_addr_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(status_ram_wr_addr_ns[3]),\n .Q(status_ram_wr_addr_r[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.status_ram.status_ram_wr_addr_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(status_ram_wr_addr_ns[4]),\n .Q(status_ram_wr_addr_r[4]),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1476\" *) \n LUT4 #(\n .INIT(16'h404C)) \n \\not_strict_mode.status_ram.status_ram_wr_data_r[0]_i_1 \n (.I0(wr_status_r1),\n .I1(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I2(\\read_fifo.fifo_out_data_r_reg[7] [0]),\n .I3(wr_status),\n .O(status_ram_wr_data_ns[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1476\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\not_strict_mode.status_ram.status_ram_wr_data_r[1]_i_1 \n (.I0(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I1(\\read_fifo.fifo_out_data_r_reg[7] [6]),\n .O(status_ram_wr_data_ns[1]));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(status_ram_wr_data_ns[0]),\n .Q(status_ram_wr_data_r[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.status_ram.status_ram_wr_data_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(status_ram_wr_data_ns[1]),\n .Q(status_ram_wr_data_r[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\not_strict_mode.status_ram.wr_status_r1_reg \n (.C(CLK),\n .CE(1'b1),\n .D(wr_status),\n .Q(wr_status_r1),\n .R(1'b0));\n LUT3 #(\n .INIT(8'hB8)) \n \\pointer_ram.rams[0].RAM32M0_i_2 \n (.I0(\\cmd_pipe_plus.wr_data_addr_reg[3] [1]),\n .I1(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I2(Q[1]),\n .O(pointer_wr_data[1]));\n LUT3 #(\n .INIT(8'hB8)) \n \\pointer_ram.rams[0].RAM32M0_i_3 \n (.I0(\\cmd_pipe_plus.wr_data_addr_reg[3] [0]),\n .I1(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I2(Q[0]),\n .O(pointer_wr_data[0]));\n LUT3 #(\n .INIT(8'hB8)) \n \\pointer_ram.rams[0].RAM32M0_i_4 \n (.I0(\\read_data_indx.rd_data_indx_r_reg[3] [3]),\n .I1(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I2(Q[3]),\n .O(ADDRD[3]));\n LUT3 #(\n .INIT(8'hB8)) \n \\pointer_ram.rams[0].RAM32M0_i_5 \n (.I0(\\read_data_indx.rd_data_indx_r_reg[3] [2]),\n .I1(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I2(Q[2]),\n .O(ADDRD[2]));\n LUT3 #(\n .INIT(8'hB8)) \n \\pointer_ram.rams[0].RAM32M0_i_6 \n (.I0(\\read_data_indx.rd_data_indx_r_reg[3] [1]),\n .I1(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I2(Q[1]),\n .O(ADDRD[1]));\n LUT3 #(\n .INIT(8'hB8)) \n \\pointer_ram.rams[0].RAM32M0_i_7 \n (.I0(\\read_data_indx.rd_data_indx_r_reg[3] [0]),\n .I1(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I2(Q[0]),\n .O(ADDRD[0]));\n LUT3 #(\n .INIT(8'hB8)) \n \\pointer_ram.rams[1].RAM32M0_i_1 \n (.I0(\\cmd_pipe_plus.wr_data_addr_reg[3] [3]),\n .I1(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I2(Q[3]),\n .O(pointer_wr_data[3]));\n LUT3 #(\n .INIT(8'hB8)) \n \\pointer_ram.rams[1].RAM32M0_i_2 \n (.I0(\\cmd_pipe_plus.wr_data_addr_reg[3] [2]),\n .I1(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I2(Q[2]),\n .O(pointer_wr_data[2]));\n LUT6 #(\n .INIT(64'hFFFFFFFF80000000)) \n \\rd_buf_indx.ram_init_done_r_lcl_i_1 \n (.I0(Q[3]),\n .I1(Q[4]),\n .I2(\\rd_buf_indx.ram_init_done_r_lcl_i_2_n_0 ),\n .I3(Q[2]),\n .I4(Q[1]),\n .I5(\\rd_buf_indx.ram_init_done_r_lcl_reg_0 ),\n .O(ram_init_done_ns));\n LUT2 #(\n .INIT(4'h2)) \n \\rd_buf_indx.ram_init_done_r_lcl_i_2 \n (.I0(Q[0]),\n .I1(reset_reg),\n .O(\\rd_buf_indx.ram_init_done_r_lcl_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1475\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\rd_buf_indx.ram_init_done_r_lcl_i_3 \n (.I0(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I1(reset_reg),\n .O(\\rd_buf_indx.ram_init_done_r_lcl_reg_0 ));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n \\rd_buf_indx.ram_init_done_r_lcl_reg \n (.C(CLK),\n .CE(1'b1),\n .D(ram_init_done_ns),\n .Q(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h000000001400EBFF)) \n \\rd_buf_indx.rd_buf_indx_r[0]_i_1 \n (.I0(bypass__0),\n .I1(\\rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ),\n .I2(rd_status),\n .I3(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I4(Q[0]),\n .I5(reset_reg),\n .O(rd_buf_indx_ns[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1477\" *) \n LUT3 #(\n .INIT(8'h09)) \n \\rd_buf_indx.rd_buf_indx_r[1]_i_1 \n (.I0(\\rd_buf_indx.rd_buf_indx_r[1]_i_2_n_0 ),\n .I1(Q[1]),\n .I2(reset_reg),\n .O(rd_buf_indx_ns[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1472\" *) \n LUT5 #(\n .INIT(32'h0028FFFF)) \n \\rd_buf_indx.rd_buf_indx_r[1]_i_2 \n (.I0(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I1(rd_status),\n .I2(\\rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ),\n .I3(bypass__0),\n .I4(Q[0]),\n .O(\\rd_buf_indx.rd_buf_indx_r[1]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1477\" *) \n LUT3 #(\n .INIT(8'h06)) \n \\rd_buf_indx.rd_buf_indx_r[2]_i_1 \n (.I0(\\rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0 ),\n .I1(Q[2]),\n .I2(reset_reg),\n .O(rd_buf_indx_ns[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1471\" *) \n LUT4 #(\n .INIT(16'h0078)) \n \\rd_buf_indx.rd_buf_indx_r[3]_i_1 \n (.I0(\\rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0 ),\n .I1(Q[2]),\n .I2(Q[3]),\n .I3(reset_reg),\n .O(rd_buf_indx_ns[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1471\" *) \n LUT5 #(\n .INIT(32'h00007F80)) \n \\rd_buf_indx.rd_buf_indx_r[4]_i_1 \n (.I0(Q[3]),\n .I1(Q[2]),\n .I2(\\rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0 ),\n .I3(Q[4]),\n .I4(reset_reg),\n .O(rd_buf_indx_ns[4]));\n LUT6 #(\n .INIT(64'h000000007FFF8000)) \n \\rd_buf_indx.rd_buf_indx_r[5]_i_1 \n (.I0(\\rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0 ),\n .I1(Q[2]),\n .I2(Q[3]),\n .I3(Q[4]),\n .I4(\\rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ),\n .I5(reset_reg),\n .O(rd_buf_indx_ns[5]));\n LUT6 #(\n .INIT(64'h8880808888888888)) \n \\rd_buf_indx.rd_buf_indx_r[5]_i_2 \n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(bypass__0),\n .I3(\\rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ),\n .I4(rd_status),\n .I5(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .O(\\rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rd_buf_indx.rd_buf_indx_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_buf_indx_ns[0]),\n .Q(Q[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rd_buf_indx.rd_buf_indx_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_buf_indx_ns[1]),\n .Q(Q[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rd_buf_indx.rd_buf_indx_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_buf_indx_ns[2]),\n .Q(Q[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rd_buf_indx.rd_buf_indx_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_buf_indx_ns[3]),\n .Q(Q[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rd_buf_indx.rd_buf_indx_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_buf_indx_ns[4]),\n .Q(Q[4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rd_buf_indx.rd_buf_indx_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_buf_indx_ns[5]),\n .Q(\\rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ),\n .R(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ui_top\" *) \nmodule ddr3_ifmig_7series_v4_0_ui_top\n (\\not_strict_mode.app_rd_data_end_reg ,\n Q,\n DOA,\n DOB,\n DOC,\n \\not_strict_mode.app_rd_data_reg[11] ,\n \\not_strict_mode.app_rd_data_reg[9] ,\n \\not_strict_mode.app_rd_data_reg[7] ,\n \\not_strict_mode.app_rd_data_reg[17] ,\n \\not_strict_mode.app_rd_data_reg[15] ,\n \\not_strict_mode.app_rd_data_reg[13] ,\n \\not_strict_mode.app_rd_data_reg[23] ,\n \\not_strict_mode.app_rd_data_reg[21] ,\n \\not_strict_mode.app_rd_data_reg[19] ,\n \\not_strict_mode.app_rd_data_reg[29] ,\n \\not_strict_mode.app_rd_data_reg[27] ,\n \\not_strict_mode.app_rd_data_reg[25] ,\n \\not_strict_mode.app_rd_data_reg[35] ,\n \\not_strict_mode.app_rd_data_reg[33] ,\n \\not_strict_mode.app_rd_data_reg[31] ,\n \\not_strict_mode.app_rd_data_reg[41] ,\n \\not_strict_mode.app_rd_data_reg[39] ,\n \\not_strict_mode.app_rd_data_reg[37] ,\n \\not_strict_mode.app_rd_data_reg[47] ,\n \\not_strict_mode.app_rd_data_reg[45] ,\n \\not_strict_mode.app_rd_data_reg[43] ,\n \\not_strict_mode.app_rd_data_reg[53] ,\n \\not_strict_mode.app_rd_data_reg[51] ,\n \\not_strict_mode.app_rd_data_reg[49] ,\n \\not_strict_mode.app_rd_data_reg[59] ,\n \\not_strict_mode.app_rd_data_reg[57] ,\n \\not_strict_mode.app_rd_data_reg[55] ,\n \\not_strict_mode.app_rd_data_reg[65] ,\n \\not_strict_mode.app_rd_data_reg[63] ,\n \\not_strict_mode.app_rd_data_reg[61] ,\n \\not_strict_mode.app_rd_data_reg[71] ,\n \\not_strict_mode.app_rd_data_reg[69] ,\n \\not_strict_mode.app_rd_data_reg[67] ,\n \\not_strict_mode.app_rd_data_reg[77] ,\n \\not_strict_mode.app_rd_data_reg[75] ,\n \\not_strict_mode.app_rd_data_reg[73] ,\n \\not_strict_mode.app_rd_data_reg[83] ,\n \\not_strict_mode.app_rd_data_reg[81] ,\n \\not_strict_mode.app_rd_data_reg[79] ,\n \\not_strict_mode.app_rd_data_reg[89] ,\n \\not_strict_mode.app_rd_data_reg[87] ,\n \\not_strict_mode.app_rd_data_reg[85] ,\n \\not_strict_mode.app_rd_data_reg[95] ,\n \\not_strict_mode.app_rd_data_reg[93] ,\n \\not_strict_mode.app_rd_data_reg[91] ,\n \\not_strict_mode.app_rd_data_reg[101] ,\n \\not_strict_mode.app_rd_data_reg[99] ,\n \\not_strict_mode.app_rd_data_reg[97] ,\n \\not_strict_mode.app_rd_data_reg[107] ,\n \\not_strict_mode.app_rd_data_reg[105] ,\n \\not_strict_mode.app_rd_data_reg[103] ,\n \\not_strict_mode.app_rd_data_reg[113] ,\n \\not_strict_mode.app_rd_data_reg[111] ,\n \\not_strict_mode.app_rd_data_reg[109] ,\n \\not_strict_mode.app_rd_data_reg[119] ,\n \\not_strict_mode.app_rd_data_reg[117] ,\n \\not_strict_mode.app_rd_data_reg[115] ,\n \\not_strict_mode.app_rd_data_reg[125] ,\n \\not_strict_mode.app_rd_data_reg[123] ,\n \\not_strict_mode.app_rd_data_reg[121] ,\n \\not_strict_mode.app_rd_data_reg[131] ,\n \\not_strict_mode.app_rd_data_reg[129] ,\n \\not_strict_mode.app_rd_data_reg[127] ,\n \\not_strict_mode.app_rd_data_reg[137] ,\n \\not_strict_mode.app_rd_data_reg[135] ,\n \\not_strict_mode.app_rd_data_reg[133] ,\n \\not_strict_mode.app_rd_data_reg[143] ,\n \\not_strict_mode.app_rd_data_reg[141] ,\n \\not_strict_mode.app_rd_data_reg[139] ,\n \\not_strict_mode.app_rd_data_reg[149] ,\n \\not_strict_mode.app_rd_data_reg[147] ,\n \\not_strict_mode.app_rd_data_reg[145] ,\n \\not_strict_mode.app_rd_data_reg[155] ,\n \\not_strict_mode.app_rd_data_reg[153] ,\n \\not_strict_mode.app_rd_data_reg[151] ,\n \\not_strict_mode.app_rd_data_reg[161] ,\n \\not_strict_mode.app_rd_data_reg[159] ,\n \\not_strict_mode.app_rd_data_reg[157] ,\n \\not_strict_mode.app_rd_data_reg[167] ,\n \\not_strict_mode.app_rd_data_reg[165] ,\n \\not_strict_mode.app_rd_data_reg[163] ,\n \\not_strict_mode.app_rd_data_reg[173] ,\n \\not_strict_mode.app_rd_data_reg[171] ,\n \\not_strict_mode.app_rd_data_reg[169] ,\n \\not_strict_mode.app_rd_data_reg[179] ,\n \\not_strict_mode.app_rd_data_reg[177] ,\n \\not_strict_mode.app_rd_data_reg[175] ,\n \\not_strict_mode.app_rd_data_reg[185] ,\n \\not_strict_mode.app_rd_data_reg[183] ,\n \\not_strict_mode.app_rd_data_reg[181] ,\n \\not_strict_mode.app_rd_data_reg[191] ,\n \\not_strict_mode.app_rd_data_reg[189] ,\n \\not_strict_mode.app_rd_data_reg[187] ,\n \\not_strict_mode.app_rd_data_reg[197] ,\n \\not_strict_mode.app_rd_data_reg[195] ,\n \\not_strict_mode.app_rd_data_reg[193] ,\n \\not_strict_mode.app_rd_data_reg[203] ,\n \\not_strict_mode.app_rd_data_reg[201] ,\n \\not_strict_mode.app_rd_data_reg[199] ,\n \\not_strict_mode.app_rd_data_reg[209] ,\n \\not_strict_mode.app_rd_data_reg[207] ,\n \\not_strict_mode.app_rd_data_reg[205] ,\n \\not_strict_mode.app_rd_data_reg[215] ,\n \\not_strict_mode.app_rd_data_reg[213] ,\n \\not_strict_mode.app_rd_data_reg[211] ,\n \\not_strict_mode.app_rd_data_reg[221] ,\n \\not_strict_mode.app_rd_data_reg[219] ,\n \\not_strict_mode.app_rd_data_reg[217] ,\n \\not_strict_mode.app_rd_data_reg[227] ,\n \\not_strict_mode.app_rd_data_reg[225] ,\n \\not_strict_mode.app_rd_data_reg[223] ,\n \\not_strict_mode.app_rd_data_reg[233] ,\n \\not_strict_mode.app_rd_data_reg[231] ,\n \\not_strict_mode.app_rd_data_reg[229] ,\n \\not_strict_mode.app_rd_data_reg[239] ,\n \\not_strict_mode.app_rd_data_reg[237] ,\n \\not_strict_mode.app_rd_data_reg[235] ,\n \\not_strict_mode.app_rd_data_reg[245] ,\n \\not_strict_mode.app_rd_data_reg[243] ,\n \\not_strict_mode.app_rd_data_reg[241] ,\n \\not_strict_mode.app_rd_data_reg[251] ,\n \\not_strict_mode.app_rd_data_reg[249] ,\n \\not_strict_mode.app_rd_data_reg[247] ,\n \\not_strict_mode.app_rd_data_reg[255] ,\n \\not_strict_mode.app_rd_data_reg[253] ,\n app_rdy,\n app_en_r1,\n app_hi_pri_r2,\n hi_priority,\n ram_init_done_r,\n app_wdf_rdy,\n app_rd_data_valid,\n cmd,\n p_28_out,\n rb_hit_busy_r_reg,\n p_67_out,\n rb_hit_busy_r_reg_0,\n \\req_bank_r_lcl_reg[2] ,\n use_addr,\n \\req_data_buf_addr_r_reg[4] ,\n \\req_row_r_lcl_reg[14] ,\n \\req_col_r_reg[9] ,\n \\my_empty_reg[7] ,\n \\s_axi_rdata[255] ,\n CLK,\n pointer_we,\n \\cmd_pipe_plus.wr_data_addr_reg[3] ,\n rd_buf_we,\n DIA,\n DIB,\n DIC,\n \\read_fifo.fifo_out_data_r_reg[7] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ,\n app_en_ns1,\n E,\n app_rd_data_end_ns,\n reset_reg,\n mc_app_cmd,\n idle_ns,\n \\req_bank_r_lcl_reg[2]_0 ,\n \\req_bank_r_lcl_reg[2]_1 ,\n mc_app_wdf_wren_reg,\n w_cmd_rdy,\n D,\n mc_app_wdf_mask_reg,\n wready_reg_rep__1,\n mc_app_wdf_data_reg,\n accept_ns,\n bypass__0,\n app_rdy_r_reg,\n \\axaddr_incr_reg[29] ,\n app_wdf_data,\n app_wdf_mask,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 );\n output [0:0]\\not_strict_mode.app_rd_data_end_reg ;\n output [4:0]Q;\n output [1:0]DOA;\n output [1:0]DOB;\n output [1:0]DOC;\n output [1:0]\\not_strict_mode.app_rd_data_reg[11] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[9] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[7] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[17] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[15] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[13] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[23] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[21] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[19] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[29] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[27] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[25] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[35] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[33] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[31] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[41] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[39] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[37] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[47] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[45] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[43] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[53] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[51] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[49] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[59] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[57] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[55] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[65] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[63] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[61] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[71] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[69] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[67] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[77] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[75] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[73] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[83] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[81] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[79] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[89] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[87] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[85] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[95] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[93] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[91] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[101] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[99] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[97] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[107] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[105] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[103] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[113] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[111] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[109] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[119] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[117] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[115] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[125] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[123] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[121] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[131] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[129] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[127] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[137] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[135] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[133] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[143] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[141] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[139] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[149] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[147] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[145] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[155] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[153] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[151] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[161] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[159] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[157] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[167] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[165] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[163] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[173] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[171] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[169] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[179] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[177] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[175] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[185] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[183] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[181] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[191] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[189] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[187] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[197] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[195] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[193] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[203] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[201] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[199] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[209] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[207] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[205] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[215] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[213] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[211] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[221] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[219] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[217] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[227] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[225] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[223] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[233] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[231] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[229] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[239] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[237] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[235] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[245] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[243] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[241] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[251] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[249] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[247] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[255] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[253] ;\n output app_rdy;\n output app_en_r1;\n output app_hi_pri_r2;\n output hi_priority;\n output ram_init_done_r;\n output app_wdf_rdy;\n output app_rd_data_valid;\n output [1:0]cmd;\n output p_28_out;\n output rb_hit_busy_r_reg;\n output p_67_out;\n output rb_hit_busy_r_reg_0;\n output [2:0]\\req_bank_r_lcl_reg[2] ;\n output use_addr;\n output [4:0]\\req_data_buf_addr_r_reg[4] ;\n output [14:0]\\req_row_r_lcl_reg[14] ;\n output [6:0]\\req_col_r_reg[9] ;\n output [287:0]\\my_empty_reg[7] ;\n output [255:0]\\s_axi_rdata[255] ;\n input CLK;\n input pointer_we;\n input [3:0]\\cmd_pipe_plus.wr_data_addr_reg[3] ;\n input rd_buf_we;\n input [1:0]DIA;\n input [1:0]DIB;\n input [1:0]DIC;\n input [6:0]\\read_fifo.fifo_out_data_r_reg[7] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;\n input app_en_ns1;\n input [0:0]E;\n input app_rd_data_end_ns;\n input reset_reg;\n input [0:0]mc_app_cmd;\n input [1:0]idle_ns;\n input [2:0]\\req_bank_r_lcl_reg[2]_0 ;\n input [2:0]\\req_bank_r_lcl_reg[2]_1 ;\n input mc_app_wdf_wren_reg;\n input w_cmd_rdy;\n input [31:0]D;\n input [31:0]mc_app_wdf_mask_reg;\n input [255:0]wready_reg_rep__1;\n input [255:0]mc_app_wdf_data_reg;\n input accept_ns;\n input bypass__0;\n input [0:0]app_rdy_r_reg;\n input [24:0]\\axaddr_incr_reg[29] ;\n input [255:0]app_wdf_data;\n input [31:0]app_wdf_mask;\n input [255:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ;\n\n wire CLK;\n wire [31:0]D;\n wire [1:0]DIA;\n wire [1:0]DIB;\n wire [1:0]DIC;\n wire [1:0]DOA;\n wire [1:0]DOB;\n wire [1:0]DOC;\n wire [0:0]E;\n wire [4:0]Q;\n wire accept_ns;\n wire app_en_ns1;\n wire app_en_r1;\n wire app_hi_pri_r2;\n wire app_rd_data_end_ns;\n wire app_rd_data_valid;\n wire app_rdy;\n wire app_rdy_ns;\n wire [0:0]app_rdy_r_reg;\n wire [255:0]app_wdf_data;\n wire [31:0]app_wdf_mask;\n wire app_wdf_rdy;\n wire [24:0]\\axaddr_incr_reg[29] ;\n wire bypass__0;\n wire [1:0]cmd;\n wire [3:0]\\cmd_pipe_plus.wr_data_addr_reg[3] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ;\n wire [255:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ;\n wire hi_priority;\n wire [1:0]idle_ns;\n wire [0:0]mc_app_cmd;\n wire [255:0]mc_app_wdf_data_reg;\n wire [31:0]mc_app_wdf_mask_reg;\n wire mc_app_wdf_wren_reg;\n wire [287:0]\\my_empty_reg[7] ;\n wire [0:0]\\not_strict_mode.app_rd_data_end_reg ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[101] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[103] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[105] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[107] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[109] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[111] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[113] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[115] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[117] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[119] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[11] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[121] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[123] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[125] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[127] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[129] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[131] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[133] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[135] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[137] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[139] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[13] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[141] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[143] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[145] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[147] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[149] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[151] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[153] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[155] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[157] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[159] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[15] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[161] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[163] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[165] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[167] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[169] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[171] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[173] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[175] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[177] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[179] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[17] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[181] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[183] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[185] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[187] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[189] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[191] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[193] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[195] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[197] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[199] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[19] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[201] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[203] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[205] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[207] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[209] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[211] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[213] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[215] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[217] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[219] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[21] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[221] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[223] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[225] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[227] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[229] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[231] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[233] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[235] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[237] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[239] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[23] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[241] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[243] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[245] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[247] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[249] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[251] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[253] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[255] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[25] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[27] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[29] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[31] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[33] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[35] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[37] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[39] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[41] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[43] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[45] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[47] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[49] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[51] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[53] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[55] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[57] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[59] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[61] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[63] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[65] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[67] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[69] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[71] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[73] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[75] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[77] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[79] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[7] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[81] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[83] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[85] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[87] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[89] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[91] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[93] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[95] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[97] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[99] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[9] ;\n wire [1:0]occ_cnt_r;\n wire [0:0]p_0_in;\n wire p_28_out;\n wire p_67_out;\n wire pointer_we;\n wire [3:0]pointer_wr_addr;\n wire [3:0]pointer_wr_data;\n wire ram_init_done_r;\n wire rb_hit_busy_r_reg;\n wire rb_hit_busy_r_reg_0;\n wire rd_accepted;\n wire rd_buf_we;\n wire [4:0]rd_data_buf_addr_r;\n wire [3:0]\\read_data_indx.rd_data_indx_r_reg__0 ;\n wire [6:0]\\read_fifo.fifo_out_data_r_reg[7] ;\n wire [2:0]\\req_bank_r_lcl_reg[2] ;\n wire [2:0]\\req_bank_r_lcl_reg[2]_0 ;\n wire [2:0]\\req_bank_r_lcl_reg[2]_1 ;\n wire [6:0]\\req_col_r_reg[9] ;\n wire [4:0]\\req_data_buf_addr_r_reg[4] ;\n wire [14:0]\\req_row_r_lcl_reg[14] ;\n wire reset_reg;\n wire [255:0]\\s_axi_rdata[255] ;\n wire ui_cmd0_n_13;\n wire ui_cmd0_n_14;\n wire ui_cmd0_n_16;\n wire ui_rd_data0_n_264;\n wire ui_rd_data0_n_272;\n wire use_addr;\n wire w_cmd_rdy;\n wire wr_accepted;\n wire [3:0]wr_data_buf_addr;\n wire [1:0]wr_req_cnt_r;\n wire [255:0]wready_reg_rep__1;\n\n ddr3_ifmig_7series_v4_0_ui_cmd ui_cmd0\n (.CLK(CLK),\n .E(app_rdy),\n .Q(occ_cnt_r),\n .app_en_ns1(app_en_ns1),\n .app_en_r1(app_en_r1),\n .app_hi_pri_r2(app_hi_pri_r2),\n .app_rdy_ns(app_rdy_ns),\n .app_rdy_r_reg_0(app_rdy_r_reg),\n .\\axaddr_incr_reg[29] (\\axaddr_incr_reg[29] ),\n .cmd(cmd),\n .hi_priority(hi_priority),\n .idle_ns(idle_ns),\n .mc_app_cmd(mc_app_cmd),\n .\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (rd_data_buf_addr_r),\n .\\not_strict_mode.occupied_counter.occ_cnt_r_reg[3] (ui_cmd0_n_16),\n .p_0_in(p_0_in),\n .p_28_out(p_28_out),\n .p_67_out(p_67_out),\n .rb_hit_busy_r_reg(rb_hit_busy_r_reg),\n .rb_hit_busy_r_reg_0(rb_hit_busy_r_reg_0),\n .rd_accepted(rd_accepted),\n .\\req_bank_r_lcl_reg[2] (\\req_bank_r_lcl_reg[2] ),\n .\\req_bank_r_lcl_reg[2]_0 (\\req_bank_r_lcl_reg[2]_0 ),\n .\\req_bank_r_lcl_reg[2]_1 (\\req_bank_r_lcl_reg[2]_1 ),\n .\\req_col_r_reg[9] (\\req_col_r_reg[9] ),\n .\\req_data_buf_addr_r_reg[4] (\\req_data_buf_addr_r_reg[4] ),\n .\\req_row_r_lcl_reg[14] (\\req_row_r_lcl_reg[14] ),\n .reset_reg(reset_reg),\n .use_addr(use_addr),\n .wr_accepted(wr_accepted),\n .wr_data_buf_addr(wr_data_buf_addr),\n .wr_req_cnt_r(wr_req_cnt_r),\n .\\wr_req_counter.wr_req_cnt_r_reg[3] (ui_cmd0_n_14),\n .\\wr_req_counter.wr_req_cnt_r_reg[4] (ui_cmd0_n_13));\n ddr3_ifmig_7series_v4_0_ui_rd_data ui_rd_data0\n (.ADDRD(pointer_wr_addr),\n .CLK(CLK),\n .D(ui_rd_data0_n_264),\n .DIA(DIA),\n .DIB(DIB),\n .DIC(DIC),\n .DOA(DOA),\n .DOB(DOB),\n .DOC(DOC),\n .Q(Q),\n .app_rd_data_end_ns(app_rd_data_end_ns),\n .app_rd_data_valid(app_rd_data_valid),\n .bypass__0(bypass__0),\n .\\cmd_pipe_plus.wr_data_addr_reg[3] (\\cmd_pipe_plus.wr_data_addr_reg[3] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ),\n .\\not_strict_mode.app_rd_data_end_reg_0 (\\not_strict_mode.app_rd_data_end_reg ),\n .\\not_strict_mode.app_rd_data_reg[101]_0 (\\not_strict_mode.app_rd_data_reg[101] ),\n .\\not_strict_mode.app_rd_data_reg[103]_0 (\\not_strict_mode.app_rd_data_reg[103] ),\n .\\not_strict_mode.app_rd_data_reg[105]_0 (\\not_strict_mode.app_rd_data_reg[105] ),\n .\\not_strict_mode.app_rd_data_reg[107]_0 (\\not_strict_mode.app_rd_data_reg[107] ),\n .\\not_strict_mode.app_rd_data_reg[109]_0 (\\not_strict_mode.app_rd_data_reg[109] ),\n .\\not_strict_mode.app_rd_data_reg[111]_0 (\\not_strict_mode.app_rd_data_reg[111] ),\n .\\not_strict_mode.app_rd_data_reg[113]_0 (\\not_strict_mode.app_rd_data_reg[113] ),\n .\\not_strict_mode.app_rd_data_reg[115]_0 (\\not_strict_mode.app_rd_data_reg[115] ),\n .\\not_strict_mode.app_rd_data_reg[117]_0 (\\not_strict_mode.app_rd_data_reg[117] ),\n .\\not_strict_mode.app_rd_data_reg[119]_0 (\\not_strict_mode.app_rd_data_reg[119] ),\n .\\not_strict_mode.app_rd_data_reg[11]_0 (\\not_strict_mode.app_rd_data_reg[11] ),\n .\\not_strict_mode.app_rd_data_reg[121]_0 (\\not_strict_mode.app_rd_data_reg[121] ),\n .\\not_strict_mode.app_rd_data_reg[123]_0 (\\not_strict_mode.app_rd_data_reg[123] ),\n .\\not_strict_mode.app_rd_data_reg[125]_0 (\\not_strict_mode.app_rd_data_reg[125] ),\n .\\not_strict_mode.app_rd_data_reg[127]_0 (\\not_strict_mode.app_rd_data_reg[127] ),\n .\\not_strict_mode.app_rd_data_reg[129]_0 (\\not_strict_mode.app_rd_data_reg[129] ),\n .\\not_strict_mode.app_rd_data_reg[131]_0 (\\not_strict_mode.app_rd_data_reg[131] ),\n .\\not_strict_mode.app_rd_data_reg[133]_0 (\\not_strict_mode.app_rd_data_reg[133] ),\n .\\not_strict_mode.app_rd_data_reg[135]_0 (\\not_strict_mode.app_rd_data_reg[135] ),\n .\\not_strict_mode.app_rd_data_reg[137]_0 (\\not_strict_mode.app_rd_data_reg[137] ),\n .\\not_strict_mode.app_rd_data_reg[139]_0 (\\not_strict_mode.app_rd_data_reg[139] ),\n .\\not_strict_mode.app_rd_data_reg[13]_0 (\\not_strict_mode.app_rd_data_reg[13] ),\n .\\not_strict_mode.app_rd_data_reg[141]_0 (\\not_strict_mode.app_rd_data_reg[141] ),\n .\\not_strict_mode.app_rd_data_reg[143]_0 (\\not_strict_mode.app_rd_data_reg[143] ),\n .\\not_strict_mode.app_rd_data_reg[145]_0 (\\not_strict_mode.app_rd_data_reg[145] ),\n .\\not_strict_mode.app_rd_data_reg[147]_0 (\\not_strict_mode.app_rd_data_reg[147] ),\n .\\not_strict_mode.app_rd_data_reg[149]_0 (\\not_strict_mode.app_rd_data_reg[149] ),\n .\\not_strict_mode.app_rd_data_reg[151]_0 (\\not_strict_mode.app_rd_data_reg[151] ),\n .\\not_strict_mode.app_rd_data_reg[153]_0 (\\not_strict_mode.app_rd_data_reg[153] ),\n .\\not_strict_mode.app_rd_data_reg[155]_0 (\\not_strict_mode.app_rd_data_reg[155] ),\n .\\not_strict_mode.app_rd_data_reg[157]_0 (\\not_strict_mode.app_rd_data_reg[157] ),\n .\\not_strict_mode.app_rd_data_reg[159]_0 (\\not_strict_mode.app_rd_data_reg[159] ),\n .\\not_strict_mode.app_rd_data_reg[15]_0 (\\not_strict_mode.app_rd_data_reg[15] ),\n .\\not_strict_mode.app_rd_data_reg[161]_0 (\\not_strict_mode.app_rd_data_reg[161] ),\n .\\not_strict_mode.app_rd_data_reg[163]_0 (\\not_strict_mode.app_rd_data_reg[163] ),\n .\\not_strict_mode.app_rd_data_reg[165]_0 (\\not_strict_mode.app_rd_data_reg[165] ),\n .\\not_strict_mode.app_rd_data_reg[167]_0 (\\not_strict_mode.app_rd_data_reg[167] ),\n .\\not_strict_mode.app_rd_data_reg[169]_0 (\\not_strict_mode.app_rd_data_reg[169] ),\n .\\not_strict_mode.app_rd_data_reg[171]_0 (\\not_strict_mode.app_rd_data_reg[171] ),\n .\\not_strict_mode.app_rd_data_reg[173]_0 (\\not_strict_mode.app_rd_data_reg[173] ),\n .\\not_strict_mode.app_rd_data_reg[175]_0 (\\not_strict_mode.app_rd_data_reg[175] ),\n .\\not_strict_mode.app_rd_data_reg[177]_0 (\\not_strict_mode.app_rd_data_reg[177] ),\n .\\not_strict_mode.app_rd_data_reg[179]_0 (\\not_strict_mode.app_rd_data_reg[179] ),\n .\\not_strict_mode.app_rd_data_reg[17]_0 (\\not_strict_mode.app_rd_data_reg[17] ),\n .\\not_strict_mode.app_rd_data_reg[181]_0 (\\not_strict_mode.app_rd_data_reg[181] ),\n .\\not_strict_mode.app_rd_data_reg[183]_0 (\\not_strict_mode.app_rd_data_reg[183] ),\n .\\not_strict_mode.app_rd_data_reg[185]_0 (\\not_strict_mode.app_rd_data_reg[185] ),\n .\\not_strict_mode.app_rd_data_reg[187]_0 (\\not_strict_mode.app_rd_data_reg[187] ),\n .\\not_strict_mode.app_rd_data_reg[189]_0 (\\not_strict_mode.app_rd_data_reg[189] ),\n .\\not_strict_mode.app_rd_data_reg[191]_0 (\\not_strict_mode.app_rd_data_reg[191] ),\n .\\not_strict_mode.app_rd_data_reg[193]_0 (\\not_strict_mode.app_rd_data_reg[193] ),\n .\\not_strict_mode.app_rd_data_reg[195]_0 (\\not_strict_mode.app_rd_data_reg[195] ),\n .\\not_strict_mode.app_rd_data_reg[197]_0 (\\not_strict_mode.app_rd_data_reg[197] ),\n .\\not_strict_mode.app_rd_data_reg[199]_0 (\\not_strict_mode.app_rd_data_reg[199] ),\n .\\not_strict_mode.app_rd_data_reg[19]_0 (\\not_strict_mode.app_rd_data_reg[19] ),\n .\\not_strict_mode.app_rd_data_reg[201]_0 (\\not_strict_mode.app_rd_data_reg[201] ),\n .\\not_strict_mode.app_rd_data_reg[203]_0 (\\not_strict_mode.app_rd_data_reg[203] ),\n .\\not_strict_mode.app_rd_data_reg[205]_0 (\\not_strict_mode.app_rd_data_reg[205] ),\n .\\not_strict_mode.app_rd_data_reg[207]_0 (\\not_strict_mode.app_rd_data_reg[207] ),\n .\\not_strict_mode.app_rd_data_reg[209]_0 (\\not_strict_mode.app_rd_data_reg[209] ),\n .\\not_strict_mode.app_rd_data_reg[211]_0 (\\not_strict_mode.app_rd_data_reg[211] ),\n .\\not_strict_mode.app_rd_data_reg[213]_0 (\\not_strict_mode.app_rd_data_reg[213] ),\n .\\not_strict_mode.app_rd_data_reg[215]_0 (\\not_strict_mode.app_rd_data_reg[215] ),\n .\\not_strict_mode.app_rd_data_reg[217]_0 (\\not_strict_mode.app_rd_data_reg[217] ),\n .\\not_strict_mode.app_rd_data_reg[219]_0 (\\not_strict_mode.app_rd_data_reg[219] ),\n .\\not_strict_mode.app_rd_data_reg[21]_0 (\\not_strict_mode.app_rd_data_reg[21] ),\n .\\not_strict_mode.app_rd_data_reg[221]_0 (\\not_strict_mode.app_rd_data_reg[221] ),\n .\\not_strict_mode.app_rd_data_reg[223]_0 (\\not_strict_mode.app_rd_data_reg[223] ),\n .\\not_strict_mode.app_rd_data_reg[225]_0 (\\not_strict_mode.app_rd_data_reg[225] ),\n .\\not_strict_mode.app_rd_data_reg[227]_0 (\\not_strict_mode.app_rd_data_reg[227] ),\n .\\not_strict_mode.app_rd_data_reg[229]_0 (\\not_strict_mode.app_rd_data_reg[229] ),\n .\\not_strict_mode.app_rd_data_reg[231]_0 (\\not_strict_mode.app_rd_data_reg[231] ),\n .\\not_strict_mode.app_rd_data_reg[233]_0 (\\not_strict_mode.app_rd_data_reg[233] ),\n .\\not_strict_mode.app_rd_data_reg[235]_0 (\\not_strict_mode.app_rd_data_reg[235] ),\n .\\not_strict_mode.app_rd_data_reg[237]_0 (\\not_strict_mode.app_rd_data_reg[237] ),\n .\\not_strict_mode.app_rd_data_reg[239]_0 (\\not_strict_mode.app_rd_data_reg[239] ),\n .\\not_strict_mode.app_rd_data_reg[23]_0 (\\not_strict_mode.app_rd_data_reg[23] ),\n .\\not_strict_mode.app_rd_data_reg[241]_0 (\\not_strict_mode.app_rd_data_reg[241] ),\n .\\not_strict_mode.app_rd_data_reg[243]_0 (\\not_strict_mode.app_rd_data_reg[243] ),\n .\\not_strict_mode.app_rd_data_reg[245]_0 (\\not_strict_mode.app_rd_data_reg[245] ),\n .\\not_strict_mode.app_rd_data_reg[247]_0 (\\not_strict_mode.app_rd_data_reg[247] ),\n .\\not_strict_mode.app_rd_data_reg[249]_0 (\\not_strict_mode.app_rd_data_reg[249] ),\n .\\not_strict_mode.app_rd_data_reg[251]_0 (\\not_strict_mode.app_rd_data_reg[251] ),\n .\\not_strict_mode.app_rd_data_reg[253]_0 (\\not_strict_mode.app_rd_data_reg[253] ),\n .\\not_strict_mode.app_rd_data_reg[255]_0 (\\not_strict_mode.app_rd_data_reg[255] ),\n .\\not_strict_mode.app_rd_data_reg[25]_0 (\\not_strict_mode.app_rd_data_reg[25] ),\n .\\not_strict_mode.app_rd_data_reg[27]_0 (\\not_strict_mode.app_rd_data_reg[27] ),\n .\\not_strict_mode.app_rd_data_reg[29]_0 (\\not_strict_mode.app_rd_data_reg[29] ),\n .\\not_strict_mode.app_rd_data_reg[31]_0 (\\not_strict_mode.app_rd_data_reg[31] ),\n .\\not_strict_mode.app_rd_data_reg[33]_0 (\\not_strict_mode.app_rd_data_reg[33] ),\n .\\not_strict_mode.app_rd_data_reg[35]_0 (\\not_strict_mode.app_rd_data_reg[35] ),\n .\\not_strict_mode.app_rd_data_reg[37]_0 (\\not_strict_mode.app_rd_data_reg[37] ),\n .\\not_strict_mode.app_rd_data_reg[39]_0 (\\not_strict_mode.app_rd_data_reg[39] ),\n .\\not_strict_mode.app_rd_data_reg[41]_0 (\\not_strict_mode.app_rd_data_reg[41] ),\n .\\not_strict_mode.app_rd_data_reg[43]_0 (\\not_strict_mode.app_rd_data_reg[43] ),\n .\\not_strict_mode.app_rd_data_reg[45]_0 (\\not_strict_mode.app_rd_data_reg[45] ),\n .\\not_strict_mode.app_rd_data_reg[47]_0 (\\not_strict_mode.app_rd_data_reg[47] ),\n .\\not_strict_mode.app_rd_data_reg[49]_0 (\\not_strict_mode.app_rd_data_reg[49] ),\n .\\not_strict_mode.app_rd_data_reg[51]_0 (\\not_strict_mode.app_rd_data_reg[51] ),\n .\\not_strict_mode.app_rd_data_reg[53]_0 (\\not_strict_mode.app_rd_data_reg[53] ),\n .\\not_strict_mode.app_rd_data_reg[55]_0 (\\not_strict_mode.app_rd_data_reg[55] ),\n .\\not_strict_mode.app_rd_data_reg[57]_0 (\\not_strict_mode.app_rd_data_reg[57] ),\n .\\not_strict_mode.app_rd_data_reg[59]_0 (\\not_strict_mode.app_rd_data_reg[59] ),\n .\\not_strict_mode.app_rd_data_reg[61]_0 (\\not_strict_mode.app_rd_data_reg[61] ),\n .\\not_strict_mode.app_rd_data_reg[63]_0 (\\not_strict_mode.app_rd_data_reg[63] ),\n .\\not_strict_mode.app_rd_data_reg[65]_0 (\\not_strict_mode.app_rd_data_reg[65] ),\n .\\not_strict_mode.app_rd_data_reg[67]_0 (\\not_strict_mode.app_rd_data_reg[67] ),\n .\\not_strict_mode.app_rd_data_reg[69]_0 (\\not_strict_mode.app_rd_data_reg[69] ),\n .\\not_strict_mode.app_rd_data_reg[71]_0 (\\not_strict_mode.app_rd_data_reg[71] ),\n .\\not_strict_mode.app_rd_data_reg[73]_0 (\\not_strict_mode.app_rd_data_reg[73] ),\n .\\not_strict_mode.app_rd_data_reg[75]_0 (\\not_strict_mode.app_rd_data_reg[75] ),\n .\\not_strict_mode.app_rd_data_reg[77]_0 (\\not_strict_mode.app_rd_data_reg[77] ),\n .\\not_strict_mode.app_rd_data_reg[79]_0 (\\not_strict_mode.app_rd_data_reg[79] ),\n .\\not_strict_mode.app_rd_data_reg[7]_0 (\\not_strict_mode.app_rd_data_reg[7] ),\n .\\not_strict_mode.app_rd_data_reg[81]_0 (\\not_strict_mode.app_rd_data_reg[81] ),\n .\\not_strict_mode.app_rd_data_reg[83]_0 (\\not_strict_mode.app_rd_data_reg[83] ),\n .\\not_strict_mode.app_rd_data_reg[85]_0 (\\not_strict_mode.app_rd_data_reg[85] ),\n .\\not_strict_mode.app_rd_data_reg[87]_0 (\\not_strict_mode.app_rd_data_reg[87] ),\n .\\not_strict_mode.app_rd_data_reg[89]_0 (\\not_strict_mode.app_rd_data_reg[89] ),\n .\\not_strict_mode.app_rd_data_reg[91]_0 (\\not_strict_mode.app_rd_data_reg[91] ),\n .\\not_strict_mode.app_rd_data_reg[93]_0 (\\not_strict_mode.app_rd_data_reg[93] ),\n .\\not_strict_mode.app_rd_data_reg[95]_0 (\\not_strict_mode.app_rd_data_reg[95] ),\n .\\not_strict_mode.app_rd_data_reg[97]_0 (\\not_strict_mode.app_rd_data_reg[97] ),\n .\\not_strict_mode.app_rd_data_reg[99]_0 (\\not_strict_mode.app_rd_data_reg[99] ),\n .\\not_strict_mode.app_rd_data_reg[9]_0 (\\not_strict_mode.app_rd_data_reg[9] ),\n .\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 (rd_data_buf_addr_r),\n .\\not_strict_mode.occupied_counter.occ_cnt_r_reg[1]_0 (ui_cmd0_n_16),\n .\\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 (occ_cnt_r),\n .\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 (ram_init_done_r),\n .pointer_wr_data(pointer_wr_data),\n .rd_accepted(rd_accepted),\n .\\rd_buf_indx.ram_init_done_r_lcl_reg_0 (ui_rd_data0_n_272),\n .rd_buf_we(rd_buf_we),\n .\\read_data_indx.rd_data_indx_r_reg[3] (\\read_data_indx.rd_data_indx_r_reg__0 ),\n .\\read_fifo.fifo_out_data_r_reg[7] (\\read_fifo.fifo_out_data_r_reg[7] ),\n .reset_reg(reset_reg),\n .\\s_axi_rdata[255] (\\s_axi_rdata[255] ));\n ddr3_ifmig_7series_v4_0_ui_wr_data ui_wr_data0\n (.ADDRD(pointer_wr_addr),\n .CLK(CLK),\n .D(D),\n .E(E),\n .Q(\\read_data_indx.rd_data_indx_r_reg__0 ),\n .accept_ns(accept_ns),\n .app_rdy_ns(app_rdy_ns),\n .app_wdf_data(app_wdf_data),\n .app_wdf_mask(app_wdf_mask),\n .\\cmd_pipe_plus.wr_data_addr_reg[3] (\\cmd_pipe_plus.wr_data_addr_reg[3] ),\n .mc_app_wdf_data_reg(mc_app_wdf_data_reg),\n .mc_app_wdf_mask_reg(mc_app_wdf_mask_reg),\n .\\mc_app_wdf_mask_reg_reg[0] (app_wdf_rdy),\n .mc_app_wdf_wren_reg(mc_app_wdf_wren_reg),\n .\\my_empty_reg[7] (\\my_empty_reg[7] ),\n .\\not_strict_mode.occupied_counter.occ_cnt_r_reg[4] (ui_rd_data0_n_264),\n .p_0_in(p_0_in),\n .pointer_we(pointer_we),\n .pointer_wr_data(pointer_wr_data),\n .ram_init_done_r(ram_init_done_r),\n .\\rd_buf_indx.ram_init_done_r_lcl_reg (ui_rd_data0_n_272),\n .\\read_data_indx.rd_data_upd_indx_r_reg_0 (ui_cmd0_n_13),\n .reset_reg(reset_reg),\n .w_cmd_rdy(w_cmd_rdy),\n .wr_accepted(wr_accepted),\n .wr_data_buf_addr(wr_data_buf_addr),\n .\\wr_req_counter.wr_req_cnt_r_reg[1]_0 (wr_req_cnt_r),\n .\\wr_req_counter.wr_req_cnt_r_reg[1]_1 (ui_cmd0_n_14),\n .wready_reg_rep__1(wready_reg_rep__1));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ui_wr_data\" *) \nmodule ddr3_ifmig_7series_v4_0_ui_wr_data\n (wr_data_buf_addr,\n p_0_in,\n \\mc_app_wdf_mask_reg_reg[0] ,\n app_rdy_ns,\n \\wr_req_counter.wr_req_cnt_r_reg[1]_0 ,\n Q,\n \\my_empty_reg[7] ,\n CLK,\n pointer_we,\n pointer_wr_data,\n ADDRD,\n \\cmd_pipe_plus.wr_data_addr_reg[3] ,\n E,\n mc_app_wdf_wren_reg,\n w_cmd_rdy,\n reset_reg,\n D,\n mc_app_wdf_mask_reg,\n wready_reg_rep__1,\n mc_app_wdf_data_reg,\n \\not_strict_mode.occupied_counter.occ_cnt_r_reg[4] ,\n accept_ns,\n wr_accepted,\n \\wr_req_counter.wr_req_cnt_r_reg[1]_1 ,\n \\read_data_indx.rd_data_upd_indx_r_reg_0 ,\n \\rd_buf_indx.ram_init_done_r_lcl_reg ,\n ram_init_done_r,\n app_wdf_data,\n app_wdf_mask);\n output [3:0]wr_data_buf_addr;\n output [0:0]p_0_in;\n output \\mc_app_wdf_mask_reg_reg[0] ;\n output app_rdy_ns;\n output [1:0]\\wr_req_counter.wr_req_cnt_r_reg[1]_0 ;\n output [3:0]Q;\n output [287:0]\\my_empty_reg[7] ;\n input CLK;\n input pointer_we;\n input [3:0]pointer_wr_data;\n input [3:0]ADDRD;\n input [3:0]\\cmd_pipe_plus.wr_data_addr_reg[3] ;\n input [0:0]E;\n input mc_app_wdf_wren_reg;\n input w_cmd_rdy;\n input reset_reg;\n input [31:0]D;\n input [31:0]mc_app_wdf_mask_reg;\n input [255:0]wready_reg_rep__1;\n input [255:0]mc_app_wdf_data_reg;\n input [0:0]\\not_strict_mode.occupied_counter.occ_cnt_r_reg[4] ;\n input accept_ns;\n input wr_accepted;\n input \\wr_req_counter.wr_req_cnt_r_reg[1]_1 ;\n input \\read_data_indx.rd_data_upd_indx_r_reg_0 ;\n input \\rd_buf_indx.ram_init_done_r_lcl_reg ;\n input ram_init_done_r;\n input [255:0]app_wdf_data;\n input [31:0]app_wdf_mask;\n\n wire [3:0]ADDRD;\n wire CLK;\n wire [31:0]D;\n wire [0:0]E;\n wire [3:0]Q;\n wire accept_ns;\n wire app_rdy_ns;\n wire app_rdy_r_i_2_n_0;\n wire app_rdy_r_i_3_n_0;\n wire [255:0]app_wdf_data;\n wire [255:0]app_wdf_data_r1;\n wire app_wdf_end_ns1;\n wire app_wdf_end_r1;\n wire [31:0]app_wdf_mask;\n wire [31:0]app_wdf_mask_r1;\n wire app_wdf_rdy_r_copy1;\n wire app_wdf_rdy_r_copy2;\n wire app_wdf_rdy_r_copy3;\n wire app_wdf_wren_ns1;\n wire app_wdf_wren_r1;\n wire [3:0]\\cmd_pipe_plus.wr_data_addr_reg[3] ;\n wire [3:0]\\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 ;\n wire [255:0]mc_app_wdf_data_reg;\n wire [31:0]mc_app_wdf_mask_reg;\n wire \\mc_app_wdf_mask_reg_reg[0] ;\n wire mc_app_wdf_wren_reg;\n wire [287:0]\\my_empty_reg[7] ;\n wire [0:0]\\not_strict_mode.occupied_counter.occ_cnt_r_reg[4] ;\n wire \\occupied_counter.occ_cnt[0]_i_1_n_0 ;\n wire \\occupied_counter.occ_cnt[10]_i_1_n_0 ;\n wire \\occupied_counter.occ_cnt[11]_i_1_n_0 ;\n wire \\occupied_counter.occ_cnt[12]_i_1_n_0 ;\n wire \\occupied_counter.occ_cnt[13]_i_1_n_0 ;\n wire \\occupied_counter.occ_cnt[14]_i_1_n_0 ;\n wire \\occupied_counter.occ_cnt[15]_i_1_n_0 ;\n wire \\occupied_counter.occ_cnt[15]_i_2_n_0 ;\n wire \\occupied_counter.occ_cnt[1]_i_1_n_0 ;\n wire \\occupied_counter.occ_cnt[2]_i_1_n_0 ;\n wire \\occupied_counter.occ_cnt[3]_i_1_n_0 ;\n wire \\occupied_counter.occ_cnt[4]_i_1_n_0 ;\n wire \\occupied_counter.occ_cnt[5]_i_1_n_0 ;\n wire \\occupied_counter.occ_cnt[6]_i_1_n_0 ;\n wire \\occupied_counter.occ_cnt[7]_i_1_n_0 ;\n wire \\occupied_counter.occ_cnt[8]_i_1_n_0 ;\n wire \\occupied_counter.occ_cnt[9]_i_1_n_0 ;\n wire \\occupied_counter.occ_cnt_reg_n_0_[0] ;\n wire \\occupied_counter.occ_cnt_reg_n_0_[10] ;\n wire \\occupied_counter.occ_cnt_reg_n_0_[11] ;\n wire \\occupied_counter.occ_cnt_reg_n_0_[12] ;\n wire \\occupied_counter.occ_cnt_reg_n_0_[13] ;\n wire \\occupied_counter.occ_cnt_reg_n_0_[15] ;\n wire \\occupied_counter.occ_cnt_reg_n_0_[1] ;\n wire \\occupied_counter.occ_cnt_reg_n_0_[2] ;\n wire \\occupied_counter.occ_cnt_reg_n_0_[3] ;\n wire \\occupied_counter.occ_cnt_reg_n_0_[4] ;\n wire \\occupied_counter.occ_cnt_reg_n_0_[5] ;\n wire \\occupied_counter.occ_cnt_reg_n_0_[6] ;\n wire \\occupied_counter.occ_cnt_reg_n_0_[7] ;\n wire \\occupied_counter.occ_cnt_reg_n_0_[8] ;\n wire \\occupied_counter.occ_cnt_reg_n_0_[9] ;\n wire [0:0]p_0_in;\n wire [3:0]p_0_in__0;\n wire [1:1]p_0_in__0_0;\n wire [3:0]p_0_in__0__0;\n wire [3:0]p_0_in__1;\n wire p_4_in;\n wire pointer_we;\n wire [3:0]pointer_wr_data;\n wire ram_init_done_r;\n wire \\rd_buf_indx.ram_init_done_r_lcl_reg ;\n wire \\read_data_indx.rd_data_upd_indx_r_reg_0 ;\n wire reset_reg;\n wire w_cmd_rdy;\n wire wb_wr_data_addr0_ns;\n wire wb_wr_data_addr0_r;\n wire [4:1]wb_wr_data_addr_r;\n wire [4:1]wb_wr_data_addr_w;\n wire wdf_rdy_ns;\n wire wr_accepted;\n wire [287:0]wr_buf_in_data;\n wire [287:0]wr_buf_out_data_w;\n wire wr_data_addr_le;\n wire [3:0]wr_data_buf_addr;\n wire [3:0]wr_data_pntr;\n wire [4:2]wr_req_cnt_r;\n wire \\wr_req_counter.wr_req_cnt_r[0]_i_1_n_0 ;\n wire \\wr_req_counter.wr_req_cnt_r[1]_i_1_n_0 ;\n wire \\wr_req_counter.wr_req_cnt_r[2]_i_1_n_0 ;\n wire \\wr_req_counter.wr_req_cnt_r[3]_i_1_n_0 ;\n wire \\wr_req_counter.wr_req_cnt_r[4]_i_1_n_0 ;\n wire \\wr_req_counter.wr_req_cnt_r[4]_i_2_n_0 ;\n wire [1:0]\\wr_req_counter.wr_req_cnt_r_reg[1]_0 ;\n wire \\wr_req_counter.wr_req_cnt_r_reg[1]_1 ;\n wire [255:0]wready_reg_rep__1;\n wire [3:0]\\write_data_control.wr_data_indx_r_reg__0 ;\n wire [1:0]\\NLW_pointer_ram.rams[0].RAM32M0_DOA_UNCONNECTED ;\n wire [1:0]\\NLW_pointer_ram.rams[0].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_pointer_ram.rams[1].RAM32M0_DOA_UNCONNECTED ;\n wire [1:0]\\NLW_pointer_ram.rams[1].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[0].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[10].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[11].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[12].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[13].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[14].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[15].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[16].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[17].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[18].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[19].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[1].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[20].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[21].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[22].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[23].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[24].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[25].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[26].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[27].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[28].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[29].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[2].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[30].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[31].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[32].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[33].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[34].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[35].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[36].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[37].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[38].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[39].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[3].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[40].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[41].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[42].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[43].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[44].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[45].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[46].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[47].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[4].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[5].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[6].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[7].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[8].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[9].RAM32M0_DOD_UNCONNECTED ;\n\n LUT5 #(\n .INIT(32'h44440444)) \n app_rdy_r_i_1\n (.I0(\\not_strict_mode.occupied_counter.occ_cnt_r_reg[4] ),\n .I1(accept_ns),\n .I2(app_rdy_r_i_2_n_0),\n .I3(app_rdy_r_i_3_n_0),\n .I4(\\wr_req_counter.wr_req_cnt_r[3]_i_1_n_0 ),\n .O(app_rdy_ns));\n LUT6 #(\n .INIT(64'hFFFF00007FFE8001)) \n app_rdy_r_i_2\n (.I0(wr_req_cnt_r[3]),\n .I1(wr_req_cnt_r[2]),\n .I2(\\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]),\n .I3(\\wr_req_counter.wr_req_cnt_r_reg[1]_1 ),\n .I4(wr_req_cnt_r[4]),\n .I5(\\read_data_indx.rd_data_upd_indx_r_reg_0 ),\n .O(app_rdy_r_i_2_n_0));\n LUT6 #(\n .INIT(64'h0040010000001001)) \n app_rdy_r_i_3\n (.I0(reset_reg),\n .I1(wr_req_cnt_r[2]),\n .I2(wr_accepted),\n .I3(p_0_in),\n .I4(\\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]),\n .I5(\\wr_req_counter.wr_req_cnt_r_reg[1]_0 [0]),\n .O(app_rdy_r_i_3_n_0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[0] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[0]),\n .Q(app_wdf_data_r1[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[100] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[100]),\n .Q(app_wdf_data_r1[100]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[101] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[101]),\n .Q(app_wdf_data_r1[101]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[102] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[102]),\n .Q(app_wdf_data_r1[102]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[103] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[103]),\n .Q(app_wdf_data_r1[103]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[104] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[104]),\n .Q(app_wdf_data_r1[104]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[105] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[105]),\n .Q(app_wdf_data_r1[105]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[106] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[106]),\n .Q(app_wdf_data_r1[106]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[107] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[107]),\n .Q(app_wdf_data_r1[107]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[108] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[108]),\n .Q(app_wdf_data_r1[108]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[109] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[109]),\n .Q(app_wdf_data_r1[109]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[10] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[10]),\n .Q(app_wdf_data_r1[10]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[110] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[110]),\n .Q(app_wdf_data_r1[110]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[111] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[111]),\n .Q(app_wdf_data_r1[111]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[112] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[112]),\n .Q(app_wdf_data_r1[112]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[113] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[113]),\n .Q(app_wdf_data_r1[113]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[114] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[114]),\n .Q(app_wdf_data_r1[114]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[115] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[115]),\n .Q(app_wdf_data_r1[115]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[116] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[116]),\n .Q(app_wdf_data_r1[116]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[117] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[117]),\n .Q(app_wdf_data_r1[117]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[118] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[118]),\n .Q(app_wdf_data_r1[118]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[119] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[119]),\n .Q(app_wdf_data_r1[119]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[11] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[11]),\n .Q(app_wdf_data_r1[11]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[120] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[120]),\n .Q(app_wdf_data_r1[120]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[121] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[121]),\n .Q(app_wdf_data_r1[121]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[122] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[122]),\n .Q(app_wdf_data_r1[122]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[123] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[123]),\n .Q(app_wdf_data_r1[123]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[124] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[124]),\n .Q(app_wdf_data_r1[124]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[125] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[125]),\n .Q(app_wdf_data_r1[125]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[126] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[126]),\n .Q(app_wdf_data_r1[126]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[127] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[127]),\n .Q(app_wdf_data_r1[127]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[128] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[128]),\n .Q(app_wdf_data_r1[128]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[129] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[129]),\n .Q(app_wdf_data_r1[129]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[12] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[12]),\n .Q(app_wdf_data_r1[12]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[130] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[130]),\n .Q(app_wdf_data_r1[130]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[131] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[131]),\n .Q(app_wdf_data_r1[131]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[132] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[132]),\n .Q(app_wdf_data_r1[132]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[133] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[133]),\n .Q(app_wdf_data_r1[133]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[134] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[134]),\n .Q(app_wdf_data_r1[134]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[135] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[135]),\n .Q(app_wdf_data_r1[135]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[136] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[136]),\n .Q(app_wdf_data_r1[136]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[137] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[137]),\n .Q(app_wdf_data_r1[137]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[138] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[138]),\n .Q(app_wdf_data_r1[138]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[139] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[139]),\n .Q(app_wdf_data_r1[139]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[13] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[13]),\n .Q(app_wdf_data_r1[13]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[140] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[140]),\n .Q(app_wdf_data_r1[140]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[141] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[141]),\n .Q(app_wdf_data_r1[141]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[142] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[142]),\n .Q(app_wdf_data_r1[142]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[143] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[143]),\n .Q(app_wdf_data_r1[143]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[144] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[144]),\n .Q(app_wdf_data_r1[144]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[145] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[145]),\n .Q(app_wdf_data_r1[145]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[146] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[146]),\n .Q(app_wdf_data_r1[146]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[147] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[147]),\n .Q(app_wdf_data_r1[147]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[148] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[148]),\n .Q(app_wdf_data_r1[148]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[149] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[149]),\n .Q(app_wdf_data_r1[149]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[14] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[14]),\n .Q(app_wdf_data_r1[14]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[150] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[150]),\n .Q(app_wdf_data_r1[150]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[151] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[151]),\n .Q(app_wdf_data_r1[151]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[152] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[152]),\n .Q(app_wdf_data_r1[152]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[153] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[153]),\n .Q(app_wdf_data_r1[153]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[154] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[154]),\n .Q(app_wdf_data_r1[154]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[155] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[155]),\n .Q(app_wdf_data_r1[155]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[156] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[156]),\n .Q(app_wdf_data_r1[156]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[157] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[157]),\n .Q(app_wdf_data_r1[157]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[158] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[158]),\n .Q(app_wdf_data_r1[158]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[159] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[159]),\n .Q(app_wdf_data_r1[159]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[15] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[15]),\n .Q(app_wdf_data_r1[15]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[160] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[160]),\n .Q(app_wdf_data_r1[160]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[161] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[161]),\n .Q(app_wdf_data_r1[161]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[162] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[162]),\n .Q(app_wdf_data_r1[162]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[163] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[163]),\n .Q(app_wdf_data_r1[163]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[164] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[164]),\n .Q(app_wdf_data_r1[164]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[165] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[165]),\n .Q(app_wdf_data_r1[165]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[166] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[166]),\n .Q(app_wdf_data_r1[166]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[167] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[167]),\n .Q(app_wdf_data_r1[167]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[168] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[168]),\n .Q(app_wdf_data_r1[168]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[169] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[169]),\n .Q(app_wdf_data_r1[169]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[16] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[16]),\n .Q(app_wdf_data_r1[16]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[170] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[170]),\n .Q(app_wdf_data_r1[170]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[171] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[171]),\n .Q(app_wdf_data_r1[171]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[172] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[172]),\n .Q(app_wdf_data_r1[172]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[173] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[173]),\n .Q(app_wdf_data_r1[173]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[174] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[174]),\n .Q(app_wdf_data_r1[174]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[175] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[175]),\n .Q(app_wdf_data_r1[175]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[176] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[176]),\n .Q(app_wdf_data_r1[176]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[177] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[177]),\n .Q(app_wdf_data_r1[177]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[178] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[178]),\n .Q(app_wdf_data_r1[178]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[179] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[179]),\n .Q(app_wdf_data_r1[179]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[17] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[17]),\n .Q(app_wdf_data_r1[17]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[180] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[180]),\n .Q(app_wdf_data_r1[180]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[181] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[181]),\n .Q(app_wdf_data_r1[181]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[182] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[182]),\n .Q(app_wdf_data_r1[182]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[183] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[183]),\n .Q(app_wdf_data_r1[183]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[184] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[184]),\n .Q(app_wdf_data_r1[184]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[185] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[185]),\n .Q(app_wdf_data_r1[185]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[186] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[186]),\n .Q(app_wdf_data_r1[186]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[187] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[187]),\n .Q(app_wdf_data_r1[187]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[188] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[188]),\n .Q(app_wdf_data_r1[188]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[189] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[189]),\n .Q(app_wdf_data_r1[189]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[18] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[18]),\n .Q(app_wdf_data_r1[18]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[190] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[190]),\n .Q(app_wdf_data_r1[190]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[191] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[191]),\n .Q(app_wdf_data_r1[191]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[192] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[192]),\n .Q(app_wdf_data_r1[192]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[193] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[193]),\n .Q(app_wdf_data_r1[193]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[194] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[194]),\n .Q(app_wdf_data_r1[194]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[195] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[195]),\n .Q(app_wdf_data_r1[195]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[196] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[196]),\n .Q(app_wdf_data_r1[196]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[197] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[197]),\n .Q(app_wdf_data_r1[197]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[198] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[198]),\n .Q(app_wdf_data_r1[198]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[199] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[199]),\n .Q(app_wdf_data_r1[199]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[19] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[19]),\n .Q(app_wdf_data_r1[19]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[1] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[1]),\n .Q(app_wdf_data_r1[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[200] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[200]),\n .Q(app_wdf_data_r1[200]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[201] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[201]),\n .Q(app_wdf_data_r1[201]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[202] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[202]),\n .Q(app_wdf_data_r1[202]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[203] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[203]),\n .Q(app_wdf_data_r1[203]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[204] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[204]),\n .Q(app_wdf_data_r1[204]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[205] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[205]),\n .Q(app_wdf_data_r1[205]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[206] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[206]),\n .Q(app_wdf_data_r1[206]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[207] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[207]),\n .Q(app_wdf_data_r1[207]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[208] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[208]),\n .Q(app_wdf_data_r1[208]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[209] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[209]),\n .Q(app_wdf_data_r1[209]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[20] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[20]),\n .Q(app_wdf_data_r1[20]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[210] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[210]),\n .Q(app_wdf_data_r1[210]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[211] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[211]),\n .Q(app_wdf_data_r1[211]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[212] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[212]),\n .Q(app_wdf_data_r1[212]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[213] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[213]),\n .Q(app_wdf_data_r1[213]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[214] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[214]),\n .Q(app_wdf_data_r1[214]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[215] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[215]),\n .Q(app_wdf_data_r1[215]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[216] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[216]),\n .Q(app_wdf_data_r1[216]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[217] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[217]),\n .Q(app_wdf_data_r1[217]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[218] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[218]),\n .Q(app_wdf_data_r1[218]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[219] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[219]),\n .Q(app_wdf_data_r1[219]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[21] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[21]),\n .Q(app_wdf_data_r1[21]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[220] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[220]),\n .Q(app_wdf_data_r1[220]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[221] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[221]),\n .Q(app_wdf_data_r1[221]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[222] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[222]),\n .Q(app_wdf_data_r1[222]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[223] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[223]),\n .Q(app_wdf_data_r1[223]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[224] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[224]),\n .Q(app_wdf_data_r1[224]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[225] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[225]),\n .Q(app_wdf_data_r1[225]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[226] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[226]),\n .Q(app_wdf_data_r1[226]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[227] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[227]),\n .Q(app_wdf_data_r1[227]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[228] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[228]),\n .Q(app_wdf_data_r1[228]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[229] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[229]),\n .Q(app_wdf_data_r1[229]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[22] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[22]),\n .Q(app_wdf_data_r1[22]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[230] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[230]),\n .Q(app_wdf_data_r1[230]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[231] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[231]),\n .Q(app_wdf_data_r1[231]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[232] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[232]),\n .Q(app_wdf_data_r1[232]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[233] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[233]),\n .Q(app_wdf_data_r1[233]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[234] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[234]),\n .Q(app_wdf_data_r1[234]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[235] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[235]),\n .Q(app_wdf_data_r1[235]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[236] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[236]),\n .Q(app_wdf_data_r1[236]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[237] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[237]),\n .Q(app_wdf_data_r1[237]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[238] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[238]),\n .Q(app_wdf_data_r1[238]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[239] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[239]),\n .Q(app_wdf_data_r1[239]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[23] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[23]),\n .Q(app_wdf_data_r1[23]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[240] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[240]),\n .Q(app_wdf_data_r1[240]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[241] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[241]),\n .Q(app_wdf_data_r1[241]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[242] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[242]),\n .Q(app_wdf_data_r1[242]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[243] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[243]),\n .Q(app_wdf_data_r1[243]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[244] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[244]),\n .Q(app_wdf_data_r1[244]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[245] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[245]),\n .Q(app_wdf_data_r1[245]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[246] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[246]),\n .Q(app_wdf_data_r1[246]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[247] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[247]),\n .Q(app_wdf_data_r1[247]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[248] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[248]),\n .Q(app_wdf_data_r1[248]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[249] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[249]),\n .Q(app_wdf_data_r1[249]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[24] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[24]),\n .Q(app_wdf_data_r1[24]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[250] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[250]),\n .Q(app_wdf_data_r1[250]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[251] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[251]),\n .Q(app_wdf_data_r1[251]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[252] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[252]),\n .Q(app_wdf_data_r1[252]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[253] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[253]),\n .Q(app_wdf_data_r1[253]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[254] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[254]),\n .Q(app_wdf_data_r1[254]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[255] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[255]),\n .Q(app_wdf_data_r1[255]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[25] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[25]),\n .Q(app_wdf_data_r1[25]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[26] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[26]),\n .Q(app_wdf_data_r1[26]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[27] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[27]),\n .Q(app_wdf_data_r1[27]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[28] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[28]),\n .Q(app_wdf_data_r1[28]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[29] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[29]),\n .Q(app_wdf_data_r1[29]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[2] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[2]),\n .Q(app_wdf_data_r1[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[30] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[30]),\n .Q(app_wdf_data_r1[30]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[31] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[31]),\n .Q(app_wdf_data_r1[31]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[32] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[32]),\n .Q(app_wdf_data_r1[32]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[33] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[33]),\n .Q(app_wdf_data_r1[33]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[34] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[34]),\n .Q(app_wdf_data_r1[34]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[35] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[35]),\n .Q(app_wdf_data_r1[35]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[36] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[36]),\n .Q(app_wdf_data_r1[36]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[37] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[37]),\n .Q(app_wdf_data_r1[37]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[38] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[38]),\n .Q(app_wdf_data_r1[38]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[39] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[39]),\n .Q(app_wdf_data_r1[39]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[3] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[3]),\n .Q(app_wdf_data_r1[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[40] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[40]),\n .Q(app_wdf_data_r1[40]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[41] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[41]),\n .Q(app_wdf_data_r1[41]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[42] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[42]),\n .Q(app_wdf_data_r1[42]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[43] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[43]),\n .Q(app_wdf_data_r1[43]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[44] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[44]),\n .Q(app_wdf_data_r1[44]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[45] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[45]),\n .Q(app_wdf_data_r1[45]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[46] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[46]),\n .Q(app_wdf_data_r1[46]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[47] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[47]),\n .Q(app_wdf_data_r1[47]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[48] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[48]),\n .Q(app_wdf_data_r1[48]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[49] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[49]),\n .Q(app_wdf_data_r1[49]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[4] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[4]),\n .Q(app_wdf_data_r1[4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[50] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[50]),\n .Q(app_wdf_data_r1[50]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[51] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[51]),\n .Q(app_wdf_data_r1[51]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[52] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[52]),\n .Q(app_wdf_data_r1[52]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[53] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[53]),\n .Q(app_wdf_data_r1[53]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[54] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[54]),\n .Q(app_wdf_data_r1[54]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[55] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[55]),\n .Q(app_wdf_data_r1[55]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[56] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[56]),\n .Q(app_wdf_data_r1[56]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[57] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[57]),\n .Q(app_wdf_data_r1[57]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[58] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[58]),\n .Q(app_wdf_data_r1[58]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[59] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[59]),\n .Q(app_wdf_data_r1[59]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[5] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[5]),\n .Q(app_wdf_data_r1[5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[60] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[60]),\n .Q(app_wdf_data_r1[60]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[61] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[61]),\n .Q(app_wdf_data_r1[61]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[62] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[62]),\n .Q(app_wdf_data_r1[62]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[63] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[63]),\n .Q(app_wdf_data_r1[63]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[64] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[64]),\n .Q(app_wdf_data_r1[64]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[65] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[65]),\n .Q(app_wdf_data_r1[65]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[66] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[66]),\n .Q(app_wdf_data_r1[66]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[67] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[67]),\n .Q(app_wdf_data_r1[67]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[68] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[68]),\n .Q(app_wdf_data_r1[68]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[69] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[69]),\n .Q(app_wdf_data_r1[69]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[6] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[6]),\n .Q(app_wdf_data_r1[6]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[70] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[70]),\n .Q(app_wdf_data_r1[70]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[71] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[71]),\n .Q(app_wdf_data_r1[71]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[72] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[72]),\n .Q(app_wdf_data_r1[72]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[73] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[73]),\n .Q(app_wdf_data_r1[73]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[74] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[74]),\n .Q(app_wdf_data_r1[74]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[75] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[75]),\n .Q(app_wdf_data_r1[75]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[76] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[76]),\n .Q(app_wdf_data_r1[76]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[77] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[77]),\n .Q(app_wdf_data_r1[77]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[78] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[78]),\n .Q(app_wdf_data_r1[78]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[79] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[79]),\n .Q(app_wdf_data_r1[79]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[7] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[7]),\n .Q(app_wdf_data_r1[7]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[80] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[80]),\n .Q(app_wdf_data_r1[80]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[81] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[81]),\n .Q(app_wdf_data_r1[81]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[82] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[82]),\n .Q(app_wdf_data_r1[82]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[83] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[83]),\n .Q(app_wdf_data_r1[83]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[84] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[84]),\n .Q(app_wdf_data_r1[84]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[85] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[85]),\n .Q(app_wdf_data_r1[85]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[86] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[86]),\n .Q(app_wdf_data_r1[86]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[87] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[87]),\n .Q(app_wdf_data_r1[87]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[88] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[88]),\n .Q(app_wdf_data_r1[88]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[89] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[89]),\n .Q(app_wdf_data_r1[89]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[8] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[8]),\n .Q(app_wdf_data_r1[8]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[90] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[90]),\n .Q(app_wdf_data_r1[90]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[91] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[91]),\n .Q(app_wdf_data_r1[91]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[92] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[92]),\n .Q(app_wdf_data_r1[92]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[93] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[93]),\n .Q(app_wdf_data_r1[93]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[94] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[94]),\n .Q(app_wdf_data_r1[94]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[95] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[95]),\n .Q(app_wdf_data_r1[95]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[96] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[96]),\n .Q(app_wdf_data_r1[96]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[97] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[97]),\n .Q(app_wdf_data_r1[97]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[98] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[98]),\n .Q(app_wdf_data_r1[98]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[99] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[99]),\n .Q(app_wdf_data_r1[99]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_data_r1_reg[9] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[9]),\n .Q(app_wdf_data_r1[9]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00E200E200FF0000)) \n app_wdf_end_r1_i_1\n (.I0(mc_app_wdf_wren_reg),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(w_cmd_rdy),\n .I3(reset_reg),\n .I4(app_wdf_end_r1),\n .I5(app_wdf_rdy_r_copy2),\n .O(app_wdf_end_ns1));\n FDRE #(\n .INIT(1'b0)) \n app_wdf_end_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(app_wdf_end_ns1),\n .Q(app_wdf_end_r1),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_mask_r1_reg[0] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[0]),\n .Q(app_wdf_mask_r1[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_mask_r1_reg[10] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[10]),\n .Q(app_wdf_mask_r1[10]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_mask_r1_reg[11] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[11]),\n .Q(app_wdf_mask_r1[11]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_mask_r1_reg[12] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[12]),\n .Q(app_wdf_mask_r1[12]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_mask_r1_reg[13] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[13]),\n .Q(app_wdf_mask_r1[13]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_mask_r1_reg[14] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[14]),\n .Q(app_wdf_mask_r1[14]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_mask_r1_reg[15] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[15]),\n .Q(app_wdf_mask_r1[15]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_mask_r1_reg[16] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[16]),\n .Q(app_wdf_mask_r1[16]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_mask_r1_reg[17] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[17]),\n .Q(app_wdf_mask_r1[17]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_mask_r1_reg[18] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[18]),\n .Q(app_wdf_mask_r1[18]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_mask_r1_reg[19] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[19]),\n .Q(app_wdf_mask_r1[19]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_mask_r1_reg[1] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[1]),\n .Q(app_wdf_mask_r1[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_mask_r1_reg[20] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[20]),\n .Q(app_wdf_mask_r1[20]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_mask_r1_reg[21] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[21]),\n .Q(app_wdf_mask_r1[21]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_mask_r1_reg[22] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[22]),\n .Q(app_wdf_mask_r1[22]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_mask_r1_reg[23] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[23]),\n .Q(app_wdf_mask_r1[23]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_mask_r1_reg[24] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[24]),\n .Q(app_wdf_mask_r1[24]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_mask_r1_reg[25] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[25]),\n .Q(app_wdf_mask_r1[25]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_mask_r1_reg[26] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[26]),\n .Q(app_wdf_mask_r1[26]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_mask_r1_reg[27] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[27]),\n .Q(app_wdf_mask_r1[27]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_mask_r1_reg[28] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[28]),\n .Q(app_wdf_mask_r1[28]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_mask_r1_reg[29] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[29]),\n .Q(app_wdf_mask_r1[29]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_mask_r1_reg[2] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[2]),\n .Q(app_wdf_mask_r1[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_mask_r1_reg[30] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[30]),\n .Q(app_wdf_mask_r1[30]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_mask_r1_reg[31] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[31]),\n .Q(app_wdf_mask_r1[31]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_mask_r1_reg[3] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[3]),\n .Q(app_wdf_mask_r1[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_mask_r1_reg[4] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[4]),\n .Q(app_wdf_mask_r1[4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_mask_r1_reg[5] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[5]),\n .Q(app_wdf_mask_r1[5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_mask_r1_reg[6] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[6]),\n .Q(app_wdf_mask_r1[6]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_mask_r1_reg[7] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[7]),\n .Q(app_wdf_mask_r1[7]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_mask_r1_reg[8] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[8]),\n .Q(app_wdf_mask_r1[8]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\app_wdf_mask_r1_reg[9] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[9]),\n .Q(app_wdf_mask_r1[9]),\n .R(1'b0));\n (* equivalent_register_removal = \"no\" *) \n FDRE #(\n .INIT(1'b0)) \n app_wdf_rdy_r_copy1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wdf_rdy_ns),\n .Q(app_wdf_rdy_r_copy1),\n .R(1'b0));\n (* equivalent_register_removal = \"no\" *) \n FDRE #(\n .INIT(1'b0)) \n app_wdf_rdy_r_copy2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wdf_rdy_ns),\n .Q(app_wdf_rdy_r_copy2),\n .R(1'b0));\n (* equivalent_register_removal = \"no\" *) \n FDRE #(\n .INIT(1'b0)) \n app_wdf_rdy_r_copy3_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wdf_rdy_ns),\n .Q(app_wdf_rdy_r_copy3),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00E200E200FF0000)) \n app_wdf_wren_r1_i_1\n (.I0(mc_app_wdf_wren_reg),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(w_cmd_rdy),\n .I3(reset_reg),\n .I4(app_wdf_wren_r1),\n .I5(app_wdf_rdy_r_copy2),\n .O(app_wdf_wren_ns1));\n FDRE #(\n .INIT(1'b0)) \n app_wdf_wren_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(app_wdf_wren_ns1),\n .Q(app_wdf_wren_r1),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1486\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\data_buf_address_counter.data_buf_addr_cnt_r[0]_i_1 \n (.I0(\\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [0]),\n .O(p_0_in__0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1486\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\data_buf_address_counter.data_buf_addr_cnt_r[1]_i_1 \n (.I0(\\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [0]),\n .I1(\\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [1]),\n .O(p_0_in__0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1484\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\data_buf_address_counter.data_buf_addr_cnt_r[2]_i_1 \n (.I0(\\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [0]),\n .I1(\\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [1]),\n .I2(\\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [2]),\n .O(p_0_in__0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1484\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\data_buf_address_counter.data_buf_addr_cnt_r[3]_i_2 \n (.I0(\\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [2]),\n .I1(\\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [1]),\n .I2(\\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [0]),\n .I3(\\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [3]),\n .O(p_0_in__0[3]));\n FDRE #(\n .INIT(1'b0)) \n \\data_buf_address_counter.data_buf_addr_cnt_r_reg[0] \n (.C(CLK),\n .CE(wr_accepted),\n .D(p_0_in__0[0]),\n .Q(\\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [0]),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\data_buf_address_counter.data_buf_addr_cnt_r_reg[1] \n (.C(CLK),\n .CE(wr_accepted),\n .D(p_0_in__0[1]),\n .Q(\\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [1]),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\data_buf_address_counter.data_buf_addr_cnt_r_reg[2] \n (.C(CLK),\n .CE(wr_accepted),\n .D(p_0_in__0[2]),\n .Q(\\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [2]),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\data_buf_address_counter.data_buf_addr_cnt_r_reg[3] \n (.C(CLK),\n .CE(wr_accepted),\n .D(p_0_in__0[3]),\n .Q(\\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [3]),\n .R(reset_reg));\n (* equivalent_register_removal = \"no\" *) \n FDRE #(\n .INIT(1'b0)) \n \\occupied_counter.app_wdf_rdy_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(wdf_rdy_ns),\n .Q(\\mc_app_wdf_mask_reg_reg[0] ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1481\" *) \n LUT4 #(\n .INIT(16'hEAAA)) \n \\occupied_counter.occ_cnt[0]_i_1 \n (.I0(\\occupied_counter.occ_cnt_reg_n_0_[1] ),\n .I1(app_wdf_rdy_r_copy1),\n .I2(app_wdf_end_r1),\n .I3(app_wdf_wren_r1),\n .O(\\occupied_counter.occ_cnt[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hBFFF8000)) \n \\occupied_counter.occ_cnt[10]_i_1 \n (.I0(\\occupied_counter.occ_cnt_reg_n_0_[9] ),\n .I1(app_wdf_wren_r1),\n .I2(app_wdf_end_r1),\n .I3(app_wdf_rdy_r_copy1),\n .I4(\\occupied_counter.occ_cnt_reg_n_0_[11] ),\n .O(\\occupied_counter.occ_cnt[10]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hBFFF8000)) \n \\occupied_counter.occ_cnt[11]_i_1 \n (.I0(\\occupied_counter.occ_cnt_reg_n_0_[10] ),\n .I1(app_wdf_wren_r1),\n .I2(app_wdf_end_r1),\n .I3(app_wdf_rdy_r_copy1),\n .I4(\\occupied_counter.occ_cnt_reg_n_0_[12] ),\n .O(\\occupied_counter.occ_cnt[11]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hBFFF8000)) \n \\occupied_counter.occ_cnt[12]_i_1 \n (.I0(\\occupied_counter.occ_cnt_reg_n_0_[11] ),\n .I1(app_wdf_wren_r1),\n .I2(app_wdf_end_r1),\n .I3(app_wdf_rdy_r_copy1),\n .I4(\\occupied_counter.occ_cnt_reg_n_0_[13] ),\n .O(\\occupied_counter.occ_cnt[12]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1482\" *) \n LUT5 #(\n .INIT(32'hBFFF8000)) \n \\occupied_counter.occ_cnt[13]_i_1 \n (.I0(\\occupied_counter.occ_cnt_reg_n_0_[12] ),\n .I1(app_wdf_wren_r1),\n .I2(app_wdf_end_r1),\n .I3(app_wdf_rdy_r_copy1),\n .I4(p_4_in),\n .O(\\occupied_counter.occ_cnt[13]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hBFFF8000)) \n \\occupied_counter.occ_cnt[14]_i_1 \n (.I0(\\occupied_counter.occ_cnt_reg_n_0_[13] ),\n .I1(app_wdf_wren_r1),\n .I2(app_wdf_end_r1),\n .I3(app_wdf_rdy_r_copy1),\n .I4(\\occupied_counter.occ_cnt_reg_n_0_[15] ),\n .O(\\occupied_counter.occ_cnt[14]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h6AAA)) \n \\occupied_counter.occ_cnt[15]_i_1 \n (.I0(p_0_in),\n .I1(app_wdf_rdy_r_copy1),\n .I2(app_wdf_end_r1),\n .I3(app_wdf_wren_r1),\n .O(\\occupied_counter.occ_cnt[15]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1482\" *) \n LUT4 #(\n .INIT(16'h8000)) \n \\occupied_counter.occ_cnt[15]_i_2 \n (.I0(app_wdf_wren_r1),\n .I1(app_wdf_end_r1),\n .I2(app_wdf_rdy_r_copy1),\n .I3(p_4_in),\n .O(\\occupied_counter.occ_cnt[15]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hBFFF8000)) \n \\occupied_counter.occ_cnt[1]_i_1 \n (.I0(\\occupied_counter.occ_cnt_reg_n_0_[0] ),\n .I1(app_wdf_wren_r1),\n .I2(app_wdf_end_r1),\n .I3(app_wdf_rdy_r_copy1),\n .I4(\\occupied_counter.occ_cnt_reg_n_0_[2] ),\n .O(\\occupied_counter.occ_cnt[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1481\" *) \n LUT5 #(\n .INIT(32'hBFFF8000)) \n \\occupied_counter.occ_cnt[2]_i_1 \n (.I0(\\occupied_counter.occ_cnt_reg_n_0_[1] ),\n .I1(app_wdf_wren_r1),\n .I2(app_wdf_end_r1),\n .I3(app_wdf_rdy_r_copy1),\n .I4(\\occupied_counter.occ_cnt_reg_n_0_[3] ),\n .O(\\occupied_counter.occ_cnt[2]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hBFFF8000)) \n \\occupied_counter.occ_cnt[3]_i_1 \n (.I0(\\occupied_counter.occ_cnt_reg_n_0_[2] ),\n .I1(app_wdf_wren_r1),\n .I2(app_wdf_end_r1),\n .I3(app_wdf_rdy_r_copy1),\n .I4(\\occupied_counter.occ_cnt_reg_n_0_[4] ),\n .O(\\occupied_counter.occ_cnt[3]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hBFFF8000)) \n \\occupied_counter.occ_cnt[4]_i_1 \n (.I0(\\occupied_counter.occ_cnt_reg_n_0_[3] ),\n .I1(app_wdf_wren_r1),\n .I2(app_wdf_end_r1),\n .I3(app_wdf_rdy_r_copy1),\n .I4(\\occupied_counter.occ_cnt_reg_n_0_[5] ),\n .O(\\occupied_counter.occ_cnt[4]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hBFFF8000)) \n \\occupied_counter.occ_cnt[5]_i_1 \n (.I0(\\occupied_counter.occ_cnt_reg_n_0_[4] ),\n .I1(app_wdf_wren_r1),\n .I2(app_wdf_end_r1),\n .I3(app_wdf_rdy_r_copy1),\n .I4(\\occupied_counter.occ_cnt_reg_n_0_[6] ),\n .O(\\occupied_counter.occ_cnt[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hBFFF8000)) \n \\occupied_counter.occ_cnt[6]_i_1 \n (.I0(\\occupied_counter.occ_cnt_reg_n_0_[5] ),\n .I1(app_wdf_wren_r1),\n .I2(app_wdf_end_r1),\n .I3(app_wdf_rdy_r_copy1),\n .I4(\\occupied_counter.occ_cnt_reg_n_0_[7] ),\n .O(\\occupied_counter.occ_cnt[6]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hBFFF8000)) \n \\occupied_counter.occ_cnt[7]_i_1 \n (.I0(\\occupied_counter.occ_cnt_reg_n_0_[6] ),\n .I1(app_wdf_wren_r1),\n .I2(app_wdf_end_r1),\n .I3(app_wdf_rdy_r_copy1),\n .I4(\\occupied_counter.occ_cnt_reg_n_0_[8] ),\n .O(\\occupied_counter.occ_cnt[7]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1479\" *) \n LUT5 #(\n .INIT(32'hBFFF8000)) \n \\occupied_counter.occ_cnt[8]_i_1 \n (.I0(\\occupied_counter.occ_cnt_reg_n_0_[7] ),\n .I1(app_wdf_wren_r1),\n .I2(app_wdf_end_r1),\n .I3(app_wdf_rdy_r_copy1),\n .I4(\\occupied_counter.occ_cnt_reg_n_0_[9] ),\n .O(\\occupied_counter.occ_cnt[8]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hBFFF8000)) \n \\occupied_counter.occ_cnt[9]_i_1 \n (.I0(\\occupied_counter.occ_cnt_reg_n_0_[8] ),\n .I1(app_wdf_wren_r1),\n .I2(app_wdf_end_r1),\n .I3(app_wdf_rdy_r_copy1),\n .I4(\\occupied_counter.occ_cnt_reg_n_0_[10] ),\n .O(\\occupied_counter.occ_cnt[9]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\occupied_counter.occ_cnt_reg[0] \n (.C(CLK),\n .CE(\\occupied_counter.occ_cnt[15]_i_1_n_0 ),\n .D(\\occupied_counter.occ_cnt[0]_i_1_n_0 ),\n .Q(\\occupied_counter.occ_cnt_reg_n_0_[0] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\occupied_counter.occ_cnt_reg[10] \n (.C(CLK),\n .CE(\\occupied_counter.occ_cnt[15]_i_1_n_0 ),\n .D(\\occupied_counter.occ_cnt[10]_i_1_n_0 ),\n .Q(\\occupied_counter.occ_cnt_reg_n_0_[10] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\occupied_counter.occ_cnt_reg[11] \n (.C(CLK),\n .CE(\\occupied_counter.occ_cnt[15]_i_1_n_0 ),\n .D(\\occupied_counter.occ_cnt[11]_i_1_n_0 ),\n .Q(\\occupied_counter.occ_cnt_reg_n_0_[11] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\occupied_counter.occ_cnt_reg[12] \n (.C(CLK),\n .CE(\\occupied_counter.occ_cnt[15]_i_1_n_0 ),\n .D(\\occupied_counter.occ_cnt[12]_i_1_n_0 ),\n .Q(\\occupied_counter.occ_cnt_reg_n_0_[12] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\occupied_counter.occ_cnt_reg[13] \n (.C(CLK),\n .CE(\\occupied_counter.occ_cnt[15]_i_1_n_0 ),\n .D(\\occupied_counter.occ_cnt[13]_i_1_n_0 ),\n .Q(\\occupied_counter.occ_cnt_reg_n_0_[13] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\occupied_counter.occ_cnt_reg[14] \n (.C(CLK),\n .CE(\\occupied_counter.occ_cnt[15]_i_1_n_0 ),\n .D(\\occupied_counter.occ_cnt[14]_i_1_n_0 ),\n .Q(p_4_in),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\occupied_counter.occ_cnt_reg[15] \n (.C(CLK),\n .CE(\\occupied_counter.occ_cnt[15]_i_1_n_0 ),\n .D(\\occupied_counter.occ_cnt[15]_i_2_n_0 ),\n .Q(\\occupied_counter.occ_cnt_reg_n_0_[15] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\occupied_counter.occ_cnt_reg[1] \n (.C(CLK),\n .CE(\\occupied_counter.occ_cnt[15]_i_1_n_0 ),\n .D(\\occupied_counter.occ_cnt[1]_i_1_n_0 ),\n .Q(\\occupied_counter.occ_cnt_reg_n_0_[1] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\occupied_counter.occ_cnt_reg[2] \n (.C(CLK),\n .CE(\\occupied_counter.occ_cnt[15]_i_1_n_0 ),\n .D(\\occupied_counter.occ_cnt[2]_i_1_n_0 ),\n .Q(\\occupied_counter.occ_cnt_reg_n_0_[2] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\occupied_counter.occ_cnt_reg[3] \n (.C(CLK),\n .CE(\\occupied_counter.occ_cnt[15]_i_1_n_0 ),\n .D(\\occupied_counter.occ_cnt[3]_i_1_n_0 ),\n .Q(\\occupied_counter.occ_cnt_reg_n_0_[3] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\occupied_counter.occ_cnt_reg[4] \n (.C(CLK),\n .CE(\\occupied_counter.occ_cnt[15]_i_1_n_0 ),\n .D(\\occupied_counter.occ_cnt[4]_i_1_n_0 ),\n .Q(\\occupied_counter.occ_cnt_reg_n_0_[4] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\occupied_counter.occ_cnt_reg[5] \n (.C(CLK),\n .CE(\\occupied_counter.occ_cnt[15]_i_1_n_0 ),\n .D(\\occupied_counter.occ_cnt[5]_i_1_n_0 ),\n .Q(\\occupied_counter.occ_cnt_reg_n_0_[5] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\occupied_counter.occ_cnt_reg[6] \n (.C(CLK),\n .CE(\\occupied_counter.occ_cnt[15]_i_1_n_0 ),\n .D(\\occupied_counter.occ_cnt[6]_i_1_n_0 ),\n .Q(\\occupied_counter.occ_cnt_reg_n_0_[6] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\occupied_counter.occ_cnt_reg[7] \n (.C(CLK),\n .CE(\\occupied_counter.occ_cnt[15]_i_1_n_0 ),\n .D(\\occupied_counter.occ_cnt[7]_i_1_n_0 ),\n .Q(\\occupied_counter.occ_cnt_reg_n_0_[7] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\occupied_counter.occ_cnt_reg[8] \n (.C(CLK),\n .CE(\\occupied_counter.occ_cnt[15]_i_1_n_0 ),\n .D(\\occupied_counter.occ_cnt[8]_i_1_n_0 ),\n .Q(\\occupied_counter.occ_cnt_reg_n_0_[8] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\occupied_counter.occ_cnt_reg[9] \n (.C(CLK),\n .CE(\\occupied_counter.occ_cnt[15]_i_1_n_0 ),\n .D(\\occupied_counter.occ_cnt[9]_i_1_n_0 ),\n .Q(\\occupied_counter.occ_cnt_reg_n_0_[9] ),\n .R(reset_reg));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\pointer_ram.rams[0].RAM32M0 \n (.ADDRA({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .ADDRB({1'b0,\\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 }),\n .ADDRC({1'b0,\\write_data_control.wr_data_indx_r_reg__0 }),\n .ADDRD({1'b0,ADDRD}),\n .DIA({1'b0,1'b0}),\n .DIB(pointer_wr_data[1:0]),\n .DIC(pointer_wr_data[1:0]),\n .DID({1'b0,1'b0}),\n .DOA(\\NLW_pointer_ram.rams[0].RAM32M0_DOA_UNCONNECTED [1:0]),\n .DOB(wr_data_buf_addr[1:0]),\n .DOC(wr_data_pntr[1:0]),\n .DOD(\\NLW_pointer_ram.rams[0].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(pointer_we));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\pointer_ram.rams[1].RAM32M0 \n (.ADDRA({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .ADDRB({1'b0,\\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 }),\n .ADDRC({1'b0,\\write_data_control.wr_data_indx_r_reg__0 }),\n .ADDRD({1'b0,ADDRD}),\n .DIA({1'b0,1'b0}),\n .DIB(pointer_wr_data[3:2]),\n .DIC(pointer_wr_data[3:2]),\n .DID({1'b0,1'b0}),\n .DOA(\\NLW_pointer_ram.rams[1].RAM32M0_DOA_UNCONNECTED [1:0]),\n .DOB(wr_data_buf_addr[3:2]),\n .DOC(wr_data_pntr[3:2]),\n .DOD(\\NLW_pointer_ram.rams[1].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(pointer_we));\n (* SOFT_HLUTNM = \"soft_lutpair1487\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\read_data_indx.rd_data_indx_r[0]_i_1 \n (.I0(Q[0]),\n .O(p_0_in__1[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1487\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\read_data_indx.rd_data_indx_r[1]_i_1 \n (.I0(Q[0]),\n .I1(Q[1]),\n .O(p_0_in__1[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1483\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\read_data_indx.rd_data_indx_r[2]_i_1 \n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(Q[2]),\n .O(p_0_in__1[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1483\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\read_data_indx.rd_data_indx_r[3]_i_1 \n (.I0(Q[2]),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(Q[3]),\n .O(p_0_in__1[3]));\n FDRE #(\n .INIT(1'b0)) \n \\read_data_indx.rd_data_indx_r_reg[0] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__1[0]),\n .Q(Q[0]),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\read_data_indx.rd_data_indx_r_reg[1] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__1[1]),\n .Q(Q[1]),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\read_data_indx.rd_data_indx_r_reg[2] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__1[2]),\n .Q(Q[2]),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\read_data_indx.rd_data_indx_r_reg[3] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__1[3]),\n .Q(Q[3]),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\read_data_indx.rd_data_upd_indx_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(E),\n .Q(p_0_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1480\" *) \n LUT4 #(\n .INIT(16'h0096)) \n \\wr_req_counter.wr_req_cnt_r[0]_i_1 \n (.I0(p_0_in),\n .I1(wr_accepted),\n .I2(\\wr_req_counter.wr_req_cnt_r_reg[1]_0 [0]),\n .I3(reset_reg),\n .O(\\wr_req_counter.wr_req_cnt_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1480\" *) \n LUT5 #(\n .INIT(32'h0000D2B4)) \n \\wr_req_counter.wr_req_cnt_r[1]_i_1 \n (.I0(wr_accepted),\n .I1(p_0_in),\n .I2(\\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]),\n .I3(\\wr_req_counter.wr_req_cnt_r_reg[1]_0 [0]),\n .I4(reset_reg),\n .O(\\wr_req_counter.wr_req_cnt_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00000000F7EF0810)) \n \\wr_req_counter.wr_req_cnt_r[2]_i_1 \n (.I0(\\wr_req_counter.wr_req_cnt_r_reg[1]_0 [0]),\n .I1(\\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]),\n .I2(p_0_in),\n .I3(wr_accepted),\n .I4(wr_req_cnt_r[2]),\n .I5(reset_reg),\n .O(\\wr_req_counter.wr_req_cnt_r[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FF7E0081)) \n \\wr_req_counter.wr_req_cnt_r[3]_i_1 \n (.I0(wr_req_cnt_r[2]),\n .I1(\\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]),\n .I2(\\wr_req_counter.wr_req_cnt_r_reg[1]_1 ),\n .I3(\\read_data_indx.rd_data_upd_indx_r_reg_0 ),\n .I4(wr_req_cnt_r[3]),\n .I5(reset_reg),\n .O(\\wr_req_counter.wr_req_cnt_r[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h000000009CCCCCC9)) \n \\wr_req_counter.wr_req_cnt_r[4]_i_1 \n (.I0(\\read_data_indx.rd_data_upd_indx_r_reg_0 ),\n .I1(wr_req_cnt_r[4]),\n .I2(\\wr_req_counter.wr_req_cnt_r[4]_i_2_n_0 ),\n .I3(wr_req_cnt_r[2]),\n .I4(wr_req_cnt_r[3]),\n .I5(reset_reg),\n .O(\\wr_req_counter.wr_req_cnt_r[4]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h80FE)) \n \\wr_req_counter.wr_req_cnt_r[4]_i_2 \n (.I0(\\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]),\n .I1(wr_accepted),\n .I2(\\wr_req_counter.wr_req_cnt_r_reg[1]_0 [0]),\n .I3(wr_req_cnt_r[2]),\n .O(\\wr_req_counter.wr_req_cnt_r[4]_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\wr_req_counter.wr_req_cnt_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_req_counter.wr_req_cnt_r[0]_i_1_n_0 ),\n .Q(\\wr_req_counter.wr_req_cnt_r_reg[1]_0 [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wr_req_counter.wr_req_cnt_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_req_counter.wr_req_cnt_r[1]_i_1_n_0 ),\n .Q(\\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wr_req_counter.wr_req_cnt_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_req_counter.wr_req_cnt_r[2]_i_1_n_0 ),\n .Q(wr_req_cnt_r[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wr_req_counter.wr_req_cnt_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_req_counter.wr_req_cnt_r[3]_i_1_n_0 ),\n .Q(wr_req_cnt_r[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\wr_req_counter.wr_req_cnt_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_req_counter.wr_req_cnt_r[4]_i_1_n_0 ),\n .Q(wr_req_cnt_r[4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[0]),\n .Q(\\my_empty_reg[7] [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[100] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[100]),\n .Q(\\my_empty_reg[7] [100]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[101] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[101]),\n .Q(\\my_empty_reg[7] [101]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[102] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[102]),\n .Q(\\my_empty_reg[7] [102]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[103] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[103]),\n .Q(\\my_empty_reg[7] [103]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[104] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[104]),\n .Q(\\my_empty_reg[7] [104]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[105] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[105]),\n .Q(\\my_empty_reg[7] [105]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[106] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[106]),\n .Q(\\my_empty_reg[7] [106]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[107] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[107]),\n .Q(\\my_empty_reg[7] [107]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[108] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[108]),\n .Q(\\my_empty_reg[7] [108]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[109] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[109]),\n .Q(\\my_empty_reg[7] [109]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[10]),\n .Q(\\my_empty_reg[7] [10]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[110] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[110]),\n .Q(\\my_empty_reg[7] [110]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[111] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[111]),\n .Q(\\my_empty_reg[7] [111]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[112] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[112]),\n .Q(\\my_empty_reg[7] [112]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[113] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[113]),\n .Q(\\my_empty_reg[7] [113]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[114] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[114]),\n .Q(\\my_empty_reg[7] [114]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[115] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[115]),\n .Q(\\my_empty_reg[7] [115]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[116] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[116]),\n .Q(\\my_empty_reg[7] [116]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[117] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[117]),\n .Q(\\my_empty_reg[7] [117]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[118] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[118]),\n .Q(\\my_empty_reg[7] [118]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[119] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[119]),\n .Q(\\my_empty_reg[7] [119]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[11]),\n .Q(\\my_empty_reg[7] [11]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[120] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[120]),\n .Q(\\my_empty_reg[7] [120]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[121] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[121]),\n .Q(\\my_empty_reg[7] [121]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[122] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[122]),\n .Q(\\my_empty_reg[7] [122]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[123] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[123]),\n .Q(\\my_empty_reg[7] [123]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[124] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[124]),\n .Q(\\my_empty_reg[7] [124]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[125] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[125]),\n .Q(\\my_empty_reg[7] [125]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[126] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[126]),\n .Q(\\my_empty_reg[7] [126]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[127] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[127]),\n .Q(\\my_empty_reg[7] [127]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[128] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[128]),\n .Q(\\my_empty_reg[7] [128]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[129] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[129]),\n .Q(\\my_empty_reg[7] [129]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[12] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[12]),\n .Q(\\my_empty_reg[7] [12]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[130] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[130]),\n .Q(\\my_empty_reg[7] [130]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[131] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[131]),\n .Q(\\my_empty_reg[7] [131]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[132] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[132]),\n .Q(\\my_empty_reg[7] [132]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[133] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[133]),\n .Q(\\my_empty_reg[7] [133]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[134] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[134]),\n .Q(\\my_empty_reg[7] [134]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[135] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[135]),\n .Q(\\my_empty_reg[7] [135]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[136] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[136]),\n .Q(\\my_empty_reg[7] [136]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[137] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[137]),\n .Q(\\my_empty_reg[7] [137]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[138] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[138]),\n .Q(\\my_empty_reg[7] [138]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[139] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[139]),\n .Q(\\my_empty_reg[7] [139]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[13] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[13]),\n .Q(\\my_empty_reg[7] [13]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[140] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[140]),\n .Q(\\my_empty_reg[7] [140]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[141] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[141]),\n .Q(\\my_empty_reg[7] [141]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[142] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[142]),\n .Q(\\my_empty_reg[7] [142]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[143] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[143]),\n .Q(\\my_empty_reg[7] [143]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[144] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[144]),\n .Q(\\my_empty_reg[7] [144]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[145] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[145]),\n .Q(\\my_empty_reg[7] [145]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[146] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[146]),\n .Q(\\my_empty_reg[7] [146]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[147] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[147]),\n .Q(\\my_empty_reg[7] [147]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[148] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[148]),\n .Q(\\my_empty_reg[7] [148]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[149] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[149]),\n .Q(\\my_empty_reg[7] [149]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[14] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[14]),\n .Q(\\my_empty_reg[7] [14]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[150] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[150]),\n .Q(\\my_empty_reg[7] [150]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[151] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[151]),\n .Q(\\my_empty_reg[7] [151]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[152] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[152]),\n .Q(\\my_empty_reg[7] [152]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[153] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[153]),\n .Q(\\my_empty_reg[7] [153]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[154] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[154]),\n .Q(\\my_empty_reg[7] [154]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[155] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[155]),\n .Q(\\my_empty_reg[7] [155]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[156] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[156]),\n .Q(\\my_empty_reg[7] [156]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[157] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[157]),\n .Q(\\my_empty_reg[7] [157]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[158] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[158]),\n .Q(\\my_empty_reg[7] [158]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[159] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[159]),\n .Q(\\my_empty_reg[7] [159]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[15] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[15]),\n .Q(\\my_empty_reg[7] [15]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[160] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[160]),\n .Q(\\my_empty_reg[7] [160]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[161] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[161]),\n .Q(\\my_empty_reg[7] [161]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[162] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[162]),\n .Q(\\my_empty_reg[7] [162]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[163] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[163]),\n .Q(\\my_empty_reg[7] [163]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[164] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[164]),\n .Q(\\my_empty_reg[7] [164]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[165] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[165]),\n .Q(\\my_empty_reg[7] [165]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[166] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[166]),\n .Q(\\my_empty_reg[7] [166]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[167] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[167]),\n .Q(\\my_empty_reg[7] [167]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[168] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[168]),\n .Q(\\my_empty_reg[7] [168]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[169] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[169]),\n .Q(\\my_empty_reg[7] [169]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[16] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[16]),\n .Q(\\my_empty_reg[7] [16]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[170] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[170]),\n .Q(\\my_empty_reg[7] [170]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[171] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[171]),\n .Q(\\my_empty_reg[7] [171]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[172] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[172]),\n .Q(\\my_empty_reg[7] [172]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[173] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[173]),\n .Q(\\my_empty_reg[7] [173]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[174] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[174]),\n .Q(\\my_empty_reg[7] [174]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[175] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[175]),\n .Q(\\my_empty_reg[7] [175]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[176] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[176]),\n .Q(\\my_empty_reg[7] [176]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[177] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[177]),\n .Q(\\my_empty_reg[7] [177]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[178] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[178]),\n .Q(\\my_empty_reg[7] [178]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[179] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[179]),\n .Q(\\my_empty_reg[7] [179]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[17] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[17]),\n .Q(\\my_empty_reg[7] [17]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[180] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[180]),\n .Q(\\my_empty_reg[7] [180]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[181] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[181]),\n .Q(\\my_empty_reg[7] [181]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[182] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[182]),\n .Q(\\my_empty_reg[7] [182]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[183] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[183]),\n .Q(\\my_empty_reg[7] [183]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[184] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[184]),\n .Q(\\my_empty_reg[7] [184]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[185] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[185]),\n .Q(\\my_empty_reg[7] [185]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[186] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[186]),\n .Q(\\my_empty_reg[7] [186]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[187] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[187]),\n .Q(\\my_empty_reg[7] [187]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[188] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[188]),\n .Q(\\my_empty_reg[7] [188]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[189] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[189]),\n .Q(\\my_empty_reg[7] [189]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[18] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[18]),\n .Q(\\my_empty_reg[7] [18]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[190] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[190]),\n .Q(\\my_empty_reg[7] [190]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[191] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[191]),\n .Q(\\my_empty_reg[7] [191]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[192] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[192]),\n .Q(\\my_empty_reg[7] [192]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[193] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[193]),\n .Q(\\my_empty_reg[7] [193]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[194] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[194]),\n .Q(\\my_empty_reg[7] [194]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[195] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[195]),\n .Q(\\my_empty_reg[7] [195]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[196] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[196]),\n .Q(\\my_empty_reg[7] [196]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[197] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[197]),\n .Q(\\my_empty_reg[7] [197]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[198] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[198]),\n .Q(\\my_empty_reg[7] [198]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[199] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[199]),\n .Q(\\my_empty_reg[7] [199]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[19] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[19]),\n .Q(\\my_empty_reg[7] [19]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[1]),\n .Q(\\my_empty_reg[7] [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[200] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[200]),\n .Q(\\my_empty_reg[7] [200]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[201] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[201]),\n .Q(\\my_empty_reg[7] [201]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[202] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[202]),\n .Q(\\my_empty_reg[7] [202]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[203] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[203]),\n .Q(\\my_empty_reg[7] [203]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[204] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[204]),\n .Q(\\my_empty_reg[7] [204]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[205] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[205]),\n .Q(\\my_empty_reg[7] [205]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[206] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[206]),\n .Q(\\my_empty_reg[7] [206]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[207] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[207]),\n .Q(\\my_empty_reg[7] [207]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[208] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[208]),\n .Q(\\my_empty_reg[7] [208]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[209] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[209]),\n .Q(\\my_empty_reg[7] [209]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[20] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[20]),\n .Q(\\my_empty_reg[7] [20]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[210] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[210]),\n .Q(\\my_empty_reg[7] [210]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[211] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[211]),\n .Q(\\my_empty_reg[7] [211]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[212] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[212]),\n .Q(\\my_empty_reg[7] [212]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[213] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[213]),\n .Q(\\my_empty_reg[7] [213]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[214] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[214]),\n .Q(\\my_empty_reg[7] [214]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[215] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[215]),\n .Q(\\my_empty_reg[7] [215]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[216] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[216]),\n .Q(\\my_empty_reg[7] [216]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[217] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[217]),\n .Q(\\my_empty_reg[7] [217]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[218] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[218]),\n .Q(\\my_empty_reg[7] [218]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[219] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[219]),\n .Q(\\my_empty_reg[7] [219]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[21] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[21]),\n .Q(\\my_empty_reg[7] [21]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[220] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[220]),\n .Q(\\my_empty_reg[7] [220]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[221] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[221]),\n .Q(\\my_empty_reg[7] [221]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[222] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[222]),\n .Q(\\my_empty_reg[7] [222]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[223] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[223]),\n .Q(\\my_empty_reg[7] [223]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[224] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[224]),\n .Q(\\my_empty_reg[7] [224]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[225] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[225]),\n .Q(\\my_empty_reg[7] [225]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[226] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[226]),\n .Q(\\my_empty_reg[7] [226]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[227] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[227]),\n .Q(\\my_empty_reg[7] [227]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[228] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[228]),\n .Q(\\my_empty_reg[7] [228]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[229] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[229]),\n .Q(\\my_empty_reg[7] [229]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[22] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[22]),\n .Q(\\my_empty_reg[7] [22]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[230] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[230]),\n .Q(\\my_empty_reg[7] [230]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[231] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[231]),\n .Q(\\my_empty_reg[7] [231]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[232] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[232]),\n .Q(\\my_empty_reg[7] [232]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[233] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[233]),\n .Q(\\my_empty_reg[7] [233]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[234] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[234]),\n .Q(\\my_empty_reg[7] [234]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[235] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[235]),\n .Q(\\my_empty_reg[7] [235]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[236] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[236]),\n .Q(\\my_empty_reg[7] [236]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[237] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[237]),\n .Q(\\my_empty_reg[7] [237]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[238] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[238]),\n .Q(\\my_empty_reg[7] [238]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[239] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[239]),\n .Q(\\my_empty_reg[7] [239]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[23] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[23]),\n .Q(\\my_empty_reg[7] [23]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[240] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[240]),\n .Q(\\my_empty_reg[7] [240]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[241] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[241]),\n .Q(\\my_empty_reg[7] [241]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[242] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[242]),\n .Q(\\my_empty_reg[7] [242]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[243] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[243]),\n .Q(\\my_empty_reg[7] [243]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[244] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[244]),\n .Q(\\my_empty_reg[7] [244]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[245] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[245]),\n .Q(\\my_empty_reg[7] [245]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[246] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[246]),\n .Q(\\my_empty_reg[7] [246]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[247] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[247]),\n .Q(\\my_empty_reg[7] [247]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[248] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[248]),\n .Q(\\my_empty_reg[7] [248]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[249] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[249]),\n .Q(\\my_empty_reg[7] [249]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[24] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[24]),\n .Q(\\my_empty_reg[7] [24]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[250] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[250]),\n .Q(\\my_empty_reg[7] [250]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[251] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[251]),\n .Q(\\my_empty_reg[7] [251]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[252] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[252]),\n .Q(\\my_empty_reg[7] [252]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[253] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[253]),\n .Q(\\my_empty_reg[7] [253]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[254] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[254]),\n .Q(\\my_empty_reg[7] [254]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[255] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[255]),\n .Q(\\my_empty_reg[7] [255]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[256] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[256]),\n .Q(\\my_empty_reg[7] [256]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[257] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[257]),\n .Q(\\my_empty_reg[7] [257]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[258] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[258]),\n .Q(\\my_empty_reg[7] [258]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[259] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[259]),\n .Q(\\my_empty_reg[7] [259]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[25] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[25]),\n .Q(\\my_empty_reg[7] [25]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[260] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[260]),\n .Q(\\my_empty_reg[7] [260]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[261] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[261]),\n .Q(\\my_empty_reg[7] [261]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[262] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[262]),\n .Q(\\my_empty_reg[7] [262]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[263] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[263]),\n .Q(\\my_empty_reg[7] [263]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[264] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[264]),\n .Q(\\my_empty_reg[7] [264]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[265] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[265]),\n .Q(\\my_empty_reg[7] [265]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[266] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[266]),\n .Q(\\my_empty_reg[7] [266]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[267] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[267]),\n .Q(\\my_empty_reg[7] [267]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[268] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[268]),\n .Q(\\my_empty_reg[7] [268]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[269] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[269]),\n .Q(\\my_empty_reg[7] [269]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[26] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[26]),\n .Q(\\my_empty_reg[7] [26]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[270] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[270]),\n .Q(\\my_empty_reg[7] [270]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[271] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[271]),\n .Q(\\my_empty_reg[7] [271]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[272] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[272]),\n .Q(\\my_empty_reg[7] [272]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[273] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[273]),\n .Q(\\my_empty_reg[7] [273]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[274] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[274]),\n .Q(\\my_empty_reg[7] [274]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[275] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[275]),\n .Q(\\my_empty_reg[7] [275]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[276] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[276]),\n .Q(\\my_empty_reg[7] [276]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[277] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[277]),\n .Q(\\my_empty_reg[7] [277]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[278] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[278]),\n .Q(\\my_empty_reg[7] [278]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[279] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[279]),\n .Q(\\my_empty_reg[7] [279]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[27] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[27]),\n .Q(\\my_empty_reg[7] [27]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[280] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[280]),\n .Q(\\my_empty_reg[7] [280]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[281] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[281]),\n .Q(\\my_empty_reg[7] [281]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[282] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[282]),\n .Q(\\my_empty_reg[7] [282]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[283] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[283]),\n .Q(\\my_empty_reg[7] [283]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[284] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[284]),\n .Q(\\my_empty_reg[7] [284]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[285] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[285]),\n .Q(\\my_empty_reg[7] [285]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[286] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[286]),\n .Q(\\my_empty_reg[7] [286]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[287] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[287]),\n .Q(\\my_empty_reg[7] [287]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[28] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[28]),\n .Q(\\my_empty_reg[7] [28]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[29] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[29]),\n .Q(\\my_empty_reg[7] [29]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[2]),\n .Q(\\my_empty_reg[7] [2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[30] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[30]),\n .Q(\\my_empty_reg[7] [30]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[31] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[31]),\n .Q(\\my_empty_reg[7] [31]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[32] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[32]),\n .Q(\\my_empty_reg[7] [32]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[33] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[33]),\n .Q(\\my_empty_reg[7] [33]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[34] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[34]),\n .Q(\\my_empty_reg[7] [34]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[35] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[35]),\n .Q(\\my_empty_reg[7] [35]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[36] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[36]),\n .Q(\\my_empty_reg[7] [36]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[37] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[37]),\n .Q(\\my_empty_reg[7] [37]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[38] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[38]),\n .Q(\\my_empty_reg[7] [38]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[39] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[39]),\n .Q(\\my_empty_reg[7] [39]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[3]),\n .Q(\\my_empty_reg[7] [3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[40] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[40]),\n .Q(\\my_empty_reg[7] [40]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[41] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[41]),\n .Q(\\my_empty_reg[7] [41]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[42] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[42]),\n .Q(\\my_empty_reg[7] [42]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[43] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[43]),\n .Q(\\my_empty_reg[7] [43]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[44] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[44]),\n .Q(\\my_empty_reg[7] [44]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[45] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[45]),\n .Q(\\my_empty_reg[7] [45]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[46] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[46]),\n .Q(\\my_empty_reg[7] [46]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[47] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[47]),\n .Q(\\my_empty_reg[7] [47]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[48] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[48]),\n .Q(\\my_empty_reg[7] [48]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[49] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[49]),\n .Q(\\my_empty_reg[7] [49]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[4]),\n .Q(\\my_empty_reg[7] [4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[50] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[50]),\n .Q(\\my_empty_reg[7] [50]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[51] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[51]),\n .Q(\\my_empty_reg[7] [51]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[52] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[52]),\n .Q(\\my_empty_reg[7] [52]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[53] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[53]),\n .Q(\\my_empty_reg[7] [53]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[54] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[54]),\n .Q(\\my_empty_reg[7] [54]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[55] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[55]),\n .Q(\\my_empty_reg[7] [55]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[56] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[56]),\n .Q(\\my_empty_reg[7] [56]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[57] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[57]),\n .Q(\\my_empty_reg[7] [57]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[58] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[58]),\n .Q(\\my_empty_reg[7] [58]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[59] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[59]),\n .Q(\\my_empty_reg[7] [59]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[5]),\n .Q(\\my_empty_reg[7] [5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[60] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[60]),\n .Q(\\my_empty_reg[7] [60]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[61] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[61]),\n .Q(\\my_empty_reg[7] [61]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[62] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[62]),\n .Q(\\my_empty_reg[7] [62]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[63] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[63]),\n .Q(\\my_empty_reg[7] [63]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[64] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[64]),\n .Q(\\my_empty_reg[7] [64]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[65] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[65]),\n .Q(\\my_empty_reg[7] [65]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[66] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[66]),\n .Q(\\my_empty_reg[7] [66]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[67] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[67]),\n .Q(\\my_empty_reg[7] [67]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[68] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[68]),\n .Q(\\my_empty_reg[7] [68]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[69] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[69]),\n .Q(\\my_empty_reg[7] [69]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[6]),\n .Q(\\my_empty_reg[7] [6]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[70] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[70]),\n .Q(\\my_empty_reg[7] [70]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[71] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[71]),\n .Q(\\my_empty_reg[7] [71]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[72] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[72]),\n .Q(\\my_empty_reg[7] [72]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[73] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[73]),\n .Q(\\my_empty_reg[7] [73]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[74] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[74]),\n .Q(\\my_empty_reg[7] [74]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[75] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[75]),\n .Q(\\my_empty_reg[7] [75]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[76] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[76]),\n .Q(\\my_empty_reg[7] [76]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[77] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[77]),\n .Q(\\my_empty_reg[7] [77]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[78] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[78]),\n .Q(\\my_empty_reg[7] [78]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[79] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[79]),\n .Q(\\my_empty_reg[7] [79]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[7]),\n .Q(\\my_empty_reg[7] [7]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[80] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[80]),\n .Q(\\my_empty_reg[7] [80]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[81] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[81]),\n .Q(\\my_empty_reg[7] [81]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[82] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[82]),\n .Q(\\my_empty_reg[7] [82]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[83] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[83]),\n .Q(\\my_empty_reg[7] [83]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[84] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[84]),\n .Q(\\my_empty_reg[7] [84]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[85] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[85]),\n .Q(\\my_empty_reg[7] [85]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[86] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[86]),\n .Q(\\my_empty_reg[7] [86]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[87] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[87]),\n .Q(\\my_empty_reg[7] [87]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[88] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[88]),\n .Q(\\my_empty_reg[7] [88]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[89] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[89]),\n .Q(\\my_empty_reg[7] [89]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[8]),\n .Q(\\my_empty_reg[7] [8]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[90] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[90]),\n .Q(\\my_empty_reg[7] [90]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[91] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[91]),\n .Q(\\my_empty_reg[7] [91]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[92] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[92]),\n .Q(\\my_empty_reg[7] [92]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[93] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[93]),\n .Q(\\my_empty_reg[7] [93]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[94] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[94]),\n .Q(\\my_empty_reg[7] [94]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[95] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[95]),\n .Q(\\my_empty_reg[7] [95]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[96] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[96]),\n .Q(\\my_empty_reg[7] [96]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[97] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[97]),\n .Q(\\my_empty_reg[7] [97]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[98] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[98]),\n .Q(\\my_empty_reg[7] [98]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[99] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[99]),\n .Q(\\my_empty_reg[7] [99]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_buffer.wr_buf_out_data_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[9]),\n .Q(\\my_empty_reg[7] [9]),\n .R(1'b0));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[0].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[5:4]),\n .DIB(wr_buf_in_data[3:2]),\n .DIC(wr_buf_in_data[1:0]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[5:4]),\n .DOB(wr_buf_out_data_w[3:2]),\n .DOC(wr_buf_out_data_w[1:0]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[0].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT6 #(\n .INIT(64'h4040404040444444)) \n \\write_buffer.wr_buffer_ram[0].RAM32M0_i_1 \n (.I0(reset_reg),\n .I1(ram_init_done_r),\n .I2(p_0_in),\n .I3(p_0_in__0_0),\n .I4(p_4_in),\n .I5(\\occupied_counter.occ_cnt_reg_n_0_[15] ),\n .O(wdf_rdy_ns));\n LUT4 #(\n .INIT(16'h00AC)) \n \\write_buffer.wr_buffer_ram[0].RAM32M0_i_10 \n (.I0(wr_data_pntr[1]),\n .I1(wb_wr_data_addr_r[2]),\n .I2(wr_data_addr_le),\n .I3(reset_reg),\n .O(wb_wr_data_addr_w[2]));\n LUT4 #(\n .INIT(16'h00AC)) \n \\write_buffer.wr_buffer_ram[0].RAM32M0_i_11 \n (.I0(wr_data_pntr[0]),\n .I1(wb_wr_data_addr_r[1]),\n .I2(wr_data_addr_le),\n .I3(reset_reg),\n .O(wb_wr_data_addr_w[1]));\n LUT5 #(\n .INIT(32'h02020F00)) \n \\write_buffer.wr_buffer_ram[0].RAM32M0_i_12 \n (.I0(app_wdf_rdy_r_copy3),\n .I1(app_wdf_end_r1),\n .I2(reset_reg),\n .I3(wb_wr_data_addr0_r),\n .I4(app_wdf_wren_r1),\n .O(wb_wr_data_addr0_ns));\n (* SOFT_HLUTNM = \"soft_lutpair1479\" *) \n LUT3 #(\n .INIT(8'h80)) \n \\write_buffer.wr_buffer_ram[0].RAM32M0_i_13 \n (.I0(app_wdf_wren_r1),\n .I1(app_wdf_end_r1),\n .I2(app_wdf_rdy_r_copy1),\n .O(p_0_in__0_0));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[0].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[5]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[5]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[5]),\n .O(wr_buf_in_data[5]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[0].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[4]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[4]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[4]),\n .O(wr_buf_in_data[4]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[0].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[3]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[3]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[3]),\n .O(wr_buf_in_data[3]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[0].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[2]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[2]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[2]),\n .O(wr_buf_in_data[2]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[0].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[1]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[1]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[1]),\n .O(wr_buf_in_data[1]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[0].RAM32M0_i_7 \n (.I0(wready_reg_rep__1[0]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[0]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[0]),\n .O(wr_buf_in_data[0]));\n LUT4 #(\n .INIT(16'h00AC)) \n \\write_buffer.wr_buffer_ram[0].RAM32M0_i_8 \n (.I0(wr_data_pntr[3]),\n .I1(wb_wr_data_addr_r[4]),\n .I2(wr_data_addr_le),\n .I3(reset_reg),\n .O(wb_wr_data_addr_w[4]));\n LUT4 #(\n .INIT(16'h00AC)) \n \\write_buffer.wr_buffer_ram[0].RAM32M0_i_9 \n (.I0(wr_data_pntr[2]),\n .I1(wb_wr_data_addr_r[3]),\n .I2(wr_data_addr_le),\n .I3(reset_reg),\n .O(wb_wr_data_addr_w[3]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[10].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[65:64]),\n .DIB(wr_buf_in_data[63:62]),\n .DIC(wr_buf_in_data[61:60]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[65:64]),\n .DOB(wr_buf_out_data_w[63:62]),\n .DOC(wr_buf_out_data_w[61:60]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[10].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[10].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[65]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[65]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[65]),\n .O(wr_buf_in_data[65]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[10].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[64]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[64]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[64]),\n .O(wr_buf_in_data[64]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[10].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[63]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[63]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[63]),\n .O(wr_buf_in_data[63]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[10].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[62]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[62]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[62]),\n .O(wr_buf_in_data[62]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[10].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[61]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[61]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[61]),\n .O(wr_buf_in_data[61]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[10].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[60]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[60]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[60]),\n .O(wr_buf_in_data[60]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[11].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[71:70]),\n .DIB(wr_buf_in_data[69:68]),\n .DIC(wr_buf_in_data[67:66]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[71:70]),\n .DOB(wr_buf_out_data_w[69:68]),\n .DOC(wr_buf_out_data_w[67:66]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[11].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[11].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[71]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[71]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[71]),\n .O(wr_buf_in_data[71]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[11].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[70]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[70]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[70]),\n .O(wr_buf_in_data[70]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[11].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[69]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[69]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[69]),\n .O(wr_buf_in_data[69]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[11].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[68]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[68]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[68]),\n .O(wr_buf_in_data[68]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[11].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[67]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[67]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[67]),\n .O(wr_buf_in_data[67]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[11].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[66]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[66]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[66]),\n .O(wr_buf_in_data[66]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[12].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[77:76]),\n .DIB(wr_buf_in_data[75:74]),\n .DIC(wr_buf_in_data[73:72]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[77:76]),\n .DOB(wr_buf_out_data_w[75:74]),\n .DOC(wr_buf_out_data_w[73:72]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[12].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[12].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[77]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[77]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[77]),\n .O(wr_buf_in_data[77]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[12].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[76]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[76]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[76]),\n .O(wr_buf_in_data[76]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[12].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[75]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[75]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[75]),\n .O(wr_buf_in_data[75]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[12].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[74]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[74]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[74]),\n .O(wr_buf_in_data[74]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[12].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[73]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[73]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[73]),\n .O(wr_buf_in_data[73]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[12].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[72]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[72]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[72]),\n .O(wr_buf_in_data[72]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[13].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[83:82]),\n .DIB(wr_buf_in_data[81:80]),\n .DIC(wr_buf_in_data[79:78]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[83:82]),\n .DOB(wr_buf_out_data_w[81:80]),\n .DOC(wr_buf_out_data_w[79:78]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[13].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[13].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[83]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[83]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[83]),\n .O(wr_buf_in_data[83]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[13].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[82]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[82]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[82]),\n .O(wr_buf_in_data[82]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[13].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[81]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[81]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[81]),\n .O(wr_buf_in_data[81]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[13].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[80]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[80]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[80]),\n .O(wr_buf_in_data[80]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[13].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[79]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[79]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[79]),\n .O(wr_buf_in_data[79]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[13].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[78]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[78]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[78]),\n .O(wr_buf_in_data[78]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[14].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[89:88]),\n .DIB(wr_buf_in_data[87:86]),\n .DIC(wr_buf_in_data[85:84]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[89:88]),\n .DOB(wr_buf_out_data_w[87:86]),\n .DOC(wr_buf_out_data_w[85:84]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[14].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[14].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[89]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[89]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[89]),\n .O(wr_buf_in_data[89]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[14].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[88]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[88]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[88]),\n .O(wr_buf_in_data[88]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[14].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[87]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[87]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[87]),\n .O(wr_buf_in_data[87]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[14].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[86]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[86]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[86]),\n .O(wr_buf_in_data[86]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[14].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[85]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[85]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[85]),\n .O(wr_buf_in_data[85]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[14].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[84]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[84]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[84]),\n .O(wr_buf_in_data[84]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[15].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[95:94]),\n .DIB(wr_buf_in_data[93:92]),\n .DIC(wr_buf_in_data[91:90]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[95:94]),\n .DOB(wr_buf_out_data_w[93:92]),\n .DOC(wr_buf_out_data_w[91:90]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[15].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[15].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[95]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[95]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[95]),\n .O(wr_buf_in_data[95]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[15].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[94]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[94]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[94]),\n .O(wr_buf_in_data[94]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[15].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[93]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[93]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[93]),\n .O(wr_buf_in_data[93]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[15].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[92]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[92]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[92]),\n .O(wr_buf_in_data[92]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[15].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[91]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[91]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[91]),\n .O(wr_buf_in_data[91]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[15].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[90]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[90]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[90]),\n .O(wr_buf_in_data[90]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[16].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[101:100]),\n .DIB(wr_buf_in_data[99:98]),\n .DIC(wr_buf_in_data[97:96]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[101:100]),\n .DOB(wr_buf_out_data_w[99:98]),\n .DOC(wr_buf_out_data_w[97:96]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[16].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[16].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[101]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[101]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[101]),\n .O(wr_buf_in_data[101]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[16].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[100]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[100]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[100]),\n .O(wr_buf_in_data[100]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[16].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[99]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[99]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[99]),\n .O(wr_buf_in_data[99]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[16].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[98]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[98]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[98]),\n .O(wr_buf_in_data[98]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[16].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[97]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[97]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[97]),\n .O(wr_buf_in_data[97]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[16].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[96]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[96]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[96]),\n .O(wr_buf_in_data[96]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[17].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[107:106]),\n .DIB(wr_buf_in_data[105:104]),\n .DIC(wr_buf_in_data[103:102]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[107:106]),\n .DOB(wr_buf_out_data_w[105:104]),\n .DOC(wr_buf_out_data_w[103:102]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[17].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[17].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[107]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[107]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[107]),\n .O(wr_buf_in_data[107]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[17].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[106]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[106]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[106]),\n .O(wr_buf_in_data[106]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[17].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[105]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[105]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[105]),\n .O(wr_buf_in_data[105]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[17].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[104]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[104]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[104]),\n .O(wr_buf_in_data[104]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[17].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[103]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[103]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[103]),\n .O(wr_buf_in_data[103]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[17].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[102]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[102]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[102]),\n .O(wr_buf_in_data[102]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[18].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[113:112]),\n .DIB(wr_buf_in_data[111:110]),\n .DIC(wr_buf_in_data[109:108]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[113:112]),\n .DOB(wr_buf_out_data_w[111:110]),\n .DOC(wr_buf_out_data_w[109:108]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[18].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[18].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[113]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[113]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[113]),\n .O(wr_buf_in_data[113]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[18].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[112]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[112]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[112]),\n .O(wr_buf_in_data[112]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[18].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[111]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[111]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[111]),\n .O(wr_buf_in_data[111]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[18].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[110]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[110]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[110]),\n .O(wr_buf_in_data[110]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[18].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[109]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[109]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[109]),\n .O(wr_buf_in_data[109]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[18].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[108]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[108]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[108]),\n .O(wr_buf_in_data[108]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[19].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[119:118]),\n .DIB(wr_buf_in_data[117:116]),\n .DIC(wr_buf_in_data[115:114]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[119:118]),\n .DOB(wr_buf_out_data_w[117:116]),\n .DOC(wr_buf_out_data_w[115:114]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[19].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[19].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[119]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[119]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[119]),\n .O(wr_buf_in_data[119]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[19].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[118]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[118]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[118]),\n .O(wr_buf_in_data[118]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[19].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[117]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[117]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[117]),\n .O(wr_buf_in_data[117]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[19].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[116]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[116]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[116]),\n .O(wr_buf_in_data[116]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[19].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[115]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[115]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[115]),\n .O(wr_buf_in_data[115]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[19].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[114]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[114]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[114]),\n .O(wr_buf_in_data[114]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[1].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[11:10]),\n .DIB(wr_buf_in_data[9:8]),\n .DIC(wr_buf_in_data[7:6]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[11:10]),\n .DOB(wr_buf_out_data_w[9:8]),\n .DOC(wr_buf_out_data_w[7:6]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[1].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[1].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[11]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[11]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[11]),\n .O(wr_buf_in_data[11]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[1].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[10]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[10]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[10]),\n .O(wr_buf_in_data[10]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[1].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[9]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[9]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[9]),\n .O(wr_buf_in_data[9]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[1].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[8]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[8]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[8]),\n .O(wr_buf_in_data[8]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[1].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[7]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[7]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[7]),\n .O(wr_buf_in_data[7]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[1].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[6]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[6]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[6]),\n .O(wr_buf_in_data[6]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[20].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[125:124]),\n .DIB(wr_buf_in_data[123:122]),\n .DIC(wr_buf_in_data[121:120]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[125:124]),\n .DOB(wr_buf_out_data_w[123:122]),\n .DOC(wr_buf_out_data_w[121:120]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[20].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[20].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[125]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[125]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[125]),\n .O(wr_buf_in_data[125]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[20].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[124]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[124]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[124]),\n .O(wr_buf_in_data[124]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[20].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[123]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[123]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[123]),\n .O(wr_buf_in_data[123]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[20].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[122]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[122]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[122]),\n .O(wr_buf_in_data[122]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[20].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[121]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[121]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[121]),\n .O(wr_buf_in_data[121]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[20].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[120]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[120]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[120]),\n .O(wr_buf_in_data[120]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[21].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[131:130]),\n .DIB(wr_buf_in_data[129:128]),\n .DIC(wr_buf_in_data[127:126]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[131:130]),\n .DOB(wr_buf_out_data_w[129:128]),\n .DOC(wr_buf_out_data_w[127:126]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[21].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[21].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[131]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[131]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[131]),\n .O(wr_buf_in_data[131]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[21].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[130]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[130]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[130]),\n .O(wr_buf_in_data[130]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[21].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[129]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[129]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[129]),\n .O(wr_buf_in_data[129]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[21].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[128]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[128]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[128]),\n .O(wr_buf_in_data[128]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[21].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[127]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[127]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[127]),\n .O(wr_buf_in_data[127]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[21].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[126]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[126]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[126]),\n .O(wr_buf_in_data[126]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[22].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[137:136]),\n .DIB(wr_buf_in_data[135:134]),\n .DIC(wr_buf_in_data[133:132]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[137:136]),\n .DOB(wr_buf_out_data_w[135:134]),\n .DOC(wr_buf_out_data_w[133:132]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[22].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[22].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[137]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[137]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[137]),\n .O(wr_buf_in_data[137]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[22].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[136]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[136]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[136]),\n .O(wr_buf_in_data[136]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[22].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[135]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[135]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[135]),\n .O(wr_buf_in_data[135]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[22].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[134]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[134]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[134]),\n .O(wr_buf_in_data[134]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[22].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[133]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[133]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[133]),\n .O(wr_buf_in_data[133]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[22].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[132]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[132]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[132]),\n .O(wr_buf_in_data[132]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[23].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[143:142]),\n .DIB(wr_buf_in_data[141:140]),\n .DIC(wr_buf_in_data[139:138]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[143:142]),\n .DOB(wr_buf_out_data_w[141:140]),\n .DOC(wr_buf_out_data_w[139:138]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[23].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[23].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[143]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[143]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[143]),\n .O(wr_buf_in_data[143]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[23].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[142]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[142]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[142]),\n .O(wr_buf_in_data[142]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[23].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[141]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[141]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[141]),\n .O(wr_buf_in_data[141]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[23].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[140]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[140]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[140]),\n .O(wr_buf_in_data[140]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[23].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[139]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[139]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[139]),\n .O(wr_buf_in_data[139]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[23].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[138]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[138]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[138]),\n .O(wr_buf_in_data[138]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[24].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[149:148]),\n .DIB(wr_buf_in_data[147:146]),\n .DIC(wr_buf_in_data[145:144]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[149:148]),\n .DOB(wr_buf_out_data_w[147:146]),\n .DOC(wr_buf_out_data_w[145:144]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[24].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[24].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[149]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[149]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[149]),\n .O(wr_buf_in_data[149]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[24].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[148]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[148]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[148]),\n .O(wr_buf_in_data[148]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[24].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[147]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[147]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[147]),\n .O(wr_buf_in_data[147]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[24].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[146]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[146]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[146]),\n .O(wr_buf_in_data[146]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[24].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[145]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[145]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[145]),\n .O(wr_buf_in_data[145]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[24].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[144]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[144]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[144]),\n .O(wr_buf_in_data[144]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[25].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[155:154]),\n .DIB(wr_buf_in_data[153:152]),\n .DIC(wr_buf_in_data[151:150]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[155:154]),\n .DOB(wr_buf_out_data_w[153:152]),\n .DOC(wr_buf_out_data_w[151:150]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[25].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[25].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[155]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[155]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[155]),\n .O(wr_buf_in_data[155]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[25].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[154]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[154]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[154]),\n .O(wr_buf_in_data[154]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[25].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[153]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[153]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[153]),\n .O(wr_buf_in_data[153]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[25].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[152]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[152]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[152]),\n .O(wr_buf_in_data[152]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[25].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[151]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[151]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[151]),\n .O(wr_buf_in_data[151]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[25].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[150]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[150]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[150]),\n .O(wr_buf_in_data[150]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[26].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[161:160]),\n .DIB(wr_buf_in_data[159:158]),\n .DIC(wr_buf_in_data[157:156]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[161:160]),\n .DOB(wr_buf_out_data_w[159:158]),\n .DOC(wr_buf_out_data_w[157:156]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[26].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[26].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[161]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[161]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[161]),\n .O(wr_buf_in_data[161]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[26].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[160]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[160]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[160]),\n .O(wr_buf_in_data[160]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[26].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[159]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[159]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[159]),\n .O(wr_buf_in_data[159]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[26].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[158]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[158]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[158]),\n .O(wr_buf_in_data[158]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[26].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[157]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[157]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[157]),\n .O(wr_buf_in_data[157]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[26].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[156]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[156]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[156]),\n .O(wr_buf_in_data[156]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[27].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[167:166]),\n .DIB(wr_buf_in_data[165:164]),\n .DIC(wr_buf_in_data[163:162]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[167:166]),\n .DOB(wr_buf_out_data_w[165:164]),\n .DOC(wr_buf_out_data_w[163:162]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[27].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[27].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[167]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[167]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[167]),\n .O(wr_buf_in_data[167]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[27].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[166]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[166]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[166]),\n .O(wr_buf_in_data[166]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[27].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[165]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[165]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[165]),\n .O(wr_buf_in_data[165]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[27].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[164]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[164]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[164]),\n .O(wr_buf_in_data[164]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[27].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[163]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[163]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[163]),\n .O(wr_buf_in_data[163]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[27].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[162]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[162]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[162]),\n .O(wr_buf_in_data[162]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[28].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[173:172]),\n .DIB(wr_buf_in_data[171:170]),\n .DIC(wr_buf_in_data[169:168]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[173:172]),\n .DOB(wr_buf_out_data_w[171:170]),\n .DOC(wr_buf_out_data_w[169:168]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[28].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[28].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[173]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[173]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[173]),\n .O(wr_buf_in_data[173]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[28].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[172]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[172]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[172]),\n .O(wr_buf_in_data[172]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[28].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[171]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[171]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[171]),\n .O(wr_buf_in_data[171]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[28].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[170]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[170]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[170]),\n .O(wr_buf_in_data[170]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[28].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[169]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[169]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[169]),\n .O(wr_buf_in_data[169]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[28].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[168]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[168]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[168]),\n .O(wr_buf_in_data[168]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[29].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[179:178]),\n .DIB(wr_buf_in_data[177:176]),\n .DIC(wr_buf_in_data[175:174]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[179:178]),\n .DOB(wr_buf_out_data_w[177:176]),\n .DOC(wr_buf_out_data_w[175:174]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[29].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[29].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[179]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[179]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[179]),\n .O(wr_buf_in_data[179]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[29].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[178]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[178]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[178]),\n .O(wr_buf_in_data[178]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[29].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[177]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[177]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[177]),\n .O(wr_buf_in_data[177]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[29].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[176]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[176]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[176]),\n .O(wr_buf_in_data[176]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[29].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[175]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[175]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[175]),\n .O(wr_buf_in_data[175]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[29].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[174]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[174]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[174]),\n .O(wr_buf_in_data[174]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[2].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[17:16]),\n .DIB(wr_buf_in_data[15:14]),\n .DIC(wr_buf_in_data[13:12]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[17:16]),\n .DOB(wr_buf_out_data_w[15:14]),\n .DOC(wr_buf_out_data_w[13:12]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[2].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[2].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[17]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[17]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[17]),\n .O(wr_buf_in_data[17]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[2].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[16]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[16]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[16]),\n .O(wr_buf_in_data[16]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[2].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[15]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[15]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[15]),\n .O(wr_buf_in_data[15]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[2].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[14]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[14]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[14]),\n .O(wr_buf_in_data[14]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[2].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[13]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[13]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[13]),\n .O(wr_buf_in_data[13]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[2].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[12]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[12]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[12]),\n .O(wr_buf_in_data[12]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[30].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[185:184]),\n .DIB(wr_buf_in_data[183:182]),\n .DIC(wr_buf_in_data[181:180]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[185:184]),\n .DOB(wr_buf_out_data_w[183:182]),\n .DOC(wr_buf_out_data_w[181:180]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[30].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[30].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[185]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[185]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[185]),\n .O(wr_buf_in_data[185]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[30].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[184]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[184]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[184]),\n .O(wr_buf_in_data[184]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[30].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[183]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[183]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[183]),\n .O(wr_buf_in_data[183]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[30].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[182]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[182]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[182]),\n .O(wr_buf_in_data[182]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[30].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[181]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[181]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[181]),\n .O(wr_buf_in_data[181]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[30].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[180]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[180]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[180]),\n .O(wr_buf_in_data[180]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[31].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[191:190]),\n .DIB(wr_buf_in_data[189:188]),\n .DIC(wr_buf_in_data[187:186]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[191:190]),\n .DOB(wr_buf_out_data_w[189:188]),\n .DOC(wr_buf_out_data_w[187:186]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[31].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[31].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[191]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[191]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[191]),\n .O(wr_buf_in_data[191]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[31].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[190]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[190]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[190]),\n .O(wr_buf_in_data[190]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[31].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[189]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[189]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[189]),\n .O(wr_buf_in_data[189]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[31].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[188]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[188]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[188]),\n .O(wr_buf_in_data[188]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[31].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[187]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[187]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[187]),\n .O(wr_buf_in_data[187]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[31].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[186]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[186]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[186]),\n .O(wr_buf_in_data[186]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[32].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[197:196]),\n .DIB(wr_buf_in_data[195:194]),\n .DIC(wr_buf_in_data[193:192]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[197:196]),\n .DOB(wr_buf_out_data_w[195:194]),\n .DOC(wr_buf_out_data_w[193:192]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[32].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[32].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[197]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[197]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[197]),\n .O(wr_buf_in_data[197]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[32].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[196]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[196]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[196]),\n .O(wr_buf_in_data[196]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[32].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[195]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[195]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[195]),\n .O(wr_buf_in_data[195]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[32].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[194]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[194]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[194]),\n .O(wr_buf_in_data[194]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[32].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[193]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[193]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[193]),\n .O(wr_buf_in_data[193]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[32].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[192]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[192]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[192]),\n .O(wr_buf_in_data[192]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[33].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[203:202]),\n .DIB(wr_buf_in_data[201:200]),\n .DIC(wr_buf_in_data[199:198]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[203:202]),\n .DOB(wr_buf_out_data_w[201:200]),\n .DOC(wr_buf_out_data_w[199:198]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[33].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[33].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[203]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[203]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[203]),\n .O(wr_buf_in_data[203]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[33].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[202]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[202]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[202]),\n .O(wr_buf_in_data[202]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[33].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[201]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[201]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[201]),\n .O(wr_buf_in_data[201]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[33].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[200]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[200]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[200]),\n .O(wr_buf_in_data[200]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[33].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[199]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[199]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[199]),\n .O(wr_buf_in_data[199]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[33].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[198]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[198]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[198]),\n .O(wr_buf_in_data[198]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[34].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[209:208]),\n .DIB(wr_buf_in_data[207:206]),\n .DIC(wr_buf_in_data[205:204]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[209:208]),\n .DOB(wr_buf_out_data_w[207:206]),\n .DOC(wr_buf_out_data_w[205:204]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[34].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[34].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[209]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[209]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[209]),\n .O(wr_buf_in_data[209]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[34].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[208]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[208]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[208]),\n .O(wr_buf_in_data[208]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[34].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[207]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[207]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[207]),\n .O(wr_buf_in_data[207]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[34].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[206]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[206]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[206]),\n .O(wr_buf_in_data[206]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[34].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[205]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[205]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[205]),\n .O(wr_buf_in_data[205]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[34].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[204]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[204]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[204]),\n .O(wr_buf_in_data[204]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[35].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[215:214]),\n .DIB(wr_buf_in_data[213:212]),\n .DIC(wr_buf_in_data[211:210]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[215:214]),\n .DOB(wr_buf_out_data_w[213:212]),\n .DOC(wr_buf_out_data_w[211:210]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[35].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[35].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[215]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[215]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[215]),\n .O(wr_buf_in_data[215]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[35].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[214]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[214]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[214]),\n .O(wr_buf_in_data[214]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[35].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[213]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[213]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[213]),\n .O(wr_buf_in_data[213]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[35].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[212]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[212]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[212]),\n .O(wr_buf_in_data[212]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[35].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[211]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[211]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[211]),\n .O(wr_buf_in_data[211]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[35].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[210]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[210]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[210]),\n .O(wr_buf_in_data[210]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[36].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[221:220]),\n .DIB(wr_buf_in_data[219:218]),\n .DIC(wr_buf_in_data[217:216]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[221:220]),\n .DOB(wr_buf_out_data_w[219:218]),\n .DOC(wr_buf_out_data_w[217:216]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[36].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[36].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[221]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[221]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[221]),\n .O(wr_buf_in_data[221]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[36].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[220]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[220]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[220]),\n .O(wr_buf_in_data[220]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[36].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[219]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[219]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[219]),\n .O(wr_buf_in_data[219]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[36].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[218]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[218]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[218]),\n .O(wr_buf_in_data[218]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[36].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[217]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[217]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[217]),\n .O(wr_buf_in_data[217]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[36].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[216]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[216]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[216]),\n .O(wr_buf_in_data[216]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[37].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[227:226]),\n .DIB(wr_buf_in_data[225:224]),\n .DIC(wr_buf_in_data[223:222]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[227:226]),\n .DOB(wr_buf_out_data_w[225:224]),\n .DOC(wr_buf_out_data_w[223:222]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[37].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[37].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[227]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[227]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[227]),\n .O(wr_buf_in_data[227]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[37].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[226]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[226]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[226]),\n .O(wr_buf_in_data[226]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[37].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[225]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[225]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[225]),\n .O(wr_buf_in_data[225]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[37].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[224]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[224]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[224]),\n .O(wr_buf_in_data[224]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[37].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[223]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[223]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[223]),\n .O(wr_buf_in_data[223]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[37].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[222]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[222]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[222]),\n .O(wr_buf_in_data[222]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[38].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[233:232]),\n .DIB(wr_buf_in_data[231:230]),\n .DIC(wr_buf_in_data[229:228]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[233:232]),\n .DOB(wr_buf_out_data_w[231:230]),\n .DOC(wr_buf_out_data_w[229:228]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[38].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[38].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[233]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[233]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[233]),\n .O(wr_buf_in_data[233]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[38].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[232]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[232]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[232]),\n .O(wr_buf_in_data[232]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[38].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[231]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[231]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[231]),\n .O(wr_buf_in_data[231]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[38].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[230]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[230]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[230]),\n .O(wr_buf_in_data[230]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[38].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[229]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[229]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[229]),\n .O(wr_buf_in_data[229]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[38].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[228]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[228]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[228]),\n .O(wr_buf_in_data[228]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[39].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[239:238]),\n .DIB(wr_buf_in_data[237:236]),\n .DIC(wr_buf_in_data[235:234]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[239:238]),\n .DOB(wr_buf_out_data_w[237:236]),\n .DOC(wr_buf_out_data_w[235:234]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[39].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[39].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[239]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[239]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[239]),\n .O(wr_buf_in_data[239]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[39].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[238]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[238]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[238]),\n .O(wr_buf_in_data[238]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[39].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[237]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[237]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[237]),\n .O(wr_buf_in_data[237]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[39].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[236]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[236]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[236]),\n .O(wr_buf_in_data[236]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[39].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[235]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[235]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[235]),\n .O(wr_buf_in_data[235]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[39].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[234]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[234]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[234]),\n .O(wr_buf_in_data[234]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[3].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[23:22]),\n .DIB(wr_buf_in_data[21:20]),\n .DIC(wr_buf_in_data[19:18]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[23:22]),\n .DOB(wr_buf_out_data_w[21:20]),\n .DOC(wr_buf_out_data_w[19:18]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[3].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[3].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[23]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[23]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[23]),\n .O(wr_buf_in_data[23]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[3].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[22]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[22]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[22]),\n .O(wr_buf_in_data[22]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[3].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[21]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[21]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[21]),\n .O(wr_buf_in_data[21]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[3].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[20]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[20]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[20]),\n .O(wr_buf_in_data[20]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[3].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[19]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[19]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[19]),\n .O(wr_buf_in_data[19]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[3].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[18]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[18]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[18]),\n .O(wr_buf_in_data[18]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[40].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[245:244]),\n .DIB(wr_buf_in_data[243:242]),\n .DIC(wr_buf_in_data[241:240]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[245:244]),\n .DOB(wr_buf_out_data_w[243:242]),\n .DOC(wr_buf_out_data_w[241:240]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[40].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[40].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[245]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[245]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[245]),\n .O(wr_buf_in_data[245]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[40].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[244]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[244]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[244]),\n .O(wr_buf_in_data[244]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[40].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[243]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[243]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[243]),\n .O(wr_buf_in_data[243]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[40].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[242]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[242]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[242]),\n .O(wr_buf_in_data[242]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[40].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[241]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[241]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[241]),\n .O(wr_buf_in_data[241]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[40].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[240]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[240]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[240]),\n .O(wr_buf_in_data[240]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[41].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[251:250]),\n .DIB(wr_buf_in_data[249:248]),\n .DIC(wr_buf_in_data[247:246]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[251:250]),\n .DOB(wr_buf_out_data_w[249:248]),\n .DOC(wr_buf_out_data_w[247:246]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[41].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[41].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[251]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[251]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[251]),\n .O(wr_buf_in_data[251]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[41].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[250]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[250]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[250]),\n .O(wr_buf_in_data[250]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[41].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[249]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[249]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[249]),\n .O(wr_buf_in_data[249]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[41].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[248]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[248]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[248]),\n .O(wr_buf_in_data[248]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[41].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[247]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[247]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[247]),\n .O(wr_buf_in_data[247]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[41].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[246]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[246]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[246]),\n .O(wr_buf_in_data[246]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[42].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[257:256]),\n .DIB(wr_buf_in_data[255:254]),\n .DIC(wr_buf_in_data[253:252]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[257:256]),\n .DOB(wr_buf_out_data_w[255:254]),\n .DOC(wr_buf_out_data_w[253:252]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[42].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[42].RAM32M0_i_1 \n (.I0(D[1]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[1]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[1]),\n .O(wr_buf_in_data[257]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[42].RAM32M0_i_2 \n (.I0(D[0]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[0]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[0]),\n .O(wr_buf_in_data[256]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[42].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[255]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[255]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[255]),\n .O(wr_buf_in_data[255]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[42].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[254]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[254]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[254]),\n .O(wr_buf_in_data[254]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[42].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[253]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[253]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[253]),\n .O(wr_buf_in_data[253]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[42].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[252]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[252]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[252]),\n .O(wr_buf_in_data[252]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[43].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[263:262]),\n .DIB(wr_buf_in_data[261:260]),\n .DIC(wr_buf_in_data[259:258]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[263:262]),\n .DOB(wr_buf_out_data_w[261:260]),\n .DOC(wr_buf_out_data_w[259:258]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[43].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[43].RAM32M0_i_1 \n (.I0(D[7]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[7]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[7]),\n .O(wr_buf_in_data[263]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[43].RAM32M0_i_2 \n (.I0(D[6]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[6]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[6]),\n .O(wr_buf_in_data[262]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[43].RAM32M0_i_3 \n (.I0(D[5]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[5]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[5]),\n .O(wr_buf_in_data[261]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[43].RAM32M0_i_4 \n (.I0(D[4]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[4]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[4]),\n .O(wr_buf_in_data[260]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[43].RAM32M0_i_5 \n (.I0(D[3]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[3]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[3]),\n .O(wr_buf_in_data[259]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[43].RAM32M0_i_6 \n (.I0(D[2]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[2]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[2]),\n .O(wr_buf_in_data[258]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[44].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[269:268]),\n .DIB(wr_buf_in_data[267:266]),\n .DIC(wr_buf_in_data[265:264]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[269:268]),\n .DOB(wr_buf_out_data_w[267:266]),\n .DOC(wr_buf_out_data_w[265:264]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[44].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[44].RAM32M0_i_1 \n (.I0(D[13]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[13]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[13]),\n .O(wr_buf_in_data[269]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[44].RAM32M0_i_2 \n (.I0(D[12]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[12]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[12]),\n .O(wr_buf_in_data[268]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[44].RAM32M0_i_3 \n (.I0(D[11]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[11]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[11]),\n .O(wr_buf_in_data[267]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[44].RAM32M0_i_4 \n (.I0(D[10]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[10]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[10]),\n .O(wr_buf_in_data[266]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[44].RAM32M0_i_5 \n (.I0(D[9]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[9]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[9]),\n .O(wr_buf_in_data[265]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[44].RAM32M0_i_6 \n (.I0(D[8]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[8]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[8]),\n .O(wr_buf_in_data[264]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[45].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[275:274]),\n .DIB(wr_buf_in_data[273:272]),\n .DIC(wr_buf_in_data[271:270]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[275:274]),\n .DOB(wr_buf_out_data_w[273:272]),\n .DOC(wr_buf_out_data_w[271:270]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[45].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[45].RAM32M0_i_1 \n (.I0(D[19]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[19]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[19]),\n .O(wr_buf_in_data[275]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[45].RAM32M0_i_2 \n (.I0(D[18]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[18]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[18]),\n .O(wr_buf_in_data[274]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[45].RAM32M0_i_3 \n (.I0(D[17]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[17]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[17]),\n .O(wr_buf_in_data[273]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[45].RAM32M0_i_4 \n (.I0(D[16]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[16]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[16]),\n .O(wr_buf_in_data[272]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[45].RAM32M0_i_5 \n (.I0(D[15]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[15]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[15]),\n .O(wr_buf_in_data[271]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[45].RAM32M0_i_6 \n (.I0(D[14]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[14]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[14]),\n .O(wr_buf_in_data[270]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[46].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[281:280]),\n .DIB(wr_buf_in_data[279:278]),\n .DIC(wr_buf_in_data[277:276]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[281:280]),\n .DOB(wr_buf_out_data_w[279:278]),\n .DOC(wr_buf_out_data_w[277:276]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[46].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[46].RAM32M0_i_1 \n (.I0(D[25]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[25]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[25]),\n .O(wr_buf_in_data[281]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[46].RAM32M0_i_2 \n (.I0(D[24]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[24]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[24]),\n .O(wr_buf_in_data[280]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[46].RAM32M0_i_3 \n (.I0(D[23]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[23]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[23]),\n .O(wr_buf_in_data[279]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[46].RAM32M0_i_4 \n (.I0(D[22]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[22]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[22]),\n .O(wr_buf_in_data[278]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[46].RAM32M0_i_5 \n (.I0(D[21]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[21]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[21]),\n .O(wr_buf_in_data[277]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[46].RAM32M0_i_6 \n (.I0(D[20]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[20]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[20]),\n .O(wr_buf_in_data[276]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[47].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[287:286]),\n .DIB(wr_buf_in_data[285:284]),\n .DIC(wr_buf_in_data[283:282]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[287:286]),\n .DOB(wr_buf_out_data_w[285:284]),\n .DOC(wr_buf_out_data_w[283:282]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[47].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[47].RAM32M0_i_1 \n (.I0(D[31]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[31]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[31]),\n .O(wr_buf_in_data[287]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[47].RAM32M0_i_2 \n (.I0(D[30]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[30]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[30]),\n .O(wr_buf_in_data[286]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[47].RAM32M0_i_3 \n (.I0(D[29]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[29]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[29]),\n .O(wr_buf_in_data[285]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[47].RAM32M0_i_4 \n (.I0(D[28]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[28]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[28]),\n .O(wr_buf_in_data[284]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[47].RAM32M0_i_5 \n (.I0(D[27]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[27]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[27]),\n .O(wr_buf_in_data[283]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[47].RAM32M0_i_6 \n (.I0(D[26]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[26]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[26]),\n .O(wr_buf_in_data[282]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[4].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[29:28]),\n .DIB(wr_buf_in_data[27:26]),\n .DIC(wr_buf_in_data[25:24]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[29:28]),\n .DOB(wr_buf_out_data_w[27:26]),\n .DOC(wr_buf_out_data_w[25:24]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[4].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[4].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[29]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[29]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[29]),\n .O(wr_buf_in_data[29]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[4].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[28]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[28]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[28]),\n .O(wr_buf_in_data[28]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[4].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[27]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[27]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[27]),\n .O(wr_buf_in_data[27]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[4].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[26]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[26]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[26]),\n .O(wr_buf_in_data[26]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[4].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[25]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[25]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[25]),\n .O(wr_buf_in_data[25]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[4].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[24]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[24]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[24]),\n .O(wr_buf_in_data[24]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[5].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[35:34]),\n .DIB(wr_buf_in_data[33:32]),\n .DIC(wr_buf_in_data[31:30]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[35:34]),\n .DOB(wr_buf_out_data_w[33:32]),\n .DOC(wr_buf_out_data_w[31:30]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[5].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[5].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[35]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[35]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[35]),\n .O(wr_buf_in_data[35]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[5].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[34]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[34]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[34]),\n .O(wr_buf_in_data[34]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[5].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[33]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[33]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[33]),\n .O(wr_buf_in_data[33]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[5].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[32]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[32]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[32]),\n .O(wr_buf_in_data[32]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[5].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[31]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[31]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[31]),\n .O(wr_buf_in_data[31]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[5].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[30]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[30]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[30]),\n .O(wr_buf_in_data[30]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[6].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[41:40]),\n .DIB(wr_buf_in_data[39:38]),\n .DIC(wr_buf_in_data[37:36]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[41:40]),\n .DOB(wr_buf_out_data_w[39:38]),\n .DOC(wr_buf_out_data_w[37:36]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[6].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[6].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[41]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[41]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[41]),\n .O(wr_buf_in_data[41]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[6].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[40]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[40]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[40]),\n .O(wr_buf_in_data[40]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[6].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[39]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[39]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[39]),\n .O(wr_buf_in_data[39]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[6].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[38]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[38]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[38]),\n .O(wr_buf_in_data[38]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[6].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[37]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[37]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[37]),\n .O(wr_buf_in_data[37]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[6].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[36]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[36]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[36]),\n .O(wr_buf_in_data[36]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[7].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[47:46]),\n .DIB(wr_buf_in_data[45:44]),\n .DIC(wr_buf_in_data[43:42]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[47:46]),\n .DOB(wr_buf_out_data_w[45:44]),\n .DOC(wr_buf_out_data_w[43:42]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[7].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[7].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[47]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[47]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[47]),\n .O(wr_buf_in_data[47]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[7].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[46]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[46]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[46]),\n .O(wr_buf_in_data[46]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[7].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[45]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[45]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[45]),\n .O(wr_buf_in_data[45]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[7].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[44]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[44]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[44]),\n .O(wr_buf_in_data[44]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[7].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[43]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[43]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[43]),\n .O(wr_buf_in_data[43]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[7].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[42]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[42]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[42]),\n .O(wr_buf_in_data[42]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[8].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[53:52]),\n .DIB(wr_buf_in_data[51:50]),\n .DIC(wr_buf_in_data[49:48]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[53:52]),\n .DOB(wr_buf_out_data_w[51:50]),\n .DOC(wr_buf_out_data_w[49:48]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[8].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[8].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[53]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[53]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[53]),\n .O(wr_buf_in_data[53]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[8].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[52]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[52]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[52]),\n .O(wr_buf_in_data[52]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[8].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[51]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[51]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[51]),\n .O(wr_buf_in_data[51]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[8].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[50]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[50]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[50]),\n .O(wr_buf_in_data[50]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[8].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[49]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[49]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[49]),\n .O(wr_buf_in_data[49]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[8].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[48]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[48]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[48]),\n .O(wr_buf_in_data[48]));\n (* box_type = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[9].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[59:58]),\n .DIB(wr_buf_in_data[57:56]),\n .DIC(wr_buf_in_data[55:54]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[59:58]),\n .DOB(wr_buf_out_data_w[57:56]),\n .DOC(wr_buf_out_data_w[55:54]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[9].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[9].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[59]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[59]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[59]),\n .O(wr_buf_in_data[59]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[9].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[58]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[58]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[58]),\n .O(wr_buf_in_data[58]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[9].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[57]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[57]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[57]),\n .O(wr_buf_in_data[57]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[9].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[56]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[56]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[56]),\n .O(wr_buf_in_data[56]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[9].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[55]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[55]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[55]),\n .O(wr_buf_in_data[55]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[9].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[54]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[54]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[54]),\n .O(wr_buf_in_data[54]));\n FDRE #(\n .INIT(1'b0)) \n \\write_data_control.wb_wr_data_addr0_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(wb_wr_data_addr0_ns),\n .Q(wb_wr_data_addr0_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_data_control.wb_wr_data_addr_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(wb_wr_data_addr_w[1]),\n .Q(wb_wr_data_addr_r[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_data_control.wb_wr_data_addr_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(wb_wr_data_addr_w[2]),\n .Q(wb_wr_data_addr_r[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_data_control.wb_wr_data_addr_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(wb_wr_data_addr_w[3]),\n .Q(wb_wr_data_addr_r[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\write_data_control.wb_wr_data_addr_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(wb_wr_data_addr_w[4]),\n .Q(wb_wr_data_addr_r[4]),\n .R(1'b0));\n LUT1 #(\n .INIT(2'h1)) \n \\write_data_control.wr_data_indx_r[0]_i_1 \n (.I0(\\write_data_control.wr_data_indx_r_reg__0 [0]),\n .O(p_0_in__0__0[0]));\n LUT2 #(\n .INIT(4'h6)) \n \\write_data_control.wr_data_indx_r[1]_i_1 \n (.I0(\\write_data_control.wr_data_indx_r_reg__0 [0]),\n .I1(\\write_data_control.wr_data_indx_r_reg__0 [1]),\n .O(p_0_in__0__0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1485\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\write_data_control.wr_data_indx_r[2]_i_1 \n (.I0(\\write_data_control.wr_data_indx_r_reg__0 [0]),\n .I1(\\write_data_control.wr_data_indx_r_reg__0 [1]),\n .I2(\\write_data_control.wr_data_indx_r_reg__0 [2]),\n .O(p_0_in__0__0[2]));\n LUT6 #(\n .INIT(64'hF000FFFF10001000)) \n \\write_data_control.wr_data_indx_r[3]_i_1 \n (.I0(\\occupied_counter.occ_cnt_reg_n_0_[15] ),\n .I1(p_4_in),\n .I2(p_0_in__0_0),\n .I3(\\rd_buf_indx.ram_init_done_r_lcl_reg ),\n .I4(app_wdf_rdy_r_copy1),\n .I5(p_0_in),\n .O(wr_data_addr_le));\n (* SOFT_HLUTNM = \"soft_lutpair1485\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\write_data_control.wr_data_indx_r[3]_i_2 \n (.I0(\\write_data_control.wr_data_indx_r_reg__0 [2]),\n .I1(\\write_data_control.wr_data_indx_r_reg__0 [1]),\n .I2(\\write_data_control.wr_data_indx_r_reg__0 [0]),\n .I3(\\write_data_control.wr_data_indx_r_reg__0 [3]),\n .O(p_0_in__0__0[3]));\n FDSE #(\n .INIT(1'b1)) \n \\write_data_control.wr_data_indx_r_reg[0] \n (.C(CLK),\n .CE(wr_data_addr_le),\n .D(p_0_in__0__0[0]),\n .Q(\\write_data_control.wr_data_indx_r_reg__0 [0]),\n .S(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\write_data_control.wr_data_indx_r_reg[1] \n (.C(CLK),\n .CE(wr_data_addr_le),\n .D(p_0_in__0__0[1]),\n .Q(\\write_data_control.wr_data_indx_r_reg__0 [1]),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\write_data_control.wr_data_indx_r_reg[2] \n (.C(CLK),\n .CE(wr_data_addr_le),\n .D(p_0_in__0__0[2]),\n .Q(\\write_data_control.wr_data_indx_r_reg__0 [2]),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\write_data_control.wr_data_indx_r_reg[3] \n (.C(CLK),\n .CE(wr_data_addr_le),\n .D(p_0_in__0__0[3]),\n .Q(\\write_data_control.wr_data_indx_r_reg__0 [3]),\n .R(reset_reg));\nendmodule\n\nmodule dvi_pll\n (pixel_clock,\n dvi_bit_clock,\n sysclk);\n output pixel_clock;\n output dvi_bit_clock;\n input sysclk;\n\n wire dvi_bit_clock;\n wire pixel_clock;\n wire sysclk;\n\n dvi_pll_dvi_pll_clk_wiz inst\n (.dvi_bit_clock(dvi_bit_clock),\n .pixel_clock(pixel_clock),\n .sysclk(sysclk));\nendmodule\n\n(* ORIG_REF_NAME = \"dvi_pll_clk_wiz\" *) \nmodule dvi_pll_dvi_pll_clk_wiz\n (pixel_clock,\n dvi_bit_clock,\n sysclk);\n output pixel_clock;\n output dvi_bit_clock;\n input sysclk;\n\n wire clkfbout_buf_dvi_pll;\n wire clkfbout_dvi_pll;\n wire dvi_bit_clock;\n wire dvi_bit_clock_dvi_pll;\n wire pixel_clock;\n wire pixel_clock_dvi_pll;\n wire sysclk;\n wire sysclk_dvi_pll;\n wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED;\n wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED;\n wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED;\n wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED;\n wire NLW_plle2_adv_inst_DRDY_UNCONNECTED;\n wire NLW_plle2_adv_inst_LOCKED_UNCONNECTED;\n wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED;\n\n (* box_type = \"PRIMITIVE\" *) \n BUFG clkf_buf\n (.I(clkfbout_dvi_pll),\n .O(clkfbout_buf_dvi_pll));\n (* box_type = \"PRIMITIVE\" *) \n BUFG clkin1_bufg\n (.I(sysclk),\n .O(sysclk_dvi_pll));\n (* box_type = \"PRIMITIVE\" *) \n BUFG clkout1_buf\n (.I(pixel_clock_dvi_pll),\n .O(pixel_clock));\n (* box_type = \"PRIMITIVE\" *) \n BUFG clkout2_buf\n (.I(dvi_bit_clock_dvi_pll),\n .O(dvi_bit_clock));\n (* box_type = \"PRIMITIVE\" *) \n PLLE2_ADV #(\n .BANDWIDTH(\"OPTIMIZED\"),\n .CLKFBOUT_MULT(37),\n .CLKFBOUT_PHASE(0.000000),\n .CLKIN1_PERIOD(5.000000),\n .CLKIN2_PERIOD(0.000000),\n .CLKOUT0_DIVIDE(10),\n .CLKOUT0_DUTY_CYCLE(0.500000),\n .CLKOUT0_PHASE(0.000000),\n .CLKOUT1_DIVIDE(2),\n .CLKOUT1_DUTY_CYCLE(0.500000),\n .CLKOUT1_PHASE(0.000000),\n .CLKOUT2_DIVIDE(1),\n .CLKOUT2_DUTY_CYCLE(0.500000),\n .CLKOUT2_PHASE(0.000000),\n .CLKOUT3_DIVIDE(1),\n .CLKOUT3_DUTY_CYCLE(0.500000),\n .CLKOUT3_PHASE(0.000000),\n .CLKOUT4_DIVIDE(1),\n .CLKOUT4_DUTY_CYCLE(0.500000),\n .CLKOUT4_PHASE(0.000000),\n .CLKOUT5_DIVIDE(1),\n .CLKOUT5_DUTY_CYCLE(0.500000),\n .CLKOUT5_PHASE(0.000000),\n .COMPENSATION(\"BUF_IN\"),\n .DIVCLK_DIVIDE(5),\n .IS_CLKINSEL_INVERTED(1'b0),\n .IS_PWRDWN_INVERTED(1'b0),\n .IS_RST_INVERTED(1'b0),\n .REF_JITTER1(0.010000),\n .REF_JITTER2(0.010000),\n .STARTUP_WAIT(\"FALSE\")) \n plle2_adv_inst\n (.CLKFBIN(clkfbout_buf_dvi_pll),\n .CLKFBOUT(clkfbout_dvi_pll),\n .CLKIN1(sysclk_dvi_pll),\n .CLKIN2(1'b0),\n .CLKINSEL(1'b1),\n .CLKOUT0(pixel_clock_dvi_pll),\n .CLKOUT1(dvi_bit_clock_dvi_pll),\n .CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED),\n .CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED),\n .CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED),\n .CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED),\n .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DCLK(1'b0),\n .DEN(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]),\n .DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED),\n .DWE(1'b0),\n .LOCKED(NLW_plle2_adv_inst_LOCKED_UNCONNECTED),\n .PWRDWN(1'b0),\n .RST(1'b0));\nendmodule\n\nmodule dvi_tx\n (hdmi_d0,\n hdmi_d1,\n hdmi_d2,\n hdmi_clk,\n dvi_bit_clock,\n pixel_clock,\n SR,\n dvi_den,\n reset_n_IBUF,\n D);\n output [1:0]hdmi_d0;\n output [1:0]hdmi_d1;\n output [1:0]hdmi_d2;\n output [1:0]hdmi_clk;\n input dvi_bit_clock;\n input pixel_clock;\n input [0:0]SR;\n input dvi_den;\n input reset_n_IBUF;\n input [1:0]D;\n\n wire [1:0]D;\n wire RST;\n wire [0:0]SR;\n wire den_lat;\n wire dvi_bit_clock;\n wire dvi_den;\n wire \\gen_lane[0].lane_enc_n_1 ;\n wire [1:0]hdmi_clk;\n wire [1:0]hdmi_d0;\n wire [1:0]hdmi_d1;\n wire [1:0]hdmi_d2;\n wire pixel_clock;\n wire reset_n_IBUF;\n wire [9:0]tmds_enc_0;\n wire [8:0]tmds_enc_10;\n wire [2:0]tmds_enc_20;\n\n dvi_tx_clk_drv clock_phy\n (.hdmi_clk(hdmi_clk),\n .pixel_clock(pixel_clock));\n dvi_tx_tmds_enc \\gen_lane[0].lane_enc \n (.D(D),\n .Q({tmds_enc_0[9:8],tmds_enc_0[2],tmds_enc_0[0]}),\n .SR(SR),\n .\\cnt_q_reg[8]_0 (\\gen_lane[0].lane_enc_n_1 ),\n .den_lat(den_lat),\n .dvi_den(dvi_den),\n .pixel_clock(pixel_clock),\n .reset_n_IBUF(reset_n_IBUF));\n dvi_tx_tmds_phy \\gen_lane[0].lane_phy \n (.Q({tmds_enc_0[9:8],tmds_enc_0[2],tmds_enc_0[0]}),\n .RST(RST),\n .SR(SR),\n .dvi_bit_clock(dvi_bit_clock),\n .hdmi_d0(hdmi_d0),\n .pixel_clock(pixel_clock));\n dvi_tx_tmds_enc_0 \\gen_lane[1].lane_enc \n (.SR(SR),\n .den_lat(den_lat),\n .den_lat_reg(\\gen_lane[0].lane_enc_n_1 ),\n .pixel_clock(pixel_clock),\n .tmds_enc_10({tmds_enc_10[8],tmds_enc_10[2],tmds_enc_10[0]}));\n dvi_tx_tmds_phy_1 \\gen_lane[1].lane_phy \n (.RST(RST),\n .dvi_bit_clock(dvi_bit_clock),\n .hdmi_d1(hdmi_d1),\n .pixel_clock(pixel_clock),\n .tmds_enc_10({tmds_enc_10[8],tmds_enc_10[2],tmds_enc_10[0]}));\n dvi_tx_tmds_enc_2 \\gen_lane[2].lane_enc \n (.Q({tmds_enc_20[2],tmds_enc_20[0]}),\n .SR(SR),\n .den_lat(den_lat),\n .den_lat_reg(\\gen_lane[0].lane_enc_n_1 ),\n .pixel_clock(pixel_clock));\n dvi_tx_tmds_phy_3 \\gen_lane[2].lane_phy \n (.Q({tmds_enc_20[2],tmds_enc_20[0]}),\n .RST(RST),\n .dvi_bit_clock(dvi_bit_clock),\n .hdmi_d2(hdmi_d2),\n .pixel_clock(pixel_clock),\n .tmds_enc_10(tmds_enc_10[8]));\nendmodule\n\nmodule dvi_tx_clk_drv\n (hdmi_clk,\n pixel_clock);\n output [1:0]hdmi_clk;\n input pixel_clock;\n\n wire [1:0]hdmi_clk;\n wire pixel_clock;\n wire tmds_clk_pre;\n wire NLW_clk_oddr_R_UNCONNECTED;\n wire NLW_clk_oddr_S_UNCONNECTED;\n\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* XILINX_LEGACY_PRIM = \"OBUFDS\" *) \n (* box_type = \"PRIMITIVE\" *) \n OBUFDS #(\n .IOSTANDARD(\"DEFAULT\")) \n clk_obuf\n (.I(tmds_clk_pre),\n .O(hdmi_clk[1]),\n .OB(hdmi_clk[0]));\n (* __SRVAL = \"TRUE\" *) \n (* box_type = \"PRIMITIVE\" *) \n ODDR #(\n .DDR_CLK_EDGE(\"OPPOSITE_EDGE\"),\n .INIT(1'b0),\n .IS_C_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .SRTYPE(\"SYNC\")) \n clk_oddr\n (.C(pixel_clock),\n .CE(1'b1),\n .D1(1'b1),\n .D2(1'b0),\n .Q(tmds_clk_pre),\n .R(NLW_clk_oddr_R_UNCONNECTED),\n .S(NLW_clk_oddr_S_UNCONNECTED));\nendmodule\n\nmodule dvi_tx_tmds_enc\n (den_lat,\n \\cnt_q_reg[8]_0 ,\n Q,\n SR,\n dvi_den,\n pixel_clock,\n reset_n_IBUF,\n D);\n output den_lat;\n output \\cnt_q_reg[8]_0 ;\n output [3:0]Q;\n input [0:0]SR;\n input dvi_den;\n input pixel_clock;\n input reset_n_IBUF;\n input [1:0]D;\n\n wire [1:0]D;\n wire [3:0]Q;\n wire [0:0]SR;\n wire [8:0]cnt_d0;\n wire [8:0]cnt_q;\n wire \\cnt_q[0]_i_1__0_n_0 ;\n wire \\cnt_q[0]_i_3_n_0 ;\n wire \\cnt_q[0]_i_4__0_n_0 ;\n wire \\cnt_q[0]_i_5_n_0 ;\n wire \\cnt_q[0]_i_6_n_0 ;\n wire \\cnt_q[1]_i_1_n_0 ;\n wire \\cnt_q[1]_i_3_n_0 ;\n wire \\cnt_q[1]_i_4_n_0 ;\n wire \\cnt_q[1]_i_5_n_0 ;\n wire \\cnt_q[1]_i_6_n_0 ;\n wire \\cnt_q[2]_i_1_n_0 ;\n wire \\cnt_q[3]_i_1_n_0 ;\n wire \\cnt_q[4]_i_1_n_0 ;\n wire \\cnt_q[4]_i_3_n_0 ;\n wire \\cnt_q[4]_i_4_n_0 ;\n wire \\cnt_q[4]_i_5_n_0 ;\n wire \\cnt_q[4]_i_6_n_0 ;\n wire \\cnt_q[5]_i_1_n_0 ;\n wire \\cnt_q[5]_i_3_n_0 ;\n wire \\cnt_q[5]_i_4_n_0 ;\n wire \\cnt_q[5]_i_5_n_0 ;\n wire \\cnt_q[5]_i_6_n_0 ;\n wire \\cnt_q[6]_i_1_n_0 ;\n wire \\cnt_q[7]_i_1_n_0 ;\n wire \\cnt_q[8]_i_1_n_0 ;\n wire \\cnt_q[8]_i_3_n_0 ;\n wire \\cnt_q_reg[0]_i_2_n_0 ;\n wire \\cnt_q_reg[0]_i_2_n_1 ;\n wire \\cnt_q_reg[0]_i_2_n_2 ;\n wire \\cnt_q_reg[0]_i_2_n_3 ;\n wire \\cnt_q_reg[1]_i_2_n_0 ;\n wire \\cnt_q_reg[1]_i_2_n_1 ;\n wire \\cnt_q_reg[1]_i_2_n_2 ;\n wire \\cnt_q_reg[1]_i_2_n_3 ;\n wire \\cnt_q_reg[1]_i_2_n_4 ;\n wire \\cnt_q_reg[1]_i_2_n_5 ;\n wire \\cnt_q_reg[1]_i_2_n_6 ;\n wire \\cnt_q_reg[1]_i_2_n_7 ;\n wire \\cnt_q_reg[4]_i_2_n_0 ;\n wire \\cnt_q_reg[4]_i_2_n_1 ;\n wire \\cnt_q_reg[4]_i_2_n_2 ;\n wire \\cnt_q_reg[4]_i_2_n_3 ;\n wire \\cnt_q_reg[5]_i_2_n_1 ;\n wire \\cnt_q_reg[5]_i_2_n_2 ;\n wire \\cnt_q_reg[5]_i_2_n_3 ;\n wire \\cnt_q_reg[5]_i_2_n_4 ;\n wire \\cnt_q_reg[5]_i_2_n_5 ;\n wire \\cnt_q_reg[5]_i_2_n_6 ;\n wire \\cnt_q_reg[5]_i_2_n_7 ;\n wire \\cnt_q_reg[8]_0 ;\n wire [1:0]ctrl_lat;\n wire den_lat;\n wire dvi_den;\n wire pixel_clock;\n wire q_out23_in;\n wire q_out2_carry_i_1_n_0;\n wire q_out2_carry_i_2_n_0;\n wire q_out2_carry_i_3_n_0;\n wire q_out2_carry_n_2;\n wire q_out2_carry_n_3;\n wire reset_n_IBUF;\n wire \\tmds[0]_i_1_n_0 ;\n wire \\tmds[2]_i_1_n_0 ;\n wire \\tmds[8]_i_1_n_0 ;\n wire \\tmds[9]_i_1_n_0 ;\n wire [3:3]\\NLW_cnt_q_reg[5]_i_2_CO_UNCONNECTED ;\n wire [3:0]\\NLW_cnt_q_reg[8]_i_2_CO_UNCONNECTED ;\n wire [3:1]\\NLW_cnt_q_reg[8]_i_2_O_UNCONNECTED ;\n wire [3:3]NLW_q_out2_carry_CO_UNCONNECTED;\n wire [3:0]NLW_q_out2_carry_O_UNCONNECTED;\n\n LUT2 #(\n .INIT(4'h7)) \n \\cnt_q[0]_i_1 \n (.I0(reset_n_IBUF),\n .I1(den_lat),\n .O(\\cnt_q_reg[8]_0 ));\n LUT4 #(\n .INIT(16'hFB08)) \n \\cnt_q[0]_i_1__0 \n (.I0(cnt_q[0]),\n .I1(cnt_q[8]),\n .I2(q_out23_in),\n .I3(cnt_d0[0]),\n .O(\\cnt_q[0]_i_1__0_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_q[0]_i_3 \n (.I0(cnt_q[3]),\n .O(\\cnt_q[0]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\cnt_q[0]_i_4__0 \n (.I0(cnt_q[2]),\n .O(\\cnt_q[0]_i_4__0_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\cnt_q[0]_i_5 \n (.I0(cnt_q[1]),\n .O(\\cnt_q[0]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\cnt_q[0]_i_6 \n (.I0(cnt_q[0]),\n .O(\\cnt_q[0]_i_6_n_0 ));\n LUT4 #(\n .INIT(16'hFB08)) \n \\cnt_q[1]_i_1 \n (.I0(\\cnt_q_reg[1]_i_2_n_7 ),\n .I1(cnt_q[8]),\n .I2(q_out23_in),\n .I3(cnt_d0[1]),\n .O(\\cnt_q[1]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h6)) \n \\cnt_q[1]_i_3 \n (.I0(cnt_q[3]),\n .I1(cnt_q[4]),\n .O(\\cnt_q[1]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_q[1]_i_4 \n (.I0(cnt_q[3]),\n .O(\\cnt_q[1]_i_4_n_0 ));\n LUT2 #(\n .INIT(4'h6)) \n \\cnt_q[1]_i_5 \n (.I0(cnt_q[1]),\n .I1(cnt_q[2]),\n .O(\\cnt_q[1]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_q[1]_i_6 \n (.I0(cnt_q[1]),\n .O(\\cnt_q[1]_i_6_n_0 ));\n LUT4 #(\n .INIT(16'hFB08)) \n \\cnt_q[2]_i_1 \n (.I0(\\cnt_q_reg[1]_i_2_n_6 ),\n .I1(cnt_q[8]),\n .I2(q_out23_in),\n .I3(cnt_d0[2]),\n .O(\\cnt_q[2]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hFB08)) \n \\cnt_q[3]_i_1 \n (.I0(\\cnt_q_reg[1]_i_2_n_5 ),\n .I1(cnt_q[8]),\n .I2(q_out23_in),\n .I3(cnt_d0[3]),\n .O(\\cnt_q[3]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hFB08)) \n \\cnt_q[4]_i_1 \n (.I0(\\cnt_q_reg[1]_i_2_n_4 ),\n .I1(cnt_q[8]),\n .I2(q_out23_in),\n .I3(cnt_d0[4]),\n .O(\\cnt_q[4]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_q[4]_i_3 \n (.I0(cnt_q[7]),\n .O(\\cnt_q[4]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_q[4]_i_4 \n (.I0(cnt_q[6]),\n .O(\\cnt_q[4]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_q[4]_i_5 \n (.I0(cnt_q[5]),\n .O(\\cnt_q[4]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_q[4]_i_6 \n (.I0(cnt_q[4]),\n .O(\\cnt_q[4]_i_6_n_0 ));\n LUT4 #(\n .INIT(16'hFB08)) \n \\cnt_q[5]_i_1 \n (.I0(\\cnt_q_reg[5]_i_2_n_7 ),\n .I1(cnt_q[8]),\n .I2(q_out23_in),\n .I3(cnt_d0[5]),\n .O(\\cnt_q[5]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\cnt_q[5]_i_3 \n (.I0(cnt_q[8]),\n .O(\\cnt_q[5]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\cnt_q[5]_i_4 \n (.I0(cnt_q[7]),\n .O(\\cnt_q[5]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\cnt_q[5]_i_5 \n (.I0(cnt_q[6]),\n .O(\\cnt_q[5]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\cnt_q[5]_i_6 \n (.I0(cnt_q[5]),\n .O(\\cnt_q[5]_i_6_n_0 ));\n LUT4 #(\n .INIT(16'hFB08)) \n \\cnt_q[6]_i_1 \n (.I0(\\cnt_q_reg[5]_i_2_n_6 ),\n .I1(cnt_q[8]),\n .I2(q_out23_in),\n .I3(cnt_d0[6]),\n .O(\\cnt_q[6]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hFB08)) \n \\cnt_q[7]_i_1 \n (.I0(\\cnt_q_reg[5]_i_2_n_5 ),\n .I1(cnt_q[8]),\n .I2(q_out23_in),\n .I3(cnt_d0[7]),\n .O(\\cnt_q[7]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hFB08)) \n \\cnt_q[8]_i_1 \n (.I0(\\cnt_q_reg[5]_i_2_n_4 ),\n .I1(cnt_q[8]),\n .I2(q_out23_in),\n .I3(cnt_d0[8]),\n .O(\\cnt_q[8]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_q[8]_i_3 \n (.I0(cnt_q[8]),\n .O(\\cnt_q[8]_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_q_reg[0] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\cnt_q[0]_i_1__0_n_0 ),\n .Q(cnt_q[0]),\n .R(\\cnt_q_reg[8]_0 ));\n CARRY4 \\cnt_q_reg[0]_i_2 \n (.CI(1'b0),\n .CO({\\cnt_q_reg[0]_i_2_n_0 ,\\cnt_q_reg[0]_i_2_n_1 ,\\cnt_q_reg[0]_i_2_n_2 ,\\cnt_q_reg[0]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({cnt_q[3:1],1'b0}),\n .O(cnt_d0[3:0]),\n .S({\\cnt_q[0]_i_3_n_0 ,\\cnt_q[0]_i_4__0_n_0 ,\\cnt_q[0]_i_5_n_0 ,\\cnt_q[0]_i_6_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_q_reg[1] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\cnt_q[1]_i_1_n_0 ),\n .Q(cnt_q[1]),\n .R(\\cnt_q_reg[8]_0 ));\n CARRY4 \\cnt_q_reg[1]_i_2 \n (.CI(1'b0),\n .CO({\\cnt_q_reg[1]_i_2_n_0 ,\\cnt_q_reg[1]_i_2_n_1 ,\\cnt_q_reg[1]_i_2_n_2 ,\\cnt_q_reg[1]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({cnt_q[3],1'b0,cnt_q[1],1'b0}),\n .O({\\cnt_q_reg[1]_i_2_n_4 ,\\cnt_q_reg[1]_i_2_n_5 ,\\cnt_q_reg[1]_i_2_n_6 ,\\cnt_q_reg[1]_i_2_n_7 }),\n .S({\\cnt_q[1]_i_3_n_0 ,\\cnt_q[1]_i_4_n_0 ,\\cnt_q[1]_i_5_n_0 ,\\cnt_q[1]_i_6_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_q_reg[2] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\cnt_q[2]_i_1_n_0 ),\n .Q(cnt_q[2]),\n .R(\\cnt_q_reg[8]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_q_reg[3] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\cnt_q[3]_i_1_n_0 ),\n .Q(cnt_q[3]),\n .R(\\cnt_q_reg[8]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_q_reg[4] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\cnt_q[4]_i_1_n_0 ),\n .Q(cnt_q[4]),\n .R(\\cnt_q_reg[8]_0 ));\n CARRY4 \\cnt_q_reg[4]_i_2 \n (.CI(\\cnt_q_reg[0]_i_2_n_0 ),\n .CO({\\cnt_q_reg[4]_i_2_n_0 ,\\cnt_q_reg[4]_i_2_n_1 ,\\cnt_q_reg[4]_i_2_n_2 ,\\cnt_q_reg[4]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI(cnt_q[7:4]),\n .O(cnt_d0[7:4]),\n .S({\\cnt_q[4]_i_3_n_0 ,\\cnt_q[4]_i_4_n_0 ,\\cnt_q[4]_i_5_n_0 ,\\cnt_q[4]_i_6_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_q_reg[5] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\cnt_q[5]_i_1_n_0 ),\n .Q(cnt_q[5]),\n .R(\\cnt_q_reg[8]_0 ));\n CARRY4 \\cnt_q_reg[5]_i_2 \n (.CI(\\cnt_q_reg[1]_i_2_n_0 ),\n .CO({\\NLW_cnt_q_reg[5]_i_2_CO_UNCONNECTED [3],\\cnt_q_reg[5]_i_2_n_1 ,\\cnt_q_reg[5]_i_2_n_2 ,\\cnt_q_reg[5]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\cnt_q_reg[5]_i_2_n_4 ,\\cnt_q_reg[5]_i_2_n_5 ,\\cnt_q_reg[5]_i_2_n_6 ,\\cnt_q_reg[5]_i_2_n_7 }),\n .S({\\cnt_q[5]_i_3_n_0 ,\\cnt_q[5]_i_4_n_0 ,\\cnt_q[5]_i_5_n_0 ,\\cnt_q[5]_i_6_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_q_reg[6] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\cnt_q[6]_i_1_n_0 ),\n .Q(cnt_q[6]),\n .R(\\cnt_q_reg[8]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_q_reg[7] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\cnt_q[7]_i_1_n_0 ),\n .Q(cnt_q[7]),\n .R(\\cnt_q_reg[8]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_q_reg[8] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\cnt_q[8]_i_1_n_0 ),\n .Q(cnt_q[8]),\n .R(\\cnt_q_reg[8]_0 ));\n CARRY4 \\cnt_q_reg[8]_i_2 \n (.CI(\\cnt_q_reg[4]_i_2_n_0 ),\n .CO(\\NLW_cnt_q_reg[8]_i_2_CO_UNCONNECTED [3:0]),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\NLW_cnt_q_reg[8]_i_2_O_UNCONNECTED [3:1],cnt_d0[8]}),\n .S({1'b0,1'b0,1'b0,\\cnt_q[8]_i_3_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\ctrl_lat_reg[0] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(D[0]),\n .Q(ctrl_lat[0]),\n .R(SR));\n FDRE #(\n .INIT(1'b0)) \n \\ctrl_lat_reg[1] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(D[1]),\n .Q(ctrl_lat[1]),\n .R(SR));\n FDRE #(\n .INIT(1'b0)) \n den_lat_reg\n (.C(pixel_clock),\n .CE(1'b1),\n .D(dvi_den),\n .Q(den_lat),\n .R(SR));\n CARRY4 q_out2_carry\n (.CI(1'b0),\n .CO({NLW_q_out2_carry_CO_UNCONNECTED[3],q_out23_in,q_out2_carry_n_2,q_out2_carry_n_3}),\n .CYINIT(1'b1),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(NLW_q_out2_carry_O_UNCONNECTED[3:0]),\n .S({1'b0,q_out2_carry_i_1_n_0,q_out2_carry_i_2_n_0,q_out2_carry_i_3_n_0}));\n LUT3 #(\n .INIT(8'h01)) \n q_out2_carry_i_1\n (.I0(cnt_q[6]),\n .I1(cnt_q[7]),\n .I2(cnt_q[8]),\n .O(q_out2_carry_i_1_n_0));\n LUT3 #(\n .INIT(8'h01)) \n q_out2_carry_i_2\n (.I0(cnt_q[3]),\n .I1(cnt_q[4]),\n .I2(cnt_q[5]),\n .O(q_out2_carry_i_2_n_0));\n LUT3 #(\n .INIT(8'h01)) \n q_out2_carry_i_3\n (.I0(cnt_q[2]),\n .I1(cnt_q[1]),\n .I2(cnt_q[0]),\n .O(q_out2_carry_i_3_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair0\" *) \n LUT4 #(\n .INIT(16'h2F20)) \n \\tmds[0]_i_1 \n (.I0(cnt_q[8]),\n .I1(q_out23_in),\n .I2(den_lat),\n .I3(ctrl_lat[0]),\n .O(\\tmds[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1\" *) \n LUT4 #(\n .INIT(16'h0C55)) \n \\tmds[2]_i_1 \n (.I0(ctrl_lat[0]),\n .I1(cnt_q[8]),\n .I2(q_out23_in),\n .I3(den_lat),\n .O(\\tmds[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1\" *) \n LUT2 #(\n .INIT(4'hB)) \n \\tmds[8]_i_1 \n (.I0(den_lat),\n .I1(ctrl_lat[0]),\n .O(\\tmds[8]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair0\" *) \n LUT5 #(\n .INIT(32'h00F09999)) \n \\tmds[9]_i_1 \n (.I0(ctrl_lat[1]),\n .I1(ctrl_lat[0]),\n .I2(cnt_q[8]),\n .I3(q_out23_in),\n .I4(den_lat),\n .O(\\tmds[9]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\tmds_reg[0] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\tmds[0]_i_1_n_0 ),\n .Q(Q[0]),\n .R(SR));\n FDRE #(\n .INIT(1'b0)) \n \\tmds_reg[2] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\tmds[2]_i_1_n_0 ),\n .Q(Q[1]),\n .R(SR));\n FDRE #(\n .INIT(1'b0)) \n \\tmds_reg[8] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\tmds[8]_i_1_n_0 ),\n .Q(Q[2]),\n .R(SR));\n FDRE #(\n .INIT(1'b0)) \n \\tmds_reg[9] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\tmds[9]_i_1_n_0 ),\n .Q(Q[3]),\n .R(SR));\nendmodule\n\n(* ORIG_REF_NAME = \"dvi_tx_tmds_enc\" *) \nmodule dvi_tx_tmds_enc_0\n (tmds_enc_10,\n den_lat_reg,\n pixel_clock,\n SR,\n den_lat);\n output [2:0]tmds_enc_10;\n input den_lat_reg;\n input pixel_clock;\n input [0:0]SR;\n input den_lat;\n\n wire [0:0]SR;\n wire \\cnt_q[0]_i_1__1_n_0 ;\n wire \\cnt_q[0]_i_3__0_n_0 ;\n wire \\cnt_q[0]_i_4__1_n_0 ;\n wire \\cnt_q[0]_i_5__0_n_0 ;\n wire \\cnt_q[0]_i_6__0_n_0 ;\n wire \\cnt_q[1]_i_1__0_n_0 ;\n wire \\cnt_q[1]_i_3_n_0 ;\n wire \\cnt_q[1]_i_4__0_n_0 ;\n wire \\cnt_q[1]_i_5_n_0 ;\n wire \\cnt_q[1]_i_6__0_n_0 ;\n wire \\cnt_q[2]_i_1__0_n_0 ;\n wire \\cnt_q[3]_i_1__0_n_0 ;\n wire \\cnt_q[4]_i_1__0_n_0 ;\n wire \\cnt_q[4]_i_3__0_n_0 ;\n wire \\cnt_q[4]_i_4__0_n_0 ;\n wire \\cnt_q[4]_i_5__0_n_0 ;\n wire \\cnt_q[4]_i_6__0_n_0 ;\n wire \\cnt_q[5]_i_1__0_n_0 ;\n wire \\cnt_q[5]_i_3__0_n_0 ;\n wire \\cnt_q[5]_i_4__0_n_0 ;\n wire \\cnt_q[5]_i_5__0_n_0 ;\n wire \\cnt_q[5]_i_6__0_n_0 ;\n wire \\cnt_q[6]_i_1__0_n_0 ;\n wire \\cnt_q[7]_i_1__0_n_0 ;\n wire \\cnt_q[8]_i_1__0_n_0 ;\n wire \\cnt_q[8]_i_3__0_n_0 ;\n wire \\cnt_q_reg[0]_i_2__0_n_0 ;\n wire \\cnt_q_reg[0]_i_2__0_n_1 ;\n wire \\cnt_q_reg[0]_i_2__0_n_2 ;\n wire \\cnt_q_reg[0]_i_2__0_n_3 ;\n wire \\cnt_q_reg[0]_i_2__0_n_4 ;\n wire \\cnt_q_reg[0]_i_2__0_n_5 ;\n wire \\cnt_q_reg[0]_i_2__0_n_6 ;\n wire \\cnt_q_reg[0]_i_2__0_n_7 ;\n wire \\cnt_q_reg[1]_i_2__0_n_0 ;\n wire \\cnt_q_reg[1]_i_2__0_n_1 ;\n wire \\cnt_q_reg[1]_i_2__0_n_2 ;\n wire \\cnt_q_reg[1]_i_2__0_n_3 ;\n wire \\cnt_q_reg[1]_i_2__0_n_4 ;\n wire \\cnt_q_reg[1]_i_2__0_n_5 ;\n wire \\cnt_q_reg[1]_i_2__0_n_6 ;\n wire \\cnt_q_reg[1]_i_2__0_n_7 ;\n wire \\cnt_q_reg[4]_i_2__0_n_0 ;\n wire \\cnt_q_reg[4]_i_2__0_n_1 ;\n wire \\cnt_q_reg[4]_i_2__0_n_2 ;\n wire \\cnt_q_reg[4]_i_2__0_n_3 ;\n wire \\cnt_q_reg[4]_i_2__0_n_4 ;\n wire \\cnt_q_reg[4]_i_2__0_n_5 ;\n wire \\cnt_q_reg[4]_i_2__0_n_6 ;\n wire \\cnt_q_reg[4]_i_2__0_n_7 ;\n wire \\cnt_q_reg[5]_i_2__0_n_1 ;\n wire \\cnt_q_reg[5]_i_2__0_n_2 ;\n wire \\cnt_q_reg[5]_i_2__0_n_3 ;\n wire \\cnt_q_reg[5]_i_2__0_n_4 ;\n wire \\cnt_q_reg[5]_i_2__0_n_5 ;\n wire \\cnt_q_reg[5]_i_2__0_n_6 ;\n wire \\cnt_q_reg[5]_i_2__0_n_7 ;\n wire \\cnt_q_reg[8]_i_2__0_n_7 ;\n wire \\cnt_q_reg_n_0_[0] ;\n wire \\cnt_q_reg_n_0_[1] ;\n wire \\cnt_q_reg_n_0_[2] ;\n wire \\cnt_q_reg_n_0_[3] ;\n wire \\cnt_q_reg_n_0_[4] ;\n wire \\cnt_q_reg_n_0_[5] ;\n wire \\cnt_q_reg_n_0_[6] ;\n wire \\cnt_q_reg_n_0_[7] ;\n wire \\cnt_q_reg_n_0_[8] ;\n wire den_lat;\n wire den_lat_reg;\n wire pixel_clock;\n wire q_out23_in;\n wire q_out2_carry_i_1__0_n_0;\n wire q_out2_carry_i_2__0_n_0;\n wire q_out2_carry_i_3__0_n_0;\n wire q_out2_carry_n_2;\n wire q_out2_carry_n_3;\n wire \\tmds[0]_i_1__0_n_0 ;\n wire \\tmds[2]_i_1__0_n_0 ;\n wire [2:0]tmds_enc_10;\n wire [3:3]\\NLW_cnt_q_reg[5]_i_2__0_CO_UNCONNECTED ;\n wire [3:0]\\NLW_cnt_q_reg[8]_i_2__0_CO_UNCONNECTED ;\n wire [3:1]\\NLW_cnt_q_reg[8]_i_2__0_O_UNCONNECTED ;\n wire [3:3]NLW_q_out2_carry_CO_UNCONNECTED;\n wire [3:0]NLW_q_out2_carry_O_UNCONNECTED;\n\n LUT4 #(\n .INIT(16'hFB08)) \n \\cnt_q[0]_i_1__1 \n (.I0(\\cnt_q_reg_n_0_[0] ),\n .I1(\\cnt_q_reg_n_0_[8] ),\n .I2(q_out23_in),\n .I3(\\cnt_q_reg[0]_i_2__0_n_7 ),\n .O(\\cnt_q[0]_i_1__1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_q[0]_i_3__0 \n (.I0(\\cnt_q_reg_n_0_[3] ),\n .O(\\cnt_q[0]_i_3__0_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\cnt_q[0]_i_4__1 \n (.I0(\\cnt_q_reg_n_0_[2] ),\n .O(\\cnt_q[0]_i_4__1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\cnt_q[0]_i_5__0 \n (.I0(\\cnt_q_reg_n_0_[1] ),\n .O(\\cnt_q[0]_i_5__0_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\cnt_q[0]_i_6__0 \n (.I0(\\cnt_q_reg_n_0_[0] ),\n .O(\\cnt_q[0]_i_6__0_n_0 ));\n LUT4 #(\n .INIT(16'hFB08)) \n \\cnt_q[1]_i_1__0 \n (.I0(\\cnt_q_reg[1]_i_2__0_n_7 ),\n .I1(\\cnt_q_reg_n_0_[8] ),\n .I2(q_out23_in),\n .I3(\\cnt_q_reg[0]_i_2__0_n_6 ),\n .O(\\cnt_q[1]_i_1__0_n_0 ));\n LUT2 #(\n .INIT(4'h6)) \n \\cnt_q[1]_i_3 \n (.I0(\\cnt_q_reg_n_0_[3] ),\n .I1(\\cnt_q_reg_n_0_[4] ),\n .O(\\cnt_q[1]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_q[1]_i_4__0 \n (.I0(\\cnt_q_reg_n_0_[3] ),\n .O(\\cnt_q[1]_i_4__0_n_0 ));\n LUT2 #(\n .INIT(4'h6)) \n \\cnt_q[1]_i_5 \n (.I0(\\cnt_q_reg_n_0_[1] ),\n .I1(\\cnt_q_reg_n_0_[2] ),\n .O(\\cnt_q[1]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_q[1]_i_6__0 \n (.I0(\\cnt_q_reg_n_0_[1] ),\n .O(\\cnt_q[1]_i_6__0_n_0 ));\n LUT4 #(\n .INIT(16'hFB08)) \n \\cnt_q[2]_i_1__0 \n (.I0(\\cnt_q_reg[1]_i_2__0_n_6 ),\n .I1(\\cnt_q_reg_n_0_[8] ),\n .I2(q_out23_in),\n .I3(\\cnt_q_reg[0]_i_2__0_n_5 ),\n .O(\\cnt_q[2]_i_1__0_n_0 ));\n LUT4 #(\n .INIT(16'hFB08)) \n \\cnt_q[3]_i_1__0 \n (.I0(\\cnt_q_reg[1]_i_2__0_n_5 ),\n .I1(\\cnt_q_reg_n_0_[8] ),\n .I2(q_out23_in),\n .I3(\\cnt_q_reg[0]_i_2__0_n_4 ),\n .O(\\cnt_q[3]_i_1__0_n_0 ));\n LUT4 #(\n .INIT(16'hFB08)) \n \\cnt_q[4]_i_1__0 \n (.I0(\\cnt_q_reg[1]_i_2__0_n_4 ),\n .I1(\\cnt_q_reg_n_0_[8] ),\n .I2(q_out23_in),\n .I3(\\cnt_q_reg[4]_i_2__0_n_7 ),\n .O(\\cnt_q[4]_i_1__0_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_q[4]_i_3__0 \n (.I0(\\cnt_q_reg_n_0_[7] ),\n .O(\\cnt_q[4]_i_3__0_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_q[4]_i_4__0 \n (.I0(\\cnt_q_reg_n_0_[6] ),\n .O(\\cnt_q[4]_i_4__0_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_q[4]_i_5__0 \n (.I0(\\cnt_q_reg_n_0_[5] ),\n .O(\\cnt_q[4]_i_5__0_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_q[4]_i_6__0 \n (.I0(\\cnt_q_reg_n_0_[4] ),\n .O(\\cnt_q[4]_i_6__0_n_0 ));\n LUT4 #(\n .INIT(16'hFB08)) \n \\cnt_q[5]_i_1__0 \n (.I0(\\cnt_q_reg[5]_i_2__0_n_7 ),\n .I1(\\cnt_q_reg_n_0_[8] ),\n .I2(q_out23_in),\n .I3(\\cnt_q_reg[4]_i_2__0_n_6 ),\n .O(\\cnt_q[5]_i_1__0_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\cnt_q[5]_i_3__0 \n (.I0(\\cnt_q_reg_n_0_[8] ),\n .O(\\cnt_q[5]_i_3__0_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\cnt_q[5]_i_4__0 \n (.I0(\\cnt_q_reg_n_0_[7] ),\n .O(\\cnt_q[5]_i_4__0_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\cnt_q[5]_i_5__0 \n (.I0(\\cnt_q_reg_n_0_[6] ),\n .O(\\cnt_q[5]_i_5__0_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\cnt_q[5]_i_6__0 \n (.I0(\\cnt_q_reg_n_0_[5] ),\n .O(\\cnt_q[5]_i_6__0_n_0 ));\n LUT4 #(\n .INIT(16'hFB08)) \n \\cnt_q[6]_i_1__0 \n (.I0(\\cnt_q_reg[5]_i_2__0_n_6 ),\n .I1(\\cnt_q_reg_n_0_[8] ),\n .I2(q_out23_in),\n .I3(\\cnt_q_reg[4]_i_2__0_n_5 ),\n .O(\\cnt_q[6]_i_1__0_n_0 ));\n LUT4 #(\n .INIT(16'hFB08)) \n \\cnt_q[7]_i_1__0 \n (.I0(\\cnt_q_reg[5]_i_2__0_n_5 ),\n .I1(\\cnt_q_reg_n_0_[8] ),\n .I2(q_out23_in),\n .I3(\\cnt_q_reg[4]_i_2__0_n_4 ),\n .O(\\cnt_q[7]_i_1__0_n_0 ));\n LUT4 #(\n .INIT(16'hFB08)) \n \\cnt_q[8]_i_1__0 \n (.I0(\\cnt_q_reg[5]_i_2__0_n_4 ),\n .I1(\\cnt_q_reg_n_0_[8] ),\n .I2(q_out23_in),\n .I3(\\cnt_q_reg[8]_i_2__0_n_7 ),\n .O(\\cnt_q[8]_i_1__0_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_q[8]_i_3__0 \n (.I0(\\cnt_q_reg_n_0_[8] ),\n .O(\\cnt_q[8]_i_3__0_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_q_reg[0] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\cnt_q[0]_i_1__1_n_0 ),\n .Q(\\cnt_q_reg_n_0_[0] ),\n .R(den_lat_reg));\n CARRY4 \\cnt_q_reg[0]_i_2__0 \n (.CI(1'b0),\n .CO({\\cnt_q_reg[0]_i_2__0_n_0 ,\\cnt_q_reg[0]_i_2__0_n_1 ,\\cnt_q_reg[0]_i_2__0_n_2 ,\\cnt_q_reg[0]_i_2__0_n_3 }),\n .CYINIT(1'b0),\n .DI({\\cnt_q_reg_n_0_[3] ,\\cnt_q_reg_n_0_[2] ,\\cnt_q_reg_n_0_[1] ,1'b0}),\n .O({\\cnt_q_reg[0]_i_2__0_n_4 ,\\cnt_q_reg[0]_i_2__0_n_5 ,\\cnt_q_reg[0]_i_2__0_n_6 ,\\cnt_q_reg[0]_i_2__0_n_7 }),\n .S({\\cnt_q[0]_i_3__0_n_0 ,\\cnt_q[0]_i_4__1_n_0 ,\\cnt_q[0]_i_5__0_n_0 ,\\cnt_q[0]_i_6__0_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_q_reg[1] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\cnt_q[1]_i_1__0_n_0 ),\n .Q(\\cnt_q_reg_n_0_[1] ),\n .R(den_lat_reg));\n CARRY4 \\cnt_q_reg[1]_i_2__0 \n (.CI(1'b0),\n .CO({\\cnt_q_reg[1]_i_2__0_n_0 ,\\cnt_q_reg[1]_i_2__0_n_1 ,\\cnt_q_reg[1]_i_2__0_n_2 ,\\cnt_q_reg[1]_i_2__0_n_3 }),\n .CYINIT(1'b0),\n .DI({\\cnt_q_reg_n_0_[3] ,1'b0,\\cnt_q_reg_n_0_[1] ,1'b0}),\n .O({\\cnt_q_reg[1]_i_2__0_n_4 ,\\cnt_q_reg[1]_i_2__0_n_5 ,\\cnt_q_reg[1]_i_2__0_n_6 ,\\cnt_q_reg[1]_i_2__0_n_7 }),\n .S({\\cnt_q[1]_i_3_n_0 ,\\cnt_q[1]_i_4__0_n_0 ,\\cnt_q[1]_i_5_n_0 ,\\cnt_q[1]_i_6__0_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_q_reg[2] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\cnt_q[2]_i_1__0_n_0 ),\n .Q(\\cnt_q_reg_n_0_[2] ),\n .R(den_lat_reg));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_q_reg[3] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\cnt_q[3]_i_1__0_n_0 ),\n .Q(\\cnt_q_reg_n_0_[3] ),\n .R(den_lat_reg));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_q_reg[4] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\cnt_q[4]_i_1__0_n_0 ),\n .Q(\\cnt_q_reg_n_0_[4] ),\n .R(den_lat_reg));\n CARRY4 \\cnt_q_reg[4]_i_2__0 \n (.CI(\\cnt_q_reg[0]_i_2__0_n_0 ),\n .CO({\\cnt_q_reg[4]_i_2__0_n_0 ,\\cnt_q_reg[4]_i_2__0_n_1 ,\\cnt_q_reg[4]_i_2__0_n_2 ,\\cnt_q_reg[4]_i_2__0_n_3 }),\n .CYINIT(1'b0),\n .DI({\\cnt_q_reg_n_0_[7] ,\\cnt_q_reg_n_0_[6] ,\\cnt_q_reg_n_0_[5] ,\\cnt_q_reg_n_0_[4] }),\n .O({\\cnt_q_reg[4]_i_2__0_n_4 ,\\cnt_q_reg[4]_i_2__0_n_5 ,\\cnt_q_reg[4]_i_2__0_n_6 ,\\cnt_q_reg[4]_i_2__0_n_7 }),\n .S({\\cnt_q[4]_i_3__0_n_0 ,\\cnt_q[4]_i_4__0_n_0 ,\\cnt_q[4]_i_5__0_n_0 ,\\cnt_q[4]_i_6__0_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_q_reg[5] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\cnt_q[5]_i_1__0_n_0 ),\n .Q(\\cnt_q_reg_n_0_[5] ),\n .R(den_lat_reg));\n CARRY4 \\cnt_q_reg[5]_i_2__0 \n (.CI(\\cnt_q_reg[1]_i_2__0_n_0 ),\n .CO({\\NLW_cnt_q_reg[5]_i_2__0_CO_UNCONNECTED [3],\\cnt_q_reg[5]_i_2__0_n_1 ,\\cnt_q_reg[5]_i_2__0_n_2 ,\\cnt_q_reg[5]_i_2__0_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\cnt_q_reg[5]_i_2__0_n_4 ,\\cnt_q_reg[5]_i_2__0_n_5 ,\\cnt_q_reg[5]_i_2__0_n_6 ,\\cnt_q_reg[5]_i_2__0_n_7 }),\n .S({\\cnt_q[5]_i_3__0_n_0 ,\\cnt_q[5]_i_4__0_n_0 ,\\cnt_q[5]_i_5__0_n_0 ,\\cnt_q[5]_i_6__0_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_q_reg[6] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\cnt_q[6]_i_1__0_n_0 ),\n .Q(\\cnt_q_reg_n_0_[6] ),\n .R(den_lat_reg));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_q_reg[7] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\cnt_q[7]_i_1__0_n_0 ),\n .Q(\\cnt_q_reg_n_0_[7] ),\n .R(den_lat_reg));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_q_reg[8] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\cnt_q[8]_i_1__0_n_0 ),\n .Q(\\cnt_q_reg_n_0_[8] ),\n .R(den_lat_reg));\n CARRY4 \\cnt_q_reg[8]_i_2__0 \n (.CI(\\cnt_q_reg[4]_i_2__0_n_0 ),\n .CO(\\NLW_cnt_q_reg[8]_i_2__0_CO_UNCONNECTED [3:0]),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\NLW_cnt_q_reg[8]_i_2__0_O_UNCONNECTED [3:1],\\cnt_q_reg[8]_i_2__0_n_7 }),\n .S({1'b0,1'b0,1'b0,\\cnt_q[8]_i_3__0_n_0 }));\n CARRY4 q_out2_carry\n (.CI(1'b0),\n .CO({NLW_q_out2_carry_CO_UNCONNECTED[3],q_out23_in,q_out2_carry_n_2,q_out2_carry_n_3}),\n .CYINIT(1'b1),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(NLW_q_out2_carry_O_UNCONNECTED[3:0]),\n .S({1'b0,q_out2_carry_i_1__0_n_0,q_out2_carry_i_2__0_n_0,q_out2_carry_i_3__0_n_0}));\n LUT3 #(\n .INIT(8'h01)) \n q_out2_carry_i_1__0\n (.I0(\\cnt_q_reg_n_0_[6] ),\n .I1(\\cnt_q_reg_n_0_[7] ),\n .I2(\\cnt_q_reg_n_0_[8] ),\n .O(q_out2_carry_i_1__0_n_0));\n LUT3 #(\n .INIT(8'h01)) \n q_out2_carry_i_2__0\n (.I0(\\cnt_q_reg_n_0_[3] ),\n .I1(\\cnt_q_reg_n_0_[4] ),\n .I2(\\cnt_q_reg_n_0_[5] ),\n .O(q_out2_carry_i_2__0_n_0));\n LUT3 #(\n .INIT(8'h01)) \n q_out2_carry_i_3__0\n (.I0(\\cnt_q_reg_n_0_[2] ),\n .I1(\\cnt_q_reg_n_0_[1] ),\n .I2(\\cnt_q_reg_n_0_[0] ),\n .O(q_out2_carry_i_3__0_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair2\" *) \n LUT3 #(\n .INIT(8'h40)) \n \\tmds[0]_i_1__0 \n (.I0(q_out23_in),\n .I1(\\cnt_q_reg_n_0_[8] ),\n .I2(den_lat),\n .O(\\tmds[0]_i_1__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair2\" *) \n LUT3 #(\n .INIT(8'h4F)) \n \\tmds[2]_i_1__0 \n (.I0(q_out23_in),\n .I1(\\cnt_q_reg_n_0_[8] ),\n .I2(den_lat),\n .O(\\tmds[2]_i_1__0_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\tmds_reg[0] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\tmds[0]_i_1__0_n_0 ),\n .Q(tmds_enc_10[0]),\n .R(SR));\n FDRE #(\n .INIT(1'b0)) \n \\tmds_reg[2] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\tmds[2]_i_1__0_n_0 ),\n .Q(tmds_enc_10[1]),\n .R(SR));\n FDRE #(\n .INIT(1'b0)) \n \\tmds_reg[8] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(1'b1),\n .Q(tmds_enc_10[2]),\n .R(SR));\nendmodule\n\n(* ORIG_REF_NAME = \"dvi_tx_tmds_enc\" *) \nmodule dvi_tx_tmds_enc_2\n (Q,\n den_lat_reg,\n pixel_clock,\n den_lat,\n SR);\n output [1:0]Q;\n input den_lat_reg;\n input pixel_clock;\n input den_lat;\n input [0:0]SR;\n\n wire [1:0]Q;\n wire [0:0]SR;\n wire \\cnt_q[0]_i_2_n_0 ;\n wire \\cnt_q[0]_i_4_n_0 ;\n wire \\cnt_q[0]_i_5__1_n_0 ;\n wire \\cnt_q[0]_i_6__1_n_0 ;\n wire \\cnt_q[0]_i_7_n_0 ;\n wire \\cnt_q[1]_i_1__1_n_0 ;\n wire \\cnt_q[1]_i_3_n_0 ;\n wire \\cnt_q[1]_i_4__1_n_0 ;\n wire \\cnt_q[1]_i_5_n_0 ;\n wire \\cnt_q[1]_i_6__1_n_0 ;\n wire \\cnt_q[2]_i_1__1_n_0 ;\n wire \\cnt_q[3]_i_1__1_n_0 ;\n wire \\cnt_q[4]_i_1__1_n_0 ;\n wire \\cnt_q[4]_i_3__1_n_0 ;\n wire \\cnt_q[4]_i_4__1_n_0 ;\n wire \\cnt_q[4]_i_5__1_n_0 ;\n wire \\cnt_q[4]_i_6__1_n_0 ;\n wire \\cnt_q[5]_i_1__1_n_0 ;\n wire \\cnt_q[5]_i_3__1_n_0 ;\n wire \\cnt_q[5]_i_4__1_n_0 ;\n wire \\cnt_q[5]_i_5__1_n_0 ;\n wire \\cnt_q[5]_i_6__1_n_0 ;\n wire \\cnt_q[6]_i_1__1_n_0 ;\n wire \\cnt_q[7]_i_1__1_n_0 ;\n wire \\cnt_q[8]_i_1__1_n_0 ;\n wire \\cnt_q[8]_i_3__1_n_0 ;\n wire \\cnt_q_reg[0]_i_3_n_0 ;\n wire \\cnt_q_reg[0]_i_3_n_1 ;\n wire \\cnt_q_reg[0]_i_3_n_2 ;\n wire \\cnt_q_reg[0]_i_3_n_3 ;\n wire \\cnt_q_reg[0]_i_3_n_4 ;\n wire \\cnt_q_reg[0]_i_3_n_5 ;\n wire \\cnt_q_reg[0]_i_3_n_6 ;\n wire \\cnt_q_reg[0]_i_3_n_7 ;\n wire \\cnt_q_reg[1]_i_2__1_n_0 ;\n wire \\cnt_q_reg[1]_i_2__1_n_1 ;\n wire \\cnt_q_reg[1]_i_2__1_n_2 ;\n wire \\cnt_q_reg[1]_i_2__1_n_3 ;\n wire \\cnt_q_reg[1]_i_2__1_n_4 ;\n wire \\cnt_q_reg[1]_i_2__1_n_5 ;\n wire \\cnt_q_reg[1]_i_2__1_n_6 ;\n wire \\cnt_q_reg[1]_i_2__1_n_7 ;\n wire \\cnt_q_reg[4]_i_2__1_n_0 ;\n wire \\cnt_q_reg[4]_i_2__1_n_1 ;\n wire \\cnt_q_reg[4]_i_2__1_n_2 ;\n wire \\cnt_q_reg[4]_i_2__1_n_3 ;\n wire \\cnt_q_reg[4]_i_2__1_n_4 ;\n wire \\cnt_q_reg[4]_i_2__1_n_5 ;\n wire \\cnt_q_reg[4]_i_2__1_n_6 ;\n wire \\cnt_q_reg[4]_i_2__1_n_7 ;\n wire \\cnt_q_reg[5]_i_2__1_n_1 ;\n wire \\cnt_q_reg[5]_i_2__1_n_2 ;\n wire \\cnt_q_reg[5]_i_2__1_n_3 ;\n wire \\cnt_q_reg[5]_i_2__1_n_4 ;\n wire \\cnt_q_reg[5]_i_2__1_n_5 ;\n wire \\cnt_q_reg[5]_i_2__1_n_6 ;\n wire \\cnt_q_reg[5]_i_2__1_n_7 ;\n wire \\cnt_q_reg[8]_i_2__1_n_7 ;\n wire \\cnt_q_reg_n_0_[0] ;\n wire \\cnt_q_reg_n_0_[1] ;\n wire \\cnt_q_reg_n_0_[2] ;\n wire \\cnt_q_reg_n_0_[3] ;\n wire \\cnt_q_reg_n_0_[4] ;\n wire \\cnt_q_reg_n_0_[5] ;\n wire \\cnt_q_reg_n_0_[6] ;\n wire \\cnt_q_reg_n_0_[7] ;\n wire \\cnt_q_reg_n_0_[8] ;\n wire den_lat;\n wire den_lat_reg;\n wire pixel_clock;\n wire q_out23_in;\n wire q_out2_carry_i_1__1_n_0;\n wire q_out2_carry_i_2__1_n_0;\n wire q_out2_carry_i_3__1_n_0;\n wire q_out2_carry_n_2;\n wire q_out2_carry_n_3;\n wire \\tmds[0]_i_1__1_n_0 ;\n wire \\tmds[2]_i_1__1_n_0 ;\n wire [3:3]\\NLW_cnt_q_reg[5]_i_2__1_CO_UNCONNECTED ;\n wire [3:0]\\NLW_cnt_q_reg[8]_i_2__1_CO_UNCONNECTED ;\n wire [3:1]\\NLW_cnt_q_reg[8]_i_2__1_O_UNCONNECTED ;\n wire [3:3]NLW_q_out2_carry_CO_UNCONNECTED;\n wire [3:0]NLW_q_out2_carry_O_UNCONNECTED;\n\n LUT4 #(\n .INIT(16'hFB08)) \n \\cnt_q[0]_i_2 \n (.I0(\\cnt_q_reg_n_0_[0] ),\n .I1(\\cnt_q_reg_n_0_[8] ),\n .I2(q_out23_in),\n .I3(\\cnt_q_reg[0]_i_3_n_7 ),\n .O(\\cnt_q[0]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_q[0]_i_4 \n (.I0(\\cnt_q_reg_n_0_[3] ),\n .O(\\cnt_q[0]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\cnt_q[0]_i_5__1 \n (.I0(\\cnt_q_reg_n_0_[2] ),\n .O(\\cnt_q[0]_i_5__1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\cnt_q[0]_i_6__1 \n (.I0(\\cnt_q_reg_n_0_[1] ),\n .O(\\cnt_q[0]_i_6__1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\cnt_q[0]_i_7 \n (.I0(\\cnt_q_reg_n_0_[0] ),\n .O(\\cnt_q[0]_i_7_n_0 ));\n LUT4 #(\n .INIT(16'hFB08)) \n \\cnt_q[1]_i_1__1 \n (.I0(\\cnt_q_reg[1]_i_2__1_n_7 ),\n .I1(\\cnt_q_reg_n_0_[8] ),\n .I2(q_out23_in),\n .I3(\\cnt_q_reg[0]_i_3_n_6 ),\n .O(\\cnt_q[1]_i_1__1_n_0 ));\n LUT2 #(\n .INIT(4'h6)) \n \\cnt_q[1]_i_3 \n (.I0(\\cnt_q_reg_n_0_[3] ),\n .I1(\\cnt_q_reg_n_0_[4] ),\n .O(\\cnt_q[1]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_q[1]_i_4__1 \n (.I0(\\cnt_q_reg_n_0_[3] ),\n .O(\\cnt_q[1]_i_4__1_n_0 ));\n LUT2 #(\n .INIT(4'h6)) \n \\cnt_q[1]_i_5 \n (.I0(\\cnt_q_reg_n_0_[1] ),\n .I1(\\cnt_q_reg_n_0_[2] ),\n .O(\\cnt_q[1]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_q[1]_i_6__1 \n (.I0(\\cnt_q_reg_n_0_[1] ),\n .O(\\cnt_q[1]_i_6__1_n_0 ));\n LUT4 #(\n .INIT(16'hFB08)) \n \\cnt_q[2]_i_1__1 \n (.I0(\\cnt_q_reg[1]_i_2__1_n_6 ),\n .I1(\\cnt_q_reg_n_0_[8] ),\n .I2(q_out23_in),\n .I3(\\cnt_q_reg[0]_i_3_n_5 ),\n .O(\\cnt_q[2]_i_1__1_n_0 ));\n LUT4 #(\n .INIT(16'hFB08)) \n \\cnt_q[3]_i_1__1 \n (.I0(\\cnt_q_reg[1]_i_2__1_n_5 ),\n .I1(\\cnt_q_reg_n_0_[8] ),\n .I2(q_out23_in),\n .I3(\\cnt_q_reg[0]_i_3_n_4 ),\n .O(\\cnt_q[3]_i_1__1_n_0 ));\n LUT4 #(\n .INIT(16'hFB08)) \n \\cnt_q[4]_i_1__1 \n (.I0(\\cnt_q_reg[1]_i_2__1_n_4 ),\n .I1(\\cnt_q_reg_n_0_[8] ),\n .I2(q_out23_in),\n .I3(\\cnt_q_reg[4]_i_2__1_n_7 ),\n .O(\\cnt_q[4]_i_1__1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_q[4]_i_3__1 \n (.I0(\\cnt_q_reg_n_0_[7] ),\n .O(\\cnt_q[4]_i_3__1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_q[4]_i_4__1 \n (.I0(\\cnt_q_reg_n_0_[6] ),\n .O(\\cnt_q[4]_i_4__1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_q[4]_i_5__1 \n (.I0(\\cnt_q_reg_n_0_[5] ),\n .O(\\cnt_q[4]_i_5__1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_q[4]_i_6__1 \n (.I0(\\cnt_q_reg_n_0_[4] ),\n .O(\\cnt_q[4]_i_6__1_n_0 ));\n LUT4 #(\n .INIT(16'hFB08)) \n \\cnt_q[5]_i_1__1 \n (.I0(\\cnt_q_reg[5]_i_2__1_n_7 ),\n .I1(\\cnt_q_reg_n_0_[8] ),\n .I2(q_out23_in),\n .I3(\\cnt_q_reg[4]_i_2__1_n_6 ),\n .O(\\cnt_q[5]_i_1__1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\cnt_q[5]_i_3__1 \n (.I0(\\cnt_q_reg_n_0_[8] ),\n .O(\\cnt_q[5]_i_3__1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\cnt_q[5]_i_4__1 \n (.I0(\\cnt_q_reg_n_0_[7] ),\n .O(\\cnt_q[5]_i_4__1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\cnt_q[5]_i_5__1 \n (.I0(\\cnt_q_reg_n_0_[6] ),\n .O(\\cnt_q[5]_i_5__1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\cnt_q[5]_i_6__1 \n (.I0(\\cnt_q_reg_n_0_[5] ),\n .O(\\cnt_q[5]_i_6__1_n_0 ));\n LUT4 #(\n .INIT(16'hFB08)) \n \\cnt_q[6]_i_1__1 \n (.I0(\\cnt_q_reg[5]_i_2__1_n_6 ),\n .I1(\\cnt_q_reg_n_0_[8] ),\n .I2(q_out23_in),\n .I3(\\cnt_q_reg[4]_i_2__1_n_5 ),\n .O(\\cnt_q[6]_i_1__1_n_0 ));\n LUT4 #(\n .INIT(16'hFB08)) \n \\cnt_q[7]_i_1__1 \n (.I0(\\cnt_q_reg[5]_i_2__1_n_5 ),\n .I1(\\cnt_q_reg_n_0_[8] ),\n .I2(q_out23_in),\n .I3(\\cnt_q_reg[4]_i_2__1_n_4 ),\n .O(\\cnt_q[7]_i_1__1_n_0 ));\n LUT4 #(\n .INIT(16'hFB08)) \n \\cnt_q[8]_i_1__1 \n (.I0(\\cnt_q_reg[5]_i_2__1_n_4 ),\n .I1(\\cnt_q_reg_n_0_[8] ),\n .I2(q_out23_in),\n .I3(\\cnt_q_reg[8]_i_2__1_n_7 ),\n .O(\\cnt_q[8]_i_1__1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_q[8]_i_3__1 \n (.I0(\\cnt_q_reg_n_0_[8] ),\n .O(\\cnt_q[8]_i_3__1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_q_reg[0] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\cnt_q[0]_i_2_n_0 ),\n .Q(\\cnt_q_reg_n_0_[0] ),\n .R(den_lat_reg));\n CARRY4 \\cnt_q_reg[0]_i_3 \n (.CI(1'b0),\n .CO({\\cnt_q_reg[0]_i_3_n_0 ,\\cnt_q_reg[0]_i_3_n_1 ,\\cnt_q_reg[0]_i_3_n_2 ,\\cnt_q_reg[0]_i_3_n_3 }),\n .CYINIT(1'b0),\n .DI({\\cnt_q_reg_n_0_[3] ,\\cnt_q_reg_n_0_[2] ,\\cnt_q_reg_n_0_[1] ,1'b0}),\n .O({\\cnt_q_reg[0]_i_3_n_4 ,\\cnt_q_reg[0]_i_3_n_5 ,\\cnt_q_reg[0]_i_3_n_6 ,\\cnt_q_reg[0]_i_3_n_7 }),\n .S({\\cnt_q[0]_i_4_n_0 ,\\cnt_q[0]_i_5__1_n_0 ,\\cnt_q[0]_i_6__1_n_0 ,\\cnt_q[0]_i_7_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_q_reg[1] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\cnt_q[1]_i_1__1_n_0 ),\n .Q(\\cnt_q_reg_n_0_[1] ),\n .R(den_lat_reg));\n CARRY4 \\cnt_q_reg[1]_i_2__1 \n (.CI(1'b0),\n .CO({\\cnt_q_reg[1]_i_2__1_n_0 ,\\cnt_q_reg[1]_i_2__1_n_1 ,\\cnt_q_reg[1]_i_2__1_n_2 ,\\cnt_q_reg[1]_i_2__1_n_3 }),\n .CYINIT(1'b0),\n .DI({\\cnt_q_reg_n_0_[3] ,1'b0,\\cnt_q_reg_n_0_[1] ,1'b0}),\n .O({\\cnt_q_reg[1]_i_2__1_n_4 ,\\cnt_q_reg[1]_i_2__1_n_5 ,\\cnt_q_reg[1]_i_2__1_n_6 ,\\cnt_q_reg[1]_i_2__1_n_7 }),\n .S({\\cnt_q[1]_i_3_n_0 ,\\cnt_q[1]_i_4__1_n_0 ,\\cnt_q[1]_i_5_n_0 ,\\cnt_q[1]_i_6__1_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_q_reg[2] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\cnt_q[2]_i_1__1_n_0 ),\n .Q(\\cnt_q_reg_n_0_[2] ),\n .R(den_lat_reg));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_q_reg[3] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\cnt_q[3]_i_1__1_n_0 ),\n .Q(\\cnt_q_reg_n_0_[3] ),\n .R(den_lat_reg));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_q_reg[4] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\cnt_q[4]_i_1__1_n_0 ),\n .Q(\\cnt_q_reg_n_0_[4] ),\n .R(den_lat_reg));\n CARRY4 \\cnt_q_reg[4]_i_2__1 \n (.CI(\\cnt_q_reg[0]_i_3_n_0 ),\n .CO({\\cnt_q_reg[4]_i_2__1_n_0 ,\\cnt_q_reg[4]_i_2__1_n_1 ,\\cnt_q_reg[4]_i_2__1_n_2 ,\\cnt_q_reg[4]_i_2__1_n_3 }),\n .CYINIT(1'b0),\n .DI({\\cnt_q_reg_n_0_[7] ,\\cnt_q_reg_n_0_[6] ,\\cnt_q_reg_n_0_[5] ,\\cnt_q_reg_n_0_[4] }),\n .O({\\cnt_q_reg[4]_i_2__1_n_4 ,\\cnt_q_reg[4]_i_2__1_n_5 ,\\cnt_q_reg[4]_i_2__1_n_6 ,\\cnt_q_reg[4]_i_2__1_n_7 }),\n .S({\\cnt_q[4]_i_3__1_n_0 ,\\cnt_q[4]_i_4__1_n_0 ,\\cnt_q[4]_i_5__1_n_0 ,\\cnt_q[4]_i_6__1_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_q_reg[5] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\cnt_q[5]_i_1__1_n_0 ),\n .Q(\\cnt_q_reg_n_0_[5] ),\n .R(den_lat_reg));\n CARRY4 \\cnt_q_reg[5]_i_2__1 \n (.CI(\\cnt_q_reg[1]_i_2__1_n_0 ),\n .CO({\\NLW_cnt_q_reg[5]_i_2__1_CO_UNCONNECTED [3],\\cnt_q_reg[5]_i_2__1_n_1 ,\\cnt_q_reg[5]_i_2__1_n_2 ,\\cnt_q_reg[5]_i_2__1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\cnt_q_reg[5]_i_2__1_n_4 ,\\cnt_q_reg[5]_i_2__1_n_5 ,\\cnt_q_reg[5]_i_2__1_n_6 ,\\cnt_q_reg[5]_i_2__1_n_7 }),\n .S({\\cnt_q[5]_i_3__1_n_0 ,\\cnt_q[5]_i_4__1_n_0 ,\\cnt_q[5]_i_5__1_n_0 ,\\cnt_q[5]_i_6__1_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_q_reg[6] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\cnt_q[6]_i_1__1_n_0 ),\n .Q(\\cnt_q_reg_n_0_[6] ),\n .R(den_lat_reg));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_q_reg[7] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\cnt_q[7]_i_1__1_n_0 ),\n .Q(\\cnt_q_reg_n_0_[7] ),\n .R(den_lat_reg));\n FDRE #(\n .INIT(1'b0)) \n \\cnt_q_reg[8] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\cnt_q[8]_i_1__1_n_0 ),\n .Q(\\cnt_q_reg_n_0_[8] ),\n .R(den_lat_reg));\n CARRY4 \\cnt_q_reg[8]_i_2__1 \n (.CI(\\cnt_q_reg[4]_i_2__1_n_0 ),\n .CO(\\NLW_cnt_q_reg[8]_i_2__1_CO_UNCONNECTED [3:0]),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\NLW_cnt_q_reg[8]_i_2__1_O_UNCONNECTED [3:1],\\cnt_q_reg[8]_i_2__1_n_7 }),\n .S({1'b0,1'b0,1'b0,\\cnt_q[8]_i_3__1_n_0 }));\n CARRY4 q_out2_carry\n (.CI(1'b0),\n .CO({NLW_q_out2_carry_CO_UNCONNECTED[3],q_out23_in,q_out2_carry_n_2,q_out2_carry_n_3}),\n .CYINIT(1'b1),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(NLW_q_out2_carry_O_UNCONNECTED[3:0]),\n .S({1'b0,q_out2_carry_i_1__1_n_0,q_out2_carry_i_2__1_n_0,q_out2_carry_i_3__1_n_0}));\n LUT3 #(\n .INIT(8'h01)) \n q_out2_carry_i_1__1\n (.I0(\\cnt_q_reg_n_0_[6] ),\n .I1(\\cnt_q_reg_n_0_[7] ),\n .I2(\\cnt_q_reg_n_0_[8] ),\n .O(q_out2_carry_i_1__1_n_0));\n LUT3 #(\n .INIT(8'h01)) \n q_out2_carry_i_2__1\n (.I0(\\cnt_q_reg_n_0_[3] ),\n .I1(\\cnt_q_reg_n_0_[4] ),\n .I2(\\cnt_q_reg_n_0_[5] ),\n .O(q_out2_carry_i_2__1_n_0));\n LUT3 #(\n .INIT(8'h01)) \n q_out2_carry_i_3__1\n (.I0(\\cnt_q_reg_n_0_[2] ),\n .I1(\\cnt_q_reg_n_0_[1] ),\n .I2(\\cnt_q_reg_n_0_[0] ),\n .O(q_out2_carry_i_3__1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair3\" *) \n LUT3 #(\n .INIT(8'h40)) \n \\tmds[0]_i_1__1 \n (.I0(q_out23_in),\n .I1(\\cnt_q_reg_n_0_[8] ),\n .I2(den_lat),\n .O(\\tmds[0]_i_1__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair3\" *) \n LUT3 #(\n .INIT(8'h4F)) \n \\tmds[2]_i_1__1 \n (.I0(q_out23_in),\n .I1(\\cnt_q_reg_n_0_[8] ),\n .I2(den_lat),\n .O(\\tmds[2]_i_1__1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\tmds_reg[0] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\tmds[0]_i_1__1_n_0 ),\n .Q(Q[0]),\n .R(SR));\n FDRE #(\n .INIT(1'b0)) \n \\tmds_reg[2] \n (.C(pixel_clock),\n .CE(1'b1),\n .D(\\tmds[2]_i_1__1_n_0 ),\n .Q(Q[1]),\n .R(SR));\nendmodule\n\nmodule dvi_tx_tmds_phy\n (RST,\n hdmi_d0,\n dvi_bit_clock,\n pixel_clock,\n Q,\n SR);\n output RST;\n output [1:0]hdmi_d0;\n input dvi_bit_clock;\n input pixel_clock;\n input [3:0]Q;\n input [0:0]SR;\n\n wire [3:0]Q;\n wire RST;\n wire SHIFTIN1;\n wire SHIFTIN2;\n wire [0:0]SR;\n wire data_se;\n wire dvi_bit_clock;\n wire [1:0]hdmi_d0;\n wire pixel_clock;\n wire NLW_master_oserdes_OFB_UNCONNECTED;\n wire NLW_master_oserdes_SHIFTOUT1_UNCONNECTED;\n wire NLW_master_oserdes_SHIFTOUT2_UNCONNECTED;\n wire NLW_master_oserdes_TBYTEOUT_UNCONNECTED;\n wire NLW_master_oserdes_TFB_UNCONNECTED;\n wire NLW_master_oserdes_TQ_UNCONNECTED;\n wire NLW_slave_oserdes_OFB_UNCONNECTED;\n wire NLW_slave_oserdes_OQ_UNCONNECTED;\n wire NLW_slave_oserdes_TBYTEOUT_UNCONNECTED;\n wire NLW_slave_oserdes_TFB_UNCONNECTED;\n wire NLW_slave_oserdes_TQ_UNCONNECTED;\n\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(10),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b0),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n master_oserdes\n (.CLK(dvi_bit_clock),\n .CLKDIV(pixel_clock),\n .D1(Q[0]),\n .D2(Q[0]),\n .D3(Q[1]),\n .D4(Q[0]),\n .D5(Q[1]),\n .D6(Q[0]),\n .D7(Q[1]),\n .D8(Q[0]),\n .OCE(1'b1),\n .OFB(NLW_master_oserdes_OFB_UNCONNECTED),\n .OQ(data_se),\n .RST(RST),\n .SHIFTIN1(SHIFTIN1),\n .SHIFTIN2(SHIFTIN2),\n .SHIFTOUT1(NLW_master_oserdes_SHIFTOUT1_UNCONNECTED),\n .SHIFTOUT2(NLW_master_oserdes_SHIFTOUT2_UNCONNECTED),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(1'b0),\n .TBYTEOUT(NLW_master_oserdes_TBYTEOUT_UNCONNECTED),\n .TCE(1'b1),\n .TFB(NLW_master_oserdes_TFB_UNCONNECTED),\n .TQ(NLW_master_oserdes_TQ_UNCONNECTED));\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* XILINX_LEGACY_PRIM = \"OBUFDS\" *) \n (* box_type = \"PRIMITIVE\" *) \n OBUFDS #(\n .IOSTANDARD(\"DEFAULT\")) \n outbuf\n (.I(data_se),\n .O(hdmi_d0[1]),\n .OB(hdmi_d0[0]));\n FDRE #(\n .INIT(1'b0)) \n reset_lat_reg\n (.C(pixel_clock),\n .CE(1'b1),\n .D(SR),\n .Q(RST),\n .R(1'b0));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(10),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"SLAVE\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b0),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n slave_oserdes\n (.CLK(dvi_bit_clock),\n .CLKDIV(pixel_clock),\n .D1(1'b0),\n .D2(1'b0),\n .D3(Q[2]),\n .D4(Q[3]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(NLW_slave_oserdes_OFB_UNCONNECTED),\n .OQ(NLW_slave_oserdes_OQ_UNCONNECTED),\n .RST(RST),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(SHIFTIN1),\n .SHIFTOUT2(SHIFTIN2),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(1'b0),\n .TBYTEOUT(NLW_slave_oserdes_TBYTEOUT_UNCONNECTED),\n .TCE(1'b1),\n .TFB(NLW_slave_oserdes_TFB_UNCONNECTED),\n .TQ(NLW_slave_oserdes_TQ_UNCONNECTED));\nendmodule\n\n(* ORIG_REF_NAME = \"dvi_tx_tmds_phy\" *) \nmodule dvi_tx_tmds_phy_1\n (hdmi_d1,\n dvi_bit_clock,\n pixel_clock,\n tmds_enc_10,\n RST);\n output [1:0]hdmi_d1;\n input dvi_bit_clock;\n input pixel_clock;\n input [2:0]tmds_enc_10;\n input RST;\n\n wire RST;\n wire SHIFTIN1;\n wire SHIFTIN2;\n wire data_se;\n wire dvi_bit_clock;\n wire [1:0]hdmi_d1;\n wire pixel_clock;\n wire [2:0]tmds_enc_10;\n wire NLW_master_oserdes_OFB_UNCONNECTED;\n wire NLW_master_oserdes_SHIFTOUT1_UNCONNECTED;\n wire NLW_master_oserdes_SHIFTOUT2_UNCONNECTED;\n wire NLW_master_oserdes_TBYTEOUT_UNCONNECTED;\n wire NLW_master_oserdes_TFB_UNCONNECTED;\n wire NLW_master_oserdes_TQ_UNCONNECTED;\n wire NLW_slave_oserdes_OFB_UNCONNECTED;\n wire NLW_slave_oserdes_OQ_UNCONNECTED;\n wire NLW_slave_oserdes_TBYTEOUT_UNCONNECTED;\n wire NLW_slave_oserdes_TFB_UNCONNECTED;\n wire NLW_slave_oserdes_TQ_UNCONNECTED;\n\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(10),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b0),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n master_oserdes\n (.CLK(dvi_bit_clock),\n .CLKDIV(pixel_clock),\n .D1(tmds_enc_10[0]),\n .D2(tmds_enc_10[0]),\n .D3(tmds_enc_10[1]),\n .D4(tmds_enc_10[0]),\n .D5(tmds_enc_10[1]),\n .D6(tmds_enc_10[0]),\n .D7(tmds_enc_10[1]),\n .D8(tmds_enc_10[0]),\n .OCE(1'b1),\n .OFB(NLW_master_oserdes_OFB_UNCONNECTED),\n .OQ(data_se),\n .RST(RST),\n .SHIFTIN1(SHIFTIN1),\n .SHIFTIN2(SHIFTIN2),\n .SHIFTOUT1(NLW_master_oserdes_SHIFTOUT1_UNCONNECTED),\n .SHIFTOUT2(NLW_master_oserdes_SHIFTOUT2_UNCONNECTED),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(1'b0),\n .TBYTEOUT(NLW_master_oserdes_TBYTEOUT_UNCONNECTED),\n .TCE(1'b1),\n .TFB(NLW_master_oserdes_TFB_UNCONNECTED),\n .TQ(NLW_master_oserdes_TQ_UNCONNECTED));\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* XILINX_LEGACY_PRIM = \"OBUFDS\" *) \n (* box_type = \"PRIMITIVE\" *) \n OBUFDS #(\n .IOSTANDARD(\"DEFAULT\")) \n outbuf\n (.I(data_se),\n .O(hdmi_d1[1]),\n .OB(hdmi_d1[0]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(10),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"SLAVE\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b0),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n slave_oserdes\n (.CLK(dvi_bit_clock),\n .CLKDIV(pixel_clock),\n .D1(1'b0),\n .D2(1'b0),\n .D3(tmds_enc_10[2]),\n .D4(tmds_enc_10[1]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(NLW_slave_oserdes_OFB_UNCONNECTED),\n .OQ(NLW_slave_oserdes_OQ_UNCONNECTED),\n .RST(RST),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(SHIFTIN1),\n .SHIFTOUT2(SHIFTIN2),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(1'b0),\n .TBYTEOUT(NLW_slave_oserdes_TBYTEOUT_UNCONNECTED),\n .TCE(1'b1),\n .TFB(NLW_slave_oserdes_TFB_UNCONNECTED),\n .TQ(NLW_slave_oserdes_TQ_UNCONNECTED));\nendmodule\n\n(* ORIG_REF_NAME = \"dvi_tx_tmds_phy\" *) \nmodule dvi_tx_tmds_phy_3\n (hdmi_d2,\n dvi_bit_clock,\n pixel_clock,\n Q,\n RST,\n tmds_enc_10);\n output [1:0]hdmi_d2;\n input dvi_bit_clock;\n input pixel_clock;\n input [1:0]Q;\n input RST;\n input [0:0]tmds_enc_10;\n\n wire [1:0]Q;\n wire RST;\n wire SHIFTIN1;\n wire SHIFTIN2;\n wire data_se;\n wire dvi_bit_clock;\n wire [1:0]hdmi_d2;\n wire pixel_clock;\n wire [0:0]tmds_enc_10;\n wire NLW_master_oserdes_OFB_UNCONNECTED;\n wire NLW_master_oserdes_SHIFTOUT1_UNCONNECTED;\n wire NLW_master_oserdes_SHIFTOUT2_UNCONNECTED;\n wire NLW_master_oserdes_TBYTEOUT_UNCONNECTED;\n wire NLW_master_oserdes_TFB_UNCONNECTED;\n wire NLW_master_oserdes_TQ_UNCONNECTED;\n wire NLW_slave_oserdes_OFB_UNCONNECTED;\n wire NLW_slave_oserdes_OQ_UNCONNECTED;\n wire NLW_slave_oserdes_TBYTEOUT_UNCONNECTED;\n wire NLW_slave_oserdes_TFB_UNCONNECTED;\n wire NLW_slave_oserdes_TQ_UNCONNECTED;\n\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(10),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b0),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n master_oserdes\n (.CLK(dvi_bit_clock),\n .CLKDIV(pixel_clock),\n .D1(Q[0]),\n .D2(Q[0]),\n .D3(Q[1]),\n .D4(Q[0]),\n .D5(Q[1]),\n .D6(Q[0]),\n .D7(Q[1]),\n .D8(Q[0]),\n .OCE(1'b1),\n .OFB(NLW_master_oserdes_OFB_UNCONNECTED),\n .OQ(data_se),\n .RST(RST),\n .SHIFTIN1(SHIFTIN1),\n .SHIFTIN2(SHIFTIN2),\n .SHIFTOUT1(NLW_master_oserdes_SHIFTOUT1_UNCONNECTED),\n .SHIFTOUT2(NLW_master_oserdes_SHIFTOUT2_UNCONNECTED),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(1'b0),\n .TBYTEOUT(NLW_master_oserdes_TBYTEOUT_UNCONNECTED),\n .TCE(1'b1),\n .TFB(NLW_master_oserdes_TFB_UNCONNECTED),\n .TQ(NLW_master_oserdes_TQ_UNCONNECTED));\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* XILINX_LEGACY_PRIM = \"OBUFDS\" *) \n (* box_type = \"PRIMITIVE\" *) \n OBUFDS #(\n .IOSTANDARD(\"DEFAULT\")) \n outbuf\n (.I(data_se),\n .O(hdmi_d2[1]),\n .OB(hdmi_d2[0]));\n (* box_type = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(10),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"SLAVE\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b0),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n slave_oserdes\n (.CLK(dvi_bit_clock),\n .CLKDIV(pixel_clock),\n .D1(1'b0),\n .D2(1'b0),\n .D3(tmds_enc_10),\n .D4(Q[1]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(NLW_slave_oserdes_OFB_UNCONNECTED),\n .OQ(NLW_slave_oserdes_OQ_UNCONNECTED),\n .RST(RST),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(SHIFTIN1),\n .SHIFTOUT2(SHIFTIN2),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(1'b0),\n .TBYTEOUT(NLW_slave_oserdes_TBYTEOUT_UNCONNECTED),\n .TCE(1'b1),\n .TFB(NLW_slave_oserdes_TFB_UNCONNECTED),\n .TQ(NLW_slave_oserdes_TQ_UNCONNECTED));\nendmodule\n\n(* CHECK_LICENSE_TYPE = \"fb_input_fifo,fifo_generator_v13_1_2,{}\" *) (* downgradeipidentifiedwarnings = \"yes\" *) (* x_core_info = \"fifo_generator_v13_1_2,Vivado 2016.3\" *) \nmodule fb_input_fifo\n (rst,\n wr_clk,\n rd_clk,\n din,\n wr_en,\n rd_en,\n dout,\n full,\n empty,\n prog_empty);\n input rst;\n (* x_interface_info = \"xilinx.com:signal:clock:1.0 write_clk CLK\" *) input wr_clk;\n (* x_interface_info = \"xilinx.com:signal:clock:1.0 read_clk CLK\" *) input rd_clk;\n (* x_interface_info = \"xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA\" *) input [63:0]din;\n (* x_interface_info = \"xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN\" *) input wr_en;\n (* x_interface_info = \"xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN\" *) input rd_en;\n (* x_interface_info = \"xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA\" *) output [255:0]dout;\n (* x_interface_info = \"xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL\" *) output full;\n (* x_interface_info = \"xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY\" *) output empty;\n output prog_empty;\n\n wire [63:0]din;\n wire [255:0]dout;\n wire empty;\n wire full;\n wire prog_empty;\n wire rd_clk;\n wire rd_en;\n wire rst;\n wire wr_clk;\n wire wr_en;\n wire NLW_U0_almost_empty_UNCONNECTED;\n wire NLW_U0_almost_full_UNCONNECTED;\n wire NLW_U0_axi_ar_dbiterr_UNCONNECTED;\n wire NLW_U0_axi_ar_overflow_UNCONNECTED;\n wire NLW_U0_axi_ar_prog_empty_UNCONNECTED;\n wire NLW_U0_axi_ar_prog_full_UNCONNECTED;\n wire NLW_U0_axi_ar_sbiterr_UNCONNECTED;\n wire NLW_U0_axi_ar_underflow_UNCONNECTED;\n wire NLW_U0_axi_aw_dbiterr_UNCONNECTED;\n wire NLW_U0_axi_aw_overflow_UNCONNECTED;\n wire NLW_U0_axi_aw_prog_empty_UNCONNECTED;\n wire NLW_U0_axi_aw_prog_full_UNCONNECTED;\n wire NLW_U0_axi_aw_sbiterr_UNCONNECTED;\n wire NLW_U0_axi_aw_underflow_UNCONNECTED;\n wire NLW_U0_axi_b_dbiterr_UNCONNECTED;\n wire NLW_U0_axi_b_overflow_UNCONNECTED;\n wire NLW_U0_axi_b_prog_empty_UNCONNECTED;\n wire NLW_U0_axi_b_prog_full_UNCONNECTED;\n wire NLW_U0_axi_b_sbiterr_UNCONNECTED;\n wire NLW_U0_axi_b_underflow_UNCONNECTED;\n wire NLW_U0_axi_r_dbiterr_UNCONNECTED;\n wire NLW_U0_axi_r_overflow_UNCONNECTED;\n wire NLW_U0_axi_r_prog_empty_UNCONNECTED;\n wire NLW_U0_axi_r_prog_full_UNCONNECTED;\n wire NLW_U0_axi_r_sbiterr_UNCONNECTED;\n wire NLW_U0_axi_r_underflow_UNCONNECTED;\n wire NLW_U0_axi_w_dbiterr_UNCONNECTED;\n wire NLW_U0_axi_w_overflow_UNCONNECTED;\n wire NLW_U0_axi_w_prog_empty_UNCONNECTED;\n wire NLW_U0_axi_w_prog_full_UNCONNECTED;\n wire NLW_U0_axi_w_sbiterr_UNCONNECTED;\n wire NLW_U0_axi_w_underflow_UNCONNECTED;\n wire NLW_U0_axis_dbiterr_UNCONNECTED;\n wire NLW_U0_axis_overflow_UNCONNECTED;\n wire NLW_U0_axis_prog_empty_UNCONNECTED;\n wire NLW_U0_axis_prog_full_UNCONNECTED;\n wire NLW_U0_axis_sbiterr_UNCONNECTED;\n wire NLW_U0_axis_underflow_UNCONNECTED;\n wire NLW_U0_dbiterr_UNCONNECTED;\n wire NLW_U0_m_axi_arvalid_UNCONNECTED;\n wire NLW_U0_m_axi_awvalid_UNCONNECTED;\n wire NLW_U0_m_axi_bready_UNCONNECTED;\n wire NLW_U0_m_axi_rready_UNCONNECTED;\n wire NLW_U0_m_axi_wlast_UNCONNECTED;\n wire NLW_U0_m_axi_wvalid_UNCONNECTED;\n wire NLW_U0_m_axis_tlast_UNCONNECTED;\n wire NLW_U0_m_axis_tvalid_UNCONNECTED;\n wire NLW_U0_overflow_UNCONNECTED;\n wire NLW_U0_prog_full_UNCONNECTED;\n wire NLW_U0_rd_rst_busy_UNCONNECTED;\n wire NLW_U0_s_axi_arready_UNCONNECTED;\n wire NLW_U0_s_axi_awready_UNCONNECTED;\n wire NLW_U0_s_axi_bvalid_UNCONNECTED;\n wire NLW_U0_s_axi_rlast_UNCONNECTED;\n wire NLW_U0_s_axi_rvalid_UNCONNECTED;\n wire NLW_U0_s_axi_wready_UNCONNECTED;\n wire NLW_U0_s_axis_tready_UNCONNECTED;\n wire NLW_U0_sbiterr_UNCONNECTED;\n wire NLW_U0_underflow_UNCONNECTED;\n wire NLW_U0_valid_UNCONNECTED;\n wire NLW_U0_wr_ack_UNCONNECTED;\n wire NLW_U0_wr_rst_busy_UNCONNECTED;\n wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED;\n wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED;\n wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED;\n wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED;\n wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED;\n wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED;\n wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED;\n wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED;\n wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED;\n wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED;\n wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED;\n wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED;\n wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED;\n wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED;\n wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED;\n wire [10:0]NLW_U0_axis_data_count_UNCONNECTED;\n wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED;\n wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED;\n wire [10:0]NLW_U0_data_count_UNCONNECTED;\n wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED;\n wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED;\n wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED;\n wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED;\n wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED;\n wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED;\n wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED;\n wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED;\n wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED;\n wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED;\n wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED;\n wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED;\n wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED;\n wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED;\n wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED;\n wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED;\n wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED;\n wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED;\n wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED;\n wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED;\n wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED;\n wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED;\n wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED;\n wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED;\n wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED;\n wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED;\n wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED;\n wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED;\n wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED;\n wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED;\n wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED;\n wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED;\n wire [8:0]NLW_U0_rd_data_count_UNCONNECTED;\n wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;\n wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;\n wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED;\n wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;\n wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;\n wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;\n wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED;\n wire [10:0]NLW_U0_wr_data_count_UNCONNECTED;\n\n (* C_ADD_NGC_CONSTRAINT = \"0\" *) \n (* C_APPLICATION_TYPE_AXIS = \"0\" *) \n (* C_APPLICATION_TYPE_RACH = \"0\" *) \n (* C_APPLICATION_TYPE_RDCH = \"0\" *) \n (* C_APPLICATION_TYPE_WACH = \"0\" *) \n (* C_APPLICATION_TYPE_WDCH = \"0\" *) \n (* C_APPLICATION_TYPE_WRCH = \"0\" *) \n (* C_AXIS_TDATA_WIDTH = \"8\" *) \n (* C_AXIS_TDEST_WIDTH = \"1\" *) \n (* C_AXIS_TID_WIDTH = \"1\" *) \n (* C_AXIS_TKEEP_WIDTH = \"1\" *) \n (* C_AXIS_TSTRB_WIDTH = \"1\" *) \n (* C_AXIS_TUSER_WIDTH = \"4\" *) \n (* C_AXIS_TYPE = \"0\" *) \n (* C_AXI_ADDR_WIDTH = \"32\" *) \n (* C_AXI_ARUSER_WIDTH = \"1\" *) \n (* C_AXI_AWUSER_WIDTH = \"1\" *) \n (* C_AXI_BUSER_WIDTH = \"1\" *) \n (* C_AXI_DATA_WIDTH = \"64\" *) \n (* C_AXI_ID_WIDTH = \"1\" *) \n (* C_AXI_LEN_WIDTH = \"8\" *) \n (* C_AXI_LOCK_WIDTH = \"1\" *) \n (* C_AXI_RUSER_WIDTH = \"1\" *) \n (* C_AXI_TYPE = \"1\" *) \n (* C_AXI_WUSER_WIDTH = \"1\" *) \n (* C_COMMON_CLOCK = \"0\" *) \n (* C_COUNT_TYPE = \"0\" *) \n (* C_DATA_COUNT_WIDTH = \"11\" *) \n (* C_DEFAULT_VALUE = \"BlankString\" *) \n (* C_DIN_WIDTH = \"64\" *) \n (* C_DIN_WIDTH_AXIS = \"1\" *) \n (* C_DIN_WIDTH_RACH = \"32\" *) \n (* C_DIN_WIDTH_RDCH = \"64\" *) \n (* C_DIN_WIDTH_WACH = \"1\" *) \n (* C_DIN_WIDTH_WDCH = \"64\" *) \n (* C_DIN_WIDTH_WRCH = \"2\" *) \n (* C_DOUT_RST_VAL = \"0\" *) \n (* C_DOUT_WIDTH = \"256\" *) \n (* C_ENABLE_RLOCS = \"0\" *) \n (* C_ENABLE_RST_SYNC = \"1\" *) \n (* C_EN_SAFETY_CKT = \"0\" *) \n (* C_ERROR_INJECTION_TYPE = \"0\" *) \n (* C_ERROR_INJECTION_TYPE_AXIS = \"0\" *) \n (* C_ERROR_INJECTION_TYPE_RACH = \"0\" *) \n (* C_ERROR_INJECTION_TYPE_RDCH = \"0\" *) \n (* C_ERROR_INJECTION_TYPE_WACH = \"0\" *) \n (* C_ERROR_INJECTION_TYPE_WDCH = \"0\" *) \n (* C_ERROR_INJECTION_TYPE_WRCH = \"0\" *) \n (* C_FAMILY = \"kintex7\" *) \n (* C_FULL_FLAGS_RST_VAL = \"1\" *) \n (* C_HAS_ALMOST_EMPTY = \"0\" *) \n (* C_HAS_ALMOST_FULL = \"0\" *) \n (* C_HAS_AXIS_TDATA = \"1\" *) \n (* C_HAS_AXIS_TDEST = \"0\" *) \n (* C_HAS_AXIS_TID = \"0\" *) \n (* C_HAS_AXIS_TKEEP = \"0\" *) \n (* C_HAS_AXIS_TLAST = \"0\" *) \n (* C_HAS_AXIS_TREADY = \"1\" *) \n (* C_HAS_AXIS_TSTRB = \"0\" *) \n (* C_HAS_AXIS_TUSER = \"1\" *) \n (* C_HAS_AXI_ARUSER = \"0\" *) \n (* C_HAS_AXI_AWUSER = \"0\" *) \n (* C_HAS_AXI_BUSER = \"0\" *) \n (* C_HAS_AXI_ID = \"0\" *) \n (* C_HAS_AXI_RD_CHANNEL = \"1\" *) \n (* C_HAS_AXI_RUSER = \"0\" *) \n (* C_HAS_AXI_WR_CHANNEL = \"1\" *) \n (* C_HAS_AXI_WUSER = \"0\" *) \n (* C_HAS_BACKUP = \"0\" *) \n (* C_HAS_DATA_COUNT = \"0\" *) \n (* C_HAS_DATA_COUNTS_AXIS = \"0\" *) \n (* C_HAS_DATA_COUNTS_RACH = \"0\" *) \n (* C_HAS_DATA_COUNTS_RDCH = \"0\" *) \n (* C_HAS_DATA_COUNTS_WACH = \"0\" *) \n (* C_HAS_DATA_COUNTS_WDCH = \"0\" *) \n (* C_HAS_DATA_COUNTS_WRCH = \"0\" *) \n (* C_HAS_INT_CLK = \"0\" *) \n (* C_HAS_MASTER_CE = \"0\" *) \n (* C_HAS_MEMINIT_FILE = \"0\" *) \n (* C_HAS_OVERFLOW = \"0\" *) \n (* C_HAS_PROG_FLAGS_AXIS = \"0\" *) \n (* C_HAS_PROG_FLAGS_RACH = \"0\" *) \n (* C_HAS_PROG_FLAGS_RDCH = \"0\" *) \n (* C_HAS_PROG_FLAGS_WACH = \"0\" *) \n (* C_HAS_PROG_FLAGS_WDCH = \"0\" *) \n (* C_HAS_PROG_FLAGS_WRCH = \"0\" *) \n (* C_HAS_RD_DATA_COUNT = \"0\" *) \n (* C_HAS_RD_RST = \"0\" *) \n (* C_HAS_RST = \"1\" *) \n (* C_HAS_SLAVE_CE = \"0\" *) \n (* C_HAS_SRST = \"0\" *) \n (* C_HAS_UNDERFLOW = \"0\" *) \n (* C_HAS_VALID = \"0\" *) \n (* C_HAS_WR_ACK = \"0\" *) \n (* C_HAS_WR_DATA_COUNT = \"0\" *) \n (* C_HAS_WR_RST = \"0\" *) \n (* C_IMPLEMENTATION_TYPE = \"2\" *) \n (* C_IMPLEMENTATION_TYPE_AXIS = \"1\" *) \n (* C_IMPLEMENTATION_TYPE_RACH = \"1\" *) \n (* C_IMPLEMENTATION_TYPE_RDCH = \"1\" *) \n (* C_IMPLEMENTATION_TYPE_WACH = \"1\" *) \n (* C_IMPLEMENTATION_TYPE_WDCH = \"1\" *) \n (* C_IMPLEMENTATION_TYPE_WRCH = \"1\" *) \n (* C_INIT_WR_PNTR_VAL = \"0\" *) \n (* C_INTERFACE_TYPE = \"0\" *) \n (* C_MEMORY_TYPE = \"1\" *) \n (* C_MIF_FILE_NAME = \"BlankString\" *) \n (* C_MSGON_VAL = \"1\" *) \n (* C_OPTIMIZATION_MODE = \"0\" *) \n (* C_OVERFLOW_LOW = \"0\" *) \n (* C_POWER_SAVING_MODE = \"0\" *) \n (* C_PRELOAD_LATENCY = \"1\" *) \n (* C_PRELOAD_REGS = \"0\" *) \n (* C_PRIM_FIFO_TYPE = \"2kx18\" *) \n (* C_PRIM_FIFO_TYPE_AXIS = \"1kx18\" *) \n (* C_PRIM_FIFO_TYPE_RACH = \"512x36\" *) \n (* C_PRIM_FIFO_TYPE_RDCH = \"1kx36\" *) \n (* C_PRIM_FIFO_TYPE_WACH = \"512x36\" *) \n (* C_PRIM_FIFO_TYPE_WDCH = \"1kx36\" *) \n (* C_PRIM_FIFO_TYPE_WRCH = \"512x36\" *) \n (* C_PROG_EMPTY_THRESH_ASSERT_VAL = \"15\" *) \n (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = \"1022\" *) \n (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = \"1022\" *) \n (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = \"1022\" *) \n (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = \"1022\" *) \n (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = \"1022\" *) \n (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = \"1022\" *) \n (* C_PROG_EMPTY_THRESH_NEGATE_VAL = \"16\" *) \n (* C_PROG_EMPTY_TYPE = \"1\" *) \n (* C_PROG_EMPTY_TYPE_AXIS = \"0\" *) \n (* C_PROG_EMPTY_TYPE_RACH = \"0\" *) \n (* C_PROG_EMPTY_TYPE_RDCH = \"0\" *) \n (* C_PROG_EMPTY_TYPE_WACH = \"0\" *) \n (* C_PROG_EMPTY_TYPE_WDCH = \"0\" *) \n (* C_PROG_EMPTY_TYPE_WRCH = \"0\" *) \n (* C_PROG_FULL_THRESH_ASSERT_VAL = \"2045\" *) \n (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = \"1023\" *) \n (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = \"1023\" *) \n (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = \"1023\" *) \n (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = \"1023\" *) \n (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = \"1023\" *) \n (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = \"1023\" *) \n (* C_PROG_FULL_THRESH_NEGATE_VAL = \"2044\" *) \n (* C_PROG_FULL_TYPE = \"0\" *) \n (* C_PROG_FULL_TYPE_AXIS = \"0\" *) \n (* C_PROG_FULL_TYPE_RACH = \"0\" *) \n (* C_PROG_FULL_TYPE_RDCH = \"0\" *) \n (* C_PROG_FULL_TYPE_WACH = \"0\" *) \n (* C_PROG_FULL_TYPE_WDCH = \"0\" *) \n (* C_PROG_FULL_TYPE_WRCH = \"0\" *) \n (* C_RACH_TYPE = \"0\" *) \n (* C_RDCH_TYPE = \"0\" *) \n (* C_RD_DATA_COUNT_WIDTH = \"9\" *) \n (* C_RD_DEPTH = \"512\" *) \n (* C_RD_FREQ = \"1\" *) \n (* C_RD_PNTR_WIDTH = \"9\" *) \n (* C_REG_SLICE_MODE_AXIS = \"0\" *) \n (* C_REG_SLICE_MODE_RACH = \"0\" *) \n (* C_REG_SLICE_MODE_RDCH = \"0\" *) \n (* C_REG_SLICE_MODE_WACH = \"0\" *) \n (* C_REG_SLICE_MODE_WDCH = \"0\" *) \n (* C_REG_SLICE_MODE_WRCH = \"0\" *) \n (* C_SELECT_XPM = \"0\" *) \n (* C_SYNCHRONIZER_STAGE = \"2\" *) \n (* C_UNDERFLOW_LOW = \"0\" *) \n (* C_USE_COMMON_OVERFLOW = \"0\" *) \n (* C_USE_COMMON_UNDERFLOW = \"0\" *) \n (* C_USE_DEFAULT_SETTINGS = \"0\" *) \n (* C_USE_DOUT_RST = \"1\" *) \n (* C_USE_ECC = \"0\" *) \n (* C_USE_ECC_AXIS = \"0\" *) \n (* C_USE_ECC_RACH = \"0\" *) \n (* C_USE_ECC_RDCH = \"0\" *) \n (* C_USE_ECC_WACH = \"0\" *) \n (* C_USE_ECC_WDCH = \"0\" *) \n (* C_USE_ECC_WRCH = \"0\" *) \n (* C_USE_EMBEDDED_REG = \"0\" *) \n (* C_USE_FIFO16_FLAGS = \"0\" *) \n (* C_USE_FWFT_DATA_COUNT = \"0\" *) \n (* C_USE_PIPELINE_REG = \"0\" *) \n (* C_VALID_LOW = \"0\" *) \n (* C_WACH_TYPE = \"0\" *) \n (* C_WDCH_TYPE = \"0\" *) \n (* C_WRCH_TYPE = \"0\" *) \n (* C_WR_ACK_LOW = \"0\" *) \n (* C_WR_DATA_COUNT_WIDTH = \"11\" *) \n (* C_WR_DEPTH = \"2048\" *) \n (* C_WR_DEPTH_AXIS = \"1024\" *) \n (* C_WR_DEPTH_RACH = \"16\" *) \n (* C_WR_DEPTH_RDCH = \"1024\" *) \n (* C_WR_DEPTH_WACH = \"16\" *) \n (* C_WR_DEPTH_WDCH = \"1024\" *) \n (* C_WR_DEPTH_WRCH = \"16\" *) \n (* C_WR_FREQ = \"1\" *) \n (* C_WR_PNTR_WIDTH = \"11\" *) \n (* C_WR_PNTR_WIDTH_AXIS = \"10\" *) \n (* C_WR_PNTR_WIDTH_RACH = \"4\" *) \n (* C_WR_PNTR_WIDTH_RDCH = \"10\" *) \n (* C_WR_PNTR_WIDTH_WACH = \"4\" *) \n (* C_WR_PNTR_WIDTH_WDCH = \"10\" *) \n (* C_WR_PNTR_WIDTH_WRCH = \"4\" *) \n (* C_WR_RESPONSE_LATENCY = \"1\" *) \n fb_input_fifo_fifo_generator_v13_1_2 U0\n (.almost_empty(NLW_U0_almost_empty_UNCONNECTED),\n .almost_full(NLW_U0_almost_full_UNCONNECTED),\n .axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]),\n .axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED),\n .axi_ar_injectdbiterr(1'b0),\n .axi_ar_injectsbiterr(1'b0),\n .axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED),\n .axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED),\n .axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),\n .axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED),\n .axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),\n .axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]),\n .axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED),\n .axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED),\n .axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]),\n .axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]),\n .axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED),\n .axi_aw_injectdbiterr(1'b0),\n .axi_aw_injectsbiterr(1'b0),\n .axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED),\n .axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED),\n .axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),\n .axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED),\n .axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),\n .axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]),\n .axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED),\n .axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED),\n .axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]),\n .axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]),\n .axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED),\n .axi_b_injectdbiterr(1'b0),\n .axi_b_injectsbiterr(1'b0),\n .axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED),\n .axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED),\n .axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),\n .axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED),\n .axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),\n .axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]),\n .axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED),\n .axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED),\n .axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]),\n .axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]),\n .axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED),\n .axi_r_injectdbiterr(1'b0),\n .axi_r_injectsbiterr(1'b0),\n .axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED),\n .axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED),\n .axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED),\n .axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]),\n .axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED),\n .axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED),\n .axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]),\n .axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]),\n .axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED),\n .axi_w_injectdbiterr(1'b0),\n .axi_w_injectsbiterr(1'b0),\n .axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED),\n .axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED),\n .axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED),\n .axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]),\n .axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED),\n .axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED),\n .axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]),\n .axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]),\n .axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED),\n .axis_injectdbiterr(1'b0),\n .axis_injectsbiterr(1'b0),\n .axis_overflow(NLW_U0_axis_overflow_UNCONNECTED),\n .axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED),\n .axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED),\n .axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]),\n .axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED),\n .axis_underflow(NLW_U0_axis_underflow_UNCONNECTED),\n .axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]),\n .backup(1'b0),\n .backup_marker(1'b0),\n .clk(1'b0),\n .data_count(NLW_U0_data_count_UNCONNECTED[10:0]),\n .dbiterr(NLW_U0_dbiterr_UNCONNECTED),\n .din(din),\n .dout(dout),\n .empty(empty),\n .full(full),\n .injectdbiterr(1'b0),\n .injectsbiterr(1'b0),\n .int_clk(1'b0),\n .m_aclk(1'b0),\n .m_aclk_en(1'b0),\n .m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]),\n .m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]),\n .m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]),\n .m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]),\n .m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]),\n .m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]),\n .m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]),\n .m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]),\n .m_axi_arready(1'b0),\n .m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]),\n .m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]),\n .m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]),\n .m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED),\n .m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]),\n .m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]),\n .m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]),\n .m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]),\n .m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]),\n .m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]),\n .m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]),\n .m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]),\n .m_axi_awready(1'b0),\n .m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]),\n .m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]),\n .m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]),\n .m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED),\n .m_axi_bid(1'b0),\n .m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED),\n .m_axi_bresp({1'b0,1'b0}),\n .m_axi_buser(1'b0),\n .m_axi_bvalid(1'b0),\n .m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .m_axi_rid(1'b0),\n .m_axi_rlast(1'b0),\n .m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED),\n .m_axi_rresp({1'b0,1'b0}),\n .m_axi_ruser(1'b0),\n .m_axi_rvalid(1'b0),\n .m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]),\n .m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]),\n .m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED),\n .m_axi_wready(1'b0),\n .m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]),\n .m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]),\n .m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED),\n .m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]),\n .m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]),\n .m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]),\n .m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]),\n .m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED),\n .m_axis_tready(1'b0),\n .m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]),\n .m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]),\n .m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED),\n .overflow(NLW_U0_overflow_UNCONNECTED),\n .prog_empty(prog_empty),\n .prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .prog_full(NLW_U0_prog_full_UNCONNECTED),\n .prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .rd_clk(rd_clk),\n .rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[8:0]),\n .rd_en(rd_en),\n .rd_rst(1'b0),\n .rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED),\n .rst(rst),\n .s_aclk(1'b0),\n .s_aclk_en(1'b0),\n .s_aresetn(1'b0),\n .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axi_arburst({1'b0,1'b0}),\n .s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),\n .s_axi_arid(1'b0),\n .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axi_arlock(1'b0),\n .s_axi_arprot({1'b0,1'b0,1'b0}),\n .s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),\n .s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),\n .s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),\n .s_axi_arsize({1'b0,1'b0,1'b0}),\n .s_axi_aruser(1'b0),\n .s_axi_arvalid(1'b0),\n .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axi_awburst({1'b0,1'b0}),\n .s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),\n .s_axi_awid(1'b0),\n .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axi_awlock(1'b0),\n .s_axi_awprot({1'b0,1'b0,1'b0}),\n .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),\n .s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),\n .s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),\n .s_axi_awsize({1'b0,1'b0,1'b0}),\n .s_axi_awuser(1'b0),\n .s_axi_awvalid(1'b0),\n .s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),\n .s_axi_bready(1'b0),\n .s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),\n .s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]),\n .s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),\n .s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),\n .s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),\n .s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),\n .s_axi_rready(1'b0),\n .s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),\n .s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]),\n .s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),\n .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axi_wid(1'b0),\n .s_axi_wlast(1'b0),\n .s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),\n .s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axi_wuser(1'b0),\n .s_axi_wvalid(1'b0),\n .s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axis_tdest(1'b0),\n .s_axis_tid(1'b0),\n .s_axis_tkeep(1'b0),\n .s_axis_tlast(1'b0),\n .s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED),\n .s_axis_tstrb(1'b0),\n .s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),\n .s_axis_tvalid(1'b0),\n .sbiterr(NLW_U0_sbiterr_UNCONNECTED),\n .sleep(1'b0),\n .srst(1'b0),\n .underflow(NLW_U0_underflow_UNCONNECTED),\n .valid(NLW_U0_valid_UNCONNECTED),\n .wr_ack(NLW_U0_wr_ack_UNCONNECTED),\n .wr_clk(wr_clk),\n .wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[10:0]),\n .wr_en(wr_en),\n .wr_rst(1'b0),\n .wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED));\nendmodule\n\n(* CHECK_LICENSE_TYPE = \"fb_output_fifo,fifo_generator_v13_1_2,{}\" *) (* downgradeipidentifiedwarnings = \"yes\" *) (* x_core_info = \"fifo_generator_v13_1_2,Vivado 2016.3\" *) \nmodule fb_output_fifo\n (rst,\n wr_clk,\n rd_clk,\n din,\n wr_en,\n rd_en,\n dout,\n full,\n empty,\n prog_full);\n input rst;\n (* x_interface_info = \"xilinx.com:signal:clock:1.0 write_clk CLK\" *) input wr_clk;\n (* x_interface_info = \"xilinx.com:signal:clock:1.0 read_clk CLK\" *) input rd_clk;\n (* x_interface_info = \"xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA\" *) input [127:0]din;\n (* x_interface_info = \"xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN\" *) input wr_en;\n (* x_interface_info = \"xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN\" *) input rd_en;\n (* x_interface_info = \"xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA\" *) output [31:0]dout;\n (* x_interface_info = \"xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL\" *) output full;\n (* x_interface_info = \"xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY\" *) output empty;\n output prog_full;\n\n wire [127:0]din;\n wire [31:0]dout;\n wire empty;\n wire full;\n wire prog_full;\n wire rd_clk;\n wire rd_en;\n wire rst;\n wire wr_clk;\n wire wr_en;\n wire NLW_U0_almost_empty_UNCONNECTED;\n wire NLW_U0_almost_full_UNCONNECTED;\n wire NLW_U0_axi_ar_dbiterr_UNCONNECTED;\n wire NLW_U0_axi_ar_overflow_UNCONNECTED;\n wire NLW_U0_axi_ar_prog_empty_UNCONNECTED;\n wire NLW_U0_axi_ar_prog_full_UNCONNECTED;\n wire NLW_U0_axi_ar_sbiterr_UNCONNECTED;\n wire NLW_U0_axi_ar_underflow_UNCONNECTED;\n wire NLW_U0_axi_aw_dbiterr_UNCONNECTED;\n wire NLW_U0_axi_aw_overflow_UNCONNECTED;\n wire NLW_U0_axi_aw_prog_empty_UNCONNECTED;\n wire NLW_U0_axi_aw_prog_full_UNCONNECTED;\n wire NLW_U0_axi_aw_sbiterr_UNCONNECTED;\n wire NLW_U0_axi_aw_underflow_UNCONNECTED;\n wire NLW_U0_axi_b_dbiterr_UNCONNECTED;\n wire NLW_U0_axi_b_overflow_UNCONNECTED;\n wire NLW_U0_axi_b_prog_empty_UNCONNECTED;\n wire NLW_U0_axi_b_prog_full_UNCONNECTED;\n wire NLW_U0_axi_b_sbiterr_UNCONNECTED;\n wire NLW_U0_axi_b_underflow_UNCONNECTED;\n wire NLW_U0_axi_r_dbiterr_UNCONNECTED;\n wire NLW_U0_axi_r_overflow_UNCONNECTED;\n wire NLW_U0_axi_r_prog_empty_UNCONNECTED;\n wire NLW_U0_axi_r_prog_full_UNCONNECTED;\n wire NLW_U0_axi_r_sbiterr_UNCONNECTED;\n wire NLW_U0_axi_r_underflow_UNCONNECTED;\n wire NLW_U0_axi_w_dbiterr_UNCONNECTED;\n wire NLW_U0_axi_w_overflow_UNCONNECTED;\n wire NLW_U0_axi_w_prog_empty_UNCONNECTED;\n wire NLW_U0_axi_w_prog_full_UNCONNECTED;\n wire NLW_U0_axi_w_sbiterr_UNCONNECTED;\n wire NLW_U0_axi_w_underflow_UNCONNECTED;\n wire NLW_U0_axis_dbiterr_UNCONNECTED;\n wire NLW_U0_axis_overflow_UNCONNECTED;\n wire NLW_U0_axis_prog_empty_UNCONNECTED;\n wire NLW_U0_axis_prog_full_UNCONNECTED;\n wire NLW_U0_axis_sbiterr_UNCONNECTED;\n wire NLW_U0_axis_underflow_UNCONNECTED;\n wire NLW_U0_dbiterr_UNCONNECTED;\n wire NLW_U0_m_axi_arvalid_UNCONNECTED;\n wire NLW_U0_m_axi_awvalid_UNCONNECTED;\n wire NLW_U0_m_axi_bready_UNCONNECTED;\n wire NLW_U0_m_axi_rready_UNCONNECTED;\n wire NLW_U0_m_axi_wlast_UNCONNECTED;\n wire NLW_U0_m_axi_wvalid_UNCONNECTED;\n wire NLW_U0_m_axis_tlast_UNCONNECTED;\n wire NLW_U0_m_axis_tvalid_UNCONNECTED;\n wire NLW_U0_overflow_UNCONNECTED;\n wire NLW_U0_prog_empty_UNCONNECTED;\n wire NLW_U0_rd_rst_busy_UNCONNECTED;\n wire NLW_U0_s_axi_arready_UNCONNECTED;\n wire NLW_U0_s_axi_awready_UNCONNECTED;\n wire NLW_U0_s_axi_bvalid_UNCONNECTED;\n wire NLW_U0_s_axi_rlast_UNCONNECTED;\n wire NLW_U0_s_axi_rvalid_UNCONNECTED;\n wire NLW_U0_s_axi_wready_UNCONNECTED;\n wire NLW_U0_s_axis_tready_UNCONNECTED;\n wire NLW_U0_sbiterr_UNCONNECTED;\n wire NLW_U0_underflow_UNCONNECTED;\n wire NLW_U0_valid_UNCONNECTED;\n wire NLW_U0_wr_ack_UNCONNECTED;\n wire NLW_U0_wr_rst_busy_UNCONNECTED;\n wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED;\n wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED;\n wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED;\n wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED;\n wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED;\n wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED;\n wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED;\n wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED;\n wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED;\n wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED;\n wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED;\n wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED;\n wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED;\n wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED;\n wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED;\n wire [10:0]NLW_U0_axis_data_count_UNCONNECTED;\n wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED;\n wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED;\n wire [8:0]NLW_U0_data_count_UNCONNECTED;\n wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED;\n wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED;\n wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED;\n wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED;\n wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED;\n wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED;\n wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED;\n wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED;\n wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED;\n wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED;\n wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED;\n wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED;\n wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED;\n wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED;\n wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED;\n wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED;\n wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED;\n wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED;\n wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED;\n wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED;\n wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED;\n wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED;\n wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED;\n wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED;\n wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED;\n wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED;\n wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED;\n wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED;\n wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED;\n wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED;\n wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED;\n wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED;\n wire [10:0]NLW_U0_rd_data_count_UNCONNECTED;\n wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;\n wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;\n wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED;\n wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;\n wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;\n wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;\n wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED;\n wire [8:0]NLW_U0_wr_data_count_UNCONNECTED;\n\n (* C_ADD_NGC_CONSTRAINT = \"0\" *) \n (* C_APPLICATION_TYPE_AXIS = \"0\" *) \n (* C_APPLICATION_TYPE_RACH = \"0\" *) \n (* C_APPLICATION_TYPE_RDCH = \"0\" *) \n (* C_APPLICATION_TYPE_WACH = \"0\" *) \n (* C_APPLICATION_TYPE_WDCH = \"0\" *) \n (* C_APPLICATION_TYPE_WRCH = \"0\" *) \n (* C_AXIS_TDATA_WIDTH = \"8\" *) \n (* C_AXIS_TDEST_WIDTH = \"1\" *) \n (* C_AXIS_TID_WIDTH = \"1\" *) \n (* C_AXIS_TKEEP_WIDTH = \"1\" *) \n (* C_AXIS_TSTRB_WIDTH = \"1\" *) \n (* C_AXIS_TUSER_WIDTH = \"4\" *) \n (* C_AXIS_TYPE = \"0\" *) \n (* C_AXI_ADDR_WIDTH = \"32\" *) \n (* C_AXI_ARUSER_WIDTH = \"1\" *) \n (* C_AXI_AWUSER_WIDTH = \"1\" *) \n (* C_AXI_BUSER_WIDTH = \"1\" *) \n (* C_AXI_DATA_WIDTH = \"64\" *) \n (* C_AXI_ID_WIDTH = \"1\" *) \n (* C_AXI_LEN_WIDTH = \"8\" *) \n (* C_AXI_LOCK_WIDTH = \"1\" *) \n (* C_AXI_RUSER_WIDTH = \"1\" *) \n (* C_AXI_TYPE = \"1\" *) \n (* C_AXI_WUSER_WIDTH = \"1\" *) \n (* C_COMMON_CLOCK = \"0\" *) \n (* C_COUNT_TYPE = \"0\" *) \n (* C_DATA_COUNT_WIDTH = \"9\" *) \n (* C_DEFAULT_VALUE = \"BlankString\" *) \n (* C_DIN_WIDTH = \"128\" *) \n (* C_DIN_WIDTH_AXIS = \"1\" *) \n (* C_DIN_WIDTH_RACH = \"32\" *) \n (* C_DIN_WIDTH_RDCH = \"64\" *) \n (* C_DIN_WIDTH_WACH = \"1\" *) \n (* C_DIN_WIDTH_WDCH = \"64\" *) \n (* C_DIN_WIDTH_WRCH = \"2\" *) \n (* C_DOUT_RST_VAL = \"0\" *) \n (* C_DOUT_WIDTH = \"32\" *) \n (* C_ENABLE_RLOCS = \"0\" *) \n (* C_ENABLE_RST_SYNC = \"1\" *) \n (* C_EN_SAFETY_CKT = \"0\" *) \n (* C_ERROR_INJECTION_TYPE = \"0\" *) \n (* C_ERROR_INJECTION_TYPE_AXIS = \"0\" *) \n (* C_ERROR_INJECTION_TYPE_RACH = \"0\" *) \n (* C_ERROR_INJECTION_TYPE_RDCH = \"0\" *) \n (* C_ERROR_INJECTION_TYPE_WACH = \"0\" *) \n (* C_ERROR_INJECTION_TYPE_WDCH = \"0\" *) \n (* C_ERROR_INJECTION_TYPE_WRCH = \"0\" *) \n (* C_FAMILY = \"kintex7\" *) \n (* C_FULL_FLAGS_RST_VAL = \"1\" *) \n (* C_HAS_ALMOST_EMPTY = \"0\" *) \n (* C_HAS_ALMOST_FULL = \"0\" *) \n (* C_HAS_AXIS_TDATA = \"1\" *) \n (* C_HAS_AXIS_TDEST = \"0\" *) \n (* C_HAS_AXIS_TID = \"0\" *) \n (* C_HAS_AXIS_TKEEP = \"0\" *) \n (* C_HAS_AXIS_TLAST = \"0\" *) \n (* C_HAS_AXIS_TREADY = \"1\" *) \n (* C_HAS_AXIS_TSTRB = \"0\" *) \n (* C_HAS_AXIS_TUSER = \"1\" *) \n (* C_HAS_AXI_ARUSER = \"0\" *) \n (* C_HAS_AXI_AWUSER = \"0\" *) \n (* C_HAS_AXI_BUSER = \"0\" *) \n (* C_HAS_AXI_ID = \"0\" *) \n (* C_HAS_AXI_RD_CHANNEL = \"1\" *) \n (* C_HAS_AXI_RUSER = \"0\" *) \n (* C_HAS_AXI_WR_CHANNEL = \"1\" *) \n (* C_HAS_AXI_WUSER = \"0\" *) \n (* C_HAS_BACKUP = \"0\" *) \n (* C_HAS_DATA_COUNT = \"0\" *) \n (* C_HAS_DATA_COUNTS_AXIS = \"0\" *) \n (* C_HAS_DATA_COUNTS_RACH = \"0\" *) \n (* C_HAS_DATA_COUNTS_RDCH = \"0\" *) \n (* C_HAS_DATA_COUNTS_WACH = \"0\" *) \n (* C_HAS_DATA_COUNTS_WDCH = \"0\" *) \n (* C_HAS_DATA_COUNTS_WRCH = \"0\" *) \n (* C_HAS_INT_CLK = \"0\" *) \n (* C_HAS_MASTER_CE = \"0\" *) \n (* C_HAS_MEMINIT_FILE = \"0\" *) \n (* C_HAS_OVERFLOW = \"0\" *) \n (* C_HAS_PROG_FLAGS_AXIS = \"0\" *) \n (* C_HAS_PROG_FLAGS_RACH = \"0\" *) \n (* C_HAS_PROG_FLAGS_RDCH = \"0\" *) \n (* C_HAS_PROG_FLAGS_WACH = \"0\" *) \n (* C_HAS_PROG_FLAGS_WDCH = \"0\" *) \n (* C_HAS_PROG_FLAGS_WRCH = \"0\" *) \n (* C_HAS_RD_DATA_COUNT = \"0\" *) \n (* C_HAS_RD_RST = \"0\" *) \n (* C_HAS_RST = \"1\" *) \n (* C_HAS_SLAVE_CE = \"0\" *) \n (* C_HAS_SRST = \"0\" *) \n (* C_HAS_UNDERFLOW = \"0\" *) \n (* C_HAS_VALID = \"0\" *) \n (* C_HAS_WR_ACK = \"0\" *) \n (* C_HAS_WR_DATA_COUNT = \"0\" *) \n (* C_HAS_WR_RST = \"0\" *) \n (* C_IMPLEMENTATION_TYPE = \"2\" *) \n (* C_IMPLEMENTATION_TYPE_AXIS = \"1\" *) \n (* C_IMPLEMENTATION_TYPE_RACH = \"1\" *) \n (* C_IMPLEMENTATION_TYPE_RDCH = \"1\" *) \n (* C_IMPLEMENTATION_TYPE_WACH = \"1\" *) \n (* C_IMPLEMENTATION_TYPE_WDCH = \"1\" *) \n (* C_IMPLEMENTATION_TYPE_WRCH = \"1\" *) \n (* C_INIT_WR_PNTR_VAL = \"0\" *) \n (* C_INTERFACE_TYPE = \"0\" *) \n (* C_MEMORY_TYPE = \"1\" *) \n (* C_MIF_FILE_NAME = \"BlankString\" *) \n (* C_MSGON_VAL = \"1\" *) \n (* C_OPTIMIZATION_MODE = \"0\" *) \n (* C_OVERFLOW_LOW = \"0\" *) \n (* C_POWER_SAVING_MODE = \"0\" *) \n (* C_PRELOAD_LATENCY = \"1\" *) \n (* C_PRELOAD_REGS = \"0\" *) \n (* C_PRIM_FIFO_TYPE = \"512x72\" *) \n (* C_PRIM_FIFO_TYPE_AXIS = \"1kx18\" *) \n (* C_PRIM_FIFO_TYPE_RACH = \"512x36\" *) \n (* C_PRIM_FIFO_TYPE_RDCH = \"1kx36\" *) \n (* C_PRIM_FIFO_TYPE_WACH = \"512x36\" *) \n (* C_PRIM_FIFO_TYPE_WDCH = \"1kx36\" *) \n (* C_PRIM_FIFO_TYPE_WRCH = \"512x36\" *) \n (* C_PROG_EMPTY_THRESH_ASSERT_VAL = \"2\" *) \n (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = \"1022\" *) \n (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = \"1022\" *) \n (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = \"1022\" *) \n (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = \"1022\" *) \n (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = \"1022\" *) \n (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = \"1022\" *) \n (* C_PROG_EMPTY_THRESH_NEGATE_VAL = \"3\" *) \n (* C_PROG_EMPTY_TYPE = \"0\" *) \n (* C_PROG_EMPTY_TYPE_AXIS = \"0\" *) \n (* C_PROG_EMPTY_TYPE_RACH = \"0\" *) \n (* C_PROG_EMPTY_TYPE_RDCH = \"0\" *) \n (* C_PROG_EMPTY_TYPE_WACH = \"0\" *) \n (* C_PROG_EMPTY_TYPE_WDCH = \"0\" *) \n (* C_PROG_EMPTY_TYPE_WRCH = \"0\" *) \n (* C_PROG_FULL_THRESH_ASSERT_VAL = \"496\" *) \n (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = \"1023\" *) \n (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = \"1023\" *) \n (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = \"1023\" *) \n (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = \"1023\" *) \n (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = \"1023\" *) \n (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = \"1023\" *) \n (* C_PROG_FULL_THRESH_NEGATE_VAL = \"495\" *) \n (* C_PROG_FULL_TYPE = \"1\" *) \n (* C_PROG_FULL_TYPE_AXIS = \"0\" *) \n (* C_PROG_FULL_TYPE_RACH = \"0\" *) \n (* C_PROG_FULL_TYPE_RDCH = \"0\" *) \n (* C_PROG_FULL_TYPE_WACH = \"0\" *) \n (* C_PROG_FULL_TYPE_WDCH = \"0\" *) \n (* C_PROG_FULL_TYPE_WRCH = \"0\" *) \n (* C_RACH_TYPE = \"0\" *) \n (* C_RDCH_TYPE = \"0\" *) \n (* C_RD_DATA_COUNT_WIDTH = \"11\" *) \n (* C_RD_DEPTH = \"2048\" *) \n (* C_RD_FREQ = \"1\" *) \n (* C_RD_PNTR_WIDTH = \"11\" *) \n (* C_REG_SLICE_MODE_AXIS = \"0\" *) \n (* C_REG_SLICE_MODE_RACH = \"0\" *) \n (* C_REG_SLICE_MODE_RDCH = \"0\" *) \n (* C_REG_SLICE_MODE_WACH = \"0\" *) \n (* C_REG_SLICE_MODE_WDCH = \"0\" *) \n (* C_REG_SLICE_MODE_WRCH = \"0\" *) \n (* C_SELECT_XPM = \"0\" *) \n (* C_SYNCHRONIZER_STAGE = \"2\" *) \n (* C_UNDERFLOW_LOW = \"0\" *) \n (* C_USE_COMMON_OVERFLOW = \"0\" *) \n (* C_USE_COMMON_UNDERFLOW = \"0\" *) \n (* C_USE_DEFAULT_SETTINGS = \"0\" *) \n (* C_USE_DOUT_RST = \"1\" *) \n (* C_USE_ECC = \"0\" *) \n (* C_USE_ECC_AXIS = \"0\" *) \n (* C_USE_ECC_RACH = \"0\" *) \n (* C_USE_ECC_RDCH = \"0\" *) \n (* C_USE_ECC_WACH = \"0\" *) \n (* C_USE_ECC_WDCH = \"0\" *) \n (* C_USE_ECC_WRCH = \"0\" *) \n (* C_USE_EMBEDDED_REG = \"0\" *) \n (* C_USE_FIFO16_FLAGS = \"0\" *) \n (* C_USE_FWFT_DATA_COUNT = \"0\" *) \n (* C_USE_PIPELINE_REG = \"0\" *) \n (* C_VALID_LOW = \"0\" *) \n (* C_WACH_TYPE = \"0\" *) \n (* C_WDCH_TYPE = \"0\" *) \n (* C_WRCH_TYPE = \"0\" *) \n (* C_WR_ACK_LOW = \"0\" *) \n (* C_WR_DATA_COUNT_WIDTH = \"9\" *) \n (* C_WR_DEPTH = \"512\" *) \n (* C_WR_DEPTH_AXIS = \"1024\" *) \n (* C_WR_DEPTH_RACH = \"16\" *) \n (* C_WR_DEPTH_RDCH = \"1024\" *) \n (* C_WR_DEPTH_WACH = \"16\" *) \n (* C_WR_DEPTH_WDCH = \"1024\" *) \n (* C_WR_DEPTH_WRCH = \"16\" *) \n (* C_WR_FREQ = \"1\" *) \n (* C_WR_PNTR_WIDTH = \"9\" *) \n (* C_WR_PNTR_WIDTH_AXIS = \"10\" *) \n (* C_WR_PNTR_WIDTH_RACH = \"4\" *) \n (* C_WR_PNTR_WIDTH_RDCH = \"10\" *) \n (* C_WR_PNTR_WIDTH_WACH = \"4\" *) \n (* C_WR_PNTR_WIDTH_WDCH = \"10\" *) \n (* C_WR_PNTR_WIDTH_WRCH = \"4\" *) \n (* C_WR_RESPONSE_LATENCY = \"1\" *) \n fb_output_fifo_fifo_generator_v13_1_2 U0\n (.almost_empty(NLW_U0_almost_empty_UNCONNECTED),\n .almost_full(NLW_U0_almost_full_UNCONNECTED),\n .axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]),\n .axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED),\n .axi_ar_injectdbiterr(1'b0),\n .axi_ar_injectsbiterr(1'b0),\n .axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED),\n .axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED),\n .axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),\n .axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED),\n .axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),\n .axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]),\n .axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED),\n .axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED),\n .axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]),\n .axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]),\n .axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED),\n .axi_aw_injectdbiterr(1'b0),\n .axi_aw_injectsbiterr(1'b0),\n .axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED),\n .axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED),\n .axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),\n .axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED),\n .axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),\n .axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]),\n .axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED),\n .axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED),\n .axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]),\n .axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]),\n .axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED),\n .axi_b_injectdbiterr(1'b0),\n .axi_b_injectsbiterr(1'b0),\n .axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED),\n .axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED),\n .axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),\n .axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED),\n .axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),\n .axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]),\n .axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED),\n .axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED),\n .axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]),\n .axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]),\n .axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED),\n .axi_r_injectdbiterr(1'b0),\n .axi_r_injectsbiterr(1'b0),\n .axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED),\n .axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED),\n .axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED),\n .axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]),\n .axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED),\n .axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED),\n .axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]),\n .axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]),\n .axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED),\n .axi_w_injectdbiterr(1'b0),\n .axi_w_injectsbiterr(1'b0),\n .axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED),\n .axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED),\n .axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED),\n .axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]),\n .axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED),\n .axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED),\n .axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]),\n .axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]),\n .axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED),\n .axis_injectdbiterr(1'b0),\n .axis_injectsbiterr(1'b0),\n .axis_overflow(NLW_U0_axis_overflow_UNCONNECTED),\n .axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED),\n .axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED),\n .axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]),\n .axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED),\n .axis_underflow(NLW_U0_axis_underflow_UNCONNECTED),\n .axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]),\n .backup(1'b0),\n .backup_marker(1'b0),\n .clk(1'b0),\n .data_count(NLW_U0_data_count_UNCONNECTED[8:0]),\n .dbiterr(NLW_U0_dbiterr_UNCONNECTED),\n .din(din),\n .dout(dout),\n .empty(empty),\n .full(full),\n .injectdbiterr(1'b0),\n .injectsbiterr(1'b0),\n .int_clk(1'b0),\n .m_aclk(1'b0),\n .m_aclk_en(1'b0),\n .m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]),\n .m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]),\n .m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]),\n .m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]),\n .m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]),\n .m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]),\n .m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]),\n .m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]),\n .m_axi_arready(1'b0),\n .m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]),\n .m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]),\n .m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]),\n .m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED),\n .m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]),\n .m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]),\n .m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]),\n .m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]),\n .m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]),\n .m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]),\n .m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]),\n .m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]),\n .m_axi_awready(1'b0),\n .m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]),\n .m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]),\n .m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]),\n .m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED),\n .m_axi_bid(1'b0),\n .m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED),\n .m_axi_bresp({1'b0,1'b0}),\n .m_axi_buser(1'b0),\n .m_axi_bvalid(1'b0),\n .m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .m_axi_rid(1'b0),\n .m_axi_rlast(1'b0),\n .m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED),\n .m_axi_rresp({1'b0,1'b0}),\n .m_axi_ruser(1'b0),\n .m_axi_rvalid(1'b0),\n .m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]),\n .m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]),\n .m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED),\n .m_axi_wready(1'b0),\n .m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]),\n .m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]),\n .m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED),\n .m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]),\n .m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]),\n .m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]),\n .m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]),\n .m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED),\n .m_axis_tready(1'b0),\n .m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]),\n .m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]),\n .m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED),\n .overflow(NLW_U0_overflow_UNCONNECTED),\n .prog_empty(NLW_U0_prog_empty_UNCONNECTED),\n .prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .prog_full(prog_full),\n .prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .rd_clk(rd_clk),\n .rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[10:0]),\n .rd_en(rd_en),\n .rd_rst(1'b0),\n .rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED),\n .rst(rst),\n .s_aclk(1'b0),\n .s_aclk_en(1'b0),\n .s_aresetn(1'b0),\n .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axi_arburst({1'b0,1'b0}),\n .s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),\n .s_axi_arid(1'b0),\n .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axi_arlock(1'b0),\n .s_axi_arprot({1'b0,1'b0,1'b0}),\n .s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),\n .s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),\n .s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),\n .s_axi_arsize({1'b0,1'b0,1'b0}),\n .s_axi_aruser(1'b0),\n .s_axi_arvalid(1'b0),\n .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axi_awburst({1'b0,1'b0}),\n .s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),\n .s_axi_awid(1'b0),\n .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axi_awlock(1'b0),\n .s_axi_awprot({1'b0,1'b0,1'b0}),\n .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),\n .s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),\n .s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),\n .s_axi_awsize({1'b0,1'b0,1'b0}),\n .s_axi_awuser(1'b0),\n .s_axi_awvalid(1'b0),\n .s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),\n .s_axi_bready(1'b0),\n .s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),\n .s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]),\n .s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),\n .s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),\n .s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),\n .s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),\n .s_axi_rready(1'b0),\n .s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),\n .s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]),\n .s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),\n .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axi_wid(1'b0),\n .s_axi_wlast(1'b0),\n .s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),\n .s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axi_wuser(1'b0),\n .s_axi_wvalid(1'b0),\n .s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axis_tdest(1'b0),\n .s_axis_tid(1'b0),\n .s_axis_tkeep(1'b0),\n .s_axis_tlast(1'b0),\n .s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED),\n .s_axis_tstrb(1'b0),\n .s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),\n .s_axis_tvalid(1'b0),\n .sbiterr(NLW_U0_sbiterr_UNCONNECTED),\n .sleep(1'b0),\n .srst(1'b0),\n .underflow(NLW_U0_underflow_UNCONNECTED),\n .valid(NLW_U0_valid_UNCONNECTED),\n .wr_ack(NLW_U0_wr_ack_UNCONNECTED),\n .wr_clk(wr_clk),\n .wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[8:0]),\n .wr_en(wr_en),\n .wr_rst(1'b0),\n .wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED));\nendmodule\n\nmodule framebuffer_addr_ctrl\n (s_axi_awaddr,\n \\FSM_sequential_write_state_reg[0] ,\n \\FSM_sequential_write_state_reg[0]_0 ,\n ui_clk,\n rst,\n out);\n output [16:0]s_axi_awaddr;\n output \\FSM_sequential_write_state_reg[0] ;\n output \\FSM_sequential_write_state_reg[0]_0 ;\n input ui_clk;\n input rst;\n input [2:0]out;\n\n wire \\FSM_sequential_write_state[2]_i_6_n_0 ;\n wire \\FSM_sequential_write_state_reg[0] ;\n wire \\FSM_sequential_write_state_reg[0]_0 ;\n wire fb_xpos_q;\n wire \\fb_xpos_q[11]_i_2_n_0 ;\n wire \\fb_xpos_q[7]_i_3_n_0 ;\n wire \\fb_xpos_q[7]_i_4_n_0 ;\n wire \\fb_xpos_q[7]_i_5_n_0 ;\n wire \\fb_xpos_q[7]_i_6_n_0 ;\n wire [11:7]fb_xpos_q_reg;\n wire \\fb_xpos_q_reg[11]_i_1_n_7 ;\n wire \\fb_xpos_q_reg[7]_i_2_n_0 ;\n wire \\fb_xpos_q_reg[7]_i_2_n_1 ;\n wire \\fb_xpos_q_reg[7]_i_2_n_2 ;\n wire \\fb_xpos_q_reg[7]_i_2_n_3 ;\n wire \\fb_xpos_q_reg[7]_i_2_n_4 ;\n wire \\fb_xpos_q_reg[7]_i_2_n_5 ;\n wire \\fb_xpos_q_reg[7]_i_2_n_6 ;\n wire \\fb_xpos_q_reg[7]_i_2_n_7 ;\n wire \\fb_ypos_q[0]_i_10_n_0 ;\n wire \\fb_ypos_q[0]_i_1_n_0 ;\n wire \\fb_ypos_q[0]_i_3_n_0 ;\n wire \\fb_ypos_q[0]_i_4_n_0 ;\n wire \\fb_ypos_q[0]_i_5_n_0 ;\n wire \\fb_ypos_q[0]_i_6_n_0 ;\n wire \\fb_ypos_q[0]_i_7_n_0 ;\n wire \\fb_ypos_q[0]_i_8_n_0 ;\n wire \\fb_ypos_q[0]_i_9_n_0 ;\n wire \\fb_ypos_q[4]_i_2_n_0 ;\n wire \\fb_ypos_q[4]_i_3_n_0 ;\n wire \\fb_ypos_q[4]_i_4_n_0 ;\n wire \\fb_ypos_q[4]_i_5_n_0 ;\n wire \\fb_ypos_q[8]_i_2_n_0 ;\n wire \\fb_ypos_q[8]_i_3_n_0 ;\n wire \\fb_ypos_q[8]_i_4_n_0 ;\n wire \\fb_ypos_q[8]_i_5_n_0 ;\n wire [11:0]fb_ypos_q_reg;\n wire \\fb_ypos_q_reg[0]_i_2_n_0 ;\n wire \\fb_ypos_q_reg[0]_i_2_n_1 ;\n wire \\fb_ypos_q_reg[0]_i_2_n_2 ;\n wire \\fb_ypos_q_reg[0]_i_2_n_3 ;\n wire \\fb_ypos_q_reg[0]_i_2_n_4 ;\n wire \\fb_ypos_q_reg[0]_i_2_n_5 ;\n wire \\fb_ypos_q_reg[0]_i_2_n_6 ;\n wire \\fb_ypos_q_reg[0]_i_2_n_7 ;\n wire \\fb_ypos_q_reg[4]_i_1_n_0 ;\n wire \\fb_ypos_q_reg[4]_i_1_n_1 ;\n wire \\fb_ypos_q_reg[4]_i_1_n_2 ;\n wire \\fb_ypos_q_reg[4]_i_1_n_3 ;\n wire \\fb_ypos_q_reg[4]_i_1_n_4 ;\n wire \\fb_ypos_q_reg[4]_i_1_n_5 ;\n wire \\fb_ypos_q_reg[4]_i_1_n_6 ;\n wire \\fb_ypos_q_reg[4]_i_1_n_7 ;\n wire \\fb_ypos_q_reg[8]_i_1_n_1 ;\n wire \\fb_ypos_q_reg[8]_i_1_n_2 ;\n wire \\fb_ypos_q_reg[8]_i_1_n_3 ;\n wire \\fb_ypos_q_reg[8]_i_1_n_4 ;\n wire \\fb_ypos_q_reg[8]_i_1_n_5 ;\n wire \\fb_ypos_q_reg[8]_i_1_n_6 ;\n wire \\fb_ypos_q_reg[8]_i_1_n_7 ;\n wire int_address_q;\n wire \\int_address_q[11]_i_2_n_0 ;\n wire \\int_address_q[11]_i_3_n_0 ;\n wire \\int_address_q[11]_i_4_n_0 ;\n wire \\int_address_q[11]_i_5__0_n_0 ;\n wire \\int_address_q[15]_i_2_n_0 ;\n wire \\int_address_q[15]_i_3_n_0 ;\n wire \\int_address_q[15]_i_4_n_0 ;\n wire \\int_address_q[15]_i_5_n_0 ;\n wire \\int_address_q[19]_i_2_n_0 ;\n wire \\int_address_q[19]_i_3_n_0 ;\n wire \\int_address_q[19]_i_4_n_0 ;\n wire \\int_address_q[19]_i_5_n_0 ;\n wire \\int_address_q[23]_i_2_n_0 ;\n wire \\int_address_q[7]_i_3__0_n_0 ;\n wire \\int_address_q[7]_i_4__0_n_0 ;\n wire \\int_address_q[7]_i_5__0_n_0 ;\n wire \\int_address_q[7]_i_6_n_0 ;\n wire \\int_address_q_reg[11]_i_1_n_0 ;\n wire \\int_address_q_reg[11]_i_1_n_1 ;\n wire \\int_address_q_reg[11]_i_1_n_2 ;\n wire \\int_address_q_reg[11]_i_1_n_3 ;\n wire \\int_address_q_reg[11]_i_1_n_4 ;\n wire \\int_address_q_reg[11]_i_1_n_5 ;\n wire \\int_address_q_reg[11]_i_1_n_6 ;\n wire \\int_address_q_reg[11]_i_1_n_7 ;\n wire \\int_address_q_reg[15]_i_1_n_0 ;\n wire \\int_address_q_reg[15]_i_1_n_1 ;\n wire \\int_address_q_reg[15]_i_1_n_2 ;\n wire \\int_address_q_reg[15]_i_1_n_3 ;\n wire \\int_address_q_reg[15]_i_1_n_4 ;\n wire \\int_address_q_reg[15]_i_1_n_5 ;\n wire \\int_address_q_reg[15]_i_1_n_6 ;\n wire \\int_address_q_reg[15]_i_1_n_7 ;\n wire \\int_address_q_reg[19]_i_1_n_0 ;\n wire \\int_address_q_reg[19]_i_1_n_1 ;\n wire \\int_address_q_reg[19]_i_1_n_2 ;\n wire \\int_address_q_reg[19]_i_1_n_3 ;\n wire \\int_address_q_reg[19]_i_1_n_4 ;\n wire \\int_address_q_reg[19]_i_1_n_5 ;\n wire \\int_address_q_reg[19]_i_1_n_6 ;\n wire \\int_address_q_reg[19]_i_1_n_7 ;\n wire \\int_address_q_reg[23]_i_1_n_7 ;\n wire \\int_address_q_reg[7]_i_2_n_0 ;\n wire \\int_address_q_reg[7]_i_2_n_1 ;\n wire \\int_address_q_reg[7]_i_2_n_2 ;\n wire \\int_address_q_reg[7]_i_2_n_3 ;\n wire \\int_address_q_reg[7]_i_2_n_4 ;\n wire \\int_address_q_reg[7]_i_2_n_5 ;\n wire \\int_address_q_reg[7]_i_2_n_6 ;\n wire \\int_address_q_reg[7]_i_2_n_7 ;\n wire [2:0]out;\n wire rst;\n wire [16:0]s_axi_awaddr;\n wire ui_clk;\n wire [3:0]\\NLW_fb_xpos_q_reg[11]_i_1_CO_UNCONNECTED ;\n wire [3:1]\\NLW_fb_xpos_q_reg[11]_i_1_O_UNCONNECTED ;\n wire [3:3]\\NLW_fb_ypos_q_reg[8]_i_1_CO_UNCONNECTED ;\n wire [3:0]\\NLW_int_address_q_reg[23]_i_1_CO_UNCONNECTED ;\n wire [3:1]\\NLW_int_address_q_reg[23]_i_1_O_UNCONNECTED ;\n\n LUT6 #(\n .INIT(64'h7FFFFFFFFFFFFFFF)) \n \\FSM_sequential_write_state[2]_i_3 \n (.I0(s_axi_awaddr[12]),\n .I1(s_axi_awaddr[10]),\n .I2(s_axi_awaddr[15]),\n .I3(s_axi_awaddr[11]),\n .I4(s_axi_awaddr[14]),\n .I5(s_axi_awaddr[13]),\n .O(\\FSM_sequential_write_state_reg[0] ));\n LUT6 #(\n .INIT(64'h000000005555555D)) \n \\FSM_sequential_write_state[2]_i_4 \n (.I0(s_axi_awaddr[8]),\n .I1(\\FSM_sequential_write_state[2]_i_6_n_0 ),\n .I2(s_axi_awaddr[6]),\n .I3(s_axi_awaddr[5]),\n .I4(s_axi_awaddr[7]),\n .I5(s_axi_awaddr[9]),\n .O(\\FSM_sequential_write_state_reg[0]_0 ));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\FSM_sequential_write_state[2]_i_6 \n (.I0(s_axi_awaddr[2]),\n .I1(s_axi_awaddr[3]),\n .I2(s_axi_awaddr[4]),\n .I3(s_axi_awaddr[1]),\n .O(\\FSM_sequential_write_state[2]_i_6_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_xpos_q[11]_i_2 \n (.I0(fb_xpos_q_reg[11]),\n .O(\\fb_xpos_q[11]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h00000004)) \n \\fb_xpos_q[7]_i_1 \n (.I0(rst),\n .I1(out[2]),\n .I2(out[0]),\n .I3(out[1]),\n .I4(\\fb_ypos_q[0]_i_3_n_0 ),\n .O(fb_xpos_q));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_xpos_q[7]_i_3 \n (.I0(fb_xpos_q_reg[10]),\n .O(\\fb_xpos_q[7]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_xpos_q[7]_i_4 \n (.I0(fb_xpos_q_reg[9]),\n .O(\\fb_xpos_q[7]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_xpos_q[7]_i_5 \n (.I0(fb_xpos_q_reg[8]),\n .O(\\fb_xpos_q[7]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\fb_xpos_q[7]_i_6 \n (.I0(fb_xpos_q_reg[7]),\n .O(\\fb_xpos_q[7]_i_6_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\fb_xpos_q_reg[10] \n (.C(ui_clk),\n .CE(fb_xpos_q),\n .D(\\fb_xpos_q_reg[7]_i_2_n_4 ),\n .Q(fb_xpos_q_reg[10]),\n .R(\\fb_ypos_q[0]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\fb_xpos_q_reg[11] \n (.C(ui_clk),\n .CE(fb_xpos_q),\n .D(\\fb_xpos_q_reg[11]_i_1_n_7 ),\n .Q(fb_xpos_q_reg[11]),\n .R(\\fb_ypos_q[0]_i_1_n_0 ));\n CARRY4 \\fb_xpos_q_reg[11]_i_1 \n (.CI(\\fb_xpos_q_reg[7]_i_2_n_0 ),\n .CO(\\NLW_fb_xpos_q_reg[11]_i_1_CO_UNCONNECTED [3:0]),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\NLW_fb_xpos_q_reg[11]_i_1_O_UNCONNECTED [3:1],\\fb_xpos_q_reg[11]_i_1_n_7 }),\n .S({1'b0,1'b0,1'b0,\\fb_xpos_q[11]_i_2_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\fb_xpos_q_reg[7] \n (.C(ui_clk),\n .CE(fb_xpos_q),\n .D(\\fb_xpos_q_reg[7]_i_2_n_7 ),\n .Q(fb_xpos_q_reg[7]),\n .R(\\fb_ypos_q[0]_i_1_n_0 ));\n CARRY4 \\fb_xpos_q_reg[7]_i_2 \n (.CI(1'b0),\n .CO({\\fb_xpos_q_reg[7]_i_2_n_0 ,\\fb_xpos_q_reg[7]_i_2_n_1 ,\\fb_xpos_q_reg[7]_i_2_n_2 ,\\fb_xpos_q_reg[7]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b1}),\n .O({\\fb_xpos_q_reg[7]_i_2_n_4 ,\\fb_xpos_q_reg[7]_i_2_n_5 ,\\fb_xpos_q_reg[7]_i_2_n_6 ,\\fb_xpos_q_reg[7]_i_2_n_7 }),\n .S({\\fb_xpos_q[7]_i_3_n_0 ,\\fb_xpos_q[7]_i_4_n_0 ,\\fb_xpos_q[7]_i_5_n_0 ,\\fb_xpos_q[7]_i_6_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\fb_xpos_q_reg[8] \n (.C(ui_clk),\n .CE(fb_xpos_q),\n .D(\\fb_xpos_q_reg[7]_i_2_n_6 ),\n .Q(fb_xpos_q_reg[8]),\n .R(\\fb_ypos_q[0]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\fb_xpos_q_reg[9] \n (.C(ui_clk),\n .CE(fb_xpos_q),\n .D(\\fb_xpos_q_reg[7]_i_2_n_5 ),\n .Q(fb_xpos_q_reg[9]),\n .R(\\fb_ypos_q[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000040000)) \n \\fb_ypos_q[0]_i_1 \n (.I0(rst),\n .I1(out[2]),\n .I2(out[0]),\n .I3(out[1]),\n .I4(\\fb_ypos_q[0]_i_3_n_0 ),\n .I5(\\fb_ypos_q[0]_i_4_n_0 ),\n .O(\\fb_ypos_q[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h00007FFF)) \n \\fb_ypos_q[0]_i_10 \n (.I0(fb_ypos_q_reg[0]),\n .I1(fb_ypos_q_reg[1]),\n .I2(fb_ypos_q_reg[3]),\n .I3(fb_ypos_q_reg[2]),\n .I4(fb_ypos_q_reg[4]),\n .O(\\fb_ypos_q[0]_i_10_n_0 ));\n LUT5 #(\n .INIT(32'hE0000000)) \n \\fb_ypos_q[0]_i_3 \n (.I0(fb_xpos_q_reg[7]),\n .I1(fb_xpos_q_reg[8]),\n .I2(fb_xpos_q_reg[9]),\n .I3(fb_xpos_q_reg[10]),\n .I4(fb_xpos_q_reg[11]),\n .O(\\fb_ypos_q[0]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'h8A888888)) \n \\fb_ypos_q[0]_i_4 \n (.I0(fb_ypos_q_reg[11]),\n .I1(\\fb_ypos_q[0]_i_9_n_0 ),\n .I2(\\fb_ypos_q[0]_i_10_n_0 ),\n .I3(fb_ypos_q_reg[5]),\n .I4(fb_ypos_q_reg[6]),\n .O(\\fb_ypos_q[0]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_ypos_q[0]_i_5 \n (.I0(fb_ypos_q_reg[3]),\n .O(\\fb_ypos_q[0]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_ypos_q[0]_i_6 \n (.I0(fb_ypos_q_reg[2]),\n .O(\\fb_ypos_q[0]_i_6_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_ypos_q[0]_i_7 \n (.I0(fb_ypos_q_reg[1]),\n .O(\\fb_ypos_q[0]_i_7_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\fb_ypos_q[0]_i_8 \n (.I0(fb_ypos_q_reg[0]),\n .O(\\fb_ypos_q[0]_i_8_n_0 ));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\fb_ypos_q[0]_i_9 \n (.I0(fb_ypos_q_reg[7]),\n .I1(fb_ypos_q_reg[10]),\n .I2(fb_ypos_q_reg[9]),\n .I3(fb_ypos_q_reg[8]),\n .O(\\fb_ypos_q[0]_i_9_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_ypos_q[4]_i_2 \n (.I0(fb_ypos_q_reg[7]),\n .O(\\fb_ypos_q[4]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_ypos_q[4]_i_3 \n (.I0(fb_ypos_q_reg[6]),\n .O(\\fb_ypos_q[4]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_ypos_q[4]_i_4 \n (.I0(fb_ypos_q_reg[5]),\n .O(\\fb_ypos_q[4]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_ypos_q[4]_i_5 \n (.I0(fb_ypos_q_reg[4]),\n .O(\\fb_ypos_q[4]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_ypos_q[8]_i_2 \n (.I0(fb_ypos_q_reg[11]),\n .O(\\fb_ypos_q[8]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_ypos_q[8]_i_3 \n (.I0(fb_ypos_q_reg[10]),\n .O(\\fb_ypos_q[8]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_ypos_q[8]_i_4 \n (.I0(fb_ypos_q_reg[9]),\n .O(\\fb_ypos_q[8]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_ypos_q[8]_i_5 \n (.I0(fb_ypos_q_reg[8]),\n .O(\\fb_ypos_q[8]_i_5_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[0] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[0]_i_1_n_0 ),\n .D(\\fb_ypos_q_reg[0]_i_2_n_7 ),\n .Q(fb_ypos_q_reg[0]),\n .R(1'b0));\n CARRY4 \\fb_ypos_q_reg[0]_i_2 \n (.CI(1'b0),\n .CO({\\fb_ypos_q_reg[0]_i_2_n_0 ,\\fb_ypos_q_reg[0]_i_2_n_1 ,\\fb_ypos_q_reg[0]_i_2_n_2 ,\\fb_ypos_q_reg[0]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b1}),\n .O({\\fb_ypos_q_reg[0]_i_2_n_4 ,\\fb_ypos_q_reg[0]_i_2_n_5 ,\\fb_ypos_q_reg[0]_i_2_n_6 ,\\fb_ypos_q_reg[0]_i_2_n_7 }),\n .S({\\fb_ypos_q[0]_i_5_n_0 ,\\fb_ypos_q[0]_i_6_n_0 ,\\fb_ypos_q[0]_i_7_n_0 ,\\fb_ypos_q[0]_i_8_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[10] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[0]_i_1_n_0 ),\n .D(\\fb_ypos_q_reg[8]_i_1_n_5 ),\n .Q(fb_ypos_q_reg[10]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[11] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[0]_i_1_n_0 ),\n .D(\\fb_ypos_q_reg[8]_i_1_n_4 ),\n .Q(fb_ypos_q_reg[11]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[1] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[0]_i_1_n_0 ),\n .D(\\fb_ypos_q_reg[0]_i_2_n_6 ),\n .Q(fb_ypos_q_reg[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[2] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[0]_i_1_n_0 ),\n .D(\\fb_ypos_q_reg[0]_i_2_n_5 ),\n .Q(fb_ypos_q_reg[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[3] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[0]_i_1_n_0 ),\n .D(\\fb_ypos_q_reg[0]_i_2_n_4 ),\n .Q(fb_ypos_q_reg[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[4] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[0]_i_1_n_0 ),\n .D(\\fb_ypos_q_reg[4]_i_1_n_7 ),\n .Q(fb_ypos_q_reg[4]),\n .R(1'b0));\n CARRY4 \\fb_ypos_q_reg[4]_i_1 \n (.CI(\\fb_ypos_q_reg[0]_i_2_n_0 ),\n .CO({\\fb_ypos_q_reg[4]_i_1_n_0 ,\\fb_ypos_q_reg[4]_i_1_n_1 ,\\fb_ypos_q_reg[4]_i_1_n_2 ,\\fb_ypos_q_reg[4]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\fb_ypos_q_reg[4]_i_1_n_4 ,\\fb_ypos_q_reg[4]_i_1_n_5 ,\\fb_ypos_q_reg[4]_i_1_n_6 ,\\fb_ypos_q_reg[4]_i_1_n_7 }),\n .S({\\fb_ypos_q[4]_i_2_n_0 ,\\fb_ypos_q[4]_i_3_n_0 ,\\fb_ypos_q[4]_i_4_n_0 ,\\fb_ypos_q[4]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[5] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[0]_i_1_n_0 ),\n .D(\\fb_ypos_q_reg[4]_i_1_n_6 ),\n .Q(fb_ypos_q_reg[5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[6] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[0]_i_1_n_0 ),\n .D(\\fb_ypos_q_reg[4]_i_1_n_5 ),\n .Q(fb_ypos_q_reg[6]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[7] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[0]_i_1_n_0 ),\n .D(\\fb_ypos_q_reg[4]_i_1_n_4 ),\n .Q(fb_ypos_q_reg[7]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[8] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[0]_i_1_n_0 ),\n .D(\\fb_ypos_q_reg[8]_i_1_n_7 ),\n .Q(fb_ypos_q_reg[8]),\n .R(1'b0));\n CARRY4 \\fb_ypos_q_reg[8]_i_1 \n (.CI(\\fb_ypos_q_reg[4]_i_1_n_0 ),\n .CO({\\NLW_fb_ypos_q_reg[8]_i_1_CO_UNCONNECTED [3],\\fb_ypos_q_reg[8]_i_1_n_1 ,\\fb_ypos_q_reg[8]_i_1_n_2 ,\\fb_ypos_q_reg[8]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\fb_ypos_q_reg[8]_i_1_n_4 ,\\fb_ypos_q_reg[8]_i_1_n_5 ,\\fb_ypos_q_reg[8]_i_1_n_6 ,\\fb_ypos_q_reg[8]_i_1_n_7 }),\n .S({\\fb_ypos_q[8]_i_2_n_0 ,\\fb_ypos_q[8]_i_3_n_0 ,\\fb_ypos_q[8]_i_4_n_0 ,\\fb_ypos_q[8]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[9] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[0]_i_1_n_0 ),\n .D(\\fb_ypos_q_reg[8]_i_1_n_6 ),\n .Q(fb_ypos_q_reg[9]),\n .R(1'b0));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[11]_i_2 \n (.I0(s_axi_awaddr[7]),\n .O(\\int_address_q[11]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[11]_i_3 \n (.I0(s_axi_awaddr[6]),\n .O(\\int_address_q[11]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[11]_i_4 \n (.I0(s_axi_awaddr[5]),\n .O(\\int_address_q[11]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[11]_i_5__0 \n (.I0(s_axi_awaddr[4]),\n .O(\\int_address_q[11]_i_5__0_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[15]_i_2 \n (.I0(s_axi_awaddr[11]),\n .O(\\int_address_q[15]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[15]_i_3 \n (.I0(s_axi_awaddr[10]),\n .O(\\int_address_q[15]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[15]_i_4 \n (.I0(s_axi_awaddr[9]),\n .O(\\int_address_q[15]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[15]_i_5 \n (.I0(s_axi_awaddr[8]),\n .O(\\int_address_q[15]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[19]_i_2 \n (.I0(s_axi_awaddr[15]),\n .O(\\int_address_q[19]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[19]_i_3 \n (.I0(s_axi_awaddr[14]),\n .O(\\int_address_q[19]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[19]_i_4 \n (.I0(s_axi_awaddr[13]),\n .O(\\int_address_q[19]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[19]_i_5 \n (.I0(s_axi_awaddr[12]),\n .O(\\int_address_q[19]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[23]_i_2 \n (.I0(s_axi_awaddr[16]),\n .O(\\int_address_q[23]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h00101010)) \n \\int_address_q[7]_i_1 \n (.I0(out[1]),\n .I1(out[0]),\n .I2(out[2]),\n .I3(\\fb_ypos_q[0]_i_3_n_0 ),\n .I4(\\fb_ypos_q[0]_i_4_n_0 ),\n .O(int_address_q));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[7]_i_3__0 \n (.I0(s_axi_awaddr[3]),\n .O(\\int_address_q[7]_i_3__0_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[7]_i_4__0 \n (.I0(s_axi_awaddr[2]),\n .O(\\int_address_q[7]_i_4__0_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[7]_i_5__0 \n (.I0(s_axi_awaddr[1]),\n .O(\\int_address_q[7]_i_5__0_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\int_address_q[7]_i_6 \n (.I0(s_axi_awaddr[0]),\n .O(\\int_address_q[7]_i_6_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[10] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[7]_i_2_n_4 ),\n .Q(s_axi_awaddr[3]),\n .R(rst));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[11] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[11]_i_1_n_7 ),\n .Q(s_axi_awaddr[4]),\n .R(rst));\n CARRY4 \\int_address_q_reg[11]_i_1 \n (.CI(\\int_address_q_reg[7]_i_2_n_0 ),\n .CO({\\int_address_q_reg[11]_i_1_n_0 ,\\int_address_q_reg[11]_i_1_n_1 ,\\int_address_q_reg[11]_i_1_n_2 ,\\int_address_q_reg[11]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\int_address_q_reg[11]_i_1_n_4 ,\\int_address_q_reg[11]_i_1_n_5 ,\\int_address_q_reg[11]_i_1_n_6 ,\\int_address_q_reg[11]_i_1_n_7 }),\n .S({\\int_address_q[11]_i_2_n_0 ,\\int_address_q[11]_i_3_n_0 ,\\int_address_q[11]_i_4_n_0 ,\\int_address_q[11]_i_5__0_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[12] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[11]_i_1_n_6 ),\n .Q(s_axi_awaddr[5]),\n .R(rst));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[13] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[11]_i_1_n_5 ),\n .Q(s_axi_awaddr[6]),\n .R(rst));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[14] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[11]_i_1_n_4 ),\n .Q(s_axi_awaddr[7]),\n .R(rst));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[15] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[15]_i_1_n_7 ),\n .Q(s_axi_awaddr[8]),\n .R(rst));\n CARRY4 \\int_address_q_reg[15]_i_1 \n (.CI(\\int_address_q_reg[11]_i_1_n_0 ),\n .CO({\\int_address_q_reg[15]_i_1_n_0 ,\\int_address_q_reg[15]_i_1_n_1 ,\\int_address_q_reg[15]_i_1_n_2 ,\\int_address_q_reg[15]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\int_address_q_reg[15]_i_1_n_4 ,\\int_address_q_reg[15]_i_1_n_5 ,\\int_address_q_reg[15]_i_1_n_6 ,\\int_address_q_reg[15]_i_1_n_7 }),\n .S({\\int_address_q[15]_i_2_n_0 ,\\int_address_q[15]_i_3_n_0 ,\\int_address_q[15]_i_4_n_0 ,\\int_address_q[15]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[16] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[15]_i_1_n_6 ),\n .Q(s_axi_awaddr[9]),\n .R(rst));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[17] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[15]_i_1_n_5 ),\n .Q(s_axi_awaddr[10]),\n .R(rst));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[18] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[15]_i_1_n_4 ),\n .Q(s_axi_awaddr[11]),\n .R(rst));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[19] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[19]_i_1_n_7 ),\n .Q(s_axi_awaddr[12]),\n .R(rst));\n CARRY4 \\int_address_q_reg[19]_i_1 \n (.CI(\\int_address_q_reg[15]_i_1_n_0 ),\n .CO({\\int_address_q_reg[19]_i_1_n_0 ,\\int_address_q_reg[19]_i_1_n_1 ,\\int_address_q_reg[19]_i_1_n_2 ,\\int_address_q_reg[19]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\int_address_q_reg[19]_i_1_n_4 ,\\int_address_q_reg[19]_i_1_n_5 ,\\int_address_q_reg[19]_i_1_n_6 ,\\int_address_q_reg[19]_i_1_n_7 }),\n .S({\\int_address_q[19]_i_2_n_0 ,\\int_address_q[19]_i_3_n_0 ,\\int_address_q[19]_i_4_n_0 ,\\int_address_q[19]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[20] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[19]_i_1_n_6 ),\n .Q(s_axi_awaddr[13]),\n .R(rst));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[21] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[19]_i_1_n_5 ),\n .Q(s_axi_awaddr[14]),\n .R(rst));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[22] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[19]_i_1_n_4 ),\n .Q(s_axi_awaddr[15]),\n .R(rst));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[23] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[23]_i_1_n_7 ),\n .Q(s_axi_awaddr[16]),\n .R(rst));\n CARRY4 \\int_address_q_reg[23]_i_1 \n (.CI(\\int_address_q_reg[19]_i_1_n_0 ),\n .CO(\\NLW_int_address_q_reg[23]_i_1_CO_UNCONNECTED [3:0]),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\NLW_int_address_q_reg[23]_i_1_O_UNCONNECTED [3:1],\\int_address_q_reg[23]_i_1_n_7 }),\n .S({1'b0,1'b0,1'b0,\\int_address_q[23]_i_2_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[7] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[7]_i_2_n_7 ),\n .Q(s_axi_awaddr[0]),\n .R(rst));\n CARRY4 \\int_address_q_reg[7]_i_2 \n (.CI(1'b0),\n .CO({\\int_address_q_reg[7]_i_2_n_0 ,\\int_address_q_reg[7]_i_2_n_1 ,\\int_address_q_reg[7]_i_2_n_2 ,\\int_address_q_reg[7]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b1}),\n .O({\\int_address_q_reg[7]_i_2_n_4 ,\\int_address_q_reg[7]_i_2_n_5 ,\\int_address_q_reg[7]_i_2_n_6 ,\\int_address_q_reg[7]_i_2_n_7 }),\n .S({\\int_address_q[7]_i_3__0_n_0 ,\\int_address_q[7]_i_4__0_n_0 ,\\int_address_q[7]_i_5__0_n_0 ,\\int_address_q[7]_i_6_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[8] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[7]_i_2_n_6 ),\n .Q(s_axi_awaddr[1]),\n .R(rst));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[9] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[7]_i_2_n_5 ),\n .Q(s_axi_awaddr[2]),\n .R(rst));\nendmodule\n\n(* ORIG_REF_NAME = \"framebuffer_addr_ctrl\" *) \nmodule framebuffer_addr_ctrl__parameterized0\n (int_address_q_reg,\n \\read_state_reg[0] ,\n ui_clk,\n \\v_pos_reg[4] ,\n Q,\n zoom_mode_IBUF,\n prog_full);\n output [16:0]int_address_q_reg;\n output \\read_state_reg[0] ;\n input ui_clk;\n input \\v_pos_reg[4] ;\n input [1:0]Q;\n input zoom_mode_IBUF;\n input prog_full;\n\n wire [1:0]Q;\n wire \\fb_xpos_q[11]_i_2__0_n_0 ;\n wire \\fb_xpos_q[7]_i_1__1_n_0 ;\n wire \\fb_xpos_q[7]_i_3__0_n_0 ;\n wire \\fb_xpos_q[7]_i_4__0_n_0 ;\n wire \\fb_xpos_q[7]_i_5__0_n_0 ;\n wire \\fb_xpos_q[7]_i_6__0_n_0 ;\n wire [11:7]fb_xpos_q_reg;\n wire \\fb_xpos_q_reg[11]_i_1__0_n_7 ;\n wire \\fb_xpos_q_reg[7]_i_2__0_n_0 ;\n wire \\fb_xpos_q_reg[7]_i_2__0_n_1 ;\n wire \\fb_xpos_q_reg[7]_i_2__0_n_2 ;\n wire \\fb_xpos_q_reg[7]_i_2__0_n_3 ;\n wire \\fb_xpos_q_reg[7]_i_2__0_n_4 ;\n wire \\fb_xpos_q_reg[7]_i_2__0_n_5 ;\n wire \\fb_xpos_q_reg[7]_i_2__0_n_6 ;\n wire \\fb_xpos_q_reg[7]_i_2__0_n_7 ;\n wire \\fb_ypos_q[1]_i_1_n_0 ;\n wire \\fb_ypos_q[1]_i_3_n_0 ;\n wire \\fb_ypos_q[1]_i_4_n_0 ;\n wire \\fb_ypos_q[1]_i_5_n_0 ;\n wire \\fb_ypos_q[1]_i_6_n_0 ;\n wire \\fb_ypos_q[1]_i_7_n_0 ;\n wire \\fb_ypos_q[1]_i_8_n_0 ;\n wire \\fb_ypos_q[1]_i_9_n_0 ;\n wire \\fb_ypos_q[5]_i_2_n_0 ;\n wire \\fb_ypos_q[5]_i_3_n_0 ;\n wire \\fb_ypos_q[5]_i_4_n_0 ;\n wire \\fb_ypos_q[5]_i_5_n_0 ;\n wire \\fb_ypos_q[9]_i_2_n_0 ;\n wire \\fb_ypos_q[9]_i_3_n_0 ;\n wire \\fb_ypos_q[9]_i_4_n_0 ;\n wire [11:1]fb_ypos_q_reg;\n wire \\fb_ypos_q_reg[1]_i_2_n_0 ;\n wire \\fb_ypos_q_reg[1]_i_2_n_1 ;\n wire \\fb_ypos_q_reg[1]_i_2_n_2 ;\n wire \\fb_ypos_q_reg[1]_i_2_n_3 ;\n wire \\fb_ypos_q_reg[1]_i_2_n_4 ;\n wire \\fb_ypos_q_reg[1]_i_2_n_5 ;\n wire \\fb_ypos_q_reg[1]_i_2_n_6 ;\n wire \\fb_ypos_q_reg[1]_i_2_n_7 ;\n wire \\fb_ypos_q_reg[5]_i_1_n_0 ;\n wire \\fb_ypos_q_reg[5]_i_1_n_1 ;\n wire \\fb_ypos_q_reg[5]_i_1_n_2 ;\n wire \\fb_ypos_q_reg[5]_i_1_n_3 ;\n wire \\fb_ypos_q_reg[5]_i_1_n_4 ;\n wire \\fb_ypos_q_reg[5]_i_1_n_5 ;\n wire \\fb_ypos_q_reg[5]_i_1_n_6 ;\n wire \\fb_ypos_q_reg[5]_i_1_n_7 ;\n wire \\fb_ypos_q_reg[9]_i_1_n_2 ;\n wire \\fb_ypos_q_reg[9]_i_1_n_3 ;\n wire \\fb_ypos_q_reg[9]_i_1_n_5 ;\n wire \\fb_ypos_q_reg[9]_i_1_n_6 ;\n wire \\fb_ypos_q_reg[9]_i_1_n_7 ;\n wire int_address_q;\n wire \\int_address_q[11]_i_2__0_n_0 ;\n wire \\int_address_q[11]_i_3__0_n_0 ;\n wire \\int_address_q[11]_i_4__0_n_0 ;\n wire \\int_address_q[11]_i_5_n_0 ;\n wire \\int_address_q[15]_i_2__0_n_0 ;\n wire \\int_address_q[15]_i_3__0_n_0 ;\n wire \\int_address_q[15]_i_4__0_n_0 ;\n wire \\int_address_q[15]_i_5__0_n_0 ;\n wire \\int_address_q[19]_i_2__0_n_0 ;\n wire \\int_address_q[19]_i_3__0_n_0 ;\n wire \\int_address_q[19]_i_4__0_n_0 ;\n wire \\int_address_q[19]_i_5__0_n_0 ;\n wire \\int_address_q[23]_i_2__0_n_0 ;\n wire \\int_address_q[7]_i_3_n_0 ;\n wire \\int_address_q[7]_i_4_n_0 ;\n wire \\int_address_q[7]_i_5_n_0 ;\n wire \\int_address_q[7]_i_6__0_n_0 ;\n wire [16:0]int_address_q_reg;\n wire \\int_address_q_reg[11]_i_1__0_n_0 ;\n wire \\int_address_q_reg[11]_i_1__0_n_1 ;\n wire \\int_address_q_reg[11]_i_1__0_n_2 ;\n wire \\int_address_q_reg[11]_i_1__0_n_3 ;\n wire \\int_address_q_reg[11]_i_1__0_n_4 ;\n wire \\int_address_q_reg[11]_i_1__0_n_5 ;\n wire \\int_address_q_reg[11]_i_1__0_n_6 ;\n wire \\int_address_q_reg[11]_i_1__0_n_7 ;\n wire \\int_address_q_reg[15]_i_1__0_n_0 ;\n wire \\int_address_q_reg[15]_i_1__0_n_1 ;\n wire \\int_address_q_reg[15]_i_1__0_n_2 ;\n wire \\int_address_q_reg[15]_i_1__0_n_3 ;\n wire \\int_address_q_reg[15]_i_1__0_n_4 ;\n wire \\int_address_q_reg[15]_i_1__0_n_5 ;\n wire \\int_address_q_reg[15]_i_1__0_n_6 ;\n wire \\int_address_q_reg[15]_i_1__0_n_7 ;\n wire \\int_address_q_reg[19]_i_1__0_n_0 ;\n wire \\int_address_q_reg[19]_i_1__0_n_1 ;\n wire \\int_address_q_reg[19]_i_1__0_n_2 ;\n wire \\int_address_q_reg[19]_i_1__0_n_3 ;\n wire \\int_address_q_reg[19]_i_1__0_n_4 ;\n wire \\int_address_q_reg[19]_i_1__0_n_5 ;\n wire \\int_address_q_reg[19]_i_1__0_n_6 ;\n wire \\int_address_q_reg[19]_i_1__0_n_7 ;\n wire \\int_address_q_reg[23]_i_1__0_n_7 ;\n wire \\int_address_q_reg[7]_i_2__0_n_0 ;\n wire \\int_address_q_reg[7]_i_2__0_n_1 ;\n wire \\int_address_q_reg[7]_i_2__0_n_2 ;\n wire \\int_address_q_reg[7]_i_2__0_n_3 ;\n wire \\int_address_q_reg[7]_i_2__0_n_4 ;\n wire \\int_address_q_reg[7]_i_2__0_n_5 ;\n wire \\int_address_q_reg[7]_i_2__0_n_6 ;\n wire \\int_address_q_reg[7]_i_2__0_n_7 ;\n wire prog_full;\n wire \\read_state[1]_i_8_n_0 ;\n wire \\read_state[1]_i_9_n_0 ;\n wire \\read_state_reg[0] ;\n wire ui_clk;\n wire \\v_pos_reg[4] ;\n wire zoom_mode_IBUF;\n wire [3:0]\\NLW_fb_xpos_q_reg[11]_i_1__0_CO_UNCONNECTED ;\n wire [3:1]\\NLW_fb_xpos_q_reg[11]_i_1__0_O_UNCONNECTED ;\n wire [3:2]\\NLW_fb_ypos_q_reg[9]_i_1_CO_UNCONNECTED ;\n wire [3:3]\\NLW_fb_ypos_q_reg[9]_i_1_O_UNCONNECTED ;\n wire [3:0]\\NLW_int_address_q_reg[23]_i_1__0_CO_UNCONNECTED ;\n wire [3:1]\\NLW_int_address_q_reg[23]_i_1__0_O_UNCONNECTED ;\n\n LUT1 #(\n .INIT(2'h2)) \n \\fb_xpos_q[11]_i_2__0 \n (.I0(fb_xpos_q_reg[11]),\n .O(\\fb_xpos_q[11]_i_2__0_n_0 ));\n LUT4 #(\n .INIT(16'h0040)) \n \\fb_xpos_q[7]_i_1__1 \n (.I0(\\fb_ypos_q[1]_i_3_n_0 ),\n .I1(Q[0]),\n .I2(Q[1]),\n .I3(\\v_pos_reg[4] ),\n .O(\\fb_xpos_q[7]_i_1__1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_xpos_q[7]_i_3__0 \n (.I0(fb_xpos_q_reg[10]),\n .O(\\fb_xpos_q[7]_i_3__0_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_xpos_q[7]_i_4__0 \n (.I0(fb_xpos_q_reg[9]),\n .O(\\fb_xpos_q[7]_i_4__0_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_xpos_q[7]_i_5__0 \n (.I0(fb_xpos_q_reg[8]),\n .O(\\fb_xpos_q[7]_i_5__0_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\fb_xpos_q[7]_i_6__0 \n (.I0(fb_xpos_q_reg[7]),\n .O(\\fb_xpos_q[7]_i_6__0_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\fb_xpos_q_reg[10] \n (.C(ui_clk),\n .CE(\\fb_xpos_q[7]_i_1__1_n_0 ),\n .D(\\fb_xpos_q_reg[7]_i_2__0_n_4 ),\n .Q(fb_xpos_q_reg[10]),\n .R(\\fb_ypos_q[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\fb_xpos_q_reg[11] \n (.C(ui_clk),\n .CE(\\fb_xpos_q[7]_i_1__1_n_0 ),\n .D(\\fb_xpos_q_reg[11]_i_1__0_n_7 ),\n .Q(fb_xpos_q_reg[11]),\n .R(\\fb_ypos_q[1]_i_1_n_0 ));\n CARRY4 \\fb_xpos_q_reg[11]_i_1__0 \n (.CI(\\fb_xpos_q_reg[7]_i_2__0_n_0 ),\n .CO(\\NLW_fb_xpos_q_reg[11]_i_1__0_CO_UNCONNECTED [3:0]),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\NLW_fb_xpos_q_reg[11]_i_1__0_O_UNCONNECTED [3:1],\\fb_xpos_q_reg[11]_i_1__0_n_7 }),\n .S({1'b0,1'b0,1'b0,\\fb_xpos_q[11]_i_2__0_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\fb_xpos_q_reg[7] \n (.C(ui_clk),\n .CE(\\fb_xpos_q[7]_i_1__1_n_0 ),\n .D(\\fb_xpos_q_reg[7]_i_2__0_n_7 ),\n .Q(fb_xpos_q_reg[7]),\n .R(\\fb_ypos_q[1]_i_1_n_0 ));\n CARRY4 \\fb_xpos_q_reg[7]_i_2__0 \n (.CI(1'b0),\n .CO({\\fb_xpos_q_reg[7]_i_2__0_n_0 ,\\fb_xpos_q_reg[7]_i_2__0_n_1 ,\\fb_xpos_q_reg[7]_i_2__0_n_2 ,\\fb_xpos_q_reg[7]_i_2__0_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b1}),\n .O({\\fb_xpos_q_reg[7]_i_2__0_n_4 ,\\fb_xpos_q_reg[7]_i_2__0_n_5 ,\\fb_xpos_q_reg[7]_i_2__0_n_6 ,\\fb_xpos_q_reg[7]_i_2__0_n_7 }),\n .S({\\fb_xpos_q[7]_i_3__0_n_0 ,\\fb_xpos_q[7]_i_4__0_n_0 ,\\fb_xpos_q[7]_i_5__0_n_0 ,\\fb_xpos_q[7]_i_6__0_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\fb_xpos_q_reg[8] \n (.C(ui_clk),\n .CE(\\fb_xpos_q[7]_i_1__1_n_0 ),\n .D(\\fb_xpos_q_reg[7]_i_2__0_n_6 ),\n .Q(fb_xpos_q_reg[8]),\n .R(\\fb_ypos_q[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\fb_xpos_q_reg[9] \n (.C(ui_clk),\n .CE(\\fb_xpos_q[7]_i_1__1_n_0 ),\n .D(\\fb_xpos_q_reg[7]_i_2__0_n_5 ),\n .Q(fb_xpos_q_reg[9]),\n .R(\\fb_ypos_q[1]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h00000800)) \n \\fb_ypos_q[1]_i_1 \n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(\\v_pos_reg[4] ),\n .I3(\\fb_ypos_q[1]_i_3_n_0 ),\n .I4(\\fb_ypos_q[1]_i_4_n_0 ),\n .O(\\fb_ypos_q[1]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hE0000000)) \n \\fb_ypos_q[1]_i_3 \n (.I0(fb_xpos_q_reg[7]),\n .I1(fb_xpos_q_reg[8]),\n .I2(fb_xpos_q_reg[9]),\n .I3(fb_xpos_q_reg[10]),\n .I4(fb_xpos_q_reg[11]),\n .O(\\fb_ypos_q[1]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAA8AAAAAAAA)) \n \\fb_ypos_q[1]_i_4 \n (.I0(fb_ypos_q_reg[11]),\n .I1(fb_ypos_q_reg[8]),\n .I2(fb_ypos_q_reg[7]),\n .I3(fb_ypos_q_reg[9]),\n .I4(fb_ypos_q_reg[10]),\n .I5(\\fb_ypos_q[1]_i_9_n_0 ),\n .O(\\fb_ypos_q[1]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_ypos_q[1]_i_5 \n (.I0(fb_ypos_q_reg[4]),\n .O(\\fb_ypos_q[1]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_ypos_q[1]_i_6 \n (.I0(fb_ypos_q_reg[3]),\n .O(\\fb_ypos_q[1]_i_6_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_ypos_q[1]_i_7 \n (.I0(fb_ypos_q_reg[2]),\n .O(\\fb_ypos_q[1]_i_7_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\fb_ypos_q[1]_i_8 \n (.I0(fb_ypos_q_reg[1]),\n .O(\\fb_ypos_q[1]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'h1555FFFFFFFFFFFF)) \n \\fb_ypos_q[1]_i_9 \n (.I0(fb_ypos_q_reg[4]),\n .I1(fb_ypos_q_reg[1]),\n .I2(fb_ypos_q_reg[2]),\n .I3(fb_ypos_q_reg[3]),\n .I4(fb_ypos_q_reg[5]),\n .I5(fb_ypos_q_reg[6]),\n .O(\\fb_ypos_q[1]_i_9_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_ypos_q[5]_i_2 \n (.I0(fb_ypos_q_reg[8]),\n .O(\\fb_ypos_q[5]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_ypos_q[5]_i_3 \n (.I0(fb_ypos_q_reg[7]),\n .O(\\fb_ypos_q[5]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_ypos_q[5]_i_4 \n (.I0(fb_ypos_q_reg[6]),\n .O(\\fb_ypos_q[5]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_ypos_q[5]_i_5 \n (.I0(fb_ypos_q_reg[5]),\n .O(\\fb_ypos_q[5]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_ypos_q[9]_i_2 \n (.I0(fb_ypos_q_reg[11]),\n .O(\\fb_ypos_q[9]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_ypos_q[9]_i_3 \n (.I0(fb_ypos_q_reg[10]),\n .O(\\fb_ypos_q[9]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_ypos_q[9]_i_4 \n (.I0(fb_ypos_q_reg[9]),\n .O(\\fb_ypos_q[9]_i_4_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[10] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[1]_i_1_n_0 ),\n .D(\\fb_ypos_q_reg[9]_i_1_n_6 ),\n .Q(fb_ypos_q_reg[10]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[11] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[1]_i_1_n_0 ),\n .D(\\fb_ypos_q_reg[9]_i_1_n_5 ),\n .Q(fb_ypos_q_reg[11]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[1] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[1]_i_1_n_0 ),\n .D(\\fb_ypos_q_reg[1]_i_2_n_7 ),\n .Q(fb_ypos_q_reg[1]),\n .R(1'b0));\n CARRY4 \\fb_ypos_q_reg[1]_i_2 \n (.CI(1'b0),\n .CO({\\fb_ypos_q_reg[1]_i_2_n_0 ,\\fb_ypos_q_reg[1]_i_2_n_1 ,\\fb_ypos_q_reg[1]_i_2_n_2 ,\\fb_ypos_q_reg[1]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b1}),\n .O({\\fb_ypos_q_reg[1]_i_2_n_4 ,\\fb_ypos_q_reg[1]_i_2_n_5 ,\\fb_ypos_q_reg[1]_i_2_n_6 ,\\fb_ypos_q_reg[1]_i_2_n_7 }),\n .S({\\fb_ypos_q[1]_i_5_n_0 ,\\fb_ypos_q[1]_i_6_n_0 ,\\fb_ypos_q[1]_i_7_n_0 ,\\fb_ypos_q[1]_i_8_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[2] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[1]_i_1_n_0 ),\n .D(\\fb_ypos_q_reg[1]_i_2_n_6 ),\n .Q(fb_ypos_q_reg[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[3] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[1]_i_1_n_0 ),\n .D(\\fb_ypos_q_reg[1]_i_2_n_5 ),\n .Q(fb_ypos_q_reg[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[4] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[1]_i_1_n_0 ),\n .D(\\fb_ypos_q_reg[1]_i_2_n_4 ),\n .Q(fb_ypos_q_reg[4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[5] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[1]_i_1_n_0 ),\n .D(\\fb_ypos_q_reg[5]_i_1_n_7 ),\n .Q(fb_ypos_q_reg[5]),\n .R(1'b0));\n CARRY4 \\fb_ypos_q_reg[5]_i_1 \n (.CI(\\fb_ypos_q_reg[1]_i_2_n_0 ),\n .CO({\\fb_ypos_q_reg[5]_i_1_n_0 ,\\fb_ypos_q_reg[5]_i_1_n_1 ,\\fb_ypos_q_reg[5]_i_1_n_2 ,\\fb_ypos_q_reg[5]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\fb_ypos_q_reg[5]_i_1_n_4 ,\\fb_ypos_q_reg[5]_i_1_n_5 ,\\fb_ypos_q_reg[5]_i_1_n_6 ,\\fb_ypos_q_reg[5]_i_1_n_7 }),\n .S({\\fb_ypos_q[5]_i_2_n_0 ,\\fb_ypos_q[5]_i_3_n_0 ,\\fb_ypos_q[5]_i_4_n_0 ,\\fb_ypos_q[5]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[6] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[1]_i_1_n_0 ),\n .D(\\fb_ypos_q_reg[5]_i_1_n_6 ),\n .Q(fb_ypos_q_reg[6]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[7] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[1]_i_1_n_0 ),\n .D(\\fb_ypos_q_reg[5]_i_1_n_5 ),\n .Q(fb_ypos_q_reg[7]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[8] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[1]_i_1_n_0 ),\n .D(\\fb_ypos_q_reg[5]_i_1_n_4 ),\n .Q(fb_ypos_q_reg[8]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[9] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[1]_i_1_n_0 ),\n .D(\\fb_ypos_q_reg[9]_i_1_n_7 ),\n .Q(fb_ypos_q_reg[9]),\n .R(1'b0));\n CARRY4 \\fb_ypos_q_reg[9]_i_1 \n (.CI(\\fb_ypos_q_reg[5]_i_1_n_0 ),\n .CO({\\NLW_fb_ypos_q_reg[9]_i_1_CO_UNCONNECTED [3:2],\\fb_ypos_q_reg[9]_i_1_n_2 ,\\fb_ypos_q_reg[9]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\NLW_fb_ypos_q_reg[9]_i_1_O_UNCONNECTED [3],\\fb_ypos_q_reg[9]_i_1_n_5 ,\\fb_ypos_q_reg[9]_i_1_n_6 ,\\fb_ypos_q_reg[9]_i_1_n_7 }),\n .S({1'b0,\\fb_ypos_q[9]_i_2_n_0 ,\\fb_ypos_q[9]_i_3_n_0 ,\\fb_ypos_q[9]_i_4_n_0 }));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[11]_i_2__0 \n (.I0(int_address_q_reg[7]),\n .O(\\int_address_q[11]_i_2__0_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[11]_i_3__0 \n (.I0(int_address_q_reg[6]),\n .O(\\int_address_q[11]_i_3__0_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[11]_i_4__0 \n (.I0(int_address_q_reg[5]),\n .O(\\int_address_q[11]_i_4__0_n_0 ));\n LUT6 #(\n .INIT(64'h7F7F7FFF80808000)) \n \\int_address_q[11]_i_5 \n (.I0(fb_xpos_q_reg[11]),\n .I1(fb_xpos_q_reg[10]),\n .I2(fb_xpos_q_reg[9]),\n .I3(fb_xpos_q_reg[8]),\n .I4(fb_xpos_q_reg[7]),\n .I5(int_address_q_reg[4]),\n .O(\\int_address_q[11]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[15]_i_2__0 \n (.I0(int_address_q_reg[11]),\n .O(\\int_address_q[15]_i_2__0_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[15]_i_3__0 \n (.I0(int_address_q_reg[10]),\n .O(\\int_address_q[15]_i_3__0_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[15]_i_4__0 \n (.I0(int_address_q_reg[9]),\n .O(\\int_address_q[15]_i_4__0_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[15]_i_5__0 \n (.I0(int_address_q_reg[8]),\n .O(\\int_address_q[15]_i_5__0_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[19]_i_2__0 \n (.I0(int_address_q_reg[15]),\n .O(\\int_address_q[19]_i_2__0_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[19]_i_3__0 \n (.I0(int_address_q_reg[14]),\n .O(\\int_address_q[19]_i_3__0_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[19]_i_4__0 \n (.I0(int_address_q_reg[13]),\n .O(\\int_address_q[19]_i_4__0_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[19]_i_5__0 \n (.I0(int_address_q_reg[12]),\n .O(\\int_address_q[19]_i_5__0_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[23]_i_2__0 \n (.I0(int_address_q_reg[16]),\n .O(\\int_address_q[23]_i_2__0_n_0 ));\n LUT4 #(\n .INIT(16'h0888)) \n \\int_address_q[7]_i_1__0 \n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(\\fb_ypos_q[1]_i_3_n_0 ),\n .I3(\\fb_ypos_q[1]_i_4_n_0 ),\n .O(int_address_q));\n LUT6 #(\n .INIT(64'h7F7F7FFF80808000)) \n \\int_address_q[7]_i_3 \n (.I0(fb_xpos_q_reg[11]),\n .I1(fb_xpos_q_reg[10]),\n .I2(fb_xpos_q_reg[9]),\n .I3(fb_xpos_q_reg[8]),\n .I4(fb_xpos_q_reg[7]),\n .I5(int_address_q_reg[3]),\n .O(\\int_address_q[7]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h7F7F7FFF80808000)) \n \\int_address_q[7]_i_4 \n (.I0(fb_xpos_q_reg[11]),\n .I1(fb_xpos_q_reg[10]),\n .I2(fb_xpos_q_reg[9]),\n .I3(fb_xpos_q_reg[8]),\n .I4(fb_xpos_q_reg[7]),\n .I5(int_address_q_reg[2]),\n .O(\\int_address_q[7]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h7F7F7FFF80808000)) \n \\int_address_q[7]_i_5 \n (.I0(fb_xpos_q_reg[11]),\n .I1(fb_xpos_q_reg[10]),\n .I2(fb_xpos_q_reg[9]),\n .I3(fb_xpos_q_reg[8]),\n .I4(fb_xpos_q_reg[7]),\n .I5(int_address_q_reg[1]),\n .O(\\int_address_q[7]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\int_address_q[7]_i_6__0 \n (.I0(int_address_q_reg[0]),\n .O(\\int_address_q[7]_i_6__0_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[10] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[7]_i_2__0_n_4 ),\n .Q(int_address_q_reg[3]),\n .R(\\v_pos_reg[4] ));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[11] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[11]_i_1__0_n_7 ),\n .Q(int_address_q_reg[4]),\n .R(\\v_pos_reg[4] ));\n CARRY4 \\int_address_q_reg[11]_i_1__0 \n (.CI(\\int_address_q_reg[7]_i_2__0_n_0 ),\n .CO({\\int_address_q_reg[11]_i_1__0_n_0 ,\\int_address_q_reg[11]_i_1__0_n_1 ,\\int_address_q_reg[11]_i_1__0_n_2 ,\\int_address_q_reg[11]_i_1__0_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,\\fb_ypos_q[1]_i_3_n_0 }),\n .O({\\int_address_q_reg[11]_i_1__0_n_4 ,\\int_address_q_reg[11]_i_1__0_n_5 ,\\int_address_q_reg[11]_i_1__0_n_6 ,\\int_address_q_reg[11]_i_1__0_n_7 }),\n .S({\\int_address_q[11]_i_2__0_n_0 ,\\int_address_q[11]_i_3__0_n_0 ,\\int_address_q[11]_i_4__0_n_0 ,\\int_address_q[11]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[12] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[11]_i_1__0_n_6 ),\n .Q(int_address_q_reg[5]),\n .R(\\v_pos_reg[4] ));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[13] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[11]_i_1__0_n_5 ),\n .Q(int_address_q_reg[6]),\n .R(\\v_pos_reg[4] ));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[14] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[11]_i_1__0_n_4 ),\n .Q(int_address_q_reg[7]),\n .R(\\v_pos_reg[4] ));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[15] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[15]_i_1__0_n_7 ),\n .Q(int_address_q_reg[8]),\n .R(\\v_pos_reg[4] ));\n CARRY4 \\int_address_q_reg[15]_i_1__0 \n (.CI(\\int_address_q_reg[11]_i_1__0_n_0 ),\n .CO({\\int_address_q_reg[15]_i_1__0_n_0 ,\\int_address_q_reg[15]_i_1__0_n_1 ,\\int_address_q_reg[15]_i_1__0_n_2 ,\\int_address_q_reg[15]_i_1__0_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\int_address_q_reg[15]_i_1__0_n_4 ,\\int_address_q_reg[15]_i_1__0_n_5 ,\\int_address_q_reg[15]_i_1__0_n_6 ,\\int_address_q_reg[15]_i_1__0_n_7 }),\n .S({\\int_address_q[15]_i_2__0_n_0 ,\\int_address_q[15]_i_3__0_n_0 ,\\int_address_q[15]_i_4__0_n_0 ,\\int_address_q[15]_i_5__0_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[16] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[15]_i_1__0_n_6 ),\n .Q(int_address_q_reg[9]),\n .R(\\v_pos_reg[4] ));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[17] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[15]_i_1__0_n_5 ),\n .Q(int_address_q_reg[10]),\n .R(\\v_pos_reg[4] ));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[18] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[15]_i_1__0_n_4 ),\n .Q(int_address_q_reg[11]),\n .R(\\v_pos_reg[4] ));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[19] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[19]_i_1__0_n_7 ),\n .Q(int_address_q_reg[12]),\n .R(\\v_pos_reg[4] ));\n CARRY4 \\int_address_q_reg[19]_i_1__0 \n (.CI(\\int_address_q_reg[15]_i_1__0_n_0 ),\n .CO({\\int_address_q_reg[19]_i_1__0_n_0 ,\\int_address_q_reg[19]_i_1__0_n_1 ,\\int_address_q_reg[19]_i_1__0_n_2 ,\\int_address_q_reg[19]_i_1__0_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\int_address_q_reg[19]_i_1__0_n_4 ,\\int_address_q_reg[19]_i_1__0_n_5 ,\\int_address_q_reg[19]_i_1__0_n_6 ,\\int_address_q_reg[19]_i_1__0_n_7 }),\n .S({\\int_address_q[19]_i_2__0_n_0 ,\\int_address_q[19]_i_3__0_n_0 ,\\int_address_q[19]_i_4__0_n_0 ,\\int_address_q[19]_i_5__0_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[20] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[19]_i_1__0_n_6 ),\n .Q(int_address_q_reg[13]),\n .R(\\v_pos_reg[4] ));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[21] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[19]_i_1__0_n_5 ),\n .Q(int_address_q_reg[14]),\n .R(\\v_pos_reg[4] ));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[22] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[19]_i_1__0_n_4 ),\n .Q(int_address_q_reg[15]),\n .R(\\v_pos_reg[4] ));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[23] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[23]_i_1__0_n_7 ),\n .Q(int_address_q_reg[16]),\n .R(\\v_pos_reg[4] ));\n CARRY4 \\int_address_q_reg[23]_i_1__0 \n (.CI(\\int_address_q_reg[19]_i_1__0_n_0 ),\n .CO(\\NLW_int_address_q_reg[23]_i_1__0_CO_UNCONNECTED [3:0]),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\NLW_int_address_q_reg[23]_i_1__0_O_UNCONNECTED [3:1],\\int_address_q_reg[23]_i_1__0_n_7 }),\n .S({1'b0,1'b0,1'b0,\\int_address_q[23]_i_2__0_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[7] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[7]_i_2__0_n_7 ),\n .Q(int_address_q_reg[0]),\n .R(\\v_pos_reg[4] ));\n CARRY4 \\int_address_q_reg[7]_i_2__0 \n (.CI(1'b0),\n .CO({\\int_address_q_reg[7]_i_2__0_n_0 ,\\int_address_q_reg[7]_i_2__0_n_1 ,\\int_address_q_reg[7]_i_2__0_n_2 ,\\int_address_q_reg[7]_i_2__0_n_3 }),\n .CYINIT(1'b0),\n .DI({\\fb_ypos_q[1]_i_3_n_0 ,\\fb_ypos_q[1]_i_3_n_0 ,\\fb_ypos_q[1]_i_3_n_0 ,1'b1}),\n .O({\\int_address_q_reg[7]_i_2__0_n_4 ,\\int_address_q_reg[7]_i_2__0_n_5 ,\\int_address_q_reg[7]_i_2__0_n_6 ,\\int_address_q_reg[7]_i_2__0_n_7 }),\n .S({\\int_address_q[7]_i_3_n_0 ,\\int_address_q[7]_i_4_n_0 ,\\int_address_q[7]_i_5_n_0 ,\\int_address_q[7]_i_6__0_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[8] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[7]_i_2__0_n_6 ),\n .Q(int_address_q_reg[1]),\n .R(\\v_pos_reg[4] ));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[9] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[7]_i_2__0_n_5 ),\n .Q(int_address_q_reg[2]),\n .R(\\v_pos_reg[4] ));\n LUT5 #(\n .INIT(32'hFFFF0054)) \n \\read_state[1]_i_4 \n (.I0(\\read_state[1]_i_8_n_0 ),\n .I1(int_address_q_reg[8]),\n .I2(int_address_q_reg[9]),\n .I3(zoom_mode_IBUF),\n .I4(\\read_state[1]_i_9_n_0 ),\n .O(\\read_state_reg[0] ));\n LUT6 #(\n .INIT(64'h7FFFFFFFFFFFFFFF)) \n \\read_state[1]_i_8 \n (.I0(int_address_q_reg[14]),\n .I1(int_address_q_reg[10]),\n .I2(int_address_q_reg[12]),\n .I3(int_address_q_reg[15]),\n .I4(int_address_q_reg[11]),\n .I5(int_address_q_reg[13]),\n .O(\\read_state[1]_i_8_n_0 ));\n LUT4 #(\n .INIT(16'hFFF4)) \n \\read_state[1]_i_9 \n (.I0(zoom_mode_IBUF),\n .I1(int_address_q_reg[16]),\n .I2(prog_full),\n .I3(Q[1]),\n .O(\\read_state[1]_i_9_n_0 ));\nendmodule\n\n(* ORIG_REF_NAME = \"framebuffer_addr_ctrl\" *) \nmodule framebuffer_addr_ctrl__parameterized1\n (E,\n s_axi_araddr,\n ui_clk,\n \\v_pos_reg[4] ,\n Q,\n \\read_state_reg[1] ,\n \\int_address_q_reg[15]_0 ,\n \\read_state_reg[1]_0 ,\n zoom_mode_IBUF,\n int_address_q_reg);\n output [0:0]E;\n output [17:0]s_axi_araddr;\n input ui_clk;\n input \\v_pos_reg[4] ;\n input [1:0]Q;\n input \\read_state_reg[1] ;\n input \\int_address_q_reg[15]_0 ;\n input \\read_state_reg[1]_0 ;\n input zoom_mode_IBUF;\n input [16:0]int_address_q_reg;\n\n wire [0:0]E;\n wire [1:0]Q;\n wire \\fb_xpos_q[11]_i_2__1_n_0 ;\n wire \\fb_xpos_q[7]_i_1__0_n_0 ;\n wire \\fb_xpos_q[7]_i_3__1_n_0 ;\n wire \\fb_xpos_q[7]_i_4__1_n_0 ;\n wire \\fb_xpos_q[7]_i_5__1_n_0 ;\n wire \\fb_xpos_q[7]_i_6__1_n_0 ;\n wire [11:7]fb_xpos_q_reg;\n wire \\fb_xpos_q_reg[11]_i_1__1_n_7 ;\n wire \\fb_xpos_q_reg[7]_i_2__1_n_0 ;\n wire \\fb_xpos_q_reg[7]_i_2__1_n_1 ;\n wire \\fb_xpos_q_reg[7]_i_2__1_n_2 ;\n wire \\fb_xpos_q_reg[7]_i_2__1_n_3 ;\n wire \\fb_xpos_q_reg[7]_i_2__1_n_4 ;\n wire \\fb_xpos_q_reg[7]_i_2__1_n_5 ;\n wire \\fb_xpos_q_reg[7]_i_2__1_n_6 ;\n wire \\fb_xpos_q_reg[7]_i_2__1_n_7 ;\n wire \\fb_ypos_q[0]_i_10__0_n_0 ;\n wire \\fb_ypos_q[0]_i_1__0_n_0 ;\n wire \\fb_ypos_q[0]_i_3__0_n_0 ;\n wire \\fb_ypos_q[0]_i_4__0_n_0 ;\n wire \\fb_ypos_q[0]_i_5__0_n_0 ;\n wire \\fb_ypos_q[0]_i_6__0_n_0 ;\n wire \\fb_ypos_q[0]_i_7__0_n_0 ;\n wire \\fb_ypos_q[0]_i_8__0_n_0 ;\n wire \\fb_ypos_q[0]_i_9__0_n_0 ;\n wire \\fb_ypos_q[4]_i_2__0_n_0 ;\n wire \\fb_ypos_q[4]_i_3__0_n_0 ;\n wire \\fb_ypos_q[4]_i_4__0_n_0 ;\n wire \\fb_ypos_q[4]_i_5__0_n_0 ;\n wire \\fb_ypos_q[8]_i_2__0_n_0 ;\n wire \\fb_ypos_q[8]_i_3__0_n_0 ;\n wire \\fb_ypos_q[8]_i_4__0_n_0 ;\n wire \\fb_ypos_q[8]_i_5__0_n_0 ;\n wire [11:0]fb_ypos_q_reg;\n wire \\fb_ypos_q_reg[0]_i_2__0_n_0 ;\n wire \\fb_ypos_q_reg[0]_i_2__0_n_1 ;\n wire \\fb_ypos_q_reg[0]_i_2__0_n_2 ;\n wire \\fb_ypos_q_reg[0]_i_2__0_n_3 ;\n wire \\fb_ypos_q_reg[0]_i_2__0_n_4 ;\n wire \\fb_ypos_q_reg[0]_i_2__0_n_5 ;\n wire \\fb_ypos_q_reg[0]_i_2__0_n_6 ;\n wire \\fb_ypos_q_reg[0]_i_2__0_n_7 ;\n wire \\fb_ypos_q_reg[4]_i_1__0_n_0 ;\n wire \\fb_ypos_q_reg[4]_i_1__0_n_1 ;\n wire \\fb_ypos_q_reg[4]_i_1__0_n_2 ;\n wire \\fb_ypos_q_reg[4]_i_1__0_n_3 ;\n wire \\fb_ypos_q_reg[4]_i_1__0_n_4 ;\n wire \\fb_ypos_q_reg[4]_i_1__0_n_5 ;\n wire \\fb_ypos_q_reg[4]_i_1__0_n_6 ;\n wire \\fb_ypos_q_reg[4]_i_1__0_n_7 ;\n wire \\fb_ypos_q_reg[8]_i_1__0_n_1 ;\n wire \\fb_ypos_q_reg[8]_i_1__0_n_2 ;\n wire \\fb_ypos_q_reg[8]_i_1__0_n_3 ;\n wire \\fb_ypos_q_reg[8]_i_1__0_n_4 ;\n wire \\fb_ypos_q_reg[8]_i_1__0_n_5 ;\n wire \\fb_ypos_q_reg[8]_i_1__0_n_6 ;\n wire \\fb_ypos_q_reg[8]_i_1__0_n_7 ;\n wire int_address_q;\n wire \\int_address_q[10]_i_2_n_0 ;\n wire \\int_address_q[10]_i_3_n_0 ;\n wire \\int_address_q[10]_i_4_n_0 ;\n wire \\int_address_q[10]_i_5_n_0 ;\n wire \\int_address_q[14]_i_2_n_0 ;\n wire \\int_address_q[14]_i_3_n_0 ;\n wire \\int_address_q[14]_i_4_n_0 ;\n wire \\int_address_q[14]_i_5_n_0 ;\n wire \\int_address_q[18]_i_2_n_0 ;\n wire \\int_address_q[18]_i_3_n_0 ;\n wire \\int_address_q[18]_i_4_n_0 ;\n wire \\int_address_q[18]_i_5_n_0 ;\n wire \\int_address_q[22]_i_2_n_0 ;\n wire \\int_address_q[22]_i_3_n_0 ;\n wire \\int_address_q[6]_i_3_n_0 ;\n wire \\int_address_q[6]_i_4_n_0 ;\n wire \\int_address_q[6]_i_5_n_0 ;\n wire \\int_address_q[6]_i_6_n_0 ;\n wire \\int_address_q[6]_i_7_n_0 ;\n wire [16:0]int_address_q_reg;\n wire \\int_address_q_reg[10]_i_1_n_0 ;\n wire \\int_address_q_reg[10]_i_1_n_1 ;\n wire \\int_address_q_reg[10]_i_1_n_2 ;\n wire \\int_address_q_reg[10]_i_1_n_3 ;\n wire \\int_address_q_reg[10]_i_1_n_4 ;\n wire \\int_address_q_reg[10]_i_1_n_5 ;\n wire \\int_address_q_reg[10]_i_1_n_6 ;\n wire \\int_address_q_reg[10]_i_1_n_7 ;\n wire \\int_address_q_reg[14]_i_1_n_0 ;\n wire \\int_address_q_reg[14]_i_1_n_1 ;\n wire \\int_address_q_reg[14]_i_1_n_2 ;\n wire \\int_address_q_reg[14]_i_1_n_3 ;\n wire \\int_address_q_reg[14]_i_1_n_4 ;\n wire \\int_address_q_reg[14]_i_1_n_5 ;\n wire \\int_address_q_reg[14]_i_1_n_6 ;\n wire \\int_address_q_reg[14]_i_1_n_7 ;\n wire \\int_address_q_reg[15]_0 ;\n wire \\int_address_q_reg[18]_i_1_n_0 ;\n wire \\int_address_q_reg[18]_i_1_n_1 ;\n wire \\int_address_q_reg[18]_i_1_n_2 ;\n wire \\int_address_q_reg[18]_i_1_n_3 ;\n wire \\int_address_q_reg[18]_i_1_n_4 ;\n wire \\int_address_q_reg[18]_i_1_n_5 ;\n wire \\int_address_q_reg[18]_i_1_n_6 ;\n wire \\int_address_q_reg[18]_i_1_n_7 ;\n wire \\int_address_q_reg[22]_i_1_n_3 ;\n wire \\int_address_q_reg[22]_i_1_n_6 ;\n wire \\int_address_q_reg[22]_i_1_n_7 ;\n wire \\int_address_q_reg[6]_i_2_n_0 ;\n wire \\int_address_q_reg[6]_i_2_n_1 ;\n wire \\int_address_q_reg[6]_i_2_n_2 ;\n wire \\int_address_q_reg[6]_i_2_n_3 ;\n wire \\int_address_q_reg[6]_i_2_n_4 ;\n wire \\int_address_q_reg[6]_i_2_n_5 ;\n wire \\int_address_q_reg[6]_i_2_n_6 ;\n wire \\int_address_q_reg[6]_i_2_n_7 ;\n wire [23:6]int_address_q_reg_0;\n wire \\read_state[1]_i_10_n_0 ;\n wire \\read_state[1]_i_11_n_0 ;\n wire \\read_state[1]_i_12_n_0 ;\n wire \\read_state[1]_i_13_n_0 ;\n wire \\read_state[1]_i_5_n_0 ;\n wire \\read_state[1]_i_6_n_0 ;\n wire \\read_state_reg[1] ;\n wire \\read_state_reg[1]_0 ;\n wire [17:0]s_axi_araddr;\n wire ui_clk;\n wire \\v_pos_reg[4] ;\n wire zoom_mode_IBUF;\n wire [3:0]\\NLW_fb_xpos_q_reg[11]_i_1__1_CO_UNCONNECTED ;\n wire [3:1]\\NLW_fb_xpos_q_reg[11]_i_1__1_O_UNCONNECTED ;\n wire [3:3]\\NLW_fb_ypos_q_reg[8]_i_1__0_CO_UNCONNECTED ;\n wire [3:1]\\NLW_int_address_q_reg[22]_i_1_CO_UNCONNECTED ;\n wire [3:2]\\NLW_int_address_q_reg[22]_i_1_O_UNCONNECTED ;\n\n LUT1 #(\n .INIT(2'h2)) \n \\fb_xpos_q[11]_i_2__1 \n (.I0(fb_xpos_q_reg[11]),\n .O(\\fb_xpos_q[11]_i_2__1_n_0 ));\n LUT4 #(\n .INIT(16'h0040)) \n \\fb_xpos_q[7]_i_1__0 \n (.I0(\\fb_ypos_q[0]_i_4__0_n_0 ),\n .I1(Q[0]),\n .I2(Q[1]),\n .I3(\\v_pos_reg[4] ),\n .O(\\fb_xpos_q[7]_i_1__0_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_xpos_q[7]_i_3__1 \n (.I0(fb_xpos_q_reg[10]),\n .O(\\fb_xpos_q[7]_i_3__1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_xpos_q[7]_i_4__1 \n (.I0(fb_xpos_q_reg[9]),\n .O(\\fb_xpos_q[7]_i_4__1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_xpos_q[7]_i_5__1 \n (.I0(fb_xpos_q_reg[8]),\n .O(\\fb_xpos_q[7]_i_5__1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\fb_xpos_q[7]_i_6__1 \n (.I0(fb_xpos_q_reg[7]),\n .O(\\fb_xpos_q[7]_i_6__1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\fb_xpos_q_reg[10] \n (.C(ui_clk),\n .CE(\\fb_xpos_q[7]_i_1__0_n_0 ),\n .D(\\fb_xpos_q_reg[7]_i_2__1_n_4 ),\n .Q(fb_xpos_q_reg[10]),\n .R(\\fb_ypos_q[0]_i_1__0_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\fb_xpos_q_reg[11] \n (.C(ui_clk),\n .CE(\\fb_xpos_q[7]_i_1__0_n_0 ),\n .D(\\fb_xpos_q_reg[11]_i_1__1_n_7 ),\n .Q(fb_xpos_q_reg[11]),\n .R(\\fb_ypos_q[0]_i_1__0_n_0 ));\n CARRY4 \\fb_xpos_q_reg[11]_i_1__1 \n (.CI(\\fb_xpos_q_reg[7]_i_2__1_n_0 ),\n .CO(\\NLW_fb_xpos_q_reg[11]_i_1__1_CO_UNCONNECTED [3:0]),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\NLW_fb_xpos_q_reg[11]_i_1__1_O_UNCONNECTED [3:1],\\fb_xpos_q_reg[11]_i_1__1_n_7 }),\n .S({1'b0,1'b0,1'b0,\\fb_xpos_q[11]_i_2__1_n_0 }));\n FDSE #(\n .INIT(1'b1)) \n \\fb_xpos_q_reg[7] \n (.C(ui_clk),\n .CE(\\fb_xpos_q[7]_i_1__0_n_0 ),\n .D(\\fb_xpos_q_reg[7]_i_2__1_n_7 ),\n .Q(fb_xpos_q_reg[7]),\n .S(\\fb_ypos_q[0]_i_1__0_n_0 ));\n CARRY4 \\fb_xpos_q_reg[7]_i_2__1 \n (.CI(1'b0),\n .CO({\\fb_xpos_q_reg[7]_i_2__1_n_0 ,\\fb_xpos_q_reg[7]_i_2__1_n_1 ,\\fb_xpos_q_reg[7]_i_2__1_n_2 ,\\fb_xpos_q_reg[7]_i_2__1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b1}),\n .O({\\fb_xpos_q_reg[7]_i_2__1_n_4 ,\\fb_xpos_q_reg[7]_i_2__1_n_5 ,\\fb_xpos_q_reg[7]_i_2__1_n_6 ,\\fb_xpos_q_reg[7]_i_2__1_n_7 }),\n .S({\\fb_xpos_q[7]_i_3__1_n_0 ,\\fb_xpos_q[7]_i_4__1_n_0 ,\\fb_xpos_q[7]_i_5__1_n_0 ,\\fb_xpos_q[7]_i_6__1_n_0 }));\n FDSE #(\n .INIT(1'b1)) \n \\fb_xpos_q_reg[8] \n (.C(ui_clk),\n .CE(\\fb_xpos_q[7]_i_1__0_n_0 ),\n .D(\\fb_xpos_q_reg[7]_i_2__1_n_6 ),\n .Q(fb_xpos_q_reg[8]),\n .S(\\fb_ypos_q[0]_i_1__0_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\fb_xpos_q_reg[9] \n (.C(ui_clk),\n .CE(\\fb_xpos_q[7]_i_1__0_n_0 ),\n .D(\\fb_xpos_q_reg[7]_i_2__1_n_5 ),\n .Q(fb_xpos_q_reg[9]),\n .S(\\fb_ypos_q[0]_i_1__0_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\fb_ypos_q[0]_i_10__0 \n (.I0(fb_ypos_q_reg[8]),\n .I1(fb_ypos_q_reg[7]),\n .O(\\fb_ypos_q[0]_i_10__0_n_0 ));\n LUT5 #(\n .INIT(32'h08000000)) \n \\fb_ypos_q[0]_i_1__0 \n (.I0(\\fb_ypos_q[0]_i_3__0_n_0 ),\n .I1(\\fb_ypos_q[0]_i_4__0_n_0 ),\n .I2(\\v_pos_reg[4] ),\n .I3(Q[1]),\n .I4(Q[0]),\n .O(\\fb_ypos_q[0]_i_1__0_n_0 ));\n LUT6 #(\n .INIT(64'h000000000BFFFFFF)) \n \\fb_ypos_q[0]_i_3__0 \n (.I0(\\fb_ypos_q[0]_i_9__0_n_0 ),\n .I1(fb_ypos_q_reg[6]),\n .I2(\\fb_ypos_q[0]_i_10__0_n_0 ),\n .I3(fb_ypos_q_reg[10]),\n .I4(fb_ypos_q_reg[9]),\n .I5(fb_ypos_q_reg[11]),\n .O(\\fb_ypos_q[0]_i_3__0_n_0 ));\n LUT5 #(\n .INIT(32'hAAA88888)) \n \\fb_ypos_q[0]_i_4__0 \n (.I0(fb_xpos_q_reg[11]),\n .I1(fb_xpos_q_reg[10]),\n .I2(fb_xpos_q_reg[7]),\n .I3(fb_xpos_q_reg[8]),\n .I4(fb_xpos_q_reg[9]),\n .O(\\fb_ypos_q[0]_i_4__0_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_ypos_q[0]_i_5__0 \n (.I0(fb_ypos_q_reg[3]),\n .O(\\fb_ypos_q[0]_i_5__0_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_ypos_q[0]_i_6__0 \n (.I0(fb_ypos_q_reg[2]),\n .O(\\fb_ypos_q[0]_i_6__0_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_ypos_q[0]_i_7__0 \n (.I0(fb_ypos_q_reg[1]),\n .O(\\fb_ypos_q[0]_i_7__0_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\fb_ypos_q[0]_i_8__0 \n (.I0(fb_ypos_q_reg[0]),\n .O(\\fb_ypos_q[0]_i_8__0_n_0 ));\n LUT6 #(\n .INIT(64'h000000005555557F)) \n \\fb_ypos_q[0]_i_9__0 \n (.I0(fb_ypos_q_reg[4]),\n .I1(fb_ypos_q_reg[0]),\n .I2(fb_ypos_q_reg[1]),\n .I3(fb_ypos_q_reg[2]),\n .I4(fb_ypos_q_reg[3]),\n .I5(fb_ypos_q_reg[5]),\n .O(\\fb_ypos_q[0]_i_9__0_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_ypos_q[4]_i_2__0 \n (.I0(fb_ypos_q_reg[7]),\n .O(\\fb_ypos_q[4]_i_2__0_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_ypos_q[4]_i_3__0 \n (.I0(fb_ypos_q_reg[6]),\n .O(\\fb_ypos_q[4]_i_3__0_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_ypos_q[4]_i_4__0 \n (.I0(fb_ypos_q_reg[5]),\n .O(\\fb_ypos_q[4]_i_4__0_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_ypos_q[4]_i_5__0 \n (.I0(fb_ypos_q_reg[4]),\n .O(\\fb_ypos_q[4]_i_5__0_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_ypos_q[8]_i_2__0 \n (.I0(fb_ypos_q_reg[11]),\n .O(\\fb_ypos_q[8]_i_2__0_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_ypos_q[8]_i_3__0 \n (.I0(fb_ypos_q_reg[10]),\n .O(\\fb_ypos_q[8]_i_3__0_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_ypos_q[8]_i_4__0 \n (.I0(fb_ypos_q_reg[9]),\n .O(\\fb_ypos_q[8]_i_4__0_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\fb_ypos_q[8]_i_5__0 \n (.I0(fb_ypos_q_reg[8]),\n .O(\\fb_ypos_q[8]_i_5__0_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[0] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[0]_i_1__0_n_0 ),\n .D(\\fb_ypos_q_reg[0]_i_2__0_n_7 ),\n .Q(fb_ypos_q_reg[0]),\n .R(1'b0));\n CARRY4 \\fb_ypos_q_reg[0]_i_2__0 \n (.CI(1'b0),\n .CO({\\fb_ypos_q_reg[0]_i_2__0_n_0 ,\\fb_ypos_q_reg[0]_i_2__0_n_1 ,\\fb_ypos_q_reg[0]_i_2__0_n_2 ,\\fb_ypos_q_reg[0]_i_2__0_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b1}),\n .O({\\fb_ypos_q_reg[0]_i_2__0_n_4 ,\\fb_ypos_q_reg[0]_i_2__0_n_5 ,\\fb_ypos_q_reg[0]_i_2__0_n_6 ,\\fb_ypos_q_reg[0]_i_2__0_n_7 }),\n .S({\\fb_ypos_q[0]_i_5__0_n_0 ,\\fb_ypos_q[0]_i_6__0_n_0 ,\\fb_ypos_q[0]_i_7__0_n_0 ,\\fb_ypos_q[0]_i_8__0_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[10] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[0]_i_1__0_n_0 ),\n .D(\\fb_ypos_q_reg[8]_i_1__0_n_5 ),\n .Q(fb_ypos_q_reg[10]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[11] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[0]_i_1__0_n_0 ),\n .D(\\fb_ypos_q_reg[8]_i_1__0_n_4 ),\n .Q(fb_ypos_q_reg[11]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[1] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[0]_i_1__0_n_0 ),\n .D(\\fb_ypos_q_reg[0]_i_2__0_n_6 ),\n .Q(fb_ypos_q_reg[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[2] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[0]_i_1__0_n_0 ),\n .D(\\fb_ypos_q_reg[0]_i_2__0_n_5 ),\n .Q(fb_ypos_q_reg[2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[3] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[0]_i_1__0_n_0 ),\n .D(\\fb_ypos_q_reg[0]_i_2__0_n_4 ),\n .Q(fb_ypos_q_reg[3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[4] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[0]_i_1__0_n_0 ),\n .D(\\fb_ypos_q_reg[4]_i_1__0_n_7 ),\n .Q(fb_ypos_q_reg[4]),\n .R(1'b0));\n CARRY4 \\fb_ypos_q_reg[4]_i_1__0 \n (.CI(\\fb_ypos_q_reg[0]_i_2__0_n_0 ),\n .CO({\\fb_ypos_q_reg[4]_i_1__0_n_0 ,\\fb_ypos_q_reg[4]_i_1__0_n_1 ,\\fb_ypos_q_reg[4]_i_1__0_n_2 ,\\fb_ypos_q_reg[4]_i_1__0_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\fb_ypos_q_reg[4]_i_1__0_n_4 ,\\fb_ypos_q_reg[4]_i_1__0_n_5 ,\\fb_ypos_q_reg[4]_i_1__0_n_6 ,\\fb_ypos_q_reg[4]_i_1__0_n_7 }),\n .S({\\fb_ypos_q[4]_i_2__0_n_0 ,\\fb_ypos_q[4]_i_3__0_n_0 ,\\fb_ypos_q[4]_i_4__0_n_0 ,\\fb_ypos_q[4]_i_5__0_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[5] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[0]_i_1__0_n_0 ),\n .D(\\fb_ypos_q_reg[4]_i_1__0_n_6 ),\n .Q(fb_ypos_q_reg[5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[6] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[0]_i_1__0_n_0 ),\n .D(\\fb_ypos_q_reg[4]_i_1__0_n_5 ),\n .Q(fb_ypos_q_reg[6]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[7] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[0]_i_1__0_n_0 ),\n .D(\\fb_ypos_q_reg[4]_i_1__0_n_4 ),\n .Q(fb_ypos_q_reg[7]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[8] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[0]_i_1__0_n_0 ),\n .D(\\fb_ypos_q_reg[8]_i_1__0_n_7 ),\n .Q(fb_ypos_q_reg[8]),\n .R(1'b0));\n CARRY4 \\fb_ypos_q_reg[8]_i_1__0 \n (.CI(\\fb_ypos_q_reg[4]_i_1__0_n_0 ),\n .CO({\\NLW_fb_ypos_q_reg[8]_i_1__0_CO_UNCONNECTED [3],\\fb_ypos_q_reg[8]_i_1__0_n_1 ,\\fb_ypos_q_reg[8]_i_1__0_n_2 ,\\fb_ypos_q_reg[8]_i_1__0_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\fb_ypos_q_reg[8]_i_1__0_n_4 ,\\fb_ypos_q_reg[8]_i_1__0_n_5 ,\\fb_ypos_q_reg[8]_i_1__0_n_6 ,\\fb_ypos_q_reg[8]_i_1__0_n_7 }),\n .S({\\fb_ypos_q[8]_i_2__0_n_0 ,\\fb_ypos_q[8]_i_3__0_n_0 ,\\fb_ypos_q[8]_i_4__0_n_0 ,\\fb_ypos_q[8]_i_5__0_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\fb_ypos_q_reg[9] \n (.C(ui_clk),\n .CE(\\fb_ypos_q[0]_i_1__0_n_0 ),\n .D(\\fb_ypos_q_reg[8]_i_1__0_n_6 ),\n .Q(fb_ypos_q_reg[9]),\n .R(1'b0));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[10]_i_2 \n (.I0(int_address_q_reg_0[13]),\n .O(\\int_address_q[10]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[10]_i_3 \n (.I0(int_address_q_reg_0[12]),\n .O(\\int_address_q[10]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0057FFFFFFA80000)) \n \\int_address_q[10]_i_4 \n (.I0(fb_xpos_q_reg[9]),\n .I1(fb_xpos_q_reg[8]),\n .I2(fb_xpos_q_reg[7]),\n .I3(fb_xpos_q_reg[10]),\n .I4(fb_xpos_q_reg[11]),\n .I5(int_address_q_reg_0[11]),\n .O(\\int_address_q[10]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[10]_i_5 \n (.I0(int_address_q_reg_0[10]),\n .O(\\int_address_q[10]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[14]_i_2 \n (.I0(int_address_q_reg_0[17]),\n .O(\\int_address_q[14]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[14]_i_3 \n (.I0(int_address_q_reg_0[16]),\n .O(\\int_address_q[14]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[14]_i_4 \n (.I0(int_address_q_reg_0[15]),\n .O(\\int_address_q[14]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[14]_i_5 \n (.I0(int_address_q_reg_0[14]),\n .O(\\int_address_q[14]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[18]_i_2 \n (.I0(int_address_q_reg_0[21]),\n .O(\\int_address_q[18]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[18]_i_3 \n (.I0(int_address_q_reg_0[20]),\n .O(\\int_address_q[18]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[18]_i_4 \n (.I0(int_address_q_reg_0[19]),\n .O(\\int_address_q[18]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[18]_i_5 \n (.I0(int_address_q_reg_0[18]),\n .O(\\int_address_q[18]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[22]_i_2 \n (.I0(int_address_q_reg_0[23]),\n .O(\\int_address_q[22]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[22]_i_3 \n (.I0(int_address_q_reg_0[22]),\n .O(\\int_address_q[22]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'h8088)) \n \\int_address_q[6]_i_1 \n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(\\fb_ypos_q[0]_i_3__0_n_0 ),\n .I3(\\fb_ypos_q[0]_i_4__0_n_0 ),\n .O(int_address_q));\n LUT5 #(\n .INIT(32'h0057FFFF)) \n \\int_address_q[6]_i_3 \n (.I0(fb_xpos_q_reg[9]),\n .I1(fb_xpos_q_reg[8]),\n .I2(fb_xpos_q_reg[7]),\n .I3(fb_xpos_q_reg[10]),\n .I4(fb_xpos_q_reg[11]),\n .O(\\int_address_q[6]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[6]_i_4 \n (.I0(int_address_q_reg_0[9]),\n .O(\\int_address_q[6]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[6]_i_5 \n (.I0(int_address_q_reg_0[8]),\n .O(\\int_address_q[6]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFA800000057FFFF)) \n \\int_address_q[6]_i_6 \n (.I0(fb_xpos_q_reg[9]),\n .I1(fb_xpos_q_reg[8]),\n .I2(fb_xpos_q_reg[7]),\n .I3(fb_xpos_q_reg[10]),\n .I4(fb_xpos_q_reg[11]),\n .I5(int_address_q_reg_0[7]),\n .O(\\int_address_q[6]_i_6_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\int_address_q[6]_i_7 \n (.I0(int_address_q_reg_0[6]),\n .O(\\int_address_q[6]_i_7_n_0 ));\n FDSE #(\n .INIT(1'b1)) \n \\int_address_q_reg[10] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[10]_i_1_n_7 ),\n .Q(int_address_q_reg_0[10]),\n .S(\\v_pos_reg[4] ));\n CARRY4 \\int_address_q_reg[10]_i_1 \n (.CI(\\int_address_q_reg[6]_i_2_n_0 ),\n .CO({\\int_address_q_reg[10]_i_1_n_0 ,\\int_address_q_reg[10]_i_1_n_1 ,\\int_address_q_reg[10]_i_1_n_2 ,\\int_address_q_reg[10]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,\\fb_ypos_q[0]_i_4__0_n_0 ,1'b0}),\n .O({\\int_address_q_reg[10]_i_1_n_4 ,\\int_address_q_reg[10]_i_1_n_5 ,\\int_address_q_reg[10]_i_1_n_6 ,\\int_address_q_reg[10]_i_1_n_7 }),\n .S({\\int_address_q[10]_i_2_n_0 ,\\int_address_q[10]_i_3_n_0 ,\\int_address_q[10]_i_4_n_0 ,\\int_address_q[10]_i_5_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[11] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[10]_i_1_n_6 ),\n .Q(int_address_q_reg_0[11]),\n .R(\\v_pos_reg[4] ));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[12] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[10]_i_1_n_5 ),\n .Q(int_address_q_reg_0[12]),\n .R(\\v_pos_reg[4] ));\n FDSE #(\n .INIT(1'b1)) \n \\int_address_q_reg[13] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[10]_i_1_n_4 ),\n .Q(int_address_q_reg_0[13]),\n .S(\\v_pos_reg[4] ));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[14] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[14]_i_1_n_7 ),\n .Q(int_address_q_reg_0[14]),\n .R(\\v_pos_reg[4] ));\n CARRY4 \\int_address_q_reg[14]_i_1 \n (.CI(\\int_address_q_reg[10]_i_1_n_0 ),\n .CO({\\int_address_q_reg[14]_i_1_n_0 ,\\int_address_q_reg[14]_i_1_n_1 ,\\int_address_q_reg[14]_i_1_n_2 ,\\int_address_q_reg[14]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\int_address_q_reg[14]_i_1_n_4 ,\\int_address_q_reg[14]_i_1_n_5 ,\\int_address_q_reg[14]_i_1_n_6 ,\\int_address_q_reg[14]_i_1_n_7 }),\n .S({\\int_address_q[14]_i_2_n_0 ,\\int_address_q[14]_i_3_n_0 ,\\int_address_q[14]_i_4_n_0 ,\\int_address_q[14]_i_5_n_0 }));\n FDSE #(\n .INIT(1'b1)) \n \\int_address_q_reg[15] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[14]_i_1_n_6 ),\n .Q(int_address_q_reg_0[15]),\n .S(\\v_pos_reg[4] ));\n FDSE #(\n .INIT(1'b1)) \n \\int_address_q_reg[16] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[14]_i_1_n_5 ),\n .Q(int_address_q_reg_0[16]),\n .S(\\v_pos_reg[4] ));\n FDSE #(\n .INIT(1'b1)) \n \\int_address_q_reg[17] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[14]_i_1_n_4 ),\n .Q(int_address_q_reg_0[17]),\n .S(\\v_pos_reg[4] ));\n FDSE #(\n .INIT(1'b1)) \n \\int_address_q_reg[18] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[18]_i_1_n_7 ),\n .Q(int_address_q_reg_0[18]),\n .S(\\v_pos_reg[4] ));\n CARRY4 \\int_address_q_reg[18]_i_1 \n (.CI(\\int_address_q_reg[14]_i_1_n_0 ),\n .CO({\\int_address_q_reg[18]_i_1_n_0 ,\\int_address_q_reg[18]_i_1_n_1 ,\\int_address_q_reg[18]_i_1_n_2 ,\\int_address_q_reg[18]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\int_address_q_reg[18]_i_1_n_4 ,\\int_address_q_reg[18]_i_1_n_5 ,\\int_address_q_reg[18]_i_1_n_6 ,\\int_address_q_reg[18]_i_1_n_7 }),\n .S({\\int_address_q[18]_i_2_n_0 ,\\int_address_q[18]_i_3_n_0 ,\\int_address_q[18]_i_4_n_0 ,\\int_address_q[18]_i_5_n_0 }));\n FDSE #(\n .INIT(1'b1)) \n \\int_address_q_reg[19] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[18]_i_1_n_6 ),\n .Q(int_address_q_reg_0[19]),\n .S(\\v_pos_reg[4] ));\n FDSE #(\n .INIT(1'b1)) \n \\int_address_q_reg[20] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[18]_i_1_n_5 ),\n .Q(int_address_q_reg_0[20]),\n .S(\\v_pos_reg[4] ));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[21] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[18]_i_1_n_4 ),\n .Q(int_address_q_reg_0[21]),\n .R(\\v_pos_reg[4] ));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[22] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[22]_i_1_n_7 ),\n .Q(int_address_q_reg_0[22]),\n .R(\\v_pos_reg[4] ));\n CARRY4 \\int_address_q_reg[22]_i_1 \n (.CI(\\int_address_q_reg[18]_i_1_n_0 ),\n .CO({\\NLW_int_address_q_reg[22]_i_1_CO_UNCONNECTED [3:1],\\int_address_q_reg[22]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\NLW_int_address_q_reg[22]_i_1_O_UNCONNECTED [3:2],\\int_address_q_reg[22]_i_1_n_6 ,\\int_address_q_reg[22]_i_1_n_7 }),\n .S({1'b0,1'b0,\\int_address_q[22]_i_2_n_0 ,\\int_address_q[22]_i_3_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[23] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[22]_i_1_n_6 ),\n .Q(int_address_q_reg_0[23]),\n .R(\\v_pos_reg[4] ));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[6] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[6]_i_2_n_7 ),\n .Q(int_address_q_reg_0[6]),\n .R(\\v_pos_reg[4] ));\n CARRY4 \\int_address_q_reg[6]_i_2 \n (.CI(1'b0),\n .CO({\\int_address_q_reg[6]_i_2_n_0 ,\\int_address_q_reg[6]_i_2_n_1 ,\\int_address_q_reg[6]_i_2_n_2 ,\\int_address_q_reg[6]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,\\int_address_q[6]_i_3_n_0 ,1'b0}),\n .O({\\int_address_q_reg[6]_i_2_n_4 ,\\int_address_q_reg[6]_i_2_n_5 ,\\int_address_q_reg[6]_i_2_n_6 ,\\int_address_q_reg[6]_i_2_n_7 }),\n .S({\\int_address_q[6]_i_4_n_0 ,\\int_address_q[6]_i_5_n_0 ,\\int_address_q[6]_i_6_n_0 ,\\int_address_q[6]_i_7_n_0 }));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[7] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[6]_i_2_n_6 ),\n .Q(int_address_q_reg_0[7]),\n .R(\\v_pos_reg[4] ));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[8] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[6]_i_2_n_5 ),\n .Q(int_address_q_reg_0[8]),\n .R(\\v_pos_reg[4] ));\n FDRE #(\n .INIT(1'b0)) \n \\int_address_q_reg[9] \n (.C(ui_clk),\n .CE(int_address_q),\n .D(\\int_address_q_reg[6]_i_2_n_4 ),\n .Q(int_address_q_reg_0[9]),\n .R(\\v_pos_reg[4] ));\n (* SOFT_HLUTNM = \"soft_lutpair9\" *) \n LUT3 #(\n .INIT(8'hB8)) \n memctl_i_10\n (.I0(int_address_q_reg_0[15]),\n .I1(zoom_mode_IBUF),\n .I2(int_address_q_reg[8]),\n .O(s_axi_araddr[9]));\n (* SOFT_HLUTNM = \"soft_lutpair8\" *) \n LUT3 #(\n .INIT(8'hB8)) \n memctl_i_11\n (.I0(int_address_q_reg_0[14]),\n .I1(zoom_mode_IBUF),\n .I2(int_address_q_reg[7]),\n .O(s_axi_araddr[8]));\n (* SOFT_HLUTNM = \"soft_lutpair10\" *) \n LUT3 #(\n .INIT(8'hB8)) \n memctl_i_12\n (.I0(int_address_q_reg_0[13]),\n .I1(zoom_mode_IBUF),\n .I2(int_address_q_reg[6]),\n .O(s_axi_araddr[7]));\n (* SOFT_HLUTNM = \"soft_lutpair4\" *) \n LUT3 #(\n .INIT(8'hB8)) \n memctl_i_13\n (.I0(int_address_q_reg_0[12]),\n .I1(zoom_mode_IBUF),\n .I2(int_address_q_reg[5]),\n .O(s_axi_araddr[6]));\n (* SOFT_HLUTNM = \"soft_lutpair10\" *) \n LUT3 #(\n .INIT(8'hB8)) \n memctl_i_14\n (.I0(int_address_q_reg_0[11]),\n .I1(zoom_mode_IBUF),\n .I2(int_address_q_reg[4]),\n .O(s_axi_araddr[5]));\n (* SOFT_HLUTNM = \"soft_lutpair11\" *) \n LUT3 #(\n .INIT(8'hB8)) \n memctl_i_15\n (.I0(int_address_q_reg_0[10]),\n .I1(zoom_mode_IBUF),\n .I2(int_address_q_reg[3]),\n .O(s_axi_araddr[4]));\n (* SOFT_HLUTNM = \"soft_lutpair11\" *) \n LUT3 #(\n .INIT(8'hB8)) \n memctl_i_16\n (.I0(int_address_q_reg_0[9]),\n .I1(zoom_mode_IBUF),\n .I2(int_address_q_reg[2]),\n .O(s_axi_araddr[3]));\n (* SOFT_HLUTNM = \"soft_lutpair12\" *) \n LUT3 #(\n .INIT(8'hB8)) \n memctl_i_17\n (.I0(int_address_q_reg_0[8]),\n .I1(zoom_mode_IBUF),\n .I2(int_address_q_reg[1]),\n .O(s_axi_araddr[2]));\n (* SOFT_HLUTNM = \"soft_lutpair12\" *) \n LUT3 #(\n .INIT(8'hB8)) \n memctl_i_18\n (.I0(int_address_q_reg_0[7]),\n .I1(zoom_mode_IBUF),\n .I2(int_address_q_reg[0]),\n .O(s_axi_araddr[1]));\n LUT2 #(\n .INIT(4'h8)) \n memctl_i_19\n (.I0(zoom_mode_IBUF),\n .I1(int_address_q_reg_0[6]),\n .O(s_axi_araddr[0]));\n (* SOFT_HLUTNM = \"soft_lutpair5\" *) \n LUT3 #(\n .INIT(8'hB8)) \n memctl_i_2\n (.I0(int_address_q_reg_0[23]),\n .I1(zoom_mode_IBUF),\n .I2(int_address_q_reg[16]),\n .O(s_axi_araddr[17]));\n (* SOFT_HLUTNM = \"soft_lutpair6\" *) \n LUT3 #(\n .INIT(8'hB8)) \n memctl_i_3\n (.I0(int_address_q_reg_0[22]),\n .I1(zoom_mode_IBUF),\n .I2(int_address_q_reg[15]),\n .O(s_axi_araddr[16]));\n (* SOFT_HLUTNM = \"soft_lutpair6\" *) \n LUT3 #(\n .INIT(8'hB8)) \n memctl_i_4\n (.I0(int_address_q_reg_0[21]),\n .I1(zoom_mode_IBUF),\n .I2(int_address_q_reg[14]),\n .O(s_axi_araddr[15]));\n (* SOFT_HLUTNM = \"soft_lutpair7\" *) \n LUT3 #(\n .INIT(8'hB8)) \n memctl_i_5\n (.I0(int_address_q_reg_0[20]),\n .I1(zoom_mode_IBUF),\n .I2(int_address_q_reg[13]),\n .O(s_axi_araddr[14]));\n (* SOFT_HLUTNM = \"soft_lutpair5\" *) \n LUT3 #(\n .INIT(8'hB8)) \n memctl_i_6\n (.I0(int_address_q_reg_0[19]),\n .I1(zoom_mode_IBUF),\n .I2(int_address_q_reg[12]),\n .O(s_axi_araddr[13]));\n (* SOFT_HLUTNM = \"soft_lutpair7\" *) \n LUT3 #(\n .INIT(8'hB8)) \n memctl_i_7\n (.I0(int_address_q_reg_0[18]),\n .I1(zoom_mode_IBUF),\n .I2(int_address_q_reg[11]),\n .O(s_axi_araddr[12]));\n (* SOFT_HLUTNM = \"soft_lutpair8\" *) \n LUT3 #(\n .INIT(8'hB8)) \n memctl_i_8\n (.I0(int_address_q_reg_0[17]),\n .I1(zoom_mode_IBUF),\n .I2(int_address_q_reg[10]),\n .O(s_axi_araddr[11]));\n (* SOFT_HLUTNM = \"soft_lutpair9\" *) \n LUT3 #(\n .INIT(8'hB8)) \n memctl_i_9\n (.I0(int_address_q_reg_0[16]),\n .I1(zoom_mode_IBUF),\n .I2(int_address_q_reg[9]),\n .O(s_axi_araddr[10]));\n LUT6 #(\n .INIT(64'hFFFFBBBAAAAABBBA)) \n \\read_state[1]_i_1 \n (.I0(\\read_state_reg[1] ),\n .I1(\\int_address_q_reg[15]_0 ),\n .I2(\\read_state[1]_i_5_n_0 ),\n .I3(\\read_state[1]_i_6_n_0 ),\n .I4(Q[0]),\n .I5(\\read_state_reg[1]_0 ),\n .O(E));\n LUT4 #(\n .INIT(16'h007F)) \n \\read_state[1]_i_10 \n (.I0(int_address_q_reg_0[13]),\n .I1(int_address_q_reg_0[15]),\n .I2(int_address_q_reg_0[14]),\n .I3(int_address_q_reg_0[16]),\n .O(\\read_state[1]_i_10_n_0 ));\n LUT5 #(\n .INIT(32'h7FFFFFFF)) \n \\read_state[1]_i_11 \n (.I0(int_address_q_reg_0[17]),\n .I1(int_address_q_reg_0[18]),\n .I2(int_address_q_reg_0[22]),\n .I3(int_address_q_reg_0[20]),\n .I4(int_address_q_reg_0[19]),\n .O(\\read_state[1]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'h0001010101010101)) \n \\read_state[1]_i_12 \n (.I0(int_address_q_reg_0[11]),\n .I1(int_address_q_reg_0[16]),\n .I2(int_address_q_reg_0[12]),\n .I3(int_address_q_reg_0[8]),\n .I4(int_address_q_reg_0[10]),\n .I5(int_address_q_reg_0[9]),\n .O(\\read_state[1]_i_12_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair4\" *) \n LUT3 #(\n .INIT(8'h01)) \n \\read_state[1]_i_13 \n (.I0(int_address_q_reg_0[12]),\n .I1(int_address_q_reg_0[16]),\n .I2(int_address_q_reg_0[11]),\n .O(\\read_state[1]_i_13_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000FEFEFE)) \n \\read_state[1]_i_5 \n (.I0(\\read_state[1]_i_10_n_0 ),\n .I1(\\read_state[1]_i_11_n_0 ),\n .I2(\\read_state[1]_i_12_n_0 ),\n .I3(int_address_q_reg_0[21]),\n .I4(int_address_q_reg_0[22]),\n .I5(int_address_q_reg_0[23]),\n .O(\\read_state[1]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h555555555555555D)) \n \\read_state[1]_i_6 \n (.I0(zoom_mode_IBUF),\n .I1(\\read_state[1]_i_13_n_0 ),\n .I2(int_address_q_reg_0[6]),\n .I3(int_address_q_reg_0[21]),\n .I4(int_address_q_reg_0[7]),\n .I5(int_address_q_reg_0[23]),\n .O(\\read_state[1]_i_6_n_0 ));\nendmodule\n\nmodule framebuffer_ctrl_crop_scale\n (dout,\n s_axi_awaddr,\n odd_pixel,\n s_axi_arvalid,\n s_axi_araddr,\n s_axi_wlast,\n D,\n s_axi_awvalid,\n rst,\n CLK,\n ui_clk,\n wr_en,\n \\v_pos_reg[4] ,\n bbstub_pixel_clock,\n s_axi_rdata,\n rd_en,\n odd_pixel_reg_0,\n odd_pixel_reg_1,\n fbc_ovsync,\n s_axi_arready,\n zoom_mode_IBUF,\n s_axi_rlast,\n s_axi_rvalid,\n s_axi_wready,\n s_axi_awready);\n output [255:0]dout;\n output [16:0]s_axi_awaddr;\n output odd_pixel;\n output s_axi_arvalid;\n output [17:0]s_axi_araddr;\n output s_axi_wlast;\n output [0:0]D;\n output s_axi_awvalid;\n input rst;\n input CLK;\n input ui_clk;\n input wr_en;\n input \\v_pos_reg[4] ;\n input bbstub_pixel_clock;\n input [255:0]s_axi_rdata;\n input rd_en;\n input odd_pixel_reg_0;\n input odd_pixel_reg_1;\n input fbc_ovsync;\n input s_axi_arready;\n input zoom_mode_IBUF;\n input s_axi_rlast;\n input s_axi_rvalid;\n input s_axi_wready;\n input s_axi_awready;\n\n wire CLK;\n wire [0:0]D;\n wire \\FSM_sequential_write_state[0]_i_1_n_0 ;\n wire \\FSM_sequential_write_state[1]_i_1_n_0 ;\n wire \\FSM_sequential_write_state[2]_i_1_n_0 ;\n wire \\FSM_sequential_write_state[2]_i_2_n_0 ;\n wire \\FSM_sequential_write_state[2]_i_5_n_0 ;\n wire bbstub_pixel_clock;\n wire [255:0]dout;\n wire fbc_ovsync;\n wire i__i_1_n_0;\n wire [23:7]int_address_q_reg;\n wire odd_pixel;\n wire odd_pixel_reg_0;\n wire odd_pixel_reg_1;\n wire output_fifo1_i_2_n_0;\n wire prog_empty;\n wire prog_full;\n wire rd_adctrl_crop_n_0;\n wire rd_adctrl_scale_n_17;\n wire rd_en;\n wire rd_en_0;\n wire [1:1]read_state;\n wire \\read_state[0]_i_1_n_0 ;\n wire \\read_state[1]_i_3_n_0 ;\n wire \\read_state[1]_i_7_n_0 ;\n wire \\read_state_reg_n_0_[0] ;\n wire \\read_state_reg_n_0_[1] ;\n wire rst;\n wire [17:0]s_axi_araddr;\n wire s_axi_arready;\n wire s_axi_arvalid;\n wire [16:0]s_axi_awaddr;\n wire s_axi_awready;\n wire s_axi_awvalid;\n wire [255:0]s_axi_rdata;\n wire s_axi_rlast;\n wire s_axi_rvalid;\n wire s_axi_wlast;\n wire s_axi_wready;\n wire ui_clk;\n wire \\v_pos_reg[4] ;\n wire wr_adctrl_n_17;\n wire wr_adctrl_n_18;\n wire wr_en;\n wire write_count;\n wire \\write_count[0]_i_1_n_0 ;\n wire \\write_count[1]_i_1_n_0 ;\n wire \\write_count[2]_i_1_n_0 ;\n wire \\write_count[3]_i_1_n_0 ;\n wire \\write_count_reg_n_0_[0] ;\n wire \\write_count_reg_n_0_[1] ;\n wire \\write_count_reg_n_0_[2] ;\n wire \\write_count_reg_n_0_[3] ;\n (* RTL_KEEP = \"yes\" *) wire [2:0]write_state;\n wire zoom_mode_IBUF;\n wire NLW_input_fifo_empty_UNCONNECTED;\n wire NLW_input_fifo_full_UNCONNECTED;\n wire NLW_output_fifo1_empty_UNCONNECTED;\n wire NLW_output_fifo1_full_UNCONNECTED;\n wire [31:0]NLW_output_fifo1_dout_UNCONNECTED;\n wire NLW_output_fifo2_empty_UNCONNECTED;\n wire NLW_output_fifo2_full_UNCONNECTED;\n wire NLW_output_fifo2_prog_full_UNCONNECTED;\n wire [31:0]NLW_output_fifo2_dout_UNCONNECTED;\n\n LUT6 #(\n .INIT(64'h4440004000400040)) \n \\/i_ \n (.I0(write_state[2]),\n .I1(write_state[0]),\n .I2(s_axi_awready),\n .I3(write_state[1]),\n .I4(i__i_1_n_0),\n .I5(s_axi_wready),\n .O(write_count));\n LUT2 #(\n .INIT(4'h1)) \n \\FSM_sequential_write_state[0]_i_1 \n (.I0(write_state[0]),\n .I1(write_state[2]),\n .O(\\FSM_sequential_write_state[0]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h06)) \n \\FSM_sequential_write_state[1]_i_1 \n (.I0(write_state[1]),\n .I1(write_state[0]),\n .I2(write_state[2]),\n .O(\\FSM_sequential_write_state[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF000000A8)) \n \\FSM_sequential_write_state[2]_i_1 \n (.I0(\\FSM_sequential_write_state[2]_i_2_n_0 ),\n .I1(wr_adctrl_n_17),\n .I2(wr_adctrl_n_18),\n .I3(prog_empty),\n .I4(s_axi_awaddr[16]),\n .I5(\\FSM_sequential_write_state[2]_i_5_n_0 ),\n .O(\\FSM_sequential_write_state[2]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h1)) \n \\FSM_sequential_write_state[2]_i_2 \n (.I0(write_state[1]),\n .I1(write_state[0]),\n .O(\\FSM_sequential_write_state[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h105555AA100055AA)) \n \\FSM_sequential_write_state[2]_i_5 \n (.I0(write_state[2]),\n .I1(i__i_1_n_0),\n .I2(s_axi_wready),\n .I3(write_state[1]),\n .I4(write_state[0]),\n .I5(s_axi_awready),\n .O(\\FSM_sequential_write_state[2]_i_5_n_0 ));\n (* KEEP = \"yes\" *) \n FDCE #(\n .INIT(1'b0)) \n \\FSM_sequential_write_state_reg[0] \n (.C(ui_clk),\n .CE(\\FSM_sequential_write_state[2]_i_1_n_0 ),\n .CLR(rst),\n .D(\\FSM_sequential_write_state[0]_i_1_n_0 ),\n .Q(write_state[0]));\n (* KEEP = \"yes\" *) \n FDCE #(\n .INIT(1'b0)) \n \\FSM_sequential_write_state_reg[1] \n (.C(ui_clk),\n .CE(\\FSM_sequential_write_state[2]_i_1_n_0 ),\n .CLR(rst),\n .D(\\FSM_sequential_write_state[1]_i_1_n_0 ),\n .Q(write_state[1]));\n (* KEEP = \"yes\" *) \n FDCE #(\n .INIT(1'b0)) \n \\FSM_sequential_write_state_reg[2] \n (.C(ui_clk),\n .CE(\\FSM_sequential_write_state[2]_i_1_n_0 ),\n .CLR(rst),\n .D(D),\n .Q(write_state[2]));\n LUT3 #(\n .INIT(8'h02)) \n axi_awvalid\n (.I0(write_state[0]),\n .I1(write_state[2]),\n .I2(write_state[1]),\n .O(s_axi_awvalid));\n (* SOFT_HLUTNM = \"soft_lutpair13\" *) \n LUT5 #(\n .INIT(32'h80000000)) \n axi_wlast0\n (.I0(\\write_count_reg_n_0_[2] ),\n .I1(\\write_count_reg_n_0_[0] ),\n .I2(D),\n .I3(\\write_count_reg_n_0_[3] ),\n .I4(\\write_count_reg_n_0_[1] ),\n .O(s_axi_wlast));\n (* SOFT_HLUTNM = \"soft_lutpair13\" *) \n LUT4 #(\n .INIT(16'h7FFF)) \n i__i_1\n (.I0(\\write_count_reg_n_0_[3] ),\n .I1(\\write_count_reg_n_0_[2] ),\n .I2(\\write_count_reg_n_0_[0] ),\n .I3(\\write_count_reg_n_0_[1] ),\n .O(i__i_1_n_0));\n (* x_core_info = \"fifo_generator_v13_1_2,Vivado 2016.3\" *) \n fb_input_fifo input_fifo\n (.din({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .dout(dout),\n .empty(NLW_input_fifo_empty_UNCONNECTED),\n .full(NLW_input_fifo_full_UNCONNECTED),\n .prog_empty(prog_empty),\n .rd_clk(ui_clk),\n .rd_en(rd_en_0),\n .rst(rst),\n .wr_clk(CLK),\n .wr_en(wr_en));\n LUT3 #(\n .INIT(8'h40)) \n memctl_i_1\n (.I0(write_state[2]),\n .I1(write_state[0]),\n .I2(write_state[1]),\n .O(D));\n (* SOFT_HLUTNM = \"soft_lutpair16\" *) \n LUT2 #(\n .INIT(4'h2)) \n memctl_i_20\n (.I0(\\read_state_reg_n_0_[0] ),\n .I1(\\read_state_reg_n_0_[1] ),\n .O(s_axi_arvalid));\n FDPE #(\n .INIT(1'b1)) \n odd_pixel_reg\n (.C(bbstub_pixel_clock),\n .CE(1'b1),\n .D(odd_pixel_reg_1),\n .PRE(fbc_ovsync),\n .Q(odd_pixel));\n (* x_core_info = \"fifo_generator_v13_1_2,Vivado 2016.3\" *) \n fb_output_fifo output_fifo1\n (.din({s_axi_rdata[223:192],s_axi_rdata[159:128],s_axi_rdata[95:64],s_axi_rdata[31:0]}),\n .dout(NLW_output_fifo1_dout_UNCONNECTED[31:0]),\n .empty(NLW_output_fifo1_empty_UNCONNECTED),\n .full(NLW_output_fifo1_full_UNCONNECTED),\n .prog_full(prog_full),\n .rd_clk(bbstub_pixel_clock),\n .rd_en(rd_en),\n .rst(\\v_pos_reg[4] ),\n .wr_clk(ui_clk),\n .wr_en(output_fifo1_i_2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair15\" *) \n LUT3 #(\n .INIT(8'h40)) \n output_fifo1_i_2\n (.I0(\\read_state_reg_n_0_[0] ),\n .I1(s_axi_rvalid),\n .I2(\\read_state_reg_n_0_[1] ),\n .O(output_fifo1_i_2_n_0));\n (* x_core_info = \"fifo_generator_v13_1_2,Vivado 2016.3\" *) \n fb_output_fifo output_fifo2\n (.din({s_axi_rdata[255:224],s_axi_rdata[191:160],s_axi_rdata[127:96],s_axi_rdata[63:32]}),\n .dout(NLW_output_fifo2_dout_UNCONNECTED[31:0]),\n .empty(NLW_output_fifo2_empty_UNCONNECTED),\n .full(NLW_output_fifo2_full_UNCONNECTED),\n .prog_full(NLW_output_fifo2_prog_full_UNCONNECTED),\n .rd_clk(bbstub_pixel_clock),\n .rd_en(odd_pixel_reg_0),\n .rst(\\v_pos_reg[4] ),\n .wr_clk(ui_clk),\n .wr_en(output_fifo1_i_2_n_0));\n framebuffer_addr_ctrl__parameterized1 rd_adctrl_crop\n (.E(rd_adctrl_crop_n_0),\n .Q({\\read_state_reg_n_0_[1] ,\\read_state_reg_n_0_[0] }),\n .int_address_q_reg(int_address_q_reg),\n .\\int_address_q_reg[15]_0 (rd_adctrl_scale_n_17),\n .\\read_state_reg[1] (\\read_state[1]_i_3_n_0 ),\n .\\read_state_reg[1]_0 (\\read_state[1]_i_7_n_0 ),\n .s_axi_araddr(s_axi_araddr),\n .ui_clk(ui_clk),\n .\\v_pos_reg[4] (\\v_pos_reg[4] ),\n .zoom_mode_IBUF(zoom_mode_IBUF));\n framebuffer_addr_ctrl__parameterized0 rd_adctrl_scale\n (.Q({\\read_state_reg_n_0_[1] ,\\read_state_reg_n_0_[0] }),\n .int_address_q_reg(int_address_q_reg),\n .prog_full(prog_full),\n .\\read_state_reg[0] (rd_adctrl_scale_n_17),\n .ui_clk(ui_clk),\n .\\v_pos_reg[4] (\\v_pos_reg[4] ),\n .zoom_mode_IBUF(zoom_mode_IBUF));\n LUT4 #(\n .INIT(16'h2300)) \n rd_en0\n (.I0(s_axi_wready),\n .I1(write_state[2]),\n .I2(write_state[0]),\n .I3(write_state[1]),\n .O(rd_en_0));\n (* SOFT_HLUTNM = \"soft_lutpair14\" *) \n LUT4 #(\n .INIT(16'h4055)) \n \\read_state[0]_i_1 \n (.I0(\\read_state_reg_n_0_[0] ),\n .I1(s_axi_rvalid),\n .I2(s_axi_rlast),\n .I3(\\read_state_reg_n_0_[1] ),\n .O(\\read_state[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair14\" *) \n LUT4 #(\n .INIT(16'h40AA)) \n \\read_state[1]_i_2 \n (.I0(\\read_state_reg_n_0_[0] ),\n .I1(s_axi_rlast),\n .I2(s_axi_rvalid),\n .I3(\\read_state_reg_n_0_[1] ),\n .O(read_state));\n (* SOFT_HLUTNM = \"soft_lutpair15\" *) \n LUT3 #(\n .INIT(8'h80)) \n \\read_state[1]_i_3 \n (.I0(s_axi_rlast),\n .I1(s_axi_rvalid),\n .I2(\\read_state_reg_n_0_[1] ),\n .O(\\read_state[1]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair16\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\read_state[1]_i_7 \n (.I0(\\read_state_reg_n_0_[1] ),\n .I1(s_axi_arready),\n .O(\\read_state[1]_i_7_n_0 ));\n FDCE #(\n .INIT(1'b0)) \n \\read_state_reg[0] \n (.C(ui_clk),\n .CE(rd_adctrl_crop_n_0),\n .CLR(\\v_pos_reg[4] ),\n .D(\\read_state[0]_i_1_n_0 ),\n .Q(\\read_state_reg_n_0_[0] ));\n FDCE #(\n .INIT(1'b0)) \n \\read_state_reg[1] \n (.C(ui_clk),\n .CE(rd_adctrl_crop_n_0),\n .CLR(\\v_pos_reg[4] ),\n .D(read_state),\n .Q(\\read_state_reg_n_0_[1] ));\n framebuffer_addr_ctrl wr_adctrl\n (.\\FSM_sequential_write_state_reg[0] (wr_adctrl_n_17),\n .\\FSM_sequential_write_state_reg[0]_0 (wr_adctrl_n_18),\n .out(write_state),\n .rst(rst),\n .s_axi_awaddr(s_axi_awaddr),\n .ui_clk(ui_clk));\n LUT3 #(\n .INIT(8'h04)) \n \\write_count[0]_i_1 \n (.I0(write_state[2]),\n .I1(write_state[1]),\n .I2(\\write_count_reg_n_0_[0] ),\n .O(\\write_count[0]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h0440)) \n \\write_count[1]_i_1 \n (.I0(write_state[2]),\n .I1(write_state[1]),\n .I2(\\write_count_reg_n_0_[0] ),\n .I3(\\write_count_reg_n_0_[1] ),\n .O(\\write_count[1]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h04444000)) \n \\write_count[2]_i_1 \n (.I0(write_state[2]),\n .I1(write_state[1]),\n .I2(\\write_count_reg_n_0_[0] ),\n .I3(\\write_count_reg_n_0_[1] ),\n .I4(\\write_count_reg_n_0_[2] ),\n .O(\\write_count[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0444444440000000)) \n \\write_count[3]_i_1 \n (.I0(write_state[2]),\n .I1(write_state[1]),\n .I2(\\write_count_reg_n_0_[1] ),\n .I3(\\write_count_reg_n_0_[0] ),\n .I4(\\write_count_reg_n_0_[2] ),\n .I5(\\write_count_reg_n_0_[3] ),\n .O(\\write_count[3]_i_1_n_0 ));\n FDCE #(\n .INIT(1'b0)) \n \\write_count_reg[0] \n (.C(ui_clk),\n .CE(write_count),\n .CLR(rst),\n .D(\\write_count[0]_i_1_n_0 ),\n .Q(\\write_count_reg_n_0_[0] ));\n FDCE #(\n .INIT(1'b0)) \n \\write_count_reg[1] \n (.C(ui_clk),\n .CE(write_count),\n .CLR(rst),\n .D(\\write_count[1]_i_1_n_0 ),\n .Q(\\write_count_reg_n_0_[1] ));\n FDCE #(\n .INIT(1'b0)) \n \\write_count_reg[2] \n (.C(ui_clk),\n .CE(write_count),\n .CLR(rst),\n .D(\\write_count[2]_i_1_n_0 ),\n .Q(\\write_count_reg_n_0_[2] ));\n FDCE #(\n .INIT(1'b0)) \n \\write_count_reg[3] \n (.C(ui_clk),\n .CE(write_count),\n .CLR(rst),\n .D(\\write_count[3]_i_1_n_0 ),\n .Q(\\write_count_reg_n_0_[3] ));\nendmodule\n\nmodule framebuffer_top\n (ddr3_addr,\n ddr3_ba,\n ddr3_ras_n,\n ddr3_cas_n,\n ddr3_we_n,\n ddr3_reset_n,\n ddr3_ck_p,\n ddr3_ck_n,\n ddr3_cke,\n ddr3_cs_n,\n ddr3_dm,\n ddr3_odt,\n AR,\n dvi_den,\n D,\n ddr3_dq,\n ddr3_dqs_n,\n ddr3_dqs_p,\n rst,\n CLK,\n wr_en,\n bbstub_pixel_clock,\n sys_clk_i,\n reset_n_IBUF,\n zoom_mode_IBUF);\n output [14:0]ddr3_addr;\n output [2:0]ddr3_ba;\n output ddr3_ras_n;\n output ddr3_cas_n;\n output ddr3_we_n;\n output ddr3_reset_n;\n output [0:0]ddr3_ck_p;\n output [0:0]ddr3_ck_n;\n output [0:0]ddr3_cke;\n output [0:0]ddr3_cs_n;\n output [3:0]ddr3_dm;\n output [0:0]ddr3_odt;\n output [0:0]AR;\n output dvi_den;\n output [1:0]D;\n inout [31:0]ddr3_dq;\n inout [3:0]ddr3_dqs_n;\n inout [3:0]ddr3_dqs_p;\n input rst;\n input CLK;\n input wr_en;\n input bbstub_pixel_clock;\n input sys_clk_i;\n input reset_n_IBUF;\n input zoom_mode_IBUF;\n\n wire [0:0]AR;\n wire CLK;\n wire [1:0]D;\n wire [25:8]axi_araddr;\n wire axi_arready;\n wire axi_arvalid;\n wire [25:9]axi_awaddr;\n wire axi_awready;\n wire axi_awvalid;\n wire axi_bid;\n wire [1:0]axi_bresp;\n wire axi_bvalid;\n wire [255:0]axi_rdata;\n wire axi_rid;\n wire axi_rlast;\n wire [1:0]axi_rresp;\n wire axi_rvalid;\n wire [255:0]axi_wdata;\n wire axi_wlast;\n wire axi_wready;\n wire bbstub_pixel_clock;\n wire [14:0]ddr3_addr;\n wire [2:0]ddr3_ba;\n wire ddr3_cas_n;\n wire [0:0]ddr3_ck_n;\n wire [0:0]ddr3_ck_p;\n wire [0:0]ddr3_cke;\n wire [0:0]ddr3_cs_n;\n wire [3:0]ddr3_dm;\n wire [31:0]ddr3_dq;\n wire [3:0]ddr3_dqs_n;\n wire [3:0]ddr3_dqs_p;\n wire [0:0]ddr3_odt;\n wire ddr3_ras_n;\n wire ddr3_reset_n;\n wire ddr3_we_n;\n wire dvi_den;\n wire fbc_ovsync;\n wire fbctl_n_294;\n wire odd_pixel;\n wire output_n_2;\n wire output_n_3;\n wire output_n_7;\n wire output_n_8;\n wire reset_n_IBUF;\n wire rst;\n wire sys_clk_i;\n wire ui_clock;\n wire wr_en;\n wire zoom_mode_IBUF;\n wire NLW_memctl_app_ref_ack_UNCONNECTED;\n wire NLW_memctl_app_sr_active_UNCONNECTED;\n wire NLW_memctl_app_zq_ack_UNCONNECTED;\n wire NLW_memctl_init_calib_complete_UNCONNECTED;\n wire NLW_memctl_mmcm_locked_UNCONNECTED;\n wire NLW_memctl_ui_clk_sync_rst_UNCONNECTED;\n wire [11:0]NLW_memctl_device_temp_UNCONNECTED;\n\n framebuffer_ctrl_crop_scale fbctl\n (.CLK(CLK),\n .D(fbctl_n_294),\n .bbstub_pixel_clock(bbstub_pixel_clock),\n .dout(axi_wdata),\n .fbc_ovsync(fbc_ovsync),\n .odd_pixel(odd_pixel),\n .odd_pixel_reg_0(output_n_3),\n .odd_pixel_reg_1(output_n_7),\n .rd_en(output_n_2),\n .rst(rst),\n .s_axi_araddr(axi_araddr),\n .s_axi_arready(axi_arready),\n .s_axi_arvalid(axi_arvalid),\n .s_axi_awaddr(axi_awaddr),\n .s_axi_awready(axi_awready),\n .s_axi_awvalid(axi_awvalid),\n .s_axi_rdata(axi_rdata),\n .s_axi_rlast(axi_rlast),\n .s_axi_rvalid(axi_rvalid),\n .s_axi_wlast(axi_wlast),\n .s_axi_wready(axi_wready),\n .ui_clk(ui_clock),\n .\\v_pos_reg[4] (output_n_8),\n .wr_en(wr_en),\n .zoom_mode_IBUF(zoom_mode_IBUF));\n ddr3_if memctl\n (.app_ref_ack(NLW_memctl_app_ref_ack_UNCONNECTED),\n .app_ref_req(1'b0),\n .app_sr_active(NLW_memctl_app_sr_active_UNCONNECTED),\n .app_sr_req(1'b0),\n .app_zq_ack(NLW_memctl_app_zq_ack_UNCONNECTED),\n .app_zq_req(1'b0),\n .aresetn(reset_n_IBUF),\n .ddr3_addr(ddr3_addr),\n .ddr3_ba(ddr3_ba),\n .ddr3_cas_n(ddr3_cas_n),\n .ddr3_ck_n(ddr3_ck_n),\n .ddr3_ck_p(ddr3_ck_p),\n .ddr3_cke(ddr3_cke),\n .ddr3_cs_n(ddr3_cs_n),\n .ddr3_dm(ddr3_dm),\n .ddr3_dq(ddr3_dq),\n .ddr3_dqs_n(ddr3_dqs_n),\n .ddr3_dqs_p(ddr3_dqs_p),\n .ddr3_odt(ddr3_odt),\n .ddr3_ras_n(ddr3_ras_n),\n .ddr3_reset_n(ddr3_reset_n),\n .ddr3_we_n(ddr3_we_n),\n .device_temp(NLW_memctl_device_temp_UNCONNECTED[11:0]),\n .init_calib_complete(NLW_memctl_init_calib_complete_UNCONNECTED),\n .mmcm_locked(NLW_memctl_mmcm_locked_UNCONNECTED),\n .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,axi_araddr,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axi_arburst({1'b0,1'b1}),\n .s_axi_arcache({1'b0,1'b0,1'b1,1'b1}),\n .s_axi_arid(1'b1),\n .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1}),\n .s_axi_arlock(1'b0),\n .s_axi_arprot({1'b0,1'b0,1'b0}),\n .s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),\n .s_axi_arready(axi_arready),\n .s_axi_arsize({1'b0,1'b1,1'b0}),\n .s_axi_arvalid(axi_arvalid),\n .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,axi_awaddr,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axi_awburst({1'b0,1'b1}),\n .s_axi_awcache({1'b0,1'b0,1'b1,1'b1}),\n .s_axi_awid(1'b0),\n .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1}),\n .s_axi_awlock(1'b0),\n .s_axi_awprot({1'b0,1'b0,1'b0}),\n .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),\n .s_axi_awready(axi_awready),\n .s_axi_awsize({1'b0,1'b1,1'b0}),\n .s_axi_awvalid(axi_awvalid),\n .s_axi_bid(axi_bid),\n .s_axi_bready(1'b1),\n .s_axi_bresp(axi_bresp),\n .s_axi_bvalid(axi_bvalid),\n .s_axi_rdata(axi_rdata),\n .s_axi_rid(axi_rid),\n .s_axi_rlast(axi_rlast),\n .s_axi_rready(1'b1),\n .s_axi_rresp(axi_rresp),\n .s_axi_rvalid(axi_rvalid),\n .s_axi_wdata(axi_wdata),\n .s_axi_wlast(axi_wlast),\n .s_axi_wready(axi_wready),\n .s_axi_wstrb({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .s_axi_wvalid(fbctl_n_294),\n .sys_clk_i(sys_clk_i),\n .sys_rst(AR),\n .ui_clk(ui_clock),\n .ui_clk_sync_rst(NLW_memctl_ui_clk_sync_rst_UNCONNECTED));\n video_fb_output \\output \n (.AR(AR),\n .D(D),\n .bbstub_pixel_clock(bbstub_pixel_clock),\n .dvi_den(dvi_den),\n .fbc_ovsync(fbc_ovsync),\n .\\int_address_q_reg[23] (output_n_8),\n .odd_pixel(odd_pixel),\n .odd_pixel_reg(output_n_7),\n .output_fifo2(output_n_3),\n .rd_en(output_n_2),\n .reset_n_IBUF(reset_n_IBUF),\n .zoom_mode_IBUF(zoom_mode_IBUF));\nendmodule\n\n(* NotValidForBitStream *)\nmodule genesys2_fbtest\n (clock_p,\n clock_n,\n reset_n,\n hdmi_clk,\n hdmi_d0,\n hdmi_d1,\n hdmi_d2,\n zoom_mode,\n ddr3_addr,\n ddr3_ba,\n ddr3_cas_n,\n ddr3_ck_n,\n ddr3_ck_p,\n ddr3_cke,\n ddr3_ras_n,\n ddr3_reset_n,\n ddr3_we_n,\n ddr3_dq,\n ddr3_dqs_n,\n ddr3_dqs_p,\n ddr3_cs_n,\n ddr3_dm,\n ddr3_odt);\n input clock_p;\n input clock_n;\n input reset_n;\n output [1:0]hdmi_clk;\n output [1:0]hdmi_d0;\n output [1:0]hdmi_d1;\n output [1:0]hdmi_d2;\n input zoom_mode;\n (* CLOCK_BUFFER_TYPE = \"none\" *) output [14:0]ddr3_addr;\n (* CLOCK_BUFFER_TYPE = \"none\" *) output [2:0]ddr3_ba;\n (* CLOCK_BUFFER_TYPE = \"none\" *) output ddr3_cas_n;\n output [0:0]ddr3_ck_n;\n output [0:0]ddr3_ck_p;\n (* CLOCK_BUFFER_TYPE = \"none\" *) output [0:0]ddr3_cke;\n (* CLOCK_BUFFER_TYPE = \"none\" *) output ddr3_ras_n;\n (* CLOCK_BUFFER_TYPE = \"none\" *) output ddr3_reset_n;\n (* CLOCK_BUFFER_TYPE = \"none\" *) output ddr3_we_n;\n (* CLOCK_BUFFER_TYPE = \"none\" *) inout [31:0]ddr3_dq;\n (* CLOCK_BUFFER_TYPE = \"none\" *) inout [3:0]ddr3_dqs_n;\n (* CLOCK_BUFFER_TYPE = \"none\" *) inout [3:0]ddr3_dqs_p;\n (* CLOCK_BUFFER_TYPE = \"none\" *) output [0:0]ddr3_cs_n;\n (* CLOCK_BUFFER_TYPE = \"none\" *) output [3:0]ddr3_dm;\n (* CLOCK_BUFFER_TYPE = \"none\" *) output [0:0]ddr3_odt;\n\n (* DIFF_TERM *) (* IBUF_LOW_PWR = 0 *) wire clock_n;\n (* DIFF_TERM *) (* IBUF_LOW_PWR = 0 *) wire clock_p;\n wire [14:0]ddr3_addr;\n wire [2:0]ddr3_ba;\n wire ddr3_cas_n;\n wire [0:0]ddr3_ck_n;\n wire [0:0]ddr3_ck_p;\n wire [0:0]ddr3_cke;\n wire [0:0]ddr3_cs_n;\n wire [3:0]ddr3_dm;\n (* IBUF_LOW_PWR = 0 *) wire [31:0]ddr3_dq;\n (* DIFF_TERM = 0 *) (* IBUF_LOW_PWR = 0 *) wire [3:0]ddr3_dqs_n;\n (* DIFF_TERM = 0 *) (* IBUF_LOW_PWR = 0 *) wire [3:0]ddr3_dqs_p;\n wire [0:0]ddr3_odt;\n wire ddr3_ras_n;\n (* DRIVE = \"12\" *) wire ddr3_reset_n;\n wire ddr3_we_n;\n wire dvi_bit_clock;\n wire dvi_den;\n wire dvi_pixel_clock;\n wire [1:0]hdmi_clk;\n wire [1:0]hdmi_d0;\n wire [1:0]hdmi_d1;\n wire [1:0]hdmi_d2;\n wire hsync_pos;\n wire input_den;\n wire input_pixel_clock;\n wire reset;\n wire reset_n;\n wire reset_n_IBUF;\n wire sys_clock;\n wire tp_n_1;\n wire vsync_pos;\n wire zoom_mode;\n wire zoom_mode_IBUF;\n\n (* CAPACITANCE = \"DONT_CARE\" *) \n (* IBUF_DELAY_VALUE = \"0\" *) \n (* XILINX_LEGACY_PRIM = \"IBUFGDS\" *) \n (* box_type = \"PRIMITIVE\" *) \n IBUFDS #(\n .DQS_BIAS(\"FALSE\"),\n .IOSTANDARD(\"DEFAULT\")) \n clkbuf\n (.I(clock_p),\n .IB(clock_n),\n .O(sys_clock));\n dvi_tx dvi_tx\n (.D({vsync_pos,hsync_pos}),\n .SR(reset),\n .dvi_bit_clock(dvi_bit_clock),\n .dvi_den(dvi_den),\n .hdmi_clk(hdmi_clk),\n .hdmi_d0(hdmi_d0),\n .hdmi_d1(hdmi_d1),\n .hdmi_d2(hdmi_d2),\n .pixel_clock(dvi_pixel_clock),\n .reset_n_IBUF(reset_n_IBUF));\n framebuffer_top fbtest\n (.AR(reset),\n .CLK(input_pixel_clock),\n .D({vsync_pos,hsync_pos}),\n .bbstub_pixel_clock(dvi_pixel_clock),\n .ddr3_addr(ddr3_addr),\n .ddr3_ba(ddr3_ba),\n .ddr3_cas_n(ddr3_cas_n),\n .ddr3_ck_n(ddr3_ck_n),\n .ddr3_ck_p(ddr3_ck_p),\n .ddr3_cke(ddr3_cke),\n .ddr3_cs_n(ddr3_cs_n),\n .ddr3_dm(ddr3_dm),\n .ddr3_dq(ddr3_dq),\n .ddr3_dqs_n(ddr3_dqs_n),\n .ddr3_dqs_p(ddr3_dqs_p),\n .ddr3_odt(ddr3_odt),\n .ddr3_ras_n(ddr3_ras_n),\n .ddr3_reset_n(ddr3_reset_n),\n .ddr3_we_n(ddr3_we_n),\n .dvi_den(dvi_den),\n .reset_n_IBUF(reset_n_IBUF),\n .rst(tp_n_1),\n .sys_clk_i(sys_clock),\n .wr_en(input_den),\n .zoom_mode_IBUF(zoom_mode_IBUF));\n dvi_pll pll1\n (.dvi_bit_clock(dvi_bit_clock),\n .pixel_clock(dvi_pixel_clock),\n .sysclk(sys_clock));\n camera_pll pll2\n (.camera_pixel_clock(input_pixel_clock),\n .sysclk(sys_clock));\n IBUF reset_n_IBUF_inst\n (.I(reset_n),\n .O(reset_n_IBUF));\n test_pattern_gen tp\n (.AR(reset),\n .CLK(input_pixel_clock),\n .reset_n_IBUF(reset_n_IBUF),\n .rst(tp_n_1),\n .wr_en(input_den));\n IBUF zoom_mode_IBUF_inst\n (.I(zoom_mode),\n .O(zoom_mode_IBUF));\nendmodule\n\nmodule test_pattern_gen\n (wr_en,\n rst,\n reset_n_IBUF,\n CLK,\n AR);\n output wr_en;\n output rst;\n input reset_n_IBUF;\n input CLK;\n input [0:0]AR;\n\n wire [0:0]AR;\n wire CLK;\n wire reset_n_IBUF;\n wire rst;\n wire wr_en;\n\n video_timing_ctrl__parameterized0 tmg_gen\n (.AR(AR),\n .CLK(CLK),\n .reset_n_IBUF(reset_n_IBUF),\n .rst(rst),\n .wr_en(wr_en));\nendmodule\n\nmodule video_fb_output\n (AR,\n dvi_den,\n rd_en,\n output_fifo2,\n D,\n fbc_ovsync,\n odd_pixel_reg,\n \\int_address_q_reg[23] ,\n reset_n_IBUF,\n odd_pixel,\n zoom_mode_IBUF,\n bbstub_pixel_clock);\n output [0:0]AR;\n output dvi_den;\n output rd_en;\n output output_fifo2;\n output [1:0]D;\n output fbc_ovsync;\n output odd_pixel_reg;\n output \\int_address_q_reg[23] ;\n input reset_n_IBUF;\n input odd_pixel;\n input zoom_mode_IBUF;\n input bbstub_pixel_clock;\n\n wire [0:0]AR;\n wire [1:0]D;\n wire bbstub_pixel_clock;\n wire dvi_den;\n wire fbc_ovsync;\n wire \\int_address_q_reg[23] ;\n wire odd_pixel;\n wire odd_pixel_reg;\n wire output_fifo2;\n wire rd_en;\n wire reset_n_IBUF;\n wire zoom_mode_IBUF;\n\n video_timing_ctrl tmg_gen\n (.AR(AR),\n .D(D),\n .bbstub_pixel_clock(bbstub_pixel_clock),\n .dvi_den(dvi_den),\n .fbc_ovsync(fbc_ovsync),\n .\\int_address_q_reg[23] (\\int_address_q_reg[23] ),\n .odd_pixel(odd_pixel),\n .odd_pixel_reg(odd_pixel_reg),\n .output_fifo2(output_fifo2),\n .rd_en(rd_en),\n .reset_n_IBUF(reset_n_IBUF),\n .zoom_mode_IBUF(zoom_mode_IBUF));\nendmodule\n\nmodule video_timing_ctrl\n (AR,\n dvi_den,\n rd_en,\n output_fifo2,\n D,\n fbc_ovsync,\n odd_pixel_reg,\n \\int_address_q_reg[23] ,\n reset_n_IBUF,\n odd_pixel,\n zoom_mode_IBUF,\n bbstub_pixel_clock);\n output [0:0]AR;\n output dvi_den;\n output rd_en;\n output output_fifo2;\n output [1:0]D;\n output fbc_ovsync;\n output odd_pixel_reg;\n output \\int_address_q_reg[23] ;\n input reset_n_IBUF;\n input odd_pixel;\n input zoom_mode_IBUF;\n input bbstub_pixel_clock;\n\n wire [0:0]AR;\n wire [1:0]D;\n wire bbstub_pixel_clock;\n wire \\ctrl_lat[0]_i_2_n_0 ;\n wire \\ctrl_lat[1]_i_2_n_0 ;\n wire [11:1]data0;\n wire den_lat_i_2_n_0;\n wire den_lat_i_3_n_0;\n wire dvi_den;\n wire fbc_ovsync;\n wire [11:0]h_pos;\n wire \\h_pos[11]_i_2_n_0 ;\n wire \\h_pos[11]_i_3_n_0 ;\n wire \\h_pos[11]_i_5_n_0 ;\n wire \\h_pos[11]_i_6_n_0 ;\n wire \\h_pos[11]_i_7_n_0 ;\n wire \\h_pos[4]_i_3_n_0 ;\n wire \\h_pos[4]_i_4_n_0 ;\n wire \\h_pos[4]_i_5_n_0 ;\n wire \\h_pos[4]_i_6_n_0 ;\n wire \\h_pos[8]_i_3_n_0 ;\n wire \\h_pos[8]_i_4_n_0 ;\n wire \\h_pos[8]_i_5_n_0 ;\n wire \\h_pos[8]_i_6_n_0 ;\n wire \\h_pos_reg[11]_i_4_n_2 ;\n wire \\h_pos_reg[11]_i_4_n_3 ;\n wire \\h_pos_reg[4]_i_2_n_0 ;\n wire \\h_pos_reg[4]_i_2_n_1 ;\n wire \\h_pos_reg[4]_i_2_n_2 ;\n wire \\h_pos_reg[4]_i_2_n_3 ;\n wire \\h_pos_reg[8]_i_2_n_0 ;\n wire \\h_pos_reg[8]_i_2_n_1 ;\n wire \\h_pos_reg[8]_i_2_n_2 ;\n wire \\h_pos_reg[8]_i_2_n_3 ;\n wire \\int_address_q_reg[23] ;\n wire odd_pixel;\n wire odd_pixel_i_3_n_0;\n wire odd_pixel_reg;\n wire output_fifo1_i_10_n_0;\n wire output_fifo1_i_4_n_0;\n wire output_fifo1_i_5_n_0;\n wire output_fifo1_i_6_n_0;\n wire output_fifo1_i_7_n_0;\n wire output_fifo1_i_8_n_0;\n wire output_fifo1_i_9_n_0;\n wire output_fifo2;\n wire rd_en;\n wire reset_n_IBUF;\n wire [11:0]timing_h_pos;\n wire [10:0]timing_v_pos;\n wire [10:0]v_pos;\n wire v_pos0;\n wire \\v_pos[10]_i_3_n_0 ;\n wire \\v_pos[10]_i_4_n_0 ;\n wire \\v_pos[10]_i_5_n_0 ;\n wire \\v_pos[10]_i_6_n_0 ;\n wire \\v_pos[2]_i_2_n_0 ;\n wire \\v_pos[2]_i_3_n_0 ;\n wire \\v_pos[9]_i_2_n_0 ;\n wire zoom_mode_IBUF;\n wire [3:2]\\NLW_h_pos_reg[11]_i_4_CO_UNCONNECTED ;\n wire [3:3]\\NLW_h_pos_reg[11]_i_4_O_UNCONNECTED ;\n\n LUT5 #(\n .INIT(32'h000015FF)) \n \\ctrl_lat[0]_i_1 \n (.I0(timing_h_pos[4]),\n .I1(timing_h_pos[3]),\n .I2(timing_h_pos[2]),\n .I3(timing_h_pos[5]),\n .I4(\\ctrl_lat[0]_i_2_n_0 ),\n .O(D[0]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\ctrl_lat[0]_i_2 \n (.I0(timing_h_pos[9]),\n .I1(timing_h_pos[8]),\n .I2(timing_h_pos[10]),\n .I3(timing_h_pos[6]),\n .I4(timing_h_pos[11]),\n .I5(timing_h_pos[7]),\n .O(\\ctrl_lat[0]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair19\" *) \n LUT4 #(\n .INIT(16'h001F)) \n \\ctrl_lat[1]_i_1 \n (.I0(timing_v_pos[1]),\n .I1(timing_v_pos[0]),\n .I2(timing_v_pos[2]),\n .I3(\\ctrl_lat[1]_i_2_n_0 ),\n .O(D[1]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\ctrl_lat[1]_i_2 \n (.I0(timing_v_pos[6]),\n .I1(\\v_pos[2]_i_2_n_0 ),\n .I2(timing_v_pos[10]),\n .I3(timing_v_pos[4]),\n .I4(timing_v_pos[3]),\n .I5(timing_v_pos[5]),\n .O(\\ctrl_lat[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0C0C04040C0C0040)) \n den_lat_i_1\n (.I0(den_lat_i_2_n_0),\n .I1(output_fifo1_i_7_n_0),\n .I2(timing_h_pos[11]),\n .I3(timing_h_pos[2]),\n .I4(den_lat_i_3_n_0),\n .I5(timing_h_pos[3]),\n .O(dvi_den));\n LUT4 #(\n .INIT(16'h0010)) \n den_lat_i_2\n (.I0(timing_h_pos[0]),\n .I1(timing_h_pos[2]),\n .I2(timing_h_pos[3]),\n .I3(timing_h_pos[1]),\n .O(den_lat_i_2_n_0));\n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n den_lat_i_3\n (.I0(\\h_pos[11]_i_2_n_0 ),\n .I1(timing_h_pos[7]),\n .I2(timing_h_pos[4]),\n .I3(timing_h_pos[6]),\n .I4(timing_h_pos[5]),\n .O(den_lat_i_3_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair18\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\h_pos[0]_i_1 \n (.I0(timing_h_pos[0]),\n .O(h_pos[0]));\n LUT6 #(\n .INIT(64'hFFFFFFFE00000000)) \n \\h_pos[10]_i_1__0 \n (.I0(\\h_pos[11]_i_2_n_0 ),\n .I1(timing_h_pos[3]),\n .I2(timing_h_pos[5]),\n .I3(timing_h_pos[6]),\n .I4(\\h_pos[11]_i_3_n_0 ),\n .I5(data0[10]),\n .O(h_pos[10]));\n LUT6 #(\n .INIT(64'hFFFFFFFE00000000)) \n \\h_pos[11]_i_1 \n (.I0(\\h_pos[11]_i_2_n_0 ),\n .I1(timing_h_pos[3]),\n .I2(timing_h_pos[5]),\n .I3(timing_h_pos[6]),\n .I4(\\h_pos[11]_i_3_n_0 ),\n .I5(data0[11]),\n .O(h_pos[11]));\n LUT3 #(\n .INIT(8'hFE)) \n \\h_pos[11]_i_2 \n (.I0(timing_h_pos[10]),\n .I1(timing_h_pos[8]),\n .I2(timing_h_pos[9]),\n .O(\\h_pos[11]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h7FFFFFFFFFFFFFFF)) \n \\h_pos[11]_i_3 \n (.I0(timing_h_pos[0]),\n .I1(timing_h_pos[1]),\n .I2(timing_h_pos[4]),\n .I3(timing_h_pos[11]),\n .I4(timing_h_pos[7]),\n .I5(timing_h_pos[2]),\n .O(\\h_pos[11]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\h_pos[11]_i_5 \n (.I0(timing_h_pos[11]),\n .O(\\h_pos[11]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\h_pos[11]_i_6 \n (.I0(timing_h_pos[10]),\n .O(\\h_pos[11]_i_6_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\h_pos[11]_i_7 \n (.I0(timing_h_pos[9]),\n .O(\\h_pos[11]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFE00000000)) \n \\h_pos[1]_i_1 \n (.I0(\\h_pos[11]_i_2_n_0 ),\n .I1(timing_h_pos[3]),\n .I2(timing_h_pos[5]),\n .I3(timing_h_pos[6]),\n .I4(\\h_pos[11]_i_3_n_0 ),\n .I5(data0[1]),\n .O(h_pos[1]));\n LUT6 #(\n .INIT(64'hFFFFFFFE00000000)) \n \\h_pos[2]_i_1 \n (.I0(\\h_pos[11]_i_2_n_0 ),\n .I1(timing_h_pos[3]),\n .I2(timing_h_pos[5]),\n .I3(timing_h_pos[6]),\n .I4(\\h_pos[11]_i_3_n_0 ),\n .I5(data0[2]),\n .O(h_pos[2]));\n LUT6 #(\n .INIT(64'hFFFFFFFE00000000)) \n \\h_pos[3]_i_1__0 \n (.I0(\\h_pos[11]_i_2_n_0 ),\n .I1(timing_h_pos[3]),\n .I2(timing_h_pos[5]),\n .I3(timing_h_pos[6]),\n .I4(\\h_pos[11]_i_3_n_0 ),\n .I5(data0[3]),\n .O(h_pos[3]));\n LUT6 #(\n .INIT(64'hFFFFFFFE00000000)) \n \\h_pos[4]_i_1__0 \n (.I0(\\h_pos[11]_i_2_n_0 ),\n .I1(timing_h_pos[3]),\n .I2(timing_h_pos[5]),\n .I3(timing_h_pos[6]),\n .I4(\\h_pos[11]_i_3_n_0 ),\n .I5(data0[4]),\n .O(h_pos[4]));\n LUT1 #(\n .INIT(2'h2)) \n \\h_pos[4]_i_3 \n (.I0(timing_h_pos[4]),\n .O(\\h_pos[4]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\h_pos[4]_i_4 \n (.I0(timing_h_pos[3]),\n .O(\\h_pos[4]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\h_pos[4]_i_5 \n (.I0(timing_h_pos[2]),\n .O(\\h_pos[4]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\h_pos[4]_i_6 \n (.I0(timing_h_pos[1]),\n .O(\\h_pos[4]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFE00000000)) \n \\h_pos[5]_i_1__0 \n (.I0(\\h_pos[11]_i_2_n_0 ),\n .I1(timing_h_pos[3]),\n .I2(timing_h_pos[5]),\n .I3(timing_h_pos[6]),\n .I4(\\h_pos[11]_i_3_n_0 ),\n .I5(data0[5]),\n .O(h_pos[5]));\n LUT6 #(\n .INIT(64'hFFFFFFFE00000000)) \n \\h_pos[6]_i_1__0 \n (.I0(\\h_pos[11]_i_2_n_0 ),\n .I1(timing_h_pos[3]),\n .I2(timing_h_pos[5]),\n .I3(timing_h_pos[6]),\n .I4(\\h_pos[11]_i_3_n_0 ),\n .I5(data0[6]),\n .O(h_pos[6]));\n LUT6 #(\n .INIT(64'hFFFFFFFE00000000)) \n \\h_pos[7]_i_1__0 \n (.I0(\\h_pos[11]_i_2_n_0 ),\n .I1(timing_h_pos[3]),\n .I2(timing_h_pos[5]),\n .I3(timing_h_pos[6]),\n .I4(\\h_pos[11]_i_3_n_0 ),\n .I5(data0[7]),\n .O(h_pos[7]));\n LUT6 #(\n .INIT(64'hFFFFFFFE00000000)) \n \\h_pos[8]_i_1__0 \n (.I0(\\h_pos[11]_i_2_n_0 ),\n .I1(timing_h_pos[3]),\n .I2(timing_h_pos[5]),\n .I3(timing_h_pos[6]),\n .I4(\\h_pos[11]_i_3_n_0 ),\n .I5(data0[8]),\n .O(h_pos[8]));\n LUT1 #(\n .INIT(2'h2)) \n \\h_pos[8]_i_3 \n (.I0(timing_h_pos[8]),\n .O(\\h_pos[8]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\h_pos[8]_i_4 \n (.I0(timing_h_pos[7]),\n .O(\\h_pos[8]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\h_pos[8]_i_5 \n (.I0(timing_h_pos[6]),\n .O(\\h_pos[8]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\h_pos[8]_i_6 \n (.I0(timing_h_pos[5]),\n .O(\\h_pos[8]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFE00000000)) \n \\h_pos[9]_i_1__0 \n (.I0(\\h_pos[11]_i_2_n_0 ),\n .I1(timing_h_pos[3]),\n .I2(timing_h_pos[5]),\n .I3(timing_h_pos[6]),\n .I4(\\h_pos[11]_i_3_n_0 ),\n .I5(data0[9]),\n .O(h_pos[9]));\n FDCE #(\n .INIT(1'b0)) \n \\h_pos_reg[0] \n (.C(bbstub_pixel_clock),\n .CE(1'b1),\n .CLR(AR),\n .D(h_pos[0]),\n .Q(timing_h_pos[0]));\n FDCE #(\n .INIT(1'b0)) \n \\h_pos_reg[10] \n (.C(bbstub_pixel_clock),\n .CE(1'b1),\n .CLR(AR),\n .D(h_pos[10]),\n .Q(timing_h_pos[10]));\n FDCE #(\n .INIT(1'b0)) \n \\h_pos_reg[11] \n (.C(bbstub_pixel_clock),\n .CE(1'b1),\n .CLR(AR),\n .D(h_pos[11]),\n .Q(timing_h_pos[11]));\n CARRY4 \\h_pos_reg[11]_i_4 \n (.CI(\\h_pos_reg[8]_i_2_n_0 ),\n .CO({\\NLW_h_pos_reg[11]_i_4_CO_UNCONNECTED [3:2],\\h_pos_reg[11]_i_4_n_2 ,\\h_pos_reg[11]_i_4_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\NLW_h_pos_reg[11]_i_4_O_UNCONNECTED [3],data0[11:9]}),\n .S({1'b0,\\h_pos[11]_i_5_n_0 ,\\h_pos[11]_i_6_n_0 ,\\h_pos[11]_i_7_n_0 }));\n FDCE #(\n .INIT(1'b0)) \n \\h_pos_reg[1] \n (.C(bbstub_pixel_clock),\n .CE(1'b1),\n .CLR(AR),\n .D(h_pos[1]),\n .Q(timing_h_pos[1]));\n FDCE #(\n .INIT(1'b0)) \n \\h_pos_reg[2] \n (.C(bbstub_pixel_clock),\n .CE(1'b1),\n .CLR(AR),\n .D(h_pos[2]),\n .Q(timing_h_pos[2]));\n FDCE #(\n .INIT(1'b0)) \n \\h_pos_reg[3] \n (.C(bbstub_pixel_clock),\n .CE(1'b1),\n .CLR(AR),\n .D(h_pos[3]),\n .Q(timing_h_pos[3]));\n FDCE #(\n .INIT(1'b0)) \n \\h_pos_reg[4] \n (.C(bbstub_pixel_clock),\n .CE(1'b1),\n .CLR(AR),\n .D(h_pos[4]),\n .Q(timing_h_pos[4]));\n CARRY4 \\h_pos_reg[4]_i_2 \n (.CI(1'b0),\n .CO({\\h_pos_reg[4]_i_2_n_0 ,\\h_pos_reg[4]_i_2_n_1 ,\\h_pos_reg[4]_i_2_n_2 ,\\h_pos_reg[4]_i_2_n_3 }),\n .CYINIT(timing_h_pos[0]),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(data0[4:1]),\n .S({\\h_pos[4]_i_3_n_0 ,\\h_pos[4]_i_4_n_0 ,\\h_pos[4]_i_5_n_0 ,\\h_pos[4]_i_6_n_0 }));\n FDCE #(\n .INIT(1'b0)) \n \\h_pos_reg[5] \n (.C(bbstub_pixel_clock),\n .CE(1'b1),\n .CLR(AR),\n .D(h_pos[5]),\n .Q(timing_h_pos[5]));\n FDCE #(\n .INIT(1'b0)) \n \\h_pos_reg[6] \n (.C(bbstub_pixel_clock),\n .CE(1'b1),\n .CLR(AR),\n .D(h_pos[6]),\n .Q(timing_h_pos[6]));\n FDCE #(\n .INIT(1'b0)) \n \\h_pos_reg[7] \n (.C(bbstub_pixel_clock),\n .CE(1'b1),\n .CLR(AR),\n .D(h_pos[7]),\n .Q(timing_h_pos[7]));\n FDCE #(\n .INIT(1'b0)) \n \\h_pos_reg[8] \n (.C(bbstub_pixel_clock),\n .CE(1'b1),\n .CLR(AR),\n .D(h_pos[8]),\n .Q(timing_h_pos[8]));\n CARRY4 \\h_pos_reg[8]_i_2 \n (.CI(\\h_pos_reg[4]_i_2_n_0 ),\n .CO({\\h_pos_reg[8]_i_2_n_0 ,\\h_pos_reg[8]_i_2_n_1 ,\\h_pos_reg[8]_i_2_n_2 ,\\h_pos_reg[8]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(data0[8:5]),\n .S({\\h_pos[8]_i_3_n_0 ,\\h_pos[8]_i_4_n_0 ,\\h_pos[8]_i_5_n_0 ,\\h_pos[8]_i_6_n_0 }));\n FDCE #(\n .INIT(1'b0)) \n \\h_pos_reg[9] \n (.C(bbstub_pixel_clock),\n .CE(1'b1),\n .CLR(AR),\n .D(h_pos[9]),\n .Q(timing_h_pos[9]));\n LUT1 #(\n .INIT(2'h1)) \n memctl_i_21\n (.I0(reset_n_IBUF),\n .O(AR));\n LUT3 #(\n .INIT(8'hB4)) \n odd_pixel_i_1\n (.I0(output_fifo1_i_6_n_0),\n .I1(output_fifo1_i_7_n_0),\n .I2(odd_pixel),\n .O(odd_pixel_reg));\n LUT6 #(\n .INIT(64'h0000000000000001)) \n odd_pixel_i_2\n (.I0(odd_pixel_i_3_n_0),\n .I1(timing_v_pos[2]),\n .I2(timing_v_pos[5]),\n .I3(timing_v_pos[3]),\n .I4(timing_v_pos[4]),\n .I5(output_fifo1_i_4_n_0),\n .O(fbc_ovsync));\n (* SOFT_HLUTNM = \"soft_lutpair17\" *) \n LUT2 #(\n .INIT(4'hE)) \n odd_pixel_i_3\n (.I0(timing_v_pos[1]),\n .I1(timing_v_pos[0]),\n .O(odd_pixel_i_3_n_0));\n LUT6 #(\n .INIT(64'h00010000FFFFFFFF)) \n output_fifo1_i_1\n (.I0(output_fifo1_i_4_n_0),\n .I1(timing_v_pos[4]),\n .I2(timing_v_pos[3]),\n .I3(timing_v_pos[5]),\n .I4(output_fifo1_i_5_n_0),\n .I5(reset_n_IBUF),\n .O(\\int_address_q_reg[23] ));\n (* SOFT_HLUTNM = \"soft_lutpair21\" *) \n LUT3 #(\n .INIT(8'hFE)) \n output_fifo1_i_10\n (.I0(timing_v_pos[5]),\n .I1(timing_v_pos[3]),\n .I2(timing_v_pos[4]),\n .O(output_fifo1_i_10_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair20\" *) \n LUT4 #(\n .INIT(16'h4044)) \n output_fifo1_i_3\n (.I0(output_fifo1_i_6_n_0),\n .I1(output_fifo1_i_7_n_0),\n .I2(odd_pixel),\n .I3(zoom_mode_IBUF),\n .O(rd_en));\n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n output_fifo1_i_4\n (.I0(timing_v_pos[10]),\n .I1(timing_v_pos[7]),\n .I2(timing_v_pos[9]),\n .I3(timing_v_pos[8]),\n .I4(timing_v_pos[6]),\n .O(output_fifo1_i_4_n_0));\n LUT3 #(\n .INIT(8'h01)) \n output_fifo1_i_5\n (.I0(timing_v_pos[2]),\n .I1(timing_v_pos[0]),\n .I2(timing_v_pos[1]),\n .O(output_fifo1_i_5_n_0));\n LUT6 #(\n .INIT(64'hFFFFFEFF05051505)) \n output_fifo1_i_6\n (.I0(\\h_pos[11]_i_2_n_0 ),\n .I1(timing_h_pos[2]),\n .I2(timing_h_pos[7]),\n .I3(output_fifo1_i_8_n_0),\n .I4(timing_h_pos[4]),\n .I5(timing_h_pos[11]),\n .O(output_fifo1_i_6_n_0));\n LUT6 #(\n .INIT(64'h333E333E3F3E333E)) \n output_fifo1_i_7\n (.I0(output_fifo1_i_9_n_0),\n .I1(timing_v_pos[10]),\n .I2(\\v_pos[2]_i_2_n_0 ),\n .I3(timing_v_pos[6]),\n .I4(output_fifo1_i_5_n_0),\n .I5(output_fifo1_i_10_n_0),\n .O(output_fifo1_i_7_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair18\" *) \n LUT5 #(\n .INIT(32'h00010101)) \n output_fifo1_i_8\n (.I0(timing_h_pos[6]),\n .I1(timing_h_pos[5]),\n .I2(timing_h_pos[3]),\n .I3(timing_h_pos[0]),\n .I4(timing_h_pos[1]),\n .O(output_fifo1_i_8_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFEEEEEEEEE)) \n output_fifo1_i_9\n (.I0(timing_v_pos[4]),\n .I1(timing_v_pos[5]),\n .I2(timing_v_pos[2]),\n .I3(timing_v_pos[0]),\n .I4(timing_v_pos[1]),\n .I5(timing_v_pos[3]),\n .O(output_fifo1_i_9_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair20\" *) \n LUT4 #(\n .INIT(16'h0444)) \n output_fifo2_i_1\n (.I0(output_fifo1_i_6_n_0),\n .I1(output_fifo1_i_7_n_0),\n .I2(odd_pixel),\n .I3(zoom_mode_IBUF),\n .O(output_fifo2));\n LUT6 #(\n .INIT(64'h0F0E0F0F0F0F0F0F)) \n \\v_pos[0]_i_1__0 \n (.I0(\\v_pos[2]_i_2_n_0 ),\n .I1(\\v_pos[2]_i_3_n_0 ),\n .I2(timing_v_pos[0]),\n .I3(timing_v_pos[1]),\n .I4(timing_v_pos[2]),\n .I5(timing_v_pos[10]),\n .O(v_pos[0]));\n LUT5 #(\n .INIT(32'h00000001)) \n \\v_pos[10]_i_1 \n (.I0(\\h_pos[11]_i_2_n_0 ),\n .I1(timing_h_pos[3]),\n .I2(timing_h_pos[5]),\n .I3(timing_h_pos[6]),\n .I4(\\h_pos[11]_i_3_n_0 ),\n .O(v_pos0));\n LUT4 #(\n .INIT(16'h0078)) \n \\v_pos[10]_i_2 \n (.I0(timing_v_pos[9]),\n .I1(\\v_pos[10]_i_3_n_0 ),\n .I2(timing_v_pos[10]),\n .I3(\\v_pos[10]_i_4_n_0 ),\n .O(v_pos[10]));\n LUT5 #(\n .INIT(32'h80000000)) \n \\v_pos[10]_i_3 \n (.I0(timing_v_pos[8]),\n .I1(\\v_pos[9]_i_2_n_0 ),\n .I2(timing_v_pos[5]),\n .I3(timing_v_pos[6]),\n .I4(timing_v_pos[7]),\n .O(\\v_pos[10]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000004)) \n \\v_pos[10]_i_4 \n (.I0(\\v_pos[10]_i_5_n_0 ),\n .I1(timing_v_pos[6]),\n .I2(odd_pixel_i_3_n_0),\n .I3(timing_v_pos[3]),\n .I4(timing_v_pos[8]),\n .I5(\\v_pos[10]_i_6_n_0 ),\n .O(\\v_pos[10]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair19\" *) \n LUT2 #(\n .INIT(4'h7)) \n \\v_pos[10]_i_5 \n (.I0(timing_v_pos[10]),\n .I1(timing_v_pos[2]),\n .O(\\v_pos[10]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair21\" *) \n LUT4 #(\n .INIT(16'hFFFD)) \n \\v_pos[10]_i_6 \n (.I0(timing_v_pos[5]),\n .I1(timing_v_pos[9]),\n .I2(timing_v_pos[4]),\n .I3(timing_v_pos[7]),\n .O(\\v_pos[10]_i_6_n_0 ));\n LUT2 #(\n .INIT(4'h6)) \n \\v_pos[1]_i_1 \n (.I0(timing_v_pos[1]),\n .I1(timing_v_pos[0]),\n .O(v_pos[1]));\n LUT6 #(\n .INIT(64'h0FFEF0000FFFF000)) \n \\v_pos[2]_i_1__0 \n (.I0(\\v_pos[2]_i_2_n_0 ),\n .I1(\\v_pos[2]_i_3_n_0 ),\n .I2(timing_v_pos[0]),\n .I3(timing_v_pos[1]),\n .I4(timing_v_pos[2]),\n .I5(timing_v_pos[10]),\n .O(v_pos[2]));\n LUT3 #(\n .INIT(8'hFE)) \n \\v_pos[2]_i_2 \n (.I0(timing_v_pos[7]),\n .I1(timing_v_pos[9]),\n .I2(timing_v_pos[8]),\n .O(\\v_pos[2]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'hEFFF)) \n \\v_pos[2]_i_3 \n (.I0(timing_v_pos[3]),\n .I1(timing_v_pos[4]),\n .I2(timing_v_pos[5]),\n .I3(timing_v_pos[6]),\n .O(\\v_pos[2]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'h6AAA)) \n \\v_pos[3]_i_1 \n (.I0(timing_v_pos[3]),\n .I1(timing_v_pos[0]),\n .I2(timing_v_pos[1]),\n .I3(timing_v_pos[2]),\n .O(v_pos[3]));\n LUT5 #(\n .INIT(32'h7FFF8000)) \n \\v_pos[4]_i_1 \n (.I0(timing_v_pos[2]),\n .I1(timing_v_pos[1]),\n .I2(timing_v_pos[0]),\n .I3(timing_v_pos[3]),\n .I4(timing_v_pos[4]),\n .O(v_pos[4]));\n LUT3 #(\n .INIT(8'h06)) \n \\v_pos[5]_i_1 \n (.I0(\\v_pos[9]_i_2_n_0 ),\n .I1(timing_v_pos[5]),\n .I2(\\v_pos[10]_i_4_n_0 ),\n .O(v_pos[5]));\n LUT4 #(\n .INIT(16'h0078)) \n \\v_pos[6]_i_1 \n (.I0(timing_v_pos[5]),\n .I1(\\v_pos[9]_i_2_n_0 ),\n .I2(timing_v_pos[6]),\n .I3(\\v_pos[10]_i_4_n_0 ),\n .O(v_pos[6]));\n LUT4 #(\n .INIT(16'h6AAA)) \n \\v_pos[7]_i_1 \n (.I0(timing_v_pos[7]),\n .I1(timing_v_pos[6]),\n .I2(timing_v_pos[5]),\n .I3(\\v_pos[9]_i_2_n_0 ),\n .O(v_pos[7]));\n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\v_pos[8]_i_1 \n (.I0(timing_v_pos[8]),\n .I1(\\v_pos[9]_i_2_n_0 ),\n .I2(timing_v_pos[5]),\n .I3(timing_v_pos[6]),\n .I4(timing_v_pos[7]),\n .O(v_pos[8]));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n \\v_pos[9]_i_1 \n (.I0(timing_v_pos[9]),\n .I1(timing_v_pos[7]),\n .I2(timing_v_pos[6]),\n .I3(timing_v_pos[5]),\n .I4(\\v_pos[9]_i_2_n_0 ),\n .I5(timing_v_pos[8]),\n .O(v_pos[9]));\n (* SOFT_HLUTNM = \"soft_lutpair17\" *) \n LUT5 #(\n .INIT(32'h80000000)) \n \\v_pos[9]_i_2 \n (.I0(timing_v_pos[4]),\n .I1(timing_v_pos[3]),\n .I2(timing_v_pos[0]),\n .I3(timing_v_pos[1]),\n .I4(timing_v_pos[2]),\n .O(\\v_pos[9]_i_2_n_0 ));\n FDCE #(\n .INIT(1'b0)) \n \\v_pos_reg[0] \n (.C(bbstub_pixel_clock),\n .CE(v_pos0),\n .CLR(AR),\n .D(v_pos[0]),\n .Q(timing_v_pos[0]));\n FDCE #(\n .INIT(1'b0)) \n \\v_pos_reg[10] \n (.C(bbstub_pixel_clock),\n .CE(v_pos0),\n .CLR(AR),\n .D(v_pos[10]),\n .Q(timing_v_pos[10]));\n FDCE #(\n .INIT(1'b0)) \n \\v_pos_reg[1] \n (.C(bbstub_pixel_clock),\n .CE(v_pos0),\n .CLR(AR),\n .D(v_pos[1]),\n .Q(timing_v_pos[1]));\n FDCE #(\n .INIT(1'b0)) \n \\v_pos_reg[2] \n (.C(bbstub_pixel_clock),\n .CE(v_pos0),\n .CLR(AR),\n .D(v_pos[2]),\n .Q(timing_v_pos[2]));\n FDCE #(\n .INIT(1'b0)) \n \\v_pos_reg[3] \n (.C(bbstub_pixel_clock),\n .CE(v_pos0),\n .CLR(AR),\n .D(v_pos[3]),\n .Q(timing_v_pos[3]));\n FDCE #(\n .INIT(1'b0)) \n \\v_pos_reg[4] \n (.C(bbstub_pixel_clock),\n .CE(v_pos0),\n .CLR(AR),\n .D(v_pos[4]),\n .Q(timing_v_pos[4]));\n FDCE #(\n .INIT(1'b0)) \n \\v_pos_reg[5] \n (.C(bbstub_pixel_clock),\n .CE(v_pos0),\n .CLR(AR),\n .D(v_pos[5]),\n .Q(timing_v_pos[5]));\n FDCE #(\n .INIT(1'b0)) \n \\v_pos_reg[6] \n (.C(bbstub_pixel_clock),\n .CE(v_pos0),\n .CLR(AR),\n .D(v_pos[6]),\n .Q(timing_v_pos[6]));\n FDCE #(\n .INIT(1'b0)) \n \\v_pos_reg[7] \n (.C(bbstub_pixel_clock),\n .CE(v_pos0),\n .CLR(AR),\n .D(v_pos[7]),\n .Q(timing_v_pos[7]));\n FDCE #(\n .INIT(1'b0)) \n \\v_pos_reg[8] \n (.C(bbstub_pixel_clock),\n .CE(v_pos0),\n .CLR(AR),\n .D(v_pos[8]),\n .Q(timing_v_pos[8]));\n FDCE #(\n .INIT(1'b0)) \n \\v_pos_reg[9] \n (.C(bbstub_pixel_clock),\n .CE(v_pos0),\n .CLR(AR),\n .D(v_pos[9]),\n .Q(timing_v_pos[9]));\nendmodule\n\n(* ORIG_REF_NAME = \"video_timing_ctrl\" *) \nmodule video_timing_ctrl__parameterized0\n (wr_en,\n rst,\n reset_n_IBUF,\n CLK,\n AR);\n output wr_en;\n output rst;\n input reset_n_IBUF;\n input CLK;\n input [0:0]AR;\n\n wire [0:0]AR;\n wire CLK;\n wire [10:0]h_pos;\n wire \\h_pos[10]_i_2_n_0 ;\n wire \\h_pos[10]_i_3_n_0 ;\n wire \\h_pos[10]_i_4_n_0 ;\n wire \\h_pos[2]_i_2_n_0 ;\n wire \\h_pos[2]_i_3_n_0 ;\n wire \\h_pos[8]_i_2_n_0 ;\n wire \\h_pos_reg_n_0_[0] ;\n wire \\h_pos_reg_n_0_[10] ;\n wire \\h_pos_reg_n_0_[1] ;\n wire \\h_pos_reg_n_0_[2] ;\n wire \\h_pos_reg_n_0_[3] ;\n wire \\h_pos_reg_n_0_[4] ;\n wire \\h_pos_reg_n_0_[5] ;\n wire \\h_pos_reg_n_0_[6] ;\n wire \\h_pos_reg_n_0_[7] ;\n wire \\h_pos_reg_n_0_[8] ;\n wire \\h_pos_reg_n_0_[9] ;\n wire input_fifo_i_10_n_0;\n wire input_fifo_i_11_n_0;\n wire input_fifo_i_12_n_0;\n wire input_fifo_i_3_n_0;\n wire input_fifo_i_4_n_0;\n wire input_fifo_i_5_n_0;\n wire input_fifo_i_6_n_0;\n wire input_fifo_i_7_n_0;\n wire input_fifo_i_8_n_0;\n wire input_fifo_i_9_n_0;\n wire reset_n_IBUF;\n wire rst;\n wire [11:0]v_pos;\n wire \\v_pos[11]_i_1_n_0 ;\n wire \\v_pos[11]_i_3_n_0 ;\n wire \\v_pos[11]_i_4_n_0 ;\n wire \\v_pos[11]_i_6_n_0 ;\n wire \\v_pos[11]_i_7_n_0 ;\n wire \\v_pos[11]_i_8_n_0 ;\n wire \\v_pos[4]_i_3_n_0 ;\n wire \\v_pos[4]_i_4_n_0 ;\n wire \\v_pos[4]_i_5_n_0 ;\n wire \\v_pos[4]_i_6_n_0 ;\n wire \\v_pos[8]_i_3_n_0 ;\n wire \\v_pos[8]_i_4_n_0 ;\n wire \\v_pos[8]_i_5_n_0 ;\n wire \\v_pos[8]_i_6_n_0 ;\n wire \\v_pos_reg[11]_i_5_n_2 ;\n wire \\v_pos_reg[11]_i_5_n_3 ;\n wire \\v_pos_reg[11]_i_5_n_5 ;\n wire \\v_pos_reg[11]_i_5_n_6 ;\n wire \\v_pos_reg[11]_i_5_n_7 ;\n wire \\v_pos_reg[4]_i_2_n_0 ;\n wire \\v_pos_reg[4]_i_2_n_1 ;\n wire \\v_pos_reg[4]_i_2_n_2 ;\n wire \\v_pos_reg[4]_i_2_n_3 ;\n wire \\v_pos_reg[4]_i_2_n_4 ;\n wire \\v_pos_reg[4]_i_2_n_5 ;\n wire \\v_pos_reg[4]_i_2_n_6 ;\n wire \\v_pos_reg[4]_i_2_n_7 ;\n wire \\v_pos_reg[8]_i_2_n_0 ;\n wire \\v_pos_reg[8]_i_2_n_1 ;\n wire \\v_pos_reg[8]_i_2_n_2 ;\n wire \\v_pos_reg[8]_i_2_n_3 ;\n wire \\v_pos_reg[8]_i_2_n_4 ;\n wire \\v_pos_reg[8]_i_2_n_5 ;\n wire \\v_pos_reg[8]_i_2_n_6 ;\n wire \\v_pos_reg[8]_i_2_n_7 ;\n wire \\v_pos_reg_n_0_[0] ;\n wire \\v_pos_reg_n_0_[10] ;\n wire \\v_pos_reg_n_0_[11] ;\n wire \\v_pos_reg_n_0_[1] ;\n wire \\v_pos_reg_n_0_[2] ;\n wire \\v_pos_reg_n_0_[3] ;\n wire \\v_pos_reg_n_0_[4] ;\n wire \\v_pos_reg_n_0_[5] ;\n wire \\v_pos_reg_n_0_[6] ;\n wire \\v_pos_reg_n_0_[7] ;\n wire \\v_pos_reg_n_0_[8] ;\n wire \\v_pos_reg_n_0_[9] ;\n wire wr_en;\n wire [3:2]\\NLW_v_pos_reg[11]_i_5_CO_UNCONNECTED ;\n wire [3:3]\\NLW_v_pos_reg[11]_i_5_O_UNCONNECTED ;\n\n (* SOFT_HLUTNM = \"soft_lutpair24\" *) \n LUT4 #(\n .INIT(16'h0D0F)) \n \\h_pos[0]_i_1__0 \n (.I0(\\h_pos[2]_i_2_n_0 ),\n .I1(\\h_pos[2]_i_3_n_0 ),\n .I2(\\h_pos_reg_n_0_[0] ),\n .I3(\\h_pos_reg_n_0_[5] ),\n .O(h_pos[0]));\n (* SOFT_HLUTNM = \"soft_lutpair26\" *) \n LUT4 #(\n .INIT(16'h2A80)) \n \\h_pos[10]_i_1 \n (.I0(\\h_pos[10]_i_2_n_0 ),\n .I1(\\h_pos[10]_i_3_n_0 ),\n .I2(\\h_pos_reg_n_0_[9] ),\n .I3(\\h_pos_reg_n_0_[10] ),\n .O(h_pos[10]));\n LUT5 #(\n .INIT(32'hFFFFFFF7)) \n \\h_pos[10]_i_2 \n (.I0(\\h_pos_reg_n_0_[9] ),\n .I1(\\h_pos_reg_n_0_[10] ),\n .I2(\\h_pos_reg_n_0_[0] ),\n .I3(\\h_pos[10]_i_4_n_0 ),\n .I4(\\h_pos[2]_i_3_n_0 ),\n .O(\\h_pos[10]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair22\" *) \n LUT5 #(\n .INIT(32'h08000000)) \n \\h_pos[10]_i_3 \n (.I0(\\h_pos_reg_n_0_[8] ),\n .I1(\\h_pos_reg_n_0_[7] ),\n .I2(\\h_pos[8]_i_2_n_0 ),\n .I3(\\h_pos_reg_n_0_[5] ),\n .I4(\\h_pos_reg_n_0_[6] ),\n .O(\\h_pos[10]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair22\" *) \n LUT4 #(\n .INIT(16'h7FFF)) \n \\h_pos[10]_i_4 \n (.I0(\\h_pos_reg_n_0_[7] ),\n .I1(\\h_pos_reg_n_0_[8] ),\n .I2(\\h_pos_reg_n_0_[5] ),\n .I3(\\h_pos_reg_n_0_[6] ),\n .O(\\h_pos[10]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair24\" *) \n LUT5 #(\n .INIT(32'h0D0FF0F0)) \n \\h_pos[1]_i_1__0 \n (.I0(\\h_pos[2]_i_2_n_0 ),\n .I1(\\h_pos[2]_i_3_n_0 ),\n .I2(\\h_pos_reg_n_0_[0] ),\n .I3(\\h_pos_reg_n_0_[5] ),\n .I4(\\h_pos_reg_n_0_[1] ),\n .O(h_pos[1]));\n LUT6 #(\n .INIT(64'h0D0FFDFFF0F00000)) \n \\h_pos[2]_i_1__0 \n (.I0(\\h_pos[2]_i_2_n_0 ),\n .I1(\\h_pos[2]_i_3_n_0 ),\n .I2(\\h_pos_reg_n_0_[0] ),\n .I3(\\h_pos_reg_n_0_[5] ),\n .I4(\\h_pos_reg_n_0_[1] ),\n .I5(\\h_pos_reg_n_0_[2] ),\n .O(h_pos[2]));\n LUT5 #(\n .INIT(32'h80000000)) \n \\h_pos[2]_i_2 \n (.I0(\\h_pos_reg_n_0_[6] ),\n .I1(\\h_pos_reg_n_0_[9] ),\n .I2(\\h_pos_reg_n_0_[7] ),\n .I3(\\h_pos_reg_n_0_[8] ),\n .I4(\\h_pos_reg_n_0_[10] ),\n .O(\\h_pos[2]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'hFFF7)) \n \\h_pos[2]_i_3 \n (.I0(\\h_pos_reg_n_0_[2] ),\n .I1(\\h_pos_reg_n_0_[1] ),\n .I2(\\h_pos_reg_n_0_[3] ),\n .I3(\\h_pos_reg_n_0_[4] ),\n .O(\\h_pos[2]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'h7F80)) \n \\h_pos[3]_i_1 \n (.I0(\\h_pos_reg_n_0_[0] ),\n .I1(\\h_pos_reg_n_0_[1] ),\n .I2(\\h_pos_reg_n_0_[2] ),\n .I3(\\h_pos_reg_n_0_[3] ),\n .O(h_pos[3]));\n (* SOFT_HLUTNM = \"soft_lutpair25\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\h_pos[4]_i_1 \n (.I0(\\h_pos_reg_n_0_[4] ),\n .I1(\\h_pos_reg_n_0_[0] ),\n .I2(\\h_pos_reg_n_0_[1] ),\n .I3(\\h_pos_reg_n_0_[2] ),\n .I4(\\h_pos_reg_n_0_[3] ),\n .O(h_pos[4]));\n LUT3 #(\n .INIT(8'h82)) \n \\h_pos[5]_i_1 \n (.I0(\\h_pos[10]_i_2_n_0 ),\n .I1(\\h_pos[8]_i_2_n_0 ),\n .I2(\\h_pos_reg_n_0_[5] ),\n .O(h_pos[5]));\n (* SOFT_HLUTNM = \"soft_lutpair23\" *) \n LUT4 #(\n .INIT(16'hA208)) \n \\h_pos[6]_i_1 \n (.I0(\\h_pos[10]_i_2_n_0 ),\n .I1(\\h_pos_reg_n_0_[5] ),\n .I2(\\h_pos[8]_i_2_n_0 ),\n .I3(\\h_pos_reg_n_0_[6] ),\n .O(h_pos[6]));\n (* SOFT_HLUTNM = \"soft_lutpair23\" *) \n LUT5 #(\n .INIT(32'h8AAA2000)) \n \\h_pos[7]_i_1 \n (.I0(\\h_pos[10]_i_2_n_0 ),\n .I1(\\h_pos[8]_i_2_n_0 ),\n .I2(\\h_pos_reg_n_0_[5] ),\n .I3(\\h_pos_reg_n_0_[6] ),\n .I4(\\h_pos_reg_n_0_[7] ),\n .O(h_pos[7]));\n LUT6 #(\n .INIT(64'hAA2AAAAA00800000)) \n \\h_pos[8]_i_1 \n (.I0(\\h_pos[10]_i_2_n_0 ),\n .I1(\\h_pos_reg_n_0_[6] ),\n .I2(\\h_pos_reg_n_0_[5] ),\n .I3(\\h_pos[8]_i_2_n_0 ),\n .I4(\\h_pos_reg_n_0_[7] ),\n .I5(\\h_pos_reg_n_0_[8] ),\n .O(h_pos[8]));\n (* SOFT_HLUTNM = \"soft_lutpair25\" *) \n LUT5 #(\n .INIT(32'h7FFFFFFF)) \n \\h_pos[8]_i_2 \n (.I0(\\h_pos_reg_n_0_[2] ),\n .I1(\\h_pos_reg_n_0_[1] ),\n .I2(\\h_pos_reg_n_0_[0] ),\n .I3(\\h_pos_reg_n_0_[3] ),\n .I4(\\h_pos_reg_n_0_[4] ),\n .O(\\h_pos[8]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair26\" *) \n LUT3 #(\n .INIT(8'h28)) \n \\h_pos[9]_i_1 \n (.I0(\\h_pos[10]_i_2_n_0 ),\n .I1(\\h_pos[10]_i_3_n_0 ),\n .I2(\\h_pos_reg_n_0_[9] ),\n .O(h_pos[9]));\n FDCE #(\n .INIT(1'b0)) \n \\h_pos_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .CLR(AR),\n .D(h_pos[0]),\n .Q(\\h_pos_reg_n_0_[0] ));\n FDCE #(\n .INIT(1'b0)) \n \\h_pos_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .CLR(AR),\n .D(h_pos[10]),\n .Q(\\h_pos_reg_n_0_[10] ));\n FDCE #(\n .INIT(1'b0)) \n \\h_pos_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .CLR(AR),\n .D(h_pos[1]),\n .Q(\\h_pos_reg_n_0_[1] ));\n FDCE #(\n .INIT(1'b0)) \n \\h_pos_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .CLR(AR),\n .D(h_pos[2]),\n .Q(\\h_pos_reg_n_0_[2] ));\n FDCE #(\n .INIT(1'b0)) \n \\h_pos_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .CLR(AR),\n .D(h_pos[3]),\n .Q(\\h_pos_reg_n_0_[3] ));\n FDCE #(\n .INIT(1'b0)) \n \\h_pos_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .CLR(AR),\n .D(h_pos[4]),\n .Q(\\h_pos_reg_n_0_[4] ));\n FDCE #(\n .INIT(1'b0)) \n \\h_pos_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .CLR(AR),\n .D(h_pos[5]),\n .Q(\\h_pos_reg_n_0_[5] ));\n FDCE #(\n .INIT(1'b0)) \n \\h_pos_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .CLR(AR),\n .D(h_pos[6]),\n .Q(\\h_pos_reg_n_0_[6] ));\n FDCE #(\n .INIT(1'b0)) \n \\h_pos_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .CLR(AR),\n .D(h_pos[7]),\n .Q(\\h_pos_reg_n_0_[7] ));\n FDCE #(\n .INIT(1'b0)) \n \\h_pos_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .CLR(AR),\n .D(h_pos[8]),\n .Q(\\h_pos_reg_n_0_[8] ));\n FDCE #(\n .INIT(1'b0)) \n \\h_pos_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .CLR(AR),\n .D(h_pos[9]),\n .Q(\\h_pos_reg_n_0_[9] ));\n LUT6 #(\n .INIT(64'h00010000FFFFFFFF)) \n input_fifo_i_1\n (.I0(input_fifo_i_3_n_0),\n .I1(\\v_pos_reg_n_0_[5] ),\n .I2(\\v_pos_reg_n_0_[6] ),\n .I3(\\v_pos_reg_n_0_[4] ),\n .I4(input_fifo_i_4_n_0),\n .I5(reset_n_IBUF),\n .O(rst));\n LUT6 #(\n .INIT(64'h0000000000FF57FF)) \n input_fifo_i_10\n (.I0(\\h_pos_reg_n_0_[2] ),\n .I1(\\h_pos_reg_n_0_[1] ),\n .I2(\\h_pos_reg_n_0_[0] ),\n .I3(\\h_pos_reg_n_0_[4] ),\n .I4(\\h_pos_reg_n_0_[3] ),\n .I5(\\h_pos_reg_n_0_[5] ),\n .O(input_fifo_i_10_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFE000)) \n input_fifo_i_11\n (.I0(\\h_pos_reg_n_0_[1] ),\n .I1(\\h_pos_reg_n_0_[2] ),\n .I2(\\h_pos_reg_n_0_[4] ),\n .I3(\\h_pos_reg_n_0_[3] ),\n .I4(\\h_pos_reg_n_0_[10] ),\n .I5(\\h_pos_reg_n_0_[9] ),\n .O(input_fifo_i_11_n_0));\n LUT4 #(\n .INIT(16'h0001)) \n input_fifo_i_12\n (.I0(\\h_pos_reg_n_0_[7] ),\n .I1(\\h_pos_reg_n_0_[8] ),\n .I2(\\h_pos_reg_n_0_[5] ),\n .I3(\\h_pos_reg_n_0_[6] ),\n .O(input_fifo_i_12_n_0));\n LUT6 #(\n .INIT(64'h000000001111FFFB)) \n input_fifo_i_2\n (.I0(input_fifo_i_5_n_0),\n .I1(input_fifo_i_6_n_0),\n .I2(\\v_pos_reg_n_0_[10] ),\n .I3(\\v_pos_reg_n_0_[7] ),\n .I4(\\v_pos_reg_n_0_[11] ),\n .I5(input_fifo_i_7_n_0),\n .O(wr_en));\n LUT4 #(\n .INIT(16'hFFFE)) \n input_fifo_i_3\n (.I0(\\v_pos_reg_n_0_[7] ),\n .I1(\\v_pos_reg_n_0_[10] ),\n .I2(\\v_pos_reg_n_0_[9] ),\n .I3(\\v_pos_reg_n_0_[8] ),\n .O(input_fifo_i_3_n_0));\n LUT5 #(\n .INIT(32'h00000007)) \n input_fifo_i_4\n (.I0(\\v_pos_reg_n_0_[0] ),\n .I1(\\v_pos_reg_n_0_[1] ),\n .I2(\\v_pos_reg_n_0_[11] ),\n .I3(\\v_pos_reg_n_0_[3] ),\n .I4(\\v_pos_reg_n_0_[2] ),\n .O(input_fifo_i_4_n_0));\n LUT2 #(\n .INIT(4'hE)) \n input_fifo_i_5\n (.I0(\\v_pos_reg_n_0_[8] ),\n .I1(\\v_pos_reg_n_0_[9] ),\n .O(input_fifo_i_5_n_0));\n LUT6 #(\n .INIT(64'hFFFFFC11FFFFFF01)) \n input_fifo_i_6\n (.I0(\\v_pos_reg_n_0_[11] ),\n .I1(input_fifo_i_8_n_0),\n .I2(\\v_pos_reg_n_0_[4] ),\n .I3(\\v_pos_reg_n_0_[7] ),\n .I4(\\v_pos_reg_n_0_[10] ),\n .I5(input_fifo_i_9_n_0),\n .O(input_fifo_i_6_n_0));\n LUT4 #(\n .INIT(16'h4F44)) \n input_fifo_i_7\n (.I0(input_fifo_i_10_n_0),\n .I1(\\h_pos[2]_i_2_n_0 ),\n .I2(input_fifo_i_11_n_0),\n .I3(input_fifo_i_12_n_0),\n .O(input_fifo_i_7_n_0));\n LUT2 #(\n .INIT(4'hE)) \n input_fifo_i_8\n (.I0(\\v_pos_reg_n_0_[5] ),\n .I1(\\v_pos_reg_n_0_[6] ),\n .O(input_fifo_i_8_n_0));\n LUT3 #(\n .INIT(8'h1F)) \n input_fifo_i_9\n (.I0(\\v_pos_reg_n_0_[2] ),\n .I1(\\v_pos_reg_n_0_[1] ),\n .I2(\\v_pos_reg_n_0_[3] ),\n .O(input_fifo_i_9_n_0));\n LUT1 #(\n .INIT(2'h1)) \n \\v_pos[0]_i_1 \n (.I0(\\v_pos_reg_n_0_[0] ),\n .O(v_pos[0]));\n LUT6 #(\n .INIT(64'hFFFFBFFF00000000)) \n \\v_pos[10]_i_1__0 \n (.I0(\\v_pos[11]_i_3_n_0 ),\n .I1(\\v_pos_reg_n_0_[2] ),\n .I2(\\v_pos_reg_n_0_[11] ),\n .I3(\\v_pos_reg_n_0_[3] ),\n .I4(\\v_pos[11]_i_4_n_0 ),\n .I5(\\v_pos_reg[11]_i_5_n_6 ),\n .O(v_pos[10]));\n LUT4 #(\n .INIT(16'h0200)) \n \\v_pos[11]_i_1 \n (.I0(\\h_pos[2]_i_2_n_0 ),\n .I1(\\h_pos[2]_i_3_n_0 ),\n .I2(\\h_pos_reg_n_0_[0] ),\n .I3(\\h_pos_reg_n_0_[5] ),\n .O(\\v_pos[11]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFBFFF00000000)) \n \\v_pos[11]_i_2 \n (.I0(\\v_pos[11]_i_3_n_0 ),\n .I1(\\v_pos_reg_n_0_[2] ),\n .I2(\\v_pos_reg_n_0_[11] ),\n .I3(\\v_pos_reg_n_0_[3] ),\n .I4(\\v_pos[11]_i_4_n_0 ),\n .I5(\\v_pos_reg[11]_i_5_n_5 ),\n .O(v_pos[11]));\n LUT4 #(\n .INIT(16'hFFEF)) \n \\v_pos[11]_i_3 \n (.I0(\\v_pos_reg_n_0_[9] ),\n .I1(\\v_pos_reg_n_0_[8] ),\n .I2(\\v_pos_reg_n_0_[0] ),\n .I3(\\v_pos_reg_n_0_[1] ),\n .O(\\v_pos[11]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFFEFF)) \n \\v_pos[11]_i_4 \n (.I0(\\v_pos_reg_n_0_[5] ),\n .I1(\\v_pos_reg_n_0_[6] ),\n .I2(\\v_pos_reg_n_0_[4] ),\n .I3(\\v_pos_reg_n_0_[7] ),\n .I4(\\v_pos_reg_n_0_[10] ),\n .O(\\v_pos[11]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\v_pos[11]_i_6 \n (.I0(\\v_pos_reg_n_0_[11] ),\n .O(\\v_pos[11]_i_6_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\v_pos[11]_i_7 \n (.I0(\\v_pos_reg_n_0_[10] ),\n .O(\\v_pos[11]_i_7_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\v_pos[11]_i_8 \n (.I0(\\v_pos_reg_n_0_[9] ),\n .O(\\v_pos[11]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFBFFF00000000)) \n \\v_pos[1]_i_1__0 \n (.I0(\\v_pos[11]_i_3_n_0 ),\n .I1(\\v_pos_reg_n_0_[2] ),\n .I2(\\v_pos_reg_n_0_[11] ),\n .I3(\\v_pos_reg_n_0_[3] ),\n .I4(\\v_pos[11]_i_4_n_0 ),\n .I5(\\v_pos_reg[4]_i_2_n_7 ),\n .O(v_pos[1]));\n LUT6 #(\n .INIT(64'hFFFFBFFF00000000)) \n \\v_pos[2]_i_1 \n (.I0(\\v_pos[11]_i_3_n_0 ),\n .I1(\\v_pos_reg_n_0_[2] ),\n .I2(\\v_pos_reg_n_0_[11] ),\n .I3(\\v_pos_reg_n_0_[3] ),\n .I4(\\v_pos[11]_i_4_n_0 ),\n .I5(\\v_pos_reg[4]_i_2_n_6 ),\n .O(v_pos[2]));\n LUT6 #(\n .INIT(64'hFFFFBFFF00000000)) \n \\v_pos[3]_i_1__0 \n (.I0(\\v_pos[11]_i_3_n_0 ),\n .I1(\\v_pos_reg_n_0_[2] ),\n .I2(\\v_pos_reg_n_0_[11] ),\n .I3(\\v_pos_reg_n_0_[3] ),\n .I4(\\v_pos[11]_i_4_n_0 ),\n .I5(\\v_pos_reg[4]_i_2_n_5 ),\n .O(v_pos[3]));\n LUT6 #(\n .INIT(64'hFFFFBFFF00000000)) \n \\v_pos[4]_i_1__0 \n (.I0(\\v_pos[11]_i_3_n_0 ),\n .I1(\\v_pos_reg_n_0_[2] ),\n .I2(\\v_pos_reg_n_0_[11] ),\n .I3(\\v_pos_reg_n_0_[3] ),\n .I4(\\v_pos[11]_i_4_n_0 ),\n .I5(\\v_pos_reg[4]_i_2_n_4 ),\n .O(v_pos[4]));\n LUT1 #(\n .INIT(2'h2)) \n \\v_pos[4]_i_3 \n (.I0(\\v_pos_reg_n_0_[4] ),\n .O(\\v_pos[4]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\v_pos[4]_i_4 \n (.I0(\\v_pos_reg_n_0_[3] ),\n .O(\\v_pos[4]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\v_pos[4]_i_5 \n (.I0(\\v_pos_reg_n_0_[2] ),\n .O(\\v_pos[4]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\v_pos[4]_i_6 \n (.I0(\\v_pos_reg_n_0_[1] ),\n .O(\\v_pos[4]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFBFFF00000000)) \n \\v_pos[5]_i_1__0 \n (.I0(\\v_pos[11]_i_3_n_0 ),\n .I1(\\v_pos_reg_n_0_[2] ),\n .I2(\\v_pos_reg_n_0_[11] ),\n .I3(\\v_pos_reg_n_0_[3] ),\n .I4(\\v_pos[11]_i_4_n_0 ),\n .I5(\\v_pos_reg[8]_i_2_n_7 ),\n .O(v_pos[5]));\n LUT6 #(\n .INIT(64'hFFFFBFFF00000000)) \n \\v_pos[6]_i_1__0 \n (.I0(\\v_pos[11]_i_3_n_0 ),\n .I1(\\v_pos_reg_n_0_[2] ),\n .I2(\\v_pos_reg_n_0_[11] ),\n .I3(\\v_pos_reg_n_0_[3] ),\n .I4(\\v_pos[11]_i_4_n_0 ),\n .I5(\\v_pos_reg[8]_i_2_n_6 ),\n .O(v_pos[6]));\n LUT6 #(\n .INIT(64'hFFFFBFFF00000000)) \n \\v_pos[7]_i_1__0 \n (.I0(\\v_pos[11]_i_3_n_0 ),\n .I1(\\v_pos_reg_n_0_[2] ),\n .I2(\\v_pos_reg_n_0_[11] ),\n .I3(\\v_pos_reg_n_0_[3] ),\n .I4(\\v_pos[11]_i_4_n_0 ),\n .I5(\\v_pos_reg[8]_i_2_n_5 ),\n .O(v_pos[7]));\n LUT6 #(\n .INIT(64'hFFFFBFFF00000000)) \n \\v_pos[8]_i_1__0 \n (.I0(\\v_pos[11]_i_3_n_0 ),\n .I1(\\v_pos_reg_n_0_[2] ),\n .I2(\\v_pos_reg_n_0_[11] ),\n .I3(\\v_pos_reg_n_0_[3] ),\n .I4(\\v_pos[11]_i_4_n_0 ),\n .I5(\\v_pos_reg[8]_i_2_n_4 ),\n .O(v_pos[8]));\n LUT1 #(\n .INIT(2'h2)) \n \\v_pos[8]_i_3 \n (.I0(\\v_pos_reg_n_0_[8] ),\n .O(\\v_pos[8]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\v_pos[8]_i_4 \n (.I0(\\v_pos_reg_n_0_[7] ),\n .O(\\v_pos[8]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\v_pos[8]_i_5 \n (.I0(\\v_pos_reg_n_0_[6] ),\n .O(\\v_pos[8]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\v_pos[8]_i_6 \n (.I0(\\v_pos_reg_n_0_[5] ),\n .O(\\v_pos[8]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFBFFF00000000)) \n \\v_pos[9]_i_1__0 \n (.I0(\\v_pos[11]_i_3_n_0 ),\n .I1(\\v_pos_reg_n_0_[2] ),\n .I2(\\v_pos_reg_n_0_[11] ),\n .I3(\\v_pos_reg_n_0_[3] ),\n .I4(\\v_pos[11]_i_4_n_0 ),\n .I5(\\v_pos_reg[11]_i_5_n_7 ),\n .O(v_pos[9]));\n FDCE #(\n .INIT(1'b0)) \n \\v_pos_reg[0] \n (.C(CLK),\n .CE(\\v_pos[11]_i_1_n_0 ),\n .CLR(AR),\n .D(v_pos[0]),\n .Q(\\v_pos_reg_n_0_[0] ));\n FDCE #(\n .INIT(1'b0)) \n \\v_pos_reg[10] \n (.C(CLK),\n .CE(\\v_pos[11]_i_1_n_0 ),\n .CLR(AR),\n .D(v_pos[10]),\n .Q(\\v_pos_reg_n_0_[10] ));\n FDCE #(\n .INIT(1'b0)) \n \\v_pos_reg[11] \n (.C(CLK),\n .CE(\\v_pos[11]_i_1_n_0 ),\n .CLR(AR),\n .D(v_pos[11]),\n .Q(\\v_pos_reg_n_0_[11] ));\n CARRY4 \\v_pos_reg[11]_i_5 \n (.CI(\\v_pos_reg[8]_i_2_n_0 ),\n .CO({\\NLW_v_pos_reg[11]_i_5_CO_UNCONNECTED [3:2],\\v_pos_reg[11]_i_5_n_2 ,\\v_pos_reg[11]_i_5_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\NLW_v_pos_reg[11]_i_5_O_UNCONNECTED [3],\\v_pos_reg[11]_i_5_n_5 ,\\v_pos_reg[11]_i_5_n_6 ,\\v_pos_reg[11]_i_5_n_7 }),\n .S({1'b0,\\v_pos[11]_i_6_n_0 ,\\v_pos[11]_i_7_n_0 ,\\v_pos[11]_i_8_n_0 }));\n FDCE #(\n .INIT(1'b0)) \n \\v_pos_reg[1] \n (.C(CLK),\n .CE(\\v_pos[11]_i_1_n_0 ),\n .CLR(AR),\n .D(v_pos[1]),\n .Q(\\v_pos_reg_n_0_[1] ));\n FDCE #(\n .INIT(1'b0)) \n \\v_pos_reg[2] \n (.C(CLK),\n .CE(\\v_pos[11]_i_1_n_0 ),\n .CLR(AR),\n .D(v_pos[2]),\n .Q(\\v_pos_reg_n_0_[2] ));\n FDCE #(\n .INIT(1'b0)) \n \\v_pos_reg[3] \n (.C(CLK),\n .CE(\\v_pos[11]_i_1_n_0 ),\n .CLR(AR),\n .D(v_pos[3]),\n .Q(\\v_pos_reg_n_0_[3] ));\n FDCE #(\n .INIT(1'b0)) \n \\v_pos_reg[4] \n (.C(CLK),\n .CE(\\v_pos[11]_i_1_n_0 ),\n .CLR(AR),\n .D(v_pos[4]),\n .Q(\\v_pos_reg_n_0_[4] ));\n CARRY4 \\v_pos_reg[4]_i_2 \n (.CI(1'b0),\n .CO({\\v_pos_reg[4]_i_2_n_0 ,\\v_pos_reg[4]_i_2_n_1 ,\\v_pos_reg[4]_i_2_n_2 ,\\v_pos_reg[4]_i_2_n_3 }),\n .CYINIT(\\v_pos_reg_n_0_[0] ),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\v_pos_reg[4]_i_2_n_4 ,\\v_pos_reg[4]_i_2_n_5 ,\\v_pos_reg[4]_i_2_n_6 ,\\v_pos_reg[4]_i_2_n_7 }),\n .S({\\v_pos[4]_i_3_n_0 ,\\v_pos[4]_i_4_n_0 ,\\v_pos[4]_i_5_n_0 ,\\v_pos[4]_i_6_n_0 }));\n FDCE #(\n .INIT(1'b0)) \n \\v_pos_reg[5] \n (.C(CLK),\n .CE(\\v_pos[11]_i_1_n_0 ),\n .CLR(AR),\n .D(v_pos[5]),\n .Q(\\v_pos_reg_n_0_[5] ));\n FDCE #(\n .INIT(1'b0)) \n \\v_pos_reg[6] \n (.C(CLK),\n .CE(\\v_pos[11]_i_1_n_0 ),\n .CLR(AR),\n .D(v_pos[6]),\n .Q(\\v_pos_reg_n_0_[6] ));\n FDCE #(\n .INIT(1'b0)) \n \\v_pos_reg[7] \n (.C(CLK),\n .CE(\\v_pos[11]_i_1_n_0 ),\n .CLR(AR),\n .D(v_pos[7]),\n .Q(\\v_pos_reg_n_0_[7] ));\n FDCE #(\n .INIT(1'b0)) \n \\v_pos_reg[8] \n (.C(CLK),\n .CE(\\v_pos[11]_i_1_n_0 ),\n .CLR(AR),\n .D(v_pos[8]),\n .Q(\\v_pos_reg_n_0_[8] ));\n CARRY4 \\v_pos_reg[8]_i_2 \n (.CI(\\v_pos_reg[4]_i_2_n_0 ),\n .CO({\\v_pos_reg[8]_i_2_n_0 ,\\v_pos_reg[8]_i_2_n_1 ,\\v_pos_reg[8]_i_2_n_2 ,\\v_pos_reg[8]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\v_pos_reg[8]_i_2_n_4 ,\\v_pos_reg[8]_i_2_n_5 ,\\v_pos_reg[8]_i_2_n_6 ,\\v_pos_reg[8]_i_2_n_7 }),\n .S({\\v_pos[8]_i_3_n_0 ,\\v_pos[8]_i_4_n_0 ,\\v_pos[8]_i_5_n_0 ,\\v_pos[8]_i_6_n_0 }));\n FDCE #(\n .INIT(1'b0)) \n \\v_pos_reg[9] \n (.C(CLK),\n .CE(\\v_pos[11]_i_1_n_0 ),\n .CLR(AR),\n .D(v_pos[9]),\n .Q(\\v_pos_reg_n_0_[9] ));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_generic_cstr\" *) \nmodule fb_input_fifo_blk_mem_gen_generic_cstr\n (dout,\n rd_clk,\n wr_clk,\n tmp_ram_rd_en,\n ram_full_fb_i_reg,\n out,\n Q,\n \\gic0.gc0.count_d2_reg[10] ,\n din);\n output [255:0]dout;\n input rd_clk;\n input wr_clk;\n input tmp_ram_rd_en;\n input ram_full_fb_i_reg;\n input [0:0]out;\n input [8:0]Q;\n input [10:0]\\gic0.gc0.count_d2_reg[10] ;\n input [63:0]din;\n\n wire [8:0]Q;\n wire [63:0]din;\n wire [255:0]dout;\n wire [10:0]\\gic0.gc0.count_d2_reg[10] ;\n wire [0:0]out;\n wire ram_full_fb_i_reg;\n wire rd_clk;\n wire tmp_ram_rd_en;\n wire wr_clk;\n\n fb_input_fifo_blk_mem_gen_prim_width \\ramloop[0].ram.r \n (.Q(Q),\n .din(din[17:0]),\n .dout({dout[209:192],dout[145:128],dout[81:64],dout[17:0]}),\n .\\gic0.gc0.count_d2_reg[10] (\\gic0.gc0.count_d2_reg[10] ),\n .out(out),\n .ram_full_fb_i_reg(ram_full_fb_i_reg),\n .rd_clk(rd_clk),\n .tmp_ram_rd_en(tmp_ram_rd_en),\n .wr_clk(wr_clk));\n fb_input_fifo_blk_mem_gen_prim_width__parameterized0 \\ramloop[1].ram.r \n (.Q(Q),\n .din(din[35:18]),\n .dout({dout[227:210],dout[163:146],dout[99:82],dout[35:18]}),\n .\\gic0.gc0.count_d2_reg[10] (\\gic0.gc0.count_d2_reg[10] ),\n .out(out),\n .ram_full_fb_i_reg(ram_full_fb_i_reg),\n .rd_clk(rd_clk),\n .tmp_ram_rd_en(tmp_ram_rd_en),\n .wr_clk(wr_clk));\n fb_input_fifo_blk_mem_gen_prim_width__parameterized1 \\ramloop[2].ram.r \n (.Q(Q),\n .din(din[53:36]),\n .dout({dout[245:228],dout[181:164],dout[117:100],dout[53:36]}),\n .\\gic0.gc0.count_d2_reg[10] (\\gic0.gc0.count_d2_reg[10] ),\n .out(out),\n .ram_full_fb_i_reg(ram_full_fb_i_reg),\n .rd_clk(rd_clk),\n .tmp_ram_rd_en(tmp_ram_rd_en),\n .wr_clk(wr_clk));\n fb_input_fifo_blk_mem_gen_prim_width__parameterized2 \\ramloop[3].ram.r \n (.Q(Q),\n .din(din[63:54]),\n .dout({dout[255:246],dout[191:182],dout[127:118],dout[63:54]}),\n .\\gic0.gc0.count_d2_reg[10] (\\gic0.gc0.count_d2_reg[10] ),\n .out(out),\n .ram_full_fb_i_reg(ram_full_fb_i_reg),\n .rd_clk(rd_clk),\n .tmp_ram_rd_en(tmp_ram_rd_en),\n .wr_clk(wr_clk));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule fb_input_fifo_blk_mem_gen_prim_width\n (dout,\n rd_clk,\n wr_clk,\n tmp_ram_rd_en,\n ram_full_fb_i_reg,\n out,\n Q,\n \\gic0.gc0.count_d2_reg[10] ,\n din);\n output [71:0]dout;\n input rd_clk;\n input wr_clk;\n input tmp_ram_rd_en;\n input ram_full_fb_i_reg;\n input [0:0]out;\n input [8:0]Q;\n input [10:0]\\gic0.gc0.count_d2_reg[10] ;\n input [17:0]din;\n\n wire [8:0]Q;\n wire [17:0]din;\n wire [71:0]dout;\n wire [10:0]\\gic0.gc0.count_d2_reg[10] ;\n wire [0:0]out;\n wire ram_full_fb_i_reg;\n wire rd_clk;\n wire tmp_ram_rd_en;\n wire wr_clk;\n\n fb_input_fifo_blk_mem_gen_prim_wrapper \\prim_noinit.ram \n (.Q(Q),\n .din(din),\n .dout(dout),\n .\\gic0.gc0.count_d2_reg[10] (\\gic0.gc0.count_d2_reg[10] ),\n .out(out),\n .ram_full_fb_i_reg(ram_full_fb_i_reg),\n .rd_clk(rd_clk),\n .tmp_ram_rd_en(tmp_ram_rd_en),\n .wr_clk(wr_clk));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule fb_input_fifo_blk_mem_gen_prim_width__parameterized0\n (dout,\n rd_clk,\n wr_clk,\n tmp_ram_rd_en,\n ram_full_fb_i_reg,\n out,\n Q,\n \\gic0.gc0.count_d2_reg[10] ,\n din);\n output [71:0]dout;\n input rd_clk;\n input wr_clk;\n input tmp_ram_rd_en;\n input ram_full_fb_i_reg;\n input [0:0]out;\n input [8:0]Q;\n input [10:0]\\gic0.gc0.count_d2_reg[10] ;\n input [17:0]din;\n\n wire [8:0]Q;\n wire [17:0]din;\n wire [71:0]dout;\n wire [10:0]\\gic0.gc0.count_d2_reg[10] ;\n wire [0:0]out;\n wire ram_full_fb_i_reg;\n wire rd_clk;\n wire tmp_ram_rd_en;\n wire wr_clk;\n\n fb_input_fifo_blk_mem_gen_prim_wrapper__parameterized0 \\prim_noinit.ram \n (.Q(Q),\n .din(din),\n .dout(dout),\n .\\gic0.gc0.count_d2_reg[10] (\\gic0.gc0.count_d2_reg[10] ),\n .out(out),\n .ram_full_fb_i_reg(ram_full_fb_i_reg),\n .rd_clk(rd_clk),\n .tmp_ram_rd_en(tmp_ram_rd_en),\n .wr_clk(wr_clk));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule fb_input_fifo_blk_mem_gen_prim_width__parameterized1\n (dout,\n rd_clk,\n wr_clk,\n tmp_ram_rd_en,\n ram_full_fb_i_reg,\n out,\n Q,\n \\gic0.gc0.count_d2_reg[10] ,\n din);\n output [71:0]dout;\n input rd_clk;\n input wr_clk;\n input tmp_ram_rd_en;\n input ram_full_fb_i_reg;\n input [0:0]out;\n input [8:0]Q;\n input [10:0]\\gic0.gc0.count_d2_reg[10] ;\n input [17:0]din;\n\n wire [8:0]Q;\n wire [17:0]din;\n wire [71:0]dout;\n wire [10:0]\\gic0.gc0.count_d2_reg[10] ;\n wire [0:0]out;\n wire ram_full_fb_i_reg;\n wire rd_clk;\n wire tmp_ram_rd_en;\n wire wr_clk;\n\n fb_input_fifo_blk_mem_gen_prim_wrapper__parameterized1 \\prim_noinit.ram \n (.Q(Q),\n .din(din),\n .dout(dout),\n .\\gic0.gc0.count_d2_reg[10] (\\gic0.gc0.count_d2_reg[10] ),\n .out(out),\n .ram_full_fb_i_reg(ram_full_fb_i_reg),\n .rd_clk(rd_clk),\n .tmp_ram_rd_en(tmp_ram_rd_en),\n .wr_clk(wr_clk));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule fb_input_fifo_blk_mem_gen_prim_width__parameterized2\n (dout,\n rd_clk,\n wr_clk,\n tmp_ram_rd_en,\n ram_full_fb_i_reg,\n out,\n Q,\n \\gic0.gc0.count_d2_reg[10] ,\n din);\n output [39:0]dout;\n input rd_clk;\n input wr_clk;\n input tmp_ram_rd_en;\n input ram_full_fb_i_reg;\n input [0:0]out;\n input [8:0]Q;\n input [10:0]\\gic0.gc0.count_d2_reg[10] ;\n input [9:0]din;\n\n wire [8:0]Q;\n wire [9:0]din;\n wire [39:0]dout;\n wire [10:0]\\gic0.gc0.count_d2_reg[10] ;\n wire [0:0]out;\n wire ram_full_fb_i_reg;\n wire rd_clk;\n wire tmp_ram_rd_en;\n wire wr_clk;\n\n fb_input_fifo_blk_mem_gen_prim_wrapper__parameterized2 \\prim_noinit.ram \n (.Q(Q),\n .din(din),\n .dout(dout),\n .\\gic0.gc0.count_d2_reg[10] (\\gic0.gc0.count_d2_reg[10] ),\n .out(out),\n .ram_full_fb_i_reg(ram_full_fb_i_reg),\n .rd_clk(rd_clk),\n .tmp_ram_rd_en(tmp_ram_rd_en),\n .wr_clk(wr_clk));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule fb_input_fifo_blk_mem_gen_prim_wrapper\n (dout,\n rd_clk,\n wr_clk,\n tmp_ram_rd_en,\n ram_full_fb_i_reg,\n out,\n Q,\n \\gic0.gc0.count_d2_reg[10] ,\n din);\n output [71:0]dout;\n input rd_clk;\n input wr_clk;\n input tmp_ram_rd_en;\n input ram_full_fb_i_reg;\n input [0:0]out;\n input [8:0]Q;\n input [10:0]\\gic0.gc0.count_d2_reg[10] ;\n input [17:0]din;\n\n wire [8:0]Q;\n wire [17:0]din;\n wire [71:0]dout;\n wire [10:0]\\gic0.gc0.count_d2_reg[10] ;\n wire [0:0]out;\n wire ram_full_fb_i_reg;\n wire rd_clk;\n wire tmp_ram_rd_en;\n wire wr_clk;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_CASCADEOUTA_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_CASCADEOUTB_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_DBITERR_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_SBITERR_UNCONNECTED ;\n wire [7:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_ECCPARITY_UNCONNECTED ;\n wire [8:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_RDADDRECC_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB36E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .EN_ECC_READ(\"FALSE\"),\n .EN_ECC_WRITE(\"FALSE\"),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(36'h000000000),\n .INIT_B(36'h000000000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_EXTENSION_A(\"NONE\"),\n .RAM_EXTENSION_B(\"NONE\"),\n .RAM_MODE(\"SDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(72),\n .READ_WIDTH_B(0),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(36'h000000000),\n .SRVAL_B(36'h000000000),\n .WRITE_MODE_A(\"WRITE_FIRST\"),\n .WRITE_MODE_B(\"WRITE_FIRST\"),\n .WRITE_WIDTH_A(0),\n .WRITE_WIDTH_B(18)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram \n (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .ADDRBWRADDR({1'b1,\\gic0.gc0.count_d2_reg[10] ,1'b1,1'b1,1'b1,1'b1}),\n .CASCADEINA(1'b0),\n .CASCADEINB(1'b0),\n .CASCADEOUTA(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_CASCADEOUTA_UNCONNECTED ),\n .CASCADEOUTB(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_CASCADEOUTB_UNCONNECTED ),\n .CLKARDCLK(rd_clk),\n .CLKBWRCLK(wr_clk),\n .DBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_DBITERR_UNCONNECTED ),\n .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[16:9],din[7:0]}),\n .DIPADIP({1'b0,1'b0,1'b0,1'b0}),\n .DIPBDIP({1'b0,1'b0,din[17],din[8]}),\n .DOADO({dout[52:45],dout[43:36],dout[70:63],dout[61:54]}),\n .DOBDO({dout[16:9],dout[7:0],dout[34:27],dout[25:18]}),\n .DOPADOP({dout[53],dout[44],dout[71],dout[62]}),\n .DOPBDOP({dout[17],dout[8],dout[35],dout[26]}),\n .ECCPARITY(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_ECCPARITY_UNCONNECTED [7:0]),\n .ENARDEN(tmp_ram_rd_en),\n .ENBWREN(ram_full_fb_i_reg),\n .INJECTDBITERR(1'b0),\n .INJECTSBITERR(1'b0),\n .RDADDRECC(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_RDADDRECC_UNCONNECTED [8:0]),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(out),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .SBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_SBITERR_UNCONNECTED ),\n .WEA({1'b0,1'b0,1'b0,1'b0}),\n .WEBWE({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule fb_input_fifo_blk_mem_gen_prim_wrapper__parameterized0\n (dout,\n rd_clk,\n wr_clk,\n tmp_ram_rd_en,\n ram_full_fb_i_reg,\n out,\n Q,\n \\gic0.gc0.count_d2_reg[10] ,\n din);\n output [71:0]dout;\n input rd_clk;\n input wr_clk;\n input tmp_ram_rd_en;\n input ram_full_fb_i_reg;\n input [0:0]out;\n input [8:0]Q;\n input [10:0]\\gic0.gc0.count_d2_reg[10] ;\n input [17:0]din;\n\n wire [8:0]Q;\n wire [17:0]din;\n wire [71:0]dout;\n wire [10:0]\\gic0.gc0.count_d2_reg[10] ;\n wire [0:0]out;\n wire ram_full_fb_i_reg;\n wire rd_clk;\n wire tmp_ram_rd_en;\n wire wr_clk;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_CASCADEOUTA_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_CASCADEOUTB_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_DBITERR_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_SBITERR_UNCONNECTED ;\n wire [7:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_ECCPARITY_UNCONNECTED ;\n wire [8:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_RDADDRECC_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB36E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .EN_ECC_READ(\"FALSE\"),\n .EN_ECC_WRITE(\"FALSE\"),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(36'h000000000),\n .INIT_B(36'h000000000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_EXTENSION_A(\"NONE\"),\n .RAM_EXTENSION_B(\"NONE\"),\n .RAM_MODE(\"SDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(72),\n .READ_WIDTH_B(0),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(36'h000000000),\n .SRVAL_B(36'h000000000),\n .WRITE_MODE_A(\"WRITE_FIRST\"),\n .WRITE_MODE_B(\"WRITE_FIRST\"),\n .WRITE_WIDTH_A(0),\n .WRITE_WIDTH_B(18)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram \n (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .ADDRBWRADDR({1'b1,\\gic0.gc0.count_d2_reg[10] ,1'b1,1'b1,1'b1,1'b1}),\n .CASCADEINA(1'b0),\n .CASCADEINB(1'b0),\n .CASCADEOUTA(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_CASCADEOUTA_UNCONNECTED ),\n .CASCADEOUTB(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_CASCADEOUTB_UNCONNECTED ),\n .CLKARDCLK(rd_clk),\n .CLKBWRCLK(wr_clk),\n .DBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_DBITERR_UNCONNECTED ),\n .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[16:9],din[7:0]}),\n .DIPADIP({1'b0,1'b0,1'b0,1'b0}),\n .DIPBDIP({1'b0,1'b0,din[17],din[8]}),\n .DOADO({dout[52:45],dout[43:36],dout[70:63],dout[61:54]}),\n .DOBDO({dout[16:9],dout[7:0],dout[34:27],dout[25:18]}),\n .DOPADOP({dout[53],dout[44],dout[71],dout[62]}),\n .DOPBDOP({dout[17],dout[8],dout[35],dout[26]}),\n .ECCPARITY(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_ECCPARITY_UNCONNECTED [7:0]),\n .ENARDEN(tmp_ram_rd_en),\n .ENBWREN(ram_full_fb_i_reg),\n .INJECTDBITERR(1'b0),\n .INJECTSBITERR(1'b0),\n .RDADDRECC(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_RDADDRECC_UNCONNECTED [8:0]),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(out),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .SBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_SBITERR_UNCONNECTED ),\n .WEA({1'b0,1'b0,1'b0,1'b0}),\n .WEBWE({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule fb_input_fifo_blk_mem_gen_prim_wrapper__parameterized1\n (dout,\n rd_clk,\n wr_clk,\n tmp_ram_rd_en,\n ram_full_fb_i_reg,\n out,\n Q,\n \\gic0.gc0.count_d2_reg[10] ,\n din);\n output [71:0]dout;\n input rd_clk;\n input wr_clk;\n input tmp_ram_rd_en;\n input ram_full_fb_i_reg;\n input [0:0]out;\n input [8:0]Q;\n input [10:0]\\gic0.gc0.count_d2_reg[10] ;\n input [17:0]din;\n\n wire [8:0]Q;\n wire [17:0]din;\n wire [71:0]dout;\n wire [10:0]\\gic0.gc0.count_d2_reg[10] ;\n wire [0:0]out;\n wire ram_full_fb_i_reg;\n wire rd_clk;\n wire tmp_ram_rd_en;\n wire wr_clk;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_CASCADEOUTA_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_CASCADEOUTB_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_DBITERR_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_SBITERR_UNCONNECTED ;\n wire [7:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_ECCPARITY_UNCONNECTED ;\n wire [8:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_RDADDRECC_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB36E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .EN_ECC_READ(\"FALSE\"),\n .EN_ECC_WRITE(\"FALSE\"),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(36'h000000000),\n .INIT_B(36'h000000000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_EXTENSION_A(\"NONE\"),\n .RAM_EXTENSION_B(\"NONE\"),\n .RAM_MODE(\"SDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(72),\n .READ_WIDTH_B(0),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(36'h000000000),\n .SRVAL_B(36'h000000000),\n .WRITE_MODE_A(\"WRITE_FIRST\"),\n .WRITE_MODE_B(\"WRITE_FIRST\"),\n .WRITE_WIDTH_A(0),\n .WRITE_WIDTH_B(18)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram \n (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .ADDRBWRADDR({1'b1,\\gic0.gc0.count_d2_reg[10] ,1'b1,1'b1,1'b1,1'b1}),\n .CASCADEINA(1'b0),\n .CASCADEINB(1'b0),\n .CASCADEOUTA(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_CASCADEOUTA_UNCONNECTED ),\n .CASCADEOUTB(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_CASCADEOUTB_UNCONNECTED ),\n .CLKARDCLK(rd_clk),\n .CLKBWRCLK(wr_clk),\n .DBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_DBITERR_UNCONNECTED ),\n .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[16:9],din[7:0]}),\n .DIPADIP({1'b0,1'b0,1'b0,1'b0}),\n .DIPBDIP({1'b0,1'b0,din[17],din[8]}),\n .DOADO({dout[52:45],dout[43:36],dout[70:63],dout[61:54]}),\n .DOBDO({dout[16:9],dout[7:0],dout[34:27],dout[25:18]}),\n .DOPADOP({dout[53],dout[44],dout[71],dout[62]}),\n .DOPBDOP({dout[17],dout[8],dout[35],dout[26]}),\n .ECCPARITY(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_ECCPARITY_UNCONNECTED [7:0]),\n .ENARDEN(tmp_ram_rd_en),\n .ENBWREN(ram_full_fb_i_reg),\n .INJECTDBITERR(1'b0),\n .INJECTSBITERR(1'b0),\n .RDADDRECC(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_RDADDRECC_UNCONNECTED [8:0]),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(out),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .SBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_SBITERR_UNCONNECTED ),\n .WEA({1'b0,1'b0,1'b0,1'b0}),\n .WEBWE({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule fb_input_fifo_blk_mem_gen_prim_wrapper__parameterized2\n (dout,\n rd_clk,\n wr_clk,\n tmp_ram_rd_en,\n ram_full_fb_i_reg,\n out,\n Q,\n \\gic0.gc0.count_d2_reg[10] ,\n din);\n output [39:0]dout;\n input rd_clk;\n input wr_clk;\n input tmp_ram_rd_en;\n input ram_full_fb_i_reg;\n input [0:0]out;\n input [8:0]Q;\n input [10:0]\\gic0.gc0.count_d2_reg[10] ;\n input [9:0]din;\n\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_21 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_22 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_23 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_29 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_30 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_31 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_37 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_38 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_39 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_45 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_46 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_47 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_53 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_54 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_55 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_61 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_62 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_63 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_69 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_70 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_71 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_77 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_78 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_79 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_85 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_86 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_87 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_88 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_89 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_90 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_91 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_92 ;\n wire [8:0]Q;\n wire [9:0]din;\n wire [39:0]dout;\n wire [10:0]\\gic0.gc0.count_d2_reg[10] ;\n wire [0:0]out;\n wire ram_full_fb_i_reg;\n wire rd_clk;\n wire tmp_ram_rd_en;\n wire wr_clk;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_CASCADEOUTA_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_CASCADEOUTB_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_DBITERR_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_SBITERR_UNCONNECTED ;\n wire [7:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_ECCPARITY_UNCONNECTED ;\n wire [8:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_RDADDRECC_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB36E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .EN_ECC_READ(\"FALSE\"),\n .EN_ECC_WRITE(\"FALSE\"),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(36'h000000000),\n .INIT_B(36'h000000000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_EXTENSION_A(\"NONE\"),\n .RAM_EXTENSION_B(\"NONE\"),\n .RAM_MODE(\"SDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(72),\n .READ_WIDTH_B(0),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(36'h000000000),\n .SRVAL_B(36'h000000000),\n .WRITE_MODE_A(\"WRITE_FIRST\"),\n .WRITE_MODE_B(\"WRITE_FIRST\"),\n .WRITE_WIDTH_A(0),\n .WRITE_WIDTH_B(18)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram \n (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .ADDRBWRADDR({1'b1,\\gic0.gc0.count_d2_reg[10] ,1'b1,1'b1,1'b1,1'b1}),\n .CASCADEINA(1'b0),\n .CASCADEINB(1'b0),\n .CASCADEOUTA(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_CASCADEOUTA_UNCONNECTED ),\n .CASCADEOUTB(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_CASCADEOUTB_UNCONNECTED ),\n .CLKARDCLK(rd_clk),\n .CLKBWRCLK(wr_clk),\n .DBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_DBITERR_UNCONNECTED ),\n .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[9:5],1'b0,1'b0,1'b0,din[4:0]}),\n .DIPADIP({1'b0,1'b0,1'b0,1'b0}),\n .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),\n .DOADO({\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_21 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_22 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_23 ,dout[29:25],\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_29 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_30 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_31 ,dout[24:20],\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_37 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_38 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_39 ,dout[39:35],\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_45 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_46 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_47 ,dout[34:30]}),\n .DOBDO({\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_53 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_54 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_55 ,dout[9:5],\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_61 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_62 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_63 ,dout[4:0],\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_69 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_70 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_71 ,dout[19:15],\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_77 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_78 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_79 ,dout[14:10]}),\n .DOPADOP({\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_85 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_86 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_87 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_88 }),\n .DOPBDOP({\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_89 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_90 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_91 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_n_92 }),\n .ECCPARITY(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_ECCPARITY_UNCONNECTED [7:0]),\n .ENARDEN(tmp_ram_rd_en),\n .ENBWREN(ram_full_fb_i_reg),\n .INJECTDBITERR(1'b0),\n .INJECTSBITERR(1'b0),\n .RDADDRECC(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_RDADDRECC_UNCONNECTED [8:0]),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(out),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .SBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_SBITERR_UNCONNECTED ),\n .WEA({1'b0,1'b0,1'b0,1'b0}),\n .WEBWE({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_top\" *) \nmodule fb_input_fifo_blk_mem_gen_top\n (dout,\n rd_clk,\n wr_clk,\n tmp_ram_rd_en,\n ram_full_fb_i_reg,\n out,\n Q,\n \\gic0.gc0.count_d2_reg[10] ,\n din);\n output [255:0]dout;\n input rd_clk;\n input wr_clk;\n input tmp_ram_rd_en;\n input ram_full_fb_i_reg;\n input [0:0]out;\n input [8:0]Q;\n input [10:0]\\gic0.gc0.count_d2_reg[10] ;\n input [63:0]din;\n\n wire [8:0]Q;\n wire [63:0]din;\n wire [255:0]dout;\n wire [10:0]\\gic0.gc0.count_d2_reg[10] ;\n wire [0:0]out;\n wire ram_full_fb_i_reg;\n wire rd_clk;\n wire tmp_ram_rd_en;\n wire wr_clk;\n\n fb_input_fifo_blk_mem_gen_generic_cstr \\valid.cstr \n (.Q(Q),\n .din(din),\n .dout(dout),\n .\\gic0.gc0.count_d2_reg[10] (\\gic0.gc0.count_d2_reg[10] ),\n .out(out),\n .ram_full_fb_i_reg(ram_full_fb_i_reg),\n .rd_clk(rd_clk),\n .tmp_ram_rd_en(tmp_ram_rd_en),\n .wr_clk(wr_clk));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_v8_3_4\" *) \nmodule fb_input_fifo_blk_mem_gen_v8_3_4\n (dout,\n rd_clk,\n wr_clk,\n tmp_ram_rd_en,\n ram_full_fb_i_reg,\n out,\n Q,\n \\gic0.gc0.count_d2_reg[10] ,\n din);\n output [255:0]dout;\n input rd_clk;\n input wr_clk;\n input tmp_ram_rd_en;\n input ram_full_fb_i_reg;\n input [0:0]out;\n input [8:0]Q;\n input [10:0]\\gic0.gc0.count_d2_reg[10] ;\n input [63:0]din;\n\n wire [8:0]Q;\n wire [63:0]din;\n wire [255:0]dout;\n wire [10:0]\\gic0.gc0.count_d2_reg[10] ;\n wire [0:0]out;\n wire ram_full_fb_i_reg;\n wire rd_clk;\n wire tmp_ram_rd_en;\n wire wr_clk;\n\n fb_input_fifo_blk_mem_gen_v8_3_4_synth inst_blk_mem_gen\n (.Q(Q),\n .din(din),\n .dout(dout),\n .\\gic0.gc0.count_d2_reg[10] (\\gic0.gc0.count_d2_reg[10] ),\n .out(out),\n .ram_full_fb_i_reg(ram_full_fb_i_reg),\n .rd_clk(rd_clk),\n .tmp_ram_rd_en(tmp_ram_rd_en),\n .wr_clk(wr_clk));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_v8_3_4_synth\" *) \nmodule fb_input_fifo_blk_mem_gen_v8_3_4_synth\n (dout,\n rd_clk,\n wr_clk,\n tmp_ram_rd_en,\n ram_full_fb_i_reg,\n out,\n Q,\n \\gic0.gc0.count_d2_reg[10] ,\n din);\n output [255:0]dout;\n input rd_clk;\n input wr_clk;\n input tmp_ram_rd_en;\n input ram_full_fb_i_reg;\n input [0:0]out;\n input [8:0]Q;\n input [10:0]\\gic0.gc0.count_d2_reg[10] ;\n input [63:0]din;\n\n wire [8:0]Q;\n wire [63:0]din;\n wire [255:0]dout;\n wire [10:0]\\gic0.gc0.count_d2_reg[10] ;\n wire [0:0]out;\n wire ram_full_fb_i_reg;\n wire rd_clk;\n wire tmp_ram_rd_en;\n wire wr_clk;\n\n fb_input_fifo_blk_mem_gen_top \\gnbram.gnativebmg.native_blk_mem_gen \n (.Q(Q),\n .din(din),\n .dout(dout),\n .\\gic0.gc0.count_d2_reg[10] (\\gic0.gc0.count_d2_reg[10] ),\n .out(out),\n .ram_full_fb_i_reg(ram_full_fb_i_reg),\n .rd_clk(rd_clk),\n .tmp_ram_rd_en(tmp_ram_rd_en),\n .wr_clk(wr_clk));\nendmodule\n\n(* ORIG_REF_NAME = \"clk_x_pntrs\" *) \nmodule fb_input_fifo_clk_x_pntrs\n (S,\n WR_PNTR_RD,\n \\gdiff.diff_pntr_pad_reg[8] ,\n \\gdiff.diff_pntr_pad_reg[9] ,\n ram_full_fb_i_reg,\n RD_PNTR_WR,\n ram_full_fb_i_reg_0,\n v1_reg,\n v1_reg_0,\n Q,\n \\gic0.gc0.count_d1_reg[10] ,\n D,\n \\gc0.count_reg[7] ,\n \\gic0.gc0.count_d2_reg[10] ,\n wr_clk,\n AR,\n rd_clk,\n \\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );\n output [3:0]S;\n output [8:0]WR_PNTR_RD;\n output [3:0]\\gdiff.diff_pntr_pad_reg[8] ;\n output [0:0]\\gdiff.diff_pntr_pad_reg[9] ;\n output ram_full_fb_i_reg;\n output [7:0]RD_PNTR_WR;\n output ram_full_fb_i_reg_0;\n output [3:0]v1_reg;\n output [3:0]v1_reg_0;\n input [8:0]Q;\n input [0:0]\\gic0.gc0.count_d1_reg[10] ;\n input [0:0]D;\n input [7:0]\\gc0.count_reg[7] ;\n input [10:0]\\gic0.gc0.count_d2_reg[10] ;\n input wr_clk;\n input [0:0]AR;\n input rd_clk;\n input [0:0]\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;\n\n wire [0:0]AR;\n wire [0:0]D;\n wire [8:0]Q;\n wire [7:0]RD_PNTR_WR;\n wire [3:0]S;\n wire [8:0]WR_PNTR_RD;\n wire [9:0]bin2gray;\n wire [7:0]\\gc0.count_reg[7] ;\n wire [3:0]\\gdiff.diff_pntr_pad_reg[8] ;\n wire [0:0]\\gdiff.diff_pntr_pad_reg[9] ;\n wire [0:0]\\gic0.gc0.count_d1_reg[10] ;\n wire [10:0]\\gic0.gc0.count_d2_reg[10] ;\n wire \\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ;\n wire \\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ;\n wire \\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ;\n wire \\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ;\n wire \\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ;\n wire \\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ;\n wire \\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ;\n wire \\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ;\n wire \\gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 ;\n wire \\gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 ;\n wire \\gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 ;\n wire \\gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 ;\n wire \\gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 ;\n wire \\gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 ;\n wire \\gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 ;\n wire \\gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 ;\n wire [8:2]gray2bin;\n wire [0:0]\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;\n wire p_0_out;\n wire [8:8]p_23_out;\n wire [10:0]p_3_out;\n wire [8:0]p_4_out;\n wire [10:10]p_5_out;\n wire [8:8]p_6_out;\n wire ram_full_fb_i_reg;\n wire ram_full_fb_i_reg_0;\n wire rd_clk;\n wire [8:0]rd_pntr_gc;\n wire [3:0]v1_reg;\n wire [3:0]v1_reg_0;\n wire wr_clk;\n wire [10:0]wr_pntr_gc;\n\n LUT4 #(\n .INIT(16'h9009)) \n \\gmux.gm[0].gm1.m1_i_1 \n (.I0(WR_PNTR_RD[0]),\n .I1(Q[0]),\n .I2(WR_PNTR_RD[1]),\n .I3(Q[1]),\n .O(v1_reg[0]));\n LUT4 #(\n .INIT(16'h9009)) \n \\gmux.gm[0].gm1.m1_i_1__0 \n (.I0(WR_PNTR_RD[0]),\n .I1(\\gc0.count_reg[7] [0]),\n .I2(WR_PNTR_RD[1]),\n .I3(\\gc0.count_reg[7] [1]),\n .O(v1_reg_0[0]));\n LUT4 #(\n .INIT(16'h9009)) \n \\gmux.gm[1].gms.ms_i_1 \n (.I0(WR_PNTR_RD[2]),\n .I1(Q[2]),\n .I2(WR_PNTR_RD[3]),\n .I3(Q[3]),\n .O(v1_reg[1]));\n LUT4 #(\n .INIT(16'h9009)) \n \\gmux.gm[1].gms.ms_i_1__0 \n (.I0(WR_PNTR_RD[2]),\n .I1(\\gc0.count_reg[7] [2]),\n .I2(WR_PNTR_RD[3]),\n .I3(\\gc0.count_reg[7] [3]),\n .O(v1_reg_0[1]));\n LUT4 #(\n .INIT(16'h9009)) \n \\gmux.gm[2].gms.ms_i_1 \n (.I0(WR_PNTR_RD[4]),\n .I1(Q[4]),\n .I2(WR_PNTR_RD[5]),\n .I3(Q[5]),\n .O(v1_reg[2]));\n LUT4 #(\n .INIT(16'h9009)) \n \\gmux.gm[2].gms.ms_i_1__0 \n (.I0(WR_PNTR_RD[4]),\n .I1(\\gc0.count_reg[7] [4]),\n .I2(WR_PNTR_RD[5]),\n .I3(\\gc0.count_reg[7] [5]),\n .O(v1_reg_0[2]));\n LUT4 #(\n .INIT(16'h9009)) \n \\gmux.gm[3].gms.ms_i_1 \n (.I0(WR_PNTR_RD[6]),\n .I1(Q[6]),\n .I2(WR_PNTR_RD[7]),\n .I3(Q[7]),\n .O(v1_reg[3]));\n LUT4 #(\n .INIT(16'h9009)) \n \\gmux.gm[3].gms.ms_i_1__0 \n (.I0(WR_PNTR_RD[6]),\n .I1(\\gc0.count_reg[7] [6]),\n .I2(WR_PNTR_RD[7]),\n .I3(\\gc0.count_reg[7] [7]),\n .O(v1_reg_0[3]));\n LUT2 #(\n .INIT(4'h9)) \n \\gmux.gm[5].gms.ms_i_1 \n (.I0(p_23_out),\n .I1(\\gic0.gc0.count_d1_reg[10] ),\n .O(ram_full_fb_i_reg));\n LUT2 #(\n .INIT(4'h9)) \n \\gmux.gm[5].gms.ms_i_1__0 \n (.I0(p_23_out),\n .I1(D),\n .O(ram_full_fb_i_reg_0));\n fb_input_fifo_synchronizer_ff__parameterized0 \\gnxpm_cdc.gsync_stage[1].rd_stg_inst \n (.D(p_3_out),\n .Q(wr_pntr_gc),\n .\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .rd_clk(rd_clk));\n fb_input_fifo_synchronizer_ff__parameterized1 \\gnxpm_cdc.gsync_stage[1].wr_stg_inst \n (.AR(AR),\n .D(p_4_out),\n .Q(rd_pntr_gc),\n .wr_clk(wr_clk));\n fb_input_fifo_synchronizer_ff__parameterized2 \\gnxpm_cdc.gsync_stage[2].rd_stg_inst \n (.D(p_3_out),\n .\\gnxpm_cdc.wr_pntr_bin_reg[9] ({p_0_out,gray2bin}),\n .\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .out(p_5_out),\n .rd_clk(rd_clk));\n fb_input_fifo_synchronizer_ff__parameterized3 \\gnxpm_cdc.gsync_stage[2].wr_stg_inst \n (.AR(AR),\n .D(p_4_out),\n .\\gnxpm_cdc.rd_pntr_bin_reg[7] ({\\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ,\\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ,\\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ,\\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ,\\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ,\\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ,\\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ,\\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 }),\n .out(p_6_out),\n .wr_clk(wr_clk));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_bin_reg[0] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(\\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ),\n .Q(RD_PNTR_WR[0]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_bin_reg[1] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(\\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ),\n .Q(RD_PNTR_WR[1]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_bin_reg[2] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(\\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ),\n .Q(RD_PNTR_WR[2]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_bin_reg[3] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(\\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ),\n .Q(RD_PNTR_WR[3]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_bin_reg[4] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(\\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ),\n .Q(RD_PNTR_WR[4]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_bin_reg[5] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(\\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ),\n .Q(RD_PNTR_WR[5]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_bin_reg[6] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(\\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ),\n .Q(RD_PNTR_WR[6]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_bin_reg[7] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(\\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ),\n .Q(RD_PNTR_WR[7]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_bin_reg[8] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(p_6_out),\n .Q(p_23_out));\n (* SOFT_HLUTNM = \"soft_lutpair5\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.rd_pntr_gc[0]_i_1 \n (.I0(Q[0]),\n .I1(Q[1]),\n .O(\\gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair5\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.rd_pntr_gc[1]_i_1 \n (.I0(Q[1]),\n .I1(Q[2]),\n .O(\\gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair6\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.rd_pntr_gc[2]_i_1 \n (.I0(Q[2]),\n .I1(Q[3]),\n .O(\\gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair6\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.rd_pntr_gc[3]_i_1 \n (.I0(Q[3]),\n .I1(Q[4]),\n .O(\\gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair7\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.rd_pntr_gc[4]_i_1 \n (.I0(Q[4]),\n .I1(Q[5]),\n .O(\\gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair7\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.rd_pntr_gc[5]_i_1 \n (.I0(Q[5]),\n .I1(Q[6]),\n .O(\\gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair8\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.rd_pntr_gc[6]_i_1 \n (.I0(Q[6]),\n .I1(Q[7]),\n .O(\\gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair8\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.rd_pntr_gc[7]_i_1 \n (.I0(Q[7]),\n .I1(Q[8]),\n .O(\\gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 ));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_gc_reg[0] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(\\gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 ),\n .Q(rd_pntr_gc[0]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_gc_reg[1] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(\\gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 ),\n .Q(rd_pntr_gc[1]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_gc_reg[2] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(\\gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 ),\n .Q(rd_pntr_gc[2]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_gc_reg[3] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(\\gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 ),\n .Q(rd_pntr_gc[3]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_gc_reg[4] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(\\gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 ),\n .Q(rd_pntr_gc[4]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_gc_reg[5] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(\\gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 ),\n .Q(rd_pntr_gc[5]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_gc_reg[6] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(\\gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 ),\n .Q(rd_pntr_gc[6]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_gc_reg[7] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(\\gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 ),\n .Q(rd_pntr_gc[7]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_gc_reg[8] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(Q[8]),\n .Q(rd_pntr_gc[8]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_bin_reg[10] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(p_5_out),\n .Q(WR_PNTR_RD[8]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_bin_reg[2] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(gray2bin[2]),\n .Q(WR_PNTR_RD[0]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_bin_reg[3] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(gray2bin[3]),\n .Q(WR_PNTR_RD[1]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_bin_reg[4] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(gray2bin[4]),\n .Q(WR_PNTR_RD[2]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_bin_reg[5] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(gray2bin[5]),\n .Q(WR_PNTR_RD[3]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_bin_reg[6] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(gray2bin[6]),\n .Q(WR_PNTR_RD[4]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_bin_reg[7] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(gray2bin[7]),\n .Q(WR_PNTR_RD[5]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_bin_reg[8] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(gray2bin[8]),\n .Q(WR_PNTR_RD[6]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_bin_reg[9] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(p_0_out),\n .Q(WR_PNTR_RD[7]));\n (* SOFT_HLUTNM = \"soft_lutpair0\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.wr_pntr_gc[0]_i_1 \n (.I0(\\gic0.gc0.count_d2_reg[10] [0]),\n .I1(\\gic0.gc0.count_d2_reg[10] [1]),\n .O(bin2gray[0]));\n (* SOFT_HLUTNM = \"soft_lutpair0\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.wr_pntr_gc[1]_i_1 \n (.I0(\\gic0.gc0.count_d2_reg[10] [1]),\n .I1(\\gic0.gc0.count_d2_reg[10] [2]),\n .O(bin2gray[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.wr_pntr_gc[2]_i_1 \n (.I0(\\gic0.gc0.count_d2_reg[10] [2]),\n .I1(\\gic0.gc0.count_d2_reg[10] [3]),\n .O(bin2gray[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.wr_pntr_gc[3]_i_1 \n (.I0(\\gic0.gc0.count_d2_reg[10] [3]),\n .I1(\\gic0.gc0.count_d2_reg[10] [4]),\n .O(bin2gray[3]));\n (* SOFT_HLUTNM = \"soft_lutpair2\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.wr_pntr_gc[4]_i_1 \n (.I0(\\gic0.gc0.count_d2_reg[10] [4]),\n .I1(\\gic0.gc0.count_d2_reg[10] [5]),\n .O(bin2gray[4]));\n (* SOFT_HLUTNM = \"soft_lutpair2\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.wr_pntr_gc[5]_i_1 \n (.I0(\\gic0.gc0.count_d2_reg[10] [5]),\n .I1(\\gic0.gc0.count_d2_reg[10] [6]),\n .O(bin2gray[5]));\n (* SOFT_HLUTNM = \"soft_lutpair3\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.wr_pntr_gc[6]_i_1 \n (.I0(\\gic0.gc0.count_d2_reg[10] [6]),\n .I1(\\gic0.gc0.count_d2_reg[10] [7]),\n .O(bin2gray[6]));\n (* SOFT_HLUTNM = \"soft_lutpair3\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.wr_pntr_gc[7]_i_1 \n (.I0(\\gic0.gc0.count_d2_reg[10] [7]),\n .I1(\\gic0.gc0.count_d2_reg[10] [8]),\n .O(bin2gray[7]));\n (* SOFT_HLUTNM = \"soft_lutpair4\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.wr_pntr_gc[8]_i_1 \n (.I0(\\gic0.gc0.count_d2_reg[10] [8]),\n .I1(\\gic0.gc0.count_d2_reg[10] [9]),\n .O(bin2gray[8]));\n (* SOFT_HLUTNM = \"soft_lutpair4\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.wr_pntr_gc[9]_i_1 \n (.I0(\\gic0.gc0.count_d2_reg[10] [9]),\n .I1(\\gic0.gc0.count_d2_reg[10] [10]),\n .O(bin2gray[9]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_gc_reg[0] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(bin2gray[0]),\n .Q(wr_pntr_gc[0]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_gc_reg[10] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(\\gic0.gc0.count_d2_reg[10] [10]),\n .Q(wr_pntr_gc[10]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_gc_reg[1] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(bin2gray[1]),\n .Q(wr_pntr_gc[1]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_gc_reg[2] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(bin2gray[2]),\n .Q(wr_pntr_gc[2]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_gc_reg[3] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(bin2gray[3]),\n .Q(wr_pntr_gc[3]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_gc_reg[4] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(bin2gray[4]),\n .Q(wr_pntr_gc[4]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_gc_reg[5] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(bin2gray[5]),\n .Q(wr_pntr_gc[5]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_gc_reg[6] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(bin2gray[6]),\n .Q(wr_pntr_gc[6]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_gc_reg[7] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(bin2gray[7]),\n .Q(wr_pntr_gc[7]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_gc_reg[8] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(bin2gray[8]),\n .Q(wr_pntr_gc[8]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_gc_reg[9] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(bin2gray[9]),\n .Q(wr_pntr_gc[9]));\n LUT2 #(\n .INIT(4'h9)) \n plusOp_carry__0_i_1\n (.I0(WR_PNTR_RD[7]),\n .I1(Q[7]),\n .O(\\gdiff.diff_pntr_pad_reg[8] [3]));\n LUT2 #(\n .INIT(4'h9)) \n plusOp_carry__0_i_2\n (.I0(WR_PNTR_RD[6]),\n .I1(Q[6]),\n .O(\\gdiff.diff_pntr_pad_reg[8] [2]));\n LUT2 #(\n .INIT(4'h9)) \n plusOp_carry__0_i_3\n (.I0(WR_PNTR_RD[5]),\n .I1(Q[5]),\n .O(\\gdiff.diff_pntr_pad_reg[8] [1]));\n LUT2 #(\n .INIT(4'h9)) \n plusOp_carry__0_i_4\n (.I0(WR_PNTR_RD[4]),\n .I1(Q[4]),\n .O(\\gdiff.diff_pntr_pad_reg[8] [0]));\n LUT2 #(\n .INIT(4'h9)) \n plusOp_carry__1_i_1\n (.I0(WR_PNTR_RD[8]),\n .I1(Q[8]),\n .O(\\gdiff.diff_pntr_pad_reg[9] ));\n LUT2 #(\n .INIT(4'h9)) \n plusOp_carry_i_2\n (.I0(WR_PNTR_RD[3]),\n .I1(Q[3]),\n .O(S[3]));\n LUT2 #(\n .INIT(4'h9)) \n plusOp_carry_i_3\n (.I0(WR_PNTR_RD[2]),\n .I1(Q[2]),\n .O(S[2]));\n LUT2 #(\n .INIT(4'h9)) \n plusOp_carry_i_4\n (.I0(WR_PNTR_RD[1]),\n .I1(Q[1]),\n .O(S[1]));\n LUT2 #(\n .INIT(4'h9)) \n plusOp_carry_i_5\n (.I0(WR_PNTR_RD[0]),\n .I1(Q[0]),\n .O(S[0]));\nendmodule\n\n(* ORIG_REF_NAME = \"compare\" *) \nmodule fb_input_fifo_compare\n (ram_empty_fb_i_reg,\n v1_reg,\n \\gc0.count_d1_reg[8] ,\n rd_en,\n out,\n comp1);\n output ram_empty_fb_i_reg;\n input [3:0]v1_reg;\n input \\gc0.count_d1_reg[8] ;\n input rd_en;\n input out;\n input comp1;\n\n wire carrynet_0;\n wire carrynet_1;\n wire carrynet_2;\n wire carrynet_3;\n wire comp0;\n wire comp1;\n wire \\gc0.count_d1_reg[8] ;\n wire out;\n wire ram_empty_fb_i_reg;\n wire rd_en;\n wire [3:0]v1_reg;\n wire [3:0]\\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;\n wire [3:1]\\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;\n wire [3:1]\\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;\n wire [3:0]\\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;\n wire [3:1]\\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;\n\n (* XILINX_LEGACY_PRIM = \"(MUXCY,XORCY)\" *) \n (* box_type = \"PRIMITIVE\" *) \n CARRY4 \\gmux.gm[0].gm1.m1_CARRY4 \n (.CI(1'b0),\n .CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),\n .CYINIT(1'b1),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),\n .S(v1_reg));\n (* XILINX_LEGACY_PRIM = \"(MUXCY,XORCY)\" *) \n (* box_type = \"PRIMITIVE\" *) \n CARRY4 \\gmux.gm[4].gms.ms_CARRY4 \n (.CI(carrynet_3),\n .CO({\\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp0}),\n .CYINIT(1'b0),\n .DI({\\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),\n .O(\\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),\n .S({\\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],\\gc0.count_d1_reg[8] }));\n LUT4 #(\n .INIT(16'hAEAA)) \n ram_empty_i_i_1\n (.I0(comp0),\n .I1(rd_en),\n .I2(out),\n .I3(comp1),\n .O(ram_empty_fb_i_reg));\nendmodule\n\n(* ORIG_REF_NAME = \"compare\" *) \nmodule fb_input_fifo_compare_3\n (comp1,\n v1_reg_0,\n \\gc0.count_reg[8] );\n output comp1;\n input [3:0]v1_reg_0;\n input \\gc0.count_reg[8] ;\n\n wire carrynet_0;\n wire carrynet_1;\n wire carrynet_2;\n wire carrynet_3;\n wire comp1;\n wire \\gc0.count_reg[8] ;\n wire [3:0]v1_reg_0;\n wire [3:0]\\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;\n wire [3:1]\\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;\n wire [3:1]\\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;\n wire [3:0]\\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;\n wire [3:1]\\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;\n\n (* XILINX_LEGACY_PRIM = \"(MUXCY,XORCY)\" *) \n (* box_type = \"PRIMITIVE\" *) \n CARRY4 \\gmux.gm[0].gm1.m1_CARRY4 \n (.CI(1'b0),\n .CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),\n .CYINIT(1'b1),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),\n .S(v1_reg_0));\n (* XILINX_LEGACY_PRIM = \"(MUXCY,XORCY)\" *) \n (* box_type = \"PRIMITIVE\" *) \n CARRY4 \\gmux.gm[4].gms.ms_CARRY4 \n (.CI(carrynet_3),\n .CO({\\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}),\n .CYINIT(1'b0),\n .DI({\\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),\n .O(\\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),\n .S({\\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],\\gc0.count_reg[8] }));\nendmodule\n\n(* ORIG_REF_NAME = \"compare\" *) \nmodule fb_input_fifo_compare__parameterized0\n (comp1,\n v1_reg,\n \\gnxpm_cdc.rd_pntr_bin_reg[8] );\n output comp1;\n input [4:0]v1_reg;\n input \\gnxpm_cdc.rd_pntr_bin_reg[8] ;\n\n wire carrynet_0;\n wire carrynet_1;\n wire carrynet_2;\n wire carrynet_3;\n wire carrynet_4;\n wire comp1;\n wire \\gnxpm_cdc.rd_pntr_bin_reg[8] ;\n wire [4:0]v1_reg;\n wire [3:0]\\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;\n wire [3:2]\\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;\n wire [3:2]\\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;\n wire [3:0]\\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;\n wire [3:2]\\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;\n\n (* XILINX_LEGACY_PRIM = \"(MUXCY,XORCY)\" *) \n (* box_type = \"PRIMITIVE\" *) \n CARRY4 \\gmux.gm[0].gm1.m1_CARRY4 \n (.CI(1'b0),\n .CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),\n .CYINIT(1'b1),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),\n .S(v1_reg[3:0]));\n (* XILINX_LEGACY_PRIM = \"(MUXCY,XORCY)\" *) \n (* box_type = \"PRIMITIVE\" *) \n CARRY4 \\gmux.gm[4].gms.ms_CARRY4 \n (.CI(carrynet_3),\n .CO({\\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp1,carrynet_4}),\n .CYINIT(1'b0),\n .DI({\\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),\n .O(\\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),\n .S({\\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],\\gnxpm_cdc.rd_pntr_bin_reg[8] ,v1_reg[4]}));\nendmodule\n\n(* ORIG_REF_NAME = \"compare\" *) \nmodule fb_input_fifo_compare__parameterized1\n (ram_full_fb_i_reg,\n v1_reg_0,\n \\gnxpm_cdc.rd_pntr_bin_reg[8] ,\n wr_rst_busy,\n out,\n wr_en,\n comp1);\n output ram_full_fb_i_reg;\n input [4:0]v1_reg_0;\n input \\gnxpm_cdc.rd_pntr_bin_reg[8] ;\n input wr_rst_busy;\n input out;\n input wr_en;\n input comp1;\n\n wire carrynet_0;\n wire carrynet_1;\n wire carrynet_2;\n wire carrynet_3;\n wire carrynet_4;\n wire comp1;\n wire comp2;\n wire \\gnxpm_cdc.rd_pntr_bin_reg[8] ;\n wire out;\n wire ram_full_fb_i_reg;\n wire [4:0]v1_reg_0;\n wire wr_en;\n wire wr_rst_busy;\n wire [3:0]\\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;\n wire [3:2]\\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;\n wire [3:2]\\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;\n wire [3:0]\\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;\n wire [3:2]\\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;\n\n (* XILINX_LEGACY_PRIM = \"(MUXCY,XORCY)\" *) \n (* box_type = \"PRIMITIVE\" *) \n CARRY4 \\gmux.gm[0].gm1.m1_CARRY4 \n (.CI(1'b0),\n .CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),\n .CYINIT(1'b1),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),\n .S(v1_reg_0[3:0]));\n (* XILINX_LEGACY_PRIM = \"(MUXCY,XORCY)\" *) \n (* box_type = \"PRIMITIVE\" *) \n CARRY4 \\gmux.gm[4].gms.ms_CARRY4 \n (.CI(carrynet_3),\n .CO({\\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp2,carrynet_4}),\n .CYINIT(1'b0),\n .DI({\\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),\n .O(\\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),\n .S({\\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],\\gnxpm_cdc.rd_pntr_bin_reg[8] ,v1_reg_0[4]}));\n LUT5 #(\n .INIT(32'h55550400)) \n ram_full_i_i_1\n (.I0(wr_rst_busy),\n .I1(comp2),\n .I2(out),\n .I3(wr_en),\n .I4(comp1),\n .O(ram_full_fb_i_reg));\nendmodule\n\n(* ORIG_REF_NAME = \"fifo_generator_ramfifo\" *) \nmodule fb_input_fifo_fifo_generator_ramfifo\n (wr_rst_busy,\n dout,\n empty,\n full,\n prog_empty,\n rd_en,\n wr_en,\n rd_clk,\n wr_clk,\n din,\n rst);\n output wr_rst_busy;\n output [255:0]dout;\n output empty;\n output full;\n output prog_empty;\n input rd_en;\n input wr_en;\n input rd_clk;\n input wr_clk;\n input [63:0]din;\n input rst;\n\n wire [63:0]din;\n wire [255:0]dout;\n wire empty;\n wire full;\n wire \\gntv_or_sync_fifo.gcx.clkx_n_0 ;\n wire \\gntv_or_sync_fifo.gcx.clkx_n_1 ;\n wire \\gntv_or_sync_fifo.gcx.clkx_n_13 ;\n wire \\gntv_or_sync_fifo.gcx.clkx_n_14 ;\n wire \\gntv_or_sync_fifo.gcx.clkx_n_15 ;\n wire \\gntv_or_sync_fifo.gcx.clkx_n_16 ;\n wire \\gntv_or_sync_fifo.gcx.clkx_n_17 ;\n wire \\gntv_or_sync_fifo.gcx.clkx_n_18 ;\n wire \\gntv_or_sync_fifo.gcx.clkx_n_2 ;\n wire \\gntv_or_sync_fifo.gcx.clkx_n_27 ;\n wire \\gntv_or_sync_fifo.gcx.clkx_n_3 ;\n wire \\gntv_or_sync_fifo.gl0.wr_n_1 ;\n wire [3:0]\\gras.rsts/c0/v1_reg ;\n wire [3:0]\\gras.rsts/c1/v1_reg ;\n wire [8:0]p_0_out_0;\n wire [10:0]p_12_out;\n wire [10:10]p_13_out;\n wire [10:2]p_22_out;\n wire [7:0]p_23_out;\n wire p_2_out;\n wire prog_empty;\n wire rd_clk;\n wire rd_en;\n wire [7:0]rd_pntr_plus1;\n wire [2:0]rd_rst_i;\n wire rst;\n wire rst_full_ff_i;\n wire tmp_ram_rd_en;\n wire wr_clk;\n wire wr_en;\n wire [10:10]wr_pntr_plus2;\n wire wr_rst_busy;\n wire [1:0]wr_rst_i;\n\n fb_input_fifo_clk_x_pntrs \\gntv_or_sync_fifo.gcx.clkx \n (.AR(wr_rst_i[0]),\n .D(wr_pntr_plus2),\n .Q(p_0_out_0),\n .RD_PNTR_WR(p_23_out),\n .S({\\gntv_or_sync_fifo.gcx.clkx_n_0 ,\\gntv_or_sync_fifo.gcx.clkx_n_1 ,\\gntv_or_sync_fifo.gcx.clkx_n_2 ,\\gntv_or_sync_fifo.gcx.clkx_n_3 }),\n .WR_PNTR_RD(p_22_out),\n .\\gc0.count_reg[7] (rd_pntr_plus1),\n .\\gdiff.diff_pntr_pad_reg[8] ({\\gntv_or_sync_fifo.gcx.clkx_n_13 ,\\gntv_or_sync_fifo.gcx.clkx_n_14 ,\\gntv_or_sync_fifo.gcx.clkx_n_15 ,\\gntv_or_sync_fifo.gcx.clkx_n_16 }),\n .\\gdiff.diff_pntr_pad_reg[9] (\\gntv_or_sync_fifo.gcx.clkx_n_17 ),\n .\\gic0.gc0.count_d1_reg[10] (p_13_out),\n .\\gic0.gc0.count_d2_reg[10] (p_12_out),\n .\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (rd_rst_i[1]),\n .ram_full_fb_i_reg(\\gntv_or_sync_fifo.gcx.clkx_n_18 ),\n .ram_full_fb_i_reg_0(\\gntv_or_sync_fifo.gcx.clkx_n_27 ),\n .rd_clk(rd_clk),\n .v1_reg(\\gras.rsts/c0/v1_reg ),\n .v1_reg_0(\\gras.rsts/c1/v1_reg ),\n .wr_clk(wr_clk));\n fb_input_fifo_rd_logic \\gntv_or_sync_fifo.gl0.rd \n (.AR(rd_rst_i[2]),\n .Q(p_0_out_0),\n .S({\\gntv_or_sync_fifo.gcx.clkx_n_0 ,\\gntv_or_sync_fifo.gcx.clkx_n_1 ,\\gntv_or_sync_fifo.gcx.clkx_n_2 ,\\gntv_or_sync_fifo.gcx.clkx_n_3 }),\n .WR_PNTR_RD(p_22_out),\n .empty(empty),\n .\\gc0.count_d1_reg[7] (rd_pntr_plus1),\n .\\gnxpm_cdc.wr_pntr_bin_reg[10] (\\gntv_or_sync_fifo.gcx.clkx_n_17 ),\n .\\gnxpm_cdc.wr_pntr_bin_reg[9] ({\\gntv_or_sync_fifo.gcx.clkx_n_13 ,\\gntv_or_sync_fifo.gcx.clkx_n_14 ,\\gntv_or_sync_fifo.gcx.clkx_n_15 ,\\gntv_or_sync_fifo.gcx.clkx_n_16 }),\n .out(p_2_out),\n .prog_empty(prog_empty),\n .rd_clk(rd_clk),\n .rd_en(rd_en),\n .v1_reg(\\gras.rsts/c0/v1_reg ),\n .v1_reg_0(\\gras.rsts/c1/v1_reg ));\n fb_input_fifo_wr_logic \\gntv_or_sync_fifo.gl0.wr \n (.AR(wr_rst_i[1]),\n .\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram (p_12_out),\n .Q(p_13_out),\n .RD_PNTR_WR(p_23_out),\n .full(full),\n .\\gic0.gc0.count_d1_reg[10] (\\gntv_or_sync_fifo.gl0.wr_n_1 ),\n .\\gic0.gc0.count_d1_reg[10]_0 (wr_pntr_plus2),\n .\\gnxpm_cdc.rd_pntr_bin_reg[8] (\\gntv_or_sync_fifo.gcx.clkx_n_18 ),\n .\\gnxpm_cdc.rd_pntr_bin_reg[8]_0 (\\gntv_or_sync_fifo.gcx.clkx_n_27 ),\n .out(rst_full_ff_i),\n .wr_clk(wr_clk),\n .wr_en(wr_en),\n .wr_rst_busy(wr_rst_busy));\n fb_input_fifo_memory \\gntv_or_sync_fifo.mem \n (.Q(p_0_out_0),\n .din(din),\n .dout(dout),\n .\\gic0.gc0.count_d2_reg[10] (p_12_out),\n .out(rd_rst_i[0]),\n .ram_full_fb_i_reg(\\gntv_or_sync_fifo.gl0.wr_n_1 ),\n .rd_clk(rd_clk),\n .tmp_ram_rd_en(tmp_ram_rd_en),\n .wr_clk(wr_clk));\n fb_input_fifo_reset_blk_ramfifo rstblk\n (.\\gc0.count_reg[1] (rd_rst_i),\n .\\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_ff_i),\n .out(wr_rst_i),\n .ram_empty_fb_i_reg(p_2_out),\n .rd_clk(rd_clk),\n .rd_en(rd_en),\n .rst(rst),\n .tmp_ram_rd_en(tmp_ram_rd_en),\n .wr_clk(wr_clk),\n .wr_rst_busy(wr_rst_busy));\nendmodule\n\n(* ORIG_REF_NAME = \"fifo_generator_top\" *) \nmodule fb_input_fifo_fifo_generator_top\n (wr_rst_busy,\n dout,\n empty,\n full,\n prog_empty,\n rd_en,\n wr_en,\n rd_clk,\n wr_clk,\n din,\n rst);\n output wr_rst_busy;\n output [255:0]dout;\n output empty;\n output full;\n output prog_empty;\n input rd_en;\n input wr_en;\n input rd_clk;\n input wr_clk;\n input [63:0]din;\n input rst;\n\n wire [63:0]din;\n wire [255:0]dout;\n wire empty;\n wire full;\n wire prog_empty;\n wire rd_clk;\n wire rd_en;\n wire rst;\n wire wr_clk;\n wire wr_en;\n wire wr_rst_busy;\n\n fb_input_fifo_fifo_generator_ramfifo \\grf.rf \n (.din(din),\n .dout(dout),\n .empty(empty),\n .full(full),\n .prog_empty(prog_empty),\n .rd_clk(rd_clk),\n .rd_en(rd_en),\n .rst(rst),\n .wr_clk(wr_clk),\n .wr_en(wr_en),\n .wr_rst_busy(wr_rst_busy));\nendmodule\n\n(* C_ADD_NGC_CONSTRAINT = \"0\" *) (* C_APPLICATION_TYPE_AXIS = \"0\" *) (* C_APPLICATION_TYPE_RACH = \"0\" *) \n(* C_APPLICATION_TYPE_RDCH = \"0\" *) (* C_APPLICATION_TYPE_WACH = \"0\" *) (* C_APPLICATION_TYPE_WDCH = \"0\" *) \n(* C_APPLICATION_TYPE_WRCH = \"0\" *) (* C_AXIS_TDATA_WIDTH = \"8\" *) (* C_AXIS_TDEST_WIDTH = \"1\" *) \n(* C_AXIS_TID_WIDTH = \"1\" *) (* C_AXIS_TKEEP_WIDTH = \"1\" *) (* C_AXIS_TSTRB_WIDTH = \"1\" *) \n(* C_AXIS_TUSER_WIDTH = \"4\" *) (* C_AXIS_TYPE = \"0\" *) (* C_AXI_ADDR_WIDTH = \"32\" *) \n(* C_AXI_ARUSER_WIDTH = \"1\" *) (* C_AXI_AWUSER_WIDTH = \"1\" *) (* C_AXI_BUSER_WIDTH = \"1\" *) \n(* C_AXI_DATA_WIDTH = \"64\" *) (* C_AXI_ID_WIDTH = \"1\" *) (* C_AXI_LEN_WIDTH = \"8\" *) \n(* C_AXI_LOCK_WIDTH = \"1\" *) (* C_AXI_RUSER_WIDTH = \"1\" *) (* C_AXI_TYPE = \"1\" *) \n(* C_AXI_WUSER_WIDTH = \"1\" *) (* C_COMMON_CLOCK = \"0\" *) (* C_COUNT_TYPE = \"0\" *) \n(* C_DATA_COUNT_WIDTH = \"11\" *) (* C_DEFAULT_VALUE = \"BlankString\" *) (* C_DIN_WIDTH = \"64\" *) \n(* C_DIN_WIDTH_AXIS = \"1\" *) (* C_DIN_WIDTH_RACH = \"32\" *) (* C_DIN_WIDTH_RDCH = \"64\" *) \n(* C_DIN_WIDTH_WACH = \"1\" *) (* C_DIN_WIDTH_WDCH = \"64\" *) (* C_DIN_WIDTH_WRCH = \"2\" *) \n(* C_DOUT_RST_VAL = \"0\" *) (* C_DOUT_WIDTH = \"256\" *) (* C_ENABLE_RLOCS = \"0\" *) \n(* C_ENABLE_RST_SYNC = \"1\" *) (* C_EN_SAFETY_CKT = \"0\" *) (* C_ERROR_INJECTION_TYPE = \"0\" *) \n(* C_ERROR_INJECTION_TYPE_AXIS = \"0\" *) (* C_ERROR_INJECTION_TYPE_RACH = \"0\" *) (* C_ERROR_INJECTION_TYPE_RDCH = \"0\" *) \n(* C_ERROR_INJECTION_TYPE_WACH = \"0\" *) (* C_ERROR_INJECTION_TYPE_WDCH = \"0\" *) (* C_ERROR_INJECTION_TYPE_WRCH = \"0\" *) \n(* C_FAMILY = \"kintex7\" *) (* C_FULL_FLAGS_RST_VAL = \"1\" *) (* C_HAS_ALMOST_EMPTY = \"0\" *) \n(* C_HAS_ALMOST_FULL = \"0\" *) (* C_HAS_AXIS_TDATA = \"1\" *) (* C_HAS_AXIS_TDEST = \"0\" *) \n(* C_HAS_AXIS_TID = \"0\" *) (* C_HAS_AXIS_TKEEP = \"0\" *) (* C_HAS_AXIS_TLAST = \"0\" *) \n(* C_HAS_AXIS_TREADY = \"1\" *) (* C_HAS_AXIS_TSTRB = \"0\" *) (* C_HAS_AXIS_TUSER = \"1\" *) \n(* C_HAS_AXI_ARUSER = \"0\" *) (* C_HAS_AXI_AWUSER = \"0\" *) (* C_HAS_AXI_BUSER = \"0\" *) \n(* C_HAS_AXI_ID = \"0\" *) (* C_HAS_AXI_RD_CHANNEL = \"1\" *) (* C_HAS_AXI_RUSER = \"0\" *) \n(* C_HAS_AXI_WR_CHANNEL = \"1\" *) (* C_HAS_AXI_WUSER = \"0\" *) (* C_HAS_BACKUP = \"0\" *) \n(* C_HAS_DATA_COUNT = \"0\" *) (* C_HAS_DATA_COUNTS_AXIS = \"0\" *) (* C_HAS_DATA_COUNTS_RACH = \"0\" *) \n(* C_HAS_DATA_COUNTS_RDCH = \"0\" *) (* C_HAS_DATA_COUNTS_WACH = \"0\" *) (* C_HAS_DATA_COUNTS_WDCH = \"0\" *) \n(* C_HAS_DATA_COUNTS_WRCH = \"0\" *) (* C_HAS_INT_CLK = \"0\" *) (* C_HAS_MASTER_CE = \"0\" *) \n(* C_HAS_MEMINIT_FILE = \"0\" *) (* C_HAS_OVERFLOW = \"0\" *) (* C_HAS_PROG_FLAGS_AXIS = \"0\" *) \n(* C_HAS_PROG_FLAGS_RACH = \"0\" *) (* C_HAS_PROG_FLAGS_RDCH = \"0\" *) (* C_HAS_PROG_FLAGS_WACH = \"0\" *) \n(* C_HAS_PROG_FLAGS_WDCH = \"0\" *) (* C_HAS_PROG_FLAGS_WRCH = \"0\" *) (* C_HAS_RD_DATA_COUNT = \"0\" *) \n(* C_HAS_RD_RST = \"0\" *) (* C_HAS_RST = \"1\" *) (* C_HAS_SLAVE_CE = \"0\" *) \n(* C_HAS_SRST = \"0\" *) (* C_HAS_UNDERFLOW = \"0\" *) (* C_HAS_VALID = \"0\" *) \n(* C_HAS_WR_ACK = \"0\" *) (* C_HAS_WR_DATA_COUNT = \"0\" *) (* C_HAS_WR_RST = \"0\" *) \n(* C_IMPLEMENTATION_TYPE = \"2\" *) (* C_IMPLEMENTATION_TYPE_AXIS = \"1\" *) (* C_IMPLEMENTATION_TYPE_RACH = \"1\" *) \n(* C_IMPLEMENTATION_TYPE_RDCH = \"1\" *) (* C_IMPLEMENTATION_TYPE_WACH = \"1\" *) (* C_IMPLEMENTATION_TYPE_WDCH = \"1\" *) \n(* C_IMPLEMENTATION_TYPE_WRCH = \"1\" *) (* C_INIT_WR_PNTR_VAL = \"0\" *) (* C_INTERFACE_TYPE = \"0\" *) \n(* C_MEMORY_TYPE = \"1\" *) (* C_MIF_FILE_NAME = \"BlankString\" *) (* C_MSGON_VAL = \"1\" *) \n(* C_OPTIMIZATION_MODE = \"0\" *) (* C_OVERFLOW_LOW = \"0\" *) (* C_POWER_SAVING_MODE = \"0\" *) \n(* C_PRELOAD_LATENCY = \"1\" *) (* C_PRELOAD_REGS = \"0\" *) (* C_PRIM_FIFO_TYPE = \"2kx18\" *) \n(* C_PRIM_FIFO_TYPE_AXIS = \"1kx18\" *) (* C_PRIM_FIFO_TYPE_RACH = \"512x36\" *) (* C_PRIM_FIFO_TYPE_RDCH = \"1kx36\" *) \n(* C_PRIM_FIFO_TYPE_WACH = \"512x36\" *) (* C_PRIM_FIFO_TYPE_WDCH = \"1kx36\" *) (* C_PRIM_FIFO_TYPE_WRCH = \"512x36\" *) \n(* C_PROG_EMPTY_THRESH_ASSERT_VAL = \"15\" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = \"1022\" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = \"1022\" *) \n(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = \"1022\" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = \"1022\" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = \"1022\" *) \n(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = \"1022\" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = \"16\" *) (* C_PROG_EMPTY_TYPE = \"1\" *) \n(* C_PROG_EMPTY_TYPE_AXIS = \"0\" *) (* C_PROG_EMPTY_TYPE_RACH = \"0\" *) (* C_PROG_EMPTY_TYPE_RDCH = \"0\" *) \n(* C_PROG_EMPTY_TYPE_WACH = \"0\" *) (* C_PROG_EMPTY_TYPE_WDCH = \"0\" *) (* C_PROG_EMPTY_TYPE_WRCH = \"0\" *) \n(* C_PROG_FULL_THRESH_ASSERT_VAL = \"2045\" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = \"1023\" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = \"1023\" *) \n(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = \"1023\" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = \"1023\" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = \"1023\" *) \n(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = \"1023\" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = \"2044\" *) (* C_PROG_FULL_TYPE = \"0\" *) \n(* C_PROG_FULL_TYPE_AXIS = \"0\" *) (* C_PROG_FULL_TYPE_RACH = \"0\" *) (* C_PROG_FULL_TYPE_RDCH = \"0\" *) \n(* C_PROG_FULL_TYPE_WACH = \"0\" *) (* C_PROG_FULL_TYPE_WDCH = \"0\" *) (* C_PROG_FULL_TYPE_WRCH = \"0\" *) \n(* C_RACH_TYPE = \"0\" *) (* C_RDCH_TYPE = \"0\" *) (* C_RD_DATA_COUNT_WIDTH = \"9\" *) \n(* C_RD_DEPTH = \"512\" *) (* C_RD_FREQ = \"1\" *) (* C_RD_PNTR_WIDTH = \"9\" *) \n(* C_REG_SLICE_MODE_AXIS = \"0\" *) (* C_REG_SLICE_MODE_RACH = \"0\" *) (* C_REG_SLICE_MODE_RDCH = \"0\" *) \n(* C_REG_SLICE_MODE_WACH = \"0\" *) (* C_REG_SLICE_MODE_WDCH = \"0\" *) (* C_REG_SLICE_MODE_WRCH = \"0\" *) \n(* C_SELECT_XPM = \"0\" *) (* C_SYNCHRONIZER_STAGE = \"2\" *) (* C_UNDERFLOW_LOW = \"0\" *) \n(* C_USE_COMMON_OVERFLOW = \"0\" *) (* C_USE_COMMON_UNDERFLOW = \"0\" *) (* C_USE_DEFAULT_SETTINGS = \"0\" *) \n(* C_USE_DOUT_RST = \"1\" *) (* C_USE_ECC = \"0\" *) (* C_USE_ECC_AXIS = \"0\" *) \n(* C_USE_ECC_RACH = \"0\" *) (* C_USE_ECC_RDCH = \"0\" *) (* C_USE_ECC_WACH = \"0\" *) \n(* C_USE_ECC_WDCH = \"0\" *) (* C_USE_ECC_WRCH = \"0\" *) (* C_USE_EMBEDDED_REG = \"0\" *) \n(* C_USE_FIFO16_FLAGS = \"0\" *) (* C_USE_FWFT_DATA_COUNT = \"0\" *) (* C_USE_PIPELINE_REG = \"0\" *) \n(* C_VALID_LOW = \"0\" *) (* C_WACH_TYPE = \"0\" *) (* C_WDCH_TYPE = \"0\" *) \n(* C_WRCH_TYPE = \"0\" *) (* C_WR_ACK_LOW = \"0\" *) (* C_WR_DATA_COUNT_WIDTH = \"11\" *) \n(* C_WR_DEPTH = \"2048\" *) (* C_WR_DEPTH_AXIS = \"1024\" *) (* C_WR_DEPTH_RACH = \"16\" *) \n(* C_WR_DEPTH_RDCH = \"1024\" *) (* C_WR_DEPTH_WACH = \"16\" *) (* C_WR_DEPTH_WDCH = \"1024\" *) \n(* C_WR_DEPTH_WRCH = \"16\" *) (* C_WR_FREQ = \"1\" *) (* C_WR_PNTR_WIDTH = \"11\" *) \n(* C_WR_PNTR_WIDTH_AXIS = \"10\" *) (* C_WR_PNTR_WIDTH_RACH = \"4\" *) (* C_WR_PNTR_WIDTH_RDCH = \"10\" *) \n(* C_WR_PNTR_WIDTH_WACH = \"4\" *) (* C_WR_PNTR_WIDTH_WDCH = \"10\" *) (* C_WR_PNTR_WIDTH_WRCH = \"4\" *) \n(* C_WR_RESPONSE_LATENCY = \"1\" *) (* ORIG_REF_NAME = \"fifo_generator_v13_1_2\" *) \nmodule fb_input_fifo_fifo_generator_v13_1_2\n (backup,\n backup_marker,\n clk,\n rst,\n srst,\n wr_clk,\n wr_rst,\n rd_clk,\n rd_rst,\n din,\n wr_en,\n rd_en,\n prog_empty_thresh,\n prog_empty_thresh_assert,\n prog_empty_thresh_negate,\n prog_full_thresh,\n prog_full_thresh_assert,\n prog_full_thresh_negate,\n int_clk,\n injectdbiterr,\n injectsbiterr,\n sleep,\n dout,\n full,\n almost_full,\n wr_ack,\n overflow,\n empty,\n almost_empty,\n valid,\n underflow,\n data_count,\n rd_data_count,\n wr_data_count,\n prog_full,\n prog_empty,\n sbiterr,\n dbiterr,\n wr_rst_busy,\n rd_rst_busy,\n m_aclk,\n s_aclk,\n s_aresetn,\n m_aclk_en,\n s_aclk_en,\n s_axi_awid,\n s_axi_awaddr,\n s_axi_awlen,\n s_axi_awsize,\n s_axi_awburst,\n s_axi_awlock,\n s_axi_awcache,\n s_axi_awprot,\n s_axi_awqos,\n s_axi_awregion,\n s_axi_awuser,\n s_axi_awvalid,\n s_axi_awready,\n s_axi_wid,\n s_axi_wdata,\n s_axi_wstrb,\n s_axi_wlast,\n s_axi_wuser,\n s_axi_wvalid,\n s_axi_wready,\n s_axi_bid,\n s_axi_bresp,\n s_axi_buser,\n s_axi_bvalid,\n s_axi_bready,\n m_axi_awid,\n m_axi_awaddr,\n m_axi_awlen,\n m_axi_awsize,\n m_axi_awburst,\n m_axi_awlock,\n m_axi_awcache,\n m_axi_awprot,\n m_axi_awqos,\n m_axi_awregion,\n m_axi_awuser,\n m_axi_awvalid,\n m_axi_awready,\n m_axi_wid,\n m_axi_wdata,\n m_axi_wstrb,\n m_axi_wlast,\n m_axi_wuser,\n m_axi_wvalid,\n m_axi_wready,\n m_axi_bid,\n m_axi_bresp,\n m_axi_buser,\n m_axi_bvalid,\n m_axi_bready,\n s_axi_arid,\n s_axi_araddr,\n s_axi_arlen,\n s_axi_arsize,\n s_axi_arburst,\n s_axi_arlock,\n s_axi_arcache,\n s_axi_arprot,\n s_axi_arqos,\n s_axi_arregion,\n s_axi_aruser,\n s_axi_arvalid,\n s_axi_arready,\n s_axi_rid,\n s_axi_rdata,\n s_axi_rresp,\n s_axi_rlast,\n s_axi_ruser,\n s_axi_rvalid,\n s_axi_rready,\n m_axi_arid,\n m_axi_araddr,\n m_axi_arlen,\n m_axi_arsize,\n m_axi_arburst,\n m_axi_arlock,\n m_axi_arcache,\n m_axi_arprot,\n m_axi_arqos,\n m_axi_arregion,\n m_axi_aruser,\n m_axi_arvalid,\n m_axi_arready,\n m_axi_rid,\n m_axi_rdata,\n m_axi_rresp,\n m_axi_rlast,\n m_axi_ruser,\n m_axi_rvalid,\n m_axi_rready,\n s_axis_tvalid,\n s_axis_tready,\n s_axis_tdata,\n s_axis_tstrb,\n s_axis_tkeep,\n s_axis_tlast,\n s_axis_tid,\n s_axis_tdest,\n s_axis_tuser,\n m_axis_tvalid,\n m_axis_tready,\n m_axis_tdata,\n m_axis_tstrb,\n m_axis_tkeep,\n m_axis_tlast,\n m_axis_tid,\n m_axis_tdest,\n m_axis_tuser,\n axi_aw_injectsbiterr,\n axi_aw_injectdbiterr,\n axi_aw_prog_full_thresh,\n axi_aw_prog_empty_thresh,\n axi_aw_data_count,\n axi_aw_wr_data_count,\n axi_aw_rd_data_count,\n axi_aw_sbiterr,\n axi_aw_dbiterr,\n axi_aw_overflow,\n axi_aw_underflow,\n axi_aw_prog_full,\n axi_aw_prog_empty,\n axi_w_injectsbiterr,\n axi_w_injectdbiterr,\n axi_w_prog_full_thresh,\n axi_w_prog_empty_thresh,\n axi_w_data_count,\n axi_w_wr_data_count,\n axi_w_rd_data_count,\n axi_w_sbiterr,\n axi_w_dbiterr,\n axi_w_overflow,\n axi_w_underflow,\n axi_w_prog_full,\n axi_w_prog_empty,\n axi_b_injectsbiterr,\n axi_b_injectdbiterr,\n axi_b_prog_full_thresh,\n axi_b_prog_empty_thresh,\n axi_b_data_count,\n axi_b_wr_data_count,\n axi_b_rd_data_count,\n axi_b_sbiterr,\n axi_b_dbiterr,\n axi_b_overflow,\n axi_b_underflow,\n axi_b_prog_full,\n axi_b_prog_empty,\n axi_ar_injectsbiterr,\n axi_ar_injectdbiterr,\n axi_ar_prog_full_thresh,\n axi_ar_prog_empty_thresh,\n axi_ar_data_count,\n axi_ar_wr_data_count,\n axi_ar_rd_data_count,\n axi_ar_sbiterr,\n axi_ar_dbiterr,\n axi_ar_overflow,\n axi_ar_underflow,\n axi_ar_prog_full,\n axi_ar_prog_empty,\n axi_r_injectsbiterr,\n axi_r_injectdbiterr,\n axi_r_prog_full_thresh,\n axi_r_prog_empty_thresh,\n axi_r_data_count,\n axi_r_wr_data_count,\n axi_r_rd_data_count,\n axi_r_sbiterr,\n axi_r_dbiterr,\n axi_r_overflow,\n axi_r_underflow,\n axi_r_prog_full,\n axi_r_prog_empty,\n axis_injectsbiterr,\n axis_injectdbiterr,\n axis_prog_full_thresh,\n axis_prog_empty_thresh,\n axis_data_count,\n axis_wr_data_count,\n axis_rd_data_count,\n axis_sbiterr,\n axis_dbiterr,\n axis_overflow,\n axis_underflow,\n axis_prog_full,\n axis_prog_empty);\n input backup;\n input backup_marker;\n input clk;\n input rst;\n input srst;\n input wr_clk;\n input wr_rst;\n input rd_clk;\n input rd_rst;\n input [63:0]din;\n input wr_en;\n input rd_en;\n input [8:0]prog_empty_thresh;\n input [8:0]prog_empty_thresh_assert;\n input [8:0]prog_empty_thresh_negate;\n input [10:0]prog_full_thresh;\n input [10:0]prog_full_thresh_assert;\n input [10:0]prog_full_thresh_negate;\n input int_clk;\n input injectdbiterr;\n input injectsbiterr;\n input sleep;\n output [255:0]dout;\n output full;\n output almost_full;\n output wr_ack;\n output overflow;\n output empty;\n output almost_empty;\n output valid;\n output underflow;\n output [10:0]data_count;\n output [8:0]rd_data_count;\n output [10:0]wr_data_count;\n output prog_full;\n output prog_empty;\n output sbiterr;\n output dbiterr;\n output wr_rst_busy;\n output rd_rst_busy;\n input m_aclk;\n input s_aclk;\n input s_aresetn;\n input m_aclk_en;\n input s_aclk_en;\n input [0:0]s_axi_awid;\n input [31:0]s_axi_awaddr;\n input [7:0]s_axi_awlen;\n input [2:0]s_axi_awsize;\n input [1:0]s_axi_awburst;\n input [0:0]s_axi_awlock;\n input [3:0]s_axi_awcache;\n input [2:0]s_axi_awprot;\n input [3:0]s_axi_awqos;\n input [3:0]s_axi_awregion;\n input [0:0]s_axi_awuser;\n input s_axi_awvalid;\n output s_axi_awready;\n input [0:0]s_axi_wid;\n input [63:0]s_axi_wdata;\n input [7:0]s_axi_wstrb;\n input s_axi_wlast;\n input [0:0]s_axi_wuser;\n input s_axi_wvalid;\n output s_axi_wready;\n output [0:0]s_axi_bid;\n output [1:0]s_axi_bresp;\n output [0:0]s_axi_buser;\n output s_axi_bvalid;\n input s_axi_bready;\n output [0:0]m_axi_awid;\n output [31:0]m_axi_awaddr;\n output [7:0]m_axi_awlen;\n output [2:0]m_axi_awsize;\n output [1:0]m_axi_awburst;\n output [0:0]m_axi_awlock;\n output [3:0]m_axi_awcache;\n output [2:0]m_axi_awprot;\n output [3:0]m_axi_awqos;\n output [3:0]m_axi_awregion;\n output [0:0]m_axi_awuser;\n output m_axi_awvalid;\n input m_axi_awready;\n output [0:0]m_axi_wid;\n output [63:0]m_axi_wdata;\n output [7:0]m_axi_wstrb;\n output m_axi_wlast;\n output [0:0]m_axi_wuser;\n output m_axi_wvalid;\n input m_axi_wready;\n input [0:0]m_axi_bid;\n input [1:0]m_axi_bresp;\n input [0:0]m_axi_buser;\n input m_axi_bvalid;\n output m_axi_bready;\n input [0:0]s_axi_arid;\n input [31:0]s_axi_araddr;\n input [7:0]s_axi_arlen;\n input [2:0]s_axi_arsize;\n input [1:0]s_axi_arburst;\n input [0:0]s_axi_arlock;\n input [3:0]s_axi_arcache;\n input [2:0]s_axi_arprot;\n input [3:0]s_axi_arqos;\n input [3:0]s_axi_arregion;\n input [0:0]s_axi_aruser;\n input s_axi_arvalid;\n output s_axi_arready;\n output [0:0]s_axi_rid;\n output [63:0]s_axi_rdata;\n output [1:0]s_axi_rresp;\n output s_axi_rlast;\n output [0:0]s_axi_ruser;\n output s_axi_rvalid;\n input s_axi_rready;\n output [0:0]m_axi_arid;\n output [31:0]m_axi_araddr;\n output [7:0]m_axi_arlen;\n output [2:0]m_axi_arsize;\n output [1:0]m_axi_arburst;\n output [0:0]m_axi_arlock;\n output [3:0]m_axi_arcache;\n output [2:0]m_axi_arprot;\n output [3:0]m_axi_arqos;\n output [3:0]m_axi_arregion;\n output [0:0]m_axi_aruser;\n output m_axi_arvalid;\n input m_axi_arready;\n input [0:0]m_axi_rid;\n input [63:0]m_axi_rdata;\n input [1:0]m_axi_rresp;\n input m_axi_rlast;\n input [0:0]m_axi_ruser;\n input m_axi_rvalid;\n output m_axi_rready;\n input s_axis_tvalid;\n output s_axis_tready;\n input [7:0]s_axis_tdata;\n input [0:0]s_axis_tstrb;\n input [0:0]s_axis_tkeep;\n input s_axis_tlast;\n input [0:0]s_axis_tid;\n input [0:0]s_axis_tdest;\n input [3:0]s_axis_tuser;\n output m_axis_tvalid;\n input m_axis_tready;\n output [7:0]m_axis_tdata;\n output [0:0]m_axis_tstrb;\n output [0:0]m_axis_tkeep;\n output m_axis_tlast;\n output [0:0]m_axis_tid;\n output [0:0]m_axis_tdest;\n output [3:0]m_axis_tuser;\n input axi_aw_injectsbiterr;\n input axi_aw_injectdbiterr;\n input [3:0]axi_aw_prog_full_thresh;\n input [3:0]axi_aw_prog_empty_thresh;\n output [4:0]axi_aw_data_count;\n output [4:0]axi_aw_wr_data_count;\n output [4:0]axi_aw_rd_data_count;\n output axi_aw_sbiterr;\n output axi_aw_dbiterr;\n output axi_aw_overflow;\n output axi_aw_underflow;\n output axi_aw_prog_full;\n output axi_aw_prog_empty;\n input axi_w_injectsbiterr;\n input axi_w_injectdbiterr;\n input [9:0]axi_w_prog_full_thresh;\n input [9:0]axi_w_prog_empty_thresh;\n output [10:0]axi_w_data_count;\n output [10:0]axi_w_wr_data_count;\n output [10:0]axi_w_rd_data_count;\n output axi_w_sbiterr;\n output axi_w_dbiterr;\n output axi_w_overflow;\n output axi_w_underflow;\n output axi_w_prog_full;\n output axi_w_prog_empty;\n input axi_b_injectsbiterr;\n input axi_b_injectdbiterr;\n input [3:0]axi_b_prog_full_thresh;\n input [3:0]axi_b_prog_empty_thresh;\n output [4:0]axi_b_data_count;\n output [4:0]axi_b_wr_data_count;\n output [4:0]axi_b_rd_data_count;\n output axi_b_sbiterr;\n output axi_b_dbiterr;\n output axi_b_overflow;\n output axi_b_underflow;\n output axi_b_prog_full;\n output axi_b_prog_empty;\n input axi_ar_injectsbiterr;\n input axi_ar_injectdbiterr;\n input [3:0]axi_ar_prog_full_thresh;\n input [3:0]axi_ar_prog_empty_thresh;\n output [4:0]axi_ar_data_count;\n output [4:0]axi_ar_wr_data_count;\n output [4:0]axi_ar_rd_data_count;\n output axi_ar_sbiterr;\n output axi_ar_dbiterr;\n output axi_ar_overflow;\n output axi_ar_underflow;\n output axi_ar_prog_full;\n output axi_ar_prog_empty;\n input axi_r_injectsbiterr;\n input axi_r_injectdbiterr;\n input [9:0]axi_r_prog_full_thresh;\n input [9:0]axi_r_prog_empty_thresh;\n output [10:0]axi_r_data_count;\n output [10:0]axi_r_wr_data_count;\n output [10:0]axi_r_rd_data_count;\n output axi_r_sbiterr;\n output axi_r_dbiterr;\n output axi_r_overflow;\n output axi_r_underflow;\n output axi_r_prog_full;\n output axi_r_prog_empty;\n input axis_injectsbiterr;\n input axis_injectdbiterr;\n input [9:0]axis_prog_full_thresh;\n input [9:0]axis_prog_empty_thresh;\n output [10:0]axis_data_count;\n output [10:0]axis_wr_data_count;\n output [10:0]axis_rd_data_count;\n output axis_sbiterr;\n output axis_dbiterr;\n output axis_overflow;\n output axis_underflow;\n output axis_prog_full;\n output axis_prog_empty;\n\n wire \\ ;\n wire \\ ;\n wire [63:0]din;\n wire [255:0]dout;\n wire empty;\n wire full;\n wire prog_empty;\n wire rd_clk;\n wire rd_en;\n wire rst;\n wire wr_clk;\n wire wr_en;\n wire wr_rst_busy;\n\n assign almost_empty = \\ ;\n assign almost_full = \\ ;\n assign axi_ar_data_count[4] = \\ ;\n assign axi_ar_data_count[3] = \\ ;\n assign axi_ar_data_count[2] = \\ ;\n assign axi_ar_data_count[1] = \\ ;\n assign axi_ar_data_count[0] = \\ ;\n assign axi_ar_dbiterr = \\ ;\n assign axi_ar_overflow = \\ ;\n assign axi_ar_prog_empty = \\ ;\n assign axi_ar_prog_full = \\ ;\n assign axi_ar_rd_data_count[4] = \\ ;\n assign axi_ar_rd_data_count[3] = \\ ;\n assign axi_ar_rd_data_count[2] = \\ ;\n assign axi_ar_rd_data_count[1] = \\ ;\n assign axi_ar_rd_data_count[0] = \\ ;\n assign axi_ar_sbiterr = \\ ;\n assign axi_ar_underflow = \\ ;\n assign axi_ar_wr_data_count[4] = \\ ;\n assign axi_ar_wr_data_count[3] = \\ ;\n assign axi_ar_wr_data_count[2] = \\ ;\n assign axi_ar_wr_data_count[1] = \\ ;\n assign axi_ar_wr_data_count[0] = \\ ;\n assign axi_aw_data_count[4] = \\ ;\n assign axi_aw_data_count[3] = \\ ;\n assign axi_aw_data_count[2] = \\ ;\n assign axi_aw_data_count[1] = \\ ;\n assign axi_aw_data_count[0] = \\ ;\n assign axi_aw_dbiterr = \\ ;\n assign axi_aw_overflow = \\ ;\n assign axi_aw_prog_empty = \\ ;\n assign axi_aw_prog_full = \\ ;\n assign axi_aw_rd_data_count[4] = \\ ;\n assign axi_aw_rd_data_count[3] = \\ ;\n assign axi_aw_rd_data_count[2] = \\ ;\n assign axi_aw_rd_data_count[1] = \\ ;\n assign axi_aw_rd_data_count[0] = \\ ;\n assign axi_aw_sbiterr = \\ ;\n assign axi_aw_underflow = \\ ;\n assign axi_aw_wr_data_count[4] = \\ ;\n assign axi_aw_wr_data_count[3] = \\ ;\n assign axi_aw_wr_data_count[2] = \\ ;\n assign axi_aw_wr_data_count[1] = \\ ;\n assign axi_aw_wr_data_count[0] = \\ ;\n assign axi_b_data_count[4] = \\ ;\n assign axi_b_data_count[3] = \\ ;\n assign axi_b_data_count[2] = \\ ;\n assign axi_b_data_count[1] = \\ ;\n assign axi_b_data_count[0] = \\ ;\n assign axi_b_dbiterr = \\ ;\n assign axi_b_overflow = \\ ;\n assign axi_b_prog_empty = \\ ;\n assign axi_b_prog_full = \\ ;\n assign axi_b_rd_data_count[4] = \\ ;\n assign axi_b_rd_data_count[3] = \\ ;\n assign axi_b_rd_data_count[2] = \\ ;\n assign axi_b_rd_data_count[1] = \\ ;\n assign axi_b_rd_data_count[0] = \\ ;\n assign axi_b_sbiterr = \\ ;\n assign axi_b_underflow = \\ ;\n assign axi_b_wr_data_count[4] = \\ ;\n assign axi_b_wr_data_count[3] = \\ ;\n assign axi_b_wr_data_count[2] = \\ ;\n assign axi_b_wr_data_count[1] = \\ ;\n assign axi_b_wr_data_count[0] = \\ ;\n assign axi_r_data_count[10] = \\ ;\n assign axi_r_data_count[9] = \\ ;\n assign axi_r_data_count[8] = \\ ;\n assign axi_r_data_count[7] = \\ ;\n assign axi_r_data_count[6] = \\ ;\n assign axi_r_data_count[5] = \\ ;\n assign axi_r_data_count[4] = \\ ;\n assign axi_r_data_count[3] = \\ ;\n assign axi_r_data_count[2] = \\ ;\n assign axi_r_data_count[1] = \\ ;\n assign axi_r_data_count[0] = \\ ;\n assign axi_r_dbiterr = \\ ;\n assign axi_r_overflow = \\ ;\n assign axi_r_prog_empty = \\ ;\n assign axi_r_prog_full = \\ ;\n assign axi_r_rd_data_count[10] = \\ ;\n assign axi_r_rd_data_count[9] = \\ ;\n assign axi_r_rd_data_count[8] = \\ ;\n assign axi_r_rd_data_count[7] = \\ ;\n assign axi_r_rd_data_count[6] = \\ ;\n assign axi_r_rd_data_count[5] = \\ ;\n assign axi_r_rd_data_count[4] = \\ ;\n assign axi_r_rd_data_count[3] = \\ ;\n assign axi_r_rd_data_count[2] = \\ ;\n assign axi_r_rd_data_count[1] = \\ ;\n assign axi_r_rd_data_count[0] = \\ ;\n assign axi_r_sbiterr = \\ ;\n assign axi_r_underflow = \\ ;\n assign axi_r_wr_data_count[10] = \\ ;\n assign axi_r_wr_data_count[9] = \\ ;\n assign axi_r_wr_data_count[8] = \\ ;\n assign axi_r_wr_data_count[7] = \\ ;\n assign axi_r_wr_data_count[6] = \\ ;\n assign axi_r_wr_data_count[5] = \\ ;\n assign axi_r_wr_data_count[4] = \\ ;\n assign axi_r_wr_data_count[3] = \\ ;\n assign axi_r_wr_data_count[2] = \\ ;\n assign axi_r_wr_data_count[1] = \\ ;\n assign axi_r_wr_data_count[0] = \\ ;\n assign axi_w_data_count[10] = \\ ;\n assign axi_w_data_count[9] = \\ ;\n assign axi_w_data_count[8] = \\ ;\n assign axi_w_data_count[7] = \\ ;\n assign axi_w_data_count[6] = \\ ;\n assign axi_w_data_count[5] = \\ ;\n assign axi_w_data_count[4] = \\ ;\n assign axi_w_data_count[3] = \\ ;\n assign axi_w_data_count[2] = \\ ;\n assign axi_w_data_count[1] = \\ ;\n assign axi_w_data_count[0] = \\ ;\n assign axi_w_dbiterr = \\ ;\n assign axi_w_overflow = \\ ;\n assign axi_w_prog_empty = \\ ;\n assign axi_w_prog_full = \\ ;\n assign axi_w_rd_data_count[10] = \\ ;\n assign axi_w_rd_data_count[9] = \\ ;\n assign axi_w_rd_data_count[8] = \\ ;\n assign axi_w_rd_data_count[7] = \\ ;\n assign axi_w_rd_data_count[6] = \\ ;\n assign axi_w_rd_data_count[5] = \\ ;\n assign axi_w_rd_data_count[4] = \\ ;\n assign axi_w_rd_data_count[3] = \\ ;\n assign axi_w_rd_data_count[2] = \\ ;\n assign axi_w_rd_data_count[1] = \\ ;\n assign axi_w_rd_data_count[0] = \\ ;\n assign axi_w_sbiterr = \\ ;\n assign axi_w_underflow = \\ ;\n assign axi_w_wr_data_count[10] = \\ ;\n assign axi_w_wr_data_count[9] = \\ ;\n assign axi_w_wr_data_count[8] = \\ ;\n assign axi_w_wr_data_count[7] = \\ ;\n assign axi_w_wr_data_count[6] = \\ ;\n assign axi_w_wr_data_count[5] = \\ ;\n assign axi_w_wr_data_count[4] = \\ ;\n assign axi_w_wr_data_count[3] = \\ ;\n assign axi_w_wr_data_count[2] = \\ ;\n assign axi_w_wr_data_count[1] = \\ ;\n assign axi_w_wr_data_count[0] = \\ ;\n assign axis_data_count[10] = \\ ;\n assign axis_data_count[9] = \\ ;\n assign axis_data_count[8] = \\ ;\n assign axis_data_count[7] = \\ ;\n assign axis_data_count[6] = \\ ;\n assign axis_data_count[5] = \\ ;\n assign axis_data_count[4] = \\ ;\n assign axis_data_count[3] = \\ ;\n assign axis_data_count[2] = \\ ;\n assign axis_data_count[1] = \\ ;\n assign axis_data_count[0] = \\ ;\n assign axis_dbiterr = \\ ;\n assign axis_overflow = \\ ;\n assign axis_prog_empty = \\ ;\n assign axis_prog_full = \\ ;\n assign axis_rd_data_count[10] = \\ ;\n assign axis_rd_data_count[9] = \\ ;\n assign axis_rd_data_count[8] = \\ ;\n assign axis_rd_data_count[7] = \\ ;\n assign axis_rd_data_count[6] = \\ ;\n assign axis_rd_data_count[5] = \\ ;\n assign axis_rd_data_count[4] = \\ ;\n assign axis_rd_data_count[3] = \\ ;\n assign axis_rd_data_count[2] = \\ ;\n assign axis_rd_data_count[1] = \\ ;\n assign axis_rd_data_count[0] = \\ ;\n assign axis_sbiterr = \\ ;\n assign axis_underflow = \\ ;\n assign axis_wr_data_count[10] = \\ ;\n assign axis_wr_data_count[9] = \\ ;\n assign axis_wr_data_count[8] = \\ ;\n assign axis_wr_data_count[7] = \\ ;\n assign axis_wr_data_count[6] = \\ ;\n assign axis_wr_data_count[5] = \\ ;\n assign axis_wr_data_count[4] = \\ ;\n assign axis_wr_data_count[3] = \\ ;\n assign axis_wr_data_count[2] = \\ ;\n assign axis_wr_data_count[1] = \\ ;\n assign axis_wr_data_count[0] = \\ ;\n assign data_count[10] = \\ ;\n assign data_count[9] = \\ ;\n assign data_count[8] = \\ ;\n assign data_count[7] = \\ ;\n assign data_count[6] = \\ ;\n assign data_count[5] = \\ ;\n assign data_count[4] = \\ ;\n assign data_count[3] = \\ ;\n assign data_count[2] = \\ ;\n assign data_count[1] = \\ ;\n assign data_count[0] = \\ ;\n assign dbiterr = \\ ;\n assign m_axi_araddr[31] = \\ ;\n assign m_axi_araddr[30] = \\ ;\n assign m_axi_araddr[29] = \\ ;\n assign m_axi_araddr[28] = \\ ;\n assign m_axi_araddr[27] = \\ ;\n assign m_axi_araddr[26] = \\ ;\n assign m_axi_araddr[25] = \\ ;\n assign m_axi_araddr[24] = \\ ;\n assign m_axi_araddr[23] = \\ ;\n assign m_axi_araddr[22] = \\ ;\n assign m_axi_araddr[21] = \\ ;\n assign m_axi_araddr[20] = \\ ;\n assign m_axi_araddr[19] = \\ ;\n assign m_axi_araddr[18] = \\ ;\n assign m_axi_araddr[17] = \\ ;\n assign m_axi_araddr[16] = \\ ;\n assign m_axi_araddr[15] = \\ ;\n assign m_axi_araddr[14] = \\ ;\n assign m_axi_araddr[13] = \\ ;\n assign m_axi_araddr[12] = \\ ;\n assign m_axi_araddr[11] = \\ ;\n assign m_axi_araddr[10] = \\ ;\n assign m_axi_araddr[9] = \\ ;\n assign m_axi_araddr[8] = \\ ;\n assign m_axi_araddr[7] = \\ ;\n assign m_axi_araddr[6] = \\ ;\n assign m_axi_araddr[5] = \\ ;\n assign m_axi_araddr[4] = \\ ;\n assign m_axi_araddr[3] = \\ ;\n assign m_axi_araddr[2] = \\ ;\n assign m_axi_araddr[1] = \\ ;\n assign m_axi_araddr[0] = \\ ;\n assign m_axi_arburst[1] = \\ ;\n assign m_axi_arburst[0] = \\ ;\n assign m_axi_arcache[3] = \\ ;\n assign m_axi_arcache[2] = \\ ;\n assign m_axi_arcache[1] = \\ ;\n assign m_axi_arcache[0] = \\ ;\n assign m_axi_arid[0] = \\ ;\n assign m_axi_arlen[7] = \\ ;\n assign m_axi_arlen[6] = \\ ;\n assign m_axi_arlen[5] = \\ ;\n assign m_axi_arlen[4] = \\ ;\n assign m_axi_arlen[3] = \\ ;\n assign m_axi_arlen[2] = \\ ;\n assign m_axi_arlen[1] = \\ ;\n assign m_axi_arlen[0] = \\ ;\n assign m_axi_arlock[0] = \\ ;\n assign m_axi_arprot[2] = \\ ;\n assign m_axi_arprot[1] = \\ ;\n assign m_axi_arprot[0] = \\ ;\n assign m_axi_arqos[3] = \\ ;\n assign m_axi_arqos[2] = \\ ;\n assign m_axi_arqos[1] = \\ ;\n assign m_axi_arqos[0] = \\ ;\n assign m_axi_arregion[3] = \\ ;\n assign m_axi_arregion[2] = \\ ;\n assign m_axi_arregion[1] = \\ ;\n assign m_axi_arregion[0] = \\ ;\n assign m_axi_arsize[2] = \\ ;\n assign m_axi_arsize[1] = \\ ;\n assign m_axi_arsize[0] = \\ ;\n assign m_axi_aruser[0] = \\ ;\n assign m_axi_arvalid = \\ ;\n assign m_axi_awaddr[31] = \\ ;\n assign m_axi_awaddr[30] = \\ ;\n assign m_axi_awaddr[29] = \\ ;\n assign m_axi_awaddr[28] = \\ ;\n assign m_axi_awaddr[27] = \\ ;\n assign m_axi_awaddr[26] = \\ ;\n assign m_axi_awaddr[25] = \\ ;\n assign m_axi_awaddr[24] = \\ ;\n assign m_axi_awaddr[23] = \\ ;\n assign m_axi_awaddr[22] = \\ ;\n assign m_axi_awaddr[21] = \\ ;\n assign m_axi_awaddr[20] = \\ ;\n assign m_axi_awaddr[19] = \\ ;\n assign m_axi_awaddr[18] = \\ ;\n assign m_axi_awaddr[17] = \\ ;\n assign m_axi_awaddr[16] = \\ ;\n assign m_axi_awaddr[15] = \\ ;\n assign m_axi_awaddr[14] = \\ ;\n assign m_axi_awaddr[13] = \\ ;\n assign m_axi_awaddr[12] = \\ ;\n assign m_axi_awaddr[11] = \\ ;\n assign m_axi_awaddr[10] = \\ ;\n assign m_axi_awaddr[9] = \\ ;\n assign m_axi_awaddr[8] = \\ ;\n assign m_axi_awaddr[7] = \\ ;\n assign m_axi_awaddr[6] = \\ ;\n assign m_axi_awaddr[5] = \\ ;\n assign m_axi_awaddr[4] = \\ ;\n assign m_axi_awaddr[3] = \\ ;\n assign m_axi_awaddr[2] = \\ ;\n assign m_axi_awaddr[1] = \\ ;\n assign m_axi_awaddr[0] = \\ ;\n assign m_axi_awburst[1] = \\ ;\n assign m_axi_awburst[0] = \\ ;\n assign m_axi_awcache[3] = \\ ;\n assign m_axi_awcache[2] = \\ ;\n assign m_axi_awcache[1] = \\ ;\n assign m_axi_awcache[0] = \\ ;\n assign m_axi_awid[0] = \\ ;\n assign m_axi_awlen[7] = \\ ;\n assign m_axi_awlen[6] = \\ ;\n assign m_axi_awlen[5] = \\ ;\n assign m_axi_awlen[4] = \\ ;\n assign m_axi_awlen[3] = \\ ;\n assign m_axi_awlen[2] = \\ ;\n assign m_axi_awlen[1] = \\ ;\n assign m_axi_awlen[0] = \\ ;\n assign m_axi_awlock[0] = \\ ;\n assign m_axi_awprot[2] = \\ ;\n assign m_axi_awprot[1] = \\ ;\n assign m_axi_awprot[0] = \\ ;\n assign m_axi_awqos[3] = \\ ;\n assign m_axi_awqos[2] = \\ ;\n assign m_axi_awqos[1] = \\ ;\n assign m_axi_awqos[0] = \\ ;\n assign m_axi_awregion[3] = \\ ;\n assign m_axi_awregion[2] = \\ ;\n assign m_axi_awregion[1] = \\ ;\n assign m_axi_awregion[0] = \\ ;\n assign m_axi_awsize[2] = \\ ;\n assign m_axi_awsize[1] = \\ ;\n assign m_axi_awsize[0] = \\ ;\n assign m_axi_awuser[0] = \\ ;\n assign m_axi_awvalid = \\ ;\n assign m_axi_bready = \\ ;\n assign m_axi_rready = \\ ;\n assign m_axi_wdata[63] = \\ ;\n assign m_axi_wdata[62] = \\ ;\n assign m_axi_wdata[61] = \\ ;\n assign m_axi_wdata[60] = \\ ;\n assign m_axi_wdata[59] = \\ ;\n assign m_axi_wdata[58] = \\ ;\n assign m_axi_wdata[57] = \\ ;\n assign m_axi_wdata[56] = \\ ;\n assign m_axi_wdata[55] = \\ ;\n assign m_axi_wdata[54] = \\ ;\n assign m_axi_wdata[53] = \\ ;\n assign m_axi_wdata[52] = \\ ;\n assign m_axi_wdata[51] = \\ ;\n assign m_axi_wdata[50] = \\ ;\n assign m_axi_wdata[49] = \\ ;\n assign m_axi_wdata[48] = \\ ;\n assign m_axi_wdata[47] = \\ ;\n assign m_axi_wdata[46] = \\ ;\n assign m_axi_wdata[45] = \\ ;\n assign m_axi_wdata[44] = \\ ;\n assign m_axi_wdata[43] = \\ ;\n assign m_axi_wdata[42] = \\ ;\n assign m_axi_wdata[41] = \\ ;\n assign m_axi_wdata[40] = \\ ;\n assign m_axi_wdata[39] = \\ ;\n assign m_axi_wdata[38] = \\ ;\n assign m_axi_wdata[37] = \\ ;\n assign m_axi_wdata[36] = \\ ;\n assign m_axi_wdata[35] = \\ ;\n assign m_axi_wdata[34] = \\ ;\n assign m_axi_wdata[33] = \\ ;\n assign m_axi_wdata[32] = \\ ;\n assign m_axi_wdata[31] = \\ ;\n assign m_axi_wdata[30] = \\ ;\n assign m_axi_wdata[29] = \\ ;\n assign m_axi_wdata[28] = \\ ;\n assign m_axi_wdata[27] = \\ ;\n assign m_axi_wdata[26] = \\ ;\n assign m_axi_wdata[25] = \\ ;\n assign m_axi_wdata[24] = \\ ;\n assign m_axi_wdata[23] = \\ ;\n assign m_axi_wdata[22] = \\ ;\n assign m_axi_wdata[21] = \\ ;\n assign m_axi_wdata[20] = \\ ;\n assign m_axi_wdata[19] = \\ ;\n assign m_axi_wdata[18] = \\ ;\n assign m_axi_wdata[17] = \\ ;\n assign m_axi_wdata[16] = \\ ;\n assign m_axi_wdata[15] = \\ ;\n assign m_axi_wdata[14] = \\ ;\n assign m_axi_wdata[13] = \\ ;\n assign m_axi_wdata[12] = \\ ;\n assign m_axi_wdata[11] = \\ ;\n assign m_axi_wdata[10] = \\ ;\n assign m_axi_wdata[9] = \\ ;\n assign m_axi_wdata[8] = \\ ;\n assign m_axi_wdata[7] = \\ ;\n assign m_axi_wdata[6] = \\ ;\n assign m_axi_wdata[5] = \\ ;\n assign m_axi_wdata[4] = \\ ;\n assign m_axi_wdata[3] = \\ ;\n assign m_axi_wdata[2] = \\ ;\n assign m_axi_wdata[1] = \\ ;\n assign m_axi_wdata[0] = \\ ;\n assign m_axi_wid[0] = \\ ;\n assign m_axi_wlast = \\ ;\n assign m_axi_wstrb[7] = \\ ;\n assign m_axi_wstrb[6] = \\ ;\n assign m_axi_wstrb[5] = \\ ;\n assign m_axi_wstrb[4] = \\ ;\n assign m_axi_wstrb[3] = \\ ;\n assign m_axi_wstrb[2] = \\ ;\n assign m_axi_wstrb[1] = \\ ;\n assign m_axi_wstrb[0] = \\ ;\n assign m_axi_wuser[0] = \\ ;\n assign m_axi_wvalid = \\ ;\n assign m_axis_tdata[7] = \\ ;\n assign m_axis_tdata[6] = \\ ;\n assign m_axis_tdata[5] = \\ ;\n assign m_axis_tdata[4] = \\ ;\n assign m_axis_tdata[3] = \\ ;\n assign m_axis_tdata[2] = \\ ;\n assign m_axis_tdata[1] = \\ ;\n assign m_axis_tdata[0] = \\ ;\n assign m_axis_tdest[0] = \\ ;\n assign m_axis_tid[0] = \\ ;\n assign m_axis_tkeep[0] = \\ ;\n assign m_axis_tlast = \\ ;\n assign m_axis_tstrb[0] = \\ ;\n assign m_axis_tuser[3] = \\ ;\n assign m_axis_tuser[2] = \\ ;\n assign m_axis_tuser[1] = \\ ;\n assign m_axis_tuser[0] = \\ ;\n assign m_axis_tvalid = \\ ;\n assign overflow = \\ ;\n assign prog_full = \\ ;\n assign rd_data_count[8] = \\ ;\n assign rd_data_count[7] = \\ ;\n assign rd_data_count[6] = \\ ;\n assign rd_data_count[5] = \\ ;\n assign rd_data_count[4] = \\ ;\n assign rd_data_count[3] = \\ ;\n assign rd_data_count[2] = \\ ;\n assign rd_data_count[1] = \\ ;\n assign rd_data_count[0] = \\ ;\n assign rd_rst_busy = \\ ;\n assign s_axi_arready = \\ ;\n assign s_axi_awready = \\ ;\n assign s_axi_bid[0] = \\ ;\n assign s_axi_bresp[1] = \\ ;\n assign s_axi_bresp[0] = \\ ;\n assign s_axi_buser[0] = \\ ;\n assign s_axi_bvalid = \\ ;\n assign s_axi_rdata[63] = \\ ;\n assign s_axi_rdata[62] = \\ ;\n assign s_axi_rdata[61] = \\ ;\n assign s_axi_rdata[60] = \\ ;\n assign s_axi_rdata[59] = \\ ;\n assign s_axi_rdata[58] = \\ ;\n assign s_axi_rdata[57] = \\ ;\n assign s_axi_rdata[56] = \\ ;\n assign s_axi_rdata[55] = \\ ;\n assign s_axi_rdata[54] = \\ ;\n assign s_axi_rdata[53] = \\ ;\n assign s_axi_rdata[52] = \\ ;\n assign s_axi_rdata[51] = \\ ;\n assign s_axi_rdata[50] = \\ ;\n assign s_axi_rdata[49] = \\ ;\n assign s_axi_rdata[48] = \\ ;\n assign s_axi_rdata[47] = \\ ;\n assign s_axi_rdata[46] = \\ ;\n assign s_axi_rdata[45] = \\ ;\n assign s_axi_rdata[44] = \\ ;\n assign s_axi_rdata[43] = \\ ;\n assign s_axi_rdata[42] = \\ ;\n assign s_axi_rdata[41] = \\ ;\n assign s_axi_rdata[40] = \\ ;\n assign s_axi_rdata[39] = \\ ;\n assign s_axi_rdata[38] = \\ ;\n assign s_axi_rdata[37] = \\ ;\n assign s_axi_rdata[36] = \\ ;\n assign s_axi_rdata[35] = \\ ;\n assign s_axi_rdata[34] = \\ ;\n assign s_axi_rdata[33] = \\ ;\n assign s_axi_rdata[32] = \\ ;\n assign s_axi_rdata[31] = \\ ;\n assign s_axi_rdata[30] = \\ ;\n assign s_axi_rdata[29] = \\ ;\n assign s_axi_rdata[28] = \\ ;\n assign s_axi_rdata[27] = \\ ;\n assign s_axi_rdata[26] = \\ ;\n assign s_axi_rdata[25] = \\ ;\n assign s_axi_rdata[24] = \\ ;\n assign s_axi_rdata[23] = \\ ;\n assign s_axi_rdata[22] = \\ ;\n assign s_axi_rdata[21] = \\ ;\n assign s_axi_rdata[20] = \\ ;\n assign s_axi_rdata[19] = \\ ;\n assign s_axi_rdata[18] = \\ ;\n assign s_axi_rdata[17] = \\ ;\n assign s_axi_rdata[16] = \\ ;\n assign s_axi_rdata[15] = \\ ;\n assign s_axi_rdata[14] = \\ ;\n assign s_axi_rdata[13] = \\ ;\n assign s_axi_rdata[12] = \\ ;\n assign s_axi_rdata[11] = \\ ;\n assign s_axi_rdata[10] = \\ ;\n assign s_axi_rdata[9] = \\ ;\n assign s_axi_rdata[8] = \\ ;\n assign s_axi_rdata[7] = \\ ;\n assign s_axi_rdata[6] = \\ ;\n assign s_axi_rdata[5] = \\ ;\n assign s_axi_rdata[4] = \\ ;\n assign s_axi_rdata[3] = \\ ;\n assign s_axi_rdata[2] = \\ ;\n assign s_axi_rdata[1] = \\ ;\n assign s_axi_rdata[0] = \\ ;\n assign s_axi_rid[0] = \\ ;\n assign s_axi_rlast = \\ ;\n assign s_axi_rresp[1] = \\ ;\n assign s_axi_rresp[0] = \\ ;\n assign s_axi_ruser[0] = \\ ;\n assign s_axi_rvalid = \\ ;\n assign s_axi_wready = \\ ;\n assign s_axis_tready = \\ ;\n assign sbiterr = \\ ;\n assign underflow = \\ ;\n assign valid = \\ ;\n assign wr_ack = \\ ;\n assign wr_data_count[10] = \\ ;\n assign wr_data_count[9] = \\ ;\n assign wr_data_count[8] = \\ ;\n assign wr_data_count[7] = \\ ;\n assign wr_data_count[6] = \\ ;\n assign wr_data_count[5] = \\ ;\n assign wr_data_count[4] = \\ ;\n assign wr_data_count[3] = \\ ;\n assign wr_data_count[2] = \\ ;\n assign wr_data_count[1] = \\ ;\n assign wr_data_count[0] = \\ ;\n GND GND\n (.G(\\ ));\n VCC VCC\n (.P(\\ ));\n fb_input_fifo_fifo_generator_v13_1_2_synth inst_fifo_gen\n (.din(din),\n .dout(dout),\n .empty(empty),\n .full(full),\n .prog_empty(prog_empty),\n .rd_clk(rd_clk),\n .rd_en(rd_en),\n .rst(rst),\n .wr_clk(wr_clk),\n .wr_en(wr_en),\n .wr_rst_busy(wr_rst_busy));\nendmodule\n\n(* ORIG_REF_NAME = \"fifo_generator_v13_1_2_synth\" *) \nmodule fb_input_fifo_fifo_generator_v13_1_2_synth\n (wr_rst_busy,\n dout,\n empty,\n full,\n prog_empty,\n rd_en,\n wr_en,\n rd_clk,\n wr_clk,\n din,\n rst);\n output wr_rst_busy;\n output [255:0]dout;\n output empty;\n output full;\n output prog_empty;\n input rd_en;\n input wr_en;\n input rd_clk;\n input wr_clk;\n input [63:0]din;\n input rst;\n\n wire [63:0]din;\n wire [255:0]dout;\n wire empty;\n wire full;\n wire prog_empty;\n wire rd_clk;\n wire rd_en;\n wire rst;\n wire wr_clk;\n wire wr_en;\n wire wr_rst_busy;\n\n fb_input_fifo_fifo_generator_top \\gconvfifo.rf \n (.din(din),\n .dout(dout),\n .empty(empty),\n .full(full),\n .prog_empty(prog_empty),\n .rd_clk(rd_clk),\n .rd_en(rd_en),\n .rst(rst),\n .wr_clk(wr_clk),\n .wr_en(wr_en),\n .wr_rst_busy(wr_rst_busy));\nendmodule\n\n(* ORIG_REF_NAME = \"memory\" *) \nmodule fb_input_fifo_memory\n (dout,\n rd_clk,\n wr_clk,\n tmp_ram_rd_en,\n ram_full_fb_i_reg,\n out,\n Q,\n \\gic0.gc0.count_d2_reg[10] ,\n din);\n output [255:0]dout;\n input rd_clk;\n input wr_clk;\n input tmp_ram_rd_en;\n input ram_full_fb_i_reg;\n input [0:0]out;\n input [8:0]Q;\n input [10:0]\\gic0.gc0.count_d2_reg[10] ;\n input [63:0]din;\n\n wire [8:0]Q;\n wire [63:0]din;\n wire [255:0]dout;\n wire [10:0]\\gic0.gc0.count_d2_reg[10] ;\n wire [0:0]out;\n wire ram_full_fb_i_reg;\n wire rd_clk;\n wire tmp_ram_rd_en;\n wire wr_clk;\n\n fb_input_fifo_blk_mem_gen_v8_3_4 \\gbm.gbmg.gbmga.ngecc.bmg \n (.Q(Q),\n .din(din),\n .dout(dout),\n .\\gic0.gc0.count_d2_reg[10] (\\gic0.gc0.count_d2_reg[10] ),\n .out(out),\n .ram_full_fb_i_reg(ram_full_fb_i_reg),\n .rd_clk(rd_clk),\n .tmp_ram_rd_en(tmp_ram_rd_en),\n .wr_clk(wr_clk));\nendmodule\n\n(* ORIG_REF_NAME = \"rd_bin_cntr\" *) \nmodule fb_input_fifo_rd_bin_cntr\n (ram_empty_fb_i_reg,\n Q,\n ram_empty_fb_i_reg_0,\n \\gc0.count_d1_reg[7]_0 ,\n WR_PNTR_RD,\n E,\n rd_clk,\n AR);\n output ram_empty_fb_i_reg;\n output [8:0]Q;\n output ram_empty_fb_i_reg_0;\n output [7:0]\\gc0.count_d1_reg[7]_0 ;\n input [0:0]WR_PNTR_RD;\n input [0:0]E;\n input rd_clk;\n input [0:0]AR;\n\n wire [0:0]AR;\n wire [0:0]E;\n wire [8:0]Q;\n wire [0:0]WR_PNTR_RD;\n wire \\gc0.count[8]_i_2_n_0 ;\n wire [7:0]\\gc0.count_d1_reg[7]_0 ;\n wire [8:0]plusOp__0;\n wire ram_empty_fb_i_reg;\n wire ram_empty_fb_i_reg_0;\n wire rd_clk;\n wire [8:8]rd_pntr_plus1;\n\n LUT1 #(\n .INIT(2'h1)) \n \\gc0.count[0]_i_1 \n (.I0(\\gc0.count_d1_reg[7]_0 [0]),\n .O(plusOp__0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair11\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gc0.count[1]_i_1 \n (.I0(\\gc0.count_d1_reg[7]_0 [0]),\n .I1(\\gc0.count_d1_reg[7]_0 [1]),\n .O(plusOp__0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair11\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\gc0.count[2]_i_1 \n (.I0(\\gc0.count_d1_reg[7]_0 [0]),\n .I1(\\gc0.count_d1_reg[7]_0 [1]),\n .I2(\\gc0.count_d1_reg[7]_0 [2]),\n .O(plusOp__0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair9\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\gc0.count[3]_i_1 \n (.I0(\\gc0.count_d1_reg[7]_0 [1]),\n .I1(\\gc0.count_d1_reg[7]_0 [0]),\n .I2(\\gc0.count_d1_reg[7]_0 [2]),\n .I3(\\gc0.count_d1_reg[7]_0 [3]),\n .O(plusOp__0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair9\" *) \n LUT5 #(\n .INIT(32'h7FFF8000)) \n \\gc0.count[4]_i_1 \n (.I0(\\gc0.count_d1_reg[7]_0 [2]),\n .I1(\\gc0.count_d1_reg[7]_0 [0]),\n .I2(\\gc0.count_d1_reg[7]_0 [1]),\n .I3(\\gc0.count_d1_reg[7]_0 [3]),\n .I4(\\gc0.count_d1_reg[7]_0 [4]),\n .O(plusOp__0[4]));\n LUT6 #(\n .INIT(64'h7FFFFFFF80000000)) \n \\gc0.count[5]_i_1 \n (.I0(\\gc0.count_d1_reg[7]_0 [3]),\n .I1(\\gc0.count_d1_reg[7]_0 [1]),\n .I2(\\gc0.count_d1_reg[7]_0 [0]),\n .I3(\\gc0.count_d1_reg[7]_0 [2]),\n .I4(\\gc0.count_d1_reg[7]_0 [4]),\n .I5(\\gc0.count_d1_reg[7]_0 [5]),\n .O(plusOp__0[5]));\n LUT2 #(\n .INIT(4'h6)) \n \\gc0.count[6]_i_1 \n (.I0(\\gc0.count[8]_i_2_n_0 ),\n .I1(\\gc0.count_d1_reg[7]_0 [6]),\n .O(plusOp__0[6]));\n (* SOFT_HLUTNM = \"soft_lutpair10\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\gc0.count[7]_i_1 \n (.I0(\\gc0.count[8]_i_2_n_0 ),\n .I1(\\gc0.count_d1_reg[7]_0 [6]),\n .I2(\\gc0.count_d1_reg[7]_0 [7]),\n .O(plusOp__0[7]));\n (* SOFT_HLUTNM = \"soft_lutpair10\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\gc0.count[8]_i_1 \n (.I0(\\gc0.count_d1_reg[7]_0 [6]),\n .I1(\\gc0.count[8]_i_2_n_0 ),\n .I2(\\gc0.count_d1_reg[7]_0 [7]),\n .I3(rd_pntr_plus1),\n .O(plusOp__0[8]));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\gc0.count[8]_i_2 \n (.I0(\\gc0.count_d1_reg[7]_0 [5]),\n .I1(\\gc0.count_d1_reg[7]_0 [3]),\n .I2(\\gc0.count_d1_reg[7]_0 [1]),\n .I3(\\gc0.count_d1_reg[7]_0 [0]),\n .I4(\\gc0.count_d1_reg[7]_0 [2]),\n .I5(\\gc0.count_d1_reg[7]_0 [4]),\n .O(\\gc0.count[8]_i_2_n_0 ));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_d1_reg[0] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(\\gc0.count_d1_reg[7]_0 [0]),\n .Q(Q[0]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_d1_reg[1] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(\\gc0.count_d1_reg[7]_0 [1]),\n .Q(Q[1]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_d1_reg[2] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(\\gc0.count_d1_reg[7]_0 [2]),\n .Q(Q[2]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_d1_reg[3] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(\\gc0.count_d1_reg[7]_0 [3]),\n .Q(Q[3]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_d1_reg[4] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(\\gc0.count_d1_reg[7]_0 [4]),\n .Q(Q[4]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_d1_reg[5] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(\\gc0.count_d1_reg[7]_0 [5]),\n .Q(Q[5]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_d1_reg[6] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(\\gc0.count_d1_reg[7]_0 [6]),\n .Q(Q[6]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_d1_reg[7] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(\\gc0.count_d1_reg[7]_0 [7]),\n .Q(Q[7]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_d1_reg[8] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(rd_pntr_plus1),\n .Q(Q[8]));\n FDPE #(\n .INIT(1'b1)) \n \\gc0.count_reg[0] \n (.C(rd_clk),\n .CE(E),\n .D(plusOp__0[0]),\n .PRE(AR),\n .Q(\\gc0.count_d1_reg[7]_0 [0]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_reg[1] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__0[1]),\n .Q(\\gc0.count_d1_reg[7]_0 [1]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_reg[2] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__0[2]),\n .Q(\\gc0.count_d1_reg[7]_0 [2]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_reg[3] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__0[3]),\n .Q(\\gc0.count_d1_reg[7]_0 [3]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_reg[4] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__0[4]),\n .Q(\\gc0.count_d1_reg[7]_0 [4]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_reg[5] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__0[5]),\n .Q(\\gc0.count_d1_reg[7]_0 [5]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_reg[6] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__0[6]),\n .Q(\\gc0.count_d1_reg[7]_0 [6]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_reg[7] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__0[7]),\n .Q(\\gc0.count_d1_reg[7]_0 [7]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_reg[8] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__0[8]),\n .Q(rd_pntr_plus1));\n LUT2 #(\n .INIT(4'h9)) \n \\gmux.gm[4].gms.ms_i_1__1 \n (.I0(Q[8]),\n .I1(WR_PNTR_RD),\n .O(ram_empty_fb_i_reg));\n LUT2 #(\n .INIT(4'h9)) \n \\gmux.gm[4].gms.ms_i_1__2 \n (.I0(rd_pntr_plus1),\n .I1(WR_PNTR_RD),\n .O(ram_empty_fb_i_reg_0));\nendmodule\n\n(* ORIG_REF_NAME = \"rd_logic\" *) \nmodule fb_input_fifo_rd_logic\n (empty,\n out,\n prog_empty,\n Q,\n \\gc0.count_d1_reg[7] ,\n v1_reg,\n v1_reg_0,\n rd_clk,\n AR,\n WR_PNTR_RD,\n S,\n \\gnxpm_cdc.wr_pntr_bin_reg[9] ,\n \\gnxpm_cdc.wr_pntr_bin_reg[10] ,\n rd_en);\n output empty;\n output out;\n output prog_empty;\n output [8:0]Q;\n output [7:0]\\gc0.count_d1_reg[7] ;\n input [3:0]v1_reg;\n input [3:0]v1_reg_0;\n input rd_clk;\n input [0:0]AR;\n input [8:0]WR_PNTR_RD;\n input [3:0]S;\n input [3:0]\\gnxpm_cdc.wr_pntr_bin_reg[9] ;\n input [0:0]\\gnxpm_cdc.wr_pntr_bin_reg[10] ;\n input rd_en;\n\n wire [0:0]AR;\n wire [8:0]Q;\n wire [3:0]S;\n wire [8:0]WR_PNTR_RD;\n wire empty;\n wire [7:0]\\gc0.count_d1_reg[7] ;\n wire [0:0]\\gnxpm_cdc.wr_pntr_bin_reg[10] ;\n wire [3:0]\\gnxpm_cdc.wr_pntr_bin_reg[9] ;\n wire \\gras.rsts_n_2 ;\n wire out;\n wire p_0_out;\n wire prog_empty;\n wire rd_clk;\n wire rd_en;\n wire rpntr_n_0;\n wire rpntr_n_10;\n wire [3:0]v1_reg;\n wire [3:0]v1_reg_0;\n\n fb_input_fifo_rd_pe_as \\gras.gpe.rdpe \n (.AR(AR),\n .S(S),\n .WR_PNTR_RD(WR_PNTR_RD[7:0]),\n .\\gnxpm_cdc.wr_pntr_bin_reg[10] (\\gnxpm_cdc.wr_pntr_bin_reg[10] ),\n .\\gnxpm_cdc.wr_pntr_bin_reg[9] (\\gnxpm_cdc.wr_pntr_bin_reg[9] ),\n .out(out),\n .p_0_out(p_0_out),\n .prog_empty(prog_empty),\n .rd_clk(rd_clk));\n fb_input_fifo_rd_status_flags_as \\gras.rsts \n (.AR(AR),\n .E(\\gras.rsts_n_2 ),\n .empty(empty),\n .\\gc0.count_d1_reg[8] (rpntr_n_0),\n .\\gc0.count_reg[8] (rpntr_n_10),\n .out(out),\n .p_0_out(p_0_out),\n .rd_clk(rd_clk),\n .rd_en(rd_en),\n .v1_reg(v1_reg),\n .v1_reg_0(v1_reg_0));\n fb_input_fifo_rd_bin_cntr rpntr\n (.AR(AR),\n .E(\\gras.rsts_n_2 ),\n .Q(Q),\n .WR_PNTR_RD(WR_PNTR_RD[8]),\n .\\gc0.count_d1_reg[7]_0 (\\gc0.count_d1_reg[7] ),\n .ram_empty_fb_i_reg(rpntr_n_0),\n .ram_empty_fb_i_reg_0(rpntr_n_10),\n .rd_clk(rd_clk));\nendmodule\n\n(* ORIG_REF_NAME = \"rd_pe_as\" *) \nmodule fb_input_fifo_rd_pe_as\n (prog_empty,\n p_0_out,\n WR_PNTR_RD,\n S,\n \\gnxpm_cdc.wr_pntr_bin_reg[9] ,\n \\gnxpm_cdc.wr_pntr_bin_reg[10] ,\n rd_clk,\n AR,\n out);\n output prog_empty;\n input p_0_out;\n input [7:0]WR_PNTR_RD;\n input [3:0]S;\n input [3:0]\\gnxpm_cdc.wr_pntr_bin_reg[9] ;\n input [0:0]\\gnxpm_cdc.wr_pntr_bin_reg[10] ;\n input rd_clk;\n input [0:0]AR;\n input out;\n\n wire [0:0]AR;\n wire [3:0]S;\n wire [7:0]WR_PNTR_RD;\n wire [9:5]diff_pntr_pad;\n wire [0:0]\\gnxpm_cdc.wr_pntr_bin_reg[10] ;\n wire [3:0]\\gnxpm_cdc.wr_pntr_bin_reg[9] ;\n wire \\gpe1.prog_empty_i_i_1_n_0 ;\n wire leqOp__0;\n wire out;\n wire p_0_out;\n wire [9:5]plusOp;\n wire plusOp_carry__0_n_0;\n wire plusOp_carry__0_n_1;\n wire plusOp_carry__0_n_2;\n wire plusOp_carry__0_n_3;\n wire plusOp_carry_n_0;\n wire plusOp_carry_n_1;\n wire plusOp_carry_n_2;\n wire plusOp_carry_n_3;\n wire prog_empty;\n wire rd_clk;\n wire [3:0]NLW_plusOp_carry_O_UNCONNECTED;\n wire [3:0]NLW_plusOp_carry__1_CO_UNCONNECTED;\n wire [3:1]NLW_plusOp_carry__1_O_UNCONNECTED;\n\n FDCE #(\n .INIT(1'b0)) \n \\gdiff.diff_pntr_pad_reg[5] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(plusOp[5]),\n .Q(diff_pntr_pad[5]));\n FDCE #(\n .INIT(1'b0)) \n \\gdiff.diff_pntr_pad_reg[6] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(plusOp[6]),\n .Q(diff_pntr_pad[6]));\n FDCE #(\n .INIT(1'b0)) \n \\gdiff.diff_pntr_pad_reg[7] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(plusOp[7]),\n .Q(diff_pntr_pad[7]));\n FDCE #(\n .INIT(1'b0)) \n \\gdiff.diff_pntr_pad_reg[8] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(plusOp[8]),\n .Q(diff_pntr_pad[8]));\n FDCE #(\n .INIT(1'b0)) \n \\gdiff.diff_pntr_pad_reg[9] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(plusOp[9]),\n .Q(diff_pntr_pad[9]));\n LUT3 #(\n .INIT(8'hB8)) \n \\gpe1.prog_empty_i_i_1 \n (.I0(prog_empty),\n .I1(out),\n .I2(leqOp__0),\n .O(\\gpe1.prog_empty_i_i_1_n_0 ));\n FDPE #(\n .INIT(1'b1)) \n \\gpe1.prog_empty_i_reg \n (.C(rd_clk),\n .CE(1'b1),\n .D(\\gpe1.prog_empty_i_i_1_n_0 ),\n .PRE(AR),\n .Q(prog_empty));\n LUT5 #(\n .INIT(32'h00000001)) \n leqOp\n (.I0(diff_pntr_pad[8]),\n .I1(diff_pntr_pad[9]),\n .I2(diff_pntr_pad[5]),\n .I3(diff_pntr_pad[6]),\n .I4(diff_pntr_pad[7]),\n .O(leqOp__0));\n CARRY4 plusOp_carry\n (.CI(1'b0),\n .CO({plusOp_carry_n_0,plusOp_carry_n_1,plusOp_carry_n_2,plusOp_carry_n_3}),\n .CYINIT(p_0_out),\n .DI(WR_PNTR_RD[3:0]),\n .O(NLW_plusOp_carry_O_UNCONNECTED[3:0]),\n .S(S));\n CARRY4 plusOp_carry__0\n (.CI(plusOp_carry_n_0),\n .CO({plusOp_carry__0_n_0,plusOp_carry__0_n_1,plusOp_carry__0_n_2,plusOp_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI(WR_PNTR_RD[7:4]),\n .O(plusOp[8:5]),\n .S(\\gnxpm_cdc.wr_pntr_bin_reg[9] ));\n CARRY4 plusOp_carry__1\n (.CI(plusOp_carry__0_n_0),\n .CO(NLW_plusOp_carry__1_CO_UNCONNECTED[3:0]),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({NLW_plusOp_carry__1_O_UNCONNECTED[3:1],plusOp[9]}),\n .S({1'b0,1'b0,1'b0,\\gnxpm_cdc.wr_pntr_bin_reg[10] }));\nendmodule\n\n(* ORIG_REF_NAME = \"rd_status_flags_as\" *) \nmodule fb_input_fifo_rd_status_flags_as\n (empty,\n out,\n E,\n p_0_out,\n v1_reg,\n \\gc0.count_d1_reg[8] ,\n v1_reg_0,\n \\gc0.count_reg[8] ,\n rd_clk,\n AR,\n rd_en);\n output empty;\n output out;\n output [0:0]E;\n output p_0_out;\n input [3:0]v1_reg;\n input \\gc0.count_d1_reg[8] ;\n input [3:0]v1_reg_0;\n input \\gc0.count_reg[8] ;\n input rd_clk;\n input [0:0]AR;\n input rd_en;\n\n wire [0:0]AR;\n wire [0:0]E;\n wire c0_n_0;\n wire comp1;\n wire \\gc0.count_d1_reg[8] ;\n wire \\gc0.count_reg[8] ;\n wire p_0_out;\n (* DONT_TOUCH *) wire ram_empty_fb_i;\n (* DONT_TOUCH *) wire ram_empty_i;\n wire rd_clk;\n wire rd_en;\n wire [3:0]v1_reg;\n wire [3:0]v1_reg_0;\n\n assign empty = ram_empty_i;\n assign out = ram_empty_fb_i;\n fb_input_fifo_compare c0\n (.comp1(comp1),\n .\\gc0.count_d1_reg[8] (\\gc0.count_d1_reg[8] ),\n .out(ram_empty_fb_i),\n .ram_empty_fb_i_reg(c0_n_0),\n .rd_en(rd_en),\n .v1_reg(v1_reg));\n fb_input_fifo_compare_3 c1\n (.comp1(comp1),\n .\\gc0.count_reg[8] (\\gc0.count_reg[8] ),\n .v1_reg_0(v1_reg_0));\n LUT2 #(\n .INIT(4'h2)) \n \\gc0.count_d1[8]_i_1 \n (.I0(rd_en),\n .I1(ram_empty_fb_i),\n .O(E));\n LUT2 #(\n .INIT(4'hB)) \n plusOp_carry_i_1\n (.I0(ram_empty_fb_i),\n .I1(rd_en),\n .O(p_0_out));\n (* DONT_TOUCH *) \n (* KEEP = \"yes\" *) \n (* equivalent_register_removal = \"no\" *) \n FDPE #(\n .INIT(1'b1)) \n ram_empty_fb_i_reg\n (.C(rd_clk),\n .CE(1'b1),\n .D(c0_n_0),\n .PRE(AR),\n .Q(ram_empty_fb_i));\n (* DONT_TOUCH *) \n (* KEEP = \"yes\" *) \n (* equivalent_register_removal = \"no\" *) \n FDPE #(\n .INIT(1'b1)) \n ram_empty_i_reg\n (.C(rd_clk),\n .CE(1'b1),\n .D(c0_n_0),\n .PRE(AR),\n .Q(ram_empty_i));\nendmodule\n\n(* ORIG_REF_NAME = \"reset_blk_ramfifo\" *) \nmodule fb_input_fifo_reset_blk_ramfifo\n (out,\n \\gc0.count_reg[1] ,\n \\grstd1.grst_full.grst_f.rst_d3_reg_0 ,\n wr_rst_busy,\n tmp_ram_rd_en,\n rd_clk,\n wr_clk,\n rst,\n ram_empty_fb_i_reg,\n rd_en);\n output [1:0]out;\n output [2:0]\\gc0.count_reg[1] ;\n output \\grstd1.grst_full.grst_f.rst_d3_reg_0 ;\n output wr_rst_busy;\n output tmp_ram_rd_en;\n input rd_clk;\n input wr_clk;\n input rst;\n input ram_empty_fb_i_reg;\n input rd_en;\n\n wire \\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ;\n wire \\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ;\n wire \\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ;\n wire \\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ;\n wire p_7_out;\n wire p_8_out;\n wire ram_empty_fb_i_reg;\n wire rd_clk;\n wire rd_en;\n wire rd_rst_asreg;\n (* DONT_TOUCH *) wire [2:0]rd_rst_reg;\n wire rst;\n (* async_reg = \"true\" *) (* msgon = \"true\" *) wire rst_d1;\n (* async_reg = \"true\" *) (* msgon = \"true\" *) wire rst_d2;\n (* async_reg = \"true\" *) (* msgon = \"true\" *) wire rst_d3;\n (* async_reg = \"true\" *) (* msgon = \"true\" *) wire rst_rd_reg1;\n (* async_reg = \"true\" *) (* msgon = \"true\" *) wire rst_rd_reg2;\n (* async_reg = \"true\" *) (* msgon = \"true\" *) wire rst_wr_reg1;\n (* async_reg = \"true\" *) (* msgon = \"true\" *) wire rst_wr_reg2;\n wire tmp_ram_rd_en;\n wire wr_clk;\n wire wr_rst_asreg;\n (* DONT_TOUCH *) wire [2:0]wr_rst_reg;\n\n assign \\gc0.count_reg[1] [2:0] = rd_rst_reg;\n assign \\grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d2;\n assign out[1:0] = wr_rst_reg[1:0];\n assign wr_rst_busy = rst_d3;\n LUT3 #(\n .INIT(8'hBA)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_i_1 \n (.I0(rd_rst_reg[0]),\n .I1(ram_empty_fb_i_reg),\n .I2(rd_en),\n .O(tmp_ram_rd_en));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDPE #(\n .INIT(1'b1)) \n \\grstd1.grst_full.grst_f.rst_d1_reg \n (.C(wr_clk),\n .CE(1'b1),\n .D(1'b0),\n .PRE(rst_wr_reg2),\n .Q(rst_d1));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDPE #(\n .INIT(1'b1)) \n \\grstd1.grst_full.grst_f.rst_d2_reg \n (.C(wr_clk),\n .CE(1'b1),\n .D(rst_d1),\n .PRE(rst_wr_reg2),\n .Q(rst_d2));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDPE #(\n .INIT(1'b1)) \n \\grstd1.grst_full.grst_f.rst_d3_reg \n (.C(wr_clk),\n .CE(1'b1),\n .D(rst_d2),\n .PRE(rst_wr_reg2),\n .Q(rst_d3));\n fb_input_fifo_synchronizer_ff \\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst \n (.in0(rd_rst_asreg),\n .\\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg (\\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ),\n .out(p_7_out),\n .rd_clk(rd_clk));\n fb_input_fifo_synchronizer_ff_0 \\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst \n (.in0(wr_rst_asreg),\n .\\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg (\\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ),\n .out(p_8_out),\n .wr_clk(wr_clk));\n fb_input_fifo_synchronizer_ff_1 \\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst \n (.AS(\\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),\n .in0(rd_rst_asreg),\n .out(p_7_out),\n .rd_clk(rd_clk));\n fb_input_fifo_synchronizer_ff_2 \\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst \n (.AS(\\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),\n .in0(wr_rst_asreg),\n .out(p_8_out),\n .wr_clk(wr_clk));\n FDPE #(\n .INIT(1'b1)) \n \\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg \n (.C(rd_clk),\n .CE(1'b1),\n .D(\\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ),\n .PRE(rst_rd_reg2),\n .Q(rd_rst_asreg));\n (* DONT_TOUCH *) \n (* KEEP = \"yes\" *) \n (* equivalent_register_removal = \"no\" *) \n FDPE #(\n .INIT(1'b1)) \n \\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] \n (.C(rd_clk),\n .CE(1'b1),\n .D(1'b0),\n .PRE(\\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),\n .Q(rd_rst_reg[0]));\n (* DONT_TOUCH *) \n (* KEEP = \"yes\" *) \n (* equivalent_register_removal = \"no\" *) \n FDPE #(\n .INIT(1'b1)) \n \\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] \n (.C(rd_clk),\n .CE(1'b1),\n .D(1'b0),\n .PRE(\\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),\n .Q(rd_rst_reg[1]));\n (* DONT_TOUCH *) \n (* KEEP = \"yes\" *) \n (* equivalent_register_removal = \"no\" *) \n FDPE #(\n .INIT(1'b1)) \n \\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] \n (.C(rd_clk),\n .CE(1'b1),\n .D(1'b0),\n .PRE(\\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),\n .Q(rd_rst_reg[2]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDPE #(\n .INIT(1'b0)) \n \\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg \n (.C(rd_clk),\n .CE(1'b1),\n .D(1'b0),\n .PRE(rst),\n .Q(rst_rd_reg1));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDPE #(\n .INIT(1'b0)) \n \\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg \n (.C(rd_clk),\n .CE(1'b1),\n .D(rst_rd_reg1),\n .PRE(rst),\n .Q(rst_rd_reg2));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDPE #(\n .INIT(1'b0)) \n \\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg \n (.C(wr_clk),\n .CE(1'b1),\n .D(1'b0),\n .PRE(rst),\n .Q(rst_wr_reg1));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDPE #(\n .INIT(1'b0)) \n \\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg \n (.C(wr_clk),\n .CE(1'b1),\n .D(rst_wr_reg1),\n .PRE(rst),\n .Q(rst_wr_reg2));\n FDPE #(\n .INIT(1'b1)) \n \\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg \n (.C(wr_clk),\n .CE(1'b1),\n .D(\\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ),\n .PRE(rst_wr_reg2),\n .Q(wr_rst_asreg));\n (* DONT_TOUCH *) \n (* KEEP = \"yes\" *) \n (* equivalent_register_removal = \"no\" *) \n FDPE #(\n .INIT(1'b1)) \n \\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] \n (.C(wr_clk),\n .CE(1'b1),\n .D(1'b0),\n .PRE(\\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),\n .Q(wr_rst_reg[0]));\n (* DONT_TOUCH *) \n (* KEEP = \"yes\" *) \n (* equivalent_register_removal = \"no\" *) \n FDPE #(\n .INIT(1'b1)) \n \\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] \n (.C(wr_clk),\n .CE(1'b1),\n .D(1'b0),\n .PRE(\\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),\n .Q(wr_rst_reg[1]));\n (* DONT_TOUCH *) \n (* KEEP = \"yes\" *) \n (* equivalent_register_removal = \"no\" *) \n FDPE #(\n .INIT(1'b1)) \n \\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2] \n (.C(wr_clk),\n .CE(1'b1),\n .D(1'b0),\n .PRE(\\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),\n .Q(wr_rst_reg[2]));\nendmodule\n\n(* ORIG_REF_NAME = \"synchronizer_ff\" *) \nmodule fb_input_fifo_synchronizer_ff\n (out,\n \\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ,\n in0,\n rd_clk);\n output out;\n output \\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ;\n input [0:0]in0;\n input rd_clk;\n\n (* async_reg = \"true\" *) (* msgon = \"true\" *) wire Q_reg;\n wire [0:0]in0;\n wire \\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ;\n wire rd_clk;\n\n assign out = Q_reg;\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDRE #(\n .INIT(1'b0)) \n \\Q_reg_reg[0] \n (.C(rd_clk),\n .CE(1'b1),\n .D(in0),\n .Q(Q_reg),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h2)) \n \\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1 \n (.I0(in0),\n .I1(Q_reg),\n .O(\\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ));\nendmodule\n\n(* ORIG_REF_NAME = \"synchronizer_ff\" *) \nmodule fb_input_fifo_synchronizer_ff_0\n (out,\n \\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ,\n in0,\n wr_clk);\n output out;\n output \\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ;\n input [0:0]in0;\n input wr_clk;\n\n (* async_reg = \"true\" *) (* msgon = \"true\" *) wire Q_reg;\n wire [0:0]in0;\n wire \\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ;\n wire wr_clk;\n\n assign out = Q_reg;\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDRE #(\n .INIT(1'b0)) \n \\Q_reg_reg[0] \n (.C(wr_clk),\n .CE(1'b1),\n .D(in0),\n .Q(Q_reg),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h2)) \n \\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1 \n (.I0(in0),\n .I1(Q_reg),\n .O(\\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ));\nendmodule\n\n(* ORIG_REF_NAME = \"synchronizer_ff\" *) \nmodule fb_input_fifo_synchronizer_ff_1\n (AS,\n out,\n rd_clk,\n in0);\n output [0:0]AS;\n input out;\n input rd_clk;\n input [0:0]in0;\n\n wire [0:0]AS;\n (* async_reg = \"true\" *) (* msgon = \"true\" *) wire Q_reg;\n wire [0:0]in0;\n wire out;\n wire rd_clk;\n\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDRE #(\n .INIT(1'b0)) \n \\Q_reg_reg[0] \n (.C(rd_clk),\n .CE(1'b1),\n .D(out),\n .Q(Q_reg),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h2)) \n \\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1 \n (.I0(in0),\n .I1(Q_reg),\n .O(AS));\nendmodule\n\n(* ORIG_REF_NAME = \"synchronizer_ff\" *) \nmodule fb_input_fifo_synchronizer_ff_2\n (AS,\n out,\n wr_clk,\n in0);\n output [0:0]AS;\n input out;\n input wr_clk;\n input [0:0]in0;\n\n wire [0:0]AS;\n (* async_reg = \"true\" *) (* msgon = \"true\" *) wire Q_reg;\n wire [0:0]in0;\n wire out;\n wire wr_clk;\n\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDRE #(\n .INIT(1'b0)) \n \\Q_reg_reg[0] \n (.C(wr_clk),\n .CE(1'b1),\n .D(out),\n .Q(Q_reg),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h2)) \n \\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1 \n (.I0(in0),\n .I1(Q_reg),\n .O(AS));\nendmodule\n\n(* ORIG_REF_NAME = \"synchronizer_ff\" *) \nmodule fb_input_fifo_synchronizer_ff__parameterized0\n (D,\n Q,\n rd_clk,\n \\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );\n output [10:0]D;\n input [10:0]Q;\n input rd_clk;\n input [0:0]\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;\n\n wire [10:0]Q;\n (* async_reg = \"true\" *) (* msgon = \"true\" *) wire [10:0]Q_reg;\n wire [0:0]\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;\n wire rd_clk;\n\n assign D[10:0] = Q_reg;\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[0] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(Q[0]),\n .Q(Q_reg[0]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[10] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(Q[10]),\n .Q(Q_reg[10]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[1] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(Q[1]),\n .Q(Q_reg[1]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[2] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(Q[2]),\n .Q(Q_reg[2]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[3] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(Q[3]),\n .Q(Q_reg[3]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[4] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(Q[4]),\n .Q(Q_reg[4]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[5] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(Q[5]),\n .Q(Q_reg[5]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[6] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(Q[6]),\n .Q(Q_reg[6]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[7] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(Q[7]),\n .Q(Q_reg[7]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[8] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(Q[8]),\n .Q(Q_reg[8]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[9] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(Q[9]),\n .Q(Q_reg[9]));\nendmodule\n\n(* ORIG_REF_NAME = \"synchronizer_ff\" *) \nmodule fb_input_fifo_synchronizer_ff__parameterized1\n (D,\n Q,\n wr_clk,\n AR);\n output [8:0]D;\n input [8:0]Q;\n input wr_clk;\n input [0:0]AR;\n\n wire [0:0]AR;\n wire [8:0]Q;\n (* async_reg = \"true\" *) (* msgon = \"true\" *) wire [8:0]Q_reg;\n wire wr_clk;\n\n assign D[8:0] = Q_reg;\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[0] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(Q[0]),\n .Q(Q_reg[0]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[1] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(Q[1]),\n .Q(Q_reg[1]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[2] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(Q[2]),\n .Q(Q_reg[2]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[3] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(Q[3]),\n .Q(Q_reg[3]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[4] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(Q[4]),\n .Q(Q_reg[4]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[5] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(Q[5]),\n .Q(Q_reg[5]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[6] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(Q[6]),\n .Q(Q_reg[6]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[7] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(Q[7]),\n .Q(Q_reg[7]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[8] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(Q[8]),\n .Q(Q_reg[8]));\nendmodule\n\n(* ORIG_REF_NAME = \"synchronizer_ff\" *) \nmodule fb_input_fifo_synchronizer_ff__parameterized2\n (out,\n \\gnxpm_cdc.wr_pntr_bin_reg[9] ,\n D,\n rd_clk,\n \\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );\n output [0:0]out;\n output [7:0]\\gnxpm_cdc.wr_pntr_bin_reg[9] ;\n input [10:0]D;\n input rd_clk;\n input [0:0]\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;\n\n wire [10:0]D;\n (* async_reg = \"true\" *) (* msgon = \"true\" *) wire [10:0]Q_reg;\n wire \\gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0 ;\n wire \\gnxpm_cdc.wr_pntr_bin[4]_i_2_n_0 ;\n wire [7:0]\\gnxpm_cdc.wr_pntr_bin_reg[9] ;\n wire [0:0]\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;\n wire rd_clk;\n\n assign out[0] = Q_reg[10];\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[0] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(D[0]),\n .Q(Q_reg[0]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[10] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(D[10]),\n .Q(Q_reg[10]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[1] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(D[1]),\n .Q(Q_reg[1]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[2] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(D[2]),\n .Q(Q_reg[2]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[3] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(D[3]),\n .Q(Q_reg[3]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[4] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(D[4]),\n .Q(Q_reg[4]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[5] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(D[5]),\n .Q(Q_reg[5]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[6] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(D[6]),\n .Q(Q_reg[6]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[7] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(D[7]),\n .Q(Q_reg[7]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[8] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(D[8]),\n .Q(Q_reg[8]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[9] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(D[9]),\n .Q(Q_reg[9]));\n LUT6 #(\n .INIT(64'h6996966996696996)) \n \\gnxpm_cdc.wr_pntr_bin[2]_i_1 \n (.I0(Q_reg[3]),\n .I1(Q_reg[2]),\n .I2(\\gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0 ),\n .I3(Q_reg[5]),\n .I4(Q_reg[4]),\n .I5(Q_reg[10]),\n .O(\\gnxpm_cdc.wr_pntr_bin_reg[9] [0]));\n LUT5 #(\n .INIT(32'h96696996)) \n \\gnxpm_cdc.wr_pntr_bin[3]_i_1 \n (.I0(\\gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0 ),\n .I1(Q_reg[5]),\n .I2(Q_reg[4]),\n .I3(Q_reg[10]),\n .I4(Q_reg[3]),\n .O(\\gnxpm_cdc.wr_pntr_bin_reg[9] [1]));\n LUT4 #(\n .INIT(16'h6996)) \n \\gnxpm_cdc.wr_pntr_bin[3]_i_2 \n (.I0(Q_reg[9]),\n .I1(Q_reg[8]),\n .I2(Q_reg[7]),\n .I3(Q_reg[6]),\n .O(\\gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h6996966996696996)) \n \\gnxpm_cdc.wr_pntr_bin[4]_i_1 \n (.I0(Q_reg[10]),\n .I1(Q_reg[4]),\n .I2(Q_reg[5]),\n .I3(\\gnxpm_cdc.wr_pntr_bin[4]_i_2_n_0 ),\n .I4(Q_reg[8]),\n .I5(Q_reg[9]),\n .O(\\gnxpm_cdc.wr_pntr_bin_reg[9] [2]));\n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.wr_pntr_bin[4]_i_2 \n (.I0(Q_reg[6]),\n .I1(Q_reg[7]),\n .O(\\gnxpm_cdc.wr_pntr_bin[4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h6996966996696996)) \n \\gnxpm_cdc.wr_pntr_bin[5]_i_1 \n (.I0(Q_reg[7]),\n .I1(Q_reg[5]),\n .I2(Q_reg[6]),\n .I3(Q_reg[10]),\n .I4(Q_reg[8]),\n .I5(Q_reg[9]),\n .O(\\gnxpm_cdc.wr_pntr_bin_reg[9] [3]));\n LUT5 #(\n .INIT(32'h96696996)) \n \\gnxpm_cdc.wr_pntr_bin[6]_i_1 \n (.I0(Q_reg[8]),\n .I1(Q_reg[6]),\n .I2(Q_reg[7]),\n .I3(Q_reg[10]),\n .I4(Q_reg[9]),\n .O(\\gnxpm_cdc.wr_pntr_bin_reg[9] [4]));\n LUT4 #(\n .INIT(16'h6996)) \n \\gnxpm_cdc.wr_pntr_bin[7]_i_1 \n (.I0(Q_reg[8]),\n .I1(Q_reg[7]),\n .I2(Q_reg[10]),\n .I3(Q_reg[9]),\n .O(\\gnxpm_cdc.wr_pntr_bin_reg[9] [5]));\n LUT3 #(\n .INIT(8'h96)) \n \\gnxpm_cdc.wr_pntr_bin[8]_i_1 \n (.I0(Q_reg[9]),\n .I1(Q_reg[8]),\n .I2(Q_reg[10]),\n .O(\\gnxpm_cdc.wr_pntr_bin_reg[9] [6]));\n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.wr_pntr_bin[9]_i_1 \n (.I0(Q_reg[9]),\n .I1(Q_reg[10]),\n .O(\\gnxpm_cdc.wr_pntr_bin_reg[9] [7]));\nendmodule\n\n(* ORIG_REF_NAME = \"synchronizer_ff\" *) \nmodule fb_input_fifo_synchronizer_ff__parameterized3\n (out,\n \\gnxpm_cdc.rd_pntr_bin_reg[7] ,\n D,\n wr_clk,\n AR);\n output [0:0]out;\n output [7:0]\\gnxpm_cdc.rd_pntr_bin_reg[7] ;\n input [8:0]D;\n input wr_clk;\n input [0:0]AR;\n\n wire [0:0]AR;\n wire [8:0]D;\n (* async_reg = \"true\" *) (* msgon = \"true\" *) wire [8:0]Q_reg;\n wire \\gnxpm_cdc.rd_pntr_bin[1]_i_2_n_0 ;\n wire \\gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 ;\n wire [7:0]\\gnxpm_cdc.rd_pntr_bin_reg[7] ;\n wire wr_clk;\n\n assign out[0] = Q_reg[8];\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[0] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(D[0]),\n .Q(Q_reg[0]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[1] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(D[1]),\n .Q(Q_reg[1]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[2] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(D[2]),\n .Q(Q_reg[2]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[3] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(D[3]),\n .Q(Q_reg[3]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[4] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(D[4]),\n .Q(Q_reg[4]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[5] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(D[5]),\n .Q(Q_reg[5]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[6] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(D[6]),\n .Q(Q_reg[6]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[7] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(D[7]),\n .Q(Q_reg[7]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[8] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(D[8]),\n .Q(Q_reg[8]));\n LUT6 #(\n .INIT(64'h6996966996696996)) \n \\gnxpm_cdc.rd_pntr_bin[0]_i_1 \n (.I0(Q_reg[1]),\n .I1(Q_reg[0]),\n .I2(\\gnxpm_cdc.rd_pntr_bin[1]_i_2_n_0 ),\n .I3(Q_reg[3]),\n .I4(Q_reg[2]),\n .I5(Q_reg[8]),\n .O(\\gnxpm_cdc.rd_pntr_bin_reg[7] [0]));\n LUT5 #(\n .INIT(32'h96696996)) \n \\gnxpm_cdc.rd_pntr_bin[1]_i_1 \n (.I0(\\gnxpm_cdc.rd_pntr_bin[1]_i_2_n_0 ),\n .I1(Q_reg[3]),\n .I2(Q_reg[2]),\n .I3(Q_reg[8]),\n .I4(Q_reg[1]),\n .O(\\gnxpm_cdc.rd_pntr_bin_reg[7] [1]));\n LUT4 #(\n .INIT(16'h6996)) \n \\gnxpm_cdc.rd_pntr_bin[1]_i_2 \n (.I0(Q_reg[7]),\n .I1(Q_reg[6]),\n .I2(Q_reg[5]),\n .I3(Q_reg[4]),\n .O(\\gnxpm_cdc.rd_pntr_bin[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h6996966996696996)) \n \\gnxpm_cdc.rd_pntr_bin[2]_i_1 \n (.I0(Q_reg[8]),\n .I1(Q_reg[2]),\n .I2(Q_reg[3]),\n .I3(\\gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 ),\n .I4(Q_reg[6]),\n .I5(Q_reg[7]),\n .O(\\gnxpm_cdc.rd_pntr_bin_reg[7] [2]));\n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.rd_pntr_bin[2]_i_2 \n (.I0(Q_reg[4]),\n .I1(Q_reg[5]),\n .O(\\gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h6996966996696996)) \n \\gnxpm_cdc.rd_pntr_bin[3]_i_1 \n (.I0(Q_reg[5]),\n .I1(Q_reg[3]),\n .I2(Q_reg[4]),\n .I3(Q_reg[8]),\n .I4(Q_reg[6]),\n .I5(Q_reg[7]),\n .O(\\gnxpm_cdc.rd_pntr_bin_reg[7] [3]));\n LUT5 #(\n .INIT(32'h96696996)) \n \\gnxpm_cdc.rd_pntr_bin[4]_i_1 \n (.I0(Q_reg[6]),\n .I1(Q_reg[4]),\n .I2(Q_reg[5]),\n .I3(Q_reg[8]),\n .I4(Q_reg[7]),\n .O(\\gnxpm_cdc.rd_pntr_bin_reg[7] [4]));\n LUT4 #(\n .INIT(16'h6996)) \n \\gnxpm_cdc.rd_pntr_bin[5]_i_1 \n (.I0(Q_reg[6]),\n .I1(Q_reg[5]),\n .I2(Q_reg[8]),\n .I3(Q_reg[7]),\n .O(\\gnxpm_cdc.rd_pntr_bin_reg[7] [5]));\n LUT3 #(\n .INIT(8'h96)) \n \\gnxpm_cdc.rd_pntr_bin[6]_i_1 \n (.I0(Q_reg[7]),\n .I1(Q_reg[6]),\n .I2(Q_reg[8]),\n .O(\\gnxpm_cdc.rd_pntr_bin_reg[7] [6]));\n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.rd_pntr_bin[7]_i_1 \n (.I0(Q_reg[7]),\n .I1(Q_reg[8]),\n .O(\\gnxpm_cdc.rd_pntr_bin_reg[7] [7]));\nendmodule\n\n(* ORIG_REF_NAME = \"wr_bin_cntr\" *) \nmodule fb_input_fifo_wr_bin_cntr\n (\\gic0.gc0.count_d1_reg[10]_0 ,\n v1_reg,\n v1_reg_0,\n Q,\n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram ,\n RD_PNTR_WR,\n E,\n wr_clk,\n AR);\n output [0:0]\\gic0.gc0.count_d1_reg[10]_0 ;\n output [4:0]v1_reg;\n output [4:0]v1_reg_0;\n output [0:0]Q;\n output [10:0]\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram ;\n input [7:0]RD_PNTR_WR;\n input [0:0]E;\n input wr_clk;\n input [0:0]AR;\n\n wire [0:0]AR;\n wire [10:0]\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram ;\n wire [0:0]E;\n wire [0:0]Q;\n wire [7:0]RD_PNTR_WR;\n wire \\gic0.gc0.count[10]_i_2_n_0 ;\n wire [0:0]\\gic0.gc0.count_d1_reg[10]_0 ;\n wire [9:0]p_13_out;\n wire [10:0]plusOp__1;\n wire [4:0]v1_reg;\n wire [4:0]v1_reg_0;\n wire wr_clk;\n wire [9:0]wr_pntr_plus2;\n\n (* SOFT_HLUTNM = \"soft_lutpair15\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gic0.gc0.count[0]_i_1 \n (.I0(wr_pntr_plus2[0]),\n .O(plusOp__1[0]));\n LUT6 #(\n .INIT(64'h7FFFFFFF80000000)) \n \\gic0.gc0.count[10]_i_1 \n (.I0(wr_pntr_plus2[8]),\n .I1(wr_pntr_plus2[6]),\n .I2(\\gic0.gc0.count[10]_i_2_n_0 ),\n .I3(wr_pntr_plus2[7]),\n .I4(wr_pntr_plus2[9]),\n .I5(\\gic0.gc0.count_d1_reg[10]_0 ),\n .O(plusOp__1[10]));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\gic0.gc0.count[10]_i_2 \n (.I0(wr_pntr_plus2[5]),\n .I1(wr_pntr_plus2[3]),\n .I2(wr_pntr_plus2[1]),\n .I3(wr_pntr_plus2[0]),\n .I4(wr_pntr_plus2[2]),\n .I5(wr_pntr_plus2[4]),\n .O(\\gic0.gc0.count[10]_i_2_n_0 ));\n LUT2 #(\n .INIT(4'h6)) \n \\gic0.gc0.count[1]_i_1 \n (.I0(wr_pntr_plus2[0]),\n .I1(wr_pntr_plus2[1]),\n .O(plusOp__1[1]));\n (* SOFT_HLUTNM = \"soft_lutpair15\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\gic0.gc0.count[2]_i_1 \n (.I0(wr_pntr_plus2[0]),\n .I1(wr_pntr_plus2[1]),\n .I2(wr_pntr_plus2[2]),\n .O(plusOp__1[2]));\n (* SOFT_HLUTNM = \"soft_lutpair13\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\gic0.gc0.count[3]_i_1 \n (.I0(wr_pntr_plus2[1]),\n .I1(wr_pntr_plus2[0]),\n .I2(wr_pntr_plus2[2]),\n .I3(wr_pntr_plus2[3]),\n .O(plusOp__1[3]));\n (* SOFT_HLUTNM = \"soft_lutpair13\" *) \n LUT5 #(\n .INIT(32'h7FFF8000)) \n \\gic0.gc0.count[4]_i_1 \n (.I0(wr_pntr_plus2[2]),\n .I1(wr_pntr_plus2[0]),\n .I2(wr_pntr_plus2[1]),\n .I3(wr_pntr_plus2[3]),\n .I4(wr_pntr_plus2[4]),\n .O(plusOp__1[4]));\n LUT6 #(\n .INIT(64'h7FFFFFFF80000000)) \n \\gic0.gc0.count[5]_i_1 \n (.I0(wr_pntr_plus2[3]),\n .I1(wr_pntr_plus2[1]),\n .I2(wr_pntr_plus2[0]),\n .I3(wr_pntr_plus2[2]),\n .I4(wr_pntr_plus2[4]),\n .I5(wr_pntr_plus2[5]),\n .O(plusOp__1[5]));\n (* SOFT_HLUTNM = \"soft_lutpair14\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gic0.gc0.count[6]_i_1 \n (.I0(\\gic0.gc0.count[10]_i_2_n_0 ),\n .I1(wr_pntr_plus2[6]),\n .O(plusOp__1[6]));\n (* SOFT_HLUTNM = \"soft_lutpair14\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\gic0.gc0.count[7]_i_1 \n (.I0(\\gic0.gc0.count[10]_i_2_n_0 ),\n .I1(wr_pntr_plus2[6]),\n .I2(wr_pntr_plus2[7]),\n .O(plusOp__1[7]));\n (* SOFT_HLUTNM = \"soft_lutpair12\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\gic0.gc0.count[8]_i_1 \n (.I0(wr_pntr_plus2[6]),\n .I1(\\gic0.gc0.count[10]_i_2_n_0 ),\n .I2(wr_pntr_plus2[7]),\n .I3(wr_pntr_plus2[8]),\n .O(plusOp__1[8]));\n (* SOFT_HLUTNM = \"soft_lutpair12\" *) \n LUT5 #(\n .INIT(32'h7FFF8000)) \n \\gic0.gc0.count[9]_i_1 \n (.I0(wr_pntr_plus2[7]),\n .I1(\\gic0.gc0.count[10]_i_2_n_0 ),\n .I2(wr_pntr_plus2[6]),\n .I3(wr_pntr_plus2[8]),\n .I4(wr_pntr_plus2[9]),\n .O(plusOp__1[9]));\n FDPE #(\n .INIT(1'b1)) \n \\gic0.gc0.count_d1_reg[0] \n (.C(wr_clk),\n .CE(E),\n .D(wr_pntr_plus2[0]),\n .PRE(AR),\n .Q(p_13_out[0]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d1_reg[10] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(\\gic0.gc0.count_d1_reg[10]_0 ),\n .Q(Q));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d1_reg[1] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(wr_pntr_plus2[1]),\n .Q(p_13_out[1]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d1_reg[2] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(wr_pntr_plus2[2]),\n .Q(p_13_out[2]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d1_reg[3] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(wr_pntr_plus2[3]),\n .Q(p_13_out[3]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d1_reg[4] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(wr_pntr_plus2[4]),\n .Q(p_13_out[4]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d1_reg[5] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(wr_pntr_plus2[5]),\n .Q(p_13_out[5]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d1_reg[6] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(wr_pntr_plus2[6]),\n .Q(p_13_out[6]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d1_reg[7] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(wr_pntr_plus2[7]),\n .Q(p_13_out[7]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d1_reg[8] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(wr_pntr_plus2[8]),\n .Q(p_13_out[8]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d1_reg[9] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(wr_pntr_plus2[9]),\n .Q(p_13_out[9]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d2_reg[0] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(p_13_out[0]),\n .Q(\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram [0]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d2_reg[10] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(Q),\n .Q(\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram [10]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d2_reg[1] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(p_13_out[1]),\n .Q(\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram [1]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d2_reg[2] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(p_13_out[2]),\n .Q(\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram [2]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d2_reg[3] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(p_13_out[3]),\n .Q(\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram [3]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d2_reg[4] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(p_13_out[4]),\n .Q(\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram [4]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d2_reg[5] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(p_13_out[5]),\n .Q(\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram [5]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d2_reg[6] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(p_13_out[6]),\n .Q(\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram [6]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d2_reg[7] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(p_13_out[7]),\n .Q(\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram [7]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d2_reg[8] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(p_13_out[8]),\n .Q(\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram [8]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d2_reg[9] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(p_13_out[9]),\n .Q(\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram [9]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_reg[0] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__1[0]),\n .Q(wr_pntr_plus2[0]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_reg[10] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__1[10]),\n .Q(\\gic0.gc0.count_d1_reg[10]_0 ));\n FDPE #(\n .INIT(1'b1)) \n \\gic0.gc0.count_reg[1] \n (.C(wr_clk),\n .CE(E),\n .D(plusOp__1[1]),\n .PRE(AR),\n .Q(wr_pntr_plus2[1]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_reg[2] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__1[2]),\n .Q(wr_pntr_plus2[2]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_reg[3] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__1[3]),\n .Q(wr_pntr_plus2[3]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_reg[4] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__1[4]),\n .Q(wr_pntr_plus2[4]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_reg[5] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__1[5]),\n .Q(wr_pntr_plus2[5]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_reg[6] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__1[6]),\n .Q(wr_pntr_plus2[6]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_reg[7] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__1[7]),\n .Q(wr_pntr_plus2[7]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_reg[8] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__1[8]),\n .Q(wr_pntr_plus2[8]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_reg[9] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__1[9]),\n .Q(wr_pntr_plus2[9]));\n LUT2 #(\n .INIT(4'h1)) \n \\gmux.gm[0].gm1.m1_i_1__1 \n (.I0(p_13_out[0]),\n .I1(p_13_out[1]),\n .O(v1_reg[0]));\n LUT2 #(\n .INIT(4'h1)) \n \\gmux.gm[0].gm1.m1_i_1__2 \n (.I0(wr_pntr_plus2[0]),\n .I1(wr_pntr_plus2[1]),\n .O(v1_reg_0[0]));\n LUT4 #(\n .INIT(16'h9009)) \n \\gmux.gm[1].gms.ms_i_1__1 \n (.I0(p_13_out[2]),\n .I1(RD_PNTR_WR[0]),\n .I2(p_13_out[3]),\n .I3(RD_PNTR_WR[1]),\n .O(v1_reg[1]));\n LUT4 #(\n .INIT(16'h9009)) \n \\gmux.gm[1].gms.ms_i_1__2 \n (.I0(wr_pntr_plus2[2]),\n .I1(RD_PNTR_WR[0]),\n .I2(wr_pntr_plus2[3]),\n .I3(RD_PNTR_WR[1]),\n .O(v1_reg_0[1]));\n LUT4 #(\n .INIT(16'h9009)) \n \\gmux.gm[2].gms.ms_i_1__1 \n (.I0(p_13_out[4]),\n .I1(RD_PNTR_WR[2]),\n .I2(p_13_out[5]),\n .I3(RD_PNTR_WR[3]),\n .O(v1_reg[2]));\n LUT4 #(\n .INIT(16'h9009)) \n \\gmux.gm[2].gms.ms_i_1__2 \n (.I0(wr_pntr_plus2[4]),\n .I1(RD_PNTR_WR[2]),\n .I2(wr_pntr_plus2[5]),\n .I3(RD_PNTR_WR[3]),\n .O(v1_reg_0[2]));\n LUT4 #(\n .INIT(16'h9009)) \n \\gmux.gm[3].gms.ms_i_1__1 \n (.I0(p_13_out[6]),\n .I1(RD_PNTR_WR[4]),\n .I2(p_13_out[7]),\n .I3(RD_PNTR_WR[5]),\n .O(v1_reg[3]));\n LUT4 #(\n .INIT(16'h9009)) \n \\gmux.gm[3].gms.ms_i_1__2 \n (.I0(wr_pntr_plus2[6]),\n .I1(RD_PNTR_WR[4]),\n .I2(wr_pntr_plus2[7]),\n .I3(RD_PNTR_WR[5]),\n .O(v1_reg_0[3]));\n LUT4 #(\n .INIT(16'h9009)) \n \\gmux.gm[4].gms.ms_i_1 \n (.I0(p_13_out[8]),\n .I1(RD_PNTR_WR[6]),\n .I2(p_13_out[9]),\n .I3(RD_PNTR_WR[7]),\n .O(v1_reg[4]));\n LUT4 #(\n .INIT(16'h9009)) \n \\gmux.gm[4].gms.ms_i_1__0 \n (.I0(wr_pntr_plus2[8]),\n .I1(RD_PNTR_WR[6]),\n .I2(wr_pntr_plus2[9]),\n .I3(RD_PNTR_WR[7]),\n .O(v1_reg_0[4]));\nendmodule\n\n(* ORIG_REF_NAME = \"wr_logic\" *) \nmodule fb_input_fifo_wr_logic\n (full,\n \\gic0.gc0.count_d1_reg[10] ,\n Q,\n \\gic0.gc0.count_d1_reg[10]_0 ,\n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram ,\n \\gnxpm_cdc.rd_pntr_bin_reg[8] ,\n \\gnxpm_cdc.rd_pntr_bin_reg[8]_0 ,\n wr_clk,\n out,\n wr_en,\n AR,\n RD_PNTR_WR,\n wr_rst_busy);\n output full;\n output \\gic0.gc0.count_d1_reg[10] ;\n output [0:0]Q;\n output [0:0]\\gic0.gc0.count_d1_reg[10]_0 ;\n output [10:0]\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram ;\n input \\gnxpm_cdc.rd_pntr_bin_reg[8] ;\n input \\gnxpm_cdc.rd_pntr_bin_reg[8]_0 ;\n input wr_clk;\n input out;\n input wr_en;\n input [0:0]AR;\n input [7:0]RD_PNTR_WR;\n input wr_rst_busy;\n\n wire [0:0]AR;\n wire [10:0]\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram ;\n wire [0:0]Q;\n wire [7:0]RD_PNTR_WR;\n wire [4:0]\\c1/v1_reg ;\n wire [4:0]\\c2/v1_reg ;\n wire full;\n wire \\gic0.gc0.count_d1_reg[10] ;\n wire [0:0]\\gic0.gc0.count_d1_reg[10]_0 ;\n wire \\gnxpm_cdc.rd_pntr_bin_reg[8] ;\n wire \\gnxpm_cdc.rd_pntr_bin_reg[8]_0 ;\n wire out;\n wire wr_clk;\n wire wr_en;\n wire wr_rst_busy;\n\n fb_input_fifo_wr_status_flags_as \\gwas.wsts \n (.E(\\gic0.gc0.count_d1_reg[10] ),\n .full(full),\n .\\gnxpm_cdc.rd_pntr_bin_reg[8] (\\gnxpm_cdc.rd_pntr_bin_reg[8] ),\n .\\gnxpm_cdc.rd_pntr_bin_reg[8]_0 (\\gnxpm_cdc.rd_pntr_bin_reg[8]_0 ),\n .out(out),\n .v1_reg(\\c1/v1_reg ),\n .v1_reg_0(\\c2/v1_reg ),\n .wr_clk(wr_clk),\n .wr_en(wr_en),\n .wr_rst_busy(wr_rst_busy));\n fb_input_fifo_wr_bin_cntr wpntr\n (.AR(AR),\n .\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram (\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram ),\n .E(\\gic0.gc0.count_d1_reg[10] ),\n .Q(Q),\n .RD_PNTR_WR(RD_PNTR_WR),\n .\\gic0.gc0.count_d1_reg[10]_0 (\\gic0.gc0.count_d1_reg[10]_0 ),\n .v1_reg(\\c1/v1_reg ),\n .v1_reg_0(\\c2/v1_reg ),\n .wr_clk(wr_clk));\nendmodule\n\n(* ORIG_REF_NAME = \"wr_status_flags_as\" *) \nmodule fb_input_fifo_wr_status_flags_as\n (full,\n E,\n v1_reg,\n \\gnxpm_cdc.rd_pntr_bin_reg[8] ,\n v1_reg_0,\n \\gnxpm_cdc.rd_pntr_bin_reg[8]_0 ,\n wr_clk,\n out,\n wr_en,\n wr_rst_busy);\n output full;\n output [0:0]E;\n input [4:0]v1_reg;\n input \\gnxpm_cdc.rd_pntr_bin_reg[8] ;\n input [4:0]v1_reg_0;\n input \\gnxpm_cdc.rd_pntr_bin_reg[8]_0 ;\n input wr_clk;\n input out;\n input wr_en;\n input wr_rst_busy;\n\n wire [0:0]E;\n wire c2_n_0;\n wire comp1;\n wire \\gnxpm_cdc.rd_pntr_bin_reg[8] ;\n wire \\gnxpm_cdc.rd_pntr_bin_reg[8]_0 ;\n wire out;\n (* DONT_TOUCH *) wire ram_full_fb_i;\n (* DONT_TOUCH *) wire ram_full_i;\n wire [4:0]v1_reg;\n wire [4:0]v1_reg_0;\n wire wr_clk;\n wire wr_en;\n wire wr_rst_busy;\n\n assign full = ram_full_i;\n LUT2 #(\n .INIT(4'h2)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram_i_2 \n (.I0(wr_en),\n .I1(ram_full_fb_i),\n .O(E));\n fb_input_fifo_compare__parameterized0 c1\n (.comp1(comp1),\n .\\gnxpm_cdc.rd_pntr_bin_reg[8] (\\gnxpm_cdc.rd_pntr_bin_reg[8] ),\n .v1_reg(v1_reg));\n fb_input_fifo_compare__parameterized1 c2\n (.comp1(comp1),\n .\\gnxpm_cdc.rd_pntr_bin_reg[8] (\\gnxpm_cdc.rd_pntr_bin_reg[8]_0 ),\n .out(ram_full_fb_i),\n .ram_full_fb_i_reg(c2_n_0),\n .v1_reg_0(v1_reg_0),\n .wr_en(wr_en),\n .wr_rst_busy(wr_rst_busy));\n (* DONT_TOUCH *) \n (* KEEP = \"yes\" *) \n (* equivalent_register_removal = \"no\" *) \n FDPE #(\n .INIT(1'b1)) \n ram_full_fb_i_reg\n (.C(wr_clk),\n .CE(1'b1),\n .D(c2_n_0),\n .PRE(out),\n .Q(ram_full_fb_i));\n (* DONT_TOUCH *) \n (* KEEP = \"yes\" *) \n (* equivalent_register_removal = \"no\" *) \n FDPE #(\n .INIT(1'b1)) \n ram_full_i_reg\n (.C(wr_clk),\n .CE(1'b1),\n .D(c2_n_0),\n .PRE(out),\n .Q(ram_full_i));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_generic_cstr\" *) \nmodule fb_output_fifo_blk_mem_gen_generic_cstr\n (dout,\n rd_clk,\n wr_clk,\n tmp_ram_rd_en,\n WEBWE,\n out,\n Q,\n \\gic0.gc0.count_d2_reg[8] ,\n din);\n output [31:0]dout;\n input rd_clk;\n input wr_clk;\n input tmp_ram_rd_en;\n input [0:0]WEBWE;\n input [0:0]out;\n input [10:0]Q;\n input [8:0]\\gic0.gc0.count_d2_reg[8] ;\n input [127:0]din;\n\n wire [10:0]Q;\n wire [0:0]WEBWE;\n wire [127:0]din;\n wire [31:0]dout;\n wire [8:0]\\gic0.gc0.count_d2_reg[8] ;\n wire [0:0]out;\n wire rd_clk;\n wire tmp_ram_rd_en;\n wire wr_clk;\n\n fb_output_fifo_blk_mem_gen_prim_width \\ramloop[0].ram.r \n (.Q(Q),\n .WEBWE(WEBWE),\n .din({din[113:96],din[81:64],din[49:32],din[17:0]}),\n .dout(dout[17:0]),\n .\\gic0.gc0.count_d2_reg[8] (\\gic0.gc0.count_d2_reg[8] ),\n .out(out),\n .rd_clk(rd_clk),\n .tmp_ram_rd_en(tmp_ram_rd_en),\n .wr_clk(wr_clk));\n fb_output_fifo_blk_mem_gen_prim_width__parameterized0 \\ramloop[1].ram.r \n (.Q(Q),\n .WEBWE(WEBWE),\n .din({din[127:114],din[95:82],din[63:50],din[31:18]}),\n .dout(dout[31:18]),\n .\\gic0.gc0.count_d2_reg[8] (\\gic0.gc0.count_d2_reg[8] ),\n .out(out),\n .rd_clk(rd_clk),\n .tmp_ram_rd_en(tmp_ram_rd_en),\n .wr_clk(wr_clk));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule fb_output_fifo_blk_mem_gen_prim_width\n (dout,\n rd_clk,\n wr_clk,\n tmp_ram_rd_en,\n WEBWE,\n out,\n Q,\n \\gic0.gc0.count_d2_reg[8] ,\n din);\n output [17:0]dout;\n input rd_clk;\n input wr_clk;\n input tmp_ram_rd_en;\n input [0:0]WEBWE;\n input [0:0]out;\n input [10:0]Q;\n input [8:0]\\gic0.gc0.count_d2_reg[8] ;\n input [71:0]din;\n\n wire [10:0]Q;\n wire [0:0]WEBWE;\n wire [71:0]din;\n wire [17:0]dout;\n wire [8:0]\\gic0.gc0.count_d2_reg[8] ;\n wire [0:0]out;\n wire rd_clk;\n wire tmp_ram_rd_en;\n wire wr_clk;\n\n fb_output_fifo_blk_mem_gen_prim_wrapper \\prim_noinit.ram \n (.Q(Q),\n .WEBWE(WEBWE),\n .din(din),\n .dout(dout),\n .\\gic0.gc0.count_d2_reg[8] (\\gic0.gc0.count_d2_reg[8] ),\n .out(out),\n .rd_clk(rd_clk),\n .tmp_ram_rd_en(tmp_ram_rd_en),\n .wr_clk(wr_clk));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule fb_output_fifo_blk_mem_gen_prim_width__parameterized0\n (dout,\n rd_clk,\n wr_clk,\n tmp_ram_rd_en,\n WEBWE,\n out,\n Q,\n \\gic0.gc0.count_d2_reg[8] ,\n din);\n output [13:0]dout;\n input rd_clk;\n input wr_clk;\n input tmp_ram_rd_en;\n input [0:0]WEBWE;\n input [0:0]out;\n input [10:0]Q;\n input [8:0]\\gic0.gc0.count_d2_reg[8] ;\n input [55:0]din;\n\n wire [10:0]Q;\n wire [0:0]WEBWE;\n wire [55:0]din;\n wire [13:0]dout;\n wire [8:0]\\gic0.gc0.count_d2_reg[8] ;\n wire [0:0]out;\n wire rd_clk;\n wire tmp_ram_rd_en;\n wire wr_clk;\n\n fb_output_fifo_blk_mem_gen_prim_wrapper__parameterized0 \\prim_noinit.ram \n (.Q(Q),\n .WEBWE(WEBWE),\n .din(din),\n .dout(dout),\n .\\gic0.gc0.count_d2_reg[8] (\\gic0.gc0.count_d2_reg[8] ),\n .out(out),\n .rd_clk(rd_clk),\n .tmp_ram_rd_en(tmp_ram_rd_en),\n .wr_clk(wr_clk));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule fb_output_fifo_blk_mem_gen_prim_wrapper\n (dout,\n rd_clk,\n wr_clk,\n tmp_ram_rd_en,\n WEBWE,\n out,\n Q,\n \\gic0.gc0.count_d2_reg[8] ,\n din);\n output [17:0]dout;\n input rd_clk;\n input wr_clk;\n input tmp_ram_rd_en;\n input [0:0]WEBWE;\n input [0:0]out;\n input [10:0]Q;\n input [8:0]\\gic0.gc0.count_d2_reg[8] ;\n input [71:0]din;\n\n wire [10:0]Q;\n wire [0:0]WEBWE;\n wire [71:0]din;\n wire [17:0]dout;\n wire [8:0]\\gic0.gc0.count_d2_reg[8] ;\n wire [0:0]out;\n wire rd_clk;\n wire tmp_ram_rd_en;\n wire wr_clk;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED ;\n wire [31:16]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DOADO_UNCONNECTED ;\n wire [31:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DOBDO_UNCONNECTED ;\n wire [3:2]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DOPADOP_UNCONNECTED ;\n wire [3:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DOPBDOP_UNCONNECTED ;\n wire [7:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED ;\n wire [8:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB36E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .EN_ECC_READ(\"FALSE\"),\n .EN_ECC_WRITE(\"FALSE\"),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(36'h000000000),\n .INIT_B(36'h000000000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_EXTENSION_A(\"NONE\"),\n .RAM_EXTENSION_B(\"NONE\"),\n .RAM_MODE(\"SDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(18),\n .READ_WIDTH_B(0),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(36'h000000000),\n .SRVAL_B(36'h000000000),\n .WRITE_MODE_A(\"WRITE_FIRST\"),\n .WRITE_MODE_B(\"WRITE_FIRST\"),\n .WRITE_WIDTH_A(0),\n .WRITE_WIDTH_B(72)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram \n (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1,1'b1}),\n .ADDRBWRADDR({1'b1,\\gic0.gc0.count_d2_reg[8] ,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .CASCADEINA(1'b0),\n .CASCADEINB(1'b0),\n .CASCADEOUTA(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED ),\n .CASCADEOUTB(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED ),\n .CLKARDCLK(rd_clk),\n .CLKBWRCLK(wr_clk),\n .DBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED ),\n .DIADI({din[52:45],din[43:36],din[70:63],din[61:54]}),\n .DIBDI({din[16:9],din[7:0],din[34:27],din[25:18]}),\n .DIPADIP({din[53],din[44],din[71],din[62]}),\n .DIPBDIP({din[17],din[8],din[35],din[26]}),\n .DOADO({\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DOADO_UNCONNECTED [31:16],dout[16:9],dout[7:0]}),\n .DOBDO(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DOBDO_UNCONNECTED [31:0]),\n .DOPADOP({\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DOPADOP_UNCONNECTED [3:2],dout[17],dout[8]}),\n .DOPBDOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DOPBDOP_UNCONNECTED [3:0]),\n .ECCPARITY(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED [7:0]),\n .ENARDEN(tmp_ram_rd_en),\n .ENBWREN(WEBWE),\n .INJECTDBITERR(1'b0),\n .INJECTSBITERR(1'b0),\n .RDADDRECC(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED [8:0]),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(out),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .SBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED ),\n .WEA({1'b0,1'b0,1'b0,1'b0}),\n .WEBWE({WEBWE,WEBWE,WEBWE,WEBWE,WEBWE,WEBWE,WEBWE,WEBWE}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule fb_output_fifo_blk_mem_gen_prim_wrapper__parameterized0\n (dout,\n rd_clk,\n wr_clk,\n tmp_ram_rd_en,\n WEBWE,\n out,\n Q,\n \\gic0.gc0.count_d2_reg[8] ,\n din);\n output [13:0]dout;\n input rd_clk;\n input wr_clk;\n input tmp_ram_rd_en;\n input [0:0]WEBWE;\n input [0:0]out;\n input [10:0]Q;\n input [8:0]\\gic0.gc0.count_d2_reg[8] ;\n input [55:0]din;\n\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_37 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_45 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_88 ;\n wire [10:0]Q;\n wire [0:0]WEBWE;\n wire [55:0]din;\n wire [13:0]dout;\n wire [8:0]\\gic0.gc0.count_d2_reg[8] ;\n wire [0:0]out;\n wire rd_clk;\n wire tmp_ram_rd_en;\n wire wr_clk;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED ;\n wire [31:16]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DOADO_UNCONNECTED ;\n wire [31:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DOBDO_UNCONNECTED ;\n wire [3:2]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DOPADOP_UNCONNECTED ;\n wire [3:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DOPBDOP_UNCONNECTED ;\n wire [7:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED ;\n wire [8:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB36E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .EN_ECC_READ(\"FALSE\"),\n .EN_ECC_WRITE(\"FALSE\"),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(36'h000000000),\n .INIT_B(36'h000000000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_EXTENSION_A(\"NONE\"),\n .RAM_EXTENSION_B(\"NONE\"),\n .RAM_MODE(\"SDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(18),\n .READ_WIDTH_B(0),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(36'h000000000),\n .SRVAL_B(36'h000000000),\n .WRITE_MODE_A(\"WRITE_FIRST\"),\n .WRITE_MODE_B(\"WRITE_FIRST\"),\n .WRITE_WIDTH_A(0),\n .WRITE_WIDTH_B(72)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram \n (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1,1'b1}),\n .ADDRBWRADDR({1'b1,\\gic0.gc0.count_d2_reg[8] ,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .CASCADEINA(1'b0),\n .CASCADEINB(1'b0),\n .CASCADEOUTA(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED ),\n .CASCADEOUTB(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED ),\n .CLKARDCLK(rd_clk),\n .CLKBWRCLK(wr_clk),\n .DBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED ),\n .DIADI({1'b0,din[41:35],1'b0,din[34:28],1'b0,din[55:49],1'b0,din[48:42]}),\n .DIBDI({1'b0,din[13:7],1'b0,din[6:0],1'b0,din[27:21],1'b0,din[20:14]}),\n .DIPADIP({1'b0,1'b0,1'b0,1'b0}),\n .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),\n .DOADO({\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DOADO_UNCONNECTED [31:16],\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_37 ,dout[13:7],\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_45 ,dout[6:0]}),\n .DOBDO(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DOBDO_UNCONNECTED [31:0]),\n .DOPADOP({\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DOPADOP_UNCONNECTED [3:2],\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_88 }),\n .DOPBDOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DOPBDOP_UNCONNECTED [3:0]),\n .ECCPARITY(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED [7:0]),\n .ENARDEN(tmp_ram_rd_en),\n .ENBWREN(WEBWE),\n .INJECTDBITERR(1'b0),\n .INJECTSBITERR(1'b0),\n .RDADDRECC(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED [8:0]),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(out),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .SBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED ),\n .WEA({1'b0,1'b0,1'b0,1'b0}),\n .WEBWE({WEBWE,WEBWE,WEBWE,WEBWE,WEBWE,WEBWE,WEBWE,WEBWE}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_top\" *) \nmodule fb_output_fifo_blk_mem_gen_top\n (dout,\n rd_clk,\n wr_clk,\n tmp_ram_rd_en,\n WEBWE,\n out,\n Q,\n \\gic0.gc0.count_d2_reg[8] ,\n din);\n output [31:0]dout;\n input rd_clk;\n input wr_clk;\n input tmp_ram_rd_en;\n input [0:0]WEBWE;\n input [0:0]out;\n input [10:0]Q;\n input [8:0]\\gic0.gc0.count_d2_reg[8] ;\n input [127:0]din;\n\n wire [10:0]Q;\n wire [0:0]WEBWE;\n wire [127:0]din;\n wire [31:0]dout;\n wire [8:0]\\gic0.gc0.count_d2_reg[8] ;\n wire [0:0]out;\n wire rd_clk;\n wire tmp_ram_rd_en;\n wire wr_clk;\n\n fb_output_fifo_blk_mem_gen_generic_cstr \\valid.cstr \n (.Q(Q),\n .WEBWE(WEBWE),\n .din(din),\n .dout(dout),\n .\\gic0.gc0.count_d2_reg[8] (\\gic0.gc0.count_d2_reg[8] ),\n .out(out),\n .rd_clk(rd_clk),\n .tmp_ram_rd_en(tmp_ram_rd_en),\n .wr_clk(wr_clk));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_v8_3_4\" *) \nmodule fb_output_fifo_blk_mem_gen_v8_3_4\n (dout,\n rd_clk,\n wr_clk,\n tmp_ram_rd_en,\n WEBWE,\n out,\n Q,\n \\gic0.gc0.count_d2_reg[8] ,\n din);\n output [31:0]dout;\n input rd_clk;\n input wr_clk;\n input tmp_ram_rd_en;\n input [0:0]WEBWE;\n input [0:0]out;\n input [10:0]Q;\n input [8:0]\\gic0.gc0.count_d2_reg[8] ;\n input [127:0]din;\n\n wire [10:0]Q;\n wire [0:0]WEBWE;\n wire [127:0]din;\n wire [31:0]dout;\n wire [8:0]\\gic0.gc0.count_d2_reg[8] ;\n wire [0:0]out;\n wire rd_clk;\n wire tmp_ram_rd_en;\n wire wr_clk;\n\n fb_output_fifo_blk_mem_gen_v8_3_4_synth inst_blk_mem_gen\n (.Q(Q),\n .WEBWE(WEBWE),\n .din(din),\n .dout(dout),\n .\\gic0.gc0.count_d2_reg[8] (\\gic0.gc0.count_d2_reg[8] ),\n .out(out),\n .rd_clk(rd_clk),\n .tmp_ram_rd_en(tmp_ram_rd_en),\n .wr_clk(wr_clk));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_v8_3_4_synth\" *) \nmodule fb_output_fifo_blk_mem_gen_v8_3_4_synth\n (dout,\n rd_clk,\n wr_clk,\n tmp_ram_rd_en,\n WEBWE,\n out,\n Q,\n \\gic0.gc0.count_d2_reg[8] ,\n din);\n output [31:0]dout;\n input rd_clk;\n input wr_clk;\n input tmp_ram_rd_en;\n input [0:0]WEBWE;\n input [0:0]out;\n input [10:0]Q;\n input [8:0]\\gic0.gc0.count_d2_reg[8] ;\n input [127:0]din;\n\n wire [10:0]Q;\n wire [0:0]WEBWE;\n wire [127:0]din;\n wire [31:0]dout;\n wire [8:0]\\gic0.gc0.count_d2_reg[8] ;\n wire [0:0]out;\n wire rd_clk;\n wire tmp_ram_rd_en;\n wire wr_clk;\n\n fb_output_fifo_blk_mem_gen_top \\gnbram.gnativebmg.native_blk_mem_gen \n (.Q(Q),\n .WEBWE(WEBWE),\n .din(din),\n .dout(dout),\n .\\gic0.gc0.count_d2_reg[8] (\\gic0.gc0.count_d2_reg[8] ),\n .out(out),\n .rd_clk(rd_clk),\n .tmp_ram_rd_en(tmp_ram_rd_en),\n .wr_clk(wr_clk));\nendmodule\n\n(* ORIG_REF_NAME = \"clk_x_pntrs\" *) \nmodule fb_output_fifo_clk_x_pntrs\n (ram_full_fb_i_reg,\n RD_PNTR_WR,\n ram_full_fb_i_reg_0,\n v1_reg,\n WR_PNTR_RD,\n v1_reg_0,\n Q,\n D,\n \\gc0.count_d1_reg[10] ,\n \\gc0.count_reg[9] ,\n \\gic0.gc0.count_d2_reg[8] ,\n wr_clk,\n AR,\n rd_clk,\n \\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );\n output ram_full_fb_i_reg;\n output [8:0]RD_PNTR_WR;\n output ram_full_fb_i_reg_0;\n output [3:0]v1_reg;\n output [0:0]WR_PNTR_RD;\n output [3:0]v1_reg_0;\n input [0:0]Q;\n input [0:0]D;\n input [10:0]\\gc0.count_d1_reg[10] ;\n input [7:0]\\gc0.count_reg[9] ;\n input [8:0]\\gic0.gc0.count_d2_reg[8] ;\n input wr_clk;\n input [0:0]AR;\n input rd_clk;\n input [0:0]\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;\n\n wire [0:0]AR;\n wire [0:0]D;\n wire [0:0]Q;\n wire [8:0]RD_PNTR_WR;\n wire [0:0]WR_PNTR_RD;\n wire [7:0]bin2gray;\n wire [10:0]\\gc0.count_d1_reg[10] ;\n wire [7:0]\\gc0.count_reg[9] ;\n wire [8:0]\\gic0.gc0.count_d2_reg[8] ;\n wire \\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ;\n wire \\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ;\n wire \\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ;\n wire \\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ;\n wire \\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ;\n wire \\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ;\n wire \\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ;\n wire \\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ;\n wire \\gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 ;\n wire \\gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 ;\n wire \\gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 ;\n wire \\gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 ;\n wire \\gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 ;\n wire \\gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 ;\n wire \\gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 ;\n wire \\gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 ;\n wire \\gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0 ;\n wire \\gnxpm_cdc.rd_pntr_gc[9]_i_1_n_0 ;\n wire [6:0]gray2bin;\n wire [0:0]\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;\n wire p_0_out;\n wire [7:0]p_22_out;\n wire [8:0]p_3_out;\n wire [10:0]p_4_out;\n wire [8:8]p_5_out;\n wire [10:10]p_6_out;\n wire ram_full_fb_i_reg;\n wire ram_full_fb_i_reg_0;\n wire rd_clk;\n wire [10:0]rd_pntr_gc;\n wire [3:0]v1_reg;\n wire [3:0]v1_reg_0;\n wire wr_clk;\n wire [8:0]wr_pntr_gc;\n\n LUT4 #(\n .INIT(16'h9009)) \n \\gmux.gm[1].gms.ms_i_1 \n (.I0(p_22_out[0]),\n .I1(\\gc0.count_d1_reg[10] [2]),\n .I2(p_22_out[1]),\n .I3(\\gc0.count_d1_reg[10] [3]),\n .O(v1_reg[0]));\n LUT4 #(\n .INIT(16'h9009)) \n \\gmux.gm[1].gms.ms_i_1__0 \n (.I0(p_22_out[0]),\n .I1(\\gc0.count_reg[9] [0]),\n .I2(p_22_out[1]),\n .I3(\\gc0.count_reg[9] [1]),\n .O(v1_reg_0[0]));\n LUT4 #(\n .INIT(16'h9009)) \n \\gmux.gm[2].gms.ms_i_1 \n (.I0(p_22_out[2]),\n .I1(\\gc0.count_d1_reg[10] [4]),\n .I2(p_22_out[3]),\n .I3(\\gc0.count_d1_reg[10] [5]),\n .O(v1_reg[1]));\n LUT4 #(\n .INIT(16'h9009)) \n \\gmux.gm[2].gms.ms_i_1__0 \n (.I0(p_22_out[2]),\n .I1(\\gc0.count_reg[9] [2]),\n .I2(p_22_out[3]),\n .I3(\\gc0.count_reg[9] [3]),\n .O(v1_reg_0[1]));\n LUT4 #(\n .INIT(16'h9009)) \n \\gmux.gm[3].gms.ms_i_1 \n (.I0(p_22_out[4]),\n .I1(\\gc0.count_d1_reg[10] [6]),\n .I2(p_22_out[5]),\n .I3(\\gc0.count_d1_reg[10] [7]),\n .O(v1_reg[2]));\n LUT4 #(\n .INIT(16'h9009)) \n \\gmux.gm[3].gms.ms_i_1__0 \n (.I0(p_22_out[4]),\n .I1(\\gc0.count_reg[9] [4]),\n .I2(p_22_out[5]),\n .I3(\\gc0.count_reg[9] [5]),\n .O(v1_reg_0[2]));\n LUT4 #(\n .INIT(16'h9009)) \n \\gmux.gm[4].gms.ms_i_1 \n (.I0(p_22_out[6]),\n .I1(\\gc0.count_d1_reg[10] [8]),\n .I2(p_22_out[7]),\n .I3(\\gc0.count_d1_reg[10] [9]),\n .O(v1_reg[3]));\n LUT4 #(\n .INIT(16'h9009)) \n \\gmux.gm[4].gms.ms_i_1__0 \n (.I0(p_22_out[6]),\n .I1(\\gc0.count_reg[9] [6]),\n .I2(p_22_out[7]),\n .I3(\\gc0.count_reg[9] [7]),\n .O(v1_reg_0[3]));\n LUT2 #(\n .INIT(4'h9)) \n \\gmux.gm[4].gms.ms_i_1__1 \n (.I0(RD_PNTR_WR[8]),\n .I1(Q),\n .O(ram_full_fb_i_reg));\n LUT2 #(\n .INIT(4'h9)) \n \\gmux.gm[4].gms.ms_i_1__2 \n (.I0(RD_PNTR_WR[8]),\n .I1(D),\n .O(ram_full_fb_i_reg_0));\n fb_output_fifo_synchronizer_ff__parameterized0 \\gnxpm_cdc.gsync_stage[1].rd_stg_inst \n (.D(p_3_out),\n .Q(wr_pntr_gc),\n .\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .rd_clk(rd_clk));\n fb_output_fifo_synchronizer_ff__parameterized1 \\gnxpm_cdc.gsync_stage[1].wr_stg_inst \n (.AR(AR),\n .D(p_4_out),\n .Q(rd_pntr_gc),\n .wr_clk(wr_clk));\n fb_output_fifo_synchronizer_ff__parameterized2 \\gnxpm_cdc.gsync_stage[2].rd_stg_inst \n (.D(p_3_out),\n .\\gnxpm_cdc.wr_pntr_bin_reg[7] ({p_0_out,gray2bin}),\n .\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .out(p_5_out),\n .rd_clk(rd_clk));\n fb_output_fifo_synchronizer_ff__parameterized3 \\gnxpm_cdc.gsync_stage[2].wr_stg_inst \n (.AR(AR),\n .D(p_4_out),\n .\\gnxpm_cdc.rd_pntr_bin_reg[9] ({\\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ,\\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ,\\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ,\\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ,\\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ,\\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ,\\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ,\\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 }),\n .out(p_6_out),\n .wr_clk(wr_clk));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_bin_reg[10] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(p_6_out),\n .Q(RD_PNTR_WR[8]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_bin_reg[2] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(\\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ),\n .Q(RD_PNTR_WR[0]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_bin_reg[3] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(\\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ),\n .Q(RD_PNTR_WR[1]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_bin_reg[4] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(\\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ),\n .Q(RD_PNTR_WR[2]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_bin_reg[5] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(\\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ),\n .Q(RD_PNTR_WR[3]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_bin_reg[6] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(\\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ),\n .Q(RD_PNTR_WR[4]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_bin_reg[7] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(\\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ),\n .Q(RD_PNTR_WR[5]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_bin_reg[8] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(\\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ),\n .Q(RD_PNTR_WR[6]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_bin_reg[9] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(\\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ),\n .Q(RD_PNTR_WR[7]));\n (* SOFT_HLUTNM = \"soft_lutpair4\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.rd_pntr_gc[0]_i_1 \n (.I0(\\gc0.count_d1_reg[10] [0]),\n .I1(\\gc0.count_d1_reg[10] [1]),\n .O(\\gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair4\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.rd_pntr_gc[1]_i_1 \n (.I0(\\gc0.count_d1_reg[10] [1]),\n .I1(\\gc0.count_d1_reg[10] [2]),\n .O(\\gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair5\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.rd_pntr_gc[2]_i_1 \n (.I0(\\gc0.count_d1_reg[10] [2]),\n .I1(\\gc0.count_d1_reg[10] [3]),\n .O(\\gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair5\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.rd_pntr_gc[3]_i_1 \n (.I0(\\gc0.count_d1_reg[10] [3]),\n .I1(\\gc0.count_d1_reg[10] [4]),\n .O(\\gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair6\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.rd_pntr_gc[4]_i_1 \n (.I0(\\gc0.count_d1_reg[10] [4]),\n .I1(\\gc0.count_d1_reg[10] [5]),\n .O(\\gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair6\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.rd_pntr_gc[5]_i_1 \n (.I0(\\gc0.count_d1_reg[10] [5]),\n .I1(\\gc0.count_d1_reg[10] [6]),\n .O(\\gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair7\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.rd_pntr_gc[6]_i_1 \n (.I0(\\gc0.count_d1_reg[10] [6]),\n .I1(\\gc0.count_d1_reg[10] [7]),\n .O(\\gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair7\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.rd_pntr_gc[7]_i_1 \n (.I0(\\gc0.count_d1_reg[10] [7]),\n .I1(\\gc0.count_d1_reg[10] [8]),\n .O(\\gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair8\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.rd_pntr_gc[8]_i_1 \n (.I0(\\gc0.count_d1_reg[10] [8]),\n .I1(\\gc0.count_d1_reg[10] [9]),\n .O(\\gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair8\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.rd_pntr_gc[9]_i_1 \n (.I0(\\gc0.count_d1_reg[10] [9]),\n .I1(\\gc0.count_d1_reg[10] [10]),\n .O(\\gnxpm_cdc.rd_pntr_gc[9]_i_1_n_0 ));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_gc_reg[0] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(\\gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 ),\n .Q(rd_pntr_gc[0]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_gc_reg[10] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(\\gc0.count_d1_reg[10] [10]),\n .Q(rd_pntr_gc[10]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_gc_reg[1] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(\\gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 ),\n .Q(rd_pntr_gc[1]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_gc_reg[2] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(\\gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 ),\n .Q(rd_pntr_gc[2]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_gc_reg[3] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(\\gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 ),\n .Q(rd_pntr_gc[3]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_gc_reg[4] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(\\gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 ),\n .Q(rd_pntr_gc[4]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_gc_reg[5] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(\\gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 ),\n .Q(rd_pntr_gc[5]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_gc_reg[6] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(\\gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 ),\n .Q(rd_pntr_gc[6]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_gc_reg[7] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(\\gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 ),\n .Q(rd_pntr_gc[7]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_gc_reg[8] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(\\gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0 ),\n .Q(rd_pntr_gc[8]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.rd_pntr_gc_reg[9] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(\\gnxpm_cdc.rd_pntr_gc[9]_i_1_n_0 ),\n .Q(rd_pntr_gc[9]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_bin_reg[0] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(gray2bin[0]),\n .Q(p_22_out[0]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_bin_reg[1] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(gray2bin[1]),\n .Q(p_22_out[1]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_bin_reg[2] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(gray2bin[2]),\n .Q(p_22_out[2]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_bin_reg[3] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(gray2bin[3]),\n .Q(p_22_out[3]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_bin_reg[4] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(gray2bin[4]),\n .Q(p_22_out[4]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_bin_reg[5] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(gray2bin[5]),\n .Q(p_22_out[5]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_bin_reg[6] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(gray2bin[6]),\n .Q(p_22_out[6]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_bin_reg[7] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(p_0_out),\n .Q(p_22_out[7]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_bin_reg[8] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(p_5_out),\n .Q(WR_PNTR_RD));\n (* SOFT_HLUTNM = \"soft_lutpair0\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.wr_pntr_gc[0]_i_1 \n (.I0(\\gic0.gc0.count_d2_reg[8] [0]),\n .I1(\\gic0.gc0.count_d2_reg[8] [1]),\n .O(bin2gray[0]));\n (* SOFT_HLUTNM = \"soft_lutpair0\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.wr_pntr_gc[1]_i_1 \n (.I0(\\gic0.gc0.count_d2_reg[8] [1]),\n .I1(\\gic0.gc0.count_d2_reg[8] [2]),\n .O(bin2gray[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.wr_pntr_gc[2]_i_1 \n (.I0(\\gic0.gc0.count_d2_reg[8] [2]),\n .I1(\\gic0.gc0.count_d2_reg[8] [3]),\n .O(bin2gray[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.wr_pntr_gc[3]_i_1 \n (.I0(\\gic0.gc0.count_d2_reg[8] [3]),\n .I1(\\gic0.gc0.count_d2_reg[8] [4]),\n .O(bin2gray[3]));\n (* SOFT_HLUTNM = \"soft_lutpair2\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.wr_pntr_gc[4]_i_1 \n (.I0(\\gic0.gc0.count_d2_reg[8] [4]),\n .I1(\\gic0.gc0.count_d2_reg[8] [5]),\n .O(bin2gray[4]));\n (* SOFT_HLUTNM = \"soft_lutpair2\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.wr_pntr_gc[5]_i_1 \n (.I0(\\gic0.gc0.count_d2_reg[8] [5]),\n .I1(\\gic0.gc0.count_d2_reg[8] [6]),\n .O(bin2gray[5]));\n (* SOFT_HLUTNM = \"soft_lutpair3\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.wr_pntr_gc[6]_i_1 \n (.I0(\\gic0.gc0.count_d2_reg[8] [6]),\n .I1(\\gic0.gc0.count_d2_reg[8] [7]),\n .O(bin2gray[6]));\n (* SOFT_HLUTNM = \"soft_lutpair3\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.wr_pntr_gc[7]_i_1 \n (.I0(\\gic0.gc0.count_d2_reg[8] [7]),\n .I1(\\gic0.gc0.count_d2_reg[8] [8]),\n .O(bin2gray[7]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_gc_reg[0] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(bin2gray[0]),\n .Q(wr_pntr_gc[0]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_gc_reg[1] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(bin2gray[1]),\n .Q(wr_pntr_gc[1]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_gc_reg[2] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(bin2gray[2]),\n .Q(wr_pntr_gc[2]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_gc_reg[3] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(bin2gray[3]),\n .Q(wr_pntr_gc[3]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_gc_reg[4] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(bin2gray[4]),\n .Q(wr_pntr_gc[4]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_gc_reg[5] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(bin2gray[5]),\n .Q(wr_pntr_gc[5]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_gc_reg[6] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(bin2gray[6]),\n .Q(wr_pntr_gc[6]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_gc_reg[7] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(bin2gray[7]),\n .Q(wr_pntr_gc[7]));\n FDCE #(\n .INIT(1'b0)) \n \\gnxpm_cdc.wr_pntr_gc_reg[8] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(\\gic0.gc0.count_d2_reg[8] [8]),\n .Q(wr_pntr_gc[8]));\nendmodule\n\n(* ORIG_REF_NAME = \"compare\" *) \nmodule fb_output_fifo_compare\n (ram_empty_fb_i_reg,\n v1_reg,\n \\gnxpm_cdc.wr_pntr_bin_reg[6] ,\n \\gc0.count_d1_reg[10] ,\n rd_en,\n out,\n comp1);\n output ram_empty_fb_i_reg;\n input [0:0]v1_reg;\n input [3:0]\\gnxpm_cdc.wr_pntr_bin_reg[6] ;\n input \\gc0.count_d1_reg[10] ;\n input rd_en;\n input out;\n input comp1;\n\n wire carrynet_0;\n wire carrynet_1;\n wire carrynet_2;\n wire carrynet_3;\n wire carrynet_4;\n wire comp0;\n wire comp1;\n wire \\gc0.count_d1_reg[10] ;\n wire [3:0]\\gnxpm_cdc.wr_pntr_bin_reg[6] ;\n wire out;\n wire ram_empty_fb_i_reg;\n wire rd_en;\n wire [0:0]v1_reg;\n wire [3:0]\\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;\n wire [3:2]\\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;\n wire [3:2]\\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;\n wire [3:0]\\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;\n wire [3:2]\\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;\n\n (* XILINX_LEGACY_PRIM = \"(MUXCY,XORCY)\" *) \n (* box_type = \"PRIMITIVE\" *) \n CARRY4 \\gmux.gm[0].gm1.m1_CARRY4 \n (.CI(1'b0),\n .CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),\n .CYINIT(1'b1),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),\n .S({\\gnxpm_cdc.wr_pntr_bin_reg[6] [2:0],v1_reg}));\n (* XILINX_LEGACY_PRIM = \"(MUXCY,XORCY)\" *) \n (* box_type = \"PRIMITIVE\" *) \n CARRY4 \\gmux.gm[4].gms.ms_CARRY4 \n (.CI(carrynet_3),\n .CO({\\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp0,carrynet_4}),\n .CYINIT(1'b0),\n .DI({\\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),\n .O(\\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),\n .S({\\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],\\gc0.count_d1_reg[10] ,\\gnxpm_cdc.wr_pntr_bin_reg[6] [3]}));\n LUT4 #(\n .INIT(16'hAEAA)) \n ram_empty_i_i_1\n (.I0(comp0),\n .I1(rd_en),\n .I2(out),\n .I3(comp1),\n .O(ram_empty_fb_i_reg));\nendmodule\n\n(* ORIG_REF_NAME = \"compare\" *) \nmodule fb_output_fifo_compare_3\n (comp1,\n v1_reg_0,\n \\gnxpm_cdc.wr_pntr_bin_reg[6] ,\n \\gc0.count_reg[10] );\n output comp1;\n input [0:0]v1_reg_0;\n input [3:0]\\gnxpm_cdc.wr_pntr_bin_reg[6] ;\n input \\gc0.count_reg[10] ;\n\n wire carrynet_0;\n wire carrynet_1;\n wire carrynet_2;\n wire carrynet_3;\n wire carrynet_4;\n wire comp1;\n wire \\gc0.count_reg[10] ;\n wire [3:0]\\gnxpm_cdc.wr_pntr_bin_reg[6] ;\n wire [0:0]v1_reg_0;\n wire [3:0]\\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;\n wire [3:2]\\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;\n wire [3:2]\\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;\n wire [3:0]\\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;\n wire [3:2]\\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;\n\n (* XILINX_LEGACY_PRIM = \"(MUXCY,XORCY)\" *) \n (* box_type = \"PRIMITIVE\" *) \n CARRY4 \\gmux.gm[0].gm1.m1_CARRY4 \n (.CI(1'b0),\n .CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),\n .CYINIT(1'b1),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),\n .S({\\gnxpm_cdc.wr_pntr_bin_reg[6] [2:0],v1_reg_0}));\n (* XILINX_LEGACY_PRIM = \"(MUXCY,XORCY)\" *) \n (* box_type = \"PRIMITIVE\" *) \n CARRY4 \\gmux.gm[4].gms.ms_CARRY4 \n (.CI(carrynet_3),\n .CO({\\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp1,carrynet_4}),\n .CYINIT(1'b0),\n .DI({\\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),\n .O(\\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),\n .S({\\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],\\gc0.count_reg[10] ,\\gnxpm_cdc.wr_pntr_bin_reg[6] [3]}));\nendmodule\n\n(* ORIG_REF_NAME = \"compare\" *) \nmodule fb_output_fifo_compare__parameterized0\n (comp1,\n v1_reg,\n \\gnxpm_cdc.rd_pntr_bin_reg[10] );\n output comp1;\n input [3:0]v1_reg;\n input \\gnxpm_cdc.rd_pntr_bin_reg[10] ;\n\n wire carrynet_0;\n wire carrynet_1;\n wire carrynet_2;\n wire carrynet_3;\n wire comp1;\n wire \\gnxpm_cdc.rd_pntr_bin_reg[10] ;\n wire [3:0]v1_reg;\n wire [3:0]\\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;\n wire [3:1]\\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;\n wire [3:1]\\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;\n wire [3:0]\\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;\n wire [3:1]\\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;\n\n (* XILINX_LEGACY_PRIM = \"(MUXCY,XORCY)\" *) \n (* box_type = \"PRIMITIVE\" *) \n CARRY4 \\gmux.gm[0].gm1.m1_CARRY4 \n (.CI(1'b0),\n .CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),\n .CYINIT(1'b1),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),\n .S(v1_reg));\n (* XILINX_LEGACY_PRIM = \"(MUXCY,XORCY)\" *) \n (* box_type = \"PRIMITIVE\" *) \n CARRY4 \\gmux.gm[4].gms.ms_CARRY4 \n (.CI(carrynet_3),\n .CO({\\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}),\n .CYINIT(1'b0),\n .DI({\\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),\n .O(\\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),\n .S({\\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],\\gnxpm_cdc.rd_pntr_bin_reg[10] }));\nendmodule\n\n(* ORIG_REF_NAME = \"compare\" *) \nmodule fb_output_fifo_compare__parameterized1\n (ram_full_fb_i_reg,\n v1_reg_0,\n \\gnxpm_cdc.rd_pntr_bin_reg[10] ,\n \\grstd1.grst_full.grst_f.rst_d3_reg ,\n out,\n wr_en,\n comp1);\n output ram_full_fb_i_reg;\n input [3:0]v1_reg_0;\n input \\gnxpm_cdc.rd_pntr_bin_reg[10] ;\n input \\grstd1.grst_full.grst_f.rst_d3_reg ;\n input out;\n input wr_en;\n input comp1;\n\n wire carrynet_0;\n wire carrynet_1;\n wire carrynet_2;\n wire carrynet_3;\n wire comp1;\n wire comp2;\n wire \\gnxpm_cdc.rd_pntr_bin_reg[10] ;\n wire \\grstd1.grst_full.grst_f.rst_d3_reg ;\n wire out;\n wire ram_full_fb_i_reg;\n wire [3:0]v1_reg_0;\n wire wr_en;\n wire [3:0]\\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;\n wire [3:1]\\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;\n wire [3:1]\\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;\n wire [3:0]\\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;\n wire [3:1]\\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;\n\n (* XILINX_LEGACY_PRIM = \"(MUXCY,XORCY)\" *) \n (* box_type = \"PRIMITIVE\" *) \n CARRY4 \\gmux.gm[0].gm1.m1_CARRY4 \n (.CI(1'b0),\n .CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),\n .CYINIT(1'b1),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),\n .S(v1_reg_0));\n (* XILINX_LEGACY_PRIM = \"(MUXCY,XORCY)\" *) \n (* box_type = \"PRIMITIVE\" *) \n CARRY4 \\gmux.gm[4].gms.ms_CARRY4 \n (.CI(carrynet_3),\n .CO({\\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp2}),\n .CYINIT(1'b0),\n .DI({\\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),\n .O(\\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),\n .S({\\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],\\gnxpm_cdc.rd_pntr_bin_reg[10] }));\n LUT5 #(\n .INIT(32'h55550400)) \n ram_full_i_i_1\n (.I0(\\grstd1.grst_full.grst_f.rst_d3_reg ),\n .I1(comp2),\n .I2(out),\n .I3(wr_en),\n .I4(comp1),\n .O(ram_full_fb_i_reg));\nendmodule\n\n(* ORIG_REF_NAME = \"fifo_generator_ramfifo\" *) \nmodule fb_output_fifo_fifo_generator_ramfifo\n (WR_RST_BUSY,\n dout,\n empty,\n full,\n prog_full,\n rd_en,\n wr_en,\n rd_clk,\n wr_clk,\n din,\n rst);\n output WR_RST_BUSY;\n output [31:0]dout;\n output empty;\n output full;\n output prog_full;\n input rd_en;\n input wr_en;\n input rd_clk;\n input wr_clk;\n input [127:0]din;\n input rst;\n\n wire WR_RST_BUSY;\n wire [127:0]din;\n wire [31:0]dout;\n wire empty;\n wire full;\n wire \\gntv_or_sync_fifo.gcx.clkx_n_0 ;\n wire \\gntv_or_sync_fifo.gcx.clkx_n_10 ;\n wire \\gntv_or_sync_fifo.gl0.wr_n_3 ;\n wire [4:1]\\gras.rsts/c0/v1_reg ;\n wire [4:1]\\gras.rsts/c1/v1_reg ;\n wire [10:0]p_0_out;\n wire [8:0]p_12_out;\n wire [8:8]p_13_out;\n wire [8:8]p_22_out;\n wire [10:2]p_23_out;\n wire p_2_out;\n wire prog_full;\n wire rd_clk;\n wire rd_en;\n wire [9:2]rd_pntr_plus1;\n wire [2:0]rd_rst_i;\n wire rst;\n wire rst_full_ff_i;\n wire tmp_ram_rd_en;\n wire wr_clk;\n wire wr_en;\n wire [8:8]wr_pntr_plus2;\n wire [1:0]wr_rst_i;\n\n fb_output_fifo_clk_x_pntrs \\gntv_or_sync_fifo.gcx.clkx \n (.AR(wr_rst_i[0]),\n .D(wr_pntr_plus2),\n .Q(p_13_out),\n .RD_PNTR_WR(p_23_out),\n .WR_PNTR_RD(p_22_out),\n .\\gc0.count_d1_reg[10] (p_0_out),\n .\\gc0.count_reg[9] (rd_pntr_plus1),\n .\\gic0.gc0.count_d2_reg[8] (p_12_out),\n .\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (rd_rst_i[1]),\n .ram_full_fb_i_reg(\\gntv_or_sync_fifo.gcx.clkx_n_0 ),\n .ram_full_fb_i_reg_0(\\gntv_or_sync_fifo.gcx.clkx_n_10 ),\n .rd_clk(rd_clk),\n .v1_reg(\\gras.rsts/c0/v1_reg ),\n .v1_reg_0(\\gras.rsts/c1/v1_reg ),\n .wr_clk(wr_clk));\n fb_output_fifo_rd_logic \\gntv_or_sync_fifo.gl0.rd \n (.AR(rd_rst_i[2]),\n .Q(p_0_out),\n .WR_PNTR_RD(p_22_out),\n .empty(empty),\n .\\gc0.count_d1_reg[9] (rd_pntr_plus1),\n .\\gnxpm_cdc.wr_pntr_bin_reg[6] (\\gras.rsts/c0/v1_reg ),\n .\\gnxpm_cdc.wr_pntr_bin_reg[6]_0 (\\gras.rsts/c1/v1_reg ),\n .out(p_2_out),\n .rd_clk(rd_clk),\n .rd_en(rd_en));\n fb_output_fifo_wr_logic \\gntv_or_sync_fifo.gl0.wr \n (.AR(wr_rst_i[1]),\n .\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (p_12_out),\n .Q(p_13_out),\n .RD_PNTR_WR(p_23_out),\n .WEBWE(\\gntv_or_sync_fifo.gl0.wr_n_3 ),\n .full(full),\n .\\gic0.gc0.count_d1_reg[8] (wr_pntr_plus2),\n .\\gnxpm_cdc.rd_pntr_bin_reg[10] (\\gntv_or_sync_fifo.gcx.clkx_n_0 ),\n .\\gnxpm_cdc.rd_pntr_bin_reg[10]_0 (\\gntv_or_sync_fifo.gcx.clkx_n_10 ),\n .\\grstd1.grst_full.grst_f.rst_d3_reg (WR_RST_BUSY),\n .out(rst_full_ff_i),\n .prog_full(prog_full),\n .wr_clk(wr_clk),\n .wr_en(wr_en));\n fb_output_fifo_memory \\gntv_or_sync_fifo.mem \n (.Q(p_0_out),\n .WEBWE(\\gntv_or_sync_fifo.gl0.wr_n_3 ),\n .din(din),\n .dout(dout),\n .\\gic0.gc0.count_d2_reg[8] (p_12_out),\n .out(rd_rst_i[0]),\n .rd_clk(rd_clk),\n .tmp_ram_rd_en(tmp_ram_rd_en),\n .wr_clk(wr_clk));\n fb_output_fifo_reset_blk_ramfifo rstblk\n (.WR_RST_BUSY(WR_RST_BUSY),\n .\\gc0.count_reg[1] (rd_rst_i),\n .\\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_ff_i),\n .out(wr_rst_i),\n .ram_empty_fb_i_reg(p_2_out),\n .rd_clk(rd_clk),\n .rd_en(rd_en),\n .rst(rst),\n .tmp_ram_rd_en(tmp_ram_rd_en),\n .wr_clk(wr_clk));\nendmodule\n\n(* ORIG_REF_NAME = \"fifo_generator_top\" *) \nmodule fb_output_fifo_fifo_generator_top\n (WR_RST_BUSY,\n dout,\n empty,\n full,\n prog_full,\n rd_en,\n wr_en,\n rd_clk,\n wr_clk,\n din,\n rst);\n output WR_RST_BUSY;\n output [31:0]dout;\n output empty;\n output full;\n output prog_full;\n input rd_en;\n input wr_en;\n input rd_clk;\n input wr_clk;\n input [127:0]din;\n input rst;\n\n wire WR_RST_BUSY;\n wire [127:0]din;\n wire [31:0]dout;\n wire empty;\n wire full;\n wire prog_full;\n wire rd_clk;\n wire rd_en;\n wire rst;\n wire wr_clk;\n wire wr_en;\n\n fb_output_fifo_fifo_generator_ramfifo \\grf.rf \n (.WR_RST_BUSY(WR_RST_BUSY),\n .din(din),\n .dout(dout),\n .empty(empty),\n .full(full),\n .prog_full(prog_full),\n .rd_clk(rd_clk),\n .rd_en(rd_en),\n .rst(rst),\n .wr_clk(wr_clk),\n .wr_en(wr_en));\nendmodule\n\n(* C_ADD_NGC_CONSTRAINT = \"0\" *) (* C_APPLICATION_TYPE_AXIS = \"0\" *) (* C_APPLICATION_TYPE_RACH = \"0\" *) \n(* C_APPLICATION_TYPE_RDCH = \"0\" *) (* C_APPLICATION_TYPE_WACH = \"0\" *) (* C_APPLICATION_TYPE_WDCH = \"0\" *) \n(* C_APPLICATION_TYPE_WRCH = \"0\" *) (* C_AXIS_TDATA_WIDTH = \"8\" *) (* C_AXIS_TDEST_WIDTH = \"1\" *) \n(* C_AXIS_TID_WIDTH = \"1\" *) (* C_AXIS_TKEEP_WIDTH = \"1\" *) (* C_AXIS_TSTRB_WIDTH = \"1\" *) \n(* C_AXIS_TUSER_WIDTH = \"4\" *) (* C_AXIS_TYPE = \"0\" *) (* C_AXI_ADDR_WIDTH = \"32\" *) \n(* C_AXI_ARUSER_WIDTH = \"1\" *) (* C_AXI_AWUSER_WIDTH = \"1\" *) (* C_AXI_BUSER_WIDTH = \"1\" *) \n(* C_AXI_DATA_WIDTH = \"64\" *) (* C_AXI_ID_WIDTH = \"1\" *) (* C_AXI_LEN_WIDTH = \"8\" *) \n(* C_AXI_LOCK_WIDTH = \"1\" *) (* C_AXI_RUSER_WIDTH = \"1\" *) (* C_AXI_TYPE = \"1\" *) \n(* C_AXI_WUSER_WIDTH = \"1\" *) (* C_COMMON_CLOCK = \"0\" *) (* C_COUNT_TYPE = \"0\" *) \n(* C_DATA_COUNT_WIDTH = \"9\" *) (* C_DEFAULT_VALUE = \"BlankString\" *) (* C_DIN_WIDTH = \"128\" *) \n(* C_DIN_WIDTH_AXIS = \"1\" *) (* C_DIN_WIDTH_RACH = \"32\" *) (* C_DIN_WIDTH_RDCH = \"64\" *) \n(* C_DIN_WIDTH_WACH = \"1\" *) (* C_DIN_WIDTH_WDCH = \"64\" *) (* C_DIN_WIDTH_WRCH = \"2\" *) \n(* C_DOUT_RST_VAL = \"0\" *) (* C_DOUT_WIDTH = \"32\" *) (* C_ENABLE_RLOCS = \"0\" *) \n(* C_ENABLE_RST_SYNC = \"1\" *) (* C_EN_SAFETY_CKT = \"0\" *) (* C_ERROR_INJECTION_TYPE = \"0\" *) \n(* C_ERROR_INJECTION_TYPE_AXIS = \"0\" *) (* C_ERROR_INJECTION_TYPE_RACH = \"0\" *) (* C_ERROR_INJECTION_TYPE_RDCH = \"0\" *) \n(* C_ERROR_INJECTION_TYPE_WACH = \"0\" *) (* C_ERROR_INJECTION_TYPE_WDCH = \"0\" *) (* C_ERROR_INJECTION_TYPE_WRCH = \"0\" *) \n(* C_FAMILY = \"kintex7\" *) (* C_FULL_FLAGS_RST_VAL = \"1\" *) (* C_HAS_ALMOST_EMPTY = \"0\" *) \n(* C_HAS_ALMOST_FULL = \"0\" *) (* C_HAS_AXIS_TDATA = \"1\" *) (* C_HAS_AXIS_TDEST = \"0\" *) \n(* C_HAS_AXIS_TID = \"0\" *) (* C_HAS_AXIS_TKEEP = \"0\" *) (* C_HAS_AXIS_TLAST = \"0\" *) \n(* C_HAS_AXIS_TREADY = \"1\" *) (* C_HAS_AXIS_TSTRB = \"0\" *) (* C_HAS_AXIS_TUSER = \"1\" *) \n(* C_HAS_AXI_ARUSER = \"0\" *) (* C_HAS_AXI_AWUSER = \"0\" *) (* C_HAS_AXI_BUSER = \"0\" *) \n(* C_HAS_AXI_ID = \"0\" *) (* C_HAS_AXI_RD_CHANNEL = \"1\" *) (* C_HAS_AXI_RUSER = \"0\" *) \n(* C_HAS_AXI_WR_CHANNEL = \"1\" *) (* C_HAS_AXI_WUSER = \"0\" *) (* C_HAS_BACKUP = \"0\" *) \n(* C_HAS_DATA_COUNT = \"0\" *) (* C_HAS_DATA_COUNTS_AXIS = \"0\" *) (* C_HAS_DATA_COUNTS_RACH = \"0\" *) \n(* C_HAS_DATA_COUNTS_RDCH = \"0\" *) (* C_HAS_DATA_COUNTS_WACH = \"0\" *) (* C_HAS_DATA_COUNTS_WDCH = \"0\" *) \n(* C_HAS_DATA_COUNTS_WRCH = \"0\" *) (* C_HAS_INT_CLK = \"0\" *) (* C_HAS_MASTER_CE = \"0\" *) \n(* C_HAS_MEMINIT_FILE = \"0\" *) (* C_HAS_OVERFLOW = \"0\" *) (* C_HAS_PROG_FLAGS_AXIS = \"0\" *) \n(* C_HAS_PROG_FLAGS_RACH = \"0\" *) (* C_HAS_PROG_FLAGS_RDCH = \"0\" *) (* C_HAS_PROG_FLAGS_WACH = \"0\" *) \n(* C_HAS_PROG_FLAGS_WDCH = \"0\" *) (* C_HAS_PROG_FLAGS_WRCH = \"0\" *) (* C_HAS_RD_DATA_COUNT = \"0\" *) \n(* C_HAS_RD_RST = \"0\" *) (* C_HAS_RST = \"1\" *) (* C_HAS_SLAVE_CE = \"0\" *) \n(* C_HAS_SRST = \"0\" *) (* C_HAS_UNDERFLOW = \"0\" *) (* C_HAS_VALID = \"0\" *) \n(* C_HAS_WR_ACK = \"0\" *) (* C_HAS_WR_DATA_COUNT = \"0\" *) (* C_HAS_WR_RST = \"0\" *) \n(* C_IMPLEMENTATION_TYPE = \"2\" *) (* C_IMPLEMENTATION_TYPE_AXIS = \"1\" *) (* C_IMPLEMENTATION_TYPE_RACH = \"1\" *) \n(* C_IMPLEMENTATION_TYPE_RDCH = \"1\" *) (* C_IMPLEMENTATION_TYPE_WACH = \"1\" *) (* C_IMPLEMENTATION_TYPE_WDCH = \"1\" *) \n(* C_IMPLEMENTATION_TYPE_WRCH = \"1\" *) (* C_INIT_WR_PNTR_VAL = \"0\" *) (* C_INTERFACE_TYPE = \"0\" *) \n(* C_MEMORY_TYPE = \"1\" *) (* C_MIF_FILE_NAME = \"BlankString\" *) (* C_MSGON_VAL = \"1\" *) \n(* C_OPTIMIZATION_MODE = \"0\" *) (* C_OVERFLOW_LOW = \"0\" *) (* C_POWER_SAVING_MODE = \"0\" *) \n(* C_PRELOAD_LATENCY = \"1\" *) (* C_PRELOAD_REGS = \"0\" *) (* C_PRIM_FIFO_TYPE = \"512x72\" *) \n(* C_PRIM_FIFO_TYPE_AXIS = \"1kx18\" *) (* C_PRIM_FIFO_TYPE_RACH = \"512x36\" *) (* C_PRIM_FIFO_TYPE_RDCH = \"1kx36\" *) \n(* C_PRIM_FIFO_TYPE_WACH = \"512x36\" *) (* C_PRIM_FIFO_TYPE_WDCH = \"1kx36\" *) (* C_PRIM_FIFO_TYPE_WRCH = \"512x36\" *) \n(* C_PROG_EMPTY_THRESH_ASSERT_VAL = \"2\" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = \"1022\" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = \"1022\" *) \n(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = \"1022\" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = \"1022\" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = \"1022\" *) \n(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = \"1022\" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = \"3\" *) (* C_PROG_EMPTY_TYPE = \"0\" *) \n(* C_PROG_EMPTY_TYPE_AXIS = \"0\" *) (* C_PROG_EMPTY_TYPE_RACH = \"0\" *) (* C_PROG_EMPTY_TYPE_RDCH = \"0\" *) \n(* C_PROG_EMPTY_TYPE_WACH = \"0\" *) (* C_PROG_EMPTY_TYPE_WDCH = \"0\" *) (* C_PROG_EMPTY_TYPE_WRCH = \"0\" *) \n(* C_PROG_FULL_THRESH_ASSERT_VAL = \"496\" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = \"1023\" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = \"1023\" *) \n(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = \"1023\" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = \"1023\" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = \"1023\" *) \n(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = \"1023\" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = \"495\" *) (* C_PROG_FULL_TYPE = \"1\" *) \n(* C_PROG_FULL_TYPE_AXIS = \"0\" *) (* C_PROG_FULL_TYPE_RACH = \"0\" *) (* C_PROG_FULL_TYPE_RDCH = \"0\" *) \n(* C_PROG_FULL_TYPE_WACH = \"0\" *) (* C_PROG_FULL_TYPE_WDCH = \"0\" *) (* C_PROG_FULL_TYPE_WRCH = \"0\" *) \n(* C_RACH_TYPE = \"0\" *) (* C_RDCH_TYPE = \"0\" *) (* C_RD_DATA_COUNT_WIDTH = \"11\" *) \n(* C_RD_DEPTH = \"2048\" *) (* C_RD_FREQ = \"1\" *) (* C_RD_PNTR_WIDTH = \"11\" *) \n(* C_REG_SLICE_MODE_AXIS = \"0\" *) (* C_REG_SLICE_MODE_RACH = \"0\" *) (* C_REG_SLICE_MODE_RDCH = \"0\" *) \n(* C_REG_SLICE_MODE_WACH = \"0\" *) (* C_REG_SLICE_MODE_WDCH = \"0\" *) (* C_REG_SLICE_MODE_WRCH = \"0\" *) \n(* C_SELECT_XPM = \"0\" *) (* C_SYNCHRONIZER_STAGE = \"2\" *) (* C_UNDERFLOW_LOW = \"0\" *) \n(* C_USE_COMMON_OVERFLOW = \"0\" *) (* C_USE_COMMON_UNDERFLOW = \"0\" *) (* C_USE_DEFAULT_SETTINGS = \"0\" *) \n(* C_USE_DOUT_RST = \"1\" *) (* C_USE_ECC = \"0\" *) (* C_USE_ECC_AXIS = \"0\" *) \n(* C_USE_ECC_RACH = \"0\" *) (* C_USE_ECC_RDCH = \"0\" *) (* C_USE_ECC_WACH = \"0\" *) \n(* C_USE_ECC_WDCH = \"0\" *) (* C_USE_ECC_WRCH = \"0\" *) (* C_USE_EMBEDDED_REG = \"0\" *) \n(* C_USE_FIFO16_FLAGS = \"0\" *) (* C_USE_FWFT_DATA_COUNT = \"0\" *) (* C_USE_PIPELINE_REG = \"0\" *) \n(* C_VALID_LOW = \"0\" *) (* C_WACH_TYPE = \"0\" *) (* C_WDCH_TYPE = \"0\" *) \n(* C_WRCH_TYPE = \"0\" *) (* C_WR_ACK_LOW = \"0\" *) (* C_WR_DATA_COUNT_WIDTH = \"9\" *) \n(* C_WR_DEPTH = \"512\" *) (* C_WR_DEPTH_AXIS = \"1024\" *) (* C_WR_DEPTH_RACH = \"16\" *) \n(* C_WR_DEPTH_RDCH = \"1024\" *) (* C_WR_DEPTH_WACH = \"16\" *) (* C_WR_DEPTH_WDCH = \"1024\" *) \n(* C_WR_DEPTH_WRCH = \"16\" *) (* C_WR_FREQ = \"1\" *) (* C_WR_PNTR_WIDTH = \"9\" *) \n(* C_WR_PNTR_WIDTH_AXIS = \"10\" *) (* C_WR_PNTR_WIDTH_RACH = \"4\" *) (* C_WR_PNTR_WIDTH_RDCH = \"10\" *) \n(* C_WR_PNTR_WIDTH_WACH = \"4\" *) (* C_WR_PNTR_WIDTH_WDCH = \"10\" *) (* C_WR_PNTR_WIDTH_WRCH = \"4\" *) \n(* C_WR_RESPONSE_LATENCY = \"1\" *) (* ORIG_REF_NAME = \"fifo_generator_v13_1_2\" *) \nmodule fb_output_fifo_fifo_generator_v13_1_2\n (backup,\n backup_marker,\n clk,\n rst,\n srst,\n wr_clk,\n wr_rst,\n rd_clk,\n rd_rst,\n din,\n wr_en,\n rd_en,\n prog_empty_thresh,\n prog_empty_thresh_assert,\n prog_empty_thresh_negate,\n prog_full_thresh,\n prog_full_thresh_assert,\n prog_full_thresh_negate,\n int_clk,\n injectdbiterr,\n injectsbiterr,\n sleep,\n dout,\n full,\n almost_full,\n wr_ack,\n overflow,\n empty,\n almost_empty,\n valid,\n underflow,\n data_count,\n rd_data_count,\n wr_data_count,\n prog_full,\n prog_empty,\n sbiterr,\n dbiterr,\n wr_rst_busy,\n rd_rst_busy,\n m_aclk,\n s_aclk,\n s_aresetn,\n m_aclk_en,\n s_aclk_en,\n s_axi_awid,\n s_axi_awaddr,\n s_axi_awlen,\n s_axi_awsize,\n s_axi_awburst,\n s_axi_awlock,\n s_axi_awcache,\n s_axi_awprot,\n s_axi_awqos,\n s_axi_awregion,\n s_axi_awuser,\n s_axi_awvalid,\n s_axi_awready,\n s_axi_wid,\n s_axi_wdata,\n s_axi_wstrb,\n s_axi_wlast,\n s_axi_wuser,\n s_axi_wvalid,\n s_axi_wready,\n s_axi_bid,\n s_axi_bresp,\n s_axi_buser,\n s_axi_bvalid,\n s_axi_bready,\n m_axi_awid,\n m_axi_awaddr,\n m_axi_awlen,\n m_axi_awsize,\n m_axi_awburst,\n m_axi_awlock,\n m_axi_awcache,\n m_axi_awprot,\n m_axi_awqos,\n m_axi_awregion,\n m_axi_awuser,\n m_axi_awvalid,\n m_axi_awready,\n m_axi_wid,\n m_axi_wdata,\n m_axi_wstrb,\n m_axi_wlast,\n m_axi_wuser,\n m_axi_wvalid,\n m_axi_wready,\n m_axi_bid,\n m_axi_bresp,\n m_axi_buser,\n m_axi_bvalid,\n m_axi_bready,\n s_axi_arid,\n s_axi_araddr,\n s_axi_arlen,\n s_axi_arsize,\n s_axi_arburst,\n s_axi_arlock,\n s_axi_arcache,\n s_axi_arprot,\n s_axi_arqos,\n s_axi_arregion,\n s_axi_aruser,\n s_axi_arvalid,\n s_axi_arready,\n s_axi_rid,\n s_axi_rdata,\n s_axi_rresp,\n s_axi_rlast,\n s_axi_ruser,\n s_axi_rvalid,\n s_axi_rready,\n m_axi_arid,\n m_axi_araddr,\n m_axi_arlen,\n m_axi_arsize,\n m_axi_arburst,\n m_axi_arlock,\n m_axi_arcache,\n m_axi_arprot,\n m_axi_arqos,\n m_axi_arregion,\n m_axi_aruser,\n m_axi_arvalid,\n m_axi_arready,\n m_axi_rid,\n m_axi_rdata,\n m_axi_rresp,\n m_axi_rlast,\n m_axi_ruser,\n m_axi_rvalid,\n m_axi_rready,\n s_axis_tvalid,\n s_axis_tready,\n s_axis_tdata,\n s_axis_tstrb,\n s_axis_tkeep,\n s_axis_tlast,\n s_axis_tid,\n s_axis_tdest,\n s_axis_tuser,\n m_axis_tvalid,\n m_axis_tready,\n m_axis_tdata,\n m_axis_tstrb,\n m_axis_tkeep,\n m_axis_tlast,\n m_axis_tid,\n m_axis_tdest,\n m_axis_tuser,\n axi_aw_injectsbiterr,\n axi_aw_injectdbiterr,\n axi_aw_prog_full_thresh,\n axi_aw_prog_empty_thresh,\n axi_aw_data_count,\n axi_aw_wr_data_count,\n axi_aw_rd_data_count,\n axi_aw_sbiterr,\n axi_aw_dbiterr,\n axi_aw_overflow,\n axi_aw_underflow,\n axi_aw_prog_full,\n axi_aw_prog_empty,\n axi_w_injectsbiterr,\n axi_w_injectdbiterr,\n axi_w_prog_full_thresh,\n axi_w_prog_empty_thresh,\n axi_w_data_count,\n axi_w_wr_data_count,\n axi_w_rd_data_count,\n axi_w_sbiterr,\n axi_w_dbiterr,\n axi_w_overflow,\n axi_w_underflow,\n axi_w_prog_full,\n axi_w_prog_empty,\n axi_b_injectsbiterr,\n axi_b_injectdbiterr,\n axi_b_prog_full_thresh,\n axi_b_prog_empty_thresh,\n axi_b_data_count,\n axi_b_wr_data_count,\n axi_b_rd_data_count,\n axi_b_sbiterr,\n axi_b_dbiterr,\n axi_b_overflow,\n axi_b_underflow,\n axi_b_prog_full,\n axi_b_prog_empty,\n axi_ar_injectsbiterr,\n axi_ar_injectdbiterr,\n axi_ar_prog_full_thresh,\n axi_ar_prog_empty_thresh,\n axi_ar_data_count,\n axi_ar_wr_data_count,\n axi_ar_rd_data_count,\n axi_ar_sbiterr,\n axi_ar_dbiterr,\n axi_ar_overflow,\n axi_ar_underflow,\n axi_ar_prog_full,\n axi_ar_prog_empty,\n axi_r_injectsbiterr,\n axi_r_injectdbiterr,\n axi_r_prog_full_thresh,\n axi_r_prog_empty_thresh,\n axi_r_data_count,\n axi_r_wr_data_count,\n axi_r_rd_data_count,\n axi_r_sbiterr,\n axi_r_dbiterr,\n axi_r_overflow,\n axi_r_underflow,\n axi_r_prog_full,\n axi_r_prog_empty,\n axis_injectsbiterr,\n axis_injectdbiterr,\n axis_prog_full_thresh,\n axis_prog_empty_thresh,\n axis_data_count,\n axis_wr_data_count,\n axis_rd_data_count,\n axis_sbiterr,\n axis_dbiterr,\n axis_overflow,\n axis_underflow,\n axis_prog_full,\n axis_prog_empty);\n input backup;\n input backup_marker;\n input clk;\n input rst;\n input srst;\n input wr_clk;\n input wr_rst;\n input rd_clk;\n input rd_rst;\n input [127:0]din;\n input wr_en;\n input rd_en;\n input [10:0]prog_empty_thresh;\n input [10:0]prog_empty_thresh_assert;\n input [10:0]prog_empty_thresh_negate;\n input [8:0]prog_full_thresh;\n input [8:0]prog_full_thresh_assert;\n input [8:0]prog_full_thresh_negate;\n input int_clk;\n input injectdbiterr;\n input injectsbiterr;\n input sleep;\n output [31:0]dout;\n output full;\n output almost_full;\n output wr_ack;\n output overflow;\n output empty;\n output almost_empty;\n output valid;\n output underflow;\n output [8:0]data_count;\n output [10:0]rd_data_count;\n output [8:0]wr_data_count;\n output prog_full;\n output prog_empty;\n output sbiterr;\n output dbiterr;\n output wr_rst_busy;\n output rd_rst_busy;\n input m_aclk;\n input s_aclk;\n input s_aresetn;\n input m_aclk_en;\n input s_aclk_en;\n input [0:0]s_axi_awid;\n input [31:0]s_axi_awaddr;\n input [7:0]s_axi_awlen;\n input [2:0]s_axi_awsize;\n input [1:0]s_axi_awburst;\n input [0:0]s_axi_awlock;\n input [3:0]s_axi_awcache;\n input [2:0]s_axi_awprot;\n input [3:0]s_axi_awqos;\n input [3:0]s_axi_awregion;\n input [0:0]s_axi_awuser;\n input s_axi_awvalid;\n output s_axi_awready;\n input [0:0]s_axi_wid;\n input [63:0]s_axi_wdata;\n input [7:0]s_axi_wstrb;\n input s_axi_wlast;\n input [0:0]s_axi_wuser;\n input s_axi_wvalid;\n output s_axi_wready;\n output [0:0]s_axi_bid;\n output [1:0]s_axi_bresp;\n output [0:0]s_axi_buser;\n output s_axi_bvalid;\n input s_axi_bready;\n output [0:0]m_axi_awid;\n output [31:0]m_axi_awaddr;\n output [7:0]m_axi_awlen;\n output [2:0]m_axi_awsize;\n output [1:0]m_axi_awburst;\n output [0:0]m_axi_awlock;\n output [3:0]m_axi_awcache;\n output [2:0]m_axi_awprot;\n output [3:0]m_axi_awqos;\n output [3:0]m_axi_awregion;\n output [0:0]m_axi_awuser;\n output m_axi_awvalid;\n input m_axi_awready;\n output [0:0]m_axi_wid;\n output [63:0]m_axi_wdata;\n output [7:0]m_axi_wstrb;\n output m_axi_wlast;\n output [0:0]m_axi_wuser;\n output m_axi_wvalid;\n input m_axi_wready;\n input [0:0]m_axi_bid;\n input [1:0]m_axi_bresp;\n input [0:0]m_axi_buser;\n input m_axi_bvalid;\n output m_axi_bready;\n input [0:0]s_axi_arid;\n input [31:0]s_axi_araddr;\n input [7:0]s_axi_arlen;\n input [2:0]s_axi_arsize;\n input [1:0]s_axi_arburst;\n input [0:0]s_axi_arlock;\n input [3:0]s_axi_arcache;\n input [2:0]s_axi_arprot;\n input [3:0]s_axi_arqos;\n input [3:0]s_axi_arregion;\n input [0:0]s_axi_aruser;\n input s_axi_arvalid;\n output s_axi_arready;\n output [0:0]s_axi_rid;\n output [63:0]s_axi_rdata;\n output [1:0]s_axi_rresp;\n output s_axi_rlast;\n output [0:0]s_axi_ruser;\n output s_axi_rvalid;\n input s_axi_rready;\n output [0:0]m_axi_arid;\n output [31:0]m_axi_araddr;\n output [7:0]m_axi_arlen;\n output [2:0]m_axi_arsize;\n output [1:0]m_axi_arburst;\n output [0:0]m_axi_arlock;\n output [3:0]m_axi_arcache;\n output [2:0]m_axi_arprot;\n output [3:0]m_axi_arqos;\n output [3:0]m_axi_arregion;\n output [0:0]m_axi_aruser;\n output m_axi_arvalid;\n input m_axi_arready;\n input [0:0]m_axi_rid;\n input [63:0]m_axi_rdata;\n input [1:0]m_axi_rresp;\n input m_axi_rlast;\n input [0:0]m_axi_ruser;\n input m_axi_rvalid;\n output m_axi_rready;\n input s_axis_tvalid;\n output s_axis_tready;\n input [7:0]s_axis_tdata;\n input [0:0]s_axis_tstrb;\n input [0:0]s_axis_tkeep;\n input s_axis_tlast;\n input [0:0]s_axis_tid;\n input [0:0]s_axis_tdest;\n input [3:0]s_axis_tuser;\n output m_axis_tvalid;\n input m_axis_tready;\n output [7:0]m_axis_tdata;\n output [0:0]m_axis_tstrb;\n output [0:0]m_axis_tkeep;\n output m_axis_tlast;\n output [0:0]m_axis_tid;\n output [0:0]m_axis_tdest;\n output [3:0]m_axis_tuser;\n input axi_aw_injectsbiterr;\n input axi_aw_injectdbiterr;\n input [3:0]axi_aw_prog_full_thresh;\n input [3:0]axi_aw_prog_empty_thresh;\n output [4:0]axi_aw_data_count;\n output [4:0]axi_aw_wr_data_count;\n output [4:0]axi_aw_rd_data_count;\n output axi_aw_sbiterr;\n output axi_aw_dbiterr;\n output axi_aw_overflow;\n output axi_aw_underflow;\n output axi_aw_prog_full;\n output axi_aw_prog_empty;\n input axi_w_injectsbiterr;\n input axi_w_injectdbiterr;\n input [9:0]axi_w_prog_full_thresh;\n input [9:0]axi_w_prog_empty_thresh;\n output [10:0]axi_w_data_count;\n output [10:0]axi_w_wr_data_count;\n output [10:0]axi_w_rd_data_count;\n output axi_w_sbiterr;\n output axi_w_dbiterr;\n output axi_w_overflow;\n output axi_w_underflow;\n output axi_w_prog_full;\n output axi_w_prog_empty;\n input axi_b_injectsbiterr;\n input axi_b_injectdbiterr;\n input [3:0]axi_b_prog_full_thresh;\n input [3:0]axi_b_prog_empty_thresh;\n output [4:0]axi_b_data_count;\n output [4:0]axi_b_wr_data_count;\n output [4:0]axi_b_rd_data_count;\n output axi_b_sbiterr;\n output axi_b_dbiterr;\n output axi_b_overflow;\n output axi_b_underflow;\n output axi_b_prog_full;\n output axi_b_prog_empty;\n input axi_ar_injectsbiterr;\n input axi_ar_injectdbiterr;\n input [3:0]axi_ar_prog_full_thresh;\n input [3:0]axi_ar_prog_empty_thresh;\n output [4:0]axi_ar_data_count;\n output [4:0]axi_ar_wr_data_count;\n output [4:0]axi_ar_rd_data_count;\n output axi_ar_sbiterr;\n output axi_ar_dbiterr;\n output axi_ar_overflow;\n output axi_ar_underflow;\n output axi_ar_prog_full;\n output axi_ar_prog_empty;\n input axi_r_injectsbiterr;\n input axi_r_injectdbiterr;\n input [9:0]axi_r_prog_full_thresh;\n input [9:0]axi_r_prog_empty_thresh;\n output [10:0]axi_r_data_count;\n output [10:0]axi_r_wr_data_count;\n output [10:0]axi_r_rd_data_count;\n output axi_r_sbiterr;\n output axi_r_dbiterr;\n output axi_r_overflow;\n output axi_r_underflow;\n output axi_r_prog_full;\n output axi_r_prog_empty;\n input axis_injectsbiterr;\n input axis_injectdbiterr;\n input [9:0]axis_prog_full_thresh;\n input [9:0]axis_prog_empty_thresh;\n output [10:0]axis_data_count;\n output [10:0]axis_wr_data_count;\n output [10:0]axis_rd_data_count;\n output axis_sbiterr;\n output axis_dbiterr;\n output axis_overflow;\n output axis_underflow;\n output axis_prog_full;\n output axis_prog_empty;\n\n wire \\ ;\n wire \\ ;\n wire [127:0]din;\n wire [31:0]dout;\n wire empty;\n wire full;\n wire prog_full;\n wire rd_clk;\n wire rd_en;\n wire rst;\n wire wr_clk;\n wire wr_en;\n wire wr_rst_busy;\n\n assign almost_empty = \\ ;\n assign almost_full = \\ ;\n assign axi_ar_data_count[4] = \\ ;\n assign axi_ar_data_count[3] = \\ ;\n assign axi_ar_data_count[2] = \\ ;\n assign axi_ar_data_count[1] = \\ ;\n assign axi_ar_data_count[0] = \\ ;\n assign axi_ar_dbiterr = \\ ;\n assign axi_ar_overflow = \\ ;\n assign axi_ar_prog_empty = \\ ;\n assign axi_ar_prog_full = \\ ;\n assign axi_ar_rd_data_count[4] = \\ ;\n assign axi_ar_rd_data_count[3] = \\ ;\n assign axi_ar_rd_data_count[2] = \\ ;\n assign axi_ar_rd_data_count[1] = \\ ;\n assign axi_ar_rd_data_count[0] = \\ ;\n assign axi_ar_sbiterr = \\ ;\n assign axi_ar_underflow = \\ ;\n assign axi_ar_wr_data_count[4] = \\ ;\n assign axi_ar_wr_data_count[3] = \\ ;\n assign axi_ar_wr_data_count[2] = \\ ;\n assign axi_ar_wr_data_count[1] = \\ ;\n assign axi_ar_wr_data_count[0] = \\ ;\n assign axi_aw_data_count[4] = \\ ;\n assign axi_aw_data_count[3] = \\ ;\n assign axi_aw_data_count[2] = \\ ;\n assign axi_aw_data_count[1] = \\ ;\n assign axi_aw_data_count[0] = \\ ;\n assign axi_aw_dbiterr = \\ ;\n assign axi_aw_overflow = \\ ;\n assign axi_aw_prog_empty = \\ ;\n assign axi_aw_prog_full = \\ ;\n assign axi_aw_rd_data_count[4] = \\ ;\n assign axi_aw_rd_data_count[3] = \\ ;\n assign axi_aw_rd_data_count[2] = \\ ;\n assign axi_aw_rd_data_count[1] = \\ ;\n assign axi_aw_rd_data_count[0] = \\ ;\n assign axi_aw_sbiterr = \\ ;\n assign axi_aw_underflow = \\ ;\n assign axi_aw_wr_data_count[4] = \\ ;\n assign axi_aw_wr_data_count[3] = \\ ;\n assign axi_aw_wr_data_count[2] = \\ ;\n assign axi_aw_wr_data_count[1] = \\ ;\n assign axi_aw_wr_data_count[0] = \\ ;\n assign axi_b_data_count[4] = \\ ;\n assign axi_b_data_count[3] = \\ ;\n assign axi_b_data_count[2] = \\ ;\n assign axi_b_data_count[1] = \\ ;\n assign axi_b_data_count[0] = \\ ;\n assign axi_b_dbiterr = \\ ;\n assign axi_b_overflow = \\ ;\n assign axi_b_prog_empty = \\ ;\n assign axi_b_prog_full = \\ ;\n assign axi_b_rd_data_count[4] = \\ ;\n assign axi_b_rd_data_count[3] = \\ ;\n assign axi_b_rd_data_count[2] = \\ ;\n assign axi_b_rd_data_count[1] = \\ ;\n assign axi_b_rd_data_count[0] = \\ ;\n assign axi_b_sbiterr = \\ ;\n assign axi_b_underflow = \\ ;\n assign axi_b_wr_data_count[4] = \\ ;\n assign axi_b_wr_data_count[3] = \\ ;\n assign axi_b_wr_data_count[2] = \\ ;\n assign axi_b_wr_data_count[1] = \\ ;\n assign axi_b_wr_data_count[0] = \\ ;\n assign axi_r_data_count[10] = \\ ;\n assign axi_r_data_count[9] = \\ ;\n assign axi_r_data_count[8] = \\ ;\n assign axi_r_data_count[7] = \\ ;\n assign axi_r_data_count[6] = \\ ;\n assign axi_r_data_count[5] = \\ ;\n assign axi_r_data_count[4] = \\ ;\n assign axi_r_data_count[3] = \\ ;\n assign axi_r_data_count[2] = \\ ;\n assign axi_r_data_count[1] = \\ ;\n assign axi_r_data_count[0] = \\ ;\n assign axi_r_dbiterr = \\ ;\n assign axi_r_overflow = \\ ;\n assign axi_r_prog_empty = \\ ;\n assign axi_r_prog_full = \\ ;\n assign axi_r_rd_data_count[10] = \\ ;\n assign axi_r_rd_data_count[9] = \\ ;\n assign axi_r_rd_data_count[8] = \\ ;\n assign axi_r_rd_data_count[7] = \\ ;\n assign axi_r_rd_data_count[6] = \\ ;\n assign axi_r_rd_data_count[5] = \\ ;\n assign axi_r_rd_data_count[4] = \\ ;\n assign axi_r_rd_data_count[3] = \\ ;\n assign axi_r_rd_data_count[2] = \\ ;\n assign axi_r_rd_data_count[1] = \\ ;\n assign axi_r_rd_data_count[0] = \\ ;\n assign axi_r_sbiterr = \\ ;\n assign axi_r_underflow = \\ ;\n assign axi_r_wr_data_count[10] = \\ ;\n assign axi_r_wr_data_count[9] = \\ ;\n assign axi_r_wr_data_count[8] = \\ ;\n assign axi_r_wr_data_count[7] = \\ ;\n assign axi_r_wr_data_count[6] = \\ ;\n assign axi_r_wr_data_count[5] = \\ ;\n assign axi_r_wr_data_count[4] = \\ ;\n assign axi_r_wr_data_count[3] = \\ ;\n assign axi_r_wr_data_count[2] = \\ ;\n assign axi_r_wr_data_count[1] = \\ ;\n assign axi_r_wr_data_count[0] = \\ ;\n assign axi_w_data_count[10] = \\ ;\n assign axi_w_data_count[9] = \\ ;\n assign axi_w_data_count[8] = \\ ;\n assign axi_w_data_count[7] = \\ ;\n assign axi_w_data_count[6] = \\ ;\n assign axi_w_data_count[5] = \\ ;\n assign axi_w_data_count[4] = \\ ;\n assign axi_w_data_count[3] = \\ ;\n assign axi_w_data_count[2] = \\ ;\n assign axi_w_data_count[1] = \\ ;\n assign axi_w_data_count[0] = \\ ;\n assign axi_w_dbiterr = \\ ;\n assign axi_w_overflow = \\ ;\n assign axi_w_prog_empty = \\ ;\n assign axi_w_prog_full = \\ ;\n assign axi_w_rd_data_count[10] = \\ ;\n assign axi_w_rd_data_count[9] = \\ ;\n assign axi_w_rd_data_count[8] = \\ ;\n assign axi_w_rd_data_count[7] = \\ ;\n assign axi_w_rd_data_count[6] = \\ ;\n assign axi_w_rd_data_count[5] = \\ ;\n assign axi_w_rd_data_count[4] = \\ ;\n assign axi_w_rd_data_count[3] = \\ ;\n assign axi_w_rd_data_count[2] = \\ ;\n assign axi_w_rd_data_count[1] = \\ ;\n assign axi_w_rd_data_count[0] = \\ ;\n assign axi_w_sbiterr = \\ ;\n assign axi_w_underflow = \\ ;\n assign axi_w_wr_data_count[10] = \\ ;\n assign axi_w_wr_data_count[9] = \\ ;\n assign axi_w_wr_data_count[8] = \\ ;\n assign axi_w_wr_data_count[7] = \\ ;\n assign axi_w_wr_data_count[6] = \\ ;\n assign axi_w_wr_data_count[5] = \\ ;\n assign axi_w_wr_data_count[4] = \\ ;\n assign axi_w_wr_data_count[3] = \\ ;\n assign axi_w_wr_data_count[2] = \\ ;\n assign axi_w_wr_data_count[1] = \\ ;\n assign axi_w_wr_data_count[0] = \\ ;\n assign axis_data_count[10] = \\ ;\n assign axis_data_count[9] = \\ ;\n assign axis_data_count[8] = \\ ;\n assign axis_data_count[7] = \\ ;\n assign axis_data_count[6] = \\ ;\n assign axis_data_count[5] = \\ ;\n assign axis_data_count[4] = \\ ;\n assign axis_data_count[3] = \\ ;\n assign axis_data_count[2] = \\ ;\n assign axis_data_count[1] = \\ ;\n assign axis_data_count[0] = \\ ;\n assign axis_dbiterr = \\ ;\n assign axis_overflow = \\ ;\n assign axis_prog_empty = \\ ;\n assign axis_prog_full = \\ ;\n assign axis_rd_data_count[10] = \\ ;\n assign axis_rd_data_count[9] = \\ ;\n assign axis_rd_data_count[8] = \\ ;\n assign axis_rd_data_count[7] = \\ ;\n assign axis_rd_data_count[6] = \\ ;\n assign axis_rd_data_count[5] = \\ ;\n assign axis_rd_data_count[4] = \\ ;\n assign axis_rd_data_count[3] = \\ ;\n assign axis_rd_data_count[2] = \\ ;\n assign axis_rd_data_count[1] = \\ ;\n assign axis_rd_data_count[0] = \\ ;\n assign axis_sbiterr = \\ ;\n assign axis_underflow = \\ ;\n assign axis_wr_data_count[10] = \\ ;\n assign axis_wr_data_count[9] = \\ ;\n assign axis_wr_data_count[8] = \\ ;\n assign axis_wr_data_count[7] = \\ ;\n assign axis_wr_data_count[6] = \\ ;\n assign axis_wr_data_count[5] = \\ ;\n assign axis_wr_data_count[4] = \\ ;\n assign axis_wr_data_count[3] = \\ ;\n assign axis_wr_data_count[2] = \\ ;\n assign axis_wr_data_count[1] = \\ ;\n assign axis_wr_data_count[0] = \\ ;\n assign data_count[8] = \\ ;\n assign data_count[7] = \\ ;\n assign data_count[6] = \\ ;\n assign data_count[5] = \\ ;\n assign data_count[4] = \\ ;\n assign data_count[3] = \\ ;\n assign data_count[2] = \\ ;\n assign data_count[1] = \\ ;\n assign data_count[0] = \\ ;\n assign dbiterr = \\ ;\n assign m_axi_araddr[31] = \\ ;\n assign m_axi_araddr[30] = \\ ;\n assign m_axi_araddr[29] = \\ ;\n assign m_axi_araddr[28] = \\ ;\n assign m_axi_araddr[27] = \\ ;\n assign m_axi_araddr[26] = \\ ;\n assign m_axi_araddr[25] = \\ ;\n assign m_axi_araddr[24] = \\ ;\n assign m_axi_araddr[23] = \\ ;\n assign m_axi_araddr[22] = \\ ;\n assign m_axi_araddr[21] = \\ ;\n assign m_axi_araddr[20] = \\ ;\n assign m_axi_araddr[19] = \\ ;\n assign m_axi_araddr[18] = \\ ;\n assign m_axi_araddr[17] = \\ ;\n assign m_axi_araddr[16] = \\ ;\n assign m_axi_araddr[15] = \\ ;\n assign m_axi_araddr[14] = \\ ;\n assign m_axi_araddr[13] = \\ ;\n assign m_axi_araddr[12] = \\ ;\n assign m_axi_araddr[11] = \\ ;\n assign m_axi_araddr[10] = \\ ;\n assign m_axi_araddr[9] = \\ ;\n assign m_axi_araddr[8] = \\ ;\n assign m_axi_araddr[7] = \\ ;\n assign m_axi_araddr[6] = \\ ;\n assign m_axi_araddr[5] = \\ ;\n assign m_axi_araddr[4] = \\ ;\n assign m_axi_araddr[3] = \\ ;\n assign m_axi_araddr[2] = \\ ;\n assign m_axi_araddr[1] = \\ ;\n assign m_axi_araddr[0] = \\ ;\n assign m_axi_arburst[1] = \\ ;\n assign m_axi_arburst[0] = \\ ;\n assign m_axi_arcache[3] = \\ ;\n assign m_axi_arcache[2] = \\ ;\n assign m_axi_arcache[1] = \\ ;\n assign m_axi_arcache[0] = \\ ;\n assign m_axi_arid[0] = \\ ;\n assign m_axi_arlen[7] = \\ ;\n assign m_axi_arlen[6] = \\ ;\n assign m_axi_arlen[5] = \\ ;\n assign m_axi_arlen[4] = \\ ;\n assign m_axi_arlen[3] = \\ ;\n assign m_axi_arlen[2] = \\ ;\n assign m_axi_arlen[1] = \\ ;\n assign m_axi_arlen[0] = \\ ;\n assign m_axi_arlock[0] = \\ ;\n assign m_axi_arprot[2] = \\ ;\n assign m_axi_arprot[1] = \\ ;\n assign m_axi_arprot[0] = \\ ;\n assign m_axi_arqos[3] = \\ ;\n assign m_axi_arqos[2] = \\ ;\n assign m_axi_arqos[1] = \\ ;\n assign m_axi_arqos[0] = \\ ;\n assign m_axi_arregion[3] = \\ ;\n assign m_axi_arregion[2] = \\ ;\n assign m_axi_arregion[1] = \\ ;\n assign m_axi_arregion[0] = \\ ;\n assign m_axi_arsize[2] = \\ ;\n assign m_axi_arsize[1] = \\ ;\n assign m_axi_arsize[0] = \\ ;\n assign m_axi_aruser[0] = \\ ;\n assign m_axi_arvalid = \\ ;\n assign m_axi_awaddr[31] = \\ ;\n assign m_axi_awaddr[30] = \\ ;\n assign m_axi_awaddr[29] = \\ ;\n assign m_axi_awaddr[28] = \\ ;\n assign m_axi_awaddr[27] = \\ ;\n assign m_axi_awaddr[26] = \\ ;\n assign m_axi_awaddr[25] = \\ ;\n assign m_axi_awaddr[24] = \\ ;\n assign m_axi_awaddr[23] = \\ ;\n assign m_axi_awaddr[22] = \\ ;\n assign m_axi_awaddr[21] = \\ ;\n assign m_axi_awaddr[20] = \\ ;\n assign m_axi_awaddr[19] = \\ ;\n assign m_axi_awaddr[18] = \\ ;\n assign m_axi_awaddr[17] = \\ ;\n assign m_axi_awaddr[16] = \\ ;\n assign m_axi_awaddr[15] = \\ ;\n assign m_axi_awaddr[14] = \\ ;\n assign m_axi_awaddr[13] = \\ ;\n assign m_axi_awaddr[12] = \\ ;\n assign m_axi_awaddr[11] = \\ ;\n assign m_axi_awaddr[10] = \\ ;\n assign m_axi_awaddr[9] = \\ ;\n assign m_axi_awaddr[8] = \\ ;\n assign m_axi_awaddr[7] = \\ ;\n assign m_axi_awaddr[6] = \\ ;\n assign m_axi_awaddr[5] = \\ ;\n assign m_axi_awaddr[4] = \\ ;\n assign m_axi_awaddr[3] = \\ ;\n assign m_axi_awaddr[2] = \\ ;\n assign m_axi_awaddr[1] = \\ ;\n assign m_axi_awaddr[0] = \\ ;\n assign m_axi_awburst[1] = \\ ;\n assign m_axi_awburst[0] = \\ ;\n assign m_axi_awcache[3] = \\ ;\n assign m_axi_awcache[2] = \\ ;\n assign m_axi_awcache[1] = \\ ;\n assign m_axi_awcache[0] = \\ ;\n assign m_axi_awid[0] = \\ ;\n assign m_axi_awlen[7] = \\ ;\n assign m_axi_awlen[6] = \\ ;\n assign m_axi_awlen[5] = \\ ;\n assign m_axi_awlen[4] = \\ ;\n assign m_axi_awlen[3] = \\ ;\n assign m_axi_awlen[2] = \\ ;\n assign m_axi_awlen[1] = \\ ;\n assign m_axi_awlen[0] = \\ ;\n assign m_axi_awlock[0] = \\ ;\n assign m_axi_awprot[2] = \\ ;\n assign m_axi_awprot[1] = \\ ;\n assign m_axi_awprot[0] = \\ ;\n assign m_axi_awqos[3] = \\ ;\n assign m_axi_awqos[2] = \\ ;\n assign m_axi_awqos[1] = \\ ;\n assign m_axi_awqos[0] = \\ ;\n assign m_axi_awregion[3] = \\ ;\n assign m_axi_awregion[2] = \\ ;\n assign m_axi_awregion[1] = \\ ;\n assign m_axi_awregion[0] = \\ ;\n assign m_axi_awsize[2] = \\ ;\n assign m_axi_awsize[1] = \\ ;\n assign m_axi_awsize[0] = \\ ;\n assign m_axi_awuser[0] = \\ ;\n assign m_axi_awvalid = \\ ;\n assign m_axi_bready = \\ ;\n assign m_axi_rready = \\ ;\n assign m_axi_wdata[63] = \\ ;\n assign m_axi_wdata[62] = \\ ;\n assign m_axi_wdata[61] = \\ ;\n assign m_axi_wdata[60] = \\ ;\n assign m_axi_wdata[59] = \\ ;\n assign m_axi_wdata[58] = \\ ;\n assign m_axi_wdata[57] = \\ ;\n assign m_axi_wdata[56] = \\ ;\n assign m_axi_wdata[55] = \\ ;\n assign m_axi_wdata[54] = \\ ;\n assign m_axi_wdata[53] = \\ ;\n assign m_axi_wdata[52] = \\ ;\n assign m_axi_wdata[51] = \\ ;\n assign m_axi_wdata[50] = \\ ;\n assign m_axi_wdata[49] = \\ ;\n assign m_axi_wdata[48] = \\ ;\n assign m_axi_wdata[47] = \\ ;\n assign m_axi_wdata[46] = \\ ;\n assign m_axi_wdata[45] = \\ ;\n assign m_axi_wdata[44] = \\ ;\n assign m_axi_wdata[43] = \\ ;\n assign m_axi_wdata[42] = \\ ;\n assign m_axi_wdata[41] = \\ ;\n assign m_axi_wdata[40] = \\ ;\n assign m_axi_wdata[39] = \\ ;\n assign m_axi_wdata[38] = \\ ;\n assign m_axi_wdata[37] = \\ ;\n assign m_axi_wdata[36] = \\ ;\n assign m_axi_wdata[35] = \\ ;\n assign m_axi_wdata[34] = \\ ;\n assign m_axi_wdata[33] = \\ ;\n assign m_axi_wdata[32] = \\ ;\n assign m_axi_wdata[31] = \\ ;\n assign m_axi_wdata[30] = \\ ;\n assign m_axi_wdata[29] = \\ ;\n assign m_axi_wdata[28] = \\ ;\n assign m_axi_wdata[27] = \\ ;\n assign m_axi_wdata[26] = \\ ;\n assign m_axi_wdata[25] = \\ ;\n assign m_axi_wdata[24] = \\ ;\n assign m_axi_wdata[23] = \\ ;\n assign m_axi_wdata[22] = \\ ;\n assign m_axi_wdata[21] = \\ ;\n assign m_axi_wdata[20] = \\ ;\n assign m_axi_wdata[19] = \\ ;\n assign m_axi_wdata[18] = \\ ;\n assign m_axi_wdata[17] = \\ ;\n assign m_axi_wdata[16] = \\ ;\n assign m_axi_wdata[15] = \\ ;\n assign m_axi_wdata[14] = \\ ;\n assign m_axi_wdata[13] = \\ ;\n assign m_axi_wdata[12] = \\ ;\n assign m_axi_wdata[11] = \\ ;\n assign m_axi_wdata[10] = \\ ;\n assign m_axi_wdata[9] = \\ ;\n assign m_axi_wdata[8] = \\ ;\n assign m_axi_wdata[7] = \\ ;\n assign m_axi_wdata[6] = \\ ;\n assign m_axi_wdata[5] = \\ ;\n assign m_axi_wdata[4] = \\ ;\n assign m_axi_wdata[3] = \\ ;\n assign m_axi_wdata[2] = \\ ;\n assign m_axi_wdata[1] = \\ ;\n assign m_axi_wdata[0] = \\ ;\n assign m_axi_wid[0] = \\ ;\n assign m_axi_wlast = \\ ;\n assign m_axi_wstrb[7] = \\ ;\n assign m_axi_wstrb[6] = \\ ;\n assign m_axi_wstrb[5] = \\ ;\n assign m_axi_wstrb[4] = \\ ;\n assign m_axi_wstrb[3] = \\ ;\n assign m_axi_wstrb[2] = \\ ;\n assign m_axi_wstrb[1] = \\ ;\n assign m_axi_wstrb[0] = \\ ;\n assign m_axi_wuser[0] = \\ ;\n assign m_axi_wvalid = \\ ;\n assign m_axis_tdata[7] = \\ ;\n assign m_axis_tdata[6] = \\ ;\n assign m_axis_tdata[5] = \\ ;\n assign m_axis_tdata[4] = \\ ;\n assign m_axis_tdata[3] = \\ ;\n assign m_axis_tdata[2] = \\ ;\n assign m_axis_tdata[1] = \\ ;\n assign m_axis_tdata[0] = \\ ;\n assign m_axis_tdest[0] = \\ ;\n assign m_axis_tid[0] = \\ ;\n assign m_axis_tkeep[0] = \\ ;\n assign m_axis_tlast = \\ ;\n assign m_axis_tstrb[0] = \\ ;\n assign m_axis_tuser[3] = \\ ;\n assign m_axis_tuser[2] = \\ ;\n assign m_axis_tuser[1] = \\ ;\n assign m_axis_tuser[0] = \\ ;\n assign m_axis_tvalid = \\ ;\n assign overflow = \\ ;\n assign prog_empty = \\ ;\n assign rd_data_count[10] = \\ ;\n assign rd_data_count[9] = \\ ;\n assign rd_data_count[8] = \\ ;\n assign rd_data_count[7] = \\ ;\n assign rd_data_count[6] = \\ ;\n assign rd_data_count[5] = \\ ;\n assign rd_data_count[4] = \\ ;\n assign rd_data_count[3] = \\ ;\n assign rd_data_count[2] = \\ ;\n assign rd_data_count[1] = \\ ;\n assign rd_data_count[0] = \\ ;\n assign rd_rst_busy = \\ ;\n assign s_axi_arready = \\ ;\n assign s_axi_awready = \\ ;\n assign s_axi_bid[0] = \\ ;\n assign s_axi_bresp[1] = \\ ;\n assign s_axi_bresp[0] = \\ ;\n assign s_axi_buser[0] = \\ ;\n assign s_axi_bvalid = \\ ;\n assign s_axi_rdata[63] = \\ ;\n assign s_axi_rdata[62] = \\ ;\n assign s_axi_rdata[61] = \\ ;\n assign s_axi_rdata[60] = \\ ;\n assign s_axi_rdata[59] = \\ ;\n assign s_axi_rdata[58] = \\ ;\n assign s_axi_rdata[57] = \\ ;\n assign s_axi_rdata[56] = \\ ;\n assign s_axi_rdata[55] = \\ ;\n assign s_axi_rdata[54] = \\ ;\n assign s_axi_rdata[53] = \\ ;\n assign s_axi_rdata[52] = \\ ;\n assign s_axi_rdata[51] = \\ ;\n assign s_axi_rdata[50] = \\ ;\n assign s_axi_rdata[49] = \\ ;\n assign s_axi_rdata[48] = \\ ;\n assign s_axi_rdata[47] = \\ ;\n assign s_axi_rdata[46] = \\ ;\n assign s_axi_rdata[45] = \\ ;\n assign s_axi_rdata[44] = \\ ;\n assign s_axi_rdata[43] = \\ ;\n assign s_axi_rdata[42] = \\ ;\n assign s_axi_rdata[41] = \\ ;\n assign s_axi_rdata[40] = \\ ;\n assign s_axi_rdata[39] = \\ ;\n assign s_axi_rdata[38] = \\ ;\n assign s_axi_rdata[37] = \\ ;\n assign s_axi_rdata[36] = \\ ;\n assign s_axi_rdata[35] = \\ ;\n assign s_axi_rdata[34] = \\ ;\n assign s_axi_rdata[33] = \\ ;\n assign s_axi_rdata[32] = \\ ;\n assign s_axi_rdata[31] = \\ ;\n assign s_axi_rdata[30] = \\ ;\n assign s_axi_rdata[29] = \\ ;\n assign s_axi_rdata[28] = \\ ;\n assign s_axi_rdata[27] = \\ ;\n assign s_axi_rdata[26] = \\ ;\n assign s_axi_rdata[25] = \\ ;\n assign s_axi_rdata[24] = \\ ;\n assign s_axi_rdata[23] = \\ ;\n assign s_axi_rdata[22] = \\ ;\n assign s_axi_rdata[21] = \\ ;\n assign s_axi_rdata[20] = \\ ;\n assign s_axi_rdata[19] = \\ ;\n assign s_axi_rdata[18] = \\ ;\n assign s_axi_rdata[17] = \\ ;\n assign s_axi_rdata[16] = \\ ;\n assign s_axi_rdata[15] = \\ ;\n assign s_axi_rdata[14] = \\ ;\n assign s_axi_rdata[13] = \\ ;\n assign s_axi_rdata[12] = \\ ;\n assign s_axi_rdata[11] = \\ ;\n assign s_axi_rdata[10] = \\ ;\n assign s_axi_rdata[9] = \\ ;\n assign s_axi_rdata[8] = \\ ;\n assign s_axi_rdata[7] = \\ ;\n assign s_axi_rdata[6] = \\ ;\n assign s_axi_rdata[5] = \\ ;\n assign s_axi_rdata[4] = \\ ;\n assign s_axi_rdata[3] = \\ ;\n assign s_axi_rdata[2] = \\ ;\n assign s_axi_rdata[1] = \\ ;\n assign s_axi_rdata[0] = \\ ;\n assign s_axi_rid[0] = \\ ;\n assign s_axi_rlast = \\ ;\n assign s_axi_rresp[1] = \\ ;\n assign s_axi_rresp[0] = \\ ;\n assign s_axi_ruser[0] = \\ ;\n assign s_axi_rvalid = \\ ;\n assign s_axi_wready = \\ ;\n assign s_axis_tready = \\ ;\n assign sbiterr = \\ ;\n assign underflow = \\ ;\n assign valid = \\ ;\n assign wr_ack = \\ ;\n assign wr_data_count[8] = \\ ;\n assign wr_data_count[7] = \\ ;\n assign wr_data_count[6] = \\ ;\n assign wr_data_count[5] = \\ ;\n assign wr_data_count[4] = \\ ;\n assign wr_data_count[3] = \\ ;\n assign wr_data_count[2] = \\ ;\n assign wr_data_count[1] = \\ ;\n assign wr_data_count[0] = \\ ;\n GND GND\n (.G(\\ ));\n VCC VCC\n (.P(\\ ));\n fb_output_fifo_fifo_generator_v13_1_2_synth inst_fifo_gen\n (.WR_RST_BUSY(wr_rst_busy),\n .din(din),\n .dout(dout),\n .empty(empty),\n .full(full),\n .prog_full(prog_full),\n .rd_clk(rd_clk),\n .rd_en(rd_en),\n .rst(rst),\n .wr_clk(wr_clk),\n .wr_en(wr_en));\nendmodule\n\n(* ORIG_REF_NAME = \"fifo_generator_v13_1_2_synth\" *) \nmodule fb_output_fifo_fifo_generator_v13_1_2_synth\n (WR_RST_BUSY,\n dout,\n empty,\n full,\n prog_full,\n rd_en,\n wr_en,\n rd_clk,\n wr_clk,\n din,\n rst);\n output WR_RST_BUSY;\n output [31:0]dout;\n output empty;\n output full;\n output prog_full;\n input rd_en;\n input wr_en;\n input rd_clk;\n input wr_clk;\n input [127:0]din;\n input rst;\n\n wire WR_RST_BUSY;\n wire [127:0]din;\n wire [31:0]dout;\n wire empty;\n wire full;\n wire prog_full;\n wire rd_clk;\n wire rd_en;\n wire rst;\n wire wr_clk;\n wire wr_en;\n\n fb_output_fifo_fifo_generator_top \\gconvfifo.rf \n (.WR_RST_BUSY(WR_RST_BUSY),\n .din(din),\n .dout(dout),\n .empty(empty),\n .full(full),\n .prog_full(prog_full),\n .rd_clk(rd_clk),\n .rd_en(rd_en),\n .rst(rst),\n .wr_clk(wr_clk),\n .wr_en(wr_en));\nendmodule\n\n(* ORIG_REF_NAME = \"memory\" *) \nmodule fb_output_fifo_memory\n (dout,\n rd_clk,\n wr_clk,\n tmp_ram_rd_en,\n WEBWE,\n out,\n Q,\n \\gic0.gc0.count_d2_reg[8] ,\n din);\n output [31:0]dout;\n input rd_clk;\n input wr_clk;\n input tmp_ram_rd_en;\n input [0:0]WEBWE;\n input [0:0]out;\n input [10:0]Q;\n input [8:0]\\gic0.gc0.count_d2_reg[8] ;\n input [127:0]din;\n\n wire [10:0]Q;\n wire [0:0]WEBWE;\n wire [127:0]din;\n wire [31:0]dout;\n wire [8:0]\\gic0.gc0.count_d2_reg[8] ;\n wire [0:0]out;\n wire rd_clk;\n wire tmp_ram_rd_en;\n wire wr_clk;\n\n fb_output_fifo_blk_mem_gen_v8_3_4 \\gbm.gbmg.gbmga.ngecc.bmg \n (.Q(Q),\n .WEBWE(WEBWE),\n .din(din),\n .dout(dout),\n .\\gic0.gc0.count_d2_reg[8] (\\gic0.gc0.count_d2_reg[8] ),\n .out(out),\n .rd_clk(rd_clk),\n .tmp_ram_rd_en(tmp_ram_rd_en),\n .wr_clk(wr_clk));\nendmodule\n\n(* ORIG_REF_NAME = \"rd_bin_cntr\" *) \nmodule fb_output_fifo_rd_bin_cntr\n (ram_empty_fb_i_reg,\n Q,\n ram_empty_fb_i_reg_0,\n \\gc0.count_d1_reg[9]_0 ,\n v1_reg,\n v1_reg_0,\n WR_PNTR_RD,\n E,\n rd_clk,\n AR);\n output ram_empty_fb_i_reg;\n output [10:0]Q;\n output ram_empty_fb_i_reg_0;\n output [7:0]\\gc0.count_d1_reg[9]_0 ;\n output [0:0]v1_reg;\n output [0:0]v1_reg_0;\n input [0:0]WR_PNTR_RD;\n input [0:0]E;\n input rd_clk;\n input [0:0]AR;\n\n wire [0:0]AR;\n wire [0:0]E;\n wire [10:0]Q;\n wire [0:0]WR_PNTR_RD;\n wire \\gc0.count[10]_i_2_n_0 ;\n wire [7:0]\\gc0.count_d1_reg[9]_0 ;\n wire [10:0]plusOp__0;\n wire ram_empty_fb_i_reg;\n wire ram_empty_fb_i_reg_0;\n wire rd_clk;\n wire [10:0]rd_pntr_plus1;\n wire [0:0]v1_reg;\n wire [0:0]v1_reg_0;\n\n LUT1 #(\n .INIT(2'h1)) \n \\gc0.count[0]_i_1 \n (.I0(rd_pntr_plus1[0]),\n .O(plusOp__0[0]));\n LUT6 #(\n .INIT(64'h7FFFFFFF80000000)) \n \\gc0.count[10]_i_1 \n (.I0(\\gc0.count_d1_reg[9]_0 [6]),\n .I1(\\gc0.count_d1_reg[9]_0 [4]),\n .I2(\\gc0.count[10]_i_2_n_0 ),\n .I3(\\gc0.count_d1_reg[9]_0 [5]),\n .I4(\\gc0.count_d1_reg[9]_0 [7]),\n .I5(rd_pntr_plus1[10]),\n .O(plusOp__0[10]));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\gc0.count[10]_i_2 \n (.I0(\\gc0.count_d1_reg[9]_0 [3]),\n .I1(\\gc0.count_d1_reg[9]_0 [1]),\n .I2(rd_pntr_plus1[1]),\n .I3(rd_pntr_plus1[0]),\n .I4(\\gc0.count_d1_reg[9]_0 [0]),\n .I5(\\gc0.count_d1_reg[9]_0 [2]),\n .O(\\gc0.count[10]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair12\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gc0.count[1]_i_1 \n (.I0(rd_pntr_plus1[0]),\n .I1(rd_pntr_plus1[1]),\n .O(plusOp__0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair12\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\gc0.count[2]_i_1 \n (.I0(rd_pntr_plus1[0]),\n .I1(rd_pntr_plus1[1]),\n .I2(\\gc0.count_d1_reg[9]_0 [0]),\n .O(plusOp__0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair10\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\gc0.count[3]_i_1 \n (.I0(rd_pntr_plus1[1]),\n .I1(rd_pntr_plus1[0]),\n .I2(\\gc0.count_d1_reg[9]_0 [0]),\n .I3(\\gc0.count_d1_reg[9]_0 [1]),\n .O(plusOp__0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair10\" *) \n LUT5 #(\n .INIT(32'h7FFF8000)) \n \\gc0.count[4]_i_1 \n (.I0(\\gc0.count_d1_reg[9]_0 [0]),\n .I1(rd_pntr_plus1[0]),\n .I2(rd_pntr_plus1[1]),\n .I3(\\gc0.count_d1_reg[9]_0 [1]),\n .I4(\\gc0.count_d1_reg[9]_0 [2]),\n .O(plusOp__0[4]));\n LUT6 #(\n .INIT(64'h7FFFFFFF80000000)) \n \\gc0.count[5]_i_1 \n (.I0(\\gc0.count_d1_reg[9]_0 [1]),\n .I1(rd_pntr_plus1[1]),\n .I2(rd_pntr_plus1[0]),\n .I3(\\gc0.count_d1_reg[9]_0 [0]),\n .I4(\\gc0.count_d1_reg[9]_0 [2]),\n .I5(\\gc0.count_d1_reg[9]_0 [3]),\n .O(plusOp__0[5]));\n (* SOFT_HLUTNM = \"soft_lutpair11\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gc0.count[6]_i_1 \n (.I0(\\gc0.count[10]_i_2_n_0 ),\n .I1(\\gc0.count_d1_reg[9]_0 [4]),\n .O(plusOp__0[6]));\n (* SOFT_HLUTNM = \"soft_lutpair11\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\gc0.count[7]_i_1 \n (.I0(\\gc0.count[10]_i_2_n_0 ),\n .I1(\\gc0.count_d1_reg[9]_0 [4]),\n .I2(\\gc0.count_d1_reg[9]_0 [5]),\n .O(plusOp__0[7]));\n (* SOFT_HLUTNM = \"soft_lutpair9\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\gc0.count[8]_i_1 \n (.I0(\\gc0.count_d1_reg[9]_0 [4]),\n .I1(\\gc0.count[10]_i_2_n_0 ),\n .I2(\\gc0.count_d1_reg[9]_0 [5]),\n .I3(\\gc0.count_d1_reg[9]_0 [6]),\n .O(plusOp__0[8]));\n (* SOFT_HLUTNM = \"soft_lutpair9\" *) \n LUT5 #(\n .INIT(32'h7FFF8000)) \n \\gc0.count[9]_i_1 \n (.I0(\\gc0.count_d1_reg[9]_0 [5]),\n .I1(\\gc0.count[10]_i_2_n_0 ),\n .I2(\\gc0.count_d1_reg[9]_0 [4]),\n .I3(\\gc0.count_d1_reg[9]_0 [6]),\n .I4(\\gc0.count_d1_reg[9]_0 [7]),\n .O(plusOp__0[9]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_d1_reg[0] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(rd_pntr_plus1[0]),\n .Q(Q[0]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_d1_reg[10] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(rd_pntr_plus1[10]),\n .Q(Q[10]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_d1_reg[1] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(rd_pntr_plus1[1]),\n .Q(Q[1]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_d1_reg[2] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(\\gc0.count_d1_reg[9]_0 [0]),\n .Q(Q[2]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_d1_reg[3] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(\\gc0.count_d1_reg[9]_0 [1]),\n .Q(Q[3]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_d1_reg[4] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(\\gc0.count_d1_reg[9]_0 [2]),\n .Q(Q[4]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_d1_reg[5] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(\\gc0.count_d1_reg[9]_0 [3]),\n .Q(Q[5]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_d1_reg[6] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(\\gc0.count_d1_reg[9]_0 [4]),\n .Q(Q[6]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_d1_reg[7] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(\\gc0.count_d1_reg[9]_0 [5]),\n .Q(Q[7]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_d1_reg[8] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(\\gc0.count_d1_reg[9]_0 [6]),\n .Q(Q[8]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_d1_reg[9] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(\\gc0.count_d1_reg[9]_0 [7]),\n .Q(Q[9]));\n FDPE #(\n .INIT(1'b1)) \n \\gc0.count_reg[0] \n (.C(rd_clk),\n .CE(E),\n .D(plusOp__0[0]),\n .PRE(AR),\n .Q(rd_pntr_plus1[0]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_reg[10] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__0[10]),\n .Q(rd_pntr_plus1[10]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_reg[1] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__0[1]),\n .Q(rd_pntr_plus1[1]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_reg[2] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__0[2]),\n .Q(\\gc0.count_d1_reg[9]_0 [0]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_reg[3] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__0[3]),\n .Q(\\gc0.count_d1_reg[9]_0 [1]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_reg[4] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__0[4]),\n .Q(\\gc0.count_d1_reg[9]_0 [2]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_reg[5] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__0[5]),\n .Q(\\gc0.count_d1_reg[9]_0 [3]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_reg[6] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__0[6]),\n .Q(\\gc0.count_d1_reg[9]_0 [4]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_reg[7] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__0[7]),\n .Q(\\gc0.count_d1_reg[9]_0 [5]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_reg[8] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__0[8]),\n .Q(\\gc0.count_d1_reg[9]_0 [6]));\n FDCE #(\n .INIT(1'b0)) \n \\gc0.count_reg[9] \n (.C(rd_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__0[9]),\n .Q(\\gc0.count_d1_reg[9]_0 [7]));\n LUT2 #(\n .INIT(4'h1)) \n \\gmux.gm[0].gm1.m1_i_1 \n (.I0(Q[0]),\n .I1(Q[1]),\n .O(v1_reg));\n LUT2 #(\n .INIT(4'h1)) \n \\gmux.gm[0].gm1.m1_i_1__0 \n (.I0(rd_pntr_plus1[0]),\n .I1(rd_pntr_plus1[1]),\n .O(v1_reg_0));\n LUT2 #(\n .INIT(4'h9)) \n \\gmux.gm[5].gms.ms_i_1 \n (.I0(Q[10]),\n .I1(WR_PNTR_RD),\n .O(ram_empty_fb_i_reg));\n LUT2 #(\n .INIT(4'h9)) \n \\gmux.gm[5].gms.ms_i_1__0 \n (.I0(rd_pntr_plus1[10]),\n .I1(WR_PNTR_RD),\n .O(ram_empty_fb_i_reg_0));\nendmodule\n\n(* ORIG_REF_NAME = \"rd_logic\" *) \nmodule fb_output_fifo_rd_logic\n (empty,\n out,\n Q,\n \\gc0.count_d1_reg[9] ,\n \\gnxpm_cdc.wr_pntr_bin_reg[6] ,\n \\gnxpm_cdc.wr_pntr_bin_reg[6]_0 ,\n rd_clk,\n AR,\n rd_en,\n WR_PNTR_RD);\n output empty;\n output out;\n output [10:0]Q;\n output [7:0]\\gc0.count_d1_reg[9] ;\n input [3:0]\\gnxpm_cdc.wr_pntr_bin_reg[6] ;\n input [3:0]\\gnxpm_cdc.wr_pntr_bin_reg[6]_0 ;\n input rd_clk;\n input [0:0]AR;\n input rd_en;\n input [0:0]WR_PNTR_RD;\n\n wire [0:0]AR;\n wire [10:0]Q;\n wire [0:0]WR_PNTR_RD;\n wire [0:0]\\c0/v1_reg ;\n wire [0:0]\\c1/v1_reg ;\n wire empty;\n wire [7:0]\\gc0.count_d1_reg[9] ;\n wire [3:0]\\gnxpm_cdc.wr_pntr_bin_reg[6] ;\n wire [3:0]\\gnxpm_cdc.wr_pntr_bin_reg[6]_0 ;\n wire \\gras.rsts_n_2 ;\n wire out;\n wire rd_clk;\n wire rd_en;\n wire rpntr_n_0;\n wire rpntr_n_12;\n\n fb_output_fifo_rd_status_flags_as \\gras.rsts \n (.AR(AR),\n .E(\\gras.rsts_n_2 ),\n .empty(empty),\n .\\gc0.count_d1_reg[10] (rpntr_n_0),\n .\\gc0.count_reg[10] (rpntr_n_12),\n .\\gnxpm_cdc.wr_pntr_bin_reg[6] (\\gnxpm_cdc.wr_pntr_bin_reg[6] ),\n .\\gnxpm_cdc.wr_pntr_bin_reg[6]_0 (\\gnxpm_cdc.wr_pntr_bin_reg[6]_0 ),\n .out(out),\n .rd_clk(rd_clk),\n .rd_en(rd_en),\n .v1_reg(\\c0/v1_reg ),\n .v1_reg_0(\\c1/v1_reg ));\n fb_output_fifo_rd_bin_cntr rpntr\n (.AR(AR),\n .E(\\gras.rsts_n_2 ),\n .Q(Q),\n .WR_PNTR_RD(WR_PNTR_RD),\n .\\gc0.count_d1_reg[9]_0 (\\gc0.count_d1_reg[9] ),\n .ram_empty_fb_i_reg(rpntr_n_0),\n .ram_empty_fb_i_reg_0(rpntr_n_12),\n .rd_clk(rd_clk),\n .v1_reg(\\c0/v1_reg ),\n .v1_reg_0(\\c1/v1_reg ));\nendmodule\n\n(* ORIG_REF_NAME = \"rd_status_flags_as\" *) \nmodule fb_output_fifo_rd_status_flags_as\n (empty,\n out,\n E,\n v1_reg,\n \\gnxpm_cdc.wr_pntr_bin_reg[6] ,\n \\gc0.count_d1_reg[10] ,\n v1_reg_0,\n \\gnxpm_cdc.wr_pntr_bin_reg[6]_0 ,\n \\gc0.count_reg[10] ,\n rd_clk,\n AR,\n rd_en);\n output empty;\n output out;\n output [0:0]E;\n input [0:0]v1_reg;\n input [3:0]\\gnxpm_cdc.wr_pntr_bin_reg[6] ;\n input \\gc0.count_d1_reg[10] ;\n input [0:0]v1_reg_0;\n input [3:0]\\gnxpm_cdc.wr_pntr_bin_reg[6]_0 ;\n input \\gc0.count_reg[10] ;\n input rd_clk;\n input [0:0]AR;\n input rd_en;\n\n wire [0:0]AR;\n wire [0:0]E;\n wire c0_n_0;\n wire comp1;\n wire \\gc0.count_d1_reg[10] ;\n wire \\gc0.count_reg[10] ;\n wire [3:0]\\gnxpm_cdc.wr_pntr_bin_reg[6] ;\n wire [3:0]\\gnxpm_cdc.wr_pntr_bin_reg[6]_0 ;\n (* DONT_TOUCH *) wire ram_empty_fb_i;\n (* DONT_TOUCH *) wire ram_empty_i;\n wire rd_clk;\n wire rd_en;\n wire [0:0]v1_reg;\n wire [0:0]v1_reg_0;\n\n assign empty = ram_empty_i;\n assign out = ram_empty_fb_i;\n fb_output_fifo_compare c0\n (.comp1(comp1),\n .\\gc0.count_d1_reg[10] (\\gc0.count_d1_reg[10] ),\n .\\gnxpm_cdc.wr_pntr_bin_reg[6] (\\gnxpm_cdc.wr_pntr_bin_reg[6] ),\n .out(ram_empty_fb_i),\n .ram_empty_fb_i_reg(c0_n_0),\n .rd_en(rd_en),\n .v1_reg(v1_reg));\n fb_output_fifo_compare_3 c1\n (.comp1(comp1),\n .\\gc0.count_reg[10] (\\gc0.count_reg[10] ),\n .\\gnxpm_cdc.wr_pntr_bin_reg[6] (\\gnxpm_cdc.wr_pntr_bin_reg[6]_0 ),\n .v1_reg_0(v1_reg_0));\n LUT2 #(\n .INIT(4'h2)) \n \\gc0.count_d1[10]_i_1 \n (.I0(rd_en),\n .I1(ram_empty_fb_i),\n .O(E));\n (* DONT_TOUCH *) \n (* KEEP = \"yes\" *) \n (* equivalent_register_removal = \"no\" *) \n FDPE #(\n .INIT(1'b1)) \n ram_empty_fb_i_reg\n (.C(rd_clk),\n .CE(1'b1),\n .D(c0_n_0),\n .PRE(AR),\n .Q(ram_empty_fb_i));\n (* DONT_TOUCH *) \n (* KEEP = \"yes\" *) \n (* equivalent_register_removal = \"no\" *) \n FDPE #(\n .INIT(1'b1)) \n ram_empty_i_reg\n (.C(rd_clk),\n .CE(1'b1),\n .D(c0_n_0),\n .PRE(AR),\n .Q(ram_empty_i));\nendmodule\n\n(* ORIG_REF_NAME = \"reset_blk_ramfifo\" *) \nmodule fb_output_fifo_reset_blk_ramfifo\n (out,\n \\gc0.count_reg[1] ,\n \\grstd1.grst_full.grst_f.rst_d3_reg_0 ,\n WR_RST_BUSY,\n tmp_ram_rd_en,\n rd_clk,\n wr_clk,\n rst,\n ram_empty_fb_i_reg,\n rd_en);\n output [1:0]out;\n output [2:0]\\gc0.count_reg[1] ;\n output \\grstd1.grst_full.grst_f.rst_d3_reg_0 ;\n output WR_RST_BUSY;\n output tmp_ram_rd_en;\n input rd_clk;\n input wr_clk;\n input rst;\n input ram_empty_fb_i_reg;\n input rd_en;\n\n wire \\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ;\n wire \\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ;\n wire \\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ;\n wire \\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ;\n wire p_7_out;\n wire p_8_out;\n wire ram_empty_fb_i_reg;\n wire rd_clk;\n wire rd_en;\n wire rd_rst_asreg;\n (* DONT_TOUCH *) wire [2:0]rd_rst_reg;\n wire rst;\n (* async_reg = \"true\" *) (* msgon = \"true\" *) wire rst_d1;\n (* async_reg = \"true\" *) (* msgon = \"true\" *) wire rst_d2;\n (* async_reg = \"true\" *) (* msgon = \"true\" *) wire rst_d3;\n (* async_reg = \"true\" *) (* msgon = \"true\" *) wire rst_rd_reg1;\n (* async_reg = \"true\" *) (* msgon = \"true\" *) wire rst_rd_reg2;\n (* async_reg = \"true\" *) (* msgon = \"true\" *) wire rst_wr_reg1;\n (* async_reg = \"true\" *) (* msgon = \"true\" *) wire rst_wr_reg2;\n wire tmp_ram_rd_en;\n wire wr_clk;\n wire wr_rst_asreg;\n (* DONT_TOUCH *) wire [2:0]wr_rst_reg;\n\n assign WR_RST_BUSY = rst_d3;\n assign \\gc0.count_reg[1] [2:0] = rd_rst_reg;\n assign \\grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d2;\n assign out[1:0] = wr_rst_reg[1:0];\n LUT3 #(\n .INIT(8'hBA)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_1 \n (.I0(rd_rst_reg[0]),\n .I1(ram_empty_fb_i_reg),\n .I2(rd_en),\n .O(tmp_ram_rd_en));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDPE #(\n .INIT(1'b1)) \n \\grstd1.grst_full.grst_f.rst_d1_reg \n (.C(wr_clk),\n .CE(1'b1),\n .D(1'b0),\n .PRE(rst_wr_reg2),\n .Q(rst_d1));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDPE #(\n .INIT(1'b1)) \n \\grstd1.grst_full.grst_f.rst_d2_reg \n (.C(wr_clk),\n .CE(1'b1),\n .D(rst_d1),\n .PRE(rst_wr_reg2),\n .Q(rst_d2));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDPE #(\n .INIT(1'b1)) \n \\grstd1.grst_full.grst_f.rst_d3_reg \n (.C(wr_clk),\n .CE(1'b1),\n .D(rst_d2),\n .PRE(rst_wr_reg2),\n .Q(rst_d3));\n fb_output_fifo_synchronizer_ff \\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst \n (.in0(rd_rst_asreg),\n .\\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg (\\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ),\n .out(p_7_out),\n .rd_clk(rd_clk));\n fb_output_fifo_synchronizer_ff_0 \\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst \n (.in0(wr_rst_asreg),\n .\\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg (\\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ),\n .out(p_8_out),\n .wr_clk(wr_clk));\n fb_output_fifo_synchronizer_ff_1 \\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst \n (.AS(\\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),\n .in0(rd_rst_asreg),\n .out(p_7_out),\n .rd_clk(rd_clk));\n fb_output_fifo_synchronizer_ff_2 \\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst \n (.AS(\\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),\n .in0(wr_rst_asreg),\n .out(p_8_out),\n .wr_clk(wr_clk));\n FDPE #(\n .INIT(1'b1)) \n \\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg \n (.C(rd_clk),\n .CE(1'b1),\n .D(\\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ),\n .PRE(rst_rd_reg2),\n .Q(rd_rst_asreg));\n (* DONT_TOUCH *) \n (* KEEP = \"yes\" *) \n (* equivalent_register_removal = \"no\" *) \n FDPE #(\n .INIT(1'b1)) \n \\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] \n (.C(rd_clk),\n .CE(1'b1),\n .D(1'b0),\n .PRE(\\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),\n .Q(rd_rst_reg[0]));\n (* DONT_TOUCH *) \n (* KEEP = \"yes\" *) \n (* equivalent_register_removal = \"no\" *) \n FDPE #(\n .INIT(1'b1)) \n \\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] \n (.C(rd_clk),\n .CE(1'b1),\n .D(1'b0),\n .PRE(\\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),\n .Q(rd_rst_reg[1]));\n (* DONT_TOUCH *) \n (* KEEP = \"yes\" *) \n (* equivalent_register_removal = \"no\" *) \n FDPE #(\n .INIT(1'b1)) \n \\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] \n (.C(rd_clk),\n .CE(1'b1),\n .D(1'b0),\n .PRE(\\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),\n .Q(rd_rst_reg[2]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDPE #(\n .INIT(1'b0)) \n \\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg \n (.C(rd_clk),\n .CE(1'b1),\n .D(1'b0),\n .PRE(rst),\n .Q(rst_rd_reg1));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDPE #(\n .INIT(1'b0)) \n \\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg \n (.C(rd_clk),\n .CE(1'b1),\n .D(rst_rd_reg1),\n .PRE(rst),\n .Q(rst_rd_reg2));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDPE #(\n .INIT(1'b0)) \n \\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg \n (.C(wr_clk),\n .CE(1'b1),\n .D(1'b0),\n .PRE(rst),\n .Q(rst_wr_reg1));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDPE #(\n .INIT(1'b0)) \n \\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg \n (.C(wr_clk),\n .CE(1'b1),\n .D(rst_wr_reg1),\n .PRE(rst),\n .Q(rst_wr_reg2));\n FDPE #(\n .INIT(1'b1)) \n \\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg \n (.C(wr_clk),\n .CE(1'b1),\n .D(\\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ),\n .PRE(rst_wr_reg2),\n .Q(wr_rst_asreg));\n (* DONT_TOUCH *) \n (* KEEP = \"yes\" *) \n (* equivalent_register_removal = \"no\" *) \n FDPE #(\n .INIT(1'b1)) \n \\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] \n (.C(wr_clk),\n .CE(1'b1),\n .D(1'b0),\n .PRE(\\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),\n .Q(wr_rst_reg[0]));\n (* DONT_TOUCH *) \n (* KEEP = \"yes\" *) \n (* equivalent_register_removal = \"no\" *) \n FDPE #(\n .INIT(1'b1)) \n \\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] \n (.C(wr_clk),\n .CE(1'b1),\n .D(1'b0),\n .PRE(\\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),\n .Q(wr_rst_reg[1]));\n (* DONT_TOUCH *) \n (* KEEP = \"yes\" *) \n (* equivalent_register_removal = \"no\" *) \n FDPE #(\n .INIT(1'b1)) \n \\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2] \n (.C(wr_clk),\n .CE(1'b1),\n .D(1'b0),\n .PRE(\\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),\n .Q(wr_rst_reg[2]));\nendmodule\n\n(* ORIG_REF_NAME = \"synchronizer_ff\" *) \nmodule fb_output_fifo_synchronizer_ff\n (out,\n \\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ,\n in0,\n rd_clk);\n output out;\n output \\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ;\n input [0:0]in0;\n input rd_clk;\n\n (* async_reg = \"true\" *) (* msgon = \"true\" *) wire Q_reg;\n wire [0:0]in0;\n wire \\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ;\n wire rd_clk;\n\n assign out = Q_reg;\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDRE #(\n .INIT(1'b0)) \n \\Q_reg_reg[0] \n (.C(rd_clk),\n .CE(1'b1),\n .D(in0),\n .Q(Q_reg),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h2)) \n \\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1 \n (.I0(in0),\n .I1(Q_reg),\n .O(\\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ));\nendmodule\n\n(* ORIG_REF_NAME = \"synchronizer_ff\" *) \nmodule fb_output_fifo_synchronizer_ff_0\n (out,\n \\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ,\n in0,\n wr_clk);\n output out;\n output \\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ;\n input [0:0]in0;\n input wr_clk;\n\n (* async_reg = \"true\" *) (* msgon = \"true\" *) wire Q_reg;\n wire [0:0]in0;\n wire \\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ;\n wire wr_clk;\n\n assign out = Q_reg;\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDRE #(\n .INIT(1'b0)) \n \\Q_reg_reg[0] \n (.C(wr_clk),\n .CE(1'b1),\n .D(in0),\n .Q(Q_reg),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h2)) \n \\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1 \n (.I0(in0),\n .I1(Q_reg),\n .O(\\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ));\nendmodule\n\n(* ORIG_REF_NAME = \"synchronizer_ff\" *) \nmodule fb_output_fifo_synchronizer_ff_1\n (AS,\n out,\n rd_clk,\n in0);\n output [0:0]AS;\n input out;\n input rd_clk;\n input [0:0]in0;\n\n wire [0:0]AS;\n (* async_reg = \"true\" *) (* msgon = \"true\" *) wire Q_reg;\n wire [0:0]in0;\n wire out;\n wire rd_clk;\n\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDRE #(\n .INIT(1'b0)) \n \\Q_reg_reg[0] \n (.C(rd_clk),\n .CE(1'b1),\n .D(out),\n .Q(Q_reg),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h2)) \n \\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1 \n (.I0(in0),\n .I1(Q_reg),\n .O(AS));\nendmodule\n\n(* ORIG_REF_NAME = \"synchronizer_ff\" *) \nmodule fb_output_fifo_synchronizer_ff_2\n (AS,\n out,\n wr_clk,\n in0);\n output [0:0]AS;\n input out;\n input wr_clk;\n input [0:0]in0;\n\n wire [0:0]AS;\n (* async_reg = \"true\" *) (* msgon = \"true\" *) wire Q_reg;\n wire [0:0]in0;\n wire out;\n wire wr_clk;\n\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDRE #(\n .INIT(1'b0)) \n \\Q_reg_reg[0] \n (.C(wr_clk),\n .CE(1'b1),\n .D(out),\n .Q(Q_reg),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h2)) \n \\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1 \n (.I0(in0),\n .I1(Q_reg),\n .O(AS));\nendmodule\n\n(* ORIG_REF_NAME = \"synchronizer_ff\" *) \nmodule fb_output_fifo_synchronizer_ff__parameterized0\n (D,\n Q,\n rd_clk,\n \\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );\n output [8:0]D;\n input [8:0]Q;\n input rd_clk;\n input [0:0]\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;\n\n wire [8:0]Q;\n (* async_reg = \"true\" *) (* msgon = \"true\" *) wire [8:0]Q_reg;\n wire [0:0]\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;\n wire rd_clk;\n\n assign D[8:0] = Q_reg;\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[0] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(Q[0]),\n .Q(Q_reg[0]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[1] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(Q[1]),\n .Q(Q_reg[1]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[2] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(Q[2]),\n .Q(Q_reg[2]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[3] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(Q[3]),\n .Q(Q_reg[3]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[4] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(Q[4]),\n .Q(Q_reg[4]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[5] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(Q[5]),\n .Q(Q_reg[5]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[6] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(Q[6]),\n .Q(Q_reg[6]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[7] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(Q[7]),\n .Q(Q_reg[7]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[8] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(Q[8]),\n .Q(Q_reg[8]));\nendmodule\n\n(* ORIG_REF_NAME = \"synchronizer_ff\" *) \nmodule fb_output_fifo_synchronizer_ff__parameterized1\n (D,\n Q,\n wr_clk,\n AR);\n output [10:0]D;\n input [10:0]Q;\n input wr_clk;\n input [0:0]AR;\n\n wire [0:0]AR;\n wire [10:0]Q;\n (* async_reg = \"true\" *) (* msgon = \"true\" *) wire [10:0]Q_reg;\n wire wr_clk;\n\n assign D[10:0] = Q_reg;\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[0] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(Q[0]),\n .Q(Q_reg[0]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[10] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(Q[10]),\n .Q(Q_reg[10]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[1] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(Q[1]),\n .Q(Q_reg[1]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[2] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(Q[2]),\n .Q(Q_reg[2]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[3] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(Q[3]),\n .Q(Q_reg[3]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[4] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(Q[4]),\n .Q(Q_reg[4]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[5] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(Q[5]),\n .Q(Q_reg[5]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[6] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(Q[6]),\n .Q(Q_reg[6]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[7] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(Q[7]),\n .Q(Q_reg[7]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[8] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(Q[8]),\n .Q(Q_reg[8]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[9] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(Q[9]),\n .Q(Q_reg[9]));\nendmodule\n\n(* ORIG_REF_NAME = \"synchronizer_ff\" *) \nmodule fb_output_fifo_synchronizer_ff__parameterized2\n (out,\n \\gnxpm_cdc.wr_pntr_bin_reg[7] ,\n D,\n rd_clk,\n \\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );\n output [0:0]out;\n output [7:0]\\gnxpm_cdc.wr_pntr_bin_reg[7] ;\n input [8:0]D;\n input rd_clk;\n input [0:0]\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;\n\n wire [8:0]D;\n (* async_reg = \"true\" *) (* msgon = \"true\" *) wire [8:0]Q_reg;\n wire \\gnxpm_cdc.wr_pntr_bin[1]_i_2_n_0 ;\n wire \\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ;\n wire [7:0]\\gnxpm_cdc.wr_pntr_bin_reg[7] ;\n wire [0:0]\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;\n wire rd_clk;\n\n assign out[0] = Q_reg[8];\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[0] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(D[0]),\n .Q(Q_reg[0]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[1] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(D[1]),\n .Q(Q_reg[1]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[2] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(D[2]),\n .Q(Q_reg[2]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[3] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(D[3]),\n .Q(Q_reg[3]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[4] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(D[4]),\n .Q(Q_reg[4]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[5] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(D[5]),\n .Q(Q_reg[5]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[6] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(D[6]),\n .Q(Q_reg[6]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[7] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(D[7]),\n .Q(Q_reg[7]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[8] \n (.C(rd_clk),\n .CE(1'b1),\n .CLR(\\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),\n .D(D[8]),\n .Q(Q_reg[8]));\n LUT6 #(\n .INIT(64'h6996966996696996)) \n \\gnxpm_cdc.wr_pntr_bin[0]_i_1 \n (.I0(Q_reg[1]),\n .I1(Q_reg[0]),\n .I2(\\gnxpm_cdc.wr_pntr_bin[1]_i_2_n_0 ),\n .I3(Q_reg[3]),\n .I4(Q_reg[2]),\n .I5(Q_reg[8]),\n .O(\\gnxpm_cdc.wr_pntr_bin_reg[7] [0]));\n LUT5 #(\n .INIT(32'h96696996)) \n \\gnxpm_cdc.wr_pntr_bin[1]_i_1 \n (.I0(\\gnxpm_cdc.wr_pntr_bin[1]_i_2_n_0 ),\n .I1(Q_reg[3]),\n .I2(Q_reg[2]),\n .I3(Q_reg[8]),\n .I4(Q_reg[1]),\n .O(\\gnxpm_cdc.wr_pntr_bin_reg[7] [1]));\n LUT4 #(\n .INIT(16'h6996)) \n \\gnxpm_cdc.wr_pntr_bin[1]_i_2 \n (.I0(Q_reg[7]),\n .I1(Q_reg[6]),\n .I2(Q_reg[5]),\n .I3(Q_reg[4]),\n .O(\\gnxpm_cdc.wr_pntr_bin[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h6996966996696996)) \n \\gnxpm_cdc.wr_pntr_bin[2]_i_1 \n (.I0(Q_reg[8]),\n .I1(Q_reg[2]),\n .I2(Q_reg[3]),\n .I3(\\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ),\n .I4(Q_reg[6]),\n .I5(Q_reg[7]),\n .O(\\gnxpm_cdc.wr_pntr_bin_reg[7] [2]));\n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.wr_pntr_bin[2]_i_2 \n (.I0(Q_reg[4]),\n .I1(Q_reg[5]),\n .O(\\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h6996966996696996)) \n \\gnxpm_cdc.wr_pntr_bin[3]_i_1 \n (.I0(Q_reg[5]),\n .I1(Q_reg[3]),\n .I2(Q_reg[4]),\n .I3(Q_reg[8]),\n .I4(Q_reg[6]),\n .I5(Q_reg[7]),\n .O(\\gnxpm_cdc.wr_pntr_bin_reg[7] [3]));\n LUT5 #(\n .INIT(32'h96696996)) \n \\gnxpm_cdc.wr_pntr_bin[4]_i_1 \n (.I0(Q_reg[6]),\n .I1(Q_reg[4]),\n .I2(Q_reg[5]),\n .I3(Q_reg[8]),\n .I4(Q_reg[7]),\n .O(\\gnxpm_cdc.wr_pntr_bin_reg[7] [4]));\n LUT4 #(\n .INIT(16'h6996)) \n \\gnxpm_cdc.wr_pntr_bin[5]_i_1 \n (.I0(Q_reg[6]),\n .I1(Q_reg[5]),\n .I2(Q_reg[8]),\n .I3(Q_reg[7]),\n .O(\\gnxpm_cdc.wr_pntr_bin_reg[7] [5]));\n LUT3 #(\n .INIT(8'h96)) \n \\gnxpm_cdc.wr_pntr_bin[6]_i_1 \n (.I0(Q_reg[7]),\n .I1(Q_reg[6]),\n .I2(Q_reg[8]),\n .O(\\gnxpm_cdc.wr_pntr_bin_reg[7] [6]));\n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.wr_pntr_bin[7]_i_1 \n (.I0(Q_reg[7]),\n .I1(Q_reg[8]),\n .O(\\gnxpm_cdc.wr_pntr_bin_reg[7] [7]));\nendmodule\n\n(* ORIG_REF_NAME = \"synchronizer_ff\" *) \nmodule fb_output_fifo_synchronizer_ff__parameterized3\n (out,\n \\gnxpm_cdc.rd_pntr_bin_reg[9] ,\n D,\n wr_clk,\n AR);\n output [0:0]out;\n output [7:0]\\gnxpm_cdc.rd_pntr_bin_reg[9] ;\n input [10:0]D;\n input wr_clk;\n input [0:0]AR;\n\n wire [0:0]AR;\n wire [10:0]D;\n (* async_reg = \"true\" *) (* msgon = \"true\" *) wire [10:0]Q_reg;\n wire \\gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0 ;\n wire \\gnxpm_cdc.rd_pntr_bin[4]_i_2_n_0 ;\n wire [7:0]\\gnxpm_cdc.rd_pntr_bin_reg[9] ;\n wire wr_clk;\n\n assign out[0] = Q_reg[10];\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[0] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(D[0]),\n .Q(Q_reg[0]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[10] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(D[10]),\n .Q(Q_reg[10]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[1] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(D[1]),\n .Q(Q_reg[1]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[2] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(D[2]),\n .Q(Q_reg[2]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[3] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(D[3]),\n .Q(Q_reg[3]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[4] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(D[4]),\n .Q(Q_reg[4]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[5] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(D[5]),\n .Q(Q_reg[5]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[6] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(D[6]),\n .Q(Q_reg[6]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[7] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(D[7]),\n .Q(Q_reg[7]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[8] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(D[8]),\n .Q(Q_reg[8]));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* msgon = \"true\" *) \n FDCE #(\n .INIT(1'b0)) \n \\Q_reg_reg[9] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(D[9]),\n .Q(Q_reg[9]));\n LUT6 #(\n .INIT(64'h6996966996696996)) \n \\gnxpm_cdc.rd_pntr_bin[2]_i_1 \n (.I0(Q_reg[3]),\n .I1(Q_reg[2]),\n .I2(\\gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0 ),\n .I3(Q_reg[5]),\n .I4(Q_reg[4]),\n .I5(Q_reg[10]),\n .O(\\gnxpm_cdc.rd_pntr_bin_reg[9] [0]));\n LUT5 #(\n .INIT(32'h96696996)) \n \\gnxpm_cdc.rd_pntr_bin[3]_i_1 \n (.I0(\\gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0 ),\n .I1(Q_reg[5]),\n .I2(Q_reg[4]),\n .I3(Q_reg[10]),\n .I4(Q_reg[3]),\n .O(\\gnxpm_cdc.rd_pntr_bin_reg[9] [1]));\n LUT4 #(\n .INIT(16'h6996)) \n \\gnxpm_cdc.rd_pntr_bin[3]_i_2 \n (.I0(Q_reg[9]),\n .I1(Q_reg[8]),\n .I2(Q_reg[7]),\n .I3(Q_reg[6]),\n .O(\\gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h6996966996696996)) \n \\gnxpm_cdc.rd_pntr_bin[4]_i_1 \n (.I0(Q_reg[10]),\n .I1(Q_reg[4]),\n .I2(Q_reg[5]),\n .I3(\\gnxpm_cdc.rd_pntr_bin[4]_i_2_n_0 ),\n .I4(Q_reg[8]),\n .I5(Q_reg[9]),\n .O(\\gnxpm_cdc.rd_pntr_bin_reg[9] [2]));\n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.rd_pntr_bin[4]_i_2 \n (.I0(Q_reg[6]),\n .I1(Q_reg[7]),\n .O(\\gnxpm_cdc.rd_pntr_bin[4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h6996966996696996)) \n \\gnxpm_cdc.rd_pntr_bin[5]_i_1 \n (.I0(Q_reg[7]),\n .I1(Q_reg[5]),\n .I2(Q_reg[6]),\n .I3(Q_reg[10]),\n .I4(Q_reg[8]),\n .I5(Q_reg[9]),\n .O(\\gnxpm_cdc.rd_pntr_bin_reg[9] [3]));\n LUT5 #(\n .INIT(32'h96696996)) \n \\gnxpm_cdc.rd_pntr_bin[6]_i_1 \n (.I0(Q_reg[8]),\n .I1(Q_reg[6]),\n .I2(Q_reg[7]),\n .I3(Q_reg[10]),\n .I4(Q_reg[9]),\n .O(\\gnxpm_cdc.rd_pntr_bin_reg[9] [4]));\n LUT4 #(\n .INIT(16'h6996)) \n \\gnxpm_cdc.rd_pntr_bin[7]_i_1 \n (.I0(Q_reg[8]),\n .I1(Q_reg[7]),\n .I2(Q_reg[10]),\n .I3(Q_reg[9]),\n .O(\\gnxpm_cdc.rd_pntr_bin_reg[9] [5]));\n LUT3 #(\n .INIT(8'h96)) \n \\gnxpm_cdc.rd_pntr_bin[8]_i_1 \n (.I0(Q_reg[9]),\n .I1(Q_reg[8]),\n .I2(Q_reg[10]),\n .O(\\gnxpm_cdc.rd_pntr_bin_reg[9] [6]));\n LUT2 #(\n .INIT(4'h6)) \n \\gnxpm_cdc.rd_pntr_bin[9]_i_1 \n (.I0(Q_reg[9]),\n .I1(Q_reg[10]),\n .O(\\gnxpm_cdc.rd_pntr_bin_reg[9] [7]));\nendmodule\n\n(* ORIG_REF_NAME = \"wr_bin_cntr\" *) \nmodule fb_output_fifo_wr_bin_cntr\n (S,\n Q,\n \\gdiff.diff_pntr_pad_reg[8] ,\n \\gdiff.diff_pntr_pad_reg[9] ,\n \\gic0.gc0.count_d1_reg[8]_0 ,\n v1_reg,\n v1_reg_0,\n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ,\n RD_PNTR_WR,\n E,\n wr_clk,\n AR);\n output [3:0]S;\n output [8:0]Q;\n output [3:0]\\gdiff.diff_pntr_pad_reg[8] ;\n output [0:0]\\gdiff.diff_pntr_pad_reg[9] ;\n output [0:0]\\gic0.gc0.count_d1_reg[8]_0 ;\n output [3:0]v1_reg;\n output [3:0]v1_reg_0;\n output [8:0]\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;\n input [8:0]RD_PNTR_WR;\n input [0:0]E;\n input wr_clk;\n input [0:0]AR;\n\n wire [0:0]AR;\n wire [8:0]\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;\n wire [0:0]E;\n wire [8:0]Q;\n wire [8:0]RD_PNTR_WR;\n wire [3:0]S;\n wire [3:0]\\gdiff.diff_pntr_pad_reg[8] ;\n wire [0:0]\\gdiff.diff_pntr_pad_reg[9] ;\n wire \\gic0.gc0.count[8]_i_2_n_0 ;\n wire [0:0]\\gic0.gc0.count_d1_reg[8]_0 ;\n wire [8:0]plusOp__1;\n wire [3:0]v1_reg;\n wire [3:0]v1_reg_0;\n wire wr_clk;\n wire [7:0]wr_pntr_plus2;\n\n (* SOFT_HLUTNM = \"soft_lutpair15\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gic0.gc0.count[0]_i_1 \n (.I0(wr_pntr_plus2[0]),\n .O(plusOp__1[0]));\n LUT2 #(\n .INIT(4'h6)) \n \\gic0.gc0.count[1]_i_1 \n (.I0(wr_pntr_plus2[0]),\n .I1(wr_pntr_plus2[1]),\n .O(plusOp__1[1]));\n (* SOFT_HLUTNM = \"soft_lutpair15\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\gic0.gc0.count[2]_i_1 \n (.I0(wr_pntr_plus2[0]),\n .I1(wr_pntr_plus2[1]),\n .I2(wr_pntr_plus2[2]),\n .O(plusOp__1[2]));\n (* SOFT_HLUTNM = \"soft_lutpair13\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\gic0.gc0.count[3]_i_1 \n (.I0(wr_pntr_plus2[1]),\n .I1(wr_pntr_plus2[0]),\n .I2(wr_pntr_plus2[2]),\n .I3(wr_pntr_plus2[3]),\n .O(plusOp__1[3]));\n (* SOFT_HLUTNM = \"soft_lutpair13\" *) \n LUT5 #(\n .INIT(32'h7FFF8000)) \n \\gic0.gc0.count[4]_i_1 \n (.I0(wr_pntr_plus2[2]),\n .I1(wr_pntr_plus2[0]),\n .I2(wr_pntr_plus2[1]),\n .I3(wr_pntr_plus2[3]),\n .I4(wr_pntr_plus2[4]),\n .O(plusOp__1[4]));\n LUT6 #(\n .INIT(64'h7FFFFFFF80000000)) \n \\gic0.gc0.count[5]_i_1 \n (.I0(wr_pntr_plus2[3]),\n .I1(wr_pntr_plus2[1]),\n .I2(wr_pntr_plus2[0]),\n .I3(wr_pntr_plus2[2]),\n .I4(wr_pntr_plus2[4]),\n .I5(wr_pntr_plus2[5]),\n .O(plusOp__1[5]));\n LUT2 #(\n .INIT(4'h6)) \n \\gic0.gc0.count[6]_i_1 \n (.I0(\\gic0.gc0.count[8]_i_2_n_0 ),\n .I1(wr_pntr_plus2[6]),\n .O(plusOp__1[6]));\n (* SOFT_HLUTNM = \"soft_lutpair14\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\gic0.gc0.count[7]_i_1 \n (.I0(\\gic0.gc0.count[8]_i_2_n_0 ),\n .I1(wr_pntr_plus2[6]),\n .I2(wr_pntr_plus2[7]),\n .O(plusOp__1[7]));\n (* SOFT_HLUTNM = \"soft_lutpair14\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\gic0.gc0.count[8]_i_1 \n (.I0(wr_pntr_plus2[6]),\n .I1(\\gic0.gc0.count[8]_i_2_n_0 ),\n .I2(wr_pntr_plus2[7]),\n .I3(\\gic0.gc0.count_d1_reg[8]_0 ),\n .O(plusOp__1[8]));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\gic0.gc0.count[8]_i_2 \n (.I0(wr_pntr_plus2[5]),\n .I1(wr_pntr_plus2[3]),\n .I2(wr_pntr_plus2[1]),\n .I3(wr_pntr_plus2[0]),\n .I4(wr_pntr_plus2[2]),\n .I5(wr_pntr_plus2[4]),\n .O(\\gic0.gc0.count[8]_i_2_n_0 ));\n FDPE #(\n .INIT(1'b1)) \n \\gic0.gc0.count_d1_reg[0] \n (.C(wr_clk),\n .CE(E),\n .D(wr_pntr_plus2[0]),\n .PRE(AR),\n .Q(Q[0]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d1_reg[1] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(wr_pntr_plus2[1]),\n .Q(Q[1]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d1_reg[2] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(wr_pntr_plus2[2]),\n .Q(Q[2]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d1_reg[3] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(wr_pntr_plus2[3]),\n .Q(Q[3]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d1_reg[4] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(wr_pntr_plus2[4]),\n .Q(Q[4]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d1_reg[5] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(wr_pntr_plus2[5]),\n .Q(Q[5]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d1_reg[6] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(wr_pntr_plus2[6]),\n .Q(Q[6]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d1_reg[7] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(wr_pntr_plus2[7]),\n .Q(Q[7]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d1_reg[8] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(\\gic0.gc0.count_d1_reg[8]_0 ),\n .Q(Q[8]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d2_reg[0] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(Q[0]),\n .Q(\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [0]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d2_reg[1] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(Q[1]),\n .Q(\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [1]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d2_reg[2] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(Q[2]),\n .Q(\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [2]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d2_reg[3] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(Q[3]),\n .Q(\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [3]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d2_reg[4] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(Q[4]),\n .Q(\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [4]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d2_reg[5] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(Q[5]),\n .Q(\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [5]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d2_reg[6] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(Q[6]),\n .Q(\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [6]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d2_reg[7] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(Q[7]),\n .Q(\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [7]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_d2_reg[8] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(Q[8]),\n .Q(\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [8]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_reg[0] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__1[0]),\n .Q(wr_pntr_plus2[0]));\n FDPE #(\n .INIT(1'b1)) \n \\gic0.gc0.count_reg[1] \n (.C(wr_clk),\n .CE(E),\n .D(plusOp__1[1]),\n .PRE(AR),\n .Q(wr_pntr_plus2[1]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_reg[2] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__1[2]),\n .Q(wr_pntr_plus2[2]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_reg[3] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__1[3]),\n .Q(wr_pntr_plus2[3]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_reg[4] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__1[4]),\n .Q(wr_pntr_plus2[4]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_reg[5] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__1[5]),\n .Q(wr_pntr_plus2[5]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_reg[6] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__1[6]),\n .Q(wr_pntr_plus2[6]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_reg[7] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__1[7]),\n .Q(wr_pntr_plus2[7]));\n FDCE #(\n .INIT(1'b0)) \n \\gic0.gc0.count_reg[8] \n (.C(wr_clk),\n .CE(E),\n .CLR(AR),\n .D(plusOp__1[8]),\n .Q(\\gic0.gc0.count_d1_reg[8]_0 ));\n LUT4 #(\n .INIT(16'h9009)) \n \\gmux.gm[0].gm1.m1_i_1__1 \n (.I0(Q[0]),\n .I1(RD_PNTR_WR[0]),\n .I2(Q[1]),\n .I3(RD_PNTR_WR[1]),\n .O(v1_reg[0]));\n LUT4 #(\n .INIT(16'h9009)) \n \\gmux.gm[0].gm1.m1_i_1__2 \n (.I0(wr_pntr_plus2[0]),\n .I1(RD_PNTR_WR[0]),\n .I2(wr_pntr_plus2[1]),\n .I3(RD_PNTR_WR[1]),\n .O(v1_reg_0[0]));\n LUT4 #(\n .INIT(16'h9009)) \n \\gmux.gm[1].gms.ms_i_1__1 \n (.I0(Q[2]),\n .I1(RD_PNTR_WR[2]),\n .I2(Q[3]),\n .I3(RD_PNTR_WR[3]),\n .O(v1_reg[1]));\n LUT4 #(\n .INIT(16'h9009)) \n \\gmux.gm[1].gms.ms_i_1__2 \n (.I0(wr_pntr_plus2[2]),\n .I1(RD_PNTR_WR[2]),\n .I2(wr_pntr_plus2[3]),\n .I3(RD_PNTR_WR[3]),\n .O(v1_reg_0[1]));\n LUT4 #(\n .INIT(16'h9009)) \n \\gmux.gm[2].gms.ms_i_1__1 \n (.I0(Q[4]),\n .I1(RD_PNTR_WR[4]),\n .I2(Q[5]),\n .I3(RD_PNTR_WR[5]),\n .O(v1_reg[2]));\n LUT4 #(\n .INIT(16'h9009)) \n \\gmux.gm[2].gms.ms_i_1__2 \n (.I0(wr_pntr_plus2[4]),\n .I1(RD_PNTR_WR[4]),\n .I2(wr_pntr_plus2[5]),\n .I3(RD_PNTR_WR[5]),\n .O(v1_reg_0[2]));\n LUT4 #(\n .INIT(16'h9009)) \n \\gmux.gm[3].gms.ms_i_1__1 \n (.I0(Q[6]),\n .I1(RD_PNTR_WR[6]),\n .I2(Q[7]),\n .I3(RD_PNTR_WR[7]),\n .O(v1_reg[3]));\n LUT4 #(\n .INIT(16'h9009)) \n \\gmux.gm[3].gms.ms_i_1__2 \n (.I0(wr_pntr_plus2[6]),\n .I1(RD_PNTR_WR[6]),\n .I2(wr_pntr_plus2[7]),\n .I3(RD_PNTR_WR[7]),\n .O(v1_reg_0[3]));\n LUT2 #(\n .INIT(4'h9)) \n plusOp_carry__0_i_1\n (.I0(Q[7]),\n .I1(RD_PNTR_WR[7]),\n .O(\\gdiff.diff_pntr_pad_reg[8] [3]));\n LUT2 #(\n .INIT(4'h9)) \n plusOp_carry__0_i_2\n (.I0(Q[6]),\n .I1(RD_PNTR_WR[6]),\n .O(\\gdiff.diff_pntr_pad_reg[8] [2]));\n LUT2 #(\n .INIT(4'h9)) \n plusOp_carry__0_i_3\n (.I0(Q[5]),\n .I1(RD_PNTR_WR[5]),\n .O(\\gdiff.diff_pntr_pad_reg[8] [1]));\n LUT2 #(\n .INIT(4'h9)) \n plusOp_carry__0_i_4\n (.I0(Q[4]),\n .I1(RD_PNTR_WR[4]),\n .O(\\gdiff.diff_pntr_pad_reg[8] [0]));\n LUT2 #(\n .INIT(4'h9)) \n plusOp_carry__1_i_1\n (.I0(Q[8]),\n .I1(RD_PNTR_WR[8]),\n .O(\\gdiff.diff_pntr_pad_reg[9] ));\n LUT2 #(\n .INIT(4'h9)) \n plusOp_carry_i_1\n (.I0(Q[3]),\n .I1(RD_PNTR_WR[3]),\n .O(S[3]));\n LUT2 #(\n .INIT(4'h9)) \n plusOp_carry_i_2\n (.I0(Q[2]),\n .I1(RD_PNTR_WR[2]),\n .O(S[2]));\n LUT2 #(\n .INIT(4'h9)) \n plusOp_carry_i_3\n (.I0(Q[1]),\n .I1(RD_PNTR_WR[1]),\n .O(S[1]));\n LUT2 #(\n .INIT(4'h9)) \n plusOp_carry_i_4\n (.I0(Q[0]),\n .I1(RD_PNTR_WR[0]),\n .O(S[0]));\nendmodule\n\n(* ORIG_REF_NAME = \"wr_logic\" *) \nmodule fb_output_fifo_wr_logic\n (full,\n prog_full,\n Q,\n WEBWE,\n \\gic0.gc0.count_d1_reg[8] ,\n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ,\n \\gnxpm_cdc.rd_pntr_bin_reg[10] ,\n \\gnxpm_cdc.rd_pntr_bin_reg[10]_0 ,\n wr_clk,\n out,\n RD_PNTR_WR,\n wr_en,\n \\grstd1.grst_full.grst_f.rst_d3_reg ,\n AR);\n output full;\n output prog_full;\n output [0:0]Q;\n output [0:0]WEBWE;\n output [0:0]\\gic0.gc0.count_d1_reg[8] ;\n output [8:0]\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;\n input \\gnxpm_cdc.rd_pntr_bin_reg[10] ;\n input \\gnxpm_cdc.rd_pntr_bin_reg[10]_0 ;\n input wr_clk;\n input out;\n input [8:0]RD_PNTR_WR;\n input wr_en;\n input \\grstd1.grst_full.grst_f.rst_d3_reg ;\n input [0:0]AR;\n\n wire [0:0]AR;\n wire [8:0]\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ;\n wire [0:0]Q;\n wire [8:0]RD_PNTR_WR;\n wire [0:0]WEBWE;\n wire [3:0]\\c1/v1_reg ;\n wire [3:0]\\c2/v1_reg ;\n wire full;\n wire [0:0]\\gic0.gc0.count_d1_reg[8] ;\n wire \\gnxpm_cdc.rd_pntr_bin_reg[10] ;\n wire \\gnxpm_cdc.rd_pntr_bin_reg[10]_0 ;\n wire \\grstd1.grst_full.grst_f.rst_d3_reg ;\n wire \\gwas.wsts_n_1 ;\n wire out;\n wire [7:0]p_13_out;\n wire prog_full;\n wire wpntr_n_0;\n wire wpntr_n_1;\n wire wpntr_n_13;\n wire wpntr_n_14;\n wire wpntr_n_15;\n wire wpntr_n_16;\n wire wpntr_n_17;\n wire wpntr_n_2;\n wire wpntr_n_3;\n wire wr_clk;\n wire wr_en;\n\n fb_output_fifo_wr_pf_as \\gwas.gpf.wrpf \n (.AR(AR),\n .E(WEBWE),\n .Q(p_13_out),\n .S({wpntr_n_0,wpntr_n_1,wpntr_n_2,wpntr_n_3}),\n .\\gic0.gc0.count_d1_reg[7] ({wpntr_n_13,wpntr_n_14,wpntr_n_15,wpntr_n_16}),\n .\\gic0.gc0.count_d1_reg[8] (wpntr_n_17),\n .\\grstd1.grst_full.grst_f.rst_d3_reg (\\grstd1.grst_full.grst_f.rst_d3_reg ),\n .out(out),\n .prog_full(prog_full),\n .ram_full_fb_i_reg(\\gwas.wsts_n_1 ),\n .wr_clk(wr_clk));\n fb_output_fifo_wr_status_flags_as \\gwas.wsts \n (.E(WEBWE),\n .full(full),\n .\\gnxpm_cdc.rd_pntr_bin_reg[10] (\\gnxpm_cdc.rd_pntr_bin_reg[10] ),\n .\\gnxpm_cdc.rd_pntr_bin_reg[10]_0 (\\gnxpm_cdc.rd_pntr_bin_reg[10]_0 ),\n .\\grstd1.grst_full.grst_f.rst_d2_reg (out),\n .\\grstd1.grst_full.grst_f.rst_d3_reg (\\grstd1.grst_full.grst_f.rst_d3_reg ),\n .out(\\gwas.wsts_n_1 ),\n .v1_reg(\\c1/v1_reg ),\n .v1_reg_0(\\c2/v1_reg ),\n .wr_clk(wr_clk),\n .wr_en(wr_en));\n fb_output_fifo_wr_bin_cntr wpntr\n (.AR(AR),\n .\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ),\n .E(WEBWE),\n .Q({Q,p_13_out}),\n .RD_PNTR_WR(RD_PNTR_WR),\n .S({wpntr_n_0,wpntr_n_1,wpntr_n_2,wpntr_n_3}),\n .\\gdiff.diff_pntr_pad_reg[8] ({wpntr_n_13,wpntr_n_14,wpntr_n_15,wpntr_n_16}),\n .\\gdiff.diff_pntr_pad_reg[9] (wpntr_n_17),\n .\\gic0.gc0.count_d1_reg[8]_0 (\\gic0.gc0.count_d1_reg[8] ),\n .v1_reg(\\c1/v1_reg ),\n .v1_reg_0(\\c2/v1_reg ),\n .wr_clk(wr_clk));\nendmodule\n\n(* ORIG_REF_NAME = \"wr_pf_as\" *) \nmodule fb_output_fifo_wr_pf_as\n (prog_full,\n wr_clk,\n out,\n E,\n Q,\n S,\n \\gic0.gc0.count_d1_reg[7] ,\n \\gic0.gc0.count_d1_reg[8] ,\n \\grstd1.grst_full.grst_f.rst_d3_reg ,\n ram_full_fb_i_reg,\n AR);\n output prog_full;\n input wr_clk;\n input out;\n input [0:0]E;\n input [7:0]Q;\n input [3:0]S;\n input [3:0]\\gic0.gc0.count_d1_reg[7] ;\n input [0:0]\\gic0.gc0.count_d1_reg[8] ;\n input \\grstd1.grst_full.grst_f.rst_d3_reg ;\n input ram_full_fb_i_reg;\n input [0:0]AR;\n\n wire [0:0]AR;\n wire [0:0]E;\n wire [7:0]Q;\n wire [3:0]S;\n wire [8:4]diff_pntr;\n wire [3:0]\\gic0.gc0.count_d1_reg[7] ;\n wire [0:0]\\gic0.gc0.count_d1_reg[8] ;\n wire \\gpf1.prog_full_i_i_1_n_0 ;\n wire \\grstd1.grst_full.grst_f.rst_d3_reg ;\n wire out;\n wire [9:5]plusOp;\n wire plusOp_carry__0_n_0;\n wire plusOp_carry__0_n_1;\n wire plusOp_carry__0_n_2;\n wire plusOp_carry__0_n_3;\n wire plusOp_carry_n_0;\n wire plusOp_carry_n_1;\n wire plusOp_carry_n_2;\n wire plusOp_carry_n_3;\n wire prog_full;\n wire prog_full_i;\n wire ram_full_fb_i_reg;\n wire wr_clk;\n wire [3:0]NLW_plusOp_carry_O_UNCONNECTED;\n wire [3:0]NLW_plusOp_carry__1_CO_UNCONNECTED;\n wire [3:1]NLW_plusOp_carry__1_O_UNCONNECTED;\n\n FDCE #(\n .INIT(1'b0)) \n \\gdiff.diff_pntr_pad_reg[5] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(plusOp[5]),\n .Q(diff_pntr[4]));\n FDCE #(\n .INIT(1'b0)) \n \\gdiff.diff_pntr_pad_reg[6] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(plusOp[6]),\n .Q(diff_pntr[5]));\n FDCE #(\n .INIT(1'b0)) \n \\gdiff.diff_pntr_pad_reg[7] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(plusOp[7]),\n .Q(diff_pntr[6]));\n FDCE #(\n .INIT(1'b0)) \n \\gdiff.diff_pntr_pad_reg[8] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(plusOp[8]),\n .Q(diff_pntr[7]));\n FDCE #(\n .INIT(1'b0)) \n \\gdiff.diff_pntr_pad_reg[9] \n (.C(wr_clk),\n .CE(1'b1),\n .CLR(AR),\n .D(plusOp[9]),\n .Q(diff_pntr[8]));\n LUT4 #(\n .INIT(16'hBA8A)) \n \\gpf1.prog_full_i_i_1 \n (.I0(prog_full_i),\n .I1(\\grstd1.grst_full.grst_f.rst_d3_reg ),\n .I2(ram_full_fb_i_reg),\n .I3(prog_full),\n .O(\\gpf1.prog_full_i_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h2000000000000000)) \n \\gpf1.prog_full_i_i_2 \n (.I0(diff_pntr[7]),\n .I1(\\grstd1.grst_full.grst_f.rst_d3_reg ),\n .I2(diff_pntr[4]),\n .I3(diff_pntr[8]),\n .I4(diff_pntr[6]),\n .I5(diff_pntr[5]),\n .O(prog_full_i));\n FDPE #(\n .INIT(1'b1)) \n \\gpf1.prog_full_i_reg \n (.C(wr_clk),\n .CE(1'b1),\n .D(\\gpf1.prog_full_i_i_1_n_0 ),\n .PRE(out),\n .Q(prog_full));\n CARRY4 plusOp_carry\n (.CI(1'b0),\n .CO({plusOp_carry_n_0,plusOp_carry_n_1,plusOp_carry_n_2,plusOp_carry_n_3}),\n .CYINIT(E),\n .DI(Q[3:0]),\n .O(NLW_plusOp_carry_O_UNCONNECTED[3:0]),\n .S(S));\n CARRY4 plusOp_carry__0\n (.CI(plusOp_carry_n_0),\n .CO({plusOp_carry__0_n_0,plusOp_carry__0_n_1,plusOp_carry__0_n_2,plusOp_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI(Q[7:4]),\n .O(plusOp[8:5]),\n .S(\\gic0.gc0.count_d1_reg[7] ));\n CARRY4 plusOp_carry__1\n (.CI(plusOp_carry__0_n_0),\n .CO(NLW_plusOp_carry__1_CO_UNCONNECTED[3:0]),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({NLW_plusOp_carry__1_O_UNCONNECTED[3:1],plusOp[9]}),\n .S({1'b0,1'b0,1'b0,\\gic0.gc0.count_d1_reg[8] }));\nendmodule\n\n(* ORIG_REF_NAME = \"wr_status_flags_as\" *) \nmodule fb_output_fifo_wr_status_flags_as\n (full,\n out,\n E,\n v1_reg,\n \\gnxpm_cdc.rd_pntr_bin_reg[10] ,\n v1_reg_0,\n \\gnxpm_cdc.rd_pntr_bin_reg[10]_0 ,\n wr_clk,\n \\grstd1.grst_full.grst_f.rst_d2_reg ,\n wr_en,\n \\grstd1.grst_full.grst_f.rst_d3_reg );\n output full;\n output out;\n output [0:0]E;\n input [3:0]v1_reg;\n input \\gnxpm_cdc.rd_pntr_bin_reg[10] ;\n input [3:0]v1_reg_0;\n input \\gnxpm_cdc.rd_pntr_bin_reg[10]_0 ;\n input wr_clk;\n input \\grstd1.grst_full.grst_f.rst_d2_reg ;\n input wr_en;\n input \\grstd1.grst_full.grst_f.rst_d3_reg ;\n\n wire [0:0]E;\n wire c2_n_0;\n wire comp1;\n wire \\gnxpm_cdc.rd_pntr_bin_reg[10] ;\n wire \\gnxpm_cdc.rd_pntr_bin_reg[10]_0 ;\n wire \\grstd1.grst_full.grst_f.rst_d2_reg ;\n wire \\grstd1.grst_full.grst_f.rst_d3_reg ;\n (* DONT_TOUCH *) wire ram_full_fb_i;\n (* DONT_TOUCH *) wire ram_full_i;\n wire [3:0]v1_reg;\n wire [3:0]v1_reg_0;\n wire wr_clk;\n wire wr_en;\n\n assign full = ram_full_i;\n assign out = ram_full_fb_i;\n LUT2 #(\n .INIT(4'h2)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_2 \n (.I0(wr_en),\n .I1(ram_full_fb_i),\n .O(E));\n fb_output_fifo_compare__parameterized0 c1\n (.comp1(comp1),\n .\\gnxpm_cdc.rd_pntr_bin_reg[10] (\\gnxpm_cdc.rd_pntr_bin_reg[10] ),\n .v1_reg(v1_reg));\n fb_output_fifo_compare__parameterized1 c2\n (.comp1(comp1),\n .\\gnxpm_cdc.rd_pntr_bin_reg[10] (\\gnxpm_cdc.rd_pntr_bin_reg[10]_0 ),\n .\\grstd1.grst_full.grst_f.rst_d3_reg (\\grstd1.grst_full.grst_f.rst_d3_reg ),\n .out(ram_full_fb_i),\n .ram_full_fb_i_reg(c2_n_0),\n .v1_reg_0(v1_reg_0),\n .wr_en(wr_en));\n (* DONT_TOUCH *) \n (* KEEP = \"yes\" *) \n (* equivalent_register_removal = \"no\" *) \n FDPE #(\n .INIT(1'b1)) \n ram_full_fb_i_reg\n (.C(wr_clk),\n .CE(1'b1),\n .D(c2_n_0),\n .PRE(\\grstd1.grst_full.grst_f.rst_d2_reg ),\n .Q(ram_full_fb_i));\n (* DONT_TOUCH *) \n (* KEEP = \"yes\" *) \n (* equivalent_register_removal = \"no\" *) \n FDPE #(\n .INIT(1'b1)) \n ram_full_i_reg\n (.C(wr_clk),\n .CE(1'b1),\n .D(c2_n_0),\n .PRE(\\grstd1.grst_full.grst_f.rst_d2_reg ),\n .Q(ram_full_i));\nendmodule\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.sim/sim_1/synth/func/genesys2_fbtest_vlog.prj", "content": "# compile verilog/system verilog design source files\nverilog xil_defaultlib \"genesys2_fbtest_func_synth.v\" --include \"../../../../framebuffer_test.srcs/sources_1/ip/dvi_pll\" --include \"../../../../framebuffer_test.srcs/sources_1/ip/camera_pll\"\n\n# Do not sort compile order\nnosort\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/constrs_1/imports/constraints/ddr3_if.xdc", "content": "##################################################################################################\n##\n## Xilinx, Inc. 2010 www.xilinx.com\n## Sat Nov 12 10:25:17 2016\n## Generated by MIG Version 4.0\n##\n##################################################################################################\n## File name : ddr3_if.xdc\n## Details : Constraints file\n## FPGA Family: KINTEX7\n## FPGA Part: XC7K325T-FFG900\n## Speedgrade: -2\n## Design Entry: VERILOG\n## Frequency: 0 MHz\n## Time Period: 1112 ps\n##################################################################################################\n\n##################################################################################################\n## Controller 0\n## Memory Device: DDR3_SDRAM->Components->MT41J256m16XX-107\n## Data Width: 32\n## Time Period: 1112\n## Data Mask: 1\n##################################################################################################\n\n#create_clock -period 5.004 [get_ports sys_clk_i]\n\n############## NET - IOSTANDARD ##################\n\n\n# PadFunction: IO_L1N_T0_34\nset_property SLEW FAST [get_ports {ddr3_dq[0]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[0]}]\nset_property PACKAGE_PIN AD3 [get_ports {ddr3_dq[0]}]\n\n# PadFunction: IO_L2P_T0_34\nset_property SLEW FAST [get_ports {ddr3_dq[1]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[1]}]\nset_property PACKAGE_PIN AC2 [get_ports {ddr3_dq[1]}]\n\n# PadFunction: IO_L2N_T0_34\nset_property SLEW FAST [get_ports {ddr3_dq[2]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[2]}]\nset_property PACKAGE_PIN AC1 [get_ports {ddr3_dq[2]}]\n\n# PadFunction: IO_L4P_T0_34\nset_property SLEW FAST [get_ports {ddr3_dq[3]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[3]}]\nset_property PACKAGE_PIN AC5 [get_ports {ddr3_dq[3]}]\n\n# PadFunction: IO_L4N_T0_34\nset_property SLEW FAST [get_ports {ddr3_dq[4]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[4]}]\nset_property PACKAGE_PIN AC4 [get_ports {ddr3_dq[4]}]\n\n# PadFunction: IO_L5P_T0_34\nset_property SLEW FAST [get_ports {ddr3_dq[5]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[5]}]\nset_property PACKAGE_PIN AD6 [get_ports {ddr3_dq[5]}]\n\n# PadFunction: IO_L5N_T0_34\nset_property SLEW FAST [get_ports {ddr3_dq[6]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[6]}]\nset_property PACKAGE_PIN AE6 [get_ports {ddr3_dq[6]}]\n\n# PadFunction: IO_L6P_T0_34\nset_property SLEW FAST [get_ports {ddr3_dq[7]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[7]}]\nset_property PACKAGE_PIN AC7 [get_ports {ddr3_dq[7]}]\n\n# PadFunction: IO_L7N_T1_34\nset_property SLEW FAST [get_ports {ddr3_dq[8]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[8]}]\nset_property PACKAGE_PIN AF2 [get_ports {ddr3_dq[8]}]\n\n# PadFunction: IO_L8P_T1_34\nset_property SLEW FAST [get_ports {ddr3_dq[9]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[9]}]\nset_property PACKAGE_PIN AE1 [get_ports {ddr3_dq[9]}]\n\n# PadFunction: IO_L8N_T1_34\nset_property SLEW FAST [get_ports {ddr3_dq[10]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[10]}]\nset_property PACKAGE_PIN AF1 [get_ports {ddr3_dq[10]}]\n\n# PadFunction: IO_L10P_T1_34\nset_property SLEW FAST [get_ports {ddr3_dq[11]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[11]}]\nset_property PACKAGE_PIN AE4 [get_ports {ddr3_dq[11]}]\n\n# PadFunction: IO_L10N_T1_34\nset_property SLEW FAST [get_ports {ddr3_dq[12]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[12]}]\nset_property PACKAGE_PIN AE3 [get_ports {ddr3_dq[12]}]\n\n# PadFunction: IO_L11P_T1_SRCC_34\nset_property SLEW FAST [get_ports {ddr3_dq[13]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[13]}]\nset_property PACKAGE_PIN AE5 [get_ports {ddr3_dq[13]}]\n\n# PadFunction: IO_L11N_T1_SRCC_34\nset_property SLEW FAST [get_ports {ddr3_dq[14]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[14]}]\nset_property PACKAGE_PIN AF5 [get_ports {ddr3_dq[14]}]\n\n# PadFunction: IO_L12P_T1_MRCC_34\nset_property SLEW FAST [get_ports {ddr3_dq[15]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[15]}]\nset_property PACKAGE_PIN AF6 [get_ports {ddr3_dq[15]}]\n\n# PadFunction: IO_L13N_T2_MRCC_34\nset_property SLEW FAST [get_ports {ddr3_dq[16]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[16]}]\nset_property PACKAGE_PIN AJ4 [get_ports {ddr3_dq[16]}]\n\n# PadFunction: IO_L14P_T2_SRCC_34\nset_property SLEW FAST [get_ports {ddr3_dq[17]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[17]}]\nset_property PACKAGE_PIN AH6 [get_ports {ddr3_dq[17]}]\n\n# PadFunction: IO_L14N_T2_SRCC_34\nset_property SLEW FAST [get_ports {ddr3_dq[18]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[18]}]\nset_property PACKAGE_PIN AH5 [get_ports {ddr3_dq[18]}]\n\n# PadFunction: IO_L16P_T2_34\nset_property SLEW FAST [get_ports {ddr3_dq[19]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[19]}]\nset_property PACKAGE_PIN AH2 [get_ports {ddr3_dq[19]}]\n\n# PadFunction: IO_L16N_T2_34\nset_property SLEW FAST [get_ports {ddr3_dq[20]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[20]}]\nset_property PACKAGE_PIN AJ2 [get_ports {ddr3_dq[20]}]\n\n# PadFunction: IO_L17P_T2_34\nset_property SLEW FAST [get_ports {ddr3_dq[21]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[21]}]\nset_property PACKAGE_PIN AJ1 [get_ports {ddr3_dq[21]}]\n\n# PadFunction: IO_L17N_T2_34\nset_property SLEW FAST [get_ports {ddr3_dq[22]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[22]}]\nset_property PACKAGE_PIN AK1 [get_ports {ddr3_dq[22]}]\n\n# PadFunction: IO_L18P_T2_34\nset_property SLEW FAST [get_ports {ddr3_dq[23]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[23]}]\nset_property PACKAGE_PIN AJ3 [get_ports {ddr3_dq[23]}]\n\n# PadFunction: IO_L20P_T3_34\nset_property SLEW FAST [get_ports {ddr3_dq[24]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[24]}]\nset_property PACKAGE_PIN AF7 [get_ports {ddr3_dq[24]}]\n\n# PadFunction: IO_L20N_T3_34\nset_property SLEW FAST [get_ports {ddr3_dq[25]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[25]}]\nset_property PACKAGE_PIN AG7 [get_ports {ddr3_dq[25]}]\n\n# PadFunction: IO_L22P_T3_34\nset_property SLEW FAST [get_ports {ddr3_dq[26]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[26]}]\nset_property PACKAGE_PIN AJ6 [get_ports {ddr3_dq[26]}]\n\n# PadFunction: IO_L22N_T3_34\nset_property SLEW FAST [get_ports {ddr3_dq[27]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[27]}]\nset_property PACKAGE_PIN AK6 [get_ports {ddr3_dq[27]}]\n\n# PadFunction: IO_L23P_T3_34\nset_property SLEW FAST [get_ports {ddr3_dq[28]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[28]}]\nset_property PACKAGE_PIN AJ8 [get_ports {ddr3_dq[28]}]\n\n# PadFunction: IO_L23N_T3_34\nset_property SLEW FAST [get_ports {ddr3_dq[29]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[29]}]\nset_property PACKAGE_PIN AK8 [get_ports {ddr3_dq[29]}]\n\n# PadFunction: IO_L24P_T3_34\nset_property SLEW FAST [get_ports {ddr3_dq[30]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[30]}]\nset_property PACKAGE_PIN AK5 [get_ports {ddr3_dq[30]}]\n\n# PadFunction: IO_L24N_T3_34\nset_property SLEW FAST [get_ports {ddr3_dq[31]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[31]}]\nset_property PACKAGE_PIN AK4 [get_ports {ddr3_dq[31]}]\n\n# PadFunction: IO_L16N_T2_33\nset_property SLEW FAST [get_ports {ddr3_addr[14]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[14]}]\nset_property PACKAGE_PIN AH9 [get_ports {ddr3_addr[14]}]\n\n# PadFunction: IO_L1P_T0_33\nset_property SLEW FAST [get_ports {ddr3_addr[13]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[13]}]\nset_property PACKAGE_PIN AA12 [get_ports {ddr3_addr[13]}]\n\n# PadFunction: IO_L1N_T0_33\nset_property SLEW FAST [get_ports {ddr3_addr[12]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[12]}]\nset_property PACKAGE_PIN AB12 [get_ports {ddr3_addr[12]}]\n\n# PadFunction: IO_L2P_T0_33\nset_property SLEW FAST [get_ports {ddr3_addr[11]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[11]}]\nset_property PACKAGE_PIN AA8 [get_ports {ddr3_addr[11]}]\n\n# PadFunction: IO_L2N_T0_33\nset_property SLEW FAST [get_ports {ddr3_addr[10]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[10]}]\nset_property PACKAGE_PIN AB8 [get_ports {ddr3_addr[10]}]\n\n# PadFunction: IO_L4P_T0_33\nset_property SLEW FAST [get_ports {ddr3_addr[9]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[9]}]\nset_property PACKAGE_PIN Y11 [get_ports {ddr3_addr[9]}]\n\n# PadFunction: IO_L4N_T0_33\nset_property SLEW FAST [get_ports {ddr3_addr[8]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[8]}]\nset_property PACKAGE_PIN Y10 [get_ports {ddr3_addr[8]}]\n\n# PadFunction: IO_L5P_T0_33\nset_property SLEW FAST [get_ports {ddr3_addr[7]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[7]}]\nset_property PACKAGE_PIN AA11 [get_ports {ddr3_addr[7]}]\n\n# PadFunction: IO_L5N_T0_33\nset_property SLEW FAST [get_ports {ddr3_addr[6]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[6]}]\nset_property PACKAGE_PIN AA10 [get_ports {ddr3_addr[6]}]\n\n# PadFunction: IO_L6P_T0_33\nset_property SLEW FAST [get_ports {ddr3_addr[5]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[5]}]\nset_property PACKAGE_PIN AA13 [get_ports {ddr3_addr[5]}]\n\n# PadFunction: IO_L10P_T1_33\nset_property SLEW FAST [get_ports {ddr3_addr[4]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[4]}]\nset_property PACKAGE_PIN AD9 [get_ports {ddr3_addr[4]}]\n\n# PadFunction: IO_L7N_T1_33\nset_property SLEW FAST [get_ports {ddr3_addr[3]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[3]}]\nset_property PACKAGE_PIN AC10 [get_ports {ddr3_addr[3]}]\n\n# PadFunction: IO_L8P_T1_33\nset_property SLEW FAST [get_ports {ddr3_addr[2]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[2]}]\nset_property PACKAGE_PIN AD8 [get_ports {ddr3_addr[2]}]\n\n# PadFunction: IO_L8N_T1_33\nset_property SLEW FAST [get_ports {ddr3_addr[1]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[1]}]\nset_property PACKAGE_PIN AE8 [get_ports {ddr3_addr[1]}]\n\n# PadFunction: IO_L9P_T1_DQS_33\nset_property SLEW FAST [get_ports {ddr3_addr[0]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[0]}]\nset_property PACKAGE_PIN AC12 [get_ports {ddr3_addr[0]}]\n\n# PadFunction: IO_L9N_T1_DQS_33\nset_property SLEW FAST [get_ports {ddr3_ba[2]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[2]}]\nset_property PACKAGE_PIN AC11 [get_ports {ddr3_ba[2]}]\n\n# PadFunction: IO_L7P_T1_33\nset_property SLEW FAST [get_ports {ddr3_ba[1]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[1]}]\nset_property PACKAGE_PIN AB10 [get_ports {ddr3_ba[1]}]\n\n# PadFunction: IO_L10N_T1_33\nset_property SLEW FAST [get_ports {ddr3_ba[0]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[0]}]\nset_property PACKAGE_PIN AE9 [get_ports {ddr3_ba[0]}]\n\n# PadFunction: IO_L11P_T1_SRCC_33\nset_property SLEW FAST [get_ports ddr3_ras_n]\nset_property IOSTANDARD SSTL15 [get_ports ddr3_ras_n]\nset_property PACKAGE_PIN AE11 [get_ports ddr3_ras_n]\n\n# PadFunction: IO_L11N_T1_SRCC_33\nset_property SLEW FAST [get_ports ddr3_cas_n]\nset_property IOSTANDARD SSTL15 [get_ports ddr3_cas_n]\nset_property PACKAGE_PIN AF11 [get_ports ddr3_cas_n]\n\n# PadFunction: IO_L24P_T3_33\nset_property SLEW FAST [get_ports ddr3_we_n]\nset_property IOSTANDARD SSTL15 [get_ports ddr3_we_n]\nset_property PACKAGE_PIN AG13 [get_ports ddr3_we_n]\n\n# PadFunction: IO_L12N_T1_MRCC_34\nset_property SLEW FAST [get_ports ddr3_reset_n]\nset_property IOSTANDARD LVCMOS15 [get_ports ddr3_reset_n]\nset_property PACKAGE_PIN AG5 [get_ports ddr3_reset_n]\n\n# PadFunction: IO_L15P_T2_DQS_33\nset_property SLEW FAST [get_ports {ddr3_cke[0]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_cke[0]}]\nset_property PACKAGE_PIN AJ9 [get_ports {ddr3_cke[0]}]\n\n# PadFunction: IO_L15N_T2_DQS_33\nset_property SLEW FAST [get_ports {ddr3_odt[0]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_odt[0]}]\nset_property PACKAGE_PIN AK9 [get_ports {ddr3_odt[0]}]\n\n# PadFunction: IO_L24N_T3_33\nset_property SLEW FAST [get_ports {ddr3_cs_n[0]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_cs_n[0]}]\nset_property PACKAGE_PIN AH12 [get_ports {ddr3_cs_n[0]}]\n\n# PadFunction: IO_L1P_T0_34\nset_property SLEW FAST [get_ports {ddr3_dm[0]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[0]}]\nset_property PACKAGE_PIN AD4 [get_ports {ddr3_dm[0]}]\n\n# PadFunction: IO_L7P_T1_34\nset_property SLEW FAST [get_ports {ddr3_dm[1]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[1]}]\nset_property PACKAGE_PIN AF3 [get_ports {ddr3_dm[1]}]\n\n# PadFunction: IO_L13P_T2_MRCC_34\nset_property SLEW FAST [get_ports {ddr3_dm[2]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[2]}]\nset_property PACKAGE_PIN AH4 [get_ports {ddr3_dm[2]}]\n\n# PadFunction: IO_L19P_T3_34\nset_property SLEW FAST [get_ports {ddr3_dm[3]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[3]}]\nset_property PACKAGE_PIN AF8 [get_ports {ddr3_dm[3]}]\n\n# PadFunction: IO_L3P_T0_DQS_34\nset_property SLEW FAST [get_ports {ddr3_dqs_p[0]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[0]}]\n\n# PadFunction: IO_L3N_T0_DQS_34\nset_property SLEW FAST [get_ports {ddr3_dqs_n[0]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[0]}]\nset_property PACKAGE_PIN AD2 [get_ports {ddr3_dqs_p[0]}]\nset_property PACKAGE_PIN AD1 [get_ports {ddr3_dqs_n[0]}]\n\n# PadFunction: IO_L9P_T1_DQS_34\nset_property SLEW FAST [get_ports {ddr3_dqs_p[1]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[1]}]\n\n# PadFunction: IO_L9N_T1_DQS_34\nset_property SLEW FAST [get_ports {ddr3_dqs_n[1]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[1]}]\nset_property PACKAGE_PIN AG4 [get_ports {ddr3_dqs_p[1]}]\nset_property PACKAGE_PIN AG3 [get_ports {ddr3_dqs_n[1]}]\n\n# PadFunction: IO_L15P_T2_DQS_34\nset_property SLEW FAST [get_ports {ddr3_dqs_p[2]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[2]}]\n\n# PadFunction: IO_L15N_T2_DQS_34\nset_property SLEW FAST [get_ports {ddr3_dqs_n[2]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[2]}]\nset_property PACKAGE_PIN AG2 [get_ports {ddr3_dqs_p[2]}]\nset_property PACKAGE_PIN AH1 [get_ports {ddr3_dqs_n[2]}]\n\n# PadFunction: IO_L21P_T3_DQS_34\nset_property SLEW FAST [get_ports {ddr3_dqs_p[3]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[3]}]\n\n# PadFunction: IO_L21N_T3_DQS_34\nset_property SLEW FAST [get_ports {ddr3_dqs_n[3]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[3]}]\nset_property PACKAGE_PIN AH7 [get_ports {ddr3_dqs_p[3]}]\nset_property PACKAGE_PIN AJ7 [get_ports {ddr3_dqs_n[3]}]\n\n# PadFunction: IO_L3P_T0_DQS_33\nset_property SLEW FAST [get_ports {ddr3_ck_p[0]}]\nset_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_p[0]}]\n\n# PadFunction: IO_L3N_T0_DQS_33\nset_property SLEW FAST [get_ports {ddr3_ck_n[0]}]\nset_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_n[0]}]\nset_property PACKAGE_PIN AB9 [get_ports {ddr3_ck_p[0]}]\nset_property PACKAGE_PIN AC9 [get_ports {ddr3_ck_n[0]}]\n\n\n\nset_property LOC PHASER_OUT_PHY_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}]\nset_property LOC PHASER_OUT_PHY_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}]\nset_property LOC PHASER_OUT_PHY_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}]\nset_property LOC PHASER_OUT_PHY_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}]\nset_property LOC PHASER_OUT_PHY_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}]\nset_property LOC PHASER_OUT_PHY_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}]\nset_property LOC PHASER_OUT_PHY_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}]\nset_property LOC PHASER_OUT_PHY_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}]\n\n## set_property LOC PHASER_IN_PHY_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}]\n## set_property LOC PHASER_IN_PHY_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}]\n## set_property LOC PHASER_IN_PHY_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}]\n## set_property LOC PHASER_IN_PHY_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}]\nset_property LOC PHASER_IN_PHY_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}]\nset_property LOC PHASER_IN_PHY_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}]\nset_property LOC PHASER_IN_PHY_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}]\nset_property LOC PHASER_IN_PHY_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}]\n\n\n\nset_property LOC OUT_FIFO_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}]\nset_property LOC OUT_FIFO_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}]\nset_property LOC OUT_FIFO_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}]\nset_property LOC OUT_FIFO_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}]\nset_property LOC OUT_FIFO_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}]\nset_property LOC OUT_FIFO_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}]\nset_property LOC OUT_FIFO_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}]\nset_property LOC OUT_FIFO_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}]\n\nset_property LOC IN_FIFO_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo}]\nset_property LOC IN_FIFO_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo}]\nset_property LOC IN_FIFO_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo}]\nset_property LOC IN_FIFO_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo}]\n\nset_property LOC PHY_CONTROL_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/phy_control_i}]\nset_property LOC PHY_CONTROL_X1Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i}]\n\nset_property LOC PHASER_REF_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/phaser_ref_i}]\nset_property LOC PHASER_REF_X1Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i}]\n\nset_property LOC OLOGIC_X1Y143 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts}]\nset_property LOC OLOGIC_X1Y131 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts}]\nset_property LOC OLOGIC_X1Y119 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts}]\nset_property LOC OLOGIC_X1Y107 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts}]\n\nset_property LOC PLLE2_ADV_X1Y1 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/plle2_i}]\nset_property LOC MMCME2_ADV_X1Y1 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/gen_mmcm.mmcm_i}]\n\n\nset_multicycle_path -setup -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] 6\n\nset_multicycle_path -hold -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] 5\n\nset_false_path -through [get_pins -filter {NAME =~ */DQSFOUND} -of [get_cells -hier -filter {REF_NAME == PHASER_IN_PHY}]]\n\nset_multicycle_path -setup -start -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] 2\nset_multicycle_path -hold -start -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] 1\n\nset_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1*}] 20.000\nset_max_delay -datapath_only -from [get_cells -hier *rstdiv0_sync_r1_reg*] -to [get_pins -filter {NAME =~ */RESET} -of [get_cells -hier -filter {REF_NAME == PHY_CONTROL}]] 5.000\nset_false_path -through [get_pins -hier -filter {NAME =~ */u_iodelay_ctrl/sys_rst}]\n\nset_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *ddr3_infrastructure/rstdiv0_sync_r1_reg*}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1*}] 20.000\n\n\n\n\n\n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/constrs_1/imports/new/genesys2.xdc", "content": "set_property PACKAGE_PIN AA20 [get_ports {hdmi_clk[1]}]\nset_property IOSTANDARD TMDS_33 [get_ports {hdmi_clk[1]}]\nset_property IOSTANDARD TMDS_33 [get_ports {hdmi_clk[0]}]\nset_property PACKAGE_PIN AC20 [get_ports {hdmi_d0[1]}]\nset_property IOSTANDARD TMDS_33 [get_ports {hdmi_d0[1]}]\nset_property IOSTANDARD TMDS_33 [get_ports {hdmi_d0[0]}]\nset_property PACKAGE_PIN AA22 [get_ports {hdmi_d1[1]}]\nset_property IOSTANDARD TMDS_33 [get_ports {hdmi_d1[1]}]\nset_property IOSTANDARD TMDS_33 [get_ports {hdmi_d1[0]}]\nset_property PACKAGE_PIN AB24 [get_ports {hdmi_d2[1]}]\nset_property IOSTANDARD TMDS_33 [get_ports {hdmi_d2[0]}]\nset_property IOSTANDARD TMDS_33 [get_ports {hdmi_d2[1]}]\nset_property PACKAGE_PIN R19 [get_ports reset_n]\nset_property IOSTANDARD LVCMOS33 [get_ports reset_n]\nset_property PACKAGE_PIN AD12 [get_ports clock_p]\nset_property IOSTANDARD DIFF_SSTL15 [get_ports clock_p]\n\n\ncreate_clock -period 5.000 -waveform {0.000 2.500} [get_ports clock_p]\ncreate_clock -period 5.000 -waveform {2.500 5.000} [get_ports clock_n]\n\n\n\n\n\nset_property PACKAGE_PIN P27 [get_ports zoom_mode]\nset_property IOSTANDARD LVCMOS33 [get_ports zoom_mode]\n\nset_property PACKAGE_PIN P26 [get_ports freeze]\nset_property IOSTANDARD LVCMOS33 [get_ports freeze]\n\nset_property PACKAGE_PIN D26 [get_ports {csi0_clk[1]}]\nset_property IOSTANDARD LVDS_25 [get_ports {csi0_clk[1]}]\nset_property IOSTANDARD LVDS_25 [get_ports {csi0_clk[0]}]\nset_property PACKAGE_PIN B30 [get_ports {csi0_d1[1]}]\nset_property IOSTANDARD LVDS_25 [get_ports {csi0_d1[1]}]\nset_property IOSTANDARD LVDS_25 [get_ports {csi0_d1[0]}]\nset_property PACKAGE_PIN B28 [get_ports {csi0_d3[1]}]\nset_property IOSTANDARD LVDS_25 [get_ports {csi0_d3[1]}]\nset_property IOSTANDARD LVDS_25 [get_ports {csi0_d3[0]}]\nset_property PACKAGE_PIN D29 [get_ports {csi0_d0[1]}]\nset_property IOSTANDARD LVDS_25 [get_ports {csi0_d0[1]}]\nset_property IOSTANDARD LVDS_25 [get_ports {csi0_d0[0]}]\nset_property PACKAGE_PIN B27 [get_ports {csi0_d2[1]}]\nset_property IOSTANDARD LVDS_25 [get_ports {csi0_d2[1]}]\nset_property IOSTANDARD LVDS_25 [get_ports {csi0_d2[0]}]\nset_property PACKAGE_PIN M28 [get_ports cam_mclk]\nset_property IOSTANDARD LVCMOS25 [get_ports cam_mclk]\nset_property PACKAGE_PIN L28 [get_ports cam_i2c_sck]\nset_property IOSTANDARD LVCMOS25 [get_ports cam_i2c_sck]\nset_property PACKAGE_PIN J29 [get_ports cam_i2c_sda]\nset_property IOSTANDARD LVCMOS25 [get_ports cam_i2c_sda]\nset_property PACKAGE_PIN N21 [get_ports cam_rstn]\nset_property IOSTANDARD LVCMOS25 [get_ports cam_rstn]\n\n\n\ncreate_clock -period 2.500 -name csi -waveform {0.000 1.250} [get_ports {csi0_clk[1]}]\ncreate_clock -period 2.500 -name csi2 -waveform {1.250 2.500} [get_ports {csi0_clk[0]}]\nset_input_delay -clock [get_clocks csi] 1.000 [get_ports {{csi0_d0[0]} {csi0_d0[1]} {csi0_d1[0]} {csi0_d1[1]} {csi0_d2[0]} {csi0_d2[1]} {csi0_d3[0]} {csi0_d3[1]}}]\nset_input_delay -clock [get_clocks csi] -clock_fall 1.000 [get_ports {{csi0_d0[0]} {csi0_d0[1]} {csi0_d1[0]} {csi0_d1[1]} {csi0_d2[0]} {csi0_d2[1]} {csi0_d3[0]} {csi0_d3[1]}}]\n\nset_output_delay -clock [get_clocks [get_clocks -filter {IS_GENERATED && MASTER_CLOCK == clock_p} -of_objects [get_pins pll1/inst/plle2_adv_inst/CLKOUT1]]] 0.000 [get_ports {{hdmi_clk[0]} {hdmi_clk[1]} {hdmi_d0[0]} {hdmi_d0[1]} {hdmi_d1[0]} {hdmi_d1[1]} {hdmi_d2[0]} {hdmi_d2[1]}}]\nset_output_delay -clock [get_clocks [get_clocks -filter {IS_GENERATED && MASTER_CLOCK == clock_p} -of_objects [get_pins pll1/inst/plle2_adv_inst/CLKOUT1]]] -clock_fall 0.000 [get_ports {{hdmi_clk[0]} {hdmi_clk[1]} {hdmi_d0[0]} {hdmi_d0[1]} {hdmi_d1[0]} {hdmi_d1[1]} {hdmi_d2[0]} {hdmi_d2[1]}}]\n\nset_property PACKAGE_PIN AH20 [get_ports {vga_b[0]}]\nset_property PACKAGE_PIN AG20 [get_ports {vga_b[1]}]\nset_property PACKAGE_PIN AF21 [get_ports {vga_b[2]}]\nset_property PACKAGE_PIN AK20 [get_ports {vga_b[3]}]\nset_property PACKAGE_PIN AG22 [get_ports {vga_b[4]}]\nset_property PACKAGE_PIN AJ23 [get_ports {vga_g[0]}]\nset_property PACKAGE_PIN AJ22 [get_ports {vga_g[1]}]\nset_property PACKAGE_PIN AH22 [get_ports {vga_g[2]}]\nset_property PACKAGE_PIN AK21 [get_ports {vga_g[3]}]\nset_property PACKAGE_PIN AJ21 [get_ports {vga_g[4]}]\nset_property PACKAGE_PIN AK23 [get_ports {vga_g[5]}]\nset_property PACKAGE_PIN AF20 [get_ports vga_hsync]\nset_property PACKAGE_PIN AK25 [get_ports {vga_r[0]}]\nset_property PACKAGE_PIN AG25 [get_ports {vga_r[1]}]\nset_property PACKAGE_PIN AH25 [get_ports {vga_r[2]}]\nset_property PACKAGE_PIN AK24 [get_ports {vga_r[3]}]\nset_property PACKAGE_PIN AJ24 [get_ports {vga_r[4]}]\nset_property PACKAGE_PIN AG23 [get_ports vga_vsync]\nset_property IOSTANDARD LVCMOS33 [get_ports {vga_b[0]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {vga_b[1]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {vga_b[2]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {vga_b[3]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {vga_b[4]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {vga_g[0]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {vga_g[1]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {vga_g[2]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {vga_g[4]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {vga_g[3]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {vga_g[5]}]\nset_property IOSTANDARD LVCMOS33 [get_ports vga_hsync]\nset_property IOSTANDARD LVCMOS33 [get_ports {vga_r[0]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {vga_r[1]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {vga_r[3]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {vga_r[2]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {vga_r[4]}]\nset_property IOSTANDARD LVCMOS33 [get_ports vga_vsync]\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll.v", "content": "\n// file: camera_pll.v\n// \n// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n//----------------------------------------------------------------------------\n// User entered comments\n//----------------------------------------------------------------------------\n// None\n//\n//----------------------------------------------------------------------------\n// Output Output Phase Duty Cycle Pk-to-Pk Phase\n// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)\n//----------------------------------------------------------------------------\n// camera_pixel_clock___145.000______0.000______50.0______280.569____321.802\n// camera_mclk____24.399______0.000______50.0______391.507____321.802\n// i2c_clkin_____4.995______0.000______50.0______519.540____321.802\n//\n//----------------------------------------------------------------------------\n// Input Clock Freq (MHz) Input Jitter (UI)\n//----------------------------------------------------------------------------\n// __primary_____________200____________0.010\n\n`timescale 1ps/1ps\n\n(* CORE_GENERATION_INFO = \"camera_pll,clk_wiz_v5_3_2_0,{component_name=camera_pll,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=3,clkin1_period=5.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}\" *)\n\nmodule camera_pll \n (\n // Clock out ports\n output camera_pixel_clock,\n output camera_mclk,\n output i2c_clkin,\n // Clock in ports\n input sysclk\n );\n\n camera_pll_clk_wiz inst\n (\n // Clock out ports \n .camera_pixel_clock(camera_pixel_clock),\n .camera_mclk(camera_mclk),\n .i2c_clkin(i2c_clkin),\n // Clock in ports\n .sysclk(sysclk)\n );\n\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll.xci", "content": "\n\n xilinx.com\n xci\n unknown\n 1.0\n \n \n camera_pll\n \n \n MMCM\n cddcdone\n cddcreq\n 0000\n 3800\n clkfb_in_n\n clkfb_in\n clkfb_in_p\n SINGLE\n clkfb_out_n\n clkfb_out\n clkfb_out_p\n clkfb_stopped\n 50.0\n 100.0\n 1041\n 3c00\n 145.000\n 134d\n 0000\n 24.399\n BUFG\n 50.0\n false\n 145.000\n 0.000\n 50.000\n 145\n 0.000\n 1\n 1fc0\n 0080\n 4.995\n BUFG\n 50.0\n false\n 24.399\n 0.000\n 50.000\n 24.4\n 0.000\n 1\n 1\n 1041\n 00c0\n 100.000\n BUFG\n 50.0\n false\n 4.995\n 0.000\n 50.000\n 5\n 0.000\n 1\n 1\n 1041\n 00c0\n 100.000\n BUFG\n 50.000\n false\n 100.000\n 0.000\n 50.000\n 100.000\n 0.000\n 1\n 0\n 1041\n 0cc0\n 100.000\n BUFG\n 50.000\n false\n 100.000\n 0.000\n 50.000\n 100.000\n 0.000\n 1\n 0\n 1041\n 28c0\n 100.000\n BUFG\n 50.000\n false\n 100.000\n 0.000\n 50.000\n 100.000\n 0.000\n 1\n 0\n BUFG\n 50.000\n false\n 100.000\n 0.000\n 50.000\n 100.000\n 0.000\n 1\n 0\n VCO\n clk_in_sel\n camera_pixel_clock\n camera_mclk\n i2c_clkin\n clk_out4\n clk_out5\n clk_out6\n clk_out7\n CLK_VALID\n NA\n daddr\n dclk\n den\n din\n 0104\n 1\n 5.942622950819673\n 29.0\n 1.45\n 1.45\n 1.45\n 1.45\n dout\n drdy\n dwe\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n FDBK_AUTO\n 0800\n 0190\n 0\n Input Clock Freq (MHz) Input Jitter (UI)\n __primary_____________200____________0.010\n no_secondary_input_clock \n input_clk_stopped\n 0\n Units_MHz\n No_Jitter\n locked\n 0190\n 7c01\n 7fe9\n false\n false\n false\n false\n false\n false\n false\n false\n OPTIMIZED\n 25.375\n 0.000\n FALSE\n 5.0\n 10.0\n 4.375\n 0.500\n 0.000\n FALSE\n 26\n 0.500\n 0.000\n FALSE\n 127\n 0.500\n 0.000\n FALSE\n 1\n 0.500\n 0.000\n FALSE\n FALSE\n 1\n 0.500\n 0.000\n FALSE\n 1\n 0.500\n 0.000\n FALSE\n 1\n 0.500\n 0.000\n FALSE\n FALSE\n ZHOLD\n 8\n None\n 0.010\n 0.010\n FALSE\n 3\n Output Output Phase Duty Cycle Pk-to-Pk Phase\n Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)\n camera_pixel_clock___145.000______0.000______50.0______280.569____321.802\n camera_mclk____24.399______0.000______50.0______391.507____321.802\n i2c_clkin_____4.995______0.000______50.0______519.540____321.802\n no_CLK_OUT4_output\n no_CLK_OUT5_output\n no_CLK_OUT6_output\n no_CLK_OUT7_output\n 0\n 0\n WAVEFORM\n UNKNOWN\n false\n false\n false\n false\n false\n OPTIMIZED\n 1\n 0.000\n 1.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n CLKFBOUT\n SYSTEM_SYNCHRONOUS\n 1\n No notes\n 0.010\n power_down\n FFFF\n 1\n sysclk\n MMCM\n AUTO\n 200\n 0.010\n 10.000\n Global_buffer\n psclk\n psdone\n psen\n psincdec\n 100.0\n 0\n reset\n 100.000\n 0.010\n 10.000\n clk_in2\n Single_ended_clock_capable_pin\n CENTER_HIGH\n 4000\n 0.004\n STATUS\n 11\n 32\n 100.0\n 100.0\n 100.0\n 100.0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n camera_pll\n MMCM\n false\n empty\n cddcdone\n cddcreq\n clkfb_in_n\n clkfb_in\n clkfb_in_p\n SINGLE\n clkfb_out_n\n clkfb_out\n clkfb_out_p\n clkfb_stopped\n 50.0\n 0.010\n 100.0\n 0.010\n BUFG\n 280.569\n false\n 321.802\n 50.000\n 145\n 0.000\n 1\n true\n BUFG\n 391.507\n false\n 321.802\n 50.000\n 24.4\n 0.000\n 1\n true\n BUFG\n 519.540\n false\n 321.802\n 50.000\n 5\n 0.000\n 1\n true\n BUFG\n 0.0\n false\n 0.0\n 50.000\n 100.000\n 0.000\n 1\n false\n BUFG\n 0.0\n false\n 0.0\n 50.000\n 100.000\n 0.000\n 1\n false\n BUFG\n 0.0\n false\n 0.0\n 50.000\n 100.000\n 0.000\n 1\n false\n BUFG\n 0.0\n false\n 0.0\n 50.000\n 100.000\n 0.000\n 1\n false\n 600.000\n Custom\n Custom\n clk_in_sel\n camera_pixel_clock\n false\n camera_mclk\n false\n i2c_clkin\n false\n clk_out4\n false\n clk_out5\n false\n clk_out6\n false\n clk_out7\n false\n CLK_VALID\n auto\n camera_pll\n daddr\n dclk\n den\n Custom\n Custom\n din\n dout\n drdy\n dwe\n false\n false\n false\n false\n false\n false\n false\n false\n false\n FDBK_AUTO\n input_clk_stopped\n frequency\n Enable_AXI\n Units_MHz\n Units_UI\n UI\n No_Jitter\n locked\n OPTIMIZED\n 25.375\n 0.000\n false\n 5.0\n 10.0\n 4.375\n 0.500\n 0.000\n false\n 26\n 0.500\n 0.000\n false\n 127\n 0.500\n 0.000\n false\n 1\n 0.500\n 0.000\n false\n false\n 1\n 0.500\n 0.000\n false\n 1\n 0.500\n 0.000\n false\n 1\n 0.500\n 0.000\n false\n false\n ZHOLD\n 8\n None\n 0.010\n 0.010\n false\n 3\n false\n false\n WAVEFORM\n false\n UNKNOWN\n OPTIMIZED\n 4\n 0.000\n 10.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n CLKFBOUT\n SYSTEM_SYNCHRONOUS\n 1\n None\n 0.010\n power_down\n 1\n sysclk\n MMCM\n mmcm_adv\n 200\n 0.010\n 10.000\n Global_buffer\n psclk\n psdone\n psen\n psincdec\n 100.0\n REL_PRIMARY\n Custom\n reset\n ACTIVE_HIGH\n 100.000\n 0.010\n 10.000\n clk_in2\n Single_ended_clock_capable_pin\n CENTER_HIGH\n 250\n 0.004\n STATUS\n empty\n 100.0\n 100.0\n 100.0\n 100.0\n false\n false\n false\n false\n false\n false\n false\n true\n false\n false\n false\n false\n false\n false\n true\n false\n false\n false\n false\n false\n kintex7\n \n xc7k325t\n ffg900\n VERILOG\n \n MIXED\n -2\n \n TRUE\n TRUE\n IP_Flow\n 2\n TRUE\n .\n \n .\n 2016.3\n OUT_OF_CONTEXT\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll.xdc", "content": "\n# file: camera_pll.xdc\n# \n# (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n# \n# This file contains confidential and proprietary information\n# of Xilinx, Inc. and is protected under U.S. and\n# international copyright and other intellectual property\n# laws.\n# \n# DISCLAIMER\n# This disclaimer is not a license and does not grant any\n# rights to the materials distributed herewith. Except as\n# otherwise provided in a valid license issued to you by\n# Xilinx, and to the maximum extent permitted by applicable\n# law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n# (2) Xilinx shall not be liable (whether in contract or tort,\n# including negligence, or under any other theory of\n# liability) for any loss or damage of any kind or nature\n# related to, arising under or in connection with these\n# materials, including for any direct, or any indirect,\n# special, incidental, or consequential loss or damage\n# (including loss of data, profits, goodwill, or any type of\n# loss or damage suffered as a result of any action brought\n# by a third party) even if such damage or loss was\n# reasonably foreseeable or Xilinx had been advised of the\n# possibility of the same.\n# \n# CRITICAL APPLICATIONS\n# Xilinx products are not designed or intended to be fail-\n# safe, or for use in any application requiring fail-safe\n# performance, such as life-support or safety devices or\n# systems, Class III medical devices, nuclear facilities,\n# applications related to the deployment of airbags, or any\n# other applications that could lead to death, personal\n# injury, or severe property or environmental damage\n# (individually and collectively, \"Critical\n# Applications\"). Customer assumes the sole risk and\n# liability of any use of Xilinx products in Critical\n# Applications, subject only to applicable laws and\n# regulations governing limitations on product liability.\n# \n# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n# PART OF THIS FILE AT ALL TIMES.\n# \n\n# Input clock periods. These duplicate the values entered for the\n# input clocks. You can use these to time your system. If required\n# commented constraints can be used in the top level xdc \n#----------------------------------------------------------------\n#create_clock -period 5.0 [get_ports sysclk]\n#set_input_jitter [get_clocks -of_objects [get_ports sysclk]] 0.05\n\n\nset_property PHASESHIFT_MODE WAVEFORM [get_cells -hierarchical *adv*]\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_board.xdc", "content": "#--------------------Physical Constraints-----------------\n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_clk_wiz.v", "content": "\n// file: camera_pll.v\n// \n// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n//----------------------------------------------------------------------------\n// User entered comments\n//----------------------------------------------------------------------------\n// None\n//\n//----------------------------------------------------------------------------\n// Output Output Phase Duty Cycle Pk-to-Pk Phase\n// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)\n//----------------------------------------------------------------------------\n// camera_pixel_clock___145.000______0.000______50.0______280.569____321.802\n// camera_mclk____24.399______0.000______50.0______391.507____321.802\n// i2c_clkin_____4.995______0.000______50.0______519.540____321.802\n//\n//----------------------------------------------------------------------------\n// Input Clock Freq (MHz) Input Jitter (UI)\n//----------------------------------------------------------------------------\n// __primary_____________200____________0.010\n\n`timescale 1ps/1ps\n\nmodule camera_pll_clk_wiz \n\n (// Clock in ports\n // Clock out ports\n output camera_pixel_clock,\n output camera_mclk,\n output i2c_clkin,\n input sysclk\n );\n // Input buffering\n //------------------------------------\nwire sysclk_camera_pll;\nwire clk_in2_camera_pll;\n BUFG clkin1_bufg\n (.O (sysclk_camera_pll),\n .I (sysclk));\n\n\n // Clocking PRIMITIVE\n //------------------------------------\n\n // Instantiation of the MMCM PRIMITIVE\n // * Unused inputs are tied off\n // * Unused outputs are labeled unused\n\n wire camera_pixel_clock_camera_pll;\n wire camera_mclk_camera_pll;\n wire i2c_clkin_camera_pll;\n wire clk_out4_camera_pll;\n wire clk_out5_camera_pll;\n wire clk_out6_camera_pll;\n wire clk_out7_camera_pll;\n\n wire [15:0] do_unused;\n wire drdy_unused;\n wire psdone_unused;\n wire locked_int;\n wire clkfbout_camera_pll;\n wire clkfbout_buf_camera_pll;\n wire clkfboutb_unused;\n wire clkout0b_unused;\n wire clkout1b_unused;\n wire clkout2b_unused;\n wire clkout3_unused;\n wire clkout3b_unused;\n wire clkout4_unused;\n wire clkout5_unused;\n wire clkout6_unused;\n wire clkfbstopped_unused;\n wire clkinstopped_unused;\n\n MMCME2_ADV\n #(.BANDWIDTH (\"OPTIMIZED\"),\n .CLKOUT4_CASCADE (\"FALSE\"),\n .COMPENSATION (\"ZHOLD\"),\n .STARTUP_WAIT (\"FALSE\"),\n .DIVCLK_DIVIDE (8),\n .CLKFBOUT_MULT_F (25.375),\n .CLKFBOUT_PHASE (0.000),\n .CLKFBOUT_USE_FINE_PS (\"FALSE\"),\n .CLKOUT0_DIVIDE_F (4.375),\n .CLKOUT0_PHASE (0.000),\n .CLKOUT0_DUTY_CYCLE (0.500),\n .CLKOUT0_USE_FINE_PS (\"FALSE\"),\n .CLKOUT1_DIVIDE (26),\n .CLKOUT1_PHASE (0.000),\n .CLKOUT1_DUTY_CYCLE (0.500),\n .CLKOUT1_USE_FINE_PS (\"FALSE\"),\n .CLKOUT2_DIVIDE (127),\n .CLKOUT2_PHASE (0.000),\n .CLKOUT2_DUTY_CYCLE (0.500),\n .CLKOUT2_USE_FINE_PS (\"FALSE\"),\n .CLKIN1_PERIOD (5.0))\n mmcm_adv_inst\n // Output clocks\n (\n .CLKFBOUT (clkfbout_camera_pll),\n .CLKFBOUTB (clkfboutb_unused),\n .CLKOUT0 (camera_pixel_clock_camera_pll),\n .CLKOUT0B (clkout0b_unused),\n .CLKOUT1 (camera_mclk_camera_pll),\n .CLKOUT1B (clkout1b_unused),\n .CLKOUT2 (i2c_clkin_camera_pll),\n .CLKOUT2B (clkout2b_unused),\n .CLKOUT3 (clkout3_unused),\n .CLKOUT3B (clkout3b_unused),\n .CLKOUT4 (clkout4_unused),\n .CLKOUT5 (clkout5_unused),\n .CLKOUT6 (clkout6_unused),\n // Input clock control\n .CLKFBIN (clkfbout_buf_camera_pll),\n .CLKIN1 (sysclk_camera_pll),\n .CLKIN2 (1'b0),\n // Tied to always select the primary input clock\n .CLKINSEL (1'b1),\n // Ports for dynamic reconfiguration\n .DADDR (7'h0),\n .DCLK (1'b0),\n .DEN (1'b0),\n .DI (16'h0),\n .DO (do_unused),\n .DRDY (drdy_unused),\n .DWE (1'b0),\n // Ports for dynamic phase shift\n .PSCLK (1'b0),\n .PSEN (1'b0),\n .PSINCDEC (1'b0),\n .PSDONE (psdone_unused),\n // Other control and status signals\n .LOCKED (locked_int),\n .CLKINSTOPPED (clkinstopped_unused),\n .CLKFBSTOPPED (clkfbstopped_unused),\n .PWRDWN (1'b0),\n .RST (1'b0));\n\n// Clock Monitor clock assigning\n//--------------------------------------\n // Output buffering\n //-----------------------------------\n\n BUFG clkf_buf\n (.O (clkfbout_buf_camera_pll),\n .I (clkfbout_camera_pll));\n\n\n\n BUFG clkout1_buf\n (.O (camera_pixel_clock),\n .I (camera_pixel_clock_camera_pll));\n\n\n BUFG clkout2_buf\n (.O (camera_mclk),\n .I (camera_mclk_camera_pll));\n\n BUFG clkout3_buf\n (.O (i2c_clkin),\n .I (i2c_clkin_camera_pll));\n\n\n\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_ooc.xdc", "content": "\n# file: camera_pll_ooc.xdc\n# \n# (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n# \n# This file contains confidential and proprietary information\n# of Xilinx, Inc. and is protected under U.S. and\n# international copyright and other intellectual property\n# laws.\n# \n# DISCLAIMER\n# This disclaimer is not a license and does not grant any\n# rights to the materials distributed herewith. Except as\n# otherwise provided in a valid license issued to you by\n# Xilinx, and to the maximum extent permitted by applicable\n# law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n# (2) Xilinx shall not be liable (whether in contract or tort,\n# including negligence, or under any other theory of\n# liability) for any loss or damage of any kind or nature\n# related to, arising under or in connection with these\n# materials, including for any direct, or any indirect,\n# special, incidental, or consequential loss or damage\n# (including loss of data, profits, goodwill, or any type of\n# loss or damage suffered as a result of any action brought\n# by a third party) even if such damage or loss was\n# reasonably foreseeable or Xilinx had been advised of the\n# possibility of the same.\n# \n# CRITICAL APPLICATIONS\n# Xilinx products are not designed or intended to be fail-\n# safe, or for use in any application requiring fail-safe\n# performance, such as life-support or safety devices or\n# systems, Class III medical devices, nuclear facilities,\n# applications related to the deployment of airbags, or any\n# other applications that could lead to death, personal\n# injury, or severe property or environmental damage\n# (individually and collectively, \"Critical\n# Applications\"). Customer assumes the sole risk and\n# liability of any use of Xilinx products in Critical\n# Applications, subject only to applicable laws and\n# regulations governing limitations on product liability.\n# \n# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n# PART OF THIS FILE AT ALL TIMES.\n# \n\n#################\n#DEFAULT CLOCK CONSTRAINTS\n\n############################################################\n# Clock Period Constraints #\n############################################################\ncreate_clock -period 5.0 [get_ports sysclk]\n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_sim_netlist.v", "content": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// --------------------------------------------------------------------------------\n// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016\n// Date : Tue Nov 15 14:32:35 2016\n// Host : david-desktop-arch running 64-bit unknown\n// Command : write_verilog -force -mode funcsim -rename_top camera_pll -prefix\n// camera_pll_ camera_pll_sim_netlist.v\n// Design : camera_pll\n// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified\n// or synthesized. This netlist cannot be used for SDF annotated simulation.\n// Device : xc7k325tffg900-2\n// --------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* NotValidForBitStream *)\nmodule camera_pll\n (camera_pixel_clock,\n camera_mclk,\n i2c_clkin,\n sysclk);\n output camera_pixel_clock;\n output camera_mclk;\n output i2c_clkin;\n input sysclk;\n\n wire camera_mclk;\n wire camera_pixel_clock;\n wire i2c_clkin;\n wire sysclk;\n\n camera_pll_camera_pll_clk_wiz inst\n (.camera_mclk(camera_mclk),\n .camera_pixel_clock(camera_pixel_clock),\n .i2c_clkin(i2c_clkin),\n .sysclk(sysclk));\nendmodule\n\nmodule camera_pll_camera_pll_clk_wiz\n (camera_pixel_clock,\n camera_mclk,\n i2c_clkin,\n sysclk);\n output camera_pixel_clock;\n output camera_mclk;\n output i2c_clkin;\n input sysclk;\n\n wire camera_mclk;\n wire camera_mclk_camera_pll;\n wire camera_pixel_clock;\n wire camera_pixel_clock_camera_pll;\n wire clkfbout_buf_camera_pll;\n wire clkfbout_camera_pll;\n wire i2c_clkin;\n wire i2c_clkin_camera_pll;\n wire sysclk;\n wire sysclk_camera_pll;\n wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;\n wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;\n wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;\n wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;\n wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;\n wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;\n wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;\n wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;\n wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;\n wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;\n wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;\n wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;\n wire NLW_mmcm_adv_inst_LOCKED_UNCONNECTED;\n wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;\n wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;\n\n (* BOX_TYPE = \"PRIMITIVE\" *) \n BUFG clkf_buf\n (.I(clkfbout_camera_pll),\n .O(clkfbout_buf_camera_pll));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n BUFG clkin1_bufg\n (.I(sysclk),\n .O(sysclk_camera_pll));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n BUFG clkout1_buf\n (.I(camera_pixel_clock_camera_pll),\n .O(camera_pixel_clock));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n BUFG clkout2_buf\n (.I(camera_mclk_camera_pll),\n .O(camera_mclk));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n BUFG clkout3_buf\n (.I(i2c_clkin_camera_pll),\n .O(i2c_clkin));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n MMCME2_ADV #(\n .BANDWIDTH(\"OPTIMIZED\"),\n .CLKFBOUT_MULT_F(25.375000),\n .CLKFBOUT_PHASE(0.000000),\n .CLKFBOUT_USE_FINE_PS(\"FALSE\"),\n .CLKIN1_PERIOD(5.000000),\n .CLKIN2_PERIOD(0.000000),\n .CLKOUT0_DIVIDE_F(4.375000),\n .CLKOUT0_DUTY_CYCLE(0.500000),\n .CLKOUT0_PHASE(0.000000),\n .CLKOUT0_USE_FINE_PS(\"FALSE\"),\n .CLKOUT1_DIVIDE(26),\n .CLKOUT1_DUTY_CYCLE(0.500000),\n .CLKOUT1_PHASE(0.000000),\n .CLKOUT1_USE_FINE_PS(\"FALSE\"),\n .CLKOUT2_DIVIDE(127),\n .CLKOUT2_DUTY_CYCLE(0.500000),\n .CLKOUT2_PHASE(0.000000),\n .CLKOUT2_USE_FINE_PS(\"FALSE\"),\n .CLKOUT3_DIVIDE(1),\n .CLKOUT3_DUTY_CYCLE(0.500000),\n .CLKOUT3_PHASE(0.000000),\n .CLKOUT3_USE_FINE_PS(\"FALSE\"),\n .CLKOUT4_CASCADE(\"FALSE\"),\n .CLKOUT4_DIVIDE(1),\n .CLKOUT4_DUTY_CYCLE(0.500000),\n .CLKOUT4_PHASE(0.000000),\n .CLKOUT4_USE_FINE_PS(\"FALSE\"),\n .CLKOUT5_DIVIDE(1),\n .CLKOUT5_DUTY_CYCLE(0.500000),\n .CLKOUT5_PHASE(0.000000),\n .CLKOUT5_USE_FINE_PS(\"FALSE\"),\n .CLKOUT6_DIVIDE(1),\n .CLKOUT6_DUTY_CYCLE(0.500000),\n .CLKOUT6_PHASE(0.000000),\n .CLKOUT6_USE_FINE_PS(\"FALSE\"),\n .COMPENSATION(\"BUF_IN\"),\n .DIVCLK_DIVIDE(8),\n .IS_CLKINSEL_INVERTED(1'b0),\n .IS_PSEN_INVERTED(1'b0),\n .IS_PSINCDEC_INVERTED(1'b0),\n .IS_PWRDWN_INVERTED(1'b0),\n .IS_RST_INVERTED(1'b0),\n .REF_JITTER1(0.010000),\n .REF_JITTER2(0.010000),\n .SS_EN(\"FALSE\"),\n .SS_MODE(\"CENTER_HIGH\"),\n .SS_MOD_PERIOD(10000),\n .STARTUP_WAIT(\"FALSE\")) \n mmcm_adv_inst\n (.CLKFBIN(clkfbout_buf_camera_pll),\n .CLKFBOUT(clkfbout_camera_pll),\n .CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),\n .CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),\n .CLKIN1(sysclk_camera_pll),\n .CLKIN2(1'b0),\n .CLKINSEL(1'b1),\n .CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),\n .CLKOUT0(camera_pixel_clock_camera_pll),\n .CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),\n .CLKOUT1(camera_mclk_camera_pll),\n .CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),\n .CLKOUT2(i2c_clkin_camera_pll),\n .CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),\n .CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),\n .CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),\n .CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),\n .CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),\n .CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),\n .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DCLK(1'b0),\n .DEN(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),\n .DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),\n .DWE(1'b0),\n .LOCKED(NLW_mmcm_adv_inst_LOCKED_UNCONNECTED),\n .PSCLK(1'b0),\n .PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),\n .PSEN(1'b0),\n .PSINCDEC(1'b0),\n .PWRDWN(1'b0),\n .RST(1'b0));\nendmodule\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_stub.v", "content": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// --------------------------------------------------------------------------------\n// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016\n// Date : Tue Nov 15 14:32:35 2016\n// Host : david-desktop-arch running 64-bit unknown\n// Command : write_verilog -force -mode synth_stub -rename_top camera_pll -prefix\n// camera_pll_ camera_pll_stub.v\n// Design : camera_pll\n// Purpose : Stub declaration of top-level module interface\n// Device : xc7k325tffg900-2\n// --------------------------------------------------------------------------------\n\n// This empty module with port declaration file causes synthesis tools to infer a black box for IP.\n// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.\n// Please paste the declaration into a Verilog source file or add the file as an additional source.\nmodule camera_pll(camera_pixel_clock, camera_mclk, i2c_clkin, \n sysclk)\n/* synthesis syn_black_box black_box_pad_pin=\"camera_pixel_clock,camera_mclk,i2c_clkin,sysclk\" */;\n output camera_pixel_clock;\n output camera_mclk;\n output i2c_clkin;\n input sysclk;\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if/mig_a.prj", "content": "\n\n\n ddr3_if\n 1\n 1\n OFF\n 1024\n ON\n Enabled\n xc7k325t-ffg900/-2\n 4.0\n No Buffer\n Use System Clock\n ACTIVE LOW\n FALSE\n 0\n OFF\n 0\n \n DDR3_SDRAM/Components/MT41J256m16XX-107\n 1250\n 2.0V\n 4:1\n 200\n 0\n 800\n 1.000\n 1\n 1\n 1\n 1\n 32\n 1\n 1\n Disabled\n Normal\n 2\n FALSE\n \n 15\n 10\n 3\n 1.5V\n ROW_BANK_COLUMN\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 8 - Fixed\n Sequential\n 11\n Normal\n No\n Slow Exit\n Enable\n RZQ/7\n Disable\n Enable\n RZQ/6\n 0\n Disabled\n Enabled\n Output Buffer Enabled\n Full Array\n 8\n Enabled\n Normal\n Dynamic ODT off\n AXI\n \n RD_PRI_REG_STARVE_LIMIT\n 30\n 256\n 1\n 0\n \n \n\n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if/mig_b.prj", "content": "\n\n\n ddr3_if\n 1\n 1\n OFF\n 1024\n ON\n Enabled\n xc7k325t-ffg900/-2\n 4.0\n No Buffer\n Use System Clock\n ACTIVE LOW\n FALSE\n 0\n OFF\n 0\n \n DDR3_SDRAM/Components/MT41J256m16XX-107\n 1875\n 1.8V\n 4:1\n 200\n 0\n 1066\n 1.000\n 1\n 1\n 1\n 1\n 32\n 1\n 1\n Disabled\n Normal\n 2\n FALSE\n \n 15\n 10\n 3\n 1.5V\n ROW_BANK_COLUMN\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 8 - Fixed\n Sequential\n 7\n Normal\n No\n Slow Exit\n Enable\n RZQ/7\n Disable\n Enable\n RZQ/6\n 0\n Disabled\n Enabled\n Output Buffer Enabled\n Full Array\n 6\n Enabled\n Normal\n Dynamic ODT off\n AXI\n \n RD_PRI_REG_STARVE_LIMIT\n 30\n 256\n 1\n 0\n \n \n\n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/constraints/ddr3_if.xdc", "content": "##################################################################################################\n## \n## Xilinx, Inc. 2010 www.xilinx.com \n## Tue Nov 15 09:39:56 2016\n## Generated by MIG Version 4.0\n## \n##################################################################################################\n## File name : ddr3_if.xdc\n## Details : Constraints file\n## FPGA Family: KINTEX7\n## FPGA Part: XC7K325T-FFG900\n## Speedgrade: -2\n## Design Entry: VERILOG\n## Frequency: 0 MHz\n## Time Period: 1112 ps\n##################################################################################################\n\n##################################################################################################\n## Controller 0\n## Memory Device: DDR3_SDRAM->Components->MT41J256m16XX-107\n## Data Width: 32\n## Time Period: 1112\n## Data Mask: 1\n##################################################################################################\n\n#create_clock -period 5.004 [get_ports sys_clk_i]\n \n############## NET - IOSTANDARD ##################\n\n\n# PadFunction: IO_L1N_T0_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[0]}]\nset_property SLEW FAST [get_ports {ddr3_dq[0]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[0]}]\nset_property PACKAGE_PIN AD3 [get_ports {ddr3_dq[0]}]\n\n# PadFunction: IO_L2P_T0_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[1]}]\nset_property SLEW FAST [get_ports {ddr3_dq[1]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[1]}]\nset_property PACKAGE_PIN AC2 [get_ports {ddr3_dq[1]}]\n\n# PadFunction: IO_L2N_T0_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[2]}]\nset_property SLEW FAST [get_ports {ddr3_dq[2]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[2]}]\nset_property PACKAGE_PIN AC1 [get_ports {ddr3_dq[2]}]\n\n# PadFunction: IO_L4P_T0_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[3]}]\nset_property SLEW FAST [get_ports {ddr3_dq[3]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[3]}]\nset_property PACKAGE_PIN AC5 [get_ports {ddr3_dq[3]}]\n\n# PadFunction: IO_L4N_T0_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[4]}]\nset_property SLEW FAST [get_ports {ddr3_dq[4]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[4]}]\nset_property PACKAGE_PIN AC4 [get_ports {ddr3_dq[4]}]\n\n# PadFunction: IO_L5P_T0_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[5]}]\nset_property SLEW FAST [get_ports {ddr3_dq[5]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[5]}]\nset_property PACKAGE_PIN AD6 [get_ports {ddr3_dq[5]}]\n\n# PadFunction: IO_L5N_T0_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[6]}]\nset_property SLEW FAST [get_ports {ddr3_dq[6]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[6]}]\nset_property PACKAGE_PIN AE6 [get_ports {ddr3_dq[6]}]\n\n# PadFunction: IO_L6P_T0_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[7]}]\nset_property SLEW FAST [get_ports {ddr3_dq[7]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[7]}]\nset_property PACKAGE_PIN AC7 [get_ports {ddr3_dq[7]}]\n\n# PadFunction: IO_L7N_T1_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[8]}]\nset_property SLEW FAST [get_ports {ddr3_dq[8]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[8]}]\nset_property PACKAGE_PIN AF2 [get_ports {ddr3_dq[8]}]\n\n# PadFunction: IO_L8P_T1_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[9]}]\nset_property SLEW FAST [get_ports {ddr3_dq[9]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[9]}]\nset_property PACKAGE_PIN AE1 [get_ports {ddr3_dq[9]}]\n\n# PadFunction: IO_L8N_T1_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[10]}]\nset_property SLEW FAST [get_ports {ddr3_dq[10]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[10]}]\nset_property PACKAGE_PIN AF1 [get_ports {ddr3_dq[10]}]\n\n# PadFunction: IO_L10P_T1_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[11]}]\nset_property SLEW FAST [get_ports {ddr3_dq[11]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[11]}]\nset_property PACKAGE_PIN AE4 [get_ports {ddr3_dq[11]}]\n\n# PadFunction: IO_L10N_T1_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[12]}]\nset_property SLEW FAST [get_ports {ddr3_dq[12]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[12]}]\nset_property PACKAGE_PIN AE3 [get_ports {ddr3_dq[12]}]\n\n# PadFunction: IO_L11P_T1_SRCC_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[13]}]\nset_property SLEW FAST [get_ports {ddr3_dq[13]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[13]}]\nset_property PACKAGE_PIN AE5 [get_ports {ddr3_dq[13]}]\n\n# PadFunction: IO_L11N_T1_SRCC_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[14]}]\nset_property SLEW FAST [get_ports {ddr3_dq[14]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[14]}]\nset_property PACKAGE_PIN AF5 [get_ports {ddr3_dq[14]}]\n\n# PadFunction: IO_L12P_T1_MRCC_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[15]}]\nset_property SLEW FAST [get_ports {ddr3_dq[15]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[15]}]\nset_property PACKAGE_PIN AF6 [get_ports {ddr3_dq[15]}]\n\n# PadFunction: IO_L13N_T2_MRCC_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[16]}]\nset_property SLEW FAST [get_ports {ddr3_dq[16]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[16]}]\nset_property PACKAGE_PIN AJ4 [get_ports {ddr3_dq[16]}]\n\n# PadFunction: IO_L14P_T2_SRCC_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[17]}]\nset_property SLEW FAST [get_ports {ddr3_dq[17]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[17]}]\nset_property PACKAGE_PIN AH6 [get_ports {ddr3_dq[17]}]\n\n# PadFunction: IO_L14N_T2_SRCC_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[18]}]\nset_property SLEW FAST [get_ports {ddr3_dq[18]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[18]}]\nset_property PACKAGE_PIN AH5 [get_ports {ddr3_dq[18]}]\n\n# PadFunction: IO_L16P_T2_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[19]}]\nset_property SLEW FAST [get_ports {ddr3_dq[19]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[19]}]\nset_property PACKAGE_PIN AH2 [get_ports {ddr3_dq[19]}]\n\n# PadFunction: IO_L16N_T2_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[20]}]\nset_property SLEW FAST [get_ports {ddr3_dq[20]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[20]}]\nset_property PACKAGE_PIN AJ2 [get_ports {ddr3_dq[20]}]\n\n# PadFunction: IO_L17P_T2_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[21]}]\nset_property SLEW FAST [get_ports {ddr3_dq[21]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[21]}]\nset_property PACKAGE_PIN AJ1 [get_ports {ddr3_dq[21]}]\n\n# PadFunction: IO_L17N_T2_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[22]}]\nset_property SLEW FAST [get_ports {ddr3_dq[22]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[22]}]\nset_property PACKAGE_PIN AK1 [get_ports {ddr3_dq[22]}]\n\n# PadFunction: IO_L18P_T2_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[23]}]\nset_property SLEW FAST [get_ports {ddr3_dq[23]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[23]}]\nset_property PACKAGE_PIN AJ3 [get_ports {ddr3_dq[23]}]\n\n# PadFunction: IO_L20P_T3_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[24]}]\nset_property SLEW FAST [get_ports {ddr3_dq[24]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[24]}]\nset_property PACKAGE_PIN AF7 [get_ports {ddr3_dq[24]}]\n\n# PadFunction: IO_L20N_T3_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[25]}]\nset_property SLEW FAST [get_ports {ddr3_dq[25]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[25]}]\nset_property PACKAGE_PIN AG7 [get_ports {ddr3_dq[25]}]\n\n# PadFunction: IO_L22P_T3_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[26]}]\nset_property SLEW FAST [get_ports {ddr3_dq[26]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[26]}]\nset_property PACKAGE_PIN AJ6 [get_ports {ddr3_dq[26]}]\n\n# PadFunction: IO_L22N_T3_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[27]}]\nset_property SLEW FAST [get_ports {ddr3_dq[27]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[27]}]\nset_property PACKAGE_PIN AK6 [get_ports {ddr3_dq[27]}]\n\n# PadFunction: IO_L23P_T3_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[28]}]\nset_property SLEW FAST [get_ports {ddr3_dq[28]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[28]}]\nset_property PACKAGE_PIN AJ8 [get_ports {ddr3_dq[28]}]\n\n# PadFunction: IO_L23N_T3_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[29]}]\nset_property SLEW FAST [get_ports {ddr3_dq[29]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[29]}]\nset_property PACKAGE_PIN AK8 [get_ports {ddr3_dq[29]}]\n\n# PadFunction: IO_L24P_T3_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[30]}]\nset_property SLEW FAST [get_ports {ddr3_dq[30]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[30]}]\nset_property PACKAGE_PIN AK5 [get_ports {ddr3_dq[30]}]\n\n# PadFunction: IO_L24N_T3_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dq[31]}]\nset_property SLEW FAST [get_ports {ddr3_dq[31]}]\nset_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[31]}]\nset_property PACKAGE_PIN AK4 [get_ports {ddr3_dq[31]}]\n\n# PadFunction: IO_L16N_T2_33 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[14]}]\nset_property SLEW FAST [get_ports {ddr3_addr[14]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[14]}]\nset_property PACKAGE_PIN AH9 [get_ports {ddr3_addr[14]}]\n\n# PadFunction: IO_L1P_T0_33 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[13]}]\nset_property SLEW FAST [get_ports {ddr3_addr[13]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[13]}]\nset_property PACKAGE_PIN AA12 [get_ports {ddr3_addr[13]}]\n\n# PadFunction: IO_L1N_T0_33 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[12]}]\nset_property SLEW FAST [get_ports {ddr3_addr[12]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[12]}]\nset_property PACKAGE_PIN AB12 [get_ports {ddr3_addr[12]}]\n\n# PadFunction: IO_L2P_T0_33 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[11]}]\nset_property SLEW FAST [get_ports {ddr3_addr[11]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[11]}]\nset_property PACKAGE_PIN AA8 [get_ports {ddr3_addr[11]}]\n\n# PadFunction: IO_L2N_T0_33 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[10]}]\nset_property SLEW FAST [get_ports {ddr3_addr[10]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[10]}]\nset_property PACKAGE_PIN AB8 [get_ports {ddr3_addr[10]}]\n\n# PadFunction: IO_L4P_T0_33 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[9]}]\nset_property SLEW FAST [get_ports {ddr3_addr[9]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[9]}]\nset_property PACKAGE_PIN Y11 [get_ports {ddr3_addr[9]}]\n\n# PadFunction: IO_L4N_T0_33 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[8]}]\nset_property SLEW FAST [get_ports {ddr3_addr[8]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[8]}]\nset_property PACKAGE_PIN Y10 [get_ports {ddr3_addr[8]}]\n\n# PadFunction: IO_L5P_T0_33 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[7]}]\nset_property SLEW FAST [get_ports {ddr3_addr[7]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[7]}]\nset_property PACKAGE_PIN AA11 [get_ports {ddr3_addr[7]}]\n\n# PadFunction: IO_L5N_T0_33 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[6]}]\nset_property SLEW FAST [get_ports {ddr3_addr[6]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[6]}]\nset_property PACKAGE_PIN AA10 [get_ports {ddr3_addr[6]}]\n\n# PadFunction: IO_L6P_T0_33 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[5]}]\nset_property SLEW FAST [get_ports {ddr3_addr[5]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[5]}]\nset_property PACKAGE_PIN AA13 [get_ports {ddr3_addr[5]}]\n\n# PadFunction: IO_L10P_T1_33 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[4]}]\nset_property SLEW FAST [get_ports {ddr3_addr[4]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[4]}]\nset_property PACKAGE_PIN AD9 [get_ports {ddr3_addr[4]}]\n\n# PadFunction: IO_L7N_T1_33 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[3]}]\nset_property SLEW FAST [get_ports {ddr3_addr[3]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[3]}]\nset_property PACKAGE_PIN AC10 [get_ports {ddr3_addr[3]}]\n\n# PadFunction: IO_L8P_T1_33 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[2]}]\nset_property SLEW FAST [get_ports {ddr3_addr[2]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[2]}]\nset_property PACKAGE_PIN AD8 [get_ports {ddr3_addr[2]}]\n\n# PadFunction: IO_L8N_T1_33 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[1]}]\nset_property SLEW FAST [get_ports {ddr3_addr[1]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[1]}]\nset_property PACKAGE_PIN AE8 [get_ports {ddr3_addr[1]}]\n\n# PadFunction: IO_L9P_T1_DQS_33 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_addr[0]}]\nset_property SLEW FAST [get_ports {ddr3_addr[0]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[0]}]\nset_property PACKAGE_PIN AC12 [get_ports {ddr3_addr[0]}]\n\n# PadFunction: IO_L9N_T1_DQS_33 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_ba[2]}]\nset_property SLEW FAST [get_ports {ddr3_ba[2]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[2]}]\nset_property PACKAGE_PIN AC11 [get_ports {ddr3_ba[2]}]\n\n# PadFunction: IO_L7P_T1_33 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_ba[1]}]\nset_property SLEW FAST [get_ports {ddr3_ba[1]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[1]}]\nset_property PACKAGE_PIN AB10 [get_ports {ddr3_ba[1]}]\n\n# PadFunction: IO_L10N_T1_33 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_ba[0]}]\nset_property SLEW FAST [get_ports {ddr3_ba[0]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[0]}]\nset_property PACKAGE_PIN AE9 [get_ports {ddr3_ba[0]}]\n\n# PadFunction: IO_L11P_T1_SRCC_33 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_ras_n}]\nset_property SLEW FAST [get_ports {ddr3_ras_n}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_ras_n}]\nset_property PACKAGE_PIN AE11 [get_ports {ddr3_ras_n}]\n\n# PadFunction: IO_L11N_T1_SRCC_33 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_cas_n}]\nset_property SLEW FAST [get_ports {ddr3_cas_n}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_cas_n}]\nset_property PACKAGE_PIN AF11 [get_ports {ddr3_cas_n}]\n\n# PadFunction: IO_L24P_T3_33 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_we_n}]\nset_property SLEW FAST [get_ports {ddr3_we_n}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_we_n}]\nset_property PACKAGE_PIN AG13 [get_ports {ddr3_we_n}]\n\n# PadFunction: IO_L12N_T1_MRCC_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_reset_n}]\nset_property SLEW FAST [get_ports {ddr3_reset_n}]\nset_property IOSTANDARD LVCMOS15 [get_ports {ddr3_reset_n}]\nset_property PACKAGE_PIN AG5 [get_ports {ddr3_reset_n}]\n\n# PadFunction: IO_L15P_T2_DQS_33 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_cke[0]}]\nset_property SLEW FAST [get_ports {ddr3_cke[0]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_cke[0]}]\nset_property PACKAGE_PIN AJ9 [get_ports {ddr3_cke[0]}]\n\n# PadFunction: IO_L15N_T2_DQS_33 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_odt[0]}]\nset_property SLEW FAST [get_ports {ddr3_odt[0]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_odt[0]}]\nset_property PACKAGE_PIN AK9 [get_ports {ddr3_odt[0]}]\n\n# PadFunction: IO_L24N_T3_33 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_cs_n[0]}]\nset_property SLEW FAST [get_ports {ddr3_cs_n[0]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_cs_n[0]}]\nset_property PACKAGE_PIN AH12 [get_ports {ddr3_cs_n[0]}]\n\n# PadFunction: IO_L1P_T0_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dm[0]}]\nset_property SLEW FAST [get_ports {ddr3_dm[0]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[0]}]\nset_property PACKAGE_PIN AD4 [get_ports {ddr3_dm[0]}]\n\n# PadFunction: IO_L7P_T1_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dm[1]}]\nset_property SLEW FAST [get_ports {ddr3_dm[1]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[1]}]\nset_property PACKAGE_PIN AF3 [get_ports {ddr3_dm[1]}]\n\n# PadFunction: IO_L13P_T2_MRCC_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dm[2]}]\nset_property SLEW FAST [get_ports {ddr3_dm[2]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[2]}]\nset_property PACKAGE_PIN AH4 [get_ports {ddr3_dm[2]}]\n\n# PadFunction: IO_L19P_T3_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dm[3]}]\nset_property SLEW FAST [get_ports {ddr3_dm[3]}]\nset_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[3]}]\nset_property PACKAGE_PIN AF8 [get_ports {ddr3_dm[3]}]\n\n# PadFunction: IO_L3P_T0_DQS_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[0]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_p[0]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[0]}]\nset_property PACKAGE_PIN AD2 [get_ports {ddr3_dqs_p[0]}]\n\n# PadFunction: IO_L3N_T0_DQS_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[0]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_n[0]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[0]}]\nset_property PACKAGE_PIN AD1 [get_ports {ddr3_dqs_n[0]}]\n\n# PadFunction: IO_L9P_T1_DQS_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[1]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_p[1]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[1]}]\nset_property PACKAGE_PIN AG4 [get_ports {ddr3_dqs_p[1]}]\n\n# PadFunction: IO_L9N_T1_DQS_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[1]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_n[1]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[1]}]\nset_property PACKAGE_PIN AG3 [get_ports {ddr3_dqs_n[1]}]\n\n# PadFunction: IO_L15P_T2_DQS_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[2]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_p[2]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[2]}]\nset_property PACKAGE_PIN AG2 [get_ports {ddr3_dqs_p[2]}]\n\n# PadFunction: IO_L15N_T2_DQS_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[2]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_n[2]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[2]}]\nset_property PACKAGE_PIN AH1 [get_ports {ddr3_dqs_n[2]}]\n\n# PadFunction: IO_L21P_T3_DQS_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[3]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_p[3]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[3]}]\nset_property PACKAGE_PIN AH7 [get_ports {ddr3_dqs_p[3]}]\n\n# PadFunction: IO_L21N_T3_DQS_34 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[3]}]\nset_property SLEW FAST [get_ports {ddr3_dqs_n[3]}]\nset_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[3]}]\nset_property PACKAGE_PIN AJ7 [get_ports {ddr3_dqs_n[3]}]\n\n# PadFunction: IO_L3P_T0_DQS_33 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_ck_p[0]}]\nset_property SLEW FAST [get_ports {ddr3_ck_p[0]}]\nset_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_p[0]}]\nset_property PACKAGE_PIN AB9 [get_ports {ddr3_ck_p[0]}]\n\n# PadFunction: IO_L3N_T0_DQS_33 \nset_property VCCAUX_IO HIGH [get_ports {ddr3_ck_n[0]}]\nset_property SLEW FAST [get_ports {ddr3_ck_n[0]}]\nset_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_n[0]}]\nset_property PACKAGE_PIN AC9 [get_ports {ddr3_ck_n[0]}]\n\n\n\nset_property LOC PHASER_OUT_PHY_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}]\nset_property LOC PHASER_OUT_PHY_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}]\nset_property LOC PHASER_OUT_PHY_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}]\nset_property LOC PHASER_OUT_PHY_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}]\nset_property LOC PHASER_OUT_PHY_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}]\nset_property LOC PHASER_OUT_PHY_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}]\nset_property LOC PHASER_OUT_PHY_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}]\nset_property LOC PHASER_OUT_PHY_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}]\n\n## set_property LOC PHASER_IN_PHY_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}]\n## set_property LOC PHASER_IN_PHY_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}]\n## set_property LOC PHASER_IN_PHY_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}]\n## set_property LOC PHASER_IN_PHY_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}]\nset_property LOC PHASER_IN_PHY_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}]\nset_property LOC PHASER_IN_PHY_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}]\nset_property LOC PHASER_IN_PHY_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}]\nset_property LOC PHASER_IN_PHY_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}]\n\n\n\nset_property LOC OUT_FIFO_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}]\nset_property LOC OUT_FIFO_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}]\nset_property LOC OUT_FIFO_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}]\nset_property LOC OUT_FIFO_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}]\nset_property LOC OUT_FIFO_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}]\nset_property LOC OUT_FIFO_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}]\nset_property LOC OUT_FIFO_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}]\nset_property LOC OUT_FIFO_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}]\n\nset_property LOC IN_FIFO_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo}]\nset_property LOC IN_FIFO_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo}]\nset_property LOC IN_FIFO_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo}]\nset_property LOC IN_FIFO_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo}]\n\nset_property LOC PHY_CONTROL_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/phy_control_i}]\nset_property LOC PHY_CONTROL_X1Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i}]\n\nset_property LOC PHASER_REF_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/phaser_ref_i}]\nset_property LOC PHASER_REF_X1Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i}]\n\nset_property LOC OLOGIC_X1Y143 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts}]\nset_property LOC OLOGIC_X1Y131 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts}]\nset_property LOC OLOGIC_X1Y119 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts}]\nset_property LOC OLOGIC_X1Y107 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts}]\n\nset_property LOC PLLE2_ADV_X1Y1 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/plle2_i}]\nset_property LOC MMCME2_ADV_X1Y1 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/gen_mmcm.mmcm_i}]\n\n\nset_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \\\n -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \\\n -setup 6\n\nset_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \\\n -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \\\n -hold 5\n\nset_false_path -through [get_pins -filter {NAME =~ */DQSFOUND} -of [get_cells -hier -filter {REF_NAME == PHASER_IN_PHY}]]\n\nset_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -setup 2 -start\nset_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -hold 1 -start\n\nset_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1*}] 20\nset_max_delay -from [get_cells -hier *rstdiv0_sync_r1_reg*] -to [get_pins -filter {NAME =~ */RESET} -of [get_cells -hier -filter {REF_NAME == PHY_CONTROL}]] -datapath_only 5\nset_false_path -through [get_pins -hier -filter {NAME =~ */u_iodelay_ctrl/sys_rst}]\n \nset_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *ddr3_infrastructure/rstdiv0_sync_r1_reg*}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1*}] 20\n " }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/constraints/ddr3_if_ooc.xdc", "content": "###################################################################################################\n## This constraints file contains default clock frequencies to be used during creation of a \n## Synthesis Design Checkpoint (DCP). For best results the frequencies should be modified \n## to match the target frequencies. \n## This constraints file is not used in top-down/global synthesis (not the default flow of Vivado).\n###################################################################################################\n\n\n##################################################################################################\n## \n## Xilinx, Inc. 2010 www.xilinx.com \n## Tue Nov 15 09:39:56 2016\n## Generated by MIG Version 4.0\n## \n##################################################################################################\n## File name : ddr3_if.xdc\n## Details : Constraints file\n## FPGA Family: KINTEX7\n## FPGA Part: XC7K325T-FFG900\n## Speedgrade: -2\n## Design Entry: VERILOG\n## Frequency: 0 MHz\n## Time Period: 1112 ps\n##################################################################################################\n\n##################################################################################################\n## Controller 0\n## Memory Device: DDR3_SDRAM->Components->MT41J256m16XX-107\n## Data Width: 32\n## Time Period: 1112\n## Data Mask: 1\n##################################################################################################\n\ncreate_clock -period 5.004 [get_ports sys_clk_i]\n " }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_addr_decode.v", "content": "// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. \n// -- \n// -- This file contains confidential and proprietary information \n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property \n// -- laws. \n// -- \n// -- DISCLAIMER \n// -- This disclaimer is not a license and does not grant any \n// -- rights to the materials distributed herewith. Except as \n// -- otherwise provided in a valid license issued to you by \n// -- Xilinx, and to the maximum extent permitted by applicable \n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND \n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES \n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING \n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- \n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and \n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of \n// -- liability) for any loss or damage of any kind or nature \n// -- related to, arising under or in connection with these \n// -- materials, including for any direct, or any indirect, \n// -- special, incidental, or consequential loss or damage \n// -- (including loss of data, profits, goodwill, or any type of \n// -- loss or damage suffered as a result of any action brought \n// -- by a third party) even if such damage or loss was \n// -- reasonably foreseeable or Xilinx had been advised of the \n// -- possibility of the same. \n// -- \n// -- CRITICAL APPLICATIONS \n// -- Xilinx products are not designed or intended to be fail- \n// -- safe, or for use in any application requiring fail-safe \n// -- performance, such as life-support or safety devices or \n// -- systems, Class III medical devices, nuclear facilities, \n// -- applications related to the deployment of airbags, or any \n// -- other applications that could lead to death, personal \n// -- injury, or severe property or environmental damage \n// -- (individually and collectively, \"Critical \n// -- Applications\"). Customer assumes the sole risk and \n// -- liability of any use of Xilinx products in Critical \n// -- Applications, subject only to applicable laws and \n// -- regulations governing limitations on product liability. \n// -- \n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS \n// -- PART OF THIS FILE AT ALL TIMES. \n// -- \n///////////////////////////////////////////////////////////////////////////////\n//\n// File name: axi_ctrl_ecc_top.v\n//\n// Description: \n//\n// Specifications:\n//\n// Structure:\n//\n///////////////////////////////////////////////////////////////////////////////\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule mig_7series_v4_0_axi_ctrl_addr_decode #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n // Width of AXI-4-Lite address bus\n parameter integer C_ADDR_WIDTH = 32,\n // Number of Registers\n parameter integer C_NUM_REG = 5,\n parameter integer C_NUM_REG_WIDTH = 3,\n // Number of Registers\n parameter C_REG_ADDR_ARRAY = 160'h0000_f00C_0000_f008_0000_f004_0000_f000_FFFF_FFFF,\n parameter C_REG_RDWR_ARRAY = 5'b00101\n\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations \n///////////////////////////////////////////////////////////////////////////////\n // AXI4-Lite Slave Interface\n // Slave Interface System Signals \n input wire [C_ADDR_WIDTH-1:0] axaddr , \n // Slave Interface Write Data Ports\n output wire [C_NUM_REG_WIDTH-1:0] reg_decode_num\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n\nfunction [C_ADDR_WIDTH-1:0] calc_bit_mask (\n input [C_NUM_REG*C_ADDR_WIDTH-1:0] addr_decode_array\n);\nbegin : func_calc_bit_mask\n integer i;\n reg [C_ADDR_WIDTH-1:0] first_addr;\n reg [C_ADDR_WIDTH-1:0] bit_mask;\n\n calc_bit_mask = {C_ADDR_WIDTH{1'b0}};\n first_addr = addr_decode_array[C_ADDR_WIDTH+:C_ADDR_WIDTH];\n\n for (i = 2; i < C_NUM_REG; i = i + 1) begin\n bit_mask = first_addr ^ addr_decode_array[C_ADDR_WIDTH*i +: C_ADDR_WIDTH];\n calc_bit_mask = calc_bit_mask | bit_mask;\n end\nend\nendfunction\n\nfunction integer lsb_mask_index (\n input [C_ADDR_WIDTH-1:0] mask\n);\nbegin : my_lsb_mask_index\n lsb_mask_index = 0;\n while ((lsb_mask_index < C_ADDR_WIDTH-1) && ~mask[lsb_mask_index]) begin \n lsb_mask_index = lsb_mask_index + 1;\n end\nend\nendfunction\n\nfunction integer msb_mask_index (\n input [C_ADDR_WIDTH-1:0] mask\n);\nbegin : my_msb_mask_index\n msb_mask_index = C_ADDR_WIDTH-1;\n while ((msb_mask_index > 0) && ~mask[msb_mask_index]) begin \n msb_mask_index = msb_mask_index - 1;\n end\nend\nendfunction\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam P_ADDR_BIT_MASK = calc_bit_mask(C_REG_ADDR_ARRAY);\nlocalparam P_MASK_LSB = lsb_mask_index(P_ADDR_BIT_MASK);\nlocalparam P_MASK_MSB = msb_mask_index(P_ADDR_BIT_MASK);\nlocalparam P_MASK_WIDTH = P_MASK_MSB - P_MASK_LSB + 1;\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\ninteger i;\n(* rom_extract = \"no\" *)\nreg [C_NUM_REG_WIDTH-1:0] reg_decode_num_i;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n///////////////////////////////////////////////////////////////////////////////\nalways @(*) begin \n reg_decode_num_i = {C_NUM_REG_WIDTH{1'b0}};\n for (i = 1; i < C_NUM_REG; i = i + 1) begin : decode_addr\n if ((axaddr[P_MASK_MSB:P_MASK_LSB] == C_REG_ADDR_ARRAY[i*C_ADDR_WIDTH+P_MASK_LSB+:P_MASK_WIDTH]) \n && C_REG_RDWR_ARRAY[i] ) begin\n reg_decode_num_i = i[C_NUM_REG_WIDTH-1:0];\n end\n end\nend\n\nassign reg_decode_num = reg_decode_num_i;\n\nendmodule\n\n`default_nettype wire\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_read.v", "content": "// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. \n// -- \n// -- This file contains confidential and proprietary information \n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property \n// -- laws. \n// -- \n// -- DISCLAIMER \n// -- This disclaimer is not a license and does not grant any \n// -- rights to the materials distributed herewith. Except as \n// -- otherwise provided in a valid license issued to you by \n// -- Xilinx, and to the maximum extent permitted by applicable \n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND \n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES \n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING \n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- \n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and \n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of \n// -- liability) for any loss or damage of any kind or nature \n// -- related to, arising under or in connection with these \n// -- materials, including for any direct, or any indirect, \n// -- special, incidental, or consequential loss or damage \n// -- (including loss of data, profits, goodwill, or any type of \n// -- loss or damage suffered as a result of any action brought \n// -- by a third party) even if such damage or loss was \n// -- reasonably foreseeable or Xilinx had been advised of the \n// -- possibility of the same. \n// -- \n// -- CRITICAL APPLICATIONS \n// -- Xilinx products are not designed or intended to be fail- \n// -- safe, or for use in any application requiring fail-safe \n// -- performance, such as life-support or safety devices or \n// -- systems, Class III medical devices, nuclear facilities, \n// -- applications related to the deployment of airbags, or any \n// -- other applications that could lead to death, personal \n// -- injury, or severe property or environmental damage \n// -- (individually and collectively, \"Critical \n// -- Applications\"). Customer assumes the sole risk and \n// -- liability of any use of Xilinx products in Critical \n// -- Applications, subject only to applicable laws and \n// -- regulations governing limitations on product liability. \n// -- \n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS \n// -- PART OF THIS FILE AT ALL TIMES. \n// -- \n///////////////////////////////////////////////////////////////////////////////\n//\n// File name: axi_ctrl_read.v\n//\n// Description: \n//\n// Specifications:\n//\n// Structure:\n// axi_ctrl_top\n// axi_ctrl_write\n// axi_ctrl_addr_decode\n// axi_ctrl_read\n// axi_ctrl_addr_decode\n// axi_ctrl_reg_bank\n// axi_ctrl_reg\n//\n///////////////////////////////////////////////////////////////////////////////\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule mig_7series_v4_0_axi_ctrl_read #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n // Width of AXI-4-Lite address bus\n parameter integer C_ADDR_WIDTH = 32,\n // Width of AXI-4-Lite data buses\n parameter integer C_DATA_WIDTH = 32,\n // Number of Registers\n parameter integer C_NUM_REG = 5,\n parameter integer C_NUM_REG_WIDTH = 3,\n // Number of Registers\n parameter C_REG_ADDR_ARRAY = 160'h0000_f00C_0000_f008_0000_f004_0000_f000_FFFF_FFFF,\n parameter C_REG_RDAC_ARRAY = 5'b11111 \n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations \n///////////////////////////////////////////////////////////////////////////////\n // AXI4-Lite Slave Interface\n // Slave Interface System Signals \n input wire clk , \n input wire reset , \n // Slave Interface Read Address Ports\n input wire [C_ADDR_WIDTH-1:0] araddr , \n // Slave Interface Read Data Ports\n output wire rvalid , \n input wire rready , \n output wire [C_DATA_WIDTH-1:0] rdata , \n output wire [1:0] rresp , \n\n input wire pending ,\n // MC Internal Signals\n input wire [C_DATA_WIDTH*C_NUM_REG-1:0] reg_bank_array \n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\nwire [C_NUM_REG_WIDTH-1:0] reg_decode_num;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n///////////////////////////////////////////////////////////////////////////////\n\nmig_7series_v4_0_axi_ctrl_addr_decode #\n(\n .C_ADDR_WIDTH ( C_ADDR_WIDTH ) ,\n .C_NUM_REG ( C_NUM_REG ) ,\n .C_NUM_REG_WIDTH ( C_NUM_REG_WIDTH ) ,\n .C_REG_ADDR_ARRAY ( C_REG_ADDR_ARRAY ) ,\n .C_REG_RDWR_ARRAY ( C_REG_RDAC_ARRAY ) \n)\naxi_ctrl_addr_decode_0\n(\n .axaddr ( araddr ) ,\n .reg_decode_num ( reg_decode_num ) \n);\n\nassign rdata = reg_bank_array[ reg_decode_num*32+:32];\nassign rresp = 2'b0; // Okay\n\nassign rvalid = pending;\n\nendmodule\n\n`default_nettype wire\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_reg.v", "content": "// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. \n// -- \n// -- This file contains confidential and proprietary information \n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property \n// -- laws. \n// -- \n// -- DISCLAIMER \n// -- This disclaimer is not a license and does not grant any \n// -- rights to the materials distributed herewith. Except as \n// -- otherwise provided in a valid license issued to you by \n// -- Xilinx, and to the maximum extent permitted by applicable \n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND \n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES \n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING \n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- \n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and \n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of \n// -- liability) for any loss or damage of any kind or nature \n// -- related to, arising under or in connection with these \n// -- materials, including for any direct, or any indirect, \n// -- special, incidental, or consequential loss or damage \n// -- (including loss of data, profits, goodwill, or any type of \n// -- loss or damage suffered as a result of any action brought \n// -- by a third party) even if such damage or loss was \n// -- reasonably foreseeable or Xilinx had been advised of the \n// -- possibility of the same. \n// -- \n// -- CRITICAL APPLICATIONS \n// -- Xilinx products are not designed or intended to be fail- \n// -- safe, or for use in any application requiring fail-safe \n// -- performance, such as life-support or safety devices or \n// -- systems, Class III medical devices, nuclear facilities, \n// -- applications related to the deployment of airbags, or any \n// -- other applications that could lead to death, personal \n// -- injury, or severe property or environmental damage \n// -- (individually and collectively, \"Critical \n// -- Applications\"). Customer assumes the sole risk and \n// -- liability of any use of Xilinx products in Critical \n// -- Applications, subject only to applicable laws and \n// -- regulations governing limitations on product liability. \n// -- \n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS \n// -- PART OF THIS FILE AT ALL TIMES. \n// -- \n///////////////////////////////////////////////////////////////////////////////\n//\n// File name: axi_ctrl_reg.v \n//\n// Description: \n// This is just a general register. It has two write enables and two data ins \n// to simplify the operation. Typically one write enable (we) comes from the \n// external interface and the second write enable is used for internal writing\n// to the register. A mask parameter is used to only write to the bits that\n// are used in the register.\n//\n// Specifications:\n//\n// Structure:\n// axi_ctrl_top\n// axi_ctrl_write\n// axi_ctrl_addr_decode\n// axi_ctrl_read\n// axi_ctrl_addr_decode\n// axi_ctrl_reg_bank\n// axi_ctrl_reg\n//\n///////////////////////////////////////////////////////////////////////////////\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule mig_7series_v4_0_axi_ctrl_reg #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n parameter integer C_REG_WIDTH = 32,\n parameter integer C_DATA_WIDTH = 32,\n parameter C_INIT = 32'h0,\n parameter C_MASK = 32'h1\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations \n///////////////////////////////////////////////////////////////////////////////\n input wire clk , \n input wire reset , \n input wire [C_REG_WIDTH-1:0] data_in , \n input wire we , \n input wire we_int , \n input wire [C_REG_WIDTH-1:0] data_in_int , \n output wire [C_DATA_WIDTH-1:0] data_out\n);\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nreg [C_REG_WIDTH-1:0] data;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n///////////////////////////////////////////////////////////////////////////////\nalways @(posedge clk) begin\n if (reset) begin\n data <= C_INIT[0+:C_REG_WIDTH];\n end\n else if (we) begin\n data <= data_in;\n end\n else if (we_int) begin\n data <= data_in_int;\n end\n else begin\n data <= data;\n end\nend\n\n// Does not supprot case where P_MASK_LSB > 0\ngenerate \n if (C_REG_WIDTH == C_DATA_WIDTH) begin : assign_no_zero_pad\n assign data_out = data;\n end\n else begin : assign_zero_pad\n assign data_out = {{C_DATA_WIDTH-C_REG_WIDTH{1'b0}}, data};\n end\nendgenerate\n\nendmodule\n\n`default_nettype wire\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_reg_bank.v", "content": "// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. \n// -- \n// -- This file contains confidential and proprietary information \n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property \n// -- laws. \n// -- \n// -- DISCLAIMER \n// -- This disclaimer is not a license and does not grant any \n// -- rights to the materials distributed herewith. Except as \n// -- otherwise provided in a valid license issued to you by \n// -- Xilinx, and to the maximum extent permitted by applicable \n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND \n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES \n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING \n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- \n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and \n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of \n// -- liability) for any loss or damage of any kind or nature \n// -- related to, arising under or in connection with these \n// -- materials, including for any direct, or any indirect, \n// -- special, incidental, or consequential loss or damage \n// -- (including loss of data, profits, goodwill, or any type of \n// -- loss or damage suffered as a result of any action brought \n// -- by a third party) even if such damage or loss was \n// -- reasonably foreseeable or Xilinx had been advised of the \n// -- possibility of the same. \n// -- \n// -- CRITICAL APPLICATIONS \n// -- Xilinx products are not designed or intended to be fail- \n// -- safe, or for use in any application requiring fail-safe \n// -- performance, such as life-support or safety devices or \n// -- systems, Class III medical devices, nuclear facilities, \n// -- applications related to the deployment of airbags, or any \n// -- other applications that could lead to death, personal \n// -- injury, or severe property or environmental damage \n// -- (individually and collectively, \"Critical \n// -- Applications\"). Customer assumes the sole risk and \n// -- liability of any use of Xilinx products in Critical \n// -- Applications, subject only to applicable laws and \n// -- regulations governing limitations on product liability. \n// -- \n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS \n// -- PART OF THIS FILE AT ALL TIMES. \n// -- \n///////////////////////////////////////////////////////////////////////////////\n//\n// File name: axi_ctrl_ecc_top.v\n//\n// Description: \n//\n// Specifications:\n//\n// Structure:\n//\n///////////////////////////////////////////////////////////////////////////////\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule mig_7series_v4_0_axi_ctrl_reg_bank #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n // Width of AXI-4-Lite address bus\n parameter C_ADDR_WIDTH = 32,\n parameter C_DATA_WIDTH = 32,\n parameter C_DQ_WIDTH = 72,\n parameter C_ECC_CE_COUNTER_WIDTH = 8,\n parameter C_ECC_ONOFF_RESET_VALUE = 1,\n parameter C_ECC_TEST = \"ON\",\n parameter C_ECC_WIDTH = 8,\n parameter C_MC_ERR_ADDR_WIDTH = 28,\n parameter C_MEM_ADDR_ORDER = \"BANK_ROW_COLUMN\",\n // # of memory Bank Address bits.\n parameter C_BANK_WIDTH = 3,\n // # of memory Row Address bits. \n parameter C_ROW_WIDTH = 14,\n // # of memory Column Address bits. \n parameter C_COL_WIDTH = 10,\n parameter C_NCK_PER_CLK = 2,\n parameter C_NUM_REG = 24,\n parameter C_NUM_REG_WIDTH = 5,\n parameter C_S_AXI_ADDR_WIDTH = 32,\n parameter C_S_AXI_BASEADDR = 32'h0000_0000,\n // Register arrays\n parameter C_REG_WIDTH_ARRAY = 160'h0,\n parameter C_REG_RDAC_ARRAY = 5'b0,\n parameter C_REG_WRAC_ARRAY = 5'b0,\n parameter C_REG_INIT_ARRAY = 160'h0,\n parameter C_REG_MASK_ARRAY = 160'h0,\n parameter C_REG_ADDR_ARRAY = 160'h0000_f00C_0000_f008_0000_f004_0000_f000_FFFF_FFFF,\n // Register Indices\n parameter integer C_REG_FI_ECC_INDX = 23,\n parameter integer C_REG_FI_D_127_96_INDX = 22,\n parameter integer C_REG_FI_D_95_64_INDX = 21,\n parameter integer C_REG_FI_D_63_32_INDX = 20,\n parameter integer C_REG_FI_D_31_00_INDX = 19,\n parameter integer C_REG_UE_FFA_63_32_INDX = 18,\n parameter integer C_REG_UE_FFA_31_00_INDX = 17,\n parameter integer C_REG_UE_FFE_INDX = 16,\n parameter integer C_REG_UE_FFD_127_96_INDX = 15,\n parameter integer C_REG_UE_FFD_95_64_INDX = 14,\n parameter integer C_REG_UE_FFD_63_32_INDX = 13,\n parameter integer C_REG_UE_FFD_31_00_INDX = 12,\n parameter integer C_REG_CE_FFA_63_32_INDX = 11,\n parameter integer C_REG_CE_FFA_31_00_INDX = 10,\n parameter integer C_REG_CE_FFE_INDX = 9 ,\n parameter integer C_REG_CE_FFD_127_96_INDX = 8 ,\n parameter integer C_REG_CE_FFD_95_64_INDX = 7 ,\n parameter integer C_REG_CE_FFD_63_32_INDX = 6 ,\n parameter integer C_REG_CE_FFD_31_00_INDX = 5 ,\n parameter integer C_REG_CE_CNT_INDX = 4 ,\n parameter integer C_REG_ECC_ON_OFF_INDX = 3 ,\n parameter integer C_REG_ECC_EN_IRQ_INDX = 2 ,\n parameter integer C_REG_ECC_STATUS_INDX = 1 ,\n parameter integer C_REG_DUMMY_INDX = 0 \n\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations \n///////////////////////////////////////////////////////////////////////////////\n // AXI4-Lite Slave Interface\n // Slave Interface System Signals \n input wire clk , \n input wire reset ,\n input wire [C_NUM_REG_WIDTH-1:0] reg_data_sel , \n input wire reg_data_write , \n input wire [C_DATA_WIDTH-1:0] reg_data_in , \n output wire [C_DATA_WIDTH*C_NUM_REG-1:0] reg_data_out ,\n\n output wire interrupt ,\n input wire [2*C_NCK_PER_CLK-1:0] ecc_single ,\n input wire [2*C_NCK_PER_CLK-1:0] ecc_multiple ,\n input wire [C_MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr ,\n output wire app_correct_en , \n input wire [2*C_NCK_PER_CLK*C_DQ_WIDTH-1:0] dfi_rddata , \n output wire [C_DQ_WIDTH/8-1:0] fi_xor_we ,\n output wire [C_DQ_WIDTH-1:0] fi_xor_wrdata \n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Functions\n////////////////////////////////////////////////////////////////////////////////\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam P_FI_XOR_WE_WIDTH = (C_DQ_WIDTH%C_DATA_WIDTH)/8; \nlocalparam P_SHIFT_BY = C_DQ_WIDTH == 72 ? 3 : 4;\nlocalparam P_CS_WIDTH = C_MC_ERR_ADDR_WIDTH - C_COL_WIDTH - C_ROW_WIDTH - C_BANK_WIDTH - 1;\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\ninteger beat;\nreg [C_DQ_WIDTH-1:0] ffs;\nreg [C_DQ_WIDTH-1:0] ffm;\nwire [7:0] ecc_single_expanded;\nwire [7:0] ecc_multiple_expanded;\nreg [C_S_AXI_ADDR_WIDTH-1:0] ffas;\nreg [C_S_AXI_ADDR_WIDTH-1:0] ffam;\nreg [2:0] ffas_lsb;\nreg [2:0] ffam_lsb;\nwire [C_MC_ERR_ADDR_WIDTH-2:0] ecc_err_addr_real;\nwire ecc_err_addr_offset;\nwire [C_MC_ERR_ADDR_WIDTH-2:0] ecc_err_addr_swap_row_bank;\nwire [C_MC_ERR_ADDR_WIDTH-2:0] ecc_err_addr_swapped;\nwire [C_NUM_REG-1:0] we;\nwire [C_DATA_WIDTH*C_NUM_REG-1:0] data_in;\nwire [C_NUM_REG-1:0] we_int;\nwire [C_DATA_WIDTH*C_NUM_REG-1:0] data_in_int;\nwire [C_DATA_WIDTH*C_NUM_REG-1:0] data_out;\nreg interrupt_r;\nreg ecc_on_off_r;\nreg ce_clr_r;\nreg ue_clr_r;\nwire ce_set_i;\nwire ue_set_i;\nreg [C_DQ_WIDTH/8-1:0] fi_xor_we_r;\nreg [C_DQ_WIDTH-1:0] fi_xor_wrdata_r;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n///////////////////////////////////////////////////////////////////////////////\n\n// Assign outputs\nassign reg_data_out = data_out;\nassign interrupt = interrupt_r & ecc_on_off_r;\nassign app_correct_en = ecc_on_off_r;\nassign fi_xor_wrdata = fi_xor_wrdata_r;\nassign fi_xor_we = fi_xor_we_r & {C_DQ_WIDTH/8{ecc_on_off_r}};\n\n// Calculate inputs\n// Always block selects the first failing beat out C_NCK_PER_CLK*2 beats. If\n// no failing beats, default to last beat.\nalways @(*) begin\n ffs = dfi_rddata[(C_NCK_PER_CLK*2-1)*C_DQ_WIDTH+:C_DQ_WIDTH];\n ffm = dfi_rddata[(C_NCK_PER_CLK*2-1)*C_DQ_WIDTH+:C_DQ_WIDTH];\n\n for( beat = C_NCK_PER_CLK*2-2; beat >= 0 ; beat = beat - 1) begin : find_first_failing_beat\n if (ecc_single[beat]) begin\n ffs = dfi_rddata[beat*C_DQ_WIDTH+:C_DQ_WIDTH];\n // ffas_lsb = beat[2:0]; // | {ecc_err_addr_offset| ecc_err_addr_real[2], 2'b0};\n end\n if (ecc_multiple[beat]) begin\n ffm = dfi_rddata[beat*C_DQ_WIDTH+:C_DQ_WIDTH];\n // ffam_lsb = beat[2:0]; // | {ecc_err_addr_offset| ecc_err_addr_real[2], 2'b0};\n end\n end\nend\n\ngenerate\n if (C_NCK_PER_CLK == 2) begin : ecc_zero_extened\n assign ecc_single_expanded = {4'b0, ecc_single[3:0]};\n assign ecc_multiple_expanded = {4'b0, ecc_multiple[3:0]};\n end\n else begin : no_ecc_zero_extend\n assign ecc_single_expanded = ecc_single[7:0];\n assign ecc_multiple_expanded = ecc_multiple[7:0];\n end\nendgenerate\n\nalways @(*) begin \n (* full_case *) (* parallel_case *)\n casex (ecc_single_expanded) \n 8'bxxxx_xxx1: \n ffas_lsb = 3'o0;\n 8'bxxxx_xx10: \n ffas_lsb = 3'o1;\n 8'bxxxx_x100: \n ffas_lsb = 3'o2;\n 8'bxxxx_1000: \n ffas_lsb = 3'o3;\n 8'bxxx1_0000: \n ffas_lsb = 3'o4;\n 8'bxx10_0000: \n ffas_lsb = 3'o5;\n 8'bx100_0000: \n ffas_lsb = 3'o6;\n 8'b1000_0000: \n ffas_lsb = 3'o7;\n default:\n ffas_lsb = 3'o0;\n endcase\nend\n\nalways @(*) begin \n (* full_case *) (* parallel_case *)\n casex (ecc_multiple_expanded)\n 8'bxxxx_xxx1: \n ffam_lsb = 3'o0;\n 8'bxxxx_xx10: \n ffam_lsb = 3'o1;\n 8'bxxxx_x100: \n ffam_lsb = 3'o2;\n 8'bxxxx_1000: \n ffam_lsb = 3'o3;\n 8'bxxx1_0000: \n ffam_lsb = 3'o4;\n 8'bxx10_0000: \n ffam_lsb = 3'o5;\n 8'bx100_0000: \n ffam_lsb = 3'o6;\n 8'b1000_0000: \n ffam_lsb = 3'o7;\n default:\n ffam_lsb = 3'o0;\n endcase\nend\n\n// Calculate first failing address\n// Split ecc_err_addr, lower bit of ecc_err_addr is the offset, and not part\n// of the column address.\nassign ecc_err_addr_real[C_MC_ERR_ADDR_WIDTH-2:3] = ecc_err_addr[C_MC_ERR_ADDR_WIDTH-1:4];\n// if ecc_err_addr[0] == 1, then the error is on the 2nd 4 beats of BL8.\nassign ecc_err_addr_real[2] = ecc_err_addr[3] | ecc_err_addr[0];\n// Lower two bits always expected to be 0b00\nassign ecc_err_addr_real[1:0] = ecc_err_addr[2:1];\n\n// Swap Row Bank bits if we need it. Special case for no cs bits.\nassign ecc_err_addr_swap_row_bank[C_COL_WIDTH+:C_ROW_WIDTH+C_BANK_WIDTH] = \n {ecc_err_addr_real[C_COL_WIDTH+:C_ROW_WIDTH], ecc_err_addr_real[C_COL_WIDTH+C_ROW_WIDTH+:C_BANK_WIDTH]};\nassign ecc_err_addr_swap_row_bank[0+:C_COL_WIDTH] = ecc_err_addr_real[0+:C_COL_WIDTH];\n\ngenerate\nbegin\n if (P_CS_WIDTH > 0) begin : CS_WIDTH_ASSIGN\n assign ecc_err_addr_swap_row_bank[C_COL_WIDTH+C_ROW_WIDTH+C_BANK_WIDTH+:P_CS_WIDTH] = \n ecc_err_addr_real[C_COL_WIDTH+C_ROW_WIDTH+C_BANK_WIDTH+:P_CS_WIDTH];\n end\nend\nendgenerate\n\n// swap row/bank if necessary\nassign ecc_err_addr_swapped = (C_MEM_ADDR_ORDER == \"BANK_ROW_COLUMN\") ? ecc_err_addr_real : ecc_err_addr_swap_row_bank;\n\n// Assign final result\nalways @(*) begin\n ffas = ({ecc_err_addr_swapped[3+:C_MC_ERR_ADDR_WIDTH-4], (ffas_lsb[2] | ecc_err_addr_real[2]), ffas_lsb[1:0]} \n << P_SHIFT_BY) | C_S_AXI_BASEADDR;\n ffam = ({ecc_err_addr_swapped[3+:C_MC_ERR_ADDR_WIDTH-4], (ffam_lsb[2] | ecc_err_addr_real[2]), ffam_lsb[1:0]} \n << P_SHIFT_BY) | C_S_AXI_BASEADDR;\nend\n \n\n\ngenerate\n genvar i;\n genvar j;\n\n for (i = 0; i < C_NUM_REG; i = i + 1) begin : inst_reg\n if (C_REG_MASK_ARRAY[i*C_DATA_WIDTH+:C_DATA_WIDTH] > 0) begin \n mig_7series_v4_0_axi_ctrl_reg #\n (\n .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n .C_REG_WIDTH ( C_REG_WIDTH_ARRAY[i*C_DATA_WIDTH+:C_DATA_WIDTH]) ,\n .C_INIT ( C_REG_INIT_ARRAY[i*C_DATA_WIDTH+:C_DATA_WIDTH] ) ,\n .C_MASK ( C_REG_MASK_ARRAY[i*C_DATA_WIDTH+:C_DATA_WIDTH] ) \n ) \n axi_ctrl_reg\n (\n .clk ( clk ) ,\n .reset ( reset ) ,\n .data_in ( data_in[i*C_DATA_WIDTH+:C_REG_WIDTH_ARRAY[i*C_DATA_WIDTH+:C_DATA_WIDTH]] ) ,\n .we ( we[i] ) ,\n .data_in_int ( data_in_int[i*C_DATA_WIDTH+:C_REG_WIDTH_ARRAY[i*C_DATA_WIDTH+:C_DATA_WIDTH]] ) ,\n .we_int ( we_int[i] ) ,\n .data_out ( data_out[i*C_DATA_WIDTH+:C_DATA_WIDTH] ) \n );\n end\n else begin : no_reg\n assign data_out[i*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n end\n end\n\n // Determine write logic for each register\n for (j = 0; j < C_NUM_REG; j = j + 1) begin : inst_reg_logic_\n case (j)\n C_REG_ECC_STATUS_INDX: \n begin\n // Bit Name Desc\n // 1 CE_STATUS If '1' a correctable error has occurred. Cleared when '1' is written to this bit \n // position.\n // 0 UE_STATUS If '1' a uncorrectable error has occurred. Cleared when '1' is written to this bit \n // position.\n assign we[j] = (reg_data_sel == j) && reg_data_write;\n assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = ~reg_data_in & data_out[j*C_DATA_WIDTH+:C_DATA_WIDTH];\n assign we_int[j] = ecc_on_off_r;\n assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {30'b0, (|ecc_single | data_out[j*C_DATA_WIDTH + 1]), \n (|ecc_multiple | data_out[j*C_DATA_WIDTH + 0])};\n\n // Drive internal signals to write to other registers\n always @(posedge clk) begin \n ce_clr_r <= ~data_in[j*C_DATA_WIDTH + 1] & we[j];\n ue_clr_r <= ~data_in[j*C_DATA_WIDTH + 0] & we[j];\n end\n\n assign ce_set_i = data_in_int[j*C_DATA_WIDTH + 1] & we_int[j] & ~data_out[j*C_DATA_WIDTH + 1];\n assign ue_set_i = data_in_int[j*C_DATA_WIDTH + 0] & we_int[j] & ~data_out[j*C_DATA_WIDTH + 0];\n end\n C_REG_ECC_EN_IRQ_INDX: \n begin\n // Bit Name Desc\n // 1 CE_EN_IRQ If '1' the value of the CE_STATUS bit of ECC Status Register will be propagated to the\n // Interrupt signal. If '0' the value of the CE_STATUS bit of ECC Status Register will not\n // be propagated to the Interrupt signal.\n // position.\n // 0 UE_EN_IRQ See above\n // \n assign we[j] = (reg_data_sel == j) ? reg_data_write : 1'b0;\n assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = reg_data_in;\n assign we_int[j] = 1'b0;\n assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n\n always @(posedge clk) begin\n interrupt_r <= |(data_out[j*C_DATA_WIDTH+:C_DATA_WIDTH] \n & data_out[C_REG_ECC_STATUS_INDX*C_DATA_WIDTH+:C_DATA_WIDTH]);\n end\n end\n C_REG_ECC_ON_OFF_INDX: \n begin\n // Bit Name Desc\n // 0 ECC_ON_OFF If '0', ECC checking is disable on read operations. If '1', ECC checking is enabled on \n // read operations. All correctable and uncorrectable error condtions will be captured\n // and status updated.\n assign we[j] = (reg_data_sel == j) ? reg_data_write : 1'b0;\n assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = reg_data_in;\n assign we_int[j] = 1'b0;\n assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n\n always @(posedge clk) begin\n ecc_on_off_r <= data_out[j*C_DATA_WIDTH+0];\n end\n end\n C_REG_CE_CNT_INDX: \n begin\n // Bit Name Desc\n // 7:0 CE_CNT Register holds number of correctable errors encountered.\n assign we[j] = (reg_data_sel == j) ? reg_data_write : 1'b0;\n assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = reg_data_in;\n assign data_in_int[j*C_DATA_WIDTH+:C_ECC_CE_COUNTER_WIDTH+1] \n = data_out[j*C_DATA_WIDTH+:C_ECC_CE_COUNTER_WIDTH+1] + 1'b1;\n assign data_in_int[j*C_DATA_WIDTH+C_ECC_CE_COUNTER_WIDTH+1+:C_DATA_WIDTH-(C_ECC_CE_COUNTER_WIDTH+1)] \n = {C_DATA_WIDTH-(C_ECC_CE_COUNTER_WIDTH+1){1'b0}};\n // Only write if there is an error and it will not cause an overflow\n assign we_int[j] = ecc_on_off_r & (|ecc_single) & ~data_in_int[j*C_DATA_WIDTH + C_ECC_CE_COUNTER_WIDTH];\n\n end\n C_REG_CE_FFD_31_00_INDX: \n begin\n assign we[j] = ce_clr_r;\n assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n assign we_int[j] = ce_set_i;\n assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = ffs[0*C_DATA_WIDTH+:C_DATA_WIDTH];\n end\n C_REG_CE_FFD_63_32_INDX: \n begin\n assign we[j] = ce_clr_r;\n assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n assign we_int[j] = ce_set_i;\n assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = ffs[1*C_DATA_WIDTH+:C_DATA_WIDTH];\n end\n C_REG_CE_FFD_95_64_INDX: \n begin\n if (C_DQ_WIDTH == 144) begin\n assign we[j] = ce_clr_r;\n assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n assign we_int[j] = ce_set_i;\n assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = ffs[2*C_DATA_WIDTH+:C_DATA_WIDTH];\n end\n else begin\n assign we[j] = 1'b0;\n assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n assign we_int[j] = 1'b0;\n assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n end\n end\n C_REG_CE_FFD_127_96_INDX: \n begin\n if (C_DQ_WIDTH == 144) begin\n assign we[j] = ce_clr_r;\n assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n assign we_int[j] = ce_set_i;\n assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = ffs[3*C_DATA_WIDTH+:C_DATA_WIDTH];\n end\n else begin\n assign we[j] = 1'b0;\n assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n assign we_int[j] = 1'b0;\n assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n end\n end\n\n C_REG_CE_FFE_INDX: \n begin\n assign we[j] = ce_clr_r;\n assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n assign we_int[j] = ce_set_i;\n if (C_DQ_WIDTH == 144) begin\n assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {{C_DATA_WIDTH-C_ECC_WIDTH{1'b0}}, ffs[128+:C_ECC_WIDTH] };\n end\n else begin\n assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {{C_DATA_WIDTH-C_ECC_WIDTH{1'b0}}, ffs[ 64+:C_ECC_WIDTH] };\n end\n end\n C_REG_CE_FFA_31_00_INDX: \n begin\n assign we[j] = ce_clr_r;\n assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n assign we_int[j] = ce_set_i;\n if (C_S_AXI_ADDR_WIDTH < C_DATA_WIDTH) begin \n assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {{(C_DATA_WIDTH-C_S_AXI_ADDR_WIDTH){1'b0}}, ffas[0*C_DATA_WIDTH+:C_S_AXI_ADDR_WIDTH]};\n end else begin\n assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = ffas[0*C_DATA_WIDTH+:C_DATA_WIDTH];\n end\n end\n\n C_REG_CE_FFA_63_32_INDX: \n begin\n assign we[j] = (C_S_AXI_ADDR_WIDTH > 32) ? ce_clr_r : 1'b0;\n assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n assign we_int[j] = (C_S_AXI_ADDR_WIDTH > 32) ? ce_set_i : 1'b0;\n if (C_S_AXI_ADDR_WIDTH > C_DATA_WIDTH) begin \n assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {{((2*C_DATA_WIDTH)-C_S_AXI_ADDR_WIDTH){1'b0}}, ffas[C_DATA_WIDTH+:(C_S_AXI_ADDR_WIDTH-C_DATA_WIDTH)]};\n end else begin\n assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n end\n end\n\n C_REG_UE_FFD_31_00_INDX: \n begin\n assign we[j] = ue_clr_r;\n assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n assign we_int[j] = ue_set_i;\n assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = ffm[0*C_DATA_WIDTH+:C_DATA_WIDTH];\n end\n C_REG_UE_FFD_63_32_INDX: \n begin\n assign we[j] = ue_clr_r;\n assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n assign we_int[j] = ue_set_i;\n assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = ffm[1*C_DATA_WIDTH+:C_DATA_WIDTH];\n end\n C_REG_UE_FFD_95_64_INDX: \n begin\n if (C_DQ_WIDTH == 144) begin\n assign we[j] = ue_clr_r;\n assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n assign we_int[j] = ue_set_i;\n assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = ffm[2*C_DATA_WIDTH+:C_DATA_WIDTH];\n end\n else begin\n assign we[j] = 1'b0;\n assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n assign we_int[j] = 1'b0;\n assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n end\n end\n C_REG_UE_FFD_127_96_INDX: \n begin\n if (C_DQ_WIDTH == 144) begin\n assign we[j] = ue_clr_r;\n assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n assign we_int[j] = ue_set_i;\n assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = ffm[3*C_DATA_WIDTH+:C_DATA_WIDTH];\n end\n else begin\n assign we[j] = 1'b0;\n assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n assign we_int[j] = 1'b0;\n assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n end\n end\n C_REG_UE_FFE_INDX: \n begin\n assign we[j] = ue_clr_r;\n assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n assign we_int[j] = ue_set_i;\n if (C_DQ_WIDTH == 144) begin\n assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {{C_DATA_WIDTH-C_ECC_WIDTH{1'b0}}, ffm[128+:C_ECC_WIDTH] };\n end\n else begin\n assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {{C_DATA_WIDTH-C_ECC_WIDTH{1'b0}}, ffm[ 64+:C_ECC_WIDTH] };\n end\n end\n C_REG_UE_FFA_31_00_INDX: \n begin\n assign we[j] = ue_clr_r;\n assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n assign we_int[j] = ue_set_i;\n if (C_S_AXI_ADDR_WIDTH < C_DATA_WIDTH) begin \n assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {{(C_DATA_WIDTH-C_S_AXI_ADDR_WIDTH){1'b0}}, ffam[0*C_DATA_WIDTH+:C_S_AXI_ADDR_WIDTH]};\n end else begin\n assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = ffam[0*C_DATA_WIDTH+:C_DATA_WIDTH];\n end\n end\n\n C_REG_UE_FFA_63_32_INDX: \n begin\n assign we[j] = (C_S_AXI_ADDR_WIDTH > 32) ? ue_clr_r : 1'b0;\n assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n assign we_int[j] = (C_S_AXI_ADDR_WIDTH > 32) ? ue_set_i : 1'b0;\n if (C_S_AXI_ADDR_WIDTH > C_DATA_WIDTH) begin \n assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {{((2*C_DATA_WIDTH)-C_S_AXI_ADDR_WIDTH){1'b0}}, ffam[C_DATA_WIDTH+:(C_S_AXI_ADDR_WIDTH-C_DATA_WIDTH)]};\n end else begin\n assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n end\n end\n\n C_REG_FI_D_31_00_INDX: \n begin\n assign we[j] = 1'b0;\n assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n assign we_int[j] = 1'b0;\n assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n\n //if (C_ECC_TEST == \"ON\") begin\n always @(posedge clk) begin\n fi_xor_we_r[0*C_DATA_WIDTH/8+:C_DATA_WIDTH/8] <= (reg_data_sel == j) ? {C_DATA_WIDTH/8{reg_data_write}} \n : {C_DATA_WIDTH/8{1'b0}};\n fi_xor_wrdata_r[0*C_DATA_WIDTH+:C_DATA_WIDTH] <= reg_data_in[C_DATA_WIDTH-1:0];\n end\n //end\n end\n C_REG_FI_D_63_32_INDX: \n begin\n assign we[j] = 1'b0;\n assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n assign we_int[j] = 1'b0;\n assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n\n //if (C_ECC_TEST == \"ON\") begin\n always @(posedge clk) begin\n fi_xor_we_r[1*C_DATA_WIDTH/8+:C_DATA_WIDTH/8] <= (reg_data_sel == j) ? {C_DATA_WIDTH/8{reg_data_write}} \n : {C_DATA_WIDTH/8{1'b0}};\n fi_xor_wrdata_r[1*C_DATA_WIDTH+:C_DATA_WIDTH] <= reg_data_in[C_DATA_WIDTH-1:0];\n end\n //end\n end\n C_REG_FI_D_95_64_INDX: \n begin\n assign we[j] = 1'b0;\n assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n assign we_int[j] = 1'b0;\n assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n\n if (C_DQ_WIDTH == 144 /*&& C_ECC_TEST == \"ON\"*/) begin\n always @(posedge clk) begin\n fi_xor_we_r[2*C_DATA_WIDTH/8+:C_DATA_WIDTH/8] <= (reg_data_sel == j) ? {C_DATA_WIDTH/8{reg_data_write}} \n : {C_DATA_WIDTH/8{1'b0}};\n fi_xor_wrdata_r[2*C_DATA_WIDTH+:C_DATA_WIDTH] <= reg_data_in[C_DATA_WIDTH-1:0];\n end\n end\n end\n C_REG_FI_D_127_96_INDX: \n begin\n assign we[j] = 1'b0;\n assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n assign we_int[j] = 1'b0;\n assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n\n if (C_DQ_WIDTH == 144 /*&& C_ECC_TEST == \"ON\"*/) begin\n always @(posedge clk) begin\n fi_xor_we_r[3*C_DATA_WIDTH/8+:C_DATA_WIDTH/8] <= (reg_data_sel == j) ? {C_DATA_WIDTH/8{reg_data_write}} \n : {C_DATA_WIDTH/8{1'b0}};\n fi_xor_wrdata_r[3*C_DATA_WIDTH+:C_DATA_WIDTH] <= reg_data_in[C_DATA_WIDTH-1:0];\n end\n end\n end\n C_REG_FI_ECC_INDX: \n begin\n assign we[j] = 1'b0;\n assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n\n assign we_int[j] = 1'b0;\n assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n\n if (C_DQ_WIDTH == 72 /*&& C_ECC_TEST == \"ON\"*/) begin\n always @(posedge clk) begin\n fi_xor_we_r[2*C_DATA_WIDTH/8+:P_FI_XOR_WE_WIDTH] <= (reg_data_sel == j) ? {P_FI_XOR_WE_WIDTH{reg_data_write}}\n : {P_FI_XOR_WE_WIDTH{1'b0}};\n fi_xor_wrdata_r[2*C_DATA_WIDTH+:C_DQ_WIDTH%C_DATA_WIDTH] <= reg_data_in[C_DQ_WIDTH%C_DATA_WIDTH-1:0];\n end\n end\n if (C_DQ_WIDTH == 144 /*&& C_ECC_TEST == \"ON\"*/) begin\n always @(posedge clk) begin\n fi_xor_we_r[4*C_DATA_WIDTH/8+:P_FI_XOR_WE_WIDTH] <= (reg_data_sel == j) ? {P_FI_XOR_WE_WIDTH{reg_data_write}}\n : {P_FI_XOR_WE_WIDTH{1'b0}};\n fi_xor_wrdata_r[4*C_DATA_WIDTH+:C_DQ_WIDTH%C_DATA_WIDTH] <= reg_data_in[C_DQ_WIDTH%C_DATA_WIDTH-1:0];\n end\n end\n end\n default: \n begin\n // Tie off reg inputs \n assign we[j] = 1'b0;\n assign data_in[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n assign we_int[j] = 1'b0;\n assign data_in_int[j*C_DATA_WIDTH+:C_DATA_WIDTH] = {C_DATA_WIDTH{1'b0}};\n end\n endcase\n end\n\n\nendgenerate \n\n\n\n \n \n\nendmodule\n\n`default_nettype wire\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_top.v", "content": "// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. \n// -- \n// -- This file contains confidential and proprietary information \n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property \n// -- laws. \n// -- \n// -- DISCLAIMER \n// -- This disclaimer is not a license and does not grant any \n// -- rights to the materials distributed herewith. Except as \n// -- otherwise provided in a valid license issued to you by \n// -- Xilinx, and to the maximum extent permitted by applicable \n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND \n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES \n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING \n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- \n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and \n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of \n// -- liability) for any loss or damage of any kind or nature \n// -- related to, arising under or in connection with these \n// -- materials, including for any direct, or any indirect, \n// -- special, incidental, or consequential loss or damage \n// -- (including loss of data, profits, goodwill, or any type of \n// -- loss or damage suffered as a result of any action brought \n// -- by a third party) even if such damage or loss was \n// -- reasonably foreseeable or Xilinx had been advised of the \n// -- possibility of the same. \n// -- \n// -- CRITICAL APPLICATIONS \n// -- Xilinx products are not designed or intended to be fail- \n// -- safe, or for use in any application requiring fail-safe \n// -- performance, such as life-support or safety devices or \n// -- systems, Class III medical devices, nuclear facilities, \n// -- applications related to the deployment of airbags, or any \n// -- other applications that could lead to death, personal \n// -- injury, or severe property or environmental damage \n// -- (individually and collectively, \"Critical \n// -- Applications\"). Customer assumes the sole risk and \n// -- liability of any use of Xilinx products in Critical \n// -- Applications, subject only to applicable laws and \n// -- regulations governing limitations on product liability. \n// -- \n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS \n// -- PART OF THIS FILE AT ALL TIMES. \n// -- \n///////////////////////////////////////////////////////////////////////////////\n//\n// File name: axi_ctrl_top.v\n//\n// Description: \n//\n// Specifications:\n//\n// Structure:\n// axi_ctrl_top\n// axi_ctrl_write\n// axi_ctrl_addr_decode\n// axi_ctrl_read\n// axi_ctrl_addr_decode\n// axi_ctrl_reg_bank\n// axi_ctrl_reg\n//\n///////////////////////////////////////////////////////////////////////////////\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule mig_7series_v4_0_axi_ctrl_top #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n // Width of AXI-4-Lite address bus\n parameter integer C_S_AXI_CTRL_ADDR_WIDTH = 32, \n // Width of AXI-4-Lite data buses\n parameter integer C_S_AXI_CTRL_DATA_WIDTH = 32, \n // Width of AXI-4 Memory Mapped address bus\n parameter integer C_S_AXI_ADDR_WIDTH = 32, \n // Width of AXI-4 Memory Mapped address bus\n parameter integer C_S_AXI_BASEADDR = 32'h0000_0000, \n // Enable or disable fault injection logic test hardware.\n parameter C_ECC_TEST = \"ON\",\n // External Memory Data Width\n parameter integer C_DQ_WIDTH = 72,\n // Memory ECC Width \n parameter integer C_ECC_WIDTH = 8,\n // Memory Address Order \n parameter C_MEM_ADDR_ORDER = \"BANK_ROW_COLUMN\",\n // # of memory Bank Address bits.\n parameter C_BANK_WIDTH = 3,\n // # of memory Row Address bits. \n parameter C_ROW_WIDTH = 14,\n // # of memory Column Address bits. \n parameter C_COL_WIDTH = 10,\n\n // Controls ECC on/off value at startup/reset\n parameter integer C_ECC_ONOFF_RESET_VALUE = 1,\n // Controls CE counter width \n parameter integer C_ECC_CE_COUNTER_WIDTH = 8,\n // The external memory to controller clock ratio.\n parameter integer C_NCK_PER_CLK = 2,\n parameter C_MC_ERR_ADDR_WIDTH = 28\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations \n///////////////////////////////////////////////////////////////////////////////\n // AXI4-Lite Slave Interface\n // Slave Interface System Signals \n input wire aclk , \n input wire aresetn , \n // Slave Interface Write Address Ports\n input wire s_axi_awvalid , \n output wire s_axi_awready , \n input wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_awaddr , \n // Slave Interface Write Data Ports\n input wire s_axi_wvalid , \n output wire s_axi_wready , \n input wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_wdata , \n // Slave Interface Write Response Ports\n output wire s_axi_bvalid , \n input wire s_axi_bready , \n output wire [1:0] s_axi_bresp , \n // Slave Interface Read Address Ports\n input wire s_axi_arvalid , \n output wire s_axi_arready , \n input wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_araddr , \n // Slave Interface Read Data Ports\n output wire s_axi_rvalid , \n input wire s_axi_rready , \n output wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_rdata , \n output wire [1:0] s_axi_rresp , \n\n // Interrupt output\n output wire interrupt ,\n\n // MC Internal Signals\n input wire init_complete , \n input wire [2*C_NCK_PER_CLK-1:0] ecc_single ,\n input wire [2*C_NCK_PER_CLK-1:0] ecc_multiple ,\n input wire [C_MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr ,\n output wire app_correct_en , \n input wire [2*C_NCK_PER_CLK*C_DQ_WIDTH-1:0] dfi_rddata , \n output wire [C_DQ_WIDTH/8-1:0] fi_xor_we ,\n output wire [C_DQ_WIDTH-1:0] fi_xor_wrdata \n);\n\n/////////////////////////////////////////////////////////////////////////////\n// Functions\n/////////////////////////////////////////////////////////////////////////////\n\nfunction integer lsb_mask_index (\n input [C_S_AXI_CTRL_DATA_WIDTH-1:0] mask\n);\nbegin : my_lsb_mask_index\n lsb_mask_index = 0;\n while ((lsb_mask_index < C_S_AXI_CTRL_DATA_WIDTH-1) && ~mask[lsb_mask_index]) begin \n lsb_mask_index = lsb_mask_index + 1;\n end\nend\nendfunction\n\nfunction integer msb_mask_index (\n input [C_S_AXI_CTRL_DATA_WIDTH-1:0] mask\n);\nbegin : my_msb_mask_index\n msb_mask_index = C_S_AXI_CTRL_DATA_WIDTH-1;\n while ((msb_mask_index > 0) && ~mask[msb_mask_index]) begin \n msb_mask_index = msb_mask_index - 1;\n end\nend\nendfunction\n\nfunction integer mask_width (\n input [C_S_AXI_CTRL_DATA_WIDTH-1:0] mask\n);\nbegin : my_mask_width\n if (msb_mask_index(mask) > lsb_mask_index(mask)) begin\n mask_width = msb_mask_index(mask) - lsb_mask_index(mask) + 1;\n end\n else begin\n mask_width = 1;\n end\nend\nendfunction\n\n// clog2.\nfunction integer clog2;\n // Value to calculate clog2 on\n input integer value;\nbegin\n for (clog2=0; value>0; clog2=clog2+1) begin\n value = value >> 1;\n end\nend\nendfunction\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n// BEGIN Auto-generated Register Mapping\nlocalparam P_NUM_REG = 24;\nlocalparam P_NUM_REG_WIDTH = clog2(P_NUM_REG);\n\nlocalparam P_REG_FI_ECC_RDAC = 1'b0;\nlocalparam P_REG_FI_ECC_INDX = 23;\nlocalparam P_REG_FI_ECC_INIT = 32'h0000_0000;\nlocalparam P_REG_FI_ECC_WRAC = (C_ECC_TEST == \"ON\") ? 1'b1 : 1'b0;\nlocalparam P_REG_FI_ECC_ADDR = 32'h0000_0380;\nlocalparam P_REG_FI_ECC_MASK = 32'h0000_0000;\n\nlocalparam P_REG_FI_D_127_96_RDAC = 1'b0;\nlocalparam P_REG_FI_D_127_96_INDX = 22;\nlocalparam P_REG_FI_D_127_96_INIT = 32'h0000_0000;\nlocalparam P_REG_FI_D_127_96_WRAC = (C_ECC_TEST == \"ON\") && (C_DQ_WIDTH > 72) ? 1'b1 : 1'b0;\nlocalparam P_REG_FI_D_127_96_ADDR = 32'h0000_030C;\nlocalparam P_REG_FI_D_127_96_MASK = 32'h0000_0000;\n\nlocalparam P_REG_FI_D_95_64_RDAC = 1'b0;\nlocalparam P_REG_FI_D_95_64_INDX = 21;\nlocalparam P_REG_FI_D_95_64_INIT = 32'h0000_0000;\nlocalparam P_REG_FI_D_95_64_WRAC = (C_ECC_TEST == \"ON\") && (C_DQ_WIDTH > 72) ? 1'b1 : 1'b0;\nlocalparam P_REG_FI_D_95_64_ADDR = 32'h0000_0308;\nlocalparam P_REG_FI_D_95_64_MASK = 32'h0000_0000;\n\nlocalparam P_REG_FI_D_63_32_RDAC = 1'b0;\nlocalparam P_REG_FI_D_63_32_INDX = 20;\nlocalparam P_REG_FI_D_63_32_INIT = 32'h0000_0000;\nlocalparam P_REG_FI_D_63_32_WRAC = (C_ECC_TEST == \"ON\") ? 1'b1 : 1'b0;\nlocalparam P_REG_FI_D_63_32_ADDR = 32'h0000_0304;\nlocalparam P_REG_FI_D_63_32_MASK = 32'h0000_0000;\n\nlocalparam P_REG_FI_D_31_00_RDAC = 1'b0;\nlocalparam P_REG_FI_D_31_00_INDX = 19;\nlocalparam P_REG_FI_D_31_00_INIT = 32'h0000_0000;\nlocalparam P_REG_FI_D_31_00_WRAC = (C_ECC_TEST == \"ON\") ? 1'b1 : 1'b0;\nlocalparam P_REG_FI_D_31_00_ADDR = 32'h0000_0300;\nlocalparam P_REG_FI_D_31_00_MASK = 32'h0000_0000;\n\nlocalparam P_REG_UE_FFA_63_32_RDAC = (C_S_AXI_ADDR_WIDTH > 32) ? 1'b1 : 1'b0;\nlocalparam P_REG_UE_FFA_63_32_INDX = 18;\nlocalparam P_REG_UE_FFA_63_32_INIT = 32'h0000_0000;\nlocalparam P_REG_UE_FFA_63_32_WRAC = 1'b0;\nlocalparam P_REG_UE_FFA_63_32_ADDR = 32'h0000_02C4;\nlocalparam P_REG_UE_FFA_63_32_MASK = 32'hFFFF_FFFF;\n\nlocalparam P_REG_UE_FFA_31_00_RDAC = 1'b1;\nlocalparam P_REG_UE_FFA_31_00_INDX = 17;\nlocalparam P_REG_UE_FFA_31_00_INIT = 32'h0000_0000;\nlocalparam P_REG_UE_FFA_31_00_WRAC = 1'b0;\nlocalparam P_REG_UE_FFA_31_00_ADDR = 32'h0000_02C0;\nlocalparam P_REG_UE_FFA_31_00_MASK = 32'hFFFF_FFFF;\n\nlocalparam P_REG_UE_FFE_RDAC = 1'b1;\nlocalparam P_REG_UE_FFE_INDX = 16;\nlocalparam P_REG_UE_FFE_INIT = 32'h0000_0000;\nlocalparam P_REG_UE_FFE_WRAC = 1'b0;\nlocalparam P_REG_UE_FFE_ADDR = 32'h0000_0280;\nlocalparam P_REG_UE_FFE_MASK = 32'h0000_FFFF;\n\nlocalparam P_REG_UE_FFD_127_96_RDAC = (C_DQ_WIDTH > 72) ? 1'b1 : 1'b0 ;\nlocalparam P_REG_UE_FFD_127_96_INDX = 15;\nlocalparam P_REG_UE_FFD_127_96_INIT = 32'h0000_0000;\nlocalparam P_REG_UE_FFD_127_96_WRAC = 1'b0;\nlocalparam P_REG_UE_FFD_127_96_ADDR = 32'h0000_020C;\nlocalparam P_REG_UE_FFD_127_96_MASK = 32'hFFFF_FFFF;\n\nlocalparam P_REG_UE_FFD_95_64_RDAC = (C_DQ_WIDTH > 72) ? 1'b1 : 1'b0 ;\nlocalparam P_REG_UE_FFD_95_64_INDX = 14;\nlocalparam P_REG_UE_FFD_95_64_INIT = 32'h0000_0000;\nlocalparam P_REG_UE_FFD_95_64_WRAC = 1'b0;\nlocalparam P_REG_UE_FFD_95_64_ADDR = 32'h0000_0208;\nlocalparam P_REG_UE_FFD_95_64_MASK = 32'hFFFF_FFFF;\n\nlocalparam P_REG_UE_FFD_63_32_RDAC = 1'b1;\nlocalparam P_REG_UE_FFD_63_32_INDX = 13;\nlocalparam P_REG_UE_FFD_63_32_INIT = 32'h0000_0000;\nlocalparam P_REG_UE_FFD_63_32_WRAC = 1'b0;\nlocalparam P_REG_UE_FFD_63_32_ADDR = 32'h0000_0204;\nlocalparam P_REG_UE_FFD_63_32_MASK = 32'hFFFF_FFFF;\n\nlocalparam P_REG_UE_FFD_31_00_RDAC = 1'b1;\nlocalparam P_REG_UE_FFD_31_00_INDX = 12;\nlocalparam P_REG_UE_FFD_31_00_INIT = 32'h0000_0000;\nlocalparam P_REG_UE_FFD_31_00_WRAC = 1'b0;\nlocalparam P_REG_UE_FFD_31_00_ADDR = 32'h0000_0200;\nlocalparam P_REG_UE_FFD_31_00_MASK = 32'hFFFF_FFFF;\n\nlocalparam P_REG_CE_FFA_63_32_RDAC = (C_S_AXI_ADDR_WIDTH > 32) ? 1'b1 : 1'b0;\nlocalparam P_REG_CE_FFA_63_32_INDX = 11;\nlocalparam P_REG_CE_FFA_63_32_INIT = 32'h0000_0000;\nlocalparam P_REG_CE_FFA_63_32_WRAC = 1'b0;\nlocalparam P_REG_CE_FFA_63_32_ADDR = 32'h0000_01C4;\nlocalparam P_REG_CE_FFA_63_32_MASK = 32'hFFFF_FFFF;\n\nlocalparam P_REG_CE_FFA_31_00_RDAC = 1'b1;\nlocalparam P_REG_CE_FFA_31_00_INDX = 10;\nlocalparam P_REG_CE_FFA_31_00_INIT = 32'h0000_0000;\nlocalparam P_REG_CE_FFA_31_00_WRAC = 1'b0;\nlocalparam P_REG_CE_FFA_31_00_ADDR = 32'h0000_01C0;\nlocalparam P_REG_CE_FFA_31_00_MASK = 32'hFFFF_FFFF;\n\nlocalparam P_REG_CE_FFE_RDAC = 1'b1;\nlocalparam P_REG_CE_FFE_INDX = 9;\nlocalparam P_REG_CE_FFE_INIT = 32'h0000_0000;\nlocalparam P_REG_CE_FFE_WRAC = 1'b0;\nlocalparam P_REG_CE_FFE_ADDR = 32'h0000_0180;\nlocalparam P_REG_CE_FFE_MASK = 32'h0000_FFFF;\n\nlocalparam P_REG_CE_FFD_127_96_RDAC = (C_DQ_WIDTH > 72) ? 1'b1 : 1'b0 ;\nlocalparam P_REG_CE_FFD_127_96_INDX = 8;\nlocalparam P_REG_CE_FFD_127_96_INIT = 32'h0000_0000;\nlocalparam P_REG_CE_FFD_127_96_WRAC = 1'b0;\nlocalparam P_REG_CE_FFD_127_96_ADDR = 32'h0000_010C;\nlocalparam P_REG_CE_FFD_127_96_MASK = 32'hFFFF_FFFF;\n\nlocalparam P_REG_CE_FFD_95_64_RDAC = (C_DQ_WIDTH > 72) ? 1'b1 : 1'b0 ;\nlocalparam P_REG_CE_FFD_95_64_INDX = 7;\nlocalparam P_REG_CE_FFD_95_64_INIT = 32'h0000_0000;\nlocalparam P_REG_CE_FFD_95_64_WRAC = 1'b0;\nlocalparam P_REG_CE_FFD_95_64_ADDR = 32'h0000_0108;\nlocalparam P_REG_CE_FFD_95_64_MASK = 32'hFFFF_FFFF;\n\nlocalparam P_REG_CE_FFD_63_32_RDAC = 1'b1;\nlocalparam P_REG_CE_FFD_63_32_INDX = 6;\nlocalparam P_REG_CE_FFD_63_32_INIT = 32'h0000_0000;\nlocalparam P_REG_CE_FFD_63_32_WRAC = 1'b0;\nlocalparam P_REG_CE_FFD_63_32_ADDR = 32'h0000_0104;\nlocalparam P_REG_CE_FFD_63_32_MASK = 32'hFFFF_FFFF;\n\nlocalparam P_REG_CE_FFD_31_00_RDAC = 1'b1;\nlocalparam P_REG_CE_FFD_31_00_INDX = 5;\nlocalparam P_REG_CE_FFD_31_00_INIT = 32'h0000_0000;\nlocalparam P_REG_CE_FFD_31_00_WRAC = 1'b0;\nlocalparam P_REG_CE_FFD_31_00_ADDR = 32'h0000_0100;\nlocalparam P_REG_CE_FFD_31_00_MASK = 32'hFFFF_FFFF;\n\nlocalparam P_REG_CE_CNT_RDAC = 1'b1;\nlocalparam P_REG_CE_CNT_INDX = 4;\nlocalparam P_REG_CE_CNT_INIT = 32'h0000_0000;\nlocalparam P_REG_CE_CNT_WRAC = 1'b1;\nlocalparam P_REG_CE_CNT_ADDR = 32'h0000_000C;\nlocalparam P_REG_CE_CNT_MASK = {{C_S_AXI_CTRL_DATA_WIDTH-C_ECC_CE_COUNTER_WIDTH{1'b0}}, {C_ECC_CE_COUNTER_WIDTH{1'b1}}};\n\nlocalparam P_REG_ECC_ON_OFF_RDAC = 1'b1;\nlocalparam P_REG_ECC_ON_OFF_INDX = 3;\nlocalparam P_REG_ECC_ON_OFF_INIT = {{31{1'b0}}, C_ECC_ONOFF_RESET_VALUE[0]};\nlocalparam P_REG_ECC_ON_OFF_WRAC = 1'b1;\nlocalparam P_REG_ECC_ON_OFF_ADDR = 32'h0000_0008;\nlocalparam P_REG_ECC_ON_OFF_MASK = 32'h0000_0001;\n\nlocalparam P_REG_ECC_EN_IRQ_RDAC = 1'b1;\nlocalparam P_REG_ECC_EN_IRQ_INDX = 2;\nlocalparam P_REG_ECC_EN_IRQ_INIT = 32'h0000_0000;\nlocalparam P_REG_ECC_EN_IRQ_WRAC = 1'b1;\nlocalparam P_REG_ECC_EN_IRQ_ADDR = 32'h0000_0004;\nlocalparam P_REG_ECC_EN_IRQ_MASK = 32'h0000_0003;\n\nlocalparam P_REG_ECC_STATUS_RDAC = 1'b1;\nlocalparam P_REG_ECC_STATUS_INDX = 1;\nlocalparam P_REG_ECC_STATUS_INIT = 32'h0000_0000;\nlocalparam P_REG_ECC_STATUS_WRAC = 1'b1;\nlocalparam P_REG_ECC_STATUS_ADDR = 32'h0000_0000;\nlocalparam P_REG_ECC_STATUS_MASK = 32'h0000_0003;\n\nlocalparam P_REG_DUMMY_RDAC = 1'b1;\nlocalparam P_REG_DUMMY_INDX = 0;\nlocalparam P_REG_DUMMY_INIT = 32'hDEAD_DEAD;\nlocalparam P_REG_DUMMY_WRAC = 1'b1;\nlocalparam P_REG_DUMMY_ADDR = 32'hFFFF_FFFF;\nlocalparam P_REG_DUMMY_MASK = 32'hFFFF_FFFF;\n\nlocalparam P_REG_INDX_ARRAY = {\n P_REG_FI_ECC_INDX,\n P_REG_FI_D_127_96_INDX,\n P_REG_FI_D_95_64_INDX,\n P_REG_FI_D_63_32_INDX,\n P_REG_FI_D_31_00_INDX,\n P_REG_UE_FFA_63_32_INDX,\n P_REG_UE_FFA_31_00_INDX,\n P_REG_UE_FFE_INDX,\n P_REG_UE_FFD_127_96_INDX,\n P_REG_UE_FFD_95_64_INDX,\n P_REG_UE_FFD_63_32_INDX,\n P_REG_UE_FFD_31_00_INDX,\n P_REG_CE_FFA_63_32_INDX,\n P_REG_CE_FFA_31_00_INDX,\n P_REG_CE_FFE_INDX,\n P_REG_CE_FFD_127_96_INDX,\n P_REG_CE_FFD_95_64_INDX,\n P_REG_CE_FFD_63_32_INDX,\n P_REG_CE_FFD_31_00_INDX,\n P_REG_CE_CNT_INDX,\n P_REG_ECC_ON_OFF_INDX,\n P_REG_ECC_EN_IRQ_INDX,\n P_REG_ECC_STATUS_INDX,\n P_REG_DUMMY_INDX\n};\n\nlocalparam P_REG_RDAC_ARRAY = {\n P_REG_FI_ECC_RDAC,\n P_REG_FI_D_127_96_RDAC,\n P_REG_FI_D_95_64_RDAC,\n P_REG_FI_D_63_32_RDAC,\n P_REG_FI_D_31_00_RDAC,\n P_REG_UE_FFA_63_32_RDAC,\n P_REG_UE_FFA_31_00_RDAC,\n P_REG_UE_FFE_RDAC,\n P_REG_UE_FFD_127_96_RDAC,\n P_REG_UE_FFD_95_64_RDAC,\n P_REG_UE_FFD_63_32_RDAC,\n P_REG_UE_FFD_31_00_RDAC,\n P_REG_CE_FFA_63_32_RDAC,\n P_REG_CE_FFA_31_00_RDAC,\n P_REG_CE_FFE_RDAC,\n P_REG_CE_FFD_127_96_RDAC,\n P_REG_CE_FFD_95_64_RDAC,\n P_REG_CE_FFD_63_32_RDAC,\n P_REG_CE_FFD_31_00_RDAC,\n P_REG_CE_CNT_RDAC,\n P_REG_ECC_ON_OFF_RDAC,\n P_REG_ECC_EN_IRQ_RDAC,\n P_REG_ECC_STATUS_RDAC,\n P_REG_DUMMY_RDAC\n};\n\nlocalparam P_REG_INIT_ARRAY = {\n P_REG_FI_ECC_INIT,\n P_REG_FI_D_127_96_INIT,\n P_REG_FI_D_95_64_INIT,\n P_REG_FI_D_63_32_INIT,\n P_REG_FI_D_31_00_INIT,\n P_REG_UE_FFA_63_32_INIT,\n P_REG_UE_FFA_31_00_INIT,\n P_REG_UE_FFE_INIT,\n P_REG_UE_FFD_127_96_INIT,\n P_REG_UE_FFD_95_64_INIT,\n P_REG_UE_FFD_63_32_INIT,\n P_REG_UE_FFD_31_00_INIT,\n P_REG_CE_FFA_63_32_INIT,\n P_REG_CE_FFA_31_00_INIT,\n P_REG_CE_FFE_INIT,\n P_REG_CE_FFD_127_96_INIT,\n P_REG_CE_FFD_95_64_INIT,\n P_REG_CE_FFD_63_32_INIT,\n P_REG_CE_FFD_31_00_INIT,\n P_REG_CE_CNT_INIT,\n P_REG_ECC_ON_OFF_INIT,\n P_REG_ECC_EN_IRQ_INIT,\n P_REG_ECC_STATUS_INIT,\n P_REG_DUMMY_INIT\n};\n\nlocalparam P_REG_ADDR_ARRAY = {\n P_REG_FI_ECC_ADDR,\n P_REG_FI_D_127_96_ADDR,\n P_REG_FI_D_95_64_ADDR,\n P_REG_FI_D_63_32_ADDR,\n P_REG_FI_D_31_00_ADDR,\n P_REG_UE_FFA_63_32_ADDR,\n P_REG_UE_FFA_31_00_ADDR,\n P_REG_UE_FFE_ADDR,\n P_REG_UE_FFD_127_96_ADDR,\n P_REG_UE_FFD_95_64_ADDR,\n P_REG_UE_FFD_63_32_ADDR,\n P_REG_UE_FFD_31_00_ADDR,\n P_REG_CE_FFA_63_32_ADDR,\n P_REG_CE_FFA_31_00_ADDR,\n P_REG_CE_FFE_ADDR,\n P_REG_CE_FFD_127_96_ADDR,\n P_REG_CE_FFD_95_64_ADDR,\n P_REG_CE_FFD_63_32_ADDR,\n P_REG_CE_FFD_31_00_ADDR,\n P_REG_CE_CNT_ADDR,\n P_REG_ECC_ON_OFF_ADDR,\n P_REG_ECC_EN_IRQ_ADDR,\n P_REG_ECC_STATUS_ADDR,\n P_REG_DUMMY_ADDR\n};\n\nlocalparam P_REG_WRAC_ARRAY = {\n P_REG_FI_ECC_WRAC,\n P_REG_FI_D_127_96_WRAC,\n P_REG_FI_D_95_64_WRAC,\n P_REG_FI_D_63_32_WRAC,\n P_REG_FI_D_31_00_WRAC,\n P_REG_UE_FFA_63_32_WRAC,\n P_REG_UE_FFA_31_00_WRAC,\n P_REG_UE_FFE_WRAC,\n P_REG_UE_FFD_127_96_WRAC,\n P_REG_UE_FFD_95_64_WRAC,\n P_REG_UE_FFD_63_32_WRAC,\n P_REG_UE_FFD_31_00_WRAC,\n P_REG_CE_FFA_63_32_WRAC,\n P_REG_CE_FFA_31_00_WRAC,\n P_REG_CE_FFE_WRAC,\n P_REG_CE_FFD_127_96_WRAC,\n P_REG_CE_FFD_95_64_WRAC,\n P_REG_CE_FFD_63_32_WRAC,\n P_REG_CE_FFD_31_00_WRAC,\n P_REG_CE_CNT_WRAC,\n P_REG_ECC_ON_OFF_WRAC,\n P_REG_ECC_EN_IRQ_WRAC,\n P_REG_ECC_STATUS_WRAC,\n P_REG_DUMMY_WRAC\n};\n\nlocalparam P_REG_WIDTH_ARRAY = {\n mask_width(P_REG_FI_ECC_MASK),\n mask_width(P_REG_FI_D_127_96_MASK),\n mask_width(P_REG_FI_D_95_64_MASK),\n mask_width(P_REG_FI_D_63_32_MASK),\n mask_width(P_REG_FI_D_31_00_MASK),\n mask_width(P_REG_UE_FFA_63_32_MASK),\n mask_width(P_REG_UE_FFA_31_00_MASK),\n mask_width(P_REG_UE_FFE_MASK),\n mask_width(P_REG_UE_FFD_127_96_MASK),\n mask_width(P_REG_UE_FFD_95_64_MASK),\n mask_width(P_REG_UE_FFD_63_32_MASK),\n mask_width(P_REG_UE_FFD_31_00_MASK),\n mask_width(P_REG_CE_FFA_63_32_MASK),\n mask_width(P_REG_CE_FFA_31_00_MASK),\n mask_width(P_REG_CE_FFE_MASK),\n mask_width(P_REG_CE_FFD_127_96_MASK),\n mask_width(P_REG_CE_FFD_95_64_MASK),\n mask_width(P_REG_CE_FFD_63_32_MASK),\n mask_width(P_REG_CE_FFD_31_00_MASK),\n mask_width(P_REG_CE_CNT_MASK),\n mask_width(P_REG_ECC_ON_OFF_MASK),\n mask_width(P_REG_ECC_EN_IRQ_MASK),\n mask_width(P_REG_ECC_STATUS_MASK),\n mask_width(P_REG_DUMMY_MASK)\n};\n\nlocalparam P_REG_MASK_ARRAY = {\n P_REG_FI_ECC_MASK,\n P_REG_FI_D_127_96_MASK,\n P_REG_FI_D_95_64_MASK,\n P_REG_FI_D_63_32_MASK,\n P_REG_FI_D_31_00_MASK,\n P_REG_UE_FFA_63_32_MASK,\n P_REG_UE_FFA_31_00_MASK,\n P_REG_UE_FFE_MASK,\n P_REG_UE_FFD_127_96_MASK,\n P_REG_UE_FFD_95_64_MASK,\n P_REG_UE_FFD_63_32_MASK,\n P_REG_UE_FFD_31_00_MASK,\n P_REG_CE_FFA_63_32_MASK,\n P_REG_CE_FFA_31_00_MASK,\n P_REG_CE_FFE_MASK,\n P_REG_CE_FFD_127_96_MASK,\n P_REG_CE_FFD_95_64_MASK,\n P_REG_CE_FFD_63_32_MASK,\n P_REG_CE_FFD_31_00_MASK,\n P_REG_CE_CNT_MASK,\n P_REG_ECC_ON_OFF_MASK,\n P_REG_ECC_EN_IRQ_MASK,\n P_REG_ECC_STATUS_MASK,\n P_REG_DUMMY_MASK\n};\n\n// END Auto-generated Register Mapping\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\nwire [ P_NUM_REG_WIDTH-1:0 ] reg_data_sel;\nwire reg_data_write;\nwire [ C_S_AXI_CTRL_DATA_WIDTH-1:0 ] reg_data_in;\nwire [ C_S_AXI_CTRL_DATA_WIDTH*P_NUM_REG-1:0 ] reg_data_out;\nwire reset;\nwire arhandshake;\nwire rhandshake;\nwire awhandshake;\nwire bhandshake;\nreg wr_pending;\nreg rd_pending;\nreg arready_r;\nreg awready_r;\nreg [ C_S_AXI_ADDR_WIDTH-1:0 ] addr;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n///////////////////////////////////////////////////////////////////////////////\nassign reset = ~aresetn;\nassign arhandshake = s_axi_arvalid & s_axi_arready;\nassign awhandshake = s_axi_awvalid & s_axi_awready;\nassign rhandshake = s_axi_rvalid & s_axi_rready;\nassign bhandshake = s_axi_bvalid & s_axi_bready;\nassign s_axi_awready = awready_r;\nassign s_axi_arready = arready_r;\n\nalways @(posedge aclk) begin \n if (reset) begin\n wr_pending <= 1'b0;\n end\n else begin \n wr_pending <= (awhandshake | wr_pending) & ~bhandshake;\n end\nend\n\nalways @(posedge aclk) begin \n if (reset) begin\n rd_pending <= 1'b0;\n end\n else begin \n rd_pending <= (arhandshake | rd_pending) & ~rhandshake;\n end\nend\n\nalways @(posedge aclk) begin \n if (reset | ~init_complete) begin\n awready_r <= 1'b0;\n end\n else begin \n awready_r <= s_axi_awvalid & ~rd_pending & ~wr_pending & ~awready_r;\n end\nend\n\nalways @(posedge aclk) begin \n if (reset | ~init_complete) begin\n arready_r <= 1'b0;\n end\n else begin \n arready_r <= s_axi_arvalid & ~rd_pending & ~wr_pending & ~s_axi_awvalid & ~arready_r;\n end\nend\n\nalways @(posedge aclk) begin \n if (awhandshake) begin \n addr <= s_axi_awaddr; \n end else if (arhandshake) begin \n addr <= s_axi_araddr;\n end\nend\n\n// Instantiate AXI4-Lite write channel module\nmig_7series_v4_0_axi_ctrl_write #\n( \n .C_ADDR_WIDTH ( C_S_AXI_CTRL_ADDR_WIDTH ) ,\n .C_DATA_WIDTH ( C_S_AXI_CTRL_DATA_WIDTH ) ,\n .C_NUM_REG ( P_NUM_REG ) ,\n .C_NUM_REG_WIDTH ( P_NUM_REG_WIDTH ) ,\n .C_REG_ADDR_ARRAY ( P_REG_ADDR_ARRAY ) ,\n .C_REG_WRAC_ARRAY ( P_REG_WRAC_ARRAY )\n)\naxi_ctrl_write_0\n(\n .clk ( aclk ) ,\n .reset ( reset ) ,\n .awvalid ( s_axi_awvalid ) ,\n .awready ( s_axi_awready ) ,\n .awaddr ( addr ) ,\n .wvalid ( s_axi_wvalid ) ,\n .wready ( s_axi_wready ) ,\n .wdata ( s_axi_wdata ) ,\n .bvalid ( s_axi_bvalid ) ,\n .bready ( s_axi_bready ) ,\n .bresp ( s_axi_bresp ) ,\n .reg_data_sel ( reg_data_sel ) ,\n .reg_data_write ( reg_data_write ) ,\n .reg_data ( reg_data_in ) \n);\n \n// Instantiate AXI4-Lite write channel module\nmig_7series_v4_0_axi_ctrl_read #\n( \n .C_ADDR_WIDTH ( C_S_AXI_CTRL_ADDR_WIDTH ) ,\n .C_DATA_WIDTH ( C_S_AXI_CTRL_DATA_WIDTH ) ,\n .C_NUM_REG ( P_NUM_REG ) ,\n .C_NUM_REG_WIDTH ( P_NUM_REG_WIDTH ) ,\n .C_REG_ADDR_ARRAY ( P_REG_ADDR_ARRAY ) ,\n .C_REG_RDAC_ARRAY ( P_REG_RDAC_ARRAY ) \n)\naxi_ctrl_read_0\n(\n .clk ( aclk ) ,\n .reset ( reset ) ,\n .araddr ( addr ) ,\n .rvalid ( s_axi_rvalid ) ,\n .rready ( s_axi_rready ) ,\n .rresp ( s_axi_rresp ) ,\n .rdata ( s_axi_rdata ) ,\n .pending ( rd_pending ) ,\n .reg_bank_array ( reg_data_out ) \n);\n \nmig_7series_v4_0_axi_ctrl_reg_bank #\n(\n .C_ADDR_WIDTH ( C_S_AXI_CTRL_ADDR_WIDTH ) ,\n .C_DATA_WIDTH ( C_S_AXI_CTRL_DATA_WIDTH ) ,\n .C_DQ_WIDTH ( C_DQ_WIDTH ) ,\n .C_ECC_CE_COUNTER_WIDTH ( C_ECC_CE_COUNTER_WIDTH ) ,\n .C_ECC_ONOFF_RESET_VALUE ( C_ECC_ONOFF_RESET_VALUE ) ,\n .C_ECC_TEST ( C_ECC_TEST ) ,\n .C_ECC_WIDTH ( C_ECC_WIDTH ) ,\n .C_MC_ERR_ADDR_WIDTH ( C_MC_ERR_ADDR_WIDTH ) ,\n .C_MEM_ADDR_ORDER ( C_MEM_ADDR_ORDER ) ,\n .C_BANK_WIDTH ( C_BANK_WIDTH ) ,\n .C_ROW_WIDTH ( C_ROW_WIDTH ) ,\n .C_COL_WIDTH ( C_COL_WIDTH ) ,\n .C_NCK_PER_CLK ( C_NCK_PER_CLK ) ,\n .C_NUM_REG ( P_NUM_REG ) ,\n .C_NUM_REG_WIDTH ( P_NUM_REG_WIDTH ) ,\n .C_S_AXI_ADDR_WIDTH ( C_S_AXI_ADDR_WIDTH ) ,\n .C_S_AXI_BASEADDR ( C_S_AXI_BASEADDR ) ,\n // Register arrays\n .C_REG_RDAC_ARRAY ( P_REG_RDAC_ARRAY ) ,\n .C_REG_WRAC_ARRAY ( P_REG_WRAC_ARRAY ) ,\n .C_REG_INIT_ARRAY ( P_REG_INIT_ARRAY ) ,\n .C_REG_MASK_ARRAY ( P_REG_MASK_ARRAY ) ,\n .C_REG_ADDR_ARRAY ( P_REG_ADDR_ARRAY ) ,\n .C_REG_WIDTH_ARRAY ( P_REG_WIDTH_ARRAY ) ,\n // Register Indices\n .C_REG_FI_ECC_INDX ( P_REG_FI_ECC_INDX ) ,\n .C_REG_FI_D_127_96_INDX ( P_REG_FI_D_127_96_INDX ) ,\n .C_REG_FI_D_95_64_INDX ( P_REG_FI_D_95_64_INDX ) ,\n .C_REG_FI_D_63_32_INDX ( P_REG_FI_D_63_32_INDX ) ,\n .C_REG_FI_D_31_00_INDX ( P_REG_FI_D_31_00_INDX ) ,\n .C_REG_UE_FFA_63_32_INDX ( P_REG_UE_FFA_63_32_INDX ) ,\n .C_REG_UE_FFA_31_00_INDX ( P_REG_UE_FFA_31_00_INDX ) ,\n .C_REG_UE_FFE_INDX ( P_REG_UE_FFE_INDX ) ,\n .C_REG_UE_FFD_127_96_INDX ( P_REG_UE_FFD_127_96_INDX ) ,\n .C_REG_UE_FFD_95_64_INDX ( P_REG_UE_FFD_95_64_INDX ) ,\n .C_REG_UE_FFD_63_32_INDX ( P_REG_UE_FFD_63_32_INDX ) ,\n .C_REG_UE_FFD_31_00_INDX ( P_REG_UE_FFD_31_00_INDX ) ,\n .C_REG_CE_FFA_63_32_INDX ( P_REG_CE_FFA_63_32_INDX ) ,\n .C_REG_CE_FFA_31_00_INDX ( P_REG_CE_FFA_31_00_INDX ) ,\n .C_REG_CE_FFE_INDX ( P_REG_CE_FFE_INDX ) ,\n .C_REG_CE_FFD_127_96_INDX ( P_REG_CE_FFD_127_96_INDX ) ,\n .C_REG_CE_FFD_95_64_INDX ( P_REG_CE_FFD_95_64_INDX ) ,\n .C_REG_CE_FFD_63_32_INDX ( P_REG_CE_FFD_63_32_INDX ) ,\n .C_REG_CE_FFD_31_00_INDX ( P_REG_CE_FFD_31_00_INDX ) ,\n .C_REG_CE_CNT_INDX ( P_REG_CE_CNT_INDX ) ,\n .C_REG_ECC_ON_OFF_INDX ( P_REG_ECC_ON_OFF_INDX ) ,\n .C_REG_ECC_EN_IRQ_INDX ( P_REG_ECC_EN_IRQ_INDX ) ,\n .C_REG_ECC_STATUS_INDX ( P_REG_ECC_STATUS_INDX ) ,\n .C_REG_DUMMY_INDX ( P_REG_DUMMY_INDX ) \n \n)\naxi_ctrl_reg_bank_0\n(\n .clk ( aclk ) ,\n .reset ( reset ) ,\n .reg_data_sel ( reg_data_sel ) ,\n .reg_data_write ( reg_data_write ) ,\n .reg_data_in ( reg_data_in ) ,\n .reg_data_out ( reg_data_out ) ,\n .interrupt ( interrupt ) ,\n .ecc_single ( ecc_single ) ,\n .ecc_multiple ( ecc_multiple ) ,\n .ecc_err_addr ( ecc_err_addr ) ,\n .app_correct_en ( app_correct_en ) ,\n .dfi_rddata ( dfi_rddata ) ,\n .fi_xor_we ( fi_xor_we ) ,\n .fi_xor_wrdata ( fi_xor_wrdata ) \n);\n\nendmodule\n\n`default_nettype wire\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_ctrl_write.v", "content": "// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. \n// -- \n// -- This file contains confidential and proprietary information \n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property \n// -- laws. \n// -- \n// -- DISCLAIMER \n// -- This disclaimer is not a license and does not grant any \n// -- rights to the materials distributed herewith. Except as \n// -- otherwise provided in a valid license issued to you by \n// -- Xilinx, and to the maximum extent permitted by applicable \n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND \n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES \n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING \n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- \n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and \n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of \n// -- liability) for any loss or damage of any kind or nature \n// -- related to, arising under or in connection with these \n// -- materials, including for any direct, or any indirect, \n// -- special, incidental, or consequential loss or damage \n// -- (including loss of data, profits, goodwill, or any type of \n// -- loss or damage suffered as a result of any action brought \n// -- by a third party) even if such damage or loss was \n// -- reasonably foreseeable or Xilinx had been advised of the \n// -- possibility of the same. \n// -- \n// -- CRITICAL APPLICATIONS \n// -- Xilinx products are not designed or intended to be fail- \n// -- safe, or for use in any application requiring fail-safe \n// -- performance, such as life-support or safety devices or \n// -- systems, Class III medical devices, nuclear facilities, \n// -- applications related to the deployment of airbags, or any \n// -- other applications that could lead to death, personal \n// -- injury, or severe property or environmental damage \n// -- (individually and collectively, \"Critical \n// -- Applications\"). Customer assumes the sole risk and \n// -- liability of any use of Xilinx products in Critical \n// -- Applications, subject only to applicable laws and \n// -- regulations governing limitations on product liability. \n// -- \n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS \n// -- PART OF THIS FILE AT ALL TIMES. \n// -- \n///////////////////////////////////////////////////////////////////////////////\n//\n// File name: axi_ctrl_write.v\n//\n// Description: \n//\n// Specifications:\n//\n// Structure:\n// axi_ctrl_top\n// axi_ctrl_write\n// axi_ctrl_addr_decode\n// axi_ctrl_read\n// axi_ctrl_addr_decode\n// axi_ctrl_reg_bank\n// axi_ctrl_reg\n//\n///////////////////////////////////////////////////////////////////////////////\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule mig_7series_v4_0_axi_ctrl_write #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n // Width of AXI-4-Lite address bus\n parameter integer C_ADDR_WIDTH = 32,\n // Width of AXI-4-Lite data buses\n parameter integer C_DATA_WIDTH = 32,\n // Number of Registers\n parameter integer C_NUM_REG = 5,\n parameter integer C_NUM_REG_WIDTH = 3,\n // Number of Registers\n parameter C_REG_ADDR_ARRAY = 160'h0000_f00C_0000_f008_0000_f004_0000_f000_FFFF_FFFF,\n parameter C_REG_WRAC_ARRAY = 5'b11111\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations \n///////////////////////////////////////////////////////////////////////////////\n // AXI4-Lite Slave Interface\n // Slave Interface System Signals \n input wire clk , \n input wire reset , \n // Slave Interface Read Address Ports\n input wire awvalid , \n input wire awready , \n input wire [C_ADDR_WIDTH-1:0] awaddr , \n // Slave Interface Read Data Ports\n input wire wvalid , \n output wire wready , \n input wire [C_DATA_WIDTH-1:0] wdata , \n\n output wire bvalid , \n input wire bready , \n output wire [1:0] bresp , \n\n // Internal Signals\n output wire [C_NUM_REG_WIDTH-1:0] reg_data_sel ,\n output wire reg_data_write ,\n output wire [C_DATA_WIDTH-1:0] reg_data \n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\nwire awhandshake;\nwire whandshake;\nreg whandshake_d1;\nwire bhandshake;\nwire [C_NUM_REG_WIDTH-1:0] reg_decode_num;\nreg awready_i;\nreg wready_i;\nreg bvalid_i;\nreg [C_DATA_WIDTH-1:0] data;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n///////////////////////////////////////////////////////////////////////////////\n\n// Handshake signals\nassign awhandshake = awvalid & awready;\nassign whandshake = wvalid & wready;\nassign bhandshake = bvalid & bready;\n\nmig_7series_v4_0_axi_ctrl_addr_decode #\n(\n .C_ADDR_WIDTH ( C_ADDR_WIDTH ) ,\n .C_NUM_REG ( C_NUM_REG ) ,\n .C_NUM_REG_WIDTH ( C_NUM_REG_WIDTH ) ,\n .C_REG_ADDR_ARRAY ( C_REG_ADDR_ARRAY ) ,\n .C_REG_RDWR_ARRAY ( C_REG_WRAC_ARRAY ) \n)\naxi_ctrl_addr_decode_0\n(\n .axaddr ( awaddr ) ,\n .reg_decode_num ( reg_decode_num ) \n);\n\n// wchannel only accepts data after aw handshake\nassign wready = wready_i;\n\nalways @(posedge clk) begin\n if (reset) begin \n wready_i <= 1'b0;\n end\n else begin\n wready_i <= (awhandshake | wready_i) & ~whandshake;\n end\nend\n\n// Data is registered but not latched (like awaddr) since it used a cycle later\nalways @(posedge clk) begin\n data <= wdata;\nend\n\n// bresponse is sent after successful w handshake\nassign bvalid = bvalid_i;\nassign bresp = 2'b0; // Okay\n\nalways @(posedge clk) begin\n if (reset) begin \n bvalid_i <= 1'b0;\n end\n else begin\n bvalid_i <= (whandshake | bvalid_i) & ~bhandshake;\n end\nend\n\n// Assign internal signals \nassign reg_data = data;\nassign reg_data_write = whandshake_d1;\nassign reg_data_sel = reg_decode_num;\n\nalways @(posedge clk) begin\n whandshake_d1 <= whandshake;\nend\n\nendmodule\n\n`default_nettype wire\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc.v", "content": "// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. \n// -- \n// -- This file contains confidential and proprietary information \n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property \n// -- laws. \n// -- \n// -- DISCLAIMER \n// -- This disclaimer is not a license and does not grant any \n// -- rights to the materials distributed herewith. Except as \n// -- otherwise provided in a valid license issued to you by \n// -- Xilinx, and to the maximum extent permitted by applicable \n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND \n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES \n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING \n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- \n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and \n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of \n// -- liability) for any loss or damage of any kind or nature \n// -- related to, arising under or in connection with these \n// -- materials, including for any direct, or any indirect, \n// -- special, incidental, or consequential loss or damage \n// -- (including loss of data, profits, goodwill, or any type of \n// -- loss or damage suffered as a result of any action brought \n// -- by a third party) even if such damage or loss was \n// -- reasonably foreseeable or Xilinx had been advised of the \n// -- possibility of the same. \n// -- \n// -- CRITICAL APPLICATIONS \n// -- Xilinx products are not designed or intended to be fail- \n// -- safe, or for use in any application requiring fail-safe \n// -- performance, such as life-support or safety devices or \n// -- systems, Class III medical devices, nuclear facilities, \n// -- applications related to the deployment of airbags, or any \n// -- other applications that could lead to death, personal \n// -- injury, or severe property or environmental damage \n// -- (individually and collectively, \"Critical \n// -- Applications\"). Customer assumes the sole risk and \n// -- liability of any use of Xilinx products in Critical \n// -- Applications, subject only to applicable laws and \n// -- regulations governing limitations on product liability. \n// -- \n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS \n// -- PART OF THIS FILE AT ALL TIMES. \n// -- \n///////////////////////////////////////////////////////////////////////////////\n//\n// File name: axi_mc.v\n//\n// Description: \n// To handle AXI4 transactions to external memory on Virtex-6 architectures \n// requires a bridge to convert the AXI4 transactions to the memory\n// controller(MC) user interface. The MC user interface has bidirectional \n// data path and supports data width of 256/128/64/32 bits. \n// The bridge is designed to allow AXI4 IP masters to communicate with \n// the MC user interface. \n//\n//\n// Specifications:\n// AXI4 Slave Side:\n// Configurable data width of 32, 64, 128, 256\n// Read acceptance depth is:\n// Write acceptance depth is:\n//\n// Structure:\n// axi_mc\n// axi_register_slice_d1\n// USE_UPSIZER\n// upsizer_d2\n// axi_register_slice_d3\n// WRITE_BUNDLE\n// axi_mc_aw_channel_0\n// axi_mc_cmd_translator_0\n// rd_cmd_fsm_0\n// axi_mc_w_channel_0\n// axi_mc_b_channel_0\n// READ_BUNDLE\n// axi_mc_ar_channel_0\n// axi_mc_cmd_translator_0\n// rd_cmd_fsm_0\n// axi_mc_r_channel_0\n// USE_CMD_ARBITER\n// axi_mc_cmd_arbiter_0\n//\n///////////////////////////////////////////////////////////////////////////////\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule mig_7series_v4_0_axi_mc #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n // FPGA Family. Current version: virtex6.\n parameter C_FAMILY = \"virtex6\", \n // Width of all master and slave ID signals.\n // Range: >= 1.\n parameter integer C_S_AXI_ID_WIDTH = 4, \n // Width of S_AXI_AWADDR, S_AXI_ARADDR, M_AXI_AWADDR and \n // M_AXI_ARADDR for all SI/MI slots.\n // Range: 32.\n parameter integer C_S_AXI_ADDR_WIDTH = 30, \n // Width of WDATA and RDATA on SI slot.\n // Must be <= C_MC_DATA_WIDTH\n // Range: 32, 64, 128, 256.\n parameter integer C_S_AXI_DATA_WIDTH = 32, \n // Memory controller address width, range 28-32\n parameter integer C_MC_ADDR_WIDTH = 30, \n // Width of wr_data and rd_data.\n // Range: 32, 64, 128, 256.\n parameter integer C_MC_DATA_WIDTH = 32,\n // Memory controller burst mode,\n // values \"8\", \"4\" & \"OTF\"\n parameter C_MC_BURST_MODE = \"8\",\n // Number of memory clocks per fabric clock\n // = 2 for DDR2 or low frequency designs\n // = 4 for DDR3 or high frequency designs \n parameter C_MC_nCK_PER_CLK = 2,\n // Indicates whether to instatiate upsizer\n // Range: 0, 1\n parameter integer C_S_AXI_SUPPORTS_NARROW_BURST = 1, \n // C_S_AXI_REG_EN0[00] = Reserved\n // C_S_AXI_REG_EN0[04] = AW CHANNEL REGISTER SLICE \n // C_S_AXI_REG_EN0[05] = W CHANNEL REGISTER SLICE\n // C_S_AXI_REG_EN0[06] = B CHANNEL REGISTER SLICE\n // C_S_AXI_REG_EN0[07] = R CHANNEL REGISTER SLICE\n // C_S_AXI_REG_EN0[08] = AW CHANNEL UPSIZER REGISTER SLICE \n // C_S_AXI_REG_EN0[09] = W CHANNEL UPSIZER REGISTER SLICE\n // C_S_AXI_REG_EN0[10] = AR CHANNEL UPSIZER REGISTER SLICE\n // C_S_AXI_REG_EN0[11] = R CHANNEL UPSIZER REGISTER SLICE\n parameter C_S_AXI_REG_EN0 = 20'h00000, \n // Instatiates register slices after the upsizer.\n // The type of register is specified for each channel\n // in a vector. 4 bits per channel are used. \n // C_S_AXI_REG_EN1[03:00] = AW CHANNEL REGISTER SLICE\n // C_S_AXI_REG_EN1[07:04] = W CHANNEL REGISTER SLICE\n // C_S_AXI_REG_EN1[11:08] = B CHANNEL REGISTER SLICE\n // C_S_AXI_REG_EN1[15:12] = AR CHANNEL REGISTER SLICE\n // C_S_AXI_REG_EN1[20:16] = R CHANNEL REGISTER SLICE\n // Possible values for each channel are:\n //\n // 0 => BYPASS = The channel is just wired through the\n // module.\n // 1 => FWD = The master VALID and payload signals\n // are registrated. \n // 2 => REV = The slave ready signal is registrated\n // 3 => FWD_REV = Both FWD and REV\n // 4 => SLAVE_FWD = All slave side signals and master \n // VALID and payload are registrated.\n // 5 => SLAVE_RDY = All slave side signals and master \n // READY are registrated.\n // 6 => INPUTS = Slave and Master side inputs are \n // registrated.\n // 7 => ADDRESS = Optimized for address channel\n // A A\n // RRBWW \n parameter C_S_AXI_REG_EN1 = 20'h00000,\n parameter C_RD_WR_ARB_ALGORITHM = \"RD_PRI_REG\",\n // Indicates the Arbitration\n // Allowed values - \"TDM\", \"ROUND_ROBIN\",\n // \"RD_PRI_REG\", \"RD_PRI_REG_STARVE_LIMIT\"\n parameter C_ECC = \"OFF\"\n // Output RMW if ECC is on.\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations \n///////////////////////////////////////////////////////////////////////////////\n // AXI Slave Interface\n // Slave Interface System Signals \n input wire aclk , \n input wire aresetn , \n // Slave Interface Write Address Ports\n input wire [C_S_AXI_ID_WIDTH-1:0] s_axi_awid , \n input wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr , \n input wire [7:0] s_axi_awlen , \n input wire [2:0] s_axi_awsize , \n input wire [1:0] s_axi_awburst , \n input wire [0:0] s_axi_awlock , \n input wire [3:0] s_axi_awcache , \n input wire [2:0] s_axi_awprot , \n input wire [3:0] s_axi_awqos , \n input wire s_axi_awvalid , \n output wire s_axi_awready , \n // Slave Interface Write Data Ports\n input wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata , \n input wire [C_S_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb , \n input wire s_axi_wlast , \n input wire s_axi_wvalid , \n output wire s_axi_wready , \n // Slave Interface Write Response Ports\n output wire [C_S_AXI_ID_WIDTH-1:0] s_axi_bid , \n output wire [1:0] s_axi_bresp , \n output wire s_axi_bvalid , \n input wire s_axi_bready , \n // Slave Interface Read Address Ports\n input wire [C_S_AXI_ID_WIDTH-1:0] s_axi_arid , \n input wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr , \n input wire [7:0] s_axi_arlen , \n input wire [2:0] s_axi_arsize , \n input wire [1:0] s_axi_arburst , \n input wire [0:0] s_axi_arlock , \n input wire [3:0] s_axi_arcache , \n input wire [2:0] s_axi_arprot , \n input wire [3:0] s_axi_arqos , \n input wire s_axi_arvalid , \n output wire s_axi_arready , \n // Slave Interface Read Data Ports\n output wire [C_S_AXI_ID_WIDTH-1:0] s_axi_rid , \n output wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata , \n output wire [1:0] s_axi_rresp , \n output wire s_axi_rlast , \n output wire s_axi_rvalid , \n input wire s_axi_rready , \n\n // MC Master Interface\n //CMD PORT\n output wire mc_app_en , \n output wire [2:0] mc_app_cmd , \n output wire mc_app_sz , \n output wire [C_MC_ADDR_WIDTH-1:0] mc_app_addr , \n output wire mc_app_hi_pri , \n input wire mc_app_rdy ,\n input wire mc_init_complete ,\n \n //DATA PORT\n output wire mc_app_wdf_wren , \n output wire [C_MC_DATA_WIDTH/8-1:0] mc_app_wdf_mask , \n output wire [C_MC_DATA_WIDTH-1:0] mc_app_wdf_data ,\n output wire mc_app_wdf_end , \n input wire mc_app_wdf_rdy , \n \n input wire mc_app_rd_valid , \n input wire [C_MC_DATA_WIDTH-1:0] mc_app_rd_data ,\n input wire mc_app_rd_end ,\n input wire [2*C_MC_nCK_PER_CLK-1:0] mc_app_ecc_multiple_err\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam integer P_AXSIZE = (C_MC_DATA_WIDTH == 32) ? 3'd2 :\n (C_MC_DATA_WIDTH == 64) ? 3'd3 : \n (C_MC_DATA_WIDTH == 128)? 3'd4 :\n (C_MC_DATA_WIDTH == 256)? 3'd5 :\n (C_MC_DATA_WIDTH == 512)? 3'd6 : 3'd7;\n \n// C_D?_REG_CONFIG_*:\n\n// 0 => BYPASS = The channel is just wired through the module.\n// 1 => FWD = The master VALID and payload signals are registrated. \n// 2 => REV = The slave ready signal is registrated\n// 3 => FWD_REV = Both FWD and REV\n// 4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.\n// 5 => SLAVE_RDY = All slave side signals and master READY are registrated.\n// 6 => INPUTS = Slave and Master side inputs are registrated.\nlocalparam integer P_D1_REG_CONFIG_AW = 0;\nlocalparam integer P_D1_REG_CONFIG_W = 0;\nlocalparam integer P_D1_REG_CONFIG_B = 0;\nlocalparam integer P_D1_REG_CONFIG_AR = 0;\nlocalparam integer P_D1_REG_CONFIG_R = 0;\n\n// Upsizer\nlocalparam integer P_USE_UPSIZER = ( C_S_AXI_DATA_WIDTH < C_MC_DATA_WIDTH) ? 1'b1\n : C_S_AXI_SUPPORTS_NARROW_BURST;\n\nlocalparam integer P_D2_REG_CONFIG_AW = P_USE_UPSIZER ? 1 : C_S_AXI_REG_EN0[8];\nlocalparam integer P_D2_REG_CONFIG_W = C_S_AXI_REG_EN0[9];\nlocalparam integer P_D2_REG_CONFIG_AR = P_USE_UPSIZER ? 1 : C_S_AXI_REG_EN0[10];\nlocalparam integer P_D2_REG_CONFIG_R = C_S_AXI_REG_EN0[11];\n\n\n// localparam integer P_D3_REG_CONFIG_AW = (C_S_AXI_DATA_WIDTH < C_MC_DATA_WIDTH)? \n// (C_S_AXI_REG_EN0[4] ? 1 : C_S_AXI_REG_EN1[ 0 +: 4]) : 1;\n// localparam integer P_D3_REG_CONFIG_W = C_S_AXI_REG_EN0[5] ? 2 : C_S_AXI_REG_EN1[ 4 +: 4];\n// localparam integer P_D3_REG_CONFIG_B = C_S_AXI_REG_EN0[6] ? 7 : C_S_AXI_REG_EN1[ 8 +: 4];\n// // AR channel must always have a register slice.\n// localparam integer P_D3_REG_CONFIG_AR = (C_S_AXI_DATA_WIDTH < C_MC_DATA_WIDTH)? 0 : 1;\n// localparam integer P_D3_REG_CONFIG_R = C_S_AXI_REG_EN0[7] ? 6 : C_S_AXI_REG_EN1[16 +: 4];\n\nlocalparam integer P_D3_REG_CONFIG_AW = 0;\nlocalparam integer P_D3_REG_CONFIG_W = 0;\nlocalparam integer P_D3_REG_CONFIG_B = 0;\nlocalparam integer P_D3_REG_CONFIG_AR = 0;\nlocalparam integer P_D3_REG_CONFIG_R = 0;\n\n\nlocalparam integer P_UPSIZER_PACKING_LEVEL = 2;\nlocalparam integer P_SUPPORTS_USER_SIGNALS = 0;\n// Set this parameter to 1 if data can be returned out of order\nlocalparam integer P_SINGLE_THREAD = 0;\n \n\n// BURST LENGTH\n// In 4:1 mode the only burst mode that is supported is BL8.\n// The BL8 in 4:1 mode will be treated as BL4 by the shim.\n// In 2:1 mode both the burst modes BL4 & BL8 are supported. \n\nlocalparam integer C_MC_BURST_LEN = (C_MC_nCK_PER_CLK == 4) ? 1:\n (C_MC_BURST_MODE == \"4\") ? 1 : 2;\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\n// AXI Slave signals from Reg Slice, Upsizer, at MC data width, internal signals\n\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n///////////////////////////////////////////////////////////////////////////////\n\n// First reg slice slave side output/inputs\nwire [C_S_AXI_ID_WIDTH-1:0] awid_d1 ;\nwire [C_S_AXI_ADDR_WIDTH-1:0] awaddr_d1 ;\nwire [7:0] awlen_d1 ;\nwire [2:0] awsize_d1 ;\nwire [1:0] awburst_d1 ;\nwire [1:0] awlock_d1 ;\nwire [3:0] awcache_d1 ;\nwire [2:0] awprot_d1 ;\nwire [3:0] awqos_d1 ;\nwire awvalid_d1 ;\nwire awready_d1 ;\nwire [C_S_AXI_DATA_WIDTH-1:0] wdata_d1 ;\nwire [C_S_AXI_DATA_WIDTH/8-1:0] wstrb_d1 ;\nwire wlast_d1 ;\nwire wvalid_d1 ;\nwire wready_d1 ;\nwire [C_S_AXI_ID_WIDTH-1:0] bid_d1 ;\nwire [1:0] bresp_d1 ;\nwire bvalid_d1 ;\nwire bready_d1 ;\nwire [C_S_AXI_ID_WIDTH-1:0] arid_d1 ;\nwire [C_S_AXI_ADDR_WIDTH-1:0] araddr_d1 ;\nwire [7:0] arlen_d1 ;\nwire [2:0] arsize_d1 ;\nwire [1:0] arburst_d1 ;\nwire [1:0] arlock_d1 ;\nwire [3:0] arcache_d1 ;\nwire [2:0] arprot_d1 ;\nwire [3:0] arqos_d1 ;\nwire arvalid_d1 ;\nwire arready_d1 ;\nwire [C_S_AXI_ID_WIDTH-1:0] rid_d1 ;\nwire [C_S_AXI_DATA_WIDTH-1:0] rdata_d1 ;\nwire [1:0] rresp_d1 ;\nwire rlast_d1 ;\nwire rvalid_d1 ;\nwire rready_d1 ;\n// Upsizer slave side outputs/inputs\nwire [C_S_AXI_ID_WIDTH-1:0] awid_d2 ;\nwire [C_S_AXI_ADDR_WIDTH-1:0] awaddr_d2 ;\nwire [7:0] awlen_d2 ;\nwire [2:0] awsize_d2 ;\nwire [1:0] awburst_d2 ;\nwire [1:0] awlock_d2 ;\nwire [3:0] awcache_d2 ;\nwire [2:0] awprot_d2 ;\nwire [3:0] awqos_d2 ;\nwire awvalid_d2 ;\nwire awready_d2 ;\nwire [C_MC_DATA_WIDTH-1:0] wdata_d2 ;\nwire [C_MC_DATA_WIDTH/8-1:0] wstrb_d2 ;\nwire wlast_d2 ;\nwire wvalid_d2 ;\nwire wready_d2 ;\nwire [C_S_AXI_ID_WIDTH-1:0] bid_d2 ;\nwire [1:0] bresp_d2 ;\nwire bvalid_d2 ;\nwire bready_d2 ;\nwire [C_S_AXI_ID_WIDTH-1:0] arid_d2 ;\nwire [C_S_AXI_ADDR_WIDTH-1:0] araddr_d2 ;\nwire [7:0] arlen_d2 ;\nwire [2:0] arsize_d2 ;\nwire [1:0] arburst_d2 ;\nwire [1:0] arlock_d2 ;\nwire [3:0] arcache_d2 ;\nwire [2:0] arprot_d2 ;\nwire [3:0] arqos_d2 ;\nwire arvalid_d2 ;\nwire arready_d2 ;\nwire [C_S_AXI_ID_WIDTH-1:0] rid_d2 ;\nwire [C_MC_DATA_WIDTH-1:0] rdata_d2 ;\nwire [1:0] rresp_d2 ;\nwire rlast_d2 ;\nwire rvalid_d2 ;\nwire rready_d2 ;\n// Registe Slice 2 slave side outputs/inputs\nwire [C_S_AXI_ID_WIDTH-1:0] awid_d3 ;\nwire [C_S_AXI_ADDR_WIDTH-1:0] awaddr_d3 ;\nwire [7:0] awlen_d3 ;\n// AxSIZE hardcoded with static value\n// wire [2:0] awsize_d3 ;\nwire [1:0] awburst_d3 ;\nwire [1:0] awlock_d3 ;\nwire [3:0] awcache_d3 ;\nwire [2:0] awprot_d3 ;\nwire [3:0] awqos_d3 ;\nwire awvalid_d3 ;\nwire awready_d3 ;\nwire [C_MC_DATA_WIDTH-1:0] wdata_d3 ;\nwire [C_MC_DATA_WIDTH/8-1:0] wstrb_d3 ;\nwire wlast_d3 ;\nwire wvalid_d3 ;\nwire wready_d3 ;\nwire [C_S_AXI_ID_WIDTH-1:0] bid_d3 ;\nwire [1:0] bresp_d3 ;\nwire bvalid_d3 ;\nwire bready_d3 ;\nwire [C_S_AXI_ID_WIDTH-1:0] arid_d3 ;\nwire [C_S_AXI_ADDR_WIDTH-1:0] araddr_d3 ;\nwire [7:0] arlen_d3 ;\n// AxSIZE hardcoded with static value\n// wire [2:0] arsize_d3 ;\nwire [1:0] arburst_d3 ;\nwire [1:0] arlock_d3 ;\nwire [3:0] arcache_d3 ;\nwire [2:0] arprot_d3 ;\nwire [3:0] arqos_d3 ;\nwire arvalid_d3 ;\nwire arready_d3 ;\nwire [C_S_AXI_ID_WIDTH-1:0] rid_d3 ;\nwire [C_MC_DATA_WIDTH-1:0] rdata_d3 ;\nwire [1:0] rresp_d3 ;\nwire rlast_d3 ;\nwire rvalid_d3 ;\nwire rready_d3 ;\n\n// AW/AR module outputs to arbiter.\nwire wr_cmd_en ;\nwire wr_cmd_en_last ;\nwire [2:0] wr_cmd_instr ;\nwire [C_MC_ADDR_WIDTH-1:0] wr_cmd_byte_addr ;\nwire wr_cmd_full ;\nwire rd_cmd_en ;\nwire rd_cmd_en_last ;\nwire [2:0] rd_cmd_instr ;\nwire [C_MC_ADDR_WIDTH-1:0] rd_cmd_byte_addr ;\nwire rd_cmd_full ;\nwire aresetn_int ;\n\nwire cmd_wr_bytes;\n\nreg areset_d1;\nreg mc_init_complete_r;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n///////////////////////////////////////////////////////////////////////////////\nassign aresetn_int = aresetn & mc_init_complete_r;\n\nalways @(posedge aclk)\n areset_d1 <= ~aresetn_int;\n\nalways @(posedge aclk)\n mc_init_complete_r <= mc_init_complete ;\n\nmig_7series_v4_0_ddr_axi_register_slice #\n(\n .C_FAMILY ( C_FAMILY ) ,\n .C_AXI_ID_WIDTH ( C_S_AXI_ID_WIDTH ) ,\n .C_AXI_ADDR_WIDTH ( C_S_AXI_ADDR_WIDTH ) ,\n .C_AXI_DATA_WIDTH ( C_S_AXI_DATA_WIDTH ) ,\n .C_AXI_SUPPORTS_USER_SIGNALS ( P_SUPPORTS_USER_SIGNALS ) ,\n .C_AXI_AWUSER_WIDTH ( 1 ) ,\n .C_AXI_ARUSER_WIDTH ( 1 ) ,\n .C_AXI_WUSER_WIDTH ( 1 ) ,\n .C_AXI_RUSER_WIDTH ( 1 ) ,\n .C_AXI_BUSER_WIDTH ( 1 ) ,\n .C_REG_CONFIG_AW ( P_D1_REG_CONFIG_AW ) ,\n .C_REG_CONFIG_W ( P_D1_REG_CONFIG_W ) ,\n .C_REG_CONFIG_B ( P_D1_REG_CONFIG_B ) ,\n .C_REG_CONFIG_AR ( P_D1_REG_CONFIG_AR ) ,\n .C_REG_CONFIG_R ( P_D1_REG_CONFIG_R ) \n)\naxi_register_slice_d1\n(\n .ACLK ( aclk ) ,\n .ARESETN ( aresetn_int ) ,\n .S_AXI_AWID ( s_axi_awid ) ,\n .S_AXI_AWADDR ( s_axi_awaddr ) ,\n .S_AXI_AWLEN ( s_axi_awlen ) ,\n .S_AXI_AWSIZE ( s_axi_awsize ) ,\n .S_AXI_AWBURST ( s_axi_awburst ) ,\n .S_AXI_AWLOCK ( {1'b0, s_axi_awlock}) ,\n .S_AXI_AWCACHE ( s_axi_awcache ) ,\n .S_AXI_AWPROT ( s_axi_awprot ) ,\n .S_AXI_AWREGION( 4'b0 ) ,\n .S_AXI_AWQOS ( s_axi_awqos ) ,\n .S_AXI_AWUSER ( 1'b0 ) ,\n .S_AXI_AWVALID ( s_axi_awvalid ) ,\n .S_AXI_AWREADY ( s_axi_awready ) ,\n .S_AXI_WDATA ( s_axi_wdata ) ,\n .S_AXI_WID ( {C_S_AXI_ID_WIDTH{1'b0}} ) ,\n .S_AXI_WSTRB ( s_axi_wstrb ) ,\n .S_AXI_WLAST ( s_axi_wlast ) ,\n .S_AXI_WUSER ( 1'b0 ) ,\n .S_AXI_WVALID ( s_axi_wvalid ) ,\n .S_AXI_WREADY ( s_axi_wready ) ,\n .S_AXI_BID ( s_axi_bid ) ,\n .S_AXI_BRESP ( s_axi_bresp ) ,\n .S_AXI_BUSER ( ) ,\n .S_AXI_BVALID ( s_axi_bvalid ) ,\n .S_AXI_BREADY ( s_axi_bready ) ,\n .S_AXI_ARID ( s_axi_arid ) ,\n .S_AXI_ARADDR ( s_axi_araddr ) ,\n .S_AXI_ARLEN ( s_axi_arlen ) ,\n .S_AXI_ARSIZE ( s_axi_arsize ) ,\n .S_AXI_ARBURST ( s_axi_arburst ) ,\n .S_AXI_ARLOCK ( {1'b0, s_axi_arlock}) ,\n .S_AXI_ARCACHE ( s_axi_arcache ) ,\n .S_AXI_ARPROT ( s_axi_arprot ) ,\n .S_AXI_ARREGION( 4'b0 ) ,\n .S_AXI_ARQOS ( s_axi_arqos ) ,\n .S_AXI_ARUSER ( 1'b0 ) ,\n .S_AXI_ARVALID ( s_axi_arvalid ) ,\n .S_AXI_ARREADY ( s_axi_arready ) ,\n .S_AXI_RID ( s_axi_rid ) ,\n .S_AXI_RDATA ( s_axi_rdata ) ,\n .S_AXI_RRESP ( s_axi_rresp ) ,\n .S_AXI_RLAST ( s_axi_rlast ) ,\n .S_AXI_RUSER ( ) ,\n .S_AXI_RVALID ( s_axi_rvalid ) ,\n .S_AXI_RREADY ( s_axi_rready ) ,\n .M_AXI_AWID ( awid_d1 ) ,\n .M_AXI_AWADDR ( awaddr_d1 ) ,\n .M_AXI_AWLEN ( awlen_d1 ) ,\n .M_AXI_AWSIZE ( awsize_d1 ) ,\n .M_AXI_AWBURST ( awburst_d1 ) ,\n .M_AXI_AWLOCK ( awlock_d1 ) ,\n .M_AXI_AWCACHE ( awcache_d1 ) ,\n .M_AXI_AWREGION( ) ,\n .M_AXI_AWPROT ( awprot_d1 ) ,\n .M_AXI_AWQOS ( awqos_d1 ) ,\n .M_AXI_AWUSER ( ) ,\n .M_AXI_AWVALID ( awvalid_d1 ) ,\n .M_AXI_AWREADY ( awready_d1 ) ,\n .M_AXI_WID ( ) ,\n .M_AXI_WDATA ( wdata_d1 ) ,\n .M_AXI_WSTRB ( wstrb_d1 ) ,\n .M_AXI_WLAST ( wlast_d1 ) ,\n .M_AXI_WUSER ( ) ,\n .M_AXI_WVALID ( wvalid_d1 ) ,\n .M_AXI_WREADY ( wready_d1 ) ,\n .M_AXI_BID ( bid_d1 ) ,\n .M_AXI_BRESP ( bresp_d1 ) ,\n .M_AXI_BUSER ( 1'b0 ) ,\n .M_AXI_BVALID ( bvalid_d1 ) ,\n .M_AXI_BREADY ( bready_d1 ) ,\n .M_AXI_ARID ( arid_d1 ) ,\n .M_AXI_ARADDR ( araddr_d1 ) ,\n .M_AXI_ARLEN ( arlen_d1 ) ,\n .M_AXI_ARSIZE ( arsize_d1 ) ,\n .M_AXI_ARBURST ( arburst_d1 ) ,\n .M_AXI_ARLOCK ( arlock_d1 ) ,\n .M_AXI_ARCACHE ( arcache_d1 ) ,\n .M_AXI_ARPROT ( arprot_d1 ) ,\n .M_AXI_ARREGION( ) ,\n .M_AXI_ARQOS ( arqos_d1 ) ,\n .M_AXI_ARUSER ( ) ,\n .M_AXI_ARVALID ( arvalid_d1 ) ,\n .M_AXI_ARREADY ( arready_d1 ) ,\n .M_AXI_RID ( rid_d1 ) ,\n .M_AXI_RDATA ( rdata_d1 ) ,\n .M_AXI_RRESP ( rresp_d1 ) ,\n .M_AXI_RLAST ( rlast_d1 ) ,\n .M_AXI_RUSER ( 1'b0 ) ,\n .M_AXI_RVALID ( rvalid_d1 ) ,\n .M_AXI_RREADY ( rready_d1 ) \n);\n\ngenerate \n if (P_USE_UPSIZER) begin : USE_UPSIZER\n mig_7series_v4_0_ddr_axi_upsizer #\n (\n .C_FAMILY ( C_FAMILY ) ,\n .C_AXI_ID_WIDTH ( C_S_AXI_ID_WIDTH ) ,\n .C_AXI_ADDR_WIDTH ( C_S_AXI_ADDR_WIDTH ) ,\n .C_S_AXI_DATA_WIDTH ( C_S_AXI_DATA_WIDTH ) ,\n .C_M_AXI_DATA_WIDTH ( C_MC_DATA_WIDTH ) ,\n .C_M_AXI_AW_REGISTER ( P_D2_REG_CONFIG_AW ) ,\n .C_M_AXI_W_REGISTER ( P_D2_REG_CONFIG_W ) ,\n .C_M_AXI_AR_REGISTER ( P_D2_REG_CONFIG_AR ) ,\n .C_S_AXI_R_REGISTER ( P_D2_REG_CONFIG_R ) ,\n .C_AXI_SUPPORTS_USER_SIGNALS ( P_SUPPORTS_USER_SIGNALS ) ,\n .C_AXI_AWUSER_WIDTH ( 1 ) ,\n .C_AXI_ARUSER_WIDTH ( 1 ) ,\n .C_AXI_WUSER_WIDTH ( 1 ) ,\n .C_AXI_RUSER_WIDTH ( 1 ) ,\n .C_AXI_BUSER_WIDTH ( 1 ) ,\n .C_AXI_SUPPORTS_WRITE ( 1 ) ,\n .C_AXI_SUPPORTS_READ ( 1 ) ,\n .C_PACKING_LEVEL ( P_UPSIZER_PACKING_LEVEL ) ,\n .C_SUPPORT_BURSTS ( 1 ) ,\n .C_SINGLE_THREAD ( P_SINGLE_THREAD ) \n )\n upsizer_d2\n (\n .ACLK ( aclk ) ,\n .ARESETN ( aresetn_int ) ,\n .S_AXI_AWID ( awid_d1 ) ,\n .S_AXI_AWADDR ( awaddr_d1 ) ,\n .S_AXI_AWLEN ( awlen_d1 ) ,\n .S_AXI_AWSIZE ( awsize_d1 ) ,\n .S_AXI_AWBURST ( awburst_d1 ) ,\n .S_AXI_AWLOCK ( awlock_d1 ) ,\n .S_AXI_AWCACHE ( awcache_d1 ) ,\n .S_AXI_AWPROT ( awprot_d1 ) ,\n .S_AXI_AWREGION( 4'b0 ) ,\n .S_AXI_AWQOS ( awqos_d1 ) ,\n .S_AXI_AWUSER ( 1'b0 ) ,\n .S_AXI_AWVALID ( awvalid_d1 ) ,\n .S_AXI_AWREADY ( awready_d1 ) ,\n .S_AXI_WDATA ( wdata_d1 ) ,\n .S_AXI_WSTRB ( wstrb_d1 ) ,\n .S_AXI_WLAST ( wlast_d1 ) ,\n .S_AXI_WUSER ( 1'b0 ) ,\n .S_AXI_WVALID ( wvalid_d1 ) ,\n .S_AXI_WREADY ( wready_d1 ) ,\n .S_AXI_BID ( bid_d1 ) ,\n .S_AXI_BRESP ( bresp_d1 ) ,\n .S_AXI_BUSER ( ) ,\n .S_AXI_BVALID ( bvalid_d1 ) ,\n .S_AXI_BREADY ( bready_d1 ) ,\n .S_AXI_ARID ( arid_d1 ) ,\n .S_AXI_ARADDR ( araddr_d1 ) ,\n .S_AXI_ARLEN ( arlen_d1 ) ,\n .S_AXI_ARSIZE ( arsize_d1 ) ,\n .S_AXI_ARBURST ( arburst_d1 ) ,\n .S_AXI_ARLOCK ( arlock_d1 ) ,\n .S_AXI_ARCACHE ( arcache_d1 ) ,\n .S_AXI_ARPROT ( arprot_d1 ) ,\n .S_AXI_ARREGION( 4'b0 ) ,\n .S_AXI_ARQOS ( arqos_d1 ) ,\n .S_AXI_ARUSER ( 1'b0 ) ,\n .S_AXI_ARVALID ( arvalid_d1 ) ,\n .S_AXI_ARREADY ( arready_d1 ) ,\n .S_AXI_RID ( rid_d1 ) ,\n .S_AXI_RDATA ( rdata_d1 ) ,\n .S_AXI_RRESP ( rresp_d1 ) ,\n .S_AXI_RLAST ( rlast_d1 ) ,\n .S_AXI_RUSER ( ) ,\n .S_AXI_RVALID ( rvalid_d1 ) ,\n .S_AXI_RREADY ( rready_d1 ) ,\n .M_AXI_AWID ( awid_d2 ) ,\n .M_AXI_AWADDR ( awaddr_d2 ) ,\n .M_AXI_AWLEN ( awlen_d2 ) ,\n .M_AXI_AWSIZE ( awsize_d2 ) ,\n .M_AXI_AWBURST ( awburst_d2 ) ,\n .M_AXI_AWLOCK ( awlock_d2 ) ,\n .M_AXI_AWCACHE ( awcache_d2 ) ,\n .M_AXI_AWPROT ( awprot_d2 ) ,\n .M_AXI_AWREGION( ) ,\n .M_AXI_AWQOS ( awqos_d2 ) ,\n .M_AXI_AWUSER ( ) ,\n .M_AXI_AWVALID ( awvalid_d2 ) ,\n .M_AXI_AWREADY ( awready_d2 ) ,\n .M_AXI_WDATA ( wdata_d2 ) ,\n .M_AXI_WSTRB ( wstrb_d2 ) ,\n .M_AXI_WLAST ( wlast_d2 ) ,\n .M_AXI_WUSER ( ) ,\n .M_AXI_WVALID ( wvalid_d2 ) ,\n .M_AXI_WREADY ( wready_d2 ) ,\n .M_AXI_BID ( bid_d2 ) ,\n .M_AXI_BRESP ( bresp_d2 ) ,\n .M_AXI_BUSER ( 1'b0 ) ,\n .M_AXI_BVALID ( bvalid_d2 ) ,\n .M_AXI_BREADY ( bready_d2 ) ,\n .M_AXI_ARID ( arid_d2 ) ,\n .M_AXI_ARADDR ( araddr_d2 ) ,\n .M_AXI_ARLEN ( arlen_d2 ) ,\n .M_AXI_ARSIZE ( arsize_d2 ) ,\n .M_AXI_ARBURST ( arburst_d2 ) ,\n .M_AXI_ARLOCK ( arlock_d2 ) ,\n .M_AXI_ARCACHE ( arcache_d2 ) ,\n .M_AXI_ARPROT ( arprot_d2 ) ,\n .M_AXI_ARREGION( ) ,\n .M_AXI_ARQOS ( arqos_d2 ) ,\n .M_AXI_ARUSER ( ) ,\n .M_AXI_ARVALID ( arvalid_d2 ) ,\n .M_AXI_ARREADY ( arready_d2 ) ,\n .M_AXI_RID ( rid_d2 ) ,\n .M_AXI_RDATA ( rdata_d2 ) ,\n .M_AXI_RRESP ( rresp_d2 ) ,\n .M_AXI_RLAST ( rlast_d2 ) ,\n .M_AXI_RUSER ( 1'b0 ) ,\n .M_AXI_RVALID ( rvalid_d2 ) ,\n .M_AXI_RREADY ( rready_d2 ) \n );\n end\n else begin : NO_UPSIZER\n assign awid_d2 = awid_d1 ; \n assign awaddr_d2 = awaddr_d1 ; \n assign awlen_d2 = awlen_d1 ; \n assign awsize_d2 = awsize_d1 ; \n assign awburst_d2 = awburst_d1 ; \n assign awlock_d2 = awlock_d1 ; \n assign awcache_d2 = awcache_d1 ; \n assign awprot_d2 = awprot_d1 ; \n assign awqos_d2 = awqos_d1 ; \n assign awvalid_d2 = awvalid_d1 ; \n assign awready_d1 = awready_d2 ; \n assign wdata_d2 = wdata_d1 ; \n assign wstrb_d2 = wstrb_d1 ; \n assign wlast_d2 = wlast_d1 ; \n assign wvalid_d2 = wvalid_d1 ; \n assign wready_d1 = wready_d2 ; \n assign bid_d1 = bid_d2 ; \n assign bresp_d1 = bresp_d2 ; \n assign bvalid_d1 = bvalid_d2 ; \n assign bready_d2 = bready_d1 ; \n assign arid_d2 = arid_d1 ; \n assign araddr_d2 = araddr_d1 ; \n assign arlen_d2 = arlen_d1 ; \n assign arsize_d2 = arsize_d1 ; \n assign arburst_d2 = arburst_d1 ; \n assign arlock_d2 = arlock_d1 ; \n assign arcache_d2 = arcache_d1 ; \n assign arprot_d2 = arprot_d1 ; \n assign arqos_d2 = arqos_d1 ; \n assign arvalid_d2 = arvalid_d1 ; \n assign arready_d1 = arready_d2 ; \n assign rid_d1 = rid_d2 ; \n assign rdata_d1 = rdata_d2 ; \n assign rresp_d1 = rresp_d2 ; \n assign rlast_d1 = rlast_d2 ; \n assign rvalid_d1 = rvalid_d2 ; \n assign rready_d2 = rready_d1 ; \n end\nendgenerate\n\nmig_7series_v4_0_ddr_axi_register_slice #\n(\n .C_FAMILY ( C_FAMILY ) ,\n .C_AXI_ID_WIDTH ( C_S_AXI_ID_WIDTH ) ,\n .C_AXI_ADDR_WIDTH ( C_S_AXI_ADDR_WIDTH ) ,\n .C_AXI_DATA_WIDTH ( C_MC_DATA_WIDTH ) ,\n .C_AXI_SUPPORTS_USER_SIGNALS ( P_SUPPORTS_USER_SIGNALS ) ,\n .C_AXI_AWUSER_WIDTH ( 1 ) ,\n .C_AXI_ARUSER_WIDTH ( 1 ) ,\n .C_AXI_WUSER_WIDTH ( 1 ) ,\n .C_AXI_RUSER_WIDTH ( 1 ) ,\n .C_AXI_BUSER_WIDTH ( 1 ) ,\n .C_REG_CONFIG_AW ( P_D3_REG_CONFIG_AW ) ,\n .C_REG_CONFIG_W ( P_D3_REG_CONFIG_W ) ,\n .C_REG_CONFIG_B ( P_D3_REG_CONFIG_B ) ,\n .C_REG_CONFIG_AR ( P_D3_REG_CONFIG_AR ) ,\n .C_REG_CONFIG_R ( P_D3_REG_CONFIG_R ) \n)\naxi_register_slice_d3\n(\n .ACLK ( aclk ) ,\n .ARESETN ( aresetn_int ) ,\n .S_AXI_AWID ( awid_d2 ) ,\n .S_AXI_AWADDR ( awaddr_d2 ) ,\n .S_AXI_AWLEN ( awlen_d2 ) ,\n .S_AXI_AWSIZE ( P_AXSIZE[2:0] ) ,\n .S_AXI_AWBURST ( awburst_d2 ) ,\n .S_AXI_AWLOCK ( awlock_d2 ) ,\n .S_AXI_AWCACHE ( awcache_d2 ) ,\n .S_AXI_AWPROT ( awprot_d2 ) ,\n .S_AXI_AWREGION( 4'b0 ) ,\n .S_AXI_AWQOS ( awqos_d2 ) ,\n .S_AXI_AWUSER ( 1'b0 ) ,\n .S_AXI_AWVALID ( awvalid_d2 ) ,\n .S_AXI_AWREADY ( awready_d2 ) ,\n .S_AXI_WID ( {C_S_AXI_ID_WIDTH{1'b0}} ) ,\n .S_AXI_WDATA ( wdata_d2 ) ,\n .S_AXI_WSTRB ( wstrb_d2 ) ,\n .S_AXI_WLAST ( wlast_d2 ) ,\n .S_AXI_WUSER ( 1'b0 ) ,\n .S_AXI_WVALID ( wvalid_d2 ) ,\n .S_AXI_WREADY ( wready_d2 ) ,\n .S_AXI_BID ( bid_d2 ) ,\n .S_AXI_BRESP ( bresp_d2 ) ,\n .S_AXI_BUSER ( ) ,\n .S_AXI_BVALID ( bvalid_d2 ) ,\n .S_AXI_BREADY ( bready_d2 ) ,\n .S_AXI_ARID ( arid_d2 ) ,\n .S_AXI_ARADDR ( araddr_d2 ) ,\n .S_AXI_ARLEN ( arlen_d2 ) ,\n .S_AXI_ARSIZE ( P_AXSIZE[2:0] ) ,\n .S_AXI_ARBURST ( arburst_d2 ) ,\n .S_AXI_ARLOCK ( arlock_d2 ) ,\n .S_AXI_ARCACHE ( arcache_d2 ) ,\n .S_AXI_ARPROT ( arprot_d2 ) ,\n .S_AXI_ARREGION( 4'b0 ) ,\n .S_AXI_ARQOS ( arqos_d2 ) ,\n .S_AXI_ARUSER ( 1'b0 ) ,\n .S_AXI_ARVALID ( arvalid_d2 ) ,\n .S_AXI_ARREADY ( arready_d2 ) ,\n .S_AXI_RID ( rid_d2 ) ,\n .S_AXI_RDATA ( rdata_d2 ) ,\n .S_AXI_RRESP ( rresp_d2 ) ,\n .S_AXI_RLAST ( rlast_d2 ) ,\n .S_AXI_RUSER ( ) ,\n .S_AXI_RVALID ( rvalid_d2 ) ,\n .S_AXI_RREADY ( rready_d2 ) ,\n .M_AXI_AWID ( awid_d3 ) ,\n .M_AXI_AWADDR ( awaddr_d3 ) ,\n .M_AXI_AWLEN ( awlen_d3 ) ,\n// AxSIZE hardcoded with static value\n// .M_AXI_AWSIZE ( awsize_d3 ) ,\n .M_AXI_AWSIZE ( ) ,\n .M_AXI_AWBURST ( awburst_d3 ) ,\n .M_AXI_AWLOCK ( awlock_d3 ) ,\n .M_AXI_AWCACHE ( awcache_d3 ) ,\n .M_AXI_AWPROT ( awprot_d3 ) ,\n .M_AXI_AWREGION( ) ,\n .M_AXI_AWQOS ( awqos_d3 ) ,\n .M_AXI_AWUSER ( ) ,\n .M_AXI_AWVALID ( awvalid_d3 ) ,\n .M_AXI_AWREADY ( awready_d3 ) ,\n .M_AXI_WID ( ) ,\n .M_AXI_WDATA ( wdata_d3 ) ,\n .M_AXI_WSTRB ( wstrb_d3 ) ,\n .M_AXI_WLAST ( wlast_d3 ) ,\n .M_AXI_WUSER ( ) ,\n .M_AXI_WVALID ( wvalid_d3 ) ,\n .M_AXI_WREADY ( wready_d3 ) ,\n .M_AXI_BID ( bid_d3 ) ,\n .M_AXI_BRESP ( bresp_d3 ) ,\n .M_AXI_BUSER ( 1'b0 ) ,\n .M_AXI_BVALID ( bvalid_d3 ) ,\n .M_AXI_BREADY ( bready_d3 ) ,\n .M_AXI_ARID ( arid_d3 ) ,\n .M_AXI_ARADDR ( araddr_d3 ) ,\n .M_AXI_ARLEN ( arlen_d3 ) ,\n// AxSIZE hardcoded with static value\n// .M_AXI_ARSIZE ( arsize_d3 ) ,\n .M_AXI_ARSIZE ( ) ,\n .M_AXI_ARBURST ( arburst_d3 ) ,\n .M_AXI_ARLOCK ( arlock_d3 ) ,\n .M_AXI_ARCACHE ( arcache_d3 ) ,\n .M_AXI_ARPROT ( arprot_d3 ) ,\n .M_AXI_ARREGION( ) ,\n .M_AXI_ARQOS ( arqos_d3 ) ,\n .M_AXI_ARUSER ( ) ,\n .M_AXI_ARVALID ( arvalid_d3 ) ,\n .M_AXI_ARREADY ( arready_d3 ) ,\n .M_AXI_RID ( rid_d3 ) ,\n .M_AXI_RDATA ( rdata_d3 ) ,\n .M_AXI_RRESP ( rresp_d3 ) ,\n .M_AXI_RLAST ( rlast_d3 ) ,\n .M_AXI_RUSER ( 1'b0 ) ,\n .M_AXI_RVALID ( rvalid_d3 ) ,\n .M_AXI_RREADY ( rready_d3 ) \n);\n \n \n// AW/W/B channel internal communication\nwire w_ignore_begin;\nwire w_ignore_end;\nwire w_cmd_rdy; \nwire awvalid_int; \nwire [3:0] awqos_int ;\nwire w_data_rdy ;\nwire b_push;\nwire [C_S_AXI_ID_WIDTH-1:0] b_awid;\nwire b_full;\n \nmig_7series_v4_0_axi_mc_aw_channel #\n(\n .C_ID_WIDTH ( C_S_AXI_ID_WIDTH ),\n .C_AXI_ADDR_WIDTH ( C_S_AXI_ADDR_WIDTH ),\n .C_MC_ADDR_WIDTH ( C_MC_ADDR_WIDTH ),\n .C_DATA_WIDTH ( C_MC_DATA_WIDTH ),\n .C_AXSIZE ( P_AXSIZE ),\n .C_MC_nCK_PER_CLK ( C_MC_nCK_PER_CLK ),\n .C_MC_BURST_LEN ( C_MC_BURST_LEN ),\n .C_ECC ( C_ECC )\n)\naxi_mc_aw_channel_0\n(\n .clk ( aclk ) ,\n .reset ( areset_d1 ) ,\n .awid ( awid_d3 ) ,\n .awaddr ( awaddr_d3 ) ,\n .awlen ( awlen_d3 ) ,\n .awsize ( P_AXSIZE[2:0] ) ,\n .awburst ( awburst_d3 ) ,\n .awlock ( awlock_d3 ) ,\n .awcache ( awcache_d3 ) ,\n .awprot ( awprot_d3 ) ,\n .awqos ( awqos_d3 ) ,\n .awvalid ( awvalid_d3 ) ,\n .awready ( awready_d3 ) ,\n .cmd_en ( wr_cmd_en ) ,\n .cmd_instr ( wr_cmd_instr ) ,\n .cmd_byte_addr ( wr_cmd_byte_addr ) ,\n .cmd_full ( wr_cmd_full ) ,\n .cmd_en_last ( wr_cmd_en_last ) ,\n .w_ignore_begin ( w_ignore_begin ) ,\n .w_ignore_end ( w_ignore_end ) ,\n .w_cmd_rdy ( w_cmd_rdy ) ,\n .awvalid_int ( awvalid_int ) ,\n .awqos_int ( awqos_int ) ,\n .w_data_rdy ( w_data_rdy ) ,\n .cmd_wr_bytes ( cmd_wr_bytes ) ,\n .b_push ( b_push ) ,\n .b_awid ( b_awid ) ,\n .b_full ( b_full )\n);\n\nmig_7series_v4_0_axi_mc_w_channel #\n(\n .C_DATA_WIDTH ( C_MC_DATA_WIDTH ), \n .C_AXI_ADDR_WIDTH ( C_S_AXI_ADDR_WIDTH ),\n .C_MC_BURST_LEN ( C_MC_BURST_LEN ),\n .C_ECC ( C_ECC )\n)\naxi_mc_w_channel_0\n(\n .clk ( aclk ) ,\n .reset ( areset_d1 ) ,\n .wdata ( wdata_d3 ) ,\n .wstrb ( wstrb_d3 ) ,\n .wvalid ( wvalid_d3 ) ,\n .wready ( wready_d3 ) ,\n .awvalid ( awvalid_int ) ,\n .w_ignore_begin ( w_ignore_begin ) ,\n .w_ignore_end ( w_ignore_end ) ,\n .w_cmd_rdy ( w_cmd_rdy ) ,\n .cmd_wr_bytes ( cmd_wr_bytes ) ,\n .mc_app_wdf_wren ( mc_app_wdf_wren ) ,\n .mc_app_wdf_mask ( mc_app_wdf_mask ) ,\n .mc_app_wdf_data ( mc_app_wdf_data ) ,\n .mc_app_wdf_last ( mc_app_wdf_end ) , \n .mc_app_wdf_rdy ( mc_app_wdf_rdy ) ,\n .w_data_rdy ( w_data_rdy )\n);\n\nmig_7series_v4_0_axi_mc_b_channel #\n(\n .C_ID_WIDTH ( C_S_AXI_ID_WIDTH )\n)\naxi_mc_b_channel_0\n(\n .clk ( aclk ) ,\n .reset ( areset_d1 ) ,\n .bid ( bid_d3 ) ,\n .bresp ( bresp_d3 ) ,\n .bvalid ( bvalid_d3 ) ,\n .bready ( bready_d3 ) ,\n .b_push ( b_push ) ,\n .b_awid ( b_awid ) ,\n .b_full ( b_full ) ,\n .b_resp_rdy ( awready_d3 ) \n);\n \n \n// AR/R channel communication\nwire r_push ; \nwire [C_S_AXI_ID_WIDTH-1:0] r_arid ; \nwire r_rlast ; \nwire r_data_rdy ;\nwire r_ignore_begin;\nwire r_ignore_end ;\nwire arvalid_int ;\nwire [3:0] arqos_int ;\n \n \n \n \n\n\nmig_7series_v4_0_axi_mc_ar_channel #\n(\n .C_ID_WIDTH ( C_S_AXI_ID_WIDTH ),\n .C_AXI_ADDR_WIDTH ( C_S_AXI_ADDR_WIDTH ),\n .C_MC_ADDR_WIDTH ( C_MC_ADDR_WIDTH ),\n .C_DATA_WIDTH ( C_MC_DATA_WIDTH ),\n .C_AXSIZE ( P_AXSIZE ),\n .C_MC_nCK_PER_CLK ( C_MC_nCK_PER_CLK ),\n .C_MC_BURST_LEN ( C_MC_BURST_LEN )\n\n)\naxi_mc_ar_channel_0\n(\n .clk ( aclk ) ,\n .reset ( areset_d1 ) ,\n .arid ( arid_d3 ) ,\n .araddr ( araddr_d3 ) ,\n .arlen ( arlen_d3 ) ,\n .arsize ( P_AXSIZE[2:0] ) ,\n .arburst ( arburst_d3 ) ,\n .arlock ( arlock_d3 ) ,\n .arcache ( arcache_d3 ) ,\n .arprot ( arprot_d3 ) ,\n .arqos ( arqos_d3 ) ,\n .arvalid ( arvalid_d3 ) ,\n .arready ( arready_d3 ) ,\n .cmd_en ( rd_cmd_en ) ,\n .cmd_instr ( rd_cmd_instr ) ,\n .cmd_byte_addr ( rd_cmd_byte_addr ) ,\n .cmd_full ( rd_cmd_full ) ,\n .cmd_en_last ( rd_cmd_en_last ) ,\n .r_push ( r_push ) ,\n .r_arid ( r_arid ) ,\n .r_rlast ( r_rlast ) ,\n .r_data_rdy ( r_data_rdy ) ,\n .r_ignore_begin ( r_ignore_begin ) ,\n .r_ignore_end ( r_ignore_end ) ,\n .arvalid_int ( arvalid_int ) ,\n .arqos_int ( arqos_int ) \n);\n\nmig_7series_v4_0_axi_mc_r_channel #\n(\n .C_ID_WIDTH ( C_S_AXI_ID_WIDTH ), \n .C_DATA_WIDTH ( C_MC_DATA_WIDTH ),\n .C_AXI_ADDR_WIDTH ( C_S_AXI_ADDR_WIDTH ),\n .C_MC_BURST_MODE ( C_MC_BURST_MODE ),\n .C_MC_BURST_LEN ( C_MC_BURST_LEN )\n)\naxi_mc_r_channel_0\n(\n .clk ( aclk ) ,\n .reset ( areset_d1 ) ,\n .rid ( rid_d3 ) ,\n .rdata ( rdata_d3 ) ,\n .rresp ( rresp_d3 ) ,\n .rlast ( rlast_d3 ) ,\n .rvalid ( rvalid_d3 ) ,\n .rready ( rready_d3 ) ,\n .mc_app_rd_valid ( mc_app_rd_valid ) ,\n .mc_app_rd_data ( mc_app_rd_data ) ,\n .mc_app_rd_last ( mc_app_rd_end ) ,\n .mc_app_ecc_multiple_err ( |mc_app_ecc_multiple_err ) ,\n .r_push ( r_push ) ,\n .r_data_rdy ( r_data_rdy ) ,\n .r_arid ( r_arid ) ,\n .r_rlast ( r_rlast ) ,\n .r_ignore_begin ( r_ignore_begin ) ,\n .r_ignore_end ( r_ignore_end ) \n);\n\n// Arbiter \nmig_7series_v4_0_axi_mc_cmd_arbiter #\n(\n .C_MC_ADDR_WIDTH ( C_MC_ADDR_WIDTH ) ,\n .C_MC_BURST_LEN ( C_MC_BURST_LEN ) ,\n .C_RD_WR_ARB_ALGORITHM ( C_RD_WR_ARB_ALGORITHM ) \n)\naxi_mc_cmd_arbiter_0\n(\n .clk ( aclk ) ,\n .reset ( areset_d1 ) ,\n // Write commands from AXI\n .wr_cmd_en ( wr_cmd_en ) ,\n .wr_cmd_en_last ( wr_cmd_en_last ) , \n .wr_cmd_instr ( wr_cmd_instr ) ,\n .wr_cmd_byte_addr ( wr_cmd_byte_addr ) ,\n .wr_cmd_full ( wr_cmd_full ) ,\n // Read commands from AXI\n .rd_cmd_en ( rd_cmd_en ) ,\n .rd_cmd_en_last ( rd_cmd_en_last ) ,\n .rd_cmd_instr ( rd_cmd_instr ) ,\n .rd_cmd_byte_addr ( rd_cmd_byte_addr ) ,\n .rd_cmd_full ( rd_cmd_full ) ,\n // Next Command info\n .arvalid ( arvalid_int ) ,\n .arqos ( arqos_int ) ,\n .awvalid ( awvalid_int ) ,\n .awqos ( awqos_int ) ,\n // To MC\n .mc_app_en ( mc_app_en ) ,\n .mc_app_cmd ( mc_app_cmd ) ,\n .mc_app_size ( mc_app_sz ) ,\n .mc_app_addr ( mc_app_addr ) ,\n .mc_app_hi_pri ( mc_app_hi_pri ) , \n .mc_app_rdy ( mc_app_rdy ) \n);\n\nendmodule\n\n`default_nettype wire\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_ar_channel.v", "content": "// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. \n// -- \n// -- This file contains confidential and proprietary information \n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property \n// -- laws. \n// -- \n// -- DISCLAIMER \n// -- This disclaimer is not a license and does not grant any \n// -- rights to the materials distributed herewith. Except as \n// -- otherwise provided in a valid license issued to you by \n// -- Xilinx, and to the maximum extent permitted by applicable \n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND \n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES \n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING \n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- \n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and \n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of \n// -- liability) for any loss or damage of any kind or nature \n// -- related to, arising under or in connection with these \n// -- materials, including for any direct, or any indirect, \n// -- special, incidental, or consequential loss or damage \n// -- (including loss of data, profits, goodwill, or any type of \n// -- loss or damage suffered as a result of any action brought \n// -- by a third party) even if such damage or loss was \n// -- reasonably foreseeable or Xilinx had been advised of the \n// -- possibility of the same. \n// -- \n// -- CRITICAL APPLICATIONS \n// -- Xilinx products are not designed or intended to be fail- \n// -- safe, or for use in any application requiring fail-safe \n// -- performance, such as life-support or safety devices or \n// -- systems, Class III medical devices, nuclear facilities, \n// -- applications related to the deployment of airbags, or any \n// -- other applications that could lead to death, personal \n// -- injury, or severe property or environmental damage \n// -- (individually and collectively, \"Critical \n// -- Applications\"). Customer assumes the sole risk and \n// -- liability of any use of Xilinx products in Critical \n// -- Applications, subject only to applicable laws and \n// -- regulations governing limitations on product liability. \n// -- \n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS \n// -- PART OF THIS FILE AT ALL TIMES. \n// -- \n///////////////////////////////////////////////////////////////////////////////\n//\n// File name: axi_mc_ar_channel.v\n//\n// Description: \n//\n///////////////////////////////////////////////////////////////////////////////\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule mig_7series_v4_0_axi_mc_ar_channel #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n // Width of ID signals.\n // Range: >= 1.\n parameter integer C_ID_WIDTH = 4, \n // Width of AxADDR\n // Range: 32.\n parameter integer C_AXI_ADDR_WIDTH = 32, \n // Width of cmd_byte_addr\n // Range: 30\n parameter integer C_MC_ADDR_WIDTH = 30,\n // Width of AXI xDATA and MC xx_data\n // Range: 32, 64, 128.\n parameter integer C_DATA_WIDTH = 32,\n // MC burst length. = 1 for BL4 or BC4, = 2 for BL8\n parameter integer C_MC_BURST_LEN = 1,\n // DRAM clock to AXI clock ratio\n // supported values 2, 4\n parameter integer C_MC_nCK_PER_CLK = 2, \n // Static value of axsize\n // Range: 2-4\n parameter integer C_AXSIZE = 2\n \n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations \n///////////////////////////////////////////////////////////////////////////////\n // AXI Slave Interface\n // Slave Interface System Signals \n input wire clk , \n input wire reset , \n\n // Slave Interface Read Address Ports\n input wire [C_ID_WIDTH-1:0] arid , \n input wire [C_AXI_ADDR_WIDTH-1:0] araddr , \n input wire [7:0] arlen , \n input wire [2:0] arsize , \n input wire [1:0] arburst , \n input wire [1:0] arlock , \n input wire [3:0] arcache , \n input wire [2:0] arprot , \n input wire [3:0] arqos , \n input wire arvalid , \n output wire arready , \n\n // MC Master Interface\n //CMD PORT\n output wire cmd_en , \n output wire cmd_en_last ,\n output wire [2:0] cmd_instr , \n output wire [C_MC_ADDR_WIDTH-1:0] cmd_byte_addr , \n input wire cmd_full ,\n\n // Connections to/from axi_mc_r_channel module\n input wire r_data_rdy ,\n output reg r_push ,\n output wire[C_ID_WIDTH-1:0] r_arid ,\n output reg r_rlast ,\n output wire r_ignore_begin ,\n output wire r_ignore_end ,\n output wire arvalid_int ,\n output wire [3:0] arqos_int \n\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam P_CMD_WRITE = 3'b000;\nlocalparam P_CMD_READ = 3'b001;\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nwire next ;\nwire next_pending ;\n\nreg [C_ID_WIDTH-1:0] axid ;\nreg [C_AXI_ADDR_WIDTH-1:0] axaddr ;\nreg [7:0] axlen ;\nreg [3:0] axqos ;\nreg [1:0] axburst ;\nreg axvalid ;\n\nwire [C_ID_WIDTH-1:0] axid_int ;\nwire [C_AXI_ADDR_WIDTH-1:0] axaddr_int ;\nwire [7:0] axlen_int ;\nwire [3:0] axqos_int ;\nwire [1:0] axburst_int ;\nwire axvalid_int ;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\nassign arvalid_int = axvalid_int;\nassign arqos_int = axqos_int;\n\nassign axid_int = arready ? arid : axid;\nassign axlen_int = arready ? arlen : axlen;\nassign axqos_int = arready ? arqos : axqos;\nassign axaddr_int = arready ? araddr : axaddr;\nassign axburst_int = arready ? arburst : axburst;\nassign axvalid_int = arready ? arvalid : axvalid;\n\nalways @(posedge clk) begin\n if(reset)\n axvalid <= 1'b0;\n else\n axvalid <= axvalid_int;\nend\n\nalways @(posedge clk) begin\n axid <= axid_int;\n axlen <= axlen_int;\n axqos <= axqos_int;\n axaddr <= axaddr_int;\n axburst <= axburst_int;\nend\n\n// Translate the AXI transaction to the MC transaction(s)\nmig_7series_v4_0_axi_mc_cmd_translator #\n(\n .C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,\n .C_MC_ADDR_WIDTH ( C_MC_ADDR_WIDTH ) ,\n .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n .C_MC_BURST_LEN ( C_MC_BURST_LEN ) ,\n .C_MC_nCK_PER_CLK ( C_MC_nCK_PER_CLK ) ,\n .C_AXSIZE ( C_AXSIZE ) ,\n .C_MC_RD_INST ( 1 )\n)\naxi_mc_cmd_translator_0\n(\n .clk ( clk ) ,\n .reset ( reset ) ,\n .axaddr ( axaddr_int ) ,\n .axlen ( axlen_int ) ,\n .axsize ( arsize ) , // This is a constant, need not be sampled. Fed the direct input to aviod timing violations.\n .axburst ( axburst_int ) ,\n .axvalid ( axvalid_int ) ,\n .axready ( arready ) ,\n .cmd_byte_addr ( cmd_byte_addr ) ,\n .ignore_begin ( r_ignore_begin ) ,\n .ignore_end ( r_ignore_end ) ,\n .next ( next ) ,\n .next_pending ( next_pending ) \n);\n\nmig_7series_v4_0_axi_mc_cmd_fsm #\n(\n .C_MC_BURST_LEN (C_MC_BURST_LEN ),\n .C_MC_RD_INST (1 )\n)\nar_cmd_fsm_0\n(\n .clk ( clk ) ,\n .reset ( reset ) ,\n .axready ( arready ) ,\n .axvalid ( axvalid_int ) ,\n .cmd_en ( cmd_en ) ,\n .cmd_full ( cmd_full ) ,\n .next ( next ) ,\n .next_pending ( next_pending ) ,\n .data_rdy ( r_data_rdy ) ,\n .cmd_en_last ( cmd_en_last )\n);\n\nassign cmd_instr = P_CMD_READ;\n\n// these signals can be moved out of this block to the top level. \nassign r_arid = axid;\n\nalways @(posedge clk) begin\n r_push <= next;\n r_rlast <= ~next_pending;\nend\n\nendmodule\n\n`default_nettype wire\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_aw_channel.v", "content": "// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. \n// -- \n// -- This file contains confidential and proprietary information \n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property \n// -- laws. \n// -- \n// -- DISCLAIMER \n// -- This disclaimer is not a license and does not grant any \n// -- rights to the materials distributed herewith. Except as \n// -- otherwise provided in a valid license issued to you by \n// -- Xilinx, and to the maximum extent permitted by applicable \n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND \n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES \n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING \n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- \n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and \n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of \n// -- liability) for any loss or damage of any kind or nature \n// -- related to, arising under or in connection with these \n// -- materials, including for any direct, or any indirect, \n// -- special, incidental, or consequential loss or damage \n// -- (including loss of data, profits, goodwill, or any type of \n// -- loss or damage suffered as a result of any action brought \n// -- by a third party) even if such damage or loss was \n// -- reasonably foreseeable or Xilinx had been advised of the \n// -- possibility of the same. \n// -- \n// -- CRITICAL APPLICATIONS \n// -- Xilinx products are not designed or intended to be fail- \n// -- safe, or for use in any application requiring fail-safe \n// -- performance, such as life-support or safety devices or \n// -- systems, Class III medical devices, nuclear facilities, \n// -- applications related to the deployment of airbags, or any \n// -- other applications that could lead to death, personal \n// -- injury, or severe property or environmental damage \n// -- (individually and collectively, \"Critical \n// -- Applications\"). Customer assumes the sole risk and \n// -- liability of any use of Xilinx products in Critical \n// -- Applications, subject only to applicable laws and \n// -- regulations governing limitations on product liability. \n// -- \n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS \n// -- PART OF THIS FILE AT ALL TIMES. \n// -- \n///////////////////////////////////////////////////////////////////////////////\n//\n// File name: axi_mc_aw_channel.v\n//\n// Description: \n//\n///////////////////////////////////////////////////////////////////////////////\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule mig_7series_v4_0_axi_mc_aw_channel #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n // Width of ID signals.\n // Range: >= 1.\n parameter integer C_ID_WIDTH = 4, \n // Width of AxADDR\n // Range: 32.\n parameter integer C_AXI_ADDR_WIDTH = 32, \n // Width of cmd_byte_addr\n // Range: 30\n parameter integer C_MC_ADDR_WIDTH = 30,\n // Width of AXI xDATA and MC xx_data\n // Range: 32, 64, 128.\n parameter integer C_DATA_WIDTH = 32,\n // MC burst length. = 1 for BL4 or BC4, = 2 for BL8\n parameter integer C_MC_BURST_LEN = 1,\n // DRAM clock to AXI clock ratio\n // supported values 2, 4\n parameter integer C_MC_nCK_PER_CLK = 2, \n // Static value of axsize\n // Range: 2-4\n parameter integer C_AXSIZE = 2,\n parameter C_ECC = \"OFF\"\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations \n///////////////////////////////////////////////////////////////////////////////\n // AXI Slave Interface\n // Slave Interface System Signals \n input wire clk , \n input wire reset , \n\n // Slave Interface Write Address Ports\n input wire [C_ID_WIDTH-1:0] awid , \n input wire [C_AXI_ADDR_WIDTH-1:0] awaddr , \n input wire [7:0] awlen , \n input wire [2:0] awsize , \n input wire [1:0] awburst , \n input wire [1:0] awlock , \n input wire [3:0] awcache , \n input wire [2:0] awprot , \n input wire [3:0] awqos , \n input wire awvalid , \n output wire awready , \n\n // MC Master Interface\n //CMD PORT\n output wire cmd_en , \n output wire cmd_en_last ,\n output wire [2:0] cmd_instr , \n output wire [C_MC_ADDR_WIDTH-1:0] cmd_byte_addr , \n input wire cmd_full ,\n\n // Connections to/from axi_mc_w_channel module\n input wire w_data_rdy ,\n input wire cmd_wr_bytes ,\n output wire w_cmd_rdy ,\n output wire w_ignore_begin ,\n output wire w_ignore_end ,\n output wire awvalid_int ,\n output wire [3:0] awqos_int ,\n \n\n // Connections to/from axi_mc_b_channel module\n output wire b_push , \n output wire [C_ID_WIDTH-1:0] b_awid ,\n input wire b_full \n\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam P_CMD_WRITE = 3'b000;\nlocalparam P_CMD_READ = 3'b001;\nlocalparam P_CMD_WRITE_BYTES = 3'b011;\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nwire next ;\nwire next_pending ;\n\nreg [C_ID_WIDTH-1:0] axid ;\nreg [C_AXI_ADDR_WIDTH-1:0] axaddr ;\nreg [7:0] axlen ;\nreg [3:0] axqos ;\nreg [1:0] axburst ;\nreg axvalid ;\n\nwire [C_ID_WIDTH-1:0] axid_int ;\nwire [C_AXI_ADDR_WIDTH-1:0] axaddr_int ;\nwire [7:0] axlen_int ;\nwire [3:0] axqos_int ;\nwire [1:0] axburst_int ;\nwire axvalid_int ;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\nassign awvalid_int = axvalid_int;\nassign awqos_int = axqos_int;\n\nassign axid_int = awready ? awid : axid;\nassign axlen_int = awready ? awlen : axlen;\nassign axqos_int = awready ? awqos : axqos;\nassign axaddr_int = awready ? awaddr : axaddr;\nassign axburst_int = awready ? awburst : axburst;\nassign axvalid_int = awready ? awvalid : axvalid;\n\nalways @(posedge clk) begin\n if(reset)\n axvalid <= 1'b0;\n else\n axvalid <= axvalid_int;\nend\n\nalways @(posedge clk) begin\n axid <= axid_int;\n axlen <= axlen_int;\n axqos <= axqos_int;\n axaddr <= axaddr_int;\n axburst <= axburst_int;\nend\n\n// Translate the AXI transaction to the MC transaction(s)\nmig_7series_v4_0_axi_mc_cmd_translator #\n(\n .C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,\n .C_MC_ADDR_WIDTH ( C_MC_ADDR_WIDTH ) ,\n .C_DATA_WIDTH ( C_DATA_WIDTH ) ,\n .C_MC_BURST_LEN ( C_MC_BURST_LEN ) ,\n .C_MC_nCK_PER_CLK ( C_MC_nCK_PER_CLK ) ,\n .C_AXSIZE ( C_AXSIZE ) ,\n .C_MC_RD_INST ( 0 )\n)\naxi_mc_cmd_translator_0\n(\n .clk ( clk ) ,\n .reset ( reset ) ,\n .axaddr ( axaddr_int ) ,\n .axlen ( axlen_int ) ,\n .axsize ( awsize ) , // This is a constant, need not be sampled. Fed the direct input to aviod timing violations.\n .axburst ( axburst_int ) ,\n .axvalid ( axvalid_int ) ,\n .axready ( awready ) ,\n .cmd_byte_addr ( cmd_byte_addr ) ,\n .ignore_begin ( w_ignore_begin ) ,\n .ignore_end ( w_ignore_end ) ,\n .next ( next ) ,\n .next_pending ( next_pending ) \n);\n\nmig_7series_v4_0_axi_mc_wr_cmd_fsm #\n(\n .C_MC_BURST_LEN (C_MC_BURST_LEN ),\n .C_MC_RD_INST (0 )\n)\naw_cmd_fsm_0\n(\n .clk ( clk ) ,\n .reset ( reset ) ,\n .axready ( awready ) ,\n .axvalid ( axvalid_int ) ,\n .cmd_en ( cmd_en ) ,\n .cmd_full ( cmd_full ) ,\n .next ( next ) ,\n .next_pending ( next_pending ) ,\n .data_rdy ( w_data_rdy ) ,\n .b_push ( b_push ) ,\n .b_full ( b_full ) ,\n .cmd_en_last ( cmd_en_last )\n);\n\n// assign cmd_instr = (C_ECC == \"ON\") ? P_CMD_WRITE_BYTES : P_CMD_WRITE;\nassign cmd_instr = ((C_ECC == \"ON\") & cmd_wr_bytes) ? P_CMD_WRITE_BYTES : P_CMD_WRITE;\n\nassign b_awid = axid_int;\n\nassign w_cmd_rdy = next;\n\nendmodule\n\n`default_nettype wire\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_b_channel.v", "content": "// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. \n// -- \n// -- This file contains confidential and proprietary information \n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property \n// -- laws. \n// -- \n// -- DISCLAIMER \n// -- This disclaimer is not a license and does not grant any \n// -- rights to the materials distributed herewith. Except as \n// -- otherwise provided in a valid license issued to you by \n// -- Xilinx, and to the maximum extent permitted by applicable \n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND \n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES \n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING \n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- \n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and \n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of \n// -- liability) for any loss or damage of any kind or nature \n// -- related to, arising under or in connection with these \n// -- materials, including for any direct, or any indirect, \n// -- special, incidental, or consequential loss or damage \n// -- (including loss of data, profits, goodwill, or any type of \n// -- loss or damage suffered as a result of any action brought \n// -- by a third party) even if such damage or loss was \n// -- reasonably foreseeable or Xilinx had been advised of the \n// -- possibility of the same. \n// -- \n// -- CRITICAL APPLICATIONS \n// -- Xilinx products are not designed or intended to be fail- \n// -- safe, or for use in any application requiring fail-safe \n// -- performance, such as life-support or safety devices or \n// -- systems, Class III medical devices, nuclear facilities, \n// -- applications related to the deployment of airbags, or any \n// -- other applications that could lead to death, personal \n// -- injury, or severe property or environmental damage \n// -- (individually and collectively, \"Critical \n// -- Applications\"). Customer assumes the sole risk and \n// -- liability of any use of Xilinx products in Critical \n// -- Applications, subject only to applicable laws and \n// -- regulations governing limitations on product liability. \n// -- \n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS \n// -- PART OF THIS FILE AT ALL TIMES. \n// -- \n///////////////////////////////////////////////////////////////////////////////\n//\n// File name: axi_mc_b_channel.v\n//\n// Description: \n// This module is responsible for returning the write response to the master\n// that initiated the write. The write address channel module will push the\n// transaction ID into a FIFO in the write response module after the\n// completion of the address write phase of the transaction. If strict\n// coherency is enabled (C_STRICT_COHERENCY == 1), then this module will\n// monitor the MCB command/write FIFOs to determine when to send back the\n// response. It will not send the response until it is guaranteed that the\n// write has been committed completely to memory.\n// \n// ERROR RESPONSE\n// If the MCB write channel indicates there is an error or write FIFO under\n// run then the AXI SLVERR response is returned otherwise the OKAY response\n// is returned.\n//\n// WRITE COHERENCY CHECKING\n// The MCB hard block can have up to 6 independent ports to memory. If the\n// MCB block is configured as single port or as multi-port with separate\n// regions then write coherency logic is not required. In all other cases,\n// once a transaction has been sent to the MCB CMD channel, it is not\n// guaranteed that it will commit to memory before a transaction on another\n// port. To ensure that the response is only sent after the data has been\n// written to external memory the write response will not be sent until\n// either the write data FIFO is empty or that the command FIFO is empty.\n//\n// Assertions: \n// 1. Standard FIFO assertions on bid_fifo_0.\n// 2. bvalid == 0, when C_STRICT_COHERENCY == 1 and mcb_empty == 0.\n///////////////////////////////////////////////////////////////////////////////\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule mig_7series_v4_0_axi_mc_b_channel #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n // Width of ID signals.\n // Range: >= 1.\n parameter integer C_ID_WIDTH = 4 \n \n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations \n///////////////////////////////////////////////////////////////////////////////\n input wire clk,\n input wire reset,\n\n // AXI signals\n output wire [C_ID_WIDTH-1:0] bid,\n output wire [1:0] bresp,\n output wire bvalid,\n input wire bready,\n\n // Signals to/from the axi_mc_aw_channel modules\n input wire b_push,\n input wire [C_ID_WIDTH-1:0] b_awid,\n input wire b_resp_rdy,\n output wire b_full\n\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n// FIFO settings\nlocalparam P_WIDTH = C_ID_WIDTH;\nlocalparam P_DEPTH = 8;\nlocalparam P_AWIDTH = 3;\n// AXI protocol responses:\nlocalparam P_OKAY = 2'b00;\nlocalparam P_EXOKAY = 2'b01;\nlocalparam P_SLVERR = 2'b10;\nlocalparam P_DECERR = 2'b11;\n\nlocalparam B_RESP_PERF = 1'b1; \t// Set to 1 to increase the write response performance for back to back single beats.\n\t\t\t\t// Set to 0 in case of timing issues, but performance degrades for back to back single beats.\nwire empty;\nwire bhandshake;\nwire [C_ID_WIDTH-1:0] bid_i;\n\nreg b_pop;\nreg bvalid_i;\nreg [C_ID_WIDTH-1:0] bid_t;\n\nassign bresp = P_OKAY;\n\ngenerate\n if (B_RESP_PERF == 1) begin\n \n assign bid = bid_t;\n assign bvalid = bvalid_i;\n assign bhandshake = ~bvalid | bready;\n \n always @(*)\n b_pop = bhandshake & ~empty;\n \n always @(posedge clk) begin\n if(reset) begin\n bid_t <= 'b0;\n bvalid_i <= 1'b0;\n end else if(bhandshake) begin\n bid_t <= bid_i;\n bvalid_i <= ~empty;\n end\n end\n \n end else begin // B_RESP_PERF\n \n assign bid = bid_i;\n assign bvalid = bvalid_i;\n assign bhandshake = bvalid & bready;\n \n always @(posedge clk)\n b_pop <= bhandshake;\n \n always @(posedge clk) begin\n if (reset | bhandshake) begin\n bvalid_i <= 1'b0;\n end else if (~empty & (~b_pop)) begin\n bvalid_i <= 1'b1;\n end\n end\n \n end // B_RESP_PERF\nendgenerate\n\nmig_7series_v4_0_axi_mc_fifo #\n (\n .C_WIDTH (P_WIDTH),\n .C_AWIDTH (P_AWIDTH),\n .C_DEPTH (P_DEPTH)\n)\nbid_fifo_0\n(\n .clk ( clk ) ,\n .rst ( reset ) ,\n .wr_en ( b_push ) ,\n .rd_en ( b_pop ) ,\n .din ( b_awid ) ,\n .dout ( bid_i ) ,\n .a_full ( ) ,\n .full ( b_full ) ,\n .a_empty ( ) ,\n .empty ( empty ) \n);\n\nendmodule\n\n`default_nettype wire\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_cmd_arbiter.v", "content": "// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. \n// -- \n// -- This file contains confidential and proprietary information \n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property \n// -- laws. \n// -- \n// -- DISCLAIMER \n// -- This disclaimer is not a license and does not grant any \n// -- rights to the materials distributed herewith. Except as \n// -- otherwise provided in a valid license issued to you by \n// -- Xilinx, and to the maximum extent permitted by applicable \n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND \n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES \n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING \n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- \n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and \n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of \n// -- liability) for any loss or damage of any kind or nature \n// -- related to, arising under or in connection with these \n// -- materials, including for any direct, or any indirect, \n// -- special, incidental, or consequential loss or damage \n// -- (including loss of data, profits, goodwill, or any type of \n// -- loss or damage suffered as a result of any action brought \n// -- by a third party) even if such damage or loss was \n// -- reasonably foreseeable or Xilinx had been advised of the \n// -- possibility of the same. \n// -- \n// -- CRITICAL APPLICATIONS \n// -- Xilinx products are not designed or intended to be fail- \n// -- safe, or for use in any application requiring fail-safe \n// -- performance, such as life-support or safety devices or \n// -- systems, Class III medical devices, nuclear facilities, \n// -- applications related to the deployment of airbags, or any \n// -- other applications that could lead to death, personal \n// -- injury, or severe property or environmental damage \n// -- (individually and collectively, \"Critical \n// -- Applications\"). Customer assumes the sole risk and \n// -- liability of any use of Xilinx products in Critical \n// -- Applications, subject only to applicable laws and \n// -- regulations governing limitations on product liability. \n// -- \n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS \n// -- PART OF THIS FILE AT ALL TIMES. \n// -- \n///////////////////////////////////////////////////////////////////////////////\n//\n// File name: axi_mc_cmd_arbiter.v\n//\n// Description: \n// This arbiter arbitrates commands from the read and write address channels\n// of AXI to the single CMD channel of the MC interface. The inputs are the\n// read and write commands that have already been translated to the MC\n// format.\n//\n///////////////////////////////////////////////////////////////////////////////\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule mig_7series_v4_0_axi_mc_cmd_arbiter #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n // Width of cmd_byte_addr\n // Range: 30\n parameter integer C_MC_ADDR_WIDTH = 30,\n \n // write command starve limit in read priority reg mode\n // MC burst length. = 1 for BL4 or BC4, = 2 for BL8\n parameter integer C_MC_BURST_LEN = 1,\n parameter integer C_AXI_WR_STARVE_LIMIT = 256,\n // log2 of C_AXI_WR_STARVE_LIMIT ceil (log2(C_AXI_WR_STARVE_LIMIT))\n parameter integer C_AXI_STARVE_CNT_WIDTH = 8,\n parameter C_RD_WR_ARB_ALGORITHM = \"RD_PRI_REG\"\n // Indicates the Arbitration\n // Allowed values - \"TDM\", \"ROUND_ROBIN\",\n // \"RD_PRI_REG\", \"RD_PRI_REG_STARVE_LIMIT\"\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations \n///////////////////////////////////////////////////////////////////////////////\n // AXI Slave Interface\n // Slave Interface System Signals \n input wire clk , \n input wire reset , \n\n input wire awvalid ,\n input wire [3:0] awqos ,\n input wire wr_cmd_en , \n input wire wr_cmd_en_last ,\n input wire [2:0] wr_cmd_instr , \n input wire [C_MC_ADDR_WIDTH-1:0] wr_cmd_byte_addr , \n output wire wr_cmd_full , \n\n input wire arvalid ,\n input wire [3:0] arqos ,\n input wire rd_cmd_en , \n input wire rd_cmd_en_last ,\n input wire [2:0] rd_cmd_instr , \n input wire [C_MC_ADDR_WIDTH-1:0] rd_cmd_byte_addr , \n output wire rd_cmd_full , \n\n output wire mc_app_en , \n output wire [2:0] mc_app_cmd , \n output wire mc_app_size , \n output wire [C_MC_ADDR_WIDTH-1:0] mc_app_addr ,\n output wire mc_app_hi_pri , \n input wire mc_app_rdy\n\n);\n\n\n\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\n\nwire rnw;\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\nassign mc_app_en = rnw ? rd_cmd_en : wr_cmd_en;\nassign mc_app_cmd = rnw ? rd_cmd_instr : wr_cmd_instr;\nassign mc_app_addr = rnw ? rd_cmd_byte_addr : wr_cmd_byte_addr;\nassign mc_app_size = 1'b0; \nassign wr_cmd_full = rnw ? 1'b1 : ~mc_app_rdy;\nassign rd_cmd_full = ~rnw ? 1'b1 : ~mc_app_rdy;\nassign mc_app_hi_pri = 1'b0;\n \n \n\ngenerate\n // TDM Arbitration scheme\n if (C_RD_WR_ARB_ALGORITHM == \"TDM\") begin : TDM\n reg rnw_i;\n always @(posedge clk) begin\n if (reset) begin\n rnw_i <= 1'b0;\n end else begin\n rnw_i <= ~rnw_i;\n end\n end\n assign rnw = rnw_i;\n end\n else if (C_RD_WR_ARB_ALGORITHM == \"ROUND_ROBIN\") begin : ROUND_ROBIN\n reg rnw_i;\n always @(posedge clk) begin\n if (reset) begin\n rnw_i <= 1'b0;\n end else begin\n rnw_i <= ~rnw;\n end\n end\n assign rnw = (rnw_i & rd_cmd_en) | (~rnw_i & rd_cmd_en & ~wr_cmd_en);\n end\n else if (C_RD_WR_ARB_ALGORITHM == \"RD_PRI_REG\") begin : RD_PRI_REG\n reg rnw_i;\n reg rd_cmd_hold;\n reg wr_cmd_hold;\n reg [4:0] rd_wait_limit;\n reg [4:0] wr_wait_limit;\n reg [9:0] rd_starve_cnt;\n reg [9:0] wr_starve_cnt;\n\n always @(posedge clk) begin\n if (~rnw | ~rd_cmd_hold) begin\n rd_wait_limit <= 5'b0;\n rd_starve_cnt <= (C_MC_BURST_LEN * 2);\n end else if (mc_app_rdy) begin\n if (~arvalid | rd_cmd_en)\n rd_wait_limit <= 5'b0;\n else\n rd_wait_limit <= rd_wait_limit + C_MC_BURST_LEN;\n\n if (rd_cmd_en & ~rd_starve_cnt[8])\n rd_starve_cnt <= rd_starve_cnt + C_MC_BURST_LEN;\n end\n end\n\n always @(posedge clk) begin\n if (rnw | ~wr_cmd_hold) begin\n wr_wait_limit <= 5'b0;\n wr_starve_cnt <= (C_MC_BURST_LEN * 2);\n end else if (mc_app_rdy) begin\n if (~awvalid | wr_cmd_en)\n wr_wait_limit <= 5'b0;\n else\n wr_wait_limit <= wr_wait_limit + C_MC_BURST_LEN;\n\n if (wr_cmd_en & ~wr_starve_cnt[8])\n wr_starve_cnt <= wr_starve_cnt + C_MC_BURST_LEN;\n end\n end\n always @(posedge clk) begin\n if (reset) begin\n rd_cmd_hold <= 1'b0;\n wr_cmd_hold <= 1'b0;\n end else begin\n rd_cmd_hold <= (rnw | rd_cmd_hold) & ~(rd_cmd_en_last & ((awvalid & (|awqos)) | rd_starve_cnt[8])) & ~rd_wait_limit[4];\n wr_cmd_hold <= (~rnw | wr_cmd_hold) & ~(wr_cmd_en_last & ((arvalid & (|arqos)) | wr_starve_cnt[8])) & ~wr_wait_limit[4];\n end\n end\n\n always @(posedge clk) begin\n if (reset)\n rnw_i <= 1'b1;\n else\n rnw_i <= rnw;\n end\n assign rnw = (rnw_i & ~(rd_cmd_hold & arvalid) & awvalid) ? 1'b0 : // RD -> WR\n (~rnw_i & ~(wr_cmd_hold & awvalid) & arvalid) ? 1'b1 : // WR -> RD\n rnw_i;\n end // block: RD_PRI_REG\n else if (C_RD_WR_ARB_ALGORITHM == \"RD_PRI_REG_STARVE_LIMIT\") begin : RD_PRI_REG_STARVE\n reg rnw_i;\n reg rd_cmd_en_d1;\n reg wr_cmd_en_d1;\n reg [C_AXI_STARVE_CNT_WIDTH-1:0] wr_starve_cnt;\n reg wr_enable;\n reg [8:0] rd_starve_cnt;\n\n // write starve count logic.\n // wr_enable to give priority to write commands will be set\n // when the write commands have been starved till the starve\n // limit. The wr_enable will be de-asserted when the pending write\n // command is processed or if the rd has been starved for 256 clock\n // cycles. \n always @(posedge clk) begin\n if(reset | ( ~(wr_cmd_en | wr_cmd_en_d1))\n | rd_starve_cnt[8])begin\n wr_starve_cnt <= 'b0;\n wr_enable <= 'b0;\n end else if(wr_cmd_en & (mc_app_rdy)) begin \n if(wr_starve_cnt < (C_AXI_WR_STARVE_LIMIT-1))\n wr_starve_cnt <= wr_starve_cnt + rnw_i;\n else\n wr_enable <= 1'b1;\n end // if (wr_cmd_en & (mc_app_rdy)\n end // always @ (posedge clk)\n\n // The rd command should not be starved for ever in this mode.\n // The maximum the read will starve is 256 clocks. \n always @(posedge clk) begin\n if(reset | rnw_i)begin\n rd_starve_cnt <= 'b0;\n end else if(rd_cmd_en & (mc_app_rdy)) begin \n rd_starve_cnt <= rd_starve_cnt + 1;\n end // if (wr_cmd_en & (mc_app_rdy)\n end // always @ (posedge clk) \n\n always @(posedge clk) begin\n if (reset) begin\n rd_cmd_en_d1 <= 1'b0;\n wr_cmd_en_d1 <= 1'b0;\n end else begin\n if (mc_app_rdy) begin\n rd_cmd_en_d1 <= rd_cmd_en & rnw;\n wr_cmd_en_d1 <= wr_cmd_en & ~rnw;\n end\n end\n end\n always @(posedge clk) begin\n if (reset) begin\n rnw_i <= 1'b1;\n end else begin\n // Only set RNW to 0 if there is a write pending and read is idle\n // rnw_i <= ~((wr_cmd_en | wr_cmd_en_d1) & (~rd_cmd_en) & (~rd_cmd_en_d1));\n rnw_i <= ~(((wr_cmd_en | wr_cmd_en_d1) & (~rd_cmd_en) & (~rd_cmd_en_d1)) | wr_enable);\n end\n end\n assign rnw = rnw_i;\n end\n else if (C_RD_WR_ARB_ALGORITHM == \"RD_PRI\") begin : RD_PRI\n assign rnw = ~(wr_cmd_en & ~rd_cmd_en);\n end\n else if (C_RD_WR_ARB_ALGORITHM == \"WR_PR_REG\") begin : WR_PR_REG\n reg rnw_i;\n always @(posedge clk) begin\n if (reset) begin\n rnw_i <= 1'b0;\n end else begin\n // Only set RNW to 1 if there is a read pending and write is idle\n // rnw_i <= (~wr_cmd_en & rd_cmd_en);\n rnw_i <= (~awvalid & arvalid);\n end\n end\n assign rnw = rnw_i;\n end\n else begin : WR_PR // if (C_RD_WR_ARB_ALGORITHM == \"WR_PR\") begin\n // assign rnw = (~wr_cmd_en & rd_cmd_en);\n assign rnw = (~awvalid & arvalid);\n end\nendgenerate\n\nendmodule\n`default_nettype wire\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_cmd_fsm.v", "content": "// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. \n// -- \n// -- This file contains confidential and proprietary information \n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property \n// -- laws. \n// -- \n// -- DISCLAIMER \n// -- This disclaimer is not a license and does not grant any \n// -- rights to the materials distributed herewith. Except as \n// -- otherwise provided in a valid license issued to you by \n// -- Xilinx, and to the maximum extent permitted by applicable \n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND \n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES \n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING \n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- \n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and \n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of \n// -- liability) for any loss or damage of any kind or nature \n// -- related to, arising under or in connection with these \n// -- materials, including for any direct, or any indirect, \n// -- special, incidental, or consequential loss or damage \n// -- (including loss of data, profits, goodwill, or any type of \n// -- loss or damage suffered as a result of any action brought \n// -- by a third party) even if such damage or loss was \n// -- reasonably foreseeable or Xilinx had been advised of the \n// -- possibility of the same. \n// -- \n// -- CRITICAL APPLICATIONS \n// -- Xilinx products are not designed or intended to be fail- \n// -- safe, or for use in any application requiring fail-safe \n// -- performance, such as life-support or safety devices or \n// -- systems, Class III medical devices, nuclear facilities, \n// -- applications related to the deployment of airbags, or any \n// -- other applications that could lead to death, personal \n// -- injury, or severe property or environmental damage \n// -- (individually and collectively, \"Critical \n// -- Applications\"). Customer assumes the sole risk and \n// -- liability of any use of Xilinx products in Critical \n// -- Applications, subject only to applicable laws and \n// -- regulations governing limitations on product liability. \n// -- \n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS \n// -- PART OF THIS FILE AT ALL TIMES. \n// -- \n///////////////////////////////////////////////////////////////////////////////\n//\n// File name: axi_mc_cmd_fsm.v\n//\n// Description: \n// Simple state machine to handle sending commands from AXI to MC. The flow:\n// 1. A transaction can only be initiaited when axvalid is true and data_rdy\n// is true. For writes, data_rdy means that one completed BL8 or BL4 write \n// data has been pushed into the MC write FIFOs. For read operations,\n// data_rdy indicates that there is enough room to push the transaction into\n// the read FIF & read transaction fifo in the shim. If the FIFO's in the \n// read channel module is full, then the state machine waits for the \n// FIFO's to drain out. \n//\n// 2. When CMD_EN is asserted, it remains high until we sample CMD_FULL in\n// a low state. When CMD_EN == 1'b1, and CMD_FULL == 1'b0, then the command\n// has been accepted. When the command is accepted, if the next_pending\n// signal is high we will incremented to the next transaction and issue the\n// cmd_en again when data_rdy is high. Otherwise we will go to the done\n// state.\n//\n///////////////////////////////////////////////////////////////////////////////\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule mig_7series_v4_0_axi_mc_cmd_fsm #(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n // MC burst length. = 1 for BL4 or BC4, = 2 for BL8\n parameter integer C_MC_BURST_LEN = 1,\n // parameter to identify rd or wr instantation\n // = 1 rd , = 0 wr \n parameter integer C_MC_RD_INST = 0\n \n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations \n///////////////////////////////////////////////////////////////////////////////\n input wire clk , \n input wire reset , \n output reg axready , \n input wire axvalid , \n output wire cmd_en , \n input wire cmd_full , \n // signal to increment to the next mc transaction \n output wire next , \n // signal to the fsm there is another transaction required\n input wire next_pending ,\n // Write Data portion has completed or Read FIFO has a slot available (not\n // full)\n input wire data_rdy ,\n // status signal for w_channel when command is written. \n output wire cmd_en_last \n);\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n///////////////////////////////////////////////////////////////////////////////\n assign cmd_en = (axvalid & data_rdy);\n\n assign next = (~cmd_full & cmd_en);\n\n assign cmd_en_last = next & ~next_pending;\n\n always @(posedge clk) begin\n if (reset)\n axready <= 1'b0;\n else\n axready <= ~axvalid | cmd_en_last;\n end\n\nendmodule\n`default_nettype wire\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_cmd_translator.v", "content": "// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. \n// -- \n// -- This file contains confidential and proprietary information \n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property \n// -- laws. \n// -- \n// -- DISCLAIMER \n// -- This disclaimer is not a license and does not grant any \n// -- rights to the materials distributed herewith. Except as \n// -- otherwise provided in a valid license issued to you by \n// -- Xilinx, and to the maximum extent permitted by applicable \n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND \n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES \n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING \n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- \n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and \n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of \n// -- liability) for any loss or damage of any kind or nature \n// -- related to, arising under or in connection with these \n// -- materials, including for any direct, or any indirect, \n// -- special, incidental, or consequential loss or damage \n// -- (including loss of data, profits, goodwill, or any type of \n// -- loss or damage suffered as a result of any action brought \n// -- by a third party) even if such damage or loss was \n// -- reasonably foreseeable or Xilinx had been advised of the \n// -- possibility of the same. \n// -- \n// -- CRITICAL APPLICATIONS \n// -- Xilinx products are not designed or intended to be fail- \n// -- safe, or for use in any application requiring fail-safe \n// -- performance, such as life-support or safety devices or \n// -- systems, Class III medical devices, nuclear facilities, \n// -- applications related to the deployment of airbags, or any \n// -- other applications that could lead to death, personal \n// -- injury, or severe property or environmental damage \n// -- (individually and collectively, \"Critical \n// -- Applications\"). Customer assumes the sole risk and \n// -- liability of any use of Xilinx products in Critical \n// -- Applications, subject only to applicable laws and \n// -- regulations governing limitations on product liability. \n// -- \n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS \n// -- PART OF THIS FILE AT ALL TIMES. \n// -- \n///////////////////////////////////////////////////////////////////////////////\n//\n// File name: axi_mc_cmd_translator.v\n//\n// Description: \n// INCR and WRAP burst modes are decoded in parallel and then the output is\n// chosen based on the AxBURST value. FIXED burst mode is not supported and\n// is mapped to the INCR command instead. \n//\n// Specifications:\n//\n///////////////////////////////////////////////////////////////////////////////\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule mig_7series_v4_0_axi_mc_cmd_translator #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n // Width of AxADDR\n // Range: 32.\n parameter integer C_AXI_ADDR_WIDTH = 32, \n // Width of cmd_byte_addr\n // Range: 30\n parameter integer C_MC_ADDR_WIDTH = 30,\n // Width of AXI xDATA and MC xx_data\n // Range: 32, 64, 128.\n parameter integer C_DATA_WIDTH = 32,\n // MC burst length. = 1 for BL4 or BC4, = 2 for BL8\n parameter integer C_MC_BURST_LEN = 1,\n // DRAM clock to AXI clock ratio\n // supported values 2, 4\n parameter integer C_MC_nCK_PER_CLK = 2, \n // Static value of axsize\n // Range: 2-5\n parameter integer C_AXSIZE = 2,\n // Instance for Read channel or write channel\n parameter integer C_MC_RD_INST = 0\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations \n///////////////////////////////////////////////////////////////////////////////\n input wire clk , \n input wire reset , \n input wire [C_AXI_ADDR_WIDTH-1:0] axaddr , \n input wire [7:0] axlen , \n input wire [2:0] axsize , \n input wire [1:0] axburst , \n input wire axvalid , \n input wire axready , \n output wire [C_MC_ADDR_WIDTH-1:0] cmd_byte_addr , \n output wire ignore_begin ,\n output wire ignore_end ,\n\n // Connections to/from fsm module\n // signal to increment to the next mc transaction \n input wire next , \n // signal to the fsm there is another transaction required\n output wire next_pending\n\n\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam P_MC_BURST_MASK = {C_MC_ADDR_WIDTH{1'b1}} ^ \n {C_MC_BURST_LEN+(C_MC_nCK_PER_CLK/2){1'b1}};\n////////////////////////////////////////////////////////////////////////////////\n// Wires/Reg declarations\n////////////////////////////////////////////////////////////////////////////////\nwire [C_AXI_ADDR_WIDTH-1:0] cmd_byte_addr_i;\n\nwire [C_AXI_ADDR_WIDTH-1:0] axi_mc_incr_cmd_byte_addr;\nwire incr_next_pending;\nwire [C_AXI_ADDR_WIDTH-1:0] axi_mc_wrap_cmd_byte_addr;\nwire wrap_next_pending;\nwire incr_ignore_begin;\nwire incr_ignore_end;\nwire wrap_ignore_begin;\nwire wrap_ignore_end; \nwire axhandshake;\nwire incr_axhandshake;\nwire wrap_axhandshake;\nwire incr_next;\nwire wrap_next;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\nassign axhandshake = axvalid & axready;\n\n// INCR and WRAP translations are calcuated in independently, select the one\n// for our transactions\n// right shift by the UI width to the DRAM width ratio \n \nassign cmd_byte_addr = (C_MC_nCK_PER_CLK == 4) ?\n (cmd_byte_addr_i >> C_AXSIZE-3) & P_MC_BURST_MASK : \n (cmd_byte_addr_i >> C_AXSIZE-2) & P_MC_BURST_MASK;\n\nassign cmd_byte_addr_i = (axburst[1]) ? axi_mc_wrap_cmd_byte_addr : axi_mc_incr_cmd_byte_addr;\n\nassign ignore_begin = (axburst[1]) ? wrap_ignore_begin : incr_ignore_begin;\n\nassign ignore_end = (axburst[1]) ? wrap_ignore_end : incr_ignore_end;\n\nassign next_pending = (axburst[1]) ? wrap_next_pending : incr_next_pending;\n\nassign incr_axhandshake = (axburst[1]) ? 1'b0 : axhandshake;\n\nassign wrap_axhandshake = (axburst[1]) ? axhandshake : 1'b0;\n\nassign incr_next = (axburst[1]) ? 1'b0 : next;\n\nassign wrap_next = (axburst[1]) ? next : 1'b0;\n\nmig_7series_v4_0_axi_mc_incr_cmd #\n(\n .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),\n .C_MC_ADDR_WIDTH (C_MC_ADDR_WIDTH),\n .C_DATA_WIDTH (C_DATA_WIDTH),\n .C_MC_BURST_LEN (C_MC_BURST_LEN),\n .C_AXSIZE (C_AXSIZE),\n .C_MC_RD_INST (C_MC_RD_INST)\n)\naxi_mc_incr_cmd_0\n(\n .clk ( clk ) ,\n .reset ( reset ) ,\n .axaddr ( axaddr ) ,\n .axlen ( axlen ) ,\n .axsize ( axsize ) ,\n .axhandshake ( incr_axhandshake ) ,\n .cmd_byte_addr ( axi_mc_incr_cmd_byte_addr ) ,\n .ignore_begin ( incr_ignore_begin ) ,\n .ignore_end ( incr_ignore_end ) ,\n .next ( incr_next ) ,\n .next_pending ( incr_next_pending ) \n);\n\nmig_7series_v4_0_axi_mc_wrap_cmd #\n(\n .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),\n .C_MC_ADDR_WIDTH (C_MC_ADDR_WIDTH),\n .C_MC_BURST_LEN (C_MC_BURST_LEN),\n .C_DATA_WIDTH (C_DATA_WIDTH),\n .C_AXSIZE (C_AXSIZE),\n .C_MC_RD_INST (C_MC_RD_INST)\n)\naxi_mc_wrap_cmd_0\n(\n .clk ( clk ) ,\n .reset ( reset ) ,\n .axaddr ( axaddr ) ,\n .axlen ( axlen ) ,\n .axsize ( axsize ) ,\n .axhandshake ( wrap_axhandshake ) ,\n .ignore_begin ( wrap_ignore_begin ) ,\n .ignore_end ( wrap_ignore_end ) ,\n .cmd_byte_addr ( axi_mc_wrap_cmd_byte_addr ) ,\n .next ( wrap_next ) ,\n .next_pending ( wrap_next_pending ) \n);\n\nendmodule\n`default_nettype wire\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_fifo.v", "content": "//-----------------------------------------------------------------------------\n//-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.\n//--\n//-- This file contains confidential and proprietary information\n//-- of Xilinx, Inc. and is protected under U.S. and\n//-- international copyright and other intellectual property\n//-- laws.\n//--\n//-- DISCLAIMER\n//-- This disclaimer is not a license and does not grant any\n//-- rights to the materials distributed herewith. Except as\n//-- otherwise provided in a valid license issued to you by\n//-- Xilinx, and to the maximum extent permitted by applicable\n//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//-- (2) Xilinx shall not be liable (whether in contract or tort,\n//-- including negligence, or under any other theory of\n//-- liability) for any loss or damage of any kind or nature\n//-- related to, arising under or in connection with these\n//-- materials, including for any direct, or any indirect,\n//-- special, incidental, or consequential loss or damage\n//-- (including loss of data, profits, goodwill, or any type of\n//-- loss or damage suffered as a result of any action brought\n//-- by a third party) even if such damage or loss was\n//-- reasonably foreseeable or Xilinx had been advised of the\n//-- possibility of the same.\n//--\n//-- CRITICAL APPLICATIONS\n//-- Xilinx products are not designed or intended to be fail-\n//-- safe, or for use in any application requiring fail-safe\n//-- performance, such as life-support or safety devices or\n//-- systems, Class III medical devices, nuclear facilities,\n//-- applications related to the deployment of airbags, or any\n//-- other applications that could lead to death, personal\n//-- injury, or severe property or environmental damage\n//-- (individually and collectively, \"Critical\n//-- Applications\"). Customer assumes the sole risk and\n//-- liability of any use of Xilinx products in Critical\n//-- Applications, subject only to applicable laws and\n//-- regulations governing limitations on product liability.\n//--\n//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//-- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//Purpose:\n// Synchronous, shallow FIFO that uses simple as a DP Memory.\n// This requires about 1/2 the resources as a Distributed RAM DPRAM \n// implementation.\n//\n// This FIFO will have the current data on the output when data is contained\n// in the FIFO. When the FIFO is empty, the output data is invalid.\n//\n//Reference:\n//Revision History:\n//\n//-----------------------------------------------\n//\n// MODULE: axi_mc_fifo\n//\n// This is the simplest form of inferring the\n// simple/SRL(16/32)CE in a Xilinx FPGA.\n//\n//-----------------------------------------------\n`timescale 1ns / 100ps\n`default_nettype none\n\nmodule mig_7series_v4_0_axi_mc_fifo #\n(\n parameter C_WIDTH = 8,\n parameter C_AWIDTH = 4,\n parameter C_DEPTH = 16\n)\n(\n input wire clk, // Main System Clock (Sync FIFO)\n input wire rst, // FIFO Counter Reset (Clk\n input wire wr_en, // FIFO Write Enable (Clk)\n input wire rd_en, // FIFO Read Enable (Clk)\n input wire [C_WIDTH-1:0] din, // FIFO Data Input (Clk)\n output wire [C_WIDTH-1:0] dout, // FIFO Data Output (Clk)\n output wire a_full,\n output wire full, // FIFO FULL Status (Clk)\n output wire a_empty,\n output wire empty // FIFO EMPTY Status (Clk)\n);\n\n///////////////////////////////////////\n// FIFO Local Parameters\n///////////////////////////////////////\nlocalparam [C_AWIDTH:0] C_EMPTY = ~(0);\nlocalparam [C_AWIDTH-1:0] C_EMPTY_PRE = 0;\nlocalparam [C_AWIDTH-1:0] C_FULL = C_DEPTH - 1;\nlocalparam [C_AWIDTH-1:0] C_FULL_PRE = C_DEPTH -2;\n \n///////////////////////////////////////\n// FIFO Internal Signals\n///////////////////////////////////////\nreg [C_WIDTH-1:0] memory [C_DEPTH-1:0];\nreg [C_AWIDTH:0] cnt_read;\nreg [C_AWIDTH:0] next_cnt_read;\n\nwire [C_AWIDTH:0] cnt_read_plus1;\nwire [C_AWIDTH:0] cnt_read_minus1;\nwire [C_AWIDTH-1:0] read_addr;\n\n///////////////////////////////////////\n// Main FIFO Array\n///////////////////////////////////////\nassign read_addr = cnt_read;\n\nassign dout = memory[read_addr];\n\nalways @(posedge clk) begin : BLKSRL\ninteger i;\n if (wr_en) begin\n for (i = 0; i < C_DEPTH-1; i = i + 1) begin\n memory[i+1] <= memory[i];\n end\n memory[0] <= din;\n end\nend\n\n///////////////////////////////////////\n// Read Index Counter\n// Up/Down Counter\n// *** Notice that there is no ***\n// *** OVERRUN protection. ***\n///////////////////////////////////////\nalways @(posedge clk) begin\n if (rst) cnt_read <= C_EMPTY;\n else cnt_read <= next_cnt_read;\nend\n\nassign cnt_read_plus1 = cnt_read + 1'b1;\nassign cnt_read_minus1 = cnt_read - 1'b1;\n\nalways @(*) begin\n next_cnt_read = cnt_read;\n if ( wr_en & !rd_en) next_cnt_read = cnt_read_plus1;\n else if (!wr_en & rd_en) next_cnt_read = cnt_read_minus1;\nend\n\n///////////////////////////////////////\n// Status Flags / Outputs\n// These could be registered, but would\n// increase logic in order to pre-decode\n// FULL/EMPTY status.\n///////////////////////////////////////\nassign full = (cnt_read == C_FULL);\nassign empty = (cnt_read == C_EMPTY);\nassign a_full = (cnt_read == C_FULL_PRE);\nassign a_empty = (cnt_read == C_EMPTY_PRE);\n\nendmodule // axi_mc_fifo\n\n`default_nettype wire\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_incr_cmd.v", "content": "// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. \n// -- \n// -- This file contains confidential and proprietary information \n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property \n// -- laws. \n// -- \n// -- DISCLAIMER \n// -- This disclaimer is not a license and does not grant any \n// -- rights to the materials distributed herewith. Except as \n// -- otherwise provided in a valid license issued to you by \n// -- Xilinx, and to the maximum extent permitted by applicable \n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND \n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES \n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING \n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- \n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and \n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of \n// -- liability) for any loss or damage of any kind or nature \n// -- related to, arising under or in connection with these \n// -- materials, including for any direct, or any indirect, \n// -- special, incidental, or consequential loss or damage \n// -- (including loss of data, profits, goodwill, or any type of \n// -- loss or damage suffered as a result of any action brought \n// -- by a third party) even if such damage or loss was \n// -- reasonably foreseeable or Xilinx had been advised of the \n// -- possibility of the same. \n// -- \n// -- CRITICAL APPLICATIONS \n// -- Xilinx products are not designed or intended to be fail- \n// -- safe, or for use in any application requiring fail-safe \n// -- performance, such as life-support or safety devices or \n// -- systems, Class III medical devices, nuclear facilities, \n// -- applications related to the deployment of airbags, or any \n// -- other applications that could lead to death, personal \n// -- injury, or severe property or environmental damage \n// -- (individually and collectively, \"Critical \n// -- Applications\"). Customer assumes the sole risk and \n// -- liability of any use of Xilinx products in Critical \n// -- Applications, subject only to applicable laws and \n// -- regulations governing limitations on product liability. \n// -- \n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS \n// -- PART OF THIS FILE AT ALL TIMES. \n// -- \n///////////////////////////////////////////////////////////////////////////////\n//\n// File name: axi_mc_incr_cmd.v\n//\n// Description: \n// MC does not support up to 256 beats per transaction to support an AXI INCR \n// command directly. Additionally for QOS purposes, larger transactions\n// issued as many smaller transactions should improve QoS for the system.\n// In the BL8 mode depending on the address offset ragged head or ragged tail\n// need to be inserted into the data stream for writes and ignored for reads.\n// In BL8 mode for transactions with odd length and even length transactions\n// with an address offset an extra BL8 transaction will be issued. \n///////////////////////////////////////////////////////////////////////////////\n\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule mig_7series_v4_0_axi_mc_incr_cmd #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n // Width of AxADDR\n // Range: 32.\n parameter integer C_AXI_ADDR_WIDTH = 32, \n // Width of cmd_byte_addr\n // Range: 30\n parameter integer C_MC_ADDR_WIDTH = 30,\n // MC burst length. = 1 for BL4 or BC4, = 2 for BL8\n parameter integer C_MC_BURST_LEN = 1,\n // Width of AXI xDATA and MC xx_data\n // Range: 32, 64, 128.\n parameter integer C_DATA_WIDTH = 32,\n // Static value of axsize\n // Range: 2-4\n parameter integer C_AXSIZE = 2,\n // Instance for Read channel or write channel\n parameter integer C_MC_RD_INST = 0\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations \n///////////////////////////////////////////////////////////////////////////////\n input wire clk , \n input wire reset , \n input wire [C_AXI_ADDR_WIDTH-1:0] axaddr , \n input wire [7:0] axlen , \n input wire [2:0] axsize , \n // axhandshake = axvalid & axready\n input wire axhandshake , \n output wire [C_AXI_ADDR_WIDTH-1:0] cmd_byte_addr ,\n output wire ignore_begin ,\n output wire ignore_end ,\n // Connections to/from fsm module\n // signal to increment to the next mc transaction \n input wire next , \n // signal to the fsm there is another transaction required\n output wire next_pending \n\n);\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam P_AXLEN_WIDTH = 8;\n////////////////////////////////////////////////////////////////////////////////\n// Wire and register declarations\n////////////////////////////////////////////////////////////////////////////////\nreg sel_first_r;\nreg [7:0] axlen_cnt;\nreg [C_AXI_ADDR_WIDTH-1:0] axaddr_incr;\nreg int_next_pending_r;\n\nwire sel_first;\nwire addr_offset;\nwire length_even;\nwire [7:0] axlen_cnt_t;\nwire [7:0] axlen_cnt_p;\nwire [7:0] axlen_cnt_i;\nwire [C_AXI_ADDR_WIDTH-1:0] axaddr_incr_t;\n(* keep = \"true\" *) reg [C_AXI_ADDR_WIDTH-1:0] axaddr_incr_p;\nwire [7:0] incr_cnt;\nwire int_next_pending;\nwire extra_cmd;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\nassign cmd_byte_addr = axaddr_incr_t;\n\ngenerate\n if(C_MC_BURST_LEN == 1) begin\n assign addr_offset = 1'b0;\n assign length_even = 1'b1;\n assign axaddr_incr_t = axhandshake ? axaddr : axaddr_incr;\n\n end else begin\n // Figuring out if the address have an offset for padding data in BL8 case\n assign addr_offset = axaddr[C_AXSIZE];\n // The length could be odd which is an issue in BL8\n assign length_even = axlen[0];\n\n if(C_MC_RD_INST == 0) // axhandshake & next won't occur in same cycle in Write channel 2:1 mode\n assign axaddr_incr_t = axaddr_incr;\n else\n assign axaddr_incr_t = axhandshake ? axaddr : axaddr_incr;\n end\nendgenerate\n\nalways @(*) begin\n axaddr_incr_p = axaddr_incr_t + (incr_cnt * C_MC_BURST_LEN);\nend\n\nalways @(posedge clk) begin\n if(reset)\n axaddr_incr <= {C_AXI_ADDR_WIDTH{1'b0}};\n else if (axhandshake & ~next)\n axaddr_incr <= axaddr;\n else if(next)\n axaddr_incr <= axaddr_incr_p;\nend\n\n// figuring out how much to much to incr based on AXSIZE\nassign incr_cnt = (C_AXSIZE == 2) ? 8'd4 : (C_AXSIZE == 3) ? 8'd8 :\n (C_AXSIZE == 4)? 8'd16 :(C_AXSIZE == 5) ? 8'd32 : \n (C_AXSIZE == 6) ? 8'd64 : (C_AXSIZE == 7) ? 8'd128 :8'd0;\n\n// assign axlen_cnt_i = (C_MC_BURST_LEN == 1) ? axlen : (extra_cmd ? ((axlen >> 1) + 1'b1) : (axlen >> 1));\nassign axlen_cnt_i = (C_MC_BURST_LEN == 1) ? axlen : (axlen >> 1);\n\nassign axlen_cnt_t = axhandshake ? axlen_cnt_i : axlen_cnt;\n\nassign axlen_cnt_p = (axlen_cnt_t - 1'b1);\n\nalways @(posedge clk) begin\n if(reset)\n axlen_cnt <= 4'hf;\n else if (axhandshake & ~next)\n axlen_cnt <= axlen_cnt_i;\n else if(next)\n axlen_cnt <= axlen_cnt_p;\nend \n\nassign extra_cmd = addr_offset & length_even;\n\nassign next_pending = extra_cmd ? int_next_pending_r : int_next_pending;\n\nassign int_next_pending = |axlen_cnt_t;\n\nalways @(posedge clk) begin\n if(reset)\n int_next_pending_r <= 1'b1;\n else if(extra_cmd & next)\n int_next_pending_r <= int_next_pending;\nend\n\n// last and ignore signals to data channel. These signals are used for\n// BL8 to ignore and insert data for even len transactions with offset\n// and odd len transactions\n// For odd len transactions with no offset the last read is ignored and\n// last write is masked\n// For odd len transactions with offset the first read is ignored and\n// first write is masked\n// For even len transactions with offset the last & first read is ignored and\n// last& first write is masked\n// For even len transactions no ingnores or masks. \n\n// Ignore logic for first transaction \nassign ignore_begin = sel_first ? addr_offset : 1'b0;\n\n// Ignore logic for second transaction. \nassign ignore_end = next_pending ? 1'b0 : ~(length_even ^ addr_offset);\n\n// Indicates if we are on the first transaction of a mc translation with more than 1 transaction.\nassign sel_first = (axhandshake | sel_first_r);\n\nalways @(posedge clk) begin\n if (reset)\n sel_first_r <= 1'b0;\n else if(axhandshake & ~next)\n sel_first_r <= 1'b1;\n else if(next)\n sel_first_r <= 1'b0;\nend\n\nendmodule\n`default_nettype wire\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_r_channel.v", "content": "\n// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. \n// -- \n// -- This file contains confidential and proprietary information \n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property \n// -- laws. \n// -- \n// -- DISCLAIMER \n// -- This disclaimer is not a license and does not grant any \n// -- rights to the materials distributed herewith. Except as \n// -- otherwise provided in a valid license issued to you by \n// -- Xilinx, and to the maximum extent permitted by applicable \n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND \n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES \n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING \n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- \n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and \n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of \n// -- liability) for any loss or damage of any kind or nature \n// -- related to, arising under or in connection with these \n// -- materials, including for any direct, or any indirect, \n// -- special, incidental, or consequential loss or damage \n// -- (including loss of data, profits, goodwill, or any type of \n// -- loss or damage suffered as a result of any action brought \n// -- by a third party) even if such damage or loss was \n// -- reasonably foreseeable or Xilinx had been advised of the \n// -- possibility of the same. \n// -- \n// -- CRITICAL APPLICATIONS \n// -- Xilinx products are not designed or intended to be fail- \n// -- safe, or for use in any application requiring fail-safe \n// -- performance, such as life-support or safety devices or \n// -- systems, Class III medical devices, nuclear facilities, \n// -- applications related to the deployment of airbags, or any \n// -- other applications that could lead to death, personal \n// -- injury, or severe property or environmental damage \n// -- (individually and collectively, \"Critical \n// -- Applications\"). Customer assumes the sole risk and \n// -- liability of any use of Xilinx products in Critical \n// -- Applications, subject only to applicable laws and \n// -- regulations governing limitations on product liability. \n// -- \n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS \n// -- PART OF THIS FILE AT ALL TIMES. \n// -- \n///////////////////////////////////////////////////////////////////////////////\n//\n// File name: axi_mc_r_channel.v\n//\n// Description: \n// Read data channel module to buffer read data from MC, ignore \n// extra data in case of BL8 and send the data to AXI.\n// The MC will send out the read data as it is ready and it has to be \n// accepted. The read data FIFO in the axi_mc_r_channel module will buffer \n// the data before being sent to AXI. The address channel module will\n// send the transaction information for every command that is sent to the \n// MC. The transaction information will be buffered in a transaction FIFO.\n// Based on the transaction FIFO information data will be ignored in\n// BL8 mode and the last signal to the AXI will be asserted. \n\n///////////////////////////////////////////////////////////////////////////////\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule mig_7series_v4_0_axi_mc_r_channel #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n // Width of ID signals.\n // Range: >= 1.\n parameter integer C_ID_WIDTH = 4, \n // Width of AXI xDATA and MCB xx_data\n // Range: 32, 64, 128.\n parameter integer C_DATA_WIDTH = 32,\n // MC burst length. = 1 for BL4 or BC4, = 2 for BL8\n parameter integer C_MC_BURST_LEN = 1,\n // axi addr width \n parameter integer C_AXI_ADDR_WIDTH = 32,\n // Number of memory clocks per fabric clock\n // = 2 for DDR2 or low frequency designs\n // = 4 for DDR3 or high frequency designs \n parameter C_MC_nCK_PER_CLK = 2,\n // memory controller burst mode,\n // values \"8\", \"4\" & \"OTF\"\n parameter C_MC_BURST_MODE = \"8\" \n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations \n///////////////////////////////////////////////////////////////////////////////\n input wire clk , \n input wire reset , \n\n output wire [C_ID_WIDTH-1:0] rid , \n output wire [C_DATA_WIDTH-1:0] rdata , \n output wire [1:0] rresp , \n output wire rlast , \n output wire rvalid , \n input wire rready , \n\n input wire [C_DATA_WIDTH-1:0] mc_app_rd_data , \n input wire mc_app_rd_valid , \n input wire mc_app_rd_last , \n input wire mc_app_ecc_multiple_err ,\n\n // Connections to/from axi_mc_ar_channel module\n input wire r_push ,\n output wire r_data_rdy , \n // length not needed. Can be removed. \n input wire [C_ID_WIDTH-1:0] r_arid , \n input wire r_rlast ,\n input wire r_ignore_begin ,\n input wire r_ignore_end \n\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam P_WIDTH = 3+C_ID_WIDTH;\nlocalparam P_DEPTH = 30;\nlocalparam P_AWIDTH = 5;\nlocalparam P_D_WIDTH = C_DATA_WIDTH+1;\n// rd data FIFO depth varies based on burst length.\n// For Bl8 it is two times the size of transaction FIFO.\n// Only in 2:1 mode BL8 transactions will happen which results in\n// two beats of read data per read transaction. \nlocalparam P_D_DEPTH = (C_MC_BURST_LEN == 2)? 64 : 32;\nlocalparam P_D_AWIDTH = (C_MC_BURST_LEN == 2)? 6: 5;\n \n// AXI protocol responses:\nlocalparam P_OKAY = 2'b00;\nlocalparam P_EXOKAY = 2'b01;\nlocalparam P_SLVERR = 2'b10;\nlocalparam P_DECERR = 2'b11;\n\n////////////////////////////////////////////////////////////////////////////////\n// Wire and register declarations\n////////////////////////////////////////////////////////////////////////////////\n \nwire done;\nwire [C_ID_WIDTH+3-1:0] trans_in;\nwire [C_ID_WIDTH+3-1:0] trans_out;\nreg [C_ID_WIDTH+3-1:0] trans_buf_out_r1;\nreg [C_ID_WIDTH+3-1:0] trans_buf_out_r;\nwire tr_empty;\nwire tr_rden;\nreg [1:0] state;\nwire [C_ID_WIDTH-1:0] rid_i;\nwire assert_rlast;\nwire ignore_begin;\nwire ignore_end;\nreg load_stage1;\nwire load_stage2;\nwire load_stage1_from_stage2;\n\nwire rhandshake;\nwire rlast_i;\nwire r_valid_i;\nwire [C_DATA_WIDTH:0] rd_data_fifo_in;\nwire [C_DATA_WIDTH:0] rd_data_fifo_out; \nwire rd_en; \nwire rd_full;\nwire rd_empty; \nwire rd_a_full;\nreg rd_last_r;\nwire fifo_rd_last;\nwire trans_a_full;\nwire trans_full;\n\nreg r_ignore_begin_r;\nreg r_ignore_end_r;\nwire fifo_full;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\n\n\n// localparam for 2 deep skid buffer\nlocalparam [1:0] \n ZERO = 2'b10,\n ONE = 2'b11,\n TWO = 2'b01;\n\nassign rresp = (rd_data_fifo_out[C_DATA_WIDTH] === 1) ? P_SLVERR : P_OKAY;\nassign rid = rid_i;\nassign rdata = rd_data_fifo_out[C_DATA_WIDTH-1:0];\nassign rlast = assert_rlast & ((~fifo_rd_last & ignore_end) \n | (fifo_rd_last & ~ignore_end));\nassign rvalid = ~rd_empty & ((~fifo_rd_last & ~ignore_begin)\n | (fifo_rd_last & ~ignore_end ));\n\n// assign MCB outputs\nassign rd_en = rhandshake & (~rd_empty);\n\nassign rhandshake =(rvalid & rready) |\n(((~fifo_rd_last & ignore_begin) | (fifo_rd_last & ignore_end )) & (~rd_empty));\n\n// register for timing \nalways @(posedge clk) begin\n r_ignore_begin_r <= r_ignore_begin;\n r_ignore_end_r <= r_ignore_end;\nend\n\nassign trans_in[0] = r_ignore_end_r;\nassign trans_in[1] = r_ignore_begin_r;\nassign trans_in[2] = r_rlast;\nassign trans_in[3+:C_ID_WIDTH] = r_arid;\n\nalways @(posedge clk) begin\n if (reset) begin\n rd_last_r <= 1'b0;\n end else if (rhandshake) begin\n rd_last_r <= ~rd_last_r;\n end\nend \n \nassign fifo_rd_last = (C_MC_BURST_LEN == 1) ? 1'b1 : rd_last_r;\n \n// rd data fifo\nmig_7series_v4_0_axi_mc_fifo #\n (\n .C_WIDTH (P_D_WIDTH),\n .C_AWIDTH (P_D_AWIDTH),\n .C_DEPTH (P_D_DEPTH)\n)\nrd_data_fifo_0\n(\n .clk ( clk ) ,\n .rst ( reset ) ,\n .wr_en ( mc_app_rd_valid ) ,\n .rd_en ( rd_en ) ,\n .din ( rd_data_fifo_in ) ,\n .dout ( rd_data_fifo_out ) ,\n .a_full ( rd_a_full ) ,\n .full ( rd_full ) ,\n .a_empty ( ) ,\n .empty ( rd_empty ) \n);\n\nassign rd_data_fifo_in = {mc_app_ecc_multiple_err, mc_app_rd_data};\n\n\nmig_7series_v4_0_axi_mc_fifo #\n (\n .C_WIDTH (P_WIDTH),\n .C_AWIDTH (P_AWIDTH),\n .C_DEPTH (P_DEPTH)\n)\ntransaction_fifo_0\n(\n .clk ( clk ) ,\n .rst ( reset ) ,\n .wr_en ( r_push ) ,\n .rd_en ( tr_rden ) ,\n .din ( trans_in ) ,\n .dout ( trans_out ) ,\n .a_full ( trans_a_full) ,\n .full ( trans_full ) ,\n .a_empty ( ) ,\n .empty ( tr_empty ) \n);\n\nassign rid_i = trans_buf_out_r[3+:C_ID_WIDTH];\nassign assert_rlast = trans_buf_out_r[2];\nassign ignore_begin = trans_buf_out_r[1];\nassign ignore_end = trans_buf_out_r[0];\n\nassign done = fifo_rd_last & rhandshake;\nassign fifo_full = (trans_a_full | trans_full) | (rd_a_full | rd_full);\nassign r_data_rdy = ~fifo_full ; \n\n// logic for 2 deep skid buffer for storing transaction data for timing\n\n// loading the output of the buffer \nalways @(posedge clk) begin\n if(load_stage1)\n if(load_stage1_from_stage2)\n trans_buf_out_r <= trans_buf_out_r1;\n else\n trans_buf_out_r <= trans_out; \nend\n\n// store data into the optional second stage \nalways @(posedge clk) begin\n if(load_stage2)\n trans_buf_out_r1 <= trans_out;\nend\n\n\n// condition to store data for the second stage \nassign load_stage2 = ~tr_empty & state[1];\n\n// Loading stage one conditions \nalways @ (*) begin\n if( ((state == ZERO) && (~tr_empty)) ||\n ((state == ONE) && (~tr_empty) && (done)) ||\n ((state == TWO) && (done)))\n load_stage1 = 1'b1;\n else\n load_stage1 = 1'b0;\nend // always @ *\n\nassign load_stage1_from_stage2 = (state == TWO);\n \nalways @(posedge clk) \nbegin\nif(reset) \n state <= ZERO;\nelse\n case (state)\n ZERO: if (~tr_empty) state <= ONE; \n ONE: begin\n if (done & tr_empty) state <= ZERO; \n// if (~done & (~tr_empty)) state <= TWO; \n else if (~done & (~tr_empty)) state <= TWO; \n end\n TWO: if (done) state <= ONE; \n endcase\nend \n\nassign tr_rden = ((state == ZERO) || (state == ONE)) && (~tr_empty);\n\nendmodule\n`default_nettype wire\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_simple_fifo.v", "content": "//-----------------------------------------------------------------------------\n//-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.\n//--\n//-- This file contains confidential and proprietary information\n//-- of Xilinx, Inc. and is protected under U.S. and\n//-- international copyright and other intellectual property\n//-- laws.\n//--\n//-- DISCLAIMER\n//-- This disclaimer is not a license and does not grant any\n//-- rights to the materials distributed herewith. Except as\n//-- otherwise provided in a valid license issued to you by\n//-- Xilinx, and to the maximum extent permitted by applicable\n//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//-- (2) Xilinx shall not be liable (whether in contract or tort,\n//-- including negligence, or under any other theory of\n//-- liability) for any loss or damage of any kind or nature\n//-- related to, arising under or in connection with these\n//-- materials, including for any direct, or any indirect,\n//-- special, incidental, or consequential loss or damage\n//-- (including loss of data, profits, goodwill, or any type of\n//-- loss or damage suffered as a result of any action brought\n//-- by a third party) even if such damage or loss was\n//-- reasonably foreseeable or Xilinx had been advised of the\n//-- possibility of the same.\n//--\n//-- CRITICAL APPLICATIONS\n//-- Xilinx products are not designed or intended to be fail-\n//-- safe, or for use in any application requiring fail-safe\n//-- performance, such as life-support or safety devices or\n//-- systems, Class III medical devices, nuclear facilities,\n//-- applications related to the deployment of airbags, or any\n//-- other applications that could lead to death, personal\n//-- injury, or severe property or environmental damage\n//-- (individually and collectively, \"Critical\n//-- Applications\"). Customer assumes the sole risk and\n//-- liability of any use of Xilinx products in Critical\n//-- Applications, subject only to applicable laws and\n//-- regulations governing limitations on product liability.\n//--\n//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//-- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//Purpose:\n// Synchronous, shallow FIFO that uses simple as a DP Memory.\n// This requires about 1/2 the resources as a Distributed RAM DPRAM \n// implementation.\n//\n// This FIFO will have the current data on the output when data is contained\n// in the FIFO. When the FIFO is empty, the output data is invalid.\n//\n//Reference:\n//Revision History:\n//\n//-----------------------------------------------\n//\n// MODULE: axi_mc_simple_fifo\n//\n// This is the simplest form of inferring the\n// simple/SRL(16/32)CE in a Xilinx FPGA.\n//\n//-----------------------------------------------\n`timescale 1ns / 100ps\n`default_nettype none\n\nmodule mig_7series_v4_0_axi_mc_simple_fifo #\n(\n parameter C_WIDTH = 8,\n parameter C_AWIDTH = 4,\n parameter C_DEPTH = 16\n)\n(\n input wire clk, // Main System Clock (Sync FIFO)\n input wire rst, // FIFO Counter Reset (Clk\n input wire wr_en, // FIFO Write Enable (Clk)\n input wire rd_en, // FIFO Read Enable (Clk)\n input wire [C_WIDTH-1:0] din, // FIFO Data Input (Clk)\n output wire [C_WIDTH-1:0] dout, // FIFO Data Output (Clk)\n output wire a_full,\n output wire full, // FIFO FULL Status (Clk)\n output wire a_empty,\n output wire empty // FIFO EMPTY Status (Clk)\n);\n\n///////////////////////////////////////\n// FIFO Local Parameters\n///////////////////////////////////////\nlocalparam [C_AWIDTH-1:0] C_EMPTY = ~(0);\nlocalparam [C_AWIDTH-1:0] C_EMPTY_PRE = (0);\nlocalparam [C_AWIDTH-1:0] C_FULL = C_EMPTY-1;\nlocalparam [C_AWIDTH-1:0] C_FULL_PRE = (C_DEPTH < 8) ? C_FULL-1 : C_FULL-(C_DEPTH/8);\n \n///////////////////////////////////////\n// FIFO Internal Signals\n///////////////////////////////////////\nreg [C_WIDTH-1:0] memory [C_DEPTH-1:0];\nreg [C_AWIDTH-1:0] cnt_read;\n\n\n///////////////////////////////////////\n// Main simple FIFO Array\n///////////////////////////////////////\nalways @(posedge clk) begin : BLKSRL\ninteger i;\n if (wr_en) begin\n for (i = 0; i < C_DEPTH-1; i = i + 1) begin\n memory[i+1] <= memory[i];\n end\n memory[0] <= din;\n end\nend\n\n///////////////////////////////////////\n// Read Index Counter\n// Up/Down Counter\n// *** Notice that there is no ***\n// *** OVERRUN protection. ***\n///////////////////////////////////////\nalways @(posedge clk) begin\n if (rst) cnt_read <= C_EMPTY;\n else if ( wr_en & !rd_en) cnt_read <= cnt_read + 1'b1;\n else if (!wr_en & rd_en) cnt_read <= cnt_read - 1'b1;\nend\n\n///////////////////////////////////////\n// Status Flags / Outputs\n// These could be registered, but would\n// increase logic in order to pre-decode\n// FULL/EMPTY status.\n///////////////////////////////////////\nassign full = (cnt_read == C_FULL);\nassign empty = (cnt_read == C_EMPTY);\nassign a_full = ((cnt_read >= C_FULL_PRE) && (cnt_read != C_EMPTY));\nassign a_empty = (cnt_read == C_EMPTY_PRE);\n\nassign dout = (C_DEPTH == 1) ? memory[0] : memory[cnt_read];\n\nendmodule // axi_mc_simple_fifo\n\n`default_nettype wire\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_w_channel.v", "content": "// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. \n// -- \n// -- This file contains confidential and proprietary information \n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property \n// -- laws. \n// -- \n// -- DISCLAIMER \n// -- This disclaimer is not a license and does not grant any \n// -- rights to the materials distributed herewith. Except as \n// -- otherwise provided in a valid license issued to you by \n// -- Xilinx, and to the maximum extent permitted by applicable \n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND \n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES \n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING \n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- \n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and \n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of \n// -- liability) for any loss or damage of any kind or nature \n// -- related to, arising under or in connection with these \n// -- materials, including for any direct, or any indirect, \n// -- special, incidental, or consequential loss or damage \n// -- (including loss of data, profits, goodwill, or any type of \n// -- loss or damage suffered as a result of any action brought \n// -- by a third party) even if such damage or loss was \n// -- reasonably foreseeable or Xilinx had been advised of the \n// -- possibility of the same. \n// -- \n// -- CRITICAL APPLICATIONS \n// -- Xilinx products are not designed or intended to be fail- \n// -- safe, or for use in any application requiring fail-safe \n// -- performance, such as life-support or safety devices or \n// -- systems, Class III medical devices, nuclear facilities, \n// -- applications related to the deployment of airbags, or any \n// -- other applications that could lead to death, personal \n// -- injury, or severe property or environmental damage \n// -- (individually and collectively, \"Critical \n// -- Applications\"). Customer assumes the sole risk and \n// -- liability of any use of Xilinx products in Critical \n// -- Applications, subject only to applicable laws and \n// -- regulations governing limitations on product liability. \n// -- \n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS \n// -- PART OF THIS FILE AT ALL TIMES. \n// -- \n///////////////////////////////////////////////////////////////////////////////\n//\n// File name: axi_mc_w_channel.v\n//\n// Description:\n// write data channel module is used to buffer the write data from AXI, mask extra transactions \n// that are not needed in BL8 mode and send them to the MC write data FIFO. \n// The use of register slice could result in write data arriving to this modules well before the \n// the commands are processed by the address modules. The data from AXI will be buffered \n// in the write data FIFO before being sent to the MC.\n// The address channel modules will send signals to mask appropriate data to before being sent \n// to the MC. \n//\n///////////////////////////////////////////////////////////////////////////////\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule mig_7series_v4_0_axi_mc_w_channel #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n // Width of AXI xDATA and MCB xx_data\n // Range: 32, 64, 128.\n parameter integer C_DATA_WIDTH = 32,\n // MC burst length. = 1 for BL4 or BC4, = 2 for BL8\n parameter integer C_MC_BURST_LEN = 1,\n // axi addr width \n parameter integer C_AXI_ADDR_WIDTH = 32,\n // ECC\n parameter C_ECC = \"OFF\"\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations \n///////////////////////////////////////////////////////////////////////////////\n input wire clk , \n input wire reset , \n\n input wire [C_DATA_WIDTH-1:0] wdata,\n input wire [C_DATA_WIDTH/8-1:0] wstrb,\n input wire wvalid,\n output reg wready,\n\n input wire awvalid,\n input wire w_cmd_rdy,\n input wire w_ignore_begin,\n input wire w_ignore_end,\n \n output wire cmd_wr_bytes,\n \n output wire mc_app_wdf_wren,\n output wire [C_DATA_WIDTH/8-1:0] mc_app_wdf_mask,\n output wire [C_DATA_WIDTH-1:0] mc_app_wdf_data,\n output wire mc_app_wdf_last,\n input wire mc_app_wdf_rdy,\n\n output wire w_data_rdy\n);\n\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\n//states\nlocalparam SM_FIRST_DATA = 1'b0;\nlocalparam SM_SECOND_DATA = 1'b1;\n\n////////////////////////////////////////////////////////////////////////////////\n// Wire and register declarations\n////////////////////////////////////////////////////////////////////////////////\nreg [C_DATA_WIDTH/8-1:0] wdf_mask;\nreg [C_DATA_WIDTH-1:0] wdf_data;\nreg valid;\n\nwire wdf_last;\nwire assert_wren;\nwire disable_data;\nwire [C_DATA_WIDTH/8-1:0] next_wdf_mask;\nwire [C_DATA_WIDTH-1:0] next_wdf_data;\nwire fsm_ready;\nwire wvalid_int;\n\nwire [C_DATA_WIDTH-1:0] next_mc_app_wdf_data;\nwire next_mc_app_wdf_wren;\nwire [C_DATA_WIDTH/8-1:0] next_mc_app_wdf_mask;\nwire next_mc_app_wdf_last;\n\nreg mc_app_wdf_wren_reg;\nreg [C_DATA_WIDTH/8-1:0] mc_app_wdf_mask_reg;\nreg [C_DATA_WIDTH-1:0] mc_app_wdf_data_reg;\nreg mc_app_wdf_last_reg;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\nassign wvalid_int = wready ? wvalid : valid;\n\nalways @(posedge clk) begin\n if(reset) begin\n valid <= 1'b0;\n wready <= 1'b0;\n end else begin\n valid <= wvalid_int;\n wready <= ~wvalid_int | fsm_ready;\n end\nend\n\nassign fsm_ready = (assert_wren & ~disable_data);\n\nassign mc_app_wdf_wren = next_mc_app_wdf_wren;\nassign mc_app_wdf_last = next_mc_app_wdf_last;\nassign mc_app_wdf_mask = next_mc_app_wdf_mask;\nassign mc_app_wdf_data = next_mc_app_wdf_data;\n\nassign next_mc_app_wdf_wren = mc_app_wdf_rdy ? assert_wren : mc_app_wdf_wren_reg;\nassign next_mc_app_wdf_last = mc_app_wdf_rdy ? wdf_last : mc_app_wdf_last_reg;\nassign next_mc_app_wdf_mask = mc_app_wdf_rdy ? ((disable_data)? {C_DATA_WIDTH/8{1'b1}} : next_wdf_mask) : mc_app_wdf_mask_reg;\nassign next_mc_app_wdf_data = mc_app_wdf_rdy ? next_wdf_data : mc_app_wdf_data_reg;\n\nalways @(posedge clk) begin\n if(reset) begin\n mc_app_wdf_wren_reg <= 1'b0;\n mc_app_wdf_last_reg <= 1'b0;\n mc_app_wdf_mask_reg <= {C_DATA_WIDTH/8{1'b0}};\n end else begin\n mc_app_wdf_wren_reg <= next_mc_app_wdf_wren;\n mc_app_wdf_last_reg <= next_mc_app_wdf_last;\n mc_app_wdf_mask_reg <= next_mc_app_wdf_mask;\n end\nend\n\nalways @(posedge clk) begin\n mc_app_wdf_data_reg <= next_mc_app_wdf_data;\nend\n\nassign next_wdf_mask = wready ? ~wstrb : wdf_mask;\nassign next_wdf_data = wready ? wdata : wdf_data;\n\nalways @(posedge clk) begin\n wdf_mask <= next_wdf_mask;\n wdf_data <= next_wdf_data;\nend\n\ngenerate\n if(C_MC_BURST_LEN == 1) begin : gen_bc1\n // w_data_rdy to axi_mc_cmd_fsm when one Bl8 or Bl4 worth of write data \n // is pumped into to MC WDF. \n assign w_data_rdy = wvalid_int & mc_app_wdf_rdy;\n\n // write enable signal to WDF\n assign assert_wren = w_cmd_rdy;\n assign wdf_last = w_cmd_rdy;\n assign disable_data = 1'b0;\n\n end else begin : gen_bc2\n // Declaration of signals used only in BC2 mode\n reg state;\n reg next_state;\n reg w_ignore_end_r;\n\n always @(posedge clk) begin\n if (reset)\n state <= SM_FIRST_DATA;\n else\n state <= next_state;\n end\n\n // Next state transitions.\n // Simple state machine to push data into the MC write data FIFO(WDF). \n // For BL4 only one data will be written into the WDF. For BL8 two \n // beats of data will be written into the WDF. \n always @(*)\n begin\n next_state = state;\n case (state)\n SM_FIRST_DATA:\n if(awvalid & wvalid_int & mc_app_wdf_rdy)\n next_state = SM_SECOND_DATA; \n else \n next_state = state;\n\n SM_SECOND_DATA:\n if(w_cmd_rdy)\n next_state = SM_FIRST_DATA;\n else\n next_state = state;\n\n default:\n next_state = SM_FIRST_DATA;\n endcase // case(state)\n end // always @ (*)\n\n // w_data_rdy to axi_mc_cmd_fsm when one Bl8 or Bl4 worth of write data \n // is pumped into to MC WDF. \n assign w_data_rdy = ((state == SM_SECOND_DATA) & (wvalid_int | w_ignore_end_r) & mc_app_wdf_rdy);\n\n // write enable signal to WDF\n assign assert_wren = ((state == SM_FIRST_DATA) & (next_state == SM_SECOND_DATA)) |\n ((state == SM_SECOND_DATA) & (next_state == SM_FIRST_DATA));\n\n assign wdf_last = w_cmd_rdy;\n\n always @(posedge clk) begin\n w_ignore_end_r <= w_ignore_end;\n end\n\n // Disable data by asserting all the MASK signals based on the\n // ignore signals from the address modules \n assign disable_data = (((state == SM_FIRST_DATA) & w_ignore_begin) |\n ((state == SM_SECOND_DATA) & w_ignore_end_r));\n\n end // if (C_MC_BURST_LEN == 1)\nendgenerate \n\ngenerate\n if(C_ECC == \"ON\") begin : gen_ecc\n if(C_MC_BURST_LEN == 1) begin : gen_ecc1\n assign cmd_wr_bytes = |next_mc_app_wdf_mask;\n\n end else begin : gen_ecc2\n\n wire mask_or;\n reg pre_mask_or;\n \n assign cmd_wr_bytes = (pre_mask_or | mask_or);\n\n assign mask_or = |next_mc_app_wdf_mask; \n \n always @(posedge clk)\n if (next_mc_app_wdf_wren & mc_app_wdf_rdy)\n pre_mask_or <= mask_or;\n\n end // if (C_MC_BURST_LEN == 1)\n end // if (C_ECC == \"ON\")\nendgenerate \n\nendmodule\n`default_nettype wire\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_wr_cmd_fsm.v", "content": "// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. \n// -- \n// -- This file contains confidential and proprietary information \n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property \n// -- laws. \n// -- \n// -- DISCLAIMER \n// -- This disclaimer is not a license and does not grant any \n// -- rights to the materials distributed herewith. Except as \n// -- otherwise provided in a valid license issued to you by \n// -- Xilinx, and to the maximum extent permitted by applicable \n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND \n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES \n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING \n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- \n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and \n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of \n// -- liability) for any loss or damage of any kind or nature \n// -- related to, arising under or in connection with these \n// -- materials, including for any direct, or any indirect, \n// -- special, incidental, or consequential loss or damage \n// -- (including loss of data, profits, goodwill, or any type of \n// -- loss or damage suffered as a result of any action brought \n// -- by a third party) even if such damage or loss was \n// -- reasonably foreseeable or Xilinx had been advised of the \n// -- possibility of the same. \n// -- \n// -- CRITICAL APPLICATIONS \n// -- Xilinx products are not designed or intended to be fail- \n// -- safe, or for use in any application requiring fail-safe \n// -- performance, such as life-support or safety devices or \n// -- systems, Class III medical devices, nuclear facilities, \n// -- applications related to the deployment of airbags, or any \n// -- other applications that could lead to death, personal \n// -- injury, or severe property or environmental damage \n// -- (individually and collectively, \"Critical \n// -- Applications\"). Customer assumes the sole risk and \n// -- liability of any use of Xilinx products in Critical \n// -- Applications, subject only to applicable laws and \n// -- regulations governing limitations on product liability. \n// -- \n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS \n// -- PART OF THIS FILE AT ALL TIMES. \n// -- \n///////////////////////////////////////////////////////////////////////////////\n//\n// File name: axi_mc_wr_cmd_fsm.v\n//\n// Description: \n// Simple state machine to handle sending commands from AXI to MC. The flow:\n// 1. A transaction can only be initiaited when axvalid is true and data_rdy\n// is true. For writes, data_rdy means that one completed BL8 or BL4 write \n// data has been pushed into the MC write FIFOs. For read operations,\n// data_rdy indicates that there is enough room to push the transaction into\n// the read FIF & read transaction fifo in the shim. If the FIFO's in the \n// read channel module is full, then the state machine waits for the \n// FIFO's to drain out. \n//\n// 2. When CMD_EN is asserted, it remains high until we sample CMD_FULL in\n// a low state. When CMD_EN == 1'b1, and CMD_FULL == 1'b0, then the command\n// has been accepted. When the command is accepted, if the next_pending\n// signal is high we will incremented to the next transaction and issue the\n// cmd_en again when data_rdy is high. Otherwise we will go to the done\n// state.\n//\n// 3. The AXI transaction can only complete when b_full is not true (for writes)\n// and no more mc transactions need to be issued. The AXREADY will be\n// asserted and the state machine will progress back to the the IDLE state.\n// \n///////////////////////////////////////////////////////////////////////////////\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule mig_7series_v4_0_axi_mc_wr_cmd_fsm #(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n // MC burst length. = 1 for BL4 or BC4, = 2 for BL8\n parameter integer C_MC_BURST_LEN = 1,\n // parameter to identify rd or wr instantation\n // = 1 rd , = 0 wr \n parameter integer C_MC_RD_INST = 0\n \n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations \n///////////////////////////////////////////////////////////////////////////////\n input wire clk , \n input wire reset , \n output reg axready , \n input wire axvalid , \n output wire cmd_en , \n input wire cmd_full , \n // signal to increment to the next mc transaction \n output wire next , \n // signal to the fsm there is another transaction required\n input wire next_pending ,\n // Write Data portion has completed or Read FIFO has a slot available (not\n // full)\n input wire data_rdy ,\n // status signal for w_channel when command is written. \n output wire b_push ,\n input wire b_full ,\n output wire cmd_en_last \n);\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n///////////////////////////////////////////////////////////////////////////////\n assign cmd_en = (~b_full & axvalid & data_rdy);\n\n assign next = (~cmd_full & cmd_en);\n\n assign cmd_en_last = next & ~next_pending;\n\n assign b_push = cmd_en_last;\n\n always @(posedge clk) begin\n if (reset)\n axready <= 1'b0;\n else\n axready <= ~axvalid | cmd_en_last;\n end\n\nendmodule\n`default_nettype wire\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_axi_mc_wrap_cmd.v", "content": "// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved. \n// -- \n// -- This file contains confidential and proprietary information \n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property \n// -- laws. \n// -- \n// -- DISCLAIMER \n// -- This disclaimer is not a license and does not grant any \n// -- rights to the materials distributed herewith. Except as \n// -- otherwise provided in a valid license issued to you by \n// -- Xilinx, and to the maximum extent permitted by applicable \n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND \n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES \n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING \n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- \n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and \n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of \n// -- liability) for any loss or damage of any kind or nature \n// -- related to, arising under or in connection with these \n// -- materials, including for any direct, or any indirect, \n// -- special, incidental, or consequential loss or damage \n// -- (including loss of data, profits, goodwill, or any type of \n// -- loss or damage suffered as a result of any action brought \n// -- by a third party) even if such damage or loss was \n// -- reasonably foreseeable or Xilinx had been advised of the \n// -- possibility of the same. \n// -- \n// -- CRITICAL APPLICATIONS \n// -- Xilinx products are not designed or intended to be fail- \n// -- safe, or for use in any application requiring fail-safe \n// -- performance, such as life-support or safety devices or \n// -- systems, Class III medical devices, nuclear facilities, \n// -- applications related to the deployment of airbags, or any \n// -- other applications that could lead to death, personal \n// -- injury, or severe property or environmental damage \n// -- (individually and collectively, \"Critical \n// -- Applications\"). Customer assumes the sole risk and \n// -- liability of any use of Xilinx products in Critical \n// -- Applications, subject only to applicable laws and \n// -- regulations governing limitations on product liability. \n// -- \n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS \n// -- PART OF THIS FILE AT ALL TIMES. \n// -- \n///////////////////////////////////////////////////////////////////////////////\n//\n// File name: axi_mc_wrap_cmd.v\n//\n// Description: \n// MC does not support an AXI WRAP command directly. \n// To complete an AXI WRAP transaction we will issue one transaction if the\n// address is wrap boundary aligned, otherwise two transactions are issued.\n// The first transaction is from the starting offset to the wrap address upper\n// boundary. The second transaction is from the wrap boundary lowest address\n// to the address offset. WRAP burst types will never exceed 16 beats.\n//\n// Calculates the number of MC beats for each axi transaction for WRAP\n// burst type ( for all axsize values = C_DATA_WIDTH ):\n// AR_SIZE | AR_LEN | OFFSET | NUM_BEATS 1 | NUM_BEATS 2\n// b010( 4) | b0001( 2) | b0000 | 2 | 0 \n// b010( 4) | b0001( 2) | b0001 | 1 | 1 \n// b010( 4) | b0011( 4) | b0000 | 4 | 0 \n// b010( 4) | b0011( 4) | b0001 | 3 | 1 \n// b010( 4) | b0011( 4) | b0010 | 2 | 2 \n// b010( 4) | b0011( 4) | b0011 | 1 | 3 \n// b010( 4) | b0111( 8) | b0000 | 8 | 0 \n// b010( 4) | b0111( 8) | b0001 | 7 | 1 \n// b010( 4) | b0111( 8) | b0010 | 6 | 2 \n// b010( 4) | b0111( 8) | b0011 | 5 | 3 \n// b010( 4) | b0111( 8) | b0100 | 4 | 4 \n// b010( 4) | b0111( 8) | b0101 | 3 | 5 \n// b010( 4) | b0111( 8) | b0110 | 2 | 6 \n// b010( 4) | b0111( 8) | b0111 | 1 | 7 \n// b010( 4) | b1111( 16) | b0000 | 16 | 0 \n// b010( 4) | b1111( 16) | b0001 | 15 | 1 \n// b010( 4) | b1111( 16) | b0010 | 14 | 2 \n// b010( 4) | b1111( 16) | b0011 | 13 | 3 \n// b010( 4) | b1111( 16) | b0100 | 12 | 4 \n// b010( 4) | b1111( 16) | b0101 | 11 | 5 \n// b010( 4) | b1111( 16) | b0110 | 10 | 6 \n// b010( 4) | b1111( 16) | b0111 | 9 | 7 \n// b010( 4) | b1111( 16) | b1000 | 8 | 8 \n// b010( 4) | b1111( 16) | b1001 | 7 | 9 \n// b010( 4) | b1111( 16) | b1010 | 6 | 10 \n// b010( 4) | b1111( 16) | b1011 | 5 | 11 \n// b010( 4) | b1111( 16) | b1100 | 4 | 12 \n// b010( 4) | b1111( 16) | b1101 | 3 | 13 \n// b010( 4) | b1111( 16) | b1110 | 2 | 14 \n// b010( 4) | b1111( 16) | b1111 | 1 | 15 \n///////////////////////////////////////////////////////////////////////////////\n\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule mig_7series_v4_0_axi_mc_wrap_cmd #\n(\n///////////////////////////////////////////////////////////////////////////////\n// Parameter Definitions\n///////////////////////////////////////////////////////////////////////////////\n // Width of AxADDR\n // Range: 32.\n parameter integer C_AXI_ADDR_WIDTH = 32, \n // Width of cmd_byte_addr\n // Range: 30\n parameter integer C_MC_ADDR_WIDTH = 30,\n // MC burst length. = 1 for BL4 or BC4, = 2 for BL8\n parameter integer C_MC_BURST_LEN = 1,\n // Width of AXI xDATA and MC xx_data\n // Range: 32, 64, 128.\n parameter integer C_DATA_WIDTH = 32,\n // Static value of axsize\n // Range: 2-5\n parameter integer C_AXSIZE = 2,\n // Instance for Read channel or write channel\n parameter integer C_MC_RD_INST = 0\n)\n(\n///////////////////////////////////////////////////////////////////////////////\n// Port Declarations \n///////////////////////////////////////////////////////////////////////////////\n input wire clk , \n input wire reset , \n input wire [C_AXI_ADDR_WIDTH-1:0] axaddr , \n input wire [7:0] axlen , \n input wire [2:0] axsize , // C_AXSIZE parameter is used instead\n // axhandshake = axvalid & axready\n input wire axhandshake , \n output wire [C_AXI_ADDR_WIDTH-1:0] cmd_byte_addr ,\n output wire ignore_begin ,\n output wire ignore_end ,\n // Connections to/from fsm module\n // signal to increment to the next mc transaction \n input wire next , \n // signal to the fsm there is another transaction required\n output wire next_pending \n\n);\n////////////////////////////////////////////////////////////////////////////////\n// Local parameters\n////////////////////////////////////////////////////////////////////////////////\nlocalparam P_AXLEN_WIDTH = 4;\n////////////////////////////////////////////////////////////////////////////////\n// Wire and register declarations\n////////////////////////////////////////////////////////////////////////////////\nreg sel_first_r;\nreg [3:0] axlen_cnt;\nreg [3:0] int_addr;\nreg int_next_pending_r;\n\nwire sel_first;\nwire [3:0] axlen_i;\nwire [3:0] axlen_cnt_i;\nwire [3:0] axlen_cnt_t;\nwire [3:0] axlen_cnt_p;\n\nwire addr_offset;\nwire [C_AXI_ADDR_WIDTH-1:0] axaddr_wrap;\nwire [3:0] int_addr_t;\nwire [3:0] int_addr_p;\nwire [3:0] int_addr_t_inc;\nwire int_next_pending;\nwire extra_cmd;\n\n////////////////////////////////////////////////////////////////////////////////\n// BEGIN RTL\n////////////////////////////////////////////////////////////////////////////////\nassign cmd_byte_addr = axaddr_wrap;\nassign axlen_i = axlen[3:0];\n\nassign axaddr_wrap = {axaddr[C_AXI_ADDR_WIDTH-1:C_AXSIZE+4], int_addr_t[3:0], axaddr[C_AXSIZE-1:0]};\n\ngenerate\n if(C_MC_BURST_LEN == 1) begin\n assign addr_offset = 1'b0;\n assign int_addr_t = axhandshake ? (axaddr[C_AXSIZE+: 4]) : int_addr;\n\n end else begin\n // Figuring out if the address have an offset for padding data in BL8 case\n assign addr_offset = axaddr[C_AXSIZE];\n\n if(C_MC_RD_INST == 0) // axhandshake & next won't occur in same cycle in Write channel 2:1 mode\n assign int_addr_t = int_addr;\n else\n assign int_addr_t = axhandshake ? (axaddr[C_AXSIZE+: 4]) : int_addr;\n end\nendgenerate\n\nassign int_addr_t_inc = int_addr_t + C_MC_BURST_LEN;\n\nassign int_addr_p = ((int_addr_t & ~axlen_i) | (int_addr_t_inc & axlen_i));\n\nalways @(posedge clk) begin\n if(reset)\n int_addr <= 4'h0;\n else if (axhandshake & ~next)\n int_addr <= (axaddr[C_AXSIZE+: 4]);\n else if(next)\n int_addr <= int_addr_p;\nend\n\n// assign axlen_cnt_i = (C_MC_BURST_LEN == 1) ? axlen_i : (extra_cmd ? ((axlen_i >> 1) + 1'b1) : (axlen_i >> 1));\nassign axlen_cnt_i = (C_MC_BURST_LEN == 1) ? axlen_i : (axlen_i >> 1);\n\nassign axlen_cnt_t = axhandshake ? axlen_cnt_i : axlen_cnt;\n\nassign axlen_cnt_p = (axlen_cnt_t - 1'b1);\n\nalways @(posedge clk) begin\n if(reset)\n axlen_cnt <= 4'hf;\n else if (axhandshake & ~next)\n axlen_cnt <= axlen_cnt_i;\n else if(next)\n axlen_cnt <= axlen_cnt_p;\nend \n\nassign extra_cmd = addr_offset;\n\nassign next_pending = extra_cmd ? int_next_pending_r : int_next_pending;\n\nassign int_next_pending = |axlen_cnt_t;\n\nalways @(posedge clk) begin\n if(reset)\n int_next_pending_r <= 1'b1;\n else if(extra_cmd & next)\n int_next_pending_r <= int_next_pending;\nend\n\n// Ignore logic for first transaction \nassign ignore_begin = sel_first ? addr_offset : 1'b0;\n\n// Ignore logic for second transaction. \nassign ignore_end = next_pending ? 1'b0 : addr_offset;\n\n// Indicates if we are on the first transaction of a mc translation with more than 1 transaction.\nassign sel_first = (axhandshake | sel_first_r);\n\nalways @(posedge clk) begin\n if (reset)\n sel_first_r <= 1'b0;\n else if(axhandshake & ~next)\n sel_first_r <= 1'b1;\n else if(next)\n sel_first_r <= 1'b0;\nend\n\nendmodule\n`default_nettype wire\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_a_upsizer.v", "content": "// -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: Address Up-Sizer\n//\n//\n// Verilog-standard: Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n// ddr_a_upsizer\n// generic_baseblocks/*\n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\nmodule mig_7series_v4_0_ddr_a_upsizer #\n (\n parameter C_FAMILY = \"rtl\", \n // FPGA Family. Current version: virtex6 or spartan6.\n parameter integer C_AXI_ID_WIDTH = 4, \n // Width of all ID signals on SI and MI side of converter.\n // Range: >= 1.\n parameter integer C_AXI_ADDR_WIDTH = 32, \n // Width of all ADDR signals on SI and MI side of converter.\n // Range: 32.\n parameter C_S_AXI_DATA_WIDTH = 32'h00000020, \n // Width of S_AXI_WDATA and S_AXI_RDATA.\n // Format: Bit32; \n // Range: 'h00000020, 'h00000040, 'h00000080, 'h00000100.\n parameter C_M_AXI_DATA_WIDTH = 32'h00000040, \n // Width of M_AXI_WDATA and M_AXI_RDATA.\n // Assume greater than or equal to C_S_AXI_DATA_WIDTH.\n // Format: Bit32;\n // Range: 'h00000020, 'h00000040, 'h00000080, 'h00000100.\n parameter integer C_M_AXI_REGISTER = 0,\n // Clock output data.\n // Range: 0, 1\n parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,\n // 1 = Propagate all USER signals, 0 = Dont propagate.\n parameter integer C_AXI_AUSER_WIDTH = 1,\n // Width of AWUSER/ARUSER signals. \n // Range: >= 1.\n parameter integer C_AXI_CHANNEL = 0,\n // 0 = AXI AW Channel.\n // 1 = AXI AR Channel.\n parameter integer C_PACKING_LEVEL = 1,\n // 0 = Never pack (expander only); packing logic is omitted.\n // 1 = Pack only when CACHE[1] (Modifiable) is high.\n // 2 = Always pack, regardless of sub-size transaction or Modifiable bit.\n // (Required when used as helper-core by mem-con.)\n parameter integer C_SUPPORT_BURSTS = 1,\n // Disabled when all connected masters and slaves are AxiLite,\n // allowing logic to be simplified.\n parameter integer C_SINGLE_THREAD = 1,\n // 0 = Ignore ID when propagating transactions (assume all responses are in order).\n // 1 = Allow multiple outstanding transactions only if the IDs are the same\n // to prevent response reordering.\n // (If ID mismatches, stall until outstanding transaction counter = 0.)\n parameter integer C_S_AXI_BYTES_LOG = 3,\n // Log2 of number of 32bit word on SI-side.\n parameter integer C_M_AXI_BYTES_LOG = 3\n // Log2 of number of 32bit word on MI-side.\n )\n (\n // Global Signals\n input wire ARESET,\n input wire ACLK,\n\n // Command Interface\n output wire cmd_valid,\n output wire cmd_fix,\n output wire cmd_modified,\n output wire cmd_complete_wrap,\n output wire cmd_packed_wrap,\n output wire [C_M_AXI_BYTES_LOG-1:0] cmd_first_word, \n output wire [C_M_AXI_BYTES_LOG-1:0] cmd_next_word, \n output wire [C_M_AXI_BYTES_LOG-1:0] cmd_last_word,\n output wire [C_M_AXI_BYTES_LOG-1:0] cmd_offset,\n output wire [C_M_AXI_BYTES_LOG-1:0] cmd_mask,\n output wire [C_S_AXI_BYTES_LOG:0] cmd_step,\n output wire [8-1:0] cmd_length,\n input wire cmd_ready,\n \n // Slave Interface Write Address Ports\n input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AID,\n input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AADDR,\n input wire [8-1:0] S_AXI_ALEN,\n input wire [3-1:0] S_AXI_ASIZE,\n input wire [2-1:0] S_AXI_ABURST,\n input wire [2-1:0] S_AXI_ALOCK,\n input wire [4-1:0] S_AXI_ACACHE,\n input wire [3-1:0] S_AXI_APROT,\n input wire [4-1:0] S_AXI_AREGION,\n input wire [4-1:0] S_AXI_AQOS,\n input wire [C_AXI_AUSER_WIDTH-1:0] S_AXI_AUSER,\n input wire S_AXI_AVALID,\n output wire S_AXI_AREADY,\n\n // Master Interface Write Address Port\n output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AID,\n output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AADDR,\n output wire [8-1:0] M_AXI_ALEN,\n output wire [3-1:0] M_AXI_ASIZE,\n output wire [2-1:0] M_AXI_ABURST,\n output wire [2-1:0] M_AXI_ALOCK,\n output wire [4-1:0] M_AXI_ACACHE,\n output wire [3-1:0] M_AXI_APROT,\n output wire [4-1:0] M_AXI_AREGION,\n output wire [4-1:0] M_AXI_AQOS,\n output wire [C_AXI_AUSER_WIDTH-1:0] M_AXI_AUSER,\n output wire M_AXI_AVALID,\n input wire M_AXI_AREADY\n );\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Local params\n /////////////////////////////////////////////////////////////////////////////\n \n // Decode the native transaction size on the SI-side interface.\n localparam [3-1:0] C_S_AXI_NATIVE_SIZE = (C_S_AXI_DATA_WIDTH == 1024) ? 3'b111 :\n (C_S_AXI_DATA_WIDTH == 512) ? 3'b110 :\n (C_S_AXI_DATA_WIDTH == 256) ? 3'b101 :\n (C_S_AXI_DATA_WIDTH == 128) ? 3'b100 :\n (C_S_AXI_DATA_WIDTH == 64) ? 3'b011 :\n (C_S_AXI_DATA_WIDTH == 32) ? 3'b010 :\n (C_S_AXI_DATA_WIDTH == 16) ? 3'b001 :\n 3'b000;\n \n // Decode the native transaction size on the MI-side interface.\n localparam [3-1:0] C_M_AXI_NATIVE_SIZE = (C_M_AXI_DATA_WIDTH == 1024) ? 3'b111 :\n (C_M_AXI_DATA_WIDTH == 512) ? 3'b110 :\n (C_M_AXI_DATA_WIDTH == 256) ? 3'b101 :\n (C_M_AXI_DATA_WIDTH == 128) ? 3'b100 :\n (C_M_AXI_DATA_WIDTH == 64) ? 3'b011 :\n (C_M_AXI_DATA_WIDTH == 32) ? 3'b010 :\n (C_M_AXI_DATA_WIDTH == 16) ? 3'b001 :\n 3'b000;\n \n // Constants used to generate maximum length on SI-side for complete wrap.\n localparam [24-1:0] C_DOUBLE_LEN = 24'b0000_0000_0000_0000_1111_1111;\n \n // Constants for burst types.\n localparam [2-1:0] C_FIX_BURST = 2'b00;\n localparam [2-1:0] C_INCR_BURST = 2'b01;\n localparam [2-1:0] C_WRAP_BURST = 2'b10;\n \n // Constants for packing levels.\n localparam integer C_NEVER_PACK = 0;\n localparam integer C_DEFAULT_PACK = 1;\n localparam integer C_ALWAYS_PACK = 2;\n \n // Depth for command FIFO.\n localparam integer C_FIFO_DEPTH_LOG = 5;\n \n // Maximum address bit coverage by WRAP.\n localparam integer C_BURST_BYTES_LOG = 4 + C_S_AXI_BYTES_LOG;\n \n // Calculate unused address bits.\n localparam integer C_SI_UNUSED_LOG = C_AXI_ADDR_WIDTH-C_S_AXI_BYTES_LOG;\n localparam integer C_MI_UNUSED_LOG = C_AXI_ADDR_WIDTH-C_M_AXI_BYTES_LOG;\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Variables for generating parameter controlled instances.\n /////////////////////////////////////////////////////////////////////////////\n \n genvar bit_cnt;\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Functions\n /////////////////////////////////////////////////////////////////////////////\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Internal signals\n /////////////////////////////////////////////////////////////////////////////\n \n // Access decoding related signals.\n wire access_is_fix;\n wire access_is_incr;\n wire access_is_wrap;\n wire access_is_modifiable;\n wire access_is_unaligned;\n reg [8-1:0] si_maximum_length;\n wire [16-1:0] mi_word_intra_len_complete;\n wire [20-1:0] mask_help_vector;\n reg [C_M_AXI_BYTES_LOG-1:0] mi_word_intra_len;\n reg [8-1:0] upsized_length;\n wire sub_sized_wrap;\n reg [C_M_AXI_BYTES_LOG-1:0] size_mask;\n reg [C_BURST_BYTES_LOG-1:0] burst_mask;\n \n // Translation related signals.\n wire access_need_extra_word;\n wire [8-1:0] adjusted_length;\n wire [C_BURST_BYTES_LOG-1:0] wrap_addr_aligned;\n \n // Command buffer help signals.\n wire cmd_empty;\n reg [C_AXI_ID_WIDTH-1:0] queue_id;\n wire id_match;\n wire cmd_id_check;\n wire s_ready;\n wire cmd_full;\n wire allow_new_cmd;\n wire cmd_push;\n reg cmd_push_block;\n \n // Internal Command Interface signals.\n wire cmd_valid_i;\n wire cmd_fix_i;\n wire cmd_modified_i;\n wire cmd_complete_wrap_i;\n wire cmd_packed_wrap_i;\n wire [C_M_AXI_BYTES_LOG-1:0] cmd_first_word_ii;\n wire [C_M_AXI_BYTES_LOG-1:0] cmd_first_word_i;\n wire [C_M_AXI_BYTES_LOG-1:0] cmd_next_word_ii;\n wire [C_M_AXI_BYTES_LOG-1:0] cmd_next_word_i;\n wire [C_M_AXI_BYTES_LOG:0] cmd_last_word_ii;\n wire [C_M_AXI_BYTES_LOG-1:0] cmd_last_word_i;\n wire [C_M_AXI_BYTES_LOG-1:0] cmd_offset_i;\n reg [C_M_AXI_BYTES_LOG-1:0] cmd_mask_i;\n wire [3-1:0] cmd_size_i;\n wire [3-1:0] cmd_size;\n reg [8-1:0] cmd_step_ii;\n wire [C_S_AXI_BYTES_LOG:0] cmd_step_i;\n reg [8-1:0] cmd_length_i;\n \n // Internal SI-side signals.\n wire S_AXI_AREADY_I;\n \n // Internal MI-side signals.\n wire [C_AXI_ID_WIDTH-1:0] M_AXI_AID_I;\n reg [C_AXI_ADDR_WIDTH-1:0] M_AXI_AADDR_I;\n reg [8-1:0] M_AXI_ALEN_I;\n reg [3-1:0] M_AXI_ASIZE_I;\n reg [2-1:0] M_AXI_ABURST_I;\n wire [2-1:0] M_AXI_ALOCK_I;\n wire [4-1:0] M_AXI_ACACHE_I;\n wire [3-1:0] M_AXI_APROT_I;\n wire [4-1:0] M_AXI_AREGION_I;\n wire [4-1:0] M_AXI_AQOS_I;\n wire [C_AXI_AUSER_WIDTH-1:0] M_AXI_AUSER_I;\n wire M_AXI_AVALID_I;\n wire M_AXI_AREADY_I;\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Decode the incoming transaction:\n //\n // Determine the burst type sucha as FIX, INCR and WRAP. Only WRAP and INCR \n // transactions can be upsized to the MI-side data width.\n // Detect if the transaction is modifiable and if it is of native size. Only\n // native sized transaction are upsized when allowed, unless forced by \n // parameter. FIX can never be upsized (packed) regardless if force is \n // turned on. However the FIX data will be steered to the correct \n // byte lane(s) and the transaction will be native on MI-side when \n // applicable.\n //\n // Calculate the MI-side length for the SI-side transaction.\n // \n // Decode the affected address bits in the MI-side. Used to determine last \n // word for a burst and if necassarily adjust the length of the upsized \n // transaction. Length adjustment only occurs when the trasaction is longer \n // than can fit in MI-side and there is an unalignment for the first word\n // (and the last word crosses MI-word boundary and wraps).\n // \n // The maximum allowed SI-side length is calculated to be able to determine \n // if a WRAP transaction can fit inside a single MI-side data word.\n // \n // Determine address bits mask for the SI-side transaction size, i.e. address\n // bits that shall be removed for unalignment when managing data in W and \n // R channels. For example: the two least significant bits are not used \n // for data packing in a 32-bit SI-side transaction (address 1-3 will appear\n // as 0 for the W and R channels, but the untouched address is still forwarded \n // to the MI-side).\n // \n // Determine the Mask bits for the address bits that are affected by a\n // sub-sized WRAP transaction (up to and including complete WRAP). The Mask \n // is used to generate the correct data mapping for a sub-sized and\n // complete WRAP, i.e. having a local wrap in a partial MI-side word.\n // \n // Detect any SI-side address unalignment when used on the MI-side.\n // \n /////////////////////////////////////////////////////////////////////////////\n \n // Transaction burst type.\n assign access_is_fix = ( S_AXI_ABURST == C_FIX_BURST );\n assign access_is_incr = ( S_AXI_ABURST == C_INCR_BURST );\n assign access_is_wrap = ( S_AXI_ABURST == C_WRAP_BURST );\n assign cmd_fix_i = access_is_fix;\n \n // Get if it is allowed to modify transaction.\n assign access_is_modifiable = S_AXI_ACACHE[1];\n \n // Get SI-side maximum length to fit MI-side.\n always @ *\n begin\n case (S_AXI_ASIZE)\n 3'b000: si_maximum_length = C_S_AXI_NATIVE_SIZE >= 3'b000 ? C_DOUBLE_LEN[ 8-C_M_AXI_BYTES_LOG +: 8] : 8'b0;\n 3'b001: si_maximum_length = C_S_AXI_NATIVE_SIZE >= 3'b001 ? C_DOUBLE_LEN[ 9-C_M_AXI_BYTES_LOG +: 8] : 8'b0;\n 3'b010: si_maximum_length = C_S_AXI_NATIVE_SIZE >= 3'b010 ? C_DOUBLE_LEN[10-C_M_AXI_BYTES_LOG +: 8] : 8'b0;\n 3'b011: si_maximum_length = C_S_AXI_NATIVE_SIZE >= 3'b011 ? C_DOUBLE_LEN[11-C_M_AXI_BYTES_LOG +: 8] : 8'b0;\n 3'b100: si_maximum_length = C_S_AXI_NATIVE_SIZE >= 3'b100 ? C_DOUBLE_LEN[12-C_M_AXI_BYTES_LOG +: 8] : 8'b0;\n 3'b101: si_maximum_length = C_S_AXI_NATIVE_SIZE >= 3'b101 ? C_DOUBLE_LEN[13-C_M_AXI_BYTES_LOG +: 8] : 8'b0;\n 3'b110: si_maximum_length = C_S_AXI_NATIVE_SIZE >= 3'b110 ? C_DOUBLE_LEN[14-C_M_AXI_BYTES_LOG +: 8] : 8'b0;\n 3'b111: si_maximum_length = C_S_AXI_NATIVE_SIZE >= 3'b111 ? C_DOUBLE_LEN[15-C_M_AXI_BYTES_LOG +: 8] : 8'b0;\n endcase\n end\n \n // Help vector to determine the length of thransaction in the MI-side domain.\n assign mi_word_intra_len_complete = {S_AXI_ALEN, 8'b0};\n \n // Get intra MI-side word length bits (in bytes).\n always @ *\n begin\n if ( C_SUPPORT_BURSTS == 1 ) begin\n if ( ~cmd_fix_i ) begin\n case (S_AXI_ASIZE)\n 3'b000: mi_word_intra_len = C_S_AXI_NATIVE_SIZE >= 3'b000 ? \n mi_word_intra_len_complete[8-0 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}};\n 3'b001: mi_word_intra_len = C_S_AXI_NATIVE_SIZE >= 3'b001 ? \n mi_word_intra_len_complete[8-1 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}};\n 3'b010: mi_word_intra_len = C_S_AXI_NATIVE_SIZE >= 3'b010 ? \n mi_word_intra_len_complete[8-2 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}};\n 3'b011: mi_word_intra_len = C_S_AXI_NATIVE_SIZE >= 3'b011 ? \n mi_word_intra_len_complete[8-3 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}};\n 3'b100: mi_word_intra_len = C_S_AXI_NATIVE_SIZE >= 3'b100 ? \n mi_word_intra_len_complete[8-4 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}};\n 3'b101: mi_word_intra_len = C_S_AXI_NATIVE_SIZE >= 3'b101 ? \n mi_word_intra_len_complete[8-5 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}};\n 3'b110: mi_word_intra_len = C_S_AXI_NATIVE_SIZE >= 3'b110 ? \n mi_word_intra_len_complete[8-6 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}};\n 3'b111: mi_word_intra_len = C_S_AXI_NATIVE_SIZE >= 3'b111 ? \n mi_word_intra_len_complete[8-7 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}}; // Illegal setting.\n endcase\n end else begin\n mi_word_intra_len = {C_M_AXI_BYTES_LOG{1'b0}};\n end\n end else begin\n mi_word_intra_len = {C_M_AXI_BYTES_LOG{1'b0}};\n end\n end\n \n // Get MI-side length after upsizing.\n always @ *\n begin\n if ( C_SUPPORT_BURSTS == 1 ) begin\n if ( cmd_fix_i | ~cmd_modified_i ) begin\n // Fix has to maintain length even if forced packing.\n upsized_length = S_AXI_ALEN;\n end else begin\n case (S_AXI_ASIZE)\n 3'b000: upsized_length = C_S_AXI_NATIVE_SIZE >= 3'b000 ? \n (S_AXI_ALEN >> C_M_AXI_BYTES_LOG-0) : 8'b0;\n 3'b001: upsized_length = C_S_AXI_NATIVE_SIZE >= 3'b001 ? \n (S_AXI_ALEN >> C_M_AXI_BYTES_LOG-1) : 8'b0;\n 3'b010: upsized_length = C_S_AXI_NATIVE_SIZE >= 3'b010 ? \n (S_AXI_ALEN >> C_M_AXI_BYTES_LOG-2) : 8'b0;\n 3'b011: upsized_length = C_S_AXI_NATIVE_SIZE >= 3'b011 ? \n (S_AXI_ALEN >> C_M_AXI_BYTES_LOG-3) : 8'b0;\n 3'b100: upsized_length = C_S_AXI_NATIVE_SIZE >= 3'b100 ? \n (S_AXI_ALEN >> C_M_AXI_BYTES_LOG-4) : 8'b0;\n 3'b101: upsized_length = C_S_AXI_NATIVE_SIZE >= 3'b101 ? \n (S_AXI_ALEN >> C_M_AXI_BYTES_LOG-5) : 8'b0;\n 3'b110: upsized_length = C_S_AXI_NATIVE_SIZE >= 3'b110 ? \n (S_AXI_ALEN >> C_M_AXI_BYTES_LOG-6) : 8'b0;\n 3'b111: upsized_length = C_S_AXI_NATIVE_SIZE >= 3'b111 ? \n (S_AXI_ALEN ) : 8'b0; // Illegal setting.\n endcase\n end\n end else begin\n upsized_length = 8'b0;\n end\n end\n \n // Generate address bits used for SI-side transaction size.\n always @ *\n begin\n case (S_AXI_ASIZE)\n 3'b000: size_mask = ~C_DOUBLE_LEN[8 +: C_S_AXI_BYTES_LOG];\n 3'b001: size_mask = ~C_DOUBLE_LEN[7 +: C_S_AXI_BYTES_LOG];\n 3'b010: size_mask = ~C_DOUBLE_LEN[6 +: C_S_AXI_BYTES_LOG];\n 3'b011: size_mask = ~C_DOUBLE_LEN[5 +: C_S_AXI_BYTES_LOG];\n 3'b100: size_mask = ~C_DOUBLE_LEN[4 +: C_S_AXI_BYTES_LOG];\n 3'b101: size_mask = ~C_DOUBLE_LEN[3 +: C_S_AXI_BYTES_LOG];\n 3'b110: size_mask = ~C_DOUBLE_LEN[2 +: C_S_AXI_BYTES_LOG];\n 3'b111: size_mask = ~C_DOUBLE_LEN[1 +: C_S_AXI_BYTES_LOG]; // Illegal setting.\n endcase\n end\n \n // Help vector to determine the length of thransaction in the MI-side domain.\n assign mask_help_vector = {4'b0, S_AXI_ALEN, 8'b1};\n \n // Calculate the address bits that are affected when a complete wrap is detected.\n always @ *\n begin\n if ( sub_sized_wrap & ( C_SUPPORT_BURSTS == 1 ) ) begin\n case (S_AXI_ASIZE)\n 3'b000: cmd_mask_i = C_S_AXI_NATIVE_SIZE >= 3'b000 ? \n mask_help_vector[8-0 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}};\n 3'b001: cmd_mask_i = C_S_AXI_NATIVE_SIZE >= 3'b000 ? \n mask_help_vector[8-1 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}};\n 3'b010: cmd_mask_i = C_S_AXI_NATIVE_SIZE >= 3'b000 ? \n mask_help_vector[8-2 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}};\n 3'b011: cmd_mask_i = C_S_AXI_NATIVE_SIZE >= 3'b000 ? \n mask_help_vector[8-3 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}};\n 3'b100: cmd_mask_i = C_S_AXI_NATIVE_SIZE >= 3'b000 ? \n mask_help_vector[8-4 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}};\n 3'b101: cmd_mask_i = C_S_AXI_NATIVE_SIZE >= 3'b000 ? \n mask_help_vector[8-5 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}};\n 3'b110: cmd_mask_i = C_S_AXI_NATIVE_SIZE >= 3'b000 ? \n mask_help_vector[8-6 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}};\n 3'b111: cmd_mask_i = C_S_AXI_NATIVE_SIZE >= 3'b000 ? \n mask_help_vector[8-7 +: C_M_AXI_BYTES_LOG] : {C_M_AXI_BYTES_LOG{1'b0}}; // Illegal setting.\n endcase\n end else begin\n cmd_mask_i = {C_M_AXI_BYTES_LOG{1'b1}};\n end\n end\n\n // Calculate the address bits that are affected when a complete wrap is detected.\n always @ *\n begin\n case (S_AXI_ASIZE)\n 3'b000: burst_mask = C_S_AXI_NATIVE_SIZE >= 3'b000 ? \n mask_help_vector[8-0 +: C_BURST_BYTES_LOG] : {C_BURST_BYTES_LOG{1'b0}};\n 3'b001: burst_mask = C_S_AXI_NATIVE_SIZE >= 3'b000 ? \n mask_help_vector[8-1 +: C_BURST_BYTES_LOG] : {C_BURST_BYTES_LOG{1'b0}};\n 3'b010: burst_mask = C_S_AXI_NATIVE_SIZE >= 3'b000 ? \n mask_help_vector[8-2 +: C_BURST_BYTES_LOG] : {C_BURST_BYTES_LOG{1'b0}};\n 3'b011: burst_mask = C_S_AXI_NATIVE_SIZE >= 3'b000 ? \n mask_help_vector[8-3 +: C_BURST_BYTES_LOG] : {C_BURST_BYTES_LOG{1'b0}};\n 3'b100: burst_mask = C_S_AXI_NATIVE_SIZE >= 3'b000 ? \n mask_help_vector[8-4 +: C_BURST_BYTES_LOG] : {C_BURST_BYTES_LOG{1'b0}};\n 3'b101: burst_mask = C_S_AXI_NATIVE_SIZE >= 3'b000 ? \n mask_help_vector[8-5 +: C_BURST_BYTES_LOG] : {C_BURST_BYTES_LOG{1'b0}};\n 3'b110: burst_mask = C_S_AXI_NATIVE_SIZE >= 3'b000 ? \n mask_help_vector[8-6 +: C_BURST_BYTES_LOG] : {C_BURST_BYTES_LOG{1'b0}};\n 3'b111: burst_mask = C_S_AXI_NATIVE_SIZE >= 3'b000 ? \n mask_help_vector[8-7 +: C_BURST_BYTES_LOG] : {C_BURST_BYTES_LOG{1'b0}}; // Illegal setting.\n endcase\n end\n\n // Propagate the SI-side size of the transaction.\n assign cmd_size_i = S_AXI_ASIZE;\n \n // Detect if there is any unalignment in regards to the MI-side.\n assign access_is_unaligned = ( S_AXI_AADDR[0 +: C_M_AXI_BYTES_LOG] != {C_M_AXI_BYTES_LOG{1'b0}} );\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Evaluate if transaction is to be translated:\n // * Forcefully translate when C_PACKING_LEVEL is set to C_ALWAYS_PACK. \n // * When SI-side transaction size is native, it is allowed and default \n // packing is set. (Expander mode never packs).\n //\n /////////////////////////////////////////////////////////////////////////////\n \n // Modify transaction forcefully or when transaction allows it\n assign cmd_modified_i = ~access_is_fix &\n ( ( C_PACKING_LEVEL == C_ALWAYS_PACK ) | \n ( access_is_modifiable & ( S_AXI_ALEN != 8'b0 ) & ( C_PACKING_LEVEL == C_DEFAULT_PACK ) ) );\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Translate SI-side access to MI-side:\n //\n // Detemine if this is a complete WRAP. Conditions are that it must fit \n // inside a single MI-side data word, it must be a WRAP access and that\n // bursts are allowed. Without burst there can never be a WRAP access.\n //\n // Determine if this ia a packed WRAP, i.e. a WRAP that is to large to \n // be a complete wrap and it is unaligned SI-side address relative to \n // the native MI-side data width.\n //\n // The address for the First SI-side data word is adjusted to when there \n // is a complete WRAP, otherwise it only the least significant bits of the \n // SI-side address.\n // For complete WRAP access the Offset is generated as the most significant \n // bits that are left by the Mask.\n // Last address is calculated with the adjusted First word address.\n //\n // The Adjusted MI-side burst length is calculated as the Upsized length\n // plus one when the SI-side data must wrap on the MI-side (unless it is\n // a complete or packed WRAP).\n // \n // Depending on the conditions some of the forwarded MI-side tranaction \n // and Command Queue parameters has to be adjusted:\n // * For unmodified transaction the parameter are left un affected.\n // (M_AXI_AADDR, M_AXI_ASIZE, M_AXI_ABURST, M_AXI_ALEN and cmd_length \n // are untouched)\n // * For complete WRAP transactions the burst type is changed to INCR\n // and the address is adjusted to the sub-size affected by the transaction\n // (the sub-size can be 2 bytes up to a full MI-side data word).\n // The size is set to the native MI-side transaction size. And the length\n // is set to the calculated upsized length.\n // * For all other modified transations the address and burst type remains \n // the same. The length is adjusted to the previosly described length\n // and size is set to native MI-side transaction size.\n //\n /////////////////////////////////////////////////////////////////////////////\n \n // Detemine if this is a sub-sized transaction.\n assign sub_sized_wrap = access_is_wrap & ( S_AXI_ALEN <= si_maximum_length ) & \n ( C_SUPPORT_BURSTS == 1);\n \n // See if entite burst can fit inside one MI-side word.\n assign cmd_complete_wrap_i = cmd_modified_i & sub_sized_wrap;\n \n // Detect if this is a packed WRAP (multiple MI-side words).\n assign cmd_packed_wrap_i = cmd_modified_i & access_is_wrap & ( S_AXI_ALEN > si_maximum_length ) & \n access_is_unaligned & ( C_SUPPORT_BURSTS == 1);\n \n // Get unalignment address bits (including aligning it inside covered area).\n assign cmd_first_word_ii = S_AXI_AADDR[C_M_AXI_BYTES_LOG-1:0];\n assign cmd_first_word_i = cmd_first_word_ii & cmd_mask_i & size_mask;\n \n // Generate next word address.\n assign cmd_next_word_ii = cmd_first_word_ii + cmd_step_ii[C_M_AXI_BYTES_LOG-1:0];\n assign cmd_next_word_i = cmd_next_word_ii & cmd_mask_i & size_mask;\n \n // Offset is the bits that is outside of the Mask.\n assign cmd_offset_i = cmd_first_word_ii & ~cmd_mask_i;\n \n // Select RTL or Optimized implementation.\n generate\n if ( C_FAMILY == \"rtl\" ) begin : USE_RTL_ADJUSTED_LEN\n // Calculate Last word on MI-side.\n assign cmd_last_word_ii = cmd_first_word_i + mi_word_intra_len;\n assign cmd_last_word_i = cmd_last_word_ii[C_M_AXI_BYTES_LOG-1:0] & cmd_mask_i & size_mask;\n \n // Detect if extra word on MI-side is needed.\n assign access_need_extra_word = cmd_last_word_ii[C_M_AXI_BYTES_LOG] & \n access_is_incr & cmd_modified_i;\n \n // Calculate true length of modified transaction.\n assign adjusted_length = upsized_length + access_need_extra_word;\n \n end else begin : USE_FPGA_ADJUSTED_LEN\n \n wire [C_M_AXI_BYTES_LOG:0] last_word_local_carry;\n wire [C_M_AXI_BYTES_LOG-1:0] last_word_sel;\n wire [C_M_AXI_BYTES_LOG:0] last_word_for_mask_local_carry;\n wire [C_M_AXI_BYTES_LOG-1:0] last_word_for_mask_dummy_carry1;\n wire [C_M_AXI_BYTES_LOG-1:0] last_word_for_mask_dummy_carry2;\n wire [C_M_AXI_BYTES_LOG-1:0] last_word_for_mask_dummy_carry3;\n wire [C_M_AXI_BYTES_LOG-1:0] last_word_for_mask_sel;\n wire [C_M_AXI_BYTES_LOG-1:0] last_word_for_mask;\n wire [C_M_AXI_BYTES_LOG-1:0] last_word_mask;\n wire sel_access_need_extra_word;\n wire [8:0] adjusted_length_local_carry;\n wire [8-1:0] adjusted_length_sel;\n \n \n assign last_word_local_carry[0] = 1'b0;\n assign last_word_for_mask_local_carry[0] = 1'b0;\n \n for (bit_cnt = 0; bit_cnt < C_M_AXI_BYTES_LOG ; bit_cnt = bit_cnt + 1) begin : LUT_LAST_MASK\n \n assign last_word_for_mask_sel[bit_cnt] = cmd_first_word_ii[bit_cnt] ^ mi_word_intra_len[bit_cnt];\n assign last_word_mask[bit_cnt] = cmd_mask_i[bit_cnt] & size_mask[bit_cnt];\n \n MUXCY and_inst1 \n (\n .O (last_word_for_mask_dummy_carry1[bit_cnt]), \n .CI (last_word_for_mask_local_carry[bit_cnt]), \n .DI (mi_word_intra_len[bit_cnt]), \n .S (last_word_for_mask_sel[bit_cnt])\n ); \n \n MUXCY and_inst2 \n (\n .O (last_word_for_mask_dummy_carry2[bit_cnt]), \n .CI (last_word_for_mask_dummy_carry1[bit_cnt]), \n .DI (1'b0), \n .S (1'b1)\n ); \n \n MUXCY and_inst3 \n (\n .O (last_word_for_mask_dummy_carry3[bit_cnt]), \n .CI (last_word_for_mask_dummy_carry2[bit_cnt]), \n .DI (1'b0), \n .S (1'b1)\n ); \n \n MUXCY and_inst4 \n (\n .O (last_word_for_mask_local_carry[bit_cnt+1]), \n .CI (last_word_for_mask_dummy_carry3[bit_cnt]), \n .DI (1'b0), \n .S (1'b1)\n ); \n \n XORCY xorcy_inst \n (\n .O(last_word_for_mask[bit_cnt]),\n .CI(last_word_for_mask_local_carry[bit_cnt]),\n .LI(last_word_for_mask_sel[bit_cnt])\n );\n \n mig_7series_v4_0_ddr_carry_latch_and #\n (\n .C_FAMILY(C_FAMILY)\n ) last_mask_inst\n (\n .CIN(last_word_for_mask[bit_cnt]),\n .I(last_word_mask[bit_cnt]),\n .O(cmd_last_word_i[bit_cnt])\n );\n \n end // end for bit_cnt\n \n for (bit_cnt = 0; bit_cnt < C_M_AXI_BYTES_LOG ; bit_cnt = bit_cnt + 1) begin : LUT_LAST\n \n assign last_word_sel[bit_cnt] = cmd_first_word_ii[bit_cnt] ^ mi_word_intra_len[bit_cnt];\n \n MUXCY and_inst \n (\n .O (last_word_local_carry[bit_cnt+1]), \n .CI (last_word_local_carry[bit_cnt]), \n .DI (mi_word_intra_len[bit_cnt]), \n .S (last_word_sel[bit_cnt])\n ); \n \n XORCY xorcy_inst \n (\n .O(cmd_last_word_ii[bit_cnt]),\n .CI(last_word_local_carry[bit_cnt]),\n .LI(last_word_sel[bit_cnt])\n );\n \n end // end for bit_cnt\n \n assign sel_access_need_extra_word = access_is_incr & cmd_modified_i;\n \n mig_7series_v4_0_ddr_carry_and #\n (\n .C_FAMILY(C_FAMILY)\n ) access_need_extra_word_inst\n (\n .CIN(last_word_local_carry[C_M_AXI_BYTES_LOG]),\n .S(sel_access_need_extra_word),\n .COUT(adjusted_length_local_carry[0])\n );\n \n for (bit_cnt = 0; bit_cnt < 8 ; bit_cnt = bit_cnt + 1) begin : LUT_ADJUST\n \n assign adjusted_length_sel[bit_cnt] = ( upsized_length[bit_cnt] & cmd_modified_i) |\n ( S_AXI_ALEN[bit_cnt] & ~cmd_modified_i);\n \n MUXCY and_inst \n (\n .O (adjusted_length_local_carry[bit_cnt+1]), \n .CI (adjusted_length_local_carry[bit_cnt]), \n .DI (1'b0), \n .S (adjusted_length_sel[bit_cnt])\n ); \n \n XORCY xorcy_inst \n (\n .O(adjusted_length[bit_cnt]),\n .CI(adjusted_length_local_carry[bit_cnt]),\n .LI(adjusted_length_sel[bit_cnt])\n );\n \n end // end for bit_cnt\n \n end\n endgenerate\n \n // Generate adjusted wrap address.\n assign wrap_addr_aligned = ( C_AXI_CHANNEL != 0 ) ? \n ( S_AXI_AADDR[0 +: C_BURST_BYTES_LOG] ) :\n ( S_AXI_AADDR[0 +: C_BURST_BYTES_LOG] + ( 2 ** C_M_AXI_BYTES_LOG ) );\n \n // Select directly forwarded or modified transaction.\n always @ *\n begin\n if ( cmd_modified_i ) begin\n // SI to MI-side transaction translation.\n if ( cmd_complete_wrap_i ) begin\n // Complete wrap is turned into incr\n M_AXI_AADDR_I = S_AXI_AADDR & {{C_MI_UNUSED_LOG{1'b1}}, ~cmd_mask_i};\n M_AXI_ABURST_I = C_INCR_BURST;\n \n end else begin\n // Retain the currenent \n if ( cmd_packed_wrap_i ) begin\n M_AXI_AADDR_I = {S_AXI_AADDR[C_BURST_BYTES_LOG +: C_AXI_ADDR_WIDTH-C_BURST_BYTES_LOG], \n (S_AXI_AADDR[0 +: C_BURST_BYTES_LOG] & ~burst_mask) | (wrap_addr_aligned & burst_mask) } & \n {{C_MI_UNUSED_LOG{1'b1}}, ~cmd_mask_i};\n end else begin\n M_AXI_AADDR_I = S_AXI_AADDR;\n end\n M_AXI_ABURST_I = S_AXI_ABURST;\n \n end\n \n M_AXI_ASIZE_I = C_M_AXI_NATIVE_SIZE;\n end else begin\n // SI to MI-side transaction forwarding.\n M_AXI_AADDR_I = S_AXI_AADDR;\n M_AXI_ASIZE_I = S_AXI_ASIZE;\n M_AXI_ABURST_I = S_AXI_ABURST;\n end\n \n M_AXI_ALEN_I = adjusted_length;\n cmd_length_i = adjusted_length;\n end\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Forward the command to the MI-side interface.\n //\n // It is determined that this is an allowed command/access when there is \n // room in the command queue (and it passes any ID checks as required).\n //\n /////////////////////////////////////////////////////////////////////////////\n \n // Select RTL or Optimized implementation.\n generate\n if ( C_FAMILY == \"rtl\" || ( C_SINGLE_THREAD == 0 ) ) begin : USE_RTL_AVALID\n // Only allowed to forward translated command when command queue is ok with it.\n assign M_AXI_AVALID_I = allow_new_cmd & S_AXI_AVALID;\n \n end else begin : USE_FPGA_AVALID\n \n wire sel_s_axi_avalid;\n \n assign sel_s_axi_avalid = S_AXI_AVALID & ~ARESET;\n \n mig_7series_v4_0_ddr_carry_and #\n (\n .C_FAMILY(C_FAMILY)\n ) avalid_inst\n (\n .CIN(allow_new_cmd),\n .S(sel_s_axi_avalid),\n .COUT(M_AXI_AVALID_I)\n );\n \n end\n endgenerate\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Simple transfer of paramters that doesn't need to be adjusted.\n //\n // ID - Transaction still recognized with the same ID.\n // LOCK - No need to change exclusive or barrier transactions.\n // CACHE - No need to change the chache features. Even if the modyfiable\n // bit is overridden (forcefully) there is no need to let downstream\n // component beleive it is ok to modify it further.\n // PROT - Security level of access is not changed when upsizing.\n // REGION - Address region stays the same.\n // QOS - Quality of Service remains the same.\n // USER - User bits remains the same.\n // \n /////////////////////////////////////////////////////////////////////////////\n \n assign M_AXI_AID_I = S_AXI_AID;\n assign M_AXI_ALOCK_I = S_AXI_ALOCK;\n assign M_AXI_ACACHE_I = S_AXI_ACACHE;\n assign M_AXI_APROT_I = S_AXI_APROT;\n assign M_AXI_AREGION_I = S_AXI_AREGION;\n assign M_AXI_AQOS_I = S_AXI_AQOS;\n assign M_AXI_AUSER_I = ( C_AXI_SUPPORTS_USER_SIGNALS ) ? S_AXI_AUSER : {C_AXI_AUSER_WIDTH{1'b0}};\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Command queue to W/R channel.\n // \n // Commands can be pushed into the Cmd FIFO even if MI-side is stalling.\n // A flag is set if MI-side is stalling when Command is pushed to the \n // Cmd FIFO. This will prevent multiple push of the same Command as well as\n // keeping the MI-side Valid signal if the Allow Cmd requirement has been \n // updated to disable furter Commands (I.e. it is made sure that the SI-side \n // Command has been forwarded to both Cmd FIFO and MI-side).\n // \n // It is allowed to continue pushing new commands as long as\n // * There is room in the queue\n // * The ID is the same as previously queued. Since data is not reordered\n // for the same ID it is ok to let them proceed.\n //\n /////////////////////////////////////////////////////////////////////////////\n \n // Keep track of current ID in queue.\n always @ (posedge ACLK) begin\n if (ARESET) begin\n queue_id <= {C_AXI_ID_WIDTH{1'b0}};\n end else begin\n if ( cmd_push ) begin\n // Store ID (it will be matching ID or a \"new beginning\").\n queue_id <= S_AXI_AID;\n end\n end\n end\n \n // Select RTL or Optimized implementation.\n generate\n if ( C_FAMILY == \"rtl\" || ( C_SINGLE_THREAD == 0 ) ) begin : USE_RTL_ID_MATCH\n // Check ID to make sure this command is allowed.\n assign id_match = ( C_SINGLE_THREAD == 0 ) | ( queue_id == S_AXI_AID);\n assign cmd_id_check = cmd_empty | ( id_match & ~cmd_empty );\n \n // Check if it is allowed to push more commands (ID is allowed and there is room in the queue).\n assign allow_new_cmd = (~cmd_full & cmd_id_check) | cmd_push_block;\n \n // Push new command when allowed and MI-side is able to receive the command.\n assign cmd_push = M_AXI_AVALID_I & ~cmd_push_block;\n \n end else begin : USE_FPGA_ID_MATCH\n \n wire cmd_id_check_i;\n wire allow_new_cmd_i;\n wire sel_cmd_id_check;\n wire sel_cmd_push;\n \n mig_7series_v4_0_ddr_comparator #\n (\n .C_FAMILY(C_FAMILY),\n .C_DATA_WIDTH(C_AXI_ID_WIDTH)\n ) id_match_inst\n (\n .CIN(1'b1),\n .A(queue_id),\n .B(S_AXI_AID),\n .COUT(id_match)\n );\n \n assign sel_cmd_id_check = ~cmd_empty;\n \n mig_7series_v4_0_ddr_carry_and #\n (\n .C_FAMILY(C_FAMILY)\n ) cmd_id_check_inst_1\n (\n .CIN(id_match),\n .S(sel_cmd_id_check),\n .COUT(cmd_id_check_i)\n );\n\n mig_7series_v4_0_ddr_carry_or #\n (\n .C_FAMILY(C_FAMILY)\n ) cmd_id_check_inst_2\n (\n .CIN(cmd_id_check_i),\n .S(cmd_empty),\n .COUT(cmd_id_check)\n );\n \n mig_7series_v4_0_ddr_carry_and #\n (\n .C_FAMILY(C_FAMILY)\n ) allow_new_cmd_inst_1\n (\n .CIN(cmd_id_check),\n .S(s_ready),\n .COUT(allow_new_cmd_i)\n );\n\n mig_7series_v4_0_ddr_carry_or #\n (\n .C_FAMILY(C_FAMILY)\n ) allow_new_cmd_inst_2\n (\n .CIN(allow_new_cmd_i),\n .S(cmd_push_block),\n .COUT(allow_new_cmd)\n );\n \n assign sel_cmd_push = ~cmd_push_block;\n \n mig_7series_v4_0_ddr_carry_and #\n (\n .C_FAMILY(C_FAMILY)\n ) cmd_push_inst\n (\n .CIN(M_AXI_AVALID_I),\n .S(sel_cmd_push),\n .COUT(cmd_push)\n );\n\n end\n endgenerate\n \n // Block furter push until command has been forwarded to MI-side.\n always @ (posedge ACLK) begin\n if (ARESET) begin\n cmd_push_block <= 1'b0;\n end else begin\n cmd_push_block <= M_AXI_AVALID_I & ~M_AXI_AREADY_I;\n end\n end\n \n // Acknowledge command when we can push it into queue (and forward it).\n assign S_AXI_AREADY_I = M_AXI_AREADY_I & allow_new_cmd & ~ARESET;\n assign S_AXI_AREADY = S_AXI_AREADY_I;\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Command Queue:\n // \n // Instantiate a FIFO as the queue and adjust the control signals.\n //\n // Decode size to step before passing it along.\n //\n // When there is no need for bursts the command FIFO can be greatly reduced \n // becase the following is always true:\n // * first = last\n // * length = 0\n // * nothing can be packed (i.e. no WRAP at all)\n // * never any sub-size wraping => static offset (0) and mask (1)\n // \n /////////////////////////////////////////////////////////////////////////////\n \n // Translate SI-side size to step for upsizer function.\n always @ *\n begin\n case (cmd_size_i)\n 3'b000: cmd_step_ii = 8'b00000001;\n 3'b001: cmd_step_ii = 8'b00000010;\n 3'b010: cmd_step_ii = 8'b00000100;\n 3'b011: cmd_step_ii = 8'b00001000;\n 3'b100: cmd_step_ii = 8'b00010000;\n 3'b101: cmd_step_ii = 8'b00100000;\n 3'b110: cmd_step_ii = 8'b01000000;\n 3'b111: cmd_step_ii = 8'b10000000; // Illegal setting.\n endcase\n end\n \n // Get only the applicable bits in step.\n assign cmd_step_i = cmd_step_ii[C_S_AXI_BYTES_LOG:0];\n \n // Instantiated queue.\n generate\n if (C_SUPPORT_BURSTS == 1) begin : USE_BURSTS\n mig_7series_v4_0_ddr_command_fifo #\n (\n .C_FAMILY (C_FAMILY),\n .C_ENABLE_S_VALID_CARRY (1),\n .C_ENABLE_REGISTERED_OUTPUT (1),\n .C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG),\n .C_FIFO_WIDTH (1+1+1+1+C_M_AXI_BYTES_LOG+C_M_AXI_BYTES_LOG+\n C_M_AXI_BYTES_LOG+C_M_AXI_BYTES_LOG+C_M_AXI_BYTES_LOG+C_S_AXI_BYTES_LOG+1+8)\n ) \n cmd_queue\n (\n .ACLK (ACLK),\n .ARESET (ARESET),\n .EMPTY (cmd_empty),\n .S_MESG ({cmd_fix_i, cmd_modified_i, cmd_complete_wrap_i, cmd_packed_wrap_i, cmd_first_word_i, cmd_next_word_i, \n cmd_last_word_i, cmd_offset_i, cmd_mask_i, cmd_step_i, cmd_length_i}),\n .S_VALID (cmd_push),\n .S_READY (s_ready),\n .M_MESG ({cmd_fix, cmd_modified, cmd_complete_wrap, cmd_packed_wrap, cmd_first_word, cmd_next_word, \n cmd_last_word, cmd_offset, cmd_mask, cmd_step, cmd_length}),\n .M_VALID (cmd_valid_i),\n .M_READY (cmd_ready)\n );\n end else begin : NO_BURSTS\n \n wire [C_M_AXI_BYTES_LOG-1:0] cmd_first_word_out;\n \n mig_7series_v4_0_ddr_command_fifo #\n (\n .C_FAMILY (C_FAMILY),\n .C_ENABLE_S_VALID_CARRY (1),\n .C_ENABLE_REGISTERED_OUTPUT (1),\n .C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG),\n .C_FIFO_WIDTH (1+C_M_AXI_BYTES_LOG+C_S_AXI_BYTES_LOG+1)\n ) \n cmd_queue\n (\n .ACLK (ACLK),\n .ARESET (ARESET),\n .EMPTY (cmd_empty),\n .S_MESG ({cmd_fix_i, cmd_first_word_i, cmd_step_i}),\n .S_VALID (cmd_push),\n .S_READY (s_ready),\n .M_MESG ({cmd_fix, cmd_first_word_out, cmd_step}),\n .M_VALID (cmd_valid_i),\n .M_READY (cmd_ready)\n );\n \n assign cmd_modified = ( C_PACKING_LEVEL == C_ALWAYS_PACK ) ? 1'b1 : 1'b0;\n assign cmd_complete_wrap = 1'b0;\n assign cmd_packed_wrap = 1'b0;\n assign cmd_first_word = cmd_first_word_out;\n assign cmd_next_word = cmd_first_word_out;\n assign cmd_last_word = cmd_first_word_out;\n assign cmd_offset = {C_M_AXI_BYTES_LOG{1'b0}};\n assign cmd_mask = {C_M_AXI_BYTES_LOG{1'b1}};\n assign cmd_length = 8'b0;\n end\n endgenerate\n\n // Queue is concidered full when not ready.\n assign cmd_full = ~s_ready;\n \n // Assign external signal.\n assign cmd_valid = cmd_valid_i;\n \n \n /////////////////////////////////////////////////////////////////////////////\n // MI-side output handling\n /////////////////////////////////////////////////////////////////////////////\n \n generate\n if ( C_M_AXI_REGISTER ) begin : USE_REGISTER\n \n reg [C_AXI_ID_WIDTH-1:0] M_AXI_AID_q;\n reg [C_AXI_ADDR_WIDTH-1:0] M_AXI_AADDR_q;\n reg [8-1:0] M_AXI_ALEN_q;\n reg [3-1:0] M_AXI_ASIZE_q;\n reg [2-1:0] M_AXI_ABURST_q;\n reg [2-1:0] M_AXI_ALOCK_q;\n reg [4-1:0] M_AXI_ACACHE_q;\n reg [3-1:0] M_AXI_APROT_q;\n reg [4-1:0] M_AXI_AREGION_q;\n reg [4-1:0] M_AXI_AQOS_q;\n reg [C_AXI_AUSER_WIDTH-1:0] M_AXI_AUSER_q;\n reg M_AXI_AVALID_q;\n \n // Register MI-side Data.\n always @ (posedge ACLK) begin\n if (ARESET) begin\n M_AXI_AVALID_q <= 1'b0;\n end else if ( M_AXI_AREADY_I ) begin\n M_AXI_AVALID_q <= M_AXI_AVALID_I;\n end\n\n if ( M_AXI_AREADY_I ) begin\n M_AXI_AID_q <= M_AXI_AID_I;\n M_AXI_AADDR_q <= M_AXI_AADDR_I;\n M_AXI_ALEN_q <= M_AXI_ALEN_I;\n M_AXI_ASIZE_q <= M_AXI_ASIZE_I;\n M_AXI_ABURST_q <= M_AXI_ABURST_I;\n M_AXI_ALOCK_q <= M_AXI_ALOCK_I;\n M_AXI_ACACHE_q <= M_AXI_ACACHE_I;\n M_AXI_APROT_q <= M_AXI_APROT_I;\n M_AXI_AREGION_q <= M_AXI_AREGION_I;\n M_AXI_AQOS_q <= M_AXI_AQOS_I;\n M_AXI_AUSER_q <= M_AXI_AUSER_I;\n end\n end\n \n assign M_AXI_AID = M_AXI_AID_q;\n assign M_AXI_AADDR = M_AXI_AADDR_q;\n assign M_AXI_ALEN = M_AXI_ALEN_q;\n assign M_AXI_ASIZE = M_AXI_ASIZE_q;\n assign M_AXI_ABURST = M_AXI_ABURST_q;\n assign M_AXI_ALOCK = M_AXI_ALOCK_q;\n assign M_AXI_ACACHE = M_AXI_ACACHE_q;\n assign M_AXI_APROT = M_AXI_APROT_q;\n assign M_AXI_AREGION = M_AXI_AREGION_q;\n assign M_AXI_AQOS = M_AXI_AQOS_q;\n assign M_AXI_AUSER = M_AXI_AUSER_q;\n assign M_AXI_AVALID = M_AXI_AVALID_q;\n assign M_AXI_AREADY_I = ( M_AXI_AVALID_q & M_AXI_AREADY) | ~M_AXI_AVALID_q;\n \n end else begin : NO_REGISTER\n \n // Combinatorial MI-side Data.\n assign M_AXI_AID = M_AXI_AID_I;\n assign M_AXI_AADDR = M_AXI_AADDR_I;\n assign M_AXI_ALEN = M_AXI_ALEN_I;\n assign M_AXI_ASIZE = M_AXI_ASIZE_I;\n assign M_AXI_ABURST = M_AXI_ABURST_I;\n assign M_AXI_ALOCK = M_AXI_ALOCK_I;\n assign M_AXI_ACACHE = M_AXI_ACACHE_I;\n assign M_AXI_APROT = M_AXI_APROT_I;\n assign M_AXI_AREGION = M_AXI_AREGION_I;\n assign M_AXI_AQOS = M_AXI_AQOS_I;\n assign M_AXI_AUSER = M_AXI_AUSER_I;\n assign M_AXI_AVALID = M_AXI_AVALID_I;\n assign M_AXI_AREADY_I = M_AXI_AREADY;\n \n end\n endgenerate\n \n \nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_axi_register_slice.v", "content": "// -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// AXI Register Slice\n// Register selected channels on the forward and/or reverse signal paths.\n// 5-channel memory-mapped AXI4 interfaces.\n//\n// Verilog-standard: Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n// ddr_axi_register_slice\n// ddr_axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule mig_7series_v4_0_ddr_axi_register_slice #\n (\n parameter C_FAMILY = \"virtex6\",\n parameter integer C_AXI_ID_WIDTH = 4,\n parameter integer C_AXI_ADDR_WIDTH = 32,\n parameter integer C_AXI_DATA_WIDTH = 32,\n parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,\n parameter integer C_AXI_AWUSER_WIDTH = 1,\n parameter integer C_AXI_ARUSER_WIDTH = 1,\n parameter integer C_AXI_WUSER_WIDTH = 1,\n parameter integer C_AXI_RUSER_WIDTH = 1,\n parameter integer C_AXI_BUSER_WIDTH = 1,\n // C_REG_CONFIG_*:\n // 0 => BYPASS = The channel is just wired through the module.\n // 1 => FWD_REV = Both FWD and REV (fully-registered)\n // 2 => FWD = The master VALID and payload signals are registrated. \n // 3 => REV = The slave ready signal is registrated\n // 4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.\n // 5 => SLAVE_RDY = All slave side signals and master READY are registrated.\n // 6 => INPUTS = Slave and Master side inputs are registrated.\n // 7 => LIGHT_WT = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n parameter C_REG_CONFIG_AW = 32'h00000000,\n parameter C_REG_CONFIG_W = 32'h00000000,\n parameter C_REG_CONFIG_B = 32'h00000000,\n parameter C_REG_CONFIG_AR = 32'h00000000,\n parameter C_REG_CONFIG_R = 32'h00000000\n )\n (\n // System Signals\n input wire ACLK,\n input wire ARESETN,\n\n // Slave Interface Write Address Ports\n input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,\n input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,\n input wire [8-1:0] S_AXI_AWLEN,\n input wire [3-1:0] S_AXI_AWSIZE,\n input wire [2-1:0] S_AXI_AWBURST,\n input wire [2-1:0] S_AXI_AWLOCK,\n input wire [4-1:0] S_AXI_AWCACHE,\n input wire [3-1:0] S_AXI_AWPROT,\n input wire [4-1:0] S_AXI_AWREGION,\n input wire [4-1:0] S_AXI_AWQOS,\n input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,\n input wire S_AXI_AWVALID,\n output wire S_AXI_AWREADY,\n\n // Slave Interface Write Data Ports\n input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,\n input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,\n input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,\n input wire S_AXI_WLAST,\n input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,\n input wire S_AXI_WVALID,\n output wire S_AXI_WREADY,\n\n // Slave Interface Write Response Ports\n output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,\n output wire [2-1:0] S_AXI_BRESP,\n output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,\n output wire S_AXI_BVALID,\n input wire S_AXI_BREADY,\n\n // Slave Interface Read Address Ports\n input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,\n input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,\n input wire [8-1:0] S_AXI_ARLEN,\n input wire [3-1:0] S_AXI_ARSIZE,\n input wire [2-1:0] S_AXI_ARBURST,\n input wire [2-1:0] S_AXI_ARLOCK,\n input wire [4-1:0] S_AXI_ARCACHE,\n input wire [3-1:0] S_AXI_ARPROT,\n input wire [4-1:0] S_AXI_ARREGION,\n input wire [4-1:0] S_AXI_ARQOS,\n input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,\n input wire S_AXI_ARVALID,\n output wire S_AXI_ARREADY,\n\n // Slave Interface Read Data Ports\n output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,\n output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,\n output wire [2-1:0] S_AXI_RRESP,\n output wire S_AXI_RLAST,\n output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,\n output wire S_AXI_RVALID,\n input wire S_AXI_RREADY,\n \n // Master Interface Write Address Port\n output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,\n output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,\n output wire [8-1:0] M_AXI_AWLEN,\n output wire [3-1:0] M_AXI_AWSIZE,\n output wire [2-1:0] M_AXI_AWBURST,\n output wire [2-1:0] M_AXI_AWLOCK,\n output wire [4-1:0] M_AXI_AWCACHE,\n output wire [3-1:0] M_AXI_AWPROT,\n output wire [4-1:0] M_AXI_AWREGION,\n output wire [4-1:0] M_AXI_AWQOS,\n output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,\n output wire M_AXI_AWVALID,\n input wire M_AXI_AWREADY,\n \n // Master Interface Write Data Ports\n output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,\n output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,\n output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,\n output wire M_AXI_WLAST,\n output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,\n output wire M_AXI_WVALID,\n input wire M_AXI_WREADY,\n \n // Master Interface Write Response Ports\n input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,\n input wire [2-1:0] M_AXI_BRESP,\n input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,\n input wire M_AXI_BVALID,\n output wire M_AXI_BREADY,\n \n // Master Interface Read Address Port\n output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,\n output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,\n output wire [8-1:0] M_AXI_ARLEN,\n output wire [3-1:0] M_AXI_ARSIZE,\n output wire [2-1:0] M_AXI_ARBURST,\n output wire [2-1:0] M_AXI_ARLOCK,\n output wire [4-1:0] M_AXI_ARCACHE,\n output wire [3-1:0] M_AXI_ARPROT,\n output wire [4-1:0] M_AXI_ARREGION,\n output wire [4-1:0] M_AXI_ARQOS,\n output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,\n output wire M_AXI_ARVALID,\n input wire M_AXI_ARREADY,\n \n // Master Interface Read Data Ports\n input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,\n input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,\n input wire [2-1:0] M_AXI_RRESP,\n input wire M_AXI_RLAST,\n input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,\n input wire M_AXI_RVALID,\n output wire M_AXI_RREADY\n );\n\n (* shift_extract=\"no\", iob=\"false\", equivalent_register_removal = \"no\" *) reg reset;\n always @(posedge ACLK) begin\n reset <= ~ARESETN;\n end\n\n // Write Address Port bit positions\n localparam C_AWUSER_RIGHT = 0;\n localparam C_AWUSER_LEN = C_AXI_SUPPORTS_USER_SIGNALS*C_AXI_AWUSER_WIDTH;\n localparam C_AWQOS_RIGHT = C_AWUSER_RIGHT + C_AWUSER_LEN;\n localparam C_AWQOS_LEN = 4;\n localparam C_AWREGION_RIGHT = C_AWQOS_RIGHT + C_AWQOS_LEN;\n localparam C_AWREGION_LEN = 4;\n localparam C_AWPROT_RIGHT = C_AWREGION_RIGHT + C_AWREGION_LEN;\n localparam C_AWPROT_LEN = 3;\n localparam C_AWCACHE_RIGHT = C_AWPROT_RIGHT + C_AWPROT_LEN;\n localparam C_AWCACHE_LEN = 4;\n localparam C_AWLOCK_RIGHT = C_AWCACHE_RIGHT + C_AWCACHE_LEN;\n localparam C_AWLOCK_LEN = 2;\n localparam C_AWBURST_RIGHT = C_AWLOCK_RIGHT + C_AWLOCK_LEN;\n localparam C_AWBURST_LEN = 2;\n localparam C_AWSIZE_RIGHT = C_AWBURST_RIGHT + C_AWBURST_LEN;\n localparam C_AWSIZE_LEN = 3;\n localparam C_AWLEN_RIGHT = C_AWSIZE_RIGHT + C_AWSIZE_LEN;\n localparam C_AWLEN_LEN = 8;\n localparam C_AWADDR_RIGHT = C_AWLEN_RIGHT + C_AWLEN_LEN;\n localparam C_AWADDR_LEN = C_AXI_ADDR_WIDTH;\n localparam C_AWID_RIGHT = C_AWADDR_RIGHT + C_AWADDR_LEN;\n localparam C_AWID_LEN = C_AXI_ID_WIDTH;\n localparam C_AW_SIZE = C_AWID_RIGHT+C_AWID_LEN;\n\n // Write Address Port FIFO data read and write\n wire [C_AW_SIZE-1:0] s_aw_data ;\n wire [C_AW_SIZE-1:0] m_aw_data ;\n \n // Write Data Port bit positions\n localparam C_WUSER_RIGHT = 0;\n localparam C_WUSER_LEN = C_AXI_SUPPORTS_USER_SIGNALS*C_AXI_WUSER_WIDTH;\n localparam C_WLAST_RIGHT = C_WUSER_RIGHT + C_WUSER_LEN;\n localparam C_WLAST_LEN = 1;\n localparam C_WSTRB_RIGHT = C_WLAST_RIGHT + C_WLAST_LEN;\n localparam C_WSTRB_LEN = C_AXI_DATA_WIDTH/8;\n localparam C_WDATA_RIGHT = C_WSTRB_RIGHT + C_WSTRB_LEN;\n localparam C_WDATA_LEN = C_AXI_DATA_WIDTH;\n localparam C_WID_RIGHT = C_WDATA_RIGHT + C_WDATA_LEN;\n localparam C_WID_LEN = C_AXI_ID_WIDTH;\n localparam C_W_SIZE = C_WID_RIGHT+C_WID_LEN;\n\n // Write Data Port FIFO data read and write\n wire [C_W_SIZE-1:0] s_w_data;\n wire [C_W_SIZE-1:0] m_w_data;\n\n // Write Response Port bit positions\n localparam C_BUSER_RIGHT = 0;\n localparam C_BUSER_LEN = C_AXI_SUPPORTS_USER_SIGNALS*C_AXI_BUSER_WIDTH;\n localparam C_BRESP_RIGHT = C_BUSER_RIGHT + C_BUSER_LEN;\n localparam C_BRESP_LEN = 2;\n localparam C_BID_RIGHT = C_BRESP_RIGHT + C_BRESP_LEN;\n localparam C_BID_LEN = C_AXI_ID_WIDTH;\n localparam C_B_SIZE = C_BID_RIGHT+C_BID_LEN;\n\n // Write Response Port FIFO data read and write\n wire [C_B_SIZE-1:0] s_b_data;\n wire [C_B_SIZE-1:0] m_b_data;\n\n // Read Address Port bit positions\n localparam C_ARUSER_RIGHT = 0;\n localparam C_ARUSER_LEN = C_AXI_SUPPORTS_USER_SIGNALS*C_AXI_ARUSER_WIDTH;\n localparam C_ARQOS_RIGHT = C_ARUSER_RIGHT + C_ARUSER_LEN;\n localparam C_ARQOS_LEN = 4;\n localparam C_ARREGION_RIGHT = C_ARQOS_RIGHT + C_ARQOS_LEN;\n localparam C_ARREGION_LEN = 4;\n localparam C_ARPROT_RIGHT = C_ARREGION_RIGHT + C_ARREGION_LEN;\n localparam C_ARPROT_LEN = 3;\n localparam C_ARCACHE_RIGHT = C_ARPROT_RIGHT + C_ARPROT_LEN;\n localparam C_ARCACHE_LEN = 4;\n localparam C_ARLOCK_RIGHT = C_ARCACHE_RIGHT + C_ARCACHE_LEN;\n localparam C_ARLOCK_LEN = 2;\n localparam C_ARBURST_RIGHT = C_ARLOCK_RIGHT + C_ARLOCK_LEN;\n localparam C_ARBURST_LEN = 2;\n localparam C_ARSIZE_RIGHT = C_ARBURST_RIGHT + C_ARBURST_LEN;\n localparam C_ARSIZE_LEN = 3;\n localparam C_ARLEN_RIGHT = C_ARSIZE_RIGHT + C_ARSIZE_LEN;\n localparam C_ARLEN_LEN = 8;\n localparam C_ARADDR_RIGHT = C_ARLEN_RIGHT + C_ARLEN_LEN;\n localparam C_ARADDR_LEN = C_AXI_ADDR_WIDTH;\n localparam C_ARID_RIGHT = C_ARADDR_RIGHT + C_ARADDR_LEN;\n localparam C_ARID_LEN = C_AXI_ID_WIDTH;\n localparam C_AR_SIZE = C_ARID_RIGHT+C_ARID_LEN;\n\n // Read Address Port FIFO data read and write\n wire [C_AR_SIZE-1:0] s_ar_data;\n wire [C_AR_SIZE-1:0] m_ar_data;\n\n // Read Data Ports bit positions\n localparam C_RUSER_RIGHT = 0;\n localparam C_RUSER_LEN = C_AXI_SUPPORTS_USER_SIGNALS*C_AXI_RUSER_WIDTH;\n localparam C_RLAST_RIGHT = C_RUSER_RIGHT + C_RUSER_LEN;\n localparam C_RLAST_LEN = 1;\n localparam C_RRESP_RIGHT = C_RLAST_RIGHT + C_RLAST_LEN;\n localparam C_RRESP_LEN = 2;\n localparam C_RDATA_RIGHT = C_RRESP_RIGHT + C_RRESP_LEN;\n localparam C_RDATA_LEN = C_AXI_DATA_WIDTH;\n localparam C_RID_RIGHT = C_RDATA_RIGHT + C_RDATA_LEN;\n localparam C_RID_LEN = C_AXI_ID_WIDTH;\n localparam C_R_SIZE = C_RID_RIGHT+C_RID_LEN;\n\n // Read Data Ports FIFO data read and write\n wire [C_R_SIZE-1:0] s_r_data;\n wire [C_R_SIZE-1:0] m_r_data;\n\n generate\n \n ///////////////////////////////////////////////////////\n //\n // AW PIPE\n //\n ///////////////////////////////////////////////////////\n \n if (C_AXI_SUPPORTS_USER_SIGNALS == 1) begin : gen_async_aw_user\n assign s_aw_data = {S_AXI_AWID, S_AXI_AWADDR, S_AXI_AWLEN, S_AXI_AWSIZE, \n S_AXI_AWBURST, S_AXI_AWLOCK, S_AXI_AWCACHE, S_AXI_AWPROT, \n S_AXI_AWREGION, S_AXI_AWQOS, S_AXI_AWUSER};\n assign M_AXI_AWUSER = m_aw_data[C_AWUSER_RIGHT+:C_AWUSER_LEN];\n end\n else begin : gen_asynch_aw_no_user\n assign s_aw_data = {S_AXI_AWID, S_AXI_AWADDR, S_AXI_AWLEN, S_AXI_AWSIZE, \n S_AXI_AWBURST, S_AXI_AWLOCK, S_AXI_AWCACHE, S_AXI_AWPROT, \n S_AXI_AWREGION, S_AXI_AWQOS};\n assign M_AXI_AWUSER = {C_AXI_AWUSER_WIDTH{1'b0}};\n end\n\n assign M_AXI_AWID = m_aw_data[C_AWID_RIGHT+:C_AWID_LEN];\n assign M_AXI_AWADDR = m_aw_data[C_AWADDR_RIGHT+:C_AWADDR_LEN];\n assign M_AXI_AWLEN = m_aw_data[C_AWLEN_RIGHT+:C_AWLEN_LEN];\n assign M_AXI_AWSIZE = m_aw_data[C_AWSIZE_RIGHT+:C_AWSIZE_LEN];\n assign M_AXI_AWBURST = m_aw_data[C_AWBURST_RIGHT+:C_AWBURST_LEN];\n assign M_AXI_AWLOCK = m_aw_data[C_AWLOCK_RIGHT+:C_AWLOCK_LEN];\n assign M_AXI_AWCACHE = m_aw_data[C_AWCACHE_RIGHT+:C_AWCACHE_LEN];\n assign M_AXI_AWPROT = m_aw_data[C_AWPROT_RIGHT+:C_AWPROT_LEN];\n assign M_AXI_AWREGION = m_aw_data[C_AWREGION_RIGHT+:C_AWREGION_LEN];\n assign M_AXI_AWQOS = m_aw_data[C_AWQOS_RIGHT+:C_AWQOS_LEN];\n \n mig_7series_v4_0_ddr_axic_register_slice #\n (\n .C_FAMILY(C_FAMILY),\n .C_DATA_WIDTH(C_AW_SIZE),\n .C_REG_CONFIG(C_REG_CONFIG_AW)\n )\n aw_pipe\n (\n // System Signals\n .ACLK(ACLK),\n .ARESET(reset),\n\n // Slave side\n .S_PAYLOAD_DATA(s_aw_data),\n .S_VALID(S_AXI_AWVALID),\n .S_READY(S_AXI_AWREADY),\n\n // Master side\n .M_PAYLOAD_DATA(m_aw_data),\n .M_VALID(M_AXI_AWVALID),\n .M_READY(M_AXI_AWREADY)\n );\n \n\n ///////////////////////////////////////////////////////\n //\n // Data Write PIPE\n //\n /////////////////////////////////////////////////////// \n if (C_AXI_SUPPORTS_USER_SIGNALS == 1) begin : gen_async_w_user\n assign s_w_data = {S_AXI_WID, S_AXI_WDATA, S_AXI_WSTRB, S_AXI_WLAST, S_AXI_WUSER};\n assign M_AXI_WUSER = m_w_data[C_WUSER_RIGHT+:C_WUSER_LEN];\n end\n else begin : gen_asynch_w_no_user\n assign s_w_data = {S_AXI_WID, S_AXI_WDATA, S_AXI_WSTRB, S_AXI_WLAST};\n assign M_AXI_WUSER = {C_AXI_WUSER_WIDTH{1'b0}};\n end\n\n assign M_AXI_WID = m_w_data[C_WID_RIGHT+:C_WID_LEN];\n assign M_AXI_WDATA = m_w_data[C_WDATA_RIGHT+:C_WDATA_LEN];\n assign M_AXI_WSTRB = m_w_data[C_WSTRB_RIGHT+:C_WSTRB_LEN];\n assign M_AXI_WLAST = m_w_data[C_WLAST_RIGHT+:C_WLAST_LEN];\n\n mig_7series_v4_0_ddr_axic_register_slice #\n (\n .C_FAMILY(C_FAMILY),\n .C_DATA_WIDTH(C_W_SIZE),\n .C_REG_CONFIG(C_REG_CONFIG_W)\n )\n w_pipe\n (\n // System Signals\n .ACLK(ACLK),\n .ARESET(reset),\n\n // Slave side\n .S_PAYLOAD_DATA(s_w_data),\n .S_VALID(S_AXI_WVALID),\n .S_READY(S_AXI_WREADY),\n\n // Master side\n .M_PAYLOAD_DATA(m_w_data),\n .M_VALID(M_AXI_WVALID),\n .M_READY(M_AXI_WREADY)\n );\n\n \n ///////////////////////////////////////////////////////\n //\n // Write Response PIPE\n //\n /////////////////////////////////////////////////////// \n if (C_AXI_SUPPORTS_USER_SIGNALS == 1) begin : gen_async_b_user\n assign m_b_data = {M_AXI_BID, M_AXI_BRESP, M_AXI_BUSER};\n assign S_AXI_BUSER = s_b_data[C_BUSER_RIGHT+:C_BUSER_LEN];\n end\n else begin : gen_asynch_b_no_user\n assign m_b_data = {M_AXI_BID, M_AXI_BRESP};\n assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}};\n end\n\n assign S_AXI_BID = s_b_data[C_BID_RIGHT+:C_BID_LEN];\n assign S_AXI_BRESP = s_b_data[C_BRESP_RIGHT+:C_BRESP_LEN];\n\n mig_7series_v4_0_ddr_axic_register_slice #\n (\n .C_FAMILY(C_FAMILY),\n .C_DATA_WIDTH(C_B_SIZE),\n .C_REG_CONFIG(C_REG_CONFIG_B)\n )\n b_pipe\n (\n // System Signals\n .ACLK(ACLK),\n .ARESET(reset),\n\n // Slave side\n .S_PAYLOAD_DATA(m_b_data),\n .S_VALID(M_AXI_BVALID),\n .S_READY(M_AXI_BREADY),\n\n // Master side\n .M_PAYLOAD_DATA(s_b_data),\n .M_VALID(S_AXI_BVALID),\n .M_READY(S_AXI_BREADY)\n );\n \n ///////////////////////////////////////////////////////\n //\n // Address Read PIPE\n //\n /////////////////////////////////////////////////////// \n\n if (C_AXI_SUPPORTS_USER_SIGNALS == 1) begin : gen_async_ar_user\n assign s_ar_data = {S_AXI_ARID, S_AXI_ARADDR, S_AXI_ARLEN, S_AXI_ARSIZE, \n S_AXI_ARBURST, S_AXI_ARLOCK, S_AXI_ARCACHE, S_AXI_ARPROT, \n S_AXI_ARREGION, S_AXI_ARQOS, S_AXI_ARUSER};\n assign M_AXI_ARUSER = m_ar_data[C_ARUSER_RIGHT+:C_ARUSER_LEN];\n end\n else begin : gen_asynch_ar_no_user\n assign s_ar_data = {S_AXI_ARID, S_AXI_ARADDR, S_AXI_ARLEN, S_AXI_ARSIZE, \n S_AXI_ARBURST, S_AXI_ARLOCK, S_AXI_ARCACHE, S_AXI_ARPROT, \n S_AXI_ARREGION, S_AXI_ARQOS};\n \n assign M_AXI_ARUSER = {C_AXI_ARUSER_WIDTH{1'b0}};\n end\n\n assign M_AXI_ARID = m_ar_data[C_ARID_RIGHT+:C_ARID_LEN];\n assign M_AXI_ARADDR = m_ar_data[C_ARADDR_RIGHT+:C_ARADDR_LEN];\n assign M_AXI_ARLEN = m_ar_data[C_ARLEN_RIGHT+:C_ARLEN_LEN];\n assign M_AXI_ARSIZE = m_ar_data[C_ARSIZE_RIGHT+:C_ARSIZE_LEN];\n assign M_AXI_ARBURST = m_ar_data[C_ARBURST_RIGHT+:C_ARBURST_LEN];\n assign M_AXI_ARLOCK = m_ar_data[C_ARLOCK_RIGHT+:C_ARLOCK_LEN];\n assign M_AXI_ARCACHE = m_ar_data[C_ARCACHE_RIGHT+:C_ARCACHE_LEN];\n assign M_AXI_ARPROT = m_ar_data[C_ARPROT_RIGHT+:C_ARPROT_LEN];\n assign M_AXI_ARREGION = m_ar_data[C_ARREGION_RIGHT+:C_ARREGION_LEN];\n assign M_AXI_ARQOS = m_ar_data[C_ARQOS_RIGHT+:C_ARQOS_LEN];\n\n mig_7series_v4_0_ddr_axic_register_slice #\n (\n .C_FAMILY(C_FAMILY),\n .C_DATA_WIDTH(C_AR_SIZE),\n .C_REG_CONFIG(C_REG_CONFIG_AR)\n )\n ar_pipe\n (\n // System Signals\n .ACLK(ACLK),\n .ARESET(reset),\n\n // Slave side\n .S_PAYLOAD_DATA(s_ar_data),\n .S_VALID(S_AXI_ARVALID),\n .S_READY(S_AXI_ARREADY),\n\n // Master side\n .M_PAYLOAD_DATA(m_ar_data),\n .M_VALID(M_AXI_ARVALID),\n .M_READY(M_AXI_ARREADY)\n );\n \n ///////////////////////////////////////////////////////\n //\n // Data Read PIPE\n //\n ///////////////////////////////////////////////////////\n \n if (C_AXI_SUPPORTS_USER_SIGNALS == 1) begin : gen_async_r_user\n assign m_r_data = {M_AXI_RID, M_AXI_RDATA, M_AXI_RRESP, M_AXI_RLAST, M_AXI_RUSER};\n assign S_AXI_RUSER = s_r_data[C_RUSER_RIGHT+:C_RUSER_LEN];\n end\n else begin : gen_asynch_r_no_user\n assign m_r_data = {M_AXI_RID, M_AXI_RDATA, M_AXI_RRESP, M_AXI_RLAST};\n assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}};\n end\n \n assign S_AXI_RID = s_r_data[C_RID_RIGHT+:C_RID_LEN];\n assign S_AXI_RDATA = s_r_data[C_RDATA_RIGHT+:C_RDATA_LEN];\n assign S_AXI_RRESP = s_r_data[C_RRESP_RIGHT+:C_RRESP_LEN];\n assign S_AXI_RLAST = s_r_data[C_RLAST_RIGHT+:C_RLAST_LEN];\n\n mig_7series_v4_0_ddr_axic_register_slice #\n (\n .C_FAMILY(C_FAMILY),\n .C_DATA_WIDTH(C_R_SIZE),\n .C_REG_CONFIG(C_REG_CONFIG_R)\n )\n r_pipe\n (\n // System Signals\n .ACLK(ACLK),\n .ARESET(reset),\n\n // Slave side\n .S_PAYLOAD_DATA(m_r_data),\n .S_VALID(M_AXI_RVALID),\n .S_READY(M_AXI_RREADY),\n\n // Master side\n .M_PAYLOAD_DATA(s_r_data),\n .M_VALID(S_AXI_RVALID),\n .M_READY(S_AXI_RREADY)\n );\n\n endgenerate\n\nendmodule // ddr_axi_register_slice\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_axi_upsizer.v", "content": "//-----------------------------------------------------------------------------\n//-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.\n//--\n//-- This file contains confidential and proprietary information\n//-- of Xilinx, Inc. and is protected under U.S. and\n//-- international copyright and other intellectual property\n//-- laws.\n//--\n//-- DISCLAIMER\n//-- This disclaimer is not a license and does not grant any\n//-- rights to the materials distributed herewith. Except as\n//-- otherwise provided in a valid license issued to you by\n//-- Xilinx, and to the maximum extent permitted by applicable\n//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n//-- (2) Xilinx shall not be liable (whether in contract or tort,\n//-- including negligence, or under any other theory of\n//-- liability) for any loss or damage of any kind or nature\n//-- related to, arising under or in connection with these\n//-- materials, including for any direct, or any indirect,\n//-- special, incidental, or consequential loss or damage\n//-- (including loss of data, profits, goodwill, or any type of\n//-- loss or damage suffered as a result of any action brought\n//-- by a third party) even if such damage or loss was\n//-- reasonably foreseeable or Xilinx had been advised of the\n//-- possibility of the same.\n//--\n//-- CRITICAL APPLICATIONS\n//-- Xilinx products are not designed or intended to be fail-\n//-- safe, or for use in any application requiring fail-safe\n//-- performance, such as life-support or safety devices or\n//-- systems, Class III medical devices, nuclear facilities,\n//-- applications related to the deployment of airbags, or any\n//-- other applications that could lead to death, personal\n//-- injury, or severe property or environmental damage\n//-- (individually and collectively, \"Critical\n//-- Applications\"). Customer assumes the sole risk and\n//-- liability of any use of Xilinx products in Critical\n//-- Applications, subject only to applicable laws and\n//-- regulations governing limitations on product liability.\n//--\n//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n//-- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: Up-Sizer\n// Up-Sizer for generic SI- and MI-side data widths. This module instantiates\n// Address, Write Data and Read Data Up-Sizer modules, each one taking care\n// of the channel specific tasks.\n// The Address Up-Sizer can handle both AR and AW channels.\n//\n// Verilog-standard: Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n// ddr_axi_upsizer\n// ddr_a_upsizer\n// fifo\n// fifo_gen\n// fifo_coregen\n// ddr_w_upsizer\n// ddr_r_upsizer\n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n`default_nettype none\n\nmodule mig_7series_v4_0_ddr_axi_upsizer #\n (\n parameter C_FAMILY = \"rtl\", \n // FPGA Family. Current version: virtex6 or spartan6.\n parameter integer C_AXI_ID_WIDTH = 4, \n // Width of all ID signals on SI and MI side of converter.\n // Range: >= 1.\n parameter integer C_AXI_ADDR_WIDTH = 32, \n // Width of all ADDR signals on SI and MI side of converter.\n // Range: 32.\n parameter C_S_AXI_DATA_WIDTH = 32'h00000020, \n // Width of S_AXI_WDATA and S_AXI_RDATA.\n // Format: Bit32; \n // Range: 'h00000020, 'h00000040, 'h00000080, 'h00000100.\n parameter C_M_AXI_DATA_WIDTH = 32'h00000040, \n // Width of M_AXI_WDATA and M_AXI_RDATA.\n // Assume greater than or equal to C_S_AXI_DATA_WIDTH.\n // Format: Bit32;\n // Range: 'h00000020, 'h00000040, 'h00000080, 'h00000100.\n parameter integer C_M_AXI_AW_REGISTER = 0,\n // Simple register AW output.\n // Range: 0, 1\n parameter integer C_M_AXI_W_REGISTER = 1, // Parameter not used; W reg always implemented.\n parameter integer C_M_AXI_AR_REGISTER = 0,\n // Simple register AR output.\n // Range: 0, 1\n parameter integer C_S_AXI_R_REGISTER = 0,\n // Simple register R output (SI).\n // Range: 0, 1\n parameter integer C_M_AXI_R_REGISTER = 1,\n // Register slice on R input (MI) side.\n // 0 = Bypass (not recommended due to combinatorial M_RVALID -> M_RREADY path)\n // 1 = Fully-registered (needed only when upsizer propagates bursts at 1:1 width ratio)\n // 7 = Light-weight (safe when upsizer always packs at 1:n width ratio, as in interconnect)\n parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,\n // 1 = Propagate all USER signals, 0 = Dont propagate.\n parameter integer C_AXI_AWUSER_WIDTH = 1,\n // Width of AWUSER signals. \n // Range: >= 1.\n parameter integer C_AXI_ARUSER_WIDTH = 1,\n // Width of ARUSER signals. \n // Range: >= 1.\n parameter integer C_AXI_WUSER_WIDTH = 1,\n // Width of WUSER signals. \n // Range: >= 1.\n parameter integer C_AXI_RUSER_WIDTH = 1,\n // Width of RUSER signals. \n // Range: >= 1.\n parameter integer C_AXI_BUSER_WIDTH = 1,\n // Width of BUSER signals. \n // Range: >= 1.\n parameter integer C_AXI_SUPPORTS_WRITE = 1,\n parameter integer C_AXI_SUPPORTS_READ = 1,\n parameter integer C_PACKING_LEVEL = 1,\n // 0 = Never pack (expander only); packing logic is omitted.\n // 1 = Pack only when CACHE[1] (Modifiable) is high.\n // 2 = Always pack, regardless of sub-size transaction or Modifiable bit.\n // (Required when used as helper-core by mem-con. Same size AXI interfaces\n // should only be used when always packing)\n parameter integer C_SUPPORT_BURSTS = 1,\n // Disabled when all connected masters and slaves are AxiLite,\n // allowing logic to be simplified.\n parameter integer C_SINGLE_THREAD = 1\n // 0 = Ignore ID when propagating transactions (assume all responses are in order).\n // 1 = Allow multiple outstanding transactions only if the IDs are the same\n // to prevent response reordering.\n // (If ID mismatches, stall until outstanding transaction counter = 0.)\n )\n (\n // Global Signals\n input wire ARESETN,\n input wire ACLK,\n\n // Slave Interface Write Address Ports\n input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,\n input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,\n input wire [8-1:0] S_AXI_AWLEN,\n input wire [3-1:0] S_AXI_AWSIZE,\n input wire [2-1:0] S_AXI_AWBURST,\n input wire [2-1:0] S_AXI_AWLOCK,\n input wire [4-1:0] S_AXI_AWCACHE,\n input wire [3-1:0] S_AXI_AWPROT,\n input wire [4-1:0] S_AXI_AWREGION,\n input wire [4-1:0] S_AXI_AWQOS,\n input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,\n input wire S_AXI_AWVALID,\n output wire S_AXI_AWREADY,\n // Slave Interface Write Data Ports\n input wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,\n input wire [C_S_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,\n input wire S_AXI_WLAST,\n input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,\n input wire S_AXI_WVALID,\n output wire S_AXI_WREADY,\n // Slave Interface Write Response Ports\n output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,\n output wire [2-1:0] S_AXI_BRESP,\n output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,\n output wire S_AXI_BVALID,\n input wire S_AXI_BREADY,\n // Slave Interface Read Address Ports\n input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,\n input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,\n input wire [8-1:0] S_AXI_ARLEN,\n input wire [3-1:0] S_AXI_ARSIZE,\n input wire [2-1:0] S_AXI_ARBURST,\n input wire [2-1:0] S_AXI_ARLOCK,\n input wire [4-1:0] S_AXI_ARCACHE,\n input wire [3-1:0] S_AXI_ARPROT,\n input wire [4-1:0] S_AXI_ARREGION,\n input wire [4-1:0] S_AXI_ARQOS,\n input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,\n input wire S_AXI_ARVALID,\n output wire S_AXI_ARREADY,\n // Slave Interface Read Data Ports\n output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,\n output wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,\n output wire [2-1:0] S_AXI_RRESP,\n output wire S_AXI_RLAST,\n output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,\n output wire S_AXI_RVALID,\n input wire S_AXI_RREADY,\n\n // Master Interface Write Address Port\n output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,\n output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,\n output wire [8-1:0] M_AXI_AWLEN,\n output wire [3-1:0] M_AXI_AWSIZE,\n output wire [2-1:0] M_AXI_AWBURST,\n output wire [2-1:0] M_AXI_AWLOCK,\n output wire [4-1:0] M_AXI_AWCACHE,\n output wire [3-1:0] M_AXI_AWPROT,\n output wire [4-1:0] M_AXI_AWREGION,\n output wire [4-1:0] M_AXI_AWQOS,\n output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,\n output wire M_AXI_AWVALID,\n input wire M_AXI_AWREADY,\n // Master Interface Write Data Ports\n output wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,\n output wire [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,\n output wire M_AXI_WLAST,\n output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,\n output wire M_AXI_WVALID,\n input wire M_AXI_WREADY,\n // Master Interface Write Response Ports\n input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,\n input wire [2-1:0] M_AXI_BRESP,\n input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,\n input wire M_AXI_BVALID,\n output wire M_AXI_BREADY,\n // Master Interface Read Address Port\n output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,\n output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,\n output wire [8-1:0] M_AXI_ARLEN,\n output wire [3-1:0] M_AXI_ARSIZE,\n output wire [2-1:0] M_AXI_ARBURST,\n output wire [2-1:0] M_AXI_ARLOCK,\n output wire [4-1:0] M_AXI_ARCACHE,\n output wire [3-1:0] M_AXI_ARPROT,\n output wire [4-1:0] M_AXI_ARREGION,\n output wire [4-1:0] M_AXI_ARQOS,\n output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,\n output wire M_AXI_ARVALID,\n input wire M_AXI_ARREADY,\n // Master Interface Read Data Ports\n input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,\n input wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,\n input wire [2-1:0] M_AXI_RRESP,\n input wire M_AXI_RLAST,\n input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,\n input wire M_AXI_RVALID,\n output wire M_AXI_RREADY\n );\n\n \n /////////////////////////////////////////////////////////////////////////////\n // Functions\n /////////////////////////////////////////////////////////////////////////////\n \n // Log2.\n function integer log2;\n input integer value;\n begin\n for (log2=0; value>1; log2=log2+1) begin\n value = value >> 1;\n end\n end\n endfunction\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Local params\n /////////////////////////////////////////////////////////////////////////////\n \n // Log2 of number of 32bit word on SI-side.\n localparam integer C_S_AXI_BYTES_LOG = log2(C_S_AXI_DATA_WIDTH/8);\n \n // Log2 of number of 32bit word on MI-side.\n localparam integer C_M_AXI_BYTES_LOG = log2(C_M_AXI_DATA_WIDTH/8);\n \n // Log2 of Up-Sizing ratio for data.\n localparam integer C_RATIO = C_M_AXI_DATA_WIDTH / C_S_AXI_DATA_WIDTH;\n localparam integer C_RATIO_LOG = log2(C_RATIO);\n localparam P_BYPASS = 32'h0;\n localparam P_LIGHTWT = 32'h7;\n localparam P_FWD_REV = 32'h1;\n \n /////////////////////////////////////////////////////////////////////////////\n // Internal signals\n /////////////////////////////////////////////////////////////////////////////\n \n wire [C_AXI_ID_WIDTH-1:0] sr_AWID ; \n wire [C_AXI_ADDR_WIDTH-1:0] sr_AWADDR ; \n wire [8-1:0] sr_AWLEN ; \n wire [3-1:0] sr_AWSIZE ; \n wire [2-1:0] sr_AWBURST ; \n wire [2-1:0] sr_AWLOCK ; \n wire [4-1:0] sr_AWCACHE ; \n wire [3-1:0] sr_AWPROT ; \n wire [4-1:0] sr_AWREGION ; \n wire [4-1:0] sr_AWQOS ; \n wire [C_AXI_AWUSER_WIDTH-1:0] sr_AWUSER ; \n wire sr_AWVALID ; \n wire sr_AWREADY ; \n wire [C_AXI_ID_WIDTH-1:0] sr_ARID ; \n wire [C_AXI_ADDR_WIDTH-1:0] sr_ARADDR ; \n wire [8-1:0] sr_ARLEN ; \n wire [3-1:0] sr_ARSIZE ; \n wire [2-1:0] sr_ARBURST ; \n wire [2-1:0] sr_ARLOCK ; \n wire [4-1:0] sr_ARCACHE ; \n wire [3-1:0] sr_ARPROT ; \n wire [4-1:0] sr_ARREGION ; \n wire [4-1:0] sr_ARQOS ; \n wire [C_AXI_ARUSER_WIDTH-1:0] sr_ARUSER ; \n wire sr_ARVALID ; \n wire sr_ARREADY ; \n \n wire [C_S_AXI_DATA_WIDTH-1:0] sr_WDATA ;\n wire [(C_S_AXI_DATA_WIDTH/8)-1:0] sr_WSTRB ;\n wire sr_WLAST ;\n wire sr_WVALID ;\n wire sr_WREADY ;\n \n wire [C_AXI_ID_WIDTH-1:0] mr_RID ; \n wire [C_M_AXI_DATA_WIDTH-1:0] mr_RDATA ; \n wire [2-1:0] mr_RRESP ; \n wire mr_RLAST ; \n wire [C_AXI_RUSER_WIDTH-1:0] mr_RUSER ; \n wire mr_RVALID ; \n wire mr_RREADY ; \n (* max_fanout = 100 *) reg ARESET ;\n \n assign M_AXI_WUSER = {C_AXI_WUSER_WIDTH{1'b0}};\n assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}};\n\n mig_7series_v4_0_ddr_axi_register_slice #\n (\n .C_FAMILY (C_FAMILY),\n .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),\n .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),\n .C_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),\n .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),\n .C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),\n .C_AXI_ARUSER_WIDTH (C_AXI_ARUSER_WIDTH),\n .C_REG_CONFIG_AW (C_AXI_SUPPORTS_WRITE ? P_LIGHTWT : P_BYPASS),\n .C_REG_CONFIG_AR (C_AXI_SUPPORTS_READ ? P_LIGHTWT : P_BYPASS)\n )\n si_register_slice_inst \n (\n .ARESETN (ARESETN),\n .ACLK (ACLK),\n .S_AXI_AWID (S_AXI_AWID ),\n .S_AXI_AWADDR (S_AXI_AWADDR ),\n .S_AXI_AWLEN (S_AXI_AWLEN ),\n .S_AXI_AWSIZE (S_AXI_AWSIZE ),\n .S_AXI_AWBURST (S_AXI_AWBURST ),\n .S_AXI_AWLOCK (S_AXI_AWLOCK ),\n .S_AXI_AWCACHE (S_AXI_AWCACHE ),\n .S_AXI_AWPROT (S_AXI_AWPROT ),\n .S_AXI_AWREGION (S_AXI_AWREGION ),\n .S_AXI_AWQOS (S_AXI_AWQOS ),\n .S_AXI_AWUSER (S_AXI_AWUSER ),\n .S_AXI_AWVALID (S_AXI_AWVALID ),\n .S_AXI_AWREADY (S_AXI_AWREADY ),\n .S_AXI_WID ( {C_AXI_ID_WIDTH{1'b0}}),\n .S_AXI_WDATA ( {C_S_AXI_DATA_WIDTH{1'b0}} ),\n .S_AXI_WSTRB ( {C_S_AXI_DATA_WIDTH/8{1'b0}} ),\n .S_AXI_WLAST ( 1'b0 ),\n .S_AXI_WUSER ( 1'b0 ),\n .S_AXI_WVALID ( 1'b0 ),\n .S_AXI_WREADY ( ),\n .S_AXI_BID ( ),\n .S_AXI_BRESP ( ),\n .S_AXI_BUSER ( ),\n .S_AXI_BVALID ( ),\n .S_AXI_BREADY ( 1'b0 ),\n .S_AXI_ARID (S_AXI_ARID ),\n .S_AXI_ARADDR (S_AXI_ARADDR ),\n .S_AXI_ARLEN (S_AXI_ARLEN ),\n .S_AXI_ARSIZE (S_AXI_ARSIZE ),\n .S_AXI_ARBURST (S_AXI_ARBURST ),\n .S_AXI_ARLOCK (S_AXI_ARLOCK ),\n .S_AXI_ARCACHE (S_AXI_ARCACHE ),\n .S_AXI_ARPROT (S_AXI_ARPROT ),\n .S_AXI_ARREGION (S_AXI_ARREGION ),\n .S_AXI_ARQOS (S_AXI_ARQOS ),\n .S_AXI_ARUSER (S_AXI_ARUSER ),\n .S_AXI_ARVALID (S_AXI_ARVALID ),\n .S_AXI_ARREADY (S_AXI_ARREADY ),\n .S_AXI_RID ( ) ,\n .S_AXI_RDATA ( ) ,\n .S_AXI_RRESP ( ) ,\n .S_AXI_RLAST ( ) ,\n .S_AXI_RUSER ( ) ,\n .S_AXI_RVALID ( ) ,\n .S_AXI_RREADY ( 1'b0 ) ,\n .M_AXI_AWID (sr_AWID ),\n .M_AXI_AWADDR (sr_AWADDR ),\n .M_AXI_AWLEN (sr_AWLEN ),\n .M_AXI_AWSIZE (sr_AWSIZE ),\n .M_AXI_AWBURST (sr_AWBURST ),\n .M_AXI_AWLOCK (sr_AWLOCK ),\n .M_AXI_AWCACHE (sr_AWCACHE ),\n .M_AXI_AWPROT (sr_AWPROT ),\n .M_AXI_AWREGION (sr_AWREGION ),\n .M_AXI_AWQOS (sr_AWQOS ),\n .M_AXI_AWUSER (sr_AWUSER ),\n .M_AXI_AWVALID (sr_AWVALID ),\n .M_AXI_AWREADY (sr_AWREADY ),\n .M_AXI_WID () ,\n .M_AXI_WDATA (),\n .M_AXI_WSTRB (),\n .M_AXI_WLAST (),\n .M_AXI_WUSER (),\n .M_AXI_WVALID (),\n .M_AXI_WREADY (1'b0),\n .M_AXI_BID ( {C_AXI_ID_WIDTH{1'b0}} ) ,\n .M_AXI_BRESP ( 2'b0 ) ,\n .M_AXI_BUSER ( 1'b0 ) ,\n .M_AXI_BVALID ( 1'b0 ) ,\n .M_AXI_BREADY ( ) ,\n .M_AXI_ARID (sr_ARID ),\n .M_AXI_ARADDR (sr_ARADDR ),\n .M_AXI_ARLEN (sr_ARLEN ),\n .M_AXI_ARSIZE (sr_ARSIZE ),\n .M_AXI_ARBURST (sr_ARBURST ),\n .M_AXI_ARLOCK (sr_ARLOCK ),\n .M_AXI_ARCACHE (sr_ARCACHE ),\n .M_AXI_ARPROT (sr_ARPROT ),\n .M_AXI_ARREGION (sr_ARREGION ),\n .M_AXI_ARQOS (sr_ARQOS ),\n .M_AXI_ARUSER (sr_ARUSER ),\n .M_AXI_ARVALID (sr_ARVALID ),\n .M_AXI_ARREADY (sr_ARREADY ),\n .M_AXI_RID ( {C_AXI_ID_WIDTH{1'b0}}),\n .M_AXI_RDATA ( {C_S_AXI_DATA_WIDTH{1'b0}} ),\n .M_AXI_RRESP ( 2'b00 ),\n .M_AXI_RLAST ( 1'b0 ),\n .M_AXI_RUSER ( 1'b0 ),\n .M_AXI_RVALID ( 1'b0 ),\n .M_AXI_RREADY ( )\n );\n \n mig_7series_v4_0_ddr_axi_register_slice #\n (\n .C_FAMILY (C_FAMILY),\n .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),\n .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),\n .C_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),\n .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),\n .C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),\n .C_REG_CONFIG_R (C_AXI_SUPPORTS_READ ? C_M_AXI_R_REGISTER : P_BYPASS)\n )\n mi_register_slice_inst \n (\n .ARESETN (ARESETN),\n .ACLK (ACLK),\n .S_AXI_AWID ({C_AXI_ID_WIDTH{1'b0}} ),\n .S_AXI_AWADDR ( {C_AXI_ADDR_WIDTH{1'b0}} ),\n .S_AXI_AWLEN ( 8'b0 ),\n .S_AXI_AWSIZE ( 3'b0 ),\n .S_AXI_AWBURST ( 2'b0 ),\n .S_AXI_AWLOCK ( 2'b0 ),\n .S_AXI_AWCACHE ( 4'b0 ),\n .S_AXI_AWPROT ( 3'b0 ),\n .S_AXI_AWREGION ( 4'b0 ),\n .S_AXI_AWQOS ( 4'b0 ),\n .S_AXI_AWUSER ( 1'b0 ),\n .S_AXI_AWVALID ( 1'b0 ),\n .S_AXI_AWREADY ( ),\n .S_AXI_WID ( {C_AXI_ID_WIDTH{1'b0}}),\n .S_AXI_WDATA ( {C_M_AXI_DATA_WIDTH{1'b0}} ),\n .S_AXI_WSTRB ( {C_M_AXI_DATA_WIDTH/8{1'b0}} ),\n .S_AXI_WLAST ( 1'b0 ),\n .S_AXI_WUSER ( 1'b0 ),\n .S_AXI_WVALID ( 1'b0 ),\n .S_AXI_WREADY ( ),\n .S_AXI_BID ( ),\n .S_AXI_BRESP ( ),\n .S_AXI_BUSER ( ),\n .S_AXI_BVALID ( ),\n .S_AXI_BREADY ( 1'b0 ),\n .S_AXI_ARID ({C_AXI_ID_WIDTH{1'b0}} ),\n .S_AXI_ARADDR ( {C_AXI_ADDR_WIDTH{1'b0}} ),\n .S_AXI_ARLEN ( 8'b0 ),\n .S_AXI_ARSIZE ( 3'b0 ),\n .S_AXI_ARBURST ( 2'b0 ),\n .S_AXI_ARLOCK ( 2'b0 ),\n .S_AXI_ARCACHE ( 4'b0 ),\n .S_AXI_ARPROT ( 3'b0 ),\n .S_AXI_ARREGION ( 4'b0 ),\n .S_AXI_ARQOS ( 4'b0 ),\n .S_AXI_ARUSER ( 1'b0 ),\n .S_AXI_ARVALID ( 1'b0 ),\n .S_AXI_ARREADY ( ),\n .S_AXI_RID (mr_RID ),\n .S_AXI_RDATA (mr_RDATA ),\n .S_AXI_RRESP (mr_RRESP ),\n .S_AXI_RLAST (mr_RLAST ),\n .S_AXI_RUSER (mr_RUSER ),\n .S_AXI_RVALID (mr_RVALID ),\n .S_AXI_RREADY (mr_RREADY ),\n .M_AXI_AWID (),\n .M_AXI_AWADDR (),\n .M_AXI_AWLEN (),\n .M_AXI_AWSIZE (),\n .M_AXI_AWBURST (),\n .M_AXI_AWLOCK (),\n .M_AXI_AWCACHE (),\n .M_AXI_AWPROT (),\n .M_AXI_AWREGION (),\n .M_AXI_AWQOS (),\n .M_AXI_AWUSER (),\n .M_AXI_AWVALID (),\n .M_AXI_AWREADY (1'b0),\n .M_AXI_WID () ,\n .M_AXI_WDATA (),\n .M_AXI_WSTRB (),\n .M_AXI_WLAST (),\n .M_AXI_WUSER (),\n .M_AXI_WVALID (),\n .M_AXI_WREADY (1'b0),\n .M_AXI_BID ( {C_AXI_ID_WIDTH{1'b0}} ) ,\n .M_AXI_BRESP ( 2'b0 ) ,\n .M_AXI_BUSER ( 1'b0 ) ,\n .M_AXI_BVALID ( 1'b0 ) ,\n .M_AXI_BREADY ( ) ,\n .M_AXI_ARID (),\n .M_AXI_ARADDR (),\n .M_AXI_ARLEN (),\n .M_AXI_ARSIZE (),\n .M_AXI_ARBURST (),\n .M_AXI_ARLOCK (),\n .M_AXI_ARCACHE (),\n .M_AXI_ARPROT (),\n .M_AXI_ARREGION (),\n .M_AXI_ARQOS (),\n .M_AXI_ARUSER (),\n .M_AXI_ARVALID (),\n .M_AXI_ARREADY (1'b0),\n .M_AXI_RID (M_AXI_RID ),\n .M_AXI_RDATA (M_AXI_RDATA ),\n .M_AXI_RRESP (M_AXI_RRESP ),\n .M_AXI_RLAST (M_AXI_RLAST ),\n .M_AXI_RUSER (M_AXI_RUSER ),\n .M_AXI_RVALID (M_AXI_RVALID ),\n .M_AXI_RREADY (M_AXI_RREADY )\n );\n \n /////////////////////////////////////////////////////////////////////////////\n // Handle Internal Reset\n /////////////////////////////////////////////////////////////////////////////\n always @ (posedge ACLK) begin\n ARESET <= !ARESETN;\n end\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Handle Write Channels (AW/W/B)\n /////////////////////////////////////////////////////////////////////////////\n generate\n if (C_AXI_SUPPORTS_WRITE == 1) begin : USE_WRITE\n \n // Write Channel Signals for Commands Queue Interface.\n wire wr_cmd_valid;\n wire wr_cmd_fix;\n wire wr_cmd_modified;\n wire wr_cmd_complete_wrap;\n wire wr_cmd_packed_wrap;\n wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_first_word;\n wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_next_word;\n wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_last_word;\n wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_offset;\n wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_mask;\n wire [C_S_AXI_BYTES_LOG:0] wr_cmd_step;\n wire [8-1:0] wr_cmd_length;\n wire wr_cmd_ready;\n \n // Write Address Channel.\n mig_7series_v4_0_ddr_a_upsizer #\n (\n .C_FAMILY (C_FAMILY),\n .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),\n .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),\n .C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),\n .C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),\n .C_M_AXI_REGISTER (C_M_AXI_AW_REGISTER),\n .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),\n .C_AXI_AUSER_WIDTH (C_AXI_AWUSER_WIDTH),\n .C_AXI_CHANNEL (0),\n .C_PACKING_LEVEL (C_PACKING_LEVEL),\n .C_SUPPORT_BURSTS (C_SUPPORT_BURSTS),\n .C_SINGLE_THREAD (C_SINGLE_THREAD),\n .C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),\n .C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG)\n ) write_addr_inst\n (\n // Global Signals\n .ARESET (ARESET),\n .ACLK (ACLK),\n \n // Command Interface\n .cmd_valid (wr_cmd_valid),\n .cmd_fix (wr_cmd_fix),\n .cmd_modified (wr_cmd_modified),\n .cmd_complete_wrap (wr_cmd_complete_wrap),\n .cmd_packed_wrap (wr_cmd_packed_wrap),\n .cmd_first_word (wr_cmd_first_word),\n .cmd_next_word (wr_cmd_next_word),\n .cmd_last_word (wr_cmd_last_word),\n .cmd_offset (wr_cmd_offset),\n .cmd_mask (wr_cmd_mask),\n .cmd_step (wr_cmd_step),\n .cmd_length (wr_cmd_length),\n .cmd_ready (wr_cmd_ready),\n \n // Slave Interface Write Address Ports\n .S_AXI_AID (sr_AWID),\n .S_AXI_AADDR (sr_AWADDR),\n .S_AXI_ALEN (sr_AWLEN),\n .S_AXI_ASIZE (sr_AWSIZE),\n .S_AXI_ABURST (sr_AWBURST),\n .S_AXI_ALOCK (sr_AWLOCK),\n .S_AXI_ACACHE (sr_AWCACHE),\n .S_AXI_APROT (sr_AWPROT),\n .S_AXI_AREGION (sr_AWREGION),\n .S_AXI_AQOS (sr_AWQOS),\n .S_AXI_AUSER (sr_AWUSER),\n .S_AXI_AVALID (sr_AWVALID),\n .S_AXI_AREADY (sr_AWREADY),\n \n // Master Interface Write Address Port\n .M_AXI_AID (M_AXI_AWID),\n .M_AXI_AADDR (M_AXI_AWADDR),\n .M_AXI_ALEN (M_AXI_AWLEN),\n .M_AXI_ASIZE (M_AXI_AWSIZE),\n .M_AXI_ABURST (M_AXI_AWBURST),\n .M_AXI_ALOCK (M_AXI_AWLOCK),\n .M_AXI_ACACHE (M_AXI_AWCACHE),\n .M_AXI_APROT (M_AXI_AWPROT),\n .M_AXI_AREGION (M_AXI_AWREGION),\n .M_AXI_AQOS (M_AXI_AWQOS),\n .M_AXI_AUSER (M_AXI_AWUSER),\n .M_AXI_AVALID (M_AXI_AWVALID),\n .M_AXI_AREADY (M_AXI_AWREADY)\n );\n \n // Write Data channel.\n mig_7series_v4_0_ddr_w_upsizer #\n (\n .C_FAMILY (C_FAMILY),\n .C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),\n .C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),\n .C_M_AXI_REGISTER (1),\n .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),\n .C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH),\n .C_PACKING_LEVEL (C_PACKING_LEVEL),\n .C_SUPPORT_BURSTS (C_SUPPORT_BURSTS),\n .C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),\n .C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),\n .C_RATIO (C_RATIO),\n .C_RATIO_LOG (C_RATIO_LOG)\n ) write_data_inst\n (\n // Global Signals\n .ARESET (ARESET),\n .ACLK (ACLK),\n \n // Command Interface\n .cmd_valid (wr_cmd_valid),\n .cmd_fix (wr_cmd_fix),\n .cmd_modified (wr_cmd_modified),\n .cmd_complete_wrap (wr_cmd_complete_wrap),\n .cmd_packed_wrap (wr_cmd_packed_wrap),\n .cmd_first_word (wr_cmd_first_word),\n .cmd_next_word (wr_cmd_next_word),\n .cmd_last_word (wr_cmd_last_word),\n .cmd_offset (wr_cmd_offset),\n .cmd_mask (wr_cmd_mask),\n .cmd_step (wr_cmd_step),\n .cmd_length (wr_cmd_length),\n .cmd_ready (wr_cmd_ready),\n \n // Slave Interface Write Data Ports\n .S_AXI_WDATA (S_AXI_WDATA),\n .S_AXI_WSTRB (S_AXI_WSTRB),\n .S_AXI_WLAST (S_AXI_WLAST),\n .S_AXI_WUSER (S_AXI_WUSER),\n .S_AXI_WVALID (S_AXI_WVALID),\n .S_AXI_WREADY (S_AXI_WREADY),\n \n // Master Interface Write Data Ports\n .M_AXI_WDATA (M_AXI_WDATA),\n .M_AXI_WSTRB (M_AXI_WSTRB),\n .M_AXI_WLAST (M_AXI_WLAST),\n .M_AXI_WUSER (),\n .M_AXI_WVALID (M_AXI_WVALID),\n .M_AXI_WREADY (M_AXI_WREADY)\n );\n \n // Write Response channel.\n assign S_AXI_BID = M_AXI_BID;\n assign S_AXI_BRESP = M_AXI_BRESP;\n assign S_AXI_BUSER = M_AXI_BUSER;\n assign S_AXI_BVALID = M_AXI_BVALID;\n assign M_AXI_BREADY = S_AXI_BREADY;\n \n end else begin : NO_WRITE\n assign sr_AWREADY = 1'b0;\n assign S_AXI_WREADY = 1'b0;\n assign S_AXI_BID = {C_AXI_ID_WIDTH{1'b0}};\n assign S_AXI_BRESP = 2'b0;\n assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}};\n assign S_AXI_BVALID = 1'b0;\n \n assign M_AXI_AWID = {C_AXI_ID_WIDTH{1'b0}};\n assign M_AXI_AWADDR = {C_AXI_ADDR_WIDTH{1'b0}};\n assign M_AXI_AWLEN = 8'b0;\n assign M_AXI_AWSIZE = 3'b0;\n assign M_AXI_AWBURST = 2'b0;\n assign M_AXI_AWLOCK = 2'b0;\n assign M_AXI_AWCACHE = 4'b0;\n assign M_AXI_AWPROT = 3'b0;\n assign M_AXI_AWQOS = 4'b0;\n assign M_AXI_AWUSER = {C_AXI_AWUSER_WIDTH{1'b0}};\n assign M_AXI_AWVALID = 1'b0;\n assign M_AXI_WDATA = {C_M_AXI_DATA_WIDTH{1'b0}};\n assign M_AXI_WSTRB = {C_M_AXI_DATA_WIDTH/8{1'b0}};\n assign M_AXI_WLAST = 1'b0;\n assign M_AXI_WVALID = 1'b0;\n assign M_AXI_BREADY = 1'b0;\n \n end\n endgenerate\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Handle Read Channels (AR/R)\n /////////////////////////////////////////////////////////////////////////////\n generate\n if (C_AXI_SUPPORTS_READ == 1) begin : USE_READ\n \n // Read Channel Signals for Commands Queue Interface.\n wire rd_cmd_valid;\n wire rd_cmd_fix;\n wire rd_cmd_modified;\n wire rd_cmd_complete_wrap;\n wire rd_cmd_packed_wrap;\n wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_first_word;\n wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_next_word;\n wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_last_word;\n wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_offset;\n wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_mask;\n wire [C_S_AXI_BYTES_LOG:0] rd_cmd_step;\n wire [8-1:0] rd_cmd_length;\n wire rd_cmd_ready;\n \n // Write Address Channel.\n mig_7series_v4_0_ddr_a_upsizer #\n (\n .C_FAMILY (C_FAMILY),\n .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),\n .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),\n .C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),\n .C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),\n .C_M_AXI_REGISTER (C_M_AXI_AR_REGISTER),\n .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),\n .C_AXI_AUSER_WIDTH (C_AXI_ARUSER_WIDTH),\n .C_AXI_CHANNEL (1),\n .C_PACKING_LEVEL (C_PACKING_LEVEL),\n .C_SUPPORT_BURSTS (C_SUPPORT_BURSTS),\n .C_SINGLE_THREAD (C_SINGLE_THREAD),\n .C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),\n .C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG)\n ) read_addr_inst\n (\n // Global Signals\n .ARESET (ARESET),\n .ACLK (ACLK),\n \n // Command Interface\n .cmd_valid (rd_cmd_valid),\n .cmd_fix (rd_cmd_fix),\n .cmd_modified (rd_cmd_modified),\n .cmd_complete_wrap (rd_cmd_complete_wrap),\n .cmd_packed_wrap (rd_cmd_packed_wrap),\n .cmd_first_word (rd_cmd_first_word),\n .cmd_next_word (rd_cmd_next_word),\n .cmd_last_word (rd_cmd_last_word),\n .cmd_offset (rd_cmd_offset),\n .cmd_mask (rd_cmd_mask),\n .cmd_step (rd_cmd_step),\n .cmd_length (rd_cmd_length),\n .cmd_ready (rd_cmd_ready),\n \n // Slave Interface Write Address Ports\n .S_AXI_AID (sr_ARID),\n .S_AXI_AADDR (sr_ARADDR),\n .S_AXI_ALEN (sr_ARLEN),\n .S_AXI_ASIZE (sr_ARSIZE),\n .S_AXI_ABURST (sr_ARBURST),\n .S_AXI_ALOCK (sr_ARLOCK),\n .S_AXI_ACACHE (sr_ARCACHE),\n .S_AXI_APROT (sr_ARPROT),\n .S_AXI_AREGION (sr_ARREGION),\n .S_AXI_AQOS (sr_ARQOS),\n .S_AXI_AUSER (sr_ARUSER),\n .S_AXI_AVALID (sr_ARVALID),\n .S_AXI_AREADY (sr_ARREADY),\n \n // Master Interface Write Address Port\n .M_AXI_AID (M_AXI_ARID),\n .M_AXI_AADDR (M_AXI_ARADDR),\n .M_AXI_ALEN (M_AXI_ARLEN),\n .M_AXI_ASIZE (M_AXI_ARSIZE),\n .M_AXI_ABURST (M_AXI_ARBURST),\n .M_AXI_ALOCK (M_AXI_ARLOCK),\n .M_AXI_ACACHE (M_AXI_ARCACHE),\n .M_AXI_APROT (M_AXI_ARPROT),\n .M_AXI_AREGION (M_AXI_ARREGION),\n .M_AXI_AQOS (M_AXI_ARQOS),\n .M_AXI_AUSER (M_AXI_ARUSER),\n .M_AXI_AVALID (M_AXI_ARVALID),\n .M_AXI_AREADY (M_AXI_ARREADY)\n );\n \n // Read Data channel.\n mig_7series_v4_0_ddr_r_upsizer #\n (\n .C_FAMILY (C_FAMILY),\n .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),\n .C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),\n .C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),\n .C_S_AXI_REGISTER (C_S_AXI_R_REGISTER),\n .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),\n .C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),\n .C_PACKING_LEVEL (C_PACKING_LEVEL),\n .C_SUPPORT_BURSTS (C_SUPPORT_BURSTS),\n .C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),\n .C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),\n .C_RATIO (C_RATIO),\n .C_RATIO_LOG (C_RATIO_LOG)\n ) read_data_inst\n (\n // Global Signals\n .ARESET (ARESET),\n .ACLK (ACLK),\n \n // Command Interface\n .cmd_valid (rd_cmd_valid),\n .cmd_fix (rd_cmd_fix),\n .cmd_modified (rd_cmd_modified),\n .cmd_complete_wrap (rd_cmd_complete_wrap),\n .cmd_packed_wrap (rd_cmd_packed_wrap),\n .cmd_first_word (rd_cmd_first_word),\n .cmd_next_word (rd_cmd_next_word),\n .cmd_last_word (rd_cmd_last_word),\n .cmd_offset (rd_cmd_offset),\n .cmd_mask (rd_cmd_mask),\n .cmd_step (rd_cmd_step),\n .cmd_length (rd_cmd_length),\n .cmd_ready (rd_cmd_ready),\n \n // Slave Interface Read Data Ports\n .S_AXI_RID (S_AXI_RID),\n .S_AXI_RDATA (S_AXI_RDATA),\n .S_AXI_RRESP (S_AXI_RRESP),\n .S_AXI_RLAST (S_AXI_RLAST),\n .S_AXI_RUSER (),\n .S_AXI_RVALID (S_AXI_RVALID),\n .S_AXI_RREADY (S_AXI_RREADY),\n \n // Master Interface Read Data Ports\n .M_AXI_RID (mr_RID),\n .M_AXI_RDATA (mr_RDATA),\n .M_AXI_RRESP (mr_RRESP),\n .M_AXI_RLAST (mr_RLAST),\n .M_AXI_RUSER (mr_RUSER),\n .M_AXI_RVALID (mr_RVALID),\n .M_AXI_RREADY (mr_RREADY)\n );\n \n end else begin : NO_READ\n assign sr_ARREADY = 1'b0;\n assign S_AXI_RID = {C_AXI_ID_WIDTH{1'b0}};\n assign S_AXI_RDATA = {C_S_AXI_DATA_WIDTH{1'b0}};\n assign S_AXI_RRESP = 2'b0;\n assign S_AXI_RLAST = 1'b0;\n assign S_AXI_RVALID = 1'b0;\n \n assign M_AXI_ARID = {C_AXI_ID_WIDTH{1'b0}};\n assign M_AXI_ARADDR = {C_AXI_ADDR_WIDTH{1'b0}};\n assign M_AXI_ARLEN = 8'b0;\n assign M_AXI_ARSIZE = 3'b0;\n assign M_AXI_ARBURST = 2'b0;\n assign M_AXI_ARLOCK = 2'b0;\n assign M_AXI_ARCACHE = 4'b0;\n assign M_AXI_ARPROT = 3'b0;\n assign M_AXI_ARQOS = 4'b0;\n assign M_AXI_ARUSER = {C_AXI_ARUSER_WIDTH{1'b0}};\n assign M_AXI_ARVALID = 1'b0;\n assign mr_RREADY = 1'b0;\n \n end\n endgenerate\n \n \nendmodule\n`default_nettype wire\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_axic_register_slice.v", "content": "// -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Register Slice\n// Generic single-channel AXI pipeline register on forward and/or reverse signal path\n//\n// Verilog-standard: Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n// ddr_axic_register_slice\n//\n//--------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule mig_7series_v4_0_ddr_axic_register_slice #\n (\n parameter C_FAMILY = \"virtex6\",\n parameter C_DATA_WIDTH = 32,\n parameter C_REG_CONFIG = 32'h00000000\n // C_REG_CONFIG:\n // 0 => BYPASS = The channel is just wired through the module.\n // 1 => FWD_REV = Both FWD and REV (fully-registered)\n // 2 => FWD = The master VALID and payload signals are registrated. \n // 3 => REV = The slave ready signal is registrated\n // 4 => RESERVED (all outputs driven to 0).\n // 5 => RESERVED (all outputs driven to 0).\n // 6 => INPUTS = Slave and Master side inputs are registrated.\n // 7 => LIGHT_WT = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n )\n (\n // System Signals\n input wire ACLK,\n input wire ARESET,\n\n // Slave side\n input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n input wire S_VALID,\n output wire S_READY,\n\n // Master side\n output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,\n output wire M_VALID,\n input wire M_READY\n );\n\n (* use_clock_enable = \"yes\" *)\n\n generate\n ////////////////////////////////////////////////////////////////////\n //\n // C_REG_CONFIG = 0\n // Bypass mode\n //\n ////////////////////////////////////////////////////////////////////\n if (C_REG_CONFIG == 32'h00000000)\n begin\n assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n assign M_VALID = S_VALID;\n assign S_READY = M_READY; \n end\n ////////////////////////////////////////////////////////////////////\n //\n // C_REG_CONFIG = 1 (or 8)\n // Both FWD and REV mode\n //\n ////////////////////////////////////////////////////////////////////\n else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008))\n begin\n (* max_fanout = 50 *) reg [1:0] state /* synthesis syn_maxfan = 30 */;\n localparam [1:0] \n ZERO = 2'b10,\n ONE = 2'b11,\n TWO = 2'b01;\n \n reg [C_DATA_WIDTH-1:0] storage_data1;\n reg [C_DATA_WIDTH-1:0] storage_data2;\n reg load_s1;\n wire load_s2;\n wire load_s1_from_s2;\n reg s_ready_i; //local signal of output\n wire m_valid_i; //local signal of output\n\n // assign local signal to its output signal\n assign S_READY = s_ready_i;\n assign M_VALID = m_valid_i;\n\n reg [1:0] areset_d; // Reset delay register\n always @(posedge ACLK) begin\n areset_d <= {areset_d[0], ARESET};\n end\n \n // Load storage1 with either slave side data or from storage2\n always @(posedge ACLK) \n begin\n if (load_s1)\n if (load_s1_from_s2)\n storage_data1 <= storage_data2;\n else\n storage_data1 <= S_PAYLOAD_DATA; \n end\n\n // Load storage2 with slave side data\n always @(posedge ACLK) \n begin\n if (load_s2)\n storage_data2 <= S_PAYLOAD_DATA;\n end\n\n assign M_PAYLOAD_DATA = storage_data1;\n\n // Always load s2 on a valid transaction even if it's unnecessary\n assign load_s2 = S_VALID & s_ready_i;\n\n // Loading s1\n always @ *\n begin\n if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction\n // Load when ONE if we both have read and write at the same time\n ((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||\n // Load when TWO and we have a transaction on Master side\n ((state == TWO) && (M_READY == 1)))\n load_s1 = 1'b1;\n else\n load_s1 = 1'b0;\n end // always @ *\n\n assign load_s1_from_s2 = (state == TWO);\n \n // State Machine for handling output signals\n always @(posedge ACLK) begin\n if (ARESET) begin\n s_ready_i <= 1'b0;\n state <= ZERO;\n end else if (areset_d == 2'b10) begin\n s_ready_i <= 1'b1;\n end else if (areset_d == 2'b00) begin\n case (state)\n // No transaction stored locally\n ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE\n\n // One transaction stored locally\n ONE: begin\n if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO\n// if (~M_READY & S_VALID) begin\n else if (~M_READY & S_VALID) begin\n state <= TWO; // Got another one so move to TWO\n s_ready_i <= 1'b0;\n end\n end\n\n // TWO transaction stored locally\n TWO: if (M_READY) begin\n state <= ONE; // Read out one so move to ONE\n s_ready_i <= 1'b1;\n end\n endcase // case (state)\n end\n end // always @ (posedge ACLK)\n \n assign m_valid_i = state[0];\n\n end // if (C_REG_CONFIG == 1)\n \n ////////////////////////////////////////////////////////////////////\n //\n // C_REG_CONFIG = 2\n // Only FWD mode\n //\n ////////////////////////////////////////////////////////////////////\n else if (C_REG_CONFIG == 32'h00000002)\n begin\n reg [C_DATA_WIDTH-1:0] storage_data;\n wire s_ready_i; //local signal of output\n reg m_valid_i; //local signal of output\n\n // assign local signal to its output signal\n assign S_READY = s_ready_i;\n assign M_VALID = m_valid_i;\n\n (* equivalent_register_removal = \"no\" *) reg [1:0] areset_d; // Reset delay register\n always @(posedge ACLK) begin\n areset_d <= {areset_d[0], ARESET};\n end\n \n // Save payload data whenever we have a transaction on the slave side\n always @(posedge ACLK) \n begin\n if (S_VALID & s_ready_i)\n storage_data <= S_PAYLOAD_DATA;\n end\n\n assign M_PAYLOAD_DATA = storage_data;\n \n // M_Valid set to high when we have a completed transfer on slave side\n // Is removed on a M_READY except if we have a new transfer on the slave side\n always @(posedge ACLK) \n begin\n if (areset_d) \n m_valid_i <= 1'b0;\n else\n if (S_VALID) // Always set m_valid_i when slave side is valid\n m_valid_i <= 1'b1;\n else\n if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready\n m_valid_i <= 1'b0;\n end // always @ (posedge ACLK)\n \n // Slave Ready is either when Master side drives M_Ready or we have space in our storage data\n assign s_ready_i = (M_READY | ~m_valid_i) & ~|areset_d;\n\n end // if (C_REG_CONFIG == 2)\n ////////////////////////////////////////////////////////////////////\n //\n // C_REG_CONFIG = 3\n // Only REV mode\n //\n ////////////////////////////////////////////////////////////////////\n else if (C_REG_CONFIG == 32'h00000003)\n begin\n reg [C_DATA_WIDTH-1:0] storage_data;\n reg s_ready_i; //local signal of output\n reg has_valid_storage_i;\n reg has_valid_storage;\n\n (* equivalent_register_removal = \"no\" *) reg areset_d; // Reset delay register\n always @(posedge ACLK) begin\n areset_d <= ARESET;\n end\n \n // Save payload data whenever we have a transaction on the slave side\n always @(posedge ACLK) \n begin\n if (S_VALID & s_ready_i)\n storage_data <= S_PAYLOAD_DATA;\n end\n\n assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;\n\n // Need to determine when we need to save a payload\n // Need a combinatorial signals since it will also effect S_READY\n always @ *\n begin\n // Set the value if we have a slave transaction but master side is not ready\n if (S_VALID & s_ready_i & ~M_READY)\n has_valid_storage_i = 1'b1;\n \n // Clear the value if it's set and Master side completes the transaction but we don't have a new slave side \n // transaction \n else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))\n has_valid_storage_i = 1'b0;\n else\n has_valid_storage_i = has_valid_storage;\n end // always @ *\n\n always @(posedge ACLK) \n begin\n if (ARESET) \n has_valid_storage <= 1'b0;\n else\n has_valid_storage <= has_valid_storage_i;\n end\n\n // S_READY is either clocked M_READY or that we have room in local storage\n always @(posedge ACLK) \n begin\n if (ARESET) \n s_ready_i <= 1'b0;\n else\n s_ready_i <= M_READY | ~has_valid_storage_i;\n end\n\n // assign local signal to its output signal\n assign S_READY = s_ready_i;\n\n // M_READY is either combinatorial S_READY or that we have valid data in local storage\n assign M_VALID = (S_VALID | has_valid_storage) & ~areset_d;\n \n end // if (C_REG_CONFIG == 3)\n \n ////////////////////////////////////////////////////////////////////\n //\n // C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED\n //\n ////////////////////////////////////////////////////////////////////\n else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))\n begin\n// synthesis translate_off\n initial begin \n $display (\"ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.\");\n end\n// synthesis translate_on\n assign M_PAYLOAD_DATA = 0;\n assign M_VALID = 1'b0;\n assign S_READY = 1'b0; \n end \n\n ////////////////////////////////////////////////////////////////////\n //\n // C_REG_CONFIG = 6\n // INPUTS mode\n //\n ////////////////////////////////////////////////////////////////////\n else if (C_REG_CONFIG == 32'h00000006)\n begin\n reg [1:0] state;\n reg [1:0] next_state;\n localparam [1:0] \n ZERO = 2'b00,\n ONE = 2'b01,\n TWO = 2'b11;\n\n reg [C_DATA_WIDTH-1:0] storage_data1;\n reg [C_DATA_WIDTH-1:0] storage_data2;\n reg s_valid_d;\n reg s_ready_d;\n reg m_ready_d;\n reg m_valid_d;\n reg load_s2;\n reg sel_s2;\n wire new_access;\n wire access_done;\n wire s_ready_i; //local signal of output\n reg s_ready_ii;\n reg m_valid_i; //local signal of output\n \n (* equivalent_register_removal = \"no\" *) reg areset_d; // Reset delay register\n always @(posedge ACLK) begin\n areset_d <= ARESET;\n end\n \n // assign local signal to its output signal\n assign S_READY = s_ready_i;\n assign M_VALID = m_valid_i;\n assign s_ready_i = s_ready_ii & ~areset_d;\n\n // Registrate input control signals\n always @(posedge ACLK) \n begin\n if (ARESET) begin \n s_valid_d <= 1'b0;\n s_ready_d <= 1'b0;\n m_ready_d <= 1'b0;\n end else begin\n s_valid_d <= S_VALID;\n s_ready_d <= s_ready_i;\n m_ready_d <= M_READY;\n end\n end // always @ (posedge ACLK)\n\n // Load storage1 with slave side payload data when slave side ready is high\n always @(posedge ACLK) \n begin\n if (s_ready_i)\n storage_data1 <= S_PAYLOAD_DATA; \n end\n\n // Load storage2 with storage data \n always @(posedge ACLK) \n begin\n if (load_s2)\n storage_data2 <= storage_data1;\n end\n\n always @(posedge ACLK) \n begin\n if (ARESET) \n m_valid_d <= 1'b0;\n else \n m_valid_d <= m_valid_i;\n end\n\n // Local help signals\n assign new_access = s_ready_d & s_valid_d;\n assign access_done = m_ready_d & m_valid_d;\n\n\n // State Machine for handling output signals\n always @*\n begin\n next_state = state; // Stay in the same state unless we need to move to another state\n load_s2 = 0;\n sel_s2 = 0;\n m_valid_i = 0;\n s_ready_ii = 0;\n case (state)\n // No transaction stored locally\n ZERO: begin\n load_s2 = 0;\n sel_s2 = 0;\n m_valid_i = 0;\n s_ready_ii = 1;\n if (new_access) begin\n next_state = ONE; // Got one so move to ONE\n load_s2 = 1;\n m_valid_i = 0;\n end\n else begin\n next_state = next_state;\n load_s2 = load_s2;\n m_valid_i = m_valid_i;\n end\n\n end // case: ZERO\n\n // One transaction stored locally\n ONE: begin\n load_s2 = 0;\n sel_s2 = 1;\n m_valid_i = 1;\n s_ready_ii = 1;\n if (~new_access & access_done) begin\n next_state = ZERO; // Read out one so move to ZERO\n m_valid_i = 0; \n end\n else if (new_access & ~access_done) begin\n next_state = TWO; // Got another one so move to TWO\n s_ready_ii = 0;\n end\n else if (new_access & access_done) begin\n load_s2 = 1;\n sel_s2 = 0;\n end\n else begin\n load_s2 = load_s2;\n sel_s2 = sel_s2;\n end\n\n\n end // case: ONE\n\n // TWO transaction stored locally\n TWO: begin\n load_s2 = 0;\n sel_s2 = 1;\n m_valid_i = 1;\n s_ready_ii = 0;\n if (access_done) begin \n next_state = ONE; // Read out one so move to ONE\n s_ready_ii = 1;\n load_s2 = 1;\n sel_s2 = 0;\n end\n else begin\n next_state = next_state;\n s_ready_ii = s_ready_ii;\n load_s2 = load_s2;\n sel_s2 = sel_s2;\n end\n end // case: TWO\n endcase // case (state)\n end // always @ *\n\n\n // State Machine for handling output signals\n always @(posedge ACLK) \n begin\n if (ARESET) \n state <= ZERO;\n else\n state <= next_state; // Stay in the same state unless we need to move to another state\n end\n \n // Master Payload mux\n assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;\n\n end // if (C_REG_CONFIG == 6)\n ////////////////////////////////////////////////////////////////////\n //\n // C_REG_CONFIG = 7\n // Light-weight mode.\n // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining\n // Operates same as 1-deep FIFO\n //\n ////////////////////////////////////////////////////////////////////\n else if (C_REG_CONFIG == 32'h00000007)\n begin\n reg [C_DATA_WIDTH-1:0] storage_data1;\n reg s_ready_i; //local signal of output\n reg m_valid_i; //local signal of output\n\n // assign local signal to its output signal\n assign S_READY = s_ready_i;\n assign M_VALID = m_valid_i;\n\n reg [1:0] areset_d; // Reset delay register\n always @(posedge ACLK) begin\n areset_d <= {areset_d[0], ARESET};\n end\n \n // Load storage1 with slave side data\n always @(posedge ACLK) \n begin\n if (ARESET) begin\n s_ready_i <= 1'b0;\n m_valid_i <= 1'b0;\n end else if (areset_d == 2'b10) begin\n s_ready_i <= 1'b1;\n end else if (areset_d == 2'b00) begin\n if (m_valid_i & M_READY) begin\n s_ready_i <= 1'b1;\n m_valid_i <= 1'b0;\n end else if (S_VALID & s_ready_i) begin\n s_ready_i <= 1'b0;\n m_valid_i <= 1'b1;\n end\n end\n if (~m_valid_i) begin\n storage_data1 <= S_PAYLOAD_DATA; \n end\n end\n assign M_PAYLOAD_DATA = storage_data1;\n end // if (C_REG_CONFIG == 7)\n \n else begin : default_case\n // Passthrough\n assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;\n assign M_VALID = S_VALID;\n assign S_READY = M_READY; \n end\n\n endgenerate\nendmodule // reg_slice\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_carry_and.v", "content": "// -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n// Optimized AND with carry logic.\n//\n// Verilog-standard: Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n// \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\nmodule mig_7series_v4_0_ddr_carry_and #\n (\n parameter C_FAMILY = \"virtex6\"\n // FPGA Family. Current version: virtex6 or spartan6.\n )\n (\n input wire CIN,\n input wire S,\n output wire COUT\n );\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Variables for generating parameter controlled instances.\n /////////////////////////////////////////////////////////////////////////////\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Local params\n /////////////////////////////////////////////////////////////////////////////\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Functions\n /////////////////////////////////////////////////////////////////////////////\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Internal signals\n /////////////////////////////////////////////////////////////////////////////\n\n \n /////////////////////////////////////////////////////////////////////////////\n // Instantiate or use RTL code\n /////////////////////////////////////////////////////////////////////////////\n \n generate\n if ( C_FAMILY == \"rtl\" ) begin : USE_RTL\n assign COUT = CIN & S;\n \n end else begin : USE_FPGA\n MUXCY and_inst \n (\n .O (COUT), \n .CI (CIN), \n .DI (1'b0), \n .S (S)\n ); \n \n end\n endgenerate\n \n \nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_carry_latch_and.v", "content": "// -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n// Optimized AND with carry logic.\n//\n// Verilog-standard: Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n// \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\nmodule mig_7series_v4_0_ddr_carry_latch_and #\n (\n parameter C_FAMILY = \"virtex6\"\n // FPGA Family. Current version: virtex6 or spartan6.\n )\n (\n input wire CIN,\n input wire I,\n output wire O\n );\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Variables for generating parameter controlled instances.\n /////////////////////////////////////////////////////////////////////////////\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Local params\n /////////////////////////////////////////////////////////////////////////////\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Functions\n /////////////////////////////////////////////////////////////////////////////\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Internal signals\n /////////////////////////////////////////////////////////////////////////////\n\n \n /////////////////////////////////////////////////////////////////////////////\n // Instantiate or use RTL code\n /////////////////////////////////////////////////////////////////////////////\n \n generate\n if ( C_FAMILY == \"rtl\" ) begin : USE_RTL\n assign O = CIN & ~I;\n \n end else begin : USE_FPGA\n wire I_n;\n \n assign I_n = ~I;\n \n AND2B1L and2b1l_inst \n (\n .O(O),\n .DI(CIN),\n .SRI(I_n)\n );\n \n end\n endgenerate\n \n \nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_carry_latch_or.v", "content": "// -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n// Optimized OR with carry logic.\n//\n// Verilog-standard: Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n// \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\nmodule mig_7series_v4_0_ddr_carry_latch_or #\n (\n parameter C_FAMILY = \"virtex6\"\n // FPGA Family. Current version: virtex6 or spartan6.\n )\n (\n input wire CIN,\n input wire I,\n output wire O\n );\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Variables for generating parameter controlled instances.\n /////////////////////////////////////////////////////////////////////////////\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Local params\n /////////////////////////////////////////////////////////////////////////////\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Functions\n /////////////////////////////////////////////////////////////////////////////\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Internal signals\n /////////////////////////////////////////////////////////////////////////////\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Instantiate or use RTL code\n /////////////////////////////////////////////////////////////////////////////\n \n generate\n if ( C_FAMILY == \"rtl\" ) begin : USE_RTL\n assign O = CIN | I;\n \n end else begin : USE_FPGA\n OR2L or2l_inst1\n (\n .O(O),\n .DI(CIN),\n .SRI(I)\n );\n \n end\n endgenerate\n \n \nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_carry_or.v", "content": "// -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n// Optimized OR with carry logic.\n//\n// Verilog-standard: Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n// \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\nmodule mig_7series_v4_0_ddr_carry_or #\n (\n parameter C_FAMILY = \"virtex6\"\n // FPGA Family. Current version: virtex6 or spartan6.\n )\n (\n input wire CIN,\n input wire S,\n output wire COUT\n );\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Variables for generating parameter controlled instances.\n /////////////////////////////////////////////////////////////////////////////\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Local params\n /////////////////////////////////////////////////////////////////////////////\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Functions\n /////////////////////////////////////////////////////////////////////////////\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Internal signals\n /////////////////////////////////////////////////////////////////////////////\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Instantiate or use RTL code\n /////////////////////////////////////////////////////////////////////////////\n \n generate\n if ( C_FAMILY == \"rtl\" ) begin : USE_RTL\n assign COUT = CIN | S;\n \n end else begin : USE_FPGA\n wire S_n;\n \n assign S_n = ~S;\n \n MUXCY and_inst \n (\n .O (COUT), \n .CI (CIN), \n .DI (1'b1), \n .S (S_n)\n ); \n \n end\n endgenerate\n \n \nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_command_fifo.v", "content": "// -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n// Optimized 16/32 word deep FIFO.\n//\n// Verilog-standard: Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n// \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\nmodule mig_7series_v4_0_ddr_command_fifo #\n (\n parameter C_FAMILY = \"virtex6\",\n parameter integer C_ENABLE_S_VALID_CARRY = 0,\n parameter integer C_ENABLE_REGISTERED_OUTPUT = 0,\n parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG\n // Range = [4:5].\n parameter integer C_FIFO_WIDTH = 64 // Width of payload [1:512]\n )\n (\n // Global inputs\n input wire ACLK, // Clock\n input wire ARESET, // Reset\n // Information\n output wire EMPTY, // FIFO empty (all stages)\n // Slave Port\n input wire [C_FIFO_WIDTH-1:0] S_MESG, // Payload (may be any set of channel signals)\n input wire S_VALID, // FIFO push\n output wire S_READY, // FIFO not full\n // Master Port\n output wire [C_FIFO_WIDTH-1:0] M_MESG, // Payload\n output wire M_VALID, // FIFO not empty\n input wire M_READY // FIFO pop\n );\n\n /////////////////////////////////////////////////////////////////////////////\n // Variables for generating parameter controlled instances.\n /////////////////////////////////////////////////////////////////////////////\n \n // Generate variable for data vector.\n genvar addr_cnt;\n genvar bit_cnt;\n integer index;\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Internal signals\n /////////////////////////////////////////////////////////////////////////////\n \n wire [C_FIFO_DEPTH_LOG-1:0] addr;\n wire buffer_Full;\n wire buffer_Empty;\n \n wire next_Data_Exists;\n reg data_Exists_I;\n \n wire valid_Write;\n wire new_write;\n \n wire [C_FIFO_DEPTH_LOG-1:0] hsum_A;\n wire [C_FIFO_DEPTH_LOG-1:0] sum_A;\n wire [C_FIFO_DEPTH_LOG-1:0] addr_cy;\n\n wire buffer_full_early;\n \n wire [C_FIFO_WIDTH-1:0] M_MESG_I; // Payload\n wire M_VALID_I; // FIFO not empty\n wire M_READY_I; // FIFO pop\n \n /////////////////////////////////////////////////////////////////////////////\n // Create Flags \n /////////////////////////////////////////////////////////////////////////////\n \n assign buffer_full_early = ( (addr == {{C_FIFO_DEPTH_LOG-1{1'b1}}, 1'b0}) & valid_Write & ~M_READY_I ) |\n ( buffer_Full & ~M_READY_I );\n\n assign S_READY = ~buffer_Full;\n\n assign buffer_Empty = (addr == {C_FIFO_DEPTH_LOG{1'b0}});\n\n assign next_Data_Exists = (data_Exists_I & ~buffer_Empty) |\n (buffer_Empty & S_VALID) |\n (data_Exists_I & ~(M_READY_I & data_Exists_I));\n\n always @ (posedge ACLK) begin\n if (ARESET) begin\n data_Exists_I <= 1'b0;\n end else begin\n data_Exists_I <= next_Data_Exists;\n end\n end\n\n assign M_VALID_I = data_Exists_I;\n \n // Select RTL or FPGA optimized instatiations for critical parts.\n generate\n if ( C_FAMILY == \"rtl\" || C_ENABLE_S_VALID_CARRY == 0 ) begin : USE_RTL_VALID_WRITE\n reg buffer_Full_q;\n \n assign valid_Write = S_VALID & ~buffer_Full;\n \n assign new_write = (S_VALID | ~buffer_Empty);\n \n assign addr_cy[0] = valid_Write;\n \n always @ (posedge ACLK) begin\n if (ARESET) begin\n buffer_Full_q <= 1'b0;\n end else if ( data_Exists_I ) begin\n buffer_Full_q <= buffer_full_early;\n end\n end\n assign buffer_Full = buffer_Full_q;\n \n end else begin : USE_FPGA_VALID_WRITE\n wire s_valid_dummy1;\n wire s_valid_dummy2;\n wire sel_s_valid;\n wire sel_new_write;\n wire valid_Write_dummy1;\n wire valid_Write_dummy2;\n \n assign sel_s_valid = ~buffer_Full;\n \n mig_7series_v4_0_ddr_carry_and #\n (\n .C_FAMILY(C_FAMILY)\n ) s_valid_dummy_inst1\n (\n .CIN(S_VALID),\n .S(1'b1),\n .COUT(s_valid_dummy1)\n );\n \n mig_7series_v4_0_ddr_carry_and #\n (\n .C_FAMILY(C_FAMILY)\n ) s_valid_dummy_inst2\n (\n .CIN(s_valid_dummy1),\n .S(1'b1),\n .COUT(s_valid_dummy2)\n );\n \n mig_7series_v4_0_ddr_carry_and #\n (\n .C_FAMILY(C_FAMILY)\n ) valid_write_inst\n (\n .CIN(s_valid_dummy2),\n .S(sel_s_valid),\n .COUT(valid_Write)\n );\n \n assign sel_new_write = ~buffer_Empty;\n \n mig_7series_v4_0_ddr_carry_latch_or #\n (\n .C_FAMILY(C_FAMILY)\n ) new_write_inst\n (\n .CIN(valid_Write),\n .I(sel_new_write),\n .O(new_write)\n );\n \n mig_7series_v4_0_ddr_carry_and #\n (\n .C_FAMILY(C_FAMILY)\n ) valid_write_dummy_inst1\n (\n .CIN(valid_Write),\n .S(1'b1),\n .COUT(valid_Write_dummy1)\n );\n \n mig_7series_v4_0_ddr_carry_and #\n (\n .C_FAMILY(C_FAMILY)\n ) valid_write_dummy_inst2\n (\n .CIN(valid_Write_dummy1),\n .S(1'b1),\n .COUT(valid_Write_dummy2)\n );\n \n mig_7series_v4_0_ddr_carry_and #\n (\n .C_FAMILY(C_FAMILY)\n ) valid_write_dummy_inst3\n (\n .CIN(valid_Write_dummy2),\n .S(1'b1),\n .COUT(addr_cy[0])\n );\n \n FDRE #(\n .INIT(1'b0) // Initial value of register (1'b0 or 1'b1)\n ) FDRE_I1 (\n .Q(buffer_Full), // Data output\n .C(ACLK), // Clock input\n .CE(data_Exists_I), // Clock enable input\n .R(ARESET), // Synchronous reset input\n .D(buffer_full_early) // Data input\n );\n \n end\n endgenerate\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Create address pointer\n /////////////////////////////////////////////////////////////////////////////\n\n generate\n if ( C_FAMILY == \"rtl\" ) begin : USE_RTL_ADDR\n \n reg [C_FIFO_DEPTH_LOG-1:0] addr_q;\n \n always @ (posedge ACLK) begin\n if (ARESET) begin\n addr_q <= {C_FIFO_DEPTH_LOG{1'b0}};\n end else if ( data_Exists_I ) begin\n if ( valid_Write & ~(M_READY_I & data_Exists_I) ) begin\n addr_q <= addr_q + 1'b1;\n end else if ( ~valid_Write & (M_READY_I & data_Exists_I) & ~buffer_Empty ) begin\n addr_q <= addr_q - 1'b1;\n end\n else begin\n addr_q <= addr_q;\n end\n end\n else begin\n addr_q <= addr_q;\n end\n end\n \n assign addr = addr_q;\n \n end else begin : USE_FPGA_ADDR\n for (addr_cnt = 0; addr_cnt < C_FIFO_DEPTH_LOG ; addr_cnt = addr_cnt + 1) begin : ADDR_GEN\n assign hsum_A[addr_cnt] = ((M_READY_I & data_Exists_I) ^ addr[addr_cnt]) & new_write;\n \n // Don't need the last muxcy, addr_cy(last) is not used anywhere\n if ( addr_cnt < C_FIFO_DEPTH_LOG - 1 ) begin : USE_MUXCY\n MUXCY MUXCY_inst (\n .DI(addr[addr_cnt]),\n .CI(addr_cy[addr_cnt]),\n .S(hsum_A[addr_cnt]),\n .O(addr_cy[addr_cnt+1])\n );\n \n end\n else begin : NO_MUXCY\n end\n \n XORCY XORCY_inst (\n .LI(hsum_A[addr_cnt]),\n .CI(addr_cy[addr_cnt]),\n .O(sum_A[addr_cnt])\n );\n \n FDRE #(\n .INIT(1'b0) // Initial value of register (1'b0 or 1'b1)\n ) FDRE_inst (\n .Q(addr[addr_cnt]), // Data output\n .C(ACLK), // Clock input\n .CE(data_Exists_I), // Clock enable input\n .R(ARESET), // Synchronous reset input\n .D(sum_A[addr_cnt]) // Data input\n );\n \n end // end for bit_cnt\n end // C_FAMILY\n endgenerate\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Data storage\n /////////////////////////////////////////////////////////////////////////////\n \n generate\n if ( C_FAMILY == \"rtl\" ) begin : USE_RTL_FIFO\n reg [C_FIFO_WIDTH-1:0] data_srl[2 ** C_FIFO_DEPTH_LOG-1:0];\n \n always @ (posedge ACLK) begin\n if ( valid_Write ) begin\n for (index = 0; index < 2 ** C_FIFO_DEPTH_LOG-1 ; index = index + 1) begin\n data_srl[index+1] <= data_srl[index];\n end\n data_srl[0] <= S_MESG;\n end\n end\n \n assign M_MESG_I = data_srl[addr];\n \n end else begin : USE_FPGA_FIFO\n for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN\n \n if ( C_FIFO_DEPTH_LOG == 5 ) begin : USE_32\n SRLC32E # (\n .INIT(32'h00000000) // Initial Value of Shift Register\n ) SRLC32E_inst (\n .Q(M_MESG_I[bit_cnt]), // SRL data output\n .Q31(), // SRL cascade output pin\n .A(addr), // 5-bit shift depth select input\n .CE(valid_Write), // Clock enable input\n .CLK(ACLK), // Clock input\n .D(S_MESG[bit_cnt]) // SRL data input\n );\n end else begin : USE_16\n SRLC16E # (\n .INIT(32'h00000000) // Initial Value of Shift Register\n ) SRLC16E_inst (\n .Q(M_MESG_I[bit_cnt]), // SRL data output\n .Q15(), // SRL cascade output pin\n .A0(addr[0]), // 4-bit shift depth select input 0\n .A1(addr[1]), // 4-bit shift depth select input 1\n .A2(addr[2]), // 4-bit shift depth select input 2\n .A3(addr[3]), // 4-bit shift depth select input 3\n .CE(valid_Write), // Clock enable input\n .CLK(ACLK), // Clock input\n .D(S_MESG[bit_cnt]) // SRL data input\n );\n end // C_FIFO_DEPTH_LOG\n \n end // end for bit_cnt\n end // C_FAMILY\n endgenerate\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Pipeline stage\n /////////////////////////////////////////////////////////////////////////////\n \n generate\n if ( C_ENABLE_REGISTERED_OUTPUT != 0 ) begin : USE_FF_OUT\n \n wire [C_FIFO_WIDTH-1:0] M_MESG_FF; // Payload\n wire M_VALID_FF; // FIFO not empty\n \n // Select RTL or FPGA optimized instatiations for critical parts.\n if ( C_FAMILY == \"rtl\" ) begin : USE_RTL_OUTPUT_PIPELINE\n \n reg [C_FIFO_WIDTH-1:0] M_MESG_Q; // Payload\n reg M_VALID_Q; // FIFO not empty\n \n always @ (posedge ACLK) begin\n if (ARESET) begin\n M_MESG_Q <= {C_FIFO_WIDTH{1'b0}};\n M_VALID_Q <= 1'b0;\n end else begin\n if ( M_READY_I ) begin\n M_MESG_Q <= M_MESG_I;\n M_VALID_Q <= M_VALID_I;\n end\n end\n end\n \n assign M_MESG_FF = M_MESG_Q;\n assign M_VALID_FF = M_VALID_Q;\n \n end else begin : USE_FPGA_OUTPUT_PIPELINE\n \n reg [C_FIFO_WIDTH-1:0] M_MESG_CMB; // Payload\n reg M_VALID_CMB; // FIFO not empty\n \n always @ *\n begin\n if ( M_READY_I ) begin\n M_MESG_CMB <= M_MESG_I;\n M_VALID_CMB <= M_VALID_I;\n end else begin\n M_MESG_CMB <= M_MESG_FF;\n M_VALID_CMB <= M_VALID_FF;\n end\n end\n \n for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN\n \n FDRE #(\n .INIT(1'b0) // Initial value of register (1'b0 or 1'b1)\n ) FDRE_inst (\n .Q(M_MESG_FF[bit_cnt]), // Data output\n .C(ACLK), // Clock input\n .CE(1'b1), // Clock enable input\n .R(ARESET), // Synchronous reset input\n .D(M_MESG_CMB[bit_cnt]) // Data input\n );\n end // end for bit_cnt\n \n FDRE #(\n .INIT(1'b0) // Initial value of register (1'b0 or 1'b1)\n ) FDRE_inst (\n .Q(M_VALID_FF), // Data output\n .C(ACLK), // Clock input\n .CE(1'b1), // Clock enable input\n .R(ARESET), // Synchronous reset input\n .D(M_VALID_CMB) // Data input\n );\n \n end\n \n assign EMPTY = ~M_VALID_I & ~M_VALID_FF;\n assign M_MESG = M_MESG_FF;\n assign M_VALID = M_VALID_FF;\n assign M_READY_I = ( M_READY & M_VALID_FF ) | ~M_VALID_FF;\n \n end else begin : NO_FF_OUT\n \n assign EMPTY = ~M_VALID_I;\n assign M_MESG = M_MESG_I;\n assign M_VALID = M_VALID_I;\n assign M_READY_I = M_READY;\n \n end\n endgenerate\n\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_comparator.v", "content": "// -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n// Optimized COMPARATOR with carry logic.\n//\n// Verilog-standard: Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n// \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\nmodule mig_7series_v4_0_ddr_comparator #\n (\n parameter C_FAMILY = \"virtex6\", \n // FPGA Family. Current version: virtex6 or spartan6.\n parameter integer C_DATA_WIDTH = 4\n // Data width for comparator.\n )\n (\n input wire CIN,\n input wire [C_DATA_WIDTH-1:0] A,\n input wire [C_DATA_WIDTH-1:0] B,\n output wire COUT\n );\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Variables for generating parameter controlled instances.\n /////////////////////////////////////////////////////////////////////////////\n \n // Generate variable for bit vector.\n genvar bit_cnt;\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Local params\n /////////////////////////////////////////////////////////////////////////////\n \n // Bits per LUT for this architecture.\n localparam integer C_BITS_PER_LUT = 3;\n \n // Constants for packing levels.\n localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;\n \n // \n localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :\n C_DATA_WIDTH;\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Functions\n /////////////////////////////////////////////////////////////////////////////\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Internal signals\n /////////////////////////////////////////////////////////////////////////////\n \n wire [C_FIX_DATA_WIDTH-1:0] a_local;\n wire [C_FIX_DATA_WIDTH-1:0] b_local;\n wire [C_NUM_LUT-1:0] sel;\n wire [C_NUM_LUT:0] carry_local;\n \n \n /////////////////////////////////////////////////////////////////////////////\n // \n /////////////////////////////////////////////////////////////////////////////\n \n generate\n // Assign input to local vectors.\n assign carry_local[0] = CIN;\n \n // Extend input data to fit.\n if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA\n assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n end else begin : NO_EXTENDED_DATA\n assign a_local = A;\n assign b_local = B;\n end\n \n // Instantiate one carry and per level.\n for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL\n // Create the local select signal\n assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == \n b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] );\n \n // Instantiate each LUT level.\n mig_7series_v4_0_ddr_carry_and # \n (\n .C_FAMILY(C_FAMILY)\n ) compare_inst \n (\n .COUT (carry_local[bit_cnt+1]),\n .CIN (carry_local[bit_cnt]),\n .S (sel[bit_cnt])\n ); \n \n end // end for bit_cnt\n \n // Assign output from local vector.\n assign COUT = carry_local[C_NUM_LUT];\n \n endgenerate\n \n \nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_comparator_sel.v", "content": "// -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n// Optimized COMPARATOR with carry logic.\n//\n// Verilog-standard: Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n// \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\nmodule mig_7series_v4_0_ddr_comparator_sel #\n (\n parameter C_FAMILY = \"virtex6\", \n // FPGA Family. Current version: virtex6 or spartan6.\n parameter integer C_DATA_WIDTH = 4\n // Data width for comparator.\n )\n (\n input wire CIN,\n input wire S,\n input wire [C_DATA_WIDTH-1:0] A,\n input wire [C_DATA_WIDTH-1:0] B,\n input wire [C_DATA_WIDTH-1:0] V,\n output wire COUT\n );\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Variables for generating parameter controlled instances.\n /////////////////////////////////////////////////////////////////////////////\n \n // Generate variable for bit vector.\n genvar bit_cnt;\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Local params\n /////////////////////////////////////////////////////////////////////////////\n \n // Bits per LUT for this architecture.\n localparam integer C_BITS_PER_LUT = 1;\n \n // Constants for packing levels.\n localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;\n \n // \n localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :\n C_DATA_WIDTH;\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Functions\n /////////////////////////////////////////////////////////////////////////////\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Internal signals\n /////////////////////////////////////////////////////////////////////////////\n \n wire [C_FIX_DATA_WIDTH-1:0] a_local;\n wire [C_FIX_DATA_WIDTH-1:0] b_local;\n wire [C_FIX_DATA_WIDTH-1:0] v_local;\n wire [C_NUM_LUT-1:0] sel;\n wire [C_NUM_LUT:0] carry_local;\n \n \n /////////////////////////////////////////////////////////////////////////////\n // \n /////////////////////////////////////////////////////////////////////////////\n \n generate\n // Assign input to local vectors.\n assign carry_local[0] = CIN;\n \n // Extend input data to fit.\n if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA\n assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n end else begin : NO_EXTENDED_DATA\n assign a_local = A;\n assign b_local = B;\n assign v_local = V;\n end\n \n // Instantiate one carry and per level.\n for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL\n // Create the local select signal\n assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == \n v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |\n ( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == \n v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );\n \n // Instantiate each LUT level.\n mig_7series_v4_0_ddr_carry_and # \n (\n .C_FAMILY(C_FAMILY)\n ) compare_inst \n (\n .COUT (carry_local[bit_cnt+1]),\n .CIN (carry_local[bit_cnt]),\n .S (sel[bit_cnt])\n ); \n \n end // end for bit_cnt\n \n // Assign output from local vector.\n assign COUT = carry_local[C_NUM_LUT];\n \n endgenerate\n \n \nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_comparator_sel_static.v", "content": "// -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: \n// Optimized COMPARATOR (against constant) with carry logic.\n//\n// Verilog-standard: Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n// \n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\nmodule mig_7series_v4_0_ddr_comparator_sel_static #\n (\n parameter C_FAMILY = \"virtex6\", \n // FPGA Family. Current version: virtex6 or spartan6.\n parameter C_VALUE = 4'b0,\n // Static value to compare against.\n parameter integer C_DATA_WIDTH = 4\n // Data width for comparator.\n )\n (\n input wire CIN,\n input wire S,\n input wire [C_DATA_WIDTH-1:0] A,\n input wire [C_DATA_WIDTH-1:0] B,\n output wire COUT\n );\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Variables for generating parameter controlled instances.\n /////////////////////////////////////////////////////////////////////////////\n \n // Generate variable for bit vector.\n genvar bit_cnt;\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Local params\n /////////////////////////////////////////////////////////////////////////////\n \n // Bits per LUT for this architecture.\n localparam integer C_BITS_PER_LUT = 2;\n \n // Constants for packing levels.\n localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;\n \n // \n localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :\n C_DATA_WIDTH;\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Functions\n /////////////////////////////////////////////////////////////////////////////\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Internal signals\n /////////////////////////////////////////////////////////////////////////////\n \n wire [C_FIX_DATA_WIDTH-1:0] a_local;\n wire [C_FIX_DATA_WIDTH-1:0] b_local;\n wire [C_FIX_DATA_WIDTH-1:0] v_local;\n wire [C_NUM_LUT-1:0] sel;\n wire [C_NUM_LUT:0] carry_local;\n \n \n /////////////////////////////////////////////////////////////////////////////\n // \n /////////////////////////////////////////////////////////////////////////////\n \n generate\n // Assign input to local vectors.\n assign carry_local[0] = CIN;\n \n // Extend input data to fit.\n if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA\n assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n assign v_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};\n end else begin : NO_EXTENDED_DATA\n assign a_local = A;\n assign b_local = B;\n assign v_local = C_VALUE;\n end\n \n // Instantiate one carry and per level.\n for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL\n // Create the local select signal\n assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == \n v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |\n ( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] == \n v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );\n \n // Instantiate each LUT level.\n mig_7series_v4_0_ddr_carry_and # \n (\n .C_FAMILY(C_FAMILY)\n ) compare_inst \n (\n .COUT (carry_local[bit_cnt+1]),\n .CIN (carry_local[bit_cnt]),\n .S (sel[bit_cnt])\n ); \n \n end // end for bit_cnt\n \n // Assign output from local vector.\n assign COUT = carry_local[C_NUM_LUT];\n \n endgenerate\n \n \nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_r_upsizer.v", "content": "// -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: Read Data Response Up-Sizer\n// Extract SI-side Data from packed and unpacked MI-side data.\n//\n// Verilog-standard: Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n// ddr_r_upsizer\n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\nmodule mig_7series_v4_0_ddr_r_upsizer #\n (\n parameter C_FAMILY = \"rtl\", \n // FPGA Family. Current version: virtex6 or spartan6.\n parameter integer C_AXI_ID_WIDTH = 4, \n // Width of all ID signals on SI and MI side of converter.\n // Range: >= 1.\n parameter C_S_AXI_DATA_WIDTH = 32'h00000020, \n // Width of S_AXI_WDATA and S_AXI_RDATA.\n // Format: Bit32; \n // Range: 'h00000020, 'h00000040, 'h00000080, 'h00000100.\n parameter C_M_AXI_DATA_WIDTH = 32'h00000040, \n // Width of M_AXI_WDATA and M_AXI_RDATA.\n // Assume greater than or equal to C_S_AXI_DATA_WIDTH.\n // Format: Bit32;\n // Range: 'h00000020, 'h00000040, 'h00000080, 'h00000100.\n parameter integer C_S_AXI_REGISTER = 0,\n // Clock output data.\n // Range: 0, 1\n parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,\n // 1 = Propagate all USER signals, 0 = Dont propagate.\n parameter integer C_AXI_RUSER_WIDTH = 1,\n // Width of RUSER signals. \n // Range: >= 1.\n parameter integer C_PACKING_LEVEL = 1,\n // 0 = Never pack (expander only); packing logic is omitted.\n // 1 = Pack only when CACHE[1] (Modifiable) is high.\n // 2 = Always pack, regardless of sub-size transaction or Modifiable bit.\n // (Required when used as helper-core by mem-con.)\n parameter integer C_SUPPORT_BURSTS = 1,\n // Disabled when all connected masters and slaves are AxiLite,\n // allowing logic to be simplified.\n parameter integer C_S_AXI_BYTES_LOG = 3,\n // Log2 of number of 32bit word on SI-side.\n parameter integer C_M_AXI_BYTES_LOG = 3,\n // Log2 of number of 32bit word on MI-side.\n parameter integer C_RATIO = 2,\n // Up-Sizing ratio for data.\n parameter integer C_RATIO_LOG = 1\n // Log2 of Up-Sizing ratio for data.\n )\n (\n // Global Signals\n input wire ARESET,\n input wire ACLK,\n\n // Command Interface\n input wire cmd_valid,\n input wire cmd_fix,\n input wire cmd_modified,\n input wire cmd_complete_wrap,\n input wire cmd_packed_wrap,\n input wire [C_M_AXI_BYTES_LOG-1:0] cmd_first_word, \n input wire [C_M_AXI_BYTES_LOG-1:0] cmd_next_word,\n input wire [C_M_AXI_BYTES_LOG-1:0] cmd_last_word,\n input wire [C_M_AXI_BYTES_LOG-1:0] cmd_offset,\n input wire [C_M_AXI_BYTES_LOG-1:0] cmd_mask,\n input wire [C_S_AXI_BYTES_LOG:0] cmd_step,\n input wire [8-1:0] cmd_length,\n output wire cmd_ready,\n \n // Slave Interface Read Data Ports\n output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,\n output wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,\n output wire [2-1:0] S_AXI_RRESP,\n output wire S_AXI_RLAST,\n output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,\n output wire S_AXI_RVALID,\n input wire S_AXI_RREADY,\n\n // Master Interface Read Data Ports\n input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,\n input wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,\n input wire [2-1:0] M_AXI_RRESP,\n input wire M_AXI_RLAST,\n input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,\n input wire M_AXI_RVALID,\n output wire M_AXI_RREADY\n );\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Variables for generating parameter controlled instances.\n /////////////////////////////////////////////////////////////////////////////\n \n genvar bit_cnt;\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Local params\n /////////////////////////////////////////////////////////////////////////////\n \n // Constants for packing levels.\n localparam integer C_NEVER_PACK = 0;\n localparam integer C_DEFAULT_PACK = 1;\n localparam integer C_ALWAYS_PACK = 2;\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Functions\n /////////////////////////////////////////////////////////////////////////////\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Internal signals\n /////////////////////////////////////////////////////////////////////////////\n \n // Sub-word handling.\n wire sel_first_word;\n reg first_word;\n reg [C_M_AXI_BYTES_LOG-1:0] current_word_1;\n reg [C_M_AXI_BYTES_LOG-1:0] current_word_cmb;\n wire [C_M_AXI_BYTES_LOG-1:0] current_word;\n wire [C_M_AXI_BYTES_LOG-1:0] current_word_adjusted;\n wire last_beat;\n wire last_word;\n wire [C_M_AXI_BYTES_LOG-1:0] cmd_step_i;\n \n // Sub-word handling for the next cycle.\n wire [C_M_AXI_BYTES_LOG-1:0] pre_next_word_i;\n wire [C_M_AXI_BYTES_LOG-1:0] pre_next_word;\n reg [C_M_AXI_BYTES_LOG-1:0] pre_next_word_1;\n wire [C_M_AXI_BYTES_LOG-1:0] next_word_i;\n wire [C_M_AXI_BYTES_LOG-1:0] next_word;\n \n // Burst length handling.\n wire first_mi_word;\n wire [8-1:0] length_counter_1;\n reg [8-1:0] length_counter;\n wire [8-1:0] next_length_counter;\n \n // Handle wrap buffering.\n wire store_in_wrap_buffer;\n reg use_wrap_buffer;\n reg wrap_buffer_available;\n reg [C_AXI_ID_WIDTH-1:0] rid_wrap_buffer;\n reg [2-1:0] rresp_wrap_buffer;\n reg [C_AXI_RUSER_WIDTH-1:0] ruser_wrap_buffer;\n \n // Throttling help signals.\n wire next_word_wrap;\n wire word_complete_next_wrap;\n wire word_complete_next_wrap_ready;\n wire word_complete_next_wrap_pop;\n wire word_complete_last_word;\n wire word_complete_rest;\n wire word_complete_rest_ready;\n wire word_complete_rest_pop;\n wire word_completed;\n wire cmd_ready_i;\n wire pop_si_data;\n wire pop_mi_data;\n wire si_stalling;\n \n // Internal signals for MI-side.\n reg [C_M_AXI_DATA_WIDTH-1:0] M_AXI_RDATA_I;\n wire M_AXI_RLAST_I;\n wire M_AXI_RVALID_I;\n wire M_AXI_RREADY_I;\n \n // Internal signals for SI-side.\n wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID_I;\n wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA_I;\n wire [2-1:0] S_AXI_RRESP_I;\n wire S_AXI_RLAST_I;\n wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER_I;\n wire S_AXI_RVALID_I;\n wire S_AXI_RREADY_I;\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Handle interface handshaking:\n //\n // Determine if a MI side word has been completely used. For FIX transactions\n // the MI-side word is used to extract a single data word. This is also true\n // for for an upsizer in Expander mode (Never Pack). Unmodified burst also \n // only use the MI word to extract a single SI-side word (although with \n // different offsets).\n // Otherwise is the MI-side word considered to be used when last SI-side beat\n // has been extracted or when the last (most significant) SI-side word has \n // been extracted from ti MI word.\n //\n // Data on the SI-side is available when data is being taken from MI-side or\n // from wrap buffer.\n //\n // The command is popped from the command queue once the last beat on the \n // SI-side has been ackowledged.\n //\n /////////////////////////////////////////////////////////////////////////////\n \n generate\n if ( C_RATIO_LOG > 1 ) begin : USE_LARGE_UPSIZING\n assign cmd_step_i = {{C_RATIO_LOG-1{1'b0}}, cmd_step};\n end else begin : NO_LARGE_UPSIZING\n assign cmd_step_i = cmd_step;\n end\n endgenerate\n \n generate\n if ( C_FAMILY == \"rtl\" || ( C_SUPPORT_BURSTS == 0 ) || \n ( C_PACKING_LEVEL == C_NEVER_PACK ) ) begin : USE_RTL_WORD_COMPLETED\n // Detect when MI-side word is completely used.\n assign word_completed = cmd_valid & \n ( ( cmd_fix ) |\n ( ~cmd_fix & ~cmd_complete_wrap & next_word == {C_M_AXI_BYTES_LOG{1'b0}} ) | \n ( ~cmd_fix & last_word & ~use_wrap_buffer ) | \n ( ~cmd_modified & ( C_PACKING_LEVEL == C_DEFAULT_PACK ) ) |\n ( C_PACKING_LEVEL == C_NEVER_PACK ) |\n ( C_SUPPORT_BURSTS == 0 ) );\n \n // RTL equivalent of optimized partial extressions (address wrap for next word).\n assign word_complete_next_wrap = ( ~cmd_fix & ~cmd_complete_wrap & next_word == {C_M_AXI_BYTES_LOG{1'b0}} ) | \n ( C_PACKING_LEVEL == C_NEVER_PACK ) |\n ( C_SUPPORT_BURSTS == 0 );\n assign word_complete_next_wrap_ready = word_complete_next_wrap & M_AXI_RVALID_I & ~si_stalling;\n assign word_complete_next_wrap_pop = word_complete_next_wrap_ready & M_AXI_RVALID_I;\n \n // RTL equivalent of optimized partial extressions (last word and the remaining).\n assign word_complete_last_word = last_word & (~cmd_fix & ~use_wrap_buffer);\n assign word_complete_rest = word_complete_last_word | cmd_fix | \n ( ~cmd_modified & ( C_PACKING_LEVEL == C_DEFAULT_PACK ) );\n assign word_complete_rest_ready = word_complete_rest & M_AXI_RVALID_I & ~si_stalling;\n assign word_complete_rest_pop = word_complete_rest_ready & M_AXI_RVALID_I;\n \n end else begin : USE_FPGA_WORD_COMPLETED\n \n wire sel_word_complete_next_wrap;\n wire sel_word_completed;\n wire sel_m_axi_rready;\n wire sel_word_complete_last_word;\n wire sel_word_complete_rest;\n \n // Optimize next word address wrap branch of expression.\n //\n mig_7series_v4_0_ddr_comparator_sel_static #\n (\n .C_FAMILY(C_FAMILY),\n .C_VALUE({C_M_AXI_BYTES_LOG{1'b0}}),\n .C_DATA_WIDTH(C_M_AXI_BYTES_LOG)\n ) next_word_wrap_inst\n (\n .CIN(1'b1),\n .S(sel_first_word),\n .A(pre_next_word_1),\n .B(cmd_next_word),\n .COUT(next_word_wrap)\n );\n \n assign sel_word_complete_next_wrap = ~cmd_fix & ~cmd_complete_wrap;\n \n mig_7series_v4_0_ddr_carry_and #\n (\n .C_FAMILY(C_FAMILY)\n ) word_complete_next_wrap_inst\n (\n .CIN(next_word_wrap),\n .S(sel_word_complete_next_wrap),\n .COUT(word_complete_next_wrap)\n );\n \n assign sel_m_axi_rready = cmd_valid & S_AXI_RREADY_I;\n \n mig_7series_v4_0_ddr_carry_and #\n (\n .C_FAMILY(C_FAMILY)\n ) word_complete_next_wrap_ready_inst\n (\n .CIN(word_complete_next_wrap),\n .S(sel_m_axi_rready),\n .COUT(word_complete_next_wrap_ready)\n );\n \n mig_7series_v4_0_ddr_carry_and #\n (\n .C_FAMILY(C_FAMILY)\n ) word_complete_next_wrap_pop_inst\n (\n .CIN(word_complete_next_wrap_ready),\n .S(M_AXI_RVALID_I),\n .COUT(word_complete_next_wrap_pop)\n );\n \n // Optimize last word and \"rest\" branch of expression.\n //\n assign sel_word_complete_last_word = ~cmd_fix & ~use_wrap_buffer;\n \n mig_7series_v4_0_ddr_carry_and #\n (\n .C_FAMILY(C_FAMILY)\n ) word_complete_last_word_inst\n (\n .CIN(last_word),\n .S(sel_word_complete_last_word),\n .COUT(word_complete_last_word)\n );\n \n assign sel_word_complete_rest = cmd_fix | ( ~cmd_modified & ( C_PACKING_LEVEL == C_DEFAULT_PACK ) );\n \n mig_7series_v4_0_ddr_carry_or #\n (\n .C_FAMILY(C_FAMILY)\n ) word_complete_rest_inst\n (\n .CIN(word_complete_last_word),\n .S(sel_word_complete_rest),\n .COUT(word_complete_rest)\n );\n \n mig_7series_v4_0_ddr_carry_and #\n (\n .C_FAMILY(C_FAMILY)\n ) word_complete_rest_ready_inst\n (\n .CIN(word_complete_rest),\n .S(sel_m_axi_rready),\n .COUT(word_complete_rest_ready)\n );\n \n mig_7series_v4_0_ddr_carry_and #\n (\n .C_FAMILY(C_FAMILY)\n ) word_complete_rest_pop_inst\n (\n .CIN(word_complete_rest_ready),\n .S(M_AXI_RVALID_I),\n .COUT(word_complete_rest_pop)\n );\n \n // Combine the two branches to generate the full signal.\n assign word_completed = word_complete_next_wrap | word_complete_rest;\n \n end\n endgenerate\n \n // Only propagate Valid when there is command information available.\n assign M_AXI_RVALID_I = M_AXI_RVALID & cmd_valid;\n \n generate\n if ( C_FAMILY == \"rtl\" ) begin : USE_RTL_CTRL\n // Pop word from MI-side.\n assign M_AXI_RREADY_I = word_completed & S_AXI_RREADY_I;\n \n // Get MI-side data.\n assign pop_mi_data = M_AXI_RVALID_I & M_AXI_RREADY_I;\n \n // Signal that the command is done (so that it can be poped from command queue).\n assign cmd_ready_i = cmd_valid & S_AXI_RLAST_I & pop_si_data;\n \n end else begin : USE_FPGA_CTRL\n wire sel_cmd_ready;\n \n assign M_AXI_RREADY_I = word_complete_next_wrap_ready | word_complete_rest_ready;\n \n assign pop_mi_data = word_complete_next_wrap_pop | word_complete_rest_pop;\n \n assign sel_cmd_ready = cmd_valid & pop_si_data;\n \n mig_7series_v4_0_ddr_carry_latch_and #\n (\n .C_FAMILY(C_FAMILY)\n ) cmd_ready_inst\n (\n .CIN(S_AXI_RLAST_I),\n .I(sel_cmd_ready),\n .O(cmd_ready_i)\n );\n \n end\n endgenerate\n \n // Indicate when there is data available @ SI-side.\n assign S_AXI_RVALID_I = ( M_AXI_RVALID_I | use_wrap_buffer );\n \n // Get SI-side data.\n assign pop_si_data = S_AXI_RVALID_I & S_AXI_RREADY_I;\n \n // Assign external signals.\n assign M_AXI_RREADY = M_AXI_RREADY_I;\n assign cmd_ready = cmd_ready_i;\n \n // Detect when SI-side is stalling.\n assign si_stalling = S_AXI_RVALID_I & ~S_AXI_RREADY_I;\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Keep track of data extraction:\n // \n // Current address is taken form the command buffer for the first data beat\n // to handle unaligned Read transactions. After this is the extraction \n // address usually calculated from this point.\n // FIX transactions uses the same word address for all data beats. \n // \n // Next word address is generated as current word plus the current step \n // size, with masking to facilitate sub-sized wraping. The Mask is all ones\n // for normal wraping, and less when sub-sized wraping is used.\n // \n // The calculated word addresses (current and next) is offseted by the \n // current Offset. For sub-sized transaction the Offset points to the least \n // significant address of the included data beats. (The least significant \n // word is not necessarily the first data to be extracted, consider WRAP).\n // Offset is only used for sub-sized WRAP transcation that are Complete.\n // \n // First word is active during the first SI-side data beat.\n // \n // First MI is set while the entire first MI-side word is processed.\n //\n // The transaction length is taken from the command buffer combinatorialy\n // during the First MI cycle. For each used MI word it is decreased until \n // Last beat is reached.\n // \n // Last word is determined depending on the current command, i.e. modified \n // burst has to scale since multiple words could be packed into one MI-side\n // word.\n // Last word is 1:1 for:\n // FIX, when burst support is disabled or unmodified for Normal Pack.\n // Last word is scaled for all other transactions.\n //\n /////////////////////////////////////////////////////////////////////////////\n \n // Select if the offset comes from command queue directly or \n // from a counter while when extracting multiple SI words per MI word\n assign sel_first_word = first_word | cmd_fix;\n assign current_word = sel_first_word ? cmd_first_word : \n current_word_1;\n \n generate\n if ( C_FAMILY == \"rtl\" ) begin : USE_RTL_NEXT_WORD\n \n // Calculate next word.\n assign pre_next_word_i = ( next_word_i + cmd_step_i );\n \n // Calculate next word.\n assign next_word_i = sel_first_word ? cmd_next_word : \n pre_next_word_1;\n \n end else begin : USE_FPGA_NEXT_WORD\n wire [C_M_AXI_BYTES_LOG-1:0] next_sel;\n wire [C_M_AXI_BYTES_LOG:0] next_carry_local;\n\n // Assign input to local vectors.\n assign next_carry_local[0] = 1'b0;\n \n // Instantiate one carry and per level.\n for (bit_cnt = 0; bit_cnt < C_M_AXI_BYTES_LOG ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL\n \n LUT6_2 # (\n .INIT(64'h5A5A_5A66_F0F0_F0CC) \n ) LUT6_2_inst (\n .O6(next_sel[bit_cnt]), // 6/5-LUT output (1-bit)\n .O5(next_word_i[bit_cnt]), // 5-LUT output (1-bit)\n .I0(cmd_step_i[bit_cnt]), // LUT input (1-bit)\n .I1(pre_next_word_1[bit_cnt]), // LUT input (1-bit)\n .I2(cmd_next_word[bit_cnt]), // LUT input (1-bit)\n .I3(first_word), // LUT input (1-bit)\n .I4(cmd_fix), // LUT input (1-bit)\n .I5(1'b1) // LUT input (1-bit)\n );\n \n MUXCY next_carry_inst \n (\n .O (next_carry_local[bit_cnt+1]), \n .CI (next_carry_local[bit_cnt]), \n .DI (cmd_step_i[bit_cnt]), \n .S (next_sel[bit_cnt])\n ); \n \n XORCY next_xorcy_inst \n (\n .O(pre_next_word_i[bit_cnt]),\n .CI(next_carry_local[bit_cnt]),\n .LI(next_sel[bit_cnt])\n );\n \n end // end for bit_cnt\n \n end\n endgenerate\n \n // Calculate next word.\n assign next_word = next_word_i & cmd_mask;\n assign pre_next_word = pre_next_word_i & cmd_mask;\n \n // Calculate the word address with offset.\n assign current_word_adjusted = current_word | cmd_offset;\n \n // Prepare next word address.\n always @ (posedge ACLK) begin\n if (ARESET) begin\n first_word <= 1'b1;\n current_word_1 <= 'b0;\n pre_next_word_1 <= {C_M_AXI_BYTES_LOG{1'b0}};\n end else begin\n if ( pop_si_data ) begin\n if ( last_word ) begin\n // Prepare for next access.\n first_word <= 1'b1;\n end else begin\n first_word <= 1'b0;\n end\n \n current_word_1 <= next_word;\n pre_next_word_1 <= pre_next_word;\n end\n end\n end\n \n // Select command length or counted length.\n always @ *\n begin\n if ( first_mi_word )\n length_counter = cmd_length;\n else\n length_counter = length_counter_1;\n end\n \n // Calculate next length counter value.\n assign next_length_counter = length_counter - 1'b1;\n \n generate\n if ( C_FAMILY == \"rtl\" ) begin : USE_RTL_LENGTH\n reg [8-1:0] length_counter_q;\n reg first_mi_word_q;\n \n always @ (posedge ACLK) begin\n if (ARESET) begin\n first_mi_word_q <= 1'b1;\n length_counter_q <= 8'b0;\n end else begin\n if ( pop_mi_data ) begin\n if ( M_AXI_RLAST ) begin\n first_mi_word_q <= 1'b1;\n end else begin\n first_mi_word_q <= 1'b0;\n end\n \n length_counter_q <= next_length_counter;\n end\n end\n end\n \n assign first_mi_word = first_mi_word_q;\n assign length_counter_1 = length_counter_q;\n \n end else begin : USE_FPGA_LENGTH\n wire [8-1:0] length_counter_i;\n wire [8-1:0] length_sel;\n wire [8-1:0] length_di;\n wire [8:0] length_local_carry;\n \n // Assign input to local vectors.\n assign length_local_carry[0] = 1'b0;\n \n for (bit_cnt = 0; bit_cnt < 8 ; bit_cnt = bit_cnt + 1) begin : BIT_LANE\n\n LUT6_2 # (\n .INIT(64'h333C_555A_FFF0_FFF0) \n ) LUT6_2_inst (\n .O6(length_sel[bit_cnt]), // 6/5-LUT output (1-bit)\n .O5(length_di[bit_cnt]), // 5-LUT output (1-bit)\n .I0(length_counter_1[bit_cnt]), // LUT input (1-bit)\n .I1(cmd_length[bit_cnt]), // LUT input (1-bit)\n .I2(word_complete_next_wrap_pop), // LUT input (1-bit)\n .I3(word_complete_rest_pop), // LUT input (1-bit)\n .I4(first_mi_word), // LUT input (1-bit)\n .I5(1'b1) // LUT input (1-bit)\n );\n \n MUXCY and_inst \n (\n .O (length_local_carry[bit_cnt+1]), \n .CI (length_local_carry[bit_cnt]), \n .DI (length_di[bit_cnt]), \n .S (length_sel[bit_cnt])\n ); \n \n XORCY xorcy_inst \n (\n .O(length_counter_i[bit_cnt]),\n .CI(length_local_carry[bit_cnt]),\n .LI(length_sel[bit_cnt])\n );\n \n FDRE #(\n .INIT(1'b0) // Initial value of register (1'b0 or 1'b1)\n ) FDRE_inst (\n .Q(length_counter_1[bit_cnt]), // Data output\n .C(ACLK), // Clock input\n .CE(1'b1), // Clock enable input\n .R(ARESET), // Synchronous reset input\n .D(length_counter_i[bit_cnt]) // Data input\n );\n end // end for bit_cnt\n \n wire first_mi_word_i;\n \n LUT6 # (\n .INIT(64'hAAAC_AAAC_AAAC_AAAC) \n ) LUT6_cnt_inst (\n .O(first_mi_word_i), // 6-LUT output (1-bit)\n .I0(M_AXI_RLAST), // LUT input (1-bit)\n .I1(first_mi_word), // LUT input (1-bit)\n .I2(word_complete_next_wrap_pop), // LUT input (1-bit)\n .I3(word_complete_rest_pop), // LUT input (1-bit)\n .I4(1'b1), // LUT input (1-bit)\n .I5(1'b1) // LUT input (1-bit)\n );\n \n FDSE #(\n .INIT(1'b1) // Initial value of register (1'b0 or 1'b1)\n ) FDRE_inst (\n .Q(first_mi_word), // Data output\n .C(ACLK), // Clock input\n .CE(1'b1), // Clock enable input\n .S(ARESET), // Synchronous reset input\n .D(first_mi_word_i) // Data input\n );\n \n end\n endgenerate\n \n generate\n if ( C_FAMILY == \"rtl\" || C_SUPPORT_BURSTS == 0 ) begin : USE_RTL_LAST_WORD\n // Detect last beat in a burst.\n assign last_beat = ( length_counter == 8'b0 );\n \n // Determine if this last word that shall be extracted from this MI-side word.\n assign last_word = ( last_beat & ( current_word == cmd_last_word ) & ~wrap_buffer_available & ( current_word == cmd_last_word ) ) |\n ( use_wrap_buffer & ( current_word == cmd_last_word ) ) |\n ( last_beat & ( current_word == cmd_last_word ) & ( C_PACKING_LEVEL == C_NEVER_PACK ) ) |\n ( C_SUPPORT_BURSTS == 0 );\n \n end else begin : USE_FPGA_LAST_WORD\n \n wire sel_last_word;\n wire last_beat_ii;\n \n \n mig_7series_v4_0_ddr_comparator_sel_static #\n (\n .C_FAMILY(C_FAMILY),\n .C_VALUE(8'b0),\n .C_DATA_WIDTH(8)\n ) last_beat_inst\n (\n .CIN(1'b1),\n .S(first_mi_word),\n .A(length_counter_1),\n .B(cmd_length),\n .COUT(last_beat)\n );\n \n if ( C_PACKING_LEVEL != C_NEVER_PACK ) begin : USE_FPGA_PACK\n // \n //\n wire sel_last_beat;\n wire last_beat_i;\n \n assign sel_last_beat = ~wrap_buffer_available;\n \n mig_7series_v4_0_ddr_carry_and #\n (\n .C_FAMILY(C_FAMILY)\n ) last_beat_inst_1\n (\n .CIN(last_beat),\n .S(sel_last_beat),\n .COUT(last_beat_i)\n );\n \n mig_7series_v4_0_ddr_carry_or #\n (\n .C_FAMILY(C_FAMILY)\n ) last_beat_wrap_inst\n (\n .CIN(last_beat_i),\n .S(use_wrap_buffer),\n .COUT(last_beat_ii)\n );\n \n end else begin : NO_PACK\n assign last_beat_ii = last_beat;\n \n end\n \n mig_7series_v4_0_ddr_comparator_sel #\n (\n .C_FAMILY(C_FAMILY),\n .C_DATA_WIDTH(C_M_AXI_BYTES_LOG)\n ) last_beat_curr_word_inst\n (\n .CIN(last_beat_ii),\n .S(sel_first_word),\n .A(current_word_1),\n .B(cmd_first_word),\n .V(cmd_last_word),\n .COUT(last_word)\n );\n \n end\n endgenerate\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Handle wrap buffer:\n // \n // The wrap buffer is used to move data around in an unaligned WRAP \n // transaction. The requested read address has been rounded down, meaning \n // that parts of the first MI-side data beat has to be delayed for later use.\n // The extraction starts at the origian unaligned address, the remaining data\n // is stored in the wrap buffer to be extracted after the last MI-side data \n // beat has been fully processed.\n // For example: an 32bit to 64bit read upsizing @ 0x4 will request a MI-side\n // read WRAP transaction 0x0. The 0x4 data word is used at once and the 0x0 \n // word is delayed to be used after all data in the last MI-side beat has \n // arrived.\n // \n /////////////////////////////////////////////////////////////////////////////\n \n // Save data to be able to perform buffer wraping.\n assign store_in_wrap_buffer = M_AXI_RVALID_I & cmd_packed_wrap & first_mi_word & ~use_wrap_buffer;\n \n // Mark that there are data available for wrap buffering.\n always @ (posedge ACLK) begin\n if (ARESET) begin\n wrap_buffer_available <= 1'b0;\n end else begin\n if ( store_in_wrap_buffer & word_completed & pop_si_data ) begin\n wrap_buffer_available <= 1'b1;\n end else if ( last_beat & word_completed & pop_si_data ) begin\n wrap_buffer_available <= 1'b0;\n end\n end\n end\n \n // Start using the wrap buffer.\n always @ (posedge ACLK) begin\n if (ARESET) begin\n use_wrap_buffer <= 1'b0;\n end else begin\n if ( wrap_buffer_available & last_beat & word_completed & pop_si_data ) begin\n use_wrap_buffer <= 1'b1;\n end else if ( cmd_ready_i ) begin\n use_wrap_buffer <= 1'b0;\n end\n end\n end\n \n // Store data in wrap buffer.\n always @ (posedge ACLK) begin\n if (ARESET) begin\n M_AXI_RDATA_I <= {C_M_AXI_DATA_WIDTH{1'b0}};\n rid_wrap_buffer <= {C_AXI_ID_WIDTH{1'b0}};\n rresp_wrap_buffer <= 2'b0;\n ruser_wrap_buffer <= {C_AXI_ID_WIDTH{1'b0}};\n end else begin\n if ( store_in_wrap_buffer ) begin\n M_AXI_RDATA_I <= M_AXI_RDATA;\n rid_wrap_buffer <= M_AXI_RID;\n rresp_wrap_buffer <= M_AXI_RRESP;\n ruser_wrap_buffer <= M_AXI_RUSER;\n end\n end\n end\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Select the SI-side word to read.\n //\n // Everything must be multiplexed since the next transfer can be arriving \n // with a different set of signals while the wrap buffer is still being \n // processed for the current transaction.\n // \n // Non modifiable word has a 1:1 ratio, i.e. only one SI-side word is \n // generated per MI-side word.\n // Data is taken either directly from the incomming MI-side data or the \n // wrap buffer (for packed WRAP).\n //\n // Last need special handling since it is the last SI-side word generated \n // from the MI-side word.\n //\n /////////////////////////////////////////////////////////////////////////////\n \n // ID, RESP and USER has to be multiplexed.\n assign S_AXI_RID_I = ( use_wrap_buffer & ( C_SUPPORT_BURSTS == 1 ) ) ? \n rid_wrap_buffer :\n M_AXI_RID;\n assign S_AXI_RRESP_I = ( use_wrap_buffer & ( C_SUPPORT_BURSTS == 1 ) ) ? \n rresp_wrap_buffer :\n M_AXI_RRESP;\n assign S_AXI_RUSER_I = ( C_AXI_SUPPORTS_USER_SIGNALS ) ? \n ( use_wrap_buffer & ( C_SUPPORT_BURSTS == 1 ) ) ? \n ruser_wrap_buffer :\n M_AXI_RUSER :\n {C_AXI_RUSER_WIDTH{1'b0}};\n \n // Data has to be multiplexed.\n generate\n if ( C_RATIO == 1 ) begin : SINGLE_WORD\n assign S_AXI_RDATA_I = ( use_wrap_buffer & ( C_SUPPORT_BURSTS == 1 ) ) ? \n M_AXI_RDATA_I :\n M_AXI_RDATA;\n end else begin : MULTIPLE_WORD\n // Get the ratio bits (MI-side words vs SI-side words).\n wire [C_RATIO_LOG-1:0] current_index;\n assign current_index = current_word_adjusted[C_M_AXI_BYTES_LOG-C_RATIO_LOG +: C_RATIO_LOG];\n \n assign S_AXI_RDATA_I = ( use_wrap_buffer & ( C_SUPPORT_BURSTS == 1 ) ) ? \n M_AXI_RDATA_I[current_index * C_S_AXI_DATA_WIDTH +: C_S_AXI_DATA_WIDTH] :\n M_AXI_RDATA[current_index * C_S_AXI_DATA_WIDTH +: C_S_AXI_DATA_WIDTH];\n end\n endgenerate\n \n // Generate the true last flag including \"keep\" while using wrap buffer.\n assign M_AXI_RLAST_I = ( M_AXI_RLAST | use_wrap_buffer );\n \n // Handle last flag, i.e. set for SI-side last word.\n assign S_AXI_RLAST_I = last_word;\n \n \n /////////////////////////////////////////////////////////////////////////////\n // SI-side output handling\n /////////////////////////////////////////////////////////////////////////////\n \n generate\n if ( C_S_AXI_REGISTER ) begin : USE_REGISTER\n reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID_q;\n reg [C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA_q;\n reg [2-1:0] S_AXI_RRESP_q;\n reg S_AXI_RLAST_q;\n reg [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER_q;\n reg S_AXI_RVALID_q;\n reg S_AXI_RREADY_q;\n \n // Register SI-side Data.\n always @ (posedge ACLK) begin\n if (ARESET) begin\n S_AXI_RID_q <= {C_AXI_ID_WIDTH{1'b0}};\n S_AXI_RDATA_q <= {C_S_AXI_DATA_WIDTH{1'b0}};\n S_AXI_RRESP_q <= 2'b0;\n S_AXI_RLAST_q <= 1'b0;\n S_AXI_RUSER_q <= {C_AXI_RUSER_WIDTH{1'b0}};\n S_AXI_RVALID_q <= 1'b0;\n end else begin\n if ( S_AXI_RREADY_I ) begin\n S_AXI_RID_q <= S_AXI_RID_I;\n S_AXI_RDATA_q <= S_AXI_RDATA_I;\n S_AXI_RRESP_q <= S_AXI_RRESP_I;\n S_AXI_RLAST_q <= S_AXI_RLAST_I;\n S_AXI_RUSER_q <= S_AXI_RUSER_I;\n S_AXI_RVALID_q <= S_AXI_RVALID_I;\n end\n \n end\n end\n \n assign S_AXI_RID = S_AXI_RID_q;\n assign S_AXI_RDATA = S_AXI_RDATA_q;\n assign S_AXI_RRESP = S_AXI_RRESP_q;\n assign S_AXI_RLAST = S_AXI_RLAST_q;\n assign S_AXI_RUSER = S_AXI_RUSER_q;\n assign S_AXI_RVALID = S_AXI_RVALID_q;\n assign S_AXI_RREADY_I = ( S_AXI_RVALID_q & S_AXI_RREADY) | ~S_AXI_RVALID_q;\n \n end else begin : NO_REGISTER\n \n // Combinatorial SI-side Data.\n assign S_AXI_RREADY_I = S_AXI_RREADY;\n assign S_AXI_RVALID = S_AXI_RVALID_I;\n assign S_AXI_RID = S_AXI_RID_I;\n assign S_AXI_RDATA = S_AXI_RDATA_I;\n assign S_AXI_RRESP = S_AXI_RRESP_I;\n assign S_AXI_RLAST = S_AXI_RLAST_I;\n assign S_AXI_RUSER = S_AXI_RUSER_I;\n \n end\n endgenerate\n \n \nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series_v4_0_ddr_w_upsizer.v", "content": "// -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.\n// --\n// -- This file contains confidential and proprietary information\n// -- of Xilinx, Inc. and is protected under U.S. and \n// -- international copyright and other intellectual property\n// -- laws.\n// --\n// -- DISCLAIMER\n// -- This disclaimer is not a license and does not grant any\n// -- rights to the materials distributed herewith. Except as\n// -- otherwise provided in a valid license issued to you by\n// -- Xilinx, and to the maximum extent permitted by applicable\n// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// -- (2) Xilinx shall not be liable (whether in contract or tort,\n// -- including negligence, or under any other theory of\n// -- liability) for any loss or damage of any kind or nature\n// -- related to, arising under or in connection with these\n// -- materials, including for any direct, or any indirect,\n// -- special, incidental, or consequential loss or damage\n// -- (including loss of data, profits, goodwill, or any type of\n// -- loss or damage suffered as a result of any action brought\n// -- by a third party) even if such damage or loss was\n// -- reasonably foreseeable or Xilinx had been advised of the\n// -- possibility of the same.\n// --\n// -- CRITICAL APPLICATIONS\n// -- Xilinx products are not designed or intended to be fail-\n// -- safe, or for use in any application requiring fail-safe\n// -- performance, such as life-support or safety devices or\n// -- systems, Class III medical devices, nuclear facilities,\n// -- applications related to the deployment of airbags, or any\n// -- other applications that could lead to death, personal\n// -- injury, or severe property or environmental damage\n// -- (individually and collectively, \"Critical\n// -- Applications\"). Customer assumes the sole risk and\n// -- liability of any use of Xilinx products in Critical\n// -- Applications, subject only to applicable laws and\n// -- regulations governing limitations on product liability.\n// --\n// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// -- PART OF THIS FILE AT ALL TIMES.\n//-----------------------------------------------------------------------------\n//\n// Description: Write Data Up-Sizer\n// Mirror data for simple accesses.\n// Merge data for burst.\n//\n//\n// Verilog-standard: Verilog 2001\n//--------------------------------------------------------------------------\n//\n// Structure:\n// ddr_w_upsizer\n//\n//--------------------------------------------------------------------------\n`timescale 1ps/1ps\n\n\nmodule mig_7series_v4_0_ddr_w_upsizer #\n (\n parameter C_FAMILY = \"rtl\", \n // FPGA Family. Current version: virtex6 or spartan6.\n parameter C_S_AXI_DATA_WIDTH = 32'h00000020, \n // Width of S_AXI_WDATA and S_AXI_RDATA.\n // Format: Bit32; \n // Range: 'h00000020, 'h00000040, 'h00000080, 'h00000100.\n parameter C_M_AXI_DATA_WIDTH = 32'h00000040, \n // Width of M_AXI_WDATA and M_AXI_RDATA.\n // Assume greater than or equal to C_S_AXI_DATA_WIDTH.\n // Format: Bit32;\n // Range: 'h00000020, 'h00000040, 'h00000080, 'h00000100.\n parameter integer C_M_AXI_REGISTER = 0,\n // Clock output data.\n // Range: 0, 1\n parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,\n // 1 = Propagate all USER signals, 0 = Dont propagate.\n parameter integer C_AXI_WUSER_WIDTH = 1,\n // Width of WUSER signals. \n // Range: >= 1.\n parameter integer C_PACKING_LEVEL = 1,\n // 0 = Never pack (expander only); packing logic is omitted.\n // 1 = Pack only when CACHE[1] (Modifiable) is high.\n // 2 = Always pack, regardless of sub-size transaction or Modifiable bit.\n // (Required when used as helper-core by mem-con.)\n parameter integer C_SUPPORT_BURSTS = 1,\n // Disabled when all connected masters and slaves are AxiLite,\n // allowing logic to be simplified.\n parameter integer C_S_AXI_BYTES_LOG = 3,\n // Log2 of number of 32bit word on SI-side.\n parameter integer C_M_AXI_BYTES_LOG = 3,\n // Log2 of number of 32bit word on MI-side.\n parameter integer C_RATIO = 2,\n // Up-Sizing ratio for data.\n parameter integer C_RATIO_LOG = 1\n // Log2 of Up-Sizing ratio for data.\n )\n (\n // Global Signals\n input wire ARESET,\n input wire ACLK,\n\n // Command Interface\n input wire cmd_valid,\n input wire cmd_fix,\n input wire cmd_modified,\n input wire cmd_complete_wrap,\n input wire cmd_packed_wrap,\n input wire [C_M_AXI_BYTES_LOG-1:0] cmd_first_word, \n input wire [C_M_AXI_BYTES_LOG-1:0] cmd_next_word,\n input wire [C_M_AXI_BYTES_LOG-1:0] cmd_last_word,\n input wire [C_M_AXI_BYTES_LOG-1:0] cmd_offset,\n input wire [C_M_AXI_BYTES_LOG-1:0] cmd_mask,\n input wire [C_S_AXI_BYTES_LOG:0] cmd_step,\n input wire [8-1:0] cmd_length,\n output wire cmd_ready,\n \n // Slave Interface Write Data Ports\n input wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,\n input wire [C_S_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,\n input wire S_AXI_WLAST,\n input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,\n input wire S_AXI_WVALID,\n output wire S_AXI_WREADY,\n\n // Master Interface Write Data Ports\n output wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,\n output wire [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,\n output wire M_AXI_WLAST,\n output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,\n output wire M_AXI_WVALID,\n input wire M_AXI_WREADY\n );\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Variables for generating parameter controlled instances.\n /////////////////////////////////////////////////////////////////////////////\n \n // Generate variable for SI-side word lanes on MI-side.\n genvar word_cnt;\n \n // Generate variable for intra SI-word byte control (on MI-side) for always pack.\n genvar byte_cnt;\n genvar bit_cnt;\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Local params\n /////////////////////////////////////////////////////////////////////////////\n \n // Constants for packing levels.\n localparam integer C_NEVER_PACK = 0;\n localparam integer C_DEFAULT_PACK = 1;\n localparam integer C_ALWAYS_PACK = 2;\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Functions\n /////////////////////////////////////////////////////////////////////////////\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Internal signals\n /////////////////////////////////////////////////////////////////////////////\n\n // Sub-word handling.\n wire sel_first_word;\n wire first_word;\n wire [C_M_AXI_BYTES_LOG-1:0] current_word_1;\n wire [C_M_AXI_BYTES_LOG-1:0] current_word;\n wire [C_M_AXI_BYTES_LOG-1:0] current_word_adjusted;\n wire [C_RATIO-1:0] current_word_idx;\n wire last_beat;\n wire last_word;\n wire last_word_extra_carry;\n wire [C_M_AXI_BYTES_LOG-1:0] cmd_step_i;\n \n // Sub-word handling for the next cycle.\n wire [C_M_AXI_BYTES_LOG-1:0] pre_next_word_i;\n wire [C_M_AXI_BYTES_LOG-1:0] pre_next_word;\n wire [C_M_AXI_BYTES_LOG-1:0] pre_next_word_1;\n wire [C_M_AXI_BYTES_LOG-1:0] next_word_i;\n wire [C_M_AXI_BYTES_LOG-1:0] next_word;\n \n // Burst length handling.\n wire first_mi_word;\n wire [8-1:0] length_counter_1;\n reg [8-1:0] length_counter;\n wire [8-1:0] next_length_counter;\n \n // Handle wrap buffering.\n wire store_in_wrap_buffer_enabled;\n wire store_in_wrap_buffer;\n wire ARESET_or_store_in_wrap_buffer;\n wire use_wrap_buffer;\n reg wrap_buffer_available;\n \n // Detect start of MI word.\n wire first_si_in_mi;\n \n // Throttling help signals.\n wire word_complete_next_wrap;\n wire word_complete_next_wrap_qual;\n wire word_complete_next_wrap_valid;\n wire word_complete_next_wrap_pop;\n wire word_complete_next_wrap_last;\n wire word_complete_next_wrap_stall;\n wire word_complete_last_word;\n wire word_complete_rest;\n wire word_complete_rest_qual;\n wire word_complete_rest_valid;\n wire word_complete_rest_pop;\n wire word_complete_rest_last;\n wire word_complete_rest_stall;\n wire word_completed;\n wire word_completed_qualified;\n wire cmd_ready_i;\n wire pop_si_data;\n wire pop_mi_data_i;\n wire pop_mi_data;\n wire mi_stalling;\n \n // Internal SI side control signals.\n wire S_AXI_WREADY_I;\n \n // Internal packed write data.\n wire use_expander_data;\n wire [C_M_AXI_DATA_WIDTH/8-1:0] wdata_qualifier; // For FPGA only\n wire [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_qualifier; // For FPGA only\n wire [C_M_AXI_DATA_WIDTH/8-1:0] wrap_qualifier; // For FPGA only\n wire [C_M_AXI_DATA_WIDTH-1:0] wdata_buffer_i; // For FPGA only\n wire [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_buffer_i; // For FPGA only\n reg [C_M_AXI_DATA_WIDTH-1:0] wdata_buffer_q; // For RTL only\n reg [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_buffer_q; // For RTL only\n wire [C_M_AXI_DATA_WIDTH-1:0] wdata_buffer;\n wire [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_buffer;\n reg [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER_II;\n reg [C_M_AXI_DATA_WIDTH-1:0] wdata_last_word_mux;\n reg [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_last_word_mux;\n reg [C_M_AXI_DATA_WIDTH-1:0] wdata_wrap_buffer_cmb; // For FPGA only\n reg [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_wrap_buffer_cmb; // For FPGA only\n reg [C_M_AXI_DATA_WIDTH-1:0] wdata_wrap_buffer_q; // For RTL only\n reg [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_wrap_buffer_q; // For RTL only\n wire [C_M_AXI_DATA_WIDTH-1:0] wdata_wrap_buffer;\n wire [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_wrap_buffer;\n \n // Internal signals for MI-side.\n wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA_cmb; // For FPGA only\n wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA_q; // For FPGA only\n reg [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA_I;\n wire [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB_cmb; // For FPGA only\n wire [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB_q; // For FPGA only\n reg [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB_I;\n wire M_AXI_WLAST_I;\n reg [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER_I;\n wire M_AXI_WVALID_I;\n wire M_AXI_WREADY_I;\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Handle interface handshaking:\n //\n // Data on the MI-side is available when data a complete word has been \n // assembled from the data on SI-side (and potentially from any remainder in\n // the wrap buffer).\n // No data is produced on the MI-side when a unaligned packed wrap is \n // encountered, instead it stored in the wrap buffer to be used when the \n // last SI-side data beat is received.\n //\n // The command is popped from the command queue once the last beat on the \n // SI-side has been ackowledged.\n // \n // The packing process is stalled when a new MI-side is completed but not \n // yet acknowledged (by ready).\n //\n /////////////////////////////////////////////////////////////////////////////\n \n generate\n if ( C_RATIO_LOG > 1 ) begin : USE_LARGE_UPSIZING\n assign cmd_step_i = {{C_RATIO_LOG-1{1'b0}}, cmd_step};\n end else begin : NO_LARGE_UPSIZING\n assign cmd_step_i = cmd_step;\n end\n endgenerate\n \n generate\n if ( C_FAMILY == \"rtl\" || ( C_SUPPORT_BURSTS == 0 ) || \n ( C_PACKING_LEVEL == C_NEVER_PACK ) ) begin : USE_RTL_WORD_COMPLETED\n \n // Detect when MI-side word is completely assembled.\n assign word_completed = ( cmd_fix ) |\n ( ~cmd_fix & ~cmd_complete_wrap & next_word == {C_M_AXI_BYTES_LOG{1'b0}} ) | \n ( ~cmd_fix & last_word ) | \n ( ~cmd_modified ) |\n ( C_PACKING_LEVEL == C_NEVER_PACK ) | \n ( C_SUPPORT_BURSTS == 0 );\n \n assign word_completed_qualified = word_completed & cmd_valid & ~store_in_wrap_buffer_enabled;\n \n // RTL equivalent of optimized partial extressions (address wrap for next word).\n assign word_complete_next_wrap = ( ~cmd_fix & ~cmd_complete_wrap & \n next_word == {C_M_AXI_BYTES_LOG{1'b0}} ) | \n ( C_PACKING_LEVEL == C_NEVER_PACK ) | \n ( C_SUPPORT_BURSTS == 0 );\n assign word_complete_next_wrap_qual = word_complete_next_wrap & cmd_valid & ~store_in_wrap_buffer_enabled;\n assign word_complete_next_wrap_valid = word_complete_next_wrap_qual & S_AXI_WVALID;\n assign word_complete_next_wrap_pop = word_complete_next_wrap_valid & M_AXI_WREADY_I;\n assign word_complete_next_wrap_last = word_complete_next_wrap_pop & M_AXI_WLAST_I;\n assign word_complete_next_wrap_stall = word_complete_next_wrap_valid & ~M_AXI_WREADY_I;\n \n // RTL equivalent of optimized partial extressions (last word and the remaining).\n assign word_complete_last_word = last_word & ~cmd_fix;\n assign word_complete_rest = word_complete_last_word | cmd_fix | ~cmd_modified;\n assign word_complete_rest_qual = word_complete_rest & cmd_valid & ~store_in_wrap_buffer_enabled;\n assign word_complete_rest_valid = word_complete_rest_qual & S_AXI_WVALID;\n assign word_complete_rest_pop = word_complete_rest_valid & M_AXI_WREADY_I;\n assign word_complete_rest_last = word_complete_rest_pop & M_AXI_WLAST_I;\n assign word_complete_rest_stall = word_complete_rest_valid & ~M_AXI_WREADY_I;\n \n end else begin : USE_FPGA_WORD_COMPLETED\n \n wire next_word_wrap;\n wire sel_word_complete_next_wrap;\n wire sel_word_complete_next_wrap_qual;\n wire sel_word_complete_next_wrap_stall;\n \n wire sel_last_word;\n wire sel_word_complete_rest;\n wire sel_word_complete_rest_qual;\n wire sel_word_complete_rest_stall;\n \n \n // Optimize next word address wrap branch of expression.\n //\n mig_7series_v4_0_ddr_comparator_sel_static #\n (\n .C_FAMILY(C_FAMILY),\n .C_VALUE({C_M_AXI_BYTES_LOG{1'b0}}),\n .C_DATA_WIDTH(C_M_AXI_BYTES_LOG)\n ) next_word_wrap_inst\n (\n .CIN(1'b1),\n .S(sel_first_word),\n .A(pre_next_word_1),\n .B(cmd_next_word),\n .COUT(next_word_wrap)\n );\n \n assign sel_word_complete_next_wrap = ~cmd_fix & ~cmd_complete_wrap;\n \n mig_7series_v4_0_ddr_carry_and #\n (\n .C_FAMILY(C_FAMILY)\n ) word_complete_next_wrap_inst\n (\n .CIN(next_word_wrap),\n .S(sel_word_complete_next_wrap),\n .COUT(word_complete_next_wrap)\n );\n \n assign sel_word_complete_next_wrap_qual = cmd_valid & ~store_in_wrap_buffer_enabled;\n \n mig_7series_v4_0_ddr_carry_and #\n (\n .C_FAMILY(C_FAMILY)\n ) word_complete_next_wrap_valid_inst\n (\n .CIN(word_complete_next_wrap),\n .S(sel_word_complete_next_wrap_qual),\n .COUT(word_complete_next_wrap_qual)\n );\n \n mig_7series_v4_0_ddr_carry_and #\n (\n .C_FAMILY(C_FAMILY)\n ) word_complete_next_wrap_qual_inst\n (\n .CIN(word_complete_next_wrap_qual),\n .S(S_AXI_WVALID),\n .COUT(word_complete_next_wrap_valid)\n );\n \n mig_7series_v4_0_ddr_carry_and #\n (\n .C_FAMILY(C_FAMILY)\n ) word_complete_next_wrap_pop_inst\n (\n .CIN(word_complete_next_wrap_valid),\n .S(M_AXI_WREADY_I),\n .COUT(word_complete_next_wrap_pop)\n );\n \n assign sel_word_complete_next_wrap_stall = ~M_AXI_WREADY_I;\n \n mig_7series_v4_0_ddr_carry_latch_and #\n (\n .C_FAMILY(C_FAMILY)\n ) word_complete_next_wrap_stall_inst\n (\n .CIN(word_complete_next_wrap_valid),\n .I(sel_word_complete_next_wrap_stall),\n .O(word_complete_next_wrap_stall)\n );\n \n mig_7series_v4_0_ddr_carry_and #\n (\n .C_FAMILY(C_FAMILY)\n ) word_complete_next_wrap_last_inst\n (\n .CIN(word_complete_next_wrap_pop),\n .S(M_AXI_WLAST_I),\n .COUT(word_complete_next_wrap_last)\n );\n \n // Optimize last word and \"rest\" branch of expression.\n //\n assign sel_last_word = ~cmd_fix;\n \n mig_7series_v4_0_ddr_carry_and #\n (\n .C_FAMILY(C_FAMILY)\n ) last_word_inst_2\n (\n .CIN(last_word_extra_carry),\n .S(sel_last_word),\n .COUT(word_complete_last_word)\n );\n \n assign sel_word_complete_rest = cmd_fix | ~cmd_modified;\n \n mig_7series_v4_0_ddr_carry_or #\n (\n .C_FAMILY(C_FAMILY)\n ) pop_si_data_inst\n (\n .CIN(word_complete_last_word),\n .S(sel_word_complete_rest),\n .COUT(word_complete_rest)\n );\n \n assign sel_word_complete_rest_qual = cmd_valid & ~store_in_wrap_buffer_enabled;\n \n mig_7series_v4_0_ddr_carry_and #\n (\n .C_FAMILY(C_FAMILY)\n ) word_complete_rest_valid_inst\n (\n .CIN(word_complete_rest),\n .S(sel_word_complete_rest_qual),\n .COUT(word_complete_rest_qual)\n );\n \n mig_7series_v4_0_ddr_carry_and #\n (\n .C_FAMILY(C_FAMILY)\n ) word_complete_rest_qual_inst\n (\n .CIN(word_complete_rest_qual),\n .S(S_AXI_WVALID),\n .COUT(word_complete_rest_valid)\n );\n \n mig_7series_v4_0_ddr_carry_and #\n (\n .C_FAMILY(C_FAMILY)\n ) word_complete_rest_pop_inst\n (\n .CIN(word_complete_rest_valid),\n .S(M_AXI_WREADY_I),\n .COUT(word_complete_rest_pop)\n );\n \n assign sel_word_complete_rest_stall = ~M_AXI_WREADY_I;\n \n mig_7series_v4_0_ddr_carry_latch_and #\n (\n .C_FAMILY(C_FAMILY)\n ) word_complete_rest_stall_inst\n (\n .CIN(word_complete_rest_valid),\n .I(sel_word_complete_rest_stall),\n .O(word_complete_rest_stall)\n );\n \n mig_7series_v4_0_ddr_carry_and #\n (\n .C_FAMILY(C_FAMILY)\n ) word_complete_rest_last_inst\n (\n .CIN(word_complete_rest_pop),\n .S(M_AXI_WLAST_I),\n .COUT(word_complete_rest_last)\n );\n \n // Combine the two branches to generate the full signal.\n assign word_completed = word_complete_next_wrap | word_complete_rest;\n \n assign word_completed_qualified = word_complete_next_wrap_qual | word_complete_rest_qual;\n \n end\n endgenerate\n \n // Pop word from SI-side.\n assign S_AXI_WREADY_I = ~mi_stalling & cmd_valid;\n assign S_AXI_WREADY = S_AXI_WREADY_I;\n \n // Indicate when there is data available @ MI-side.\n generate\n if ( C_FAMILY == \"rtl\" ) begin : USE_RTL_M_WVALID\n assign M_AXI_WVALID_I = S_AXI_WVALID & word_completed_qualified;\n \n end else begin : USE_FPGA_M_WVALID\n \n assign M_AXI_WVALID_I = ( word_complete_next_wrap_valid | word_complete_rest_valid);\n \n end\n endgenerate\n \n // Get SI-side data.\n generate\n if ( C_M_AXI_REGISTER ) begin : USE_REGISTER_SI_POP\n assign pop_si_data = S_AXI_WVALID & ~mi_stalling & cmd_valid;\n end else begin : NO_REGISTER_SI_POP\n if ( C_FAMILY == \"rtl\" ) begin : USE_RTL_POP_SI\n assign pop_si_data = S_AXI_WVALID & S_AXI_WREADY_I;\n end else begin : USE_FPGA_POP_SI\n assign pop_si_data = ~( word_complete_next_wrap_stall | word_complete_rest_stall ) &\n cmd_valid & S_AXI_WVALID;\n end\n end\n endgenerate\n \n // Signal that the command is done (so that it can be poped from command queue).\n generate\n if ( C_FAMILY == \"rtl\" ) begin : USE_RTL_CMD_READY\n assign cmd_ready_i = cmd_valid & M_AXI_WLAST_I & pop_mi_data_i;\n \n end else begin : USE_FPGA_CMD_READY\n assign cmd_ready_i = ( word_complete_next_wrap_last | word_complete_rest_last);\n \n end\n endgenerate\n assign cmd_ready = cmd_ready_i;\n \n // Set last upsized word.\n assign M_AXI_WLAST_I = S_AXI_WLAST;\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Keep track of data extraction:\n // \n // Current address is taken form the command buffer for the first data beat\n // to handle unaligned Write transactions. After this is the extraction \n // address usually calculated from this point.\n // FIX transactions uses the same word address for all data beats. \n // \n // Next word address is generated as current word plus the current step \n // size, with masking to facilitate sub-sized wraping. The Mask is all ones\n // for normal wraping, and less when sub-sized wraping is used.\n // \n // The calculated word addresses (current and next) is offseted by the \n // current Offset. For sub-sized transaction the Offest points to the least \n // significant address of the included data beats. (The least significant \n // word is not necessarily the first data to be packed, consider WRAP).\n // Offset is only used for sub-sized WRAP transcation that are Complete.\n // \n // First word is active during the first SI-side data beat.\n // \n // First MI is set while the entire first MI-side word is processed.\n //\n // The transaction length is taken from the command buffer combinatorialy\n // during the First MI cycle. For each generated MI word it is decreased \n // until Last beat is reached.\n // \n /////////////////////////////////////////////////////////////////////////////\n \n // Select if the offset comes from command queue directly or \n // from a counter while when extracting multiple SI words per MI word\n assign sel_first_word = first_word | cmd_fix;\n assign current_word = sel_first_word ? cmd_first_word : \n current_word_1;\n \n generate\n if ( C_FAMILY == \"rtl\" ) begin : USE_RTL_NEXT_WORD\n \n // Calculate next word.\n assign pre_next_word_i = ( next_word_i + cmd_step_i );\n \n // Calculate next word.\n assign next_word_i = sel_first_word ? cmd_next_word : \n pre_next_word_1;\n \n end else begin : USE_FPGA_NEXT_WORD\n wire [C_M_AXI_BYTES_LOG-1:0] next_sel;\n wire [C_M_AXI_BYTES_LOG:0] next_carry_local;\n \n // Assign input to local vectors.\n assign next_carry_local[0] = 1'b0;\n \n // Instantiate one carry and per level.\n for (bit_cnt = 0; bit_cnt < C_M_AXI_BYTES_LOG ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL\n \n LUT6_2 # (\n .INIT(64'h5A5A_5A66_F0F0_F0CC) \n ) LUT6_2_inst (\n .O6(next_sel[bit_cnt]), // 6/5-LUT output (1-bit)\n .O5(next_word_i[bit_cnt]), // 5-LUT output (1-bit)\n .I0(cmd_step_i[bit_cnt]), // LUT input (1-bit)\n .I1(pre_next_word_1[bit_cnt]), // LUT input (1-bit)\n .I2(cmd_next_word[bit_cnt]), // LUT input (1-bit)\n .I3(first_word), // LUT input (1-bit)\n .I4(cmd_fix), // LUT input (1-bit)\n .I5(1'b1) // LUT input (1-bit)\n );\n \n MUXCY next_carry_inst \n (\n .O (next_carry_local[bit_cnt+1]), \n .CI (next_carry_local[bit_cnt]), \n .DI (cmd_step_i[bit_cnt]), \n .S (next_sel[bit_cnt])\n ); \n \n XORCY next_xorcy_inst \n (\n .O(pre_next_word_i[bit_cnt]),\n .CI(next_carry_local[bit_cnt]),\n .LI(next_sel[bit_cnt])\n );\n \n end // end for bit_cnt\n \n end\n endgenerate\n \n // Calculate next word.\n assign next_word = next_word_i & cmd_mask;\n assign pre_next_word = pre_next_word_i & cmd_mask;\n \n // Calculate the word address with offset.\n assign current_word_adjusted = sel_first_word ? ( cmd_first_word | cmd_offset ) : \n ( current_word_1 | cmd_offset );\n\n // Prepare next word address.\n generate\n if ( C_FAMILY == \"rtl\" || C_M_AXI_REGISTER ) begin : USE_RTL_CURR_WORD\n reg [C_M_AXI_BYTES_LOG-1:0] current_word_q;\n reg first_word_q;\n reg [C_M_AXI_BYTES_LOG-1:0] pre_next_word_q;\n \n always @ (posedge ACLK) begin\n if (ARESET) begin\n first_word_q <= 1'b1;\n current_word_q <= {C_M_AXI_BYTES_LOG{1'b0}};\n pre_next_word_q <= {C_M_AXI_BYTES_LOG{1'b0}};\n end else begin\n if ( pop_si_data ) begin\n if ( S_AXI_WLAST ) begin\n // Prepare for next access.\n first_word_q <= 1'b1;\n end else begin\n first_word_q <= 1'b0;\n end\n \n current_word_q <= next_word;\n pre_next_word_q <= pre_next_word;\n end\n end\n end\n \n assign first_word = first_word_q;\n assign current_word_1 = current_word_q;\n assign pre_next_word_1 = pre_next_word_q;\n \n end else begin : USE_FPGA_CURR_WORD\n reg first_word_cmb;\n wire first_word_i;\n wire [C_M_AXI_BYTES_LOG-1:0] current_word_i;\n wire [C_M_AXI_BYTES_LOG-1:0] local_pre_next_word_i;\n \n \n always @ *\n begin\n if ( S_AXI_WLAST ) begin\n // Prepare for next access.\n first_word_cmb = 1'b1;\n end else begin\n first_word_cmb = 1'b0;\n end\n end\n \n for (bit_cnt = 0; bit_cnt < C_M_AXI_BYTES_LOG ; bit_cnt = bit_cnt + 1) begin : BIT_LANE\n LUT6 # (\n .INIT(64'hCCCA_CCCC_CCCC_CCCC) \n ) LUT6_current_inst (\n .O(current_word_i[bit_cnt]), // 6-LUT output (1-bit)\n .I0(next_word[bit_cnt]), // LUT input (1-bit)\n .I1(current_word_1[bit_cnt]), // LUT input (1-bit)\n .I2(word_complete_rest_stall), // LUT input (1-bit)\n .I3(word_complete_next_wrap_stall), // LUT input (1-bit)\n .I4(cmd_valid), // LUT input (1-bit)\n .I5(S_AXI_WVALID) // LUT input (1-bit)\n );\n \n FDRE #(\n .INIT(1'b0) // Initial value of register (1'b0 or 1'b1)\n ) FDRE_current_inst (\n .Q(current_word_1[bit_cnt]), // Data output\n .C(ACLK), // Clock input\n .CE(1'b1), // Clock enable input\n .R(ARESET), // Synchronous reset input\n .D(current_word_i[bit_cnt]) // Data input\n );\n \n LUT6 # (\n .INIT(64'hCCCA_CCCC_CCCC_CCCC) \n ) LUT6_next_inst (\n .O(local_pre_next_word_i[bit_cnt]), // 6-LUT output (1-bit)\n .I0(pre_next_word[bit_cnt]), // LUT input (1-bit)\n .I1(pre_next_word_1[bit_cnt]), // LUT input (1-bit)\n .I2(word_complete_rest_stall), // LUT input (1-bit)\n .I3(word_complete_next_wrap_stall), // LUT input (1-bit)\n .I4(cmd_valid), // LUT input (1-bit)\n .I5(S_AXI_WVALID) // LUT input (1-bit)\n );\n \n FDRE #(\n .INIT(1'b0) // Initial value of register (1'b0 or 1'b1)\n ) FDRE_next_inst (\n .Q(pre_next_word_1[bit_cnt]), // Data output\n .C(ACLK), // Clock input\n .CE(1'b1), // Clock enable input\n .R(ARESET), // Synchronous reset input\n .D(local_pre_next_word_i[bit_cnt]) // Data input\n );\n end // end for bit_cnt\n \n LUT6 # (\n .INIT(64'hCCCA_CCCC_CCCC_CCCC) \n ) LUT6_first_inst (\n .O(first_word_i), // 6-LUT output (1-bit)\n .I0(first_word_cmb), // LUT input (1-bit)\n .I1(first_word), // LUT input (1-bit)\n .I2(word_complete_rest_stall), // LUT input (1-bit)\n .I3(word_complete_next_wrap_stall), // LUT input (1-bit)\n .I4(cmd_valid), // LUT input (1-bit)\n .I5(S_AXI_WVALID) // LUT input (1-bit)\n );\n \n FDSE #(\n .INIT(1'b1) // Initial value of register (1'b0 or 1'b1)\n ) FDSE_first_inst (\n .Q(first_word), // Data output\n .C(ACLK), // Clock input\n .CE(1'b1), // Clock enable input\n .S(ARESET), // Synchronous reset input\n .D(first_word_i) // Data input\n );\n end\n endgenerate\n \n // Select command length or counted length.\n always @ *\n begin\n if ( first_mi_word )\n length_counter = cmd_length;\n else\n length_counter = length_counter_1;\n end\n \n generate\n if ( C_FAMILY == \"rtl\" ) begin : USE_RTL_LENGTH\n reg [8-1:0] length_counter_q;\n reg first_mi_word_q;\n \n // Calculate next length counter value.\n assign next_length_counter = length_counter - 1'b1;\n \n // Keep track of burst length.\n always @ (posedge ACLK) begin\n if (ARESET) begin\n first_mi_word_q <= 1'b1;\n length_counter_q <= 8'b0;\n end else begin\n if ( pop_mi_data_i ) begin\n if ( M_AXI_WLAST_I ) begin\n first_mi_word_q <= 1'b1;\n end else begin\n first_mi_word_q <= 1'b0;\n end\n \n length_counter_q <= next_length_counter;\n end\n end\n end\n \n assign first_mi_word = first_mi_word_q;\n assign length_counter_1 = length_counter_q;\n \n end else begin : USE_FPGA_LENGTH\n wire [8-1:0] length_counter_i;\n wire [8-1:0] length_counter_ii;\n wire [8-1:0] length_sel;\n wire [8-1:0] length_di;\n wire [8:0] length_local_carry;\n \n // Assign input to local vectors.\n assign length_local_carry[0] = 1'b0;\n \n for (bit_cnt = 0; bit_cnt < 8 ; bit_cnt = bit_cnt + 1) begin : BIT_LANE\n\n LUT6_2 # (\n .INIT(64'h333C_555A_FFF0_FFF0) \n ) LUT6_length_inst (\n .O6(length_sel[bit_cnt]), // 6/5-LUT output (1-bit)\n .O5(length_di[bit_cnt]), // 5-LUT output (1-bit)\n .I0(length_counter_1[bit_cnt]), // LUT input (1-bit)\n .I1(cmd_length[bit_cnt]), // LUT input (1-bit)\n .I2(1'b1), // LUT input (1-bit)\n .I3(1'b1), // LUT input (1-bit)\n .I4(first_mi_word), // LUT input (1-bit)\n .I5(1'b1) // LUT input (1-bit)\n );\n \n MUXCY carry_inst \n (\n .O (length_local_carry[bit_cnt+1]), \n .CI (length_local_carry[bit_cnt]), \n .DI (length_di[bit_cnt]), \n .S (length_sel[bit_cnt])\n ); \n \n XORCY xorcy_inst \n (\n .O(length_counter_ii[bit_cnt]),\n .CI(length_local_carry[bit_cnt]),\n .LI(length_sel[bit_cnt])\n );\n \n LUT4 # (\n .INIT(16'hCCCA) \n ) LUT4_inst (\n .O(length_counter_i[bit_cnt]), // 5-LUT output (1-bit)\n .I0(length_counter_1[bit_cnt]), // LUT input (1-bit)\n .I1(length_counter_ii[bit_cnt]), // LUT input (1-bit)\n .I2(word_complete_rest_pop), // LUT input (1-bit)\n .I3(word_complete_next_wrap_pop) // LUT input (1-bit)\n );\n \n FDRE #(\n .INIT(1'b0) // Initial value of register (1'b0 or 1'b1)\n ) FDRE_length_inst (\n .Q(length_counter_1[bit_cnt]), // Data output\n .C(ACLK), // Clock input\n .CE(1'b1), // Clock enable input\n .R(ARESET), // Synchronous reset input\n .D(length_counter_i[bit_cnt]) // Data input\n );\n \n end // end for bit_cnt\n \n wire first_mi_word_i;\n \n LUT6 # (\n .INIT(64'hAAAC_AAAC_AAAC_AAAC) \n ) LUT6_first_mi_inst (\n .O(first_mi_word_i), // 6-LUT output (1-bit)\n .I0(M_AXI_WLAST_I), // LUT input (1-bit)\n .I1(first_mi_word), // LUT input (1-bit)\n .I2(word_complete_rest_pop), // LUT input (1-bit)\n .I3(word_complete_next_wrap_pop), // LUT input (1-bit)\n .I4(1'b1), // LUT input (1-bit)\n .I5(1'b1) // LUT input (1-bit)\n );\n \n FDSE #(\n .INIT(1'b1) // Initial value of register (1'b0 or 1'b1)\n ) FDSE_inst (\n .Q(first_mi_word), // Data output\n .C(ACLK), // Clock input\n .CE(1'b1), // Clock enable input\n .S(ARESET), // Synchronous reset input\n .D(first_mi_word_i) // Data input\n );\n \n end\n endgenerate\n \n generate\n if ( C_FAMILY == \"rtl\" || C_SUPPORT_BURSTS == 0 ) begin : USE_RTL_LAST_WORD\n // Detect last beat in a burst.\n assign last_beat = ( length_counter == 8'b0 );\n \n // Determine if this last word that shall be assembled into this MI-side word.\n assign last_word = ( cmd_modified & last_beat & ( current_word == cmd_last_word ) ) |\n ( C_SUPPORT_BURSTS == 0 );\n \n end else begin : USE_FPGA_LAST_WORD\n wire last_beat_curr_word;\n \n mig_7series_v4_0_ddr_comparator_sel_static #\n (\n .C_FAMILY(C_FAMILY),\n .C_VALUE(8'b0),\n .C_DATA_WIDTH(8)\n ) last_beat_inst\n (\n .CIN(1'b1),\n .S(first_mi_word),\n .A(length_counter_1),\n .B(cmd_length),\n .COUT(last_beat)\n );\n \n mig_7series_v4_0_ddr_comparator_sel #\n (\n .C_FAMILY(C_FAMILY),\n .C_DATA_WIDTH(C_M_AXI_BYTES_LOG)\n ) last_beat_curr_word_inst\n (\n .CIN(last_beat),\n .S(sel_first_word),\n .A(current_word_1),\n .B(cmd_first_word),\n .V(cmd_last_word),\n .COUT(last_beat_curr_word)\n );\n \n mig_7series_v4_0_ddr_carry_and #\n (\n .C_FAMILY(C_FAMILY)\n ) last_word_inst\n (\n .CIN(last_beat_curr_word),\n .S(cmd_modified),\n .COUT(last_word)\n );\n\n end\n endgenerate\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Handle wrap buffer:\n //\n // The wrap buffer is used to move data around in an unaligned WRAP \n // transaction. SI-side data word(s) for an unaligned accesses are delay \n // to be packed with with the tail of the transaction to make it a WRAP\n // transaction that is aligned to native MI-side data with.\n // For example: an 32bit to 64bit write upsizing @ 0x4 will delay the first \n // word until the 0x0 data arrives in the last data beat. This will make the \n // Upsized transaction be WRAP at 0x8 on the MI-side \n // (was WRAP @ 0x4 on SI-side).\n // \n /////////////////////////////////////////////////////////////////////////////\n \n // The unaligned SI-side words are pushed into the wrap buffer.\n assign store_in_wrap_buffer_enabled = cmd_packed_wrap & ~wrap_buffer_available & cmd_valid;\n assign store_in_wrap_buffer = store_in_wrap_buffer_enabled & S_AXI_WVALID;\n assign ARESET_or_store_in_wrap_buffer = store_in_wrap_buffer | ARESET;\n // The wrap buffer is used to complete last word.\n generate\n if ( C_FAMILY == \"rtl\" ) begin : USE_RTL_USE_WRAP\n assign use_wrap_buffer = wrap_buffer_available & last_word;\n \n end else begin : USE_FPGA_USE_WRAP\n wire last_word_carry; \n \n mig_7series_v4_0_ddr_carry_and #\n (\n .C_FAMILY(C_FAMILY)\n ) last_word_inst2\n (\n .CIN(last_word),\n .S(1'b1),\n .COUT(last_word_carry)\n );\n\n mig_7series_v4_0_ddr_carry_and #\n (\n .C_FAMILY(C_FAMILY)\n ) last_word_inst3\n (\n .CIN(last_word_carry),\n .S(1'b1),\n .COUT(last_word_extra_carry)\n );\n\n mig_7series_v4_0_ddr_carry_latch_and #\n (\n .C_FAMILY(C_FAMILY)\n ) word_complete_next_wrap_stall_inst\n (\n .CIN(last_word_carry),\n .I(wrap_buffer_available),\n .O(use_wrap_buffer)\n );\n end\n endgenerate\n \n // Wrap buffer becomes available when the unaligned wrap words has been taken care of.\n always @ (posedge ACLK) begin\n if (ARESET) begin\n wrap_buffer_available <= 1'b0;\n end else begin\n if ( store_in_wrap_buffer & word_completed ) begin\n wrap_buffer_available <= 1'b1;\n end else if ( cmd_ready_i ) begin\n wrap_buffer_available <= 1'b0;\n end\n end\n end\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Handle USER bits:\n // \n // The USER bits are always propagated from the least significant SI-side \n // beat to the Up-Sized MI-side data beat. That means:\n // * FIX transactions propagate all USER data (1:1 SI- vs MI-side beat ratio).\n // * INCR transactions uses the first SI-side beat that goes into a MI-side\n // data word.\n // * WRAP always propagates the USER bits from the most zero aligned SI-side \n // data word, regardless if the data is packed or not. For unpacked data \n // this would be a 1:1 ratio.\n /////////////////////////////////////////////////////////////////////////////\n \n // Detect first SI-side word per MI-side word.\n assign first_si_in_mi = cmd_fix | \n first_word |\n ~cmd_modified |\n (cmd_modified & current_word == {C_M_AXI_BYTES_LOG{1'b0}}) |\n ( C_SUPPORT_BURSTS == 0 );\n \n // Select USER bits combinatorially when expanding or fix.\n always @ *\n begin\n if ( C_AXI_SUPPORTS_USER_SIGNALS ) begin\n if ( first_si_in_mi ) begin\n M_AXI_WUSER_I = S_AXI_WUSER;\n end else begin\n M_AXI_WUSER_I = M_AXI_WUSER_II;\n end\n end else begin\n M_AXI_WUSER_I = {C_AXI_WUSER_WIDTH{1'b0}};\n end\n end\n \n // Capture user bits.\n always @ (posedge ACLK) begin\n if (ARESET) begin\n M_AXI_WUSER_II <= {C_AXI_WUSER_WIDTH{1'b0}};\n end else begin\n if ( first_si_in_mi & pop_si_data ) begin\n M_AXI_WUSER_II <= S_AXI_WUSER;\n end\n end\n end\n \n \n /////////////////////////////////////////////////////////////////////////////\n // Pack multiple data SI-side words into fewer MI-side data word.\n // Data is only packed when modify is set. Granularity is SI-side word for \n // the combinatorial data mux.\n //\n // Expander:\n // WDATA is expanded to all SI-word lane on the MI-side.\n // WSTRB is activted to the correct SI-word lane on the MI-side.\n //\n // Packer:\n // The WDATA and WSTRB registers are always cleared before a new word is \n // assembled.\n // WDATA is (SI-side word granularity)\n // * Combinatorial WDATA is used for current word line or when expanding.\n // * All other is taken from registers.\n // WSTRB is\n // * Combinatorial for single data to matching word lane\n // * Zero for single data to mismatched word lane\n // * Register data when multiple data\n // \n // To support sub-sized packing during Always Pack is the combinatorial \n // information packed with \"or\" instead of multiplexing.\n //\n /////////////////////////////////////////////////////////////////////////////\n \n // Determine if expander data should be used.\n assign use_expander_data = ~cmd_modified & cmd_valid;\n \n // Registers and combinatorial data word mux.\n generate\n for (word_cnt = 0; word_cnt < C_RATIO ; word_cnt = word_cnt + 1) begin : WORD_LANE\n \n // Generate select signal per SI-side word.\n if ( C_RATIO == 1 ) begin : SINGLE_WORD\n assign current_word_idx[word_cnt] = 1'b1;\n end else begin : MULTIPLE_WORD\n assign current_word_idx[word_cnt] = current_word_adjusted[C_M_AXI_BYTES_LOG-C_RATIO_LOG +: C_RATIO_LOG] == word_cnt;\n end\n \n if ( ( C_PACKING_LEVEL == C_NEVER_PACK ) | ( C_SUPPORT_BURSTS == 0 ) ) begin : USE_EXPANDER\n // Expander only functionality.\n \n if ( C_M_AXI_REGISTER ) begin : USE_REGISTER\n \n always @ (posedge ACLK) begin\n if (ARESET) begin\n M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH +: C_S_AXI_DATA_WIDTH] = {C_S_AXI_DATA_WIDTH{1'b0}};\n M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8 +: C_S_AXI_DATA_WIDTH/8] = {C_S_AXI_DATA_WIDTH/8{1'b0}};\n end else begin\n if ( pop_si_data ) begin\n M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH +: C_S_AXI_DATA_WIDTH] = S_AXI_WDATA;\n \n // Multiplex write strobe.\n if ( current_word_idx[word_cnt] ) begin\n // Combinatorial for last word to MI-side (only word for single).\n M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8 +: C_S_AXI_DATA_WIDTH/8] = S_AXI_WSTRB;\n end else begin\n // Use registered strobes. Registers are zero until valid data is written.\n // I.e. zero when used for mismatched lanes while expanding.\n M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8 +: C_S_AXI_DATA_WIDTH/8] = {C_S_AXI_DATA_WIDTH/8{1'b0}};\n end\n end\n end\n end\n \n end else begin : NO_REGISTER\n always @ *\n begin\n M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH +: C_S_AXI_DATA_WIDTH] = S_AXI_WDATA;\n \n // Multiplex write strobe.\n if ( current_word_idx[word_cnt] ) begin\n // Combinatorial for last word to MI-side (only word for single).\n M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8 +: C_S_AXI_DATA_WIDTH/8] = S_AXI_WSTRB;\n end else begin\n // Use registered strobes. Registers are zero until valid data is written.\n // I.e. zero when used for mismatched lanes while expanding.\n M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8 +: C_S_AXI_DATA_WIDTH/8] = {C_S_AXI_DATA_WIDTH/8{1'b0}};\n end\n end\n \n end // end if C_M_AXI_REGISTER\n \n end else begin : USE_ALWAYS_PACKER\n // Packer functionality\n \n for (byte_cnt = 0; byte_cnt < C_S_AXI_DATA_WIDTH / 8 ; byte_cnt = byte_cnt + 1) begin : BYTE_LANE\n \n if ( C_FAMILY == \"rtl\" ) begin : USE_RTL_DATA\n // Generate extended write data and strobe in wrap buffer.\n always @ (posedge ACLK) begin\n if (ARESET) begin\n wdata_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0;\n wstrb_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0;\n end else begin\n if ( cmd_ready_i ) begin\n wdata_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0;\n wstrb_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0;\n end else if ( current_word_idx[word_cnt] & store_in_wrap_buffer & S_AXI_WSTRB[byte_cnt] ) begin\n wdata_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= S_AXI_WDATA[byte_cnt*8 +: 8];\n wstrb_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= S_AXI_WSTRB[byte_cnt];\n end\n end\n end\n \n assign wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = \n wdata_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8];\n assign wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = \n wstrb_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1];\n \n if ( C_M_AXI_REGISTER ) begin : USE_REGISTER\n \n always @ (posedge ACLK) begin\n if (ARESET) begin\n M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0;\n M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0;\n end else begin\n if ( ( current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] | use_expander_data ) & pop_si_data & ~store_in_wrap_buffer ) begin\n M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= S_AXI_WDATA[byte_cnt*8 +: 8];\n end else if ( use_wrap_buffer & pop_si_data &\n wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] ) begin\n M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8];\n end else if ( pop_mi_data ) begin\n M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0;\n end\n \n if ( current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] & pop_si_data & ~store_in_wrap_buffer ) begin\n M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= S_AXI_WSTRB[byte_cnt];\n end else if ( use_wrap_buffer & pop_si_data &\n wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] ) begin\n M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b1;\n end else if ( pop_mi_data ) begin\n M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0;\n end\n end\n end\n \n end else begin : NO_REGISTER\n \n // Generate extended write data and strobe.\n always @ (posedge ACLK) begin\n if (ARESET) begin\n wdata_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0;\n wstrb_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0;\n end else begin\n if ( pop_mi_data | store_in_wrap_buffer_enabled ) begin\n wdata_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0;\n wstrb_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0;\n end else if ( current_word_idx[word_cnt] & pop_si_data & S_AXI_WSTRB[byte_cnt] ) begin\n wdata_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= S_AXI_WDATA[byte_cnt*8 +: 8];\n wstrb_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= S_AXI_WSTRB[byte_cnt];\n end\n end\n end\n \n assign wdata_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = \n wdata_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8];\n assign wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = \n wstrb_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1];\n \n // Select packed or extended data.\n always @ *\n begin\n // Multiplex data.\n if ( ( current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] ) | use_expander_data ) begin\n wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = S_AXI_WDATA[byte_cnt*8 +: 8];\n end else begin\n wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = 8'b0;\n end\n \n // Multiplex write strobe.\n if ( current_word_idx[word_cnt] ) begin\n // Combinatorial for last word to MI-side (only word for single).\n wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = S_AXI_WSTRB[byte_cnt];\n end else begin\n // Use registered strobes. Registers are zero until valid data is written.\n // I.e. zero when used for mismatched lanes while expanding.\n wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = 1'b0;\n end\n end\n \n // Merge previous with current data.\n always @ *\n begin\n M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = \n ( wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] ) | \n ( wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] ) | \n ( wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] & use_wrap_buffer );\n \n M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = \n ( wdata_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] ) | \n ( wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] ) |\n ( wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] & {8{use_wrap_buffer}} );\n end\n \n end // end if C_M_AXI_REGISTER\n end else begin : USE_FPGA_DATA\n \n always @ *\n begin\n if ( cmd_ready_i ) begin\n wdata_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = 8'b0;\n wstrb_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = 1'b0;\n end else if ( current_word_idx[word_cnt] & store_in_wrap_buffer & S_AXI_WSTRB[byte_cnt] ) begin\n wdata_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = S_AXI_WDATA[byte_cnt*8 +: 8];\n wstrb_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = 1'b1;\n end else begin\n wdata_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = \n wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8];\n wstrb_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = \n wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1];\n end\n end\n \n for (bit_cnt = 0; bit_cnt < 8 ; bit_cnt = bit_cnt + 1) begin : BIT_LANE\n FDRE #(\n .INIT(1'b0) // Initial value of register (1'b0 or 1'b1)\n ) FDRE_wdata_inst (\n .Q(wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // Data output\n .C(ACLK), // Clock input\n .CE(1'b1), // Clock enable input\n .R(ARESET), // Synchronous reset input\n .D(wdata_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]) // Data input\n );\n \n end // end for bit_cnt\n \n FDRE #(\n .INIT(1'b0) // Initial value of register (1'b0 or 1'b1)\n ) FDRE_wstrb_inst (\n .Q(wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // Data output\n .C(ACLK), // Clock input\n .CE(1'b1), // Clock enable input\n .R(ARESET), // Synchronous reset input\n .D(wstrb_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]) // Data input\n );\n \n if ( C_M_AXI_REGISTER ) begin : USE_REGISTER\n \n assign wdata_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] = ( current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] | use_expander_data ) & pop_si_data & ~store_in_wrap_buffer_enabled;\n assign wstrb_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] = current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] & pop_si_data & ~store_in_wrap_buffer_enabled;\n \n assign wrap_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] = use_wrap_buffer & pop_si_data &\n wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1];\n \n for (bit_cnt = 0; bit_cnt < 8 ; bit_cnt = bit_cnt + 1) begin : BIT_LANE\n \n LUT6 # (\n .INIT(64'hF0F0_F0F0_CCCC_00AA) \n ) LUT6_data_inst (\n .O(M_AXI_WDATA_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // 6-LUT output (1-bit)\n .I0(M_AXI_WDATA_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // LUT input (1-bit)\n .I1(wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // LUT input (1-bit)\n .I2(S_AXI_WDATA[byte_cnt*8+bit_cnt]), // LUT input (1-bit)\n .I3(pop_mi_data), // LUT input (1-bit)\n .I4(wrap_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)\n .I5(wdata_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]) // LUT input (1-bit)\n );\n \n FDRE #(\n .INIT(1'b0) // Initial value of register (1'b0 or 1'b1)\n ) FDRE_wdata_inst (\n .Q(M_AXI_WDATA_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // Data output\n .C(ACLK), // Clock input\n .CE(1'b1), // Clock enable input\n .R(ARESET), // Synchronous reset input\n .D(M_AXI_WDATA_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]) // Data input\n );\n \n end // end for bit_cnt\n \n LUT6 # (\n .INIT(64'hF0F0_F0F0_CCCC_00AA) \n ) LUT6_strb_inst (\n .O(M_AXI_WSTRB_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // 6-LUT output (1-bit)\n .I0(M_AXI_WSTRB_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)\n .I1(wrap_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)\n .I2(S_AXI_WSTRB[byte_cnt]), // LUT input (1-bit)\n .I3(pop_mi_data), // LUT input (1-bit)\n .I4(wrap_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)\n .I5(wstrb_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]) // LUT input (1-bit)\n );\n \n FDRE #(\n .INIT(1'b0) // Initial value of register (1'b0 or 1'b1)\n ) FDRE_wstrb_inst (\n .Q(M_AXI_WSTRB_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // Data output\n .C(ACLK), // Clock input\n .CE(1'b1), // Clock enable input\n .R(ARESET), // Synchronous reset input\n .D(M_AXI_WSTRB_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]) // Data input\n );\n \n always @ * \n begin\n M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = M_AXI_WDATA_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8];\n M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = M_AXI_WSTRB_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1];\n end\n \n end else begin : NO_REGISTER\n \n assign wdata_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] = current_word_idx[word_cnt] & cmd_valid & S_AXI_WSTRB[byte_cnt];\n \n assign wstrb_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] = current_word_idx[word_cnt] & \n S_AXI_WSTRB[byte_cnt] & \n cmd_valid & S_AXI_WVALID;\n \n for (bit_cnt = 0; bit_cnt < 8 ; bit_cnt = bit_cnt + 1) begin : BIT_LANE\n LUT6 # (\n .INIT(64'hCCCA_CCCC_CCCC_CCCC) \n ) LUT6_data_inst (\n .O(wdata_buffer_i[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // 6-LUT output (1-bit)\n .I0(S_AXI_WDATA[byte_cnt*8+bit_cnt]), // LUT input (1-bit)\n .I1(wdata_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // LUT input (1-bit)\n .I2(word_complete_rest_stall), // LUT input (1-bit)\n .I3(word_complete_next_wrap_stall), // LUT input (1-bit)\n .I4(wdata_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)\n .I5(S_AXI_WVALID) // LUT input (1-bit)\n );\n \n FDRE #(\n .INIT(1'b0) // Initial value of register (1'b0 or 1'b1)\n ) FDRE_wdata_inst (\n .Q(wdata_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // Data output\n .C(ACLK), // Clock input\n .CE(1'b1), // Clock enable input\n .R(ARESET), // Synchronous reset input\n .D(wdata_buffer_i[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]) // Data input\n );\n \n end // end for bit_cnt\n \n LUT6 # (\n .INIT(64'h0000_0000_0000_AAAE) \n ) LUT6_strb_inst (\n .O(wstrb_buffer_i[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // 6-LUT output (1-bit)\n .I0(wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)\n .I1(wstrb_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)\n .I2(word_complete_rest_stall), // LUT input (1-bit)\n .I3(word_complete_next_wrap_stall), // LUT input (1-bit)\n .I4(word_complete_rest_pop), // LUT input (1-bit)\n .I5(word_complete_next_wrap_pop) // LUT input (1-bit)\n );\n \n FDRE #(\n .INIT(1'b0) // Initial value of register (1'b0 or 1'b1)\n ) FDRE_wstrb_inst (\n .Q(wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // Data output\n .C(ACLK), // Clock input\n .CE(1'b1), // Clock enable input\n .R(ARESET_or_store_in_wrap_buffer), // Synchronous reset input\n .D(wstrb_buffer_i[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]) // Data input\n );\n \n // Select packed or extended data.\n always @ *\n begin\n // Multiplex data.\n if ( ( current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] ) | use_expander_data ) begin\n wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = S_AXI_WDATA[byte_cnt*8 +: 8];\n end else begin\n wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = \n ( wdata_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] & {8{wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]}} ) | \n ( wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] & {8{use_wrap_buffer}} );\n end\n \n // Multiplex write strobe.\n if ( current_word_idx[word_cnt] ) begin\n // Combinatorial for last word to MI-side (only word for single).\n wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = S_AXI_WSTRB[byte_cnt] |\n ( wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] ) | \n ( wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] & use_wrap_buffer );\n end else begin\n // Use registered strobes. Registers are zero until valid data is written.\n // I.e. zero when used for mismatched lanes while expanding.\n wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = \n ( wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] ) | \n ( wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] & use_wrap_buffer );\n end\n end\n \n // Merge previous with current data.\n always @ *\n begin\n M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = \n ( wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] );\n \n M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = \n ( wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] );\n end\n \n end // end if C_M_AXI_REGISTER\n end // end if C_FAMILY\n end // end for byte_cnt\n end // end if USE_ALWAYS_PACKER\n end // end for word_cnt\n endgenerate\n \n \n /////////////////////////////////////////////////////////////////////////////\n // MI-side output handling\n /////////////////////////////////////////////////////////////////////////////\n \n generate\n if ( C_M_AXI_REGISTER ) begin : USE_REGISTER\n reg M_AXI_WLAST_q;\n reg [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER_q;\n reg M_AXI_WVALID_q;\n \n // Register MI-side Data.\n always @ (posedge ACLK) begin\n if (ARESET) begin\n M_AXI_WLAST_q <= 1'b0;\n M_AXI_WUSER_q <= {C_AXI_WUSER_WIDTH{1'b0}};\n M_AXI_WVALID_q <= 1'b0;\n \n end else begin\n if ( M_AXI_WREADY_I ) begin\n M_AXI_WLAST_q <= M_AXI_WLAST_I;\n M_AXI_WUSER_q <= M_AXI_WUSER_I;\n M_AXI_WVALID_q <= M_AXI_WVALID_I;\n end\n \n end\n end\n \n assign M_AXI_WDATA = M_AXI_WDATA_I;\n assign M_AXI_WSTRB = M_AXI_WSTRB_I;\n assign M_AXI_WLAST = M_AXI_WLAST_q;\n assign M_AXI_WUSER = M_AXI_WUSER_q;\n assign M_AXI_WVALID = M_AXI_WVALID_q;\n assign M_AXI_WREADY_I = ( M_AXI_WVALID_q & M_AXI_WREADY) | ~M_AXI_WVALID_q;\n \n // Get MI-side data.\n assign pop_mi_data_i = M_AXI_WVALID_I & M_AXI_WREADY_I;\n assign pop_mi_data = M_AXI_WVALID_q & M_AXI_WREADY_I;\n \n // Detect when MI-side is stalling.\n assign mi_stalling = ( M_AXI_WVALID_q & ~M_AXI_WREADY_I ) & ~store_in_wrap_buffer_enabled;\n \n end else begin : NO_REGISTER\n \n // Combinatorial MI-side Data.\n assign M_AXI_WDATA = M_AXI_WDATA_I;\n assign M_AXI_WSTRB = M_AXI_WSTRB_I;\n assign M_AXI_WLAST = M_AXI_WLAST_I;\n assign M_AXI_WUSER = M_AXI_WUSER_I;\n assign M_AXI_WVALID = M_AXI_WVALID_I;\n assign M_AXI_WREADY_I = M_AXI_WREADY;\n \n // Get MI-side data.\n if ( C_FAMILY == \"rtl\" ) begin : USE_RTL_POP_MI\n assign pop_mi_data_i = M_AXI_WVALID_I & M_AXI_WREADY_I;\n \n end else begin : USE_FPGA_POP_MI\n \n assign pop_mi_data_i = ( word_complete_next_wrap_pop | word_complete_rest_pop);\n \n end\n assign pop_mi_data = pop_mi_data_i;\n \n // Detect when MI-side is stalling.\n assign mi_stalling = word_completed_qualified & ~M_AXI_WREADY_I;\n \n end\n endgenerate\n \n \nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/clocking/mig_7series_v4_0_clk_ibuf.v", "content": "//*****************************************************************************\n// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor: Xilinx\n// \\ \\ \\/ Version:%version\n// \\ \\ Application: MIG\n// / / Filename: clk_ibuf.v\n// /___/ /\\ Date Last Modified: $Date: 2011/06/02 08:34:56 $\n// \\ \\ / \\ Date Created:Mon Aug 3 2009\n// \\___\\/\\___\\\n//\n//Device: Virtex-6\n//Design Name: DDR3 SDRAM\n//Purpose:\n// Clock generation/distribution and reset synchronization\n//Reference:\n//Revision History:\n//*****************************************************************************\n`timescale 1ns/1ps\n\nmodule mig_7series_v4_0_clk_ibuf #\n (\n parameter SYSCLK_TYPE = \"DIFFERENTIAL\",\n // input clock type\n parameter DIFF_TERM_SYSCLK = \"TRUE\"\n // Differential Termination\n )\n (\n // Clock inputs\n input sys_clk_p, // System clock diff input\n input sys_clk_n,\n input sys_clk_i,\n output mmcm_clk\n );\n\n (* KEEP = \"TRUE\" *) wire sys_clk_ibufg /* synthesis syn_keep = 1 */;\n\n generate\n if (SYSCLK_TYPE == \"DIFFERENTIAL\") begin: diff_input_clk\n\n //***********************************************************************\n // Differential input clock input buffers\n //***********************************************************************\n\n IBUFGDS #\n (\n .DIFF_TERM (DIFF_TERM_SYSCLK),\n .IBUF_LOW_PWR (\"FALSE\")\n )\n u_ibufg_sys_clk\n (\n .I (sys_clk_p),\n .IB (sys_clk_n),\n .O (sys_clk_ibufg)\n );\n\n end else if (SYSCLK_TYPE == \"SINGLE_ENDED\") begin: se_input_clk\n\n //***********************************************************************\n // SINGLE_ENDED input clock input buffers\n //***********************************************************************\n\n IBUFG #\n (\n .IBUF_LOW_PWR (\"FALSE\")\n )\n u_ibufg_sys_clk\n (\n .I (sys_clk_i),\n .O (sys_clk_ibufg)\n );\n end else if (SYSCLK_TYPE == \"NO_BUFFER\") begin: internal_clk\n\n //***********************************************************************\n // System clock is driven from FPGA internal clock (clock from fabric)\n //***********************************************************************\n assign sys_clk_ibufg = sys_clk_i;\n end\n endgenerate\n\n assign mmcm_clk = sys_clk_ibufg;\n\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/clocking/mig_7series_v4_0_infrastructure.v", "content": "//*****************************************************************************\n// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor: Xilinx\n// \\ \\ \\/ Version: %version\n// \\ \\ Application: MIG\n// / / Filename: infrastructure.v\n// /___/ /\\ Date Last Modified: $Date: 2011/06/02 08:34:56 $\n// \\ \\ / \\ Date Created:Tue Jun 30 2009\n// \\___\\/\\___\\\n//\n//Device: Virtex-6\n//Design Name: DDR3 SDRAM\n//Purpose:\n// Clock generation/distribution and reset synchronization\n//Reference:\n//Revision History:\n//*****************************************************************************\n\n/******************************************************************************\n**$Id: infrastructure.v,v 1.1 2011/06/02 08:34:56 mishra Exp $\n**$Date: 2011/06/02 08:34:56 $\n**$Author: mishra $\n**$Revision: 1.1 $\n**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/clocking/infrastructure.v,v $\n******************************************************************************/\n\n`timescale 1ps/1ps\n\n\nmodule mig_7series_v4_0_infrastructure #\n (\n parameter SIMULATION = \"FALSE\", // Should be TRUE during design simulations and\n // FALSE during implementations\n parameter TCQ = 100, // clk->out delay (sim only)\n parameter CLKIN_PERIOD = 3000, // Memory clock period\n parameter nCK_PER_CLK = 2, // Fabric clk period:Memory clk period\n parameter SYSCLK_TYPE = \"DIFFERENTIAL\",\n // input clock type\n // \"DIFFERENTIAL\",\"SINGLE_ENDED\"\n parameter UI_EXTRA_CLOCKS = \"FALSE\",\n // Generates extra clocks as\n // 1/2, 1/4 and 1/8 of fabrick clock.\n // Valid for DDR2/DDR3 AXI interfaces\n // based on GUI selection\n parameter CLKFBOUT_MULT = 4, // write PLL VCO multiplier\n parameter DIVCLK_DIVIDE = 1, // write PLL VCO divisor\n parameter CLKOUT0_PHASE = 45.0, // VCO output divisor for clkout0\n parameter CLKOUT0_DIVIDE = 16, // VCO output divisor for PLL clkout0\n parameter CLKOUT1_DIVIDE = 4, // VCO output divisor for PLL clkout1\n parameter CLKOUT2_DIVIDE = 64, // VCO output divisor for PLL clkout2\n parameter CLKOUT3_DIVIDE = 16, // VCO output divisor for PLL clkout3\n parameter MMCM_VCO = 1200, // Max Freq (MHz) of MMCM VCO\n parameter MMCM_MULT_F = 4, // write MMCM VCO multiplier\n parameter MMCM_DIVCLK_DIVIDE = 1, // write MMCM VCO divisor\n parameter MMCM_CLKOUT0_EN = \"FALSE\", // Enabled (or) Disable MMCM clkout0\n parameter MMCM_CLKOUT1_EN = \"FALSE\", // Enabled (or) Disable MMCM clkout1\n parameter MMCM_CLKOUT2_EN = \"FALSE\", // Enabled (or) Disable MMCM clkout2\n parameter MMCM_CLKOUT3_EN = \"FALSE\", // Enabled (or) Disable MMCM clkout3\n parameter MMCM_CLKOUT4_EN = \"FALSE\", // Enabled (or) Disable MMCM clkout4\n parameter MMCM_CLKOUT0_DIVIDE = 1, // VCO output divisor for MMCM clkout0\n parameter MMCM_CLKOUT1_DIVIDE = 1, // VCO output divisor for MMCM clkout1\n parameter MMCM_CLKOUT2_DIVIDE = 1, // VCO output divisor for MMCM clkout2\n parameter MMCM_CLKOUT3_DIVIDE = 1, // VCO output divisor for MMCM clkout3\n parameter MMCM_CLKOUT4_DIVIDE = 1, // VCO output divisor for MMCM clkout4\n parameter RST_ACT_LOW = 1,\n parameter tCK = 1250,\n // memory tCK paramter.\n // # = Clock Period in pS.\n parameter MEM_TYPE = \"DDR3\"\n )\n (\n // Clock inputs\n input mmcm_clk, // System clock diff input\n // System reset input\n input sys_rst, // core reset from user application\n // PLLE2/IDELAYCTRL Lock status\n input [1:0] iodelay_ctrl_rdy, // IDELAYCTRL lock status\n // Clock outputs\n\n output clk, // fabric clock freq ; either half rate or quarter rate and is\n // determined by PLL parameters settings.\n output clk_div2, // mem_refclk divided by 2 for PI incdec\n output rst_div2, // reset in clk_div2 domain\n output mem_refclk, // equal to memory clock\n output freq_refclk, // freq above 400 MHz: set freq_refclk = mem_refclk\n // freq below 400 MHz: set freq_refclk = 2* mem_refclk or 4* mem_refclk;\n // to hard PHY for phaser\n output sync_pulse, // exactly 1/16 of mem_refclk and the sync pulse is exactly 1 memref_clk wide\n// output auxout_clk, // IO clk used to clock out Aux_Out ports\n output mmcm_ps_clk, // Phase shift clock\n output poc_sample_pd, // Tell POC when to sample phase detector output.\n output ui_addn_clk_0, // MMCM out0 clk\n output ui_addn_clk_1, // MMCM out1 clk\n output ui_addn_clk_2, // MMCM out2 clk\n output ui_addn_clk_3, // MMCM out3 clk\n output ui_addn_clk_4, // MMCM out4 clk\n output pll_locked, // locked output from PLLE2_ADV\n output mmcm_locked, // locked output from MMCME2_ADV\n // Reset outputs\n output rstdiv0, // Reset CLK and CLKDIV logic (incl I/O),\n output iddr_rst\n\n ,output rst_phaser_ref\n ,input ref_dll_lock\n ,input psen\n ,input psincdec\n ,output psdone\n );\n\n // # of clock cycles to delay deassertion of reset. Needs to be a fairly\n // high number not so much for metastability protection, but to give time\n // for reset (i.e. stable clock cycles) to propagate through all state\n // machines and to all control signals (i.e. not all control signals have\n // resets, instead they rely on base state logic being reset, and the effect\n // of that reset propagating through the logic). Need this because we may not\n // be getting stable clock cycles while reset asserted (i.e. since reset\n // depends on DCM lock status)\n localparam RST_SYNC_NUM = 25;\n\n // Round up for clk reset delay to ensure that CLKDIV reset deassertion\n // occurs at same time or after CLK reset deassertion (still need to\n // consider route delay - add one or two extra cycles to be sure!)\n localparam RST_DIV_SYNC_NUM = (RST_SYNC_NUM+1)/2;\n\n // Input clock is assumed to be equal to the memory clock frequency\n // User should change the parameter as necessary if a different input\n // clock frequency is used\n localparam real CLKIN1_PERIOD_NS = CLKIN_PERIOD / 1000.0;\n localparam CLKOUT4_DIVIDE = 2 * CLKOUT1_DIVIDE;\n\n localparam integer VCO_PERIOD\n = (CLKIN1_PERIOD_NS * DIVCLK_DIVIDE * 1000) / CLKFBOUT_MULT;\n\n localparam CLKOUT0_PERIOD = VCO_PERIOD * CLKOUT0_DIVIDE;\n localparam CLKOUT1_PERIOD = VCO_PERIOD * CLKOUT1_DIVIDE;\n localparam CLKOUT2_PERIOD = VCO_PERIOD * CLKOUT2_DIVIDE;\n localparam CLKOUT3_PERIOD = VCO_PERIOD * CLKOUT3_DIVIDE;\n localparam CLKOUT4_PERIOD = VCO_PERIOD * CLKOUT4_DIVIDE;\n\n localparam CLKOUT4_PHASE = (SIMULATION == \"TRUE\") ? 22.5 : 168.75;\n\n localparam real CLKOUT3_PERIOD_NS = CLKOUT3_PERIOD / 1000.0;\n localparam real CLKOUT4_PERIOD_NS = CLKOUT4_PERIOD / 1000.0;\n\n //synthesis translate_off\n initial begin\n $display(\"############# Write Clocks PLLE2_ADV Parameters #############\\n\");\n $display(\"nCK_PER_CLK = %7d\", nCK_PER_CLK );\n $display(\"CLK_PERIOD = %7d\", CLKIN_PERIOD );\n $display(\"CLKIN1_PERIOD = %7.3f\", CLKIN1_PERIOD_NS);\n $display(\"DIVCLK_DIVIDE = %7d\", DIVCLK_DIVIDE );\n $display(\"CLKFBOUT_MULT = %7d\", CLKFBOUT_MULT );\n $display(\"VCO_PERIOD = %7.1f\", VCO_PERIOD );\n $display(\"CLKOUT0_DIVIDE_F = %7d\", CLKOUT0_DIVIDE );\n $display(\"CLKOUT1_DIVIDE = %7d\", CLKOUT1_DIVIDE );\n $display(\"CLKOUT2_DIVIDE = %7d\", CLKOUT2_DIVIDE );\n $display(\"CLKOUT3_DIVIDE = %7d\", CLKOUT3_DIVIDE );\n $display(\"CLKOUT0_PERIOD = %7d\", CLKOUT0_PERIOD );\n $display(\"CLKOUT1_PERIOD = %7d\", CLKOUT1_PERIOD );\n $display(\"CLKOUT2_PERIOD = %7d\", CLKOUT2_PERIOD );\n $display(\"CLKOUT3_PERIOD = %7d\", CLKOUT3_PERIOD );\n $display(\"CLKOUT4_PERIOD = %7d\", CLKOUT4_PERIOD );\n $display(\"############################################################\\n\");\n end\n //synthesis translate_on\n\n wire clk_bufg;\n wire clk_pll;\n wire clkfbout_pll;\n wire mmcm_clkfbout;\n wire pll_locked_i\n /* synthesis syn_maxfan = 10 */;\n (* max_fanout = 50 *) reg [RST_DIV_SYNC_NUM-2:0] rstdiv0_sync_r;\n wire rst_tmp;\n (* max_fanout = 50 *) reg rstdiv0_sync_r1\n /* synthesis syn_maxfan = 50 */;\n reg [RST_DIV_SYNC_NUM-2:0] rst_sync_r;\n (* max_fanout = 10 *) reg rst_sync_r1\n /* synthesis syn_maxfan = 10 */;\n reg [RST_DIV_SYNC_NUM-2:0] rstdiv2_sync_r;\n (* max_fanout = 10 *) reg rstdiv2_sync_r1\n /* synthesis syn_maxfan = 10 */;\n wire sys_rst_act_hi;\n\n wire rst_tmp_phaser_ref;\n (* max_fanout = 50 *) reg [RST_DIV_SYNC_NUM-1:0] rst_phaser_ref_sync_r\n /* synthesis syn_maxfan = 10 */;\n\n // Instantiation of the MMCM primitive\n wire clkfbout;\n wire MMCM_Locked_i;\n\n wire mmcm_clkout0;\n wire mmcm_clkout1;\n wire mmcm_clkout2;\n wire mmcm_clkout3;\n wire mmcm_clkout4;\n wire mmcm_ps_clk_bufg_in;\n wire clk_div2_bufg_in;\n\n wire pll_clk3_out;\n wire pll_clk3;\n\n assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst: sys_rst;\n\n //***************************************************************************\n // Assign global clocks:\n // 2. clk : Half rate / Quarter rate(used for majority of internal logic)\n //***************************************************************************\n\n assign clk = clk_bufg;\n assign pll_locked = pll_locked_i & MMCM_Locked_i;\n assign mmcm_locked = MMCM_Locked_i;\n\n\n //***************************************************************************\n // Global base clock generation and distribution\n //***************************************************************************\n\n //*****************************************************************\n // NOTES ON CALCULTING PROPER VCO FREQUENCY\n // 1. VCO frequency =\n // 1/((DIVCLK_DIVIDE * CLKIN_PERIOD)/(CLKFBOUT_MULT * nCK_PER_CLK))\n // 2. VCO frequency must be in the range [TBD, TBD]\n //*****************************************************************\n\n PLLE2_ADV #\n (\n .BANDWIDTH (\"OPTIMIZED\"),\n .COMPENSATION (\"INTERNAL\"),\n .STARTUP_WAIT (\"FALSE\"),\n .CLKOUT0_DIVIDE (CLKOUT0_DIVIDE), // 4 freq_ref\n .CLKOUT1_DIVIDE (CLKOUT1_DIVIDE), // 4 mem_ref\n .CLKOUT2_DIVIDE (CLKOUT2_DIVIDE), // 16 sync\n .CLKOUT3_DIVIDE (CLKOUT3_DIVIDE), // 16 sysclk\n .CLKOUT4_DIVIDE (CLKOUT4_DIVIDE),\n .CLKOUT5_DIVIDE (),\n .DIVCLK_DIVIDE (DIVCLK_DIVIDE),\n .CLKFBOUT_MULT (CLKFBOUT_MULT),\n .CLKFBOUT_PHASE (0.000),\n .CLKIN1_PERIOD (CLKIN1_PERIOD_NS),\n .CLKIN2_PERIOD (),\n .CLKOUT0_DUTY_CYCLE (0.500),\n .CLKOUT0_PHASE (CLKOUT0_PHASE),\n .CLKOUT1_DUTY_CYCLE (0.500),\n .CLKOUT1_PHASE (0.000),\n .CLKOUT2_DUTY_CYCLE (1.0/16.0),\n .CLKOUT2_PHASE (9.84375), // PHASE shift is required for sync pulse generation.\n .CLKOUT3_DUTY_CYCLE (0.500),\n .CLKOUT3_PHASE (0.000),\n .CLKOUT4_DUTY_CYCLE (0.500),\n .CLKOUT4_PHASE (CLKOUT4_PHASE),\n .CLKOUT5_DUTY_CYCLE (0.500),\n .CLKOUT5_PHASE (0.000),\n .REF_JITTER1 (0.010),\n .REF_JITTER2 (0.010)\n )\n plle2_i\n (\n .CLKFBOUT (pll_clkfbout),\n .CLKOUT0 (freq_refclk),\n .CLKOUT1 (mem_refclk),\n .CLKOUT2 (sync_pulse), // always 1/16 of mem_ref_clk\n .CLKOUT3 (pll_clk3_out),\n// .CLKOUT4 (auxout_clk_i),\n .CLKOUT4 (),\n .CLKOUT5 (),\n .DO (),\n .DRDY (),\n .LOCKED (pll_locked_i),\n .CLKFBIN (pll_clkfbout),\n .CLKIN1 (mmcm_clk),\n .CLKIN2 (),\n .CLKINSEL (1'b1),\n .DADDR (7'b0),\n .DCLK (1'b0),\n .DEN (1'b0),\n .DI (16'b0),\n .DWE (1'b0),\n .PWRDWN (1'b0),\n .RST ( sys_rst_act_hi)\n );\n\n\n// BUFH u_bufh_auxout_clk\n// (\n// .O (auxout_clk),\n// .I (auxout_clk_i)\n// );\n\n BUFG u_bufg_clkdiv0\n (\n .O (clk_bufg),\n .I (clk_pll_i)\n );\n\n BUFH u_bufh_pll_clk3\n (\n .O (pll_clk3),\n .I (pll_clk3_out)\n );\n\n localparam real MMCM_VCO_PERIOD = 1000000.0/MMCM_VCO;\n\n //synthesis translate_off\n initial begin\n $display(\"############# MMCME2_ADV Parameters #############\\n\");\n $display(\"MMCM_MULT_F = %d\", MMCM_MULT_F);\n// $display(\"MMCM_VCO_FREQ (MHz) = %7.3f\", MMCM_VCO*1000.0);\n $display(\"MMCM_VCO_FREQ (MHz) = %7.3f\", MMCM_VCO*1.000);\n $display(\"MMCM_VCO_PERIOD = %7.3f\", MMCM_VCO_PERIOD);\n $display(\"#################################################\\n\");\n end\n //synthesis translate_on\n\n generate\n if (UI_EXTRA_CLOCKS == \"TRUE\") begin: gen_ui_extra_clocks\n\n localparam MMCM_CLKOUT0_DIVIDE_CAL = (MMCM_CLKOUT0_EN == \"TRUE\") ? MMCM_CLKOUT0_DIVIDE : MMCM_MULT_F;\n localparam MMCM_CLKOUT1_DIVIDE_CAL = (MMCM_CLKOUT1_EN == \"TRUE\") ? MMCM_CLKOUT1_DIVIDE : MMCM_MULT_F;\n localparam MMCM_CLKOUT2_DIVIDE_CAL = (MMCM_CLKOUT2_EN == \"TRUE\") ? MMCM_CLKOUT2_DIVIDE : MMCM_MULT_F;\n localparam MMCM_CLKOUT3_DIVIDE_CAL = (MMCM_CLKOUT3_EN == \"TRUE\") ? MMCM_CLKOUT3_DIVIDE : MMCM_MULT_F;\n localparam MMCM_CLKOUT4_DIVIDE_CAL = (MMCM_CLKOUT4_EN == \"TRUE\") ? MMCM_CLKOUT4_DIVIDE : MMCM_MULT_F;\n\n MMCME2_ADV\n #(.BANDWIDTH (\"HIGH\"),\n .CLKOUT4_CASCADE (\"FALSE\"),\n .COMPENSATION (\"BUF_IN\"),\n .STARTUP_WAIT (\"FALSE\"),\n// .DIVCLK_DIVIDE (1),\n .DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE),\n .CLKFBOUT_MULT_F (MMCM_MULT_F),\n .CLKFBOUT_PHASE (0.000),\n .CLKFBOUT_USE_FINE_PS (\"FALSE\"),\n .CLKOUT0_DIVIDE_F (MMCM_CLKOUT0_DIVIDE_CAL),\n .CLKOUT0_PHASE (0.000),\n .CLKOUT0_DUTY_CYCLE (0.500),\n .CLKOUT0_USE_FINE_PS (\"FALSE\"),\n .CLKOUT1_DIVIDE (MMCM_CLKOUT1_DIVIDE_CAL),\n .CLKOUT1_PHASE (0.000),\n .CLKOUT1_DUTY_CYCLE (0.500),\n .CLKOUT1_USE_FINE_PS (\"FALSE\"),\n .CLKOUT2_DIVIDE (MMCM_CLKOUT2_DIVIDE_CAL),\n .CLKOUT2_PHASE (0.000),\n .CLKOUT2_DUTY_CYCLE (0.500),\n .CLKOUT2_USE_FINE_PS (\"FALSE\"),\n .CLKOUT3_DIVIDE (MMCM_CLKOUT3_DIVIDE_CAL),\n .CLKOUT3_PHASE (0.000),\n .CLKOUT3_DUTY_CYCLE (0.500),\n .CLKOUT3_USE_FINE_PS (\"FALSE\"),\n .CLKOUT4_DIVIDE (MMCM_CLKOUT4_DIVIDE_CAL),\n .CLKOUT4_PHASE (0.000),\n .CLKOUT4_DUTY_CYCLE (0.500),\n .CLKOUT4_USE_FINE_PS (\"FALSE\"),\n .CLKOUT5_DIVIDE (((MMCM_MULT_F*2)/MMCM_DIVCLK_DIVIDE)),\n .CLKOUT5_PHASE (0.000),\n .CLKOUT5_DUTY_CYCLE (0.500),\n .CLKOUT5_USE_FINE_PS (\"TRUE\"),\n .CLKOUT6_DIVIDE (MMCM_MULT_F/2),\n .CLKOUT6_PHASE (0.000),\n .CLKOUT6_DUTY_CYCLE (0.500),\n .CLKOUT6_USE_FINE_PS (\"FALSE\"),\n .CLKIN1_PERIOD (CLKOUT3_PERIOD_NS),\n .REF_JITTER1 (0.000))\n mmcm_i\n // Output clocks\n (.CLKFBOUT (clk_pll_i),\n .CLKFBOUTB (),\n .CLKOUT0 (mmcm_clkout0),\n .CLKOUT0B (),\n .CLKOUT1 (mmcm_clkout1),\n .CLKOUT1B (),\n .CLKOUT2 (mmcm_clkout2),\n .CLKOUT2B (),\n .CLKOUT3 (mmcm_clkout3),\n .CLKOUT3B (),\n .CLKOUT4 (mmcm_clkout4),\n .CLKOUT5 (mmcm_ps_clk_bufg_in),\n .CLKOUT6 (clk_div2_bufg_in),\n // Input clock control\n .CLKFBIN (clk_bufg), // From BUFH network\n .CLKIN1 (pll_clk3), // From PLL\n .CLKIN2 (1'b0),\n // Tied to always select the primary input clock\n .CLKINSEL (1'b1),\n // Ports for dynamic reconfiguration\n .DADDR (7'h0),\n .DCLK (1'b0),\n .DEN (1'b0),\n .DI (16'h0),\n .DO (),\n .DRDY (),\n .DWE (1'b0),\n // Ports for dynamic phase shift\n .PSCLK (clk),\n .PSEN (psen),\n .PSINCDEC (psincdec),\n .PSDONE (psdone),\n // Other control and status signals\n .LOCKED (MMCM_Locked_i),\n .CLKINSTOPPED (),\n .CLKFBSTOPPED (),\n .PWRDWN (1'b0),\n .RST (~pll_locked_i));\n\n BUFG u_bufg_ui_addn_clk_0\n (\n .O (ui_addn_clk_0),\n .I (mmcm_clkout0)\n );\n\n BUFG u_bufg_ui_addn_clk_1\n (\n .O (ui_addn_clk_1),\n .I (mmcm_clkout1)\n );\n\n BUFG u_bufg_ui_addn_clk_2\n (\n .O (ui_addn_clk_2),\n .I (mmcm_clkout2)\n );\n\n BUFG u_bufg_ui_addn_clk_3\n (\n .O (ui_addn_clk_3),\n .I (mmcm_clkout3)\n );\n\n BUFG u_bufg_ui_addn_clk_4\n (\n .O (ui_addn_clk_4),\n .I (mmcm_clkout4)\n );\n\n BUFG u_bufg_mmcm_ps_clk\n (\n .O (mmcm_ps_clk),\n .I (mmcm_ps_clk_bufg_in)\n );\n \n BUFG u_bufg_clk_div2\n (\n .O (clk_div2),\n .I (clk_div2_bufg_in)\n );\n end else begin: gen_mmcm\n\n MMCME2_ADV\n #(.BANDWIDTH (\"HIGH\"),\n .CLKOUT4_CASCADE (\"FALSE\"),\n .COMPENSATION (\"BUF_IN\"),\n .STARTUP_WAIT (\"FALSE\"),\n// .DIVCLK_DIVIDE (1),\n .DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE),\n .CLKFBOUT_MULT_F (MMCM_MULT_F),\n .CLKFBOUT_PHASE (0.000),\n .CLKFBOUT_USE_FINE_PS (\"FALSE\"),\n .CLKOUT0_DIVIDE_F (((MMCM_MULT_F*2)/MMCM_DIVCLK_DIVIDE)),\n .CLKOUT0_PHASE (0.000),\n .CLKOUT0_DUTY_CYCLE (0.500),\n .CLKOUT0_USE_FINE_PS (\"TRUE\"),\n .CLKOUT1_DIVIDE (MMCM_MULT_F/2),\n .CLKOUT1_PHASE (0.000),\n .CLKOUT1_DUTY_CYCLE (0.500),\n .CLKOUT1_USE_FINE_PS (\"FALSE\"),\n .CLKIN1_PERIOD (CLKOUT3_PERIOD_NS),\n .REF_JITTER1 (0.000))\n mmcm_i\n // Output clocks\n (.CLKFBOUT (clk_pll_i),\n .CLKFBOUTB (),\n .CLKOUT0 (mmcm_ps_clk_bufg_in),\n .CLKOUT0B (),\n .CLKOUT1 (clk_div2_bufg_in),\n .CLKOUT1B (),\n .CLKOUT2 (),\n .CLKOUT2B (),\n .CLKOUT3 (),\n .CLKOUT3B (),\n .CLKOUT4 (),\n .CLKOUT5 (),\n .CLKOUT6 (),\n // Input clock control\n .CLKFBIN (clk_bufg), // From BUFH network\n .CLKIN1 (pll_clk3), // From PLL\n .CLKIN2 (1'b0),\n // Tied to always select the primary input clock\n .CLKINSEL (1'b1),\n // Ports for dynamic reconfiguration\n .DADDR (7'h0),\n .DCLK (1'b0),\n .DEN (1'b0),\n .DI (16'h0),\n .DO (),\n .DRDY (),\n .DWE (1'b0),\n // Ports for dynamic phase shift\n .PSCLK (clk),\n .PSEN (psen),\n .PSINCDEC (psincdec),\n .PSDONE (psdone),\n // Other control and status signals\n .LOCKED (MMCM_Locked_i),\n .CLKINSTOPPED (),\n .CLKFBSTOPPED (),\n .PWRDWN (1'b0),\n .RST (~pll_locked_i));\n\n BUFG u_bufg_mmcm_ps_clk\n (\n .O (mmcm_ps_clk),\n .I (mmcm_ps_clk_bufg_in)\n );\n\t \n BUFG u_bufg_clk_div2\n (\n .O (clk_div2),\n .I (clk_div2_bufg_in)\n );\n\t \n end // block: gen_mmcm\n endgenerate\n\n //***************************************************************************\n // Generate poc_sample_pd.\n //\n // As the phase shift clocks precesses around kclk, it also precesses\n // around the fabric clock. Noise may be generated as output of the\n // IDDR is registered into the fabric clock domain.\n //\n // The mmcm_ps_clk signal runs at half the rate of the fabric clock.\n // This means that there are two rising edges of fabric clock per mmcm_ps_clk.\n // If we can guarantee that the POC uses the data sampled on the second\n // fabric clock, then we are certain that the setup time to the second\n // fabric clock is greater than 1 fabric clock cycle.\n //\n // To predict when the phase detctor output is from this second edge, we\n // need to know two things. The initial phase of fabric clock and mmcm_ps_clk\n // and the number of phase offsets set into the mmcm. The later is a\n // trivial count of the PSEN signal.\n //\n // The former is a bit tricky because latching a clock with a clock is\n // not well defined. This problem is solved by generating a signal\n // the goes high on the first rising edge of mmcm_ps_clk. Logic in\n // the fabric domain can look at this signal and then develop an analog\n // the mmcm_ps_clk with zero offset.\n //\n // This all depends on the timing tools making the timing work when\n // when the mmcm phase offset is zero.\n //\n // poc_sample_pd tells the POC when to sample the phase detector output.\n // Setup from the IDDR to the fabric clock is always one plus some\n // fraction of the fabric clock.\n //***************************************************************************\n\n localparam ONE = 1;\n localparam integer TAPSPERFCLK = 56 * MMCM_MULT_F;\n localparam TAPSPERFCLK_MINUS_ONE = TAPSPERFCLK - 1;\n localparam QCNTR_WIDTH = clogb2(TAPSPERFCLK);\n \n function integer clogb2 (input integer size); // ceiling logb2\n begin\n size = size - 1;\n for (clogb2=1; size>1; clogb2=clogb2+1)\n size = size >> 1;\n end\n endfunction // clogb2\n\n reg [QCNTR_WIDTH-1:0] qcntr_ns, qcntr_r;\n always @(posedge clk) qcntr_r <= #TCQ qcntr_ns;\n\n reg inv_poc_sample_ns, inv_poc_sample_r;\n always @(posedge clk) inv_poc_sample_r <= #TCQ inv_poc_sample_ns;\n \n always @(*) begin\n qcntr_ns = qcntr_r;\n inv_poc_sample_ns = inv_poc_sample_r;\n if (rstdiv0) begin\n qcntr_ns = 'b0;\n inv_poc_sample_ns = 'b0;\n end else if (psen) begin\n if (qcntr_r < TAPSPERFCLK_MINUS_ONE[QCNTR_WIDTH-1:0])\n qcntr_ns = (qcntr_r + ONE[QCNTR_WIDTH-1:0]);\n else begin\n qcntr_ns = {QCNTR_WIDTH{1'b0}};\n\tinv_poc_sample_ns = ~inv_poc_sample_r;\n end\n end\n end \n\n // Be vewy vewy careful to make sure this path is aligned with the\n // phase detector out pipeline. \n reg first_rising_ps_clk_ns, first_rising_ps_clk_r;\n always @(posedge mmcm_ps_clk) first_rising_ps_clk_r <= #TCQ first_rising_ps_clk_ns;\n always @(*) first_rising_ps_clk_ns = ~rstdiv0;\n\n reg mmcm_hi0_ns, mmcm_hi0_r;\n always @(posedge clk) mmcm_hi0_r <= #TCQ mmcm_hi0_ns;\n always @(*) mmcm_hi0_ns = ~first_rising_ps_clk_r || ~mmcm_hi0_r;\n\n reg poc_sample_pd_ns, poc_sample_pd_r;\n always @(*) poc_sample_pd_ns = inv_poc_sample_ns ^ mmcm_hi0_r;\n always @(posedge clk) poc_sample_pd_r <= #TCQ poc_sample_pd_ns;\n assign poc_sample_pd = poc_sample_pd_r;\n\n //***************************************************************************\n // Make sure logic acheives 90 degree setup time from rising mmcm_ps_clk\n // to the appropriate edge of fabric clock\n //***************************************************************************\n\n //synthesis translate_off\n generate \n if ( tCK <= 2500 ) begin : check_ocal_timing\n localparam CLK_PERIOD_PS = MMCM_VCO_PERIOD * MMCM_MULT_F;\n localparam integer CLK_PERIOD_PS_DIV4 = CLK_PERIOD_PS/4;\n\n time rising_mmcm_ps_clk;\n always @(posedge mmcm_ps_clk) rising_mmcm_ps_clk = $time();\n\n time pdiff; // Not used, except in waveform plots.\n always @(posedge clk) pdiff = $time() - rising_mmcm_ps_clk;\n end\n endgenerate\n\n //synthesis translate_on\n\n //***************************************************************************\n // RESET SYNCHRONIZATION DESCRIPTION:\n // Various resets are generated to ensure that:\n // 1. All resets are synchronously deasserted with respect to the clock\n // domain they are interfacing to. There are several different clock\n // domains - each one will receive a synchronized reset.\n // 2. The reset deassertion order starts with deassertion of SYS_RST,\n // followed by deassertion of resets for various parts of the design\n // (see \"RESET ORDER\" below) based on the lock status of PLLE2s.\n // RESET ORDER:\n // 1. User deasserts SYS_RST\n // 2. Reset PLLE2 and IDELAYCTRL\n // 3. Wait for PLLE2 and IDELAYCTRL to lock\n // 4. Release reset for all I/O primitives and internal logic\n // OTHER NOTES:\n // 1. Asynchronously assert reset. This way we can assert reset even if\n // there is no clock (needed for things like 3-stating output buffers\n // to prevent initial bus contention). Reset deassertion is synchronous.\n //***************************************************************************\n\n //*****************************************************************\n // CLKDIV logic reset\n //*****************************************************************\n\n // Wait for PLLE2 and IDELAYCTRL to lock before releasing reset\n\n // current O,25.0 unisim phaser_ref never locks. Need to find out why .\n generate\n if (MEM_TYPE == \"DDR3\" && tCK <= 1500) begin: rst_tmp_300_400\n assign rst_tmp = sys_rst_act_hi | ~iodelay_ctrl_rdy[1] |\n ~ref_dll_lock | ~MMCM_Locked_i;\n end else begin: rst_tmp_200\n assign rst_tmp = sys_rst_act_hi | ~iodelay_ctrl_rdy[0] |\n ~ref_dll_lock | ~MMCM_Locked_i;\n end\n endgenerate\n\n always @(posedge clk_bufg or posedge rst_tmp) begin\n if (rst_tmp) begin\n rstdiv0_sync_r <= #TCQ {RST_DIV_SYNC_NUM-1{1'b1}};\n rstdiv0_sync_r1 <= #TCQ 1'b1 ;\n end else begin\n rstdiv0_sync_r <= #TCQ rstdiv0_sync_r << 1;\n rstdiv0_sync_r1 <= #TCQ rstdiv0_sync_r[RST_DIV_SYNC_NUM-2];\n end\n end\n\n assign rstdiv0 = rstdiv0_sync_r1 ;\n\n//IDDR rest\n always @(posedge mmcm_ps_clk or posedge rst_tmp) begin\n if (rst_tmp) begin\n rst_sync_r <= #TCQ {RST_DIV_SYNC_NUM-1{1'b1}};\n rst_sync_r1 <= #TCQ 1'b1 ;\n end else begin\n rst_sync_r <= #TCQ rst_sync_r << 1;\n rst_sync_r1 <= #TCQ rst_sync_r[RST_DIV_SYNC_NUM-2];\n end\n end\n\n assign iddr_rst = rst_sync_r1 ;\n \n// Sync reset in the clk_div2 domain\n always @(posedge clk_div2 or posedge rst_tmp) begin\n if (rst_tmp) begin\n rstdiv2_sync_r <= #TCQ {RST_DIV_SYNC_NUM-1{1'b1}};\n rstdiv2_sync_r1 <= #TCQ 1'b1 ;\n end else begin\n rstdiv2_sync_r <= #TCQ rstdiv2_sync_r << 1;\n rstdiv2_sync_r1 <= #TCQ rstdiv2_sync_r[RST_DIV_SYNC_NUM-2];\n end\n end\n\n assign rst_div2 = rstdiv2_sync_r1 ;\n\n generate\n if (MEM_TYPE == \"DDR3\" && tCK <= 1500) begin: rst_tmp_phaser_ref_300_400\n assign rst_tmp_phaser_ref = sys_rst_act_hi | ~MMCM_Locked_i | ~iodelay_ctrl_rdy[1];\n end else begin: rst_tmp_phaser_ref_200\n assign rst_tmp_phaser_ref = sys_rst_act_hi | ~MMCM_Locked_i | ~iodelay_ctrl_rdy[0];\n end\n endgenerate\n\n always @(posedge clk_bufg or posedge rst_tmp_phaser_ref)\n if (rst_tmp_phaser_ref)\n rst_phaser_ref_sync_r <= #TCQ {RST_DIV_SYNC_NUM{1'b1}};\n else\n rst_phaser_ref_sync_r <= #TCQ rst_phaser_ref_sync_r << 1;\n\n assign rst_phaser_ref = rst_phaser_ref_sync_r[RST_DIV_SYNC_NUM-1];\n\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/clocking/mig_7series_v4_0_iodelay_ctrl.v", "content": "//*****************************************************************************\n// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor: Xilinx\n// \\ \\ \\/ Version: %version\n// \\ \\ Application: MIG\n// / / Filename: iodelay_ctrl.v\n// /___/ /\\ Date Last Modified: $Date: 2011/06/02 08:34:56 $\n// \\ \\ / \\ Date Created: Wed Aug 16 2006\n// \\___\\/\\___\\\n//\n//Device: 7 Series\n//Design Name: DDR3 SDRAM\n//Purpose:\n// This module instantiates the IDELAYCTRL primitive, which continously\n// calibrates the IODELAY elements in the region to account for varying\n// environmental conditions. A 200MHz or 300MHz reference clock (depending\n// on the desired IODELAY tap resolution) must be supplied\n//Reference:\n//Revision History:\n//*****************************************************************************\n\n/******************************************************************************\n**$Id: iodelay_ctrl.v,v 1.1 2011/06/02 08:34:56 mishra Exp $\n**$Date: 2011/06/02 08:34:56 $\n**$Author: mishra $\n**$Revision: 1.1 $\n**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/clocking/iodelay_ctrl.v,v $\n******************************************************************************/\n\n`timescale 1ps/1ps\n\nmodule mig_7series_v4_0_iodelay_ctrl #\n (\n parameter TCQ = 100,\n // clk->out delay (sim only)\n parameter IODELAY_GRP0 = \"IODELAY_MIG0\",\n // May be assigned unique name when\n // multiple IP cores used in design\n parameter IODELAY_GRP1 = \"IODELAY_MIG1\",\n // May be assigned unique name when\n // multiple IP cores used in design\n parameter REFCLK_TYPE = \"DIFFERENTIAL\",\n // Reference clock type\n // \"DIFFERENTIAL\",\"SINGLE_ENDED\"\n // NO_BUFFER, USE_SYSTEM_CLOCK\n parameter SYSCLK_TYPE = \"DIFFERENTIAL\",\n // input clock type\n // DIFFERENTIAL, SINGLE_ENDED,\n // NO_BUFFER\n parameter SYS_RST_PORT = \"FALSE\",\n // \"TRUE\" - if pin is selected for sys_rst \n\t\t\t\t// and IBUF will be instantiated.\n // \"FALSE\" - if pin is not selected for sys_rst\n parameter RST_ACT_LOW = 1,\n // Reset input polarity\n // (0 = active high, 1 = active low)\n parameter DIFF_TERM_REFCLK = \"TRUE\",\n // Differential Termination\n parameter FPGA_SPEED_GRADE = 1,\n // FPGA speed grade\n parameter REF_CLK_MMCM_IODELAY_CTRL = \"FALSE\"\n )\n (\n input clk_ref_p,\n input clk_ref_n,\n input clk_ref_i,\n input sys_rst,\n output [1:0] clk_ref,\n output sys_rst_o,\n output [1:0] iodelay_ctrl_rdy\n );\n\n // # of clock cycles to delay deassertion of reset. Needs to be a fairly\n // high number not so much for metastability protection, but to give time\n // for reset (i.e. stable clock cycles) to propagate through all state\n // machines and to all control signals (i.e. not all control signals have\n // resets, instead they rely on base state logic being reset, and the effect\n // of that reset propagating through the logic). Need this because we may not\n // be getting stable clock cycles while reset asserted (i.e. since reset\n // depends on DCM lock status)\n // COMMENTED, RC, 01/13/09 - causes pack error in MAP w/ larger #\n localparam RST_SYNC_NUM = 15;\n // localparam RST_SYNC_NUM = 25;\n\n wire clk_ref_ibufg;\n wire clk_ref_mmcm_300;\n wire clk_ref_mmcm_400;\n wire mmcm_clkfbout;\n wire mmcm_Locked;\n wire [1:0] rst_ref;\n reg [RST_SYNC_NUM-1:0] rst_ref_sync_r [1:0] /* synthesis syn_maxfan = 10 */;\n wire rst_tmp_idelay;\n wire sys_rst_act_hi;\n\n //***************************************************************************\n\n // If the pin is selected for sys_rst in GUI, IBUF will be instantiated. \n // If the pin is not selected in GUI, sys_rst signal is expected to be \n // driven internally.\n generate\n if (SYS_RST_PORT == \"TRUE\")\n IBUF u_sys_rst_ibuf\n (\n .I (sys_rst),\n .O (sys_rst_o)\n );\n else\n assign sys_rst_o = sys_rst;\n endgenerate\n\n // Possible inversion of system reset as appropriate\n assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst_o: sys_rst_o;\n\n //***************************************************************************\n // 1) Input buffer for IDELAYCTRL reference clock - handle either a\n // differential or single-ended input. Global clock buffer is used to\n // drive the rest of FPGA logic.\n // 2) For NO_BUFFER option, Reference clock will be driven from internal\n // clock i.e., clock is driven from fabric. Input buffers and Global\n // clock buffers will not be instaitaed.\n // 3) For USE_SYSTEM_CLOCK, input buffer output of system clock will be used\n // as the input reference clock. Global clock buffer is used to drive\n // the rest of FPGA logic.\n //***************************************************************************\n\n generate\n if (REFCLK_TYPE == \"DIFFERENTIAL\") begin: diff_clk_ref\n IBUFGDS #\n (\n .DIFF_TERM (DIFF_TERM_REFCLK),\n .IBUF_LOW_PWR (\"FALSE\")\n )\n u_ibufg_clk_ref\n (\n .I (clk_ref_p),\n .IB (clk_ref_n),\n .O (clk_ref_ibufg)\n );\n\n end else if (REFCLK_TYPE == \"SINGLE_ENDED\") begin : se_clk_ref\n IBUFG #\n (\n .IBUF_LOW_PWR (\"FALSE\")\n )\n u_ibufg_clk_ref\n (\n .I (clk_ref_i),\n .O (clk_ref_ibufg)\n );\n\n end else if ((REFCLK_TYPE == \"NO_BUFFER\") ||\n (REFCLK_TYPE == \"USE_SYSTEM_CLOCK\" && SYSCLK_TYPE == \"NO_BUFFER\")) begin : clk_ref_noibuf_nobuf\n assign clk_ref_ibufg = clk_ref_i;\n end else if (REFCLK_TYPE == \"USE_SYSTEM_CLOCK\" && SYSCLK_TYPE != \"NO_BUFFER\") begin : clk_ref_noibuf\n assign clk_ref_ibufg = clk_ref_i;\n end\n endgenerate\n\n // reference clock 300MHz and 400MHz generation with MMCM\n generate\n if (REF_CLK_MMCM_IODELAY_CTRL == \"TRUE\") begin: clk_ref_mmcm_gen\n\n MMCME2_ADV\n #(.BANDWIDTH (\"HIGH\"),\n .CLKOUT4_CASCADE (\"FALSE\"),\n .COMPENSATION (\"INTERNAL\"),\n .STARTUP_WAIT (\"FALSE\"),\n .DIVCLK_DIVIDE (1),\n .CLKFBOUT_MULT_F (6),\n .CLKFBOUT_PHASE (0.000),\n .CLKFBOUT_USE_FINE_PS (\"FALSE\"),\n .CLKOUT0_DIVIDE_F (4),\n .CLKOUT0_PHASE (0.000),\n .CLKOUT0_DUTY_CYCLE (0.500),\n .CLKOUT0_USE_FINE_PS (\"FALSE\"),\n .CLKOUT1_DIVIDE (3),\n .CLKOUT1_PHASE (0.000),\n .CLKOUT1_DUTY_CYCLE (0.500),\n .CLKOUT1_USE_FINE_PS (\"FALSE\"),\n .CLKIN1_PERIOD (5),\n .REF_JITTER1 (0.000))\n mmcm_i\n // Output clocks\n (.CLKFBOUT (mmcm_clkfbout),\n .CLKFBOUTB (),\n .CLKOUT0 (clk_ref_mmcm_300),\n .CLKOUT0B (),\n .CLKOUT1 (clk_ref_mmcm_400),\n .CLKOUT1B (),\n .CLKOUT2 (),\n .CLKOUT2B (),\n .CLKOUT3 (),\n .CLKOUT3B (),\n .CLKOUT4 (),\n .CLKOUT5 (),\n .CLKOUT6 (),\n // Input clock control\n .CLKFBIN (mmcm_clkfbout),\n .CLKIN1 (clk_ref_ibufg),\n .CLKIN2 (1'b0),\n // Tied to always select the primary input clock\n .CLKINSEL (1'b1),\n // Ports for dynamic reconfiguration\n .DADDR (7'h0),\n .DCLK (1'b0),\n .DEN (1'b0),\n .DI (16'h0),\n .DO (),\n .DRDY (),\n .DWE (1'b0),\n // Ports for dynamic phase shift\n .PSCLK (1'b0),\n .PSEN (1'b0),\n .PSINCDEC (1'b0),\n .PSDONE (),\n // Other control and status signals\n .LOCKED (mmcm_Locked),\n .CLKINSTOPPED (),\n .CLKFBSTOPPED (),\n .PWRDWN (1'b0),\n .RST (sys_rst_act_hi));\n end\n endgenerate\n\n generate\n if (REF_CLK_MMCM_IODELAY_CTRL == \"TRUE\") begin : clk_ref_300_400_en\n if(FPGA_SPEED_GRADE == 1) begin: clk_ref_300\n BUFG u_bufg_clk_ref_300\n (\n .O (clk_ref[1]),\n .I (clk_ref_mmcm_300)\n );\n end else if (FPGA_SPEED_GRADE == 2 || FPGA_SPEED_GRADE == 3) begin: clk_ref_400\n BUFG u_bufg_clk_ref_400\n (\n .O (clk_ref[1]),\n .I (clk_ref_mmcm_400)\n );\n end\n end\n endgenerate\n\n generate\n if ((REFCLK_TYPE == \"DIFFERENTIAL\") || \n (REFCLK_TYPE == \"SINGLE_ENDED\") ||\n (REFCLK_TYPE == \"USE_SYSTEM_CLOCK\" && SYSCLK_TYPE != \"NO_BUFFER\")) begin: clk_ref_200\n BUFG u_bufg_clk_ref\n (\n .O (clk_ref[0]),\n .I (clk_ref_ibufg)\n );\n end else begin: clk_ref_200_no_buffer\n assign clk_ref[0] = clk_ref_i;\n end\n endgenerate\n\n //*****************************************************************\n // IDELAYCTRL reset\n // This assumes an external clock signal driving the IDELAYCTRL\n // blocks. Otherwise, if a PLL drives IDELAYCTRL, then the PLL\n // lock signal will need to be incorporated in this.\n //*****************************************************************\n\n // Add PLL lock if PLL drives IDELAYCTRL in user design\n assign rst_tmp_idelay = sys_rst_act_hi;\n\n generate\n if (REF_CLK_MMCM_IODELAY_CTRL == \"TRUE\") begin: rst_ref_gen_1\n always @(posedge clk_ref[1] or posedge rst_tmp_idelay)\n if (rst_tmp_idelay)\n rst_ref_sync_r[1] <= #TCQ {RST_SYNC_NUM{1'b1}};\n else\n rst_ref_sync_r[1] <= #TCQ rst_ref_sync_r[1] << 1;\n \n assign rst_ref[1] = rst_ref_sync_r[1][RST_SYNC_NUM-1];\n end\n endgenerate\n\n always @(posedge clk_ref[0] or posedge rst_tmp_idelay)\n if (rst_tmp_idelay)\n rst_ref_sync_r[0] <= #TCQ {RST_SYNC_NUM{1'b1}};\n else\n rst_ref_sync_r[0] <= #TCQ rst_ref_sync_r[0] << 1;\n\n assign rst_ref[0] = rst_ref_sync_r[0][RST_SYNC_NUM-1];\n\n //*****************************************************************\n\n generate\n if (REF_CLK_MMCM_IODELAY_CTRL == \"TRUE\") begin: idelayctrl_gen_1\n (* IODELAY_GROUP = IODELAY_GRP1 *) IDELAYCTRL u_idelayctrl_300_400\n (\n .RDY (iodelay_ctrl_rdy[1]),\n .REFCLK (clk_ref[1]),\n .RST (rst_ref[1])\n );\n end\n endgenerate\n\n (* IODELAY_GROUP = IODELAY_GRP0 *) IDELAYCTRL u_idelayctrl_200\n (\n .RDY (iodelay_ctrl_rdy[0]),\n .REFCLK (clk_ref[0]),\n .RST (rst_ref[0])\n );\n\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/clocking/mig_7series_v4_0_tempmon.v", "content": "//*****************************************************************************\n// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor : Xilinx\n// \\ \\ \\/ Version : %version\n// \\ \\ Application : MIG\n// / / Filename : mig_7series_v4_0_tempmon.v\n// /___/ /\\ Date Last Modified : $date$\n// \\ \\ / \\ Date Created : Jul 25 2012\n// \\___\\/\\___\\\n//\n//Device : 7 Series\n//Design Name : DDR3 SDRAM\n//Purpose : Monitors chip temperature via the XADC and adjusts the\n// stage 2 tap values as appropriate.\n//Reference :\n//Revision History :\n//*****************************************************************************\n\n`timescale 1 ps / 1 ps\n\nmodule mig_7series_v4_0_tempmon #\n(\n parameter TCQ = 100, // Register delay (sim only)\n parameter TEMP_MON_CONTROL = \"INTERNAL\", // XADC or user temperature source\n parameter XADC_CLK_PERIOD = 5000, // pS (default to 200 MHz refclk)\n parameter tTEMPSAMPLE = 10000000 // ps (10 us)\n)\n(\n input clk, // Fabric clock\n input xadc_clk,\n input rst, // System reset\n input [11:0] device_temp_i, // User device temperature\n output [11:0] device_temp // Sampled temperature\n);\n\n //***************************************************************************\n // Function cdiv\n // Description:\n // This function performs ceiling division (divide and round-up)\n // Inputs:\n // num: integer to be divided\n // div: divisor\n // Outputs:\n // cdiv: result of ceiling division (num/div, rounded up)\n //***************************************************************************\n\n function integer cdiv (input integer num, input integer div);\n begin\n // perform division, then add 1 if and only if remainder is non-zero\n cdiv = (num/div) + (((num%div)>0) ? 1 : 0);\n end\n endfunction // cdiv\n\n //***************************************************************************\n // Function clogb2\n // Description:\n // This function performs binary logarithm and rounds up\n // Inputs:\n // size: integer to perform binary log upon\n // Outputs:\n // clogb2: result of binary logarithm, rounded up\n //***************************************************************************\n\n function integer clogb2 (input integer size);\n begin\n\n size = size - 1;\n\n // increment clogb2 from 1 for each bit in size\n for (clogb2 = 1; size > 1; clogb2 = clogb2 + 1)\n size = size >> 1;\n\n end\n\n endfunction // clogb2\n\n // Synchronization registers\n (* ASYNC_REG = \"TRUE\" *) reg [11:0] device_temp_sync_r1;\n (* ASYNC_REG = \"TRUE\" *) reg [11:0] device_temp_sync_r2;\n (* ASYNC_REG = \"TRUE\" *) reg [11:0] device_temp_sync_r3 /* synthesis syn_srlstyle=\"registers\" */;\n (* ASYNC_REG = \"TRUE\" *) reg [11:0] device_temp_sync_r4;\n (* ASYNC_REG = \"TRUE\" *) reg [11:0] device_temp_sync_r5;\n\n // Output register\n (* ASYNC_REG = \"TRUE\" *) reg [11:0] device_temp_r;\n\n wire [11:0] device_temp_lcl;\n reg [3:0] sync_cntr = 4'b0000;\n reg device_temp_sync_r4_neq_r3;\n\n // (* ASYNC_REG = \"TRUE\" *) reg rst_r1;\n // (* ASYNC_REG = \"TRUE\" *) reg rst_r2;\n\n // // Synchronization rst to XADC clock domain\n // always @(posedge xadc_clk) begin\n // rst_r1 <= rst;\n // rst_r2 <= rst_r1;\n // end\n\n // Synchronization counter\n always @(posedge clk) begin\n\n device_temp_sync_r1 <= #TCQ device_temp_lcl;\n device_temp_sync_r2 <= #TCQ device_temp_sync_r1;\n device_temp_sync_r3 <= #TCQ device_temp_sync_r2;\n device_temp_sync_r4 <= #TCQ device_temp_sync_r3;\n device_temp_sync_r5 <= #TCQ device_temp_sync_r4;\n\n device_temp_sync_r4_neq_r3 <= #TCQ (device_temp_sync_r4 != device_temp_sync_r3) ? 1'b1 : 1'b0;\n\n end\n\n always @(posedge clk)\n if(rst || (device_temp_sync_r4_neq_r3))\n sync_cntr <= #TCQ 4'b0000;\n else if(~&sync_cntr)\n sync_cntr <= #TCQ sync_cntr + 4'b0001;\n\n always @(posedge clk)\n if(&sync_cntr)\n device_temp_r <= #TCQ device_temp_sync_r5;\n\n assign device_temp = device_temp_r;\n\n generate\n\n if(TEMP_MON_CONTROL == \"EXTERNAL\") begin : user_supplied_temperature\n\n assign device_temp_lcl = device_temp_i;\n\n end else begin : xadc_supplied_temperature\n\n // calculate polling timer width and limit\n localparam nTEMPSAMP = cdiv(tTEMPSAMPLE, XADC_CLK_PERIOD);\n localparam nTEMPSAMP_CLKS = nTEMPSAMP;\n localparam nTEMPSAMP_CLKS_M6 = nTEMPSAMP - 6;\n localparam nTEMPSAMP_CNTR_WIDTH = clogb2(nTEMPSAMP_CLKS);\n\n // Temperature sampler FSM encoding\n localparam INIT_IDLE = 2'b00;\n localparam REQUEST_READ_TEMP = 2'b01;\n localparam WAIT_FOR_READ = 2'b10;\n localparam READ = 2'b11;\n\n // polling timer and tick\n reg [nTEMPSAMP_CNTR_WIDTH-1:0] sample_timer = {nTEMPSAMP_CNTR_WIDTH{1'b0}};\n reg sample_timer_en = 1'b0;\n reg sample_timer_clr = 1'b0;\n reg sample_en = 1'b0;\n\n // Temperature sampler state\n reg [2:0] tempmon_state = INIT_IDLE;\n reg [2:0] tempmon_next_state = INIT_IDLE;\n\n // XADC interfacing\n reg xadc_den = 1'b0;\n wire xadc_drdy;\n wire [15:0] xadc_do;\n reg xadc_drdy_r = 1'b0;\n reg [15:0] xadc_do_r = 1'b0;\n\n // Temperature storage\n reg [11:0] temperature = 12'b0;\n\n // Reset sync\n (* ASYNC_REG = \"TRUE\" *) reg rst_r1;\n (* ASYNC_REG = \"TRUE\" *) reg rst_r2;\n \n // Synchronization rst to XADC clock domain\n always @(posedge xadc_clk) begin\n rst_r1 <= rst;\n rst_r2 <= rst_r1;\n end\n\n // XADC polling interval timer\n always @ (posedge xadc_clk)\n if(rst_r2 || sample_timer_clr)\n sample_timer <= #TCQ {nTEMPSAMP_CNTR_WIDTH{1'b0}};\n else if(sample_timer_en)\n sample_timer <= #TCQ sample_timer + 1'b1;\n\n // XADC sampler state transition\n always @(posedge xadc_clk)\n if(rst_r2)\n tempmon_state <= #TCQ INIT_IDLE;\n else\n tempmon_state <= #TCQ tempmon_next_state;\n\n // Sample enable\n always @(posedge xadc_clk)\n sample_en <= #TCQ (sample_timer == nTEMPSAMP_CLKS_M6) ? 1'b1 : 1'b0;\n\n // XADC sampler next state transition\n always @(tempmon_state or sample_en or xadc_drdy_r) begin\n\n tempmon_next_state = tempmon_state;\n\n case(tempmon_state)\n\n INIT_IDLE:\n if(sample_en)\n tempmon_next_state = REQUEST_READ_TEMP;\n\n REQUEST_READ_TEMP:\n tempmon_next_state = WAIT_FOR_READ;\n\n WAIT_FOR_READ:\n if(xadc_drdy_r)\n tempmon_next_state = READ;\n\n READ:\n tempmon_next_state = INIT_IDLE;\n\n default:\n tempmon_next_state = INIT_IDLE;\n\n endcase\n\n end\n\n // Sample timer clear\n always @(posedge xadc_clk)\n if(rst_r2 || (tempmon_state == WAIT_FOR_READ))\n sample_timer_clr <= #TCQ 1'b0;\n else if(tempmon_state == REQUEST_READ_TEMP)\n sample_timer_clr <= #TCQ 1'b1;\n\n // Sample timer enable\n always @(posedge xadc_clk)\n if(rst_r2 || (tempmon_state == REQUEST_READ_TEMP))\n sample_timer_en <= #TCQ 1'b0;\n else if((tempmon_state == INIT_IDLE) || (tempmon_state == READ))\n sample_timer_en <= #TCQ 1'b1;\n\n // XADC enable\n always @(posedge xadc_clk)\n if(rst_r2 || (tempmon_state == WAIT_FOR_READ))\n xadc_den <= #TCQ 1'b0;\n else if(tempmon_state == REQUEST_READ_TEMP)\n xadc_den <= #TCQ 1'b1;\n\n // Register XADC outputs\n always @(posedge xadc_clk)\n if(rst_r2) begin\n xadc_drdy_r <= #TCQ 1'b0;\n xadc_do_r <= #TCQ 16'b0;\n end\n else begin\n xadc_drdy_r <= #TCQ xadc_drdy;\n xadc_do_r <= #TCQ xadc_do;\n end\n\n // Store current read value\n always @(posedge xadc_clk)\n if(rst_r2)\n temperature <= #TCQ 12'b0;\n else if(tempmon_state == READ)\n temperature <= #TCQ xadc_do_r[15:4];\n\n assign device_temp_lcl = temperature;\n\n // XADC: Dual 12-Bit 1MSPS Analog-to-Digital Converter\n // 7 Series\n // Xilinx HDL Libraries Guide, version 14.1\n XADC #(\n // INIT_40 - INIT_42: XADC configuration registers\n .INIT_40(16'h1000), // config reg 0\n .INIT_41(16'h2fff), // config reg 1\n .INIT_42(16'h0800), // config reg 2\n // INIT_48 - INIT_4F: Sequence Registers\n .INIT_48(16'h0101), // Sequencer channel selection\n .INIT_49(16'h0000), // Sequencer channel selection\n .INIT_4A(16'h0100), // Sequencer Average selection\n .INIT_4B(16'h0000), // Sequencer Average selection\n .INIT_4C(16'h0000), // Sequencer Bipolar selection\n .INIT_4D(16'h0000), // Sequencer Bipolar selection\n .INIT_4E(16'h0000), // Sequencer Acq time selection\n .INIT_4F(16'h0000), // Sequencer Acq time selection\n // INIT_50 - INIT_58, INIT5C: Alarm Limit Registers\n .INIT_50(16'hb5ed), // Temp alarm trigger\n .INIT_51(16'h57e4), // Vccint upper alarm limit\n .INIT_52(16'ha147), // Vccaux upper alarm limit\n .INIT_53(16'hca33), // Temp alarm OT upper\n .INIT_54(16'ha93a), // Temp alarm reset\n .INIT_55(16'h52c6), // Vccint lower alarm limit\n .INIT_56(16'h9555), // Vccaux lower alarm limit\n .INIT_57(16'hae4e), // Temp alarm OT reset\n .INIT_58(16'h5999), // VBRAM upper alarm limit\n .INIT_5C(16'h5111), // VBRAM lower alarm limit\n // Simulation attributes: Set for proepr simulation behavior\n .SIM_DEVICE(\"7SERIES\") // Select target device (values)\n )\n XADC_inst (\n // ALARMS: 8-bit (each) output: ALM, OT\n .ALM(), // 8-bit output: Output alarm for temp, Vccint, Vccaux and Vccbram\n .OT(), // 1-bit output: Over-Temperature alarm\n // Dynamic Reconfiguration Port (DRP): 16-bit (each) output: Dynamic Reconfiguration Ports\n .DO(xadc_do), // 16-bit output: DRP output data bus\n .DRDY(xadc_drdy), // 1-bit output: DRP data ready\n // STATUS: 1-bit (each) output: XADC status ports\n .BUSY(), // 1-bit output: ADC busy output\n .CHANNEL(), // 5-bit output: Channel selection outputs\n .EOC(), // 1-bit output: End of Conversion\n .EOS(), // 1-bit output: End of Sequence\n .JTAGBUSY(), // 1-bit output: JTAG DRP transaction in progress output\n .JTAGLOCKED(), // 1-bit output: JTAG requested DRP port lock\n .JTAGMODIFIED(), // 1-bit output: JTAG Write to the DRP has occurred\n .MUXADDR(), // 5-bit output: External MUX channel decode\n // Auxiliary Analog-Input Pairs: 16-bit (each) input: VAUXP[15:0], VAUXN[15:0]\n .VAUXN(16'b0), // 16-bit input: N-side auxiliary analog input\n .VAUXP(16'b0), // 16-bit input: P-side auxiliary analog input\n // CONTROL and CLOCK: 1-bit (each) input: Reset, conversion start and clock inputs\n .CONVST(1'b0), // 1-bit input: Convert start input\n .CONVSTCLK(1'b0), // 1-bit input: Convert start input\n .RESET(1'b0), // 1-bit input: Active-high reset\n // Dedicated Analog Input Pair: 1-bit (each) input: VP/VN\n .VN(1'b0), // 1-bit input: N-side analog input\n .VP(1'b0), // 1-bit input: P-side analog input\n // Dynamic Reconfiguration Port (DRP): 7-bit (each) input: Dynamic Reconfiguration Ports\n .DADDR(7'b0), // 7-bit input: DRP address bus\n .DCLK(xadc_clk), // 1-bit input: DRP clock\n .DEN(xadc_den), // 1-bit input: DRP enable signal\n .DI(16'b0), // 16-bit input: DRP input data bus\n .DWE(1'b0) // 1-bit input: DRP write enable\n );\n\n // End of XADC_inst instantiation\n\n end\n\n endgenerate\n\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_arb_mux.v", "content": "//*****************************************************************************\n// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor : Xilinx\n// \\ \\ \\/ Version : %version\n// \\ \\ Application : MIG\n// / / Filename : arb_mux.v\n// /___/ /\\ Date Last Modified : $date$\n// \\ \\ / \\ Date Created : Tue Jun 30 2009\n// \\___\\/\\___\\\n//\n//Device : 7-Series\n//Design Name : DDR3 SDRAM\n//Purpose :\n//Reference :\n//Revision History :\n//*****************************************************************************\n\n\n`timescale 1ps/1ps\n\nmodule mig_7series_v4_0_arb_mux #\n (\n parameter TCQ = 100,\n parameter EVEN_CWL_2T_MODE = \"OFF\",\n parameter ADDR_CMD_MODE = \"1T\",\n parameter BANK_VECT_INDX = 11,\n parameter BANK_WIDTH = 3,\n parameter BURST_MODE = \"8\",\n parameter CS_WIDTH = 4,\n parameter CL = 5,\n parameter CWL = 5,\n parameter DATA_BUF_ADDR_VECT_INDX = 31,\n parameter DATA_BUF_ADDR_WIDTH = 8,\n parameter DRAM_TYPE = \"DDR3\",\n parameter CKE_ODT_AUX = \"FALSE\", //Parameter to turn on/off the aux_out signal\n parameter EARLY_WR_DATA_ADDR = \"OFF\",\n parameter ECC = \"OFF\",\n parameter nBANK_MACHS = 4,\n parameter nCK_PER_CLK = 2, // # DRAM CKs per fabric CLKs\n parameter nCS_PER_RANK = 1,\n parameter nRAS = 37500, // ACT->PRE cmd period (CKs)\n parameter nRCD = 12500, // ACT->R/W delay (CKs)\n parameter nSLOTS = 2,\n parameter nWR = 6, // Write recovery (CKs)\n parameter RANKS = 1,\n parameter RANK_VECT_INDX = 15,\n parameter RANK_WIDTH = 2,\n parameter ROW_VECT_INDX = 63,\n parameter ROW_WIDTH = 16,\n parameter RTT_NOM = \"40\",\n parameter RTT_WR = \"120\",\n parameter SLOT_0_CONFIG = 8'b0000_0101,\n parameter SLOT_1_CONFIG = 8'b0000_1010\n )\n (/*AUTOARG*/\n // Outputs\n output [ROW_WIDTH-1:0] col_a, // From arb_select0 of arb_select.v\n output [BANK_WIDTH-1:0] col_ba, // From arb_select0 of arb_select.v\n output [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr,// From arb_select0 of arb_select.v\n output col_periodic_rd, // From arb_select0 of arb_select.v\n output [RANK_WIDTH-1:0] col_ra, // From arb_select0 of arb_select.v\n output col_rmw, // From arb_select0 of arb_select.v\n output col_rd_wr,\n output [ROW_WIDTH-1:0] col_row, // From arb_select0 of arb_select.v\n output col_size, // From arb_select0 of arb_select.v\n output [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr,// From arb_select0 of arb_select.v\n output wire [nCK_PER_CLK-1:0] mc_ras_n,\n output wire [nCK_PER_CLK-1:0] mc_cas_n,\n output wire [nCK_PER_CLK-1:0] mc_we_n,\n output wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address,\n output wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank,\n output wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n,\n output wire [1:0] mc_odt,\n output wire [nCK_PER_CLK-1:0] mc_cke,\n output wire [3:0] mc_aux_out0,\n output wire [3:0] mc_aux_out1,\n output [2:0] mc_cmd,\n output [5:0] mc_data_offset,\n output [5:0] mc_data_offset_1,\n output [5:0] mc_data_offset_2,\n output [1:0] mc_cas_slot,\n output [RANK_WIDTH-1:0] rnk_config, // From arb_select0 of arb_select.v\n output rnk_config_valid_r, // From arb_row_col0 of arb_row_col.v\n output [nBANK_MACHS-1:0] sending_row, // From arb_row_col0 of arb_row_col.v\n output [nBANK_MACHS-1:0] sending_pre,\n output sent_col, // From arb_row_col0 of arb_row_col.v\n output sent_col_r, // From arb_row_col0 of arb_row_col.v\n output sent_row, // From arb_row_col0 of arb_row_col.v\n output [nBANK_MACHS-1:0] sending_col,\n output rnk_config_strobe,\n output insert_maint_r1,\n output rnk_config_kill_rts_col,\n\n // Inputs\n input clk,\n input rst,\n input init_calib_complete,\n input [6*RANKS-1:0] calib_rddata_offset,\n input [6*RANKS-1:0] calib_rddata_offset_1,\n input [6*RANKS-1:0] calib_rddata_offset_2,\n input [ROW_VECT_INDX:0] col_addr, // To arb_select0 of arb_select.v\n input [nBANK_MACHS-1:0] col_rdy_wr, // To arb_row_col0 of arb_row_col.v\n input insert_maint_r, // To arb_row_col0 of arb_row_col.v\n input [RANK_WIDTH-1:0] maint_rank_r, // To arb_select0 of arb_select.v\n input maint_zq_r, // To arb_select0 of arb_select.v\n input maint_sre_r, // To arb_select0 of arb_select.v\n input maint_srx_r, // To arb_select0 of arb_select.v\n input [nBANK_MACHS-1:0] rd_wr_r, // To arb_select0 of arb_select.v\n input [BANK_VECT_INDX:0] req_bank_r, // To arb_select0 of arb_select.v\n input [nBANK_MACHS-1:0] req_cas, // To arb_select0 of arb_select.v\n input [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r,// To arb_select0 of arb_select.v\n input [nBANK_MACHS-1:0] req_periodic_rd_r, // To arb_select0 of arb_select.v\n input [RANK_VECT_INDX:0] req_rank_r, // To arb_select0 of arb_select.v\n input [nBANK_MACHS-1:0] req_ras, // To arb_select0 of arb_select.v\n input [ROW_VECT_INDX:0] req_row_r, // To arb_select0 of arb_select.v\n input [nBANK_MACHS-1:0] req_size_r, // To arb_select0 of arb_select.v\n input [nBANK_MACHS-1:0] req_wr_r, // To arb_select0 of arb_select.v\n input [ROW_VECT_INDX:0] row_addr, // To arb_select0 of arb_select.v\n input [nBANK_MACHS-1:0] row_cmd_wr, // To arb_select0 of arb_select.v\n input [nBANK_MACHS-1:0] rtc, // To arb_row_col0 of arb_row_col.v\n input [nBANK_MACHS-1:0] rts_col, // To arb_row_col0 of arb_row_col.v\n input [nBANK_MACHS-1:0] rts_row, // To arb_row_col0 of arb_row_col.v\n input [nBANK_MACHS-1:0] rts_pre, // To arb_row_col0 of arb_row_col.v\n input [7:0] slot_0_present, // To arb_select0 of arb_select.v\n input [7:0] slot_1_present // To arb_select0 of arb_select.v\n \n );\n\n /*AUTOINPUT*/\n // Beginning of automatic inputs (from unused autoinst inputs)\n // End of automatics\n\n /*AUTOOUTPUT*/\n // Beginning of automatic outputs (from unused autoinst outputs)\n \n // End of automatics\n\n /*AUTOWIRE*/\n // Beginning of automatic wires (for undeclared instantiated-module outputs)\n wire cs_en0; // From arb_row_col0 of arb_row_col.v\n wire cs_en1; // From arb_row_col0 of arb_row_col.v\n wire [nBANK_MACHS-1:0] grant_col_r; // From arb_row_col0 of arb_row_col.v\n wire [nBANK_MACHS-1:0] grant_col_wr; // From arb_row_col0 of arb_row_col.v\n wire [nBANK_MACHS-1:0] grant_config_r; // From arb_row_col0 of arb_row_col.v\n wire [nBANK_MACHS-1:0] grant_row_r; // From arb_row_col0 of arb_row_col.v\n wire [nBANK_MACHS-1:0] grant_pre_r; // From arb_row_col0 of arb_row_col.v\n wire send_cmd0_row; // From arb_row_col0 of arb_row_col.v\n wire send_cmd0_col; // From arb_row_col0 of arb_row_col.v\n wire send_cmd1_row; // From arb_row_col0 of arb_row_col.v\n wire send_cmd1_col;\n wire send_cmd2_row;\n wire send_cmd2_col;\n wire send_cmd2_pre;\n wire send_cmd3_col;\n wire [5:0] col_channel_offset;\n // End of automatics\n\n wire sent_col_i;\n wire cs_en2;\n wire cs_en3;\n assign sent_col = sent_col_i;\n \n mig_7series_v4_0_arb_row_col #\n (/*AUTOINSTPARAM*/\n // Parameters\n .TCQ (TCQ),\n .ADDR_CMD_MODE (ADDR_CMD_MODE),\n .CWL (CWL),\n .EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),\n .nBANK_MACHS (nBANK_MACHS),\n .nCK_PER_CLK (nCK_PER_CLK),\n .nRAS (nRAS),\n .nRCD (nRCD),\n .nWR (nWR))\n arb_row_col0\n (/*AUTOINST*/\n // Outputs\n .grant_row_r (grant_row_r[nBANK_MACHS-1:0]),\n .grant_pre_r (grant_pre_r[nBANK_MACHS-1:0]),\n .sent_row (sent_row),\n .sending_row (sending_row[nBANK_MACHS-1:0]),\n .sending_pre (sending_pre[nBANK_MACHS-1:0]),\n .grant_config_r (grant_config_r[nBANK_MACHS-1:0]),\n .rnk_config_strobe (rnk_config_strobe),\n .rnk_config_kill_rts_col (rnk_config_kill_rts_col),\n .rnk_config_valid_r (rnk_config_valid_r),\n .grant_col_r (grant_col_r[nBANK_MACHS-1:0]),\n .sending_col (sending_col[nBANK_MACHS-1:0]),\n .sent_col (sent_col_i),\n .sent_col_r (sent_col_r),\n .grant_col_wr (grant_col_wr[nBANK_MACHS-1:0]),\n .send_cmd0_row (send_cmd0_row),\n .send_cmd0_col (send_cmd0_col),\n .send_cmd1_row (send_cmd1_row),\n .send_cmd1_col (send_cmd1_col),\n .send_cmd2_row (send_cmd2_row),\n .send_cmd2_col (send_cmd2_col),\n .send_cmd2_pre (send_cmd2_pre),\n .send_cmd3_col (send_cmd3_col),\n .col_channel_offset (col_channel_offset),\n .cs_en0 (cs_en0),\n .cs_en1 (cs_en1),\n .cs_en2 (cs_en2),\n .cs_en3 (cs_en3),\n .insert_maint_r1 (insert_maint_r1),\n // Inputs\n .clk (clk),\n .rst (rst),\n .rts_row (rts_row[nBANK_MACHS-1:0]),\n .rts_pre (rts_pre[nBANK_MACHS-1:0]),\n .insert_maint_r (insert_maint_r),\n .rts_col (rts_col[nBANK_MACHS-1:0]),\n .rtc (rtc[nBANK_MACHS-1:0]),\n .col_rdy_wr (col_rdy_wr[nBANK_MACHS-1:0]));\n\n mig_7series_v4_0_arb_select #\n (/*AUTOINSTPARAM*/\n // Parameters\n .TCQ (TCQ),\n .EVEN_CWL_2T_MODE (EVEN_CWL_2T_MODE),\n .ADDR_CMD_MODE (ADDR_CMD_MODE),\n .BANK_VECT_INDX (BANK_VECT_INDX),\n .BANK_WIDTH (BANK_WIDTH),\n .BURST_MODE (BURST_MODE),\n .CS_WIDTH (CS_WIDTH),\n .CL (CL),\n .CWL (CWL),\n .DATA_BUF_ADDR_VECT_INDX (DATA_BUF_ADDR_VECT_INDX),\n .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),\n .DRAM_TYPE (DRAM_TYPE),\n .EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),\n .ECC (ECC),\n .CKE_ODT_AUX (CKE_ODT_AUX),\n .nBANK_MACHS (nBANK_MACHS),\n .nCK_PER_CLK (nCK_PER_CLK),\n .nCS_PER_RANK (nCS_PER_RANK),\n .nSLOTS (nSLOTS),\n .RANKS (RANKS),\n .RANK_VECT_INDX (RANK_VECT_INDX),\n .RANK_WIDTH (RANK_WIDTH),\n .ROW_VECT_INDX (ROW_VECT_INDX),\n .ROW_WIDTH (ROW_WIDTH),\n .RTT_NOM (RTT_NOM),\n .RTT_WR (RTT_WR),\n .SLOT_0_CONFIG (SLOT_0_CONFIG),\n .SLOT_1_CONFIG (SLOT_1_CONFIG))\n arb_select0\n (/*AUTOINST*/\n // Outputs\n .col_periodic_rd (col_periodic_rd),\n .col_ra (col_ra[RANK_WIDTH-1:0]),\n .col_ba (col_ba[BANK_WIDTH-1:0]),\n .col_a (col_a[ROW_WIDTH-1:0]),\n .col_rmw (col_rmw),\n .col_rd_wr (col_rd_wr),\n .col_size (col_size),\n .col_row (col_row[ROW_WIDTH-1:0]),\n .col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),\n .col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),\n .mc_bank (mc_bank),\n .mc_address (mc_address),\n .mc_ras_n (mc_ras_n),\n .mc_cas_n (mc_cas_n),\n .mc_we_n (mc_we_n),\n .mc_cs_n (mc_cs_n),\n .mc_odt (mc_odt),\n .mc_cke (mc_cke),\n .mc_aux_out0 (mc_aux_out0),\n .mc_aux_out1 (mc_aux_out1),\n .mc_cmd (mc_cmd),\n .mc_data_offset (mc_data_offset),\n .mc_data_offset_1 (mc_data_offset_1),\n .mc_data_offset_2 (mc_data_offset_2),\n .mc_cas_slot (mc_cas_slot),\n .col_channel_offset (col_channel_offset),\n .rnk_config (rnk_config),\n // Inputs\n .clk (clk),\n .rst (rst),\n .init_calib_complete (init_calib_complete),\n .calib_rddata_offset (calib_rddata_offset),\n .calib_rddata_offset_1 (calib_rddata_offset_1),\n .calib_rddata_offset_2 (calib_rddata_offset_2),\n .req_rank_r (req_rank_r[RANK_VECT_INDX:0]),\n .req_bank_r (req_bank_r[BANK_VECT_INDX:0]),\n .req_ras (req_ras[nBANK_MACHS-1:0]),\n .req_cas (req_cas[nBANK_MACHS-1:0]),\n .req_wr_r (req_wr_r[nBANK_MACHS-1:0]),\n .grant_row_r (grant_row_r[nBANK_MACHS-1:0]),\n .grant_pre_r (grant_pre_r[nBANK_MACHS-1:0]),\n .row_addr (row_addr[ROW_VECT_INDX:0]),\n .row_cmd_wr (row_cmd_wr[nBANK_MACHS-1:0]),\n .insert_maint_r1 (insert_maint_r1),\n .maint_zq_r (maint_zq_r),\n .maint_sre_r (maint_sre_r),\n .maint_srx_r (maint_srx_r),\n .maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),\n .req_periodic_rd_r (req_periodic_rd_r[nBANK_MACHS-1:0]),\n .req_size_r (req_size_r[nBANK_MACHS-1:0]),\n .rd_wr_r (rd_wr_r[nBANK_MACHS-1:0]),\n .req_row_r (req_row_r[ROW_VECT_INDX:0]),\n .col_addr (col_addr[ROW_VECT_INDX:0]),\n .req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_VECT_INDX:0]),\n .grant_col_r (grant_col_r[nBANK_MACHS-1:0]),\n .grant_col_wr (grant_col_wr[nBANK_MACHS-1:0]),\n .send_cmd0_row (send_cmd0_row),\n .send_cmd0_col (send_cmd0_col),\n .send_cmd1_row (send_cmd1_row),\n .send_cmd1_col (send_cmd1_col),\n .send_cmd2_row (send_cmd2_row),\n .send_cmd2_col (send_cmd2_col),\n .send_cmd2_pre (send_cmd2_pre),\n .send_cmd3_col (send_cmd3_col),\n .sent_col (EVEN_CWL_2T_MODE == \"ON\" ? sent_col_r : sent_col),\n .cs_en0 (cs_en0),\n .cs_en1 (cs_en1),\n .cs_en2 (cs_en2),\n .cs_en3 (cs_en3),\n .grant_config_r (grant_config_r[nBANK_MACHS-1:0]),\n .rnk_config_strobe (rnk_config_strobe),\n .slot_0_present (slot_0_present[7:0]),\n .slot_1_present (slot_1_present[7:0]));\n\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_arb_row_col.v", "content": "//*****************************************************************************\n// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor : Xilinx\n// \\ \\ \\/ Version : %version\n// \\ \\ Application : MIG\n// / / Filename : arb_row_col.v\n// /___/ /\\ Date Last Modified : $date$\n// \\ \\ / \\ Date Created : Tue Jun 30 2009\n// \\___\\/\\___\\\n//\n//Device : 7-Series\n//Design Name : DDR3 SDRAM\n//Purpose :\n//Reference :\n//Revision History :\n//*****************************************************************************\n\n\n// This block receives request to send row and column commands. These requests\n// come the individual bank machines. The arbitration winner is selected\n// and driven back to the bank machines.\n//\n// The CS enables are generated. For 2:1 mode, row commands are sent\n// in the \"0\" phase, and column commands are sent in the \"1\" phase.\n//\n// In 2T mode, a further arbitration is performed between the row\n// and column commands. The winner of this arbitration inhibits\n// arbitration by the loser. The winner is allowed to arbitrate, the loser is\n// blocked until the next state. The winning address command\n// is repeated on both the \"0\" and the \"1\" phases and the CS\n// is asserted for just the \"1\" phase.\n\n`timescale 1 ps / 1 ps\n\nmodule mig_7series_v4_0_arb_row_col #\n (\n parameter TCQ = 100,\n parameter ADDR_CMD_MODE = \"1T\",\n parameter CWL = 5,\n parameter EARLY_WR_DATA_ADDR = \"OFF\",\n parameter nBANK_MACHS = 4,\n parameter nCK_PER_CLK = 2,\n parameter nRAS = 37500, // ACT->PRE cmd period (CKs)\n parameter nRCD = 12500, // ACT->R/W delay (CKs)\n parameter nWR = 6 // Write recovery (CKs)\n )\n (/*AUTOARG*/\n // Outputs\n grant_row_r, grant_pre_r, sent_row, sending_row, sending_pre, grant_config_r,\n rnk_config_strobe, rnk_config_valid_r, grant_col_r,\n sending_col, sent_col, sent_col_r, grant_col_wr, send_cmd0_row, send_cmd0_col,\n send_cmd1_row, send_cmd1_col, send_cmd2_row, send_cmd2_col, send_cmd2_pre,\n send_cmd3_col, col_channel_offset, cs_en0, cs_en1, cs_en2, cs_en3,\n insert_maint_r1, rnk_config_kill_rts_col,\n // Inputs\n clk, rst, rts_row, rts_pre, insert_maint_r, rts_col, rtc, col_rdy_wr\n );\n\n // Create a delay when switching ranks\n localparam RNK2RNK_DLY = 12;\n localparam RNK2RNK_DLY_CLKS =\n (RNK2RNK_DLY / nCK_PER_CLK) + (RNK2RNK_DLY % nCK_PER_CLK ? 1 : 0);\n \n input clk;\n input rst;\n\n input [nBANK_MACHS-1:0] rts_row;\n input insert_maint_r;\n input [nBANK_MACHS-1:0] rts_col;\n reg [RNK2RNK_DLY_CLKS-1:0] rnk_config_strobe_r;\n wire block_grant_row;\n wire block_grant_col;\n wire rnk_config_kill_rts_col_lcl =\n RNK2RNK_DLY_CLKS > 0 ? |rnk_config_strobe_r : 1'b0;\n\n output rnk_config_kill_rts_col;\n assign rnk_config_kill_rts_col = rnk_config_kill_rts_col_lcl;\n\n wire [nBANK_MACHS-1:0] col_request;\n wire granted_col_ns = |col_request;\n wire [nBANK_MACHS-1:0] row_request =\n rts_row & {nBANK_MACHS{~insert_maint_r}};\n wire granted_row_ns = |row_request;\n generate\n if (ADDR_CMD_MODE == \"2T\" && nCK_PER_CLK != 4) begin : row_col_2T_arb\n assign col_request =\n rts_col & {nBANK_MACHS{~(rnk_config_kill_rts_col_lcl || insert_maint_r)}};\n// Give column command priority whenever previous state has no row request.\n wire [1:0] row_col_grant;\n wire [1:0] current_master = ~granted_row_ns ? 2'b10 : row_col_grant;\n wire upd_last_master = ~granted_row_ns || |row_col_grant;\n mig_7series_v4_0_round_robin_arb #\n (.WIDTH (2))\n row_col_arb0\n (.grant_ns (),\n .grant_r (row_col_grant),\n .upd_last_master (upd_last_master),\n .current_master (current_master),\n .clk (clk),\n .rst (rst),\n .req ({granted_row_ns, granted_col_ns}),\n .disable_grant (1'b0));\n assign {block_grant_col, block_grant_row} = row_col_grant;\n end\n else begin : row_col_1T_arb\n assign col_request = rts_col & {nBANK_MACHS{~rnk_config_kill_rts_col_lcl}};\n assign block_grant_row = 1'b0;\n assign block_grant_col = 1'b0;\n end\n endgenerate\n\n// Row address/command arbitration.\n wire[nBANK_MACHS-1:0] grant_row_r_lcl;\n output wire[nBANK_MACHS-1:0] grant_row_r;\n assign grant_row_r = grant_row_r_lcl;\n reg granted_row_r;\n always @(posedge clk) granted_row_r <= #TCQ granted_row_ns;\n wire sent_row_lcl = granted_row_r && ~block_grant_row;\n output wire sent_row;\n assign sent_row = sent_row_lcl;\n mig_7series_v4_0_round_robin_arb #\n (.WIDTH (nBANK_MACHS))\n row_arb0\n (.grant_ns (),\n .grant_r (grant_row_r_lcl[nBANK_MACHS-1:0]),\n .upd_last_master (sent_row_lcl),\n .current_master (grant_row_r_lcl[nBANK_MACHS-1:0]),\n .clk (clk),\n .rst (rst),\n .req (row_request),\n .disable_grant (1'b0));\n\n output wire [nBANK_MACHS-1:0] sending_row;\n assign sending_row = grant_row_r_lcl & {nBANK_MACHS{~block_grant_row}};\n\n // Precharge arbitration for 4:1 mode\n input [nBANK_MACHS-1:0] rts_pre;\n output wire[nBANK_MACHS-1:0] grant_pre_r;\n output wire [nBANK_MACHS-1:0] sending_pre;\n wire sent_pre_lcl;\n\n generate\n \n if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != \"2T\")) begin : pre_4_1_1T_arb\n \n reg granted_pre_r;\n wire[nBANK_MACHS-1:0] grant_pre_r_lcl;\n\n wire granted_pre_ns = |rts_pre;\n assign grant_pre_r = grant_pre_r_lcl;\n always @(posedge clk) granted_pre_r <= #TCQ granted_pre_ns;\n assign sent_pre_lcl = granted_pre_r;\n assign sending_pre = grant_pre_r_lcl;\n\n mig_7series_v4_0_round_robin_arb #\n (.WIDTH (nBANK_MACHS))\n pre_arb0\n (.grant_ns (),\n .grant_r (grant_pre_r_lcl[nBANK_MACHS-1:0]),\n .upd_last_master (sent_pre_lcl),\n .current_master (grant_pre_r_lcl[nBANK_MACHS-1:0]),\n .clk (clk),\n .rst (rst),\n .req (rts_pre),\n .disable_grant (1'b0));\n\n end\n\n endgenerate\n\n`ifdef MC_SVA\n all_bank_machines_row_arb:\n cover property (@(posedge clk) (~rst && &rts_row));\n`endif\n\n// Rank config arbitration.\n input [nBANK_MACHS-1:0] rtc;\n wire [nBANK_MACHS-1:0] grant_config_r_lcl;\n output wire [nBANK_MACHS-1:0] grant_config_r;\n assign grant_config_r = grant_config_r_lcl;\n wire upd_rnk_config_last_master;\n mig_7series_v4_0_round_robin_arb #\n (.WIDTH (nBANK_MACHS))\n config_arb0\n (.grant_ns (),\n .grant_r (grant_config_r_lcl[nBANK_MACHS-1:0]),\n .upd_last_master (upd_rnk_config_last_master),\n .current_master (grant_config_r_lcl[nBANK_MACHS-1:0]),\n .clk (clk),\n .rst (rst),\n .req (rtc[nBANK_MACHS-1:0]),\n .disable_grant (1'b0));\n\n`ifdef MC_SVA\n all_bank_machines_config_arb: cover property (@(posedge clk) (~rst && &rtc));\n`endif\n\n wire rnk_config_strobe_ns = ~rnk_config_strobe_r[0] && |rtc && ~granted_col_ns;\n always @(posedge clk) rnk_config_strobe_r[0] <= #TCQ rnk_config_strobe_ns;\n \n genvar i;\n generate\n for(i = 1; i < RNK2RNK_DLY_CLKS; i = i + 1)\n always @(posedge clk)\n rnk_config_strobe_r[i] <= #TCQ rnk_config_strobe_r[i-1];\n endgenerate\n\n output wire rnk_config_strobe;\n assign rnk_config_strobe = rnk_config_strobe_r[0];\n \n assign upd_rnk_config_last_master = rnk_config_strobe_r[0];\n\n// Generate rnk_config_valid.\n reg rnk_config_valid_r_lcl;\n wire rnk_config_valid_ns;\n assign rnk_config_valid_ns =\n ~rst && (rnk_config_valid_r_lcl || rnk_config_strobe_ns);\n always @(posedge clk) rnk_config_valid_r_lcl <= #TCQ rnk_config_valid_ns;\n output wire rnk_config_valid_r;\n assign rnk_config_valid_r = rnk_config_valid_r_lcl;\n\n// Column address/command arbitration.\n wire [nBANK_MACHS-1:0] grant_col_r_lcl;\n output wire [nBANK_MACHS-1:0] grant_col_r;\n assign grant_col_r = grant_col_r_lcl;\n reg granted_col_r;\n always @(posedge clk) granted_col_r <= #TCQ granted_col_ns;\n wire sent_col_lcl;\n mig_7series_v4_0_round_robin_arb #\n (.WIDTH (nBANK_MACHS))\n col_arb0\n (.grant_ns (),\n .grant_r (grant_col_r_lcl[nBANK_MACHS-1:0]),\n .upd_last_master (sent_col_lcl),\n .current_master (grant_col_r_lcl[nBANK_MACHS-1:0]),\n .clk (clk),\n .rst (rst),\n .req (col_request),\n .disable_grant (1'b0));\n\n`ifdef MC_SVA\n all_bank_machines_col_arb:\n cover property (@(posedge clk) (~rst && &rts_col));\n`endif\n\n output wire [nBANK_MACHS-1:0] sending_col;\n assign sending_col = grant_col_r_lcl & {nBANK_MACHS{~block_grant_col}};\n assign sent_col_lcl = granted_col_r && ~block_grant_col;\n reg sent_col_lcl_r = 1'b0;\n always @(posedge clk) sent_col_lcl_r <= #TCQ sent_col_lcl;\n output wire sent_col;\n assign sent_col = sent_col_lcl;\n output wire sent_col_r;\n assign sent_col_r = sent_col_lcl_r;\n\n // If we need early wr_data_addr because ECC is on, arbitrate\n // to see which bank machine might sent the next wr_data_addr;\n input [nBANK_MACHS-1:0] col_rdy_wr;\n output wire [nBANK_MACHS-1:0] grant_col_wr;\n generate\n if (EARLY_WR_DATA_ADDR == \"OFF\") begin : early_wr_addr_arb_off\n assign grant_col_wr = {nBANK_MACHS{1'b0}};\n end\n else begin : early_wr_addr_arb_on\n wire [nBANK_MACHS-1:0] grant_col_wr_raw;\n mig_7series_v4_0_round_robin_arb #\n (.WIDTH (nBANK_MACHS))\n col_arb0\n (.grant_ns (grant_col_wr_raw),\n .grant_r (),\n .upd_last_master (sent_col_lcl),\n .current_master (grant_col_r_lcl[nBANK_MACHS-1:0]),\n .clk (clk),\n .rst (rst),\n .req (col_rdy_wr),\n .disable_grant (1'b0));\n reg [nBANK_MACHS-1:0] grant_col_wr_r;\n wire [nBANK_MACHS-1:0] grant_col_wr_ns = granted_col_ns\n ? grant_col_wr_raw\n : grant_col_wr_r;\n always @(posedge clk) grant_col_wr_r <= #TCQ grant_col_wr_ns;\n assign grant_col_wr = grant_col_wr_ns;\n end // block: early_wr_addr_arb_on\n endgenerate\n\n output reg send_cmd0_row = 1'b0;\n output reg send_cmd0_col = 1'b0;\n output reg send_cmd1_row = 1'b0;\n output reg send_cmd1_col = 1'b0;\n output reg send_cmd2_row = 1'b0;\n output reg send_cmd2_col = 1'b0;\n output reg send_cmd2_pre = 1'b0;\n output reg send_cmd3_col = 1'b0;\n\n output reg cs_en0 = 1'b0;\n output reg cs_en1 = 1'b0;\n output reg cs_en2 = 1'b0;\n output reg cs_en3 = 1'b0;\n \n output wire [5:0] col_channel_offset;\n\n reg insert_maint_r1_lcl;\n always @(posedge clk) insert_maint_r1_lcl <= #TCQ insert_maint_r;\n output wire insert_maint_r1;\n assign insert_maint_r1 = insert_maint_r1_lcl;\n\n wire sent_row_or_maint = sent_row_lcl || insert_maint_r1_lcl;\n reg sent_row_or_maint_r = 1'b0;\n always @(posedge clk) sent_row_or_maint_r <= #TCQ sent_row_or_maint;\n generate\n case ({(nCK_PER_CLK == 4), (nCK_PER_CLK == 2), (ADDR_CMD_MODE == \"2T\")})\n 3'b000 : begin : one_one_not2T\n end\n 3'b001 : begin : one_one_2T\n end\n 3'b010 : begin : two_one_not2T\n\n if(!(CWL % 2)) begin // Place column commands on slot 0 for even CWL\n\n always @(sent_col_lcl) begin\n cs_en0 = sent_col_lcl;\n send_cmd0_col = sent_col_lcl;\n end\n\n always @(sent_row_or_maint) begin\n cs_en1 = sent_row_or_maint;\n send_cmd1_row = sent_row_or_maint;\n end\n\n assign col_channel_offset = 0;\n\n end\n \n else begin // Place column commands on slot 1 for odd CWL\n\n always @(sent_row_or_maint) begin \n cs_en0 = sent_row_or_maint;\n send_cmd0_row = sent_row_or_maint;\n end\n \n always @(sent_col_lcl) begin \n cs_en1 = sent_col_lcl;\n send_cmd1_col = sent_col_lcl;\n end\n \n assign col_channel_offset = 1;\n\n end\n\n end\n 3'b011 : begin : two_one_2T\n\n if(!(CWL % 2)) begin // Place column commands on slot 1->0 for even CWL\n \n always @(sent_row_or_maint_r or sent_col_lcl_r)\n cs_en0 = sent_row_or_maint_r || sent_col_lcl_r;\n\n always @(sent_row_or_maint or sent_row_or_maint_r) begin\n send_cmd0_row = sent_row_or_maint_r;\n send_cmd1_row = sent_row_or_maint;\n end\n \n always @(sent_col_lcl or sent_col_lcl_r) begin\n send_cmd0_col = sent_col_lcl_r;\n send_cmd1_col = sent_col_lcl;\n end\n\n assign col_channel_offset = 0;\n\n end\n \n else begin // Place column commands on slot 0->1 for odd CWL\n \n always @(sent_col_lcl or sent_row_or_maint)\n cs_en1 = sent_row_or_maint || sent_col_lcl;\n\n always @(sent_row_or_maint) begin\n send_cmd0_row = sent_row_or_maint;\n send_cmd1_row = sent_row_or_maint;\n end\n \n always @(sent_col_lcl) begin\n send_cmd0_col = sent_col_lcl;\n send_cmd1_col = sent_col_lcl;\n end\n\n assign col_channel_offset = 1;\n \n end\n \n end\n 3'b100 : begin : four_one_not2T\n\n if(!(CWL % 2)) begin // Place column commands on slot 0 for even CWL\n\n always @(sent_col_lcl) begin\n cs_en0 = sent_col_lcl;\n send_cmd0_col = sent_col_lcl;\n end\n\n always @(sent_row_or_maint) begin\n cs_en1 = sent_row_or_maint;\n send_cmd1_row = sent_row_or_maint;\n end\n \n assign col_channel_offset = 0;\n \n end\n\n else begin // Place column commands on slot 1 for odd CWL\n \n always @(sent_row_or_maint) begin\n cs_en0 = sent_row_or_maint;\n send_cmd0_row = sent_row_or_maint;\n end\n \n always @(sent_col_lcl) begin\n cs_en1 = sent_col_lcl;\n send_cmd1_col = sent_col_lcl;\n end\n \n assign col_channel_offset = 1;\n \n end\n\n always @(sent_pre_lcl) begin\n cs_en2 = sent_pre_lcl;\n send_cmd2_pre = sent_pre_lcl;\n end\n\n end\n 3'b101 : begin : four_one_2T\n\n if(!(CWL % 2)) begin // Place column commands on slot 3->0 for even CWL\n \n always @(sent_col_lcl or sent_col_lcl_r) begin\n cs_en0 = sent_col_lcl_r;\n send_cmd0_col = sent_col_lcl_r;\n send_cmd3_col = sent_col_lcl;\n end\n \n always @(sent_row_or_maint) begin\n cs_en2 = sent_row_or_maint;\n send_cmd1_row = sent_row_or_maint;\n send_cmd2_row = sent_row_or_maint;\n end\n\n assign col_channel_offset = 0;\n \n end\n \n else begin // Place column commands on slot 2->3 for odd CWL\n \n always @(sent_row_or_maint) begin\n cs_en1 = sent_row_or_maint;\n send_cmd0_row = sent_row_or_maint;\n send_cmd1_row = sent_row_or_maint;\n end\n\n always @(sent_col_lcl) begin\n cs_en3 = sent_col_lcl;\n send_cmd2_col = sent_col_lcl;\n send_cmd3_col = sent_col_lcl;\n end\n\n assign col_channel_offset = 3;\n \n end\n\n end\n endcase\n endgenerate\n\n\n\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_arb_select.v", "content": "//*****************************************************************************\n// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor : Xilinx\n// \\ \\ \\/ Version : %version\n// \\ \\ Application : MIG\n// / / Filename : arb_select.v\n// /___/ /\\ Date Last Modified : $date$\n// \\ \\ / \\ Date Created : Tue Jun 30 2009\n// \\___\\/\\___\\\n//\n//Device : 7-Series\n//Design Name : DDR3 SDRAM\n//Purpose :\n//Reference :\n//Revision History :\n//*****************************************************************************\n\n// Based on granta_r and grantc_r, this module selects a\n// row and column command from the request information\n// provided by the bank machines.\n//\n// Depending on address mode configuration, nCL and nCWL, a column\n// command pipeline of up to three states will be created.\n\n`timescale 1 ps / 1 ps\n\nmodule mig_7series_v4_0_arb_select #\n (\n parameter TCQ = 100,\n parameter EVEN_CWL_2T_MODE = \"OFF\",\n parameter ADDR_CMD_MODE = \"1T\",\n parameter BANK_VECT_INDX = 11,\n parameter BANK_WIDTH = 3,\n parameter BURST_MODE = \"8\",\n parameter CS_WIDTH = 4,\n parameter CL = 5,\n parameter CWL = 5,\n parameter DATA_BUF_ADDR_VECT_INDX = 31,\n parameter DATA_BUF_ADDR_WIDTH = 8,\n parameter DRAM_TYPE = \"DDR3\",\n parameter EARLY_WR_DATA_ADDR = \"OFF\",\n parameter ECC = \"OFF\",\n parameter nBANK_MACHS = 4,\n parameter nCK_PER_CLK = 2,\n parameter nCS_PER_RANK = 1,\n parameter CKE_ODT_AUX = \"FALSE\",\n parameter nSLOTS = 2,\n parameter RANKS = 1,\n parameter RANK_VECT_INDX = 15,\n parameter RANK_WIDTH = 2,\n parameter ROW_VECT_INDX = 63,\n parameter ROW_WIDTH = 16,\n parameter RTT_NOM = \"40\",\n parameter RTT_WR = \"120\",\n parameter SLOT_0_CONFIG = 8'b0000_0101,\n parameter SLOT_1_CONFIG = 8'b0000_1010\n )\n (\n\n // Outputs\n\n output wire col_periodic_rd,\n output wire [RANK_WIDTH-1:0] col_ra,\n output wire [BANK_WIDTH-1:0] col_ba,\n output wire [ROW_WIDTH-1:0] col_a,\n output wire col_rmw,\n output wire col_rd_wr,\n output wire col_size,\n output wire [ROW_WIDTH-1:0] col_row,\n output wire [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr,\n output wire [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr,\n\n output wire [nCK_PER_CLK-1:0] mc_ras_n,\n output wire [nCK_PER_CLK-1:0] mc_cas_n,\n output wire [nCK_PER_CLK-1:0] mc_we_n,\n output wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address,\n output wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank,\n output wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n,\n output wire [1:0] mc_odt,\n output wire [nCK_PER_CLK-1:0] mc_cke,\n output wire [3:0] mc_aux_out0,\n output wire [3:0] mc_aux_out1,\n output [2:0] mc_cmd,\n output wire [5:0] mc_data_offset,\n output wire [5:0] mc_data_offset_1,\n output wire [5:0] mc_data_offset_2,\n output wire [1:0] mc_cas_slot,\n \n output wire [RANK_WIDTH-1:0] rnk_config,\n\n // Inputs\n\n input clk,\n input rst,\n input init_calib_complete,\n\n input [RANK_VECT_INDX:0] req_rank_r,\n input [BANK_VECT_INDX:0] req_bank_r,\n input [nBANK_MACHS-1:0] req_ras,\n input [nBANK_MACHS-1:0] req_cas,\n input [nBANK_MACHS-1:0] req_wr_r,\n input [nBANK_MACHS-1:0] grant_row_r,\n input [nBANK_MACHS-1:0] grant_pre_r,\n input [ROW_VECT_INDX:0] row_addr,\n input [nBANK_MACHS-1:0] row_cmd_wr,\n input insert_maint_r1,\n input maint_zq_r,\n input maint_sre_r,\n input maint_srx_r,\n input [RANK_WIDTH-1:0] maint_rank_r,\n \n input [nBANK_MACHS-1:0] req_periodic_rd_r,\n input [nBANK_MACHS-1:0] req_size_r,\n input [nBANK_MACHS-1:0] rd_wr_r,\n input [ROW_VECT_INDX:0] req_row_r,\n input [ROW_VECT_INDX:0] col_addr,\n input [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r,\n input [nBANK_MACHS-1:0] grant_col_r,\n input [nBANK_MACHS-1:0] grant_col_wr,\n\n input [6*RANKS-1:0] calib_rddata_offset,\n input [6*RANKS-1:0] calib_rddata_offset_1,\n input [6*RANKS-1:0] calib_rddata_offset_2,\n input [5:0] col_channel_offset,\n \n input [nBANK_MACHS-1:0] grant_config_r,\n input rnk_config_strobe,\n\n input [7:0] slot_0_present,\n input [7:0] slot_1_present,\n\n input send_cmd0_row,\n input send_cmd0_col,\n input send_cmd1_row,\n input send_cmd1_col,\n input send_cmd2_row,\n input send_cmd2_col,\n input send_cmd2_pre,\n input send_cmd3_col,\n\n input sent_col,\n \n input cs_en0,\n input cs_en1,\n input cs_en2,\n input cs_en3\n\n );\n\n localparam OUT_CMD_WIDTH = RANK_WIDTH + BANK_WIDTH + ROW_WIDTH + 1 + 1 + 1;\n\n reg col_rd_wr_ns;\n reg col_rd_wr_r = 1'b0;\n reg [OUT_CMD_WIDTH-1:0] col_cmd_r = {OUT_CMD_WIDTH {1'b0}};\n reg [OUT_CMD_WIDTH-1:0] row_cmd_r = {OUT_CMD_WIDTH {1'b0}};\n \n // calib_rd_data_offset for currently targeted rank\n reg [5:0] rank_rddata_offset_0;\n reg [5:0] rank_rddata_offset_1;\n reg [5:0] rank_rddata_offset_2;\n\n // Toggle CKE[0] when entering and exiting self-refresh, disable CKE[1]\n assign mc_aux_out0[0] = (maint_sre_r || maint_srx_r) & insert_maint_r1;\n assign mc_aux_out0[2] = 1'b0;\n\n reg cke_r;\n reg cke_ns;\n generate\n if(CKE_ODT_AUX == \"FALSE\")begin\n always @(posedge clk) \n begin\n if (rst)\n cke_r = 1'b1;\n else\n cke_r = cke_ns;\n end\n\n always @(*) \n begin\n cke_ns = 1'b1;\n if (maint_sre_r & insert_maint_r1)\n cke_ns = 1'b0;\n else if (cke_r==1'b0)\n begin\n if (maint_srx_r & insert_maint_r1)\n cke_ns = 1'b1;\n else\n cke_ns = 1'b0;\n end\n end\n end\n endgenerate\n \n // Disable ODT & CKE toggle enable high bits\n assign mc_aux_out1 = 4'b0;\n\n // implement PHY command word \n assign mc_cmd[0] = sent_col;\n assign mc_cmd[1] = EVEN_CWL_2T_MODE == \"ON\" ?\n sent_col && col_rd_wr_r :\n sent_col && col_rd_wr_ns;\n assign mc_cmd[2] = ~sent_col;\n\n // generate calib_rd_data_offset for current rank - only use rank 0 values for now\n always @(calib_rddata_offset or calib_rddata_offset_1 or calib_rddata_offset_2) begin\n rank_rddata_offset_0 = calib_rddata_offset[5:0];\n rank_rddata_offset_1 = calib_rddata_offset_1[5:0];\n rank_rddata_offset_2 = calib_rddata_offset_2[5:0];\n end\n\n // generate data offset\n generate\n if(EVEN_CWL_2T_MODE == \"ON\") begin : gen_mc_data_offset_even_cwl_2t\n assign mc_data_offset = ~sent_col ?\n 6'b0 :\n col_rd_wr_r ?\n rank_rddata_offset_0 + col_channel_offset :\n nCK_PER_CLK == 2 ? \n CWL - 2 + col_channel_offset :\n // nCK_PER_CLK == 4\n CWL + 2 + col_channel_offset;\n assign mc_data_offset_1 = ~sent_col ?\n 6'b0 :\n col_rd_wr_r ?\n rank_rddata_offset_1 + col_channel_offset :\n nCK_PER_CLK == 2 ? \n CWL - 2 + col_channel_offset :\n // nCK_PER_CLK == 4\n CWL + 2 + col_channel_offset;\n assign mc_data_offset_2 = ~sent_col ?\n 6'b0 :\n col_rd_wr_r ?\n rank_rddata_offset_2 + col_channel_offset :\n nCK_PER_CLK == 2 ? \n CWL - 2 + col_channel_offset :\n // nCK_PER_CLK == 4\n CWL + 2 + col_channel_offset;\n end\n else begin : gen_mc_data_offset_not_even_cwl_2t\n assign mc_data_offset = ~sent_col ?\n 6'b0 :\n col_rd_wr_ns ?\n rank_rddata_offset_0 + col_channel_offset :\n nCK_PER_CLK == 2 ? \n CWL - 2 + col_channel_offset :\n // nCK_PER_CLK == 4\n CWL + 2 + col_channel_offset;\n assign mc_data_offset_1 = ~sent_col ?\n 6'b0 :\n col_rd_wr_ns ?\n rank_rddata_offset_1 + col_channel_offset :\n nCK_PER_CLK == 2 ? \n CWL - 2 + col_channel_offset :\n // nCK_PER_CLK == 4\n CWL + 2 + col_channel_offset;\n assign mc_data_offset_2 = ~sent_col ?\n 6'b0 :\n col_rd_wr_ns ?\n rank_rddata_offset_2 + col_channel_offset :\n nCK_PER_CLK == 2 ? \n CWL - 2 + col_channel_offset :\n // nCK_PER_CLK == 4\n CWL + 2 + col_channel_offset;\n end\n endgenerate\n\n assign mc_cas_slot = col_channel_offset[1:0];\n\n// Based on arbitration results, select the row and column commands.\n\n integer i;\n reg [OUT_CMD_WIDTH-1:0] row_cmd_ns;\n generate\n begin : row_mux\n wire [OUT_CMD_WIDTH-1:0] maint_cmd =\n {maint_rank_r, // maintenance rank\n row_cmd_r[15+:(BANK_WIDTH+ROW_WIDTH-11)],\n // bank plus upper address bits\n 1'b0, // A10 = 0 for ZQCS\n row_cmd_r[3+:10], // address bits [9:0]\n // ZQ, SRX or SRE/REFRESH\n (maint_zq_r ? 3'b110 : maint_srx_r ? 3'b111 : 3'b001)\n };\n always @(/*AS*/grant_row_r or insert_maint_r1 or maint_cmd\n or req_bank_r or req_cas or req_rank_r or req_ras\n or row_addr or row_cmd_r or row_cmd_wr or rst)\n begin\n row_cmd_ns = rst\n ? {RANK_WIDTH{1'b0}}\n : insert_maint_r1\n ? maint_cmd\n : row_cmd_r;\n for (i=0; i 1) begin : slot_1_configured\n wire slot_1_select = (slot_1_present[3] & slot_1_present[1])? \n |({col_ra_one_hot[slot_0_population+1],\n col_ra_one_hot[slot_0_population]}) :\n\t (slot_1_present[1]) ? col_ra_one_hot[slot_0_population] :1'b0;\n wire slot_1_read = EVEN_CWL_2T_MODE == \"ON\" ?\n slot_1_select && col_rd_wr_r :\n slot_1_select && col_rd_wr_ns;\n wire slot_1_write = EVEN_CWL_2T_MODE == \"ON\" ?\n slot_1_select && ~col_rd_wr_r :\n slot_1_select && ~col_rd_wr_ns;\n\n // ODT on in slot 1 for writes to slot 1 (and R/W to slot 0 for DDR3)\n wire slot_1_odt = (DRAM_TYPE == \"DDR3\") ? ~slot_1_read : slot_1_write;\n assign mc_aux_out0[3] = slot_1_odt & sent_col; // Only send for COL cmds\n\n end // if (nSLOTS > 1)\n else begin\n \n // Disable slot 1 ODT when not present\n assign mc_aux_out0[3] = 1'b0;\n\n end // else: !if(nSLOTS > 1)\n endgenerate\n \n\n generate\n if(CKE_ODT_AUX == \"FALSE\")begin\n reg[1:0] mc_aux_out_r ;\n reg[1:0] mc_aux_out_r_1 ;\n reg[1:0] mc_aux_out_r_2 ;\n\n always@(posedge clk) begin\n mc_aux_out_r[0] <= #TCQ mc_aux_out0[1] ;\n mc_aux_out_r[1] <= #TCQ mc_aux_out0[3] ;\n mc_aux_out_r_1 <= #TCQ mc_aux_out_r ;\n mc_aux_out_r_2 <= #TCQ mc_aux_out_r_1 ;\n end \n\n if((nCK_PER_CLK == 4) && (nSLOTS > 1 )) begin:odt_high_time_4_1_dslot\n assign mc_odt[0] = mc_aux_out0[1] | mc_aux_out_r[0] | mc_aux_out_r_1[0];\n assign mc_odt[1] = mc_aux_out0[3] | mc_aux_out_r[1] | mc_aux_out_r_1[1];\n end else if(nCK_PER_CLK == 4) begin:odt_high_time_4_1\n assign mc_odt[0] = mc_aux_out0[1] | mc_aux_out_r[0] ;\n assign mc_odt[1] = mc_aux_out0[3] | mc_aux_out_r[1] ;\n end else if(nCK_PER_CLK == 2) begin:odt_high_time_2_1\n assign mc_odt[0] = mc_aux_out0[1] | mc_aux_out_r[0] | mc_aux_out_r_1[0] | mc_aux_out_r_2[0] ;\n assign mc_odt[1] = mc_aux_out0[3] | mc_aux_out_r[1] | mc_aux_out_r_1[1] | mc_aux_out_r_2[1] ;\n end \n end\n endgenerate \n\n\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_bank_cntrl.v", "content": "//*****************************************************************************\n// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor : Xilinx\n// \\ \\ \\/ Version : %version\n// \\ \\ Application : MIG\n// / / Filename : bank_cntrl.v\n// /___/ /\\ Date Last Modified : $date$\n// \\ \\ / \\ Date Created : Tue Jun 30 2009\n// \\___\\/\\___\\\n//\n//Device : 7-Series\n//Design Name : DDR3 SDRAM\n//Purpose :\n//Reference :\n//Revision History :\n//*****************************************************************************\n\n// Structural block instantiating the three sub blocks that make up\n// a bank machine.\n`timescale 1ps/1ps\n\nmodule mig_7series_v4_0_bank_cntrl #\n (\n parameter TCQ = 100,\n parameter ADDR_CMD_MODE = \"1T\",\n parameter BANK_WIDTH = 3,\n parameter BM_CNT_WIDTH = 2,\n parameter BURST_MODE = \"8\",\n parameter COL_WIDTH = 12,\n parameter CWL = 5,\n parameter DATA_BUF_ADDR_WIDTH = 8,\n parameter DRAM_TYPE = \"DDR3\",\n parameter ECC = \"OFF\",\n parameter ID = 4,\n parameter nBANK_MACHS = 4,\n parameter nCK_PER_CLK = 2,\n parameter nOP_WAIT = 0,\n parameter nRAS_CLKS = 10,\n parameter nRCD = 5,\n parameter nRTP = 4,\n parameter nRP = 10,\n parameter nWTP_CLKS = 5,\n parameter ORDERING = \"NORM\",\n parameter RANK_WIDTH = 2,\n parameter RANKS = 4,\n parameter RAS_TIMER_WIDTH = 5,\n parameter ROW_WIDTH = 16,\n parameter STARVE_LIMIT = 2\n )\n (/*AUTOARG*/\n // Outputs\n wr_this_rank_r, start_rcd, start_pre_wait, rts_row, rts_col, rts_pre, rtc,\n row_cmd_wr, row_addr, req_size_r, req_row_r, req_ras,\n req_periodic_rd_r, req_cas, req_bank_r, rd_this_rank_r,\n rb_hit_busy_ns, ras_timer_ns, rank_busy_r, ordered_r,\n ordered_issued, op_exit_req, end_rtp, demand_priority,\n demand_act_priority, col_rdy_wr, col_addr, act_this_rank_r, idle_ns,\n req_wr_r, rd_wr_r, bm_end, idle_r, head_r, req_rank_r,\n rb_hit_busy_r, passing_open_bank, maint_hit, req_data_buf_addr_r,\n // Inputs\n was_wr, was_priority, use_addr, start_rcd_in,\n size, sent_row, sent_col, sending_row, sending_pre, sending_col, rst, row,\n req_rank_r_in, rd_rmw, rd_data_addr, rb_hit_busy_ns_in,\n rb_hit_busy_cnt, ras_timer_ns_in, rank, periodic_rd_rank_r,\n periodic_rd_insert, periodic_rd_ack_r, passing_open_bank_in,\n order_cnt, op_exit_grant, maint_zq_r, maint_sre_r, maint_req_r, maint_rank_r,\n maint_idle, low_idle_cnt_r, rnk_config_valid_r, inhbt_rd, inhbt_wr,\n rnk_config_strobe, rnk_config, inhbt_act_faw_r, idle_cnt, hi_priority,\n dq_busy_data, phy_rddata_valid, demand_priority_in, demand_act_priority_in,\n data_buf_addr, col, cmd, clk, bm_end_in, bank, adv_order_q,\n accept_req, accept_internal_r, rnk_config_kill_rts_col, phy_mc_ctl_full,\n phy_mc_cmd_full, phy_mc_data_full\n );\n\n /*AUTOINPUT*/\n // Beginning of automatic inputs (from unused autoinst inputs)\n input accept_internal_r; // To bank_queue0 of bank_queue.v\n input accept_req; // To bank_queue0 of bank_queue.v\n input adv_order_q; // To bank_queue0 of bank_queue.v\n input [BANK_WIDTH-1:0] bank; // To bank_compare0 of bank_compare.v\n input [(nBANK_MACHS*2)-1:0] bm_end_in; // To bank_queue0 of bank_queue.v\n input clk; // To bank_compare0 of bank_compare.v, ...\n input [2:0] cmd; // To bank_compare0 of bank_compare.v\n input [COL_WIDTH-1:0] col; // To bank_compare0 of bank_compare.v\n input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr;// To bank_compare0 of bank_compare.v\n input [(nBANK_MACHS*2)-1:0] demand_act_priority_in;// To bank_state0 of bank_state.v\n input [(nBANK_MACHS*2)-1:0] demand_priority_in;// To bank_state0 of bank_state.v\n input phy_rddata_valid; // To bank_state0 of bank_state.v\n input dq_busy_data; // To bank_state0 of bank_state.v\n input hi_priority; // To bank_compare0 of bank_compare.v\n input [BM_CNT_WIDTH-1:0] idle_cnt; // To bank_queue0 of bank_queue.v\n input [RANKS-1:0] inhbt_act_faw_r; // To bank_state0 of bank_state.v\n input [RANKS-1:0] inhbt_rd; // To bank_state0 of bank_state.v\n input [RANKS-1:0] inhbt_wr; // To bank_state0 of bank_state.v\n input [RANK_WIDTH-1:0]rnk_config; // To bank_state0 of bank_state.v\n input rnk_config_strobe; // To bank_state0 of bank_state.v\n input rnk_config_kill_rts_col;// To bank_state0 of bank_state.v\n input rnk_config_valid_r; // To bank_state0 of bank_state.v\n input low_idle_cnt_r; // To bank_state0 of bank_state.v\n input maint_idle; // To bank_queue0 of bank_queue.v\n input [RANK_WIDTH-1:0] maint_rank_r; // To bank_compare0 of bank_compare.v\n input maint_req_r; // To bank_queue0 of bank_queue.v\n input maint_zq_r; // To bank_compare0 of bank_compare.v\n input maint_sre_r; // To bank_compare0 of bank_compare.v\n input op_exit_grant; // To bank_state0 of bank_state.v\n input [BM_CNT_WIDTH-1:0] order_cnt; // To bank_queue0 of bank_queue.v\n input [(nBANK_MACHS*2)-1:0] passing_open_bank_in;// To bank_queue0 of bank_queue.v\n input periodic_rd_ack_r; // To bank_queue0 of bank_queue.v\n input periodic_rd_insert; // To bank_compare0 of bank_compare.v\n input [RANK_WIDTH-1:0] periodic_rd_rank_r; // To bank_compare0 of bank_compare.v\n input phy_mc_ctl_full;\n input phy_mc_cmd_full;\n input phy_mc_data_full;\n input [RANK_WIDTH-1:0] rank; // To bank_compare0 of bank_compare.v\n input [(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0] ras_timer_ns_in;// To bank_state0 of bank_state.v\n input [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt; // To bank_queue0 of bank_queue.v\n input [(nBANK_MACHS*2)-1:0] rb_hit_busy_ns_in;// To bank_queue0 of bank_queue.v\n input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; // To bank_state0 of bank_state.v\n input rd_rmw; // To bank_state0 of bank_state.v\n input [(RANK_WIDTH*nBANK_MACHS*2)-1:0] req_rank_r_in;// To bank_state0 of bank_state.v\n input [ROW_WIDTH-1:0] row; // To bank_compare0 of bank_compare.v\n input rst; // To bank_state0 of bank_state.v, ...\n input sending_col; // To bank_compare0 of bank_compare.v, ...\n input sending_row; // To bank_state0 of bank_state.v\n input sending_pre;\n input sent_col; // To bank_state0 of bank_state.v\n input sent_row; // To bank_state0 of bank_state.v\n input size; // To bank_compare0 of bank_compare.v\n input [(nBANK_MACHS*2)-1:0] start_rcd_in; // To bank_state0 of bank_state.v\n input use_addr; // To bank_queue0 of bank_queue.v\n input was_priority; // To bank_queue0 of bank_queue.v\n input was_wr; // To bank_queue0 of bank_queue.v\n // End of automatics\n\n /*AUTOOUTPUT*/\n // Beginning of automatic outputs (from unused autoinst outputs)\n output [RANKS-1:0] act_this_rank_r; // From bank_state0 of bank_state.v\n output [ROW_WIDTH-1:0] col_addr; // From bank_compare0 of bank_compare.v\n output col_rdy_wr; // From bank_state0 of bank_state.v\n output demand_act_priority; // From bank_state0 of bank_state.v\n output demand_priority; // From bank_state0 of bank_state.v\n output end_rtp; // From bank_state0 of bank_state.v\n output op_exit_req; // From bank_state0 of bank_state.v\n output ordered_issued; // From bank_queue0 of bank_queue.v\n output ordered_r; // From bank_queue0 of bank_queue.v\n output [RANKS-1:0] rank_busy_r; // From bank_compare0 of bank_compare.v\n output [RAS_TIMER_WIDTH-1:0] ras_timer_ns; // From bank_state0 of bank_state.v\n output rb_hit_busy_ns; // From bank_compare0 of bank_compare.v\n output [RANKS-1:0] rd_this_rank_r; // From bank_state0 of bank_state.v\n output [BANK_WIDTH-1:0] req_bank_r; // From bank_compare0 of bank_compare.v\n output req_cas; // From bank_compare0 of bank_compare.v\n output req_periodic_rd_r; // From bank_compare0 of bank_compare.v\n output req_ras; // From bank_compare0 of bank_compare.v\n output [ROW_WIDTH-1:0] req_row_r; // From bank_compare0 of bank_compare.v\n output req_size_r; // From bank_compare0 of bank_compare.v\n output [ROW_WIDTH-1:0] row_addr; // From bank_compare0 of bank_compare.v\n output row_cmd_wr; // From bank_compare0 of bank_compare.v\n output rtc; // From bank_state0 of bank_state.v\n output rts_col; // From bank_state0 of bank_state.v\n output rts_row; // From bank_state0 of bank_state.v\n output rts_pre;\n output start_pre_wait; // From bank_state0 of bank_state.v\n output start_rcd; // From bank_state0 of bank_state.v\n output [RANKS-1:0] wr_this_rank_r; // From bank_state0 of bank_state.v\n // End of automatics\n\n /*AUTOWIRE*/\n // Beginning of automatic wires (for undeclared instantiated-module outputs)\n wire act_wait_r; // From bank_state0 of bank_state.v\n wire allow_auto_pre; // From bank_state0 of bank_state.v\n wire auto_pre_r; // From bank_queue0 of bank_queue.v\n wire bank_wait_in_progress; // From bank_state0 of bank_state.v\n wire order_q_zero; // From bank_queue0 of bank_queue.v\n wire pass_open_bank_ns; // From bank_queue0 of bank_queue.v\n wire pass_open_bank_r; // From bank_queue0 of bank_queue.v\n wire pre_wait_r; // From bank_state0 of bank_state.v\n wire precharge_bm_end; // From bank_state0 of bank_state.v\n wire q_has_priority; // From bank_queue0 of bank_queue.v\n wire q_has_rd; // From bank_queue0 of bank_queue.v\n wire [nBANK_MACHS*2-1:0] rb_hit_busies_r; // From bank_queue0 of bank_queue.v\n wire rcv_open_bank; // From bank_queue0 of bank_queue.v\n wire rd_half_rmw; // From bank_state0 of bank_state.v\n wire req_priority_r; // From bank_compare0 of bank_compare.v\n wire row_hit_r; // From bank_compare0 of bank_compare.v\n wire tail_r; // From bank_queue0 of bank_queue.v\n wire wait_for_maint_r; // From bank_queue0 of bank_queue.v\n // End of automatics\n\n output idle_ns;\n output req_wr_r;\n output rd_wr_r;\n output bm_end;\n output idle_r;\n output head_r;\n output [RANK_WIDTH-1:0] req_rank_r;\n output rb_hit_busy_r;\n output passing_open_bank;\n output maint_hit;\n output [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r;\n\n mig_7series_v4_0_bank_compare #\n (/*AUTOINSTPARAM*/\n // Parameters\n .BANK_WIDTH (BANK_WIDTH),\n .TCQ (TCQ),\n .BURST_MODE (BURST_MODE),\n .COL_WIDTH (COL_WIDTH),\n .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),\n .ECC (ECC),\n .RANK_WIDTH (RANK_WIDTH),\n .RANKS (RANKS),\n .ROW_WIDTH (ROW_WIDTH))\n bank_compare0\n (/*AUTOINST*/\n // Outputs\n .req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_WIDTH-1:0]),\n .req_periodic_rd_r (req_periodic_rd_r),\n .req_size_r (req_size_r),\n .rd_wr_r (rd_wr_r),\n .req_rank_r (req_rank_r[RANK_WIDTH-1:0]),\n .req_bank_r (req_bank_r[BANK_WIDTH-1:0]),\n .req_row_r (req_row_r[ROW_WIDTH-1:0]),\n .req_wr_r (req_wr_r),\n .req_priority_r (req_priority_r),\n .rb_hit_busy_r (rb_hit_busy_r),\n .rb_hit_busy_ns (rb_hit_busy_ns),\n .row_hit_r (row_hit_r),\n .maint_hit (maint_hit),\n .col_addr (col_addr[ROW_WIDTH-1:0]),\n .req_ras (req_ras),\n .req_cas (req_cas),\n .row_cmd_wr (row_cmd_wr),\n .row_addr (row_addr[ROW_WIDTH-1:0]),\n .rank_busy_r (rank_busy_r[RANKS-1:0]),\n // Inputs\n .clk (clk),\n .idle_ns (idle_ns),\n .idle_r (idle_r),\n .data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),\n .periodic_rd_insert (periodic_rd_insert),\n .size (size),\n .cmd (cmd[2:0]),\n .sending_col (sending_col),\n .rank (rank[RANK_WIDTH-1:0]),\n .periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),\n .bank (bank[BANK_WIDTH-1:0]),\n .row (row[ROW_WIDTH-1:0]),\n .col (col[COL_WIDTH-1:0]),\n .hi_priority (hi_priority),\n .maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),\n .maint_zq_r (maint_zq_r),\n .maint_sre_r (maint_sre_r),\n .auto_pre_r (auto_pre_r),\n .rd_half_rmw (rd_half_rmw),\n .act_wait_r (act_wait_r));\n\n mig_7series_v4_0_bank_state #\n (/*AUTOINSTPARAM*/\n // Parameters\n .TCQ (TCQ),\n .ADDR_CMD_MODE (ADDR_CMD_MODE),\n .BM_CNT_WIDTH (BM_CNT_WIDTH),\n .BURST_MODE (BURST_MODE),\n .CWL (CWL),\n .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),\n .DRAM_TYPE (DRAM_TYPE),\n .ECC (ECC),\n .ID (ID),\n .nBANK_MACHS (nBANK_MACHS),\n .nCK_PER_CLK (nCK_PER_CLK),\n .nOP_WAIT (nOP_WAIT),\n .nRAS_CLKS (nRAS_CLKS),\n .nRP (nRP),\n .nRTP (nRTP),\n .nRCD (nRCD),\n .nWTP_CLKS (nWTP_CLKS),\n .ORDERING (ORDERING),\n .RANKS (RANKS),\n .RANK_WIDTH (RANK_WIDTH),\n .RAS_TIMER_WIDTH (RAS_TIMER_WIDTH),\n .STARVE_LIMIT (STARVE_LIMIT))\n bank_state0\n (/*AUTOINST*/\n // Outputs\n .start_rcd (start_rcd),\n .act_wait_r (act_wait_r),\n .rd_half_rmw (rd_half_rmw),\n .ras_timer_ns (ras_timer_ns[RAS_TIMER_WIDTH-1:0]),\n .end_rtp (end_rtp),\n .bank_wait_in_progress (bank_wait_in_progress),\n .start_pre_wait (start_pre_wait),\n .op_exit_req (op_exit_req),\n .pre_wait_r (pre_wait_r),\n .allow_auto_pre (allow_auto_pre),\n .precharge_bm_end (precharge_bm_end),\n .demand_act_priority (demand_act_priority),\n .rts_row (rts_row),\n .rts_pre (rts_pre),\n .act_this_rank_r (act_this_rank_r[RANKS-1:0]),\n .demand_priority (demand_priority),\n .col_rdy_wr (col_rdy_wr),\n .rts_col (rts_col),\n .wr_this_rank_r (wr_this_rank_r[RANKS-1:0]),\n .rd_this_rank_r (rd_this_rank_r[RANKS-1:0]),\n // Inputs\n .clk (clk),\n .rst (rst),\n .bm_end (bm_end),\n .pass_open_bank_r (pass_open_bank_r),\n .sending_row (sending_row),\n .sending_pre (sending_pre),\n .rcv_open_bank (rcv_open_bank),\n .sending_col (sending_col),\n .rd_wr_r (rd_wr_r),\n .req_wr_r (req_wr_r),\n .rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),\n .req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_WIDTH-1:0]),\n .phy_rddata_valid (phy_rddata_valid),\n .rd_rmw (rd_rmw),\n .ras_timer_ns_in (ras_timer_ns_in[(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0]),\n .rb_hit_busies_r (rb_hit_busies_r[(nBANK_MACHS*2)-1:0]),\n .idle_r (idle_r),\n .passing_open_bank (passing_open_bank),\n .low_idle_cnt_r (low_idle_cnt_r),\n .op_exit_grant (op_exit_grant),\n .tail_r (tail_r),\n .auto_pre_r (auto_pre_r),\n .pass_open_bank_ns (pass_open_bank_ns),\n .phy_mc_cmd_full (phy_mc_cmd_full),\n .phy_mc_ctl_full (phy_mc_ctl_full),\n .phy_mc_data_full (phy_mc_data_full),\n .rnk_config (rnk_config[RANK_WIDTH-1:0]),\n .rnk_config_strobe (rnk_config_strobe),\n .rnk_config_kill_rts_col (rnk_config_kill_rts_col),\n .rnk_config_valid_r (rnk_config_valid_r),\n .rtc (rtc),\n .req_rank_r (req_rank_r[RANK_WIDTH-1:0]),\n .req_rank_r_in (req_rank_r_in[(RANK_WIDTH*nBANK_MACHS*2)-1:0]),\n .start_rcd_in (start_rcd_in[(nBANK_MACHS*2)-1:0]),\n .inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]),\n .wait_for_maint_r (wait_for_maint_r),\n .head_r (head_r),\n .sent_row (sent_row),\n .demand_act_priority_in (demand_act_priority_in[(nBANK_MACHS*2)-1:0]),\n .order_q_zero (order_q_zero),\n .sent_col (sent_col),\n .q_has_rd (q_has_rd),\n .q_has_priority (q_has_priority),\n .req_priority_r (req_priority_r),\n .idle_ns (idle_ns),\n .demand_priority_in (demand_priority_in[(nBANK_MACHS*2)-1:0]),\n .inhbt_rd (inhbt_rd[RANKS-1:0]),\n .inhbt_wr (inhbt_wr[RANKS-1:0]),\n .dq_busy_data (dq_busy_data));\n\n mig_7series_v4_0_bank_queue #\n (/*AUTOINSTPARAM*/\n // Parameters\n .TCQ (TCQ),\n .BM_CNT_WIDTH (BM_CNT_WIDTH),\n .nBANK_MACHS (nBANK_MACHS),\n .ORDERING (ORDERING),\n .ID (ID))\n bank_queue0\n (/*AUTOINST*/\n // Outputs\n .head_r (head_r),\n .tail_r (tail_r),\n .idle_ns (idle_ns),\n .idle_r (idle_r),\n .pass_open_bank_ns (pass_open_bank_ns),\n .pass_open_bank_r (pass_open_bank_r),\n .auto_pre_r (auto_pre_r),\n .bm_end (bm_end),\n .passing_open_bank (passing_open_bank),\n .ordered_issued (ordered_issued),\n .ordered_r (ordered_r),\n .order_q_zero (order_q_zero),\n .rcv_open_bank (rcv_open_bank),\n .rb_hit_busies_r (rb_hit_busies_r[nBANK_MACHS*2-1:0]),\n .q_has_rd (q_has_rd),\n .q_has_priority (q_has_priority),\n .wait_for_maint_r (wait_for_maint_r),\n // Inputs\n .clk (clk),\n .rst (rst),\n .accept_internal_r (accept_internal_r),\n .use_addr (use_addr),\n .periodic_rd_ack_r (periodic_rd_ack_r),\n .bm_end_in (bm_end_in[(nBANK_MACHS*2)-1:0]),\n .idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]),\n .rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]),\n .accept_req (accept_req),\n .rb_hit_busy_r (rb_hit_busy_r),\n .maint_idle (maint_idle),\n .maint_hit (maint_hit),\n .row_hit_r (row_hit_r),\n .pre_wait_r (pre_wait_r),\n .allow_auto_pre (allow_auto_pre),\n .sending_col (sending_col),\n .req_wr_r (req_wr_r),\n .rd_wr_r (rd_wr_r),\n .bank_wait_in_progress (bank_wait_in_progress),\n .precharge_bm_end (precharge_bm_end),\n .adv_order_q (adv_order_q),\n .order_cnt (order_cnt[BM_CNT_WIDTH-1:0]),\n .rb_hit_busy_ns_in (rb_hit_busy_ns_in[(nBANK_MACHS*2)-1:0]),\n .passing_open_bank_in (passing_open_bank_in[(nBANK_MACHS*2)-1:0]),\n .was_wr (was_wr),\n .maint_req_r (maint_req_r),\n .was_priority (was_priority));\n\nendmodule // bank_cntrl\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_bank_common.v", "content": "//*****************************************************************************\n// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor : Xilinx\n// \\ \\ \\/ Version : %version\n// \\ \\ Application : MIG\n// / / Filename : bank_common.v\n// /___/ /\\ Date Last Modified : $date$\n// \\ \\ / \\ Date Created : Tue Jun 30 2009\n// \\___\\/\\___\\\n//\n//Device : 7-Series\n//Design Name : DDR3 SDRAM\n//Purpose :\n//Reference :\n//Revision History :\n//*****************************************************************************\n\n// Common block for the bank machines. Bank_common computes various\n// items that cross all of the bank machines. These values are then\n// fed back to all of the bank machines. Most of these values have\n// to do with a row machine figuring out where it belongs in a queue.\n\n`timescale 1 ps / 1 ps\n\nmodule mig_7series_v4_0_bank_common #\n (\n parameter TCQ = 100,\n parameter BM_CNT_WIDTH = 2,\n parameter LOW_IDLE_CNT = 1,\n parameter nBANK_MACHS = 4,\n parameter nCK_PER_CLK = 2,\n parameter nOP_WAIT = 0,\n parameter nRFC = 44,\n parameter nXSDLL = 512,\n parameter RANK_WIDTH = 2,\n parameter RANKS = 4,\n parameter CWL = 5,\n parameter tZQCS = 64\n )\n (/*AUTOARG*/\n // Outputs\n accept_internal_r, accept_ns, accept, periodic_rd_insert,\n periodic_rd_ack_r, accept_req, rb_hit_busy_cnt, idle, idle_cnt, order_cnt,\n adv_order_q, bank_mach_next, op_exit_grant, low_idle_cnt_r, was_wr,\n was_priority, maint_wip_r, maint_idle, insert_maint_r,\n // Inputs\n clk, rst, idle_ns, init_calib_complete, periodic_rd_r, use_addr,\n rb_hit_busy_r, idle_r, ordered_r, ordered_issued, head_r, end_rtp,\n passing_open_bank, op_exit_req, start_pre_wait, cmd, hi_priority, maint_req_r,\n maint_zq_r, maint_sre_r, maint_srx_r, maint_hit, bm_end,\n slot_0_present, slot_1_present\n );\n\n function integer clogb2 (input integer size); // ceiling logb2\n begin\n size = size - 1;\n for (clogb2=1; size>1; clogb2=clogb2+1)\n size = size >> 1;\n end\n endfunction // clogb2\n\n localparam ZERO = 0;\n localparam ONE = 1;\n localparam [BM_CNT_WIDTH-1:0] BM_CNT_ZERO = ZERO[0+:BM_CNT_WIDTH];\n localparam [BM_CNT_WIDTH-1:0] BM_CNT_ONE = ONE[0+:BM_CNT_WIDTH];\n\n input clk;\n input rst;\n\n input [nBANK_MACHS-1:0] idle_ns;\n input init_calib_complete;\n wire accept_internal_ns = init_calib_complete && |idle_ns;\n output reg accept_internal_r;\n always @(posedge clk) accept_internal_r <= accept_internal_ns;\n wire periodic_rd_ack_ns;\n wire accept_ns_lcl = accept_internal_ns && ~periodic_rd_ack_ns;\n output wire accept_ns;\n assign accept_ns = accept_ns_lcl;\n reg accept_r;\n always @(posedge clk) accept_r <= #TCQ accept_ns_lcl;\n\n// Wire to user interface informing user that the request has been accepted.\n output wire accept;\n assign accept = accept_r;\n\n`ifdef MC_SVA\n property none_idle;\n @(posedge clk) (init_calib_complete && ~|idle_r);\n endproperty\n\n all_bank_machines_busy: cover property (none_idle);\n`endif\n\n// periodic_rd_insert tells everyone to mux in the periodic read.\n input periodic_rd_r;\n reg periodic_rd_ack_r_lcl;\n reg periodic_rd_cntr_r ;\n always @(posedge clk) begin\n if (rst) periodic_rd_cntr_r <= #TCQ 1'b0;\n else if (periodic_rd_r && periodic_rd_ack_r_lcl)\n periodic_rd_cntr_r <= #TCQ ~periodic_rd_cntr_r;\n end\n\n wire internal_periodic_rd_ack_r_lcl = (periodic_rd_cntr_r && periodic_rd_ack_r_lcl);\n\n // wire periodic_rd_insert_lcl = periodic_rd_r && ~periodic_rd_ack_r_lcl;\n wire periodic_rd_insert_lcl = periodic_rd_r && ~internal_periodic_rd_ack_r_lcl;\n output wire periodic_rd_insert;\n assign periodic_rd_insert = periodic_rd_insert_lcl;\n\n// periodic_rd_ack_r acknowledges that the read has been accepted\n// into the queue.\n assign periodic_rd_ack_ns = periodic_rd_insert_lcl && accept_internal_ns;\n always @(posedge clk) periodic_rd_ack_r_lcl <= #TCQ periodic_rd_ack_ns;\n output wire periodic_rd_ack_r;\n assign periodic_rd_ack_r = periodic_rd_ack_r_lcl;\n\n// accept_req tells all q entries that a request has been accepted.\n input use_addr;\n wire accept_req_lcl = periodic_rd_ack_r_lcl || (accept_r && use_addr);\n output wire accept_req;\n assign accept_req = accept_req_lcl;\n\n// Count how many non idle bank machines hit on the rank and bank.\n input [nBANK_MACHS-1:0] rb_hit_busy_r;\n output reg [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt;\n integer i;\n always @(/*AS*/rb_hit_busy_r) begin\n rb_hit_busy_cnt = BM_CNT_ZERO;\n for (i = 0; i < nBANK_MACHS; i = i + 1)\n if (rb_hit_busy_r[i]) rb_hit_busy_cnt = rb_hit_busy_cnt + BM_CNT_ONE;\n end\n\n// Count the number of idle bank machines.\n input [nBANK_MACHS-1:0] idle_r;\n output reg [BM_CNT_WIDTH-1:0] idle_cnt;\n always @(/*AS*/idle_r) begin\n idle_cnt = BM_CNT_ZERO;\n for (i = 0; i < nBANK_MACHS; i = i + 1)\n if (idle_r[i]) idle_cnt = idle_cnt + BM_CNT_ONE;\n end\n\n// Report an overall idle status\n output idle;\n assign idle = init_calib_complete && &idle_r;\n \n// Count the number of bank machines in the ordering queue.\n input [nBANK_MACHS-1:0] ordered_r;\n output reg [BM_CNT_WIDTH-1:0] order_cnt;\n always @(/*AS*/ordered_r) begin\n order_cnt = BM_CNT_ZERO;\n for (i = 0; i < nBANK_MACHS; i = i + 1)\n if (ordered_r[i]) order_cnt = order_cnt + BM_CNT_ONE;\n end\n\n input [nBANK_MACHS-1:0] ordered_issued;\n output wire adv_order_q;\n assign adv_order_q = |ordered_issued;\n\n// Figure out which bank machine is going to accept the next request.\n input [nBANK_MACHS-1:0] head_r;\n wire [nBANK_MACHS-1:0] next = idle_r & head_r;\n output reg[BM_CNT_WIDTH-1:0] bank_mach_next;\n always @(/*AS*/next) begin\n bank_mach_next = BM_CNT_ZERO;\n for (i = 0; i <= nBANK_MACHS-1; i = i + 1)\n if (next[i]) bank_mach_next = i[BM_CNT_WIDTH-1:0];\n end\n\n input [nBANK_MACHS-1:0] end_rtp;\n input [nBANK_MACHS-1:0] passing_open_bank;\n input [nBANK_MACHS-1:0] op_exit_req;\n output wire [nBANK_MACHS-1:0] op_exit_grant;\n output reg low_idle_cnt_r = 1'b0;\n input [nBANK_MACHS-1:0] start_pre_wait;\n\n generate\n// In support of open page mode, the following logic\n// keeps track of how many \"idle\" bank machines there\n// are. In this case, idle means a bank machine is on\n// the idle list, or is in the process of precharging and\n// will soon be idle.\n if (nOP_WAIT == 0) begin : op_mode_disabled\n assign op_exit_grant = {nBANK_MACHS{1'b0}};\n end\n\n else begin : op_mode_enabled\n reg [BM_CNT_WIDTH:0] idle_cnt_r;\n reg [BM_CNT_WIDTH:0] idle_cnt_ns;\n always @(/*AS*/accept_req_lcl or idle_cnt_r or passing_open_bank\n or rst or start_pre_wait)\n if (rst) idle_cnt_ns = nBANK_MACHS;\n else begin\n idle_cnt_ns = idle_cnt_r - accept_req_lcl;\n for (i = 0; i <= nBANK_MACHS-1; i = i + 1) begin\n idle_cnt_ns = idle_cnt_ns + passing_open_bank[i];\n end\n idle_cnt_ns = idle_cnt_ns + |start_pre_wait;\n end\n always @(posedge clk) idle_cnt_r <= #TCQ idle_cnt_ns;\n wire low_idle_cnt_ns = (idle_cnt_ns <= LOW_IDLE_CNT[0+:BM_CNT_WIDTH]);\n always @(posedge clk) low_idle_cnt_r <= #TCQ low_idle_cnt_ns;\n\n// This arbiter determines which bank machine should transition\n// from open page wait to precharge. Ideally, this process\n// would take the oldest waiter, but don't have any reasonable\n// way to implement that. Instead, just use simple round robin\n// arb with the small enhancement that the most recent bank machine\n// to enter open page wait is given lowest priority in the arbiter.\n\n wire upd_last_master = |end_rtp; // should be one bit set at most\n mig_7series_v4_0_round_robin_arb #\n (.WIDTH (nBANK_MACHS))\n op_arb0\n (.grant_ns (op_exit_grant[nBANK_MACHS-1:0]),\n .grant_r (),\n .upd_last_master (upd_last_master),\n .current_master (end_rtp[nBANK_MACHS-1:0]),\n .clk (clk),\n .rst (rst),\n .req (op_exit_req[nBANK_MACHS-1:0]),\n .disable_grant (1'b0));\n\n end\n endgenerate\n\n// Register some command information. This information will be used\n// by the bank machines to figure out if there is something behind it\n// in the queue that require hi priority.\n\n input [2:0] cmd;\n output reg was_wr;\n always @(posedge clk) was_wr <= #TCQ\n cmd[0] && ~(periodic_rd_r && ~periodic_rd_ack_r_lcl);\n\n input hi_priority;\n output reg was_priority;\n always @(posedge clk) begin\n if (hi_priority)\n was_priority <= #TCQ 1'b1;\n else\n was_priority <= #TCQ 1'b0;\n end\n\n\n// DRAM maintenance (refresh and ZQ) and self-refresh controller\n\n input maint_req_r;\n reg maint_wip_r_lcl;\n output wire maint_wip_r;\n assign maint_wip_r = maint_wip_r_lcl;\n wire maint_idle_lcl;\n output wire maint_idle;\n assign maint_idle = maint_idle_lcl;\n input maint_zq_r;\n input maint_sre_r;\n input maint_srx_r;\n input [nBANK_MACHS-1:0] maint_hit;\n input [nBANK_MACHS-1:0] bm_end;\n wire start_maint;\n wire maint_end;\n\n generate begin : maint_controller\n\n// Idle when not (maintenance work in progress (wip), OR maintenance\n// starting tick).\n assign maint_idle_lcl = ~(maint_req_r && ~periodic_rd_cntr_r) && ~maint_wip_r_lcl;\n\n// Maintenance work in progress starts with maint_reg_r tick, terminated\n// with maint_end tick. maint_end tick is generated by the RFC/ZQ/XSDLL timer\n// below.\n wire maint_wip_ns =\n ~rst && ~maint_end && (maint_wip_r_lcl || (maint_req_r && ~periodic_rd_cntr_r));\n always @(posedge clk) maint_wip_r_lcl <= #TCQ maint_wip_ns;\n\n// Keep track of which bank machines hit on the maintenance request\n// when the request is made. As bank machines complete, an assertion\n// of the bm_end signal clears the correspoding bit in the\n// maint_hit_busies_r vector. Eventually, all bits should clear and\n// the maintenance operation will proceed. ZQ and self-refresh hit on all\n// non idle banks. Refresh hits only on non idle banks with the same rank as\n// the refresh request.\n wire [nBANK_MACHS-1:0] clear_vector = {nBANK_MACHS{rst}} | bm_end;\n wire [nBANK_MACHS-1:0] maint_zq_hits = {nBANK_MACHS{maint_idle_lcl}} &\n (maint_hit | {nBANK_MACHS{maint_zq_r}}) & ~idle_ns;\n wire [nBANK_MACHS-1:0] maint_sre_hits = {nBANK_MACHS{maint_idle_lcl}} &\n (maint_hit | {nBANK_MACHS{maint_sre_r}}) & ~idle_ns;\n reg [nBANK_MACHS-1:0] maint_hit_busies_r;\n wire [nBANK_MACHS-1:0] maint_hit_busies_ns =\n ~clear_vector & (maint_hit_busies_r | maint_zq_hits | maint_sre_hits);\n always @(posedge clk) maint_hit_busies_r <= #TCQ maint_hit_busies_ns;\n\n// Queue is clear of requests conflicting with maintenance.\n wire maint_clear = ~maint_idle_lcl && ~|maint_hit_busies_ns;\n\n// Ready to start sending maintenance commands.\n wire maint_rdy = maint_clear;\n reg maint_rdy_r1;\n reg maint_srx_r1;\n always @(posedge clk) maint_rdy_r1 <= #TCQ maint_rdy;\n always @(posedge clk) maint_srx_r1 <= #TCQ maint_srx_r;\n assign start_maint = maint_rdy && ~maint_rdy_r1 || maint_srx_r && ~maint_srx_r1;\n\n end // block: maint_controller\n endgenerate\n\n\n// Figure out how many maintenance commands to send, and send them.\n input [7:0] slot_0_present;\n input [7:0] slot_1_present;\n reg insert_maint_r_lcl;\n output wire insert_maint_r;\n assign insert_maint_r = insert_maint_r_lcl;\n\n generate begin : generate_maint_cmds\n\n// Count up how many slots are occupied. This tells\n// us how many ZQ, SRE or SRX commands to send out.\n reg [RANK_WIDTH:0] present_count;\n wire [7:0] present = slot_0_present | slot_1_present;\n always @(/*AS*/present) begin\n present_count = {RANK_WIDTH{1'b0}};\n for (i=0; i<8; i=i+1)\n present_count = present_count + {{RANK_WIDTH{1'b0}}, present[i]};\n end\n\n// For refresh, there is only a single command sent. For\n// ZQ, SRE and SRX, each rank present will receive a command. The counter\n// below counts down the number of ranks present.\n reg [RANK_WIDTH:0] send_cnt_ns;\n reg [RANK_WIDTH:0] send_cnt_r;\n always @(/*AS*/maint_zq_r or maint_sre_r or maint_srx_r or present_count\n or rst or send_cnt_r or start_maint)\n if (rst) send_cnt_ns = 4'b0;\n else begin\n send_cnt_ns = send_cnt_r;\n if (start_maint && (maint_zq_r || maint_sre_r || maint_srx_r)) send_cnt_ns = present_count;\n if (|send_cnt_ns)\n send_cnt_ns = send_cnt_ns - ONE[RANK_WIDTH-1:0];\n end\n always @(posedge clk) send_cnt_r <= #TCQ send_cnt_ns;\n\n// Insert a maintenance command for start_maint, or when the sent count\n// is not zero.\n wire insert_maint_ns = start_maint || |send_cnt_r;\n\n always @(posedge clk) insert_maint_r_lcl <= #TCQ insert_maint_ns;\n end // block: generate_maint_cmds\n endgenerate\n\n\n// RFC ZQ XSDLL timer. Generates delay from refresh, self-refresh exit or ZQ\n// command until the end of the maintenance operation.\n\n// Compute values for RFC, ZQ and XSDLL periods.\n localparam nRFC_CLKS = (nCK_PER_CLK == 1) ?\n nRFC :\n (nCK_PER_CLK == 2) ?\n ((nRFC/2) + (nRFC%2)) :\n // (nCK_PER_CLK == 4)\n ((nRFC/4) + ((nRFC%4) ? 1 : 0));\n\n localparam nZQCS_CLKS = (nCK_PER_CLK == 1) ?\n tZQCS :\n (nCK_PER_CLK == 2) ?\n ((tZQCS/2) + (tZQCS%2)) :\n // (nCK_PER_CLK == 4)\n ((tZQCS/4) + ((tZQCS%4) ? 1 : 0));\n \n localparam nXSDLL_CLKS = (nCK_PER_CLK == 1) ?\n nXSDLL :\n (nCK_PER_CLK == 2) ?\n ((nXSDLL/2) + (nXSDLL%2)) :\n // (nCK_PER_CLK == 4)\n ((nXSDLL/4) + ((nXSDLL%4) ? 1 : 0));\n\n localparam RFC_ZQ_TIMER_WIDTH = clogb2(nXSDLL_CLKS + 1);\n\n localparam THREE = 3;\n\n generate begin : rfc_zq_xsdll_timer\n\n reg [RFC_ZQ_TIMER_WIDTH-1:0] rfc_zq_xsdll_timer_ns;\n reg [RFC_ZQ_TIMER_WIDTH-1:0] rfc_zq_xsdll_timer_r;\n\n always @(/*AS*/insert_maint_r_lcl or maint_zq_r or maint_sre_r or maint_srx_r\n or rfc_zq_xsdll_timer_r or rst) begin\n rfc_zq_xsdll_timer_ns = rfc_zq_xsdll_timer_r;\n if (rst) rfc_zq_xsdll_timer_ns = {RFC_ZQ_TIMER_WIDTH{1'b0}};\n else if (insert_maint_r_lcl) rfc_zq_xsdll_timer_ns = maint_zq_r ?\n nZQCS_CLKS :\n maint_sre_r ?\n {RFC_ZQ_TIMER_WIDTH{1'b0}} :\n maint_srx_r ?\n nXSDLL_CLKS :\n nRFC_CLKS;\n else if (|rfc_zq_xsdll_timer_r) rfc_zq_xsdll_timer_ns =\n rfc_zq_xsdll_timer_r - ONE[RFC_ZQ_TIMER_WIDTH-1:0];\n end\n always @(posedge clk) rfc_zq_xsdll_timer_r <= #TCQ rfc_zq_xsdll_timer_ns;\n\n// Based on rfc_zq_xsdll_timer_r, figure out when to release any bank\n// machines waiting to send an activate. Need to add two to the end count.\n// One because the counter starts a state after the insert_refresh_r, and\n// one more because bm_end to insert_refresh_r is one state shorter\n// than bm_end to rts_row.\n assign maint_end = (rfc_zq_xsdll_timer_r == THREE[RFC_ZQ_TIMER_WIDTH-1:0]);\n end // block: rfc_zq_xsdll_timer\n endgenerate\n\n\nendmodule // bank_common\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_bank_compare.v", "content": "//*****************************************************************************\n// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor : Xilinx\n// \\ \\ \\/ Version : %version\n// \\ \\ Application : MIG\n// / / Filename : bank_compare.v\n// /___/ /\\ Date Last Modified : $date$\n// \\ \\ / \\ Date Created : Tue Jun 30 2009\n// \\___\\/\\___\\\n//\n//Device : 7-Series\n//Design Name : DDR3 SDRAM\n//Purpose :\n//Reference :\n//Revision History :\n//*****************************************************************************\n\n// This block stores the request for this bank machine.\n//\n// All possible new requests are compared against the request stored\n// here. The compare results are shared with the bank machines and\n// is used to determine where to enqueue a new request.\n\n`timescale 1ps/1ps\n\nmodule mig_7series_v4_0_bank_compare #\n (parameter BANK_WIDTH = 3,\n parameter TCQ = 100,\n parameter BURST_MODE = \"8\",\n parameter COL_WIDTH = 12,\n parameter DATA_BUF_ADDR_WIDTH = 8,\n parameter ECC = \"OFF\",\n parameter RANK_WIDTH = 2,\n parameter RANKS = 4,\n parameter ROW_WIDTH = 16)\n (/*AUTOARG*/\n // Outputs\n req_data_buf_addr_r, req_periodic_rd_r, req_size_r, rd_wr_r,\n req_rank_r, req_bank_r, req_row_r, req_wr_r, req_priority_r,\n rb_hit_busy_r, rb_hit_busy_ns, row_hit_r, maint_hit, col_addr,\n req_ras, req_cas, row_cmd_wr, row_addr, rank_busy_r,\n // Inputs\n clk, idle_ns, idle_r, data_buf_addr, periodic_rd_insert, size, cmd,\n sending_col, rank, periodic_rd_rank_r, bank, row, col, hi_priority,\n maint_rank_r, maint_zq_r, maint_sre_r, auto_pre_r, rd_half_rmw, act_wait_r\n );\n\n input clk;\n\n input idle_ns;\n input idle_r;\n\n input [DATA_BUF_ADDR_WIDTH-1:0]data_buf_addr;\n output reg [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r;\n wire [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_ns =\n idle_r\n ? data_buf_addr\n : req_data_buf_addr_r;\n always @(posedge clk) req_data_buf_addr_r <= #TCQ req_data_buf_addr_ns;\n\n input periodic_rd_insert;\n\n reg req_periodic_rd_r_lcl;\n wire req_periodic_rd_ns = idle_ns\n ? periodic_rd_insert\n : req_periodic_rd_r_lcl;\n always @(posedge clk) req_periodic_rd_r_lcl <= #TCQ req_periodic_rd_ns;\n output wire req_periodic_rd_r;\n assign req_periodic_rd_r = req_periodic_rd_r_lcl;\n\n input size;\n wire req_size_r_lcl;\n generate\n if (BURST_MODE == \"4\") begin : burst_mode_4\n assign req_size_r_lcl = 1'b0;\n end\n else\n if (BURST_MODE == \"8\") begin : burst_mode_8\n assign req_size_r_lcl = 1'b1;\n end\n else\n if (BURST_MODE == \"OTF\") begin : burst_mode_otf\n reg req_size;\n wire req_size_ns = idle_ns\n ? (periodic_rd_insert || size)\n : req_size;\n always @(posedge clk) req_size <= #TCQ req_size_ns;\n assign req_size_r_lcl = req_size;\n end\n endgenerate\n output wire req_size_r;\n assign req_size_r = req_size_r_lcl;\n\n\n\n input [2:0] cmd;\n reg [2:0] req_cmd_r;\n wire [2:0] req_cmd_ns = idle_ns\n ? (periodic_rd_insert ? 3'b001 : cmd)\n : req_cmd_r;\n \n always @(posedge clk) req_cmd_r <= #TCQ req_cmd_ns;\n\n`ifdef MC_SVA\n rd_wr_only_wo_ecc: assert property\n (@(posedge clk) ((ECC != \"OFF\") || idle_ns || ~|req_cmd_ns[2:1]));\n`endif\n \n input sending_col;\n reg rd_wr_r_lcl;\n wire rd_wr_ns = idle_ns \n ? ((req_cmd_ns[1:0] == 2'b11) || req_cmd_ns[0])\n : ~sending_col && rd_wr_r_lcl;\n always @(posedge clk) rd_wr_r_lcl <= #TCQ rd_wr_ns;\n output wire rd_wr_r;\n assign rd_wr_r = rd_wr_r_lcl;\n\n input [RANK_WIDTH-1:0] rank;\n input [RANK_WIDTH-1:0] periodic_rd_rank_r;\n reg [RANK_WIDTH-1:0] req_rank_r_lcl = {RANK_WIDTH{1'b0}};\n reg [RANK_WIDTH-1:0] req_rank_ns = {RANK_WIDTH{1'b0}};\n generate\n if (RANKS != 1) begin\n always @(/*AS*/idle_ns or periodic_rd_insert\n or periodic_rd_rank_r or rank or req_rank_r_lcl) req_rank_ns = idle_ns\n ? periodic_rd_insert\n ? periodic_rd_rank_r\n : rank\n : req_rank_r_lcl;\n always @(posedge clk) req_rank_r_lcl <= #TCQ req_rank_ns;\n end\n endgenerate\n output wire [RANK_WIDTH-1:0] req_rank_r;\n assign req_rank_r = req_rank_r_lcl;\n\n input [BANK_WIDTH-1:0] bank;\n reg [BANK_WIDTH-1:0] req_bank_r_lcl;\n wire [BANK_WIDTH-1:0] req_bank_ns = idle_ns ? bank : req_bank_r_lcl;\n always @(posedge clk) req_bank_r_lcl <= #TCQ req_bank_ns;\n output wire[BANK_WIDTH-1:0] req_bank_r;\n assign req_bank_r = req_bank_r_lcl;\n\n input [ROW_WIDTH-1:0] row;\n reg [ROW_WIDTH-1:0] req_row_r_lcl;\n wire [ROW_WIDTH-1:0] req_row_ns = idle_ns ? row : req_row_r_lcl;\n always @(posedge clk) req_row_r_lcl <= #TCQ req_row_ns;\n output wire [ROW_WIDTH-1:0] req_row_r;\n assign req_row_r = req_row_r_lcl;\n\n // Make req_col_r as wide as the max row address. This\n // makes it easier to deal with indexing different column widths.\n input [COL_WIDTH-1:0] col;\n reg [15:0] req_col_r = 16'b0;\n wire [COL_WIDTH-1:0] req_col_ns = idle_ns ? col : req_col_r[COL_WIDTH-1:0];\n always @(posedge clk) req_col_r[COL_WIDTH-1:0] <= #TCQ req_col_ns;\n\n reg req_wr_r_lcl;\n wire req_wr_ns = idle_ns \n ? ((req_cmd_ns[1:0] == 2'b11) || ~req_cmd_ns[0])\n : req_wr_r_lcl;\n always @(posedge clk) req_wr_r_lcl <= #TCQ req_wr_ns;\n output wire req_wr_r;\n assign req_wr_r = req_wr_r_lcl;\n\n input hi_priority;\n output reg req_priority_r;\n wire req_priority_ns = idle_ns ? hi_priority : req_priority_r;\n always @(posedge clk) req_priority_r <= #TCQ req_priority_ns;\n\n wire rank_hit = (req_rank_r_lcl == (periodic_rd_insert\n ? periodic_rd_rank_r\n : rank));\n wire bank_hit = (req_bank_r_lcl == bank);\n wire rank_bank_hit = rank_hit && bank_hit;\n\n output reg rb_hit_busy_r; // rank-bank hit on non idle row machine\n wire rb_hit_busy_ns_lcl;\n assign rb_hit_busy_ns_lcl = rank_bank_hit && ~idle_ns;\n output wire rb_hit_busy_ns;\n assign rb_hit_busy_ns = rb_hit_busy_ns_lcl;\n\n wire row_hit_ns = (req_row_r_lcl == row);\n output reg row_hit_r;\n\n always @(posedge clk) rb_hit_busy_r <= #TCQ rb_hit_busy_ns_lcl;\n always @(posedge clk) row_hit_r <= #TCQ row_hit_ns;\n\n input [RANK_WIDTH-1:0] maint_rank_r;\n input maint_zq_r;\n input maint_sre_r;\n output wire maint_hit;\n assign maint_hit = (req_rank_r_lcl == maint_rank_r) || maint_zq_r || maint_sre_r;\n\n// Assemble column address. Structure to be the same\n// width as the row address. This makes it easier\n// for the downstream muxing. Depending on the sizes\n// of the row and column addresses, fill in as appropriate.\n input auto_pre_r;\n input rd_half_rmw;\n reg [15:0] col_addr_template = 16'b0;\n always @(/*AS*/auto_pre_r or rd_half_rmw or req_col_r\n or req_size_r_lcl) begin\n col_addr_template = req_col_r;\n col_addr_template[10] = auto_pre_r && ~rd_half_rmw;\n col_addr_template[11] = req_col_r[10];\n col_addr_template[12] = req_size_r_lcl;\n col_addr_template[13] = req_col_r[11];\n end\n output wire [ROW_WIDTH-1:0] col_addr;\n assign col_addr = col_addr_template[ROW_WIDTH-1:0];\n\n output wire req_ras;\n output wire req_cas;\n output wire row_cmd_wr;\n input act_wait_r;\n assign req_ras = 1'b0;\n assign req_cas = 1'b1;\n assign row_cmd_wr = act_wait_r;\n\n output reg [ROW_WIDTH-1:0] row_addr;\n always @(/*AS*/act_wait_r or req_row_r_lcl) begin\n row_addr = req_row_r_lcl;\n// This causes all precharges to be precharge single bank command.\n if (~act_wait_r) row_addr[10] = 1'b0;\n end\n\n// Indicate which, if any, rank this bank machine is busy with.\n// Not registering the result would probably be more accurate, but\n// would create timing issues. This is used for refresh banking, perfect\n// accuracy is not required.\n localparam ONE = 1;\n output reg [RANKS-1:0] rank_busy_r;\n wire [RANKS-1:0] rank_busy_ns = {RANKS{~idle_ns}} & (ONE[RANKS-1:0] << req_rank_ns);\n always @(posedge clk) rank_busy_r <= #TCQ rank_busy_ns;\n\nendmodule // bank_compare\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_bank_mach.v", "content": "//*****************************************************************************\n// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor : Xilinx\n// \\ \\ \\/ Version : %version\n// \\ \\ Application : MIG\n// / / Filename : bank_mach.v\n// /___/ /\\ Date Last Modified : $date$\n// \\ \\ / \\ Date Created : Tue Jun 30 2009\n// \\___\\/\\___\\\n//\n//Device : 7-Series\n//Design Name : DDR3 SDRAM\n//Purpose :\n//Reference :\n//Revision History :\n//*****************************************************************************\n\n// Top level bank machine block. A structural block instantiating the configured\n// individual bank machines, and a common block that computes various items shared\n// by all bank machines.\n\n`timescale 1ps/1ps\n\nmodule mig_7series_v4_0_bank_mach #\n (\n parameter TCQ = 100,\n parameter EVEN_CWL_2T_MODE = \"OFF\",\n parameter ADDR_CMD_MODE = \"1T\",\n parameter BANK_WIDTH = 3,\n parameter BM_CNT_WIDTH = 2,\n parameter BURST_MODE = \"8\",\n parameter COL_WIDTH = 12,\n parameter CS_WIDTH = 4,\n parameter CL = 5,\n parameter CWL = 5,\n parameter DATA_BUF_ADDR_WIDTH = 8,\n parameter DRAM_TYPE = \"DDR3\",\n parameter EARLY_WR_DATA_ADDR = \"OFF\",\n parameter ECC = \"OFF\",\n parameter LOW_IDLE_CNT = 1,\n parameter nBANK_MACHS = 4,\n parameter nCK_PER_CLK = 2,\n parameter nCS_PER_RANK = 1,\n parameter nOP_WAIT = 0,\n parameter nRAS = 20,\n parameter nRCD = 5,\n parameter nRFC = 44,\n parameter nRTP = 4,\n parameter CKE_ODT_AUX = \"FALSE\", //Parameter to turn on/off the aux_out signal\n parameter nRP = 10,\n parameter nSLOTS = 2,\n parameter nWR = 6,\n parameter nXSDLL = 512,\n parameter ORDERING = \"NORM\",\n parameter RANK_BM_BV_WIDTH = 16,\n parameter RANK_WIDTH = 2,\n parameter RANKS = 4,\n parameter ROW_WIDTH = 16,\n parameter RTT_NOM = \"40\",\n parameter RTT_WR = \"120\",\n parameter STARVE_LIMIT = 2,\n parameter SLOT_0_CONFIG = 8'b0000_0101,\n parameter SLOT_1_CONFIG = 8'b0000_1010,\n parameter tZQCS = 64\n )\n (/*AUTOARG*/\n // Outputs\n output accept, // From bank_common0 of bank_common.v\n output accept_ns, // From bank_common0 of bank_common.v\n output [BM_CNT_WIDTH-1:0] bank_mach_next, // From bank_common0 of bank_common.v\n output [ROW_WIDTH-1:0] col_a, // From arb_mux0 of arb_mux.v\n output [BANK_WIDTH-1:0] col_ba, // From arb_mux0 of arb_mux.v\n output [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr,// From arb_mux0 of arb_mux.v\n output col_periodic_rd, // From arb_mux0 of arb_mux.v\n output [RANK_WIDTH-1:0] col_ra, // From arb_mux0 of arb_mux.v\n output col_rmw, // From arb_mux0 of arb_mux.v\n output col_rd_wr,\n output [ROW_WIDTH-1:0] col_row, // From arb_mux0 of arb_mux.v\n output col_size, // From arb_mux0 of arb_mux.v\n output [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr,// From arb_mux0 of arb_mux.v\n output wire [nCK_PER_CLK-1:0] mc_ras_n,\n output wire [nCK_PER_CLK-1:0] mc_cas_n,\n output wire [nCK_PER_CLK-1:0] mc_we_n,\n output wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address,\n output wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank,\n output wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n,\n output wire [1:0] mc_odt,\n output wire [nCK_PER_CLK-1:0] mc_cke,\n output wire [3:0] mc_aux_out0,\n output wire [3:0] mc_aux_out1,\n output [2:0] mc_cmd,\n output [5:0] mc_data_offset,\n output [5:0] mc_data_offset_1,\n output [5:0] mc_data_offset_2,\n output [1:0] mc_cas_slot,\n output insert_maint_r1, // From arb_mux0 of arb_mux.v\n output maint_wip_r, // From bank_common0 of bank_common.v\n output wire [nBANK_MACHS-1:0] sending_row,\n output wire [nBANK_MACHS-1:0] sending_col,\n output wire sent_col,\n output wire sent_col_r,\n output periodic_rd_ack_r,\n output wire [RANK_BM_BV_WIDTH-1:0] act_this_rank_r,\n output wire [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r,\n output wire [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r,\n output wire [(RANKS*nBANK_MACHS)-1:0] rank_busy_r,\n output idle,\n\n // Inputs\n input [BANK_WIDTH-1:0] bank, // To bank0 of bank_cntrl.v\n input [6*RANKS-1:0] calib_rddata_offset,\n input [6*RANKS-1:0] calib_rddata_offset_1,\n input [6*RANKS-1:0] calib_rddata_offset_2,\n input clk, // To bank0 of bank_cntrl.v, ...\n input [2:0] cmd, // To bank0 of bank_cntrl.v, ...\n input [COL_WIDTH-1:0] col, // To bank0 of bank_cntrl.v\n input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr,// To bank0 of bank_cntrl.v\n input init_calib_complete, // To bank_common0 of bank_common.v\n input phy_rddata_valid, // To bank0 of bank_cntrl.v\n input dq_busy_data, // To bank0 of bank_cntrl.v\n input hi_priority, // To bank0 of bank_cntrl.v, ...\n input [RANKS-1:0] inhbt_act_faw_r, // To bank0 of bank_cntrl.v\n input [RANKS-1:0] inhbt_rd, // To bank0 of bank_cntrl.v\n input [RANKS-1:0] inhbt_wr, // To bank0 of bank_cntrl.v\n input [RANK_WIDTH-1:0] maint_rank_r, // To bank0 of bank_cntrl.v, ...\n input maint_req_r, // To bank0 of bank_cntrl.v, ...\n input maint_zq_r, // To bank0 of bank_cntrl.v, ...\n input maint_sre_r, // To bank0 of bank_cntrl.v, ...\n input maint_srx_r, // To bank0 of bank_cntrl.v, ...\n input periodic_rd_r, // To bank_common0 of bank_common.v\n input [RANK_WIDTH-1:0] periodic_rd_rank_r, // To bank0 of bank_cntrl.v\n input phy_mc_ctl_full,\n input phy_mc_cmd_full,\n input phy_mc_data_full,\n input [RANK_WIDTH-1:0] rank, // To bank0 of bank_cntrl.v\n input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr, // To bank0 of bank_cntrl.v\n input rd_rmw, // To bank0 of bank_cntrl.v\n input [ROW_WIDTH-1:0] row, // To bank0 of bank_cntrl.v\n input rst, // To bank0 of bank_cntrl.v, ...\n input size, // To bank0 of bank_cntrl.v\n input [7:0] slot_0_present, // To bank_common0 of bank_common.v, ...\n input [7:0] slot_1_present, // To bank_common0 of bank_common.v, ...\n input use_addr\n );\n\n function integer clogb2 (input integer size); // ceiling logb2\n begin\n size = size - 1;\n for (clogb2=1; size>1; clogb2=clogb2+1)\n size = size >> 1;\n end\n endfunction // clogb2\n\n localparam RANK_VECT_INDX = (nBANK_MACHS *RANK_WIDTH) - 1;\n localparam BANK_VECT_INDX = (nBANK_MACHS * BANK_WIDTH) - 1;\n localparam ROW_VECT_INDX = (nBANK_MACHS * ROW_WIDTH) - 1;\n localparam DATA_BUF_ADDR_VECT_INDX = (nBANK_MACHS * DATA_BUF_ADDR_WIDTH) - 1;\n localparam nRAS_CLKS = (nCK_PER_CLK == 1) ? nRAS : (nCK_PER_CLK == 2) ? ((nRAS/2) + (nRAS % 2)) : ((nRAS/4) + ((nRAS%4) ? 1 : 0));\n localparam nWTP = CWL + ((BURST_MODE == \"4\") ? 2 : 4) + nWR;\n// Unless 2T mode, add one to nWTP_CLKS for 2:1 mode. This accounts for loss of\n// one DRAM CK due to column command to row command fixed offset. In 2T mode,\n// Add the remainder. In 4:1 mode, the fixed offset is -2. Add 2 unless in 2T\n// mode, in which case we add 1 if the remainder exceeds the fixed offset.\n localparam nWTP_CLKS = (nCK_PER_CLK == 1)\n ? nWTP :\n (nCK_PER_CLK == 2)\n ? (nWTP/2) + ((ADDR_CMD_MODE == \"2T\") ? nWTP%2 : 1) :\n (nWTP/4) + ((ADDR_CMD_MODE == \"2T\") ? (nWTP%4 > 2 ? 2 : 1) : 2);\n localparam RAS_TIMER_WIDTH = clogb2(((nRAS_CLKS > nWTP_CLKS)\n ? nRAS_CLKS\n : nWTP_CLKS) - 1);\n\n /*AUTOINPUT*/\n // Beginning of automatic inputs (from unused autoinst inputs)\n\n // End of automatics\n\n /*AUTOOUTPUT*/\n // Beginning of automatic outputs (from unused autoinst outputs)\n\n // End of automatics\n\n /*AUTOWIRE*/\n // Beginning of automatic wires (for undeclared instantiated-module outputs)\n wire accept_internal_r; // From bank_common0 of bank_common.v\n wire accept_req; // From bank_common0 of bank_common.v\n wire adv_order_q; // From bank_common0 of bank_common.v\n wire [BM_CNT_WIDTH-1:0] idle_cnt; // From bank_common0 of bank_common.v\n wire insert_maint_r; // From bank_common0 of bank_common.v\n wire low_idle_cnt_r; // From bank_common0 of bank_common.v\n wire maint_idle; // From bank_common0 of bank_common.v\n wire [BM_CNT_WIDTH-1:0] order_cnt; // From bank_common0 of bank_common.v\n wire periodic_rd_insert; // From bank_common0 of bank_common.v\n wire [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt; // From bank_common0 of bank_common.v\n wire sent_row; // From arb_mux0 of arb_mux.v\n wire was_priority; // From bank_common0 of bank_common.v\n wire was_wr; // From bank_common0 of bank_common.v\n // End of automatics\n\n wire [RANK_WIDTH-1:0] rnk_config;\n wire rnk_config_strobe;\n wire rnk_config_kill_rts_col;\n wire rnk_config_valid_r;\n \n wire [nBANK_MACHS-1:0] rts_row;\n wire [nBANK_MACHS-1:0] rts_col;\n wire [nBANK_MACHS-1:0] rts_pre;\n wire [nBANK_MACHS-1:0] col_rdy_wr;\n wire [nBANK_MACHS-1:0] rtc;\n wire [nBANK_MACHS-1:0] sending_pre;\n\n wire [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r;\n wire [nBANK_MACHS-1:0] req_size_r;\n wire [RANK_VECT_INDX:0] req_rank_r;\n wire [BANK_VECT_INDX:0] req_bank_r;\n wire [ROW_VECT_INDX:0] req_row_r;\n wire [ROW_VECT_INDX:0] col_addr;\n wire [nBANK_MACHS-1:0] req_periodic_rd_r;\n wire [nBANK_MACHS-1:0] req_wr_r;\n wire [nBANK_MACHS-1:0] rd_wr_r;\n wire [nBANK_MACHS-1:0] req_ras;\n wire [nBANK_MACHS-1:0] req_cas;\n wire [ROW_VECT_INDX:0] row_addr;\n wire [nBANK_MACHS-1:0] row_cmd_wr;\n wire [nBANK_MACHS-1:0] demand_priority;\n wire [nBANK_MACHS-1:0] demand_act_priority;\n\n wire [nBANK_MACHS-1:0] idle_ns;\n wire [nBANK_MACHS-1:0] rb_hit_busy_r;\n wire [nBANK_MACHS-1:0] bm_end;\n wire [nBANK_MACHS-1:0] passing_open_bank;\n wire [nBANK_MACHS-1:0] ordered_r;\n wire [nBANK_MACHS-1:0] ordered_issued;\n wire [nBANK_MACHS-1:0] rb_hit_busy_ns;\n wire [nBANK_MACHS-1:0] maint_hit;\n wire [nBANK_MACHS-1:0] idle_r;\n wire [nBANK_MACHS-1:0] head_r;\n wire [nBANK_MACHS-1:0] start_rcd;\n\n wire [nBANK_MACHS-1:0] end_rtp;\n wire [nBANK_MACHS-1:0] op_exit_req;\n wire [nBANK_MACHS-1:0] op_exit_grant;\n wire [nBANK_MACHS-1:0] start_pre_wait;\n\n wire [(RAS_TIMER_WIDTH*nBANK_MACHS)-1:0] ras_timer_ns;\n\n genvar ID;\n generate for (ID=0; ID 1) begin : compute_tail\n reg tail_ns;\n always @(accept_req or accept_this_bm\n or bm_end_in or bm_end_lcl or idle_r_lcl\n or idlers_above or rb_hit_busy_r or rst or tail_r_lcl) begin\n if (rst) tail_ns = (ID == nBANK_MACHS);\n// The order of the statements below is important in the case where\n// another bank machine is retiring and this bank machine is accepting.\n else begin\n tail_ns = tail_r_lcl;\n if ((accept_req && rb_hit_busy_r) ||\n (|bm_end_in[`BM_SHARED_BV] && idle_r_lcl))\n tail_ns = 1'b0;\n if (accept_this_bm || (bm_end_lcl && ~idlers_above)) tail_ns = 1'b1;\n end\n end\n always @(posedge clk) tail_r_lcl <= #TCQ tail_ns;\n end // if (nBANK_MACHS > 1)\n endgenerate\n output wire tail_r;\n assign tail_r = tail_r_lcl;\n\n wire clear_req = bm_end_lcl || rst;\n\n// Is this entry in the idle queue?\n reg idle_ns_lcl;\n always @(/*AS*/accept_this_bm or clear_req or idle_r_lcl) begin\n idle_ns_lcl = idle_r_lcl;\n if (accept_this_bm) idle_ns_lcl = 1'b0;\n if (clear_req) idle_ns_lcl = 1'b1;\n end\n always @(posedge clk) idle_r_lcl <= #TCQ idle_ns_lcl;\n output wire idle_ns;\n assign idle_ns = idle_ns_lcl;\n output wire idle_r;\n assign idle_r = idle_r_lcl;\n\n// Maintenance hitting on this active bank machine is in progress.\n input maint_idle;\n input maint_hit;\n wire maint_hit_this_bm = ~maint_idle && maint_hit;\n\n// Does new request hit on this bank machine while it is able to pass the\n// open bank?\n input row_hit_r;\n input pre_wait_r;\n wire pass_open_bank_eligible =\n tail_r_lcl && rb_hit_busy_r && row_hit_r && ~pre_wait_r;\n\n// Set pass open bank bit, but not if request preceded active maintenance.\n reg wait_for_maint_r_lcl;\n reg pass_open_bank_r_lcl;\n wire pass_open_bank_ns_lcl = ~clear_req &&\n (pass_open_bank_r_lcl ||\n (accept_req && pass_open_bank_eligible &&\n (~maint_hit_this_bm || wait_for_maint_r_lcl)));\n always @(posedge clk) pass_open_bank_r_lcl <= #TCQ pass_open_bank_ns_lcl;\n output wire pass_open_bank_ns;\n assign pass_open_bank_ns = pass_open_bank_ns_lcl;\n output wire pass_open_bank_r;\n assign pass_open_bank_r = pass_open_bank_r_lcl;\n\n`ifdef MC_SVA\n pass_open_bank: cover property (@(posedge clk) (~rst && pass_open_bank_ns));\n pass_open_bank_killed_by_maint: cover property (@(posedge clk)\n (~rst && accept_req && pass_open_bank_eligible &&\n maint_hit_this_bm && ~wait_for_maint_r_lcl));\n pass_open_bank_following_maint: cover property (@(posedge clk)\n (~rst && accept_req && pass_open_bank_eligible &&\n maint_hit_this_bm && wait_for_maint_r_lcl));\n`endif\n\n// Should the column command be sent with the auto precharge bit set? This\n// will happen when it is detected that next request is to a different row,\n// or the next reqest is the next request is refresh to this rank.\n reg auto_pre_r_lcl;\n reg auto_pre_ns;\n input allow_auto_pre;\n always @(/*AS*/accept_req or allow_auto_pre or auto_pre_r_lcl\n or clear_req or maint_hit_this_bm or rb_hit_busy_r\n or row_hit_r or tail_r_lcl or wait_for_maint_r_lcl) begin\n auto_pre_ns = auto_pre_r_lcl;\n if (clear_req) auto_pre_ns = 1'b0;\n else\n if (accept_req && tail_r_lcl && allow_auto_pre && rb_hit_busy_r &&\n (~row_hit_r || (maint_hit_this_bm && ~wait_for_maint_r_lcl)))\n auto_pre_ns = 1'b1;\n end\n always @(posedge clk) auto_pre_r_lcl <= #TCQ auto_pre_ns;\n output wire auto_pre_r;\n assign auto_pre_r = auto_pre_r_lcl;\n\n`ifdef MC_SVA\n auto_precharge: cover property (@(posedge clk) (~rst && auto_pre_ns));\n maint_triggers_auto_precharge: cover property (@(posedge clk)\n (~rst && auto_pre_ns && ~auto_pre_r && row_hit_r));\n`endif\n\n// Determine when the current request is finished.\n input sending_col;\n input req_wr_r;\n input rd_wr_r;\n wire sending_col_not_rmw_rd = sending_col && !(req_wr_r && rd_wr_r);\n input bank_wait_in_progress;\n input precharge_bm_end;\n reg pre_bm_end_r;\n wire pre_bm_end_ns = precharge_bm_end ||\n (bank_wait_in_progress && pass_open_bank_ns_lcl);\n always @(posedge clk) pre_bm_end_r <= #TCQ pre_bm_end_ns;\n assign bm_end_lcl = \n pre_bm_end_r || (sending_col_not_rmw_rd && pass_open_bank_r_lcl);\n output wire bm_end;\n assign bm_end = bm_end_lcl;\n\n// Determine that the open bank should be passed to the successor bank machine.\n reg pre_passing_open_bank_r;\n wire pre_passing_open_bank_ns =\n bank_wait_in_progress && pass_open_bank_ns_lcl;\n always @(posedge clk) pre_passing_open_bank_r <= #TCQ\n pre_passing_open_bank_ns;\n output wire passing_open_bank;\n assign passing_open_bank =\n pre_passing_open_bank_r || (sending_col_not_rmw_rd && pass_open_bank_r_lcl);\n\n reg ordered_ns;\n wire set_order_q = ((ORDERING == \"STRICT\") || ((ORDERING == \"NORM\") &&\n req_wr_r)) && accept_this_bm;\n\n wire ordered_issued_lcl = \n sending_col_not_rmw_rd && !(req_wr_r && rd_wr_r) &&\n ((ORDERING == \"STRICT\") || ((ORDERING == \"NORM\") && req_wr_r));\n output wire ordered_issued;\n assign ordered_issued = ordered_issued_lcl;\n\n reg ordered_r_lcl;\n always @(/*AS*/ordered_issued_lcl or ordered_r_lcl or rst\n or set_order_q) begin\n if (rst) ordered_ns = 1'b0;\n else begin\n ordered_ns = ordered_r_lcl;\n// Should never see accept_this_bm and adv_order_q at the same time.\n if (set_order_q) ordered_ns = 1'b1;\n if (ordered_issued_lcl) ordered_ns = 1'b0;\n end\n end\n always @(posedge clk) ordered_r_lcl <= #TCQ ordered_ns;\n output wire ordered_r;\n assign ordered_r = ordered_r_lcl;\n\n// Figure out when to advance the ordering queue.\n input adv_order_q;\n input [BM_CNT_WIDTH-1:0] order_cnt;\n reg [BM_CNT_WIDTH-1:0] order_q_r;\n reg [BM_CNT_WIDTH-1:0] order_q_ns;\n always @(/*AS*/adv_order_q or order_cnt or order_q_r or rst\n or set_order_q) begin\n order_q_ns = order_q_r;\n if (rst) order_q_ns = BM_CNT_ZERO;\n if (set_order_q)\n if (adv_order_q) order_q_ns = order_cnt - BM_CNT_ONE;\n else order_q_ns = order_cnt;\n if (adv_order_q && |order_q_r) order_q_ns = order_q_r - BM_CNT_ONE;\n end\n always @(posedge clk) order_q_r <= #TCQ order_q_ns;\n\n output wire order_q_zero;\n assign order_q_zero = ~|order_q_r ||\n (adv_order_q && (order_q_r == BM_CNT_ONE)) ||\n ((ORDERING == \"NORM\") && rd_wr_r);\n\n// Keep track of which other bank machine are ahead of this one in a\n// rank-bank queue. This is necessary to know when to advance this bank\n// machine in the queue, and when to update bank state machine counter upon\n// passing a bank.\n input [(nBANK_MACHS*2)-1:0] rb_hit_busy_ns_in;\n reg [(nBANK_MACHS*2)-1:0] rb_hit_busies_r_lcl = {nBANK_MACHS*2{1'b0}};\n input [(nBANK_MACHS*2)-1:0] passing_open_bank_in;\n output reg rcv_open_bank = 1'b0;\n\n generate\n if (nBANK_MACHS > 1) begin : rb_hit_busies\n\n// The clear_vector resets bits in the rb_hit_busies vector as bank machines\n// completes requests. rst also resets all the bits.\n wire [nBANK_MACHS-2:0] clear_vector =\n ({nBANK_MACHS-1{rst}} | bm_end_in[`BM_SHARED_BV]);\n\n// As this bank machine takes on a new request, capture the vector of\n// which other bank machines are in the same queue.\n wire [`BM_SHARED_BV] rb_hit_busies_ns =\n ~clear_vector &\n (idle_ns_lcl\n ? rb_hit_busy_ns_in[`BM_SHARED_BV]\n : rb_hit_busies_r_lcl[`BM_SHARED_BV]);\n always @(posedge clk) rb_hit_busies_r_lcl[`BM_SHARED_BV] <=\n #TCQ rb_hit_busies_ns;\n\n// Compute when to advance this queue entry based on seeing other bank machines\n// in the same queue finish.\n always @(bm_end_in or rb_hit_busies_r_lcl)\n adv_queue =\n |(bm_end_in[`BM_SHARED_BV] & rb_hit_busies_r_lcl[`BM_SHARED_BV]);\n\n// Decide when to receive an open bank based on knowing this bank machine is\n// one entry from the head, and a passing_open_bank hits on the\n// rb_hit_busies vector.\n always @(idle_r_lcl\n or passing_open_bank_in or q_entry_r\n or rb_hit_busies_r_lcl) rcv_open_bank =\n |(rb_hit_busies_r_lcl[`BM_SHARED_BV] & passing_open_bank_in[`BM_SHARED_BV])\n && (q_entry_r == BM_CNT_ONE) && ~idle_r_lcl;\n end\n endgenerate\n output wire [nBANK_MACHS*2-1:0] rb_hit_busies_r;\n assign rb_hit_busies_r = rb_hit_busies_r_lcl;\n\n\n// Keep track if the queue this entry is in has priority content.\n input was_wr;\n input maint_req_r;\n reg q_has_rd_r;\n wire q_has_rd_ns = ~clear_req &&\n (q_has_rd_r || (accept_req && rb_hit_busy_r && ~was_wr) ||\n (maint_req_r && maint_hit && ~idle_r_lcl));\n always @(posedge clk) q_has_rd_r <= #TCQ q_has_rd_ns;\n output wire q_has_rd;\n assign q_has_rd = q_has_rd_r;\n\n input was_priority;\n reg q_has_priority_r;\n wire q_has_priority_ns = ~clear_req &&\n (q_has_priority_r || (accept_req && rb_hit_busy_r && was_priority));\n always @(posedge clk) q_has_priority_r <= #TCQ q_has_priority_ns;\n output wire q_has_priority;\n assign q_has_priority = q_has_priority_r;\n\n// Figure out if this entry should wait for maintenance to end.\n wire wait_for_maint_ns = ~rst && ~maint_idle &&\n (wait_for_maint_r_lcl || (maint_hit && accept_this_bm));\n always @(posedge clk) wait_for_maint_r_lcl <= #TCQ wait_for_maint_ns;\n output wire wait_for_maint_r;\n assign wait_for_maint_r = wait_for_maint_r_lcl;\n\nendmodule // bank_queue\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_bank_state.v", "content": "//*****************************************************************************\n// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor : Xilinx\n// \\ \\ \\/ Version : %version\n// \\ \\ Application : MIG\n// / / Filename : bank_state.v\n// /___/ /\\ Date Last Modified : $date$\n// \\ \\ / \\ Date Created : Tue Jun 30 2009\n// \\___\\/\\___\\\n//\n//Device : 7-Series\n//Design Name : DDR3 SDRAM\n//Purpose :\n//Reference :\n//Revision History :\n//*****************************************************************************\n\n\n// Primary bank state machine. All bank specific timing is generated here.\n//\n// Conceptually, when a bank machine is assigned a request, conflicts are\n// checked. If there is a conflict, then the new request is added\n// to the queue for that rank-bank.\n//\n// Eventually, that request will find itself at the head of the queue for\n// its rank-bank. Forthwith, the bank machine will begin arbitration to send an\n// activate command to the DRAM. Once arbitration is successful and the\n// activate is sent, the row state machine waits the RCD delay. The RAS\n// counter is also started when the activate is sent.\n//\n// Upon completion of the RCD delay, the bank state machine will begin\n// arbitration for sending out the column command. Once the column\n// command has been sent, the bank state machine waits the RTP latency, and\n// if the command is a write, the RAS counter is loaded with the WR latency.\n//\n// When the RTP counter reaches zero, the pre charge wait state is entered.\n// Once the RAS timer reaches zero, arbitration to send a precharge command\n// begins.\n//\n// Upon successful transmission of the precharge command, the bank state\n// machine waits the precharge period and then rejoins the idle list.\n//\n// For an open rank-bank hit, a bank machine passes management of the rank-bank to\n// a bank machine that is managing the subsequent request to the same page. A bank\n// machine can either be a \"passer\" or a \"passee\" in this handoff. There\n// are two conditions that have to occur before an open bank can be passed.\n// A spatial condition, ie same rank-bank and row address. And a temporal condition,\n// ie the passee has completed it work with the bank, but has not issued a precharge.\n//\n// The spatial condition is signalled by pass_open_bank_ns. The temporal condition\n// is when the column command is issued, or when the bank_wait_in_progress\n// signal is true. Bank_wait_in_progress is true when the RTP timer is not\n// zero, or when the RAS/WR timer is not zero and the state machine is waiting\n// to send out a precharge command.\n//\n// On an open bank pass, the passer transitions from the temporal condition\n// noted above and performs the end of request processing and eventually lands\n// in the act_wait_r state.\n//\n// On an open bank pass, the passee lands in the col_wait_r state and waits\n// for its chance to send out a column command.\n//\n// Since there is a single data bus shared by all columns in all ranks, there\n// is a single column machine. The column machine is primarily in charge of\n// managing the timing on the DQ data bus. It reserves states for data transfer,\n// driver turnaround states, and preambles. It also has the ability to add\n// additional programmable delay for read to write changeovers. This read to write\n// delay is generated in the column machine which inhibits writes via the\n// inhbt_wr signal.\n//\n// There is a rank machine for every rank. The rank machines are responsible\n// for enforcing rank specific timing such as FAW, and WTR. RRD is guaranteed\n// in the bank machine since it is closely coupled to the operation of the\n// bank machine and is timing critical.\n//\n// Since a bank machine can be working on a request for any rank, all rank machines\n// inhibits are input to all bank machines. Based on the rank of the current\n// request, each bank machine selects the rank information corresponding\n// to the rank of its current request.\n//\n// Since driver turnaround states and WTR delays are so severe with DDRIII, the\n// memory interface has the ability to promote requests that use the same\n// driver as the most recent request. There is logic in this block that\n// detects when the driver for its request is the same as the driver for\n// the most recent request. In such a case, this block will send out special\n// \"same\" request early enough to eliminate dead states when there is no\n// driver changeover.\n\n\n`timescale 1ps/1ps\n`define BM_SHARED_BV (ID+nBANK_MACHS-1):(ID+1)\n\nmodule mig_7series_v4_0_bank_state #\n (\n parameter TCQ = 100,\n parameter ADDR_CMD_MODE = \"1T\",\n parameter BM_CNT_WIDTH = 2,\n parameter BURST_MODE = \"8\",\n parameter CWL = 5,\n parameter DATA_BUF_ADDR_WIDTH = 8,\n parameter DRAM_TYPE = \"DDR3\",\n parameter ECC = \"OFF\",\n parameter ID = 0,\n parameter nBANK_MACHS = 4,\n parameter nCK_PER_CLK = 2,\n parameter nOP_WAIT = 0,\n parameter nRAS_CLKS = 10,\n parameter nRP = 10,\n parameter nRTP = 4,\n parameter nRCD = 5,\n parameter nWTP_CLKS = 5,\n parameter ORDERING = \"NORM\",\n parameter RANKS = 4,\n parameter RANK_WIDTH = 4,\n parameter RAS_TIMER_WIDTH = 5,\n parameter STARVE_LIMIT = 2\n )\n (/*AUTOARG*/\n // Outputs\n start_rcd, act_wait_r, rd_half_rmw, ras_timer_ns, end_rtp,\n bank_wait_in_progress, start_pre_wait, op_exit_req, pre_wait_r,\n allow_auto_pre, precharge_bm_end, demand_act_priority, rts_row,\n act_this_rank_r, demand_priority, col_rdy_wr, rts_col, wr_this_rank_r,\n rd_this_rank_r, rts_pre, rtc,\n // Inputs\n clk, rst, bm_end, pass_open_bank_r, sending_row, sending_pre, rcv_open_bank,\n sending_col, rd_wr_r, req_wr_r, rd_data_addr, req_data_buf_addr_r,\n phy_rddata_valid, rd_rmw, ras_timer_ns_in, rb_hit_busies_r, idle_r,\n passing_open_bank, low_idle_cnt_r, op_exit_grant, tail_r,\n auto_pre_r, pass_open_bank_ns, req_rank_r, req_rank_r_in,\n start_rcd_in, inhbt_act_faw_r, wait_for_maint_r, head_r, sent_row,\n demand_act_priority_in, order_q_zero, sent_col, q_has_rd,\n q_has_priority, req_priority_r, idle_ns, demand_priority_in, inhbt_rd,\n inhbt_wr, dq_busy_data, rnk_config_strobe, rnk_config_valid_r, rnk_config,\n rnk_config_kill_rts_col, phy_mc_cmd_full, phy_mc_ctl_full, phy_mc_data_full\n );\n\n function integer clogb2 (input integer size); // ceiling logb2\n begin\n size = size - 1;\n for (clogb2=1; size>1; clogb2=clogb2+1)\n size = size >> 1;\n end\n endfunction // clogb2\n\n input clk;\n input rst;\n\n// Activate wait state machine.\n input bm_end;\n reg bm_end_r1;\n always @(posedge clk) bm_end_r1 <= #TCQ bm_end;\n\n reg col_wait_r;\n\n input pass_open_bank_r;\n input sending_row;\n reg act_wait_r_lcl;\n input rcv_open_bank;\n wire start_rcd_lcl = act_wait_r_lcl && sending_row;\n output wire start_rcd;\n assign start_rcd = start_rcd_lcl;\n wire act_wait_ns = rst ||\n ((act_wait_r_lcl && ~start_rcd_lcl && ~rcv_open_bank) ||\n bm_end_r1 || (pass_open_bank_r && bm_end));\n always @(posedge clk) act_wait_r_lcl <= #TCQ act_wait_ns;\n output wire act_wait_r;\n assign act_wait_r = act_wait_r_lcl;\n\n// RCD timer\n//\n// When CWL is even, CAS commands are issued on slot 0 and RAS commands are\n// issued on slot 1. This implies that the RCD can never expire in the same\n// cycle as the RAS (otherwise the CAS for a given transaction would precede\n// the RAS). Similarly, this can also cause premature expiration for longer\n// RCD. An offset must be added to RCD before translating it to the FPGA clock\n// domain. In this mode, CAS are on the first DRAM clock cycle corresponding to\n// a given FPGA cycle. In 2:1 mode add 2 to generate this offset aligned to\n// the FPGA cycle. Likewise, add 4 to generate an aligned offset in 4:1 mode.\n// \n// When CWL is odd, RAS commands are issued on slot 0 and CAS commands are\n// issued on slot 1. There is a natural 1 cycle seperation between RAS and CAS\n// in the DRAM clock domain so the RCD can expire in the same FPGA cycle as the\n// RAS command. In 2:1 mode, there are only 2 slots so direct translation\n// correctly places the CAS with respect to the corresponding RAS. In 4:1 mode,\n// there are two slots after CAS, so 2 is added to shift the timer into the\n// next FPGA cycle for cases that can't expire in the current cycle.\n//\n// In 2T mode, the offset from ROW to COL commands is fixed at 2. In 2:1 mode,\n// It is sufficient to translate to the half-rate domain and add the remainder.\n// In 4:1 mode, we must translate to the quarter-rate domain and add an\n// additional fabric cycle only if the remainder exceeds the fixed offset of 2\n\n localparam nRCD_CLKS =\n nCK_PER_CLK == 1 ?\n nRCD :\n nCK_PER_CLK == 2 ?\n ADDR_CMD_MODE == \"2T\" ?\n (nRCD/2) + (nRCD%2) :\n CWL % 2 ?\n (nRCD/2) :\n (nRCD+2) / 2 :\n// (nCK_PER_CLK == 4)\n ADDR_CMD_MODE == \"2T\" ? \n (nRCD/4) + (nRCD%4 > 2 ? 1 : 0) :\n CWL % 2 ?\n (nRCD-2 ? (nRCD-2) / 4 + 1 : 1) :\n nRCD/4 + 1;\n\n localparam nRCD_CLKS_M2 = (nRCD_CLKS-2 <0) ? 0 : nRCD_CLKS-2;\n localparam RCD_TIMER_WIDTH = clogb2(nRCD_CLKS_M2+1);\n localparam ZERO = 0;\n localparam ONE = 1;\n reg [RCD_TIMER_WIDTH-1:0] rcd_timer_r = {RCD_TIMER_WIDTH{1'b0}};\n reg end_rcd;\n reg rcd_active_r = 1'b0;\n\n generate\n if (nRCD_CLKS <= 2) begin : rcd_timer_leq_2\n always @(/*AS*/start_rcd_lcl) end_rcd = start_rcd_lcl;\n end\n else if (nRCD_CLKS > 2) begin : rcd_timer_gt_2\n reg [RCD_TIMER_WIDTH-1:0] rcd_timer_ns;\n always @(/*AS*/rcd_timer_r or rst or start_rcd_lcl) begin\n if (rst) rcd_timer_ns = ZERO[RCD_TIMER_WIDTH-1:0];\n else begin\n rcd_timer_ns = rcd_timer_r;\n if (start_rcd_lcl) rcd_timer_ns = nRCD_CLKS_M2[RCD_TIMER_WIDTH-1:0];\n else if (|rcd_timer_r) rcd_timer_ns =\n rcd_timer_r - ONE[RCD_TIMER_WIDTH-1:0];\n end\n end\n always @(posedge clk) rcd_timer_r <= #TCQ rcd_timer_ns;\n wire end_rcd_ns = (rcd_timer_ns == ONE[RCD_TIMER_WIDTH-1:0]);\n always @(posedge clk) end_rcd = end_rcd_ns;\n wire rcd_active_ns = |rcd_timer_ns;\n always @(posedge clk) rcd_active_r <= #TCQ rcd_active_ns;\n end\n endgenerate\n\n// Figure out if the read that's completing is for an RMW for\n// this bank machine. Delay by a state if CWL != 8 since the\n// data is not ready in the RMW buffer for the early write\n// data fetch that happens with ECC and CWL != 8.\n// Create a state bit indicating we're waiting for the read\n// half of the rmw to complete.\n input sending_col;\n input rd_wr_r;\n input req_wr_r;\n input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;\n input [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r;\n input phy_rddata_valid;\n input rd_rmw;\n reg rmw_rd_done = 1'b0;\n reg rd_half_rmw_lcl = 1'b0;\n output wire rd_half_rmw;\n assign rd_half_rmw = rd_half_rmw_lcl;\n reg rmw_wait_r = 1'b0;\n generate\n if (ECC != \"OFF\") begin : rmw_on\n// Delay phy_rddata_valid and rd_rmw by one cycle to align them\n// to req_data_buf_addr_r so that rmw_wait_r clears properly\n reg phy_rddata_valid_r;\n reg rd_rmw_r;\n always @(posedge clk) begin\n phy_rddata_valid_r <= #TCQ phy_rddata_valid;\n rd_rmw_r <= #TCQ rd_rmw;\n end \n wire my_rmw_rd_ns = phy_rddata_valid_r && rd_rmw_r && \n (rd_data_addr == req_data_buf_addr_r); \n if (CWL == 8) always @(my_rmw_rd_ns) rmw_rd_done = my_rmw_rd_ns;\n else always @(posedge clk) rmw_rd_done = #TCQ my_rmw_rd_ns;\n always @(/*AS*/rd_wr_r or req_wr_r) rd_half_rmw_lcl = req_wr_r && rd_wr_r;\n wire rmw_wait_ns = ~rst && \n ((rmw_wait_r && ~rmw_rd_done) || (rd_half_rmw_lcl && sending_col));\n always @(posedge clk) rmw_wait_r <= #TCQ rmw_wait_ns;\n end\n endgenerate\n\n// column wait state machine.\n wire col_wait_ns = ~rst && ((col_wait_r && ~sending_col) || end_rcd\n || rcv_open_bank || (rmw_rd_done && rmw_wait_r));\n always @(posedge clk) col_wait_r <= #TCQ col_wait_ns;\n\n// Set up various RAS timer parameters, wires, etc.\n\n localparam TWO = 2;\n output reg [RAS_TIMER_WIDTH-1:0] ras_timer_ns;\n reg [RAS_TIMER_WIDTH-1:0] ras_timer_r;\n input [(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0] ras_timer_ns_in;\n input [(nBANK_MACHS*2)-1:0] rb_hit_busies_r;\n\n// On a bank pass, select the RAS timer from the passing bank machine.\n reg [RAS_TIMER_WIDTH-1:0] passed_ras_timer;\n integer i;\n always @(/*AS*/ras_timer_ns_in or rb_hit_busies_r) begin\n passed_ras_timer = {RAS_TIMER_WIDTH{1'b0}};\n for (i=ID+1; i<(ID+nBANK_MACHS); i=i+1)\n if (rb_hit_busies_r[i])\n passed_ras_timer = ras_timer_ns_in[i*RAS_TIMER_WIDTH+:RAS_TIMER_WIDTH];\n end\n\n// RAS and (reused for) WTP timer. When an open bank is passed, this\n// timer is passed to the new owner. The existing RAS prevents\n// an activate from occuring too early.\n\n\n wire start_wtp_timer = sending_col && ~rd_wr_r;\n input idle_r;\n\n always @(/*AS*/bm_end_r1 or ras_timer_r or rst or start_rcd_lcl\n or start_wtp_timer) begin\n if (bm_end_r1 || rst) ras_timer_ns = ZERO[RAS_TIMER_WIDTH-1:0];\n else begin\n ras_timer_ns = ras_timer_r;\n if (start_rcd_lcl) ras_timer_ns =\n nRAS_CLKS[RAS_TIMER_WIDTH-1:0] - TWO[RAS_TIMER_WIDTH-1:0];\n if (start_wtp_timer) ras_timer_ns =\n // As the timer is being reused, it is essential to compare\n // before new value is loaded.\n (ras_timer_r <= (nWTP_CLKS-2)) ? nWTP_CLKS[RAS_TIMER_WIDTH-1:0] - TWO[RAS_TIMER_WIDTH-1:0]\n : ras_timer_r - ONE[RAS_TIMER_WIDTH-1:0];\n if (|ras_timer_r && ~start_wtp_timer) ras_timer_ns =\n ras_timer_r - ONE[RAS_TIMER_WIDTH-1:0];\n end\n end // always @ (...\n\n wire [RAS_TIMER_WIDTH-1:0] ras_timer_passed_ns = rcv_open_bank\n ? passed_ras_timer\n : ras_timer_ns;\n always @(posedge clk) ras_timer_r <= #TCQ ras_timer_passed_ns;\n\n wire ras_timer_zero_ns = (ras_timer_ns == ZERO[RAS_TIMER_WIDTH-1:0]);\n reg ras_timer_zero_r;\n always @(posedge clk) ras_timer_zero_r <= #TCQ ras_timer_zero_ns;\n\n// RTP timer. Unless 2T mode, add one for 2:1 mode. This accounts for loss of\n// one DRAM CK due to column command to row command fixed offset. In 2T mode,\n// Add the remainder. In 4:1 mode, the fixed offset is -2. Add 2 unless in 2T\n// mode, in which case we add 1 if the remainder exceeds the fixed offset.\n localparam nRTP_CLKS = (nCK_PER_CLK == 1)\n ? nRTP :\n (nCK_PER_CLK == 2)\n ? (nRTP/2) + ((ADDR_CMD_MODE == \"2T\") ? nRTP%2 : 1) :\n (nRTP/4) + ((ADDR_CMD_MODE == \"2T\") ? (nRTP%4 > 2 ? 2 : 1) : 2);\n localparam nRTP_CLKS_M1 = ((nRTP_CLKS-1) <= 0) ? 0 : nRTP_CLKS-1;\n localparam RTP_TIMER_WIDTH = clogb2(nRTP_CLKS_M1 + 1);\n reg [RTP_TIMER_WIDTH-1:0] rtp_timer_ns;\n reg [RTP_TIMER_WIDTH-1:0] rtp_timer_r;\n wire sending_col_not_rmw_rd = sending_col && ~rd_half_rmw_lcl;\n always @(/*AS*/pass_open_bank_r or rst or rtp_timer_r\n or sending_col_not_rmw_rd) begin\n rtp_timer_ns = rtp_timer_r;\n if (rst || pass_open_bank_r)\n rtp_timer_ns = ZERO[RTP_TIMER_WIDTH-1:0];\n else begin\n if (sending_col_not_rmw_rd) \n rtp_timer_ns = nRTP_CLKS_M1[RTP_TIMER_WIDTH-1:0];\n if (|rtp_timer_r) rtp_timer_ns = rtp_timer_r - ONE[RTP_TIMER_WIDTH-1:0];\n end\n end\n always @(posedge clk) rtp_timer_r <= #TCQ rtp_timer_ns;\n\n wire end_rtp_lcl = ~pass_open_bank_r &&\n ((rtp_timer_r == ONE[RTP_TIMER_WIDTH-1:0]) ||\n ((nRTP_CLKS_M1 == 0) && sending_col_not_rmw_rd));\n output wire end_rtp;\n assign end_rtp = end_rtp_lcl;\n\n// Optionally implement open page mode timer.\n localparam OP_WIDTH = clogb2(nOP_WAIT + 1);\n output wire bank_wait_in_progress;\n output wire start_pre_wait;\n input passing_open_bank;\n input low_idle_cnt_r;\n output wire op_exit_req;\n input op_exit_grant;\n input tail_r;\n output reg pre_wait_r;\n\n generate\n if (nOP_WAIT == 0) begin : op_mode_disabled\n assign bank_wait_in_progress = sending_col_not_rmw_rd || |rtp_timer_r ||\n (pre_wait_r && ~ras_timer_zero_r);\n assign start_pre_wait = end_rtp_lcl;\n assign op_exit_req = 1'b0;\n end\n else begin : op_mode_enabled\n reg op_wait_r;\n assign bank_wait_in_progress = sending_col || |rtp_timer_r ||\n (pre_wait_r && ~ras_timer_zero_r) ||\n op_wait_r;\n wire op_active = ~rst && ~passing_open_bank && ((end_rtp_lcl && tail_r)\n || op_wait_r);\n wire op_wait_ns = ~op_exit_grant && op_active;\n always @(posedge clk) op_wait_r <= #TCQ op_wait_ns;\n assign start_pre_wait = op_exit_grant ||\n (end_rtp_lcl && ~tail_r && ~passing_open_bank);\n if (nOP_WAIT == -1)\n assign op_exit_req = (low_idle_cnt_r && op_active);\n else begin : op_cnt\n reg [OP_WIDTH-1:0] op_cnt_r;\n wire [OP_WIDTH-1:0] op_cnt_ns =\n (passing_open_bank || op_exit_grant || rst)\n ? ZERO[OP_WIDTH-1:0]\n : end_rtp_lcl\n ? nOP_WAIT[OP_WIDTH-1:0]\n : |op_cnt_r\n ? op_cnt_r - ONE[OP_WIDTH-1:0]\n : op_cnt_r;\n always @(posedge clk) op_cnt_r <= #TCQ op_cnt_ns;\n assign op_exit_req = (low_idle_cnt_r && op_active) ||\n (op_wait_r && ~|op_cnt_r);\n end\n end\n endgenerate\n\n output allow_auto_pre;\n wire allow_auto_pre = act_wait_r_lcl || rcd_active_r ||\n (col_wait_r && ~sending_col);\n\n// precharge wait state machine.\n input auto_pre_r;\n wire start_pre;\n input pass_open_bank_ns;\n wire pre_wait_ns = ~rst && (~pass_open_bank_ns &&\n (start_pre_wait || (pre_wait_r && ~start_pre)));\n always @(posedge clk) pre_wait_r <= #TCQ pre_wait_ns;\n wire pre_request = pre_wait_r && ras_timer_zero_r && ~auto_pre_r;\n\n// precharge timer.\n localparam nRP_CLKS = (nCK_PER_CLK == 1) ? nRP : \n (nCK_PER_CLK == 2) ? ((nRP/2) + (nRP%2)) : \n /*(nCK_PER_CLK == 4)*/ ((nRP/4) + ((nRP%4) ? 1 : 0));\n\n// Subtract two because there are a minimum of two fabric states from\n// end of RP timer until earliest possible arb to send act.\n localparam nRP_CLKS_M2 = (nRP_CLKS-2 < 0) ? 0 : nRP_CLKS-2;\n localparam RP_TIMER_WIDTH = clogb2(nRP_CLKS_M2 + 1);\n \n input sending_pre;\n output rts_pre;\n \n generate\n \n if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != \"2T\")) begin\n \n assign start_pre = pre_wait_r && ras_timer_zero_r &&\n (sending_pre || auto_pre_r);\n \n assign rts_pre = ~sending_pre && pre_request;\n \n end\n \n else begin\n \n assign start_pre = pre_wait_r && ras_timer_zero_r &&\n (sending_row || auto_pre_r);\n \n assign rts_pre = 1'b0;\n \n end\n\n endgenerate\n\n reg [RP_TIMER_WIDTH-1:0] rp_timer_r = ZERO[RP_TIMER_WIDTH-1:0];\n\n generate\n if (nRP_CLKS_M2 > ZERO) begin : rp_timer\n reg [RP_TIMER_WIDTH-1:0] rp_timer_ns;\n always @(/*AS*/rp_timer_r or rst or start_pre)\n if (rst) rp_timer_ns = ZERO[RP_TIMER_WIDTH-1:0];\n else begin\n rp_timer_ns = rp_timer_r;\n if (start_pre) rp_timer_ns = nRP_CLKS_M2[RP_TIMER_WIDTH-1:0];\n else if (|rp_timer_r) rp_timer_ns =\n rp_timer_r - ONE[RP_TIMER_WIDTH-1:0];\n end\n always @(posedge clk) rp_timer_r <= #TCQ rp_timer_ns;\n end // block: rp_timer\n endgenerate\n\n output wire precharge_bm_end;\n assign precharge_bm_end = (rp_timer_r == ONE[RP_TIMER_WIDTH-1:0]) ||\n (start_pre && (nRP_CLKS_M2 == ZERO));\n\n// Compute RRD related activate inhibit.\n// Compare this bank machine's rank with others, then\n// select result based on grant. An alternative is to\n// select the just issued rank with the grant and simply\n// compare against this bank machine's rank. However, this\n// serializes the selection of the rank and the compare processes.\n// As implemented below, the compare occurs first, then the\n// selection based on grant. This is faster.\n\n input [RANK_WIDTH-1:0] req_rank_r;\n input [(RANK_WIDTH*nBANK_MACHS*2)-1:0] req_rank_r_in;\n\n reg inhbt_act_rrd;\n input [(nBANK_MACHS*2)-1:0] start_rcd_in;\n\n generate\n integer j;\n if (RANKS == 1)\n always @(/*AS*/req_rank_r or req_rank_r_in or start_rcd_in) begin\n inhbt_act_rrd = 1'b0;\n for (j=(ID+1); j<(ID+nBANK_MACHS); j=j+1)\n inhbt_act_rrd = inhbt_act_rrd || start_rcd_in[j];\n end\n else begin\n always @(/*AS*/req_rank_r or req_rank_r_in or start_rcd_in) begin\n inhbt_act_rrd = 1'b0;\n for (j=(ID+1); j<(ID+nBANK_MACHS); j=j+1)\n inhbt_act_rrd = inhbt_act_rrd ||\n (start_rcd_in[j] &&\n (req_rank_r_in[(j*RANK_WIDTH)+:RANK_WIDTH] == req_rank_r));\n end\n end\n\n endgenerate\n\n// Extract the activate command inhibit for the rank associated\n// with this request. FAW and RRD are computed separately so that\n// gate level timing can be carefully managed.\n input [RANKS-1:0] inhbt_act_faw_r;\n wire my_inhbt_act_faw = inhbt_act_faw_r[req_rank_r];\n\n input wait_for_maint_r;\n input head_r;\n wire act_req = ~idle_r && head_r && act_wait_r && ras_timer_zero_r &&\n ~wait_for_maint_r;\n\n// Implement simple starvation avoidance for act requests. Precharge\n// requests don't need this because they are never gated off by\n// timing events such as inhbt_act_rrd. Priority request timeout\n// is fixed at a single trip around the round robin arbiter.\n\n input sent_row;\n wire rts_act_denied = act_req && sent_row && ~sending_row;\n\n reg [BM_CNT_WIDTH-1:0] act_starve_limit_cntr_ns;\n reg [BM_CNT_WIDTH-1:0] act_starve_limit_cntr_r;\n\n generate\n if (BM_CNT_WIDTH > 1) // Number of Bank Machs > 2\n begin :BM_MORE_THAN_2 \n always @(/*AS*/act_req or act_starve_limit_cntr_r or rts_act_denied)\n begin\n act_starve_limit_cntr_ns = act_starve_limit_cntr_r;\n if (~act_req)\n act_starve_limit_cntr_ns = {BM_CNT_WIDTH{1'b0}};\n else\n if (rts_act_denied && &act_starve_limit_cntr_r)\n act_starve_limit_cntr_ns = act_starve_limit_cntr_r +\n {{BM_CNT_WIDTH-1{1'b0}}, 1'b1};\n end\n end \n else // Number of Bank Machs == 2\n begin :BM_EQUAL_2 \n always @(/*AS*/act_req or act_starve_limit_cntr_r or rts_act_denied)\n begin\n act_starve_limit_cntr_ns = act_starve_limit_cntr_r;\n if (~act_req)\n act_starve_limit_cntr_ns = {BM_CNT_WIDTH{1'b0}};\n else\n if (rts_act_denied && &act_starve_limit_cntr_r)\n act_starve_limit_cntr_ns = act_starve_limit_cntr_r +\n {1'b1};\n end\n end \n endgenerate\n\n always @(posedge clk) act_starve_limit_cntr_r <=\n #TCQ act_starve_limit_cntr_ns;\n\n reg demand_act_priority_r;\n wire demand_act_priority_ns = act_req &&\n (demand_act_priority_r || (rts_act_denied && &act_starve_limit_cntr_r));\n always @(posedge clk) demand_act_priority_r <= #TCQ demand_act_priority_ns;\n\n`ifdef MC_SVA\n cover_demand_act_priority:\n cover property (@(posedge clk) (~rst && demand_act_priority_r));\n`endif\n\n output wire demand_act_priority;\n assign demand_act_priority = demand_act_priority_r && ~sending_row;\n\n// compute act_demanded from other demand_act_priorities\n input [(nBANK_MACHS*2)-1:0] demand_act_priority_in;\n reg act_demanded = 1'b0;\n generate\n if (nBANK_MACHS > 1) begin : compute_act_demanded\n always @(demand_act_priority_in[`BM_SHARED_BV])\n act_demanded = |demand_act_priority_in[`BM_SHARED_BV];\n end\n endgenerate\n\n wire row_demand_ok = demand_act_priority_r || ~act_demanded;\n\n// Generate the Request To Send row arbitation signal.\n output wire rts_row;\n\n generate\n\n if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != \"2T\"))\n assign rts_row = ~sending_row && row_demand_ok &&\n (act_req && ~my_inhbt_act_faw && ~inhbt_act_rrd);\n else\n assign rts_row = ~sending_row && row_demand_ok &&\n ((act_req && ~my_inhbt_act_faw && ~inhbt_act_rrd) ||\n pre_request);\n endgenerate\n \n`ifdef MC_SVA\n four_activate_window_wait:\n cover property (@(posedge clk)\n (~rst && ~sending_row && act_req && my_inhbt_act_faw));\n ras_ras_delay_wait:\n cover property (@(posedge clk)\n (~rst && ~sending_row && act_req && inhbt_act_rrd));\n`endif\n\n// Provide rank machines early knowledge that this bank machine is\n// going to send an activate to the rank. In this way, the rank\n// machines just need to use the sending_row wire to figure out if\n// they need to keep track of the activate.\n output reg [RANKS-1:0] act_this_rank_r;\n reg [RANKS-1:0] act_this_rank_ns;\n always @(/*AS*/act_wait_r or req_rank_r) begin\n act_this_rank_ns = {RANKS{1'b0}};\n for (i = 0; i < RANKS; i = i + 1)\n act_this_rank_ns[i] = act_wait_r && (i[RANK_WIDTH-1:0] == req_rank_r);\n end\n always @(posedge clk) act_this_rank_r <= #TCQ act_this_rank_ns;\n\n\n// Generate request to send column command signal.\n\n input order_q_zero;\n wire req_bank_rdy_ns = order_q_zero && col_wait_r;\n reg req_bank_rdy_r;\n always @(posedge clk) req_bank_rdy_r <= #TCQ req_bank_rdy_ns;\n\n// Determine is we have been denied a column command request.\n input sent_col;\n wire rts_col_denied = req_bank_rdy_r && sent_col && ~sending_col;\n\n// Implement a starvation limit counter. Count the number of times a\n// request to send a column command has been denied.\n localparam STARVE_LIMIT_CNT = STARVE_LIMIT * nBANK_MACHS;\n localparam STARVE_LIMIT_WIDTH = clogb2(STARVE_LIMIT_CNT);\n reg [STARVE_LIMIT_WIDTH-1:0] starve_limit_cntr_r;\n reg [STARVE_LIMIT_WIDTH-1:0] starve_limit_cntr_ns;\n always @(/*AS*/col_wait_r or rts_col_denied or starve_limit_cntr_r)\n if (~col_wait_r)\n starve_limit_cntr_ns = {STARVE_LIMIT_WIDTH{1'b0}};\n else\n if (rts_col_denied && (starve_limit_cntr_r != STARVE_LIMIT_CNT-1))\n starve_limit_cntr_ns = starve_limit_cntr_r +\n {{STARVE_LIMIT_WIDTH-1{1'b0}}, 1'b1};\n else starve_limit_cntr_ns = starve_limit_cntr_r;\n always @(posedge clk) starve_limit_cntr_r <= #TCQ starve_limit_cntr_ns;\n\n input q_has_rd;\n input q_has_priority;\n\n// Decide if this bank machine should demand priority. Priority is demanded\n// when starvation limit counter is reached, or a bit in the request.\n wire starved = ((starve_limit_cntr_r == (STARVE_LIMIT_CNT-1)) &&\n rts_col_denied);\n input req_priority_r;\n input idle_ns;\n reg demand_priority_r;\n wire demand_priority_ns = ~idle_ns && col_wait_ns &&\n (demand_priority_r ||\n (order_q_zero &&\n (req_priority_r || q_has_priority)) ||\n (starved && (q_has_rd || ~req_wr_r)));\n\n always @(posedge clk) demand_priority_r <= #TCQ demand_priority_ns;\n\n`ifdef MC_SVA\n wire rdy_for_priority = ~rst && ~demand_priority_r && ~idle_ns &&\n col_wait_ns;\n req_triggers_demand_priority:\n cover property (@(posedge clk)\n (rdy_for_priority && req_priority_r && ~q_has_priority && ~starved));\n q_priority_triggers_demand_priority:\n cover property (@(posedge clk)\n (rdy_for_priority && ~req_priority_r && q_has_priority && ~starved));\n wire not_req_or_q_rdy_for_priority =\n rdy_for_priority && ~req_priority_r && ~q_has_priority;\n starved_req_triggers_demand_priority:\n cover property (@(posedge clk)\n (not_req_or_q_rdy_for_priority && starved && ~q_has_rd && ~req_wr_r));\n starved_q_triggers_demand_priority:\n cover property (@(posedge clk)\n (not_req_or_q_rdy_for_priority && starved && q_has_rd && req_wr_r));\n`endif\n\n// compute demanded from other demand_priorities\n input [(nBANK_MACHS*2)-1:0] demand_priority_in;\n reg demanded = 1'b0;\n generate\n if (nBANK_MACHS > 1) begin : compute_demanded\n always @(demand_priority_in[`BM_SHARED_BV]) demanded =\n |demand_priority_in[`BM_SHARED_BV];\n end\n endgenerate\n\n\n// In order to make sure that there is no starvation amongst a possibly\n// unlimited stream of priority requests, add a second stage to the demand\n// priority signal. If there are no other requests demanding priority, then\n// go ahead and assert demand_priority. If any other requests are asserting\n// demand_priority, hold off asserting demand_priority until these clear, then\n// assert demand priority. Its possible to get multiple requests asserting\n// demand priority simultaneously, but that's OK. Those requests will be\n// serviced, demanded will fall, and another group of requests will be\n// allowed to assert demand_priority.\n\n reg demanded_prior_r;\n wire demanded_prior_ns = demanded &&\n (demanded_prior_r || ~demand_priority_r);\n always @(posedge clk) demanded_prior_r <= #TCQ demanded_prior_ns;\n\n output wire demand_priority;\n assign demand_priority = demand_priority_r && ~demanded_prior_r &&\n ~sending_col;\n\n`ifdef MC_SVA\n demand_priority_gated:\n cover property (@(posedge clk) (demand_priority_r && ~demand_priority));\n generate\n if (nBANK_MACHS >1) multiple_demand_priority:\n cover property (@(posedge clk)\n ($countones(demand_priority_in[`BM_SHARED_BV]) > 1));\n endgenerate\n`endif\n\n wire demand_ok = demand_priority_r || ~demanded;\n \n // Figure out if the request in this bank machine matches the current rank\n // configuration.\n input rnk_config_strobe;\n input rnk_config_kill_rts_col;\n input rnk_config_valid_r;\n input [RANK_WIDTH-1:0] rnk_config;\n output wire rtc;\n\n wire rnk_config_match = rnk_config_valid_r && (rnk_config == req_rank_r);\n assign rtc = ~rnk_config_match && ~rnk_config_kill_rts_col && order_q_zero && col_wait_r && demand_ok;\n\n// Using rank state provided by the rank machines, figure out if\n// a read requests should wait for WTR or RTW.\n input [RANKS-1:0] inhbt_rd;\n wire my_inhbt_rd = inhbt_rd[req_rank_r];\n input [RANKS-1:0] inhbt_wr;\n wire my_inhbt_wr = inhbt_wr[req_rank_r];\n wire allow_rw = ~rd_wr_r ? ~my_inhbt_wr : ~my_inhbt_rd;\n\n// DQ bus timing constraints.\n input dq_busy_data;\n\n// Column command is ready to arbitrate, except for databus restrictions.\n wire col_rdy = (col_wait_r || ((nRCD_CLKS <= 1) && end_rcd) ||\n (rcv_open_bank && nCK_PER_CLK == 2 && DRAM_TYPE==\"DDR2\" && BURST_MODE == \"4\") || \n (rcv_open_bank && nCK_PER_CLK == 4 && BURST_MODE == \"8\")) &&\n order_q_zero;\n\n// Column command is ready to arbitrate for sending a write. Used\n// to generate early wr_data_addr for ECC mode.\n output wire col_rdy_wr;\n assign col_rdy_wr = col_rdy && ~rd_wr_r;\n \n// Figure out if we're ready to send a column command based on all timing\n// constraints.\n// if timing is an issue.\n wire col_cmd_rts = col_rdy && ~dq_busy_data && allow_rw && rnk_config_match;\n\n`ifdef MC_SVA\n col_wait_for_order_q: cover property\n (@(posedge clk)\n (~rst && col_wait_r && ~order_q_zero && ~dq_busy_data &&\n allow_rw));\n col_wait_for_dq_busy: cover property\n (@(posedge clk)\n (~rst && col_wait_r && order_q_zero && dq_busy_data &&\n allow_rw));\n col_wait_for_allow_rw: cover property\n (@(posedge clk)\n (~rst && col_wait_r && order_q_zero && ~dq_busy_data &&\n ~allow_rw));\n`endif\n\n// Implement flow control for the command and control FIFOs and for the data\n// FIFO during writes\n input phy_mc_ctl_full;\n input phy_mc_cmd_full;\n input phy_mc_data_full;\n\n // Register ctl_full and cmd_full\n reg phy_mc_ctl_full_r = 1'b0;\n reg phy_mc_cmd_full_r = 1'b0;\n always @(posedge clk)\n if(rst) begin\n phy_mc_ctl_full_r <= #TCQ 1'b0;\n phy_mc_cmd_full_r <= #TCQ 1'b0;\n end else begin\n phy_mc_ctl_full_r <= #TCQ phy_mc_ctl_full;\n phy_mc_cmd_full_r <= #TCQ phy_mc_cmd_full;\n end\n \n // register output data pre-fifo almost full condition and fold in WR status\n reg ofs_rdy_r = 1'b0;\n always @(posedge clk)\n if(rst)\n ofs_rdy_r <= #TCQ 1'b0;\n else\n ofs_rdy_r <= #TCQ ~phy_mc_cmd_full_r && ~phy_mc_ctl_full_r && ~(phy_mc_data_full && ~rd_wr_r);\n\n// Disable priority feature for one state after a config to insure\n// forward progress on the just installed io config.\n reg override_demand_r;\n wire override_demand_ns = rnk_config_strobe || rnk_config_kill_rts_col;\n always @(posedge clk) override_demand_r <= override_demand_ns;\n output wire rts_col;\n assign rts_col = ~sending_col && (demand_ok || override_demand_r) &&\n col_cmd_rts && ofs_rdy_r;\n\n// As in act_this_rank, wr/rd_this_rank informs rank machines\n// that this bank machine is doing a write/rd. Removes logic\n// after the grant.\n reg [RANKS-1:0] wr_this_rank_ns;\n reg [RANKS-1:0] rd_this_rank_ns;\n always @(/*AS*/rd_wr_r or req_rank_r) begin\n wr_this_rank_ns = {RANKS{1'b0}};\n rd_this_rank_ns = {RANKS{1'b0}};\n for (i=0; i= 1) || (DELAY_WR_DATA_CNTRL == 1)) begin : offset_pipe_0\n always @(posedge clk) offset_r1 <=\n #TCQ offset_r[DATA_BUF_OFFSET_WIDTH-1:0];\n always @(posedge clk) col_rd_wr_r1 <= #TCQ col_rd_wr;\n end\n if(nPHY_WRLAT == 2) begin : offset_pipe_1\n always @(posedge clk) offset_r2 <=\n #TCQ offset_r1[DATA_BUF_OFFSET_WIDTH-1:0];\n always @(posedge clk) col_rd_wr_r2 <= #TCQ col_rd_wr_r1;\n end\n endgenerate\n\n output wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;\n assign wr_data_offset = (DELAY_WR_DATA_CNTRL == 1)\n ? offset_r1[DATA_BUF_OFFSET_WIDTH-1:0]\n : (EARLY_WR_DATA_ADDR == \"OFF\")\n ? offset_r[DATA_BUF_OFFSET_WIDTH-1:0]\n : offset_ns[DATA_BUF_OFFSET_WIDTH-1:0];\n\n reg sent_col_r1;\n reg sent_col_r2;\n always @(posedge clk) sent_col_r1 <= #TCQ sent_col;\n always @(posedge clk) sent_col_r2 <= #TCQ sent_col_r1;\n\n wire wrdata_en = (nPHY_WRLAT == 0) ?\n (sent_col || |offset_r) & ~col_rd_wr :\n (nPHY_WRLAT == 1) ?\n (sent_col_r1 || |offset_r1) & ~col_rd_wr_r1 :\n //(nPHY_WRLAT >= 2) ?\n (sent_col_r2 || |offset_r2) & ~col_rd_wr_r2;\n\n output wire mc_wrdata_en;\n assign mc_wrdata_en = wrdata_en;\n\n output wire wr_data_en;\n assign wr_data_en = (DELAY_WR_DATA_CNTRL == 1)\n ? ((sent_col_r1 || |offset_r1) && ~col_rd_wr_r1)\n : ((sent_col || |offset_r) && ~col_rd_wr);\n\n\n input [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr;\n output wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;\n generate\n if (DELAY_WR_DATA_CNTRL == 1) begin : delay_wr_data_cntrl_eq_1\n reg [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr_r;\n always @(posedge clk) col_wr_data_buf_addr_r <= \n #TCQ col_wr_data_buf_addr;\n assign wr_data_addr = col_wr_data_buf_addr_r;\n end\n else begin : delay_wr_data_cntrl_ne_1\n assign wr_data_addr = col_wr_data_buf_addr;\n end\n endgenerate\n\n// CAS-RD to mc_rddata_en\n\n wire read_data_valid = (sent_col || |offset_r) && col_rd_wr;\n\nfunction integer clogb2 (input integer size); // ceiling logb2\n begin\n size = size - 1;\n for (clogb2=1; size>1; clogb2=clogb2+1)\n size = size >> 1;\n end\nendfunction // clogb2\n\n// Implement FIFO that records reads as they are sent to the DRAM.\n// When phy_rddata_valid is returned some unknown time later, the \n// FIFO output is used to control how the data is interpreted.\n \n input phy_rddata_valid;\n output wire rd_rmw;\n output reg [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr;\n output reg ecc_status_valid;\n output reg wr_ecc_buf;\n output reg rd_data_end;\n output reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; \n output reg [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;\n output reg rd_data_en /* synthesis syn_maxfan = 10 */;\n output col_read_fifo_empty;\n\n input col_periodic_rd; \n input [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr;\n input col_rmw;\n input [RANK_WIDTH-1:0] col_ra;\n input [BANK_WIDTH-1:0] col_ba;\n input [ROW_WIDTH-1:0] col_row;\n input [ROW_WIDTH-1:0] col_a;\n \n // Real column address (skip A10/AP and A12/BC#). The maximum width is 12;\n // the width will be tailored for the target DRAM downstream.\n wire [11:0] col_a_full;\n\n // Minimum row width is 12; take remaining 11 bits after omitting A10/AP\n assign col_a_full[10:0] = {col_a[11], col_a[9:0]};\n \n // Get the 12th bit when row address width accommodates it; omit A12/BC#\n generate\n if (ROW_WIDTH >= 14) begin : COL_A_FULL_11_1\n assign col_a_full[11] = col_a[13];\n end else begin : COL_A_FULL_11_0\n assign col_a_full[11] = 0;\n end\n endgenerate\n \n // Extract only the width of the target DRAM\n wire [COL_WIDTH-1:0] col_a_extracted = col_a_full[COL_WIDTH-1:0];\n\n localparam MC_ERR_LINE_WIDTH = MC_ERR_ADDR_WIDTH-DATA_BUF_OFFSET_WIDTH;\n localparam FIFO_WIDTH = 1 /*data_end*/ +\n 1 /*periodic_rd*/ +\n DATA_BUF_ADDR_WIDTH +\n DATA_BUF_OFFSET_WIDTH +\n ((ECC == \"OFF\") ? 0 : 1+MC_ERR_LINE_WIDTH);\n localparam FULL_RAM_CNT = (FIFO_WIDTH/6);\n localparam REMAINDER = FIFO_WIDTH % 6;\n localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);\n localparam RAM_WIDTH = (RAM_CNT*6);\n\n generate\n begin : read_fifo\n\n wire [MC_ERR_LINE_WIDTH:0] ecc_line;\n if (CS_WIDTH == 1)\n assign ecc_line = {col_rmw, col_ba, col_row, col_a_extracted};\n else\n assign ecc_line = {col_rmw,\n col_ra,\n col_ba,\n col_row,\n col_a_extracted};\n\n wire [FIFO_WIDTH-1:0] real_fifo_data;\n if (ECC == \"OFF\")\n assign real_fifo_data = {data_end,\n col_periodic_rd,\n col_data_buf_addr,\n offset_r[DATA_BUF_OFFSET_WIDTH-1:0]};\n else\n assign real_fifo_data = {data_end,\n col_periodic_rd,\n col_data_buf_addr,\n offset_r[DATA_BUF_OFFSET_WIDTH-1:0],\n ecc_line};\n\n wire [RAM_WIDTH-1:0] fifo_in_data;\n if (REMAINDER == 0)\n assign fifo_in_data = real_fifo_data;\n else\n assign fifo_in_data = {{6-REMAINDER{1'b0}}, real_fifo_data};\n\n wire [RAM_WIDTH-1:0] fifo_out_data_ns;\n\n reg [4:0] head_r;\n wire [4:0] head_ns = rst ? 5'b0 : read_data_valid\n ? (head_r + 5'b1)\n : head_r;\n always @(posedge clk) head_r <= #TCQ head_ns;\n\n\n reg [4:0] tail_r;\n wire [4:0] tail_ns = rst ? 5'b0 : phy_rddata_valid\n ? (tail_r + 5'b1)\n : tail_r;\n always @(posedge clk) tail_r <= #TCQ tail_ns;\n\n assign col_read_fifo_empty = head_r == tail_r ? 1'b1 : 1'b0;\n\n genvar i;\n for (i=0; iout delay(sim only)\n parameter ADDR_CMD_MODE = \"1T\", // registered or\n // 1Tfered mem?\n parameter BANK_WIDTH = 3, // bank address width\n parameter BM_CNT_WIDTH = 2, // # BM counter width\n // i.e., log2(nBANK_MACHS)\n parameter BURST_MODE = \"8\", // Burst length\n parameter CL = 5, // Read CAS latency\n // (in clk cyc)\n parameter CMD_PIPE_PLUS1 = \"ON\", // add register stage\n // between MC and PHY\n parameter COL_WIDTH = 12, // column address width\n parameter CS_WIDTH = 4, // # of unique CS outputs\n parameter CWL = 5, // Write CAS latency\n // (in clk cyc)\n parameter DATA_BUF_ADDR_WIDTH = 8, // User request tag (e.g.\n // user src/dest buf addr)\n parameter DATA_BUF_OFFSET_WIDTH = 1, // User buffer offset width\n parameter DATA_WIDTH = 64, // Data bus width\n parameter DQ_WIDTH = 64, // # of DQ (data)\n parameter DQS_WIDTH = 8, // # of DQS (strobe)\n parameter DRAM_TYPE = \"DDR3\", // Memory I/F type:\n // \"DDR3\", \"DDR2\" \n parameter ECC = \"OFF\", // ECC ON/OFF?\n parameter ECC_WIDTH = 8, // # of ECC bits\n parameter MAINT_PRESCALER_PERIOD= 200000, // maintenance period (ps)\n parameter MC_ERR_ADDR_WIDTH = 31, // # of error address bits\n parameter nBANK_MACHS = 4, // # of bank machines (BM)\n parameter nCK_PER_CLK = 4, // DRAM clock : MC clock\n // frequency ratio\n parameter nCS_PER_RANK = 1, // # of unique CS outputs\n // per rank\n parameter nREFRESH_BANK = 1, // # of REF cmds to pull-in\n parameter nSLOTS = 1, // # DIMM slots in system\n parameter ORDERING = \"NORM\", // request ordering mode\n parameter PAYLOAD_WIDTH = 64, // Width of data payload\n // from PHY\n parameter RANK_WIDTH = 2, // # of bits to count ranks\n parameter RANKS = 4, // # of ranks of DRAM\n parameter REG_CTRL = \"ON\", // \"ON\" for registered DIMM\n parameter ROW_WIDTH = 16, // row address width\n parameter RTT_NOM = \"40\", // Nominal ODT value\n parameter RTT_WR = \"120\", // Write ODT value\n parameter SLOT_0_CONFIG = 8'b0000_0101, // ranks allowed in slot 0\n parameter SLOT_1_CONFIG = 8'b0000_1010, // ranks allowed in slot 1\n parameter STARVE_LIMIT = 2, // max # of times a user\n // request is allowed to\n // lose arbitration when\n // reordering is enabled\n parameter tCK = 2500, // memory clk period(ps)\n parameter tCKE = 10000, // CKE minimum pulse (ps)\n parameter tFAW = 40000, // four activate window(ps)\n parameter tRAS = 37500, // ACT->PRE cmd period (ps)\n parameter tRCD = 12500, // ACT->R/W delay (ps)\n parameter tREFI = 7800000, // average periodic\n // refresh interval(ps)\n parameter CKE_ODT_AUX = \"FALSE\", //Parameter to turn on/off the aux_out signal\n parameter tRFC = 110000, // REF->ACT/REF delay (ps)\n parameter tRP = 12500, // PRE cmd period (ps)\n parameter tRRD = 10000, // ACT->ACT period (ps)\n parameter tRTP = 7500, // Read->PRE cmd delay (ps)\n parameter tWTR = 7500, // Internal write->read\n // delay (ps)\n // requiring DLL lock (CKs)\n parameter tZQCS = 64, // ZQCS cmd period (CKs)\n parameter tZQI = 128_000_000, // ZQCS interval (ps)\n parameter tPRDI = 1_000_000, // pS\n parameter USER_REFRESH = \"OFF\" // Whether user manages REF\n )\n (\n\n // System inputs\n\n input clk,\n input rst,\n\n // Physical memory slot presence\n\n input [7:0] slot_0_present,\n input [7:0] slot_1_present,\n\n // Native Interface\n\n input [2:0] cmd,\n input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr,\n input hi_priority,\n input size,\n \n input [BANK_WIDTH-1:0] bank,\n input [COL_WIDTH-1:0] col,\n input [RANK_WIDTH-1:0] rank,\n input [ROW_WIDTH-1:0] row,\n input use_addr,\n\n input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data,\n input [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask,\n \n output accept,\n output accept_ns,\n\n output [BM_CNT_WIDTH-1:0] bank_mach_next,\n \n output wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data,\n output [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr,\n output rd_data_en,\n output rd_data_end,\n output [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset,\n \n output reg [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr /* synthesis syn_maxfan = 30 */,\n output reg wr_data_en,\noutput reg [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset /* synthesis syn_maxfan = 30 */,\n \n output mc_read_idle,\n output mc_ref_zq_wip,\n\n // ECC interface\n\n input correct_en, \n input [2*nCK_PER_CLK-1:0] raw_not_ecc,\n\n input\t [DQS_WIDTH - 1:0]\t fi_xor_we,\n input\t [DQ_WIDTH -1 :0 ]\t fi_xor_wrdata,\n \n output [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr,\n output [2*nCK_PER_CLK-1:0] ecc_single,\n output [2*nCK_PER_CLK-1:0] ecc_multiple,\n \n // User maintenance requests\n\n input app_periodic_rd_req,\n input app_ref_req,\n input app_zq_req,\n input app_sr_req,\n output app_sr_active,\n output app_ref_ack,\n output app_zq_ack,\n\n // MC <==> PHY Interface\n \n output reg [nCK_PER_CLK-1:0] mc_ras_n,\n output reg [nCK_PER_CLK-1:0] mc_cas_n,\n output reg [nCK_PER_CLK-1:0] mc_we_n,\n output reg [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address,\n output reg [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank,\n output reg [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n,\n output reg [1:0] mc_odt,\n output reg [nCK_PER_CLK-1:0] mc_cke,\n output wire mc_reset_n,\n output wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata,\n output wire [2*nCK_PER_CLK*DQ_WIDTH/8-1:0]mc_wrdata_mask,\n output reg mc_wrdata_en,\n \n output wire mc_cmd_wren,\n output wire mc_ctl_wren,\n output reg [2:0] mc_cmd,\n output reg [5:0] mc_data_offset,\n output reg [5:0] mc_data_offset_1,\n output reg [5:0] mc_data_offset_2,\n output reg [1:0] mc_cas_slot,\n output reg [3:0] mc_aux_out0,\n output reg [3:0] mc_aux_out1,\n output reg [1:0] mc_rank_cnt,\n \n input phy_mc_ctl_full,\n input phy_mc_cmd_full,\n input phy_mc_data_full,\n input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rd_data,\n input phy_rddata_valid,\n \n input init_calib_complete,\n input [6*RANKS-1:0] calib_rd_data_offset,\n input [6*RANKS-1:0] calib_rd_data_offset_1,\n input [6*RANKS-1:0] calib_rd_data_offset_2\n\n );\n\n assign mc_reset_n = 1'b1; // never reset memory\n assign mc_cmd_wren = 1'b1; // always write CMD FIFO(issue DSEL when idle)\n assign mc_ctl_wren = 1'b1; // always write CTL FIFO(issue nondata when idle)\n\n // Ensure there is always at least one rank present during operation\n `ifdef MC_SVA\n ranks_present: assert property\n (@(posedge clk) (rst || (|(slot_0_present | slot_1_present))));\n `endif\n\n // Reserved. Do not change.\n localparam nPHY_WRLAT = 2;\n\n // always delay write data control unless ECC mode is enabled\n localparam DELAY_WR_DATA_CNTRL = ECC == \"ON\" ? 0 : 1;\n\n // Ensure that write control is delayed for appropriate CWL\n /*`ifdef MC_SVA\n delay_wr_data_zero_CWL_le_6: assert property\n (@(posedge clk) ((CWL > 6) || (DELAY_WR_DATA_CNTRL == 0)));\n `endif*/\n\n // Never retrieve WR_DATA_ADDR early\n localparam EARLY_WR_DATA_ADDR = \"OFF\";\n\n //***************************************************************************\n // Convert timing parameters from time to clock cycles\n //***************************************************************************\n \n localparam nCKE = cdiv(tCKE, tCK);\n localparam nRP = cdiv(tRP, tCK);\n localparam nRCD = cdiv(tRCD, tCK);\n localparam nRAS = cdiv(tRAS, tCK);\n localparam nFAW = cdiv(tFAW, tCK);\n localparam nRFC = cdiv(tRFC, tCK);\n\n // Convert tWR. As per specification, write recover for autoprecharge\n // cycles doesn't support values of 9 and 11. Round up 9 to 10 and 11 to 12\n localparam nWR_CK = cdiv(15000, tCK) ;\n localparam nWR = (nWR_CK == 9) ? 10 : (nWR_CK == 11) ? 12 : nWR_CK;\n\n // tRRD, tWTR at tRTP have a 4 cycle floor in DDR3 and 2 cycle floor in DDR2\n localparam nRRD_CK = cdiv(tRRD, tCK);\n localparam nRRD = (DRAM_TYPE == \"DDR3\") ? (nRRD_CK < 4) ? 4 : nRRD_CK\n : (nRRD_CK < 2) ? 2 : nRRD_CK;\n localparam nWTR_CK = cdiv(tWTR, tCK);\n localparam nWTR = (DRAM_TYPE == \"DDR3\") ? (nWTR_CK < 4) ? 4 : nWTR_CK\n : (nWTR_CK < 2) ? 2 : nWTR_CK;\n localparam nRTP_CK = cdiv(tRTP, tCK);\n localparam nRTP = (DRAM_TYPE == \"DDR3\") ? (nRTP_CK < 4) ? 4 : nRTP_CK\n : (nRTP_CK < 2) ? 2 : nRTP_CK;\n\n // Add a cycle to CL/CWL for the register in RDIMM devices\n localparam CWL_M = (REG_CTRL == \"ON\") ? CWL + 1 : CWL;\n localparam CL_M = (REG_CTRL == \"ON\") ? CL + 1 : CL;\n \n // Tuneable delay between read and write data on the DQ bus\n localparam DQRD2DQWR_DLY = 4;\n\n // CKE minimum pulse width for self-refresh (SRE->SRX minimum time)\n localparam nCKESR = nCKE + 1;\n \n // Delay from SRE to command requiring locked DLL. Currently fixed at 512 for\n // all devices per JEDEC spec.\n localparam tXSDLL = 512;\n\n //***************************************************************************\n // Set up maintenance counter dividers\n //***************************************************************************\n\n // CK clock divisor to generate maintenance prescaler period (round down)\n localparam MAINT_PRESCALER_DIV = MAINT_PRESCALER_PERIOD / (tCK*nCK_PER_CLK);\n \n // Maintenance prescaler divisor for refresh timer. Essentially, this is\n // just (tREFI / MAINT_PRESCALER_PERIOD), but we must account for the worst\n // case delay from the time we get a tick from the refresh counter to the\n // time that we can actually issue the REF command. Thus, subtract tRCD, CL,\n // data burst time and tRP for each implemented bank machine to ensure that\n // all transactions can complete before tREFI expires\n localparam REFRESH_TIMER_DIV =\n USER_REFRESH == \"ON\" ? 0 :\n (tREFI-((tRCD+((CL+4)*tCK)+tRP)*nBANK_MACHS)) / MAINT_PRESCALER_PERIOD;\n \n // Periodic read (RESERVED - not currently required or supported in 7 series)\n // tPRDI should only be set to 0\n // localparam tPRDI = 0; // Do NOT change.\n localparam PERIODIC_RD_TIMER_DIV = tPRDI / MAINT_PRESCALER_PERIOD;\n\n // Convert maintenance prescaler from ps to ns\n localparam MAINT_PRESCALER_PERIOD_NS = MAINT_PRESCALER_PERIOD / 1000;\n \n // Maintenance prescaler divisor for ZQ calibration (ZQCS) timer\n localparam ZQ_TIMER_DIV = tZQI / MAINT_PRESCALER_PERIOD_NS;\n\n // Bus width required to broadcast a single bit rank signal among all the\n // bank machines - 1 bit per rank, per bank\n localparam RANK_BM_BV_WIDTH = nBANK_MACHS * RANKS;\n \n //***************************************************************************\n // Define 2T, CWL-even mode to enable multi-fabric-cycle 2T commands\n //***************************************************************************\n localparam EVEN_CWL_2T_MODE =\n ((ADDR_CMD_MODE == \"2T\") && (!(CWL % 2))) ? \"ON\" : \"OFF\";\n \n //***************************************************************************\n // Reserved feature control.\n //***************************************************************************\n\n // Open page wait mode is reserved.\n // nOP_WAIT is the number of states a bank machine will park itself\n // on an otherwise inactive open page before closing the page. If\n // nOP_WAIT == 0, open page wait mode is disabled. If nOP_WAIT == -1,\n // the bank machine will remain parked until the pool of idle bank machines\n // are less than LOW_IDLE_CNT. At which point parked bank machines\n // are selected to exit until the number of idle bank machines exceeds the\n // LOW_IDLE_CNT.\n localparam nOP_WAIT = 0; // Open page mode\n localparam LOW_IDLE_CNT = 0; // Low idle bank machine threshold\n \n //***************************************************************************\n // Internal wires\n //***************************************************************************\n\n wire [RANK_BM_BV_WIDTH-1:0] act_this_rank_r;\n wire [ROW_WIDTH-1:0] col_a;\n wire [BANK_WIDTH-1:0] col_ba;\n wire [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr;\n wire col_periodic_rd;\n wire [RANK_WIDTH-1:0] col_ra;\n wire col_rmw;\n wire col_rd_wr;\n wire [ROW_WIDTH-1:0] col_row;\n wire col_size;\n wire [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr;\n wire dq_busy_data;\n wire ecc_status_valid;\n wire [RANKS-1:0] inhbt_act_faw_r;\n wire [RANKS-1:0] inhbt_rd;\n wire [RANKS-1:0] inhbt_wr;\n wire insert_maint_r1;\n wire [RANK_WIDTH-1:0] maint_rank_r;\n wire maint_req_r;\n wire maint_wip_r;\n wire maint_zq_r;\n wire maint_sre_r;\n wire maint_srx_r;\n wire periodic_rd_ack_r;\n wire periodic_rd_r;\n wire [RANK_WIDTH-1:0] periodic_rd_rank_r;\n wire [(RANKS*nBANK_MACHS)-1:0] rank_busy_r;\n wire rd_rmw;\n wire [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r;\n wire [nBANK_MACHS-1:0] sending_col;\n wire [nBANK_MACHS-1:0] sending_row;\n wire sent_col;\n wire sent_col_r;\n wire wr_ecc_buf;\n wire [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r;\n\n // MC/PHY optional pipeline stage support\n wire [nCK_PER_CLK-1:0] mc_ras_n_ns;\n wire [nCK_PER_CLK-1:0] mc_cas_n_ns;\n wire [nCK_PER_CLK-1:0] mc_we_n_ns;\n wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address_ns;\n wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank_ns;\n wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n_ns;\n wire [1:0] mc_odt_ns;\n wire [nCK_PER_CLK-1:0] mc_cke_ns;\n wire [3:0] mc_aux_out0_ns;\n wire [3:0] mc_aux_out1_ns;\n wire [1:0] mc_rank_cnt_ns = col_ra;\n wire [2:0] mc_cmd_ns;\n wire [5:0] mc_data_offset_ns;\n wire [5:0] mc_data_offset_1_ns;\n wire [5:0] mc_data_offset_2_ns;\n wire [1:0] mc_cas_slot_ns;\n wire mc_wrdata_en_ns;\n \n wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr_ns;\n wire wr_data_en_ns;\n wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset_ns;\n\n integer i;\n \n // MC Read idle support\n wire col_read_fifo_empty;\n wire mc_read_idle_ns;\n reg mc_read_idle_r;\n\n // MC Maintenance in progress with bus idle indication\n wire maint_ref_zq_wip;\n wire mc_ref_zq_wip_ns;\n reg mc_ref_zq_wip_r;\n\n //***************************************************************************\n // Function cdiv\n // Description:\n // This function performs ceiling division (divide and round-up)\n // Inputs:\n // num: integer to be divided\n // div: divisor\n // Outputs:\n // cdiv: result of ceiling division (num/div, rounded up)\n //***************************************************************************\n\n function integer cdiv (input integer num, input integer div);\n begin\n // perform division, then add 1 if and only if remainder is non-zero\n cdiv = (num/div) + (((num%div)>0) ? 1 : 0);\n end\n endfunction // cdiv\n\n //***************************************************************************\n // Optional pipeline register stage on MC/PHY interface\n //***************************************************************************\n\n generate\n \n if (CMD_PIPE_PLUS1 == \"ON\") begin : cmd_pipe_plus // register interface\n\n always @(posedge clk) begin\n \n mc_address <= #TCQ mc_address_ns;\n mc_bank <= #TCQ mc_bank_ns;\n mc_cas_n <= #TCQ mc_cas_n_ns;\n mc_cs_n <= #TCQ mc_cs_n_ns;\n mc_odt <= #TCQ mc_odt_ns;\n mc_cke <= #TCQ mc_cke_ns;\n mc_aux_out0 <= #TCQ mc_aux_out0_ns;\n mc_aux_out1 <= #TCQ mc_aux_out1_ns;\n mc_cmd <= #TCQ mc_cmd_ns;\n mc_ras_n <= #TCQ mc_ras_n_ns;\n mc_we_n <= #TCQ mc_we_n_ns;\n mc_data_offset <= #TCQ mc_data_offset_ns;\n mc_data_offset_1 <= #TCQ mc_data_offset_1_ns;\n mc_data_offset_2 <= #TCQ mc_data_offset_2_ns;\n mc_cas_slot <= #TCQ mc_cas_slot_ns;\n mc_wrdata_en <= #TCQ mc_wrdata_en_ns;\n mc_rank_cnt <= #TCQ mc_rank_cnt_ns;\n\n wr_data_addr <= #TCQ wr_data_addr_ns;\n wr_data_en <= #TCQ wr_data_en_ns;\n wr_data_offset <= #TCQ wr_data_offset_ns;\n\n end // always @ (posedge clk)\n \n end // block: cmd_pipe_plus\n \n else begin : cmd_pipe_plus0 // don't register interface\n \n always @( mc_address_ns or mc_aux_out0_ns or mc_aux_out1_ns or\n mc_bank_ns or mc_cas_n_ns or mc_cmd_ns or mc_cs_n_ns or\n mc_odt_ns or mc_cke_ns or mc_data_offset_ns or\n mc_data_offset_1_ns or mc_data_offset_2_ns or mc_rank_cnt_ns or\n mc_ras_n_ns or mc_we_n_ns or mc_wrdata_en_ns or \n wr_data_addr_ns or wr_data_en_ns or wr_data_offset_ns or\n mc_cas_slot_ns)\n begin\n\n mc_address = #TCQ mc_address_ns;\n mc_bank = #TCQ mc_bank_ns;\n mc_cas_n = #TCQ mc_cas_n_ns;\n mc_cs_n = #TCQ mc_cs_n_ns;\n mc_odt = #TCQ mc_odt_ns;\n mc_cke = #TCQ mc_cke_ns;\n mc_aux_out0 = #TCQ mc_aux_out0_ns;\n mc_aux_out1 = #TCQ mc_aux_out1_ns;\n mc_cmd = #TCQ mc_cmd_ns;\n mc_ras_n = #TCQ mc_ras_n_ns;\n mc_we_n = #TCQ mc_we_n_ns;\n mc_data_offset = #TCQ mc_data_offset_ns;\n mc_data_offset_1 = #TCQ mc_data_offset_1_ns;\n mc_data_offset_2 = #TCQ mc_data_offset_2_ns;\n mc_cas_slot = #TCQ mc_cas_slot_ns;\n mc_wrdata_en = #TCQ mc_wrdata_en_ns;\n mc_rank_cnt = #TCQ mc_rank_cnt_ns;\n\n wr_data_addr = #TCQ wr_data_addr_ns;\n wr_data_en = #TCQ wr_data_en_ns;\n wr_data_offset = #TCQ wr_data_offset_ns;\n\n end // always @ (...\n\n end // block: cmd_pipe_plus0\n\n endgenerate\n\n //***************************************************************************\n // Indicate when there are no pending reads so that input features can be\n // powered down\n //***************************************************************************\n \n assign mc_read_idle_ns = col_read_fifo_empty & init_calib_complete;\n always @(posedge clk) mc_read_idle_r <= #TCQ mc_read_idle_ns;\n assign mc_read_idle = mc_read_idle_r;\n\n //***************************************************************************\n // Indicate when there is a refresh in progress and the bus is idle so that\n // tap adjustments can be made\n //***************************************************************************\n\n assign mc_ref_zq_wip_ns = maint_ref_zq_wip && col_read_fifo_empty;\n always @(posedge clk) mc_ref_zq_wip_r <= mc_ref_zq_wip_ns;\n assign mc_ref_zq_wip = mc_ref_zq_wip_r;\n\n //***************************************************************************\n // Manage rank-level timing and maintanence\n //***************************************************************************\n \n mig_7series_v4_0_rank_mach #\n (\n // Parameters\n .BURST_MODE (BURST_MODE),\n .CL (CL),\n .CWL (CWL),\n .CS_WIDTH (CS_WIDTH),\n .DQRD2DQWR_DLY (DQRD2DQWR_DLY),\n .DRAM_TYPE (DRAM_TYPE),\n .MAINT_PRESCALER_DIV (MAINT_PRESCALER_DIV),\n .nBANK_MACHS (nBANK_MACHS),\n .nCKESR (nCKESR),\n .nCK_PER_CLK (nCK_PER_CLK),\n .nFAW (nFAW),\n .nREFRESH_BANK (nREFRESH_BANK),\n .nRRD (nRRD),\n .nWTR (nWTR),\n .PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV),\n .RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH),\n .RANK_WIDTH (RANK_WIDTH),\n .RANKS (RANKS),\n .REFRESH_TIMER_DIV (REFRESH_TIMER_DIV),\n .ZQ_TIMER_DIV (ZQ_TIMER_DIV)\n )\n rank_mach0\n (\n // Outputs\n .inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]),\n .inhbt_rd (inhbt_rd[RANKS-1:0]),\n .inhbt_wr (inhbt_wr[RANKS-1:0]),\n .maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),\n .maint_req_r (maint_req_r),\n .maint_zq_r (maint_zq_r),\n .maint_sre_r (maint_sre_r),\n .maint_srx_r (maint_srx_r),\n .maint_ref_zq_wip (maint_ref_zq_wip),\n .periodic_rd_r (periodic_rd_r),\n .periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),\n // Inputs\n .act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]),\n .app_periodic_rd_req (app_periodic_rd_req),\n .app_ref_req (app_ref_req),\n .app_ref_ack (app_ref_ack),\n .app_zq_req (app_zq_req),\n .app_zq_ack (app_zq_ack),\n .app_sr_req (app_sr_req),\n .app_sr_active (app_sr_active),\n .col_rd_wr (col_rd_wr),\n .clk (clk),\n .init_calib_complete (init_calib_complete),\n .insert_maint_r1 (insert_maint_r1),\n .maint_wip_r (maint_wip_r),\n .periodic_rd_ack_r (periodic_rd_ack_r),\n .rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]),\n .rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]),\n .rst (rst),\n .sending_col (sending_col[nBANK_MACHS-1:0]),\n .sending_row (sending_row[nBANK_MACHS-1:0]),\n .slot_0_present (slot_0_present[7:0]),\n .slot_1_present (slot_1_present[7:0]),\n .wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0])\n );\n\n //***************************************************************************\n // Manage requests, reordering and bank timing\n //***************************************************************************\n\n mig_7series_v4_0_bank_mach #\n (\n // Parameters\n .TCQ (TCQ),\n .EVEN_CWL_2T_MODE (EVEN_CWL_2T_MODE),\n .ADDR_CMD_MODE (ADDR_CMD_MODE),\n .BANK_WIDTH (BANK_WIDTH),\n .BM_CNT_WIDTH (BM_CNT_WIDTH),\n .BURST_MODE (BURST_MODE),\n .COL_WIDTH (COL_WIDTH),\n .CS_WIDTH (CS_WIDTH),\n .CL (CL_M),\n .CWL (CWL_M),\n .CKE_ODT_AUX (CKE_ODT_AUX),\n .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),\n .DRAM_TYPE (DRAM_TYPE),\n .EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),\n .ECC (ECC),\n .LOW_IDLE_CNT (LOW_IDLE_CNT),\n .nBANK_MACHS (nBANK_MACHS),\n .nCK_PER_CLK (nCK_PER_CLK),\n .nCS_PER_RANK (nCS_PER_RANK),\n .nOP_WAIT (nOP_WAIT),\n .nRAS (nRAS),\n .nRCD (nRCD),\n .nRFC (nRFC),\n .nRP (nRP),\n .nRTP (nRTP),\n .nSLOTS (nSLOTS),\n .nWR (nWR),\n .nXSDLL (tXSDLL),\n .ORDERING (ORDERING),\n .RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH),\n .RANK_WIDTH (RANK_WIDTH),\n .RANKS (RANKS),\n .ROW_WIDTH (ROW_WIDTH),\n .RTT_NOM (RTT_NOM),\n .RTT_WR (RTT_WR),\n .SLOT_0_CONFIG (SLOT_0_CONFIG),\n .SLOT_1_CONFIG (SLOT_1_CONFIG),\n .STARVE_LIMIT (STARVE_LIMIT),\n .tZQCS (tZQCS)\n )\n bank_mach0\n (\n // Outputs\n .accept (accept),\n .accept_ns (accept_ns),\n .act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]),\n .bank_mach_next (bank_mach_next[BM_CNT_WIDTH-1:0]),\n .col_a (col_a[ROW_WIDTH-1:0]),\n .col_ba (col_ba[BANK_WIDTH-1:0]),\n .col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),\n .col_periodic_rd (col_periodic_rd),\n .col_ra (col_ra[RANK_WIDTH-1:0]),\n .col_rmw (col_rmw),\n .col_rd_wr (col_rd_wr),\n .col_row (col_row[ROW_WIDTH-1:0]),\n .col_size (col_size),\n .col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),\n .mc_bank (mc_bank_ns),\n .mc_address (mc_address_ns),\n .mc_ras_n (mc_ras_n_ns),\n .mc_cas_n (mc_cas_n_ns),\n .mc_we_n (mc_we_n_ns),\n .mc_cs_n (mc_cs_n_ns),\n .mc_odt (mc_odt_ns),\n .mc_cke (mc_cke_ns),\n .mc_aux_out0 (mc_aux_out0_ns),\n .mc_aux_out1 (mc_aux_out1_ns),\n .mc_cmd (mc_cmd_ns),\n .mc_data_offset (mc_data_offset_ns),\n .mc_data_offset_1 (mc_data_offset_1_ns),\n .mc_data_offset_2 (mc_data_offset_2_ns),\n .mc_cas_slot (mc_cas_slot_ns),\n .insert_maint_r1 (insert_maint_r1),\n .maint_wip_r (maint_wip_r),\n .periodic_rd_ack_r (periodic_rd_ack_r),\n .rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]),\n .rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]),\n .sending_row (sending_row[nBANK_MACHS-1:0]),\n .sending_col (sending_col[nBANK_MACHS-1:0]),\n .sent_col (sent_col),\n .sent_col_r (sent_col_r),\n .wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0]),\n // Inputs\n .bank (bank[BANK_WIDTH-1:0]),\n .calib_rddata_offset (calib_rd_data_offset),\n .calib_rddata_offset_1 (calib_rd_data_offset_1),\n .calib_rddata_offset_2 (calib_rd_data_offset_2),\n .clk (clk),\n .cmd (cmd[2:0]),\n .col (col[COL_WIDTH-1:0]),\n .data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),\n .init_calib_complete (init_calib_complete),\n .phy_rddata_valid (phy_rddata_valid),\n .dq_busy_data (dq_busy_data),\n .hi_priority (hi_priority),\n .inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]),\n .inhbt_rd (inhbt_rd[RANKS-1:0]),\n .inhbt_wr (inhbt_wr[RANKS-1:0]),\n .maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),\n .maint_req_r (maint_req_r),\n .maint_zq_r (maint_zq_r),\n .maint_sre_r (maint_sre_r),\n .maint_srx_r (maint_srx_r),\n .periodic_rd_r (periodic_rd_r),\n .periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),\n .phy_mc_cmd_full (phy_mc_cmd_full),\n .phy_mc_ctl_full (phy_mc_ctl_full),\n .phy_mc_data_full (phy_mc_data_full),\n .rank (rank[RANK_WIDTH-1:0]),\n .rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),\n .rd_rmw (rd_rmw),\n .row (row[ROW_WIDTH-1:0]),\n .rst (rst),\n .size (size),\n .slot_0_present (slot_0_present[7:0]),\n .slot_1_present (slot_1_present[7:0]),\n .use_addr (use_addr)\n );\n\n //***************************************************************************\n // Manage DQ bus\n //***************************************************************************\n\n mig_7series_v4_0_col_mach #\n (\n // Parameters\n .TCQ (TCQ),\n .BANK_WIDTH (BANK_WIDTH),\n .BURST_MODE (BURST_MODE),\n .COL_WIDTH (COL_WIDTH),\n .CS_WIDTH (CS_WIDTH),\n .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),\n .DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH),\n .DELAY_WR_DATA_CNTRL (DELAY_WR_DATA_CNTRL),\n .DQS_WIDTH (DQS_WIDTH),\n .DRAM_TYPE (DRAM_TYPE),\n .EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),\n .ECC (ECC),\n .MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),\n .nCK_PER_CLK (nCK_PER_CLK),\n .nPHY_WRLAT (nPHY_WRLAT),\n .RANK_WIDTH (RANK_WIDTH),\n .ROW_WIDTH (ROW_WIDTH)\n )\n col_mach0\n (\n // Outputs\n .mc_wrdata_en (mc_wrdata_en_ns),\n .dq_busy_data (dq_busy_data),\n .ecc_err_addr (ecc_err_addr[MC_ERR_ADDR_WIDTH-1:0]),\n .ecc_status_valid (ecc_status_valid),\n .rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),\n .rd_data_en (rd_data_en),\n .rd_data_end (rd_data_end),\n .rd_data_offset (rd_data_offset),\n .rd_rmw (rd_rmw),\n .wr_data_addr (wr_data_addr_ns),\n .wr_data_en (wr_data_en_ns),\n .wr_data_offset (wr_data_offset_ns),\n .wr_ecc_buf (wr_ecc_buf),\n .col_read_fifo_empty (col_read_fifo_empty),\n // Inputs\n .clk (clk),\n .rst (rst),\n .col_a (col_a[ROW_WIDTH-1:0]),\n .col_ba (col_ba[BANK_WIDTH-1:0]),\n .col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),\n .col_periodic_rd (col_periodic_rd),\n .col_ra (col_ra[RANK_WIDTH-1:0]),\n .col_rmw (col_rmw),\n .col_rd_wr (col_rd_wr),\n .col_row (col_row[ROW_WIDTH-1:0]),\n .col_size (col_size),\n .col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),\n .phy_rddata_valid (phy_rddata_valid),\n .sent_col (EVEN_CWL_2T_MODE == \"ON\" ? sent_col_r : sent_col)\n );\n\n //***************************************************************************\n // Implement ECC\n //***************************************************************************\n \n // Total ECC word length = ECC code width + Data width\n localparam CODE_WIDTH = DATA_WIDTH + ECC_WIDTH;\n\n generate\n\n if (ECC == \"OFF\") begin : ecc_off\n \n assign rd_data = phy_rd_data;\n assign mc_wrdata = wr_data;\n assign mc_wrdata_mask = wr_data_mask;\n assign ecc_single = 4'b0;\n assign ecc_multiple = 4'b0;\n \n end\n\n else begin : ecc_on\n \n wire [CODE_WIDTH*ECC_WIDTH-1:0] h_rows;\n wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data;\n wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata_i;\n\n \n // Merge and encode\n mig_7series_v4_0_ecc_merge_enc #\n (\n // Parameters\n .TCQ (TCQ),\n .CODE_WIDTH (CODE_WIDTH),\n .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),\n .DATA_WIDTH (DATA_WIDTH),\n .DQ_WIDTH (DQ_WIDTH),\n .ECC_WIDTH (ECC_WIDTH),\n .PAYLOAD_WIDTH (PAYLOAD_WIDTH),\n .nCK_PER_CLK (nCK_PER_CLK)\n )\n ecc_merge_enc0\n (\n // Outputs\n .mc_wrdata (mc_wrdata_i),\n .mc_wrdata_mask (mc_wrdata_mask),\n // Inputs\n .clk (clk),\n .rst (rst),\n .h_rows (h_rows),\n .rd_merge_data (rd_merge_data),\n .raw_not_ecc (raw_not_ecc),\n .wr_data (wr_data),\n .wr_data_mask (wr_data_mask)\n );\n\n // Decode and fix\n mig_7series_v4_0_ecc_dec_fix #\n (\n // Parameters\n .TCQ (TCQ),\n .CODE_WIDTH (CODE_WIDTH), \n .DATA_WIDTH (DATA_WIDTH),\n .DQ_WIDTH (DQ_WIDTH),\n .ECC_WIDTH (ECC_WIDTH),\n .PAYLOAD_WIDTH (PAYLOAD_WIDTH),\n .nCK_PER_CLK (nCK_PER_CLK)\n )\n ecc_dec_fix0\n (\n // Outputs\n .ecc_multiple (ecc_multiple), \n .ecc_single (ecc_single),\n .rd_data (rd_data),\n // Inputs\n .clk (clk),\n .rst (rst),\n .correct_en (correct_en),\n .phy_rddata (phy_rd_data), \n .ecc_status_valid (ecc_status_valid),\n .h_rows (h_rows)\n );\n\n // ECC Buffer\n mig_7series_v4_0_ecc_buf #\n (\n // Parameters\n .TCQ (TCQ),\n .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),\n .DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH),\n .DATA_WIDTH (DATA_WIDTH),\n .PAYLOAD_WIDTH (PAYLOAD_WIDTH),\n .nCK_PER_CLK (nCK_PER_CLK)\n )\n ecc_buf0\n ( \n // Outputs\n .rd_merge_data (rd_merge_data),\n // Inputs\n .clk (clk),\n .rst (rst),\n .rd_data (rd_data),\n .rd_data_addr (rd_data_addr),\n .rd_data_offset (rd_data_offset),\n .wr_data_addr (wr_data_addr),\n .wr_data_offset (wr_data_offset),\n .wr_ecc_buf (wr_ecc_buf)\n );\n \n // Generate ECC table\n mig_7series_v4_0_ecc_gen #\n (\n // Parameters\n .CODE_WIDTH (CODE_WIDTH),\n .DATA_WIDTH (DATA_WIDTH),\n .ECC_WIDTH (ECC_WIDTH)\n )\n ecc_gen0\n (\n // Outputs\n .h_rows (h_rows)\n );\n\n\n\n if (ECC == \"ON\") begin : gen_fi_xor_inst\n reg mc_wrdata_en_r; \n wire mc_wrdata_en_i;\n\n always @(posedge clk) begin\n mc_wrdata_en_r <= mc_wrdata_en;\n end\n\n assign mc_wrdata_en_i = mc_wrdata_en_r;\n\n mig_7series_v4_0_fi_xor #(\n .DQ_WIDTH (DQ_WIDTH),\n .DQS_WIDTH (DQS_WIDTH),\n .nCK_PER_CLK (nCK_PER_CLK)\n )\n fi_xor0\n (\n .clk (clk),\n .wrdata_in (mc_wrdata_i),\n .wrdata_out (mc_wrdata),\n .wrdata_en (mc_wrdata_en_i),\n .fi_xor_we (fi_xor_we),\n .fi_xor_wrdata (fi_xor_wrdata)\n );\n end\n else begin : gen_wrdata_passthru\n assign mc_wrdata = mc_wrdata_i;\n end\n\n\n `ifdef DISPLAY_H_MATRIX\n\n integer i;\n\n always @(negedge rst) begin\n \n $display (\"**********************************************\");\n $display (\"H Matrix:\");\n\n for (i=0; iout delay (sim only)\n parameter BURST_MODE = \"8\", // Burst length\n parameter DQRD2DQWR_DLY = 2, // RD->WR DQ Bus Delay\n parameter CL = 5, // Read CAS latency\n parameter CWL = 5, // Write CAS latency\n parameter ID = 0, // Unique ID for each instance\n parameter nBANK_MACHS = 4, // # bank machines in MC\n parameter nCK_PER_CLK = 2, // DRAM clock : MC clock\n parameter nFAW = 30, // four activate window (CKs)\n parameter nREFRESH_BANK = 8, // # REF commands to pull-in\n parameter nRRD = 4, // ACT->ACT period (CKs)\n parameter nWTR = 4, // Internal write->read \n // delay (CKs)\n parameter PERIODIC_RD_TIMER_DIV = 20, // Maintenance prescaler divisor\n // for periodic read timer\n parameter RANK_BM_BV_WIDTH = 16, // Width required to broadcast a\n // single bit rank signal among\n // all the bank machines\n parameter RANK_WIDTH = 2, // # of bits to count ranks\n parameter RANKS = 4, // # of ranks of DRAM\n parameter REFRESH_TIMER_DIV = 39 // Maintenance prescaler divivor\n // for refresh timer\n )\n (\n\n // Maintenance requests\n\n output periodic_rd_request,\n output wire refresh_request,\n \n // Inhibit signals\n \n output reg inhbt_act_faw_r,\n output reg inhbt_rd,\n output reg inhbt_wr,\n \n // System Inputs\n \n input clk,\n input rst,\n\n // User maintenance requests\n \n input app_periodic_rd_req,\n input app_ref_req,\n \n // Inputs\n \n input [RANK_BM_BV_WIDTH-1:0] act_this_rank_r,\n input clear_periodic_rd_request,\n input col_rd_wr,\n input init_calib_complete,\n input insert_maint_r1,\n input maint_prescaler_tick_r,\n input [RANK_WIDTH-1:0] maint_rank_r,\n input maint_zq_r,\n input maint_sre_r,\n input maint_srx_r,\n input [(RANKS*nBANK_MACHS)-1:0] rank_busy_r,\n input refresh_tick, \n input [nBANK_MACHS-1:0] sending_col,\n input [nBANK_MACHS-1:0] sending_row,\n input [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r,\n input [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r\n\n );\n\n //***************************************************************************\n // RRD configuration. The bank machines have a mechanism to prevent RAS to\n // RAS on adjacent fabric CLK states to the same rank. When\n // nCK_PER_CLK == 1, this translates to a minimum of 2 for nRRD, 4 for nRRD\n // when nCK_PER_CLK == 2 and 8 for nRRD when nCK_PER_CLK == 4. Some of the\n // higher clock rate DDR3 DRAMs have nRRD > 4. The additional RRD inhibit\n // is worked into the inhbt_faw signal.\n //***************************************************************************\n\n localparam nADD_RRD = nRRD -\n (\n (nCK_PER_CLK == 1) ? 2 :\n (nCK_PER_CLK == 2) ? 4 :\n /*(nCK_PER_CLK == 4)*/ 8\n );\n\n // divide by nCK_PER_CLK and add a cycle if there's a remainder\n localparam nRRD_CLKS = \n (nCK_PER_CLK == 1) ? nADD_RRD :\n (nCK_PER_CLK == 2) ? ((nADD_RRD/2)+(nADD_RRD%2)) :\n /*(nCK_PER_CLK == 4)*/ ((nADD_RRD/4)+((nADD_RRD%4) ? 1 : 0));\n\n // take binary log to obtain counter width and add a tick for the idle cycle\n localparam ADD_RRD_CNTR_WIDTH = clogb2(nRRD_CLKS + /* idle state */ 1);\n\n //***************************************************************************\n // Internal signals\n //***************************************************************************\n reg act_this_rank;\n integer i; // loop invariant\n \n //***************************************************************************\n // Function clogb2\n // Description:\n // This function performs binary logarithm and rounds up\n // Inputs:\n // size: integer to perform binary log upon\n // Outputs:\n // clogb2: result of binary logarithm, rounded up\n //***************************************************************************\n \n function integer clogb2 (input integer size);\n begin\n \n size = size - 1;\n\n // increment clogb2 from 1 for each bit in size\n for (clogb2 = 1; size > 1; clogb2 = clogb2 + 1)\n size = size >> 1;\n\n end\n endfunction // clogb2\n\n //***************************************************************************\n // Determine if this rank has been activated. act_this_rank_r is a\n // registered bit vector from individual bank machines indicating the\n // corresponding bank machine is sending\n // an activate. Timing is improved with this method.\n //***************************************************************************\n \n always @(/*AS*/act_this_rank_r or sending_row) begin\n \n act_this_rank = 1'b0;\n \n for (i = 0; i < nBANK_MACHS; i = i + 1)\n act_this_rank =\n act_this_rank || (sending_row[i] && act_this_rank_r[(i*RANKS)+ID]);\n \n end\n\n\n\n reg add_rrd_inhbt = 1'b0;\n generate\n if (nADD_RRD > 0 && ADD_RRD_CNTR_WIDTH > 1) begin :add_rdd1\n reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_ns;\n reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_r;\n always @(/*AS*/act_this_rank or add_rrd_r or rst) begin\n add_rrd_ns = add_rrd_r;\n if (rst) add_rrd_ns = {ADD_RRD_CNTR_WIDTH{1'b0}};\n else\n if (act_this_rank)\n add_rrd_ns = nRRD_CLKS[0+:ADD_RRD_CNTR_WIDTH];\n else if (|add_rrd_r) add_rrd_ns =\n add_rrd_r - {{ADD_RRD_CNTR_WIDTH-1{1'b0}}, 1'b1};\n end\n always @(posedge clk) add_rrd_r <= #TCQ add_rrd_ns;\n always @(/*AS*/add_rrd_ns) add_rrd_inhbt = |add_rrd_ns;\n end // add_rdd1\n else if (nADD_RRD > 0) begin :add_rdd0\n reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_ns;\n reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_r;\n always @(/*AS*/act_this_rank or add_rrd_r or rst) begin\n add_rrd_ns = add_rrd_r;\n if (rst) add_rrd_ns = {ADD_RRD_CNTR_WIDTH{1'b0}};\n else\n if (act_this_rank)\n add_rrd_ns = nRRD_CLKS[0+:ADD_RRD_CNTR_WIDTH];\n else if (|add_rrd_r) add_rrd_ns =\n add_rrd_r - {1'b1};\n end\n always @(posedge clk) add_rrd_r <= #TCQ add_rrd_ns;\n always @(/*AS*/add_rrd_ns) add_rrd_inhbt = |add_rrd_ns;\n end // add_rdd0\n endgenerate\n\n\n// Compute inhbt_act_faw_r. Only allow a limited number of activates\n// in a window. Both the number of activates and the window are\n// configurable. This depends on the RRD mechanism to prevent\n// two consecutive activates to the same rank.\n//\n// Subtract three from the specified nFAW. Subtract three because:\n// -Zero for the delay into the SRL is really one state.\n// -Sending_row is used to trigger the delay. Sending_row is one\n// state delayed from the arb.\n// -inhbt_act_faw_r is registered to make timing work, hence the\n// generation needs to be one state early.\n\n localparam nFAW_CLKS = (nCK_PER_CLK == 1)\n ? nFAW\n : (nCK_PER_CLK == 2) ? ((nFAW/2) + (nFAW%2)) : \n ((nFAW/4) + ((nFAW%4) ? 1 : 0));\n\n generate\n begin : inhbt_act_faw\n wire act_delayed;\n wire [4:0] shift_depth = nFAW_CLKS[4:0] - 5'd3;\n\n SRLC32E #(.INIT(32'h00000000) ) SRLC32E0\n (.Q(act_delayed), // SRL data output\n .Q31(), // SRL cascade output pin\n .A(shift_depth), // 5-bit shift depth select input\n .CE(1'b1), // Clock enable input\n .CLK(clk), // Clock input\n .D(act_this_rank) // SRL data input\n );\n\n reg [2:0] faw_cnt_ns;\n reg [2:0] faw_cnt_r;\n reg inhbt_act_faw_ns;\n always @(/*AS*/act_delayed or act_this_rank or add_rrd_inhbt\n or faw_cnt_r or rst) begin\n if (rst) faw_cnt_ns = 3'b0;\n else begin\n faw_cnt_ns = faw_cnt_r;\n if (act_this_rank) faw_cnt_ns = faw_cnt_r + 3'b1;\n if (act_delayed) faw_cnt_ns = faw_cnt_ns - 3'b1;\n end\n inhbt_act_faw_ns = (faw_cnt_ns == 3'h4) || add_rrd_inhbt;\n end\n always @(posedge clk) faw_cnt_r <= #TCQ faw_cnt_ns;\n always @(posedge clk) inhbt_act_faw_r <= #TCQ inhbt_act_faw_ns;\n end // block: inhbt_act_faw\n endgenerate\n\n\n// In the DRAM spec, tWTR starts from CK following the end of the data\n// burst. Since we don't directly have that spec, the wtr timer is\n// based on when the CAS write command is sent to the DRAM.\n//\n// To compute the wtr timer value, first compute the time from the write command\n// to the read command. This is CWL + data_time + nWTR.\n//\n// Two is subtracted from the required wtr time since the timer\n// starts two states after the arbitration cycle.\n\n localparam ONE = 1;\n localparam TWO = 2;\n\n localparam CASWR2CASRD = CWL + (BURST_MODE == \"4\" ? 2 : 4) + nWTR;\n localparam CASWR2CASRD_CLKS = (nCK_PER_CLK == 1)\n ? CASWR2CASRD :\n (nCK_PER_CLK == 2)\n ? ((CASWR2CASRD / 2) + (CASWR2CASRD % 2)) :\n ((CASWR2CASRD / 4) + ((CASWR2CASRD % 4) ? 1 :0));\n localparam WTR_CNT_WIDTH = clogb2(CASWR2CASRD_CLKS);\n\n generate\n begin : wtr_timer\n\n reg write_this_rank;\n always @(/*AS*/sending_col or wr_this_rank_r) begin\n write_this_rank = 1'b0;\n for (i = 0; i < nBANK_MACHS; i = i + 1)\n write_this_rank =\n write_this_rank || (sending_col[i] && wr_this_rank_r[(i*RANKS)+ID]);\n end\n\n reg [WTR_CNT_WIDTH-1:0] wtr_cnt_r;\n reg [WTR_CNT_WIDTH-1:0] wtr_cnt_ns;\n\n always @(/*AS*/rst or write_this_rank or wtr_cnt_r)\n if (rst) wtr_cnt_ns = {WTR_CNT_WIDTH{1'b0}};\n else begin\n wtr_cnt_ns = wtr_cnt_r;\n if (write_this_rank) wtr_cnt_ns =\n CASWR2CASRD_CLKS[WTR_CNT_WIDTH-1:0] - ONE[WTR_CNT_WIDTH-1:0];\n else if (|wtr_cnt_r) wtr_cnt_ns = wtr_cnt_r - ONE[WTR_CNT_WIDTH-1:0];\n end\n\n wire inhbt_rd_ns = |wtr_cnt_ns;\n\n always @(posedge clk) wtr_cnt_r <= #TCQ wtr_cnt_ns;\n always @(inhbt_rd_ns) inhbt_rd = inhbt_rd_ns;\n\n end\n endgenerate\n\n// In the DRAM spec (with AL = 0), the read-to-write command delay is implied to\n// be CL + data_time + 2 tCK - CWL. The CL + data_time - CWL terms ensure the\n// read and write data do not collide on the DQ bus. The 2 tCK ensures a gap\n// between them. Here, we allow the user to tune this fixed term via the\n// DQRD2DQWR_DLY parameter. There's a potential for optimization by relocating\n// this to the rank_common module, since this is a DQ/DQS bus-level requirement,\n// not a per-rank requirement.\n\n localparam CASRD2CASWR = CL + (BURST_MODE == \"4\" ? 2 : 4) + DQRD2DQWR_DLY - CWL;\n localparam CASRD2CASWR_CLKS = (nCK_PER_CLK == 1)\n ? CASRD2CASWR :\n (nCK_PER_CLK == 2)\n ? ((CASRD2CASWR / 2) + (CASRD2CASWR % 2)) :\n ((CASRD2CASWR / 4) + ((CASRD2CASWR % 4) ? 1 :0));\n localparam RTW_CNT_WIDTH = clogb2(CASRD2CASWR_CLKS);\n \n generate\n begin : rtw_timer\n\n reg read_this_rank;\n always @(/*AS*/sending_col or rd_this_rank_r) begin\n read_this_rank = 1'b0;\n for (i = 0; i < nBANK_MACHS; i = i + 1)\n read_this_rank =\n read_this_rank || (sending_col[i] && rd_this_rank_r[(i*RANKS)+ID]);\n end\n\n reg [RTW_CNT_WIDTH-1:0] rtw_cnt_r;\n reg [RTW_CNT_WIDTH-1:0] rtw_cnt_ns;\n\n always @(/*AS*/rst or col_rd_wr or sending_col or rtw_cnt_r)\n if (rst) rtw_cnt_ns = {RTW_CNT_WIDTH{1'b0}};\n else begin\n rtw_cnt_ns = rtw_cnt_r;\n if (col_rd_wr && |sending_col) rtw_cnt_ns =\n CASRD2CASWR_CLKS[RTW_CNT_WIDTH-1:0] - ONE[RTW_CNT_WIDTH-1:0];\n else if (|rtw_cnt_r) rtw_cnt_ns = rtw_cnt_r - ONE[RTW_CNT_WIDTH-1:0];\n end\n\n wire inhbt_wr_ns = |rtw_cnt_ns;\n\n always @(posedge clk) rtw_cnt_r <= #TCQ rtw_cnt_ns;\n always @(inhbt_wr_ns) inhbt_wr = inhbt_wr_ns;\n\n end\n endgenerate\n\n// Refresh request generation. Implement a \"refresh bank\". Referred\n// to as pullin-in refresh in the JEDEC spec.\n// The refresh_rank_r counter increments when a refresh to this\n// rank has been decoded. In the up direction, the count saturates\n// at nREFRESH_BANK. As specified in the JEDEC spec, nREFRESH_BANK\n// is normally eight. The counter decrements with each refresh_tick,\n// saturating at zero. A refresh will be requests when the rank is\n// not busy and refresh_rank_r != nREFRESH_BANK, or refresh_rank_r\n// equals zero.\n\n localparam REFRESH_BANK_WIDTH = clogb2(nREFRESH_BANK + 1);\n\n \n generate begin : refresh_generation\n reg my_rank_busy;\n always @(/*AS*/rank_busy_r) begin\n my_rank_busy = 1'b0;\n for (i=0; i < nBANK_MACHS; i=i+1)\n my_rank_busy = my_rank_busy || rank_busy_r[(i*RANKS)+ID];\n end\n\n wire my_refresh =\n insert_maint_r1 && ~maint_zq_r && ~maint_sre_r && ~maint_srx_r &&\n (maint_rank_r == ID[RANK_WIDTH-1:0]);\n\n reg [REFRESH_BANK_WIDTH-1:0] refresh_bank_r;\n reg [REFRESH_BANK_WIDTH-1:0] refresh_bank_ns;\n always @(/*AS*/app_ref_req or init_calib_complete or my_refresh\n or refresh_bank_r or refresh_tick)\n if (~init_calib_complete)\n if (REFRESH_TIMER_DIV == 0)\n refresh_bank_ns = nREFRESH_BANK[0+:REFRESH_BANK_WIDTH];\n else refresh_bank_ns = {REFRESH_BANK_WIDTH{1'b0}};\n else\n case ({my_refresh, refresh_tick, app_ref_req})\n 3'b000, 3'b110, 3'b101, 3'b111 : refresh_bank_ns = refresh_bank_r;\n 3'b010, 3'b001, 3'b011 : refresh_bank_ns =\n (|refresh_bank_r)?\n refresh_bank_r - ONE[0+:REFRESH_BANK_WIDTH]:\n refresh_bank_r;\n 3'b100 : refresh_bank_ns =\n refresh_bank_r + ONE[0+:REFRESH_BANK_WIDTH];\n endcase // case ({my_refresh, refresh_tick})\n always @(posedge clk) refresh_bank_r <= #TCQ refresh_bank_ns;\n\n `ifdef MC_SVA\n refresh_bank_overflow: assert property (@(posedge clk)\n (rst || (refresh_bank_r <= nREFRESH_BANK)));\n refresh_bank_underflow: assert property (@(posedge clk)\n (rst || ~(~|refresh_bank_r && ~my_refresh && refresh_tick)));\n refresh_hi_priority: cover property (@(posedge clk)\n (rst && ~|refresh_bank_ns && (refresh_bank_r ==\n ONE[0+:REFRESH_BANK_WIDTH])));\n refresh_bank_full: cover property (@(posedge clk)\n (rst && (refresh_bank_r ==\n nREFRESH_BANK[0+:REFRESH_BANK_WIDTH])));\n `endif\n\n assign refresh_request = init_calib_complete &&\n (~|refresh_bank_r ||\n ((refresh_bank_r != nREFRESH_BANK[0+:REFRESH_BANK_WIDTH]) && ~my_rank_busy));\n\n end\n endgenerate\n\n// Periodic read request generation.\n\n localparam PERIODIC_RD_TIMER_WIDTH = clogb2(PERIODIC_RD_TIMER_DIV + /*idle state*/ 1);\n\n \n generate begin : periodic_rd_generation\n if ( PERIODIC_RD_TIMER_DIV != 0 ) begin // enable periodic reads\n reg read_this_rank;\n always @(/*AS*/rd_this_rank_r or sending_col) begin\n read_this_rank = 1'b0;\n for (i = 0; i < nBANK_MACHS; i = i + 1)\n read_this_rank =\n read_this_rank || (sending_col[i] && rd_this_rank_r[(i*RANKS)+ID]);\n end\n\n reg read_this_rank_r;\n reg read_this_rank_r1;\n always @(posedge clk) read_this_rank_r <= #TCQ read_this_rank;\n always @(posedge clk) read_this_rank_r1 <= #TCQ read_this_rank_r;\n wire int_read_this_rank = read_this_rank &&\n (((nCK_PER_CLK == 4) && read_this_rank_r) ||\n\t\t\t\t ((nCK_PER_CLK != 4) && read_this_rank_r1));\n\n reg periodic_rd_cntr1_ns;\n reg periodic_rd_cntr1_r;\n always @(/*AS*/clear_periodic_rd_request or periodic_rd_cntr1_r) begin\n periodic_rd_cntr1_ns = periodic_rd_cntr1_r;\n if (clear_periodic_rd_request)\n periodic_rd_cntr1_ns = periodic_rd_cntr1_r + 1'b1;\n end\n always @(posedge clk) begin\n if (rst) periodic_rd_cntr1_r <= #TCQ 1'b0;\n else periodic_rd_cntr1_r <= #TCQ periodic_rd_cntr1_ns;\n end\n\n reg [PERIODIC_RD_TIMER_WIDTH-1:0] periodic_rd_timer_r;\n reg [PERIODIC_RD_TIMER_WIDTH-1:0] periodic_rd_timer_ns;\n wire periodic_rd_timer_one = maint_prescaler_tick_r &&\n (periodic_rd_timer_r == ONE[0+:PERIODIC_RD_TIMER_WIDTH]);\n\n always @(/*AS*/init_calib_complete or maint_prescaler_tick_r\n or periodic_rd_timer_r or int_read_this_rank) begin\n periodic_rd_timer_ns = periodic_rd_timer_r;\n if (~init_calib_complete)\n periodic_rd_timer_ns = PERIODIC_RD_TIMER_DIV[0+:PERIODIC_RD_TIMER_WIDTH];\n //periodic_rd_timer_ns = {PERIODIC_RD_TIMER_WIDTH{1'b0}};\n else if (int_read_this_rank || periodic_rd_timer_one)\n periodic_rd_timer_ns =\n PERIODIC_RD_TIMER_DIV[0+:PERIODIC_RD_TIMER_WIDTH];\n else if (|periodic_rd_timer_r && maint_prescaler_tick_r)\n periodic_rd_timer_ns =\n periodic_rd_timer_r - ONE[0+:PERIODIC_RD_TIMER_WIDTH];\n end\n always @(posedge clk) periodic_rd_timer_r <= #TCQ periodic_rd_timer_ns;\n\n reg periodic_rd_request_r;\n wire periodic_rd_request_ns = ~rst &&\n ((app_periodic_rd_req && init_calib_complete) ||\n ((PERIODIC_RD_TIMER_DIV != 0) && ~init_calib_complete) ||\n // (~(read_this_rank || clear_periodic_rd_request) &&\n (~((int_read_this_rank) || (clear_periodic_rd_request && periodic_rd_cntr1_r)) &&\n (periodic_rd_request_r || periodic_rd_timer_one)));\n always @(posedge clk) periodic_rd_request_r <=\n #TCQ periodic_rd_request_ns;\n\n `ifdef MC_SVA\n read_clears_periodic_rd_request: cover property (@(posedge clk)\n (rst && (periodic_rd_request_r && read_this_rank)));\n `endif\n\n assign periodic_rd_request = init_calib_complete && periodic_rd_request_r;\n end else\n assign periodic_rd_request = 1'b0; //to disable periodic reads\n\n end\n endgenerate\n\n\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/controller/mig_7series_v4_0_rank_common.v", "content": "//*****************************************************************************\n// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor : Xilinx\n// \\ \\ \\/ Version : %version\n// \\ \\ Application : MIG\n// / / Filename : rank_common.v\n// /___/ /\\ Date Last Modified : $date$\n// \\ \\ / \\ Date Created : Tue Jun 30 2009\n// \\___\\/\\___\\\n//\n//Device : 7-Series\n//Design Name : DDR3 SDRAM\n//Purpose :\n//Reference :\n//Revision History :\n//*****************************************************************************\n\n// Block for logic common to all rank machines. Contains\n// a clock prescaler, and arbiters for refresh and periodic\n// read functions.\n\n`timescale 1 ps / 1 ps\n\nmodule mig_7series_v4_0_rank_common #\n (\n parameter TCQ = 100,\n parameter DRAM_TYPE = \"DDR3\",\n parameter MAINT_PRESCALER_DIV = 40,\n parameter nBANK_MACHS = 4,\n parameter nCKESR = 4,\n parameter nCK_PER_CLK = 2,\n parameter PERIODIC_RD_TIMER_DIV = 20,\n parameter RANK_WIDTH = 2,\n parameter RANKS = 4,\n parameter REFRESH_TIMER_DIV = 39,\n parameter ZQ_TIMER_DIV = 640000\n )\n (/*AUTOARG*/\n // Outputs\n maint_prescaler_tick_r, refresh_tick, maint_zq_r, maint_sre_r, maint_srx_r,\n maint_req_r, maint_rank_r, clear_periodic_rd_request, periodic_rd_r,\n periodic_rd_rank_r, app_ref_ack, app_zq_ack, app_sr_active, maint_ref_zq_wip,\n // Inputs\n clk, rst, init_calib_complete, app_ref_req, app_zq_req, app_sr_req,\n insert_maint_r1, refresh_request, maint_wip_r, slot_0_present, slot_1_present,\n periodic_rd_request, periodic_rd_ack_r\n );\n\n function integer clogb2 (input integer size); // ceiling logb2\n begin\n size = size - 1;\n for (clogb2=1; size>1; clogb2=clogb2+1)\n size = size >> 1;\n end\n endfunction // clogb2\n\n input clk;\n input rst;\n\n// Maintenance and periodic read prescaler. Nominally 200 nS.\n localparam ONE = 1;\n localparam MAINT_PRESCALER_WIDTH = clogb2(MAINT_PRESCALER_DIV + 1);\n input init_calib_complete;\n reg maint_prescaler_tick_r_lcl;\n generate\n begin : maint_prescaler\n reg [MAINT_PRESCALER_WIDTH-1:0] maint_prescaler_r;\n reg [MAINT_PRESCALER_WIDTH-1:0] maint_prescaler_ns;\n wire maint_prescaler_tick_ns =\n (maint_prescaler_r == ONE[MAINT_PRESCALER_WIDTH-1:0]);\n always @(/*AS*/init_calib_complete or maint_prescaler_r\n or maint_prescaler_tick_ns) begin\n maint_prescaler_ns = maint_prescaler_r;\n if (~init_calib_complete || maint_prescaler_tick_ns)\n maint_prescaler_ns = MAINT_PRESCALER_DIV[MAINT_PRESCALER_WIDTH-1:0];\n else if (|maint_prescaler_r)\n maint_prescaler_ns = maint_prescaler_r - ONE[MAINT_PRESCALER_WIDTH-1:0];\n end\n always @(posedge clk) maint_prescaler_r <= #TCQ maint_prescaler_ns;\n\n always @(posedge clk) maint_prescaler_tick_r_lcl <=\n #TCQ maint_prescaler_tick_ns;\n end\n endgenerate\n output wire maint_prescaler_tick_r;\n assign maint_prescaler_tick_r = maint_prescaler_tick_r_lcl;\n\n// Refresh timebase. Nominically 7800 nS.\n localparam REFRESH_TIMER_WIDTH = clogb2(REFRESH_TIMER_DIV + /*idle*/ 1);\n wire refresh_tick_lcl;\n generate\n begin : refresh_timer\n reg [REFRESH_TIMER_WIDTH-1:0] refresh_timer_r;\n reg [REFRESH_TIMER_WIDTH-1:0] refresh_timer_ns;\n always @(/*AS*/init_calib_complete or maint_prescaler_tick_r_lcl\n or refresh_tick_lcl or refresh_timer_r) begin\n refresh_timer_ns = refresh_timer_r;\n if (~init_calib_complete || refresh_tick_lcl)\n refresh_timer_ns = REFRESH_TIMER_DIV[REFRESH_TIMER_WIDTH-1:0];\n else if (|refresh_timer_r && maint_prescaler_tick_r_lcl)\n refresh_timer_ns =\n refresh_timer_r - ONE[REFRESH_TIMER_WIDTH-1:0];\n end\n always @(posedge clk) refresh_timer_r <= #TCQ refresh_timer_ns;\n assign refresh_tick_lcl = (refresh_timer_r ==\n ONE[REFRESH_TIMER_WIDTH-1:0]) && maint_prescaler_tick_r_lcl;\n end\n endgenerate\n output wire refresh_tick;\n assign refresh_tick = refresh_tick_lcl;\n\n// ZQ timebase. Nominally 128 mS\n localparam ZQ_TIMER_WIDTH = clogb2(ZQ_TIMER_DIV + 1);\n input app_zq_req;\n input insert_maint_r1;\n reg maint_zq_r_lcl;\n reg zq_request = 1'b0;\n generate\n if (DRAM_TYPE == \"DDR3\") begin : zq_cntrl\n reg zq_tick = 1'b0;\n if (ZQ_TIMER_DIV !=0) begin : zq_timer\n reg [ZQ_TIMER_WIDTH-1:0] zq_timer_r;\n reg [ZQ_TIMER_WIDTH-1:0] zq_timer_ns;\n always @(/*AS*/init_calib_complete or maint_prescaler_tick_r_lcl\n or zq_tick or zq_timer_r) begin\n zq_timer_ns = zq_timer_r;\n if (~init_calib_complete || zq_tick)\n zq_timer_ns = ZQ_TIMER_DIV[ZQ_TIMER_WIDTH-1:0];\n else if (|zq_timer_r && maint_prescaler_tick_r_lcl)\n zq_timer_ns = zq_timer_r - ONE[ZQ_TIMER_WIDTH-1:0];\n end\n always @(posedge clk) zq_timer_r <= #TCQ zq_timer_ns;\n always @(/*AS*/maint_prescaler_tick_r_lcl or zq_timer_r)\n zq_tick = (zq_timer_r ==\n ONE[ZQ_TIMER_WIDTH-1:0] && maint_prescaler_tick_r_lcl);\n end // zq_timer\n\n// ZQ request. Set request with timer tick, and when exiting PHY init. Never\n// request if ZQ_TIMER_DIV == 0.\n begin : zq_request_logic\n wire zq_clears_zq_request = insert_maint_r1 && maint_zq_r_lcl;\n reg zq_request_r;\n wire zq_request_ns = ~rst && (DRAM_TYPE == \"DDR3\") &&\n ((~init_calib_complete && (ZQ_TIMER_DIV != 0)) ||\n (zq_request_r && ~zq_clears_zq_request) ||\n zq_tick ||\n (app_zq_req && init_calib_complete));\n always @(posedge clk) zq_request_r <= #TCQ zq_request_ns;\n always @(/*AS*/init_calib_complete or zq_request_r)\n zq_request = init_calib_complete && zq_request_r;\n end // zq_request_logic\n end\n endgenerate\n\n // Self-refresh control\n localparam nCKESR_CLKS = (nCKESR / nCK_PER_CLK) + (nCKESR % nCK_PER_CLK ? 1 : 0);\n localparam CKESR_TIMER_WIDTH = clogb2(nCKESR_CLKS + 1);\n input app_sr_req;\n reg maint_sre_r_lcl;\n reg maint_srx_r_lcl;\n reg sre_request = 1'b0;\n wire inhbt_srx;\n \n generate begin : sr_cntrl\n \n // SRE request. Set request with user request.\n begin : sre_request_logic\n\n reg sre_request_r;\n wire sre_clears_sre_request = insert_maint_r1 && maint_sre_r_lcl;\n\n wire sre_request_ns = ~rst && ((sre_request_r && ~sre_clears_sre_request)\n || (app_sr_req && init_calib_complete && ~maint_sre_r_lcl));\n \n always @(posedge clk) sre_request_r <= #TCQ sre_request_ns;\n \n always @(init_calib_complete or sre_request_r)\n sre_request = init_calib_complete && sre_request_r;\n \n end // sre_request_logic\n \n // CKESR timer: Self-Refresh must be maintained for a minimum of tCKESR\n begin : ckesr_timer\n \n reg [CKESR_TIMER_WIDTH-1:0] ckesr_timer_r = {CKESR_TIMER_WIDTH{1'b0}};\n reg [CKESR_TIMER_WIDTH-1:0] ckesr_timer_ns = {CKESR_TIMER_WIDTH{1'b0}};\n \n always @(insert_maint_r1 or ckesr_timer_r or maint_sre_r_lcl) begin\n \n ckesr_timer_ns = ckesr_timer_r;\n\n if (insert_maint_r1 && maint_sre_r_lcl)\n ckesr_timer_ns = nCKESR_CLKS[CKESR_TIMER_WIDTH-1:0];\n else if(|ckesr_timer_r)\n ckesr_timer_ns = ckesr_timer_r - ONE[CKESR_TIMER_WIDTH-1:0];\n \n end\n \n always @(posedge clk) ckesr_timer_r <= #TCQ ckesr_timer_ns;\n \n assign inhbt_srx = |ckesr_timer_r;\n \n end // ckesr_timer\n\n end\n\n endgenerate\n \n// DRAM maintenance operations of refresh and ZQ calibration, and self-refresh\n// DRAM maintenance operations and self-refresh have their own channel in the\n// queue. There is also a single, very simple bank machine\n// dedicated to these operations. Its assumed that the\n// maintenance operations can be completed quickly enough\n// to avoid any queuing.\n//\n// ZQ, refresh and self-refresh requests share a channel into controller.\n// Self-refresh is appended to the uppermost bit of the request bus and ZQ is\n// appended just below that.\n\n input[RANKS-1:0] refresh_request;\n input maint_wip_r;\n reg maint_req_r_lcl;\n reg [RANK_WIDTH-1:0] maint_rank_r_lcl;\n input [7:0] slot_0_present;\n input [7:0] slot_1_present;\n\n generate\n begin : maintenance_request\n\n// Maintenance request pipeline.\n reg upd_last_master_r;\n reg new_maint_rank_r;\n wire maint_busy = upd_last_master_r || new_maint_rank_r ||\n maint_req_r_lcl || maint_wip_r;\n wire [RANKS+1:0] maint_request = {sre_request, zq_request, refresh_request[RANKS-1:0]};\n //wire upd_last_master_ns = |maint_request && ~maint_busy;\n wire upd_last_master_ns = |maint_request && ~maint_wip_r;\n always @(posedge clk) upd_last_master_r <= #TCQ upd_last_master_ns;\n always @(posedge clk) new_maint_rank_r <= #TCQ upd_last_master_r;\n always @(posedge clk) maint_req_r_lcl <= #TCQ new_maint_rank_r;\n wire upd_last_master_pls = upd_last_master_r & (~new_maint_rank_r);\n\n// Arbitrate maintenance requests.\n wire [RANKS+1:0] maint_grant_ns;\n wire [RANKS+1:0] maint_grant_r;\n mig_7series_v4_0_round_robin_arb #\n (.WIDTH (RANKS+2))\n maint_arb0\n (.grant_ns (maint_grant_ns),\n .grant_r (maint_grant_r),\n .upd_last_master (upd_last_master_pls),\n .current_master (maint_grant_r),\n .req (maint_request),\n .disable_grant (1'b0),\n /*AUTOINST*/\n // Inputs\n .clk (clk),\n .rst (rst));\n\n// Look at arbitration results. Decide if ZQ, refresh or self-refresh.\n// If refresh select the maintenance rank from the winning rank controller.\n// If ZQ or self-refresh, generate a sequence of rank numbers corresponding to\n// slots populated maint_rank_r is not used for comparisons in the queue for ZQ\n// or self-refresh requests. The bank machine will enable CS for the number of\n// states equal to the the number of occupied slots. This will produce a\n// command to every occupied slot, but not in any particular order.\n wire [7:0] present = slot_0_present | slot_1_present;\n integer i;\n reg [RANK_WIDTH-1:0] maint_rank_ns;\n wire maint_zq_ns = ~rst && (upd_last_master_pls\n ? maint_grant_r[RANKS]\n : maint_zq_r_lcl);\n wire maint_srx_ns = ~rst && (maint_sre_r_lcl\n ? ~app_sr_req & ~inhbt_srx\n : maint_srx_r_lcl && upd_last_master_pls\n ? maint_grant_r[RANKS+1]\n : maint_srx_r_lcl);\n wire maint_sre_ns = ~rst && (upd_last_master_pls\n ? maint_grant_r[RANKS+1]\n : maint_sre_r_lcl && ~maint_srx_ns);\n always @(/*AS*/maint_grant_r or maint_rank_r_lcl or maint_zq_ns\n or maint_sre_ns or maint_srx_ns or present or rst\n or upd_last_master_pls) begin\n if (rst) maint_rank_ns = {RANK_WIDTH{1'b0}};\n else begin\n maint_rank_ns = maint_rank_r_lcl;\n if (maint_zq_ns || maint_sre_ns || maint_srx_ns) begin\n maint_rank_ns = maint_rank_r_lcl + ONE[RANK_WIDTH-1:0];\n for (i=0; i<8; i=i+1)\n if (~present[maint_rank_ns])\n maint_rank_ns = maint_rank_ns + ONE[RANK_WIDTH-1:0];\n end\n else\n if (upd_last_master_pls)\n for (i=0; i= 1.\n parameter C_S_AXI_MEM_SIZE = \"1073741824\",\n // Address Space required for this component\n parameter C_S_AXI_ADDR_WIDTH = 30,\n // Width of S_AXI_AWADDR, S_AXI_ARADDR, M_AXI_AWADDR and\n // M_AXI_ARADDR for all SI/MI slots.\n // # = 32.\n parameter C_S_AXI_DATA_WIDTH = 256,\n // Width of WDATA and RDATA on SI slot.\n // Must be <= APP_DATA_WIDTH.\n // # = 32, 64, 128, 256.\n parameter C_MC_nCK_PER_CLK = 4,\n // Indicates whether to instatiate upsizer\n // Range: 0, 1\n parameter C_S_AXI_SUPPORTS_NARROW_BURST = 0,\n // Indicates whether to instatiate upsizer\n // Range: 0, 1\n parameter C_RD_WR_ARB_ALGORITHM = \"RD_PRI_REG_STARVE_LIMIT\",\n // Indicates the Arbitration\n // Allowed values - \"TDM\", \"ROUND_ROBIN\",\n // \"RD_PRI_REG\", \"RD_PRI_REG_STARVE_LIMIT\"\n // \"WRITE_PRIORITY\", \"WRITE_PRIORITY_REG\"\n parameter C_S_AXI_REG_EN0 = 20'h00000,\n // C_S_AXI_REG_EN0[00] = Reserved\n // C_S_AXI_REG_EN0[04] = AW CHANNEL REGISTER SLICE\n // C_S_AXI_REG_EN0[05] = W CHANNEL REGISTER SLICE\n // C_S_AXI_REG_EN0[06] = B CHANNEL REGISTER SLICE\n // C_S_AXI_REG_EN0[07] = R CHANNEL REGISTER SLICE\n // C_S_AXI_REG_EN0[08] = AW CHANNEL UPSIZER REGISTER SLICE\n // C_S_AXI_REG_EN0[09] = W CHANNEL UPSIZER REGISTER SLICE\n // C_S_AXI_REG_EN0[10] = AR CHANNEL UPSIZER REGISTER SLICE\n // C_S_AXI_REG_EN0[11] = R CHANNEL UPSIZER REGISTER SLICE\n parameter C_S_AXI_REG_EN1 = 20'h00000,\n // Instatiates register slices after the upsizer.\n // The type of register is specified for each channel\n // in a vector. 4 bits per channel are used.\n // C_S_AXI_REG_EN1[03:00] = AW CHANNEL REGISTER SLICE\n // C_S_AXI_REG_EN1[07:04] = W CHANNEL REGISTER SLICE\n // C_S_AXI_REG_EN1[11:08] = B CHANNEL REGISTER SLICE\n // C_S_AXI_REG_EN1[15:12] = AR CHANNEL REGISTER SLICE\n // C_S_AXI_REG_EN1[20:16] = R CHANNEL REGISTER SLICE\n // Possible values for each channel are:\n //\n // 0 => BYPASS = The channel is just wired through the\n // module.\n // 1 => FWD = The master VALID and payload signals\n // are registrated.\n // 2 => REV = The slave ready signal is registrated\n // 3 => FWD_REV = Both FWD and REV\n // 4 => SLAVE_FWD = All slave side signals and master\n // VALID and payload are registrated.\n // 5 => SLAVE_RDY = All slave side signals and master\n // READY are registrated.\n // 6 => INPUTS = Slave and Master side inputs are\n // registrated.\n // 7 => ADDRESS = Optimized for address channel\n parameter C_S_AXI_CTRL_ADDR_WIDTH = 32,\n // Width of AXI-4-Lite address bus\n parameter C_S_AXI_CTRL_DATA_WIDTH = 32,\n // Width of AXI-4-Lite data buses\n parameter C_S_AXI_BASEADDR = 32'h0000_0000,\n // Base address of AXI4 Memory Mapped bus.\n parameter C_ECC_ONOFF_RESET_VALUE = 1,\n // Controls ECC on/off value at startup/reset\n parameter C_ECC_CE_COUNTER_WIDTH = 8,\n // The external memory to controller clock ratio.\n\n //***************************************************************************\n // Debug parameters\n //***************************************************************************\n parameter DEBUG_PORT = \"OFF\",\n // # = \"ON\" Enable debug signals/controls.\n // = \"OFF\" Disable debug signals/controls.\n\n //***************************************************************************\n // Temparature monitor parameter\n //***************************************************************************\n parameter TEMP_MON_CONTROL = \"INTERNAL\",\n // # = \"INTERNAL\", \"EXTERNAL\"\n //***************************************************************************\n // FPGA Voltage Type parameter\n //***************************************************************************\n parameter FPGA_VOLT_TYPE = \"N\",\n // # = \"L\", \"N\". When FPGA VccINT is 0.9v,\n // the value is \"L\", else it is \"N\"\n \n parameter RST_ACT_LOW = 1\n // =1 for active low reset,\n // =0 for active high.\n )\n (\n\n // Inouts\n inout [DQ_WIDTH-1:0] ddr3_dq,\n inout [DQS_WIDTH-1:0] ddr3_dqs_n,\n inout [DQS_WIDTH-1:0] ddr3_dqs_p,\n\n // Outputs\n output [ROW_WIDTH-1:0] ddr3_addr,\n output [BANK_WIDTH-1:0] ddr3_ba,\n output ddr3_ras_n,\n output ddr3_cas_n,\n output ddr3_we_n,\n output ddr3_reset_n,\n output [CK_WIDTH-1:0] ddr3_ck_p,\n output [CK_WIDTH-1:0] ddr3_ck_n,\n output [CKE_WIDTH-1:0] ddr3_cke,\n \n output [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_cs_n,\n \n output [DM_WIDTH-1:0] ddr3_dm,\n \n output [ODT_WIDTH-1:0] ddr3_odt,\n \n\n // Inputs\n \n // Single-ended system clock\n input sys_clk_i,\n \n \n // user interface signals\n output ui_clk,\n output ui_clk_sync_rst,\n \n output mmcm_locked,\n \n input aresetn,\n input app_sr_req,\n input app_ref_req,\n input app_zq_req,\n output app_sr_active,\n output app_ref_ack,\n output app_zq_ack,\n\n // Slave Interface Write Address Ports\n input [C_S_AXI_ID_WIDTH-1:0] s_axi_awid,\n input [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,\n input [7:0] s_axi_awlen,\n input [2:0] s_axi_awsize,\n input [1:0] s_axi_awburst,\n input [0:0] s_axi_awlock,\n input [3:0] s_axi_awcache,\n input [2:0] s_axi_awprot,\n input [3:0] s_axi_awqos,\n input s_axi_awvalid,\n output s_axi_awready,\n // Slave Interface Write Data Ports\n input [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata,\n input [(C_S_AXI_DATA_WIDTH/8)-1:0] s_axi_wstrb,\n input s_axi_wlast,\n input s_axi_wvalid,\n output s_axi_wready,\n // Slave Interface Write Response Ports\n input s_axi_bready,\n output [C_S_AXI_ID_WIDTH-1:0] s_axi_bid,\n output [1:0] s_axi_bresp,\n output s_axi_bvalid,\n // Slave Interface Read Address Ports\n input [C_S_AXI_ID_WIDTH-1:0] s_axi_arid,\n input [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr,\n input [7:0] s_axi_arlen,\n input [2:0] s_axi_arsize,\n input [1:0] s_axi_arburst,\n input [0:0] s_axi_arlock,\n input [3:0] s_axi_arcache,\n input [2:0] s_axi_arprot,\n input [3:0] s_axi_arqos,\n input s_axi_arvalid,\n output s_axi_arready,\n // Slave Interface Read Data Ports\n input s_axi_rready,\n output [C_S_AXI_ID_WIDTH-1:0] s_axi_rid,\n output [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata,\n output [1:0] s_axi_rresp,\n output s_axi_rlast,\n output s_axi_rvalid,\n\n \n \n \n \n output init_calib_complete,\n \n output [11:0] device_temp,\n`ifdef SKIP_CALIB\n output calib_tap_req,\n input calib_tap_load,\n input [6:0] calib_tap_addr,\n input [7:0] calib_tap_val,\n input calib_tap_load_done,\n`endif\n \n\n // System reset - Default polarity of sys_rst pin is Active Low.\n // System reset polarity will change based on the option \n // selected in GUI.\n input sys_rst\n );\n\n function integer clogb2 (input integer size);\n begin\n size = size - 1;\n for (clogb2=1; size>1; clogb2=clogb2+1)\n size = size >> 1;\n end\n endfunction // clogb2\n\n\n localparam BM_CNT_WIDTH = clogb2(nBANK_MACHS);\n localparam RANK_WIDTH = clogb2(RANKS);\n\n localparam ECC_WIDTH = (ECC == \"OFF\")?\n 0 : (DATA_WIDTH <= 4)?\n 4 : (DATA_WIDTH <= 10)?\n 5 : (DATA_WIDTH <= 26)?\n 6 : (DATA_WIDTH <= 57)?\n 7 : (DATA_WIDTH <= 120)?\n 8 : (DATA_WIDTH <= 247)?\n 9 : 10;\n localparam DATA_BUF_OFFSET_WIDTH = 1;\n localparam MC_ERR_ADDR_WIDTH = ((CS_WIDTH == 1) ? 0 : RANK_WIDTH)\n + BANK_WIDTH + ROW_WIDTH + COL_WIDTH\n + DATA_BUF_OFFSET_WIDTH;\n\n localparam APP_DATA_WIDTH = 2 * nCK_PER_CLK * PAYLOAD_WIDTH;\n localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8;\n localparam TEMP_MON_EN = (SIMULATION == \"FALSE\") ? \"ON\" : \"OFF\";\n // Enable or disable the temp monitor module\n localparam tTEMPSAMPLE = 10000000; // sample every 10 us\n localparam XADC_CLK_PERIOD = 5000; // Use 200 MHz IODELAYCTRL clock\n `ifdef SKIP_CALIB\n localparam SKIP_CALIB = \"TRUE\";\n `else\n localparam SKIP_CALIB = \"FALSE\";\n `endif\n \n\n localparam TAPSPERKCLK = (56*MMCM_MULT_F)/nCK_PER_CLK;\n \n\n // Wire declarations\n \n wire [BM_CNT_WIDTH-1:0] bank_mach_next;\n wire clk;\n wire [1:0] clk_ref;\n wire [1:0] iodelay_ctrl_rdy;\n wire clk_ref_in;\n wire sys_rst_o;\n wire clk_div2;\n wire rst_div2;\n wire freq_refclk ;\n wire mem_refclk ;\n wire pll_lock ;\n wire sync_pulse;\n wire mmcm_ps_clk;\n wire poc_sample_pd;\n wire psen;\n wire psincdec;\n wire psdone;\n wire iddr_rst;\n wire ref_dll_lock;\n wire rst_phaser_ref;\n wire pll_locked;\n\n wire rst;\n \n wire [(2*nCK_PER_CLK)-1:0] app_ecc_multiple_err;\n wire [(2*nCK_PER_CLK)-1:0] app_ecc_single_err;\n wire ddr3_parity;\n // AXI CTRL port\n wire s_axi_ctrl_awvalid;\n wire s_axi_ctrl_awready;\n wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_awaddr;\n // Slave Interface Write Data Ports\n wire s_axi_ctrl_wvalid;\n wire s_axi_ctrl_wready;\n wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_wdata;\n // Slave Interface Write Response Ports\n wire s_axi_ctrl_bvalid;\n wire s_axi_ctrl_bready;\n wire [1:0] s_axi_ctrl_bresp;\n // Slave Interface Read Address Ports\n wire s_axi_ctrl_arvalid;\n wire s_axi_ctrl_arready;\n wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_araddr;\n // Slave Interface Read Data Ports\n wire s_axi_ctrl_rvalid;\n wire s_axi_ctrl_rready;\n wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_rdata;\n wire [1:0] s_axi_ctrl_rresp;\n\n // Interrupt output\n wire interrupt;\n\n wire sys_clk_p;\n wire sys_clk_n;\n wire mmcm_clk;\n wire clk_ref_p;\n wire clk_ref_n;\n wire clk_ref_i;\n wire [11:0] device_temp_i;\n\n // Debug port signals\n wire dbg_idel_down_all;\n wire dbg_idel_down_cpt;\n wire dbg_idel_up_all;\n wire dbg_idel_up_cpt;\n wire dbg_sel_all_idel_cpt;\n wire [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt;\n wire dbg_sel_pi_incdec;\n wire [DQS_CNT_WIDTH:0] dbg_byte_sel;\n wire dbg_pi_f_inc;\n wire dbg_pi_f_dec;\n wire [5:0] dbg_pi_counter_read_val;\n wire [8:0] dbg_po_counter_read_val;\n\n wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_tap_cnt;\n wire [(5*DQS_WIDTH*RANKS)-1:0] dbg_dq_idelay_tap_cnt;\n wire [255:0] dbg_calib_top;\n wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_first_edge_cnt;\n wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_second_edge_cnt;\n wire [(6*RANKS)-1:0] dbg_rd_data_offset;\n wire [255:0] dbg_phy_rdlvl;\n wire [99:0] dbg_phy_wrcal;\n wire [(6*DQS_WIDTH)-1:0] dbg_final_po_fine_tap_cnt;\n wire [(3*DQS_WIDTH)-1:0] dbg_final_po_coarse_tap_cnt;\n wire [255:0] dbg_phy_wrlvl;\n wire [255:0] dbg_phy_init;\n wire [255:0] dbg_prbs_rdlvl;\n wire [255:0] dbg_dqs_found_cal;\n wire dbg_pi_phaselock_start;\n wire dbg_pi_phaselocked_done;\n wire dbg_pi_phaselock_err;\n wire dbg_pi_dqsfound_start;\n wire dbg_pi_dqsfound_done;\n wire dbg_pi_dqsfound_err;\n wire dbg_wrcal_start;\n wire dbg_wrcal_done;\n wire dbg_wrcal_err;\n wire [11:0] dbg_pi_dqs_found_lanes_phy4lanes;\n wire [11:0] dbg_pi_phase_locked_phy4lanes;\n wire dbg_oclkdelay_calib_start;\n wire dbg_oclkdelay_calib_done;\n wire [255:0] dbg_phy_oclkdelay_cal;\n wire [(DRAM_WIDTH*16)-1:0] dbg_oclkdelay_rd_data;\n wire [DQS_WIDTH-1:0] dbg_rd_data_edge_detect;\n wire [(2*nCK_PER_CLK*DQ_WIDTH)-1:0] dbg_rddata;\n wire dbg_rddata_valid;\n wire [1:0] dbg_rdlvl_done;\n wire [1:0] dbg_rdlvl_err;\n wire [1:0] dbg_rdlvl_start;\n wire [(6*DQS_WIDTH)-1:0] dbg_wrlvl_fine_tap_cnt;\n wire [(3*DQS_WIDTH)-1:0] dbg_wrlvl_coarse_tap_cnt;\n wire [5:0] dbg_tap_cnt_during_wrlvl;\n wire dbg_wl_edge_detect_valid;\n wire dbg_wrlvl_done;\n wire dbg_wrlvl_err;\n wire dbg_wrlvl_start;\n reg [63:0] dbg_rddata_r;\n reg dbg_rddata_valid_r;\n wire [53:0] ocal_tap_cnt;\n wire [4:0] dbg_dqs;\n wire [8:0] dbg_bit;\n wire [8:0] rd_data_edge_detect_r;\n wire [53:0] wl_po_fine_cnt;\n wire [26:0] wl_po_coarse_cnt;\n wire [(6*RANKS)-1:0] dbg_calib_rd_data_offset_1;\n wire [(6*RANKS)-1:0] dbg_calib_rd_data_offset_2;\n wire [5:0] dbg_data_offset;\n wire [5:0] dbg_data_offset_1;\n wire [5:0] dbg_data_offset_2;\n\n wire [390:0] ddr3_ila_wrpath_int;\n wire [1023:0] ddr3_ila_rdpath_int;\n wire [119:0] ddr3_ila_basic_int;\n wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_final_dqs_tap_cnt_r_int;\n wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_first_edge_taps_int;\n wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_second_edge_taps_int;\n \n\n//***************************************************************************\n\n\n\n assign ui_clk = clk;\n assign ui_clk_sync_rst = rst;\n \n assign sys_clk_p = 1'b0;\n assign sys_clk_n = 1'b0;\n assign clk_ref_i = 1'b0;\n \n\n generate\n if (REFCLK_TYPE == \"USE_SYSTEM_CLOCK\")\n assign clk_ref_in = mmcm_clk;\n else\n assign clk_ref_in = clk_ref_i;\n endgenerate\n\n mig_7series_v4_0_iodelay_ctrl #\n (\n .TCQ (TCQ),\n .IODELAY_GRP0 (IODELAY_GRP0),\n .IODELAY_GRP1 (IODELAY_GRP1),\n .REFCLK_TYPE (REFCLK_TYPE),\n .SYSCLK_TYPE (SYSCLK_TYPE),\n .SYS_RST_PORT (SYS_RST_PORT),\n .RST_ACT_LOW (RST_ACT_LOW),\n .DIFF_TERM_REFCLK (DIFF_TERM_REFCLK),\n .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),\n .REF_CLK_MMCM_IODELAY_CTRL (REF_CLK_MMCM_IODELAY_CTRL)\n )\n u_iodelay_ctrl\n (\n // Outputs\n .iodelay_ctrl_rdy (iodelay_ctrl_rdy),\n .sys_rst_o (sys_rst_o),\n .clk_ref (clk_ref),\n // Inputs\n .clk_ref_p (clk_ref_p),\n .clk_ref_n (clk_ref_n),\n .clk_ref_i (clk_ref_in),\n .sys_rst (sys_rst)\n );\n mig_7series_v4_0_clk_ibuf #\n (\n .SYSCLK_TYPE (SYSCLK_TYPE),\n .DIFF_TERM_SYSCLK (DIFF_TERM_SYSCLK)\n )\n u_ddr3_clk_ibuf\n (\n .sys_clk_p (sys_clk_p),\n .sys_clk_n (sys_clk_n),\n .sys_clk_i (sys_clk_i),\n .mmcm_clk (mmcm_clk)\n );\n // Temperature monitoring logic\n\n generate\n if (TEMP_MON_EN == \"ON\") begin: temp_mon_enabled\n\n mig_7series_v4_0_tempmon #\n (\n .TCQ (TCQ),\n .TEMP_MON_CONTROL (TEMP_MON_CONTROL),\n .XADC_CLK_PERIOD (XADC_CLK_PERIOD),\n .tTEMPSAMPLE (tTEMPSAMPLE)\n )\n u_tempmon\n (\n .clk (clk),\n .xadc_clk (clk_ref[0]),\n .rst (rst),\n .device_temp_i (device_temp_i),\n .device_temp (device_temp)\n );\n end else begin: temp_mon_disabled\n\n assign device_temp = 'b0;\n\n end\n endgenerate\n \n mig_7series_v4_0_infrastructure #\n (\n .TCQ (TCQ),\n .nCK_PER_CLK (nCK_PER_CLK),\n .CLKIN_PERIOD (CLKIN_PERIOD),\n .SYSCLK_TYPE (SYSCLK_TYPE),\n .CLKFBOUT_MULT (CLKFBOUT_MULT),\n .DIVCLK_DIVIDE (DIVCLK_DIVIDE),\n .CLKOUT0_PHASE (CLKOUT0_PHASE),\n .CLKOUT0_DIVIDE (CLKOUT0_DIVIDE),\n .CLKOUT1_DIVIDE (CLKOUT1_DIVIDE),\n .CLKOUT2_DIVIDE (CLKOUT2_DIVIDE),\n .CLKOUT3_DIVIDE (CLKOUT3_DIVIDE),\n .MMCM_VCO (MMCM_VCO),\n .MMCM_MULT_F (MMCM_MULT_F),\n .MMCM_DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE),\n .RST_ACT_LOW (RST_ACT_LOW),\n .tCK (tCK),\n .MEM_TYPE (DRAM_TYPE)\n )\n u_ddr3_infrastructure\n (\n // Outputs\n .rstdiv0 (rst),\n .clk (clk),\n .clk_div2 (clk_div2),\n .rst_div2 (rst_div2),\n .mem_refclk (mem_refclk),\n .freq_refclk (freq_refclk),\n .sync_pulse (sync_pulse),\n .mmcm_ps_clk (mmcm_ps_clk),\n .poc_sample_pd (poc_sample_pd),\n .psdone (psdone),\n .iddr_rst (iddr_rst),\n// .auxout_clk (),\n .ui_addn_clk_0 (),\n .ui_addn_clk_1 (),\n .ui_addn_clk_2 (),\n .ui_addn_clk_3 (),\n .ui_addn_clk_4 (),\n .pll_locked (pll_locked),\n .mmcm_locked (mmcm_locked),\n .rst_phaser_ref (rst_phaser_ref),\n // Inputs\n .psen (psen),\n .psincdec (psincdec),\n .mmcm_clk (mmcm_clk),\n .sys_rst (sys_rst_o),\n .iodelay_ctrl_rdy (iodelay_ctrl_rdy),\n .ref_dll_lock (ref_dll_lock)\n );\n \n\n mig_7series_v4_0_memc_ui_top_axi #\n (\n .TCQ (TCQ),\n .ADDR_CMD_MODE (ADDR_CMD_MODE),\n .AL (AL),\n .PAYLOAD_WIDTH (PAYLOAD_WIDTH),\n .BANK_WIDTH (BANK_WIDTH),\n .BM_CNT_WIDTH (BM_CNT_WIDTH),\n .BURST_MODE (BURST_MODE),\n .BURST_TYPE (BURST_TYPE),\n .CA_MIRROR (CA_MIRROR),\n .DDR3_VDD_OP_VOLT (VDD_OP_VOLT),\n .CK_WIDTH (CK_WIDTH),\n .COL_WIDTH (COL_WIDTH),\n .CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1),\n .CS_WIDTH (CS_WIDTH),\n .nCS_PER_RANK (nCS_PER_RANK),\n .CKE_WIDTH (CKE_WIDTH),\n .DATA_WIDTH (DATA_WIDTH),\n .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),\n .DM_WIDTH (DM_WIDTH),\n .DQ_CNT_WIDTH (DQ_CNT_WIDTH),\n .DQ_WIDTH (DQ_WIDTH),\n .DQS_CNT_WIDTH (DQS_CNT_WIDTH),\n .DQS_WIDTH (DQS_WIDTH),\n .DRAM_TYPE (DRAM_TYPE),\n .DRAM_WIDTH (DRAM_WIDTH),\n .ECC (ECC),\n .ECC_WIDTH (ECC_WIDTH),\n .ECC_TEST (ECC_TEST),\n .MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),\n .REFCLK_FREQ (REFCLK_FREQ),\n .nAL (nAL),\n .nBANK_MACHS (nBANK_MACHS),\n .CKE_ODT_AUX (CKE_ODT_AUX),\n .nCK_PER_CLK (nCK_PER_CLK),\n .ORDERING (ORDERING),\n .OUTPUT_DRV (OUTPUT_DRV),\n .IBUF_LPWR_MODE (IBUF_LPWR_MODE),\n .DATA_IO_IDLE_PWRDWN (DATA_IO_IDLE_PWRDWN),\n .BANK_TYPE (BANK_TYPE),\n .DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE),\n .IODELAY_GRP0 (IODELAY_GRP0),\n .IODELAY_GRP1 (IODELAY_GRP1),\n .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),\n .REG_CTRL (REG_CTRL),\n .RTT_NOM (RTT_NOM),\n .RTT_WR (RTT_WR),\n .CL (CL),\n .CWL (CWL),\n .tCK (tCK),\n .tCKE (tCKE),\n .tFAW (tFAW),\n .tPRDI (tPRDI),\n .tRAS (tRAS),\n .tRCD (tRCD),\n .tREFI (tREFI),\n .tRFC (tRFC),\n .tRP (tRP),\n .tRRD (tRRD),\n .tRTP (tRTP),\n .tWTR (tWTR),\n .tZQI (tZQI),\n .tZQCS (tZQCS),\n .USER_REFRESH (USER_REFRESH),\n .TEMP_MON_EN (TEMP_MON_EN),\n .WRLVL (WRLVL),\n .DEBUG_PORT (DEBUG_PORT),\n .CAL_WIDTH (CAL_WIDTH),\n .RANK_WIDTH (RANK_WIDTH),\n .RANKS (RANKS),\n .ODT_WIDTH (ODT_WIDTH),\n .ROW_WIDTH (ROW_WIDTH),\n .ADDR_WIDTH (ADDR_WIDTH),\n .APP_DATA_WIDTH (APP_DATA_WIDTH),\n .APP_MASK_WIDTH (APP_MASK_WIDTH),\n .SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),\n .BYTE_LANES_B0 (BYTE_LANES_B0),\n .BYTE_LANES_B1 (BYTE_LANES_B1),\n .BYTE_LANES_B2 (BYTE_LANES_B2),\n .BYTE_LANES_B3 (BYTE_LANES_B3),\n .BYTE_LANES_B4 (BYTE_LANES_B4),\n .DATA_CTL_B0 (DATA_CTL_B0),\n .DATA_CTL_B1 (DATA_CTL_B1),\n .DATA_CTL_B2 (DATA_CTL_B2),\n .DATA_CTL_B3 (DATA_CTL_B3),\n .DATA_CTL_B4 (DATA_CTL_B4),\n .PHY_0_BITLANES (PHY_0_BITLANES),\n .PHY_1_BITLANES (PHY_1_BITLANES),\n .PHY_2_BITLANES (PHY_2_BITLANES),\n .CK_BYTE_MAP (CK_BYTE_MAP),\n .ADDR_MAP (ADDR_MAP),\n .BANK_MAP (BANK_MAP),\n .CAS_MAP (CAS_MAP),\n .CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),\n .CKE_MAP (CKE_MAP),\n .ODT_MAP (ODT_MAP),\n .CS_MAP (CS_MAP),\n .PARITY_MAP (PARITY_MAP),\n .RAS_MAP (RAS_MAP),\n .WE_MAP (WE_MAP),\n .DQS_BYTE_MAP (DQS_BYTE_MAP),\n .DATA0_MAP (DATA0_MAP),\n .DATA1_MAP (DATA1_MAP),\n .DATA2_MAP (DATA2_MAP),\n .DATA3_MAP (DATA3_MAP),\n .DATA4_MAP (DATA4_MAP),\n .DATA5_MAP (DATA5_MAP),\n .DATA6_MAP (DATA6_MAP),\n .DATA7_MAP (DATA7_MAP),\n .DATA8_MAP (DATA8_MAP),\n .DATA9_MAP (DATA9_MAP),\n .DATA10_MAP (DATA10_MAP),\n .DATA11_MAP (DATA11_MAP),\n .DATA12_MAP (DATA12_MAP),\n .DATA13_MAP (DATA13_MAP),\n .DATA14_MAP (DATA14_MAP),\n .DATA15_MAP (DATA15_MAP),\n .DATA16_MAP (DATA16_MAP),\n .DATA17_MAP (DATA17_MAP),\n .MASK0_MAP (MASK0_MAP),\n .MASK1_MAP (MASK1_MAP),\n .CALIB_ROW_ADD (CALIB_ROW_ADD),\n .CALIB_COL_ADD (CALIB_COL_ADD),\n .CALIB_BA_ADD (CALIB_BA_ADD),\n .IDELAY_ADJ (IDELAY_ADJ),\n .FINE_PER_BIT (FINE_PER_BIT),\n .CENTER_COMP_MODE (CENTER_COMP_MODE),\n .PI_VAL_ADJ (PI_VAL_ADJ),\n .SLOT_0_CONFIG (SLOT_0_CONFIG),\n .SLOT_1_CONFIG (SLOT_1_CONFIG),\n .MEM_ADDR_ORDER (MEM_ADDR_ORDER),\n .STARVE_LIMIT (STARVE_LIMIT),\n .C_S_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),\n .C_S_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH),\n .C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),\n .C_S_AXI_SUPPORTS_NARROW_BURST (C_S_AXI_SUPPORTS_NARROW_BURST),\n .C_RD_WR_ARB_ALGORITHM (C_RD_WR_ARB_ALGORITHM),\n .C_S_AXI_REG_EN0 (C_S_AXI_REG_EN0),\n .C_S_AXI_REG_EN1 (C_S_AXI_REG_EN1),\n .C_S_AXI_CTRL_ADDR_WIDTH (C_S_AXI_CTRL_ADDR_WIDTH),\n .C_S_AXI_CTRL_DATA_WIDTH (C_S_AXI_CTRL_DATA_WIDTH),\n .C_S_AXI_BASEADDR (C_S_AXI_BASEADDR),\n .C_ECC_ONOFF_RESET_VALUE (C_ECC_ONOFF_RESET_VALUE),\n .C_ECC_CE_COUNTER_WIDTH (C_ECC_CE_COUNTER_WIDTH),\n .USE_CS_PORT (USE_CS_PORT),\n .USE_DM_PORT (USE_DM_PORT),\n .USE_ODT_PORT (USE_ODT_PORT),\n .MASTER_PHY_CTL (PHY_CONTROL_MASTER_BANK),\n .TAPSPERKCLK (TAPSPERKCLK),\n .SKIP_CALIB (SKIP_CALIB),\n .FPGA_VOLT_TYPE (FPGA_VOLT_TYPE)\n )\n u_memc_ui_top_axi\n (\n .clk (clk),\n .clk_div2 (clk_div2),\n .rst_div2 (rst_div2),\n .clk_ref (clk_ref),\n .mem_refclk (mem_refclk), //memory clock\n .freq_refclk (freq_refclk),\n .pll_lock (pll_locked),\n .sync_pulse (sync_pulse),\n .mmcm_ps_clk (mmcm_ps_clk),\n .poc_sample_pd (poc_sample_pd),\n .psdone (psdone),\n .iddr_rst (iddr_rst),\n .psen (psen),\n .psincdec (psincdec),\n .rst (rst),\n .rst_phaser_ref (rst_phaser_ref),\n .ref_dll_lock (ref_dll_lock),\n\n// Memory interface ports\n .ddr_dq (ddr3_dq),\n .ddr_dqs_n (ddr3_dqs_n),\n .ddr_dqs (ddr3_dqs_p),\n .ddr_addr (ddr3_addr),\n .ddr_ba (ddr3_ba),\n .ddr_cas_n (ddr3_cas_n),\n .ddr_ck_n (ddr3_ck_n),\n .ddr_ck (ddr3_ck_p),\n .ddr_cke (ddr3_cke),\n .ddr_cs_n (ddr3_cs_n),\n .ddr_dm (ddr3_dm),\n .ddr_odt (ddr3_odt),\n .ddr_ras_n (ddr3_ras_n),\n .ddr_reset_n (ddr3_reset_n),\n .ddr_parity (ddr3_parity),\n .ddr_we_n (ddr3_we_n),\n .bank_mach_next (bank_mach_next),\n\n// Application interface ports\n .app_ecc_multiple_err_o (),\n .app_ecc_single_err (),\n\n .device_temp (device_temp),\n\n // skip calibration ports\n `ifdef SKIP_CALIB\n .calib_tap_req (calib_tap_req),\n .calib_tap_load (calib_tap_load),\n .calib_tap_addr (calib_tap_addr),\n .calib_tap_val (calib_tap_val),\n .calib_tap_load_done (calib_tap_load_done),\n `else\n .calib_tap_req (),\n .calib_tap_load (1'b0),\n .calib_tap_addr (7'b0),\n .calib_tap_val (8'b0),\n .calib_tap_load_done (1'b0),\n `endif\n\n// Debug logic ports\n .dbg_idel_up_all (dbg_idel_up_all),\n .dbg_idel_down_all (dbg_idel_down_all),\n .dbg_idel_up_cpt (dbg_idel_up_cpt),\n .dbg_idel_down_cpt (dbg_idel_down_cpt),\n .dbg_sel_idel_cpt (dbg_sel_idel_cpt),\n .dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),\n .dbg_sel_pi_incdec (dbg_sel_pi_incdec),\n .dbg_sel_po_incdec (dbg_sel_po_incdec),\n .dbg_byte_sel (dbg_byte_sel),\n .dbg_pi_f_inc (dbg_pi_f_inc),\n .dbg_pi_f_dec (dbg_pi_f_dec),\n .dbg_po_f_inc (dbg_po_f_inc),\n .dbg_po_f_stg23_sel (dbg_po_f_stg23_sel),\n .dbg_po_f_dec (dbg_po_f_dec),\n .dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),\n .dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),\n .dbg_calib_top (dbg_calib_top),\n .dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),\n .dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),\n .dbg_rd_data_offset (dbg_rd_data_offset),\n .dbg_phy_rdlvl (dbg_phy_rdlvl),\n .dbg_phy_wrcal (dbg_phy_wrcal),\n .dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),\n .dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt),\n .dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),\n .dbg_rddata (dbg_rddata),\n .dbg_rddata_valid (dbg_rddata_valid),\n .dbg_rdlvl_done (dbg_rdlvl_done),\n .dbg_rdlvl_err (dbg_rdlvl_err),\n .dbg_rdlvl_start (dbg_rdlvl_start),\n .dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),\n .dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),\n .dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),\n .dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),\n .dbg_wrlvl_done (dbg_wrlvl_done),\n .dbg_wrlvl_err (dbg_wrlvl_err),\n .dbg_wrlvl_start (dbg_wrlvl_start),\n .dbg_phy_wrlvl (dbg_phy_wrlvl),\n .dbg_phy_init (dbg_phy_init),\n .dbg_prbs_rdlvl (dbg_prbs_rdlvl),\n .dbg_pi_counter_read_val (dbg_pi_counter_read_val),\n .dbg_po_counter_read_val (dbg_po_counter_read_val),\n .dbg_prbs_final_dqs_tap_cnt_r (dbg_prbs_final_dqs_tap_cnt_r_int),\n .dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps_int),\n .dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps_int),\n .dbg_pi_phaselock_start (dbg_pi_phaselock_start),\n .dbg_pi_phaselocked_done (dbg_pi_phaselocked_done),\n .dbg_pi_phaselock_err (dbg_pi_phaselock_err),\n .dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes),\n .dbg_pi_dqsfound_start (dbg_pi_dqsfound_start),\n .dbg_pi_dqsfound_done (dbg_pi_dqsfound_done),\n .dbg_pi_dqsfound_err (dbg_pi_dqsfound_err),\n .dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes),\n .dbg_calib_rd_data_offset_1 (dbg_calib_rd_data_offset_1),\n .dbg_calib_rd_data_offset_2 (dbg_calib_rd_data_offset_2),\n .dbg_data_offset (dbg_data_offset),\n .dbg_data_offset_1 (dbg_data_offset_1),\n .dbg_data_offset_2 (dbg_data_offset_2),\n .dbg_wrcal_start (dbg_wrcal_start),\n .dbg_wrcal_done (dbg_wrcal_done),\n .dbg_wrcal_err (dbg_wrcal_err),\n .dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal),\n .dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data),\n .dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start),\n .dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done),\n .dbg_dqs_found_cal (dbg_dqs_found_cal), \n .aresetn (aresetn),\n .app_sr_req (app_sr_req),\n .app_sr_active (app_sr_active),\n .app_ref_req (app_ref_req),\n .app_ref_ack (app_ref_ack),\n .app_zq_req (app_zq_req),\n .app_zq_ack (app_zq_ack),\n\n // Slave Interface Write Address Ports\n .s_axi_awid (s_axi_awid),\n .s_axi_awaddr (s_axi_awaddr),\n .s_axi_awlen (s_axi_awlen),\n .s_axi_awsize (s_axi_awsize),\n .s_axi_awburst (s_axi_awburst),\n .s_axi_awlock (s_axi_awlock),\n .s_axi_awcache (s_axi_awcache),\n .s_axi_awprot (s_axi_awprot),\n .s_axi_awqos (s_axi_awqos),\n .s_axi_awvalid (s_axi_awvalid),\n .s_axi_awready (s_axi_awready),\n // Slave Interface Write Data Ports\n .s_axi_wdata (s_axi_wdata),\n .s_axi_wstrb (s_axi_wstrb),\n .s_axi_wlast (s_axi_wlast),\n .s_axi_wvalid (s_axi_wvalid),\n .s_axi_wready (s_axi_wready),\n // Slave Interface Write Response Ports\n .s_axi_bid (s_axi_bid),\n .s_axi_bresp (s_axi_bresp),\n .s_axi_bvalid (s_axi_bvalid),\n .s_axi_bready (s_axi_bready),\n // Slave Interface Read Address Ports\n .s_axi_arid (s_axi_arid),\n .s_axi_araddr (s_axi_araddr),\n .s_axi_arlen (s_axi_arlen),\n .s_axi_arsize (s_axi_arsize),\n .s_axi_arburst (s_axi_arburst),\n .s_axi_arlock (s_axi_arlock),\n .s_axi_arcache (s_axi_arcache),\n .s_axi_arprot (s_axi_arprot),\n .s_axi_arqos (s_axi_arqos),\n .s_axi_arvalid (s_axi_arvalid),\n .s_axi_arready (s_axi_arready),\n // Slave Interface Read Data Ports\n .s_axi_rid (s_axi_rid),\n .s_axi_rdata (s_axi_rdata),\n .s_axi_rresp (s_axi_rresp),\n .s_axi_rlast (s_axi_rlast),\n .s_axi_rvalid (s_axi_rvalid),\n .s_axi_rready (s_axi_rready),\n // AXI CTRL port\n .s_axi_ctrl_awvalid (s_axi_ctrl_awvalid),\n .s_axi_ctrl_awready (s_axi_ctrl_awready),\n .s_axi_ctrl_awaddr (s_axi_ctrl_awaddr),\n // Slave Interface Write Data Ports\n .s_axi_ctrl_wvalid (s_axi_ctrl_wvalid),\n .s_axi_ctrl_wready (s_axi_ctrl_wready),\n .s_axi_ctrl_wdata (s_axi_ctrl_wdata),\n // Slave Interface Write Response Ports\n .s_axi_ctrl_bvalid (s_axi_ctrl_bvalid),\n .s_axi_ctrl_bready (s_axi_ctrl_bready),\n .s_axi_ctrl_bresp (s_axi_ctrl_bresp),\n // Slave Interface Read Address Ports\n .s_axi_ctrl_arvalid (s_axi_ctrl_arvalid),\n .s_axi_ctrl_arready (s_axi_ctrl_arready),\n .s_axi_ctrl_araddr (s_axi_ctrl_araddr),\n // Slave Interface Read Data Ports\n .s_axi_ctrl_rvalid (s_axi_ctrl_rvalid),\n .s_axi_ctrl_rready (s_axi_ctrl_rready),\n .s_axi_ctrl_rdata (s_axi_ctrl_rdata),\n .s_axi_ctrl_rresp (s_axi_ctrl_rresp),\n // Interrupt output\n .interrupt (interrupt),\n .init_calib_complete (init_calib_complete),\n .dbg_poc ()\n );\n\n \n\n\n\n\n //*********************************************************************\n // Resetting all RTL debug inputs as the debug ports are not enabled\n //*********************************************************************\n assign dbg_idel_down_all = 1'b0;\n assign dbg_idel_down_cpt = 1'b0;\n assign dbg_idel_up_all = 1'b0;\n assign dbg_idel_up_cpt = 1'b0;\n assign dbg_sel_all_idel_cpt = 1'b0;\n assign dbg_sel_idel_cpt = 'b0;\n assign dbg_byte_sel = 'd0;\n assign dbg_sel_pi_incdec = 1'b0;\n assign dbg_pi_f_inc = 1'b0;\n assign dbg_pi_f_dec = 1'b0;\n assign dbg_po_f_inc = 'b0;\n assign dbg_po_f_dec = 'b0;\n assign dbg_po_f_stg23_sel = 'b0;\n assign dbg_sel_po_incdec = 'b0;\n\n \n\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ddr3_if_mig_sim.v", "content": "//*****************************************************************************\n// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor : Xilinx\n// \\ \\ \\/ Version : 4.0\n// \\ \\ Application : MIG\n// / / Filename : ddr3_if_mig.v\n// /___/ /\\ Date Last Modified : $Date: 2011/06/02 08:35:03 $\n// \\ \\ / \\ Date Created : Tue Sept 21 2010\n// \\___\\/\\___\\\n//\n// Device : 7 Series\n// Design Name : DDR3 SDRAM\n// Purpose :\n// Top-level module. This module can be instantiated in the\n// system and interconnect as shown in user design wrapper file (user top module).\n// In addition to the memory controller, the module instantiates:\n// 1. Clock generation/distribution, reset logic\n// 2. IDELAY control block\n// 3. Debug logic\n// Reference :\n// Revision History :\n//*****************************************************************************\n\n//`define SKIP_CALIB\n`timescale 1ps/1ps\n\nmodule ddr3_if_mig #\n (\n\n //***************************************************************************\n // The following parameters refer to width of various ports\n //***************************************************************************\n parameter BANK_WIDTH = 3,\n // # of memory Bank Address bits.\n parameter CK_WIDTH = 1,\n // # of CK/CK# outputs to memory.\n parameter COL_WIDTH = 10,\n // # of memory Column Address bits.\n parameter CS_WIDTH = 1,\n // # of unique CS outputs to memory.\n parameter nCS_PER_RANK = 1,\n // # of unique CS outputs per rank for phy\n parameter CKE_WIDTH = 1,\n // # of CKE outputs to memory.\n parameter DATA_BUF_ADDR_WIDTH = 5,\n parameter DQ_CNT_WIDTH = 5,\n // = ceil(log2(DQ_WIDTH))\n parameter DQ_PER_DM = 8,\n parameter DM_WIDTH = 4,\n // # of DM (data mask)\n parameter DQ_WIDTH = 32,\n // # of DQ (data)\n parameter DQS_WIDTH = 4,\n parameter DQS_CNT_WIDTH = 2,\n // = ceil(log2(DQS_WIDTH))\n parameter DRAM_WIDTH = 8,\n // # of DQ per DQS\n parameter ECC = \"OFF\",\n parameter DATA_WIDTH = 32,\n parameter ECC_TEST = \"OFF\",\n parameter PAYLOAD_WIDTH = (ECC_TEST == \"OFF\") ? DATA_WIDTH : DQ_WIDTH,\n parameter MEM_ADDR_ORDER = \"ROW_BANK_COLUMN\",\n //Possible Parameters\n //1.BANK_ROW_COLUMN : Address mapping is\n // in form of Bank Row Column.\n //2.ROW_BANK_COLUMN : Address mapping is\n // in the form of Row Bank Column.\n //3.TG_TEST : Scrambles Address bits\n // for distributed Addressing.\n \n //parameter nBANK_MACHS = 4,\n parameter nBANK_MACHS = 4,\n parameter RANKS = 1,\n // # of Ranks.\n parameter ODT_WIDTH = 1,\n // # of ODT outputs to memory.\n parameter ROW_WIDTH = 15,\n // # of memory Row Address bits.\n parameter ADDR_WIDTH = 29,\n // # = RANK_WIDTH + BANK_WIDTH\n // + ROW_WIDTH + COL_WIDTH;\n // Chip Select is always tied to low for\n // single rank devices\n parameter USE_CS_PORT = 1,\n // # = 1, When Chip Select (CS#) output is enabled\n // = 0, When Chip Select (CS#) output is disabled\n // If CS_N disabled, user must connect\n // DRAM CS_N input(s) to ground\n parameter USE_DM_PORT = 1,\n // # = 1, When Data Mask option is enabled\n // = 0, When Data Mask option is disbaled\n // When Data Mask option is disabled in\n // MIG Controller Options page, the logic\n // related to Data Mask should not get\n // synthesized\n parameter USE_ODT_PORT = 1,\n // # = 1, When ODT output is enabled\n // = 0, When ODT output is disabled\n // Parameter configuration for Dynamic ODT support:\n // USE_ODT_PORT = 0, RTT_NOM = \"DISABLED\", RTT_WR = \"60/120\".\n // This configuration allows to save ODT pin mapping from FPGA.\n // The user can tie the ODT input of DRAM to HIGH.\n parameter IS_CLK_SHARED = \"FALSE\",\n // # = \"true\" when clock is shared\n // = \"false\" when clock is not shared\n\n parameter PHY_CONTROL_MASTER_BANK = 1,\n // The bank index where master PHY_CONTROL resides,\n // equal to the PLL residing bank\n parameter MEM_DENSITY = \"4Gb\",\n // Indicates the density of the Memory part\n // Added for the sake of Vivado simulations\n parameter MEM_SPEEDGRADE = \"107E\",\n // Indicates the Speed grade of Memory Part\n // Added for the sake of Vivado simulations\n parameter MEM_DEVICE_WIDTH = 16,\n // Indicates the device width of the Memory Part\n // Added for the sake of Vivado simulations\n\n //***************************************************************************\n // The following parameters are mode register settings\n //***************************************************************************\n parameter AL = \"0\",\n // DDR3 SDRAM:\n // Additive Latency (Mode Register 1).\n // # = \"0\", \"CL-1\", \"CL-2\".\n // DDR2 SDRAM:\n // Additive Latency (Extended Mode Register).\n parameter nAL = 0,\n // # Additive Latency in number of clock\n // cycles.\n parameter BURST_MODE = \"8\",\n // DDR3 SDRAM:\n // Burst Length (Mode Register 0).\n // # = \"8\", \"4\", \"OTF\".\n // DDR2 SDRAM:\n // Burst Length (Mode Register).\n // # = \"8\", \"4\".\n parameter BURST_TYPE = \"SEQ\",\n // DDR3 SDRAM: Burst Type (Mode Register 0).\n // DDR2 SDRAM: Burst Type (Mode Register).\n // # = \"SEQ\" - (Sequential),\n // = \"INT\" - (Interleaved).\n parameter CL = 13,\n // in number of clock cycles\n // DDR3 SDRAM: CAS Latency (Mode Register 0).\n // DDR2 SDRAM: CAS Latency (Mode Register).\n parameter CWL = 9,\n // in number of clock cycles\n // DDR3 SDRAM: CAS Write Latency (Mode Register 2).\n // DDR2 SDRAM: Can be ignored\n parameter OUTPUT_DRV = \"HIGH\",\n // Output Driver Impedance Control (Mode Register 1).\n // # = \"HIGH\" - RZQ/7,\n // = \"LOW\" - RZQ/6.\n parameter RTT_NOM = \"40\",\n // RTT_NOM (ODT) (Mode Register 1).\n // = \"120\" - RZQ/2,\n // = \"60\" - RZQ/4,\n // = \"40\" - RZQ/6.\n parameter RTT_WR = \"OFF\",\n // RTT_WR (ODT) (Mode Register 2).\n // # = \"OFF\" - Dynamic ODT off,\n // = \"120\" - RZQ/2,\n // = \"60\" - RZQ/4,\n parameter ADDR_CMD_MODE = \"1T\" ,\n // # = \"1T\", \"2T\".\n parameter REG_CTRL = \"OFF\",\n // # = \"ON\" - RDIMMs,\n // = \"OFF\" - Components, SODIMMs, UDIMMs.\n parameter CA_MIRROR = \"OFF\",\n // C/A mirror opt for DDR3 dual rank\n\n parameter VDD_OP_VOLT = \"150\",\n // # = \"150\" - 1.5V Vdd Memory part\n // = \"135\" - 1.35V Vdd Memory part\n\n \n //***************************************************************************\n // The following parameters are multiplier and divisor factors for PLLE2.\n // Based on the selected design frequency these parameters vary.\n //***************************************************************************\n parameter CLKIN_PERIOD = 5004,\n // Input Clock Period\n parameter CLKFBOUT_MULT = 9,\n // write PLL VCO multiplier\n parameter DIVCLK_DIVIDE = 1,\n // write PLL VCO divisor\n parameter CLKOUT0_PHASE = 337.5,\n // Phase for PLL output clock (CLKOUT0)\n parameter CLKOUT0_DIVIDE = 2,\n // VCO output divisor for PLL output clock (CLKOUT0)\n parameter CLKOUT1_DIVIDE = 2,\n // VCO output divisor for PLL output clock (CLKOUT1)\n parameter CLKOUT2_DIVIDE = 32,\n // VCO output divisor for PLL output clock (CLKOUT2)\n parameter CLKOUT3_DIVIDE = 8,\n // VCO output divisor for PLL output clock (CLKOUT3)\n parameter MMCM_VCO = 899,\n // Max Freq (MHz) of MMCM VCO\n parameter MMCM_MULT_F = 4,\n // write MMCM VCO multiplier\n parameter MMCM_DIVCLK_DIVIDE = 1,\n // write MMCM VCO divisor\n\n //***************************************************************************\n // Memory Timing Parameters. These parameters varies based on the selected\n // memory part.\n //***************************************************************************\n parameter tCKE = 5000,\n // memory tCKE paramter in pS\n parameter tFAW = 35000,\n // memory tRAW paramter in pS.\n parameter tPRDI = 1_000_000,\n // memory tPRDI paramter in pS.\n parameter tRAS = 34000,\n // memory tRAS paramter in pS.\n parameter tRCD = 13910,\n // memory tRCD paramter in pS.\n parameter tREFI = 7800000,\n // memory tREFI paramter in pS.\n parameter tRFC = 260000,\n // memory tRFC paramter in pS.\n parameter tRP = 13910,\n // memory tRP paramter in pS.\n parameter tRRD = 6000,\n // memory tRRD paramter in pS.\n parameter tRTP = 7500,\n // memory tRTP paramter in pS.\n parameter tWTR = 7500,\n // memory tWTR paramter in pS.\n parameter tZQI = 128_000_000,\n // memory tZQI paramter in nS.\n parameter tZQCS = 72,//64,\n // memory tZQCS paramter in clock cycles.\n\n //***************************************************************************\n // Simulation parameters\n //***************************************************************************\n parameter SIM_BYPASS_INIT_CAL = \"FAST\",\n // # = \"OFF\" - Complete memory init &\n // calibration sequence\n // # = \"SKIP\" - Not supported\n // # = \"FAST\" - Complete memory init & use\n // abbreviated calib sequence\n\n parameter SIMULATION = \"TRUE\",\n // Should be TRUE during design simulations and\n // FALSE during implementations\n\n //***************************************************************************\n // The following parameters varies based on the pin out entered in MIG GUI.\n // Do not change any of these parameters directly by editing the RTL.\n // Any changes required should be done through GUI and the design regenerated.\n //***************************************************************************\n parameter BYTE_LANES_B0 = 4'b1111,\n // Byte lanes used in an IO column.\n parameter BYTE_LANES_B1 = 4'b1111,\n // Byte lanes used in an IO column.\n parameter BYTE_LANES_B2 = 4'b0000,\n // Byte lanes used in an IO column.\n parameter BYTE_LANES_B3 = 4'b0000,\n // Byte lanes used in an IO column.\n parameter BYTE_LANES_B4 = 4'b0000,\n // Byte lanes used in an IO column.\n parameter DATA_CTL_B0 = 4'b1111,\n // Indicates Byte lane is data byte lane\n // or control Byte lane. '1' in a bit\n // position indicates a data byte lane and\n // a '0' indicates a control byte lane\n parameter DATA_CTL_B1 = 4'b0000,\n // Indicates Byte lane is data byte lane\n // or control Byte lane. '1' in a bit\n // position indicates a data byte lane and\n // a '0' indicates a control byte lane\n parameter DATA_CTL_B2 = 4'b0000,\n // Indicates Byte lane is data byte lane\n // or control Byte lane. '1' in a bit\n // position indicates a data byte lane and\n // a '0' indicates a control byte lane\n parameter DATA_CTL_B3 = 4'b0000,\n // Indicates Byte lane is data byte lane\n // or control Byte lane. '1' in a bit\n // position indicates a data byte lane and\n // a '0' indicates a control byte lane\n parameter DATA_CTL_B4 = 4'b0000,\n // Indicates Byte lane is data byte lane\n // or control Byte lane. '1' in a bit\n // position indicates a data byte lane and\n // a '0' indicates a control byte lane\n parameter PHY_0_BITLANES = 48'h3FE_3FE_3FE_2FF,\n parameter PHY_1_BITLANES = 48'h3FE_FFC_C10_003,\n parameter PHY_2_BITLANES = 48'h000_000_000_000,\n\n // control/address/data pin mapping parameters\n parameter CK_BYTE_MAP\n = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_13,\n parameter ADDR_MAP\n = 192'h000_114_139_138_137_136_135_134_133_132_131_125_128_127_126_12B,\n parameter BANK_MAP = 36'h12A_129_124,\n parameter CAS_MAP = 12'h122,\n parameter CKE_ODT_BYTE_MAP = 8'h00,\n parameter CKE_MAP = 96'h000_000_000_000_000_000_000_11B,\n parameter ODT_MAP = 96'h000_000_000_000_000_000_000_11A,\n parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_100,\n parameter PARITY_MAP = 12'h000,\n parameter RAS_MAP = 12'h123,\n parameter WE_MAP = 12'h101,\n parameter DQS_BYTE_MAP\n = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_01_02_03,\n parameter DATA0_MAP = 96'h031_032_033_034_035_036_037_038,\n parameter DATA1_MAP = 96'h021_022_023_024_025_026_027_028,\n parameter DATA2_MAP = 96'h011_012_013_014_015_016_017_018,\n parameter DATA3_MAP = 96'h000_001_002_003_004_005_006_007,\n parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter MASK0_MAP = 108'h000_000_000_000_000_009_019_029_039,\n parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,\n\n parameter SLOT_0_CONFIG = 8'b0000_0001,\n // Mapping of Ranks.\n parameter SLOT_1_CONFIG = 8'b0000_0000,\n // Mapping of Ranks.\n\n //***************************************************************************\n // IODELAY and PHY related parameters\n //***************************************************************************\n parameter IBUF_LPWR_MODE = \"OFF\",\n // to phy_top\n parameter DATA_IO_IDLE_PWRDWN = \"ON\",\n // # = \"ON\", \"OFF\"\n parameter BANK_TYPE = \"HP_IO\",\n // # = \"HP_IO\", \"HPL_IO\", \"HR_IO\", \"HRL_IO\"\n parameter DATA_IO_PRIM_TYPE = \"HP_LP\",\n // # = \"HP_LP\", \"HR_LP\", \"DEFAULT\"\n parameter CKE_ODT_AUX = \"FALSE\",\n parameter USER_REFRESH = \"OFF\",\n parameter WRLVL = \"ON\",\n // # = \"ON\" - DDR3 SDRAM\n // = \"OFF\" - DDR2 SDRAM.\n parameter ORDERING = \"NORM\",\n // # = \"NORM\", \"STRICT\", \"RELAXED\".\n parameter CALIB_ROW_ADD = 16'h0000,\n // Calibration row address will be used for\n // calibration read and write operations\n parameter CALIB_COL_ADD = 12'h000,\n // Calibration column address will be used for\n // calibration read and write operations\n parameter CALIB_BA_ADD = 3'h0,\n // Calibration bank address will be used for\n // calibration read and write operations\n parameter TCQ = 100,\n parameter IDELAY_ADJ = \"ON\",\n parameter FINE_PER_BIT = \"ON\",\n parameter CENTER_COMP_MODE = \"ON\",\n parameter PI_VAL_ADJ = \"ON\",\n parameter IODELAY_GRP0 = \"DDR3_IF_IODELAY_MIG0\",\n // It is associated to a set of IODELAYs with\n // an IDELAYCTRL that have same IODELAY CONTROLLER\n // clock frequency (200MHz).\n parameter IODELAY_GRP1 = \"DDR3_IF_IODELAY_MIG1\",\n // It is associated to a set of IODELAYs with\n // an IDELAYCTRL that have same IODELAY CONTROLLER\n // clock frequency (300MHz/400MHz).\n parameter SYSCLK_TYPE = \"NO_BUFFER\",\n // System clock type DIFFERENTIAL, SINGLE_ENDED,\n // NO_BUFFER\n parameter REFCLK_TYPE = \"USE_SYSTEM_CLOCK\",\n // Reference clock type DIFFERENTIAL, SINGLE_ENDED,\n // NO_BUFFER, USE_SYSTEM_CLOCK\n parameter SYS_RST_PORT = \"FALSE\",\n // \"TRUE\" - if pin is selected for sys_rst\n // and IBUF will be instantiated.\n // \"FALSE\" - if pin is not selected for sys_rst\n parameter FPGA_SPEED_GRADE = 2,\n // FPGA speed grade\n \n parameter CMD_PIPE_PLUS1 = \"ON\",\n // add pipeline stage between MC and PHY\n parameter DRAM_TYPE = \"DDR3\",\n parameter CAL_WIDTH = \"HALF\",\n parameter STARVE_LIMIT = 2,\n // # = 2,3,4.\n parameter REF_CLK_MMCM_IODELAY_CTRL = \"TRUE\",\n \n\n //***************************************************************************\n // Referece clock frequency parameters\n //***************************************************************************\n parameter REFCLK_FREQ = 200.0,\n // IODELAYCTRL reference clock frequency\n parameter DIFF_TERM_REFCLK = \"TRUE\",\n // Differential Termination for idelay\n // reference clock input pins\n //***************************************************************************\n // System clock frequency parameters\n //***************************************************************************\n parameter tCK = 1112,\n // memory tCK paramter.\n // # = Clock Period in pS.\n parameter nCK_PER_CLK = 4,\n // # of memory CKs per fabric CLK\n \n parameter DIFF_TERM_SYSCLK = \"TRUE\",\n // Differential Termination for System\n // clock input pins\n \n\n \n //***************************************************************************\n // AXI4 Shim parameters\n //***************************************************************************\n \n parameter UI_EXTRA_CLOCKS = \"FALSE\",\n // Generates extra clocks as\n // 1/2, 1/4 and 1/8 of fabrick clock.\n // Valid for DDR2/DDR3 AXI interfaces\n // based on GUI selection\n parameter C_S_AXI_ID_WIDTH = 1,\n // Width of all master and slave ID signals.\n // # = >= 1.\n parameter C_S_AXI_MEM_SIZE = \"1073741824\",\n // Address Space required for this component\n parameter C_S_AXI_ADDR_WIDTH = 30,\n // Width of S_AXI_AWADDR, S_AXI_ARADDR, M_AXI_AWADDR and\n // M_AXI_ARADDR for all SI/MI slots.\n // # = 32.\n parameter C_S_AXI_DATA_WIDTH = 256,\n // Width of WDATA and RDATA on SI slot.\n // Must be <= APP_DATA_WIDTH.\n // # = 32, 64, 128, 256.\n parameter C_MC_nCK_PER_CLK = 4,\n // Indicates whether to instatiate upsizer\n // Range: 0, 1\n parameter C_S_AXI_SUPPORTS_NARROW_BURST = 0,\n // Indicates whether to instatiate upsizer\n // Range: 0, 1\n parameter C_RD_WR_ARB_ALGORITHM = \"RD_PRI_REG_STARVE_LIMIT\",\n // Indicates the Arbitration\n // Allowed values - \"TDM\", \"ROUND_ROBIN\",\n // \"RD_PRI_REG\", \"RD_PRI_REG_STARVE_LIMIT\"\n // \"WRITE_PRIORITY\", \"WRITE_PRIORITY_REG\"\n parameter C_S_AXI_REG_EN0 = 20'h00000,\n // C_S_AXI_REG_EN0[00] = Reserved\n // C_S_AXI_REG_EN0[04] = AW CHANNEL REGISTER SLICE\n // C_S_AXI_REG_EN0[05] = W CHANNEL REGISTER SLICE\n // C_S_AXI_REG_EN0[06] = B CHANNEL REGISTER SLICE\n // C_S_AXI_REG_EN0[07] = R CHANNEL REGISTER SLICE\n // C_S_AXI_REG_EN0[08] = AW CHANNEL UPSIZER REGISTER SLICE\n // C_S_AXI_REG_EN0[09] = W CHANNEL UPSIZER REGISTER SLICE\n // C_S_AXI_REG_EN0[10] = AR CHANNEL UPSIZER REGISTER SLICE\n // C_S_AXI_REG_EN0[11] = R CHANNEL UPSIZER REGISTER SLICE\n parameter C_S_AXI_REG_EN1 = 20'h00000,\n // Instatiates register slices after the upsizer.\n // The type of register is specified for each channel\n // in a vector. 4 bits per channel are used.\n // C_S_AXI_REG_EN1[03:00] = AW CHANNEL REGISTER SLICE\n // C_S_AXI_REG_EN1[07:04] = W CHANNEL REGISTER SLICE\n // C_S_AXI_REG_EN1[11:08] = B CHANNEL REGISTER SLICE\n // C_S_AXI_REG_EN1[15:12] = AR CHANNEL REGISTER SLICE\n // C_S_AXI_REG_EN1[20:16] = R CHANNEL REGISTER SLICE\n // Possible values for each channel are:\n //\n // 0 => BYPASS = The channel is just wired through the\n // module.\n // 1 => FWD = The master VALID and payload signals\n // are registrated.\n // 2 => REV = The slave ready signal is registrated\n // 3 => FWD_REV = Both FWD and REV\n // 4 => SLAVE_FWD = All slave side signals and master\n // VALID and payload are registrated.\n // 5 => SLAVE_RDY = All slave side signals and master\n // READY are registrated.\n // 6 => INPUTS = Slave and Master side inputs are\n // registrated.\n // 7 => ADDRESS = Optimized for address channel\n parameter C_S_AXI_CTRL_ADDR_WIDTH = 32,\n // Width of AXI-4-Lite address bus\n parameter C_S_AXI_CTRL_DATA_WIDTH = 32,\n // Width of AXI-4-Lite data buses\n parameter C_S_AXI_BASEADDR = 32'h0000_0000,\n // Base address of AXI4 Memory Mapped bus.\n parameter C_ECC_ONOFF_RESET_VALUE = 1,\n // Controls ECC on/off value at startup/reset\n parameter C_ECC_CE_COUNTER_WIDTH = 8,\n // The external memory to controller clock ratio.\n\n //***************************************************************************\n // Debug parameters\n //***************************************************************************\n parameter DEBUG_PORT = \"OFF\",\n // # = \"ON\" Enable debug signals/controls.\n // = \"OFF\" Disable debug signals/controls.\n\n //***************************************************************************\n // Temparature monitor parameter\n //***************************************************************************\n parameter TEMP_MON_CONTROL = \"INTERNAL\",\n // # = \"INTERNAL\", \"EXTERNAL\"\n //***************************************************************************\n // FPGA Voltage Type parameter\n //***************************************************************************\n parameter FPGA_VOLT_TYPE = \"N\",\n // # = \"L\", \"N\". When FPGA VccINT is 0.9v,\n // the value is \"L\", else it is \"N\"\n \n parameter RST_ACT_LOW = 1\n // =1 for active low reset,\n // =0 for active high.\n )\n (\n\n // Inouts\n inout [DQ_WIDTH-1:0] ddr3_dq,\n inout [DQS_WIDTH-1:0] ddr3_dqs_n,\n inout [DQS_WIDTH-1:0] ddr3_dqs_p,\n\n // Outputs\n output [ROW_WIDTH-1:0] ddr3_addr,\n output [BANK_WIDTH-1:0] ddr3_ba,\n output ddr3_ras_n,\n output ddr3_cas_n,\n output ddr3_we_n,\n output ddr3_reset_n,\n output [CK_WIDTH-1:0] ddr3_ck_p,\n output [CK_WIDTH-1:0] ddr3_ck_n,\n output [CKE_WIDTH-1:0] ddr3_cke,\n \n output [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_cs_n,\n \n output [DM_WIDTH-1:0] ddr3_dm,\n \n output [ODT_WIDTH-1:0] ddr3_odt,\n \n\n // Inputs\n \n // Single-ended system clock\n input sys_clk_i,\n \n \n // user interface signals\n output ui_clk,\n output ui_clk_sync_rst,\n \n output mmcm_locked,\n \n input aresetn,\n input app_sr_req,\n input app_ref_req,\n input app_zq_req,\n output app_sr_active,\n output app_ref_ack,\n output app_zq_ack,\n\n // Slave Interface Write Address Ports\n input [C_S_AXI_ID_WIDTH-1:0] s_axi_awid,\n input [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,\n input [7:0] s_axi_awlen,\n input [2:0] s_axi_awsize,\n input [1:0] s_axi_awburst,\n input [0:0] s_axi_awlock,\n input [3:0] s_axi_awcache,\n input [2:0] s_axi_awprot,\n input [3:0] s_axi_awqos,\n input s_axi_awvalid,\n output s_axi_awready,\n // Slave Interface Write Data Ports\n input [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata,\n input [(C_S_AXI_DATA_WIDTH/8)-1:0] s_axi_wstrb,\n input s_axi_wlast,\n input s_axi_wvalid,\n output s_axi_wready,\n // Slave Interface Write Response Ports\n input s_axi_bready,\n output [C_S_AXI_ID_WIDTH-1:0] s_axi_bid,\n output [1:0] s_axi_bresp,\n output s_axi_bvalid,\n // Slave Interface Read Address Ports\n input [C_S_AXI_ID_WIDTH-1:0] s_axi_arid,\n input [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr,\n input [7:0] s_axi_arlen,\n input [2:0] s_axi_arsize,\n input [1:0] s_axi_arburst,\n input [0:0] s_axi_arlock,\n input [3:0] s_axi_arcache,\n input [2:0] s_axi_arprot,\n input [3:0] s_axi_arqos,\n input s_axi_arvalid,\n output s_axi_arready,\n // Slave Interface Read Data Ports\n input s_axi_rready,\n output [C_S_AXI_ID_WIDTH-1:0] s_axi_rid,\n output [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata,\n output [1:0] s_axi_rresp,\n output s_axi_rlast,\n output s_axi_rvalid,\n\n \n \n \n \n output init_calib_complete,\n \n output [11:0] device_temp,\n`ifdef SKIP_CALIB\n output calib_tap_req,\n input calib_tap_load,\n input [6:0] calib_tap_addr,\n input [7:0] calib_tap_val,\n input calib_tap_load_done,\n`endif\n \n\n // System reset - Default polarity of sys_rst pin is Active Low.\n // System reset polarity will change based on the option \n // selected in GUI.\n input sys_rst\n );\n\n function integer clogb2 (input integer size);\n begin\n size = size - 1;\n for (clogb2=1; size>1; clogb2=clogb2+1)\n size = size >> 1;\n end\n endfunction // clogb2\n\n\n localparam BM_CNT_WIDTH = clogb2(nBANK_MACHS);\n localparam RANK_WIDTH = clogb2(RANKS);\n\n localparam ECC_WIDTH = (ECC == \"OFF\")?\n 0 : (DATA_WIDTH <= 4)?\n 4 : (DATA_WIDTH <= 10)?\n 5 : (DATA_WIDTH <= 26)?\n 6 : (DATA_WIDTH <= 57)?\n 7 : (DATA_WIDTH <= 120)?\n 8 : (DATA_WIDTH <= 247)?\n 9 : 10;\n localparam DATA_BUF_OFFSET_WIDTH = 1;\n localparam MC_ERR_ADDR_WIDTH = ((CS_WIDTH == 1) ? 0 : RANK_WIDTH)\n + BANK_WIDTH + ROW_WIDTH + COL_WIDTH\n + DATA_BUF_OFFSET_WIDTH;\n\n localparam APP_DATA_WIDTH = 2 * nCK_PER_CLK * PAYLOAD_WIDTH;\n localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8;\n localparam TEMP_MON_EN = (SIMULATION == \"TRUE\") ? \"ON\" : \"OFF\";\n // Enable or disable the temp monitor module\n localparam tTEMPSAMPLE = 10000000; // sample every 10 us\n localparam XADC_CLK_PERIOD = 5000; // Use 200 MHz IODELAYCTRL clock\n `ifdef SKIP_CALIB\n localparam SKIP_CALIB = \"TRUE\";\n `else\n localparam SKIP_CALIB = \"FALSE\";\n `endif\n \n\n localparam TAPSPERKCLK = (56*MMCM_MULT_F)/nCK_PER_CLK;\n \n\n // Wire declarations\n \n wire [BM_CNT_WIDTH-1:0] bank_mach_next;\n wire clk;\n wire [1:0] clk_ref;\n wire [1:0] iodelay_ctrl_rdy;\n wire clk_ref_in;\n wire sys_rst_o;\n wire clk_div2;\n wire rst_div2;\n wire freq_refclk ;\n wire mem_refclk ;\n wire pll_lock ;\n wire sync_pulse;\n wire mmcm_ps_clk;\n wire poc_sample_pd;\n wire psen;\n wire psincdec;\n wire psdone;\n wire iddr_rst;\n wire ref_dll_lock;\n wire rst_phaser_ref;\n wire pll_locked;\n\n wire rst;\n \n wire [(2*nCK_PER_CLK)-1:0] app_ecc_multiple_err;\n wire [(2*nCK_PER_CLK)-1:0] app_ecc_single_err;\n wire ddr3_parity;\n // AXI CTRL port\n wire s_axi_ctrl_awvalid;\n wire s_axi_ctrl_awready;\n wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_awaddr;\n // Slave Interface Write Data Ports\n wire s_axi_ctrl_wvalid;\n wire s_axi_ctrl_wready;\n wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_wdata;\n // Slave Interface Write Response Ports\n wire s_axi_ctrl_bvalid;\n wire s_axi_ctrl_bready;\n wire [1:0] s_axi_ctrl_bresp;\n // Slave Interface Read Address Ports\n wire s_axi_ctrl_arvalid;\n wire s_axi_ctrl_arready;\n wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_araddr;\n // Slave Interface Read Data Ports\n wire s_axi_ctrl_rvalid;\n wire s_axi_ctrl_rready;\n wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_rdata;\n wire [1:0] s_axi_ctrl_rresp;\n\n // Interrupt output\n wire interrupt;\n\n wire sys_clk_p;\n wire sys_clk_n;\n wire mmcm_clk;\n wire clk_ref_p;\n wire clk_ref_n;\n wire clk_ref_i;\n wire [11:0] device_temp_i;\n\n // Debug port signals\n wire dbg_idel_down_all;\n wire dbg_idel_down_cpt;\n wire dbg_idel_up_all;\n wire dbg_idel_up_cpt;\n wire dbg_sel_all_idel_cpt;\n wire [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt;\n wire dbg_sel_pi_incdec;\n wire [DQS_CNT_WIDTH:0] dbg_byte_sel;\n wire dbg_pi_f_inc;\n wire dbg_pi_f_dec;\n wire [5:0] dbg_pi_counter_read_val;\n wire [8:0] dbg_po_counter_read_val;\n\n wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_tap_cnt;\n wire [(5*DQS_WIDTH*RANKS)-1:0] dbg_dq_idelay_tap_cnt;\n wire [255:0] dbg_calib_top;\n wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_first_edge_cnt;\n wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_second_edge_cnt;\n wire [(6*RANKS)-1:0] dbg_rd_data_offset;\n wire [255:0] dbg_phy_rdlvl;\n wire [99:0] dbg_phy_wrcal;\n wire [(6*DQS_WIDTH)-1:0] dbg_final_po_fine_tap_cnt;\n wire [(3*DQS_WIDTH)-1:0] dbg_final_po_coarse_tap_cnt;\n wire [255:0] dbg_phy_wrlvl;\n wire [255:0] dbg_phy_init;\n wire [255:0] dbg_prbs_rdlvl;\n wire [255:0] dbg_dqs_found_cal;\n wire dbg_pi_phaselock_start;\n wire dbg_pi_phaselocked_done;\n wire dbg_pi_phaselock_err;\n wire dbg_pi_dqsfound_start;\n wire dbg_pi_dqsfound_done;\n wire dbg_pi_dqsfound_err;\n wire dbg_wrcal_start;\n wire dbg_wrcal_done;\n wire dbg_wrcal_err;\n wire [11:0] dbg_pi_dqs_found_lanes_phy4lanes;\n wire [11:0] dbg_pi_phase_locked_phy4lanes;\n wire dbg_oclkdelay_calib_start;\n wire dbg_oclkdelay_calib_done;\n wire [255:0] dbg_phy_oclkdelay_cal;\n wire [(DRAM_WIDTH*16)-1:0] dbg_oclkdelay_rd_data;\n wire [DQS_WIDTH-1:0] dbg_rd_data_edge_detect;\n wire [(2*nCK_PER_CLK*DQ_WIDTH)-1:0] dbg_rddata;\n wire dbg_rddata_valid;\n wire [1:0] dbg_rdlvl_done;\n wire [1:0] dbg_rdlvl_err;\n wire [1:0] dbg_rdlvl_start;\n wire [(6*DQS_WIDTH)-1:0] dbg_wrlvl_fine_tap_cnt;\n wire [(3*DQS_WIDTH)-1:0] dbg_wrlvl_coarse_tap_cnt;\n wire [5:0] dbg_tap_cnt_during_wrlvl;\n wire dbg_wl_edge_detect_valid;\n wire dbg_wrlvl_done;\n wire dbg_wrlvl_err;\n wire dbg_wrlvl_start;\n reg [63:0] dbg_rddata_r;\n reg dbg_rddata_valid_r;\n wire [53:0] ocal_tap_cnt;\n wire [4:0] dbg_dqs;\n wire [8:0] dbg_bit;\n wire [8:0] rd_data_edge_detect_r;\n wire [53:0] wl_po_fine_cnt;\n wire [26:0] wl_po_coarse_cnt;\n wire [(6*RANKS)-1:0] dbg_calib_rd_data_offset_1;\n wire [(6*RANKS)-1:0] dbg_calib_rd_data_offset_2;\n wire [5:0] dbg_data_offset;\n wire [5:0] dbg_data_offset_1;\n wire [5:0] dbg_data_offset_2;\n\n wire [390:0] ddr3_ila_wrpath_int;\n wire [1023:0] ddr3_ila_rdpath_int;\n wire [119:0] ddr3_ila_basic_int;\n wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_final_dqs_tap_cnt_r_int;\n wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_first_edge_taps_int;\n wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_second_edge_taps_int;\n \n\n//***************************************************************************\n\n\n\n assign ui_clk = clk;\n assign ui_clk_sync_rst = rst;\n \n assign sys_clk_p = 1'b0;\n assign sys_clk_n = 1'b0;\n assign clk_ref_i = 1'b0;\n \n\n generate\n if (REFCLK_TYPE == \"USE_SYSTEM_CLOCK\")\n assign clk_ref_in = mmcm_clk;\n else\n assign clk_ref_in = clk_ref_i;\n endgenerate\n\n mig_7series_v4_0_iodelay_ctrl #\n (\n .TCQ (TCQ),\n .IODELAY_GRP0 (IODELAY_GRP0),\n .IODELAY_GRP1 (IODELAY_GRP1),\n .REFCLK_TYPE (REFCLK_TYPE),\n .SYSCLK_TYPE (SYSCLK_TYPE),\n .SYS_RST_PORT (SYS_RST_PORT),\n .RST_ACT_LOW (RST_ACT_LOW),\n .DIFF_TERM_REFCLK (DIFF_TERM_REFCLK),\n .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),\n .REF_CLK_MMCM_IODELAY_CTRL (REF_CLK_MMCM_IODELAY_CTRL)\n )\n u_iodelay_ctrl\n (\n // Outputs\n .iodelay_ctrl_rdy (iodelay_ctrl_rdy),\n .sys_rst_o (sys_rst_o),\n .clk_ref (clk_ref),\n // Inputs\n .clk_ref_p (clk_ref_p),\n .clk_ref_n (clk_ref_n),\n .clk_ref_i (clk_ref_in),\n .sys_rst (sys_rst)\n );\n mig_7series_v4_0_clk_ibuf #\n (\n .SYSCLK_TYPE (SYSCLK_TYPE),\n .DIFF_TERM_SYSCLK (DIFF_TERM_SYSCLK)\n )\n u_ddr3_clk_ibuf\n (\n .sys_clk_p (sys_clk_p),\n .sys_clk_n (sys_clk_n),\n .sys_clk_i (sys_clk_i),\n .mmcm_clk (mmcm_clk)\n );\n // Temperature monitoring logic\n\n generate\n if (TEMP_MON_EN == \"ON\") begin: temp_mon_enabled\n\n mig_7series_v4_0_tempmon #\n (\n .TCQ (TCQ),\n .TEMP_MON_CONTROL (TEMP_MON_CONTROL),\n .XADC_CLK_PERIOD (XADC_CLK_PERIOD),\n .tTEMPSAMPLE (tTEMPSAMPLE)\n )\n u_tempmon\n (\n .clk (clk),\n .xadc_clk (clk_ref[0]),\n .rst (rst),\n .device_temp_i (device_temp_i),\n .device_temp (device_temp)\n );\n end else begin: temp_mon_disabled\n\n assign device_temp = 'b0;\n\n end\n endgenerate\n \n mig_7series_v4_0_infrastructure #\n (\n .TCQ (TCQ),\n .nCK_PER_CLK (nCK_PER_CLK),\n .CLKIN_PERIOD (CLKIN_PERIOD),\n .SYSCLK_TYPE (SYSCLK_TYPE),\n .CLKFBOUT_MULT (CLKFBOUT_MULT),\n .DIVCLK_DIVIDE (DIVCLK_DIVIDE),\n .CLKOUT0_PHASE (CLKOUT0_PHASE),\n .CLKOUT0_DIVIDE (CLKOUT0_DIVIDE),\n .CLKOUT1_DIVIDE (CLKOUT1_DIVIDE),\n .CLKOUT2_DIVIDE (CLKOUT2_DIVIDE),\n .CLKOUT3_DIVIDE (CLKOUT3_DIVIDE),\n .MMCM_VCO (MMCM_VCO),\n .MMCM_MULT_F (MMCM_MULT_F),\n .MMCM_DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE),\n .RST_ACT_LOW (RST_ACT_LOW),\n .tCK (tCK),\n .MEM_TYPE (DRAM_TYPE)\n )\n u_ddr3_infrastructure\n (\n // Outputs\n .rstdiv0 (rst),\n .clk (clk),\n .clk_div2 (clk_div2),\n .rst_div2 (rst_div2),\n .mem_refclk (mem_refclk),\n .freq_refclk (freq_refclk),\n .sync_pulse (sync_pulse),\n .mmcm_ps_clk (mmcm_ps_clk),\n .poc_sample_pd (poc_sample_pd),\n .psdone (psdone),\n .iddr_rst (iddr_rst),\n// .auxout_clk (),\n .ui_addn_clk_0 (),\n .ui_addn_clk_1 (),\n .ui_addn_clk_2 (),\n .ui_addn_clk_3 (),\n .ui_addn_clk_4 (),\n .pll_locked (pll_locked),\n .mmcm_locked (mmcm_locked),\n .rst_phaser_ref (rst_phaser_ref),\n // Inputs\n .psen (psen),\n .psincdec (psincdec),\n .mmcm_clk (mmcm_clk),\n .sys_rst (sys_rst_o),\n .iodelay_ctrl_rdy (iodelay_ctrl_rdy),\n .ref_dll_lock (ref_dll_lock)\n );\n \n\n mig_7series_v4_0_memc_ui_top_axi #\n (\n .TCQ (TCQ),\n .ADDR_CMD_MODE (ADDR_CMD_MODE),\n .AL (AL),\n .PAYLOAD_WIDTH (PAYLOAD_WIDTH),\n .BANK_WIDTH (BANK_WIDTH),\n .BM_CNT_WIDTH (BM_CNT_WIDTH),\n .BURST_MODE (BURST_MODE),\n .BURST_TYPE (BURST_TYPE),\n .CA_MIRROR (CA_MIRROR),\n .DDR3_VDD_OP_VOLT (VDD_OP_VOLT),\n .CK_WIDTH (CK_WIDTH),\n .COL_WIDTH (COL_WIDTH),\n .CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1),\n .CS_WIDTH (CS_WIDTH),\n .nCS_PER_RANK (nCS_PER_RANK),\n .CKE_WIDTH (CKE_WIDTH),\n .DATA_WIDTH (DATA_WIDTH),\n .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),\n .DM_WIDTH (DM_WIDTH),\n .DQ_CNT_WIDTH (DQ_CNT_WIDTH),\n .DQ_WIDTH (DQ_WIDTH),\n .DQS_CNT_WIDTH (DQS_CNT_WIDTH),\n .DQS_WIDTH (DQS_WIDTH),\n .DRAM_TYPE (DRAM_TYPE),\n .DRAM_WIDTH (DRAM_WIDTH),\n .ECC (ECC),\n .ECC_WIDTH (ECC_WIDTH),\n .ECC_TEST (ECC_TEST),\n .MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),\n .REFCLK_FREQ (REFCLK_FREQ),\n .nAL (nAL),\n .nBANK_MACHS (nBANK_MACHS),\n .CKE_ODT_AUX (CKE_ODT_AUX),\n .nCK_PER_CLK (nCK_PER_CLK),\n .ORDERING (ORDERING),\n .OUTPUT_DRV (OUTPUT_DRV),\n .IBUF_LPWR_MODE (IBUF_LPWR_MODE),\n .DATA_IO_IDLE_PWRDWN (DATA_IO_IDLE_PWRDWN),\n .BANK_TYPE (BANK_TYPE),\n .DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE),\n .IODELAY_GRP0 (IODELAY_GRP0),\n .IODELAY_GRP1 (IODELAY_GRP1),\n .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),\n .REG_CTRL (REG_CTRL),\n .RTT_NOM (RTT_NOM),\n .RTT_WR (RTT_WR),\n .CL (CL),\n .CWL (CWL),\n .tCK (tCK),\n .tCKE (tCKE),\n .tFAW (tFAW),\n .tPRDI (tPRDI),\n .tRAS (tRAS),\n .tRCD (tRCD),\n .tREFI (tREFI),\n .tRFC (tRFC),\n .tRP (tRP),\n .tRRD (tRRD),\n .tRTP (tRTP),\n .tWTR (tWTR),\n .tZQI (tZQI),\n .tZQCS (tZQCS),\n .USER_REFRESH (USER_REFRESH),\n .TEMP_MON_EN (TEMP_MON_EN),\n .WRLVL (WRLVL),\n .DEBUG_PORT (DEBUG_PORT),\n .CAL_WIDTH (CAL_WIDTH),\n .RANK_WIDTH (RANK_WIDTH),\n .RANKS (RANKS),\n .ODT_WIDTH (ODT_WIDTH),\n .ROW_WIDTH (ROW_WIDTH),\n .ADDR_WIDTH (ADDR_WIDTH),\n .APP_DATA_WIDTH (APP_DATA_WIDTH),\n .APP_MASK_WIDTH (APP_MASK_WIDTH),\n .SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),\n .BYTE_LANES_B0 (BYTE_LANES_B0),\n .BYTE_LANES_B1 (BYTE_LANES_B1),\n .BYTE_LANES_B2 (BYTE_LANES_B2),\n .BYTE_LANES_B3 (BYTE_LANES_B3),\n .BYTE_LANES_B4 (BYTE_LANES_B4),\n .DATA_CTL_B0 (DATA_CTL_B0),\n .DATA_CTL_B1 (DATA_CTL_B1),\n .DATA_CTL_B2 (DATA_CTL_B2),\n .DATA_CTL_B3 (DATA_CTL_B3),\n .DATA_CTL_B4 (DATA_CTL_B4),\n .PHY_0_BITLANES (PHY_0_BITLANES),\n .PHY_1_BITLANES (PHY_1_BITLANES),\n .PHY_2_BITLANES (PHY_2_BITLANES),\n .CK_BYTE_MAP (CK_BYTE_MAP),\n .ADDR_MAP (ADDR_MAP),\n .BANK_MAP (BANK_MAP),\n .CAS_MAP (CAS_MAP),\n .CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),\n .CKE_MAP (CKE_MAP),\n .ODT_MAP (ODT_MAP),\n .CS_MAP (CS_MAP),\n .PARITY_MAP (PARITY_MAP),\n .RAS_MAP (RAS_MAP),\n .WE_MAP (WE_MAP),\n .DQS_BYTE_MAP (DQS_BYTE_MAP),\n .DATA0_MAP (DATA0_MAP),\n .DATA1_MAP (DATA1_MAP),\n .DATA2_MAP (DATA2_MAP),\n .DATA3_MAP (DATA3_MAP),\n .DATA4_MAP (DATA4_MAP),\n .DATA5_MAP (DATA5_MAP),\n .DATA6_MAP (DATA6_MAP),\n .DATA7_MAP (DATA7_MAP),\n .DATA8_MAP (DATA8_MAP),\n .DATA9_MAP (DATA9_MAP),\n .DATA10_MAP (DATA10_MAP),\n .DATA11_MAP (DATA11_MAP),\n .DATA12_MAP (DATA12_MAP),\n .DATA13_MAP (DATA13_MAP),\n .DATA14_MAP (DATA14_MAP),\n .DATA15_MAP (DATA15_MAP),\n .DATA16_MAP (DATA16_MAP),\n .DATA17_MAP (DATA17_MAP),\n .MASK0_MAP (MASK0_MAP),\n .MASK1_MAP (MASK1_MAP),\n .CALIB_ROW_ADD (CALIB_ROW_ADD),\n .CALIB_COL_ADD (CALIB_COL_ADD),\n .CALIB_BA_ADD (CALIB_BA_ADD),\n .IDELAY_ADJ (IDELAY_ADJ),\n .FINE_PER_BIT (FINE_PER_BIT),\n .CENTER_COMP_MODE (CENTER_COMP_MODE),\n .PI_VAL_ADJ (PI_VAL_ADJ),\n .SLOT_0_CONFIG (SLOT_0_CONFIG),\n .SLOT_1_CONFIG (SLOT_1_CONFIG),\n .MEM_ADDR_ORDER (MEM_ADDR_ORDER),\n .STARVE_LIMIT (STARVE_LIMIT),\n .C_S_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),\n .C_S_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH),\n .C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),\n .C_S_AXI_SUPPORTS_NARROW_BURST (C_S_AXI_SUPPORTS_NARROW_BURST),\n .C_RD_WR_ARB_ALGORITHM (C_RD_WR_ARB_ALGORITHM),\n .C_S_AXI_REG_EN0 (C_S_AXI_REG_EN0),\n .C_S_AXI_REG_EN1 (C_S_AXI_REG_EN1),\n .C_S_AXI_CTRL_ADDR_WIDTH (C_S_AXI_CTRL_ADDR_WIDTH),\n .C_S_AXI_CTRL_DATA_WIDTH (C_S_AXI_CTRL_DATA_WIDTH),\n .C_S_AXI_BASEADDR (C_S_AXI_BASEADDR),\n .C_ECC_ONOFF_RESET_VALUE (C_ECC_ONOFF_RESET_VALUE),\n .C_ECC_CE_COUNTER_WIDTH (C_ECC_CE_COUNTER_WIDTH),\n .USE_CS_PORT (USE_CS_PORT),\n .USE_DM_PORT (USE_DM_PORT),\n .USE_ODT_PORT (USE_ODT_PORT),\n .MASTER_PHY_CTL (PHY_CONTROL_MASTER_BANK),\n .TAPSPERKCLK (TAPSPERKCLK),\n .SKIP_CALIB (SKIP_CALIB),\n .FPGA_VOLT_TYPE (FPGA_VOLT_TYPE)\n )\n u_memc_ui_top_axi\n (\n .clk (clk),\n .clk_div2 (clk_div2),\n .rst_div2 (rst_div2),\n .clk_ref (clk_ref),\n .mem_refclk (mem_refclk), //memory clock\n .freq_refclk (freq_refclk),\n .pll_lock (pll_locked),\n .sync_pulse (sync_pulse),\n .mmcm_ps_clk (mmcm_ps_clk),\n .poc_sample_pd (poc_sample_pd),\n .psdone (psdone),\n .iddr_rst (iddr_rst),\n .psen (psen),\n .psincdec (psincdec),\n .rst (rst),\n .rst_phaser_ref (rst_phaser_ref),\n .ref_dll_lock (ref_dll_lock),\n\n// Memory interface ports\n .ddr_dq (ddr3_dq),\n .ddr_dqs_n (ddr3_dqs_n),\n .ddr_dqs (ddr3_dqs_p),\n .ddr_addr (ddr3_addr),\n .ddr_ba (ddr3_ba),\n .ddr_cas_n (ddr3_cas_n),\n .ddr_ck_n (ddr3_ck_n),\n .ddr_ck (ddr3_ck_p),\n .ddr_cke (ddr3_cke),\n .ddr_cs_n (ddr3_cs_n),\n .ddr_dm (ddr3_dm),\n .ddr_odt (ddr3_odt),\n .ddr_ras_n (ddr3_ras_n),\n .ddr_reset_n (ddr3_reset_n),\n .ddr_parity (ddr3_parity),\n .ddr_we_n (ddr3_we_n),\n .bank_mach_next (bank_mach_next),\n\n// Application interface ports\n .app_ecc_multiple_err_o (),\n .app_ecc_single_err (),\n\n .device_temp (device_temp),\n\n // skip calibration ports\n `ifdef SKIP_CALIB\n .calib_tap_req (calib_tap_req),\n .calib_tap_load (calib_tap_load),\n .calib_tap_addr (calib_tap_addr),\n .calib_tap_val (calib_tap_val),\n .calib_tap_load_done (calib_tap_load_done),\n `else\n .calib_tap_req (),\n .calib_tap_load (1'b0),\n .calib_tap_addr (7'b0),\n .calib_tap_val (8'b0),\n .calib_tap_load_done (1'b0),\n `endif\n\n// Debug logic ports\n .dbg_idel_up_all (dbg_idel_up_all),\n .dbg_idel_down_all (dbg_idel_down_all),\n .dbg_idel_up_cpt (dbg_idel_up_cpt),\n .dbg_idel_down_cpt (dbg_idel_down_cpt),\n .dbg_sel_idel_cpt (dbg_sel_idel_cpt),\n .dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),\n .dbg_sel_pi_incdec (dbg_sel_pi_incdec),\n .dbg_sel_po_incdec (dbg_sel_po_incdec),\n .dbg_byte_sel (dbg_byte_sel),\n .dbg_pi_f_inc (dbg_pi_f_inc),\n .dbg_pi_f_dec (dbg_pi_f_dec),\n .dbg_po_f_inc (dbg_po_f_inc),\n .dbg_po_f_stg23_sel (dbg_po_f_stg23_sel),\n .dbg_po_f_dec (dbg_po_f_dec),\n .dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),\n .dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),\n .dbg_calib_top (dbg_calib_top),\n .dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),\n .dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),\n .dbg_rd_data_offset (dbg_rd_data_offset),\n .dbg_phy_rdlvl (dbg_phy_rdlvl),\n .dbg_phy_wrcal (dbg_phy_wrcal),\n .dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),\n .dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt),\n .dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),\n .dbg_rddata (dbg_rddata),\n .dbg_rddata_valid (dbg_rddata_valid),\n .dbg_rdlvl_done (dbg_rdlvl_done),\n .dbg_rdlvl_err (dbg_rdlvl_err),\n .dbg_rdlvl_start (dbg_rdlvl_start),\n .dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),\n .dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),\n .dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),\n .dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),\n .dbg_wrlvl_done (dbg_wrlvl_done),\n .dbg_wrlvl_err (dbg_wrlvl_err),\n .dbg_wrlvl_start (dbg_wrlvl_start),\n .dbg_phy_wrlvl (dbg_phy_wrlvl),\n .dbg_phy_init (dbg_phy_init),\n .dbg_prbs_rdlvl (dbg_prbs_rdlvl),\n .dbg_pi_counter_read_val (dbg_pi_counter_read_val),\n .dbg_po_counter_read_val (dbg_po_counter_read_val),\n .dbg_prbs_final_dqs_tap_cnt_r (dbg_prbs_final_dqs_tap_cnt_r_int),\n .dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps_int),\n .dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps_int),\n .dbg_pi_phaselock_start (dbg_pi_phaselock_start),\n .dbg_pi_phaselocked_done (dbg_pi_phaselocked_done),\n .dbg_pi_phaselock_err (dbg_pi_phaselock_err),\n .dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes),\n .dbg_pi_dqsfound_start (dbg_pi_dqsfound_start),\n .dbg_pi_dqsfound_done (dbg_pi_dqsfound_done),\n .dbg_pi_dqsfound_err (dbg_pi_dqsfound_err),\n .dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes),\n .dbg_calib_rd_data_offset_1 (dbg_calib_rd_data_offset_1),\n .dbg_calib_rd_data_offset_2 (dbg_calib_rd_data_offset_2),\n .dbg_data_offset (dbg_data_offset),\n .dbg_data_offset_1 (dbg_data_offset_1),\n .dbg_data_offset_2 (dbg_data_offset_2),\n .dbg_wrcal_start (dbg_wrcal_start),\n .dbg_wrcal_done (dbg_wrcal_done),\n .dbg_wrcal_err (dbg_wrcal_err),\n .dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal),\n .dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data),\n .dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start),\n .dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done),\n .dbg_dqs_found_cal (dbg_dqs_found_cal), \n .aresetn (aresetn),\n .app_sr_req (app_sr_req),\n .app_sr_active (app_sr_active),\n .app_ref_req (app_ref_req),\n .app_ref_ack (app_ref_ack),\n .app_zq_req (app_zq_req),\n .app_zq_ack (app_zq_ack),\n\n // Slave Interface Write Address Ports\n .s_axi_awid (s_axi_awid),\n .s_axi_awaddr (s_axi_awaddr),\n .s_axi_awlen (s_axi_awlen),\n .s_axi_awsize (s_axi_awsize),\n .s_axi_awburst (s_axi_awburst),\n .s_axi_awlock (s_axi_awlock),\n .s_axi_awcache (s_axi_awcache),\n .s_axi_awprot (s_axi_awprot),\n .s_axi_awqos (s_axi_awqos),\n .s_axi_awvalid (s_axi_awvalid),\n .s_axi_awready (s_axi_awready),\n // Slave Interface Write Data Ports\n .s_axi_wdata (s_axi_wdata),\n .s_axi_wstrb (s_axi_wstrb),\n .s_axi_wlast (s_axi_wlast),\n .s_axi_wvalid (s_axi_wvalid),\n .s_axi_wready (s_axi_wready),\n // Slave Interface Write Response Ports\n .s_axi_bid (s_axi_bid),\n .s_axi_bresp (s_axi_bresp),\n .s_axi_bvalid (s_axi_bvalid),\n .s_axi_bready (s_axi_bready),\n // Slave Interface Read Address Ports\n .s_axi_arid (s_axi_arid),\n .s_axi_araddr (s_axi_araddr),\n .s_axi_arlen (s_axi_arlen),\n .s_axi_arsize (s_axi_arsize),\n .s_axi_arburst (s_axi_arburst),\n .s_axi_arlock (s_axi_arlock),\n .s_axi_arcache (s_axi_arcache),\n .s_axi_arprot (s_axi_arprot),\n .s_axi_arqos (s_axi_arqos),\n .s_axi_arvalid (s_axi_arvalid),\n .s_axi_arready (s_axi_arready),\n // Slave Interface Read Data Ports\n .s_axi_rid (s_axi_rid),\n .s_axi_rdata (s_axi_rdata),\n .s_axi_rresp (s_axi_rresp),\n .s_axi_rlast (s_axi_rlast),\n .s_axi_rvalid (s_axi_rvalid),\n .s_axi_rready (s_axi_rready),\n // AXI CTRL port\n .s_axi_ctrl_awvalid (s_axi_ctrl_awvalid),\n .s_axi_ctrl_awready (s_axi_ctrl_awready),\n .s_axi_ctrl_awaddr (s_axi_ctrl_awaddr),\n // Slave Interface Write Data Ports\n .s_axi_ctrl_wvalid (s_axi_ctrl_wvalid),\n .s_axi_ctrl_wready (s_axi_ctrl_wready),\n .s_axi_ctrl_wdata (s_axi_ctrl_wdata),\n // Slave Interface Write Response Ports\n .s_axi_ctrl_bvalid (s_axi_ctrl_bvalid),\n .s_axi_ctrl_bready (s_axi_ctrl_bready),\n .s_axi_ctrl_bresp (s_axi_ctrl_bresp),\n // Slave Interface Read Address Ports\n .s_axi_ctrl_arvalid (s_axi_ctrl_arvalid),\n .s_axi_ctrl_arready (s_axi_ctrl_arready),\n .s_axi_ctrl_araddr (s_axi_ctrl_araddr),\n // Slave Interface Read Data Ports\n .s_axi_ctrl_rvalid (s_axi_ctrl_rvalid),\n .s_axi_ctrl_rready (s_axi_ctrl_rready),\n .s_axi_ctrl_rdata (s_axi_ctrl_rdata),\n .s_axi_ctrl_rresp (s_axi_ctrl_rresp),\n // Interrupt output\n .interrupt (interrupt),\n .init_calib_complete (init_calib_complete),\n .dbg_poc ()\n );\n\n \n\n\n\n\n //*********************************************************************\n // Resetting all RTL debug inputs as the debug ports are not enabled\n //*********************************************************************\n assign dbg_idel_down_all = 1'b0;\n assign dbg_idel_down_cpt = 1'b0;\n assign dbg_idel_up_all = 1'b0;\n assign dbg_idel_up_cpt = 1'b0;\n assign dbg_sel_all_idel_cpt = 1'b0;\n assign dbg_sel_idel_cpt = 'b0;\n assign dbg_byte_sel = 'd0;\n assign dbg_sel_pi_incdec = 1'b0;\n assign dbg_pi_f_inc = 1'b0;\n assign dbg_pi_f_dec = 1'b0;\n assign dbg_po_f_inc = 'b0;\n assign dbg_po_f_dec = 'b0;\n assign dbg_po_f_stg23_sel = 'b0;\n assign dbg_sel_po_incdec = 'b0;\n\n \n\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ecc/mig_7series_v4_0_ecc_buf.v", "content": "//*****************************************************************************\n// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor : Xilinx\n// \\ \\ \\/ Version : %version\n// \\ \\ Application : MIG\n// / / Filename : ecc_buf.v\n// /___/ /\\ Date Last Modified : $date$\n// \\ \\ / \\ Date Created : Tue Jun 30 2009\n// \\___\\/\\___\\\n//\n//Device : 7-Series\n//Design Name : DDR3 SDRAM\n//Purpose :\n//Reference :\n//Revision History :\n//*****************************************************************************\n\n`timescale 1ps/1ps\n\nmodule mig_7series_v4_0_ecc_buf\n #(\n parameter TCQ = 100,\n parameter PAYLOAD_WIDTH = 64,\n parameter DATA_BUF_ADDR_WIDTH = 4,\n parameter DATA_BUF_OFFSET_WIDTH = 1,\n parameter DATA_WIDTH = 64,\n parameter nCK_PER_CLK = 4\n )\n (\n /*AUTOARG*/\n // Outputs\n rd_merge_data,\n // Inputs\n clk, rst, rd_data_addr, rd_data_offset, wr_data_addr,\n wr_data_offset, rd_data, wr_ecc_buf\n );\n\n input clk;\n input rst;\n\n // RMW architecture supports only 16 data buffer entries.\n // Allow DATA_BUF_ADDR_WIDTH to be greater than 4, but\n // assume the upper bits are used for tagging.\n\n input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;\n input [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;\n wire [4:0] buf_wr_addr;\n\n input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;\n input [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;\n reg [4:0] buf_rd_addr_r;\n\n generate\n if (DATA_BUF_ADDR_WIDTH >= 4) begin : ge_4_addr_bits\n always @(posedge clk) \n buf_rd_addr_r <= #TCQ{wr_data_addr[3:0], wr_data_offset};\n assign buf_wr_addr = {rd_data_addr[3:0], rd_data_offset};\n end\n else begin : lt_4_addr_bits\n always @(posedge clk) \n buf_rd_addr_r <= #TCQ{{4-DATA_BUF_ADDR_WIDTH{1'b0}},\n wr_data_addr[DATA_BUF_ADDR_WIDTH-1:0],\n wr_data_offset};\n assign buf_wr_addr = {{4-DATA_BUF_ADDR_WIDTH{1'b0}},\n rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0], \n rd_data_offset};\n end\n endgenerate\n\n input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;\n reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] payload;\n integer h;\n always @(/*AS*/rd_data)\n for (h=0; h<2*nCK_PER_CLK; h=h+1)\n payload[h*DATA_WIDTH+:DATA_WIDTH] = \n rd_data[h*PAYLOAD_WIDTH+:DATA_WIDTH];\n\n input wr_ecc_buf;\n localparam BUF_WIDTH = 2*nCK_PER_CLK*DATA_WIDTH;\n localparam FULL_RAM_CNT = (BUF_WIDTH/6);\n localparam REMAINDER = BUF_WIDTH % 6;\n localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);\n localparam RAM_WIDTH = (RAM_CNT*6);\n wire [RAM_WIDTH-1:0] buf_out_data;\n generate\n begin : ram_buf\n wire [RAM_WIDTH-1:0] buf_in_data;\n if (REMAINDER == 0)\n assign buf_in_data = payload;\n else\n assign buf_in_data = {{6-REMAINDER{1'b0}}, payload};\n\n genvar i;\n for (i=0; i 0)\n for (t=0; t<2*nCK_PER_CLK; t=t+1) begin : copy_raw_bits\n always @(/*AS*/ecc_rddata_r)\n rd_data[(t+1)*PAYLOAD_WIDTH-1-:RAW_BIT_WIDTH] =\n ecc_rddata_r[(t+1)*PAYLOAD_WIDTH-1-:RAW_BIT_WIDTH];\n end\n endgenerate\n\n // Generate status information.\n input ecc_status_valid;\n output wire [2*nCK_PER_CLK-1:0] ecc_single;\n output wire [2*nCK_PER_CLK-1:0] ecc_multiple;\n genvar v;\n generate\n for (v=0; v<2*nCK_PER_CLK; v=v+1) begin : compute_status\n wire zero = ~|syndrome_r[v*ECC_WIDTH+:ECC_WIDTH];\n wire odd = ^syndrome_r[v*ECC_WIDTH+:ECC_WIDTH];\n assign ecc_single[v] = ecc_status_valid && ~zero && odd;\n assign ecc_multiple[v] = ecc_status_valid && ~zero && ~odd;\n end\n endgenerate\n\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ecc/mig_7series_v4_0_ecc_gen.v", "content": "//*****************************************************************************\n// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor : Xilinx\n// \\ \\ \\/ Version : %version\n// \\ \\ Application : MIG\n// / / Filename : ecc_gen.v\n// /___/ /\\ Date Last Modified : $date$\n// \\ \\ / \\ Date Created : Tue Jun 30 2009\n// \\___\\/\\___\\\n//\n//Device : 7-Series\n//Design Name : DDR3 SDRAM\n//Purpose :\n//Reference :\n//Revision History :\n//*****************************************************************************\n\n`timescale 1ps/1ps\n\n// Generate the ecc code. Note that the synthesizer should\n// generate this as a static logic. Code in this block should\n// never run during simulation phase, or directly impact timing.\n//\n// The code generated is a single correct, double detect code.\n// It is the classic Hamming code. Instead, the code is\n// optimized for minimal/balanced tree depth and size. See\n// Hsiao IBM Technial Journal 1970.\n//\n// The code is returned as a single bit vector, h_rows. This was\n// the only way to \"subroutinize\" this with the restrictions of\n// disallowed include files and that matrices cannot be passed\n// in ports.\n//\n// Factorial and the combos functions are defined. Combos\n// simply computes the number of combinations from the set\n// size and elements at a time.\n//\n// The function next_combo computes the next combination in\n// lexicographical order given the \"current\" combination. Its\n// output is undefined if given the last combination in the \n// lexicographical order. \n// \n// next_combo is insensitive to the number of elements in the\n// combinations.\n//\n// An H transpose matrix is generated because that's the easiest\n// way to do it. The H transpose matrix is generated by taking\n// the one at a time combinations, then the 3 at a time, then\n// the 5 at a time. The number combinations used is equal to\n// the width of the code (CODE_WIDTH). The boundaries between\n// the 1, 3 and 5 groups are hardcoded in the for loop.\n//\n// At the same time the h_rows vector is generated from the\n// H transpose matrix.\n\nmodule mig_7series_v4_0_ecc_gen\n #(\n parameter CODE_WIDTH = 72,\n parameter ECC_WIDTH = 8,\n parameter DATA_WIDTH = 64\n )\n (\n /*AUTOARG*/\n // Outputs\n h_rows\n );\n \n\n function integer factorial (input integer i);\n integer index;\n if (i == 1) factorial = 1;\n else begin\n factorial = 1;\n for (index=2; index<=i; index=index+1)\n factorial = factorial * index;\n end\n endfunction // factorial\n\n function integer combos (input integer n, k);\n combos = factorial(n)/(factorial(k)*factorial(n-k));\n endfunction // combinations\n \n // function next_combo\n // Given a combination, return the next combo in lexicographical\n // order. Scans from right to left. Assumes the first combination\n // is k ones all of the way to the left.\n //\n // Upon entry, initialize seen0, trig1, and ones. \"seen0\" means\n // that a zero has been observed while scanning from right to left.\n // \"trig1\" means that a one have been observed _after_ seen0 is set.\n // \"ones\" counts the number of ones observed while scanning the input.\n //\n // If trig1 is one, just copy the input bit to the output and increment\n // to the next bit. Otherwise set the the output bit to zero, if the \n // input is a one, increment ones. If the input bit is a one and seen0\n // is true, dump out the accumulated ones. Set seen0 to the complement\n // of the input bit. Note that seen0 is not used subsequent to trig1 \n // getting set.\n function [ECC_WIDTH-1:0] next_combo (input [ECC_WIDTH-1:0] i);\n integer index;\n integer dump_index;\n reg seen0;\n reg trig1;\n// integer ones;\n reg [ECC_WIDTH-1:0] ones;\n begin\n seen0 = 1'b0;\n trig1 = 1'b0;\n ones = 0;\n for (index=0; index=0;dump_index=dump_index-1)\n if (dump_index>=index-ones) next_combo[dump_index] = 1'b1; \n end \n seen0 = ~i[index];\n end // else: !if(trig1)\n end \n end // function\n endfunction // next_combo\n\n wire [ECC_WIDTH-1:0] ht_matrix [CODE_WIDTH-1:0];\n output wire [CODE_WIDTH*ECC_WIDTH-1:0] h_rows;\n\n localparam COMBOS_3 = combos(ECC_WIDTH, 3);\n localparam COMBOS_5 = combos(ECC_WIDTH, 5);\n genvar n;\n genvar s;\n generate\n for (n=0; n DATA_WIDTH)\n assign merged_data[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH]=\n wr_data[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH];\n \n end\n endgenerate\n\n // Generate ECC and overlay onto mc_wrdata.\n input [CODE_WIDTH*ECC_WIDTH-1:0] h_rows;\n input [2*nCK_PER_CLK-1:0] raw_not_ecc;\n reg [2*nCK_PER_CLK-1:0] raw_not_ecc_r;\n always @(posedge clk) raw_not_ecc_r <= #TCQ raw_not_ecc;\n output reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata;\n reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata_c;\n genvar j;\n integer k;\n generate\n for (j=0; j<2*nCK_PER_CLK; j=j+1) begin : ecc_word\n always @(/*AS*/h_rows or merged_data or raw_not_ecc_r) begin\n mc_wrdata_c[j*DQ_WIDTH+:DQ_WIDTH] =\n {{DQ_WIDTH-PAYLOAD_WIDTH{1'b0}},\n merged_data[j*PAYLOAD_WIDTH+:PAYLOAD_WIDTH]};\n for (k=0; k 6) || (CL < 3)))));\n // Not needed after the CWL fix for DDR2\n // ddr2_improper_CWL: assert property\n // (@(posedge clk) (~((DRAM_TYPE == \"DDR2\") && ((CL - CWL) != 1))));\n`endif\n\n mig_7series_v4_0_ddr_phy_top #\n (\n .TCQ (TCQ),\n .DDR3_VDD_OP_VOLT (DDR3_VDD_OP_VOLT),\n .REFCLK_FREQ (REFCLK_FREQ),\n .BYTE_LANES_B0 (BYTE_LANES_B0),\n .BYTE_LANES_B1 (BYTE_LANES_B1),\n .BYTE_LANES_B2 (BYTE_LANES_B2),\n .BYTE_LANES_B3 (BYTE_LANES_B3),\n .BYTE_LANES_B4 (BYTE_LANES_B4),\n .PHY_0_BITLANES (PHY_0_BITLANES),\n .PHY_1_BITLANES (PHY_1_BITLANES),\n .PHY_2_BITLANES (PHY_2_BITLANES),\n .CA_MIRROR (CA_MIRROR),\n .CK_BYTE_MAP (CK_BYTE_MAP),\n .ADDR_MAP (ADDR_MAP),\n .BANK_MAP (BANK_MAP),\n .CAS_MAP (CAS_MAP),\n .CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),\n .CKE_MAP (CKE_MAP),\n .ODT_MAP (ODT_MAP),\n .CKE_ODT_AUX (CKE_ODT_AUX),\n .CS_MAP (CS_MAP),\n .PARITY_MAP (PARITY_MAP),\n .RAS_MAP (RAS_MAP),\n .WE_MAP (WE_MAP),\n .DQS_BYTE_MAP (DQS_BYTE_MAP),\n .DATA0_MAP (DATA0_MAP),\n .DATA1_MAP (DATA1_MAP),\n .DATA2_MAP (DATA2_MAP),\n .DATA3_MAP (DATA3_MAP),\n .DATA4_MAP (DATA4_MAP),\n .DATA5_MAP (DATA5_MAP),\n .DATA6_MAP (DATA6_MAP),\n .DATA7_MAP (DATA7_MAP),\n .DATA8_MAP (DATA8_MAP),\n .DATA9_MAP (DATA9_MAP),\n .DATA10_MAP (DATA10_MAP),\n .DATA11_MAP (DATA11_MAP),\n .DATA12_MAP (DATA12_MAP),\n .DATA13_MAP (DATA13_MAP),\n .DATA14_MAP (DATA14_MAP),\n .DATA15_MAP (DATA15_MAP),\n .DATA16_MAP (DATA16_MAP),\n .DATA17_MAP (DATA17_MAP),\n .MASK0_MAP (MASK0_MAP),\n .MASK1_MAP (MASK1_MAP),\n .CALIB_ROW_ADD (CALIB_ROW_ADD),\n .CALIB_COL_ADD (CALIB_COL_ADD),\n .CALIB_BA_ADD (CALIB_BA_ADD),\n .nCS_PER_RANK (nCS_PER_RANK),\n .CS_WIDTH (CS_WIDTH),\n .nCK_PER_CLK (nCK_PER_CLK),\n .PRE_REV3ES (PRE_REV3ES),\n .CKE_WIDTH (CKE_WIDTH),\n .DATA_CTL_B0 (DATA_CTL_B0),\n .DATA_CTL_B1 (DATA_CTL_B1),\n .DATA_CTL_B2 (DATA_CTL_B2),\n .DATA_CTL_B3 (DATA_CTL_B3),\n .DATA_CTL_B4 (DATA_CTL_B4),\n .DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE),\n .DRAM_TYPE (DRAM_TYPE),\n .BANK_WIDTH (BANK_WIDTH),\n .CK_WIDTH (CK_WIDTH),\n .COL_WIDTH (COL_WIDTH),\n .DM_WIDTH (DM_WIDTH),\n .DQ_WIDTH (DQ_WIDTH),\n .DQS_CNT_WIDTH (DQS_CNT_WIDTH),\n .DQS_WIDTH (DQS_WIDTH),\n .DRAM_WIDTH (DRAM_WIDTH),\n .PHYCTL_CMD_FIFO (PHYCTL_CMD_FIFO),\n .ROW_WIDTH (ROW_WIDTH),\n .AL (AL),\n .ADDR_CMD_MODE (ADDR_CMD_MODE),\n .BURST_MODE (BURST_MODE),\n .BURST_TYPE (BURST_TYPE),\n .CL (nCL),\n .CWL (nCWL),\n .tRFC (tRFC),\n .tREFI (tREFI),\n .tCK (tCK),\n .OUTPUT_DRV (OUTPUT_DRV),\n .RANKS (RANKS),\n .ODT_WIDTH (ODT_WIDTH),\n .REG_CTRL (REG_CTRL),\n .RTT_NOM (RTT_NOM),\n .RTT_WR (RTT_WR),\n .SLOT_1_CONFIG (SLOT_1_CONFIG),\n .WRLVL (WRLVL),\n .BANK_TYPE (BANK_TYPE),\n .DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE),\n .DATA_IO_IDLE_PWRDWN(DATA_IO_IDLE_PWRDWN),\n .IODELAY_GRP (IODELAY_GRP),\n .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),\n // Prevent the following simulation-related parameters from\n // being overridden for synthesis - for synthesis only the\n // default values of these parameters should be used\n // synthesis translate_off\n .SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),\n // synthesis translate_on\n .USE_CS_PORT (USE_CS_PORT),\n .USE_DM_PORT (USE_DM_PORT),\n .USE_ODT_PORT (USE_ODT_PORT),\n .MASTER_PHY_CTL (MASTER_PHY_CTL),\n .DEBUG_PORT (DEBUG_PORT),\n .IDELAY_ADJ (IDELAY_ADJ),\n .FINE_PER_BIT (FINE_PER_BIT),\n .CENTER_COMP_MODE (CENTER_COMP_MODE),\n .PI_VAL_ADJ (PI_VAL_ADJ),\n .TAPSPERKCLK (TAPSPERKCLK),\n .SKIP_CALIB (SKIP_CALIB),\n .FPGA_VOLT_TYPE (FPGA_VOLT_TYPE)\n )\n ddr_phy_top0\n (\n // Outputs\n .calib_rd_data_offset_0 (calib_rd_data_offset_0),\n .calib_rd_data_offset_1 (calib_rd_data_offset_1),\n .calib_rd_data_offset_2 (calib_rd_data_offset_2),\n .ddr_ck (ddr_ck),\n .ddr_ck_n (ddr_ck_n),\n .ddr_addr (ddr_addr),\n .ddr_ba (ddr_ba),\n .ddr_ras_n (ddr_ras_n),\n .ddr_cas_n (ddr_cas_n),\n .ddr_we_n (ddr_we_n),\n .ddr_cs_n (ddr_cs_n),\n .ddr_cke (ddr_cke),\n .ddr_odt (ddr_odt),\n .ddr_reset_n (ddr_reset_n),\n .ddr_parity (ddr_parity),\n .ddr_dm (ddr_dm),\n .dbg_calib_top (dbg_calib_top),\n .dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),\n .dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),\n .dbg_phy_rdlvl (dbg_phy_rdlvl),\n .dbg_phy_wrcal (dbg_phy_wrcal),\n .dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),\n .dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt),\n .dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),\n .dbg_rddata (dbg_rddata),\n .dbg_rdlvl_done (dbg_rdlvl_done),\n .dbg_rdlvl_err (dbg_rdlvl_err),\n .dbg_rdlvl_start (dbg_rdlvl_start),\n .dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),\n .dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),\n .dbg_wrlvl_done (dbg_wrlvl_done),\n .dbg_wrlvl_err (dbg_wrlvl_err),\n .dbg_wrlvl_start (dbg_wrlvl_start),\n .dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes),\n .dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes),\n .init_calib_complete (init_calib_complete_w),\n .init_wrcal_complete (init_wrcal_complete_w),\n .mc_address (mc_address),\n .mc_aux_out0 (mc_aux_out0),\n .mc_aux_out1 (mc_aux_out1),\n .mc_bank (mc_bank),\n .mc_cke (mc_cke),\n .mc_odt (mc_odt),\n .mc_cas_n (mc_cas_n),\n .mc_cmd (mc_cmd),\n .mc_cmd_wren (mc_cmd_wren),\n .mc_cas_slot (mc_cas_slot),\n .mc_cs_n (mc_cs_n),\n .mc_ctl_wren (mc_ctl_wren),\n .mc_data_offset (mc_data_offset),\n .mc_data_offset_1 (mc_data_offset_1),\n .mc_data_offset_2 (mc_data_offset_2),\n .mc_rank_cnt (mc_rank_cnt),\n .mc_ras_n (mc_ras_n),\n .mc_reset_n (mc_reset_n),\n .mc_we_n (mc_we_n),\n .mc_wrdata (mc_wrdata),\n .mc_wrdata_en (mc_wrdata_en),\n .mc_wrdata_mask (mc_wrdata_mask),\n .idle (idle),\n .mem_refclk (mem_refclk),\n .phy_mc_ctl_full (phy_mc_ctl_full),\n .phy_mc_cmd_full (phy_mc_cmd_full),\n .phy_mc_data_full (phy_mc_data_full),\n .phy_rd_data (phy_rd_data),\n .phy_rddata_valid (phy_rddata_valid),\n .pll_lock (pll_lock),\n .sync_pulse (sync_pulse),\n // Inouts\n .ddr_dqs (ddr_dqs),\n .ddr_dqs_n (ddr_dqs_n),\n .ddr_dq (ddr_dq),\n // Inputs\n .clk_ref (clk_ref),\n .freq_refclk (freq_refclk),\n .clk (clk),\n .clk_div2 (clk_div2),\n .rst_div2 (rst_div2),\n .mmcm_ps_clk (mmcm_ps_clk),\n .poc_sample_pd (poc_sample_pd),\n .rst (rst),\n .error (error),\n .rst_tg_mc (rst_tg_mc),\n .slot_0_present (slot_0_present),\n .slot_1_present (slot_1_present),\n .dbg_idel_up_all (dbg_idel_up_all),\n .dbg_idel_down_all (dbg_idel_down_all),\n .dbg_idel_up_cpt (dbg_idel_up_cpt),\n .dbg_idel_down_cpt (dbg_idel_down_cpt),\n .dbg_sel_idel_cpt (dbg_sel_idel_cpt),\n .dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt)\n\n ,.device_temp (device_temp)\n ,.tempmon_sample_en (tempmon_sample_en)\n ,.psen (psen)\n ,.psincdec (psincdec)\n ,.psdone (psdone)\n\n ,.calib_tap_req (calib_tap_req)\n ,.calib_tap_addr (calib_tap_addr)\n ,.calib_tap_load (calib_tap_load)\n ,.calib_tap_val (calib_tap_val)\n ,.calib_tap_load_done (calib_tap_load_done)\n\n ,.dbg_sel_pi_incdec (dbg_sel_pi_incdec)\n ,.dbg_sel_po_incdec (dbg_sel_po_incdec)\n ,.dbg_byte_sel (dbg_byte_sel)\n ,.dbg_pi_f_inc (dbg_pi_f_inc)\n ,.dbg_po_f_inc (dbg_po_f_inc)\n ,.dbg_po_f_stg23_sel (dbg_po_f_stg23_sel)\n ,.dbg_pi_f_dec (dbg_pi_f_dec)\n ,.dbg_po_f_dec (dbg_po_f_dec)\n ,.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt)\n ,.dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt)\n ,.dbg_rddata_valid (dbg_rddata_valid)\n ,.dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt)\n ,.dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt)\n ,.dbg_phy_wrlvl (dbg_phy_wrlvl)\n ,.ref_dll_lock (ref_dll_lock)\n ,.rst_phaser_ref (rst_phaser_ref)\n ,.iddr_rst (iddr_rst)\n ,.dbg_rd_data_offset (dbg_rd_data_offset)\n ,.dbg_phy_init (dbg_phy_init)\n ,.dbg_prbs_rdlvl (dbg_prbs_rdlvl)\n ,.dbg_dqs_found_cal (dbg_dqs_found_cal)\n ,.dbg_po_counter_read_val (dbg_po_counter_read_val)\n ,.dbg_pi_counter_read_val (dbg_pi_counter_read_val)\n ,.dbg_pi_phaselock_start (dbg_pi_phaselock_start)\n ,.dbg_pi_phaselocked_done (dbg_pi_phaselocked_done)\n ,.dbg_pi_phaselock_err (dbg_pi_phaselock_err)\n ,.dbg_pi_dqsfound_start (dbg_pi_dqsfound_start)\n ,.dbg_pi_dqsfound_done (dbg_pi_dqsfound_done)\n ,.dbg_pi_dqsfound_err (dbg_pi_dqsfound_err)\n ,.dbg_wrcal_start (dbg_wrcal_start)\n ,.dbg_wrcal_done (dbg_wrcal_done)\n ,.dbg_wrcal_err (dbg_wrcal_err)\n ,.dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal)\n ,.dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data)\n ,.dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start)\n ,.dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done)\n ,.prbs_final_dqs_tap_cnt_r (prbs_final_dqs_tap_cnt_r)\n ,.dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps)\n ,.dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps)\n ,.dbg_poc (dbg_poc[1023:0])\n );\n\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ip_top/mig_7series_v4_0_memc_ui_top_axi.v", "content": "//*****************************************************************************\n// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor : Xilinx\n// \\ \\ \\/ Version : 3.6\n// \\ \\ Application : MIG\n// / / Filename : memc_ui_top_axi.v\n// /___/ /\\ Date Last Modified : $Date: 2011/06/02 08:35:04 $\n// \\ \\ / \\ Date Created : Fri Oct 08 2010\n// \\___\\/\\___\\\n//\n// Device : 7 Series\n// Design Name : DDR2 SDRAM & DDR3 SDRAM\n// Purpose :\n// Top level memory interface block. Instantiates a clock and\n// reset generator, the memory controller, the phy and the\n// user interface blocks.\n// Reference :\n// Revision History :\n//*****************************************************************************\n\n`timescale 1 ps / 1 ps\n\n(* X_CORE_INFO = \"mig_7series_v4_0_ddr3_7Series, ddr3_if, 2016.2\" , CORE_GENERATION_INFO = \"ddr3_7Series,mig_7series_v4_0,{LANGUAGE=Verilog, SYNTHESIS_TOOL=Vivado, LEVEL=CONTROLLER, AXI_ENABLE=1, NO_OF_CONTROLLERS=1, INTERFACE_TYPE=DDR3, AXI_ENABLE=1, CLK_PERIOD=1112, PHY_RATIO=4, CLKIN_PERIOD=5004, VCCAUX_IO=2.0V, MEMORY_TYPE=COMP, MEMORY_PART=mt41j256m16xx-107, DQ_WIDTH=32, ECC=OFF, DATA_MASK=1, ORDERING=NORM, BURST_MODE=8, BURST_TYPE=SEQ, CA_MIRROR=OFF, OUTPUT_DRV=HIGH, USE_CS_PORT=1, USE_ODT_PORT=1, RTT_NOM=40, MEMORY_ADDRESS_MAP=ROW_BANK_COLUMN, REFCLK_FREQ=200, DEBUG_PORT=OFF, INTERNAL_VREF=0, SYSCLK_TYPE=NO_BUFFER, REFCLK_TYPE=USE_SYSTEM_CLOCK}\" *)\nmodule mig_7series_v4_0_memc_ui_top_axi #\n (\n parameter TCQ = 100,\n parameter DDR3_VDD_OP_VOLT = \"135\", // Voltage mode used for DDR3\n parameter PAYLOAD_WIDTH = 64,\n parameter ADDR_CMD_MODE = \"UNBUF\",\n parameter AL = \"0\", // Additive Latency option\n parameter BANK_WIDTH = 3, // # of bank bits\n parameter BM_CNT_WIDTH = 2, // Bank machine counter width\n parameter BURST_MODE = \"8\", // Burst length\n parameter BURST_TYPE = \"SEQ\", // Burst type\n parameter CA_MIRROR = \"OFF\", // C/A mirror opt for DDR3 dual rank\n parameter CK_WIDTH = 1, // # of CK/CK# outputs to memory\n parameter CL = 5,\n parameter COL_WIDTH = 12, // column address width\n parameter CMD_PIPE_PLUS1 = \"ON\", // add pipeline stage between MC and PHY\n parameter CS_WIDTH = 1, // # of unique CS outputs\n parameter CKE_WIDTH = 1, // # of cke outputs\n parameter CWL = 5,\n parameter DATA_WIDTH = 64,\n parameter DATA_BUF_ADDR_WIDTH = 5,\n parameter DATA_BUF_OFFSET_WIDTH = 1,\n parameter DDR2_DQSN_ENABLE = \"YES\", // Enable differential DQS for DDR2\n parameter DM_WIDTH = 8, // # of DM (data mask)\n parameter DQ_CNT_WIDTH = 6, // = ceil(log2(DQ_WIDTH))\n parameter DQ_WIDTH = 64, // # of DQ (data)\n parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))\n parameter DQS_WIDTH = 8, // # of DQS (strobe)\n parameter DRAM_TYPE = \"DDR3\",\n parameter DRAM_WIDTH = 8, // # of DQ per DQS\n parameter ECC = \"OFF\",\n parameter ECC_WIDTH = 8,\n parameter ECC_TEST = \"OFF\",\n parameter MC_ERR_ADDR_WIDTH = 31,\n parameter MASTER_PHY_CTL = 0, // The bank number where master PHY_CONTROL resides\n parameter nAL = 0, // Additive latency (in clk cyc)\n parameter nBANK_MACHS = 4,\n parameter nCK_PER_CLK = 2, // # of memory CKs per fabric CLK\n parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank\n parameter ORDERING = \"NORM\",\n parameter IBUF_LPWR_MODE = \"OFF\",\n parameter BANK_TYPE = \"HP_IO\", // # = \"HP_IO\", \"HPL_IO\", \"HR_IO\", \"HRL_IO\"\n parameter DATA_IO_PRIM_TYPE = \"DEFAULT\", // # = \"HP_LP\", \"HR_LP\", \"DEFAULT\"\n parameter DATA_IO_IDLE_PWRDWN = \"ON\", // \"ON\" or \"OFF\"\n parameter IODELAY_GRP0 = \"IODELAY_MIG0\",\n parameter IODELAY_GRP1 = \"IODELAY_MIG1\",\n parameter FPGA_SPEED_GRADE = 1,\n parameter OUTPUT_DRV = \"HIGH\",\n parameter REG_CTRL = \"OFF\",\n parameter RTT_NOM = \"60\",\n parameter RTT_WR = \"120\",\n parameter STARVE_LIMIT = 2,\n parameter tCK = 2500, // pS\n parameter tCKE = 10000, // pS\n parameter tFAW = 40000, // pS\n parameter tPRDI = 1_000_000, // pS\n parameter tRAS = 37500, // pS\n parameter tRCD = 12500, // pS\n parameter tREFI = 7800000, // pS\n parameter tRFC = 110000, // pS\n parameter tRP = 12500, // pS\n parameter tRRD = 10000, // pS\n parameter tRTP = 7500, // pS\n parameter tWTR = 7500, // pS\n parameter tZQI = 128_000_000, // nS\n parameter tZQCS = 64, // CKs\n parameter USER_REFRESH = \"OFF\", // Whether user manages REF\n parameter TEMP_MON_EN = \"ON\", // Enable/Disable tempmon\n parameter WRLVL = \"OFF\",\n parameter DEBUG_PORT = \"OFF\",\n parameter CAL_WIDTH = \"HALF\",\n parameter RANK_WIDTH = 1,\n parameter RANKS = 4,\n parameter ODT_WIDTH = 1,\n parameter ROW_WIDTH = 16, // DRAM address bus width\n parameter ADDR_WIDTH = 32,\n parameter APP_MASK_WIDTH = 8,\n parameter APP_DATA_WIDTH = 64,\n parameter [3:0] BYTE_LANES_B0 = 4'b1111,\n parameter [3:0] BYTE_LANES_B1 = 4'b1111,\n parameter [3:0] BYTE_LANES_B2 = 4'b1111,\n parameter [3:0] BYTE_LANES_B3 = 4'b1111,\n parameter [3:0] BYTE_LANES_B4 = 4'b1111,\n parameter [3:0] DATA_CTL_B0 = 4'hc,\n parameter [3:0] DATA_CTL_B1 = 4'hf,\n parameter [3:0] DATA_CTL_B2 = 4'hf,\n parameter [3:0] DATA_CTL_B3 = 4'h0,\n parameter [3:0] DATA_CTL_B4 = 4'h0,\n parameter [47:0] PHY_0_BITLANES = 48'h0000_0000_0000,\n parameter [47:0] PHY_1_BITLANES = 48'h0000_0000_0000,\n parameter [47:0] PHY_2_BITLANES = 48'h0000_0000_0000,\n\n // control/address/data pin mapping parameters\n parameter [143:0] CK_BYTE_MAP\n = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,\n parameter [191:0] ADDR_MAP\n = 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,\n parameter [35:0] BANK_MAP = 36'h000_000_000,\n parameter [11:0] CAS_MAP = 12'h000,\n parameter [7:0] CKE_ODT_BYTE_MAP = 8'h00,\n parameter [95:0] CKE_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter [95:0] ODT_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter CKE_ODT_AUX = \"FALSE\",\n parameter [119:0] CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,\n parameter [11:0] PARITY_MAP = 12'h000,\n parameter [11:0] RAS_MAP = 12'h000,\n parameter [11:0] WE_MAP = 12'h000,\n parameter [143:0] DQS_BYTE_MAP\n = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,\n parameter [95:0] DATA0_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter [95:0] DATA1_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter [95:0] DATA2_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter [95:0] DATA3_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter [95:0] DATA4_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter [95:0] DATA5_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter [95:0] DATA6_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter [95:0] DATA7_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter [95:0] DATA8_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter [95:0] DATA9_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter [95:0] DATA10_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter [95:0] DATA11_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter [95:0] DATA12_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter [95:0] DATA13_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter [95:0] DATA14_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter [95:0] DATA15_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter [95:0] DATA16_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter [95:0] DATA17_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter [107:0] MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,\n parameter [107:0] MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,\n\n parameter [7:0] SLOT_0_CONFIG = 8'b0000_0001,\n parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,\n parameter MEM_ADDR_ORDER = \"BANK_ROW_COLUMN\",\n // calibration Address. The address given below will be used for calibration\n // read and write operations.\n parameter [15:0] CALIB_ROW_ADD = 16'h0000, // Calibration row address\n parameter [11:0] CALIB_COL_ADD = 12'h000, // Calibration column address\n parameter [2:0] CALIB_BA_ADD = 3'h0, // Calibration bank address\n parameter SIM_BYPASS_INIT_CAL = \"OFF\",\n parameter REFCLK_FREQ = 300.0,\n parameter USE_CS_PORT = 1, // Support chip select output\n parameter USE_DM_PORT = 1, // Support data mask output\n parameter USE_ODT_PORT = 1, // Support ODT output\n parameter IDELAY_ADJ = \"ON\", //ON : IDELAY-1, OFF: No change\n parameter FINE_PER_BIT = \"ON\", //ON : Use per bit calib for complex rdlvl\n parameter CENTER_COMP_MODE = \"ON\", //ON: use PI stg2 tap compensation\n parameter PI_VAL_ADJ = \"ON\", //ON: PI stg2 tap -1 for centering\n parameter SKIP_CALIB = \"FALSE\",\n parameter TAPSPERKCLK = 56,\n parameter C_S_AXI_ID_WIDTH = 4,\n // Width of all master and slave ID signals.\n // # = >= 1.\n parameter C_S_AXI_ADDR_WIDTH = 30,\n // Width of S_AXI_AWADDR, S_AXI_ARADDR, M_AXI_AWADDR and\n // M_AXI_ARADDR for all SI/MI slots.\n // # = 32.\n parameter C_S_AXI_DATA_WIDTH = 32,\n // Width of WDATA and RDATA on SI slot.\n // Must be <= APP_DATA_WIDTH.\n // # = 32, 64, 128, 256.\n parameter C_S_AXI_SUPPORTS_NARROW_BURST = 1,\n // Indicates whether to instatiate upsizer\n // Range: 0, 1\n parameter C_RD_WR_ARB_ALGORITHM = \"RD_PRI_REG\",\n // Indicates the Arbitration\n // Allowed values - \"TDM\", \"ROUND_ROBIN\",\n // \"RD_PRI_REG\", \"RD_PRI_REG_STARVE_LIMIT\"\n parameter C_S_AXI_REG_EN0 = 20'h00000,\n // Instatiates register slices before upsizer.\n // The type of register is specified for each channel\n // in a vector. 4 bits per channel are used.\n // C_S_AXI_REG_EN0[03:00] = AW CHANNEL REGISTER SLICE\n // C_S_AXI_REG_EN0[07:04] = W CHANNEL REGISTER SLICE\n // C_S_AXI_REG_EN0[11:08] = B CHANNEL REGISTER SLICE\n // C_S_AXI_REG_EN0[15:12] = AR CHANNEL REGISTER SLICE\n // C_S_AXI_REG_EN0[20:16] = R CHANNEL REGISTER SLICE\n // Possible values for each channel are:\n //\n // 0 => BYPASS = The channel is just wired through the\n // module.\n // 1 => FWD = The master VALID and payload signals\n // are registrated.\n // 2 => REV = The slave ready signal is registrated\n // 3 => FWD_REV = Both FWD and REV\n // 4 => SLAVE_FWD = All slave side signals and master\n // VALID and payload are registrated.\n // 5 => SLAVE_RDY = All slave side signals and master\n // READY are registrated.\n // 6 => INPUTS = Slave and Master side inputs are\n // registrated.\n parameter C_S_AXI_REG_EN1 = 20'h00000,\n // Same as C_S_AXI_REG_EN0, but this register is after\n // the upsizer\n parameter C_S_AXI_CTRL_ADDR_WIDTH = 32,\n // Width of AXI-4-Lite address bus\n parameter C_S_AXI_CTRL_DATA_WIDTH = 32,\n // Width of AXI-4-Lite data buses\n parameter C_S_AXI_BASEADDR = 32'h0000_0000,\n // Base address of AXI4 Memory Mapped bus.\n parameter C_ECC_ONOFF_RESET_VALUE = 1,\n // Controls ECC on/off value at startup/reset\n parameter C_ECC_CE_COUNTER_WIDTH = 8,\n // The external memory to controller clock ratio.\n parameter FPGA_VOLT_TYPE = \"N\"\n )\n (\n // Clock and reset ports\n input clk,\n input clk_div2,\n input rst_div2,\n input [1:0] clk_ref,\n input mem_refclk ,\n input freq_refclk ,\n input pll_lock,\n input sync_pulse ,\n input mmcm_ps_clk,\n input poc_sample_pd,\n\n input rst,\n\n // memory interface ports\n inout [DQ_WIDTH-1:0] ddr_dq,\n inout [DQS_WIDTH-1:0] ddr_dqs_n,\n inout [DQS_WIDTH-1:0] ddr_dqs,\n output [ROW_WIDTH-1:0] ddr_addr,\n output [BANK_WIDTH-1:0] ddr_ba,\n output ddr_cas_n,\n output [CK_WIDTH-1:0] ddr_ck_n,\n output [CK_WIDTH-1:0] ddr_ck,\n output [CKE_WIDTH-1:0] ddr_cke,\n output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,\n output [DM_WIDTH-1:0] ddr_dm,\n output [ODT_WIDTH-1:0] ddr_odt,\n output ddr_ras_n,\n output ddr_reset_n,\n output ddr_parity,\n output ddr_we_n,\n\n output [BM_CNT_WIDTH-1:0] bank_mach_next,\n output [2*nCK_PER_CLK-1:0] app_ecc_multiple_err_o,\n output [2*nCK_PER_CLK-1:0] app_ecc_single_err,\n\n input app_sr_req,\n output app_sr_active,\n input app_ref_req,\n output app_ref_ack,\n input app_zq_req,\n output app_zq_ack,\n\n // Ports to be used with SKIP_CALIB defined\n output calib_tap_req,\n input [6:0] calib_tap_addr,\n input calib_tap_load,\n input [7:0] calib_tap_val,\n input calib_tap_load_done,\n\n // temperature monitor ports\n input [11:0] device_temp,\n //phase shift clock control\n output psen,\n output psincdec,\n input psdone,\n // debug logic ports\n input dbg_idel_down_all,\n input dbg_idel_down_cpt,\n input dbg_idel_up_all,\n input dbg_idel_up_cpt,\n input dbg_sel_all_idel_cpt,\n input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,\n output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt,\n output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt,\n output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect,\n output [2*nCK_PER_CLK*DQ_WIDTH-1:0] dbg_rddata,\n output [1:0] dbg_rdlvl_done,\n output [1:0] dbg_rdlvl_err,\n output [1:0] dbg_rdlvl_start,\n output [5:0] dbg_tap_cnt_during_wrlvl,\n output dbg_wl_edge_detect_valid,\n output dbg_wrlvl_done,\n output dbg_wrlvl_err,\n output dbg_wrlvl_start,\n output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,\n output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,\n\n input aresetn,\n // Slave Interface Write Address Ports\n input [C_S_AXI_ID_WIDTH-1:0] s_axi_awid,\n input [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,\n input [7:0] s_axi_awlen,\n input [2:0] s_axi_awsize,\n input [1:0] s_axi_awburst,\n input [0:0] s_axi_awlock,\n input [3:0] s_axi_awcache,\n input [2:0] s_axi_awprot,\n input [3:0] s_axi_awqos,\n input s_axi_awvalid,\n output s_axi_awready,\n // Slave Interface Write Data Ports\n input [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata,\n input [C_S_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,\n input s_axi_wlast,\n input s_axi_wvalid,\n output s_axi_wready,\n // Slave Interface Write Response Ports\n input s_axi_bready,\n output [C_S_AXI_ID_WIDTH-1:0] s_axi_bid,\n output [1:0] s_axi_bresp,\n output s_axi_bvalid,\n // Slave Interface Read Address Ports\n input [C_S_AXI_ID_WIDTH-1:0] s_axi_arid,\n input [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr,\n input [7:0] s_axi_arlen,\n input [2:0] s_axi_arsize,\n input [1:0] s_axi_arburst,\n input [0:0] s_axi_arlock,\n input [3:0] s_axi_arcache,\n input [2:0] s_axi_arprot,\n input [3:0] s_axi_arqos,\n input s_axi_arvalid,\n output s_axi_arready,\n // Slave Interface Read Data Ports\n input s_axi_rready,\n output [C_S_AXI_ID_WIDTH-1:0] s_axi_rid,\n output [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata,\n output [1:0] s_axi_rresp,\n output s_axi_rlast,\n output s_axi_rvalid,\n\n // AXI CTRL port\n input s_axi_ctrl_awvalid,\n output s_axi_ctrl_awready,\n input [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_awaddr,\n // Slave Interface Write Data Ports\n input s_axi_ctrl_wvalid,\n output s_axi_ctrl_wready,\n input [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_wdata,\n // Slave Interface Write Response Ports\n output s_axi_ctrl_bvalid,\n input s_axi_ctrl_bready,\n output [1:0] s_axi_ctrl_bresp,\n // Slave Interface Read Address Ports\n input s_axi_ctrl_arvalid,\n output s_axi_ctrl_arready,\n input [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_araddr,\n // Slave Interface Read Data Ports\n output s_axi_ctrl_rvalid,\n input s_axi_ctrl_rready,\n output [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_rdata,\n output [1:0] s_axi_ctrl_rresp,\n\n // Interrupt output\n output interrupt,\n\n output init_calib_complete,\n input dbg_sel_pi_incdec,\n input dbg_sel_po_incdec,\n input [DQS_CNT_WIDTH:0] dbg_byte_sel,\n input dbg_pi_f_inc,\n input dbg_pi_f_dec,\n input dbg_po_f_inc,\n input dbg_po_f_stg23_sel,\n input dbg_po_f_dec,\n output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt,\n output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt,\n output dbg_rddata_valid,\n output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt,\n output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt,\n output ref_dll_lock,\n input rst_phaser_ref,\n input iddr_rst,\n output [6*RANKS-1:0] dbg_rd_data_offset,\n output [255:0] dbg_calib_top,\n output [255:0] dbg_phy_wrlvl,\n output [255:0] dbg_phy_rdlvl,\n output [99:0] dbg_phy_wrcal,\n output [255:0] dbg_phy_init,\n output [255:0] dbg_prbs_rdlvl,\n output [255:0] dbg_dqs_found_cal,\n output [5:0] dbg_pi_counter_read_val,\n output [8:0] dbg_po_counter_read_val,\n output dbg_pi_phaselock_start,\n output dbg_pi_phaselocked_done,\n output dbg_pi_phaselock_err,\n output dbg_pi_dqsfound_start,\n output dbg_pi_dqsfound_done,\n output dbg_pi_dqsfound_err,\n output dbg_wrcal_start,\n output dbg_wrcal_done,\n output dbg_wrcal_err,\n output [11:0] dbg_pi_dqs_found_lanes_phy4lanes,\n output [11:0] dbg_pi_phase_locked_phy4lanes,\n output [6*RANKS-1:0] dbg_calib_rd_data_offset_1,\n output [6*RANKS-1:0] dbg_calib_rd_data_offset_2,\n output [5:0] dbg_data_offset,\n output [5:0] dbg_data_offset_1,\n output [5:0] dbg_data_offset_2,\n output dbg_oclkdelay_calib_start,\n output dbg_oclkdelay_calib_done,\n output [255:0] dbg_phy_oclkdelay_cal,\n output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data,\n output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_final_dqs_tap_cnt_r,\n output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps,\n output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps,\n output [1023:0] dbg_poc\n\n );\n\n localparam IODELAY_GRP = (tCK <= 1500)? IODELAY_GRP1 : IODELAY_GRP0;\n\n localparam INTERFACE = \"AXI4\";\n // Port Interface.\n // # = UI - User Interface,\n // = AXI4 - AXI4 Interface.\n localparam C_FAMILY = \"virtex7\";\n\n\n localparam C_MC_DATA_WIDTH_LCL = 2*nCK_PER_CLK*DATA_WIDTH ;\n\n// wire [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r;\n// wire [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps;\n// wire [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps;\n\n wire correct_en;\n wire [2*nCK_PER_CLK-1:0] raw_not_ecc;\n wire [2*nCK_PER_CLK-1:0] ecc_single;\n wire [2*nCK_PER_CLK-1:0] ecc_multiple;\n wire [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr;\n wire app_correct_en;\n wire app_correct_en_i;\n wire [2*nCK_PER_CLK-1:0] app_raw_not_ecc;\n wire [DQ_WIDTH/8-1:0] fi_xor_we;\n wire [DQ_WIDTH-1:0] fi_xor_wrdata;\n\n wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;\n wire wr_data_en;\n wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;\n wire [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;\n wire rd_data_en;\n wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;\n wire accept;\n wire accept_ns;\n wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;\n wire rd_data_end;\n wire use_addr;\n wire size;\n wire [ROW_WIDTH-1:0] row;\n wire [RANK_WIDTH-1:0] rank;\n wire hi_priority;\n wire [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr;\n wire [COL_WIDTH-1:0] col;\n wire [2:0] cmd;\n wire [BANK_WIDTH-1:0] bank;\n wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data;\n wire [2*nCK_PER_CLK*PAYLOAD_WIDTH/8-1:0] wr_data_mask;\n wire [APP_DATA_WIDTH-1:0] app_rd_data;\n wire app_rd_data_end;\n wire app_rd_data_valid;\n wire app_rdy;\n wire app_wdf_rdy;\n wire [ADDR_WIDTH-1:0] app_addr;\n wire [2:0] app_cmd;\n wire app_en;\n wire app_hi_pri;\n wire app_sz;\n wire [APP_DATA_WIDTH-1:0] app_wdf_data;\n\n wire [C_MC_DATA_WIDTH_LCL-1:0] app_wdf_data_axi_o;\n\n wire app_wdf_end;\n wire [APP_MASK_WIDTH-1:0] app_wdf_mask;\n\n wire [C_MC_DATA_WIDTH_LCL/8-1:0] app_wdf_mask_axi_o;\n wire app_wdf_wren;\n\n wire app_sr_req_i;\n wire app_sr_active_i;\n wire app_ref_req_i;\n wire app_ref_ack_i;\n wire app_zq_req_i;\n wire app_zq_ack_i;\n\n wire rst_tg_mc;\n wire error;\n wire init_wrcal_complete;\n reg reset /* synthesis syn_maxfan = 10 */;\n reg init_calib_complete_r;\n\n //***************************************************************************\n // Added a single register stage for the calib_done to fix timing\n //***************************************************************************\n\n always @(posedge clk)\n init_calib_complete_r <= init_calib_complete;\n\n always @(posedge clk)\n reset <= #TCQ (rst | rst_tg_mc);\n\n mig_7series_v4_0_mem_intfc #\n (\n .TCQ (TCQ),\n .DDR3_VDD_OP_VOLT (DDR3_VDD_OP_VOLT),\n .PAYLOAD_WIDTH (PAYLOAD_WIDTH),\n .ADDR_CMD_MODE (ADDR_CMD_MODE),\n .AL (AL),\n .BANK_WIDTH (BANK_WIDTH),\n .BM_CNT_WIDTH (BM_CNT_WIDTH),\n .BURST_MODE (BURST_MODE),\n .BURST_TYPE (BURST_TYPE),\n .CA_MIRROR (CA_MIRROR),\n .CK_WIDTH (CK_WIDTH),\n .COL_WIDTH (COL_WIDTH),\n .CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1),\n .CS_WIDTH (CS_WIDTH),\n .nCS_PER_RANK (nCS_PER_RANK),\n .CKE_WIDTH (CKE_WIDTH),\n .DATA_WIDTH (DATA_WIDTH),\n .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),\n .MASTER_PHY_CTL (MASTER_PHY_CTL),\n .DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH),\n .DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE),\n .DM_WIDTH (DM_WIDTH),\n .DQ_CNT_WIDTH (DQ_CNT_WIDTH),\n .DQ_WIDTH (DQ_WIDTH),\n .DQS_CNT_WIDTH (DQS_CNT_WIDTH),\n .DQS_WIDTH (DQS_WIDTH),\n .DRAM_TYPE (DRAM_TYPE),\n .DRAM_WIDTH (DRAM_WIDTH),\n .ECC (ECC),\n .ECC_WIDTH (ECC_WIDTH),\n .MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),\n .REFCLK_FREQ (REFCLK_FREQ),\n .nAL (nAL),\n .nBANK_MACHS (nBANK_MACHS),\n .nCK_PER_CLK (nCK_PER_CLK),\n .ORDERING (ORDERING),\n .OUTPUT_DRV (OUTPUT_DRV),\n .IBUF_LPWR_MODE (IBUF_LPWR_MODE),\n .BANK_TYPE (BANK_TYPE),\n .DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE),\n .DATA_IO_IDLE_PWRDWN (DATA_IO_IDLE_PWRDWN),\n .IODELAY_GRP (IODELAY_GRP),\n .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),\n .REG_CTRL (REG_CTRL),\n .RTT_NOM (RTT_NOM),\n .RTT_WR (RTT_WR),\n .CL (CL),\n .CWL (CWL),\n .tCK (tCK),\n .tCKE (tCKE),\n .tFAW (tFAW),\n .tPRDI (tPRDI),\n .tRAS (tRAS),\n .tRCD (tRCD),\n .tREFI (tREFI),\n .tRFC (tRFC),\n .tRP (tRP),\n .tRRD (tRRD),\n .tRTP (tRTP),\n .tWTR (tWTR),\n .tZQI (tZQI),\n .tZQCS (tZQCS),\n .USER_REFRESH (USER_REFRESH),\n .TEMP_MON_EN (TEMP_MON_EN),\n .WRLVL (WRLVL),\n .DEBUG_PORT (DEBUG_PORT),\n .CAL_WIDTH (CAL_WIDTH),\n .RANK_WIDTH (RANK_WIDTH),\n .RANKS (RANKS),\n .ODT_WIDTH (ODT_WIDTH),\n .ROW_WIDTH (ROW_WIDTH),\n .SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),\n .BYTE_LANES_B0 (BYTE_LANES_B0),\n .BYTE_LANES_B1 (BYTE_LANES_B1),\n .BYTE_LANES_B2 (BYTE_LANES_B2),\n .BYTE_LANES_B3 (BYTE_LANES_B3),\n .BYTE_LANES_B4 (BYTE_LANES_B4),\n .DATA_CTL_B0 (DATA_CTL_B0),\n .DATA_CTL_B1 (DATA_CTL_B1),\n .DATA_CTL_B2 (DATA_CTL_B2),\n .DATA_CTL_B3 (DATA_CTL_B3),\n .DATA_CTL_B4 (DATA_CTL_B4),\n .PHY_0_BITLANES (PHY_0_BITLANES),\n .PHY_1_BITLANES (PHY_1_BITLANES),\n .PHY_2_BITLANES (PHY_2_BITLANES),\n .CK_BYTE_MAP (CK_BYTE_MAP),\n .ADDR_MAP (ADDR_MAP),\n .BANK_MAP (BANK_MAP),\n .CAS_MAP (CAS_MAP),\n .CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),\n .CKE_MAP (CKE_MAP),\n .ODT_MAP (ODT_MAP),\n .CKE_ODT_AUX (CKE_ODT_AUX),\n .CS_MAP (CS_MAP),\n .PARITY_MAP (PARITY_MAP),\n .RAS_MAP (RAS_MAP),\n .WE_MAP (WE_MAP),\n .DQS_BYTE_MAP (DQS_BYTE_MAP),\n .DATA0_MAP (DATA0_MAP),\n .DATA1_MAP (DATA1_MAP),\n .DATA2_MAP (DATA2_MAP),\n .DATA3_MAP (DATA3_MAP),\n .DATA4_MAP (DATA4_MAP),\n .DATA5_MAP (DATA5_MAP),\n .DATA6_MAP (DATA6_MAP),\n .DATA7_MAP (DATA7_MAP),\n .DATA8_MAP (DATA8_MAP),\n .DATA9_MAP (DATA9_MAP),\n .DATA10_MAP (DATA10_MAP),\n .DATA11_MAP (DATA11_MAP),\n .DATA12_MAP (DATA12_MAP),\n .DATA13_MAP (DATA13_MAP),\n .DATA14_MAP (DATA14_MAP),\n .DATA15_MAP (DATA15_MAP),\n .DATA16_MAP (DATA16_MAP),\n .DATA17_MAP (DATA17_MAP),\n .MASK0_MAP (MASK0_MAP),\n .MASK1_MAP (MASK1_MAP),\n .SLOT_0_CONFIG (SLOT_0_CONFIG),\n .SLOT_1_CONFIG (SLOT_1_CONFIG),\n .CALIB_ROW_ADD (CALIB_ROW_ADD),\n .CALIB_COL_ADD (CALIB_COL_ADD),\n .CALIB_BA_ADD (CALIB_BA_ADD),\n .STARVE_LIMIT (STARVE_LIMIT),\n .USE_CS_PORT (USE_CS_PORT),\n .USE_DM_PORT (USE_DM_PORT),\n .USE_ODT_PORT (USE_ODT_PORT),\n .IDELAY_ADJ (IDELAY_ADJ),\n .FINE_PER_BIT (FINE_PER_BIT),\n .CENTER_COMP_MODE (CENTER_COMP_MODE),\n .PI_VAL_ADJ (PI_VAL_ADJ),\n .TAPSPERKCLK (TAPSPERKCLK),\n .SKIP_CALIB (SKIP_CALIB),\n .FPGA_VOLT_TYPE (FPGA_VOLT_TYPE)\n )\n mem_intfc0\n (\n .clk (clk),\n .clk_div2 (clk_div2),\n .rst_div2 (rst_div2),\n .clk_ref (tCK <= 1500 ? clk_ref[1] : clk_ref[0]),\n .mem_refclk (mem_refclk), //memory clock\n .freq_refclk (freq_refclk),\n .pll_lock (pll_lock),\n .sync_pulse (sync_pulse),\n .mmcm_ps_clk (mmcm_ps_clk),\n .poc_sample_pd (poc_sample_pd),\n .rst (rst),\n .error (error),\n .reset (reset),\n .rst_tg_mc (rst_tg_mc),\n\n .ddr_dq (ddr_dq),\n .ddr_dqs_n (ddr_dqs_n),\n .ddr_dqs (ddr_dqs),\n .ddr_addr (ddr_addr),\n .ddr_ba (ddr_ba),\n .ddr_cas_n (ddr_cas_n),\n .ddr_ck_n (ddr_ck_n),\n .ddr_ck (ddr_ck),\n .ddr_cke (ddr_cke),\n .ddr_cs_n (ddr_cs_n),\n .ddr_dm (ddr_dm),\n .ddr_odt (ddr_odt),\n .ddr_ras_n (ddr_ras_n),\n .ddr_reset_n (ddr_reset_n),\n .ddr_parity (ddr_parity),\n .ddr_we_n (ddr_we_n),\n\n .slot_0_present (SLOT_0_CONFIG),\n .slot_1_present (SLOT_1_CONFIG),\n\n .correct_en (correct_en),\n .bank (bank),\n .cmd (cmd),\n .col (col),\n .data_buf_addr (data_buf_addr),\n .wr_data (wr_data),\n .wr_data_mask (wr_data_mask),\n .rank (rank),\n .raw_not_ecc (raw_not_ecc),\n .row (row),\n .hi_priority (hi_priority),\n .size (size),\n .use_addr (use_addr),\n .accept (accept),\n .accept_ns (accept_ns),\n .ecc_single (ecc_single),\n .ecc_multiple (ecc_multiple),\n .ecc_err_addr (ecc_err_addr),\n .rd_data (rd_data),\n .rd_data_addr (rd_data_addr),\n .rd_data_en (rd_data_en),\n .rd_data_end (rd_data_end),\n .rd_data_offset (rd_data_offset),\n .wr_data_addr (wr_data_addr),\n .wr_data_en (wr_data_en),\n .wr_data_offset (wr_data_offset),\n .bank_mach_next (bank_mach_next),\n .init_calib_complete (init_calib_complete),\n .init_wrcal_complete (init_wrcal_complete),\n .app_sr_req (app_sr_req_i),\n .app_sr_active (app_sr_active_i),\n .app_ref_req (app_ref_req_i),\n .app_ref_ack (app_ref_ack_i),\n .app_zq_req (app_zq_req_i),\n .app_zq_ack (app_zq_ack_i),\n\n // skip calibration i/f\n .calib_tap_req (calib_tap_req),\n .calib_tap_load (calib_tap_load),\n .calib_tap_addr (calib_tap_addr),\n .calib_tap_val (calib_tap_val),\n .calib_tap_load_done (calib_tap_load_done),\n\n .device_temp (device_temp),\n .psen (psen),\n .psincdec (psincdec),\n .psdone (psdone),\n .fi_xor_we (fi_xor_we),\n .fi_xor_wrdata (fi_xor_wrdata),\n\n\n\n .dbg_idel_up_all (dbg_idel_up_all),\n .dbg_idel_down_all (dbg_idel_down_all),\n .dbg_idel_up_cpt (dbg_idel_up_cpt),\n .dbg_idel_down_cpt (dbg_idel_down_cpt),\n .dbg_sel_idel_cpt (dbg_sel_idel_cpt),\n .dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),\n .dbg_calib_top (dbg_calib_top),\n .dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),\n .dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),\n .dbg_phy_rdlvl (dbg_phy_rdlvl),\n .dbg_phy_wrcal (dbg_phy_wrcal),\n .dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),\n .dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt),\n .dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),\n .dbg_rddata (dbg_rddata),\n .dbg_rdlvl_done (dbg_rdlvl_done),\n .dbg_rdlvl_err (dbg_rdlvl_err),\n .dbg_rdlvl_start (dbg_rdlvl_start),\n .dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),\n .dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),\n .dbg_wrlvl_done (dbg_wrlvl_done),\n .dbg_wrlvl_err (dbg_wrlvl_err),\n .dbg_wrlvl_start (dbg_wrlvl_start),\n\n .dbg_sel_pi_incdec (dbg_sel_pi_incdec),\n .dbg_sel_po_incdec (dbg_sel_po_incdec),\n .dbg_byte_sel (dbg_byte_sel),\n .dbg_pi_f_inc (dbg_pi_f_inc),\n .dbg_pi_f_dec (dbg_pi_f_dec),\n .dbg_po_f_inc (dbg_po_f_inc),\n .dbg_po_f_stg23_sel (dbg_po_f_stg23_sel),\n .dbg_po_f_dec (dbg_po_f_dec),\n .dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),\n .dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),\n .dbg_rddata_valid (dbg_rddata_valid),\n .dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),\n .dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),\n .dbg_phy_wrlvl (dbg_phy_wrlvl),\n .dbg_pi_counter_read_val (dbg_pi_counter_read_val),\n .dbg_po_counter_read_val (dbg_po_counter_read_val),\n .ref_dll_lock (ref_dll_lock),\n .rst_phaser_ref (rst_phaser_ref),\n .iddr_rst (iddr_rst),\n .dbg_rd_data_offset (dbg_rd_data_offset),\n .dbg_phy_init (dbg_phy_init),\n .dbg_prbs_rdlvl (dbg_prbs_rdlvl),\n .dbg_dqs_found_cal (dbg_dqs_found_cal),\n .dbg_pi_phaselock_start (dbg_pi_phaselock_start),\n .dbg_pi_phaselocked_done (dbg_pi_phaselocked_done),\n .dbg_pi_phaselock_err (dbg_pi_phaselock_err),\n .dbg_pi_dqsfound_start (dbg_pi_dqsfound_start),\n .dbg_pi_dqsfound_done (dbg_pi_dqsfound_done),\n .dbg_pi_dqsfound_err (dbg_pi_dqsfound_err),\n .dbg_wrcal_start (dbg_wrcal_start),\n .dbg_wrcal_done (dbg_wrcal_done),\n .dbg_wrcal_err (dbg_wrcal_err),\n .dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes),\n .dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes),\n .dbg_calib_rd_data_offset_1 (dbg_calib_rd_data_offset_1),\n .dbg_calib_rd_data_offset_2 (dbg_calib_rd_data_offset_2),\n .dbg_data_offset (dbg_data_offset),\n .dbg_data_offset_1 (dbg_data_offset_1),\n .dbg_data_offset_2 (dbg_data_offset_2),\n .dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal),\n .dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data),\n .dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start),\n .dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done),\n .prbs_final_dqs_tap_cnt_r (dbg_prbs_final_dqs_tap_cnt_r),\n .dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps),\n .dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps),\n .dbg_poc (dbg_poc[1023:0])\n );\n\n\n generate\n if(ECC_TEST == \"ON\") begin\n if(DQ_WIDTH == 72) begin\n assign app_wdf_data = {app_wdf_data_axi_o[0+:(8*2*nCK_PER_CLK)],app_wdf_data_axi_o} ;\n assign app_wdf_mask = {app_wdf_mask_axi_o[0+:(2*nCK_PER_CLK)],app_wdf_mask_axi_o} ;\n end else begin\n end\n end else begin\n assign app_wdf_data = app_wdf_data_axi_o ;\n assign app_wdf_mask = app_wdf_mask_axi_o ;\n end\n endgenerate\n\n mig_7series_v4_0_ui_top #\n (\n .TCQ (TCQ),\n .APP_DATA_WIDTH (APP_DATA_WIDTH),\n .APP_MASK_WIDTH (APP_MASK_WIDTH),\n .BANK_WIDTH (BANK_WIDTH),\n .COL_WIDTH (COL_WIDTH),\n .CWL (CWL),\n .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),\n .ECC (ECC),\n .ECC_TEST (ECC_TEST),\n .nCK_PER_CLK (nCK_PER_CLK),\n .ORDERING (ORDERING),\n .RANKS (RANKS),\n .RANK_WIDTH (RANK_WIDTH),\n .ROW_WIDTH (ROW_WIDTH),\n .MEM_ADDR_ORDER (MEM_ADDR_ORDER)\n )\n u_ui_top\n (\n .wr_data_mask (wr_data_mask[APP_MASK_WIDTH-1:0]),\n .wr_data (wr_data[APP_DATA_WIDTH-1:0]),\n .use_addr (use_addr),\n .size (size),\n .row (row),\n .raw_not_ecc (raw_not_ecc),\n .rank (rank),\n .hi_priority (hi_priority),\n .data_buf_addr (data_buf_addr),\n .col (col),\n .cmd (cmd),\n .bank (bank),\n .app_wdf_rdy (app_wdf_rdy),\n .app_rdy (app_rdy),\n .app_rd_data_valid (app_rd_data_valid),\n .app_rd_data_end (app_rd_data_end),\n .app_rd_data (app_rd_data),\n .correct_en (correct_en),\n .wr_data_offset (wr_data_offset),\n .wr_data_en (wr_data_en),\n .wr_data_addr (wr_data_addr),\n .rst (reset),\n .rd_data_offset (rd_data_offset),\n .rd_data_end (rd_data_end),\n .rd_data_en (rd_data_en),\n .rd_data_addr (rd_data_addr),\n .rd_data (rd_data[APP_DATA_WIDTH-1:0]),\n .ecc_multiple (ecc_multiple),\n .ecc_single (ecc_single),\n .clk (clk),\n .app_wdf_wren (app_wdf_wren),\n .app_wdf_mask (app_wdf_mask),\n .app_wdf_end (app_wdf_end),\n .app_wdf_data (app_wdf_data),\n .app_sz (app_sz),\n .app_hi_pri (app_hi_pri),\n .app_en (app_en),\n .app_cmd (app_cmd),\n .app_addr (app_addr),\n .accept_ns (accept_ns),\n .accept (accept),\n// ECC ports\n .app_raw_not_ecc (app_raw_not_ecc),\n .app_ecc_multiple_err (app_ecc_multiple_err_o),\n .app_ecc_single_err (app_ecc_single_err),\n .app_correct_en (app_correct_en_i),\n .app_sr_req (app_sr_req),\n .sr_req (app_sr_req_i),\n .sr_active (app_sr_active_i),\n .app_sr_active (app_sr_active),\n .app_ref_req (app_ref_req),\n .ref_req (app_ref_req_i),\n .ref_ack (app_ref_ack_i),\n .app_ref_ack (app_ref_ack),\n .app_zq_req (app_zq_req),\n .zq_req (app_zq_req_i),\n .zq_ack (app_zq_ack_i),\n .app_zq_ack (app_zq_ack)\n );\n\n mig_7series_v4_0_axi_mc #\n (\n .C_FAMILY (C_FAMILY),\n .C_S_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),\n .C_S_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH),\n .C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),\n .C_MC_DATA_WIDTH (C_MC_DATA_WIDTH_LCL),\n .C_MC_ADDR_WIDTH (ADDR_WIDTH),\n .C_MC_BURST_MODE (BURST_MODE),\n .C_MC_nCK_PER_CLK (nCK_PER_CLK),\n .C_S_AXI_SUPPORTS_NARROW_BURST (C_S_AXI_SUPPORTS_NARROW_BURST),\n .C_RD_WR_ARB_ALGORITHM (C_RD_WR_ARB_ALGORITHM),\n .C_S_AXI_REG_EN0 (C_S_AXI_REG_EN0),\n .C_S_AXI_REG_EN1 (C_S_AXI_REG_EN1),\n .C_ECC (ECC)\n )\n u_axi_mc\n (\n .aclk (clk),\n .aresetn (aresetn),\n // Slave Interface Write Address Ports\n .s_axi_awid (s_axi_awid),\n .s_axi_awaddr (s_axi_awaddr),\n .s_axi_awlen (s_axi_awlen),\n .s_axi_awsize (s_axi_awsize),\n .s_axi_awburst (s_axi_awburst),\n .s_axi_awlock (s_axi_awlock),\n .s_axi_awcache (s_axi_awcache),\n .s_axi_awprot (s_axi_awprot),\n .s_axi_awqos (s_axi_awqos),\n .s_axi_awvalid (s_axi_awvalid),\n .s_axi_awready (s_axi_awready),\n // Slave Interface Write Data Ports\n .s_axi_wdata (s_axi_wdata),\n .s_axi_wstrb (s_axi_wstrb),\n .s_axi_wlast (s_axi_wlast),\n .s_axi_wvalid (s_axi_wvalid),\n .s_axi_wready (s_axi_wready),\n // Slave Interface Write Response Ports\n .s_axi_bid (s_axi_bid),\n .s_axi_bresp (s_axi_bresp),\n .s_axi_bvalid (s_axi_bvalid),\n .s_axi_bready (s_axi_bready),\n // Slave Interface Read Address Ports\n .s_axi_arid (s_axi_arid),\n .s_axi_araddr (s_axi_araddr),\n .s_axi_arlen (s_axi_arlen),\n .s_axi_arsize (s_axi_arsize),\n .s_axi_arburst (s_axi_arburst),\n .s_axi_arlock (s_axi_arlock),\n .s_axi_arcache (s_axi_arcache),\n .s_axi_arprot (s_axi_arprot),\n .s_axi_arqos (s_axi_arqos),\n .s_axi_arvalid (s_axi_arvalid),\n .s_axi_arready (s_axi_arready),\n // Slave Interface Read Data Ports\n .s_axi_rid (s_axi_rid),\n .s_axi_rdata (s_axi_rdata),\n .s_axi_rresp (s_axi_rresp),\n .s_axi_rlast (s_axi_rlast),\n .s_axi_rvalid (s_axi_rvalid),\n .s_axi_rready (s_axi_rready),\n\n // MC Master Interface\n //CMD PORT\n .mc_app_en (app_en),\n .mc_app_cmd (app_cmd),\n .mc_app_sz (app_sz),\n .mc_app_addr (app_addr),\n .mc_app_hi_pri (app_hi_pri),\n .mc_app_rdy (app_rdy),\n .mc_init_complete (init_calib_complete_r),\n\n //DATA PORT\n .mc_app_wdf_wren (app_wdf_wren),\n .mc_app_wdf_mask (app_wdf_mask_axi_o),\n .mc_app_wdf_data (app_wdf_data_axi_o),\n .mc_app_wdf_end (app_wdf_end),\n .mc_app_wdf_rdy (app_wdf_rdy),\n\n .mc_app_rd_valid (app_rd_data_valid),\n .mc_app_rd_data (app_rd_data),\n .mc_app_rd_end (app_rd_data_end),\n .mc_app_ecc_multiple_err (app_ecc_multiple_err_o)\n );\n\n generate\n if (ECC == \"ON\") begin : gen_axi_ctrl_top\n reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] dbg_rddata_r;\n\n mig_7series_v4_0_axi_ctrl_top #\n (\n .C_S_AXI_CTRL_ADDR_WIDTH (C_S_AXI_CTRL_ADDR_WIDTH) ,\n .C_S_AXI_CTRL_DATA_WIDTH (C_S_AXI_CTRL_DATA_WIDTH) ,\n .C_S_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH) ,\n .C_S_AXI_BASEADDR (C_S_AXI_BASEADDR) ,\n .C_ECC_TEST (ECC_TEST) ,\n .C_DQ_WIDTH (DQ_WIDTH) ,\n .C_ECC_WIDTH (ECC_WIDTH) ,\n .C_MEM_ADDR_ORDER (MEM_ADDR_ORDER) ,\n .C_BANK_WIDTH (BANK_WIDTH) ,\n .C_ROW_WIDTH (ROW_WIDTH) ,\n .C_COL_WIDTH (COL_WIDTH) ,\n .C_ECC_ONOFF_RESET_VALUE (C_ECC_ONOFF_RESET_VALUE) ,\n .C_ECC_CE_COUNTER_WIDTH (C_ECC_CE_COUNTER_WIDTH) ,\n .C_NCK_PER_CLK (nCK_PER_CLK) ,\n .C_MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH)\n )\n axi_ctrl_top_0\n (\n .aclk (clk) ,\n .aresetn (aresetn) ,\n .s_axi_awvalid (s_axi_ctrl_awvalid) ,\n .s_axi_awready (s_axi_ctrl_awready) ,\n .s_axi_awaddr (s_axi_ctrl_awaddr) ,\n .s_axi_wvalid (s_axi_ctrl_wvalid) ,\n .s_axi_wready (s_axi_ctrl_wready) ,\n .s_axi_wdata (s_axi_ctrl_wdata) ,\n .s_axi_bvalid (s_axi_ctrl_bvalid) ,\n .s_axi_bready (s_axi_ctrl_bready) ,\n .s_axi_bresp (s_axi_ctrl_bresp) ,\n .s_axi_arvalid (s_axi_ctrl_arvalid) ,\n .s_axi_arready (s_axi_ctrl_arready) ,\n .s_axi_araddr (s_axi_ctrl_araddr) ,\n .s_axi_rvalid (s_axi_ctrl_rvalid) ,\n .s_axi_rready (s_axi_ctrl_rready) ,\n .s_axi_rdata (s_axi_ctrl_rdata) ,\n .s_axi_rresp (s_axi_ctrl_rresp) ,\n .interrupt (interrupt) ,\n .init_complete (init_calib_complete_r) ,\n .ecc_single (ecc_single) ,\n .ecc_multiple (ecc_multiple) ,\n .ecc_err_addr (ecc_err_addr) ,\n .app_correct_en (app_correct_en) ,\n .dfi_rddata (dbg_rddata_r) ,\n .fi_xor_we (fi_xor_we) ,\n .fi_xor_wrdata (fi_xor_wrdata)\n );\n\n // dbg_rddata delayed one cycle to match ecc_*\n always @(posedge clk) begin\n dbg_rddata_r <= dbg_rddata;\n end\n\n if(ECC_TEST == \"ON\") begin\n assign app_raw_not_ecc = {2*nCK_PER_CLK{1'b1}};\n assign app_correct_en_i = 'b0 ;\n end else begin\n assign app_raw_not_ecc = {2*nCK_PER_CLK{1'b0}};\n assign app_correct_en_i = app_correct_en ;\n end\n end\n else begin : gen_no_axi_ctrl_top\n assign s_axi_ctrl_awready = 1'b0;\n assign s_axi_ctrl_wready = 1'b0;\n assign s_axi_ctrl_bvalid = 1'b0;\n assign s_axi_ctrl_bresp = 2'b0;\n assign s_axi_ctrl_arready = 1'b0;\n assign s_axi_ctrl_rvalid = 1'b0;\n assign s_axi_ctrl_rdata = {C_S_AXI_CTRL_DATA_WIDTH{1'b0}};\n assign s_axi_ctrl_rresp = 2'b0;\n assign interrupt = 1'b0;\n assign app_correct_en = 1'b1;\n assign app_raw_not_ecc = 4'b0;\n assign fi_xor_we = {DQ_WIDTH/8{1'b0}};\n assign fi_xor_wrdata = {DQ_WIDTH{1'b0}};\n end\n endgenerate\n\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_byte_group_io.v", "content": "/*****************************************************************\n-- (c) Copyright 2011 - 2014 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). A Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n\n//\n//\n// Owner: Gary Martin\n// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/byte_group_io.v#4 $\n// $Author: $\n// $DateTime: $\n// $Change: $\n// Description:\n// This verilog file is a paramertizable I/O termination for \n// the single byte lane. \n// to create a N byte-lane wide phy. \n//\n// History:\n// Date Engineer Description\n// 04/01/2010 G. Martin Initial Checkin.\n//\n//////////////////////////////////////////////////////////////////\n*****************************************************************/\n\n`timescale 1ps/1ps\n\nmodule mig_7series_v4_0_ddr_byte_group_io #(\n// bit lane existance\n parameter BITLANES = 12'b1111_1111_1111,\n parameter BITLANES_OUTONLY = 12'b0000_0000_0000,\n parameter PO_DATA_CTL = \"FALSE\",\n parameter OSERDES_DATA_RATE = \"DDR\",\n parameter OSERDES_DATA_WIDTH = 4,\n parameter IDELAYE2_IDELAY_TYPE = \"VARIABLE\",\n parameter IDELAYE2_IDELAY_VALUE = 00,\n parameter IODELAY_GRP = \"IODELAY_MIG\",\n parameter FPGA_SPEED_GRADE = 1,\n parameter real TCK = 2500.0,\n// local usage only, don't pass down\n parameter BUS_WIDTH = 12,\n parameter SYNTHESIS = \"FALSE\"\n )\n (\n input [9:0] mem_dq_in,\n output [BUS_WIDTH-1:0] mem_dq_out,\n output [BUS_WIDTH-1:0] mem_dq_ts,\n input mem_dqs_in,\n output mem_dqs_out,\n output mem_dqs_ts,\n output [(4*10)-1:0] iserdes_dout, // 2 extra 12-bit lanes not used\n output dqs_to_phaser,\n input iserdes_clk,\n input iserdes_clkb,\n input iserdes_clkdiv,\n input phy_clk,\n input rst,\n input oserdes_rst,\n input iserdes_rst,\n input [1:0] oserdes_dqs,\n input [1:0] oserdes_dqsts,\n input [(4*BUS_WIDTH)-1:0] oserdes_dq,\n input [1:0] oserdes_dqts,\n input oserdes_clk,\n input oserdes_clk_delayed,\n input oserdes_clkdiv,\n input idelay_inc,\n input idelay_ce,\n input idelay_ld,\n input idelayctrl_refclk,\n input [29:0] fine_delay ,\n input fine_delay_sel\n );\n\n\n\n/// INSTANCES\n\n\nlocalparam ISERDES_DQ_DATA_RATE = \"DDR\";\nlocalparam ISERDES_DQ_DATA_WIDTH = 4;\nlocalparam ISERDES_DQ_DYN_CLKDIV_INV_EN = \"FALSE\";\nlocalparam ISERDES_DQ_DYN_CLK_INV_EN = \"FALSE\";\nlocalparam ISERDES_DQ_INIT_Q1 = 1'b0;\nlocalparam ISERDES_DQ_INIT_Q2 = 1'b0;\nlocalparam ISERDES_DQ_INIT_Q3 = 1'b0;\nlocalparam ISERDES_DQ_INIT_Q4 = 1'b0;\nlocalparam ISERDES_DQ_INTERFACE_TYPE = \"MEMORY_DDR3\";\nlocalparam ISERDES_NUM_CE = 2;\nlocalparam ISERDES_DQ_IOBDELAY = \"IFD\";\nlocalparam ISERDES_DQ_OFB_USED = \"FALSE\";\nlocalparam ISERDES_DQ_SERDES_MODE = \"MASTER\";\nlocalparam ISERDES_DQ_SRVAL_Q1 = 1'b0;\nlocalparam ISERDES_DQ_SRVAL_Q2 = 1'b0;\nlocalparam ISERDES_DQ_SRVAL_Q3 = 1'b0;\nlocalparam ISERDES_DQ_SRVAL_Q4 = 1'b0;\n\nlocalparam IDELAY_FINEDELAY_USE = (TCK > 1500) ? \"FALSE\" : \"TRUE\";\n\nwire [BUS_WIDTH-1:0] data_in_dly;\nwire [BUS_WIDTH-1:0] oserdes_dq_buf;\nwire [BUS_WIDTH-1:0] oserdes_dqts_buf;\nwire oserdes_dqs_buf;\nwire oserdes_dqsts_buf;\nwire [9:0] data_in;\nwire tbyte_out;\nreg [29:0] fine_delay_r;\n\nassign mem_dq_out = oserdes_dq_buf;\nassign mem_dq_ts = oserdes_dqts_buf;\nassign data_in = mem_dq_in;\n\nassign mem_dqs_out = oserdes_dqs_buf;\nassign mem_dqs_ts = oserdes_dqsts_buf;\nassign dqs_to_phaser = mem_dqs_in;\n\nreg iserdes_clk_d;\n\nalways @(*) \n iserdes_clk_d = iserdes_clk;\n\nreg idelay_ld_rst;\nreg rst_r1;\nreg rst_r2;\nreg rst_r3;\nreg rst_r4;\n\nalways @(posedge phy_clk) begin\n rst_r1 <= #1 rst;\n rst_r2 <= #1 rst_r1;\n rst_r3 <= #1 rst_r2;\n rst_r4 <= #1 rst_r3;\nend\n\nalways @(posedge phy_clk) begin\n if (rst)\n idelay_ld_rst <= #1 1'b1;\n else if (rst_r4)\n idelay_ld_rst <= #1 1'b0;\nend \n\nalways @ (posedge phy_clk) begin\n if(rst)\n fine_delay_r <= #1 1'b0;\n else if(fine_delay_sel)\n fine_delay_r <= #1 fine_delay;\nend\n\n\ngenvar i;\n\ngenerate\n\nfor ( i = 0; i != 10 && PO_DATA_CTL == \"TRUE\" ; i=i+1) begin : input_\n if ( BITLANES[i] && !BITLANES_OUTONLY[i]) begin : iserdes_dq_\n\n ISERDESE2 #(\n .DATA_RATE ( ISERDES_DQ_DATA_RATE),\n .DATA_WIDTH ( ISERDES_DQ_DATA_WIDTH),\n .DYN_CLKDIV_INV_EN ( ISERDES_DQ_DYN_CLKDIV_INV_EN),\n .DYN_CLK_INV_EN ( ISERDES_DQ_DYN_CLK_INV_EN),\n .INIT_Q1 ( ISERDES_DQ_INIT_Q1),\n .INIT_Q2 ( ISERDES_DQ_INIT_Q2),\n .INIT_Q3 ( ISERDES_DQ_INIT_Q3),\n .INIT_Q4 ( ISERDES_DQ_INIT_Q4),\n .INTERFACE_TYPE ( ISERDES_DQ_INTERFACE_TYPE),\n .NUM_CE ( ISERDES_NUM_CE),\n .IOBDELAY ( ISERDES_DQ_IOBDELAY),\n .OFB_USED ( ISERDES_DQ_OFB_USED),\n .SERDES_MODE ( ISERDES_DQ_SERDES_MODE),\n .SRVAL_Q1 ( ISERDES_DQ_SRVAL_Q1),\n .SRVAL_Q2 ( ISERDES_DQ_SRVAL_Q2),\n .SRVAL_Q3 ( ISERDES_DQ_SRVAL_Q3),\n .SRVAL_Q4 ( ISERDES_DQ_SRVAL_Q4)\n )\n iserdesdq\n (\n .O (),\n .Q1 (iserdes_dout[4*i + 3]),\n .Q2 (iserdes_dout[4*i + 2]),\n .Q3 (iserdes_dout[4*i + 1]),\n .Q4 (iserdes_dout[4*i + 0]),\n .Q5 (),\n .Q6 (),\n .Q7 (),\n .Q8 (),\n .SHIFTOUT1 (),\n .SHIFTOUT2 (),\n \n .BITSLIP (1'b0),\n .CE1 (1'b1),\n .CE2 (1'b1),\n .CLK (iserdes_clk_d),\n .CLKB (!iserdes_clk_d),\n .CLKDIVP (iserdes_clkdiv),\n .CLKDIV (),\n .DDLY (data_in_dly[i]),\n .D (data_in[i]), // dedicated route to iob for debugging\n\t // or as needed, select with IOBDELAY\n .DYNCLKDIVSEL (1'b0),\n .DYNCLKSEL (1'b0),\n// NOTE: OCLK is not used in this design, but is required to meet \n// a design rule check in map and bitgen. Do not disconnect it.\n .OCLK (oserdes_clk),\n .OCLKB (),\n .OFB (),\n .RST (1'b0),\n// .RST (iserdes_rst),\n .SHIFTIN1 (1'b0),\n .SHIFTIN2 (1'b0)\n );\n\nlocalparam IDELAYE2_CINVCTRL_SEL = \"FALSE\";\nlocalparam IDELAYE2_DELAY_SRC = \"IDATAIN\";\nlocalparam IDELAYE2_HIGH_PERFORMANCE_MODE = \"TRUE\";\nlocalparam IDELAYE2_PIPE_SEL = \"FALSE\";\nlocalparam IDELAYE2_ODELAY_TYPE = \"FIXED\";\nlocalparam IDELAYE2_REFCLK_FREQUENCY = ((FPGA_SPEED_GRADE == 2 || FPGA_SPEED_GRADE == 3) && TCK <= 1500) ? 400.0 : \n (FPGA_SPEED_GRADE == 1 && TCK <= 1500) ? 300.0 : 200.0;\nlocalparam IDELAYE2_SIGNAL_PATTERN = \"DATA\";\nlocalparam IDELAYE2_FINEDELAY_IN = \"ADD_DLY\";\n\n if(IDELAY_FINEDELAY_USE == \"TRUE\") begin: idelay_finedelay_dq\n (* IODELAY_GROUP = IODELAY_GRP *)\n IDELAYE2_FINEDELAY #( \n .CINVCTRL_SEL ( IDELAYE2_CINVCTRL_SEL),\n .DELAY_SRC ( IDELAYE2_DELAY_SRC),\n .HIGH_PERFORMANCE_MODE ( IDELAYE2_HIGH_PERFORMANCE_MODE),\n .IDELAY_TYPE ( IDELAYE2_IDELAY_TYPE),\n .IDELAY_VALUE ( IDELAYE2_IDELAY_VALUE),\n .PIPE_SEL ( IDELAYE2_PIPE_SEL),\n .FINEDELAY ( IDELAYE2_FINEDELAY_IN),\n .REFCLK_FREQUENCY ( IDELAYE2_REFCLK_FREQUENCY ),\n .SIGNAL_PATTERN ( IDELAYE2_SIGNAL_PATTERN)\n )\n idelaye2\n (\n .CNTVALUEOUT (),\n .DATAOUT (data_in_dly[i]),\n .C (phy_clk), // automatically wired by ISE\n .CE (idelay_ce),\n .CINVCTRL (),\n .CNTVALUEIN (5'b00000), \n .DATAIN (1'b0),\n .IDATAIN (data_in[i]),\n .IFDLY (fine_delay_r[i*3+:3]),\n .INC (idelay_inc),\n .LD (idelay_ld | idelay_ld_rst),\n .LDPIPEEN (1'b0),\n .REGRST (rst) \n );\n end else begin : idelay_dq\n (* IODELAY_GROUP = IODELAY_GRP *)\n IDELAYE2 #(\n .CINVCTRL_SEL ( IDELAYE2_CINVCTRL_SEL),\n .DELAY_SRC ( IDELAYE2_DELAY_SRC),\n .HIGH_PERFORMANCE_MODE ( IDELAYE2_HIGH_PERFORMANCE_MODE),\n .IDELAY_TYPE ( IDELAYE2_IDELAY_TYPE),\n .IDELAY_VALUE ( IDELAYE2_IDELAY_VALUE),\n .PIPE_SEL ( IDELAYE2_PIPE_SEL),\n .REFCLK_FREQUENCY ( IDELAYE2_REFCLK_FREQUENCY ),\n .SIGNAL_PATTERN ( IDELAYE2_SIGNAL_PATTERN)\n )\n idelaye2\n (\n .CNTVALUEOUT (),\n .DATAOUT (data_in_dly[i]),\n .C (phy_clk), // automatically wired by ISE\n .CE (idelay_ce),\n .CINVCTRL (),\n .CNTVALUEIN (5'b00000), \n .DATAIN (1'b0),\n .IDATAIN (data_in[i]),\n .INC (idelay_inc),\n .LD (idelay_ld | idelay_ld_rst),\n .LDPIPEEN (1'b0),\n .REGRST (rst) \n );\n\n end\n end // iserdes_dq\n else begin \n assign iserdes_dout[4*i + 3] = 0;\n assign iserdes_dout[4*i + 2] = 0;\n assign iserdes_dout[4*i + 1] = 0;\n assign iserdes_dout[4*i + 0] = 0;\n end\nend // input_\nendgenerate\t\t\t// iserdes_dq_\n\nlocalparam OSERDES_DQ_DATA_RATE_OQ = OSERDES_DATA_RATE;\nlocalparam OSERDES_DQ_DATA_RATE_TQ = OSERDES_DQ_DATA_RATE_OQ;\nlocalparam OSERDES_DQ_DATA_WIDTH = OSERDES_DATA_WIDTH;\nlocalparam OSERDES_DQ_INIT_OQ = 1'b1;\nlocalparam OSERDES_DQ_INIT_TQ = 1'b1;\nlocalparam OSERDES_DQ_INTERFACE_TYPE = \"DEFAULT\";\nlocalparam OSERDES_DQ_ODELAY_USED = 0;\nlocalparam OSERDES_DQ_SERDES_MODE = \"MASTER\";\nlocalparam OSERDES_DQ_SRVAL_OQ = 1'b1;\nlocalparam OSERDES_DQ_SRVAL_TQ = 1'b1;\n// note: obuf used in control path case, no ts input so width irrelevant\nlocalparam OSERDES_DQ_TRISTATE_WIDTH = (OSERDES_DQ_DATA_RATE_OQ == \"DDR\") ? 4 : 1;\n\nlocalparam OSERDES_DQS_DATA_RATE_OQ = \"DDR\";\nlocalparam OSERDES_DQS_DATA_RATE_TQ = \"DDR\";\nlocalparam OSERDES_DQS_TRISTATE_WIDTH = 4;\t// this is always ddr\nlocalparam OSERDES_DQS_DATA_WIDTH = 4;\nlocalparam ODDR_CLK_EDGE = \"SAME_EDGE\";\nlocalparam OSERDES_TBYTE_CTL = \"TRUE\";\n\n\ngenerate \n\nlocalparam NUM_BITLANES = PO_DATA_CTL == \"TRUE\" ? 10 : BUS_WIDTH;\n\n if ( PO_DATA_CTL == \"TRUE\" ) begin : slave_ts\n OSERDESE2 #(\n .DATA_RATE_OQ (OSERDES_DQ_DATA_RATE_OQ),\n .DATA_RATE_TQ (OSERDES_DQ_DATA_RATE_TQ),\n .DATA_WIDTH (OSERDES_DQ_DATA_WIDTH),\n .INIT_OQ (OSERDES_DQ_INIT_OQ),\n .INIT_TQ (OSERDES_DQ_INIT_TQ),\n .SERDES_MODE (OSERDES_DQ_SERDES_MODE),\n .SRVAL_OQ (OSERDES_DQ_SRVAL_OQ),\n .SRVAL_TQ (OSERDES_DQ_SRVAL_TQ),\n .TRISTATE_WIDTH (OSERDES_DQ_TRISTATE_WIDTH),\n .TBYTE_CTL (\"TRUE\"),\n .TBYTE_SRC (\"TRUE\")\n )\n oserdes_slave_ts\n (\n .OFB (),\n .OQ (),\n .SHIFTOUT1 (),\t// not extended\n .SHIFTOUT2 (),\t// not extended\n .TFB (),\n .TQ (),\n .CLK (oserdes_clk),\n .CLKDIV (oserdes_clkdiv),\n .D1 (),\n .D2 (),\n .D3 (),\n .D4 (),\n .D5 (),\n .D6 (),\n .D7 (),\n .D8 (),\n .OCE (1'b1),\n .RST (oserdes_rst),\n .SHIFTIN1 (), // not extended\n .SHIFTIN2 (), // not extended\n .T1 (oserdes_dqts[0]),\n .T2 (oserdes_dqts[0]),\n .T3 (oserdes_dqts[1]),\n .T4 (oserdes_dqts[1]),\n .TCE (1'b1),\n .TBYTEOUT (tbyte_out),\n .TBYTEIN (tbyte_out)\n );\n end // slave_ts\n\n for (i = 0; i != NUM_BITLANES; i=i+1) begin : output_\n if ( BITLANES[i]) begin : oserdes_dq_\n\n if ( PO_DATA_CTL == \"TRUE\" ) begin : ddr\n\n OSERDESE2 #(\n .DATA_RATE_OQ (OSERDES_DQ_DATA_RATE_OQ),\n .DATA_RATE_TQ (OSERDES_DQ_DATA_RATE_TQ),\n .DATA_WIDTH (OSERDES_DQ_DATA_WIDTH),\n .INIT_OQ (OSERDES_DQ_INIT_OQ),\n .INIT_TQ (OSERDES_DQ_INIT_TQ),\n .SERDES_MODE (OSERDES_DQ_SERDES_MODE),\n .SRVAL_OQ (OSERDES_DQ_SRVAL_OQ),\n .SRVAL_TQ (OSERDES_DQ_SRVAL_TQ),\n .TRISTATE_WIDTH (OSERDES_DQ_TRISTATE_WIDTH),\n .TBYTE_CTL (OSERDES_TBYTE_CTL),\n .TBYTE_SRC (\"FALSE\")\n )\n oserdes_dq_i \n (\n .OFB (),\n .OQ (oserdes_dq_buf[i]),\n .SHIFTOUT1 (),\t// not extended\n .SHIFTOUT2 (),\t// not extended\n .TBYTEOUT (),\n .TFB (),\n .TQ (oserdes_dqts_buf[i]),\n .CLK (oserdes_clk),\n .CLKDIV (oserdes_clkdiv),\n .D1 (oserdes_dq[4 * i + 0]),\n .D2 (oserdes_dq[4 * i + 1]),\n .D3 (oserdes_dq[4 * i + 2]),\n .D4 (oserdes_dq[4 * i + 3]),\n .D5 (),\n .D6 (),\n .D7 (),\n .D8 (),\n .OCE (1'b1),\n .RST (oserdes_rst),\n .SHIFTIN1 (), // not extended\n .SHIFTIN2 (), // not extended\n .T1 (/*oserdes_dqts[0]*/),\n .T2 (/*oserdes_dqts[0]*/),\n .T3 (/*oserdes_dqts[1]*/),\n .T4 (/*oserdes_dqts[1]*/),\n .TCE (1'b1),\n .TBYTEIN (tbyte_out)\n );\n end\n else begin : sdr \n OSERDESE2 #(\n .DATA_RATE_OQ (OSERDES_DQ_DATA_RATE_OQ),\n .DATA_RATE_TQ (OSERDES_DQ_DATA_RATE_TQ),\n .DATA_WIDTH (OSERDES_DQ_DATA_WIDTH),\n .INIT_OQ (1'b0 /*OSERDES_DQ_INIT_OQ*/),\n .INIT_TQ (OSERDES_DQ_INIT_TQ),\n .SERDES_MODE (OSERDES_DQ_SERDES_MODE),\n .SRVAL_OQ (1'b0 /*OSERDES_DQ_SRVAL_OQ*/),\n .SRVAL_TQ (OSERDES_DQ_SRVAL_TQ),\n .TRISTATE_WIDTH (OSERDES_DQ_TRISTATE_WIDTH) \n )\n oserdes_dq_i \n (\n .OFB (),\n .OQ (oserdes_dq_buf[i]),\n .SHIFTOUT1 (),\t// not extended\n .SHIFTOUT2 (),\t// not extended\n .TBYTEOUT (),\n .TFB (),\n .TQ (),\n .CLK (oserdes_clk),\n .CLKDIV (oserdes_clkdiv),\n .D1 (oserdes_dq[4 * i + 0]),\n .D2 (oserdes_dq[4 * i + 1]),\n .D3 (oserdes_dq[4 * i + 2]),\n .D4 (oserdes_dq[4 * i + 3]),\n .D5 (),\n .D6 (),\n .D7 (),\n .D8 (),\n .OCE (1'b1),\n .RST (oserdes_rst),\n .SHIFTIN1 (), // not extended\n .SHIFTIN2 (), // not extended\n .T1 (),\n .T2 (),\n .T3 (),\n .T4 (),\n .TCE (1'b1),\n .TBYTEIN ()\n );\n end // ddr\n end // oserdes_dq_\n end // output_\n \nendgenerate\n\ngenerate\n\n if ( PO_DATA_CTL == \"TRUE\" ) begin : dqs_gen\n\n ODDR \n #(.DDR_CLK_EDGE (ODDR_CLK_EDGE))\n oddr_dqs \n (\n .Q (oserdes_dqs_buf),\n .D1 (oserdes_dqs[0]),\n .D2 (oserdes_dqs[1]),\n .C (oserdes_clk_delayed),\n .R (1'b0),\n .S (),\n .CE (1'b1)\n );\n\n ODDR\n #(.DDR_CLK_EDGE (ODDR_CLK_EDGE))\n oddr_dqsts \n ( .Q (oserdes_dqsts_buf),\n .D1 (oserdes_dqsts[0]),\n .D2 (oserdes_dqsts[0]),\n .C (oserdes_clk_delayed),\n .R (),\n .S (1'b0),\n .CE (1'b1)\n );\n\n end // sdr rate\n else begin:null_dqs \n end \nendgenerate\n\nendmodule\t\t\t// byte_group_io\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_byte_lane.v", "content": "/***********************************************************\n-- (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). A Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n\n//\n//\n// Owner: Gary Martin\n// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/byte_lane.v#4 $\n// $Author: gary $\n// $DateTime: 2010/05/11 18:05:17 $\n// $Change: 490882 $\n// Description:\n// This verilog file is a parameterizable single 10 or 12 bit byte lane.\n//\n// History:\n// Date Engineer Description\n// 04/01/2010 G. Martin Initial Checkin.\n//\n////////////////////////////////////////////////////////////\n***********************************************************/\n\n\n`timescale 1ps/1ps\n\n//`include \"phy.vh\"\n\nmodule mig_7series_v4_0_ddr_byte_lane #(\n// these are used to scale the index into phaser,calib,scan,mc vectors\n// to access fields used in this instance\n parameter ABCD = \"A\", // A,B,C, or D\n parameter PO_DATA_CTL = \"FALSE\",\n parameter BITLANES = 12'b1111_1111_1111,\n parameter BITLANES_OUTONLY = 12'b1111_1111_1111,\n parameter BYTELANES_DDR_CK = 24'b0010_0010_0010_0010_0010_0010,\n parameter RCLK_SELECT_LANE = \"B\",\n parameter PC_CLK_RATIO = 4,\n parameter USE_PRE_POST_FIFO = \"FALSE\",\n//OUT_FIFO\n parameter OF_ALMOST_EMPTY_VALUE = 1,\n parameter OF_ALMOST_FULL_VALUE = 1,\n parameter OF_ARRAY_MODE = \"UNDECLARED\",\n parameter OF_OUTPUT_DISABLE = \"FALSE\",\n parameter OF_SYNCHRONOUS_MODE = \"TRUE\",\n//IN_FIFO\n parameter IF_ALMOST_EMPTY_VALUE = 1,\n parameter IF_ALMOST_FULL_VALUE = 1,\n parameter IF_ARRAY_MODE = \"UNDECLARED\",\n parameter IF_SYNCHRONOUS_MODE = \"TRUE\",\n//PHASER_IN\n parameter PI_BURST_MODE = \"TRUE\",\n parameter PI_CLKOUT_DIV = 2,\n parameter PI_FREQ_REF_DIV = \"NONE\",\n parameter PI_FINE_DELAY = 1,\n parameter PI_OUTPUT_CLK_SRC = \"DELAYED_REF\" , //\"DELAYED_REF\",\n parameter PI_SEL_CLK_OFFSET = 0,\n\n parameter PI_SYNC_IN_DIV_RST = \"FALSE\",\n//PHASER_OUT\n parameter PO_CLKOUT_DIV = (PO_DATA_CTL == \"FALSE\") ? 4 : 2,\n parameter PO_FINE_DELAY = 0,\n parameter PO_COARSE_BYPASS = \"FALSE\",\n parameter PO_COARSE_DELAY = 0,\n parameter PO_OCLK_DELAY = 0,\n parameter PO_OCLKDELAY_INV = \"TRUE\",\n parameter PO_OUTPUT_CLK_SRC = \"DELAYED_REF\",\n parameter PO_SYNC_IN_DIV_RST = \"FALSE\",\n// OSERDES\n parameter OSERDES_DATA_RATE = \"DDR\",\n parameter OSERDES_DATA_WIDTH = 4,\n\n//IDELAY\n parameter IDELAYE2_IDELAY_TYPE = \"VARIABLE\",\n parameter IDELAYE2_IDELAY_VALUE = 00,\n parameter IODELAY_GRP = \"IODELAY_MIG\",\n parameter FPGA_SPEED_GRADE = 1,\n parameter BANK_TYPE = \"HP_IO\", // # = \"HP_IO\", \"HPL_IO\", \"HR_IO\", \"HRL_IO\"\n parameter real TCK = 0.00,\n parameter SYNTHESIS = \"FALSE\",\n\n// local constants, do not pass in from above\n parameter BUS_WIDTH = 12,\n parameter MSB_BURST_PEND_PO = 3,\n parameter MSB_BURST_PEND_PI = 7,\n parameter MSB_RANK_SEL_I = MSB_BURST_PEND_PI + 8,\n parameter PHASER_CTL_BUS_WIDTH = MSB_RANK_SEL_I + 1\n ,parameter CKE_ODT_AUX = \"FALSE\"\n ,parameter PI_DIV2_INCDEC = \"FALSE\"\n )(\n input rst,\n input phy_clk,\n input rst_pi_div2,\n input clk_div2,\n input freq_refclk,\n input mem_refclk,\n input idelayctrl_refclk,\n input sync_pulse,\n output [BUS_WIDTH-1:0] mem_dq_out,\n output [BUS_WIDTH-1:0] mem_dq_ts,\n input [9:0] mem_dq_in,\n output mem_dqs_out,\n output mem_dqs_ts,\n input mem_dqs_in,\n output [11:0] ddr_ck_out,\n output rclk,\n input if_empty_def,\n output if_a_empty,\n output if_empty,\n output if_a_full,\n output if_full,\n output of_a_empty,\n output of_empty,\n output of_a_full,\n output of_full,\n output pre_fifo_a_full,\n output [79:0] phy_din,\n input [79:0] phy_dout,\n input phy_cmd_wr_en,\n input phy_data_wr_en,\n input phy_rd_en,\n input [PHASER_CTL_BUS_WIDTH-1:0] phaser_ctl_bus,\n input idelay_inc,\n input idelay_ce,\n input idelay_ld,\n input if_rst,\n input [2:0] byte_rd_en_oth_lanes,\n input [1:0] byte_rd_en_oth_banks,\n output byte_rd_en,\n\n output po_coarse_overflow,\n output po_fine_overflow,\n output [8:0] po_counter_read_val,\n input po_fine_enable,\n input po_coarse_enable,\n input [1:0] po_en_calib,\n input po_fine_inc,\n input po_coarse_inc,\n input po_counter_load_en,\n input po_counter_read_en,\n input po_sel_fine_oclk_delay,\n input [8:0] po_counter_load_val,\n\n input [1:0] pi_en_calib,\n input pi_rst_dqs_find,\n input pi_fine_enable,\n input pi_fine_inc,\n input pi_counter_load_en,\n input pi_counter_read_en,\n input [5:0] pi_counter_load_val,\n\n output wire pi_iserdes_rst,\n output pi_phase_locked,\n output pi_fine_overflow,\n output [5:0] pi_counter_read_val,\n output wire pi_dqs_found,\n output dqs_out_of_range,\n input [29:0] fine_delay,\n input fine_delay_sel\n);\n\nlocalparam PHASER_INDEX =\n (ABCD==\"B\" ? 1 : (ABCD == \"C\") ? 2 : (ABCD == \"D\" ? 3 : 0));\nlocalparam L_OF_ARRAY_MODE =\n (OF_ARRAY_MODE != \"UNDECLARED\") ? OF_ARRAY_MODE :\n (PO_DATA_CTL == \"FALSE\" || PC_CLK_RATIO == 2) ? \"ARRAY_MODE_4_X_4\" : \"ARRAY_MODE_8_X_4\";\nlocalparam L_IF_ARRAY_MODE = (IF_ARRAY_MODE != \"UNDECLARED\") ? IF_ARRAY_MODE :\n (PC_CLK_RATIO == 2) ? \"ARRAY_MODE_4_X_4\" : \"ARRAY_MODE_4_X_8\";\n\nlocalparam L_OSERDES_DATA_RATE = (OSERDES_DATA_RATE != \"UNDECLARED\") ? OSERDES_DATA_RATE : ((PO_DATA_CTL == \"FALSE\" && PC_CLK_RATIO == 4) ? \"SDR\" : \"DDR\") ;\nlocalparam L_OSERDES_DATA_WIDTH = (OSERDES_DATA_WIDTH != \"UNDECLARED\") ? OSERDES_DATA_WIDTH : 4;\nlocalparam real L_FREQ_REF_PERIOD_NS = (TCK >= 2500.0) ? (TCK/(PI_FREQ_REF_DIV == \"DIV2\" ? 2 : 1)/1000.0) : TCK/1000.0; // DIV2 change\nlocalparam real L_MEM_REF_PERIOD_NS = TCK/1000.0;\nlocalparam real L_PHASE_REF_PERIOD_NS = TCK/1000.0;\nlocalparam ODDR_CLK_EDGE = \"SAME_EDGE\";\nlocalparam PO_DCD_CORRECTION = \"ON\";\nlocalparam [2:0] PO_DCD_SETTING = (PO_DCD_CORRECTION == \"ON\") ? 3'b111 : 3'b000;\n\nlocalparam DQS_AUTO_RECAL = (BANK_TYPE == \"HR_IO\" || BANK_TYPE == \"HRL_IO\" || (BANK_TYPE == \"HPL_IO\" && TCK >= 2500)) ? 1 : 0; // DIV2 change\nlocalparam DQS_FIND_PATTERN = (BANK_TYPE == \"HR_IO\" || BANK_TYPE == \"HRL_IO\" || (BANK_TYPE == \"HPL_IO\" && TCK >= 2500)) ? \"001\" : \"000\"; // DIV2 change\n\nwire [1:0] oserdes_dqs;\nwire [1:0] oserdes_dqs_ts;\nwire [1:0] oserdes_dq_ts;\n\nwire [3:0] of_q9;\nwire [3:0] of_q8;\nwire [3:0] of_q7;\nwire [7:0] of_q6;\nwire [7:0] of_q5;\nwire [3:0] of_q4;\nwire [3:0] of_q3;\nwire [3:0] of_q2;\nwire [3:0] of_q1;\nwire [3:0] of_q0;\nwire [7:0] of_d9;\nwire [7:0] of_d8;\nwire [7:0] of_d7;\nwire [7:0] of_d6;\nwire [7:0] of_d5;\nwire [7:0] of_d4;\nwire [7:0] of_d3;\nwire [7:0] of_d2;\nwire [7:0] of_d1;\nwire [7:0] of_d0;\n\nwire [7:0] if_q9;\nwire [7:0] if_q8;\nwire [7:0] if_q7;\nwire [7:0] if_q6;\nwire [7:0] if_q5;\nwire [7:0] if_q4;\nwire [7:0] if_q3;\nwire [7:0] if_q2;\nwire [7:0] if_q1;\nwire [7:0] if_q0;\nwire [3:0] if_d9;\nwire [3:0] if_d8;\nwire [3:0] if_d7;\nwire [3:0] if_d6;\nwire [3:0] if_d5;\nwire [3:0] if_d4;\nwire [3:0] if_d3;\nwire [3:0] if_d2;\nwire [3:0] if_d1;\nwire [3:0] if_d0;\n\nwire [3:0] dummy_i5;\nwire [3:0] dummy_i6;\n\nwire [48-1:0] of_dqbus;\nwire [10*4-1:0] iserdes_dout;\n\nwire iserdes_clk;\nwire iserdes_clkdiv;\nwire ififo_wr_enable;\nwire phy_rd_en_;\n\n\nwire dqs_to_phaser;\nwire phy_wr_en = ( PO_DATA_CTL == \"FALSE\" ) ? phy_cmd_wr_en : phy_data_wr_en;\nwire if_empty_;\nwire if_a_empty_;\nwire if_full_;\nwire if_a_full_;\nwire po_oserdes_rst;\nwire empty_post_fifo;\nreg [3:0] if_empty_r /* synthesis syn_maxfan = 3 */;\nwire [79:0] rd_data;\nreg [79:0] rd_data_r;\n\nreg ififo_rst = 1'b1;\nreg ofifo_rst = 1'b1;\n\nwire of_wren_pre;\nwire [79:0] pre_fifo_dout;\nwire pre_fifo_full;\nwire pre_fifo_rden;\nwire [5:0] ddr_ck_out_q;\nwire ififo_rd_en_in /* synthesis syn_maxfan = 10 */;\nwire oserdes_clkdiv;\nwire oserdes_clk_delayed;\nwire po_rd_enable;\n\nalways @(posedge phy_clk) begin\n ififo_rst <= #1 pi_rst_dqs_find | if_rst ;\n// reset only data o-fifos on reset of dqs_found\n ofifo_rst <= #1 (pi_rst_dqs_find & PO_DATA_CTL == \"TRUE\") | rst;\nend\n\n// IN_FIFO EMPTY->RDEN TIMING FIX:\n// Always read from IN_FIFO - it doesn't hurt to read from an empty FIFO\n// since the IN_FIFO read pointers are not incr'ed when the FIFO is empty\nassign #(25) phy_rd_en_ = 1'b1;\n//assign #(25) phy_rd_en_ = phy_rd_en;\n\ngenerate\nif ( PO_DATA_CTL == \"FALSE\" ) begin : if_empty_null\n assign if_empty = 0;\n assign if_a_empty = 0;\n assign if_full = 0;\n assign if_a_full = 0;\nend\nelse begin : if_empty_gen\n assign if_empty = empty_post_fifo;\n assign if_a_empty = if_a_empty_;\n assign if_full = if_full_;\n assign if_a_full = if_a_full_;\nend\nendgenerate\n\ngenerate\nif ( PO_DATA_CTL == \"FALSE\" ) begin : dq_gen_48\n assign of_dqbus[48-1:0] = {of_q6[7:4], of_q5[7:4], of_q9, of_q8, of_q7, of_q6[3:0], of_q5[3:0], of_q4, of_q3, of_q2, of_q1, of_q0};\n assign phy_din = 80'h0;\n assign byte_rd_en = 1'b1;\nend\nelse begin : dq_gen_40\n\n assign of_dqbus[40-1:0] = {of_q9, of_q8, of_q7, of_q6[3:0], of_q5[3:0], of_q4, of_q3, of_q2, of_q1, of_q0};\n assign ififo_rd_en_in = !if_empty_def ? ((&byte_rd_en_oth_banks) && (&byte_rd_en_oth_lanes) && byte_rd_en) :\n ((|byte_rd_en_oth_banks) || (|byte_rd_en_oth_lanes) || byte_rd_en);\n\n if (USE_PRE_POST_FIFO == \"TRUE\") begin : if_post_fifo_gen\n\n // IN_FIFO EMPTY->RDEN TIMING FIX:\n assign rd_data = {if_q9, if_q8, if_q7, if_q6, if_q5, if_q4, if_q3, if_q2, if_q1, if_q0};\n\n always @(posedge phy_clk) begin\n rd_data_r <= #(025) rd_data;\n if_empty_r[0] <= #(025) if_empty_;\n if_empty_r[1] <= #(025) if_empty_;\n if_empty_r[2] <= #(025) if_empty_;\n if_empty_r[3] <= #(025) if_empty_;\n end\n\n\n mig_7series_v4_0_ddr_if_post_fifo #\n (\n .TCQ (25), // simulation CK->Q delay\n .DEPTH (4), //2 // depth - account for up to 2 cycles of skew\n .WIDTH (80) // width\n )\n u_ddr_if_post_fifo\n (\n .clk (phy_clk),\n .rst (ififo_rst),\n .empty_in (if_empty_r),\n .rd_en_in (ififo_rd_en_in),\n .d_in (rd_data_r),\n .empty_out (empty_post_fifo),\n .byte_rd_en (byte_rd_en),\n .d_out (phy_din)\n );\n\n end\n else begin : phy_din_gen\n assign phy_din = {if_q9, if_q8, if_q7, if_q6, if_q5, if_q4, if_q3, if_q2, if_q1, if_q0};\n assign empty_post_fifo = if_empty_;\n end\n\nend\nendgenerate\n\n\nassign { if_d9, if_d8, if_d7, if_d6, if_d5, if_d4, if_d3, if_d2, if_d1, if_d0} = iserdes_dout;\n\n\nwire [1:0] rank_sel_i = ((phaser_ctl_bus[MSB_RANK_SEL_I :MSB_RANK_SEL_I -7] >> (PHASER_INDEX << 1)) & 2'b11);\n\n\n\n\ngenerate\n\nif ( USE_PRE_POST_FIFO == \"TRUE\" ) begin : of_pre_fifo_gen\n assign {of_d9, of_d8, of_d7, of_d6, of_d5, of_d4, of_d3, of_d2, of_d1, of_d0} = pre_fifo_dout;\n mig_7series_v4_0_ddr_of_pre_fifo #\n (\n .TCQ (25), // simulation CK->Q delay\n .DEPTH (9), // depth - set to 9 to accommodate flow control\n .WIDTH (80) // width\n )\n u_ddr_of_pre_fifo\n (\n .clk (phy_clk),\n .rst (ofifo_rst),\n .full_in (of_full),\n .wr_en_in (phy_wr_en),\n .d_in (phy_dout),\n .wr_en_out (of_wren_pre),\n .d_out (pre_fifo_dout),\n .afull (pre_fifo_a_full)\n );\nend\nelse begin\n// wire direct to ofifo\n assign {of_d9, of_d8, of_d7, of_d6, of_d5, of_d4, of_d3, of_d2, of_d1, of_d0} = phy_dout;\n assign of_wren_pre = phy_wr_en;\nend\n\n\nendgenerate\n\n///////////////////////////////////////////////////////////////////////////////\n// Synchronize pi_phase_locked to phy_clk domain\n///////////////////////////////////////////////////////////////////////////////\nwire pi_phase_locked_w;\nwire pi_dqs_found_w;\nwire [5:0] pi_counter_read_val_w;\ngenerate\n if (PI_DIV2_INCDEC == \"TRUE\") begin: phaser_in_div2_clk\n (* ASYNC_REG = \"TRUE\" *) reg pi_phase_locked_r1;\n (* ASYNC_REG = \"TRUE\" *) reg pi_phase_locked_r2;\n (* ASYNC_REG = \"TRUE\" *) reg pi_phase_locked_r3;\n reg pi_phase_locked_r4;\n\n (* ASYNC_REG = \"TRUE\" *) reg pi_dqs_found_r1;\n (* ASYNC_REG = \"TRUE\" *) reg pi_dqs_found_r2;\n (* ASYNC_REG = \"TRUE\" *) reg pi_dqs_found_r3;\n reg pi_dqs_found_r4;\n\n (* ASYNC_REG = \"TRUE\" *) reg [5:0] pi_counter_read_val_r1;\n (* ASYNC_REG = \"TRUE\" *) reg [5:0] pi_counter_read_val_r2;\n (* ASYNC_REG = \"TRUE\" *) reg [5:0] pi_counter_read_val_r3;\n reg [5:0] pi_counter_read_val_r4;\n\n always @ (posedge phy_clk) begin\n pi_phase_locked_r1 <= pi_phase_locked_w;\n pi_phase_locked_r2 <= pi_phase_locked_r1;\n pi_phase_locked_r3 <= pi_phase_locked_r2;\n pi_dqs_found_r1 <= pi_dqs_found_w;\n pi_dqs_found_r2 <= pi_dqs_found_r1;\n pi_dqs_found_r3 <= pi_dqs_found_r2;\n pi_counter_read_val_r1 <= pi_counter_read_val_w;\n pi_counter_read_val_r2 <= pi_counter_read_val_r1;\n pi_counter_read_val_r3 <= pi_counter_read_val_r2;\n end\n\n always @ (posedge phy_clk) begin\n if (rst)\n pi_phase_locked_r4 <= 1'b0;\n else if (pi_phase_locked_r2 == pi_phase_locked_r3)\n pi_phase_locked_r4 <= pi_phase_locked_r3;\n end\n\n always @ (posedge phy_clk) begin\n if (rst)\n pi_dqs_found_r4 <= 1'b0;\n else if (pi_dqs_found_r2 == pi_dqs_found_r3)\n pi_dqs_found_r4 <= pi_dqs_found_r3;\n end\n\n always @ (posedge phy_clk) begin\n if (rst)\n pi_counter_read_val_r4 <= 1'b0;\n else if (pi_counter_read_val_r2 == pi_counter_read_val_r3)\n pi_counter_read_val_r4 <= pi_counter_read_val_r3;\n end\n\n assign pi_phase_locked = pi_phase_locked_r4;\n assign pi_dqs_found = pi_dqs_found_r4;\n assign pi_counter_read_val = pi_counter_read_val_r4;\n\n end else begin: pahser_in_div4_clk\n assign pi_phase_locked = pi_phase_locked_w;\n assign pi_dqs_found = pi_dqs_found_w;\n assign pi_counter_read_val = pi_counter_read_val_w;\n end\nendgenerate\n\n\ngenerate\n\nif ( PO_DATA_CTL == \"TRUE\" || ((RCLK_SELECT_LANE==ABCD) && (CKE_ODT_AUX ==\"TRUE\"))) begin : phaser_in_gen\n\n//if (PI_DIV2_INCDEC == \"TRUE\") begin: phaser_in_div2_sys_clk\nif (PI_DIV2_INCDEC == \"TRUE\") begin\n\nPHASER_IN_PHY #(\n .BURST_MODE ( PI_BURST_MODE),\n .CLKOUT_DIV ( PI_CLKOUT_DIV),\n .DQS_AUTO_RECAL ( DQS_AUTO_RECAL),\n .DQS_FIND_PATTERN ( DQS_FIND_PATTERN),\n .SEL_CLK_OFFSET ( PI_SEL_CLK_OFFSET),\n .FINE_DELAY ( PI_FINE_DELAY),\n .FREQ_REF_DIV ( PI_FREQ_REF_DIV),\n .OUTPUT_CLK_SRC ( PI_OUTPUT_CLK_SRC),\n .SYNC_IN_DIV_RST ( PI_SYNC_IN_DIV_RST),\n .REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS),\n .MEMREFCLK_PERIOD ( L_MEM_REF_PERIOD_NS),\n .PHASEREFCLK_PERIOD ( L_PHASE_REF_PERIOD_NS)\n) phaser_in (\n .DQSFOUND (pi_dqs_found_w),\n .DQSOUTOFRANGE (dqs_out_of_range),\n .FINEOVERFLOW (pi_fine_overflow),\n .PHASELOCKED (pi_phase_locked_w),\n .ISERDESRST (pi_iserdes_rst),\n .ICLKDIV (iserdes_clkdiv),\n .ICLK (iserdes_clk),\n .COUNTERREADVAL (pi_counter_read_val_w),\n .RCLK (rclk),\n .WRENABLE (ififo_wr_enable),\n .BURSTPENDINGPHY (phaser_ctl_bus[MSB_BURST_PEND_PI - 3 + PHASER_INDEX]),\n .ENCALIBPHY (pi_en_calib),\n .FINEENABLE (pi_fine_enable),\n .FREQREFCLK (freq_refclk),\n .MEMREFCLK (mem_refclk),\n .RANKSELPHY (rank_sel_i),\n .PHASEREFCLK (dqs_to_phaser),\n .RSTDQSFIND (pi_rst_dqs_find),\n .RST (rst_pi_div2),\n .FINEINC (pi_fine_inc),\n .COUNTERLOADEN (pi_counter_load_en),\n .COUNTERREADEN (pi_counter_read_en),\n .COUNTERLOADVAL (pi_counter_load_val),\n .SYNCIN (sync_pulse),\n .SYSCLK (clk_div2)\n);\nend\n\nelse begin\n\nPHASER_IN_PHY #(\n .BURST_MODE ( PI_BURST_MODE),\n .CLKOUT_DIV ( PI_CLKOUT_DIV),\n .DQS_AUTO_RECAL ( DQS_AUTO_RECAL),\n .DQS_FIND_PATTERN ( DQS_FIND_PATTERN),\n .SEL_CLK_OFFSET ( PI_SEL_CLK_OFFSET),\n .FINE_DELAY ( PI_FINE_DELAY),\n .FREQ_REF_DIV ( PI_FREQ_REF_DIV),\n .OUTPUT_CLK_SRC ( PI_OUTPUT_CLK_SRC),\n .SYNC_IN_DIV_RST ( PI_SYNC_IN_DIV_RST),\n .REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS),\n .MEMREFCLK_PERIOD ( L_MEM_REF_PERIOD_NS),\n .PHASEREFCLK_PERIOD ( L_PHASE_REF_PERIOD_NS)\n) phaser_in (\n .DQSFOUND (pi_dqs_found_w),\n .DQSOUTOFRANGE (dqs_out_of_range),\n .FINEOVERFLOW (pi_fine_overflow),\n .PHASELOCKED (pi_phase_locked_w),\n .ISERDESRST (pi_iserdes_rst),\n .ICLKDIV (iserdes_clkdiv),\n .ICLK (iserdes_clk),\n .COUNTERREADVAL (pi_counter_read_val_w),\n .RCLK (rclk),\n .WRENABLE (ififo_wr_enable),\n .BURSTPENDINGPHY (phaser_ctl_bus[MSB_BURST_PEND_PI - 3 + PHASER_INDEX]),\n .ENCALIBPHY (pi_en_calib),\n .FINEENABLE (pi_fine_enable),\n .FREQREFCLK (freq_refclk),\n .MEMREFCLK (mem_refclk),\n .RANKSELPHY (rank_sel_i),\n .PHASEREFCLK (dqs_to_phaser),\n .RSTDQSFIND (pi_rst_dqs_find),\n .RST (rst),\n .FINEINC (pi_fine_inc),\n .COUNTERLOADEN (pi_counter_load_en),\n .COUNTERREADEN (pi_counter_read_en),\n .COUNTERLOADVAL (pi_counter_load_val),\n .SYNCIN (sync_pulse),\n .SYSCLK (phy_clk)\n);\n\nend\nend\nelse begin\n assign pi_dqs_found_w = 1'b1;\n// assign pi_dqs_out_of_range = 1'b0;\n assign pi_phase_locked_w = 1'b1;\nend\n\nendgenerate\n\nwire #0 phase_ref = freq_refclk;\n\nwire oserdes_clk;\n\n\nPHASER_OUT_PHY #(\n .CLKOUT_DIV ( PO_CLKOUT_DIV),\n .DATA_CTL_N ( PO_DATA_CTL ),\n .FINE_DELAY ( PO_FINE_DELAY),\n .COARSE_BYPASS ( PO_COARSE_BYPASS ),\n .COARSE_DELAY ( PO_COARSE_DELAY),\n .OCLK_DELAY ( PO_OCLK_DELAY),\n .OCLKDELAY_INV ( PO_OCLKDELAY_INV),\n .OUTPUT_CLK_SRC ( PO_OUTPUT_CLK_SRC),\n .SYNC_IN_DIV_RST ( PO_SYNC_IN_DIV_RST),\n .REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS),\n .PHASEREFCLK_PERIOD ( 1), // dummy, not used\n .PO ( PO_DCD_SETTING ),\n .MEMREFCLK_PERIOD ( L_MEM_REF_PERIOD_NS)\n) phaser_out (\n .COARSEOVERFLOW (po_coarse_overflow),\n .CTSBUS (oserdes_dqs_ts),\n .DQSBUS (oserdes_dqs),\n .DTSBUS (oserdes_dq_ts),\n .FINEOVERFLOW (po_fine_overflow),\n .OCLKDIV (oserdes_clkdiv),\n .OCLK (oserdes_clk),\n .OCLKDELAYED (oserdes_clk_delayed),\n .COUNTERREADVAL (po_counter_read_val),\n .BURSTPENDINGPHY (phaser_ctl_bus[MSB_BURST_PEND_PO -3 + PHASER_INDEX]),\n .ENCALIBPHY (po_en_calib),\n .RDENABLE (po_rd_enable),\n .FREQREFCLK (freq_refclk),\n .MEMREFCLK (mem_refclk),\n .PHASEREFCLK (/*phase_ref*/),\n .RST (rst),\n .OSERDESRST (po_oserdes_rst),\n .COARSEENABLE (po_coarse_enable),\n .FINEENABLE (po_fine_enable),\n .COARSEINC (po_coarse_inc),\n .FINEINC (po_fine_inc),\n .SELFINEOCLKDELAY (po_sel_fine_oclk_delay),\n .COUNTERLOADEN (po_counter_load_en),\n .COUNTERREADEN (po_counter_read_en),\n .COUNTERLOADVAL (po_counter_load_val),\n .SYNCIN (sync_pulse),\n .SYSCLK (phy_clk)\n);\n\n\ngenerate\n\nif (PO_DATA_CTL == \"TRUE\") begin : in_fifo_gen\n\nIN_FIFO #(\n .ALMOST_EMPTY_VALUE ( IF_ALMOST_EMPTY_VALUE ),\n .ALMOST_FULL_VALUE ( IF_ALMOST_FULL_VALUE ),\n .ARRAY_MODE ( L_IF_ARRAY_MODE),\n .SYNCHRONOUS_MODE ( IF_SYNCHRONOUS_MODE)\n) in_fifo (\n .ALMOSTEMPTY (if_a_empty_),\n .ALMOSTFULL (if_a_full_),\n .EMPTY (if_empty_),\n .FULL (if_full_),\n .Q0 (if_q0),\n .Q1 (if_q1),\n .Q2 (if_q2),\n .Q3 (if_q3),\n .Q4 (if_q4),\n .Q5 (if_q5),\n .Q6 (if_q6),\n .Q7 (if_q7),\n .Q8 (if_q8),\n .Q9 (if_q9),\n//===\n .D0 (if_d0),\n .D1 (if_d1),\n .D2 (if_d2),\n .D3 (if_d3),\n .D4 (if_d4),\n .D5 ({dummy_i5,if_d5}),\n .D6 ({dummy_i6,if_d6}),\n .D7 (if_d7),\n .D8 (if_d8),\n .D9 (if_d9),\n .RDCLK (phy_clk),\n .RDEN (phy_rd_en_),\n .RESET (ififo_rst),\n .WRCLK (iserdes_clkdiv),\n .WREN (ififo_wr_enable)\n);\nend\n\nendgenerate\n\n\n\nOUT_FIFO #(\n .ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),\n .ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),\n .ARRAY_MODE (L_OF_ARRAY_MODE),\n .OUTPUT_DISABLE (OF_OUTPUT_DISABLE),\n .SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE)\n) out_fifo (\n .ALMOSTEMPTY (of_a_empty),\n .ALMOSTFULL (of_a_full),\n .EMPTY (of_empty),\n .FULL (of_full),\n .Q0 (of_q0),\n .Q1 (of_q1),\n .Q2 (of_q2),\n .Q3 (of_q3),\n .Q4 (of_q4),\n .Q5 (of_q5),\n .Q6 (of_q6),\n .Q7 (of_q7),\n .Q8 (of_q8),\n .Q9 (of_q9),\n .D0 (of_d0),\n .D1 (of_d1),\n .D2 (of_d2),\n .D3 (of_d3),\n .D4 (of_d4),\n .D5 (of_d5),\n .D6 (of_d6),\n .D7 (of_d7),\n .D8 (of_d8),\n .D9 (of_d9),\n .RDCLK (oserdes_clkdiv),\n .RDEN (po_rd_enable),\n .RESET (ofifo_rst),\n .WRCLK (phy_clk),\n .WREN (of_wren_pre)\n);\n\n\nmig_7series_v4_0_ddr_byte_group_io #\n (\n .PO_DATA_CTL (PO_DATA_CTL),\n .BITLANES (BITLANES),\n .BITLANES_OUTONLY (BITLANES_OUTONLY),\n .OSERDES_DATA_RATE (L_OSERDES_DATA_RATE),\n .OSERDES_DATA_WIDTH (L_OSERDES_DATA_WIDTH),\n .IODELAY_GRP (IODELAY_GRP),\n .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),\n .IDELAYE2_IDELAY_TYPE (IDELAYE2_IDELAY_TYPE),\n .IDELAYE2_IDELAY_VALUE (IDELAYE2_IDELAY_VALUE),\n .TCK (TCK),\n .SYNTHESIS (SYNTHESIS)\n )\n ddr_byte_group_io\n (\n .mem_dq_out (mem_dq_out),\n .mem_dq_ts (mem_dq_ts),\n .mem_dq_in (mem_dq_in),\n .mem_dqs_in (mem_dqs_in),\n .mem_dqs_out (mem_dqs_out),\n .mem_dqs_ts (mem_dqs_ts),\n .rst (rst),\n .oserdes_rst (po_oserdes_rst),\n .iserdes_rst (pi_iserdes_rst ),\n .iserdes_dout (iserdes_dout),\n .dqs_to_phaser (dqs_to_phaser),\n .phy_clk (phy_clk),\n .iserdes_clk (iserdes_clk),\n .iserdes_clkb (!iserdes_clk),\n .iserdes_clkdiv (iserdes_clkdiv),\n .idelay_inc (idelay_inc),\n .idelay_ce (idelay_ce),\n .idelay_ld (idelay_ld),\n .idelayctrl_refclk (idelayctrl_refclk),\n .oserdes_clk (oserdes_clk),\n .oserdes_clk_delayed (oserdes_clk_delayed),\n .oserdes_clkdiv (oserdes_clkdiv),\n .oserdes_dqs ({oserdes_dqs[1], oserdes_dqs[0]}),\n .oserdes_dqsts ({oserdes_dqs_ts[1], oserdes_dqs_ts[0]}),\n .oserdes_dq (of_dqbus),\n .oserdes_dqts ({oserdes_dq_ts[1], oserdes_dq_ts[0]}),\n .fine_delay (fine_delay),\n .fine_delay_sel (fine_delay_sel)\n );\n\ngenvar i;\ngenerate\n for (i = 0; i <= 5; i = i+1) begin : ddr_ck_gen_loop\n if (PO_DATA_CTL== \"FALSE\" && (BYTELANES_DDR_CK[i*4+PHASER_INDEX])) begin : ddr_ck_gen\n ODDR #(.DDR_CLK_EDGE (ODDR_CLK_EDGE))\n ddr_ck (\n .C (oserdes_clk),\n .R (1'b0),\n .S (),\n .D1 (1'b0),\n .D2 (1'b1),\n .CE (1'b1),\n .Q (ddr_ck_out_q[i])\n );\n OBUFDS ddr_ck_obuf (.I(ddr_ck_out_q[i]), .O(ddr_ck_out[i*2]), .OB(ddr_ck_out[i*2+1]));\n end // ddr_ck_gen\n else begin : ddr_ck_null\n assign ddr_ck_out[i*2+1:i*2] = 2'b0;\n end\n end // ddr_ck_gen_loop\nendgenerate\n\nendmodule // byte_lane\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_calib_top.v", "content": "//*****************************************************************************\n// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor: Xilinx\n// \\ \\ \\/ Version: %version\n// \\ \\ Application: MIG\n// / / Filename: ddr_calib_top.v\n// /___/ /\\ Date Last Modified: $Date: 2011/06/02 08:35:06 $\n// \\ \\ / \\ Date Created: Aug 03 2009\n// \\___\\/\\___\\\n//\n//Device: 7 Series\n//Design Name: DDR3 SDRAM\n//Purpose:\n//Purpose:\n// Top-level for memory physical layer (PHY) interface\n// NOTES:\n// 1. Need to support multiple copies of CS outputs\n// 2. DFI_DRAM_CKE_DISABLE not supported\n//\n//Reference:\n//Revision History:\n//*****************************************************************************\n\n/******************************************************************************\n**$Id: ddr_calib_top.v,v 1.1 2011/06/02 08:35:06 mishra Exp $\n**$Date: 2011/06/02 08:35:06 $\n**$Author: mishra $\n**$Revision: 1.1 $\n**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_calib_top.v,v $\n******************************************************************************/\n\n`timescale 1ps/1ps\n\nmodule mig_7series_v4_0_ddr_calib_top #\n (\n parameter TCQ = 100,\n parameter nCK_PER_CLK = 2, // # of memory clocks per CLK\n parameter tCK = 2500, // DDR3 SDRAM clock period\n parameter DDR3_VDD_OP_VOLT = \"135\", // Voltage mode used for DDR3\n parameter CLK_PERIOD = 3333, // Internal clock period (in ps)\n parameter N_CTL_LANES = 3, // # of control byte lanes in the PHY\n parameter DRAM_TYPE = \"DDR3\", // Memory I/F type: \"DDR3\", \"DDR2\"\n parameter PRBS_WIDTH = 8, // The PRBS sequence is 2^PRBS_WIDTH\n parameter HIGHEST_LANE = 4,\n parameter HIGHEST_BANK = 3,\n parameter BANK_TYPE = \"HP_IO\", // # = \"HP_IO\", \"HPL_IO\", \"HR_IO\", \"HRL_IO\"\n // five fields, one per possible I/O bank, 4 bits in each field,\n // 1 per lane data=1/ctl=0\n parameter DATA_CTL_B0 = 4'hc,\n parameter DATA_CTL_B1 = 4'hf,\n parameter DATA_CTL_B2 = 4'hf,\n parameter DATA_CTL_B3 = 4'hf,\n parameter DATA_CTL_B4 = 4'hf,\n // defines the byte lanes in I/O banks being used in the interface\n // 1- Used, 0- Unused\n parameter BYTE_LANES_B0 = 4'b1111,\n parameter BYTE_LANES_B1 = 4'b0000,\n parameter BYTE_LANES_B2 = 4'b0000,\n parameter BYTE_LANES_B3 = 4'b0000,\n parameter BYTE_LANES_B4 = 4'b0000,\n parameter DQS_BYTE_MAP\n = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,\n parameter CTL_BYTE_LANE = 8'hE4, // Control byte lane map\n parameter CTL_BANK = 3'b000, // Bank used for control byte lanes\n // Slot Conifg parameters\n parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,\n // DRAM bus widths\n parameter BANK_WIDTH = 2, // # of bank bits\n parameter CA_MIRROR = \"OFF\", // C/A mirror opt for DDR3 dual rank\n parameter COL_WIDTH = 10, // column address width\n parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank\n parameter DQ_WIDTH = 64, // # of DQ (data)\n parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))\n parameter DQS_WIDTH = 8, // # of DQS (strobe)\n parameter DRAM_WIDTH = 8, // # of DQ per DQS\n parameter ROW_WIDTH = 14, // DRAM address bus width\n parameter RANKS = 1, // # of memory ranks in the interface\n parameter CS_WIDTH = 1, // # of CS# signals in the interface\n parameter CKE_WIDTH = 1, // # of cke outputs\n parameter DDR2_DQSN_ENABLE = \"YES\", // Enable differential DQS for DDR2\n parameter PER_BIT_DESKEW = \"ON\",\n // calibration Address. The address given below will be used for calibration\n // read and write operations.\n parameter NUM_DQSFOUND_CAL = 1020, // # of iteration of DQSFOUND calib\n parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address\n parameter CALIB_COL_ADD = 12'h000, // Calibration column address\n parameter CALIB_BA_ADD = 3'h0, // Calibration bank address\n // DRAM mode settings\n parameter AL = \"0\", // Additive Latency option\n parameter TEST_AL = \"0\", // Additive Latency for internal use\n parameter ADDR_CMD_MODE = \"1T\", // ADDR/CTRL timing: \"2T\", \"1T\"\n parameter BURST_MODE = \"8\", // Burst length\n parameter BURST_TYPE = \"SEQ\", // Burst type\n parameter nCL = 5, // Read CAS latency (in clk cyc)\n parameter nCWL = 5, // Write CAS latency (in clk cyc)\n parameter tRFC = 110000, // Refresh-to-command delay\n parameter tREFI = 7800000, // pS Refresh-to-Refresh delay\n parameter OUTPUT_DRV = \"HIGH\", // DRAM reduced output drive option\n parameter REG_CTRL = \"ON\", // \"ON\" for registered DIMM\n parameter RTT_NOM = \"60\", // ODT Nominal termination value\n parameter RTT_WR = \"60\", // ODT Write termination value\n parameter USE_ODT_PORT = 0, // 0 - No ODT output from FPGA\n // 1 - ODT output from FPGA\n parameter WRLVL = \"OFF\", // Enable write leveling\n parameter PRE_REV3ES = \"OFF\", // Delay O/Ps using Phaser_Out fine dly\n parameter POC_USE_METASTABLE_SAMP = \"FALSE\",\n\n // Simulation /debug options\n parameter SIM_INIT_OPTION = \"NONE\", // Performs all initialization steps\n parameter SIM_CAL_OPTION = \"NONE\", // Performs all calibration steps\n parameter CKE_ODT_AUX = \"FALSE\",\n parameter IDELAY_ADJ = \"ON\",\n parameter FINE_PER_BIT = \"ON\",\n parameter CENTER_COMP_MODE = \"ON\",\n parameter PI_VAL_ADJ = \"ON\",\n parameter TAPSPERKCLK = 56,\n parameter DEBUG_PORT = \"OFF\", // Enable debug port\n parameter SKIP_CALIB = \"FALSE\",\n parameter PI_DIV2_INCDEC = \"TRUE\"\n )\n (\n input clk, // Internal (logic) clock\n input rst, // Reset sync'ed to CLK\n // Slot present inputs\n input [7:0] slot_0_present,\n input [7:0] slot_1_present,\n // Hard PHY signals\n // From PHY Ctrl Block\n input phy_ctl_ready,\n input phy_ctl_full,\n input phy_cmd_full,\n input phy_data_full,\n // To PHY Ctrl Block\n output write_calib,\n output read_calib,\n output calib_ctl_wren,\n output calib_cmd_wren,\n output [1:0] calib_seq,\n output [3:0] calib_aux_out,\n output [nCK_PER_CLK -1:0] calib_cke,\n output [1:0] calib_odt,\n output [2:0] calib_cmd,\n output calib_wrdata_en,\n output [1:0] calib_rank_cnt,\n output [1:0] calib_cas_slot,\n output [5:0] calib_data_offset_0,\n output [5:0] calib_data_offset_1,\n output [5:0] calib_data_offset_2,\n output [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address,\n output [nCK_PER_CLK*BANK_WIDTH-1:0]phy_bank,\n output [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n,\n output [nCK_PER_CLK-1:0] phy_ras_n,\n output [nCK_PER_CLK-1:0] phy_cas_n,\n output [nCK_PER_CLK-1:0] phy_we_n,\n output phy_reset_n,\n // To hard PHY wrapper\n output reg [5:0] calib_sel/* synthesis syn_maxfan = 10 */,\n output reg calib_in_common/* synthesis syn_maxfan = 10 */,\n output reg [HIGHEST_BANK-1:0] calib_zero_inputs/* synthesis syn_maxfan = 10 */,\n output reg [HIGHEST_BANK-1:0] calib_zero_ctrl,\n output phy_if_empty_def,\n output reg phy_if_reset,\n// output reg ck_addr_ctl_delay_done,\n // From DQS Phaser_In\n input pi_phaselocked,\n input pi_phase_locked_all,\n input pi_found_dqs,\n input pi_dqs_found_all,\n input [HIGHEST_LANE-1:0] pi_dqs_found_lanes,\n input [5:0] pi_counter_read_val,\n // To DQS Phaser_In\n output [HIGHEST_BANK-1:0] pi_rst_stg1_cal,\n output pi_en_stg2_f,\n output pi_stg2_f_incdec,\n output pi_stg2_load,\n output [5:0] pi_stg2_reg_l,\n // To DQ IDELAY\n output idelay_ce,\n output idelay_inc,\n output idelay_ld,\n // To DQS Phaser_Out\n output [2:0] po_sel_stg2stg3 /* synthesis syn_maxfan = 3 */,\n output [2:0] po_stg2_c_incdec /* synthesis syn_maxfan = 3 */,\n output [2:0] po_en_stg2_c /* synthesis syn_maxfan = 3 */,\n output [2:0] po_stg2_f_incdec /* synthesis syn_maxfan = 3 */,\n output [2:0] po_en_stg2_f /* synthesis syn_maxfan = 3 */,\n output po_counter_load_en,\n input [8:0] po_counter_read_val,\n // To command Phaser_Out\n input phy_if_empty,\n input [4:0] idelaye2_init_val,\n input [5:0] oclkdelay_init_val,\n\n input tg_err,\n output rst_tg_mc,\n // Write data to OUT_FIFO\n output [2*nCK_PER_CLK*DQ_WIDTH-1:0]phy_wrdata,\n // To CNTVALUEIN input of DQ IDELAYs for perbit de-skew\n output [5*RANKS*DQ_WIDTH-1:0] dlyval_dq,\n // IN_FIFO read enable during write leveling, write calibration,\n // and read leveling\n // Read data from hard PHY fans out to mc and calib logic\n input[2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata,\n // To MC\n output [6*RANKS-1:0] calib_rd_data_offset_0,\n output [6*RANKS-1:0] calib_rd_data_offset_1,\n output [6*RANKS-1:0] calib_rd_data_offset_2,\n output phy_rddata_valid,\n output calib_writes,\n (* max_fanout = 50 *) output reg init_calib_complete/* synthesis syn_maxfan = 10 */,\n output init_wrcal_complete,\n output pi_phase_locked_err,\n output pi_dqsfound_err,\n output wrcal_err,\n input pd_out,\n // input mmcm_ps_clk, //phase shift clock\n // input oclkdelay_fb_clk, //Write DQS feedback clk\n //phase shift clock control\n output psen,\n output psincdec,\n input psdone,\n input poc_sample_pd,\n\n // Ports to be used when SKIP_CALIB=\"TRUE\"\n output reg calib_tap_req,\n input [6:0] calib_tap_addr,\n input calib_tap_load,\n input [7:0] calib_tap_val,\n input calib_tap_load_done,\n\n // Debug Port\n output dbg_pi_phaselock_start,\n output dbg_pi_dqsfound_start,\n output dbg_pi_dqsfound_done,\n output dbg_wrcal_start,\n output dbg_wrcal_done,\n output dbg_wrlvl_start,\n output dbg_wrlvl_done,\n output dbg_wrlvl_err,\n output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt,\n output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt,\n output [255:0] dbg_phy_wrlvl,\n output [5:0] dbg_tap_cnt_during_wrlvl,\n output dbg_wl_edge_detect_valid,\n output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect,\n\n // Write Calibration Logic\n output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,\n output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,\n output [99:0] dbg_phy_wrcal,\n\n // Read leveling logic\n output [1:0] dbg_rdlvl_start,\n output [1:0] dbg_rdlvl_done,\n output [1:0] dbg_rdlvl_err,\n output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt,\n output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt,\n output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt,\n output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt,\n\n // Delay control\n input [11:0] device_temp,\n input tempmon_sample_en,\n input dbg_sel_pi_incdec,\n input dbg_sel_po_incdec,\n input [DQS_CNT_WIDTH:0] dbg_byte_sel,\n input dbg_pi_f_inc,\n input dbg_pi_f_dec,\n input dbg_po_f_inc,\n input dbg_po_f_stg23_sel,\n input dbg_po_f_dec,\n input dbg_idel_up_all,\n input dbg_idel_down_all,\n input dbg_idel_up_cpt,\n input dbg_idel_down_cpt,\n input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,\n input dbg_sel_all_idel_cpt,\n output [255:0] dbg_phy_rdlvl, // Read leveling calibration\n output [255:0] dbg_calib_top, // General PHY debug\n output dbg_oclkdelay_calib_start,\n output dbg_oclkdelay_calib_done,\n output [255:0] dbg_phy_oclkdelay_cal,\n output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data,\n output [255:0] dbg_phy_init,\n output [255:0] dbg_prbs_rdlvl,\n output [255:0] dbg_dqs_found_cal,\n output [1023:0] dbg_poc,\n\n output [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r,\n output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps,\n output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps,\n output reg [DQS_CNT_WIDTH:0] byte_sel_cnt,\n output [DRAM_WIDTH-1:0] fine_delay_incdec_pb, //fine_delay decreament per bit\n output fine_delay_sel\n );\n\n function integer clogb2 (input integer size);\n begin\n size = size - 1;\n for (clogb2=1; size>1; clogb2=clogb2+1)\n size = size >> 1;\n end\n endfunction\n\n// Advance ODELAY of DQ by extra 0.25*tCK (quarter clock cycle) to center\n// align DQ and DQS on writes. Round (up or down) value to nearest integer\n// localparam integer SHIFT_TBY4_TAP\n// = (CLK_PERIOD + (nCK_PER_CLK*(1000000/(REFCLK_FREQ*64))*2)-1) /\n// (nCK_PER_CLK*(1000000/(REFCLK_FREQ*64))*4);\n\n// Calculate number of slots in the system\n localparam nSLOTS = 1 + (|SLOT_1_CONFIG ? 1 : 0);\n\n localparam OCAL_EN = ((SIM_CAL_OPTION == \"FAST_CAL\") || (tCK >= 2500) || (SKIP_CALIB == \"TRUE\")) ? \"OFF\" : \"ON\"; //DIV2 change\n\n // Different CTL_LANES value for DDR2. In DDR2 during DQS found all\n // the add,ctl & data phaser out fine delays will be adjusted.\n // In DDR3 only the add/ctrl lane delays will be adjusted\n localparam DQS_FOUND_N_CTL_LANES = (DRAM_TYPE == \"DDR3\") ? N_CTL_LANES : 1;\n\n localparam DQSFOUND_CAL = (BANK_TYPE == \"HR_IO\" || BANK_TYPE == \"HRL_IO\" || (BANK_TYPE == \"HPL_IO\" && tCK >= 2500)) ? \"LEFT\" : \"RIGHT\"; // DIV2 change IO Bank used for Memory I/F: \"LEFT\", \"RIGHT\"\n\n localparam FIXED_VICTIM = (SIM_CAL_OPTION == \"NONE\") ? \"FALSE\" : \"TRUE\";\n localparam VCCO_PAT_EN = 1; // Enable VCCO pattern during calibration\n localparam VCCAUX_PAT_EN = 1; // Enable VCCAUX pattern during calibration\n localparam ISI_PAT_EN = 1; // Enable VCCO pattern during calibration\n\n //Per-bit deskew for higher freqency (>800Mhz)\n //localparam FINE_DELAY = (tCK < 1250) ? \"ON\" : \"OFF\";\n\n //BYPASS\n localparam BYPASS_COMPLEX_RDLVL = ((tCK > 2500) || (SKIP_CALIB == \"TRUE\")) ? \"TRUE\": \"FALSE\"; //\"TRUE\";\n localparam BYPASS_COMPLEX_OCAL = \"TRUE\";\n //localparam BYPASS_COMPLEX_OCAL = ((DRAM_TYPE == \"DDR2\") || (nCK_PER_CLK == 2) || (OCAL_EN == \"OFF\")) ? \"TRUE\" : \"FALSE\";\n\n // 8*tREFI in ps is divided by the fabric clock period in ps\n // 270 fabric clock cycles is subtracted to account for PRECHARGE, WR, RD times\n localparam REFRESH_TIMER = (8*tREFI/(tCK*nCK_PER_CLK)) - 270;\n\n localparam REFRESH_TIMER_WIDTH = clogb2(REFRESH_TIMER);\n\n wire [2*8*nCK_PER_CLK-1:0] prbs_seed;\n //wire [2*8*nCK_PER_CLK-1:0] prbs_out;\n wire [8*DQ_WIDTH-1:0] prbs_out;\n wire [7:0] prbs_rise0;\n wire [7:0] prbs_fall0;\n wire [7:0] prbs_rise1;\n wire [7:0] prbs_fall1;\n wire [7:0] prbs_rise2;\n wire [7:0] prbs_fall2;\n wire [7:0] prbs_rise3;\n wire [7:0] prbs_fall3;\n //wire [2*8*nCK_PER_CLK-1:0] prbs_o;\n wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o;\n wire dqsfound_retry;\n wire dqsfound_retry_done;\n wire phy_rddata_en;\n wire prech_done;\n wire rdlvl_stg1_done;\n reg rdlvl_stg1_done_r1;\n wire pi_dqs_found_done;\n wire rdlvl_stg1_err;\n wire pi_dqs_found_err;\n wire wrcal_pat_resume;\n wire wrcal_resume_w;\n wire rdlvl_prech_req;\n wire rdlvl_last_byte_done;\n wire rdlvl_stg1_start;\n wire rdlvl_stg1_rank_done;\n wire rdlvl_assrt_common;\n wire pi_dqs_found_start;\n wire pi_dqs_found_rank_done;\n wire wl_sm_start;\n wire wrcal_start;\n wire wrcal_rd_wait;\n wire wrcal_prech_req;\n wire wrcal_pat_err;\n wire wrcal_done;\n wire wrlvl_done;\n wire wrlvl_err;\n wire wrlvl_start;\n wire ck_addr_cmd_delay_done;\n wire po_ck_addr_cmd_delay_done;\n wire pi_calib_done;\n wire detect_pi_found_dqs;\n wire [5:0] rd_data_offset_0;\n wire [5:0] rd_data_offset_1;\n wire [5:0] rd_data_offset_2;\n wire [6*RANKS-1:0] rd_data_offset_ranks_0;\n wire [6*RANKS-1:0] rd_data_offset_ranks_1;\n wire [6*RANKS-1:0] rd_data_offset_ranks_2;\n wire [6*RANKS-1:0] rd_data_offset_ranks_mc_0;\n wire [6*RANKS-1:0] rd_data_offset_ranks_mc_1;\n wire [6*RANKS-1:0] rd_data_offset_ranks_mc_2;\n wire cmd_po_stg2_f_incdec;\n wire cmd_po_stg2_incdec_ddr2_c;\n wire cmd_po_en_stg2_f;\n wire cmd_po_en_stg2_ddr2_c;\n wire cmd_po_stg2_c_incdec;\n wire cmd_po_en_stg2_c;\n wire po_stg2_ddr2_incdec;\n wire po_en_stg2_ddr2;\n wire dqs_po_stg2_f_incdec;\n wire dqs_po_en_stg2_f;\n wire dqs_wl_po_stg2_c_incdec;\n wire wrcal_po_stg2_c_incdec;\n wire dqs_wl_po_en_stg2_c;\n wire wrcal_po_en_stg2_c;\n wire [N_CTL_LANES-1:0] ctl_lane_cnt;\n reg [N_CTL_LANES-1:0] ctl_lane_sel;\n wire [DQS_CNT_WIDTH:0] po_stg2_wrcal_cnt;\n wire [DQS_CNT_WIDTH:0] po_stg2_wl_cnt;\n wire [DQS_CNT_WIDTH:0] po_stg2_ddr2_cnt;\n wire [8:0] dqs_wl_po_stg2_reg_l;\n wire dqs_wl_po_stg2_load;\n wire [8:0] dqs_po_stg2_reg_l;\n wire dqs_po_stg2_load;\n wire dqs_po_dec_done;\n wire pi_fine_dly_dec_done;\n wire rdlvl_pi_stg2_f_incdec;\n wire rdlvl_pi_stg2_f_en;\n wire [DQS_CNT_WIDTH:0] pi_stg2_rdlvl_cnt;\n //reg [DQS_CNT_WIDTH:0] byte_sel_cnt;\n wire [3*DQS_WIDTH-1:0] wl_po_coarse_cnt;\n wire [6*DQS_WIDTH-1:0] wl_po_fine_cnt;\n wire phase_locked_err;\n wire phy_ctl_rdy_dly;\n wire idelay_ce_int;\n wire idelay_inc_int;\n reg idelay_ce_r1;\n reg idelay_ce_r2;\n reg idelay_inc_r1;\n reg idelay_inc_r2 /* synthesis syn_maxfan = 30 */;\n reg po_dly_req_r;\n wire wrcal_read_req;\n wire wrcal_act_req;\n wire temp_wrcal_done;\n wire tg_timer_done;\n wire no_rst_tg_mc;\n wire calib_complete;\n reg reset_if_r1;\n reg reset_if_r2;\n reg reset_if_r3;\n reg reset_if_r4;\n reg reset_if_r5;\n reg reset_if_r6;\n reg reset_if_r7;\n reg reset_if_r8;\n reg reset_if_r9;\n reg reset_if;\n wire phy_if_reset_w;\n wire pi_phaselock_start;\n\n reg dbg_pi_f_inc_r;\n reg dbg_pi_f_en_r;\n reg dbg_sel_pi_incdec_r;\n\n reg dbg_po_f_inc_r;\n reg dbg_po_f_stg23_sel_r;\n reg dbg_po_f_en_r;\n reg dbg_sel_po_incdec_r;\n\n reg tempmon_pi_f_inc_r;\n reg tempmon_pi_f_en_r;\n reg tempmon_sel_pi_incdec_r;\n\n reg ck_addr_cmd_delay_done_r1;\n reg ck_addr_cmd_delay_done_r2;\n reg ck_addr_cmd_delay_done_r3;\n reg ck_addr_cmd_delay_done_r4;\n reg ck_addr_cmd_delay_done_r5;\n reg ck_addr_cmd_delay_done_r6;\n// wire oclk_init_delay_start;\n wire oclk_prech_req;\n wire oclk_calib_resume;\n wire [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;\n wire [DQS_CNT_WIDTH:0] complex_oclkdelay_calib_cnt;\n wire oclkdelay_calib_start;\n wire oclkdelay_calib_done;\n wire complex_oclk_prech_req;\n wire complex_oclk_calib_resume;\n wire complex_oclkdelay_calib_start;\n wire complex_oclkdelay_calib_done;\n wire complex_ocal_num_samples_inc;\n wire complex_ocal_num_samples_done_r;\n wire [2:0] complex_ocal_rd_victim_sel;\n wire complex_ocal_ref_req;\n wire complex_ocal_ref_done;\n wire [6*DQS_WIDTH-1:0] oclkdelay_left_edge_val;\n wire [6*DQS_WIDTH-1:0] oclkdelay_right_edge_val;\n\n wire wrlvl_final;\n wire complex_wrlvl_final;\n reg wrlvl_final_mux;\n wire wrlvl_final_if_rst;\n wire wrlvl_byte_redo;\n wire wrlvl_byte_done;\n wire early1_data;\n wire early2_data;\n wire po_stg23_sel;\n wire po_stg23_incdec;\n wire po_en_stg23;\n wire complex_po_stg23_sel;\n wire complex_po_stg23_incdec;\n wire complex_po_en_stg23;\n wire mpr_rdlvl_done;\n wire mpr_rdlvl_start;\n wire mpr_last_byte_done;\n wire mpr_rnk_done;\n wire mpr_end_if_reset;\n wire mpr_rdlvl_err;\n wire rdlvl_err;\n wire prbs_rdlvl_start;\n wire prbs_rdlvl_done;\n wire prbs_rdlvl_done_complex;\n reg prbs_rdlvl_done_r1;\n wire prbs_last_byte_done;\n wire prbs_rdlvl_prech_req;\n wire prbs_pi_stg2_f_incdec;\n wire prbs_pi_stg2_f_en;\n wire complex_sample_cnt_inc;\n wire complex_sample_cnt_inc_ocal;\n wire [DQS_CNT_WIDTH:0] pi_stg2_prbs_rdlvl_cnt;\n wire prbs_gen_clk_en;\n wire prbs_gen_oclk_clk_en;\n wire rd_data_offset_cal_done;\n wire fine_adjust_done;\n wire [N_CTL_LANES-1:0] fine_adjust_lane_cnt;\n wire ck_po_stg2_f_indec;\n wire ck_po_stg2_f_en;\n wire dqs_found_prech_req;\n wire tempmon_pi_f_inc;\n wire tempmon_pi_f_dec;\n wire tempmon_sel_pi_incdec;\n wire wrcal_sanity_chk;\n wire wrcal_sanity_chk_done;\n wire wrlvl_done_w;\n wire wrlvl_rank_done;\n wire done_dqs_tap_inc;\n wire [2:0] rd_victim_sel;\n wire [2:0] victim_sel;\n wire [DQS_CNT_WIDTH:0] victim_byte_cnt;\n wire complex_wr_done;\n wire complex_victim_inc;\n\n wire reset_rd_addr;\n wire complex_ocal_reset_rd_addr;\n\n wire oclkdelay_center_calib_start;\n wire poc_error;\n\n wire prbs_ignore_first_byte;\n wire prbs_ignore_last_bytes;\n\n //stg3 tap values\n // wire [6*DQS_WIDTH-1:0] oclkdelay_center_val;\n\n //byte selection\n // wire [DQS_CNT_WIDTH:0] oclkdelay_center_cnt;\n\n //INC/DEC for stg3 taps\n // wire ocal_ctr_po_stg23_sel;\n // wire ocal_ctr_po_stg23_incdec;\n // wire ocal_ctr_po_en_stg23;\n\n //Write resume for DQS toggling\n wire oclk_center_write_resume;\n wire oclkdelay_center_calib_done;\n\n //Write request to toggle DQS for limit module\n wire lim2init_write_request;\n wire lim_done;\n\n // Bypass complex ocal\n wire complex_oclkdelay_calib_start_w;\n wire complex_oclkdelay_calib_done_w;\n wire [2:0] complex_ocal_rd_victim_sel_w;\n wire complex_wrlvl_final_w;\n\n wire [255:0] dbg_ocd_lim;\n\n //with MMCM phase detect logic\n //wire mmcm_edge_detect_rdy; // ready for MMCM detect\n //wire ktap_at_rightedge; // stg3 tap at right edge\n //wire ktap_at_leftedge; // stg3 tap at left edge\n //wire mmcm_tap_at_center; // indicate stg3 tap at center\n //wire mmcm_ps_clkphase_ok; // ps clkphase is OK\n //wire mmcm_edge_detect_done; // mmcm edge detect is done\n //wire mmcm_lbclk_edges_aligned; // mmcm edge detect is done\n //wire reset_mmcm; //mmcm detect logic reset per byte\n\n // wire [255:0] dbg_phy_oclkdelay_center_cal;\n\n //PI inc/dec prevention during READ\n wire rdlvl_pi_incdec;\n wire complex_act_start;\n wire complex_pi_incdec_done;\n wire num_samples_done_r;\n wire complex_init_pi_dec_done;\n\n wire calib_tap_inc_start;\n wire calib_tap_inc_done;\n wire calib_tap_end_if_reset;\n wire [5:0] calib_tap_inc_byte_cnt;\n wire calib_po_f_en;\n wire calib_po_f_incdec;\n wire calib_po_sel_stg2stg3;\n wire calib_po_c_en;\n wire calib_po_c_inc;\n wire calib_pi_f_en;\n wire calib_pi_f_incdec;\n wire calib_idelay_ce;\n wire calib_idelay_inc;\n wire coarse_dec_err;\n reg skip_cal_tempmon_samp_en;\n wire tempmon_done_skip;\n\n wire skip_cal_po_pi_dec_done;\n reg [6*DQS_WIDTH-1:0] calib_po_stage2_tap_cnt;\n reg [6*DQS_WIDTH-1:0] calib_po_stage3_tap_cnt;\n reg [3*DQS_WIDTH-1:0] calib_po_coarse_tap_cnt;\n reg [6*DQS_WIDTH-1:0] calib_pi_stage2_tap_cnt;\n reg [5*DQS_WIDTH-1:0] calib_idelay_tap_cnt;\n reg [11:0] calib_device_temp;\n wire [127:0] dbg_skip_cal;\n\n //*****************************************************************************\n // Assertions to check correctness of parameter values\n //*****************************************************************************\n // synthesis translate_off\n initial\n begin\n if (RANKS == 0) begin\n $display (\"Error: Invalid RANKS parameter. Must be 1 or greater\");\n $finish;\n end\n if (phy_ctl_full == 1'b1) begin\n $display (\"Error: Incorrect phy_ctl_full input value in 2:1 or 4:1 mode\");\n $finish;\n end\n end\n // synthesis translate_on\n\n //***************************************************************************\n // Debug\n //***************************************************************************\n reg if_empty_reg;\n reg pi_stg2_en_reg;\n\n assign prbs_rdlvl_done = (SIM_CAL_OPTION == \"FAST_CAL\")? rdlvl_stg1_done : prbs_rdlvl_done_complex;\n\n assign dbg_pi_phaselock_start = pi_phaselock_start;\n assign dbg_pi_dqsfound_start = pi_dqs_found_start;\n assign dbg_pi_dqsfound_done = pi_dqs_found_done;\n assign dbg_wrcal_start = wrcal_start;\n assign dbg_wrcal_done = wrcal_done;\n\n // Unused for now - use these as needed to bring up lower level signals\n //assign dbg_calib_top = dbg_ocd_lim;\n assign dbg_calib_top[0] = pi_stg2_en_reg ;\n assign dbg_calib_top[1] = if_empty_reg ;\n assign dbg_calib_top[3] = coarse_dec_err;\n assign dbg_calib_top[4] = calib_tap_inc_start;\n assign dbg_calib_top[5] = calib_tap_inc_done;\n assign dbg_calib_top[6+:63] = dbg_skip_cal;\n\n always @ (posedge clk) begin\n if_empty_reg <= #TCQ phy_if_empty;\n pi_stg2_en_reg <= #TCQ pi_en_stg2_f;\n end\n\n // Write Level and write calibration debug observation ports\n assign dbg_wrlvl_start = wrlvl_start;\n assign dbg_wrlvl_done = wrlvl_done;\n assign dbg_wrlvl_err = wrlvl_err;\n\n // Read Level debug observation ports\n assign dbg_rdlvl_start = {mpr_rdlvl_start, rdlvl_stg1_start};\n assign dbg_rdlvl_done = {mpr_rdlvl_done, rdlvl_stg1_done};\n assign dbg_rdlvl_err = {mpr_rdlvl_err, rdlvl_err};\n\n assign dbg_oclkdelay_calib_done = oclkdelay_calib_done;\n assign dbg_oclkdelay_calib_start = oclkdelay_calib_start;\n\n //***************************************************************************\n // Write leveling dependent signals\n //***************************************************************************\n\n assign wrcal_resume_w = (WRLVL == \"ON\") ? wrcal_pat_resume : 1'b0;\n assign wrlvl_done_w = (WRLVL == \"ON\") ? wrlvl_done : 1'b1;\n assign ck_addr_cmd_delay_done = (WRLVL == \"ON\") ? po_ck_addr_cmd_delay_done :\n (po_ck_addr_cmd_delay_done\n && pi_fine_dly_dec_done) ;\n\ngenerate\n if((WRLVL == \"ON\") && (BYPASS_COMPLEX_OCAL==\"FALSE\")) begin: complex_oclk_calib\n assign complex_oclkdelay_calib_start_w = complex_oclkdelay_calib_start;\n assign complex_oclkdelay_calib_done_w = complex_oclkdelay_calib_done;\n assign complex_ocal_rd_victim_sel_w = complex_ocal_rd_victim_sel;\n assign complex_wrlvl_final_w = complex_wrlvl_final;\n end else begin: bypass_complex_ocal\n assign complex_oclkdelay_calib_start_w = 1'b0;\n assign complex_oclkdelay_calib_done_w = prbs_rdlvl_done;\n assign complex_ocal_rd_victim_sel_w = 'd0;\n assign complex_wrlvl_final_w = 1'b0;\n end\nendgenerate\n\n\n generate\n genvar i;\n for (i = 0; i <= 2; i = i+1) begin : bankwise_signal\n\n assign po_sel_stg2stg3[i] = ((ck_addr_cmd_delay_done && ~oclkdelay_calib_done && mpr_rdlvl_done) ? po_stg23_sel :\n (complex_oclkdelay_calib_start_w&&~complex_oclkdelay_calib_done_w? po_stg23_sel : 1'b0 )\n // (~oclkdelay_center_calib_done? ocal_ctr_po_stg23_sel:1'b0))\n ) || calib_po_sel_stg2stg3 || dbg_po_f_stg23_sel_r;\n\n assign po_stg2_c_incdec[i] = cmd_po_stg2_c_incdec ||\n cmd_po_stg2_incdec_ddr2_c ||\n calib_po_c_inc ||\n dqs_wl_po_stg2_c_incdec;\n\n assign po_en_stg2_c[i] = cmd_po_en_stg2_c ||\n cmd_po_en_stg2_ddr2_c ||\n calib_po_c_en ||\n dqs_wl_po_en_stg2_c;\n\n assign po_stg2_f_incdec[i] = dqs_po_stg2_f_incdec ||\n cmd_po_stg2_f_incdec ||\n ck_po_stg2_f_indec ||\n po_stg23_incdec ||\n calib_po_f_incdec ||\n // complex_po_stg23_incdec ||\n // ocal_ctr_po_stg23_incdec ||\n dbg_po_f_inc_r;\n\n assign po_en_stg2_f[i] = dqs_po_en_stg2_f ||\n cmd_po_en_stg2_f ||\n ck_po_stg2_f_en ||\n po_en_stg23 ||\n calib_po_f_en ||\n // complex_po_en_stg23 ||\n // ocal_ctr_po_en_stg23 ||\n dbg_po_f_en_r;\n\n end\n endgenerate\n\n assign pi_stg2_f_incdec = (calib_pi_f_incdec | dbg_pi_f_inc_r | rdlvl_pi_stg2_f_incdec | prbs_pi_stg2_f_incdec | tempmon_pi_f_inc_r);\n assign pi_en_stg2_f = (calib_pi_f_en | dbg_pi_f_en_r | rdlvl_pi_stg2_f_en | prbs_pi_stg2_f_en | tempmon_pi_f_en_r);\n\n assign idelay_ce = (idelay_ce_r2 | calib_idelay_ce);\n assign idelay_inc = (idelay_inc_r2 | calib_idelay_inc);\n\n assign po_counter_load_en = 1'b0;\n\n assign complex_oclkdelay_calib_cnt = oclkdelay_calib_cnt;\n assign complex_oclk_calib_resume = oclk_calib_resume;\n assign complex_ocal_ref_req = oclk_prech_req;\n\n\n// Added single stage flop to meet timing\n always @(posedge clk) begin\n if (SKIP_CALIB == \"FALSE\")\n init_calib_complete <= calib_complete;\n else\n init_calib_complete <= tempmon_done_skip;\n end\n\n assign calib_rd_data_offset_0 = rd_data_offset_ranks_mc_0;\n assign calib_rd_data_offset_1 = rd_data_offset_ranks_mc_1;\n assign calib_rd_data_offset_2 = rd_data_offset_ranks_mc_2;\n\n //***************************************************************************\n // Hard PHY signals\n //***************************************************************************\n\n assign pi_phase_locked_err = phase_locked_err;\n assign pi_dqsfound_err = pi_dqs_found_err;\n assign wrcal_err = wrcal_pat_err;\n assign rst_tg_mc = 1'b0;\n\n//Restart WRLVL after oclkdealy cal\n always @ (posedge clk)\n wrlvl_final_mux <= #TCQ complex_oclkdelay_calib_start_w? complex_wrlvl_final_w: wrlvl_final;\n\n\n always @(posedge clk)\n phy_if_reset <= #TCQ (phy_if_reset_w | mpr_end_if_reset |\n reset_if | wrlvl_final_if_rst | calib_tap_end_if_reset);\n\n //***************************************************************************\n // Phaser_IN inc dec control for debug\n //***************************************************************************\n\n always @(posedge clk) begin\n if (rst) begin\n dbg_pi_f_inc_r <= #TCQ 1'b0;\n dbg_pi_f_en_r <= #TCQ 1'b0;\n dbg_sel_pi_incdec_r <= #TCQ 1'b0;\n end else begin\n dbg_pi_f_inc_r <= #TCQ dbg_pi_f_inc;\n dbg_pi_f_en_r <= #TCQ (dbg_pi_f_inc | dbg_pi_f_dec);\n dbg_sel_pi_incdec_r <= #TCQ dbg_sel_pi_incdec;\n end\n end\n\n //***************************************************************************\n // Phaser_OUT inc dec control for debug\n //***************************************************************************\n\n always @(posedge clk) begin\n if (rst) begin\n dbg_po_f_inc_r <= #TCQ 1'b0;\n dbg_po_f_stg23_sel_r<= #TCQ 1'b0;\n dbg_po_f_en_r <= #TCQ 1'b0;\n dbg_sel_po_incdec_r <= #TCQ 1'b0;\n end else begin\n dbg_po_f_inc_r <= #TCQ dbg_po_f_inc;\n dbg_po_f_stg23_sel_r<= #TCQ dbg_po_f_stg23_sel;\n dbg_po_f_en_r <= #TCQ (dbg_po_f_inc | dbg_po_f_dec);\n dbg_sel_po_incdec_r <= #TCQ dbg_sel_po_incdec;\n end\n end\n\n //***************************************************************************\n // Phaser_IN inc dec control for temperature tracking\n //***************************************************************************\n\n always @(posedge clk) begin\n if (rst) begin\n tempmon_pi_f_inc_r <= #TCQ 1'b0;\n tempmon_pi_f_en_r <= #TCQ 1'b0;\n tempmon_sel_pi_incdec_r <= #TCQ 1'b0;\n end else begin\n tempmon_pi_f_inc_r <= #TCQ tempmon_pi_f_inc;\n tempmon_pi_f_en_r <= #TCQ (tempmon_pi_f_inc | tempmon_pi_f_dec);\n tempmon_sel_pi_incdec_r <= #TCQ tempmon_sel_pi_incdec;\n end\n end\n\n //***************************************************************************\n // OCLKDELAY calibration signals\n //***************************************************************************\n\n // Minimum of 5 'clk' cycles required between assertion of po_sel_stg2stg3\n // and increment/decrement of Phaser_Out stage 3 delay\n always @(posedge clk) begin\n ck_addr_cmd_delay_done_r1 <= #TCQ ck_addr_cmd_delay_done;\n ck_addr_cmd_delay_done_r2 <= #TCQ ck_addr_cmd_delay_done_r1;\n ck_addr_cmd_delay_done_r3 <= #TCQ ck_addr_cmd_delay_done_r2;\n ck_addr_cmd_delay_done_r4 <= #TCQ ck_addr_cmd_delay_done_r3;\n ck_addr_cmd_delay_done_r5 <= #TCQ ck_addr_cmd_delay_done_r4;\n ck_addr_cmd_delay_done_r6 <= #TCQ ck_addr_cmd_delay_done_r5;\n end\n\n\n\n\n //***************************************************************************\n // MUX select logic to select current byte undergoing calibration\n // Use DQS_CAL_MAP to determine the correlation between the physical\n // byte numbering, and the byte numbering within the hard PHY\n //***************************************************************************\ngenerate\n if (SKIP_CALIB == \"TRUE\") begin: gen_byte_sel_skip_calib\n always @(posedge clk) begin\n if (rst) begin\n byte_sel_cnt <= #TCQ 'd0;\n ctl_lane_sel <= #TCQ 'd0;\n calib_in_common <= #TCQ 1'b0;\n end else if (~skip_cal_po_pi_dec_done) begin\n byte_sel_cnt <= #TCQ 'd0;\n calib_in_common <= #TCQ 1'b1;\n end else if (~ck_addr_cmd_delay_done && (WRLVL !=\"ON\")) begin\n byte_sel_cnt <= #TCQ 'd0;\n ctl_lane_sel <= #TCQ 'd0;\n calib_in_common <= #TCQ 1'b1;\n end else if (~ck_addr_cmd_delay_done) begin\n ctl_lane_sel <= #TCQ ctl_lane_cnt;\n calib_in_common <= #TCQ 1'b0;\n end else if (~fine_adjust_done && rd_data_offset_cal_done) begin\n if ((|pi_rst_stg1_cal) || (DRAM_TYPE == \"DDR2\")) begin\n byte_sel_cnt <= #TCQ 'd0;\n ctl_lane_sel <= #TCQ 'd0;\n calib_in_common <= #TCQ 1'b1;\n end else begin\n byte_sel_cnt <= #TCQ 'd0;\n ctl_lane_sel <= #TCQ fine_adjust_lane_cnt;\n calib_in_common <= #TCQ 1'b0;\n end\n end else if (~pi_calib_done) begin\n byte_sel_cnt <= #TCQ 'd0;\n calib_in_common <= #TCQ 1'b1;\n end else if (~pi_dqs_found_done) begin\n byte_sel_cnt <= #TCQ 'd0;\n calib_in_common <= #TCQ 1'b1;\n end else if (~calib_tap_inc_done) begin\n byte_sel_cnt <= #TCQ calib_tap_inc_byte_cnt;\n calib_in_common <= #TCQ 1'b0;\n end else if (dbg_sel_pi_incdec_r | dbg_sel_po_incdec_r) begin\n byte_sel_cnt <= #TCQ dbg_byte_sel;\n calib_in_common <= #TCQ 1'b0;\n end else if (tempmon_sel_pi_incdec) begin\n byte_sel_cnt <= #TCQ 'd0;\n calib_in_common <= #TCQ 1'b1;\n end\n end\n end else if (tCK >= 2500) begin: gen_byte_sel_div2 // DIV2 change\n\n always @(posedge clk) begin\n if (rst) begin\n byte_sel_cnt <= #TCQ 'd0;\n ctl_lane_sel <= #TCQ 'd0;\n calib_in_common <= #TCQ 1'b0;\n end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done)) begin\n byte_sel_cnt <= #TCQ 'd0;\n calib_in_common <= #TCQ 1'b1;\n end else if (~ck_addr_cmd_delay_done && (WRLVL !=\"ON\")) begin\n byte_sel_cnt <= #TCQ 'd0;\n ctl_lane_sel <= #TCQ 'd0;\n calib_in_common <= #TCQ 1'b1;\n end else if (~ck_addr_cmd_delay_done) begin\n ctl_lane_sel <= #TCQ ctl_lane_cnt;\n calib_in_common <= #TCQ 1'b0;\n end else if (~fine_adjust_done && rd_data_offset_cal_done) begin\n if ((|pi_rst_stg1_cal) || (DRAM_TYPE == \"DDR2\")) begin\n byte_sel_cnt <= #TCQ 'd0;\n ctl_lane_sel <= #TCQ 'd0;\n calib_in_common <= #TCQ 1'b1;\n end else begin\n byte_sel_cnt <= #TCQ 'd0;\n ctl_lane_sel <= #TCQ fine_adjust_lane_cnt;\n calib_in_common <= #TCQ 1'b0;\n end\n end else if (~pi_calib_done) begin\n byte_sel_cnt <= #TCQ 'd0;\n calib_in_common <= #TCQ 1'b1;\n end else if (~pi_dqs_found_done) begin\n byte_sel_cnt <= #TCQ 'd0;\n calib_in_common <= #TCQ 1'b1;\n end else if (~wrlvl_done_w) begin\n if (SIM_CAL_OPTION != \"FAST_CAL\") begin\n byte_sel_cnt <= #TCQ po_stg2_wl_cnt;\n calib_in_common <= #TCQ 1'b0;\n end else begin\n // Special case for FAST_CAL simulation only to ensure that\n // calib_in_common isn't asserted too soon\n if (!phy_ctl_rdy_dly) begin\n byte_sel_cnt <= #TCQ 'd0;\n calib_in_common <= #TCQ 1'b0;\n end else begin\n byte_sel_cnt <= #TCQ po_stg2_wl_cnt;\n calib_in_common <= #TCQ 1'b1;\n end\n end\n end else if (~mpr_rdlvl_done) begin\n byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;\n calib_in_common <= #TCQ 1'b0;\n end else if (~oclkdelay_calib_done) begin\n byte_sel_cnt <= #TCQ oclkdelay_calib_cnt;\n calib_in_common <= #TCQ 1'b0;\n end else if (~rdlvl_stg1_done && pi_calib_done) begin\n if ((SIM_CAL_OPTION == \"FAST_CAL\") && rdlvl_assrt_common) begin\n byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;\n calib_in_common <= #TCQ 1'b1;\n end else begin\n byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;\n calib_in_common <= #TCQ 1'b0;\n end\n end else if (~prbs_rdlvl_done && rdlvl_stg1_done) begin\n byte_sel_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt;\n calib_in_common <= #TCQ 1'b0;\n end else if (~complex_oclkdelay_calib_done_w && prbs_rdlvl_done) begin\n byte_sel_cnt <= #TCQ complex_oclkdelay_calib_cnt;\n calib_in_common <= #TCQ 1'b0;\n end else if ((~wrcal_done) && (DRAM_TYPE == \"DDR3\")) begin\n byte_sel_cnt <= #TCQ po_stg2_wrcal_cnt;\n calib_in_common <= #TCQ 1'b0;\n end else if (dbg_sel_pi_incdec_r | dbg_sel_po_incdec_r) begin\n byte_sel_cnt <= #TCQ dbg_byte_sel;\n calib_in_common <= #TCQ 1'b0;\n end else if (tempmon_sel_pi_incdec) begin\n byte_sel_cnt <= #TCQ 'd0;\n calib_in_common <= #TCQ 1'b1;\n end\n end\n end else begin: gen_byte_sel_div1\n\n always @(posedge clk) begin\n if (rst) begin\n byte_sel_cnt <= #TCQ 'd0;\n ctl_lane_sel <= #TCQ 'd0;\n calib_in_common <= #TCQ 1'b0;\n end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done)) begin\n byte_sel_cnt <= #TCQ 'd0;\n calib_in_common <= #TCQ 1'b1;\n end else if (~ck_addr_cmd_delay_done && (WRLVL !=\"ON\")) begin\n byte_sel_cnt <= #TCQ 'd0;\n ctl_lane_sel <= #TCQ 'd0;\n calib_in_common <= #TCQ 1'b1;\n end else if (~ck_addr_cmd_delay_done) begin\n ctl_lane_sel <= #TCQ ctl_lane_cnt;\n calib_in_common <= #TCQ 1'b0;\n end else if (~fine_adjust_done && rd_data_offset_cal_done) begin\n if ((|pi_rst_stg1_cal) || (DRAM_TYPE == \"DDR2\")) begin\n byte_sel_cnt <= #TCQ 'd0;\n ctl_lane_sel <= #TCQ 'd0;\n calib_in_common <= #TCQ 1'b1;\n end else begin\n byte_sel_cnt <= #TCQ 'd0;\n ctl_lane_sel <= #TCQ fine_adjust_lane_cnt;\n calib_in_common <= #TCQ 1'b0;\n end\n end else if (~pi_calib_done) begin\n byte_sel_cnt <= #TCQ 'd0;\n calib_in_common <= #TCQ 1'b1;\n end else if (~pi_dqs_found_done) begin\n byte_sel_cnt <= #TCQ 'd0;\n calib_in_common <= #TCQ 1'b1;\n end else if (~wrlvl_done_w) begin\n if (SIM_CAL_OPTION != \"FAST_CAL\") begin\n byte_sel_cnt <= #TCQ po_stg2_wl_cnt;\n calib_in_common <= #TCQ 1'b0;\n end else begin\n // Special case for FAST_CAL simulation only to ensure that\n // calib_in_common isn't asserted too soon\n if (!phy_ctl_rdy_dly) begin\n byte_sel_cnt <= #TCQ 'd0;\n calib_in_common <= #TCQ 1'b0;\n end else begin\n byte_sel_cnt <= #TCQ po_stg2_wl_cnt;\n calib_in_common <= #TCQ 1'b1;\n end\n end\n end else if (~mpr_rdlvl_done) begin\n byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;\n calib_in_common <= #TCQ 1'b0;\n end else if (~oclkdelay_calib_done) begin\n byte_sel_cnt <= #TCQ oclkdelay_calib_cnt;\n calib_in_common <= #TCQ 1'b0;\n end else if ((~wrcal_done)&& (DRAM_TYPE == \"DDR3\")) begin\n byte_sel_cnt <= #TCQ po_stg2_wrcal_cnt;\n calib_in_common <= #TCQ 1'b0;\n end else if (~rdlvl_stg1_done && pi_calib_done) begin\n if ((SIM_CAL_OPTION == \"FAST_CAL\") && rdlvl_assrt_common) begin\n byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;\n calib_in_common <= #TCQ 1'b1;\n end else begin\n byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;\n calib_in_common <= #TCQ 1'b0;\n end\n end else if (~prbs_rdlvl_done && rdlvl_stg1_done) begin\n byte_sel_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt;\n calib_in_common <= #TCQ 1'b0;\n end else if (~complex_oclkdelay_calib_done_w && prbs_rdlvl_done) begin\n byte_sel_cnt <= #TCQ complex_oclkdelay_calib_cnt;\n calib_in_common <= #TCQ 1'b0;\n end else if (dbg_sel_pi_incdec_r | dbg_sel_po_incdec_r) begin\n byte_sel_cnt <= #TCQ dbg_byte_sel;\n calib_in_common <= #TCQ 1'b0;\n end else if (tempmon_sel_pi_incdec) begin\n byte_sel_cnt <= #TCQ 'd0;\n calib_in_common <= #TCQ 1'b1;\n end\n end\n\n end\nendgenerate\n\n // verilint STARC-2.2.3.3 off\n always @(posedge clk) begin\n if (rst || (calib_complete && ~ (dbg_sel_pi_incdec_r|dbg_sel_po_incdec_r|tempmon_sel_pi_incdec) )) begin\n calib_sel <= #TCQ 6'b000100;\n calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}};\n calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};\n end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done) || ~skip_cal_po_pi_dec_done) begin\n calib_sel[2] <= #TCQ 1'b0;\n calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];\n calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];\n calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};\n if (~dqs_po_dec_done && (WRLVL != \"ON\"))\n //if (~dqs_po_dec_done && ((SIM_CAL_OPTION == \"FAST_CAL\") ||(WRLVL != \"ON\")))\n calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b0}};\n else\n calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};\n end else if (~ck_addr_cmd_delay_done || (~fine_adjust_done && rd_data_offset_cal_done)) begin\n if(WRLVL ==\"ON\") begin\n calib_sel[2] <= #TCQ 1'b0;\n calib_sel[1:0] <= #TCQ CTL_BYTE_LANE[(ctl_lane_sel*2)+:2];\n calib_sel[5:3] <= #TCQ CTL_BANK;\n if (|pi_rst_stg1_cal) begin\n calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};\n end else begin\n calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}};\n calib_zero_inputs[1*CTL_BANK] <= #TCQ 1'b0;\n end\n calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};\n end else begin // if (WRLVL ==\"ON\")\n calib_sel[2] <= #TCQ 1'b0;\n calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];\n calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];\n calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};\n if(~ck_addr_cmd_delay_done)\n calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};\n else\n calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b0}};\n end // else: !if(WRLVL ==\"ON\")\n end else if ((~wrlvl_done_w) && (SIM_CAL_OPTION == \"FAST_CAL\")) begin\n calib_sel[2] <= #TCQ 1'b0;\n calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];\n calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];\n calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};\n calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};\n end else if (~rdlvl_stg1_done && (SIM_CAL_OPTION == \"FAST_CAL\") &&\n rdlvl_assrt_common) begin\n calib_sel[2] <= #TCQ 1'b0;\n calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];\n calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];\n calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};\n calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};\n end else if (tempmon_sel_pi_incdec) begin\n calib_sel[2] <= #TCQ 1'b0;\n calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];\n calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];\n calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};\n calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};\n end else begin\n calib_sel[2] <= #TCQ 1'b0;\n calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];\n calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];\n calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};\n if (~calib_in_common) begin\n calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}};\n calib_zero_inputs[(1*DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3])] <= #TCQ 1'b0;\n end else\n calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};\n end\n end\n // verilint STARC-2.2.3.3 on\n // Logic to reset IN_FIFO flags to account for the possibility that\n // one or more PHASER_IN's have not correctly found the DQS preamble\n // If this happens, we can still complete read leveling, but the # of\n // words written into the IN_FIFO's may be an odd #, so that if the\n // IN_FIFO is used in 2:1 mode (\"8:4 mode\"), there may be a \"half\" word\n // of data left that can only be flushed out by reseting the IN_FIFO\n always @(posedge clk) begin\n rdlvl_stg1_done_r1 <= #TCQ rdlvl_stg1_done;\n prbs_rdlvl_done_r1 <= #TCQ prbs_rdlvl_done;\n reset_if_r1 <= #TCQ reset_if;\n reset_if_r2 <= #TCQ reset_if_r1;\n reset_if_r3 <= #TCQ reset_if_r2;\n reset_if_r4 <= #TCQ reset_if_r3;\n reset_if_r5 <= #TCQ reset_if_r4;\n reset_if_r6 <= #TCQ reset_if_r5;\n reset_if_r7 <= #TCQ reset_if_r6;\n reset_if_r8 <= #TCQ reset_if_r7;\n reset_if_r9 <= #TCQ reset_if_r8;\n end\n\n always @(posedge clk) begin\n if (rst || reset_if_r9)\n reset_if <= #TCQ 1'b0;\n else if ((rdlvl_stg1_done && ~rdlvl_stg1_done_r1) ||\n (prbs_rdlvl_done && ~prbs_rdlvl_done_r1))\n reset_if <= #TCQ 1'b1;\n end\n\n assign phy_if_empty_def = 1'b0;\n\n // DQ IDELAY tap inc and ce signals registered to control calib_in_common\n // signal during read leveling in FAST_CAL mode. The calib_in_common signal\n // is only asserted for IDELAY tap increments not Phaser_IN tap increments\n // in FAST_CAL mode. For Phaser_IN tap increments the Phaser_IN counter load\n // inputs are used.\n always @(posedge clk) begin\n if (rst) begin\n idelay_ce_r1 <= #TCQ 1'b0;\n idelay_ce_r2 <= #TCQ 1'b0;\n idelay_inc_r1 <= #TCQ 1'b0;\n idelay_inc_r2 <= #TCQ 1'b0;\n end else begin\n idelay_ce_r1 <= #TCQ idelay_ce_int;\n idelay_ce_r2 <= #TCQ idelay_ce_r1;\n idelay_inc_r1 <= #TCQ idelay_inc_int;\n idelay_inc_r2 <= #TCQ idelay_inc_r1;\n end\n end\n\n //***************************************************************************\n // Delay all Outputs using Phaser_Out fine taps\n //***************************************************************************\n\n assign init_wrcal_complete = 1'b0;\n\n //***************************************************************************\n // PRBS Generator for Read Leveling Stage 1 - read window detection and\n // DQS Centering\n //***************************************************************************\n\n // Assign initial seed (used for 1st data word in 8-burst sequence); use alternating 1/0 pat\n assign prbs_seed = 64'h9966aa559966aa55;\n\n // A single PRBS generator\n // writes 64-bits every 4to1 fabric clock cycle and\n // write 32-bits every 2to1 fabric clock cycle\n // used for complex read leveling and complex oclkdealy calib\n mig_7series_v4_0_ddr_prbs_gen #\n (\n .TCQ (TCQ),\n .PRBS_WIDTH (2*8*nCK_PER_CLK),\n .DQS_CNT_WIDTH (DQS_CNT_WIDTH),\n .DQ_WIDTH (DQ_WIDTH),\n .VCCO_PAT_EN (VCCO_PAT_EN),\n .VCCAUX_PAT_EN (VCCAUX_PAT_EN),\n .ISI_PAT_EN (ISI_PAT_EN),\n .FIXED_VICTIM (FIXED_VICTIM)\n )\n u_ddr_prbs_gen\n (.prbs_ignore_first_byte (prbs_ignore_first_byte),\n .prbs_ignore_last_bytes (prbs_ignore_last_bytes),\n .clk_i (clk),\n .clk_en_i (prbs_gen_clk_en | prbs_gen_oclk_clk_en),\n .rst_i (rst),\n .prbs_o (prbs_out),\n .prbs_seed_i (prbs_seed),\n .phy_if_empty (phy_if_empty),\n .prbs_rdlvl_start (prbs_rdlvl_start),\n .prbs_rdlvl_done (prbs_rdlvl_done),\n .complex_wr_done (complex_wr_done),\n .victim_sel (victim_sel),\n .byte_cnt (victim_byte_cnt),\n .dbg_prbs_gen (),\n .reset_rd_addr (reset_rd_addr | complex_ocal_reset_rd_addr)\n );\n\n\n// PRBS data slice that decides the Rise0, Fall0, Rise1, Fall1,\n// Rise2, Fall2, Rise3, Fall3 data\n generate\n if (nCK_PER_CLK == 4) begin: gen_ck_per_clk4\n assign prbs_o = prbs_out;\n /*assign prbs_rise0 = prbs_out[7:0];\n assign prbs_fall0 = prbs_out[15:8];\n assign prbs_rise1 = prbs_out[23:16];\n assign prbs_fall1 = prbs_out[31:24];\n assign prbs_rise2 = prbs_out[39:32];\n assign prbs_fall2 = prbs_out[47:40];\n assign prbs_rise3 = prbs_out[55:48];\n assign prbs_fall3 = prbs_out[63:56];\n assign prbs_o = {prbs_fall3, prbs_rise3, prbs_fall2, prbs_rise2,\n prbs_fall1, prbs_rise1, prbs_fall0, prbs_rise0};*/\n end else begin :gen_ck_per_clk2\n assign prbs_o = prbs_out[4*DQ_WIDTH-1:0];\n /*assign prbs_rise0 = prbs_out[7:0];\n assign prbs_fall0 = prbs_out[15:8];\n assign prbs_rise1 = prbs_out[23:16];\n assign prbs_fall1 = prbs_out[31:24];\n assign prbs_o = {prbs_fall1, prbs_rise1, prbs_fall0, prbs_rise0};*/\n end\n endgenerate\n\n\n //***************************************************************************\n // Initialization / Master PHY state logic (overall control during memory\n // init, timing leveling)\n //***************************************************************************\n\n mig_7series_v4_0_ddr_phy_init #\n (\n .tCK (tCK),\n .DDR3_VDD_OP_VOLT (DDR3_VDD_OP_VOLT),\n .TCQ (TCQ),\n .nCK_PER_CLK (nCK_PER_CLK),\n .CLK_PERIOD (CLK_PERIOD),\n .DRAM_TYPE (DRAM_TYPE),\n .PRBS_WIDTH (PRBS_WIDTH),\n .BANK_WIDTH (BANK_WIDTH),\n .CA_MIRROR (CA_MIRROR),\n .COL_WIDTH (COL_WIDTH),\n .nCS_PER_RANK (nCS_PER_RANK),\n .DQ_WIDTH (DQ_WIDTH),\n .DQS_WIDTH (DQS_WIDTH),\n .DQS_CNT_WIDTH (DQS_CNT_WIDTH),\n .ROW_WIDTH (ROW_WIDTH),\n .CS_WIDTH (CS_WIDTH),\n .RANKS (RANKS),\n .CKE_WIDTH (CKE_WIDTH),\n .CALIB_ROW_ADD (CALIB_ROW_ADD),\n .CALIB_COL_ADD (CALIB_COL_ADD),\n .CALIB_BA_ADD (CALIB_BA_ADD),\n .AL (AL),\n .BURST_MODE (BURST_MODE),\n .BURST_TYPE (BURST_TYPE),\n .nCL (nCL),\n .nCWL (nCWL),\n .tRFC (tRFC),\n .REFRESH_TIMER (REFRESH_TIMER),\n .REFRESH_TIMER_WIDTH (REFRESH_TIMER_WIDTH),\n .OUTPUT_DRV (OUTPUT_DRV),\n .REG_CTRL (REG_CTRL),\n .ADDR_CMD_MODE (ADDR_CMD_MODE),\n .RTT_NOM (RTT_NOM),\n .RTT_WR (RTT_WR),\n .WRLVL (WRLVL),\n .USE_ODT_PORT (USE_ODT_PORT),\n .DDR2_DQSN_ENABLE(DDR2_DQSN_ENABLE),\n .nSLOTS (nSLOTS),\n .SIM_INIT_OPTION (SIM_INIT_OPTION),\n .SIM_CAL_OPTION (SIM_CAL_OPTION),\n .CKE_ODT_AUX (CKE_ODT_AUX),\n .PRE_REV3ES (PRE_REV3ES),\n .TEST_AL (TEST_AL),\n .FIXED_VICTIM (FIXED_VICTIM),\n .BYPASS_COMPLEX_OCAL(BYPASS_COMPLEX_OCAL),\n .SKIP_CALIB (SKIP_CALIB)\n )\n u_ddr_phy_init\n (\n .clk (clk),\n .rst (rst),\n .prbs_o (prbs_o),\n .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done),\n .delay_incdec_done (ck_addr_cmd_delay_done),\n .pi_phase_locked_all (pi_phase_locked_all),\n .pi_phaselock_start (pi_phaselock_start),\n .pi_phase_locked_err (phase_locked_err),\n .pi_calib_done (pi_calib_done),\n .phy_if_empty (phy_if_empty),\n .phy_ctl_ready (phy_ctl_ready),\n .phy_ctl_full (phy_ctl_full),\n .phy_cmd_full (phy_cmd_full),\n .phy_data_full (phy_data_full),\n .calib_ctl_wren (calib_ctl_wren),\n .calib_cmd_wren (calib_cmd_wren),\n .calib_wrdata_en (calib_wrdata_en),\n .calib_seq (calib_seq),\n .calib_aux_out (calib_aux_out),\n .calib_rank_cnt (calib_rank_cnt),\n .calib_cas_slot (calib_cas_slot),\n .calib_data_offset_0 (calib_data_offset_0),\n .calib_data_offset_1 (calib_data_offset_1),\n .calib_data_offset_2 (calib_data_offset_2),\n .calib_cmd (calib_cmd),\n .calib_cke (calib_cke),\n .calib_odt (calib_odt),\n .write_calib (write_calib),\n .read_calib (read_calib),\n .wrlvl_done (wrlvl_done),\n .wrlvl_rank_done (wrlvl_rank_done),\n .wrlvl_byte_done (wrlvl_byte_done),\n .wrlvl_byte_redo (wrlvl_byte_redo),\n .wrlvl_final (wrlvl_final_mux),\n .wrlvl_final_if_rst (wrlvl_final_if_rst),\n .oclkdelay_calib_start (oclkdelay_calib_start),\n .oclkdelay_calib_done (oclkdelay_calib_done),\n .oclk_prech_req (oclk_prech_req),\n .oclk_calib_resume (oclk_calib_resume),\n .lim_wr_req (lim2init_write_request),\n .lim_done (lim_done),\n .complex_oclkdelay_calib_start (complex_oclkdelay_calib_start),\n .complex_oclkdelay_calib_done (complex_oclkdelay_calib_done_w),\n .complex_oclk_calib_resume (complex_oclk_calib_resume),\n .complex_oclkdelay_calib_cnt (complex_oclkdelay_calib_cnt),\n .complex_sample_cnt_inc_ocal (complex_sample_cnt_inc_ocal),\n .complex_ocal_num_samples_inc (complex_ocal_num_samples_inc),\n .complex_ocal_num_samples_done_r (complex_ocal_num_samples_done_r),\n .complex_ocal_reset_rd_addr (complex_ocal_reset_rd_addr),\n .complex_ocal_ref_req (complex_ocal_ref_req),\n .complex_ocal_ref_done (complex_ocal_ref_done),\n .done_dqs_tap_inc (done_dqs_tap_inc),\n .wl_sm_start (wl_sm_start),\n .wr_lvl_start (wrlvl_start),\n .slot_0_present (slot_0_present),\n .slot_1_present (slot_1_present),\n .mpr_rdlvl_done (mpr_rdlvl_done),\n .mpr_rdlvl_start (mpr_rdlvl_start),\n .mpr_last_byte_done (mpr_last_byte_done),\n .mpr_rnk_done (mpr_rnk_done),\n .mpr_end_if_reset (mpr_end_if_reset),\n .rdlvl_stg1_done (rdlvl_stg1_done),\n .rdlvl_stg1_rank_done (rdlvl_stg1_rank_done),\n .rdlvl_stg1_start (rdlvl_stg1_start),\n .rdlvl_prech_req (rdlvl_prech_req),\n .rdlvl_last_byte_done (rdlvl_last_byte_done),\n .prbs_rdlvl_start (prbs_rdlvl_start),\n .complex_wr_done (complex_wr_done),\n .prbs_rdlvl_done (prbs_rdlvl_done),\n .prbs_last_byte_done (prbs_last_byte_done),\n .prbs_rdlvl_prech_req (prbs_rdlvl_prech_req),\n .complex_victim_inc (complex_victim_inc),\n .rd_victim_sel (rd_victim_sel),\n .complex_ocal_rd_victim_sel (complex_ocal_rd_victim_sel),\n .pi_stg2_prbs_rdlvl_cnt(pi_stg2_prbs_rdlvl_cnt),\n .victim_sel (victim_sel),\n .victim_byte_cnt (victim_byte_cnt),\n .prbs_gen_clk_en (prbs_gen_clk_en),\n .prbs_gen_oclk_clk_en (prbs_gen_oclk_clk_en),\n .complex_sample_cnt_inc(complex_sample_cnt_inc),\n .pi_dqs_found_start (pi_dqs_found_start),\n .dqsfound_retry (dqsfound_retry),\n .dqs_found_prech_req (dqs_found_prech_req),\n .pi_dqs_found_rank_done(pi_dqs_found_rank_done),\n .pi_dqs_found_done (pi_dqs_found_done),\n .detect_pi_found_dqs (detect_pi_found_dqs),\n .rd_data_offset_0 (rd_data_offset_0),\n .rd_data_offset_1 (rd_data_offset_1),\n .rd_data_offset_2 (rd_data_offset_2),\n .rd_data_offset_ranks_0(rd_data_offset_ranks_0),\n .rd_data_offset_ranks_1(rd_data_offset_ranks_1),\n .rd_data_offset_ranks_2(rd_data_offset_ranks_2),\n .wrcal_start (wrcal_start),\n .wrcal_rd_wait (wrcal_rd_wait),\n .wrcal_prech_req (wrcal_prech_req),\n .wrcal_resume (wrcal_resume_w),\n .wrcal_read_req (wrcal_read_req),\n .wrcal_act_req (wrcal_act_req),\n .wrcal_sanity_chk (wrcal_sanity_chk),\n .temp_wrcal_done (temp_wrcal_done),\n .wrcal_sanity_chk_done (wrcal_sanity_chk_done),\n .tg_timer_done (tg_timer_done),\n .no_rst_tg_mc (no_rst_tg_mc),\n .wrcal_done (wrcal_done),\n .prech_done (prech_done),\n .calib_writes (calib_writes),\n .init_calib_complete (calib_complete),\n .phy_address (phy_address),\n .phy_bank (phy_bank),\n .phy_cas_n (phy_cas_n),\n .phy_cs_n (phy_cs_n),\n .phy_ras_n (phy_ras_n),\n .phy_reset_n (phy_reset_n),\n .phy_we_n (phy_we_n),\n .phy_wrdata (phy_wrdata),\n .phy_rddata_en (phy_rddata_en),\n .phy_rddata_valid (phy_rddata_valid),\n .dbg_phy_init (dbg_phy_init),\n .reset_rd_addr (reset_rd_addr | complex_ocal_reset_rd_addr),\n .oclkdelay_center_calib_start (oclkdelay_center_calib_start),\n .oclk_center_write_resume (oclk_center_write_resume),\n .oclkdelay_center_calib_done (oclkdelay_center_calib_done),\n .rdlvl_pi_incdec (rdlvl_pi_incdec),\n .complex_act_start (complex_act_start),\n .complex_pi_incdec_done (complex_pi_incdec_done),\n .complex_init_pi_dec_done (complex_init_pi_dec_done),\n .num_samples_done_r (num_samples_done_r),\n .calib_tap_inc_start (calib_tap_inc_start),\n .calib_tap_end_if_reset (calib_tap_end_if_reset),\n .calib_tap_inc_done (calib_tap_inc_done)\n );\n\n\n //*****************************************************************\n // Write Calibration\n //*****************************************************************\n\n mig_7series_v4_0_ddr_phy_wrcal #\n (\n .TCQ (TCQ),\n .nCK_PER_CLK (nCK_PER_CLK),\n .CLK_PERIOD (CLK_PERIOD),\n .DQ_WIDTH (DQ_WIDTH),\n .DQS_CNT_WIDTH (DQS_CNT_WIDTH),\n .DQS_WIDTH (DQS_WIDTH),\n .DRAM_WIDTH (DRAM_WIDTH),\n .SIM_CAL_OPTION (SIM_CAL_OPTION)\n )\n u_ddr_phy_wrcal\n (\n .clk (clk),\n .rst (rst),\n .wrcal_start (wrcal_start),\n .wrcal_rd_wait (wrcal_rd_wait),\n .wrcal_sanity_chk (wrcal_sanity_chk),\n .dqsfound_retry_done (pi_dqs_found_done),\n .dqsfound_retry (dqsfound_retry),\n .wrcal_read_req (wrcal_read_req),\n .wrcal_act_req (wrcal_act_req),\n .phy_rddata_en (phy_rddata_en),\n .wrcal_done (wrcal_done),\n .wrcal_pat_err (wrcal_pat_err),\n .wrcal_prech_req (wrcal_prech_req),\n .temp_wrcal_done (temp_wrcal_done),\n .wrcal_sanity_chk_done (wrcal_sanity_chk_done),\n .prech_done (prech_done),\n .rd_data (phy_rddata),\n .wrcal_pat_resume (wrcal_pat_resume),\n .po_stg2_wrcal_cnt (po_stg2_wrcal_cnt),\n .phy_if_reset (phy_if_reset_w),\n .wl_po_coarse_cnt (wl_po_coarse_cnt),\n .wl_po_fine_cnt (wl_po_fine_cnt),\n .wrlvl_byte_redo (wrlvl_byte_redo),\n .wrlvl_byte_done (wrlvl_byte_done),\n .early1_data (early1_data),\n .early2_data (early2_data),\n .idelay_ld (idelay_ld),\n .dbg_phy_wrcal (dbg_phy_wrcal),\n .dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),\n .dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt)\n );\n\n\n\n //***************************************************************************\n // Write-leveling calibration logic\n //***************************************************************************\n\n generate\n if ((WRLVL == \"ON\") && (SKIP_CALIB == \"FALSE\")) begin: mb_wrlvl_inst\n\n mig_7series_v4_0_ddr_phy_wrlvl #\n (\n .TCQ (TCQ),\n .DQS_CNT_WIDTH (DQS_CNT_WIDTH),\n .DQ_WIDTH (DQ_WIDTH),\n .DQS_WIDTH (DQS_WIDTH),\n .DRAM_WIDTH (DRAM_WIDTH),\n .RANKS (1),\n .CLK_PERIOD (CLK_PERIOD),\n .nCK_PER_CLK (nCK_PER_CLK),\n .SIM_CAL_OPTION (SIM_CAL_OPTION)\n )\n u_ddr_phy_wrlvl\n (\n .clk (clk),\n .rst (rst),\n .phy_ctl_ready (phy_ctl_ready),\n .wr_level_start (wrlvl_start),\n .wl_sm_start (wl_sm_start),\n .wrlvl_byte_redo (wrlvl_byte_redo),\n .wrcal_cnt (po_stg2_wrcal_cnt),\n .early1_data (early1_data),\n .early2_data (early2_data),\n .wrlvl_final (wrlvl_final_mux),\n .oclkdelay_calib_cnt (oclkdelay_calib_cnt),\n .wrlvl_byte_done (wrlvl_byte_done),\n .oclkdelay_calib_done (oclkdelay_calib_done),\n .rd_data_rise0 (phy_rddata[DQ_WIDTH-1:0]),\n .dqs_po_dec_done (dqs_po_dec_done),\n .phy_ctl_rdy_dly (phy_ctl_rdy_dly),\n .wr_level_done (wrlvl_done),\n .wrlvl_rank_done (wrlvl_rank_done),\n .done_dqs_tap_inc (done_dqs_tap_inc),\n .dqs_po_stg2_f_incdec (dqs_po_stg2_f_incdec),\n .dqs_po_en_stg2_f (dqs_po_en_stg2_f),\n .dqs_wl_po_stg2_c_incdec (dqs_wl_po_stg2_c_incdec),\n .dqs_wl_po_en_stg2_c (dqs_wl_po_en_stg2_c),\n .po_counter_read_val (po_counter_read_val),\n .po_stg2_wl_cnt (po_stg2_wl_cnt),\n .wrlvl_err (wrlvl_err),\n .wl_po_coarse_cnt (wl_po_coarse_cnt),\n .wl_po_fine_cnt (wl_po_fine_cnt),\n .dbg_wl_tap_cnt (dbg_tap_cnt_during_wrlvl),\n .dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),\n .dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),\n .dbg_dqs_count (),\n .dbg_wl_state (),\n .dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),\n .dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),\n .dbg_phy_wrlvl (dbg_phy_wrlvl)\n );\n\n\n mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay #\n (\n .TCQ (TCQ),\n .tCK (tCK),\n .DQS_CNT_WIDTH (DQS_CNT_WIDTH),\n .N_CTL_LANES (N_CTL_LANES),\n .SIM_CAL_OPTION(SIM_CAL_OPTION)\n )\n u_ddr_phy_ck_addr_cmd_delay\n (\n .clk (clk),\n .rst (rst),\n .cmd_delay_start (dqs_po_dec_done & pi_fine_dly_dec_done),\n .ctl_lane_cnt (ctl_lane_cnt),\n .po_stg2_f_incdec (cmd_po_stg2_f_incdec),\n .po_en_stg2_f (cmd_po_en_stg2_f),\n .po_stg2_c_incdec (cmd_po_stg2_c_incdec),\n .po_en_stg2_c (cmd_po_en_stg2_c),\n .po_ck_addr_cmd_delay_done (po_ck_addr_cmd_delay_done)\n );\n\n assign cmd_po_stg2_incdec_ddr2_c = 1'b0;\n assign cmd_po_en_stg2_ddr2_c = 1'b0;\n\n end else if ((WRLVL == \"ON\") && (SKIP_CALIB == \"TRUE\")) begin: wrlvl_on_skip_calib\n\n mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay #\n (\n .TCQ (TCQ),\n .tCK (tCK),\n .DQS_CNT_WIDTH (DQS_CNT_WIDTH),\n .N_CTL_LANES (N_CTL_LANES),\n .SIM_CAL_OPTION(SIM_CAL_OPTION)\n )\n u_ddr_phy_ck_addr_cmd_delay\n (\n .clk (clk),\n .rst (rst),\n .cmd_delay_start (skip_cal_po_pi_dec_done),\n .ctl_lane_cnt (ctl_lane_cnt),\n .po_stg2_f_incdec (cmd_po_stg2_f_incdec),\n .po_en_stg2_f (cmd_po_en_stg2_f),\n .po_stg2_c_incdec (cmd_po_stg2_c_incdec),\n .po_en_stg2_c (cmd_po_en_stg2_c),\n .po_ck_addr_cmd_delay_done (po_ck_addr_cmd_delay_done)\n );\n\n assign dqs_po_dec_done = 1'b1;\n assign wrlvl_byte_done = 1'b1;\n assign wrlvl_rank_done = 1'b1;\n assign phy_ctl_rdy_dly = 1'b1;\n assign done_dqs_tap_inc = 1'b1;\n assign po_stg2_wl_cnt = 'h0;\n assign wl_po_coarse_cnt = 'h0;\n assign wl_po_fine_cnt = 'h0;\n assign dbg_tap_cnt_during_wrlvl = 'h0;\n assign dbg_wl_edge_detect_valid = 'h0;\n assign dbg_rd_data_edge_detect = 'h0;\n assign dbg_wrlvl_fine_tap_cnt = 'h0;\n assign dbg_wrlvl_coarse_tap_cnt = 'h0;\n assign dbg_phy_wrlvl = 'h0;\n\n assign wrlvl_done = 1'b1;\n assign wrlvl_err = 1'b0;\n assign dqs_po_stg2_f_incdec = 1'b0;\n assign dqs_po_en_stg2_f = 1'b0;\n assign dqs_wl_po_en_stg2_c = 1'b0;\n assign dqs_wl_po_stg2_c_incdec = 1'b0;\n\n assign cmd_po_stg2_incdec_ddr2_c = 1'b0;\n assign cmd_po_en_stg2_ddr2_c = 1'b0;\n\n end else begin: mb_wrlvl_off\n\n mig_7series_v4_0_ddr_phy_wrlvl_off_delay #\n (\n .TCQ (TCQ),\n .tCK (tCK),\n .nCK_PER_CLK (nCK_PER_CLK),\n .CLK_PERIOD (CLK_PERIOD),\n .PO_INITIAL_DLY(60),\n .DQS_CNT_WIDTH (DQS_CNT_WIDTH),\n .DQS_WIDTH (DQS_WIDTH),\n .N_CTL_LANES (N_CTL_LANES)\n )\n u_phy_wrlvl_off_delay\n (\n .clk (clk),\n .rst (rst),\n .pi_fine_dly_dec_done (pi_fine_dly_dec_done),\n .cmd_delay_start (phy_ctl_ready),\n .ctl_lane_cnt (ctl_lane_cnt),\n .po_s2_incdec_f (cmd_po_stg2_f_incdec),\n .po_en_s2_f (cmd_po_en_stg2_f),\n .po_s2_incdec_c (cmd_po_stg2_incdec_ddr2_c),\n .po_en_s2_c (cmd_po_en_stg2_ddr2_c),\n .po_ck_addr_cmd_delay_done (po_ck_addr_cmd_delay_done),\n .po_dec_done (dqs_po_dec_done),\n .phy_ctl_rdy_dly (phy_ctl_rdy_dly)\n );\n\n assign wrlvl_byte_done = 1'b1;\n assign wrlvl_rank_done = 1'b1;\n assign po_stg2_wl_cnt = 'h0;\n assign wl_po_coarse_cnt = 'h0;\n assign wl_po_fine_cnt = 'h0;\n assign dbg_tap_cnt_during_wrlvl = 'h0;\n assign dbg_wl_edge_detect_valid = 'h0;\n assign dbg_rd_data_edge_detect = 'h0;\n assign dbg_wrlvl_fine_tap_cnt = 'h0;\n assign dbg_wrlvl_coarse_tap_cnt = 'h0;\n assign dbg_phy_wrlvl = 'h0;\n\n assign wrlvl_done = 1'b1;\n assign wrlvl_err = 1'b0;\n assign dqs_po_stg2_f_incdec = 1'b0;\n assign dqs_po_en_stg2_f = 1'b0;\n assign dqs_wl_po_en_stg2_c = 1'b0;\n assign cmd_po_stg2_c_incdec = 1'b0;\n assign dqs_wl_po_stg2_c_incdec = 1'b0;\n assign cmd_po_en_stg2_c = 1'b0;\n\n end\n endgenerate\n\n generate\n if((WRLVL == \"ON\") && (OCAL_EN == \"ON\")) begin: oclk_calib\n\n localparam SAMPCNTRWIDTH = 17;\n localparam SAMPLES = (SIM_CAL_OPTION==\"NONE\") ? 512 : 4; //MG from 2048\n localparam TAPCNTRWIDTH = clogb2(TAPSPERKCLK);\n localparam MMCM_SAMP_WAIT = (SIM_CAL_OPTION==\"NONE\") ? 256 : 10;\n localparam OCAL_SIMPLE_SCAN_SAMPS = (SIM_CAL_OPTION==\"NONE\") ? 512 : 1; //MG from 2048\n localparam POC_PCT_SAMPS_SOLID = 80;\n localparam SCAN_PCT_SAMPS_SOLID = 95;\n\n mig_7series_v4_0_ddr_phy_oclkdelay_cal #\n (/*AUTOINSTPARAM*/\n // Parameters\n .DQS_CNT_WIDTH (DQS_CNT_WIDTH),\n .DQS_WIDTH (DQS_WIDTH),\n .DQ_WIDTH (DQ_WIDTH),\n //.DRAM_TYPE (DRAM_TYPE),\n .DRAM_WIDTH (DRAM_WIDTH),\n //.OCAL_EN (OCAL_EN),\n .OCAL_SIMPLE_SCAN_SAMPS (OCAL_SIMPLE_SCAN_SAMPS),\n .PCT_SAMPS_SOLID (POC_PCT_SAMPS_SOLID),\n .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP),\n .SCAN_PCT_SAMPS_SOLID (SCAN_PCT_SAMPS_SOLID),\n .SAMPCNTRWIDTH (SAMPCNTRWIDTH),\n .SAMPLES (SAMPLES),\n .MMCM_SAMP_WAIT (MMCM_SAMP_WAIT),\n .SIM_CAL_OPTION (SIM_CAL_OPTION),\n .TAPCNTRWIDTH (TAPCNTRWIDTH),\n .TAPSPERKCLK (TAPSPERKCLK),\n .TCQ (TCQ),\n .nCK_PER_CLK (nCK_PER_CLK),\n .BYPASS_COMPLEX_OCAL (BYPASS_COMPLEX_OCAL)\n //.tCK (tCK)\n )\n u_ddr_phy_oclkdelay_cal\n (/*AUTOINST*/\n // Outputs\n .prbs_ignore_first_byte (prbs_ignore_first_byte),\n .prbs_ignore_last_bytes (prbs_ignore_last_bytes),\n .complex_oclkdelay_calib_done (complex_oclkdelay_calib_done),\n .dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data[16*DRAM_WIDTH-1:0]),\n .dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal[255:0]),\n .lim2init_write_request (lim2init_write_request),\n .lim_done (lim_done),\n .oclk_calib_resume (oclk_calib_resume),\n .oclk_prech_req (oclk_prech_req),\n .oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]),\n .oclkdelay_calib_done (oclkdelay_calib_done),\n .po_en_stg23 (po_en_stg23),\n .po_stg23_incdec (po_stg23_incdec),\n .po_stg23_sel (po_stg23_sel),\n .psen (psen),\n .psincdec (psincdec),\n .wrlvl_final (wrlvl_final),\n .rd_victim_sel (complex_ocal_rd_victim_sel),\n .ocal_num_samples_done_r (complex_ocal_num_samples_done_r),\n .complex_wrlvl_final (complex_wrlvl_final),\n .poc_error (poc_error),\n // Inputs\n .clk (clk),\n .complex_oclkdelay_calib_start (complex_oclkdelay_calib_start_w),\n .metaQ (pd_out),\n //.oclk_init_delay_start (oclk_init_delay_start),\n .po_counter_read_val (po_counter_read_val),\n .oclkdelay_calib_start (oclkdelay_calib_start),\n .oclkdelay_init_val (oclkdelay_init_val[5:0]),\n .poc_sample_pd (poc_sample_pd),\n .phy_rddata (phy_rddata[2*nCK_PER_CLK*DQ_WIDTH-1:0]),\n .phy_rddata_en (phy_rddata_en),\n .prbs_o (prbs_o[2*nCK_PER_CLK*DQ_WIDTH-1:0]),\n .prech_done (prech_done),\n .psdone (psdone),\n .rst (rst),\n .wl_po_fine_cnt (wl_po_fine_cnt[6*DQS_WIDTH-1:0]),\n .ocal_num_samples_inc (complex_ocal_num_samples_inc),\n .oclkdelay_center_calib_start (oclkdelay_center_calib_start),\n .oclk_center_write_resume (oclk_center_write_resume),\n .oclkdelay_center_calib_done (oclkdelay_center_calib_done),\n .dbg_ocd_lim (dbg_ocd_lim),\n .dbg_poc (dbg_poc[1023:0]) );\n\n end else begin : oclk_calib_disabled\n\n assign wrlvl_final = 'b0;\n assign psen = 'b0;\n assign psincdec = 'b0;\n assign po_stg23_sel = 'b0;\n assign po_stg23_incdec = 'b0;\n assign po_en_stg23 = 'b0;\n assign oclkdelay_calib_cnt = 'b0;\n assign oclk_prech_req = 'b0;\n assign oclk_calib_resume = 'b0;\n assign oclkdelay_calib_done = 1'b1;\n assign dbg_phy_oclkdelay_cal = 'h0;\n assign dbg_oclkdelay_rd_data = 'h0;\n\n end\n endgenerate\n //***************************************************************************\n // Read data-offset calibration required for Phaser_In\n //***************************************************************************\n\n generate\n if(DQSFOUND_CAL == \"RIGHT\") begin: dqsfind_calib_right\n mig_7series_v4_0_ddr_phy_dqs_found_cal #\n (\n .TCQ (TCQ),\n .nCK_PER_CLK (nCK_PER_CLK),\n .nCL (nCL),\n .AL (AL),\n .nCWL (nCWL),\n //.RANKS (RANKS),\n .RANKS (1),\n .DQS_CNT_WIDTH (DQS_CNT_WIDTH),\n .DQS_WIDTH (DQS_WIDTH),\n .DRAM_WIDTH (DRAM_WIDTH),\n .REG_CTRL (REG_CTRL),\n .SIM_CAL_OPTION (SIM_CAL_OPTION),\n .DRAM_TYPE (DRAM_TYPE),\n .NUM_DQSFOUND_CAL (NUM_DQSFOUND_CAL),\n .N_CTL_LANES (DQS_FOUND_N_CTL_LANES),\n .HIGHEST_LANE (HIGHEST_LANE),\n .HIGHEST_BANK (HIGHEST_BANK),\n .BYTE_LANES_B0 (BYTE_LANES_B0),\n .BYTE_LANES_B1 (BYTE_LANES_B1),\n .BYTE_LANES_B2 (BYTE_LANES_B2),\n .BYTE_LANES_B3 (BYTE_LANES_B3),\n .BYTE_LANES_B4 (BYTE_LANES_B4),\n .DATA_CTL_B0 (DATA_CTL_B0),\n .DATA_CTL_B1 (DATA_CTL_B1),\n .DATA_CTL_B2 (DATA_CTL_B2),\n .DATA_CTL_B3 (DATA_CTL_B3),\n .DATA_CTL_B4 (DATA_CTL_B4)\n )\n u_ddr_phy_dqs_found_cal\n (\n .clk (clk),\n .rst (rst),\n .pi_dqs_found_start (pi_dqs_found_start),\n .dqsfound_retry (dqsfound_retry),\n .detect_pi_found_dqs (detect_pi_found_dqs),\n .prech_done (prech_done),\n .pi_dqs_found_lanes (pi_dqs_found_lanes),\n .pi_rst_stg1_cal (pi_rst_stg1_cal),\n .rd_data_offset_0 (rd_data_offset_0),\n .rd_data_offset_1 (rd_data_offset_1),\n .rd_data_offset_2 (rd_data_offset_2),\n .pi_dqs_found_rank_done (pi_dqs_found_rank_done),\n .pi_dqs_found_done (pi_dqs_found_done),\n .dqsfound_retry_done (dqsfound_retry_done),\n .dqs_found_prech_req (dqs_found_prech_req),\n .pi_dqs_found_err (pi_dqs_found_err),\n .rd_data_offset_ranks_0 (rd_data_offset_ranks_0),\n .rd_data_offset_ranks_1 (rd_data_offset_ranks_1),\n .rd_data_offset_ranks_2 (rd_data_offset_ranks_2),\n .rd_data_offset_ranks_mc_0 (rd_data_offset_ranks_mc_0),\n .rd_data_offset_ranks_mc_1 (rd_data_offset_ranks_mc_1),\n .rd_data_offset_ranks_mc_2 (rd_data_offset_ranks_mc_2),\n .po_counter_read_val (po_counter_read_val),\n .rd_data_offset_cal_done (rd_data_offset_cal_done),\n .fine_adjust_done (fine_adjust_done),\n .fine_adjust_lane_cnt (fine_adjust_lane_cnt),\n .ck_po_stg2_f_indec (ck_po_stg2_f_indec),\n .ck_po_stg2_f_en (ck_po_stg2_f_en),\n .dbg_dqs_found_cal (dbg_dqs_found_cal)\n );\n end else begin: dqsfind_calib_left\n mig_7series_v4_0_ddr_phy_dqs_found_cal_hr #\n (\n .TCQ (TCQ),\n .nCK_PER_CLK (nCK_PER_CLK),\n .nCL (nCL),\n .AL (AL),\n .nCWL (nCWL),\n //.RANKS (RANKS),\n .RANKS (1),\n .DQS_CNT_WIDTH (DQS_CNT_WIDTH),\n .DQS_WIDTH (DQS_WIDTH),\n .DRAM_WIDTH (DRAM_WIDTH),\n .REG_CTRL (REG_CTRL),\n .SIM_CAL_OPTION (SIM_CAL_OPTION),\n .DRAM_TYPE (DRAM_TYPE),\n .NUM_DQSFOUND_CAL (NUM_DQSFOUND_CAL),\n .N_CTL_LANES (DQS_FOUND_N_CTL_LANES),\n .HIGHEST_LANE (HIGHEST_LANE),\n .HIGHEST_BANK (HIGHEST_BANK),\n .BYTE_LANES_B0 (BYTE_LANES_B0),\n .BYTE_LANES_B1 (BYTE_LANES_B1),\n .BYTE_LANES_B2 (BYTE_LANES_B2),\n .BYTE_LANES_B3 (BYTE_LANES_B3),\n .BYTE_LANES_B4 (BYTE_LANES_B4),\n .DATA_CTL_B0 (DATA_CTL_B0),\n .DATA_CTL_B1 (DATA_CTL_B1),\n .DATA_CTL_B2 (DATA_CTL_B2),\n .DATA_CTL_B3 (DATA_CTL_B3),\n .DATA_CTL_B4 (DATA_CTL_B4)\n )\n u_ddr_phy_dqs_found_cal_hr\n (\n .clk (clk),\n .rst (rst),\n .pi_dqs_found_start (pi_dqs_found_start),\n .dqsfound_retry (dqsfound_retry),\n .detect_pi_found_dqs (detect_pi_found_dqs),\n .prech_done (prech_done),\n .pi_dqs_found_lanes (pi_dqs_found_lanes),\n .pi_rst_stg1_cal (pi_rst_stg1_cal),\n .rd_data_offset_0 (rd_data_offset_0),\n .rd_data_offset_1 (rd_data_offset_1),\n .rd_data_offset_2 (rd_data_offset_2),\n .pi_dqs_found_rank_done (pi_dqs_found_rank_done),\n .pi_dqs_found_done (pi_dqs_found_done),\n .dqsfound_retry_done (dqsfound_retry_done),\n .dqs_found_prech_req (dqs_found_prech_req),\n .pi_dqs_found_err (pi_dqs_found_err),\n .rd_data_offset_ranks_0 (rd_data_offset_ranks_0),\n .rd_data_offset_ranks_1 (rd_data_offset_ranks_1),\n .rd_data_offset_ranks_2 (rd_data_offset_ranks_2),\n .rd_data_offset_ranks_mc_0 (rd_data_offset_ranks_mc_0),\n .rd_data_offset_ranks_mc_1 (rd_data_offset_ranks_mc_1),\n .rd_data_offset_ranks_mc_2 (rd_data_offset_ranks_mc_2),\n .po_counter_read_val (po_counter_read_val),\n .rd_data_offset_cal_done (rd_data_offset_cal_done),\n .fine_adjust_done (fine_adjust_done),\n .fine_adjust_lane_cnt (fine_adjust_lane_cnt),\n .ck_po_stg2_f_indec (ck_po_stg2_f_indec),\n .ck_po_stg2_f_en (ck_po_stg2_f_en),\n .dbg_dqs_found_cal (dbg_dqs_found_cal)\n );\n end\n endgenerate\n\n //***************************************************************************\n // Read-leveling calibration logic\n //***************************************************************************\ngenerate\nif (SKIP_CALIB == \"FALSE\") begin:ddr_phy_rdlvl_gen\n mig_7series_v4_0_ddr_phy_rdlvl #\n (\n .TCQ (TCQ),\n .nCK_PER_CLK (nCK_PER_CLK),\n .CLK_PERIOD (CLK_PERIOD),\n .DQ_WIDTH (DQ_WIDTH),\n .DQS_CNT_WIDTH (DQS_CNT_WIDTH),\n .DQS_WIDTH (DQS_WIDTH),\n .DRAM_WIDTH (DRAM_WIDTH),\n .RANKS (1),\n .PER_BIT_DESKEW (PER_BIT_DESKEW),\n .SIM_CAL_OPTION (SIM_CAL_OPTION),\n .DEBUG_PORT (DEBUG_PORT),\n .DRAM_TYPE (DRAM_TYPE),\n .OCAL_EN (OCAL_EN),\n .IDELAY_ADJ (IDELAY_ADJ),\n .PI_DIV2_INCDEC (PI_DIV2_INCDEC)\n )\n u_ddr_phy_rdlvl\n (\n .clk (clk),\n .rst (rst),\n .mpr_rdlvl_done (mpr_rdlvl_done),\n .mpr_rdlvl_start (mpr_rdlvl_start),\n .mpr_last_byte_done (mpr_last_byte_done),\n .mpr_rnk_done (mpr_rnk_done),\n .rdlvl_stg1_start (rdlvl_stg1_start),\n .rdlvl_stg1_done (rdlvl_stg1_done),\n .rdlvl_stg1_rnk_done (rdlvl_stg1_rank_done),\n .rdlvl_stg1_err (rdlvl_stg1_err),\n .mpr_rdlvl_err (mpr_rdlvl_err),\n .rdlvl_err (rdlvl_err),\n .rdlvl_prech_req (rdlvl_prech_req),\n .rdlvl_last_byte_done (rdlvl_last_byte_done),\n .rdlvl_assrt_common (rdlvl_assrt_common),\n .prech_done (prech_done),\n .phy_if_empty (phy_if_empty),\n .idelaye2_init_val (idelaye2_init_val),\n .rd_data (phy_rddata),\n .pi_en_stg2_f (rdlvl_pi_stg2_f_en),\n .pi_stg2_f_incdec (rdlvl_pi_stg2_f_incdec),\n .pi_stg2_load (pi_stg2_load),\n .pi_stg2_reg_l (pi_stg2_reg_l),\n .dqs_po_dec_done (dqs_po_dec_done),\n .pi_counter_read_val (pi_counter_read_val),\n .pi_fine_dly_dec_done (pi_fine_dly_dec_done),\n .idelay_ce (idelay_ce_int),\n .idelay_inc (idelay_inc_int),\n .idelay_ld (idelay_ld),\n .wrcal_cnt (po_stg2_wrcal_cnt),\n .pi_stg2_rdlvl_cnt (pi_stg2_rdlvl_cnt),\n .dlyval_dq (dlyval_dq),\n .rdlvl_pi_incdec (rdlvl_pi_incdec),\n .dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),\n .dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),\n .dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),\n .dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),\n .dbg_idel_up_all (dbg_idel_up_all),\n .dbg_idel_down_all (dbg_idel_down_all),\n .dbg_idel_up_cpt (dbg_idel_up_cpt),\n .dbg_idel_down_cpt (dbg_idel_down_cpt),\n .dbg_sel_idel_cpt (dbg_sel_idel_cpt),\n .dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),\n .dbg_phy_rdlvl (dbg_phy_rdlvl)\n );\nend else begin:ddr_phy_rdlvl_off\n\n assign mpr_rdlvl_done = 1'b1;\n assign mpr_last_byte_done = 1'b1;\n assign mpr_rnk_done = 1'b1;\n assign rdlvl_stg1_done = 1'b1;\n assign rdlvl_stg1_rank_done = 1'b1;\n assign rdlvl_last_byte_done = 1'b1;\n assign pi_fine_dly_dec_done = 1'b1;\n assign rdlvl_prech_req = 1'b0;\n assign rdlvl_stg1_err = 1'b0;\n assign mpr_rdlvl_err = 1'b0;\n assign rdlvl_err = 1'b0;\n assign rdlvl_assrt_common = 1'b0;\n assign rdlvl_pi_stg2_f_en = 1'b0;\n assign rdlvl_pi_stg2_f_incdec = 1'b0;\n assign pi_stg2_rdlvl_cnt = 'h0;\n assign idelay_ce_int = 1'b0;\n assign idelay_inc_int = 1'b0;\n assign rdlvl_pi_incdec = 1'b0;\n assign dbg_phy_rdlvl = 'h0;\n assign dbg_cpt_first_edge_cnt = 'h0;\n assign dbg_cpt_second_edge_cnt = 'h0;\n assign dbg_cpt_tap_cnt = 'h0;\n assign dbg_dq_idelay_tap_cnt = 'h0;\n\nend\nendgenerate\n\ngenerate\nif((DRAM_TYPE == \"DDR3\") && (nCK_PER_CLK == 4) && (BYPASS_COMPLEX_RDLVL==\"FALSE\")) begin:ddr_phy_prbs_rdlvl_gen\n mig_7series_v4_0_ddr_phy_prbs_rdlvl #\n (\n .TCQ (TCQ),\n .nCK_PER_CLK (nCK_PER_CLK),\n .DQ_WIDTH (DQ_WIDTH),\n .DQS_CNT_WIDTH (DQS_CNT_WIDTH),\n .DQS_WIDTH (DQS_WIDTH),\n .DRAM_WIDTH (DRAM_WIDTH),\n .RANKS (1),\n .SIM_CAL_OPTION (SIM_CAL_OPTION),\n .PRBS_WIDTH (PRBS_WIDTH),\n .FIXED_VICTIM (FIXED_VICTIM),\n .FINE_PER_BIT (FINE_PER_BIT),\n .CENTER_COMP_MODE (CENTER_COMP_MODE),\n .PI_VAL_ADJ (PI_VAL_ADJ)\n )\n u_ddr_phy_prbs_rdlvl\n (\n .clk (clk),\n .rst (rst),\n .prbs_rdlvl_start (prbs_rdlvl_start),\n .prbs_rdlvl_done (prbs_rdlvl_done_complex),\n .prbs_last_byte_done (prbs_last_byte_done),\n .prbs_rdlvl_prech_req (prbs_rdlvl_prech_req),\n .complex_sample_cnt_inc (complex_sample_cnt_inc),\n .prech_done (prech_done),\n .phy_if_empty (phy_if_empty),\n .rd_data (phy_rddata),\n .compare_data (prbs_o),\n .pi_counter_read_val (pi_counter_read_val),\n .pi_en_stg2_f (prbs_pi_stg2_f_en),\n .pi_stg2_f_incdec (prbs_pi_stg2_f_incdec),\n .dbg_prbs_rdlvl (dbg_prbs_rdlvl),\n .pi_stg2_prbs_rdlvl_cnt (pi_stg2_prbs_rdlvl_cnt),\n .prbs_final_dqs_tap_cnt_r (prbs_final_dqs_tap_cnt_r),\n .dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps),\n .dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps),\n .rd_victim_sel (rd_victim_sel),\n .complex_victim_inc (complex_victim_inc),\n .reset_rd_addr (reset_rd_addr),\n .fine_delay_incdec_pb (fine_delay_incdec_pb),\n .fine_delay_sel (fine_delay_sel),\n .complex_act_start (complex_act_start),\n .num_samples_done_r (num_samples_done_r),\n .complex_pi_incdec_done (complex_pi_incdec_done),\n .complex_init_pi_dec_done (complex_init_pi_dec_done)\n );\nend else begin:ddr_phy_prbs_rdlvl_off\n\n assign prbs_rdlvl_done_complex = rdlvl_stg1_done ;\n //assign prbs_last_byte_done = rdlvl_stg1_rank_done ;\n assign prbs_last_byte_done = rdlvl_stg1_done;\n assign reset_rd_addr = 1'b0;\n assign prbs_rdlvl_prech_req = 1'b0 ;\n assign prbs_pi_stg2_f_en = 1'b0 ;\n assign prbs_pi_stg2_f_incdec = 1'b0 ;\n assign pi_stg2_prbs_rdlvl_cnt = 'b0 ;\n assign dbg_prbs_rdlvl = 'h0 ;\n assign prbs_final_dqs_tap_cnt_r = {(6*DQS_WIDTH*RANKS){1'b0}};\n assign dbg_prbs_first_edge_taps = {(6*DQS_WIDTH*RANKS){1'b0}};\n assign dbg_prbs_second_edge_taps = {(6*DQS_WIDTH*RANKS){1'b0}};\n assign complex_pi_incdec_done = 'b0;\n assign complex_init_pi_dec_done = 'b1;\n assign num_samples_done_r = 'b0;\nend\nendgenerate\n\n //***************************************************************************\n // Inc/Dec Phaser_Out, Phaser_In, and IDELAY taps to match calibration values\n //***************************************************************************\n\n generate\n if (SKIP_CALIB == \"TRUE\") begin: gen_skip_calib_tap\n\n // Generate request to get calibration tap values per byte\n always @(posedge clk) begin\n if (rst)\n calib_tap_req <= #TCQ 1'b0;\n else if (phy_ctl_ready)\n calib_tap_req <= #TCQ 1'b1;\n end\n\n\n // Store calibration values to registers\n always @(posedge clk) begin\n if (rst) begin\n calib_po_coarse_tap_cnt <= #TCQ 'd0;\n calib_po_stage3_tap_cnt <= #TCQ 'd0;\n calib_po_stage2_tap_cnt <= #TCQ 'd0;\n calib_pi_stage2_tap_cnt <= #TCQ 'd0;\n calib_idelay_tap_cnt <= #TCQ 'd0;\n calib_device_temp <= #TCQ 'd0;\n end else if (calib_tap_load) begin\n case (calib_tap_addr[2:0])\n 3'b000:\n calib_po_coarse_tap_cnt[3*calib_tap_addr[6:3]+:3] <= #TCQ calib_tap_val[2:0];\n 3'b001:\n calib_po_stage3_tap_cnt[6*calib_tap_addr[6:3]+:6] <= #TCQ calib_tap_val[5:0];\n 3'b010:\n calib_po_stage2_tap_cnt[6*calib_tap_addr[6:3]+:6] <= #TCQ calib_tap_val[5:0];\n 3'b011:\n calib_pi_stage2_tap_cnt[6*calib_tap_addr[6:3]+:6] <= #TCQ calib_tap_val[5:0];\n 3'b100:\n calib_idelay_tap_cnt[5*calib_tap_addr[6:3]+:5] <= #TCQ calib_tap_val[4:0];\n 3'b110:\n if (&calib_tap_addr[6:3])\n calib_device_temp[7:0] <= #TCQ calib_tap_val[7:0];\n 3'b111:\n if (&calib_tap_addr[6:3])\n calib_device_temp[11:8] <= #TCQ calib_tap_val[3:0];\n default:\n calib_po_coarse_tap_cnt[3*calib_tap_addr[6:3]+:3] <= #TCQ calib_tap_val[2:0];\n endcase\n end\n end\n\n\n mig_7series_v4_0_ddr_skip_calib_tap #\n (\n .TCQ (TCQ),\n .DQS_WIDTH (DQS_WIDTH)\n )\n u_ddr_skip_calib_tap\n (\n .rst (rst),\n .clk (clk),\n .phy_ctl_ready (phy_ctl_ready),\n .load_done (calib_tap_load_done),\n .calib_tap_inc_start (calib_tap_inc_start),\n .calib_tap_inc_done (calib_tap_inc_done),\n .calib_tap_inc_byte_cnt (calib_tap_inc_byte_cnt),\n .calib_po_stage2_tap_cnt (calib_po_stage2_tap_cnt),\n .calib_po_stage3_tap_cnt (calib_po_stage3_tap_cnt),\n .calib_po_coarse_tap_cnt (calib_po_coarse_tap_cnt),\n .calib_pi_stage2_tap_cnt (calib_pi_stage2_tap_cnt),\n .calib_idelay_tap_cnt (calib_idelay_tap_cnt),\n .po_counter_read_val (po_counter_read_val),\n .pi_counter_read_val (pi_counter_read_val),\n .calib_po_f_en (calib_po_f_en),\n .calib_po_f_incdec (calib_po_f_incdec),\n .calib_po_sel_stg2stg3 (calib_po_sel_stg2stg3),\n .calib_po_c_en (calib_po_c_en),\n .calib_po_c_inc (calib_po_c_inc),\n .calib_pi_f_en (calib_pi_f_en),\n .calib_pi_f_incdec (calib_pi_f_incdec),\n .calib_idelay_ce (calib_idelay_ce),\n .calib_idelay_inc (calib_idelay_inc),\n .skip_cal_po_pi_dec_done (skip_cal_po_pi_dec_done),\n .coarse_dec_err (coarse_dec_err),\n .dbg_skip_cal (dbg_skip_cal)\n );\n\n // Generate tempmon_sample_en pulses for temperature adjustment\n reg [8:0] samp_en_cnt;\n\n always @ (posedge clk) begin\n if (rst || tempmon_done_skip || (samp_en_cnt == 'd0))\n samp_en_cnt <= #TCQ 'd267;\n else if (calib_complete && (samp_en_cnt > 'd0))\n samp_en_cnt <= #TCQ samp_en_cnt - 1;\n end\n\n always @ (posedge clk) begin\n if (rst || tempmon_done_skip)\n skip_cal_tempmon_samp_en <= #TCQ 1'b0;\n else if (samp_en_cnt == 'd260)\n skip_cal_tempmon_samp_en <= #TCQ 1'b1;\n else\n skip_cal_tempmon_samp_en <= #TCQ 1'b0;\n end\n\n\n\n end else begin: skip_calib_tap_off\n assign calib_po_f_en = 1'b0;\n assign calib_po_f_incdec = 1'b0;\n assign calib_po_sel_stg2stg3 = 1'b0;\n assign calib_po_c_en = 1'b0;\n assign calib_po_c_inc = 1'b0;\n assign calib_pi_f_en = 1'b0;\n assign calib_pi_f_incdec = 1'b0;\n assign calib_idelay_ce = 1'b0;\n assign calib_idelay_inc = 1'b0;\n assign calib_tap_inc_done = 1'b0;\n assign calib_tap_inc_byte_cnt = 'd0;\n assign skip_cal_po_pi_dec_done = 1'b1;\n\n always @(posedge clk) begin\n calib_tap_req <= #TCQ 1'b0;\n calib_device_temp <= #TCQ 'd0;\n skip_cal_tempmon_samp_en <= #TCQ 1'b0;\n end\n\nend\nendgenerate\n\n //***************************************************************************\n // Temperature induced PI tap adjustment logic\n //***************************************************************************\n\n mig_7series_v4_0_ddr_phy_tempmon #\n (\n .SKIP_CALIB (SKIP_CALIB),\n .TCQ (TCQ)\n )\n ddr_phy_tempmon_0\n (\n .rst (rst),\n .clk (clk),\n .calib_complete (calib_complete),\n .tempmon_pi_f_inc (tempmon_pi_f_inc),\n .tempmon_pi_f_dec (tempmon_pi_f_dec),\n .tempmon_sel_pi_incdec (tempmon_sel_pi_incdec),\n .device_temp (device_temp),\n .calib_device_temp (calib_device_temp),\n .tempmon_sample_en (tempmon_sample_en | skip_cal_tempmon_samp_en),\n .tempmon_done_skip (tempmon_done_skip)\n );\n\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_if_post_fifo.v", "content": "//*****************************************************************************\n// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor : Xilinx\n// \\ \\ \\/ Version : %version\n// \\ \\ Application : MIG\n// / / Filename : mig_7series_v1_x_ddr_if_post_fifo.v\n// /___/ /\\ Date Last Modified : $date$\n// \\ \\ / \\ Date Created : Feb 08 2011\n// \\___\\/\\___\\\n//\n//Device : 7 Series\n//Design Name : DDR3 SDRAM\n//Purpose : Extends the depth of a PHASER IN_FIFO up to 4 entries\n//Reference :\n//Revision History :\n//*****************************************************************************\n\n`timescale 1 ps / 1 ps\n\nmodule mig_7series_v4_0_ddr_if_post_fifo #\n (\n parameter TCQ = 100, // clk->out delay (sim only)\n parameter DEPTH = 4, // # of entries\n parameter WIDTH = 32 // data bus width\n )\n (\n input clk, // clock\n input rst, // synchronous reset\n input [3:0] empty_in,\n input rd_en_in,\n input [WIDTH-1:0] d_in, // write data from controller\n output empty_out,\n output byte_rd_en,\n output [WIDTH-1:0] d_out // write data to OUT_FIFO\n );\n \n // # of bits used to represent read/write pointers\n localparam PTR_BITS \n = (DEPTH == 2) ? 1 : \n (((DEPTH == 3) || (DEPTH == 4)) ? 2 : 'bx);\n\n integer i;\n \n reg [WIDTH-1:0] mem[0:DEPTH-1];\n (* max_fanout = 40 *) reg [4:0] my_empty /* synthesis syn_maxfan = 3 */;\n (* max_fanout = 40 *) reg [1:0] my_full /* synthesis syn_maxfan = 3 */;\n reg [PTR_BITS-1:0] rd_ptr /* synthesis syn_maxfan = 10 */;\n // Register duplication to reduce the fan out\n (* KEEP = \"TRUE\" *) reg [PTR_BITS-1:0] rd_ptr_timing /* synthesis syn_maxfan = 10 */;\n reg [PTR_BITS-1:0] wr_ptr /* synthesis syn_maxfan = 10 */;\n wire [WIDTH-1:0] mem_out;\n (* max_fanout = 40 *) wire wr_en /* synthesis syn_maxfan = 10 */;\n\n task updt_ptrs;\n input rd;\n input wr;\n reg [1:0] next_rd_ptr;\n reg [1:0] next_wr_ptr;\n begin\n next_rd_ptr = (rd_ptr + 1'b1)%DEPTH;\n next_wr_ptr = (wr_ptr + 1'b1)%DEPTH;\n casez ({rd, wr, my_empty[1], my_full[1]})\n 4'b00zz: ; // No access, do nothing\n 4'b0100: begin\n // Write when neither empty, nor full; check for full\n wr_ptr <= #TCQ next_wr_ptr;\n my_full[0] <= #TCQ (next_wr_ptr == rd_ptr);\n my_full[1] <= #TCQ (next_wr_ptr == rd_ptr);\n //mem[wr_ptr] <= #TCQ d_in;\n end\n 4'b0110: begin\n // Write when empty; no need to check for full\n wr_ptr <= #TCQ next_wr_ptr;\n my_empty <= #TCQ 5'b00000;\n //mem[wr_ptr] <= #TCQ d_in;\n end \n 4'b1000: begin\n // Read when neither empty, nor full; check for empty\n rd_ptr <= #TCQ next_rd_ptr;\n rd_ptr_timing <= #TCQ next_rd_ptr;\n my_empty[0] <= #TCQ (next_rd_ptr == wr_ptr);\n my_empty[1] <= #TCQ (next_rd_ptr == wr_ptr);\n my_empty[2] <= #TCQ (next_rd_ptr == wr_ptr);\n my_empty[3] <= #TCQ (next_rd_ptr == wr_ptr);\n my_empty[4] <= #TCQ (next_rd_ptr == wr_ptr);\n end\n 4'b1001: begin\n // Read when full; no need to check for empty\n rd_ptr <= #TCQ next_rd_ptr;\n rd_ptr_timing <= #TCQ next_rd_ptr;\n my_full[0] <= #TCQ 1'b0;\n my_full[1] <= #TCQ 1'b0;\n end\n 4'b1100, 4'b1101, 4'b1110: begin\n // Read and write when empty, full, or neither empty/full; no need \n // to check for empty or full conditions\n rd_ptr <= #TCQ next_rd_ptr;\n rd_ptr_timing <= #TCQ next_rd_ptr;\n wr_ptr <= #TCQ next_wr_ptr;\n //mem[wr_ptr] <= #TCQ d_in;\n end\n 4'b0101, 4'b1010: ;\n // Read when empty, Write when full; Keep all pointers the same\n // and don't change any of the flags (i.e. ignore the read/write). \n // This might happen because a faulty DQS_FOUND calibration could \n // result in excessive skew between when the various IN_FIFO's\n // first become not empty. In this case, the data going to each\n // post-FIFO/IN_FIFO should be read out and discarded\n // synthesis translate_off\n default: begin\n // Covers any other cases, in particular for simulation if\n // any signals are X's\n $display(\"ERR %m @%t: Bad access: rd:%b,wr:%b,empty:%b,full:%b\", \n $time, rd, wr, my_empty[1], my_full[1]); \n rd_ptr <= #TCQ 2'bxx;\n rd_ptr_timing <= #TCQ 2'bxx;\n wr_ptr <= #TCQ 2'bxx;\n end\n // synthesis translate_on\n endcase\n end\n endtask\n\n\n assign d_out = my_empty[4] ? d_in : mem_out;//mem[rd_ptr];\n // The combined IN_FIFO + post FIFO is only \"empty\" when both are empty\n assign empty_out = empty_in[0] & my_empty[0];\n assign byte_rd_en = !empty_in[3] || !my_empty[3];\n \n always @(posedge clk) \n if (rst) begin\n my_empty <= #TCQ 5'b11111;\n my_full <= #TCQ 2'b00;\n rd_ptr <= #TCQ 'b0;\n rd_ptr_timing <= #TCQ 'b0;\n wr_ptr <= #TCQ 'b0;\n end else begin\n // Special mode: If IN_FIFO has data, and controller is reading at\n // the same time, then operate post-FIFO in \"passthrough\" mode (i.e. \n // don't update any of the read/write pointers, and route IN_FIFO\n // data to post-FIFO data)\n if (my_empty[1] && !my_full[1] && rd_en_in && !empty_in[1]) ;\n else\n // Otherwise, we're writing to FIFO when IN_FIFO is not empty,\n // and reading from the FIFO based on the rd_en_in signal (read\n // enable from controller). The functino updt_ptrs should catch\n // an illegal conditions. \n updt_ptrs(rd_en_in, !empty_in[1]);\n end\n\n\n assign wr_en = (!empty_in[2] & ((!rd_en_in & !my_full[0]) |\n (rd_en_in & !my_empty[2])));\n \n \n always @ (posedge clk)\n begin\n if (wr_en)\n mem[wr_ptr] <= #TCQ d_in;\n end\n \n assign mem_out = mem[rd_ptr_timing];\n\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_mc_phy.v", "content": "/***********************************************************\n-- (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). A Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n\n//\n//\n// Owner: Gary Martin\n// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/mc_phy.v#5 $\n// $Author: gary $\n// $DateTime: 2010/05/11 18:05:17 $\n// $Change: 490882 $\n// Description:\n// This verilog file is a parameterizable wrapper instantiating\n// up to 5 memory banks of 4-lane phy primitives. There\n// There are always 2 control banks leaving 18 lanes for data.\n//\n// History:\n// Date Engineer Description\n// 04/01/2010 G. Martin Initial Checkin.\n//\n////////////////////////////////////////////////////////////\n***********************************************************/\n\n\n`timescale 1ps/1ps\n\nmodule mig_7series_v4_0_ddr_mc_phy\n #(\n// five fields, one per possible I/O bank, 4 bits in each field, 1 per lane data=1/ctl=0\n parameter BYTE_LANES_B0 = 4'b1111,\n parameter BYTE_LANES_B1 = 4'b0000,\n parameter BYTE_LANES_B2 = 4'b0000,\n parameter BYTE_LANES_B3 = 4'b0000,\n parameter BYTE_LANES_B4 = 4'b0000,\n parameter DATA_CTL_B0 = 4'hc,\n parameter DATA_CTL_B1 = 4'hf,\n parameter DATA_CTL_B2 = 4'hf,\n parameter DATA_CTL_B3 = 4'hf,\n parameter DATA_CTL_B4 = 4'hf,\n parameter RCLK_SELECT_BANK = 0,\n parameter RCLK_SELECT_LANE = \"B\",\n parameter RCLK_SELECT_EDGE = 4'b1111,\n parameter GENERATE_DDR_CK_MAP = \"0B\",\n parameter BYTELANES_DDR_CK = 72'h00_0000_0000_0000_0002,\n parameter USE_PRE_POST_FIFO = \"TRUE\",\n parameter SYNTHESIS = \"FALSE\",\n parameter PO_CTL_COARSE_BYPASS = \"FALSE\",\n parameter PI_SEL_CLK_OFFSET = 6,\n\n parameter PHYCTL_CMD_FIFO = \"FALSE\",\n parameter PHY_CLK_RATIO = 4, // phy to controller divide ratio\n\n// common to all i/o banks\n parameter PHY_FOUR_WINDOW_CLOCKS = 63,\n parameter PHY_EVENTS_DELAY = 18,\n parameter PHY_COUNT_EN = \"TRUE\",\n parameter PHY_SYNC_MODE = \"TRUE\",\n parameter PHY_DISABLE_SEQ_MATCH = \"FALSE\",\n parameter MASTER_PHY_CTL = 0,\n// common to instance 0\n parameter PHY_0_BITLANES = 48'hdffd_fffe_dfff,\n parameter PHY_0_BITLANES_OUTONLY = 48'h0000_0000_0000,\n parameter PHY_0_LANE_REMAP = 16'h3210,\n parameter PHY_0_GENERATE_IDELAYCTRL = \"FALSE\",\n parameter PHY_0_IODELAY_GRP = \"IODELAY_MIG\",\n parameter FPGA_SPEED_GRADE = 1,\n parameter BANK_TYPE = \"HP_IO\", // # = \"HP_IO\", \"HPL_IO\", \"HR_IO\", \"HRL_IO\"\n parameter NUM_DDR_CK = 1,\n parameter PHY_0_DATA_CTL = DATA_CTL_B0,\n parameter PHY_0_CMD_OFFSET = 0,\n parameter PHY_0_RD_CMD_OFFSET_0 = 0,\n parameter PHY_0_RD_CMD_OFFSET_1 = 0,\n parameter PHY_0_RD_CMD_OFFSET_2 = 0,\n parameter PHY_0_RD_CMD_OFFSET_3 = 0,\n parameter PHY_0_RD_DURATION_0 = 0,\n parameter PHY_0_RD_DURATION_1 = 0,\n parameter PHY_0_RD_DURATION_2 = 0,\n parameter PHY_0_RD_DURATION_3 = 0,\n parameter PHY_0_WR_CMD_OFFSET_0 = 0,\n parameter PHY_0_WR_CMD_OFFSET_1 = 0,\n parameter PHY_0_WR_CMD_OFFSET_2 = 0,\n parameter PHY_0_WR_CMD_OFFSET_3 = 0,\n parameter PHY_0_WR_DURATION_0 = 0,\n parameter PHY_0_WR_DURATION_1 = 0,\n parameter PHY_0_WR_DURATION_2 = 0,\n parameter PHY_0_WR_DURATION_3 = 0,\n parameter PHY_0_AO_WRLVL_EN = 0,\n parameter PHY_0_AO_TOGGLE = 4'b0101, // odd bits are toggle (CKE)\n parameter PHY_0_OF_ALMOST_FULL_VALUE = 1,\n parameter PHY_0_IF_ALMOST_EMPTY_VALUE = 1,\n// per lane parameters\n parameter PHY_0_A_PI_FREQ_REF_DIV = \"NONE\",\n parameter PHY_0_A_PI_CLKOUT_DIV = 2,\n parameter PHY_0_A_PO_CLKOUT_DIV = 2,\n parameter PHY_0_A_BURST_MODE = \"TRUE\",\n parameter PHY_0_A_PI_OUTPUT_CLK_SRC = \"DELAYED_REF\",\n parameter PHY_0_A_PO_OUTPUT_CLK_SRC = \"DELAYED_REF\",\n parameter PHY_0_A_PO_OCLK_DELAY = 25,\n parameter PHY_0_B_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,\n parameter PHY_0_C_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,\n parameter PHY_0_D_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,\n parameter PHY_0_A_PO_OCLKDELAY_INV = \"FALSE\",\n parameter PHY_0_A_OF_ARRAY_MODE = \"ARRAY_MODE_8_X_4\",\n parameter PHY_0_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,\n parameter PHY_0_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,\n parameter PHY_0_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,\n parameter PHY_0_A_IF_ARRAY_MODE = \"ARRAY_MODE_8_X_4\",\n parameter PHY_0_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,\n parameter PHY_0_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,\n parameter PHY_0_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,\n parameter PHY_0_A_OSERDES_DATA_RATE = \"UNDECLARED\",\n parameter PHY_0_A_OSERDES_DATA_WIDTH = \"UNDECLARED\",\n parameter PHY_0_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,\n parameter PHY_0_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,\n parameter PHY_0_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,\n parameter PHY_0_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,\n parameter PHY_0_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,\n parameter PHY_0_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,\n parameter PHY_0_A_IDELAYE2_IDELAY_TYPE = \"VARIABLE\",\n parameter PHY_0_A_IDELAYE2_IDELAY_VALUE = 00,\n parameter PHY_0_B_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,\n parameter PHY_0_B_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,\n parameter PHY_0_C_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,\n parameter PHY_0_C_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,\n parameter PHY_0_D_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,\n parameter PHY_0_D_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,\n\n// common to instance 1\n parameter PHY_1_BITLANES = PHY_0_BITLANES,\n parameter PHY_1_BITLANES_OUTONLY = 48'h0000_0000_0000,\n parameter PHY_1_LANE_REMAP = 16'h3210,\n parameter PHY_1_GENERATE_IDELAYCTRL = \"FALSE\",\n parameter PHY_1_IODELAY_GRP = PHY_0_IODELAY_GRP,\n parameter PHY_1_DATA_CTL = DATA_CTL_B1,\n parameter PHY_1_CMD_OFFSET = PHY_0_CMD_OFFSET,\n parameter PHY_1_RD_CMD_OFFSET_0 = PHY_0_RD_CMD_OFFSET_0,\n parameter PHY_1_RD_CMD_OFFSET_1 = PHY_0_RD_CMD_OFFSET_1,\n parameter PHY_1_RD_CMD_OFFSET_2 = PHY_0_RD_CMD_OFFSET_2,\n parameter PHY_1_RD_CMD_OFFSET_3 = PHY_0_RD_CMD_OFFSET_3,\n parameter PHY_1_RD_DURATION_0 = PHY_0_RD_DURATION_0,\n parameter PHY_1_RD_DURATION_1 = PHY_0_RD_DURATION_1,\n parameter PHY_1_RD_DURATION_2 = PHY_0_RD_DURATION_2,\n parameter PHY_1_RD_DURATION_3 = PHY_0_RD_DURATION_3,\n parameter PHY_1_WR_CMD_OFFSET_0 = PHY_0_WR_CMD_OFFSET_0,\n parameter PHY_1_WR_CMD_OFFSET_1 = PHY_0_WR_CMD_OFFSET_1,\n parameter PHY_1_WR_CMD_OFFSET_2 = PHY_0_WR_CMD_OFFSET_2,\n parameter PHY_1_WR_CMD_OFFSET_3 = PHY_0_WR_CMD_OFFSET_3,\n parameter PHY_1_WR_DURATION_0 = PHY_0_WR_DURATION_0,\n parameter PHY_1_WR_DURATION_1 = PHY_0_WR_DURATION_1,\n parameter PHY_1_WR_DURATION_2 = PHY_0_WR_DURATION_2,\n parameter PHY_1_WR_DURATION_3 = PHY_0_WR_DURATION_3,\n parameter PHY_1_AO_WRLVL_EN = PHY_0_AO_WRLVL_EN,\n parameter PHY_1_AO_TOGGLE = PHY_0_AO_TOGGLE, // odd bits are toggle (CKE)\n parameter PHY_1_OF_ALMOST_FULL_VALUE = 1,\n parameter PHY_1_IF_ALMOST_EMPTY_VALUE = 1,\n// per lane parameters\n parameter PHY_1_A_PI_FREQ_REF_DIV = PHY_0_A_PI_FREQ_REF_DIV,\n parameter PHY_1_A_PI_CLKOUT_DIV = PHY_0_A_PI_CLKOUT_DIV,\n parameter PHY_1_A_PO_CLKOUT_DIV = PHY_0_A_PO_CLKOUT_DIV,\n parameter PHY_1_A_BURST_MODE = PHY_0_A_BURST_MODE,\n parameter PHY_1_A_PI_OUTPUT_CLK_SRC = PHY_0_A_PI_OUTPUT_CLK_SRC,\n parameter PHY_1_A_PO_OUTPUT_CLK_SRC = PHY_0_A_PO_OUTPUT_CLK_SRC ,\n parameter PHY_1_A_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,\n parameter PHY_1_B_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,\n parameter PHY_1_C_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,\n parameter PHY_1_D_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,\n parameter PHY_1_A_PO_OCLKDELAY_INV = PHY_0_A_PO_OCLKDELAY_INV,\n parameter PHY_1_A_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,\n parameter PHY_1_A_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,\n parameter PHY_1_B_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,\n parameter PHY_1_B_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,\n parameter PHY_1_C_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,\n parameter PHY_1_C_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,\n parameter PHY_1_D_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,\n parameter PHY_1_D_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,\n parameter PHY_1_A_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,\n parameter PHY_1_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,\n parameter PHY_1_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,\n parameter PHY_1_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,\n parameter PHY_1_A_IF_ARRAY_MODE = PHY_0_A_IF_ARRAY_MODE,\n parameter PHY_1_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,\n parameter PHY_1_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,\n parameter PHY_1_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,\n parameter PHY_1_A_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,\n parameter PHY_1_A_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,\n parameter PHY_1_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,\n parameter PHY_1_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,\n parameter PHY_1_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,\n parameter PHY_1_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,\n parameter PHY_1_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,\n parameter PHY_1_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,\n\n// common to instance 2\n parameter PHY_2_BITLANES = PHY_0_BITLANES,\n parameter PHY_2_BITLANES_OUTONLY = 48'h0000_0000_0000,\n parameter PHY_2_LANE_REMAP = 16'h3210,\n parameter PHY_2_GENERATE_IDELAYCTRL = \"FALSE\",\n parameter PHY_2_IODELAY_GRP = PHY_0_IODELAY_GRP,\n parameter PHY_2_DATA_CTL = DATA_CTL_B2,\n parameter PHY_2_CMD_OFFSET = PHY_0_CMD_OFFSET,\n parameter PHY_2_RD_CMD_OFFSET_0 = PHY_0_RD_CMD_OFFSET_0,\n parameter PHY_2_RD_CMD_OFFSET_1 = PHY_0_RD_CMD_OFFSET_1,\n parameter PHY_2_RD_CMD_OFFSET_2 = PHY_0_RD_CMD_OFFSET_2,\n parameter PHY_2_RD_CMD_OFFSET_3 = PHY_0_RD_CMD_OFFSET_3,\n parameter PHY_2_RD_DURATION_0 = PHY_0_RD_DURATION_0,\n parameter PHY_2_RD_DURATION_1 = PHY_0_RD_DURATION_1,\n parameter PHY_2_RD_DURATION_2 = PHY_0_RD_DURATION_2,\n parameter PHY_2_RD_DURATION_3 = PHY_0_RD_DURATION_3,\n parameter PHY_2_WR_CMD_OFFSET_0 = PHY_0_WR_CMD_OFFSET_0,\n parameter PHY_2_WR_CMD_OFFSET_1 = PHY_0_WR_CMD_OFFSET_1,\n parameter PHY_2_WR_CMD_OFFSET_2 = PHY_0_WR_CMD_OFFSET_2,\n parameter PHY_2_WR_CMD_OFFSET_3 = PHY_0_WR_CMD_OFFSET_3,\n parameter PHY_2_WR_DURATION_0 = PHY_0_WR_DURATION_0,\n parameter PHY_2_WR_DURATION_1 = PHY_0_WR_DURATION_1,\n parameter PHY_2_WR_DURATION_2 = PHY_0_WR_DURATION_2,\n parameter PHY_2_WR_DURATION_3 = PHY_0_WR_DURATION_3,\n parameter PHY_2_AO_WRLVL_EN = PHY_0_AO_WRLVL_EN,\n parameter PHY_2_AO_TOGGLE = PHY_0_AO_TOGGLE, // odd bits are toggle (CKE)\n parameter PHY_2_OF_ALMOST_FULL_VALUE = 1,\n parameter PHY_2_IF_ALMOST_EMPTY_VALUE = 1,\n// per lane parameters\n parameter PHY_2_A_PI_FREQ_REF_DIV = PHY_0_A_PI_FREQ_REF_DIV,\n parameter PHY_2_A_PI_CLKOUT_DIV = PHY_0_A_PI_CLKOUT_DIV ,\n parameter PHY_2_A_PO_CLKOUT_DIV = PHY_0_A_PO_CLKOUT_DIV,\n parameter PHY_2_A_BURST_MODE = PHY_0_A_BURST_MODE ,\n parameter PHY_2_A_PI_OUTPUT_CLK_SRC = PHY_0_A_PI_OUTPUT_CLK_SRC,\n parameter PHY_2_A_PO_OUTPUT_CLK_SRC = PHY_0_A_PO_OUTPUT_CLK_SRC,\n parameter PHY_2_A_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,\n parameter PHY_2_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,\n parameter PHY_2_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,\n parameter PHY_2_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,\n parameter PHY_2_A_IF_ARRAY_MODE = PHY_0_A_IF_ARRAY_MODE,\n parameter PHY_2_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,\n parameter PHY_2_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,\n parameter PHY_2_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,\n parameter PHY_2_A_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,\n parameter PHY_2_B_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,\n parameter PHY_2_C_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,\n parameter PHY_2_D_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,\n parameter PHY_2_A_PO_OCLKDELAY_INV = PHY_0_A_PO_OCLKDELAY_INV,\n parameter PHY_2_A_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,\n parameter PHY_2_A_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,\n parameter PHY_2_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,\n parameter PHY_2_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,\n parameter PHY_2_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,\n parameter PHY_2_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,\n parameter PHY_2_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,\n parameter PHY_2_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,\n parameter PHY_2_A_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,\n parameter PHY_2_A_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,\n parameter PHY_2_B_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,\n parameter PHY_2_B_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,\n parameter PHY_2_C_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,\n parameter PHY_2_C_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,\n parameter PHY_2_D_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,\n parameter PHY_2_D_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,\n parameter PHY_0_IS_LAST_BANK = ((BYTE_LANES_B1 != 0) || (BYTE_LANES_B2 != 0) || (BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0)) ? \"FALSE\" : \"TRUE\",\n parameter PHY_1_IS_LAST_BANK = ((BYTE_LANES_B1 != 0) && ((BYTE_LANES_B2 != 0) || (BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0))) ? \"FALSE\" : ((PHY_0_IS_LAST_BANK) ? \"FALSE\" : \"TRUE\"),\n parameter PHY_2_IS_LAST_BANK = (BYTE_LANES_B2 != 0) && ((BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0)) ? \"FALSE\" : ((PHY_0_IS_LAST_BANK || PHY_1_IS_LAST_BANK) ? \"FALSE\" : \"TRUE\"),\n parameter TCK = 2500,\n\n// local computational use, do not pass down\n parameter N_LANES = (0+BYTE_LANES_B0[0]) + (0+BYTE_LANES_B0[1]) + (0+BYTE_LANES_B0[2]) + (0+BYTE_LANES_B0[3])\n + (0+BYTE_LANES_B1[0]) + (0+BYTE_LANES_B1[1]) + (0+BYTE_LANES_B1[2]) + (0+BYTE_LANES_B1[3]) + (0+BYTE_LANES_B2[0]) + (0+BYTE_LANES_B2[1]) + (0+BYTE_LANES_B2[2]) + (0+BYTE_LANES_B2[3])\n , // must not delete comma for syntax\n parameter HIGHEST_BANK = (BYTE_LANES_B4 != 0 ? 5 : (BYTE_LANES_B3 != 0 ? 4 : (BYTE_LANES_B2 != 0 ? 3 : (BYTE_LANES_B1 != 0 ? 2 : 1)))),\n parameter HIGHEST_LANE_B0 = ((PHY_0_IS_LAST_BANK == \"FALSE\") ? 4 : BYTE_LANES_B0[3] ? 4 : BYTE_LANES_B0[2] ? 3 : BYTE_LANES_B0[1] ? 2 : BYTE_LANES_B0[0] ? 1 : 0) ,\n parameter HIGHEST_LANE_B1 = (HIGHEST_BANK > 2) ? 4 : ( BYTE_LANES_B1[3] ? 4 : BYTE_LANES_B1[2] ? 3 : BYTE_LANES_B1[1] ? 2 : BYTE_LANES_B1[0] ? 1 : 0) ,\n parameter HIGHEST_LANE_B2 = (HIGHEST_BANK > 3) ? 4 : ( BYTE_LANES_B2[3] ? 4 : BYTE_LANES_B2[2] ? 3 : BYTE_LANES_B2[1] ? 2 : BYTE_LANES_B2[0] ? 1 : 0) ,\n parameter HIGHEST_LANE_B3 = 0,\n parameter HIGHEST_LANE_B4 = 0,\n\n parameter HIGHEST_LANE = (HIGHEST_LANE_B4 != 0) ? (HIGHEST_LANE_B4+16) : ((HIGHEST_LANE_B3 != 0) ? (HIGHEST_LANE_B3 + 12) : ((HIGHEST_LANE_B2 != 0) ? (HIGHEST_LANE_B2 + 8) : ((HIGHEST_LANE_B1 != 0) ? (HIGHEST_LANE_B1 + 4) : HIGHEST_LANE_B0))),\n parameter LP_DDR_CK_WIDTH = 2,\n parameter GENERATE_SIGNAL_SPLIT = \"FALSE\"\n ,parameter CKE_ODT_AUX = \"FALSE\"\n ,parameter PI_DIV2_INCDEC = \"FALSE\"\n )\n (\n input rst,\n input ddr_rst_in_n ,\n input phy_clk,\n input clk_div2,\n input freq_refclk,\n input mem_refclk,\n input mem_refclk_div4,\n input pll_lock,\n input sync_pulse,\n input auxout_clk,\n input idelayctrl_refclk,\n input [HIGHEST_LANE*80-1:0] phy_dout,\n input phy_cmd_wr_en,\n input phy_data_wr_en,\n input phy_rd_en,\n input [31:0] phy_ctl_wd,\n input [3:0] aux_in_1,\n input [3:0] aux_in_2,\n input [5:0] data_offset_1,\n input [5:0] data_offset_2,\n input phy_ctl_wr,\n input if_rst,\n input if_empty_def,\n input cke_in,\n input idelay_ce,\n input idelay_ld,\n input idelay_inc,\n input phyGo,\n input input_sink,\n output if_a_empty,\n output if_empty /* synthesis syn_maxfan = 3 */,\n output if_empty_or,\n output if_empty_and,\n output of_ctl_a_full,\n output of_data_a_full,\n output of_ctl_full,\n output of_data_full,\n output pre_data_a_full,\n output [HIGHEST_LANE*80-1:0] phy_din,\n output phy_ctl_a_full,\n output wire [3:0] phy_ctl_full,\n output [HIGHEST_LANE*12-1:0] mem_dq_out,\n output [HIGHEST_LANE*12-1:0] mem_dq_ts,\n input [HIGHEST_LANE*10-1:0] mem_dq_in,\n output [HIGHEST_LANE-1:0] mem_dqs_out,\n output [HIGHEST_LANE-1:0] mem_dqs_ts,\n input [HIGHEST_LANE-1:0] mem_dqs_in,\n\n(* IOB = \"FORCE\" *) output reg [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out, // to memory, odt , 4 per phy controller\n output phy_ctl_ready, // to fabric\n output reg rst_out, // to memory\n output [(NUM_DDR_CK * LP_DDR_CK_WIDTH)-1:0] ddr_clk,\n// output rclk,\n output mcGo,\n output ref_dll_lock,\n// calibration signals\n input phy_write_calib,\n input phy_read_calib,\n input [5:0] calib_sel,\n input [HIGHEST_BANK-1:0]calib_zero_inputs, // bit calib_sel[2], one per bank\n input [HIGHEST_BANK-1:0]calib_zero_ctrl, // one bit per bank, zero's only control lane calibration inputs\n input [HIGHEST_LANE-1:0] calib_zero_lanes, // one bit per lane\n input calib_in_common,\n input [2:0] po_fine_enable,\n input [2:0] po_coarse_enable,\n input [2:0] po_fine_inc,\n input [2:0] po_coarse_inc,\n input po_counter_load_en,\n input [2:0] po_sel_fine_oclk_delay,\n input [8:0] po_counter_load_val,\n input po_counter_read_en,\n output reg po_coarse_overflow,\n output reg po_fine_overflow,\n output reg [8:0] po_counter_read_val,\n\n\n input [HIGHEST_BANK-1:0] pi_rst_dqs_find,\n input pi_fine_enable,\n input pi_fine_inc,\n input pi_counter_load_en,\n input pi_counter_read_en,\n input [5:0] pi_counter_load_val,\n output reg pi_fine_overflow,\n output reg [5:0] pi_counter_read_val,\n\n output reg pi_phase_locked,\n output pi_phase_locked_all,\n output reg pi_dqs_found,\n output pi_dqs_found_all,\n output pi_dqs_found_any,\n output [HIGHEST_LANE-1:0] pi_phase_locked_lanes,\n output [HIGHEST_LANE-1:0] pi_dqs_found_lanes,\n output reg pi_dqs_out_of_range,\n input [29:0] fine_delay,\n input fine_delay_sel\n );\n\n\nwire [7:0] calib_zero_inputs_int ;\nwire [HIGHEST_BANK*4-1:0] calib_zero_lanes_int ;\n\n//Added the temporary variable for concadination operation\nwire [2:0] calib_sel_byte0 ;\nwire [2:0] calib_sel_byte1 ;\nwire [2:0] calib_sel_byte2 ;\n\nwire [4:0] po_coarse_overflow_w;\nwire [4:0] po_fine_overflow_w;\nwire [8:0] po_counter_read_val_w[4:0];\nwire [4:0] pi_fine_overflow_w;\nwire [5:0] pi_counter_read_val_w[4:0];\nwire [4:0] pi_dqs_found_w;\nwire [4:0] pi_dqs_found_all_w;\nwire [4:0] pi_dqs_found_any_w;\nwire [4:0] pi_dqs_out_of_range_w;\nwire [4:0] pi_phase_locked_w;\nwire [4:0] pi_phase_locked_all_w;\nwire [4:0] rclk_w;\nwire [HIGHEST_BANK-1:0] phy_ctl_ready_w;\nwire [(LP_DDR_CK_WIDTH*24)-1:0] ddr_clk_w [HIGHEST_BANK-1:0];\nwire [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out_;\n\n\nwire [3:0] if_q0;\nwire [3:0] if_q1;\nwire [3:0] if_q2;\nwire [3:0] if_q3;\nwire [3:0] if_q4;\nwire [7:0] if_q5;\nwire [7:0] if_q6;\nwire [3:0] if_q7;\nwire [3:0] if_q8;\nwire [3:0] if_q9;\n\nwire [31:0] _phy_ctl_wd;\nwire [3:0] aux_in_[4:1];\nwire [3:0] rst_out_w;\n\nwire freq_refclk_split;\nwire mem_refclk_split;\nwire mem_refclk_div4_split;\nwire sync_pulse_split;\nwire phy_clk_split0;\nwire phy_ctl_clk_split0;\nwire [31:0] phy_ctl_wd_split0;\nwire phy_ctl_wr_split0;\nwire phy_ctl_clk_split1;\nwire phy_clk_split1;\nwire [31:0] phy_ctl_wd_split1;\nwire phy_ctl_wr_split1;\nwire [5:0] phy_data_offset_1_split1;\nwire phy_ctl_clk_split2;\nwire phy_clk_split2;\nwire [31:0] phy_ctl_wd_split2;\nwire phy_ctl_wr_split2;\nwire [5:0] phy_data_offset_2_split2;\nwire [HIGHEST_LANE*80-1:0] phy_dout_split0;\nwire phy_cmd_wr_en_split0;\nwire phy_data_wr_en_split0;\nwire phy_rd_en_split0;\nwire [HIGHEST_LANE*80-1:0] phy_dout_split1;\nwire phy_cmd_wr_en_split1;\nwire phy_data_wr_en_split1;\nwire phy_rd_en_split1;\nwire [HIGHEST_LANE*80-1:0] phy_dout_split2;\nwire phy_cmd_wr_en_split2;\nwire phy_data_wr_en_split2;\nwire phy_rd_en_split2;\n\nwire phy_ctl_mstr_empty;\nwire [HIGHEST_BANK-1:0] phy_ctl_empty;\n\nwire _phy_ctl_a_full_f;\nwire _phy_ctl_a_empty_f;\nwire _phy_ctl_full_f;\nwire _phy_ctl_empty_f;\nwire [HIGHEST_BANK-1:0] _phy_ctl_a_full_p;\nwire [HIGHEST_BANK-1:0] _phy_ctl_full_p;\nwire [HIGHEST_BANK-1:0] of_ctl_a_full_v;\nwire [HIGHEST_BANK-1:0] of_ctl_full_v;\nwire [HIGHEST_BANK-1:0] of_data_a_full_v;\nwire [HIGHEST_BANK-1:0] of_data_full_v;\nwire [HIGHEST_BANK-1:0] pre_data_a_full_v;\nwire [HIGHEST_BANK-1:0] if_empty_v;\nwire [HIGHEST_BANK-1:0] byte_rd_en_v;\nwire [HIGHEST_BANK*2-1:0] byte_rd_en_oth_banks;\nwire [HIGHEST_BANK-1:0] if_empty_or_v;\nwire [HIGHEST_BANK-1:0] if_empty_and_v;\nwire [HIGHEST_BANK-1:0] if_a_empty_v;\n\nlocalparam IF_ARRAY_MODE = \"ARRAY_MODE_4_X_4\";\nlocalparam IF_SYNCHRONOUS_MODE = \"FALSE\";\nlocalparam IF_SLOW_WR_CLK = \"FALSE\";\nlocalparam IF_SLOW_RD_CLK = \"FALSE\";\n\nlocalparam PHY_MULTI_REGION = (HIGHEST_BANK > 1) ? \"TRUE\" : \"FALSE\";\nlocalparam RCLK_NEG_EDGE = 3'b000;\nlocalparam RCLK_POS_EDGE = 3'b111;\n\nlocalparam LP_PHY_0_BYTELANES_DDR_CK = BYTELANES_DDR_CK & 24'hFF_FFFF;\nlocalparam LP_PHY_1_BYTELANES_DDR_CK = (BYTELANES_DDR_CK >> 24) & 24'hFF_FFFF;\nlocalparam LP_PHY_2_BYTELANES_DDR_CK = (BYTELANES_DDR_CK >> 48) & 24'hFF_FFFF;\n\n// hi, lo positions for data offset field, MIG doesn't allow defines\nlocalparam PC_DATA_OFFSET_RANGE_HI = 22;\nlocalparam PC_DATA_OFFSET_RANGE_LO = 17;\n\n/* Phaser_In Output source coding table\n \"PHASE_REF\" : 4'b0000;\n \"DELAYED_MEM_REF\" : 4'b0101;\n \"DELAYED_PHASE_REF\" : 4'b0011;\n \"DELAYED_REF\" : 4'b0001;\n \"FREQ_REF\" : 4'b1000;\n \"MEM_REF\" : 4'b0010;\n*/\n\nlocalparam RCLK_PI_OUTPUT_CLK_SRC = \"DELAYED_MEM_REF\";\n\n\nlocalparam DDR_TCK = TCK;\n\nlocalparam real FREQ_REF_PERIOD = DDR_TCK / (PHY_0_A_PI_FREQ_REF_DIV == \"DIV2\" ? 2 : 1);\nlocalparam real L_FREQ_REF_PERIOD_NS = FREQ_REF_PERIOD /1000.0;\nlocalparam PO_S3_TAPS = 64 ; // Number of taps per clock cycle in OCLK_DELAYED delay line\nlocalparam PI_S2_TAPS = 128 ; // Number of taps per clock cycle in stage 2 delay line\nlocalparam PO_S2_TAPS = 128 ; // Number of taps per clock cycle in sta\n\n/*\nIntrinsic delay of Phaser In Stage 1\n@3300ps - 1.939ns - 58.8%\n@2500ps - 1.657ns - 66.3%\n@1875ps - 1.263ns - 67.4%\n@1500ps - 1.021ns - 68.1%\n@1250ps - 0.868ns - 69.4%\n@1072ps - 0.752ns - 70.1%\n@938ps - 0.667ns - 71.1%\n*/\n\n// If we use the Delayed Mem_Ref_Clk in the RCLK Phaser_In, then the Stage 1 intrinsic delay is 0.0\n// Fraction of a full DDR_TCK period\nlocalparam real PI_STG1_INTRINSIC_DELAY = (RCLK_PI_OUTPUT_CLK_SRC == \"DELAYED_MEM_REF\") ? 0.0 :\n ((DDR_TCK < 1005) ? 0.667 :\n (DDR_TCK < 1160) ? 0.752 :\n (DDR_TCK < 1375) ? 0.868 :\n (DDR_TCK < 1685) ? 1.021 :\n (DDR_TCK < 2185) ? 1.263 :\n (DDR_TCK < 2900) ? 1.657 :\n (DDR_TCK < 3100) ? 1.771 : 1.939)*1000;\n/*\nIntrinsic delay of Phaser In Stage 2\n@3300ps - 0.912ns - 27.6% - single tap - 13ps\n@3000ps - 0.848ns - 28.3% - single tap - 11ps\n@2500ps - 1.264ns - 50.6% - single tap - 19ps\n@1875ps - 1.000ns - 53.3% - single tap - 15ps\n@1500ps - 0.848ns - 56.5% - single tap - 11ps\n@1250ps - 0.736ns - 58.9% - single tap - 9ps\n@1072ps - 0.664ns - 61.9% - single tap - 8ps\n@938ps - 0.608ns - 64.8% - single tap - 7ps\n*/\n// Intrinsic delay = (.4218 + .0002freq(MHz))period(ps)\nlocalparam real PI_STG2_INTRINSIC_DELAY = (0.4218*FREQ_REF_PERIOD + 200) + 16.75; // 12ps fudge factor\n/*\nIntrinsic delay of Phaser Out Stage 2 - coarse bypass = 1\n@3300ps - 1.294ns - 39.2%\n@2500ps - 1.294ns - 51.8%\n@1875ps - 1.030ns - 54.9%\n@1500ps - 0.878ns - 58.5%\n@1250ps - 0.766ns - 61.3%\n@1072ps - 0.694ns - 64.7%\n@938ps - 0.638ns - 68.0%\n\nIntrinsic delay of Phaser Out Stage 2 - coarse bypass = 0\n@3300ps - 2.084ns - 63.2% - single tap - 20ps\n@2500ps - 2.084ns - 81.9% - single tap - 19ps\n@1875ps - 1.676ns - 89.4% - single tap - 15ps\n@1500ps - 1.444ns - 96.3% - single tap - 11ps\n@1250ps - 1.276ns - 102.1% - single tap - 9ps\n@1072ps - 1.164ns - 108.6% - single tap - 8ps\n@938ps - 1.076ns - 114.7% - single tap - 7ps\n*/\n// Fraction of a full DDR_TCK period\nlocalparam real PO_STG1_INTRINSIC_DELAY = 0;\nlocalparam real PO_STG2_FINE_INTRINSIC_DELAY = 0.4218*FREQ_REF_PERIOD + 200 + 42; // 42ps fudge factor\nlocalparam real PO_STG2_COARSE_INTRINSIC_DELAY = 0.2256*FREQ_REF_PERIOD + 200 + 29; // 29ps fudge factor\nlocalparam real PO_STG2_INTRINSIC_DELAY = PO_STG2_FINE_INTRINSIC_DELAY +\n (PO_CTL_COARSE_BYPASS == \"TRUE\" ? 30 : PO_STG2_COARSE_INTRINSIC_DELAY);\n\n// When the PO_STG2_INTRINSIC_DELAY is approximately equal to tCK, then the Phaser Out's circular buffer can\n// go metastable. The circular buffer must be prevented from getting into a metastable state. To accomplish this,\n// a default programmed value must be programmed into the stage 2 delay. This delay is only needed at reset, adjustments\n// to the stage 2 delay can be made after reset is removed.\n\nlocalparam real PO_S2_TAPS_SIZE = 1.0*FREQ_REF_PERIOD / PO_S2_TAPS ; // average delay of taps in stage 2 fine delay line\nlocalparam real PO_CIRC_BUF_META_ZONE = 200.0;\nlocalparam PO_CIRC_BUF_EARLY = (PO_STG2_INTRINSIC_DELAY < DDR_TCK) ? 1'b1 : 1'b0;\nlocalparam real PO_CIRC_BUF_OFFSET = (PO_STG2_INTRINSIC_DELAY < DDR_TCK) ? DDR_TCK - PO_STG2_INTRINSIC_DELAY : PO_STG2_INTRINSIC_DELAY - DDR_TCK;\n// If the stage 2 intrinsic delay is less than the clock period, then see if it is less than the threshold\n// If it is not more than the threshold than we must push the delay after the clock period plus a guardband.\n\n//A change in PO_CIRC_BUF_DELAY value will affect the localparam TAP_DEC value(=PO_CIRC_BUF_DELAY - 31) in ddr_phy_ck_addr_cmd_delay.v. Update TAP_DEC value when PO_CIRC_BUF_DELAY is updated.\nlocalparam integer PO_CIRC_BUF_DELAY = 60;\n\n//localparam integer PO_CIRC_BUF_DELAY = PO_CIRC_BUF_EARLY ? (PO_CIRC_BUF_OFFSET > PO_CIRC_BUF_META_ZONE) ? 0 :\n// (PO_CIRC_BUF_META_ZONE + PO_CIRC_BUF_OFFSET) / PO_S2_TAPS_SIZE :\n// (PO_CIRC_BUF_META_ZONE - PO_CIRC_BUF_OFFSET) / PO_S2_TAPS_SIZE;\n\nlocalparam real PI_S2_TAPS_SIZE = 1.0*FREQ_REF_PERIOD / PI_S2_TAPS ; // average delay of taps in stage 2 fine delay line\nlocalparam real PI_MAX_STG2_DELAY = (PI_S2_TAPS/2 - 1) * PI_S2_TAPS_SIZE;\nlocalparam real PI_INTRINSIC_DELAY = PI_STG1_INTRINSIC_DELAY + PI_STG2_INTRINSIC_DELAY;\nlocalparam real PO_INTRINSIC_DELAY = PO_STG1_INTRINSIC_DELAY + PO_STG2_INTRINSIC_DELAY;\nlocalparam real PO_DELAY = PO_INTRINSIC_DELAY + (PO_CIRC_BUF_DELAY*PO_S2_TAPS_SIZE);\nlocalparam RCLK_BUFIO_DELAY = 1200; // estimate of clock insertion delay of rclk through BUFIO to ioi\n// The PI_OFFSET is the difference between the Phaser Out delay path and the intrinsic delay path\n// of the Phaser_In that drives the rclk. The objective is to align either the rising edges of the\n// oserdes_oclk and the rclk or to align the rising to falling edges depending on which adjustment\n// is within the range of the stage 2 delay line in the Phaser_In.\nlocalparam integer RCLK_DELAY_INT= (PI_INTRINSIC_DELAY + RCLK_BUFIO_DELAY);\nlocalparam integer PO_DELAY_INT = PO_DELAY;\nlocalparam PI_OFFSET = (PO_DELAY_INT % DDR_TCK) - (RCLK_DELAY_INT % DDR_TCK);\n\n// if pi_offset >= 0 align to oclk posedge by delaying pi path to where oclk is\n// if pi_offset < 0 align to oclk negedge by delaying pi path the additional distance to next oclk edge.\n// note that in this case PI_OFFSET is negative so invert before subtracting.\nlocalparam real PI_STG2_DELAY_CAND = PI_OFFSET >= 0\n ? PI_OFFSET\n : ((-PI_OFFSET) < DDR_TCK/2) ?\n (DDR_TCK/2 - (- PI_OFFSET)) :\n (DDR_TCK - (- PI_OFFSET)) ;\n\nlocalparam real PI_STG2_DELAY =\n (PI_STG2_DELAY_CAND > PI_MAX_STG2_DELAY ?\n PI_MAX_STG2_DELAY : PI_STG2_DELAY_CAND);\nlocalparam integer DEFAULT_RCLK_DELAY = PI_STG2_DELAY / PI_S2_TAPS_SIZE;\n\nlocalparam LP_RCLK_SELECT_EDGE = (RCLK_SELECT_EDGE != 4'b1111 ) ? RCLK_SELECT_EDGE : (PI_OFFSET >= 0 ? RCLK_POS_EDGE : (PI_OFFSET <= TCK/2 ? RCLK_NEG_EDGE : RCLK_POS_EDGE));\n\nlocalparam integer L_PHY_0_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ;\nlocalparam integer L_PHY_1_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ;\nlocalparam integer L_PHY_2_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ;\n\nlocalparam L_PHY_0_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[0]) ? DEFAULT_RCLK_DELAY : 33 ;\nlocalparam L_PHY_0_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[1]) ? DEFAULT_RCLK_DELAY : 33 ;\nlocalparam L_PHY_0_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[2]) ? DEFAULT_RCLK_DELAY : 33 ;\nlocalparam L_PHY_0_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[3]) ? DEFAULT_RCLK_DELAY : 33 ;\n\nlocalparam L_PHY_1_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[0]) ? DEFAULT_RCLK_DELAY : 33 ;\nlocalparam L_PHY_1_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[1]) ? DEFAULT_RCLK_DELAY : 33 ;\nlocalparam L_PHY_1_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[2]) ? DEFAULT_RCLK_DELAY : 33 ;\nlocalparam L_PHY_1_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[3]) ? DEFAULT_RCLK_DELAY : 33 ;\n\nlocalparam L_PHY_2_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[0]) ? DEFAULT_RCLK_DELAY : 33 ;\nlocalparam L_PHY_2_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[1]) ? DEFAULT_RCLK_DELAY : 33 ;\nlocalparam L_PHY_2_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[2]) ? DEFAULT_RCLK_DELAY : 33 ;\nlocalparam L_PHY_2_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[3]) ? DEFAULT_RCLK_DELAY : 33 ;\n\n\nlocalparam L_PHY_0_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == \"A\") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;\nlocalparam L_PHY_0_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == \"B\") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;\nlocalparam L_PHY_0_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == \"C\") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;\nlocalparam L_PHY_0_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == \"D\") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;\n\nlocalparam L_PHY_1_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == \"A\") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;\nlocalparam L_PHY_1_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == \"B\") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;\nlocalparam L_PHY_1_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == \"C\") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;\nlocalparam L_PHY_1_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == \"D\") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;\n\nlocalparam L_PHY_2_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == \"A\") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;\nlocalparam L_PHY_2_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == \"B\") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;\nlocalparam L_PHY_2_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == \"C\") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;\nlocalparam L_PHY_2_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == \"D\") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;\n\nwire _phy_clk;\n\nwire [2:0] mcGo_w;\nwire [HIGHEST_BANK-1:0] ref_dll_lock_w;\nreg [15:0] mcGo_r;\n\n\nassign ref_dll_lock = & ref_dll_lock_w;\n\ninitial begin\n if ( SYNTHESIS == \"FALSE\" ) begin\n $display(\"%m : BYTE_LANES_B0 = %x BYTE_LANES_B1 = %x DATA_CTL_B0 = %x DATA_CTL_B1 = %x\", BYTE_LANES_B0, BYTE_LANES_B1, DATA_CTL_B0, DATA_CTL_B1);\n $display(\"%m : HIGHEST_LANE = %d HIGHEST_LANE_B0 = %d HIGHEST_LANE_B1 = %d\", HIGHEST_LANE, HIGHEST_LANE_B0, HIGHEST_LANE_B1);\n $display(\"%m : HIGHEST_BANK = %d\", HIGHEST_BANK);\n\n $display(\"%m : FREQ_REF_PERIOD = %0.2f \", FREQ_REF_PERIOD);\n $display(\"%m : DDR_TCK = %0d \", DDR_TCK);\n $display(\"%m : PO_S2_TAPS_SIZE = %0.2f \", PO_S2_TAPS_SIZE);\n $display(\"%m : PO_CIRC_BUF_EARLY = %0d \", PO_CIRC_BUF_EARLY);\n $display(\"%m : PO_CIRC_BUF_OFFSET = %0.2f \", PO_CIRC_BUF_OFFSET);\n $display(\"%m : PO_CIRC_BUF_META_ZONE = %0.2f \", PO_CIRC_BUF_META_ZONE);\n $display(\"%m : PO_STG2_FINE_INTR_DLY = %0.2f \", PO_STG2_FINE_INTRINSIC_DELAY);\n $display(\"%m : PO_STG2_COARSE_INTR_DLY = %0.2f \", PO_STG2_COARSE_INTRINSIC_DELAY);\n $display(\"%m : PO_STG2_INTRINSIC_DELAY = %0.2f \", PO_STG2_INTRINSIC_DELAY);\n $display(\"%m : PO_CIRC_BUF_DELAY = %0d \", PO_CIRC_BUF_DELAY);\n $display(\"%m : PO_INTRINSIC_DELAY = %0.2f \", PO_INTRINSIC_DELAY);\n $display(\"%m : PO_DELAY = %0.2f \", PO_DELAY);\n $display(\"%m : PO_OCLK_DELAY = %0d \", PHY_0_A_PO_OCLK_DELAY);\n $display(\"%m : L_PHY_0_PO_FINE_DELAY = %0d \", L_PHY_0_PO_FINE_DELAY);\n\n $display(\"%m : PI_STG1_INTRINSIC_DELAY = %0.2f \", PI_STG1_INTRINSIC_DELAY);\n $display(\"%m : PI_STG2_INTRINSIC_DELAY = %0.2f \", PI_STG2_INTRINSIC_DELAY);\n $display(\"%m : PI_INTRINSIC_DELAY = %0.2f \", PI_INTRINSIC_DELAY);\n $display(\"%m : PI_MAX_STG2_DELAY = %0.2f \", PI_MAX_STG2_DELAY);\n $display(\"%m : PI_OFFSET = %0.2f \", PI_OFFSET);\n if ( PI_OFFSET < 0) $display(\"%m : a negative PI_OFFSET means that rclk path is longer than oclk path so rclk will be delayed to next oclk edge and the negedge of rclk may be used.\");\n $display(\"%m : PI_STG2_DELAY = %0.2f \", PI_STG2_DELAY);\n $display(\"%m :PI_STG2_DELAY_CAND = %0.2f \",PI_STG2_DELAY_CAND);\n $display(\"%m : DEFAULT_RCLK_DELAY = %0d \", DEFAULT_RCLK_DELAY);\n $display(\"%m : RCLK_SELECT_EDGE = %0b \", LP_RCLK_SELECT_EDGE);\n end // SYNTHESIS\n if ( PI_STG2_DELAY_CAND > PI_MAX_STG2_DELAY) $display(\"WARNING: %m: The required delay though the phaser_in to internally match the aux_out clock to ddr clock exceeds the maximum allowable delay. The clock edge will occur at the output registers of aux_out %0.2f ps before the ddr clock edge. If aux_out is used for memory inputs, this may violate setup or hold time.\", PI_STG2_DELAY_CAND - PI_MAX_STG2_DELAY);\nend\n\n assign sync_pulse_split = sync_pulse;\n assign mem_refclk_split = mem_refclk;\n assign freq_refclk_split = freq_refclk;\n assign mem_refclk_div4_split = mem_refclk_div4;\n assign phy_ctl_clk_split0 = _phy_clk;\n assign phy_ctl_wd_split0 = phy_ctl_wd;\n assign phy_ctl_wr_split0 = phy_ctl_wr;\n assign phy_clk_split0 = phy_clk;\n assign phy_cmd_wr_en_split0 = phy_cmd_wr_en;\n assign phy_data_wr_en_split0 = phy_data_wr_en;\n assign phy_rd_en_split0 = phy_rd_en;\n assign phy_dout_split0 = phy_dout;\n assign phy_ctl_clk_split1 = phy_clk;\n assign phy_ctl_wd_split1 = phy_ctl_wd;\n assign phy_data_offset_1_split1 = data_offset_1;\n assign phy_ctl_wr_split1 = phy_ctl_wr;\n assign phy_clk_split1 = phy_clk;\n assign phy_cmd_wr_en_split1 = phy_cmd_wr_en;\n assign phy_data_wr_en_split1 = phy_data_wr_en;\n assign phy_rd_en_split1 = phy_rd_en;\n assign phy_dout_split1 = phy_dout;\n assign phy_ctl_clk_split2 = phy_clk;\n assign phy_ctl_wd_split2 = phy_ctl_wd;\n assign phy_data_offset_2_split2 = data_offset_2;\n assign phy_ctl_wr_split2 = phy_ctl_wr;\n assign phy_clk_split2 = phy_clk;\n assign phy_cmd_wr_en_split2 = phy_cmd_wr_en;\n assign phy_data_wr_en_split2 = phy_data_wr_en;\n assign phy_rd_en_split2 = phy_rd_en;\n assign phy_dout_split2 = phy_dout;\n\n// these wires are needed to coerce correct synthesis\n// the synthesizer did not always see the widths of the\n// parameters as 4 bits.\n\nwire [3:0] blb0 = BYTE_LANES_B0;\nwire [3:0] blb1 = BYTE_LANES_B1;\nwire [3:0] blb2 = BYTE_LANES_B2;\n\nwire [3:0] dcb0 = DATA_CTL_B0;\nwire [3:0] dcb1 = DATA_CTL_B1;\nwire [3:0] dcb2 = DATA_CTL_B2;\n\nassign pi_dqs_found_all = & (pi_dqs_found_lanes | ~ {blb2, blb1, blb0} | ~ {dcb2, dcb1, dcb0});\nassign pi_dqs_found_any = | (pi_dqs_found_lanes & {blb2, blb1, blb0} & {dcb2, dcb1, dcb0});\nassign pi_phase_locked_all = & pi_phase_locked_all_w[HIGHEST_BANK-1:0];\nassign calib_zero_inputs_int = {3'bxxx, calib_zero_inputs};\n//Added to remove concadination in the instantiation\nassign calib_sel_byte0 = {calib_zero_inputs_int[0], calib_sel[1:0]} ;\nassign calib_sel_byte1 = {calib_zero_inputs_int[1], calib_sel[1:0]} ;\nassign calib_sel_byte2 = {calib_zero_inputs_int[2], calib_sel[1:0]} ;\n\nassign calib_zero_lanes_int = calib_zero_lanes;\n\nassign phy_ctl_ready = &phy_ctl_ready_w[HIGHEST_BANK-1:0];\n\nassign phy_ctl_mstr_empty = phy_ctl_empty[MASTER_PHY_CTL];\n\nassign of_ctl_a_full = |of_ctl_a_full_v;\nassign of_ctl_full = |of_ctl_full_v;\nassign of_data_a_full = |of_data_a_full_v;\nassign of_data_full = |of_data_full_v;\nassign pre_data_a_full= |pre_data_a_full_v;\n// if if_empty_def == 1, empty is asserted only if all are empty;\n// this allows the user to detect a skewed fifo depth and self-clear\n// if desired. It avoids a reset to clear the flags.\nassign if_empty = !if_empty_def ? |if_empty_v : &if_empty_v;\nassign if_empty_or = |if_empty_or_v;\nassign if_empty_and = &if_empty_and_v;\nassign if_a_empty = |if_a_empty_v;\n\n\ngenerate\ngenvar i;\nfor (i = 0; i != NUM_DDR_CK; i = i + 1) begin : ddr_clk_gen\n case ((GENERATE_DDR_CK_MAP >> (16*i)) & 16'hffff)\n 16'h3041: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i)) & 2'b11;\n 16'h3042: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11;\n 16'h3043: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11;\n 16'h3044: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11;\n 16'h3141: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i)) & 2'b11;\n 16'h3142: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11;\n 16'h3143: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11;\n 16'h3144: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11;\n 16'h3241: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i)) & 2'b11;\n 16'h3242: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11;\n 16'h3243: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11;\n 16'h3244: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11;\n default : initial $display(\"ERROR: mc_phy ddr_clk_gen : invalid specification for parameter GENERATE_DDR_CK_MAP , clock index = %d, spec= %x (hex) \", i, (( GENERATE_DDR_CK_MAP >> (16 * i )) & 16'hffff ));\n endcase\nend\nendgenerate\n\n//assign rclk = rclk_w[RCLK_SELECT_BANK];\n\nreg rst_auxout;\nreg rst_auxout_r;\nreg rst_auxout_rr;\n\nalways @(posedge auxout_clk or posedge rst) begin\n if ( rst) begin\n rst_auxout_r <= #(1) 1'b1;\n rst_auxout_rr <= #(1) 1'b1;\n end\n else begin\n rst_auxout_r <= #(1) rst;\n rst_auxout_rr <= #(1) rst_auxout_r;\n end\nend\nif ( LP_RCLK_SELECT_EDGE[0]) begin\n always @(posedge auxout_clk or posedge rst) begin\n if ( rst) begin\n rst_auxout <= #(1) 1'b1;\n end\n else begin\n rst_auxout <= #(1) rst_auxout_rr;\n end\n end\nend\nelse begin\n always @(negedge auxout_clk or posedge rst) begin\n if ( rst) begin\n rst_auxout <= #(1) 1'b1;\n end\n else begin\n rst_auxout <= #(1) rst_auxout_rr;\n end\n end\nend\n\nlocalparam L_RESET_SELECT_BANK =\n (BYTE_LANES_B1 == 0 && BYTE_LANES_B2 == 0 && RCLK_SELECT_BANK) ? 0 : RCLK_SELECT_BANK;\n\nalways @(*) begin\n rst_out = rst_out_w[L_RESET_SELECT_BANK] & ddr_rst_in_n;\nend\n\nalways @(posedge phy_clk) begin\n if ( rst)\n mcGo_r <= #(1) 0;\n else\n mcGo_r <= #(1) (mcGo_r << 1) | &mcGo_w;\nend\n\nassign mcGo = mcGo_r[15];\n\n\ngenerate\n\n\n// this is an optional 1 clock delay to add latency to the phy_control programming path\n\nif (PHYCTL_CMD_FIFO == \"TRUE\") begin : cmd_fifo_soft\n reg [31:0] phy_wd_reg = 0;\n reg [3:0] aux_in1_reg = 0;\n reg [3:0] aux_in2_reg = 0;\n reg sfifo_ready = 0;\n assign _phy_ctl_wd = phy_wd_reg;\n assign aux_in_[1] = aux_in1_reg;\n assign aux_in_[2] = aux_in2_reg;\n assign phy_ctl_a_full = |_phy_ctl_a_full_p;\n assign phy_ctl_full[0] = |_phy_ctl_full_p;\n assign phy_ctl_full[1] = |_phy_ctl_full_p;\n assign phy_ctl_full[2] = |_phy_ctl_full_p;\n assign phy_ctl_full[3] = |_phy_ctl_full_p;\n assign _phy_clk = phy_clk;\n\n always @(posedge phy_clk) begin\n phy_wd_reg <= #1 phy_ctl_wd;\n aux_in1_reg <= #1 aux_in_1;\n aux_in2_reg <= #1 aux_in_2;\n sfifo_ready <= #1 phy_ctl_wr;\n end\n\nend\n\nelse if (PHYCTL_CMD_FIFO == \"FALSE\") begin\n assign _phy_ctl_wd = phy_ctl_wd;\n assign aux_in_[1] = aux_in_1;\n assign aux_in_[2] = aux_in_2;\n assign phy_ctl_a_full = |_phy_ctl_a_full_p;\n assign phy_ctl_full[0] = |_phy_ctl_full_p;\n assign phy_ctl_full[3:1] = 3'b000;\n assign _phy_clk = phy_clk;\n\nend\nendgenerate\n\n\n// instance of four-lane phy\n\ngenerate\n\nif (HIGHEST_BANK == 3) begin : banks_3\n assign byte_rd_en_oth_banks[1:0] = {byte_rd_en_v[1],byte_rd_en_v[2]};\n assign byte_rd_en_oth_banks[3:2] = {byte_rd_en_v[0],byte_rd_en_v[2]};\n assign byte_rd_en_oth_banks[5:4] = {byte_rd_en_v[0],byte_rd_en_v[1]};\nend\nelse if (HIGHEST_BANK == 2) begin : banks_2\n assign byte_rd_en_oth_banks[1:0] = {byte_rd_en_v[1],1'b1};\n assign byte_rd_en_oth_banks[3:2] = {byte_rd_en_v[0],1'b1};\nend\nelse begin : banks_1\n assign byte_rd_en_oth_banks[1:0] = {1'b1,1'b1};\nend\n\nif ( BYTE_LANES_B0 != 0) begin : ddr_phy_4lanes_0\nmig_7series_v4_0_ddr_phy_4lanes #\n (\n .BYTE_LANES (BYTE_LANES_B0), /* four bits, one per lanes */\n .DATA_CTL_N (PHY_0_DATA_CTL), /* four bits, one per lane */\n .PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),\n .PO_FINE_DELAY (L_PHY_0_PO_FINE_DELAY),\n .BITLANES (PHY_0_BITLANES),\n .BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY),\n .BYTELANES_DDR_CK (LP_PHY_0_BYTELANES_DDR_CK),\n .LAST_BANK (PHY_0_IS_LAST_BANK),\n .LANE_REMAP (PHY_0_LANE_REMAP),\n .OF_ALMOST_FULL_VALUE (PHY_0_OF_ALMOST_FULL_VALUE),\n .IF_ALMOST_EMPTY_VALUE (PHY_0_IF_ALMOST_EMPTY_VALUE),\n .GENERATE_IDELAYCTRL (PHY_0_GENERATE_IDELAYCTRL),\n .IODELAY_GRP (PHY_0_IODELAY_GRP),\n .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),\n .BANK_TYPE (BANK_TYPE),\n .NUM_DDR_CK (NUM_DDR_CK),\n .TCK (TCK),\n .RCLK_SELECT_LANE (RCLK_SELECT_LANE),\n .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),\n .SYNTHESIS (SYNTHESIS),\n .PC_CLK_RATIO (PHY_CLK_RATIO),\n .PC_EVENTS_DELAY (PHY_EVENTS_DELAY),\n .PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),\n .PC_BURST_MODE (PHY_0_A_BURST_MODE),\n .PC_SYNC_MODE (PHY_SYNC_MODE),\n .PC_MULTI_REGION (PHY_MULTI_REGION),\n .PC_PHY_COUNT_EN (PHY_COUNT_EN),\n .PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),\n .PC_CMD_OFFSET (PHY_0_CMD_OFFSET),\n .PC_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0),\n .PC_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1),\n .PC_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2),\n .PC_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3),\n .PC_RD_DURATION_0 (PHY_0_RD_DURATION_0),\n .PC_RD_DURATION_1 (PHY_0_RD_DURATION_1),\n .PC_RD_DURATION_2 (PHY_0_RD_DURATION_2),\n .PC_RD_DURATION_3 (PHY_0_RD_DURATION_3),\n .PC_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0),\n .PC_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1),\n .PC_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2),\n .PC_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3),\n .PC_WR_DURATION_0 (PHY_0_WR_DURATION_0),\n .PC_WR_DURATION_1 (PHY_0_WR_DURATION_1),\n .PC_WR_DURATION_2 (PHY_0_WR_DURATION_2),\n .PC_WR_DURATION_3 (PHY_0_WR_DURATION_3),\n .PC_AO_WRLVL_EN (PHY_0_AO_WRLVL_EN),\n .PC_AO_TOGGLE (PHY_0_AO_TOGGLE),\n\n .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),\n\n .A_PI_FINE_DELAY (L_PHY_0_A_PI_FINE_DELAY),\n .B_PI_FINE_DELAY (L_PHY_0_B_PI_FINE_DELAY),\n .C_PI_FINE_DELAY (L_PHY_0_C_PI_FINE_DELAY),\n .D_PI_FINE_DELAY (L_PHY_0_D_PI_FINE_DELAY),\n\n .A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV),\n .A_PI_BURST_MODE (PHY_0_A_BURST_MODE),\n .A_PI_OUTPUT_CLK_SRC (L_PHY_0_A_PI_OUTPUT_CLK_SRC),\n .B_PI_OUTPUT_CLK_SRC (L_PHY_0_B_PI_OUTPUT_CLK_SRC),\n .C_PI_OUTPUT_CLK_SRC (L_PHY_0_C_PI_OUTPUT_CLK_SRC),\n .D_PI_OUTPUT_CLK_SRC (L_PHY_0_D_PI_OUTPUT_CLK_SRC),\n .A_PO_OUTPUT_CLK_SRC (PHY_0_A_PO_OUTPUT_CLK_SRC),\n .A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),\n .A_PO_OCLKDELAY_INV (PHY_0_A_PO_OCLKDELAY_INV),\n .A_OF_ARRAY_MODE (PHY_0_A_OF_ARRAY_MODE),\n .B_OF_ARRAY_MODE (PHY_0_B_OF_ARRAY_MODE),\n .C_OF_ARRAY_MODE (PHY_0_C_OF_ARRAY_MODE),\n .D_OF_ARRAY_MODE (PHY_0_D_OF_ARRAY_MODE),\n .A_IF_ARRAY_MODE (PHY_0_A_IF_ARRAY_MODE),\n .B_IF_ARRAY_MODE (PHY_0_B_IF_ARRAY_MODE),\n .C_IF_ARRAY_MODE (PHY_0_C_IF_ARRAY_MODE),\n .D_IF_ARRAY_MODE (PHY_0_D_IF_ARRAY_MODE),\n .A_OS_DATA_RATE (PHY_0_A_OSERDES_DATA_RATE),\n .A_OS_DATA_WIDTH (PHY_0_A_OSERDES_DATA_WIDTH),\n .B_OS_DATA_RATE (PHY_0_B_OSERDES_DATA_RATE),\n .B_OS_DATA_WIDTH (PHY_0_B_OSERDES_DATA_WIDTH),\n .C_OS_DATA_RATE (PHY_0_C_OSERDES_DATA_RATE),\n .C_OS_DATA_WIDTH (PHY_0_C_OSERDES_DATA_WIDTH),\n .D_OS_DATA_RATE (PHY_0_D_OSERDES_DATA_RATE),\n .D_OS_DATA_WIDTH (PHY_0_D_OSERDES_DATA_WIDTH),\n .A_IDELAYE2_IDELAY_TYPE (PHY_0_A_IDELAYE2_IDELAY_TYPE),\n .A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE)\n ,.CKE_ODT_AUX (CKE_ODT_AUX)\n ,.PI_DIV2_INCDEC (PI_DIV2_INCDEC)\n)\n u_ddr_phy_4lanes\n(\n .rst (rst),\n .phy_clk (phy_clk_split0),\n .clk_div2 (clk_div2),\n .phy_ctl_clk (phy_ctl_clk_split0),\n .phy_ctl_wd (phy_ctl_wd_split0),\n .data_offset (phy_ctl_wd_split0[PC_DATA_OFFSET_RANGE_HI : PC_DATA_OFFSET_RANGE_LO]),\n .phy_ctl_wr (phy_ctl_wr_split0),\n .mem_refclk (mem_refclk_split),\n .freq_refclk (freq_refclk_split),\n .mem_refclk_div4 (mem_refclk_div4_split),\n .sync_pulse (sync_pulse_split),\n .phy_dout (phy_dout_split0[HIGHEST_LANE_B0*80-1:0]),\n .phy_cmd_wr_en (phy_cmd_wr_en_split0),\n .phy_data_wr_en (phy_data_wr_en_split0),\n .phy_rd_en (phy_rd_en_split0),\n .pll_lock (pll_lock),\n .ddr_clk (ddr_clk_w[0]),\n .rclk (),\n .rst_out (rst_out_w[0]),\n .mcGo (mcGo_w[0]),\n .ref_dll_lock (ref_dll_lock_w[0]),\n .idelayctrl_refclk (idelayctrl_refclk),\n .idelay_inc (idelay_inc),\n .idelay_ce (idelay_ce),\n .idelay_ld (idelay_ld),\n .phy_ctl_mstr_empty (phy_ctl_mstr_empty),\n .if_rst (if_rst),\n .if_empty_def (if_empty_def),\n .byte_rd_en_oth_banks (byte_rd_en_oth_banks[1:0]),\n .if_a_empty (if_a_empty_v[0]),\n .if_empty (if_empty_v[0]),\n .byte_rd_en (byte_rd_en_v[0]),\n .if_empty_or (if_empty_or_v[0]),\n .if_empty_and (if_empty_and_v[0]),\n .of_ctl_a_full (of_ctl_a_full_v[0]),\n .of_data_a_full (of_data_a_full_v[0]),\n .of_ctl_full (of_ctl_full_v[0]),\n .of_data_full (of_data_full_v[0]),\n .pre_data_a_full (pre_data_a_full_v[0]),\n .phy_din (phy_din[HIGHEST_LANE_B0*80-1:0]),\n .phy_ctl_a_full (_phy_ctl_a_full_p[0]),\n .phy_ctl_full (_phy_ctl_full_p[0]),\n .phy_ctl_empty (phy_ctl_empty[0]),\n .mem_dq_out (mem_dq_out[HIGHEST_LANE_B0*12-1:0]),\n .mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B0*12-1:0]),\n .mem_dq_in (mem_dq_in[HIGHEST_LANE_B0*10-1:0]),\n .mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B0-1:0]),\n .mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B0-1:0]),\n .mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B0-1:0]),\n .aux_out (aux_out_[3:0]),\n .phy_ctl_ready (phy_ctl_ready_w[0]),\n .phy_write_calib (phy_write_calib),\n .phy_read_calib (phy_read_calib),\n// .scan_test_bus_A (scan_test_bus_A),\n// .scan_test_bus_B (),\n// .scan_test_bus_C (),\n// .scan_test_bus_D (),\n .phyGo (phyGo),\n .input_sink (input_sink),\n\n .calib_sel (calib_sel_byte0),\n .calib_zero_ctrl (calib_zero_ctrl[0]),\n .calib_zero_lanes (calib_zero_lanes_int[3:0]),\n .calib_in_common (calib_in_common),\n .po_coarse_enable (po_coarse_enable[0]),\n .po_fine_enable (po_fine_enable[0]),\n .po_fine_inc (po_fine_inc[0]),\n .po_coarse_inc (po_coarse_inc[0]),\n .po_counter_load_en (po_counter_load_en),\n .po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[0]),\n .po_counter_load_val (po_counter_load_val),\n .po_counter_read_en (po_counter_read_en),\n .po_coarse_overflow (po_coarse_overflow_w[0]),\n .po_fine_overflow (po_fine_overflow_w[0]),\n .po_counter_read_val (po_counter_read_val_w[0]),\n\n .pi_rst_dqs_find (pi_rst_dqs_find[0]),\n .pi_fine_enable (pi_fine_enable),\n .pi_fine_inc (pi_fine_inc),\n .pi_counter_load_en (pi_counter_load_en),\n .pi_counter_read_en (pi_counter_read_en),\n .pi_counter_load_val (pi_counter_load_val),\n .pi_fine_overflow (pi_fine_overflow_w[0]),\n .pi_counter_read_val (pi_counter_read_val_w[0]),\n .pi_dqs_found (pi_dqs_found_w[0]),\n .pi_dqs_found_all (pi_dqs_found_all_w[0]),\n .pi_dqs_found_any (pi_dqs_found_any_w[0]),\n .pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B0-1:0]),\n .pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B0-1:0]),\n .pi_dqs_out_of_range (pi_dqs_out_of_range_w[0]),\n .pi_phase_locked (pi_phase_locked_w[0]),\n .pi_phase_locked_all (pi_phase_locked_all_w[0]),\n .fine_delay (fine_delay),\n .fine_delay_sel (fine_delay_sel)\n);\n\n always @(posedge auxout_clk or posedge rst_auxout) begin\n if (rst_auxout) begin\n aux_out[0] <= #100 0;\n aux_out[2] <= #100 0;\n end\n else begin\n aux_out[0] <= #100 aux_out_[0];\n aux_out[2] <= #100 aux_out_[2];\n end\n end\n if ( LP_RCLK_SELECT_EDGE[0]) begin\n always @(posedge auxout_clk or posedge rst_auxout) begin\n if (rst_auxout) begin\n aux_out[1] <= #100 0;\n aux_out[3] <= #100 0;\n end\n else begin\n aux_out[1] <= #100 aux_out_[1];\n aux_out[3] <= #100 aux_out_[3];\n end\n end\n end\n else begin\n always @(negedge auxout_clk or posedge rst_auxout) begin\n if (rst_auxout) begin\n aux_out[1] <= #100 0;\n aux_out[3] <= #100 0;\n end\n else begin\n aux_out[1] <= #100 aux_out_[1];\n aux_out[3] <= #100 aux_out_[3];\n end\n end\n end\nend\nelse begin\n if ( HIGHEST_BANK > 0) begin\n assign phy_din[HIGHEST_LANE_B0*80-1:0] = 0;\n assign _phy_ctl_a_full_p[0] = 0;\n assign of_ctl_a_full_v[0] = 0;\n assign of_ctl_full_v[0] = 0;\n assign of_data_a_full_v[0] = 0;\n assign of_data_full_v[0] = 0;\n assign pre_data_a_full_v[0] = 0;\n assign if_empty_v[0] = 0;\n assign byte_rd_en_v[0] = 1;\n always @(*)\n aux_out[3:0] = 0;\n end\n assign pi_dqs_found_w[0] = 1;\n assign pi_dqs_found_all_w[0] = 1;\n assign pi_dqs_found_any_w[0] = 0;\n assign pi_phase_locked_lanes[HIGHEST_LANE_B0-1:0] = 4'b1111;\n assign pi_dqs_found_lanes[HIGHEST_LANE_B0-1:0] = 4'b1111;\n assign pi_dqs_out_of_range_w[0] = 0;\n assign pi_phase_locked_w[0] = 1;\n assign po_fine_overflow_w[0] = 0;\n assign po_coarse_overflow_w[0] = 0;\n assign po_fine_overflow_w[0] = 0;\n assign pi_fine_overflow_w[0] = 0;\n assign po_counter_read_val_w[0] = 0;\n assign pi_counter_read_val_w[0] = 0;\n assign mcGo_w[0] = 1;\n if ( RCLK_SELECT_BANK == 0)\n always @(*)\n aux_out[3:0] = 0;\nend\n\nif ( BYTE_LANES_B1 != 0) begin : ddr_phy_4lanes_1\n\nmig_7series_v4_0_ddr_phy_4lanes #\n (\n .BYTE_LANES (BYTE_LANES_B1), /* four bits, one per lanes */\n .DATA_CTL_N (PHY_1_DATA_CTL), /* four bits, one per lane */\n .PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),\n .PO_FINE_DELAY (L_PHY_1_PO_FINE_DELAY),\n .BITLANES (PHY_1_BITLANES),\n .BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY),\n .BYTELANES_DDR_CK (LP_PHY_1_BYTELANES_DDR_CK),\n .LAST_BANK (PHY_1_IS_LAST_BANK ),\n .LANE_REMAP (PHY_1_LANE_REMAP),\n .OF_ALMOST_FULL_VALUE (PHY_1_OF_ALMOST_FULL_VALUE),\n .IF_ALMOST_EMPTY_VALUE (PHY_1_IF_ALMOST_EMPTY_VALUE),\n .GENERATE_IDELAYCTRL (PHY_1_GENERATE_IDELAYCTRL),\n .IODELAY_GRP (PHY_1_IODELAY_GRP),\n .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),\n .BANK_TYPE (BANK_TYPE),\n .NUM_DDR_CK (NUM_DDR_CK),\n .TCK (TCK),\n .RCLK_SELECT_LANE (RCLK_SELECT_LANE),\n .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),\n .SYNTHESIS (SYNTHESIS),\n .PC_CLK_RATIO (PHY_CLK_RATIO),\n .PC_EVENTS_DELAY (PHY_EVENTS_DELAY),\n .PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),\n .PC_BURST_MODE (PHY_1_A_BURST_MODE),\n .PC_SYNC_MODE (PHY_SYNC_MODE),\n .PC_MULTI_REGION (PHY_MULTI_REGION),\n .PC_PHY_COUNT_EN (PHY_COUNT_EN),\n .PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),\n .PC_CMD_OFFSET (PHY_1_CMD_OFFSET),\n .PC_RD_CMD_OFFSET_0 (PHY_1_RD_CMD_OFFSET_0),\n .PC_RD_CMD_OFFSET_1 (PHY_1_RD_CMD_OFFSET_1),\n .PC_RD_CMD_OFFSET_2 (PHY_1_RD_CMD_OFFSET_2),\n .PC_RD_CMD_OFFSET_3 (PHY_1_RD_CMD_OFFSET_3),\n .PC_RD_DURATION_0 (PHY_1_RD_DURATION_0),\n .PC_RD_DURATION_1 (PHY_1_RD_DURATION_1),\n .PC_RD_DURATION_2 (PHY_1_RD_DURATION_2),\n .PC_RD_DURATION_3 (PHY_1_RD_DURATION_3),\n .PC_WR_CMD_OFFSET_0 (PHY_1_WR_CMD_OFFSET_0),\n .PC_WR_CMD_OFFSET_1 (PHY_1_WR_CMD_OFFSET_1),\n .PC_WR_CMD_OFFSET_2 (PHY_1_WR_CMD_OFFSET_2),\n .PC_WR_CMD_OFFSET_3 (PHY_1_WR_CMD_OFFSET_3),\n .PC_WR_DURATION_0 (PHY_1_WR_DURATION_0),\n .PC_WR_DURATION_1 (PHY_1_WR_DURATION_1),\n .PC_WR_DURATION_2 (PHY_1_WR_DURATION_2),\n .PC_WR_DURATION_3 (PHY_1_WR_DURATION_3),\n .PC_AO_WRLVL_EN (PHY_1_AO_WRLVL_EN),\n .PC_AO_TOGGLE (PHY_1_AO_TOGGLE),\n\n .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),\n\n .A_PI_FINE_DELAY (L_PHY_1_A_PI_FINE_DELAY),\n .B_PI_FINE_DELAY (L_PHY_1_B_PI_FINE_DELAY),\n .C_PI_FINE_DELAY (L_PHY_1_C_PI_FINE_DELAY),\n .D_PI_FINE_DELAY (L_PHY_1_D_PI_FINE_DELAY),\n\n .A_PI_FREQ_REF_DIV (PHY_1_A_PI_FREQ_REF_DIV),\n .A_PI_BURST_MODE (PHY_1_A_BURST_MODE),\n .A_PI_OUTPUT_CLK_SRC (L_PHY_1_A_PI_OUTPUT_CLK_SRC),\n .B_PI_OUTPUT_CLK_SRC (L_PHY_1_B_PI_OUTPUT_CLK_SRC),\n .C_PI_OUTPUT_CLK_SRC (L_PHY_1_C_PI_OUTPUT_CLK_SRC),\n .D_PI_OUTPUT_CLK_SRC (L_PHY_1_D_PI_OUTPUT_CLK_SRC),\n .A_PO_OUTPUT_CLK_SRC (PHY_1_A_PO_OUTPUT_CLK_SRC),\n .A_PO_OCLK_DELAY (PHY_1_A_PO_OCLK_DELAY),\n .A_PO_OCLKDELAY_INV (PHY_1_A_PO_OCLKDELAY_INV),\n .A_OF_ARRAY_MODE (PHY_1_A_OF_ARRAY_MODE),\n .B_OF_ARRAY_MODE (PHY_1_B_OF_ARRAY_MODE),\n .C_OF_ARRAY_MODE (PHY_1_C_OF_ARRAY_MODE),\n .D_OF_ARRAY_MODE (PHY_1_D_OF_ARRAY_MODE),\n .A_IF_ARRAY_MODE (PHY_1_A_IF_ARRAY_MODE),\n .B_IF_ARRAY_MODE (PHY_1_B_IF_ARRAY_MODE),\n .C_IF_ARRAY_MODE (PHY_1_C_IF_ARRAY_MODE),\n .D_IF_ARRAY_MODE (PHY_1_D_IF_ARRAY_MODE),\n .A_OS_DATA_RATE (PHY_1_A_OSERDES_DATA_RATE),\n .A_OS_DATA_WIDTH (PHY_1_A_OSERDES_DATA_WIDTH),\n .B_OS_DATA_RATE (PHY_1_B_OSERDES_DATA_RATE),\n .B_OS_DATA_WIDTH (PHY_1_B_OSERDES_DATA_WIDTH),\n .C_OS_DATA_RATE (PHY_1_C_OSERDES_DATA_RATE),\n .C_OS_DATA_WIDTH (PHY_1_C_OSERDES_DATA_WIDTH),\n .D_OS_DATA_RATE (PHY_1_D_OSERDES_DATA_RATE),\n .D_OS_DATA_WIDTH (PHY_1_D_OSERDES_DATA_WIDTH),\n .A_IDELAYE2_IDELAY_TYPE (PHY_1_A_IDELAYE2_IDELAY_TYPE),\n .A_IDELAYE2_IDELAY_VALUE (PHY_1_A_IDELAYE2_IDELAY_VALUE)\n ,.CKE_ODT_AUX (CKE_ODT_AUX)\n ,.PI_DIV2_INCDEC (PI_DIV2_INCDEC)\n)\n u_ddr_phy_4lanes\n(\n .rst (rst),\n .phy_clk (phy_clk_split1),\n .clk_div2 (clk_div2),\n .phy_ctl_clk (phy_ctl_clk_split1),\n .phy_ctl_wd (phy_ctl_wd_split1),\n .data_offset (phy_data_offset_1_split1),\n .phy_ctl_wr (phy_ctl_wr_split1),\n .mem_refclk (mem_refclk_split),\n .freq_refclk (freq_refclk_split),\n .mem_refclk_div4 (mem_refclk_div4_split),\n .sync_pulse (sync_pulse_split),\n .phy_dout (phy_dout_split1[HIGHEST_LANE_B1*80+320-1:320]),\n .phy_cmd_wr_en (phy_cmd_wr_en_split1),\n .phy_data_wr_en (phy_data_wr_en_split1),\n .phy_rd_en (phy_rd_en_split1),\n .pll_lock (pll_lock),\n .ddr_clk (ddr_clk_w[1]),\n .rclk (),\n .rst_out (rst_out_w[1]),\n .mcGo (mcGo_w[1]),\n .ref_dll_lock (ref_dll_lock_w[1]),\n .idelayctrl_refclk (idelayctrl_refclk),\n .idelay_inc (idelay_inc),\n .idelay_ce (idelay_ce),\n .idelay_ld (idelay_ld),\n .phy_ctl_mstr_empty (phy_ctl_mstr_empty),\n .if_rst (if_rst),\n .if_empty_def (if_empty_def),\n .byte_rd_en_oth_banks (byte_rd_en_oth_banks[3:2]),\n .if_a_empty (if_a_empty_v[1]),\n .if_empty (if_empty_v[1]),\n .byte_rd_en (byte_rd_en_v[1]),\n .if_empty_or (if_empty_or_v[1]),\n .if_empty_and (if_empty_and_v[1]),\n .of_ctl_a_full (of_ctl_a_full_v[1]),\n .of_data_a_full (of_data_a_full_v[1]),\n .of_ctl_full (of_ctl_full_v[1]),\n .of_data_full (of_data_full_v[1]),\n .pre_data_a_full (pre_data_a_full_v[1]),\n .phy_din (phy_din[HIGHEST_LANE_B1*80+320-1:320]),\n .phy_ctl_a_full (_phy_ctl_a_full_p[1]),\n .phy_ctl_full (_phy_ctl_full_p[1]),\n .phy_ctl_empty (phy_ctl_empty[1]),\n .mem_dq_out (mem_dq_out[HIGHEST_LANE_B1*12+48-1:48]),\n .mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B1*12+48-1:48]),\n .mem_dq_in (mem_dq_in[HIGHEST_LANE_B1*10+40-1:40]),\n .mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B1+4-1:4]),\n .mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B1+4-1:4]),\n .mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B1+4-1:4]),\n .aux_out (aux_out_[7:4]),\n .phy_ctl_ready (phy_ctl_ready_w[1]),\n .phy_write_calib (phy_write_calib),\n .phy_read_calib (phy_read_calib),\n// .scan_test_bus_A (scan_test_bus_A),\n// .scan_test_bus_B (),\n// .scan_test_bus_C (),\n// .scan_test_bus_D (),\n .phyGo (phyGo),\n .input_sink (input_sink),\n\n .calib_sel (calib_sel_byte1),\n .calib_zero_ctrl (calib_zero_ctrl[1]),\n .calib_zero_lanes (calib_zero_lanes_int[7:4]),\n .calib_in_common (calib_in_common),\n .po_coarse_enable (po_coarse_enable[1]),\n .po_fine_enable (po_fine_enable[1]),\n .po_fine_inc (po_fine_inc[1]),\n .po_coarse_inc (po_coarse_inc[1]),\n .po_counter_load_en (po_counter_load_en),\n .po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[1]),\n .po_counter_load_val (po_counter_load_val),\n .po_counter_read_en (po_counter_read_en),\n .po_coarse_overflow (po_coarse_overflow_w[1]),\n .po_fine_overflow (po_fine_overflow_w[1]),\n .po_counter_read_val (po_counter_read_val_w[1]),\n\n .pi_rst_dqs_find (pi_rst_dqs_find[1]),\n .pi_fine_enable (pi_fine_enable),\n .pi_fine_inc (pi_fine_inc),\n .pi_counter_load_en (pi_counter_load_en),\n .pi_counter_read_en (pi_counter_read_en),\n .pi_counter_load_val (pi_counter_load_val),\n .pi_fine_overflow (pi_fine_overflow_w[1]),\n .pi_counter_read_val (pi_counter_read_val_w[1]),\n .pi_dqs_found (pi_dqs_found_w[1]),\n .pi_dqs_found_all (pi_dqs_found_all_w[1]),\n .pi_dqs_found_any (pi_dqs_found_any_w[1]),\n .pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B1+4-1:4]),\n .pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B1+4-1:4]),\n .pi_dqs_out_of_range (pi_dqs_out_of_range_w[1]),\n .pi_phase_locked (pi_phase_locked_w[1]),\n .pi_phase_locked_all (pi_phase_locked_all_w[1]),\n .fine_delay (fine_delay),\n .fine_delay_sel (fine_delay_sel)\n);\n\n always @(posedge auxout_clk or posedge rst_auxout) begin\n if (rst_auxout) begin\n aux_out[4] <= #100 0;\n aux_out[6] <= #100 0;\n end\n else begin\n aux_out[4] <= #100 aux_out_[4];\n aux_out[6] <= #100 aux_out_[6];\n end\n end\n if ( LP_RCLK_SELECT_EDGE[1]) begin\n always @(posedge auxout_clk or posedge rst_auxout) begin\n if (rst_auxout) begin\n aux_out[5] <= #100 0;\n aux_out[7] <= #100 0;\n end\n else begin\n aux_out[5] <= #100 aux_out_[5];\n aux_out[7] <= #100 aux_out_[7];\n end\n end\n end\n else begin\n always @(negedge auxout_clk or posedge rst_auxout) begin\n if (rst_auxout) begin\n aux_out[5] <= #100 0;\n aux_out[7] <= #100 0;\n end\n else begin\n aux_out[5] <= #100 aux_out_[5];\n aux_out[7] <= #100 aux_out_[7];\n end\n end\n end\nend\nelse begin\n if ( HIGHEST_BANK > 1) begin\n assign phy_din[HIGHEST_LANE_B1*80+320-1:320] = 0;\n assign _phy_ctl_a_full_p[1] = 0;\n assign of_ctl_a_full_v[1] = 0;\n assign of_ctl_full_v[1] = 0;\n assign of_data_a_full_v[1] = 0;\n assign of_data_full_v[1] = 0;\n assign pre_data_a_full_v[1] = 0;\n assign if_empty_v[1] = 0;\n assign byte_rd_en_v[1] = 1;\n assign pi_phase_locked_lanes[HIGHEST_LANE_B1+4-1:4] = 4'b1111;\n assign pi_dqs_found_lanes[HIGHEST_LANE_B1+4-1:4] = 4'b1111;\n always @(*)\n aux_out[7:4] = 0;\n end\n assign pi_dqs_found_w[1] = 1;\n assign pi_dqs_found_all_w[1] = 1;\n assign pi_dqs_found_any_w[1] = 0;\n assign pi_dqs_out_of_range_w[1] = 0;\n assign pi_phase_locked_w[1] = 1;\n assign po_coarse_overflow_w[1] = 0;\n assign po_fine_overflow_w[1] = 0;\n assign pi_fine_overflow_w[1] = 0;\n assign po_counter_read_val_w[1] = 0;\n assign pi_counter_read_val_w[1] = 0;\n assign mcGo_w[1] = 1;\nend\n\nif ( BYTE_LANES_B2 != 0) begin : ddr_phy_4lanes_2\n\nmig_7series_v4_0_ddr_phy_4lanes #\n (\n .BYTE_LANES (BYTE_LANES_B2), /* four bits, one per lanes */\n .DATA_CTL_N (PHY_2_DATA_CTL), /* four bits, one per lane */\n .PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),\n .PO_FINE_DELAY (L_PHY_2_PO_FINE_DELAY),\n .BITLANES (PHY_2_BITLANES),\n .BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY),\n .BYTELANES_DDR_CK (LP_PHY_2_BYTELANES_DDR_CK),\n .LAST_BANK (PHY_2_IS_LAST_BANK ),\n .LANE_REMAP (PHY_2_LANE_REMAP),\n .OF_ALMOST_FULL_VALUE (PHY_2_OF_ALMOST_FULL_VALUE),\n .IF_ALMOST_EMPTY_VALUE (PHY_2_IF_ALMOST_EMPTY_VALUE),\n .GENERATE_IDELAYCTRL (PHY_2_GENERATE_IDELAYCTRL),\n .IODELAY_GRP (PHY_2_IODELAY_GRP),\n .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),\n .BANK_TYPE (BANK_TYPE),\n .NUM_DDR_CK (NUM_DDR_CK),\n .TCK (TCK),\n .RCLK_SELECT_LANE (RCLK_SELECT_LANE),\n .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),\n .SYNTHESIS (SYNTHESIS),\n .PC_CLK_RATIO (PHY_CLK_RATIO),\n .PC_EVENTS_DELAY (PHY_EVENTS_DELAY),\n .PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),\n .PC_BURST_MODE (PHY_2_A_BURST_MODE),\n .PC_SYNC_MODE (PHY_SYNC_MODE),\n .PC_MULTI_REGION (PHY_MULTI_REGION),\n .PC_PHY_COUNT_EN (PHY_COUNT_EN),\n .PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),\n .PC_CMD_OFFSET (PHY_2_CMD_OFFSET),\n .PC_RD_CMD_OFFSET_0 (PHY_2_RD_CMD_OFFSET_0),\n .PC_RD_CMD_OFFSET_1 (PHY_2_RD_CMD_OFFSET_1),\n .PC_RD_CMD_OFFSET_2 (PHY_2_RD_CMD_OFFSET_2),\n .PC_RD_CMD_OFFSET_3 (PHY_2_RD_CMD_OFFSET_3),\n .PC_RD_DURATION_0 (PHY_2_RD_DURATION_0),\n .PC_RD_DURATION_1 (PHY_2_RD_DURATION_1),\n .PC_RD_DURATION_2 (PHY_2_RD_DURATION_2),\n .PC_RD_DURATION_3 (PHY_2_RD_DURATION_3),\n .PC_WR_CMD_OFFSET_0 (PHY_2_WR_CMD_OFFSET_0),\n .PC_WR_CMD_OFFSET_1 (PHY_2_WR_CMD_OFFSET_1),\n .PC_WR_CMD_OFFSET_2 (PHY_2_WR_CMD_OFFSET_2),\n .PC_WR_CMD_OFFSET_3 (PHY_2_WR_CMD_OFFSET_3),\n .PC_WR_DURATION_0 (PHY_2_WR_DURATION_0),\n .PC_WR_DURATION_1 (PHY_2_WR_DURATION_1),\n .PC_WR_DURATION_2 (PHY_2_WR_DURATION_2),\n .PC_WR_DURATION_3 (PHY_2_WR_DURATION_3),\n .PC_AO_WRLVL_EN (PHY_2_AO_WRLVL_EN),\n .PC_AO_TOGGLE (PHY_2_AO_TOGGLE),\n\n .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),\n\n .A_PI_FINE_DELAY (L_PHY_2_A_PI_FINE_DELAY),\n .B_PI_FINE_DELAY (L_PHY_2_B_PI_FINE_DELAY),\n .C_PI_FINE_DELAY (L_PHY_2_C_PI_FINE_DELAY),\n .D_PI_FINE_DELAY (L_PHY_2_D_PI_FINE_DELAY),\n .A_PI_FREQ_REF_DIV (PHY_2_A_PI_FREQ_REF_DIV),\n .A_PI_BURST_MODE (PHY_2_A_BURST_MODE),\n .A_PI_OUTPUT_CLK_SRC (L_PHY_2_A_PI_OUTPUT_CLK_SRC),\n .B_PI_OUTPUT_CLK_SRC (L_PHY_2_B_PI_OUTPUT_CLK_SRC),\n .C_PI_OUTPUT_CLK_SRC (L_PHY_2_C_PI_OUTPUT_CLK_SRC),\n .D_PI_OUTPUT_CLK_SRC (L_PHY_2_D_PI_OUTPUT_CLK_SRC),\n .A_PO_OUTPUT_CLK_SRC (PHY_2_A_PO_OUTPUT_CLK_SRC),\n .A_PO_OCLK_DELAY (PHY_2_A_PO_OCLK_DELAY),\n .A_PO_OCLKDELAY_INV (PHY_2_A_PO_OCLKDELAY_INV),\n .A_OF_ARRAY_MODE (PHY_2_A_OF_ARRAY_MODE),\n .B_OF_ARRAY_MODE (PHY_2_B_OF_ARRAY_MODE),\n .C_OF_ARRAY_MODE (PHY_2_C_OF_ARRAY_MODE),\n .D_OF_ARRAY_MODE (PHY_2_D_OF_ARRAY_MODE),\n .A_IF_ARRAY_MODE (PHY_2_A_IF_ARRAY_MODE),\n .B_IF_ARRAY_MODE (PHY_2_B_IF_ARRAY_MODE),\n .C_IF_ARRAY_MODE (PHY_2_C_IF_ARRAY_MODE),\n .D_IF_ARRAY_MODE (PHY_2_D_IF_ARRAY_MODE),\n .A_OS_DATA_RATE (PHY_2_A_OSERDES_DATA_RATE),\n .A_OS_DATA_WIDTH (PHY_2_A_OSERDES_DATA_WIDTH),\n .B_OS_DATA_RATE (PHY_2_B_OSERDES_DATA_RATE),\n .B_OS_DATA_WIDTH (PHY_2_B_OSERDES_DATA_WIDTH),\n .C_OS_DATA_RATE (PHY_2_C_OSERDES_DATA_RATE),\n .C_OS_DATA_WIDTH (PHY_2_C_OSERDES_DATA_WIDTH),\n .D_OS_DATA_RATE (PHY_2_D_OSERDES_DATA_RATE),\n .D_OS_DATA_WIDTH (PHY_2_D_OSERDES_DATA_WIDTH),\n .A_IDELAYE2_IDELAY_TYPE (PHY_2_A_IDELAYE2_IDELAY_TYPE),\n .A_IDELAYE2_IDELAY_VALUE (PHY_2_A_IDELAYE2_IDELAY_VALUE)\n ,.CKE_ODT_AUX (CKE_ODT_AUX)\n ,.PI_DIV2_INCDEC (PI_DIV2_INCDEC)\n)\n u_ddr_phy_4lanes\n(\n .rst (rst),\n .phy_clk (phy_clk_split2),\n .clk_div2 (clk_div2),\n .phy_ctl_clk (phy_ctl_clk_split2),\n .phy_ctl_wd (phy_ctl_wd_split2),\n .data_offset (phy_data_offset_2_split2),\n .phy_ctl_wr (phy_ctl_wr_split2),\n .mem_refclk (mem_refclk_split),\n .freq_refclk (freq_refclk_split),\n .mem_refclk_div4 (mem_refclk_div4_split),\n .sync_pulse (sync_pulse_split),\n .phy_dout (phy_dout_split2[HIGHEST_LANE_B2*80+640-1:640]),\n .phy_cmd_wr_en (phy_cmd_wr_en_split2),\n .phy_data_wr_en (phy_data_wr_en_split2),\n .phy_rd_en (phy_rd_en_split2),\n .pll_lock (pll_lock),\n .ddr_clk (ddr_clk_w[2]),\n .rclk (),\n .rst_out (rst_out_w[2]),\n .mcGo (mcGo_w[2]),\n .ref_dll_lock (ref_dll_lock_w[2]),\n .idelayctrl_refclk (idelayctrl_refclk),\n .idelay_inc (idelay_inc),\n .idelay_ce (idelay_ce),\n .idelay_ld (idelay_ld),\n .phy_ctl_mstr_empty (phy_ctl_mstr_empty),\n .if_rst (if_rst),\n .if_empty_def (if_empty_def),\n .byte_rd_en_oth_banks (byte_rd_en_oth_banks[5:4]),\n .if_a_empty (if_a_empty_v[2]),\n .if_empty (if_empty_v[2]),\n .byte_rd_en (byte_rd_en_v[2]),\n .if_empty_or (if_empty_or_v[2]),\n .if_empty_and (if_empty_and_v[2]),\n .of_ctl_a_full (of_ctl_a_full_v[2]),\n .of_data_a_full (of_data_a_full_v[2]),\n .of_ctl_full (of_ctl_full_v[2]),\n .of_data_full (of_data_full_v[2]),\n .pre_data_a_full (pre_data_a_full_v[2]),\n .phy_din (phy_din[HIGHEST_LANE_B2*80+640-1:640]),\n .phy_ctl_a_full (_phy_ctl_a_full_p[2]),\n .phy_ctl_full (_phy_ctl_full_p[2]),\n .phy_ctl_empty (phy_ctl_empty[2]),\n .mem_dq_out (mem_dq_out[HIGHEST_LANE_B2*12+96-1:96]),\n .mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B2*12+96-1:96]),\n .mem_dq_in (mem_dq_in[HIGHEST_LANE_B2*10+80-1:80]),\n .mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B2-1+8:8]),\n .mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B2-1+8:8]),\n .mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B2-1+8:8]),\n .aux_out (aux_out_[11:8]),\n .phy_ctl_ready (phy_ctl_ready_w[2]),\n .phy_write_calib (phy_write_calib),\n .phy_read_calib (phy_read_calib),\n// .scan_test_bus_A (scan_test_bus_A),\n// .scan_test_bus_B (),\n// .scan_test_bus_C (),\n// .scan_test_bus_D (),\n .phyGo (phyGo),\n .input_sink (input_sink),\n\n .calib_sel (calib_sel_byte2),\n .calib_zero_ctrl (calib_zero_ctrl[2]),\n .calib_zero_lanes (calib_zero_lanes_int[11:8]),\n .calib_in_common (calib_in_common),\n .po_coarse_enable (po_coarse_enable[2]),\n .po_fine_enable (po_fine_enable[2]),\n .po_fine_inc (po_fine_inc[2]),\n .po_coarse_inc (po_coarse_inc[2]),\n .po_counter_load_en (po_counter_load_en),\n .po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[2]),\n .po_counter_load_val (po_counter_load_val),\n .po_counter_read_en (po_counter_read_en),\n .po_coarse_overflow (po_coarse_overflow_w[2]),\n .po_fine_overflow (po_fine_overflow_w[2]),\n .po_counter_read_val (po_counter_read_val_w[2]),\n\n .pi_rst_dqs_find (pi_rst_dqs_find[2]),\n .pi_fine_enable (pi_fine_enable),\n .pi_fine_inc (pi_fine_inc),\n .pi_counter_load_en (pi_counter_load_en),\n .pi_counter_read_en (pi_counter_read_en),\n .pi_counter_load_val (pi_counter_load_val),\n .pi_fine_overflow (pi_fine_overflow_w[2]),\n .pi_counter_read_val (pi_counter_read_val_w[2]),\n .pi_dqs_found (pi_dqs_found_w[2]),\n .pi_dqs_found_all (pi_dqs_found_all_w[2]),\n .pi_dqs_found_any (pi_dqs_found_any_w[2]),\n .pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B2+8-1:8]),\n .pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B2+8-1:8]),\n .pi_dqs_out_of_range (pi_dqs_out_of_range_w[2]),\n .pi_phase_locked (pi_phase_locked_w[2]),\n .pi_phase_locked_all (pi_phase_locked_all_w[2]),\n .fine_delay (fine_delay),\n .fine_delay_sel (fine_delay_sel)\n);\n always @(posedge auxout_clk or posedge rst_auxout) begin\n if (rst_auxout) begin\n aux_out[8] <= #100 0;\n aux_out[10] <= #100 0;\n end\n else begin\n aux_out[8] <= #100 aux_out_[8];\n aux_out[10] <= #100 aux_out_[10];\n end\n end\n if ( LP_RCLK_SELECT_EDGE[1]) begin\n always @(posedge auxout_clk or posedge rst_auxout) begin\n if (rst_auxout) begin\n aux_out[9] <= #100 0;\n aux_out[11] <= #100 0;\n end\n else begin\n aux_out[9] <= #100 aux_out_[9];\n aux_out[11] <= #100 aux_out_[11];\n end\n end\n end\n else begin\n always @(negedge auxout_clk or posedge rst_auxout) begin\n if (rst_auxout) begin\n aux_out[9] <= #100 0;\n aux_out[11] <= #100 0;\n end\n else begin\n aux_out[9] <= #100 aux_out_[9];\n aux_out[11] <= #100 aux_out_[11];\n end\n end\n end\nend\nelse begin\n if ( HIGHEST_BANK > 2) begin\n assign phy_din[HIGHEST_LANE_B2*80+640-1:640] = 0;\n assign _phy_ctl_a_full_p[2] = 0;\n assign of_ctl_a_full_v[2] = 0;\n assign of_ctl_full_v[2] = 0;\n assign of_data_a_full_v[2] = 0;\n assign of_data_full_v[2] = 0;\n assign pre_data_a_full_v[2] = 0;\n assign if_empty_v[2] = 0;\n assign byte_rd_en_v[2] = 1;\n assign pi_phase_locked_lanes[HIGHEST_LANE_B2+8-1:8] = 4'b1111;\n assign pi_dqs_found_lanes[HIGHEST_LANE_B2+8-1:8] = 4'b1111;\n always @(*)\n aux_out[11:8] = 0;\n end\n assign pi_dqs_found_w[2] = 1;\n assign pi_dqs_found_all_w[2] = 1;\n assign pi_dqs_found_any_w[2] = 0;\n assign pi_dqs_out_of_range_w[2] = 0;\n assign pi_phase_locked_w[2] = 1;\n assign po_coarse_overflow_w[2] = 0;\n assign po_fine_overflow_w[2] = 0;\n assign po_counter_read_val_w[2] = 0;\n assign pi_counter_read_val_w[2] = 0;\n assign mcGo_w[2] = 1;\nend\nendgenerate\n\ngenerate\n\n// for single bank , emit an extra phaser_in to generate rclk\n// so that auxout can be placed in another region\n// if desired\n\nif ( BYTE_LANES_B1 == 0 && BYTE_LANES_B2 == 0 && RCLK_SELECT_BANK>0)\nbegin : phaser_in_rclk\n\nlocalparam L_EXTRA_PI_FINE_DELAY = DEFAULT_RCLK_DELAY;\n\nPHASER_IN_PHY #(\n .BURST_MODE ( PHY_0_A_BURST_MODE),\n .CLKOUT_DIV ( PHY_0_A_PI_CLKOUT_DIV),\n .FREQ_REF_DIV ( PHY_0_A_PI_FREQ_REF_DIV),\n .REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS),\n .FINE_DELAY ( L_EXTRA_PI_FINE_DELAY),\n .OUTPUT_CLK_SRC ( RCLK_PI_OUTPUT_CLK_SRC)\n) phaser_in_rclk (\n .DQSFOUND (),\n .DQSOUTOFRANGE (),\n .FINEOVERFLOW (),\n .PHASELOCKED (),\n .ISERDESRST (),\n .ICLKDIV (),\n .ICLK (),\n .COUNTERREADVAL (),\n .RCLK (),\n .WRENABLE (),\n .BURSTPENDINGPHY (),\n .ENCALIBPHY (),\n .FINEENABLE (0),\n .FREQREFCLK (freq_refclk),\n .MEMREFCLK (mem_refclk),\n .RANKSELPHY (0),\n .PHASEREFCLK (),\n .RSTDQSFIND (0),\n .RST (rst),\n .FINEINC (),\n .COUNTERLOADEN (),\n .COUNTERREADEN (),\n .COUNTERLOADVAL (),\n .SYNCIN (sync_pulse),\n .SYSCLK (phy_clk)\n);\n\nend\n\nendgenerate\n\n\n\nalways @(*) begin\n case (calib_sel[5:3])\n 3'b000: begin\n po_coarse_overflow = po_coarse_overflow_w[0];\n po_fine_overflow = po_fine_overflow_w[0];\n po_counter_read_val = po_counter_read_val_w[0];\n pi_fine_overflow = pi_fine_overflow_w[0];\n pi_counter_read_val = pi_counter_read_val_w[0];\n pi_phase_locked = pi_phase_locked_w[0];\n if ( calib_in_common)\n pi_dqs_found = pi_dqs_found_any;\n else\n pi_dqs_found = pi_dqs_found_w[0];\n pi_dqs_out_of_range = pi_dqs_out_of_range_w[0];\n end\n 3'b001: begin\n po_coarse_overflow = po_coarse_overflow_w[1];\n po_fine_overflow = po_fine_overflow_w[1];\n po_counter_read_val = po_counter_read_val_w[1];\n pi_fine_overflow = pi_fine_overflow_w[1];\n pi_counter_read_val = pi_counter_read_val_w[1];\n pi_phase_locked = pi_phase_locked_w[1];\n if ( calib_in_common)\n pi_dqs_found = pi_dqs_found_any;\n else\n pi_dqs_found = pi_dqs_found_w[1];\n pi_dqs_out_of_range = pi_dqs_out_of_range_w[1];\n end\n 3'b010: begin\n po_coarse_overflow = po_coarse_overflow_w[2];\n po_fine_overflow = po_fine_overflow_w[2];\n po_counter_read_val = po_counter_read_val_w[2];\n pi_fine_overflow = pi_fine_overflow_w[2];\n pi_counter_read_val = pi_counter_read_val_w[2];\n pi_phase_locked = pi_phase_locked_w[2];\n if ( calib_in_common)\n pi_dqs_found = pi_dqs_found_any;\n else\n pi_dqs_found = pi_dqs_found_w[2];\n pi_dqs_out_of_range = pi_dqs_out_of_range_w[2];\n end\n default: begin\n po_coarse_overflow = 0;\n po_fine_overflow = 0;\n po_counter_read_val = 0;\n pi_fine_overflow = 0;\n pi_counter_read_val = 0;\n pi_phase_locked = 0;\n pi_dqs_found = 0;\n pi_dqs_out_of_range = 0;\n end\n endcase\nend\n\nendmodule // mc_phy\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_mc_phy_wrapper.v", "content": "//*****************************************************************************\n// (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor : Xilinx\n// \\ \\ \\/ Version : %version\n// \\ \\ Application : MIG\n// / / Filename : ddr_mc_phy_wrapper.v\n// /___/ /\\ Date Last Modified : $date$\n// \\ \\ / \\ Date Created : Oct 10 2010\n// \\___\\/\\___\\\n//\n//Device : 7 Series\n//Design Name : DDR3 SDRAM\n//Purpose : Wrapper file that encompasses the MC_PHY module\n// instantiation and handles the vector remapping between\n// the MC_PHY ports and the user's DDR3 ports. Vector\n// remapping affects DDR3 control, address, and DQ/DQS/DM.\n//Reference :\n//Revision History :\n//*****************************************************************************\n\n`timescale 1 ps / 1 ps\n\nmodule mig_7series_v4_0_ddr_mc_phy_wrapper #\n (\n parameter TCQ = 100, // Register delay (simulation only)\n parameter tCK = 2500, // ps\n parameter BANK_TYPE = \"HP_IO\", // # = \"HP_IO\", \"HPL_IO\", \"HR_IO\", \"HRL_IO\"\n parameter DATA_IO_PRIM_TYPE = \"DEFAULT\", // # = \"HP_LP\", \"HR_LP\", \"DEFAULT\"\n parameter DATA_IO_IDLE_PWRDWN = \"ON\", // \"ON\" or \"OFF\"\n parameter IODELAY_GRP = \"IODELAY_MIG\",\n parameter FPGA_SPEED_GRADE = 1,\n parameter nCK_PER_CLK = 4, // Memory:Logic clock ratio\n parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank\n parameter BANK_WIDTH = 3, // # of bank address\n parameter CKE_WIDTH = 1, // # of clock enable outputs\n parameter CS_WIDTH = 1, // # of chip select\n parameter CK_WIDTH = 1, // # of CK\n parameter CWL = 5, // CAS Write latency\n parameter DDR2_DQSN_ENABLE = \"YES\", // Enable differential DQS for DDR2\n parameter DM_WIDTH = 8, // # of data mask\n parameter DQ_WIDTH = 16, // # of data bits\n parameter DQS_CNT_WIDTH = 3, // ceil(log2(DQS_WIDTH))\n parameter DQS_WIDTH = 8, // # of strobe pairs\n parameter DRAM_TYPE = \"DDR3\", // DRAM type (DDR2, DDR3)\n parameter RANKS = 4, // # of ranks\n parameter ODT_WIDTH = 1, // # of ODT outputs\n parameter POC_USE_METASTABLE_SAMP = \"FALSE\",\n parameter REG_CTRL = \"OFF\", // \"ON\" for registered DIMM\n parameter ROW_WIDTH = 16, // # of row/column address\n parameter USE_CS_PORT = 1, // Support chip select output\n parameter USE_DM_PORT = 1, // Support data mask output\n parameter USE_ODT_PORT = 1, // Support ODT output\n parameter IBUF_LPWR_MODE = \"OFF\", // input buffer low power option\n parameter LP_DDR_CK_WIDTH = 2,\n\n // Hard PHY parameters\n parameter PHYCTL_CMD_FIFO = \"FALSE\",\n parameter DATA_CTL_B0 = 4'hc,\n parameter DATA_CTL_B1 = 4'hf,\n parameter DATA_CTL_B2 = 4'hf,\n parameter DATA_CTL_B3 = 4'hf,\n parameter DATA_CTL_B4 = 4'hf,\n parameter BYTE_LANES_B0 = 4'b1111,\n parameter BYTE_LANES_B1 = 4'b0000,\n parameter BYTE_LANES_B2 = 4'b0000,\n parameter BYTE_LANES_B3 = 4'b0000,\n parameter BYTE_LANES_B4 = 4'b0000,\n parameter PHY_0_BITLANES = 48'h0000_0000_0000,\n parameter PHY_1_BITLANES = 48'h0000_0000_0000,\n parameter PHY_2_BITLANES = 48'h0000_0000_0000,\n // Parameters calculated outside of this block\n parameter HIGHEST_BANK = 3, // Highest I/O bank index\n parameter HIGHEST_LANE = 12, // Highest byte lane index\n // ** Pin mapping parameters\n // Parameters for mapping between hard PHY and physical DDR3 signals\n // There are 2 classes of parameters:\n // - DQS_BYTE_MAP, CK_BYTE_MAP, CKE_ODT_BYTE_MAP: These consist of\n // 8-bit elements. Each element indicates the bank and byte lane\n // location of that particular signal. The bit lane in this case\n // doesn't need to be specified, either because there's only one\n // pin pair in each byte lane that the DQS or CK pair can be\n // located at, or in the case of CKE_ODT_BYTE_MAP, only the byte\n // lane needs to be specified in order to determine which byte\n // lane generates the RCLK (Note that CKE, and ODT must be located\n // in the same bank, thus only one element in CKE_ODT_BYTE_MAP)\n // [7:4] = bank # (0-4)\n // [3:0] = byte lane # (0-3)\n // - All other MAP parameters: These consist of 12-bit elements. Each\n // element indicates the bank, byte lane, and bit lane location of\n // that particular signal:\n // [11:8] = bank # (0-4)\n // [7:4] = byte lane # (0-3)\n // [3:0] = bit lane # (0-11)\n // Note that not all elements in all parameters will be used - it\n // depends on the actual widths of the DDR3 buses. The parameters are\n // structured to support a maximum of:\n // - DQS groups: 18\n // - data mask bits: 18\n // In addition, the default parameter size of some of the parameters will\n // support a certain number of bits, however, this can be expanded at\n // compile time by expanding the width of the vector passed into this\n // parameter\n // - chip selects: 10\n // - bank bits: 3\n // - address bits: 16\n parameter CK_BYTE_MAP\n = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,\n parameter ADDR_MAP\n = 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,\n parameter BANK_MAP = 36'h000_000_000,\n parameter CAS_MAP = 12'h000,\n parameter CKE_ODT_BYTE_MAP = 8'h00,\n parameter CKE_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter ODT_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter CKE_ODT_AUX = \"FALSE\",\n parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,\n parameter PARITY_MAP = 12'h000,\n parameter RAS_MAP = 12'h000,\n parameter WE_MAP = 12'h000,\n parameter DQS_BYTE_MAP\n = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,\n // DATAx_MAP parameter is used for byte lane X in the design\n parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,\n // MASK0_MAP used for bytes [8:0], MASK1_MAP for bytes [17:9]\n parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,\n parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,\n // Simulation options\n parameter SIM_CAL_OPTION = \"NONE\",\n\n // The PHY_CONTROL primitive in the bank where PLL exists is declared\n // as the Master PHY_CONTROL.\n parameter MASTER_PHY_CTL = 1,\n parameter DRAM_WIDTH = 8,\n parameter PI_DIV2_INCDEC = \"FALSE\"\n )\n (\n input rst,\n input iddr_rst,\n input clk,\n input clk_div2,\n input freq_refclk,\n input mem_refclk,\n input pll_lock,\n input sync_pulse,\n input mmcm_ps_clk,\n input idelayctrl_refclk,\n input phy_cmd_wr_en,\n input phy_data_wr_en,\n input [31:0] phy_ctl_wd,\n input phy_ctl_wr,\n input phy_if_empty_def,\n input phy_if_reset,\n input [5:0] data_offset_1,\n input [5:0] data_offset_2,\n input [3:0] aux_in_1,\n input [3:0] aux_in_2,\n output [4:0] idelaye2_init_val,\n output [5:0] oclkdelay_init_val,\n output if_empty,\n output phy_ctl_full,\n output phy_cmd_full,\n output phy_data_full,\n output phy_pre_data_a_full,\n output [(CK_WIDTH * LP_DDR_CK_WIDTH)-1:0] ddr_clk,\n output phy_mc_go,\n input phy_write_calib,\n input phy_read_calib,\n input calib_in_common,\n input [5:0] calib_sel,\n input [DQS_CNT_WIDTH:0] byte_sel_cnt,\n input [DRAM_WIDTH-1:0] fine_delay_incdec_pb,\n input fine_delay_sel,\n input [HIGHEST_BANK-1:0] calib_zero_inputs,\n input [HIGHEST_BANK-1:0] calib_zero_ctrl,\n input [2:0] po_fine_enable,\n input [2:0] po_coarse_enable,\n input [2:0] po_fine_inc,\n input [2:0] po_coarse_inc,\n input po_counter_load_en,\n input po_counter_read_en,\n input [2:0] po_sel_fine_oclk_delay,\n input [8:0] po_counter_load_val,\n output [8:0] po_counter_read_val,\n output [5:0] pi_counter_read_val,\n input [HIGHEST_BANK-1:0] pi_rst_dqs_find,\n input pi_fine_enable,\n input pi_fine_inc,\n input pi_counter_load_en,\n input [5:0] pi_counter_load_val,\n input idelay_ce,\n input idelay_inc,\n input idelay_ld,\n input idle,\n output pi_phase_locked,\n output pi_phase_locked_all,\n output pi_dqs_found,\n output pi_dqs_found_all,\n output pi_dqs_out_of_range,\n // From/to calibration logic/soft PHY\n input phy_init_data_sel,\n input [nCK_PER_CLK*ROW_WIDTH-1:0] mux_address,\n input [nCK_PER_CLK*BANK_WIDTH-1:0] mux_bank,\n input [nCK_PER_CLK-1:0] mux_cas_n,\n input [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mux_cs_n,\n input [nCK_PER_CLK-1:0] mux_ras_n,\n input [1:0] mux_odt,\n input [nCK_PER_CLK-1:0] mux_cke,\n input [nCK_PER_CLK-1:0] mux_we_n,\n input [nCK_PER_CLK-1:0] parity_in,\n input [2*nCK_PER_CLK*DQ_WIDTH-1:0] mux_wrdata,\n input [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mux_wrdata_mask,\n input mux_reset_n,\n output [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,\n // Memory I/F\n output [ROW_WIDTH-1:0] ddr_addr,\n output [BANK_WIDTH-1:0] ddr_ba,\n output ddr_cas_n,\n output [CKE_WIDTH-1:0] ddr_cke,\n output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,\n output [DM_WIDTH-1:0] ddr_dm,\n output [ODT_WIDTH-1:0] ddr_odt,\n output ddr_parity,\n output ddr_ras_n,\n output ddr_we_n,\n output ddr_reset_n,\n inout [DQ_WIDTH-1:0] ddr_dq,\n inout [DQS_WIDTH-1:0] ddr_dqs,\n inout [DQS_WIDTH-1:0] ddr_dqs_n,\n //output iodelay_ctrl_rdy,\n output pd_out\n\n ,input dbg_pi_counter_read_en\n ,output ref_dll_lock\n ,input rst_phaser_ref\n ,output [11:0] dbg_pi_phase_locked_phy4lanes\n ,output [11:0] dbg_pi_dqs_found_lanes_phy4lanes\n );\n\n function [71:0] generate_bytelanes_ddr_ck;\n input [143:0] ck_byte_map;\n integer v ;\n begin\n generate_bytelanes_ddr_ck = 'b0 ;\n for (v = 0; v < CK_WIDTH; v = v + 1) begin\n if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 2)\n generate_bytelanes_ddr_ck[48+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;\n else if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 1)\n generate_bytelanes_ddr_ck[24+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;\n else\n generate_bytelanes_ddr_ck[4*v+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;\n end\n end\n endfunction\n\n function [(2*CK_WIDTH*8)-1:0] generate_ddr_ck_map;\n input [143:0] ck_byte_map;\n integer g;\n begin\n generate_ddr_ck_map = 'b0 ;\n for(g = 0 ; g < CK_WIDTH ; g= g + 1) begin\n generate_ddr_ck_map[(g*2*8)+:8] = (ck_byte_map[(g*8)+:4] == 4'd0) ? \"A\" :\n (ck_byte_map[(g*8)+:4] == 4'd1) ? \"B\" :\n (ck_byte_map[(g*8)+:4] == 4'd2) ? \"C\" : \"D\" ;\n generate_ddr_ck_map[(((g*2)+1)*8)+:8] = (ck_byte_map[((g*8)+4)+:4] == 4'd0) ? \"0\" :\n (ck_byte_map[((g*8)+4)+:4] == 4'd1) ? \"1\" : \"2\" ; //each STRING charater takes 0 location\n end\n end\n endfunction\n\n\n\n // Enable low power mode for input buffer\n localparam IBUF_LOW_PWR\n = (IBUF_LPWR_MODE == \"OFF\") ? \"FALSE\" :\n ((IBUF_LPWR_MODE == \"ON\") ? \"TRUE\" : \"ILLEGAL\");\n\n // Ratio of data to strobe\n localparam DQ_PER_DQS = DQ_WIDTH / DQS_WIDTH;\n // number of data phases per internal clock\n localparam PHASE_PER_CLK = 2*nCK_PER_CLK;\n // used to determine routing to OUT_FIFO for control/address for 2:1\n // vs. 4:1 memory:internal clock ratio modes\n localparam PHASE_DIV = 4 / nCK_PER_CLK;\n\n localparam CLK_PERIOD = tCK * nCK_PER_CLK;\n\n // Create an aggregate parameters for data mapping to reduce # of generate\n // statements required in remapping code. Need to account for the case\n // when the DQ:DQS ratio is not 8:1 - in this case, each DATAx_MAP\n // parameter will have fewer than 8 elements used\n localparam FULL_DATA_MAP = {DATA17_MAP[12*DQ_PER_DQS-1:0],\n DATA16_MAP[12*DQ_PER_DQS-1:0],\n DATA15_MAP[12*DQ_PER_DQS-1:0],\n DATA14_MAP[12*DQ_PER_DQS-1:0],\n DATA13_MAP[12*DQ_PER_DQS-1:0],\n DATA12_MAP[12*DQ_PER_DQS-1:0],\n DATA11_MAP[12*DQ_PER_DQS-1:0],\n DATA10_MAP[12*DQ_PER_DQS-1:0],\n DATA9_MAP[12*DQ_PER_DQS-1:0],\n DATA8_MAP[12*DQ_PER_DQS-1:0],\n DATA7_MAP[12*DQ_PER_DQS-1:0],\n DATA6_MAP[12*DQ_PER_DQS-1:0],\n DATA5_MAP[12*DQ_PER_DQS-1:0],\n DATA4_MAP[12*DQ_PER_DQS-1:0],\n DATA3_MAP[12*DQ_PER_DQS-1:0],\n DATA2_MAP[12*DQ_PER_DQS-1:0],\n DATA1_MAP[12*DQ_PER_DQS-1:0],\n DATA0_MAP[12*DQ_PER_DQS-1:0]};\n // Same deal, but for data mask mapping\n localparam FULL_MASK_MAP = {MASK1_MAP, MASK0_MAP};\n localparam TMP_BYTELANES_DDR_CK = generate_bytelanes_ddr_ck(CK_BYTE_MAP) ;\n localparam TMP_GENERATE_DDR_CK_MAP = generate_ddr_ck_map(CK_BYTE_MAP) ;\n\n // Temporary parameters to determine which bank is outputting the CK/CK#\n // Eventually there will be support for multiple CK/CK# output\n //localparam TMP_DDR_CLK_SELECT_BANK = (CK_BYTE_MAP[7:4]);\n //// Temporary method to force MC_PHY to generate ODDR associated with\n //// CK/CK# output only for a single byte lane in the design. All banks\n //// that won't be generating the CK/CK# will have \"UNUSED\" as their\n //// PHY_GENERATE_DDR_CK parameter\n //localparam TMP_PHY_0_GENERATE_DDR_CK\n // = (TMP_DDR_CLK_SELECT_BANK != 0) ? \"UNUSED\" :\n // ((CK_BYTE_MAP[1:0] == 2'b00) ? \"A\" :\n // ((CK_BYTE_MAP[1:0] == 2'b01) ? \"B\" :\n // ((CK_BYTE_MAP[1:0] == 2'b10) ? \"C\" : \"D\")));\n //localparam TMP_PHY_1_GENERATE_DDR_CK\n // = (TMP_DDR_CLK_SELECT_BANK != 1) ? \"UNUSED\" :\n // ((CK_BYTE_MAP[1:0] == 2'b00) ? \"A\" :\n // ((CK_BYTE_MAP[1:0] == 2'b01) ? \"B\" :\n // ((CK_BYTE_MAP[1:0] == 2'b10) ? \"C\" : \"D\")));\n //localparam TMP_PHY_2_GENERATE_DDR_CK\n // = (TMP_DDR_CLK_SELECT_BANK != 2) ? \"UNUSED\" :\n // ((CK_BYTE_MAP[1:0] == 2'b00) ? \"A\" :\n // ((CK_BYTE_MAP[1:0] == 2'b01) ? \"B\" :\n // ((CK_BYTE_MAP[1:0] == 2'b10) ? \"C\" : \"D\")));\n\n // Function to generate MC_PHY parameters PHY_BITLANES_OUTONLYx\n // which indicates which bit lanes in data byte lanes are\n // output-only bitlanes (e.g. used specifically for data mask outputs)\n function [143:0] calc_phy_bitlanes_outonly;\n input [215:0] data_mask_in;\n integer z;\n begin\n calc_phy_bitlanes_outonly = 'b0;\n // Only enable BITLANES parameters for data masks if, well, if\n // the data masks are actually enabled\n if (USE_DM_PORT == 1)\n for (z = 0; z < DM_WIDTH; z = z + 1)\n calc_phy_bitlanes_outonly[48*data_mask_in[(12*z+8)+:3] +\n 12*data_mask_in[(12*z+4)+:2] +\n data_mask_in[12*z+:4]] = 1'b1;\n end\n endfunction\n\n localparam PHY_BITLANES_OUTONLY = calc_phy_bitlanes_outonly(FULL_MASK_MAP);\n localparam PHY_0_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[47:0];\n localparam PHY_1_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[95:48];\n localparam PHY_2_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[143:96];\n\n // Determine which bank and byte lane generates the RCLK used to clock\n // out the auxilliary (ODT, CKE) outputs\n localparam CKE_ODT_RCLK_SELECT_BANK_AUX_ON\n = (CKE_ODT_BYTE_MAP[7:4] == 4'h0) ? 0 :\n ((CKE_ODT_BYTE_MAP[7:4] == 4'h1) ? 1 :\n ((CKE_ODT_BYTE_MAP[7:4] == 4'h2) ? 2 :\n ((CKE_ODT_BYTE_MAP[7:4] == 4'h3) ? 3 :\n ((CKE_ODT_BYTE_MAP[7:4] == 4'h4) ? 4 : -1))));\n localparam CKE_ODT_RCLK_SELECT_LANE_AUX_ON\n = (CKE_ODT_BYTE_MAP[3:0] == 4'h0) ? \"A\" :\n ((CKE_ODT_BYTE_MAP[3:0] == 4'h1) ? \"B\" :\n ((CKE_ODT_BYTE_MAP[3:0] == 4'h2) ? \"C\" :\n ((CKE_ODT_BYTE_MAP[3:0] == 4'h3) ? \"D\" : \"ILLEGAL\")));\n\n localparam CKE_ODT_RCLK_SELECT_BANK_AUX_OFF\n = (CKE_MAP[11:8] == 4'h0) ? 0 :\n ((CKE_MAP[11:8] == 4'h1) ? 1 :\n ((CKE_MAP[11:8] == 4'h2) ? 2 :\n ((CKE_MAP[11:8] == 4'h3) ? 3 :\n ((CKE_MAP[11:8] == 4'h4) ? 4 : -1))));\n localparam CKE_ODT_RCLK_SELECT_LANE_AUX_OFF\n = (CKE_MAP[7:4] == 4'h0) ? \"A\" :\n ((CKE_MAP[7:4] == 4'h1) ? \"B\" :\n ((CKE_MAP[7:4] == 4'h2) ? \"C\" :\n ((CKE_MAP[7:4] == 4'h3) ? \"D\" : \"ILLEGAL\")));\n\n\n localparam CKE_ODT_RCLK_SELECT_BANK = (CKE_ODT_AUX == \"TRUE\") ? CKE_ODT_RCLK_SELECT_BANK_AUX_ON : CKE_ODT_RCLK_SELECT_BANK_AUX_OFF ;\n localparam CKE_ODT_RCLK_SELECT_LANE = (CKE_ODT_AUX == \"TRUE\") ? CKE_ODT_RCLK_SELECT_LANE_AUX_ON : CKE_ODT_RCLK_SELECT_LANE_AUX_OFF ;\n\n\n //***************************************************************************\n // OCLKDELAYED tap setting calculation:\n // Parameters for calculating amount of phase shifting output clock to\n // achieve 90 degree offset between DQS and DQ on writes\n //***************************************************************************\n\n //90 deg equivalent to 0.25 for MEM_RefClk <= 300 MHz\n // and 1.25 for Mem_RefClk > 300 MHz\n //localparam PO_OCLKDELAY_INV = (((SIM_CAL_OPTION == \"NONE\") && (tCK >= 2500)) || (tCK >= 3333)) ? \"FALSE\" : \"TRUE\";//DIV2 change\n localparam PO_OCLKDELAY_INV = (tCK >= 2500) ? \"FALSE\" : \"TRUE\";//DIV2 change\n\n //DIV1: MemRefClk >= 400 MHz, DIV2: 200 <= MemRefClk < 400,\n //DIV4: MemRefClk < 200 MHz\n localparam PHY_0_A_PI_FREQ_REF_DIV = tCK > 5000 ? \"DIV4\" :\n tCK >= 2500 ? \"DIV2\": \"NONE\";//DIV2 change\n\n localparam FREQ_REF_DIV = (PHY_0_A_PI_FREQ_REF_DIV == \"DIV4\" ? 4 :\n PHY_0_A_PI_FREQ_REF_DIV == \"DIV2\" ? 2 : 1);\n\n // Intrinsic delay between OCLK and OCLK_DELAYED Phaser Output\n localparam real INT_DELAY = 0.4392/FREQ_REF_DIV + 100.0/tCK;\n\n // Whether OCLK_DELAY output comes inverted or not\n localparam real HALF_CYCLE_DELAY = 0.5*(PO_OCLKDELAY_INV == \"TRUE\" ? 1 : 0);\n\n // Phaser-Out Stage3 Tap delay for 90 deg shift.\n // Maximum tap delay is FreqRefClk period distributed over 64 taps\n // localparam real TAP_DELAY = MC_OCLK_DELAY/64/FREQ_REF_DIV;\n localparam real MC_OCLK_DELAY = ((PO_OCLKDELAY_INV == \"TRUE\" ? 1.25 : 0.25) -\n (INT_DELAY + HALF_CYCLE_DELAY))\n * 63 * FREQ_REF_DIV;\n //localparam integer PHY_0_A_PO_OCLK_DELAY = MC_OCLK_DELAY;\n\n localparam integer PHY_0_A_PO_OCLK_DELAY_HW\n = (tCK > 2273) ? 34 :\n (tCK > 2000) ? 33 :\n (tCK > 1724) ? 32 :\n (tCK > 1515) ? 31 :\n (tCK > 1315) ? 30 :\n (tCK > 1136) ? 29 :\n (tCK > 1021) ? 28 : 27;\n\n // Note that simulation requires a different value than in H/W because of the\n // difference in the way delays are modeled\n localparam integer PHY_0_A_PO_OCLK_DELAY = (SIM_CAL_OPTION == \"NONE\") ? // DIV2 change\n ((tCK >= 2500) ? 0 :\n (DRAM_TYPE == \"DDR3\") ? PHY_0_A_PO_OCLK_DELAY_HW : 30) :\n (tCK >= 2500) ? 0 : MC_OCLK_DELAY;\n\n // Initial DQ IDELAY value\n localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = (SIM_CAL_OPTION != \"FAST_CAL\") ? 0 :\n (tCK < 1000) ? 0 :\n (tCK < 1330) ? 0 :\n (tCK < 2300) ? 0 :\n (tCK < 2500) ? 2 : 0;\n //localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = 0;\n\n // Aux_out parameters RD_CMD_OFFSET = CL+2? and WR_CMD_OFFSET = CWL+3?\n localparam PHY_0_RD_CMD_OFFSET_0 = 10;\n localparam PHY_0_RD_CMD_OFFSET_1 = 10;\n localparam PHY_0_RD_CMD_OFFSET_2 = 10;\n localparam PHY_0_RD_CMD_OFFSET_3 = 10;\n // 4:1 and 2:1 have WR_CMD_OFFSET values for ODT timing\n localparam PHY_0_WR_CMD_OFFSET_0 = (nCK_PER_CLK == 4) ? 8 : 4;\n localparam PHY_0_WR_CMD_OFFSET_1 = (nCK_PER_CLK == 4) ? 8 : 4;\n localparam PHY_0_WR_CMD_OFFSET_2 = (nCK_PER_CLK == 4) ? 8 : 4;\n localparam PHY_0_WR_CMD_OFFSET_3 = (nCK_PER_CLK == 4) ? 8 : 4;\n // 4:1 and 2:1 have different values\n localparam PHY_0_WR_DURATION_0 = 7;\n localparam PHY_0_WR_DURATION_1 = 7;\n localparam PHY_0_WR_DURATION_2 = 7;\n localparam PHY_0_WR_DURATION_3 = 7;\n // Aux_out parameters for toggle mode (CKE)\n localparam CWL_M = (REG_CTRL == \"ON\") ? CWL + 1 : CWL;\n localparam PHY_0_CMD_OFFSET = (nCK_PER_CLK == 4) ? (CWL_M % 2) ? 8 : 9 :\n (CWL < 7) ?\n 4 + ((CWL_M % 2) ? 0 : 1) :\n 5 + ((CWL_M % 2) ? 0 : 1);\n\n // temporary parameter to enable/disable PHY PC counters. In both 4:1 and\n // 2:1 cases, this should be disabled. For now, enable for 4:1 mode to\n // avoid making too many changes at once.\n localparam PHY_COUNT_EN = (nCK_PER_CLK == 4) ? \"TRUE\" : \"FALSE\";\n\n\n wire [((HIGHEST_LANE+3)/4)*4-1:0] aux_out;\n wire [HIGHEST_LANE-1:0] mem_dqs_in;\n wire [HIGHEST_LANE-1:0] mem_dqs_out;\n wire [HIGHEST_LANE-1:0] mem_dqs_ts;\n wire [HIGHEST_LANE*10-1:0] mem_dq_in;\n wire [HIGHEST_LANE*12-1:0] mem_dq_out;\n wire [HIGHEST_LANE*12-1:0] mem_dq_ts;\n wire [DQ_WIDTH-1:0] in_dq;\n wire [DQS_WIDTH-1:0] in_dqs;\n wire [ROW_WIDTH-1:0] out_addr;\n wire [BANK_WIDTH-1:0] out_ba;\n wire out_cas_n;\n wire [CS_WIDTH*nCS_PER_RANK-1:0] out_cs_n;\n wire [DM_WIDTH-1:0] out_dm;\n wire [ODT_WIDTH -1:0] out_odt;\n wire [CKE_WIDTH -1 :0] out_cke ;\n wire [DQ_WIDTH-1:0] out_dq;\n wire [DQS_WIDTH-1:0] out_dqs;\n wire out_parity;\n wire out_ras_n;\n wire out_we_n;\n wire [HIGHEST_LANE*80-1:0] phy_din;\n wire [HIGHEST_LANE*80-1:0] phy_dout;\n wire phy_rd_en;\n wire [DM_WIDTH-1:0] ts_dm;\n wire [DQ_WIDTH-1:0] ts_dq;\n wire [DQS_WIDTH-1:0] ts_dqs;\n wire [DQS_WIDTH-1:0] in_dqs_lpbk_to_iddr;\n wire [DQS_WIDTH-1:0] pd_out_pre;\n //wire metaQ;\n\n reg [31:0] phy_ctl_wd_i1;\n reg [31:0] phy_ctl_wd_i2;\n reg phy_ctl_wr_i1;\n reg phy_ctl_wr_i2;\n reg [5:0] data_offset_1_i1;\n reg [5:0] data_offset_1_i2;\n reg [5:0] data_offset_2_i1;\n reg [5:0] data_offset_2_i2;\n wire [31:0] phy_ctl_wd_temp;\n wire phy_ctl_wr_temp;\n wire [5:0] data_offset_1_temp;\n wire [5:0] data_offset_2_temp;\n wire [5:0] data_offset_1_of;\n wire [5:0] data_offset_2_of;\n wire [31:0] phy_ctl_wd_of;\n wire phy_ctl_wr_of /* synthesis syn_maxfan = 1 */;\n wire [3:0] phy_ctl_full_temp;\n\n wire data_io_idle_pwrdwn;\n reg [29:0] fine_delay_mod; //3 bit per DQ\n reg fine_delay_sel_r; //timing adj with fine_delay_incdec_pb\n\n wire iddr_rst_i;\n\n (* use_dsp48 = \"no\" *) wire [DQS_CNT_WIDTH:0] byte_sel_cnt_w1;\n\n // Always read from input data FIFOs when not empty\n assign phy_rd_en = !if_empty;\n\n // IDELAYE2 initial value\n assign idelaye2_init_val = PHY_0_A_IDELAYE2_IDELAY_VALUE;\n assign oclkdelay_init_val = PHY_0_A_PO_OCLK_DELAY;\n\n // Idle powerdown when there are no pending reads in the MC\n assign data_io_idle_pwrdwn = DATA_IO_IDLE_PWRDWN == \"ON\" ? idle : 1'b0;\n assign iddr_rst_i = iddr_rst;\n //***************************************************************************\n // Auxiliary output steering\n //***************************************************************************\n\n // For a 4 rank I/F the aux_out[3:0] from the addr/ctl bank will be\n // mapped to ddr_odt and the aux_out[7:4] from one of the data banks\n // will map to ddr_cke. For I/Fs less than 4 the aux_out[3:0] from the\n // addr/ctl bank would bank would map to both ddr_odt and ddr_cke.\n generate\n if(CKE_ODT_AUX == \"TRUE\")begin:cke_thru_auxpins\n if (CKE_WIDTH == 1) begin : gen_cke\n // Explicitly instantiate OBUF to ensure that these are present\n // in the netlist. Typically this is not required since NGDBUILD\n // at the top-level knows to infer an I/O/IOBUF and therefore a\n // top-level LOC constraint can be attached to that pin. This does\n // not work when a hierarchical flow is used and the LOC is applied\n // at the individual core-level UCF\n OBUF u_cke_obuf\n (\n .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]),\n .O (ddr_cke)\n );\n end else begin: gen_2rank_cke\n OBUF u_cke0_obuf\n (\n .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]),\n .O (ddr_cke[0])\n );\n OBUF u_cke1_obuf\n (\n .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),\n .O (ddr_cke[1])\n );\n end\n end\n endgenerate\n\n generate\n if(CKE_ODT_AUX == \"TRUE\")begin:odt_thru_auxpins\n if (USE_ODT_PORT == 1) begin : gen_use_odt\n // Explicitly instantiate OBUF to ensure that these are present\n // in the netlist. Typically this is not required since NGDBUILD\n // at the top-level knows to infer an I/O/IOBUF and therefore a\n // top-level LOC constraint can be attached to that pin. This does\n // not work when a hierarchical flow is used and the LOC is applied\n // at the individual core-level UCF\n OBUF u_odt_obuf\n (\n .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+1]),\n .O (ddr_odt[0])\n );\n if (ODT_WIDTH == 2 && RANKS == 1) begin: gen_2port_odt\n OBUF u_odt1_obuf\n (\n .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),\n .O (ddr_odt[1])\n );\n end else if (ODT_WIDTH == 2 && RANKS == 2) begin: gen_2rank_odt\n OBUF u_odt1_obuf\n (\n .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]),\n .O (ddr_odt[1])\n );\n end else if (ODT_WIDTH == 3 && RANKS == 1) begin: gen_3port_odt\n OBUF u_odt1_obuf\n (\n .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),\n .O (ddr_odt[1])\n );\n OBUF u_odt2_obuf\n (\n .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]),\n .O (ddr_odt[2])\n );\n end\n end else begin\n assign ddr_odt = 'b0;\n end\n end\n endgenerate\n\n //***************************************************************************\n // Read data bit steering\n //***************************************************************************\n\n // Transpose elements of rd_data_map to form final read data output:\n // phy_din elements are grouped according to \"physical bit\" - e.g.\n // for nCK_PER_CLK = 4, there are 8 data phases transfered per physical\n // bit per clock cycle:\n // = {dq0_fall3, dq0_rise3, dq0_fall2, dq0_rise2,\n // dq0_fall1, dq0_rise1, dq0_fall0, dq0_rise0}\n // whereas rd_data is are grouped according to \"phase\" - e.g.\n // = {dq7_rise0, dq6_rise0, dq5_rise0, dq4_rise0,\n // dq3_rise0, dq2_rise0, dq1_rise0, dq0_rise0}\n // therefore rd_data is formed by transposing phy_din - e.g.\n // for nCK_PER_CLK = 4, and DQ_WIDTH = 16, and assuming MC_PHY\n // bit_lane[0] maps to DQ[0], and bit_lane[1] maps to DQ[1], then\n // the assignments for bits of rd_data corresponding to DQ[1:0]\n // would be:\n // {rd_data[112], rd_data[96], rd_data[80], rd_data[64],\n // rd_data[48], rd_data[32], rd_data[16], rd_data[0]} = phy_din[7:0]\n // {rd_data[113], rd_data[97], rd_data[81], rd_data[65],\n // rd_data[49], rd_data[33], rd_data[17], rd_data[1]} = phy_din[15:8]\n generate\n genvar i, j;\n for (i = 0; i < DQ_WIDTH; i = i + 1) begin: gen_loop_rd_data_1\n for (j = 0; j < PHASE_PER_CLK; j = j + 1) begin: gen_loop_rd_data_2\n assign rd_data[DQ_WIDTH*j + i]\n = phy_din[(320*FULL_DATA_MAP[(12*i+8)+:3]+\n 80*FULL_DATA_MAP[(12*i+4)+:2] +\n 8*FULL_DATA_MAP[12*i+:4]) + j];\n end\n end\n endgenerate\n\n //generage idelay_inc per bits\n\n reg [11:0] cal_tmp;\n reg [95:0] byte_sel_data_map;\n\n assign byte_sel_cnt_w1 = byte_sel_cnt;\n\n always @ (posedge clk) begin\n byte_sel_data_map <= #TCQ FULL_DATA_MAP[12*DQ_PER_DQS*byte_sel_cnt_w1+:96];\n end\n\n always @ (posedge clk) begin\n fine_delay_mod[((byte_sel_data_map[3:0])*3)+:3] <= #TCQ {fine_delay_incdec_pb[0],2'b00};\n fine_delay_mod[((byte_sel_data_map[12+3:12])*3)+:3] <= #TCQ {fine_delay_incdec_pb[1],2'b00};\n fine_delay_mod[((byte_sel_data_map[24+3:24])*3)+:3] <= #TCQ {fine_delay_incdec_pb[2],2'b00};\n fine_delay_mod[((byte_sel_data_map[36+3:36])*3)+:3] <= #TCQ {fine_delay_incdec_pb[3],2'b00};\n fine_delay_mod[((byte_sel_data_map[48+3:48])*3)+:3] <= #TCQ {fine_delay_incdec_pb[4],2'b00};\n fine_delay_mod[((byte_sel_data_map[60+3:60])*3)+:3] <= #TCQ {fine_delay_incdec_pb[5],2'b00};\n fine_delay_mod[((byte_sel_data_map[72+3:72])*3)+:3] <= #TCQ {fine_delay_incdec_pb[6],2'b00};\n fine_delay_mod[((byte_sel_data_map[84+3:84])*3)+:3] <= #TCQ {fine_delay_incdec_pb[7],2'b00};\n fine_delay_sel_r <= #TCQ fine_delay_sel;\n end\n\n //***************************************************************************\n // Control/address\n //***************************************************************************\n\n assign out_cas_n\n = mem_dq_out[48*CAS_MAP[10:8] + 12*CAS_MAP[5:4] + CAS_MAP[3:0]];\n\n generate\n // if signal placed on bit lanes [0-9]\n if (CAS_MAP[3:0] < 4'hA) begin: gen_cas_lt10\n // Determine routing based on clock ratio mode. If running in 4:1\n // mode, then all four bits from logic are used. If 2:1 mode, only\n // 2-bits are provided by logic, and each bit is repeated 2x to form\n // 4-bit input to IN_FIFO, e.g.\n // 4:1 mode: phy_dout[] = {in[3], in[2], in[1], in[0]}\n // 2:1 mode: phy_dout[] = {in[1], in[1], in[0], in[0]}\n assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] +\n 8*CAS_MAP[3:0])+:4]\n = {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV],\n mux_cas_n[1/PHASE_DIV], mux_cas_n[0]};\n end else begin: gen_cas_ge10\n // If signal is placed in bit lane [10] or [11], route to upper\n // nibble of phy_dout lane [5] or [6] respectively (in this case\n // phy_dout lane [5, 6] are multiplexed to take input for two\n // different SDR signals - this is how bits[10,11] need to be\n // provided to the OUT_FIFO\n assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] +\n 8*(CAS_MAP[3:0]-5) + 4)+:4]\n = {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV],\n mux_cas_n[1/PHASE_DIV], mux_cas_n[0]};\n end\n endgenerate\n\n assign out_ras_n\n = mem_dq_out[48*RAS_MAP[10:8] + 12*RAS_MAP[5:4] + RAS_MAP[3:0]];\n\n generate\n if (RAS_MAP[3:0] < 4'hA) begin: gen_ras_lt10\n assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] +\n 8*RAS_MAP[3:0])+:4]\n = {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV],\n mux_ras_n[1/PHASE_DIV], mux_ras_n[0]};\n end else begin: gen_ras_ge10\n assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] +\n 8*(RAS_MAP[3:0]-5) + 4)+:4]\n = {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV],\n mux_ras_n[1/PHASE_DIV], mux_ras_n[0]};\n end\n endgenerate\n\n assign out_we_n\n = mem_dq_out[48*WE_MAP[10:8] + 12*WE_MAP[5:4] + WE_MAP[3:0]];\n\n generate\n if (WE_MAP[3:0] < 4'hA) begin: gen_we_lt10\n assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] +\n 8*WE_MAP[3:0])+:4]\n = {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV],\n mux_we_n[1/PHASE_DIV], mux_we_n[0]};\n end else begin: gen_we_ge10\n assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] +\n 8*(WE_MAP[3:0]-5) + 4)+:4]\n = {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV],\n mux_we_n[1/PHASE_DIV], mux_we_n[0]};\n end\n endgenerate\n\n generate\n if (REG_CTRL == \"ON\") begin: gen_parity_out\n // Generate addr/ctrl parity output only for DDR3 and DDR2 registered DIMMs\n assign out_parity\n = mem_dq_out[48*PARITY_MAP[10:8] + 12*PARITY_MAP[5:4] +\n PARITY_MAP[3:0]];\n if (PARITY_MAP[3:0] < 4'hA) begin: gen_lt10\n assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] +\n 8*PARITY_MAP[3:0])+:4]\n = {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV],\n parity_in[1/PHASE_DIV], parity_in[0]};\n end else begin: gen_ge10\n assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] +\n 8*(PARITY_MAP[3:0]-5) + 4)+:4]\n = {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV],\n parity_in[1/PHASE_DIV], parity_in[0]};\n end\n end\n endgenerate\n\n //*****************************************************************\n\n generate\n genvar m, n,x;\n\n //*****************************************************************\n // Control/address (multi-bit) buses\n //*****************************************************************\n\n // Row/Column address\n for (m = 0; m < ROW_WIDTH; m = m + 1) begin: gen_addr_out\n assign out_addr[m]\n = mem_dq_out[48*ADDR_MAP[(12*m+8)+:3] +\n 12*ADDR_MAP[(12*m+4)+:2] +\n ADDR_MAP[12*m+:4]];\n\n if (ADDR_MAP[12*m+:4] < 4'hA) begin: gen_lt10\n // For multi-bit buses, we also have to deal with transposition\n // when going from the logic-side control bus to phy_dout\n for (n = 0; n < 4; n = n + 1) begin: loop_xpose\n assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] +\n 80*ADDR_MAP[(12*m+4)+:2] +\n 8*ADDR_MAP[12*m+:4] + n]\n = mux_address[ROW_WIDTH*(n/PHASE_DIV) + m];\n end\n end else begin: gen_ge10\n for (n = 0; n < 4; n = n + 1) begin: loop_xpose\n assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] +\n 80*ADDR_MAP[(12*m+4)+:2] +\n 8*(ADDR_MAP[12*m+:4]-5) + 4 + n]\n = mux_address[ROW_WIDTH*(n/PHASE_DIV) + m];\n end\n end\n end\n\n // Bank address\n for (m = 0; m < BANK_WIDTH; m = m + 1) begin: gen_ba_out\n assign out_ba[m]\n = mem_dq_out[48*BANK_MAP[(12*m+8)+:3] +\n 12*BANK_MAP[(12*m+4)+:2] +\n BANK_MAP[12*m+:4]];\n\n if (BANK_MAP[12*m+:4] < 4'hA) begin: gen_lt10\n for (n = 0; n < 4; n = n + 1) begin: loop_xpose\n assign phy_dout[320*BANK_MAP[(12*m+8)+:3] +\n 80*BANK_MAP[(12*m+4)+:2] +\n 8*BANK_MAP[12*m+:4] + n]\n = mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m];\n end\n end else begin: gen_ge10\n for (n = 0; n < 4; n = n + 1) begin: loop_xpose\n assign phy_dout[320*BANK_MAP[(12*m+8)+:3] +\n 80*BANK_MAP[(12*m+4)+:2] +\n 8*(BANK_MAP[12*m+:4]-5) + 4 + n]\n = mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m];\n end\n end\n end\n\n // Chip select\n if (USE_CS_PORT == 1) begin: gen_cs_n_out\n for (m = 0; m < CS_WIDTH*nCS_PER_RANK; m = m + 1) begin: gen_cs_out\n assign out_cs_n[m]\n = mem_dq_out[48*CS_MAP[(12*m+8)+:3] +\n 12*CS_MAP[(12*m+4)+:2] +\n CS_MAP[12*m+:4]];\n if (CS_MAP[12*m+:4] < 4'hA) begin: gen_lt10\n for (n = 0; n < 4; n = n + 1) begin: loop_xpose\n assign phy_dout[320*CS_MAP[(12*m+8)+:3] +\n 80*CS_MAP[(12*m+4)+:2] +\n 8*CS_MAP[12*m+:4] + n]\n = mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m];\n end\n end else begin: gen_ge10\n for (n = 0; n < 4; n = n + 1) begin: loop_xpose\n assign phy_dout[320*CS_MAP[(12*m+8)+:3] +\n 80*CS_MAP[(12*m+4)+:2] +\n 8*(CS_MAP[12*m+:4]-5) + 4 + n]\n = mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m];\n end\n end\n end\n end\n\n\n if(CKE_ODT_AUX == \"FALSE\") begin\n // ODT_ports\n wire [ODT_WIDTH*nCK_PER_CLK -1 :0] mux_odt_remap ;\n\n if(RANKS == 1) begin\n for(x =0 ; x < nCK_PER_CLK ; x = x+1) begin\n assign mux_odt_remap[(x*ODT_WIDTH)+:ODT_WIDTH] = {ODT_WIDTH{mux_odt[0]}} ;\n end\n end else begin\n for(x =0 ; x < 2*nCK_PER_CLK ; x = x+2) begin\n assign mux_odt_remap[(x*ODT_WIDTH/RANKS)+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[0]}} ;\n assign mux_odt_remap[((x*ODT_WIDTH/RANKS)+(ODT_WIDTH/RANKS))+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[1]}} ;\n end\n end\n\n if (USE_ODT_PORT == 1) begin: gen_odt_out\n for (m = 0; m < ODT_WIDTH; m = m + 1) begin: gen_odt_out_1\n assign out_odt[m]\n = mem_dq_out[48*ODT_MAP[(12*m+8)+:3] +\n 12*ODT_MAP[(12*m+4)+:2] +\n ODT_MAP[12*m+:4]];\n if (ODT_MAP[12*m+:4] < 4'hA) begin: gen_lt10\n for (n = 0; n < 4; n = n + 1) begin: loop_xpose\n assign phy_dout[320*ODT_MAP[(12*m+8)+:3] +\n 80*ODT_MAP[(12*m+4)+:2] +\n 8*ODT_MAP[12*m+:4] + n]\n = mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m];\n end\n end else begin: gen_ge10\n for (n = 0; n < 4; n = n + 1) begin: loop_xpose\n assign phy_dout[320*ODT_MAP[(12*m+8)+:3] +\n 80*ODT_MAP[(12*m+4)+:2] +\n 8*(ODT_MAP[12*m+:4]-5) + 4 + n]\n = mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m];\n end\n end\n end\n end\n\n\n wire [CKE_WIDTH*nCK_PER_CLK -1:0] mux_cke_remap ;\n\n for(x = 0 ; x < nCK_PER_CLK ; x = x +1) begin\n assign mux_cke_remap[(x*CKE_WIDTH)+:CKE_WIDTH] = {CKE_WIDTH{mux_cke[x]}} ;\n end\n\n\n\n for (m = 0; m < CKE_WIDTH; m = m + 1) begin: gen_cke_out\n assign out_cke[m]\n = mem_dq_out[48*CKE_MAP[(12*m+8)+:3] +\n 12*CKE_MAP[(12*m+4)+:2] +\n CKE_MAP[12*m+:4]];\n if (CKE_MAP[12*m+:4] < 4'hA) begin: gen_lt10\n for (n = 0; n < 4; n = n + 1) begin: loop_xpose\n assign phy_dout[320*CKE_MAP[(12*m+8)+:3] +\n 80*CKE_MAP[(12*m+4)+:2] +\n 8*CKE_MAP[12*m+:4] + n]\n = mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m];\n end\n end else begin: gen_ge10\n for (n = 0; n < 4; n = n + 1) begin: loop_xpose\n assign phy_dout[320*CKE_MAP[(12*m+8)+:3] +\n 80*CKE_MAP[(12*m+4)+:2] +\n 8*(CKE_MAP[12*m+:4]-5) + 4 + n]\n = mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m];\n end\n end\n end\n end\n\n //*****************************************************************\n // Data mask\n //*****************************************************************\n\n if (USE_DM_PORT == 1) begin: gen_dm_out\n for (m = 0; m < DM_WIDTH; m = m + 1) begin: gen_dm_out\n assign out_dm[m]\n = mem_dq_out[48*FULL_MASK_MAP[(12*m+8)+:3] +\n 12*FULL_MASK_MAP[(12*m+4)+:2] +\n FULL_MASK_MAP[12*m+:4]];\n assign ts_dm[m]\n = mem_dq_ts[48*FULL_MASK_MAP[(12*m+8)+:3] +\n 12*FULL_MASK_MAP[(12*m+4)+:2] +\n FULL_MASK_MAP[12*m+:4]];\n for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose\n assign phy_dout[320*FULL_MASK_MAP[(12*m+8)+:3] +\n 80*FULL_MASK_MAP[(12*m+4)+:2] +\n 8*FULL_MASK_MAP[12*m+:4] + n]\n = mux_wrdata_mask[DM_WIDTH*n + m];\n end\n end\n end\n\n //*****************************************************************\n // Input and output DQ\n //*****************************************************************\n\n for (m = 0; m < DQ_WIDTH; m = m + 1) begin: gen_dq_inout\n // to MC_PHY\n assign mem_dq_in[40*FULL_DATA_MAP[(12*m+8)+:3] +\n 10*FULL_DATA_MAP[(12*m+4)+:2] +\n FULL_DATA_MAP[12*m+:4]]\n = in_dq[m];\n // to I/O buffers\n assign out_dq[m]\n = mem_dq_out[48*FULL_DATA_MAP[(12*m+8)+:3] +\n 12*FULL_DATA_MAP[(12*m+4)+:2] +\n FULL_DATA_MAP[12*m+:4]];\n assign ts_dq[m]\n = mem_dq_ts[48*FULL_DATA_MAP[(12*m+8)+:3] +\n 12*FULL_DATA_MAP[(12*m+4)+:2] +\n FULL_DATA_MAP[12*m+:4]];\n for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose\n assign phy_dout[320*FULL_DATA_MAP[(12*m+8)+:3] +\n 80*FULL_DATA_MAP[(12*m+4)+:2] +\n 8*FULL_DATA_MAP[12*m+:4] + n]\n = mux_wrdata[DQ_WIDTH*n + m];\n end\n end\n\n //*****************************************************************\n // Input and output DQS\n //*****************************************************************\n\n for (m = 0; m < DQS_WIDTH; m = m + 1) begin: gen_dqs_inout\n // to MC_PHY\n assign mem_dqs_in[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]]\n = in_dqs[m];\n // to I/O buffers\n assign out_dqs[m]\n = mem_dqs_out[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]];\n assign ts_dqs[m]\n = mem_dqs_ts[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]];\n end\n endgenerate\n\n assign pd_out = pd_out_pre[byte_sel_cnt_w1];\n\n\n //***************************************************************************\n // Memory I/F output and I/O buffer instantiation\n //***************************************************************************\n\n // Note on instantiation - generally at the minimum, it's not required to\n // instantiate the output buffers - they can be inferred by the synthesis\n // tool, and there aren't any attributes that need to be associated with\n // them. Consider as a future option to take out the OBUF instantiations\n\n OBUF u_cas_n_obuf\n (\n .I (out_cas_n),\n .O (ddr_cas_n)\n );\n\n OBUF u_ras_n_obuf\n (\n .I (out_ras_n),\n .O (ddr_ras_n)\n );\n\n OBUF u_we_n_obuf\n (\n .I (out_we_n),\n .O (ddr_we_n)\n );\n\n generate\n genvar p;\n\n for (p = 0; p < ROW_WIDTH; p = p + 1) begin: gen_addr_obuf\n OBUF u_addr_obuf\n (\n .I (out_addr[p]),\n .O (ddr_addr[p])\n );\n end\n\n for (p = 0; p < BANK_WIDTH; p = p + 1) begin: gen_bank_obuf\n OBUF u_bank_obuf\n (\n .I (out_ba[p]),\n .O (ddr_ba[p])\n );\n end\n\n if (USE_CS_PORT == 1) begin: gen_cs_n_obuf\n for (p = 0; p < CS_WIDTH*nCS_PER_RANK; p = p + 1) begin: gen_cs_obuf\n OBUF u_cs_n_obuf\n (\n .I (out_cs_n[p]),\n .O (ddr_cs_n[p])\n );\n end\n end\n if(CKE_ODT_AUX == \"FALSE\")begin:cke_odt_thru_outfifo\n if (USE_ODT_PORT== 1) begin: gen_odt_obuf\n for (p = 0; p < ODT_WIDTH; p = p + 1) begin: gen_odt_obuf\n OBUF u_cs_n_obuf\n (\n .I (out_odt[p]),\n .O (ddr_odt[p])\n );\n end\n end\n for (p = 0; p < CKE_WIDTH; p = p + 1) begin: gen_cke_obuf\n OBUF u_cs_n_obuf\n (\n .I (out_cke[p]),\n .O (ddr_cke[p])\n );\n end\n end\n\n if (REG_CTRL == \"ON\") begin: gen_parity_obuf\n // Generate addr/ctrl parity output only for DDR3 registered DIMMs\n OBUF u_parity_obuf\n (\n .I (out_parity),\n .O (ddr_parity)\n );\n end else begin: gen_parity_tieoff\n assign ddr_parity = 1'b0;\n end\n\n if ((DRAM_TYPE == \"DDR3\") || (REG_CTRL == \"ON\")) begin: gen_reset_obuf\n // Generate reset output only for DDR3 and DDR2 RDIMMs\n OBUF u_reset_obuf\n (\n .I (mux_reset_n),\n .O (ddr_reset_n)\n );\n end else begin: gen_reset_tieoff\n assign ddr_reset_n = 1'b1;\n end\n\n if (USE_DM_PORT == 1) begin: gen_dm_obuf\n for (p = 0; p < DM_WIDTH; p = p + 1) begin: loop_dm\n OBUFT u_dm_obuf\n (\n .I (out_dm[p]),\n .T (ts_dm[p]),\n .O (ddr_dm[p])\n );\n end\n end else begin: gen_dm_tieoff\n assign ddr_dm = 'b0;\n end\n\n if (DATA_IO_PRIM_TYPE == \"HP_LP\") begin: gen_dq_iobuf_HP\n for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf\n IOBUF_DCIEN #\n (\n .IBUF_LOW_PWR (IBUF_LOW_PWR)\n )\n u_iobuf_dq\n (\n .DCITERMDISABLE (data_io_idle_pwrdwn),\n .IBUFDISABLE (data_io_idle_pwrdwn),\n .I (out_dq[p]),\n .T (ts_dq[p]),\n .O (in_dq[p]),\n .IO (ddr_dq[p])\n );\n end\n end else if (DATA_IO_PRIM_TYPE == \"HR_LP\") begin: gen_dq_iobuf_HR\n for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf\n IOBUF_INTERMDISABLE #\n (\n .IBUF_LOW_PWR (IBUF_LOW_PWR)\n )\n u_iobuf_dq\n (\n .INTERMDISABLE (data_io_idle_pwrdwn),\n .IBUFDISABLE (data_io_idle_pwrdwn),\n .I (out_dq[p]),\n .T (ts_dq[p]),\n .O (in_dq[p]),\n .IO (ddr_dq[p])\n );\n end\n end else begin: gen_dq_iobuf_default\n for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf\n IOBUF #\n (\n .IBUF_LOW_PWR (IBUF_LOW_PWR)\n )\n u_iobuf_dq\n (\n .I (out_dq[p]),\n .T (ts_dq[p]),\n .O (in_dq[p]),\n .IO (ddr_dq[p])\n );\n end\n end\n\n //if (DATA_IO_PRIM_TYPE == \"HP_LP\") begin: gen_dqs_iobuf_HP\n if ((BANK_TYPE == \"HP_IO\") || (BANK_TYPE == \"HPL_IO\")) begin: gen_dqs_iobuf_HP\n for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf\n if ((DRAM_TYPE == \"DDR2\") &&\n (DDR2_DQSN_ENABLE != \"YES\")) begin: gen_ddr2_dqs_se\n IOBUF_DCIEN #\n (\n .IBUF_LOW_PWR (IBUF_LOW_PWR)\n )\n u_iobuf_dqs\n (\n .DCITERMDISABLE (data_io_idle_pwrdwn),\n .IBUFDISABLE (data_io_idle_pwrdwn),\n .I (out_dqs[p]),\n .T (ts_dqs[p]),\n .O (in_dqs[p]),\n .IO (ddr_dqs[p])\n );\n assign ddr_dqs_n[p] = 1'b0;\n assign pd_out_pre[p] = 1'b0;\n end else if ((DRAM_TYPE == \"DDR2\") ||\n (tCK > 2500)) begin : gen_ddr2_or_low_dqs_diff\n IOBUFDS_DCIEN #\n (\n .IBUF_LOW_PWR (IBUF_LOW_PWR),\n .DQS_BIAS (\"TRUE\")\n )\n u_iobuf_dqs\n (\n .DCITERMDISABLE (data_io_idle_pwrdwn),\n .IBUFDISABLE (data_io_idle_pwrdwn),\n .I (out_dqs[p]),\n .T (ts_dqs[p]),\n .O (in_dqs[p]),\n .IO (ddr_dqs[p]),\n .IOB (ddr_dqs_n[p])\n );\n assign pd_out_pre[p] = 1'b0;\n end else begin: gen_dqs_diff\n IOBUFDS_DIFF_OUT_DCIEN #\n (\n .IBUF_LOW_PWR (IBUF_LOW_PWR),\n .DQS_BIAS (\"TRUE\"),\n .SIM_DEVICE (\"7SERIES\"),\n .USE_IBUFDISABLE (\"FALSE\")\n )\n u_iobuf_dqs\n (\n .DCITERMDISABLE (data_io_idle_pwrdwn),\n .I (out_dqs[p]),\n .TM (ts_dqs[p]),\n .TS (ts_dqs[p]),\n .OB (in_dqs_lpbk_to_iddr[p]),\n .O (in_dqs[p]),\n .IO (ddr_dqs[p]),\n .IOB (ddr_dqs_n[p])\n );\n\n mig_7series_v4_0_poc_pd #\n (\n .TCQ (TCQ),\n .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP)\n )\n u_iddr_edge_det\n (\n .clk (clk),\n .iddr_rst (iddr_rst_i),\n .kclk (in_dqs_lpbk_to_iddr[p]),\n .mmcm_ps_clk (mmcm_ps_clk),\n .pd_out (pd_out_pre[p])\n );\n end\n end\n //end else if (DATA_IO_PRIM_TYPE == \"HR_LP\") begin: gen_dqs_iobuf_HR\n end else if ((BANK_TYPE == \"HR_IO\") || (BANK_TYPE == \"HRL_IO\")) begin: gen_dqs_iobuf_HR\n for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf\n if ((DRAM_TYPE == \"DDR2\") &&\n (DDR2_DQSN_ENABLE != \"YES\")) begin: gen_ddr2_dqs_se\n IOBUF_INTERMDISABLE #\n (\n .IBUF_LOW_PWR (IBUF_LOW_PWR)\n )\n u_iobuf_dqs\n (\n .INTERMDISABLE (data_io_idle_pwrdwn),\n .IBUFDISABLE (data_io_idle_pwrdwn),\n .I (out_dqs[p]),\n .T (ts_dqs[p]),\n .O (in_dqs[p]),\n .IO (ddr_dqs[p])\n );\n assign ddr_dqs_n[p] = 1'b0;\n assign pd_out_pre[p] = 1'b0;\n end else if ((DRAM_TYPE == \"DDR2\") ||\n (tCK > 2500)) begin: gen_ddr2_or_low_dqs_diff\n IOBUFDS_INTERMDISABLE #\n (\n .IBUF_LOW_PWR (IBUF_LOW_PWR),\n .DQS_BIAS (\"TRUE\")\n )\n u_iobuf_dqs\n (\n .INTERMDISABLE (data_io_idle_pwrdwn),\n .IBUFDISABLE (data_io_idle_pwrdwn),\n .I (out_dqs[p]),\n .T (ts_dqs[p]),\n .O (in_dqs[p]),\n .IO (ddr_dqs[p]),\n .IOB (ddr_dqs_n[p])\n );\n assign pd_out_pre[p] = 1'b0;\n end else begin: gen_dqs_diff\n IOBUFDS_DIFF_OUT_INTERMDISABLE #\n (\n .IBUF_LOW_PWR (IBUF_LOW_PWR),\n .DQS_BIAS (\"TRUE\"),\n .SIM_DEVICE (\"7SERIES\"),\n .USE_IBUFDISABLE (\"FALSE\")\n )\n u_iobuf_dqs\n (\n .INTERMDISABLE (data_io_idle_pwrdwn),\n //.IBUFDISABLE (data_io_idle_pwrdwn),\n .I (out_dqs[p]),\n .TM (ts_dqs[p]),\n .TS (ts_dqs[p]),\n .OB (in_dqs_lpbk_to_iddr[p]),\n .O (in_dqs[p]),\n .IO (ddr_dqs[p]),\n .IOB (ddr_dqs_n[p])\n );\n\n mig_7series_v4_0_poc_pd #\n (\n .TCQ (TCQ),\n .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP)\n )\n u_iddr_edge_det\n (\n .clk (clk),\n .iddr_rst (iddr_rst_i),\n .kclk (in_dqs_lpbk_to_iddr[p]),\n .mmcm_ps_clk (mmcm_ps_clk),\n .pd_out (pd_out_pre[p])\n );\n end\n end\n end else begin: gen_dqs_iobuf_default\n for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf\n if ((DRAM_TYPE == \"DDR2\") &&\n (DDR2_DQSN_ENABLE != \"YES\")) begin: gen_ddr2_dqs_se\n IOBUF #\n (\n .IBUF_LOW_PWR (IBUF_LOW_PWR)\n )\n u_iobuf_dqs\n (\n .I (out_dqs[p]),\n .T (ts_dqs[p]),\n .O (in_dqs[p]),\n .IO (ddr_dqs[p])\n );\n assign ddr_dqs_n[p] = 1'b0;\n assign pd_out_pre[p] = 1'b0;\n end else begin: gen_dqs_diff\n IOBUFDS #\n (\n .IBUF_LOW_PWR (IBUF_LOW_PWR),\n .DQS_BIAS (\"TRUE\")\n )\n u_iobuf_dqs\n (\n .I (out_dqs[p]),\n .T (ts_dqs[p]),\n .O (in_dqs[p]),\n .IO (ddr_dqs[p]),\n .IOB (ddr_dqs_n[p])\n );\n assign pd_out_pre[p] = 1'b0;\n end\n end\n end\n\n endgenerate\n\n always @(posedge clk) begin\n phy_ctl_wd_i1 <= #TCQ phy_ctl_wd;\n phy_ctl_wr_i1 <= #TCQ phy_ctl_wr;\n phy_ctl_wd_i2 <= #TCQ phy_ctl_wd_i1;\n phy_ctl_wr_i2 <= #TCQ phy_ctl_wr_i1;\n data_offset_1_i1 <= #TCQ data_offset_1;\n data_offset_1_i2 <= #TCQ data_offset_1_i1;\n data_offset_2_i1 <= #TCQ data_offset_2;\n data_offset_2_i2 <= #TCQ data_offset_2_i1;\n end\n\n\n // 2 cycles of command delay needed for 4;1 mode. 2:1 mode does not need it.\n // 2:1 mode the command goes through pre fifo\n assign phy_ctl_wd_temp = (nCK_PER_CLK == 4) ? phy_ctl_wd_i2 : phy_ctl_wd_of;\n assign phy_ctl_wr_temp = (nCK_PER_CLK == 4) ? phy_ctl_wr_i2 : phy_ctl_wr_of;\n assign data_offset_1_temp = (nCK_PER_CLK == 4) ? data_offset_1_i2 : data_offset_1_of;\n assign data_offset_2_temp = (nCK_PER_CLK == 4) ? data_offset_2_i2 : data_offset_2_of;\n\n generate\n begin\n\n mig_7series_v4_0_ddr_of_pre_fifo #\n (\n .TCQ (25),\n .DEPTH (8),\n .WIDTH (32)\n )\n phy_ctl_pre_fifo_0\n (\n .clk (clk),\n .rst (rst),\n .full_in (phy_ctl_full_temp[1]),\n .wr_en_in (phy_ctl_wr),\n .d_in (phy_ctl_wd),\n .wr_en_out (phy_ctl_wr_of),\n .d_out (phy_ctl_wd_of)\n );\n\n mig_7series_v4_0_ddr_of_pre_fifo #\n (\n .TCQ (25),\n .DEPTH (8),\n .WIDTH (6)\n )\n phy_ctl_pre_fifo_1\n (\n .clk (clk),\n .rst (rst),\n .full_in (phy_ctl_full_temp[2]),\n .wr_en_in (phy_ctl_wr),\n .d_in (data_offset_1),\n .wr_en_out (),\n .d_out (data_offset_1_of)\n );\n\n mig_7series_v4_0_ddr_of_pre_fifo #\n (\n .TCQ (25),\n .DEPTH (8),\n .WIDTH (6)\n )\n phy_ctl_pre_fifo_2\n (\n .clk (clk),\n .rst (rst),\n .full_in (phy_ctl_full_temp[3]),\n .wr_en_in (phy_ctl_wr),\n .d_in (data_offset_2),\n .wr_en_out (),\n .d_out (data_offset_2_of)\n );\n\n end\n endgenerate\n\n\n\n //***************************************************************************\n // Hard PHY instantiation\n //***************************************************************************\n\n assign phy_ctl_full = phy_ctl_full_temp[0];\n\n mig_7series_v4_0_ddr_mc_phy #\n (\n .BYTE_LANES_B0 (BYTE_LANES_B0),\n .BYTE_LANES_B1 (BYTE_LANES_B1),\n .BYTE_LANES_B2 (BYTE_LANES_B2),\n .BYTE_LANES_B3 (BYTE_LANES_B3),\n .BYTE_LANES_B4 (BYTE_LANES_B4),\n .DATA_CTL_B0 (DATA_CTL_B0),\n .DATA_CTL_B1 (DATA_CTL_B1),\n .DATA_CTL_B2 (DATA_CTL_B2),\n .DATA_CTL_B3 (DATA_CTL_B3),\n .DATA_CTL_B4 (DATA_CTL_B4),\n .PHY_0_BITLANES (PHY_0_BITLANES),\n .PHY_1_BITLANES (PHY_1_BITLANES),\n .PHY_2_BITLANES (PHY_2_BITLANES),\n .PHY_0_BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY),\n .PHY_1_BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY),\n .PHY_2_BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY),\n .RCLK_SELECT_BANK (CKE_ODT_RCLK_SELECT_BANK),\n .RCLK_SELECT_LANE (CKE_ODT_RCLK_SELECT_LANE),\n //.CKE_ODT_AUX (CKE_ODT_AUX),\n .GENERATE_DDR_CK_MAP (TMP_GENERATE_DDR_CK_MAP),\n .BYTELANES_DDR_CK (TMP_BYTELANES_DDR_CK),\n .NUM_DDR_CK (CK_WIDTH),\n .LP_DDR_CK_WIDTH (LP_DDR_CK_WIDTH),\n .PO_CTL_COARSE_BYPASS (\"FALSE\"),\n .PHYCTL_CMD_FIFO (\"FALSE\"),\n .PHY_CLK_RATIO (nCK_PER_CLK),\n .MASTER_PHY_CTL (MASTER_PHY_CTL),\n .PHY_FOUR_WINDOW_CLOCKS (63),\n .PHY_EVENTS_DELAY (18),\n .PHY_COUNT_EN (\"FALSE\"), //PHY_COUNT_EN\n .PHY_SYNC_MODE (\"FALSE\"),\n .SYNTHESIS ((SIM_CAL_OPTION == \"NONE\") ? \"TRUE\" : \"FALSE\"),\n .PHY_DISABLE_SEQ_MATCH (\"TRUE\"), //\"TRUE\"\n .PHY_0_GENERATE_IDELAYCTRL (\"FALSE\"),\n .PHY_0_A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV),\n .PHY_0_CMD_OFFSET (PHY_0_CMD_OFFSET), //for CKE\n .PHY_0_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0),\n .PHY_0_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1),\n .PHY_0_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2),\n .PHY_0_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3),\n .PHY_0_RD_DURATION_0 (6),\n .PHY_0_RD_DURATION_1 (6),\n .PHY_0_RD_DURATION_2 (6),\n .PHY_0_RD_DURATION_3 (6),\n .PHY_0_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0),\n .PHY_0_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1),\n .PHY_0_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2),\n .PHY_0_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3),\n .PHY_0_WR_DURATION_0 (PHY_0_WR_DURATION_0),\n .PHY_0_WR_DURATION_1 (PHY_0_WR_DURATION_1),\n .PHY_0_WR_DURATION_2 (PHY_0_WR_DURATION_2),\n .PHY_0_WR_DURATION_3 (PHY_0_WR_DURATION_3),\n .PHY_0_AO_TOGGLE ((RANKS == 1) ? 1 : 5),\n .PHY_0_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),\n .PHY_0_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),\n .PHY_0_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),\n .PHY_0_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),\n .PHY_0_A_PO_OCLKDELAY_INV (PO_OCLKDELAY_INV),\n .PHY_0_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),\n .PHY_0_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),\n .PHY_0_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),\n .PHY_0_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),\n .PHY_1_GENERATE_IDELAYCTRL (\"FALSE\"),\n //.PHY_1_GENERATE_DDR_CK (TMP_PHY_1_GENERATE_DDR_CK),\n //.PHY_1_NUM_DDR_CK (1),\n .PHY_1_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),\n .PHY_1_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),\n .PHY_1_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),\n .PHY_1_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),\n .PHY_1_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),\n .PHY_1_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),\n .PHY_1_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),\n .PHY_1_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),\n .PHY_2_GENERATE_IDELAYCTRL (\"FALSE\"),\n //.PHY_2_GENERATE_DDR_CK (TMP_PHY_2_GENERATE_DDR_CK),\n //.PHY_2_NUM_DDR_CK (1),\n .PHY_2_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),\n .PHY_2_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),\n .PHY_2_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),\n .PHY_2_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),\n .PHY_2_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),\n .PHY_2_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),\n .PHY_2_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),\n .PHY_2_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),\n .TCK (tCK),\n .PHY_0_IODELAY_GRP (IODELAY_GRP),\n .PHY_1_IODELAY_GRP (IODELAY_GRP),\n .PHY_2_IODELAY_GRP (IODELAY_GRP),\n .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),\n .BANK_TYPE (BANK_TYPE),\n .CKE_ODT_AUX (CKE_ODT_AUX),\n .PI_DIV2_INCDEC (PI_DIV2_INCDEC)\n )\n u_ddr_mc_phy\n (\n .rst (rst),\n // Don't use MC_PHY to generate DDR_RESET_N output. Instead\n // generate this output outside of MC_PHY (and synchronous to CLK)\n .ddr_rst_in_n (1'b1),\n .phy_clk (clk),\n .clk_div2 (clk_div2),\n .freq_refclk (freq_refclk),\n .mem_refclk (mem_refclk),\n // Remove later - always same connection as phy_clk port\n .mem_refclk_div4 (clk),\n .pll_lock (pll_lock),\n .auxout_clk (),\n .sync_pulse (sync_pulse),\n // IDELAYCTRL instantiated outside of mc_phy module\n .idelayctrl_refclk (),\n .phy_dout (phy_dout),\n .phy_cmd_wr_en (phy_cmd_wr_en),\n .phy_data_wr_en (phy_data_wr_en),\n .phy_rd_en (phy_rd_en),\n .phy_ctl_wd (phy_ctl_wd_temp),\n .phy_ctl_wr (phy_ctl_wr_temp),\n .if_empty_def (phy_if_empty_def),\n .if_rst (phy_if_reset),\n .phyGo ('b1),\n .aux_in_1 (aux_in_1),\n .aux_in_2 (aux_in_2),\n // No support yet for different data offsets for different I/O banks\n // (possible use in supporting wider range of skew among bytes)\n .data_offset_1 (data_offset_1_temp),\n .data_offset_2 (data_offset_2_temp),\n .cke_in (),\n .if_a_empty (),\n .if_empty (if_empty),\n .if_empty_or (),\n .if_empty_and (),\n .of_ctl_a_full (),\n // .of_data_a_full (phy_data_full),\n .of_ctl_full (phy_cmd_full),\n .of_data_full (),\n .pre_data_a_full (phy_pre_data_a_full),\n .idelay_ld (idelay_ld),\n .idelay_ce (idelay_ce),\n .idelay_inc (idelay_inc),\n .input_sink (),\n .phy_din (phy_din),\n .phy_ctl_a_full (),\n .phy_ctl_full (phy_ctl_full_temp),\n .mem_dq_out (mem_dq_out),\n .mem_dq_ts (mem_dq_ts),\n .mem_dq_in (mem_dq_in),\n .mem_dqs_out (mem_dqs_out),\n .mem_dqs_ts (mem_dqs_ts),\n .mem_dqs_in (mem_dqs_in),\n .aux_out (aux_out),\n .phy_ctl_ready (),\n .rst_out (),\n .ddr_clk (ddr_clk),\n //.rclk (),\n .mcGo (phy_mc_go),\n .phy_write_calib (phy_write_calib),\n .phy_read_calib (phy_read_calib),\n .calib_sel (calib_sel),\n .calib_in_common (calib_in_common),\n .calib_zero_inputs (calib_zero_inputs),\n .calib_zero_ctrl (calib_zero_ctrl),\n .calib_zero_lanes ('b0),\n .po_fine_enable (po_fine_enable),\n .po_coarse_enable (po_coarse_enable),\n .po_fine_inc (po_fine_inc),\n .po_coarse_inc (po_coarse_inc),\n .po_counter_load_en (po_counter_load_en),\n .po_sel_fine_oclk_delay (po_sel_fine_oclk_delay),\n .po_counter_load_val (po_counter_load_val),\n .po_counter_read_en (po_counter_read_en),\n .po_coarse_overflow (),\n .po_fine_overflow (),\n .po_counter_read_val (po_counter_read_val),\n .pi_rst_dqs_find (pi_rst_dqs_find),\n .pi_fine_enable (pi_fine_enable),\n .pi_fine_inc (pi_fine_inc),\n .pi_counter_load_en (pi_counter_load_en),\n .pi_counter_read_en (dbg_pi_counter_read_en),\n .pi_counter_load_val (pi_counter_load_val),\n .pi_fine_overflow (),\n .pi_counter_read_val (pi_counter_read_val),\n .pi_phase_locked (pi_phase_locked),\n .pi_phase_locked_all (pi_phase_locked_all),\n .pi_dqs_found (),\n .pi_dqs_found_any (pi_dqs_found),\n .pi_dqs_found_all (pi_dqs_found_all),\n .pi_dqs_found_lanes (dbg_pi_dqs_found_lanes_phy4lanes),\n // Currently not being used. May be used in future if periodic\n // reads become a requirement. This output could be used to signal\n // a catastrophic failure in read capture and the need for\n // re-calibration.\n .pi_dqs_out_of_range (pi_dqs_out_of_range)\n\n ,.ref_dll_lock (ref_dll_lock)\n ,.pi_phase_locked_lanes (dbg_pi_phase_locked_phy4lanes)\n ,.fine_delay (fine_delay_mod)\n ,.fine_delay_sel (fine_delay_sel_r)\n// ,.rst_phaser_ref (rst_phaser_ref)\n );\n\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_of_pre_fifo.v", "content": "//*****************************************************************************\n// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor : Xilinx\n// \\ \\ \\/ Version : %version\n// \\ \\ Application : MIG\n// / / Filename : ddr_of_pre_fifo.v\n// /___/ /\\ Date Last Modified : $date$\n// \\ \\ / \\ Date Created : Feb 08 2011\n// \\___\\/\\___\\\n//\n//Device : 7 Series\n//Design Name : DDR3 SDRAM\n//Purpose : Extends the depth of a PHASER OUT_FIFO up to 4 entries\n//Reference :\n//Revision History :\n//*****************************************************************************\n\n/******************************************************************************\n**$Id: ddr_of_pre_fifo.v,v 1.1 2011/06/02 08:35:07 mishra Exp $\n**$Date: 2011/06/02 08:35:07 $\n**$Author: mishra $\n**$Revision: 1.1 $\n**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_of_pre_fifo.v,v $\n******************************************************************************/\n\n`timescale 1 ps / 1 ps\n\nmodule mig_7series_v4_0_ddr_of_pre_fifo #\n (\n parameter TCQ = 100, // clk->out delay (sim only)\n parameter DEPTH = 4, // # of entries\n parameter WIDTH = 32 // data bus width\n )\n (\n input clk, // clock\n input rst, // synchronous reset\n input full_in, // FULL flag from OUT_FIFO\n input wr_en_in, // write enable from controller\n input [WIDTH-1:0] d_in, // write data from controller\n output wr_en_out, // write enable to OUT_FIFO\n output [WIDTH-1:0] d_out, // write data to OUT_FIFO\n output afull // almost full signal to controller\n );\n \n // # of bits used to represent read/write pointers\n localparam PTR_BITS \n = (DEPTH == 2) ? 1 : \n ((DEPTH == 3) || (DEPTH == 4)) ? 2 : \n (((DEPTH == 5) || (DEPTH == 6) || \n (DEPTH == 7) || (DEPTH == 8)) ? 3 : \n DEPTH == 9 ? 4 : 'bx);\n \n // Set watermark. Always give the MC 5 cycles to engage flow control.\n localparam ALMOST_FULL_VALUE = DEPTH - 5;\n\n integer i;\n \n reg [WIDTH-1:0] mem[0:DEPTH-1] ;\n reg [8:0] my_empty /* synthesis syn_maxfan = 3 */;\n reg [5:0] my_full /* synthesis syn_maxfan = 3 */;\n reg [PTR_BITS-1:0] rd_ptr /* synthesis syn_maxfan = 10 */;\n reg [PTR_BITS-1:0] wr_ptr /* synthesis syn_maxfan = 10 */;\n (* KEEP = \"TRUE\", max_fanout = 50 *) reg [PTR_BITS-1:0] rd_ptr_timing /* synthesis syn_maxfan = 10 */;\n (* KEEP = \"TRUE\", max_fanout = 50 *) reg [PTR_BITS-1:0] wr_ptr_timing /* synthesis syn_maxfan = 10 */;\n reg [PTR_BITS:0] entry_cnt;\n wire [PTR_BITS-1:0] nxt_rd_ptr;\n wire [PTR_BITS-1:0] nxt_wr_ptr;\n wire [WIDTH-1:0] mem_out;\n (* max_fanout = 50 *) wire wr_en;\n\n assign d_out = my_empty[0] ? d_in : mem_out;\n assign wr_en_out = !full_in && (!my_empty[1] || wr_en_in);\n assign wr_en = wr_en_in & ((!my_empty[3] & !full_in)|(!my_full[2] & full_in));\n\n always @ (posedge clk)\n if (wr_en)\n mem[wr_ptr] <= #TCQ d_in;\n\n assign mem_out = mem[rd_ptr];\n\n assign nxt_rd_ptr = (rd_ptr + 1'b1)%DEPTH;\n\n always @ (posedge clk)\n begin\n if (rst) begin\n rd_ptr <= 'b0;\n rd_ptr_timing <= 'b0;\n end\n else if ((!my_empty[4]) & (!full_in)) begin\n rd_ptr <= nxt_rd_ptr;\n rd_ptr_timing <= nxt_rd_ptr;\n end\n end\n\n always @ (posedge clk)\n begin\n if (rst)\n my_empty <= 9'h1ff;\n else begin\n if (my_empty[2] & !my_full[3] & full_in & wr_en_in)\n my_empty[3:0] <= 4'b0000;\n else if (!my_empty[2] & !my_full[3] & !full_in & !wr_en_in) begin\n my_empty[0] <= (nxt_rd_ptr == wr_ptr_timing);\n my_empty[1] <= (nxt_rd_ptr == wr_ptr_timing);\n my_empty[2] <= (nxt_rd_ptr == wr_ptr_timing);\n my_empty[3] <= (nxt_rd_ptr == wr_ptr_timing);\n end\n if (my_empty[8] & !my_full[5] & full_in & wr_en_in)\n my_empty[8:4] <= 5'b00000;\n else if (!my_empty[8] & !my_full[5] & !full_in & !wr_en_in) begin\n my_empty[4] <= (nxt_rd_ptr == wr_ptr_timing);\n my_empty[5] <= (nxt_rd_ptr == wr_ptr_timing);\n my_empty[6] <= (nxt_rd_ptr == wr_ptr_timing);\n my_empty[7] <= (nxt_rd_ptr == wr_ptr_timing);\n my_empty[8] <= (nxt_rd_ptr == wr_ptr_timing);\n end\n end\n end\n\n assign nxt_wr_ptr = (wr_ptr + 1'b1)%DEPTH;\n\n always @ (posedge clk)\n begin\n if (rst) begin\n wr_ptr <= 'b0;\n wr_ptr_timing <= 'b0;\n end\n else if ((wr_en_in) & ((!my_empty[5] & !full_in) | (!my_full[1] & full_in))) begin\n wr_ptr <= nxt_wr_ptr;\n wr_ptr_timing <= nxt_wr_ptr;\n end\n end\n\n always @ (posedge clk)\n begin\n if (rst)\n my_full <= 6'b000000;\n else if (!my_empty[6] & my_full[0] & !full_in & !wr_en_in)\n my_full <= 6'b000000;\n else if (!my_empty[6] & !my_full[0] & full_in & wr_en_in) begin\n my_full[0] <= (nxt_wr_ptr == rd_ptr_timing);\n my_full[1] <= (nxt_wr_ptr == rd_ptr_timing);\n my_full[2] <= (nxt_wr_ptr == rd_ptr_timing);\n my_full[3] <= (nxt_wr_ptr == rd_ptr_timing);\n my_full[4] <= (nxt_wr_ptr == rd_ptr_timing);\n my_full[5] <= (nxt_wr_ptr == rd_ptr_timing);\n end\n end\n\n always @ (posedge clk)\n begin\n if (rst)\n entry_cnt <= 'b0;\n else if (wr_en_in & full_in & !my_full[4])\n entry_cnt <= entry_cnt + 1'b1;\n else if (!wr_en_in & !full_in & !my_empty[7])\n entry_cnt <= entry_cnt - 1'b1;\n end\n\n assign afull = (entry_cnt >= ALMOST_FULL_VALUE);\n\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_4lanes.v", "content": "/**********************************************************\n-- (c) Copyright 2011 - 2014 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). A Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n\n//\n// THIS NOTICE MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.\n//\n//\n// Owner: Gary Martin\n// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/phy_4lanes.v#6 $\n// $Author: gary $\n// $DateTime: 2010/05/11 18:05:17 $\n// $Change: 490882 $\n// Description:\n// This verilog file is the parameterizable 4-byte lane phy primitive top\n// This module may be ganged to create an N-lane phy.\n//\n// History:\n// Date Engineer Description\n// 04/01/2010 G. Martin Initial Checkin.\n//\n///////////////////////////////////////////////////////////\n**********************************************************/\n\n`timescale 1ps/1ps\n\n`define PC_DATA_OFFSET_RANGE 22:17\n\nmodule mig_7series_v4_0_ddr_phy_4lanes #(\nparameter GENERATE_IDELAYCTRL = \"TRUE\",\nparameter IODELAY_GRP = \"IODELAY_MIG\",\nparameter FPGA_SPEED_GRADE = 1,\nparameter BANK_TYPE = \"HP_IO\", // # = \"HP_IO\", \"HPL_IO\", \"HR_IO\", \"HRL_IO\"\nparameter BYTELANES_DDR_CK = 24'b0010_0010_0010_0010_0010_0010,\nparameter NUM_DDR_CK = 1,\n// next three parameter fields correspond to byte lanes for lane order DCBA\nparameter BYTE_LANES = 4'b1111, // lane existence, one per lane\nparameter DATA_CTL_N = 4'b1111, // data or control, per lane\nparameter BITLANES = 48'hffff_ffff_ffff,\nparameter BITLANES_OUTONLY = 48'h0000_0000_0000,\nparameter LANE_REMAP = 16'h3210,// 4-bit index\n // used to rewire to one of four\n // input/output buss lanes\n // example: 0321 remaps lanes as:\n // D->A\n // C->D\n // B->C\n // A->B\nparameter LAST_BANK = \"FALSE\",\nparameter USE_PRE_POST_FIFO = \"FALSE\",\nparameter RCLK_SELECT_LANE = \"B\",\nparameter real TCK = 0.00,\nparameter SYNTHESIS = \"FALSE\",\nparameter PO_CTL_COARSE_BYPASS = \"FALSE\",\nparameter PO_FINE_DELAY = 0,\nparameter PI_SEL_CLK_OFFSET = 0,\n\n// phy_control paramter used in other paramsters\nparameter PC_CLK_RATIO = 4,\n\n//phaser_in parameters\nparameter A_PI_FREQ_REF_DIV = \"NONE\",\nparameter A_PI_CLKOUT_DIV = 2,\nparameter A_PI_BURST_MODE = \"TRUE\",\nparameter A_PI_OUTPUT_CLK_SRC = \"DELAYED_REF\" , //\"DELAYED_REF\",\nparameter A_PI_FINE_DELAY = 60,\nparameter A_PI_SYNC_IN_DIV_RST = \"TRUE\",\n\nparameter B_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV,\nparameter B_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV,\nparameter B_PI_BURST_MODE = A_PI_BURST_MODE,\nparameter B_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC,\nparameter B_PI_FINE_DELAY = A_PI_FINE_DELAY,\nparameter B_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST,\n\nparameter C_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV,\nparameter C_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV,\nparameter C_PI_BURST_MODE = A_PI_BURST_MODE,\nparameter C_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC,\nparameter C_PI_FINE_DELAY = 0,\nparameter C_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST,\n\nparameter D_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV,\nparameter D_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV,\nparameter D_PI_BURST_MODE = A_PI_BURST_MODE,\nparameter D_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC,\nparameter D_PI_FINE_DELAY = 0,\nparameter D_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST,\n\n//phaser_out parameters\nparameter A_PO_CLKOUT_DIV = (DATA_CTL_N[0] == 0) ? PC_CLK_RATIO : 2,\nparameter A_PO_FINE_DELAY = PO_FINE_DELAY,\nparameter A_PO_COARSE_DELAY = 0,\nparameter A_PO_OCLK_DELAY = 0,\nparameter A_PO_OCLKDELAY_INV = \"FALSE\",\nparameter A_PO_OUTPUT_CLK_SRC = \"DELAYED_REF\",\nparameter A_PO_SYNC_IN_DIV_RST = \"TRUE\",\n//parameter A_PO_SYNC_IN_DIV_RST = \"FALSE\",\n\nparameter B_PO_CLKOUT_DIV = (DATA_CTL_N[1] == 0) ? PC_CLK_RATIO : 2,\nparameter B_PO_FINE_DELAY = PO_FINE_DELAY,\nparameter B_PO_COARSE_DELAY = A_PO_COARSE_DELAY,\nparameter B_PO_OCLK_DELAY = A_PO_OCLK_DELAY,\nparameter B_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV,\nparameter B_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC,\nparameter B_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST,\n\nparameter C_PO_CLKOUT_DIV = (DATA_CTL_N[2] == 0) ? PC_CLK_RATIO : 2,\nparameter C_PO_FINE_DELAY = PO_FINE_DELAY,\nparameter C_PO_COARSE_DELAY = A_PO_COARSE_DELAY,\nparameter C_PO_OCLK_DELAY = A_PO_OCLK_DELAY,\nparameter C_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV,\nparameter C_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC,\nparameter C_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST,\n\nparameter D_PO_CLKOUT_DIV = (DATA_CTL_N[3] == 0) ? PC_CLK_RATIO : 2,\nparameter D_PO_FINE_DELAY = PO_FINE_DELAY,\nparameter D_PO_COARSE_DELAY = A_PO_COARSE_DELAY,\nparameter D_PO_OCLK_DELAY = A_PO_OCLK_DELAY,\nparameter D_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV,\nparameter D_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC,\nparameter D_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST,\n\nparameter A_IDELAYE2_IDELAY_TYPE = \"VARIABLE\",\nparameter A_IDELAYE2_IDELAY_VALUE = 00,\nparameter B_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE,\nparameter B_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE,\nparameter C_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE,\nparameter C_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE,\nparameter D_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE,\nparameter D_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE,\n\n\n// phy_control parameters\n\nparameter PC_BURST_MODE = \"TRUE\",\nparameter PC_DATA_CTL_N = DATA_CTL_N,\nparameter PC_CMD_OFFSET = 0,\nparameter PC_RD_CMD_OFFSET_0 = 0,\nparameter PC_RD_CMD_OFFSET_1 = 0,\nparameter PC_RD_CMD_OFFSET_2 = 0,\nparameter PC_RD_CMD_OFFSET_3 = 0,\nparameter PC_CO_DURATION = 1,\nparameter PC_DI_DURATION = 1,\nparameter PC_DO_DURATION = 1,\nparameter PC_RD_DURATION_0 = 0,\nparameter PC_RD_DURATION_1 = 0,\nparameter PC_RD_DURATION_2 = 0,\nparameter PC_RD_DURATION_3 = 0,\nparameter PC_WR_CMD_OFFSET_0 = 5,\nparameter PC_WR_CMD_OFFSET_1 = 5,\nparameter PC_WR_CMD_OFFSET_2 = 5,\nparameter PC_WR_CMD_OFFSET_3 = 5,\nparameter PC_WR_DURATION_0 = 6,\nparameter PC_WR_DURATION_1 = 6,\nparameter PC_WR_DURATION_2 = 6,\nparameter PC_WR_DURATION_3 = 6,\nparameter PC_AO_WRLVL_EN = 0,\nparameter PC_AO_TOGGLE = 4'b0101, // odd bits are toggle (CKE)\nparameter PC_FOUR_WINDOW_CLOCKS = 63,\nparameter PC_EVENTS_DELAY = 18,\nparameter PC_PHY_COUNT_EN = \"TRUE\",\nparameter PC_SYNC_MODE = \"TRUE\",\nparameter PC_DISABLE_SEQ_MATCH = \"TRUE\",\nparameter PC_MULTI_REGION = \"FALSE\",\n\n// io fifo parameters\n\nparameter A_OF_ARRAY_MODE = (DATA_CTL_N[0] == 1) ? \"ARRAY_MODE_8_X_4\" : \"ARRAY_MODE_4_X_4\",\nparameter B_OF_ARRAY_MODE = (DATA_CTL_N[1] == 1) ? \"ARRAY_MODE_8_X_4\" : \"ARRAY_MODE_4_X_4\",\nparameter C_OF_ARRAY_MODE = (DATA_CTL_N[2] == 1) ? \"ARRAY_MODE_8_X_4\" : \"ARRAY_MODE_4_X_4\",\nparameter D_OF_ARRAY_MODE = (DATA_CTL_N[3] == 1) ? \"ARRAY_MODE_8_X_4\" : \"ARRAY_MODE_4_X_4\",\nparameter OF_ALMOST_EMPTY_VALUE = 1,\nparameter OF_ALMOST_FULL_VALUE = 1,\nparameter OF_OUTPUT_DISABLE = \"TRUE\",\nparameter OF_SYNCHRONOUS_MODE = PC_SYNC_MODE,\n\nparameter A_OS_DATA_RATE = \"DDR\",\nparameter A_OS_DATA_WIDTH = 4,\nparameter B_OS_DATA_RATE = A_OS_DATA_RATE,\nparameter B_OS_DATA_WIDTH = A_OS_DATA_WIDTH,\nparameter C_OS_DATA_RATE = A_OS_DATA_RATE,\nparameter C_OS_DATA_WIDTH = A_OS_DATA_WIDTH,\nparameter D_OS_DATA_RATE = A_OS_DATA_RATE,\nparameter D_OS_DATA_WIDTH = A_OS_DATA_WIDTH,\n\n\nparameter A_IF_ARRAY_MODE = \"ARRAY_MODE_4_X_8\",\nparameter B_IF_ARRAY_MODE = A_IF_ARRAY_MODE,\nparameter C_IF_ARRAY_MODE = A_IF_ARRAY_MODE,\nparameter D_IF_ARRAY_MODE = A_IF_ARRAY_MODE,\nparameter IF_ALMOST_EMPTY_VALUE = 1,\nparameter IF_ALMOST_FULL_VALUE = 1,\nparameter IF_SYNCHRONOUS_MODE = PC_SYNC_MODE,\n\n\n// this is used locally, not for external pushdown\n// NOTE: the 0+ is needed in each to coerce to integer for addition.\n// otherwise 4x 1'b values are added producing a 1'b value.\nparameter HIGHEST_LANE = LAST_BANK == \"FALSE\" ? 4 : (BYTE_LANES[3] ? 4 : BYTE_LANES[2] ? 3 : BYTE_LANES[1] ? 2 : 1),\nparameter N_CTL_LANES = ((0+(!DATA_CTL_N[0]) & BYTE_LANES[0]) + (0+(!DATA_CTL_N[1]) & BYTE_LANES[1]) + (0+(!DATA_CTL_N[2]) & BYTE_LANES[2]) + (0+(!DATA_CTL_N[3]) & BYTE_LANES[3])),\n\nparameter N_BYTE_LANES = (0+BYTE_LANES[0]) + (0+BYTE_LANES[1]) + (0+BYTE_LANES[2]) + (0+BYTE_LANES[3]),\n\nparameter N_DATA_LANES = N_BYTE_LANES - N_CTL_LANES,\n// assume odt per rank + any declared cke's\nparameter AUXOUT_WIDTH = 4,\nparameter LP_DDR_CK_WIDTH = 2\n,parameter CKE_ODT_AUX = \"FALSE\"\n,parameter PI_DIV2_INCDEC = \"FALSE\"\n)\n(\n\n//`include \"phy.vh\"\n\n input rst,\n input phy_clk,\n input clk_div2,\n input phy_ctl_clk,\n input freq_refclk,\n input mem_refclk,\n input mem_refclk_div4,\n input pll_lock,\n input sync_pulse,\n input idelayctrl_refclk,\n input [HIGHEST_LANE*80-1:0] phy_dout,\n input phy_cmd_wr_en,\n input phy_data_wr_en,\n input phy_rd_en,\n input phy_ctl_mstr_empty,\n input [31:0] phy_ctl_wd,\n input [`PC_DATA_OFFSET_RANGE] data_offset,\n input phy_ctl_wr,\n input if_empty_def,\n input phyGo,\n input input_sink,\n\n output [(LP_DDR_CK_WIDTH*24)-1:0] ddr_clk, // to memory\n output rclk,\n output if_a_empty,\n output if_empty,\n output byte_rd_en,\n output if_empty_or,\n output if_empty_and,\n output of_ctl_a_full,\n output of_data_a_full,\n output of_ctl_full,\n output of_data_full,\n output pre_data_a_full,\n output [HIGHEST_LANE*80-1:0]phy_din, // assume input bus same size as output bus\n output phy_ctl_empty,\n output phy_ctl_a_full,\n output phy_ctl_full,\n output [HIGHEST_LANE*12-1:0]mem_dq_out,\n output [HIGHEST_LANE*12-1:0]mem_dq_ts,\n input [HIGHEST_LANE*10-1:0]mem_dq_in,\n output [HIGHEST_LANE-1:0] mem_dqs_out,\n output [HIGHEST_LANE-1:0] mem_dqs_ts,\n input [HIGHEST_LANE-1:0] mem_dqs_in,\n input [1:0] byte_rd_en_oth_banks,\n\n output [AUXOUT_WIDTH-1:0] aux_out,\n output reg rst_out = 0,\n output reg mcGo=0,\n output phy_ctl_ready,\n output ref_dll_lock,\n input if_rst,\n input phy_read_calib,\n input phy_write_calib,\n input idelay_inc,\n input idelay_ce,\n input idelay_ld,\n input [2:0] calib_sel,\n input calib_zero_ctrl,\n input [HIGHEST_LANE-1:0] calib_zero_lanes,\n input calib_in_common,\n input po_fine_enable,\n input po_coarse_enable,\n input po_fine_inc,\n input po_coarse_inc,\n input po_counter_load_en,\n input po_counter_read_en,\n input [8:0] po_counter_load_val,\n input po_sel_fine_oclk_delay,\n output reg po_coarse_overflow,\n output reg po_fine_overflow,\n output reg [8:0] po_counter_read_val,\n\n\n\n input pi_rst_dqs_find,\n input pi_fine_enable,\n input pi_fine_inc,\n input pi_counter_load_en,\n input pi_counter_read_en,\n input [5:0] pi_counter_load_val,\n output reg pi_fine_overflow,\n output reg [5:0] pi_counter_read_val,\n\n output reg pi_dqs_found,\n output pi_dqs_found_all,\n output pi_dqs_found_any,\n output [HIGHEST_LANE-1:0] pi_phase_locked_lanes,\n output [HIGHEST_LANE-1:0] pi_dqs_found_lanes,\n output reg pi_dqs_out_of_range,\n output reg pi_phase_locked,\n output pi_phase_locked_all,\n input [29:0] fine_delay,\n input fine_delay_sel\n);\n\nlocalparam DATA_CTL_A = (~DATA_CTL_N[0]);\nlocalparam DATA_CTL_B = (~DATA_CTL_N[1]);\nlocalparam DATA_CTL_C = (~DATA_CTL_N[2]);\nlocalparam DATA_CTL_D = (~DATA_CTL_N[3]);\nlocalparam PRESENT_CTL_A = BYTE_LANES[0] && ! DATA_CTL_N[0];\nlocalparam PRESENT_CTL_B = BYTE_LANES[1] && ! DATA_CTL_N[1];\nlocalparam PRESENT_CTL_C = BYTE_LANES[2] && ! DATA_CTL_N[2];\nlocalparam PRESENT_CTL_D = BYTE_LANES[3] && ! DATA_CTL_N[3];\nlocalparam PRESENT_DATA_A = BYTE_LANES[0] && DATA_CTL_N[0];\nlocalparam PRESENT_DATA_B = BYTE_LANES[1] && DATA_CTL_N[1];\nlocalparam PRESENT_DATA_C = BYTE_LANES[2] && DATA_CTL_N[2];\nlocalparam PRESENT_DATA_D = BYTE_LANES[3] && DATA_CTL_N[3];\nlocalparam PC_DATA_CTL_A = (DATA_CTL_A) ? \"FALSE\" : \"TRUE\";\nlocalparam PC_DATA_CTL_B = (DATA_CTL_B) ? \"FALSE\" : \"TRUE\";\nlocalparam PC_DATA_CTL_C = (DATA_CTL_C) ? \"FALSE\" : \"TRUE\";\nlocalparam PC_DATA_CTL_D = (DATA_CTL_D) ? \"FALSE\" : \"TRUE\";\nlocalparam A_PO_COARSE_BYPASS = (DATA_CTL_A) ? PO_CTL_COARSE_BYPASS : \"FALSE\";\nlocalparam B_PO_COARSE_BYPASS = (DATA_CTL_B) ? PO_CTL_COARSE_BYPASS : \"FALSE\";\nlocalparam C_PO_COARSE_BYPASS = (DATA_CTL_C) ? PO_CTL_COARSE_BYPASS : \"FALSE\";\nlocalparam D_PO_COARSE_BYPASS = (DATA_CTL_D) ? PO_CTL_COARSE_BYPASS : \"FALSE\";\n\nlocalparam IO_A_START = 41;\nlocalparam IO_A_END = 40;\nlocalparam IO_B_START = 43;\nlocalparam IO_B_END = 42;\nlocalparam IO_C_START = 45;\nlocalparam IO_C_END = 44;\nlocalparam IO_D_START = 47;\nlocalparam IO_D_END = 46;\nlocalparam IO_A_X_START = (HIGHEST_LANE * 10) + 1;\nlocalparam IO_A_X_END = (IO_A_X_START-1);\nlocalparam IO_B_X_START = (IO_A_X_START + 2);\nlocalparam IO_B_X_END = (IO_B_X_START -1);\nlocalparam IO_C_X_START = (IO_B_X_START + 2);\nlocalparam IO_C_X_END = (IO_C_X_START -1);\nlocalparam IO_D_X_START = (IO_C_X_START + 2);\nlocalparam IO_D_X_END = (IO_D_X_START -1);\n\nlocalparam MSB_BURST_PEND_PO = 3;\nlocalparam MSB_BURST_PEND_PI = 7;\nlocalparam MSB_RANK_SEL_I = MSB_BURST_PEND_PI + 8;\nlocalparam PHASER_CTL_BUS_WIDTH = MSB_RANK_SEL_I + 1;\n\nwire [1:0] oserdes_dqs;\nwire [1:0] oserdes_dqs_ts;\nwire [1:0] oserdes_dq_ts;\n\n\nwire [PHASER_CTL_BUS_WIDTH-1:0] phaser_ctl_bus;\nwire [7:0] in_rank;\nwire [11:0] IO_A;\nwire [11:0] IO_B;\nwire [11:0] IO_C;\nwire [11:0] IO_D;\n\nwire [319:0] phy_din_remap;\n\nreg A_po_counter_read_en;\nwire [8:0] A_po_counter_read_val;\nreg A_pi_counter_read_en;\nwire [5:0] A_pi_counter_read_val;\nwire A_pi_fine_overflow;\nwire A_po_coarse_overflow;\nwire A_po_fine_overflow;\nwire A_pi_dqs_found;\nwire A_pi_dqs_out_of_range;\nwire A_pi_phase_locked;\nwire A_pi_iserdes_rst;\nreg A_pi_fine_enable;\nreg A_pi_fine_inc;\nreg A_pi_counter_load_en;\nreg [5:0] A_pi_counter_load_val;\nreg A_pi_rst_dqs_find;\n\n\nreg A_po_fine_enable;\nreg A_po_coarse_enable;\n reg A_po_fine_inc /* synthesis syn_maxfan = 3 */;\nreg A_po_sel_fine_oclk_delay;\nreg A_po_coarse_inc;\nreg A_po_counter_load_en;\nreg [8:0] A_po_counter_load_val;\nwire A_rclk;\nreg A_idelay_ce;\nreg A_idelay_ld;\nreg [29:0] A_fine_delay;\nreg A_fine_delay_sel;\n\nreg B_po_counter_read_en;\nwire [8:0] B_po_counter_read_val;\nreg B_pi_counter_read_en;\nwire [5:0] B_pi_counter_read_val;\nwire B_pi_fine_overflow;\nwire B_po_coarse_overflow;\nwire B_po_fine_overflow;\nwire B_pi_phase_locked;\nwire B_pi_iserdes_rst;\nwire B_pi_dqs_found;\nwire B_pi_dqs_out_of_range;\nreg B_pi_fine_enable;\nreg B_pi_fine_inc;\nreg B_pi_counter_load_en;\nreg [5:0] B_pi_counter_load_val;\nreg B_pi_rst_dqs_find;\n\n\nreg B_po_fine_enable;\nreg B_po_coarse_enable;\n reg B_po_fine_inc /* synthesis syn_maxfan = 3 */;\nreg B_po_coarse_inc;\nreg B_po_sel_fine_oclk_delay;\nreg B_po_counter_load_en;\nreg [8:0] B_po_counter_load_val;\nwire B_rclk;\nreg B_idelay_ce;\nreg B_idelay_ld;\nreg [29:0] B_fine_delay;\nreg B_fine_delay_sel;\n\n\nreg C_pi_fine_inc;\nreg D_pi_fine_inc;\nreg C_pi_fine_enable;\nreg D_pi_fine_enable;\nreg C_po_counter_load_en;\nreg D_po_counter_load_en;\nreg C_po_coarse_inc;\nreg D_po_coarse_inc;\n reg C_po_fine_inc /* synthesis syn_maxfan = 3 */;\n reg D_po_fine_inc /* synthesis syn_maxfan = 3 */;\nreg C_po_sel_fine_oclk_delay;\nreg D_po_sel_fine_oclk_delay;\nreg [5:0] C_pi_counter_load_val;\nreg [5:0] D_pi_counter_load_val;\nreg [8:0] C_po_counter_load_val;\nreg [8:0] D_po_counter_load_val;\nreg C_po_coarse_enable;\nreg D_po_coarse_enable;\nreg C_po_fine_enable;\nreg D_po_fine_enable;\nwire C_po_coarse_overflow;\nwire D_po_coarse_overflow;\nwire C_po_fine_overflow;\nwire D_po_fine_overflow;\nwire [8:0] C_po_counter_read_val;\nwire [8:0] D_po_counter_read_val;\nreg C_po_counter_read_en;\nreg D_po_counter_read_en;\nwire C_pi_dqs_found;\nwire D_pi_dqs_found;\nwire C_pi_fine_overflow;\nwire D_pi_fine_overflow;\nreg C_pi_counter_read_en;\nreg D_pi_counter_read_en;\nreg C_pi_counter_load_en;\nreg D_pi_counter_load_en;\nwire C_pi_phase_locked;\nwire C_pi_iserdes_rst;\nwire D_pi_phase_locked;\nwire D_pi_iserdes_rst;\nwire C_pi_dqs_out_of_range;\nwire D_pi_dqs_out_of_range;\nwire [5:0] C_pi_counter_read_val;\nwire [5:0] D_pi_counter_read_val;\nwire C_rclk;\nwire D_rclk;\nreg C_idelay_ce;\nreg D_idelay_ce;\nreg C_idelay_ld;\nreg D_idelay_ld;\nreg C_pi_rst_dqs_find;\nreg D_pi_rst_dqs_find;\nreg [29:0] C_fine_delay;\nreg [29:0] D_fine_delay;\nreg C_fine_delay_sel;\nreg D_fine_delay_sel;\n\nwire pi_iserdes_rst;\n\nwire A_if_empty;\nwire B_if_empty;\nwire C_if_empty;\nwire D_if_empty;\nwire A_byte_rd_en;\nwire B_byte_rd_en;\nwire C_byte_rd_en;\nwire D_byte_rd_en;\nwire A_if_a_empty;\nwire B_if_a_empty;\nwire C_if_a_empty;\nwire D_if_a_empty;\n//wire A_if_full;\n//wire B_if_full;\n//wire C_if_full;\n//wire D_if_full;\n//wire A_of_empty;\n//wire B_of_empty;\n//wire C_of_empty;\n//wire D_of_empty;\nwire A_of_full;\nwire B_of_full;\nwire C_of_full;\nwire D_of_full;\nwire A_of_ctl_full;\nwire B_of_ctl_full;\nwire C_of_ctl_full;\nwire D_of_ctl_full;\nwire A_of_data_full;\nwire B_of_data_full;\nwire C_of_data_full;\nwire D_of_data_full;\nwire A_of_a_full;\nwire B_of_a_full;\nwire C_of_a_full;\nwire D_of_a_full;\nwire A_pre_fifo_a_full;\nwire B_pre_fifo_a_full;\nwire C_pre_fifo_a_full;\nwire D_pre_fifo_a_full;\nwire A_of_ctl_a_full;\nwire B_of_ctl_a_full;\nwire C_of_ctl_a_full;\nwire D_of_ctl_a_full;\nwire A_of_data_a_full;\nwire B_of_data_a_full;\nwire C_of_data_a_full;\nwire D_of_data_a_full;\nwire A_pre_data_a_full;\nwire B_pre_data_a_full;\nwire C_pre_data_a_full;\nwire D_pre_data_a_full;\nwire [LP_DDR_CK_WIDTH*6-1:0] A_ddr_clk; // for generation\nwire [LP_DDR_CK_WIDTH*6-1:0] B_ddr_clk; //\nwire [LP_DDR_CK_WIDTH*6-1:0] C_ddr_clk; //\nwire [LP_DDR_CK_WIDTH*6-1:0] D_ddr_clk; //\n\nwire [3:0] dummy_data;\n\nwire [31:0] _phy_ctl_wd;\n\nwire [1:0] phy_encalib;\n\nassign pi_dqs_found_all =\n (! PRESENT_DATA_A | A_pi_dqs_found) &\n (! PRESENT_DATA_B | B_pi_dqs_found) &\n (! PRESENT_DATA_C | C_pi_dqs_found) &\n (! PRESENT_DATA_D | D_pi_dqs_found) ;\n\nassign pi_dqs_found_any =\n ( PRESENT_DATA_A & A_pi_dqs_found) |\n ( PRESENT_DATA_B & B_pi_dqs_found) |\n ( PRESENT_DATA_C & C_pi_dqs_found) |\n ( PRESENT_DATA_D & D_pi_dqs_found) ;\n\nassign pi_phase_locked_all =\n (! PRESENT_DATA_A | A_pi_phase_locked) &\n (! PRESENT_DATA_B | B_pi_phase_locked) &\n (! PRESENT_DATA_C | C_pi_phase_locked) &\n (! PRESENT_DATA_D | D_pi_phase_locked);\n\nwire dangling_inputs = (& dummy_data) & input_sink & 1'b0; // this reduces all constant 0 values to 1 signal\n // which is combined into another signals such that\n // the other signal isn't changed. The purpose\n // is to fake the tools into ignoring dangling inputs.\n // Because it is anded with 1'b0, the contributing signals\n // are folded as constants or trimmed.\n\n\nassign if_empty = !if_empty_def ? (A_if_empty | B_if_empty | C_if_empty | D_if_empty) : (A_if_empty & B_if_empty & C_if_empty & D_if_empty);\nassign byte_rd_en = !if_empty_def ? (A_byte_rd_en & B_byte_rd_en & C_byte_rd_en & D_byte_rd_en) :\n (A_byte_rd_en | B_byte_rd_en | C_byte_rd_en | D_byte_rd_en);\nassign if_empty_or = (A_if_empty | B_if_empty | C_if_empty | D_if_empty);\nassign if_empty_and = (A_if_empty & B_if_empty & C_if_empty & D_if_empty);\nassign if_a_empty = A_if_a_empty | B_if_a_empty | C_if_a_empty | D_if_a_empty;\n//assign if_full = A_if_full | B_if_full | C_if_full | D_if_full ;\n//assign of_empty = A_of_empty & B_of_empty & C_of_empty & D_of_empty;\nassign of_ctl_full = A_of_ctl_full | B_of_ctl_full | C_of_ctl_full | D_of_ctl_full ;\nassign of_data_full = A_of_data_full | B_of_data_full | C_of_data_full | D_of_data_full ;\nassign of_ctl_a_full = A_of_ctl_a_full | B_of_ctl_a_full | C_of_ctl_a_full | D_of_ctl_a_full ;\nassign of_data_a_full = A_of_data_a_full | B_of_data_a_full | C_of_data_a_full | D_of_data_a_full | dangling_inputs ;\nassign pre_data_a_full = A_pre_data_a_full | B_pre_data_a_full | C_pre_data_a_full | D_pre_data_a_full;\n\n\nfunction [79:0] part_select_80;\ninput [319:0] vector;\ninput [1:0] select;\nbegin\n case (select)\n 2'b00 : part_select_80[79:0] = vector[1*80-1:0*80];\n 2'b01 : part_select_80[79:0] = vector[2*80-1:1*80];\n 2'b10 : part_select_80[79:0] = vector[3*80-1:2*80];\n 2'b11 : part_select_80[79:0] = vector[4*80-1:3*80];\n endcase\nend\nendfunction\n\nwire [319:0] phy_dout_remap;\n\nreg rst_out_trig = 1'b0;\nreg [31:0] rclk_delay;\nreg rst_edge1 = 1'b0;\nreg rst_edge2 = 1'b0;\nreg rst_edge3 = 1'b0;\nreg rst_edge_detect = 1'b0;\nwire rclk_;\nreg rst_out_start = 1'b0 ;\nreg rst_primitives=0;\nreg A_rst_primitives=0;\nreg B_rst_primitives=0;\nreg C_rst_primitives=0;\nreg D_rst_primitives=0;\n\n`ifdef USE_PHY_CONTROL_TEST\n wire [15:0] test_output;\n wire [15:0] test_input;\n wire [2:0] test_select=0;\n wire scan_enable = 0;\n`endif\n\ngenerate\n\ngenvar i;\n\nif (RCLK_SELECT_LANE == \"A\") begin\n assign rclk_ = A_rclk;\n assign pi_iserdes_rst = A_pi_iserdes_rst;\n end\nelse if (RCLK_SELECT_LANE == \"B\") begin\n assign rclk_ = B_rclk;\n assign pi_iserdes_rst = B_pi_iserdes_rst;\n end\nelse if (RCLK_SELECT_LANE == \"C\") begin\n assign rclk_ = C_rclk;\n assign pi_iserdes_rst = C_pi_iserdes_rst;\n end\nelse if (RCLK_SELECT_LANE == \"D\") begin\n assign rclk_ = D_rclk;\n assign pi_iserdes_rst = D_pi_iserdes_rst;\n end\nelse begin\n assign rclk_ = B_rclk; // default\n end\n\nendgenerate\n\nassign ddr_clk[LP_DDR_CK_WIDTH*6-1:0] = A_ddr_clk;\nassign ddr_clk[LP_DDR_CK_WIDTH*12-1:LP_DDR_CK_WIDTH*6] = B_ddr_clk;\nassign ddr_clk[LP_DDR_CK_WIDTH*18-1:LP_DDR_CK_WIDTH*12] = C_ddr_clk;\nassign ddr_clk[LP_DDR_CK_WIDTH*24-1:LP_DDR_CK_WIDTH*18] = D_ddr_clk;\n\nassign pi_phase_locked_lanes =\n {(! PRESENT_DATA_D[0] | D_pi_phase_locked),\n (! PRESENT_DATA_C[0] | C_pi_phase_locked) ,\n (! PRESENT_DATA_B[0] | B_pi_phase_locked) ,\n (! PRESENT_DATA_A[0] | A_pi_phase_locked)};\n\nassign pi_dqs_found_lanes = {D_pi_dqs_found, C_pi_dqs_found, B_pi_dqs_found, A_pi_dqs_found};\n\n// this block scrubs X from rclk_delay[11]\nreg rclk_delay_11;\nalways @(rclk_delay[11]) begin : rclk_delay_11_blk\n if ( rclk_delay[11])\n rclk_delay_11 = 1;\n else\n rclk_delay_11 = 0;\nend\n\nalways @(posedge phy_clk or posedge rst ) begin\n// scrub 4-state values from rclk_delay[11]\n if ( rst) begin\n rst_out <= #1 0;\n end\n else begin\n if ( rclk_delay_11)\n rst_out <= #1 1;\n end\nend\n\nalways @(posedge phy_clk ) begin\n // phy_ctl_ready drives reset of the system\n rst_primitives <= !phy_ctl_ready ;\n A_rst_primitives <= rst_primitives ;\n B_rst_primitives <= rst_primitives ;\n C_rst_primitives <= rst_primitives ;\n D_rst_primitives <= rst_primitives ;\n\n rclk_delay <= #1 (rclk_delay << 1) | (!rst_primitives && phyGo);\n mcGo <= #1 rst_out ;\n\nend\n\n//reset synchronized to clk_div2\n (* ASYNC_REG = \"TRUE\" *) reg A_pi_rst_div2;\n (* ASYNC_REG = \"TRUE\" *) reg B_pi_rst_div2;\n (* ASYNC_REG = \"TRUE\" *) reg C_pi_rst_div2;\n (* ASYNC_REG = \"TRUE\" *) reg D_pi_rst_div2;\ngenerate\n if (PI_DIV2_INCDEC == \"TRUE\") begin: phaser_in_div2\n (* ASYNC_REG = \"TRUE\" *) reg pi_rst_div2r1;\n (* ASYNC_REG = \"TRUE\" *) reg pi_rst_div2r2;\n\n always @(posedge clk_div2) begin\n pi_rst_div2r1 <= rst_primitives;\n pi_rst_div2r2 <= pi_rst_div2r1;\n A_pi_rst_div2 <= pi_rst_div2r2;\n B_pi_rst_div2 <= pi_rst_div2r2;\n C_pi_rst_div2 <= pi_rst_div2r2;\n D_pi_rst_div2 <= pi_rst_div2r2;\n end\n end else begin: phaser_in_div4\n always @ (*) begin\n A_pi_rst_div2 <= 1'b0;\n B_pi_rst_div2 <= 1'b0;\n C_pi_rst_div2 <= 1'b0;\n D_pi_rst_div2 <= 1'b0;\n end\n end\nendgenerate\n\ngenerate\n\n if (BYTE_LANES[0]) begin\n assign dummy_data[0] = 0;\n end\n else begin\n assign dummy_data[0] = &phy_dout_remap[1*80-1:0*80];\n end\n if (BYTE_LANES[1]) begin\n assign dummy_data[1] = 0;\n end\n else begin\n assign dummy_data[1] = &phy_dout_remap[2*80-1:1*80];\n end\n if (BYTE_LANES[2]) begin\n assign dummy_data[2] = 0;\n end\n else begin\n assign dummy_data[2] = &phy_dout_remap[3*80-1:2*80];\n end\n if (BYTE_LANES[3]) begin\n assign dummy_data[3] = 0;\n end\n else begin\n assign dummy_data[3] = &phy_dout_remap[4*80-1:3*80];\n end\n\n if (PRESENT_DATA_A) begin\n assign A_of_data_full = A_of_full;\n assign A_of_ctl_full = 0;\n assign A_of_data_a_full = A_of_a_full;\n assign A_of_ctl_a_full = 0;\n assign A_pre_data_a_full = A_pre_fifo_a_full;\n end\n else begin\n assign A_of_ctl_full = A_of_full;\n assign A_of_data_full = 0;\n assign A_of_ctl_a_full = A_of_a_full;\n assign A_of_data_a_full = 0;\n assign A_pre_data_a_full = 0;\n end\n if (PRESENT_DATA_B) begin\n assign B_of_data_full = B_of_full;\n assign B_of_ctl_full = 0;\n assign B_of_data_a_full = B_of_a_full;\n assign B_of_ctl_a_full = 0;\n assign B_pre_data_a_full = B_pre_fifo_a_full;\n end\n else begin\n assign B_of_ctl_full = B_of_full;\n assign B_of_data_full = 0;\n assign B_of_ctl_a_full = B_of_a_full;\n assign B_of_data_a_full = 0;\n assign B_pre_data_a_full = 0;\n end\n if (PRESENT_DATA_C) begin\n assign C_of_data_full = C_of_full;\n assign C_of_ctl_full = 0;\n assign C_of_data_a_full = C_of_a_full;\n assign C_of_ctl_a_full = 0;\n assign C_pre_data_a_full = C_pre_fifo_a_full;\n end\n else begin\n assign C_of_ctl_full = C_of_full;\n assign C_of_data_full = 0;\n assign C_of_ctl_a_full = C_of_a_full;\n assign C_of_data_a_full = 0;\n assign C_pre_data_a_full = 0;\n end\n if (PRESENT_DATA_D) begin\n assign D_of_data_full = D_of_full;\n assign D_of_ctl_full = 0;\n assign D_of_data_a_full = D_of_a_full;\n assign D_of_ctl_a_full = 0;\n assign D_pre_data_a_full = D_pre_fifo_a_full;\n end\n else begin\n assign D_of_ctl_full = D_of_full;\n assign D_of_data_full = 0;\n assign D_of_ctl_a_full = D_of_a_full;\n assign D_of_data_a_full = 0;\n assign D_pre_data_a_full = 0;\n end\n// byte lane must exist and be data lane.\n if (PRESENT_DATA_A )\n case ( LANE_REMAP[1:0] )\n 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[79:0];\n 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[79:0];\n 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[79:0];\n 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[79:0];\n endcase\n else\n case ( LANE_REMAP[1:0] )\n 2'b00 : assign phy_din[1*80-1:0] = 80'h0;\n 2'b01 : assign phy_din[2*80-1:80] = 80'h0;\n 2'b10 : assign phy_din[3*80-1:160] = 80'h0;\n 2'b11 : assign phy_din[4*80-1:240] = 80'h0;\n endcase\n\n if (PRESENT_DATA_B )\n case ( LANE_REMAP[5:4] )\n 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[159:80];\n 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[159:80];\n 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[159:80];\n 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[159:80];\n endcase\n else\n if (HIGHEST_LANE > 1)\n case ( LANE_REMAP[5:4] )\n 2'b00 : assign phy_din[1*80-1:0] = 80'h0;\n 2'b01 : assign phy_din[2*80-1:80] = 80'h0;\n 2'b10 : assign phy_din[3*80-1:160] = 80'h0;\n 2'b11 : assign phy_din[4*80-1:240] = 80'h0;\n endcase\n\n if (PRESENT_DATA_C)\n case ( LANE_REMAP[9:8] )\n 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[239:160];\n 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[239:160];\n 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[239:160];\n 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[239:160];\n endcase\n else\n if (HIGHEST_LANE > 2)\n case ( LANE_REMAP[9:8] )\n 2'b00 : assign phy_din[1*80-1:0] = 80'h0;\n 2'b01 : assign phy_din[2*80-1:80] = 80'h0;\n 2'b10 : assign phy_din[3*80-1:160] = 80'h0;\n 2'b11 : assign phy_din[4*80-1:240] = 80'h0;\n endcase\n\n if (PRESENT_DATA_D )\n case ( LANE_REMAP[13:12] )\n 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[319:240];\n 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[319:240];\n 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[319:240];\n 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[319:240];\n endcase\n else\n if (HIGHEST_LANE > 3)\n case ( LANE_REMAP[13:12] )\n 2'b00 : assign phy_din[1*80-1:0] = 80'h0;\n 2'b01 : assign phy_din[2*80-1:80] = 80'h0;\n 2'b10 : assign phy_din[3*80-1:160] = 80'h0;\n 2'b11 : assign phy_din[4*80-1:240] = 80'h0;\n endcase\n\nif (HIGHEST_LANE > 1)\n assign _phy_ctl_wd = {phy_ctl_wd[31:23], data_offset, phy_ctl_wd[16:0]};\nif (HIGHEST_LANE == 1)\n assign _phy_ctl_wd = phy_ctl_wd;\n\n\n//BUFR #(.BUFR_DIVIDE (\"1\")) rclk_buf(.I(rclk_), .O(rclk), .CE (1'b1), .CLR (pi_iserdes_rst));\nBUFIO rclk_buf(.I(rclk_), .O(rclk) );\n\nif ( BYTE_LANES[0] ) begin : ddr_byte_lane_A\n\n assign phy_dout_remap[79:0] = part_select_80(phy_dout, (LANE_REMAP[1:0]));\n\n mig_7series_v4_0_ddr_byte_lane #\n (\n .ABCD (\"A\"),\n .PO_DATA_CTL (PC_DATA_CTL_N[0] ? \"TRUE\" : \"FALSE\"),\n .BITLANES (BITLANES[11:0]),\n .BITLANES_OUTONLY (BITLANES_OUTONLY[11:0]),\n .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),\n .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),\n .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE),\n //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE),\n //.OF_ARRAY_MODE (A_OF_ARRAY_MODE),\n //.IF_ARRAY_MODE (IF_ARRAY_MODE),\n .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE),\n .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE),\n .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE),\n .IODELAY_GRP (IODELAY_GRP),\n .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),\n .BANK_TYPE (BANK_TYPE),\n .BYTELANES_DDR_CK (BYTELANES_DDR_CK),\n .RCLK_SELECT_LANE (RCLK_SELECT_LANE),\n .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),\n .SYNTHESIS (SYNTHESIS),\n .TCK (TCK),\n .PC_CLK_RATIO (PC_CLK_RATIO),\n .PI_BURST_MODE (A_PI_BURST_MODE),\n .PI_CLKOUT_DIV (A_PI_CLKOUT_DIV),\n .PI_FREQ_REF_DIV (A_PI_FREQ_REF_DIV),\n .PI_FINE_DELAY (A_PI_FINE_DELAY),\n .PI_OUTPUT_CLK_SRC (A_PI_OUTPUT_CLK_SRC),\n .PI_SYNC_IN_DIV_RST (A_PI_SYNC_IN_DIV_RST),\n .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),\n .PO_CLKOUT_DIV (A_PO_CLKOUT_DIV),\n .PO_FINE_DELAY (A_PO_FINE_DELAY),\n .PO_COARSE_BYPASS (A_PO_COARSE_BYPASS),\n .PO_COARSE_DELAY (A_PO_COARSE_DELAY),\n .PO_OCLK_DELAY (A_PO_OCLK_DELAY),\n .PO_OCLKDELAY_INV (A_PO_OCLKDELAY_INV),\n .PO_OUTPUT_CLK_SRC (A_PO_OUTPUT_CLK_SRC),\n .PO_SYNC_IN_DIV_RST (A_PO_SYNC_IN_DIV_RST),\n .OSERDES_DATA_RATE (A_OS_DATA_RATE),\n .OSERDES_DATA_WIDTH (A_OS_DATA_WIDTH),\n .IDELAYE2_IDELAY_TYPE (A_IDELAYE2_IDELAY_TYPE),\n .IDELAYE2_IDELAY_VALUE (A_IDELAYE2_IDELAY_VALUE)\n ,.CKE_ODT_AUX (CKE_ODT_AUX)\n ,.PI_DIV2_INCDEC (PI_DIV2_INCDEC)\n )\n ddr_byte_lane_A(\n .mem_dq_out (mem_dq_out[11:0]),\n .mem_dq_ts (mem_dq_ts[11:0]),\n .mem_dq_in (mem_dq_in[9:0]),\n .mem_dqs_out (mem_dqs_out[0]),\n .mem_dqs_ts (mem_dqs_ts[0]),\n .mem_dqs_in (mem_dqs_in[0]),\n .rst (A_rst_primitives),\n .rst_pi_div2 (A_pi_rst_div2),\n .phy_clk (phy_clk),\n .clk_div2 (clk_div2),\n .freq_refclk (freq_refclk),\n .mem_refclk (mem_refclk),\n .idelayctrl_refclk (idelayctrl_refclk),\n .sync_pulse (sync_pulse),\n .ddr_ck_out (A_ddr_clk),\n .rclk (A_rclk),\n .pi_dqs_found (A_pi_dqs_found),\n .dqs_out_of_range (A_pi_dqs_out_of_range),\n .if_empty_def (if_empty_def),\n .if_a_empty (A_if_a_empty),\n .if_empty (A_if_empty),\n .if_a_full (/*if_a_full*/),\n .if_full (/*A_if_full*/),\n .of_a_empty (/*of_a_empty*/),\n .of_empty (/*A_of_empty*/),\n .of_a_full (A_of_a_full),\n .of_full (A_of_full),\n .pre_fifo_a_full (A_pre_fifo_a_full),\n .phy_din (phy_din_remap[79:0]),\n .phy_dout (phy_dout_remap[79:0]),\n .phy_cmd_wr_en (phy_cmd_wr_en),\n .phy_data_wr_en (phy_data_wr_en),\n .phy_rd_en (phy_rd_en),\n .phaser_ctl_bus (phaser_ctl_bus),\n .if_rst (if_rst),\n .byte_rd_en_oth_lanes ({B_byte_rd_en,C_byte_rd_en,D_byte_rd_en}),\n .byte_rd_en_oth_banks (byte_rd_en_oth_banks),\n .byte_rd_en (A_byte_rd_en),\n// calibration signals\n .idelay_inc (idelay_inc),\n .idelay_ce (A_idelay_ce),\n .idelay_ld (A_idelay_ld),\n .pi_rst_dqs_find (A_pi_rst_dqs_find),\n .po_en_calib (phy_encalib),\n .po_fine_enable (A_po_fine_enable),\n .po_coarse_enable (A_po_coarse_enable),\n .po_fine_inc (A_po_fine_inc),\n .po_coarse_inc (A_po_coarse_inc),\n .po_counter_load_en (A_po_counter_load_en),\n .po_counter_read_en (A_po_counter_read_en),\n .po_counter_load_val (A_po_counter_load_val),\n .po_coarse_overflow (A_po_coarse_overflow),\n .po_fine_overflow (A_po_fine_overflow),\n .po_counter_read_val (A_po_counter_read_val),\n .po_sel_fine_oclk_delay(A_po_sel_fine_oclk_delay),\n .pi_en_calib (phy_encalib),\n .pi_fine_enable (A_pi_fine_enable),\n .pi_fine_inc (A_pi_fine_inc),\n .pi_counter_load_en (A_pi_counter_load_en),\n .pi_counter_read_en (A_pi_counter_read_en),\n .pi_counter_load_val (A_pi_counter_load_val),\n .pi_fine_overflow (A_pi_fine_overflow),\n .pi_counter_read_val (A_pi_counter_read_val),\n .pi_iserdes_rst (A_pi_iserdes_rst),\n .pi_phase_locked (A_pi_phase_locked),\n .fine_delay (A_fine_delay),\n .fine_delay_sel (A_fine_delay_sel)\n);\n\nend\nelse begin : no_ddr_byte_lane_A\n assign A_of_a_full = 1'b0;\n assign A_of_full = 1'b0;\n assign A_pre_fifo_a_full = 1'b0;\n assign A_if_empty = 1'b0;\n assign A_byte_rd_en = 1'b1;\n assign A_if_a_empty = 1'b0;\n assign A_pi_phase_locked = 1;\n assign A_pi_dqs_found = 1;\n assign A_rclk = 0;\n assign A_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}};\n assign A_pi_counter_read_val = 0;\n assign A_po_counter_read_val = 0;\n assign A_pi_fine_overflow = 0;\n assign A_po_coarse_overflow = 0;\n assign A_po_fine_overflow = 0;\nend\n\nif ( BYTE_LANES[1] ) begin : ddr_byte_lane_B\n\n assign phy_dout_remap[159:80] = part_select_80(phy_dout, (LANE_REMAP[5:4]));\n mig_7series_v4_0_ddr_byte_lane #\n (\n .ABCD (\"B\"),\n .PO_DATA_CTL (PC_DATA_CTL_N[1] ? \"TRUE\" : \"FALSE\"),\n .BITLANES (BITLANES[23:12]),\n .BITLANES_OUTONLY (BITLANES_OUTONLY[23:12]),\n .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),\n .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),\n .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE),\n //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE),\n //.OF_ARRAY_MODE (B_OF_ARRAY_MODE),\n //.IF_ARRAY_MODE (IF_ARRAY_MODE),\n .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE),\n .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE),\n .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE),\n .IODELAY_GRP (IODELAY_GRP),\n .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),\n .BANK_TYPE (BANK_TYPE),\n .BYTELANES_DDR_CK (BYTELANES_DDR_CK),\n .RCLK_SELECT_LANE (RCLK_SELECT_LANE),\n .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),\n .SYNTHESIS (SYNTHESIS),\n .TCK (TCK),\n .PC_CLK_RATIO (PC_CLK_RATIO),\n .PI_BURST_MODE (B_PI_BURST_MODE),\n .PI_CLKOUT_DIV (B_PI_CLKOUT_DIV),\n .PI_FREQ_REF_DIV (B_PI_FREQ_REF_DIV),\n .PI_FINE_DELAY (B_PI_FINE_DELAY),\n .PI_OUTPUT_CLK_SRC (B_PI_OUTPUT_CLK_SRC),\n .PI_SYNC_IN_DIV_RST (B_PI_SYNC_IN_DIV_RST),\n .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),\n .PO_CLKOUT_DIV (B_PO_CLKOUT_DIV),\n .PO_FINE_DELAY (B_PO_FINE_DELAY),\n .PO_COARSE_BYPASS (B_PO_COARSE_BYPASS),\n .PO_COARSE_DELAY (B_PO_COARSE_DELAY),\n .PO_OCLK_DELAY (B_PO_OCLK_DELAY),\n .PO_OCLKDELAY_INV (B_PO_OCLKDELAY_INV),\n .PO_OUTPUT_CLK_SRC (B_PO_OUTPUT_CLK_SRC),\n .PO_SYNC_IN_DIV_RST (B_PO_SYNC_IN_DIV_RST),\n .OSERDES_DATA_RATE (B_OS_DATA_RATE),\n .OSERDES_DATA_WIDTH (B_OS_DATA_WIDTH),\n .IDELAYE2_IDELAY_TYPE (B_IDELAYE2_IDELAY_TYPE),\n .IDELAYE2_IDELAY_VALUE (B_IDELAYE2_IDELAY_VALUE)\n ,.CKE_ODT_AUX (CKE_ODT_AUX)\n ,.PI_DIV2_INCDEC (PI_DIV2_INCDEC)\n )\n ddr_byte_lane_B(\n .mem_dq_out (mem_dq_out[23:12]),\n .mem_dq_ts (mem_dq_ts[23:12]),\n .mem_dq_in (mem_dq_in[19:10]),\n .mem_dqs_out (mem_dqs_out[1]),\n .mem_dqs_ts (mem_dqs_ts[1]),\n .mem_dqs_in (mem_dqs_in[1]),\n .rst (B_rst_primitives),\n .rst_pi_div2 (B_pi_rst_div2),\n .phy_clk (phy_clk),\n .clk_div2 (clk_div2),\n .freq_refclk (freq_refclk),\n .mem_refclk (mem_refclk),\n .idelayctrl_refclk (idelayctrl_refclk),\n .sync_pulse (sync_pulse),\n .ddr_ck_out (B_ddr_clk),\n .rclk (B_rclk),\n .pi_dqs_found (B_pi_dqs_found),\n .dqs_out_of_range (B_pi_dqs_out_of_range),\n .if_empty_def (if_empty_def),\n .if_a_empty (B_if_a_empty),\n .if_empty (B_if_empty),\n .if_a_full (/*if_a_full*/),\n .if_full (/*B_if_full*/),\n .of_a_empty (/*of_a_empty*/),\n .of_empty (/*B_of_empty*/),\n .of_a_full (B_of_a_full),\n .of_full (B_of_full),\n .pre_fifo_a_full (B_pre_fifo_a_full),\n .phy_din (phy_din_remap[159:80]),\n .phy_dout (phy_dout_remap[159:80]),\n .phy_cmd_wr_en (phy_cmd_wr_en),\n .phy_data_wr_en (phy_data_wr_en),\n .phy_rd_en (phy_rd_en),\n .phaser_ctl_bus (phaser_ctl_bus),\n .if_rst (if_rst),\n .byte_rd_en_oth_lanes ({A_byte_rd_en,C_byte_rd_en,D_byte_rd_en}),\n .byte_rd_en_oth_banks (byte_rd_en_oth_banks),\n .byte_rd_en (B_byte_rd_en),\n// calibration signals\n .idelay_inc (idelay_inc),\n .idelay_ce (B_idelay_ce),\n .idelay_ld (B_idelay_ld),\n .pi_rst_dqs_find (B_pi_rst_dqs_find),\n .po_en_calib (phy_encalib),\n .po_fine_enable (B_po_fine_enable),\n .po_coarse_enable (B_po_coarse_enable),\n .po_fine_inc (B_po_fine_inc),\n .po_coarse_inc (B_po_coarse_inc),\n .po_counter_load_en (B_po_counter_load_en),\n .po_counter_read_en (B_po_counter_read_en),\n .po_counter_load_val (B_po_counter_load_val),\n .po_coarse_overflow (B_po_coarse_overflow),\n .po_fine_overflow (B_po_fine_overflow),\n .po_counter_read_val (B_po_counter_read_val),\n .po_sel_fine_oclk_delay(B_po_sel_fine_oclk_delay),\n .pi_en_calib (phy_encalib),\n .pi_fine_enable (B_pi_fine_enable),\n .pi_fine_inc (B_pi_fine_inc),\n .pi_counter_load_en (B_pi_counter_load_en),\n .pi_counter_read_en (B_pi_counter_read_en),\n .pi_counter_load_val (B_pi_counter_load_val),\n .pi_fine_overflow (B_pi_fine_overflow),\n .pi_counter_read_val (B_pi_counter_read_val),\n .pi_iserdes_rst (B_pi_iserdes_rst),\n .pi_phase_locked (B_pi_phase_locked),\n .fine_delay (B_fine_delay),\n .fine_delay_sel (B_fine_delay_sel)\n);\nend\nelse begin : no_ddr_byte_lane_B\n assign B_of_a_full = 1'b0;\n assign B_of_full = 1'b0;\n assign B_pre_fifo_a_full = 1'b0;\n assign B_if_empty = 1'b0;\n assign B_if_a_empty = 1'b0;\n assign B_byte_rd_en = 1'b1;\n assign B_pi_phase_locked = 1;\n assign B_pi_dqs_found = 1;\n assign B_rclk = 0;\n assign B_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}};\n assign B_pi_counter_read_val = 0;\n assign B_po_counter_read_val = 0;\n assign B_pi_fine_overflow = 0;\n assign B_po_coarse_overflow = 0;\n assign B_po_fine_overflow = 0;\nend\n\nif ( BYTE_LANES[2] ) begin : ddr_byte_lane_C\n\n assign phy_dout_remap[239:160] = part_select_80(phy_dout, (LANE_REMAP[9:8]));\n mig_7series_v4_0_ddr_byte_lane #\n (\n .ABCD (\"C\"),\n .PO_DATA_CTL (PC_DATA_CTL_N[2] ? \"TRUE\" : \"FALSE\"),\n .BITLANES (BITLANES[35:24]),\n .BITLANES_OUTONLY (BITLANES_OUTONLY[35:24]),\n .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),\n .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),\n .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE),\n //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE),\n //.OF_ARRAY_MODE (C_OF_ARRAY_MODE),\n //.IF_ARRAY_MODE (IF_ARRAY_MODE),\n .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE),\n .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE),\n .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE),\n .IODELAY_GRP (IODELAY_GRP),\n .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),\n .BANK_TYPE (BANK_TYPE),\n .BYTELANES_DDR_CK (BYTELANES_DDR_CK),\n .RCLK_SELECT_LANE (RCLK_SELECT_LANE),\n .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),\n .SYNTHESIS (SYNTHESIS),\n .TCK (TCK),\n .PC_CLK_RATIO (PC_CLK_RATIO),\n .PI_BURST_MODE (C_PI_BURST_MODE),\n .PI_CLKOUT_DIV (C_PI_CLKOUT_DIV),\n .PI_FREQ_REF_DIV (C_PI_FREQ_REF_DIV),\n .PI_FINE_DELAY (C_PI_FINE_DELAY),\n .PI_OUTPUT_CLK_SRC (C_PI_OUTPUT_CLK_SRC),\n .PI_SYNC_IN_DIV_RST (C_PI_SYNC_IN_DIV_RST),\n .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),\n .PO_CLKOUT_DIV (C_PO_CLKOUT_DIV),\n .PO_FINE_DELAY (C_PO_FINE_DELAY),\n .PO_COARSE_BYPASS (C_PO_COARSE_BYPASS),\n .PO_COARSE_DELAY (C_PO_COARSE_DELAY),\n .PO_OCLK_DELAY (C_PO_OCLK_DELAY),\n .PO_OCLKDELAY_INV (C_PO_OCLKDELAY_INV),\n .PO_OUTPUT_CLK_SRC (C_PO_OUTPUT_CLK_SRC),\n .PO_SYNC_IN_DIV_RST (C_PO_SYNC_IN_DIV_RST),\n .OSERDES_DATA_RATE (C_OS_DATA_RATE),\n .OSERDES_DATA_WIDTH (C_OS_DATA_WIDTH),\n .IDELAYE2_IDELAY_TYPE (C_IDELAYE2_IDELAY_TYPE),\n .IDELAYE2_IDELAY_VALUE (C_IDELAYE2_IDELAY_VALUE)\n ,.CKE_ODT_AUX (CKE_ODT_AUX)\n ,.PI_DIV2_INCDEC (PI_DIV2_INCDEC)\n )\n ddr_byte_lane_C(\n .mem_dq_out (mem_dq_out[35:24]),\n .mem_dq_ts (mem_dq_ts[35:24]),\n .mem_dq_in (mem_dq_in[29:20]),\n .mem_dqs_out (mem_dqs_out[2]),\n .mem_dqs_ts (mem_dqs_ts[2]),\n .mem_dqs_in (mem_dqs_in[2]),\n .rst (C_rst_primitives),\n .rst_pi_div2 (C_pi_rst_div2),\n .phy_clk (phy_clk),\n .clk_div2 (clk_div2),\n .freq_refclk (freq_refclk),\n .mem_refclk (mem_refclk),\n .idelayctrl_refclk (idelayctrl_refclk),\n .sync_pulse (sync_pulse),\n .ddr_ck_out (C_ddr_clk),\n .rclk (C_rclk),\n .pi_dqs_found (C_pi_dqs_found),\n .dqs_out_of_range (C_pi_dqs_out_of_range),\n .if_empty_def (if_empty_def),\n .if_a_empty (C_if_a_empty),\n .if_empty (C_if_empty),\n .if_a_full (/*if_a_full*/),\n .if_full (/*C_if_full*/),\n .of_a_empty (/*of_a_empty*/),\n .of_empty (/*C_of_empty*/),\n .of_a_full (C_of_a_full),\n .of_full (C_of_full),\n .pre_fifo_a_full (C_pre_fifo_a_full),\n .phy_din (phy_din_remap[239:160]),\n .phy_dout (phy_dout_remap[239:160]),\n .phy_cmd_wr_en (phy_cmd_wr_en),\n .phy_data_wr_en (phy_data_wr_en),\n .phy_rd_en (phy_rd_en),\n .phaser_ctl_bus (phaser_ctl_bus),\n .if_rst (if_rst),\n .byte_rd_en_oth_lanes ({A_byte_rd_en,B_byte_rd_en,D_byte_rd_en}),\n .byte_rd_en_oth_banks (byte_rd_en_oth_banks),\n .byte_rd_en (C_byte_rd_en),\n// calibration signals\n .idelay_inc (idelay_inc),\n .idelay_ce (C_idelay_ce),\n .idelay_ld (C_idelay_ld),\n .pi_rst_dqs_find (C_pi_rst_dqs_find),\n .po_en_calib (phy_encalib),\n .po_fine_enable (C_po_fine_enable),\n .po_coarse_enable (C_po_coarse_enable),\n .po_fine_inc (C_po_fine_inc),\n .po_coarse_inc (C_po_coarse_inc),\n .po_counter_load_en (C_po_counter_load_en),\n .po_counter_read_en (C_po_counter_read_en),\n .po_counter_load_val (C_po_counter_load_val),\n .po_coarse_overflow (C_po_coarse_overflow),\n .po_fine_overflow (C_po_fine_overflow),\n .po_counter_read_val (C_po_counter_read_val),\n .po_sel_fine_oclk_delay(C_po_sel_fine_oclk_delay),\n .pi_en_calib (phy_encalib),\n .pi_fine_enable (C_pi_fine_enable),\n .pi_fine_inc (C_pi_fine_inc),\n .pi_counter_load_en (C_pi_counter_load_en),\n .pi_counter_read_en (C_pi_counter_read_en),\n .pi_counter_load_val (C_pi_counter_load_val),\n .pi_fine_overflow (C_pi_fine_overflow),\n .pi_counter_read_val (C_pi_counter_read_val),\n .pi_iserdes_rst (C_pi_iserdes_rst),\n .pi_phase_locked (C_pi_phase_locked),\n .fine_delay (C_fine_delay),\n .fine_delay_sel (C_fine_delay_sel)\n);\n\nend\nelse begin : no_ddr_byte_lane_C\n assign C_of_a_full = 1'b0;\n assign C_of_full = 1'b0;\n assign C_pre_fifo_a_full = 1'b0;\n assign C_if_empty = 1'b0;\n assign C_byte_rd_en = 1'b1;\n assign C_if_a_empty = 1'b0;\n assign C_pi_phase_locked = 1;\n assign C_pi_dqs_found = 1;\n assign C_rclk = 0;\n assign C_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}};\n assign C_pi_counter_read_val = 0;\n assign C_po_counter_read_val = 0;\n assign C_pi_fine_overflow = 0;\n assign C_po_coarse_overflow = 0;\n assign C_po_fine_overflow = 0;\nend\n\nif ( BYTE_LANES[3] ) begin : ddr_byte_lane_D\n assign phy_dout_remap[319:240] = part_select_80(phy_dout, (LANE_REMAP[13:12]));\n\n mig_7series_v4_0_ddr_byte_lane #\n (\n .ABCD (\"D\"),\n .PO_DATA_CTL (PC_DATA_CTL_N[3] ? \"TRUE\" : \"FALSE\"),\n .BITLANES (BITLANES[47:36]),\n .BITLANES_OUTONLY (BITLANES_OUTONLY[47:36]),\n .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),\n .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),\n .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE),\n //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE),\n //.OF_ARRAY_MODE (D_OF_ARRAY_MODE),\n //.IF_ARRAY_MODE (IF_ARRAY_MODE),\n .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE),\n .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE),\n .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE),\n .IODELAY_GRP (IODELAY_GRP),\n .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),\n .BANK_TYPE (BANK_TYPE),\n .BYTELANES_DDR_CK (BYTELANES_DDR_CK),\n .RCLK_SELECT_LANE (RCLK_SELECT_LANE),\n .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),\n .SYNTHESIS (SYNTHESIS),\n .TCK (TCK),\n .PC_CLK_RATIO (PC_CLK_RATIO),\n .PI_BURST_MODE (D_PI_BURST_MODE),\n .PI_CLKOUT_DIV (D_PI_CLKOUT_DIV),\n .PI_FREQ_REF_DIV (D_PI_FREQ_REF_DIV),\n .PI_FINE_DELAY (D_PI_FINE_DELAY),\n .PI_OUTPUT_CLK_SRC (D_PI_OUTPUT_CLK_SRC),\n .PI_SYNC_IN_DIV_RST (D_PI_SYNC_IN_DIV_RST),\n .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),\n .PO_CLKOUT_DIV (D_PO_CLKOUT_DIV),\n .PO_FINE_DELAY (D_PO_FINE_DELAY),\n .PO_COARSE_BYPASS (D_PO_COARSE_BYPASS),\n .PO_COARSE_DELAY (D_PO_COARSE_DELAY),\n .PO_OCLK_DELAY (D_PO_OCLK_DELAY),\n .PO_OCLKDELAY_INV (D_PO_OCLKDELAY_INV),\n .PO_OUTPUT_CLK_SRC (D_PO_OUTPUT_CLK_SRC),\n .PO_SYNC_IN_DIV_RST (D_PO_SYNC_IN_DIV_RST),\n .OSERDES_DATA_RATE (D_OS_DATA_RATE),\n .OSERDES_DATA_WIDTH (D_OS_DATA_WIDTH),\n .IDELAYE2_IDELAY_TYPE (D_IDELAYE2_IDELAY_TYPE),\n .IDELAYE2_IDELAY_VALUE (D_IDELAYE2_IDELAY_VALUE)\n ,.CKE_ODT_AUX (CKE_ODT_AUX)\n ,.PI_DIV2_INCDEC (PI_DIV2_INCDEC)\n )\n ddr_byte_lane_D(\n .mem_dq_out (mem_dq_out[47:36]),\n .mem_dq_ts (mem_dq_ts[47:36]),\n .mem_dq_in (mem_dq_in[39:30]),\n .mem_dqs_out (mem_dqs_out[3]),\n .mem_dqs_ts (mem_dqs_ts[3]),\n .mem_dqs_in (mem_dqs_in[3]),\n .rst (D_rst_primitives),\n .rst_pi_div2 (D_pi_rst_div2),\n .phy_clk (phy_clk),\n .clk_div2 (clk_div2),\n .freq_refclk (freq_refclk),\n .mem_refclk (mem_refclk),\n .idelayctrl_refclk (idelayctrl_refclk),\n .sync_pulse (sync_pulse),\n .ddr_ck_out (D_ddr_clk),\n .rclk (D_rclk),\n .pi_dqs_found (D_pi_dqs_found),\n .dqs_out_of_range (D_pi_dqs_out_of_range),\n .if_empty_def (if_empty_def),\n .if_a_empty (D_if_a_empty),\n .if_empty (D_if_empty),\n .if_a_full (/*if_a_full*/),\n .if_full (/*D_if_full*/),\n .of_a_empty (/*of_a_empty*/),\n .of_empty (/*D_of_empty*/),\n .of_a_full (D_of_a_full),\n .of_full (D_of_full),\n .pre_fifo_a_full (D_pre_fifo_a_full),\n .phy_din (phy_din_remap[319:240]),\n .phy_dout (phy_dout_remap[319:240]),\n .phy_cmd_wr_en (phy_cmd_wr_en),\n .phy_data_wr_en (phy_data_wr_en),\n .phy_rd_en (phy_rd_en),\n .phaser_ctl_bus (phaser_ctl_bus),\n .idelay_inc (idelay_inc),\n .idelay_ce (D_idelay_ce),\n .idelay_ld (D_idelay_ld),\n .if_rst (if_rst),\n .byte_rd_en_oth_lanes ({A_byte_rd_en,B_byte_rd_en,C_byte_rd_en}),\n .byte_rd_en_oth_banks (byte_rd_en_oth_banks),\n .byte_rd_en (D_byte_rd_en),\n// calibration signals\n .pi_rst_dqs_find (D_pi_rst_dqs_find),\n .po_en_calib (phy_encalib),\n .po_fine_enable (D_po_fine_enable),\n .po_coarse_enable (D_po_coarse_enable),\n .po_fine_inc (D_po_fine_inc),\n .po_coarse_inc (D_po_coarse_inc),\n .po_counter_load_en (D_po_counter_load_en),\n .po_counter_read_en (D_po_counter_read_en),\n .po_counter_load_val (D_po_counter_load_val),\n .po_coarse_overflow (D_po_coarse_overflow),\n .po_fine_overflow (D_po_fine_overflow),\n .po_counter_read_val (D_po_counter_read_val),\n .po_sel_fine_oclk_delay(D_po_sel_fine_oclk_delay),\n .pi_en_calib (phy_encalib),\n .pi_fine_enable (D_pi_fine_enable),\n .pi_fine_inc (D_pi_fine_inc),\n .pi_counter_load_en (D_pi_counter_load_en),\n .pi_counter_read_en (D_pi_counter_read_en),\n .pi_counter_load_val (D_pi_counter_load_val),\n .pi_fine_overflow (D_pi_fine_overflow),\n .pi_counter_read_val (D_pi_counter_read_val),\n .pi_iserdes_rst (D_pi_iserdes_rst),\n .pi_phase_locked (D_pi_phase_locked),\n .fine_delay (D_fine_delay),\n .fine_delay_sel (D_fine_delay_sel)\n);\nend\nelse begin : no_ddr_byte_lane_D\n assign D_of_a_full = 1'b0;\n assign D_of_full = 1'b0;\n assign D_pre_fifo_a_full = 1'b0;\n assign D_if_empty = 1'b0;\n assign D_byte_rd_en = 1'b1;\n assign D_if_a_empty = 1'b0;\n assign D_rclk = 0;\n assign D_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}};\n assign D_pi_dqs_found = 1;\n assign D_pi_phase_locked = 1;\n assign D_pi_counter_read_val = 0;\n assign D_po_counter_read_val = 0;\n assign D_pi_fine_overflow = 0;\n assign D_po_coarse_overflow = 0;\n assign D_po_fine_overflow = 0;\nend\nendgenerate\n\n\nassign phaser_ctl_bus[MSB_RANK_SEL_I : MSB_RANK_SEL_I - 7] = in_rank;\n\nPHY_CONTROL #(\n .AO_WRLVL_EN ( PC_AO_WRLVL_EN),\n .AO_TOGGLE ( PC_AO_TOGGLE),\n .BURST_MODE ( PC_BURST_MODE),\n .CO_DURATION ( PC_CO_DURATION ),\n .CLK_RATIO ( PC_CLK_RATIO),\n .DATA_CTL_A_N ( PC_DATA_CTL_A),\n .DATA_CTL_B_N ( PC_DATA_CTL_B),\n .DATA_CTL_C_N ( PC_DATA_CTL_C),\n .DATA_CTL_D_N ( PC_DATA_CTL_D),\n .DI_DURATION ( PC_DI_DURATION ),\n .DO_DURATION ( PC_DO_DURATION ),\n .EVENTS_DELAY ( PC_EVENTS_DELAY),\n .FOUR_WINDOW_CLOCKS ( PC_FOUR_WINDOW_CLOCKS),\n .MULTI_REGION ( PC_MULTI_REGION ),\n .PHY_COUNT_ENABLE ( PC_PHY_COUNT_EN),\n .DISABLE_SEQ_MATCH ( PC_DISABLE_SEQ_MATCH),\n .SYNC_MODE ( PC_SYNC_MODE),\n .CMD_OFFSET ( PC_CMD_OFFSET),\n\n .RD_CMD_OFFSET_0 ( PC_RD_CMD_OFFSET_0),\n .RD_CMD_OFFSET_1 ( PC_RD_CMD_OFFSET_1),\n .RD_CMD_OFFSET_2 ( PC_RD_CMD_OFFSET_2),\n .RD_CMD_OFFSET_3 ( PC_RD_CMD_OFFSET_3),\n .RD_DURATION_0 ( PC_RD_DURATION_0),\n .RD_DURATION_1 ( PC_RD_DURATION_1),\n .RD_DURATION_2 ( PC_RD_DURATION_2),\n .RD_DURATION_3 ( PC_RD_DURATION_3),\n .WR_CMD_OFFSET_0 ( PC_WR_CMD_OFFSET_0),\n .WR_CMD_OFFSET_1 ( PC_WR_CMD_OFFSET_1),\n .WR_CMD_OFFSET_2 ( PC_WR_CMD_OFFSET_2),\n .WR_CMD_OFFSET_3 ( PC_WR_CMD_OFFSET_3),\n .WR_DURATION_0 ( PC_WR_DURATION_0),\n .WR_DURATION_1 ( PC_WR_DURATION_1),\n .WR_DURATION_2 ( PC_WR_DURATION_2),\n .WR_DURATION_3 ( PC_WR_DURATION_3)\n) phy_control_i (\n .AUXOUTPUT (aux_out),\n .INBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PI:MSB_BURST_PEND_PI-3]),\n .INRANKA (in_rank[1:0]),\n .INRANKB (in_rank[3:2]),\n .INRANKC (in_rank[5:4]),\n .INRANKD (in_rank[7:6]),\n .OUTBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PO:MSB_BURST_PEND_PO-3]),\n .PCENABLECALIB (phy_encalib),\n .PHYCTLALMOSTFULL (phy_ctl_a_full),\n .PHYCTLEMPTY (phy_ctl_empty),\n .PHYCTLFULL (phy_ctl_full),\n .PHYCTLREADY (phy_ctl_ready),\n .MEMREFCLK (mem_refclk),\n .PHYCLK (phy_ctl_clk),\n .PHYCTLMSTREMPTY (phy_ctl_mstr_empty),\n .PHYCTLWD (_phy_ctl_wd),\n .PHYCTLWRENABLE (phy_ctl_wr),\n .PLLLOCK (pll_lock),\n .REFDLLLOCK (ref_dll_lock), // is reset while !locked\n .RESET (rst),\n .SYNCIN (sync_pulse),\n .READCALIBENABLE (phy_read_calib),\n .WRITECALIBENABLE (phy_write_calib)\n`ifdef USE_PHY_CONTROL_TEST\n , .TESTINPUT (16'b0),\n .TESTOUTPUT (test_output),\n .TESTSELECT (test_select),\n .SCANENABLEN (scan_enable)\n`endif\n);\n\n\n\n// register outputs to give extra slack in timing\nalways @(posedge phy_clk ) begin\n case (calib_sel[1:0])\n 2'h0: begin\n po_coarse_overflow <= #1 A_po_coarse_overflow;\n po_fine_overflow <= #1 A_po_fine_overflow;\n po_counter_read_val <= #1 A_po_counter_read_val;\n\n pi_fine_overflow <= #1 A_pi_fine_overflow;\n pi_counter_read_val<= #1 A_pi_counter_read_val;\n\n pi_phase_locked <= #1 A_pi_phase_locked;\n if ( calib_in_common)\n pi_dqs_found <= #1 pi_dqs_found_any;\n else\n pi_dqs_found <= #1 A_pi_dqs_found;\n pi_dqs_out_of_range <= #1 A_pi_dqs_out_of_range;\n end\n\n 2'h1: begin\n po_coarse_overflow <= #1 B_po_coarse_overflow;\n po_fine_overflow <= #1 B_po_fine_overflow;\n po_counter_read_val <= #1 B_po_counter_read_val;\n\n pi_fine_overflow <= #1 B_pi_fine_overflow;\n pi_counter_read_val <= #1 B_pi_counter_read_val;\n\n pi_phase_locked <= #1 B_pi_phase_locked;\n if ( calib_in_common)\n pi_dqs_found <= #1 pi_dqs_found_any;\n else\n pi_dqs_found <= #1 B_pi_dqs_found;\n pi_dqs_out_of_range <= #1 B_pi_dqs_out_of_range;\n end\n\n 2'h2: begin\n po_coarse_overflow <= #1 C_po_coarse_overflow;\n po_fine_overflow <= #1 C_po_fine_overflow;\n po_counter_read_val <= #1 C_po_counter_read_val;\n\n pi_fine_overflow <= #1 C_pi_fine_overflow;\n pi_counter_read_val <= #1 C_pi_counter_read_val;\n\n pi_phase_locked <= #1 C_pi_phase_locked;\n if ( calib_in_common)\n pi_dqs_found <= #1 pi_dqs_found_any;\n else\n pi_dqs_found <= #1 C_pi_dqs_found;\n pi_dqs_out_of_range <= #1 C_pi_dqs_out_of_range;\n end\n\n 2'h3: begin\n po_coarse_overflow <= #1 D_po_coarse_overflow;\n po_fine_overflow <= #1 D_po_fine_overflow;\n po_counter_read_val <= #1 D_po_counter_read_val;\n\n pi_fine_overflow <= #1 D_pi_fine_overflow;\n pi_counter_read_val <= #1 D_pi_counter_read_val;\n\n pi_phase_locked <= #1 D_pi_phase_locked;\n if ( calib_in_common)\n pi_dqs_found <= #1 pi_dqs_found_any;\n else\n pi_dqs_found <= #1 D_pi_dqs_found;\n pi_dqs_out_of_range <= #1 D_pi_dqs_out_of_range;\n\n end\n default: begin\n po_coarse_overflow <= po_coarse_overflow;\n end\n endcase\nend\n\nwire B_mux_ctrl;\nwire C_mux_ctrl;\nwire D_mux_ctrl;\ngenerate\n if (HIGHEST_LANE > 1)\n assign B_mux_ctrl = ( !calib_zero_lanes[1] && ( ! calib_zero_ctrl || DATA_CTL_N[1]));\n else\n assign B_mux_ctrl = 0;\n if (HIGHEST_LANE > 2)\n assign C_mux_ctrl = ( !calib_zero_lanes[2] && (! calib_zero_ctrl || DATA_CTL_N[2]));\n else\n assign C_mux_ctrl = 0;\n if (HIGHEST_LANE > 3)\n assign D_mux_ctrl = ( !calib_zero_lanes[3] && ( ! calib_zero_ctrl || DATA_CTL_N[3]));\n else\n assign D_mux_ctrl = 0;\nendgenerate\n\nalways @(*) begin\n A_pi_fine_enable = 0;\n A_pi_fine_inc = 0;\n A_pi_counter_load_en = 0;\n A_pi_counter_read_en = 0;\n A_pi_counter_load_val = 0;\n A_pi_rst_dqs_find = 0;\n\n\n A_po_fine_enable = 0;\n A_po_coarse_enable = 0;\n A_po_fine_inc = 0;\n A_po_coarse_inc = 0;\n A_po_counter_load_en = 0;\n A_po_counter_read_en = 0;\n A_po_counter_load_val = 0;\n A_po_sel_fine_oclk_delay = 0;\n\n A_idelay_ce = 0;\n A_idelay_ld = 0;\n A_fine_delay = 0;\n A_fine_delay_sel = 0;\n\n B_pi_fine_enable = 0;\n B_pi_fine_inc = 0;\n B_pi_counter_load_en = 0;\n B_pi_counter_read_en = 0;\n B_pi_counter_load_val = 0;\n B_pi_rst_dqs_find = 0;\n\n\n B_po_fine_enable = 0;\n B_po_coarse_enable = 0;\n B_po_fine_inc = 0;\n B_po_coarse_inc = 0;\n B_po_counter_load_en = 0;\n B_po_counter_read_en = 0;\n B_po_counter_load_val = 0;\n B_po_sel_fine_oclk_delay = 0;\n\n B_idelay_ce = 0;\n B_idelay_ld = 0;\n B_fine_delay = 0;\n B_fine_delay_sel = 0;\n\n C_pi_fine_enable = 0;\n C_pi_fine_inc = 0;\n C_pi_counter_load_en = 0;\n C_pi_counter_read_en = 0;\n C_pi_counter_load_val = 0;\n C_pi_rst_dqs_find = 0;\n\n\n C_po_fine_enable = 0;\n C_po_coarse_enable = 0;\n C_po_fine_inc = 0;\n C_po_coarse_inc = 0;\n C_po_counter_load_en = 0;\n C_po_counter_read_en = 0;\n C_po_counter_load_val = 0;\n C_po_sel_fine_oclk_delay = 0;\n\n C_idelay_ce = 0;\n C_idelay_ld = 0;\n C_fine_delay = 0;\n C_fine_delay_sel = 0;\n\n D_pi_fine_enable = 0;\n D_pi_fine_inc = 0;\n D_pi_counter_load_en = 0;\n D_pi_counter_read_en = 0;\n D_pi_counter_load_val = 0;\n D_pi_rst_dqs_find = 0;\n\n\n D_po_fine_enable = 0;\n D_po_coarse_enable = 0;\n D_po_fine_inc = 0;\n D_po_coarse_inc = 0;\n D_po_counter_load_en = 0;\n D_po_counter_read_en = 0;\n D_po_counter_load_val = 0;\n D_po_sel_fine_oclk_delay = 0;\n\n D_idelay_ce = 0;\n D_idelay_ld = 0;\n D_fine_delay = 0;\n D_fine_delay_sel = 0;\n\n if ( calib_sel[2]) begin\n // if this is asserted, all calib signals are deasserted\n A_pi_fine_enable = 0;\n A_pi_fine_inc = 0;\n A_pi_counter_load_en = 0;\n A_pi_counter_read_en = 0;\n A_pi_counter_load_val = 0;\n A_pi_rst_dqs_find = 0;\n\n\n A_po_fine_enable = 0;\n A_po_coarse_enable = 0;\n A_po_fine_inc = 0;\n A_po_coarse_inc = 0;\n A_po_counter_load_en = 0;\n A_po_counter_read_en = 0;\n A_po_counter_load_val = 0;\n A_po_sel_fine_oclk_delay = 0;\n\n A_idelay_ce = 0;\n A_idelay_ld = 0;\n A_fine_delay = 0;\n A_fine_delay_sel = 0;\n\n B_pi_fine_enable = 0;\n B_pi_fine_inc = 0;\n B_pi_counter_load_en = 0;\n B_pi_counter_read_en = 0;\n B_pi_counter_load_val = 0;\n B_pi_rst_dqs_find = 0;\n\n\n B_po_fine_enable = 0;\n B_po_coarse_enable = 0;\n B_po_fine_inc = 0;\n B_po_coarse_inc = 0;\n B_po_counter_load_en = 0;\n B_po_counter_read_en = 0;\n B_po_counter_load_val = 0;\n B_po_sel_fine_oclk_delay = 0;\n\n B_idelay_ce = 0;\n B_idelay_ld = 0;\n B_fine_delay = 0;\n B_fine_delay_sel = 0;\n\n\n C_pi_fine_enable = 0;\n C_pi_fine_inc = 0;\n C_pi_counter_load_en = 0;\n C_pi_counter_read_en = 0;\n C_pi_counter_load_val = 0;\n C_pi_rst_dqs_find = 0;\n\n\n C_po_fine_enable = 0;\n C_po_coarse_enable = 0;\n C_po_fine_inc = 0;\n C_po_coarse_inc = 0;\n C_po_counter_load_en = 0;\n C_po_counter_read_en = 0;\n C_po_counter_load_val = 0;\n C_po_sel_fine_oclk_delay = 0;\n\n C_idelay_ce = 0;\n C_idelay_ld = 0;\n C_fine_delay = 0;\n C_fine_delay_sel = 0;\n\n\n D_pi_fine_enable = 0;\n D_pi_fine_inc = 0;\n D_pi_counter_load_en = 0;\n D_pi_counter_read_en = 0;\n D_pi_counter_load_val = 0;\n D_pi_rst_dqs_find = 0;\n\n\n D_po_fine_enable = 0;\n D_po_coarse_enable = 0;\n D_po_fine_inc = 0;\n D_po_coarse_inc = 0;\n D_po_counter_load_en = 0;\n D_po_counter_read_en = 0;\n D_po_counter_load_val = 0;\n D_po_sel_fine_oclk_delay = 0;\n\n D_idelay_ce = 0;\n D_idelay_ld = 0;\n D_fine_delay = 0;\n D_fine_delay_sel = 0;\n\n end else\n if (calib_in_common) begin\n // if this is asserted, each signal is broadcast to all phasers\n // in common\n if ( !calib_zero_lanes[0] && (! calib_zero_ctrl || DATA_CTL_N[0])) begin\n A_pi_fine_enable = pi_fine_enable;\n A_pi_fine_inc = pi_fine_inc;\n A_pi_counter_load_en = pi_counter_load_en;\n A_pi_counter_read_en = pi_counter_read_en;\n A_pi_counter_load_val = pi_counter_load_val;\n A_pi_rst_dqs_find = pi_rst_dqs_find;\n\n\n A_po_fine_enable = po_fine_enable;\n A_po_coarse_enable = po_coarse_enable;\n A_po_fine_inc = po_fine_inc;\n A_po_coarse_inc = po_coarse_inc;\n A_po_counter_load_en = po_counter_load_en;\n A_po_counter_read_en = po_counter_read_en;\n A_po_counter_load_val = po_counter_load_val;\n A_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;\n\n A_idelay_ce = idelay_ce;\n A_idelay_ld = idelay_ld;\n A_fine_delay = fine_delay ;\n A_fine_delay_sel = fine_delay_sel;\n end\n\n if ( B_mux_ctrl) begin\n B_pi_fine_enable = pi_fine_enable;\n B_pi_fine_inc = pi_fine_inc;\n B_pi_counter_load_en = pi_counter_load_en;\n B_pi_counter_read_en = pi_counter_read_en;\n B_pi_counter_load_val = pi_counter_load_val;\n B_pi_rst_dqs_find = pi_rst_dqs_find;\n\n\n B_po_fine_enable = po_fine_enable;\n B_po_coarse_enable = po_coarse_enable;\n B_po_fine_inc = po_fine_inc;\n B_po_coarse_inc = po_coarse_inc;\n B_po_counter_load_en = po_counter_load_en;\n B_po_counter_read_en = po_counter_read_en;\n B_po_counter_load_val = po_counter_load_val;\n B_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;\n\n B_idelay_ce = idelay_ce;\n B_idelay_ld = idelay_ld;\n B_fine_delay = fine_delay ;\n B_fine_delay_sel = fine_delay_sel;\n end\n\n if ( C_mux_ctrl) begin\n C_pi_fine_enable = pi_fine_enable;\n C_pi_fine_inc = pi_fine_inc;\n C_pi_counter_load_en = pi_counter_load_en;\n C_pi_counter_read_en = pi_counter_read_en;\n C_pi_counter_load_val = pi_counter_load_val;\n C_pi_rst_dqs_find = pi_rst_dqs_find;\n\n\n C_po_fine_enable = po_fine_enable;\n C_po_coarse_enable = po_coarse_enable;\n C_po_fine_inc = po_fine_inc;\n C_po_coarse_inc = po_coarse_inc;\n C_po_counter_load_en = po_counter_load_en;\n C_po_counter_read_en = po_counter_read_en;\n C_po_counter_load_val = po_counter_load_val;\n C_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;\n\n C_idelay_ce = idelay_ce;\n C_idelay_ld = idelay_ld;\n C_fine_delay = fine_delay ;\n C_fine_delay_sel = fine_delay_sel;\n end\n\n if ( D_mux_ctrl) begin\n D_pi_fine_enable = pi_fine_enable;\n D_pi_fine_inc = pi_fine_inc;\n D_pi_counter_load_en = pi_counter_load_en;\n D_pi_counter_read_en = pi_counter_read_en;\n D_pi_counter_load_val = pi_counter_load_val;\n D_pi_rst_dqs_find = pi_rst_dqs_find;\n\n\n D_po_fine_enable = po_fine_enable;\n D_po_coarse_enable = po_coarse_enable;\n D_po_fine_inc = po_fine_inc;\n D_po_coarse_inc = po_coarse_inc;\n D_po_counter_load_en = po_counter_load_en;\n D_po_counter_read_en = po_counter_read_en;\n D_po_counter_load_val = po_counter_load_val;\n D_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;\n\n D_idelay_ce = idelay_ce;\n D_idelay_ld = idelay_ld;\n D_fine_delay = fine_delay ;\n D_fine_delay_sel = fine_delay_sel;\n end\n end\n else begin\n // otherwise, only a single phaser is selected\n\n\n case (calib_sel[1:0])\n 0: begin\n A_pi_fine_enable = pi_fine_enable;\n A_pi_fine_inc = pi_fine_inc;\n A_pi_counter_load_en = pi_counter_load_en;\n A_pi_counter_read_en = pi_counter_read_en;\n A_pi_counter_load_val = pi_counter_load_val;\n A_pi_rst_dqs_find = pi_rst_dqs_find;\n\n\n A_po_fine_enable = po_fine_enable;\n A_po_coarse_enable = po_coarse_enable;\n A_po_fine_inc = po_fine_inc;\n A_po_coarse_inc = po_coarse_inc;\n A_po_counter_load_en = po_counter_load_en;\n A_po_counter_read_en = po_counter_read_en;\n A_po_counter_load_val = po_counter_load_val;\n A_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;\n\n A_idelay_ce = idelay_ce;\n A_idelay_ld = idelay_ld;\n A_fine_delay = fine_delay ;\n A_fine_delay_sel = fine_delay_sel;\n\n end\n 1: begin\n B_pi_fine_enable = pi_fine_enable;\n B_pi_fine_inc = pi_fine_inc;\n B_pi_counter_load_en = pi_counter_load_en;\n B_pi_counter_read_en = pi_counter_read_en;\n B_pi_counter_load_val = pi_counter_load_val;\n B_pi_rst_dqs_find = pi_rst_dqs_find;\n\n\n B_po_fine_enable = po_fine_enable;\n B_po_coarse_enable = po_coarse_enable;\n B_po_fine_inc = po_fine_inc;\n B_po_coarse_inc = po_coarse_inc;\n B_po_counter_load_en = po_counter_load_en;\n B_po_counter_read_en = po_counter_read_en;\n B_po_counter_load_val = po_counter_load_val;\n B_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;\n\n B_idelay_ce = idelay_ce;\n B_idelay_ld = idelay_ld;\n B_fine_delay = fine_delay ;\n B_fine_delay_sel = fine_delay_sel;\n\n end\n\n 2: begin\n C_pi_fine_enable = pi_fine_enable;\n C_pi_fine_inc = pi_fine_inc;\n C_pi_counter_load_en = pi_counter_load_en;\n C_pi_counter_read_en = pi_counter_read_en;\n C_pi_counter_load_val = pi_counter_load_val;\n C_pi_rst_dqs_find = pi_rst_dqs_find;\n\n\n C_po_fine_enable = po_fine_enable;\n C_po_coarse_enable = po_coarse_enable;\n C_po_fine_inc = po_fine_inc;\n C_po_coarse_inc = po_coarse_inc;\n C_po_counter_load_en = po_counter_load_en;\n C_po_counter_read_en = po_counter_read_en;\n C_po_counter_load_val = po_counter_load_val;\n C_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;\n\n C_idelay_ce = idelay_ce;\n C_idelay_ld = idelay_ld;\n C_fine_delay = fine_delay ;\n C_fine_delay_sel = fine_delay_sel;\n\n end\n\n 3: begin\n D_pi_fine_enable = pi_fine_enable;\n D_pi_fine_inc = pi_fine_inc;\n D_pi_counter_load_en = pi_counter_load_en;\n D_pi_counter_read_en = pi_counter_read_en;\n D_pi_counter_load_val = pi_counter_load_val;\n D_pi_rst_dqs_find = pi_rst_dqs_find;\n\n\n D_po_fine_enable = po_fine_enable;\n D_po_coarse_enable = po_coarse_enable;\n D_po_fine_inc = po_fine_inc;\n D_po_coarse_inc = po_coarse_inc;\n D_po_counter_load_en = po_counter_load_en;\n D_po_counter_load_val = po_counter_load_val;\n D_po_counter_read_en = po_counter_read_en;\n D_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;\n\n D_idelay_ce = idelay_ce;\n D_idelay_ld = idelay_ld;\n D_fine_delay = fine_delay ;\n D_fine_delay_sel = fine_delay_sel;\n\n end\n endcase\n end\nend\n\n//obligatory phaser-ref\nPHASER_REF phaser_ref_i(\n\n .LOCKED (ref_dll_lock),\n .CLKIN (freq_refclk),\n .PWRDWN (1'b0),\n .RST ( ! pll_lock)\n\n);\n\n\n// optional idelay_ctrl\ngenerate\nif ( GENERATE_IDELAYCTRL == \"TRUE\")\nIDELAYCTRL idelayctrl (\n .RDY (/*idelayctrl_rdy*/),\n .REFCLK (idelayctrl_refclk),\n .RST (rst)\n);\nendgenerate\n\n\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay.v", "content": "//*****************************************************************************\n// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor: Xilinx\n// \\ \\ \\/ Version: %version\n// \\ \\ Application: MIG\n// / / Filename: ddr_phy_ck_addr_cmd_delay.v\n// /___/ /\\ Date Last Modified: $Date: 2011/02/25 02:07:40 $\n// \\ \\ / \\ Date Created: Aug 03 2009\n// \\___\\/\\___\\\n//\n//Device: 7 Series\n//Design Name: DDR3 SDRAM\n//Purpose: Shift CK/Address/Commands/Controls\n//Reference:\n//Revision History:\n//*****************************************************************************\n\n`timescale 1ps/1ps\n\nmodule mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay #\n (\n parameter TCQ = 100,\n parameter tCK = 3636,\n parameter DQS_CNT_WIDTH = 3,\n parameter N_CTL_LANES = 3,\n parameter SIM_CAL_OPTION = \"NONE\"\n )\n (\n input clk,\n input rst,\n // Start only after PO_CIRC_BUF_DELAY decremented\n input cmd_delay_start,\n // Control lane being shifted using Phaser_Out fine delay taps\n output reg [N_CTL_LANES-1:0] ctl_lane_cnt,\n // Inc/dec Phaser_Out fine delay line\n output reg po_stg2_f_incdec,\n output reg po_en_stg2_f,\n output reg po_stg2_c_incdec,\n output reg po_en_stg2_c,\n // Completed delaying CK/Address/Commands/Controls\n output po_ck_addr_cmd_delay_done\n );\n\n localparam TAP_CNT_LIMIT = 63;\n\n //Calculate the tap resolution of the PHASER based on the clock period\n localparam FREQ_REF_DIV = (tCK > 5000 ? 4 :\n tCK > 2500 ? 2 : 1);\n\n localparam integer PHASER_TAP_RES = ((tCK/2)/64);\n\n // Determine whether 300 ps or 350 ps delay required\n localparam CALC_TAP_CNT = (tCK >= 1250) ? 350 : 300;\n\n // Determine the number of Phaser_Out taps required to delay by 300 ps\n // 300 ps is the PCB trace uncertainty between CK and DQS byte groups\n\n\n // Increment control byte lanes\n localparam TAP_CNT = 0;\n //localparam TAP_CNT = (CALC_TAP_CNT + PHASER_TAP_RES - 1)/PHASER_TAP_RES;\n //Decrement control byte lanes\n localparam TAP_DEC = (SIM_CAL_OPTION == \"FAST_CAL\") ? 0 : 29;\n\n\n\n\n reg delay_dec_done;\n reg delay_done_r1;\n reg delay_done_r2;\n reg delay_done_r3;\n reg delay_done_r4 /* synthesis syn_maxfan = 10 */;\n reg [5:0] delay_cnt_r;\n reg [5:0] delaydec_cnt_r;\n reg po_cnt_inc;\n reg po_cnt_dec;\n reg [3:0] wait_cnt_r;\n\n assign po_ck_addr_cmd_delay_done = ((TAP_CNT == 0) && (TAP_DEC == 0)) ? 1'b1 : delay_done_r4;\n\n always @(posedge clk) begin\n if (rst || po_cnt_dec || po_cnt_inc)\n wait_cnt_r <= #TCQ 'd8;\n else if (cmd_delay_start && (wait_cnt_r > 'd0))\n wait_cnt_r <= #TCQ wait_cnt_r - 1;\n end\n\n always @(posedge clk) begin\n if (rst || (delaydec_cnt_r > 6'd0) || (delay_cnt_r == 'd0) || (TAP_DEC == 0))\n po_cnt_inc <= #TCQ 1'b0;\n else if ((delay_cnt_r > 'd0) && (wait_cnt_r == 'd1))\n po_cnt_inc <= #TCQ 1'b1;\n else\n po_cnt_inc <= #TCQ 1'b0;\n end\n\n //Tap decrement\n always @(posedge clk) begin\n if (rst || (delaydec_cnt_r == 'd0))\n po_cnt_dec <= #TCQ 1'b0;\n else if (cmd_delay_start && (delaydec_cnt_r > 'd0) && (wait_cnt_r == 'd1))\n po_cnt_dec <= #TCQ 1'b1;\n else\n po_cnt_dec <= #TCQ 1'b0;\n end\n\n //po_stg2_f_incdec and po_en_stg2_f stay asserted HIGH for TAP_COUNT cycles for every control byte lane\n //the alignment is started once the\n always @(posedge clk) begin\n if (rst) begin\n po_stg2_f_incdec <= #TCQ 1'b0;\n po_en_stg2_f <= #TCQ 1'b0;\n po_stg2_c_incdec <= #TCQ 1'b0;\n po_en_stg2_c <= #TCQ 1'b0;\n end else begin\n if (po_cnt_dec) begin\n po_stg2_f_incdec <= #TCQ 1'b0;\n po_en_stg2_f <= #TCQ 1'b1;\n end else begin\n po_stg2_f_incdec <= #TCQ 1'b0;\n po_en_stg2_f <= #TCQ 1'b0;\n end\n if (po_cnt_inc) begin\n po_stg2_c_incdec <= #TCQ 1'b1;\n po_en_stg2_c <= #TCQ 1'b1;\n end else begin\n po_stg2_c_incdec <= #TCQ 1'b0;\n po_en_stg2_c <= #TCQ 1'b0;\n end\n end\n end\n\n // delay counter to count 2 cycles\n // Increment coarse taps by 2 for all control byte lanes\n // to mitigate late writes\n always @(posedge clk) begin\n // load delay counter with init value\n if (rst || (tCK >= 2500) || (SIM_CAL_OPTION == \"FAST_CAL\"))\n delay_cnt_r <= #TCQ 'd0;\n else if ((delaydec_cnt_r > 6'd0) ||((delay_cnt_r == 6'd0) && (ctl_lane_cnt != N_CTL_LANES-1)))\n delay_cnt_r <= #TCQ 'd1;\n else if (po_cnt_inc && (delay_cnt_r > 6'd0))\n delay_cnt_r <= #TCQ delay_cnt_r - 1;\n end\n\n // delay counter to count TAP_DEC cycles\n always @(posedge clk) begin\n // load delay counter with init value of TAP_DEC\n if (rst || ~cmd_delay_start ||((delaydec_cnt_r == 6'd0) && (delay_cnt_r == 6'd0) && (ctl_lane_cnt != N_CTL_LANES-1)))\n delaydec_cnt_r <= #TCQ TAP_DEC;\n else if (po_cnt_dec && (delaydec_cnt_r > 6'd0))\n delaydec_cnt_r <= #TCQ delaydec_cnt_r - 1;\n end\n\n //ctl_lane_cnt is used to count the number of CTL_LANES or byte lanes that have the address/command phase shifted by 1/4 mem. cycle\n //This ensures all ctrl byte lanes have had their output phase shifted.\n always @(posedge clk) begin\n if (rst || ~cmd_delay_start )\n ctl_lane_cnt <= #TCQ 6'b0;\n else if (~delay_dec_done && (ctl_lane_cnt == N_CTL_LANES-1) && (delaydec_cnt_r == 6'd1))\n ctl_lane_cnt <= #TCQ ctl_lane_cnt;\n else if ((ctl_lane_cnt != N_CTL_LANES-1) && (delaydec_cnt_r == 6'd0) && (delay_cnt_r == 'd0))\n ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;\n end\n\n // All control lanes have decremented to 31 fine taps from 46\n always @(posedge clk) begin\n if (rst || ~cmd_delay_start) begin\n delay_dec_done <= #TCQ 1'b0;\n end else if (((TAP_CNT == 0) && (TAP_DEC == 0)) ||\n ((delaydec_cnt_r == 6'd0) && (delay_cnt_r == 'd0) && (ctl_lane_cnt == N_CTL_LANES-1))) begin\n delay_dec_done <= #TCQ 1'b1;\n end\n end\n\n\n\n always @(posedge clk) begin\n delay_done_r1 <= #TCQ delay_dec_done;\n delay_done_r2 <= #TCQ delay_done_r1;\n delay_done_r3 <= #TCQ delay_done_r2;\n delay_done_r4 <= #TCQ delay_done_r3;\n end\n\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_dqs_found_cal.v", "content": "//*****************************************************************************\n// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor: Xilinx\n// \\ \\ \\/ Version:\n// \\ \\ Application: MIG\n// / / Filename: ddr_phy_dqs_found_cal.v\n// /___/ /\\ Date Last Modified: $Date: 2011/06/02 08:35:08 $\n// \\ \\ / \\ Date Created:\n// \\___\\/\\___\\\n//\n//Device: 7 Series\n//Design Name: DDR3 SDRAM\n//Purpose:\n// Read leveling calibration logic\n// NOTES:\n// 1. Phaser_In DQSFOUND calibration\n//Reference:\n//Revision History:\n//*****************************************************************************\n\n/******************************************************************************\n**$Id: ddr_phy_dqs_found_cal.v,v 1.1 2011/06/02 08:35:08 mishra Exp $\n**$Date: 2011/06/02 08:35:08 $\n**$Author: \n**$Revision:\n**$Source: \n******************************************************************************/\n\n`timescale 1ps/1ps\n\nmodule mig_7series_v4_0_ddr_phy_dqs_found_cal #\n (\n parameter TCQ = 100, // clk->out delay (sim only)\n parameter nCK_PER_CLK = 2, // # of memory clocks per CLK\n parameter nCL = 5, // Read CAS latency\n parameter AL = \"0\",\n parameter nCWL = 5, // Write CAS latency\n parameter DRAM_TYPE = \"DDR3\", // Memory I/F type: \"DDR3\", \"DDR2\"\n parameter RANKS = 1, // # of memory ranks in the system\n parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))\n parameter DQS_WIDTH = 8, // # of DQS (strobe)\n parameter DRAM_WIDTH = 8, // # of DQ per DQS\n parameter REG_CTRL = \"ON\", // \"ON\" for registered DIMM\n parameter SIM_CAL_OPTION = \"NONE\", // Performs all calibration steps\n parameter NUM_DQSFOUND_CAL = 3, // Number of times to iterate\n parameter N_CTL_LANES = 3, // Number of control byte lanes\n parameter HIGHEST_LANE = 12, // Sum of byte lanes (Data + Ctrl)\n parameter HIGHEST_BANK = 3, // Sum of I/O Banks\n parameter BYTE_LANES_B0 = 4'b1111,\n parameter BYTE_LANES_B1 = 4'b0000,\n parameter BYTE_LANES_B2 = 4'b0000,\n parameter BYTE_LANES_B3 = 4'b0000,\n parameter BYTE_LANES_B4 = 4'b0000,\n parameter DATA_CTL_B0 = 4'hc,\n parameter DATA_CTL_B1 = 4'hf,\n parameter DATA_CTL_B2 = 4'hf,\n parameter DATA_CTL_B3 = 4'hf,\n parameter DATA_CTL_B4 = 4'hf\n )\n (\n input clk,\n input rst,\n input dqsfound_retry,\n // From phy_init\n input pi_dqs_found_start,\n input detect_pi_found_dqs,\n input prech_done,\n // DQSFOUND per Phaser_IN\n input [HIGHEST_LANE-1:0] pi_dqs_found_lanes,\n\n output reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal,\n \n // To phy_init\n output [5:0] rd_data_offset_0,\n output [5:0] rd_data_offset_1,\n output [5:0] rd_data_offset_2,\n output pi_dqs_found_rank_done,\n output pi_dqs_found_done,\n output reg pi_dqs_found_err,\n output [6*RANKS-1:0] rd_data_offset_ranks_0,\n output [6*RANKS-1:0] rd_data_offset_ranks_1,\n output [6*RANKS-1:0] rd_data_offset_ranks_2,\n output reg dqsfound_retry_done,\n output reg dqs_found_prech_req,\n //To MC\n output [6*RANKS-1:0] rd_data_offset_ranks_mc_0,\n output [6*RANKS-1:0] rd_data_offset_ranks_mc_1,\n output [6*RANKS-1:0] rd_data_offset_ranks_mc_2,\n\n input [8:0] po_counter_read_val,\n output rd_data_offset_cal_done,\n output fine_adjust_done,\n output [N_CTL_LANES-1:0] fine_adjust_lane_cnt,\n output reg ck_po_stg2_f_indec,\n output reg ck_po_stg2_f_en,\n output [255:0] dbg_dqs_found_cal\n );\n \n\n // For non-zero AL values\n localparam nAL = (AL == \"CL-1\") ? nCL - 1 : 0; \n\n // Adding the register dimm latency to write latency\n localparam CWL_M = (REG_CTRL == \"ON\") ? nCWL + nAL + 1 : nCWL + nAL;\n\n // Added to reduce simulation time\n localparam LATENCY_FACTOR = 13;\n \n localparam NUM_READS = (SIM_CAL_OPTION == \"NONE\") ? 7 : 1;\n \n localparam [19:0] DATA_PRESENT = {(DATA_CTL_B4[3] & BYTE_LANES_B4[3]),\n (DATA_CTL_B4[2] & BYTE_LANES_B4[2]),\n (DATA_CTL_B4[1] & BYTE_LANES_B4[1]),\n (DATA_CTL_B4[0] & BYTE_LANES_B4[0]),\n (DATA_CTL_B3[3] & BYTE_LANES_B3[3]),\n (DATA_CTL_B3[2] & BYTE_LANES_B3[2]),\n (DATA_CTL_B3[1] & BYTE_LANES_B3[1]),\n (DATA_CTL_B3[0] & BYTE_LANES_B3[0]),\n (DATA_CTL_B2[3] & BYTE_LANES_B2[3]),\n (DATA_CTL_B2[2] & BYTE_LANES_B2[2]),\n (DATA_CTL_B2[1] & BYTE_LANES_B2[1]),\n (DATA_CTL_B2[0] & BYTE_LANES_B2[0]),\n (DATA_CTL_B1[3] & BYTE_LANES_B1[3]),\n (DATA_CTL_B1[2] & BYTE_LANES_B1[2]),\n (DATA_CTL_B1[1] & BYTE_LANES_B1[1]),\n (DATA_CTL_B1[0] & BYTE_LANES_B1[0]),\n (DATA_CTL_B0[3] & BYTE_LANES_B0[3]),\n (DATA_CTL_B0[2] & BYTE_LANES_B0[2]),\n (DATA_CTL_B0[1] & BYTE_LANES_B0[1]),\n (DATA_CTL_B0[0] & BYTE_LANES_B0[0])};\n \n localparam FINE_ADJ_IDLE = 4'h0;\n localparam RST_POSTWAIT = 4'h1;\n localparam RST_POSTWAIT1 = 4'h2;\n localparam RST_WAIT = 4'h3;\n localparam FINE_ADJ_INIT = 4'h4;\n localparam FINE_INC = 4'h5;\n localparam FINE_INC_WAIT = 4'h6;\n localparam FINE_INC_PREWAIT = 4'h7;\n localparam DETECT_PREWAIT = 4'h8;\n localparam DETECT_DQSFOUND = 4'h9;\n localparam PRECH_WAIT = 4'hA;\n localparam FINE_DEC = 4'hB;\n localparam FINE_DEC_WAIT = 4'hC;\n localparam FINE_DEC_PREWAIT = 4'hD;\n localparam FINAL_WAIT = 4'hE;\n localparam FINE_ADJ_DONE = 4'hF;\n \n\n integer k,l,m,n,p,q,r,s;\n \n reg dqs_found_start_r;\n reg [6*HIGHEST_BANK-1:0] rd_byte_data_offset[0:RANKS-1];\n reg rank_done_r;\n reg rank_done_r1;\n reg dqs_found_done_r;\n (* ASYNC_REG = \"TRUE\" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r1;\n (* ASYNC_REG = \"TRUE\" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r2;\n (* ASYNC_REG = \"TRUE\" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r3;\n reg init_dqsfound_done_r;\n reg init_dqsfound_done_r1;\n reg init_dqsfound_done_r2;\n reg init_dqsfound_done_r3;\n reg init_dqsfound_done_r4;\n reg init_dqsfound_done_r5;\n reg [1:0] rnk_cnt_r;\n reg [2:0 ] final_do_index[0:RANKS-1];\n reg [5:0 ] final_do_max[0:RANKS-1];\n reg [6*HIGHEST_BANK-1:0] final_data_offset[0:RANKS-1];\n reg [6*HIGHEST_BANK-1:0] final_data_offset_mc[0:RANKS-1];\n reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r;\n reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r1;\n reg [10*HIGHEST_BANK-1:0] retry_cnt;\n reg dqsfound_retry_r1;\n wire [4*HIGHEST_BANK-1:0] pi_dqs_found_lanes_int;\n reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank;\n reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank_r;\n reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank;\n reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank_r;\n reg [HIGHEST_BANK-1:0] pi_dqs_found_err_r;\n \n // CK/Control byte lanes fine adjust stage\n reg fine_adjust;\n reg [N_CTL_LANES-1:0] ctl_lane_cnt;\n reg [3:0] fine_adj_state_r;\n reg fine_adjust_done_r;\n reg rst_dqs_find;\n reg rst_dqs_find_r1;\n reg rst_dqs_find_r2;\n reg [5:0] init_dec_cnt;\n reg [5:0] dec_cnt;\n reg [5:0] inc_cnt;\n reg final_dec_done;\n reg init_dec_done;\n reg first_fail_detect;\n reg second_fail_detect;\n reg [5:0] first_fail_taps;\n reg [5:0] second_fail_taps;\n reg [5:0] stable_pass_cnt;\n reg [3:0] detect_rd_cnt;\n \n\n \n \n //***************************************************************************\n // Debug signals\n //\n //***************************************************************************\n assign dbg_dqs_found_cal[5:0] = first_fail_taps;\n assign dbg_dqs_found_cal[11:6] = second_fail_taps;\n assign dbg_dqs_found_cal[12] = first_fail_detect;\n assign dbg_dqs_found_cal[13] = second_fail_detect;\n assign dbg_dqs_found_cal[14] = fine_adjust_done_r;\n \n\n assign pi_dqs_found_rank_done = rank_done_r;\n assign pi_dqs_found_done = dqs_found_done_r;\n\n generate\n genvar rnk_cnt;\n if (HIGHEST_BANK == 3) begin // Three Bank Interface\n for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop\n assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];\n assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6];\n assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][17:12];\n assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];\n assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6];\n assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][17:12];\n end\n end else if (HIGHEST_BANK == 2) begin // Two Bank Interface\n for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop\n assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];\n assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6];\n assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0;\n assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];\n assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6];\n assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0;\n end\n end else begin // Single Bank Interface\n for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop\n assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];\n assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = 'd0;\n assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0;\n assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];\n assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = 'd0;\n assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0;\n end\n end\n endgenerate\n \n // final_data_offset is used during write calibration and during\n // normal operation. One rd_data_offset value per rank for entire\n // interface\n generate\n if (HIGHEST_BANK == 3) begin // Three I/O Bank interface\n assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :\n final_data_offset[rnk_cnt_r][0+:6];\n assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] :\n final_data_offset[rnk_cnt_r][6+:6];\n assign rd_data_offset_2 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][12+:6] :\n final_data_offset[rnk_cnt_r][12+:6];\n end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface\n assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :\n final_data_offset[rnk_cnt_r][0+:6];\n assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] :\n final_data_offset[rnk_cnt_r][6+:6];\n assign rd_data_offset_2 = 'd0;\n end else begin\n assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :\n final_data_offset[rnk_cnt_r][0+:6];\n assign rd_data_offset_1 = 'd0;\n assign rd_data_offset_2 = 'd0;\n end\n endgenerate\n \n assign rd_data_offset_cal_done = init_dqsfound_done_r;\n assign fine_adjust_lane_cnt = ctl_lane_cnt;\n \n //**************************************************************************\n // DQSFOUND all and any generation\n // pi_dqs_found_all_bank[x] asserted when all Phaser_INs in Bankx are\n // asserted\n // pi_dqs_found_any_bank[x] asserted when at least one Phaser_IN in Bankx\n // is asserted\n //**************************************************************************\n\n generate\n if ((HIGHEST_LANE == 4) || (HIGHEST_LANE == 8) || (HIGHEST_LANE == 12))\n assign pi_dqs_found_lanes_int = pi_dqs_found_lanes_r3;\n else if ((HIGHEST_LANE == 3) || (HIGHEST_LANE == 7) || (HIGHEST_LANE == 11))\n assign pi_dqs_found_lanes_int = {1'b0, pi_dqs_found_lanes_r3};\n else if ((HIGHEST_LANE == 6) || (HIGHEST_LANE == 10))\n assign pi_dqs_found_lanes_int = {2'b00, pi_dqs_found_lanes_r3};\n else if ((HIGHEST_LANE == 5) || (HIGHEST_LANE == 9))\n assign pi_dqs_found_lanes_int = {3'b000, pi_dqs_found_lanes_r3};\n endgenerate\n \n always @(posedge clk) begin\n if (rst) begin\n for (k = 0; k < HIGHEST_BANK; k = k + 1) begin: rst_pi_dqs_found\n pi_dqs_found_all_bank[k] <= #TCQ 'b0;\n pi_dqs_found_any_bank[k] <= #TCQ 'b0;\n end\n end else if (pi_dqs_found_start) begin\n for (p = 0; p < HIGHEST_BANK; p = p +1) begin: assign_pi_dqs_found\n pi_dqs_found_all_bank[p] <= #TCQ (!DATA_PRESENT[4*p+0] | pi_dqs_found_lanes_int[4*p+0]) &\n (!DATA_PRESENT[4*p+1] | pi_dqs_found_lanes_int[4*p+1]) &\n (!DATA_PRESENT[4*p+2] | pi_dqs_found_lanes_int[4*p+2]) &\n (!DATA_PRESENT[4*p+3] | pi_dqs_found_lanes_int[4*p+3]);\n pi_dqs_found_any_bank[p] <= #TCQ (DATA_PRESENT[4*p+0] & pi_dqs_found_lanes_int[4*p+0]) |\n (DATA_PRESENT[4*p+1] & pi_dqs_found_lanes_int[4*p+1]) |\n (DATA_PRESENT[4*p+2] & pi_dqs_found_lanes_int[4*p+2]) |\n (DATA_PRESENT[4*p+3] & pi_dqs_found_lanes_int[4*p+3]);\n end\n end\n end\n\n \n always @(posedge clk) begin\n pi_dqs_found_all_bank_r <= #TCQ pi_dqs_found_all_bank;\n pi_dqs_found_any_bank_r <= #TCQ pi_dqs_found_any_bank;\n end\n \n//*****************************************************************************\n// Counter to increase number of 4 back-to-back reads per rd_data_offset and\n// per CK/A/C tap value\n//*****************************************************************************\n\n always @(posedge clk) begin\n if (rst || (detect_rd_cnt == 'd0))\n\t detect_rd_cnt <= #TCQ NUM_READS;\n\telse if (detect_pi_found_dqs && (detect_rd_cnt > 'd0))\n\t detect_rd_cnt <= #TCQ detect_rd_cnt - 1;\n end\n \n \n //**************************************************************************\n // Adjust Phaser_Out stage 2 taps on CK/Address/Command/Controls \n // \n //**************************************************************************\n \n assign fine_adjust_done = fine_adjust_done_r;\n \n always @(posedge clk) begin\n rst_dqs_find_r1 <= #TCQ rst_dqs_find;\n\t rst_dqs_find_r2 <= #TCQ rst_dqs_find_r1;\n end\n \n always @(posedge clk) begin\n if(rst)begin\n fine_adjust <= #TCQ 1'b0;\n ctl_lane_cnt <= #TCQ 'd0;\n fine_adj_state_r <= #TCQ FINE_ADJ_IDLE;\n fine_adjust_done_r <= #TCQ 1'b0;\n ck_po_stg2_f_indec <= #TCQ 1'b0;\n ck_po_stg2_f_en <= #TCQ 1'b0;\n rst_dqs_find <= #TCQ 1'b0;\n init_dec_cnt <= #TCQ 'd31;\n dec_cnt <= #TCQ 'd0;\n inc_cnt <= #TCQ 'd0;\n init_dec_done <= #TCQ 1'b0;\n final_dec_done <= #TCQ 1'b0;\n first_fail_detect <= #TCQ 1'b0;\n second_fail_detect <= #TCQ 1'b0;\n first_fail_taps <= #TCQ 'd0;\n second_fail_taps <= #TCQ 'd0;\n stable_pass_cnt <= #TCQ 'd0;\n dqs_found_prech_req<= #TCQ 1'b0;\n end else begin\n case (fine_adj_state_r)\n \n FINE_ADJ_IDLE: begin\n if (init_dqsfound_done_r5) begin\n if (SIM_CAL_OPTION == \"FAST_CAL\") begin\n fine_adjust <= #TCQ 1'b1;\n fine_adj_state_r <= #TCQ FINE_ADJ_DONE;\n rst_dqs_find <= #TCQ 1'b0;\n end else begin\n fine_adjust <= #TCQ 1'b1;\n fine_adj_state_r <= #TCQ RST_WAIT;\n rst_dqs_find <= #TCQ 1'b1;\n end\n end\n end\n \n RST_WAIT: begin\n if (~(|pi_dqs_found_any_bank) && rst_dqs_find_r2) begin\n rst_dqs_find <= #TCQ 1'b0;\n if (|init_dec_cnt)\n fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;\n else if (final_dec_done)\n fine_adj_state_r <= #TCQ FINE_ADJ_DONE;\n else\n fine_adj_state_r <= #TCQ RST_POSTWAIT;\n end\n end\n \n RST_POSTWAIT: begin\n fine_adj_state_r <= #TCQ RST_POSTWAIT1;\n end\n \n RST_POSTWAIT1: begin\n fine_adj_state_r <= #TCQ FINE_ADJ_INIT;\n end\n \n FINE_ADJ_INIT: begin\n //if (detect_pi_found_dqs && (inc_cnt < 'd63))\n fine_adj_state_r <= #TCQ FINE_INC;\n end\n \n FINE_INC: begin\n fine_adj_state_r <= #TCQ FINE_INC_WAIT;\n ck_po_stg2_f_indec <= #TCQ 1'b1;\n ck_po_stg2_f_en <= #TCQ 1'b1;\n if (ctl_lane_cnt == N_CTL_LANES-1)\n inc_cnt <= #TCQ inc_cnt + 1;\n end\n \n FINE_INC_WAIT: begin\n ck_po_stg2_f_indec <= #TCQ 1'b0;\n ck_po_stg2_f_en <= #TCQ 1'b0;\n if (ctl_lane_cnt != N_CTL_LANES-1) begin\n ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;\n fine_adj_state_r <= #TCQ FINE_INC_PREWAIT;\n end else if (ctl_lane_cnt == N_CTL_LANES-1) begin\n ctl_lane_cnt <= #TCQ 'd0;\n fine_adj_state_r <= #TCQ DETECT_PREWAIT;\n end\n end\n \n FINE_INC_PREWAIT: begin\n fine_adj_state_r <= #TCQ FINE_INC;\n end\n \n DETECT_PREWAIT: begin\n if (detect_pi_found_dqs && (detect_rd_cnt == 'd1))\n fine_adj_state_r <= #TCQ DETECT_DQSFOUND;\n\t\t\t else\n\t\t\t fine_adj_state_r <= #TCQ DETECT_PREWAIT;\n end\n \n DETECT_DQSFOUND: begin\n if (detect_pi_found_dqs && ~(&pi_dqs_found_all_bank)) begin\n stable_pass_cnt <= #TCQ 'd0;\n if (~first_fail_detect && (inc_cnt == 'd63)) begin\n // First failing tap detected at 63 taps\n // then decrement to 31\n first_fail_detect <= #TCQ 1'b1;\n first_fail_taps <= #TCQ inc_cnt;\n fine_adj_state_r <= #TCQ FINE_DEC;\n dec_cnt <= #TCQ 'd32;\n end else if (~first_fail_detect && (inc_cnt > 'd30) && (stable_pass_cnt > 'd29)) begin\n // First failing tap detected at greater than 30 taps\n // then stop looking for second edge and decrement\n first_fail_detect <= #TCQ 1'b1;\n first_fail_taps <= #TCQ inc_cnt;\n fine_adj_state_r <= #TCQ FINE_DEC;\n dec_cnt <= #TCQ (inc_cnt>>1) + 1;\t\t\t\t \n\t\t\t end else if (~first_fail_detect || (first_fail_detect && (stable_pass_cnt < 'd30) && (inc_cnt <= 'd32))) begin\n // First failing tap detected, continue incrementing\n // until either second failing tap detected or 63\n first_fail_detect <= #TCQ 1'b1;\n first_fail_taps <= #TCQ inc_cnt;\n rst_dqs_find <= #TCQ 1'b1;\n if ((inc_cnt == 'd12) || (inc_cnt == 'd24)) begin\n dqs_found_prech_req <= #TCQ 1'b1;\n fine_adj_state_r <= #TCQ PRECH_WAIT;\n end else\n fine_adj_state_r <= #TCQ RST_WAIT;\n end else if (first_fail_detect && (inc_cnt > 'd32) && (inc_cnt < 'd63) && (stable_pass_cnt < 'd30)) begin\n // Consecutive 30 taps of passing region was not found\n // continue incrementing\n first_fail_detect <= #TCQ 1'b1;\n first_fail_taps <= #TCQ inc_cnt;\n rst_dqs_find <= #TCQ 1'b1;\n if ((inc_cnt == 'd36) || (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin\n dqs_found_prech_req <= #TCQ 1'b1;\n fine_adj_state_r <= #TCQ PRECH_WAIT;\n end else\n fine_adj_state_r <= #TCQ RST_WAIT;\n end else if (first_fail_detect && (inc_cnt == 'd63)) begin\n if (stable_pass_cnt < 'd30) begin\n // Consecutive 30 taps of passing region was not found\n // from tap 0 to 63 so decrement back to 31\n first_fail_detect <= #TCQ 1'b1;\n first_fail_taps <= #TCQ inc_cnt;\n fine_adj_state_r <= #TCQ FINE_DEC;\n dec_cnt <= #TCQ 'd32;\n end else begin\n // Consecutive 30 taps of passing region was found\n // between first_fail_taps and 63\n fine_adj_state_r <= #TCQ FINE_DEC;\n dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);\n end\n end else begin\n // Second failing tap detected, decrement to center of\n // failing taps\n second_fail_detect <= #TCQ 1'b1;\n second_fail_taps <= #TCQ inc_cnt;\n dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);\n fine_adj_state_r <= #TCQ FINE_DEC;\n end\n end else if (detect_pi_found_dqs && (&pi_dqs_found_all_bank)) begin\n stable_pass_cnt <= #TCQ stable_pass_cnt + 1;\n if ((inc_cnt == 'd12) || (inc_cnt == 'd24) || (inc_cnt == 'd36) || \n (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin\n dqs_found_prech_req <= #TCQ 1'b1;\n fine_adj_state_r <= #TCQ PRECH_WAIT;\n end else if (inc_cnt < 'd63) begin\n rst_dqs_find <= #TCQ 1'b1;\n fine_adj_state_r <= #TCQ RST_WAIT;\n end else begin\n fine_adj_state_r <= #TCQ FINE_DEC;\n if (~first_fail_detect || (first_fail_taps > 'd33))\n // No failing taps detected, decrement by 31\n dec_cnt <= #TCQ 'd32;\n //else if (first_fail_detect && (stable_pass_cnt > 'd28))\n // // First failing tap detected between 0 and 34\n // // decrement midpoint between 63 and failing tap\n // dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);\n else\n // First failing tap detected\n // decrement to midpoint between 63 and failing tap\n dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);\n end\n end\n end\n \n PRECH_WAIT: begin\n if (prech_done) begin\n dqs_found_prech_req <= #TCQ 1'b0;\n rst_dqs_find <= #TCQ 1'b1;\n fine_adj_state_r <= #TCQ RST_WAIT;\n end\n end\n \n \n FINE_DEC: begin\n fine_adj_state_r <= #TCQ FINE_DEC_WAIT;\n ck_po_stg2_f_indec <= #TCQ 1'b0;\n ck_po_stg2_f_en <= #TCQ 1'b1;\n if ((ctl_lane_cnt == N_CTL_LANES-1) && (init_dec_cnt > 'd0))\n init_dec_cnt <= #TCQ init_dec_cnt - 1;\n else if ((ctl_lane_cnt == N_CTL_LANES-1) && (dec_cnt > 'd0))\n dec_cnt <= #TCQ dec_cnt - 1;\n end\n \n FINE_DEC_WAIT: begin\n ck_po_stg2_f_indec <= #TCQ 1'b0;\n ck_po_stg2_f_en <= #TCQ 1'b0;\n if (ctl_lane_cnt != N_CTL_LANES-1) begin\n ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;\n fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;\n end else if (ctl_lane_cnt == N_CTL_LANES-1) begin\n ctl_lane_cnt <= #TCQ 'd0;\n if ((dec_cnt > 'd0) || (init_dec_cnt > 'd0))\n fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;\n else begin\n fine_adj_state_r <= #TCQ FINAL_WAIT;\n if ((init_dec_cnt == 'd0) && ~init_dec_done)\n init_dec_done <= #TCQ 1'b1;\n else\n final_dec_done <= #TCQ 1'b1;\n end\n end\n end\n \n FINE_DEC_PREWAIT: begin\n fine_adj_state_r <= #TCQ FINE_DEC;\n end\n \n FINAL_WAIT: begin\n rst_dqs_find <= #TCQ 1'b1;\n fine_adj_state_r <= #TCQ RST_WAIT;\n end\n \n FINE_ADJ_DONE: begin\n if (&pi_dqs_found_all_bank) begin\n fine_adjust_done_r <= #TCQ 1'b1;\n rst_dqs_find <= #TCQ 1'b0;\n fine_adj_state_r <= #TCQ FINE_ADJ_DONE;\n end\n end\n \n endcase\n end\n end\n \n\n \n \n//***************************************************************************** \n \n\n always@(posedge clk)\n dqs_found_start_r <= #TCQ pi_dqs_found_start;\n \n\n always @(posedge clk) begin\n if (rst)\n rnk_cnt_r <= #TCQ 2'b00;\n else if (init_dqsfound_done_r)\n rnk_cnt_r <= #TCQ rnk_cnt_r;\n else if (rank_done_r)\n rnk_cnt_r <= #TCQ rnk_cnt_r + 1;\n end\n \n //*****************************************************************\n // Read data_offset calibration done signal\n //*****************************************************************\n \n always @(posedge clk) begin\n if (rst || (|pi_rst_stg1_cal_r))\n init_dqsfound_done_r <= #TCQ 1'b0;\n else if (&pi_dqs_found_all_bank) begin\n if (rnk_cnt_r == RANKS-1)\n init_dqsfound_done_r <= #TCQ 1'b1;\n else\n init_dqsfound_done_r <= #TCQ 1'b0;\n end\n end\n \n always @(posedge clk) begin\n if (rst ||\n (init_dqsfound_done_r && (rnk_cnt_r == RANKS-1)))\n rank_done_r <= #TCQ 1'b0;\n else if (&pi_dqs_found_all_bank && ~(&pi_dqs_found_all_bank_r))\n rank_done_r <= #TCQ 1'b1;\n else\n rank_done_r <= #TCQ 1'b0;\n end\n \n always @(posedge clk) begin\n pi_dqs_found_lanes_r1 <= #TCQ pi_dqs_found_lanes;\n pi_dqs_found_lanes_r2 <= #TCQ pi_dqs_found_lanes_r1;\n pi_dqs_found_lanes_r3 <= #TCQ pi_dqs_found_lanes_r2;\n init_dqsfound_done_r1 <= #TCQ init_dqsfound_done_r;\n init_dqsfound_done_r2 <= #TCQ init_dqsfound_done_r1;\n init_dqsfound_done_r3 <= #TCQ init_dqsfound_done_r2;\n init_dqsfound_done_r4 <= #TCQ init_dqsfound_done_r3;\n init_dqsfound_done_r5 <= #TCQ init_dqsfound_done_r4;\n rank_done_r1 <= #TCQ rank_done_r;\n dqsfound_retry_r1 <= #TCQ dqsfound_retry;\n end\n\n \n always @(posedge clk) begin\n if (rst)\n dqs_found_done_r <= #TCQ 1'b0;\n else if (&pi_dqs_found_all_bank && (rnk_cnt_r == RANKS-1) && init_dqsfound_done_r1 &&\n (fine_adj_state_r == FINE_ADJ_DONE))\n dqs_found_done_r <= #TCQ 1'b1;\n else\n dqs_found_done_r <= #TCQ 1'b0;\n end\n \n\n generate\n if (HIGHEST_BANK == 3) begin // Three I/O Bank interface\n\n // Reset read data offset calibration in all DQS Phaser_INs\n // in a Bank after the read data offset value for a rank is determined\n // or if within a Bank DQSFOUND is not asserted for all DQSs\n always @(posedge clk) begin\n if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)\n pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;\n else if ((pi_dqs_found_start && ~dqs_found_start_r) ||\n //(dqsfound_retry[0]) ||\n (pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||\n (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))\n pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;\n end\n\n always @(posedge clk) begin\n if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust)\n pi_rst_stg1_cal_r[1] <= #TCQ 1'b0;\n else if ((pi_dqs_found_start && ~dqs_found_start_r) ||\n //(dqsfound_retry[1]) ||\n (pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) ||\n (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))\n pi_rst_stg1_cal_r[1] <= #TCQ 1'b1;\n end\n\n always @(posedge clk) begin\n if (rst || pi_rst_stg1_cal_r1[2] || fine_adjust)\n pi_rst_stg1_cal_r[2] <= #TCQ 1'b0;\n else if ((pi_dqs_found_start && ~dqs_found_start_r) ||\n //(dqsfound_retry[2]) ||\n (pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2]) ||\n (rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1)))\n pi_rst_stg1_cal_r[2] <= #TCQ 1'b1;\n end\n \n always @(posedge clk) begin\n if (rst || fine_adjust)\n pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;\n else if (pi_rst_stg1_cal_r[0])\n pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;\n else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])\n pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;\n end\n \n always @(posedge clk) begin\n if (rst || fine_adjust)\n pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;\n else if (pi_rst_stg1_cal_r[1])\n pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1;\n else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1])\n pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;\n end\n \n always @(posedge clk) begin\n if (rst || fine_adjust)\n pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0;\n else if (pi_rst_stg1_cal_r[2])\n pi_rst_stg1_cal_r1[2] <= #TCQ 1'b1;\n else if (~pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2])\n pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0;\n end\n\n //*****************************************************************************\n // Retry counter to track number of DQSFOUND retries\n //*****************************************************************************\n \n always @(posedge clk) begin\n if (rst || rank_done_r)\n retry_cnt[0+:10] <= #TCQ 'b0;\n else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) &&\n ~pi_dqs_found_all_bank[0])\n retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;\n else\n retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];\n end\n\t \n\t always @(posedge clk) begin\n if (rst || rank_done_r)\n retry_cnt[10+:10] <= #TCQ 'b0;\n else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)) &&\n ~pi_dqs_found_all_bank[1])\n retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1;\n else\n retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10];\n end\n\t \n\t always @(posedge clk) begin\n if (rst || rank_done_r)\n retry_cnt[20+:10] <= #TCQ 'b0;\n else if ((rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1)) &&\n ~pi_dqs_found_all_bank[2])\n retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10] + 1;\n else\n retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10];\n end\n\t \n // Error generation in case pi_dqs_found_all_bank\n // is not asserted\n always @(posedge clk) begin\n if (rst)\n pi_dqs_found_err_r[0] <= #TCQ 1'b0;\n else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&\n (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))\n pi_dqs_found_err_r[0] <= #TCQ 1'b1;\n end\n\n always @(posedge clk) begin\n if (rst)\n pi_dqs_found_err_r[1] <= #TCQ 1'b0;\n else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) &&\n (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))\n pi_dqs_found_err_r[1] <= #TCQ 1'b1;\n end\n\n always @(posedge clk) begin\n if (rst)\n pi_dqs_found_err_r[2] <= #TCQ 1'b0;\n else if (~pi_dqs_found_all_bank[2] && (retry_cnt[20+:10] == NUM_DQSFOUND_CAL) &&\n (rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1)))\n pi_dqs_found_err_r[2] <= #TCQ 1'b1;\n end\n\n // Read data offset value for all DQS in a Bank\n always @(posedge clk) begin\n if (rst) begin\n for (q = 0; q < RANKS; q = q + 1) begin: three_bank0_rst_loop\n rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;\n end\n end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||\n (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))\n rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;\n else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&\n //(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL -1)) &&\n (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)\n rd_byte_data_offset[rnk_cnt_r][0+:6]\n <= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] - 1;\n end\n\n always @(posedge clk) begin\n if (rst) begin\n for (r = 0; r < RANKS; r = r + 1) begin: three_bank1_rst_loop\n rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;\n end\n end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||\n (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))\n rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;\n else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] &&\n //(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL -1)) &&\n (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)\n rd_byte_data_offset[rnk_cnt_r][6+:6]\n <= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] - 1;\n end\n\n always @(posedge clk) begin\n if (rst) begin\n for (s = 0; s < RANKS; s = s + 1) begin: three_bank2_rst_loop\n rd_byte_data_offset[s][12+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;\n end\n end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||\n (rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1)))\n rd_byte_data_offset[rnk_cnt_r][12+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;\n else if (dqs_found_start_r && ~pi_dqs_found_all_bank[2] &&\n //(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL -1)) &&\n (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)\n rd_byte_data_offset[rnk_cnt_r][12+:6]\n <= #TCQ rd_byte_data_offset[rnk_cnt_r][12+:6] - 1;\n end\n\n//*****************************************************************************\n// Two I/O Bank Interface\n//*****************************************************************************\n end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface\n\n // Reset read data offset calibration in all DQS Phaser_INs\n // in a Bank after the read data offset value for a rank is determined\n // or if within a Bank DQSFOUND is not asserted for all DQSs\n always @(posedge clk) begin\n if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)\n pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;\n else if ((pi_dqs_found_start && ~dqs_found_start_r) ||\n //(dqsfound_retry[0]) ||\n (pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||\n (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))\n pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;\n end\n\n always @(posedge clk) begin\n if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust)\n pi_rst_stg1_cal_r[1] <= #TCQ 1'b0;\n else if ((pi_dqs_found_start && ~dqs_found_start_r) ||\n //(dqsfound_retry[1]) ||\n (pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) ||\n (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))\n pi_rst_stg1_cal_r[1] <= #TCQ 1'b1;\n end\n \n always @(posedge clk) begin\n if (rst || fine_adjust)\n pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;\n else if (pi_rst_stg1_cal_r[0])\n pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;\n else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])\n pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;\n end\n \n always @(posedge clk) begin\n if (rst || fine_adjust)\n pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;\n else if (pi_rst_stg1_cal_r[1])\n pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1;\n else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1])\n pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;\n end\n\n //*****************************************************************************\n // Retry counter to track number of DQSFOUND retries\n //*****************************************************************************\n \n always @(posedge clk) begin\n if (rst || rank_done_r)\n retry_cnt[0+:10] <= #TCQ 'b0;\n else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) &&\n ~pi_dqs_found_all_bank[0])\n retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;\n else\n retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];\n end\n\t \n\t always @(posedge clk) begin\n if (rst || rank_done_r)\n retry_cnt[10+:10] <= #TCQ 'b0;\n else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)) &&\n ~pi_dqs_found_all_bank[1])\n retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1;\n else\n retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10];\n end\n\n // Error generation in case pi_dqs_found_all_bank\n // is not asserted\n\t always @(posedge clk) begin\n if (rst)\n pi_dqs_found_err_r[0] <= #TCQ 1'b0;\n else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&\n (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))\n pi_dqs_found_err_r[0] <= #TCQ 1'b1;\n end\n\n always @(posedge clk) begin\n if (rst)\n pi_dqs_found_err_r[1] <= #TCQ 1'b0;\n else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) &&\n (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))\n pi_dqs_found_err_r[1] <= #TCQ 1'b1;\n end\n\n\n // Read data offset value for all DQS in a Bank\n always @(posedge clk) begin\n if (rst) begin\n for (q = 0; q < RANKS; q = q + 1) begin: two_bank0_rst_loop\n rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;\n end\n end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||\n (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))\n rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;\n else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&\n //(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL -1)) &&\n (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)\n rd_byte_data_offset[rnk_cnt_r][0+:6]\n <= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] - 1;\n end\n\n always @(posedge clk) begin\n if (rst) begin\n for (r = 0; r < RANKS; r = r + 1) begin: two_bank1_rst_loop\n rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;\n end\n end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||\n (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))\n rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;\n else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] &&\n //(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL -1)) &&\n (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)\n rd_byte_data_offset[rnk_cnt_r][6+:6]\n <= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] - 1;\n end\n//*****************************************************************************\n// One I/O Bank Interface\n//*****************************************************************************\n end else begin // One I/O Bank Interface\n\n // Read data offset value for all DQS in Bank0\n always @(posedge clk) begin\n if (rst) begin\n for (l = 0; l < RANKS; l = l + 1) begin: bank_rst_loop\n rd_byte_data_offset[l] <= #TCQ nCL + nAL + LATENCY_FACTOR;\n end\n end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||\n (rd_byte_data_offset[rnk_cnt_r] < (nCL + nAL - 1)))\n rd_byte_data_offset[rnk_cnt_r] <= #TCQ nCL + nAL + LATENCY_FACTOR;\n else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&\n //(rd_byte_data_offset[rnk_cnt_r] > (nCL + nAL -1)) &&\n (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)\n rd_byte_data_offset[rnk_cnt_r]\n <= #TCQ rd_byte_data_offset[rnk_cnt_r] - 1;\n end\n\n // Reset read data offset calibration in all DQS Phaser_INs\n // in a Bank after the read data offset value for a rank is determined\n // or if within a Bank DQSFOUND is not asserted for all DQSs\n always @(posedge clk) begin\n if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)\n pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;\n else if ((pi_dqs_found_start && ~dqs_found_start_r) ||\n //(dqsfound_retry[0]) ||\n (pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||\n (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))\n pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;\n end\n \n always @(posedge clk) begin\n if (rst || fine_adjust)\n pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;\n else if (pi_rst_stg1_cal_r[0])\n pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;\n else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])\n pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;\n end\n\n //*****************************************************************************\n // Retry counter to track number of DQSFOUND retries\n //*****************************************************************************\n \n always @(posedge clk) begin\n if (rst || rank_done_r)\n retry_cnt[0+:10] <= #TCQ 'b0;\n else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) &&\n ~pi_dqs_found_all_bank[0])\n retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;\n else\n retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];\n end\n\n // Error generation in case pi_dqs_found_all_bank\n // is not asserted even with 3 dqfound retries\n always @(posedge clk) begin\n if (rst)\n pi_dqs_found_err_r[0] <= #TCQ 1'b0;\n else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&\n (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))\n pi_dqs_found_err_r[0] <= #TCQ 1'b1;\n end\n\n end\n endgenerate\n \n always @(posedge clk) begin\n if (rst)\n pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b0}};\n else if (rst_dqs_find)\n pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b1}};\n else\n pi_rst_stg1_cal <= #TCQ pi_rst_stg1_cal_r;\n end\n \n\n\n // Final read data offset value to be used during write calibration and\n // normal operation\n generate\n genvar i;\n genvar j;\n for (i = 0; i < RANKS; i = i + 1) begin: rank_final_loop\n reg [5:0] final_do_cand [RANKS-1:0];\n // combinatorially select the candidate offset for the bank\n // indexed by final_do_index\n if (HIGHEST_BANK == 3) begin\n always @(*) begin\n case (final_do_index[i])\n\t 3'b000: final_do_cand[i] = final_data_offset[i][5:0];\n\t 3'b001: final_do_cand[i] = final_data_offset[i][11:6];\n\t 3'b010: final_do_cand[i] = final_data_offset[i][17:12];\n\t default: final_do_cand[i] = 'd0;\n\t endcase\n end\n end else if (HIGHEST_BANK == 2) begin\n always @(*) begin\n case (final_do_index[i])\n\t 3'b000: final_do_cand[i] = final_data_offset[i][5:0];\n\t 3'b001: final_do_cand[i] = final_data_offset[i][11:6];\n\t 3'b010: final_do_cand[i] = 'd0;\n\t default: final_do_cand[i] = 'd0;\n\t endcase\n end\n end else begin\n always @(*) begin\n case (final_do_index[i])\n\t 3'b000: final_do_cand[i] = final_data_offset[i][5:0];\n\t 3'b001: final_do_cand[i] = 'd0;\n\t 3'b010: final_do_cand[i] = 'd0;\n\t default: final_do_cand[i] = 'd0;\n\t endcase\n end\n end\n \n always @(posedge clk) begin\n if (rst) \n\t final_do_max[i] <= #TCQ 0;\n\t else begin\n\t final_do_max[i] <= #TCQ final_do_max[i]; // default\n case (final_do_index[i])\n\t 3'b000: if ( | DATA_PRESENT[3:0]) \n\t if (final_do_max[i] < final_do_cand[i])\n\t if (CWL_M % 2) // odd latency CAS slot 1\n\t\t final_do_max[i] <= #TCQ final_do_cand[i] - 1;\n\t\t else\n\t\t final_do_max[i] <= #TCQ final_do_cand[i];\n\t 3'b001: if ( | DATA_PRESENT[7:4]) \n\t if (final_do_max[i] < final_do_cand[i])\n\t\t if (CWL_M % 2) // odd latency CAS slot 1\n\t\t final_do_max[i] <= #TCQ final_do_cand[i] - 1;\n\t\t else\n\t\t final_do_max[i] <= #TCQ final_do_cand[i];\n\t 3'b010: if ( | DATA_PRESENT[11:8]) \n\t if (final_do_max[i] < final_do_cand[i])\n\t\t if (CWL_M % 2) // odd latency CAS slot 1\n\t\t final_do_max[i] <= #TCQ final_do_cand[i] - 1;\n\t\t else\n\t\t final_do_max[i] <= #TCQ final_do_cand[i];\n default:\n\t final_do_max[i] <= #TCQ final_do_max[i];\n\t endcase\n\t end\n\tend\n\n\talways @(posedge clk) \n\t if (rst) begin\n\t final_do_index[i] <= #TCQ 0;\n\t end\n\t else begin\n\t final_do_index[i] <= #TCQ final_do_index[i] + 1;\n\t end\n\n for (j = 0; j < HIGHEST_BANK; j = j + 1) begin: bank_final_loop\n \n always @(posedge clk) begin\n if (rst) begin\n final_data_offset[i][6*j+:6] <= #TCQ 'b0;\n\t end\n else begin\n\t //if (dqsfound_retry[j])\n // final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];\n //else \n if (init_dqsfound_done_r && ~init_dqsfound_done_r1) begin\n\t if ( DATA_PRESENT [ j*4+:4] != 0) begin // has a data lane\n final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];\n if (CWL_M % 2) // odd latency CAS slot 1\n final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6] - 1;\n else // even latency CAS slot 0\n final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];\n end \n\t end\n else if (init_dqsfound_done_r5 ) begin\n\t if ( DATA_PRESENT [ j*4+:4] == 0) begin // all control lanes\n final_data_offset[i][6*j+:6] <= #TCQ final_do_max[i];\n final_data_offset_mc[i][6*j+:6] <= #TCQ final_do_max[i];\n end\t\n end\n\t end\n end\n end\n end\n endgenerate\n\n \n // Error generation in case pi_found_dqs signal from Phaser_IN\n // is not asserted when a common rddata_offset value is used\n \n always @(posedge clk) begin\n pi_dqs_found_err <= #TCQ |pi_dqs_found_err_r;\n end\n \n\n \nendmodule\n \n \n \n \n\n \n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_dqs_found_cal_hr.v", "content": "//*****************************************************************************\n// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor: Xilinx\n// \\ \\ \\/ Version:\n// \\ \\ Application: MIG\n// / / Filename: ddr_phy_dqs_found_cal.v\n// /___/ /\\ Date Last Modified: $Date: 2011/06/02 08:35:08 $\n// \\ \\ / \\ Date Created:\n// \\___\\/\\___\\\n//\n//Device: 7 Series\n//Design Name: DDR3 SDRAM\n//Purpose:\n// Read leveling calibration logic\n// NOTES:\n// 1. Phaser_In DQSFOUND calibration\n//Reference:\n//Revision History:\n//*****************************************************************************\n\n/******************************************************************************\n**$Id: ddr_phy_dqs_found_cal.v,v 1.1 2011/06/02 08:35:08 mishra Exp $\n**$Date: 2011/06/02 08:35:08 $\n**$Author: \n**$Revision:\n**$Source: \n******************************************************************************/\n\n`timescale 1ps/1ps\n\nmodule mig_7series_v4_0_ddr_phy_dqs_found_cal_hr #\n (\n parameter TCQ = 100, // clk->out delay (sim only)\n parameter nCK_PER_CLK = 2, // # of memory clocks per CLK\n parameter nCL = 5, // Read CAS latency\n parameter AL = \"0\",\n parameter nCWL = 5, // Write CAS latency\n parameter DRAM_TYPE = \"DDR3\", // Memory I/F type: \"DDR3\", \"DDR2\"\n parameter RANKS = 1, // # of memory ranks in the system\n parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))\n parameter DQS_WIDTH = 8, // # of DQS (strobe)\n parameter DRAM_WIDTH = 8, // # of DQ per DQS\n parameter REG_CTRL = \"ON\", // \"ON\" for registered DIMM\n parameter SIM_CAL_OPTION = \"NONE\", // Performs all calibration steps\n parameter NUM_DQSFOUND_CAL = 3, // Number of times to iterate\n parameter N_CTL_LANES = 3, // Number of control byte lanes\n parameter HIGHEST_LANE = 12, // Sum of byte lanes (Data + Ctrl)\n parameter HIGHEST_BANK = 3, // Sum of I/O Banks\n parameter BYTE_LANES_B0 = 4'b1111,\n parameter BYTE_LANES_B1 = 4'b0000,\n parameter BYTE_LANES_B2 = 4'b0000,\n parameter BYTE_LANES_B3 = 4'b0000,\n parameter BYTE_LANES_B4 = 4'b0000,\n parameter DATA_CTL_B0 = 4'hc,\n parameter DATA_CTL_B1 = 4'hf,\n parameter DATA_CTL_B2 = 4'hf,\n parameter DATA_CTL_B3 = 4'hf,\n parameter DATA_CTL_B4 = 4'hf\n )\n (\n input clk,\n input rst,\n input dqsfound_retry,\n // From phy_init\n input pi_dqs_found_start,\n input detect_pi_found_dqs,\n input prech_done,\n // DQSFOUND per Phaser_IN\n input [HIGHEST_LANE-1:0] pi_dqs_found_lanes,\n\n output reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal,\n \n // To phy_init\n output [5:0] rd_data_offset_0,\n output [5:0] rd_data_offset_1,\n output [5:0] rd_data_offset_2,\n output pi_dqs_found_rank_done,\n output pi_dqs_found_done,\n output reg pi_dqs_found_err,\n output [6*RANKS-1:0] rd_data_offset_ranks_0,\n output [6*RANKS-1:0] rd_data_offset_ranks_1,\n output [6*RANKS-1:0] rd_data_offset_ranks_2,\n output reg dqsfound_retry_done,\n output reg dqs_found_prech_req,\n //To MC\n output [6*RANKS-1:0] rd_data_offset_ranks_mc_0,\n output [6*RANKS-1:0] rd_data_offset_ranks_mc_1,\n output [6*RANKS-1:0] rd_data_offset_ranks_mc_2,\n\n input [8:0] po_counter_read_val,\n output rd_data_offset_cal_done,\n output fine_adjust_done,\n output [N_CTL_LANES-1:0] fine_adjust_lane_cnt,\n output reg ck_po_stg2_f_indec,\n output reg ck_po_stg2_f_en,\n output [255:0] dbg_dqs_found_cal\n );\n \n\n // For non-zero AL values\n localparam nAL = (AL == \"CL-1\") ? nCL - 1 : 0; \n\n // Adding the register dimm latency to write latency\n localparam CWL_M = (REG_CTRL == \"ON\") ? nCWL + nAL + 1 : nCWL + nAL;\n\n // Added to reduce simulation time\n localparam LATENCY_FACTOR = 13;\n \n localparam NUM_READS = (SIM_CAL_OPTION == \"NONE\") ? 7 : 1;\n \n localparam [19:0] DATA_PRESENT = {(DATA_CTL_B4[3] & BYTE_LANES_B4[3]),\n (DATA_CTL_B4[2] & BYTE_LANES_B4[2]),\n (DATA_CTL_B4[1] & BYTE_LANES_B4[1]),\n (DATA_CTL_B4[0] & BYTE_LANES_B4[0]),\n (DATA_CTL_B3[3] & BYTE_LANES_B3[3]),\n (DATA_CTL_B3[2] & BYTE_LANES_B3[2]),\n (DATA_CTL_B3[1] & BYTE_LANES_B3[1]),\n (DATA_CTL_B3[0] & BYTE_LANES_B3[0]),\n (DATA_CTL_B2[3] & BYTE_LANES_B2[3]),\n (DATA_CTL_B2[2] & BYTE_LANES_B2[2]),\n (DATA_CTL_B2[1] & BYTE_LANES_B2[1]),\n (DATA_CTL_B2[0] & BYTE_LANES_B2[0]),\n (DATA_CTL_B1[3] & BYTE_LANES_B1[3]),\n (DATA_CTL_B1[2] & BYTE_LANES_B1[2]),\n (DATA_CTL_B1[1] & BYTE_LANES_B1[1]),\n (DATA_CTL_B1[0] & BYTE_LANES_B1[0]),\n (DATA_CTL_B0[3] & BYTE_LANES_B0[3]),\n (DATA_CTL_B0[2] & BYTE_LANES_B0[2]),\n (DATA_CTL_B0[1] & BYTE_LANES_B0[1]),\n (DATA_CTL_B0[0] & BYTE_LANES_B0[0])};\n \n localparam FINE_ADJ_IDLE = 4'h0;\n localparam RST_POSTWAIT = 4'h1;\n localparam RST_POSTWAIT1 = 4'h2;\n localparam RST_WAIT = 4'h3;\n localparam FINE_ADJ_INIT = 4'h4;\n localparam FINE_INC = 4'h5;\n localparam FINE_INC_WAIT = 4'h6;\n localparam FINE_INC_PREWAIT = 4'h7;\n localparam DETECT_PREWAIT = 4'h8;\n localparam DETECT_DQSFOUND = 4'h9;\n localparam PRECH_WAIT = 4'hA;\n localparam FINE_DEC = 4'hB;\n localparam FINE_DEC_WAIT = 4'hC;\n localparam FINE_DEC_PREWAIT = 4'hD;\n localparam FINAL_WAIT = 4'hE;\n localparam FINE_ADJ_DONE = 4'hF;\n \n\n integer k,l,m,n,p,q,r,s;\n \n reg dqs_found_start_r;\n reg [6*HIGHEST_BANK-1:0] rd_byte_data_offset[0:RANKS-1];\n reg rank_done_r;\n reg rank_done_r1;\n reg dqs_found_done_r;\n (* ASYNC_REG = \"TRUE\" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r1;\n (* ASYNC_REG = \"TRUE\" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r2;\n (* ASYNC_REG = \"TRUE\" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r3;\n reg init_dqsfound_done_r;\n reg init_dqsfound_done_r1;\n reg init_dqsfound_done_r2;\n reg init_dqsfound_done_r3;\n reg init_dqsfound_done_r4;\n reg init_dqsfound_done_r5;\n reg [1:0] rnk_cnt_r;\n reg [2:0 ] final_do_index[0:RANKS-1];\n reg [5:0 ] final_do_max[0:RANKS-1];\n reg [6*HIGHEST_BANK-1:0] final_data_offset[0:RANKS-1];\n reg [6*HIGHEST_BANK-1:0] final_data_offset_mc[0:RANKS-1];\n reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r;\n reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r1;\n reg [10*HIGHEST_BANK-1:0] retry_cnt;\n reg dqsfound_retry_r1;\n wire [4*HIGHEST_BANK-1:0] pi_dqs_found_lanes_int;\n reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank;\n reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank_r;\n reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank;\n reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank_r;\n reg [HIGHEST_BANK-1:0] pi_dqs_found_err_r;\n \n // CK/Control byte lanes fine adjust stage\n reg fine_adjust;\n reg [N_CTL_LANES-1:0] ctl_lane_cnt;\n reg [3:0] fine_adj_state_r;\n reg fine_adjust_done_r;\n reg rst_dqs_find;\n reg rst_dqs_find_r1;\n reg rst_dqs_find_r2;\n reg [5:0] init_dec_cnt;\n reg [5:0] dec_cnt;\n reg [5:0] inc_cnt;\n reg final_dec_done;\n reg init_dec_done;\n reg first_fail_detect;\n reg second_fail_detect;\n reg [5:0] first_fail_taps;\n reg [5:0] second_fail_taps;\n reg [5:0] stable_pass_cnt;\n reg [3:0] detect_rd_cnt;\n \n\n \n \n //***************************************************************************\n // Debug signals\n //\n //***************************************************************************\n assign dbg_dqs_found_cal[5:0] = first_fail_taps;\n assign dbg_dqs_found_cal[11:6] = second_fail_taps;\n assign dbg_dqs_found_cal[12] = first_fail_detect;\n assign dbg_dqs_found_cal[13] = second_fail_detect;\n assign dbg_dqs_found_cal[14] = fine_adjust_done_r;\n \n\n assign pi_dqs_found_rank_done = rank_done_r;\n assign pi_dqs_found_done = dqs_found_done_r;\n\n generate\n genvar rnk_cnt;\n if (HIGHEST_BANK == 3) begin // Three Bank Interface\n for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop\n assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];\n assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6];\n assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][17:12];\n assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];\n assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6];\n assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][17:12];\n end\n end else if (HIGHEST_BANK == 2) begin // Two Bank Interface\n for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop\n assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];\n assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6];\n assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0;\n assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];\n assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6];\n assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0;\n end\n end else begin // Single Bank Interface\n for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop\n assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];\n assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = 'd0;\n assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0;\n assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];\n assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = 'd0;\n assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0;\n end\n end\n endgenerate\n \n // final_data_offset is used during write calibration and during\n // normal operation. One rd_data_offset value per rank for entire\n // interface\n generate\n if (HIGHEST_BANK == 3) begin // Three I/O Bank interface\n assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :\n final_data_offset[rnk_cnt_r][0+:6];\n assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] :\n final_data_offset[rnk_cnt_r][6+:6];\n assign rd_data_offset_2 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][12+:6] :\n final_data_offset[rnk_cnt_r][12+:6];\n end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface\n assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :\n final_data_offset[rnk_cnt_r][0+:6];\n assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] :\n final_data_offset[rnk_cnt_r][6+:6];\n assign rd_data_offset_2 = 'd0;\n end else begin\n assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :\n final_data_offset[rnk_cnt_r][0+:6];\n assign rd_data_offset_1 = 'd0;\n assign rd_data_offset_2 = 'd0;\n end\n endgenerate\n \n assign rd_data_offset_cal_done = init_dqsfound_done_r;\n assign fine_adjust_lane_cnt = ctl_lane_cnt;\n \n //**************************************************************************\n // DQSFOUND all and any generation\n // pi_dqs_found_all_bank[x] asserted when all Phaser_INs in Bankx are\n // asserted\n // pi_dqs_found_any_bank[x] asserted when at least one Phaser_IN in Bankx\n // is asserted\n //**************************************************************************\n\n generate\n if ((HIGHEST_LANE == 4) || (HIGHEST_LANE == 8) || (HIGHEST_LANE == 12))\n assign pi_dqs_found_lanes_int = pi_dqs_found_lanes_r3;\n else if ((HIGHEST_LANE == 3) || (HIGHEST_LANE == 7) || (HIGHEST_LANE == 11))\n assign pi_dqs_found_lanes_int = {1'b0, pi_dqs_found_lanes_r3};\n else if ((HIGHEST_LANE == 6) || (HIGHEST_LANE == 10))\n assign pi_dqs_found_lanes_int = {2'b00, pi_dqs_found_lanes_r3};\n else if ((HIGHEST_LANE == 5) || (HIGHEST_LANE == 9))\n assign pi_dqs_found_lanes_int = {3'b000, pi_dqs_found_lanes_r3};\n endgenerate\n \n always @(posedge clk) begin\n if (rst) begin\n for (k = 0; k < HIGHEST_BANK; k = k + 1) begin: rst_pi_dqs_found\n pi_dqs_found_all_bank[k] <= #TCQ 'b0;\n pi_dqs_found_any_bank[k] <= #TCQ 'b0;\n end\n end else if (pi_dqs_found_start) begin\n for (p = 0; p < HIGHEST_BANK; p = p +1) begin: assign_pi_dqs_found\n pi_dqs_found_all_bank[p] <= #TCQ (!DATA_PRESENT[4*p+0] | pi_dqs_found_lanes_int[4*p+0]) &\n (!DATA_PRESENT[4*p+1] | pi_dqs_found_lanes_int[4*p+1]) &\n (!DATA_PRESENT[4*p+2] | pi_dqs_found_lanes_int[4*p+2]) &\n (!DATA_PRESENT[4*p+3] | pi_dqs_found_lanes_int[4*p+3]);\n pi_dqs_found_any_bank[p] <= #TCQ (DATA_PRESENT[4*p+0] & pi_dqs_found_lanes_int[4*p+0]) |\n (DATA_PRESENT[4*p+1] & pi_dqs_found_lanes_int[4*p+1]) |\n (DATA_PRESENT[4*p+2] & pi_dqs_found_lanes_int[4*p+2]) |\n (DATA_PRESENT[4*p+3] & pi_dqs_found_lanes_int[4*p+3]);\n end\n end\n end\n\n \n always @(posedge clk) begin\n pi_dqs_found_all_bank_r <= #TCQ pi_dqs_found_all_bank;\n pi_dqs_found_any_bank_r <= #TCQ pi_dqs_found_any_bank;\n end\n \n//*****************************************************************************\n// Counter to increase number of 4 back-to-back reads per rd_data_offset and\n// per CK/A/C tap value\n//*****************************************************************************\n\n always @(posedge clk) begin\n if (rst || (detect_rd_cnt == 'd0))\n\t detect_rd_cnt <= #TCQ NUM_READS;\n\telse if (detect_pi_found_dqs && (detect_rd_cnt > 'd0))\n\t detect_rd_cnt <= #TCQ detect_rd_cnt - 1;\n end\n \n //**************************************************************************\n // Adjust Phaser_Out stage 2 taps on CK/Address/Command/Controls \n // \n //**************************************************************************\n \n assign fine_adjust_done = fine_adjust_done_r;\n \n always @(posedge clk) begin\n rst_dqs_find_r1 <= #TCQ rst_dqs_find;\n\t rst_dqs_find_r2 <= #TCQ rst_dqs_find_r1;\n end\n \n always @(posedge clk) begin\n if(rst)begin\n fine_adjust <= #TCQ 1'b0;\n ctl_lane_cnt <= #TCQ 'd0;\n fine_adj_state_r <= #TCQ FINE_ADJ_IDLE;\n fine_adjust_done_r <= #TCQ 1'b0;\n ck_po_stg2_f_indec <= #TCQ 1'b0;\n ck_po_stg2_f_en <= #TCQ 1'b0;\n rst_dqs_find <= #TCQ 1'b0;\n init_dec_cnt <= #TCQ 'd31;\n dec_cnt <= #TCQ 'd0;\n inc_cnt <= #TCQ 'd0;\n init_dec_done <= #TCQ 1'b0;\n final_dec_done <= #TCQ 1'b0;\n first_fail_detect <= #TCQ 1'b0;\n second_fail_detect <= #TCQ 1'b0;\n first_fail_taps <= #TCQ 'd0;\n second_fail_taps <= #TCQ 'd0;\n stable_pass_cnt <= #TCQ 'd0;\n dqs_found_prech_req<= #TCQ 1'b0;\n end else begin\n case (fine_adj_state_r)\n \n FINE_ADJ_IDLE: begin\n if (init_dqsfound_done_r5) begin\n if (SIM_CAL_OPTION == \"FAST_CAL\") begin\n fine_adjust <= #TCQ 1'b1;\n fine_adj_state_r <= #TCQ FINE_ADJ_DONE;\n rst_dqs_find <= #TCQ 1'b0;\n end else begin\n fine_adjust <= #TCQ 1'b1;\n fine_adj_state_r <= #TCQ RST_WAIT;\n rst_dqs_find <= #TCQ 1'b1;\n end\n end\n end\n \n RST_WAIT: begin\n if (~(|pi_dqs_found_any_bank) && rst_dqs_find_r2) begin\n rst_dqs_find <= #TCQ 1'b0;\n if (|init_dec_cnt)\n fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;\n else if (final_dec_done)\n fine_adj_state_r <= #TCQ FINE_ADJ_DONE;\n else\n fine_adj_state_r <= #TCQ RST_POSTWAIT;\n end\n end\n \n RST_POSTWAIT: begin\n fine_adj_state_r <= #TCQ RST_POSTWAIT1;\n end\n \n RST_POSTWAIT1: begin\n fine_adj_state_r <= #TCQ FINE_ADJ_INIT;\n end\n \n FINE_ADJ_INIT: begin\n //if (detect_pi_found_dqs && (inc_cnt < 'd63))\n fine_adj_state_r <= #TCQ FINE_INC;\n end\n \n FINE_INC: begin\n fine_adj_state_r <= #TCQ FINE_INC_WAIT;\n ck_po_stg2_f_indec <= #TCQ 1'b1;\n ck_po_stg2_f_en <= #TCQ 1'b1;\n if (ctl_lane_cnt == N_CTL_LANES-1)\n inc_cnt <= #TCQ inc_cnt + 1;\n end\n \n FINE_INC_WAIT: begin\n ck_po_stg2_f_indec <= #TCQ 1'b0;\n ck_po_stg2_f_en <= #TCQ 1'b0;\n if (ctl_lane_cnt != N_CTL_LANES-1) begin\n ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;\n fine_adj_state_r <= #TCQ FINE_INC_PREWAIT;\n end else if (ctl_lane_cnt == N_CTL_LANES-1) begin\n ctl_lane_cnt <= #TCQ 'd0;\n fine_adj_state_r <= #TCQ DETECT_PREWAIT;\n end\n end\n \n FINE_INC_PREWAIT: begin\n fine_adj_state_r <= #TCQ FINE_INC;\n end\n \n DETECT_PREWAIT: begin\n if (detect_pi_found_dqs && (detect_rd_cnt == 'd1))\n fine_adj_state_r <= #TCQ DETECT_DQSFOUND;\n\t\t\t else\n\t\t\t fine_adj_state_r <= #TCQ DETECT_PREWAIT;\n end\n \n DETECT_DQSFOUND: begin\n if (detect_pi_found_dqs && ~(&pi_dqs_found_all_bank)) begin\n stable_pass_cnt <= #TCQ 'd0;\n if (~first_fail_detect && (inc_cnt == 'd63)) begin\n // First failing tap detected at 63 taps\n // then decrement to 31\n first_fail_detect <= #TCQ 1'b1;\n first_fail_taps <= #TCQ inc_cnt;\n fine_adj_state_r <= #TCQ FINE_DEC;\n dec_cnt <= #TCQ 'd32;\n end else if (~first_fail_detect && (inc_cnt > 'd30) && (stable_pass_cnt > 'd29)) begin\n // First failing tap detected at greater than 30 taps\n // then stop looking for second edge and decrement\n first_fail_detect <= #TCQ 1'b1;\n first_fail_taps <= #TCQ inc_cnt;\n fine_adj_state_r <= #TCQ FINE_DEC;\n dec_cnt <= #TCQ (inc_cnt>>1) + 1;\t\t\t\t \n\t\t\t end else if (~first_fail_detect || (first_fail_detect && (stable_pass_cnt < 'd30) && (inc_cnt <= 'd32))) begin\n // First failing tap detected, continue incrementing\n // until either second failing tap detected or 63\n first_fail_detect <= #TCQ 1'b1;\n first_fail_taps <= #TCQ inc_cnt;\n rst_dqs_find <= #TCQ 1'b1;\n if ((inc_cnt == 'd12) || (inc_cnt == 'd24)) begin\n dqs_found_prech_req <= #TCQ 1'b1;\n fine_adj_state_r <= #TCQ PRECH_WAIT;\n end else\n fine_adj_state_r <= #TCQ RST_WAIT;\n end else if (first_fail_detect && (inc_cnt > 'd32) && (inc_cnt < 'd63) && (stable_pass_cnt < 'd30)) begin\n // Consecutive 30 taps of passing region was not found\n // continue incrementing\n first_fail_detect <= #TCQ 1'b1;\n first_fail_taps <= #TCQ inc_cnt;\n rst_dqs_find <= #TCQ 1'b1;\n if ((inc_cnt == 'd36) || (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin\n dqs_found_prech_req <= #TCQ 1'b1;\n fine_adj_state_r <= #TCQ PRECH_WAIT;\n end else\n fine_adj_state_r <= #TCQ RST_WAIT;\n end else if (first_fail_detect && (inc_cnt == 'd63)) begin\n if (stable_pass_cnt < 'd30) begin\n // Consecutive 30 taps of passing region was not found\n // from tap 0 to 63 so decrement back to 31\n first_fail_detect <= #TCQ 1'b1;\n first_fail_taps <= #TCQ inc_cnt;\n fine_adj_state_r <= #TCQ FINE_DEC;\n dec_cnt <= #TCQ 'd32;\n end else begin\n // Consecutive 30 taps of passing region was found\n // between first_fail_taps and 63\n fine_adj_state_r <= #TCQ FINE_DEC;\n dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);\n end\n end else begin\n // Second failing tap detected, decrement to center of\n // failing taps\n second_fail_detect <= #TCQ 1'b1;\n second_fail_taps <= #TCQ inc_cnt;\n dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);\n fine_adj_state_r <= #TCQ FINE_DEC;\n end\n end else if (detect_pi_found_dqs && (&pi_dqs_found_all_bank)) begin\n stable_pass_cnt <= #TCQ stable_pass_cnt + 1;\n if ((inc_cnt == 'd12) || (inc_cnt == 'd24) || (inc_cnt == 'd36) || \n (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin\n dqs_found_prech_req <= #TCQ 1'b1;\n fine_adj_state_r <= #TCQ PRECH_WAIT;\n end else if (inc_cnt < 'd63) begin\n rst_dqs_find <= #TCQ 1'b1;\n fine_adj_state_r <= #TCQ RST_WAIT;\n end else begin\n fine_adj_state_r <= #TCQ FINE_DEC;\n if (~first_fail_detect || (first_fail_taps > 'd33))\n // No failing taps detected, decrement by 31\n dec_cnt <= #TCQ 'd32;\n //else if (first_fail_detect && (stable_pass_cnt > 'd28))\n // // First failing tap detected between 0 and 34\n // // decrement midpoint between 63 and failing tap\n // dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);\n else\n // First failing tap detected\n // decrement to midpoint between 63 and failing tap\n dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);\n end\n end\n end\n \n PRECH_WAIT: begin\n if (prech_done) begin\n dqs_found_prech_req <= #TCQ 1'b0;\n rst_dqs_find <= #TCQ 1'b1;\n fine_adj_state_r <= #TCQ RST_WAIT;\n end\n end\n \n \n FINE_DEC: begin\n fine_adj_state_r <= #TCQ FINE_DEC_WAIT;\n ck_po_stg2_f_indec <= #TCQ 1'b0;\n ck_po_stg2_f_en <= #TCQ 1'b1;\n if ((ctl_lane_cnt == N_CTL_LANES-1) && (init_dec_cnt > 'd0))\n init_dec_cnt <= #TCQ init_dec_cnt - 1;\n else if ((ctl_lane_cnt == N_CTL_LANES-1) && (dec_cnt > 'd0))\n dec_cnt <= #TCQ dec_cnt - 1;\n end\n \n FINE_DEC_WAIT: begin\n ck_po_stg2_f_indec <= #TCQ 1'b0;\n ck_po_stg2_f_en <= #TCQ 1'b0;\n if (ctl_lane_cnt != N_CTL_LANES-1) begin\n ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;\n fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;\n end else if (ctl_lane_cnt == N_CTL_LANES-1) begin\n ctl_lane_cnt <= #TCQ 'd0;\n if ((dec_cnt > 'd0) || (init_dec_cnt > 'd0))\n fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;\n else begin\n fine_adj_state_r <= #TCQ FINAL_WAIT;\n if ((init_dec_cnt == 'd0) && ~init_dec_done)\n init_dec_done <= #TCQ 1'b1;\n else\n final_dec_done <= #TCQ 1'b1;\n end\n end\n end\n \n FINE_DEC_PREWAIT: begin\n fine_adj_state_r <= #TCQ FINE_DEC;\n end\n \n FINAL_WAIT: begin\n rst_dqs_find <= #TCQ 1'b1;\n fine_adj_state_r <= #TCQ RST_WAIT;\n end\n \n FINE_ADJ_DONE: begin\n if (&pi_dqs_found_all_bank) begin\n fine_adjust_done_r <= #TCQ 1'b1;\n rst_dqs_find <= #TCQ 1'b0;\n fine_adj_state_r <= #TCQ FINE_ADJ_DONE;\n end\n end\n \n endcase\n end\n end\n \n\n \n \n//***************************************************************************** \n \n\n always@(posedge clk)\n dqs_found_start_r <= #TCQ pi_dqs_found_start;\n \n\n always @(posedge clk) begin\n if (rst)\n rnk_cnt_r <= #TCQ 2'b00;\n else if (init_dqsfound_done_r)\n rnk_cnt_r <= #TCQ rnk_cnt_r;\n else if (rank_done_r)\n rnk_cnt_r <= #TCQ rnk_cnt_r + 1;\n end\n \n //*****************************************************************\n // Read data_offset calibration done signal\n //*****************************************************************\n \n always @(posedge clk) begin\n if (rst || (|pi_rst_stg1_cal_r))\n init_dqsfound_done_r <= #TCQ 1'b0;\n else if (&pi_dqs_found_all_bank) begin\n if (rnk_cnt_r == RANKS-1)\n init_dqsfound_done_r <= #TCQ 1'b1;\n else\n init_dqsfound_done_r <= #TCQ 1'b0;\n end\n end\n \n always @(posedge clk) begin\n if (rst ||\n (init_dqsfound_done_r && (rnk_cnt_r == RANKS-1)))\n rank_done_r <= #TCQ 1'b0;\n else if (&pi_dqs_found_all_bank && ~(&pi_dqs_found_all_bank_r))\n rank_done_r <= #TCQ 1'b1;\n else\n rank_done_r <= #TCQ 1'b0;\n end\n \n always @(posedge clk) begin\n pi_dqs_found_lanes_r1 <= #TCQ pi_dqs_found_lanes;\n pi_dqs_found_lanes_r2 <= #TCQ pi_dqs_found_lanes_r1;\n pi_dqs_found_lanes_r3 <= #TCQ pi_dqs_found_lanes_r2;\n init_dqsfound_done_r1 <= #TCQ init_dqsfound_done_r;\n init_dqsfound_done_r2 <= #TCQ init_dqsfound_done_r1;\n init_dqsfound_done_r3 <= #TCQ init_dqsfound_done_r2;\n init_dqsfound_done_r4 <= #TCQ init_dqsfound_done_r3;\n init_dqsfound_done_r5 <= #TCQ init_dqsfound_done_r4;\n rank_done_r1 <= #TCQ rank_done_r;\n dqsfound_retry_r1 <= #TCQ dqsfound_retry;\n end\n\n \n always @(posedge clk) begin\n if (rst)\n dqs_found_done_r <= #TCQ 1'b0;\n else if (&pi_dqs_found_all_bank && (rnk_cnt_r == RANKS-1) && init_dqsfound_done_r1 &&\n (fine_adj_state_r == FINE_ADJ_DONE))\n dqs_found_done_r <= #TCQ 1'b1;\n else\n dqs_found_done_r <= #TCQ 1'b0;\n end\n \n\n generate\n if (HIGHEST_BANK == 3) begin // Three I/O Bank interface\n\n // Reset read data offset calibration in all DQS Phaser_INs\n // in a Bank after the read data offset value for a rank is determined\n // or if within a Bank DQSFOUND is not asserted for all DQSs\n always @(posedge clk) begin\n if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)\n pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;\n else if ((pi_dqs_found_start && ~dqs_found_start_r) ||\n //(dqsfound_retry[0]) ||\n (pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||\n (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))\n pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;\n end\n\n always @(posedge clk) begin\n if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust)\n pi_rst_stg1_cal_r[1] <= #TCQ 1'b0;\n else if ((pi_dqs_found_start && ~dqs_found_start_r) ||\n //(dqsfound_retry[1]) ||\n (pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) ||\n (rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))\n pi_rst_stg1_cal_r[1] <= #TCQ 1'b1;\n end\n\n always @(posedge clk) begin\n if (rst || pi_rst_stg1_cal_r1[2] || fine_adjust)\n pi_rst_stg1_cal_r[2] <= #TCQ 1'b0;\n else if ((pi_dqs_found_start && ~dqs_found_start_r) ||\n //(dqsfound_retry[2]) ||\n (pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2]) ||\n (rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))\n pi_rst_stg1_cal_r[2] <= #TCQ 1'b1;\n end\n \n always @(posedge clk) begin\n if (rst || fine_adjust)\n pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;\n else if (pi_rst_stg1_cal_r[0])\n pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;\n else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])\n pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;\n end\n \n always @(posedge clk) begin\n if (rst || fine_adjust)\n pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;\n else if (pi_rst_stg1_cal_r[1])\n pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1;\n else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1])\n pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;\n end\n \n always @(posedge clk) begin\n if (rst || fine_adjust)\n pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0;\n else if (pi_rst_stg1_cal_r[2])\n pi_rst_stg1_cal_r1[2] <= #TCQ 1'b1;\n else if (~pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2])\n pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0;\n end\n\n //*****************************************************************************\n // Retry counter to track number of DQSFOUND retries\n //*****************************************************************************\n \n always @(posedge clk) begin\n if (rst || rank_done_r)\n retry_cnt[0+:10] <= #TCQ 'b0;\n else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&\n ~pi_dqs_found_all_bank[0])\n retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;\n else\n retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];\n end\n\t \n\t always @(posedge clk) begin\n if (rst || rank_done_r)\n retry_cnt[10+:10] <= #TCQ 'b0;\n else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&\n ~pi_dqs_found_all_bank[1])\n retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1;\n else\n retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10];\n end\n\t \n\t always @(posedge clk) begin\n if (rst || rank_done_r)\n retry_cnt[20+:10] <= #TCQ 'b0;\n else if ((rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&\n ~pi_dqs_found_all_bank[2])\n retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10] + 1;\n else\n retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10];\n end\n\n // Error generation in case pi_dqs_found_all_bank\n // is not asserted\n always @(posedge clk) begin\n if (rst)\n pi_dqs_found_err_r[0] <= #TCQ 1'b0;\n else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&\n (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))\n pi_dqs_found_err_r[0] <= #TCQ 1'b1;\n end\n\n always @(posedge clk) begin\n if (rst)\n pi_dqs_found_err_r[1] <= #TCQ 1'b0;\n else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) &&\n (rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))\n pi_dqs_found_err_r[1] <= #TCQ 1'b1;\n end\n\n always @(posedge clk) begin\n if (rst)\n pi_dqs_found_err_r[2] <= #TCQ 1'b0;\n else if (~pi_dqs_found_all_bank[2] && (retry_cnt[20+:10] == NUM_DQSFOUND_CAL) &&\n (rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))\n pi_dqs_found_err_r[2] <= #TCQ 1'b1;\n end\n\n // Read data offset value for all DQS in a Bank\n always @(posedge clk) begin\n if (rst) begin\n for (q = 0; q < RANKS; q = q + 1) begin: three_bank0_rst_loop\n rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL - 2;\n end\n end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||\n\t\t (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))\n rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL - 2;\n else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&\n //(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL + LATENCY_FACTOR)) &&\n (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)\n rd_byte_data_offset[rnk_cnt_r][0+:6]\n <= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] + 1;\n end\n\n always @(posedge clk) begin\n if (rst) begin\n for (r = 0; r < RANKS; r = r + 1) begin: three_bank1_rst_loop\n rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL - 2;\n end\n end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||\n\t\t (rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))\n rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL - 2;\n else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] &&\n //(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL + LATENCY_FACTOR)) &&\n (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)\n rd_byte_data_offset[rnk_cnt_r][6+:6]\n <= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] + 1;\n end\n\n always @(posedge clk) begin\n if (rst) begin\n for (s = 0; s < RANKS; s = s + 1) begin: three_bank2_rst_loop\n rd_byte_data_offset[s][12+:6] <= #TCQ nCL + nAL - 2;\n end\n end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||\n\t\t (rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))\n rd_byte_data_offset[rnk_cnt_r][12+:6] <= #TCQ nCL + nAL - 2;\n else if (dqs_found_start_r && ~pi_dqs_found_all_bank[2] &&\n //(rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL + LATENCY_FACTOR)) &&\n (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)\n rd_byte_data_offset[rnk_cnt_r][12+:6]\n <= #TCQ rd_byte_data_offset[rnk_cnt_r][12+:6] + 1;\n end\n\n//*****************************************************************************\n// Two I/O Bank Interface\n//*****************************************************************************\n end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface\n\n // Reset read data offset calibration in all DQS Phaser_INs\n // in a Bank after the read data offset value for a rank is determined\n // or if within a Bank DQSFOUND is not asserted for all DQSs\n always @(posedge clk) begin\n if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)\n pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;\n else if ((pi_dqs_found_start && ~dqs_found_start_r) ||\n //(dqsfound_retry[0]) ||\n (pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||\n (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))\n pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;\n end\n\n always @(posedge clk) begin\n if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust)\n pi_rst_stg1_cal_r[1] <= #TCQ 1'b0;\n else if ((pi_dqs_found_start && ~dqs_found_start_r) ||\n //(dqsfound_retry[1]) ||\n (pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) ||\n (rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))\n pi_rst_stg1_cal_r[1] <= #TCQ 1'b1;\n end\n \n always @(posedge clk) begin\n if (rst || fine_adjust)\n pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;\n else if (pi_rst_stg1_cal_r[0])\n pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;\n else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])\n pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;\n end\n \n always @(posedge clk) begin\n if (rst || fine_adjust)\n pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;\n else if (pi_rst_stg1_cal_r[1])\n pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1;\n else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1])\n pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;\n end\n\n //*****************************************************************************\n // Retry counter to track number of DQSFOUND retries\n //*****************************************************************************\n \n always @(posedge clk) begin\n if (rst || rank_done_r)\n retry_cnt[0+:10] <= #TCQ 'b0;\n else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&\n ~pi_dqs_found_all_bank[0])\n retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;\n else\n retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];\n end\n\t \n\t always @(posedge clk) begin\n if (rst || rank_done_r)\n retry_cnt[10+:10] <= #TCQ 'b0;\n else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&\n ~pi_dqs_found_all_bank[1])\n retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1;\n else\n retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10];\n end\n\n\n // Error generation in case pi_dqs_found_all_bank\n // is not asserted\n always @(posedge clk) begin\n if (rst)\n pi_dqs_found_err_r[0] <= #TCQ 1'b0;\n else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&\n (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))\n pi_dqs_found_err_r[0] <= #TCQ 1'b1;\n end\n\n always @(posedge clk) begin\n if (rst)\n pi_dqs_found_err_r[1] <= #TCQ 1'b0;\n else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) &&\n (rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))\n pi_dqs_found_err_r[1] <= #TCQ 1'b1;\n end\n\n\n // Read data offset value for all DQS in a Bank\n always @(posedge clk) begin\n if (rst) begin\n for (q = 0; q < RANKS; q = q + 1) begin: two_bank0_rst_loop\n rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL - 2;\n end\n end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||\n\t\t (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))\n rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL - 2;\n else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&\n //(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL + LATENCY_FACTOR)) &&\n (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)\n rd_byte_data_offset[rnk_cnt_r][0+:6]\n <= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] + 1;\n end\n\n always @(posedge clk) begin\n if (rst) begin\n for (r = 0; r < RANKS; r = r + 1) begin: two_bank1_rst_loop\n rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL - 2;\n end\n end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||\n\t\t (rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))\n rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL - 2;\n else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] &&\n //(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL + LATENCY_FACTOR)) &&\n (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)\n rd_byte_data_offset[rnk_cnt_r][6+:6]\n <= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] + 1;\n end\n//*****************************************************************************\n// One I/O Bank Interface\n//*****************************************************************************\n end else begin // One I/O Bank Interface\n\n // Read data offset value for all DQS in Bank0\n always @(posedge clk) begin\n if (rst) begin\n for (l = 0; l < RANKS; l = l + 1) begin: bank_rst_loop\n rd_byte_data_offset[l] <= #TCQ nCL + nAL - 2;\n end\n end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||\n\t\t (rd_byte_data_offset[rnk_cnt_r] > (nCL + nAL + LATENCY_FACTOR - 1)))\n rd_byte_data_offset[rnk_cnt_r] <= #TCQ nCL + nAL - 2;\n else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&\n //(rd_byte_data_offset[rnk_cnt_r] < (nCL + nAL + LATENCY_FACTOR)) &&\n (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)\n rd_byte_data_offset[rnk_cnt_r]\n <= #TCQ rd_byte_data_offset[rnk_cnt_r] + 1;\n end\n\n // Reset read data offset calibration in all DQS Phaser_INs\n // in a Bank after the read data offset value for a rank is determined\n // or if within a Bank DQSFOUND is not asserted for all DQSs\n always @(posedge clk) begin\n if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)\n pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;\n else if ((pi_dqs_found_start && ~dqs_found_start_r) ||\n //(dqsfound_retry[0]) ||\n (pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||\n (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))\n pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;\n end\n \n always @(posedge clk) begin\n if (rst || fine_adjust)\n pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;\n else if (pi_rst_stg1_cal_r[0])\n pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;\n else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])\n pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;\n end\n\n //*****************************************************************************\n // Retry counter to track number of DQSFOUND retries\n //*****************************************************************************\n \n always @(posedge clk) begin\n if (rst || rank_done_r)\n retry_cnt[0+:10] <= #TCQ 'b0;\n else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&\n ~pi_dqs_found_all_bank[0])\n retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;\n else\n retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];\n end\n\n\n // Error generation in case pi_dqs_found_all_bank\n // is not asserted even with 3 dqfound retries\n always @(posedge clk) begin\n if (rst)\n pi_dqs_found_err_r[0] <= #TCQ 1'b0;\n else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&\n (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))\n pi_dqs_found_err_r[0] <= #TCQ 1'b1;\n end\n\n end\n endgenerate\n \n always @(posedge clk) begin\n if (rst)\n pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b0}};\n else if (rst_dqs_find)\n pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b1}};\n else\n pi_rst_stg1_cal <= #TCQ pi_rst_stg1_cal_r;\n end\n \n\n\n // Final read data offset value to be used during write calibration and\n // normal operation\n generate\n genvar i;\n genvar j;\n for (i = 0; i < RANKS; i = i + 1) begin: rank_final_loop\n reg [5:0] final_do_cand [RANKS-1:0];\n // combinatorially select the candidate offset for the bank\n // indexed by final_do_index\n if (HIGHEST_BANK == 3) begin\n always @(*) begin\n case (final_do_index[i])\n\t 3'b000: final_do_cand[i] = final_data_offset[i][5:0];\n\t 3'b001: final_do_cand[i] = final_data_offset[i][11:6];\n\t 3'b010: final_do_cand[i] = final_data_offset[i][17:12];\n\t default: final_do_cand[i] = 'd0;\n\t endcase\n end\n end else if (HIGHEST_BANK == 2) begin\n always @(*) begin\n case (final_do_index[i])\n\t 3'b000: final_do_cand[i] = final_data_offset[i][5:0];\n\t 3'b001: final_do_cand[i] = final_data_offset[i][11:6];\n\t 3'b010: final_do_cand[i] = 'd0;\n\t default: final_do_cand[i] = 'd0;\n\t endcase\n end\n end else begin\n always @(*) begin\n case (final_do_index[i])\n\t 3'b000: final_do_cand[i] = final_data_offset[i][5:0];\n\t 3'b001: final_do_cand[i] = 'd0;\n\t 3'b010: final_do_cand[i] = 'd0;\n\t default: final_do_cand[i] = 'd0;\n\t endcase\n end\n end\n \n always @(posedge clk) begin\n if (rst) \n\t final_do_max[i] <= #TCQ 0;\n\t else begin\n\t final_do_max[i] <= #TCQ final_do_max[i]; // default\n case (final_do_index[i])\n\t 3'b000: if ( | DATA_PRESENT[3:0]) \n\t if (final_do_max[i] < final_do_cand[i])\n\t if (CWL_M % 2) // odd latency CAS slot 1\n\t\t final_do_max[i] <= #TCQ final_do_cand[i] - 1;\n\t\t else\n\t\t final_do_max[i] <= #TCQ final_do_cand[i];\n\t 3'b001: if ( | DATA_PRESENT[7:4]) \n\t if (final_do_max[i] < final_do_cand[i])\n\t\t if (CWL_M % 2) // odd latency CAS slot 1\n\t\t final_do_max[i] <= #TCQ final_do_cand[i] - 1;\n\t\t else\n\t\t final_do_max[i] <= #TCQ final_do_cand[i];\n\t 3'b010: if ( | DATA_PRESENT[11:8]) \n\t if (final_do_max[i] < final_do_cand[i])\n\t\t if (CWL_M % 2) // odd latency CAS slot 1\n\t\t final_do_max[i] <= #TCQ final_do_cand[i] - 1;\n\t\t else\n\t\t final_do_max[i] <= #TCQ final_do_cand[i];\n default:\n\t final_do_max[i] <= #TCQ final_do_max[i];\n\t endcase\n\t end\n\tend\n\n\talways @(posedge clk) \n\t if (rst) begin\n\t final_do_index[i] <= #TCQ 0;\n\t end\n\t else begin\n\t final_do_index[i] <= #TCQ final_do_index[i] + 1;\n\t end\n\n for (j = 0; j < HIGHEST_BANK; j = j + 1) begin: bank_final_loop\n \n always @(posedge clk) begin\n if (rst) begin\n final_data_offset[i][6*j+:6] <= #TCQ 'b0;\n\t end\n else begin\n\t //if (dqsfound_retry[j])\n // final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];\n //else \n if (init_dqsfound_done_r && ~init_dqsfound_done_r1) begin\n\t if ( DATA_PRESENT [ j*4+:4] != 0) begin // has a data lane\n final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];\n if (CWL_M % 2) // odd latency CAS slot 1\n final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6] - 1;\n else // even latency CAS slot 0\n final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];\n end \n\t end\n else if (init_dqsfound_done_r5 ) begin\n\t if ( DATA_PRESENT [ j*4+:4] == 0) begin // all control lanes\n final_data_offset[i][6*j+:6] <= #TCQ final_do_max[i];\n final_data_offset_mc[i][6*j+:6] <= #TCQ final_do_max[i];\n end\t\n end\n\t end\n end\n end\n end\n endgenerate\n\n \n // Error generation in case pi_found_dqs signal from Phaser_IN\n // is not asserted when a common rddata_offset value is used\n \n always @(posedge clk) begin\n pi_dqs_found_err <= #TCQ |pi_dqs_found_err_r;\n end\n \n\n \nendmodule\n \n \n \n \n\n \n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_init.v", "content": "//*****************************************************************************\n// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor: Xilinx\n// \\ \\ \\/ Version: %version\n// \\ \\ Application: MIG\n// / / Filename: ddr_phy_init.v\n// /___/ /\\ Date Last Modified: $Date: 2011/06/02 08:35:09 $\n// \\ \\ / \\ Date Created:\n// \\___\\/\\___\\\n//\n//Device: 7 Series\n//Design Name: DDR3 SDRAM\n//Purpose:\n// Memory initialization and overall master state control during\n// initialization and calibration. Specifically, the following functions\n// are performed:\n// 1. Memory initialization (initial AR, mode register programming, etc.)\n// 2. Initiating write leveling\n// 3. Generate training pattern writes for read leveling. Generate\n// memory readback for read leveling.\n// This module has an interface for providing control/address and write\n// data to the PHY Control Block during initialization/calibration.\n// Once initialization and calibration are complete, control is passed to the MC. \n//\n//Reference:\n//Revision History:\n// \n//*****************************************************************************\n\n/******************************************************************************\n**$Id: ddr_phy_init.v,v 1.1 2011/06/02 08:35:09 mishra Exp $\n**$Date: 2011/06/02 08:35:09 $\n**$Author: mishra $\n**$Revision: 1.1 $\n**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_init.v,v $\n******************************************************************************/\n\n`timescale 1ps/1ps\n\n\nmodule mig_7series_v4_0_ddr_phy_init #\n (\n parameter tCK = 1500, // DDRx SDRAM clock period\n parameter TCQ = 100,\n parameter nCK_PER_CLK = 4, // # of memory clocks per CLK\n parameter CLK_PERIOD = 3000, // Logic (internal) clk period (in ps)\n parameter USE_ODT_PORT = 0, // 0 - No ODT output from FPGA\n // 1 - ODT output from FPGA\n parameter DDR3_VDD_OP_VOLT = \"150\", // Voltage mode used for DDR3\n // 150 - 1.50 V\n // 135 - 1.35 V\n // 125 - 1.25 V\n parameter VREF = \"EXTERNAL\", // Internal or external Vref\n parameter PRBS_WIDTH = 8, // PRBS sequence = 2^PRBS_WIDTH\n parameter BANK_WIDTH = 2,\n parameter CA_MIRROR = \"OFF\", // C/A mirror opt for DDR3 dual rank\n parameter COL_WIDTH = 10,\n parameter nCS_PER_RANK = 1, // # of CS bits per rank e.g. for \n // component I/F with CS_WIDTH=1, \n // nCS_PER_RANK=# of components\n parameter DQ_WIDTH = 64,\n parameter DQS_WIDTH = 8,\n parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))\n parameter ROW_WIDTH = 14,\n parameter CS_WIDTH = 1,\n parameter RANKS = 1, // # of memory ranks in the interface\n parameter CKE_WIDTH = 1, // # of cke outputs \n parameter DRAM_TYPE = \"DDR3\",\n parameter REG_CTRL = \"ON\",\n parameter ADDR_CMD_MODE= \"1T\", \n\n // calibration Address\n parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address\n parameter CALIB_COL_ADD = 12'h000, // Calibration column address\n parameter CALIB_BA_ADD = 3'h0, // Calibration bank address \n \n // DRAM mode settings\n parameter AL = \"0\", // Additive Latency option\n parameter BURST_MODE = \"8\", // Burst length\n parameter BURST_TYPE = \"SEQ\", // Burst type \n// parameter nAL = 0, // Additive latency (in clk cyc)\n parameter nCL = 5, // Read CAS latency (in clk cyc)\n parameter nCWL = 5, // Write CAS latency (in clk cyc)\n parameter tRFC = 110000, // Refresh-to-command delay (in ps)\n parameter REFRESH_TIMER = 1553, // Refresh interval in fabrci cycles between 8 posted refreshes\n parameter REFRESH_TIMER_WIDTH = 8,\n parameter OUTPUT_DRV = \"HIGH\", // DRAM reduced output drive option\n parameter RTT_NOM = \"60\", // Nominal ODT termination value\n parameter RTT_WR = \"60\", // Write ODT termination value\n parameter WRLVL = \"ON\", // Enable write leveling\n// parameter PHASE_DETECT = \"ON\", // Enable read phase detector\n parameter DDR2_DQSN_ENABLE = \"YES\", // Enable differential DQS for DDR2\n parameter nSLOTS = 1, // Number of DIMM SLOTs in the system\n parameter SIM_INIT_OPTION = \"NONE\", // \"NONE\", \"SKIP_PU_DLY\", \"SKIP_INIT\"\n parameter SIM_CAL_OPTION = \"NONE\", // \"NONE\", \"FAST_CAL\", \"SKIP_CAL\"\n parameter CKE_ODT_AUX = \"FALSE\",\n parameter PRE_REV3ES = \"OFF\", // Enable TG error detection during calibration\n parameter TEST_AL = \"0\", // Internal use for ICM verification\n parameter FIXED_VICTIM = \"TRUE\",\n parameter BYPASS_COMPLEX_OCAL = \"FALSE\",\n parameter SKIP_CALIB = \"FALSE\"\n )\n (\n input clk,\n input rst,\n input [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o,\n input delay_incdec_done,\n input ck_addr_cmd_delay_done,\n input pi_phase_locked_all,\n input pi_dqs_found_done,\n input dqsfound_retry,\n input dqs_found_prech_req,\n output reg pi_phaselock_start,\n output pi_phase_locked_err,\n output pi_calib_done,\n input phy_if_empty,\n // Read/write calibration interface\n input wrlvl_done,\n input wrlvl_rank_done,\n input wrlvl_byte_done,\n input wrlvl_byte_redo,\n input wrlvl_final,\n output reg wrlvl_final_if_rst,\n input oclkdelay_calib_done,\n input oclk_prech_req,\n input oclk_calib_resume,\n input lim_done,\n input lim_wr_req,\n output reg oclkdelay_calib_start,\n //complex oclkdelay calibration\n input complex_oclkdelay_calib_done,\n input complex_oclk_prech_req,\n input complex_oclk_calib_resume,\n output reg complex_oclkdelay_calib_start,\n input [DQS_CNT_WIDTH:0] complex_oclkdelay_calib_cnt, // same as oclkdelay_calib_cnt\n output reg complex_ocal_num_samples_inc,\n input complex_ocal_num_samples_done_r,\n input [2:0] complex_ocal_rd_victim_sel,\n output reg complex_ocal_reset_rd_addr,\n input complex_ocal_ref_req,\n output reg complex_ocal_ref_done,\n \n input done_dqs_tap_inc,\n input [5:0] rd_data_offset_0,\n input [5:0] rd_data_offset_1,\n input [5:0] rd_data_offset_2,\n input [6*RANKS-1:0] rd_data_offset_ranks_0,\n input [6*RANKS-1:0] rd_data_offset_ranks_1,\n input [6*RANKS-1:0] rd_data_offset_ranks_2,\n input pi_dqs_found_rank_done,\n input wrcal_done,\n input wrcal_prech_req,\n input wrcal_read_req,\n input wrcal_act_req,\n input temp_wrcal_done,\n input [7:0] slot_0_present,\n input [7:0] slot_1_present,\n output reg wl_sm_start,\n output reg wr_lvl_start,\n output reg wrcal_start,\n output reg wrcal_rd_wait,\n output reg wrcal_sanity_chk,\n output reg tg_timer_done,\n output reg no_rst_tg_mc,\n input rdlvl_stg1_done,\n input rdlvl_stg1_rank_done,\n output reg rdlvl_stg1_start,\n output reg pi_dqs_found_start,\n output reg detect_pi_found_dqs,\n // rdlvl stage 1 precharge requested after each DQS \n input rdlvl_prech_req,\n input rdlvl_last_byte_done,\n input wrcal_resume,\n input wrcal_sanity_chk_done,\n // MPR read leveling\n input mpr_rdlvl_done,\n input mpr_rnk_done,\n input mpr_last_byte_done,\n output reg mpr_rdlvl_start,\n output reg mpr_end_if_reset,\n\n // PRBS Read Leveling\n input prbs_rdlvl_done,\n input prbs_last_byte_done,\n input prbs_rdlvl_prech_req,\n input complex_victim_inc,\n input [2:0] rd_victim_sel,\n input [DQS_CNT_WIDTH:0] pi_stg2_prbs_rdlvl_cnt,\n output reg [2:0] victim_sel,\n output reg [DQS_CNT_WIDTH:0]victim_byte_cnt,\n output reg prbs_rdlvl_start,\n output reg prbs_gen_clk_en,\n output reg prbs_gen_oclk_clk_en,\n output reg complex_sample_cnt_inc,\n output reg complex_sample_cnt_inc_ocal,\n output reg complex_wr_done,\n\n // Signals shared btw multiple calibration stages\n output reg prech_done,\n // Data select / status\n output reg init_calib_complete, \n // Signal to mask memory model error for Invalid latching edge\n output reg calib_writes, \n // PHY address/control\n // 2 commands to PHY Control Block per div 2 clock in 2:1 mode\n // 4 commands to PHY Control Block per div 4 clock in 4:1 mode\n output reg [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address,\n output reg [nCK_PER_CLK*BANK_WIDTH-1:0]phy_bank,\n output reg [nCK_PER_CLK-1:0] phy_ras_n,\n output reg [nCK_PER_CLK-1:0] phy_cas_n,\n output reg [nCK_PER_CLK-1:0] phy_we_n,\n output reg phy_reset_n,\n output [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n,\n\n // Hard PHY Interface signals\n input phy_ctl_ready,\n input phy_ctl_full,\n input phy_cmd_full,\n input phy_data_full,\n output reg calib_ctl_wren,\n output reg calib_cmd_wren,\n output reg [1:0] calib_seq,\n output reg write_calib,\n output reg read_calib,\n // PHY_Ctl_Wd\n output reg [2:0] calib_cmd,\n // calib_aux_out used for CKE and ODT\n output reg [3:0] calib_aux_out,\n output reg [1:0] calib_odt ,\n output reg [nCK_PER_CLK-1:0] calib_cke ,\n output [1:0] calib_rank_cnt,\n output reg [1:0] calib_cas_slot,\n output reg [5:0] calib_data_offset_0,\n output reg [5:0] calib_data_offset_1,\n output reg [5:0] calib_data_offset_2,\n // PHY OUT_FIFO\n output reg calib_wrdata_en,\n output reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_wrdata,\n // PHY Read\n output phy_rddata_en,\n output phy_rddata_valid,\n output [255:0] dbg_phy_init,\n input reset_rd_addr,\n //OCAL centering calibration\n input oclkdelay_center_calib_start,\n input oclk_center_write_resume,\n input oclkdelay_center_calib_done,\n input rdlvl_pi_incdec, //rdlvl pi dec \n input complex_pi_incdec_done,\n input num_samples_done_r,\n input complex_init_pi_dec_done,\n output reg complex_act_start,\n output reg calib_tap_inc_start,\n output reg calib_tap_end_if_reset,\n input calib_tap_inc_done\n );\n\n//*****************************************************************************\n// Assertions to be added\n//***************************************************************************** \n// The phy_ctl_full signal must never be asserted in synchronous mode of \n// operation either 4:1 or 2:1\n//\n// The RANKS parameter must never be set to '0' by the user \n// valid values: 1 to 4\n//\n//*****************************************************************************\n\n //***************************************************************************\n \n // Number of Read level stage 1 writes limited to a SDRAM row\n // The address of Read Level stage 1 reads must also be limited\n // to a single SDRAM row\n // (2^COL_WIDTH)/BURST_MODE = (2^10)/8 = 128\n localparam NUM_STG1_WR_RD = (BURST_MODE == \"8\") ? 4 :\n (BURST_MODE == \"4\") ? 8 : 4; \n\n\n localparam ADDR_INC = (BURST_MODE == \"8\") ? 8 :\n (BURST_MODE == \"4\") ? 4 : 8; \n \n // In a 2 slot dual rank per system RTT_NOM values \n // for Rank2 and Rank3 default to 40 ohms\n localparam RTT_NOM2 = \"40\";\n localparam RTT_NOM3 = \"40\";\n\n localparam RTT_NOM_int = (USE_ODT_PORT == 1) ? RTT_NOM : RTT_WR;\n\n // Specifically for use with half-frequency controller (nCK_PER_CLK=2)\n // = 1 if burst length = 4, = 0 if burst length = 8. Determines how\n // often row command needs to be issued during read-leveling\n // For DDR3 the burst length is fixed during calibration \n localparam BURST4_FLAG = (DRAM_TYPE == \"DDR3\")? 1'b0 : \n (BURST_MODE == \"8\") ? 1'b0 : \n ((BURST_MODE == \"4\") ? 1'b1 : 1'b0);\n \n\n\n\n //***************************************************************************\n // Counter values used to determine bus timing\n // NOTE on all counter terminal counts - these can/should be one less than \n // the actual delay to take into account extra clock cycle delay in \n // generating the corresponding \"done\" signal\n //***************************************************************************\n\n localparam CLK_MEM_PERIOD = CLK_PERIOD / nCK_PER_CLK;\n \n // Calculate initial delay required in number of CLK clock cycles\n // to delay initially. The counter is clocked by [CLK/1024] - which\n // is approximately division by 1000 - note that the formulas below will\n // result in more than the minimum wait time because of this approximation.\n // NOTE: For DDR3 JEDEC specifies to delay reset\n // by 200us, and CKE by an additional 500us after power-up\n // For DDR2 CKE is delayed by 200us after power up.\n localparam DDR3_RESET_DELAY_NS = 200000;\n localparam DDR3_CKE_DELAY_NS = 500000 + DDR3_RESET_DELAY_NS;\n localparam DDR2_CKE_DELAY_NS = 200000;\n localparam PWRON_RESET_DELAY_CNT = \n ((DDR3_RESET_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD);\n localparam PWRON_CKE_DELAY_CNT = (DRAM_TYPE == \"DDR3\") ?\n (((DDR3_CKE_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD)) :\n (((DDR2_CKE_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD));\n // FOR DDR2 -1 taken out. With -1 not getting 200us. The equation\n // needs to be reworked. \n localparam DDR2_INIT_PRE_DELAY_PS = 400000;\n localparam DDR2_INIT_PRE_CNT = \n ((DDR2_INIT_PRE_DELAY_PS+CLK_PERIOD-1)/CLK_PERIOD)-1;\n \n // Calculate tXPR time: reset from CKE HIGH to valid command after power-up\n // tXPR = (max(5nCK, tRFC(min)+10ns). Add a few (blah, messy) more clock\n // cycles because this counter actually starts up before CKE is asserted\n // to memory.\n localparam TXPR_DELAY_CNT =\n (5*CLK_MEM_PERIOD > tRFC+10000) ?\n (((5+nCK_PER_CLK-1)/nCK_PER_CLK)-1)+11 :\n (((tRFC+10000+CLK_PERIOD-1)/CLK_PERIOD)-1)+11;\n\n // tDLLK/tZQINIT time = 512*tCK = 256*tCLKDIV\n localparam TDLLK_TZQINIT_DELAY_CNT = 255;\n \n // TWR values in ns. Both DDR2 and DDR3 have the same value.\n // 15000ns/tCK\n localparam TWR_CYC = ((15000) % CLK_MEM_PERIOD) ?\n (15000/CLK_MEM_PERIOD) + 1 : 15000/CLK_MEM_PERIOD;\n \n // time to wait between consecutive commands in PHY_INIT - this is a\n // generic number, and must be large enough to account for worst case\n // timing parameter (tRFC - refresh-to-active) across all memory speed\n // grades and operating frequencies. Expressed in clk \n // (Divided by 4 or Divided by 2) clock cycles. \n localparam CNTNEXT_CMD = 7'b1111111;\n \n // Counter values to keep track of which MR register to load during init\n // Set value of INIT_CNT_MR_DONE to equal value of counter for last mode\n // register configured during initialization. \n // NOTE: Reserve more bits for DDR2 - more MR accesses for DDR2 init\n localparam INIT_CNT_MR2 = 2'b00;\n localparam INIT_CNT_MR3 = 2'b01;\n localparam INIT_CNT_MR1 = 2'b10;\n localparam INIT_CNT_MR0 = 2'b11;\n localparam INIT_CNT_MR_DONE = 2'b11;\n\n // Register chip programmable values for DDR3\n // The register chip for the registered DIMM needs to be programmed\n // before the initialization of the registered DIMM.\n // Address for the control word is in : DBA2, DA2, DA1, DA0\n // Data for the control word is in: DBA1 DBA0, DA4, DA3\n // The values will be stored in the local param in the following format\n // {DBA[2:0], DA[4:0]}\n \n // RC0 is global features control word. Address == 000\n\n localparam REG_RC0 = 8'b00000000;\n \n // RC1 Clock driver enable control word. Enables or disables the four\n // output clocks in the register chip. For single rank and dual rank\n // two clocks will be enabled and for quad rank all the four clocks\n // will be enabled. Address == 000. Data = 0110 for single and dual rank.\n // = 0000 for quad rank \n localparam REG_RC1 = 8'b00000001;\n\n // RC2 timing control word. Set in 1T timing mode\n // Address = 010. Data = 0000\n localparam REG_RC2 = 8'b00000010;\n \n // RC3 timing control word. Setting the data based on number of RANKS (inturn the number of loads)\n // This setting is specific to RDIMMs from Micron Technology\n localparam REG_RC3 = (RANKS >= 2) ? 8'b00101011 : 8'b00000011;\n\n // RC4 timing control work. Setting the data based on number of RANKS (inturn the number of loads)\n // This setting is specific to RDIMMs from Micron Technology\n localparam REG_RC4 = (RANKS >= 2) ? 8'b00101100 : 8'b00000100;\n \n // RC5 timing control work. Setting the data based on number of RANKS (inturn the number of loads)\n // This setting is specific to RDIMMs from Micron Technology\n localparam REG_RC5 = (RANKS >= 2) ? 8'b00101101 : 8'b00000101; \n \n // RC10 timing control work. Setting the data to 0000 \n localparam [3:0] FREQUENCY_ENCODING = (tCK >= 1072 && tCK < 1250) ? 4'b0100 : \n (tCK >= 1250 && tCK < 1500) ? 4'b0011 :\n (tCK >= 1500 && tCK < 1875) ? 4'b0010 :\n (tCK >= 1875 && tCK < 2500) ? 4'b0001 : 4'b0000;\n\n localparam REG_RC10 = {1'b1,FREQUENCY_ENCODING,3'b010}; \n\n localparam VREF_ENCODING = (VREF == \"INTERNAL\") ? 1'b1 : 1'b0;\n localparam [3:0] DDR3_VOLTAGE_ENCODING = (DDR3_VDD_OP_VOLT == \"125\") ? {1'b0,VREF_ENCODING,2'b10} :\n (DDR3_VDD_OP_VOLT == \"135\") ? {1'b0,VREF_ENCODING,2'b01} : \n {1'b0,VREF_ENCODING,2'b00} ;\n\n localparam REG_RC11 = {1'b1,DDR3_VOLTAGE_ENCODING,3'b011};\n\n // For non-zero AL values\n localparam nAL = (AL == \"CL-1\") ? nCL - 1 : 0; \n\n // Adding the register dimm latency to write latency\n localparam CWL_M = (REG_CTRL == \"ON\") ? nCWL + nAL + 1 : nCWL + nAL;\n\n // Count value to generate pi_phase_locked_err signal\n localparam PHASELOCKED_TIMEOUT = (SIM_CAL_OPTION == \"NONE\") ? 16383 : 1000; \n\n // Timeout interval for detecting error with Traffic Generator\n localparam [13:0] TG_TIMER_TIMEOUT \n = (SIM_CAL_OPTION == \"NONE\") ? 14'h3FFF : 14'h0001;\n \n //bit num per DQS\n localparam DQ_PER_DQS = DQ_WIDTH/DQS_WIDTH;\n\n //COMPLEX_ROW_CNT_BYTE\n localparam COMPLEX_ROW_CNT_BYTE = (FIXED_VICTIM==\"FALSE\")? DQ_PER_DQS*2: 2;\n localparam COMPLEX_RD = (FIXED_VICTIM==\"FALSE\")? DQ_PER_DQS : 1; \n \n // Master state machine encoding\n localparam INIT_IDLE = 7'b0000000; //0\n localparam INIT_WAIT_CKE_EXIT = 7'b0000001; //1\n localparam INIT_LOAD_MR = 7'b0000010; //2\n localparam INIT_LOAD_MR_WAIT = 7'b0000011; //3\n localparam INIT_ZQCL = 7'b0000100; //4\n localparam INIT_WAIT_DLLK_ZQINIT = 7'b0000101; //5\n localparam INIT_WRLVL_START = 7'b0000110; //6\n localparam INIT_WRLVL_WAIT = 7'b0000111; //7\n localparam INIT_WRLVL_LOAD_MR = 7'b0001000; //8\n localparam INIT_WRLVL_LOAD_MR_WAIT = 7'b0001001; //9\n localparam INIT_WRLVL_LOAD_MR2 = 7'b0001010; //A\n localparam INIT_WRLVL_LOAD_MR2_WAIT = 7'b0001011; //B\n localparam INIT_RDLVL_ACT = 7'b0001100; //C\n localparam INIT_RDLVL_ACT_WAIT = 7'b0001101; //D\n localparam INIT_RDLVL_STG1_WRITE = 7'b0001110; //E\n localparam INIT_RDLVL_STG1_WRITE_READ = 7'b0001111; //F\n localparam INIT_RDLVL_STG1_READ = 7'b0010000; //10\n localparam INIT_RDLVL_STG2_READ = 7'b0010001; //11\n localparam INIT_RDLVL_STG2_READ_WAIT = 7'b0010010; //12\n localparam INIT_PRECHARGE_PREWAIT = 7'b0010011; //13\n localparam INIT_PRECHARGE = 7'b0010100; //14\n localparam INIT_PRECHARGE_WAIT = 7'b0010101; //15\n localparam INIT_DONE = 7'b0010110; //16\n localparam INIT_DDR2_PRECHARGE = 7'b0010111; //17\n localparam INIT_DDR2_PRECHARGE_WAIT = 7'b0011000; //18\n localparam INIT_REFRESH = 7'b0011001; //19\n localparam INIT_REFRESH_WAIT = 7'b0011010; //1A\n localparam INIT_REG_WRITE = 7'b0011011; //1B\n localparam INIT_REG_WRITE_WAIT = 7'b0011100; //1C\n localparam INIT_DDR2_MULTI_RANK = 7'b0011101; //1D\n localparam INIT_DDR2_MULTI_RANK_WAIT = 7'b0011110; //1E\n localparam INIT_WRCAL_ACT = 7'b0011111; //1F\n localparam INIT_WRCAL_ACT_WAIT = 7'b0100000; //20\n localparam INIT_WRCAL_WRITE = 7'b0100001; //21\n localparam INIT_WRCAL_WRITE_READ = 7'b0100010; //22\n localparam INIT_WRCAL_READ = 7'b0100011; //23\n localparam INIT_WRCAL_READ_WAIT = 7'b0100100; //24\n localparam INIT_WRCAL_MULT_READS = 7'b0100101; //25\n localparam INIT_PI_PHASELOCK_READS = 7'b0100110; //26\n localparam INIT_MPR_RDEN = 7'b0100111; //27\n localparam INIT_MPR_WAIT = 7'b0101000; //28\n localparam INIT_MPR_READ = 7'b0101001; //29\n localparam INIT_MPR_DISABLE_PREWAIT = 7'b0101010; //2A\n localparam INIT_MPR_DISABLE = 7'b0101011; //2B\n localparam INIT_MPR_DISABLE_WAIT = 7'b0101100; //2C\n localparam INIT_OCLKDELAY_ACT = 7'b0101101; //2D\n localparam INIT_OCLKDELAY_ACT_WAIT = 7'b0101110; //2E\n localparam INIT_OCLKDELAY_WRITE = 7'b0101111; //2F\n localparam INIT_OCLKDELAY_WRITE_WAIT = 7'b0110000; //30\n localparam INIT_OCLKDELAY_READ = 7'b0110001; //31\n localparam INIT_OCLKDELAY_READ_WAIT = 7'b0110010; //32\n localparam INIT_REFRESH_RNK2_WAIT = 7'b0110011; //33\n localparam INIT_RDLVL_COMPLEX_PRECHARGE = 7'b0110100; //34\n localparam INIT_RDLVL_COMPLEX_PRECHARGE_WAIT = 7'b0110101; //35\n localparam INIT_RDLVL_COMPLEX_ACT = 7'b0110110; //36\n localparam INIT_RDLVL_COMPLEX_ACT_WAIT = 7'b0110111; //37\n localparam INIT_RDLVL_COMPLEX_READ = 7'b0111000; //38\n localparam INIT_RDLVL_COMPLEX_READ_WAIT = 7'b0111001; //39\n localparam INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT = 7'b0111010; //3A\n localparam INIT_OCAL_COMPLEX_ACT = 7'b0111011; //3B\n localparam INIT_OCAL_COMPLEX_ACT_WAIT = 7'b0111100; //3C\n localparam INIT_OCAL_COMPLEX_WRITE_WAIT = 7'b0111101; //3D \n localparam INIT_OCAL_COMPLEX_RESUME_WAIT = 7'b0111110; //3E \n localparam INIT_OCAL_CENTER_ACT = 7'b0111111; //3F \n localparam INIT_OCAL_CENTER_WRITE = 7'b1000000; //40\n localparam INIT_OCAL_CENTER_WRITE_WAIT = 7'b1000001; //41\n localparam INIT_OCAL_CENTER_ACT_WAIT = 7'b1000010; //42 \n localparam INIT_RDLVL_COMPLEX_PI_WAIT = 7'b1000011; //43\n localparam INIT_SKIP_CALIB_WAIT = 7'b1000100; //44 \n\n integer i, j, k, l, m, n, p, q;\n\n reg pi_dqs_found_all_r;\n (* ASYNC_REG = \"TRUE\" *) reg pi_phase_locked_all_r1;\n (* ASYNC_REG = \"TRUE\" *) reg pi_phase_locked_all_r2;\n (* ASYNC_REG = \"TRUE\" *) reg pi_phase_locked_all_r3;\n (* ASYNC_REG = \"TRUE\" *) reg pi_phase_locked_all_r4;\n reg pi_calib_rank_done_r;\n reg [13:0] pi_phaselock_timer;\n reg stg1_wr_done;\n reg rnk_ref_cnt;\n reg pi_dqs_found_done_r1;\n reg pi_dqs_found_rank_done_r;\n reg read_calib_int;\n reg read_calib_r;\n reg pi_calib_done_r;\n reg pi_calib_done_r1;\n reg burst_addr_r; \n reg [1:0] chip_cnt_r;\n reg [6:0] cnt_cmd_r;\n reg cnt_cmd_done_r; \n reg cnt_cmd_done_m7_r;\n reg [7:0] cnt_dllk_zqinit_r;\n reg cnt_dllk_zqinit_done_r;\n reg cnt_init_af_done_r; \n reg [1:0] cnt_init_af_r;\n reg [1:0] cnt_init_data_r; \n reg [1:0] cnt_init_mr_r;\n reg cnt_init_mr_done_r;\n reg cnt_init_pre_wait_done_r;\n reg [7:0] cnt_init_pre_wait_r; \n reg [9:0] cnt_pwron_ce_r; \n reg cnt_pwron_cke_done_r;\n reg cnt_pwron_cke_done_r1; \n reg [8:0] cnt_pwron_r; \n reg cnt_pwron_reset_done_r; \n reg cnt_txpr_done_r; \n reg [7:0] cnt_txpr_r;\n reg ddr2_pre_flag_r;\n reg ddr2_refresh_flag_r;\n reg ddr3_lm_done_r;\n reg [4:0] enable_wrlvl_cnt;\n reg init_complete_r;\n reg init_complete_r1;\n reg init_complete_r2;\n(* keep = \"true\" *) reg init_complete_r_timing;\n(* keep = \"true\" *) reg init_complete_r1_timing;\n reg [6:0] init_next_state; \n reg [6:0] init_state_r;\n reg [6:0] init_state_r1;\n wire [15:0] load_mr0;\n wire [15:0] load_mr1;\n wire [15:0] load_mr2;\n wire [15:0] load_mr3;\n reg mem_init_done_r;\n reg [1:0] mr2_r [0:3];\n reg [2:0] mr1_r [0:3];\n reg new_burst_r;\n reg [15:0] wrcal_start_dly_r;\n wire wrcal_start_pre;\n reg wrcal_resume_r;\n // Only one ODT signal per rank in PHY Control Block\n reg [nCK_PER_CLK-1:0] phy_tmp_odt_r;\n reg [nCK_PER_CLK-1:0] phy_tmp_odt_r1;\n \n reg [CS_WIDTH*nCS_PER_RANK-1:0] phy_tmp_cs1_r;\n reg [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_int_cs_n;\n wire prech_done_pre;\n reg [15:0] prech_done_dly_r; \n reg prech_pending_r;\n reg prech_req_posedge_r; \n reg prech_req_r; \n reg pwron_ce_r;\n reg first_rdlvl_pat_r;\n reg first_wrcal_pat_r;\n reg phy_wrdata_en;\n reg phy_wrdata_en_r1;\n reg [1:0] wrdata_pat_cnt;\n reg [1:0] wrcal_pat_cnt;\n reg [ROW_WIDTH-1:0] address_w;\n reg [BANK_WIDTH-1:0] bank_w;\n reg rdlvl_stg1_done_r1;\n reg rdlvl_stg1_start_int;\n reg [15:0] rdlvl_start_dly0_r;\n reg rdlvl_start_pre;\n reg rdlvl_last_byte_done_r;\n wire rdlvl_rd;\n wire rdlvl_wr;\n reg rdlvl_wr_r;\n wire rdlvl_wr_rd;\n reg [3:0] reg_ctrl_cnt_r;\n reg [1:0] tmp_mr2_r [0:3];\n reg [2:0] tmp_mr1_r [0:3];\n reg wrlvl_done_r;\n reg wrlvl_done_r1;\n reg wrlvl_rank_done_r1;\n reg wrlvl_rank_done_r2;\n reg wrlvl_rank_done_r3;\n reg wrlvl_rank_done_r4;\n reg wrlvl_rank_done_r5;\n reg wrlvl_rank_done_r6;\n reg wrlvl_rank_done_r7;\n reg [2:0] wrlvl_rank_cntr;\n reg wrlvl_odt_ctl;\n reg wrlvl_odt;\n reg wrlvl_active;\n reg wrlvl_active_r1;\n reg [2:0] num_reads;\n reg temp_wrcal_done_r;\n reg temp_lmr_done;\n reg extend_cal_pat;\n reg [13:0] tg_timer;\n reg tg_timer_go;\n reg cnt_wrcal_rd;\n reg [3:0] cnt_wait;\n reg [7:0] wrcal_reads;\n reg [8:0] stg1_wr_rd_cnt;\n reg phy_data_full_r;\n reg wr_level_dqs_asrt;\n reg wr_level_dqs_asrt_r1;\n reg [1:0] dqs_asrt_cnt;\n\n\n reg [3:0] num_refresh;\n wire oclkdelay_calib_start_pre;\n reg [15:0] oclkdelay_start_dly_r;\n reg [3:0] oclk_wr_cnt;\n reg [3:0] wrcal_wr_cnt;\n reg wrlvl_final_r;\n\n \n reg prbs_rdlvl_done_r1;\n reg prbs_rdlvl_done_r2;\n reg prbs_rdlvl_done_r3;\n reg prbs_last_byte_done_r;\n reg phy_if_empty_r;\n reg prbs_pat_resume_int;\n reg complex_row0_wr_done;\n reg complex_row1_wr_done;\n reg complex_row0_rd_done;\n reg complex_row1_rd_done;\n reg complex_row0_rd_done_r1;\n reg [3:0] complex_wait_cnt;\n reg [3:0] complex_num_reads;\n reg [3:0] complex_num_reads_dec;\n reg [ROW_WIDTH-1:0] complex_address;\n reg wr_victim_inc;\n reg [2:0] wr_victim_sel;\n reg [7:0] complex_row_cnt;\n\n reg complex_sample_cnt_inc_r1;\n reg complex_sample_cnt_inc_r2;\n reg complex_odt_ext;\n reg complex_ocal_odt_ext;\n\n reg wrcal_final_chk;\n wire prech_req;\n\n reg reset_rd_addr_r1;\n reg complex_rdlvl_int_ref_req;\n reg ext_int_ref_req;\n\n //complex OCLK delay calibration\n reg [7:0] complex_row_cnt_ocal;\n reg [4:0] complex_num_writes;\n reg [4:0] complex_num_writes_dec;\n reg complex_oclkdelay_calib_start_int; \n reg complex_oclkdelay_calib_start_r1;\n reg complex_oclkdelay_calib_start_r2; \n reg complex_oclkdelay_calib_done_r1;\n // reg [DQS_CNT_WIDTH:0] wr_byte_cnt_ocal;\n reg [2:0] wr_victim_sel_ocal;\n \n reg complex_row1_rd_done_r1; //time for switch to write\n reg [2:0] complex_row1_rd_cnt; //row1 read number for the byte (8 (16 rows) row1)\n reg complex_byte_rd_done; //read for the byte is done\n reg complex_byte_rd_done_r1; \n // reg complex_row_change; //every 16 rows of read, it is set to \"0\" for write\n reg ocal_num_samples_inc; //1 read/write is done\n reg complex_ocal_wr_start; //indicate complex ocal write is started. used for prbs rd addr gen\n\n reg prbs_rdlvl_done_pulse; //rising edge for prbs_rdlvl_done. used for pipelining\n reg prech_done_r1, prech_done_r2, prech_done_r3;\n reg mask_lim_done;\n reg complex_mask_lim_done;\n reg oclkdelay_calib_start_int;\n reg [REFRESH_TIMER_WIDTH-1:0] oclkdelay_ref_cnt;\n reg oclkdelay_int_ref_req;\n reg [3:0] ocal_act_wait_cnt;\n reg oclk_calib_resume_level;\n reg ocal_last_byte_done;\n wire mmcm_wr; //MMCM centering write. no CS will be set\n\n wire exit_ocal_complex_resume_wait = \n init_state_r == INIT_OCAL_COMPLEX_RESUME_WAIT && complex_oclk_calib_resume;\n\n reg calib_tap_inc_done_r1;\n\n\n \n //***************************************************************************\n // Debug\n //***************************************************************************\n\n //synthesis translate_off\n always @(posedge mem_init_done_r) begin \n if (!rst)\n $display (\"PHY_INIT: Memory Initialization completed at %t\", $time);\n end\n\n always @(posedge wrlvl_done) begin\n if (!rst && (WRLVL == \"ON\"))\n $display (\"PHY_INIT: Write Leveling completed at %t\", $time);\n end\n\n always @(posedge rdlvl_stg1_done) begin\n if (!rst) \n $display (\"PHY_INIT: Read Leveling Stage 1 completed at %t\", $time);\n end\n \n always @(posedge mpr_rdlvl_done) begin\n if (!rst) \n $display (\"PHY_INIT: MPR Read Leveling completed at %t\", $time);\n end\n \n always @(posedge oclkdelay_calib_done) begin\n if (!rst) \n $display (\"PHY_INIT: OCLKDELAY calibration completed at %t\", $time);\n end\n\n always @(posedge pi_calib_done_r1) begin\n if (!rst) \n $display (\"PHY_INIT: Phaser_In Phase Locked at %t\", $time);\n end\n \n always @(posedge pi_dqs_found_done) begin\n if (!rst) \n $display (\"PHY_INIT: Phaser_In DQSFOUND completed at %t\", $time);\n end\n\n always @(posedge wrcal_done) begin\n if (!rst && (WRLVL == \"ON\"))\n $display (\"PHY_INIT: Write Calibration completed at %t\", $time);\n end \n\n always@(posedge prbs_rdlvl_done)begin\n if(!rst)\n \t$display(\"PHY_INIT : PRBS/PER_BIT calibration completed at %t\",$time);\n end \n\n\n always@(posedge complex_oclkdelay_calib_done)begin\n if(!rst)\n \t$display(\"PHY_INIT : COMPLEX OCLKDELAY calibration completed at %t\",$time);\n end \n always@(posedge oclkdelay_center_calib_done)begin\n if(!rst)\n \t$display(\"PHY_INIT : OCLKDELAY CENTER CALIB calibration completed at %t\",$time);\n end \n \n //synthesis translate_on\n\n assign dbg_phy_init[5:0] = init_state_r;\n assign dbg_phy_init[6+:8] = complex_row_cnt;\n assign dbg_phy_init[14+:3] = victim_sel;\n assign dbg_phy_init[17+:4] = victim_byte_cnt;\n assign dbg_phy_init[21+:9] = stg1_wr_rd_cnt[8:0]; \n assign dbg_phy_init[30+:15] = complex_address;\n assign dbg_phy_init[(30+15)+:15] = phy_address[14:0];\n assign dbg_phy_init[60] =prbs_rdlvl_prech_req ;\n assign dbg_phy_init[61] =prech_req_posedge_r ;\n\n\n //***************************************************************************\n // DQS count to be sent to hard PHY during Phaser_IN Phase Locking stage\n //***************************************************************************\n \n// assign pi_phaselock_calib_cnt = dqs_cnt_r;\n \n assign pi_calib_done = pi_calib_done_r1;\n \n //prevent PI incdec during complex read\n always @ (posedge clk) \n complex_act_start <= #TCQ (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (init_state_r == INIT_RDLVL_COMPLEX_PI_WAIT);\n\n //detect rising edge of prbs_rdlvl_done to reset all control sighals\n always @ (posedge clk) begin\n prbs_rdlvl_done_pulse <= #TCQ prbs_rdlvl_done & ~prbs_rdlvl_done_r1;\n end\n \n always @(posedge clk) begin\n if (rst)\n wrcal_final_chk <= #TCQ 1'b0;\n else if ((init_next_state == INIT_WRCAL_ACT) && (wrcal_done || (SKIP_CALIB == \"TRUE\")) && \n (DRAM_TYPE == \"DDR3\"))\n wrcal_final_chk <= #TCQ 1'b1;\n end\n\n always @(posedge clk) begin\n rdlvl_stg1_done_r1 <= #TCQ rdlvl_stg1_done;\n prbs_rdlvl_done_r1 <= #TCQ prbs_rdlvl_done;\n\tprbs_rdlvl_done_r2 <= #TCQ prbs_rdlvl_done_r1;\n\tprbs_rdlvl_done_r3 <= #TCQ prbs_rdlvl_done_r2;\n wrcal_resume_r <= #TCQ wrcal_resume;\n wrcal_sanity_chk <= #TCQ wrcal_final_chk;\n end\n \n always @(posedge clk) begin\n if (rst)\n mpr_end_if_reset <= #TCQ 1'b0;\n else if (mpr_last_byte_done && (num_refresh != 'd0))\n mpr_end_if_reset <= #TCQ 1'b1;\n else\n mpr_end_if_reset <= #TCQ 1'b0;\n end\n \n // Siganl to mask memory model error for Invalid latching edge\n\n always @(posedge clk)\n if (rst)\n calib_writes <= #TCQ 1'b0;\n else if ((init_state_r == INIT_OCLKDELAY_WRITE) || \n (init_state_r == INIT_OCAL_CENTER_WRITE) || \n (init_state_r == INIT_RDLVL_STG1_WRITE) ||\n (init_state_r == INIT_RDLVL_STG1_WRITE_READ) ||\n (init_state_r == INIT_WRCAL_WRITE) ||\n (init_state_r == INIT_WRCAL_WRITE_READ))\n calib_writes <= #TCQ 1'b1;\n else\n calib_writes <= #TCQ 1'b0;\n\n always @(posedge clk)\n if (rst)\n wrcal_rd_wait <= #TCQ 1'b0;\n else if (init_state_r == INIT_WRCAL_READ_WAIT)\n wrcal_rd_wait <= #TCQ 1'b1;\n else\n wrcal_rd_wait <= #TCQ 1'b0;\n \n //***************************************************************************\n // Signal PHY completion when calibration is finished\n // Signal assertion is delayed by four clock cycles to account for the\n // multi cycle path constraint to (phy_init_data_sel) signal. \n //***************************************************************************\n \n always @(posedge clk)\n if (rst) begin\n init_complete_r <= #TCQ 1'b0;\n init_complete_r_timing <= #TCQ 1'b0;\n init_complete_r1 <= #TCQ 1'b0;\n init_complete_r1_timing <= #TCQ 1'b0; \n init_complete_r2 <= #TCQ 1'b0;\n init_calib_complete <= #TCQ 1'b0;\n end else begin\n if (init_state_r == INIT_DONE) begin\n init_complete_r <= #TCQ 1'b1;\n init_complete_r_timing <= #TCQ 1'b1;\n end\n init_complete_r1 <= #TCQ init_complete_r;\n init_complete_r1_timing <= #TCQ init_complete_r_timing; \n init_complete_r2 <= #TCQ init_complete_r1; \n init_calib_complete <= #TCQ init_complete_r2;\n end \n\n always @ (posedge clk)\n if (rst) \n complex_oclkdelay_calib_done_r1 <= #TCQ 1'b0;\n else\n complex_oclkdelay_calib_done_r1 <= #TCQ complex_oclkdelay_calib_done;\n\n //reset read address for starting complex ocaldealy calib \n always @ (posedge clk) begin\n complex_ocal_reset_rd_addr <= #TCQ ((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && (complex_wait_cnt == 'd9)) || (prbs_last_byte_done && ~prbs_last_byte_done_r);\n \n end\n\n //first write for complex oclkdealy calib\n always @ (posedge clk) begin\n if (rst)\n complex_ocal_wr_start <= #TCQ 'b0;\n else\n complex_ocal_wr_start <= #TCQ complex_ocal_reset_rd_addr? 1'b1 : complex_ocal_wr_start;\n end\n\n //ocal stg3 centering start\n// always @ (posedge clk) \n// if(rst) oclkdelay_center_calib_start <= #TCQ 1'b0;\n// else\n// oclkdelay_center_calib_start <= #TCQ ((init_state_r == INIT_OCAL_CENTER_ACT) && lim_done)? 1'b1: oclkdelay_center_calib_start;\n \n //***************************************************************************\n // Instantiate FF for the phy_init_data_sel signal. A multi cycle path \n // constraint will be assigned to this signal. This signal will only be \n // used within the PHY \n //***************************************************************************\n\n// FDRSE u_ff_phy_init_data_sel\n// (\n// .Q (phy_init_data_sel),\n// .C (clk),\n// .CE (1'b1),\n// .D (init_complete_r),\n// .R (1'b0),\n// .S (1'b0)\n// ) /* synthesis syn_preserve=1 */\n// /* synthesis syn_replicate = 0 */;\n\n \n //***************************************************************************\n // Mode register programming\n //***************************************************************************\n \n //*****************************************************************\n // DDR3 Load mode reg0\n // Mode Register (MR0):\n // [15:13] - unused - 000\n // [12] - Precharge Power-down DLL usage - 0 (DLL frozen, slow-exit), \n // 1 (DLL maintained)\n // [11:9] - write recovery for Auto Precharge (tWR/tCK = 6)\n // [8] - DLL reset - 0 or 1\n // [7] - Test Mode - 0 (normal)\n // [6:4],[2] - CAS latency - CAS_LAT\n // [3] - Burst Type - BURST_TYPE\n // [1:0] - Burst Length - BURST_LEN\n // DDR2 Load mode register\n // Mode Register (MR):\n // [15:14] - unused - 00\n // [13] - reserved - 0\n // [12] - Power-down mode - 0 (normal)\n // [11:9] - write recovery - write recovery for Auto Precharge\n // (tWR/tCK = 6)\n // [8] - DLL reset - 0 or 1\n // [7] - Test Mode - 0 (normal)\n // [6:4] - CAS latency - CAS_LAT\n // [3] - Burst Type - BURST_TYPE\n // [2:0] - Burst Length - BURST_LEN\n \n //*****************************************************************\n generate\n if(DRAM_TYPE == \"DDR3\") begin: gen_load_mr0_DDR3\n assign load_mr0[1:0] = (BURST_MODE == \"8\") ? 2'b00 :\n (BURST_MODE == \"OTF\") ? 2'b01 : \n (BURST_MODE == \"4\") ? 2'b10 : 2'b11;\n assign load_mr0[2] = (nCL >= 12) ? 1'b1 : 1'b0; // LSb of CAS latency\n assign load_mr0[3] = (BURST_TYPE == \"SEQ\") ? 1'b0 : 1'b1;\n assign load_mr0[6:4] = ((nCL == 5) || (nCL == 13)) ? 3'b001 :\n ((nCL == 6) || (nCL == 14)) ? 3'b010 : \n (nCL == 7) ? 3'b011 : \n (nCL == 8) ? 3'b100 :\n (nCL == 9) ? 3'b101 :\n (nCL == 10) ? 3'b110 : \n (nCL == 11) ? 3'b111 : \n (nCL == 12) ? 3'b000 : 3'b111;\n assign load_mr0[7] = 1'b0;\n assign load_mr0[8] = 1'b1; // Reset DLL (init only) \n assign load_mr0[11:9] = (TWR_CYC == 5) ? 3'b001 :\n (TWR_CYC == 6) ? 3'b010 : \n (TWR_CYC == 7) ? 3'b011 :\n (TWR_CYC == 8) ? 3'b100 :\n (TWR_CYC == 9) ? 3'b101 :\n (TWR_CYC == 10) ? 3'b101 :\n (TWR_CYC == 11) ? 3'b110 : \n (TWR_CYC == 12) ? 3'b110 :\n (TWR_CYC == 13) ? 3'b111 :\n (TWR_CYC == 14) ? 3'b111 :\n (TWR_CYC == 15) ? 3'b000 :\n (TWR_CYC == 16) ? 3'b000 : 3'b010;\n assign load_mr0[12] = 1'b0; // Precharge Power-Down DLL 'slow-exit'\n assign load_mr0[15:13] = 3'b000;\n end else if (DRAM_TYPE == \"DDR2\") begin: gen_load_mr0_DDR2 // block: gen\n assign load_mr0[2:0] = (BURST_MODE == \"8\") ? 3'b011 :\n (BURST_MODE == \"4\") ? 3'b010 : 3'b111;\n assign load_mr0[3] = (BURST_TYPE == \"SEQ\") ? 1'b0 : 1'b1; \n assign load_mr0[6:4] = (nCL == 3) ? 3'b011 :\n (nCL == 4) ? 3'b100 :\n (nCL == 5) ? 3'b101 : \n (nCL == 6) ? 3'b110 : 3'b111;\n assign load_mr0[7] = 1'b0;\n assign load_mr0[8] = 1'b1; // Reset DLL (init only)\n assign load_mr0[11:9] = (TWR_CYC == 2) ? 3'b001 :\n (TWR_CYC == 3) ? 3'b010 :\n (TWR_CYC == 4) ? 3'b011 :\n (TWR_CYC == 5) ? 3'b100 : \n (TWR_CYC == 6) ? 3'b101 : 3'b010;\n assign load_mr0[15:12]= 4'b0000; // Reserved\n end\n endgenerate\n \n //*****************************************************************\n // DDR3 Load mode reg1\n // Mode Register (MR1):\n // [15:13] - unused - 00\n // [12] - output enable - 0 (enabled for DQ, DQS, DQS#)\n // [11] - TDQS enable - 0 (TDQS disabled and DM enabled)\n // [10] - reserved - 0 (must be '0')\n // [9] - RTT[2] - 0 \n // [8] - reserved - 0 (must be '0')\n // [7] - write leveling - 0 (disabled), 1 (enabled)\n // [6] - RTT[1] - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50)\n // [5] - Output driver impedance[1] - 0 (RZQ/6 and RZQ/7)\n // [4:3] - Additive CAS - ADDITIVE_CAS\n // [2] - RTT[0]\n // [1] - Output driver impedance[0] - 0(RZQ/6), or 1 (RZQ/7)\n // [0] - DLL enable - 0 (normal)\n // DDR2 ext mode register\n // Extended Mode Register (MR):\n // [15:14] - unused - 00\n // [13] - reserved - 0\n // [12] - output enable - 0 (enabled)\n // [11] - RDQS enable - 0 (disabled)\n // [10] - DQS# enable - 0 (enabled)\n // [9:7] - OCD Program - 111 or 000 (first 111, then 000 during init)\n // [6] - RTT[1] - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50)\n // [5:3] - Additive CAS - ADDITIVE_CAS\n // [2] - RTT[0]\n // [1] - Output drive - REDUCE_DRV (= 0(full), = 1 (reduced)\n // [0] - DLL enable - 0 (normal)\n //*****************************************************************\n \n generate\n if(DRAM_TYPE == \"DDR3\") begin: gen_load_mr1_DDR3\n assign load_mr1[0] = 1'b0; // DLL enabled during Imitialization\n assign load_mr1[1] = (OUTPUT_DRV == \"LOW\") ? 1'b0 : 1'b1; \n assign load_mr1[2] = ((RTT_NOM_int == \"30\") || (RTT_NOM_int == \"40\") || \n (RTT_NOM_int == \"60\")) ? 1'b1 : 1'b0;\n assign load_mr1[4:3] = (AL == \"0\") ? 2'b00 :\n (AL == \"CL-1\") ? 2'b01 :\n (AL == \"CL-2\") ? 2'b10 : 2'b11;\n assign load_mr1[5] = 1'b0; \n assign load_mr1[6] = ((RTT_NOM_int == \"40\") || (RTT_NOM_int == \"120\")) ? \n 1'b1 : 1'b0;\n assign load_mr1[7] = 1'b0; // Enable write lvl after init sequence\n assign load_mr1[8] = 1'b0;\n assign load_mr1[9] = ((RTT_NOM_int == \"20\") || (RTT_NOM_int == \"30\")) ?\n 1'b1 : 1'b0;\n assign load_mr1[10] = 1'b0;\n assign load_mr1[15:11] = 5'b00000;\n end else if (DRAM_TYPE == \"DDR2\") begin: gen_load_mr1_DDR2 \n assign load_mr1[0] = 1'b0; // DLL enabled during Imitialization\n assign load_mr1[1] = (OUTPUT_DRV == \"LOW\") ? 1'b1 : 1'b0; \n assign load_mr1[2] = ((RTT_NOM_int == \"75\") || (RTT_NOM_int == \"50\")) ?\n 1'b1 : 1'b0;\n assign load_mr1[5:3] = (AL == \"0\") ? 3'b000 :\n (AL == \"1\") ? 3'b001 :\n (AL == \"2\") ? 3'b010 :\n (AL == \"3\") ? 3'b011 :\n (AL == \"4\") ? 3'b100 : 3'b111; \n assign load_mr1[6] = ((RTT_NOM_int == \"50\") || \n (RTT_NOM_int == \"150\")) ? 1'b1 : 1'b0;\n assign load_mr1[9:7] = 3'b000;\n assign load_mr1[10] = (DDR2_DQSN_ENABLE == \"YES\") ? 1'b0 : 1'b1;\n assign load_mr1[15:11] = 5'b00000;\n\n end\n endgenerate\n\n //*****************************************************************\n // DDR3 Load mode reg2\n // Mode Register (MR2):\n // [15:11] - unused - 00\n // [10:9] - RTT_WR - 00 (Dynamic ODT off) \n // [8] - reserved - 0 (must be '0')\n // [7] - self-refresh temperature range - \n // 0 (normal), 1 (extended)\n // [6] - Auto Self-Refresh - 0 (manual), 1(auto)\n // [5:3] - CAS Write Latency (CWL) - \n // 000 (5 for 400 MHz device), \n // 001 (6 for 400 MHz to 533 MHz devices), \n // 010 (7 for 533 MHz to 667 MHz devices), \n // 011 (8 for 667 MHz to 800 MHz)\n // [2:0] - Partial Array Self-Refresh (Optional) - \n // 000 (full array)\n // Not used for DDR2 \n //*****************************************************************\n generate\n if(DRAM_TYPE == \"DDR3\") begin: gen_load_mr2_DDR3\n assign load_mr2[2:0] = 3'b000; \n assign load_mr2[5:3] = (nCWL == 5) ? 3'b000 :\n (nCWL == 6) ? 3'b001 : \n (nCWL == 7) ? 3'b010 : \n (nCWL == 8) ? 3'b011 : \n (nCWL == 9) ? 3'b100 :\n (nCWL == 10) ? 3'b101 :\n (nCWL == 11) ? 3'b110 : 3'b111;\n assign load_mr2[6] = 1'b0;\n assign load_mr2[7] = 1'b0;\n assign load_mr2[8] = 1'b0;\n // Dynamic ODT disabled\n assign load_mr2[10:9] = 2'b00;\n assign load_mr2[15:11] = 5'b00000;\n end else begin: gen_load_mr2_DDR2\n assign load_mr2[15:0] = 16'd0;\n end\n endgenerate\n \n //*****************************************************************\n // DDR3 Load mode reg3\n // Mode Register (MR3):\n // [15:3] - unused - All zeros\n // [2] - MPR Operation - 0(normal operation), 1(data flow from MPR)\n // [1:0] - MPR location - 00 (Predefined pattern)\n //*****************************************************************\n\n assign load_mr3[1:0] = 2'b00;\n assign load_mr3[2] = 1'b0;\n assign load_mr3[15:3] = 13'b0000000000000;\n \n // For multi-rank systems the rank being accessed during writes in \n // Read Leveling must be sent to phy_write for the bitslip logic\n assign calib_rank_cnt = chip_cnt_r;\n\n //***************************************************************************\n // Logic to begin initial calibration, and to handle precharge requests\n // during read-leveling (to avoid tRAS violations if individual read \n // levelling calibration stages take more than max{tRAS) to complete). \n //***************************************************************************\n\n // Assert when readback for each stage of read-leveling begins. However,\n // note this indicates only when the read command is issued and when\n // Phaser_IN has phase aligned FREQ_REF clock to read DQS. It does not\n // indicate when the read data is present on the bus (when this happens \n // after the read command is issued depends on CAS LATENCY) - there will \n // need to be some delay before valid data is present on the bus. \n// assign rdlvl_start_pre = (init_state_r == INIT_PI_PHASELOCK_READS);\n\n // Assert when read back for oclkdelay calibration begins\n assign oclkdelay_calib_start_pre = (init_state_r == INIT_OCAL_CENTER_ACT); //(init_state_r == INIT_OCLKDELAY_READ);\n \n // Assert when read back for write calibration begins\n assign wrcal_start_pre = (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS);\n \n // Common precharge signal done signal - pulses only when there has been\n // a precharge issued as a result of a PRECH_REQ pulse. Note also a common\n // PRECH_DONE signal is used for all blocks\n assign prech_done_pre = (((init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_STG1_WRITE_READ) || \n ((rdlvl_last_byte_done_r || prbs_last_byte_done_r) && (init_state_r == INIT_RDLVL_ACT_WAIT) && cnt_cmd_done_r) ||\n (dqs_found_prech_req && (init_state_r == INIT_RDLVL_ACT_WAIT)) ||\n (init_state_r == INIT_MPR_RDEN) ||\n ((init_state_r == INIT_WRCAL_ACT_WAIT) && cnt_cmd_done_r) ||\n (init_state_r == INIT_OCAL_CENTER_ACT) ||\n ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT) && complex_oclkdelay_calib_start_r1) ||\n ((init_state_r == INIT_OCLKDELAY_ACT_WAIT) && cnt_cmd_done_r) ||\n ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) && prbs_last_byte_done_r) || //prbs_rdlvl_done\n (wrlvl_final && (init_state_r == INIT_REFRESH_WAIT) && cnt_cmd_done_r && ~oclkdelay_calib_done)) &&\n prech_pending_r && \n !prech_req_posedge_r);\n \n always @(posedge clk)\n if (rst)\n\t calib_tap_inc_start <= #TCQ 1'b0;\n\telse if (init_state_r == INIT_SKIP_CALIB_WAIT)\n\t calib_tap_inc_start <= #TCQ 1'b1;\n\t \n always @(posedge clk)\n calib_tap_inc_done_r1 <= #TCQ calib_tap_inc_done;\n \n always @(posedge clk)\n if (rst || (init_state_r == INIT_WRCAL_WRITE))\n\t calib_tap_end_if_reset <= #TCQ 1'b0;\n\telse if (calib_tap_inc_done && ~calib_tap_inc_done_r1)\n\t calib_tap_end_if_reset <= #TCQ 1'b1;\n\n always @(posedge clk)\n if (rst)\n pi_phaselock_start <= #TCQ 1'b0;\n else if (init_state_r == INIT_PI_PHASELOCK_READS)\n pi_phaselock_start <= #TCQ 1'b1;\n \n // Delay start of each calibration by 16 clock cycles to ensure that when \n // calibration logic begins, read data is already appearing on the bus. \n // Each circuit should synthesize using an SRL16. Assume that reset is\n // long enough to clear contents of SRL16. \n always @(posedge clk) begin \n rdlvl_last_byte_done_r <= #TCQ rdlvl_last_byte_done; \n prbs_last_byte_done_r <= #TCQ prbs_last_byte_done; \n rdlvl_start_dly0_r <= #TCQ {rdlvl_start_dly0_r[14:0], \n rdlvl_start_pre};\n wrcal_start_dly_r <= #TCQ {wrcal_start_dly_r[14:0],\n wrcal_start_pre};\n oclkdelay_start_dly_r <= #TCQ {oclkdelay_start_dly_r[14:0],\n oclkdelay_calib_start_pre};\n prech_done_dly_r <= #TCQ {prech_done_dly_r[14:0], \n prech_done_pre};\n end\n \n always @(posedge clk)\n if (rst)\n oclkdelay_calib_start_int <= #TCQ 1'b0;\n else if (oclkdelay_start_dly_r[5])\n oclkdelay_calib_start_int <= #TCQ 1'b1;\n \n always @(posedge clk) begin\n if (rst)\n\t ocal_last_byte_done <= #TCQ 1'b0;\n\telse if ((complex_oclkdelay_calib_cnt == DQS_WIDTH-1) && oclkdelay_center_calib_done)\n\t ocal_last_byte_done <= #TCQ 1'b1;\n end\n\n always @(posedge clk) begin\n if (rst || (init_state_r == INIT_REFRESH) || prbs_rdlvl_done || ocal_last_byte_done || oclkdelay_center_calib_done)\n\t oclkdelay_ref_cnt <= #TCQ REFRESH_TIMER;\n\telse if (oclkdelay_calib_start_int) begin\n\t if (oclkdelay_ref_cnt > 'd0)\n\t oclkdelay_ref_cnt <= #TCQ oclkdelay_ref_cnt - 1;\n\t else\n\t oclkdelay_ref_cnt <= #TCQ REFRESH_TIMER;\n\tend\n end\n \n always @(posedge clk) begin\n if (rst || (init_state_r == INIT_OCAL_CENTER_ACT) || oclkdelay_calib_done || ocal_last_byte_done || oclkdelay_center_calib_done)\n\t oclkdelay_int_ref_req <= #TCQ 1'b0;\n\telse if (oclkdelay_ref_cnt == 'd1)\n\t oclkdelay_int_ref_req <= #TCQ 1'b1;\n end\n \n always @(posedge clk) begin\n if (rst)\n ocal_act_wait_cnt <= #TCQ 'd0;\n else if ((init_state_r == INIT_OCAL_CENTER_ACT_WAIT) && ocal_act_wait_cnt < 'd15)\n ocal_act_wait_cnt <= #TCQ ocal_act_wait_cnt + 1;\n else\n ocal_act_wait_cnt <= #TCQ 'd0;\n end\n \n always @(posedge clk) begin\n if (rst || (init_state_r == INIT_OCLKDELAY_READ))\n\t oclk_calib_resume_level <= #TCQ 1'b0;\n\telse if (oclk_calib_resume)\n\t oclk_calib_resume_level <= #TCQ 1'b1;\n end\n \n always @(posedge clk) begin\n if (rst || (init_state_r == INIT_RDLVL_ACT_WAIT) || prbs_rdlvl_done)\n\t complex_rdlvl_int_ref_req <= #TCQ 1'b0;\n\telse if (oclkdelay_ref_cnt == 'd1)\n//\t complex_rdlvl_int_ref_req <= #TCQ 1'b1;\n\t complex_rdlvl_int_ref_req <= #TCQ 1'b0; //temporary fix for read issue\n end\n \n always @(posedge clk) begin\n if (rst || (init_state_r == INIT_RDLVL_COMPLEX_READ))\n\t ext_int_ref_req <= #TCQ 1'b0;\n\telse if ((init_state_r == INIT_RDLVL_ACT_WAIT) && complex_rdlvl_int_ref_req)\n\t ext_int_ref_req <= #TCQ 1'b1;\n end\n \n\n always @(posedge clk) begin \n prech_done <= #TCQ prech_done_dly_r[15];\n\tprech_done_r1 <= #TCQ prech_done_dly_r[15];\n prech_done_r2 <= #TCQ prech_done_r1;\n\tprech_done_r3 <= #TCQ prech_done_r2;\n end\n\t \n\n always @(posedge clk)\n if (rst)\n mpr_rdlvl_start <= #TCQ 1'b0;\n else if (pi_dqs_found_done &&\n (init_state_r == INIT_MPR_READ))\n mpr_rdlvl_start <= #TCQ 1'b1;\n\n always @(posedge clk)\n phy_if_empty_r <= #TCQ phy_if_empty;\n\n always @(posedge clk)\n if (rst || \n ((stg1_wr_rd_cnt == 'd2) && ~stg1_wr_done) || prbs_rdlvl_done) \n prbs_gen_clk_en <= #TCQ 1'b0;\n else if ((~phy_if_empty_r && rdlvl_stg1_done_r1 && ~prbs_rdlvl_done) ||\n ((init_state_r == INIT_RDLVL_ACT_WAIT) && rdlvl_stg1_done_r1 && (cnt_cmd_r == 'd127)) ||\n ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && rdlvl_stg1_done_r1 && (complex_wait_cnt == 'd14)) \n || (init_state_r == INIT_RDLVL_COMPLEX_READ) || ((init_state_r == INIT_PRECHARGE_PREWAIT) && prbs_rdlvl_start)) \n prbs_gen_clk_en <= #TCQ 1'b1;\n \n //Enable for complex oclkdelay - used in prbs gen\n always @(posedge clk)\n if (rst || \n ((stg1_wr_rd_cnt == 'd2) && ~stg1_wr_done) || complex_oclkdelay_calib_done || \n (complex_wait_cnt == 'd15 && complex_num_writes == 1 && complex_ocal_wr_start) ||\n ( init_state_r == INIT_RDLVL_STG1_WRITE && complex_num_writes_dec == 'd2) || ~complex_ocal_wr_start ||\n (complex_byte_rd_done && init_state_r == INIT_RDLVL_COMPLEX_ACT ) ||\n\t (init_state_r != INIT_OCAL_COMPLEX_RESUME_WAIT && init_state_r1 == INIT_OCAL_COMPLEX_RESUME_WAIT) ||\n (init_state_r == INIT_OCAL_COMPLEX_ACT)) \n prbs_gen_oclk_clk_en <= #TCQ 1'b0;\n else if ((~phy_if_empty_r && ~complex_oclkdelay_calib_done && prbs_rdlvl_done_r1) || // changed for new algo 3/26\n ((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && (complex_wait_cnt == 'd14)) ||\n ((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (complex_wait_cnt == 'd14)) ||\n\t exit_ocal_complex_resume_wait ||\n ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && ~stg1_wr_done && ~complex_row1_wr_done && ~complex_ocal_num_samples_done_r && (complex_wait_cnt == 'd14)) \n || (init_state_r == INIT_RDLVL_COMPLEX_READ) )\n prbs_gen_oclk_clk_en <= #TCQ 1'b1;\n\ngenerate\nif (RANKS < 2) begin\n always @(posedge clk)\n if (rst) begin\n rdlvl_stg1_start <= #TCQ 1'b0;\n rdlvl_stg1_start_int <= #TCQ 1'b0;\n rdlvl_start_pre <= #TCQ 1'b0;\n prbs_rdlvl_start <= #TCQ 1'b0;\n end else begin \n if (pi_dqs_found_done && cnt_cmd_done_r &&\n (init_state_r == INIT_RDLVL_ACT_WAIT))\n rdlvl_stg1_start_int <= #TCQ 1'b1;\n if (pi_dqs_found_done &&\n (init_state_r == INIT_RDLVL_STG1_READ))begin\n rdlvl_start_pre <= #TCQ 1'b1;\n rdlvl_stg1_start <= #TCQ rdlvl_start_dly0_r[14];\n end \n if (pi_dqs_found_done && rdlvl_stg1_done && ~prbs_rdlvl_done &&\n (init_state_r == INIT_RDLVL_COMPLEX_PI_WAIT) && (WRLVL == \"ON\")) begin\n prbs_rdlvl_start <= #TCQ 1'b1;\n end \n end\nend else begin\n always @(posedge clk)\n if (rst || rdlvl_stg1_rank_done) begin\n rdlvl_stg1_start <= #TCQ 1'b0;\n rdlvl_stg1_start_int <= #TCQ 1'b0;\n rdlvl_start_pre <= #TCQ 1'b0;\n prbs_rdlvl_start <= #TCQ 1'b0;\n end else begin \n if (pi_dqs_found_done && cnt_cmd_done_r &&\n (init_state_r == INIT_RDLVL_ACT_WAIT))\n rdlvl_stg1_start_int <= #TCQ 1'b1;\n if (pi_dqs_found_done &&\n (init_state_r == INIT_RDLVL_STG1_READ))begin\n rdlvl_start_pre <= #TCQ 1'b1;\n rdlvl_stg1_start <= #TCQ rdlvl_start_dly0_r[14];\n end \n if (pi_dqs_found_done && rdlvl_stg1_done && ~prbs_rdlvl_done &&\n (init_state_r == INIT_RDLVL_COMPLEX_PI_WAIT) && (WRLVL == \"ON\")) begin\n prbs_rdlvl_start <= #TCQ 1'b1;\n end \n end\nend\nendgenerate\n\n\n always @(posedge clk) begin\n if (rst || dqsfound_retry || wrlvl_byte_redo) begin\n pi_dqs_found_start <= #TCQ 1'b0;\n wrcal_start <= #TCQ 1'b0;\n end else begin\n if (!pi_dqs_found_done && init_state_r == INIT_RDLVL_STG2_READ)\n pi_dqs_found_start <= #TCQ 1'b1;\n if (wrcal_start_dly_r[5])\n wrcal_start <= #TCQ 1'b1;\n end \n end // else: !if(rst)\n\n\n always @(posedge clk)\n if (rst)\n oclkdelay_calib_start <= #TCQ 1'b0;\n else if (oclkdelay_start_dly_r[5])\n oclkdelay_calib_start <= #TCQ 1'b1;\n \n always @(posedge clk)\n if (rst)\n pi_dqs_found_done_r1 <= #TCQ 1'b0;\n else\n pi_dqs_found_done_r1 <= #TCQ pi_dqs_found_done;\n\n \n always @(posedge clk)\n wrlvl_final_r <= #TCQ wrlvl_final;\n \n // Reset IN_FIFO after final write leveling to make sure the FIFO\n // pointers are initialized\n always @(posedge clk)\n if (rst || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_REFRESH))\n wrlvl_final_if_rst <= #TCQ 1'b0;\n else if (wrlvl_done_r && //(wrlvl_final_r && wrlvl_done_r && \n (init_state_r == INIT_WRLVL_LOAD_MR2))\n wrlvl_final_if_rst <= #TCQ 1'b1;\n\n // Constantly enable DQS while write leveling is enabled in the memory\n // This is more to get rid of warnings in simulation, can later change\n // this code to only enable WRLVL_ACTIVE when WRLVL_START is asserted\n\n always @(posedge clk)\n if (rst ||\n ((init_state_r1 != INIT_WRLVL_START) && \n (init_state_r == INIT_WRLVL_START)))\n wrlvl_odt_ctl <= #TCQ 1'b0;\n else if (wrlvl_rank_done && ~wrlvl_rank_done_r1)\n wrlvl_odt_ctl <= #TCQ 1'b1;\n\n generate\n if (nCK_PER_CLK == 4) begin: en_cnt_div4\n always @ (posedge clk)\n if (rst)\n enable_wrlvl_cnt <= #TCQ 5'd0;\n else if ((init_state_r == INIT_WRLVL_START) ||\n (wrlvl_odt && (enable_wrlvl_cnt == 5'd0)))\n enable_wrlvl_cnt <= #TCQ 5'd12;\n else if ((enable_wrlvl_cnt > 5'd0) && ~(phy_ctl_full || phy_cmd_full))\n enable_wrlvl_cnt <= #TCQ enable_wrlvl_cnt - 1;\n \n // ODT stays asserted as long as write_calib\n // signal is asserted \n always @(posedge clk)\n if (rst || wrlvl_odt_ctl)\n wrlvl_odt <= #TCQ 1'b0;\n else if (enable_wrlvl_cnt == 5'd1)\n wrlvl_odt <= #TCQ 1'b1;\n \n end else begin: en_cnt_div2 \n always @ (posedge clk)\n if (rst)\n enable_wrlvl_cnt <= #TCQ 5'd0;\n else if ((init_state_r == INIT_WRLVL_START) ||\n (wrlvl_odt && (enable_wrlvl_cnt == 5'd0)))\n enable_wrlvl_cnt <= #TCQ 5'd21;\n else if ((enable_wrlvl_cnt > 5'd0) && ~(phy_ctl_full || phy_cmd_full))\n enable_wrlvl_cnt <= #TCQ enable_wrlvl_cnt - 1;\n \n // ODT stays asserted as long as write_calib\n // signal is asserted \n always @(posedge clk)\n if (rst || wrlvl_odt_ctl)\n wrlvl_odt <= #TCQ 1'b0;\n else if (enable_wrlvl_cnt == 5'd1)\n wrlvl_odt <= #TCQ 1'b1;\n \n end\n endgenerate\n \n always @(posedge clk)\n if (rst || wrlvl_rank_done || done_dqs_tap_inc)\n wrlvl_active <= #TCQ 1'b0;\n else if ((enable_wrlvl_cnt == 5'd1) && wrlvl_odt && !wrlvl_active)\n wrlvl_active <= #TCQ 1'b1;\n\n// signal used to assert DQS for write leveling.\n// the DQS will be asserted once every 16 clock cycles.\n always @(posedge clk)begin\n if(rst || (enable_wrlvl_cnt != 5'd1)) begin\n wr_level_dqs_asrt <= #TCQ 1'd0;\n end else if ((enable_wrlvl_cnt == 5'd1) && (wrlvl_active_r1)) begin\n wr_level_dqs_asrt <= #TCQ 1'd1;\n end\n end\n\n always @ (posedge clk) begin\n if (rst || (wrlvl_done_r && ~wrlvl_done_r1))\n dqs_asrt_cnt <= #TCQ 2'd0;\n else if (wr_level_dqs_asrt && dqs_asrt_cnt != 2'd3)\n dqs_asrt_cnt <= #TCQ (dqs_asrt_cnt + 1);\n end\n\n always @ (posedge clk) begin\n if (rst || ~wrlvl_active)\n wr_lvl_start <= #TCQ 1'd0;\n else if (dqs_asrt_cnt == 2'd3)\n wr_lvl_start <= #TCQ 1'd1;\n end\n\n \n always @(posedge clk) begin\n if (rst)\n wl_sm_start <= #TCQ 1'b0;\n else\n wl_sm_start <= #TCQ wr_level_dqs_asrt_r1;\n end\n\n\n always @(posedge clk) begin\n wrlvl_active_r1 <= #TCQ wrlvl_active;\n wr_level_dqs_asrt_r1 <= #TCQ wr_level_dqs_asrt;\n wrlvl_done_r <= #TCQ wrlvl_done;\n wrlvl_done_r1 <= #TCQ wrlvl_done_r;\n wrlvl_rank_done_r1 <= #TCQ wrlvl_rank_done;\n wrlvl_rank_done_r2 <= #TCQ wrlvl_rank_done_r1;\n wrlvl_rank_done_r3 <= #TCQ wrlvl_rank_done_r2;\n wrlvl_rank_done_r4 <= #TCQ wrlvl_rank_done_r3;\n wrlvl_rank_done_r5 <= #TCQ wrlvl_rank_done_r4;\n wrlvl_rank_done_r6 <= #TCQ wrlvl_rank_done_r5;\n wrlvl_rank_done_r7 <= #TCQ wrlvl_rank_done_r6;\n end\n \n always @ (posedge clk) begin\n //if (rst)\n wrlvl_rank_cntr <= #TCQ 3'd0;\n //else if (wrlvl_rank_done)\n // wrlvl_rank_cntr <= #TCQ wrlvl_rank_cntr + 1'b1;\n end \n \n //*****************************************************************\n // Precharge request logic - those calibration logic blocks\n // that require greater than tRAS(max) to finish must break up\n // their calibration into smaller units of time, with precharges\n // issued in between. This is done using the XXX_PRECH_REQ and\n // PRECH_DONE handshaking between PHY_INIT and those blocks\n //*****************************************************************\n\n // Shared request from multiple sources\n assign prech_req = oclk_prech_req | rdlvl_prech_req | wrcal_prech_req | prbs_rdlvl_prech_req | \n (dqs_found_prech_req & (init_state_r == INIT_RDLVL_STG2_READ_WAIT));\n \n // Handshaking logic to force precharge during read leveling, and to\n // notify read leveling logic when precharge has been initiated and\n // it's okay to proceed with leveling again\n always @(posedge clk)\n if (rst) begin\n prech_req_r <= #TCQ 1'b0;\n prech_req_posedge_r <= #TCQ 1'b0;\n prech_pending_r <= #TCQ 1'b0;\n end else begin\n prech_req_r <= #TCQ prech_req;\n prech_req_posedge_r <= #TCQ prech_req & ~prech_req_r;\n if (prech_req_posedge_r)\n prech_pending_r <= #TCQ 1'b1;\n // Clear after we've finished with the precharge and have\n // returned to issuing read leveling calibration reads\n else if (prech_done_pre)\n prech_pending_r <= #TCQ 1'b0;\n end\n\t\n always @(posedge clk) begin\n if (rst || prech_done_r3)\n mask_lim_done <= #TCQ 1'b0;\n else if (prech_pending_r)\n mask_lim_done <= #TCQ 1'b1;\n end\n \n always @(posedge clk) begin\n if (rst || prbs_rdlvl_done_r3)\n complex_mask_lim_done <= #TCQ 1'b0;\n else if (~prbs_rdlvl_done && complex_oclkdelay_calib_start_int)\n complex_mask_lim_done <= #TCQ 1'b1;\n end\n\n //Complex oclkdelay calibrration\n\n //***************************************************************************\n // Various timing counters\n //***************************************************************************\n \n //*****************************************************************\n // Generic delay for various states that require it (e.g. for turnaround\n // between read and write). Make this a sufficiently large number of clock\n // cycles to cover all possible frequencies and memory components)\n // Requirements for this counter:\n // 1. Greater than tMRD\n // 2. tRFC (refresh-active) for DDR2\n // 3. (list the other requirements, slacker...)\n //*****************************************************************\n\n always @(posedge clk) begin\n case (init_state_r)\n INIT_LOAD_MR_WAIT,\n INIT_WRLVL_LOAD_MR_WAIT,\n INIT_WRLVL_LOAD_MR2_WAIT,\n INIT_MPR_WAIT,\n INIT_MPR_DISABLE_PREWAIT,\n INIT_MPR_DISABLE_WAIT,\n INIT_OCLKDELAY_ACT_WAIT,\n INIT_OCLKDELAY_WRITE_WAIT,\n INIT_RDLVL_ACT_WAIT,\n INIT_RDLVL_STG1_WRITE_READ,\n INIT_RDLVL_STG2_READ_WAIT,\n INIT_WRCAL_ACT_WAIT,\n INIT_WRCAL_WRITE_READ,\n INIT_WRCAL_READ_WAIT,\n INIT_PRECHARGE_PREWAIT,\n INIT_PRECHARGE_WAIT,\n INIT_DDR2_PRECHARGE_WAIT,\n INIT_REG_WRITE_WAIT,\n INIT_REFRESH_WAIT,\n INIT_REFRESH_RNK2_WAIT: begin\n if (phy_ctl_full || phy_cmd_full)\n cnt_cmd_r <= #TCQ cnt_cmd_r;\n else\n cnt_cmd_r <= #TCQ cnt_cmd_r + 1;\n end\n INIT_WRLVL_WAIT:\n cnt_cmd_r <= #TCQ 'b0;\n default:\n cnt_cmd_r <= #TCQ 'b0;\n endcase\n end\n\n // pulse when count reaches terminal count\n always @(posedge clk)\n cnt_cmd_done_r <= #TCQ (cnt_cmd_r == CNTNEXT_CMD);\n \n // For ODT deassertion - hold throughout post read/write wait stage, but\n // deassert before next command. The post read/write stage is very long, so\n // we simply address the longest case here plus some margin.\n always @(posedge clk)\n cnt_cmd_done_m7_r <= #TCQ (cnt_cmd_r == (CNTNEXT_CMD - 7));\n\n//************************************************************************\n// Added to support PO fine delay inc when TG errors\n always @(posedge clk) begin\n case (init_state_r)\n INIT_WRCAL_READ_WAIT: begin\n if (phy_ctl_full || phy_cmd_full)\n cnt_wait <= #TCQ cnt_wait;\n else\n cnt_wait <= #TCQ cnt_wait + 1;\n end\n default:\n cnt_wait <= #TCQ 'b0;\n endcase\n end\n \n always @(posedge clk)\n cnt_wrcal_rd <= #TCQ (cnt_wait == 'd4);\n \n always @(posedge clk) begin\n if (rst || ~temp_wrcal_done)\n temp_lmr_done <= #TCQ 1'b0;\n else if (temp_wrcal_done && (init_state_r == INIT_LOAD_MR))\n temp_lmr_done <= #TCQ 1'b1;\n end\n \n always @(posedge clk)\n temp_wrcal_done_r <= #TCQ temp_wrcal_done;\n \n always @(posedge clk)\n if (rst) begin\n tg_timer_go <= #TCQ 1'b0;\n end else if ((PRE_REV3ES == \"ON\") && temp_wrcal_done && temp_lmr_done &&\n (init_state_r == INIT_WRCAL_READ_WAIT)) begin\n tg_timer_go <= #TCQ 1'b1;\n end else begin\n tg_timer_go <= #TCQ 1'b0;\n end\n\n always @(posedge clk) begin\n if (rst || (temp_wrcal_done && ~temp_wrcal_done_r) ||\n (init_state_r == INIT_PRECHARGE_PREWAIT))\n tg_timer <= #TCQ 'd0;\n else if ((pi_phaselock_timer == PHASELOCKED_TIMEOUT) &&\n tg_timer_go &&\n (tg_timer != TG_TIMER_TIMEOUT))\n tg_timer <= #TCQ tg_timer + 1;\n end\n \n always @(posedge clk) begin\n if (rst)\n tg_timer_done <= #TCQ 1'b0;\n else if (tg_timer == TG_TIMER_TIMEOUT)\n tg_timer_done <= #TCQ 1'b1;\n else\n tg_timer_done <= #TCQ 1'b0;\n end\n \n always @(posedge clk) begin\n if (rst)\n no_rst_tg_mc <= #TCQ 1'b0;\n else if ((init_state_r == INIT_WRCAL_ACT) && wrcal_read_req)\n no_rst_tg_mc <= #TCQ 1'b1;\n else\n no_rst_tg_mc <= #TCQ 1'b0;\n end\n \n//************************************************************************\n \n always @(posedge clk) begin\n if (rst)\n detect_pi_found_dqs <= #TCQ 1'b0;\n else if ((cnt_cmd_r == 7'b0111111) &&\n (init_state_r == INIT_RDLVL_STG2_READ_WAIT))\n detect_pi_found_dqs <= #TCQ 1'b1;\n else\n detect_pi_found_dqs <= #TCQ 1'b0;\n end \n\n //*****************************************************************\n // Initial delay after power-on for RESET, CKE\n // NOTE: Could reduce power consumption by turning off these counters\n // after initial power-up (at expense of more logic)\n // NOTE: Likely can combine multiple counters into single counter\n //*****************************************************************\n\n // Create divided by 1024 version of clock \n always @(posedge clk)\n if (rst) begin\n cnt_pwron_ce_r <= #TCQ 10'h000;\n pwron_ce_r <= #TCQ 1'b0;\n end else begin\n cnt_pwron_ce_r <= #TCQ cnt_pwron_ce_r + 1;\n pwron_ce_r <= #TCQ (cnt_pwron_ce_r == 10'h3FF);\n end\n \n // \"Main\" power-on counter - ticks every CLKDIV/1024 cycles\n always @(posedge clk) \n if (rst)\n cnt_pwron_r <= #TCQ 'b0;\n else if (pwron_ce_r)\n cnt_pwron_r <= #TCQ cnt_pwron_r + 1;\n\n always @(posedge clk)\n if (rst || ~phy_ctl_ready) begin\n cnt_pwron_reset_done_r <= #TCQ 1'b0;\n cnt_pwron_cke_done_r <= #TCQ 1'b0;\n end else begin\n // skip power-up count for simulation purposes only\n if ((SIM_INIT_OPTION == \"SKIP_PU_DLY\") || \n (SIM_INIT_OPTION == \"SKIP_INIT\")) begin\n cnt_pwron_reset_done_r <= #TCQ 1'b1;\n cnt_pwron_cke_done_r <= #TCQ 1'b1;\n end else begin\n // otherwise, create latched version of done signal for RESET, CKE\n if (DRAM_TYPE == \"DDR3\") begin\n if (!cnt_pwron_reset_done_r)\n cnt_pwron_reset_done_r \n <= #TCQ (cnt_pwron_r == PWRON_RESET_DELAY_CNT);\n if (!cnt_pwron_cke_done_r)\n cnt_pwron_cke_done_r \n <= #TCQ (cnt_pwron_r == PWRON_CKE_DELAY_CNT);\n end else begin // DDR2\n cnt_pwron_reset_done_r <= #TCQ 1'b1; // not needed \n if (!cnt_pwron_cke_done_r)\n cnt_pwron_cke_done_r \n <= #TCQ (cnt_pwron_r == PWRON_CKE_DELAY_CNT);\n end \n end\n end // else: !if(rst || ~phy_ctl_ready)\n\n\n always @(posedge clk)\n cnt_pwron_cke_done_r1 <= #TCQ cnt_pwron_cke_done_r;\n\n // Keep RESET asserted and CKE deasserted until after power-on delay\n always @(posedge clk or posedge rst) begin\n if (rst)\n phy_reset_n <= #TCQ 1'b0;\n else\n phy_reset_n <= #TCQ cnt_pwron_reset_done_r;\n// phy_cke <= #TCQ {CKE_WIDTH{cnt_pwron_cke_done_r}};\n end\n\n //*****************************************************************\n // Counter for tXPR (pronouned \"Tax-Payer\") - wait time after \n // CKE deassertion before first MRS command can be asserted\n //*****************************************************************\n\n always @(posedge clk)\n if (!cnt_pwron_cke_done_r) begin\n cnt_txpr_r <= #TCQ 'b0;\n cnt_txpr_done_r <= #TCQ 1'b0;\n end else begin\n cnt_txpr_r <= #TCQ cnt_txpr_r + 1;\n if (!cnt_txpr_done_r)\n cnt_txpr_done_r <= #TCQ (cnt_txpr_r == TXPR_DELAY_CNT);\n end\n\n //*****************************************************************\n // Counter for the initial 400ns wait for issuing precharge all\n // command after CKE assertion. Only for DDR2. \n //*****************************************************************\n\n always @(posedge clk)\n if (!cnt_pwron_cke_done_r) begin\n cnt_init_pre_wait_r <= #TCQ 'b0;\n cnt_init_pre_wait_done_r <= #TCQ 1'b0;\n end else begin\n cnt_init_pre_wait_r <= #TCQ cnt_init_pre_wait_r + 1;\n if (!cnt_init_pre_wait_done_r)\n cnt_init_pre_wait_done_r \n <= #TCQ (cnt_init_pre_wait_r >= DDR2_INIT_PRE_CNT);\n end\n \n //*****************************************************************\n // Wait for both DLL to lock (tDLLK) and ZQ calibration to finish\n // (tZQINIT). Both take the same amount of time (512*tCK)\n //*****************************************************************\n\n always @(posedge clk)\n if (init_state_r == INIT_ZQCL) begin\n cnt_dllk_zqinit_r <= #TCQ 'b0;\n cnt_dllk_zqinit_done_r <= #TCQ 1'b0;\n end else if (~(phy_ctl_full || phy_cmd_full)) begin\n cnt_dllk_zqinit_r <= #TCQ cnt_dllk_zqinit_r + 1;\n if (!cnt_dllk_zqinit_done_r) \n cnt_dllk_zqinit_done_r \n <= #TCQ (cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT);\n end\n\n //***************************************************************** \n // Keep track of which MRS counter needs to be programmed during\n // memory initialization\n // The counter and the done signal are reset an additional time\n // for DDR2. The same signals are used for the additional DDR2\n // initialization sequence. \n //*****************************************************************\n \n always @(posedge clk)\n if ((init_state_r == INIT_IDLE)||\n ((init_state_r == INIT_REFRESH)\n && (~mem_init_done_r))) begin\n cnt_init_mr_r <= #TCQ 'b0;\n cnt_init_mr_done_r <= #TCQ 1'b0;\n end else if (init_state_r == INIT_LOAD_MR) begin\n cnt_init_mr_r <= #TCQ cnt_init_mr_r + 1;\n cnt_init_mr_done_r <= #TCQ (cnt_init_mr_r == INIT_CNT_MR_DONE);\n end\n\n \n //***************************************************************** \n // Flag to tell if the first precharge for DDR2 init sequence is\n // done \n //*****************************************************************\n \n always @(posedge clk)\n if (init_state_r == INIT_IDLE) \n ddr2_pre_flag_r<= #TCQ 'b0;\n else if (init_state_r == INIT_LOAD_MR) \n ddr2_pre_flag_r<= #TCQ 1'b1;\n // reset the flag for multi rank case \n else if ((ddr2_refresh_flag_r) &&\n (init_state_r == INIT_LOAD_MR_WAIT)&&\n (cnt_cmd_done_r) && (cnt_init_mr_done_r))\n ddr2_pre_flag_r <= #TCQ 'b0;\n\n //***************************************************************** \n // Flag to tell if the refresh stat for DDR2 init sequence is\n // reached \n //*****************************************************************\n \n always @(posedge clk)\n if (init_state_r == INIT_IDLE) \n ddr2_refresh_flag_r<= #TCQ 'b0;\n else if ((init_state_r == INIT_REFRESH) && (~mem_init_done_r)) \n // reset the flag for multi rank case \n ddr2_refresh_flag_r<= #TCQ 1'b1;\n else if ((ddr2_refresh_flag_r) &&\n (init_state_r == INIT_LOAD_MR_WAIT)&&\n (cnt_cmd_done_r) && (cnt_init_mr_done_r))\n ddr2_refresh_flag_r <= #TCQ 'b0;\n \n //***************************************************************** \n // Keep track of the number of auto refreshes for DDR2 \n // initialization. The spec asks for a minimum of two refreshes.\n // Four refreshes are performed here. The two extra refreshes is to\n // account for the 200 clock cycle wait between step h and l.\n // Without the two extra refreshes we would have to have a\n // wait state. \n //*****************************************************************\n \n always @(posedge clk)\n if (init_state_r == INIT_IDLE) begin\n cnt_init_af_r <= #TCQ 'b0;\n cnt_init_af_done_r <= #TCQ 1'b0;\n end else if ((init_state_r == INIT_REFRESH) && (~mem_init_done_r))begin\n cnt_init_af_r <= #TCQ cnt_init_af_r + 1;\n cnt_init_af_done_r <= #TCQ (cnt_init_af_r == 2'b11);\n end \n\n //***************************************************************** \n // Keep track of the register control word programming for\n // DDR3 RDIMM \n //*****************************************************************\n \n always @(posedge clk)\n if (init_state_r == INIT_IDLE)\n reg_ctrl_cnt_r <= #TCQ 'b0;\n else if (init_state_r == INIT_REG_WRITE)\n reg_ctrl_cnt_r <= #TCQ reg_ctrl_cnt_r + 1;\n\n generate\n if (RANKS < 2) begin: one_rank\n always @(posedge clk)\n if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done || \n (complex_byte_rd_done) || prbs_rdlvl_done_pulse )\n stg1_wr_done <= #TCQ 1'b0;\n else if (init_state_r == INIT_RDLVL_STG1_WRITE_READ)\n stg1_wr_done <= #TCQ 1'b1;\n end else begin: two_ranks\n always @(posedge clk)\n if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done || \n (complex_byte_rd_done) || prbs_rdlvl_done_pulse ||\n (rdlvl_stg1_rank_done ))\n stg1_wr_done <= #TCQ 1'b0;\n else if (init_state_r == INIT_RDLVL_STG1_WRITE_READ)\n stg1_wr_done <= #TCQ 1'b1;\n end\n endgenerate\n \n always @(posedge clk)\n if (rst)\n rnk_ref_cnt <= #TCQ 1'b0;\n else if (stg1_wr_done && \n (init_state_r == INIT_REFRESH_WAIT) && cnt_cmd_done_r)\n rnk_ref_cnt <= #TCQ ~rnk_ref_cnt;\n \n\n always @(posedge clk)\n if (rst || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_OCAL_CENTER_ACT) ||\n (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_RDLVL_ACT) || \n (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r ==INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT))\n num_refresh <= #TCQ 'd0;\n else if ((init_state_r == INIT_REFRESH) &&\n (~pi_dqs_found_done || ((DRAM_TYPE == \"DDR3\") && ~oclkdelay_calib_done) ||\n (rdlvl_stg1_done && ~prbs_rdlvl_done) ||\n (prbs_rdlvl_done && ~complex_oclkdelay_calib_done) ||\n ((CLK_PERIOD/nCK_PER_CLK <= 2500) && wrcal_done && ~rdlvl_stg1_done) ||\n ((CLK_PERIOD/nCK_PER_CLK > 2500) && wrlvl_done_r1 && ~rdlvl_stg1_done)))\n num_refresh <= #TCQ num_refresh + 1;\n \n \n //***************************************************************************\n // Initialization state machine\n //***************************************************************************\n\n //*****************************************************************\n // Next-state logic \n //*****************************************************************\n\n always @(posedge clk)\n if (rst)begin\n init_state_r <= #TCQ INIT_IDLE;\n init_state_r1 <= #TCQ INIT_IDLE;\n end else begin\n init_state_r <= #TCQ init_next_state;\n init_state_r1 <= #TCQ init_state_r;\n end \n \n always @(*) begin \n init_next_state = init_state_r;\n (* full_case, parallel_case *) case (init_state_r)\n\n //*******************************************************\n // DRAM initialization\n //*******************************************************\n\n // Initial state - wait for:\n // 1. Power-on delays to pass\n // 2. PHY Control Block to assert phy_ctl_ready\n // 3. PHY Control FIFO must not be FULL\n // 4. Read path initialization to finish\n INIT_IDLE:\n if (cnt_pwron_cke_done_r && phy_ctl_ready && ck_addr_cmd_delay_done && delay_incdec_done\n && ~(phy_ctl_full || phy_cmd_full) ) begin \n // If skipping memory initialization (simulation only)\n if (SIM_INIT_OPTION == \"SKIP_INIT\") \n //if (WRLVL == \"ON\") \n // Proceed to write leveling \n // init_next_state = INIT_WRLVL_START;\n //else //if (SIM_CAL_OPTION != \"SKIP_CAL\") \n // Proceed to Phaser_In phase lock \n init_next_state = INIT_RDLVL_ACT;\n // else\n // Skip read leveling\n //init_next_state = INIT_DONE; \n else\n init_next_state = INIT_WAIT_CKE_EXIT;\n end\n \n // Wait minimum of Reset CKE exit time (tXPR = max(tXS, \n INIT_WAIT_CKE_EXIT:\n if ((cnt_txpr_done_r) && (DRAM_TYPE == \"DDR3\") \n && ~(phy_ctl_full || phy_cmd_full)) begin\n if((REG_CTRL == \"ON\") && ((nCS_PER_RANK > 1) ||\n (RANKS > 1)))\n //register write for reg dimm. Some register chips\n // have the register chip in a pre-programmed state\n // in that case the nCS_PER_RANK == 1 && RANKS == 1 \n init_next_state = INIT_REG_WRITE;\n else\n // Load mode register - this state is repeated multiple times\n init_next_state = INIT_LOAD_MR;\n end else if ((cnt_init_pre_wait_done_r) && (DRAM_TYPE == \"DDR2\")\n && ~(phy_ctl_full || phy_cmd_full))\n // DDR2 start with a precharge all command \n init_next_state = INIT_DDR2_PRECHARGE; \n\n INIT_REG_WRITE:\n init_next_state = INIT_REG_WRITE_WAIT;\n\n INIT_REG_WRITE_WAIT:\n if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin\n if(reg_ctrl_cnt_r == 4'd8)\n init_next_state = INIT_LOAD_MR;\n else\n init_next_state = INIT_REG_WRITE;\n end\n \n INIT_LOAD_MR:\n init_next_state = INIT_LOAD_MR_WAIT;\n // After loading MR, wait at least tMRD\n \n INIT_LOAD_MR_WAIT:\n if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin\n // If finished loading all mode registers, proceed to next step\n if (prbs_rdlvl_done && pi_dqs_found_done && rdlvl_stg1_done)\n // for ddr3 when the correct burst length is writtern at end\n init_next_state = INIT_PRECHARGE;\n else if (~wrcal_done && temp_lmr_done)\n init_next_state = INIT_PRECHARGE_PREWAIT;\n else if (cnt_init_mr_done_r)begin\n if(DRAM_TYPE == \"DDR3\")\n init_next_state = INIT_ZQCL;\n else begin //DDR2\n if(ddr2_refresh_flag_r)begin\n // memory initialization per rank for multi-rank case\n if (!mem_init_done_r && (chip_cnt_r <= RANKS-1))\n init_next_state = INIT_DDR2_MULTI_RANK; \n else \n init_next_state = INIT_RDLVL_ACT;\n // ddr2 initialization done.load mode state after refresh\n end else \n init_next_state = INIT_DDR2_PRECHARGE;\n end \n end else \n init_next_state = INIT_LOAD_MR;\n end\n\n // DDR2 multi rank transition state\n INIT_DDR2_MULTI_RANK:\n init_next_state = INIT_DDR2_MULTI_RANK_WAIT;\n\n INIT_DDR2_MULTI_RANK_WAIT:\n init_next_state = INIT_DDR2_PRECHARGE;\n \n // Initial ZQ calibration \n INIT_ZQCL:\n init_next_state = INIT_WAIT_DLLK_ZQINIT;\n\n // Wait until both DLL have locked, and ZQ calibration done\n INIT_WAIT_DLLK_ZQINIT:\n if (cnt_dllk_zqinit_done_r && ~(phy_ctl_full || phy_cmd_full))\n // memory initialization per rank for multi-rank case\n if (!mem_init_done_r && (chip_cnt_r <= RANKS-1))\n init_next_state = INIT_LOAD_MR;\n //else if (WRLVL == \"ON\")\n // init_next_state = INIT_WRLVL_START;\n else\n // skip write-leveling (e.g. for DDR2 interface)\n init_next_state = INIT_RDLVL_ACT;\n\n // Initial precharge for DDR2\n INIT_DDR2_PRECHARGE: \n init_next_state = INIT_DDR2_PRECHARGE_WAIT; \n\n INIT_DDR2_PRECHARGE_WAIT: \n if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin\n if (ddr2_pre_flag_r)\n init_next_state = INIT_REFRESH;\n else // from precharge state initially go to load mode \n init_next_state = INIT_LOAD_MR;\n end \n\n INIT_REFRESH:\n if ((SKIP_CALIB == \"TRUE\") && ~calib_tap_inc_done && pi_dqs_found_done)\n\t\t init_next_state = INIT_SKIP_CALIB_WAIT;\n\t\telse if ((RANKS == 2) && (chip_cnt_r == RANKS - 1))\n init_next_state = INIT_REFRESH_RNK2_WAIT;\n else\n init_next_state = INIT_REFRESH_WAIT; \n\n INIT_REFRESH_RNK2_WAIT:\n if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))\n init_next_state = INIT_PRECHARGE;\n \n INIT_REFRESH_WAIT: \n if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))begin\n if(cnt_init_af_done_r && (~mem_init_done_r))\n // go to lm state as part of DDR2 init sequence \n init_next_state = INIT_LOAD_MR;\n // Go to state to issue back-to-back writes during limit check and centering\n else if (~oclkdelay_calib_done && (mpr_last_byte_done || mpr_rdlvl_done) && (DRAM_TYPE == \"DDR3\")) begin\n if (num_refresh == 'd8)\n init_next_state = INIT_OCAL_CENTER_ACT;\n else\n init_next_state = INIT_REFRESH;\n end else if(rdlvl_stg1_done && oclkdelay_center_calib_done &&\n\t complex_oclkdelay_calib_done && ~wrlvl_done_r1 && (WRLVL == \"ON\")) \n init_next_state = INIT_WRLVL_START;\n else if (pi_dqs_found_done && ~wrlvl_done_r1 && ~wrlvl_final && ~wrlvl_byte_redo && (WRLVL == \"ON\"))\n init_next_state = INIT_WRLVL_START;\n else if ((((prbs_last_byte_done_r || prbs_rdlvl_done) && ~complex_oclkdelay_calib_done\n && pi_dqs_found_done) && (WRLVL == \"ON\")) //&& rdlvl_stg1_done // changed for new algo 3/26\n && mem_init_done_r) begin\n if (num_refresh == 'd8) begin\n\t\t\t if (BYPASS_COMPLEX_OCAL == \"FALSE\")\n init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT;\n\t\t\t else\n\t\t\t init_next_state = INIT_WRCAL_ACT;\n end else \n init_next_state = INIT_REFRESH;\n end else if (~pi_dqs_found_done ||\n (rdlvl_stg1_done && ~prbs_rdlvl_done && ~complex_oclkdelay_calib_done) ||\n ((CLK_PERIOD/nCK_PER_CLK <= 2500) && wrcal_done && ~rdlvl_stg1_done) ||\n ((CLK_PERIOD/nCK_PER_CLK > 2500) && wrlvl_done_r1 && ~rdlvl_stg1_done)) begin\n if (num_refresh == 'd8)\n init_next_state = INIT_RDLVL_ACT;\n else\n init_next_state = INIT_REFRESH;\n end else if ((~wrcal_done && wrlvl_byte_redo)&& (DRAM_TYPE == \"DDR3\")\n && (CLK_PERIOD/nCK_PER_CLK > 2500))\n init_next_state = INIT_WRLVL_LOAD_MR2;\n else if (((prbs_rdlvl_done && rdlvl_stg1_done && complex_oclkdelay_calib_done && pi_dqs_found_done) && (WRLVL == \"ON\"))\n && mem_init_done_r && (CLK_PERIOD/nCK_PER_CLK > 2500))\n init_next_state = INIT_WRCAL_ACT;\n else if (pi_dqs_found_done && (DRAM_TYPE == \"DDR3\") && ~(mpr_last_byte_done || mpr_rdlvl_done)) begin\n if (num_refresh == 'd8)\n init_next_state = INIT_MPR_RDEN;\n else\n init_next_state = INIT_REFRESH;\n end else if (((oclkdelay_calib_done && wrlvl_final && ~wrlvl_done_r1) || // changed for new algo 3/25\n (~wrcal_done && wrlvl_byte_redo)) && (DRAM_TYPE == \"DDR3\"))\n init_next_state = INIT_WRLVL_LOAD_MR2;\n else if ((~wrcal_done && (WRLVL == \"ON\") && (CLK_PERIOD/nCK_PER_CLK <= 2500)) \n && pi_dqs_found_done)\n init_next_state = INIT_WRCAL_ACT;\n else if (mem_init_done_r) begin\n if (RANKS < 2)\n init_next_state = INIT_RDLVL_ACT;\n else if (stg1_wr_done && ~rnk_ref_cnt && ~rdlvl_stg1_done)\n init_next_state = INIT_PRECHARGE;\n else\n init_next_state = INIT_RDLVL_ACT;\n end else // to DDR2 init state as part of DDR2 init sequence \n init_next_state = INIT_REFRESH;\n end\n \n\t INIT_SKIP_CALIB_WAIT:\n\t if (calib_tap_inc_done)\n\t\t init_next_state = INIT_WRCAL_ACT;\n\t\t \n \n //******************************************************\n // Write Leveling\n //*******************************************************\n\n // Enable write leveling in MR1 and start write leveling\n // for current rank\n INIT_WRLVL_START:\n init_next_state = INIT_WRLVL_WAIT;\n\n // Wait for both MR load and write leveling to complete\n // (write leveling should take much longer than MR load..)\n INIT_WRLVL_WAIT:\n if (wrlvl_rank_done_r7 && ~(phy_ctl_full || phy_cmd_full))\n init_next_state = INIT_WRLVL_LOAD_MR;\n\n // Disable write leveling in MR1 for current rank\n INIT_WRLVL_LOAD_MR:\n init_next_state = INIT_WRLVL_LOAD_MR_WAIT;\n \n INIT_WRLVL_LOAD_MR_WAIT:\n if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))\n init_next_state = INIT_WRLVL_LOAD_MR2;\n \n // Load MR2 to set ODT: Dynamic ODT for single rank case\n // And ODTs for multi-rank case as well\n INIT_WRLVL_LOAD_MR2:\n init_next_state = INIT_WRLVL_LOAD_MR2_WAIT; \n\n // Wait tMRD before proceeding\n INIT_WRLVL_LOAD_MR2_WAIT:\n if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin \n //if (wrlvl_byte_done)\n // init_next_state = INIT_PRECHARGE_PREWAIT;\n // else if ((RANKS == 2) && wrlvl_rank_done_r2)\n // init_next_state = INIT_WRLVL_LOAD_MR2_WAIT;\n if (~wrlvl_done_r1)\n init_next_state = INIT_WRLVL_START;\n else if (SIM_CAL_OPTION == \"SKIP_CAL\")\n // If skip rdlvl, then we're done\n init_next_state = INIT_DONE;\n else \n // Otherwise, proceed to read leveling \n //init_next_state = INIT_RDLVL_ACT;\n init_next_state = INIT_PRECHARGE_PREWAIT;\n end\n \n //*******************************************************\n // Read Leveling\n //******************************************************* \n\n // single row activate. All subsequent read leveling writes and \n // read will take place in this row \n INIT_RDLVL_ACT:\n init_next_state = INIT_RDLVL_ACT_WAIT;\n\n // hang out for awhile before issuing subsequent column commands\n // it's also possible to reach this state at various points\n // during read leveling - determine what the current stage is \n INIT_RDLVL_ACT_WAIT:\n if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin\n // Just finished an activate. Now either write, read, or precharge \n // depending on where we are in the training sequence\n if (!pi_calib_done_r1)\n init_next_state = INIT_PI_PHASELOCK_READS;\n else if (!pi_dqs_found_done)\n // (!pi_dqs_found_start || pi_dqs_found_rank_done))\n init_next_state = INIT_RDLVL_STG2_READ;\n else if (~wrcal_done && (WRLVL == \"ON\") && (CLK_PERIOD/nCK_PER_CLK <= 2500))\n init_next_state = INIT_WRCAL_ACT_WAIT;\n else if ((!rdlvl_stg1_done && ~stg1_wr_done && ~rdlvl_last_byte_done) ||\n (!prbs_rdlvl_done && ~stg1_wr_done && ~prbs_last_byte_done)) begin\n // Added to avoid rdlvl_stg1 write data pattern at the start of PRBS rdlvl\n if (!prbs_rdlvl_done && ~stg1_wr_done && rdlvl_last_byte_done)\n init_next_state = INIT_RDLVL_ACT_WAIT;\n else\n init_next_state = INIT_RDLVL_STG1_WRITE;\n end else if ((!rdlvl_stg1_done && rdlvl_stg1_start_int) || !prbs_rdlvl_done) begin\n if (rdlvl_last_byte_done || prbs_last_byte_done)\n // Added to avoid extra reads at the end of read leveling\n init_next_state = INIT_RDLVL_ACT_WAIT;\n else begin\n // Case 2: If in stage 1, and just precharged after training\n // previous byte, then continue reading\n if (rdlvl_stg1_done)\n init_next_state = INIT_RDLVL_STG1_WRITE_READ;\n else\n init_next_state = INIT_RDLVL_STG1_READ;\n end\n end else if ((prbs_rdlvl_done && rdlvl_stg1_done && (RANKS == 1)) && (WRLVL == \"ON\") &&\n (CLK_PERIOD/nCK_PER_CLK > 2500))\n init_next_state = INIT_WRCAL_ACT_WAIT;\n else\n // Otherwise, if we're finished with calibration, then precharge\n // the row - silly, because we just opened it - possible to take\n // this out by adding logic to avoid the ACT in first place. Make\n // sure that cnt_cmd_done will handle tRAS(min)\n init_next_state = INIT_PRECHARGE_PREWAIT;\n end\n\n //**************************************************\n // Back-to-back reads for Phaser_IN Phase locking\n // DQS to FREQ_REF clock\n //**************************************************\n \n INIT_PI_PHASELOCK_READS:\n if (pi_phase_locked_all_r3 && ~pi_phase_locked_all_r4)\n init_next_state = INIT_PRECHARGE_PREWAIT;\n \n //********************************************* \n // Stage 1 read-leveling (write and continuous read)\n //********************************************* \n\n // Write training pattern for stage 1\n // PRBS pattern of TBD length\n INIT_RDLVL_STG1_WRITE:\n // 4:1 DDR3 BL8 will require all 8 words in 1 DIV4 clock cycle\n // 2:1 DDR2/DDR3 BL8 will require 2 DIV2 clock cycles for 8 words\n // 2:1 DDR2 BL4 will require 1 DIV2 clock cycle for 4 words\n // An entire row worth of writes issued before proceeding to reads\n // The number of write is (2^column width)/burst length to accomodate\n // PRBS pattern for window detection.\n //VCCO/VCCAUX write is not done\n if ((complex_num_writes_dec == 1) && ~complex_row0_wr_done && prbs_rdlvl_done && rdlvl_stg1_done_r1)\n init_next_state = INIT_OCAL_COMPLEX_WRITE_WAIT;\n //back to back write from row1\n else if (stg1_wr_rd_cnt == 9'd1) begin\n if (rdlvl_stg1_done_r1)\n init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT;\n else\n init_next_state = INIT_RDLVL_STG1_WRITE_READ;\n end\n\n INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT:\n if (complex_rdlvl_int_ref_req || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) \n init_next_state = INIT_PRECHARGE_PREWAIT;\n else if (complex_wait_cnt == 'd15)\n //At the end of the byte, it goes to REFRESH\n init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE;\n \n INIT_RDLVL_COMPLEX_PRECHARGE:\n init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_WAIT;\n \n INIT_RDLVL_COMPLEX_PRECHARGE_WAIT:\n if (complex_rdlvl_int_ref_req || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1))\n init_next_state = INIT_PRECHARGE_PREWAIT;\n else if (complex_wait_cnt == 'd15) begin\n if (prbs_rdlvl_done || prbs_last_byte_done_r) begin // changed for new algo 3/26\n\t\t // added condition to ensure that limit starts after rdlvl_stg1_done is asserted in the bypass complex rdlvl mode\n\t\t if ((~prbs_rdlvl_done && complex_oclkdelay_calib_start_int) || ~lim_done)\n init_next_state = INIT_OCAL_CENTER_ACT; //INIT_OCAL_COMPLEX_ACT; // changed for new algo 3/26\n\t\t\telse if (lim_done && complex_oclkdelay_calib_start_r2)\n\t\t\t init_next_state = INIT_RDLVL_COMPLEX_ACT;\n\t\t\telse\n\t\t\t init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_WAIT;\n end else\n\t\t init_next_state = INIT_RDLVL_COMPLEX_ACT;\n\t\tend\n \n \n INIT_RDLVL_COMPLEX_ACT:\n //only for sampling boundary it need to wait\n //when initial pi dec is not done in complex per-bit, it need to wait \n if(prbs_rdlvl_start && (num_samples_done_r || ~complex_init_pi_dec_done))\n init_next_state = INIT_RDLVL_COMPLEX_PI_WAIT;\n else init_next_state = INIT_RDLVL_COMPLEX_ACT_WAIT;\n\n //wait PI movement is done before proceeding read\n INIT_RDLVL_COMPLEX_PI_WAIT:\n if(complex_pi_incdec_done) \n init_next_state = INIT_RDLVL_COMPLEX_ACT_WAIT;\n \n INIT_RDLVL_COMPLEX_ACT_WAIT: \n if (complex_rdlvl_int_ref_req || prech_req_posedge_r) //prech req always happen in this state\n init_next_state = INIT_PRECHARGE_PREWAIT;\n else if (complex_wait_cnt == 'd15) begin\n if (oclkdelay_center_calib_start)\n init_next_state = INIT_OCAL_CENTER_WRITE_WAIT;\n else if (stg1_wr_done)\n init_next_state = INIT_RDLVL_COMPLEX_READ;\n else if (~complex_row1_wr_done)\n if (complex_oclkdelay_calib_start_int && complex_ocal_num_samples_done_r) //WAIT for resume signal for write\n init_next_state = INIT_OCAL_COMPLEX_RESUME_WAIT;\n else \n init_next_state = INIT_RDLVL_STG1_WRITE;\n else\n init_next_state = INIT_RDLVL_STG1_WRITE_READ;\n end\n \n // Write-read turnaround\n INIT_RDLVL_STG1_WRITE_READ: \n if (reset_rd_addr_r1)\n init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT;\n else if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))begin\n if (rdlvl_stg1_done_r1)\n //before going to read, wait for PI inc/dec done\n init_next_state = INIT_RDLVL_COMPLEX_PI_WAIT; \n else\n init_next_state = INIT_RDLVL_STG1_READ;\n end\n\n // Continuous read, where interruptible by precharge request from\n // calibration logic. Also precharges when stage 1 is complete\n // No precharges when reads provided to Phaser_IN for phase locking\n // FREQ_REF to read DQS since data integrity is not important.\n INIT_RDLVL_STG1_READ:\n if (rdlvl_stg1_rank_done || (rdlvl_stg1_done && ~rdlvl_stg1_done_r1) ||\n prech_req_posedge_r || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1))\n init_next_state = INIT_PRECHARGE_PREWAIT;\n\n INIT_RDLVL_COMPLEX_READ:\n if (prech_req_posedge_r || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1))\n init_next_state = INIT_PRECHARGE_PREWAIT; \n //For non-back-to-back reads from row0 (VCCO and VCCAUX pattern)\n else if (~prbs_rdlvl_done && (complex_num_reads_dec == 1) && ~complex_row0_rd_done) \n init_next_state = INIT_RDLVL_COMPLEX_READ_WAIT;\n //For back-to-back reads from row1 (ISI pattern)\n else if (stg1_wr_rd_cnt == 'd1)\n init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT;\n\n INIT_RDLVL_COMPLEX_READ_WAIT:\n if (prech_req_posedge_r || complex_rdlvl_int_ref_req || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1))\n init_next_state = INIT_PRECHARGE_PREWAIT;\n else if (stg1_wr_rd_cnt == 'd1)\n init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT;\n else if (complex_wait_cnt == 'd15)\n init_next_state = INIT_RDLVL_COMPLEX_READ; \n\n \n //********************************************* \n // DQSFOUND calibration (set of 4 reads with gaps)\n //********************************************* \n\n // Read of training data. Note that Stage 2 is not a constant read, \n // instead there is a large gap between each set of back-to-back reads\n INIT_RDLVL_STG2_READ:\n // 4 read commands issued back-to-back\n if (num_reads == 'b1)\n init_next_state = INIT_RDLVL_STG2_READ_WAIT;\n\n // Wait before issuing the next set of reads. If a precharge request\n // comes in then handle - this can occur after stage 2 calibration is\n // completed for a DQS group\n INIT_RDLVL_STG2_READ_WAIT:\n if (~(phy_ctl_full || phy_cmd_full)) begin\n if (pi_dqs_found_rank_done ||\n pi_dqs_found_done || prech_req_posedge_r)\n init_next_state = INIT_PRECHARGE_PREWAIT;\n else if (cnt_cmd_done_r)\n init_next_state = INIT_RDLVL_STG2_READ;\n end\n \n \n //******************************************************************\n // MPR Read Leveling for DDR3 OCLK_DELAYED calibration\n //******************************************************************\n \n // Issue Load Mode Register 3 command with A[2]=1, A[1:0]=2'b00\n // to enable Multi Purpose Register (MPR) Read\n INIT_MPR_RDEN:\n init_next_state = INIT_MPR_WAIT;\n \n //Wait tMRD, tMOD\n INIT_MPR_WAIT:\n if (cnt_cmd_done_r) begin\n init_next_state = INIT_MPR_READ;\n end\n \n // Issue back-to-back read commands to read from MPR with\n // Address bus 0x0000 for BL=8. DQ[0] will output the pre-defined\n // MPR pattern of 01010101 (Rise0 = 1'b0, Fall0 = 1'b1 ...)\n INIT_MPR_READ:\n if (mpr_rdlvl_done || mpr_rnk_done || rdlvl_prech_req)\n init_next_state = INIT_MPR_DISABLE_PREWAIT;\n \n INIT_MPR_DISABLE_PREWAIT:\n if (cnt_cmd_done_r)\n init_next_state = INIT_MPR_DISABLE;\n \n // Issue Load Mode Register 3 command with A[2]=0 to disable\n // MPR read\n INIT_MPR_DISABLE:\n init_next_state = INIT_MPR_DISABLE_WAIT;\n \n INIT_MPR_DISABLE_WAIT:\n init_next_state = INIT_PRECHARGE_PREWAIT;\n \n \n //***********************************************************************\n // OCLKDELAY Calibration\n //***********************************************************************\n \n // This calibration requires single write followed by single read to\n // determine the Phaser_Out stage 3 delay required to center write DQS\n // in write DQ valid window.\n \n // Single Row Activate command before issuing Write command\n INIT_OCLKDELAY_ACT:\n init_next_state = INIT_OCLKDELAY_ACT_WAIT;\n \n INIT_OCLKDELAY_ACT_WAIT:\n if (cnt_cmd_done_r && ~oclk_prech_req)\n init_next_state = INIT_OCLKDELAY_WRITE;\n else if (oclkdelay_calib_done || prech_req_posedge_r)\n init_next_state = INIT_PRECHARGE_PREWAIT;\n \n INIT_OCLKDELAY_WRITE:\n if (oclk_wr_cnt == 4'd1)\n init_next_state = INIT_OCLKDELAY_WRITE_WAIT;\n \n INIT_OCLKDELAY_WRITE_WAIT:\n if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin\n if (oclkdelay_int_ref_req)\n init_next_state = INIT_PRECHARGE_PREWAIT;\n else\t\t\t\n init_next_state = INIT_OCLKDELAY_READ;\n\t\tend\n \n INIT_OCLKDELAY_READ:\n init_next_state = INIT_OCLKDELAY_READ_WAIT;\n\n INIT_OCLKDELAY_READ_WAIT:\n if (~(phy_ctl_full || phy_cmd_full)) begin\n if ((oclk_calib_resume_level || oclk_calib_resume) && ~oclkdelay_int_ref_req)\n init_next_state = INIT_OCLKDELAY_WRITE;\n else if (oclkdelay_calib_done || prech_req_posedge_r ||\n wrlvl_final || oclkdelay_int_ref_req)\n init_next_state = INIT_PRECHARGE_PREWAIT;\n\t\t else if (oclkdelay_center_calib_start)\n\t\t init_next_state = INIT_OCAL_CENTER_WRITE_WAIT;\n end\n \n \n //********************************************* \n // Write calibration \n //*********************************************\n\n // single row activate \n INIT_WRCAL_ACT:\n init_next_state = INIT_WRCAL_ACT_WAIT;\n\n // hang out for awhile before issuing subsequent column command\n INIT_WRCAL_ACT_WAIT:\n if (cnt_cmd_done_r && ~wrcal_prech_req)\n init_next_state = INIT_WRCAL_WRITE;\n else if (wrcal_done || prech_req_posedge_r)\n init_next_state = INIT_PRECHARGE_PREWAIT; \n\n // Write training pattern for write calibration\n INIT_WRCAL_WRITE:\n // Once we've issued enough commands for 8 words - proceed to reads\n //if (burst_addr_r == 1'b1)\n if (wrcal_wr_cnt == 4'd1)\n init_next_state = INIT_WRCAL_WRITE_READ;\n\n // Write-read turnaround\n INIT_WRCAL_WRITE_READ: \n if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) \n init_next_state = INIT_WRCAL_READ;\n else if (dqsfound_retry)\n init_next_state = INIT_RDLVL_STG2_READ_WAIT;\n\n\n INIT_WRCAL_READ:\n if (burst_addr_r == 1'b1)\n init_next_state = INIT_WRCAL_READ_WAIT;\n \n INIT_WRCAL_READ_WAIT:\n if (~(phy_ctl_full || phy_cmd_full)) begin\n if (wrcal_resume_r) begin\n if (wrcal_final_chk)\n init_next_state = INIT_WRCAL_READ;\n else\n init_next_state = INIT_WRCAL_WRITE;\n end else if (wrcal_done || prech_req_posedge_r || wrcal_act_req ||\n // Added to support PO fine delay inc when TG errors\n wrlvl_byte_redo || (temp_wrcal_done && ~temp_lmr_done))\n init_next_state = INIT_PRECHARGE_PREWAIT;\n else if (dqsfound_retry)\n init_next_state = INIT_RDLVL_STG2_READ_WAIT;\n else if (wrcal_read_req && cnt_wrcal_rd)\n init_next_state = INIT_WRCAL_MULT_READS;\n end \n\n INIT_WRCAL_MULT_READS:\n // multiple read commands issued back-to-back\n if (wrcal_reads == 'b1)\n init_next_state = INIT_WRCAL_READ_WAIT; \n\n //********************************************* \n // Handling of precharge during and in between read-level stages\n //********************************************* \n\n // Make sure we aren't violating any timing specs by precharging\n // immediately\n INIT_PRECHARGE_PREWAIT:\n if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))\n init_next_state = INIT_PRECHARGE; \n \n // Initiate precharge\n INIT_PRECHARGE: \n init_next_state = INIT_PRECHARGE_WAIT; \n\n INIT_PRECHARGE_WAIT: \n if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin\n if ((wrcal_sanity_chk_done && (DRAM_TYPE == \"DDR3\")) || \n (rdlvl_stg1_done && prbs_rdlvl_done && pi_dqs_found_done && \n (DRAM_TYPE == \"DDR2\")))\n init_next_state = INIT_DONE; \n else if ((wrcal_done || (WRLVL == \"OFF\")) && rdlvl_stg1_done && prbs_rdlvl_done &&\n pi_dqs_found_done && complex_oclkdelay_calib_done && wrlvl_done_r1 && ((ddr3_lm_done_r) || (DRAM_TYPE == \"DDR2\")))\n init_next_state = INIT_WRCAL_ACT; \n else if ((wrcal_done || (WRLVL == \"OFF\") || (~wrcal_done && temp_wrcal_done && ~temp_lmr_done)) \n && (rdlvl_stg1_done || (~wrcal_done && temp_wrcal_done && ~temp_lmr_done)) \n && prbs_rdlvl_done && complex_oclkdelay_calib_done && wrlvl_done_r1 &rdlvl_stg1_done && pi_dqs_found_done) begin\n // after all calibration program the correct burst length\n init_next_state = INIT_LOAD_MR; \n // Added to support PO fine delay inc when TG errors\n end else if (~wrcal_done && temp_wrcal_done && temp_lmr_done)\n init_next_state = INIT_WRCAL_READ_WAIT;\n else if (rdlvl_stg1_done && pi_dqs_found_done && (WRLVL == \"ON\"))\n // If read leveling finished, proceed to write calibration\n init_next_state = INIT_REFRESH; \n else\n // Otherwise, open row for read-leveling purposes\n init_next_state = INIT_REFRESH;\n end\n \n //*******************************************************\n // COMPLEX OCLK calibration - for fragmented write\n //******************************************************* \n INIT_OCAL_COMPLEX_ACT:\n init_next_state = INIT_OCAL_COMPLEX_ACT_WAIT;\n \n INIT_OCAL_COMPLEX_ACT_WAIT:\n if (complex_wait_cnt =='d15)\n init_next_state = INIT_RDLVL_STG1_WRITE;\n \n INIT_OCAL_COMPLEX_WRITE_WAIT:\n if (prech_req_posedge_r || (complex_oclkdelay_calib_done && ~complex_oclkdelay_calib_done_r1))\n init_next_state = INIT_PRECHARGE_PREWAIT;\n else if (stg1_wr_rd_cnt == 'd1)\n init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT;\n else if (complex_wait_cnt == 'd15)\n init_next_state = INIT_RDLVL_STG1_WRITE; \n \n //wait for all srg2/stg3 tap movement is done and go back to write again \n INIT_OCAL_COMPLEX_RESUME_WAIT:\n if (complex_oclk_calib_resume)\n init_next_state = INIT_RDLVL_STG1_WRITE; \n else if (complex_oclkdelay_calib_done || complex_ocal_ref_req ) \n init_next_state = INIT_PRECHARGE_PREWAIT; \n\n //*******************************************************\n // OCAL STG3 Centering calibration \n //*******************************************************\n INIT_OCAL_CENTER_ACT: \n init_next_state = INIT_OCAL_CENTER_ACT_WAIT;\n \n INIT_OCAL_CENTER_ACT_WAIT:\n\t if (ocal_act_wait_cnt == 'd15)\n\t init_next_state = INIT_OCAL_CENTER_WRITE_WAIT;\n\t \n\t INIT_OCAL_CENTER_WRITE:\n if(!oclk_center_write_resume && !lim_wr_req)\n init_next_state = INIT_OCAL_CENTER_WRITE_WAIT;\n \n INIT_OCAL_CENTER_WRITE_WAIT:\n\t //if (oclkdelay_center_calib_done || prech_req_posedge_r)\n\t\tif (prech_req_posedge_r)\n init_next_state = INIT_PRECHARGE_PREWAIT;\n else if (lim_done && ~mask_lim_done && ~complex_mask_lim_done && oclkdelay_calib_done && ~oclkdelay_center_calib_start)\n\t\t init_next_state = INIT_OCAL_COMPLEX_ACT_WAIT;\n\t\telse if (lim_done && ~mask_lim_done && ~complex_mask_lim_done && ~oclkdelay_center_calib_start)\n\t\t init_next_state = INIT_OCLKDELAY_READ_WAIT; \n else if (oclk_center_write_resume || lim_wr_req)\n init_next_state = INIT_OCAL_CENTER_WRITE;\n \n //*******************************************************\n // Initialization/Calibration done. Take a long rest, relax\n //*******************************************************\n\n INIT_DONE:\n init_next_state = INIT_DONE;\n\n endcase\n end\n \n //*****************************************************************\n // Initialization done signal - asserted before leveling starts\n //*****************************************************************\n\n \n always @(posedge clk)\n if (rst)\n mem_init_done_r <= #TCQ 1'b0;\n else if ((!cnt_dllk_zqinit_done_r && \n (cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT) &&\n (chip_cnt_r == RANKS-1) && (DRAM_TYPE == \"DDR3\"))\n || ( (init_state_r == INIT_LOAD_MR_WAIT) &&\n (ddr2_refresh_flag_r) && (chip_cnt_r == RANKS-1)\n && (cnt_init_mr_done_r) && (DRAM_TYPE == \"DDR2\")))\n mem_init_done_r <= #TCQ 1'b1;\n \n //*****************************************************************\n // Write Calibration signal to PHY Control Block - asserted before\n // Write Leveling starts\n //*****************************************************************\n\n //generate\n //if (RANKS < 2) begin: ranks_one\n always @(posedge clk) begin\n if (rst || (done_dqs_tap_inc &&\n (init_state_r == INIT_WRLVL_LOAD_MR2)))\n write_calib <= #TCQ 1'b0;\n else if (wrlvl_active_r1)\n write_calib <= #TCQ 1'b1;\n end\n //end else begin: ranks_two\n // always @(posedge clk) begin\n // if (rst || \n // ((init_state_r1 == INIT_WRLVL_LOAD_MR_WAIT) && \n // ((wrlvl_rank_done_r2 && (chip_cnt_r == RANKS-1)) || \n // (SIM_CAL_OPTION == \"FAST_CAL\"))))\n // write_calib <= #TCQ 1'b0;\n // else if (wrlvl_active_r1)\n // write_calib <= #TCQ 1'b1;\n // end\n //end\n //endgenerate\n \n //*****************************************************************\n // Read Calibration signal to PHY Control Block - asserted after\n // Write Leveling during PHASER_IN phase locking stage.\n // Must be de-asserted before Read Leveling\n //*****************************************************************\n \n always @(posedge clk) begin\n if (rst || pi_calib_done_r1)\n read_calib_int <= #TCQ 1'b0;\n else if (~pi_calib_done_r1 && (init_state_r == INIT_RDLVL_ACT_WAIT) &&\n (cnt_cmd_r == CNTNEXT_CMD))\n read_calib_int <= #TCQ 1'b1;\n end\n \n always @(posedge clk)\n read_calib_r <= #TCQ read_calib_int;\n \n \n always @(posedge clk) begin\n if (rst || pi_calib_done_r1)\n read_calib <= #TCQ 1'b0;\n else if (~pi_calib_done_r1 && (init_state_r == INIT_PI_PHASELOCK_READS))\n read_calib <= #TCQ 1'b1;\n end\n\n \n always @(posedge clk)\n if (rst)\n pi_calib_done_r <= #TCQ 1'b0;\n else if (pi_calib_rank_done_r)// && (chip_cnt_r == RANKS-1))\n pi_calib_done_r <= #TCQ 1'b1;\n \n always @(posedge clk)\n if (rst)\n pi_calib_rank_done_r <= #TCQ 1'b0;\n else if (pi_phase_locked_all_r3 && ~pi_phase_locked_all_r4)\n pi_calib_rank_done_r <= #TCQ 1'b1;\n else\n pi_calib_rank_done_r <= #TCQ 1'b0;\n\n always @(posedge clk) begin\n if (rst || ((PRE_REV3ES == \"ON\") && temp_wrcal_done && ~temp_wrcal_done_r))\n pi_phaselock_timer <= #TCQ 'd0;\n else if (((init_state_r == INIT_PI_PHASELOCK_READS) &&\n (pi_phaselock_timer != PHASELOCKED_TIMEOUT)) ||\n tg_timer_go)\n pi_phaselock_timer <= #TCQ pi_phaselock_timer + 1;\n else\n pi_phaselock_timer <= #TCQ pi_phaselock_timer;\n end\n \n assign pi_phase_locked_err = (pi_phaselock_timer == PHASELOCKED_TIMEOUT) ? 1'b1 : 1'b0;\n\n //*****************************************************************\n // DDR3 final burst length programming done. For DDR3 during\n // calibration the burst length is fixed to BL8. After calibration\n // the correct burst length is programmed. \n //*****************************************************************\n always @(posedge clk)\n if (rst)\n ddr3_lm_done_r <= #TCQ 1'b0;\n else if ((init_state_r == INIT_LOAD_MR_WAIT) &&\n (chip_cnt_r == RANKS-1) && wrcal_done)\n ddr3_lm_done_r <= #TCQ 1'b1;\n\n always @(posedge clk) begin\n pi_dqs_found_rank_done_r <= #TCQ pi_dqs_found_rank_done;\n pi_phase_locked_all_r1 <= #TCQ pi_phase_locked_all;\n pi_phase_locked_all_r2 <= #TCQ pi_phase_locked_all_r1;\n pi_phase_locked_all_r3 <= #TCQ pi_phase_locked_all_r2;\n pi_phase_locked_all_r4 <= #TCQ pi_phase_locked_all_r3;\n pi_dqs_found_all_r <= #TCQ pi_dqs_found_done;\n pi_calib_done_r1 <= #TCQ pi_calib_done_r;\n end\n \n //***************************************************************************\n // Logic for deep memory (multi-rank) configurations\n //***************************************************************************\n\n // For DDR3 asserted when \n\ngenerate\n if (RANKS < 2) begin: single_rank\n always @(posedge clk)\n chip_cnt_r <= #TCQ 2'b00;\n end else begin: dual_rank \n always @(posedge clk)\n if (rst ||\n // Set chip_cnt_r to 2'b00 after both Ranks are read leveled \n (rdlvl_stg1_done && prbs_rdlvl_done && ~wrcal_done && (SKIP_CALIB == \"FALSE\")) ||\n // Set chip_cnt_r to 2'b00 after both Ranks are write leveled \n (wrlvl_done_r &&\n (init_state_r==INIT_WRLVL_LOAD_MR2_WAIT)))begin \n chip_cnt_r <= #TCQ 2'b00;\n end else if ((((init_state_r == INIT_WAIT_DLLK_ZQINIT) &&\n (cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT)) && \n (DRAM_TYPE == \"DDR3\")) ||\n ((init_state_r==INIT_REFRESH_RNK2_WAIT) &&\n (cnt_cmd_r=='d36)) ||\n //mpr_rnk_done ||\n //(rdlvl_stg1_rank_done && ~rdlvl_last_byte_done) ||\n //(stg1_wr_done && (init_state_r == INIT_REFRESH) &&\n //~(rnk_ref_cnt && rdlvl_last_byte_done)) ||\n \n // Increment chip_cnt_r to issue Refresh to second rank\n (~pi_dqs_found_all_r &&\n (init_state_r==INIT_PRECHARGE_PREWAIT) &&\n (cnt_cmd_r=='d36) && (SKIP_CALIB == \"FALSE\")) ||\n \n // Increment chip_cnt_r when DQSFOUND done for the Rank\n (pi_dqs_found_rank_done && ~pi_dqs_found_rank_done_r && (SKIP_CALIB == \"FALSE\")) ||\n ((init_state_r == INIT_LOAD_MR_WAIT)&& cnt_cmd_done_r \n && wrcal_done) ||\n ((init_state_r == INIT_DDR2_MULTI_RANK)\n && (DRAM_TYPE == \"DDR2\"))) begin\n if ((~mem_init_done_r || ~rdlvl_stg1_done || ~pi_dqs_found_done ||\n // condition to increment chip_cnt during\n // final burst length programming for DDR3 \n ~pi_calib_done_r || wrcal_done) //~mpr_rdlvl_done || \n && (chip_cnt_r != RANKS-1)) \n chip_cnt_r <= #TCQ chip_cnt_r + 1;\n else\n chip_cnt_r <= #TCQ 2'b00;\n end\n end\n endgenerate \n// verilint STARC-2.2.3.3 off\ngenerate\n if ((REG_CTRL == \"ON\") && (RANKS == 1)) begin: DDR3_RDIMM_1rank\n always @(posedge clk) begin\n if (rst)\n phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};\n else if (init_state_r == INIT_REG_WRITE) begin\n phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};\n if(!(CWL_M%2)) begin\n phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0;\n phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0;\n end else begin\n phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0;\n phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0;\n end\n end else if ((init_state_r == INIT_LOAD_MR) ||\n (init_state_r == INIT_MPR_RDEN) ||\n (init_state_r == INIT_MPR_DISABLE) ||\n (init_state_r == INIT_WRLVL_START) ||\n (init_state_r == INIT_WRLVL_LOAD_MR) ||\n (init_state_r == INIT_WRLVL_LOAD_MR2) ||\n (init_state_r == INIT_ZQCL) ||\n (init_state_r == INIT_RDLVL_ACT) ||\n (init_state_r == INIT_WRCAL_ACT) ||\n (init_state_r == INIT_OCLKDELAY_ACT) ||\n (init_state_r == INIT_OCAL_COMPLEX_ACT) ||\n (init_state_r == INIT_OCAL_CENTER_ACT) || \n (init_state_r == INIT_PRECHARGE) ||\n (init_state_r == INIT_DDR2_PRECHARGE) ||\n (init_state_r == INIT_REFRESH) ||\n (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||\n (init_state_r == INIT_RDLVL_COMPLEX_ACT) ||\n (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin\n phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};\n if (!(CWL_M % 2)) //even CWL \n phy_int_cs_n[0] <= #TCQ 1'b0;\n else // odd CWL\n phy_int_cs_n[1*nCS_PER_RANK] <= #TCQ 1'b0;\n end else\n phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};\n end\n end else if (RANKS == 1) begin: DDR3_1rank\n always @(posedge clk) begin\n if (rst)\n phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};\n else if ((init_state_r == INIT_LOAD_MR) ||\n (init_state_r == INIT_MPR_RDEN) ||\n (init_state_r == INIT_MPR_DISABLE) ||\n (init_state_r == INIT_WRLVL_START) ||\n (init_state_r == INIT_WRLVL_LOAD_MR) ||\n (init_state_r == INIT_WRLVL_LOAD_MR2) ||\n (init_state_r == INIT_ZQCL) ||\n (init_state_r == INIT_RDLVL_ACT) ||\n (init_state_r == INIT_WRCAL_ACT) ||\n (init_state_r == INIT_OCLKDELAY_ACT) ||\n (init_state_r == INIT_OCAL_COMPLEX_ACT) ||\n (init_state_r == INIT_OCAL_CENTER_ACT) || \n (init_state_r == INIT_PRECHARGE) ||\n (init_state_r == INIT_DDR2_PRECHARGE) ||\n (init_state_r == INIT_REFRESH) ||\n (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||\n (init_state_r == INIT_RDLVL_COMPLEX_ACT) ||\n (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin\n phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};\n if (!(CWL_M % 2)) begin //even CWL\n for (n = 0; n < nCS_PER_RANK; n = n + 1) begin \n phy_int_cs_n[n] <= #TCQ 1'b0;\n end\n end else begin //odd CWL\n for (p = nCS_PER_RANK; p < 2*nCS_PER_RANK; p = p + 1) begin \n phy_int_cs_n[p] <= #TCQ 1'b0;\n end\n end\n end else\n phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};\n end\n end else if ((REG_CTRL == \"ON\") && (RANKS == 2)) begin: DDR3_2rank\n always @(posedge clk) begin\n if (rst)\n phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};\n else if (init_state_r == INIT_REG_WRITE) begin\n phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};\n if(!(CWL_M%2)) begin\n phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0;\n phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0;\n end else begin\n phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0;\n phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0;\n end\n end else begin\n phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};\n case (chip_cnt_r)\n 2'b00:begin\n if ((init_state_r == INIT_LOAD_MR) ||\n (init_state_r == INIT_MPR_RDEN) ||\n (init_state_r == INIT_MPR_DISABLE) ||\n (init_state_r == INIT_WRLVL_START) ||\n (init_state_r == INIT_WRLVL_LOAD_MR) ||\n (init_state_r == INIT_WRLVL_LOAD_MR2) ||\n (init_state_r == INIT_ZQCL) ||\n (init_state_r == INIT_RDLVL_ACT) ||\n (init_state_r == INIT_WRCAL_ACT) ||\n (init_state_r == INIT_OCLKDELAY_ACT) ||\n (init_state_r == INIT_OCAL_COMPLEX_ACT) || \n (init_state_r == INIT_OCAL_CENTER_ACT) || \n (init_state_r == INIT_PRECHARGE) ||\n (init_state_r == INIT_DDR2_PRECHARGE) ||\n (init_state_r == INIT_REFRESH) ||\n (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||\n (init_state_r == INIT_RDLVL_COMPLEX_ACT) ||\n (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin\n phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};\n if (!(CWL_M % 2)) //even CWL \n phy_int_cs_n[0] <= #TCQ 1'b0;\n else // odd CWL\n phy_int_cs_n[1*CS_WIDTH*nCS_PER_RANK] <= #TCQ 1'b0;\n end else\n phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};\n //for (n = 0; n < nCS_PER_RANK*nCK_PER_CLK*2; n = n + (nCS_PER_RANK*2)) begin \n //\n // phy_int_cs_n[n+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}};\n //end\n end\n 2'b01:begin\n if ((init_state_r == INIT_LOAD_MR) ||\n (init_state_r == INIT_MPR_RDEN) ||\n (init_state_r == INIT_MPR_DISABLE) ||\n (init_state_r == INIT_WRLVL_START) ||\n (init_state_r == INIT_WRLVL_LOAD_MR) ||\n (init_state_r == INIT_WRLVL_LOAD_MR2) ||\n (init_state_r == INIT_ZQCL) ||\n (init_state_r == INIT_RDLVL_ACT) ||\n (init_state_r == INIT_WRCAL_ACT) ||\n (init_state_r == INIT_OCLKDELAY_ACT) ||\n (init_state_r == INIT_OCAL_COMPLEX_ACT) ||\n (init_state_r == INIT_OCAL_CENTER_ACT) ||\n (init_state_r == INIT_PRECHARGE) ||\n (init_state_r == INIT_DDR2_PRECHARGE) ||\n (init_state_r == INIT_REFRESH) ||\n (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||\n (init_state_r == INIT_RDLVL_COMPLEX_ACT) ||\n (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin\n phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};\n if (!(CWL_M % 2)) //even CWL \n phy_int_cs_n[1] <= #TCQ 1'b0;\n else // odd CWL\n phy_int_cs_n[1+1*CS_WIDTH*nCS_PER_RANK] <= #TCQ 1'b0;\n end else\n phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};\n //for (p = nCS_PER_RANK; p < nCS_PER_RANK*nCK_PER_CLK*2; p = p + (nCS_PER_RANK*2)) begin \n //\n // phy_int_cs_n[p+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}};\n //end\n end\n endcase\n end\n end\n end else if (RANKS == 2) begin: DDR3_2rank\n always @(posedge clk) begin\n if (rst)\n phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};\n else if (init_state_r == INIT_REG_WRITE) begin\n phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};\n if(!(CWL_M%2)) begin\n phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0;\n phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0;\n end else begin\n phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0;\n phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0;\n end\n end else begin\n phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};\n case (chip_cnt_r)\n 2'b00:begin\n if ((init_state_r == INIT_LOAD_MR) ||\n (init_state_r == INIT_MPR_RDEN) ||\n (init_state_r == INIT_MPR_DISABLE) ||\n (init_state_r == INIT_WRLVL_START) ||\n (init_state_r == INIT_WRLVL_LOAD_MR) ||\n (init_state_r == INIT_WRLVL_LOAD_MR2) ||\n (init_state_r == INIT_ZQCL) ||\n (init_state_r == INIT_RDLVL_ACT) ||\n (init_state_r == INIT_WRCAL_ACT) ||\n (init_state_r == INIT_OCLKDELAY_ACT) ||\n (init_state_r == INIT_OCAL_COMPLEX_ACT) ||\n (init_state_r == INIT_OCAL_CENTER_ACT) ||\n (init_state_r == INIT_PRECHARGE) ||\n (init_state_r == INIT_DDR2_PRECHARGE) ||\n (init_state_r == INIT_REFRESH) ||\n (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||\n (init_state_r == INIT_RDLVL_COMPLEX_ACT) ||\n (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin\n phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};\n if (!(CWL_M % 2)) begin //even CWL \n for (n = 0; n < nCS_PER_RANK; n = n + 1) begin \n phy_int_cs_n[n] <= #TCQ 1'b0;\n end\n end else begin // odd CWL\n for (p = CS_WIDTH*nCS_PER_RANK; p < (CS_WIDTH*nCS_PER_RANK + nCS_PER_RANK); p = p + 1) begin\n phy_int_cs_n[p] <= #TCQ 1'b0;\n end\n end\n end else\n phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};\n //for (n = 0; n < nCS_PER_RANK*nCK_PER_CLK*2; n = n + (nCS_PER_RANK*2)) begin \n //\n // phy_int_cs_n[n+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}};\n //end\n end\n 2'b01:begin\n if ((init_state_r == INIT_LOAD_MR) ||\n (init_state_r == INIT_MPR_RDEN) ||\n (init_state_r == INIT_MPR_DISABLE) ||\n (init_state_r == INIT_WRLVL_START) ||\n (init_state_r == INIT_WRLVL_LOAD_MR) ||\n (init_state_r == INIT_WRLVL_LOAD_MR2) ||\n (init_state_r == INIT_ZQCL) ||\n (init_state_r == INIT_RDLVL_ACT) ||\n (init_state_r == INIT_WRCAL_ACT) ||\n (init_state_r == INIT_OCLKDELAY_ACT) ||\n (init_state_r == INIT_OCAL_COMPLEX_ACT) ||\n (init_state_r == INIT_OCAL_CENTER_ACT) ||\n (init_state_r == INIT_PRECHARGE) ||\n (init_state_r == INIT_DDR2_PRECHARGE) ||\n (init_state_r == INIT_REFRESH) ||\n (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||\n (init_state_r == INIT_RDLVL_COMPLEX_ACT) ||\n (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin\n phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};\n if (!(CWL_M % 2)) begin //even CWL\n for (q = nCS_PER_RANK; q < (2 * nCS_PER_RANK); q = q + 1) begin \n phy_int_cs_n[q] <= #TCQ 1'b0;\n end\n end else begin // odd CWL\n for (m = (nCS_PER_RANK*CS_WIDTH + nCS_PER_RANK); m < (nCS_PER_RANK*CS_WIDTH + 2*nCS_PER_RANK); m = m + 1) begin\n phy_int_cs_n[m] <= #TCQ 1'b0;\n end\n end\n end else\n phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};\n //for (p = nCS_PER_RANK; p < nCS_PER_RANK*nCK_PER_CLK*2; p = p + (nCS_PER_RANK*2)) begin \n //\n // phy_int_cs_n[p+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}};\n //end\n end\n endcase\n end\n end // always @ (posedge clk)\n end \n// verilint STARC-2.2.3.3 on\n // commented out for now. Need it for DDR2 2T timing \n /* end else begin: DDR2\n always @(posedge clk)\n if (rst) begin\n phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};\n end else begin\n if (init_state_r == INIT_REG_WRITE) begin\n // All ranks selected simultaneously\n phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b0}};\n end else if ((wrlvl_odt) ||\n (init_state_r == INIT_LOAD_MR) ||\n (init_state_r == INIT_ZQCL) ||\n (init_state_r == INIT_WRLVL_START) ||\n (init_state_r == INIT_WRLVL_LOAD_MR) ||\n (init_state_r == INIT_WRLVL_LOAD_MR2) ||\n (init_state_r == INIT_RDLVL_ACT) ||\n (init_state_r == INIT_PI_PHASELOCK_READS) ||\n (init_state_r == INIT_RDLVL_STG1_WRITE) ||\n (init_state_r == INIT_RDLVL_STG1_READ) ||\n (init_state_r == INIT_PRECHARGE) ||\n (init_state_r == INIT_RDLVL_STG2_READ) ||\n (init_state_r == INIT_WRCAL_ACT) ||\n (init_state_r == INIT_WRCAL_READ) ||\n (init_state_r == INIT_WRCAL_WRITE) ||\n (init_state_r == INIT_DDR2_PRECHARGE) ||\n (init_state_r == INIT_REFRESH)) begin\n phy_int_cs_n[0] <= #TCQ 1'b0;\n end \n else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; \n end // else: !if(rst)\n end // block: DDR2 */ \nendgenerate\n\n assign phy_cs_n = phy_int_cs_n;\n\n //***************************************************************************\n // Write/read burst logic for calibration\n //***************************************************************************\n\n assign rdlvl_wr = (init_state_r == INIT_OCLKDELAY_WRITE) ||\n (init_state_r == INIT_OCAL_CENTER_WRITE) || \n (init_state_r == INIT_RDLVL_STG1_WRITE) ||\n (init_state_r == INIT_WRCAL_WRITE);\n assign rdlvl_rd = (init_state_r == INIT_PI_PHASELOCK_READS) ||\n ((init_state_r == INIT_RDLVL_STG1_READ) && ~rdlvl_pi_incdec) || //rdlvl pi dec\n (init_state_r == INIT_RDLVL_COMPLEX_READ) ||\n (init_state_r == INIT_RDLVL_STG2_READ) ||\n (init_state_r == INIT_OCLKDELAY_READ) ||\n (init_state_r == INIT_WRCAL_READ) ||\n ((init_state_r == INIT_MPR_READ) && ~rdlvl_pi_incdec) ||\n (init_state_r == INIT_WRCAL_MULT_READS);\n assign rdlvl_wr_rd = rdlvl_wr | rdlvl_rd;\n assign mmcm_wr = (init_state_r == INIT_OCAL_CENTER_WRITE); //used to de-assert cs_n during centering\n// assign mmcm_wr = 'b0; // (init_state_r == INIT_OCAL_CENTER_WRITE);\n\n //***************************************************************************\n // Address generation and logic to count # of writes/reads issued during\n // certain stages of calibration\n //***************************************************************************\n\n // Column address generation logic:\n // Keep track of the current column address - since all bursts are in\n // increments of 8 only during calibration, we need to keep track of\n // addresses [COL_WIDTH-1:3], lower order address bits will always = 0\n\n always @(posedge clk)\n if (rst || wrcal_done)\n burst_addr_r <= #TCQ 1'b0;\n else if ((init_state_r == INIT_WRCAL_ACT_WAIT) ||\n (init_state_r == INIT_OCLKDELAY_ACT_WAIT) ||\n (init_state_r == INIT_OCLKDELAY_WRITE) || \n (init_state_r == INIT_OCLKDELAY_READ) ||\n (init_state_r == INIT_WRCAL_WRITE) ||\n (init_state_r == INIT_WRCAL_WRITE_READ) ||\n (init_state_r == INIT_WRCAL_READ) ||\n (init_state_r == INIT_WRCAL_MULT_READS) ||\n (init_state_r == INIT_WRCAL_READ_WAIT))\n burst_addr_r <= #TCQ 1'b1;\n else if (rdlvl_wr_rd && new_burst_r)\n burst_addr_r <= #TCQ ~burst_addr_r;\n else\n burst_addr_r <= #TCQ 1'b0;\n\n // Read Level Stage 1 requires writes to the entire row since \n // a PRBS pattern is being written. This counter keeps track\n // of the number of writes which depends on the column width\n // The (stg1_wr_rd_cnt==9'd0) condition was added so the col\n // address wraps around during stage1 reads\n always @(posedge clk)\n if (rst || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) && \n ~rdlvl_stg1_done))\n stg1_wr_rd_cnt <= #TCQ NUM_STG1_WR_RD;\n else if (rdlvl_last_byte_done || (stg1_wr_rd_cnt == 9'd1) ||\n (prbs_rdlvl_prech_req && (init_state_r == INIT_RDLVL_ACT_WAIT)) ||\n (init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) ) begin\n if (~complex_row0_wr_done || wr_victim_inc ||\n (complex_row1_wr_done && (~complex_row0_rd_done || (complex_row0_rd_done && complex_row1_rd_done)))) \n stg1_wr_rd_cnt <= #TCQ 'd127;\n else\n stg1_wr_rd_cnt <= #TCQ prbs_rdlvl_done?'d30 :'d22;\n end else if (((init_state_r == INIT_RDLVL_STG1_WRITE) && new_burst_r && ~phy_data_full)\n ||((init_state_r == INIT_RDLVL_COMPLEX_READ) && rdlvl_stg1_done))\n stg1_wr_rd_cnt <= #TCQ stg1_wr_rd_cnt - 1;\n \n always @(posedge clk)\n if (rst)\n wr_victim_inc <= #TCQ 1'b0;\n else if (complex_row0_wr_done && (stg1_wr_rd_cnt == 9'd2) && ~stg1_wr_done)\n wr_victim_inc <= #TCQ 1'b1;\n else\n wr_victim_inc <= #TCQ 1'b0;\n\n always @(posedge clk)\n reset_rd_addr_r1 <= #TCQ reset_rd_addr;\n \ngenerate\n if (FIXED_VICTIM == \"FALSE\") begin: row_cnt_victim_rotate \n always @(posedge clk)\n if (rst || (wr_victim_inc && (complex_row_cnt == DQ_PER_DQS*2-1)) || ~rdlvl_stg1_done_r1 || prbs_rdlvl_done)\n complex_row_cnt <= #TCQ 'd0;\n else if ((((stg1_wr_rd_cnt == 'd22) && ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || \n\t (complex_rdlvl_int_ref_req && (init_state_r == INIT_REFRESH_WAIT) && (cnt_cmd_r == 'd127)))) || \n complex_victim_inc || (complex_sample_cnt_inc_r2 && ~complex_victim_inc) || wr_victim_inc || reset_rd_addr_r1)) begin\n // During writes row count is incremented with every wr_victim_in and stg1_wr_rd_cnt=='d22\n if ((complex_row_cnt < DQ_PER_DQS*2-1) && ~stg1_wr_done)\n complex_row_cnt <= #TCQ complex_row_cnt + 1;\n // During reads row count requires different conditions for increments\n else if (stg1_wr_done) begin\n if (reset_rd_addr_r1)\n complex_row_cnt <= #TCQ 'd0; \n // When looping multiple times in the same victim bit in a byte\n else if (complex_sample_cnt_inc_r2 && ~complex_victim_inc)\n complex_row_cnt <= #TCQ rd_victim_sel*2;\n // When looping through victim bits within a byte\n else if (complex_row_cnt < DQ_PER_DQS*2-1)\n complex_row_cnt <= #TCQ complex_row_cnt + 1;\n // When the number of samples is done and tap is incremented within a byte\n else\n complex_row_cnt <= #TCQ 'd0; \n end\n end\n end else begin: row_cnt_victim_fixed\n always @(posedge clk)\n if (rst || ~rdlvl_stg1_done_r1 || prbs_rdlvl_done)\n complex_row_cnt <= #TCQ 'd0;\n else if ((stg1_wr_rd_cnt == 'd22) && (((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_WAIT) && (complex_wait_cnt == 'd15)) || complex_rdlvl_int_ref_req))\n complex_row_cnt <= #TCQ 'd1;\n else\n complex_row_cnt <= #TCQ 'd0;\n end\nendgenerate\n\n//row count \n\n always @(posedge clk)\n if (rst || (wr_victim_inc && (complex_row_cnt_ocal == COMPLEX_ROW_CNT_BYTE-1)) || ~rdlvl_stg1_done_r1 || prbs_rdlvl_done_pulse || complex_byte_rd_done)\n complex_row_cnt_ocal <= #TCQ 'd0;\n else if ( prbs_rdlvl_done && (((stg1_wr_rd_cnt == 'd30) && (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE)) || \n (complex_sample_cnt_inc_r2) || wr_victim_inc)) begin\n // During writes row count is incremented with every wr_victim_in and stg1_wr_rd_cnt=='d22\n if (complex_row_cnt_ocal < COMPLEX_ROW_CNT_BYTE-1) begin\n complex_row_cnt_ocal <= #TCQ complex_row_cnt_ocal + 1;\n end\n end \n \n always @(posedge clk)\n if (rst)\n complex_odt_ext <= #TCQ 1'b0;\n else if ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_PRECHARGE))\n complex_odt_ext <= #TCQ 1'b0;\n else if (rdlvl_stg1_done_r1 && (stg1_wr_rd_cnt == 9'd1) && (init_state_r == INIT_RDLVL_STG1_WRITE))\n complex_odt_ext <= #TCQ 1'b1;\n \n always @(posedge clk)\n if (rst || (wr_victim_inc && (complex_row_cnt == DQ_PER_DQS*2-1))) begin \n wr_victim_sel <= #TCQ 'd0;\n end else if (rdlvl_stg1_done_r1 && wr_victim_inc) begin\n wr_victim_sel <= #TCQ wr_victim_sel + 1;\n end\n \n always @(posedge clk)\n if (rst) begin\n wr_victim_sel_ocal <= #TCQ 'd0;\n end else if (wr_victim_inc && (complex_row_cnt_ocal == COMPLEX_ROW_CNT_BYTE-1)) begin\n wr_victim_sel_ocal <= #TCQ 'd0;\n end else if (prbs_rdlvl_done && wr_victim_inc) begin\n wr_victim_sel_ocal <= #TCQ wr_victim_sel_ocal + 1;\n end\n\n always @(posedge clk)\n if (rst) begin\n victim_sel <= #TCQ 'd0;\n victim_byte_cnt <= #TCQ 'd0;\n end else if ((~stg1_wr_done && ~prbs_rdlvl_done) || (prbs_rdlvl_done && ~complex_wr_done)) begin\n victim_sel <= #TCQ prbs_rdlvl_done? wr_victim_sel_ocal: wr_victim_sel;\n victim_byte_cnt <= #TCQ 'd0; \n end else begin\n if( (init_state_r == INIT_RDLVL_COMPLEX_ACT) || reset_rd_addr)\n victim_sel <= #TCQ prbs_rdlvl_done? complex_ocal_rd_victim_sel:rd_victim_sel; \n victim_byte_cnt <= #TCQ 'd0; \n end\n \ngenerate\n if (FIXED_VICTIM == \"FALSE\") begin: wr_done_victim_rotate\n always @(posedge clk)\n if (rst || (wr_victim_inc && (complex_row_cnt < DQ_PER_DQS*2-1) && ~prbs_rdlvl_done) || \n (wr_victim_inc && prbs_rdlvl_done && complex_row_cnt_ocal 'd85) begin\n if (complex_num_reads < 'd6)\n complex_num_reads <= #TCQ complex_num_reads + 1;\n else\n complex_num_reads <= #TCQ 'd1;\n // Initila value for VCCAUX pattern is 3, 7, and 12\n end else if (stg1_wr_rd_cnt > 'd73) begin\n if (stg1_wr_rd_cnt == 'd85) \n complex_num_reads <= #TCQ 'd3;\n else if (complex_num_reads < 'd5)\n complex_num_reads <= #TCQ complex_num_reads + 1;\n end else if (stg1_wr_rd_cnt > 'd39) begin\n if (stg1_wr_rd_cnt == 'd73) \n complex_num_reads <= #TCQ 'd7;\n else if (complex_num_reads < 'd10)\n complex_num_reads <= #TCQ complex_num_reads + 1;\n end else begin\n if (stg1_wr_rd_cnt == 'd39) \n complex_num_reads <= #TCQ 'd12;\n else if (complex_num_reads < 'd14)\n complex_num_reads <= #TCQ complex_num_reads + 1;\n end \n // Initialize to 1 at the start of reads or after precharge and activate\n end else if ((((init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT)) && ~ext_int_ref_req) ||\n\t ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) && (stg1_wr_rd_cnt == 'd22)))\n complex_num_reads <= #TCQ 'd1;\n\n always @(posedge clk)\n if (rst)\n complex_num_reads_dec <= #TCQ 'd1;\n else if (((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) && (complex_wait_cnt == 'd15) && ~complex_row0_rd_done) ||\n ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT)))\n complex_num_reads_dec <= #TCQ complex_num_reads;\n else if ((init_state_r == INIT_RDLVL_COMPLEX_READ) && (complex_num_reads_dec > 'd0))\n complex_num_reads_dec <= #TCQ complex_num_reads_dec - 1;\n\n always @(posedge clk)\n if (rst)\n complex_address <= #TCQ 'd0;\n else if (((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) && (init_state_r1 != INIT_RDLVL_COMPLEX_READ_WAIT)) ||\n ((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (init_state_r1 != INIT_OCAL_COMPLEX_WRITE_WAIT))) \n complex_address <= #TCQ phy_address[COL_WIDTH-1:0];\n \n\n always @ (posedge clk)\n if (rst) \n complex_oclkdelay_calib_start_int <= #TCQ 'b0;\n else if ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT) && prbs_last_byte_done_r) // changed for new algo 3/26\n complex_oclkdelay_calib_start_int <= #TCQ 'b1;\n\t \n always @(posedge clk) begin\n\tcomplex_oclkdelay_calib_start_r1 <= #TCQ complex_oclkdelay_calib_start_int;\n complex_oclkdelay_calib_start_r2 <= #TCQ complex_oclkdelay_calib_start_r1;\n end\n \n always @ (posedge clk)\n if (rst) \n complex_oclkdelay_calib_start <= #TCQ 'b0;\n else if (complex_oclkdelay_calib_start_int && (init_state_r == INIT_OCAL_CENTER_WRITE_WAIT) && prbs_rdlvl_done) // changed for new algo 3/26\n complex_oclkdelay_calib_start <= #TCQ 'b1;\n \n //packet fragmentation for complex oclkdealy calib write\n always @(posedge clk)\n if (rst || prbs_rdlvl_done_pulse) begin\n complex_num_writes <= #TCQ 'd1;\n end else if ((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (complex_wait_cnt == 'd14) && ~complex_row0_wr_done) begin\n if (stg1_wr_rd_cnt > 'd85) begin\n if (complex_num_writes < 'd6)\n complex_num_writes <= #TCQ complex_num_writes + 1;\n else\n complex_num_writes <= #TCQ 'd1;\n // Initila value for VCCAUX pattern is 3, 7, and 12\n end else if (stg1_wr_rd_cnt > 'd73) begin\n if (stg1_wr_rd_cnt == 'd85) \n complex_num_writes <= #TCQ 'd3;\n else if (complex_num_writes < 'd5)\n complex_num_writes <= #TCQ complex_num_writes + 1;\n end else if (stg1_wr_rd_cnt > 'd39) begin\n if (stg1_wr_rd_cnt == 'd73) \n complex_num_writes <= #TCQ 'd7;\n else if (complex_num_writes < 'd10)\n complex_num_writes <= #TCQ complex_num_writes + 1;\n end else begin\n if (stg1_wr_rd_cnt == 'd39) \n complex_num_writes <= #TCQ 'd12;\n else if (complex_num_writes < 'd14)\n complex_num_writes <= #TCQ complex_num_writes + 1;\n end \n // Initialize to 1 at the start of write or after precharge and activate\n end else if ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && complex_row0_wr_done)\n complex_num_writes <= #TCQ 'd30;\n else if (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT)\n complex_num_writes <= #TCQ 'd1; \n\n always @(posedge clk)\n if (rst || prbs_rdlvl_done_pulse)\n complex_num_writes_dec <= #TCQ 'd1;\n else if (((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (complex_wait_cnt == 'd15) && ~complex_row0_rd_done) ||\n ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT)))\n complex_num_writes_dec <= #TCQ complex_num_writes;\n else if ((init_state_r == INIT_RDLVL_STG1_WRITE) && (complex_num_writes_dec > 'd0))\n complex_num_writes_dec <= #TCQ complex_num_writes_dec - 1;\n\n always @(posedge clk)\n if (rst)\n complex_sample_cnt_inc_ocal <= #TCQ 1'b0;\n else if ((stg1_wr_rd_cnt == 9'd1) && complex_byte_rd_done && prbs_rdlvl_done)\n complex_sample_cnt_inc_ocal <= #TCQ 1'b1;\n else\n complex_sample_cnt_inc_ocal <= #TCQ 1'b0;\n\n always @(posedge clk)\n if (rst)\n complex_sample_cnt_inc <= #TCQ 1'b0;\n else if ((stg1_wr_rd_cnt == 9'd1) && complex_row1_rd_done)\n complex_sample_cnt_inc <= #TCQ 1'b1;\n else\n complex_sample_cnt_inc <= #TCQ 1'b0;\n \n always @(posedge clk) begin\n complex_sample_cnt_inc_r1 <= #TCQ complex_sample_cnt_inc;\n complex_sample_cnt_inc_r2 <= #TCQ complex_sample_cnt_inc_r1;\n end\n \n //complex refresh req \n always @ (posedge clk) begin\n if(rst || (init_state_r == INIT_OCAL_COMPLEX_ACT) || \n (prbs_rdlvl_done && (init_state_r == INIT_RDLVL_COMPLEX_ACT)) )\n complex_ocal_ref_done <= #TCQ 1'b1; \n else if (init_state_r == INIT_RDLVL_STG1_WRITE)\n complex_ocal_ref_done <= #TCQ 1'b0; \n end\n\n //complex ocal odt extention\n always @(posedge clk)\n if (rst)\n complex_ocal_odt_ext <= #TCQ 1'b0;\n else if (((init_state_r == INIT_PRECHARGE_PREWAIT) && cnt_cmd_done_m7_r) || (init_state_r == INIT_OCLKDELAY_READ_WAIT))\n complex_ocal_odt_ext <= #TCQ 1'b0;\n else if ((init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE_WAIT))\n complex_ocal_odt_ext <= #TCQ 1'b1;\n\n // OCLKDELAY calibration requires multiple writes because\n // write can be up to 2 cycles early since OCLKDELAY tap\n // can go down to 0\n always @(posedge clk)\n if (rst || (init_state_r == INIT_OCLKDELAY_WRITE_WAIT) ||\n (oclk_wr_cnt == 4'd0))\n oclk_wr_cnt <= #TCQ NUM_STG1_WR_RD;\n else if ((init_state_r == INIT_OCLKDELAY_WRITE) && \n new_burst_r && ~phy_data_full)\n oclk_wr_cnt <= #TCQ oclk_wr_cnt - 1;\n \n // Write calibration requires multiple writes because\n // write can be up to 2 cycles early due to new write\n // leveling algorithm to avoid late writes\n always @(posedge clk)\n if (rst || (init_state_r == INIT_WRCAL_WRITE_READ) ||\n (wrcal_wr_cnt == 4'd0))\n wrcal_wr_cnt <= #TCQ NUM_STG1_WR_RD;\n else if ((init_state_r == INIT_WRCAL_WRITE) && \n new_burst_r && ~phy_data_full)\n wrcal_wr_cnt <= #TCQ wrcal_wr_cnt - 1;\n\n\ngenerate\nif(nCK_PER_CLK == 4) begin:back_to_back_reads_4_1\n // 4 back-to-back reads with gaps for \n // read data_offset calibration (rdlvl stage 2) \n always @(posedge clk)\n if (rst || (init_state_r == INIT_RDLVL_STG2_READ_WAIT))\n num_reads <= #TCQ 3'b000;\n else if ((num_reads > 3'b000) && ~(phy_ctl_full || phy_cmd_full))\n num_reads <= #TCQ num_reads - 1;\n else if ((init_state_r == INIT_RDLVL_STG2_READ) || phy_ctl_full || \n phy_cmd_full && new_burst_r)\n num_reads <= #TCQ 3'b011;\nend else if(nCK_PER_CLK == 2) begin: back_to_back_reads_2_1 \n // 4 back-to-back reads with gaps for \n // read data_offset calibration (rdlvl stage 2) \n always @(posedge clk)\n if (rst || (init_state_r == INIT_RDLVL_STG2_READ_WAIT))\n num_reads <= #TCQ 3'b000;\n else if ((num_reads > 3'b000) && ~(phy_ctl_full || phy_cmd_full))\n num_reads <= #TCQ num_reads - 1;\n else if ((init_state_r == INIT_RDLVL_STG2_READ) || phy_ctl_full || \n phy_cmd_full && new_burst_r)\n num_reads <= #TCQ 3'b111;\nend\nendgenerate\n \n // back-to-back reads during write calibration\n always @(posedge clk)\n if (rst ||(init_state_r == INIT_WRCAL_READ_WAIT))\n wrcal_reads <= #TCQ 2'b00;\n else if ((wrcal_reads > 2'b00) && ~(phy_ctl_full || phy_cmd_full))\n wrcal_reads <= #TCQ wrcal_reads - 1;\n else if ((init_state_r == INIT_WRCAL_MULT_READS) || phy_ctl_full || \n phy_cmd_full && new_burst_r)\n wrcal_reads <= #TCQ 'd255;\n\n // determine how often to issue row command during read leveling writes\n // and reads\n always @(posedge clk)\n if (rdlvl_wr_rd) begin\n // 2:1 mode - every other command issued is a data command\n // 4:1 mode - every command issued is a data command\n if (nCK_PER_CLK == 2) begin\n if (!phy_ctl_full)\n new_burst_r <= #TCQ ~new_burst_r;\n end else\n new_burst_r <= #TCQ 1'b1;\n end else\n new_burst_r <= #TCQ 1'b1;\n \n // indicate when a write is occurring. PHY_WRDATA_EN must be asserted\n // simultaneous with the corresponding command/address for CWL = 5,6\n always @(posedge clk) begin\n rdlvl_wr_r <= #TCQ rdlvl_wr;\n calib_wrdata_en <= #TCQ phy_wrdata_en;\n end \n\n always @(posedge clk) begin\n if (rst || wrcal_done)\n extend_cal_pat <= #TCQ 1'b0;\n else if (temp_lmr_done && (PRE_REV3ES == \"ON\")) \n extend_cal_pat <= #TCQ 1'b1;\n end\n\n\n generate\n if ((nCK_PER_CLK == 4) || (BURST_MODE == \"4\")) begin: wrdqen_div4\n // Write data enable asserted for one DIV4 clock cycle\n // Only BL8 supported with DIV4. DDR2 BL4 will use DIV2.\n always @(*) begin\n if (~phy_data_full && ((init_state_r == INIT_RDLVL_STG1_WRITE) ||\n (init_state_r == INIT_OCLKDELAY_WRITE) ||\n (init_state_r == INIT_OCAL_CENTER_WRITE) || \n (init_state_r == INIT_WRCAL_WRITE)))\n phy_wrdata_en = 1'b1;\n else\n phy_wrdata_en = 1'b0;\n end\n end else begin: wrdqen_div2 // block: wrdqen_div4\n always @(*)\n if((rdlvl_wr & ~phy_ctl_full & new_burst_r & ~phy_data_full) \n | phy_wrdata_en_r1)\n phy_wrdata_en = 1'b1;\n else\n phy_wrdata_en = 1'b0;\n\n always @(posedge clk)\n phy_wrdata_en_r1 <= #TCQ rdlvl_wr & ~phy_ctl_full & new_burst_r\n & ~phy_data_full;\n \n always @(posedge clk) begin\n if (!phy_wrdata_en & first_rdlvl_pat_r)\n wrdata_pat_cnt <= #TCQ 2'b00;\n else if (wrdata_pat_cnt == 2'b11)\n wrdata_pat_cnt <= #TCQ 2'b10;\n else\n wrdata_pat_cnt <= #TCQ wrdata_pat_cnt + 1;\n end\n \n always @(posedge clk) begin\n if (!phy_wrdata_en & first_wrcal_pat_r)\n wrcal_pat_cnt <= #TCQ 2'b00;\n else if (extend_cal_pat && (wrcal_pat_cnt == 2'b01))\n wrcal_pat_cnt <= #TCQ 2'b00;\n else if (wrcal_pat_cnt == 2'b11)\n wrcal_pat_cnt <= #TCQ 2'b10;\n else\n wrcal_pat_cnt <= #TCQ wrcal_pat_cnt + 1;\n end\n \n end\n endgenerate\n\n \n // indicate when a write is occurring. PHY_RDDATA_EN must be asserted\n // simultaneous with the corresponding command/address. PHY_RDDATA_EN\n // is used during read-leveling to determine read latency\n assign phy_rddata_en = ~phy_if_empty;\n\n // Read data valid generation for MC and User Interface after calibration is\n // complete \n assign phy_rddata_valid = init_complete_r1_timing ? phy_rddata_en : 1'b0;\n\n //***************************************************************************\n // Generate training data written at start of each read-leveling stage\n // For every stage of read leveling, 8 words are written into memory\n // The format is as follows (shown as {rise,fall}):\n // Stage 1: 0xF, 0x0, 0xF, 0x0, 0xF, 0x0, 0xF, 0x0\n // Stage 2: 0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6\n //***************************************************************************\n\n\n always @(posedge clk)\n if ((init_state_r == INIT_IDLE) ||\n (init_state_r == INIT_RDLVL_STG1_WRITE))\n cnt_init_data_r <= #TCQ 2'b00;\n else if (phy_wrdata_en)\n cnt_init_data_r <= #TCQ cnt_init_data_r + 1;\n else if (init_state_r == INIT_WRCAL_WRITE)\n cnt_init_data_r <= #TCQ 2'b10; \n\n\n // write different sequence for very\n // first write to memory only. Used to help us differentiate\n // if the writes are \"early\" or \"on-time\" during read leveling\n always @(posedge clk)\n if (rst || rdlvl_stg1_rank_done)\n first_rdlvl_pat_r <= #TCQ 1'b1;\n else if (phy_wrdata_en && (init_state_r == INIT_RDLVL_STG1_WRITE))\n first_rdlvl_pat_r <= #TCQ 1'b0;\n \n \n always @(posedge clk)\n if (rst || wrcal_resume ||\n (init_state_r == INIT_WRCAL_ACT_WAIT))\n first_wrcal_pat_r <= #TCQ 1'b1;\n else if (phy_wrdata_en && (init_state_r == INIT_WRCAL_WRITE))\n first_wrcal_pat_r <= #TCQ 1'b0;\n\ngenerate\n if ((CLK_PERIOD/nCK_PER_CLK > 2500) && (nCK_PER_CLK == 2)) begin: wrdq_div2_2to1_rdlvl_first\n \n always @(posedge clk)\n if (~oclkdelay_calib_done)\n phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}},\n {DQ_WIDTH/4{4'h0}},\n {DQ_WIDTH/4{4'hF}},\n {DQ_WIDTH/4{4'h0}}};\n else if (!rdlvl_stg1_done) begin\n // The 16 words for stage 1 write data in 2:1 mode is written \n // over 4 consecutive controller clock cycles. Note that write \n // data follows phy_wrdata_en by one clock cycle\n case (wrdata_pat_cnt)\n 2'b00: begin\n phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}},\n {DQ_WIDTH/4{4'h7}},\n {DQ_WIDTH/4{4'h3}},\n {DQ_WIDTH/4{4'h9}}};\n end\n \n 2'b01: begin\n phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},\n {DQ_WIDTH/4{4'h2}},\n {DQ_WIDTH/4{4'h9}},\n {DQ_WIDTH/4{4'hC}}};\n end\n \n 2'b10: begin\n phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}},\n {DQ_WIDTH/4{4'h7}},\n {DQ_WIDTH/4{4'h1}},\n {DQ_WIDTH/4{4'hB}}};\n end\n \n 2'b11: begin\n phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},\n {DQ_WIDTH/4{4'h2}},\n {DQ_WIDTH/4{4'h9}},\n {DQ_WIDTH/4{4'hC}}};\n end\n endcase\n end else if (!prbs_rdlvl_done && ~phy_data_full) begin\n phy_wrdata <= #TCQ prbs_o;\n // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in\n // prbs_o being concatenated 8 times resulting in DQ_WIDTH\n /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[4*8-1:3*8]}},\n {DQ_WIDTH/8{prbs_o[3*8-1:2*8]}},\n {DQ_WIDTH/8{prbs_o[2*8-1:8]}},\n {DQ_WIDTH/8{prbs_o[8-1:0]}}};*/\n end else if (!wrcal_done) begin\n case (wrcal_pat_cnt)\n 2'b00: begin\n phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h5}},\n {DQ_WIDTH/4{4'hA}},\n {DQ_WIDTH/4{4'h0}},\n {DQ_WIDTH/4{4'hF}}};\n end\n 2'b01: begin\n phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},\n {DQ_WIDTH/4{4'h9}},\n {DQ_WIDTH/4{4'hA}},\n {DQ_WIDTH/4{4'h5}}};\n end\n 2'b10: begin\n phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},\n {DQ_WIDTH/4{4'hE}},\n {DQ_WIDTH/4{4'h1}},\n {DQ_WIDTH/4{4'hB}}};\n end\n 2'b11: begin\n phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}},\n {DQ_WIDTH/4{4'hD}},\n {DQ_WIDTH/4{4'hE}},\n {DQ_WIDTH/4{4'h4}}};\n end\n endcase\n end\n \n end else if ((CLK_PERIOD/nCK_PER_CLK > 2500) && (nCK_PER_CLK == 4)) begin: wrdq_div2_4to1_rdlvl_first\n \n always @(posedge clk)\n if (~oclkdelay_calib_done)\n phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}},\n {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}},\n {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}},\n {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}};\n else if (!rdlvl_stg1_done && ~phy_data_full)\n // write different sequence for very\n // first write to memory only. Used to help us differentiate\n // if the writes are \"early\" or \"on-time\" during read leveling\n if (first_rdlvl_pat_r)\n phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}},\n {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}},\n {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}},\n {DQ_WIDTH/4{4'h3}},{DQ_WIDTH/4{4'h9}}};\n else\n // For all others, change the first two words written in order\n // to differentiate the \"early write\" and \"on-time write\"\n // readback patterns during read leveling\n phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}},\n {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}},\n {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}},\n {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}};\n else if (~(prbs_rdlvl_done || prbs_last_byte_done_r) && ~phy_data_full)\n phy_wrdata <= #TCQ prbs_o;\n // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in\n // prbs_o being concatenated 8 times resulting in DQ_WIDTH\n /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[8*8-1:7*8]}},{DQ_WIDTH/8{prbs_o[7*8-1:6*8]}},\n {DQ_WIDTH/8{prbs_o[6*8-1:5*8]}},{DQ_WIDTH/8{prbs_o[5*8-1:4*8]}},\n {DQ_WIDTH/8{prbs_o[4*8-1:3*8]}},{DQ_WIDTH/8{prbs_o[3*8-1:2*8]}},\n {DQ_WIDTH/8{prbs_o[2*8-1:8]}},{DQ_WIDTH/8{prbs_o[8-1:0]}}};*/ \n else if (!wrcal_done)\n if (first_wrcal_pat_r)\n phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}},\n {DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}},\n {DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}},\n {DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}};\n else\n phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}},{DQ_WIDTH/4{4'hD}},\n {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h4}},\n {DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'hE}},\n {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}};\n \n \n end else if (nCK_PER_CLK == 4) begin: wrdq_div1_4to1_wrcal_first\n \n always @(posedge clk)\n if ((~oclkdelay_calib_done) && (DRAM_TYPE == \"DDR3\"))\n phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}},\n {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}},\n {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}},\n {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}};\n else if ((!wrcal_done)&& (DRAM_TYPE == \"DDR3\")) begin\n if (extend_cal_pat)\n phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}},\n {DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}},\n {DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}},\n {DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}};\n else if (first_wrcal_pat_r)\n phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}},\n {DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}},\n {DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}},\n {DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}};\n else\n phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}},{DQ_WIDTH/4{4'hD}},\n {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h4}},\n {DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'hE}},\n {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}};\n end else if (!rdlvl_stg1_done && ~phy_data_full) begin\n // write different sequence for very\n // first write to memory only. Used to help us differentiate\n // if the writes are \"early\" or \"on-time\" during read leveling\n if (first_rdlvl_pat_r)\n phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}},\n {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}},\n {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}},\n {DQ_WIDTH/4{4'h3}},{DQ_WIDTH/4{4'h9}}};\n else\n // For all others, change the first two words written in order\n // to differentiate the \"early write\" and \"on-time write\"\n // readback patterns during read leveling\n phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}},\n {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}},\n {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}},\n {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}}; \n end else if (!prbs_rdlvl_done && ~phy_data_full)\n phy_wrdata <= #TCQ prbs_o;\n // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in\n // prbs_o being concatenated 8 times resulting in DQ_WIDTH\n /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[8*8-1:7*8]}},{DQ_WIDTH/8{prbs_o[7*8-1:6*8]}},\n {DQ_WIDTH/8{prbs_o[6*8-1:5*8]}},{DQ_WIDTH/8{prbs_o[5*8-1:4*8]}},\n {DQ_WIDTH/8{prbs_o[4*8-1:3*8]}},{DQ_WIDTH/8{prbs_o[3*8-1:2*8]}},\n {DQ_WIDTH/8{prbs_o[2*8-1:8]}},{DQ_WIDTH/8{prbs_o[8-1:0]}}};*/ \n else if (!complex_oclkdelay_calib_done && ~phy_data_full) \n phy_wrdata <= #TCQ prbs_o;\n end else begin: wrdq_div1_2to1_wrcal_first\n \n always @(posedge clk)\n if ((~oclkdelay_calib_done)&& (DRAM_TYPE == \"DDR3\"))\n phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}},\n {DQ_WIDTH/4{4'h0}},\n {DQ_WIDTH/4{4'hF}},\n {DQ_WIDTH/4{4'h0}}};\n else if ((!wrcal_done) && (DRAM_TYPE == \"DDR3\"))begin\n case (wrcal_pat_cnt)\n 2'b00: begin\n phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h5}},\n {DQ_WIDTH/4{4'hA}},\n {DQ_WIDTH/4{4'h0}},\n {DQ_WIDTH/4{4'hF}}};\n end\n 2'b01: begin\n phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},\n {DQ_WIDTH/4{4'h9}},\n {DQ_WIDTH/4{4'hA}},\n {DQ_WIDTH/4{4'h5}}};\n end\n 2'b10: begin\n phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},\n {DQ_WIDTH/4{4'hE}},\n {DQ_WIDTH/4{4'h1}},\n {DQ_WIDTH/4{4'hB}}};\n end\n 2'b11: begin\n phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}},\n {DQ_WIDTH/4{4'hD}},\n {DQ_WIDTH/4{4'hE}},\n {DQ_WIDTH/4{4'h4}}};\n end\n endcase\n end else if (!rdlvl_stg1_done) begin\n // The 16 words for stage 1 write data in 2:1 mode is written \n // over 4 consecutive controller clock cycles. Note that write \n // data follows phy_wrdata_en by one clock cycle\n case (wrdata_pat_cnt)\n 2'b00: begin\n phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}},\n {DQ_WIDTH/4{4'h7}},\n {DQ_WIDTH/4{4'h3}},\n {DQ_WIDTH/4{4'h9}}};\n end\n \n 2'b01: begin\n phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},\n {DQ_WIDTH/4{4'h2}},\n {DQ_WIDTH/4{4'h9}},\n {DQ_WIDTH/4{4'hC}}};\n end\n \n 2'b10: begin\n phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}},\n {DQ_WIDTH/4{4'h7}},\n {DQ_WIDTH/4{4'h1}},\n {DQ_WIDTH/4{4'hB}}};\n end\n \n 2'b11: begin\n phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},\n {DQ_WIDTH/4{4'h2}},\n {DQ_WIDTH/4{4'h9}},\n {DQ_WIDTH/4{4'hC}}};\n end\n endcase\n end else if (!prbs_rdlvl_done && ~phy_data_full) begin\n phy_wrdata <= #TCQ prbs_o;\n // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in\n // prbs_o being concatenated 8 times resulting in DQ_WIDTH\n /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[4*8-1:3*8]}},\n {DQ_WIDTH/8{prbs_o[3*8-1:2*8]}},\n {DQ_WIDTH/8{prbs_o[2*8-1:8]}},\n {DQ_WIDTH/8{prbs_o[8-1:0]}}};*/\n end else if (!complex_oclkdelay_calib_done && ~phy_data_full) begin\n phy_wrdata <= #TCQ prbs_o;\n end\n\n end\nendgenerate\n \n //***************************************************************************\n // Memory control/address\n //***************************************************************************\n\n\n // Phases [2] and [3] are always deasserted for 4:1 mode\n generate\n if (nCK_PER_CLK == 4) begin: gen_div4_ca_tieoff\n always @(posedge clk) begin\n phy_ras_n[3:2] <= #TCQ 3'b11;\n phy_cas_n[3:2] <= #TCQ 3'b11;\n phy_we_n[3:2] <= #TCQ 3'b11;\n end\n end\n endgenerate\n \n // Assert RAS when: (1) Loading MRS, (2) Activating Row, (3) Precharging\n // (4) auto refresh\n // verilint STARC-2.7.3.3b off\n generate \n if (!(CWL_M % 2)) begin: even_cwl\n always @(posedge clk) begin\n if ((init_state_r == INIT_LOAD_MR) ||\n (init_state_r == INIT_MPR_RDEN) ||\n (init_state_r == INIT_MPR_DISABLE) ||\n (init_state_r == INIT_REG_WRITE) ||\n (init_state_r == INIT_WRLVL_START) ||\n (init_state_r == INIT_WRLVL_LOAD_MR) ||\n (init_state_r == INIT_WRLVL_LOAD_MR2) ||\n (init_state_r == INIT_RDLVL_ACT) ||\n (init_state_r == INIT_WRCAL_ACT) ||\n (init_state_r == INIT_OCLKDELAY_ACT) ||\n (init_state_r == INIT_OCAL_COMPLEX_ACT) || \n (init_state_r == INIT_OCAL_CENTER_ACT) || \n (init_state_r == INIT_PRECHARGE) ||\n (init_state_r == INIT_DDR2_PRECHARGE) ||\n (init_state_r == INIT_REFRESH) ||\n (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||\n (init_state_r == INIT_RDLVL_COMPLEX_ACT))begin\n phy_ras_n[0] <= #TCQ 1'b0;\n phy_ras_n[1] <= #TCQ 1'b1;\n end else begin\n phy_ras_n[0] <= #TCQ 1'b1;\n phy_ras_n[1] <= #TCQ 1'b1;\n end\n end\n \n // Assert CAS when: (1) Loading MRS, (2) Issuing Read/Write command\n // (3) auto refresh\n always @(posedge clk) begin\n if ((init_state_r == INIT_LOAD_MR) ||\n (init_state_r == INIT_MPR_RDEN) ||\n (init_state_r == INIT_MPR_DISABLE) ||\n (init_state_r == INIT_REG_WRITE) ||\n (init_state_r == INIT_WRLVL_START) ||\n (init_state_r == INIT_WRLVL_LOAD_MR) ||\n (init_state_r == INIT_WRLVL_LOAD_MR2) ||\n (init_state_r == INIT_REFRESH) ||\n (rdlvl_wr_rd && new_burst_r))begin\n phy_cas_n[0] <= #TCQ 1'b0;\n phy_cas_n[1] <= #TCQ 1'b1;\n end else begin\n phy_cas_n[0] <= #TCQ 1'b1;\n phy_cas_n[1] <= #TCQ 1'b1;\n end\n end\n // Assert WE when: (1) Loading MRS, (2) Issuing Write command (only\n // occur during read leveling), (3) Issuing ZQ Long Calib command,\n // (4) Precharge\n always @(posedge clk) begin\n if ((init_state_r == INIT_LOAD_MR) ||\n (init_state_r == INIT_MPR_RDEN) ||\n (init_state_r == INIT_MPR_DISABLE) ||\n (init_state_r == INIT_REG_WRITE) ||\n (init_state_r == INIT_ZQCL) ||\n (init_state_r == INIT_WRLVL_START) ||\n (init_state_r == INIT_WRLVL_LOAD_MR) ||\n (init_state_r == INIT_WRLVL_LOAD_MR2) ||\n (init_state_r == INIT_PRECHARGE) ||\n (init_state_r == INIT_DDR2_PRECHARGE)||\n (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||\n (rdlvl_wr && new_burst_r))begin\n phy_we_n[0] <= #TCQ 1'b0;\n phy_we_n[1] <= #TCQ 1'b1;\n end else begin\n phy_we_n[0] <= #TCQ 1'b1;\n phy_we_n[1] <= #TCQ 1'b1;\n end\n end\n end else begin: odd_cwl\n always @(posedge clk) begin\n if ((init_state_r == INIT_LOAD_MR) ||\n (init_state_r == INIT_MPR_RDEN) ||\n (init_state_r == INIT_MPR_DISABLE) ||\n (init_state_r == INIT_REG_WRITE) ||\n (init_state_r == INIT_WRLVL_START) ||\n (init_state_r == INIT_WRLVL_LOAD_MR) ||\n (init_state_r == INIT_WRLVL_LOAD_MR2) ||\n (init_state_r == INIT_RDLVL_ACT) ||\n (init_state_r == INIT_WRCAL_ACT) ||\n (init_state_r == INIT_OCLKDELAY_ACT) ||\n (init_state_r == INIT_OCAL_COMPLEX_ACT) ||\n (init_state_r == INIT_OCAL_CENTER_ACT) || \n (init_state_r == INIT_PRECHARGE) ||\n (init_state_r == INIT_DDR2_PRECHARGE) ||\n (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||\n (init_state_r == INIT_RDLVL_COMPLEX_ACT) ||\n (init_state_r == INIT_REFRESH))begin\n phy_ras_n[0] <= #TCQ 1'b1;\n phy_ras_n[1] <= #TCQ 1'b0;\n end else begin\n phy_ras_n[0] <= #TCQ 1'b1;\n phy_ras_n[1] <= #TCQ 1'b1;\n end\n end\n // Assert CAS when: (1) Loading MRS, (2) Issuing Read/Write command\n // (3) auto refresh\n always @(posedge clk) begin\n if ((init_state_r == INIT_LOAD_MR) ||\n (init_state_r == INIT_MPR_RDEN) ||\n (init_state_r == INIT_MPR_DISABLE) ||\n (init_state_r == INIT_REG_WRITE) ||\n (init_state_r == INIT_WRLVL_START) ||\n (init_state_r == INIT_WRLVL_LOAD_MR) ||\n (init_state_r == INIT_WRLVL_LOAD_MR2) ||\n (init_state_r == INIT_REFRESH) ||\n (rdlvl_wr_rd && new_burst_r))begin\n phy_cas_n[0] <= #TCQ 1'b1;\n phy_cas_n[1] <= #TCQ 1'b0;\n end else begin\n phy_cas_n[0] <= #TCQ 1'b1;\n phy_cas_n[1] <= #TCQ 1'b1;\n end\n end\n // Assert WE when: (1) Loading MRS, (2) Issuing Write command (only\n // occur during read leveling), (3) Issuing ZQ Long Calib command,\n // (4) Precharge\n always @(posedge clk) begin\n if ((init_state_r == INIT_LOAD_MR) ||\n (init_state_r == INIT_MPR_RDEN) ||\n (init_state_r == INIT_MPR_DISABLE) ||\n (init_state_r == INIT_REG_WRITE) ||\n (init_state_r == INIT_ZQCL) ||\n (init_state_r == INIT_WRLVL_START) ||\n (init_state_r == INIT_WRLVL_LOAD_MR) ||\n (init_state_r == INIT_WRLVL_LOAD_MR2) ||\n (init_state_r == INIT_PRECHARGE) ||\n (init_state_r == INIT_DDR2_PRECHARGE)||\n (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||\n (rdlvl_wr && new_burst_r))begin\n phy_we_n[0] <= #TCQ 1'b1;\n phy_we_n[1] <= #TCQ 1'b0;\n end else begin\n phy_we_n[0] <= #TCQ 1'b1;\n phy_we_n[1] <= #TCQ 1'b1;\n end\n end\n end\n endgenerate\n// verilint STARC-2.7.3.3b on\n\n\n // Assign calib_cmd for the command field in PHY_Ctl_Word\n always @(posedge clk) begin\n if (wr_level_dqs_asrt) begin\n // Request to toggle DQS during write leveling\n calib_cmd <= #TCQ 3'b001;\n if (CWL_M % 2) begin // odd write latency\n calib_data_offset_0 <= #TCQ CWL_M + 3;\n calib_data_offset_1 <= #TCQ CWL_M + 3;\n calib_data_offset_2 <= #TCQ CWL_M + 3;\n calib_cas_slot <= #TCQ 2'b01;\n end else begin // even write latency\n calib_data_offset_0 <= #TCQ CWL_M + 2;\n calib_data_offset_1 <= #TCQ CWL_M + 2;\n calib_data_offset_2 <= #TCQ CWL_M + 2;\n calib_cas_slot <= #TCQ 2'b00;\n end\n end else if (rdlvl_wr && new_burst_r) begin\n // Write Command\n calib_cmd <= #TCQ 3'b001;\n if (CWL_M % 2) begin // odd write latency\n calib_data_offset_0 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1;\n calib_data_offset_1 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1;\n calib_data_offset_2 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1;\n calib_cas_slot <= #TCQ 2'b01;\n end else begin // even write latency\n calib_data_offset_0 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ;\n calib_data_offset_1 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ;\n calib_data_offset_2 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ;\n calib_cas_slot <= #TCQ 2'b00;\n end\n end else if (rdlvl_rd && new_burst_r) begin\n // Read Command\n calib_cmd <= #TCQ 3'b011;\n if (CWL_M % 2)\n calib_cas_slot <= #TCQ 2'b01;\n else\n calib_cas_slot <= #TCQ 2'b00;\n if (~pi_calib_done_r1) begin\n calib_data_offset_0 <= #TCQ 6'd0;\n calib_data_offset_1 <= #TCQ 6'd0;\n calib_data_offset_2 <= #TCQ 6'd0;\n end else if (~pi_dqs_found_done_r1) begin\n calib_data_offset_0 <= #TCQ rd_data_offset_0;\n calib_data_offset_1 <= #TCQ rd_data_offset_1;\n calib_data_offset_2 <= #TCQ rd_data_offset_2;\n end else begin\n calib_data_offset_0 <= #TCQ rd_data_offset_ranks_0[6*chip_cnt_r+:6];\n calib_data_offset_1 <= #TCQ rd_data_offset_ranks_1[6*chip_cnt_r+:6];\n calib_data_offset_2 <= #TCQ rd_data_offset_ranks_2[6*chip_cnt_r+:6];\n end\n end else begin\n // Non-Data Commands like NOP, MRS, ZQ Long Cal, Precharge,\n // Active, Refresh\n calib_cmd <= #TCQ 3'b100;\n calib_data_offset_0 <= #TCQ 6'd0;\n calib_data_offset_1 <= #TCQ 6'd0;\n calib_data_offset_2 <= #TCQ 6'd0;\n if (CWL_M % 2)\n calib_cas_slot <= #TCQ 2'b01;\n else\n calib_cas_slot <= #TCQ 2'b00;\n end\n end\n \n // Write Enable to PHY_Control FIFO always asserted\n // No danger of this FIFO being Full with 4:1 sync clock ratio\n // This is also the write enable to the command OUT_FIFO\n always @(posedge clk) begin\n if (rst) begin\n calib_ctl_wren <= #TCQ 1'b0;\n calib_cmd_wren <= #TCQ 1'b0;\n calib_seq <= #TCQ 2'b00;\n end else if (cnt_pwron_cke_done_r && phy_ctl_ready\n && ~(phy_ctl_full || phy_cmd_full )) begin\n calib_ctl_wren <= #TCQ 1'b1;\n calib_cmd_wren <= #TCQ 1'b1;\n calib_seq <= #TCQ calib_seq + 1;\n end else begin\n calib_ctl_wren <= #TCQ 1'b0;\n calib_cmd_wren <= #TCQ 1'b0;\n calib_seq <= #TCQ calib_seq;\n end\n end\n\n generate\n genvar rnk_i;\n for (rnk_i = 0; rnk_i < 4; rnk_i = rnk_i + 1) begin: gen_rnk\n always @(posedge clk) begin\n if (rst) begin\n mr2_r[rnk_i] <= #TCQ 2'b00;\n mr1_r[rnk_i] <= #TCQ 3'b000;\n end else begin\n mr2_r[rnk_i] <= #TCQ tmp_mr2_r[rnk_i];\n mr1_r[rnk_i] <= #TCQ tmp_mr1_r[rnk_i];\n end\n end\n end\n endgenerate\n\n // ODT assignment based on slot config and slot present\n // For single slot systems slot_1_present input will be ignored\n // Assuming component interfaces to be single slot systems\n generate\n if (nSLOTS == 1) begin: gen_single_slot_odt\n always @(posedge clk) begin\n if (rst) begin\n tmp_mr2_r[1] <= #TCQ 2'b00;\n tmp_mr2_r[2] <= #TCQ 2'b00;\n tmp_mr2_r[3] <= #TCQ 2'b00;\n tmp_mr1_r[1] <= #TCQ 3'b000;\n tmp_mr1_r[2] <= #TCQ 3'b000;\n tmp_mr1_r[3] <= #TCQ 3'b000;\n phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}};\n phy_tmp_odt_r <= #TCQ 4'b0000;\n phy_tmp_odt_r1 <= #TCQ phy_tmp_odt_r;\n end else begin \n case ({slot_0_present[0],slot_0_present[1],\n slot_0_present[2],slot_0_present[3]})\n // Single slot configuration with quad rank\n // Assuming same behavior as single slot dual rank for now\n // DDR2 does not have quad rank parts \n 4'b1111: begin \n if ((RTT_WR == \"OFF\") || \n ((WRLVL==\"ON\") && ~wrlvl_done &&\n (wrlvl_rank_cntr==3'd0))) begin\n //Rank0 Dynamic ODT disabled\n tmp_mr2_r[0] <= #TCQ 2'b00;\n //Rank0 RTT_NOM\n tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == \"40\") ? 3'b011 :\n (RTT_NOM_int == \"60\") ? 3'b001 :\n (RTT_NOM_int == \"120\") ? 3'b010 :\n 3'b000;\n end else begin\n //Rank0 Dynamic ODT defaults to 120 ohms\n tmp_mr2_r[0] <= #TCQ (RTT_WR == \"60\") ? 2'b01 :\n 2'b10;\n //Rank0 RTT_NOM after write leveling completes\n tmp_mr1_r[0] <= #TCQ 3'b000;\n end\n phy_tmp_odt_r <= #TCQ 4'b0001;\n // Chip Select assignments\n phy_tmp_cs1_r[((chip_cnt_r*nCS_PER_RANK)\n ) +: nCS_PER_RANK] <= #TCQ 'b0;\n end \n \n // Single slot configuration with single rank\n 4'b1000: begin \n phy_tmp_odt_r <= #TCQ 4'b0001;\n if ((REG_CTRL == \"ON\") && (nCS_PER_RANK > 1)) begin\n phy_tmp_cs1_r[chip_cnt_r] <= #TCQ 1'b0;\n end else begin\n phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};\n end\n if ((RTT_WR == \"OFF\") || \n ((WRLVL==\"ON\") && ~wrlvl_done && \n ((cnt_init_mr_r == 2'd0) || (USE_ODT_PORT == 1)))) begin\n //Rank0 Dynamic ODT disabled\n tmp_mr2_r[0] <= #TCQ 2'b00;\n //Rank0 RTT_NOM\n tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == \"40\") ? 3'b011 :\n (RTT_NOM_int == \"60\") ? 3'b001 :\n (RTT_NOM_int == \"120\") ? 3'b010 :\n 3'b000;\n end else begin\n //Rank0 Dynamic ODT defaults to 120 ohms\n tmp_mr2_r[0] <= #TCQ (RTT_WR == \"60\") ? 2'b01 :\n 2'b10;\n //Rank0 RTT_NOM after write leveling completes\n tmp_mr1_r[0] <= #TCQ 3'b000;\n end\n end \n \n // Single slot configuration with dual rank\n 4'b1100: begin\n phy_tmp_odt_r <= #TCQ 4'b0001;\n // Chip Select assignments\n \n phy_tmp_cs1_r[((chip_cnt_r*nCS_PER_RANK)\n ) +: nCS_PER_RANK] <= #TCQ 'b0;\n if ((RTT_WR == \"OFF\") || \n ((WRLVL==\"ON\") && ~wrlvl_done &&\n (wrlvl_rank_cntr==3'd0))) begin\n //Rank0 Dynamic ODT disabled\n tmp_mr2_r[0] <= #TCQ 2'b00;\n //Rank0 Rtt_NOM\n tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == \"40\") ? 3'b011 :\n (RTT_NOM_int == \"60\") ? 3'b001 :\n (RTT_NOM_int == \"120\") ? 3'b010 :\n 3'b000;\n end else begin\n //Rank0 Dynamic ODT defaults to 120 ohms\n tmp_mr2_r[0] <= #TCQ (RTT_WR == \"60\") ? 2'b01 :\n 2'b10;\n //Rank0 Rtt_NOM after write leveling completes\n tmp_mr1_r[0] <= #TCQ 3'b000;\n end\n end \n \n default: begin \n phy_tmp_odt_r <= #TCQ 4'b0001;\n phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};\n if ((RTT_WR == \"OFF\") || \n ((WRLVL==\"ON\") && ~wrlvl_done)) begin\n //Rank0 Dynamic ODT disabled\n tmp_mr2_r[0] <= #TCQ 2'b00;\n //Rank0 Rtt_NOM\n tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == \"40\") ? 3'b011 :\n (RTT_NOM_int == \"60\") ? 3'b001 :\n (RTT_NOM_int == \"120\") ? 3'b010 :\n 3'b000;\n end else begin\n //Rank0 Dynamic ODT defaults to 120 ohms\n tmp_mr2_r[0] <= #TCQ (RTT_WR == \"60\") ? 2'b01 :\n 2'b10;\n //Rank0 Rtt_NOM after write leveling completes\n tmp_mr1_r[0] <= #TCQ 3'b000;\n end\n end \n endcase\n end\n end\n end else if (nSLOTS == 2) begin: gen_dual_slot_odt\n always @ (posedge clk) begin\n if (rst) begin\n tmp_mr2_r[1] <= #TCQ 2'b00;\n tmp_mr2_r[2] <= #TCQ 2'b00;\n tmp_mr2_r[3] <= #TCQ 2'b00;\n tmp_mr1_r[1] <= #TCQ 3'b000;\n tmp_mr1_r[2] <= #TCQ 3'b000;\n tmp_mr1_r[3] <= #TCQ 3'b000;\n phy_tmp_odt_r <= #TCQ 4'b0000;\n phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}};\n phy_tmp_odt_r1 <= #TCQ phy_tmp_odt_r;\n end else begin \n case ({slot_0_present[0],slot_0_present[1],\n slot_1_present[0],slot_1_present[1]}) \n // Two slot configuration, one slot present, single rank\n 4'b10_00: begin\n if (//wrlvl_odt ||\n (init_state_r == INIT_RDLVL_STG1_WRITE) ||\n (init_state_r == INIT_WRCAL_WRITE) ||\n (init_state_r == INIT_OCAL_CENTER_WRITE) || \n (init_state_r == INIT_OCLKDELAY_WRITE)) begin\n // odt turned on only during write \n phy_tmp_odt_r <= #TCQ 4'b0001;\n end\n phy_tmp_cs1_r <= #TCQ {nCS_PER_RANK{1'b0}};\n if ((RTT_WR == \"OFF\") || \n ((WRLVL==\"ON\") && ~wrlvl_done)) begin\n //Rank0 Dynamic ODT disabled\n tmp_mr2_r[0] <= #TCQ 2'b00;\n //Rank0 Rtt_NOM\n tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == \"40\") ? 3'b011 :\n (RTT_NOM_int == \"60\") ? 3'b001 :\n (RTT_NOM_int == \"120\") ? 3'b010 :\n 3'b000;\n end else begin\n //Rank0 Dynamic ODT defaults to 120 ohms\n tmp_mr2_r[0] <= #TCQ (RTT_WR == \"60\") ? 2'b01 :\n 2'b10;\n //Rank0 Rtt_NOM after write leveling completes\n tmp_mr1_r[0] <= #TCQ 3'b000;\n end\n end\n 4'b00_10: begin\n \n //Rank1 ODT enabled\n if (//wrlvl_odt ||\n (init_state_r == INIT_RDLVL_STG1_WRITE) || \n (init_state_r == INIT_WRCAL_WRITE) ||\n (init_state_r == INIT_OCAL_CENTER_WRITE) || \n (init_state_r == INIT_OCLKDELAY_WRITE)) begin\n // odt turned on only during write\n phy_tmp_odt_r <= #TCQ 4'b0001;\n end\n phy_tmp_cs1_r <= #TCQ {nCS_PER_RANK{1'b0}};\n if ((RTT_WR == \"OFF\") || \n ((WRLVL==\"ON\") && ~wrlvl_done)) begin\n //Rank1 Dynamic ODT disabled\n tmp_mr2_r[0] <= #TCQ 2'b00;\n //Rank1 Rtt_NOM defaults to 120 ohms\n tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == \"40\") ? 3'b011 :\n (RTT_NOM_int == \"60\") ? 3'b001 :\n (RTT_NOM_int == \"120\") ? 3'b010 :\n 3'b000;\n end else begin\n //Rank1 Dynamic ODT defaults to 120 ohms\n tmp_mr2_r[0] <= #TCQ (RTT_WR == \"60\") ? 2'b01 :\n 2'b10;\n //Rank1 Rtt_NOM after write leveling completes\n tmp_mr1_r[0] <= #TCQ 3'b000;\n end\n end\n // Two slot configuration, one slot present, dual rank\n 4'b00_11: begin\n if (//wrlvl_odt ||\n (init_state_r == INIT_RDLVL_STG1_WRITE) || \n (init_state_r == INIT_WRCAL_WRITE) ||\n (init_state_r == INIT_OCAL_CENTER_WRITE) || \n (init_state_r == INIT_OCLKDELAY_WRITE)) begin\n // odt turned on only during write\n phy_tmp_odt_r \n <= #TCQ 4'b0001;\n end\n \n // Chip Select assignments\n phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] \n <= #TCQ {nCS_PER_RANK{1'b0}};\n \n if ((RTT_WR == \"OFF\") ||\n ((WRLVL==\"ON\") && ~wrlvl_done &&\n (wrlvl_rank_cntr==3'd0))) begin\n //Rank0 Dynamic ODT disabled\n tmp_mr2_r[0] <= #TCQ 2'b00;\n //Rank0 Rtt_NOM\n tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == \"40\") ? 3'b011 :\n (RTT_NOM_int == \"60\") ? 3'b001 :\n (RTT_NOM_int == \"120\") ? 3'b010 :\n 3'b000;\n end else begin\n //Rank0 Dynamic ODT defaults to 120 ohms\n tmp_mr2_r[0] <= #TCQ (RTT_WR == \"60\") ? 2'b01 :\n 2'b10;\n //Rank0 Rtt_NOM after write leveling completes\n tmp_mr1_r[0] <= #TCQ 3'b000;\n end\n end\n 4'b11_00: begin\n if (//wrlvl_odt ||\n (init_state_r == INIT_RDLVL_STG1_WRITE) || \n (init_state_r == INIT_WRCAL_WRITE) ||\n (init_state_r == INIT_OCAL_CENTER_WRITE) || \n (init_state_r == INIT_OCLKDELAY_WRITE)) begin\n // odt turned on only during write\n phy_tmp_odt_r <= #TCQ 4'b0001;\n end\n \n // Chip Select assignments\n phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] \n <= #TCQ {nCS_PER_RANK{1'b0}};\n \n if ((RTT_WR == \"OFF\") ||\n ((WRLVL==\"ON\") && ~wrlvl_done &&\n (wrlvl_rank_cntr==3'd0))) begin\n //Rank1 Dynamic ODT disabled\n tmp_mr2_r[0] <= #TCQ 2'b00;\n //Rank1 Rtt_NOM\n tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == \"40\") ? 3'b011 :\n (RTT_NOM_int == \"60\") ? 3'b001 :\n (RTT_NOM_int == \"120\") ? 3'b010 :\n 3'b000;\n end else begin\n //Rank1 Dynamic ODT defaults to 120 ohms\n tmp_mr2_r[0] <= #TCQ (RTT_WR == \"60\") ? 2'b01 :\n 2'b10;\n //Rank1 Rtt_NOM after write leveling completes\n tmp_mr1_r[0] <= #TCQ 3'b000;\n end\n end\n // Two slot configuration, one rank per slot\n 4'b10_10: begin\n if(DRAM_TYPE == \"DDR2\")begin\n if(chip_cnt_r == 2'b00)begin\n phy_tmp_odt_r\n <= #TCQ 4'b0010; //bit0 for rank0\n end else begin\n phy_tmp_odt_r\n <= #TCQ 4'b0001; //bit0 for rank0\n end\n end else begin\n if((init_state_r == INIT_WRLVL_WAIT) ||\n (init_next_state == INIT_RDLVL_STG1_WRITE) ||\n (init_next_state == INIT_WRCAL_WRITE) ||\n (init_next_state == INIT_OCAL_CENTER_WRITE) || \n (init_next_state == INIT_OCLKDELAY_WRITE))\n phy_tmp_odt_r <= #TCQ 4'b0011; // bit0 for rank0/1 (write)\n else if ((init_next_state == INIT_PI_PHASELOCK_READS) ||\n (init_next_state == INIT_MPR_READ) ||\n (init_next_state == INIT_RDLVL_STG1_READ) ||\n (init_next_state == INIT_RDLVL_COMPLEX_READ) || \n (init_next_state == INIT_RDLVL_STG2_READ) ||\n (init_next_state == INIT_OCLKDELAY_READ) ||\n (init_next_state == INIT_WRCAL_READ) ||\n (init_next_state == INIT_WRCAL_MULT_READS))\n phy_tmp_odt_r <= #TCQ 4'b0010; // bit0 for rank1 (rank 0 rd)\n end\n \n // Chip Select assignments\n phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] \n <= #TCQ {nCS_PER_RANK{1'b0}};\n\n if ((RTT_WR == \"OFF\") ||\n ((WRLVL==\"ON\") && ~wrlvl_done &&\n (wrlvl_rank_cntr==3'd0))) begin\n //Rank0 Dynamic ODT disabled\n tmp_mr2_r[0] <= #TCQ 2'b00;\n //Rank0 Rtt_NOM\n tmp_mr1_r[0] <= #TCQ (RTT_WR == \"60\") ? 3'b001 :\n (RTT_WR == \"120\") ? 3'b010 :\n 3'b000;\n //Rank1 Dynamic ODT disabled\n tmp_mr2_r[1] <= #TCQ (RTT_WR == \"60\") ? 2'b01 :\n 2'b10;\n //Rank1 Rtt_NOM\n tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == \"40\") ? 3'b011 :\n (RTT_NOM_int == \"60\") ? 3'b001 :\n (RTT_NOM_int == \"120\") ? 3'b010 :\n 3'b000;\n end else begin\n //Rank0 Dynamic ODT defaults to 120 ohms\n tmp_mr2_r[0] <= #TCQ (RTT_WR == \"60\") ? 2'b01 :\n 2'b10;\n //Rank0 Rtt_NOM\n tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == \"60\") ? 3'b001 :\n (RTT_NOM_int == \"120\") ? 3'b010 :\n (RTT_NOM_int == \"20\") ? 3'b100 :\n (RTT_NOM_int == \"30\") ? 3'b101 :\n (RTT_NOM_int == \"40\") ? 3'b011 :\n 3'b000;\n //Rank1 Dynamic ODT defaults to 120 ohms\n tmp_mr2_r[1] <= #TCQ (RTT_WR == \"60\") ? 2'b01 :\n 2'b10;\n //Rank1 Rtt_NOM\n tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == \"60\") ? 3'b001 :\n (RTT_NOM_int == \"120\") ? 3'b010 :\n (RTT_NOM_int == \"20\") ? 3'b100 :\n (RTT_NOM_int == \"30\") ? 3'b101 :\n (RTT_NOM_int == \"40\") ? 3'b011 :\n 3'b000;\n end\n end\n // Two Slots - One slot with dual rank and other with single rank\n 4'b10_11: begin\n\n //Rank3 Rtt_NOM\n tmp_mr1_r[2] <= #TCQ (RTT_NOM_int == \"60\") ? 3'b001 :\n (RTT_NOM_int == \"120\") ? 3'b010 :\n (RTT_NOM_int == \"20\") ? 3'b100 :\n (RTT_NOM_int == \"30\") ? 3'b101 :\n (RTT_NOM_int == \"40\") ? 3'b011 :\n 3'b000;\n tmp_mr2_r[2] <= #TCQ 2'b00;\n if ((RTT_WR == \"OFF\") ||\n ((WRLVL==\"ON\") && ~wrlvl_done &&\n (wrlvl_rank_cntr==3'd0))) begin\n //Rank0 Dynamic ODT disabled\n tmp_mr2_r[0] <= #TCQ 2'b00;\n //Rank0 Rtt_NOM\n tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == \"40\") ? 3'b011 :\n (RTT_NOM_int == \"60\") ? 3'b001 :\n (RTT_NOM_int == \"120\") ? 3'b010 :\n 3'b000;\n //Rank1 Dynamic ODT disabled\n tmp_mr2_r[1] <= #TCQ 2'b00;\n //Rank1 Rtt_NOM\n tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == \"40\") ? 3'b011 :\n (RTT_NOM_int == \"60\") ? 3'b001 :\n (RTT_NOM_int == \"120\") ? 3'b010 :\n 3'b000;\n end else begin\n //Rank0 Dynamic ODT defaults to 120 ohms\n tmp_mr2_r[0] <= #TCQ (RTT_WR == \"60\") ? 2'b01 :\n 2'b10;\n //Rank0 Rtt_NOM after write leveling completes\n tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == \"60\") ? 3'b001 :\n (RTT_NOM_int == \"120\") ? 3'b010 :\n (RTT_NOM_int == \"20\") ? 3'b100 :\n (RTT_NOM_int == \"30\") ? 3'b101 :\n (RTT_NOM_int == \"40\") ? 3'b011 :\n 3'b000;\n //Rank1 Dynamic ODT defaults to 120 ohms\n tmp_mr2_r[1] <= #TCQ (RTT_WR == \"60\") ? 2'b01 :\n 2'b10;\n //Rank1 Rtt_NOM after write leveling completes\n tmp_mr1_r[1] <= #TCQ 3'b000;\n end\n //Slot1 Rank1 or Rank3 is being written\n if(DRAM_TYPE == \"DDR2\")begin\n if(chip_cnt_r == 2'b00)begin\n phy_tmp_odt_r \n <= #TCQ 4'b0010;\n end else begin\n phy_tmp_odt_r \n <= #TCQ 4'b0001;\n end\n end else begin \n if (//wrlvl_odt ||\n (init_state_r == INIT_RDLVL_STG1_WRITE) || \n (init_state_r == INIT_WRCAL_WRITE) ||\n (init_state_r == INIT_OCAL_CENTER_WRITE) || \n (init_state_r == INIT_OCLKDELAY_WRITE)) begin\n if (chip_cnt_r[0] == 1'b1) begin\n phy_tmp_odt_r \n <= #TCQ 4'b0011;\n //Slot0 Rank0 is being written\n end else begin\n phy_tmp_odt_r \n <= #TCQ 4'b0101; // ODT for ranks 0 and 2 aserted\n end\n end else if ((init_state_r == INIT_RDLVL_STG1_READ) ||\n (init_state_r == INIT_RDLVL_COMPLEX_READ) || \n (init_state_r == INIT_PI_PHASELOCK_READS) ||\n (init_state_r == INIT_RDLVL_STG2_READ) ||\n (init_state_r == INIT_OCLKDELAY_READ) ||\n (init_state_r == INIT_WRCAL_READ) ||\n (init_state_r == INIT_WRCAL_MULT_READS))begin\n if (chip_cnt_r == 2'b00) begin\n phy_tmp_odt_r \n <= #TCQ 4'b0100;\n end else begin\n phy_tmp_odt_r\n <= #TCQ 4'b0001;\n end\n end\n end\n \n // Chip Select assignments\n phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] \n <= #TCQ {nCS_PER_RANK{1'b0}}; \n \n end\n // Two Slots - One slot with dual rank and other with single rank\n 4'b11_10: begin\n \n //Rank2 Rtt_NOM\n tmp_mr1_r[2] <= #TCQ (RTT_NOM2 == \"60\") ? 3'b001 :\n (RTT_NOM2 == \"120\") ? 3'b010 :\n (RTT_NOM2 == \"20\") ? 3'b100 :\n (RTT_NOM2 == \"30\") ? 3'b101 :\n (RTT_NOM2 == \"40\") ? 3'b011:\n 3'b000;\n tmp_mr2_r[2] <= #TCQ 2'b00;\n if ((RTT_WR == \"OFF\") ||\n ((WRLVL==\"ON\") && ~wrlvl_done &&\n (wrlvl_rank_cntr==3'd0))) begin\n //Rank0 Dynamic ODT disabled\n tmp_mr2_r[0] <= #TCQ 2'b00;\n //Rank0 Rtt_NOM\n tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == \"40\") ? 3'b011 :\n (RTT_NOM_int == \"60\") ? 3'b001 :\n (RTT_NOM_int == \"120\") ? 3'b010 :\n 3'b000;\n //Rank1 Dynamic ODT disabled\n tmp_mr2_r[1] <= #TCQ 2'b00;\n //Rank1 Rtt_NOM\n tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == \"40\") ? 3'b011 :\n (RTT_NOM_int == \"60\") ? 3'b001 :\n (RTT_NOM_int == \"120\") ? 3'b010 :\n 3'b000;\n end else begin\n //Rank1 Dynamic ODT defaults to 120 ohms\n tmp_mr2_r[1] <= #TCQ (RTT_WR == \"60\") ? 2'b01 :\n 2'b10;\n //Rank1 Rtt_NOM\n tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == \"60\") ? 3'b001 :\n (RTT_NOM_int == \"120\") ? 3'b010 :\n (RTT_NOM_int == \"20\") ? 3'b100 :\n (RTT_NOM_int == \"30\") ? 3'b101 :\n (RTT_NOM_int == \"40\") ? 3'b011:\n 3'b000;\n //Rank0 Dynamic ODT defaults to 120 ohms\n tmp_mr2_r[0] <= #TCQ (RTT_WR == \"60\") ? 2'b01 :\n 2'b10;\n //Rank0 Rtt_NOM after write leveling completes\n tmp_mr1_r[0] <= #TCQ 3'b000;\n end\n \n if(DRAM_TYPE == \"DDR2\")begin\n if(chip_cnt_r[1] == 1'b1)begin\n phy_tmp_odt_r <= \n #TCQ 4'b0001;\n end else begin\n phy_tmp_odt_r \n <= #TCQ 4'b0100; // rank 2 ODT asserted\n end\n end else begin \n if (// wrlvl_odt ||\n (init_state_r == INIT_RDLVL_STG1_WRITE) || \n (init_state_r == INIT_WRCAL_WRITE) ||\n (init_state_r == INIT_OCAL_CENTER_WRITE) || \n (init_state_r == INIT_OCLKDELAY_WRITE)) begin\n \n if (chip_cnt_r[1] == 1'b1) begin\n phy_tmp_odt_r \n <= #TCQ 4'b0110;\n end else begin\n phy_tmp_odt_r <= \n #TCQ 4'b0101;\n end\n end else if ((init_state_r == INIT_RDLVL_STG1_READ) ||\n (init_state_r == INIT_RDLVL_COMPLEX_READ) ||\n (init_state_r == INIT_PI_PHASELOCK_READS) ||\n (init_state_r == INIT_RDLVL_STG2_READ) ||\n (init_state_r == INIT_OCLKDELAY_READ) ||\n (init_state_r == INIT_WRCAL_READ) ||\n (init_state_r == INIT_WRCAL_MULT_READS)) begin\n \n if (chip_cnt_r[1] == 1'b1) begin\n phy_tmp_odt_r[(1*nCS_PER_RANK) +: nCS_PER_RANK] \n <= #TCQ 4'b0010;\n end else begin\n phy_tmp_odt_r \n <= #TCQ 4'b0100;\n end\n end\n end\n \n // Chip Select assignments\n phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] \n <= #TCQ {nCS_PER_RANK{1'b0}};\n end\n // Two Slots - two ranks per slot\n 4'b11_11: begin\n //Rank2 Rtt_NOM\n tmp_mr1_r[2] <= #TCQ (RTT_NOM2 == \"60\") ? 3'b001 :\n (RTT_NOM2 == \"120\") ? 3'b010 :\n (RTT_NOM2 == \"20\") ? 3'b100 :\n (RTT_NOM2 == \"30\") ? 3'b101 :\n (RTT_NOM2 == \"40\") ? 3'b011 :\n 3'b000;\n //Rank3 Rtt_NOM\n tmp_mr1_r[3] <= #TCQ (RTT_NOM3 == \"60\") ? 3'b001 :\n (RTT_NOM3 == \"120\") ? 3'b010 :\n (RTT_NOM3 == \"20\") ? 3'b100 :\n (RTT_NOM3 == \"30\") ? 3'b101 :\n (RTT_NOM3 == \"40\") ? 3'b011 :\n 3'b000;\n tmp_mr2_r[2] <= #TCQ 2'b00;\n tmp_mr2_r[3] <= #TCQ 2'b00;\n if ((RTT_WR == \"OFF\") ||\n ((WRLVL==\"ON\") && ~wrlvl_done &&\n (wrlvl_rank_cntr==3'd0))) begin\n //Rank0 Dynamic ODT disabled\n tmp_mr2_r[0] <= #TCQ 2'b00;\n //Rank0 Rtt_NOM\n tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == \"40\") ? 3'b011 :\n (RTT_NOM_int == \"60\") ? 3'b001 :\n (RTT_NOM_int == \"120\") ? 3'b010 :\n 3'b000;\n //Rank1 Dynamic ODT disabled\n tmp_mr2_r[1] <= #TCQ 2'b00;\n //Rank1 Rtt_NOM\n tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == \"40\") ? 3'b011 :\n (RTT_NOM_int == \"60\") ? 3'b001 :\n (RTT_NOM_int == \"120\") ? 3'b010 :\n 3'b000;\n end else begin\n //Rank1 Dynamic ODT defaults to 120 ohms\n tmp_mr2_r[1] <= #TCQ (RTT_WR == \"60\") ? 2'b01 :\n 2'b10;\n //Rank1 Rtt_NOM after write leveling completes\n tmp_mr1_r[1] <= #TCQ 3'b000;\n //Rank0 Dynamic ODT defaults to 120 ohms\n tmp_mr2_r[0] <= #TCQ (RTT_WR == \"60\") ? 2'b01 :\n 2'b10;\n //Rank0 Rtt_NOM after write leveling completes\n tmp_mr1_r[0] <= #TCQ 3'b000;\n end\n \n if(DRAM_TYPE == \"DDR2\")begin\n if(chip_cnt_r[1] == 1'b1)begin\n phy_tmp_odt_r\n <= #TCQ 4'b0001;\n end else begin\n phy_tmp_odt_r\n <= #TCQ 4'b0100;\n end\n end else begin\n if (//wrlvl_odt ||\n (init_state_r == INIT_RDLVL_STG1_WRITE) || \n (init_state_r == INIT_WRCAL_WRITE) ||\n (init_state_r == INIT_OCAL_CENTER_WRITE) || \n (init_state_r == INIT_OCLKDELAY_WRITE)) begin\n //Slot1 Rank1 or Rank3 is being written\n if (chip_cnt_r[0] == 1'b1) begin\n phy_tmp_odt_r\n <= #TCQ 4'b0110;\n //Slot0 Rank0 or Rank2 is being written\n end else begin\n phy_tmp_odt_r\n <= #TCQ 4'b1001;\n end\n end else if ((init_state_r == INIT_RDLVL_STG1_READ) ||\n (init_state_r == INIT_RDLVL_COMPLEX_READ) || \n (init_state_r == INIT_PI_PHASELOCK_READS) ||\n (init_state_r == INIT_RDLVL_STG2_READ) ||\n (init_state_r == INIT_OCLKDELAY_READ) ||\n (init_state_r == INIT_WRCAL_READ) ||\n (init_state_r == INIT_WRCAL_MULT_READS))begin\n //Slot1 Rank1 or Rank3 is being read\n if (chip_cnt_r[0] == 1'b1) begin\n phy_tmp_odt_r\n <= #TCQ 4'b0100;\n //Slot0 Rank0 or Rank2 is being read\n end else begin\n phy_tmp_odt_r\n <= #TCQ 4'b1000;\n end\n end\n end\n \n // Chip Select assignments\n phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] \n <= #TCQ {nCS_PER_RANK{1'b0}};\n end\n default: begin\n phy_tmp_odt_r <= #TCQ 4'b1111;\n // Chip Select assignments\n phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] \n <= #TCQ {nCS_PER_RANK{1'b0}};\n if ((RTT_WR == \"OFF\") ||\n ((WRLVL==\"ON\") && ~wrlvl_done)) begin\n //Rank0 Dynamic ODT disabled\n tmp_mr2_r[0] <= #TCQ 2'b00;\n //Rank0 Rtt_NOM\n tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == \"40\") ? 3'b011 :\n (RTT_NOM_int == \"60\") ? 3'b001 :\n (RTT_NOM_int == \"120\") ? 3'b010 :\n 3'b000;\n //Rank1 Dynamic ODT disabled\n tmp_mr2_r[1] <= #TCQ 2'b00;\n //Rank1 Rtt_NOM\n tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == \"40\") ? 3'b011 :\n (RTT_NOM_int == \"60\") ? 3'b001 :\n (RTT_NOM_int == \"60\") ? 3'b010 :\n 3'b000;\n end else begin\n //Rank0 Dynamic ODT defaults to 120 ohms\n tmp_mr2_r[0] <= #TCQ (RTT_WR == \"60\") ? 2'b01 :\n 2'b10;\n //Rank0 Rtt_NOM\n tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == \"60\") ? 3'b001 :\n (RTT_NOM_int == \"120\") ? 3'b010 :\n (RTT_NOM_int == \"20\") ? 3'b100 :\n (RTT_NOM_int == \"30\") ? 3'b101 :\n (RTT_NOM_int == \"40\") ? 3'b011 :\n 3'b000;\n //Rank1 Dynamic ODT defaults to 120 ohms\n tmp_mr2_r[1] <= #TCQ (RTT_WR == \"60\") ? 2'b01 :\n 2'b10;\n //Rank1 Rtt_NOM\n tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == \"60\") ? 3'b001 :\n (RTT_NOM_int == \"120\") ? 3'b010 :\n (RTT_NOM_int == \"20\") ? 3'b100 :\n (RTT_NOM_int == \"30\") ? 3'b101 :\n (RTT_NOM_int == \"40\") ? 3'b011 :\n 3'b000;\n end\n end\n endcase\n end\n end\n end\n endgenerate\n\n\n // PHY only supports two ranks.\n // calib_aux_out[0] is CKE for rank 0 and calib_aux_out[1] is ODT for rank 0\n // calib_aux_out[2] is CKE for rank 1 and calib_aux_out[3] is ODT for rank 1\n\ngenerate\nif(CKE_ODT_AUX == \"FALSE\") begin\n if ((nSLOTS == 1) && (RANKS < 2)) begin\n always @(posedge clk)\n if (rst) begin\n calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ;\n calib_odt <= 2'b00 ;\n end else begin\n if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin\n calib_cke <= #TCQ {nCK_PER_CLK{1'b1}};\n end else begin\n calib_cke <= #TCQ {nCK_PER_CLK{1'b0}};\n end\n if ((((RTT_NOM == \"DISABLED\") && (RTT_WR == \"OFF\"))/* ||\n wrlvl_rank_done || wrlvl_rank_done_r1 ||\n (wrlvl_done && !wrlvl_done_r)*/) && (DRAM_TYPE == \"DDR3\")) begin\n calib_odt[0] <= #TCQ 1'b0;\n calib_odt[1] <= #TCQ 1'b0;\n end else if (((DRAM_TYPE == \"DDR3\") \n ||((RTT_NOM != \"DISABLED\") && (DRAM_TYPE == \"DDR2\"))) \n && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt ) || \n (init_state_r == INIT_RDLVL_STG1_WRITE) ||\n (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) ||\n (init_state_r == INIT_RDLVL_STG1_WRITE_READ) ||\n complex_odt_ext ||\n (init_state_r == INIT_WRCAL_WRITE) ||\n (init_state_r == INIT_WRCAL_WRITE_READ) ||\n (init_state_r == INIT_OCAL_CENTER_WRITE) || \n complex_ocal_odt_ext ||\n (init_state_r == INIT_OCLKDELAY_WRITE)||\n\t (init_state_r == INIT_OCLKDELAY_WRITE_WAIT))) begin\n // Quad rank in a single slot \n calib_odt[0] <= #TCQ phy_tmp_odt_r[0];\n calib_odt[1] <= #TCQ phy_tmp_odt_r[1];\n end else begin\n calib_odt[0] <= #TCQ 1'b0;\n calib_odt[1] <= #TCQ 1'b0;\n end\n end\n end else if ((nSLOTS == 1) && (RANKS <= 2)) begin\n always @(posedge clk)\n if (rst) begin\n calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ;\n calib_odt <= 2'b00 ;\n end else begin\n if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin\n calib_cke <= #TCQ {nCK_PER_CLK{1'b1}};\n end else begin\n calib_cke <= #TCQ {nCK_PER_CLK{1'b0}};\n end\n if ((((RTT_NOM == \"DISABLED\") && (RTT_WR == \"OFF\"))/* ||\n wrlvl_rank_done_r2 ||\n (wrlvl_done && !wrlvl_done_r)*/) && (DRAM_TYPE == \"DDR3\")) begin\n calib_odt[0] <= #TCQ 1'b0;\n calib_odt[1] <= #TCQ 1'b0;\n end else if (((DRAM_TYPE == \"DDR3\") \n ||((RTT_NOM != \"DISABLED\") && (DRAM_TYPE == \"DDR2\"))) \n && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt)|| \n (init_state_r == INIT_RDLVL_STG1_WRITE) ||\n (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) ||\n (init_state_r == INIT_RDLVL_STG1_WRITE_READ) ||\n complex_odt_ext ||\n (init_state_r == INIT_WRCAL_WRITE) ||\n (init_state_r == INIT_WRCAL_WRITE_READ) ||\n (init_state_r == INIT_OCAL_CENTER_WRITE) || \n complex_ocal_odt_ext ||\n (init_state_r == INIT_OCLKDELAY_WRITE)||\n (init_state_r == INIT_OCLKDELAY_WRITE_WAIT))) begin\n // Dual rank in a single slot \n calib_odt[0] <= #TCQ phy_tmp_odt_r[0];\n calib_odt[1] <= #TCQ phy_tmp_odt_r[1];\n end else begin\n calib_odt[0] <= #TCQ 1'b0;\n calib_odt[1] <= #TCQ 1'b0;\n end\n end\n end else if ((nSLOTS == 2) && (RANKS == 2)) begin\n always @(posedge clk)\n if (rst)begin\n calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ;\n calib_odt <= 2'b00 ;\n end else begin\n if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin\n calib_cke <= #TCQ {nCK_PER_CLK{1'b1}};\n end else begin\n calib_cke <= #TCQ {nCK_PER_CLK{1'b0}};\n end\n if (((DRAM_TYPE == \"DDR2\") && (RTT_NOM == \"DISABLED\")) ||\n ((DRAM_TYPE == \"DDR3\") &&\n (RTT_NOM == \"DISABLED\") && (RTT_WR == \"OFF\"))) begin\n calib_odt[0] <= #TCQ 1'b0;\n calib_odt[1] <= #TCQ 1'b0;\n end else if (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || \n (init_state_r == INIT_RDLVL_STG1_WRITE) ||\n (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) ||\n (init_state_r == INIT_WRCAL_WRITE) ||\n (init_state_r == INIT_OCAL_CENTER_WRITE) || \n (init_state_r == INIT_OCLKDELAY_WRITE)) begin\n // Quad rank in a single slot \n if (nCK_PER_CLK == 2) begin\n calib_odt[0] \n <= #TCQ (!calib_odt[0]) ? phy_tmp_odt_r[0] : 1'b0;\n calib_odt[1] \n <= #TCQ (!calib_odt[1]) ? phy_tmp_odt_r[1] : 1'b0;\n end else begin \n calib_odt[0] <= #TCQ phy_tmp_odt_r[0];\n calib_odt[1] <= #TCQ phy_tmp_odt_r[1];\n end\n // Turn on for idle rank during read if dynamic ODT is enabled in DDR3\n end else if(((DRAM_TYPE == \"DDR3\") && (RTT_WR != \"OFF\")) &&\n ((init_state_r == INIT_PI_PHASELOCK_READS) ||\n (init_state_r == INIT_MPR_READ) ||\n (init_state_r == INIT_RDLVL_STG1_READ) ||\n (init_state_r == INIT_RDLVL_COMPLEX_READ) ||\n (init_state_r == INIT_RDLVL_STG2_READ) ||\n (init_state_r == INIT_OCLKDELAY_READ) ||\n (init_state_r == INIT_WRCAL_READ) ||\n (init_state_r == INIT_WRCAL_MULT_READS))) begin\n if (nCK_PER_CLK == 2) begin\n calib_odt[0] \n <= #TCQ (!calib_odt[0]) ? phy_tmp_odt_r[0] : 1'b0;\n calib_odt[1] \n <= #TCQ (!calib_odt[1]) ? phy_tmp_odt_r[1] : 1'b0;\n end else begin \n calib_odt[0] <= #TCQ phy_tmp_odt_r[0];\n calib_odt[1] <= #TCQ phy_tmp_odt_r[1];\n end\n // disable well before next command and before disabling write leveling\n end else if(cnt_cmd_done_m7_r ||\n (init_state_r == INIT_WRLVL_WAIT && ~wrlvl_odt))\n calib_odt <= #TCQ 2'b00;\n end\n end\nend else begin//USE AUX OUTPUT for routing CKE and ODT.\n if ((nSLOTS == 1) && (RANKS < 2)) begin\n always @(posedge clk)\n if (rst) begin\n calib_aux_out <= #TCQ 4'b0000;\n end else begin\n if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin\n calib_aux_out[0] <= #TCQ 1'b1;\n calib_aux_out[2] <= #TCQ 1'b1;\n end else begin\n calib_aux_out[0] <= #TCQ 1'b0;\n calib_aux_out[2] <= #TCQ 1'b0;\n end\n if ((((RTT_NOM == \"DISABLED\") && (RTT_WR == \"OFF\")) ||\n wrlvl_rank_done || wrlvl_rank_done_r1 ||\n (wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == \"DDR3\")) begin\n calib_aux_out[1] <= #TCQ 1'b0;\n calib_aux_out[3] <= #TCQ 1'b0;\n end else if (((DRAM_TYPE == \"DDR3\") \n ||((RTT_NOM != \"DISABLED\") && (DRAM_TYPE == \"DDR2\"))) \n && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || \n (init_state_r == INIT_RDLVL_STG1_WRITE) ||\n (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) ||\n (init_state_r == INIT_WRCAL_WRITE) ||\n (init_state_r == INIT_OCAL_CENTER_WRITE) || \n (init_state_r == INIT_OCLKDELAY_WRITE))) begin\n // Quad rank in a single slot \n calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0];\n calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1];\n end else begin\n calib_aux_out[1] <= #TCQ 1'b0;\n calib_aux_out[3] <= #TCQ 1'b0;\n end\n end\n end else if ((nSLOTS == 1) && (RANKS <= 2)) begin\n always @(posedge clk)\n if (rst) begin\n calib_aux_out <= #TCQ 4'b0000;\n end else begin\n if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin\n calib_aux_out[0] <= #TCQ 1'b1;\n calib_aux_out[2] <= #TCQ 1'b1;\n end else begin\n calib_aux_out[0] <= #TCQ 1'b0;\n calib_aux_out[2] <= #TCQ 1'b0;\n end\n if ((((RTT_NOM == \"DISABLED\") && (RTT_WR == \"OFF\")) ||\n wrlvl_rank_done_r2 ||\n (wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == \"DDR3\")) begin\n calib_aux_out[1] <= #TCQ 1'b0;\n calib_aux_out[3] <= #TCQ 1'b0;\n end else if (((DRAM_TYPE == \"DDR3\") \n ||((RTT_NOM != \"DISABLED\") && (DRAM_TYPE == \"DDR2\"))) \n && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || \n (init_state_r == INIT_RDLVL_STG1_WRITE) ||\n (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) ||\n (init_state_r == INIT_WRCAL_WRITE) ||\n (init_state_r == INIT_OCAL_CENTER_WRITE) || \n (init_state_r == INIT_OCLKDELAY_WRITE))) begin\n // Dual rank in a single slot \n calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0];\n calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1];\n end else begin\n calib_aux_out[1] <= #TCQ 1'b0;\n calib_aux_out[3] <= #TCQ 1'b0;\n end\n end\n end else if ((nSLOTS == 2) && (RANKS == 2)) begin\n always @(posedge clk)\n if (rst)\n calib_aux_out <= #TCQ 4'b0000;\n else begin\n if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin\n calib_aux_out[0] <= #TCQ 1'b1;\n calib_aux_out[2] <= #TCQ 1'b1;\n end else begin\n calib_aux_out[0] <= #TCQ 1'b0;\n calib_aux_out[2] <= #TCQ 1'b0;\n end\n if ((((RTT_NOM == \"DISABLED\") && (RTT_WR == \"OFF\")) ||\n wrlvl_rank_done_r2 ||\n (wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == \"DDR3\")) begin\n calib_aux_out[1] <= #TCQ 1'b0;\n calib_aux_out[3] <= #TCQ 1'b0;\n end else if (((DRAM_TYPE == \"DDR3\") \n ||((RTT_NOM != \"DISABLED\") && (DRAM_TYPE == \"DDR2\"))) \n && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || \n (init_state_r == INIT_RDLVL_STG1_WRITE) ||\n (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) ||\n (init_state_r == INIT_WRCAL_WRITE) ||\n (init_state_r == INIT_OCAL_CENTER_WRITE) || \n (init_state_r == INIT_OCLKDELAY_WRITE))) begin \n // Quad rank in a single slot \n if (nCK_PER_CLK == 2) begin\n calib_aux_out[1] \n <= #TCQ (!calib_aux_out[1]) ? phy_tmp_odt_r[0] : 1'b0;\n calib_aux_out[3] \n <= #TCQ (!calib_aux_out[3]) ? phy_tmp_odt_r[1] : 1'b0;\n end else begin \n calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0];\n calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1];\n end\n end else begin\n calib_aux_out[1] <= #TCQ 1'b0;\n calib_aux_out[3] <= #TCQ 1'b0;\n end\n end\n end\nend \nendgenerate\n \n //*****************************************************************\n // memory address during init\n //*****************************************************************\n\n always @(posedge clk)\n phy_data_full_r <= #TCQ phy_data_full;\n// verilint STARC-2.7.3.3b off\n always @(*)begin\n // Bus 0 for address/bank never used\n address_w = 'b0;\n bank_w = 'b0;\n if ((init_state_r == INIT_PRECHARGE) ||\n (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||\n (init_state_r == INIT_ZQCL) ||\n (init_state_r == INIT_DDR2_PRECHARGE)) begin\n // Set A10=1 for ZQ long calibration or Precharge All\n address_w = 'b0;\n address_w[10] = 1'b1;\n bank_w = 'b0;\n end else if (init_state_r == INIT_WRLVL_START) begin\n // Enable wrlvl in MR1\n bank_w[1:0] = 2'b01;\n address_w = load_mr1[ROW_WIDTH-1:0];\n address_w[2] = mr1_r[chip_cnt_r][0];\n address_w[6] = mr1_r[chip_cnt_r][1];\n address_w[9] = mr1_r[chip_cnt_r][2];\n address_w[7] = 1'b1;\n end else if (init_state_r == INIT_WRLVL_LOAD_MR) begin\n // Finished with write leveling, disable wrlvl in MR1\n // For single rank disable Rtt_Nom\n bank_w[1:0] = 2'b01;\n address_w = load_mr1[ROW_WIDTH-1:0];\n address_w[2] = mr1_r[chip_cnt_r][0];\n address_w[6] = mr1_r[chip_cnt_r][1];\n address_w[9] = mr1_r[chip_cnt_r][2];\n end else if (init_state_r == INIT_WRLVL_LOAD_MR2) begin\n // Set RTT_WR in MR2 after write leveling disabled\n bank_w[1:0] = 2'b10;\n address_w = load_mr2[ROW_WIDTH-1:0];\n address_w[10:9] = mr2_r[chip_cnt_r];\n end else if (init_state_r == INIT_MPR_READ) begin\n address_w = 'b0;\n bank_w = 'b0;\n end else if (init_state_r == INIT_MPR_RDEN) begin\n // Enable MPR read with LMR3 and A2=1\n bank_w[BANK_WIDTH-1:0] = 'd3;\n address_w = {ROW_WIDTH{1'b0}};\n address_w[2] = 1'b1;\n end else if (init_state_r == INIT_MPR_DISABLE) begin\n // Disable MPR read with LMR3 and A2=0\n bank_w[BANK_WIDTH-1:0] = 'd3;\n address_w = {ROW_WIDTH{1'b0}}; \n end else if ((init_state_r == INIT_REG_WRITE)&\n (DRAM_TYPE == \"DDR3\"))begin\n // bank_w is assigned a 3 bit value. In some\n // DDR2 cases there will be only two bank bits.\n //Qualifying the condition with DDR3\n bank_w = 'b0;\n address_w = 'b0;\n case (reg_ctrl_cnt_r)\n 4'h1:begin\n address_w[4:0] = REG_RC1[4:0];\n bank_w = REG_RC1[7:5];\n end\n 4'h2: address_w[4:0] = REG_RC2[4:0];\n 4'h3: begin\n address_w[4:0] = REG_RC3[4:0];\n bank_w = REG_RC3[7:5];\n end\n 4'h4: begin\n address_w[4:0] = REG_RC4[4:0];\n bank_w = REG_RC4[7:5];\n end\n 4'h5: begin\n address_w[4:0] = REG_RC5[4:0];\n bank_w = REG_RC5[7:5];\n end\n 4'h6: begin\n address_w[4:0] = REG_RC10[4:0];\n bank_w = REG_RC10[7:5];\n end\n 4'h7: begin\n address_w[4:0] = REG_RC11[4:0];\n bank_w = REG_RC11[7:5];\n end\n default: address_w[4:0] = REG_RC0[4:0];\n endcase\n end else if (init_state_r == INIT_LOAD_MR) begin\n // If loading mode register, look at cnt_init_mr to determine\n // which MR is currently being programmed\n address_w = 'b0;\n bank_w = 'b0;\n if(DRAM_TYPE == \"DDR3\")begin\n if(rdlvl_stg1_done && prbs_rdlvl_done && pi_dqs_found_done)begin\n // end of the calibration programming correct\n // burst length\n if (TEST_AL == \"0\") begin\n bank_w[1:0] = 2'b00;\n address_w = load_mr0[ROW_WIDTH-1:0];\n address_w[8]= 1'b0; //Don't reset DLL\n end else begin\n // programming correct AL value\n bank_w[1:0] = 2'b01;\n address_w = load_mr1[ROW_WIDTH-1:0];\n if (TEST_AL == \"CL-1\")\n address_w[4:3]= 2'b01; // AL=\"CL-1\"\n else\n address_w[4:3]= 2'b10; // AL=\"CL-2\"\n end\n end else begin\n case (cnt_init_mr_r)\n INIT_CNT_MR2: begin\n bank_w[1:0] = 2'b10;\n address_w = load_mr2[ROW_WIDTH-1:0];\n address_w[10:9] = mr2_r[chip_cnt_r];\n end\n INIT_CNT_MR3: begin\n bank_w[1:0] = 2'b11;\n address_w = load_mr3[ROW_WIDTH-1:0];\n end\n INIT_CNT_MR1: begin\n bank_w[1:0] = 2'b01;\n address_w = load_mr1[ROW_WIDTH-1:0];\n address_w[2] = mr1_r[chip_cnt_r][0];\n address_w[6] = mr1_r[chip_cnt_r][1];\n address_w[9] = mr1_r[chip_cnt_r][2];\n end\n INIT_CNT_MR0: begin\n bank_w[1:0] = 2'b00;\n address_w = load_mr0[ROW_WIDTH-1:0];\n // fixing it to BL8 for calibration\n address_w[1:0] = 2'b00;\n end\n default: begin\n bank_w = {BANK_WIDTH{1'bx}};\n address_w = {ROW_WIDTH{1'bx}};\n end\n endcase\n end\n end else begin // DDR2\n case (cnt_init_mr_r)\n INIT_CNT_MR2: begin\n if(~ddr2_refresh_flag_r)begin\n bank_w[1:0] = 2'b10;\n address_w = load_mr2[ROW_WIDTH-1:0];\n end else begin // second set of lm commands\n bank_w[1:0] = 2'b00;\n address_w = load_mr0[ROW_WIDTH-1:0];\n address_w[8]= 1'b0;\n //MRS command without resetting DLL\n end\n end\n INIT_CNT_MR3: begin\n if(~ddr2_refresh_flag_r)begin\n bank_w[1:0] = 2'b11;\n address_w = load_mr3[ROW_WIDTH-1:0];\n end else begin // second set of lm commands\n bank_w[1:0] = 2'b00;\n address_w = load_mr0[ROW_WIDTH-1:0];\n address_w[8]= 1'b0;\n //MRS command without resetting DLL. Repeted again\n // because there is an extra state.\n end\n end\n INIT_CNT_MR1: begin\n bank_w[1:0] = 2'b01; \n if(~ddr2_refresh_flag_r)begin \n address_w = load_mr1[ROW_WIDTH-1:0]; \n end else begin // second set of lm commands\n address_w = load_mr1[ROW_WIDTH-1:0];\n address_w[9:7] = 3'b111;\n //OCD default state\n end\n end\n INIT_CNT_MR0: begin\n if(~ddr2_refresh_flag_r)begin\n bank_w[1:0] = 2'b00;\n address_w = load_mr0[ROW_WIDTH-1:0];\n end else begin // second set of lm commands\n bank_w[1:0] = 2'b01;\n address_w = load_mr1[ROW_WIDTH-1:0];\n if((chip_cnt_r == 2'd1) || (chip_cnt_r == 2'd3))begin\n // always disable odt for rank 1 and rank 3 as per SPEC\n address_w[2] = 'b0;\n address_w[6] = 'b0;\n end \n //OCD exit\n end\n end\n default: begin\n bank_w = {BANK_WIDTH{1'bx}};\n address_w = {ROW_WIDTH{1'bx}};\n end\n endcase\n end\n end else if ( ~prbs_rdlvl_done && ((init_state_r == INIT_PI_PHASELOCK_READS) ||\n (init_state_r == INIT_RDLVL_STG1_WRITE) ||\n (init_state_r == INIT_RDLVL_STG1_READ) ||\n (init_state_r == INIT_RDLVL_COMPLEX_READ))) begin\n // Writing and reading PRBS pattern for read leveling stage 1\n // Need to support burst length 4 or 8. PRBS pattern will be\n // written to entire row and read back from the same row repeatedly \n bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0];\n address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}};\n if (((stg1_wr_rd_cnt == NUM_STG1_WR_RD) && ~rdlvl_stg1_done) || (stg1_wr_rd_cnt == 'd127) || \n ((stg1_wr_rd_cnt == 'd22) && (((init_state_r1 != INIT_RDLVL_STG1_WRITE) && ~stg1_wr_done) || complex_row0_rd_done))) begin\n address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}};\n end else if (phy_data_full_r || (!new_burst_r))\n address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0];\n else if ((stg1_wr_rd_cnt >= 9'd0) && new_burst_r && ~phy_data_full_r) begin\n if ((init_state_r == INIT_RDLVL_COMPLEX_READ) && (init_state_r1 != INIT_RDLVL_COMPLEX_READ) )// ||\n // ((init_state_r == INIT_RDLVL_STG1_WRITE) && prbs_rdlvl_done) )\n address_w[COL_WIDTH-1:0] = complex_address[COL_WIDTH-1:0] + ADDR_INC;\n else\n address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC;\n end\n //need to add address for complex oclkdelay calib\n end else if (prbs_rdlvl_done && ((init_state_r == INIT_RDLVL_STG1_WRITE) || \n (init_state_r == INIT_RDLVL_COMPLEX_READ))) begin\n bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0];\n address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}};\n if ((stg1_wr_rd_cnt == 'd127) || ((stg1_wr_rd_cnt == 'd30) && (((init_state_r1 != INIT_RDLVL_STG1_WRITE) && ~stg1_wr_done) || complex_row0_rd_done))) begin\n address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}};\n end else if (phy_data_full_r || (!new_burst_r))\n address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0];\n else if ((stg1_wr_rd_cnt >= 9'd0) && new_burst_r && ~phy_data_full_r) begin\n if ((init_state_r == INIT_RDLVL_STG1_WRITE) && (init_state_r1 != INIT_RDLVL_STG1_WRITE) )\n // ((init_state_r == INIT_RDLVL_STG1_WRITE) && prbs_rdlvl_done) )\n address_w[COL_WIDTH-1:0] = complex_address[COL_WIDTH-1:0] + ADDR_INC;\n else\n address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC;\n end \n \n end else if ((init_state_r == INIT_OCLKDELAY_WRITE) ||\n (init_state_r == INIT_OCAL_CENTER_WRITE) || \n (init_state_r == INIT_OCLKDELAY_READ)) begin\n bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0];\n address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}};\n if (oclk_wr_cnt == NUM_STG1_WR_RD)\n address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}};\n else if (phy_data_full_r || (!new_burst_r))\n address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0];\n else if ((oclk_wr_cnt >= 4'd0) && new_burst_r && ~phy_data_full_r)\n address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC;\n end else if ((init_state_r == INIT_WRCAL_WRITE) ||\n (init_state_r == INIT_WRCAL_READ)) begin\n bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0];\n address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}};\n if (wrcal_wr_cnt == NUM_STG1_WR_RD)\n address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}};\n else if (phy_data_full_r || (!new_burst_r))\n address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0];\n else if ((wrcal_wr_cnt >= 4'd0) && new_burst_r && ~phy_data_full_r)\n address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC; \n end else if ((init_state_r == INIT_WRCAL_MULT_READS) ||\n (init_state_r == INIT_RDLVL_STG2_READ)) begin\n // when writing or reading back training pattern for read leveling stage2\n // need to support burst length of 4 or 8. This may mean issuing\n // multiple commands to cover the entire range of addresses accessed\n // during read leveling.\n // Hard coding A[12] to 1 so that it will always be burst length of 8\n // for DDR3. Does not have any effect on DDR2. \n bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0];\n address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}};\n address_w[COL_WIDTH-1:0] = \n {CALIB_COL_ADD[COL_WIDTH-1:3],burst_addr_r, 3'b000};\n address_w[12] = 1'b1;\n end else if ((init_state_r == INIT_RDLVL_ACT) ||\n (init_state_r == INIT_RDLVL_COMPLEX_ACT) ||\n (init_state_r == INIT_WRCAL_ACT) ||\n (init_state_r == INIT_OCAL_COMPLEX_ACT) ||\n (init_state_r == INIT_OCAL_CENTER_ACT) ||\n (init_state_r == INIT_OCLKDELAY_ACT)) begin\n\n bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0];\n //if (stg1_wr_rd_cnt == 'd22)\n // address_w = CALIB_ROW_ADD[ROW_WIDTH-1:0] + 1;\n //else\n address_w = prbs_rdlvl_done ? CALIB_ROW_ADD[ROW_WIDTH-1:0] + complex_row_cnt_ocal :\n CALIB_ROW_ADD[ROW_WIDTH-1:0] + complex_row_cnt;\n end else begin\n bank_w = {BANK_WIDTH{1'bx}};\n address_w = {ROW_WIDTH{1'bx}};\n end\n end \n // verilint STARC-2.7.3.3b on\n // registring before sending out\n generate\n genvar r,s;\n if ((DRAM_TYPE != \"DDR3\") || (CA_MIRROR != \"ON\")) begin: gen_no_mirror\n for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: div_clk_loop\n always @(posedge clk) begin\n phy_address[(r*ROW_WIDTH) +: ROW_WIDTH] <= #TCQ address_w;\n phy_bank[(r*BANK_WIDTH) +: BANK_WIDTH] <= #TCQ bank_w;\n end\n end\n end else begin: gen_mirror\n // Control/addressing mirroring (optional for DDR3 dual rank DIMMs)\n // Mirror for the 2nd rank only. Logic needs to be enhanced to account\n // for multiple slots, currently only supports one slot, 2-rank config\n\n for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: gen_ba_div_clk_loop \n for (s = 0; s < BANK_WIDTH; s = s + 1) begin: gen_ba\n \n always @(posedge clk)\n if (chip_cnt_r == 2'b00) begin\n phy_bank[(r*BANK_WIDTH) + s] <= #TCQ bank_w[s];\n end else begin\n phy_bank[(r*BANK_WIDTH) + s] <= #TCQ bank_w[(s == 0) ? 1 : ((s == 1) ? 0 : s)];\n end\n\n end\n end\n\n for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: gen_addr_div_clk_loop \n for (s = 0; s < ROW_WIDTH; s = s + 1) begin: gen_addr\n always @(posedge clk) \n if (chip_cnt_r == 2'b00) begin \n phy_address[(r*ROW_WIDTH) + s] <= #TCQ address_w[s];\n end else begin \n phy_address[(r*ROW_WIDTH) + s] <= #TCQ address_w[\n (s == 3) ? 4 : \n ((s == 4) ? 3 :\n ((s == 5) ? 6 : \n ((s == 6) ? 5 :\n ((s == 7) ? 8 : \n ((s == 8) ? 7 : s)))))];\n end\n end\n end\n \n end\n endgenerate\n \nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_cntlr.v", "content": "//*****************************************************************************\n// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor: Xilinx\n// \\ \\ \\/ Version: %version\n// \\ \\ Application: MIG\n// / / Filename: ddr_phy_v4_0_phy_ocd_cntlr.v\n// /___/ /\\ Date Last Modified: $Date: 2011/02/25 02:07:40 $\n// \\ \\ / \\ Date Created: Aug 03 2009 \n// \\___\\/\\___\\\n//\n//Device: 7 Series\n//Design Name: DDR3 SDRAM\n//Purpose: Steps through the major sections of the output clock\n// delay algorithm. Enabling various subblocks at the right time.\n//\n// Steps through each byte of the interface.\n//\n// Implements both the simple and complex data pattern.\n//\n// for each byte in interface\n// begin\n// Limit\n// Scan - which includes DQS centering\n// Precharge\n// end\n// set _wrlvl and _done equal to one\n// \n//Reference:\n//Revision History:\n//*****************************************************************************\n\n`timescale 1ps/1ps\n\nmodule mig_7series_v4_0_ddr_phy_ocd_cntlr #\n (parameter TCQ = 100,\n parameter DQS_CNT_WIDTH = 3,\n parameter DQS_WIDTH = 8)\n (/*AUTOARG*/\n // Outputs\n wrlvl_final, complex_wrlvl_final, oclk_init_delay_done,\n ocd_prech_req, lim_start, complex_oclkdelay_calib_done,\n oclkdelay_calib_done, phy_rddata_en_1, phy_rddata_en_2,\n phy_rddata_en_3, ocd_cntlr2stg2_dec, oclkdelay_calib_cnt,\n reset_scan,\n // Inputs\n clk, rst, prech_done, oclkdelay_calib_start,\n complex_oclkdelay_calib_start, lim_done, phy_rddata_en,\n po_counter_read_val, po_rdy, scan_done\n );\n\n localparam ONE = 1;\n \n input clk;\n input rst;\n \n output wrlvl_final, complex_wrlvl_final;\n reg wrlvl_final_ns, wrlvl_final_r, complex_wrlvl_final_ns, complex_wrlvl_final_r;\n always @(posedge clk) wrlvl_final_r <= #TCQ wrlvl_final_ns;\n always @(posedge clk) complex_wrlvl_final_r <= #TCQ complex_wrlvl_final_ns;\n assign wrlvl_final = wrlvl_final_r;\n assign complex_wrlvl_final = complex_wrlvl_final_r;\n \n // Completed initial delay increment\n output oclk_init_delay_done; // may not need this... maybe for fast cal mode.\n assign oclk_init_delay_done = 1'b1;\n\n // Precharge done status from ddr_phy_init\n input prech_done;\n reg ocd_prech_req_ns, ocd_prech_req_r;\n always @(posedge clk) ocd_prech_req_r <= #TCQ ocd_prech_req_ns;\n output ocd_prech_req;\n assign ocd_prech_req = ocd_prech_req_r;\n\n input oclkdelay_calib_start, complex_oclkdelay_calib_start;\n input lim_done;\n\n reg lim_start_ns, lim_start_r;\n always @(posedge clk) lim_start_r <= #TCQ lim_start_ns;\n output lim_start;\n assign lim_start = lim_start_r;\n \n reg complex_oclkdelay_calib_done_ns, complex_oclkdelay_calib_done_r;\n always @(posedge clk) complex_oclkdelay_calib_done_r <= #TCQ complex_oclkdelay_calib_done_ns;\n output complex_oclkdelay_calib_done;\n assign complex_oclkdelay_calib_done = complex_oclkdelay_calib_done_r;\n \n reg oclkdelay_calib_done_ns, oclkdelay_calib_done_r;\n always @(posedge clk) oclkdelay_calib_done_r <= #TCQ oclkdelay_calib_done_ns;\n output oclkdelay_calib_done;\n assign oclkdelay_calib_done = oclkdelay_calib_done_r;\n\n input phy_rddata_en;\n reg prde_r1, prde_r2;\n always @(posedge clk) prde_r1 <= #TCQ phy_rddata_en;\n always @(posedge clk) prde_r2 <= #TCQ prde_r1;\n wire prde = complex_oclkdelay_calib_start ? prde_r2 : phy_rddata_en;\n \n reg phy_rddata_en_r1, phy_rddata_en_r2, phy_rddata_en_r3;\n always @(posedge clk) phy_rddata_en_r1 <= #TCQ prde;\n always @(posedge clk) phy_rddata_en_r2 <= #TCQ phy_rddata_en_r1;\n always @(posedge clk) phy_rddata_en_r3 <= #TCQ phy_rddata_en_r2;\n output phy_rddata_en_1, phy_rddata_en_2, phy_rddata_en_3;\n assign phy_rddata_en_1 = phy_rddata_en_r1;\n assign phy_rddata_en_2 = phy_rddata_en_r2;\n assign phy_rddata_en_3 = phy_rddata_en_r3;\n\n input [8:0] po_counter_read_val;\n reg ocd_cntlr2stg2_dec_r;\n output ocd_cntlr2stg2_dec;\n assign ocd_cntlr2stg2_dec = ocd_cntlr2stg2_dec_r;\n input po_rdy;\n\n reg [3:0] po_rd_wait_ns, po_rd_wait_r;\n always @(posedge clk) po_rd_wait_r <= #TCQ po_rd_wait_ns;\n\n reg [DQS_CNT_WIDTH-1:0] byte_ns, byte_r;\n always @(posedge clk) byte_r <= #TCQ byte_ns;\n output [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;\n assign oclkdelay_calib_cnt = {1'b0, byte_r};\n\n reg reset_scan_ns, reset_scan_r;\n always @(posedge clk) reset_scan_r <= #TCQ reset_scan_ns;\n output reset_scan;\n assign reset_scan = reset_scan_r;\n input scan_done;\n\n reg [2:0] sm_ns, sm_r;\n always @(posedge clk) sm_r <= #TCQ sm_ns;\n\n // Primary state machine.\n \n always @(*) begin\n\n // Default next state assignments.\n\n byte_ns = byte_r;\n complex_wrlvl_final_ns = complex_wrlvl_final_r;\n lim_start_ns = lim_start_r;\n oclkdelay_calib_done_ns = oclkdelay_calib_done_r;\n complex_oclkdelay_calib_done_ns = complex_oclkdelay_calib_done_r;\n ocd_cntlr2stg2_dec_r = 1'b0;\n po_rd_wait_ns = po_rd_wait_r;\n if (|po_rd_wait_r) po_rd_wait_ns = po_rd_wait_r - 4'b1;\n reset_scan_ns = reset_scan_r;\n wrlvl_final_ns = wrlvl_final_r;\n sm_ns = sm_r;\n ocd_prech_req_ns= 1'b0;\n \n if (rst == 1'b1) begin\n \n // RESET next states\n complex_oclkdelay_calib_done_ns = 1'b0;\n complex_wrlvl_final_ns = 1'b0;\n sm_ns = /*AK(\"READY\")*/3'd0;\n lim_start_ns = 1'b0;\n oclkdelay_calib_done_ns = 1'b0;\n reset_scan_ns = 1'b1;\n wrlvl_final_ns = 1'b0;\n end else\n \n // State based actions and next states. \n case (sm_r)\n /*AL(\"READY\")*/3'd0: begin\n\t byte_ns = {DQS_CNT_WIDTH{1'b0}};\n\t if (oclkdelay_calib_start && ~oclkdelay_calib_done_r ||\n\t complex_oclkdelay_calib_start && ~complex_oclkdelay_calib_done_r)\n begin\n sm_ns = /*AK(\"LIMIT_START\")*/3'd1;\n\t lim_start_ns = 1'b1;\n\t end\n end\t\n\n /*AL(\"LIMIT_START\")*/3'd1:\n\t sm_ns = /*AK(\"LIMIT_WAIT\")*/3'd2;\n\n /*AL(\"LIMIT_WAIT\")*/3'd2:begin\n\t if (lim_done) begin\n\t lim_start_ns = 1'b0;\n\t sm_ns = /*AK(\"SCAN\")*/3'd3;\n\t reset_scan_ns = 1'b0;\n\t end\n end\n\n\t/*AL(\"SCAN\")*/3'd3:begin\n\t if (scan_done) begin\n\t reset_scan_ns = 1'b1;\n\t sm_ns = /*AK(\"COMPUTE\")*/3'd4;\n\t end\n end\n\n /*AL(\"COMPUTE\")*/3'd4:begin\n\t sm_ns = /*AK(\"PRECHARGE\")*/3'd5;\n\t ocd_prech_req_ns = 1'b1;\n end\n\t\n /*AL(\"PRECHARGE\")*/3'd5:begin\n\t if (prech_done) sm_ns = /*AK(\"DONE\")*/3'd6;\n end\n\t\n\t/*AL(\"DONE\")*/3'd6:begin\n\t byte_ns = byte_r + ONE[DQS_CNT_WIDTH-1:0];\n\t if ({1'b0, byte_r} == DQS_WIDTH[DQS_CNT_WIDTH:0] - ONE[DQS_WIDTH:0]) begin\n\t byte_ns = {DQS_CNT_WIDTH{1'b0}};\n\t po_rd_wait_ns = 4'd8;\n\t sm_ns = /*AK(\"STG2_2_ZERO\")*/3'd7;\n\t end else begin\n\t sm_ns = /*AK(\"LIMIT_START\")*/3'd1;\n\t lim_start_ns = 1'b1;\n\t end\n end\n\n\t/*AL(\"STG2_2_ZERO\")*/3'd7:\n\t if (~|po_rd_wait_r && po_rdy)\n\t if (|po_counter_read_val[5:0]) ocd_cntlr2stg2_dec_r = 1'b1;\n\t else begin\n\t if ({1'b0, byte_r} == DQS_WIDTH[DQS_CNT_WIDTH:0] - ONE[DQS_WIDTH:0]) begin\n\t sm_ns = /*AK(\"READY\")*/3'd0;\n\t oclkdelay_calib_done_ns= 1'b1;\n\t wrlvl_final_ns = 1'b1;\n\t if (complex_oclkdelay_calib_start) begin\n complex_oclkdelay_calib_done_ns = 1'b1;\n\t complex_wrlvl_final_ns = 1'b1;\n\t end\n\t end else begin\n\t\tbyte_ns = byte_r + ONE[DQS_CNT_WIDTH-1:0];\n\t\tpo_rd_wait_ns = 4'd8;\n\t end\n\t end // else: !if(|po_counter_read_val[5:0])\n \n endcase // case (sm_r)\n end // always @ begin\n \nendmodule // mig_7series_v4_0_ddr_phy_ocd_cntlr\n\n// Local Variables:\n// verilog-autolabel-prefix: \"3'd\"\n// End:\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_data.v", "content": "//*****************************************************************************\n// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor: Xilinx\n// \\ \\ \\/ Version: %version\n// \\ \\ Application: MIG\n// / / Filename: ddr_phy_v4_0_phy_ocd_data.v\n// /___/ /\\ Date Last Modified: $Date: 2011/02/25 02:07:40 $\n// \\ \\ / \\ Date Created: Aug 03 2009 \n// \\___\\/\\___\\\n//\n//Device: 7 Series\n//Design Name: DDR3 SDRAM\n//Purpose: Data comparison for both \"non-complex\" and \"complex\" data.\n//\n// Depending on complex_oclkdelay_calib_start, data provided on the phy_rddata\n// bus is compared against a fixed ones and zeros pattern, or against data\n// provided on the prob_o bus.\n//\n// In the case of complex data, the phy_rddata data is delayed by two\n// clocks to match up with the prbs_o data.\n//\n// For 4:1 mode, in each fabric clock, a complete DRAM burst may be delivered.\n// A DRAM burst is 8 times the width of the DQ bus. For an 8 byte DQ\n// bus, 64 bytes are delivered on each clock.\n//\n// In 2:1 mode the DRAM burst is delivered on two fabric clocks. For\n// an 8 byte bus, 32 bytes are delivered with each fabric clock.\n//\n// For the most part, this block does not use phy_rddata_en. It delivers\n// its results and depends on downstream logic to know when its valid.\n//\n// phy_rddata_en is used for the PRBS compares when the last line of data\n// needs to be carried over to a subsequent line.\n//\n// Since we work on a byte at a time, the comparison only works on\n// one byte of the DQ bus at a time. The oclkdelay_calib_cnt field is used to\n// select the proper 8 bytes out of both the phy_rddata and prob_o streams.\n//\n// Comparisons are computed for \"zero\" or \"rise\" data, and \"oneeighty\" or\n// \"fall\" data. The \"oneeighty\" compares assumes the rising edge clock is\n// landing in the oneeighty data.\n//\n// For the simple data, we don't need to worry about first byte or last\n// byte conditions because the sampled data is taken from the middle\n// of a 4 burst segment.\n//\n// The complex (or PRBS) data starts and stops. And we need to be\n// careful about ignoring compares that might be using invalid latched\n// data. The PRBS generator provides prbs_ignore_first_byte and \n// prbs_ignore_last_bytes. The comparison block is procedural. It\n// first compares across the entire line, then comes back and overwrites\n// any byte compare results as indicated by the _ignore_ wires.\n// \n// The compares generate an eight bit vector, one for each byte. The\n// final step is to bitwise AND this eight bit vector. We end up\n// with two sets of two bits. Zero and oneeighty for the fixed pattern\n// and the prbs. \n//\n// complex_oclkdelay_calib_start is used to\n// select between the fixed and prbs compares. The final output\n// is a two bit match bus.\n//\n// There is a deprecated feature to mask the compare for any byte.\n//\n// \n//Reference:\n//Revision History:\n//*****************************************************************************\n\n`timescale 1ps/1ps\n\nmodule mig_7series_v4_0_ddr_phy_ocd_data #\n (parameter TCQ = 100,\n parameter nCK_PER_CLK = 4,\n parameter DQS_CNT_WIDTH = 3,\n parameter DQ_WIDTH = 64)\n (/*AUTOARG*/\n // Outputs\n match,\n // Inputs\n clk, rst, complex_oclkdelay_calib_start, phy_rddata, prbs_o,\n oclkdelay_calib_cnt, prbs_ignore_first_byte, prbs_ignore_last_bytes,\n phy_rddata_en_1\n );\n\n localparam [7:0] OCAL_DQ_MASK = 8'b0000_0000;\n\n input clk;\n input rst;\n\n input complex_oclkdelay_calib_start;\n input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata;\n input [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o;\n input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;\n\n reg [DQ_WIDTH-1:0] word, word_shifted;\n \n reg [63:0] data_bytes_ns, data_bytes_r, data_bytes_r1, data_bytes_r2, prbs_bytes_ns, prbs_bytes_r;\n always @(posedge clk) data_bytes_r <= #TCQ data_bytes_ns;\n always @(posedge clk) data_bytes_r1 <= #TCQ data_bytes_r;\n always @(posedge clk) data_bytes_r2 <= #TCQ data_bytes_r1;\n always @(posedge clk) prbs_bytes_r <= #TCQ prbs_bytes_ns;\n\n input prbs_ignore_first_byte, prbs_ignore_last_bytes;\n reg prbs_ignore_first_byte_r, prbs_ignore_last_bytes_r;\n always @(posedge clk) prbs_ignore_first_byte_r <= #TCQ prbs_ignore_first_byte;\n always @(posedge clk) prbs_ignore_last_bytes_r <= #TCQ prbs_ignore_last_bytes;\n\n input phy_rddata_en_1;\n reg [7:0] last_byte_r;\n wire [63:0] data_bytes = complex_oclkdelay_calib_start ? data_bytes_r2 : data_bytes_r;\n \n wire [7:0] last_byte_ns;\n generate if (nCK_PER_CLK == 4) begin\n assign last_byte_ns = phy_rddata_en_1 ? data_bytes[63:56] : last_byte_r;\n end else begin\n assign last_byte_ns = phy_rddata_en_1 ? data_bytes[31:24] : last_byte_r;\n end endgenerate\n always @(posedge clk) last_byte_r <= #TCQ last_byte_ns;\n\n reg second_half_ns, second_half_r;\n always @(posedge clk) second_half_r <= #TCQ second_half_ns;\n always @(*) begin\n second_half_ns = second_half_r;\n if (rst) second_half_ns = 1'b0;\n else second_half_ns = phy_rddata_en_1 ^ second_half_r;\n end\n\n reg [7:0] comp0, comp180, prbs0, prbs180;\n \n integer ii;\n always @(*) begin\n comp0 = 8'hff;\n comp180 = 8'hff;\n prbs0 = 8'hff;\n prbs180 = 8'hff;\n data_bytes_ns = 64'b0;\n prbs_bytes_ns = 64'b0;\n for (ii=0; ii<2*nCK_PER_CLK; ii=ii+1) \n begin\n word = phy_rddata[ii*DQ_WIDTH+:DQ_WIDTH];\n\tword_shifted = word >> oclkdelay_calib_cnt*8;\n\tdata_bytes_ns[ii*8+:8] = word_shifted[7:0];\n\t\n word = prbs_o[ii*DQ_WIDTH+:DQ_WIDTH];\n\tword_shifted = word >> oclkdelay_calib_cnt*8;\n\tprbs_bytes_ns[ii*8+:8] = word_shifted[7:0];\n\t\n\tcomp0[ii] = data_bytes[ii*8+:8] == (ii%2 ? 8'hff : 8'h00);\n\tcomp180[ii] = data_bytes[ii*8+:8] == (ii%2 ? 8'h00 : 8'hff);\n\t\n prbs0[ii] = data_bytes[ii*8+:8] == prbs_bytes_r[ii*8+:8];\n end // for (ii=0; ii<2*nCK_PER_CLK; ii=ii+1)\n prbs180[0] = last_byte_r == prbs_bytes_r[7:0];\n for (ii=1; ii<2*nCK_PER_CLK; ii=ii+1)\n \tprbs180[ii] = data_bytes[(ii-1)*8+:8] == prbs_bytes_r[ii*8+:8];\n if (nCK_PER_CLK == 4) begin\n if (prbs_ignore_last_bytes_r) begin\n prbs0[7:6] = 2'b11;\n\tprbs180[7] = 1'b1;\n end\n if (prbs_ignore_first_byte_r) prbs180[0] = 1'b1;\n end else begin\n if (second_half_r) begin\n if (prbs_ignore_last_bytes_r) begin\n\t prbs0[3:2] = 2'b11;\n\t prbs180[3] = 1'b1;\n\tend\n end else if (prbs_ignore_first_byte_r) prbs180[0] = 1'b1;\n end // else: !if(nCK_PER_CLK == 4)\n end // always @ (*)\n\n wire [7:0] comp0_masked = comp0 | OCAL_DQ_MASK;\n wire [7:0] comp180_masked = comp180 | OCAL_DQ_MASK;\n wire [7:0] prbs0_masked = prbs0 | OCAL_DQ_MASK;\n wire [7:0] prbs180_masked = prbs180 | OCAL_DQ_MASK;\n \n output [1:0] match;\n assign match = complex_oclkdelay_calib_start ? {&prbs180_masked, &prbs0_masked} : {&comp180_masked , &comp0_masked};\n\n\nendmodule // mig_7series_v4_0_ddr_phy_ocd_data\n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_edge.v", "content": "//*****************************************************************************\n// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor: Xilinx\n// \\ \\ \\/ Version: %version\n// \\ \\ Application: MIG\n// / / Filename: ddr_phy_v4_0_phy_ocd_edge.v\n// /___/ /\\ Date Last Modified: $Date: 2011/02/25 02:07:40 $\n// \\ \\ / \\ Date Created: Aug 03 2009 \n// \\___\\/\\___\\\n//\n//Device: 7 Series\n//Design Name: DDR3 SDRAM\n//Purpose: Detects and stores edges as the test pattern is scanned via\n// manipulating the phaser out stage 3 taps.\n//\n// Scanning always proceeds from the left to the right. For more\n// on the scanning algorithm, see the _po_cntlr block.\n//\n// Four scan results are reported. The edges at fuzz2zero, \n// zero2fuzz, fuzz2oneeighty, and oneeighty2fuzz. Each edge\n// has a 6 bit stg3 tap value and a valid bit. The valid bits\n// are reset before the scan starts.\n//\n// Once reset_scan is set low, this block waits for the first\n// samp_done while scanning_right. This marks the left end\n// of the scan, and initializes prev_samp_r with samp_result and \n// sets the prev_samp_r valid bit to one.\n//\n// At each subesquent samp_done, the previous samp is compared\n// to the current samp_result. The case statement details how\n// edges are identified.\n//\n// Original design assumed fuzz between valid regions. Design\n// has been updated to tolerate transitions from zero to oneeight\n// and vice-versa without fuzz in between.\n//\n//Reference:\n//Revision History:\n//*****************************************************************************\n\n`timescale 1ps/1ps\n\nmodule mig_7series_v4_0_ddr_phy_ocd_edge #\n (parameter TCQ = 100)\n (/*AUTOARG*/\n // Outputs\n scan_right, z2f, f2z, o2f, f2o, zero2fuzz, fuzz2zero,\n oneeighty2fuzz, fuzz2oneeighty,\n // Inputs\n clk, samp_done, phy_rddata_en_2, reset_scan, scanning_right,\n samp_result, stg3\n );\n\n \n localparam [1:0] NULL = 2'b11,\n FUZZ = 2'b00,\n ONEEIGHTY = 2'b10,\n ZERO = 2'b01;\n \n input clk;\n \n input samp_done;\n input phy_rddata_en_2;\n wire samp_valid = samp_done && phy_rddata_en_2;\n \n input reset_scan;\n\n input scanning_right;\n\n reg prev_samp_valid_ns, prev_samp_valid_r;\n always @(posedge clk) prev_samp_valid_r <= #TCQ prev_samp_valid_ns;\n always @(*) begin\n prev_samp_valid_ns = prev_samp_valid_r;\n if (reset_scan) prev_samp_valid_ns = 1'b0;\n else if (samp_valid) prev_samp_valid_ns = 1'b1;\n end\n \n input [1:0] samp_result;\n\n reg [1:0] prev_samp_ns, prev_samp_r;\n always @(posedge clk) prev_samp_r <= #TCQ prev_samp_ns;\n always @(*)\n if (samp_valid) prev_samp_ns = samp_result;\n else prev_samp_ns = prev_samp_r;\n\n reg scan_right_ns, scan_right_r;\n always @(posedge clk) scan_right_r <= #TCQ scan_right_ns;\n output scan_right;\n assign scan_right = scan_right_r;\n\n input [5:0] stg3;\n\n reg z2f_ns, z2f_r, f2z_ns, f2z_r, o2f_ns, o2f_r, f2o_ns, f2o_r;\n always @(posedge clk) z2f_r <= #TCQ z2f_ns;\n always @(posedge clk) f2z_r <= #TCQ f2z_ns;\n always @(posedge clk) o2f_r <= #TCQ o2f_ns;\n always @(posedge clk) f2o_r <= #TCQ f2o_ns;\n\n output z2f, f2z, o2f, f2o;\n assign z2f = z2f_r;\n assign f2z = f2z_r;\n assign o2f = o2f_r;\n assign f2o = f2o_r;\n \n reg [5:0] zero2fuzz_ns, zero2fuzz_r, fuzz2zero_ns, fuzz2zero_r, \n oneeighty2fuzz_ns, oneeighty2fuzz_r, fuzz2oneeighty_ns, fuzz2oneeighty_r;\n always @(posedge clk) zero2fuzz_r <= #TCQ zero2fuzz_ns;\n always @(posedge clk) fuzz2zero_r <= #TCQ fuzz2zero_ns;\n always @(posedge clk) oneeighty2fuzz_r <= #TCQ oneeighty2fuzz_ns;\n always @(posedge clk) fuzz2oneeighty_r <= #TCQ fuzz2oneeighty_ns;\n \n output [5:0] zero2fuzz, fuzz2zero, oneeighty2fuzz, fuzz2oneeighty;\n assign zero2fuzz = zero2fuzz_r;\n assign fuzz2zero = fuzz2zero_r;\n assign oneeighty2fuzz = oneeighty2fuzz_r;\n assign fuzz2oneeighty = fuzz2oneeighty_r;\n \n always @(*) begin\n z2f_ns = z2f_r;\n f2z_ns = f2z_r;\n o2f_ns = o2f_r;\n f2o_ns = f2o_r;\n zero2fuzz_ns = zero2fuzz_r;\n fuzz2zero_ns = fuzz2zero_r;\n oneeighty2fuzz_ns = oneeighty2fuzz_r;\n fuzz2oneeighty_ns = fuzz2oneeighty_r;\n scan_right_ns = 1'b0;\n \n if (reset_scan) begin\n z2f_ns = 1'b0;\n f2z_ns = 1'b0;\n o2f_ns = 1'b0;\n f2o_ns = 1'b0;\n end \n else if (samp_valid && prev_samp_valid_r)\n case (prev_samp_r)\n\tFUZZ :\n\t if (scanning_right) begin\n if (samp_result == ZERO) begin\n\t fuzz2zero_ns = stg3;\n\t f2z_ns = 1'b1;\n\t end\n if (samp_result == ONEEIGHTY) begin\n\t fuzz2oneeighty_ns = stg3;\n\t f2o_ns = 1'b1;\n\t end\n\t end\n\tZERO : begin\n if (samp_result == FUZZ || samp_result == ONEEIGHTY) scan_right_ns = !scanning_right;\n if (scanning_right) begin\n\t if (samp_result == FUZZ) begin\n\t zero2fuzz_ns = stg3 - 6'b1;\n\t z2f_ns = 1'b1;\n\t end\n\t if (samp_result == ONEEIGHTY) begin\n\t zero2fuzz_ns = stg3 - 6'b1;\n\t z2f_ns = 1'b1;\n\t fuzz2oneeighty_ns = stg3;\n\t f2o_ns = 1'b1;\n\t end\n\t end\n\tend\n ONEEIGHTY :\n if (scanning_right) begin\n\t if (samp_result == FUZZ) begin\n\t oneeighty2fuzz_ns = stg3 - 6'b1;\n\t o2f_ns = 1'b1;\n\t end \n if (samp_result == ZERO)\n if (f2o_r) begin\n\t\toneeighty2fuzz_ns = stg3 - 6'b1;\n\t o2f_ns = 1'b1;\n end else begin\n\t fuzz2zero_ns = stg3;\n\t f2z_ns = 1'b1;\n\t end\n\n\t end // if (scanning_right)\n//\tNULL : // Should never happen\n endcase\t \n end\n \nendmodule // mig_7series_v4_0_ddr_phy_ocd_edge\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_lim.v", "content": "//*****************************************************************************\n// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor: Xilinx\n// \\ \\ \\/ Version: %version\n// \\ \\ Application: MIG\n// / / Filename: ddr_phy_oclkdelay_cal.v\n// /___/ /\\ Date Last Modified: $Date: 2011/02/25 02:07:40 $\n// \\ \\ / \\ Date Created: Aug 03 2009 \n// \\___\\/\\___\\\n//\n//Device: 7 Series\n//Design Name: DDR3 SDRAM\n//Purpose: Center write DQS in write DQ valid window using Phaser_Out Stage3\n// delay\n//Reference:\n//Revision History:\n//*****************************************************************************\n\n`timescale 1ps/1ps\n\nmodule mig_7series_v4_0_ddr_phy_ocd_lim #\n (parameter TAPCNTRWIDTH = 7,\n parameter DQS_CNT_WIDTH = 3,\n parameter DQS_WIDTH = 9,\n parameter TCQ = 100,\n parameter TAPSPERKCLK = 56,\n parameter TDQSS_DEGREES = 60,\n parameter BYPASS_COMPLEX_OCAL = \"FALSE\")\n (/*AUTOARG*/\n // Outputs\n lim2init_write_request, lim2init_prech_req, lim2poc_rdy, lim2poc_ktap_right,\n lim2stg3_inc, lim2stg3_dec, lim2stg2_inc, lim2stg2_dec, lim_done,\n lim2ocal_stg3_right_lim, lim2ocal_stg3_left_lim, dbg_ocd_lim,\n // Inputs\n clk, rst, lim_start, po_rdy, poc2lim_rise_align_taps_lead,\n poc2lim_rise_align_taps_trail, poc2lim_fall_align_taps_lead,\n poc2lim_fall_align_taps_trail, oclkdelay_init_val, wl_po_fine_cnt,\n simp_stg3_final_sel, oclkdelay_calib_done, poc2lim_detect_done,\n prech_done, oclkdelay_calib_cnt\n );\n \n function [TAPCNTRWIDTH:0] mod_sub (input [TAPCNTRWIDTH-1:0] a, \n input [TAPCNTRWIDTH-1:0] b, \n input integer base); \n begin\n mod_sub = (a>=b) ? a-b : a+base[TAPCNTRWIDTH-1:0]-b;\n end\n endfunction // mod_sub\n\n input clk;\n input rst;\n\n input lim_start;\n input po_rdy;\n input [TAPCNTRWIDTH-1:0] poc2lim_rise_align_taps_lead;\n input [TAPCNTRWIDTH-1:0] poc2lim_rise_align_taps_trail;\n input [TAPCNTRWIDTH-1:0] poc2lim_fall_align_taps_lead;\n input [TAPCNTRWIDTH-1:0] poc2lim_fall_align_taps_trail;\n input [5:0] oclkdelay_init_val;\n input [5:0] wl_po_fine_cnt;\n input [5:0] simp_stg3_final_sel;\n input oclkdelay_calib_done;\n input poc2lim_detect_done;\n input prech_done;\n input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;\n \n \n output lim2init_write_request;\n output lim2init_prech_req;\n output lim2poc_rdy;\n output lim2poc_ktap_right; // I think this can be defaulted.\n output lim2stg3_inc;\n output lim2stg3_dec;\n output lim2stg2_inc;\n output lim2stg2_dec;\n output lim_done;\n output [5:0] lim2ocal_stg3_right_lim;\n output [5:0] lim2ocal_stg3_left_lim;\n output [255:0] dbg_ocd_lim; \n \n // Stage 3 taps can move an additional + or - 60 degrees from the write level position\n // Convert 60 degrees to MMCM taps. 360/60=6.\n //localparam real DIV_FACTOR = 360/TDQSS_DEGREES;\n //localparam real TDQSS_LIM_MMCM_TAPS = TAPSPERKCLK/DIV_FACTOR;\n localparam DIV_FACTOR = 360/TDQSS_DEGREES;\n localparam TDQSS_LIM_MMCM_TAPS = TAPSPERKCLK/DIV_FACTOR;\n localparam WAIT_CNT = 15;\n \n localparam IDLE = 14'b00_0000_0000_0001;\n localparam INIT = 14'b00_0000_0000_0010;\n localparam WAIT_WR_REQ = 14'b00_0000_0000_0100;\n localparam WAIT_POC_DONE = 14'b00_0000_0000_1000;\n localparam WAIT_STG3 = 14'b00_0000_0001_0000;\n localparam STAGE3_INC = 14'b00_0000_0010_0000;\n localparam STAGE3_DEC = 14'b00_0000_0100_0000;\n localparam STAGE2_INC = 14'b00_0000_1000_0000;\n localparam STAGE2_DEC = 14'b00_0001_0000_0000;\n localparam STG3_INCDEC_WAIT = 14'b00_0010_0000_0000;\n localparam STG2_INCDEC_WAIT = 14'b00_0100_0000_0000;\n localparam STAGE2_TAP_CHK = 14'b00_1000_0000_0000;\n localparam PRECH_REQUEST = 14'b01_0000_0000_0000;\n localparam LIMIT_DONE = 14'b10_0000_0000_0000;\n\n// Flip-flops \n reg [5:0] stg3_init_val;\n reg [13:0] lim_state;\n reg lim_start_r;\n reg ktap_right_r;\n reg write_request_r;\n reg prech_req_r;\n reg poc_ready_r;\n reg wait_cnt_en_r;\n reg wait_cnt_done;\n reg [3:0] wait_cnt_r;\n reg [5:0] stg3_tap_cnt;\n reg [5:0] stg2_tap_cnt;\n reg [5:0] stg3_left_lim;\n reg [5:0] stg3_right_lim;\n reg [DQS_WIDTH*6-1:0] cmplx_stg3_left_lim;\n reg [DQS_WIDTH*6-1:0] simp_stg3_left_lim;\n reg [DQS_WIDTH*6-1:0] cmplx_stg3_right_lim;\n reg [DQS_WIDTH*6-1:0] simp_stg3_right_lim;\n reg [5:0] stg3_dec_val;\n reg [5:0] stg3_inc_val;\n reg detect_done_r;\n reg stg3_dec_r;\n reg stg2_inc_r;\n reg stg3_inc2init_val_r;\n reg stg3_inc2init_val_r1;\n reg stg3_dec2init_val_r;\n reg stg3_dec2init_val_r1;\n reg stg3_dec_req_r;\n reg stg3_inc_req_r;\n reg stg2_dec_req_r;\n reg stg2_inc_req_r;\n reg stg3_init_dec_r;\n reg [TAPCNTRWIDTH:0] mmcm_current;\n reg [TAPCNTRWIDTH:0] mmcm_init_trail;\n reg [TAPCNTRWIDTH:0] mmcm_init_lead;\n reg done_r;\n \n reg [13:0] lim_nxt_state;\n reg ktap_right;\n reg write_request;\n reg prech_req;\n reg poc_ready;\n reg stg3_dec;\n reg stg2_inc;\n reg stg3_inc2init_val;\n reg stg3_dec2init_val;\n reg stg3_dec_req;\n reg stg3_inc_req;\n reg stg2_dec_req;\n reg stg2_inc_req;\n reg stg3_init_dec;\n reg done;\n reg oclkdelay_calib_done_r;\n \n wire [TAPCNTRWIDTH:0] mmcm_sub_dec = mod_sub (mmcm_init_trail, mmcm_current, TAPSPERKCLK);\n wire [TAPCNTRWIDTH:0] mmcm_sub_inc = mod_sub (mmcm_current, mmcm_init_lead, TAPSPERKCLK);\n \n /***************************************************************************/\n // Debug signals\n /***************************************************************************/\n \n assign dbg_ocd_lim[0+:DQS_WIDTH*6] = simp_stg3_left_lim[DQS_WIDTH*6-1:0];\n assign dbg_ocd_lim[54+:DQS_WIDTH*6] = simp_stg3_right_lim[DQS_WIDTH*6-1:0];\n assign dbg_ocd_lim[255:108] = 'd0;\n\n \n \n \n assign lim2init_write_request = write_request_r;\n assign lim2init_prech_req = prech_req_r;\n assign lim2poc_ktap_right = ktap_right_r;\n assign lim2poc_rdy = poc_ready_r;\n assign lim2ocal_stg3_left_lim = stg3_left_lim;\n assign lim2ocal_stg3_right_lim = stg3_right_lim;\n assign lim2stg3_dec = stg3_dec_req_r;\n assign lim2stg3_inc = stg3_inc_req_r;\n assign lim2stg2_dec = stg2_dec_req_r;\n assign lim2stg2_inc = stg2_inc_req_r;\n assign lim_done = done_r;\n \n\n/**************************Wait Counter Start*********************************/\n// Wait counter enable for wait states WAIT_WR_REQ and WAIT_STG3\n// To avoid DQS toggling when stage2 and 3 taps are moving \n always @(posedge clk) begin\n if ((lim_state == WAIT_WR_REQ) ||\n (lim_state == WAIT_STG3) ||\n\t\t(lim_state == INIT))\n wait_cnt_en_r <= #TCQ 1'b1;\n else\n wait_cnt_en_r <= #TCQ 1'b0;\n end\n\n// Wait counter for wait states WAIT_WR_REQ and WAIT_STG3\n// To avoid DQS toggling when stage2 and 3 taps are moving \n always @(posedge clk) begin\n if (!wait_cnt_en_r) begin\n wait_cnt_r <= #TCQ 'b0;\n wait_cnt_done <= #TCQ 1'b0;\n end else begin\n if (wait_cnt_r != WAIT_CNT - 1) begin\n wait_cnt_r <= #TCQ wait_cnt_r + 1;\n wait_cnt_done <= #TCQ 1'b0;\n end else begin\n wait_cnt_r <= #TCQ 'b0; \n wait_cnt_done <= #TCQ 1'b1;\n end\n end\n end\n/**************************Wait Counter End***********************************/\n \n// Flip-flops\n\n always @(posedge clk) begin\n if (rst)\n oclkdelay_calib_done_r <= #TCQ 1'b0;\n else\n oclkdelay_calib_done_r <= #TCQ oclkdelay_calib_done;\n end\n\n always @(posedge clk) begin\n if (rst)\n\t stg3_init_val <= #TCQ oclkdelay_init_val;\n\telse if (oclkdelay_calib_done)\n\t stg3_init_val <= #TCQ simp_stg3_final_sel;\n\telse\n\t stg3_init_val <= #TCQ oclkdelay_init_val;\n end\n\n always @(posedge clk) begin\n if (rst) begin\n\t lim_state <= #TCQ IDLE;\n\t lim_start_r <= #TCQ 1'b0;\n\t ktap_right_r <= #TCQ 1'b0;\n\t write_request_r <= #TCQ 1'b0;\n\t prech_req_r <= #TCQ 1'b0;\n\t poc_ready_r <= #TCQ 1'b0;\n\t detect_done_r <= #TCQ 1'b0;\n\t stg3_dec_r <= #TCQ 1'b0;\n\t stg2_inc_r <= #TCQ 1'b0;\n\t stg3_inc2init_val_r <= #TCQ 1'b0;\n\t stg3_inc2init_val_r1<= #TCQ 1'b0;\n\t stg3_dec2init_val_r <= #TCQ 1'b0;\n\t stg3_dec2init_val_r1<= #TCQ 1'b0;\n\t stg3_dec_req_r <= #TCQ 1'b0;\n\t stg3_inc_req_r <= #TCQ 1'b0;\n\t stg2_dec_req_r <= #TCQ 1'b0;\n\t stg2_inc_req_r <= #TCQ 1'b0;\n\t done_r <= #TCQ 1'b0;\n\t stg3_dec_val <= #TCQ 'd0;\n\t stg3_inc_val <= #TCQ 'd0;\n\t stg3_init_dec_r <= #TCQ 1'b0;\n\tend else begin\n\t lim_state <= #TCQ lim_nxt_state;\n\t lim_start_r <= #TCQ lim_start;\n\t ktap_right_r <= #TCQ ktap_right;\n\t write_request_r <= #TCQ write_request;\n\t prech_req_r <= #TCQ prech_req;\n\t poc_ready_r <= #TCQ poc_ready;\n\t detect_done_r <= #TCQ poc2lim_detect_done;\n\t stg3_dec_r <= #TCQ stg3_dec;\n\t stg2_inc_r <= #TCQ stg2_inc;\n\t stg3_inc2init_val_r <= #TCQ stg3_inc2init_val;\n\t stg3_inc2init_val_r1<= #TCQ stg3_inc2init_val_r;\n\t stg3_dec2init_val_r <= #TCQ stg3_dec2init_val;\n\t stg3_dec2init_val_r1<= #TCQ stg3_dec2init_val_r;\n\t stg3_dec_req_r <= #TCQ stg3_dec_req;\n\t stg3_inc_req_r <= #TCQ stg3_inc_req;\n\t stg2_dec_req_r <= #TCQ stg2_dec_req;\n\t stg2_inc_req_r <= #TCQ stg2_inc_req;\n\t stg3_init_dec_r <= #TCQ stg3_init_dec;\n\t done_r <= #TCQ done;\n\t if (stg3_init_val > (('d63 - wl_po_fine_cnt)/2))\n\t stg3_dec_val <= #TCQ (stg3_init_val - ('d63 - wl_po_fine_cnt)/2);\n\t else\n\t stg3_dec_val <= #TCQ 'd0;\n\t if (stg3_init_val < 'd63 - ((wl_po_fine_cnt)/2))\n\t stg3_inc_val <= #TCQ (stg3_init_val + (wl_po_fine_cnt)/2);\n\t else\n\t stg3_inc_val <= #TCQ 'd63;\n\tend\n end\n\n// Keeping track of stage 3 tap count \n always @(posedge clk) begin\n if (rst)\n\t stg3_tap_cnt <= #TCQ stg3_init_val;\n\telse if ((lim_state == IDLE) || (lim_state == INIT))\n\t stg3_tap_cnt <= #TCQ stg3_init_val;\n\telse if (lim_state == STAGE3_INC)\n\t stg3_tap_cnt <= #TCQ stg3_tap_cnt + 1;\n\telse if (lim_state == STAGE3_DEC)\n\t stg3_tap_cnt <= #TCQ stg3_tap_cnt - 1;\n end\n \n// Keeping track of stage 2 tap count \n always @(posedge clk) begin\n if (rst)\n\t stg2_tap_cnt <= #TCQ 'd0;\n\telse if ((lim_state == IDLE) || (lim_state == INIT))\n\t stg2_tap_cnt <= #TCQ wl_po_fine_cnt;\n\telse if (lim_state == STAGE2_INC)\n\t stg2_tap_cnt <= #TCQ stg2_tap_cnt + 1;\n\telse if (lim_state == STAGE2_DEC)\n\t stg2_tap_cnt <= #TCQ stg2_tap_cnt - 1;\n end\n \n// Keeping track of MMCM tap count\n always @(posedge clk) begin\n if (rst) begin\n\t mmcm_init_trail <= #TCQ 'd0;\n\t mmcm_init_lead <= #TCQ 'd0;\n\tend else if (poc2lim_detect_done && !detect_done_r) begin\n\t if (stg3_tap_cnt == stg3_dec_val)\n\t mmcm_init_trail <= #TCQ poc2lim_rise_align_taps_trail;\n\t if (stg3_tap_cnt == stg3_inc_val)\n\t mmcm_init_lead <= #TCQ poc2lim_rise_align_taps_lead;\n\tend \n end\n \n always @(posedge clk) begin\n if (rst) begin\n\t mmcm_current <= #TCQ 'd0;\n\tend else if (stg3_dec_r) begin\n\t if (stg3_tap_cnt == stg3_dec_val)\n\t mmcm_current <= #TCQ mmcm_init_trail;\n\t else\n\t mmcm_current <= #TCQ poc2lim_rise_align_taps_lead;\n\tend else begin\n\t if (stg3_tap_cnt == stg3_inc_val)\n\t mmcm_current <= #TCQ mmcm_init_lead;\n\t else\n\t mmcm_current <= #TCQ poc2lim_rise_align_taps_trail;\n\tend \n end\n\n// Record Stage3 Left Limit\n always @(posedge clk) begin\n if (rst) begin\n\t stg3_left_lim <= #TCQ 'd0;\n\t simp_stg3_left_lim <= #TCQ 'd0;\n\t cmplx_stg3_left_lim <= #TCQ 'd0;\n\tend else if (stg3_inc2init_val_r && !stg3_inc2init_val_r1) begin\n\t stg3_left_lim <= #TCQ stg3_tap_cnt;\n\t if (oclkdelay_calib_done)\n\t cmplx_stg3_left_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt;\n\t else\n\t simp_stg3_left_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt;\n\tend else if (lim_start && !lim_start_r)\n\t stg3_left_lim <= #TCQ 'd0;\n end\n\n// Record Stage3 Right Limit\n always @(posedge clk) begin\n if (rst) begin\n\t stg3_right_lim <= #TCQ 'd0;\n\t cmplx_stg3_right_lim <= #TCQ 'd0;\n\t simp_stg3_right_lim <= #TCQ 'd0;\n\tend else if (stg3_dec2init_val_r && !stg3_dec2init_val_r1) begin\n\t stg3_right_lim <= #TCQ stg3_tap_cnt;\n\t if (oclkdelay_calib_done)\n\t cmplx_stg3_right_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt;\n\t else\n\t simp_stg3_right_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt;\n\tend else if (lim_start && !lim_start_r)\n\t stg3_right_lim <= #TCQ 'd0;\n end \n \n always @(*) begin\n\t lim_nxt_state = lim_state;\n\t ktap_right = ktap_right_r;\n\t write_request = write_request_r;\n\t prech_req = prech_req_r;\n\t poc_ready = poc_ready_r;\n\t stg3_dec = stg3_dec_r;\n\t stg2_inc = stg2_inc_r;\n\t stg3_inc2init_val = stg3_inc2init_val_r;\n\t stg3_dec2init_val = stg3_dec2init_val_r;\n\t stg3_dec_req = stg3_dec_req_r;\n\t stg3_inc_req = stg3_inc_req_r;\n\t stg2_inc_req = stg2_inc_req_r;\n\t stg2_dec_req = stg2_dec_req_r;\n\t stg3_init_dec = stg3_init_dec_r;\n\t done = done_r;\n\n\t\n\t case(lim_state)\n\t IDLE: begin\n\t if (lim_start && !lim_start_r) begin\n lim_nxt_state = INIT;\n stg3_dec = 1'b1;\n stg2_inc = 1'b1;\n stg3_init_dec = 1'b1;\n done = 1'b0;\n\t end\n\t //New start of limit module for complex oclkdelay calib\n else if (oclkdelay_calib_done && !oclkdelay_calib_done_r && (BYPASS_COMPLEX_OCAL == \"FALSE\")) begin\n done = 1'b0;\n end\n\t end\n\t INIT: begin\n\t ktap_right = 1'b1;\n\t\t // Initial stage 2 increment to 63 for left limit\n\t\t if (wait_cnt_done)\n \t lim_nxt_state = STAGE2_TAP_CHK;\n\t end\n\t // Wait for DQS to toggle before asserting poc_ready\n\t WAIT_WR_REQ: begin\n\t write_request = 1'b1;\n\t if (wait_cnt_done) begin\n\t \t poc_ready = 1'b1;\n\t \t lim_nxt_state = WAIT_POC_DONE;\n\t \t end\n\t end\n\t // Wait for POC detect done signal\n\t WAIT_POC_DONE: begin\n\t \t if (poc2lim_detect_done) begin\n\t \t write_request = 1'b0;\n\t\t\tpoc_ready = 1'b0;\n\t \t lim_nxt_state = WAIT_STG3;\n\t \t end\n\t end\n\t // Wait for DQS to stop toggling before stage3 inc/dec\n\t WAIT_STG3: begin\n\t if (wait_cnt_done) begin\n\t \t if (stg3_dec_r) begin\n\t \t // Check for Stage 3 underflow and MMCM tap limit\n\t \t if ((stg3_tap_cnt > 'd0) && (mmcm_sub_dec < TDQSS_LIM_MMCM_TAPS))\n\t \t lim_nxt_state = STAGE3_DEC;\n\t \t\t else begin\n\t \t\t stg3_dec = 1'b0;\n\t \t\t stg3_inc2init_val = 1'b1;\n\t \t\t lim_nxt_state = STAGE3_INC;\n\t \t\t end\n\t \t end else begin // Stage 3 being incremented\n\t \t // Check for Stage 3 overflow and MMCM tap limit\n\t \t if ((stg3_tap_cnt < 'd63) && (mmcm_sub_inc < TDQSS_LIM_MMCM_TAPS))\n\t \t lim_nxt_state = STAGE3_INC;\n\t \t\t else begin\n\t \t\t stg3_dec2init_val = 1'b1;\n lim_nxt_state = STAGE3_DEC;\n end\n end\t\t\t\n\t \t end\n\t end\n\t STAGE3_INC: begin\n\t stg3_inc_req = 1'b1;\n\t \t lim_nxt_state = STG3_INCDEC_WAIT;\n\t end\n\t STAGE3_DEC: begin\n\t stg3_dec_req = 1'b1; \n\t \t lim_nxt_state = STG3_INCDEC_WAIT;\n\t end\n\t // Wait for stage3 inc/dec to complete (po_rdy)\n\t STG3_INCDEC_WAIT: begin\n\t stg3_dec_req = 1'b0;\n\t \t stg3_inc_req = 1'b0;\n\t if (!stg3_dec_req_r && !stg3_inc_req_r && po_rdy) begin\n\t\t if (stg3_init_dec_r) begin\n\t\t\t // Initial decrement of stage 3\n\t\t\t if (stg3_tap_cnt > stg3_dec_val)\n\t\t\t lim_nxt_state = STAGE3_DEC;\n\t\t\t else begin\n\t\t\t lim_nxt_state = WAIT_WR_REQ;\n\t\t\t\tstg3_init_dec = 1'b0;\n\t\t\t end\n\t end else if (stg3_dec2init_val_r) begin \n\t\t\t if (stg3_tap_cnt > stg3_init_val)\n\t \t lim_nxt_state = STAGE3_DEC;\n\t\t\t else\n\t\t\t lim_nxt_state = STAGE2_TAP_CHK;\n\t \t end else if (stg3_inc2init_val_r) begin\n\t\t\t if (stg3_tap_cnt < stg3_inc_val)\n\t \t lim_nxt_state = STAGE3_INC;\n\t\t\t else\n\t\t\t lim_nxt_state = STAGE2_TAP_CHK;\n\t \t end else begin\n\t \t lim_nxt_state = WAIT_WR_REQ;\n\t\t\tend\n\t \t end\n\t end\n\t // Check for overflow and underflow of stage2 taps\n\t STAGE2_TAP_CHK: begin\n\t if (stg3_dec2init_val_r) begin\n\t\t // Increment stage 2 to write level tap value at the end of limit detection\n\t \t if (stg2_tap_cnt < wl_po_fine_cnt)\n\t \t lim_nxt_state = STAGE2_INC;\n\t else begin\n\t lim_nxt_state = PRECH_REQUEST;\t \t\t \n\t \t end\n\t \t end else if (stg3_inc2init_val_r) begin\n\t\t // Decrement stage 2 to '0' to determine right limit\n\t \t if (stg2_tap_cnt > 'd0)\n\t \t lim_nxt_state = STAGE2_DEC;\n\t \t else begin\n\t \t lim_nxt_state = PRECH_REQUEST;\n\t \t\t stg3_inc2init_val = 1'b0;\n\t \t end\n\t\t end else if (stg2_inc_r && (stg2_tap_cnt < 'd63)) begin\n\t\t // Initial increment to 63\n\t \t lim_nxt_state = STAGE2_INC;\n end else begin\n lim_nxt_state = STG3_INCDEC_WAIT;\n\t\t\tstg2_inc = 1'b0;\n\t\t end\n\t end\n\t STAGE2_INC: begin\n\t stg2_inc_req = 1'b1;\n\t \t lim_nxt_state = STG2_INCDEC_WAIT;\n\t end\n\t STAGE2_DEC: begin\n\t stg2_dec_req = 1'b1;\n\t \t lim_nxt_state = STG2_INCDEC_WAIT;\n\t end\n\t // Wait for stage3 inc/dec to complete (po_rdy)\n\t STG2_INCDEC_WAIT: begin\n\t stg2_inc_req = 1'b0;\n\t \t stg2_dec_req = 1'b0;\n\t \t if (!stg2_inc_req_r && !stg2_dec_req_r && po_rdy)\n\t \t lim_nxt_state = STAGE2_TAP_CHK;\n\t end\n\t\tPRECH_REQUEST: begin\n\t\t prech_req = 1'b1;\n\t\t if (prech_done) begin\n\t\t prech_req = 1'b0;\n\t\t if (stg3_dec2init_val_r)\n\t\t\t lim_nxt_state = LIMIT_DONE;\n\t\t\telse\n\t\t lim_nxt_state = WAIT_WR_REQ;\n\t\t end\n\t\tend\n\t LIMIT_DONE: begin\n\t done = 1'b1;\n\t \t ktap_right = 1'b0;\n\t\t stg3_dec2init_val = 1'b0;\n\t\t lim_nxt_state = IDLE;\n\t end\n\t default: begin\n\t lim_nxt_state = IDLE;\n\t end\n\t endcase\n end\n \n\nendmodule //mig_7_series_v4_0_ddr_phy_ocd_lim\n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_mux.v", "content": "//*****************************************************************************\n// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor: Xilinx\n// \\ \\ \\/ Version: %version\n// \\ \\ Application: MIG\n// / / Filename: ddr_phy_v4_0_phy_ocd_mux.v\n// /___/ /\\ Date Last Modified: $Date: 2011/02/25 02:07:40 $\n// \\ \\ / \\ Date Created: Aug 03 2009 \n// \\___\\/\\___\\\n//\n//Device: 7 Series\n//Design Name: DDR3 SDRAM\n//Purpose: The limit block and the _po_cntlr block both manipulate\n// the phaser out and the POC. This block muxes those commands\n// together, and encapsulates logic required for meeting phaser\n// setup and wait times.\n// \n//Reference:\n//Revision History:\n//*****************************************************************************\n\n`timescale 1ps/1ps\n\nmodule mig_7series_v4_0_ddr_phy_ocd_mux #\n (parameter DQS_CNT_WIDTH = 3,\n parameter DQS_WIDTH = 8,\n parameter TCQ = 100)\n (/*AUTOARG*/\n // Outputs\n ktap_at_left_edge, ktap_at_right_edge, mmcm_edge_detect_rdy,\n po_stg3_incdec, po_en_stg3, po_en_stg23, po_stg23_sel,\n po_stg23_incdec, po_rdy, wl_po_fine_cnt_sel, oclk_prech_req,\n // Inputs\n clk, rst, ocd_ktap_right, ocd_ktap_left, lim2poc_ktap_right,\n lim2poc_rdy, ocd_edge_detect_rdy, lim2stg2_inc, lim2stg2_dec,\n lim2stg3_inc, lim2stg3_dec, ocd2stg2_inc, ocd2stg2_dec,\n ocd_cntlr2stg2_dec, ocd2stg3_inc, ocd2stg3_dec, wl_po_fine_cnt,\n oclkdelay_calib_cnt, lim2init_prech_req, ocd_prech_req\n );\n\n function integer clogb2 (input integer size); // ceiling logb2\n begin\n size = size - 1;\n for (clogb2=1; size>1; clogb2=clogb2+1)\n size = size >> 1;\n end\n endfunction // clogb2\n\n localparam PO_WAIT = 15;\n localparam POW_WIDTH = clogb2(PO_WAIT);\n localparam ONE = 1;\n localparam TWO = 2;\n\n input clk;\n input rst;\n\n input ocd_ktap_right, ocd_ktap_left;\n input lim2poc_ktap_right;\n output ktap_at_left_edge, ktap_at_right_edge;\n assign ktap_at_left_edge = ocd_ktap_left;\n assign ktap_at_right_edge = lim2poc_ktap_right || ocd_ktap_right;\n \n input lim2poc_rdy;\n input ocd_edge_detect_rdy;\n output mmcm_edge_detect_rdy;\n assign mmcm_edge_detect_rdy = lim2poc_rdy || ocd_edge_detect_rdy;\n \n // po_stg3_incdec and po_en_stg3 are deprecated and should be removed.\n output po_stg3_incdec;\n output po_en_stg3;\n assign po_stg3_incdec = 1'b0;\n assign po_en_stg3 = 1'b0;\n\n\n reg [1:0] po_setup_ns, po_setup_r;\n always @(posedge clk) po_setup_r <= #TCQ po_setup_ns;\n\n input lim2stg2_inc;\n input lim2stg2_dec;\n\n input lim2stg3_inc;\n input lim2stg3_dec;\n\n input ocd2stg2_inc;\n input ocd2stg2_dec;\n input ocd_cntlr2stg2_dec;\n \n input ocd2stg3_inc;\n input ocd2stg3_dec;\n\n wire setup_po = \n lim2stg2_inc || lim2stg2_dec || lim2stg3_inc || lim2stg3_dec ||\n ocd2stg2_inc || ocd2stg2_dec || ocd2stg3_inc || ocd2stg3_dec || ocd_cntlr2stg2_dec;\n\n always @(*) begin\n po_setup_ns = po_setup_r;\n if (rst) po_setup_ns = 2'b00;\n else if (setup_po) po_setup_ns = 2'b11;\n else if (|po_setup_r) po_setup_ns = po_setup_r - 2'b01;\n end\n\n reg po_en_stg23_r;\n wire po_en_stg23_ns = ~rst && po_setup_r == 2'b01;\n always @(posedge clk) po_en_stg23_r <= #TCQ po_en_stg23_ns;\n output po_en_stg23;\n assign po_en_stg23 = po_en_stg23_r; \n\n wire sel_stg3 = lim2stg3_inc || lim2stg3_dec || ocd2stg3_inc || ocd2stg3_dec;\n\n reg [POW_WIDTH-1:0] po_wait_r, po_wait_ns;\n reg po_stg23_sel_r;\n // Reset to zero at the end. Makes adjust stg2 at end of centering\n // get the correct value of po_counter_read_val.\n wire po_stg23_sel_ns = ~rst && (setup_po \n ? sel_stg3\n ? 1'b1 \n : 1'b0 \n : po_stg23_sel_r && !(po_wait_r == ONE[POW_WIDTH-1:0]));\n always @(posedge clk) po_stg23_sel_r <= #TCQ po_stg23_sel_ns;\n output po_stg23_sel;\n assign po_stg23_sel = po_stg23_sel_r;\n\n wire po_inc = lim2stg2_inc || lim2stg3_inc || ocd2stg2_inc || ocd2stg3_inc;\n\n reg po_stg23_incdec_r;\n wire po_stg23_incdec_ns = ~rst && (setup_po ? po_inc ? 1'b1 : 1'b0 : po_stg23_incdec_r);\n always @(posedge clk) po_stg23_incdec_r <= #TCQ po_stg23_incdec_ns;\n output po_stg23_incdec;\n assign po_stg23_incdec = po_stg23_incdec_r;\n\n\n always @(posedge clk) po_wait_r <= #TCQ po_wait_ns;\n always @(*) begin\n po_wait_ns = po_wait_r;\n if (rst) po_wait_ns = {POW_WIDTH{1'b0}};\n else if (po_en_stg23_r) po_wait_ns = PO_WAIT[POW_WIDTH-1:0] - ONE[POW_WIDTH-1:0];\n else if (po_wait_r != {POW_WIDTH{1'b0}}) po_wait_ns = po_wait_r - ONE[POW_WIDTH-1:0];\t \n end\n \n wire po_rdy_ns = ~(setup_po || |po_setup_r || |po_wait_ns);\n reg po_rdy_r;\n always @(posedge clk) po_rdy_r <= #TCQ po_rdy_ns;\n \n output po_rdy;\n assign po_rdy = po_rdy_r;\n\n input [6*DQS_WIDTH-1:0] wl_po_fine_cnt;\n input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;\n wire [6*DQS_WIDTH-1:0] wl_po_fine_shifted = wl_po_fine_cnt >> oclkdelay_calib_cnt*6;\n output [5:0] wl_po_fine_cnt_sel;\n assign wl_po_fine_cnt_sel = wl_po_fine_shifted[5:0];\n\n input lim2init_prech_req;\n input ocd_prech_req;\n output oclk_prech_req;\n assign oclk_prech_req = ocd_prech_req || lim2init_prech_req;\n\t\nendmodule // mig_7series_v4_0_ddr_phy_ocd_mux\n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v", "content": "\n//*****************************************************************************\n// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor: Xilinx\n// \\ \\ \\/ Version: %version\n// \\ \\ Application: MIG\n// / / Filename: ddr_phy_v4_0_phy_ocd_po_cntlr.v\n// /___/ /\\ Date Last Modified: $Date: 2011/02/25 02:07:40 $\n// \\ \\ / \\ Date Created: Aug 03 2009 \n// \\___\\/\\___\\\n//\n//Device: 7 Series\n//Design Name: DDR3 SDRAM\n//Purpose: Manipulates phaser out stg2f and stg3 on behalf of\n// scan and DQS centering.\n//\n// Maintains a shadow of the phaser out stg2f and stg3 tap settings.\n// The stg3 shadow is 6 bits, just like the phaser out. stg2f is\n// 8 bits. This allows the po_cntlr to track how far past the stg2f\n// saturation points we have gone when stepping to the limits of stg3.\n// This way we're can stay in sync when we step back from the saturation\n// limits.\n//\n// Looks at the edge values and determines which case has been\n// detected by the scan. Uses the results to drive the centering.\n//\n// Main state machine waits until it sees reset_scan go to zero. While\n// waiting it is writing the initialzation values to the stg2 and stg3\n// shadows. When reset_scan goes low, taps_set is pulsed. This\n// tells the sampling block to begin sampling. When the sampling\n// block has finished sampling this setting of the phaser out taps,\n// is signals by setting samp_done. When the main state machine\n// sees samp_done it sets the next value in the phaser out and\n// waits for the phaser out to be ready before beginning the next\n// sample.\n//\n// Turns out phy_init is sensitive to the length of the ocal_num_samples_done\n// pulse. Something like a precharge and activate time. Added feature\n// to resume_wait to wait at least 32 cycles between assertion and\n// subsequent deassertion of ocal_num_samples_done.\n//\n// Also turns out phy_init needs help to get into consistent\n// starting state for complex cal. This can be done by preseting\n// ocal_num_samples_done to one. Then waiting for 32 fabric clocks,\n// turn off _done and then assert _resume.\n//\n// Scanning algorithm.\n//\n// Phaser manipulation algoritm.\n// \n//Reference:\n//Revision History:\n//*****************************************************************************\n\n`timescale 1ps/1ps\n\nmodule mig_7series_v4_0_ddr_phy_ocd_po_cntlr #\n (parameter DQS_CNT_WIDTH = 3,\n parameter DQS_WIDTH = 8,\n parameter nCK_PER_CLK = 4,\n parameter SAMPLES = 128,\n parameter TCQ = 100)\n (/*AUTOARG*/\n // Outputs\n scan_done, ocal_num_samples_done_r, oclkdelay_center_calib_start,\n oclkdelay_center_calib_done, oclk_center_write_resume, ocd2stg2_inc,\n ocd2stg2_dec, ocd2stg3_inc, ocd2stg3_dec, stg3, simp_stg3_final,\n cmplx_stg3_final, simp_stg3_final_sel, ninety_offsets,\n scanning_right, ocd_ktap_left, ocd_ktap_right, ocd_edge_detect_rdy,\n taps_set, use_noise_window, ocal_scan_win_not_found,\n // Inputs\n clk, rst, reset_scan, oclkdelay_init_val, lim2ocal_stg3_right_lim,\n lim2ocal_stg3_left_lim, complex_oclkdelay_calib_start,\n po_counter_read_val, oclkdelay_calib_cnt, mmcm_edge_detect_done,\n mmcm_lbclk_edge_aligned, poc_backup, phy_rddata_en_3, zero2fuzz,\n fuzz2zero, oneeighty2fuzz, fuzz2oneeighty, z2f, f2z, o2f, f2o,\n scan_right, samp_done, wl_po_fine_cnt_sel, po_rdy\n );\n\n function integer clogb2 (input integer size); // ceiling logb2\n begin\n size = size - 1;\n for (clogb2=1; size>1; clogb2=clogb2+1)\n size = size >> 1;\n end\n endfunction // clogb2\n \n input clk;\n input rst;\n \n input reset_scan;\n reg scan_done_r;\n output scan_done;\n assign scan_done = scan_done_r;\n output [5:0] simp_stg3_final_sel;\n\n reg cmplx_samples_done_ns, cmplx_samples_done_r;\n always @(posedge clk) cmplx_samples_done_r <= #TCQ cmplx_samples_done_ns;\n output ocal_num_samples_done_r;\n assign ocal_num_samples_done_r = cmplx_samples_done_r;\n\n // Write Level signals during OCLKDELAY calibration\n input [5:0] oclkdelay_init_val;\n input [5:0] lim2ocal_stg3_right_lim;\n input [5:0] lim2ocal_stg3_left_lim;\n\n input complex_oclkdelay_calib_start;\n\n reg oclkdelay_center_calib_start_ns, oclkdelay_center_calib_start_r;\n always @(posedge clk) oclkdelay_center_calib_start_r <= #TCQ oclkdelay_center_calib_start_ns;\n output oclkdelay_center_calib_start;\n assign oclkdelay_center_calib_start = oclkdelay_center_calib_start_r;\n\n reg oclkdelay_center_calib_done_ns, oclkdelay_center_calib_done_r;\n always @(posedge clk) oclkdelay_center_calib_done_r <= #TCQ oclkdelay_center_calib_done_ns;\n output oclkdelay_center_calib_done;\n assign oclkdelay_center_calib_done = oclkdelay_center_calib_done_r;\n\n reg oclk_center_write_resume_ns, oclk_center_write_resume_r;\n always @(posedge clk) oclk_center_write_resume_r <= #TCQ oclk_center_write_resume_ns;\n output oclk_center_write_resume;\n assign oclk_center_write_resume = oclk_center_write_resume_r;\n\n reg ocd2stg2_inc_r, ocd2stg2_dec_r, ocd2stg3_inc_r, ocd2stg3_dec_r;\n output ocd2stg2_inc, ocd2stg2_dec, ocd2stg3_inc, ocd2stg3_dec;\n assign ocd2stg2_inc = ocd2stg2_inc_r;\n assign ocd2stg2_dec = ocd2stg2_dec_r;\n assign ocd2stg3_inc = ocd2stg3_inc_r;\n assign ocd2stg3_dec = ocd2stg3_dec_r;\n\n // Remember, two stage 2 steps for every stg 3 step. And we need a sign bit.\n reg [8:0] stg2_ns, stg2_r;\n always @(posedge clk) stg2_r <= #TCQ stg2_ns;\n \n reg [5:0] stg3_ns, stg3_r;\n always @(posedge clk) stg3_r <= #TCQ stg3_ns;\n output [5:0] stg3;\n assign stg3 = stg3_r;\n\n input [5:0] wl_po_fine_cnt_sel;\n \n input [8:0] po_counter_read_val;\n reg [5:0] po_counter_read_val_r;\n always @(posedge clk) po_counter_read_val_r <= #TCQ po_counter_read_val[5:0];\n\n reg [DQS_WIDTH*6-1:0] simp_stg3_final_ns, simp_stg3_final_r, cmplx_stg3_final_ns, cmplx_stg3_final_r;\n always @(posedge clk) simp_stg3_final_r <= #TCQ simp_stg3_final_ns;\n always @(posedge clk) cmplx_stg3_final_r <= #TCQ cmplx_stg3_final_ns;\n output [DQS_WIDTH*6-1:0] simp_stg3_final, cmplx_stg3_final;\n assign simp_stg3_final = simp_stg3_final_r;\n assign cmplx_stg3_final = cmplx_stg3_final_r;\n \n input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;\n wire [DQS_WIDTH*6-1:0] simp_stg3_final_shft = simp_stg3_final_r >> oclkdelay_calib_cnt * 6;\n assign simp_stg3_final_sel = simp_stg3_final_shft[5:0];\n wire [5:0] stg3_init = complex_oclkdelay_calib_start ? simp_stg3_final_sel : oclkdelay_init_val;\n \n wire signed [8:0] stg2_steps = stg3_r > stg3_init \n ? -9'sd2 * $signed({3'b0, (stg3_r - stg3_init)})\n : 9'sd2 * $signed({3'b0, (stg3_init - stg3_r)});\n\n wire signed [8:0] stg2_target_ns = $signed({3'b0, wl_po_fine_cnt_sel}) + stg2_steps;\n reg signed [8:0] stg2_target_r;\n always @ (posedge clk) stg2_target_r <= #TCQ stg2_target_ns;\n\n reg [5:0] stg2_final_ns, stg2_final_r;\n always @(posedge clk) stg2_final_r <= #TCQ stg2_final_ns;\n always @(*) stg2_final_ns = stg2_target_r[8] == 1'b1\n\t ? 6'd0\n\t : stg2_target_r > 9'd63\n\t ? 6'd63\n\t : stg2_target_r[5:0];\n\t\t\t\t\t\t \n wire final_stg2_inc = stg2_final_r > po_counter_read_val_r;\n wire final_stg2_dec = stg2_final_r < po_counter_read_val_r;\n \n wire left_lim = stg3_r == lim2ocal_stg3_left_lim;\n wire right_lim = stg3_r == lim2ocal_stg3_right_lim;\n\n reg [1:0] ninety_offsets_ns, ninety_offsets_r;\n always @(posedge clk) ninety_offsets_r <= #TCQ ninety_offsets_ns;\n output [1:0] ninety_offsets;\n assign ninety_offsets = ninety_offsets_r;\n\n reg scanning_right_ns, scanning_right_r;\n always @(posedge clk) scanning_right_r <= #TCQ scanning_right_ns;\n output scanning_right;\n assign scanning_right = scanning_right_r;\n\n reg ocd_ktap_left_ns, ocd_ktap_left_r, ocd_ktap_right_ns, ocd_ktap_right_r;\n always @(posedge clk) ocd_ktap_left_r <= #TCQ ocd_ktap_left_ns;\n always @(posedge clk) ocd_ktap_right_r <= #TCQ ocd_ktap_right_ns;\n output ocd_ktap_left, ocd_ktap_right;\n assign ocd_ktap_left = ocd_ktap_left_r;\n assign ocd_ktap_right = ocd_ktap_right_r;\n\n reg ocd_edge_detect_rdy_ns, ocd_edge_detect_rdy_r;\n always @(posedge clk) ocd_edge_detect_rdy_r <= #TCQ ocd_edge_detect_rdy_ns;\n output ocd_edge_detect_rdy;\n assign ocd_edge_detect_rdy = ocd_edge_detect_rdy_r;\n \n input mmcm_edge_detect_done;\n input mmcm_lbclk_edge_aligned;\n input poc_backup;\n reg poc_backup_ns, poc_backup_r;\n always @(posedge clk) poc_backup_r <= #TCQ poc_backup_ns;\n\n reg taps_set_r;\n output taps_set;\n assign taps_set = taps_set_r;\n\n input phy_rddata_en_3;\n\n input [5:0] zero2fuzz, fuzz2zero, oneeighty2fuzz, fuzz2oneeighty;\n input z2f, f2z, o2f, f2o;\n\n wire zero = f2z && z2f;\n wire noise = z2f && f2o;\n wire oneeighty = f2o && o2f;\n\n reg win_not_found;\n reg [1:0] ninety_offsets_final_ns, ninety_offsets_final_r;\n always @(posedge clk) ninety_offsets_final_r <= #TCQ ninety_offsets_final_ns;\n reg [5:0] left, right, current_edge;\n always @(*) begin\n left = lim2ocal_stg3_left_lim;\n right = lim2ocal_stg3_right_lim;\n ninety_offsets_final_ns = 2'd0;\n win_not_found = 1'b0;\n if (zero) begin\n left = fuzz2zero;\n right = zero2fuzz;\n end\n else if (noise) begin\n left = zero2fuzz;\n right = fuzz2oneeighty;\n ninety_offsets_final_ns = 2'd1;\n end\n else if (oneeighty) begin\n left = fuzz2oneeighty;\n right = oneeighty2fuzz;\n ninety_offsets_final_ns = 2'd2;\n end\n else if (z2f) begin\n right = zero2fuzz;\n end\n else if (f2o) begin\n left = fuzz2oneeighty;\n ninety_offsets_final_ns = 2'd2;\n end\n else if (f2z) begin\n left = fuzz2zero;\n end\n else win_not_found = 1'b1;\n current_edge = ocd_ktap_left_r ? left : right;\n end // always @ begin\n\n output use_noise_window;\n assign use_noise_window = ninety_offsets == 2'd1;\n\n reg ocal_scan_win_not_found_ns, ocal_scan_win_not_found_r;\n always @(posedge clk) ocal_scan_win_not_found_r <= #TCQ ocal_scan_win_not_found_ns;\n output ocal_scan_win_not_found;\n assign ocal_scan_win_not_found = ocal_scan_win_not_found_r;\n\n wire inc_po_ns = current_edge > stg3_r;\n wire dec_po_ns = current_edge < stg3_r;\n reg inc_po_r, dec_po_r;\n always @(posedge clk) inc_po_r <= #TCQ inc_po_ns;\n always @(posedge clk) dec_po_r <= #TCQ dec_po_ns;\n\n input scan_right;\n \n wire left_stop = left_lim || scan_right;\n wire right_stop = right_lim || o2f;\n\n // POC samples every other fabric clock.\n localparam POC_SAMPLE_CLEAR_WAIT = SAMPLES * 2 > 15 ? SAMPLES * 2 : 15;\n localparam MAX_RESUME_WAIT = POC_SAMPLE_CLEAR_WAIT > 31 ? POC_SAMPLE_CLEAR_WAIT : 31;\n localparam RESUME_WAIT_WIDTH = clogb2(MAX_RESUME_WAIT + 1);\n\n reg [RESUME_WAIT_WIDTH-1:0] resume_wait_ns, resume_wait_r;\n always @(posedge clk) resume_wait_r <= #TCQ resume_wait_ns;\n\n wire resume_wait = |resume_wait_r;\n \n reg po_done_ns, po_done_r;\n always @(posedge clk) po_done_r <= #TCQ po_done_ns;\n \n input samp_done;\n \n input po_rdy;\n \n reg up_ns, up_r;\n always @(posedge clk) up_r <= #TCQ up_ns;\n \n reg [1:0] two_ns, two_r;\n always @(posedge clk) two_r <= #TCQ two_ns;\n\n \n/* wire stg2_zero = ~|stg2_r;\n wire [8:0] stg2_2_zero = stg2_r[8] ? 9'd0 \n : stg2_r > 9'd63\n ? 9'd63\n : stg2_r; */\n\n reg [3:0] sm_ns, sm_r;\n always @(posedge clk) sm_r <= #TCQ sm_ns;\n\n reg phy_rddata_en_3_second_ns, phy_rddata_en_3_second_r;\n always @(posedge clk) phy_rddata_en_3_second_r <= #TCQ phy_rddata_en_3_second_ns;\n always @(*) phy_rddata_en_3_second_ns = ~reset_scan && (phy_rddata_en_3 \n ? ~phy_rddata_en_3_second_r \n : phy_rddata_en_3_second_r);\n wire use_samp_done = nCK_PER_CLK == 2 ? phy_rddata_en_3 && phy_rddata_en_3_second_r : phy_rddata_en_3;\n\n reg po_center_wait;\n reg po_slew;\n reg po_finish_scan;\n \n always @(*) begin\n\n // Default next state assignments.\n\n cmplx_samples_done_ns = cmplx_samples_done_r;\n cmplx_stg3_final_ns = cmplx_stg3_final_r;\n scanning_right_ns = scanning_right_r;\n ninety_offsets_ns = ninety_offsets_r;\n ocal_scan_win_not_found_ns = ocal_scan_win_not_found_r;\n ocd_edge_detect_rdy_ns = ocd_edge_detect_rdy_r;\n ocd_ktap_left_ns = ocd_ktap_left_r;\n ocd_ktap_right_ns = ocd_ktap_right_r;\n ocd2stg2_inc_r = 1'b0;\n ocd2stg2_dec_r = 1'b0;\n ocd2stg3_inc_r = 1'b0;\n ocd2stg3_dec_r = 1'b0;\n oclkdelay_center_calib_start_ns = oclkdelay_center_calib_start_r;\n oclkdelay_center_calib_done_ns = 1'b0;\n oclk_center_write_resume_ns = oclk_center_write_resume_r;\n po_center_wait = 1'b0;\n po_done_ns = po_done_r;\n po_finish_scan = 1'b0;\n po_slew = 1'b0;\n poc_backup_ns = poc_backup_r;\n scan_done_r = 1'b0;\n simp_stg3_final_ns = simp_stg3_final_r;\n sm_ns = sm_r;\n taps_set_r = 1'b0;\n up_ns = up_r;\n stg2_ns = stg2_r;\n stg3_ns = stg3_r;\n two_ns = two_r;\n resume_wait_ns = resume_wait_r;\n \n if (rst == 1'b1) begin\n \n // RESET next states\n cmplx_samples_done_ns = 1'b0;\n ocal_scan_win_not_found_ns = 1'b0;\n ocd_ktap_left_ns = 1'b0;\n ocd_ktap_right_ns = 1'b0;\n ocd_edge_detect_rdy_ns = 1'b0;\n oclk_center_write_resume_ns = 1'b0;\n oclkdelay_center_calib_start_ns = 1'b0;\n po_done_ns = 1'b1;\n resume_wait_ns = 5'd0;\n sm_ns = /*AK(\"READY\")*/4'd0;\n \n end else\n \n // State based actions and next states. \n case (sm_r)\n\n /*AL(\"READY\")*/4'd0:begin\n\t poc_backup_ns = 1'b0;\n\t stg2_ns = {3'b0, wl_po_fine_cnt_sel};\n stg3_ns = stg3_init;\n\t scanning_right_ns = 1'b0;\n\t if (complex_oclkdelay_calib_start) cmplx_samples_done_ns = 1'b1;\n\t if (!reset_scan && ~resume_wait) begin\n\t cmplx_samples_done_ns = 1'b0;\n\t ocal_scan_win_not_found_ns = 1'b0;\n\t taps_set_r = 1'b1;\n\t sm_ns = /*AK(\"SAMPLING\")*/4'd1;\n\t end\n end\n\n /*AL(\"SAMPLING\")*/4'd1:begin\n\t if (samp_done && use_samp_done) begin\n\t if (complex_oclkdelay_calib_start) cmplx_samples_done_ns = 1'b1;\n\t scanning_right_ns = scanning_right_r || left_stop;\n\t if (right_stop && scanning_right_r) begin\n\t\toclkdelay_center_calib_start_ns = 1'b1;\n\t\tocd_ktap_left_ns = 1'b1;\n\t\tocal_scan_win_not_found_ns = win_not_found;\n\t\tsm_ns = /*AK(\"SLEW_PO\")*/4'd3;\n\t end else begin\n\t\tif (scanning_right_ns) ocd2stg3_inc_r = 1'b1;\n\t\telse ocd2stg3_dec_r = 1'b1;\n\t sm_ns = /*AK(\"PO_WAIT\")*/4'd2;\n\t end\n\t end\n\tend\n\n\t/*AL(\"PO_WAIT\")*/4'd2:begin\n\t if (po_done_r && ~resume_wait) begin\n\t taps_set_r = 1'b1;\n\t sm_ns = /*AK(\"SAMPLING\")*/4'd1;\n\t cmplx_samples_done_ns = 1'b0;\n\t end\n\tend\n\n\t/*AL(\"SLEW_PO\")*/4'd3:begin\n\t po_slew = 1'b1;\n\t ninety_offsets_ns = |ninety_offsets_final_r ? 2'b01 : 2'b00;\n\t if (~resume_wait) begin\n\t if (po_done_r) begin\n if (inc_po_r) ocd2stg3_inc_r = 1'b1;\n else if (dec_po_r) ocd2stg3_dec_r = 1'b1;\n\t else if (~resume_wait) begin\n\t\t cmplx_samples_done_ns = 1'b0;\n sm_ns = /*AK(\"ALIGN_EDGES\")*/4'd4;\n\t\t oclk_center_write_resume_ns = 1'b1;\n\t end\n\t end // if (po_done)\n\t end\n\tend // case: 3'd3\n\n\t/*AL(\"ALIGN_EDGES\")*/4'd4:\n\t if (~resume_wait) begin \n\t if (mmcm_edge_detect_done) begin\n\t ocd_edge_detect_rdy_ns = 1'b0;\n \t if (ocd_ktap_left_r) begin\n\t\t ocd_ktap_left_ns = 1'b0;\n\t\t ocd_ktap_right_ns = 1'b1;\n\t\t oclk_center_write_resume_ns = 1'b0;\n\t sm_ns = /*AK(\"SLEW_PO\")*/4'd3;\n\t end else if (ocd_ktap_right_r) begin\n\t\t ocd_ktap_right_ns = 1'b0;\n\t\t sm_ns = /*AK(\"WAIT_ONE\")*/4'd5;\n\t\t end else if (~mmcm_lbclk_edge_aligned) begin\n\t\t sm_ns = /*AK(\"DQS_STOP_WAIT\")*/4'd6;\n\t\t oclk_center_write_resume_ns = 1'b0; \n\t end else begin\n if (ninety_offsets_r != ninety_offsets_final_r && ocd_edge_detect_rdy_r) begin\n ninety_offsets_ns = ninety_offsets_r + 2'b01;\n\t\t sm_ns = /*AK(\"WAIT_ONE\")*/4'd5;\n\t\t end else begin\n\t\t oclk_center_write_resume_ns = 1'b0;\n\t\t poc_backup_ns = poc_backup;\n//\t\t stg2_ns = stg2_2_zero;\n sm_ns = /*AK(\"FINISH_SCAN\")*/4'd8;\n\t end\n\t\t end // else: !if(~mmcm_lbclk_edge_aligned)\n\t end else ocd_edge_detect_rdy_ns = 1'b1;\n\t end // if (~resume_wait)\n\n\n /*AL(\"WAIT_ONE\")*/4'd5:\n\t sm_ns = /*AK(\"ALIGN_EDGES\")*/4'd4;\n\t\n /*AL(\"DQS_STOP_WAIT\")*/4'd6:\n\t if (~resume_wait) begin\n\t ocd2stg3_dec_r = 1'b1;\n\t sm_ns = /*AK(\"CENTER_PO_WAIT\")*/4'd7;\n\t end\n\n /*AL(\"CENTER_PO_WAIT\")*/4'd7: begin\n\t po_center_wait = 1'b1; // Kludge to get around limitation of the AUTOs symbols.\n if (po_done_r) begin\n sm_ns = /*AK(\"ALIGN_EDGES\")*/4'd4;\t \n oclk_center_write_resume_ns = 1'b1;\n\t end\n end\n\t \n /*AL(\"FINISH_SCAN\")*/4'd8: begin\n\t po_finish_scan = 1'b1;\n\t if (resume_wait_r == 5'd1) begin\n if (~poc_backup_r) begin\n oclkdelay_center_calib_done_ns = 1'b1;\n\t oclkdelay_center_calib_start_ns = 1'b0;\n\t end\n\t end\n\t if (~resume_wait) begin\n\t if (po_rdy)\n\t if (poc_backup_r) begin\n ocd2stg3_inc_r = 1'b1;\n\t poc_backup_ns = 1'b0;\n\t end \n else if (~final_stg2_inc && ~final_stg2_dec) begin\n\t if (complex_oclkdelay_calib_start) cmplx_stg3_final_ns[oclkdelay_calib_cnt*6+:6] = stg3_r;\n\t else simp_stg3_final_ns[oclkdelay_calib_cnt*6+:6] = stg3_r;\n\t sm_ns = /*AK(\"READY\")*/4'd0;\n\t scan_done_r = 1'b1;\n\t end else begin\n\t ocd2stg2_inc_r = final_stg2_inc;\n\t ocd2stg2_dec_r = final_stg2_dec;\n\t end\n\t end // if (~resume_wait)\n end // case: 4'd8\n\t\n endcase // case (sm_r)\n\n if (ocd2stg3_inc_r) begin\n stg3_ns = stg3_r + 6'h1;\n up_ns = 1'b0;\n end\n if (ocd2stg3_dec_r) begin\n stg3_ns = stg3_r - 6'h1;\n up_ns = 1'b1;\n end\n if (ocd2stg3_inc_r || ocd2stg3_dec_r) begin\n po_done_ns = 1'b0;\n two_ns = 2'b00;\n end\n\n if (~po_done_r)\n if (po_rdy)\n if (two_r == 2'b10 || po_center_wait || po_slew || po_finish_scan) po_done_ns = 1'b1;\n else begin\n\t two_ns = two_r + 2'b1;\n if (up_r) begin\n stg2_ns = stg2_r + 9'b1;\n\t if (stg2_r >= 9'd0 && stg2_r < 9'd63) ocd2stg2_inc_r = 1'b1;\n\t end else begin\n stg2_ns = stg2_r - 9'b1;\n\t if (stg2_r > 9'd0 && stg2_r <= 9'd63) ocd2stg2_dec_r = 1'b1;\n\t end\n\t end // else: !if(two_r == 2'b10)\n\n if (ocd_ktap_left_ns && ~ocd_ktap_left_r) resume_wait_ns = 'b1;\n else if (oclk_center_write_resume_ns && ~oclk_center_write_resume_r) \n resume_wait_ns = POC_SAMPLE_CLEAR_WAIT[RESUME_WAIT_WIDTH-1:0];\n else if (~oclk_center_write_resume_ns && oclk_center_write_resume_r) resume_wait_ns = 'd15;\n else if (cmplx_samples_done_ns & ~cmplx_samples_done_r || \n complex_oclkdelay_calib_start & reset_scan ||\n poc_backup_r & ocd2stg3_inc_r) resume_wait_ns = 'd31;\n else if (|resume_wait_r) resume_wait_ns = resume_wait_r - 'd1;\n \n end // always @ begin\n \nendmodule // mig_7series_v4_0_ddr_phy_ocd_po_cntlr\n\n// Local Variables:\n// verilog-autolabel-prefix: \"4'd\"\n// End:\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ocd_samp.v", "content": "//*****************************************************************************\n// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor: Xilinx\n// \\ \\ \\/ Version: %version\n// \\ \\ Application: MIG\n// / / Filename: ddr_phy_v4_0_phy_ocd_samp.v\n// /___/ /\\ Date Last Modified: $Date: 2011/02/25 02:07:40 $\n// \\ \\ / \\ Date Created: Aug 03 2009 \n// \\___\\/\\___\\\n//\n//Device: 7 Series\n//Design Name: DDR3 SDRAM\n//Purpose: Controls the number of samples and generates an aggregate\n//sampling result.\n//\n// The following shows the nesting of the sampling loop. Nominally built\n// to accomodate the \"complex\" sampling protocol. Adapted for use with\n// \"simple\" samplng.\n//\n// simple complex\n// \n// samples OCAL_SIMPLE_SCAN_SAMPS 1 or 50 Depends on SIM_CAL_OPTION\n// rd_victim_sel 0 0 to 7\n// data_cnt 1 157\n//\n// First it collects comparison results provided on the\n// two bit \"match\" bus. A particular phaser tap setting may be recorded one\n// or many times depending on various parameter settings. \n// The two bit match bus corresponds to comparisons for the\n// zero or rising phase, and the oneeighty or falling phase. The \"aggregate\"\n// starts out as NULL and then begins collecting comparison results\n// when phy_rddata_en_1 is high. The first result is always set into\n// the aggregate result. Subsequent results that match aggregate, don't\n// make any change. Subsequent compare results that don't match cause the aggregate\n// to turn to FUZZ.\n//\n// A \"sample\" is defined as a single DRAM burst for the simple step, and\n// an entire 157 DRAM data bursts across the 8 victim bits for complex.\n//\n// Once all samples have been taken, the samp_result is computed by\n// comparing the number of successful compares against the threshold.\n//\n// The second function is to track and control the number of samples. For \n// \"simple\" data, the number of samples is set by OCAL_SIMPLE_SCAN_SAMPS. \n// For \"complex\" data, nominally\n// the complex data pattern consists of a sequence of 157 DRAM chunks. This\n// sequence is run with each bit in the byte designated as the \"victim\". This sequence\n// is repeated 50 times, although when SIM_CAL_OPTION is set to none \"NONE\", it is only\n// repeated once.\n//\n// This block generates oclk_calib_resume. For the simple pattern, a single DRAM\n// burst is returned For complex its 157 which indicates the start of the 157*50\n// sequence for a bit. samp_done is pulsed.\n//\n//Reference:\n//Revision History:\n//*****************************************************************************\n\n`timescale 1ps/1ps\n\nmodule mig_7series_v4_0_ddr_phy_ocd_samp #\n (parameter nCK_PER_CLK = 4,\n parameter OCAL_SIMPLE_SCAN_SAMPS = 2,\n parameter SCAN_PCT_SAMPS_SOLID = 95,\n parameter TCQ = 100,\n parameter SIM_CAL_OPTION = \"NONE\")\n (/*AUTOARG*/\n // Outputs\n samp_done, oclk_calib_resume, rd_victim_sel, samp_result,\n // Inputs\n complex_oclkdelay_calib_start, clk, rst, reset_scan,\n ocal_num_samples_inc, match, phy_rddata_en_1, taps_set,\n phy_rddata_en_2\n );\n\n function integer clogb2 (input integer size); // ceiling logb2\n begin\n size = size - 1;\n for (clogb2=1; size>1; clogb2=clogb2+1)\n size = size >> 1;\n end\n endfunction // clogb2\n\n localparam ONE = 1;\n\n localparam CMPLX_DATA_CNT = nCK_PER_CLK == 2 ? 157 * 2 : 157;\n localparam SIMP_DATA_CNT = nCK_PER_CLK == 2 ? 2 : 1;\n\n localparam DATA_CNT_WIDTH = nCK_PER_CLK == 2 ? 9 : 8;\n\n localparam CMPLX_SAMPS = SIM_CAL_OPTION == \"NONE\" ? 50 : 1;\n \n // Plus one because were counting in natural numbers. \n localparam SAMP_CNT_WIDTH = clogb2(OCAL_SIMPLE_SCAN_SAMPS > CMPLX_SAMPS \n ? OCAL_SIMPLE_SCAN_SAMPS : CMPLX_SAMPS) + 1;\n\n // Remember SAMPLES is natural number counting. One corresponds to one sample.\n localparam integer SIMP_SAMPS_SOLID_THRESH = OCAL_SIMPLE_SCAN_SAMPS * SCAN_PCT_SAMPS_SOLID * 0.01;\n localparam integer SIMP_SAMPS_HALF_THRESH = SIMP_SAMPS_SOLID_THRESH/2;\n localparam integer CMPLX_SAMPS_SOLID_THRESH = CMPLX_SAMPS * SCAN_PCT_SAMPS_SOLID * 0.01;\n localparam integer CMPLX_SAMPS_HALF_THRESH = CMPLX_SAMPS_SOLID_THRESH/2;\n\n input complex_oclkdelay_calib_start;\n \n wire [SAMP_CNT_WIDTH-1:0] samples = complex_oclkdelay_calib_start\n\t\t\t ? CMPLX_SAMPS[SAMP_CNT_WIDTH-1:0]\t \n : OCAL_SIMPLE_SCAN_SAMPS[SAMP_CNT_WIDTH-1:0];\n \n localparam [1:0] NULL = 2'b11,\n FUZZ = 2'b00,\n ONEEIGHTY = 2'b10,\n ZERO = 2'b01;\n \n input clk;\n input rst;\n\n input reset_scan;\n\n // Given the need to count phy_data_en, this is not useful.\n input ocal_num_samples_inc;\n \n input [1:0] match;\n\n input phy_rddata_en_1;\n \n input taps_set;\n\n reg samp_done_ns, samp_done_r;\n always @(posedge clk) samp_done_r <= #TCQ samp_done_ns;\n output samp_done;\n assign samp_done = samp_done_r;\n\n input phy_rddata_en_2;\n wire samp_valid = samp_done_r && phy_rddata_en_2;\n\n reg [1:0] agg_samp_ns, agg_samp_r;\n always @(posedge clk) agg_samp_r <= #TCQ agg_samp_ns;\n\n reg oclk_calib_resume_ns, oclk_calib_resume_r;\n always @(posedge clk) oclk_calib_resume_r <= #TCQ oclk_calib_resume_ns;\n output oclk_calib_resume;\n assign oclk_calib_resume = oclk_calib_resume_r;\n\n // Complex data counting.\n // Inner most loop. 157 phy_data_en.\n reg [DATA_CNT_WIDTH-1:0] data_cnt_ns, data_cnt_r;\n always @(posedge clk) data_cnt_r <= #TCQ data_cnt_ns;\n\n // Nominally, 50 samples of the above 157 phy_data_en.\n reg [SAMP_CNT_WIDTH-1:0] samps_ns, samps_r;\n always @(posedge clk) samps_r <= #TCQ samps_ns;\n\n // Step through the 8 bits in the byte.\n reg [2:0] rd_victim_sel_ns, rd_victim_sel_r;\n always @(posedge clk) rd_victim_sel_r <= #TCQ rd_victim_sel_ns;\n output [2:0] rd_victim_sel;\n assign rd_victim_sel = rd_victim_sel_r;\n\n reg [SAMP_CNT_WIDTH-1:0] zero_ns, zero_r, oneeighty_ns, oneeighty_r;\n always @(posedge clk) zero_r <= #TCQ zero_ns;\n always @(posedge clk) oneeighty_r <= #TCQ oneeighty_ns;\n\n wire [SAMP_CNT_WIDTH-1:0] samp_thresh = (complex_oclkdelay_calib_start \n ? CMPLX_SAMPS_SOLID_THRESH[SAMP_CNT_WIDTH-1:0]\n : SIMP_SAMPS_SOLID_THRESH[SAMP_CNT_WIDTH-1:0]);\n\n wire [SAMP_CNT_WIDTH-1:0] samp_half_thresh = (complex_oclkdelay_calib_start \n ? CMPLX_SAMPS_HALF_THRESH[SAMP_CNT_WIDTH-1:0]\n : SIMP_SAMPS_HALF_THRESH[SAMP_CNT_WIDTH-1:0]);\n\n wire zero_ge_thresh = zero_r >= samp_thresh;\n wire zero_le_half_thresh = zero_r <= samp_half_thresh;\n wire oneeighty_ge_thresh = oneeighty_r >= samp_thresh;\n wire oneeighty_le_half_thresh = oneeighty_r <= samp_half_thresh;\n \n reg [1:0] samp_result_ns, samp_result_r;\n always @(posedge clk) samp_result_r <= #TCQ samp_result_ns;\n always @(*) \n if (rst) samp_result_ns = 'b0;\n else begin\n samp_result_ns = samp_result_r;\n if (samp_valid) begin\n\tif (~samp_result_r[0] && zero_ge_thresh) samp_result_ns[0] = 'b1;\n if (samp_result_r[0] && zero_le_half_thresh) samp_result_ns[0] = 'b0;\n\tif (~samp_result_r[1] && oneeighty_ge_thresh) samp_result_ns[1] = 'b1;\n if (samp_result_r[1] && oneeighty_le_half_thresh) samp_result_ns[1] = 'b0;\n end\n end\n \n output [1:0] samp_result;\n assign samp_result = samp_result_ns;\n\n reg [0:0] sm_ns, sm_r;\n always @(posedge clk) sm_r <= #TCQ sm_ns;\n\n wire [DATA_CNT_WIDTH-1:0] data_cnt = complex_oclkdelay_calib_start \n ? CMPLX_DATA_CNT[DATA_CNT_WIDTH-1:0] \n : SIMP_DATA_CNT[DATA_CNT_WIDTH-1:0];\n wire [2:0] rd_victim_end = complex_oclkdelay_calib_start ? 3'h7 : 3'h0;\n wire data_end = data_cnt_r == ONE[DATA_CNT_WIDTH-1:0];\n wire samp_end = samps_r == ONE[SAMP_CNT_WIDTH-1:0];\n \n // Primary state machine.\n \n always @(*) begin\n\n // Default next state assignments.\n\n agg_samp_ns = agg_samp_r;\n data_cnt_ns = data_cnt_r;\n oclk_calib_resume_ns = 1'b0;\n oneeighty_ns = oneeighty_r;\n rd_victim_sel_ns = rd_victim_sel_r;\n samp_done_ns = samp_done_r;\n samps_ns = samps_r;\n sm_ns = sm_r;\n zero_ns = zero_r;\n \n if (rst == 1'b1) begin\n // RESET next states\n sm_ns = /*AK(\"READY\")*/1'd0;\n \n end else\n \n // State based actions and next states. \n case (sm_r)\n\n /*AL(\"READY\")*/1'd0:begin\n\t agg_samp_ns = NULL;\n\t data_cnt_ns = data_cnt;\n\t oneeighty_ns = 'b0;\n\t zero_ns = 'b0;\n\t rd_victim_sel_ns = 3'b0;\n\t samps_ns = complex_oclkdelay_calib_start ? CMPLX_SAMPS[SAMP_CNT_WIDTH-1:0]\n : OCAL_SIMPLE_SCAN_SAMPS[SAMP_CNT_WIDTH-1:0];\n\t \n\t \n\t if (taps_set) begin\n\t samp_done_ns = 1'b0;\n\t sm_ns = /*AK(\"AWAITING_DATA\")*/1'd1;\n\t oclk_calib_resume_ns = 1'b1;\n\t end\n end\n\n /*AL(\"AWAITING_DATA\")*/1'd1:begin\n\t if (phy_rddata_en_1) begin\n\n\t case (agg_samp_r)\n\t NULL : if (~&match) agg_samp_ns = match;\n\t ZERO, ONEEIGHTY : if (~(agg_samp_r == match || &match)) agg_samp_ns = FUZZ;\n\t FUZZ : ;\n\t endcase // case (agg_samp_r)\n\n\t if (~data_end) data_cnt_ns = data_cnt_r - ONE[DATA_CNT_WIDTH-1:0];\n\t else begin\n\t data_cnt_ns = data_cnt;\n\t if (rd_victim_end != rd_victim_sel_r) rd_victim_sel_ns = rd_victim_sel_r + 3'h1;\n\t else begin\n\t\trd_victim_sel_ns = 3'h0;\n\t\tif (agg_samp_ns == ZERO) zero_ns = zero_r + ONE[SAMP_CNT_WIDTH-1:0];\n\t if (agg_samp_ns == ONEEIGHTY) oneeighty_ns = oneeighty_r + ONE[SAMP_CNT_WIDTH-1:0];\n\t\tagg_samp_ns = NULL;\n\t\tif (~samp_end) samps_ns = samps_r - ONE[SAMP_CNT_WIDTH-1:0];\n\t\telse samp_done_ns = 1'b1;\n\t end\n\t end\n \n \t if (samp_done_ns) sm_ns = /*AK(\"READY\")*/1'd0;\n\t else oclk_calib_resume_ns = ~complex_oclkdelay_calib_start && data_end;\n\t end\n\tend\n\t\n endcase // case (sm_r)\n end // always @ begin\n \n \nendmodule // mig_7series_v4_0_ddr_phy_ocd_samp\n\n// Local Variables:\n// verilog-autolabel-prefix: \"1'd\"\n// End:\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_oclkdelay_cal.v", "content": "//*****************************************************************************\n// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor: Xilinx\n// \\ \\ \\/ Version: %version\n// \\ \\ Application: MIG\n// / / Filename: ddr_phy_oclkdelay_cal.v\n// /___/ /\\ Date Last Modified: $Date: 2011/02/25 02:07:40 $\n// \\ \\ / \\ Date Created: Aug 03 2009 \n// \\___\\/\\___\\\n//\n//Device: 7 Series\n//Design Name: DDR3 SDRAM\n//Purpose: Center write DQS in write DQ valid window using Phaser_Out Stage3\n// delay\n//Reference:\n//Revision History:\n//*****************************************************************************\n\n`timescale 1ps/1ps\n\nmodule mig_7series_v4_0_ddr_phy_oclkdelay_cal #\n (parameter TCQ = 100,\n parameter nCK_PER_CLK = 4,\n parameter DRAM_WIDTH = 8,\n parameter DQS_CNT_WIDTH = 3,\n parameter DQS_WIDTH = 8,\n parameter DQ_WIDTH = 64,\n parameter MMCM_SAMP_WAIT = 10,\n parameter OCAL_SIMPLE_SCAN_SAMPS = 2,\n parameter PCT_SAMPS_SOLID = 95,\n parameter POC_USE_METASTABLE_SAMP = \"FALSE\",\n parameter SCAN_PCT_SAMPS_SOLID = 95,\n parameter SIM_CAL_OPTION = \"NONE\",\n parameter SAMPCNTRWIDTH = 8,\n parameter SAMPLES\t = 128,\n parameter TAPCNTRWIDTH = 7,\n parameter TAPSPERKCLK = 56,\n parameter BYPASS_COMPLEX_OCAL = \"FALSE\")\n (/*AUTOARG*/\n // Outputs\n wrlvl_final, rd_victim_sel, psincdec, psen, poc_error, po_stg23_sel,\n po_stg23_incdec, po_en_stg23, oclkdelay_center_calib_start,\n oclkdelay_center_calib_done, oclk_prech_req,\n oclk_center_write_resume, oclk_calib_resume,\n ocal_num_samples_done_r, lim2init_write_request, dbg_poc,\n complex_wrlvl_final, complex_oclkdelay_calib_done,\n oclkdelay_calib_cnt, dbg_phy_oclkdelay_cal, dbg_oclkdelay_rd_data,\n oclkdelay_calib_done, lim_done, dbg_ocd_lim,\n // Inputs\n wl_po_fine_cnt, rst, psdone, prech_done, prbs_o,\n prbs_ignore_last_bytes, prbs_ignore_first_byte, poc_sample_pd,\n po_counter_read_val, phy_rddata_en, phy_rddata, oclkdelay_init_val,\n oclkdelay_calib_start, ocal_num_samples_inc, metaQ,\n complex_oclkdelay_calib_start, clk\n );\n\n /*AUTOINPUT*/\n // Beginning of automatic inputs (from unused autoinst inputs)\n input\t\t\tclk;\t\t\t// To u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v, ...\n input\t\t\tcomplex_oclkdelay_calib_start;// To u_ocd_data of mig_7series_v4_0_ddr_phy_ocd_data.v, ...\n input\t\t\tmetaQ;\t\t\t// To u_poc of mig_7series_v4_0_poc_top.v\n input\t\t\tocal_num_samples_inc;\t// To u_ocd_samp of mig_7series_v4_0_ddr_phy_ocd_samp.v\n input\t\t\toclkdelay_calib_start;\t// To u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v\n input [5:0]\t\toclkdelay_init_val;\t// To u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v, ...\n input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata;// To u_ocd_data of mig_7series_v4_0_ddr_phy_ocd_data.v\n input\t\t\tphy_rddata_en;\t\t// To u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v\n input [8:0]\t\tpo_counter_read_val;\t// To u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v, ...\n input\t\t\tpoc_sample_pd;\t\t// To u_poc of mig_7series_v4_0_poc_top.v\n input\t\t\tprbs_ignore_first_byte;\t// To u_ocd_data of mig_7series_v4_0_ddr_phy_ocd_data.v\n input\t\t\tprbs_ignore_last_bytes;\t// To u_ocd_data of mig_7series_v4_0_ddr_phy_ocd_data.v\n input [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o;\t// To u_ocd_data of mig_7series_v4_0_ddr_phy_ocd_data.v\n input\t\t\tprech_done;\t\t// To u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v, ...\n input\t\t\tpsdone;\t\t\t// To u_poc of mig_7series_v4_0_poc_top.v\n input\t\t\trst;\t\t\t// To u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v, ...\n input [6*DQS_WIDTH-1:0] wl_po_fine_cnt;\t// To u_ocd_mux of mig_7series_v4_0_ddr_phy_ocd_mux.v\n // End of automatics\n /*AUTOOUTPUT*/\n // Beginning of automatic outputs (from unused autoinst outputs)\n output\t\tcomplex_oclkdelay_calib_done;// From u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v\n output\t\tcomplex_wrlvl_final;\t// From u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v\n output [1023:0]\tdbg_poc;\t\t// From u_poc of mig_7series_v4_0_poc_top.v\n output\t\tlim2init_write_request;\t// From u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v\n output\t\tocal_num_samples_done_r;// From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v\n output\t\toclk_calib_resume;\t// From u_ocd_samp of mig_7series_v4_0_ddr_phy_ocd_samp.v\n output\t\toclk_center_write_resume;// From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v\n output\t\toclk_prech_req;\t\t// From u_ocd_mux of mig_7series_v4_0_ddr_phy_ocd_mux.v\n output\t\toclkdelay_center_calib_done;// From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v\n output\t\toclkdelay_center_calib_start;// From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v\n output\t\tpo_en_stg23;\t\t// From u_ocd_mux of mig_7series_v4_0_ddr_phy_ocd_mux.v\n output\t\tpo_stg23_incdec;\t// From u_ocd_mux of mig_7series_v4_0_ddr_phy_ocd_mux.v\n output\t\tpo_stg23_sel;\t\t// From u_ocd_mux of mig_7series_v4_0_ddr_phy_ocd_mux.v\n output\t\tpoc_error;\t\t// From u_poc of mig_7series_v4_0_poc_top.v\n output\t\tpsen;\t\t\t// From u_poc of mig_7series_v4_0_poc_top.v\n output\t\tpsincdec;\t\t// From u_poc of mig_7series_v4_0_poc_top.v\n output [2:0]\t\trd_victim_sel;\t\t// From u_ocd_samp of mig_7series_v4_0_ddr_phy_ocd_samp.v\n output\t\twrlvl_final;\t\t// From u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v\n // End of automatics\n /*AUTOWIRE*/\n // Beginning of automatic wires (for undeclared instantiated-module outputs)\n wire\t\t\tf2o;\t\t\t// From u_ocd_edge of mig_7series_v4_0_ddr_phy_ocd_edge.v\n wire\t\t\tf2z;\t\t\t// From u_ocd_edge of mig_7series_v4_0_ddr_phy_ocd_edge.v\n wire [5:0]\t\tfuzz2oneeighty;\t\t// From u_ocd_edge of mig_7series_v4_0_ddr_phy_ocd_edge.v\n wire [5:0]\t\tfuzz2zero;\t\t// From u_ocd_edge of mig_7series_v4_0_ddr_phy_ocd_edge.v\n wire\t\t\tktap_at_left_edge;\t// From u_ocd_mux of mig_7series_v4_0_ddr_phy_ocd_mux.v\n wire\t\t\tktap_at_right_edge;\t// From u_ocd_mux of mig_7series_v4_0_ddr_phy_ocd_mux.v\n wire\t\t\tlim2init_prech_req;\t// From u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v\n wire [5:0]\t\tlim2ocal_stg3_left_lim;\t// From u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v\n wire [5:0]\t\tlim2ocal_stg3_right_lim;// From u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v\n wire\t\t\tlim2poc_ktap_right;\t// From u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v\n wire\t\t\tlim2poc_rdy;\t\t// From u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v\n wire\t\t\tlim2stg2_dec;\t\t// From u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v\n wire\t\t\tlim2stg2_inc;\t\t// From u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v\n wire\t\t\tlim2stg3_dec;\t\t// From u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v\n wire\t\t\tlim2stg3_inc;\t\t// From u_ocd_lim of mig_7series_v4_0_ddr_phy_ocd_lim.v\n wire\t\t\tlim_start;\t\t// From u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v\n wire [1:0]\t\tmatch;\t\t\t// From u_ocd_data of mig_7series_v4_0_ddr_phy_ocd_data.v\n wire\t\t\tmmcm_edge_detect_done;\t// From u_poc of mig_7series_v4_0_poc_top.v\n wire\t\t\tmmcm_edge_detect_rdy;\t// From u_ocd_mux of mig_7series_v4_0_ddr_phy_ocd_mux.v\n wire\t\t\tmmcm_lbclk_edge_aligned;// From u_poc of mig_7series_v4_0_poc_top.v\n wire [1:0]\t\tninety_offsets;\t\t// From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v\n wire\t\t\to2f;\t\t\t// From u_ocd_edge of mig_7series_v4_0_ddr_phy_ocd_edge.v\n wire\t\t\tocd2stg2_dec;\t\t// From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v\n wire\t\t\tocd2stg2_inc;\t\t// From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v\n wire\t\t\tocd2stg3_dec;\t\t// From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v\n wire\t\t\tocd2stg3_inc;\t\t// From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v\n wire\t\t\tocd_cntlr2stg2_dec;\t// From u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v\n wire\t\t\tocd_edge_detect_rdy;\t// From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v\n wire\t\t\tocd_ktap_left;\t\t// From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v\n wire\t\t\tocd_ktap_right;\t\t// From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v\n wire\t\t\tocd_prech_req;\t\t// From u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v\n wire [5:0]\t\toneeighty2fuzz;\t\t// From u_ocd_edge of mig_7series_v4_0_ddr_phy_ocd_edge.v\n wire\t\t\tphy_rddata_en_1;\t// From u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v\n wire\t\t\tphy_rddata_en_2;\t// From u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v\n wire\t\t\tphy_rddata_en_3;\t// From u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v\n wire\t\t\tpo_rdy;\t\t\t// From u_ocd_mux of mig_7series_v4_0_ddr_phy_ocd_mux.v\n wire\t\t\tpoc_backup;\t\t// From u_poc of mig_7series_v4_0_poc_top.v\n wire\t\t\treset_scan;\t\t// From u_ocd_cntlr of mig_7series_v4_0_ddr_phy_ocd_cntlr.v\n wire [TAPCNTRWIDTH-1:0] rise_lead_right;\t// From u_poc of mig_7series_v4_0_poc_top.v\n wire [TAPCNTRWIDTH-1:0] rise_trail_right;\t// From u_poc of mig_7series_v4_0_poc_top.v\n wire\t\t\tsamp_done;\t\t// From u_ocd_samp of mig_7series_v4_0_ddr_phy_ocd_samp.v\n wire [1:0]\t\tsamp_result;\t\t// From u_ocd_samp of mig_7series_v4_0_ddr_phy_ocd_samp.v\n wire\t\t\tscan_done;\t\t// From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v\n wire\t\t\tscan_right;\t\t// From u_ocd_edge of mig_7series_v4_0_ddr_phy_ocd_edge.v\n wire\t\t\tscanning_right;\t\t// From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v\n wire [5:0]\t\tsimp_stg3_final_sel;\t// From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v\n wire [5:0]\t\tstg3;\t\t\t// From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v\n wire\t\t\ttaps_set;\t\t// From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v\n wire\t\t\tuse_noise_window;\t// From u_ocd_po_cntlr of mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v\n wire [5:0]\t\twl_po_fine_cnt_sel;\t// From u_ocd_mux of mig_7series_v4_0_ddr_phy_ocd_mux.v\n wire\t\t\tz2f;\t\t\t// From u_ocd_edge of mig_7series_v4_0_ddr_phy_ocd_edge.v\n wire [5:0]\t\tzero2fuzz;\t\t// From u_ocd_edge of mig_7series_v4_0_ddr_phy_ocd_edge.v\n // End of automatics\n wire [DQS_WIDTH*6-1:0] simp_stg3_final, cmplx_stg3_final;\n wire ocal_scan_win_not_found;\n\n\n output [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;\n output [255:0] dbg_phy_oclkdelay_cal;\n output [16*DRAM_WIDTH-1:0] dbg_oclkdelay_rd_data;\n output oclkdelay_calib_done;\n\n output lim_done;\n output [255:0] dbg_ocd_lim;\n \n // Debug signals\n assign dbg_phy_oclkdelay_cal[0] = f2o; \n assign dbg_phy_oclkdelay_cal[1] = f2z;\n assign dbg_phy_oclkdelay_cal[2] = o2f;\n assign dbg_phy_oclkdelay_cal[3] = z2f;\n assign dbg_phy_oclkdelay_cal[4+:6] = fuzz2oneeighty;\n assign dbg_phy_oclkdelay_cal[10+:6] = fuzz2zero;\n assign dbg_phy_oclkdelay_cal[16+:6] = oneeighty2fuzz;\n assign dbg_phy_oclkdelay_cal[22+:6] = zero2fuzz;\n assign dbg_phy_oclkdelay_cal[28+:3] = oclkdelay_calib_cnt;\n assign dbg_phy_oclkdelay_cal[31] = oclkdelay_calib_start;\n assign dbg_phy_oclkdelay_cal[32] = lim_done;\n assign dbg_phy_oclkdelay_cal[33+:6] =lim2ocal_stg3_left_lim ;\n assign dbg_phy_oclkdelay_cal[39+:6] = lim2ocal_stg3_right_lim ;\n assign dbg_phy_oclkdelay_cal[45+:8] = po_counter_read_val[8:0];\n assign dbg_phy_oclkdelay_cal[53+:54] = simp_stg3_final[DQS_WIDTH*6-1:0];\n assign dbg_phy_oclkdelay_cal[107] = ocal_scan_win_not_found; \n assign dbg_phy_oclkdelay_cal[108] = oclkdelay_center_calib_start;\n assign dbg_phy_oclkdelay_cal[109] = oclkdelay_center_calib_done;\n assign dbg_phy_oclkdelay_cal[115:110] = stg3[5:0];\n \n /*mig_7series_v4_0_ddr_phy_ocd_lim AUTO_TEMPLATE(\n .TDQSS_DEGREES (),\n .wl_po_fine_cnt (wl_po_fine_cnt_sel[5:0]),\n .poc2lim_detect_done (mmcm_edge_detect_done),\n .poc2lim_fall_align_taps_.* ({TAPCNTRWIDTH{1'b0}}),\n .poc2lim_rise_align_taps_lead (rise_lead_right),\n .poc2lim_rise_align_taps_trail (rise_trail_right),); */\n\n mig_7series_v4_0_ddr_phy_ocd_lim #\n (/*AUTOINSTPARAM*/\n // Parameters\n .BYPASS_COMPLEX_OCAL\t\t(BYPASS_COMPLEX_OCAL),\n .DQS_CNT_WIDTH\t\t\t(DQS_CNT_WIDTH),\n .DQS_WIDTH\t\t\t\t(DQS_WIDTH),\n .TAPCNTRWIDTH\t\t\t(TAPCNTRWIDTH),\n .TAPSPERKCLK\t\t\t(TAPSPERKCLK),\n .TCQ\t\t\t\t(TCQ),\n .TDQSS_DEGREES\t\t\t())\t\t\t // Templated\n u_ocd_lim\n (/*AUTOINST*/\n // Outputs\n .dbg_ocd_lim\t\t\t(dbg_ocd_lim[255:0]),\n .lim2init_prech_req\t\t(lim2init_prech_req),\n .lim2init_write_request\t\t(lim2init_write_request),\n .lim2ocal_stg3_left_lim\t\t(lim2ocal_stg3_left_lim[5:0]),\n .lim2ocal_stg3_right_lim\t\t(lim2ocal_stg3_right_lim[5:0]),\n .lim2poc_ktap_right\t\t(lim2poc_ktap_right),\n .lim2poc_rdy\t\t\t(lim2poc_rdy),\n .lim2stg2_dec\t\t\t(lim2stg2_dec),\n .lim2stg2_inc\t\t\t(lim2stg2_inc),\n .lim2stg3_dec\t\t\t(lim2stg3_dec),\n .lim2stg3_inc\t\t\t(lim2stg3_inc),\n .lim_done\t\t\t\t(lim_done),\n // Inputs\n .clk\t\t\t\t(clk),\n .lim_start\t\t\t\t(lim_start),\n .oclkdelay_calib_cnt\t\t(oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]),\n .oclkdelay_calib_done\t\t(oclkdelay_calib_done),\n .oclkdelay_init_val\t\t(oclkdelay_init_val[5:0]),\n .po_rdy\t\t\t\t(po_rdy),\n .poc2lim_detect_done\t\t(mmcm_edge_detect_done), // Templated\n .poc2lim_fall_align_taps_lead\t({TAPCNTRWIDTH{1'b0}}),\t // Templated\n .poc2lim_fall_align_taps_trail\t({TAPCNTRWIDTH{1'b0}}),\t // Templated\n .poc2lim_rise_align_taps_lead\t(rise_lead_right),\t // Templated\n .poc2lim_rise_align_taps_trail\t(rise_trail_right),\t // Templated\n .prech_done\t\t\t(prech_done),\n .rst\t\t\t\t(rst),\n .simp_stg3_final_sel\t\t(simp_stg3_final_sel[5:0]),\n .wl_po_fine_cnt\t\t\t(wl_po_fine_cnt_sel[5:0])); // Templated\n\n /*mig_7series_v4_0_poc_top AUTO_TEMPLATE(\n .CCENABLE (0),\n .LANE_CNT_WIDTH (DQS_CNT_WIDTH),\n .SCANFROMRIGHT (1),\n .lane (oclkdelay_calib_cnt[DQS_CNT_WIDTH-1:0]),\n .pd_out (metaQ),); */\n\n mig_7series_v4_0_poc_top #\n (/*AUTOINSTPARAM*/\n // Parameters\n .CCENABLE\t\t\t\t(0),\t\t\t // Templated\n .LANE_CNT_WIDTH\t\t\t(DQS_CNT_WIDTH),\t // Templated\n .MMCM_SAMP_WAIT\t\t\t(MMCM_SAMP_WAIT),\n .PCT_SAMPS_SOLID\t\t\t(PCT_SAMPS_SOLID),\n .POC_USE_METASTABLE_SAMP\t\t(POC_USE_METASTABLE_SAMP),\n .SAMPCNTRWIDTH\t\t\t(SAMPCNTRWIDTH),\n .SAMPLES\t\t\t\t(SAMPLES),\n .SCANFROMRIGHT\t\t\t(1),\t\t\t // Templated\n .TAPCNTRWIDTH\t\t\t(TAPCNTRWIDTH),\n .TAPSPERKCLK\t\t\t(TAPSPERKCLK),\n .TCQ\t\t\t\t(TCQ))\n u_poc\n (/*AUTOINST*/\n // Outputs\n .dbg_poc\t\t\t\t(dbg_poc[1023:0]),\n .mmcm_edge_detect_done\t\t(mmcm_edge_detect_done),\n .mmcm_lbclk_edge_aligned\t\t(mmcm_lbclk_edge_aligned),\n .poc_backup\t\t\t(poc_backup),\n .poc_error\t\t\t\t(poc_error),\n .psen\t\t\t\t(psen),\n .psincdec\t\t\t\t(psincdec),\n .rise_lead_right\t\t\t(rise_lead_right[TAPCNTRWIDTH-1:0]),\n .rise_trail_right\t\t\t(rise_trail_right[TAPCNTRWIDTH-1:0]),\n // Inputs\n .clk\t\t\t\t(clk),\n .ktap_at_left_edge\t\t\t(ktap_at_left_edge),\n .ktap_at_right_edge\t\t(ktap_at_right_edge),\n .lane\t\t\t\t(oclkdelay_calib_cnt[DQS_CNT_WIDTH-1:0]), // Templated\n .mmcm_edge_detect_rdy\t\t(mmcm_edge_detect_rdy),\n .ninety_offsets\t\t\t(ninety_offsets[1:0]),\n .pd_out\t\t\t\t(metaQ),\t\t // Templated\n .poc_sample_pd\t\t\t(poc_sample_pd),\n .psdone\t\t\t\t(psdone),\n .rst\t\t\t\t(rst),\n .use_noise_window\t\t\t(use_noise_window));\n\n /*mig_7series_v4_0_ddr_phy_ocd_mux AUTO_TEMPLATE(\n .po_stg3_incdec (),\n .po_en_stg3 (),); */\n\n mig_7series_v4_0_ddr_phy_ocd_mux #\n (/*AUTOINSTPARAM*/\n // Parameters\n .DQS_CNT_WIDTH\t\t\t(DQS_CNT_WIDTH),\n .DQS_WIDTH\t\t\t\t(DQS_WIDTH),\n .TCQ\t\t\t\t(TCQ))\n u_ocd_mux\n (/*AUTOINST*/\n // Outputs\n .ktap_at_left_edge\t\t\t(ktap_at_left_edge),\n .ktap_at_right_edge\t\t(ktap_at_right_edge),\n .mmcm_edge_detect_rdy\t\t(mmcm_edge_detect_rdy),\n .oclk_prech_req\t\t\t(oclk_prech_req),\n .po_en_stg23\t\t\t(po_en_stg23),\n .po_en_stg3\t\t\t(),\t\t\t // Templated\n .po_rdy\t\t\t\t(po_rdy),\n .po_stg23_incdec\t\t\t(po_stg23_incdec),\n .po_stg23_sel\t\t\t(po_stg23_sel),\n .po_stg3_incdec\t\t\t(),\t\t\t // Templated\n .wl_po_fine_cnt_sel\t\t(wl_po_fine_cnt_sel[5:0]),\n // Inputs\n .clk\t\t\t\t(clk),\n .lim2init_prech_req\t\t(lim2init_prech_req),\n .lim2poc_ktap_right\t\t(lim2poc_ktap_right),\n .lim2poc_rdy\t\t\t(lim2poc_rdy),\n .lim2stg2_dec\t\t\t(lim2stg2_dec),\n .lim2stg2_inc\t\t\t(lim2stg2_inc),\n .lim2stg3_dec\t\t\t(lim2stg3_dec),\n .lim2stg3_inc\t\t\t(lim2stg3_inc),\n .ocd2stg2_dec\t\t\t(ocd2stg2_dec),\n .ocd2stg2_inc\t\t\t(ocd2stg2_inc),\n .ocd2stg3_dec\t\t\t(ocd2stg3_dec),\n .ocd2stg3_inc\t\t\t(ocd2stg3_inc),\n .ocd_cntlr2stg2_dec\t\t(ocd_cntlr2stg2_dec),\n .ocd_edge_detect_rdy\t\t(ocd_edge_detect_rdy),\n .ocd_ktap_left\t\t\t(ocd_ktap_left),\n .ocd_ktap_right\t\t\t(ocd_ktap_right),\n .ocd_prech_req\t\t\t(ocd_prech_req),\n .oclkdelay_calib_cnt\t\t(oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]),\n .rst\t\t\t\t(rst),\n .wl_po_fine_cnt\t\t\t(wl_po_fine_cnt[6*DQS_WIDTH-1:0]));\n \n mig_7series_v4_0_ddr_phy_ocd_data #\n (/*AUTOINSTPARAM*/\n // Parameters\n .DQS_CNT_WIDTH\t\t\t(DQS_CNT_WIDTH),\n .DQ_WIDTH\t\t\t\t(DQ_WIDTH),\n .TCQ\t\t\t\t(TCQ),\n .nCK_PER_CLK\t\t\t(nCK_PER_CLK))\n u_ocd_data\n (/*AUTOINST*/\n // Outputs\n .match\t\t\t\t(match[1:0]),\n // Inputs\n .clk\t\t\t\t(clk),\n .complex_oclkdelay_calib_start\t(complex_oclkdelay_calib_start),\n .oclkdelay_calib_cnt\t\t(oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]),\n .phy_rddata\t\t\t(phy_rddata[2*nCK_PER_CLK*DQ_WIDTH-1:0]),\n .phy_rddata_en_1\t\t\t(phy_rddata_en_1),\n .prbs_ignore_first_byte\t\t(prbs_ignore_first_byte),\n .prbs_ignore_last_bytes\t\t(prbs_ignore_last_bytes),\n .prbs_o\t\t\t\t(prbs_o[2*nCK_PER_CLK*DQ_WIDTH-1:0]),\n .rst\t\t\t\t(rst));\n \n mig_7series_v4_0_ddr_phy_ocd_samp #\n (/*AUTOINSTPARAM*/\n // Parameters\n .OCAL_SIMPLE_SCAN_SAMPS\t\t(OCAL_SIMPLE_SCAN_SAMPS),\n .SCAN_PCT_SAMPS_SOLID\t\t(SCAN_PCT_SAMPS_SOLID),\n .SIM_CAL_OPTION\t\t\t(SIM_CAL_OPTION),\n .TCQ\t\t\t\t(TCQ),\n .nCK_PER_CLK\t\t\t(nCK_PER_CLK))\n u_ocd_samp\n (/*AUTOINST*/\n // Outputs\n .oclk_calib_resume\t\t\t(oclk_calib_resume),\n .rd_victim_sel\t\t\t(rd_victim_sel[2:0]),\n .samp_done\t\t\t\t(samp_done),\n .samp_result\t\t\t(samp_result[1:0]),\n // Inputs\n .clk\t\t\t\t(clk),\n .complex_oclkdelay_calib_start\t(complex_oclkdelay_calib_start),\n .match\t\t\t\t(match[1:0]),\n .ocal_num_samples_inc\t\t(ocal_num_samples_inc),\n .phy_rddata_en_1\t\t\t(phy_rddata_en_1),\n .phy_rddata_en_2\t\t\t(phy_rddata_en_2),\n .reset_scan\t\t\t(reset_scan),\n .rst\t\t\t\t(rst),\n .taps_set\t\t\t\t(taps_set));\n\n mig_7series_v4_0_ddr_phy_ocd_edge #\n (/*AUTOINSTPARAM*/\n // Parameters\n .TCQ\t\t\t\t(TCQ))\n u_ocd_edge\n (/*AUTOINST*/\n // Outputs\n .f2o\t\t\t\t(f2o),\n .f2z\t\t\t\t(f2z),\n .fuzz2oneeighty\t\t\t(fuzz2oneeighty[5:0]),\n .fuzz2zero\t\t\t\t(fuzz2zero[5:0]),\n .o2f\t\t\t\t(o2f),\n .oneeighty2fuzz\t\t\t(oneeighty2fuzz[5:0]),\n .scan_right\t\t\t(scan_right),\n .z2f\t\t\t\t(z2f),\n .zero2fuzz\t\t\t\t(zero2fuzz[5:0]),\n // Inputs\n .clk\t\t\t\t(clk),\n .phy_rddata_en_2\t\t\t(phy_rddata_en_2),\n .reset_scan\t\t\t(reset_scan),\n .samp_done\t\t\t\t(samp_done),\n .samp_result\t\t\t(samp_result[1:0]),\n .scanning_right\t\t\t(scanning_right),\n .stg3\t\t\t\t(stg3[5:0]));\n\n /*mig_7series_v4_0_ddr_phy_ocd_cntlr AUTO_TEMPLATE(\n .oclk_init_delay_done (),); */\n \n mig_7series_v4_0_ddr_phy_ocd_cntlr #\n (/*AUTOINSTPARAM*/\n // Parameters\n .DQS_CNT_WIDTH\t\t\t(DQS_CNT_WIDTH),\n .DQS_WIDTH\t\t\t\t(DQS_WIDTH),\n .TCQ\t\t\t\t(TCQ))\n u_ocd_cntlr\n (/*AUTOINST*/\n // Outputs\n .complex_oclkdelay_calib_done\t(complex_oclkdelay_calib_done),\n .complex_wrlvl_final\t\t(complex_wrlvl_final),\n .lim_start\t\t\t\t(lim_start),\n .ocd_cntlr2stg2_dec\t\t(ocd_cntlr2stg2_dec),\n .ocd_prech_req\t\t\t(ocd_prech_req),\n .oclk_init_delay_done\t\t(),\t\t\t // Templated\n .oclkdelay_calib_cnt\t\t(oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]),\n .oclkdelay_calib_done\t\t(oclkdelay_calib_done),\n .phy_rddata_en_1\t\t\t(phy_rddata_en_1),\n .phy_rddata_en_2\t\t\t(phy_rddata_en_2),\n .phy_rddata_en_3\t\t\t(phy_rddata_en_3),\n .reset_scan\t\t\t(reset_scan),\n .wrlvl_final\t\t\t(wrlvl_final),\n // Inputs\n .clk\t\t\t\t(clk),\n .complex_oclkdelay_calib_start\t(complex_oclkdelay_calib_start),\n .lim_done\t\t\t\t(lim_done),\n .oclkdelay_calib_start\t\t(oclkdelay_calib_start),\n .phy_rddata_en\t\t\t(phy_rddata_en),\n .po_counter_read_val\t\t(po_counter_read_val[8:0]),\n .po_rdy\t\t\t\t(po_rdy),\n .prech_done\t\t\t(prech_done),\n .rst\t\t\t\t(rst),\n .scan_done\t\t\t\t(scan_done));\n\n \n mig_7series_v4_0_ddr_phy_ocd_po_cntlr #\n (/*AUTOINSTPARAM*/\n // Parameters\n .DQS_CNT_WIDTH\t\t\t(DQS_CNT_WIDTH),\n .DQS_WIDTH\t\t\t\t(DQS_WIDTH),\n .SAMPLES\t\t\t\t(SAMPLES),\n .TCQ\t\t\t\t(TCQ),\n .nCK_PER_CLK\t\t\t(nCK_PER_CLK))\n u_ocd_po_cntlr\n (.cmplx_stg3_final\t\t\t(cmplx_stg3_final[DQS_WIDTH*6-1:0]),\n .ocal_scan_win_not_found\t\t(ocal_scan_win_not_found),\n .simp_stg3_final\t\t\t(simp_stg3_final[DQS_WIDTH*6-1:0]),\n /*AUTOINST*/\n // Outputs\n .ninety_offsets\t\t\t(ninety_offsets[1:0]),\n .ocal_num_samples_done_r\t\t(ocal_num_samples_done_r),\n .ocd2stg2_dec\t\t\t(ocd2stg2_dec),\n .ocd2stg2_inc\t\t\t(ocd2stg2_inc),\n .ocd2stg3_dec\t\t\t(ocd2stg3_dec),\n .ocd2stg3_inc\t\t\t(ocd2stg3_inc),\n .ocd_edge_detect_rdy\t\t(ocd_edge_detect_rdy),\n .ocd_ktap_left\t\t\t(ocd_ktap_left),\n .ocd_ktap_right\t\t\t(ocd_ktap_right),\n .oclk_center_write_resume\t\t(oclk_center_write_resume),\n .oclkdelay_center_calib_done\t(oclkdelay_center_calib_done),\n .oclkdelay_center_calib_start\t(oclkdelay_center_calib_start),\n .scan_done\t\t\t\t(scan_done),\n .scanning_right\t\t\t(scanning_right),\n .simp_stg3_final_sel\t\t(simp_stg3_final_sel[5:0]),\n .stg3\t\t\t\t(stg3[5:0]),\n .taps_set\t\t\t\t(taps_set),\n .use_noise_window\t\t\t(use_noise_window),\n // Inputs\n .clk\t\t\t\t(clk),\n .complex_oclkdelay_calib_start\t(complex_oclkdelay_calib_start),\n .f2o\t\t\t\t(f2o),\n .f2z\t\t\t\t(f2z),\n .fuzz2oneeighty\t\t\t(fuzz2oneeighty[5:0]),\n .fuzz2zero\t\t\t\t(fuzz2zero[5:0]),\n .lim2ocal_stg3_left_lim\t\t(lim2ocal_stg3_left_lim[5:0]),\n .lim2ocal_stg3_right_lim\t\t(lim2ocal_stg3_right_lim[5:0]),\n .mmcm_edge_detect_done\t\t(mmcm_edge_detect_done),\n .mmcm_lbclk_edge_aligned\t\t(mmcm_lbclk_edge_aligned),\n .o2f\t\t\t\t(o2f),\n .oclkdelay_calib_cnt\t\t(oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]),\n .oclkdelay_init_val\t\t(oclkdelay_init_val[5:0]),\n .oneeighty2fuzz\t\t\t(oneeighty2fuzz[5:0]),\n .phy_rddata_en_3\t\t\t(phy_rddata_en_3),\n .po_counter_read_val\t\t(po_counter_read_val[8:0]),\n .po_rdy\t\t\t\t(po_rdy),\n .poc_backup\t\t\t(poc_backup),\n .reset_scan\t\t\t(reset_scan),\n .rst\t\t\t\t(rst),\n .samp_done\t\t\t\t(samp_done),\n .scan_right\t\t\t(scan_right),\n .wl_po_fine_cnt_sel\t\t(wl_po_fine_cnt_sel[5:0]),\n .z2f\t\t\t\t(z2f),\n .zero2fuzz\t\t\t\t(zero2fuzz[5:0]));\n \n \nendmodule // mig_7series_v4_0_ddr_phy_oclkdelay_cal\n\n// Local Variables:\n// verilog-library-directories:(\".\")\n// verilog-library-extensions:(\".v\")\n// End:\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_prbs_rdlvl.v", "content": "//*****************************************************************************\n// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor: Xilinx\n// \\ \\ \\/ Version:\n// \\ \\ Application: MIG\n// / / Filename: ddr_phy_prbs_rdlvl.v\n// /___/ /\\ Date Last Modified: $Date: 2011/06/24 14:49:00 $\n// \\ \\ / \\ Date Created:\n// \\___\\/\\___\\\n//\n//Device: 7 Series\n//Design Name: DDR3 SDRAM\n//Purpose:\n// PRBS Read leveling calibration logic\n// NOTES:\n// 1. Window detection with PRBS pattern.\n//Reference:\n//Revision History:\n//*****************************************************************************\n\n/******************************************************************************\n**$Id: ddr_phy_prbs_rdlvl.v,v 1.2 2011/06/24 14:49:00 mgeorge Exp $\n**$Date: 2011/06/24 14:49:00 $\n**$Author: mgeorge $\n**$Revision: 1.2 $\n**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_prbs_rdlvl.v,v $\n******************************************************************************/\n\n`timescale 1ps/1ps\n\nmodule mig_7series_v4_0_ddr_phy_prbs_rdlvl #\n (\n parameter TCQ = 100, // clk->out delay (sim only)\n parameter nCK_PER_CLK = 2, // # of memory clocks per CLK\n parameter DQ_WIDTH = 64, // # of DQ (data)\n parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))\n parameter DQS_WIDTH = 8, // # of DQS (strobe)\n parameter DRAM_WIDTH = 8, // # of DQ per DQS\n parameter RANKS = 1, // # of DRAM ranks\n parameter SIM_CAL_OPTION = \"NONE\", // Skip various calibration steps\n parameter PRBS_WIDTH = 8, // PRBS generator output width\n parameter FIXED_VICTIM = \"TRUE\", // No victim rotation when \"TRUE\"\n parameter FINE_PER_BIT = \"ON\",\n parameter CENTER_COMP_MODE = \"ON\",\n parameter PI_VAL_ADJ = \"ON\"\n )\n (\n input clk,\n input rst,\n // Calibration status, control signals\n input prbs_rdlvl_start,\n (* max_fanout = 100 *) output reg prbs_rdlvl_done,\n output reg prbs_last_byte_done,\n output reg prbs_rdlvl_prech_req,\n input complex_sample_cnt_inc,\n input prech_done,\n input phy_if_empty,\n // Captured data in fabric clock domain\n input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,\n //Expected data from PRBS generator\n input [2*nCK_PER_CLK*DQ_WIDTH-1:0] compare_data,\n // Decrement initial Phaser_IN Fine tap delay\n input [5:0] pi_counter_read_val,\n // Stage 1 calibration outputs\n output reg pi_en_stg2_f,\n output reg pi_stg2_f_incdec,\n output [255:0] dbg_prbs_rdlvl,\n output [DQS_CNT_WIDTH:0] pi_stg2_prbs_rdlvl_cnt, \n output reg [2:0] rd_victim_sel,\n output reg complex_victim_inc,\n output reg reset_rd_addr,\n \n output reg [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r,\n output reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps,\n output reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps,\n output reg [DRAM_WIDTH-1:0] fine_delay_incdec_pb, //fine_delay decreament per bit\n output reg fine_delay_sel, //fine delay selection - actual update of fine delay\n output reg num_samples_done_r,\n input complex_act_start, //read is done. ready for PI movement\n output complex_init_pi_dec_done, //Initial PI incdec is done. ready for start\n output reg complex_pi_incdec_done //PI incdec is done. ready for Read\n );\n\n\n\n \n localparam [5:0] PRBS_IDLE = 6'h00;\n localparam [5:0] PRBS_NEW_DQS_WAIT = 6'h01;\n localparam [5:0] PRBS_PAT_COMPARE = 6'h02;\n localparam [5:0] PRBS_DEC_DQS = 6'h03;\n localparam [5:0] PRBS_DEC_DQS_WAIT = 6'h04;\n localparam [5:0] PRBS_INC_DQS = 6'h05;\n localparam [5:0] PRBS_INC_DQS_WAIT = 6'h06;\n localparam [5:0] PRBS_CALC_TAPS = 6'h07;\n localparam [5:0] PRBS_NEXT_DQS = 6'h08;\n localparam [5:0] PRBS_NEW_DQS_PREWAIT = 6'h09;\n localparam [5:0] PRBS_DONE = 6'h0A;\n localparam [5:0] PRBS_CALC_TAPS_PRE = 6'h0B;\n localparam [5:0] PRBS_CALC_TAPS_WAIT = 6'h0C;\n\n localparam [5:0] FINE_PI_DEC = 6'h0D; //go back to all fail or back to center\n localparam [5:0] FINE_PI_DEC_WAIT = 6'h0E; //wait for PI tap dec settle\n localparam [5:0] FINE_PI_INC = 6'h0F; //increse up to 1 fail \n localparam [5:0] FINE_PI_INC_WAIT = 6'h10; //wait for PI tap int settle\n localparam [5:0] FINE_PAT_COMPARE_PER_BIT = 6'h11; //compare per bit error and check left/right/gain/loss\n localparam [5:0] FINE_CALC_TAPS = 6'h12; //setup fine_delay_incdec_pb for better window size\n localparam [5:0] FINE_CALC_TAPS_WAIT = 6'h13; //wait for ROM value for dec cnt\n localparam [5:0] RD_DONE_WAIT_FOR_PI_INC_INC = 6'h14; //wait for read is done before PI inc\n localparam [5:0] RD_DONE_WAIT_FOR_PI_INC_DEC = 6'h15; //wait for read is done before PI dec\n\n localparam [11:0] NUM_SAMPLES_CNT = (SIM_CAL_OPTION == \"NONE\") ? 'd12 : 12'h001; //MG from 50 \n localparam [11:0] NUM_SAMPLES_CNT1 = (SIM_CAL_OPTION == \"NONE\") ? 'd20 : 12'h001; \n localparam [11:0] NUM_SAMPLES_CNT2 = (SIM_CAL_OPTION == \"NONE\") ? 'd10 : 12'h001; \n\n //minimum valid window for centering\n localparam MIN_WIN = 8;\n localparam [MIN_WIN-1:0] MATCH_ALL_ONE = {MIN_WIN{1'b1}};\n localparam [MIN_WIN-1:0] MIN_PASS = {MIN_WIN{1'b0}}; //8'b00000000\n localparam [MIN_WIN-1:0] MIN_LEFT = {1'b1,{{MIN_WIN-1}{1'b0}}}; //8'b10000000\n\n wire [DQS_CNT_WIDTH+2:0]prbs_dqs_cnt_timing;\n reg [DQS_CNT_WIDTH+2:0] prbs_dqs_cnt_timing_r;\n reg [DQS_CNT_WIDTH:0] prbs_dqs_cnt_r;\n reg prbs_prech_req_r;\n reg [5:0] prbs_state_r;\n reg [5:0] prbs_state_r1;\n reg wait_state_cnt_en_r;\n reg [3:0] wait_state_cnt_r;\n reg cnt_wait_state;\n reg err_chk_invalid;\n // reg found_edge_r;\n reg prbs_found_1st_edge_r;\n reg prbs_found_2nd_edge_r;\n reg [5:0] prbs_1st_edge_taps_r;\n // reg found_stable_eye_r;\n reg [5:0] prbs_dqs_tap_cnt_r;\n reg [5:0] prbs_dec_tap_calc_plus_3;\n reg [5:0] prbs_dec_tap_calc_minus_3;\n reg prbs_dqs_tap_limit_r;\n reg [5:0] prbs_inc_tap_cnt;\n reg [5:0] prbs_dec_tap_cnt;\n reg [DRAM_WIDTH-1:0] mux_rd_fall0_r1;\n reg [DRAM_WIDTH-1:0] mux_rd_fall1_r1;\n reg [DRAM_WIDTH-1:0] mux_rd_rise0_r1;\n reg [DRAM_WIDTH-1:0] mux_rd_rise1_r1;\n reg [DRAM_WIDTH-1:0] mux_rd_fall2_r1;\n reg [DRAM_WIDTH-1:0] mux_rd_fall3_r1;\n reg [DRAM_WIDTH-1:0] mux_rd_rise2_r1;\n reg [DRAM_WIDTH-1:0] mux_rd_rise3_r1;\n reg [DRAM_WIDTH-1:0] mux_rd_fall0_r2;\n reg [DRAM_WIDTH-1:0] mux_rd_fall1_r2;\n reg [DRAM_WIDTH-1:0] mux_rd_rise0_r2;\n reg [DRAM_WIDTH-1:0] mux_rd_rise1_r2;\n reg [DRAM_WIDTH-1:0] mux_rd_fall2_r2;\n reg [DRAM_WIDTH-1:0] mux_rd_fall3_r2;\n reg [DRAM_WIDTH-1:0] mux_rd_rise2_r2;\n reg [DRAM_WIDTH-1:0] mux_rd_rise3_r2;\n reg [DRAM_WIDTH-1:0] mux_rd_fall0_r3;\n reg [DRAM_WIDTH-1:0] mux_rd_fall1_r3;\n reg [DRAM_WIDTH-1:0] mux_rd_rise0_r3;\n reg [DRAM_WIDTH-1:0] mux_rd_rise1_r3;\n reg [DRAM_WIDTH-1:0] mux_rd_fall2_r3;\n reg [DRAM_WIDTH-1:0] mux_rd_fall3_r3;\n reg [DRAM_WIDTH-1:0] mux_rd_rise2_r3;\n reg [DRAM_WIDTH-1:0] mux_rd_rise3_r3;\n reg [DRAM_WIDTH-1:0] mux_rd_fall0_r4;\n reg [DRAM_WIDTH-1:0] mux_rd_fall1_r4;\n reg [DRAM_WIDTH-1:0] mux_rd_rise0_r4;\n reg [DRAM_WIDTH-1:0] mux_rd_rise1_r4;\n reg [DRAM_WIDTH-1:0] mux_rd_fall2_r4;\n reg [DRAM_WIDTH-1:0] mux_rd_fall3_r4;\n reg [DRAM_WIDTH-1:0] mux_rd_rise2_r4;\n reg [DRAM_WIDTH-1:0] mux_rd_rise3_r4;\n reg mux_rd_valid_r;\n reg rd_valid_r1;\n reg rd_valid_r2;\n reg rd_valid_r3;\n reg new_cnt_dqs_r;\n reg prbs_tap_en_r;\n reg prbs_tap_inc_r;\n reg pi_en_stg2_f_timing;\n reg pi_stg2_f_incdec_timing;\n wire [DQ_WIDTH-1:0] rd_data_rise0;\n wire [DQ_WIDTH-1:0] rd_data_fall0;\n wire [DQ_WIDTH-1:0] rd_data_rise1;\n wire [DQ_WIDTH-1:0] rd_data_fall1;\n wire [DQ_WIDTH-1:0] rd_data_rise2;\n wire [DQ_WIDTH-1:0] rd_data_fall2;\n wire [DQ_WIDTH-1:0] rd_data_rise3;\n wire [DQ_WIDTH-1:0] rd_data_fall3;\n wire [DQ_WIDTH-1:0] compare_data_r0;\n wire [DQ_WIDTH-1:0] compare_data_f0;\n wire [DQ_WIDTH-1:0] compare_data_r1;\n wire [DQ_WIDTH-1:0] compare_data_f1;\n wire [DQ_WIDTH-1:0] compare_data_r2;\n wire [DQ_WIDTH-1:0] compare_data_f2;\n wire [DQ_WIDTH-1:0] compare_data_r3;\n wire [DQ_WIDTH-1:0] compare_data_f3;\n reg [DRAM_WIDTH-1:0] compare_data_rise0_r1;\n reg [DRAM_WIDTH-1:0] compare_data_fall0_r1;\n reg [DRAM_WIDTH-1:0] compare_data_rise1_r1;\n reg [DRAM_WIDTH-1:0] compare_data_fall1_r1;\n reg [DRAM_WIDTH-1:0] compare_data_rise2_r1;\n reg [DRAM_WIDTH-1:0] compare_data_fall2_r1;\n reg [DRAM_WIDTH-1:0] compare_data_rise3_r1;\n reg [DRAM_WIDTH-1:0] compare_data_fall3_r1;\n reg [DQS_CNT_WIDTH:0] rd_mux_sel_r;\n reg [5:0] prbs_2nd_edge_taps_r;\n \n // reg [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r;\n reg [5:0] rdlvl_cpt_tap_cnt;\n reg prbs_rdlvl_start_r;\n \n reg compare_err;\n reg compare_err_r0;\n reg compare_err_f0;\n reg compare_err_r1;\n reg compare_err_f1;\n reg compare_err_r2;\n reg compare_err_f2;\n reg compare_err_r3;\n reg compare_err_f3;\n reg compare_err_latch;\n \n reg samples_cnt1_en_r;\n reg samples_cnt2_en_r;\n reg [11:0] samples_cnt_r;\n reg num_samples_done_ind; //indicate num_samples_done_r is set in FINE_PAT_COMPARE_PER_BIT to prevent victim_sel_rd out of sync\n reg [DQS_WIDTH-1:0] prbs_tap_mod;\n \n //reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps;\n //reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps;\n \n //**************************************************************************\n // signals for per-bit algorithm of fine_delay calculations\n //**************************************************************************\n reg [6*DRAM_WIDTH-1:0] left_edge_pb; //left edge value per bit\n reg [6*DRAM_WIDTH-1:0] right_edge_pb; //right edge value per bit\n reg [MIN_WIN*DRAM_WIDTH-1:0] match_flag_pb; //5 consecutive match flag per bit\n reg [MIN_WIN-1:0] match_flag_and; //5 consecute match flag of all bits (1: all bit fail)\n reg [MIN_WIN-1:0] match_flag_or; //5 consecute match flag of all bits (1: any bit fail)\n reg [DRAM_WIDTH-1:0] left_edge_found_pb; //left_edge found per bit - use for loss calculation \n reg [DRAM_WIDTH-1:0] left_edge_updated; //left edge was updated for this PI tap - used for largest left edge /ref bit update\n reg [DRAM_WIDTH-1:0] right_edge_found_pb; //right_edge found per bit - use for gail calulation and smallest right edge update \n reg right_edge_found; //smallest right_edge found \n reg [DRAM_WIDTH*6-1:0] left_loss_pb; //left_edge loss per bit\n reg [DRAM_WIDTH*6-1:0] right_gain_pb; //right_edge gain per bit\n reg [DRAM_WIDTH-1:0] ref_bit; //bit number which has largest left edge (with smaller right edge)\n reg [DRAM_WIDTH-1:0] bit_cnt; //bit number used to calculate ref bit\n reg [DRAM_WIDTH-1:0] ref_bit_per_bit; //bit flags which have largest left edge\n reg [5:0] ref_right_edge; //ref_bit right edge - keep the smallest edge of ref bits\n reg [5:0] largest_left_edge; //biggest left edge of per bit - will be left edge of byte\n reg [5:0] smallest_right_edge; //smallest right edge of per bit - will be right edge of byte\n reg [5:0] fine_pi_dec_cnt; //Phase In tap decrement count (to go back to '0' or center)\n reg [6:0] center_calc; //used for calculate the dec tap for centering\n reg [5:0] right_edge_ref; //ref_bit right edge\n reg [5:0] left_edge_ref; //ref_bit left edge\n\n reg [DRAM_WIDTH-1:0] compare_err_pb; //compare error per bit\n reg [DRAM_WIDTH-1:0] compare_err_pb_latch_r; //sticky compare error per bit used for left/right edge\n reg compare_err_pb_and; //indicate all bit fail\n reg compare_err_pb_or; //indicate any bit fail\n reg fine_inc_stage; //fine_inc_stage (1: increment all except ref_bit, 0: only inc for gain bit)\n reg [1:0] stage_cnt; //stage cnt (0,1: fine delay inc stage, 2: fine delay dec stage)\n wire fine_calib; //turn on/off fine delay calibration\n\n reg [5:0] mem_out_dec;\n reg [5:0] dec_cnt;\n reg fine_dly_error; //indicate it has wrong left/right edge \n reg edge_det_error; //indicate it has wrong left/right edge \n\n wire center_comp;\n wire pi_adj;\n\n reg no_err_win_detected;\n reg no_err_win_detected_latch;\n reg [1:0] valid_window_cnt; //number of valid window in the scan\n reg double_window_ind; //indication of double window \n\n //if inital PI dec is not done, init SM should wait until it is done\n reg complex_init_pi_dec_done_r; //if inital PI dec is not done, init SM should wait until it is done\n wire complex_rdlvl_err;\n\n //**************************************************************************\n // DQS count to hard PHY during write calibration using Phaser_OUT Stage2\n // coarse delay \n //**************************************************************************\n assign pi_stg2_prbs_rdlvl_cnt = prbs_dqs_cnt_r; \n\n //fine delay turn on\n assign fine_calib = (FINE_PER_BIT==\"ON\")? 1:0;\n assign center_comp = (CENTER_COMP_MODE == \"ON\")? 1: 0;\n assign pi_adj = (PI_VAL_ADJ == \"ON\")?1:0;\n \n //Debug error flag\n assign complex_rdlvl_err = fine_dly_error | edge_det_error;\n\n //initial dec is only happening for per-bit \n assign complex_init_pi_dec_done = fine_calib? complex_init_pi_dec_done_r : 1'b1;\n\n assign dbg_prbs_rdlvl[0+:6] = left_edge_pb[0+:6];\n assign dbg_prbs_rdlvl[7:6] = left_loss_pb[0+:2];\n assign dbg_prbs_rdlvl[8+:6] = left_edge_pb[6+:6]; \n assign dbg_prbs_rdlvl[15:14] = left_loss_pb[6+:2];\n assign dbg_prbs_rdlvl[16+:6] = left_edge_pb[12+:6] ;\n assign dbg_prbs_rdlvl[23:22] = left_loss_pb[12+:2];\n assign dbg_prbs_rdlvl[24+:6] = left_edge_pb[18+:6] ;\n assign dbg_prbs_rdlvl[31:30] = left_loss_pb[18+:2];\n assign dbg_prbs_rdlvl[32+:6] = left_edge_pb[24+:6];\n assign dbg_prbs_rdlvl[39:38] = left_loss_pb[24+:2];\n assign dbg_prbs_rdlvl[40+:6] = left_edge_pb[30+:6];\n assign dbg_prbs_rdlvl[47:46] = left_loss_pb[30+:2];\n assign dbg_prbs_rdlvl[48+:6] = left_edge_pb[36+:6];\n assign dbg_prbs_rdlvl[55:54] = left_loss_pb[36+:2];\n assign dbg_prbs_rdlvl[56+:6] = left_edge_pb[42+:6];\n assign dbg_prbs_rdlvl[63:62] = left_loss_pb[42+:2];\n\n assign dbg_prbs_rdlvl[64+:6] = right_edge_pb[0+:6];\n assign dbg_prbs_rdlvl[71:70] = right_gain_pb[0+:2];\n assign dbg_prbs_rdlvl[72+:6] = right_edge_pb[6+:6] ;\n assign dbg_prbs_rdlvl[79:78] = right_gain_pb[6+:2];\n assign dbg_prbs_rdlvl[80+:6] = right_edge_pb[12+:6];\n assign dbg_prbs_rdlvl[87:86] = right_gain_pb[12+:2];\n assign dbg_prbs_rdlvl[88+:6] = right_edge_pb[18+:6];\n assign dbg_prbs_rdlvl[95:94] = right_gain_pb[18+:2];\n assign dbg_prbs_rdlvl[96+:6] = right_edge_pb[24+:6];\n assign dbg_prbs_rdlvl[103:102] = right_gain_pb[24+:2];\n assign dbg_prbs_rdlvl[104+:6] = right_edge_pb[30+:6];\n assign dbg_prbs_rdlvl[111:110] = right_gain_pb[30+:2];\n assign dbg_prbs_rdlvl[112+:6] = right_edge_pb[36+:6];\n assign dbg_prbs_rdlvl[119:118] = right_gain_pb[36+:2];\n assign dbg_prbs_rdlvl[120+:6] = right_edge_pb[42+:6]; \n assign dbg_prbs_rdlvl[127:126] = right_gain_pb[42+:2];\n \n assign dbg_prbs_rdlvl[128+:6] = pi_counter_read_val;\n assign dbg_prbs_rdlvl[134+:6] = prbs_dqs_tap_cnt_r;\n\n assign dbg_prbs_rdlvl[140] = prbs_found_1st_edge_r;\n assign dbg_prbs_rdlvl[141] = prbs_found_2nd_edge_r;\n assign dbg_prbs_rdlvl[142] = compare_err;\n assign dbg_prbs_rdlvl[143] = phy_if_empty;\n assign dbg_prbs_rdlvl[144] = prbs_rdlvl_start;\n assign dbg_prbs_rdlvl[145] = prbs_rdlvl_done;\n assign dbg_prbs_rdlvl[146+:5] = prbs_dqs_cnt_r;\n assign dbg_prbs_rdlvl[151+:6] = left_edge_pb[prbs_dqs_cnt_r*6+:6] ;\n assign dbg_prbs_rdlvl[157+:6] = right_edge_pb[prbs_dqs_cnt_r*6+:6];\n assign dbg_prbs_rdlvl[163+:6] = {2'h0,complex_victim_inc, rd_victim_sel[2:0]};\n assign dbg_prbs_rdlvl[169+:6] =right_gain_pb[prbs_dqs_cnt_r*6+:6] ;\n assign dbg_prbs_rdlvl[177:175] = ref_bit[2:0];\n\n assign dbg_prbs_rdlvl[178+:6] = prbs_state_r1[5:0];\n assign dbg_prbs_rdlvl[184] = rd_valid_r2;\n assign dbg_prbs_rdlvl[185] = compare_err_r0;\n assign dbg_prbs_rdlvl[186] = compare_err_f0;\n assign dbg_prbs_rdlvl[187] = compare_err_r1;\n assign dbg_prbs_rdlvl[188] = compare_err_f1;\n assign dbg_prbs_rdlvl[189] = compare_err_r2;\n assign dbg_prbs_rdlvl[190] = compare_err_f2;\n assign dbg_prbs_rdlvl[191] = compare_err_r3;\n assign dbg_prbs_rdlvl[192] = compare_err_f3;\n assign dbg_prbs_rdlvl[193+:8] = left_edge_found_pb;\n assign dbg_prbs_rdlvl[201+:8] = right_edge_found_pb;\n assign dbg_prbs_rdlvl[209+:6] =largest_left_edge ;\n assign dbg_prbs_rdlvl[215+:6] =smallest_right_edge ;\n assign dbg_prbs_rdlvl[221+:8] = fine_delay_incdec_pb;\n assign dbg_prbs_rdlvl[229] = fine_delay_sel;\n assign dbg_prbs_rdlvl[230+:8] = compare_err_pb_latch_r;\n assign dbg_prbs_rdlvl[238+:6] = fine_pi_dec_cnt;\n assign dbg_prbs_rdlvl[244+:5] = match_flag_and[4:0]; \n assign dbg_prbs_rdlvl[249+:2] = stage_cnt;\n assign dbg_prbs_rdlvl[251] = fine_inc_stage;\n assign dbg_prbs_rdlvl[252] = compare_err_pb_and;\n assign dbg_prbs_rdlvl[253] = right_edge_found;\n assign dbg_prbs_rdlvl[254] = complex_rdlvl_err;\n assign dbg_prbs_rdlvl[255] = double_window_ind;\n \n //************************************************************************** \n // Record first and second edges found during calibration\n //**************************************************************************\n generate\n always @(posedge clk)\n if (rst) begin\n dbg_prbs_first_edge_taps <= #TCQ 'b0;\n dbg_prbs_second_edge_taps <= #TCQ 'b0;\n end else if (prbs_state_r == PRBS_CALC_TAPS) begin\n // Record tap counts of first and second edge edges during\n // calibration for each DQS group. If neither edge has\n // been found, then those taps will remain 0\n if (prbs_found_1st_edge_r)\n dbg_prbs_first_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6] \n <= #TCQ prbs_1st_edge_taps_r;\n if (prbs_found_2nd_edge_r)\n dbg_prbs_second_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6] \n <= #TCQ prbs_2nd_edge_taps_r;\n end else if (prbs_state_r == FINE_CALC_TAPS) begin\n if(stage_cnt == 'd2) begin\n dbg_prbs_first_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6] \n <= #TCQ largest_left_edge;\n dbg_prbs_second_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6] \n <= #TCQ smallest_right_edge; \n end\n end\n endgenerate\n \n //double window indication flag\n always @ (posedge clk)\n if (rst) double_window_ind <= #TCQ 1'd0;\n else double_window_ind <= #TCQ double_window_ind? 1'b1: (valid_window_cnt > 1);\n\n //padded calculation\n always @ (smallest_right_edge or largest_left_edge)\n center_calc <= {1'b0, smallest_right_edge} + {1'b0,largest_left_edge}; \n //***************************************************************************\n //***************************************************************************\n // Data mux to route appropriate bit to calibration logic - i.e. calibration\n // is done sequentially, one bit (or DQS group) at a time\n //***************************************************************************\n\n generate\n if (nCK_PER_CLK == 4) begin: rd_data_div4_logic_clk\n assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];\n assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];\n assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];\n assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];\n assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH];\n assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH];\n assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH];\n assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH];\n assign compare_data_r0 = compare_data[DQ_WIDTH-1:0];\n assign compare_data_f0 = compare_data[2*DQ_WIDTH-1:DQ_WIDTH];\n assign compare_data_r1 = compare_data[3*DQ_WIDTH-1:2*DQ_WIDTH];\n assign compare_data_f1 = compare_data[4*DQ_WIDTH-1:3*DQ_WIDTH];\n assign compare_data_r2 = compare_data[5*DQ_WIDTH-1:4*DQ_WIDTH];\n assign compare_data_f2 = compare_data[6*DQ_WIDTH-1:5*DQ_WIDTH];\n assign compare_data_r3 = compare_data[7*DQ_WIDTH-1:6*DQ_WIDTH];\n assign compare_data_f3 = compare_data[8*DQ_WIDTH-1:7*DQ_WIDTH];\n end else begin: rd_data_div2_logic_clk\n assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];\n assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];\n assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];\n assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];\n assign compare_data_r0 = compare_data[DQ_WIDTH-1:0];\n assign compare_data_f0 = compare_data[2*DQ_WIDTH-1:DQ_WIDTH];\n assign compare_data_r1 = compare_data[3*DQ_WIDTH-1:2*DQ_WIDTH];\n assign compare_data_f1 = compare_data[4*DQ_WIDTH-1:3*DQ_WIDTH];\n assign compare_data_r2 = 'h0;\n assign compare_data_f2 = 'h0;\n assign compare_data_r3 = 'h0;\n assign compare_data_f3 = 'h0;\n end\n endgenerate\n\n always @(posedge clk) begin\n rd_mux_sel_r <= #TCQ prbs_dqs_cnt_r;\n end\n\n // Register outputs for improved timing.\n // NOTE: Will need to change when per-bit DQ deskew is supported.\n // Currenly all bits in DQS group are checked in aggregate\n generate\n genvar mux_i;\n for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd\n always @(posedge clk) begin\n mux_rd_rise0_r1[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i];\n mux_rd_fall0_r1[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i];\n mux_rd_rise1_r1[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i];\n mux_rd_fall1_r1[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i];\n mux_rd_rise2_r1[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r + mux_i];\n mux_rd_fall2_r1[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r + mux_i];\n mux_rd_rise3_r1[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r + mux_i];\n mux_rd_fall3_r1[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r + mux_i];\n //Compare data\n compare_data_rise0_r1[mux_i] <= #TCQ compare_data_r0[DRAM_WIDTH*rd_mux_sel_r + mux_i];\n compare_data_fall0_r1[mux_i] <= #TCQ compare_data_f0[DRAM_WIDTH*rd_mux_sel_r + mux_i];\n compare_data_rise1_r1[mux_i] <= #TCQ compare_data_r1[DRAM_WIDTH*rd_mux_sel_r + mux_i];\n compare_data_fall1_r1[mux_i] <= #TCQ compare_data_f1[DRAM_WIDTH*rd_mux_sel_r + mux_i];\n compare_data_rise2_r1[mux_i] <= #TCQ compare_data_r2[DRAM_WIDTH*rd_mux_sel_r + mux_i];\n compare_data_fall2_r1[mux_i] <= #TCQ compare_data_f2[DRAM_WIDTH*rd_mux_sel_r + mux_i];\n compare_data_rise3_r1[mux_i] <= #TCQ compare_data_r3[DRAM_WIDTH*rd_mux_sel_r + mux_i];\n compare_data_fall3_r1[mux_i] <= #TCQ compare_data_f3[DRAM_WIDTH*rd_mux_sel_r + mux_i];\n end\n end\n endgenerate\n \n generate\n genvar muxr2_i;\n if (nCK_PER_CLK == 4) begin: gen_mux_div4\n for (muxr2_i = 0; muxr2_i < DRAM_WIDTH; muxr2_i = muxr2_i + 1) begin: gen_rd_4\n always @(posedge clk) begin\n if (mux_rd_valid_r) begin\n mux_rd_rise0_r2[muxr2_i] <= #TCQ mux_rd_rise0_r1[muxr2_i];\n mux_rd_fall0_r2[muxr2_i] <= #TCQ mux_rd_fall0_r1[muxr2_i];\n mux_rd_rise1_r2[muxr2_i] <= #TCQ mux_rd_rise1_r1[muxr2_i];\n mux_rd_fall1_r2[muxr2_i] <= #TCQ mux_rd_fall1_r1[muxr2_i];\n mux_rd_rise2_r2[muxr2_i] <= #TCQ mux_rd_rise2_r1[muxr2_i];\n mux_rd_fall2_r2[muxr2_i] <= #TCQ mux_rd_fall2_r1[muxr2_i];\n mux_rd_rise3_r2[muxr2_i] <= #TCQ mux_rd_rise3_r1[muxr2_i];\n mux_rd_fall3_r2[muxr2_i] <= #TCQ mux_rd_fall3_r1[muxr2_i];\n end\n //pipeline stage\n mux_rd_rise0_r3[muxr2_i] <= #TCQ mux_rd_rise0_r2[muxr2_i];\n mux_rd_fall0_r3[muxr2_i] <= #TCQ mux_rd_fall0_r2[muxr2_i];\n mux_rd_rise1_r3[muxr2_i] <= #TCQ mux_rd_rise1_r2[muxr2_i];\n mux_rd_fall1_r3[muxr2_i] <= #TCQ mux_rd_fall1_r2[muxr2_i];\n mux_rd_rise2_r3[muxr2_i] <= #TCQ mux_rd_rise2_r2[muxr2_i];\n mux_rd_fall2_r3[muxr2_i] <= #TCQ mux_rd_fall2_r2[muxr2_i];\n mux_rd_rise3_r3[muxr2_i] <= #TCQ mux_rd_rise3_r2[muxr2_i];\n mux_rd_fall3_r3[muxr2_i] <= #TCQ mux_rd_fall3_r2[muxr2_i];\n //pipeline stage\n mux_rd_rise0_r4[muxr2_i] <= #TCQ mux_rd_rise0_r3[muxr2_i];\n mux_rd_fall0_r4[muxr2_i] <= #TCQ mux_rd_fall0_r3[muxr2_i];\n mux_rd_rise1_r4[muxr2_i] <= #TCQ mux_rd_rise1_r3[muxr2_i];\n mux_rd_fall1_r4[muxr2_i] <= #TCQ mux_rd_fall1_r3[muxr2_i];\n mux_rd_rise2_r4[muxr2_i] <= #TCQ mux_rd_rise2_r3[muxr2_i];\n mux_rd_fall2_r4[muxr2_i] <= #TCQ mux_rd_fall2_r3[muxr2_i];\n mux_rd_rise3_r4[muxr2_i] <= #TCQ mux_rd_rise3_r3[muxr2_i];\n mux_rd_fall3_r4[muxr2_i] <= #TCQ mux_rd_fall3_r3[muxr2_i];\n end\n end\n end else if (nCK_PER_CLK == 2) begin: gen_mux_div2\n for (muxr2_i = 0; muxr2_i < DRAM_WIDTH; muxr2_i = muxr2_i + 1) begin: gen_rd_2\n always @(posedge clk) begin\n if (mux_rd_valid_r) begin\n mux_rd_rise0_r2[muxr2_i] <= #TCQ mux_rd_rise0_r1[muxr2_i];\n mux_rd_fall0_r2[muxr2_i] <= #TCQ mux_rd_fall0_r1[muxr2_i];\n mux_rd_rise1_r2[muxr2_i] <= #TCQ mux_rd_rise1_r1[muxr2_i];\n mux_rd_fall1_r2[muxr2_i] <= #TCQ mux_rd_fall1_r1[muxr2_i]; \n mux_rd_rise2_r2[muxr2_i] <= 'h0;\n mux_rd_fall2_r2[muxr2_i] <= 'h0;\n mux_rd_rise3_r2[muxr2_i] <= 'h0;\n mux_rd_fall3_r2[muxr2_i] <= 'h0;\n end\n mux_rd_rise0_r3[muxr2_i] <= #TCQ mux_rd_rise0_r2[muxr2_i];\n mux_rd_fall0_r3[muxr2_i] <= #TCQ mux_rd_fall0_r2[muxr2_i];\n mux_rd_rise1_r3[muxr2_i] <= #TCQ mux_rd_rise1_r2[muxr2_i];\n mux_rd_fall1_r3[muxr2_i] <= #TCQ mux_rd_fall1_r2[muxr2_i];\n mux_rd_rise2_r3[muxr2_i] <= 'h0;\n mux_rd_fall2_r3[muxr2_i] <= 'h0;\n mux_rd_rise3_r3[muxr2_i] <= 'h0;\n mux_rd_fall3_r3[muxr2_i] <= 'h0;\n\n //pipeline stage\n mux_rd_rise0_r4[muxr2_i] <= #TCQ mux_rd_rise0_r3[muxr2_i];\n mux_rd_fall0_r4[muxr2_i] <= #TCQ mux_rd_fall0_r3[muxr2_i];\n mux_rd_rise1_r4[muxr2_i] <= #TCQ mux_rd_rise1_r3[muxr2_i];\n mux_rd_fall1_r4[muxr2_i] <= #TCQ mux_rd_fall1_r3[muxr2_i];\n mux_rd_rise2_r4[muxr2_i] <= 'h0;\n mux_rd_fall2_r4[muxr2_i] <= 'h0;\n mux_rd_rise3_r4[muxr2_i] <= 'h0;\n mux_rd_fall3_r4[muxr2_i] <= 'h0;\n end\n end\n end\n endgenerate\n\n \n // Registered signal indicates when mux_rd_rise/fall_r is valid\n always @(posedge clk) begin\n mux_rd_valid_r <= #TCQ ~phy_if_empty && prbs_rdlvl_start;\n rd_valid_r1 <= #TCQ mux_rd_valid_r;\n rd_valid_r2 <= #TCQ rd_valid_r1;\n rd_valid_r3 <= #TCQ rd_valid_r2;\n end\n \n\n\n \n// Counter counts # of samples compared\n// Reset sample counter when not \"sampling\"\n// Otherwise, count # of samples compared\n// Same counter is shared for three samples checked\n always @(posedge clk)\n if (rst)\n samples_cnt_r <= #TCQ 'b0;\n else if (samples_cnt_r == NUM_SAMPLES_CNT) begin\n samples_cnt_r <= #TCQ 'b0;\n end else if (complex_sample_cnt_inc) begin\n samples_cnt_r <= #TCQ samples_cnt_r + 1;\n /*if (!rd_valid_r1 ||\n (prbs_state_r == PRBS_DEC_DQS_WAIT) ||\n (prbs_state_r == PRBS_INC_DQS_WAIT) ||\n (prbs_state_r == PRBS_DEC_DQS) ||\n (prbs_state_r == PRBS_INC_DQS) ||\n (samples_cnt_r == NUM_SAMPLES_CNT) ||\n (samples_cnt_r == NUM_SAMPLES_CNT1))\n samples_cnt_r <= #TCQ 'b0;\n else if (rd_valid_r1 && \n (((samples_cnt_r < NUM_SAMPLES_CNT) && ~samples_cnt1_en_r) ||\n ((samples_cnt_r < NUM_SAMPLES_CNT1) && ~samples_cnt2_en_r) ||\n ((samples_cnt_r < NUM_SAMPLES_CNT2) && samples_cnt2_en_r)))\n samples_cnt_r <= #TCQ samples_cnt_r + 1;*/\n end\n\n// Count #2 enable generation\n// Assert when correct number of samples compared\n always @(posedge clk)\n if (rst)\n samples_cnt1_en_r <= #TCQ 1'b0;\n else begin \n if ((prbs_state_r == PRBS_IDLE) || \n (prbs_state_r == PRBS_DEC_DQS) ||\n (prbs_state_r == PRBS_INC_DQS) ||\n (prbs_state_r == FINE_PI_INC) ||\n (prbs_state_r == PRBS_NEW_DQS_PREWAIT))\n samples_cnt1_en_r <= #TCQ 1'b0;\n else if ((samples_cnt_r == NUM_SAMPLES_CNT) && rd_valid_r1)\n samples_cnt1_en_r <= #TCQ 1'b1;\n end\n\n// Counter #3 enable generation\n// Assert when correct number of samples compared\n always @(posedge clk)\n if (rst)\n samples_cnt2_en_r <= #TCQ 1'b0;\n else begin \n if ((prbs_state_r == PRBS_IDLE) || \n (prbs_state_r == PRBS_DEC_DQS) ||\n (prbs_state_r == PRBS_INC_DQS) ||\n (prbs_state_r == FINE_PI_INC) ||\n (prbs_state_r == PRBS_NEW_DQS_PREWAIT))\n samples_cnt2_en_r <= #TCQ 1'b0;\n else if ((samples_cnt_r == NUM_SAMPLES_CNT1) && rd_valid_r1 && samples_cnt1_en_r)\n samples_cnt2_en_r <= #TCQ 1'b1;\n end\n\n// Victim selection logic\n always @(posedge clk)\n if (rst)\n rd_victim_sel <= #TCQ 'd0;\n else if (num_samples_done_r)\n rd_victim_sel <= #TCQ 'd0;\n else if (samples_cnt_r == NUM_SAMPLES_CNT) begin\n if (rd_victim_sel < 'd7)\n rd_victim_sel <= #TCQ rd_victim_sel + 1;\n end\n \n// Output row count increment pulse to phy_init\n always @(posedge clk)\n if (rst)\n complex_victim_inc <= #TCQ 1'b0;\n else if (samples_cnt_r == NUM_SAMPLES_CNT)\n complex_victim_inc <= #TCQ 1'b1;\n else\n complex_victim_inc <= #TCQ 1'b0;\n \ngenerate\n if (FIXED_VICTIM == \"TRUE\") begin: victim_fixed\n always @(posedge clk)\n if (rst)\n num_samples_done_r <= #TCQ 1'b0;\n else if ((prbs_state_r == PRBS_DEC_DQS) ||\n (prbs_state_r == PRBS_INC_DQS)||\n (prbs_state_r == FINE_PI_INC) ||\n (prbs_state_r == FINE_PI_DEC))\n num_samples_done_r <= #TCQ 'b0;\n else if (samples_cnt_r == NUM_SAMPLES_CNT)\n num_samples_done_r <= #TCQ 1'b1;\n end else begin: victim_not_fixed\n always @(posedge clk)\n if (rst)\n num_samples_done_r <= #TCQ 1'b0;\n else if ((prbs_state_r == PRBS_DEC_DQS) ||\n (prbs_state_r == PRBS_INC_DQS)||\n (prbs_state_r == FINE_PI_INC) ||\n (prbs_state_r == FINE_PI_DEC))\n num_samples_done_r <= #TCQ 'b0;\n else if ((samples_cnt_r == NUM_SAMPLES_CNT) && (rd_victim_sel == 'd7))\n num_samples_done_r <= #TCQ 1'b1;\n end\nendgenerate\n \n \n //***************************************************************************\n // Compare Read Data for the byte being Leveled with Expected data from PRBS\n // generator. Resulting compare_err signal used to determine read data valid\n // edge.\n //***************************************************************************\n generate\n if (nCK_PER_CLK == 4) begin: cmp_err_4to1\n always @ (posedge clk) begin\n if (rst || new_cnt_dqs_r || (prbs_state_r == PRBS_INC_DQS) || (prbs_state_r == PRBS_DEC_DQS)) begin\n compare_err <= #TCQ 1'b0;\n compare_err_r0 <= #TCQ 1'b0;\n compare_err_f0 <= #TCQ 1'b0;\n compare_err_r1 <= #TCQ 1'b0;\n compare_err_f1 <= #TCQ 1'b0;\n compare_err_r2 <= #TCQ 1'b0;\n compare_err_f2 <= #TCQ 1'b0;\n compare_err_r3 <= #TCQ 1'b0;\n compare_err_f3 <= #TCQ 1'b0;\n end else if (rd_valid_r2) begin\n compare_err_r0 <= #TCQ (mux_rd_rise0_r3 != compare_data_rise0_r1);\n compare_err_f0 <= #TCQ (mux_rd_fall0_r3 != compare_data_fall0_r1);\n compare_err_r1 <= #TCQ (mux_rd_rise1_r3 != compare_data_rise1_r1);\n compare_err_f1 <= #TCQ (mux_rd_fall1_r3 != compare_data_fall1_r1);\n compare_err_r2 <= #TCQ (mux_rd_rise2_r3 != compare_data_rise2_r1);\n compare_err_f2 <= #TCQ (mux_rd_fall2_r3 != compare_data_fall2_r1);\n compare_err_r3 <= #TCQ (mux_rd_rise3_r3 != compare_data_rise3_r1);\n compare_err_f3 <= #TCQ (mux_rd_fall3_r3 != compare_data_fall3_r1);\n compare_err <= #TCQ (compare_err_r0 | compare_err_f0 |\n compare_err_r1 | compare_err_f1 |\n compare_err_r2 | compare_err_f2 |\n compare_err_r3 | compare_err_f3);\n end\n end\n end else begin: cmp_err_2to1\n always @ (posedge clk) begin\n if (rst || new_cnt_dqs_r || (prbs_state_r == PRBS_INC_DQS) || (prbs_state_r == PRBS_DEC_DQS)) begin\n compare_err <= #TCQ 1'b0;\n compare_err_r0 <= #TCQ 1'b0;\n compare_err_f0 <= #TCQ 1'b0;\n compare_err_r1 <= #TCQ 1'b0;\n compare_err_f1 <= #TCQ 1'b0;\n end else if (rd_valid_r2) begin\n compare_err_r0 <= #TCQ (mux_rd_rise0_r3 != compare_data_rise0_r1);\n compare_err_f0 <= #TCQ (mux_rd_fall0_r3 != compare_data_fall0_r1);\n compare_err_r1 <= #TCQ (mux_rd_rise1_r3 != compare_data_rise1_r1);\n compare_err_f1 <= #TCQ (mux_rd_fall1_r3 != compare_data_fall1_r1);\n compare_err <= #TCQ (compare_err_r0 | compare_err_f0 |\n compare_err_r1 | compare_err_f1);\n end\n end\n end\n endgenerate\n\n //Sticky bit compare_err\n always @ (posedge clk)\n if (prbs_state_r == PRBS_PAT_COMPARE)\n compare_err_latch <= #TCQ compare_err? 1'b1: compare_err_latch;\n else \n compare_err_latch <= #TCQ 1'b0;\n \n//***************************************************************************\n// Decrement initial Phaser_IN fine delay value before proceeding with\n// read calibration\n//***************************************************************************\n \n \n//***************************************************************************\n// Demultiplexor to control Phaser_IN delay values\n//***************************************************************************\n\n// Read DQS\n always @(posedge clk) begin\n if (rst) begin\n pi_en_stg2_f_timing <= #TCQ 'b0;\n pi_stg2_f_incdec_timing <= #TCQ 'b0;\n end else if (prbs_tap_en_r) begin\n// Change only specified DQS\n pi_en_stg2_f_timing <= #TCQ 1'b1; \n pi_stg2_f_incdec_timing <= #TCQ prbs_tap_inc_r;\n end else begin\n pi_en_stg2_f_timing <= #TCQ 'b0;\n pi_stg2_f_incdec_timing <= #TCQ 'b0;\n end\n end\n\n// registered for timing \n always @(posedge clk) begin\n pi_en_stg2_f <= #TCQ pi_en_stg2_f_timing;\n pi_stg2_f_incdec <= #TCQ pi_stg2_f_incdec_timing;\n end\n \n//***************************************************************************\n// generate request to PHY_INIT logic to issue precharged. Required when\n// calibration can take a long time (during which there are only constant\n// reads present on this bus). In this case need to issue perioidic\n// precharges to avoid tRAS violation. This signal must meet the following\n// requirements: (1) only transition from 0->1 when prech is first needed,\n// (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted\n//***************************************************************************\n\n always @(posedge clk)\n if (rst)\n prbs_rdlvl_prech_req <= #TCQ 1'b0;\n else\n prbs_rdlvl_prech_req <= #TCQ prbs_prech_req_r;\n\n//*****************************************************************\n// keep track of edge tap counts found, and current capture clock\n// tap count\n//*****************************************************************\n\n always @(posedge clk)\n if (rst) begin\n prbs_dqs_tap_cnt_r <= #TCQ 'b0;\n rdlvl_cpt_tap_cnt <= #TCQ 'b0;\n end else if (new_cnt_dqs_r) begin\n prbs_dqs_tap_cnt_r <= #TCQ pi_counter_read_val;\n rdlvl_cpt_tap_cnt <= #TCQ pi_counter_read_val;\n end else if (prbs_tap_en_r) begin\n if (prbs_tap_inc_r)\n prbs_dqs_tap_cnt_r <= #TCQ prbs_dqs_tap_cnt_r + 1;\n else if (prbs_dqs_tap_cnt_r != 'd0)\n prbs_dqs_tap_cnt_r <= #TCQ prbs_dqs_tap_cnt_r - 1;\n end\n \n always @(posedge clk)\n if (rst) begin\n prbs_dec_tap_calc_plus_3 <= #TCQ 'b0;\n prbs_dec_tap_calc_minus_3 <= #TCQ 'b0;\n end else if (new_cnt_dqs_r) begin\n prbs_dec_tap_calc_plus_3 <= #TCQ 'b000011;\n prbs_dec_tap_calc_minus_3 <= #TCQ 'b111100;\n end else begin\n prbs_dec_tap_calc_plus_3 <= #TCQ (prbs_dqs_tap_cnt_r - rdlvl_cpt_tap_cnt + 3);\n prbs_dec_tap_calc_minus_3 <= #TCQ (prbs_dqs_tap_cnt_r - rdlvl_cpt_tap_cnt - 3);\n end\n\n always @(posedge clk)\n if (rst || new_cnt_dqs_r)\n prbs_dqs_tap_limit_r <= #TCQ 1'b0;\n else if (prbs_dqs_tap_cnt_r == 6'd63)\n prbs_dqs_tap_limit_r <= #TCQ 1'b1;\n else\n prbs_dqs_tap_limit_r <= #TCQ 1'b0;\n\n // Temp wire for timing.\n // The following in the always block below causes timing issues\n // due to DSP block inference\n // 6*prbs_dqs_cnt_r.\n // replacing this with two left shifts + one left shift to avoid\n // DSP multiplier.\n\n assign prbs_dqs_cnt_timing = {2'd0, prbs_dqs_cnt_r};\n\n\n always @(posedge clk)\n prbs_dqs_cnt_timing_r <= #TCQ prbs_dqs_cnt_timing;\n \n\n // Storing DQS tap values at the end of each DQS read leveling\n always @(posedge clk) begin\n if (rst) begin\n prbs_final_dqs_tap_cnt_r <= #TCQ 'b0;\n end else if ((prbs_state_r == PRBS_NEXT_DQS) && (prbs_state_r1 != PRBS_NEXT_DQS)) begin\n prbs_final_dqs_tap_cnt_r[(prbs_dqs_cnt_timing_r*6)+:6]\n <= #TCQ prbs_dqs_tap_cnt_r;\n end\n end\n\n\n\n\n //*****************************************************************\n \n always @(posedge clk) begin\n prbs_state_r1 <= #TCQ prbs_state_r;\n prbs_rdlvl_start_r <= #TCQ prbs_rdlvl_start;\n end\n \n// Wait counter for wait states\n always @(posedge clk)\n if ((prbs_state_r == PRBS_NEW_DQS_WAIT) ||\n (prbs_state_r == PRBS_INC_DQS_WAIT) ||\n (prbs_state_r == PRBS_DEC_DQS_WAIT) ||\n (prbs_state_r == FINE_PI_DEC_WAIT) ||\n (prbs_state_r == FINE_PI_INC_WAIT) ||\n (prbs_state_r == PRBS_NEW_DQS_PREWAIT))\n wait_state_cnt_en_r <= #TCQ 1'b1;\n else\n wait_state_cnt_en_r <= #TCQ 1'b0;\n \n always @(posedge clk)\n if (!wait_state_cnt_en_r) begin\n wait_state_cnt_r <= #TCQ 'b0;\n cnt_wait_state <= #TCQ 1'b0;\n end else begin\n if (wait_state_cnt_r < 'd15) begin\n wait_state_cnt_r <= #TCQ wait_state_cnt_r + 1;\n cnt_wait_state <= #TCQ 1'b0;\n end else begin\n // Need to reset to 0 to handle the case when there are two\n // different WAIT states back-to-back\n wait_state_cnt_r <= #TCQ 'b0; \n cnt_wait_state <= #TCQ 1'b1;\n end\n end\n\n always @ (posedge clk)\n err_chk_invalid <= #TCQ (wait_state_cnt_r < 'd14);\n \n\n//*****************************************************************\n// compare error checking per-bit\n//****************************************************************\n\n generate \n genvar pb_i;\n if (nCK_PER_CLK == 4) begin: cmp_err_pb_4to1\n for(pb_i=0 ; pb_i prbs_dqs_tap_cnt_r -(MIN_WIN-1))? 'd0\n : prbs_dqs_tap_cnt_r-(MIN_WIN-1)-left_edge_ref;\n //right edge is updated when match flag becomes 000000001 (8 success, 1 fail)\n end else if (match_flag_pb[eg*MIN_WIN+:MIN_WIN]== MIN_PASS && compare_err_pb_latch_r[eg]) begin \n right_edge_pb[eg*6+:6] <= #TCQ prbs_dqs_tap_cnt_r-1;\n right_edge_found_pb[eg] <= #TCQ 1'b1;\n //check the gain of bit - update only for right edge found\n if(~right_edge_found_pb[eg]) \n right_gain_pb[eg*6+:6] <= #TCQ (right_edge_ref > prbs_dqs_tap_cnt_r-1)?\n ((right_edge_pb[eg*6 +:6] > prbs_dqs_tap_cnt_r-1)? 0: prbs_dqs_tap_cnt_r-1- right_edge_pb[eg*6+:6]):\n ((right_edge_pb[eg*6+:6] > right_edge_ref)? 0 : right_edge_ref - right_edge_pb[eg*6+:6]);\n //no right edge found\n end else if (prbs_dqs_tap_cnt_r == 6'h3f && ~right_edge_found_pb[eg]) begin\n right_edge_pb[eg*6+:6] <= #TCQ 6'h3f;\n right_edge_found_pb[eg] <= #TCQ 1'b1;\n //right edge at 63. gain = max(0, ref_bit_right_tap - prev_right_edge)\n right_gain_pb[eg*6+:6] <= #TCQ (right_edge_ref > right_edge_pb[eg*6+:6])?\n (right_edge_ref - right_edge_pb[eg*6+:6]) : 0;\n end\n //update match flag - shift and update\n match_flag_pb[eg*MIN_WIN+:MIN_WIN] <= #TCQ {match_flag_pb[(eg*MIN_WIN)+:(MIN_WIN-1)],compare_err_pb_latch_r[eg]};\n end else if (prbs_state_r == FINE_PI_DEC) begin\n left_edge_found_pb[eg] <= #TCQ 1'b0;\n right_edge_found_pb[eg] <= #TCQ 1'b0;\n left_loss_pb[eg*6+:6] <= #TCQ 'b0;\n right_gain_pb[eg*6+:6] <= #TCQ 'b0; \n match_flag_pb[eg*MIN_WIN+:MIN_WIN] <= #TCQ MATCH_ALL_ONE ; //new fix\n left_edge_updated[eg] <= #TCQ 'b0; //used only for update largest ref_bit and largest_left_edge\n end else if (prbs_state_r == FINE_PI_INC) begin\n left_edge_updated[eg] <= #TCQ 'b0; //used only for update largest ref_bit and largest_left_edge\n end\n end\n end //always\n end //for\n endgenerate\n\n //update fine_delay according to loss/gain value per bit\n generate \n genvar f_pb;\n for(f_pb=0; f_pbleft_loss_pb[f_pb*6+:6])?1'b1:1'b0;\n end\n end\n end\n endgenerate\n \n //fine inc stage (stage cnt 0,1,2), fine dec stage (stage cnt 3)\n always @ (posedge clk) begin\n if (rst)\n fine_inc_stage <= #TCQ 'b1;\n else\n fine_inc_stage <= #TCQ (stage_cnt!='d3);\n end\n//*****************************************************************\n \n always @(posedge clk)\n if (rst) begin\n prbs_dqs_cnt_r <= #TCQ 'b0;\n prbs_tap_en_r <= #TCQ 1'b0;\n prbs_tap_inc_r <= #TCQ 1'b0;\n prbs_prech_req_r <= #TCQ 1'b0;\n prbs_state_r <= #TCQ PRBS_IDLE;\n prbs_found_1st_edge_r <= #TCQ 1'b0;\n prbs_found_2nd_edge_r <= #TCQ 1'b0;\n prbs_1st_edge_taps_r <= #TCQ 6'bxxxxxx;\n prbs_inc_tap_cnt <= #TCQ 'b0;\n prbs_dec_tap_cnt <= #TCQ 'b0;\n new_cnt_dqs_r <= #TCQ 1'b0;\n if (SIM_CAL_OPTION == \"FAST_CAL\")\n prbs_rdlvl_done <= #TCQ 1'b1;\n else\n prbs_rdlvl_done <= #TCQ 1'b0;\n prbs_2nd_edge_taps_r <= #TCQ 6'bxxxxxx;\n prbs_last_byte_done <= #TCQ 1'b0;\n prbs_tap_mod <= #TCQ 'd0;\n reset_rd_addr <= #TCQ 'b0;\n fine_pi_dec_cnt <= #TCQ 'b0; \n match_flag_and <= #TCQ MATCH_ALL_ONE;\n match_flag_or <= #TCQ MATCH_ALL_ONE;\n no_err_win_detected <= #TCQ 1'b0; \n no_err_win_detected_latch <= #TCQ 1'b0; \n valid_window_cnt <= 2'd0;\n stage_cnt <= #TCQ 2'b00;\n right_edge_found <= #TCQ 1'b0;\n largest_left_edge <= #TCQ 6'b000000;\n smallest_right_edge <= #TCQ 6'b111111;\n num_samples_done_ind <= #TCQ 'b0;\n fine_delay_sel <= #TCQ 'b0;\n fine_dly_error <= #TCQ 'b0;\n edge_det_error <= #TCQ 'b0;\n complex_pi_incdec_done <= #TCQ 1'b0;\n complex_init_pi_dec_done_r <= #TCQ 1'b0;\n end else begin\n \n case (prbs_state_r)\n \n PRBS_IDLE: begin\n prbs_last_byte_done <= #TCQ 1'b0;\n prbs_prech_req_r <= #TCQ 1'b0;\n if (prbs_rdlvl_start && ~prbs_rdlvl_start_r) begin\n if (SIM_CAL_OPTION == \"SKIP_CAL\" || SIM_CAL_OPTION == \"FAST_CAL\") begin\n prbs_state_r <= #TCQ PRBS_DONE;\n reset_rd_addr <= #TCQ 1'b1;\n end else begin\n new_cnt_dqs_r <= #TCQ 1'b1; \n prbs_state_r <= #TCQ PRBS_NEW_DQS_WAIT;\n fine_pi_dec_cnt <= #TCQ pi_counter_read_val;//.\n end\n end\n end\n \n // Wait for the new DQS group to change\n // also gives time for the read data IN_FIFO to\n // output the updated data for the new DQS group\n PRBS_NEW_DQS_WAIT: begin\n reset_rd_addr <= #TCQ 'b0;\n prbs_last_byte_done <= #TCQ 1'b0;\n prbs_prech_req_r <= #TCQ 1'b0;\n stage_cnt <= #TCQ 2'b0;\n match_flag_and <= #TCQ MATCH_ALL_ONE;\n match_flag_or <= #TCQ MATCH_ALL_ONE;\n no_err_win_detected <= #TCQ 1'b0;\n no_err_win_detected_latch <= #TCQ 1'b0;\n if (cnt_wait_state) begin\n new_cnt_dqs_r <= #TCQ 1'b0;\n prbs_state_r <= #TCQ fine_calib? FINE_PI_DEC:PRBS_PAT_COMPARE;\n //For normal, it doesn't have initial pi incdec\n complex_pi_incdec_done <= #TCQ fine_calib? complex_pi_incdec_done: 1'b1;\n end\n end\n\n // Check for presence of data eye edge. During this state, we\n // sample the read data multiple times, and look for changes\n // in the read data, specifically:\n // 1. A change in the read data compared with the value of\n // read data from the previous delay tap. This indicates \n // that the most recent tap delay increment has moved us\n // into either a new window, or moved/kept us in the\n // transition/jitter region between windows. Note that this\n // condition only needs to be checked for once, and for\n // logistical purposes, we check this soon after entering\n // this state (see comment in PRBS_PAT_COMPARE below for \n // why this is done)\n // 2. A change in the read data while we are in this state\n // (i.e. in the absence of a tap delay increment). This\n // indicates that we're close enough to a window edge that\n // jitter will cause the read data to change even in the\n // absence of a tap delay change \n PRBS_PAT_COMPARE: begin\n // Continue to sample read data and look for edges until the\n // appropriate time interval (shorter for simulation-only, \n // much, much longer for actual h/w) has elapsed\n //comparision started - wait for next PI movement after read\n complex_pi_incdec_done <= #TCQ 1'b0; //need to be wait for new incdec done \n if (num_samples_done_r) begin\n if (prbs_dqs_tap_limit_r)\n // Only one edge detected and ran out of taps since only one\n // bit time worth of taps available for window detection. This\n // can happen if at tap 0 DQS is in previous window which results\n // in only left edge being detected. Or at tap 0 DQS is in the\n // current window resulting in only right edge being detected.\n // Depending on the frequency this case can also happen if at\n // tap 0 DQS is in the left noise region resulting in only left\n // edge being detected.\n prbs_state_r <= #TCQ PRBS_CALC_TAPS_PRE;\n else if (compare_err_latch || (prbs_dqs_tap_cnt_r == 'd0)) begin \n // Sticky bit - asserted after we encounter an edge, although\n // the current edge may not be considered the \"first edge\" this\n // just means we found at least one edge\n prbs_found_1st_edge_r <= #TCQ 1'b1;\n \n // Both edges of data valid window found:\n // If we've found a second edge after a region of stability\n // then we must have just passed the second (\"right\" edge of\n // the window. Record this second_edge_taps = current tap-1, \n // because we're one past the actual second edge tap, where \n // the edge taps represent the extremes of the data valid \n // window (i.e. smallest & largest taps where data still valid\n if (prbs_found_1st_edge_r) begin\n prbs_found_2nd_edge_r <= #TCQ 1'b1;\n prbs_2nd_edge_taps_r <= #TCQ prbs_dqs_tap_cnt_r - 1;\n prbs_state_r <= #TCQ PRBS_CALC_TAPS_PRE;\n end else begin\n // Otherwise, an edge was found (just not the \"second\" edge)\n // Assuming DQS is in the correct window at tap 0 of Phaser IN\n // fine tap. The first edge found is the right edge of the valid\n // window and is the beginning of the jitter region hence done!\n if (compare_err_latch)\n prbs_1st_edge_taps_r <= #TCQ prbs_dqs_tap_cnt_r + 1;\n else\n prbs_1st_edge_taps_r <= #TCQ 'd0;\n \n prbs_inc_tap_cnt <= #TCQ rdlvl_cpt_tap_cnt - prbs_dqs_tap_cnt_r; \n prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_INC;\n end\n end else begin\n // Otherwise, if we haven't found an edge.... \n // If we still have taps left to use, then keep incrementing\n if (prbs_found_1st_edge_r)\n //prbs_state_r <= #TCQ PRBS_INC_DQS;\n prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_INC;\n else\n //prbs_state_r <= #TCQ PRBS_DEC_DQS;\n prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_DEC;\n end\n end \n end\n \n // Increment Phaser_IN delay for DQS\n PRBS_INC_DQS: begin\n prbs_state_r <= #TCQ PRBS_INC_DQS_WAIT;\n if (prbs_inc_tap_cnt > 'd0)\n prbs_inc_tap_cnt <= #TCQ prbs_inc_tap_cnt - 1;\n if (~prbs_dqs_tap_limit_r) begin\n prbs_tap_en_r <= #TCQ 1'b1;\n prbs_tap_inc_r <= #TCQ 1'b1;\n end\n end\n\n // Wait for Phaser_In to settle, before checking again for an edge \n // only all INC is done, incdec done is asserted \n PRBS_INC_DQS_WAIT: begin\n prbs_tap_en_r <= #TCQ 1'b0;\n prbs_tap_inc_r <= #TCQ 1'b0; \n if (cnt_wait_state) begin\n if (prbs_inc_tap_cnt > 'd0)\n prbs_state_r <= #TCQ PRBS_INC_DQS; //centering\n else begin\n prbs_state_r <= #TCQ PRBS_PAT_COMPARE;\n complex_pi_incdec_done <= #TCQ 1'b1;\n end\n end\n end\n \n // Calculate final value of Phaser_IN taps. At this point, one or both\n // edges of data eye have been found, and/or all taps have been\n // exhausted looking for the edges\n // NOTE: The amount to be decrement by is calculated, not the\n // absolute setting for DQS.\n // CENTER compensation with shift by 1 \n //wait finishing the read before PI dec to center\n PRBS_CALC_TAPS: begin\n if (center_comp) begin\n prbs_dec_tap_cnt <= #TCQ (dec_cnt[5] & dec_cnt[0])? 'd32: dec_cnt + pi_adj;\n fine_dly_error <= #TCQ (dec_cnt[5] & dec_cnt[0])? 1'b1: fine_dly_error; //sticky bit\n prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_DEC;\n end else begin //No center compensation\n if (prbs_found_2nd_edge_r && prbs_found_1st_edge_r) begin\n // Both edges detected\n prbs_dec_tap_cnt \n <= #TCQ ((prbs_2nd_edge_taps_r -\n prbs_1st_edge_taps_r)>>1) + 1 + pi_adj; \n edge_det_error <= #TCQ edge_det_error? 1'b1: \n (prbs_1st_edge_taps_r >= prbs_2nd_edge_taps_r);\n end else if (~prbs_found_2nd_edge_r && prbs_found_1st_edge_r) begin\n // Only left edge detected \n prbs_dec_tap_cnt \n <= #TCQ ((prbs_dqs_tap_cnt_r - prbs_1st_edge_taps_r)>>1) + pi_adj; \n end else begin\n // No edges detected\n edge_det_error <= #TCQ 1'b1;\n prbs_dec_tap_cnt \n <= #TCQ (prbs_dqs_tap_cnt_r>>1) + pi_adj; \n end\n // Now use the value we just calculated to decrement CPT taps\n // to the desired calibration point\n //wait finishing the read before PI dec to center\n prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_DEC;\n end\n end\n \n // decrement capture clock for final adjustment - center\n // capture clock in middle of data eye. This adjustment will occur\n // only when both the edges are found usign CPT taps. Must do this\n // incrementally to avoid clock glitching (since CPT drives clock\n // divider within each ISERDES)\n PRBS_DEC_DQS: begin\n prbs_tap_en_r <= #TCQ 1'b1;\n prbs_tap_inc_r <= #TCQ 1'b0;\n // once adjustment is complete, we're done with calibration for\n // this DQS, repeat for next DQS\n if (prbs_dec_tap_cnt > 'd0)\n prbs_dec_tap_cnt <= #TCQ prbs_dec_tap_cnt - 1;\n if (prbs_dec_tap_cnt == 6'b000001) begin\n prbs_state_r <= #TCQ PRBS_NEXT_DQS;\n //only all DEC is done, incdec done is asserted \n complex_pi_incdec_done <= #TCQ 1'b1; \n end else\n prbs_state_r <= #TCQ PRBS_DEC_DQS_WAIT;\n end\n\n PRBS_DEC_DQS_WAIT: begin\n prbs_tap_en_r <= #TCQ 1'b0;\n prbs_tap_inc_r <= #TCQ 1'b0;\n if (cnt_wait_state) begin\n if (prbs_dec_tap_cnt > 'd0)\n prbs_state_r <= #TCQ PRBS_DEC_DQS;\n else begin \n //PI movement is done, go to read and compare\n complex_pi_incdec_done <= #TCQ 1'b1;\n prbs_state_r <= #TCQ PRBS_PAT_COMPARE;\n end\n end\n end\n\n // Determine whether we're done, or have more DQS's to calibrate\n // Also request precharge after every byte, as appropriate\n PRBS_NEXT_DQS: begin\n //Need to do initial dec for per-bit algorithm\n complex_init_pi_dec_done_r <= #TCQ 1'b0;\n reset_rd_addr <= #TCQ 'b1; \n prbs_prech_req_r <= #TCQ 1'b1;\n prbs_tap_en_r <= #TCQ 1'b0;\n prbs_tap_inc_r <= #TCQ 1'b0;\n // Prepare for another iteration with next DQS group\n prbs_found_1st_edge_r <= #TCQ 1'b0;\n prbs_found_2nd_edge_r <= #TCQ 1'b0;\n prbs_1st_edge_taps_r <= #TCQ 'd0;\n prbs_2nd_edge_taps_r <= #TCQ 'd0;\n largest_left_edge <= #TCQ 6'b000000;\n smallest_right_edge <= #TCQ 6'b111111;\n if (prbs_dqs_cnt_r >= DQS_WIDTH-1) begin\n prbs_last_byte_done <= #TCQ 1'b1;\n end\n \n // Wait until precharge that occurs in between calibration of\n // DQS groups is finished\n if (prech_done) begin\n prbs_prech_req_r <= #TCQ 1'b0;\n if (prbs_dqs_cnt_r >= DQS_WIDTH-1) begin\n // All DQS groups done\n prbs_state_r <= #TCQ PRBS_DONE;\n end else begin\n // Process next DQS group\n new_cnt_dqs_r <= #TCQ 1'b1;\n prbs_dqs_cnt_r <= #TCQ prbs_dqs_cnt_r + 1;\n prbs_state_r <= #TCQ PRBS_NEW_DQS_PREWAIT;\n end\n end\n end\n \n PRBS_NEW_DQS_PREWAIT: begin\n if (cnt_wait_state) begin\n prbs_state_r <= #TCQ PRBS_NEW_DQS_WAIT;\n fine_pi_dec_cnt <= #TCQ pi_counter_read_val;//.\n end\n end\n \n PRBS_CALC_TAPS_PRE:\n begin\n //Wait for new PI movement\n complex_pi_incdec_done <= #TCQ 1'b0;\n prbs_state_r <= #TCQ fine_calib? PRBS_NEXT_DQS:PRBS_CALC_TAPS_WAIT;\n if(center_comp && ~fine_calib) begin\n if(prbs_found_1st_edge_r) largest_left_edge <= #TCQ prbs_1st_edge_taps_r;\n else largest_left_edge <= #TCQ 6'd0;\n if(prbs_found_2nd_edge_r) smallest_right_edge <= #TCQ prbs_2nd_edge_taps_r;\n else smallest_right_edge <= #TCQ 6'd63;\n end\n end\n\n //wait for center compensation\n PRBS_CALC_TAPS_WAIT:\n begin\n prbs_state_r <= #TCQ PRBS_CALC_TAPS;\n end\n //if it is fine_inc stage (first/second stage): dec to 0\n //if it is fine_dec stage (third stage): dec to center\n FINE_PI_DEC: begin\n fine_delay_sel <= #TCQ 'b0; \n if(fine_pi_dec_cnt > 0) begin\n prbs_tap_en_r <= #TCQ 1'b1;\n prbs_tap_inc_r <= #TCQ 1'b0;\n fine_pi_dec_cnt <= #TCQ fine_pi_dec_cnt - 'd1;\n end\n prbs_state_r <= #TCQ FINE_PI_DEC_WAIT;\n end\n //wait for phaser_in tap decrement. \n //if first/second stage is done, goes to FINE_PI_INC\n //if last stage is done, goes to NEXT_DQS\n //All PI DEC is done, incdec done is asserted\n FINE_PI_DEC_WAIT: begin\n prbs_tap_en_r <= #TCQ 1'b0;\n prbs_tap_inc_r <= #TCQ 1'b0;\n if(cnt_wait_state) begin\n if(fine_pi_dec_cnt >0)\n prbs_state_r <= #TCQ FINE_PI_DEC;\n else begin \n complex_pi_incdec_done <= #TCQ 1'b1;\n if(fine_inc_stage)\n prbs_state_r <= #TCQ FINE_PAT_COMPARE_PER_BIT; //start from pi tap \"0\"\n else \n prbs_state_r <= #TCQ PRBS_CALC_TAPS_PRE; //finish the process and go to the next DQS\n end\n end\n end\n \n //finish the read before PI increament\n RD_DONE_WAIT_FOR_PI_INC_INC: begin\n if(complex_act_start)\n prbs_state_r <= #TCQ fine_calib? FINE_PI_INC: PRBS_INC_DQS;\n end\n \n FINE_PI_INC: begin\n //prevent left edge update after valid window found\n if(|left_edge_updated && ~no_err_win_detected_latch) largest_left_edge <= #TCQ prbs_dqs_tap_cnt_r- (MIN_WIN-1); \n \n if (no_err_win_detected) begin\n //ignore previous right edge updated if valid window shown after\n right_edge_found <= #TCQ 'b0; \n end else if(|right_edge_found_pb && ~right_edge_found) begin\n smallest_right_edge <= #TCQ prbs_dqs_tap_cnt_r -1 ;\n right_edge_found <= #TCQ 'b1;\n end \n //until minimum window is detected, left edge can be updated\n //once minimum window is detected, no further left edge update will be done\n if(no_err_win_detected) no_err_win_detected_latch <= #TCQ 1'b1;\n prbs_state_r <= #TCQ FINE_PI_INC_WAIT;\n if(~prbs_dqs_tap_limit_r) begin\n prbs_tap_en_r <= #TCQ 1'b1;\n prbs_tap_inc_r <= #TCQ 1'b1;\n end\n end\n \n //wait for phase_in tap increment\n //need to do pattern compare for every bit\n FINE_PI_INC_WAIT: begin\n prbs_tap_en_r <= #TCQ 1'b0;\n prbs_tap_inc_r <= #TCQ 1'b0; \n if (cnt_wait_state) begin\n prbs_state_r <= #TCQ FINE_PAT_COMPARE_PER_BIT;\n //PI movement is done, go to read and compare\n complex_pi_incdec_done <= #TCQ 1'b1;\n end\n end\n \n //compare per bit data and update flags,left/right edge\n FINE_PAT_COMPARE_PER_BIT: begin\n //comparision started - initial pi dec is done, wait for another pi movement after read\n complex_init_pi_dec_done_r <= #TCQ 1'b1;\n complex_pi_incdec_done <= #TCQ 1'b0;\n if(num_samples_done_r) begin //sampling boundary\n //update and_flag - shift and add\n match_flag_and <= #TCQ {match_flag_and[MIN_WIN-2:0],compare_err_pb_and};\n match_flag_or <= #TCQ {match_flag_or[MIN_WIN-2:0],compare_err_pb_or};\n\n //to solve false left/right edge detection\n if({match_flag_or[MIN_WIN-2:0],compare_err_pb_or} == MIN_PASS) begin //if it detect minimum window\n no_err_win_detected <= #TCQ 1'b1;\n valid_window_cnt <= #TCQ valid_window_cnt + 'd1;\n end else begin\n no_err_win_detected <= #TCQ 1'b0;\n end\n //if it is consecutive 8 passing taps followed by fail or tap limit (finish the search)\n //don't go to fine_FINE_CALC_TAPS to prevent to skip whole stage\n //Or if all right edge are found\n if((match_flag_and == MIN_PASS && compare_err_pb_and && (prbs_dqs_tap_cnt_r > MIN_WIN )) || prbs_dqs_tap_limit_r || (&right_edge_found_pb)) begin \n prbs_state_r <= #TCQ FINE_CALC_TAPS; \n //if all right edge are alined (all right edge found at the same time), update smallest right edge in here\n //doesnt need to set right_edge_found to 1 since it is not used after this stage\n if(!right_edge_found) smallest_right_edge <= #TCQ prbs_dqs_tap_cnt_r-1; \n end else begin\n prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_INC; //keep increase until all fail \n end\n num_samples_done_ind <= num_samples_done_r;\n end \n end\n //for fine_inc stage, inc all fine delay\n //for fine_dec stage, apply dec fine delay for specific bits (by calculating the loss/gain)\n // put phaser_in taps to the center\n FINE_CALC_TAPS: begin\n if(num_samples_done_ind || num_samples_done_r) begin\n num_samples_done_ind <= #TCQ 'b0; //indicate num_samples_done_r is set \n right_edge_found <= #TCQ 1'b0; //reset right edge found\n match_flag_and <= #TCQ MATCH_ALL_ONE; //reset match flag for all bits\n match_flag_or <= #TCQ MATCH_ALL_ONE; //reset match flag for all bits\n no_err_win_detected <= #TCQ 1'b0;\n no_err_win_detected_latch <= #TCQ 1'b0;\n prbs_state_r <= #TCQ FINE_CALC_TAPS_WAIT;\n valid_window_cnt <= #TCQ 2'd0; //reset valid window counter\n end\n end\n\n FINE_CALC_TAPS_WAIT: begin //wait for ROM read out\n if(stage_cnt == 'd2) begin //last stage : back to center\n if(center_comp) begin\n fine_pi_dec_cnt <= #TCQ (dec_cnt[5]&dec_cnt[0])? 'd32: prbs_dqs_tap_cnt_r - smallest_right_edge + dec_cnt - 1 + pi_adj ; //going to the center value & shift by 1\n fine_dly_error <= #TCQ (dec_cnt[5]&dec_cnt[0]) ? 1'b1: fine_dly_error;\n end else begin\n fine_pi_dec_cnt <= #TCQ prbs_dqs_tap_cnt_r - center_calc[6:1] - center_calc[0] + pi_adj; //going to the center value & shift left by 1\n fine_dly_error <= #TCQ 1'b0;\n end\n end else begin\n fine_pi_dec_cnt <= #TCQ prbs_dqs_tap_cnt_r; \n end\n if (bit_cnt == DRAM_WIDTH) begin\n fine_delay_sel <= #TCQ 'b1;\n stage_cnt <= #TCQ stage_cnt + 1;\n prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_DEC;\n end\n\n end\n \n //wait for finishing the read before PI movement\n RD_DONE_WAIT_FOR_PI_INC_DEC: begin\n if (complex_act_start & ~complex_rdlvl_err) \n prbs_state_r <= #TCQ fine_calib? FINE_PI_DEC: PRBS_DEC_DQS;\n end\n\n // Done with this stage of calibration\n PRBS_DONE: begin\n prbs_prech_req_r <= #TCQ 1'b0;\n prbs_last_byte_done <= #TCQ 1'b0;\n prbs_rdlvl_done <= #TCQ ~complex_rdlvl_err;\n reset_rd_addr <= #TCQ 1'b0;\n end\n\n endcase\n end\n\n //ROM generation for dec counter\n always @ (largest_left_edge or smallest_right_edge) begin\n case ({largest_left_edge, smallest_right_edge})\n 12'd0 : mem_out_dec = 6'b111111;\n 12'd1 : mem_out_dec = 6'b111111;\n 12'd2 : mem_out_dec = 6'b111111;\n 12'd3 : mem_out_dec = 6'b111111;\n 12'd4 : mem_out_dec = 6'b111111;\n 12'd5 : mem_out_dec = 6'b111111;\n 12'd6 : mem_out_dec = 6'b000100;\n 12'd7 : mem_out_dec = 6'b000101;\n 12'd8 : mem_out_dec = 6'b000101;\n 12'd9 : mem_out_dec = 6'b000110;\n 12'd10 : mem_out_dec = 6'b000110;\n 12'd11 : mem_out_dec = 6'b000111;\n 12'd12 : mem_out_dec = 6'b001000;\n 12'd13 : mem_out_dec = 6'b001000;\n 12'd14 : mem_out_dec = 6'b001001;\n 12'd15 : mem_out_dec = 6'b001010;\n 12'd16 : mem_out_dec = 6'b001010;\n 12'd17 : mem_out_dec = 6'b001011;\n 12'd18 : mem_out_dec = 6'b001011;\n 12'd19 : mem_out_dec = 6'b001100;\n 12'd20 : mem_out_dec = 6'b001100;\n 12'd21 : mem_out_dec = 6'b001100;\n 12'd22 : mem_out_dec = 6'b001100;\n 12'd23 : mem_out_dec = 6'b001101;\n 12'd24 : mem_out_dec = 6'b001100;\n 12'd25 : mem_out_dec = 6'b001100;\n 12'd26 : mem_out_dec = 6'b001101;\n 12'd27 : mem_out_dec = 6'b001110;\n 12'd28 : mem_out_dec = 6'b001110;\n 12'd29 : mem_out_dec = 6'b001111;\n 12'd30 : mem_out_dec = 6'b010000;\n 12'd31 : mem_out_dec = 6'b010001;\n 12'd32 : mem_out_dec = 6'b010001;\n 12'd33 : mem_out_dec = 6'b010010;\n 12'd34 : mem_out_dec = 6'b010010;\n 12'd35 : mem_out_dec = 6'b010010;\n 12'd36 : mem_out_dec = 6'b010011;\n 12'd37 : mem_out_dec = 6'b010100;\n 12'd38 : mem_out_dec = 6'b010100;\n 12'd39 : mem_out_dec = 6'b010101;\n 12'd40 : mem_out_dec = 6'b010101;\n 12'd41 : mem_out_dec = 6'b010110;\n 12'd42 : mem_out_dec = 6'b010110;\n 12'd43 : mem_out_dec = 6'b010111;\n 12'd44 : mem_out_dec = 6'b011000;\n 12'd45 : mem_out_dec = 6'b011001;\n 12'd46 : mem_out_dec = 6'b011001;\n 12'd47 : mem_out_dec = 6'b011010;\n 12'd48 : mem_out_dec = 6'b011010;\n 12'd49 : mem_out_dec = 6'b011011;\n 12'd50 : mem_out_dec = 6'b011011;\n 12'd51 : mem_out_dec = 6'b011100;\n 12'd52 : mem_out_dec = 6'b011100;\n 12'd53 : mem_out_dec = 6'b011100;\n 12'd54 : mem_out_dec = 6'b011100;\n 12'd55 : mem_out_dec = 6'b011100;\n 12'd56 : mem_out_dec = 6'b011100;\n 12'd57 : mem_out_dec = 6'b011100;\n 12'd58 : mem_out_dec = 6'b011100;\n 12'd59 : mem_out_dec = 6'b011101;\n 12'd60 : mem_out_dec = 6'b011110;\n 12'd61 : mem_out_dec = 6'b011111;\n 12'd62 : mem_out_dec = 6'b100000;\n 12'd63 : mem_out_dec = 6'b100000;\n 12'd64 : mem_out_dec = 6'b111111;\n 12'd65 : mem_out_dec = 6'b111111;\n 12'd66 : mem_out_dec = 6'b111111;\n 12'd67 : mem_out_dec = 6'b111111;\n 12'd68 : mem_out_dec = 6'b111111;\n 12'd69 : mem_out_dec = 6'b111111;\n 12'd70 : mem_out_dec = 6'b111111;\n 12'd71 : mem_out_dec = 6'b000100;\n 12'd72 : mem_out_dec = 6'b000100;\n 12'd73 : mem_out_dec = 6'b000101;\n 12'd74 : mem_out_dec = 6'b000110;\n 12'd75 : mem_out_dec = 6'b000111;\n 12'd76 : mem_out_dec = 6'b000111;\n 12'd77 : mem_out_dec = 6'b001000;\n 12'd78 : mem_out_dec = 6'b001001;\n 12'd79 : mem_out_dec = 6'b001001;\n 12'd80 : mem_out_dec = 6'b001010;\n 12'd81 : mem_out_dec = 6'b001010;\n 12'd82 : mem_out_dec = 6'b001011;\n 12'd83 : mem_out_dec = 6'b001011;\n 12'd84 : mem_out_dec = 6'b001011;\n 12'd85 : mem_out_dec = 6'b001011;\n 12'd86 : mem_out_dec = 6'b001011;\n 12'd87 : mem_out_dec = 6'b001100;\n 12'd88 : mem_out_dec = 6'b001011;\n 12'd89 : mem_out_dec = 6'b001100;\n 12'd90 : mem_out_dec = 6'b001100;\n 12'd91 : mem_out_dec = 6'b001101;\n 12'd92 : mem_out_dec = 6'b001110;\n 12'd93 : mem_out_dec = 6'b001111;\n 12'd94 : mem_out_dec = 6'b001111;\n 12'd95 : mem_out_dec = 6'b010000;\n 12'd96 : mem_out_dec = 6'b010001;\n 12'd97 : mem_out_dec = 6'b010001;\n 12'd98 : mem_out_dec = 6'b010010;\n 12'd99 : mem_out_dec = 6'b010010;\n 12'd100 : mem_out_dec = 6'b010011;\n 12'd101 : mem_out_dec = 6'b010011;\n 12'd102 : mem_out_dec = 6'b010100;\n 12'd103 : mem_out_dec = 6'b010100;\n 12'd104 : mem_out_dec = 6'b010100;\n 12'd105 : mem_out_dec = 6'b010101;\n 12'd106 : mem_out_dec = 6'b010110;\n 12'd107 : mem_out_dec = 6'b010111;\n 12'd108 : mem_out_dec = 6'b010111;\n 12'd109 : mem_out_dec = 6'b011000;\n 12'd110 : mem_out_dec = 6'b011001;\n 12'd111 : mem_out_dec = 6'b011001;\n 12'd112 : mem_out_dec = 6'b011010;\n 12'd113 : mem_out_dec = 6'b011010;\n 12'd114 : mem_out_dec = 6'b011011;\n 12'd115 : mem_out_dec = 6'b011011;\n 12'd116 : mem_out_dec = 6'b011011;\n 12'd117 : mem_out_dec = 6'b011011;\n 12'd118 : mem_out_dec = 6'b011011;\n 12'd119 : mem_out_dec = 6'b011011;\n 12'd120 : mem_out_dec = 6'b011011;\n 12'd121 : mem_out_dec = 6'b011011;\n 12'd122 : mem_out_dec = 6'b011100;\n 12'd123 : mem_out_dec = 6'b011101;\n 12'd124 : mem_out_dec = 6'b011110;\n 12'd125 : mem_out_dec = 6'b011110;\n 12'd126 : mem_out_dec = 6'b011111;\n 12'd127 : mem_out_dec = 6'b100000;\n 12'd128 : mem_out_dec = 6'b111111;\n 12'd129 : mem_out_dec = 6'b111111;\n 12'd130 : mem_out_dec = 6'b111111;\n 12'd131 : mem_out_dec = 6'b111111;\n 12'd132 : mem_out_dec = 6'b111111;\n 12'd133 : mem_out_dec = 6'b111111;\n 12'd134 : mem_out_dec = 6'b111111;\n 12'd135 : mem_out_dec = 6'b111111;\n 12'd136 : mem_out_dec = 6'b000100;\n 12'd137 : mem_out_dec = 6'b000101;\n 12'd138 : mem_out_dec = 6'b000101;\n 12'd139 : mem_out_dec = 6'b000110;\n 12'd140 : mem_out_dec = 6'b000110;\n 12'd141 : mem_out_dec = 6'b000111;\n 12'd142 : mem_out_dec = 6'b001000;\n 12'd143 : mem_out_dec = 6'b001001;\n 12'd144 : mem_out_dec = 6'b001001;\n 12'd145 : mem_out_dec = 6'b001010;\n 12'd146 : mem_out_dec = 6'b001010;\n 12'd147 : mem_out_dec = 6'b001010;\n 12'd148 : mem_out_dec = 6'b001010;\n 12'd149 : mem_out_dec = 6'b001010;\n 12'd150 : mem_out_dec = 6'b001010;\n 12'd151 : mem_out_dec = 6'b001011;\n 12'd152 : mem_out_dec = 6'b001010;\n 12'd153 : mem_out_dec = 6'b001011;\n 12'd154 : mem_out_dec = 6'b001100;\n 12'd155 : mem_out_dec = 6'b001101;\n 12'd156 : mem_out_dec = 6'b001101;\n 12'd157 : mem_out_dec = 6'b001110;\n 12'd158 : mem_out_dec = 6'b001111;\n 12'd159 : mem_out_dec = 6'b010000;\n 12'd160 : mem_out_dec = 6'b010000;\n 12'd161 : mem_out_dec = 6'b010001;\n 12'd162 : mem_out_dec = 6'b010001;\n 12'd163 : mem_out_dec = 6'b010010;\n 12'd164 : mem_out_dec = 6'b010010;\n 12'd165 : mem_out_dec = 6'b010011;\n 12'd166 : mem_out_dec = 6'b010011;\n 12'd167 : mem_out_dec = 6'b010100;\n 12'd168 : mem_out_dec = 6'b010100;\n 12'd169 : mem_out_dec = 6'b010101;\n 12'd170 : mem_out_dec = 6'b010101;\n 12'd171 : mem_out_dec = 6'b010110;\n 12'd172 : mem_out_dec = 6'b010111;\n 12'd173 : mem_out_dec = 6'b010111;\n 12'd174 : mem_out_dec = 6'b011000;\n 12'd175 : mem_out_dec = 6'b011001;\n 12'd176 : mem_out_dec = 6'b011001;\n 12'd177 : mem_out_dec = 6'b011010;\n 12'd178 : mem_out_dec = 6'b011010;\n 12'd179 : mem_out_dec = 6'b011010;\n 12'd180 : mem_out_dec = 6'b011010;\n 12'd181 : mem_out_dec = 6'b011010;\n 12'd182 : mem_out_dec = 6'b011010;\n 12'd183 : mem_out_dec = 6'b011010;\n 12'd184 : mem_out_dec = 6'b011010;\n 12'd185 : mem_out_dec = 6'b011011;\n 12'd186 : mem_out_dec = 6'b011100;\n 12'd187 : mem_out_dec = 6'b011100;\n 12'd188 : mem_out_dec = 6'b011101;\n 12'd189 : mem_out_dec = 6'b011110;\n 12'd190 : mem_out_dec = 6'b011111;\n 12'd191 : mem_out_dec = 6'b100000;\n 12'd192 : mem_out_dec = 6'b111111;\n 12'd193 : mem_out_dec = 6'b111111;\n 12'd194 : mem_out_dec = 6'b111111;\n 12'd195 : mem_out_dec = 6'b111111;\n 12'd196 : mem_out_dec = 6'b111111;\n 12'd197 : mem_out_dec = 6'b111111;\n 12'd198 : mem_out_dec = 6'b111111;\n 12'd199 : mem_out_dec = 6'b111111;\n 12'd200 : mem_out_dec = 6'b111111;\n 12'd201 : mem_out_dec = 6'b000100;\n 12'd202 : mem_out_dec = 6'b000100;\n 12'd203 : mem_out_dec = 6'b000101;\n 12'd204 : mem_out_dec = 6'b000110;\n 12'd205 : mem_out_dec = 6'b000111;\n 12'd206 : mem_out_dec = 6'b001000;\n 12'd207 : mem_out_dec = 6'b001000;\n 12'd208 : mem_out_dec = 6'b001001;\n 12'd209 : mem_out_dec = 6'b001001;\n 12'd210 : mem_out_dec = 6'b001001;\n 12'd211 : mem_out_dec = 6'b001001;\n 12'd212 : mem_out_dec = 6'b001001;\n 12'd213 : mem_out_dec = 6'b001001;\n 12'd214 : mem_out_dec = 6'b001001;\n 12'd215 : mem_out_dec = 6'b001010;\n 12'd216 : mem_out_dec = 6'b001010;\n 12'd217 : mem_out_dec = 6'b001011;\n 12'd218 : mem_out_dec = 6'b001011;\n 12'd219 : mem_out_dec = 6'b001100;\n 12'd220 : mem_out_dec = 6'b001101;\n 12'd221 : mem_out_dec = 6'b001110;\n 12'd222 : mem_out_dec = 6'b001111;\n 12'd223 : mem_out_dec = 6'b001111;\n 12'd224 : mem_out_dec = 6'b010000;\n 12'd225 : mem_out_dec = 6'b010000;\n 12'd226 : mem_out_dec = 6'b010001;\n 12'd227 : mem_out_dec = 6'b010001;\n 12'd228 : mem_out_dec = 6'b010010;\n 12'd229 : mem_out_dec = 6'b010010;\n 12'd230 : mem_out_dec = 6'b010011;\n 12'd231 : mem_out_dec = 6'b010011;\n 12'd232 : mem_out_dec = 6'b010011;\n 12'd233 : mem_out_dec = 6'b010100;\n 12'd234 : mem_out_dec = 6'b010100;\n 12'd235 : mem_out_dec = 6'b010101;\n 12'd236 : mem_out_dec = 6'b010110;\n 12'd237 : mem_out_dec = 6'b010111;\n 12'd238 : mem_out_dec = 6'b011000;\n 12'd239 : mem_out_dec = 6'b011000;\n 12'd240 : mem_out_dec = 6'b011001;\n 12'd241 : mem_out_dec = 6'b011001;\n 12'd242 : mem_out_dec = 6'b011001;\n 12'd243 : mem_out_dec = 6'b011001;\n 12'd244 : mem_out_dec = 6'b011001;\n 12'd245 : mem_out_dec = 6'b011001;\n 12'd246 : mem_out_dec = 6'b011001;\n 12'd247 : mem_out_dec = 6'b011001;\n 12'd248 : mem_out_dec = 6'b011010;\n 12'd249 : mem_out_dec = 6'b011010;\n 12'd250 : mem_out_dec = 6'b011011;\n 12'd251 : mem_out_dec = 6'b011100;\n 12'd252 : mem_out_dec = 6'b011101;\n 12'd253 : mem_out_dec = 6'b011110;\n 12'd254 : mem_out_dec = 6'b011110;\n 12'd255 : mem_out_dec = 6'b011111;\n 12'd256 : mem_out_dec = 6'b111111;\n 12'd257 : mem_out_dec = 6'b111111;\n 12'd258 : mem_out_dec = 6'b111111;\n 12'd259 : mem_out_dec = 6'b111111;\n 12'd260 : mem_out_dec = 6'b111111;\n 12'd261 : mem_out_dec = 6'b111111;\n 12'd262 : mem_out_dec = 6'b111111;\n 12'd263 : mem_out_dec = 6'b111111;\n 12'd264 : mem_out_dec = 6'b111111;\n 12'd265 : mem_out_dec = 6'b111111;\n 12'd266 : mem_out_dec = 6'b000100;\n 12'd267 : mem_out_dec = 6'b000101;\n 12'd268 : mem_out_dec = 6'b000110;\n 12'd269 : mem_out_dec = 6'b000110;\n 12'd270 : mem_out_dec = 6'b000111;\n 12'd271 : mem_out_dec = 6'b001000;\n 12'd272 : mem_out_dec = 6'b001000;\n 12'd273 : mem_out_dec = 6'b001000;\n 12'd274 : mem_out_dec = 6'b001000;\n 12'd275 : mem_out_dec = 6'b001000;\n 12'd276 : mem_out_dec = 6'b001000;\n 12'd277 : mem_out_dec = 6'b001000;\n 12'd278 : mem_out_dec = 6'b001000;\n 12'd279 : mem_out_dec = 6'b001001;\n 12'd280 : mem_out_dec = 6'b001001;\n 12'd281 : mem_out_dec = 6'b001010;\n 12'd282 : mem_out_dec = 6'b001011;\n 12'd283 : mem_out_dec = 6'b001100;\n 12'd284 : mem_out_dec = 6'b001101;\n 12'd285 : mem_out_dec = 6'b001101;\n 12'd286 : mem_out_dec = 6'b001110;\n 12'd287 : mem_out_dec = 6'b001111;\n 12'd288 : mem_out_dec = 6'b001111;\n 12'd289 : mem_out_dec = 6'b010000;\n 12'd290 : mem_out_dec = 6'b010000;\n 12'd291 : mem_out_dec = 6'b010001;\n 12'd292 : mem_out_dec = 6'b010001;\n 12'd293 : mem_out_dec = 6'b010010;\n 12'd294 : mem_out_dec = 6'b010010;\n 12'd295 : mem_out_dec = 6'b010011;\n 12'd296 : mem_out_dec = 6'b010010;\n 12'd297 : mem_out_dec = 6'b010011;\n 12'd298 : mem_out_dec = 6'b010100;\n 12'd299 : mem_out_dec = 6'b010101;\n 12'd300 : mem_out_dec = 6'b010110;\n 12'd301 : mem_out_dec = 6'b010110;\n 12'd302 : mem_out_dec = 6'b010111;\n 12'd303 : mem_out_dec = 6'b011000;\n 12'd304 : mem_out_dec = 6'b011000;\n 12'd305 : mem_out_dec = 6'b011000;\n 12'd306 : mem_out_dec = 6'b011000;\n 12'd307 : mem_out_dec = 6'b011000;\n 12'd308 : mem_out_dec = 6'b011000;\n 12'd309 : mem_out_dec = 6'b011000;\n 12'd310 : mem_out_dec = 6'b011000;\n 12'd311 : mem_out_dec = 6'b011001;\n 12'd312 : mem_out_dec = 6'b011001;\n 12'd313 : mem_out_dec = 6'b011010;\n 12'd314 : mem_out_dec = 6'b011011;\n 12'd315 : mem_out_dec = 6'b011100;\n 12'd316 : mem_out_dec = 6'b011100;\n 12'd317 : mem_out_dec = 6'b011101;\n 12'd318 : mem_out_dec = 6'b011110;\n 12'd319 : mem_out_dec = 6'b011111;\n 12'd320 : mem_out_dec = 6'b111111;\n 12'd321 : mem_out_dec = 6'b111111;\n 12'd322 : mem_out_dec = 6'b111111;\n 12'd323 : mem_out_dec = 6'b111111;\n 12'd324 : mem_out_dec = 6'b111111;\n 12'd325 : mem_out_dec = 6'b111111;\n 12'd326 : mem_out_dec = 6'b111111;\n 12'd327 : mem_out_dec = 6'b111111;\n 12'd328 : mem_out_dec = 6'b111111;\n 12'd329 : mem_out_dec = 6'b111111;\n 12'd330 : mem_out_dec = 6'b111111;\n 12'd331 : mem_out_dec = 6'b000100;\n 12'd332 : mem_out_dec = 6'b000101;\n 12'd333 : mem_out_dec = 6'b000110;\n 12'd334 : mem_out_dec = 6'b000111;\n 12'd335 : mem_out_dec = 6'b001000;\n 12'd336 : mem_out_dec = 6'b000111;\n 12'd337 : mem_out_dec = 6'b000111;\n 12'd338 : mem_out_dec = 6'b000111;\n 12'd339 : mem_out_dec = 6'b000111;\n 12'd340 : mem_out_dec = 6'b000111;\n 12'd341 : mem_out_dec = 6'b000111;\n 12'd342 : mem_out_dec = 6'b001000;\n 12'd343 : mem_out_dec = 6'b001001;\n 12'd344 : mem_out_dec = 6'b001001;\n 12'd345 : mem_out_dec = 6'b001010;\n 12'd346 : mem_out_dec = 6'b001011;\n 12'd347 : mem_out_dec = 6'b001011;\n 12'd348 : mem_out_dec = 6'b001100;\n 12'd349 : mem_out_dec = 6'b001101;\n 12'd350 : mem_out_dec = 6'b001110;\n 12'd351 : mem_out_dec = 6'b001110;\n 12'd352 : mem_out_dec = 6'b001111;\n 12'd353 : mem_out_dec = 6'b001111;\n 12'd354 : mem_out_dec = 6'b010000;\n 12'd355 : mem_out_dec = 6'b010000;\n 12'd356 : mem_out_dec = 6'b010001;\n 12'd357 : mem_out_dec = 6'b010001;\n 12'd358 : mem_out_dec = 6'b010001;\n 12'd359 : mem_out_dec = 6'b010010;\n 12'd360 : mem_out_dec = 6'b010010;\n 12'd361 : mem_out_dec = 6'b010011;\n 12'd362 : mem_out_dec = 6'b010100;\n 12'd363 : mem_out_dec = 6'b010100;\n 12'd364 : mem_out_dec = 6'b010101;\n 12'd365 : mem_out_dec = 6'b010110;\n 12'd366 : mem_out_dec = 6'b010111;\n 12'd367 : mem_out_dec = 6'b011000;\n 12'd368 : mem_out_dec = 6'b010111;\n 12'd369 : mem_out_dec = 6'b010111;\n 12'd370 : mem_out_dec = 6'b010111;\n 12'd371 : mem_out_dec = 6'b010111;\n 12'd372 : mem_out_dec = 6'b010111;\n 12'd373 : mem_out_dec = 6'b010111;\n 12'd374 : mem_out_dec = 6'b011000;\n 12'd375 : mem_out_dec = 6'b011001;\n 12'd376 : mem_out_dec = 6'b011001;\n 12'd377 : mem_out_dec = 6'b011010;\n 12'd378 : mem_out_dec = 6'b011010;\n 12'd379 : mem_out_dec = 6'b011011;\n 12'd380 : mem_out_dec = 6'b011100;\n 12'd381 : mem_out_dec = 6'b011101;\n 12'd382 : mem_out_dec = 6'b011101;\n 12'd383 : mem_out_dec = 6'b011110;\n 12'd384 : mem_out_dec = 6'b111111;\n 12'd385 : mem_out_dec = 6'b111111;\n 12'd386 : mem_out_dec = 6'b111111;\n 12'd387 : mem_out_dec = 6'b111111;\n 12'd388 : mem_out_dec = 6'b111111;\n 12'd389 : mem_out_dec = 6'b111111;\n 12'd390 : mem_out_dec = 6'b111111;\n 12'd391 : mem_out_dec = 6'b111111;\n 12'd392 : mem_out_dec = 6'b111111;\n 12'd393 : mem_out_dec = 6'b111111;\n 12'd394 : mem_out_dec = 6'b111111;\n 12'd395 : mem_out_dec = 6'b111111;\n 12'd396 : mem_out_dec = 6'b000101;\n 12'd397 : mem_out_dec = 6'b000110;\n 12'd398 : mem_out_dec = 6'b000110;\n 12'd399 : mem_out_dec = 6'b000111;\n 12'd400 : mem_out_dec = 6'b000110;\n 12'd401 : mem_out_dec = 6'b000110;\n 12'd402 : mem_out_dec = 6'b000110;\n 12'd403 : mem_out_dec = 6'b000110;\n 12'd404 : mem_out_dec = 6'b000110;\n 12'd405 : mem_out_dec = 6'b000111;\n 12'd406 : mem_out_dec = 6'b001000;\n 12'd407 : mem_out_dec = 6'b001000;\n 12'd408 : mem_out_dec = 6'b001001;\n 12'd409 : mem_out_dec = 6'b001001;\n 12'd410 : mem_out_dec = 6'b001010;\n 12'd411 : mem_out_dec = 6'b001011;\n 12'd412 : mem_out_dec = 6'b001100;\n 12'd413 : mem_out_dec = 6'b001100;\n 12'd414 : mem_out_dec = 6'b001101;\n 12'd415 : mem_out_dec = 6'b001110;\n 12'd416 : mem_out_dec = 6'b001110;\n 12'd417 : mem_out_dec = 6'b001111;\n 12'd418 : mem_out_dec = 6'b001111;\n 12'd419 : mem_out_dec = 6'b010000;\n 12'd420 : mem_out_dec = 6'b010000;\n 12'd421 : mem_out_dec = 6'b010000;\n 12'd422 : mem_out_dec = 6'b010001;\n 12'd423 : mem_out_dec = 6'b010001;\n 12'd424 : mem_out_dec = 6'b010010;\n 12'd425 : mem_out_dec = 6'b010011;\n 12'd426 : mem_out_dec = 6'b010011;\n 12'd427 : mem_out_dec = 6'b010100;\n 12'd428 : mem_out_dec = 6'b010101;\n 12'd429 : mem_out_dec = 6'b010110;\n 12'd430 : mem_out_dec = 6'b010111;\n 12'd431 : mem_out_dec = 6'b010111;\n 12'd432 : mem_out_dec = 6'b010110;\n 12'd433 : mem_out_dec = 6'b010110;\n 12'd434 : mem_out_dec = 6'b010110;\n 12'd435 : mem_out_dec = 6'b010110;\n 12'd436 : mem_out_dec = 6'b010110;\n 12'd437 : mem_out_dec = 6'b010111;\n 12'd438 : mem_out_dec = 6'b010111;\n 12'd439 : mem_out_dec = 6'b011000;\n 12'd440 : mem_out_dec = 6'b011001;\n 12'd441 : mem_out_dec = 6'b011001;\n 12'd442 : mem_out_dec = 6'b011010;\n 12'd443 : mem_out_dec = 6'b011011;\n 12'd444 : mem_out_dec = 6'b011011;\n 12'd445 : mem_out_dec = 6'b011100;\n 12'd446 : mem_out_dec = 6'b011101;\n 12'd447 : mem_out_dec = 6'b011110;\n 12'd448 : mem_out_dec = 6'b111111;\n 12'd449 : mem_out_dec = 6'b111111;\n 12'd450 : mem_out_dec = 6'b111111;\n 12'd451 : mem_out_dec = 6'b111111;\n 12'd452 : mem_out_dec = 6'b111111;\n 12'd453 : mem_out_dec = 6'b111111;\n 12'd454 : mem_out_dec = 6'b111111;\n 12'd455 : mem_out_dec = 6'b111111;\n 12'd456 : mem_out_dec = 6'b111111;\n 12'd457 : mem_out_dec = 6'b111111;\n 12'd458 : mem_out_dec = 6'b111111;\n 12'd459 : mem_out_dec = 6'b111111;\n 12'd460 : mem_out_dec = 6'b111111;\n 12'd461 : mem_out_dec = 6'b000101;\n 12'd462 : mem_out_dec = 6'b000110;\n 12'd463 : mem_out_dec = 6'b000110;\n 12'd464 : mem_out_dec = 6'b000110;\n 12'd465 : mem_out_dec = 6'b000110;\n 12'd466 : mem_out_dec = 6'b000110;\n 12'd467 : mem_out_dec = 6'b000110;\n 12'd468 : mem_out_dec = 6'b000110;\n 12'd469 : mem_out_dec = 6'b000111;\n 12'd470 : mem_out_dec = 6'b000111;\n 12'd471 : mem_out_dec = 6'b001000;\n 12'd472 : mem_out_dec = 6'b001000;\n 12'd473 : mem_out_dec = 6'b001001;\n 12'd474 : mem_out_dec = 6'b001010;\n 12'd475 : mem_out_dec = 6'b001011;\n 12'd476 : mem_out_dec = 6'b001011;\n 12'd477 : mem_out_dec = 6'b001100;\n 12'd478 : mem_out_dec = 6'b001101;\n 12'd479 : mem_out_dec = 6'b001110;\n 12'd480 : mem_out_dec = 6'b001110;\n 12'd481 : mem_out_dec = 6'b001110;\n 12'd482 : mem_out_dec = 6'b001111;\n 12'd483 : mem_out_dec = 6'b001111;\n 12'd484 : mem_out_dec = 6'b010000;\n 12'd485 : mem_out_dec = 6'b010000;\n 12'd486 : mem_out_dec = 6'b010000;\n 12'd487 : mem_out_dec = 6'b010001;\n 12'd488 : mem_out_dec = 6'b010001;\n 12'd489 : mem_out_dec = 6'b010010;\n 12'd490 : mem_out_dec = 6'b010011;\n 12'd491 : mem_out_dec = 6'b010100;\n 12'd492 : mem_out_dec = 6'b010101;\n 12'd493 : mem_out_dec = 6'b010101;\n 12'd494 : mem_out_dec = 6'b010110;\n 12'd495 : mem_out_dec = 6'b010110;\n 12'd496 : mem_out_dec = 6'b010110;\n 12'd497 : mem_out_dec = 6'b010110;\n 12'd498 : mem_out_dec = 6'b010101;\n 12'd499 : mem_out_dec = 6'b010101;\n 12'd500 : mem_out_dec = 6'b010110;\n 12'd501 : mem_out_dec = 6'b010111;\n 12'd502 : mem_out_dec = 6'b010111;\n 12'd503 : mem_out_dec = 6'b011000;\n 12'd504 : mem_out_dec = 6'b011000;\n 12'd505 : mem_out_dec = 6'b011001;\n 12'd506 : mem_out_dec = 6'b011010;\n 12'd507 : mem_out_dec = 6'b011010;\n 12'd508 : mem_out_dec = 6'b011011;\n 12'd509 : mem_out_dec = 6'b011100;\n 12'd510 : mem_out_dec = 6'b011101;\n 12'd511 : mem_out_dec = 6'b011101;\n 12'd512 : mem_out_dec = 6'b111111;\n 12'd513 : mem_out_dec = 6'b111111;\n 12'd514 : mem_out_dec = 6'b111111;\n 12'd515 : mem_out_dec = 6'b111111;\n 12'd516 : mem_out_dec = 6'b111111;\n 12'd517 : mem_out_dec = 6'b111111;\n 12'd518 : mem_out_dec = 6'b111111;\n 12'd519 : mem_out_dec = 6'b111111;\n 12'd520 : mem_out_dec = 6'b111111;\n 12'd521 : mem_out_dec = 6'b111111;\n 12'd522 : mem_out_dec = 6'b111111;\n 12'd523 : mem_out_dec = 6'b111111;\n 12'd524 : mem_out_dec = 6'b111111;\n 12'd525 : mem_out_dec = 6'b111111;\n 12'd526 : mem_out_dec = 6'b000100;\n 12'd527 : mem_out_dec = 6'b000101;\n 12'd528 : mem_out_dec = 6'b000100;\n 12'd529 : mem_out_dec = 6'b000100;\n 12'd530 : mem_out_dec = 6'b000100;\n 12'd531 : mem_out_dec = 6'b000101;\n 12'd532 : mem_out_dec = 6'b000101;\n 12'd533 : mem_out_dec = 6'b000110;\n 12'd534 : mem_out_dec = 6'b000111;\n 12'd535 : mem_out_dec = 6'b000111;\n 12'd536 : mem_out_dec = 6'b000111;\n 12'd537 : mem_out_dec = 6'b001000;\n 12'd538 : mem_out_dec = 6'b001001;\n 12'd539 : mem_out_dec = 6'b001010;\n 12'd540 : mem_out_dec = 6'b001011;\n 12'd541 : mem_out_dec = 6'b001011;\n 12'd542 : mem_out_dec = 6'b001100;\n 12'd543 : mem_out_dec = 6'b001101;\n 12'd544 : mem_out_dec = 6'b001101;\n 12'd545 : mem_out_dec = 6'b001101;\n 12'd546 : mem_out_dec = 6'b001110;\n 12'd547 : mem_out_dec = 6'b001110;\n 12'd548 : mem_out_dec = 6'b001110;\n 12'd549 : mem_out_dec = 6'b001111;\n 12'd550 : mem_out_dec = 6'b010000;\n 12'd551 : mem_out_dec = 6'b010000;\n 12'd552 : mem_out_dec = 6'b010001;\n 12'd553 : mem_out_dec = 6'b010001;\n 12'd554 : mem_out_dec = 6'b010010;\n 12'd555 : mem_out_dec = 6'b010010;\n 12'd556 : mem_out_dec = 6'b010011;\n 12'd557 : mem_out_dec = 6'b010100;\n 12'd558 : mem_out_dec = 6'b010100;\n 12'd559 : mem_out_dec = 6'b010100;\n 12'd560 : mem_out_dec = 6'b010100;\n 12'd561 : mem_out_dec = 6'b010100;\n 12'd562 : mem_out_dec = 6'b010100;\n 12'd563 : mem_out_dec = 6'b010101;\n 12'd564 : mem_out_dec = 6'b010101;\n 12'd565 : mem_out_dec = 6'b010110;\n 12'd566 : mem_out_dec = 6'b010111;\n 12'd567 : mem_out_dec = 6'b010111;\n 12'd568 : mem_out_dec = 6'b010111;\n 12'd569 : mem_out_dec = 6'b011000;\n 12'd570 : mem_out_dec = 6'b011001;\n 12'd571 : mem_out_dec = 6'b011010;\n 12'd572 : mem_out_dec = 6'b011010;\n 12'd573 : mem_out_dec = 6'b011011;\n 12'd574 : mem_out_dec = 6'b011100;\n 12'd575 : mem_out_dec = 6'b011101;\n 12'd576 : mem_out_dec = 6'b111111;\n 12'd577 : mem_out_dec = 6'b111111;\n 12'd578 : mem_out_dec = 6'b111111;\n 12'd579 : mem_out_dec = 6'b111111;\n 12'd580 : mem_out_dec = 6'b111111;\n 12'd581 : mem_out_dec = 6'b111111;\n 12'd582 : mem_out_dec = 6'b111111;\n 12'd583 : mem_out_dec = 6'b111111;\n 12'd584 : mem_out_dec = 6'b111111;\n 12'd585 : mem_out_dec = 6'b111111;\n 12'd586 : mem_out_dec = 6'b111111;\n 12'd587 : mem_out_dec = 6'b111111;\n 12'd588 : mem_out_dec = 6'b111111;\n 12'd589 : mem_out_dec = 6'b111111;\n 12'd590 : mem_out_dec = 6'b111111;\n 12'd591 : mem_out_dec = 6'b000100;\n 12'd592 : mem_out_dec = 6'b000011;\n 12'd593 : mem_out_dec = 6'b000011;\n 12'd594 : mem_out_dec = 6'b000100;\n 12'd595 : mem_out_dec = 6'b000101;\n 12'd596 : mem_out_dec = 6'b000101;\n 12'd597 : mem_out_dec = 6'b000110;\n 12'd598 : mem_out_dec = 6'b000110;\n 12'd599 : mem_out_dec = 6'b000111;\n 12'd600 : mem_out_dec = 6'b000111;\n 12'd601 : mem_out_dec = 6'b001000;\n 12'd602 : mem_out_dec = 6'b001001;\n 12'd603 : mem_out_dec = 6'b001010;\n 12'd604 : mem_out_dec = 6'b001010;\n 12'd605 : mem_out_dec = 6'b001011;\n 12'd606 : mem_out_dec = 6'b001100;\n 12'd607 : mem_out_dec = 6'b001101;\n 12'd608 : mem_out_dec = 6'b001101;\n 12'd609 : mem_out_dec = 6'b001101;\n 12'd610 : mem_out_dec = 6'b001110;\n 12'd611 : mem_out_dec = 6'b001110;\n 12'd612 : mem_out_dec = 6'b001110;\n 12'd613 : mem_out_dec = 6'b001111;\n 12'd614 : mem_out_dec = 6'b010000;\n 12'd615 : mem_out_dec = 6'b010000;\n 12'd616 : mem_out_dec = 6'b010000;\n 12'd617 : mem_out_dec = 6'b010001;\n 12'd618 : mem_out_dec = 6'b010001;\n 12'd619 : mem_out_dec = 6'b010010;\n 12'd620 : mem_out_dec = 6'b010010;\n 12'd621 : mem_out_dec = 6'b010011;\n 12'd622 : mem_out_dec = 6'b010011;\n 12'd623 : mem_out_dec = 6'b010100;\n 12'd624 : mem_out_dec = 6'b010011;\n 12'd625 : mem_out_dec = 6'b010011;\n 12'd626 : mem_out_dec = 6'b010100;\n 12'd627 : mem_out_dec = 6'b010100;\n 12'd628 : mem_out_dec = 6'b010101;\n 12'd629 : mem_out_dec = 6'b010110;\n 12'd630 : mem_out_dec = 6'b010110;\n 12'd631 : mem_out_dec = 6'b010111;\n 12'd632 : mem_out_dec = 6'b010111;\n 12'd633 : mem_out_dec = 6'b011000;\n 12'd634 : mem_out_dec = 6'b011001;\n 12'd635 : mem_out_dec = 6'b011001;\n 12'd636 : mem_out_dec = 6'b011010;\n 12'd637 : mem_out_dec = 6'b011011;\n 12'd638 : mem_out_dec = 6'b011100;\n 12'd639 : mem_out_dec = 6'b011100;\n 12'd640 : mem_out_dec = 6'b111111;\n 12'd641 : mem_out_dec = 6'b111111;\n 12'd642 : mem_out_dec = 6'b111111;\n 12'd643 : mem_out_dec = 6'b111111;\n 12'd644 : mem_out_dec = 6'b111111;\n 12'd645 : mem_out_dec = 6'b111111;\n 12'd646 : mem_out_dec = 6'b111111;\n 12'd647 : mem_out_dec = 6'b111111;\n 12'd648 : mem_out_dec = 6'b111111;\n 12'd649 : mem_out_dec = 6'b111111;\n 12'd650 : mem_out_dec = 6'b111111;\n 12'd651 : mem_out_dec = 6'b111111;\n 12'd652 : mem_out_dec = 6'b111111;\n 12'd653 : mem_out_dec = 6'b111111;\n 12'd654 : mem_out_dec = 6'b111111;\n 12'd655 : mem_out_dec = 6'b111111;\n 12'd656 : mem_out_dec = 6'b000011;\n 12'd657 : mem_out_dec = 6'b000011;\n 12'd658 : mem_out_dec = 6'b000100;\n 12'd659 : mem_out_dec = 6'b000100;\n 12'd660 : mem_out_dec = 6'b000101;\n 12'd661 : mem_out_dec = 6'b000110;\n 12'd662 : mem_out_dec = 6'b000110;\n 12'd663 : mem_out_dec = 6'b000111;\n 12'd664 : mem_out_dec = 6'b000111;\n 12'd665 : mem_out_dec = 6'b001000;\n 12'd666 : mem_out_dec = 6'b001001;\n 12'd667 : mem_out_dec = 6'b001001;\n 12'd668 : mem_out_dec = 6'b001010;\n 12'd669 : mem_out_dec = 6'b001011;\n 12'd670 : mem_out_dec = 6'b001100;\n 12'd671 : mem_out_dec = 6'b001100;\n 12'd672 : mem_out_dec = 6'b001100;\n 12'd673 : mem_out_dec = 6'b001101;\n 12'd674 : mem_out_dec = 6'b001101;\n 12'd675 : mem_out_dec = 6'b001101;\n 12'd676 : mem_out_dec = 6'b001110;\n 12'd677 : mem_out_dec = 6'b001111;\n 12'd678 : mem_out_dec = 6'b001111;\n 12'd679 : mem_out_dec = 6'b010000;\n 12'd680 : mem_out_dec = 6'b010000;\n 12'd681 : mem_out_dec = 6'b010000;\n 12'd682 : mem_out_dec = 6'b010001;\n 12'd683 : mem_out_dec = 6'b010001;\n 12'd684 : mem_out_dec = 6'b010010;\n 12'd685 : mem_out_dec = 6'b010010;\n 12'd686 : mem_out_dec = 6'b010011;\n 12'd687 : mem_out_dec = 6'b010011;\n 12'd688 : mem_out_dec = 6'b010011;\n 12'd689 : mem_out_dec = 6'b010011;\n 12'd690 : mem_out_dec = 6'b010100;\n 12'd691 : mem_out_dec = 6'b010100;\n 12'd692 : mem_out_dec = 6'b010101;\n 12'd693 : mem_out_dec = 6'b010101;\n 12'd694 : mem_out_dec = 6'b010110;\n 12'd695 : mem_out_dec = 6'b010111;\n 12'd696 : mem_out_dec = 6'b010111;\n 12'd697 : mem_out_dec = 6'b011000;\n 12'd698 : mem_out_dec = 6'b011000;\n 12'd699 : mem_out_dec = 6'b011001;\n 12'd700 : mem_out_dec = 6'b011010;\n 12'd701 : mem_out_dec = 6'b011011;\n 12'd702 : mem_out_dec = 6'b011011;\n 12'd703 : mem_out_dec = 6'b011100;\n 12'd704 : mem_out_dec = 6'b111111;\n 12'd705 : mem_out_dec = 6'b111111;\n 12'd706 : mem_out_dec = 6'b111111;\n 12'd707 : mem_out_dec = 6'b111111;\n 12'd708 : mem_out_dec = 6'b111111;\n 12'd709 : mem_out_dec = 6'b111111;\n 12'd710 : mem_out_dec = 6'b111111;\n 12'd711 : mem_out_dec = 6'b111111;\n 12'd712 : mem_out_dec = 6'b111111;\n 12'd713 : mem_out_dec = 6'b111111;\n 12'd714 : mem_out_dec = 6'b111111;\n 12'd715 : mem_out_dec = 6'b111111;\n 12'd716 : mem_out_dec = 6'b111111;\n 12'd717 : mem_out_dec = 6'b111111;\n 12'd718 : mem_out_dec = 6'b111111;\n 12'd719 : mem_out_dec = 6'b111111;\n 12'd720 : mem_out_dec = 6'b111111;\n 12'd721 : mem_out_dec = 6'b000011;\n 12'd722 : mem_out_dec = 6'b000100;\n 12'd723 : mem_out_dec = 6'b000100;\n 12'd724 : mem_out_dec = 6'b000101;\n 12'd725 : mem_out_dec = 6'b000101;\n 12'd726 : mem_out_dec = 6'b000110;\n 12'd727 : mem_out_dec = 6'b000111;\n 12'd728 : mem_out_dec = 6'b000111;\n 12'd729 : mem_out_dec = 6'b000111;\n 12'd730 : mem_out_dec = 6'b001000;\n 12'd731 : mem_out_dec = 6'b001001;\n 12'd732 : mem_out_dec = 6'b001010;\n 12'd733 : mem_out_dec = 6'b001011;\n 12'd734 : mem_out_dec = 6'b001011;\n 12'd735 : mem_out_dec = 6'b001100;\n 12'd736 : mem_out_dec = 6'b001100;\n 12'd737 : mem_out_dec = 6'b001101;\n 12'd738 : mem_out_dec = 6'b001101;\n 12'd739 : mem_out_dec = 6'b001101;\n 12'd740 : mem_out_dec = 6'b001110;\n 12'd741 : mem_out_dec = 6'b001110;\n 12'd742 : mem_out_dec = 6'b001111;\n 12'd743 : mem_out_dec = 6'b010000;\n 12'd744 : mem_out_dec = 6'b001111;\n 12'd745 : mem_out_dec = 6'b010000;\n 12'd746 : mem_out_dec = 6'b010000;\n 12'd747 : mem_out_dec = 6'b010001;\n 12'd748 : mem_out_dec = 6'b010001;\n 12'd749 : mem_out_dec = 6'b010010;\n 12'd750 : mem_out_dec = 6'b010010;\n 12'd751 : mem_out_dec = 6'b010011;\n 12'd752 : mem_out_dec = 6'b010010;\n 12'd753 : mem_out_dec = 6'b010011;\n 12'd754 : mem_out_dec = 6'b010011;\n 12'd755 : mem_out_dec = 6'b010100;\n 12'd756 : mem_out_dec = 6'b010101;\n 12'd757 : mem_out_dec = 6'b010101;\n 12'd758 : mem_out_dec = 6'b010110;\n 12'd759 : mem_out_dec = 6'b010110;\n 12'd760 : mem_out_dec = 6'b010111;\n 12'd761 : mem_out_dec = 6'b010111;\n 12'd762 : mem_out_dec = 6'b011000;\n 12'd763 : mem_out_dec = 6'b011001;\n 12'd764 : mem_out_dec = 6'b011010;\n 12'd765 : mem_out_dec = 6'b011010;\n 12'd766 : mem_out_dec = 6'b011011;\n 12'd767 : mem_out_dec = 6'b011100;\n 12'd768 : mem_out_dec = 6'b111111;\n 12'd769 : mem_out_dec = 6'b111111;\n 12'd770 : mem_out_dec = 6'b111111;\n 12'd771 : mem_out_dec = 6'b111111;\n 12'd772 : mem_out_dec = 6'b111111;\n 12'd773 : mem_out_dec = 6'b111111;\n 12'd774 : mem_out_dec = 6'b111111;\n 12'd775 : mem_out_dec = 6'b111111;\n 12'd776 : mem_out_dec = 6'b111111;\n 12'd777 : mem_out_dec = 6'b111111;\n 12'd778 : mem_out_dec = 6'b111111;\n 12'd779 : mem_out_dec = 6'b111111;\n 12'd780 : mem_out_dec = 6'b111111;\n 12'd781 : mem_out_dec = 6'b111111;\n 12'd782 : mem_out_dec = 6'b111111;\n 12'd783 : mem_out_dec = 6'b111111;\n 12'd784 : mem_out_dec = 6'b111111;\n 12'd785 : mem_out_dec = 6'b111111;\n 12'd786 : mem_out_dec = 6'b000011;\n 12'd787 : mem_out_dec = 6'b000100;\n 12'd788 : mem_out_dec = 6'b000101;\n 12'd789 : mem_out_dec = 6'b000101;\n 12'd790 : mem_out_dec = 6'b000110;\n 12'd791 : mem_out_dec = 6'b000110;\n 12'd792 : mem_out_dec = 6'b000110;\n 12'd793 : mem_out_dec = 6'b000111;\n 12'd794 : mem_out_dec = 6'b001000;\n 12'd795 : mem_out_dec = 6'b001001;\n 12'd796 : mem_out_dec = 6'b001010;\n 12'd797 : mem_out_dec = 6'b001010;\n 12'd798 : mem_out_dec = 6'b001011;\n 12'd799 : mem_out_dec = 6'b001100;\n 12'd800 : mem_out_dec = 6'b001100;\n 12'd801 : mem_out_dec = 6'b001100;\n 12'd802 : mem_out_dec = 6'b001101;\n 12'd803 : mem_out_dec = 6'b001101;\n 12'd804 : mem_out_dec = 6'b001110;\n 12'd805 : mem_out_dec = 6'b001110;\n 12'd806 : mem_out_dec = 6'b001111;\n 12'd807 : mem_out_dec = 6'b010000;\n 12'd808 : mem_out_dec = 6'b001111;\n 12'd809 : mem_out_dec = 6'b001111;\n 12'd810 : mem_out_dec = 6'b010000;\n 12'd811 : mem_out_dec = 6'b010000;\n 12'd812 : mem_out_dec = 6'b010001;\n 12'd813 : mem_out_dec = 6'b010001;\n 12'd814 : mem_out_dec = 6'b010010;\n 12'd815 : mem_out_dec = 6'b010010;\n 12'd816 : mem_out_dec = 6'b010010;\n 12'd817 : mem_out_dec = 6'b010011;\n 12'd818 : mem_out_dec = 6'b010011;\n 12'd819 : mem_out_dec = 6'b010100;\n 12'd820 : mem_out_dec = 6'b010100;\n 12'd821 : mem_out_dec = 6'b010101;\n 12'd822 : mem_out_dec = 6'b010110;\n 12'd823 : mem_out_dec = 6'b010110;\n 12'd824 : mem_out_dec = 6'b010110;\n 12'd825 : mem_out_dec = 6'b010111;\n 12'd826 : mem_out_dec = 6'b011000;\n 12'd827 : mem_out_dec = 6'b011001;\n 12'd828 : mem_out_dec = 6'b011001;\n 12'd829 : mem_out_dec = 6'b011010;\n 12'd830 : mem_out_dec = 6'b011011;\n 12'd831 : mem_out_dec = 6'b011100;\n 12'd832 : mem_out_dec = 6'b111111;\n 12'd833 : mem_out_dec = 6'b111111;\n 12'd834 : mem_out_dec = 6'b111111;\n 12'd835 : mem_out_dec = 6'b111111;\n 12'd836 : mem_out_dec = 6'b111111;\n 12'd837 : mem_out_dec = 6'b111111;\n 12'd838 : mem_out_dec = 6'b111111;\n 12'd839 : mem_out_dec = 6'b111111;\n 12'd840 : mem_out_dec = 6'b111111;\n 12'd841 : mem_out_dec = 6'b111111;\n 12'd842 : mem_out_dec = 6'b111111;\n 12'd843 : mem_out_dec = 6'b111111;\n 12'd844 : mem_out_dec = 6'b111111;\n 12'd845 : mem_out_dec = 6'b111111;\n 12'd846 : mem_out_dec = 6'b111111;\n 12'd847 : mem_out_dec = 6'b111111;\n 12'd848 : mem_out_dec = 6'b111111;\n 12'd849 : mem_out_dec = 6'b111111;\n 12'd850 : mem_out_dec = 6'b111111;\n 12'd851 : mem_out_dec = 6'b000100;\n 12'd852 : mem_out_dec = 6'b000100;\n 12'd853 : mem_out_dec = 6'b000101;\n 12'd854 : mem_out_dec = 6'b000101;\n 12'd855 : mem_out_dec = 6'b000110;\n 12'd856 : mem_out_dec = 6'b000110;\n 12'd857 : mem_out_dec = 6'b000111;\n 12'd858 : mem_out_dec = 6'b001000;\n 12'd859 : mem_out_dec = 6'b001001;\n 12'd860 : mem_out_dec = 6'b001001;\n 12'd861 : mem_out_dec = 6'b001010;\n 12'd862 : mem_out_dec = 6'b001011;\n 12'd863 : mem_out_dec = 6'b001100;\n 12'd864 : mem_out_dec = 6'b001100;\n 12'd865 : mem_out_dec = 6'b001100;\n 12'd866 : mem_out_dec = 6'b001100;\n 12'd867 : mem_out_dec = 6'b001101;\n 12'd868 : mem_out_dec = 6'b001101;\n 12'd869 : mem_out_dec = 6'b001110;\n 12'd870 : mem_out_dec = 6'b001111;\n 12'd871 : mem_out_dec = 6'b001111;\n 12'd872 : mem_out_dec = 6'b001110;\n 12'd873 : mem_out_dec = 6'b001111;\n 12'd874 : mem_out_dec = 6'b001111;\n 12'd875 : mem_out_dec = 6'b010000;\n 12'd876 : mem_out_dec = 6'b010000;\n 12'd877 : mem_out_dec = 6'b010001;\n 12'd878 : mem_out_dec = 6'b010001;\n 12'd879 : mem_out_dec = 6'b010010;\n 12'd880 : mem_out_dec = 6'b010010;\n 12'd881 : mem_out_dec = 6'b010010;\n 12'd882 : mem_out_dec = 6'b010011;\n 12'd883 : mem_out_dec = 6'b010100;\n 12'd884 : mem_out_dec = 6'b010100;\n 12'd885 : mem_out_dec = 6'b010101;\n 12'd886 : mem_out_dec = 6'b010101;\n 12'd887 : mem_out_dec = 6'b010110;\n 12'd888 : mem_out_dec = 6'b010110;\n 12'd889 : mem_out_dec = 6'b010111;\n 12'd890 : mem_out_dec = 6'b011000;\n 12'd891 : mem_out_dec = 6'b011000;\n 12'd892 : mem_out_dec = 6'b011001;\n 12'd893 : mem_out_dec = 6'b011010;\n 12'd894 : mem_out_dec = 6'b011011;\n 12'd895 : mem_out_dec = 6'b011011;\n 12'd896 : mem_out_dec = 6'b111111;\n 12'd897 : mem_out_dec = 6'b111111;\n 12'd898 : mem_out_dec = 6'b111111;\n 12'd899 : mem_out_dec = 6'b111111;\n 12'd900 : mem_out_dec = 6'b111111;\n 12'd901 : mem_out_dec = 6'b111111;\n 12'd902 : mem_out_dec = 6'b111111;\n 12'd903 : mem_out_dec = 6'b111111;\n 12'd904 : mem_out_dec = 6'b111111;\n 12'd905 : mem_out_dec = 6'b111111;\n 12'd906 : mem_out_dec = 6'b111111;\n 12'd907 : mem_out_dec = 6'b111111;\n 12'd908 : mem_out_dec = 6'b111111;\n 12'd909 : mem_out_dec = 6'b111111;\n 12'd910 : mem_out_dec = 6'b111111;\n 12'd911 : mem_out_dec = 6'b111111;\n 12'd912 : mem_out_dec = 6'b111111;\n 12'd913 : mem_out_dec = 6'b111111;\n 12'd914 : mem_out_dec = 6'b111111;\n 12'd915 : mem_out_dec = 6'b111111;\n 12'd916 : mem_out_dec = 6'b000100;\n 12'd917 : mem_out_dec = 6'b000101;\n 12'd918 : mem_out_dec = 6'b000101;\n 12'd919 : mem_out_dec = 6'b000110;\n 12'd920 : mem_out_dec = 6'b000110;\n 12'd921 : mem_out_dec = 6'b000111;\n 12'd922 : mem_out_dec = 6'b001000;\n 12'd923 : mem_out_dec = 6'b001000;\n 12'd924 : mem_out_dec = 6'b001001;\n 12'd925 : mem_out_dec = 6'b001010;\n 12'd926 : mem_out_dec = 6'b001011;\n 12'd927 : mem_out_dec = 6'b001011;\n 12'd928 : mem_out_dec = 6'b001011;\n 12'd929 : mem_out_dec = 6'b001100;\n 12'd930 : mem_out_dec = 6'b001100;\n 12'd931 : mem_out_dec = 6'b001101;\n 12'd932 : mem_out_dec = 6'b001101;\n 12'd933 : mem_out_dec = 6'b001110;\n 12'd934 : mem_out_dec = 6'b001110;\n 12'd935 : mem_out_dec = 6'b001111;\n 12'd936 : mem_out_dec = 6'b001110;\n 12'd937 : mem_out_dec = 6'b001110;\n 12'd938 : mem_out_dec = 6'b001111;\n 12'd939 : mem_out_dec = 6'b001111;\n 12'd940 : mem_out_dec = 6'b010000;\n 12'd941 : mem_out_dec = 6'b010000;\n 12'd942 : mem_out_dec = 6'b010001;\n 12'd943 : mem_out_dec = 6'b010001;\n 12'd944 : mem_out_dec = 6'b010010;\n 12'd945 : mem_out_dec = 6'b010010;\n 12'd946 : mem_out_dec = 6'b010011;\n 12'd947 : mem_out_dec = 6'b010011;\n 12'd948 : mem_out_dec = 6'b010100;\n 12'd949 : mem_out_dec = 6'b010100;\n 12'd950 : mem_out_dec = 6'b010101;\n 12'd951 : mem_out_dec = 6'b010110;\n 12'd952 : mem_out_dec = 6'b010110;\n 12'd953 : mem_out_dec = 6'b010111;\n 12'd954 : mem_out_dec = 6'b010111;\n 12'd955 : mem_out_dec = 6'b011000;\n 12'd956 : mem_out_dec = 6'b011001;\n 12'd957 : mem_out_dec = 6'b011010;\n 12'd958 : mem_out_dec = 6'b011010;\n 12'd959 : mem_out_dec = 6'b011011;\n 12'd960 : mem_out_dec = 6'b111111;\n 12'd961 : mem_out_dec = 6'b111111;\n 12'd962 : mem_out_dec = 6'b111111;\n 12'd963 : mem_out_dec = 6'b111111;\n 12'd964 : mem_out_dec = 6'b111111;\n 12'd965 : mem_out_dec = 6'b111111;\n 12'd966 : mem_out_dec = 6'b111111;\n 12'd967 : mem_out_dec = 6'b111111;\n 12'd968 : mem_out_dec = 6'b111111;\n 12'd969 : mem_out_dec = 6'b111111;\n 12'd970 : mem_out_dec = 6'b111111;\n 12'd971 : mem_out_dec = 6'b111111;\n 12'd972 : mem_out_dec = 6'b111111;\n 12'd973 : mem_out_dec = 6'b111111;\n 12'd974 : mem_out_dec = 6'b111111;\n 12'd975 : mem_out_dec = 6'b111111;\n 12'd976 : mem_out_dec = 6'b111111;\n 12'd977 : mem_out_dec = 6'b111111;\n 12'd978 : mem_out_dec = 6'b111111;\n 12'd979 : mem_out_dec = 6'b111111;\n 12'd980 : mem_out_dec = 6'b111111;\n 12'd981 : mem_out_dec = 6'b000100;\n 12'd982 : mem_out_dec = 6'b000101;\n 12'd983 : mem_out_dec = 6'b000110;\n 12'd984 : mem_out_dec = 6'b000110;\n 12'd985 : mem_out_dec = 6'b000111;\n 12'd986 : mem_out_dec = 6'b000111;\n 12'd987 : mem_out_dec = 6'b001000;\n 12'd988 : mem_out_dec = 6'b001001;\n 12'd989 : mem_out_dec = 6'b001010;\n 12'd990 : mem_out_dec = 6'b001010;\n 12'd991 : mem_out_dec = 6'b001011;\n 12'd992 : mem_out_dec = 6'b001011;\n 12'd993 : mem_out_dec = 6'b001011;\n 12'd994 : mem_out_dec = 6'b001100;\n 12'd995 : mem_out_dec = 6'b001100;\n 12'd996 : mem_out_dec = 6'b001101;\n 12'd997 : mem_out_dec = 6'b001110;\n 12'd998 : mem_out_dec = 6'b001110;\n 12'd999 : mem_out_dec = 6'b001110;\n 12'd1000 : mem_out_dec = 6'b001101;\n 12'd1001 : mem_out_dec = 6'b001110;\n 12'd1002 : mem_out_dec = 6'b001110;\n 12'd1003 : mem_out_dec = 6'b001111;\n 12'd1004 : mem_out_dec = 6'b001111;\n 12'd1005 : mem_out_dec = 6'b010000;\n 12'd1006 : mem_out_dec = 6'b010000;\n 12'd1007 : mem_out_dec = 6'b010001;\n 12'd1008 : mem_out_dec = 6'b010001;\n 12'd1009 : mem_out_dec = 6'b010010;\n 12'd1010 : mem_out_dec = 6'b010011;\n 12'd1011 : mem_out_dec = 6'b010011;\n 12'd1012 : mem_out_dec = 6'b010100;\n 12'd1013 : mem_out_dec = 6'b010100;\n 12'd1014 : mem_out_dec = 6'b010101;\n 12'd1015 : mem_out_dec = 6'b010110;\n 12'd1016 : mem_out_dec = 6'b010110;\n 12'd1017 : mem_out_dec = 6'b010110;\n 12'd1018 : mem_out_dec = 6'b010111;\n 12'd1019 : mem_out_dec = 6'b011000;\n 12'd1020 : mem_out_dec = 6'b011001;\n 12'd1021 : mem_out_dec = 6'b011001;\n 12'd1022 : mem_out_dec = 6'b011010;\n 12'd1023 : mem_out_dec = 6'b011011;\n 12'd1024 : mem_out_dec = 6'b111111;\n 12'd1025 : mem_out_dec = 6'b111111;\n 12'd1026 : mem_out_dec = 6'b111111;\n 12'd1027 : mem_out_dec = 6'b111111;\n 12'd1028 : mem_out_dec = 6'b111111;\n 12'd1029 : mem_out_dec = 6'b111111;\n 12'd1030 : mem_out_dec = 6'b111111;\n 12'd1031 : mem_out_dec = 6'b111111;\n 12'd1032 : mem_out_dec = 6'b111111;\n 12'd1033 : mem_out_dec = 6'b111111;\n 12'd1034 : mem_out_dec = 6'b111111;\n 12'd1035 : mem_out_dec = 6'b111111;\n 12'd1036 : mem_out_dec = 6'b111111;\n 12'd1037 : mem_out_dec = 6'b111111;\n 12'd1038 : mem_out_dec = 6'b111111;\n 12'd1039 : mem_out_dec = 6'b111111;\n 12'd1040 : mem_out_dec = 6'b111111;\n 12'd1041 : mem_out_dec = 6'b111111;\n 12'd1042 : mem_out_dec = 6'b111111;\n 12'd1043 : mem_out_dec = 6'b111111;\n 12'd1044 : mem_out_dec = 6'b111111;\n 12'd1045 : mem_out_dec = 6'b111111;\n 12'd1046 : mem_out_dec = 6'b000100;\n 12'd1047 : mem_out_dec = 6'b000101;\n 12'd1048 : mem_out_dec = 6'b000101;\n 12'd1049 : mem_out_dec = 6'b000110;\n 12'd1050 : mem_out_dec = 6'b000110;\n 12'd1051 : mem_out_dec = 6'b000111;\n 12'd1052 : mem_out_dec = 6'b001000;\n 12'd1053 : mem_out_dec = 6'b001001;\n 12'd1054 : mem_out_dec = 6'b001001;\n 12'd1055 : mem_out_dec = 6'b001010;\n 12'd1056 : mem_out_dec = 6'b001010;\n 12'd1057 : mem_out_dec = 6'b001011;\n 12'd1058 : mem_out_dec = 6'b001011;\n 12'd1059 : mem_out_dec = 6'b001100;\n 12'd1060 : mem_out_dec = 6'b001100;\n 12'd1061 : mem_out_dec = 6'b001100;\n 12'd1062 : mem_out_dec = 6'b001100;\n 12'd1063 : mem_out_dec = 6'b001100;\n 12'd1064 : mem_out_dec = 6'b001100;\n 12'd1065 : mem_out_dec = 6'b001100;\n 12'd1066 : mem_out_dec = 6'b001101;\n 12'd1067 : mem_out_dec = 6'b001101;\n 12'd1068 : mem_out_dec = 6'b001110;\n 12'd1069 : mem_out_dec = 6'b001111;\n 12'd1070 : mem_out_dec = 6'b010000;\n 12'd1071 : mem_out_dec = 6'b010000;\n 12'd1072 : mem_out_dec = 6'b010001;\n 12'd1073 : mem_out_dec = 6'b010001;\n 12'd1074 : mem_out_dec = 6'b010010;\n 12'd1075 : mem_out_dec = 6'b010010;\n 12'd1076 : mem_out_dec = 6'b010011;\n 12'd1077 : mem_out_dec = 6'b010011;\n 12'd1078 : mem_out_dec = 6'b010100;\n 12'd1079 : mem_out_dec = 6'b010101;\n 12'd1080 : mem_out_dec = 6'b010101;\n 12'd1081 : mem_out_dec = 6'b010110;\n 12'd1082 : mem_out_dec = 6'b010110;\n 12'd1083 : mem_out_dec = 6'b010111;\n 12'd1084 : mem_out_dec = 6'b011000;\n 12'd1085 : mem_out_dec = 6'b011000;\n 12'd1086 : mem_out_dec = 6'b011001;\n 12'd1087 : mem_out_dec = 6'b011010;\n 12'd1088 : mem_out_dec = 6'b111111;\n 12'd1089 : mem_out_dec = 6'b111111;\n 12'd1090 : mem_out_dec = 6'b111111;\n 12'd1091 : mem_out_dec = 6'b111111;\n 12'd1092 : mem_out_dec = 6'b111111;\n 12'd1093 : mem_out_dec = 6'b111111;\n 12'd1094 : mem_out_dec = 6'b111111;\n 12'd1095 : mem_out_dec = 6'b111111;\n 12'd1096 : mem_out_dec = 6'b111111;\n 12'd1097 : mem_out_dec = 6'b111111;\n 12'd1098 : mem_out_dec = 6'b111111;\n 12'd1099 : mem_out_dec = 6'b111111;\n 12'd1100 : mem_out_dec = 6'b111111;\n 12'd1101 : mem_out_dec = 6'b111111;\n 12'd1102 : mem_out_dec = 6'b111111;\n 12'd1103 : mem_out_dec = 6'b111111;\n 12'd1104 : mem_out_dec = 6'b111111;\n 12'd1105 : mem_out_dec = 6'b111111;\n 12'd1106 : mem_out_dec = 6'b111111;\n 12'd1107 : mem_out_dec = 6'b111111;\n 12'd1108 : mem_out_dec = 6'b111111;\n 12'd1109 : mem_out_dec = 6'b111111;\n 12'd1110 : mem_out_dec = 6'b111111;\n 12'd1111 : mem_out_dec = 6'b000100;\n 12'd1112 : mem_out_dec = 6'b000100;\n 12'd1113 : mem_out_dec = 6'b000101;\n 12'd1114 : mem_out_dec = 6'b000110;\n 12'd1115 : mem_out_dec = 6'b000111;\n 12'd1116 : mem_out_dec = 6'b000111;\n 12'd1117 : mem_out_dec = 6'b001000;\n 12'd1118 : mem_out_dec = 6'b001001;\n 12'd1119 : mem_out_dec = 6'b001001;\n 12'd1120 : mem_out_dec = 6'b001010;\n 12'd1121 : mem_out_dec = 6'b001010;\n 12'd1122 : mem_out_dec = 6'b001011;\n 12'd1123 : mem_out_dec = 6'b001011;\n 12'd1124 : mem_out_dec = 6'b001011;\n 12'd1125 : mem_out_dec = 6'b001011;\n 12'd1126 : mem_out_dec = 6'b001011;\n 12'd1127 : mem_out_dec = 6'b001011;\n 12'd1128 : mem_out_dec = 6'b001011;\n 12'd1129 : mem_out_dec = 6'b001011;\n 12'd1130 : mem_out_dec = 6'b001100;\n 12'd1131 : mem_out_dec = 6'b001101;\n 12'd1132 : mem_out_dec = 6'b001110;\n 12'd1133 : mem_out_dec = 6'b001110;\n 12'd1134 : mem_out_dec = 6'b001111;\n 12'd1135 : mem_out_dec = 6'b010000;\n 12'd1136 : mem_out_dec = 6'b010000;\n 12'd1137 : mem_out_dec = 6'b010001;\n 12'd1138 : mem_out_dec = 6'b010001;\n 12'd1139 : mem_out_dec = 6'b010010;\n 12'd1140 : mem_out_dec = 6'b010010;\n 12'd1141 : mem_out_dec = 6'b010011;\n 12'd1142 : mem_out_dec = 6'b010100;\n 12'd1143 : mem_out_dec = 6'b010100;\n 12'd1144 : mem_out_dec = 6'b010100;\n 12'd1145 : mem_out_dec = 6'b010101;\n 12'd1146 : mem_out_dec = 6'b010110;\n 12'd1147 : mem_out_dec = 6'b010110;\n 12'd1148 : mem_out_dec = 6'b010111;\n 12'd1149 : mem_out_dec = 6'b011000;\n 12'd1150 : mem_out_dec = 6'b011000;\n 12'd1151 : mem_out_dec = 6'b011001;\n 12'd1152 : mem_out_dec = 6'b111111;\n 12'd1153 : mem_out_dec = 6'b111111;\n 12'd1154 : mem_out_dec = 6'b111111;\n 12'd1155 : mem_out_dec = 6'b111111;\n 12'd1156 : mem_out_dec = 6'b111111;\n 12'd1157 : mem_out_dec = 6'b111111;\n 12'd1158 : mem_out_dec = 6'b111111;\n 12'd1159 : mem_out_dec = 6'b111111;\n 12'd1160 : mem_out_dec = 6'b111111;\n 12'd1161 : mem_out_dec = 6'b111111;\n 12'd1162 : mem_out_dec = 6'b111111;\n 12'd1163 : mem_out_dec = 6'b111111;\n 12'd1164 : mem_out_dec = 6'b111111;\n 12'd1165 : mem_out_dec = 6'b111111;\n 12'd1166 : mem_out_dec = 6'b111111;\n 12'd1167 : mem_out_dec = 6'b111111;\n 12'd1168 : mem_out_dec = 6'b111111;\n 12'd1169 : mem_out_dec = 6'b111111;\n 12'd1170 : mem_out_dec = 6'b111111;\n 12'd1171 : mem_out_dec = 6'b111111;\n 12'd1172 : mem_out_dec = 6'b111111;\n 12'd1173 : mem_out_dec = 6'b111111;\n 12'd1174 : mem_out_dec = 6'b111111;\n 12'd1175 : mem_out_dec = 6'b111111;\n 12'd1176 : mem_out_dec = 6'b000100;\n 12'd1177 : mem_out_dec = 6'b000101;\n 12'd1178 : mem_out_dec = 6'b000101;\n 12'd1179 : mem_out_dec = 6'b000110;\n 12'd1180 : mem_out_dec = 6'b000111;\n 12'd1181 : mem_out_dec = 6'b000111;\n 12'd1182 : mem_out_dec = 6'b001000;\n 12'd1183 : mem_out_dec = 6'b001001;\n 12'd1184 : mem_out_dec = 6'b001001;\n 12'd1185 : mem_out_dec = 6'b001010;\n 12'd1186 : mem_out_dec = 6'b001010;\n 12'd1187 : mem_out_dec = 6'b001010;\n 12'd1188 : mem_out_dec = 6'b001010;\n 12'd1189 : mem_out_dec = 6'b001010;\n 12'd1190 : mem_out_dec = 6'b001010;\n 12'd1191 : mem_out_dec = 6'b001010;\n 12'd1192 : mem_out_dec = 6'b001010;\n 12'd1193 : mem_out_dec = 6'b001011;\n 12'd1194 : mem_out_dec = 6'b001100;\n 12'd1195 : mem_out_dec = 6'b001100;\n 12'd1196 : mem_out_dec = 6'b001101;\n 12'd1197 : mem_out_dec = 6'b001110;\n 12'd1198 : mem_out_dec = 6'b001111;\n 12'd1199 : mem_out_dec = 6'b010000;\n 12'd1200 : mem_out_dec = 6'b010000;\n 12'd1201 : mem_out_dec = 6'b010000;\n 12'd1202 : mem_out_dec = 6'b010001;\n 12'd1203 : mem_out_dec = 6'b010001;\n 12'd1204 : mem_out_dec = 6'b010010;\n 12'd1205 : mem_out_dec = 6'b010011;\n 12'd1206 : mem_out_dec = 6'b010011;\n 12'd1207 : mem_out_dec = 6'b010100;\n 12'd1208 : mem_out_dec = 6'b010100;\n 12'd1209 : mem_out_dec = 6'b010100;\n 12'd1210 : mem_out_dec = 6'b010101;\n 12'd1211 : mem_out_dec = 6'b010110;\n 12'd1212 : mem_out_dec = 6'b010110;\n 12'd1213 : mem_out_dec = 6'b010111;\n 12'd1214 : mem_out_dec = 6'b011000;\n 12'd1215 : mem_out_dec = 6'b011001;\n 12'd1216 : mem_out_dec = 6'b111111;\n 12'd1217 : mem_out_dec = 6'b111111;\n 12'd1218 : mem_out_dec = 6'b111111;\n 12'd1219 : mem_out_dec = 6'b111111;\n 12'd1220 : mem_out_dec = 6'b111111;\n 12'd1221 : mem_out_dec = 6'b111111;\n 12'd1222 : mem_out_dec = 6'b111111;\n 12'd1223 : mem_out_dec = 6'b111111;\n 12'd1224 : mem_out_dec = 6'b111111;\n 12'd1225 : mem_out_dec = 6'b111111;\n 12'd1226 : mem_out_dec = 6'b111111;\n 12'd1227 : mem_out_dec = 6'b111111;\n 12'd1228 : mem_out_dec = 6'b111111;\n 12'd1229 : mem_out_dec = 6'b111111;\n 12'd1230 : mem_out_dec = 6'b111111;\n 12'd1231 : mem_out_dec = 6'b111111;\n 12'd1232 : mem_out_dec = 6'b111111;\n 12'd1233 : mem_out_dec = 6'b111111;\n 12'd1234 : mem_out_dec = 6'b111111;\n 12'd1235 : mem_out_dec = 6'b111111;\n 12'd1236 : mem_out_dec = 6'b111111;\n 12'd1237 : mem_out_dec = 6'b111111;\n 12'd1238 : mem_out_dec = 6'b111111;\n 12'd1239 : mem_out_dec = 6'b111111;\n 12'd1240 : mem_out_dec = 6'b111111;\n 12'd1241 : mem_out_dec = 6'b000100;\n 12'd1242 : mem_out_dec = 6'b000100;\n 12'd1243 : mem_out_dec = 6'b000101;\n 12'd1244 : mem_out_dec = 6'b000110;\n 12'd1245 : mem_out_dec = 6'b000111;\n 12'd1246 : mem_out_dec = 6'b001000;\n 12'd1247 : mem_out_dec = 6'b001000;\n 12'd1248 : mem_out_dec = 6'b001001;\n 12'd1249 : mem_out_dec = 6'b001001;\n 12'd1250 : mem_out_dec = 6'b001001;\n 12'd1251 : mem_out_dec = 6'b001001;\n 12'd1252 : mem_out_dec = 6'b001001;\n 12'd1253 : mem_out_dec = 6'b001001;\n 12'd1254 : mem_out_dec = 6'b001001;\n 12'd1255 : mem_out_dec = 6'b001001;\n 12'd1256 : mem_out_dec = 6'b001010;\n 12'd1257 : mem_out_dec = 6'b001010;\n 12'd1258 : mem_out_dec = 6'b001011;\n 12'd1259 : mem_out_dec = 6'b001100;\n 12'd1260 : mem_out_dec = 6'b001101;\n 12'd1261 : mem_out_dec = 6'b001110;\n 12'd1262 : mem_out_dec = 6'b001110;\n 12'd1263 : mem_out_dec = 6'b001111;\n 12'd1264 : mem_out_dec = 6'b001111;\n 12'd1265 : mem_out_dec = 6'b010000;\n 12'd1266 : mem_out_dec = 6'b010000;\n 12'd1267 : mem_out_dec = 6'b010001;\n 12'd1268 : mem_out_dec = 6'b010001;\n 12'd1269 : mem_out_dec = 6'b010010;\n 12'd1270 : mem_out_dec = 6'b010011;\n 12'd1271 : mem_out_dec = 6'b010011;\n 12'd1272 : mem_out_dec = 6'b010011;\n 12'd1273 : mem_out_dec = 6'b010100;\n 12'd1274 : mem_out_dec = 6'b010100;\n 12'd1275 : mem_out_dec = 6'b010101;\n 12'd1276 : mem_out_dec = 6'b010110;\n 12'd1277 : mem_out_dec = 6'b010111;\n 12'd1278 : mem_out_dec = 6'b011000;\n 12'd1279 : mem_out_dec = 6'b011000;\n 12'd1280 : mem_out_dec = 6'b111111;\n 12'd1281 : mem_out_dec = 6'b111111;\n 12'd1282 : mem_out_dec = 6'b111111;\n 12'd1283 : mem_out_dec = 6'b111111;\n 12'd1284 : mem_out_dec = 6'b111111;\n 12'd1285 : mem_out_dec = 6'b111111;\n 12'd1286 : mem_out_dec = 6'b111111;\n 12'd1287 : mem_out_dec = 6'b111111;\n 12'd1288 : mem_out_dec = 6'b111111;\n 12'd1289 : mem_out_dec = 6'b111111;\n 12'd1290 : mem_out_dec = 6'b111111;\n 12'd1291 : mem_out_dec = 6'b111111;\n 12'd1292 : mem_out_dec = 6'b111111;\n 12'd1293 : mem_out_dec = 6'b111111;\n 12'd1294 : mem_out_dec = 6'b111111;\n 12'd1295 : mem_out_dec = 6'b111111;\n 12'd1296 : mem_out_dec = 6'b111111;\n 12'd1297 : mem_out_dec = 6'b111111;\n 12'd1298 : mem_out_dec = 6'b111111;\n 12'd1299 : mem_out_dec = 6'b111111;\n 12'd1300 : mem_out_dec = 6'b111111;\n 12'd1301 : mem_out_dec = 6'b111111;\n 12'd1302 : mem_out_dec = 6'b111111;\n 12'd1303 : mem_out_dec = 6'b111111;\n 12'd1304 : mem_out_dec = 6'b111111;\n 12'd1305 : mem_out_dec = 6'b111111;\n 12'd1306 : mem_out_dec = 6'b000100;\n 12'd1307 : mem_out_dec = 6'b000101;\n 12'd1308 : mem_out_dec = 6'b000110;\n 12'd1309 : mem_out_dec = 6'b000110;\n 12'd1310 : mem_out_dec = 6'b000111;\n 12'd1311 : mem_out_dec = 6'b001000;\n 12'd1312 : mem_out_dec = 6'b001000;\n 12'd1313 : mem_out_dec = 6'b001000;\n 12'd1314 : mem_out_dec = 6'b001000;\n 12'd1315 : mem_out_dec = 6'b001000;\n 12'd1316 : mem_out_dec = 6'b001000;\n 12'd1317 : mem_out_dec = 6'b001000;\n 12'd1318 : mem_out_dec = 6'b001000;\n 12'd1319 : mem_out_dec = 6'b001001;\n 12'd1320 : mem_out_dec = 6'b001001;\n 12'd1321 : mem_out_dec = 6'b001010;\n 12'd1322 : mem_out_dec = 6'b001011;\n 12'd1323 : mem_out_dec = 6'b001100;\n 12'd1324 : mem_out_dec = 6'b001100;\n 12'd1325 : mem_out_dec = 6'b001101;\n 12'd1326 : mem_out_dec = 6'b001110;\n 12'd1327 : mem_out_dec = 6'b001111;\n 12'd1328 : mem_out_dec = 6'b001111;\n 12'd1329 : mem_out_dec = 6'b001111;\n 12'd1330 : mem_out_dec = 6'b010000;\n 12'd1331 : mem_out_dec = 6'b010000;\n 12'd1332 : mem_out_dec = 6'b010001;\n 12'd1333 : mem_out_dec = 6'b010001;\n 12'd1334 : mem_out_dec = 6'b010010;\n 12'd1335 : mem_out_dec = 6'b010011;\n 12'd1336 : mem_out_dec = 6'b010010;\n 12'd1337 : mem_out_dec = 6'b010011;\n 12'd1338 : mem_out_dec = 6'b010100;\n 12'd1339 : mem_out_dec = 6'b010101;\n 12'd1340 : mem_out_dec = 6'b010110;\n 12'd1341 : mem_out_dec = 6'b010110;\n 12'd1342 : mem_out_dec = 6'b010111;\n 12'd1343 : mem_out_dec = 6'b011000;\n 12'd1344 : mem_out_dec = 6'b111111;\n 12'd1345 : mem_out_dec = 6'b111111;\n 12'd1346 : mem_out_dec = 6'b111111;\n 12'd1347 : mem_out_dec = 6'b111111;\n 12'd1348 : mem_out_dec = 6'b111111;\n 12'd1349 : mem_out_dec = 6'b111111;\n 12'd1350 : mem_out_dec = 6'b111111;\n 12'd1351 : mem_out_dec = 6'b111111;\n 12'd1352 : mem_out_dec = 6'b111111;\n 12'd1353 : mem_out_dec = 6'b111111;\n 12'd1354 : mem_out_dec = 6'b111111;\n 12'd1355 : mem_out_dec = 6'b111111;\n 12'd1356 : mem_out_dec = 6'b111111;\n 12'd1357 : mem_out_dec = 6'b111111;\n 12'd1358 : mem_out_dec = 6'b111111;\n 12'd1359 : mem_out_dec = 6'b111111;\n 12'd1360 : mem_out_dec = 6'b111111;\n 12'd1361 : mem_out_dec = 6'b111111;\n 12'd1362 : mem_out_dec = 6'b111111;\n 12'd1363 : mem_out_dec = 6'b111111;\n 12'd1364 : mem_out_dec = 6'b111111;\n 12'd1365 : mem_out_dec = 6'b111111;\n 12'd1366 : mem_out_dec = 6'b111111;\n 12'd1367 : mem_out_dec = 6'b111111;\n 12'd1368 : mem_out_dec = 6'b111111;\n 12'd1369 : mem_out_dec = 6'b111111;\n 12'd1370 : mem_out_dec = 6'b111111;\n 12'd1371 : mem_out_dec = 6'b000101;\n 12'd1372 : mem_out_dec = 6'b000101;\n 12'd1373 : mem_out_dec = 6'b000110;\n 12'd1374 : mem_out_dec = 6'b000111;\n 12'd1375 : mem_out_dec = 6'b001000;\n 12'd1376 : mem_out_dec = 6'b000111;\n 12'd1377 : mem_out_dec = 6'b000111;\n 12'd1378 : mem_out_dec = 6'b000111;\n 12'd1379 : mem_out_dec = 6'b000111;\n 12'd1380 : mem_out_dec = 6'b000111;\n 12'd1381 : mem_out_dec = 6'b000111;\n 12'd1382 : mem_out_dec = 6'b001000;\n 12'd1383 : mem_out_dec = 6'b001001;\n 12'd1384 : mem_out_dec = 6'b001001;\n 12'd1385 : mem_out_dec = 6'b001010;\n 12'd1386 : mem_out_dec = 6'b001010;\n 12'd1387 : mem_out_dec = 6'b001011;\n 12'd1388 : mem_out_dec = 6'b001100;\n 12'd1389 : mem_out_dec = 6'b001101;\n 12'd1390 : mem_out_dec = 6'b001110;\n 12'd1391 : mem_out_dec = 6'b001110;\n 12'd1392 : mem_out_dec = 6'b001111;\n 12'd1393 : mem_out_dec = 6'b001111;\n 12'd1394 : mem_out_dec = 6'b010000;\n 12'd1395 : mem_out_dec = 6'b010000;\n 12'd1396 : mem_out_dec = 6'b010001;\n 12'd1397 : mem_out_dec = 6'b010001;\n 12'd1398 : mem_out_dec = 6'b010010;\n 12'd1399 : mem_out_dec = 6'b010010;\n 12'd1400 : mem_out_dec = 6'b010010;\n 12'd1401 : mem_out_dec = 6'b010011;\n 12'd1402 : mem_out_dec = 6'b010100;\n 12'd1403 : mem_out_dec = 6'b010100;\n 12'd1404 : mem_out_dec = 6'b010101;\n 12'd1405 : mem_out_dec = 6'b010110;\n 12'd1406 : mem_out_dec = 6'b010111;\n 12'd1407 : mem_out_dec = 6'b010111;\n 12'd1408 : mem_out_dec = 6'b111111;\n 12'd1409 : mem_out_dec = 6'b111111;\n 12'd1410 : mem_out_dec = 6'b111111;\n 12'd1411 : mem_out_dec = 6'b111111;\n 12'd1412 : mem_out_dec = 6'b111111;\n 12'd1413 : mem_out_dec = 6'b111111;\n 12'd1414 : mem_out_dec = 6'b111111;\n 12'd1415 : mem_out_dec = 6'b111111;\n 12'd1416 : mem_out_dec = 6'b111111;\n 12'd1417 : mem_out_dec = 6'b111111;\n 12'd1418 : mem_out_dec = 6'b111111;\n 12'd1419 : mem_out_dec = 6'b111111;\n 12'd1420 : mem_out_dec = 6'b111111;\n 12'd1421 : mem_out_dec = 6'b111111;\n 12'd1422 : mem_out_dec = 6'b111111;\n 12'd1423 : mem_out_dec = 6'b111111;\n 12'd1424 : mem_out_dec = 6'b111111;\n 12'd1425 : mem_out_dec = 6'b111111;\n 12'd1426 : mem_out_dec = 6'b111111;\n 12'd1427 : mem_out_dec = 6'b111111;\n 12'd1428 : mem_out_dec = 6'b111111;\n 12'd1429 : mem_out_dec = 6'b111111;\n 12'd1430 : mem_out_dec = 6'b111111;\n 12'd1431 : mem_out_dec = 6'b111111;\n 12'd1432 : mem_out_dec = 6'b111111;\n 12'd1433 : mem_out_dec = 6'b111111;\n 12'd1434 : mem_out_dec = 6'b111111;\n 12'd1435 : mem_out_dec = 6'b111111;\n 12'd1436 : mem_out_dec = 6'b000101;\n 12'd1437 : mem_out_dec = 6'b000110;\n 12'd1438 : mem_out_dec = 6'b000111;\n 12'd1439 : mem_out_dec = 6'b000111;\n 12'd1440 : mem_out_dec = 6'b000110;\n 12'd1441 : mem_out_dec = 6'b000110;\n 12'd1442 : mem_out_dec = 6'b000110;\n 12'd1443 : mem_out_dec = 6'b000110;\n 12'd1444 : mem_out_dec = 6'b000110;\n 12'd1445 : mem_out_dec = 6'b000111;\n 12'd1446 : mem_out_dec = 6'b000111;\n 12'd1447 : mem_out_dec = 6'b001000;\n 12'd1448 : mem_out_dec = 6'b001001;\n 12'd1449 : mem_out_dec = 6'b001001;\n 12'd1450 : mem_out_dec = 6'b001010;\n 12'd1451 : mem_out_dec = 6'b001011;\n 12'd1452 : mem_out_dec = 6'b001100;\n 12'd1453 : mem_out_dec = 6'b001100;\n 12'd1454 : mem_out_dec = 6'b001101;\n 12'd1455 : mem_out_dec = 6'b001110;\n 12'd1456 : mem_out_dec = 6'b001110;\n 12'd1457 : mem_out_dec = 6'b001111;\n 12'd1458 : mem_out_dec = 6'b001111;\n 12'd1459 : mem_out_dec = 6'b010000;\n 12'd1460 : mem_out_dec = 6'b010000;\n 12'd1461 : mem_out_dec = 6'b010001;\n 12'd1462 : mem_out_dec = 6'b010001;\n 12'd1463 : mem_out_dec = 6'b010010;\n 12'd1464 : mem_out_dec = 6'b010010;\n 12'd1465 : mem_out_dec = 6'b010011;\n 12'd1466 : mem_out_dec = 6'b010011;\n 12'd1467 : mem_out_dec = 6'b010100;\n 12'd1468 : mem_out_dec = 6'b010101;\n 12'd1469 : mem_out_dec = 6'b010110;\n 12'd1470 : mem_out_dec = 6'b010110;\n 12'd1471 : mem_out_dec = 6'b010111;\n 12'd1472 : mem_out_dec = 6'b111111;\n 12'd1473 : mem_out_dec = 6'b111111;\n 12'd1474 : mem_out_dec = 6'b111111;\n 12'd1475 : mem_out_dec = 6'b111111;\n 12'd1476 : mem_out_dec = 6'b111111;\n 12'd1477 : mem_out_dec = 6'b111111;\n 12'd1478 : mem_out_dec = 6'b111111;\n 12'd1479 : mem_out_dec = 6'b111111;\n 12'd1480 : mem_out_dec = 6'b111111;\n 12'd1481 : mem_out_dec = 6'b111111;\n 12'd1482 : mem_out_dec = 6'b111111;\n 12'd1483 : mem_out_dec = 6'b111111;\n 12'd1484 : mem_out_dec = 6'b111111;\n 12'd1485 : mem_out_dec = 6'b111111;\n 12'd1486 : mem_out_dec = 6'b111111;\n 12'd1487 : mem_out_dec = 6'b111111;\n 12'd1488 : mem_out_dec = 6'b111111;\n 12'd1489 : mem_out_dec = 6'b111111;\n 12'd1490 : mem_out_dec = 6'b111111;\n 12'd1491 : mem_out_dec = 6'b111111;\n 12'd1492 : mem_out_dec = 6'b111111;\n 12'd1493 : mem_out_dec = 6'b111111;\n 12'd1494 : mem_out_dec = 6'b111111;\n 12'd1495 : mem_out_dec = 6'b111111;\n 12'd1496 : mem_out_dec = 6'b111111;\n 12'd1497 : mem_out_dec = 6'b111111;\n 12'd1498 : mem_out_dec = 6'b111111;\n 12'd1499 : mem_out_dec = 6'b111111;\n 12'd1500 : mem_out_dec = 6'b111111;\n 12'd1501 : mem_out_dec = 6'b000101;\n 12'd1502 : mem_out_dec = 6'b000110;\n 12'd1503 : mem_out_dec = 6'b000110;\n 12'd1504 : mem_out_dec = 6'b000110;\n 12'd1505 : mem_out_dec = 6'b000110;\n 12'd1506 : mem_out_dec = 6'b000101;\n 12'd1507 : mem_out_dec = 6'b000101;\n 12'd1508 : mem_out_dec = 6'b000110;\n 12'd1509 : mem_out_dec = 6'b000111;\n 12'd1510 : mem_out_dec = 6'b000111;\n 12'd1511 : mem_out_dec = 6'b001000;\n 12'd1512 : mem_out_dec = 6'b001000;\n 12'd1513 : mem_out_dec = 6'b001001;\n 12'd1514 : mem_out_dec = 6'b001010;\n 12'd1515 : mem_out_dec = 6'b001011;\n 12'd1516 : mem_out_dec = 6'b001011;\n 12'd1517 : mem_out_dec = 6'b001100;\n 12'd1518 : mem_out_dec = 6'b001101;\n 12'd1519 : mem_out_dec = 6'b001110;\n 12'd1520 : mem_out_dec = 6'b001110;\n 12'd1521 : mem_out_dec = 6'b001110;\n 12'd1522 : mem_out_dec = 6'b001111;\n 12'd1523 : mem_out_dec = 6'b001111;\n 12'd1524 : mem_out_dec = 6'b010000;\n 12'd1525 : mem_out_dec = 6'b010000;\n 12'd1526 : mem_out_dec = 6'b010001;\n 12'd1527 : mem_out_dec = 6'b010001;\n 12'd1528 : mem_out_dec = 6'b010001;\n 12'd1529 : mem_out_dec = 6'b010010;\n 12'd1530 : mem_out_dec = 6'b010011;\n 12'd1531 : mem_out_dec = 6'b010100;\n 12'd1532 : mem_out_dec = 6'b010101;\n 12'd1533 : mem_out_dec = 6'b010101;\n 12'd1534 : mem_out_dec = 6'b010110;\n 12'd1535 : mem_out_dec = 6'b010110;\n 12'd1536 : mem_out_dec = 6'b111111;\n 12'd1537 : mem_out_dec = 6'b111111;\n 12'd1538 : mem_out_dec = 6'b111111;\n 12'd1539 : mem_out_dec = 6'b111111;\n 12'd1540 : mem_out_dec = 6'b111111;\n 12'd1541 : mem_out_dec = 6'b111111;\n 12'd1542 : mem_out_dec = 6'b111111;\n 12'd1543 : mem_out_dec = 6'b111111;\n 12'd1544 : mem_out_dec = 6'b111111;\n 12'd1545 : mem_out_dec = 6'b111111;\n 12'd1546 : mem_out_dec = 6'b111111;\n 12'd1547 : mem_out_dec = 6'b111111;\n 12'd1548 : mem_out_dec = 6'b111111;\n 12'd1549 : mem_out_dec = 6'b111111;\n 12'd1550 : mem_out_dec = 6'b111111;\n 12'd1551 : mem_out_dec = 6'b111111;\n 12'd1552 : mem_out_dec = 6'b111111;\n 12'd1553 : mem_out_dec = 6'b111111;\n 12'd1554 : mem_out_dec = 6'b111111;\n 12'd1555 : mem_out_dec = 6'b111111;\n 12'd1556 : mem_out_dec = 6'b111111;\n 12'd1557 : mem_out_dec = 6'b111111;\n 12'd1558 : mem_out_dec = 6'b111111;\n 12'd1559 : mem_out_dec = 6'b111111;\n 12'd1560 : mem_out_dec = 6'b111111;\n 12'd1561 : mem_out_dec = 6'b111111;\n 12'd1562 : mem_out_dec = 6'b111111;\n 12'd1563 : mem_out_dec = 6'b111111;\n 12'd1564 : mem_out_dec = 6'b111111;\n 12'd1565 : mem_out_dec = 6'b111111;\n 12'd1566 : mem_out_dec = 6'b000100;\n 12'd1567 : mem_out_dec = 6'b000100;\n 12'd1568 : mem_out_dec = 6'b000100;\n 12'd1569 : mem_out_dec = 6'b000100;\n 12'd1570 : mem_out_dec = 6'b000100;\n 12'd1571 : mem_out_dec = 6'b000101;\n 12'd1572 : mem_out_dec = 6'b000101;\n 12'd1573 : mem_out_dec = 6'b000110;\n 12'd1574 : mem_out_dec = 6'b000111;\n 12'd1575 : mem_out_dec = 6'b000111;\n 12'd1576 : mem_out_dec = 6'b000111;\n 12'd1577 : mem_out_dec = 6'b001000;\n 12'd1578 : mem_out_dec = 6'b001001;\n 12'd1579 : mem_out_dec = 6'b001010;\n 12'd1580 : mem_out_dec = 6'b001010;\n 12'd1581 : mem_out_dec = 6'b001011;\n 12'd1582 : mem_out_dec = 6'b001100;\n 12'd1583 : mem_out_dec = 6'b001101;\n 12'd1584 : mem_out_dec = 6'b001101;\n 12'd1585 : mem_out_dec = 6'b001101;\n 12'd1586 : mem_out_dec = 6'b001110;\n 12'd1587 : mem_out_dec = 6'b001110;\n 12'd1588 : mem_out_dec = 6'b001111;\n 12'd1589 : mem_out_dec = 6'b001111;\n 12'd1590 : mem_out_dec = 6'b010000;\n 12'd1591 : mem_out_dec = 6'b010001;\n 12'd1592 : mem_out_dec = 6'b010001;\n 12'd1593 : mem_out_dec = 6'b010001;\n 12'd1594 : mem_out_dec = 6'b010010;\n 12'd1595 : mem_out_dec = 6'b010010;\n 12'd1596 : mem_out_dec = 6'b010011;\n 12'd1597 : mem_out_dec = 6'b010011;\n 12'd1598 : mem_out_dec = 6'b010100;\n 12'd1599 : mem_out_dec = 6'b010100;\n 12'd1600 : mem_out_dec = 6'b111111;\n 12'd1601 : mem_out_dec = 6'b111111;\n 12'd1602 : mem_out_dec = 6'b111111;\n 12'd1603 : mem_out_dec = 6'b111111;\n 12'd1604 : mem_out_dec = 6'b111111;\n 12'd1605 : mem_out_dec = 6'b111111;\n 12'd1606 : mem_out_dec = 6'b111111;\n 12'd1607 : mem_out_dec = 6'b111111;\n 12'd1608 : mem_out_dec = 6'b111111;\n 12'd1609 : mem_out_dec = 6'b111111;\n 12'd1610 : mem_out_dec = 6'b111111;\n 12'd1611 : mem_out_dec = 6'b111111;\n 12'd1612 : mem_out_dec = 6'b111111;\n 12'd1613 : mem_out_dec = 6'b111111;\n 12'd1614 : mem_out_dec = 6'b111111;\n 12'd1615 : mem_out_dec = 6'b111111;\n 12'd1616 : mem_out_dec = 6'b111111;\n 12'd1617 : mem_out_dec = 6'b111111;\n 12'd1618 : mem_out_dec = 6'b111111;\n 12'd1619 : mem_out_dec = 6'b111111;\n 12'd1620 : mem_out_dec = 6'b111111;\n 12'd1621 : mem_out_dec = 6'b111111;\n 12'd1622 : mem_out_dec = 6'b111111;\n 12'd1623 : mem_out_dec = 6'b111111;\n 12'd1624 : mem_out_dec = 6'b111111;\n 12'd1625 : mem_out_dec = 6'b111111;\n 12'd1626 : mem_out_dec = 6'b111111;\n 12'd1627 : mem_out_dec = 6'b111111;\n 12'd1628 : mem_out_dec = 6'b111111;\n 12'd1629 : mem_out_dec = 6'b111111;\n 12'd1630 : mem_out_dec = 6'b111111;\n 12'd1631 : mem_out_dec = 6'b000100;\n 12'd1632 : mem_out_dec = 6'b000011;\n 12'd1633 : mem_out_dec = 6'b000011;\n 12'd1634 : mem_out_dec = 6'b000100;\n 12'd1635 : mem_out_dec = 6'b000100;\n 12'd1636 : mem_out_dec = 6'b000101;\n 12'd1637 : mem_out_dec = 6'b000110;\n 12'd1638 : mem_out_dec = 6'b000110;\n 12'd1639 : mem_out_dec = 6'b000111;\n 12'd1640 : mem_out_dec = 6'b000111;\n 12'd1641 : mem_out_dec = 6'b001000;\n 12'd1642 : mem_out_dec = 6'b001001;\n 12'd1643 : mem_out_dec = 6'b001001;\n 12'd1644 : mem_out_dec = 6'b001010;\n 12'd1645 : mem_out_dec = 6'b001011;\n 12'd1646 : mem_out_dec = 6'b001100;\n 12'd1647 : mem_out_dec = 6'b001101;\n 12'd1648 : mem_out_dec = 6'b001101;\n 12'd1649 : mem_out_dec = 6'b001101;\n 12'd1650 : mem_out_dec = 6'b001110;\n 12'd1651 : mem_out_dec = 6'b001110;\n 12'd1652 : mem_out_dec = 6'b001110;\n 12'd1653 : mem_out_dec = 6'b001111;\n 12'd1654 : mem_out_dec = 6'b010000;\n 12'd1655 : mem_out_dec = 6'b010000;\n 12'd1656 : mem_out_dec = 6'b010001;\n 12'd1657 : mem_out_dec = 6'b010001;\n 12'd1658 : mem_out_dec = 6'b010001;\n 12'd1659 : mem_out_dec = 6'b010010;\n 12'd1660 : mem_out_dec = 6'b010010;\n 12'd1661 : mem_out_dec = 6'b010011;\n 12'd1662 : mem_out_dec = 6'b010011;\n 12'd1663 : mem_out_dec = 6'b010100;\n 12'd1664 : mem_out_dec = 6'b111111;\n 12'd1665 : mem_out_dec = 6'b111111;\n 12'd1666 : mem_out_dec = 6'b111111;\n 12'd1667 : mem_out_dec = 6'b111111;\n 12'd1668 : mem_out_dec = 6'b111111;\n 12'd1669 : mem_out_dec = 6'b111111;\n 12'd1670 : mem_out_dec = 6'b111111;\n 12'd1671 : mem_out_dec = 6'b111111;\n 12'd1672 : mem_out_dec = 6'b111111;\n 12'd1673 : mem_out_dec = 6'b111111;\n 12'd1674 : mem_out_dec = 6'b111111;\n 12'd1675 : mem_out_dec = 6'b111111;\n 12'd1676 : mem_out_dec = 6'b111111;\n 12'd1677 : mem_out_dec = 6'b111111;\n 12'd1678 : mem_out_dec = 6'b111111;\n 12'd1679 : mem_out_dec = 6'b111111;\n 12'd1680 : mem_out_dec = 6'b111111;\n 12'd1681 : mem_out_dec = 6'b111111;\n 12'd1682 : mem_out_dec = 6'b111111;\n 12'd1683 : mem_out_dec = 6'b111111;\n 12'd1684 : mem_out_dec = 6'b111111;\n 12'd1685 : mem_out_dec = 6'b111111;\n 12'd1686 : mem_out_dec = 6'b111111;\n 12'd1687 : mem_out_dec = 6'b111111;\n 12'd1688 : mem_out_dec = 6'b111111;\n 12'd1689 : mem_out_dec = 6'b111111;\n 12'd1690 : mem_out_dec = 6'b111111;\n 12'd1691 : mem_out_dec = 6'b111111;\n 12'd1692 : mem_out_dec = 6'b111111;\n 12'd1693 : mem_out_dec = 6'b111111;\n 12'd1694 : mem_out_dec = 6'b111111;\n 12'd1695 : mem_out_dec = 6'b111111;\n 12'd1696 : mem_out_dec = 6'b000011;\n 12'd1697 : mem_out_dec = 6'b000011;\n 12'd1698 : mem_out_dec = 6'b000100;\n 12'd1699 : mem_out_dec = 6'b000100;\n 12'd1700 : mem_out_dec = 6'b000101;\n 12'd1701 : mem_out_dec = 6'b000101;\n 12'd1702 : mem_out_dec = 6'b000110;\n 12'd1703 : mem_out_dec = 6'b000111;\n 12'd1704 : mem_out_dec = 6'b000111;\n 12'd1705 : mem_out_dec = 6'b001000;\n 12'd1706 : mem_out_dec = 6'b001000;\n 12'd1707 : mem_out_dec = 6'b001001;\n 12'd1708 : mem_out_dec = 6'b001010;\n 12'd1709 : mem_out_dec = 6'b001011;\n 12'd1710 : mem_out_dec = 6'b001100;\n 12'd1711 : mem_out_dec = 6'b001100;\n 12'd1712 : mem_out_dec = 6'b001100;\n 12'd1713 : mem_out_dec = 6'b001101;\n 12'd1714 : mem_out_dec = 6'b001101;\n 12'd1715 : mem_out_dec = 6'b001110;\n 12'd1716 : mem_out_dec = 6'b001110;\n 12'd1717 : mem_out_dec = 6'b001111;\n 12'd1718 : mem_out_dec = 6'b001111;\n 12'd1719 : mem_out_dec = 6'b010000;\n 12'd1720 : mem_out_dec = 6'b010000;\n 12'd1721 : mem_out_dec = 6'b010000;\n 12'd1722 : mem_out_dec = 6'b010001;\n 12'd1723 : mem_out_dec = 6'b010001;\n 12'd1724 : mem_out_dec = 6'b010010;\n 12'd1725 : mem_out_dec = 6'b010010;\n 12'd1726 : mem_out_dec = 6'b010011;\n 12'd1727 : mem_out_dec = 6'b010011;\n 12'd1728 : mem_out_dec = 6'b111111;\n 12'd1729 : mem_out_dec = 6'b111111;\n 12'd1730 : mem_out_dec = 6'b111111;\n 12'd1731 : mem_out_dec = 6'b111111;\n 12'd1732 : mem_out_dec = 6'b111111;\n 12'd1733 : mem_out_dec = 6'b111111;\n 12'd1734 : mem_out_dec = 6'b111111;\n 12'd1735 : mem_out_dec = 6'b111111;\n 12'd1736 : mem_out_dec = 6'b111111;\n 12'd1737 : mem_out_dec = 6'b111111;\n 12'd1738 : mem_out_dec = 6'b111111;\n 12'd1739 : mem_out_dec = 6'b111111;\n 12'd1740 : mem_out_dec = 6'b111111;\n 12'd1741 : mem_out_dec = 6'b111111;\n 12'd1742 : mem_out_dec = 6'b111111;\n 12'd1743 : mem_out_dec = 6'b111111;\n 12'd1744 : mem_out_dec = 6'b111111;\n 12'd1745 : mem_out_dec = 6'b111111;\n 12'd1746 : mem_out_dec = 6'b111111;\n 12'd1747 : mem_out_dec = 6'b111111;\n 12'd1748 : mem_out_dec = 6'b111111;\n 12'd1749 : mem_out_dec = 6'b111111;\n 12'd1750 : mem_out_dec = 6'b111111;\n 12'd1751 : mem_out_dec = 6'b111111;\n 12'd1752 : mem_out_dec = 6'b111111;\n 12'd1753 : mem_out_dec = 6'b111111;\n 12'd1754 : mem_out_dec = 6'b111111;\n 12'd1755 : mem_out_dec = 6'b111111;\n 12'd1756 : mem_out_dec = 6'b111111;\n 12'd1757 : mem_out_dec = 6'b111111;\n 12'd1758 : mem_out_dec = 6'b111111;\n 12'd1759 : mem_out_dec = 6'b111111;\n 12'd1760 : mem_out_dec = 6'b111111;\n 12'd1761 : mem_out_dec = 6'b000011;\n 12'd1762 : mem_out_dec = 6'b000011;\n 12'd1763 : mem_out_dec = 6'b000100;\n 12'd1764 : mem_out_dec = 6'b000101;\n 12'd1765 : mem_out_dec = 6'b000101;\n 12'd1766 : mem_out_dec = 6'b000110;\n 12'd1767 : mem_out_dec = 6'b000111;\n 12'd1768 : mem_out_dec = 6'b000111;\n 12'd1769 : mem_out_dec = 6'b000111;\n 12'd1770 : mem_out_dec = 6'b001000;\n 12'd1771 : mem_out_dec = 6'b001001;\n 12'd1772 : mem_out_dec = 6'b001010;\n 12'd1773 : mem_out_dec = 6'b001011;\n 12'd1774 : mem_out_dec = 6'b001011;\n 12'd1775 : mem_out_dec = 6'b001100;\n 12'd1776 : mem_out_dec = 6'b001100;\n 12'd1777 : mem_out_dec = 6'b001101;\n 12'd1778 : mem_out_dec = 6'b001101;\n 12'd1779 : mem_out_dec = 6'b001101;\n 12'd1780 : mem_out_dec = 6'b001110;\n 12'd1781 : mem_out_dec = 6'b001111;\n 12'd1782 : mem_out_dec = 6'b001111;\n 12'd1783 : mem_out_dec = 6'b010000;\n 12'd1784 : mem_out_dec = 6'b010000;\n 12'd1785 : mem_out_dec = 6'b010000;\n 12'd1786 : mem_out_dec = 6'b010000;\n 12'd1787 : mem_out_dec = 6'b010001;\n 12'd1788 : mem_out_dec = 6'b010001;\n 12'd1789 : mem_out_dec = 6'b010010;\n 12'd1790 : mem_out_dec = 6'b010010;\n 12'd1791 : mem_out_dec = 6'b010011;\n 12'd1792 : mem_out_dec = 6'b111111;\n 12'd1793 : mem_out_dec = 6'b111111;\n 12'd1794 : mem_out_dec = 6'b111111;\n 12'd1795 : mem_out_dec = 6'b111111;\n 12'd1796 : mem_out_dec = 6'b111111;\n 12'd1797 : mem_out_dec = 6'b111111;\n 12'd1798 : mem_out_dec = 6'b111111;\n 12'd1799 : mem_out_dec = 6'b111111;\n 12'd1800 : mem_out_dec = 6'b111111;\n 12'd1801 : mem_out_dec = 6'b111111;\n 12'd1802 : mem_out_dec = 6'b111111;\n 12'd1803 : mem_out_dec = 6'b111111;\n 12'd1804 : mem_out_dec = 6'b111111;\n 12'd1805 : mem_out_dec = 6'b111111;\n 12'd1806 : mem_out_dec = 6'b111111;\n 12'd1807 : mem_out_dec = 6'b111111;\n 12'd1808 : mem_out_dec = 6'b111111;\n 12'd1809 : mem_out_dec = 6'b111111;\n 12'd1810 : mem_out_dec = 6'b111111;\n 12'd1811 : mem_out_dec = 6'b111111;\n 12'd1812 : mem_out_dec = 6'b111111;\n 12'd1813 : mem_out_dec = 6'b111111;\n 12'd1814 : mem_out_dec = 6'b111111;\n 12'd1815 : mem_out_dec = 6'b111111;\n 12'd1816 : mem_out_dec = 6'b111111;\n 12'd1817 : mem_out_dec = 6'b111111;\n 12'd1818 : mem_out_dec = 6'b111111;\n 12'd1819 : mem_out_dec = 6'b111111;\n 12'd1820 : mem_out_dec = 6'b111111;\n 12'd1821 : mem_out_dec = 6'b111111;\n 12'd1822 : mem_out_dec = 6'b111111;\n 12'd1823 : mem_out_dec = 6'b111111;\n 12'd1824 : mem_out_dec = 6'b111111;\n 12'd1825 : mem_out_dec = 6'b111111;\n 12'd1826 : mem_out_dec = 6'b000011;\n 12'd1827 : mem_out_dec = 6'b000100;\n 12'd1828 : mem_out_dec = 6'b000100;\n 12'd1829 : mem_out_dec = 6'b000101;\n 12'd1830 : mem_out_dec = 6'b000110;\n 12'd1831 : mem_out_dec = 6'b000110;\n 12'd1832 : mem_out_dec = 6'b000110;\n 12'd1833 : mem_out_dec = 6'b000111;\n 12'd1834 : mem_out_dec = 6'b001000;\n 12'd1835 : mem_out_dec = 6'b001001;\n 12'd1836 : mem_out_dec = 6'b001010;\n 12'd1837 : mem_out_dec = 6'b001010;\n 12'd1838 : mem_out_dec = 6'b001011;\n 12'd1839 : mem_out_dec = 6'b001100;\n 12'd1840 : mem_out_dec = 6'b001100;\n 12'd1841 : mem_out_dec = 6'b001100;\n 12'd1842 : mem_out_dec = 6'b001101;\n 12'd1843 : mem_out_dec = 6'b001101;\n 12'd1844 : mem_out_dec = 6'b001110;\n 12'd1845 : mem_out_dec = 6'b001110;\n 12'd1846 : mem_out_dec = 6'b001111;\n 12'd1847 : mem_out_dec = 6'b010000;\n 12'd1848 : mem_out_dec = 6'b001111;\n 12'd1849 : mem_out_dec = 6'b001111;\n 12'd1850 : mem_out_dec = 6'b010000;\n 12'd1851 : mem_out_dec = 6'b010000;\n 12'd1852 : mem_out_dec = 6'b010001;\n 12'd1853 : mem_out_dec = 6'b010001;\n 12'd1854 : mem_out_dec = 6'b010010;\n 12'd1855 : mem_out_dec = 6'b010010;\n 12'd1856 : mem_out_dec = 6'b111111;\n 12'd1857 : mem_out_dec = 6'b111111;\n 12'd1858 : mem_out_dec = 6'b111111;\n 12'd1859 : mem_out_dec = 6'b111111;\n 12'd1860 : mem_out_dec = 6'b111111;\n 12'd1861 : mem_out_dec = 6'b111111;\n 12'd1862 : mem_out_dec = 6'b111111;\n 12'd1863 : mem_out_dec = 6'b111111;\n 12'd1864 : mem_out_dec = 6'b111111;\n 12'd1865 : mem_out_dec = 6'b111111;\n 12'd1866 : mem_out_dec = 6'b111111;\n 12'd1867 : mem_out_dec = 6'b111111;\n 12'd1868 : mem_out_dec = 6'b111111;\n 12'd1869 : mem_out_dec = 6'b111111;\n 12'd1870 : mem_out_dec = 6'b111111;\n 12'd1871 : mem_out_dec = 6'b111111;\n 12'd1872 : mem_out_dec = 6'b111111;\n 12'd1873 : mem_out_dec = 6'b111111;\n 12'd1874 : mem_out_dec = 6'b111111;\n 12'd1875 : mem_out_dec = 6'b111111;\n 12'd1876 : mem_out_dec = 6'b111111;\n 12'd1877 : mem_out_dec = 6'b111111;\n 12'd1878 : mem_out_dec = 6'b111111;\n 12'd1879 : mem_out_dec = 6'b111111;\n 12'd1880 : mem_out_dec = 6'b111111;\n 12'd1881 : mem_out_dec = 6'b111111;\n 12'd1882 : mem_out_dec = 6'b111111;\n 12'd1883 : mem_out_dec = 6'b111111;\n 12'd1884 : mem_out_dec = 6'b111111;\n 12'd1885 : mem_out_dec = 6'b111111;\n 12'd1886 : mem_out_dec = 6'b111111;\n 12'd1887 : mem_out_dec = 6'b111111;\n 12'd1888 : mem_out_dec = 6'b111111;\n 12'd1889 : mem_out_dec = 6'b111111;\n 12'd1890 : mem_out_dec = 6'b111111;\n 12'd1891 : mem_out_dec = 6'b000100;\n 12'd1892 : mem_out_dec = 6'b000100;\n 12'd1893 : mem_out_dec = 6'b000101;\n 12'd1894 : mem_out_dec = 6'b000101;\n 12'd1895 : mem_out_dec = 6'b000110;\n 12'd1896 : mem_out_dec = 6'b000110;\n 12'd1897 : mem_out_dec = 6'b000111;\n 12'd1898 : mem_out_dec = 6'b001000;\n 12'd1899 : mem_out_dec = 6'b001001;\n 12'd1900 : mem_out_dec = 6'b001001;\n 12'd1901 : mem_out_dec = 6'b001010;\n 12'd1902 : mem_out_dec = 6'b001011;\n 12'd1903 : mem_out_dec = 6'b001100;\n 12'd1904 : mem_out_dec = 6'b001100;\n 12'd1905 : mem_out_dec = 6'b001100;\n 12'd1906 : mem_out_dec = 6'b001100;\n 12'd1907 : mem_out_dec = 6'b001101;\n 12'd1908 : mem_out_dec = 6'b001110;\n 12'd1909 : mem_out_dec = 6'b001110;\n 12'd1910 : mem_out_dec = 6'b001111;\n 12'd1911 : mem_out_dec = 6'b001111;\n 12'd1912 : mem_out_dec = 6'b001111;\n 12'd1913 : mem_out_dec = 6'b001111;\n 12'd1914 : mem_out_dec = 6'b001111;\n 12'd1915 : mem_out_dec = 6'b010000;\n 12'd1916 : mem_out_dec = 6'b010000;\n 12'd1917 : mem_out_dec = 6'b010001;\n 12'd1918 : mem_out_dec = 6'b010001;\n 12'd1919 : mem_out_dec = 6'b010010;\n 12'd1920 : mem_out_dec = 6'b111111;\n 12'd1921 : mem_out_dec = 6'b111111;\n 12'd1922 : mem_out_dec = 6'b111111;\n 12'd1923 : mem_out_dec = 6'b111111;\n 12'd1924 : mem_out_dec = 6'b111111;\n 12'd1925 : mem_out_dec = 6'b111111;\n 12'd1926 : mem_out_dec = 6'b111111;\n 12'd1927 : mem_out_dec = 6'b111111;\n 12'd1928 : mem_out_dec = 6'b111111;\n 12'd1929 : mem_out_dec = 6'b111111;\n 12'd1930 : mem_out_dec = 6'b111111;\n 12'd1931 : mem_out_dec = 6'b111111;\n 12'd1932 : mem_out_dec = 6'b111111;\n 12'd1933 : mem_out_dec = 6'b111111;\n 12'd1934 : mem_out_dec = 6'b111111;\n 12'd1935 : mem_out_dec = 6'b111111;\n 12'd1936 : mem_out_dec = 6'b111111;\n 12'd1937 : mem_out_dec = 6'b111111;\n 12'd1938 : mem_out_dec = 6'b111111;\n 12'd1939 : mem_out_dec = 6'b111111;\n 12'd1940 : mem_out_dec = 6'b111111;\n 12'd1941 : mem_out_dec = 6'b111111;\n 12'd1942 : mem_out_dec = 6'b111111;\n 12'd1943 : mem_out_dec = 6'b111111;\n 12'd1944 : mem_out_dec = 6'b111111;\n 12'd1945 : mem_out_dec = 6'b111111;\n 12'd1946 : mem_out_dec = 6'b111111;\n 12'd1947 : mem_out_dec = 6'b111111;\n 12'd1948 : mem_out_dec = 6'b111111;\n 12'd1949 : mem_out_dec = 6'b111111;\n 12'd1950 : mem_out_dec = 6'b111111;\n 12'd1951 : mem_out_dec = 6'b111111;\n 12'd1952 : mem_out_dec = 6'b111111;\n 12'd1953 : mem_out_dec = 6'b111111;\n 12'd1954 : mem_out_dec = 6'b111111;\n 12'd1955 : mem_out_dec = 6'b111111;\n 12'd1956 : mem_out_dec = 6'b000100;\n 12'd1957 : mem_out_dec = 6'b000101;\n 12'd1958 : mem_out_dec = 6'b000101;\n 12'd1959 : mem_out_dec = 6'b000110;\n 12'd1960 : mem_out_dec = 6'b000110;\n 12'd1961 : mem_out_dec = 6'b000111;\n 12'd1962 : mem_out_dec = 6'b001000;\n 12'd1963 : mem_out_dec = 6'b001000;\n 12'd1964 : mem_out_dec = 6'b001001;\n 12'd1965 : mem_out_dec = 6'b001010;\n 12'd1966 : mem_out_dec = 6'b001011;\n 12'd1967 : mem_out_dec = 6'b001011;\n 12'd1968 : mem_out_dec = 6'b001011;\n 12'd1969 : mem_out_dec = 6'b001100;\n 12'd1970 : mem_out_dec = 6'b001100;\n 12'd1971 : mem_out_dec = 6'b001101;\n 12'd1972 : mem_out_dec = 6'b001101;\n 12'd1973 : mem_out_dec = 6'b001110;\n 12'd1974 : mem_out_dec = 6'b001111;\n 12'd1975 : mem_out_dec = 6'b001111;\n 12'd1976 : mem_out_dec = 6'b001110;\n 12'd1977 : mem_out_dec = 6'b001110;\n 12'd1978 : mem_out_dec = 6'b001111;\n 12'd1979 : mem_out_dec = 6'b001111;\n 12'd1980 : mem_out_dec = 6'b010000;\n 12'd1981 : mem_out_dec = 6'b010000;\n 12'd1982 : mem_out_dec = 6'b010001;\n 12'd1983 : mem_out_dec = 6'b010001;\n 12'd1984 : mem_out_dec = 6'b111111;\n 12'd1985 : mem_out_dec = 6'b111111;\n 12'd1986 : mem_out_dec = 6'b111111;\n 12'd1987 : mem_out_dec = 6'b111111;\n 12'd1988 : mem_out_dec = 6'b111111;\n 12'd1989 : mem_out_dec = 6'b111111;\n 12'd1990 : mem_out_dec = 6'b111111;\n 12'd1991 : mem_out_dec = 6'b111111;\n 12'd1992 : mem_out_dec = 6'b111111;\n 12'd1993 : mem_out_dec = 6'b111111;\n 12'd1994 : mem_out_dec = 6'b111111;\n 12'd1995 : mem_out_dec = 6'b111111;\n 12'd1996 : mem_out_dec = 6'b111111;\n 12'd1997 : mem_out_dec = 6'b111111;\n 12'd1998 : mem_out_dec = 6'b111111;\n 12'd1999 : mem_out_dec = 6'b111111;\n 12'd2000 : mem_out_dec = 6'b111111;\n 12'd2001 : mem_out_dec = 6'b111111;\n 12'd2002 : mem_out_dec = 6'b111111;\n 12'd2003 : mem_out_dec = 6'b111111;\n 12'd2004 : mem_out_dec = 6'b111111;\n 12'd2005 : mem_out_dec = 6'b111111;\n 12'd2006 : mem_out_dec = 6'b111111;\n 12'd2007 : mem_out_dec = 6'b111111;\n 12'd2008 : mem_out_dec = 6'b111111;\n 12'd2009 : mem_out_dec = 6'b111111;\n 12'd2010 : mem_out_dec = 6'b111111;\n 12'd2011 : mem_out_dec = 6'b111111;\n 12'd2012 : mem_out_dec = 6'b111111;\n 12'd2013 : mem_out_dec = 6'b111111;\n 12'd2014 : mem_out_dec = 6'b111111;\n 12'd2015 : mem_out_dec = 6'b111111;\n 12'd2016 : mem_out_dec = 6'b111111;\n 12'd2017 : mem_out_dec = 6'b111111;\n 12'd2018 : mem_out_dec = 6'b111111;\n 12'd2019 : mem_out_dec = 6'b111111;\n 12'd2020 : mem_out_dec = 6'b111111;\n 12'd2021 : mem_out_dec = 6'b000100;\n 12'd2022 : mem_out_dec = 6'b000101;\n 12'd2023 : mem_out_dec = 6'b000110;\n 12'd2024 : mem_out_dec = 6'b000110;\n 12'd2025 : mem_out_dec = 6'b000111;\n 12'd2026 : mem_out_dec = 6'b000111;\n 12'd2027 : mem_out_dec = 6'b001000;\n 12'd2028 : mem_out_dec = 6'b001001;\n 12'd2029 : mem_out_dec = 6'b001010;\n 12'd2030 : mem_out_dec = 6'b001010;\n 12'd2031 : mem_out_dec = 6'b001011;\n 12'd2032 : mem_out_dec = 6'b001011;\n 12'd2033 : mem_out_dec = 6'b001011;\n 12'd2034 : mem_out_dec = 6'b001100;\n 12'd2035 : mem_out_dec = 6'b001101;\n 12'd2036 : mem_out_dec = 6'b001101;\n 12'd2037 : mem_out_dec = 6'b001110;\n 12'd2038 : mem_out_dec = 6'b001110;\n 12'd2039 : mem_out_dec = 6'b001110;\n 12'd2040 : mem_out_dec = 6'b001101;\n 12'd2041 : mem_out_dec = 6'b001110;\n 12'd2042 : mem_out_dec = 6'b001110;\n 12'd2043 : mem_out_dec = 6'b001111;\n 12'd2044 : mem_out_dec = 6'b001111;\n 12'd2045 : mem_out_dec = 6'b010000;\n 12'd2046 : mem_out_dec = 6'b010000;\n 12'd2047 : mem_out_dec = 6'b010001;\n 12'd2048 : mem_out_dec = 6'b111111;\n 12'd2049 : mem_out_dec = 6'b111111;\n 12'd2050 : mem_out_dec = 6'b111111;\n 12'd2051 : mem_out_dec = 6'b111111;\n 12'd2052 : mem_out_dec = 6'b111111;\n 12'd2053 : mem_out_dec = 6'b111111;\n 12'd2054 : mem_out_dec = 6'b111111;\n 12'd2055 : mem_out_dec = 6'b111111;\n 12'd2056 : mem_out_dec = 6'b111111;\n 12'd2057 : mem_out_dec = 6'b111111;\n 12'd2058 : mem_out_dec = 6'b111111;\n 12'd2059 : mem_out_dec = 6'b111111;\n 12'd2060 : mem_out_dec = 6'b111111;\n 12'd2061 : mem_out_dec = 6'b111111;\n 12'd2062 : mem_out_dec = 6'b111111;\n 12'd2063 : mem_out_dec = 6'b111111;\n 12'd2064 : mem_out_dec = 6'b111111;\n 12'd2065 : mem_out_dec = 6'b111111;\n 12'd2066 : mem_out_dec = 6'b111111;\n 12'd2067 : mem_out_dec = 6'b111111;\n 12'd2068 : mem_out_dec = 6'b111111;\n 12'd2069 : mem_out_dec = 6'b111111;\n 12'd2070 : mem_out_dec = 6'b111111;\n 12'd2071 : mem_out_dec = 6'b111111;\n 12'd2072 : mem_out_dec = 6'b111111;\n 12'd2073 : mem_out_dec = 6'b111111;\n 12'd2074 : mem_out_dec = 6'b111111;\n 12'd2075 : mem_out_dec = 6'b111111;\n 12'd2076 : mem_out_dec = 6'b111111;\n 12'd2077 : mem_out_dec = 6'b111111;\n 12'd2078 : mem_out_dec = 6'b111111;\n 12'd2079 : mem_out_dec = 6'b111111;\n 12'd2080 : mem_out_dec = 6'b111111;\n 12'd2081 : mem_out_dec = 6'b111111;\n 12'd2082 : mem_out_dec = 6'b111111;\n 12'd2083 : mem_out_dec = 6'b111111;\n 12'd2084 : mem_out_dec = 6'b111111;\n 12'd2085 : mem_out_dec = 6'b111111;\n 12'd2086 : mem_out_dec = 6'b000100;\n 12'd2087 : mem_out_dec = 6'b000101;\n 12'd2088 : mem_out_dec = 6'b000101;\n 12'd2089 : mem_out_dec = 6'b000110;\n 12'd2090 : mem_out_dec = 6'b000110;\n 12'd2091 : mem_out_dec = 6'b000111;\n 12'd2092 : mem_out_dec = 6'b001000;\n 12'd2093 : mem_out_dec = 6'b001001;\n 12'd2094 : mem_out_dec = 6'b001001;\n 12'd2095 : mem_out_dec = 6'b001010;\n 12'd2096 : mem_out_dec = 6'b001010;\n 12'd2097 : mem_out_dec = 6'b001011;\n 12'd2098 : mem_out_dec = 6'b001011;\n 12'd2099 : mem_out_dec = 6'b001100;\n 12'd2100 : mem_out_dec = 6'b001100;\n 12'd2101 : mem_out_dec = 6'b001100;\n 12'd2102 : mem_out_dec = 6'b001100;\n 12'd2103 : mem_out_dec = 6'b001101;\n 12'd2104 : mem_out_dec = 6'b001100;\n 12'd2105 : mem_out_dec = 6'b001100;\n 12'd2106 : mem_out_dec = 6'b001101;\n 12'd2107 : mem_out_dec = 6'b001101;\n 12'd2108 : mem_out_dec = 6'b001110;\n 12'd2109 : mem_out_dec = 6'b001111;\n 12'd2110 : mem_out_dec = 6'b010000;\n 12'd2111 : mem_out_dec = 6'b010000;\n 12'd2112 : mem_out_dec = 6'b111111;\n 12'd2113 : mem_out_dec = 6'b111111;\n 12'd2114 : mem_out_dec = 6'b111111;\n 12'd2115 : mem_out_dec = 6'b111111;\n 12'd2116 : mem_out_dec = 6'b111111;\n 12'd2117 : mem_out_dec = 6'b111111;\n 12'd2118 : mem_out_dec = 6'b111111;\n 12'd2119 : mem_out_dec = 6'b111111;\n 12'd2120 : mem_out_dec = 6'b111111;\n 12'd2121 : mem_out_dec = 6'b111111;\n 12'd2122 : mem_out_dec = 6'b111111;\n 12'd2123 : mem_out_dec = 6'b111111;\n 12'd2124 : mem_out_dec = 6'b111111;\n 12'd2125 : mem_out_dec = 6'b111111;\n 12'd2126 : mem_out_dec = 6'b111111;\n 12'd2127 : mem_out_dec = 6'b111111;\n 12'd2128 : mem_out_dec = 6'b111111;\n 12'd2129 : mem_out_dec = 6'b111111;\n 12'd2130 : mem_out_dec = 6'b111111;\n 12'd2131 : mem_out_dec = 6'b111111;\n 12'd2132 : mem_out_dec = 6'b111111;\n 12'd2133 : mem_out_dec = 6'b111111;\n 12'd2134 : mem_out_dec = 6'b111111;\n 12'd2135 : mem_out_dec = 6'b111111;\n 12'd2136 : mem_out_dec = 6'b111111;\n 12'd2137 : mem_out_dec = 6'b111111;\n 12'd2138 : mem_out_dec = 6'b111111;\n 12'd2139 : mem_out_dec = 6'b111111;\n 12'd2140 : mem_out_dec = 6'b111111;\n 12'd2141 : mem_out_dec = 6'b111111;\n 12'd2142 : mem_out_dec = 6'b111111;\n 12'd2143 : mem_out_dec = 6'b111111;\n 12'd2144 : mem_out_dec = 6'b111111;\n 12'd2145 : mem_out_dec = 6'b111111;\n 12'd2146 : mem_out_dec = 6'b111111;\n 12'd2147 : mem_out_dec = 6'b111111;\n 12'd2148 : mem_out_dec = 6'b111111;\n 12'd2149 : mem_out_dec = 6'b111111;\n 12'd2150 : mem_out_dec = 6'b111111;\n 12'd2151 : mem_out_dec = 6'b000100;\n 12'd2152 : mem_out_dec = 6'b000100;\n 12'd2153 : mem_out_dec = 6'b000101;\n 12'd2154 : mem_out_dec = 6'b000110;\n 12'd2155 : mem_out_dec = 6'b000111;\n 12'd2156 : mem_out_dec = 6'b000111;\n 12'd2157 : mem_out_dec = 6'b001000;\n 12'd2158 : mem_out_dec = 6'b001001;\n 12'd2159 : mem_out_dec = 6'b001001;\n 12'd2160 : mem_out_dec = 6'b001010;\n 12'd2161 : mem_out_dec = 6'b001010;\n 12'd2162 : mem_out_dec = 6'b001011;\n 12'd2163 : mem_out_dec = 6'b001011;\n 12'd2164 : mem_out_dec = 6'b001011;\n 12'd2165 : mem_out_dec = 6'b001011;\n 12'd2166 : mem_out_dec = 6'b001011;\n 12'd2167 : mem_out_dec = 6'b001100;\n 12'd2168 : mem_out_dec = 6'b001011;\n 12'd2169 : mem_out_dec = 6'b001011;\n 12'd2170 : mem_out_dec = 6'b001100;\n 12'd2171 : mem_out_dec = 6'b001101;\n 12'd2172 : mem_out_dec = 6'b001110;\n 12'd2173 : mem_out_dec = 6'b001110;\n 12'd2174 : mem_out_dec = 6'b001111;\n 12'd2175 : mem_out_dec = 6'b010000;\n 12'd2176 : mem_out_dec = 6'b111111;\n 12'd2177 : mem_out_dec = 6'b111111;\n 12'd2178 : mem_out_dec = 6'b111111;\n 12'd2179 : mem_out_dec = 6'b111111;\n 12'd2180 : mem_out_dec = 6'b111111;\n 12'd2181 : mem_out_dec = 6'b111111;\n 12'd2182 : mem_out_dec = 6'b111111;\n 12'd2183 : mem_out_dec = 6'b111111;\n 12'd2184 : mem_out_dec = 6'b111111;\n 12'd2185 : mem_out_dec = 6'b111111;\n 12'd2186 : mem_out_dec = 6'b111111;\n 12'd2187 : mem_out_dec = 6'b111111;\n 12'd2188 : mem_out_dec = 6'b111111;\n 12'd2189 : mem_out_dec = 6'b111111;\n 12'd2190 : mem_out_dec = 6'b111111;\n 12'd2191 : mem_out_dec = 6'b111111;\n 12'd2192 : mem_out_dec = 6'b111111;\n 12'd2193 : mem_out_dec = 6'b111111;\n 12'd2194 : mem_out_dec = 6'b111111;\n 12'd2195 : mem_out_dec = 6'b111111;\n 12'd2196 : mem_out_dec = 6'b111111;\n 12'd2197 : mem_out_dec = 6'b111111;\n 12'd2198 : mem_out_dec = 6'b111111;\n 12'd2199 : mem_out_dec = 6'b111111;\n 12'd2200 : mem_out_dec = 6'b111111;\n 12'd2201 : mem_out_dec = 6'b111111;\n 12'd2202 : mem_out_dec = 6'b111111;\n 12'd2203 : mem_out_dec = 6'b111111;\n 12'd2204 : mem_out_dec = 6'b111111;\n 12'd2205 : mem_out_dec = 6'b111111;\n 12'd2206 : mem_out_dec = 6'b111111;\n 12'd2207 : mem_out_dec = 6'b111111;\n 12'd2208 : mem_out_dec = 6'b111111;\n 12'd2209 : mem_out_dec = 6'b111111;\n 12'd2210 : mem_out_dec = 6'b111111;\n 12'd2211 : mem_out_dec = 6'b111111;\n 12'd2212 : mem_out_dec = 6'b111111;\n 12'd2213 : mem_out_dec = 6'b111111;\n 12'd2214 : mem_out_dec = 6'b111111;\n 12'd2215 : mem_out_dec = 6'b111111;\n 12'd2216 : mem_out_dec = 6'b000100;\n 12'd2217 : mem_out_dec = 6'b000101;\n 12'd2218 : mem_out_dec = 6'b000101;\n 12'd2219 : mem_out_dec = 6'b000110;\n 12'd2220 : mem_out_dec = 6'b000111;\n 12'd2221 : mem_out_dec = 6'b000111;\n 12'd2222 : mem_out_dec = 6'b001000;\n 12'd2223 : mem_out_dec = 6'b001001;\n 12'd2224 : mem_out_dec = 6'b001001;\n 12'd2225 : mem_out_dec = 6'b001010;\n 12'd2226 : mem_out_dec = 6'b001010;\n 12'd2227 : mem_out_dec = 6'b001010;\n 12'd2228 : mem_out_dec = 6'b001010;\n 12'd2229 : mem_out_dec = 6'b001010;\n 12'd2230 : mem_out_dec = 6'b001010;\n 12'd2231 : mem_out_dec = 6'b001010;\n 12'd2232 : mem_out_dec = 6'b001010;\n 12'd2233 : mem_out_dec = 6'b001011;\n 12'd2234 : mem_out_dec = 6'b001100;\n 12'd2235 : mem_out_dec = 6'b001100;\n 12'd2236 : mem_out_dec = 6'b001101;\n 12'd2237 : mem_out_dec = 6'b001110;\n 12'd2238 : mem_out_dec = 6'b001111;\n 12'd2239 : mem_out_dec = 6'b010000;\n 12'd2240 : mem_out_dec = 6'b111111;\n 12'd2241 : mem_out_dec = 6'b111111;\n 12'd2242 : mem_out_dec = 6'b111111;\n 12'd2243 : mem_out_dec = 6'b111111;\n 12'd2244 : mem_out_dec = 6'b111111;\n 12'd2245 : mem_out_dec = 6'b111111;\n 12'd2246 : mem_out_dec = 6'b111111;\n 12'd2247 : mem_out_dec = 6'b111111;\n 12'd2248 : mem_out_dec = 6'b111111;\n 12'd2249 : mem_out_dec = 6'b111111;\n 12'd2250 : mem_out_dec = 6'b111111;\n 12'd2251 : mem_out_dec = 6'b111111;\n 12'd2252 : mem_out_dec = 6'b111111;\n 12'd2253 : mem_out_dec = 6'b111111;\n 12'd2254 : mem_out_dec = 6'b111111;\n 12'd2255 : mem_out_dec = 6'b111111;\n 12'd2256 : mem_out_dec = 6'b111111;\n 12'd2257 : mem_out_dec = 6'b111111;\n 12'd2258 : mem_out_dec = 6'b111111;\n 12'd2259 : mem_out_dec = 6'b111111;\n 12'd2260 : mem_out_dec = 6'b111111;\n 12'd2261 : mem_out_dec = 6'b111111;\n 12'd2262 : mem_out_dec = 6'b111111;\n 12'd2263 : mem_out_dec = 6'b111111;\n 12'd2264 : mem_out_dec = 6'b111111;\n 12'd2265 : mem_out_dec = 6'b111111;\n 12'd2266 : mem_out_dec = 6'b111111;\n 12'd2267 : mem_out_dec = 6'b111111;\n 12'd2268 : mem_out_dec = 6'b111111;\n 12'd2269 : mem_out_dec = 6'b111111;\n 12'd2270 : mem_out_dec = 6'b111111;\n 12'd2271 : mem_out_dec = 6'b111111;\n 12'd2272 : mem_out_dec = 6'b111111;\n 12'd2273 : mem_out_dec = 6'b111111;\n 12'd2274 : mem_out_dec = 6'b111111;\n 12'd2275 : mem_out_dec = 6'b111111;\n 12'd2276 : mem_out_dec = 6'b111111;\n 12'd2277 : mem_out_dec = 6'b111111;\n 12'd2278 : mem_out_dec = 6'b111111;\n 12'd2279 : mem_out_dec = 6'b111111;\n 12'd2280 : mem_out_dec = 6'b111111;\n 12'd2281 : mem_out_dec = 6'b000100;\n 12'd2282 : mem_out_dec = 6'b000101;\n 12'd2283 : mem_out_dec = 6'b000101;\n 12'd2284 : mem_out_dec = 6'b000110;\n 12'd2285 : mem_out_dec = 6'b000111;\n 12'd2286 : mem_out_dec = 6'b001000;\n 12'd2287 : mem_out_dec = 6'b001001;\n 12'd2288 : mem_out_dec = 6'b001001;\n 12'd2289 : mem_out_dec = 6'b001001;\n 12'd2290 : mem_out_dec = 6'b001001;\n 12'd2291 : mem_out_dec = 6'b001001;\n 12'd2292 : mem_out_dec = 6'b001001;\n 12'd2293 : mem_out_dec = 6'b001001;\n 12'd2294 : mem_out_dec = 6'b001001;\n 12'd2295 : mem_out_dec = 6'b001001;\n 12'd2296 : mem_out_dec = 6'b001010;\n 12'd2297 : mem_out_dec = 6'b001010;\n 12'd2298 : mem_out_dec = 6'b001011;\n 12'd2299 : mem_out_dec = 6'b001100;\n 12'd2300 : mem_out_dec = 6'b001101;\n 12'd2301 : mem_out_dec = 6'b001110;\n 12'd2302 : mem_out_dec = 6'b001110;\n 12'd2303 : mem_out_dec = 6'b001111;\n 12'd2304 : mem_out_dec = 6'b111111;\n 12'd2305 : mem_out_dec = 6'b111111;\n 12'd2306 : mem_out_dec = 6'b111111;\n 12'd2307 : mem_out_dec = 6'b111111;\n 12'd2308 : mem_out_dec = 6'b111111;\n 12'd2309 : mem_out_dec = 6'b111111;\n 12'd2310 : mem_out_dec = 6'b111111;\n 12'd2311 : mem_out_dec = 6'b111111;\n 12'd2312 : mem_out_dec = 6'b111111;\n 12'd2313 : mem_out_dec = 6'b111111;\n 12'd2314 : mem_out_dec = 6'b111111;\n 12'd2315 : mem_out_dec = 6'b111111;\n 12'd2316 : mem_out_dec = 6'b111111;\n 12'd2317 : mem_out_dec = 6'b111111;\n 12'd2318 : mem_out_dec = 6'b111111;\n 12'd2319 : mem_out_dec = 6'b111111;\n 12'd2320 : mem_out_dec = 6'b111111;\n 12'd2321 : mem_out_dec = 6'b111111;\n 12'd2322 : mem_out_dec = 6'b111111;\n 12'd2323 : mem_out_dec = 6'b111111;\n 12'd2324 : mem_out_dec = 6'b111111;\n 12'd2325 : mem_out_dec = 6'b111111;\n 12'd2326 : mem_out_dec = 6'b111111;\n 12'd2327 : mem_out_dec = 6'b111111;\n 12'd2328 : mem_out_dec = 6'b111111;\n 12'd2329 : mem_out_dec = 6'b111111;\n 12'd2330 : mem_out_dec = 6'b111111;\n 12'd2331 : mem_out_dec = 6'b111111;\n 12'd2332 : mem_out_dec = 6'b111111;\n 12'd2333 : mem_out_dec = 6'b111111;\n 12'd2334 : mem_out_dec = 6'b111111;\n 12'd2335 : mem_out_dec = 6'b111111;\n 12'd2336 : mem_out_dec = 6'b111111;\n 12'd2337 : mem_out_dec = 6'b111111;\n 12'd2338 : mem_out_dec = 6'b111111;\n 12'd2339 : mem_out_dec = 6'b111111;\n 12'd2340 : mem_out_dec = 6'b111111;\n 12'd2341 : mem_out_dec = 6'b111111;\n 12'd2342 : mem_out_dec = 6'b111111;\n 12'd2343 : mem_out_dec = 6'b111111;\n 12'd2344 : mem_out_dec = 6'b111111;\n 12'd2345 : mem_out_dec = 6'b111111;\n 12'd2346 : mem_out_dec = 6'b000100;\n 12'd2347 : mem_out_dec = 6'b000101;\n 12'd2348 : mem_out_dec = 6'b000110;\n 12'd2349 : mem_out_dec = 6'b000111;\n 12'd2350 : mem_out_dec = 6'b000111;\n 12'd2351 : mem_out_dec = 6'b001000;\n 12'd2352 : mem_out_dec = 6'b001000;\n 12'd2353 : mem_out_dec = 6'b001000;\n 12'd2354 : mem_out_dec = 6'b001000;\n 12'd2355 : mem_out_dec = 6'b001000;\n 12'd2356 : mem_out_dec = 6'b001000;\n 12'd2357 : mem_out_dec = 6'b001000;\n 12'd2358 : mem_out_dec = 6'b001000;\n 12'd2359 : mem_out_dec = 6'b001001;\n 12'd2360 : mem_out_dec = 6'b001001;\n 12'd2361 : mem_out_dec = 6'b001010;\n 12'd2362 : mem_out_dec = 6'b001011;\n 12'd2363 : mem_out_dec = 6'b001100;\n 12'd2364 : mem_out_dec = 6'b001100;\n 12'd2365 : mem_out_dec = 6'b001101;\n 12'd2366 : mem_out_dec = 6'b001110;\n 12'd2367 : mem_out_dec = 6'b001111;\n 12'd2368 : mem_out_dec = 6'b111111;\n 12'd2369 : mem_out_dec = 6'b111111;\n 12'd2370 : mem_out_dec = 6'b111111;\n 12'd2371 : mem_out_dec = 6'b111111;\n 12'd2372 : mem_out_dec = 6'b111111;\n 12'd2373 : mem_out_dec = 6'b111111;\n 12'd2374 : mem_out_dec = 6'b111111;\n 12'd2375 : mem_out_dec = 6'b111111;\n 12'd2376 : mem_out_dec = 6'b111111;\n 12'd2377 : mem_out_dec = 6'b111111;\n 12'd2378 : mem_out_dec = 6'b111111;\n 12'd2379 : mem_out_dec = 6'b111111;\n 12'd2380 : mem_out_dec = 6'b111111;\n 12'd2381 : mem_out_dec = 6'b111111;\n 12'd2382 : mem_out_dec = 6'b111111;\n 12'd2383 : mem_out_dec = 6'b111111;\n 12'd2384 : mem_out_dec = 6'b111111;\n 12'd2385 : mem_out_dec = 6'b111111;\n 12'd2386 : mem_out_dec = 6'b111111;\n 12'd2387 : mem_out_dec = 6'b111111;\n 12'd2388 : mem_out_dec = 6'b111111;\n 12'd2389 : mem_out_dec = 6'b111111;\n 12'd2390 : mem_out_dec = 6'b111111;\n 12'd2391 : mem_out_dec = 6'b111111;\n 12'd2392 : mem_out_dec = 6'b111111;\n 12'd2393 : mem_out_dec = 6'b111111;\n 12'd2394 : mem_out_dec = 6'b111111;\n 12'd2395 : mem_out_dec = 6'b111111;\n 12'd2396 : mem_out_dec = 6'b111111;\n 12'd2397 : mem_out_dec = 6'b111111;\n 12'd2398 : mem_out_dec = 6'b111111;\n 12'd2399 : mem_out_dec = 6'b111111;\n 12'd2400 : mem_out_dec = 6'b111111;\n 12'd2401 : mem_out_dec = 6'b111111;\n 12'd2402 : mem_out_dec = 6'b111111;\n 12'd2403 : mem_out_dec = 6'b111111;\n 12'd2404 : mem_out_dec = 6'b111111;\n 12'd2405 : mem_out_dec = 6'b111111;\n 12'd2406 : mem_out_dec = 6'b111111;\n 12'd2407 : mem_out_dec = 6'b111111;\n 12'd2408 : mem_out_dec = 6'b111111;\n 12'd2409 : mem_out_dec = 6'b111111;\n 12'd2410 : mem_out_dec = 6'b111111;\n 12'd2411 : mem_out_dec = 6'b000101;\n 12'd2412 : mem_out_dec = 6'b000101;\n 12'd2413 : mem_out_dec = 6'b000110;\n 12'd2414 : mem_out_dec = 6'b000111;\n 12'd2415 : mem_out_dec = 6'b001000;\n 12'd2416 : mem_out_dec = 6'b000111;\n 12'd2417 : mem_out_dec = 6'b000111;\n 12'd2418 : mem_out_dec = 6'b000111;\n 12'd2419 : mem_out_dec = 6'b000111;\n 12'd2420 : mem_out_dec = 6'b000111;\n 12'd2421 : mem_out_dec = 6'b000111;\n 12'd2422 : mem_out_dec = 6'b001000;\n 12'd2423 : mem_out_dec = 6'b001001;\n 12'd2424 : mem_out_dec = 6'b001001;\n 12'd2425 : mem_out_dec = 6'b001010;\n 12'd2426 : mem_out_dec = 6'b001010;\n 12'd2427 : mem_out_dec = 6'b001011;\n 12'd2428 : mem_out_dec = 6'b001100;\n 12'd2429 : mem_out_dec = 6'b001101;\n 12'd2430 : mem_out_dec = 6'b001101;\n 12'd2431 : mem_out_dec = 6'b001110;\n 12'd2432 : mem_out_dec = 6'b111111;\n 12'd2433 : mem_out_dec = 6'b111111;\n 12'd2434 : mem_out_dec = 6'b111111;\n 12'd2435 : mem_out_dec = 6'b111111;\n 12'd2436 : mem_out_dec = 6'b111111;\n 12'd2437 : mem_out_dec = 6'b111111;\n 12'd2438 : mem_out_dec = 6'b111111;\n 12'd2439 : mem_out_dec = 6'b111111;\n 12'd2440 : mem_out_dec = 6'b111111;\n 12'd2441 : mem_out_dec = 6'b111111;\n 12'd2442 : mem_out_dec = 6'b111111;\n 12'd2443 : mem_out_dec = 6'b111111;\n 12'd2444 : mem_out_dec = 6'b111111;\n 12'd2445 : mem_out_dec = 6'b111111;\n 12'd2446 : mem_out_dec = 6'b111111;\n 12'd2447 : mem_out_dec = 6'b111111;\n 12'd2448 : mem_out_dec = 6'b111111;\n 12'd2449 : mem_out_dec = 6'b111111;\n 12'd2450 : mem_out_dec = 6'b111111;\n 12'd2451 : mem_out_dec = 6'b111111;\n 12'd2452 : mem_out_dec = 6'b111111;\n 12'd2453 : mem_out_dec = 6'b111111;\n 12'd2454 : mem_out_dec = 6'b111111;\n 12'd2455 : mem_out_dec = 6'b111111;\n 12'd2456 : mem_out_dec = 6'b111111;\n 12'd2457 : mem_out_dec = 6'b111111;\n 12'd2458 : mem_out_dec = 6'b111111;\n 12'd2459 : mem_out_dec = 6'b111111;\n 12'd2460 : mem_out_dec = 6'b111111;\n 12'd2461 : mem_out_dec = 6'b111111;\n 12'd2462 : mem_out_dec = 6'b111111;\n 12'd2463 : mem_out_dec = 6'b111111;\n 12'd2464 : mem_out_dec = 6'b111111;\n 12'd2465 : mem_out_dec = 6'b111111;\n 12'd2466 : mem_out_dec = 6'b111111;\n 12'd2467 : mem_out_dec = 6'b111111;\n 12'd2468 : mem_out_dec = 6'b111111;\n 12'd2469 : mem_out_dec = 6'b111111;\n 12'd2470 : mem_out_dec = 6'b111111;\n 12'd2471 : mem_out_dec = 6'b111111;\n 12'd2472 : mem_out_dec = 6'b111111;\n 12'd2473 : mem_out_dec = 6'b111111;\n 12'd2474 : mem_out_dec = 6'b111111;\n 12'd2475 : mem_out_dec = 6'b111111;\n 12'd2476 : mem_out_dec = 6'b000101;\n 12'd2477 : mem_out_dec = 6'b000110;\n 12'd2478 : mem_out_dec = 6'b000111;\n 12'd2479 : mem_out_dec = 6'b000111;\n 12'd2480 : mem_out_dec = 6'b000110;\n 12'd2481 : mem_out_dec = 6'b000110;\n 12'd2482 : mem_out_dec = 6'b000110;\n 12'd2483 : mem_out_dec = 6'b000110;\n 12'd2484 : mem_out_dec = 6'b000110;\n 12'd2485 : mem_out_dec = 6'b000111;\n 12'd2486 : mem_out_dec = 6'b000111;\n 12'd2487 : mem_out_dec = 6'b001000;\n 12'd2488 : mem_out_dec = 6'b001001;\n 12'd2489 : mem_out_dec = 6'b001001;\n 12'd2490 : mem_out_dec = 6'b001010;\n 12'd2491 : mem_out_dec = 6'b001011;\n 12'd2492 : mem_out_dec = 6'b001011;\n 12'd2493 : mem_out_dec = 6'b001100;\n 12'd2494 : mem_out_dec = 6'b001101;\n 12'd2495 : mem_out_dec = 6'b001110;\n 12'd2496 : mem_out_dec = 6'b111111;\n 12'd2497 : mem_out_dec = 6'b111111;\n 12'd2498 : mem_out_dec = 6'b111111;\n 12'd2499 : mem_out_dec = 6'b111111;\n 12'd2500 : mem_out_dec = 6'b111111;\n 12'd2501 : mem_out_dec = 6'b111111;\n 12'd2502 : mem_out_dec = 6'b111111;\n 12'd2503 : mem_out_dec = 6'b111111;\n 12'd2504 : mem_out_dec = 6'b111111;\n 12'd2505 : mem_out_dec = 6'b111111;\n 12'd2506 : mem_out_dec = 6'b111111;\n 12'd2507 : mem_out_dec = 6'b111111;\n 12'd2508 : mem_out_dec = 6'b111111;\n 12'd2509 : mem_out_dec = 6'b111111;\n 12'd2510 : mem_out_dec = 6'b111111;\n 12'd2511 : mem_out_dec = 6'b111111;\n 12'd2512 : mem_out_dec = 6'b111111;\n 12'd2513 : mem_out_dec = 6'b111111;\n 12'd2514 : mem_out_dec = 6'b111111;\n 12'd2515 : mem_out_dec = 6'b111111;\n 12'd2516 : mem_out_dec = 6'b111111;\n 12'd2517 : mem_out_dec = 6'b111111;\n 12'd2518 : mem_out_dec = 6'b111111;\n 12'd2519 : mem_out_dec = 6'b111111;\n 12'd2520 : mem_out_dec = 6'b111111;\n 12'd2521 : mem_out_dec = 6'b111111;\n 12'd2522 : mem_out_dec = 6'b111111;\n 12'd2523 : mem_out_dec = 6'b111111;\n 12'd2524 : mem_out_dec = 6'b111111;\n 12'd2525 : mem_out_dec = 6'b111111;\n 12'd2526 : mem_out_dec = 6'b111111;\n 12'd2527 : mem_out_dec = 6'b111111;\n 12'd2528 : mem_out_dec = 6'b111111;\n 12'd2529 : mem_out_dec = 6'b111111;\n 12'd2530 : mem_out_dec = 6'b111111;\n 12'd2531 : mem_out_dec = 6'b111111;\n 12'd2532 : mem_out_dec = 6'b111111;\n 12'd2533 : mem_out_dec = 6'b111111;\n 12'd2534 : mem_out_dec = 6'b111111;\n 12'd2535 : mem_out_dec = 6'b111111;\n 12'd2536 : mem_out_dec = 6'b111111;\n 12'd2537 : mem_out_dec = 6'b111111;\n 12'd2538 : mem_out_dec = 6'b111111;\n 12'd2539 : mem_out_dec = 6'b111111;\n 12'd2540 : mem_out_dec = 6'b111111;\n 12'd2541 : mem_out_dec = 6'b000101;\n 12'd2542 : mem_out_dec = 6'b000110;\n 12'd2543 : mem_out_dec = 6'b000110;\n 12'd2544 : mem_out_dec = 6'b000110;\n 12'd2545 : mem_out_dec = 6'b000110;\n 12'd2546 : mem_out_dec = 6'b000101;\n 12'd2547 : mem_out_dec = 6'b000101;\n 12'd2548 : mem_out_dec = 6'b000110;\n 12'd2549 : mem_out_dec = 6'b000111;\n 12'd2550 : mem_out_dec = 6'b000111;\n 12'd2551 : mem_out_dec = 6'b001000;\n 12'd2552 : mem_out_dec = 6'b001000;\n 12'd2553 : mem_out_dec = 6'b001001;\n 12'd2554 : mem_out_dec = 6'b001010;\n 12'd2555 : mem_out_dec = 6'b001010;\n 12'd2556 : mem_out_dec = 6'b001011;\n 12'd2557 : mem_out_dec = 6'b001100;\n 12'd2558 : mem_out_dec = 6'b001101;\n 12'd2559 : mem_out_dec = 6'b001101;\n 12'd2560 : mem_out_dec = 6'b111111;\n 12'd2561 : mem_out_dec = 6'b111111;\n 12'd2562 : mem_out_dec = 6'b111111;\n 12'd2563 : mem_out_dec = 6'b111111;\n 12'd2564 : mem_out_dec = 6'b111111;\n 12'd2565 : mem_out_dec = 6'b111111;\n 12'd2566 : mem_out_dec = 6'b111111;\n 12'd2567 : mem_out_dec = 6'b111111;\n 12'd2568 : mem_out_dec = 6'b111111;\n 12'd2569 : mem_out_dec = 6'b111111;\n 12'd2570 : mem_out_dec = 6'b111111;\n 12'd2571 : mem_out_dec = 6'b111111;\n 12'd2572 : mem_out_dec = 6'b111111;\n 12'd2573 : mem_out_dec = 6'b111111;\n 12'd2574 : mem_out_dec = 6'b111111;\n 12'd2575 : mem_out_dec = 6'b111111;\n 12'd2576 : mem_out_dec = 6'b111111;\n 12'd2577 : mem_out_dec = 6'b111111;\n 12'd2578 : mem_out_dec = 6'b111111;\n 12'd2579 : mem_out_dec = 6'b111111;\n 12'd2580 : mem_out_dec = 6'b111111;\n 12'd2581 : mem_out_dec = 6'b111111;\n 12'd2582 : mem_out_dec = 6'b111111;\n 12'd2583 : mem_out_dec = 6'b111111;\n 12'd2584 : mem_out_dec = 6'b111111;\n 12'd2585 : mem_out_dec = 6'b111111;\n 12'd2586 : mem_out_dec = 6'b111111;\n 12'd2587 : mem_out_dec = 6'b111111;\n 12'd2588 : mem_out_dec = 6'b111111;\n 12'd2589 : mem_out_dec = 6'b111111;\n 12'd2590 : mem_out_dec = 6'b111111;\n 12'd2591 : mem_out_dec = 6'b111111;\n 12'd2592 : mem_out_dec = 6'b111111;\n 12'd2593 : mem_out_dec = 6'b111111;\n 12'd2594 : mem_out_dec = 6'b111111;\n 12'd2595 : mem_out_dec = 6'b111111;\n 12'd2596 : mem_out_dec = 6'b111111;\n 12'd2597 : mem_out_dec = 6'b111111;\n 12'd2598 : mem_out_dec = 6'b111111;\n 12'd2599 : mem_out_dec = 6'b111111;\n 12'd2600 : mem_out_dec = 6'b111111;\n 12'd2601 : mem_out_dec = 6'b111111;\n 12'd2602 : mem_out_dec = 6'b111111;\n 12'd2603 : mem_out_dec = 6'b111111;\n 12'd2604 : mem_out_dec = 6'b111111;\n 12'd2605 : mem_out_dec = 6'b111111;\n 12'd2606 : mem_out_dec = 6'b000100;\n 12'd2607 : mem_out_dec = 6'b000101;\n 12'd2608 : mem_out_dec = 6'b000100;\n 12'd2609 : mem_out_dec = 6'b000100;\n 12'd2610 : mem_out_dec = 6'b000100;\n 12'd2611 : mem_out_dec = 6'b000101;\n 12'd2612 : mem_out_dec = 6'b000101;\n 12'd2613 : mem_out_dec = 6'b000110;\n 12'd2614 : mem_out_dec = 6'b000111;\n 12'd2615 : mem_out_dec = 6'b000111;\n 12'd2616 : mem_out_dec = 6'b000111;\n 12'd2617 : mem_out_dec = 6'b001000;\n 12'd2618 : mem_out_dec = 6'b001001;\n 12'd2619 : mem_out_dec = 6'b001010;\n 12'd2620 : mem_out_dec = 6'b001010;\n 12'd2621 : mem_out_dec = 6'b001011;\n 12'd2622 : mem_out_dec = 6'b001100;\n 12'd2623 : mem_out_dec = 6'b001101;\n 12'd2624 : mem_out_dec = 6'b111111;\n 12'd2625 : mem_out_dec = 6'b111111;\n 12'd2626 : mem_out_dec = 6'b111111;\n 12'd2627 : mem_out_dec = 6'b111111;\n 12'd2628 : mem_out_dec = 6'b111111;\n 12'd2629 : mem_out_dec = 6'b111111;\n 12'd2630 : mem_out_dec = 6'b111111;\n 12'd2631 : mem_out_dec = 6'b111111;\n 12'd2632 : mem_out_dec = 6'b111111;\n 12'd2633 : mem_out_dec = 6'b111111;\n 12'd2634 : mem_out_dec = 6'b111111;\n 12'd2635 : mem_out_dec = 6'b111111;\n 12'd2636 : mem_out_dec = 6'b111111;\n 12'd2637 : mem_out_dec = 6'b111111;\n 12'd2638 : mem_out_dec = 6'b111111;\n 12'd2639 : mem_out_dec = 6'b111111;\n 12'd2640 : mem_out_dec = 6'b111111;\n 12'd2641 : mem_out_dec = 6'b111111;\n 12'd2642 : mem_out_dec = 6'b111111;\n 12'd2643 : mem_out_dec = 6'b111111;\n 12'd2644 : mem_out_dec = 6'b111111;\n 12'd2645 : mem_out_dec = 6'b111111;\n 12'd2646 : mem_out_dec = 6'b111111;\n 12'd2647 : mem_out_dec = 6'b111111;\n 12'd2648 : mem_out_dec = 6'b111111;\n 12'd2649 : mem_out_dec = 6'b111111;\n 12'd2650 : mem_out_dec = 6'b111111;\n 12'd2651 : mem_out_dec = 6'b111111;\n 12'd2652 : mem_out_dec = 6'b111111;\n 12'd2653 : mem_out_dec = 6'b111111;\n 12'd2654 : mem_out_dec = 6'b111111;\n 12'd2655 : mem_out_dec = 6'b111111;\n 12'd2656 : mem_out_dec = 6'b111111;\n 12'd2657 : mem_out_dec = 6'b111111;\n 12'd2658 : mem_out_dec = 6'b111111;\n 12'd2659 : mem_out_dec = 6'b111111;\n 12'd2660 : mem_out_dec = 6'b111111;\n 12'd2661 : mem_out_dec = 6'b111111;\n 12'd2662 : mem_out_dec = 6'b111111;\n 12'd2663 : mem_out_dec = 6'b111111;\n 12'd2664 : mem_out_dec = 6'b111111;\n 12'd2665 : mem_out_dec = 6'b111111;\n 12'd2666 : mem_out_dec = 6'b111111;\n 12'd2667 : mem_out_dec = 6'b111111;\n 12'd2668 : mem_out_dec = 6'b111111;\n 12'd2669 : mem_out_dec = 6'b111111;\n 12'd2670 : mem_out_dec = 6'b111111;\n 12'd2671 : mem_out_dec = 6'b000100;\n 12'd2672 : mem_out_dec = 6'b000011;\n 12'd2673 : mem_out_dec = 6'b000011;\n 12'd2674 : mem_out_dec = 6'b000100;\n 12'd2675 : mem_out_dec = 6'b000100;\n 12'd2676 : mem_out_dec = 6'b000101;\n 12'd2677 : mem_out_dec = 6'b000110;\n 12'd2678 : mem_out_dec = 6'b000110;\n 12'd2679 : mem_out_dec = 6'b000111;\n 12'd2680 : mem_out_dec = 6'b000111;\n 12'd2681 : mem_out_dec = 6'b001000;\n 12'd2682 : mem_out_dec = 6'b001001;\n 12'd2683 : mem_out_dec = 6'b001001;\n 12'd2684 : mem_out_dec = 6'b001010;\n 12'd2685 : mem_out_dec = 6'b001011;\n 12'd2686 : mem_out_dec = 6'b001100;\n 12'd2687 : mem_out_dec = 6'b001100;\n 12'd2688 : mem_out_dec = 6'b111111;\n 12'd2689 : mem_out_dec = 6'b111111;\n 12'd2690 : mem_out_dec = 6'b111111;\n 12'd2691 : mem_out_dec = 6'b111111;\n 12'd2692 : mem_out_dec = 6'b111111;\n 12'd2693 : mem_out_dec = 6'b111111;\n 12'd2694 : mem_out_dec = 6'b111111;\n 12'd2695 : mem_out_dec = 6'b111111;\n 12'd2696 : mem_out_dec = 6'b111111;\n 12'd2697 : mem_out_dec = 6'b111111;\n 12'd2698 : mem_out_dec = 6'b111111;\n 12'd2699 : mem_out_dec = 6'b111111;\n 12'd2700 : mem_out_dec = 6'b111111;\n 12'd2701 : mem_out_dec = 6'b111111;\n 12'd2702 : mem_out_dec = 6'b111111;\n 12'd2703 : mem_out_dec = 6'b111111;\n 12'd2704 : mem_out_dec = 6'b111111;\n 12'd2705 : mem_out_dec = 6'b111111;\n 12'd2706 : mem_out_dec = 6'b111111;\n 12'd2707 : mem_out_dec = 6'b111111;\n 12'd2708 : mem_out_dec = 6'b111111;\n 12'd2709 : mem_out_dec = 6'b111111;\n 12'd2710 : mem_out_dec = 6'b111111;\n 12'd2711 : mem_out_dec = 6'b111111;\n 12'd2712 : mem_out_dec = 6'b111111;\n 12'd2713 : mem_out_dec = 6'b111111;\n 12'd2714 : mem_out_dec = 6'b111111;\n 12'd2715 : mem_out_dec = 6'b111111;\n 12'd2716 : mem_out_dec = 6'b111111;\n 12'd2717 : mem_out_dec = 6'b111111;\n 12'd2718 : mem_out_dec = 6'b111111;\n 12'd2719 : mem_out_dec = 6'b111111;\n 12'd2720 : mem_out_dec = 6'b111111;\n 12'd2721 : mem_out_dec = 6'b111111;\n 12'd2722 : mem_out_dec = 6'b111111;\n 12'd2723 : mem_out_dec = 6'b111111;\n 12'd2724 : mem_out_dec = 6'b111111;\n 12'd2725 : mem_out_dec = 6'b111111;\n 12'd2726 : mem_out_dec = 6'b111111;\n 12'd2727 : mem_out_dec = 6'b111111;\n 12'd2728 : mem_out_dec = 6'b111111;\n 12'd2729 : mem_out_dec = 6'b111111;\n 12'd2730 : mem_out_dec = 6'b111111;\n 12'd2731 : mem_out_dec = 6'b111111;\n 12'd2732 : mem_out_dec = 6'b111111;\n 12'd2733 : mem_out_dec = 6'b111111;\n 12'd2734 : mem_out_dec = 6'b111111;\n 12'd2735 : mem_out_dec = 6'b111111;\n 12'd2736 : mem_out_dec = 6'b000011;\n 12'd2737 : mem_out_dec = 6'b000011;\n 12'd2738 : mem_out_dec = 6'b000100;\n 12'd2739 : mem_out_dec = 6'b000100;\n 12'd2740 : mem_out_dec = 6'b000101;\n 12'd2741 : mem_out_dec = 6'b000101;\n 12'd2742 : mem_out_dec = 6'b000110;\n 12'd2743 : mem_out_dec = 6'b000111;\n 12'd2744 : mem_out_dec = 6'b000111;\n 12'd2745 : mem_out_dec = 6'b001000;\n 12'd2746 : mem_out_dec = 6'b001000;\n 12'd2747 : mem_out_dec = 6'b001001;\n 12'd2748 : mem_out_dec = 6'b001010;\n 12'd2749 : mem_out_dec = 6'b001011;\n 12'd2750 : mem_out_dec = 6'b001011;\n 12'd2751 : mem_out_dec = 6'b001100;\n 12'd2752 : mem_out_dec = 6'b111111;\n 12'd2753 : mem_out_dec = 6'b111111;\n 12'd2754 : mem_out_dec = 6'b111111;\n 12'd2755 : mem_out_dec = 6'b111111;\n 12'd2756 : mem_out_dec = 6'b111111;\n 12'd2757 : mem_out_dec = 6'b111111;\n 12'd2758 : mem_out_dec = 6'b111111;\n 12'd2759 : mem_out_dec = 6'b111111;\n 12'd2760 : mem_out_dec = 6'b111111;\n 12'd2761 : mem_out_dec = 6'b111111;\n 12'd2762 : mem_out_dec = 6'b111111;\n 12'd2763 : mem_out_dec = 6'b111111;\n 12'd2764 : mem_out_dec = 6'b111111;\n 12'd2765 : mem_out_dec = 6'b111111;\n 12'd2766 : mem_out_dec = 6'b111111;\n 12'd2767 : mem_out_dec = 6'b111111;\n 12'd2768 : mem_out_dec = 6'b111111;\n 12'd2769 : mem_out_dec = 6'b111111;\n 12'd2770 : mem_out_dec = 6'b111111;\n 12'd2771 : mem_out_dec = 6'b111111;\n 12'd2772 : mem_out_dec = 6'b111111;\n 12'd2773 : mem_out_dec = 6'b111111;\n 12'd2774 : mem_out_dec = 6'b111111;\n 12'd2775 : mem_out_dec = 6'b111111;\n 12'd2776 : mem_out_dec = 6'b111111;\n 12'd2777 : mem_out_dec = 6'b111111;\n 12'd2778 : mem_out_dec = 6'b111111;\n 12'd2779 : mem_out_dec = 6'b111111;\n 12'd2780 : mem_out_dec = 6'b111111;\n 12'd2781 : mem_out_dec = 6'b111111;\n 12'd2782 : mem_out_dec = 6'b111111;\n 12'd2783 : mem_out_dec = 6'b111111;\n 12'd2784 : mem_out_dec = 6'b111111;\n 12'd2785 : mem_out_dec = 6'b111111;\n 12'd2786 : mem_out_dec = 6'b111111;\n 12'd2787 : mem_out_dec = 6'b111111;\n 12'd2788 : mem_out_dec = 6'b111111;\n 12'd2789 : mem_out_dec = 6'b111111;\n 12'd2790 : mem_out_dec = 6'b111111;\n 12'd2791 : mem_out_dec = 6'b111111;\n 12'd2792 : mem_out_dec = 6'b111111;\n 12'd2793 : mem_out_dec = 6'b111111;\n 12'd2794 : mem_out_dec = 6'b111111;\n 12'd2795 : mem_out_dec = 6'b111111;\n 12'd2796 : mem_out_dec = 6'b111111;\n 12'd2797 : mem_out_dec = 6'b111111;\n 12'd2798 : mem_out_dec = 6'b111111;\n 12'd2799 : mem_out_dec = 6'b111111;\n 12'd2800 : mem_out_dec = 6'b111111;\n 12'd2801 : mem_out_dec = 6'b000011;\n 12'd2802 : mem_out_dec = 6'b000011;\n 12'd2803 : mem_out_dec = 6'b000100;\n 12'd2804 : mem_out_dec = 6'b000101;\n 12'd2805 : mem_out_dec = 6'b000101;\n 12'd2806 : mem_out_dec = 6'b000110;\n 12'd2807 : mem_out_dec = 6'b000111;\n 12'd2808 : mem_out_dec = 6'b000111;\n 12'd2809 : mem_out_dec = 6'b000111;\n 12'd2810 : mem_out_dec = 6'b001000;\n 12'd2811 : mem_out_dec = 6'b001001;\n 12'd2812 : mem_out_dec = 6'b001010;\n 12'd2813 : mem_out_dec = 6'b001010;\n 12'd2814 : mem_out_dec = 6'b001011;\n 12'd2815 : mem_out_dec = 6'b001100;\n 12'd2816 : mem_out_dec = 6'b111111;\n 12'd2817 : mem_out_dec = 6'b111111;\n 12'd2818 : mem_out_dec = 6'b111111;\n 12'd2819 : mem_out_dec = 6'b111111;\n 12'd2820 : mem_out_dec = 6'b111111;\n 12'd2821 : mem_out_dec = 6'b111111;\n 12'd2822 : mem_out_dec = 6'b111111;\n 12'd2823 : mem_out_dec = 6'b111111;\n 12'd2824 : mem_out_dec = 6'b111111;\n 12'd2825 : mem_out_dec = 6'b111111;\n 12'd2826 : mem_out_dec = 6'b111111;\n 12'd2827 : mem_out_dec = 6'b111111;\n 12'd2828 : mem_out_dec = 6'b111111;\n 12'd2829 : mem_out_dec = 6'b111111;\n 12'd2830 : mem_out_dec = 6'b111111;\n 12'd2831 : mem_out_dec = 6'b111111;\n 12'd2832 : mem_out_dec = 6'b111111;\n 12'd2833 : mem_out_dec = 6'b111111;\n 12'd2834 : mem_out_dec = 6'b111111;\n 12'd2835 : mem_out_dec = 6'b111111;\n 12'd2836 : mem_out_dec = 6'b111111;\n 12'd2837 : mem_out_dec = 6'b111111;\n 12'd2838 : mem_out_dec = 6'b111111;\n 12'd2839 : mem_out_dec = 6'b111111;\n 12'd2840 : mem_out_dec = 6'b111111;\n 12'd2841 : mem_out_dec = 6'b111111;\n 12'd2842 : mem_out_dec = 6'b111111;\n 12'd2843 : mem_out_dec = 6'b111111;\n 12'd2844 : mem_out_dec = 6'b111111;\n 12'd2845 : mem_out_dec = 6'b111111;\n 12'd2846 : mem_out_dec = 6'b111111;\n 12'd2847 : mem_out_dec = 6'b111111;\n 12'd2848 : mem_out_dec = 6'b111111;\n 12'd2849 : mem_out_dec = 6'b111111;\n 12'd2850 : mem_out_dec = 6'b111111;\n 12'd2851 : mem_out_dec = 6'b111111;\n 12'd2852 : mem_out_dec = 6'b111111;\n 12'd2853 : mem_out_dec = 6'b111111;\n 12'd2854 : mem_out_dec = 6'b111111;\n 12'd2855 : mem_out_dec = 6'b111111;\n 12'd2856 : mem_out_dec = 6'b111111;\n 12'd2857 : mem_out_dec = 6'b111111;\n 12'd2858 : mem_out_dec = 6'b111111;\n 12'd2859 : mem_out_dec = 6'b111111;\n 12'd2860 : mem_out_dec = 6'b111111;\n 12'd2861 : mem_out_dec = 6'b111111;\n 12'd2862 : mem_out_dec = 6'b111111;\n 12'd2863 : mem_out_dec = 6'b111111;\n 12'd2864 : mem_out_dec = 6'b111111;\n 12'd2865 : mem_out_dec = 6'b111111;\n 12'd2866 : mem_out_dec = 6'b000011;\n 12'd2867 : mem_out_dec = 6'b000100;\n 12'd2868 : mem_out_dec = 6'b000100;\n 12'd2869 : mem_out_dec = 6'b000101;\n 12'd2870 : mem_out_dec = 6'b000110;\n 12'd2871 : mem_out_dec = 6'b000110;\n 12'd2872 : mem_out_dec = 6'b000110;\n 12'd2873 : mem_out_dec = 6'b000111;\n 12'd2874 : mem_out_dec = 6'b001000;\n 12'd2875 : mem_out_dec = 6'b001001;\n 12'd2876 : mem_out_dec = 6'b001001;\n 12'd2877 : mem_out_dec = 6'b001010;\n 12'd2878 : mem_out_dec = 6'b001011;\n 12'd2879 : mem_out_dec = 6'b001100;\n 12'd2880 : mem_out_dec = 6'b111111;\n 12'd2881 : mem_out_dec = 6'b111111;\n 12'd2882 : mem_out_dec = 6'b111111;\n 12'd2883 : mem_out_dec = 6'b111111;\n 12'd2884 : mem_out_dec = 6'b111111;\n 12'd2885 : mem_out_dec = 6'b111111;\n 12'd2886 : mem_out_dec = 6'b111111;\n 12'd2887 : mem_out_dec = 6'b111111;\n 12'd2888 : mem_out_dec = 6'b111111;\n 12'd2889 : mem_out_dec = 6'b111111;\n 12'd2890 : mem_out_dec = 6'b111111;\n 12'd2891 : mem_out_dec = 6'b111111;\n 12'd2892 : mem_out_dec = 6'b111111;\n 12'd2893 : mem_out_dec = 6'b111111;\n 12'd2894 : mem_out_dec = 6'b111111;\n 12'd2895 : mem_out_dec = 6'b111111;\n 12'd2896 : mem_out_dec = 6'b111111;\n 12'd2897 : mem_out_dec = 6'b111111;\n 12'd2898 : mem_out_dec = 6'b111111;\n 12'd2899 : mem_out_dec = 6'b111111;\n 12'd2900 : mem_out_dec = 6'b111111;\n 12'd2901 : mem_out_dec = 6'b111111;\n 12'd2902 : mem_out_dec = 6'b111111;\n 12'd2903 : mem_out_dec = 6'b111111;\n 12'd2904 : mem_out_dec = 6'b111111;\n 12'd2905 : mem_out_dec = 6'b111111;\n 12'd2906 : mem_out_dec = 6'b111111;\n 12'd2907 : mem_out_dec = 6'b111111;\n 12'd2908 : mem_out_dec = 6'b111111;\n 12'd2909 : mem_out_dec = 6'b111111;\n 12'd2910 : mem_out_dec = 6'b111111;\n 12'd2911 : mem_out_dec = 6'b111111;\n 12'd2912 : mem_out_dec = 6'b111111;\n 12'd2913 : mem_out_dec = 6'b111111;\n 12'd2914 : mem_out_dec = 6'b111111;\n 12'd2915 : mem_out_dec = 6'b111111;\n 12'd2916 : mem_out_dec = 6'b111111;\n 12'd2917 : mem_out_dec = 6'b111111;\n 12'd2918 : mem_out_dec = 6'b111111;\n 12'd2919 : mem_out_dec = 6'b111111;\n 12'd2920 : mem_out_dec = 6'b111111;\n 12'd2921 : mem_out_dec = 6'b111111;\n 12'd2922 : mem_out_dec = 6'b111111;\n 12'd2923 : mem_out_dec = 6'b111111;\n 12'd2924 : mem_out_dec = 6'b111111;\n 12'd2925 : mem_out_dec = 6'b111111;\n 12'd2926 : mem_out_dec = 6'b111111;\n 12'd2927 : mem_out_dec = 6'b111111;\n 12'd2928 : mem_out_dec = 6'b111111;\n 12'd2929 : mem_out_dec = 6'b111111;\n 12'd2930 : mem_out_dec = 6'b111111;\n 12'd2931 : mem_out_dec = 6'b000100;\n 12'd2932 : mem_out_dec = 6'b000100;\n 12'd2933 : mem_out_dec = 6'b000101;\n 12'd2934 : mem_out_dec = 6'b000101;\n 12'd2935 : mem_out_dec = 6'b000110;\n 12'd2936 : mem_out_dec = 6'b000110;\n 12'd2937 : mem_out_dec = 6'b000111;\n 12'd2938 : mem_out_dec = 6'b001000;\n 12'd2939 : mem_out_dec = 6'b001000;\n 12'd2940 : mem_out_dec = 6'b001001;\n 12'd2941 : mem_out_dec = 6'b001010;\n 12'd2942 : mem_out_dec = 6'b001011;\n 12'd2943 : mem_out_dec = 6'b001011;\n 12'd2944 : mem_out_dec = 6'b111111;\n 12'd2945 : mem_out_dec = 6'b111111;\n 12'd2946 : mem_out_dec = 6'b111111;\n 12'd2947 : mem_out_dec = 6'b111111;\n 12'd2948 : mem_out_dec = 6'b111111;\n 12'd2949 : mem_out_dec = 6'b111111;\n 12'd2950 : mem_out_dec = 6'b111111;\n 12'd2951 : mem_out_dec = 6'b111111;\n 12'd2952 : mem_out_dec = 6'b111111;\n 12'd2953 : mem_out_dec = 6'b111111;\n 12'd2954 : mem_out_dec = 6'b111111;\n 12'd2955 : mem_out_dec = 6'b111111;\n 12'd2956 : mem_out_dec = 6'b111111;\n 12'd2957 : mem_out_dec = 6'b111111;\n 12'd2958 : mem_out_dec = 6'b111111;\n 12'd2959 : mem_out_dec = 6'b111111;\n 12'd2960 : mem_out_dec = 6'b111111;\n 12'd2961 : mem_out_dec = 6'b111111;\n 12'd2962 : mem_out_dec = 6'b111111;\n 12'd2963 : mem_out_dec = 6'b111111;\n 12'd2964 : mem_out_dec = 6'b111111;\n 12'd2965 : mem_out_dec = 6'b111111;\n 12'd2966 : mem_out_dec = 6'b111111;\n 12'd2967 : mem_out_dec = 6'b111111;\n 12'd2968 : mem_out_dec = 6'b111111;\n 12'd2969 : mem_out_dec = 6'b111111;\n 12'd2970 : mem_out_dec = 6'b111111;\n 12'd2971 : mem_out_dec = 6'b111111;\n 12'd2972 : mem_out_dec = 6'b111111;\n 12'd2973 : mem_out_dec = 6'b111111;\n 12'd2974 : mem_out_dec = 6'b111111;\n 12'd2975 : mem_out_dec = 6'b111111;\n 12'd2976 : mem_out_dec = 6'b111111;\n 12'd2977 : mem_out_dec = 6'b111111;\n 12'd2978 : mem_out_dec = 6'b111111;\n 12'd2979 : mem_out_dec = 6'b111111;\n 12'd2980 : mem_out_dec = 6'b111111;\n 12'd2981 : mem_out_dec = 6'b111111;\n 12'd2982 : mem_out_dec = 6'b111111;\n 12'd2983 : mem_out_dec = 6'b111111;\n 12'd2984 : mem_out_dec = 6'b111111;\n 12'd2985 : mem_out_dec = 6'b111111;\n 12'd2986 : mem_out_dec = 6'b111111;\n 12'd2987 : mem_out_dec = 6'b111111;\n 12'd2988 : mem_out_dec = 6'b111111;\n 12'd2989 : mem_out_dec = 6'b111111;\n 12'd2990 : mem_out_dec = 6'b111111;\n 12'd2991 : mem_out_dec = 6'b111111;\n 12'd2992 : mem_out_dec = 6'b111111;\n 12'd2993 : mem_out_dec = 6'b111111;\n 12'd2994 : mem_out_dec = 6'b111111;\n 12'd2995 : mem_out_dec = 6'b111111;\n 12'd2996 : mem_out_dec = 6'b000100;\n 12'd2997 : mem_out_dec = 6'b000101;\n 12'd2998 : mem_out_dec = 6'b000101;\n 12'd2999 : mem_out_dec = 6'b000110;\n 12'd3000 : mem_out_dec = 6'b000110;\n 12'd3001 : mem_out_dec = 6'b000111;\n 12'd3002 : mem_out_dec = 6'b000111;\n 12'd3003 : mem_out_dec = 6'b001000;\n 12'd3004 : mem_out_dec = 6'b001001;\n 12'd3005 : mem_out_dec = 6'b001010;\n 12'd3006 : mem_out_dec = 6'b001010;\n 12'd3007 : mem_out_dec = 6'b001011;\n 12'd3008 : mem_out_dec = 6'b111111;\n 12'd3009 : mem_out_dec = 6'b111111;\n 12'd3010 : mem_out_dec = 6'b111111;\n 12'd3011 : mem_out_dec = 6'b111111;\n 12'd3012 : mem_out_dec = 6'b111111;\n 12'd3013 : mem_out_dec = 6'b111111;\n 12'd3014 : mem_out_dec = 6'b111111;\n 12'd3015 : mem_out_dec = 6'b111111;\n 12'd3016 : mem_out_dec = 6'b111111;\n 12'd3017 : mem_out_dec = 6'b111111;\n 12'd3018 : mem_out_dec = 6'b111111;\n 12'd3019 : mem_out_dec = 6'b111111;\n 12'd3020 : mem_out_dec = 6'b111111;\n 12'd3021 : mem_out_dec = 6'b111111;\n 12'd3022 : mem_out_dec = 6'b111111;\n 12'd3023 : mem_out_dec = 6'b111111;\n 12'd3024 : mem_out_dec = 6'b111111;\n 12'd3025 : mem_out_dec = 6'b111111;\n 12'd3026 : mem_out_dec = 6'b111111;\n 12'd3027 : mem_out_dec = 6'b111111;\n 12'd3028 : mem_out_dec = 6'b111111;\n 12'd3029 : mem_out_dec = 6'b111111;\n 12'd3030 : mem_out_dec = 6'b111111;\n 12'd3031 : mem_out_dec = 6'b111111;\n 12'd3032 : mem_out_dec = 6'b111111;\n 12'd3033 : mem_out_dec = 6'b111111;\n 12'd3034 : mem_out_dec = 6'b111111;\n 12'd3035 : mem_out_dec = 6'b111111;\n 12'd3036 : mem_out_dec = 6'b111111;\n 12'd3037 : mem_out_dec = 6'b111111;\n 12'd3038 : mem_out_dec = 6'b111111;\n 12'd3039 : mem_out_dec = 6'b111111;\n 12'd3040 : mem_out_dec = 6'b111111;\n 12'd3041 : mem_out_dec = 6'b111111;\n 12'd3042 : mem_out_dec = 6'b111111;\n 12'd3043 : mem_out_dec = 6'b111111;\n 12'd3044 : mem_out_dec = 6'b111111;\n 12'd3045 : mem_out_dec = 6'b111111;\n 12'd3046 : mem_out_dec = 6'b111111;\n 12'd3047 : mem_out_dec = 6'b111111;\n 12'd3048 : mem_out_dec = 6'b111111;\n 12'd3049 : mem_out_dec = 6'b111111;\n 12'd3050 : mem_out_dec = 6'b111111;\n 12'd3051 : mem_out_dec = 6'b111111;\n 12'd3052 : mem_out_dec = 6'b111111;\n 12'd3053 : mem_out_dec = 6'b111111;\n 12'd3054 : mem_out_dec = 6'b111111;\n 12'd3055 : mem_out_dec = 6'b111111;\n 12'd3056 : mem_out_dec = 6'b111111;\n 12'd3057 : mem_out_dec = 6'b111111;\n 12'd3058 : mem_out_dec = 6'b111111;\n 12'd3059 : mem_out_dec = 6'b111111;\n 12'd3060 : mem_out_dec = 6'b111111;\n 12'd3061 : mem_out_dec = 6'b000100;\n 12'd3062 : mem_out_dec = 6'b000101;\n 12'd3063 : mem_out_dec = 6'b000110;\n 12'd3064 : mem_out_dec = 6'b000110;\n 12'd3065 : mem_out_dec = 6'b000111;\n 12'd3066 : mem_out_dec = 6'b000111;\n 12'd3067 : mem_out_dec = 6'b001000;\n 12'd3068 : mem_out_dec = 6'b001001;\n 12'd3069 : mem_out_dec = 6'b001001;\n 12'd3070 : mem_out_dec = 6'b001010;\n 12'd3071 : mem_out_dec = 6'b001011;\n 12'd3072 : mem_out_dec = 6'b111111;\n 12'd3073 : mem_out_dec = 6'b111111;\n 12'd3074 : mem_out_dec = 6'b111111;\n 12'd3075 : mem_out_dec = 6'b111111;\n 12'd3076 : mem_out_dec = 6'b111111;\n 12'd3077 : mem_out_dec = 6'b111111;\n 12'd3078 : mem_out_dec = 6'b111111;\n 12'd3079 : mem_out_dec = 6'b111111;\n 12'd3080 : mem_out_dec = 6'b111111;\n 12'd3081 : mem_out_dec = 6'b111111;\n 12'd3082 : mem_out_dec = 6'b111111;\n 12'd3083 : mem_out_dec = 6'b111111;\n 12'd3084 : mem_out_dec = 6'b111111;\n 12'd3085 : mem_out_dec = 6'b111111;\n 12'd3086 : mem_out_dec = 6'b111111;\n 12'd3087 : mem_out_dec = 6'b111111;\n 12'd3088 : mem_out_dec = 6'b111111;\n 12'd3089 : mem_out_dec = 6'b111111;\n 12'd3090 : mem_out_dec = 6'b111111;\n 12'd3091 : mem_out_dec = 6'b111111;\n 12'd3092 : mem_out_dec = 6'b111111;\n 12'd3093 : mem_out_dec = 6'b111111;\n 12'd3094 : mem_out_dec = 6'b111111;\n 12'd3095 : mem_out_dec = 6'b111111;\n 12'd3096 : mem_out_dec = 6'b111111;\n 12'd3097 : mem_out_dec = 6'b111111;\n 12'd3098 : mem_out_dec = 6'b111111;\n 12'd3099 : mem_out_dec = 6'b111111;\n 12'd3100 : mem_out_dec = 6'b111111;\n 12'd3101 : mem_out_dec = 6'b111111;\n 12'd3102 : mem_out_dec = 6'b111111;\n 12'd3103 : mem_out_dec = 6'b111111;\n 12'd3104 : mem_out_dec = 6'b111111;\n 12'd3105 : mem_out_dec = 6'b111111;\n 12'd3106 : mem_out_dec = 6'b111111;\n 12'd3107 : mem_out_dec = 6'b111111;\n 12'd3108 : mem_out_dec = 6'b111111;\n 12'd3109 : mem_out_dec = 6'b111111;\n 12'd3110 : mem_out_dec = 6'b111111;\n 12'd3111 : mem_out_dec = 6'b111111;\n 12'd3112 : mem_out_dec = 6'b111111;\n 12'd3113 : mem_out_dec = 6'b111111;\n 12'd3114 : mem_out_dec = 6'b111111;\n 12'd3115 : mem_out_dec = 6'b111111;\n 12'd3116 : mem_out_dec = 6'b111111;\n 12'd3117 : mem_out_dec = 6'b111111;\n 12'd3118 : mem_out_dec = 6'b111111;\n 12'd3119 : mem_out_dec = 6'b111111;\n 12'd3120 : mem_out_dec = 6'b111111;\n 12'd3121 : mem_out_dec = 6'b111111;\n 12'd3122 : mem_out_dec = 6'b111111;\n 12'd3123 : mem_out_dec = 6'b111111;\n 12'd3124 : mem_out_dec = 6'b111111;\n 12'd3125 : mem_out_dec = 6'b111111;\n 12'd3126 : mem_out_dec = 6'b000100;\n 12'd3127 : mem_out_dec = 6'b000101;\n 12'd3128 : mem_out_dec = 6'b000101;\n 12'd3129 : mem_out_dec = 6'b000110;\n 12'd3130 : mem_out_dec = 6'b000110;\n 12'd3131 : mem_out_dec = 6'b000111;\n 12'd3132 : mem_out_dec = 6'b001000;\n 12'd3133 : mem_out_dec = 6'b001000;\n 12'd3134 : mem_out_dec = 6'b001001;\n 12'd3135 : mem_out_dec = 6'b001010;\n 12'd3136 : mem_out_dec = 6'b111111;\n 12'd3137 : mem_out_dec = 6'b111111;\n 12'd3138 : mem_out_dec = 6'b111111;\n 12'd3139 : mem_out_dec = 6'b111111;\n 12'd3140 : mem_out_dec = 6'b111111;\n 12'd3141 : mem_out_dec = 6'b111111;\n 12'd3142 : mem_out_dec = 6'b111111;\n 12'd3143 : mem_out_dec = 6'b111111;\n 12'd3144 : mem_out_dec = 6'b111111;\n 12'd3145 : mem_out_dec = 6'b111111;\n 12'd3146 : mem_out_dec = 6'b111111;\n 12'd3147 : mem_out_dec = 6'b111111;\n 12'd3148 : mem_out_dec = 6'b111111;\n 12'd3149 : mem_out_dec = 6'b111111;\n 12'd3150 : mem_out_dec = 6'b111111;\n 12'd3151 : mem_out_dec = 6'b111111;\n 12'd3152 : mem_out_dec = 6'b111111;\n 12'd3153 : mem_out_dec = 6'b111111;\n 12'd3154 : mem_out_dec = 6'b111111;\n 12'd3155 : mem_out_dec = 6'b111111;\n 12'd3156 : mem_out_dec = 6'b111111;\n 12'd3157 : mem_out_dec = 6'b111111;\n 12'd3158 : mem_out_dec = 6'b111111;\n 12'd3159 : mem_out_dec = 6'b111111;\n 12'd3160 : mem_out_dec = 6'b111111;\n 12'd3161 : mem_out_dec = 6'b111111;\n 12'd3162 : mem_out_dec = 6'b111111;\n 12'd3163 : mem_out_dec = 6'b111111;\n 12'd3164 : mem_out_dec = 6'b111111;\n 12'd3165 : mem_out_dec = 6'b111111;\n 12'd3166 : mem_out_dec = 6'b111111;\n 12'd3167 : mem_out_dec = 6'b111111;\n 12'd3168 : mem_out_dec = 6'b111111;\n 12'd3169 : mem_out_dec = 6'b111111;\n 12'd3170 : mem_out_dec = 6'b111111;\n 12'd3171 : mem_out_dec = 6'b111111;\n 12'd3172 : mem_out_dec = 6'b111111;\n 12'd3173 : mem_out_dec = 6'b111111;\n 12'd3174 : mem_out_dec = 6'b111111;\n 12'd3175 : mem_out_dec = 6'b111111;\n 12'd3176 : mem_out_dec = 6'b111111;\n 12'd3177 : mem_out_dec = 6'b111111;\n 12'd3178 : mem_out_dec = 6'b111111;\n 12'd3179 : mem_out_dec = 6'b111111;\n 12'd3180 : mem_out_dec = 6'b111111;\n 12'd3181 : mem_out_dec = 6'b111111;\n 12'd3182 : mem_out_dec = 6'b111111;\n 12'd3183 : mem_out_dec = 6'b111111;\n 12'd3184 : mem_out_dec = 6'b111111;\n 12'd3185 : mem_out_dec = 6'b111111;\n 12'd3186 : mem_out_dec = 6'b111111;\n 12'd3187 : mem_out_dec = 6'b111111;\n 12'd3188 : mem_out_dec = 6'b111111;\n 12'd3189 : mem_out_dec = 6'b111111;\n 12'd3190 : mem_out_dec = 6'b111111;\n 12'd3191 : mem_out_dec = 6'b000100;\n 12'd3192 : mem_out_dec = 6'b000100;\n 12'd3193 : mem_out_dec = 6'b000101;\n 12'd3194 : mem_out_dec = 6'b000110;\n 12'd3195 : mem_out_dec = 6'b000110;\n 12'd3196 : mem_out_dec = 6'b000111;\n 12'd3197 : mem_out_dec = 6'b001000;\n 12'd3198 : mem_out_dec = 6'b001000;\n 12'd3199 : mem_out_dec = 6'b001001;\n 12'd3200 : mem_out_dec = 6'b111111;\n 12'd3201 : mem_out_dec = 6'b111111;\n 12'd3202 : mem_out_dec = 6'b111111;\n 12'd3203 : mem_out_dec = 6'b111111;\n 12'd3204 : mem_out_dec = 6'b111111;\n 12'd3205 : mem_out_dec = 6'b111111;\n 12'd3206 : mem_out_dec = 6'b111111;\n 12'd3207 : mem_out_dec = 6'b111111;\n 12'd3208 : mem_out_dec = 6'b111111;\n 12'd3209 : mem_out_dec = 6'b111111;\n 12'd3210 : mem_out_dec = 6'b111111;\n 12'd3211 : mem_out_dec = 6'b111111;\n 12'd3212 : mem_out_dec = 6'b111111;\n 12'd3213 : mem_out_dec = 6'b111111;\n 12'd3214 : mem_out_dec = 6'b111111;\n 12'd3215 : mem_out_dec = 6'b111111;\n 12'd3216 : mem_out_dec = 6'b111111;\n 12'd3217 : mem_out_dec = 6'b111111;\n 12'd3218 : mem_out_dec = 6'b111111;\n 12'd3219 : mem_out_dec = 6'b111111;\n 12'd3220 : mem_out_dec = 6'b111111;\n 12'd3221 : mem_out_dec = 6'b111111;\n 12'd3222 : mem_out_dec = 6'b111111;\n 12'd3223 : mem_out_dec = 6'b111111;\n 12'd3224 : mem_out_dec = 6'b111111;\n 12'd3225 : mem_out_dec = 6'b111111;\n 12'd3226 : mem_out_dec = 6'b111111;\n 12'd3227 : mem_out_dec = 6'b111111;\n 12'd3228 : mem_out_dec = 6'b111111;\n 12'd3229 : mem_out_dec = 6'b111111;\n 12'd3230 : mem_out_dec = 6'b111111;\n 12'd3231 : mem_out_dec = 6'b111111;\n 12'd3232 : mem_out_dec = 6'b111111;\n 12'd3233 : mem_out_dec = 6'b111111;\n 12'd3234 : mem_out_dec = 6'b111111;\n 12'd3235 : mem_out_dec = 6'b111111;\n 12'd3236 : mem_out_dec = 6'b111111;\n 12'd3237 : mem_out_dec = 6'b111111;\n 12'd3238 : mem_out_dec = 6'b111111;\n 12'd3239 : mem_out_dec = 6'b111111;\n 12'd3240 : mem_out_dec = 6'b111111;\n 12'd3241 : mem_out_dec = 6'b111111;\n 12'd3242 : mem_out_dec = 6'b111111;\n 12'd3243 : mem_out_dec = 6'b111111;\n 12'd3244 : mem_out_dec = 6'b111111;\n 12'd3245 : mem_out_dec = 6'b111111;\n 12'd3246 : mem_out_dec = 6'b111111;\n 12'd3247 : mem_out_dec = 6'b111111;\n 12'd3248 : mem_out_dec = 6'b111111;\n 12'd3249 : mem_out_dec = 6'b111111;\n 12'd3250 : mem_out_dec = 6'b111111;\n 12'd3251 : mem_out_dec = 6'b111111;\n 12'd3252 : mem_out_dec = 6'b111111;\n 12'd3253 : mem_out_dec = 6'b111111;\n 12'd3254 : mem_out_dec = 6'b111111;\n 12'd3255 : mem_out_dec = 6'b111111;\n 12'd3256 : mem_out_dec = 6'b000100;\n 12'd3257 : mem_out_dec = 6'b000100;\n 12'd3258 : mem_out_dec = 6'b000101;\n 12'd3259 : mem_out_dec = 6'b000110;\n 12'd3260 : mem_out_dec = 6'b000110;\n 12'd3261 : mem_out_dec = 6'b000111;\n 12'd3262 : mem_out_dec = 6'b001000;\n 12'd3263 : mem_out_dec = 6'b001001;\n 12'd3264 : mem_out_dec = 6'b111111;\n 12'd3265 : mem_out_dec = 6'b111111;\n 12'd3266 : mem_out_dec = 6'b111111;\n 12'd3267 : mem_out_dec = 6'b111111;\n 12'd3268 : mem_out_dec = 6'b111111;\n 12'd3269 : mem_out_dec = 6'b111111;\n 12'd3270 : mem_out_dec = 6'b111111;\n 12'd3271 : mem_out_dec = 6'b111111;\n 12'd3272 : mem_out_dec = 6'b111111;\n 12'd3273 : mem_out_dec = 6'b111111;\n 12'd3274 : mem_out_dec = 6'b111111;\n 12'd3275 : mem_out_dec = 6'b111111;\n 12'd3276 : mem_out_dec = 6'b111111;\n 12'd3277 : mem_out_dec = 6'b111111;\n 12'd3278 : mem_out_dec = 6'b111111;\n 12'd3279 : mem_out_dec = 6'b111111;\n 12'd3280 : mem_out_dec = 6'b111111;\n 12'd3281 : mem_out_dec = 6'b111111;\n 12'd3282 : mem_out_dec = 6'b111111;\n 12'd3283 : mem_out_dec = 6'b111111;\n 12'd3284 : mem_out_dec = 6'b111111;\n 12'd3285 : mem_out_dec = 6'b111111;\n 12'd3286 : mem_out_dec = 6'b111111;\n 12'd3287 : mem_out_dec = 6'b111111;\n 12'd3288 : mem_out_dec = 6'b111111;\n 12'd3289 : mem_out_dec = 6'b111111;\n 12'd3290 : mem_out_dec = 6'b111111;\n 12'd3291 : mem_out_dec = 6'b111111;\n 12'd3292 : mem_out_dec = 6'b111111;\n 12'd3293 : mem_out_dec = 6'b111111;\n 12'd3294 : mem_out_dec = 6'b111111;\n 12'd3295 : mem_out_dec = 6'b111111;\n 12'd3296 : mem_out_dec = 6'b111111;\n 12'd3297 : mem_out_dec = 6'b111111;\n 12'd3298 : mem_out_dec = 6'b111111;\n 12'd3299 : mem_out_dec = 6'b111111;\n 12'd3300 : mem_out_dec = 6'b111111;\n 12'd3301 : mem_out_dec = 6'b111111;\n 12'd3302 : mem_out_dec = 6'b111111;\n 12'd3303 : mem_out_dec = 6'b111111;\n 12'd3304 : mem_out_dec = 6'b111111;\n 12'd3305 : mem_out_dec = 6'b111111;\n 12'd3306 : mem_out_dec = 6'b111111;\n 12'd3307 : mem_out_dec = 6'b111111;\n 12'd3308 : mem_out_dec = 6'b111111;\n 12'd3309 : mem_out_dec = 6'b111111;\n 12'd3310 : mem_out_dec = 6'b111111;\n 12'd3311 : mem_out_dec = 6'b111111;\n 12'd3312 : mem_out_dec = 6'b111111;\n 12'd3313 : mem_out_dec = 6'b111111;\n 12'd3314 : mem_out_dec = 6'b111111;\n 12'd3315 : mem_out_dec = 6'b111111;\n 12'd3316 : mem_out_dec = 6'b111111;\n 12'd3317 : mem_out_dec = 6'b111111;\n 12'd3318 : mem_out_dec = 6'b111111;\n 12'd3319 : mem_out_dec = 6'b111111;\n 12'd3320 : mem_out_dec = 6'b111111;\n 12'd3321 : mem_out_dec = 6'b000100;\n 12'd3322 : mem_out_dec = 6'b000100;\n 12'd3323 : mem_out_dec = 6'b000101;\n 12'd3324 : mem_out_dec = 6'b000110;\n 12'd3325 : mem_out_dec = 6'b000111;\n 12'd3326 : mem_out_dec = 6'b001000;\n 12'd3327 : mem_out_dec = 6'b001000;\n 12'd3328 : mem_out_dec = 6'b111111;\n 12'd3329 : mem_out_dec = 6'b111111;\n 12'd3330 : mem_out_dec = 6'b111111;\n 12'd3331 : mem_out_dec = 6'b111111;\n 12'd3332 : mem_out_dec = 6'b111111;\n 12'd3333 : mem_out_dec = 6'b111111;\n 12'd3334 : mem_out_dec = 6'b111111;\n 12'd3335 : mem_out_dec = 6'b111111;\n 12'd3336 : mem_out_dec = 6'b111111;\n 12'd3337 : mem_out_dec = 6'b111111;\n 12'd3338 : mem_out_dec = 6'b111111;\n 12'd3339 : mem_out_dec = 6'b111111;\n 12'd3340 : mem_out_dec = 6'b111111;\n 12'd3341 : mem_out_dec = 6'b111111;\n 12'd3342 : mem_out_dec = 6'b111111;\n 12'd3343 : mem_out_dec = 6'b111111;\n 12'd3344 : mem_out_dec = 6'b111111;\n 12'd3345 : mem_out_dec = 6'b111111;\n 12'd3346 : mem_out_dec = 6'b111111;\n 12'd3347 : mem_out_dec = 6'b111111;\n 12'd3348 : mem_out_dec = 6'b111111;\n 12'd3349 : mem_out_dec = 6'b111111;\n 12'd3350 : mem_out_dec = 6'b111111;\n 12'd3351 : mem_out_dec = 6'b111111;\n 12'd3352 : mem_out_dec = 6'b111111;\n 12'd3353 : mem_out_dec = 6'b111111;\n 12'd3354 : mem_out_dec = 6'b111111;\n 12'd3355 : mem_out_dec = 6'b111111;\n 12'd3356 : mem_out_dec = 6'b111111;\n 12'd3357 : mem_out_dec = 6'b111111;\n 12'd3358 : mem_out_dec = 6'b111111;\n 12'd3359 : mem_out_dec = 6'b111111;\n 12'd3360 : mem_out_dec = 6'b111111;\n 12'd3361 : mem_out_dec = 6'b111111;\n 12'd3362 : mem_out_dec = 6'b111111;\n 12'd3363 : mem_out_dec = 6'b111111;\n 12'd3364 : mem_out_dec = 6'b111111;\n 12'd3365 : mem_out_dec = 6'b111111;\n 12'd3366 : mem_out_dec = 6'b111111;\n 12'd3367 : mem_out_dec = 6'b111111;\n 12'd3368 : mem_out_dec = 6'b111111;\n 12'd3369 : mem_out_dec = 6'b111111;\n 12'd3370 : mem_out_dec = 6'b111111;\n 12'd3371 : mem_out_dec = 6'b111111;\n 12'd3372 : mem_out_dec = 6'b111111;\n 12'd3373 : mem_out_dec = 6'b111111;\n 12'd3374 : mem_out_dec = 6'b111111;\n 12'd3375 : mem_out_dec = 6'b111111;\n 12'd3376 : mem_out_dec = 6'b111111;\n 12'd3377 : mem_out_dec = 6'b111111;\n 12'd3378 : mem_out_dec = 6'b111111;\n 12'd3379 : mem_out_dec = 6'b111111;\n 12'd3380 : mem_out_dec = 6'b111111;\n 12'd3381 : mem_out_dec = 6'b111111;\n 12'd3382 : mem_out_dec = 6'b111111;\n 12'd3383 : mem_out_dec = 6'b111111;\n 12'd3384 : mem_out_dec = 6'b111111;\n 12'd3385 : mem_out_dec = 6'b111111;\n 12'd3386 : mem_out_dec = 6'b000100;\n 12'd3387 : mem_out_dec = 6'b000101;\n 12'd3388 : mem_out_dec = 6'b000110;\n 12'd3389 : mem_out_dec = 6'b000110;\n 12'd3390 : mem_out_dec = 6'b000111;\n 12'd3391 : mem_out_dec = 6'b001000;\n 12'd3392 : mem_out_dec = 6'b111111;\n 12'd3393 : mem_out_dec = 6'b111111;\n 12'd3394 : mem_out_dec = 6'b111111;\n 12'd3395 : mem_out_dec = 6'b111111;\n 12'd3396 : mem_out_dec = 6'b111111;\n 12'd3397 : mem_out_dec = 6'b111111;\n 12'd3398 : mem_out_dec = 6'b111111;\n 12'd3399 : mem_out_dec = 6'b111111;\n 12'd3400 : mem_out_dec = 6'b111111;\n 12'd3401 : mem_out_dec = 6'b111111;\n 12'd3402 : mem_out_dec = 6'b111111;\n 12'd3403 : mem_out_dec = 6'b111111;\n 12'd3404 : mem_out_dec = 6'b111111;\n 12'd3405 : mem_out_dec = 6'b111111;\n 12'd3406 : mem_out_dec = 6'b111111;\n 12'd3407 : mem_out_dec = 6'b111111;\n 12'd3408 : mem_out_dec = 6'b111111;\n 12'd3409 : mem_out_dec = 6'b111111;\n 12'd3410 : mem_out_dec = 6'b111111;\n 12'd3411 : mem_out_dec = 6'b111111;\n 12'd3412 : mem_out_dec = 6'b111111;\n 12'd3413 : mem_out_dec = 6'b111111;\n 12'd3414 : mem_out_dec = 6'b111111;\n 12'd3415 : mem_out_dec = 6'b111111;\n 12'd3416 : mem_out_dec = 6'b111111;\n 12'd3417 : mem_out_dec = 6'b111111;\n 12'd3418 : mem_out_dec = 6'b111111;\n 12'd3419 : mem_out_dec = 6'b111111;\n 12'd3420 : mem_out_dec = 6'b111111;\n 12'd3421 : mem_out_dec = 6'b111111;\n 12'd3422 : mem_out_dec = 6'b111111;\n 12'd3423 : mem_out_dec = 6'b111111;\n 12'd3424 : mem_out_dec = 6'b111111;\n 12'd3425 : mem_out_dec = 6'b111111;\n 12'd3426 : mem_out_dec = 6'b111111;\n 12'd3427 : mem_out_dec = 6'b111111;\n 12'd3428 : mem_out_dec = 6'b111111;\n 12'd3429 : mem_out_dec = 6'b111111;\n 12'd3430 : mem_out_dec = 6'b111111;\n 12'd3431 : mem_out_dec = 6'b111111;\n 12'd3432 : mem_out_dec = 6'b111111;\n 12'd3433 : mem_out_dec = 6'b111111;\n 12'd3434 : mem_out_dec = 6'b111111;\n 12'd3435 : mem_out_dec = 6'b111111;\n 12'd3436 : mem_out_dec = 6'b111111;\n 12'd3437 : mem_out_dec = 6'b111111;\n 12'd3438 : mem_out_dec = 6'b111111;\n 12'd3439 : mem_out_dec = 6'b111111;\n 12'd3440 : mem_out_dec = 6'b111111;\n 12'd3441 : mem_out_dec = 6'b111111;\n 12'd3442 : mem_out_dec = 6'b111111;\n 12'd3443 : mem_out_dec = 6'b111111;\n 12'd3444 : mem_out_dec = 6'b111111;\n 12'd3445 : mem_out_dec = 6'b111111;\n 12'd3446 : mem_out_dec = 6'b111111;\n 12'd3447 : mem_out_dec = 6'b111111;\n 12'd3448 : mem_out_dec = 6'b111111;\n 12'd3449 : mem_out_dec = 6'b111111;\n 12'd3450 : mem_out_dec = 6'b111111;\n 12'd3451 : mem_out_dec = 6'b000100;\n 12'd3452 : mem_out_dec = 6'b000101;\n 12'd3453 : mem_out_dec = 6'b000110;\n 12'd3454 : mem_out_dec = 6'b000111;\n 12'd3455 : mem_out_dec = 6'b001000;\n 12'd3456 : mem_out_dec = 6'b111111;\n 12'd3457 : mem_out_dec = 6'b111111;\n 12'd3458 : mem_out_dec = 6'b111111;\n 12'd3459 : mem_out_dec = 6'b111111;\n 12'd3460 : mem_out_dec = 6'b111111;\n 12'd3461 : mem_out_dec = 6'b111111;\n 12'd3462 : mem_out_dec = 6'b111111;\n 12'd3463 : mem_out_dec = 6'b111111;\n 12'd3464 : mem_out_dec = 6'b111111;\n 12'd3465 : mem_out_dec = 6'b111111;\n 12'd3466 : mem_out_dec = 6'b111111;\n 12'd3467 : mem_out_dec = 6'b111111;\n 12'd3468 : mem_out_dec = 6'b111111;\n 12'd3469 : mem_out_dec = 6'b111111;\n 12'd3470 : mem_out_dec = 6'b111111;\n 12'd3471 : mem_out_dec = 6'b111111;\n 12'd3472 : mem_out_dec = 6'b111111;\n 12'd3473 : mem_out_dec = 6'b111111;\n 12'd3474 : mem_out_dec = 6'b111111;\n 12'd3475 : mem_out_dec = 6'b111111;\n 12'd3476 : mem_out_dec = 6'b111111;\n 12'd3477 : mem_out_dec = 6'b111111;\n 12'd3478 : mem_out_dec = 6'b111111;\n 12'd3479 : mem_out_dec = 6'b111111;\n 12'd3480 : mem_out_dec = 6'b111111;\n 12'd3481 : mem_out_dec = 6'b111111;\n 12'd3482 : mem_out_dec = 6'b111111;\n 12'd3483 : mem_out_dec = 6'b111111;\n 12'd3484 : mem_out_dec = 6'b111111;\n 12'd3485 : mem_out_dec = 6'b111111;\n 12'd3486 : mem_out_dec = 6'b111111;\n 12'd3487 : mem_out_dec = 6'b111111;\n 12'd3488 : mem_out_dec = 6'b111111;\n 12'd3489 : mem_out_dec = 6'b111111;\n 12'd3490 : mem_out_dec = 6'b111111;\n 12'd3491 : mem_out_dec = 6'b111111;\n 12'd3492 : mem_out_dec = 6'b111111;\n 12'd3493 : mem_out_dec = 6'b111111;\n 12'd3494 : mem_out_dec = 6'b111111;\n 12'd3495 : mem_out_dec = 6'b111111;\n 12'd3496 : mem_out_dec = 6'b111111;\n 12'd3497 : mem_out_dec = 6'b111111;\n 12'd3498 : mem_out_dec = 6'b111111;\n 12'd3499 : mem_out_dec = 6'b111111;\n 12'd3500 : mem_out_dec = 6'b111111;\n 12'd3501 : mem_out_dec = 6'b111111;\n 12'd3502 : mem_out_dec = 6'b111111;\n 12'd3503 : mem_out_dec = 6'b111111;\n 12'd3504 : mem_out_dec = 6'b111111;\n 12'd3505 : mem_out_dec = 6'b111111;\n 12'd3506 : mem_out_dec = 6'b111111;\n 12'd3507 : mem_out_dec = 6'b111111;\n 12'd3508 : mem_out_dec = 6'b111111;\n 12'd3509 : mem_out_dec = 6'b111111;\n 12'd3510 : mem_out_dec = 6'b111111;\n 12'd3511 : mem_out_dec = 6'b111111;\n 12'd3512 : mem_out_dec = 6'b111111;\n 12'd3513 : mem_out_dec = 6'b111111;\n 12'd3514 : mem_out_dec = 6'b111111;\n 12'd3515 : mem_out_dec = 6'b111111;\n 12'd3516 : mem_out_dec = 6'b000101;\n 12'd3517 : mem_out_dec = 6'b000110;\n 12'd3518 : mem_out_dec = 6'b000110;\n 12'd3519 : mem_out_dec = 6'b000111;\n 12'd3520 : mem_out_dec = 6'b111111;\n 12'd3521 : mem_out_dec = 6'b111111;\n 12'd3522 : mem_out_dec = 6'b111111;\n 12'd3523 : mem_out_dec = 6'b111111;\n 12'd3524 : mem_out_dec = 6'b111111;\n 12'd3525 : mem_out_dec = 6'b111111;\n 12'd3526 : mem_out_dec = 6'b111111;\n 12'd3527 : mem_out_dec = 6'b111111;\n 12'd3528 : mem_out_dec = 6'b111111;\n 12'd3529 : mem_out_dec = 6'b111111;\n 12'd3530 : mem_out_dec = 6'b111111;\n 12'd3531 : mem_out_dec = 6'b111111;\n 12'd3532 : mem_out_dec = 6'b111111;\n 12'd3533 : mem_out_dec = 6'b111111;\n 12'd3534 : mem_out_dec = 6'b111111;\n 12'd3535 : mem_out_dec = 6'b111111;\n 12'd3536 : mem_out_dec = 6'b111111;\n 12'd3537 : mem_out_dec = 6'b111111;\n 12'd3538 : mem_out_dec = 6'b111111;\n 12'd3539 : mem_out_dec = 6'b111111;\n 12'd3540 : mem_out_dec = 6'b111111;\n 12'd3541 : mem_out_dec = 6'b111111;\n 12'd3542 : mem_out_dec = 6'b111111;\n 12'd3543 : mem_out_dec = 6'b111111;\n 12'd3544 : mem_out_dec = 6'b111111;\n 12'd3545 : mem_out_dec = 6'b111111;\n 12'd3546 : mem_out_dec = 6'b111111;\n 12'd3547 : mem_out_dec = 6'b111111;\n 12'd3548 : mem_out_dec = 6'b111111;\n 12'd3549 : mem_out_dec = 6'b111111;\n 12'd3550 : mem_out_dec = 6'b111111;\n 12'd3551 : mem_out_dec = 6'b111111;\n 12'd3552 : mem_out_dec = 6'b111111;\n 12'd3553 : mem_out_dec = 6'b111111;\n 12'd3554 : mem_out_dec = 6'b111111;\n 12'd3555 : mem_out_dec = 6'b111111;\n 12'd3556 : mem_out_dec = 6'b111111;\n 12'd3557 : mem_out_dec = 6'b111111;\n 12'd3558 : mem_out_dec = 6'b111111;\n 12'd3559 : mem_out_dec = 6'b111111;\n 12'd3560 : mem_out_dec = 6'b111111;\n 12'd3561 : mem_out_dec = 6'b111111;\n 12'd3562 : mem_out_dec = 6'b111111;\n 12'd3563 : mem_out_dec = 6'b111111;\n 12'd3564 : mem_out_dec = 6'b111111;\n 12'd3565 : mem_out_dec = 6'b111111;\n 12'd3566 : mem_out_dec = 6'b111111;\n 12'd3567 : mem_out_dec = 6'b111111;\n 12'd3568 : mem_out_dec = 6'b111111;\n 12'd3569 : mem_out_dec = 6'b111111;\n 12'd3570 : mem_out_dec = 6'b111111;\n 12'd3571 : mem_out_dec = 6'b111111;\n 12'd3572 : mem_out_dec = 6'b111111;\n 12'd3573 : mem_out_dec = 6'b111111;\n 12'd3574 : mem_out_dec = 6'b111111;\n 12'd3575 : mem_out_dec = 6'b111111;\n 12'd3576 : mem_out_dec = 6'b111111;\n 12'd3577 : mem_out_dec = 6'b111111;\n 12'd3578 : mem_out_dec = 6'b111111;\n 12'd3579 : mem_out_dec = 6'b111111;\n 12'd3580 : mem_out_dec = 6'b111111;\n 12'd3581 : mem_out_dec = 6'b000101;\n 12'd3582 : mem_out_dec = 6'b000110;\n 12'd3583 : mem_out_dec = 6'b000110;\n 12'd3584 : mem_out_dec = 6'b111111;\n 12'd3585 : mem_out_dec = 6'b111111;\n 12'd3586 : mem_out_dec = 6'b111111;\n 12'd3587 : mem_out_dec = 6'b111111;\n 12'd3588 : mem_out_dec = 6'b111111;\n 12'd3589 : mem_out_dec = 6'b111111;\n 12'd3590 : mem_out_dec = 6'b111111;\n 12'd3591 : mem_out_dec = 6'b111111;\n 12'd3592 : mem_out_dec = 6'b111111;\n 12'd3593 : mem_out_dec = 6'b111111;\n 12'd3594 : mem_out_dec = 6'b111111;\n 12'd3595 : mem_out_dec = 6'b111111;\n 12'd3596 : mem_out_dec = 6'b111111;\n 12'd3597 : mem_out_dec = 6'b111111;\n 12'd3598 : mem_out_dec = 6'b111111;\n 12'd3599 : mem_out_dec = 6'b111111;\n 12'd3600 : mem_out_dec = 6'b111111;\n 12'd3601 : mem_out_dec = 6'b111111;\n 12'd3602 : mem_out_dec = 6'b111111;\n 12'd3603 : mem_out_dec = 6'b111111;\n 12'd3604 : mem_out_dec = 6'b111111;\n 12'd3605 : mem_out_dec = 6'b111111;\n 12'd3606 : mem_out_dec = 6'b111111;\n 12'd3607 : mem_out_dec = 6'b111111;\n 12'd3608 : mem_out_dec = 6'b111111;\n 12'd3609 : mem_out_dec = 6'b111111;\n 12'd3610 : mem_out_dec = 6'b111111;\n 12'd3611 : mem_out_dec = 6'b111111;\n 12'd3612 : mem_out_dec = 6'b111111;\n 12'd3613 : mem_out_dec = 6'b111111;\n 12'd3614 : mem_out_dec = 6'b111111;\n 12'd3615 : mem_out_dec = 6'b111111;\n 12'd3616 : mem_out_dec = 6'b111111;\n 12'd3617 : mem_out_dec = 6'b111111;\n 12'd3618 : mem_out_dec = 6'b111111;\n 12'd3619 : mem_out_dec = 6'b111111;\n 12'd3620 : mem_out_dec = 6'b111111;\n 12'd3621 : mem_out_dec = 6'b111111;\n 12'd3622 : mem_out_dec = 6'b111111;\n 12'd3623 : mem_out_dec = 6'b111111;\n 12'd3624 : mem_out_dec = 6'b111111;\n 12'd3625 : mem_out_dec = 6'b111111;\n 12'd3626 : mem_out_dec = 6'b111111;\n 12'd3627 : mem_out_dec = 6'b111111;\n 12'd3628 : mem_out_dec = 6'b111111;\n 12'd3629 : mem_out_dec = 6'b111111;\n 12'd3630 : mem_out_dec = 6'b111111;\n 12'd3631 : mem_out_dec = 6'b111111;\n 12'd3632 : mem_out_dec = 6'b111111;\n 12'd3633 : mem_out_dec = 6'b111111;\n 12'd3634 : mem_out_dec = 6'b111111;\n 12'd3635 : mem_out_dec = 6'b111111;\n 12'd3636 : mem_out_dec = 6'b111111;\n 12'd3637 : mem_out_dec = 6'b111111;\n 12'd3638 : mem_out_dec = 6'b111111;\n 12'd3639 : mem_out_dec = 6'b111111;\n 12'd3640 : mem_out_dec = 6'b111111;\n 12'd3641 : mem_out_dec = 6'b111111;\n 12'd3642 : mem_out_dec = 6'b111111;\n 12'd3643 : mem_out_dec = 6'b111111;\n 12'd3644 : mem_out_dec = 6'b111111;\n 12'd3645 : mem_out_dec = 6'b111111;\n 12'd3646 : mem_out_dec = 6'b000100;\n 12'd3647 : mem_out_dec = 6'b000101;\n 12'd3648 : mem_out_dec = 6'b111111;\n 12'd3649 : mem_out_dec = 6'b111111;\n 12'd3650 : mem_out_dec = 6'b111111;\n 12'd3651 : mem_out_dec = 6'b111111;\n 12'd3652 : mem_out_dec = 6'b111111;\n 12'd3653 : mem_out_dec = 6'b111111;\n 12'd3654 : mem_out_dec = 6'b111111;\n 12'd3655 : mem_out_dec = 6'b111111;\n 12'd3656 : mem_out_dec = 6'b111111;\n 12'd3657 : mem_out_dec = 6'b111111;\n 12'd3658 : mem_out_dec = 6'b111111;\n 12'd3659 : mem_out_dec = 6'b111111;\n 12'd3660 : mem_out_dec = 6'b111111;\n 12'd3661 : mem_out_dec = 6'b111111;\n 12'd3662 : mem_out_dec = 6'b111111;\n 12'd3663 : mem_out_dec = 6'b111111;\n 12'd3664 : mem_out_dec = 6'b111111;\n 12'd3665 : mem_out_dec = 6'b111111;\n 12'd3666 : mem_out_dec = 6'b111111;\n 12'd3667 : mem_out_dec = 6'b111111;\n 12'd3668 : mem_out_dec = 6'b111111;\n 12'd3669 : mem_out_dec = 6'b111111;\n 12'd3670 : mem_out_dec = 6'b111111;\n 12'd3671 : mem_out_dec = 6'b111111;\n 12'd3672 : mem_out_dec = 6'b111111;\n 12'd3673 : mem_out_dec = 6'b111111;\n 12'd3674 : mem_out_dec = 6'b111111;\n 12'd3675 : mem_out_dec = 6'b111111;\n 12'd3676 : mem_out_dec = 6'b111111;\n 12'd3677 : mem_out_dec = 6'b111111;\n 12'd3678 : mem_out_dec = 6'b111111;\n 12'd3679 : mem_out_dec = 6'b111111;\n 12'd3680 : mem_out_dec = 6'b111111;\n 12'd3681 : mem_out_dec = 6'b111111;\n 12'd3682 : mem_out_dec = 6'b111111;\n 12'd3683 : mem_out_dec = 6'b111111;\n 12'd3684 : mem_out_dec = 6'b111111;\n 12'd3685 : mem_out_dec = 6'b111111;\n 12'd3686 : mem_out_dec = 6'b111111;\n 12'd3687 : mem_out_dec = 6'b111111;\n 12'd3688 : mem_out_dec = 6'b111111;\n 12'd3689 : mem_out_dec = 6'b111111;\n 12'd3690 : mem_out_dec = 6'b111111;\n 12'd3691 : mem_out_dec = 6'b111111;\n 12'd3692 : mem_out_dec = 6'b111111;\n 12'd3693 : mem_out_dec = 6'b111111;\n 12'd3694 : mem_out_dec = 6'b111111;\n 12'd3695 : mem_out_dec = 6'b111111;\n 12'd3696 : mem_out_dec = 6'b111111;\n 12'd3697 : mem_out_dec = 6'b111111;\n 12'd3698 : mem_out_dec = 6'b111111;\n 12'd3699 : mem_out_dec = 6'b111111;\n 12'd3700 : mem_out_dec = 6'b111111;\n 12'd3701 : mem_out_dec = 6'b111111;\n 12'd3702 : mem_out_dec = 6'b111111;\n 12'd3703 : mem_out_dec = 6'b111111;\n 12'd3704 : mem_out_dec = 6'b111111;\n 12'd3705 : mem_out_dec = 6'b111111;\n 12'd3706 : mem_out_dec = 6'b111111;\n 12'd3707 : mem_out_dec = 6'b111111;\n 12'd3708 : mem_out_dec = 6'b111111;\n 12'd3709 : mem_out_dec = 6'b111111;\n 12'd3710 : mem_out_dec = 6'b111111;\n 12'd3711 : mem_out_dec = 6'b000100;\n 12'd3712 : mem_out_dec = 6'b111111;\n 12'd3713 : mem_out_dec = 6'b111111;\n 12'd3714 : mem_out_dec = 6'b111111;\n 12'd3715 : mem_out_dec = 6'b111111;\n 12'd3716 : mem_out_dec = 6'b111111;\n 12'd3717 : mem_out_dec = 6'b111111;\n 12'd3718 : mem_out_dec = 6'b111111;\n 12'd3719 : mem_out_dec = 6'b111111;\n 12'd3720 : mem_out_dec = 6'b111111;\n 12'd3721 : mem_out_dec = 6'b111111;\n 12'd3722 : mem_out_dec = 6'b111111;\n 12'd3723 : mem_out_dec = 6'b111111;\n 12'd3724 : mem_out_dec = 6'b111111;\n 12'd3725 : mem_out_dec = 6'b111111;\n 12'd3726 : mem_out_dec = 6'b111111;\n 12'd3727 : mem_out_dec = 6'b111111;\n 12'd3728 : mem_out_dec = 6'b111111;\n 12'd3729 : mem_out_dec = 6'b111111;\n 12'd3730 : mem_out_dec = 6'b111111;\n 12'd3731 : mem_out_dec = 6'b111111;\n 12'd3732 : mem_out_dec = 6'b111111;\n 12'd3733 : mem_out_dec = 6'b111111;\n 12'd3734 : mem_out_dec = 6'b111111;\n 12'd3735 : mem_out_dec = 6'b111111;\n 12'd3736 : mem_out_dec = 6'b111111;\n 12'd3737 : mem_out_dec = 6'b111111;\n 12'd3738 : mem_out_dec = 6'b111111;\n 12'd3739 : mem_out_dec = 6'b111111;\n 12'd3740 : mem_out_dec = 6'b111111;\n 12'd3741 : mem_out_dec = 6'b111111;\n 12'd3742 : mem_out_dec = 6'b111111;\n 12'd3743 : mem_out_dec = 6'b111111;\n 12'd3744 : mem_out_dec = 6'b111111;\n 12'd3745 : mem_out_dec = 6'b111111;\n 12'd3746 : mem_out_dec = 6'b111111;\n 12'd3747 : mem_out_dec = 6'b111111;\n 12'd3748 : mem_out_dec = 6'b111111;\n 12'd3749 : mem_out_dec = 6'b111111;\n 12'd3750 : mem_out_dec = 6'b111111;\n 12'd3751 : mem_out_dec = 6'b111111;\n 12'd3752 : mem_out_dec = 6'b111111;\n 12'd3753 : mem_out_dec = 6'b111111;\n 12'd3754 : mem_out_dec = 6'b111111;\n 12'd3755 : mem_out_dec = 6'b111111;\n 12'd3756 : mem_out_dec = 6'b111111;\n 12'd3757 : mem_out_dec = 6'b111111;\n 12'd3758 : mem_out_dec = 6'b111111;\n 12'd3759 : mem_out_dec = 6'b111111;\n 12'd3760 : mem_out_dec = 6'b111111;\n 12'd3761 : mem_out_dec = 6'b111111;\n 12'd3762 : mem_out_dec = 6'b111111;\n 12'd3763 : mem_out_dec = 6'b111111;\n 12'd3764 : mem_out_dec = 6'b111111;\n 12'd3765 : mem_out_dec = 6'b111111;\n 12'd3766 : mem_out_dec = 6'b111111;\n 12'd3767 : mem_out_dec = 6'b111111;\n 12'd3768 : mem_out_dec = 6'b111111;\n 12'd3769 : mem_out_dec = 6'b111111;\n 12'd3770 : mem_out_dec = 6'b111111;\n 12'd3771 : mem_out_dec = 6'b111111;\n 12'd3772 : mem_out_dec = 6'b111111;\n 12'd3773 : mem_out_dec = 6'b111111;\n 12'd3774 : mem_out_dec = 6'b111111;\n 12'd3775 : mem_out_dec = 6'b111111;\n 12'd3776 : mem_out_dec = 6'b111111;\n 12'd3777 : mem_out_dec = 6'b111111;\n 12'd3778 : mem_out_dec = 6'b111111;\n 12'd3779 : mem_out_dec = 6'b111111;\n 12'd3780 : mem_out_dec = 6'b111111;\n 12'd3781 : mem_out_dec = 6'b111111;\n 12'd3782 : mem_out_dec = 6'b111111;\n 12'd3783 : mem_out_dec = 6'b111111;\n 12'd3784 : mem_out_dec = 6'b111111;\n 12'd3785 : mem_out_dec = 6'b111111;\n 12'd3786 : mem_out_dec = 6'b111111;\n 12'd3787 : mem_out_dec = 6'b111111;\n 12'd3788 : mem_out_dec = 6'b111111;\n 12'd3789 : mem_out_dec = 6'b111111;\n 12'd3790 : mem_out_dec = 6'b111111;\n 12'd3791 : mem_out_dec = 6'b111111;\n 12'd3792 : mem_out_dec = 6'b111111;\n 12'd3793 : mem_out_dec = 6'b111111;\n 12'd3794 : mem_out_dec = 6'b111111;\n 12'd3795 : mem_out_dec = 6'b111111;\n 12'd3796 : mem_out_dec = 6'b111111;\n 12'd3797 : mem_out_dec = 6'b111111;\n 12'd3798 : mem_out_dec = 6'b111111;\n 12'd3799 : mem_out_dec = 6'b111111;\n 12'd3800 : mem_out_dec = 6'b111111;\n 12'd3801 : mem_out_dec = 6'b111111;\n 12'd3802 : mem_out_dec = 6'b111111;\n 12'd3803 : mem_out_dec = 6'b111111;\n 12'd3804 : mem_out_dec = 6'b111111;\n 12'd3805 : mem_out_dec = 6'b111111;\n 12'd3806 : mem_out_dec = 6'b111111;\n 12'd3807 : mem_out_dec = 6'b111111;\n 12'd3808 : mem_out_dec = 6'b111111;\n 12'd3809 : mem_out_dec = 6'b111111;\n 12'd3810 : mem_out_dec = 6'b111111;\n 12'd3811 : mem_out_dec = 6'b111111;\n 12'd3812 : mem_out_dec = 6'b111111;\n 12'd3813 : mem_out_dec = 6'b111111;\n 12'd3814 : mem_out_dec = 6'b111111;\n 12'd3815 : mem_out_dec = 6'b111111;\n 12'd3816 : mem_out_dec = 6'b111111;\n 12'd3817 : mem_out_dec = 6'b111111;\n 12'd3818 : mem_out_dec = 6'b111111;\n 12'd3819 : mem_out_dec = 6'b111111;\n 12'd3820 : mem_out_dec = 6'b111111;\n 12'd3821 : mem_out_dec = 6'b111111;\n 12'd3822 : mem_out_dec = 6'b111111;\n 12'd3823 : mem_out_dec = 6'b111111;\n 12'd3824 : mem_out_dec = 6'b111111;\n 12'd3825 : mem_out_dec = 6'b111111;\n 12'd3826 : mem_out_dec = 6'b111111;\n 12'd3827 : mem_out_dec = 6'b111111;\n 12'd3828 : mem_out_dec = 6'b111111;\n 12'd3829 : mem_out_dec = 6'b111111;\n 12'd3830 : mem_out_dec = 6'b111111;\n 12'd3831 : mem_out_dec = 6'b111111;\n 12'd3832 : mem_out_dec = 6'b111111;\n 12'd3833 : mem_out_dec = 6'b111111;\n 12'd3834 : mem_out_dec = 6'b111111;\n 12'd3835 : mem_out_dec = 6'b111111;\n 12'd3836 : mem_out_dec = 6'b111111;\n 12'd3837 : mem_out_dec = 6'b111111;\n 12'd3838 : mem_out_dec = 6'b111111;\n 12'd3839 : mem_out_dec = 6'b111111;\n 12'd3840 : mem_out_dec = 6'b111111;\n 12'd3841 : mem_out_dec = 6'b111111;\n 12'd3842 : mem_out_dec = 6'b111111;\n 12'd3843 : mem_out_dec = 6'b111111;\n 12'd3844 : mem_out_dec = 6'b111111;\n 12'd3845 : mem_out_dec = 6'b111111;\n 12'd3846 : mem_out_dec = 6'b111111;\n 12'd3847 : mem_out_dec = 6'b111111;\n 12'd3848 : mem_out_dec = 6'b111111;\n 12'd3849 : mem_out_dec = 6'b111111;\n 12'd3850 : mem_out_dec = 6'b111111;\n 12'd3851 : mem_out_dec = 6'b111111;\n 12'd3852 : mem_out_dec = 6'b111111;\n 12'd3853 : mem_out_dec = 6'b111111;\n 12'd3854 : mem_out_dec = 6'b111111;\n 12'd3855 : mem_out_dec = 6'b111111;\n 12'd3856 : mem_out_dec = 6'b111111;\n 12'd3857 : mem_out_dec = 6'b111111;\n 12'd3858 : mem_out_dec = 6'b111111;\n 12'd3859 : mem_out_dec = 6'b111111;\n 12'd3860 : mem_out_dec = 6'b111111;\n 12'd3861 : mem_out_dec = 6'b111111;\n 12'd3862 : mem_out_dec = 6'b111111;\n 12'd3863 : mem_out_dec = 6'b111111;\n 12'd3864 : mem_out_dec = 6'b111111;\n 12'd3865 : mem_out_dec = 6'b111111;\n 12'd3866 : mem_out_dec = 6'b111111;\n 12'd3867 : mem_out_dec = 6'b111111;\n 12'd3868 : mem_out_dec = 6'b111111;\n 12'd3869 : mem_out_dec = 6'b111111;\n 12'd3870 : mem_out_dec = 6'b111111;\n 12'd3871 : mem_out_dec = 6'b111111;\n 12'd3872 : mem_out_dec = 6'b111111;\n 12'd3873 : mem_out_dec = 6'b111111;\n 12'd3874 : mem_out_dec = 6'b111111;\n 12'd3875 : mem_out_dec = 6'b111111;\n 12'd3876 : mem_out_dec = 6'b111111;\n 12'd3877 : mem_out_dec = 6'b111111;\n 12'd3878 : mem_out_dec = 6'b111111;\n 12'd3879 : mem_out_dec = 6'b111111;\n 12'd3880 : mem_out_dec = 6'b111111;\n 12'd3881 : mem_out_dec = 6'b111111;\n 12'd3882 : mem_out_dec = 6'b111111;\n 12'd3883 : mem_out_dec = 6'b111111;\n 12'd3884 : mem_out_dec = 6'b111111;\n 12'd3885 : mem_out_dec = 6'b111111;\n 12'd3886 : mem_out_dec = 6'b111111;\n 12'd3887 : mem_out_dec = 6'b111111;\n 12'd3888 : mem_out_dec = 6'b111111;\n 12'd3889 : mem_out_dec = 6'b111111;\n 12'd3890 : mem_out_dec = 6'b111111;\n 12'd3891 : mem_out_dec = 6'b111111;\n 12'd3892 : mem_out_dec = 6'b111111;\n 12'd3893 : mem_out_dec = 6'b111111;\n 12'd3894 : mem_out_dec = 6'b111111;\n 12'd3895 : mem_out_dec = 6'b111111;\n 12'd3896 : mem_out_dec = 6'b111111;\n 12'd3897 : mem_out_dec = 6'b111111;\n 12'd3898 : mem_out_dec = 6'b111111;\n 12'd3899 : mem_out_dec = 6'b111111;\n 12'd3900 : mem_out_dec = 6'b111111;\n 12'd3901 : mem_out_dec = 6'b111111;\n 12'd3902 : mem_out_dec = 6'b111111;\n 12'd3903 : mem_out_dec = 6'b111111;\n 12'd3904 : mem_out_dec = 6'b111111;\n 12'd3905 : mem_out_dec = 6'b111111;\n 12'd3906 : mem_out_dec = 6'b111111;\n 12'd3907 : mem_out_dec = 6'b111111;\n 12'd3908 : mem_out_dec = 6'b111111;\n 12'd3909 : mem_out_dec = 6'b111111;\n 12'd3910 : mem_out_dec = 6'b111111;\n 12'd3911 : mem_out_dec = 6'b111111;\n 12'd3912 : mem_out_dec = 6'b111111;\n 12'd3913 : mem_out_dec = 6'b111111;\n 12'd3914 : mem_out_dec = 6'b111111;\n 12'd3915 : mem_out_dec = 6'b111111;\n 12'd3916 : mem_out_dec = 6'b111111;\n 12'd3917 : mem_out_dec = 6'b111111;\n 12'd3918 : mem_out_dec = 6'b111111;\n 12'd3919 : mem_out_dec = 6'b111111;\n 12'd3920 : mem_out_dec = 6'b111111;\n 12'd3921 : mem_out_dec = 6'b111111;\n 12'd3922 : mem_out_dec = 6'b111111;\n 12'd3923 : mem_out_dec = 6'b111111;\n 12'd3924 : mem_out_dec = 6'b111111;\n 12'd3925 : mem_out_dec = 6'b111111;\n 12'd3926 : mem_out_dec = 6'b111111;\n 12'd3927 : mem_out_dec = 6'b111111;\n 12'd3928 : mem_out_dec = 6'b111111;\n 12'd3929 : mem_out_dec = 6'b111111;\n 12'd3930 : mem_out_dec = 6'b111111;\n 12'd3931 : mem_out_dec = 6'b111111;\n 12'd3932 : mem_out_dec = 6'b111111;\n 12'd3933 : mem_out_dec = 6'b111111;\n 12'd3934 : mem_out_dec = 6'b111111;\n 12'd3935 : mem_out_dec = 6'b111111;\n 12'd3936 : mem_out_dec = 6'b111111;\n 12'd3937 : mem_out_dec = 6'b111111;\n 12'd3938 : mem_out_dec = 6'b111111;\n 12'd3939 : mem_out_dec = 6'b111111;\n 12'd3940 : mem_out_dec = 6'b111111;\n 12'd3941 : mem_out_dec = 6'b111111;\n 12'd3942 : mem_out_dec = 6'b111111;\n 12'd3943 : mem_out_dec = 6'b111111;\n 12'd3944 : mem_out_dec = 6'b111111;\n 12'd3945 : mem_out_dec = 6'b111111;\n 12'd3946 : mem_out_dec = 6'b111111;\n 12'd3947 : mem_out_dec = 6'b111111;\n 12'd3948 : mem_out_dec = 6'b111111;\n 12'd3949 : mem_out_dec = 6'b111111;\n 12'd3950 : mem_out_dec = 6'b111111;\n 12'd3951 : mem_out_dec = 6'b111111;\n 12'd3952 : mem_out_dec = 6'b111111;\n 12'd3953 : mem_out_dec = 6'b111111;\n 12'd3954 : mem_out_dec = 6'b111111;\n 12'd3955 : mem_out_dec = 6'b111111;\n 12'd3956 : mem_out_dec = 6'b111111;\n 12'd3957 : mem_out_dec = 6'b111111;\n 12'd3958 : mem_out_dec = 6'b111111;\n 12'd3959 : mem_out_dec = 6'b111111;\n 12'd3960 : mem_out_dec = 6'b111111;\n 12'd3961 : mem_out_dec = 6'b111111;\n 12'd3962 : mem_out_dec = 6'b111111;\n 12'd3963 : mem_out_dec = 6'b111111;\n 12'd3964 : mem_out_dec = 6'b111111;\n 12'd3965 : mem_out_dec = 6'b111111;\n 12'd3966 : mem_out_dec = 6'b111111;\n 12'd3967 : mem_out_dec = 6'b111111;\n 12'd3968 : mem_out_dec = 6'b111111;\n 12'd3969 : mem_out_dec = 6'b111111;\n 12'd3970 : mem_out_dec = 6'b111111;\n 12'd3971 : mem_out_dec = 6'b111111;\n 12'd3972 : mem_out_dec = 6'b111111;\n 12'd3973 : mem_out_dec = 6'b111111;\n 12'd3974 : mem_out_dec = 6'b111111;\n 12'd3975 : mem_out_dec = 6'b111111;\n 12'd3976 : mem_out_dec = 6'b111111;\n 12'd3977 : mem_out_dec = 6'b111111;\n 12'd3978 : mem_out_dec = 6'b111111;\n 12'd3979 : mem_out_dec = 6'b111111;\n 12'd3980 : mem_out_dec = 6'b111111;\n 12'd3981 : mem_out_dec = 6'b111111;\n 12'd3982 : mem_out_dec = 6'b111111;\n 12'd3983 : mem_out_dec = 6'b111111;\n 12'd3984 : mem_out_dec = 6'b111111;\n 12'd3985 : mem_out_dec = 6'b111111;\n 12'd3986 : mem_out_dec = 6'b111111;\n 12'd3987 : mem_out_dec = 6'b111111;\n 12'd3988 : mem_out_dec = 6'b111111;\n 12'd3989 : mem_out_dec = 6'b111111;\n 12'd3990 : mem_out_dec = 6'b111111;\n 12'd3991 : mem_out_dec = 6'b111111;\n 12'd3992 : mem_out_dec = 6'b111111;\n 12'd3993 : mem_out_dec = 6'b111111;\n 12'd3994 : mem_out_dec = 6'b111111;\n 12'd3995 : mem_out_dec = 6'b111111;\n 12'd3996 : mem_out_dec = 6'b111111;\n 12'd3997 : mem_out_dec = 6'b111111;\n 12'd3998 : mem_out_dec = 6'b111111;\n 12'd3999 : mem_out_dec = 6'b111111;\n 12'd4000 : mem_out_dec = 6'b111111;\n 12'd4001 : mem_out_dec = 6'b111111;\n 12'd4002 : mem_out_dec = 6'b111111;\n 12'd4003 : mem_out_dec = 6'b111111;\n 12'd4004 : mem_out_dec = 6'b111111;\n 12'd4005 : mem_out_dec = 6'b111111;\n 12'd4006 : mem_out_dec = 6'b111111;\n 12'd4007 : mem_out_dec = 6'b111111;\n 12'd4008 : mem_out_dec = 6'b111111;\n 12'd4009 : mem_out_dec = 6'b111111;\n 12'd4010 : mem_out_dec = 6'b111111;\n 12'd4011 : mem_out_dec = 6'b111111;\n 12'd4012 : mem_out_dec = 6'b111111;\n 12'd4013 : mem_out_dec = 6'b111111;\n 12'd4014 : mem_out_dec = 6'b111111;\n 12'd4015 : mem_out_dec = 6'b111111;\n 12'd4016 : mem_out_dec = 6'b111111;\n 12'd4017 : mem_out_dec = 6'b111111;\n 12'd4018 : mem_out_dec = 6'b111111;\n 12'd4019 : mem_out_dec = 6'b111111;\n 12'd4020 : mem_out_dec = 6'b111111;\n 12'd4021 : mem_out_dec = 6'b111111;\n 12'd4022 : mem_out_dec = 6'b111111;\n 12'd4023 : mem_out_dec = 6'b111111;\n 12'd4024 : mem_out_dec = 6'b111111;\n 12'd4025 : mem_out_dec = 6'b111111;\n 12'd4026 : mem_out_dec = 6'b111111;\n 12'd4027 : mem_out_dec = 6'b111111;\n 12'd4028 : mem_out_dec = 6'b111111;\n 12'd4029 : mem_out_dec = 6'b111111;\n 12'd4030 : mem_out_dec = 6'b111111;\n 12'd4031 : mem_out_dec = 6'b111111;\n 12'd4032 : mem_out_dec = 6'b111111;\n 12'd4033 : mem_out_dec = 6'b111111;\n 12'd4034 : mem_out_dec = 6'b111111;\n 12'd4035 : mem_out_dec = 6'b111111;\n 12'd4036 : mem_out_dec = 6'b111111;\n 12'd4037 : mem_out_dec = 6'b111111;\n 12'd4038 : mem_out_dec = 6'b111111;\n 12'd4039 : mem_out_dec = 6'b111111;\n 12'd4040 : mem_out_dec = 6'b111111;\n 12'd4041 : mem_out_dec = 6'b111111;\n 12'd4042 : mem_out_dec = 6'b111111;\n 12'd4043 : mem_out_dec = 6'b111111;\n 12'd4044 : mem_out_dec = 6'b111111;\n 12'd4045 : mem_out_dec = 6'b111111;\n 12'd4046 : mem_out_dec = 6'b111111;\n 12'd4047 : mem_out_dec = 6'b111111;\n 12'd4048 : mem_out_dec = 6'b111111;\n 12'd4049 : mem_out_dec = 6'b111111;\n 12'd4050 : mem_out_dec = 6'b111111;\n 12'd4051 : mem_out_dec = 6'b111111;\n 12'd4052 : mem_out_dec = 6'b111111;\n 12'd4053 : mem_out_dec = 6'b111111;\n 12'd4054 : mem_out_dec = 6'b111111;\n 12'd4055 : mem_out_dec = 6'b111111;\n 12'd4056 : mem_out_dec = 6'b111111;\n 12'd4057 : mem_out_dec = 6'b111111;\n 12'd4058 : mem_out_dec = 6'b111111;\n 12'd4059 : mem_out_dec = 6'b111111;\n 12'd4060 : mem_out_dec = 6'b111111;\n 12'd4061 : mem_out_dec = 6'b111111;\n 12'd4062 : mem_out_dec = 6'b111111;\n 12'd4063 : mem_out_dec = 6'b111111;\n 12'd4064 : mem_out_dec = 6'b111111;\n 12'd4065 : mem_out_dec = 6'b111111;\n 12'd4066 : mem_out_dec = 6'b111111;\n 12'd4067 : mem_out_dec = 6'b111111;\n 12'd4068 : mem_out_dec = 6'b111111;\n 12'd4069 : mem_out_dec = 6'b111111;\n 12'd4070 : mem_out_dec = 6'b111111;\n 12'd4071 : mem_out_dec = 6'b111111;\n 12'd4072 : mem_out_dec = 6'b111111;\n 12'd4073 : mem_out_dec = 6'b111111;\n 12'd4074 : mem_out_dec = 6'b111111;\n 12'd4075 : mem_out_dec = 6'b111111;\n 12'd4076 : mem_out_dec = 6'b111111;\n 12'd4077 : mem_out_dec = 6'b111111;\n 12'd4078 : mem_out_dec = 6'b111111;\n 12'd4079 : mem_out_dec = 6'b111111;\n 12'd4080 : mem_out_dec = 6'b111111;\n 12'd4081 : mem_out_dec = 6'b111111;\n 12'd4082 : mem_out_dec = 6'b111111;\n 12'd4083 : mem_out_dec = 6'b111111;\n 12'd4084 : mem_out_dec = 6'b111111;\n 12'd4085 : mem_out_dec = 6'b111111;\n 12'd4086 : mem_out_dec = 6'b111111;\n 12'd4087 : mem_out_dec = 6'b111111;\n 12'd4088 : mem_out_dec = 6'b111111;\n 12'd4089 : mem_out_dec = 6'b111111;\n 12'd4090 : mem_out_dec = 6'b111111;\n 12'd4091 : mem_out_dec = 6'b111111;\n 12'd4092 : mem_out_dec = 6'b111111;\n 12'd4093 : mem_out_dec = 6'b111111;\n 12'd4094 : mem_out_dec = 6'b111111;\n 12'd4095 : mem_out_dec = 6'b111111;\n endcase\n end\n\n always @ (posedge clk) begin\n dec_cnt <= #TCQ mem_out_dec;\n end\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_rdlvl.v", "content": "//*****************************************************************************\n// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor: Xilinx\n// \\ \\ \\/ Version:\n// \\ \\ Application: MIG\n// / / Filename: ddr_phy_rdlvl.v\n// /___/ /\\ Date Last Modified: $Date: 2011/06/24 14:49:00 $\n// \\ \\ / \\ Date Created:\n// \\___\\/\\___\\\n//\n//Device: 7 Series\n//Design Name: DDR3 SDRAM\n//Purpose:\n// Read leveling Stage1 calibration logic\n// NOTES:\n// 1. Window detection with PRBS pattern.\n//Reference:\n//Revision History:\n//*****************************************************************************\n\n/******************************************************************************\n**$Id: ddr_phy_rdlvl.v,v 1.2 2011/06/24 14:49:00 mgeorge Exp $\n**$Date: 2011/06/24 14:49:00 $\n**$Author: mgeorge $\n**$Revision: 1.2 $\n**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_rdlvl.v,v $\n******************************************************************************/\n\n`timescale 1ps/1ps\n\n(* use_dsp48 = \"no\" *)\n\nmodule mig_7series_v4_0_ddr_phy_rdlvl #\n (\n parameter TCQ = 100, // clk->out delay (sim only)\n parameter nCK_PER_CLK = 2, // # of memory clocks per CLK\n parameter CLK_PERIOD = 3333, // Internal clock period (in ps)\n parameter DQ_WIDTH = 64, // # of DQ (data)\n parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))\n parameter DQS_WIDTH = 8, // # of DQS (strobe)\n parameter DRAM_WIDTH = 8, // # of DQ per DQS\n parameter RANKS = 1, // # of DRAM ranks\n parameter PER_BIT_DESKEW = \"ON\", // Enable per-bit DQ deskew\n parameter SIM_CAL_OPTION = \"NONE\", // Skip various calibration steps\n parameter DEBUG_PORT = \"OFF\", // Enable debug port\n parameter DRAM_TYPE = \"DDR3\", // Memory I/F type: \"DDR3\", \"DDR2\"\n parameter OCAL_EN = \"ON\",\n parameter IDELAY_ADJ = \"ON\",\n parameter PI_DIV2_INCDEC = \"TRUE\"\n )\n (\n input clk,\n input rst,\n // Calibration status, control signals\n input mpr_rdlvl_start,\n output mpr_rdlvl_done,\n output reg mpr_last_byte_done,\n output mpr_rnk_done,\n input rdlvl_stg1_start,\n output rdlvl_stg1_done /* synthesis syn_maxfan = 30 */,\n output rdlvl_stg1_rnk_done,\n output reg rdlvl_stg1_err,\n output mpr_rdlvl_err,\n output rdlvl_err,\n output reg rdlvl_prech_req,\n output rdlvl_last_byte_done,\n output reg rdlvl_assrt_common,\n input prech_done,\n input phy_if_empty,\n input [4:0] idelaye2_init_val,\n // Captured data in fabric clock domain\n input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,\n // Decrement initial Phaser_IN Fine tap delay\n input dqs_po_dec_done,\n input [5:0] pi_counter_read_val,\n // Stage 1 calibration outputs\n output reg pi_fine_dly_dec_done,\n output reg pi_en_stg2_f,\n output reg pi_stg2_f_incdec,\n output reg pi_stg2_load,\n output reg [5:0] pi_stg2_reg_l,\n output [DQS_CNT_WIDTH:0] pi_stg2_rdlvl_cnt,\n // To DQ IDELAY required to find left edge of\n // valid window\n output idelay_ce,\n output idelay_inc,\n input idelay_ld,\n input [DQS_CNT_WIDTH:0] wrcal_cnt,\n // Only output if Per-bit de-skew enabled\n output reg [5*RANKS*DQ_WIDTH-1:0] dlyval_dq,\n //output to prevent read during PI movement\n output reg rdlvl_pi_incdec,\n // Debug Port\n output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt,\n output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt,\n output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt,\n output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt,\n\n input dbg_idel_up_all,\n input dbg_idel_down_all,\n input dbg_idel_up_cpt,\n input dbg_idel_down_cpt,\n input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,\n input dbg_sel_all_idel_cpt,\n output [255:0] dbg_phy_rdlvl\n );\n\n // minimum time (in IDELAY taps) for which capture data must be stable for\n // algorithm to consider a valid data eye to be found. The read leveling\n // logic will ignore any window found smaller than this value. Limitations\n // on how small this number can be is determined by: (1) the algorithmic\n // limitation of how many taps wide the data eye can be (3 taps), and (2)\n // how wide regions of \"instability\" that occur around the edges of the\n // read valid window can be (i.e. need to be able to filter out \"false\"\n // windows that occur for a short # of taps around the edges of the true\n // data window, although with multi-sampling during read leveling, this is\n // not as much a concern) - the larger the value, the more protection\n // against \"false\" windows\n localparam MIN_EYE_SIZE = 16;\n\n // Length of calibration sequence (in # of words)\n localparam CAL_PAT_LEN = 8;\n // Read data shift register length\n localparam RD_SHIFT_LEN = CAL_PAT_LEN / (2*nCK_PER_CLK);\n\n // # of cycles required to perform read data shift register compare\n // This is defined as from the cycle the new data is loaded until\n // signal found_edge_r is valid\n localparam RD_SHIFT_COMP_DELAY = 5;\n\n // worst-case # of cycles to wait to ensure that both the SR and\n // PREV_SR shift registers have valid data, and that the comparison\n // of the two shift register values is valid. The \"+1\" at the end of\n // this equation is a fudge factor, I freely admit that\n localparam SR_VALID_DELAY = (2 * RD_SHIFT_LEN) + RD_SHIFT_COMP_DELAY + 1;\n\n // # of clock cycles to wait after changing tap value or read data MUX\n // to allow: (1) tap chain to settle, (2) for delayed input to propagate\n // thru ISERDES, (3) for the read data comparison logic to have time to\n // output the comparison of two consecutive samples of the settled read data\n // The minimum delay is 16 cycles, which should be good enough to handle all\n // three of the above conditions for the simulation-only case with a short\n // training pattern. For H/W (or for simulation with longer training\n // pattern), it will take longer to store and compare two consecutive\n // samples, and the value of this parameter will reflect that\n // put the maximum number for 2:1 mode\n localparam PIPE_WAIT_CNT = (nCK_PER_CLK == 2) ? 31 : (SR_VALID_DELAY < 8) ? 16\n : (SR_VALID_DELAY + 8);\n\n // # of read data samples to examine when detecting whether an edge has\n // occured during stage 1 calibration. Width of local param must be\n // changed as appropriate. Note that there are two counters used, each\n // counter can be changed independently of the other - they are used in\n // cascade to create a larger counter\n localparam [11:0] DETECT_EDGE_SAMPLE_CNT0 = 12'h001; //12'hFFF;\n localparam [11:0] DETECT_EDGE_SAMPLE_CNT1 = 12'h001; // 12'h1FF Must be > 0\n\n localparam [5:0] CAL1_IDLE = 6'h00;\n localparam [5:0] CAL1_NEW_DQS_WAIT = 6'h01;\n localparam [5:0] CAL1_STORE_FIRST_WAIT = 6'h02;\n localparam [5:0] CAL1_PAT_DETECT = 6'h03;\n localparam [5:0] CAL1_DQ_IDEL_TAP_INC = 6'h04;\n localparam [5:0] CAL1_DQ_IDEL_TAP_INC_WAIT = 6'h05;\n localparam [5:0] CAL1_DQ_IDEL_TAP_DEC = 6'h06;\n localparam [5:0] CAL1_DQ_IDEL_TAP_DEC_WAIT = 6'h07;\n localparam [5:0] CAL1_DETECT_EDGE = 6'h08;\n localparam [5:0] CAL1_IDEL_INC_CPT = 6'h09;\n localparam [5:0] CAL1_IDEL_INC_CPT_WAIT = 6'h0A;\n localparam [5:0] CAL1_CALC_IDEL = 6'h0B;\n localparam [5:0] CAL1_IDEL_DEC_CPT = 6'h0C;\n localparam [5:0] CAL1_IDEL_DEC_CPT_WAIT = 6'h0D;\n localparam [5:0] CAL1_NEXT_DQS = 6'h0E;\n localparam [5:0] CAL1_DONE = 6'h0F;\n localparam [5:0] CAL1_PB_STORE_FIRST_WAIT = 6'h10;\n localparam [5:0] CAL1_PB_DETECT_EDGE = 6'h11;\n localparam [5:0] CAL1_PB_INC_CPT = 6'h12;\n localparam [5:0] CAL1_PB_INC_CPT_WAIT = 6'h13;\n localparam [5:0] CAL1_PB_DEC_CPT_LEFT = 6'h14;\n localparam [5:0] CAL1_PB_DEC_CPT_LEFT_WAIT = 6'h15;\n localparam [5:0] CAL1_PB_DETECT_EDGE_DQ = 6'h16;\n localparam [5:0] CAL1_PB_INC_DQ = 6'h17;\n localparam [5:0] CAL1_PB_INC_DQ_WAIT = 6'h18;\n localparam [5:0] CAL1_PB_DEC_CPT = 6'h19;\n localparam [5:0] CAL1_PB_DEC_CPT_WAIT = 6'h1A;\n localparam [5:0] CAL1_REGL_LOAD = 6'h1B;\n localparam [5:0] CAL1_RDLVL_ERR = 6'h1C;\n localparam [5:0] CAL1_MPR_NEW_DQS_WAIT = 6'h1D;\n localparam [5:0] CAL1_VALID_WAIT = 6'h1E;\n localparam [5:0] CAL1_MPR_PAT_DETECT = 6'h1F;\n localparam [5:0] CAL1_NEW_DQS_PREWAIT = 6'h20;\n localparam [5:0] CAL1_RD_STOP_FOR_PI_INC = 6'h21;\n localparam [5:0] CAL1_CENTER_WAIT = 6'h22;\n\n integer a;\n integer b;\n integer d;\n integer e;\n integer f;\n integer h;\n integer g;\n integer i;\n integer j;\n integer k;\n integer l;\n integer m;\n integer n;\n integer r;\n integer p;\n integer q;\n integer s;\n integer t;\n integer u;\n integer w;\n integer ce_i;\n integer ce_rnk_i;\n integer aa;\n integer bb;\n integer cc;\n integer dd;\n genvar x;\n genvar z;\n\n reg [DQS_CNT_WIDTH:0] cal1_cnt_cpt_r;\n wire [DQS_CNT_WIDTH+2:0]cal1_cnt_cpt_timing;\n reg [DQS_CNT_WIDTH:0] cal1_cnt_cpt_timing_r;\n reg cal1_dq_idel_ce;\n reg cal1_dq_idel_inc;\n reg cal1_dlyce_cpt_r;\n reg cal1_dlyinc_cpt_r;\n reg cal1_dlyce_dq_r;\n reg cal1_dlyinc_dq_r;\n reg cal1_wait_cnt_en_r;\n reg [4:0] cal1_wait_cnt_r;\n reg cal1_wait_r;\n reg [DQ_WIDTH-1:0] dlyce_dq_r;\n reg dlyinc_dq_r;\n reg [4:0] dlyval_dq_reg_r [0:RANKS-1][0:DQ_WIDTH-1];\n reg cal1_prech_req_r;\n reg [5:0] cal1_state_r;\n reg [5:0] cal1_state_r1;\n reg [5:0] cal1_state_r2;\n reg [5:0] cal1_state_r3;\n reg [5:0] cnt_idel_dec_cpt_r;\n reg [3:0] cnt_shift_r;\n reg detect_edge_done_r;\n reg [5:0] right_edge_taps_r;\n reg [5:0] first_edge_taps_r;\n reg found_edge_r;\n reg found_first_edge_r;\n reg found_second_edge_r;\n reg found_stable_eye_r;\n reg found_stable_eye_last_r;\n reg found_edge_all_r;\n reg [5:0] tap_cnt_cpt_r;\n reg tap_limit_cpt_r;\n reg [4:0] idel_tap_cnt_dq_pb_r;\n reg idel_tap_limit_dq_pb_r;\n reg [DRAM_WIDTH-1:0] mux_rd_fall0_r;\n reg [DRAM_WIDTH-1:0] mux_rd_fall1_r;\n reg [DRAM_WIDTH-1:0] mux_rd_rise0_r;\n reg [DRAM_WIDTH-1:0] mux_rd_rise1_r;\n reg [DRAM_WIDTH-1:0] mux_rd_fall2_r;\n reg [DRAM_WIDTH-1:0] mux_rd_fall3_r;\n reg [DRAM_WIDTH-1:0] mux_rd_rise2_r;\n reg [DRAM_WIDTH-1:0] mux_rd_rise3_r;\n reg mux_rd_valid_r;\n reg new_cnt_cpt_r;\n reg [RD_SHIFT_LEN-1:0] old_sr_fall0_r [DRAM_WIDTH-1:0];\n reg [RD_SHIFT_LEN-1:0] old_sr_fall1_r [DRAM_WIDTH-1:0];\n reg [RD_SHIFT_LEN-1:0] old_sr_rise0_r [DRAM_WIDTH-1:0];\n reg [RD_SHIFT_LEN-1:0] old_sr_rise1_r [DRAM_WIDTH-1:0];\n reg [RD_SHIFT_LEN-1:0] old_sr_fall2_r [DRAM_WIDTH-1:0];\n reg [RD_SHIFT_LEN-1:0] old_sr_fall3_r [DRAM_WIDTH-1:0];\n reg [RD_SHIFT_LEN-1:0] old_sr_rise2_r [DRAM_WIDTH-1:0];\n reg [RD_SHIFT_LEN-1:0] old_sr_rise3_r [DRAM_WIDTH-1:0];\n reg [DRAM_WIDTH-1:0] old_sr_match_fall0_r;\n reg [DRAM_WIDTH-1:0] old_sr_match_fall1_r;\n reg [DRAM_WIDTH-1:0] old_sr_match_rise0_r;\n reg [DRAM_WIDTH-1:0] old_sr_match_rise1_r;\n reg [DRAM_WIDTH-1:0] old_sr_match_fall2_r;\n reg [DRAM_WIDTH-1:0] old_sr_match_fall3_r;\n reg [DRAM_WIDTH-1:0] old_sr_match_rise2_r;\n reg [DRAM_WIDTH-1:0] old_sr_match_rise3_r;\n reg [4:0] pb_cnt_eye_size_r [DRAM_WIDTH-1:0];\n reg [DRAM_WIDTH-1:0] pb_detect_edge_done_r;\n reg [DRAM_WIDTH-1:0] pb_found_edge_last_r;\n reg [DRAM_WIDTH-1:0] pb_found_edge_r;\n reg [DRAM_WIDTH-1:0] pb_found_first_edge_r;\n reg [DRAM_WIDTH-1:0] pb_found_stable_eye_r;\n reg [DRAM_WIDTH-1:0] pb_last_tap_jitter_r;\n reg pi_en_stg2_f_timing;\n reg pi_stg2_f_incdec_timing;\n reg pi_stg2_load_timing;\n reg [5:0] pi_stg2_reg_l_timing;\n reg [DRAM_WIDTH-1:0] prev_sr_diff_r;\n reg [RD_SHIFT_LEN-1:0] prev_sr_fall0_r [DRAM_WIDTH-1:0];\n reg [RD_SHIFT_LEN-1:0] prev_sr_fall1_r [DRAM_WIDTH-1:0];\n reg [RD_SHIFT_LEN-1:0] prev_sr_rise0_r [DRAM_WIDTH-1:0];\n reg [RD_SHIFT_LEN-1:0] prev_sr_rise1_r [DRAM_WIDTH-1:0];\n reg [RD_SHIFT_LEN-1:0] prev_sr_fall2_r [DRAM_WIDTH-1:0];\n reg [RD_SHIFT_LEN-1:0] prev_sr_fall3_r [DRAM_WIDTH-1:0];\n reg [RD_SHIFT_LEN-1:0] prev_sr_rise2_r [DRAM_WIDTH-1:0];\n reg [RD_SHIFT_LEN-1:0] prev_sr_rise3_r [DRAM_WIDTH-1:0];\n reg [DRAM_WIDTH-1:0] prev_sr_match_cyc2_r;\n reg [DRAM_WIDTH-1:0] prev_sr_match_fall0_r;\n reg [DRAM_WIDTH-1:0] prev_sr_match_fall1_r;\n reg [DRAM_WIDTH-1:0] prev_sr_match_rise0_r;\n reg [DRAM_WIDTH-1:0] prev_sr_match_rise1_r;\n reg [DRAM_WIDTH-1:0] prev_sr_match_fall2_r;\n reg [DRAM_WIDTH-1:0] prev_sr_match_fall3_r;\n reg [DRAM_WIDTH-1:0] prev_sr_match_rise2_r;\n reg [DRAM_WIDTH-1:0] prev_sr_match_rise3_r;\n wire [DQ_WIDTH-1:0] rd_data_rise0;\n wire [DQ_WIDTH-1:0] rd_data_fall0;\n wire [DQ_WIDTH-1:0] rd_data_rise1;\n wire [DQ_WIDTH-1:0] rd_data_fall1;\n wire [DQ_WIDTH-1:0] rd_data_rise2;\n wire [DQ_WIDTH-1:0] rd_data_fall2;\n wire [DQ_WIDTH-1:0] rd_data_rise3;\n wire [DQ_WIDTH-1:0] rd_data_fall3;\n reg samp_cnt_done_r;\n reg samp_edge_cnt0_en_r;\n reg [11:0] samp_edge_cnt0_r;\n reg samp_edge_cnt1_en_r;\n reg [11:0] samp_edge_cnt1_r;\n reg [DQS_CNT_WIDTH:0] rd_mux_sel_r;\n reg [5:0] second_edge_taps_r;\n reg [RD_SHIFT_LEN-1:0] sr_fall0_r [DRAM_WIDTH-1:0];\n reg [RD_SHIFT_LEN-1:0] sr_fall1_r [DRAM_WIDTH-1:0];\n reg [RD_SHIFT_LEN-1:0] sr_rise0_r [DRAM_WIDTH-1:0];\n reg [RD_SHIFT_LEN-1:0] sr_rise1_r [DRAM_WIDTH-1:0];\n reg [RD_SHIFT_LEN-1:0] sr_fall2_r [DRAM_WIDTH-1:0];\n reg [RD_SHIFT_LEN-1:0] sr_fall3_r [DRAM_WIDTH-1:0];\n reg [RD_SHIFT_LEN-1:0] sr_rise2_r [DRAM_WIDTH-1:0];\n reg [RD_SHIFT_LEN-1:0] sr_rise3_r [DRAM_WIDTH-1:0];\n reg store_sr_r;\n reg store_sr_req_pulsed_r;\n reg store_sr_req_r;\n reg sr_valid_r;\n reg sr_valid_r1;\n reg sr_valid_r2;\n reg [DRAM_WIDTH-1:0] old_sr_diff_r;\n reg [DRAM_WIDTH-1:0] old_sr_match_cyc2_r;\n reg pat0_data_match_r;\n reg pat1_data_match_r;\n wire pat_data_match_r;\n wire [RD_SHIFT_LEN-1:0] pat0_fall0 [3:0];\n wire [RD_SHIFT_LEN-1:0] pat0_fall1 [3:0];\n wire [RD_SHIFT_LEN-1:0] pat0_fall2 [3:0];\n wire [RD_SHIFT_LEN-1:0] pat0_fall3 [3:0];\n wire [RD_SHIFT_LEN-1:0] pat1_fall0 [3:0];\n wire [RD_SHIFT_LEN-1:0] pat1_fall1 [3:0];\n wire [RD_SHIFT_LEN-1:0] pat1_fall2 [3:0];\n wire [RD_SHIFT_LEN-1:0] pat1_fall3 [3:0];\n reg [DRAM_WIDTH-1:0] pat0_match_fall0_r;\n reg pat0_match_fall0_and_r;\n reg [DRAM_WIDTH-1:0] pat0_match_fall1_r;\n reg pat0_match_fall1_and_r;\n reg [DRAM_WIDTH-1:0] pat0_match_fall2_r;\n reg pat0_match_fall2_and_r;\n reg [DRAM_WIDTH-1:0] pat0_match_fall3_r;\n reg pat0_match_fall3_and_r;\n reg [DRAM_WIDTH-1:0] pat0_match_rise0_r;\n reg pat0_match_rise0_and_r;\n reg [DRAM_WIDTH-1:0] pat0_match_rise1_r;\n reg pat0_match_rise1_and_r;\n reg [DRAM_WIDTH-1:0] pat0_match_rise2_r;\n reg pat0_match_rise2_and_r;\n reg [DRAM_WIDTH-1:0] pat0_match_rise3_r;\n reg pat0_match_rise3_and_r;\n reg [DRAM_WIDTH-1:0] pat1_match_fall0_r;\n reg pat1_match_fall0_and_r;\n reg [DRAM_WIDTH-1:0] pat1_match_fall1_r;\n reg pat1_match_fall1_and_r;\n reg [DRAM_WIDTH-1:0] pat1_match_fall2_r;\n reg pat1_match_fall2_and_r;\n reg [DRAM_WIDTH-1:0] pat1_match_fall3_r;\n reg pat1_match_fall3_and_r;\n reg [DRAM_WIDTH-1:0] pat1_match_rise0_r;\n reg pat1_match_rise0_and_r;\n reg [DRAM_WIDTH-1:0] pat1_match_rise1_r;\n reg pat1_match_rise1_and_r;\n reg [DRAM_WIDTH-1:0] pat1_match_rise2_r;\n reg pat1_match_rise2_and_r;\n reg [DRAM_WIDTH-1:0] pat1_match_rise3_r;\n reg pat1_match_rise3_and_r;\n reg [4:0] idelay_tap_cnt_r [0:RANKS-1][0:DQS_WIDTH-1];\n reg [5*DQS_WIDTH*RANKS-1:0] idelay_tap_cnt_w;\n reg [4:0] idelay_tap_cnt_slice_r;\n reg idelay_tap_limit_r;\n\n wire [RD_SHIFT_LEN-1:0] pat0_rise0 [3:0];\n wire [RD_SHIFT_LEN-1:0] pat0_rise1 [3:0];\n wire [RD_SHIFT_LEN-1:0] pat0_rise2 [3:0];\n wire [RD_SHIFT_LEN-1:0] pat0_rise3 [3:0];\n wire [RD_SHIFT_LEN-1:0] pat1_rise0 [3:0];\n wire [RD_SHIFT_LEN-1:0] pat1_rise1 [3:0];\n wire [RD_SHIFT_LEN-1:0] pat1_rise2 [3:0];\n wire [RD_SHIFT_LEN-1:0] pat1_rise3 [3:0];\n\n wire [RD_SHIFT_LEN-1:0] idel_pat0_rise0 [3:0];\n wire [RD_SHIFT_LEN-1:0] idel_pat0_fall0 [3:0];\n wire [RD_SHIFT_LEN-1:0] idel_pat0_rise1 [3:0];\n wire [RD_SHIFT_LEN-1:0] idel_pat0_fall1 [3:0];\n wire [RD_SHIFT_LEN-1:0] idel_pat0_rise2 [3:0];\n wire [RD_SHIFT_LEN-1:0] idel_pat0_fall2 [3:0];\n wire [RD_SHIFT_LEN-1:0] idel_pat0_rise3 [3:0];\n wire [RD_SHIFT_LEN-1:0] idel_pat0_fall3 [3:0];\n wire [RD_SHIFT_LEN-1:0] idel_pat1_rise0 [3:0];\n wire [RD_SHIFT_LEN-1:0] idel_pat1_fall0 [3:0];\n wire [RD_SHIFT_LEN-1:0] idel_pat1_rise1 [3:0];\n wire [RD_SHIFT_LEN-1:0] idel_pat1_fall1 [3:0];\n wire [RD_SHIFT_LEN-1:0] idel_pat1_rise2 [3:0];\n wire [RD_SHIFT_LEN-1:0] idel_pat1_fall2 [3:0];\n wire [RD_SHIFT_LEN-1:0] idel_pat1_rise3 [3:0];\n wire [RD_SHIFT_LEN-1:0] idel_pat1_fall3 [3:0];\n\n reg [DRAM_WIDTH-1:0] idel_pat0_match_rise0_r;\n reg [DRAM_WIDTH-1:0] idel_pat0_match_fall0_r;\n reg [DRAM_WIDTH-1:0] idel_pat0_match_rise1_r;\n reg [DRAM_WIDTH-1:0] idel_pat0_match_fall1_r;\n reg [DRAM_WIDTH-1:0] idel_pat0_match_rise2_r;\n reg [DRAM_WIDTH-1:0] idel_pat0_match_fall2_r;\n reg [DRAM_WIDTH-1:0] idel_pat0_match_rise3_r;\n reg [DRAM_WIDTH-1:0] idel_pat0_match_fall3_r;\n\n reg [DRAM_WIDTH-1:0] idel_pat1_match_rise0_r;\n reg [DRAM_WIDTH-1:0] idel_pat1_match_fall0_r;\n reg [DRAM_WIDTH-1:0] idel_pat1_match_rise1_r;\n reg [DRAM_WIDTH-1:0] idel_pat1_match_fall1_r;\n reg [DRAM_WIDTH-1:0] idel_pat1_match_rise2_r;\n reg [DRAM_WIDTH-1:0] idel_pat1_match_fall2_r;\n reg [DRAM_WIDTH-1:0] idel_pat1_match_rise3_r;\n reg [DRAM_WIDTH-1:0] idel_pat1_match_fall3_r;\n\n reg idel_pat0_match_rise0_and_r;\n reg idel_pat0_match_fall0_and_r;\n reg idel_pat0_match_rise1_and_r;\n reg idel_pat0_match_fall1_and_r;\n reg idel_pat0_match_rise2_and_r;\n reg idel_pat0_match_fall2_and_r;\n reg idel_pat0_match_rise3_and_r;\n reg idel_pat0_match_fall3_and_r;\n\n reg idel_pat1_match_rise0_and_r;\n reg idel_pat1_match_fall0_and_r;\n reg idel_pat1_match_rise1_and_r;\n reg idel_pat1_match_fall1_and_r;\n reg idel_pat1_match_rise2_and_r;\n reg idel_pat1_match_fall2_and_r;\n reg idel_pat1_match_rise3_and_r;\n reg idel_pat1_match_fall3_and_r;\n\n reg idel_pat0_data_match_r;\n reg idel_pat1_data_match_r;\n\n reg idel_pat_data_match;\n reg idel_pat_data_match_r;\n\n reg [4:0] idel_dec_cnt;\n\n reg [5:0] rdlvl_dqs_tap_cnt_r [0:RANKS-1][0:DQS_WIDTH-1];\n reg [1:0] rnk_cnt_r;\n reg rdlvl_rank_done_r;\n\n reg [3:0] done_cnt;\n reg [1:0] regl_rank_cnt;\n reg [DQS_CNT_WIDTH:0] regl_dqs_cnt;\n reg [DQS_CNT_WIDTH:0] regl_dqs_cnt_r;\n wire [DQS_CNT_WIDTH+2:0]regl_dqs_cnt_timing;\n reg regl_rank_done_r;\n reg rdlvl_stg1_start_r;\n\n reg dqs_po_dec_done_r1;\n reg dqs_po_dec_done_r2;\n reg fine_dly_dec_done_r1;\n reg fine_dly_dec_done_r2;\n reg fine_dly_dec_done_r3;\n reg fine_dly_dec_done_r4;\n reg [3:0] wait_cnt_r;\n reg [5:0] pi_rdval_cnt;\n reg pi_cnt_dec;\n\n reg mpr_valid_r;\n reg mpr_valid_r1;\n reg mpr_valid_r2;\n reg mpr_rd_rise0_prev_r;\n reg mpr_rd_fall0_prev_r;\n reg mpr_rd_rise1_prev_r;\n reg mpr_rd_fall1_prev_r;\n reg mpr_rd_rise2_prev_r;\n reg mpr_rd_fall2_prev_r;\n reg mpr_rd_rise3_prev_r;\n reg mpr_rd_fall3_prev_r;\n reg mpr_rdlvl_done_r;\n reg mpr_rdlvl_done_r1;\n reg mpr_rdlvl_done_r2;\n reg mpr_rdlvl_start_r;\n reg mpr_rank_done_r;\n reg [2:0] stable_idel_cnt;\n reg inhibit_edge_detect_r;\n reg idel_pat_detect_valid_r;\n reg idel_mpr_pat_detect_r;\n reg mpr_pat_detect_r;\n reg mpr_dec_cpt_r;\n reg idel_adj_inc; //IDELAY adjustment\n wire [1:0] idelay_adj;\n wire pb_detect_edge_setup;\n wire pb_detect_edge;\n // Debug\n reg [6*DQS_WIDTH-1:0] dbg_cpt_first_edge_taps;\n reg [6*DQS_WIDTH-1:0] dbg_cpt_second_edge_taps;\n reg [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt_w;\n reg rdlvl_stg1_done_int;\n reg rdlvl_stg1_done_int_r1, rdlvl_stg1_done_int_r2, rdlvl_stg1_done_int_r3;\n reg rdlvl_last_byte_done_int;\n reg rdlvl_last_byte_done_int_r1, rdlvl_last_byte_done_int_r2, rdlvl_last_byte_done_int_r3;\n\n\n //IDELAY adjustment setting for -1\n //2'b10 : IDELAY - 1\n //2'b01 : IDELAY + 1\n //2'b00 : No IDELAY adjustment\n assign idelay_adj = (IDELAY_ADJ == \"ON\") ? 2'b10: 2'b00;\n\n //***************************************************************************\n // Debug\n //***************************************************************************\n\n always @(*) begin\n for (d = 0; d < RANKS; d = d + 1) begin\n for (e = 0; e < DQS_WIDTH; e = e + 1) begin\n idelay_tap_cnt_w[(5*e+5*DQS_WIDTH*d)+:5] = idelay_tap_cnt_r[d][e];\n dbg_cpt_tap_cnt_w[(6*e+6*DQS_WIDTH*d)+:6] = rdlvl_dqs_tap_cnt_r[d][e];\n end\n end\n end\n\n assign mpr_rdlvl_err = rdlvl_stg1_err & (!mpr_rdlvl_done);\n assign rdlvl_err = rdlvl_stg1_err & (mpr_rdlvl_done);\n\n\n assign dbg_phy_rdlvl[0] = rdlvl_stg1_start;\n assign dbg_phy_rdlvl[1] = pat_data_match_r;\n assign dbg_phy_rdlvl[2] = mux_rd_valid_r;\n assign dbg_phy_rdlvl[3] = idelay_tap_limit_r;\n assign dbg_phy_rdlvl[8:4] = 'b0;\n assign dbg_phy_rdlvl[14:9] = cal1_state_r[5:0];\n assign dbg_phy_rdlvl[20:15] = cnt_idel_dec_cpt_r;\n assign dbg_phy_rdlvl[21] = found_first_edge_r;\n assign dbg_phy_rdlvl[22] = found_second_edge_r;\n assign dbg_phy_rdlvl[23] = found_edge_r;\n assign dbg_phy_rdlvl[24] = store_sr_r;\n // [40:25] previously used for sr, old_sr shift registers. If connecting\n // these signals again, don't forget to parameterize based on RD_SHIFT_LEN\n assign dbg_phy_rdlvl[40:25] = 'b0;\n assign dbg_phy_rdlvl[41] = sr_valid_r;\n assign dbg_phy_rdlvl[42] = found_stable_eye_r;\n assign dbg_phy_rdlvl[48:43] = tap_cnt_cpt_r;\n assign dbg_phy_rdlvl[54:49] = first_edge_taps_r;\n assign dbg_phy_rdlvl[60:55] = second_edge_taps_r;\n assign dbg_phy_rdlvl[64:61] = cal1_cnt_cpt_timing_r;\n assign dbg_phy_rdlvl[65] = cal1_dlyce_cpt_r;\n assign dbg_phy_rdlvl[66] = cal1_dlyinc_cpt_r;\n assign dbg_phy_rdlvl[67] = found_edge_r;\n assign dbg_phy_rdlvl[68] = found_first_edge_r;\n assign dbg_phy_rdlvl[73:69] = 'b0;\n assign dbg_phy_rdlvl[74] = idel_pat_data_match;\n assign dbg_phy_rdlvl[75] = idel_pat0_data_match_r;\n assign dbg_phy_rdlvl[76] = idel_pat1_data_match_r;\n assign dbg_phy_rdlvl[77] = pat0_data_match_r;\n assign dbg_phy_rdlvl[78] = pat1_data_match_r;\n assign dbg_phy_rdlvl[79+:5*DQS_WIDTH*RANKS] = idelay_tap_cnt_w;\n assign dbg_phy_rdlvl[170+:8] = mux_rd_rise0_r;\n assign dbg_phy_rdlvl[178+:8] = mux_rd_fall0_r;\n assign dbg_phy_rdlvl[186+:8] = mux_rd_rise1_r;\n assign dbg_phy_rdlvl[194+:8] = mux_rd_fall1_r;\n assign dbg_phy_rdlvl[202+:8] = mux_rd_rise2_r;\n assign dbg_phy_rdlvl[210+:8] = mux_rd_fall2_r;\n assign dbg_phy_rdlvl[218+:8] = mux_rd_rise3_r;\n assign dbg_phy_rdlvl[226+:8] = mux_rd_fall3_r;\n\n //***************************************************************************\n // Debug output\n //***************************************************************************\n\n // CPT taps\n assign dbg_cpt_first_edge_cnt = dbg_cpt_first_edge_taps;\n assign dbg_cpt_second_edge_cnt = dbg_cpt_second_edge_taps;\n assign dbg_cpt_tap_cnt = dbg_cpt_tap_cnt_w;\n assign dbg_dq_idelay_tap_cnt = idelay_tap_cnt_w;\n\n // Record first and second edges found during CPT calibration\n\n generate\n always @(posedge clk)\n if (rst || (rdlvl_stg1_start && ~rdlvl_stg1_start_r)) begin\n dbg_cpt_first_edge_taps <= #TCQ 'b0;\n dbg_cpt_second_edge_taps <= #TCQ 'b0;\n end else if ((SIM_CAL_OPTION == \"FAST_CAL\") & (cal1_state_r1 == CAL1_CALC_IDEL)) begin\n //for (ce_rnk_i = 0; ce_rnk_i < RANKS; ce_rnk_i = ce_rnk_i + 1) begin: gen_dbg_cpt_rnk\n for (ce_i = 0; ce_i < DQS_WIDTH; ce_i = ce_i + 1) begin: gen_dbg_cpt_edge\n if (found_first_edge_r)\n dbg_cpt_first_edge_taps[(6*ce_i)+:6]\n <= #TCQ first_edge_taps_r;\n if (found_second_edge_r)\n dbg_cpt_second_edge_taps[(6*ce_i)+:6]\n <= #TCQ second_edge_taps_r;\n end\n //end\n end else if (cal1_state_r == CAL1_CALC_IDEL) begin\n // Record tap counts of first and second edge edges during\n // CPT calibration for each DQS group. If neither edge has\n // been found, then those taps will remain 0\n if (found_first_edge_r)\n dbg_cpt_first_edge_taps[((cal1_cnt_cpt_timing <<2) + (cal1_cnt_cpt_timing <<1))+:6]\n <= #TCQ first_edge_taps_r;\n if (found_second_edge_r)\n dbg_cpt_second_edge_taps[((cal1_cnt_cpt_timing <<2) + (cal1_cnt_cpt_timing <<1))+:6]\n <= #TCQ second_edge_taps_r;\n end\n endgenerate\n\n assign rdlvl_stg1_rnk_done = rdlvl_rank_done_r;// || regl_rank_done_r;\n assign mpr_rnk_done = mpr_rank_done_r;\n assign mpr_rdlvl_done = ((DRAM_TYPE == \"DDR3\") && (OCAL_EN == \"ON\")) ? //&& (SIM_CAL_OPTION == \"NONE\")\n mpr_rdlvl_done_r : 1'b1;\n\n //**************************************************************************\n // DQS count to hard PHY during write calibration using Phaser_OUT Stage2\n // coarse delay\n //**************************************************************************\n assign pi_stg2_rdlvl_cnt = (((PI_DIV2_INCDEC == \"TRUE\") && (cal1_state_r3 == CAL1_REGL_LOAD)) || ((PI_DIV2_INCDEC == \"FALSE\") && (cal1_state_r == CAL1_REGL_LOAD))) ? regl_dqs_cnt_r : cal1_cnt_cpt_r;\n assign rdlvl_stg1_done = (PI_DIV2_INCDEC == \"TRUE\") ? rdlvl_stg1_done_int_r3 : rdlvl_stg1_done_int;\n assign rdlvl_last_byte_done = (PI_DIV2_INCDEC == \"TRUE\") ? rdlvl_last_byte_done_int_r3 : rdlvl_last_byte_done_int;\n\n always @ (posedge clk) begin\n rdlvl_stg1_done_int_r1 <= #TCQ rdlvl_stg1_done_int;\n rdlvl_stg1_done_int_r2 <= #TCQ rdlvl_stg1_done_int_r1;\n rdlvl_stg1_done_int_r3 <= #TCQ rdlvl_stg1_done_int_r2;\n rdlvl_last_byte_done_int_r1 <= #TCQ rdlvl_last_byte_done_int;\n rdlvl_last_byte_done_int_r2 <= #TCQ rdlvl_last_byte_done_int_r1;\n rdlvl_last_byte_done_int_r3 <= #TCQ rdlvl_last_byte_done_int_r2;\n end\n\n assign idelay_ce = cal1_dq_idel_ce;\n assign idelay_inc = cal1_dq_idel_inc;\n\n //***************************************************************************\n // Assert calib_in_common in FAST_CAL mode for IDELAY tap increments to all\n // DQs simultaneously\n //***************************************************************************\n\n always @(posedge clk) begin\n if (rst)\n rdlvl_assrt_common <= #TCQ 1'b0;\n else if ((SIM_CAL_OPTION == \"FAST_CAL\") & rdlvl_stg1_start &\n !rdlvl_stg1_start_r)\n rdlvl_assrt_common <= #TCQ 1'b1;\n else if (!idel_pat_data_match_r & idel_pat_data_match)\n rdlvl_assrt_common <= #TCQ 1'b0;\n end\n\n //***************************************************************************\n // Data mux to route appropriate bit to calibration logic - i.e. calibration\n // is done sequentially, one bit (or DQS group) at a time\n //***************************************************************************\n\n generate\n if (nCK_PER_CLK == 4) begin: rd_data_div4_logic_clk\n assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];\n assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];\n assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];\n assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];\n assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH];\n assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH];\n assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH];\n assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH];\n end else begin: rd_data_div2_logic_clk\n assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];\n assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];\n assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];\n assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];\n end\n endgenerate\n\n always @(posedge clk) begin\n rd_mux_sel_r <= #TCQ cal1_cnt_cpt_r;\n end\n\n // Register outputs for improved timing.\n // NOTE: Will need to change when per-bit DQ deskew is supported.\n // Currenly all bits in DQS group are checked in aggregate\n generate\n genvar mux_i;\n for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd\n always @(posedge clk) begin\n mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r +\n mux_i];\n mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r +\n mux_i];\n mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r +\n mux_i];\n mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r +\n mux_i];\n mux_rd_rise2_r[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r +\n mux_i];\n mux_rd_fall2_r[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r +\n mux_i];\n mux_rd_rise3_r[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r +\n mux_i];\n mux_rd_fall3_r[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r +\n mux_i];\n end\n end\n endgenerate\n\n //***************************************************************************\n // MPR Read Leveling\n //***************************************************************************\n\n // storing the previous read data for checking later. Only bit 0 is used\n // since MPR contents (01010101) are available generally on DQ[0] per\n // JEDEC spec.\n always @(posedge clk)begin\n if ((cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) ||\n ((cal1_state_r == CAL1_MPR_PAT_DETECT) && (idel_pat_detect_valid_r)))begin\n mpr_rd_rise0_prev_r <= #TCQ mux_rd_rise0_r[0];\n mpr_rd_fall0_prev_r <= #TCQ mux_rd_fall0_r[0];\n mpr_rd_rise1_prev_r <= #TCQ mux_rd_rise1_r[0];\n mpr_rd_fall1_prev_r <= #TCQ mux_rd_fall1_r[0];\n mpr_rd_rise2_prev_r <= #TCQ mux_rd_rise2_r[0];\n mpr_rd_fall2_prev_r <= #TCQ mux_rd_fall2_r[0];\n mpr_rd_rise3_prev_r <= #TCQ mux_rd_rise3_r[0];\n mpr_rd_fall3_prev_r <= #TCQ mux_rd_fall3_r[0];\n end\n end\n\n generate\n if (nCK_PER_CLK == 4) begin: mpr_4to1\n // changed stable count of 2 IDELAY taps at 78 ps resolution\n always @(posedge clk) begin\n if (rst | (cal1_state_r == CAL1_NEW_DQS_PREWAIT) |\n //(cal1_state_r == CAL1_DETECT_EDGE) |\n (mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) |\n (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) |\n (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) |\n (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0]) |\n (mpr_rd_rise2_prev_r != mux_rd_rise2_r[0]) |\n (mpr_rd_fall2_prev_r != mux_rd_fall2_r[0]) |\n (mpr_rd_rise3_prev_r != mux_rd_rise3_r[0]) |\n (mpr_rd_fall3_prev_r != mux_rd_fall3_r[0]))\n stable_idel_cnt <= #TCQ 3'd0;\n else if ((|idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]) &\n ((cal1_state_r == CAL1_MPR_PAT_DETECT) &\n (idel_pat_detect_valid_r))) begin\n if ((mpr_rd_rise0_prev_r == mux_rd_rise0_r[0]) &\n (mpr_rd_fall0_prev_r == mux_rd_fall0_r[0]) &\n (mpr_rd_rise1_prev_r == mux_rd_rise1_r[0]) &\n (mpr_rd_fall1_prev_r == mux_rd_fall1_r[0]) &\n (mpr_rd_rise2_prev_r == mux_rd_rise2_r[0]) &\n (mpr_rd_fall2_prev_r == mux_rd_fall2_r[0]) &\n (mpr_rd_rise3_prev_r == mux_rd_rise3_r[0]) &\n (mpr_rd_fall3_prev_r == mux_rd_fall3_r[0]) &\n (stable_idel_cnt < 3'd2))\n stable_idel_cnt <= #TCQ stable_idel_cnt + 1;\n end\n end\n\n always @(posedge clk) begin\n if (rst |\n (mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r &\n mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r &\n mpr_rd_rise2_prev_r & ~mpr_rd_fall2_prev_r &\n mpr_rd_rise3_prev_r & ~mpr_rd_fall3_prev_r))\n inhibit_edge_detect_r <= 1'b1;\n // Wait for settling time after idelay tap increment before\n // de-asserting inhibit_edge_detect_r\n else if ((cal1_state_r == CAL1_MPR_PAT_DETECT) &\n (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] > 5'd1) &\n (~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r &\n ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r &\n ~mpr_rd_rise2_prev_r & mpr_rd_fall2_prev_r &\n ~mpr_rd_rise3_prev_r & mpr_rd_fall3_prev_r))\n inhibit_edge_detect_r <= 1'b0;\n end\n\n //checking for transition from 01010101 to 10101010\n always @(posedge clk)begin\n if (rst | (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) |\n inhibit_edge_detect_r)\n idel_mpr_pat_detect_r <= #TCQ 1'b0;\n // 10101010 is not the correct pattern\n else if ((mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r &\n mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r &\n mpr_rd_rise2_prev_r & ~mpr_rd_fall2_prev_r &\n mpr_rd_rise3_prev_r & ~mpr_rd_fall3_prev_r) ||\n ((stable_idel_cnt < 3'd2) & (cal1_state_r == CAL1_MPR_PAT_DETECT)\n && (idel_pat_detect_valid_r)))\n //|| (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] < 5'd2))\n idel_mpr_pat_detect_r <= #TCQ 1'b0;\n // 01010101 to 10101010 is the correct transition\n else if ((~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r &\n ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r &\n ~mpr_rd_rise2_prev_r & mpr_rd_fall2_prev_r &\n ~mpr_rd_rise3_prev_r & mpr_rd_fall3_prev_r) &\n (stable_idel_cnt == 3'd2) &\n ((mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) ||\n (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) ||\n (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) ||\n (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0]) ||\n (mpr_rd_rise2_prev_r != mux_rd_rise2_r[0]) ||\n (mpr_rd_fall2_prev_r != mux_rd_fall2_r[0]) ||\n (mpr_rd_rise3_prev_r != mux_rd_rise3_r[0]) ||\n (mpr_rd_fall3_prev_r != mux_rd_fall3_r[0])))\n idel_mpr_pat_detect_r <= #TCQ 1'b1;\n end\n end else if (nCK_PER_CLK == 2) begin: mpr_2to1\n // changed stable count of 2 IDELAY taps at 78 ps resolution\n always @(posedge clk) begin\n if (rst | (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) |\n (mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) |\n (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) |\n (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) |\n (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0]))\n stable_idel_cnt <= #TCQ 3'd0;\n else if ((idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] > 5'd0) &\n ((cal1_state_r == CAL1_MPR_PAT_DETECT) &\n (idel_pat_detect_valid_r))) begin\n if ((mpr_rd_rise0_prev_r == mux_rd_rise0_r[0]) &\n (mpr_rd_fall0_prev_r == mux_rd_fall0_r[0]) &\n (mpr_rd_rise1_prev_r == mux_rd_rise1_r[0]) &\n (mpr_rd_fall1_prev_r == mux_rd_fall1_r[0]) &\n (stable_idel_cnt < 3'd2))\n stable_idel_cnt <= #TCQ stable_idel_cnt + 1;\n end\n end\n\n always @(posedge clk) begin\n if (rst |\n (mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r &\n mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r))\n inhibit_edge_detect_r <= 1'b1;\n else if ((cal1_state_r == CAL1_MPR_PAT_DETECT) &\n (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] > 5'd1) &\n (~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r &\n ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r))\n inhibit_edge_detect_r <= 1'b0;\n end\n\n //checking for transition from 01010101 to 10101010\n always @(posedge clk)begin\n if (rst | (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) |\n inhibit_edge_detect_r)\n idel_mpr_pat_detect_r <= #TCQ 1'b0;\n // 1010 is not the correct pattern\n else if ((mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r &\n mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r) ||\n ((stable_idel_cnt < 3'd2) & (cal1_state_r == CAL1_MPR_PAT_DETECT)\n & (idel_pat_detect_valid_r)))\n // ||(idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] < 5'd2))\n idel_mpr_pat_detect_r <= #TCQ 1'b0;\n // 0101 to 1010 is the correct transition\n else if ((~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r &\n ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r) &\n (stable_idel_cnt == 3'd2) &\n ((mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) ||\n (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) ||\n (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) ||\n (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0])))\n idel_mpr_pat_detect_r <= #TCQ 1'b1;\n end\n end\n endgenerate\n\n\n\n // Registered signal indicates when mux_rd_rise/fall_r is valid\n always @(posedge clk)\n mux_rd_valid_r <= #TCQ ~phy_if_empty;\n\n\n //***************************************************************************\n // Decrement initial Phaser_IN fine delay value before proceeding with\n // read calibration\n //***************************************************************************\n\n always @(posedge clk) begin\n dqs_po_dec_done_r1 <= #TCQ dqs_po_dec_done;\n dqs_po_dec_done_r2 <= #TCQ dqs_po_dec_done_r1;\n fine_dly_dec_done_r2 <= #TCQ fine_dly_dec_done_r1;\n fine_dly_dec_done_r3 <= #TCQ fine_dly_dec_done_r2;\n fine_dly_dec_done_r4 <= #TCQ fine_dly_dec_done_r3;\n if (PI_DIV2_INCDEC == \"TRUE\")\n pi_fine_dly_dec_done <= #TCQ fine_dly_dec_done_r4;\n else\n pi_fine_dly_dec_done <= #TCQ fine_dly_dec_done_r2;\n end\n\n always @(posedge clk) begin\n if (rst || pi_cnt_dec)\n wait_cnt_r <= #TCQ 'd8;\n else if (dqs_po_dec_done_r2 && (wait_cnt_r > 'd0))\n wait_cnt_r <= #TCQ wait_cnt_r - 1;\n end\n\n always @(posedge clk) begin\n if (rst) begin\n pi_rdval_cnt <= #TCQ 'd0;\n end else if (dqs_po_dec_done_r1 && ~dqs_po_dec_done_r2) begin\n pi_rdval_cnt <= #TCQ pi_counter_read_val;\n end else if (pi_rdval_cnt > 'd0) begin\n if (pi_cnt_dec)\n pi_rdval_cnt <= #TCQ pi_rdval_cnt - 1;\n else\n pi_rdval_cnt <= #TCQ pi_rdval_cnt;\n end else if (pi_rdval_cnt == 'd0) begin\n pi_rdval_cnt <= #TCQ pi_rdval_cnt;\n end\n end\n\n always @(posedge clk) begin\n if (rst || (pi_rdval_cnt == 'd0))\n pi_cnt_dec <= #TCQ 1'b0;\n else if (dqs_po_dec_done_r2 && (pi_rdval_cnt > 'd0)\n && (wait_cnt_r == 'd1))\n pi_cnt_dec <= #TCQ 1'b1;\n else\n pi_cnt_dec <= #TCQ 1'b0;\n end\n\n always @(posedge clk) begin\n if (rst) begin\n fine_dly_dec_done_r1 <= #TCQ 1'b0;\n end else if (((pi_cnt_dec == 'd1) && (pi_rdval_cnt == 'd1)) ||\n (dqs_po_dec_done_r2 && (pi_rdval_cnt == 'd0))) begin\n fine_dly_dec_done_r1 <= #TCQ 1'b1;\n end\n end\n\n //***************************************************************************\n // Demultiplexor to control Phaser_IN delay values\n //***************************************************************************\n\n // Read DQS\n always @(posedge clk) begin\n if (rst) begin\n pi_en_stg2_f_timing <= #TCQ 'b0;\n pi_stg2_f_incdec_timing <= #TCQ 'b0;\n end else if (pi_cnt_dec) begin\n pi_en_stg2_f_timing <= #TCQ 'b1;\n pi_stg2_f_incdec_timing <= #TCQ 'b0;\n end else if (cal1_dlyce_cpt_r) begin\n if ((SIM_CAL_OPTION == \"NONE\") ||\n (SIM_CAL_OPTION == \"FAST_WIN_DETECT\")) begin\n // Change only specified DQS\n pi_en_stg2_f_timing <= #TCQ 1'b1;\n pi_stg2_f_incdec_timing <= #TCQ cal1_dlyinc_cpt_r;\n end else if (SIM_CAL_OPTION == \"FAST_CAL\") begin\n // if simulating, and \"shortcuts\" for calibration enabled, apply\n // results to all DQSs (i.e. assume same delay on all\n // DQSs).\n pi_en_stg2_f_timing <= #TCQ 1'b1;\n pi_stg2_f_incdec_timing <= #TCQ cal1_dlyinc_cpt_r;\n end\n end else begin\n pi_en_stg2_f_timing <= #TCQ 'b0;\n pi_stg2_f_incdec_timing <= #TCQ 'b0;\n end\n end\n\n // registered for timing\n always @(posedge clk) begin\n pi_en_stg2_f <= #TCQ pi_en_stg2_f_timing;\n pi_stg2_f_incdec <= #TCQ pi_stg2_f_incdec_timing;\n end\n\n // This counter used to implement settling time between\n // Phaser_IN rank register loads to different DQSs\n always @(posedge clk) begin\n if (rst)\n done_cnt <= #TCQ 'b0;\n else if (((cal1_state_r == CAL1_REGL_LOAD) &&\n (cal1_state_r1 == CAL1_NEXT_DQS)) ||\n ((done_cnt == 4'd1) && (cal1_state_r != CAL1_DONE)))\n done_cnt <= #TCQ 4'b1010;\n else if (done_cnt > 'b0)\n done_cnt <= #TCQ done_cnt - 1;\n end\n\n // During rank register loading the rank count must be sent to\n // Phaser_IN via the phy_ctl_wd?? If so phy_init will have to\n // issue NOPs during rank register loading with the appropriate\n // rank count\n always @(posedge clk) begin\n if (rst || (regl_rank_done_r == 1'b1))\n regl_rank_done_r <= #TCQ 1'b0;\n else if ((regl_dqs_cnt == DQS_WIDTH-1) &&\n (regl_rank_cnt != RANKS-1) &&\n (done_cnt == 4'd1))\n regl_rank_done_r <= #TCQ 1'b1;\n end\n\n // Temp wire for timing.\n // The following in the always block below causes timing issues\n // due to DSP block inference\n // 6*regl_dqs_cnt.\n // replacing this with two left shifts + 1 left shift to avoid\n // DSP multiplier.\n assign regl_dqs_cnt_timing = {2'd0, regl_dqs_cnt};\n\n // Load Phaser_OUT rank register with rdlvl delay value\n // for each DQS per rank.\n always @(posedge clk) begin\n if (rst || (done_cnt == 4'd0)) begin\n pi_stg2_load_timing <= #TCQ 'b0;\n pi_stg2_reg_l_timing <= #TCQ 'b0;\n end else if ((cal1_state_r == CAL1_REGL_LOAD) &&\n (regl_dqs_cnt <= DQS_WIDTH-1) && (done_cnt == 4'd1)) begin\n pi_stg2_load_timing <= #TCQ 'b1;\n pi_stg2_reg_l_timing <= #TCQ\n rdlvl_dqs_tap_cnt_r[rnk_cnt_r][regl_dqs_cnt];\n end else begin\n pi_stg2_load_timing <= #TCQ 'b0;\n pi_stg2_reg_l_timing <= #TCQ 'b0;\n end\n end\n\n // registered for timing\n always @(posedge clk) begin\n pi_stg2_load <= #TCQ pi_stg2_load_timing;\n pi_stg2_reg_l <= #TCQ pi_stg2_reg_l_timing;\n end\n\n always @(posedge clk) begin\n if (rst || (done_cnt == 4'd0) ||\n (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2))\n regl_rank_cnt <= #TCQ 2'b00;\n else if ((cal1_state_r == CAL1_REGL_LOAD) &&\n (regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1)) begin\n if (regl_rank_cnt == RANKS-1)\n regl_rank_cnt <= #TCQ regl_rank_cnt;\n else\n regl_rank_cnt <= #TCQ regl_rank_cnt + 1;\n end\n end\n\n always @(posedge clk) begin\n if (rst || (done_cnt == 4'd0) ||\n (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2))\n regl_dqs_cnt <= #TCQ {DQS_CNT_WIDTH+1{1'b0}};\n else if ((cal1_state_r == CAL1_REGL_LOAD) &&\n (regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1)) begin\n if (regl_rank_cnt == RANKS-1)\n regl_dqs_cnt <= #TCQ regl_dqs_cnt;\n else\n regl_dqs_cnt <= #TCQ 'b0;\n end else if ((cal1_state_r == CAL1_REGL_LOAD) && (regl_dqs_cnt != DQS_WIDTH-1)\n && (done_cnt == 4'd1))\n regl_dqs_cnt <= #TCQ regl_dqs_cnt + 1;\n else\n regl_dqs_cnt <= #TCQ regl_dqs_cnt;\n end\n\n\n always @(posedge clk)\n regl_dqs_cnt_r <= #TCQ regl_dqs_cnt;\n //*****************************************************************\n // DQ Stage 1 CALIBRATION INCREMENT/DECREMENT LOGIC:\n // The actual IDELAY elements for each of the DQ bits is set via the\n // DLYVAL parallel load port. However, the stage 1 calibration\n // algorithm (well most of it) only needs to increment or decrement the DQ\n // IDELAY value by 1 at any one time.\n //*****************************************************************\n\n // Chip-select generation for each of the individual counters tracking\n // IDELAY tap values for each DQ\n generate\n for (z = 0; z < DQS_WIDTH; z = z + 1) begin: gen_dlyce_dq\n always @(posedge clk)\n if (rst)\n dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0;\n else\n if (SIM_CAL_OPTION == \"SKIP_CAL\")\n // If skipping calibration altogether (only for simulation), no\n // need to set DQ IODELAY values - they are hardcoded\n dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0;\n else if (SIM_CAL_OPTION == \"FAST_CAL\") begin\n // If fast calibration option (simulation only) selected, DQ\n // IODELAYs across all bytes are updated simultaneously\n // (although per-bit deskew within DQS[0] is still supported)\n for (h = 0; h < DRAM_WIDTH; h = h + 1) begin\n dlyce_dq_r[DRAM_WIDTH*z + h] <= #TCQ cal1_dlyce_dq_r;\n end\n end else if ((SIM_CAL_OPTION == \"NONE\") ||\n (SIM_CAL_OPTION == \"FAST_WIN_DETECT\")) begin\n if (cal1_cnt_cpt_r == z) begin\n for (g = 0; g < DRAM_WIDTH; g = g + 1) begin\n dlyce_dq_r[DRAM_WIDTH*z + g]\n <= #TCQ cal1_dlyce_dq_r;\n end\n end else\n dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0;\n end\n end\n endgenerate\n\n // Also delay increment/decrement control to match delay on DLYCE\n always @(posedge clk)\n if (rst)\n dlyinc_dq_r <= #TCQ 1'b0;\n else\n dlyinc_dq_r <= #TCQ cal1_dlyinc_dq_r;\n\n\n // Each DQ has a counter associated with it to record current read-leveling\n // delay value\n always @(posedge clk)\n // Reset or skipping calibration all together\n if (rst | (SIM_CAL_OPTION == \"SKIP_CAL\")) begin\n for (aa = 0; aa < RANKS; aa = aa + 1) begin: rst_dlyval_dq_reg_r\n for (bb = 0; bb < DQ_WIDTH; bb = bb + 1)\n dlyval_dq_reg_r[aa][bb] <= #TCQ 'b0;\n end\n end else if (SIM_CAL_OPTION == \"FAST_CAL\") begin\n for (n = 0; n < RANKS; n = n + 1) begin: gen_dlyval_dq_reg_rnk\n for (r = 0; r < DQ_WIDTH; r = r + 1) begin: gen_dlyval_dq_reg\n if (dlyce_dq_r[r]) begin\n if (dlyinc_dq_r)\n dlyval_dq_reg_r[n][r] <= #TCQ dlyval_dq_reg_r[n][r] + 5'h01;\n else\n dlyval_dq_reg_r[n][r] <= #TCQ dlyval_dq_reg_r[n][r] - 5'h01;\n end\n end\n end\n end else begin\n if (dlyce_dq_r[cal1_cnt_cpt_r]) begin\n if (dlyinc_dq_r)\n dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] <= #TCQ\n dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] + 5'h01;\n else\n dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] <= #TCQ\n dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] - 5'h01;\n end\n end\n\n // Register for timing (help with logic placement)\n always @(posedge clk) begin\n for (cc = 0; cc < RANKS; cc = cc + 1) begin: dlyval_dq_assgn\n for (dd = 0; dd < DQ_WIDTH; dd = dd + 1)\n dlyval_dq[((5*dd)+(cc*DQ_WIDTH*5))+:5] <= #TCQ dlyval_dq_reg_r[cc][dd];\n end\n end\n\n //***************************************************************************\n // Generate signal used to delay calibration state machine - used when:\n // (1) IDELAY value changed\n // (2) RD_MUX_SEL value changed\n // Use when a delay is necessary to give the change time to propagate\n // through the data pipeline (through IDELAY and ISERDES, and fabric\n // pipeline stages)\n //***************************************************************************\n\n\n // List all the stage 1 calibration wait states here.\n // verilint STARC-2.7.3.3b off\n always @(posedge clk)\n if ((cal1_state_r == CAL1_NEW_DQS_WAIT) ||\n (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) ||\n (cal1_state_r == CAL1_NEW_DQS_PREWAIT) ||\n (cal1_state_r == CAL1_VALID_WAIT) ||\n (cal1_state_r == CAL1_PB_STORE_FIRST_WAIT) ||\n (cal1_state_r == CAL1_PB_INC_CPT_WAIT) ||\n (cal1_state_r == CAL1_PB_DEC_CPT_LEFT_WAIT) ||\n (cal1_state_r == CAL1_PB_INC_DQ_WAIT) ||\n (cal1_state_r == CAL1_PB_DEC_CPT_WAIT) ||\n (cal1_state_r == CAL1_IDEL_INC_CPT_WAIT) ||\n (cal1_state_r == CAL1_IDEL_DEC_CPT_WAIT) ||\n (cal1_state_r == CAL1_STORE_FIRST_WAIT) ||\n (cal1_state_r == CAL1_DQ_IDEL_TAP_INC_WAIT) ||\n (cal1_state_r == CAL1_DQ_IDEL_TAP_DEC_WAIT) ||\n (cal1_state_r == CAL1_CENTER_WAIT) ||\n (cal1_state_r == CAL1_RD_STOP_FOR_PI_INC))\n cal1_wait_cnt_en_r <= #TCQ 1'b1;\n else\n cal1_wait_cnt_en_r <= #TCQ 1'b0;\n// verilint STARC-2.7.3.3b on\n always @(posedge clk)\n if (!cal1_wait_cnt_en_r) begin\n cal1_wait_cnt_r <= #TCQ 5'b00000;\n cal1_wait_r <= #TCQ 1'b1;\n end else begin\n if (cal1_wait_cnt_r != PIPE_WAIT_CNT - 1) begin\n cal1_wait_cnt_r <= #TCQ cal1_wait_cnt_r + 1;\n cal1_wait_r <= #TCQ 1'b1;\n end else begin\n // Need to reset to 0 to handle the case when there are two\n // different WAIT states back-to-back\n cal1_wait_cnt_r <= #TCQ 5'b00000;\n cal1_wait_r <= #TCQ 1'b0;\n end\n end\n\n //***************************************************************************\n // generate request to PHY_INIT logic to issue precharged. Required when\n // calibration can take a long time (during which there are only constant\n // reads present on this bus). In this case need to issue perioidic\n // precharges to avoid tRAS violation. This signal must meet the following\n // requirements: (1) only transition from 0->1 when prech is first needed,\n // (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted\n //***************************************************************************\n\n always @(posedge clk)\n if (rst)\n rdlvl_prech_req <= #TCQ 1'b0;\n else\n rdlvl_prech_req <= #TCQ cal1_prech_req_r;\n\n //***************************************************************************\n // Serial-to-parallel register to store last RDDATA_SHIFT_LEN cycles of\n // data from ISERDES. The value of this register is also stored, so that\n // previous and current values of the ISERDES data can be compared while\n // varying the IODELAY taps to see if an \"edge\" of the data valid window\n // has been encountered since the last IODELAY tap adjustment\n //***************************************************************************\n\n //***************************************************************************\n // Shift register to store last RDDATA_SHIFT_LEN cycles of data from ISERDES\n // NOTE: Written using discrete flops, but SRL can be used if the matching\n // logic does the comparison sequentially, rather than parallel\n //***************************************************************************\n\n generate\n genvar rd_i;\n if (nCK_PER_CLK == 4) begin: gen_sr_div4\n if (RD_SHIFT_LEN == 1) begin: gen_sr_len_eq1\n for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr\n always @(posedge clk) begin\n if (mux_rd_valid_r) begin\n sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i];\n sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i];\n sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i];\n sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i];\n sr_rise2_r[rd_i] <= #TCQ mux_rd_rise2_r[rd_i];\n sr_fall2_r[rd_i] <= #TCQ mux_rd_fall2_r[rd_i];\n sr_rise3_r[rd_i] <= #TCQ mux_rd_rise3_r[rd_i];\n sr_fall3_r[rd_i] <= #TCQ mux_rd_fall3_r[rd_i];\n end\n end\n end\n end else if (RD_SHIFT_LEN > 1) begin: gen_sr_len_gt1\n for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr\n always @(posedge clk) begin\n if (mux_rd_valid_r) begin\n sr_rise0_r[rd_i] <= #TCQ {sr_rise0_r[rd_i][RD_SHIFT_LEN-2:0],\n mux_rd_rise0_r[rd_i]};\n sr_fall0_r[rd_i] <= #TCQ {sr_fall0_r[rd_i][RD_SHIFT_LEN-2:0],\n mux_rd_fall0_r[rd_i]};\n sr_rise1_r[rd_i] <= #TCQ {sr_rise1_r[rd_i][RD_SHIFT_LEN-2:0],\n mux_rd_rise1_r[rd_i]};\n sr_fall1_r[rd_i] <= #TCQ {sr_fall1_r[rd_i][RD_SHIFT_LEN-2:0],\n mux_rd_fall1_r[rd_i]};\n sr_rise2_r[rd_i] <= #TCQ {sr_rise2_r[rd_i][RD_SHIFT_LEN-2:0],\n mux_rd_rise2_r[rd_i]};\n sr_fall2_r[rd_i] <= #TCQ {sr_fall2_r[rd_i][RD_SHIFT_LEN-2:0],\n mux_rd_fall2_r[rd_i]};\n sr_rise3_r[rd_i] <= #TCQ {sr_rise3_r[rd_i][RD_SHIFT_LEN-2:0],\n mux_rd_rise3_r[rd_i]};\n sr_fall3_r[rd_i] <= #TCQ {sr_fall3_r[rd_i][RD_SHIFT_LEN-2:0],\n mux_rd_fall3_r[rd_i]};\n end\n end\n end\n end\n end else if (nCK_PER_CLK == 2) begin: gen_sr_div2\n if (RD_SHIFT_LEN == 1) begin: gen_sr_len_eq1\n for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr\n always @(posedge clk) begin\n if (mux_rd_valid_r) begin\n sr_rise0_r[rd_i] <= #TCQ {mux_rd_rise0_r[rd_i]};\n sr_fall0_r[rd_i] <= #TCQ {mux_rd_fall0_r[rd_i]};\n sr_rise1_r[rd_i] <= #TCQ {mux_rd_rise1_r[rd_i]};\n sr_fall1_r[rd_i] <= #TCQ {mux_rd_fall1_r[rd_i]};\n end\n end\n end\n end else if (RD_SHIFT_LEN > 1) begin: gen_sr_len_gt1\n for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr\n always @(posedge clk) begin\n if (mux_rd_valid_r) begin\n sr_rise0_r[rd_i] <= #TCQ {sr_rise0_r[rd_i][RD_SHIFT_LEN-2:0],\n mux_rd_rise0_r[rd_i]};\n sr_fall0_r[rd_i] <= #TCQ {sr_fall0_r[rd_i][RD_SHIFT_LEN-2:0],\n mux_rd_fall0_r[rd_i]};\n sr_rise1_r[rd_i] <= #TCQ {sr_rise1_r[rd_i][RD_SHIFT_LEN-2:0],\n mux_rd_rise1_r[rd_i]};\n sr_fall1_r[rd_i] <= #TCQ {sr_fall1_r[rd_i][RD_SHIFT_LEN-2:0],\n mux_rd_fall1_r[rd_i]};\n end\n end\n end\n end\n end\n endgenerate\n\n //***************************************************************************\n // Conversion to pattern calibration\n //***************************************************************************\n\n // Pattern for DQ IDELAY calibration\n\n //*****************************************************************\n // Expected data pattern when DQ shifted to the right such that\n // DQS before the left edge of the DVW:\n // Based on pattern of ({rise,fall}) =\n // 0x1, 0xB, 0x4, 0x4, 0xB, 0x9\n // Each nibble will look like:\n // bit3: 0, 1, 0, 0, 1, 1\n // bit2: 0, 0, 1, 1, 0, 0\n // bit1: 0, 1, 0, 0, 1, 0\n // bit0: 1, 1, 0, 0, 1, 1\n // Or if the write is early it could look like:\n // 0x4, 0x4, 0xB, 0x9, 0x6, 0xE\n // bit3: 0, 0, 1, 1, 0, 1\n // bit2: 1, 1, 0, 0, 1, 1\n // bit1: 0, 0, 1, 0, 1, 1\n // bit0: 0, 0, 1, 1, 0, 0\n // Change the hard-coded pattern below accordingly as RD_SHIFT_LEN\n // and the actual training pattern contents change\n //*****************************************************************\n\n generate\n if (nCK_PER_CLK == 4) begin: gen_pat_div4\n // Pattern for DQ IDELAY increment\n\n // Target pattern for \"early write\"\n assign {idel_pat0_rise0[3], idel_pat0_rise0[2],\n idel_pat0_rise0[1], idel_pat0_rise0[0]} = 4'h1;\n assign {idel_pat0_fall0[3], idel_pat0_fall0[2],\n idel_pat0_fall0[1], idel_pat0_fall0[0]} = 4'h7;\n assign {idel_pat0_rise1[3], idel_pat0_rise1[2],\n idel_pat0_rise1[1], idel_pat0_rise1[0]} = 4'hE;\n assign {idel_pat0_fall1[3], idel_pat0_fall1[2],\n idel_pat0_fall1[1], idel_pat0_fall1[0]} = 4'hC;\n assign {idel_pat0_rise2[3], idel_pat0_rise2[2],\n idel_pat0_rise2[1], idel_pat0_rise2[0]} = 4'h9;\n assign {idel_pat0_fall2[3], idel_pat0_fall2[2],\n idel_pat0_fall2[1], idel_pat0_fall2[0]} = 4'h2;\n assign {idel_pat0_rise3[3], idel_pat0_rise3[2],\n idel_pat0_rise3[1], idel_pat0_rise3[0]} = 4'h4;\n assign {idel_pat0_fall3[3], idel_pat0_fall3[2],\n idel_pat0_fall3[1], idel_pat0_fall3[0]} = 4'hB;\n\n // Target pattern for \"on-time write\"\n assign {idel_pat1_rise0[3], idel_pat1_rise0[2],\n idel_pat1_rise0[1], idel_pat1_rise0[0]} = 4'h4;\n assign {idel_pat1_fall0[3], idel_pat1_fall0[2],\n idel_pat1_fall0[1], idel_pat1_fall0[0]} = 4'h9;\n assign {idel_pat1_rise1[3], idel_pat1_rise1[2],\n idel_pat1_rise1[1], idel_pat1_rise1[0]} = 4'h3;\n assign {idel_pat1_fall1[3], idel_pat1_fall1[2],\n idel_pat1_fall1[1], idel_pat1_fall1[0]} = 4'h7;\n assign {idel_pat1_rise2[3], idel_pat1_rise2[2],\n idel_pat1_rise2[1], idel_pat1_rise2[0]} = 4'hE;\n assign {idel_pat1_fall2[3], idel_pat1_fall2[2],\n idel_pat1_fall2[1], idel_pat1_fall2[0]} = 4'hC;\n assign {idel_pat1_rise3[3], idel_pat1_rise3[2],\n idel_pat1_rise3[1], idel_pat1_rise3[0]} = 4'h9;\n assign {idel_pat1_fall3[3], idel_pat1_fall3[2],\n idel_pat1_fall3[1], idel_pat1_fall3[0]} = 4'h2;\n\n\n // Correct data valid window for \"early write\"\n assign {pat0_rise0[3], pat0_rise0[2],\n pat0_rise0[1], pat0_rise0[0]} = 4'h7;\n assign {pat0_fall0[3], pat0_fall0[2],\n pat0_fall0[1], pat0_fall0[0]} = 4'hE;\n assign {pat0_rise1[3], pat0_rise1[2],\n pat0_rise1[1], pat0_rise1[0]} = 4'hC;\n assign {pat0_fall1[3], pat0_fall1[2],\n pat0_fall1[1], pat0_fall1[0]} = 4'h9;\n assign {pat0_rise2[3], pat0_rise2[2],\n pat0_rise2[1], pat0_rise2[0]} = 4'h2;\n assign {pat0_fall2[3], pat0_fall2[2],\n pat0_fall2[1], pat0_fall2[0]} = 4'h4;\n assign {pat0_rise3[3], pat0_rise3[2],\n pat0_rise3[1], pat0_rise3[0]} = 4'hB;\n assign {pat0_fall3[3], pat0_fall3[2],\n pat0_fall3[1], pat0_fall3[0]} = 4'h1;\n\n // Correct data valid window for \"on-time write\"\n assign {pat1_rise0[3], pat1_rise0[2],\n pat1_rise0[1], pat1_rise0[0]} = 4'h9;\n assign {pat1_fall0[3], pat1_fall0[2],\n pat1_fall0[1], pat1_fall0[0]} = 4'h3;\n assign {pat1_rise1[3], pat1_rise1[2],\n pat1_rise1[1], pat1_rise1[0]} = 4'h7;\n assign {pat1_fall1[3], pat1_fall1[2],\n pat1_fall1[1], pat1_fall1[0]} = 4'hE;\n assign {pat1_rise2[3], pat1_rise2[2],\n pat1_rise2[1], pat1_rise2[0]} = 4'hC;\n assign {pat1_fall2[3], pat1_fall2[2],\n pat1_fall2[1], pat1_fall2[0]} = 4'h9;\n assign {pat1_rise3[3], pat1_rise3[2],\n pat1_rise3[1], pat1_rise3[0]} = 4'h2;\n assign {pat1_fall3[3], pat1_fall3[2],\n pat1_fall3[1], pat1_fall3[0]} = 4'h4;\n\n end else if (nCK_PER_CLK == 2) begin: gen_pat_div2\n\n // Pattern for DQ IDELAY increment\n\n // Target pattern for \"early write\"\n assign idel_pat0_rise0[3] = 2'b01;\n assign idel_pat0_fall0[3] = 2'b00;\n assign idel_pat0_rise1[3] = 2'b10;\n assign idel_pat0_fall1[3] = 2'b11;\n\n assign idel_pat0_rise0[2] = 2'b00;\n assign idel_pat0_fall0[2] = 2'b10;\n assign idel_pat0_rise1[2] = 2'b11;\n assign idel_pat0_fall1[2] = 2'b10;\n\n assign idel_pat0_rise0[1] = 2'b00;\n assign idel_pat0_fall0[1] = 2'b11;\n assign idel_pat0_rise1[1] = 2'b10;\n assign idel_pat0_fall1[1] = 2'b01;\n\n assign idel_pat0_rise0[0] = 2'b11;\n assign idel_pat0_fall0[0] = 2'b10;\n assign idel_pat0_rise1[0] = 2'b00;\n assign idel_pat0_fall1[0] = 2'b01;\n\n\n // Target pattern for \"on-time write\"\n assign idel_pat1_rise0[3] = 2'b01;\n assign idel_pat1_fall0[3] = 2'b11;\n assign idel_pat1_rise1[3] = 2'b01;\n assign idel_pat1_fall1[3] = 2'b00;\n\n assign idel_pat1_rise0[2] = 2'b11;\n assign idel_pat1_fall0[2] = 2'b01;\n assign idel_pat1_rise1[2] = 2'b00;\n assign idel_pat1_fall1[2] = 2'b10;\n\n assign idel_pat1_rise0[1] = 2'b01;\n assign idel_pat1_fall0[1] = 2'b00;\n assign idel_pat1_rise1[1] = 2'b10;\n assign idel_pat1_fall1[1] = 2'b11;\n\n assign idel_pat1_rise0[0] = 2'b00;\n assign idel_pat1_fall0[0] = 2'b10;\n assign idel_pat1_rise1[0] = 2'b11;\n assign idel_pat1_fall1[0] = 2'b10;\n\n\n // Correct data valid window for \"early write\"\n assign pat0_rise0[3] = 2'b00;\n assign pat0_fall0[3] = 2'b10;\n assign pat0_rise1[3] = 2'b11;\n assign pat0_fall1[3] = 2'b10;\n\n assign pat0_rise0[2] = 2'b10;\n assign pat0_fall0[2] = 2'b11;\n assign pat0_rise1[2] = 2'b10;\n assign pat0_fall1[2] = 2'b00;\n\n assign pat0_rise0[1] = 2'b11;\n assign pat0_fall0[1] = 2'b10;\n assign pat0_rise1[1] = 2'b01;\n assign pat0_fall1[1] = 2'b00;\n\n assign pat0_rise0[0] = 2'b10;\n assign pat0_fall0[0] = 2'b00;\n assign pat0_rise1[0] = 2'b01;\n assign pat0_fall1[0] = 2'b11;\n\n // Correct data valid window for \"on-time write\"\n assign pat1_rise0[3] = 2'b11;\n assign pat1_fall0[3] = 2'b01;\n assign pat1_rise1[3] = 2'b00;\n assign pat1_fall1[3] = 2'b10;\n\n assign pat1_rise0[2] = 2'b01;\n assign pat1_fall0[2] = 2'b00;\n assign pat1_rise1[2] = 2'b10;\n assign pat1_fall1[2] = 2'b11;\n\n assign pat1_rise0[1] = 2'b00;\n assign pat1_fall0[1] = 2'b10;\n assign pat1_rise1[1] = 2'b11;\n assign pat1_fall1[1] = 2'b10;\n\n assign pat1_rise0[0] = 2'b10;\n assign pat1_fall0[0] = 2'b11;\n assign pat1_rise1[0] = 2'b10;\n assign pat1_fall1[0] = 2'b00;\n end\n endgenerate\n\n // Each bit of each byte is compared to expected pattern.\n // This was done to prevent (and \"drastically decrease\") the chance that\n // invalid data clocked in when the DQ bus is tri-state (along with a\n // combination of the correct data) will resemble the expected data\n // pattern. A better fix for this is to change the training pattern and/or\n // make the pattern longer.\n generate\n genvar pt_i;\n if (nCK_PER_CLK == 4) begin: gen_pat_match_div4\n for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match\n\n // DQ IDELAY pattern detection\n always @(posedge clk) begin\n if (sr_rise0_r[pt_i] == idel_pat0_rise0[pt_i%4])\n idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b1;\n else\n idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_fall0_r[pt_i] == idel_pat0_fall0[pt_i%4])\n idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b1;\n else\n idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_rise1_r[pt_i] == idel_pat0_rise1[pt_i%4])\n idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b1;\n else\n idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_fall1_r[pt_i] == idel_pat0_fall1[pt_i%4])\n idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b1;\n else\n idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_rise2_r[pt_i] == idel_pat0_rise2[pt_i%4])\n idel_pat0_match_rise2_r[pt_i] <= #TCQ 1'b1;\n else\n idel_pat0_match_rise2_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_fall2_r[pt_i] == idel_pat0_fall2[pt_i%4])\n idel_pat0_match_fall2_r[pt_i] <= #TCQ 1'b1;\n else\n idel_pat0_match_fall2_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_rise3_r[pt_i] == idel_pat0_rise3[pt_i%4])\n idel_pat0_match_rise3_r[pt_i] <= #TCQ 1'b1;\n else\n idel_pat0_match_rise3_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_fall3_r[pt_i] == idel_pat0_fall3[pt_i%4])\n idel_pat0_match_fall3_r[pt_i] <= #TCQ 1'b1;\n else\n idel_pat0_match_fall3_r[pt_i] <= #TCQ 1'b0;\n end\n\n always @(posedge clk) begin\n if (sr_rise0_r[pt_i] == idel_pat1_rise0[pt_i%4])\n idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b1;\n else\n idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_fall0_r[pt_i] == idel_pat1_fall0[pt_i%4])\n idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b1;\n else\n idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_rise1_r[pt_i] == idel_pat1_rise1[pt_i%4])\n idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b1;\n else\n idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_fall1_r[pt_i] == idel_pat1_fall1[pt_i%4])\n idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b1;\n else\n idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_rise2_r[pt_i] == idel_pat1_rise2[pt_i%4])\n idel_pat1_match_rise2_r[pt_i] <= #TCQ 1'b1;\n else\n idel_pat1_match_rise2_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_fall2_r[pt_i] == idel_pat1_fall2[pt_i%4])\n idel_pat1_match_fall2_r[pt_i] <= #TCQ 1'b1;\n else\n idel_pat1_match_fall2_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_rise3_r[pt_i] == idel_pat1_rise3[pt_i%4])\n idel_pat1_match_rise3_r[pt_i] <= #TCQ 1'b1;\n else\n idel_pat1_match_rise3_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_fall3_r[pt_i] == idel_pat1_fall3[pt_i%4])\n idel_pat1_match_fall3_r[pt_i] <= #TCQ 1'b1;\n else\n idel_pat1_match_fall3_r[pt_i] <= #TCQ 1'b0;\n end\n\n // DQS DVW pattern detection\n always @(posedge clk) begin\n if (sr_rise0_r[pt_i] == pat0_rise0[pt_i%4])\n pat0_match_rise0_r[pt_i] <= #TCQ 1'b1;\n else\n pat0_match_rise0_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_fall0_r[pt_i] == pat0_fall0[pt_i%4])\n pat0_match_fall0_r[pt_i] <= #TCQ 1'b1;\n else\n pat0_match_fall0_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_rise1_r[pt_i] == pat0_rise1[pt_i%4])\n pat0_match_rise1_r[pt_i] <= #TCQ 1'b1;\n else\n pat0_match_rise1_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_fall1_r[pt_i] == pat0_fall1[pt_i%4])\n pat0_match_fall1_r[pt_i] <= #TCQ 1'b1;\n else\n pat0_match_fall1_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_rise2_r[pt_i] == pat0_rise2[pt_i%4])\n pat0_match_rise2_r[pt_i] <= #TCQ 1'b1;\n else\n pat0_match_rise2_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_fall2_r[pt_i] == pat0_fall2[pt_i%4])\n pat0_match_fall2_r[pt_i] <= #TCQ 1'b1;\n else\n pat0_match_fall2_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_rise3_r[pt_i] == pat0_rise3[pt_i%4])\n pat0_match_rise3_r[pt_i] <= #TCQ 1'b1;\n else\n pat0_match_rise3_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_fall3_r[pt_i] == pat0_fall3[pt_i%4])\n pat0_match_fall3_r[pt_i] <= #TCQ 1'b1;\n else\n pat0_match_fall3_r[pt_i] <= #TCQ 1'b0;\n end\n\n always @(posedge clk) begin\n if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4])\n pat1_match_rise0_r[pt_i] <= #TCQ 1'b1;\n else\n pat1_match_rise0_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4])\n pat1_match_fall0_r[pt_i] <= #TCQ 1'b1;\n else\n pat1_match_fall0_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4])\n pat1_match_rise1_r[pt_i] <= #TCQ 1'b1;\n else\n pat1_match_rise1_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4])\n pat1_match_fall1_r[pt_i] <= #TCQ 1'b1;\n else\n pat1_match_fall1_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_rise2_r[pt_i] == pat1_rise2[pt_i%4])\n pat1_match_rise2_r[pt_i] <= #TCQ 1'b1;\n else\n pat1_match_rise2_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_fall2_r[pt_i] == pat1_fall2[pt_i%4])\n pat1_match_fall2_r[pt_i] <= #TCQ 1'b1;\n else\n pat1_match_fall2_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_rise3_r[pt_i] == pat1_rise3[pt_i%4])\n pat1_match_rise3_r[pt_i] <= #TCQ 1'b1;\n else\n pat1_match_rise3_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_fall3_r[pt_i] == pat1_fall3[pt_i%4])\n pat1_match_fall3_r[pt_i] <= #TCQ 1'b1;\n else\n pat1_match_fall3_r[pt_i] <= #TCQ 1'b0;\n end\n\n end\n\n // Combine pattern match \"subterms\" for DQ-IDELAY stage\n always @(posedge clk) begin\n idel_pat0_match_rise0_and_r <= #TCQ &idel_pat0_match_rise0_r;\n idel_pat0_match_fall0_and_r <= #TCQ &idel_pat0_match_fall0_r;\n idel_pat0_match_rise1_and_r <= #TCQ &idel_pat0_match_rise1_r;\n idel_pat0_match_fall1_and_r <= #TCQ &idel_pat0_match_fall1_r;\n idel_pat0_match_rise2_and_r <= #TCQ &idel_pat0_match_rise2_r;\n idel_pat0_match_fall2_and_r <= #TCQ &idel_pat0_match_fall2_r;\n idel_pat0_match_rise3_and_r <= #TCQ &idel_pat0_match_rise3_r;\n idel_pat0_match_fall3_and_r <= #TCQ &idel_pat0_match_fall3_r;\n idel_pat0_data_match_r <= #TCQ (idel_pat0_match_rise0_and_r &&\n idel_pat0_match_fall0_and_r &&\n idel_pat0_match_rise1_and_r &&\n idel_pat0_match_fall1_and_r &&\n idel_pat0_match_rise2_and_r &&\n idel_pat0_match_fall2_and_r &&\n idel_pat0_match_rise3_and_r &&\n idel_pat0_match_fall3_and_r);\n end\n\n always @(posedge clk) begin\n idel_pat1_match_rise0_and_r <= #TCQ &idel_pat1_match_rise0_r;\n idel_pat1_match_fall0_and_r <= #TCQ &idel_pat1_match_fall0_r;\n idel_pat1_match_rise1_and_r <= #TCQ &idel_pat1_match_rise1_r;\n idel_pat1_match_fall1_and_r <= #TCQ &idel_pat1_match_fall1_r;\n idel_pat1_match_rise2_and_r <= #TCQ &idel_pat1_match_rise2_r;\n idel_pat1_match_fall2_and_r <= #TCQ &idel_pat1_match_fall2_r;\n idel_pat1_match_rise3_and_r <= #TCQ &idel_pat1_match_rise3_r;\n idel_pat1_match_fall3_and_r <= #TCQ &idel_pat1_match_fall3_r;\n idel_pat1_data_match_r <= #TCQ (idel_pat1_match_rise0_and_r &&\n idel_pat1_match_fall0_and_r &&\n idel_pat1_match_rise1_and_r &&\n idel_pat1_match_fall1_and_r &&\n idel_pat1_match_rise2_and_r &&\n idel_pat1_match_fall2_and_r &&\n idel_pat1_match_rise3_and_r &&\n idel_pat1_match_fall3_and_r);\n end\n\n always @(*)\n idel_pat_data_match <= #TCQ idel_pat0_data_match_r |\n idel_pat1_data_match_r;\n\n always @(posedge clk)\n idel_pat_data_match_r <= #TCQ idel_pat_data_match;\n\n // Combine pattern match \"subterms\" for DQS-PHASER_IN stage\n always @(posedge clk) begin\n pat0_match_rise0_and_r <= #TCQ &pat0_match_rise0_r;\n pat0_match_fall0_and_r <= #TCQ &pat0_match_fall0_r;\n pat0_match_rise1_and_r <= #TCQ &pat0_match_rise1_r;\n pat0_match_fall1_and_r <= #TCQ &pat0_match_fall1_r;\n pat0_match_rise2_and_r <= #TCQ &pat0_match_rise2_r;\n pat0_match_fall2_and_r <= #TCQ &pat0_match_fall2_r;\n pat0_match_rise3_and_r <= #TCQ &pat0_match_rise3_r;\n pat0_match_fall3_and_r <= #TCQ &pat0_match_fall3_r;\n pat0_data_match_r <= #TCQ (pat0_match_rise0_and_r &&\n pat0_match_fall0_and_r &&\n pat0_match_rise1_and_r &&\n pat0_match_fall1_and_r &&\n pat0_match_rise2_and_r &&\n pat0_match_fall2_and_r &&\n pat0_match_rise3_and_r &&\n pat0_match_fall3_and_r);\n end\n\n always @(posedge clk) begin\n pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r;\n pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r;\n pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r;\n pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r;\n pat1_match_rise2_and_r <= #TCQ &pat1_match_rise2_r;\n pat1_match_fall2_and_r <= #TCQ &pat1_match_fall2_r;\n pat1_match_rise3_and_r <= #TCQ &pat1_match_rise3_r;\n pat1_match_fall3_and_r <= #TCQ &pat1_match_fall3_r;\n pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r &&\n pat1_match_fall0_and_r &&\n pat1_match_rise1_and_r &&\n pat1_match_fall1_and_r &&\n pat1_match_rise2_and_r &&\n pat1_match_fall2_and_r &&\n pat1_match_rise3_and_r &&\n pat1_match_fall3_and_r);\n end\n\n assign pat_data_match_r = pat0_data_match_r | pat1_data_match_r;\n\n end else if (nCK_PER_CLK == 2) begin: gen_pat_match_div2\n for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match\n\n // DQ IDELAY pattern detection\n always @(posedge clk) begin\n if (sr_rise0_r[pt_i] == idel_pat0_rise0[pt_i%4])\n idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b1;\n else\n idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_fall0_r[pt_i] == idel_pat0_fall0[pt_i%4])\n idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b1;\n else\n idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_rise1_r[pt_i] == idel_pat0_rise1[pt_i%4])\n idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b1;\n else\n idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_fall1_r[pt_i] == idel_pat0_fall1[pt_i%4])\n idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b1;\n else\n idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b0;\n end\n\n always @(posedge clk) begin\n if (sr_rise0_r[pt_i] == idel_pat1_rise0[pt_i%4])\n idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b1;\n else\n idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_fall0_r[pt_i] == idel_pat1_fall0[pt_i%4])\n idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b1;\n else\n idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_rise1_r[pt_i] == idel_pat1_rise1[pt_i%4])\n idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b1;\n else\n idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_fall1_r[pt_i] == idel_pat1_fall1[pt_i%4])\n idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b1;\n else\n idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b0;\n end\n\n // DQS DVW pattern detection\n always @(posedge clk) begin\n if (sr_rise0_r[pt_i] == pat0_rise0[pt_i%4])\n pat0_match_rise0_r[pt_i] <= #TCQ 1'b1;\n else\n pat0_match_rise0_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_fall0_r[pt_i] == pat0_fall0[pt_i%4])\n pat0_match_fall0_r[pt_i] <= #TCQ 1'b1;\n else\n pat0_match_fall0_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_rise1_r[pt_i] == pat0_rise1[pt_i%4])\n pat0_match_rise1_r[pt_i] <= #TCQ 1'b1;\n else\n pat0_match_rise1_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_fall1_r[pt_i] == pat0_fall1[pt_i%4])\n pat0_match_fall1_r[pt_i] <= #TCQ 1'b1;\n else\n pat0_match_fall1_r[pt_i] <= #TCQ 1'b0;\n end\n\n always @(posedge clk) begin\n if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4])\n pat1_match_rise0_r[pt_i] <= #TCQ 1'b1;\n else\n pat1_match_rise0_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4])\n pat1_match_fall0_r[pt_i] <= #TCQ 1'b1;\n else\n pat1_match_fall0_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4])\n pat1_match_rise1_r[pt_i] <= #TCQ 1'b1;\n else\n pat1_match_rise1_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4])\n pat1_match_fall1_r[pt_i] <= #TCQ 1'b1;\n else\n pat1_match_fall1_r[pt_i] <= #TCQ 1'b0;\n end\n\n end\n\n // Combine pattern match \"subterms\" for DQ-IDELAY stage\n always @(posedge clk) begin\n idel_pat0_match_rise0_and_r <= #TCQ &idel_pat0_match_rise0_r;\n idel_pat0_match_fall0_and_r <= #TCQ &idel_pat0_match_fall0_r;\n idel_pat0_match_rise1_and_r <= #TCQ &idel_pat0_match_rise1_r;\n idel_pat0_match_fall1_and_r <= #TCQ &idel_pat0_match_fall1_r;\n idel_pat0_data_match_r <= #TCQ (idel_pat0_match_rise0_and_r &&\n idel_pat0_match_fall0_and_r &&\n idel_pat0_match_rise1_and_r &&\n idel_pat0_match_fall1_and_r);\n end\n\n always @(posedge clk) begin\n idel_pat1_match_rise0_and_r <= #TCQ &idel_pat1_match_rise0_r;\n idel_pat1_match_fall0_and_r <= #TCQ &idel_pat1_match_fall0_r;\n idel_pat1_match_rise1_and_r <= #TCQ &idel_pat1_match_rise1_r;\n idel_pat1_match_fall1_and_r <= #TCQ &idel_pat1_match_fall1_r;\n idel_pat1_data_match_r <= #TCQ (idel_pat1_match_rise0_and_r &&\n idel_pat1_match_fall0_and_r &&\n idel_pat1_match_rise1_and_r &&\n idel_pat1_match_fall1_and_r);\n end\n\n always @(posedge clk) begin\n if (sr_valid_r2)\n idel_pat_data_match <= #TCQ idel_pat0_data_match_r |\n idel_pat1_data_match_r;\n end\n\n //assign idel_pat_data_match = idel_pat0_data_match_r |\n // idel_pat1_data_match_r;\n\n always @(posedge clk)\n idel_pat_data_match_r <= #TCQ idel_pat_data_match;\n\n // Combine pattern match \"subterms\" for DQS-PHASER_IN stage\n always @(posedge clk) begin\n pat0_match_rise0_and_r <= #TCQ &pat0_match_rise0_r;\n pat0_match_fall0_and_r <= #TCQ &pat0_match_fall0_r;\n pat0_match_rise1_and_r <= #TCQ &pat0_match_rise1_r;\n pat0_match_fall1_and_r <= #TCQ &pat0_match_fall1_r;\n pat0_data_match_r <= #TCQ (pat0_match_rise0_and_r &&\n pat0_match_fall0_and_r &&\n pat0_match_rise1_and_r &&\n pat0_match_fall1_and_r);\n end\n\n always @(posedge clk) begin\n pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r;\n pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r;\n pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r;\n pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r;\n pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r &&\n pat1_match_fall0_and_r &&\n pat1_match_rise1_and_r &&\n pat1_match_fall1_and_r);\n end\n\n assign pat_data_match_r = pat0_data_match_r | pat1_data_match_r;\n\n end\n\n endgenerate\n\n\n always @(posedge clk) begin\n rdlvl_stg1_start_r <= #TCQ rdlvl_stg1_start;\n mpr_rdlvl_done_r1 <= #TCQ mpr_rdlvl_done_r;\n mpr_rdlvl_done_r2 <= #TCQ mpr_rdlvl_done_r1;\n mpr_rdlvl_start_r <= #TCQ mpr_rdlvl_start;\n end\n\n //***************************************************************************\n // First stage calibration: Capture clock\n //***************************************************************************\n\n //*****************************************************************\n // Keep track of how many samples have been written to shift registers\n // Every time RD_SHIFT_LEN samples have been written, then we have a\n // full read training pattern loaded into the sr_* registers. Then assert\n // sr_valid_r to indicate that: (1) comparison between the sr_* and\n // old_sr_* and prev_sr_* registers can take place, (2) transfer of\n // the contents of sr_* to old_sr_* and prev_sr_* registers can also\n // take place\n //*****************************************************************\n// verilint STARC-2.2.3.3 off\n always @(posedge clk)\n if (rst || (mpr_rdlvl_done_r && ~rdlvl_stg1_start)) begin\n cnt_shift_r <= #TCQ 'b1;\n sr_valid_r <= #TCQ 1'b0;\n mpr_valid_r <= #TCQ 1'b0;\n end else begin\n if (mux_rd_valid_r && mpr_rdlvl_start && ~mpr_rdlvl_done_r) begin\n if (cnt_shift_r == 'b0)\n mpr_valid_r <= #TCQ 1'b1;\n else begin\n mpr_valid_r <= #TCQ 1'b0;\n cnt_shift_r <= #TCQ cnt_shift_r + 1;\n end\n end else\n mpr_valid_r <= #TCQ 1'b0;\n\n if (mux_rd_valid_r && rdlvl_stg1_start) begin\n if (cnt_shift_r == RD_SHIFT_LEN-1) begin\n sr_valid_r <= #TCQ 1'b1;\n cnt_shift_r <= #TCQ 'b0;\n end else begin\n sr_valid_r <= #TCQ 1'b0;\n cnt_shift_r <= #TCQ cnt_shift_r + 1;\n end\n end else\n // When the current mux_rd_* contents are not valid, then\n // retain the current value of cnt_shift_r, and make sure\n // that sr_valid_r = 0 to prevent any downstream loads or\n // comparisons\n sr_valid_r <= #TCQ 1'b0;\n end\n// verilint STARC-2.2.3.3 on\n //*****************************************************************\n // Logic to determine when either edge of the data eye encountered\n // Pre- and post-IDELAY update data pattern is compared, if they\n // differ, than an edge has been encountered. Currently no attempt\n // made to determine if the data pattern itself is \"correct\", only\n // whether it changes after incrementing the IDELAY (possible\n // future enhancement)\n //*****************************************************************\n\n // One-way control for ensuring that state machine request to store\n // current read data into OLD SR shift register only occurs on a\n // valid clock cycle. The FSM provides a one-cycle request pulse.\n // It is the responsibility of the FSM to wait the worst-case time\n // before relying on any downstream results of this load.\n always @(posedge clk)\n if (rst)\n store_sr_r <= #TCQ 1'b0;\n else begin\n if (store_sr_req_r)\n store_sr_r <= #TCQ 1'b1;\n else if ((sr_valid_r || mpr_valid_r) && store_sr_r)\n store_sr_r <= #TCQ 1'b0;\n end\n\n // Transfer current data to old data, prior to incrementing delay\n // Also store data from current sampling window - so that we can detect\n // if the current delay tap yields data that is \"jittery\"\n generate\n if (nCK_PER_CLK == 4) begin: gen_old_sr_div4\n for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_old_sr\n always @(posedge clk) begin\n if (sr_valid_r || mpr_valid_r) begin\n // Load last sample (i.e. from current sampling interval)\n prev_sr_rise0_r[z] <= #TCQ sr_rise0_r[z];\n prev_sr_fall0_r[z] <= #TCQ sr_fall0_r[z];\n prev_sr_rise1_r[z] <= #TCQ sr_rise1_r[z];\n prev_sr_fall1_r[z] <= #TCQ sr_fall1_r[z];\n prev_sr_rise2_r[z] <= #TCQ sr_rise2_r[z];\n prev_sr_fall2_r[z] <= #TCQ sr_fall2_r[z];\n prev_sr_rise3_r[z] <= #TCQ sr_rise3_r[z];\n prev_sr_fall3_r[z] <= #TCQ sr_fall3_r[z];\n end\n if ((sr_valid_r || mpr_valid_r) && store_sr_r) begin\n old_sr_rise0_r[z] <= #TCQ sr_rise0_r[z];\n old_sr_fall0_r[z] <= #TCQ sr_fall0_r[z];\n old_sr_rise1_r[z] <= #TCQ sr_rise1_r[z];\n old_sr_fall1_r[z] <= #TCQ sr_fall1_r[z];\n old_sr_rise2_r[z] <= #TCQ sr_rise2_r[z];\n old_sr_fall2_r[z] <= #TCQ sr_fall2_r[z];\n old_sr_rise3_r[z] <= #TCQ sr_rise3_r[z];\n old_sr_fall3_r[z] <= #TCQ sr_fall3_r[z];\n end\n end\n end\n end else if (nCK_PER_CLK == 2) begin: gen_old_sr_div2\n for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_old_sr\n always @(posedge clk) begin\n if (sr_valid_r || mpr_valid_r) begin\n prev_sr_rise0_r[z] <= #TCQ sr_rise0_r[z];\n prev_sr_fall0_r[z] <= #TCQ sr_fall0_r[z];\n prev_sr_rise1_r[z] <= #TCQ sr_rise1_r[z];\n prev_sr_fall1_r[z] <= #TCQ sr_fall1_r[z];\n end\n if ((sr_valid_r || mpr_valid_r) && store_sr_r) begin\n old_sr_rise0_r[z] <= #TCQ sr_rise0_r[z];\n old_sr_fall0_r[z] <= #TCQ sr_fall0_r[z];\n old_sr_rise1_r[z] <= #TCQ sr_rise1_r[z];\n old_sr_fall1_r[z] <= #TCQ sr_fall1_r[z];\n end\n end\n end\n end\n endgenerate\n\n //*******************************************************\n // Match determination occurs over 3 cycles - pipelined for better timing\n //*******************************************************\n\n // Match valid with # of cycles of pipelining in match determination\n always @(posedge clk) begin\n sr_valid_r1 <= #TCQ sr_valid_r;\n sr_valid_r2 <= #TCQ sr_valid_r1;\n mpr_valid_r1 <= #TCQ mpr_valid_r;\n mpr_valid_r2 <= #TCQ mpr_valid_r1;\n end\n\n generate\n if (nCK_PER_CLK == 4) begin: gen_sr_match_div4\n for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_sr_match\n always @(posedge clk) begin\n // CYCLE1: Compare all bits in DQS grp, generate separate term for\n // each bit over four bit times. For example, if there are 8-bits\n // per DQS group, 32 terms are generated on cycle 1\n // NOTE: Structure HDL such that X on data bus will result in a\n // mismatch. This is required for memory models that can drive the\n // bus with X's to model uncertainty regions (e.g. Denali)\n if ((pat_data_match_r || mpr_valid_r1) && (sr_rise0_r[z] == old_sr_rise0_r[z]))\n old_sr_match_rise0_r[z] <= #TCQ 1'b1;\n else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)\n old_sr_match_rise0_r[z] <= #TCQ old_sr_match_rise0_r[z];\n else\n old_sr_match_rise0_r[z] <= #TCQ 1'b0;\n\n if ((pat_data_match_r || mpr_valid_r1) && (sr_fall0_r[z] == old_sr_fall0_r[z]))\n old_sr_match_fall0_r[z] <= #TCQ 1'b1;\n else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)\n old_sr_match_fall0_r[z] <= #TCQ old_sr_match_fall0_r[z];\n else\n old_sr_match_fall0_r[z] <= #TCQ 1'b0;\n\n if ((pat_data_match_r || mpr_valid_r1) && (sr_rise1_r[z] == old_sr_rise1_r[z]))\n old_sr_match_rise1_r[z] <= #TCQ 1'b1;\n else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)\n old_sr_match_rise1_r[z] <= #TCQ old_sr_match_rise1_r[z];\n else\n old_sr_match_rise1_r[z] <= #TCQ 1'b0;\n\n if ((pat_data_match_r || mpr_valid_r1) && (sr_fall1_r[z] == old_sr_fall1_r[z]))\n old_sr_match_fall1_r[z] <= #TCQ 1'b1;\n else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)\n old_sr_match_fall1_r[z] <= #TCQ old_sr_match_fall1_r[z];\n else\n old_sr_match_fall1_r[z] <= #TCQ 1'b0;\n\n if ((pat_data_match_r || mpr_valid_r1) && (sr_rise2_r[z] == old_sr_rise2_r[z]))\n old_sr_match_rise2_r[z] <= #TCQ 1'b1;\n else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)\n old_sr_match_rise2_r[z] <= #TCQ old_sr_match_rise2_r[z];\n else\n old_sr_match_rise2_r[z] <= #TCQ 1'b0;\n\n if ((pat_data_match_r || mpr_valid_r1) && (sr_fall2_r[z] == old_sr_fall2_r[z]))\n old_sr_match_fall2_r[z] <= #TCQ 1'b1;\n else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)\n old_sr_match_fall2_r[z] <= #TCQ old_sr_match_fall2_r[z];\n else\n old_sr_match_fall2_r[z] <= #TCQ 1'b0;\n\n if ((pat_data_match_r || mpr_valid_r1) && (sr_rise3_r[z] == old_sr_rise3_r[z]))\n old_sr_match_rise3_r[z] <= #TCQ 1'b1;\n else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)\n old_sr_match_rise3_r[z] <= #TCQ old_sr_match_rise3_r[z];\n else\n old_sr_match_rise3_r[z] <= #TCQ 1'b0;\n\n if ((pat_data_match_r || mpr_valid_r1) && (sr_fall3_r[z] == old_sr_fall3_r[z]))\n old_sr_match_fall3_r[z] <= #TCQ 1'b1;\n else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)\n old_sr_match_fall3_r[z] <= #TCQ old_sr_match_fall3_r[z];\n else\n old_sr_match_fall3_r[z] <= #TCQ 1'b0;\n\n if ((pat_data_match_r || mpr_valid_r1) && (sr_rise0_r[z] == prev_sr_rise0_r[z]))\n prev_sr_match_rise0_r[z] <= #TCQ 1'b1;\n else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)\n prev_sr_match_rise0_r[z] <= #TCQ prev_sr_match_rise0_r[z];\n else\n prev_sr_match_rise0_r[z] <= #TCQ 1'b0;\n\n if ((pat_data_match_r || mpr_valid_r1) && (sr_fall0_r[z] == prev_sr_fall0_r[z]))\n prev_sr_match_fall0_r[z] <= #TCQ 1'b1;\n else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)\n prev_sr_match_fall0_r[z] <= #TCQ prev_sr_match_fall0_r[z];\n else\n prev_sr_match_fall0_r[z] <= #TCQ 1'b0;\n\n if ((pat_data_match_r || mpr_valid_r1) && (sr_rise1_r[z] == prev_sr_rise1_r[z]))\n prev_sr_match_rise1_r[z] <= #TCQ 1'b1;\n else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)\n prev_sr_match_rise1_r[z] <= #TCQ prev_sr_match_rise1_r[z];\n else\n prev_sr_match_rise1_r[z] <= #TCQ 1'b0;\n\n if ((pat_data_match_r || mpr_valid_r1) && (sr_fall1_r[z] == prev_sr_fall1_r[z]))\n prev_sr_match_fall1_r[z] <= #TCQ 1'b1;\n else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)\n prev_sr_match_fall1_r[z] <= #TCQ prev_sr_match_fall1_r[z];\n else\n prev_sr_match_fall1_r[z] <= #TCQ 1'b0;\n\n if ((pat_data_match_r || mpr_valid_r1) && (sr_rise2_r[z] == prev_sr_rise2_r[z]))\n prev_sr_match_rise2_r[z] <= #TCQ 1'b1;\n else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)\n prev_sr_match_rise2_r[z] <= #TCQ prev_sr_match_rise2_r[z];\n else\n prev_sr_match_rise2_r[z] <= #TCQ 1'b0;\n\n if ((pat_data_match_r || mpr_valid_r1) && (sr_fall2_r[z] == prev_sr_fall2_r[z]))\n prev_sr_match_fall2_r[z] <= #TCQ 1'b1;\n else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)\n prev_sr_match_fall2_r[z] <= #TCQ prev_sr_match_fall2_r[z];\n else\n prev_sr_match_fall2_r[z] <= #TCQ 1'b0;\n\n if ((pat_data_match_r || mpr_valid_r1) && (sr_rise3_r[z] == prev_sr_rise3_r[z]))\n prev_sr_match_rise3_r[z] <= #TCQ 1'b1;\n else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)\n prev_sr_match_rise3_r[z] <= #TCQ prev_sr_match_rise3_r[z];\n else\n prev_sr_match_rise3_r[z] <= #TCQ 1'b0;\n\n if ((pat_data_match_r || mpr_valid_r1) && (sr_fall3_r[z] == prev_sr_fall3_r[z]))\n prev_sr_match_fall3_r[z] <= #TCQ 1'b1;\n else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)\n prev_sr_match_fall3_r[z] <= #TCQ prev_sr_match_fall3_r[z];\n else\n prev_sr_match_fall3_r[z] <= #TCQ 1'b0;\n\n // CYCLE2: Combine all the comparisons for every 8 words (rise0,\n // fall0,rise1, fall1) in the calibration sequence. Now we're down\n // to DRAM_WIDTH terms\n old_sr_match_cyc2_r[z] <= #TCQ\n old_sr_match_rise0_r[z] &\n old_sr_match_fall0_r[z] &\n old_sr_match_rise1_r[z] &\n old_sr_match_fall1_r[z] &\n old_sr_match_rise2_r[z] &\n old_sr_match_fall2_r[z] &\n old_sr_match_rise3_r[z] &\n old_sr_match_fall3_r[z];\n prev_sr_match_cyc2_r[z] <= #TCQ\n prev_sr_match_rise0_r[z] &\n prev_sr_match_fall0_r[z] &\n prev_sr_match_rise1_r[z] &\n prev_sr_match_fall1_r[z] &\n prev_sr_match_rise2_r[z] &\n prev_sr_match_fall2_r[z] &\n prev_sr_match_rise3_r[z] &\n prev_sr_match_fall3_r[z];\n\n // CYCLE3: Invert value (i.e. assert when DIFFERENCE in value seen),\n // and qualify with pipelined valid signal) - probably don't need\n // a cycle just do do this....\n if (sr_valid_r2 || mpr_valid_r2) begin\n old_sr_diff_r[z] <= #TCQ ~old_sr_match_cyc2_r[z];\n prev_sr_diff_r[z] <= #TCQ ~prev_sr_match_cyc2_r[z];\n end else begin\n old_sr_diff_r[z] <= #TCQ 'b0;\n prev_sr_diff_r[z] <= #TCQ 'b0;\n end\n end\n end\n end if (nCK_PER_CLK == 2) begin: gen_sr_match_div2\n for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_sr_match\n always @(posedge clk) begin\n if ((sr_valid_r || mpr_valid_r1) && (sr_rise0_r[z] == old_sr_rise0_r[z]))\n old_sr_match_rise0_r[z] <= #TCQ 1'b1;\n else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)\n old_sr_match_rise0_r[z] <= #TCQ old_sr_match_rise0_r[z];\n else\n old_sr_match_rise0_r[z] <= #TCQ 1'b0;\n\n if ((sr_valid_r || mpr_valid_r1) && (sr_fall0_r[z] == old_sr_fall0_r[z]))\n old_sr_match_fall0_r[z] <= #TCQ 1'b1;\n else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)\n old_sr_match_fall0_r[z] <= #TCQ old_sr_match_fall0_r[z];\n else\n old_sr_match_fall0_r[z] <= #TCQ 1'b0;\n\n if ((sr_valid_r || mpr_valid_r1) && (sr_rise1_r[z] == old_sr_rise1_r[z]))\n old_sr_match_rise1_r[z] <= #TCQ 1'b1;\n else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)\n old_sr_match_rise1_r[z] <= #TCQ old_sr_match_rise1_r[z];\n else\n old_sr_match_rise1_r[z] <= #TCQ 1'b0;\n\n if ((sr_valid_r || mpr_valid_r1) && (sr_fall1_r[z] == old_sr_fall1_r[z]))\n old_sr_match_fall1_r[z] <= #TCQ 1'b1;\n else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)\n old_sr_match_fall1_r[z] <= #TCQ old_sr_match_fall1_r[z];\n else\n old_sr_match_fall1_r[z] <= #TCQ 1'b0;\n\n if ((sr_valid_r || mpr_valid_r1) && (sr_rise0_r[z] == prev_sr_rise0_r[z]))\n prev_sr_match_rise0_r[z] <= #TCQ 1'b1;\n else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)\n prev_sr_match_rise0_r[z] <= #TCQ prev_sr_match_rise0_r[z];\n else\n prev_sr_match_rise0_r[z] <= #TCQ 1'b0;\n\n if ((sr_valid_r || mpr_valid_r1) && (sr_fall0_r[z] == prev_sr_fall0_r[z]))\n prev_sr_match_fall0_r[z] <= #TCQ 1'b1;\n else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)\n prev_sr_match_fall0_r[z] <= #TCQ prev_sr_match_fall0_r[z];\n else\n prev_sr_match_fall0_r[z] <= #TCQ 1'b0;\n\n if ((sr_valid_r || mpr_valid_r1) && (sr_rise1_r[z] == prev_sr_rise1_r[z]))\n prev_sr_match_rise1_r[z] <= #TCQ 1'b1;\n else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)\n prev_sr_match_rise1_r[z] <= #TCQ prev_sr_match_rise1_r[z];\n else\n prev_sr_match_rise1_r[z] <= #TCQ 1'b0;\n\n if ((sr_valid_r || mpr_valid_r1) && (sr_fall1_r[z] == prev_sr_fall1_r[z]))\n prev_sr_match_fall1_r[z] <= #TCQ 1'b1;\n else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)\n prev_sr_match_fall1_r[z] <= #TCQ prev_sr_match_fall1_r[z];\n else\n prev_sr_match_fall1_r[z] <= #TCQ 1'b0;\n\n old_sr_match_cyc2_r[z] <= #TCQ\n old_sr_match_rise0_r[z] &\n old_sr_match_fall0_r[z] &\n old_sr_match_rise1_r[z] &\n old_sr_match_fall1_r[z];\n prev_sr_match_cyc2_r[z] <= #TCQ\n prev_sr_match_rise0_r[z] &\n prev_sr_match_fall0_r[z] &\n prev_sr_match_rise1_r[z] &\n prev_sr_match_fall1_r[z];\n\n // CYCLE3: Invert value (i.e. assert when DIFFERENCE in value seen),\n // and qualify with pipelined valid signal) - probably don't need\n // a cycle just do do this....\n if (sr_valid_r2 || mpr_valid_r2) begin\n old_sr_diff_r[z] <= #TCQ ~old_sr_match_cyc2_r[z];\n prev_sr_diff_r[z] <= #TCQ ~prev_sr_match_cyc2_r[z];\n end else begin\n old_sr_diff_r[z] <= #TCQ 'b0;\n prev_sr_diff_r[z] <= #TCQ 'b0;\n end\n end\n end\n end\n endgenerate\n\n //***************************************************************************\n // First stage calibration: DQS Capture\n //***************************************************************************\n\n\n //*******************************************************\n // Counters for tracking # of samples compared\n // For each comparision point (i.e. to determine if an edge has\n // occurred after each IODELAY increment when read leveling),\n // multiple samples are compared in order to average out the effects\n // of jitter. If any one of these samples is different than the \"old\"\n // sample corresponding to the previous IODELAY value, then an edge\n // is declared to be detected.\n //*******************************************************\n\n // Two cascaded counters are used to keep track of # of samples compared,\n // in order to make it easier to meeting timing on these paths. Once\n // optimal sampling interval is determined, it may be possible to remove\n // the second counter\n always @(posedge clk)\n samp_edge_cnt0_en_r <= #TCQ\n (cal1_state_r == CAL1_PAT_DETECT) ||\n (cal1_state_r == CAL1_DETECT_EDGE) ||\n (cal1_state_r == CAL1_PB_DETECT_EDGE) ||\n (cal1_state_r == CAL1_PB_DETECT_EDGE_DQ);\n\n // First counter counts # of samples compared\n always @(posedge clk)\n if (rst)\n samp_edge_cnt0_r <= #TCQ 'b0;\n else begin\n if (!samp_edge_cnt0_en_r)\n // Reset sample counter when not in any of the \"sampling\" states\n samp_edge_cnt0_r <= #TCQ 'b0;\n else if (sr_valid_r2 || mpr_valid_r2)\n // Otherwise, count # of samples compared\n samp_edge_cnt0_r <= #TCQ samp_edge_cnt0_r + 1;\n end\n\n // Counter #2 enable generation\n always @(posedge clk)\n if (rst)\n samp_edge_cnt1_en_r <= #TCQ 1'b0;\n else begin\n // Assert pulse when correct number of samples compared\n if ((samp_edge_cnt0_r == DETECT_EDGE_SAMPLE_CNT0) &&\n (sr_valid_r2 || mpr_valid_r2))\n samp_edge_cnt1_en_r <= #TCQ 1'b1;\n else\n samp_edge_cnt1_en_r <= #TCQ 1'b0;\n end\n\n // Counter #2\n always @(posedge clk)\n if (rst)\n samp_edge_cnt1_r <= #TCQ 'b0;\n else\n if (!samp_edge_cnt0_en_r)\n samp_edge_cnt1_r <= #TCQ 'b0;\n else if (samp_edge_cnt1_en_r)\n samp_edge_cnt1_r <= #TCQ samp_edge_cnt1_r + 1;\n\n always @(posedge clk)\n if (rst)\n samp_cnt_done_r <= #TCQ 1'b0;\n else begin\n if (!samp_edge_cnt0_en_r)\n samp_cnt_done_r <= #TCQ 'b0;\n else if ((SIM_CAL_OPTION == \"FAST_CAL\") ||\n (SIM_CAL_OPTION == \"FAST_WIN_DETECT\")) begin\n if (samp_edge_cnt0_r == SR_VALID_DELAY-1)\n // For simulation only, stay in edge detection mode a minimum\n // amount of time - just enough for two data compares to finish\n samp_cnt_done_r <= #TCQ 1'b1;\n end else begin\n if (samp_edge_cnt1_r == DETECT_EDGE_SAMPLE_CNT1)\n samp_cnt_done_r <= #TCQ 1'b1;\n end\n end\n\n //*****************************************************************\n // Logic to keep track of (on per-bit basis):\n // 1. When a region of stability preceded by a known edge occurs\n // 2. If for the current tap, the read data jitters\n // 3. If an edge occured between the current and previous tap\n // 4. When the current edge detection/sampling interval can end\n // Essentially, these are a series of status bits - the stage 1\n // calibration FSM monitors these to determine when an edge is\n // found. Additional information is provided to help the FSM\n // determine if a left or right edge has been found.\n //****************************************************************\n\n assign pb_detect_edge_setup\n = (cal1_state_r == CAL1_STORE_FIRST_WAIT) ||\n (cal1_state_r == CAL1_PB_STORE_FIRST_WAIT) ||\n (cal1_state_r == CAL1_PB_DEC_CPT_LEFT_WAIT);\n\n assign pb_detect_edge\n = (cal1_state_r == CAL1_PAT_DETECT) ||\n (cal1_state_r == CAL1_DETECT_EDGE) ||\n (cal1_state_r == CAL1_PB_DETECT_EDGE) ||\n (cal1_state_r == CAL1_PB_DETECT_EDGE_DQ);\n\n generate\n for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_track_left_edge\n always @(posedge clk) begin\n if (pb_detect_edge_setup) begin\n // Reset eye size, stable eye marker, and jitter marker before\n // starting new edge detection iteration\n pb_cnt_eye_size_r[z] <= #TCQ 5'd0;\n pb_detect_edge_done_r[z] <= #TCQ 1'b0;\n pb_found_stable_eye_r[z] <= #TCQ 1'b0;\n pb_last_tap_jitter_r[z] <= #TCQ 1'b0;\n pb_found_edge_last_r[z] <= #TCQ 1'b0;\n pb_found_edge_r[z] <= #TCQ 1'b0;\n pb_found_first_edge_r[z] <= #TCQ 1'b0;\n end else if (pb_detect_edge) begin\n // Save information on which DQ bits are already out of the\n // data valid window - those DQ bits will later not have their\n // IDELAY tap value incremented\n pb_found_edge_last_r[z] <= #TCQ pb_found_edge_r[z];\n\n if (!pb_detect_edge_done_r[z]) begin\n if (samp_cnt_done_r) begin\n // If we've reached end of sampling interval, no jitter on\n // current tap has been found (although an edge could have\n // been found between the current and previous taps), and\n // the sampling interval is complete. Increment the stable\n // eye counter if no edge found, and always clear the jitter\n // flag in preparation for the next tap.\n pb_last_tap_jitter_r[z] <= #TCQ 1'b0;\n pb_detect_edge_done_r[z] <= #TCQ 1'b1;\n if (!pb_found_edge_r[z] && !pb_last_tap_jitter_r[z]) begin\n // If the data was completely stable during this tap and\n // no edge was found between this and the previous tap\n // then increment the stable eye counter \"as appropriate\"\n if (pb_cnt_eye_size_r[z] != MIN_EYE_SIZE-1)\n pb_cnt_eye_size_r[z] <= #TCQ pb_cnt_eye_size_r[z] + 1;\n else //if (pb_found_first_edge_r[z])\n // We've reached minimum stable eye width\n pb_found_stable_eye_r[z] <= #TCQ 1'b1;\n end else begin\n // Otherwise, an edge was found, either because of a\n // difference between this and the previous tap's read\n // data, and/or because the previous tap's data jittered\n // (but not the current tap's data), then just set the\n // edge found flag, and enable the stable eye counter\n pb_cnt_eye_size_r[z] <= #TCQ 5'd0;\n pb_found_stable_eye_r[z] <= #TCQ 1'b0;\n pb_found_edge_r[z] <= #TCQ 1'b1;\n pb_detect_edge_done_r[z] <= #TCQ 1'b1;\n end\n end else if (prev_sr_diff_r[z]) begin\n // If we find that the current tap read data jitters, then\n // set edge and jitter found flags, \"enable\" the eye size\n // counter, and stop sampling interval for this bit\n pb_cnt_eye_size_r[z] <= #TCQ 5'd0;\n pb_found_stable_eye_r[z] <= #TCQ 1'b0;\n pb_last_tap_jitter_r[z] <= #TCQ 1'b1;\n pb_found_edge_r[z] <= #TCQ 1'b1;\n pb_found_first_edge_r[z] <= #TCQ 1'b1;\n pb_detect_edge_done_r[z] <= #TCQ 1'b1;\n end else if (old_sr_diff_r[z] || pb_last_tap_jitter_r[z]) begin\n // If either an edge was found (i.e. difference between\n // current tap and previous tap read data), or the previous\n // tap exhibited jitter (which means by definition that the\n // current tap cannot match the previous tap because the\n // previous tap gave unstable data), then set the edge found\n // flag, and \"enable\" eye size counter. But do not stop\n // sampling interval - we still need to check if the current\n // tap exhibits jitter\n pb_cnt_eye_size_r[z] <= #TCQ 5'd0;\n pb_found_stable_eye_r[z] <= #TCQ 1'b0;\n pb_found_edge_r[z] <= #TCQ 1'b1;\n pb_found_first_edge_r[z] <= #TCQ 1'b1;\n end\n end\n end else begin\n // Before every edge detection interval, reset \"intra-tap\" flags\n pb_found_edge_r[z] <= #TCQ 1'b0;\n pb_detect_edge_done_r[z] <= #TCQ 1'b0;\n end\n end\n end\n endgenerate\n\n // Combine the above per-bit status flags into combined terms when\n // performing deskew on the aggregate data window\n always @(posedge clk) begin\n detect_edge_done_r <= #TCQ &pb_detect_edge_done_r;\n found_edge_r <= #TCQ |pb_found_edge_r;\n found_edge_all_r <= #TCQ &pb_found_edge_r;\n found_stable_eye_r <= #TCQ &pb_found_stable_eye_r;\n end\n\n // last IODELAY \"stable eye\" indicator is updated only after\n // detect_edge_done_r is asserted - so that when we do find the \"right edge\"\n // of the data valid window, found_edge_r = 1, AND found_stable_eye_r = 1\n // when detect_edge_done_r = 1 (otherwise, if found_stable_eye_r updates\n // immediately, then it never possible to have found_stable_eye_r = 1\n // when we detect an edge - and we'll never know whether we've found\n // a \"right edge\")\n always @(posedge clk)\n if (pb_detect_edge_setup)\n found_stable_eye_last_r <= #TCQ 1'b0;\n else if (detect_edge_done_r)\n found_stable_eye_last_r <= #TCQ found_stable_eye_r;\n\n //*****************************************************************\n // Keep track of DQ IDELAYE2 taps used\n //*****************************************************************\n\n // Added additional register stage to improve timing\n always @(posedge clk)\n if (rst)\n idelay_tap_cnt_slice_r <= 5'h0;\n else\n idelay_tap_cnt_slice_r <= idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing];\n\n always @(posedge clk)\n if (rst || (SIM_CAL_OPTION == \"SKIP_CAL\")) begin //|| new_cnt_cpt_r\n for (s = 0; s < RANKS; s = s + 1) begin\n for (t = 0; t < DQS_WIDTH; t = t + 1) begin\n idelay_tap_cnt_r[s][t] <= #TCQ idelaye2_init_val;\n end\n end\n end else if (SIM_CAL_OPTION == \"FAST_CAL\") begin\n for (u = 0; u < RANKS; u = u + 1) begin\n for (w = 0; w < DQS_WIDTH; w = w + 1) begin\n if (cal1_dq_idel_ce) begin\n if (cal1_dq_idel_inc)\n idelay_tap_cnt_r[u][w] <= #TCQ idelay_tap_cnt_r[u][w] + 1;\n else\n idelay_tap_cnt_r[u][w] <= #TCQ idelay_tap_cnt_r[u][w] - 1;\n end\n end\n end\n end else if ((rnk_cnt_r == RANKS-1) && (RANKS == 2) &&\n rdlvl_rank_done_r && (cal1_state_r == CAL1_IDLE)) begin\n for (f = 0; f < DQS_WIDTH; f = f + 1) begin\n idelay_tap_cnt_r[rnk_cnt_r][f] <= #TCQ idelay_tap_cnt_r[(rnk_cnt_r-1)][f];\n end\n end else if (cal1_dq_idel_ce) begin\n if (cal1_dq_idel_inc)\n idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] <= #TCQ idelay_tap_cnt_slice_r + 5'h1;\n else\n idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] <= #TCQ idelay_tap_cnt_slice_r - 5'h1;\n end else if (idelay_ld)\n idelay_tap_cnt_r[0][wrcal_cnt] <= #TCQ 5'b00000;\n\n always @(posedge clk)\n if (rst || new_cnt_cpt_r)\n idelay_tap_limit_r <= #TCQ 1'b0;\n else if (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_r] == 'd31)\n idelay_tap_limit_r <= #TCQ 1'b1;\n\n //*****************************************************************\n // keep track of edge tap counts found, and current capture clock\n // tap count\n //*****************************************************************\n\n always @(posedge clk)\n if (rst || new_cnt_cpt_r ||\n (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2))\n tap_cnt_cpt_r <= #TCQ 'b0;\n else if (cal1_dlyce_cpt_r) begin\n if (cal1_dlyinc_cpt_r)\n tap_cnt_cpt_r <= #TCQ tap_cnt_cpt_r + 1;\n else if (tap_cnt_cpt_r != 'd0)\n tap_cnt_cpt_r <= #TCQ tap_cnt_cpt_r - 1;\n end\n\n always @(posedge clk)\n if (rst || new_cnt_cpt_r ||\n (cal1_state_r1 == CAL1_DQ_IDEL_TAP_INC) ||\n (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2))\n tap_limit_cpt_r <= #TCQ 1'b0;\n else if (tap_cnt_cpt_r == 6'd63)\n tap_limit_cpt_r <= #TCQ 1'b1;\n\n always @(posedge clk)\n cal1_cnt_cpt_timing_r <= #TCQ cal1_cnt_cpt_r;\n\n assign cal1_cnt_cpt_timing = {2'b00, cal1_cnt_cpt_r};\n\n // Storing DQS tap values at the end of each DQS read leveling\n always @(posedge clk) begin\n if (rst) begin\n for (a = 0; a < RANKS; a = a + 1) begin: rst_rdlvl_dqs_tap_count_loop\n for (b = 0; b < DQS_WIDTH; b = b + 1)\n rdlvl_dqs_tap_cnt_r[a][b] <= #TCQ 'b0;\n end\n end else if ((SIM_CAL_OPTION == \"FAST_CAL\") & (cal1_state_r1 == CAL1_NEXT_DQS)) begin\n for (p = 0; p < RANKS; p = p +1) begin: rdlvl_dqs_tap_rank_cnt\n for(q = 0; q < DQS_WIDTH; q = q +1) begin: rdlvl_dqs_tap_cnt\n rdlvl_dqs_tap_cnt_r[p][q] <= #TCQ tap_cnt_cpt_r;\n end\n end\n end else if (SIM_CAL_OPTION == \"SKIP_CAL\") begin\n for (j = 0; j < RANKS; j = j +1) begin: rdlvl_dqs_tap_rnk_cnt\n for(i = 0; i < DQS_WIDTH; i = i +1) begin: rdlvl_dqs_cnt\n rdlvl_dqs_tap_cnt_r[j][i] <= #TCQ 6'd31;\n end\n end\n end else if (cal1_state_r1 == CAL1_NEXT_DQS) begin\n rdlvl_dqs_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing_r] <= #TCQ tap_cnt_cpt_r;\n end\n end\n\n\n // Counter to track maximum DQ IODELAY tap usage during the per-bit\n // deskew portion of stage 1 calibration\n always @(posedge clk)\n if (rst) begin\n idel_tap_cnt_dq_pb_r <= #TCQ 'b0;\n idel_tap_limit_dq_pb_r <= #TCQ 1'b0;\n end else\n if (new_cnt_cpt_r) begin\n idel_tap_cnt_dq_pb_r <= #TCQ 'b0;\n idel_tap_limit_dq_pb_r <= #TCQ 1'b0;\n end else if (|cal1_dlyce_dq_r) begin\n if (cal1_dlyinc_dq_r)\n idel_tap_cnt_dq_pb_r <= #TCQ idel_tap_cnt_dq_pb_r + 1;\n else\n idel_tap_cnt_dq_pb_r <= #TCQ idel_tap_cnt_dq_pb_r - 1;\n\n if (idel_tap_cnt_dq_pb_r == 31)\n idel_tap_limit_dq_pb_r <= #TCQ 1'b1;\n else\n idel_tap_limit_dq_pb_r <= #TCQ 1'b0;\n end\n\n\n //*****************************************************************\n\n always @(posedge clk) begin\n cal1_state_r1 <= #TCQ cal1_state_r;\n cal1_state_r2 <= #TCQ cal1_state_r1;\n cal1_state_r3 <= #TCQ cal1_state_r2;\n end\n\n always @(posedge clk)\n if (rst) begin\n cal1_cnt_cpt_r <= #TCQ 'b0;\n cal1_dlyce_cpt_r <= #TCQ 1'b0;\n cal1_dlyinc_cpt_r <= #TCQ 1'b0;\n cal1_dq_idel_ce <= #TCQ 1'b0;\n cal1_dq_idel_inc <= #TCQ 1'b0;\n cal1_prech_req_r <= #TCQ 1'b0;\n cal1_state_r <= #TCQ CAL1_IDLE;\n cnt_idel_dec_cpt_r <= #TCQ 6'bxxxxxx;\n found_first_edge_r <= #TCQ 1'b0;\n found_second_edge_r <= #TCQ 1'b0;\n right_edge_taps_r <= #TCQ 6'b000000;\n first_edge_taps_r <= #TCQ 6'bxxxxxx;\n new_cnt_cpt_r <= #TCQ 1'b0;\n rdlvl_stg1_done_int <= #TCQ 1'b0;\n rdlvl_stg1_err <= #TCQ 1'b0;\n second_edge_taps_r <= #TCQ 6'bxxxxxx;\n store_sr_req_pulsed_r <= #TCQ 1'b0;\n store_sr_req_r <= #TCQ 1'b0;\n rnk_cnt_r <= #TCQ 2'b00;\n rdlvl_rank_done_r <= #TCQ 1'b0;\n idel_dec_cnt <= #TCQ 'd0;\n rdlvl_last_byte_done_int <= #TCQ 1'b0;\n idel_pat_detect_valid_r <= #TCQ 1'b0;\n mpr_rank_done_r <= #TCQ 1'b0;\n mpr_last_byte_done <= #TCQ 1'b0;\n idel_adj_inc <= #TCQ 1'b0;\n if (OCAL_EN == \"ON\")\n mpr_rdlvl_done_r <= #TCQ 1'b0;\n else\n mpr_rdlvl_done_r <= #TCQ 1'b1;\n mpr_dec_cpt_r <= #TCQ 1'b0;\n rdlvl_pi_incdec <= #TCQ 1'b0;\n end else begin\n // default (inactive) states for all \"pulse\" outputs\n // verilint STARC-2.2.3.3 off\n cal1_prech_req_r <= #TCQ 1'b0;\n cal1_dlyce_cpt_r <= #TCQ 1'b0;\n cal1_dlyinc_cpt_r <= #TCQ 1'b0;\n cal1_dq_idel_ce <= #TCQ 1'b0;\n cal1_dq_idel_inc <= #TCQ 1'b0;\n new_cnt_cpt_r <= #TCQ 1'b0;\n store_sr_req_pulsed_r <= #TCQ 1'b0;\n store_sr_req_r <= #TCQ 1'b0;\n\n case (cal1_state_r)\n\n CAL1_IDLE: begin\n rdlvl_rank_done_r <= #TCQ 1'b0;\n rdlvl_last_byte_done_int <= #TCQ 1'b0;\n mpr_rank_done_r <= #TCQ 1'b0;\n mpr_last_byte_done <= #TCQ 1'b0;\n if (mpr_rdlvl_start && ~mpr_rdlvl_start_r) begin\n rdlvl_pi_incdec <= #TCQ 1'b0;\n cal1_state_r <= #TCQ CAL1_MPR_NEW_DQS_WAIT;\n end else begin\n rdlvl_pi_incdec <= #TCQ 1'b1;\n if (rdlvl_stg1_start && ~rdlvl_stg1_start_r) begin\n if (SIM_CAL_OPTION == \"SKIP_CAL\")\n cal1_state_r <= #TCQ CAL1_REGL_LOAD;\n else if (SIM_CAL_OPTION == \"FAST_CAL\")\n cal1_state_r <= #TCQ CAL1_NEXT_DQS;\n else begin\n new_cnt_cpt_r <= #TCQ 1'b1;\n cal1_state_r <= #TCQ CAL1_NEW_DQS_WAIT;\n end\n end\n end\n end\n\n CAL1_MPR_NEW_DQS_WAIT: begin\n cal1_prech_req_r <= #TCQ 1'b0;\n if (!cal1_wait_r && mpr_valid_r)\n cal1_state_r <= #TCQ CAL1_MPR_PAT_DETECT;\n end\n\n // Wait for the new DQS group to change\n // also gives time for the read data IN_FIFO to\n // output the updated data for the new DQS group\n CAL1_NEW_DQS_WAIT: begin\n rdlvl_rank_done_r <= #TCQ 1'b0;\n rdlvl_last_byte_done_int <= #TCQ 1'b0;\n mpr_rank_done_r <= #TCQ 1'b0;\n mpr_last_byte_done <= #TCQ 1'b0;\n cal1_prech_req_r <= #TCQ 1'b0;\n if (|pi_counter_read_val) begin //VK_REVIEW\n mpr_dec_cpt_r <= #TCQ 1'b1;\n cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT;\n cnt_idel_dec_cpt_r <= #TCQ pi_counter_read_val;\n rdlvl_pi_incdec <= #TCQ 1'b1; //every byte dec first so no read needed\n end else if (!cal1_wait_r) begin\n rdlvl_pi_incdec <= #TCQ 1'b0;\n\n // Store \"previous tap\" read data. Technically there is no\n // \"previous\" read data, since we are starting a new DQS\n // group, so we'll never find an edge at tap 0 unless the\n // data is fluctuating/jittering\n store_sr_req_r <= #TCQ 1'b1;\n // If per-bit deskew is disabled, then skip the first\n // portion of stage 1 calibration\n if (PER_BIT_DESKEW == \"OFF\")\n cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT;\n else if (PER_BIT_DESKEW == \"ON\")\n cal1_state_r <= #TCQ CAL1_PB_STORE_FIRST_WAIT;\n end else\n rdlvl_pi_incdec <= #TCQ 1'b1; //every byte dec first so no read needed\n end\n //*****************************************************************\n // Per-bit deskew states\n //*****************************************************************\n\n // Wait state following storage of initial read data\n CAL1_PB_STORE_FIRST_WAIT:\n if (!cal1_wait_r)\n cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE;\n\n // Look for an edge on all DQ bits in current DQS group\n CAL1_PB_DETECT_EDGE:\n if (detect_edge_done_r) begin\n if (found_stable_eye_r) begin\n // If we've found the left edge for all bits (or more precisely,\n // we've found the left edge, and then part of the stable\n // window thereafter), then proceed to positioning the CPT clock\n // right before the left margin\n cnt_idel_dec_cpt_r <= #TCQ MIN_EYE_SIZE + 1;\n cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_LEFT;\n end else begin\n // If we've reached the end of the sampling time, and haven't\n // yet found the left margin of all the DQ bits, then:\n if (!tap_limit_cpt_r) begin\n // If we still have taps left to use, then store current value\n // of read data, increment the capture clock, and continue to\n // look for (left) edges\n store_sr_req_r <= #TCQ 1'b1;\n cal1_state_r <= #TCQ CAL1_PB_INC_CPT;\n end else begin\n // If we ran out of taps moving the capture clock, and we\n // haven't finished edge detection, then reset the capture\n // clock taps to 0 (gradually, one tap at a time...\n // then exit the per-bit portion of the algorithm -\n // i.e. proceed to adjust the capture clock and DQ IODELAYs as\n cnt_idel_dec_cpt_r <= #TCQ 6'd63;\n cal1_state_r <= #TCQ CAL1_PB_DEC_CPT;\n end\n end\n end\n\n // Increment delay for DQS\n CAL1_PB_INC_CPT: begin\n cal1_dlyce_cpt_r <= #TCQ 1'b1;\n cal1_dlyinc_cpt_r <= #TCQ 1'b1;\n cal1_state_r <= #TCQ CAL1_PB_INC_CPT_WAIT;\n end\n\n // Wait for IODELAY for both capture and internal nodes within\n // ISERDES to settle, before checking again for an edge\n CAL1_PB_INC_CPT_WAIT: begin\n cal1_dlyce_cpt_r <= #TCQ 1'b0;\n cal1_dlyinc_cpt_r <= #TCQ 1'b0;\n if (!cal1_wait_r) begin\n cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE;\n\n end\n end\n // We've found the left edges of the windows for all DQ bits\n // (actually, we found it MIN_EYE_SIZE taps ago) Decrement capture\n // clock IDELAY to position just outside left edge of data window\n CAL1_PB_DEC_CPT_LEFT:\n if (cnt_idel_dec_cpt_r == 6'b000000)\n cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_LEFT_WAIT;\n else begin\n cal1_dlyce_cpt_r <= #TCQ 1'b1;\n cal1_dlyinc_cpt_r <= #TCQ 1'b0;\n cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1;\n end\n\n CAL1_PB_DEC_CPT_LEFT_WAIT:\n if (!cal1_wait_r)\n cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE_DQ;\n\n // If there is skew between individual DQ bits, then after we've\n // positioned the CPT clock, we will be \"in the window\" for some\n // DQ bits (\"early\" DQ bits), and \"out of the window\" for others\n // (\"late\" DQ bits). Increase DQ taps until we are out of the\n // window for all DQ bits\n CAL1_PB_DETECT_EDGE_DQ:\n if (detect_edge_done_r)\n if (found_edge_all_r) begin\n // We're out of the window for all DQ bits in this DQS group\n // We're done with per-bit deskew for this group - now decr\n // capture clock IODELAY tap count back to 0, and proceed\n // with the rest of stage 1 calibration for this DQS group\n cnt_idel_dec_cpt_r <= #TCQ tap_cnt_cpt_r;\n cal1_state_r <= #TCQ CAL1_PB_DEC_CPT;\n end else\n if (!idel_tap_limit_dq_pb_r)\n // If we still have DQ taps available for deskew, keep\n // incrementing IODELAY tap count for the appropriate DQ bits\n cal1_state_r <= #TCQ CAL1_PB_INC_DQ;\n else begin\n // Otherwise, stop immediately (we've done the best we can)\n // and proceed with rest of stage 1 calibration\n cnt_idel_dec_cpt_r <= #TCQ tap_cnt_cpt_r;\n cal1_state_r <= #TCQ CAL1_PB_DEC_CPT;\n end\n\n CAL1_PB_INC_DQ: begin\n // Increment only those DQ for which an edge hasn't been found yet\n cal1_dlyce_dq_r <= #TCQ ~pb_found_edge_last_r;\n cal1_dlyinc_dq_r <= #TCQ 1'b1;\n cal1_state_r <= #TCQ CAL1_PB_INC_DQ_WAIT;\n end\n\n CAL1_PB_INC_DQ_WAIT:\n if (!cal1_wait_r)\n cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE_DQ;\n\n // Decrement capture clock taps back to initial value\n CAL1_PB_DEC_CPT:\n if (cnt_idel_dec_cpt_r == 6'b000000)\n cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_WAIT;\n else begin\n cal1_dlyce_cpt_r <= #TCQ 1'b1;\n cal1_dlyinc_cpt_r <= #TCQ 1'b0;\n cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1;\n end\n\n // Wait for capture clock to settle, then proceed to rest of\n // state 1 calibration for this DQS group\n CAL1_PB_DEC_CPT_WAIT:\n if (!cal1_wait_r) begin\n store_sr_req_r <= #TCQ 1'b1;\n cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT;\n end\n\n // When first starting calibration for a DQS group, save the\n // current value of the read data shift register, and use this\n // as a reference. Note that for the first iteration of the\n // edge detection loop, we will in effect be checking for an edge\n // at IODELAY taps = 0 - normally, we are comparing the read data\n // for IODELAY taps = N, with the read data for IODELAY taps = N-1\n // An edge can only be found at IODELAY taps = 0 if the read data\n // is changing during this time (possible due to jitter)\n CAL1_STORE_FIRST_WAIT: begin\n mpr_dec_cpt_r <= #TCQ 1'b0;\n if (!cal1_wait_r)\n cal1_state_r <= #TCQ CAL1_PAT_DETECT;\n end\n\n CAL1_VALID_WAIT: begin\n if (!cal1_wait_r)\n cal1_state_r <= #TCQ CAL1_MPR_PAT_DETECT;\n end\n\n CAL1_MPR_PAT_DETECT: begin\n rdlvl_pi_incdec <= #TCQ 1'b0;\n // MPR read leveling for centering DQS in valid window before\n // OCLKDELAYED calibration begins in order to eliminate read issues\n if (idel_pat_detect_valid_r == 1'b0) begin\n cal1_state_r <= #TCQ CAL1_VALID_WAIT;\n idel_pat_detect_valid_r <= #TCQ 1'b1;\n end else if (idel_pat_detect_valid_r && idel_mpr_pat_detect_r) begin\n cal1_state_r <= #TCQ CAL1_DETECT_EDGE;\n idel_dec_cnt <= #TCQ 'd0;\n end else if (!idelay_tap_limit_r)\n cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_INC;\n else\n cal1_state_r <= #TCQ CAL1_RDLVL_ERR;\n end\n\n CAL1_PAT_DETECT: begin\n // All DQ bits associated with a DQS are pushed to the right one IDELAY\n // tap at a time until first rising DQS is in the tri-state region\n // before first rising edge window.\n // The detect_edge_done_r condition included to support averaging\n // during IDELAY tap increments\n rdlvl_pi_incdec <= #TCQ 1'b0;\n if (detect_edge_done_r) begin\n if (idel_pat_data_match) begin\n case (idelay_adj)\n 2'b01: begin\n cal1_state_r <= CAL1_DQ_IDEL_TAP_INC;\n idel_dec_cnt <= #TCQ 5'd0;\n idel_adj_inc <= #TCQ 1'b1;\n end\n 2'b10: begin //DEC by 1\n cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC ;\n idel_dec_cnt <= #TCQ 5'd1;\n idel_adj_inc <= #TCQ 1'b0;\n end\n default: begin\n cal1_state_r <= #TCQ CAL1_DETECT_EDGE;\n idel_dec_cnt <= #TCQ 5'd0;\n idel_adj_inc <= #TCQ 1'b0;\n end\n endcase\n end else if (!idelay_tap_limit_r) begin\n cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_INC;\n end else begin\n cal1_state_r <= #TCQ CAL1_RDLVL_ERR;\n end\n end\n end\n\n // Increment IDELAY tap by 1 for DQ bits in the byte being calibrated\n // until left edge of valid window detected\n CAL1_DQ_IDEL_TAP_INC: begin\n cal1_dq_idel_ce <= #TCQ 1'b1;\n cal1_dq_idel_inc <= #TCQ 1'b1;\n cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_INC_WAIT;\n idel_pat_detect_valid_r <= #TCQ 1'b0;\n end\n\n CAL1_DQ_IDEL_TAP_INC_WAIT: begin\n cal1_dq_idel_ce <= #TCQ 1'b0;\n cal1_dq_idel_inc <= #TCQ 1'b0;\n if (!cal1_wait_r) begin\n idel_adj_inc <= #TCQ 1'b0;\n if (idel_adj_inc)\n cal1_state_r <= #TCQ CAL1_DETECT_EDGE;\n else if (~mpr_rdlvl_done_r & (DRAM_TYPE == \"DDR3\"))\n cal1_state_r <= #TCQ CAL1_MPR_PAT_DETECT;\n else\n cal1_state_r <= #TCQ CAL1_PAT_DETECT;\n end\n end\n\n // Decrement by 2 IDELAY taps once idel_pat_data_match detected\n CAL1_DQ_IDEL_TAP_DEC: begin\n cal1_dq_idel_inc <= #TCQ 1'b0;\n cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC_WAIT;\n if (idel_dec_cnt >= 'd0)\n cal1_dq_idel_ce <= #TCQ 1'b1;\n else\n cal1_dq_idel_ce <= #TCQ 1'b0;\n if (idel_dec_cnt > 'd0)\n idel_dec_cnt <= #TCQ idel_dec_cnt - 1;\n else\n idel_dec_cnt <= #TCQ idel_dec_cnt;\n end\n\n CAL1_DQ_IDEL_TAP_DEC_WAIT: begin\n cal1_dq_idel_ce <= #TCQ 1'b0;\n cal1_dq_idel_inc <= #TCQ 1'b0;\n if (!cal1_wait_r) begin\n if ((idel_dec_cnt > 'd0) || (pi_rdval_cnt > 'd0))\n cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC;\n else if (mpr_dec_cpt_r)\n cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT;\n else\n cal1_state_r <= #TCQ CAL1_DETECT_EDGE;\n end\n end\n\n // Check for presence of data eye edge. During this state, we\n // sample the read data multiple times, and look for changes\n // in the read data, specifically:\n // 1. A change in the read data compared with the value of\n // read data from the previous delay tap. This indicates\n // that the most recent tap delay increment has moved us\n // into either a new window, or moved/kept us in the\n // transition/jitter region between windows. Note that this\n // condition only needs to be checked for once, and for\n // logistical purposes, we check this soon after entering\n // this state (see comment in CAL1_DETECT_EDGE below for\n // why this is done)\n // 2. A change in the read data while we are in this state\n // (i.e. in the absence of a tap delay increment). This\n // indicates that we're close enough to a window edge that\n // jitter will cause the read data to change even in the\n // absence of a tap delay change\n CAL1_DETECT_EDGE: begin\n // Essentially wait for the first comparision to finish, then\n // store current data into \"old\" data register. This store\n // happens now, rather than later (e.g. when we've have already\n // left this state) in order to avoid the situation the data that\n // is stored as \"old\" data has not been used in an \"active\n // comparison\" - i.e. data is stored after the last comparison\n // of this state. In this case, we can miss an edge if the\n // following sequence occurs:\n // 1. Comparison completes in this state - no edge found\n // 2. \"Momentary jitter\" occurs which \"pushes\" the data out the\n // equivalent of one delay tap\n // 3. We store this jittered data as the \"old\" data\n // 4. \"Jitter\" no longer present\n // 5. We increment the delay tap by one\n // 6. Now we compare the current with the \"old\" data - they're\n // the same, and no edge is detected\n // NOTE: Given the large # of comparisons done in this state, it's\n // highly unlikely the above sequence will occur in actual H/W\n\n // Wait for the first load of read data into the comparison\n // shift register to finish, then load the current read data\n // into the \"old\" data register. This allows us to do one\n // initial comparision between the current read data, and\n // stored data corresponding to the previous delay tap\n idel_pat_detect_valid_r <= #TCQ 1'b0;\n if (!store_sr_req_pulsed_r) begin\n // Pulse store_sr_req_r only once in this state\n store_sr_req_r <= #TCQ 1'b1;\n store_sr_req_pulsed_r <= #TCQ 1'b1;\n end else begin\n store_sr_req_r <= #TCQ 1'b0;\n store_sr_req_pulsed_r <= #TCQ 1'b1;\n end\n\n // Continue to sample read data and look for edges until the\n // appropriate time interval (shorter for simulation-only,\n // much, much longer for actual h/w) has elapsed\n if (detect_edge_done_r) begin\n if (tap_limit_cpt_r)\n // Only one edge detected and ran out of taps since only one\n // bit time worth of taps available for window detection. This\n // can happen if at tap 0 DQS is in previous window which results\n // in only left edge being detected. Or at tap 0 DQS is in the\n // current window resulting in only right edge being detected.\n // Depending on the frequency this case can also happen if at\n // tap 0 DQS is in the left noise region resulting in only left\n // edge being detected.\n cal1_state_r <= #TCQ CAL1_CALC_IDEL;\n else if (found_edge_r) begin\n // Sticky bit - asserted after we encounter an edge, although\n // the current edge may not be considered the \"first edge\" this\n // just means we found at least one edge\n found_first_edge_r <= #TCQ 1'b1;\n\n // Only the right edge of the data valid window is found\n // Record the inner right edge tap value\n if (!found_first_edge_r && found_stable_eye_last_r) begin\n if (tap_cnt_cpt_r == 'd0)\n right_edge_taps_r <= #TCQ 'd0;\n else\n right_edge_taps_r <= #TCQ tap_cnt_cpt_r;\n end\n\n // Both edges of data valid window found:\n // If we've found a second edge after a region of stability\n // then we must have just passed the second (\"right\" edge of\n // the window. Record this second_edge_taps = current tap-1,\n // because we're one past the actual second edge tap, where\n // the edge taps represent the extremes of the data valid\n // window (i.e. smallest & largest taps where data still valid\n if (found_first_edge_r && found_stable_eye_last_r) begin\n found_second_edge_r <= #TCQ 1'b1;\n second_edge_taps_r <= #TCQ tap_cnt_cpt_r - 1;\n cal1_state_r <= #TCQ CAL1_CALC_IDEL;\n end else begin\n // Otherwise, an edge was found (just not the \"second\" edge)\n // Assuming DQS is in the correct window at tap 0 of Phaser IN\n // fine tap. The first edge found is the right edge of the valid\n // window and is the beginning of the jitter region hence done!\n first_edge_taps_r <= #TCQ tap_cnt_cpt_r;\n //wait for read stop before PI increament\n cal1_state_r <= #TCQ CAL1_RD_STOP_FOR_PI_INC;\n end\n end else\n // Otherwise, if we haven't found an edge....\n // If we still have taps left to use, then keep incrementing\n //wait for read stop before PI increament\n cal1_state_r <= #TCQ CAL1_RD_STOP_FOR_PI_INC;\n end\n end\n\n //before increment PI, read command sending should be stopped.\n //Also need to wait existing read is finished\n CAL1_RD_STOP_FOR_PI_INC: begin\n rdlvl_pi_incdec <= #TCQ 1'b1;\n if (!cal1_wait_r)\n cal1_state_r <= #TCQ CAL1_IDEL_INC_CPT;\n end\n\n // Increment Phaser_IN delay for DQS\n CAL1_IDEL_INC_CPT: begin\n cal1_state_r <= #TCQ CAL1_IDEL_INC_CPT_WAIT;\n if (~tap_limit_cpt_r) begin\n cal1_dlyce_cpt_r <= #TCQ 1'b1;\n cal1_dlyinc_cpt_r <= #TCQ 1'b1;\n end else begin\n cal1_dlyce_cpt_r <= #TCQ 1'b0;\n cal1_dlyinc_cpt_r <= #TCQ 1'b0;\n end\n end\n\n // Wait for Phaser_In to settle, before checking again for an edge\n CAL1_IDEL_INC_CPT_WAIT: begin\n cal1_dlyce_cpt_r <= #TCQ 1'b0;\n cal1_dlyinc_cpt_r <= #TCQ 1'b0;\n if (!cal1_wait_r) begin\n cal1_state_r <= #TCQ CAL1_DETECT_EDGE;\n rdlvl_pi_incdec <= #TCQ 1'b0; //return to normal read\n end\n end\n\n // Calculate final value of Phaser_IN taps. At this point, one or both\n // edges of data eye have been found, and/or all taps have been\n // exhausted looking for the edges\n // NOTE: We're calculating the amount to decrement by, not the\n // absolute setting for DQS.\n CAL1_CALC_IDEL: begin\n // CASE1: If 2 edges found.\n if (found_second_edge_r)\n cnt_idel_dec_cpt_r\n <= #TCQ ((second_edge_taps_r -\n first_edge_taps_r)>>1) + 1;\n else if (right_edge_taps_r > 6'd0)\n // Only right edge detected\n // right_edge_taps_r is the inner right edge tap value\n // hence used for calculation\n cnt_idel_dec_cpt_r\n <= #TCQ (tap_cnt_cpt_r - (right_edge_taps_r>>1));\n else if (found_first_edge_r)\n // Only left edge detected\n cnt_idel_dec_cpt_r\n <= #TCQ ((tap_cnt_cpt_r - first_edge_taps_r)>>1);\n else\n cnt_idel_dec_cpt_r\n <= #TCQ (tap_cnt_cpt_r>>1);\n // Now use the value we just calculated to decrement CPT taps\n // to the desired calibration point\n //cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT;\n cal1_state_r <= #TCQ CAL1_CENTER_WAIT;\n rdlvl_pi_incdec <= #TCQ 1'b1;\n end\n\n CAL1_CENTER_WAIT: begin\n if(!cal1_wait_r)\n cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT;\n end\n // decrement capture clock for final adjustment - center\n // capture clock in middle of data eye. This adjustment will occur\n // only when both the edges are found usign CPT taps. Must do this\n // incrementally to avoid clock glitching (since CPT drives clock\n // divider within each ISERDES)\n CAL1_IDEL_DEC_CPT: begin\n cal1_dlyce_cpt_r <= #TCQ 1'b1;\n cal1_dlyinc_cpt_r <= #TCQ 1'b0;\n // once adjustment is complete, we're done with calibration for\n // this DQS, repeat for next DQS\n cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1;\n if (cnt_idel_dec_cpt_r == 6'b000001) begin\n if (mpr_dec_cpt_r) begin\n if (|idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]) begin\n idel_dec_cnt <= #TCQ idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing];\n cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC;\n end else\n cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT;\n end else\n cal1_state_r <= #TCQ CAL1_NEXT_DQS;\n end else\n cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT_WAIT;\n end\n\n CAL1_IDEL_DEC_CPT_WAIT: begin\n cal1_dlyce_cpt_r <= #TCQ 1'b0;\n cal1_dlyinc_cpt_r <= #TCQ 1'b0;\n if (!cal1_wait_r)\n cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT;\n end\n\n // Determine whether we're done, or have more DQS's to calibrate\n // Also request precharge after every byte, as appropriate\n CAL1_NEXT_DQS: begin\n //if (mpr_rdlvl_done_r || (DRAM_TYPE == \"DDR2\"))\n cal1_prech_req_r <= #TCQ 1'b1;\n //else\n // cal1_prech_req_r <= #TCQ 1'b0;\n cal1_dlyce_cpt_r <= #TCQ 1'b0;\n cal1_dlyinc_cpt_r <= #TCQ 1'b0;\n // Prepare for another iteration with next DQS group\n found_first_edge_r <= #TCQ 1'b0;\n found_second_edge_r <= #TCQ 1'b0;\n first_edge_taps_r <= #TCQ 'd0;\n second_edge_taps_r <= #TCQ 'd0;\n right_edge_taps_r <= #TCQ 'd0;\n if ((SIM_CAL_OPTION == \"FAST_CAL\") ||\n (cal1_cnt_cpt_r >= DQS_WIDTH-1)) begin\n if (mpr_rdlvl_done_r) begin\n rdlvl_last_byte_done_int <= #TCQ 1'b1;\n mpr_last_byte_done <= #TCQ 1'b0;\n end else begin\n rdlvl_last_byte_done_int <= #TCQ 1'b0;\n mpr_last_byte_done <= #TCQ 1'b1;\n end\n end\n\n // Wait until precharge that occurs in between calibration of\n // DQS groups is finished\n if (prech_done) begin // || (~mpr_rdlvl_done_r & (DRAM_TYPE == \"DDR3\"))) begin\n if (SIM_CAL_OPTION == \"FAST_CAL\") begin\n //rdlvl_rank_done_r <= #TCQ 1'b1;\n rdlvl_last_byte_done_int <= #TCQ 1'b0;\n mpr_last_byte_done <= #TCQ 1'b0;\n cal1_state_r <= #TCQ CAL1_DONE; //CAL1_REGL_LOAD;\n end else if (cal1_cnt_cpt_r >= DQS_WIDTH-1) begin\n if (~mpr_rdlvl_done_r) begin\n mpr_rank_done_r <= #TCQ 1'b1;\n // if (rnk_cnt_r == RANKS-1) begin\n // All DQS groups in all ranks done\n cal1_state_r <= #TCQ CAL1_DONE;\n cal1_cnt_cpt_r <= #TCQ 'b0;\n // end else begin\n // // Process DQS groups in next rank\n // rnk_cnt_r <= #TCQ rnk_cnt_r + 1;\n // new_cnt_cpt_r <= #TCQ 1'b1;\n // cal1_cnt_cpt_r <= #TCQ 'b0;\n // cal1_state_r <= #TCQ CAL1_IDLE;\n // end\n end else begin\n // All DQS groups in a rank done\n rdlvl_rank_done_r <= #TCQ 1'b1;\n if (rnk_cnt_r == RANKS-1) begin\n // All DQS groups in all ranks done\n cal1_state_r <= #TCQ CAL1_REGL_LOAD;\n end else begin\n // Process DQS groups in next rank\n rnk_cnt_r <= #TCQ rnk_cnt_r + 1;\n new_cnt_cpt_r <= #TCQ 1'b1;\n cal1_cnt_cpt_r <= #TCQ 'b0;\n cal1_state_r <= #TCQ CAL1_IDLE;\n end\n end\n end else begin\n // Process next DQS group\n new_cnt_cpt_r <= #TCQ 1'b1;\n cal1_cnt_cpt_r <= #TCQ cal1_cnt_cpt_r + 1;\n cal1_state_r <= #TCQ CAL1_NEW_DQS_PREWAIT;\n end\n end\n end\n\n CAL1_NEW_DQS_PREWAIT: begin\n if (!cal1_wait_r) begin\n rdlvl_pi_incdec <= #TCQ 1'b0;\n if (~mpr_rdlvl_done_r & (DRAM_TYPE == \"DDR3\"))\n cal1_state_r <= #TCQ CAL1_MPR_NEW_DQS_WAIT;\n else\n cal1_state_r <= #TCQ CAL1_NEW_DQS_WAIT;\n end\n end\n\n // Load rank registers in Phaser_IN\n CAL1_REGL_LOAD: begin\n rdlvl_rank_done_r <= #TCQ 1'b0;\n mpr_rank_done_r <= #TCQ 1'b0;\n cal1_prech_req_r <= #TCQ 1'b0;\n cal1_cnt_cpt_r <= #TCQ 'b0;\n rnk_cnt_r <= #TCQ 2'b00;\n if ((regl_rank_cnt == RANKS-1) &&\n ((regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1))) begin\n cal1_state_r <= #TCQ CAL1_DONE;\n rdlvl_last_byte_done_int <= #TCQ 1'b0;\n mpr_last_byte_done <= #TCQ 1'b0;\n end else\n cal1_state_r <= #TCQ CAL1_REGL_LOAD;\n end\n\n CAL1_RDLVL_ERR: begin\n rdlvl_stg1_err <= #TCQ 1'b1;\n end\n\n // Done with this stage of calibration\n // if used, allow DEBUG_PORT to control taps\n CAL1_DONE: begin\n mpr_rdlvl_done_r <= #TCQ 1'b1;\n cal1_prech_req_r <= #TCQ 1'b0;\n if (~mpr_rdlvl_done_r && (OCAL_EN==\"ON\") && (DRAM_TYPE == \"DDR3\")) begin\n rdlvl_stg1_done_int <= #TCQ 1'b0;\n cal1_state_r <= #TCQ CAL1_IDLE;\n end else\n rdlvl_stg1_done_int <= #TCQ 1'b1;\n end\n\n endcase\n end\n// verilint STARC-2.2.3.3 on\n\n\n\n\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_tempmon.v", "content": "//*****************************************************************************\n// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor : Xilinx\n// \\ \\ \\/ Version : %version\n// \\ \\ Application : MIG\n// / / Filename : mig_7series_v4_0_ddr_phy_tempmon.v\n// /___/ /\\ Date Last Modified : $date$\n// \\ \\ / \\ Date Created : Dec 20 2013\n// \\___\\/\\___\\\n//\n//Device : 7 Series\n//Design Name : DDR3 SDRAM\n//Purpose : Monitors chip temperature via the XADC and adjusts the\n// stage 2 tap values as appropriate.\n//Reference :\n//Revision History :\n//*****************************************************************************\n\n`timescale 1 ps / 1 ps\n\nmodule mig_7series_v4_0_ddr_phy_tempmon #\n(\n parameter SKIP_CALIB = \"FALSE\",\n parameter TCQ = 100, // Register delay (simulation only)\n // Temperature bands must be in order. To disable bands, set to extreme.\n parameter TEMP_INCDEC = 1465, // Degrees C * 100 (14.65 * 100) \n parameter TEMP_HYST = 1,\n parameter TEMP_MIN_LIMIT = 12'h8ac,\n parameter TEMP_MAX_LIMIT = 12'hca4\n)\n(\n input clk, // Fabric clock\n input rst, // System reset\n input calib_complete, // Calibration complete\n input tempmon_sample_en, // Signal to enable sampling\n input [11:0] device_temp, // Current device temperature\n input [11:0] calib_device_temp, // Calibration device temperature\n output tempmon_pi_f_inc, // Increment PHASER_IN taps\n output tempmon_pi_f_dec, // Decrement PHASER_IN taps\n output tempmon_sel_pi_incdec, // Assume control of PHASER_IN taps\n output tempmon_done_skip\n);\n\n // translate hysteresis into XADC units\n localparam HYST_OFFSET = (TEMP_HYST * 4096) / 504;\n\n localparam TEMP_INCDEC_OFFSET = ((TEMP_INCDEC * 4096) / 50400) ;\n\n // Temperature sampler FSM encoding\n localparam IDLE = 11'b000_0000_0001;\n localparam INIT = 11'b000_0000_0010;\n localparam FOUR_INC = 11'b000_0000_0100;\n localparam THREE_INC = 11'b000_0000_1000;\n localparam TWO_INC = 11'b000_0001_0000;\n localparam ONE_INC = 11'b000_0010_0000;\n localparam NEUTRAL = 11'b000_0100_0000;\n localparam ONE_DEC = 11'b000_1000_0000;\n localparam TWO_DEC = 11'b001_0000_0000;\n localparam THREE_DEC = 11'b010_0000_0000;\n localparam FOUR_DEC = 11'b100_0000_0000;\n\n\n //===========================================================================\n // Reg declarations\n //===========================================================================\n\n // Output port flops. Inc and dec are mutex.\n reg pi_f_dec; // Flop output\n reg pi_f_inc; // Flop output\n reg pi_f_dec_nxt; // FSM output\n reg pi_f_inc_nxt; // FSM output\n\n // FSM state\n reg [10:0] tempmon_state;\n reg [10:0] tempmon_state_nxt;\n\n // FSM output used to capture the initial device termperature\n reg tempmon_state_init;\n\n // Flag to indicate the initial device temperature is captured and normal operation can begin\n reg tempmon_init_complete;\n\n // Temperature band/state boundaries\n reg [11:0] four_inc_max_limit;\n reg [11:0] three_inc_max_limit;\n reg [11:0] two_inc_max_limit;\n reg [11:0] one_inc_max_limit;\n reg [11:0] neutral_max_limit;\n reg [11:0] one_dec_max_limit;\n reg [11:0] two_dec_max_limit;\n reg [11:0] three_dec_max_limit;\n reg [11:0] three_inc_min_limit;\n reg [11:0] two_inc_min_limit;\n reg [11:0] one_inc_min_limit;\n reg [11:0] neutral_min_limit;\n reg [11:0] one_dec_min_limit;\n reg [11:0] two_dec_min_limit;\n reg [11:0] three_dec_min_limit;\n reg [11:0] four_dec_min_limit;\n reg [11:0] device_temp_init;\n\n // Flops for capturing and storing the current device temperature\n reg tempmon_sample_en_101;\n reg tempmon_sample_en_102;\n reg [11:0] device_temp_101;\n reg [11:0] device_temp_capture_102;\n reg update_temp_102;\n\n // Flops for comparing temperature to max limits\n reg temp_cmp_four_inc_max_102;\n reg temp_cmp_three_inc_max_102;\n reg temp_cmp_two_inc_max_102;\n reg temp_cmp_one_inc_max_102;\n reg temp_cmp_neutral_max_102;\n reg temp_cmp_one_dec_max_102;\n reg temp_cmp_two_dec_max_102;\n reg temp_cmp_three_dec_max_102;\n\n // Flops for comparing temperature to min limits\n reg temp_cmp_three_inc_min_102;\n reg temp_cmp_two_inc_min_102;\n reg temp_cmp_one_inc_min_102;\n reg temp_cmp_neutral_min_102;\n reg temp_cmp_one_dec_min_102;\n reg temp_cmp_two_dec_min_102;\n reg temp_cmp_three_dec_min_102;\n reg temp_cmp_four_dec_min_102;\n \n reg calib_complete_r;\n reg tempmon_done;\n reg [2:0] sample_en_cnt;\n \n always @ (posedge clk)\n calib_complete_r <= #TCQ calib_complete;\n\t\n wire [11:0] device_temp_in = ((tempmon_state_init | ~calib_complete_r) & (SKIP_CALIB == \"TRUE\")) ? calib_device_temp : device_temp;\n \n always @ (posedge clk) begin\n if (rst)\n\t sample_en_cnt <= #TCQ 'd0;\n\telse if ((tempmon_sample_en & ~tempmon_sample_en_101) & ((SKIP_CALIB == \"TRUE\")) & (sample_en_cnt < 'd5))\n\t sample_en_cnt <= #TCQ sample_en_cnt + 1;\n end\n \n always @ (posedge clk) begin\n if (rst)\n\t tempmon_done <= #TCQ 1'b0;\n\telse if ((sample_en_cnt == 'd5) & ((SKIP_CALIB == \"TRUE\")))\n\t tempmon_done <= #TCQ 1'b1;\n end\n \n assign tempmon_done_skip = tempmon_done;\n \n //===========================================================================\n // Overview and temperature band limits\n //===========================================================================\n\n // The main feature of the tempmon block is an FSM that tracks the temerature provided by the ADC and decides if the phaser needs to be adjusted. The FSM \n // has nine temperature bands or states, centered around an initial device temperature. The name of each state is the net number of phaser increments or\n // decrements that have been issued in getting to the state. There are two temperature boundaries or limits between adjacent states. These two boundaries are\n // offset by a small amount to provide hysteresis. The max limits are the boundaries that are used to determine when to move to the next higher temperature state\n // and decrement the phaser. The min limits determine when to move to the next lower temperature state and increment the phaser. The limits are calculated when\n // the initial device temperature is taken, and will always be at fixed offsets from the initial device temperature. States with limits below 0C or above\n // 125C will never be entered.\n\n // Temperature lowest highest\n // <------------------------------------------------------------------------------------------------------------------------------------------------>\n //\n // Temp four three two one neutral one two three four\n // band/state inc inc inc inc dec dec dec dec \n // \n // Max limits |<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|\n // Min limits |<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->| |\n // | | | | | | |\n // | | | | | | |\n // three_inc_min_limit | HYST_OFFSET--->| |<-- | four_dec_min_limit |\n // | device_temp_init |\n // four_inc_max_limit three_dec_max_limit\n\n\n\n // Boundaries for moving from lower temp bands to higher temp bands.\n // Note that only three_dec_max_limit can roll over, assuming device_temp_init is between 0C and 125C and TEMP_INCDEC_OFFSET is 14.65C,\n // and none of the min or max limits can roll under. So three_dec_max_limit has a check for being out of the 0x0 to 0xFFF range.\n wire [11:0] four_inc_max_limit_nxt = device_temp_init - 7*TEMP_INCDEC_OFFSET; // upper boundary of lowest temp band\n wire [11:0] three_inc_max_limit_nxt = device_temp_init - 5*TEMP_INCDEC_OFFSET;\n wire [11:0] two_inc_max_limit_nxt = device_temp_init - 3*TEMP_INCDEC_OFFSET;\n wire [11:0] one_inc_max_limit_nxt = device_temp_init - TEMP_INCDEC_OFFSET; \n wire [11:0] neutral_max_limit_nxt = device_temp_init + TEMP_INCDEC_OFFSET; // upper boundary of init temp band\n wire [11:0] one_dec_max_limit_nxt = device_temp_init + 3*TEMP_INCDEC_OFFSET;\n wire [11:0] two_dec_max_limit_nxt = device_temp_init + 5*TEMP_INCDEC_OFFSET;\n wire [12:0] three_dec_max_limit_tmp = device_temp_init + 7*TEMP_INCDEC_OFFSET; // upper boundary of 2nd highest temp band\n wire [11:0] three_dec_max_limit_nxt = three_dec_max_limit_tmp[12] ? 12'hFFF : three_dec_max_limit_tmp[11:0];\n\n\n // Boundaries for moving from higher temp bands to lower temp bands\n wire [11:0] three_inc_min_limit_nxt = four_inc_max_limit - HYST_OFFSET; // lower boundary of 2nd lowest temp band\n wire [11:0] two_inc_min_limit_nxt = three_inc_max_limit - HYST_OFFSET;\n wire [11:0] one_inc_min_limit_nxt = two_inc_max_limit - HYST_OFFSET;\n wire [11:0] neutral_min_limit_nxt = one_inc_max_limit - HYST_OFFSET; // lower boundary of init temp band\n wire [11:0] one_dec_min_limit_nxt = neutral_max_limit - HYST_OFFSET;\n wire [11:0] two_dec_min_limit_nxt = one_dec_max_limit - HYST_OFFSET;\n wire [11:0] three_dec_min_limit_nxt = two_dec_max_limit - HYST_OFFSET;\n wire [11:0] four_dec_min_limit_nxt = three_dec_max_limit - HYST_OFFSET; // lower boundary of highest temp band\n\n\n\n //===========================================================================\n // Capture device temperature\n //===========================================================================\n\n // There is a three stage pipeline used to capture temperature, calculate the next state\n // of the FSM, and update the tempmon outputs.\n //\n // Stage 100 Inputs device_temp and tempmon_sample_en become valid and are flopped.\n // Input device_temp is compared to ADC codes for 0C and 125C and limited\n // at the flop input if needed.\n //\n // Stage 101 The flopped version of device_temp is compared to the FSM temperature band boundaries\n // to determine if a state change is needed. State changes are only enabled on the\n // rising edge of the flopped tempmon_sample_en signal. If there is a state change a phaser\n // increment or decrement signal is generated and flopped.\n //\n // Stage 102 The flopped versions of the phaser inc/dec signals drive the module outputs.\n\n // Limit device_temp to 0C to 125C and assign it to flop input device_temp_100\n // temp C = ( ( ADC CODE * 503.975 ) / 4096 ) - 273.15\n wire device_temp_high = device_temp_in > TEMP_MAX_LIMIT;\n wire device_temp_low = device_temp_in < TEMP_MIN_LIMIT;\n wire [11:0] device_temp_100 = ( { 12 { device_temp_high } } & TEMP_MAX_LIMIT )\n | ( { 12 { device_temp_low } } & TEMP_MIN_LIMIT )\n | ( { 12 { ~device_temp_high & ~device_temp_low } } & device_temp_in );\n\n // Capture/hold the initial temperature used in setting temperature bands and set init complete flag\n // to enable normal sample operation.\n wire [11:0] device_temp_init_nxt = tempmon_state_init ? device_temp_101 : device_temp_init;\n wire tempmon_init_complete_nxt = tempmon_state_init ? 1'b1 : tempmon_init_complete;\n\n // Capture/hold the current temperature on the sample enable signal rising edge after init is complete.\n // The captured current temp is not used functionaly. It is just useful for debug and waveform review.\n wire update_temp_101 = tempmon_init_complete & ~tempmon_sample_en_102 & tempmon_sample_en_101;\n wire [11:0] device_temp_capture_101 = update_temp_101 ? device_temp_101 : device_temp_capture_102;\n\n\n //===========================================================================\n // Generate FSM arc signals\n //===========================================================================\n\n // Temperature comparisons for increasing temperature.\n wire temp_cmp_four_inc_max_101 = device_temp_101 >= four_inc_max_limit ;\n wire temp_cmp_three_inc_max_101 = device_temp_101 >= three_inc_max_limit ;\n wire temp_cmp_two_inc_max_101 = device_temp_101 >= two_inc_max_limit ;\n wire temp_cmp_one_inc_max_101 = device_temp_101 >= one_inc_max_limit ;\n wire temp_cmp_neutral_max_101 = device_temp_101 >= neutral_max_limit ;\n wire temp_cmp_one_dec_max_101 = device_temp_101 >= one_dec_max_limit ;\n wire temp_cmp_two_dec_max_101 = device_temp_101 >= two_dec_max_limit ;\n wire temp_cmp_three_dec_max_101 = device_temp_101 >= three_dec_max_limit ;\n\n // Temperature comparisons for decreasing temperature.\n wire temp_cmp_three_inc_min_101 = device_temp_101 < three_inc_min_limit ;\n wire temp_cmp_two_inc_min_101 = device_temp_101 < two_inc_min_limit ;\n wire temp_cmp_one_inc_min_101 = device_temp_101 < one_inc_min_limit ;\n wire temp_cmp_neutral_min_101 = device_temp_101 < neutral_min_limit ;\n wire temp_cmp_one_dec_min_101 = device_temp_101 < one_dec_min_limit ;\n wire temp_cmp_two_dec_min_101 = device_temp_101 < two_dec_min_limit ;\n wire temp_cmp_three_dec_min_101 = device_temp_101 < three_dec_min_limit ;\n wire temp_cmp_four_dec_min_101 = device_temp_101 < four_dec_min_limit ;\n\n // FSM arcs for increasing temperature.\n wire temp_gte_four_inc_max = update_temp_102 & temp_cmp_four_inc_max_102;\n wire temp_gte_three_inc_max = update_temp_102 & temp_cmp_three_inc_max_102;\n wire temp_gte_two_inc_max = update_temp_102 & temp_cmp_two_inc_max_102;\n wire temp_gte_one_inc_max = update_temp_102 & temp_cmp_one_inc_max_102;\n wire temp_gte_neutral_max = update_temp_102 & temp_cmp_neutral_max_102;\n wire temp_gte_one_dec_max = update_temp_102 & temp_cmp_one_dec_max_102;\n wire temp_gte_two_dec_max = update_temp_102 & temp_cmp_two_dec_max_102;\n wire temp_gte_three_dec_max = update_temp_102 & temp_cmp_three_dec_max_102;\n\n // FSM arcs for decreasing temperature.\n wire temp_lte_three_inc_min = update_temp_102 & temp_cmp_three_inc_min_102;\n wire temp_lte_two_inc_min = update_temp_102 & temp_cmp_two_inc_min_102;\n wire temp_lte_one_inc_min = update_temp_102 & temp_cmp_one_inc_min_102;\n wire temp_lte_neutral_min = update_temp_102 & temp_cmp_neutral_min_102;\n wire temp_lte_one_dec_min = update_temp_102 & temp_cmp_one_dec_min_102;\n wire temp_lte_two_dec_min = update_temp_102 & temp_cmp_two_dec_min_102;\n wire temp_lte_three_dec_min = update_temp_102 & temp_cmp_three_dec_min_102;\n wire temp_lte_four_dec_min = update_temp_102 & temp_cmp_four_dec_min_102;\n\n\n //===========================================================================\n // Implement FSM\n //===========================================================================\n\n // In addition to the nine temperature states, there are also IDLE and INIT states.\n // The INIT state triggers the calculation of the temperature boundaries between the\n // other states. After INIT, the FSM will always go to the NEUTRAL state. There is\n // no timing restriction required between calib_complete and tempmon_sample_en.\n\n always @(*) begin\n\n tempmon_state_nxt = tempmon_state;\n tempmon_state_init = 1'b0;\n pi_f_inc_nxt = 1'b0;\n pi_f_dec_nxt = 1'b0;\n\n casez (tempmon_state)\n IDLE: begin\n if (calib_complete) tempmon_state_nxt = INIT;\n end\n INIT: begin\n tempmon_state_nxt = NEUTRAL;\n tempmon_state_init = 1'b1;\n end\n FOUR_INC: begin\n if (temp_gte_four_inc_max) begin\n\t tempmon_state_nxt = THREE_INC;\n pi_f_dec_nxt = 1'b1;\n end\n end\n THREE_INC: begin\n if (temp_gte_three_inc_max) begin\n\t tempmon_state_nxt = TWO_INC;\n pi_f_dec_nxt = 1'b1;\n end\n\telse if (temp_lte_three_inc_min) begin\n\t tempmon_state_nxt = FOUR_INC;\n pi_f_inc_nxt = 1'b1;\n end\n end\n TWO_INC: begin\n if (temp_gte_two_inc_max) begin\n\t tempmon_state_nxt = ONE_INC;\n pi_f_dec_nxt = 1'b1;\n end\n\telse if (temp_lte_two_inc_min) begin\n\t tempmon_state_nxt = THREE_INC;\n pi_f_inc_nxt = 1'b1;\n end\n end\n ONE_INC: begin\n if (temp_gte_one_inc_max) begin\n\t tempmon_state_nxt = NEUTRAL;\n pi_f_dec_nxt = 1'b1;\n end\n\telse if (temp_lte_one_inc_min) begin\n\t tempmon_state_nxt = TWO_INC;\n pi_f_inc_nxt = 1'b1;\n end\n end\n NEUTRAL: begin\n if (temp_gte_neutral_max) begin\n\t tempmon_state_nxt = ONE_DEC;\n pi_f_dec_nxt = 1'b1;\n end\n\telse if (temp_lte_neutral_min) begin\n\t tempmon_state_nxt = ONE_INC;\n pi_f_inc_nxt = 1'b1;\n end\n end\n ONE_DEC: begin\n if (temp_gte_one_dec_max) begin\n\t tempmon_state_nxt = TWO_DEC;\n pi_f_dec_nxt = 1'b1;\n end\n\telse if (temp_lte_one_dec_min) begin\n\t tempmon_state_nxt = NEUTRAL;\n pi_f_inc_nxt = 1'b1;\n end\n end\n TWO_DEC: begin\n if (temp_gte_two_dec_max) begin\n\t tempmon_state_nxt = THREE_DEC;\n pi_f_dec_nxt = 1'b1;\n end\n\telse if (temp_lte_two_dec_min) begin\n\t tempmon_state_nxt = ONE_DEC;\n pi_f_inc_nxt = 1'b1;\n end\n end\n THREE_DEC: begin\n if (temp_gte_three_dec_max) begin\n\t tempmon_state_nxt = FOUR_DEC;\n pi_f_dec_nxt = 1'b1;\n end\n\telse if (temp_lte_three_dec_min) begin\n\t tempmon_state_nxt = TWO_DEC;\n pi_f_inc_nxt = 1'b1;\n end\n end\n FOUR_DEC: begin\n\tif (temp_lte_four_dec_min) begin\n\t tempmon_state_nxt = THREE_DEC;\n pi_f_inc_nxt = 1'b1;\n end\n end\n default: begin\n\t tempmon_state_nxt = IDLE;\n end\n endcase\n\n end //always\n\n//synopsys translate_off\nreg [71:0] tempmon_state_name;\nalways @(*) casez (tempmon_state)\n IDLE : tempmon_state_name = \"IDLE\";\n INIT : tempmon_state_name = \"INIT\";\n FOUR_INC : tempmon_state_name = \"FOUR_INC\";\n THREE_INC : tempmon_state_name = \"THREE_INC\";\n TWO_INC : tempmon_state_name = \"TWO_INC\";\n ONE_INC : tempmon_state_name = \"ONE_INC\";\n NEUTRAL : tempmon_state_name = \"NEUTRAL\";\n ONE_DEC : tempmon_state_name = \"ONE_DEC\";\n TWO_DEC : tempmon_state_name = \"TWO_DEC\";\n THREE_DEC : tempmon_state_name = \"THREE_DEC\";\n FOUR_DEC : tempmon_state_name = \"FOUR_DEC\";\n default : tempmon_state_name = \"BAD_STATE\";\nendcase\n//synopsys translate_on\n\n //===========================================================================\n // Generate final output and implement flops\n //===========================================================================\n\n // Generate output\n assign tempmon_pi_f_inc = pi_f_inc;\n assign tempmon_pi_f_dec = pi_f_dec;\n assign tempmon_sel_pi_incdec = pi_f_inc | pi_f_dec;\n\n\n // Implement reset flops\n always @(posedge clk) begin\n if(rst) begin\n tempmon_state <= #TCQ 11'b000_0000_0001;\n pi_f_inc <= #TCQ 1'b0;\n pi_f_dec <= #TCQ 1'b0;\n four_inc_max_limit <= #TCQ 12'b0;\n three_inc_max_limit <= #TCQ 12'b0;\n two_inc_max_limit <= #TCQ 12'b0;\n one_inc_max_limit <= #TCQ 12'b0;\n neutral_max_limit <= #TCQ 12'b0;\n one_dec_max_limit <= #TCQ 12'b0;\n two_dec_max_limit <= #TCQ 12'b0;\n three_dec_max_limit <= #TCQ 12'b0;\n three_inc_min_limit <= #TCQ 12'b0;\n two_inc_min_limit <= #TCQ 12'b0;\n one_inc_min_limit <= #TCQ 12'b0;\n neutral_min_limit <= #TCQ 12'b0;\n one_dec_min_limit <= #TCQ 12'b0;\n two_dec_min_limit <= #TCQ 12'b0;\n three_dec_min_limit <= #TCQ 12'b0;\n four_dec_min_limit <= #TCQ 12'b0;\n device_temp_init <= #TCQ 12'b0;\n tempmon_init_complete <= #TCQ 1'b0;\n tempmon_sample_en_101 <= #TCQ 1'b0;\n tempmon_sample_en_102 <= #TCQ 1'b0;\n device_temp_101 <= #TCQ 12'b0;\n device_temp_capture_102 <= #TCQ 12'b0;\n end\n else begin\n tempmon_state <= #TCQ tempmon_state_nxt;\n pi_f_inc <= #TCQ pi_f_inc_nxt;\n pi_f_dec <= #TCQ pi_f_dec_nxt;\n four_inc_max_limit <= #TCQ four_inc_max_limit_nxt;\n three_inc_max_limit <= #TCQ three_inc_max_limit_nxt;\n two_inc_max_limit <= #TCQ two_inc_max_limit_nxt;\n one_inc_max_limit <= #TCQ one_inc_max_limit_nxt;\n neutral_max_limit <= #TCQ neutral_max_limit_nxt;\n one_dec_max_limit <= #TCQ one_dec_max_limit_nxt;\n two_dec_max_limit <= #TCQ two_dec_max_limit_nxt;\n three_dec_max_limit <= #TCQ three_dec_max_limit_nxt;\n three_inc_min_limit <= #TCQ three_inc_min_limit_nxt;\n two_inc_min_limit <= #TCQ two_inc_min_limit_nxt;\n one_inc_min_limit <= #TCQ one_inc_min_limit_nxt;\n neutral_min_limit <= #TCQ neutral_min_limit_nxt;\n one_dec_min_limit <= #TCQ one_dec_min_limit_nxt;\n two_dec_min_limit <= #TCQ two_dec_min_limit_nxt;\n three_dec_min_limit <= #TCQ three_dec_min_limit_nxt;\n four_dec_min_limit <= #TCQ four_dec_min_limit_nxt;\n device_temp_init <= #TCQ device_temp_init_nxt;\n tempmon_init_complete <= #TCQ tempmon_init_complete_nxt;\n tempmon_sample_en_101 <= #TCQ tempmon_sample_en;\n tempmon_sample_en_102 <= #TCQ tempmon_sample_en_101;\n device_temp_101 <= #TCQ device_temp_100;\n device_temp_capture_102 <= #TCQ device_temp_capture_101;\n end\n end\n\n // Implement non-reset flops\n always @(posedge clk) begin\n temp_cmp_four_inc_max_102 <= #TCQ temp_cmp_four_inc_max_101;\n temp_cmp_three_inc_max_102 <= #TCQ temp_cmp_three_inc_max_101;\n temp_cmp_two_inc_max_102 <= #TCQ temp_cmp_two_inc_max_101;\n temp_cmp_one_inc_max_102 <= #TCQ temp_cmp_one_inc_max_101;\n temp_cmp_neutral_max_102 <= #TCQ temp_cmp_neutral_max_101;\n temp_cmp_one_dec_max_102 <= #TCQ temp_cmp_one_dec_max_101;\n temp_cmp_two_dec_max_102 <= #TCQ temp_cmp_two_dec_max_101;\n temp_cmp_three_dec_max_102 <= #TCQ temp_cmp_three_dec_max_101;\n temp_cmp_three_inc_min_102 <= #TCQ temp_cmp_three_inc_min_101;\n temp_cmp_two_inc_min_102 <= #TCQ temp_cmp_two_inc_min_101;\n temp_cmp_one_inc_min_102 <= #TCQ temp_cmp_one_inc_min_101;\n temp_cmp_neutral_min_102 <= #TCQ temp_cmp_neutral_min_101;\n temp_cmp_one_dec_min_102 <= #TCQ temp_cmp_one_dec_min_101;\n temp_cmp_two_dec_min_102 <= #TCQ temp_cmp_two_dec_min_101;\n temp_cmp_three_dec_min_102 <= #TCQ temp_cmp_three_dec_min_101;\n temp_cmp_four_dec_min_102 <= #TCQ temp_cmp_four_dec_min_101;\n update_temp_102 <= #TCQ update_temp_101;\n end\n\n\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_top.v", "content": "//*****************************************************************************\n// (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor : Xilinx\n// \\ \\ \\/ Version : 4.0\n// \\ \\ Application : MIG\n// / / Filename : ddr_phy_top.v\n// /___/ /\\ Date Last Modified : $date$\n// \\ \\ / \\ Date Created : Aug 03 2009\n// \\___\\/\\___\\\n//\n//Device : 7 Series\n//Design Name : DDR3 SDRAM\n//Purpose : Top level memory interface block. Instantiates a clock\n// and reset generator, the memory controller, the phy and\n// the user interface blocks.\n//Reference :\n//Revision History :\n//*****************************************************************************\n\n`timescale 1 ps / 1 ps\n\nmodule mig_7series_v4_0_ddr_phy_top #\n (\n parameter TCQ = 100, // Register delay (simulation only)\n parameter DDR3_VDD_OP_VOLT = 135, // Voltage mode used for DDR3\n parameter AL = \"0\", // Additive Latency option\n parameter BANK_WIDTH = 3, // # of bank bits\n parameter BURST_MODE = \"8\", // Burst length\n parameter BURST_TYPE = \"SEQ\", // Burst type\n parameter CA_MIRROR = \"OFF\", // C/A mirror opt for DDR3 dual rank\n parameter CK_WIDTH = 1, // # of CK/CK# outputs to memory\n parameter CL = 5,\n parameter COL_WIDTH = 12, // column address width\n parameter CS_WIDTH = 1, // # of unique CS outputs\n parameter CKE_WIDTH = 1, // # of cke outputs\n parameter CWL = 5,\n parameter DM_WIDTH = 8, // # of DM (data mask)\n parameter DQ_WIDTH = 64, // # of DQ (data)\n parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))\n parameter DQS_WIDTH = 8, // # of DQS (strobe)\n parameter DRAM_TYPE = \"DDR3\",\n parameter DRAM_WIDTH = 8, // # of DQ per DQS\n parameter MASTER_PHY_CTL = 0, // The bank number where master PHY_CONTROL resides\n parameter LP_DDR_CK_WIDTH = 2,\n\n // Hard PHY parameters\n parameter PHYCTL_CMD_FIFO = \"FALSE\",\n // five fields, one per possible I/O bank, 4 bits in each field,\n // 1 per lane data=1/ctl=0\n parameter DATA_CTL_B0 = 4'hc,\n parameter DATA_CTL_B1 = 4'hf,\n parameter DATA_CTL_B2 = 4'hf,\n parameter DATA_CTL_B3 = 4'hf,\n parameter DATA_CTL_B4 = 4'hf,\n // defines the byte lanes in I/O banks being used in the interface\n // 1- Used, 0- Unused\n parameter BYTE_LANES_B0 = 4'b1111,\n parameter BYTE_LANES_B1 = 4'b0000,\n parameter BYTE_LANES_B2 = 4'b0000,\n parameter BYTE_LANES_B3 = 4'b0000,\n parameter BYTE_LANES_B4 = 4'b0000,\n // defines the bit lanes in I/O banks being used in the interface. Each\n // parameter = 1 I/O bank = 4 byte lanes = 48 bit lanes. 1-Used, 0-Unused\n parameter PHY_0_BITLANES = 48'h0000_0000_0000,\n parameter PHY_1_BITLANES = 48'h0000_0000_0000,\n parameter PHY_2_BITLANES = 48'h0000_0000_0000,\n\n // control/address/data pin mapping parameters\n parameter CK_BYTE_MAP\n = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,\n parameter ADDR_MAP\n = 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,\n parameter BANK_MAP = 36'h000_000_000,\n parameter CAS_MAP = 12'h000,\n parameter CKE_ODT_BYTE_MAP = 8'h00,\n parameter CKE_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter ODT_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter CKE_ODT_AUX = \"FALSE\",\n parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,\n parameter PARITY_MAP = 12'h000,\n parameter RAS_MAP = 12'h000,\n parameter WE_MAP = 12'h000,\n parameter DQS_BYTE_MAP\n = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,\n parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,\n parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,\n parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,\n\n // This parameter must be set based on memory clock frequency\n // It must be set to 4 for frequencies above 533 MHz?? (undecided)\n // and set to 2 for 533 MHz and below\n parameter PRE_REV3ES = \"OFF\", // Delay O/Ps using Phaser_Out fine dly\n parameter nCK_PER_CLK = 2, // # of memory CKs per fabric CLK\n parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank\n parameter ADDR_CMD_MODE = \"1T\", // ADDR/CTRL timing: \"2T\", \"1T\"\n parameter BANK_TYPE = \"HP_IO\", // # = \"HP_IO\", \"HPL_IO\", \"HR_IO\", \"HRL_IO\"\n parameter DATA_IO_PRIM_TYPE = \"DEFAULT\", // # = \"HP_LP\", \"HR_LP\", \"DEFAULT\"\n parameter DATA_IO_IDLE_PWRDWN = \"ON\", // \"ON\" or \"OFF\"\n parameter IODELAY_GRP = \"IODELAY_MIG\",\n parameter FPGA_SPEED_GRADE = 1,\n parameter IBUF_LPWR_MODE = \"OFF\", // input buffer low power option\n parameter OUTPUT_DRV = \"HIGH\", // to calib_top\n parameter REG_CTRL = \"OFF\", // to calib_top\n parameter RTT_NOM = \"60\", // to calib_top\n parameter RTT_WR = \"120\", // to calib_top\n parameter tCK = 2500, // pS\n parameter tRFC = 110000, // pS\n parameter tREFI = 7800000, // pS\n parameter DDR2_DQSN_ENABLE = \"YES\", // Enable differential DQS for DDR2\n parameter WRLVL = \"OFF\", // to calib_top\n parameter DEBUG_PORT = \"OFF\", // to calib_top\n parameter RANKS = 4,\n parameter ODT_WIDTH = 1,\n parameter ROW_WIDTH = 16, // DRAM address bus width\n parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,\n // calibration Address. The address given below will be used for calibration\n // read and write operations.\n parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address\n parameter CALIB_COL_ADD = 12'h000, // Calibration column address\n parameter CALIB_BA_ADD = 3'h0, // Calibration bank address\n // Simulation /debug options\n parameter SIM_BYPASS_INIT_CAL = \"OFF\",\n // Parameter used to force skipping\n // or abbreviation of initialization\n // and calibration. Overrides\n // SIM_INIT_OPTION, SIM_CAL_OPTION,\n // and disables various other blocks\n //parameter SIM_INIT_OPTION = \"SKIP_PU_DLY\", // Skip various init steps\n //parameter SIM_CAL_OPTION = \"NONE\", // Skip various calib steps\n parameter REFCLK_FREQ = 200.0, // IODELAY ref clock freq (MHz)\n parameter USE_CS_PORT = 1, // Support chip select output\n parameter USE_DM_PORT = 1, // Support data mask output\n parameter USE_ODT_PORT = 1, // Support ODT output\n parameter RD_PATH_REG = 0, // optional registers in the read path\n // to MC for timing improvement.\n // =1 enabled, = 0 disabled\n parameter IDELAY_ADJ = \"ON\", //ON : IDELAY-1, OFF: No change\n parameter FINE_PER_BIT = \"ON\", //ON : Use per bit calib for complex rdlvl\n parameter CENTER_COMP_MODE = \"ON\", //ON: use PI stg2 tap compensation\n parameter PI_VAL_ADJ = \"ON\", //ON: PI stg2 tap -1 for centering\n parameter TAPSPERKCLK = 56,\n parameter POC_USE_METASTABLE_SAMP = \"FALSE\",\n parameter SKIP_CALIB = \"FALSE\",\n parameter FPGA_VOLT_TYPE = \"N\"\n )\n (\n input clk, // Fabric logic clock\n // To MC, calib_top, hard PHY\n input clk_div2, // mem_refclk divided by 2 for PI incdec\n input rst_div2, // reset in clk_div2 domain\n input clk_ref, // Idelay_ctrl reference clock\n // To hard PHY (external source)\n input freq_refclk, // To hard PHY for Phasers\n input mem_refclk, // Memory clock to hard PHY\n input pll_lock, // System PLL lock signal\n input sync_pulse, // 1/N sync pulse used to synchronize all PHASERS\n input mmcm_ps_clk, // Phase shift clock for oclk stg3 centering\n input poc_sample_pd, // Tell POC how to avoid metastability.\n\n input error, // Support for TG error detect\n output rst_tg_mc, // Support for TG error detect\n\n input [11:0] device_temp,\n input tempmon_sample_en,\n\n input dbg_sel_pi_incdec,\n input dbg_sel_po_incdec,\n input [DQS_CNT_WIDTH:0] dbg_byte_sel,\n input dbg_pi_f_inc,\n input dbg_pi_f_dec,\n input dbg_po_f_inc,\n input dbg_po_f_stg23_sel,\n input dbg_po_f_dec,\n input dbg_idel_down_all,\n input dbg_idel_down_cpt,\n input dbg_idel_up_all,\n input dbg_idel_up_cpt,\n input dbg_sel_all_idel_cpt,\n input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,\n input rst,\n input iddr_rst,\n input [7:0] slot_0_present,\n input [7:0] slot_1_present,\n // From MC\n input [nCK_PER_CLK-1:0] mc_ras_n,\n input [nCK_PER_CLK-1:0] mc_cas_n,\n input [nCK_PER_CLK-1:0] mc_we_n,\n input [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address,\n input [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank,\n input [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n,\n input mc_reset_n,\n input [1:0] mc_odt,\n input [nCK_PER_CLK-1:0] mc_cke,\n // AUX - For ODT and CKE assertion during reads and writes\n input [3:0] mc_aux_out0,\n input [3:0] mc_aux_out1,\n input mc_cmd_wren,\n input mc_ctl_wren,\n input [2:0] mc_cmd,\n input [1:0] mc_cas_slot,\n input [5:0] mc_data_offset,\n input [5:0] mc_data_offset_1,\n input [5:0] mc_data_offset_2,\n input [1:0] mc_rank_cnt,\n // Write\n input mc_wrdata_en,\n input [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata,\n input [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mc_wrdata_mask,\n input idle,\n // DDR bus signals\n output [ROW_WIDTH-1:0] ddr_addr,\n output [BANK_WIDTH-1:0] ddr_ba,\n output ddr_cas_n,\n output [CK_WIDTH-1:0] ddr_ck_n,\n output [CK_WIDTH-1:0] ddr_ck,\n output [CKE_WIDTH-1:0] ddr_cke,\n output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,\n output [DM_WIDTH-1:0] ddr_dm,\n output [ODT_WIDTH-1:0] ddr_odt,\n output ddr_ras_n,\n output ddr_reset_n,\n output ddr_parity,\n output ddr_we_n,\n inout [DQ_WIDTH-1:0] ddr_dq,\n inout [DQS_WIDTH-1:0] ddr_dqs_n,\n inout [DQS_WIDTH-1:0] ddr_dqs,\n\n // Ports to be used when SKIP_CALIB=\"TRUE\"\n output calib_tap_req,\n input [6:0] calib_tap_addr,\n input calib_tap_load,\n input [7:0] calib_tap_val,\n input calib_tap_load_done,\n\n //phase shift clock control\n output psen,\n output psincdec,\n input psdone,\n // Debug Port Outputs\n output [255:0] dbg_calib_top,\n output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt,\n output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt,\n output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt,\n output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt,\n output [255:0] dbg_phy_rdlvl,\n output [99:0] dbg_phy_wrcal,\n output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,\n output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,\n output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect,\n output [2*nCK_PER_CLK*DQ_WIDTH-1:0] dbg_rddata,\n output dbg_rddata_valid,\n output [1:0] dbg_rdlvl_done,\n output [1:0] dbg_rdlvl_err,\n output [1:0] dbg_rdlvl_start,\n output [5:0] dbg_tap_cnt_during_wrlvl,\n output dbg_wl_edge_detect_valid,\n output dbg_wrlvl_done,\n output dbg_wrlvl_err,\n output dbg_wrlvl_start,\n output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt,\n output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt,\n output [255:0] dbg_phy_wrlvl,\n output dbg_pi_phaselock_start,\n output dbg_pi_phaselocked_done,\n output dbg_pi_phaselock_err,\n output [11:0] dbg_pi_phase_locked_phy4lanes,\n output dbg_pi_dqsfound_start,\n output dbg_pi_dqsfound_done,\n output dbg_pi_dqsfound_err,\n output [11:0] dbg_pi_dqs_found_lanes_phy4lanes,\n output dbg_wrcal_start,\n output dbg_wrcal_done,\n output dbg_wrcal_err,\n output [1023:0] dbg_poc,\n // FIFO status flags\n output phy_mc_ctl_full,\n output phy_mc_cmd_full,\n output phy_mc_data_full,\n // Calibration status and resultant outputs\n output init_calib_complete,\n output init_wrcal_complete,\n output [6*RANKS-1:0] calib_rd_data_offset_0,\n output [6*RANKS-1:0] calib_rd_data_offset_1,\n output [6*RANKS-1:0] calib_rd_data_offset_2,\n output phy_rddata_valid,\n output [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rd_data,\n\n output ref_dll_lock,\n input rst_phaser_ref,\n output [6*RANKS-1:0] dbg_rd_data_offset,\n output [255:0] dbg_phy_init,\n output [255:0] dbg_prbs_rdlvl,\n output [255:0] dbg_dqs_found_cal,\n output [5:0] dbg_pi_counter_read_val,\n output [8:0] dbg_po_counter_read_val,\n output dbg_oclkdelay_calib_start,\n output dbg_oclkdelay_calib_done,\n output [255:0] dbg_phy_oclkdelay_cal,\n output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data,\n output [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r,\n output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps,\n output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps\n );\n\n // Calculate number of slots in the system\n localparam nSLOTS = 1 + (|SLOT_1_CONFIG ? 1 : 0);\n localparam CLK_PERIOD = tCK * nCK_PER_CLK;\n\n // Parameter used to force skipping or abbreviation of initialization\n // and calibration. Overrides SIM_INIT_OPTION, SIM_CAL_OPTION, and\n // disables various other blocks depending on the option selected\n // This option should only be used during simulation. In the case of\n // the \"SKIP\" option, the testbench used should also not be modeling\n // propagation delays.\n // Allowable options = {\"NONE\", \"SIM_FULL\", \"SKIP\", \"FAST\"}\n // \"NONE\" = options determined by the individual parameter settings\n // \"SIM_FULL\" = skip power-up delay. FULL calibration performed without\n // averaging algorithm turned ON during window detection.\n // \"SKIP\" = skip power-up delay. Skip calibration not yet supported.\n // \"FAST\" = skip power-up delay, and calibrate (read leveling, write\n // leveling, and phase detector) only using one DQS group, and\n // apply the results to all other DQS groups.\n localparam SIM_INIT_OPTION\n = ((SIM_BYPASS_INIT_CAL == \"SKIP\") ? \"SKIP_INIT\" :\n ((SIM_BYPASS_INIT_CAL == \"FAST\") ||\n (SIM_BYPASS_INIT_CAL == \"SIM_FULL\")) ? \"SKIP_PU_DLY\" :\n \"NONE\");\n localparam SIM_CAL_OPTION\n = ((SIM_BYPASS_INIT_CAL == \"SKIP\") ? \"SKIP_CAL\" :\n (SIM_BYPASS_INIT_CAL == \"FAST\") ? \"FAST_CAL\" :\n ((SIM_BYPASS_INIT_CAL == \"SIM_FULL\") ||\n (SIM_BYPASS_INIT_CAL == \"SIM_INIT_CAL_FULL\")) ? \"FAST_WIN_DETECT\" :\n \"NONE\");\n localparam WRLVL_W\n = (SIM_BYPASS_INIT_CAL == \"SKIP\") ? \"OFF\" : WRLVL;\n\n localparam HIGHEST_BANK = (BYTE_LANES_B4 != 0 ? 5 : (BYTE_LANES_B3 != 0 ? 4 :\n (BYTE_LANES_B2 != 0 ? 3 :\n (BYTE_LANES_B1 != 0 ? 2 : 1))));\n\n localparam HIGHEST_LANE_B0 = BYTE_LANES_B0[3] ? 4 : BYTE_LANES_B0[2] ? 3 :\n BYTE_LANES_B0[1] ? 2 : BYTE_LANES_B0[0] ? 1 :\n 0;\n localparam HIGHEST_LANE_B1 = BYTE_LANES_B1[3] ? 4 : BYTE_LANES_B1[2] ? 3 :\n BYTE_LANES_B1[1] ? 2 : BYTE_LANES_B1[0] ? 1 :\n 0;\n localparam HIGHEST_LANE_B2 = BYTE_LANES_B2[3] ? 4 : BYTE_LANES_B2[2] ? 3 :\n BYTE_LANES_B2[1] ? 2 : BYTE_LANES_B2[0] ? 1 :\n 0;\n localparam HIGHEST_LANE_B3 = BYTE_LANES_B3[3] ? 4 : BYTE_LANES_B3[2] ? 3 :\n BYTE_LANES_B3[1] ? 2 : BYTE_LANES_B3[0] ? 1 :\n 0;\n localparam HIGHEST_LANE_B4 = BYTE_LANES_B4[3] ? 4 : BYTE_LANES_B4[2] ? 3 :\n BYTE_LANES_B4[1] ? 2 : BYTE_LANES_B4[0] ? 1 :\n 0;\n localparam HIGHEST_LANE =\n (HIGHEST_LANE_B4 != 0) ? (HIGHEST_LANE_B4+16) :\n ((HIGHEST_LANE_B3 != 0) ? (HIGHEST_LANE_B3 + 12) :\n ((HIGHEST_LANE_B2 != 0) ? (HIGHEST_LANE_B2 + 8) :\n ((HIGHEST_LANE_B1 != 0) ? (HIGHEST_LANE_B1 + 4) :\n HIGHEST_LANE_B0)));\n\n localparam N_CTL_LANES = ((0+(!DATA_CTL_B0[0]) & BYTE_LANES_B0[0]) +\n (0+(!DATA_CTL_B0[1]) & BYTE_LANES_B0[1]) +\n (0+(!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) +\n (0+(!DATA_CTL_B0[3]) & BYTE_LANES_B0[3])) +\n ((0+(!DATA_CTL_B1[0]) & BYTE_LANES_B1[0]) +\n (0+(!DATA_CTL_B1[1]) & BYTE_LANES_B1[1]) +\n (0+(!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) +\n (0+(!DATA_CTL_B1[3]) & BYTE_LANES_B1[3])) +\n ((0+(!DATA_CTL_B2[0]) & BYTE_LANES_B2[0]) +\n (0+(!DATA_CTL_B2[1]) & BYTE_LANES_B2[1]) +\n (0+(!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) +\n (0+(!DATA_CTL_B2[3]) & BYTE_LANES_B2[3])) +\n ((0+(!DATA_CTL_B3[0]) & BYTE_LANES_B3[0]) +\n (0+(!DATA_CTL_B3[1]) & BYTE_LANES_B3[1]) +\n (0+(!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) +\n (0+(!DATA_CTL_B3[3]) & BYTE_LANES_B3[3])) +\n ((0+(!DATA_CTL_B4[0]) & BYTE_LANES_B4[0]) +\n (0+(!DATA_CTL_B4[1]) & BYTE_LANES_B4[1]) +\n (0+(!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]) +\n (0+(!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]));\n\n // Assuming Ck/Addr/Cmd and Control are placed in a single IO Bank\n // This should be the case since the PLL should be placed adjacent\n // to the same IO Bank as Ck/Addr/Cmd and Control\n localparam [2:0] CTL_BANK = (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0]) |\n ((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1]) |\n ((!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) |\n ((!DATA_CTL_B0[3]) & BYTE_LANES_B0[3])) ?\n 3'b000 :\n (((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0]) |\n ((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1]) |\n ((!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) |\n ((!DATA_CTL_B1[3]) & BYTE_LANES_B1[3])) ?\n 3'b001 :\n (((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0]) |\n ((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1]) |\n ((!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) |\n ((!DATA_CTL_B2[3]) & BYTE_LANES_B2[3])) ?\n 3'b010 :\n (((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0]) |\n ((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1]) |\n ((!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) |\n ((!DATA_CTL_B3[3]) & BYTE_LANES_B3[3])) ?\n 3'b011 :\n (((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0]) |\n ((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1]) |\n ((!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]) |\n ((!DATA_CTL_B4[3]) & BYTE_LANES_B4[3])) ?\n 3'b100 : 3'b000;\n\n localparam [7:0] CTL_BYTE_LANE = (N_CTL_LANES == 4) ? 8'b11_10_01_00 :\n ((N_CTL_LANES == 3) &\n (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &\n (!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] &\n (!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) |\n ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &\n (!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] &\n (!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) |\n ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &\n (!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] &\n (!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) |\n ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &\n (!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] &\n (!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) |\n ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &\n (!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] &\n (!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]))) ?\n 8'b00_10_01_00 :\n ((N_CTL_LANES == 3) &\n (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &\n (!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] &\n (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |\n ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &\n (!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] &\n (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |\n ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &\n (!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] &\n (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |\n ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &\n (!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] &\n (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |\n ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &\n (!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] &\n (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?\n 8'b00_11_01_00 :\n ((N_CTL_LANES == 3) &\n (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &\n (!DATA_CTL_B0[2]) & BYTE_LANES_B0[2] &\n (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |\n ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &\n (!DATA_CTL_B1[2]) & BYTE_LANES_B1[2] &\n (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |\n ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &\n (!DATA_CTL_B2[2]) & BYTE_LANES_B2[2] &\n (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |\n ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &\n (!DATA_CTL_B3[2]) & BYTE_LANES_B3[2] &\n (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |\n ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &\n (!DATA_CTL_B4[2]) & BYTE_LANES_B4[2] &\n (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?\n 8'b00_11_10_00 :\n ((N_CTL_LANES == 3) &\n (((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] &\n (!DATA_CTL_B0[2]) & BYTE_LANES_B0[2] &\n (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |\n ((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] &\n (!DATA_CTL_B1[2]) & BYTE_LANES_B1[2] &\n (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |\n ((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] &\n (!DATA_CTL_B2[2]) & BYTE_LANES_B2[2] &\n (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |\n ((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] &\n (!DATA_CTL_B3[2]) & BYTE_LANES_B3[2] &\n (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |\n ((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] &\n (!DATA_CTL_B4[2]) & BYTE_LANES_B4[2] &\n (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?\n 8'b00_11_10_01 :\n ((N_CTL_LANES == 2) &\n (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &\n (!DATA_CTL_B0[1]) & BYTE_LANES_B0[1]) |\n ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &\n (!DATA_CTL_B1[1]) & BYTE_LANES_B1[1]) |\n ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &\n (!DATA_CTL_B2[1]) & BYTE_LANES_B2[1]) |\n ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &\n (!DATA_CTL_B3[1]) & BYTE_LANES_B3[1]) |\n ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &\n (!DATA_CTL_B4[1]) & BYTE_LANES_B4[1]))) ?\n 8'b00_00_01_00 :\n ((N_CTL_LANES == 2) &\n (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &\n (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |\n ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &\n (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |\n ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &\n (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |\n ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &\n (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |\n ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &\n (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?\n 8'b00_00_11_00 :\n ((N_CTL_LANES == 2) &\n (((!DATA_CTL_B0[2]) & BYTE_LANES_B0[2] &\n (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |\n ((!DATA_CTL_B1[2]) & BYTE_LANES_B1[2] &\n (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |\n ((!DATA_CTL_B2[2]) & BYTE_LANES_B2[2] &\n (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |\n ((!DATA_CTL_B3[2]) & BYTE_LANES_B3[2] &\n (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |\n ((!DATA_CTL_B4[2]) & BYTE_LANES_B4[2] &\n (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?\n 8'b00_00_11_10 :\n ((N_CTL_LANES == 2) &\n (((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] &\n (!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) |\n ((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] &\n (!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) |\n ((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] &\n (!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) |\n ((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] &\n (!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) |\n ((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] &\n (!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]))) ?\n 8'b00_00_10_01 :\n ((N_CTL_LANES == 2) &\n (((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] &\n (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |\n ((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] &\n (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |\n ((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] &\n (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |\n ((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] &\n (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |\n ((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] &\n (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?\n 8'b00_00_11_01 :\n ((N_CTL_LANES == 2) &\n (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &\n (!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) |\n ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &\n (!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) |\n ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &\n (!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) |\n ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &\n (!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) |\n ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &\n (!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]))) ?\n 8'b00_00_10_00 : 8'b11_10_01_00;\n\n localparam PI_DIV2_INCDEC = (DRAM_TYPE == \"DDR2\") ? \"FALSE\" : (((FPGA_VOLT_TYPE == \"L\") && (nCK_PER_CLK == 4)) ? \"TRUE\" : \"FALSE\");\n\n wire [HIGHEST_LANE*80-1:0] phy_din;\n wire [HIGHEST_LANE*80-1:0] phy_dout;\n wire [(HIGHEST_LANE*12)-1:0] ddr_cmd_ctl_data;\n wire [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out;\n wire [(CK_WIDTH * LP_DDR_CK_WIDTH)-1:0] ddr_clk;\n wire phy_mc_go;\n wire phy_ctl_full;\n wire phy_cmd_full;\n wire phy_data_full;\n wire phy_pre_data_a_full;\n wire if_empty /* synthesis syn_maxfan = 3 */;\n wire phy_write_calib;\n wire phy_read_calib;\n wire [HIGHEST_BANK-1:0] rst_stg1_cal;\n wire [5:0] calib_sel;\n wire calib_in_common /* synthesis syn_maxfan = 10 */;\n wire [HIGHEST_BANK-1:0] calib_zero_inputs;\n wire [HIGHEST_BANK-1:0] calib_zero_ctrl;\n wire pi_phase_locked;\n wire pi_phase_locked_all;\n wire pi_found_dqs;\n wire pi_dqs_found_all;\n wire pi_dqs_out_of_range;\n wire pi_enstg2_f;\n wire pi_stg2_fincdec;\n wire pi_stg2_load;\n wire [5:0] pi_stg2_reg_l;\n wire idelay_ce;\n wire idelay_inc;\n wire idelay_ld;\n wire [2:0] po_sel_stg2stg3;\n wire [2:0] po_stg2_cincdec;\n wire [2:0] po_enstg2_c;\n wire [2:0] po_stg2_fincdec;\n wire [2:0] po_enstg2_f;\n wire [8:0] po_counter_read_val;\n wire [5:0] pi_counter_read_val;\n wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_wrdata;\n reg [nCK_PER_CLK-1:0] parity;\n wire [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address;\n wire [nCK_PER_CLK*BANK_WIDTH-1:0] phy_bank;\n wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n;\n wire [nCK_PER_CLK-1:0] phy_ras_n;\n wire [nCK_PER_CLK-1:0] phy_cas_n;\n wire [nCK_PER_CLK-1:0] phy_we_n;\n wire phy_reset_n;\n wire [3:0] calib_aux_out;\n wire [nCK_PER_CLK-1:0] calib_cke;\n wire [1:0] calib_odt;\n wire calib_ctl_wren;\n wire calib_cmd_wren;\n wire calib_wrdata_en;\n wire [2:0] calib_cmd;\n wire [1:0] calib_seq;\n wire [5:0] calib_data_offset_0;\n wire [5:0] calib_data_offset_1;\n wire [5:0] calib_data_offset_2;\n wire [1:0] calib_rank_cnt;\n wire [1:0] calib_cas_slot;\n wire [nCK_PER_CLK*ROW_WIDTH-1:0] mux_address;\n wire [3:0] mux_aux_out;\n wire [3:0] aux_out_map;\n wire [nCK_PER_CLK*BANK_WIDTH-1:0] mux_bank;\n wire [2:0] mux_cmd;\n wire mux_cmd_wren;\n wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mux_cs_n;\n wire mux_ctl_wren;\n wire [1:0] mux_cas_slot;\n wire [5:0] mux_data_offset;\n wire [5:0] mux_data_offset_1;\n wire [5:0] mux_data_offset_2;\n wire [nCK_PER_CLK-1:0] mux_ras_n;\n wire [nCK_PER_CLK-1:0] mux_cas_n;\n wire [1:0] mux_rank_cnt;\n wire mux_reset_n;\n wire [nCK_PER_CLK-1:0] mux_we_n;\n wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] mux_wrdata;\n wire [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mux_wrdata_mask;\n wire mux_wrdata_en;\n wire [nCK_PER_CLK-1:0] mux_cke ;\n wire [1:0] mux_odt ;\n wire phy_if_empty_def;\n wire phy_if_reset;\n wire phy_init_data_sel;\n wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data_map;\n wire phy_rddata_valid_w;\n reg rddata_valid_reg;\n reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data_reg;\n wire [4:0] idelaye2_init_val;\n wire [5:0] oclkdelay_init_val;\n wire po_counter_load_en;\n wire [DQS_CNT_WIDTH:0] byte_sel_cnt;\n wire [DRAM_WIDTH-1:0] fine_delay_incdec_pb;\n wire fine_delay_sel;\n wire pd_out;\n\n //***************************************************************************\n\n assign dbg_rddata_valid = rddata_valid_reg;\n assign dbg_rddata = rd_data_reg;\n\n assign dbg_rd_data_offset = calib_rd_data_offset_0;\n assign dbg_pi_phaselocked_done = pi_phase_locked_all;\n\n assign dbg_po_counter_read_val = po_counter_read_val;\n assign dbg_pi_counter_read_val = pi_counter_read_val;\n\n //***************************************************************************\n\n //***************************************************************************\n // Clock domain crossing from DIV4 to DIV2 for Phaser_In stage2 incdec\n //***************************************************************************\n //localparam PI_DIV2_INCDEC = \"TRUE\";\n\n wire pi_fine_enable;\n wire pi_fine_inc;\n wire pi_counter_load_en;\n wire [5:0] pi_counter_load_val;\n wire [HIGHEST_BANK-1:0] pi_rst_dqs_find;\n\n generate\n if (PI_DIV2_INCDEC == \"TRUE\") begin: div2_incdec\n // 3-stage synchronizer registers\n (* ASYNC_REG = \"TRUE\" *) reg pi_enstg2_f_div2r1;\n (* ASYNC_REG = \"TRUE\" *) reg pi_enstg2_f_div2r2;\n (* ASYNC_REG = \"TRUE\" *) reg pi_enstg2_f_div2r3;\n (* ASYNC_REG = \"TRUE\" *) reg pi_stg2_fincdec_div2r1;\n (* ASYNC_REG = \"TRUE\" *) reg pi_stg2_fincdec_div2r2;\n (* ASYNC_REG = \"TRUE\" *) reg pi_stg2_fincdec_div2r3;\n (* ASYNC_REG = \"TRUE\" *) reg pi_stg2_load_div2r1;\n (* ASYNC_REG = \"TRUE\" *) reg pi_stg2_load_div2r2;\n (* ASYNC_REG = \"TRUE\" *) reg pi_stg2_load_div2r3;\n (* ASYNC_REG = \"TRUE\" *) reg [HIGHEST_BANK-1:0] rst_stg1_cal_div2r1;\n (* ASYNC_REG = \"TRUE\" *) reg [HIGHEST_BANK-1:0] rst_stg1_cal_div2r2;\n (* ASYNC_REG = \"TRUE\" *) reg [5:0] pi_stg2_reg_l_div2r1;\n (* ASYNC_REG = \"TRUE\" *) reg [5:0] pi_stg2_reg_l_div2r2;\n (* ASYNC_REG = \"TRUE\" *) reg [5:0] pi_stg2_reg_l_div2r3;\n\n reg pi_stg2_fine_enable, pi_stg2_fine_enable_r1;\n reg pi_stg2_fine_inc, pi_stg2_fine_inc_r1;\n reg pi_stg2_load_en, pi_stg2_load_en_r1;\n reg [5:0] pi_stg2_load_val;\n (* ASYNC_REG = \"TRUE\" *) reg [HIGHEST_BANK-1:0] pi_dqs_find_rst;\n\n // 3-stage synchronizer\n always @(posedge clk_div2) begin\n //Phaser_In fine enable\n pi_enstg2_f_div2r1 <= #TCQ pi_enstg2_f;\n pi_enstg2_f_div2r2 <= #TCQ pi_enstg2_f_div2r1;\n pi_enstg2_f_div2r3 <= #TCQ pi_enstg2_f_div2r2;\n //Phaser_In fine incdec\n pi_stg2_fincdec_div2r1 <= #TCQ pi_stg2_fincdec;\n pi_stg2_fincdec_div2r2 <= #TCQ pi_stg2_fincdec_div2r1;\n pi_stg2_fincdec_div2r3 <= #TCQ pi_stg2_fincdec_div2r2;\n //Phaser_In stage2 load\n pi_stg2_load_div2r1 <= #TCQ pi_stg2_load;\n pi_stg2_load_div2r2 <= #TCQ pi_stg2_load_div2r1;\n pi_stg2_load_div2r3 <= #TCQ pi_stg2_load_div2r2;\n //Phaser_In stage2 load value\n pi_stg2_reg_l_div2r1 <= #TCQ pi_stg2_reg_l;\n pi_stg2_reg_l_div2r2 <= #TCQ pi_stg2_reg_l_div2r1;\n pi_stg2_reg_l_div2r3 <= #TCQ pi_stg2_reg_l_div2r2;\n //Phaser_In reset DQSFOUND\n rst_stg1_cal_div2r1 <= #TCQ rst_stg1_cal;\n rst_stg1_cal_div2r2 <= #TCQ rst_stg1_cal_div2r1;\n pi_dqs_find_rst <= #TCQ rst_stg1_cal_div2r2;\n end\n\n always @(posedge clk_div2) begin\n pi_stg2_fine_enable_r1 <= #TCQ pi_stg2_fine_enable;\n pi_stg2_fine_inc_r1 <= #TCQ pi_stg2_fine_inc;\n pi_stg2_load_en_r1 <= #TCQ pi_stg2_load_en;\n end\n\n always @(posedge clk_div2) begin\n if (rst_div2 || pi_stg2_fine_enable || pi_stg2_fine_enable_r1)\n pi_stg2_fine_enable <= #TCQ 1'b0;\n else if (pi_enstg2_f_div2r3)\n pi_stg2_fine_enable <= #TCQ 1'b1;\n end\n\n always @(posedge clk_div2) begin\n if (rst_div2 || pi_stg2_fine_inc || pi_stg2_fine_inc_r1)\n pi_stg2_fine_inc <= #TCQ 1'b0;\n else if (pi_stg2_fincdec_div2r3)\n pi_stg2_fine_inc <= #TCQ 1'b1;\n end\n\n always @(posedge clk_div2) begin\n if (rst_div2 || pi_stg2_load_en || pi_stg2_load_en_r1)\n pi_stg2_load_en <= #TCQ 1'b0;\n else if (pi_stg2_load_div2r3)\n pi_stg2_load_en <= #TCQ 1'b1;\n end\n\n always @(posedge clk_div2) begin\n if (rst_div2 || pi_stg2_load_en || pi_stg2_load_en_r1)\n pi_stg2_load_val <= #TCQ 6'd0;\n else if (pi_stg2_load_div2r3)\n pi_stg2_load_val <= #TCQ pi_stg2_reg_l_div2r3;\n end\n\n\n assign pi_fine_enable = pi_stg2_fine_enable;\n assign pi_fine_inc = pi_stg2_fine_inc;\n assign pi_counter_load_en = pi_stg2_load_en;\n assign pi_counter_load_val = pi_stg2_load_val;\n assign pi_rst_dqs_find = pi_dqs_find_rst;\n\n end else begin: div4_incdec\n assign pi_fine_enable = pi_enstg2_f;\n assign pi_fine_inc = pi_stg2_fincdec;\n assign pi_counter_load_en = pi_stg2_load;\n assign pi_counter_load_val = pi_stg2_reg_l;\n assign pi_rst_dqs_find = rst_stg1_cal;\n\n end\n endgenerate\n\n genvar i;\n generate\n for (i = 0; i < CK_WIDTH; i = i+1) begin: clock_gen\n assign ddr_ck[i] = ddr_clk[LP_DDR_CK_WIDTH * i];\n assign ddr_ck_n[i] = ddr_clk[(LP_DDR_CK_WIDTH * i) + 1];\n end\n endgenerate\n\n //***************************************************************************\n // During memory initialization and calibration the calibration logic drives\n // the memory signals. After calibration is complete the memory controller\n // drives the memory signals.\n // Do not expect timing issues in 4:1 mode at 800 MHz/1600 Mbps\n //***************************************************************************\n\n wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n_temp ;\n genvar v ;\n\n generate\n if((REG_CTRL == \"ON\") && (DRAM_TYPE == \"DDR3\") && (RANKS == 1) && (nCS_PER_RANK ==2)) begin : cs_rdimm\n for(v = 0 ; v < CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK ; v = v+1 ) begin\n if((v%(CS_WIDTH*nCS_PER_RANK)) == 0) begin\n assign mc_cs_n_temp[v] = mc_cs_n[v] ;\n end else begin\n assign mc_cs_n_temp[v] = 'b1 ;\n end\n end\n end else begin\n assign mc_cs_n_temp = mc_cs_n ;\n end\n endgenerate\n\n assign mux_wrdata = (phy_init_data_sel | init_wrcal_complete) ? mc_wrdata : phy_wrdata;\n assign mux_wrdata_mask = (phy_init_data_sel | init_wrcal_complete) ? mc_wrdata_mask : 'b0;\n assign mux_address = (phy_init_data_sel | init_wrcal_complete) ? mc_address : phy_address;\n assign mux_bank = (phy_init_data_sel | init_wrcal_complete) ? mc_bank : phy_bank;\n assign mux_cs_n = (phy_init_data_sel | init_wrcal_complete) ? mc_cs_n_temp : phy_cs_n;\n assign mux_ras_n = (phy_init_data_sel | init_wrcal_complete) ? mc_ras_n : phy_ras_n;\n assign mux_cas_n = (phy_init_data_sel | init_wrcal_complete) ? mc_cas_n : phy_cas_n;\n assign mux_we_n = (phy_init_data_sel | init_wrcal_complete) ? mc_we_n : phy_we_n;\n assign mux_reset_n = (phy_init_data_sel | init_wrcal_complete) ? mc_reset_n : phy_reset_n;\n assign mux_aux_out = (phy_init_data_sel | init_wrcal_complete) ? mc_aux_out0 : calib_aux_out;\n assign mux_odt = (phy_init_data_sel | init_wrcal_complete) ? mc_odt : calib_odt ;\n assign mux_cke = (phy_init_data_sel | init_wrcal_complete) ? mc_cke : calib_cke ;\n assign mux_cmd_wren = (phy_init_data_sel | init_wrcal_complete) ? mc_cmd_wren :\n calib_cmd_wren;\n assign mux_ctl_wren = (phy_init_data_sel | init_wrcal_complete) ? mc_ctl_wren :\n calib_ctl_wren;\n assign mux_wrdata_en = (phy_init_data_sel | init_wrcal_complete) ? mc_wrdata_en :\n calib_wrdata_en;\n assign mux_cmd = (phy_init_data_sel | init_wrcal_complete) ? mc_cmd : calib_cmd;\n assign mux_cas_slot = (phy_init_data_sel | init_wrcal_complete) ? mc_cas_slot : calib_cas_slot;\n assign mux_data_offset = (phy_init_data_sel | init_wrcal_complete) ? mc_data_offset :\n calib_data_offset_0;\n assign mux_data_offset_1 = (phy_init_data_sel | init_wrcal_complete) ? mc_data_offset_1 :\n calib_data_offset_1;\n assign mux_data_offset_2 = (phy_init_data_sel | init_wrcal_complete) ? mc_data_offset_2 :\n calib_data_offset_2;\n // Reserved field. Hard coded to 2'b00 irrespective of the number of ranks. CR 643601\n assign mux_rank_cnt = 2'b00;\n\n\n // Assigning cke & odt for DDR2 & DDR3\n // No changes for DDR3 & DDR2 dual rank\n // DDR2 single rank systems might potentially need 3 odt signals.\n // Aux_out[2] will have the odt toggled by phy and controller\n // wiring aux_out[2] to 0 & 3. Depending upon the odt parameter\n // all of the three odt bits or some of them might be used.\n // mapping done in mc_phy_wrapper module\n generate\n if(CKE_ODT_AUX == \"TRUE\") begin\n assign aux_out_map = ((DRAM_TYPE == \"DDR2\") && (RANKS == 1)) ?\n {mux_aux_out[1],mux_aux_out[1],mux_aux_out[1],mux_aux_out[0]} :\n mux_aux_out;\n end else begin\n assign aux_out_map = 4'b0000 ;\n end\n endgenerate\n\n assign init_calib_complete = phy_init_data_sel;\n\n assign phy_mc_ctl_full = phy_ctl_full;\n assign phy_mc_cmd_full = phy_cmd_full;\n assign phy_mc_data_full = phy_pre_data_a_full;\n\n //***************************************************************************\n // Generate parity for DDR3 RDIMM.\n //***************************************************************************\n\n generate\n if ((DRAM_TYPE == \"DDR3\") && (REG_CTRL == \"ON\")) begin: gen_ddr3_parity\n if (nCK_PER_CLK == 4) begin\n always @(posedge clk) begin\n parity[0] <= #TCQ (^{mux_address[(ROW_WIDTH*4)-1:ROW_WIDTH*3],\n mux_bank[(BANK_WIDTH*4)-1:BANK_WIDTH*3],\n mux_cas_n[3], mux_ras_n[3], mux_we_n[3]});\n end\n always @(*) begin\n parity[1] = (^{mux_address[ROW_WIDTH-1:0], mux_bank[BANK_WIDTH-1:0],\n mux_cas_n[0],mux_ras_n[0], mux_we_n[0]});\n parity[2] = (^{mux_address[(ROW_WIDTH*2)-1:ROW_WIDTH],\n mux_bank[(BANK_WIDTH*2)-1:BANK_WIDTH],\n mux_cas_n[1], mux_ras_n[1], mux_we_n[1]});\n parity[3] = (^{mux_address[(ROW_WIDTH*3)-1:ROW_WIDTH*2],\n mux_bank[(BANK_WIDTH*3)-1:BANK_WIDTH*2],\n mux_cas_n[2],mux_ras_n[2], mux_we_n[2]});\n end\n end else begin\n always @(posedge clk) begin\n parity[0] <= #TCQ(^{mux_address[(ROW_WIDTH*2)-1:ROW_WIDTH],\n mux_bank[(BANK_WIDTH*2)-1:BANK_WIDTH],\n mux_cas_n[1], mux_ras_n[1], mux_we_n[1]});\n end\n always @(*) begin\n parity[1] = (^{mux_address[ROW_WIDTH-1:0],\n mux_bank[BANK_WIDTH-1:0],\n mux_cas_n[0], mux_ras_n[0], mux_we_n[0]});\n end\n end\n end else begin: gen_ddr3_noparity\n if (nCK_PER_CLK == 4) begin\n always @(posedge clk) begin\n parity[0] <= #TCQ 1'b0;\n parity[1] <= #TCQ 1'b0;\n parity[2] <= #TCQ 1'b0;\n parity[3] <= #TCQ 1'b0;\n end\n end else begin\n always @(posedge clk) begin\n parity[0] <= #TCQ 1'b0;\n parity[1] <= #TCQ 1'b0;\n end\n end\n end\n endgenerate\n\n //***************************************************************************\n // Code for optional register stage in read path to MC for timing\n //***************************************************************************\n generate\n if(RD_PATH_REG == 1)begin:RD_REG_TIMING\n always @(posedge clk)begin\n rddata_valid_reg <= #TCQ phy_rddata_valid_w;\n rd_data_reg <= #TCQ rd_data_map;\n end // always @ (posedge clk)\n end else begin : RD_REG_NO_TIMING // block: RD_REG_TIMING\n always @(phy_rddata_valid_w or rd_data_map)begin\n rddata_valid_reg = phy_rddata_valid_w;\n rd_data_reg = rd_data_map;\n end\n end\n endgenerate\n\n assign phy_rddata_valid = rddata_valid_reg;\n assign phy_rd_data = rd_data_reg;\n\n //***************************************************************************\n // Hard PHY and accompanying bit mapping logic\n //***************************************************************************\n\n mig_7series_v4_0_ddr_mc_phy_wrapper #\n (\n .TCQ (TCQ),\n .tCK (tCK),\n .BANK_TYPE (BANK_TYPE),\n .DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE),\n .DATA_IO_IDLE_PWRDWN(DATA_IO_IDLE_PWRDWN),\n .IODELAY_GRP (IODELAY_GRP),\n .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),\n .nCK_PER_CLK (nCK_PER_CLK),\n .nCS_PER_RANK (nCS_PER_RANK),\n .BANK_WIDTH (BANK_WIDTH),\n .CKE_WIDTH (CKE_WIDTH),\n .CS_WIDTH (CS_WIDTH),\n .CK_WIDTH (CK_WIDTH),\n .LP_DDR_CK_WIDTH (LP_DDR_CK_WIDTH),\n .DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE),\n .CWL (CWL),\n .DM_WIDTH (DM_WIDTH),\n .DQ_WIDTH (DQ_WIDTH),\n .DQS_CNT_WIDTH (DQS_CNT_WIDTH),\n .DQS_WIDTH (DQS_WIDTH),\n .DRAM_TYPE (DRAM_TYPE),\n .RANKS (RANKS),\n .ODT_WIDTH (ODT_WIDTH),\n .REG_CTRL (REG_CTRL),\n .ROW_WIDTH (ROW_WIDTH),\n .USE_CS_PORT (USE_CS_PORT),\n .USE_DM_PORT (USE_DM_PORT),\n .USE_ODT_PORT (USE_ODT_PORT),\n .IBUF_LPWR_MODE (IBUF_LPWR_MODE),\n .PHYCTL_CMD_FIFO (PHYCTL_CMD_FIFO),\n .DATA_CTL_B0 (DATA_CTL_B0),\n .DATA_CTL_B1 (DATA_CTL_B1),\n .DATA_CTL_B2 (DATA_CTL_B2),\n .DATA_CTL_B3 (DATA_CTL_B3),\n .DATA_CTL_B4 (DATA_CTL_B4),\n .BYTE_LANES_B0 (BYTE_LANES_B0),\n .BYTE_LANES_B1 (BYTE_LANES_B1),\n .BYTE_LANES_B2 (BYTE_LANES_B2),\n .BYTE_LANES_B3 (BYTE_LANES_B3),\n .BYTE_LANES_B4 (BYTE_LANES_B4),\n .PHY_0_BITLANES (PHY_0_BITLANES),\n .PHY_1_BITLANES (PHY_1_BITLANES),\n .PHY_2_BITLANES (PHY_2_BITLANES),\n .HIGHEST_BANK (HIGHEST_BANK),\n .HIGHEST_LANE (HIGHEST_LANE),\n .CK_BYTE_MAP (CK_BYTE_MAP),\n .ADDR_MAP (ADDR_MAP),\n .BANK_MAP (BANK_MAP),\n .CAS_MAP (CAS_MAP),\n .CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),\n .CKE_MAP (CKE_MAP),\n .ODT_MAP (ODT_MAP),\n .CKE_ODT_AUX (CKE_ODT_AUX),\n .CS_MAP (CS_MAP),\n .PARITY_MAP (PARITY_MAP),\n .RAS_MAP (RAS_MAP),\n .WE_MAP (WE_MAP),\n .DQS_BYTE_MAP (DQS_BYTE_MAP),\n .DATA0_MAP (DATA0_MAP),\n .DATA1_MAP (DATA1_MAP),\n .DATA2_MAP (DATA2_MAP),\n .DATA3_MAP (DATA3_MAP),\n .DATA4_MAP (DATA4_MAP),\n .DATA5_MAP (DATA5_MAP),\n .DATA6_MAP (DATA6_MAP),\n .DATA7_MAP (DATA7_MAP),\n .DATA8_MAP (DATA8_MAP),\n .DATA9_MAP (DATA9_MAP),\n .DATA10_MAP (DATA10_MAP),\n .DATA11_MAP (DATA11_MAP),\n .DATA12_MAP (DATA12_MAP),\n .DATA13_MAP (DATA13_MAP),\n .DATA14_MAP (DATA14_MAP),\n .DATA15_MAP (DATA15_MAP),\n .DATA16_MAP (DATA16_MAP),\n .DATA17_MAP (DATA17_MAP),\n .MASK0_MAP (MASK0_MAP),\n .MASK1_MAP (MASK1_MAP),\n .SIM_CAL_OPTION (SIM_CAL_OPTION),\n .MASTER_PHY_CTL (MASTER_PHY_CTL),\n .DRAM_WIDTH (DRAM_WIDTH),\n .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP),\n .PI_DIV2_INCDEC (PI_DIV2_INCDEC)\n )\n u_ddr_mc_phy_wrapper\n (\n .rst (rst),\n .iddr_rst (iddr_rst),\n .clk (clk),\n .clk_div2 (clk_div2),\n // For memory frequencies between 400~1066 MHz freq_refclk = mem_refclk\n // For memory frequencies below 400 MHz mem_refclk = mem_refclk and\n // freq_refclk = 2x or 4x mem_refclk such that it remains in the\n // 400~1066 MHz range\n .freq_refclk (freq_refclk),\n .mem_refclk (mem_refclk),\n .mmcm_ps_clk (mmcm_ps_clk),\n .pll_lock (pll_lock),\n .sync_pulse (sync_pulse),\n .idelayctrl_refclk (clk_ref),\n .phy_cmd_wr_en (mux_cmd_wren),\n .phy_data_wr_en (mux_wrdata_en),\n // phy_ctl_wd = {ACTPRE[31:30],EventDelay[29:25],seq[24:23],\n // DataOffset[22:17],HiIndex[16:15],LowIndex[14:12],\n // AuxOut[11:8],ControlOffset[7:3],PHYCmd[2:0]}\n // The fields ACTPRE, and BankCount are only used\n // when the hard PHY counters are used by the MC.\n .phy_ctl_wd ({5'd0, mux_cas_slot, calib_seq, mux_data_offset,\n mux_rank_cnt, 3'd0, aux_out_map,\n 5'd0, mux_cmd}),\n .phy_ctl_wr (mux_ctl_wren),\n .phy_if_empty_def (phy_if_empty_def),\n .phy_if_reset (phy_if_reset),\n .data_offset_1 (mux_data_offset_1),\n .data_offset_2 (mux_data_offset_2),\n .aux_in_1 (aux_out_map),\n .aux_in_2 (aux_out_map),\n .idelaye2_init_val (idelaye2_init_val),\n .oclkdelay_init_val (oclkdelay_init_val),\n .if_empty (if_empty),\n .phy_ctl_full (phy_ctl_full),\n .phy_cmd_full (phy_cmd_full),\n .phy_data_full (phy_data_full),\n .phy_pre_data_a_full (phy_pre_data_a_full),\n .ddr_clk (ddr_clk),\n .phy_mc_go (phy_mc_go),\n .phy_write_calib (phy_write_calib),\n .phy_read_calib (phy_read_calib),\n .po_fine_enable (po_enstg2_f),\n .po_coarse_enable (po_enstg2_c),\n .po_fine_inc (po_stg2_fincdec),\n .po_coarse_inc (po_stg2_cincdec),\n .po_counter_load_en (po_counter_load_en),\n .po_counter_read_en (1'b1),\n .po_sel_fine_oclk_delay (po_sel_stg2stg3),\n .po_counter_load_val (),\n .po_counter_read_val (po_counter_read_val),\n .pi_rst_dqs_find (pi_rst_dqs_find),\n .pi_fine_enable (pi_fine_enable),\n .pi_fine_inc (pi_fine_inc),\n .pi_counter_load_en (pi_counter_load_en),\n .pi_counter_load_val (pi_counter_load_val),\n .pi_counter_read_val (pi_counter_read_val),\n .idelay_ce (idelay_ce),\n .idelay_inc (idelay_inc),\n .idelay_ld (idelay_ld),\n .pi_phase_locked (pi_phase_locked),\n .pi_phase_locked_all (pi_phase_locked_all),\n .pi_dqs_found (pi_found_dqs),\n .pi_dqs_found_all (pi_dqs_found_all),\n // Currently not being used. May be used in future if periodic reads\n // become a requirement. This output could also be used to signal a\n // catastrophic failure in read capture and the need for re-cal\n .pi_dqs_out_of_range (pi_dqs_out_of_range),\n .phy_init_data_sel (phy_init_data_sel),\n .calib_sel (calib_sel),\n .calib_in_common (calib_in_common),\n .calib_zero_inputs (calib_zero_inputs),\n .calib_zero_ctrl (calib_zero_ctrl),\n .mux_address (mux_address),\n .mux_bank (mux_bank),\n .mux_cs_n (mux_cs_n),\n .mux_ras_n (mux_ras_n),\n .mux_cas_n (mux_cas_n),\n .mux_we_n (mux_we_n),\n .mux_reset_n (mux_reset_n),\n .parity_in (parity),\n .mux_wrdata (mux_wrdata),\n .mux_wrdata_mask (mux_wrdata_mask),\n .mux_odt (mux_odt),\n .mux_cke (mux_cke),\n .idle (idle),\n .rd_data (rd_data_map),\n .ddr_addr (ddr_addr),\n .ddr_ba (ddr_ba),\n .ddr_cas_n (ddr_cas_n),\n .ddr_cke (ddr_cke),\n .ddr_cs_n (ddr_cs_n),\n .ddr_dm (ddr_dm),\n .ddr_odt (ddr_odt),\n .ddr_parity (ddr_parity),\n .ddr_ras_n (ddr_ras_n),\n .ddr_we_n (ddr_we_n),\n .ddr_dq (ddr_dq),\n .ddr_dqs (ddr_dqs),\n .ddr_dqs_n (ddr_dqs_n),\n .ddr_reset_n (ddr_reset_n),\n .dbg_pi_counter_read_en (1'b1),\n .ref_dll_lock (ref_dll_lock),\n .rst_phaser_ref (rst_phaser_ref),\n .dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes),\n .dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes),\n .byte_sel_cnt (byte_sel_cnt),\n .pd_out (pd_out),\n .fine_delay_incdec_pb (fine_delay_incdec_pb),\n .fine_delay_sel (fine_delay_sel)\n );\n\n //***************************************************************************\n // Soft memory initialization and calibration logic\n //***************************************************************************\n\n mig_7series_v4_0_ddr_calib_top #\n (\n .TCQ (TCQ),\n .DDR3_VDD_OP_VOLT (DDR3_VDD_OP_VOLT),\n .nCK_PER_CLK (nCK_PER_CLK),\n .PRE_REV3ES (PRE_REV3ES),\n .tCK (tCK),\n .CLK_PERIOD (CLK_PERIOD),\n .N_CTL_LANES (N_CTL_LANES),\n .CTL_BYTE_LANE (CTL_BYTE_LANE),\n .CTL_BANK (CTL_BANK),\n .DRAM_TYPE (DRAM_TYPE),\n .PRBS_WIDTH (8),\n .DQS_BYTE_MAP (DQS_BYTE_MAP),\n .HIGHEST_BANK (HIGHEST_BANK),\n .BANK_TYPE (BANK_TYPE),\n .HIGHEST_LANE (HIGHEST_LANE),\n .BYTE_LANES_B0 (BYTE_LANES_B0),\n .BYTE_LANES_B1 (BYTE_LANES_B1),\n .BYTE_LANES_B2 (BYTE_LANES_B2),\n .BYTE_LANES_B3 (BYTE_LANES_B3),\n .BYTE_LANES_B4 (BYTE_LANES_B4),\n .DATA_CTL_B0 (DATA_CTL_B0),\n .DATA_CTL_B1 (DATA_CTL_B1),\n .DATA_CTL_B2 (DATA_CTL_B2),\n .DATA_CTL_B3 (DATA_CTL_B3),\n .DATA_CTL_B4 (DATA_CTL_B4),\n .SLOT_1_CONFIG (SLOT_1_CONFIG),\n .BANK_WIDTH (BANK_WIDTH),\n .CA_MIRROR (CA_MIRROR),\n .COL_WIDTH (COL_WIDTH),\n .CKE_ODT_AUX (CKE_ODT_AUX),\n .nCS_PER_RANK (nCS_PER_RANK),\n .DQ_WIDTH (DQ_WIDTH),\n .DQS_CNT_WIDTH (DQS_CNT_WIDTH),\n .DQS_WIDTH (DQS_WIDTH),\n .DRAM_WIDTH (DRAM_WIDTH),\n .ROW_WIDTH (ROW_WIDTH),\n .RANKS (RANKS),\n .CS_WIDTH (CS_WIDTH),\n .CKE_WIDTH (CKE_WIDTH),\n .DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE),\n .PER_BIT_DESKEW (\"OFF\"),\n .CALIB_ROW_ADD (CALIB_ROW_ADD),\n .CALIB_COL_ADD (CALIB_COL_ADD),\n .CALIB_BA_ADD (CALIB_BA_ADD),\n .AL (AL),\n .BURST_MODE (BURST_MODE),\n .BURST_TYPE (BURST_TYPE),\n .nCL (CL),\n .nCWL (CWL),\n .tRFC (tRFC),\n .tREFI (tREFI),\n .OUTPUT_DRV (OUTPUT_DRV),\n .REG_CTRL (REG_CTRL),\n .ADDR_CMD_MODE (ADDR_CMD_MODE),\n .RTT_NOM (RTT_NOM),\n .RTT_WR (RTT_WR),\n .WRLVL (WRLVL_W),\n .USE_ODT_PORT (USE_ODT_PORT),\n .SIM_INIT_OPTION (SIM_INIT_OPTION),\n .SIM_CAL_OPTION (SIM_CAL_OPTION),\n .DEBUG_PORT (DEBUG_PORT),\n .IDELAY_ADJ (IDELAY_ADJ),\n .FINE_PER_BIT (FINE_PER_BIT),\n .CENTER_COMP_MODE (CENTER_COMP_MODE),\n .PI_VAL_ADJ (PI_VAL_ADJ),\n .TAPSPERKCLK (TAPSPERKCLK),\n .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP),\n .SKIP_CALIB (SKIP_CALIB),\n .PI_DIV2_INCDEC (PI_DIV2_INCDEC)\n )\n u_ddr_calib_top\n (\n .clk (clk),\n .rst (rst),\n\n .tg_err (error),\n .rst_tg_mc (rst_tg_mc),\n\n .slot_0_present (slot_0_present),\n .slot_1_present (slot_1_present),\n // PHY Control Block and IN_FIFO status\n .phy_ctl_ready (phy_mc_go),\n .phy_ctl_full (1'b0),\n .phy_cmd_full (1'b0),\n .phy_data_full (1'b0),\n .phy_if_empty (if_empty),\n .idelaye2_init_val (idelaye2_init_val),\n .oclkdelay_init_val (oclkdelay_init_val),\n // From calib logic To data IN_FIFO\n // DQ IDELAY tap value from Calib logic\n // port to be added to mc_phy by Gary\n .dlyval_dq (),\n // hard PHY calibration modes\n .write_calib (phy_write_calib),\n .read_calib (phy_read_calib),\n // DQS count and ck/addr/cmd to be mapped to calib_sel\n // based on parameter that defines placement of ctl lanes\n // and DQS byte groups in each bank. When phy_write_calib\n // is de-asserted calib_sel should select CK/addr/cmd/ctl.\n .calib_sel (calib_sel),\n .calib_in_common (calib_in_common),\n .calib_zero_inputs (calib_zero_inputs),\n .calib_zero_ctrl (calib_zero_ctrl),\n .phy_if_empty_def (phy_if_empty_def),\n .phy_if_reset (phy_if_reset),\n // Signals from calib logic to be MUXED with MC\n // signals before sending to hard PHY\n .calib_ctl_wren (calib_ctl_wren),\n .calib_cmd_wren (calib_cmd_wren),\n .calib_seq (calib_seq),\n .calib_aux_out (calib_aux_out),\n .calib_odt (calib_odt),\n .calib_cke (calib_cke),\n .calib_cmd (calib_cmd),\n .calib_wrdata_en (calib_wrdata_en),\n .calib_rank_cnt (calib_rank_cnt),\n .calib_cas_slot (calib_cas_slot),\n .calib_data_offset_0 (calib_data_offset_0),\n .calib_data_offset_1 (calib_data_offset_1),\n .calib_data_offset_2 (calib_data_offset_2),\n .phy_reset_n (phy_reset_n),\n .phy_address (phy_address),\n .phy_bank (phy_bank),\n .phy_cs_n (phy_cs_n),\n .phy_ras_n (phy_ras_n),\n .phy_cas_n (phy_cas_n),\n .phy_we_n (phy_we_n),\n .phy_wrdata (phy_wrdata),\n // DQS Phaser_IN calibration/status signals\n .pi_phaselocked (pi_phase_locked),\n .pi_phase_locked_all (pi_phase_locked_all),\n .pi_found_dqs (pi_found_dqs),\n .pi_dqs_found_all (pi_dqs_found_all),\n .pi_dqs_found_lanes (dbg_pi_dqs_found_lanes_phy4lanes),\n .pi_rst_stg1_cal (rst_stg1_cal),\n .pi_en_stg2_f (pi_enstg2_f),\n .pi_stg2_f_incdec (pi_stg2_fincdec),\n .pi_stg2_load (pi_stg2_load),\n .pi_stg2_reg_l (pi_stg2_reg_l),\n .pi_counter_read_val (pi_counter_read_val),\n .device_temp (device_temp),\n .tempmon_sample_en (tempmon_sample_en),\n // IDELAY tap enable and inc signals\n .idelay_ce (idelay_ce),\n .idelay_inc (idelay_inc),\n .idelay_ld (idelay_ld),\n // DQS Phaser_OUT calibration/status signals\n .po_sel_stg2stg3 (po_sel_stg2stg3),\n .po_stg2_c_incdec (po_stg2_cincdec),\n .po_en_stg2_c (po_enstg2_c),\n .po_stg2_f_incdec (po_stg2_fincdec),\n .po_en_stg2_f (po_enstg2_f),\n .po_counter_load_en (po_counter_load_en),\n .po_counter_read_val (po_counter_read_val),\n // From data IN_FIFO To Calib logic and MC/UI\n .phy_rddata (rd_data_map),\n // From calib logic To MC\n .phy_rddata_valid (phy_rddata_valid_w),\n .calib_rd_data_offset_0 (calib_rd_data_offset_0),\n .calib_rd_data_offset_1 (calib_rd_data_offset_1),\n .calib_rd_data_offset_2 (calib_rd_data_offset_2),\n .calib_writes (),\n // Mem Init and Calibration status To MC\n .init_calib_complete (phy_init_data_sel),\n .init_wrcal_complete (init_wrcal_complete),\n // Debug Error signals\n .pi_phase_locked_err (dbg_pi_phaselock_err),\n .pi_dqsfound_err (dbg_pi_dqsfound_err),\n .wrcal_err (dbg_wrcal_err),\n //used for oclk stg3 centering\n .pd_out (pd_out),\n .psen (psen),\n .psincdec (psincdec),\n .psdone (psdone),\n .poc_sample_pd (poc_sample_pd),\n .calib_tap_req (calib_tap_req),\n .calib_tap_addr (calib_tap_addr),\n .calib_tap_load (calib_tap_load),\n .calib_tap_val (calib_tap_val),\n .calib_tap_load_done (calib_tap_load_done),\n // Debug Signals\n .dbg_pi_phaselock_start (dbg_pi_phaselock_start),\n .dbg_pi_dqsfound_start (dbg_pi_dqsfound_start),\n .dbg_pi_dqsfound_done (dbg_pi_dqsfound_done),\n .dbg_wrlvl_start (dbg_wrlvl_start),\n .dbg_wrlvl_done (dbg_wrlvl_done),\n .dbg_wrlvl_err (dbg_wrlvl_err),\n .dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),\n .dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),\n .dbg_phy_wrlvl (dbg_phy_wrlvl),\n .dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),\n .dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),\n .dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),\n .dbg_wrcal_start (dbg_wrcal_start),\n .dbg_wrcal_done (dbg_wrcal_done),\n .dbg_phy_wrcal (dbg_phy_wrcal),\n .dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),\n .dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt),\n .dbg_rdlvl_start (dbg_rdlvl_start),\n .dbg_rdlvl_done (dbg_rdlvl_done),\n .dbg_rdlvl_err (dbg_rdlvl_err),\n .dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),\n .dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),\n .dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),\n .dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),\n .dbg_sel_pi_incdec (dbg_sel_pi_incdec),\n .dbg_sel_po_incdec (dbg_sel_po_incdec),\n .dbg_byte_sel (dbg_byte_sel),\n .dbg_pi_f_inc (dbg_pi_f_inc),\n .dbg_pi_f_dec (dbg_pi_f_dec),\n .dbg_po_f_inc (dbg_po_f_inc),\n .dbg_po_f_stg23_sel (dbg_po_f_stg23_sel),\n .dbg_po_f_dec (dbg_po_f_dec),\n .dbg_idel_up_all (dbg_idel_up_all),\n .dbg_idel_down_all (dbg_idel_down_all),\n .dbg_idel_up_cpt (dbg_idel_up_cpt),\n .dbg_idel_down_cpt (dbg_idel_down_cpt),\n .dbg_sel_idel_cpt (dbg_sel_idel_cpt),\n .dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),\n .dbg_phy_rdlvl (dbg_phy_rdlvl),\n .dbg_calib_top (dbg_calib_top),\n .dbg_phy_init (dbg_phy_init),\n .dbg_prbs_rdlvl (dbg_prbs_rdlvl),\n .dbg_dqs_found_cal (dbg_dqs_found_cal),\n .dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal),\n .dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data),\n .dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start),\n .dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done),\n .dbg_poc (dbg_poc[1023:0]),\n .prbs_final_dqs_tap_cnt_r (prbs_final_dqs_tap_cnt_r),\n .dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps),\n .dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps),\n .byte_sel_cnt (byte_sel_cnt),\n .fine_delay_incdec_pb (fine_delay_incdec_pb),\n .fine_delay_sel (fine_delay_sel)\n );\n\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_wrcal.v", "content": "//*****************************************************************************\n// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor: Xilinx\n// \\ \\ \\/ Version:\n// \\ \\ Application: MIG\n// / / Filename: ddr_phy_wrcal.v\n// /___/ /\\ Date Last Modified: $Date: 2011/06/02 08:35:09 $\n// \\ \\ / \\ Date Created:\n// \\___\\/\\___\\\n//\n//Device: 7 Series\n//Design Name: DDR3 SDRAM\n//Purpose:\n// Write calibration logic to align DQS to correct CK edge\n//Reference:\n//Revision History:\n//*****************************************************************************\n\n/******************************************************************************\n**$Id: ddr_phy_wrcal.v,v 1.1 2011/06/02 08:35:09 mishra Exp $\n**$Date: 2011/06/02 08:35:09 $\n**$Author: \n**$Revision:\n**$Source: \n******************************************************************************/\n\n`timescale 1ps/1ps\n\nmodule mig_7series_v4_0_ddr_phy_wrcal #\n (\n parameter TCQ = 100, // clk->out delay (sim only)\n parameter nCK_PER_CLK = 2, // # of memory clocks per CLK\n parameter CLK_PERIOD = 2500,\n parameter DQ_WIDTH = 64, // # of DQ (data)\n parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))\n parameter DQS_WIDTH = 8, // # of DQS (strobe)\n parameter DRAM_WIDTH = 8, // # of DQ per DQS\n parameter PRE_REV3ES = \"OFF\", // Delay O/Ps using Phaser_Out fine dly\n parameter SIM_CAL_OPTION = \"NONE\" // Skip various calibration steps\n )\n (\n input clk,\n input rst,\n // Calibration status, control signals\n input wrcal_start,\n input wrcal_rd_wait,\n input wrcal_sanity_chk,\n input dqsfound_retry_done,\n input phy_rddata_en,\n output dqsfound_retry,\n output wrcal_read_req,\n output reg wrcal_act_req,\n output reg wrcal_done,\n output reg wrcal_pat_err,\n output reg wrcal_prech_req,\n output reg temp_wrcal_done,\n output reg wrcal_sanity_chk_done,\n input prech_done,\n // Captured data in resync clock domain\n input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,\n // Write level values of Phaser_Out coarse and fine\n // delay taps required to load Phaser_Out register\n input [3*DQS_WIDTH-1:0] wl_po_coarse_cnt,\n input [6*DQS_WIDTH-1:0] wl_po_fine_cnt,\n input wrlvl_byte_done,\n output reg wrlvl_byte_redo,\n output reg early1_data,\n output reg early2_data,\n // DQ IDELAY\n output reg idelay_ld,\n output reg wrcal_pat_resume, // to phy_init for write\n output reg [DQS_CNT_WIDTH:0] po_stg2_wrcal_cnt,\n output phy_if_reset,\n\n // Debug Port\n output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,\n output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt, \n output [99:0] dbg_phy_wrcal\n );\n\n // Length of calibration sequence (in # of words)\n //localparam CAL_PAT_LEN = 8;\n\n // Read data shift register length\n localparam RD_SHIFT_LEN = 1; //(nCK_PER_CLK == 4) ? 1 : 2;\n\n // # of reads for reliable read capture\n localparam NUM_READS = 2;\n \n // # of cycles to wait after changing RDEN count value\n localparam RDEN_WAIT_CNT = 12;\n \n localparam COARSE_CNT = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 3 : 6;\n localparam FINE_CNT = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 22 : 44;\n \n \n localparam CAL2_IDLE = 4'h0;\n localparam CAL2_READ_WAIT = 4'h1;\n localparam CAL2_NEXT_DQS = 4'h2;\n localparam CAL2_WRLVL_WAIT = 4'h3;\n localparam CAL2_IFIFO_RESET = 4'h4;\n localparam CAL2_DQ_IDEL_DEC = 4'h5;\n localparam CAL2_DONE = 4'h6;\n localparam CAL2_SANITY_WAIT = 4'h7;\n localparam CAL2_ERR = 4'h8;\n\n integer i,j,k,l,m,p,q,d;\n \n reg [2:0] po_coarse_tap_cnt [0:DQS_WIDTH-1];\n reg [3*DQS_WIDTH-1:0] po_coarse_tap_cnt_w;\n reg [5:0] po_fine_tap_cnt [0:DQS_WIDTH-1];\n reg [6*DQS_WIDTH-1:0] po_fine_tap_cnt_w;\n reg [DQS_CNT_WIDTH:0] wrcal_dqs_cnt_r/* synthesis syn_maxfan = 10 */;\n reg [4:0] not_empty_wait_cnt;\n reg [3:0] tap_inc_wait_cnt;\n reg cal2_done_r;\n reg cal2_done_r1;\n reg cal2_prech_req_r;\n reg [3:0] cal2_state_r;\n reg [3:0] cal2_state_r1;\n reg [2:0] wl_po_coarse_cnt_w [0:DQS_WIDTH-1];\n reg [5:0] wl_po_fine_cnt_w [0:DQS_WIDTH-1];\n reg cal2_if_reset;\n reg wrcal_pat_resume_r;\n reg wrcal_pat_resume_r1;\n reg wrcal_pat_resume_r2;\n reg wrcal_pat_resume_r3;\n reg [DRAM_WIDTH-1:0] mux_rd_fall0_r;\n reg [DRAM_WIDTH-1:0] mux_rd_fall1_r;\n reg [DRAM_WIDTH-1:0] mux_rd_rise0_r;\n reg [DRAM_WIDTH-1:0] mux_rd_rise1_r;\n reg [DRAM_WIDTH-1:0] mux_rd_fall2_r;\n reg [DRAM_WIDTH-1:0] mux_rd_fall3_r;\n reg [DRAM_WIDTH-1:0] mux_rd_rise2_r;\n reg [DRAM_WIDTH-1:0] mux_rd_rise3_r;\n reg pat_data_match_r;\n reg pat1_data_match_r;\n reg pat1_data_match_r1;\n reg pat2_data_match_r;\n reg pat_data_match_valid_r;\n wire [RD_SHIFT_LEN-1:0] pat_fall0 [3:0];\n wire [RD_SHIFT_LEN-1:0] pat_fall1 [3:0];\n wire [RD_SHIFT_LEN-1:0] pat_fall2 [3:0];\n wire [RD_SHIFT_LEN-1:0] pat_fall3 [3:0];\n wire [RD_SHIFT_LEN-1:0] pat1_fall0 [3:0];\n wire [RD_SHIFT_LEN-1:0] pat1_fall1 [3:0];\n wire [RD_SHIFT_LEN-1:0] pat2_fall0 [3:0];\n wire [RD_SHIFT_LEN-1:0] pat2_fall1 [3:0];\n wire [RD_SHIFT_LEN-1:0] early_fall0 [3:0];\n wire [RD_SHIFT_LEN-1:0] early_fall1 [3:0];\n wire [RD_SHIFT_LEN-1:0] early_fall2 [3:0];\n wire [RD_SHIFT_LEN-1:0] early_fall3 [3:0];\n wire [RD_SHIFT_LEN-1:0] early1_fall0 [3:0];\n wire [RD_SHIFT_LEN-1:0] early1_fall1 [3:0];\n wire [RD_SHIFT_LEN-1:0] early2_fall0 [3:0];\n wire [RD_SHIFT_LEN-1:0] early2_fall1 [3:0];\n reg [DRAM_WIDTH-1:0] pat_match_fall0_r;\n reg pat_match_fall0_and_r;\n reg [DRAM_WIDTH-1:0] pat_match_fall1_r;\n reg pat_match_fall1_and_r;\n reg [DRAM_WIDTH-1:0] pat_match_fall2_r;\n reg pat_match_fall2_and_r;\n reg [DRAM_WIDTH-1:0] pat_match_fall3_r;\n reg pat_match_fall3_and_r;\n reg [DRAM_WIDTH-1:0] pat_match_rise0_r;\n reg pat_match_rise0_and_r;\n reg [DRAM_WIDTH-1:0] pat_match_rise1_r;\n reg pat_match_rise1_and_r;\n reg [DRAM_WIDTH-1:0] pat_match_rise2_r;\n reg pat_match_rise2_and_r;\n reg [DRAM_WIDTH-1:0] pat_match_rise3_r;\n reg pat_match_rise3_and_r;\n reg [DRAM_WIDTH-1:0] pat1_match_rise0_r;\n reg [DRAM_WIDTH-1:0] pat1_match_rise1_r;\n reg [DRAM_WIDTH-1:0] pat1_match_fall0_r;\n reg [DRAM_WIDTH-1:0] pat1_match_fall1_r;\n reg [DRAM_WIDTH-1:0] pat2_match_rise0_r;\n reg [DRAM_WIDTH-1:0] pat2_match_rise1_r;\n reg [DRAM_WIDTH-1:0] pat2_match_fall0_r;\n reg [DRAM_WIDTH-1:0] pat2_match_fall1_r;\n reg pat1_match_rise0_and_r;\n reg pat1_match_rise1_and_r;\n reg pat1_match_fall0_and_r;\n reg pat1_match_fall1_and_r;\n reg pat2_match_rise0_and_r;\n reg pat2_match_rise1_and_r;\n reg pat2_match_fall0_and_r;\n reg pat2_match_fall1_and_r;\n reg early1_data_match_r;\n reg early1_data_match_r1;\n reg [DRAM_WIDTH-1:0] early1_match_fall0_r;\n reg early1_match_fall0_and_r;\n reg [DRAM_WIDTH-1:0] early1_match_fall1_r;\n reg early1_match_fall1_and_r;\n reg [DRAM_WIDTH-1:0] early1_match_fall2_r;\n reg early1_match_fall2_and_r;\n reg [DRAM_WIDTH-1:0] early1_match_fall3_r;\n reg early1_match_fall3_and_r;\n reg [DRAM_WIDTH-1:0] early1_match_rise0_r;\n reg early1_match_rise0_and_r;\n reg [DRAM_WIDTH-1:0] early1_match_rise1_r;\n reg early1_match_rise1_and_r;\n reg [DRAM_WIDTH-1:0] early1_match_rise2_r;\n reg early1_match_rise2_and_r;\n reg [DRAM_WIDTH-1:0] early1_match_rise3_r;\n reg early1_match_rise3_and_r;\n reg early2_data_match_r;\n reg [DRAM_WIDTH-1:0] early2_match_fall0_r;\n reg early2_match_fall0_and_r;\n reg [DRAM_WIDTH-1:0] early2_match_fall1_r;\n reg early2_match_fall1_and_r;\n reg [DRAM_WIDTH-1:0] early2_match_fall2_r;\n reg early2_match_fall2_and_r;\n reg [DRAM_WIDTH-1:0] early2_match_fall3_r;\n reg early2_match_fall3_and_r;\n reg [DRAM_WIDTH-1:0] early2_match_rise0_r;\n reg early2_match_rise0_and_r;\n reg [DRAM_WIDTH-1:0] early2_match_rise1_r;\n reg early2_match_rise1_and_r;\n reg [DRAM_WIDTH-1:0] early2_match_rise2_r;\n reg early2_match_rise2_and_r;\n reg [DRAM_WIDTH-1:0] early2_match_rise3_r;\n reg early2_match_rise3_and_r; \n wire [RD_SHIFT_LEN-1:0] pat_rise0 [3:0];\n wire [RD_SHIFT_LEN-1:0] pat_rise1 [3:0];\n wire [RD_SHIFT_LEN-1:0] pat_rise2 [3:0];\n wire [RD_SHIFT_LEN-1:0] pat_rise3 [3:0];\n wire [RD_SHIFT_LEN-1:0] pat1_rise0 [3:0];\n wire [RD_SHIFT_LEN-1:0] pat1_rise1 [3:0];\n wire [RD_SHIFT_LEN-1:0] pat2_rise0 [3:0];\n wire [RD_SHIFT_LEN-1:0] pat2_rise1 [3:0];\n wire [RD_SHIFT_LEN-1:0] early_rise0 [3:0];\n wire [RD_SHIFT_LEN-1:0] early_rise1 [3:0];\n wire [RD_SHIFT_LEN-1:0] early_rise2 [3:0];\n wire [RD_SHIFT_LEN-1:0] early_rise3 [3:0];\n wire [RD_SHIFT_LEN-1:0] early1_rise0 [3:0];\n wire [RD_SHIFT_LEN-1:0] early1_rise1 [3:0];\n wire [RD_SHIFT_LEN-1:0] early2_rise0 [3:0];\n wire [RD_SHIFT_LEN-1:0] early2_rise1 [3:0];\n wire [DQ_WIDTH-1:0] rd_data_rise0; \n wire [DQ_WIDTH-1:0] rd_data_fall0;\n wire [DQ_WIDTH-1:0] rd_data_rise1;\n wire [DQ_WIDTH-1:0] rd_data_fall1;\n wire [DQ_WIDTH-1:0] rd_data_rise2;\n wire [DQ_WIDTH-1:0] rd_data_fall2;\n wire [DQ_WIDTH-1:0] rd_data_rise3;\n wire [DQ_WIDTH-1:0] rd_data_fall3;\n reg [DQS_CNT_WIDTH:0] rd_mux_sel_r;\n reg rd_active_posedge_r;\n reg rd_active_r;\n reg rd_active_r1;\n reg rd_active_r2;\n reg rd_active_r3;\n reg rd_active_r4;\n reg rd_active_r5;\n reg [RD_SHIFT_LEN-1:0] sr_fall0_r [DRAM_WIDTH-1:0];\n reg [RD_SHIFT_LEN-1:0] sr_fall1_r [DRAM_WIDTH-1:0];\n reg [RD_SHIFT_LEN-1:0] sr_rise0_r [DRAM_WIDTH-1:0];\n reg [RD_SHIFT_LEN-1:0] sr_rise1_r [DRAM_WIDTH-1:0];\n reg [RD_SHIFT_LEN-1:0] sr_fall2_r [DRAM_WIDTH-1:0];\n reg [RD_SHIFT_LEN-1:0] sr_fall3_r [DRAM_WIDTH-1:0];\n reg [RD_SHIFT_LEN-1:0] sr_rise2_r [DRAM_WIDTH-1:0];\n reg [RD_SHIFT_LEN-1:0] sr_rise3_r [DRAM_WIDTH-1:0];\n reg wrlvl_byte_done_r;\n reg idelay_ld_done;\n reg pat1_detect;\n reg early1_detect;\n reg wrcal_sanity_chk_r;\n reg wrcal_sanity_chk_err;\n\n\n //***************************************************************************\n // Debug\n //***************************************************************************\n\n always @(*) begin\n for (d = 0; d < DQS_WIDTH; d = d + 1) begin\n po_fine_tap_cnt_w[(6*d)+:6] = po_fine_tap_cnt[d];\n po_coarse_tap_cnt_w[(3*d)+:3] = po_coarse_tap_cnt[d];\n end\n end\n\n assign dbg_final_po_fine_tap_cnt = po_fine_tap_cnt_w;\n assign dbg_final_po_coarse_tap_cnt = po_coarse_tap_cnt_w;\n \n assign dbg_phy_wrcal[0] = pat_data_match_r;\n assign dbg_phy_wrcal[4:1] = cal2_state_r1[3:0];\n assign dbg_phy_wrcal[5] = wrcal_sanity_chk_err;\n assign dbg_phy_wrcal[6] = wrcal_start;\n assign dbg_phy_wrcal[7] = wrcal_done;\n assign dbg_phy_wrcal[8] = pat_data_match_valid_r;\n assign dbg_phy_wrcal[13+:DQS_CNT_WIDTH]= wrcal_dqs_cnt_r;\n assign dbg_phy_wrcal[17+:5] = not_empty_wait_cnt; \n assign dbg_phy_wrcal[22] = early1_data; \n assign dbg_phy_wrcal[23] = early2_data; \n assign dbg_phy_wrcal[24+:8] = mux_rd_rise0_r; \n assign dbg_phy_wrcal[32+:8] = mux_rd_fall0_r; \n assign dbg_phy_wrcal[40+:8] = mux_rd_rise1_r; \n assign dbg_phy_wrcal[48+:8] = mux_rd_fall1_r; \n assign dbg_phy_wrcal[56+:8] = mux_rd_rise2_r; \n assign dbg_phy_wrcal[64+:8] = mux_rd_fall2_r; \n assign dbg_phy_wrcal[72+:8] = mux_rd_rise3_r; \n assign dbg_phy_wrcal[80+:8] = mux_rd_fall3_r; \n assign dbg_phy_wrcal[88] = early1_data_match_r; \n assign dbg_phy_wrcal[89] = early2_data_match_r; \n assign dbg_phy_wrcal[90] = wrcal_sanity_chk_r & pat_data_match_valid_r; \n assign dbg_phy_wrcal[91] = wrcal_sanity_chk_r; \n assign dbg_phy_wrcal[92] = wrcal_sanity_chk_done; \n \n assign dqsfound_retry = 1'b0;\n assign wrcal_read_req = 1'b0;\n assign phy_if_reset = cal2_if_reset;\n \n //**************************************************************************\n // DQS count to hard PHY during write calibration using Phaser_OUT Stage2\n // coarse delay \n //**************************************************************************\n \n always @(posedge clk) begin\n po_stg2_wrcal_cnt <= #TCQ wrcal_dqs_cnt_r;\n wrlvl_byte_done_r <= #TCQ wrlvl_byte_done;\n\t wrcal_sanity_chk_r <= #TCQ wrcal_sanity_chk;\n end\n\n //***************************************************************************\n // Data mux to route appropriate byte to calibration logic - i.e. calibration\n // is done sequentially, one byte (or DQS group) at a time\n //***************************************************************************\n\n generate\n if (nCK_PER_CLK == 4) begin: gen_rd_data_div4\n assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];\n assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];\n assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];\n assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];\n assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH];\n assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH];\n assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH];\n assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH];\n end else if (nCK_PER_CLK == 2) begin: gen_rd_data_div2\n assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];\n assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];\n assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];\n assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];\n end\n endgenerate\n\n //**************************************************************************\n // Final Phaser OUT coarse and fine delay taps after write calibration\n // Sum of taps used during write leveling taps and write calibration\n //**************************************************************************\n\n always @(*) begin\n for (m = 0; m < DQS_WIDTH; m = m + 1) begin\n wl_po_coarse_cnt_w[m] = wl_po_coarse_cnt[3*m+:3];\n wl_po_fine_cnt_w[m] = wl_po_fine_cnt[6*m+:6];\n end\n end\n\n always @(posedge clk) begin\n if (rst) begin\n for (p = 0; p < DQS_WIDTH; p = p + 1) begin\n po_coarse_tap_cnt[p] <= #TCQ {3{1'b0}};\n po_fine_tap_cnt[p] <= #TCQ {6{1'b0}};\n end\n end else if (cal2_done_r && ~cal2_done_r1) begin\n for (q = 0; q < DQS_WIDTH; q = q + 1) begin\n po_coarse_tap_cnt[q] <= #TCQ wl_po_coarse_cnt_w[i];\n po_fine_tap_cnt[q] <= #TCQ wl_po_fine_cnt_w[i]; \n end\n end\n end\n\n always @(posedge clk) begin\n rd_mux_sel_r <= #TCQ wrcal_dqs_cnt_r;\n end\n\n // Register outputs for improved timing.\n // NOTE: Will need to change when per-bit DQ deskew is supported.\n // Currenly all bits in DQS group are checked in aggregate\n generate\n genvar mux_i;\n if (nCK_PER_CLK == 4) begin: gen_mux_rd_div4\n for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd\n always @(posedge clk) begin\n mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i];\n mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i];\n mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i];\n mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i];\n mux_rd_rise2_r[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r + mux_i];\n mux_rd_fall2_r[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r + mux_i];\n mux_rd_rise3_r[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r + mux_i];\n mux_rd_fall3_r[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r + mux_i];\n end\n end\n end else if (nCK_PER_CLK == 2) begin: gen_mux_rd_div2 \n for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd\n always @(posedge clk) begin\n mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i];\n mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i];\n mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i];\n mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i];\n end\n end\n end\n endgenerate\n\n //***************************************************************************\n // generate request to PHY_INIT logic to issue precharged. Required when\n // calibration can take a long time (during which there are only constant\n // reads present on this bus). In this case need to issue perioidic\n // precharges to avoid tRAS violation. This signal must meet the following\n // requirements: (1) only transition from 0->1 when prech is first needed,\n // (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted\n //***************************************************************************\n\n always @(posedge clk)\n if (rst)\n wrcal_prech_req <= #TCQ 1'b0;\n else\n // Combine requests from all stages here\n wrcal_prech_req <= #TCQ cal2_prech_req_r;\n\n //***************************************************************************\n // Shift register to store last RDDATA_SHIFT_LEN cycles of data from ISERDES\n // NOTE: Written using discrete flops, but SRL can be used if the matching\n // logic does the comparison sequentially, rather than parallel\n //***************************************************************************\n\n generate\n genvar rd_i;\n if (nCK_PER_CLK == 4) begin: gen_sr_div4\n for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr\n always @(posedge clk) begin\n sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i];\n sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i];\n sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i];\n sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i];\n sr_rise2_r[rd_i] <= #TCQ mux_rd_rise2_r[rd_i];\n sr_fall2_r[rd_i] <= #TCQ mux_rd_fall2_r[rd_i];\n sr_rise3_r[rd_i] <= #TCQ mux_rd_rise3_r[rd_i];\n sr_fall3_r[rd_i] <= #TCQ mux_rd_fall3_r[rd_i];\n end\n end \n end else if (nCK_PER_CLK == 2) begin: gen_sr_div2\n for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr\n always @(posedge clk) begin\n sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i]; \n sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i];\n sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i];\n sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i];\n end\n end\n end\n endgenerate\n\n //***************************************************************************\n // Write calibration:\n // During write leveling DQS is aligned to the nearest CK edge that may not \n // be the correct CK edge. Write calibration is required to align the DQS to \n // the correct CK edge that clocks the write command. \n // The Phaser_Out coarse delay line is adjusted if required to add a memory\n // clock cycle of delay in order to read back the expected pattern.\n //***************************************************************************\n\n always @(posedge clk) begin\n rd_active_r <= #TCQ phy_rddata_en;\n rd_active_r1 <= #TCQ rd_active_r;\n rd_active_r2 <= #TCQ rd_active_r1;\n rd_active_r3 <= #TCQ rd_active_r2;\n rd_active_r4 <= #TCQ rd_active_r3;\n rd_active_r5 <= #TCQ rd_active_r4; \n end\n\n //*****************************************************************\n // Expected data pattern when properly received by read capture\n // logic:\n // Based on pattern of ({rise,fall}) =\n // 0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6\n // Each nibble will look like:\n // bit3: 1, 0, 1, 0, 0, 1, 1, 0\n // bit2: 1, 0, 0, 1, 1, 0, 0, 1\n // bit1: 1, 0, 1, 0, 0, 1, 0, 1\n // bit0: 1, 0, 0, 1, 1, 0, 1, 0\n // Change the hard-coded pattern below accordingly as RD_SHIFT_LEN\n // and the actual training pattern contents change\n //*****************************************************************\n \n generate\n if (nCK_PER_CLK == 4) begin: gen_pat_div4\n // FF00AA5555AA9966\n assign pat_rise0[3] = 1'b1;\n assign pat_fall0[3] = 1'b0;\n assign pat_rise1[3] = 1'b1;\n assign pat_fall1[3] = 1'b0;\n assign pat_rise2[3] = 1'b0;\n assign pat_fall2[3] = 1'b1;\n assign pat_rise3[3] = 1'b1;\n assign pat_fall3[3] = 1'b0;\n \n assign pat_rise0[2] = 1'b1;\n assign pat_fall0[2] = 1'b0;\n assign pat_rise1[2] = 1'b0;\n assign pat_fall1[2] = 1'b1;\n assign pat_rise2[2] = 1'b1;\n assign pat_fall2[2] = 1'b0;\n assign pat_rise3[2] = 1'b0;\n assign pat_fall3[2] = 1'b1;\n \n assign pat_rise0[1] = 1'b1;\n assign pat_fall0[1] = 1'b0;\n assign pat_rise1[1] = 1'b1;\n assign pat_fall1[1] = 1'b0;\n assign pat_rise2[1] = 1'b0;\n assign pat_fall2[1] = 1'b1;\n assign pat_rise3[1] = 1'b0;\n assign pat_fall3[1] = 1'b1;\n \n assign pat_rise0[0] = 1'b1;\n assign pat_fall0[0] = 1'b0;\n assign pat_rise1[0] = 1'b0;\n assign pat_fall1[0] = 1'b1;\n assign pat_rise2[0] = 1'b1;\n assign pat_fall2[0] = 1'b0;\n assign pat_rise3[0] = 1'b1;\n assign pat_fall3[0] = 1'b0;\n \n // Pattern to distinguish between early write and incorrect read\n // BB11EE4444EEDD88\n assign early_rise0[3] = 1'b1;\n assign early_fall0[3] = 1'b0;\n assign early_rise1[3] = 1'b1;\n assign early_fall1[3] = 1'b0;\n assign early_rise2[3] = 1'b0;\n assign early_fall2[3] = 1'b1;\n assign early_rise3[3] = 1'b1;\n assign early_fall3[3] = 1'b1;\n \n assign early_rise0[2] = 1'b0;\n assign early_fall0[2] = 1'b0;\n assign early_rise1[2] = 1'b1;\n assign early_fall1[2] = 1'b1;\n assign early_rise2[2] = 1'b1;\n assign early_fall2[2] = 1'b1;\n assign early_rise3[2] = 1'b1;\n assign early_fall3[2] = 1'b0;\n \n assign early_rise0[1] = 1'b1;\n assign early_fall0[1] = 1'b0;\n assign early_rise1[1] = 1'b1;\n assign early_fall1[1] = 1'b0;\n assign early_rise2[1] = 1'b0;\n assign early_fall2[1] = 1'b1;\n assign early_rise3[1] = 1'b0;\n assign early_fall3[1] = 1'b0;\n \n assign early_rise0[0] = 1'b1;\n assign early_fall0[0] = 1'b1;\n assign early_rise1[0] = 1'b0;\n assign early_fall1[0] = 1'b0;\n assign early_rise2[0] = 1'b0;\n assign early_fall2[0] = 1'b0;\n assign early_rise3[0] = 1'b1;\n assign early_fall3[0] = 1'b0;\n \n end else if (nCK_PER_CLK == 2) begin: gen_pat_div2\n // First cycle pattern FF00AA55\n assign pat1_rise0[3] = 1'b1;\n assign pat1_fall0[3] = 1'b0;\n assign pat1_rise1[3] = 1'b1;\n assign pat1_fall1[3] = 1'b0;\n \n assign pat1_rise0[2] = 1'b1;\n assign pat1_fall0[2] = 1'b0;\n assign pat1_rise1[2] = 1'b0;\n assign pat1_fall1[2] = 1'b1;\n \n assign pat1_rise0[1] = 1'b1;\n assign pat1_fall0[1] = 1'b0;\n assign pat1_rise1[1] = 1'b1;\n assign pat1_fall1[1] = 1'b0;\n \n assign pat1_rise0[0] = 1'b1;\n assign pat1_fall0[0] = 1'b0;\n assign pat1_rise1[0] = 1'b0;\n assign pat1_fall1[0] = 1'b1;\n \n // Second cycle pattern 55AA9966\n assign pat2_rise0[3] = 1'b0;\n assign pat2_fall0[3] = 1'b1;\n assign pat2_rise1[3] = 1'b1;\n assign pat2_fall1[3] = 1'b0;\n \n assign pat2_rise0[2] = 1'b1;\n assign pat2_fall0[2] = 1'b0;\n assign pat2_rise1[2] = 1'b0;\n assign pat2_fall1[2] = 1'b1;\n \n assign pat2_rise0[1] = 1'b0;\n assign pat2_fall0[1] = 1'b1;\n assign pat2_rise1[1] = 1'b0;\n assign pat2_fall1[1] = 1'b1;\n \n assign pat2_rise0[0] = 1'b1;\n assign pat2_fall0[0] = 1'b0;\n assign pat2_rise1[0] = 1'b1;\n assign pat2_fall1[0] = 1'b0;\n \n //Pattern to distinguish between early write and incorrect read\n // First cycle pattern AA5555AA\n assign early1_rise0[3] = 2'b1;\n assign early1_fall0[3] = 2'b0;\n assign early1_rise1[3] = 2'b0;\n assign early1_fall1[3] = 2'b1;\n \n assign early1_rise0[2] = 2'b0;\n assign early1_fall0[2] = 2'b1;\n assign early1_rise1[2] = 2'b1;\n assign early1_fall1[2] = 2'b0;\n \n assign early1_rise0[1] = 2'b1;\n assign early1_fall0[1] = 2'b0;\n assign early1_rise1[1] = 2'b0;\n assign early1_fall1[1] = 2'b1;\n \n assign early1_rise0[0] = 2'b0;\n assign early1_fall0[0] = 2'b1;\n assign early1_rise1[0] = 2'b1;\n assign early1_fall1[0] = 2'b0;\n \n // Second cycle pattern 9966BB11\n assign early2_rise0[3] = 2'b1;\n assign early2_fall0[3] = 2'b0;\n assign early2_rise1[3] = 2'b1;\n assign early2_fall1[3] = 2'b0;\n \n assign early2_rise0[2] = 2'b0;\n assign early2_fall0[2] = 2'b1;\n assign early2_rise1[2] = 2'b0;\n assign early2_fall1[2] = 2'b0;\n \n assign early2_rise0[1] = 2'b0;\n assign early2_fall0[1] = 2'b1;\n assign early2_rise1[1] = 2'b1;\n assign early2_fall1[1] = 2'b0;\n \n assign early2_rise0[0] = 2'b1;\n assign early2_fall0[0] = 2'b0;\n assign early2_rise1[0] = 2'b1;\n assign early2_fall1[0] = 2'b1;\n end\n endgenerate\n\n // Each bit of each byte is compared to expected pattern.\n // This was done to prevent (and \"drastically decrease\") the chance that\n // invalid data clocked in when the DQ bus is tri-state (along with a\n // combination of the correct data) will resemble the expected data\n // pattern. A better fix for this is to change the training pattern and/or\n // make the pattern longer.\n generate\n genvar pt_i;\n if (nCK_PER_CLK == 4) begin: gen_pat_match_div4\n for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match\n always @(posedge clk) begin\n if (sr_rise0_r[pt_i] == pat_rise0[pt_i%4])\n pat_match_rise0_r[pt_i] <= #TCQ 1'b1;\n else\n pat_match_rise0_r[pt_i] <= #TCQ 1'b0;\n \n if (sr_fall0_r[pt_i] == pat_fall0[pt_i%4])\n pat_match_fall0_r[pt_i] <= #TCQ 1'b1;\n else\n pat_match_fall0_r[pt_i] <= #TCQ 1'b0;\n \n if (sr_rise1_r[pt_i] == pat_rise1[pt_i%4])\n pat_match_rise1_r[pt_i] <= #TCQ 1'b1;\n else\n pat_match_rise1_r[pt_i] <= #TCQ 1'b0;\n \n if (sr_fall1_r[pt_i] == pat_fall1[pt_i%4])\n pat_match_fall1_r[pt_i] <= #TCQ 1'b1;\n else\n pat_match_fall1_r[pt_i] <= #TCQ 1'b0;\n \n if (sr_rise2_r[pt_i] == pat_rise2[pt_i%4])\n pat_match_rise2_r[pt_i] <= #TCQ 1'b1;\n else\n pat_match_rise2_r[pt_i] <= #TCQ 1'b0;\n \n if (sr_fall2_r[pt_i] == pat_fall2[pt_i%4])\n pat_match_fall2_r[pt_i] <= #TCQ 1'b1;\n else\n pat_match_fall2_r[pt_i] <= #TCQ 1'b0;\n \n if (sr_rise3_r[pt_i] == pat_rise3[pt_i%4])\n pat_match_rise3_r[pt_i] <= #TCQ 1'b1;\n else\n pat_match_rise3_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_fall3_r[pt_i] == pat_fall3[pt_i%4])\n pat_match_fall3_r[pt_i] <= #TCQ 1'b1;\n else\n pat_match_fall3_r[pt_i] <= #TCQ 1'b0;\n end\n \n always @(posedge clk) begin\n if (sr_rise0_r[pt_i] == pat_rise1[pt_i%4])\n early1_match_rise0_r[pt_i] <= #TCQ 1'b1;\n else\n early1_match_rise0_r[pt_i] <= #TCQ 1'b0;\n \n if (sr_fall0_r[pt_i] == pat_fall1[pt_i%4])\n early1_match_fall0_r[pt_i] <= #TCQ 1'b1;\n else\n early1_match_fall0_r[pt_i] <= #TCQ 1'b0;\n \n if (sr_rise1_r[pt_i] == pat_rise2[pt_i%4])\n early1_match_rise1_r[pt_i] <= #TCQ 1'b1;\n else\n early1_match_rise1_r[pt_i] <= #TCQ 1'b0;\n \n if (sr_fall1_r[pt_i] == pat_fall2[pt_i%4])\n early1_match_fall1_r[pt_i] <= #TCQ 1'b1;\n else\n early1_match_fall1_r[pt_i] <= #TCQ 1'b0;\n \n if (sr_rise2_r[pt_i] == pat_rise3[pt_i%4])\n early1_match_rise2_r[pt_i] <= #TCQ 1'b1;\n else\n early1_match_rise2_r[pt_i] <= #TCQ 1'b0;\n \n if (sr_fall2_r[pt_i] == pat_fall3[pt_i%4])\n early1_match_fall2_r[pt_i] <= #TCQ 1'b1;\n else\n early1_match_fall2_r[pt_i] <= #TCQ 1'b0;\n \n if (sr_rise3_r[pt_i] == early_rise0[pt_i%4])\n early1_match_rise3_r[pt_i] <= #TCQ 1'b1;\n else\n early1_match_rise3_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_fall3_r[pt_i] == early_fall0[pt_i%4])\n early1_match_fall3_r[pt_i] <= #TCQ 1'b1;\n else\n early1_match_fall3_r[pt_i] <= #TCQ 1'b0;\n end\n\n always @(posedge clk) begin\n if (sr_rise0_r[pt_i] == pat_rise2[pt_i%4])\n early2_match_rise0_r[pt_i] <= #TCQ 1'b1;\n else\n early2_match_rise0_r[pt_i] <= #TCQ 1'b0;\n \n if (sr_fall0_r[pt_i] == pat_fall2[pt_i%4])\n early2_match_fall0_r[pt_i] <= #TCQ 1'b1;\n else\n early2_match_fall0_r[pt_i] <= #TCQ 1'b0;\n \n if (sr_rise1_r[pt_i] == pat_rise3[pt_i%4])\n early2_match_rise1_r[pt_i] <= #TCQ 1'b1;\n else\n early2_match_rise1_r[pt_i] <= #TCQ 1'b0;\n \n if (sr_fall1_r[pt_i] == pat_fall3[pt_i%4])\n early2_match_fall1_r[pt_i] <= #TCQ 1'b1;\n else\n early2_match_fall1_r[pt_i] <= #TCQ 1'b0;\n \n if (sr_rise2_r[pt_i] == early_rise0[pt_i%4])\n early2_match_rise2_r[pt_i] <= #TCQ 1'b1;\n else\n early2_match_rise2_r[pt_i] <= #TCQ 1'b0;\n \n if (sr_fall2_r[pt_i] == early_fall0[pt_i%4])\n early2_match_fall2_r[pt_i] <= #TCQ 1'b1;\n else\n early2_match_fall2_r[pt_i] <= #TCQ 1'b0;\n \n if (sr_rise3_r[pt_i] == early_rise1[pt_i%4])\n early2_match_rise3_r[pt_i] <= #TCQ 1'b1;\n else\n early2_match_rise3_r[pt_i] <= #TCQ 1'b0;\n\n if (sr_fall3_r[pt_i] == early_fall1[pt_i%4])\n early2_match_fall3_r[pt_i] <= #TCQ 1'b1;\n else\n early2_match_fall3_r[pt_i] <= #TCQ 1'b0;\n end \n end\n \n\n always @(posedge clk) begin\n pat_match_rise0_and_r <= #TCQ &pat_match_rise0_r;\n pat_match_fall0_and_r <= #TCQ &pat_match_fall0_r;\n pat_match_rise1_and_r <= #TCQ &pat_match_rise1_r;\n pat_match_fall1_and_r <= #TCQ &pat_match_fall1_r;\n pat_match_rise2_and_r <= #TCQ &pat_match_rise2_r;\n pat_match_fall2_and_r <= #TCQ &pat_match_fall2_r;\n pat_match_rise3_and_r <= #TCQ &pat_match_rise3_r;\n pat_match_fall3_and_r <= #TCQ &pat_match_fall3_r;\n pat_data_match_r <= #TCQ (pat_match_rise0_and_r &&\n pat_match_fall0_and_r &&\n pat_match_rise1_and_r &&\n pat_match_fall1_and_r &&\n pat_match_rise2_and_r &&\n pat_match_fall2_and_r &&\n pat_match_rise3_and_r &&\n pat_match_fall3_and_r);\n pat_data_match_valid_r <= #TCQ rd_active_r3;\n end\n \n always @(posedge clk) begin\n early1_match_rise0_and_r <= #TCQ &early1_match_rise0_r;\n early1_match_fall0_and_r <= #TCQ &early1_match_fall0_r;\n early1_match_rise1_and_r <= #TCQ &early1_match_rise1_r;\n early1_match_fall1_and_r <= #TCQ &early1_match_fall1_r;\n early1_match_rise2_and_r <= #TCQ &early1_match_rise2_r;\n early1_match_fall2_and_r <= #TCQ &early1_match_fall2_r;\n early1_match_rise3_and_r <= #TCQ &early1_match_rise3_r;\n early1_match_fall3_and_r <= #TCQ &early1_match_fall3_r;\n early1_data_match_r <= #TCQ (early1_match_rise0_and_r &&\n early1_match_fall0_and_r &&\n early1_match_rise1_and_r &&\n early1_match_fall1_and_r &&\n early1_match_rise2_and_r &&\n early1_match_fall2_and_r &&\n early1_match_rise3_and_r &&\n early1_match_fall3_and_r);\n end\n \n always @(posedge clk) begin\n early2_match_rise0_and_r <= #TCQ &early2_match_rise0_r;\n early2_match_fall0_and_r <= #TCQ &early2_match_fall0_r;\n early2_match_rise1_and_r <= #TCQ &early2_match_rise1_r;\n early2_match_fall1_and_r <= #TCQ &early2_match_fall1_r;\n early2_match_rise2_and_r <= #TCQ &early2_match_rise2_r;\n early2_match_fall2_and_r <= #TCQ &early2_match_fall2_r;\n early2_match_rise3_and_r <= #TCQ &early2_match_rise3_r;\n early2_match_fall3_and_r <= #TCQ &early2_match_fall3_r;\n early2_data_match_r <= #TCQ (early2_match_rise0_and_r &&\n early2_match_fall0_and_r &&\n early2_match_rise1_and_r &&\n early2_match_fall1_and_r &&\n early2_match_rise2_and_r &&\n early2_match_fall2_and_r &&\n early2_match_rise3_and_r &&\n early2_match_fall3_and_r);\n end \n\n end else if (nCK_PER_CLK == 2) begin: gen_pat_match_div2\n \n for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match\n always @(posedge clk) begin\n if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4])\n pat1_match_rise0_r[pt_i] <= #TCQ 1'b1;\n else\n pat1_match_rise0_r[pt_i] <= #TCQ 1'b0;\n \n if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4])\n pat1_match_fall0_r[pt_i] <= #TCQ 1'b1;\n else\n pat1_match_fall0_r[pt_i] <= #TCQ 1'b0;\n \n if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4])\n pat1_match_rise1_r[pt_i] <= #TCQ 1'b1;\n else\n pat1_match_rise1_r[pt_i] <= #TCQ 1'b0;\n \n if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4])\n pat1_match_fall1_r[pt_i] <= #TCQ 1'b1;\n else\n pat1_match_fall1_r[pt_i] <= #TCQ 1'b0;\n end\n \n always @(posedge clk) begin\n if (sr_rise0_r[pt_i] == pat2_rise0[pt_i%4])\n pat2_match_rise0_r[pt_i] <= #TCQ 1'b1;\n else\n pat2_match_rise0_r[pt_i] <= #TCQ 1'b0;\n \n if (sr_fall0_r[pt_i] == pat2_fall0[pt_i%4])\n pat2_match_fall0_r[pt_i] <= #TCQ 1'b1;\n else\n pat2_match_fall0_r[pt_i] <= #TCQ 1'b0;\n \n if (sr_rise1_r[pt_i] == pat2_rise1[pt_i%4])\n pat2_match_rise1_r[pt_i] <= #TCQ 1'b1;\n else\n pat2_match_rise1_r[pt_i] <= #TCQ 1'b0;\n \n if (sr_fall1_r[pt_i] == pat2_fall1[pt_i%4])\n pat2_match_fall1_r[pt_i] <= #TCQ 1'b1;\n else\n pat2_match_fall1_r[pt_i] <= #TCQ 1'b0;\n end\n \n always @(posedge clk) begin\n if (sr_rise0_r[pt_i] == early1_rise0[pt_i%4])\n early1_match_rise0_r[pt_i] <= #TCQ 1'b1;\n else\n early1_match_rise0_r[pt_i] <= #TCQ 1'b0;\n \n if (sr_fall0_r[pt_i] == early1_fall0[pt_i%4])\n early1_match_fall0_r[pt_i] <= #TCQ 1'b1;\n else\n early1_match_fall0_r[pt_i] <= #TCQ 1'b0;\n \n if (sr_rise1_r[pt_i] == early1_rise1[pt_i%4])\n early1_match_rise1_r[pt_i] <= #TCQ 1'b1;\n else\n early1_match_rise1_r[pt_i] <= #TCQ 1'b0;\n \n if (sr_fall1_r[pt_i] == early1_fall1[pt_i%4])\n early1_match_fall1_r[pt_i] <= #TCQ 1'b1;\n else\n early1_match_fall1_r[pt_i] <= #TCQ 1'b0;\n end\n \n // early2 in this case does not mean 2 cycles early but \n // the second cycle of read data in 2:1 mode\n always @(posedge clk) begin\n if (sr_rise0_r[pt_i] == early2_rise0[pt_i%4])\n early2_match_rise0_r[pt_i] <= #TCQ 1'b1;\n else\n early2_match_rise0_r[pt_i] <= #TCQ 1'b0;\n \n if (sr_fall0_r[pt_i] == early2_fall0[pt_i%4])\n early2_match_fall0_r[pt_i] <= #TCQ 1'b1;\n else\n early2_match_fall0_r[pt_i] <= #TCQ 1'b0;\n \n if (sr_rise1_r[pt_i] == early2_rise1[pt_i%4])\n early2_match_rise1_r[pt_i] <= #TCQ 1'b1;\n else\n early2_match_rise1_r[pt_i] <= #TCQ 1'b0;\n \n if (sr_fall1_r[pt_i] == early2_fall1[pt_i%4])\n early2_match_fall1_r[pt_i] <= #TCQ 1'b1;\n else\n early2_match_fall1_r[pt_i] <= #TCQ 1'b0;\n end\n end \n \n always @(posedge clk) begin\n pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r;\n pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r;\n pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r;\n pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r;\n pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r &&\n pat1_match_fall0_and_r &&\n pat1_match_rise1_and_r &&\n pat1_match_fall1_and_r);\n pat1_data_match_r1 <= #TCQ pat1_data_match_r;\n \n pat2_match_rise0_and_r <= #TCQ &pat2_match_rise0_r && rd_active_r3;\n pat2_match_fall0_and_r <= #TCQ &pat2_match_fall0_r && rd_active_r3;\n pat2_match_rise1_and_r <= #TCQ &pat2_match_rise1_r && rd_active_r3;\n pat2_match_fall1_and_r <= #TCQ &pat2_match_fall1_r && rd_active_r3;\n pat2_data_match_r <= #TCQ (pat2_match_rise0_and_r &&\n pat2_match_fall0_and_r &&\n pat2_match_rise1_and_r &&\n pat2_match_fall1_and_r);\n\n // For 2:1 mode, read valid is asserted for 2 clock cycles -\n // here we generate a \"match valid\" pulse that is only 1 clock\n // cycle wide that is simulatenous when the match calculation\n // is complete\n pat_data_match_valid_r <= #TCQ rd_active_r4 & ~rd_active_r5;\n end\n \n always @(posedge clk) begin\n early1_match_rise0_and_r <= #TCQ &early1_match_rise0_r;\n early1_match_fall0_and_r <= #TCQ &early1_match_fall0_r;\n early1_match_rise1_and_r <= #TCQ &early1_match_rise1_r;\n early1_match_fall1_and_r <= #TCQ &early1_match_fall1_r;\n early1_data_match_r <= #TCQ (early1_match_rise0_and_r &&\n early1_match_fall0_and_r &&\n early1_match_rise1_and_r &&\n early1_match_fall1_and_r);\n early1_data_match_r1 <= #TCQ early1_data_match_r;\n \n early2_match_rise0_and_r <= #TCQ &early2_match_rise0_r && rd_active_r3;\n early2_match_fall0_and_r <= #TCQ &early2_match_fall0_r && rd_active_r3;\n early2_match_rise1_and_r <= #TCQ &early2_match_rise1_r && rd_active_r3;\n early2_match_fall1_and_r <= #TCQ &early2_match_fall1_r && rd_active_r3;\n early2_data_match_r <= #TCQ (early2_match_rise0_and_r &&\n early2_match_fall0_and_r &&\n early2_match_rise1_and_r &&\n early2_match_fall1_and_r);\n end\n \n end\n endgenerate\n\n // Need to delay it by 3 cycles in order to wait for Phaser_Out\n // coarse delay to take effect before issuing a write command\n always @(posedge clk) begin\n wrcal_pat_resume_r1 <= #TCQ wrcal_pat_resume_r;\n wrcal_pat_resume_r2 <= #TCQ wrcal_pat_resume_r1;\n wrcal_pat_resume <= #TCQ wrcal_pat_resume_r2;\n end\n \n always @(posedge clk) begin\n if (rst)\n tap_inc_wait_cnt <= #TCQ 'd0;\n else if ((cal2_state_r == CAL2_DQ_IDEL_DEC) ||\n (cal2_state_r == CAL2_IFIFO_RESET) ||\n\t\t\t (cal2_state_r == CAL2_SANITY_WAIT))\n tap_inc_wait_cnt <= #TCQ tap_inc_wait_cnt + 1;\n else\n tap_inc_wait_cnt <= #TCQ 'd0;\n end\n \n always @(posedge clk) begin\n if (rst)\n not_empty_wait_cnt <= #TCQ 'd0;\n else if ((cal2_state_r == CAL2_READ_WAIT) && wrcal_rd_wait)\n not_empty_wait_cnt <= #TCQ not_empty_wait_cnt + 1;\n else\n not_empty_wait_cnt <= #TCQ 'd0;\n end\n\n always @(posedge clk)\n cal2_state_r1 <= #TCQ cal2_state_r;\n \n //*****************************************************************\n // Write Calibration state machine\n //*****************************************************************\n\n // when calibrating, check to see if the expected pattern is received.\n // Otherwise delay DQS to align to correct CK edge.\n // NOTES:\n // 1. An error condition can occur due to two reasons:\n // a. If the matching logic does not receive the expected data\n // pattern. However, the error may be \"recoverable\" because \n // the write calibration is still in progress. If an error is\n // found the write calibration logic delays DQS by an additional\n // clock cycle and restarts the pattern detection process.\n // By design, if the write path timing is incorrect, the correct\n // data pattern will never be detected.\n // b. Valid data not found even after incrementing Phaser_Out\n // coarse delay line.\n\n\n always @(posedge clk) begin\n if (rst) begin\n wrcal_dqs_cnt_r <= #TCQ 'b0;\n cal2_done_r <= #TCQ 1'b0;\n cal2_prech_req_r <= #TCQ 1'b0;\n cal2_state_r <= #TCQ CAL2_IDLE;\n wrcal_pat_err <= #TCQ 1'b0;\n wrcal_pat_resume_r <= #TCQ 1'b0;\n wrcal_act_req <= #TCQ 1'b0;\n cal2_if_reset <= #TCQ 1'b0;\n temp_wrcal_done <= #TCQ 1'b0;\n wrlvl_byte_redo <= #TCQ 1'b0;\n early1_data <= #TCQ 1'b0;\n early2_data <= #TCQ 1'b0;\n idelay_ld <= #TCQ 1'b0;\n idelay_ld_done <= #TCQ 1'b0;\n pat1_detect <= #TCQ 1'b0;\n early1_detect <= #TCQ 1'b0;\n\t wrcal_sanity_chk_done <= #TCQ 1'b0;\n wrcal_sanity_chk_err <= #TCQ 1'b0;\n end else begin\n cal2_prech_req_r <= #TCQ 1'b0;\n case (cal2_state_r)\n CAL2_IDLE: begin\n wrcal_pat_err <= #TCQ 1'b0;\n if (wrcal_start) begin\n cal2_if_reset <= #TCQ 1'b0;\n if (SIM_CAL_OPTION == \"SKIP_CAL\")\n // If skip write calibration, then proceed to end.\n cal2_state_r <= #TCQ CAL2_DONE;\n else\n cal2_state_r <= #TCQ CAL2_READ_WAIT;\n end\n end\n\n // General wait state to wait for read data to be output by the\n // IN_FIFO\n CAL2_READ_WAIT: begin\n wrcal_pat_resume_r <= #TCQ 1'b0;\n cal2_if_reset <= #TCQ 1'b0;\n // Wait until read data is received, and pattern matching\n // calculation is complete. NOTE: Need to add a timeout here\n // in case for some reason data is never received (or rather\n // the PHASER_IN and IN_FIFO think they never receives data)\n if (pat_data_match_valid_r && (nCK_PER_CLK == 4)) begin\n if (pat_data_match_r)\n // If found data match, then move on to next DQS group\n cal2_state_r <= #TCQ CAL2_NEXT_DQS;\n else begin\n\t\t\t if (wrcal_sanity_chk_r)\n\t\t\t cal2_state_r <= #TCQ CAL2_ERR;\n // If writes are one or two cycles early then redo\n // write leveling for the byte\n else if (early1_data_match_r) begin\n early1_data <= #TCQ 1'b1;\n early2_data <= #TCQ 1'b0;\n wrlvl_byte_redo <= #TCQ 1'b1;\n cal2_state_r <= #TCQ CAL2_WRLVL_WAIT;\n end else if (early2_data_match_r) begin\n early1_data <= #TCQ 1'b0;\n early2_data <= #TCQ 1'b1;\n wrlvl_byte_redo <= #TCQ 1'b1;\n cal2_state_r <= #TCQ CAL2_WRLVL_WAIT;\n // Read late due to incorrect MPR idelay value\n // Decrement Idelay to '0'for the current byte\n end else if (~idelay_ld_done) begin\n cal2_state_r <= #TCQ CAL2_DQ_IDEL_DEC;\n idelay_ld <= #TCQ 1'b1;\n end else\n cal2_state_r <= #TCQ CAL2_ERR; \n end\n end else if (pat_data_match_valid_r && (nCK_PER_CLK == 2)) begin\n if ((pat1_data_match_r1 && pat2_data_match_r) || \n (pat1_detect && pat2_data_match_r))\n // If found data match, then move on to next DQS group\n cal2_state_r <= #TCQ CAL2_NEXT_DQS;\n else if (pat1_data_match_r1 && ~pat2_data_match_r) begin\n cal2_state_r <= #TCQ CAL2_READ_WAIT;\n pat1_detect <= #TCQ 1'b1;\n end else begin\n // If writes are one or two cycles early then redo\n // write leveling for the byte\n if (wrcal_sanity_chk_r)\n\t\t\t cal2_state_r <= #TCQ CAL2_ERR;\n else if ((early1_data_match_r1 && early2_data_match_r) ||\n (early1_detect && early2_data_match_r)) begin\n early1_data <= #TCQ 1'b1;\n early2_data <= #TCQ 1'b0;\n wrlvl_byte_redo <= #TCQ 1'b1;\n cal2_state_r <= #TCQ CAL2_WRLVL_WAIT;\n end else if (early1_data_match_r1 && ~early2_data_match_r) begin\n early1_detect <= #TCQ 1'b1;\n cal2_state_r <= #TCQ CAL2_READ_WAIT;\n // Read late due to incorrect MPR idelay value\n // Decrement Idelay to '0'for the current byte\n end else if (~idelay_ld_done) begin\n cal2_state_r <= #TCQ CAL2_DQ_IDEL_DEC;\n idelay_ld <= #TCQ 1'b1;\n end else\n cal2_state_r <= #TCQ CAL2_ERR; \n end\n end else if (not_empty_wait_cnt == 'd31)\n cal2_state_r <= #TCQ CAL2_ERR;\n end\n \n CAL2_WRLVL_WAIT: begin\n early1_detect <= #TCQ 1'b0;\n if (wrlvl_byte_done && ~wrlvl_byte_done_r)\n wrlvl_byte_redo <= #TCQ 1'b0;\n if (wrlvl_byte_done) begin\n if (rd_active_r1 && ~rd_active_r) begin\n cal2_state_r <= #TCQ CAL2_IFIFO_RESET;\n cal2_if_reset <= #TCQ 1'b1;\n early1_data <= #TCQ 1'b0;\n early2_data <= #TCQ 1'b0;\n end\n end\n end\n \n CAL2_DQ_IDEL_DEC: begin\n if (tap_inc_wait_cnt == 'd4) begin\n idelay_ld <= #TCQ 1'b0;\n cal2_state_r <= #TCQ CAL2_IFIFO_RESET;\n cal2_if_reset <= #TCQ 1'b1;\n idelay_ld_done <= #TCQ 1'b1;\n end\n end\n \n CAL2_IFIFO_RESET: begin\n if (tap_inc_wait_cnt == 'd15) begin\n cal2_if_reset <= #TCQ 1'b0;\n\t\t\tif (wrcal_sanity_chk_r)\n\t\t\t cal2_state_r <= #TCQ CAL2_DONE;\n else if (idelay_ld_done) begin\n wrcal_pat_resume_r <= #TCQ 1'b1;\n cal2_state_r <= #TCQ CAL2_READ_WAIT;\n end else\n cal2_state_r <= #TCQ CAL2_IDLE;\n end\n end\n \n // Final processing for current DQS group. Move on to next group\n CAL2_NEXT_DQS: begin\n // At this point, we've just found the correct pattern for the\n // current DQS group.\n \n // Request bank/row precharge, and wait for its completion. Always\n // precharge after each DQS group to avoid tRAS(max) violation\n\t\t\t\t\t//verilint STARC-2.2.3.3 off\n if (wrcal_sanity_chk_r && (wrcal_dqs_cnt_r != DQS_WIDTH-1)) begin\n\t\t cal2_prech_req_r <= #TCQ 1'b0;\n\t\t\twrcal_dqs_cnt_r <= #TCQ wrcal_dqs_cnt_r + 1;\n cal2_state_r <= #TCQ CAL2_SANITY_WAIT;\n\t\t end else\n\t\t cal2_prech_req_r <= #TCQ 1'b1;\n idelay_ld_done <= #TCQ 1'b0;\n pat1_detect <= #TCQ 1'b0;\n if (prech_done)\n if (((DQS_WIDTH == 1) || (SIM_CAL_OPTION == \"FAST_CAL\")) ||\n (wrcal_dqs_cnt_r == DQS_WIDTH-1)) begin\n // If either FAST_CAL is enabled and first DQS group is \n // finished, or if the last DQS group was just finished,\n // then end of write calibration\n if (wrcal_sanity_chk_r) begin\n\t\t\t cal2_if_reset <= #TCQ 1'b1;\n\t\t\t\tcal2_state_r <= #TCQ CAL2_IFIFO_RESET;\n\t\t\t end else\n cal2_state_r <= #TCQ CAL2_DONE;\n end else begin\n // Continue to next DQS group\n wrcal_dqs_cnt_r <= #TCQ wrcal_dqs_cnt_r + 1;\n cal2_state_r <= #TCQ CAL2_READ_WAIT;\n end\n end\n\t//verilint STARC-2.2.3.3 on\t\n\t\tCAL2_SANITY_WAIT: begin\n\t\t if (tap_inc_wait_cnt == 'd15) begin\n\t\t cal2_state_r <= #TCQ CAL2_READ_WAIT;\n\t\t\twrcal_pat_resume_r <= #TCQ 1'b1;\n\t end\n\t\tend\n\n // Finished with read enable calibration\n CAL2_DONE: begin\n\t\t if (wrcal_sanity_chk && ~wrcal_sanity_chk_r) begin\n\t\t cal2_done_r <= #TCQ 1'b0;\n\t\t\twrcal_dqs_cnt_r <= #TCQ 'd0;\n\t\t\tcal2_state_r <= #TCQ CAL2_IDLE;\n\t\t end else\n cal2_done_r <= #TCQ 1'b1;\n cal2_prech_req_r <= #TCQ 1'b0;\n cal2_if_reset <= #TCQ 1'b0;\n\t\t\tif (wrcal_sanity_chk_r)\n\t\t\t wrcal_sanity_chk_done <= #TCQ 1'b1;\n end\n\n // Assert error signal indicating that writes timing is incorrect\n CAL2_ERR: begin\n wrcal_pat_resume_r <= #TCQ 1'b0;\n if (wrcal_sanity_chk_r)\n wrcal_sanity_chk_err <= #TCQ 1'b1;\n else\n wrcal_pat_err <= #TCQ 1'b1;\n cal2_state_r <= #TCQ CAL2_ERR;\n end\n endcase\n end\n end\n\n // Delay assertion of wrcal_done for write calibration by a few cycles after\n // we've reached CAL2_DONE\n always @(posedge clk)\n if (rst) \n cal2_done_r1 <= #TCQ 1'b0;\n else\n cal2_done_r1 <= #TCQ cal2_done_r;\n \n always @(posedge clk)\n if (rst || (wrcal_sanity_chk && ~wrcal_sanity_chk_r))\n wrcal_done <= #TCQ 1'b0;\n else if (cal2_done_r)\n wrcal_done <= #TCQ 1'b1;\n \nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_wrlvl.v", "content": "//*****************************************************************************\n// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor: Xilinx\n// \\ \\ \\/ Version: %version \n// \\ \\ Application: MIG\n// / / Filename: ddr_phy_wrlvl.v\n// /___/ /\\ Date Last Modified: $Date: 2011/06/24 14:49:00 $\n// \\ \\ / \\ Date Created: Mon Jun 23 2008\n// \\___\\/\\___\\\n//\n//Device: 7 Series\n//Design Name: DDR3 SDRAM\n//Purpose:\n// Memory initialization and overall master state control during\n// initialization and calibration. Specifically, the following functions\n// are performed:\n// 1. Memory initialization (initial AR, mode register programming, etc.)\n// 2. Initiating write leveling\n// 3. Generate training pattern writes for read leveling. Generate\n// memory readback for read leveling.\n// This module has a DFI interface for providing control/address and write\n// data to the rest of the PHY datapath during initialization/calibration.\n// Once initialization is complete, control is passed to the MC. \n// NOTES:\n// 1. Multiple CS (multi-rank) not supported\n// 2. DDR2 not supported\n// 3. ODT not supported\n//Reference:\n//Revision History:\n//*****************************************************************************\n\n/******************************************************************************\n**$Id: ddr_phy_wrlvl.v,v 1.3 2011/06/24 14:49:00 mgeorge Exp $\n**$Date: 2011/06/24 14:49:00 $\n**$Author: mgeorge $\n**$Revision: 1.3 $\n**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_wrlvl.v,v $\n******************************************************************************/\n\n`timescale 1ps/1ps\n\nmodule mig_7series_v4_0_ddr_phy_wrlvl #\n (\n parameter TCQ = 100,\n parameter DQS_CNT_WIDTH = 3,\n parameter DQ_WIDTH = 64,\n parameter DQS_WIDTH = 2,\n parameter DRAM_WIDTH = 8,\n parameter RANKS = 1,\n parameter nCK_PER_CLK = 4,\n parameter CLK_PERIOD = 4,\n parameter SIM_CAL_OPTION = \"NONE\"\n )\n (\n input clk,\n input rst,\n input phy_ctl_ready,\n input wr_level_start,\n input wl_sm_start,\n input wrlvl_final,\n input wrlvl_byte_redo,\n input [DQS_CNT_WIDTH:0] wrcal_cnt,\n input early1_data,\n input early2_data,\n input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt,\n input oclkdelay_calib_done,\n input [(DQ_WIDTH)-1:0] rd_data_rise0,\n output reg wrlvl_byte_done,\n output reg dqs_po_dec_done /* synthesis syn_maxfan = 2 */,\n output phy_ctl_rdy_dly,\n output reg wr_level_done /* synthesis syn_maxfan = 2 */,\n // to phy_init for cs logic\n output wrlvl_rank_done,\n output done_dqs_tap_inc,\n output [DQS_CNT_WIDTH:0] po_stg2_wl_cnt,\n // Fine delay line used only during write leveling\n // Inc/dec Phaser_Out fine delay line\n output reg dqs_po_stg2_f_incdec,\n // Enable Phaser_Out fine delay inc/dec\n output reg dqs_po_en_stg2_f,\n // Coarse delay line used during write leveling\n // only if 64 taps of fine delay line were not\n // sufficient to detect a 0->1 transition\n // Inc Phaser_Out coarse delay line\n output reg dqs_wl_po_stg2_c_incdec,\n // Enable Phaser_Out coarse delay inc/dec\n output reg dqs_wl_po_en_stg2_c,\n // Read Phaser_Out delay value\n input [8:0] po_counter_read_val,\n// output reg dqs_wl_po_stg2_load,\n// output reg [8:0] dqs_wl_po_stg2_reg_l,\n // CK edge undetected\n output reg wrlvl_err,\n output reg [3*DQS_WIDTH-1:0] wl_po_coarse_cnt,\n output reg [6*DQS_WIDTH-1:0] wl_po_fine_cnt,\n // Debug ports\n output [5:0] dbg_wl_tap_cnt,\n output dbg_wl_edge_detect_valid,\n output [(DQS_WIDTH)-1:0] dbg_rd_data_edge_detect,\n output [DQS_CNT_WIDTH:0] dbg_dqs_count,\n output [4:0] dbg_wl_state,\n output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt,\n output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt,\n output [255:0] dbg_phy_wrlvl \n );\n\n\n localparam WL_IDLE = 5'h0;\n localparam WL_INIT = 5'h1;\n localparam WL_INIT_FINE_INC = 5'h2;\n localparam WL_INIT_FINE_INC_WAIT1= 5'h3;\n localparam WL_INIT_FINE_INC_WAIT = 5'h4;\n localparam WL_INIT_FINE_DEC = 5'h5;\n localparam WL_INIT_FINE_DEC_WAIT = 5'h6;\n localparam WL_FINE_INC = 5'h7;\n localparam WL_WAIT = 5'h8;\n localparam WL_EDGE_CHECK = 5'h9;\n localparam WL_DQS_CHECK = 5'hA;\n localparam WL_DQS_CNT = 5'hB;\n localparam WL_2RANK_TAP_DEC = 5'hC;\n localparam WL_2RANK_DQS_CNT = 5'hD;\n localparam WL_FINE_DEC = 5'hE;\n localparam WL_FINE_DEC_WAIT = 5'hF;\n localparam WL_CORSE_INC = 5'h10;\n localparam WL_CORSE_INC_WAIT = 5'h11;\n localparam WL_CORSE_INC_WAIT1 = 5'h12;\n localparam WL_CORSE_INC_WAIT2 = 5'h13;\n localparam WL_CORSE_DEC = 5'h14;\n localparam WL_CORSE_DEC_WAIT = 5'h15;\n localparam WL_CORSE_DEC_WAIT1 = 5'h16;\n localparam WL_FINE_INC_WAIT = 5'h17;\n localparam WL_2RANK_FINAL_TAP = 5'h18;\n localparam WL_INIT_FINE_DEC_WAIT1= 5'h19;\n localparam WL_FINE_DEC_WAIT1 = 5'h1A;\n localparam WL_CORSE_INC_WAIT_TMP = 5'h1B;\n\n localparam COARSE_TAPS = 7;\n \n localparam FAST_CAL_FINE = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 45 : 48;\n localparam FAST_CAL_COARSE = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 1 : 2;\n localparam REDO_COARSE = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 2 : 5;\n\n\n integer i, j, k, l, p, q, r, s, t, m, n, u, v, w, x,y;\n\n reg phy_ctl_ready_r1;\n reg phy_ctl_ready_r2;\n reg phy_ctl_ready_r3;\n reg phy_ctl_ready_r4;\n reg phy_ctl_ready_r5;\n reg phy_ctl_ready_r6;\n (* max_fanout = 50 *) reg [DQS_CNT_WIDTH:0] dqs_count_r;\n reg [1:0] rank_cnt_r;\n reg [DQS_WIDTH-1:0] rd_data_rise_wl_r;\n reg [DQS_WIDTH-1:0] rd_data_previous_r;\n reg [DQS_WIDTH-1:0] rd_data_edge_detect_r;\n reg wr_level_done_r;\n reg wrlvl_rank_done_r;\n reg wr_level_start_r;\n reg [4:0] wl_state_r, wl_state_r1;\n reg inhibit_edge_detect_r;\n reg wl_edge_detect_valid_r;\n reg [5:0] wl_tap_count_r;\n reg [5:0] fine_dec_cnt;\n reg [5:0] fine_inc[0:DQS_WIDTH-1]; // DQS_WIDTH number of counters 6-bit each\n reg [2:0] corse_dec[0:DQS_WIDTH-1];\n reg [2:0] corse_inc[0:DQS_WIDTH-1];\n reg dq_cnt_inc;\n reg [3:0] stable_cnt;\n reg flag_ck_negedge;\n //reg past_negedge;\n reg flag_init;\n reg [2:0] corse_cnt[0:DQS_WIDTH-1];\n reg [3*DQS_WIDTH-1:0] corse_cnt_dbg;\n reg [2:0] wl_corse_cnt[0:RANKS-1][0:DQS_WIDTH-1];\n //reg [3*DQS_WIDTH-1:0] coarse_tap_inc;\n reg [2:0] final_coarse_tap[0:DQS_WIDTH-1];\n reg [5:0] add_smallest[0:DQS_WIDTH-1];\n reg [5:0] add_largest[0:DQS_WIDTH-1];\n //reg [6*DQS_WIDTH-1:0] fine_tap_inc;\n //reg [6*DQS_WIDTH-1:0] fine_tap_dec;\n reg wr_level_done_r1;\n reg wr_level_done_r2;\n reg wr_level_done_r3;\n reg wr_level_done_r4;\n reg wr_level_done_r5;\n reg [5:0] wl_dqs_tap_count_r[0:RANKS-1][0:DQS_WIDTH-1];\n reg [5:0] smallest[0:DQS_WIDTH-1];\n reg [5:0] largest[0:DQS_WIDTH-1];\n reg [5:0] final_val[0:DQS_WIDTH-1];\n reg [5:0] po_dec_cnt[0:DQS_WIDTH-1];\n reg done_dqs_dec;\n reg [8:0] po_rdval_cnt;\n reg po_cnt_dec;\n reg po_dec_done;\n reg dual_rnk_dec;\n wire [DQS_CNT_WIDTH+2:0] dqs_count_w;\n reg [5:0] fast_cal_fine_cnt;\n reg [2:0] fast_cal_coarse_cnt;\n reg wrlvl_byte_redo_r;\n reg [2:0] wrlvl_redo_corse_inc;\n reg wrlvl_final_r;\n reg final_corse_dec;\n wire [DQS_CNT_WIDTH+2:0] oclk_count_w;\n reg wrlvl_tap_done_r ;\n reg [3:0] wait_cnt;\n reg [3:0] incdec_wait_cnt;\n \n\n\n // Debug ports\n assign dbg_wl_edge_detect_valid = wl_edge_detect_valid_r;\n assign dbg_rd_data_edge_detect = rd_data_edge_detect_r;\n assign dbg_wl_tap_cnt = wl_tap_count_r;\n assign dbg_dqs_count = dqs_count_r;\n assign dbg_wl_state = wl_state_r;\n assign dbg_wrlvl_fine_tap_cnt = wl_po_fine_cnt;\n assign dbg_wrlvl_coarse_tap_cnt = wl_po_coarse_cnt;\n\n always @(*) begin\n for (v = 0; v < DQS_WIDTH; v = v + 1)\n corse_cnt_dbg[3*v+:3] = corse_cnt[v];\n end\n \n assign dbg_phy_wrlvl[0+:27] = corse_cnt_dbg;\n assign dbg_phy_wrlvl[27+:5] = wl_state_r;\n assign dbg_phy_wrlvl[32+:4] = dqs_count_r;\n assign dbg_phy_wrlvl[36+:9] = rd_data_rise_wl_r;\n assign dbg_phy_wrlvl[45+:9] = rd_data_previous_r;\n assign dbg_phy_wrlvl[54+:4] = stable_cnt;\n assign dbg_phy_wrlvl[58] = 'd0;\n assign dbg_phy_wrlvl[59] = flag_ck_negedge;\n\n assign dbg_phy_wrlvl [60] = wl_edge_detect_valid_r;\n assign dbg_phy_wrlvl [61+:6] = wl_tap_count_r;\n assign dbg_phy_wrlvl [67+:9] = rd_data_edge_detect_r;\n assign dbg_phy_wrlvl [76+:54] = wl_po_fine_cnt;\n assign dbg_phy_wrlvl [130+:27] = wl_po_coarse_cnt;\n \n\n \n //**************************************************************************\n // DQS count to hard PHY during write leveling using Phaser_OUT Stage2 delay \n //**************************************************************************\n assign po_stg2_wl_cnt = dqs_count_r;\n\n assign wrlvl_rank_done = wrlvl_rank_done_r;\n \n assign done_dqs_tap_inc = done_dqs_dec;\n \n assign phy_ctl_rdy_dly = phy_ctl_ready_r6;\n \n always @(posedge clk) begin\n phy_ctl_ready_r1 <= #TCQ phy_ctl_ready;\n phy_ctl_ready_r2 <= #TCQ phy_ctl_ready_r1;\n phy_ctl_ready_r3 <= #TCQ phy_ctl_ready_r2;\n phy_ctl_ready_r4 <= #TCQ phy_ctl_ready_r3;\n phy_ctl_ready_r5 <= #TCQ phy_ctl_ready_r4;\n phy_ctl_ready_r6 <= #TCQ phy_ctl_ready_r5;\n wrlvl_byte_redo_r <= #TCQ wrlvl_byte_redo;\n wrlvl_final_r <= #TCQ wrlvl_final;\n if ((wrlvl_byte_redo && ~wrlvl_byte_redo_r) ||\n (wrlvl_final && ~wrlvl_final_r))\n wr_level_done <= #TCQ 1'b0;\n else\n wr_level_done <= #TCQ done_dqs_dec;\n end\n\n// Status signal that will be asserted once the first \n// pass of write leveling is done. \n always @(posedge clk) begin\n if(rst) begin\n wrlvl_tap_done_r <= #TCQ 1'b0 ;\n end else begin\n if(wrlvl_tap_done_r == 1'b0) begin\n if(oclkdelay_calib_done) begin\n\t wrlvl_tap_done_r <= #TCQ 1'b1 ;\n\t end\n end\n end\n end\n \n always @(posedge clk) begin\n if (rst || po_cnt_dec)\n wait_cnt <= #TCQ 'd8;\n else if (phy_ctl_ready_r6 && (wait_cnt > 'd0))\n wait_cnt <= #TCQ wait_cnt - 1;\n end\n \n always @(posedge clk) begin\n if (rst) begin\n po_rdval_cnt <= #TCQ 'd0;\n end else if (phy_ctl_ready_r5 && ~phy_ctl_ready_r6) begin\n po_rdval_cnt <= #TCQ po_counter_read_val;\n end else if (po_rdval_cnt > 'd0) begin\n if (po_cnt_dec)\n po_rdval_cnt <= #TCQ po_rdval_cnt - 1;\n else \n po_rdval_cnt <= #TCQ po_rdval_cnt;\n end else if (po_rdval_cnt == 'd0) begin\n po_rdval_cnt <= #TCQ po_rdval_cnt;\n end\n end\n\n always @(posedge clk) begin\n if (rst || (po_rdval_cnt == 'd0))\n po_cnt_dec <= #TCQ 1'b0;\n else if (phy_ctl_ready_r6 && (po_rdval_cnt > 'd0) && (wait_cnt == 'd1))\n po_cnt_dec <= #TCQ 1'b1;\n else\n po_cnt_dec <= #TCQ 1'b0;\n end\n \n always @(posedge clk) begin\n if (rst)\n po_dec_done <= #TCQ 1'b0;\n else if (((po_cnt_dec == 'd1) && (po_rdval_cnt == 'd1)) || \n (phy_ctl_ready_r6 && (po_rdval_cnt == 'd0))) begin\n po_dec_done <= #TCQ 1'b1;\n end\n end\n\n \n always @(posedge clk) begin\n dqs_po_dec_done <= #TCQ po_dec_done;\n wr_level_done_r1 <= #TCQ wr_level_done_r;\n wr_level_done_r2 <= #TCQ wr_level_done_r1;\n wr_level_done_r3 <= #TCQ wr_level_done_r2;\n wr_level_done_r4 <= #TCQ wr_level_done_r3;\n wr_level_done_r5 <= #TCQ wr_level_done_r4;\n for (l = 0; l < DQS_WIDTH; l = l + 1) begin \n wl_po_coarse_cnt[3*l+:3] <= #TCQ final_coarse_tap[l];\n if ((RANKS == 1) || ~oclkdelay_calib_done)\n wl_po_fine_cnt[6*l+:6] <= #TCQ smallest[l];\n else \n wl_po_fine_cnt[6*l+:6] <= #TCQ final_val[l];\n end\n end\n \n generate\n if (RANKS == 2) begin: dual_rank\n always @(posedge clk) begin\n if (rst || (wrlvl_byte_redo && ~wrlvl_byte_redo_r) ||\n (wrlvl_final && ~wrlvl_final_r))\n done_dqs_dec <= #TCQ 1'b0;\n else if ((SIM_CAL_OPTION == \"FAST_CAL\") || ~oclkdelay_calib_done)\n done_dqs_dec <= #TCQ wr_level_done_r;\n else if (wr_level_done_r5 && (wl_state_r == WL_IDLE))\n done_dqs_dec <= #TCQ 1'b1;\n end\n end else begin: single_rank\n always @(posedge clk) begin\n if (rst || (wrlvl_byte_redo && ~wrlvl_byte_redo_r) ||\n (wrlvl_final && ~wrlvl_final_r))\n done_dqs_dec <= #TCQ 1'b0;\n else if (~oclkdelay_calib_done)\n done_dqs_dec <= #TCQ wr_level_done_r;\n else if (wr_level_done_r3 && ~wr_level_done_r4)\n done_dqs_dec <= #TCQ 1'b1;\n end\n end\n endgenerate\n \n always @(posedge clk)\n if (rst || (wrlvl_byte_redo && ~wrlvl_byte_redo_r))\n wrlvl_byte_done <= #TCQ 1'b0;\n else if (wrlvl_byte_redo && wr_level_done_r3 && ~wr_level_done_r4)\n wrlvl_byte_done <= #TCQ 1'b1;\n \n // Storing DQS tap values at the end of each DQS write leveling\n always @(posedge clk) begin\n if (rst) begin\n for (k = 0; k < RANKS; k = k + 1) begin: rst_wl_dqs_tap_count_loop\n for (n = 0; n < DQS_WIDTH; n = n + 1) begin\n wl_corse_cnt[k][n] <= #TCQ 'b0;\n wl_dqs_tap_count_r[k][n] <= #TCQ 'b0;\n end\n end\n end else if ((wl_state_r == WL_DQS_CNT) | (wl_state_r == WL_WAIT) | \n (wl_state_r == WL_FINE_DEC_WAIT1) |\n (wl_state_r == WL_2RANK_TAP_DEC)) begin\n wl_dqs_tap_count_r[rank_cnt_r][dqs_count_r] <= #TCQ wl_tap_count_r;\n wl_corse_cnt[rank_cnt_r][dqs_count_r] <= #TCQ corse_cnt[dqs_count_r];\n end else if ((SIM_CAL_OPTION == \"FAST_CAL\") & (wl_state_r == WL_DQS_CHECK)) begin\n for (p = 0; p < RANKS; p = p +1) begin: dqs_tap_rank_cnt \n for(q = 0; q < DQS_WIDTH; q = q +1) begin: dqs_tap_dqs_cnt\n wl_dqs_tap_count_r[p][q] <= #TCQ wl_tap_count_r;\n wl_corse_cnt[p][q] <= #TCQ corse_cnt[0];\n end\n end\n end\n end\n \n // Convert coarse delay to fine taps in case of unequal number of coarse\n // taps between ranks. Assuming a difference of 1 coarse tap counts\n // between ranks. A common fine and coarse tap value must be used for both ranks\n // because Phaser_Out has only one rank register.\n // Coarse tap1 = period(ps)*93/360 = 34 fine taps\n // Other coarse taps = period(ps)*103/360 = 38 fine taps\n\n generate\n genvar cnt;\n if (RANKS == 2) begin // Dual rank\n for(cnt = 0; cnt < DQS_WIDTH; cnt = cnt +1) begin: coarse_dqs_cnt\n always @(posedge clk) begin\n if (rst) begin\n //coarse_tap_inc[3*cnt+:3] <= #TCQ 'b0;\n add_smallest[cnt] <= #TCQ 'd0;\n add_largest[cnt] <= #TCQ 'd0;\n final_coarse_tap[cnt] <= #TCQ 'd0;\n end else if (wr_level_done_r1 & ~wr_level_done_r2) begin\n if (~oclkdelay_calib_done) begin\n\t for(y = 0 ; y < DQS_WIDTH; y = y+1) begin\n final_coarse_tap[y] <= #TCQ wl_corse_cnt[0][y]; \n add_smallest[y] <= #TCQ 'd0;\n add_largest[y] <= #TCQ 'd0;\n\t end\n end else \n\t if (wl_corse_cnt[0][cnt] == wl_corse_cnt[1][cnt]) begin\n // Both ranks have use the same number of coarse delay taps.\n // No conversion of coarse tap to fine taps required. \n //coarse_tap_inc[3*cnt+:3] <= #TCQ wl_corse_cnt[1][3*cnt+:3];\n final_coarse_tap[cnt] <= #TCQ wl_corse_cnt[1][cnt];\n add_smallest[cnt] <= #TCQ 'd0;\n add_largest[cnt] <= #TCQ 'd0;\n end else if (wl_corse_cnt[0][cnt] < wl_corse_cnt[1][cnt]) begin\n // Rank 0 uses fewer coarse delay taps than rank1.\n // conversion of coarse tap to fine taps required for rank1.\n // The final coarse count will the smaller value.\n //coarse_tap_inc[3*cnt+:3] <= #TCQ wl_corse_cnt[1][3*cnt+:3] - 1;\n final_coarse_tap[cnt] <= #TCQ wl_corse_cnt[1][cnt] - 1;\n if (|wl_corse_cnt[0][cnt])\n // Coarse tap 2 or higher being converted to fine taps\n // This will be added to 'largest' value in final_val\n // computation \n add_largest[cnt] <= #TCQ 'd38;\n else\n // Coarse tap 1 being converted to fine taps\n // This will be added to 'largest' value in final_val\n // computation\n add_largest[cnt] <= #TCQ 'd34;\n end else if (wl_corse_cnt[0][cnt] > wl_corse_cnt[1][cnt]) begin\n // This may be an unlikely scenario in a real system.\n // Rank 0 uses more coarse delay taps than rank1.\n // conversion of coarse tap to fine taps required.\n //coarse_tap_inc[3*cnt+:3] <= #TCQ 'd0;\n final_coarse_tap[cnt] <= #TCQ wl_corse_cnt[1][cnt];\n if (|wl_corse_cnt[1][cnt])\n // Coarse tap 2 or higher being converted to fine taps\n // This will be added to 'smallest' value in final_val\n // computation\n add_smallest[cnt] <= #TCQ 'd38;\n else\n // Coarse tap 1 being converted to fine taps\n // This will be added to 'smallest' value in\n // final_val computation\n add_smallest[cnt] <= #TCQ 'd34;\n end\n end\n end\n end\n end else begin\n // Single rank\n always @(posedge clk) begin\n //coarse_tap_inc <= #TCQ 'd0;\n for(w = 0; w < DQS_WIDTH; w = w + 1) begin\n final_coarse_tap[w] <= #TCQ wl_corse_cnt[0][w];\n add_smallest[w] <= #TCQ 'd0;\n add_largest[w] <= #TCQ 'd0;\n end\n end\n end\n endgenerate\n\n \n // Determine delay value for DQS in multirank system\n // Assuming delay value is the smallest for rank 0 DQS \n // and largest delay value for rank 4 DQS\n // Set to smallest + ((largest-smallest)/2)\n always @(posedge clk) begin\n if (rst) begin\n for(x = 0; x < DQS_WIDTH; x = x +1) begin\n smallest[x] <= #TCQ 'b0;\n largest[x] <= #TCQ 'b0;\n end\n end else if ((wl_state_r == WL_DQS_CNT) & wrlvl_byte_redo) begin\n smallest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[0][dqs_count_r];\n largest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[0][dqs_count_r];\n end else if ((wl_state_r == WL_DQS_CNT) | \n (wl_state_r == WL_2RANK_TAP_DEC)) begin\n smallest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[0][dqs_count_r];\n largest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[RANKS-1][dqs_count_r];\n end else if (((SIM_CAL_OPTION == \"FAST_CAL\") | \n (~oclkdelay_calib_done & ~wrlvl_byte_redo)) & \n wr_level_done_r1 & ~wr_level_done_r2) begin\n for(i = 0; i < DQS_WIDTH; i = i +1) begin: smallest_dqs\n smallest[i] <= #TCQ wl_dqs_tap_count_r[0][i];\n largest[i] <= #TCQ wl_dqs_tap_count_r[0][i];\n end\n end\n end\n\n \n// final_val to be used for all DQSs in all ranks \n genvar wr_i;\n generate\n for (wr_i = 0; wr_i < DQS_WIDTH; wr_i = wr_i +1) begin: gen_final_tap\n always @(posedge clk) begin\n if (rst)\n final_val[wr_i] <= #TCQ 'b0;\n else if (wr_level_done_r2 && ~wr_level_done_r3) begin\n if (~oclkdelay_calib_done)\n final_val[wr_i] <= #TCQ (smallest[wr_i] + add_smallest[wr_i]); \n else if ((smallest[wr_i] + add_smallest[wr_i]) < \n (largest[wr_i] + add_largest[wr_i]))\n final_val[wr_i] <= #TCQ ((smallest[wr_i] + add_smallest[wr_i]) +\n (((largest[wr_i] + add_largest[wr_i]) -\n (smallest[wr_i] + add_smallest[wr_i]))/2));\n else if ((smallest[wr_i] + add_smallest[wr_i]) >\n (largest[wr_i] + add_largest[wr_i]))\n final_val[wr_i] <= #TCQ ((largest[wr_i] + add_largest[wr_i]) +\n (((smallest[wr_i] + add_smallest[wr_i]) -\n (largest[wr_i] + add_largest[wr_i]))/2));\n else if ((smallest[wr_i] + add_smallest[wr_i]) ==\n (largest[wr_i] + add_largest[wr_i]))\n final_val[wr_i] <= #TCQ (largest[wr_i] + add_largest[wr_i]);\n end\n end\n end\n endgenerate\n \n// // fine tap inc/dec value for all DQSs in all ranks\n// genvar dqs_i;\n// generate\n// for (dqs_i = 0; dqs_i < DQS_WIDTH; dqs_i = dqs_i +1) begin: gen_fine_tap\n// always @(posedge clk) begin\n// if (rst)\n// fine_tap_inc[6*dqs_i+:6] <= #TCQ 'd0;\n// //fine_tap_dec[6*dqs_i+:6] <= #TCQ 'd0;\n// else if (wr_level_done_r3 && ~wr_level_done_r4) begin\n// fine_tap_inc[6*dqs_i+:6] <= #TCQ final_val[6*dqs_i+:6];\n// //fine_tap_dec[6*dqs_i+:6] <= #TCQ 'd0;\n// end\n// end\n// endgenerate\n\n \n // Inc/Dec Phaser_Out stage 2 fine delay line\n always @(posedge clk) begin\n if (rst) begin\n // Fine delay line used only during write leveling\n dqs_po_stg2_f_incdec <= #TCQ 1'b0;\n dqs_po_en_stg2_f <= #TCQ 1'b0;\n // Dec Phaser_Out fine delay (1)before write leveling,\n // (2)if no 0 to 1 transition detected with 63 fine delay taps, or \n // (3)dual rank case where fine taps for the first rank need to be 0\n end else if (po_cnt_dec || (wl_state_r == WL_INIT_FINE_DEC) ||\n (wl_state_r == WL_FINE_DEC)) begin\n dqs_po_stg2_f_incdec <= #TCQ 1'b0;\n dqs_po_en_stg2_f <= #TCQ 1'b1;\n // Inc Phaser_Out fine delay during write leveling\n end else if ((wl_state_r == WL_INIT_FINE_INC) ||\n (wl_state_r == WL_FINE_INC)) begin\n dqs_po_stg2_f_incdec <= #TCQ 1'b1;\n dqs_po_en_stg2_f <= #TCQ 1'b1;\n end else begin\n dqs_po_stg2_f_incdec <= #TCQ 1'b0;\n dqs_po_en_stg2_f <= #TCQ 1'b0; \n end\n end\n \n\n // Inc Phaser_Out stage 2 Coarse delay line\n always @(posedge clk) begin\n if (rst) begin\n // Coarse delay line used during write leveling\n // only if no 0->1 transition undetected with 64\n // fine delay line taps\n dqs_wl_po_stg2_c_incdec <= #TCQ 1'b0;\n dqs_wl_po_en_stg2_c <= #TCQ 1'b0;\n end else if (wl_state_r == WL_CORSE_INC) begin\n // Inc Phaser_Out coarse delay during write leveling\n dqs_wl_po_stg2_c_incdec <= #TCQ 1'b1;\n dqs_wl_po_en_stg2_c <= #TCQ 1'b1;\n end else begin\n dqs_wl_po_stg2_c_incdec <= #TCQ 1'b0;\n dqs_wl_po_en_stg2_c <= #TCQ 1'b0; \n end\n end\n \n\n // only storing the rise data for checking. The data comming back during\n // write leveling will be a static value. Just checking for rise data is\n // enough. \n\ngenvar rd_i;\ngenerate\n for(rd_i = 0; rd_i < DQS_WIDTH; rd_i = rd_i +1)begin: gen_rd\n always @(posedge clk)\n rd_data_rise_wl_r[rd_i] <=\n #TCQ |rd_data_rise0[(rd_i*DRAM_WIDTH)+DRAM_WIDTH-1:rd_i*DRAM_WIDTH];\n end\nendgenerate\n\n\n // storing the previous data for checking later.\n always @(posedge clk)begin\n if ((wl_state_r == WL_INIT) || //(wl_state_r == WL_INIT_FINE_INC_WAIT) ||\n //(wl_state_r == WL_INIT_FINE_INC_WAIT1) ||\n\t\t ((wl_state_r1 == WL_INIT_FINE_INC_WAIT) & (wl_state_r == WL_INIT_FINE_INC)) ||\n (wl_state_r == WL_FINE_DEC) || (wl_state_r == WL_FINE_DEC_WAIT1) || (wl_state_r == WL_FINE_DEC_WAIT) ||\n (wl_state_r == WL_CORSE_INC) || (wl_state_r == WL_CORSE_INC_WAIT) || (wl_state_r == WL_CORSE_INC_WAIT_TMP) || \n (wl_state_r == WL_CORSE_INC_WAIT1) || (wl_state_r == WL_CORSE_INC_WAIT2) ||\n ((wl_state_r == WL_EDGE_CHECK) & (wl_edge_detect_valid_r)))\n rd_data_previous_r <= #TCQ rd_data_rise_wl_r;\n end\n \n // changed stable count from 3 to 7 because of fine tap resolution\n always @(posedge clk)begin\n if (rst | (wl_state_r == WL_DQS_CNT) |\n (wl_state_r == WL_2RANK_TAP_DEC) |\n (wl_state_r == WL_FINE_DEC) |\n (rd_data_previous_r[dqs_count_r] != rd_data_rise_wl_r[dqs_count_r]) |\n (wl_state_r1 == WL_INIT_FINE_DEC))\n stable_cnt <= #TCQ 'd0;\n else if ((wl_tap_count_r > 6'd0) & \n (((wl_state_r == WL_EDGE_CHECK) & (wl_edge_detect_valid_r)) |\n ((wl_state_r1 == WL_INIT_FINE_INC_WAIT) & (wl_state_r == WL_INIT_FINE_INC)))) begin\n if ((rd_data_previous_r[dqs_count_r] == rd_data_rise_wl_r[dqs_count_r])\n & (stable_cnt < 'd14))\n stable_cnt <= #TCQ stable_cnt + 1;\n end\n end\n \n // Signal to ensure that flag_ck_negedge does not incorrectly assert\n // when DQS is very close to CK rising edge\n //always @(posedge clk) begin\n // if (rst | (wl_state_r == WL_DQS_CNT) |\n // (wl_state_r == WL_DQS_CHECK) | wr_level_done_r)\n // past_negedge <= #TCQ 1'b0;\n // else if (~flag_ck_negedge && ~rd_data_previous_r[dqs_count_r] &&\n // (stable_cnt == 'd0) && ((wl_state_r == WL_CORSE_INC_WAIT1) |\n // (wl_state_r == WL_CORSE_INC_WAIT2)))\n // past_negedge <= #TCQ 1'b1;\n //end \n \n // Flag to indicate negedge of CK detected and ignore 0->1 transitions\n // in this region\n always @(posedge clk)begin\n if (rst | (wl_state_r == WL_DQS_CNT) |\n (wl_state_r == WL_DQS_CHECK) | wr_level_done_r |\n (wl_state_r1 == WL_INIT_FINE_DEC))\n flag_ck_negedge <= #TCQ 1'd0;\n else if ((rd_data_previous_r[dqs_count_r] && ((stable_cnt > 'd0) |\n (wl_state_r == WL_FINE_DEC) | (wl_state_r == WL_FINE_DEC_WAIT) | (wl_state_r == WL_FINE_DEC_WAIT1))) |\n\t\t\t (wl_state_r == WL_CORSE_INC)) \n flag_ck_negedge <= #TCQ 1'd1;\n else if (~rd_data_previous_r[dqs_count_r] && (stable_cnt == 'd14))\n //&& flag_ck_negedge)\n flag_ck_negedge <= #TCQ 1'd0;\n end\n \n // Flag to inhibit rd_data_edge_detect_r before stable DQ\n always @(posedge clk) begin\n if (rst)\n flag_init <= #TCQ 1'b1;\n else if ((wl_state_r == WL_WAIT) && ((wl_state_r1 == WL_INIT_FINE_INC_WAIT) ||\n (wl_state_r1 == WL_INIT_FINE_DEC_WAIT)))\n flag_init <= #TCQ 1'b0;\n end\n\n //checking for transition from 0 to 1\n always @(posedge clk)begin\n if (rst | flag_ck_negedge | flag_init | (wl_tap_count_r < 'd1) |\n inhibit_edge_detect_r)\n rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}};\n else if (rd_data_edge_detect_r[dqs_count_r] == 1'b1) begin\n if ((wl_state_r == WL_FINE_DEC) || (wl_state_r == WL_FINE_DEC_WAIT) || (wl_state_r == WL_FINE_DEC_WAIT1) ||\n (wl_state_r == WL_CORSE_INC) || (wl_state_r == WL_CORSE_INC_WAIT) || (wl_state_r == WL_CORSE_INC_WAIT_TMP) ||\n (wl_state_r == WL_CORSE_INC_WAIT1) || (wl_state_r == WL_CORSE_INC_WAIT2))\n rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}};\n else\n rd_data_edge_detect_r <= #TCQ rd_data_edge_detect_r;\n end else if (rd_data_previous_r[dqs_count_r] && (stable_cnt < 'd14))\n rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}};\n else\n rd_data_edge_detect_r <= #TCQ (~rd_data_previous_r & rd_data_rise_wl_r);\n end\n\n\n \n // registring the write level start signal\n always@(posedge clk) begin\n wr_level_start_r <= #TCQ wr_level_start;\n end\n\n // Assign dqs_count_r to dqs_count_w to perform the shift operation \n // instead of multiply operation \n assign dqs_count_w = {2'b00, dqs_count_r};\n\n assign oclk_count_w = {2'b00, oclkdelay_calib_cnt};\n \n always @(posedge clk) begin\n if (rst)\n incdec_wait_cnt <= #TCQ 'd0;\n else if ((wl_state_r == WL_FINE_DEC_WAIT1) ||\n (wl_state_r == WL_INIT_FINE_DEC_WAIT1) ||\n (wl_state_r == WL_CORSE_INC_WAIT_TMP))\n incdec_wait_cnt <= #TCQ incdec_wait_cnt + 1;\n else\n incdec_wait_cnt <= #TCQ 'd0;\n end\n \n \n // state machine to initiate the write leveling sequence\n // The state machine operates on one byte at a time.\n // It will increment the delays to the DQS OSERDES\n // and sample the DQ from the memory. When it detects\n // a transition from 1 to 0 then the write leveling is considered\n // done. \n always @(posedge clk) begin\n if(rst)begin\n wrlvl_err <= #TCQ 1'b0;\n wr_level_done_r <= #TCQ 1'b0;\n wrlvl_rank_done_r <= #TCQ 1'b0;\n dqs_count_r <= #TCQ {DQS_CNT_WIDTH+1{1'b0}};\n dq_cnt_inc <= #TCQ 1'b1;\n rank_cnt_r <= #TCQ 2'b00;\n wl_state_r <= #TCQ WL_IDLE;\n wl_state_r1 <= #TCQ WL_IDLE;\n inhibit_edge_detect_r <= #TCQ 1'b1;\n wl_edge_detect_valid_r <= #TCQ 1'b0;\n wl_tap_count_r <= #TCQ 6'd0;\n fine_dec_cnt <= #TCQ 6'd0;\n for (r = 0; r < DQS_WIDTH; r = r + 1) begin\n fine_inc[r] <= #TCQ 6'b0;\n corse_dec[r] <= #TCQ 3'b0;\n corse_inc[r] <= #TCQ 3'b0;\n corse_cnt[r] <= #TCQ 3'b0;\n end\n dual_rnk_dec <= #TCQ 1'b0;\n fast_cal_fine_cnt <= #TCQ FAST_CAL_FINE;\n fast_cal_coarse_cnt <= #TCQ FAST_CAL_COARSE;\n final_corse_dec <= #TCQ 1'b0;\n //zero_tran_r <= #TCQ 1'b0;\n wrlvl_redo_corse_inc <= #TCQ 'd0;\n end else begin\n wl_state_r1 <= #TCQ wl_state_r;\n case (wl_state_r)\n \n WL_IDLE: begin\n wrlvl_rank_done_r <= #TCQ 1'd0;\n inhibit_edge_detect_r <= #TCQ 1'b1;\n if (wrlvl_byte_redo && ~wrlvl_byte_redo_r) begin\n wr_level_done_r <= #TCQ 1'b0;\n dqs_count_r <= #TCQ wrcal_cnt;\n corse_cnt[wrcal_cnt] <= #TCQ final_coarse_tap[wrcal_cnt];\n wl_tap_count_r <= #TCQ smallest[wrcal_cnt];\n if (early1_data && \n (((final_coarse_tap[wrcal_cnt] < 'd6) && (CLK_PERIOD/nCK_PER_CLK <= 2500)) ||\n ((final_coarse_tap[wrcal_cnt] < 'd3) && (CLK_PERIOD/nCK_PER_CLK > 2500))))\n wrlvl_redo_corse_inc <= #TCQ REDO_COARSE;\n else if (early2_data && (final_coarse_tap[wrcal_cnt] < 'd2))\n wrlvl_redo_corse_inc <= #TCQ 3'd6;\n else begin\n wl_state_r <= #TCQ WL_IDLE;\n wrlvl_err <= #TCQ 1'b1;\n end\n end else if (wrlvl_final && ~wrlvl_final_r) begin\n wr_level_done_r <= #TCQ 1'b0;\n dqs_count_r <= #TCQ 'd0;\n end\n\t\t\t\t\t\t\t// verilint STARC-2.2.3.3 off\n if(!wr_level_done_r & wr_level_start_r & wl_sm_start) begin\n if (SIM_CAL_OPTION == \"FAST_CAL\")\n wl_state_r <= #TCQ WL_FINE_INC;\n else\n wl_state_r <= #TCQ WL_INIT;\n end\n end\n // verilint STARC-2.2.3.3 on\n WL_INIT: begin\n wl_edge_detect_valid_r <= #TCQ 1'b0;\n inhibit_edge_detect_r <= #TCQ 1'b1;\n wrlvl_rank_done_r <= #TCQ 1'd0;\n //zero_tran_r <= #TCQ 1'b0;\n if (wrlvl_final)\n corse_cnt[dqs_count_w ] <= #TCQ final_coarse_tap[dqs_count_w ]; \n if (wrlvl_byte_redo) begin\n if (|wl_tap_count_r) begin\n wl_state_r <= #TCQ WL_FINE_DEC;\n fine_dec_cnt <= #TCQ wl_tap_count_r;\n end else if ((corse_cnt[dqs_count_w] + wrlvl_redo_corse_inc) <= 'd7)\n wl_state_r <= #TCQ WL_CORSE_INC;\n else begin\n wl_state_r <= #TCQ WL_IDLE;\n wrlvl_err <= #TCQ 1'b1;\n end\n end else if(wl_sm_start)\n wl_state_r <= #TCQ WL_INIT_FINE_INC;\n end\n \n // Initially Phaser_Out fine delay taps incremented\n // until stable_cnt=14. A stable_cnt of 14 indicates\n // that rd_data_rise_wl_r=rd_data_previous_r for 14 fine\n // tap increments. This is done to inhibit false 0->1 \n // edge detection when DQS is initially aligned to the\n // negedge of CK\n WL_INIT_FINE_INC: begin\n wl_state_r <= #TCQ WL_INIT_FINE_INC_WAIT1;\n wl_tap_count_r <= #TCQ wl_tap_count_r + 1'b1;\n final_corse_dec <= #TCQ 1'b0;\n end\n\n WL_INIT_FINE_INC_WAIT1: begin\n if (wl_sm_start)\n wl_state_r <= #TCQ WL_INIT_FINE_INC_WAIT;\n end\n\n // Case1: stable value of rd_data_previous_r=0 then\n // proceed to 0->1 edge detection.\n // Case2: stable value of rd_data_previous_r=1 then\n // decrement fine taps to '0' and proceed to 0->1\n // edge detection. Need to decrement in this case to\n // make sure a valid 0->1 transition was not left \n // undetected. \n WL_INIT_FINE_INC_WAIT: begin\n if (wl_sm_start) begin\n if (stable_cnt < 'd14)\n wl_state_r <= #TCQ WL_INIT_FINE_INC;\n else if (~rd_data_previous_r[dqs_count_r]) begin\n wl_state_r <= #TCQ WL_WAIT;\n inhibit_edge_detect_r <= #TCQ 1'b0;\n end else begin\n wl_state_r <= #TCQ WL_INIT_FINE_DEC;\n fine_dec_cnt <= #TCQ wl_tap_count_r;\n end\n end\n end\n\n // Case2: stable value of rd_data_previous_r=1 then\n // decrement fine taps to '0' and proceed to 0->1\n // edge detection. Need to decrement in this case to\n // make sure a valid 0->1 transition was not left \n // undetected.\n WL_INIT_FINE_DEC: begin\n wl_tap_count_r <= #TCQ 'd0;\n wl_state_r <= #TCQ WL_INIT_FINE_DEC_WAIT1;\n if (fine_dec_cnt > 6'd0)\n fine_dec_cnt <= #TCQ fine_dec_cnt - 1;\n else\n fine_dec_cnt <= #TCQ fine_dec_cnt;\n end\n \n WL_INIT_FINE_DEC_WAIT1: begin\n if (incdec_wait_cnt == 'd8)\n wl_state_r <= #TCQ WL_INIT_FINE_DEC_WAIT;\n end\n \n WL_INIT_FINE_DEC_WAIT: begin\n if (fine_dec_cnt > 6'd0) begin\n wl_state_r <= #TCQ WL_INIT_FINE_DEC;\n inhibit_edge_detect_r <= #TCQ 1'b1;\n end else begin\n wl_state_r <= #TCQ WL_WAIT;\n inhibit_edge_detect_r <= #TCQ 1'b0;\n end\n end\n \n // Inc DQS Phaser_Out Stage2 Fine Delay line\n WL_FINE_INC: begin\n wl_edge_detect_valid_r <= #TCQ 1'b0;\n if (SIM_CAL_OPTION == \"FAST_CAL\") begin\n wl_state_r <= #TCQ WL_FINE_INC_WAIT;\n if (fast_cal_fine_cnt > 'd0)\n fast_cal_fine_cnt <= #TCQ fast_cal_fine_cnt - 1;\n else\n fast_cal_fine_cnt <= #TCQ fast_cal_fine_cnt;\n end else if (wr_level_done_r5) begin\n wl_tap_count_r <= #TCQ 'd0;\n wl_state_r <= #TCQ WL_FINE_INC_WAIT;\n if (|fine_inc[dqs_count_w])\n fine_inc[dqs_count_w] <= #TCQ fine_inc[dqs_count_w] - 1;\n end else begin\n wl_state_r <= #TCQ WL_WAIT;\n wl_tap_count_r <= #TCQ wl_tap_count_r + 1'b1;\n end\n end\n \n WL_FINE_INC_WAIT: begin\n if (SIM_CAL_OPTION == \"FAST_CAL\") begin\n if (fast_cal_fine_cnt > 'd0)\n wl_state_r <= #TCQ WL_FINE_INC;\n else if (fast_cal_coarse_cnt > 'd0)\n wl_state_r <= #TCQ WL_CORSE_INC;\n else\n wl_state_r <= #TCQ WL_DQS_CNT;\n end else if (|fine_inc[dqs_count_w])\n wl_state_r <= #TCQ WL_FINE_INC;\n else if (dqs_count_r == (DQS_WIDTH-1))\n wl_state_r <= #TCQ WL_IDLE;\n else begin\n wl_state_r <= #TCQ WL_2RANK_FINAL_TAP;\n dqs_count_r <= #TCQ dqs_count_r + 1;\n end\n end\n \n WL_FINE_DEC: begin\n wl_edge_detect_valid_r <= #TCQ 1'b0;\n wl_tap_count_r <= #TCQ 'd0;\n wl_state_r <= #TCQ WL_FINE_DEC_WAIT1;\n if (fine_dec_cnt > 6'd0)\n fine_dec_cnt <= #TCQ fine_dec_cnt - 1;\n else\n fine_dec_cnt <= #TCQ fine_dec_cnt;\n end\n \n WL_FINE_DEC_WAIT1: begin\n if (incdec_wait_cnt == 'd8)\n wl_state_r <= #TCQ WL_FINE_DEC_WAIT;\n end\n \n WL_FINE_DEC_WAIT: begin\n if (fine_dec_cnt > 6'd0)\n wl_state_r <= #TCQ WL_FINE_DEC;\n //else if (zero_tran_r)\n // wl_state_r <= #TCQ WL_DQS_CNT;\n else if (dual_rnk_dec) begin \n if (|corse_dec[dqs_count_r])\n wl_state_r <= #TCQ WL_CORSE_DEC;\n else\n wl_state_r <= #TCQ WL_2RANK_DQS_CNT;\n end else if (wrlvl_byte_redo) begin\n if ((corse_cnt[dqs_count_w] + wrlvl_redo_corse_inc) <= 'd7)\n wl_state_r <= #TCQ WL_CORSE_INC;\n else begin\n wl_state_r <= #TCQ WL_IDLE;\n wrlvl_err <= #TCQ 1'b1;\n end\n end else\n wl_state_r <= #TCQ WL_CORSE_INC;\n end\n \n WL_CORSE_DEC: begin\n wl_state_r <= #TCQ WL_CORSE_DEC_WAIT;\n dual_rnk_dec <= #TCQ 1'b0;\n if (|corse_dec[dqs_count_r])\n corse_dec[dqs_count_r] <= #TCQ corse_dec[dqs_count_r] - 1;\n else\n corse_dec[dqs_count_r] <= #TCQ corse_dec[dqs_count_r];\n end\n \n WL_CORSE_DEC_WAIT: begin\n if (wl_sm_start) begin\n //if (|corse_dec[dqs_count_r])\n // wl_state_r <= #TCQ WL_CORSE_DEC;\n if (|corse_dec[dqs_count_r])\n wl_state_r <= #TCQ WL_CORSE_DEC_WAIT1;\n else\n wl_state_r <= #TCQ WL_2RANK_DQS_CNT;\n end\n end\n \n WL_CORSE_DEC_WAIT1: begin\n if (wl_sm_start)\n wl_state_r <= #TCQ WL_CORSE_DEC;\n end\n \n WL_CORSE_INC: begin\n wl_state_r <= #TCQ WL_CORSE_INC_WAIT_TMP;\n if (SIM_CAL_OPTION == \"FAST_CAL\") begin\n if (fast_cal_coarse_cnt > 'd0)\n fast_cal_coarse_cnt <= #TCQ fast_cal_coarse_cnt - 1;\n else\n fast_cal_coarse_cnt <= #TCQ fast_cal_coarse_cnt;\n end else if (wrlvl_byte_redo) begin\n corse_cnt[dqs_count_w] <= #TCQ corse_cnt[dqs_count_w] + 1;\n if (|wrlvl_redo_corse_inc) \n wrlvl_redo_corse_inc <= #TCQ wrlvl_redo_corse_inc - 1;\n end else if (~wr_level_done_r5)\n corse_cnt[dqs_count_r] <= #TCQ corse_cnt[dqs_count_r] + 1;\n else if (|corse_inc[dqs_count_w]) \n corse_inc[dqs_count_w] <= #TCQ corse_inc[dqs_count_w] - 1;\n end\n\n WL_CORSE_INC_WAIT_TMP: begin\n if (incdec_wait_cnt == 'd8)\n wl_state_r <= #TCQ WL_CORSE_INC_WAIT;\n end\n \n WL_CORSE_INC_WAIT: begin\n if (SIM_CAL_OPTION == \"FAST_CAL\") begin\n if (fast_cal_coarse_cnt > 'd0)\n wl_state_r <= #TCQ WL_CORSE_INC;\n else\n wl_state_r <= #TCQ WL_DQS_CNT;\n end else if (wrlvl_byte_redo) begin\n if (|wrlvl_redo_corse_inc)\n wl_state_r <= #TCQ WL_CORSE_INC;\n else begin\n wl_state_r <= #TCQ WL_INIT_FINE_INC;\n inhibit_edge_detect_r <= #TCQ 1'b1;\n end\n end else if (~wr_level_done_r5 && wl_sm_start)\n wl_state_r <= #TCQ WL_CORSE_INC_WAIT1;\n else if (wr_level_done_r5) begin\n if (|corse_inc[dqs_count_r])\n wl_state_r <= #TCQ WL_CORSE_INC;\n else if (|fine_inc[dqs_count_w]) \n wl_state_r <= #TCQ WL_FINE_INC;\n else if (dqs_count_r == (DQS_WIDTH-1))\n wl_state_r <= #TCQ WL_IDLE;\n else begin\n wl_state_r <= #TCQ WL_2RANK_FINAL_TAP;\n dqs_count_r <= #TCQ dqs_count_r + 1;\n end\n end\n end\n \n WL_CORSE_INC_WAIT1: begin\n if (wl_sm_start)\n wl_state_r <= #TCQ WL_CORSE_INC_WAIT2;\n end\n\n WL_CORSE_INC_WAIT2: begin\n if (wl_sm_start)\n wl_state_r <= #TCQ WL_WAIT;\n end\n \n WL_WAIT: begin\n if (wl_sm_start)\n wl_state_r <= #TCQ WL_EDGE_CHECK;\n end\n \n WL_EDGE_CHECK: begin // Look for the edge\n if (wl_edge_detect_valid_r == 1'b0) begin\n wl_state_r <= #TCQ WL_WAIT;\n wl_edge_detect_valid_r <= #TCQ 1'b1;\n end\n // 0->1 transition detected with DQS\n else if(rd_data_edge_detect_r[dqs_count_r] &&\n wl_edge_detect_valid_r)\n begin\n wl_tap_count_r <= #TCQ wl_tap_count_r;\n if ((SIM_CAL_OPTION == \"FAST_CAL\") || (RANKS < 2) ||\n ~oclkdelay_calib_done)\n wl_state_r <= #TCQ WL_DQS_CNT;\n else\n wl_state_r <= #TCQ WL_2RANK_TAP_DEC;\n end\n // For initial writes check only upto 56 taps. Reserving the \n // remaining taps for OCLK calibration. \n else if((~wrlvl_tap_done_r) && (wl_tap_count_r > 6'd55)) begin\n if (corse_cnt[dqs_count_r] < COARSE_TAPS) begin\n wl_state_r <= #TCQ WL_FINE_DEC;\n fine_dec_cnt <= #TCQ wl_tap_count_r;\n end else begin\n wrlvl_err <= #TCQ 1'b1;\n wl_state_r <= #TCQ WL_IDLE;\n end\n\t end else begin\n\t if (wl_tap_count_r < 6'd56) //for reuse wrlvl for complex ocal\t \n wl_state_r <= #TCQ WL_FINE_INC;\n\t else if (corse_cnt[dqs_count_r] < COARSE_TAPS) begin\n wl_state_r <= #TCQ WL_FINE_DEC;\n fine_dec_cnt <= #TCQ wl_tap_count_r;\n end else begin\n wrlvl_err <= #TCQ 1'b1;\n wl_state_r <= #TCQ WL_IDLE;\n end\n\t end\n end\n\n WL_2RANK_TAP_DEC: begin\n wl_state_r <= #TCQ WL_FINE_DEC;\n fine_dec_cnt <= #TCQ wl_tap_count_r;\n for (m = 0; m < DQS_WIDTH; m = m + 1)\n corse_dec[m] <= #TCQ corse_cnt[m];\n wl_edge_detect_valid_r <= #TCQ 1'b0;\n dual_rnk_dec <= #TCQ 1'b1;\n end\n \n WL_DQS_CNT: begin\n if ((SIM_CAL_OPTION == \"FAST_CAL\") ||\n (dqs_count_r == (DQS_WIDTH-1)) ||\n wrlvl_byte_redo) begin\n dqs_count_r <= #TCQ dqs_count_r;\n dq_cnt_inc <= #TCQ 1'b0;\n end else begin\n dqs_count_r <= #TCQ dqs_count_r + 1'b1;\n dq_cnt_inc <= #TCQ 1'b1;\n end\n wl_state_r <= #TCQ WL_DQS_CHECK;\n wl_edge_detect_valid_r <= #TCQ 1'b0;\n end\n \n WL_2RANK_DQS_CNT: begin\n if ((SIM_CAL_OPTION == \"FAST_CAL\") ||\n (dqs_count_r == (DQS_WIDTH-1))) begin\n dqs_count_r <= #TCQ dqs_count_r;\n dq_cnt_inc <= #TCQ 1'b0;\n end else begin\n dqs_count_r <= #TCQ dqs_count_r + 1'b1;\n dq_cnt_inc <= #TCQ 1'b1;\n end\n wl_state_r <= #TCQ WL_DQS_CHECK;\n wl_edge_detect_valid_r <= #TCQ 1'b0;\n dual_rnk_dec <= #TCQ 1'b0;\n end \n \n WL_DQS_CHECK: begin // check if all DQS have been calibrated\n wl_tap_count_r <= #TCQ 'd0;\n if (dq_cnt_inc == 1'b0)begin\n wrlvl_rank_done_r <= #TCQ 1'd1;\n for (t = 0; t < DQS_WIDTH; t = t + 1)\n corse_cnt[t] <= #TCQ 3'b0;\n if ((SIM_CAL_OPTION == \"FAST_CAL\") || (RANKS < 2) || ~oclkdelay_calib_done) begin\n wl_state_r <= #TCQ WL_IDLE;\n if (wrlvl_byte_redo)\n dqs_count_r <= #TCQ dqs_count_r;\n else \n dqs_count_r <= #TCQ 'd0;\n end else if (rank_cnt_r == RANKS-1) begin\n dqs_count_r <= #TCQ dqs_count_r;\n if (RANKS > 1)\n wl_state_r <= #TCQ WL_2RANK_FINAL_TAP;\n else\n wl_state_r <= #TCQ WL_IDLE;\n end else begin\n wl_state_r <= #TCQ WL_INIT;\n dqs_count_r <= #TCQ 'd0;\n end\n if ((SIM_CAL_OPTION == \"FAST_CAL\") ||\n (rank_cnt_r == RANKS-1)) begin\n wr_level_done_r <= #TCQ 1'd1;\n rank_cnt_r <= #TCQ 2'b00;\n end else begin\n wr_level_done_r <= #TCQ 1'd0;\n rank_cnt_r <= #TCQ rank_cnt_r + 1'b1;\n end\n end else\n wl_state_r <= #TCQ WL_INIT;\n end\n \n WL_2RANK_FINAL_TAP: begin\n if (wr_level_done_r4 && ~wr_level_done_r5) begin\n for(u = 0; u < DQS_WIDTH; u = u + 1) begin\n corse_inc[u] <= #TCQ final_coarse_tap[u];\n fine_inc[u] <= #TCQ final_val[u];\n end\n dqs_count_r <= #TCQ 'd0;\n end else if (wr_level_done_r5) begin\n if (|corse_inc[dqs_count_r])\n wl_state_r <= #TCQ WL_CORSE_INC;\n else if (|fine_inc[dqs_count_w])\n wl_state_r <= #TCQ WL_FINE_INC;\n end \n end\n endcase\n end\n end // always @ (posedge clk)\n\nendmodule\n \n \n \n \n \n\n \n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_wrlvl_off_delay.v", "content": "//*****************************************************************************\n// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor: Xilinx\n// \\ \\ \\/ Version: %version\n// \\ \\ Application: MIG\n// / / Filename: ddr_phy_ck_addr_cmd_delay.v\n// /___/ /\\ Date Last Modified: $Date: 2011/02/25 02:07:40 $\n// \\ \\ / \\ Date Created: Aug 03 2009\n// \\___\\/\\___\\\n//\n//Device: 7 Series\n//Design Name: DDR3 SDRAM\n//Purpose: Module to decrement initial PO delay to 0 and add 1/4 tck for tdqss\n//Reference:\n//Revision History:\n//*****************************************************************************\n\n`timescale 1ps/1ps\n\nmodule mig_7series_v4_0_ddr_phy_wrlvl_off_delay #\n (\n parameter TCQ = 100,\n parameter tCK = 3636,\n parameter nCK_PER_CLK = 2,\n parameter CLK_PERIOD = 4,\n parameter PO_INITIAL_DLY= 46,\n parameter DQS_CNT_WIDTH = 3,\n parameter DQS_WIDTH = 8,\n parameter N_CTL_LANES = 3\n )\n (\n input clk,\n input rst,\n input pi_fine_dly_dec_done,\n input cmd_delay_start,\n // Control lane being shifted using Phaser_Out fine delay taps\n output reg [DQS_CNT_WIDTH:0] ctl_lane_cnt,\n // Inc/dec Phaser_Out fine delay line\n output reg po_s2_incdec_f,\n output reg po_en_s2_f,\n // Inc/dec Phaser_Out coarse delay line\n output reg po_s2_incdec_c,\n output reg po_en_s2_c,\n // Completed adjusting delays for dq, dqs for tdqss\n output po_ck_addr_cmd_delay_done,\n // completed decrementing initialPO delays\n output po_dec_done,\n output phy_ctl_rdy_dly\n );\n\n\n localparam TAP_LIMIT = 63;\n\n\n\n// PO fine delay tap resolution change by frequency. tCK > 2500, need\n// twice the amount of taps\n// localparam D_DLY_F = (tCK > 2500 ) ? D_DLY * 2 : D_DLY;\n\n // coarse delay tap is added DQ/DQS to meet the TDQSS specification.\n //localparam TDQSS_DLY = (tCK > 2500 )? 2: 1;\n localparam TDQSS_DLY = 2; // DIV2 change\n\n reg delay_done;\n reg delay_done_r1;\n reg delay_done_r2;\n reg delay_done_r3;\n reg delay_done_r4;\n reg [5:0] po_delay_cnt_r;\n reg po_cnt_inc;\n reg cmd_delay_start_r1;\n reg cmd_delay_start_r2;\n reg cmd_delay_start_r3;\n reg cmd_delay_start_r4;\n reg cmd_delay_start_r5;\n reg cmd_delay_start_r6;\n reg po_delay_done;\n reg po_delay_done_r1;\n reg po_delay_done_r2;\n reg po_delay_done_r3;\n reg po_delay_done_r4;\n reg pi_fine_dly_dec_done_r;\n reg po_en_stg2_c;\n reg po_en_stg2_f;\n reg po_stg2_incdec_c;\n reg po_stg2_f_incdec;\n reg [DQS_CNT_WIDTH:0] lane_cnt_dqs_c_r;\n reg [DQS_CNT_WIDTH:0] lane_cnt_po_r;\n reg [5:0] delay_cnt_r;\n\n always @(posedge clk) begin\n cmd_delay_start_r1 <= #TCQ cmd_delay_start;\n cmd_delay_start_r2 <= #TCQ cmd_delay_start_r1;\n cmd_delay_start_r3 <= #TCQ cmd_delay_start_r2;\n cmd_delay_start_r4 <= #TCQ cmd_delay_start_r3;\n cmd_delay_start_r5 <= #TCQ cmd_delay_start_r4;\n cmd_delay_start_r6 <= #TCQ cmd_delay_start_r5;\n pi_fine_dly_dec_done_r <= #TCQ pi_fine_dly_dec_done;\n end\n\n assign phy_ctl_rdy_dly = cmd_delay_start_r6;\n\n\n // logic for decrementing initial fine delay taps for all PO\n // Decrement done for add, ctrl and data phaser outs\n\n assign po_dec_done = (PO_INITIAL_DLY == 0) ? 1 : po_delay_done_r4;\n\n\n always @(posedge clk)\n if (rst || ~cmd_delay_start_r6 || po_delay_done) begin\n po_stg2_f_incdec <= #TCQ 1'b0;\n po_en_stg2_f <= #TCQ 1'b0;\n end else if (po_delay_cnt_r > 6'd0) begin\n po_en_stg2_f <= #TCQ ~po_en_stg2_f;\n end\n\n always @(posedge clk)\n if (rst || ~cmd_delay_start_r6 || (po_delay_cnt_r == 6'd0))\n // set all the PO delays to 31. Decrement from 46 to 31.\n // Requirement comes from dqs_found logic\n po_delay_cnt_r <= #TCQ (PO_INITIAL_DLY - 31);\n else if ( po_en_stg2_f && (po_delay_cnt_r > 6'd0))\n po_delay_cnt_r <= #TCQ po_delay_cnt_r - 1;\n\n always @(posedge clk)\n if (rst)\n lane_cnt_po_r <= #TCQ 'd0;\n else if ( po_en_stg2_f && (po_delay_cnt_r == 6'd1))\n lane_cnt_po_r <= #TCQ lane_cnt_po_r + 1;\n\n always @(posedge clk)\n if (rst || ~cmd_delay_start_r6 )\n po_delay_done <= #TCQ 1'b0;\n else if ((po_delay_cnt_r == 6'd1) && (lane_cnt_po_r ==1'b0))\n po_delay_done <= #TCQ 1'b1;\n\n always @(posedge clk) begin\n po_delay_done_r1 <= #TCQ po_delay_done;\n po_delay_done_r2 <= #TCQ po_delay_done_r1;\n po_delay_done_r3 <= #TCQ po_delay_done_r2;\n po_delay_done_r4 <= #TCQ po_delay_done_r3;\n end\n\n // logic to select between all PO delays and data path delay.\n always @(posedge clk) begin\n po_s2_incdec_f <= #TCQ po_stg2_f_incdec;\n po_en_s2_f <= #TCQ po_en_stg2_f;\n end\n\n// Logic to add 1/4 taps amount of delay to data path for tdqss.\n// After all the initial PO delays are decremented the 1/4 delay will\n// be added. Coarse delay taps will be added here .\n// Delay added only to data path\n\n assign po_ck_addr_cmd_delay_done = (TDQSS_DLY == 0) ? pi_fine_dly_dec_done_r\n : delay_done_r4;\n\n always @(posedge clk)\n if (rst || ~pi_fine_dly_dec_done_r || delay_done) begin\n po_stg2_incdec_c <= #TCQ 1'b1;\n po_en_stg2_c <= #TCQ 1'b0;\n end else if (delay_cnt_r > 6'd0) begin\n po_en_stg2_c <= #TCQ ~po_en_stg2_c;\n end\n\n always @(posedge clk)\n if (rst || ~pi_fine_dly_dec_done_r || (delay_cnt_r == 6'd0))\n delay_cnt_r <= #TCQ TDQSS_DLY;\n else if ( po_en_stg2_c && (delay_cnt_r > 6'd0))\n delay_cnt_r <= #TCQ delay_cnt_r - 1;\n\n always @(posedge clk)\n if (rst)\n lane_cnt_dqs_c_r <= #TCQ 'd0;\n else if ( po_en_stg2_c && (delay_cnt_r == 6'd1))\n lane_cnt_dqs_c_r <= #TCQ lane_cnt_dqs_c_r + 1;\n\n always @(posedge clk)\n if (rst || ~pi_fine_dly_dec_done_r)\n delay_done <= #TCQ 1'b0;\n else if ((delay_cnt_r == 6'd1) && (lane_cnt_dqs_c_r == 1'b0))\n delay_done <= #TCQ 1'b1;\n\n\n always @(posedge clk) begin\n delay_done_r1 <= #TCQ delay_done;\n delay_done_r2 <= #TCQ delay_done_r1;\n delay_done_r3 <= #TCQ delay_done_r2;\n delay_done_r4 <= #TCQ delay_done_r3;\n end\n\n always @(posedge clk) begin\n po_s2_incdec_c <= #TCQ po_stg2_incdec_c;\n po_en_s2_c <= #TCQ po_en_stg2_c;\n ctl_lane_cnt <= #TCQ lane_cnt_dqs_c_r;\n end\n\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_prbs_gen.v", "content": "//*****************************************************************************\r\n// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.\r\n//\r\n// This file contains confidential and proprietary information\r\n// of Xilinx, Inc. and is protected under U.S. and\r\n// international copyright and other intellectual property\r\n// laws.\r\n//\r\n// DISCLAIMER\r\n// This disclaimer is not a license and does not grant any\r\n// rights to the materials distributed herewith. Except as\r\n// otherwise provided in a valid license issued to you by\r\n// Xilinx, and to the maximum extent permitted by applicable\r\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\r\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r\n// (2) Xilinx shall not be liable (whether in contract or tort,\r\n// including negligence, or under any other theory of\r\n// liability) for any loss or damage of any kind or nature\r\n// related to, arising under or in connection with these\r\n// materials, including for any direct, or any indirect,\r\n// special, incidental, or consequential loss or damage\r\n// (including loss of data, profits, goodwill, or any type of\r\n// loss or damage suffered as a result of any action brought\r\n// by a third party) even if such damage or loss was\r\n// reasonably foreseeable or Xilinx had been advised of the\r\n// possibility of the same.\r\n//\r\n// CRITICAL APPLICATIONS\r\n// Xilinx products are not designed or intended to be fail-\r\n// safe, or for use in any application requiring fail-safe\r\n// performance, such as life-support or safety devices or\r\n// systems, Class III medical devices, nuclear facilities,\r\n// applications related to the deployment of airbags, or any\r\n// other applications that could lead to death, personal\r\n// injury, or severe property or environmental damage\r\n// (individually and collectively, \"Critical\r\n// Applications\"). Customer assumes the sole risk and\r\n// liability of any use of Xilinx products in Critical\r\n// Applications, subject only to applicable laws and\r\n// regulations governing limitations on product liability.\r\n//\r\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r\n// PART OF THIS FILE AT ALL TIMES.\r\n// \r\n//*****************************************************************************\r\n// ____ ____\r\n// / /\\/ /\r\n// /___/ \\ / Vendor: Xilinx\r\n// \\ \\ \\/ Version: %version\r\n// \\ \\ Application: MIG\r\n// / / Filename: ddr_prbs_gen.v\r\n// /___/ /\\ Date Last Modified: $Date: 2011/06/02 08:35:10 $\r\n// \\ \\ / \\ Date Created: 05/12/10\r\n// \\___\\/\\___\\\r\n//\r\n//Device: 7 Series\r\n//Design Name: ddr_prbs_gen\r\n// Overview:\r\n// Implements a \"pseudo-PRBS\" generator. Basically this is a standard\r\n// PRBS generator (using an linear feedback shift register) along with\r\n// logic to force the repetition of the sequence after 2^PRBS_WIDTH\r\n// samples (instead of 2^PRBS_WIDTH - 1). The LFSR is based on the design\r\n// from Table 1 of XAPP 210. Note that only 8- and 10-tap long LFSR chains\r\n// are supported in this code\r\n// Parameter Requirements:\r\n// 1. PRBS_WIDTH = 8 or 10\r\n// 2. PRBS_WIDTH >= 2*nCK_PER_CLK\r\n// Output notes:\r\n// The output of this module consists of 2*nCK_PER_CLK bits, these contain\r\n// the value of the LFSR output for the next 2*CK_PER_CLK bit times. Note\r\n// that prbs_o[0] contains the bit value for the \"earliest\" bit time. \r\n//\r\n//Reference:\r\n//Revision History:\r\n// \r\n//*****************************************************************************\r\n\r\n/******************************************************************************\r\n**$Id: ddr_prbs_gen.v,v 1.1 2011/06/02 08:35:10 mishra Exp $\r\n**$Date: 2011/06/02 08:35:10 $\r\n**$Author: mishra $\r\n**$Revision: 1.1 $\r\n**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_prbs_gen.v,v $\r\n******************************************************************************/\r\n\r\n\r\n`timescale 1ps/1ps\r\n\r\nmodule mig_7series_v4_0_ddr_prbs_gen #\r\n (\r\n parameter TCQ = 100, // clk->out delay (sim only)\r\n parameter PRBS_WIDTH = 64, // LFSR shift register length\r\n parameter DQS_CNT_WIDTH = 5,\r\n parameter DQ_WIDTH = 72,\r\n parameter VCCO_PAT_EN = 1,\r\n parameter VCCAUX_PAT_EN = 1,\r\n parameter ISI_PAT_EN = 1,\r\n parameter FIXED_VICTIM = \"TRUE\"\r\n )\r\n (\r\n input clk_i, // input clock\r\n input clk_en_i, // clock enable \r\n input rst_i, // synchronous reset\r\n input [PRBS_WIDTH-1:0] prbs_seed_i, // initial LFSR seed\r\n input phy_if_empty, // IN_FIFO empty flag\r\n input prbs_rdlvl_start, // PRBS read lveling start\r\n input prbs_rdlvl_done,\r\n input complex_wr_done,\r\n input [2:0] victim_sel,\r\n input [DQS_CNT_WIDTH:0] byte_cnt,\r\n //output [PRBS_WIDTH-1:0] prbs_o // generated pseudo random data\r\n output [8*DQ_WIDTH-1:0] prbs_o,\r\n output [9:0] dbg_prbs_gen,\r\n input reset_rd_addr,\r\n output prbs_ignore_first_byte,\r\n output prbs_ignore_last_bytes\r\n );\r\n\r\n //***************************************************************************\r\n\r\n function integer clogb2 (input integer size);\r\n begin\r\n size = size - 1;\r\n for (clogb2=1; size>1; clogb2=clogb2+1)\r\n size = size >> 1;\r\n end\r\n endfunction\r\n \r\n // Number of internal clock cycles before the PRBS sequence will repeat\r\n localparam PRBS_SEQ_LEN_CYCLES = 128;\r\n localparam PRBS_SEQ_LEN_CYCLES_BITS = clogb2(PRBS_SEQ_LEN_CYCLES);\r\n \r\n reg phy_if_empty_r;\r\n reg reseed_prbs_r;\r\n reg [PRBS_SEQ_LEN_CYCLES_BITS-1:0] sample_cnt_r;\r\n reg [PRBS_WIDTH - 1 :0] prbs; \r\n reg [PRBS_WIDTH :1] lfsr_q;\r\n \r\n\r\n //***************************************************************************\r\n always @(posedge clk_i) begin\r\n phy_if_empty_r <= #TCQ phy_if_empty;\r\n end\r\n\r\n //***************************************************************************\r\n // Generate PRBS reset signal to ensure that PRBS sequence repeats after\r\n // every 2**PRBS_WIDTH samples. Basically what happens is that we let the\r\n // LFSR run for an extra cycle after \"truly PRBS\" 2**PRBS_WIDTH - 1\r\n // samples have past. Once that extra cycle is finished, we reseed the LFSR\r\n always @(posedge clk_i)\r\n begin\r\n if (rst_i || ~clk_en_i) begin\r\n sample_cnt_r <= #TCQ 'b0;\r\n reseed_prbs_r <= #TCQ 1'b0;\r\n end else if (clk_en_i && (~phy_if_empty_r || ~prbs_rdlvl_start)) begin\r\n // The rollver count should always be [(power of 2) - 1]\r\n sample_cnt_r <= #TCQ sample_cnt_r + 1;\r\n // Assert PRBS reset signal so that it is simultaneously with the\r\n // last sample of the sequence\r\n if (sample_cnt_r == PRBS_SEQ_LEN_CYCLES - 2)\r\n reseed_prbs_r <= #TCQ 1'b1;\r\n else\r\n reseed_prbs_r <= #TCQ 1'b0;\r\n end\r\n end\r\n\r\n always @ (posedge clk_i)\r\n begin\r\n//reset it to a known good state to prevent it locks up\r\n if ((reseed_prbs_r && clk_en_i) || rst_i || ~clk_en_i) begin\r\n lfsr_q[4:1] <= #TCQ prbs_seed_i[3:0] | 4'h5;\r\n lfsr_q[PRBS_WIDTH:5] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4];\r\n end\r\n else if (clk_en_i && (~phy_if_empty_r || ~prbs_rdlvl_start)) begin\r\n lfsr_q[PRBS_WIDTH:31] <= #TCQ lfsr_q[PRBS_WIDTH-1:30];\r\n lfsr_q[30] <= #TCQ lfsr_q[16] ^ lfsr_q[13] ^ lfsr_q[5] ^ lfsr_q[1];\r\n lfsr_q[29:9] <= #TCQ lfsr_q[28:8];\r\n lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7];\r\n lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6];\r\n lfsr_q[6:4] <= #TCQ lfsr_q[5:3];\r\n lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2];\r\n lfsr_q[2] <= #TCQ lfsr_q[1] ;\r\n lfsr_q[1] <= #TCQ lfsr_q[32];\r\n end\r\n end\r\n \r\n always @ (lfsr_q[PRBS_WIDTH:1]) begin\r\n prbs = lfsr_q[PRBS_WIDTH:1];\r\n end\r\n \r\n//******************************************************************************\r\n// Complex pattern BRAM\r\n//******************************************************************************\r\n\r\nlocalparam BRAM_ADDR_WIDTH = 8;\r\nlocalparam BRAM_DATA_WIDTH = 18;\r\nlocalparam BRAM_DEPTH = 256;\r\n\r\ninteger i,j;\r\n(* RAM_STYLE = \"distributed\" *) reg [BRAM_ADDR_WIDTH - 1:0] rd_addr;\r\n//reg [BRAM_DATA_WIDTH - 1:0] mem[0:BRAM_DEPTH - 1]; \r\n(* RAM_STYLE = \"distributed\" *) reg [BRAM_DATA_WIDTH - 1:0] mem_out;\r\nreg [BRAM_DATA_WIDTH - 3:0] dout_o;\r\nreg [DQ_WIDTH-1:0] sel;\r\nreg [DQ_WIDTH-1:0] dout_rise0;\r\nreg [DQ_WIDTH-1:0] dout_fall0;\r\nreg [DQ_WIDTH-1:0] dout_rise1;\r\nreg [DQ_WIDTH-1:0] dout_fall1;\r\nreg [DQ_WIDTH-1:0] dout_rise2;\r\nreg [DQ_WIDTH-1:0] dout_fall2;\r\nreg [DQ_WIDTH-1:0] dout_rise3;\r\nreg [DQ_WIDTH-1:0] dout_fall3;\r\n\r\n// VCCO noise injection pattern with matching victim (reads with gaps)\r\n// content format\r\n// {aggressor pattern, victim pattern}\r\nalways @ (rd_addr) begin\r\n case (rd_addr)\r\n 8'd0 : mem_out = {2'b11, 8'b10101010,8'b10101010}; //1 read\r\n 8'd1 : mem_out = {2'b01, 8'b11001100,8'b11001100}; //2 reads\r\n 8'd2 : mem_out = {2'b10, 8'b11001100,8'b11001100}; //2 reads\r\n 8'd3 : mem_out = {2'b01, 8'b11100011,8'b11100011}; //3 reads\r\n 8'd4 : mem_out = {2'b00, 8'b10001110,8'b10001110}; //3 reads\r\n 8'd5 : mem_out = {2'b10, 8'b00111000,8'b00111000}; //3 reads\r\n 8'd6 : mem_out = {2'b01, 8'b11110000,8'b11110000}; //4 reads\r\n 8'd7 : mem_out = {2'b00, 8'b11110000,8'b11110000}; //4 reads\r\n 8'd8 : mem_out = {2'b00, 8'b11110000,8'b11110000}; //4 reads\r\n 8'd9 : mem_out = {2'b10, 8'b11110000,8'b11110000}; //4 reads\r\n 8'd10 : mem_out = {2'b01, 8'b11111000,8'b11111000}; //5 reads\r\n 8'd11 : mem_out = {2'b00, 8'b00111110,8'b00111110}; //5 reads\r\n 8'd12 : mem_out = {2'b00, 8'b00001111,8'b00001111}; //5 reads\r\n 8'd13 : mem_out = {2'b00, 8'b10000011,8'b10000011}; //5 reads\r\n 8'd14 : mem_out = {2'b10, 8'b11100000,8'b11100000}; //5 reads\r\n 8'd15 : mem_out = {2'b01, 8'b11111100,8'b11111100}; //6 reads\r\n 8'd16 : mem_out = {2'b00, 8'b00001111,8'b00001111}; //6 reads\r\n 8'd17 : mem_out = {2'b00, 8'b11000000,8'b11000000}; //6 reads\r\n 8'd18 : mem_out = {2'b00, 8'b11111100,8'b11111100}; //6 reads\r\n 8'd19 : mem_out = {2'b00, 8'b00001111,8'b00001111}; //6 reads\r\n 8'd20 : mem_out = {2'b10, 8'b11000000,8'b11000000}; //6 reads\r\n // VCCO noise injection pattern with non-matching victim (reads with gaps)\r\n // content format\r\n // {aggressor pattern, victim pattern}\r\n 8'd21 : mem_out = {2'b11, 8'b10101010,8'b01010101}; //1 read\r\n 8'd22 : mem_out = {2'b01, 8'b11001100,8'b00110011}; //2 reads\r\n 8'd23 : mem_out = {2'b10, 8'b11001100,8'b00110011}; //2 reads\r\n 8'd24 : mem_out = {2'b01, 8'b11100011,8'b00011100}; //3 reads\r\n 8'd25 : mem_out = {2'b00, 8'b10001110,8'b01110001}; //3 reads\r\n 8'd26 : mem_out = {2'b10, 8'b00111000,8'b11000111}; //3 reads\r\n 8'd27 : mem_out = {2'b01, 8'b11110000,8'b00001111}; //4 reads\r\n 8'd28 : mem_out = {2'b00, 8'b11110000,8'b00001111}; //4 reads\r\n 8'd29 : mem_out = {2'b00, 8'b11110000,8'b00001111}; //4 reads\r\n 8'd30 : mem_out = {2'b10, 8'b11110000,8'b00001111}; //4 reads\r\n 8'd31 : mem_out = {2'b01, 8'b11111000,8'b00000111}; //5 reads\r\n 8'd32 : mem_out = {2'b00, 8'b00111110,8'b11000001}; //5 reads\r\n 8'd33 : mem_out = {2'b00, 8'b00001111,8'b11110000}; //5 reads\r\n 8'd34 : mem_out = {2'b00, 8'b10000011,8'b01111100}; //5 reads\r\n 8'd35 : mem_out = {2'b10, 8'b11100000,8'b00011111}; //5 reads\r\n 8'd36 : mem_out = {2'b01, 8'b11111100,8'b00000011}; //6 reads\r\n 8'd37 : mem_out = {2'b00, 8'b00001111,8'b11110000}; //6 reads\r\n 8'd38 : mem_out = {2'b00, 8'b11000000,8'b00111111}; //6 reads\r\n 8'd39 : mem_out = {2'b00, 8'b11111100,8'b00000011}; //6 reads\r\n 8'd40 : mem_out = {2'b00, 8'b00001111,8'b11110000}; //6 reads\r\n 8'd41 : mem_out = {2'b10, 8'b11000000,8'b00111111}; //6 reads\r\n // VCCAUX noise injection pattern with ISI pattern on victim (reads with gaps)\r\n // content format\r\n // {aggressor pattern, victim pattern}\r\n 8'd42 : mem_out = {2'b01, 8'b10110100,8'b01010111}; //3 reads\r\n 8'd43 : mem_out = {2'b00, 8'b10110100,8'b01101111}; //3 reads\r\n 8'd44 : mem_out = {2'b10, 8'b10110100,8'b11000000}; //3 reads\r\n 8'd45 : mem_out = {2'b01, 8'b10100010,8'b10000100}; //4 reads\r\n 8'd46 : mem_out = {2'b00, 8'b10001010,8'b00110001}; //4 reads\r\n 8'd47 : mem_out = {2'b00, 8'b00101000,8'b01000111}; //4 reads\r\n 8'd48 : mem_out = {2'b10, 8'b10100010,8'b00100101}; //4 reads\r\n 8'd49 : mem_out = {2'b01, 8'b10101111,8'b10011010}; //5 reads\r\n 8'd50 : mem_out = {2'b00, 8'b01010000,8'b01111010}; //5 reads\r\n 8'd51 : mem_out = {2'b00, 8'b10101111,8'b10010101}; //5 reads\r\n 8'd52 : mem_out = {2'b00, 8'b01010000,8'b11011011}; //5 reads\r\n 8'd53 : mem_out = {2'b10, 8'b10101111,8'b11110000}; //5 reads\r\n 8'd54 : mem_out = {2'b01, 8'b10101000,8'b00100001}; //7 reads\r\n 8'd55 : mem_out = {2'b00, 8'b00101010,8'b10001010}; //7 reads\r\n 8'd56 : mem_out = {2'b00, 8'b00001010,8'b00100101}; //7 reads\r\n 8'd57 : mem_out = {2'b00, 8'b10000010,8'b10011010}; //7 reads\r\n 8'd58 : mem_out = {2'b00, 8'b10100000,8'b01111010}; //7 reads\r\n 8'd59 : mem_out = {2'b00, 8'b10101000,8'b10111111}; //7 reads\r\n 8'd60 : mem_out = {2'b10, 8'b00101010,8'b01010111}; //7 reads\r\n 8'd61 : mem_out = {2'b01, 8'b10101011,8'b01101111}; //8 reads\r\n 8'd62 : mem_out = {2'b00, 8'b11110101,8'b11000000}; //8 reads\r\n 8'd63 : mem_out = {2'b00, 8'b01000000,8'b10000100}; //8 reads\r\n 8'd64 : mem_out = {2'b00, 8'b10101011,8'b00110001}; //8 reads\r\n 8'd65 : mem_out = {2'b00, 8'b11110101,8'b01000111}; //8 reads\r\n 8'd66 : mem_out = {2'b00, 8'b01000000,8'b00100101}; //8 reads\r\n 8'd67 : mem_out = {2'b00, 8'b10101011,8'b10011010}; //8 reads\r\n 8'd68 : mem_out = {2'b10, 8'b11110101,8'b01111010}; //8 reads\r\n 8'd69 : mem_out = {2'b01, 8'b10101010,8'b10010101}; //9 reads\r\n 8'd70 : mem_out = {2'b00, 8'b00000010,8'b11011011}; //9 reads\r\n 8'd71 : mem_out = {2'b00, 8'b10101000,8'b11110000}; //9 reads\r\n 8'd72 : mem_out = {2'b00, 8'b00001010,8'b00100001}; //9 reads\r\n 8'd73 : mem_out = {2'b00, 8'b10100000,8'b10001010}; //9 reads\r\n 8'd74 : mem_out = {2'b00, 8'b00101010,8'b00100101}; //9 reads\r\n 8'd75 : mem_out = {2'b00, 8'b10000000,8'b10011010}; //9 reads\r\n 8'd76 : mem_out = {2'b00, 8'b10101010,8'b01111010}; //9 reads\r\n 8'd77 : mem_out = {2'b10, 8'b00000010,8'b10111111}; //9 reads\r\n 8'd78 : mem_out = {2'b01, 8'b10101010,8'b01010111}; //10 reads\r\n 8'd79 : mem_out = {2'b00, 8'b11111111,8'b01101111}; //10 reads\r\n 8'd80 : mem_out = {2'b00, 8'b01010101,8'b11000000}; //10 reads\r\n 8'd81 : mem_out = {2'b00, 8'b00000000,8'b10000100}; //10 reads\r\n 8'd82 : mem_out = {2'b00, 8'b10101010,8'b00110001}; //10 reads\r\n 8'd83 : mem_out = {2'b00, 8'b11111111,8'b01000111}; //10 reads\r\n 8'd84 : mem_out = {2'b00, 8'b01010101,8'b00100101}; //10 reads\r\n 8'd85 : mem_out = {2'b00, 8'b00000000,8'b10011010}; //10 reads\r\n 8'd86 : mem_out = {2'b00, 8'b10101010,8'b01111010}; //10 reads\r\n 8'd87 : mem_out = {2'b10, 8'b11111111,8'b10010101}; //10 reads\r\n 8'd88 : mem_out = {2'b01, 8'b10101010,8'b11011011}; //12 reads\r\n 8'd89 : mem_out = {2'b00, 8'b10000000,8'b11110000}; //12 reads\r\n 8'd90 : mem_out = {2'b00, 8'b00101010,8'b00100001}; //12 reads\r\n 8'd91 : mem_out = {2'b00, 8'b10100000,8'b10001010}; //12 reads\r\n 8'd92 : mem_out = {2'b00, 8'b00001010,8'b00100101}; //12 reads\r\n 8'd93 : mem_out = {2'b00, 8'b10101000,8'b10011010}; //12 reads\r\n 8'd94 : mem_out = {2'b00, 8'b00000010,8'b01111010}; //12 reads\r\n 8'd95 : mem_out = {2'b00, 8'b10101010,8'b10111111}; //12 reads\r\n 8'd96 : mem_out = {2'b00, 8'b00000000,8'b01010111}; //12 reads\r\n 8'd97 : mem_out = {2'b00, 8'b10101010,8'b01101111}; //12 reads\r\n 8'd98 : mem_out = {2'b00, 8'b10000000,8'b11000000}; //12 reads\r\n 8'd99 : mem_out = {2'b10, 8'b00101010,8'b10000100}; //12 reads\r\n 8'd100 : mem_out = {2'b01, 8'b10101010,8'b00110001}; //13 reads\r\n 8'd101 : mem_out = {2'b00, 8'b10111111,8'b01000111}; //13 reads\r\n 8'd102 : mem_out = {2'b00, 8'b11110101,8'b00100101}; //13 reads\r\n 8'd103 : mem_out = {2'b00, 8'b01010100,8'b10011010}; //13 reads\r\n 8'd104 : mem_out = {2'b00, 8'b00000000,8'b01111010}; //13 reads\r\n 8'd105 : mem_out = {2'b00, 8'b10101010,8'b10010101}; //13 reads\r\n 8'd106 : mem_out = {2'b00, 8'b10111111,8'b11011011}; //13 reads\r\n 8'd107 : mem_out = {2'b00, 8'b11110101,8'b11110000}; //13 reads\r\n 8'd108 : mem_out = {2'b00, 8'b01010100,8'b00100001}; //13 reads\r\n 8'd109 : mem_out = {2'b00, 8'b00000000,8'b10001010}; //13 reads\r\n 8'd110 : mem_out = {2'b00, 8'b10101010,8'b00100101}; //13 reads\r\n 8'd111 : mem_out = {2'b00, 8'b10111111,8'b10011010}; //13 reads\r\n 8'd112 : mem_out = {2'b10, 8'b11110101,8'b01111010}; //13 reads\r\n 8'd113 : mem_out = {2'b01, 8'b10101010,8'b10111111}; //14 reads\r\n 8'd114 : mem_out = {2'b00, 8'b10100000,8'b01010111}; //14 reads\r\n 8'd115 : mem_out = {2'b00, 8'b00000010,8'b01101111}; //14 reads\r\n 8'd116 : mem_out = {2'b00, 8'b10101010,8'b11000000}; //14 reads\r\n 8'd117 : mem_out = {2'b00, 8'b10000000,8'b10000100}; //14 reads\r\n 8'd118 : mem_out = {2'b00, 8'b00001010,8'b00110001}; //14 reads\r\n 8'd119 : mem_out = {2'b00, 8'b10101010,8'b01000111}; //14 reads\r\n 8'd120 : mem_out = {2'b00, 8'b00000000,8'b00100101}; //14 reads\r\n 8'd121 : mem_out = {2'b00, 8'b00101010,8'b10011010}; //14 reads\r\n 8'd122 : mem_out = {2'b00, 8'b10101000,8'b01111010}; //14 reads\r\n 8'd123 : mem_out = {2'b00, 8'b00000000,8'b10010101}; //14 reads\r\n 8'd124 : mem_out = {2'b00, 8'b10101010,8'b11011011}; //14 reads\r\n 8'd125 : mem_out = {2'b00, 8'b10100000,8'b11110000}; //14 reads\r\n 8'd126 : mem_out = {2'b10, 8'b00000010,8'b00100001}; //14 reads\r\n // ISI pattern (Back-to-back reads)\r\n // content format\r\n // {aggressor pattern, victim pattern}\r\n 8'd127 : mem_out = {2'b01, 8'b01010111,8'b01010111};\r\n 8'd128 : mem_out = {2'b00, 8'b01101111,8'b01101111};\r\n 8'd129 : mem_out = {2'b00, 8'b11000000,8'b11000000};\r\n 8'd130 : mem_out = {2'b00, 8'b10000110,8'b10000100};\r\n 8'd131 : mem_out = {2'b00, 8'b00101000,8'b00110001};\r\n 8'd132 : mem_out = {2'b00, 8'b11100100,8'b01000111};\r\n 8'd133 : mem_out = {2'b00, 8'b10110011,8'b00100101};\r\n 8'd134 : mem_out = {2'b00, 8'b01001111,8'b10011011};\r\n 8'd135 : mem_out = {2'b00, 8'b10110101,8'b01010101};\r\n 8'd136 : mem_out = {2'b00, 8'b10110101,8'b01010101};\r\n 8'd137 : mem_out = {2'b00, 8'b10000111,8'b10011000};\r\n 8'd138 : mem_out = {2'b00, 8'b11100011,8'b00011100};\r\n 8'd139 : mem_out = {2'b00, 8'b00001010,8'b11110101};\r\n 8'd140 : mem_out = {2'b00, 8'b11010100,8'b00101011};\r\n 8'd141 : mem_out = {2'b00, 8'b01001000,8'b10110111};\r\n 8'd142 : mem_out = {2'b00, 8'b00011111,8'b11100000};\r\n 8'd143 : mem_out = {2'b00, 8'b10111100,8'b01000011};\r\n 8'd144 : mem_out = {2'b00, 8'b10001111,8'b00010100};\r\n 8'd145 : mem_out = {2'b00, 8'b10110100,8'b01001011};\r\n 8'd146 : mem_out = {2'b00, 8'b11001011,8'b00110100};\r\n 8'd147 : mem_out = {2'b00, 8'b00001010,8'b11110101};\r\n 8'd148 : mem_out = {2'b00, 8'b10000000,8'b00000000};\r\n //Additional for ISI \r\n 8'd149 : mem_out = {2'b00, 8'b00000000,8'b00000000};\r\n 8'd150 : mem_out = {2'b00, 8'b01010101,8'b01010101};\r\n 8'd151 : mem_out = {2'b00, 8'b01010101,8'b01010101};\r\n 8'd152 : mem_out = {2'b00, 8'b00000000,8'b00000000};\r\n 8'd153 : mem_out = {2'b00, 8'b00000000,8'b00000000};\r\n 8'd154 : mem_out = {2'b00, 8'b01010101,8'b00101010};\r\n 8'd155 : mem_out = {2'b00, 8'b01010101,8'b10101010};\r\n 8'd156 : mem_out = {2'b10, 8'b00000000,8'b10000000};\r\n //Available\r\n 8'd157 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd158 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd159 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd160 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd161 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd162 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd163 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd164 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd165 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd166 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd167 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd168 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd169 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd170 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd171 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd172 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd173 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd174 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd175 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd176 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd177 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd178 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd179 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd180 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd181 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd182 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd183 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd184 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd185 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd186 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd187 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd188 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd189 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd190 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd191 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd192 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd193 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd194 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd195 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd196 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd197 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd198 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd199 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd200 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd201 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd202 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd203 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd204 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd205 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd206 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd207 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd208 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd209 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd210 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd211 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd212 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd213 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd214 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd215 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd216 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd217 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd218 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd219 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd220 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd221 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd222 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd223 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd224 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd225 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd226 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd227 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd228 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd229 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd230 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd231 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd232 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd233 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd234 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd235 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd236 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd237 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd238 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd239 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd240 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd241 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd242 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd243 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd244 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd245 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd246 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd247 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd248 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd249 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd250 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd251 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd252 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd253 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd254 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n 8'd255 : mem_out = {2'b00, 8'b00000001,8'b00000001};\r\n endcase\r\nend\r\n\r\n\r\n\r\nalways @ (posedge clk_i) begin\r\n if (rst_i | reset_rd_addr)\r\n rd_addr <= #TCQ 'b0;\r\n //rd_addr for complex oclkdelay calib\r\n else if (clk_en_i && prbs_rdlvl_done && (~phy_if_empty_r || ~complex_wr_done)) begin\r\n if (rd_addr == 'd156) rd_addr <= #TCQ 'b0;\r\n else rd_addr <= #TCQ rd_addr + 1;\r\n end\r\n //rd_addr for complex rdlvl\r\n else if (clk_en_i && (~phy_if_empty_r || (~prbs_rdlvl_start && ~complex_wr_done))) begin\r\n if (rd_addr == 'd148) rd_addr <= #TCQ 'b0;\r\n else rd_addr <= #TCQ rd_addr+1; \r\n end\r\n\r\nend\r\n\r\n// Each pattern can be disabled independently\r\n// When disabled zeros are written to and read from the DRAM \r\nalways @ (posedge clk_i) begin\r\n if ((rd_addr < 42) && VCCO_PAT_EN)\r\n dout_o <= #TCQ mem_out[BRAM_DATA_WIDTH-3:0];\r\n else if ((rd_addr < 127) && VCCAUX_PAT_EN)\r\n dout_o <= #TCQ mem_out[BRAM_DATA_WIDTH-3:0];\r\n else if (ISI_PAT_EN && (rd_addr > 126))\r\n dout_o <= #TCQ mem_out[BRAM_DATA_WIDTH-3:0];\r\n else\r\n dout_o <= #TCQ 'd0;\r\nend\r\n\r\nreg prbs_ignore_first_byte_r;\r\nalways @(posedge clk_i) prbs_ignore_first_byte_r <= #TCQ mem_out[16];\r\nassign prbs_ignore_first_byte = prbs_ignore_first_byte_r;\r\n\r\nreg prbs_ignore_last_bytes_r;\r\nalways @(posedge clk_i) prbs_ignore_last_bytes_r <= #TCQ mem_out[17];\r\nassign prbs_ignore_last_bytes = prbs_ignore_last_bytes_r;\r\n \r\n \r\n\r\ngenerate\r\n if (FIXED_VICTIM == \"TRUE\") begin: victim_sel_fixed\r\n // Fixed victim bit 3\r\n always @(posedge clk_i)\r\n sel <= #TCQ {DQ_WIDTH/8{8'h08}};\r\n end else begin: victim_sel_rotate\r\n // One-hot victim select\r\n always @(posedge clk_i)\r\n if (rst_i)\r\n sel <= #TCQ 'd0;\r\n else begin \r\n\t for (i = 0; i < DQ_WIDTH/8; i = i+1) begin\r\n\t for (j=0; j <8 ; j = j+1) begin\r\n\t if (j == victim_sel)\r\n\t\t sel[i*8+j] <= #TCQ 1'b1;\r\n\t\t else \r\n\t\t sel[i*8+j] <= #TCQ 1'b0;\r\n\t\t end \t\r\n\t end\r\n end\r\n end\r\nendgenerate\r\n \r\n\r\n\r\n// construct 8 X DATA_WIDTH output bus\r\nalways @(*)\r\n for (i = 0; i < DQ_WIDTH; i = i+1) begin\r\n dout_rise0[i] = (dout_o[7]&&sel[i] || dout_o[15]&&~sel[i]);\r\n dout_fall0[i] = (dout_o[6]&&sel[i] || dout_o[14]&&~sel[i]);\r\n dout_rise1[i] = (dout_o[5]&&sel[i] || dout_o[13]&&~sel[i]);\r\n dout_fall1[i] = (dout_o[4]&&sel[i] || dout_o[12]&&~sel[i]);\r\n dout_rise2[i] = (dout_o[3]&&sel[i] || dout_o[11]&&~sel[i]);\r\n dout_fall2[i] = (dout_o[2]&&sel[i] || dout_o[10]&&~sel[i]);\r\n dout_rise3[i] = (dout_o[1]&&sel[i] || dout_o[9]&&~sel[i]);\r\n dout_fall3[i] = (dout_o[0]&&sel[i] || dout_o[8]&&~sel[i]);\r\n end\r\n\r\n\r\n assign prbs_o = {dout_fall3, dout_rise3, dout_fall2, dout_rise2, dout_fall1, dout_rise1, dout_fall0, dout_rise0};\r\n \r\n assign dbg_prbs_gen[9] = phy_if_empty_r;\r\n assign dbg_prbs_gen[8] = clk_en_i;\r\n assign dbg_prbs_gen[7:0] = rd_addr[7:0];\r\n\r\nendmodule\r\n \r\n \r\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_ddr_skip_calib_tap.v", "content": "//*****************************************************************************\r\n// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.\r\n//\r\n// This file contains confidential and proprietary information\r\n// of Xilinx, Inc. and is protected under U.S. and\r\n// international copyright and other intellectual property\r\n// laws.\r\n//\r\n// DISCLAIMER\r\n// This disclaimer is not a license and does not grant any\r\n// rights to the materials distributed herewith. Except as\r\n// otherwise provided in a valid license issued to you by\r\n// Xilinx, and to the maximum extent permitted by applicable\r\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\r\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r\n// (2) Xilinx shall not be liable (whether in contract or tort,\r\n// including negligence, or under any other theory of\r\n// liability) for any loss or damage of any kind or nature\r\n// related to, arising under or in connection with these\r\n// materials, including for any direct, or any indirect,\r\n// special, incidental, or consequential loss or damage\r\n// (including loss of data, profits, goodwill, or any type of\r\n// loss or damage suffered as a result of any action brought\r\n// by a third party) even if such damage or loss was\r\n// reasonably foreseeable or Xilinx had been advised of the\r\n// possibility of the same.\r\n//\r\n// CRITICAL APPLICATIONS\r\n// Xilinx products are not designed or intended to be fail-\r\n// safe, or for use in any application requiring fail-safe\r\n// performance, such as life-support or safety devices or\r\n// systems, Class III medical devices, nuclear facilities,\r\n// applications related to the deployment of airbags, or any\r\n// other applications that could lead to death, personal\r\n// injury, or severe property or environmental damage\r\n// (individually and collectively, \"Critical\r\n// Applications\"). Customer assumes the sole risk and\r\n// liability of any use of Xilinx products in Critical\r\n// Applications, subject only to applicable laws and\r\n// regulations governing limitations on product liability.\r\n//\r\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r\n// PART OF THIS FILE AT ALL TIMES.\r\n//\r\n//*****************************************************************************\r\n// ____ ____\r\n// / /\\/ /\r\n// /___/ \\ / Vendor: Xilinx\r\n// \\ \\ \\/ Version: %version\r\n// \\ \\ Application: MIG\r\n// / / Filename: ddr_skip_calib_tap.v\r\n// /___/ /\\ Date Last Modified: $Date: 2015/05/06 02:07:40 $\r\n// \\ \\ / \\ Date Created: May 06 2015 \r\n// \\___\\/\\___\\\r\n//\r\n//Device: 7 Series\r\n//Design Name: DDR3 SDRAM\r\n//Purpose: Phaser_Out, Phaser_In, and IDELAY tap adjustments to match\r\n// calibration values when SKIP_CALIB==\"TRUE\"\r\n//Reference:\r\n//Revision History:\r\n//*****************************************************************************\r\n\r\n`timescale 1ps/1ps\r\n\r\nmodule mig_7series_v4_0_ddr_skip_calib_tap #\r\n (\r\n parameter TCQ = 100, // clk->out delay (sim only)\r\n parameter DQS_WIDTH = 8 // number of bytes\r\n )\r\n (\r\n input clk,\r\n input rst,\r\n input phy_ctl_ready,\r\n // Completed loading calib tap values into registers\r\n input load_done,\r\n // Tap adjustment status\r\n input calib_tap_inc_start, \r\n output calib_tap_inc_done,\r\n // Calibration tap values\r\n input [6*DQS_WIDTH-1:0] calib_po_stage2_tap_cnt,\r\n input [6*DQS_WIDTH-1:0] calib_po_stage3_tap_cnt,\r\n input [3*DQS_WIDTH-1:0] calib_po_coarse_tap_cnt,\r\n input [6*DQS_WIDTH-1:0] calib_pi_stage2_tap_cnt,\r\n input [5*DQS_WIDTH-1:0] calib_idelay_tap_cnt,\r\n // Phaser_Out and Phaser_In tap count\r\n input [8:0] po_counter_read_val,\r\n input [5:0] pi_counter_read_val,\r\n\t// Phaser_Out and Phaser_In tap inc/dec control signals\r\n output [5:0] calib_tap_inc_byte_cnt,\r\n output calib_po_f_en,\r\n output calib_po_f_incdec,\r\n output calib_po_sel_stg2stg3,\r\n output calib_po_c_en,\r\n output calib_po_c_inc,\r\n output calib_pi_f_en,\r\n output calib_pi_f_incdec,\r\n output calib_idelay_ce,\r\n output calib_idelay_inc,\r\n output skip_cal_po_pi_dec_done,\r\n output reg coarse_dec_err,\r\n output [127:0] dbg_skip_cal\r\n );\r\n \r\n //***************************************************************************\r\n // Decrement initial Phaser_OUT fine delay value before proceeding with\r\n // calibration\r\n //***************************************************************************\r\n\r\n\r\n reg phy_ctl_ready_r1, phy_ctl_ready_r2, phy_ctl_ready_r3, phy_ctl_ready_r4, phy_ctl_ready_r5, phy_ctl_ready_r6;\r\n reg po_cnt_dec;\r\n reg [3:0] dec_wait_cnt;\r\n reg [8:0] po_rdval_cnt;\r\n reg po_dec_done;\r\n reg dec_po_f_en_r;\r\n reg dec_po_f_incdec_r;\r\n reg dqs_po_dec_done_r1, dqs_po_dec_done_r2;\r\n reg fine_dly_dec_done_r1, fine_dly_dec_done_r2, fine_dly_dec_done_r3;\r\n reg [5:0] pi_rdval_cnt;\r\n reg pi_cnt_dec;\r\n reg dec_pi_f_en_r;\r\n reg dec_pi_f_incdec_r;\r\n \r\n always @(posedge clk) begin\r\n phy_ctl_ready_r1 <= #TCQ phy_ctl_ready;\r\n phy_ctl_ready_r2 <= #TCQ phy_ctl_ready_r1;\r\n phy_ctl_ready_r3 <= #TCQ phy_ctl_ready_r2;\r\n phy_ctl_ready_r4 <= #TCQ phy_ctl_ready_r3;\r\n phy_ctl_ready_r5 <= #TCQ phy_ctl_ready_r4;\r\n phy_ctl_ready_r6 <= #TCQ phy_ctl_ready_r5;\r\n end\r\n\r\n always @(posedge clk) begin\r\n if (rst || po_cnt_dec || pi_cnt_dec)\r\n dec_wait_cnt <= #TCQ 'd8;\r\n else if (phy_ctl_ready_r6 && (dec_wait_cnt > 'd0))\r\n dec_wait_cnt <= #TCQ dec_wait_cnt - 1;\r\n end\r\n \r\n always @(posedge clk) begin\r\n if (rst) begin\r\n po_rdval_cnt <= #TCQ 'd0;\r\n end else if (phy_ctl_ready_r5 && ~phy_ctl_ready_r6) begin\r\n po_rdval_cnt <= #TCQ po_counter_read_val;\r\n end else if (po_rdval_cnt > 'd0) begin\r\n if (po_cnt_dec)\r\n po_rdval_cnt <= #TCQ po_rdval_cnt - 1;\r\n else \r\n po_rdval_cnt <= #TCQ po_rdval_cnt;\r\n end else if (po_rdval_cnt == 'd0) begin\r\n po_rdval_cnt <= #TCQ po_rdval_cnt;\r\n end\r\n end\r\n\r\n always @(posedge clk) begin\r\n if (rst || (po_rdval_cnt == 'd0))\r\n po_cnt_dec <= #TCQ 1'b0;\r\n else if (phy_ctl_ready_r6 && (po_rdval_cnt > 'd0) && (dec_wait_cnt == 'd1))\r\n po_cnt_dec <= #TCQ 1'b1;\r\n else\r\n po_cnt_dec <= #TCQ 1'b0;\r\n end\r\n \r\n // Inc/Dec Phaser_Out stage 2 fine delay line\r\n always @(posedge clk) begin\r\n if (rst) begin\r\n dec_po_f_incdec_r <= #TCQ 1'b0;\r\n dec_po_f_en_r <= #TCQ 1'b0;\r\n end else if (po_cnt_dec) begin\r\n dec_po_f_incdec_r <= #TCQ 1'b0;\r\n dec_po_f_en_r <= #TCQ 1'b1;\r\n end else begin\r\n\t dec_po_f_incdec_r <= #TCQ 1'b0;\r\n dec_po_f_en_r <= #TCQ 1'b0;\r\n\t end\r\n end\r\n \r\n always @(posedge clk) begin\r\n if (rst)\r\n po_dec_done <= #TCQ 1'b0;\r\n else if (((po_cnt_dec == 'd1) && (po_rdval_cnt == 'd1)) || \r\n (phy_ctl_ready_r6 && (po_rdval_cnt == 'd0))) begin\r\n po_dec_done <= #TCQ 1'b1;\r\n end\r\n end\r\n\r\n //***************************************************************************\r\n // Decrement initial Phaser_IN fine delay value before proceeding with\r\n // calibration\r\n //***************************************************************************\r\n \r\n always @(posedge clk) begin\r\n dqs_po_dec_done_r1 <= #TCQ po_dec_done;\r\n dqs_po_dec_done_r2 <= #TCQ dqs_po_dec_done_r1;\r\n fine_dly_dec_done_r2 <= #TCQ fine_dly_dec_done_r1;\r\n fine_dly_dec_done_r3 <= #TCQ fine_dly_dec_done_r2;\r\n end\r\n\t \r\n always @(posedge clk) begin\r\n if (rst) begin\r\n pi_rdval_cnt <= #TCQ 'd0;\r\n end else if (dqs_po_dec_done_r1 && ~dqs_po_dec_done_r2) begin\r\n pi_rdval_cnt <= #TCQ pi_counter_read_val;\r\n end else if (pi_rdval_cnt > 'd0) begin\r\n if (pi_cnt_dec)\r\n pi_rdval_cnt <= #TCQ pi_rdval_cnt - 1;\r\n else \r\n pi_rdval_cnt <= #TCQ pi_rdval_cnt;\r\n end else if (pi_rdval_cnt == 'd0) begin\r\n pi_rdval_cnt <= #TCQ pi_rdval_cnt;\r\n end\r\n end\r\n\r\n always @(posedge clk) begin\r\n if (rst || (pi_rdval_cnt == 'd0))\r\n pi_cnt_dec <= #TCQ 1'b0;\r\n else if (dqs_po_dec_done_r2 && (pi_rdval_cnt > 'd0)\r\n \t && (dec_wait_cnt == 'd1))\r\n pi_cnt_dec <= #TCQ 1'b1;\r\n else\r\n pi_cnt_dec <= #TCQ 1'b0;\r\n end\r\n \r\n // Inc/Dec Phaser_In stage 2 fine delay line\r\n always @(posedge clk) begin\r\n if (rst) begin\r\n dec_pi_f_incdec_r <= #TCQ 1'b0;\r\n dec_pi_f_en_r <= #TCQ 1'b0;\r\n end else if (pi_cnt_dec) begin\r\n dec_pi_f_incdec_r <= #TCQ 1'b0;\r\n dec_pi_f_en_r <= #TCQ 1'b1;\r\n end else begin\r\n\t dec_pi_f_incdec_r <= #TCQ 1'b0;\r\n dec_pi_f_en_r <= #TCQ 1'b0;\r\n\t end\r\n end\r\n \r\n always @(posedge clk) begin\r\n if (rst) begin\r\n fine_dly_dec_done_r1 <= #TCQ 1'b0;\r\n end else if (((pi_cnt_dec == 'd1) && (pi_rdval_cnt == 'd1)) ||\r\n (dqs_po_dec_done_r2 && (pi_rdval_cnt == 'd0))) begin\r\n fine_dly_dec_done_r1 <= #TCQ 1'b1;\r\n end\r\n end\r\n \r\n assign skip_cal_po_pi_dec_done = fine_dly_dec_done_r3;\r\n\r\n//*************************end Phaser_Out and Phaser_In decrement to zero*******\r\n \r\n \r\n \r\n localparam WAIT_CNT = 15;\r\n\r\n // State Machine \r\n localparam [4:0] IDLE = 5'h00;\r\n localparam [4:0] READ_PO_PI_COUNTER_VAL = 5'h01;\r\n localparam [4:0] CALC_INC_DEC_CNT_VAL = 5'h02;\r\n localparam [4:0] WAIT_STG3_SEL = 5'h03;\r\n localparam [4:0] PO_COARSE_CNT_CHECK = 5'h04;\r\n localparam [4:0] PO_COARSE_INC = 5'h05;\r\n localparam [4:0] PO_STG3_SEL = 5'h06;\r\n localparam [4:0] PO_STG3_INC_CNT_CHECK = 5'h07;\r\n localparam [4:0] PO_STG3_INC = 5'h08;\r\n localparam [4:0] PO_STG3_DEC_CNT_CHECK = 5'h09;\r\n localparam [4:0] PO_STG3_DEC = 5'h0A;\r\n localparam [4:0] PO_STG2_INC_CNT_CHECK = 5'h0B;\r\n localparam [4:0] PO_STG2_INC = 5'h0C;\r\n localparam [4:0] PO_STG2_DEC_CNT_CHECK = 5'h0D;\r\n localparam [4:0] PO_STG2_DEC = 5'h0E;\r\n localparam [4:0] PI_STG2_INC_CNT_CHECK = 5'h0F;\r\n localparam [4:0] PI_STG2_INC = 5'h10;\r\n localparam [4:0] PI_STG2_DEC_CNT_CHECK = 5'h11;\r\n localparam [4:0] PI_STG2_DEC = 5'h12;\r\n localparam [4:0] IDELAY_CNT_CHECK = 5'h13;\r\n localparam [4:0] IDELAY_TAP_INC = 5'h14;\r\n localparam [4:0] WAIT_TAP_INC_DEC = 5'h15;\r\n localparam [4:0] NEXT_BYTE = 5'h16;\r\n localparam [4:0] WAIT_PO_PI_COUNTER_VAL = 5'h17;\r\n localparam [4:0] PO_PI_TAP_ADJ_DONE = 5'h18;\r\n \r\n \r\n reg calib_tap_inc_start_r;\r\n reg [4:0] skip_state_r;\r\n reg wait_cnt_en_r;\r\n reg wait_cnt_done;\r\n reg [3:0] wait_cnt_r;\r\n reg po_sel_stg23_r;\r\n reg po_f_en_r;\r\n reg po_f_incdec_r;\r\n reg po_c_en_r;\r\n reg po_c_inc_r;\r\n reg pi_f_en_r;\r\n reg pi_f_incdec_r;\r\n reg idelay_ce_r;\r\n reg idelay_inc_r;\r\n reg [2:0] po_c_inc_cnt;\r\n reg [5:0] po_stg3_inc_cnt;\r\n reg [5:0] po_stg3_dec_cnt;\r\n reg [5:0] po_stg2_inc_cnt;\r\n reg [5:0] po_stg2_dec_cnt;\r\n reg [5:0] pi_stg2_inc_cnt;\r\n reg [5:0] pi_stg2_dec_cnt;\r\n reg [4:0] idelay_inc_cnt;\r\n reg po_stg3_cnt_load_r;\r\n reg po_c_inc_active_r;\r\n reg po_stg3_inc_active_r;\r\n reg po_stg3_dec_active_r;\r\n reg po_stg2_inc_active_r;\r\n reg po_stg2_dec_active_r;\r\n reg pi_stg2_inc_active_r;\r\n reg pi_stg2_dec_active_r;\r\n reg idelay_inc_active_r;\r\n reg [5:0] byte_cnt_r;\r\n reg tap_adj_done_r;\r\n reg [2:0] calib_byte_po_c_cnt;\r\n reg [5:0] calib_byte_po_stg2_cnt;\r\n reg [5:0] calib_byte_po_stg3_cnt;\r\n reg [5:0] calib_byte_pi_stg2_cnt;\r\n reg [4:0] calib_byte_idelay_cnt;\r\n \r\n reg [4:0] skip_next_state;\r\n reg [5:0] byte_cnt;\r\n reg tap_adj_done;\r\n reg po_sel_stg23;\r\n reg po_f_en;\r\n reg po_f_incdec;\r\n reg po_c_en;\r\n reg po_c_inc;\r\n reg pi_f_en;\r\n reg pi_f_incdec;\r\n reg idelay_ce;\r\n reg idelay_inc;\r\n reg po_stg3_cnt_load;\r\n reg po_c_inc_active;\r\n reg po_stg3_inc_active;\r\n reg po_stg3_dec_active;\r\n reg po_stg2_inc_active;\r\n reg po_stg2_dec_active;\r\n reg pi_stg2_inc_active;\r\n reg pi_stg2_dec_active;\r\n reg idelay_inc_active;\r\n \r\n\r\n \r\n// Output assignments\r\n assign calib_tap_inc_byte_cnt = byte_cnt_r;\r\n assign calib_po_f_en = fine_dly_dec_done_r3 ? po_f_en_r : dec_po_f_en_r;\r\n assign calib_po_f_incdec = fine_dly_dec_done_r3 ? po_f_incdec_r : dec_po_f_incdec_r;\r\n assign calib_po_sel_stg2stg3 = po_sel_stg23_r;\r\n assign calib_po_c_en = po_c_en_r;\r\n assign calib_po_c_inc = po_c_inc_r;\r\n assign calib_pi_f_en = fine_dly_dec_done_r3 ? pi_f_en_r : dec_pi_f_en_r;\r\n assign calib_pi_f_incdec = fine_dly_dec_done_r3 ? pi_f_incdec_r : dec_pi_f_incdec_r;\r\n assign calib_idelay_ce = idelay_ce_r;\r\n assign calib_idelay_inc = idelay_inc_r;\r\n assign calib_tap_inc_done = tap_adj_done_r;\r\n \r\n// Register input calib_tap_inc_start\r\n always @(posedge clk)\r\n calib_tap_inc_start_r <= #TCQ calib_tap_inc_start;\r\n\r\n \r\n/**************************Wait Counter Start*********************************/\r\n// Wait counter enable for wait states WAIT_STG3_SEL, WAIT_TAP_INC_DEC, and\r\n// WAIT_PO_PI_COUNTER_VAL \r\n always @(posedge clk) begin\r\n if ((skip_state_r == WAIT_STG3_SEL) ||\r\n (skip_state_r == WAIT_TAP_INC_DEC) ||\r\n\t\t(skip_state_r == WAIT_PO_PI_COUNTER_VAL))\r\n wait_cnt_en_r <= #TCQ 1'b1;\r\n else\r\n wait_cnt_en_r <= #TCQ 1'b0;\r\n end\r\n\r\n// Wait counter enable for wait states WAIT_STG3_SEL, WAIT_TAP_INC_DEC, and\r\n// WAIT_PO_PI_COUNTER_VAL \r\n always @(posedge clk) begin\r\n if (!wait_cnt_en_r) begin\r\n wait_cnt_r <= #TCQ 'b0;\r\n wait_cnt_done <= #TCQ 1'b0;\r\n end else begin\r\n if (wait_cnt_r != WAIT_CNT - 1) begin\r\n wait_cnt_r <= #TCQ wait_cnt_r + 1;\r\n wait_cnt_done <= #TCQ 1'b0;\r\n end else begin\r\n wait_cnt_r <= #TCQ 'b0; \r\n wait_cnt_done <= #TCQ 1'b1;\r\n end\r\n end\r\n end\r\n/**************************Wait Counter End***********************************/\r\n\r\n// Calibration tap values for current byte being adjusted \r\n always @(posedge clk) begin\r\n if (rst) begin\r\n\t calib_byte_po_c_cnt <= #TCQ 'd0;\r\n\t calib_byte_po_stg2_cnt <= #TCQ 'd0;\r\n\t calib_byte_po_stg3_cnt <= #TCQ 'd0;\r\n\t calib_byte_pi_stg2_cnt <= #TCQ 'd0;\r\n\t calib_byte_idelay_cnt <= #TCQ 'd0;\r\n\tend else begin\r\n\t calib_byte_po_c_cnt <= #TCQ calib_po_coarse_tap_cnt[3*byte_cnt_r+:3];\r\n\t calib_byte_po_stg2_cnt <= #TCQ calib_po_stage2_tap_cnt[6*byte_cnt_r+:6];\r\n\t calib_byte_po_stg3_cnt <= #TCQ calib_po_stage3_tap_cnt[6*byte_cnt_r+:6];\r\n\t calib_byte_pi_stg2_cnt <= #TCQ calib_pi_stage2_tap_cnt[6*byte_cnt_r+:6];\r\n\t calib_byte_idelay_cnt <= #TCQ calib_idelay_tap_cnt[5*byte_cnt_r+:5];\r\n\tend\r\n end\r\n\r\n// Phaser_Out, Phaser_In, and IDELAY inc/dec counters \r\n always @(posedge clk) begin\r\n if (rst) begin\r\n\t po_c_inc_cnt <= #TCQ 'd0;\r\n\t po_stg2_inc_cnt <= #TCQ 'd0;\r\n\t po_stg2_dec_cnt <= #TCQ 'd0;\r\n\t pi_stg2_inc_cnt <= #TCQ 'd0;\r\n\t pi_stg2_dec_cnt <= #TCQ 'd0;\r\n\t idelay_inc_cnt <= #TCQ 'd0;\r\n\tend else if (skip_state_r == READ_PO_PI_COUNTER_VAL) begin\r\n\t // IDELAY tap count setting\r\n\t idelay_inc_cnt <= #TCQ calib_byte_idelay_cnt;\r\n // Phaser_Out coarse tap setting\t\r\n\t if (po_counter_read_val[8:6] == 'd0) begin\r\n\t coarse_dec_err <= #TCQ 1'b0;\r\n\t po_c_inc_cnt <= #TCQ calib_byte_po_c_cnt;\r\n\t end else if (po_counter_read_val[8:6] < calib_byte_po_c_cnt) begin\r\n\t coarse_dec_err <= #TCQ 1'b0;\r\n\t po_c_inc_cnt <= #TCQ calib_byte_po_c_cnt - po_counter_read_val[8:6];\r\n\t end else begin\r\n\t // Phaser_Out coarse taps cannot be decremented\r\n\t coarse_dec_err <= #TCQ 1'b1;\r\n\t po_c_inc_cnt <= #TCQ 'd0;\t\t\r\n\t end\r\n\t // Phaser_Out stage2 tap count setting when po_sel_stg23_r=0\r\n\t if (po_counter_read_val[5:0] == 'd0) begin\r\n\t po_stg2_inc_cnt <= #TCQ calib_byte_po_stg2_cnt;\r\n\t\tpo_stg2_dec_cnt <= #TCQ 'd0;\r\n\t end else if (po_counter_read_val[5:0] > calib_byte_po_stg2_cnt) begin\r\n\t po_stg2_inc_cnt <= #TCQ 'd0;\r\n\t\tpo_stg2_dec_cnt <= #TCQ po_counter_read_val[5:0] - calib_byte_po_stg2_cnt;\r\n\t end else if (po_counter_read_val[5:0] < calib_byte_po_stg2_cnt) begin\r\n\t po_stg2_inc_cnt <= #TCQ calib_byte_po_stg2_cnt - po_counter_read_val[5:0];\r\n\t\tpo_stg2_dec_cnt <= #TCQ 'd0;\r\n\t end else if (po_counter_read_val[5:0] == calib_byte_po_stg2_cnt) begin\r\n\t po_stg2_inc_cnt <= #TCQ 'd0;\r\n\t po_stg2_dec_cnt <= #TCQ 'd0;\r\n\t end\r\n\t //Phaser_In stgae2 tap count setting\r\n\t if (pi_counter_read_val == 'd0) begin\r\n\t pi_stg2_inc_cnt <= #TCQ calib_byte_pi_stg2_cnt;\r\n\t pi_stg2_dec_cnt <= #TCQ 'd0;\r\n\t end else if (pi_counter_read_val > calib_byte_pi_stg2_cnt) begin\r\n\t pi_stg2_inc_cnt <= #TCQ 'd0;\r\n\t pi_stg2_dec_cnt <= #TCQ pi_counter_read_val - calib_byte_pi_stg2_cnt;\r\n\t end else if (pi_counter_read_val < calib_byte_pi_stg2_cnt) begin\r\n\t pi_stg2_inc_cnt <= #TCQ calib_byte_pi_stg2_cnt - pi_counter_read_val;\r\n\t\tpi_stg2_dec_cnt <= #TCQ 'd0;\r\n\t end else if (pi_counter_read_val == calib_byte_pi_stg2_cnt) begin\r\n\t pi_stg2_inc_cnt <= #TCQ 'd0;\r\n\t\tpi_stg2_dec_cnt <= #TCQ 'd0;\r\n\t end\r\n\tend else begin\r\n\t if (skip_state_r == IDELAY_TAP_INC)\r\n\t idelay_inc_cnt <= #TCQ idelay_inc_cnt - 1;\r\n\t if (skip_state_r == PO_COARSE_INC)\r\n\t po_c_inc_cnt <= #TCQ po_c_inc_cnt - 1;\r\n\t if (skip_state_r == PO_STG2_INC)\r\n\t po_stg2_inc_cnt <= #TCQ po_stg2_inc_cnt - 1;\r\n\t if (skip_state_r == PO_STG2_DEC)\r\n\t po_stg2_dec_cnt <= #TCQ po_stg2_dec_cnt - 1;\r\n\t if (skip_state_r == PI_STG2_INC)\r\n\t pi_stg2_inc_cnt <= #TCQ pi_stg2_inc_cnt - 1;\r\n\t if (skip_state_r == PI_STG2_DEC)\r\n\t pi_stg2_dec_cnt <= #TCQ pi_stg2_dec_cnt - 1;\r\n\tend\r\n end\r\n \r\n // Phaser_Out stage 3 tap count setting when po_sel_stg23_r=1\r\n always @(posedge clk) begin\r\n if (rst) begin\r\n\t po_stg3_inc_cnt <= #TCQ 'd0;\r\n\t po_stg3_dec_cnt <= #TCQ 'd0;\r\n\tend else if ((skip_state_r == WAIT_STG3_SEL) && wait_cnt_done && po_stg3_cnt_load_r) begin\r\n\t if (po_counter_read_val[5:0] == 'd0) begin\r\n\t po_stg3_inc_cnt <= #TCQ calib_byte_po_stg3_cnt;\r\n\t\tpo_stg3_dec_cnt <= #TCQ 'd0;\r\n\t end else if (po_counter_read_val[5:0] > calib_byte_po_stg3_cnt) begin\r\n\t po_stg3_inc_cnt <= #TCQ 'd0;\r\n\t\tpo_stg3_dec_cnt <= #TCQ po_counter_read_val[5:0] - calib_byte_po_stg3_cnt;\r\n\t end else if (po_counter_read_val[5:0] < calib_byte_po_stg3_cnt) begin\r\n\t po_stg3_inc_cnt <= #TCQ calib_byte_po_stg3_cnt - po_counter_read_val[5:0];\r\n\t\tpo_stg3_dec_cnt <= #TCQ 'd0;\r\n\t end else if (po_counter_read_val[5:0] == calib_byte_po_stg3_cnt) begin\r\n\t po_stg3_inc_cnt <= #TCQ 'd0;\r\n\t po_stg3_dec_cnt <= #TCQ 'd0;\r\n\t end\r\n\tend else begin \r\n\t if (skip_state_r == PO_STG3_INC)\r\n\t po_stg3_inc_cnt <= #TCQ po_stg3_inc_cnt - 1;\r\n\t if (skip_state_r == PO_STG3_DEC)\r\n\t po_stg3_dec_cnt <= #TCQ po_stg3_dec_cnt - 1;\r\n\tend\r\n end\r\n\t \r\n always @(posedge clk) begin\r\n if (rst) begin\r\n\t skip_state_r <= #TCQ IDLE;\r\n\t byte_cnt_r <= #TCQ 'd0;\r\n\t tap_adj_done_r <= #TCQ 1'b0;\r\n\t po_sel_stg23_r <= #TCQ 1'b0;\r\n\t po_f_en_r <= #TCQ 1'b0;\r\n\t po_f_incdec_r <= #TCQ 1'b0;\r\n\t po_c_en_r <= #TCQ 1'b0;\r\n\t po_c_inc_r <= #TCQ 1'b0;\r\n\t pi_f_en_r <= #TCQ 1'b0;\r\n\t pi_f_incdec_r <= #TCQ 1'b0;\r\n\t idelay_ce_r <= #TCQ 1'b0;\r\n\t idelay_inc_r <= #TCQ 1'b0;\r\n\t po_stg3_cnt_load_r <= #TCQ 1'b0;\r\n\t po_c_inc_active_r <= #TCQ 1'b0;\r\n\t po_stg3_inc_active_r <= #TCQ 1'b0;\r\n\t po_stg3_dec_active_r <= #TCQ 1'b0;\r\n\t po_stg2_inc_active_r <= #TCQ 1'b0;\r\n\t po_stg2_dec_active_r <= #TCQ 1'b0;\r\n\t pi_stg2_inc_active_r <= #TCQ 1'b0;\r\n\t pi_stg2_dec_active_r <= #TCQ 1'b0;\r\n\t idelay_inc_active_r <= #TCQ 1'b0;\r\n\tend else begin\r\n\t skip_state_r <= #TCQ skip_next_state;\r\n\t byte_cnt_r <= #TCQ byte_cnt;\r\n\t tap_adj_done_r <= #TCQ tap_adj_done;\r\n\t po_sel_stg23_r <= #TCQ po_sel_stg23;\r\n\t po_f_en_r <= #TCQ po_f_en;\r\n\t po_f_incdec_r <= #TCQ po_f_incdec;\r\n\t po_c_en_r <= #TCQ po_c_en;\r\n\t po_c_inc_r <= #TCQ po_c_inc;\r\n\t pi_f_en_r <= #TCQ pi_f_en;\r\n\t pi_f_incdec_r <= #TCQ pi_f_incdec;\r\n\t idelay_ce_r <= #TCQ idelay_ce;\r\n\t idelay_inc_r <= #TCQ idelay_inc;\r\n\t po_stg3_cnt_load_r <= #TCQ po_stg3_cnt_load;\r\n\t po_c_inc_active_r <= #TCQ po_c_inc_active;\r\n\t po_stg3_inc_active_r <= #TCQ po_stg3_inc_active;\r\n\t po_stg3_dec_active_r <= #TCQ po_stg3_dec_active;\r\n\t po_stg2_inc_active_r <= #TCQ po_stg2_inc_active;\r\n\t po_stg2_dec_active_r <= #TCQ po_stg2_dec_active;\r\n\t pi_stg2_inc_active_r <= #TCQ pi_stg2_inc_active;\r\n\t pi_stg2_dec_active_r <= #TCQ pi_stg2_dec_active;\r\n\t idelay_inc_active_r <= #TCQ idelay_inc_active;\r\n\tend\r\n end\r\n\r\n// State Machine\r\n always @(*) begin\r\n\t skip_next_state = skip_state_r;\r\n\t byte_cnt = byte_cnt_r;\r\n\t tap_adj_done = tap_adj_done_r;\r\n\t po_sel_stg23 = po_sel_stg23_r;\r\n\t po_f_en = po_f_en_r;\r\n\t po_f_incdec = po_f_incdec_r;\r\n\t po_c_en = po_c_en_r;\r\n\t po_c_inc = po_c_inc_r;\r\n\t pi_f_en = pi_f_en_r;\r\n\t pi_f_incdec = pi_f_incdec_r;\r\n\t idelay_ce = idelay_ce_r;\r\n\t idelay_inc = idelay_inc_r;\r\n\t po_stg3_cnt_load = po_stg3_cnt_load_r;\r\n\t po_c_inc_active = po_c_inc_active_r;\r\n\t po_stg3_inc_active = po_stg3_inc_active_r;\r\n\t po_stg3_dec_active = po_stg3_dec_active_r;\r\n\t po_stg2_inc_active = po_stg2_inc_active_r;\r\n\t po_stg2_dec_active = po_stg2_dec_active_r;\r\n\t pi_stg2_inc_active = pi_stg2_inc_active_r;\r\n\t pi_stg2_dec_active = pi_stg2_dec_active_r;\r\n\t idelay_inc_active = idelay_inc_active_r;\r\n\r\n\t\r\n\t case(skip_state_r)\r\n\t IDLE: begin\r\n\t\t // Begin tap adjustment on the rising edge of calib_tap_inc_start\r\n\t\t // This logic assumes that load_done is asserted before calib_tap_inc_start\r\n\t\t // If this is not the case this logic will have to change\r\n\t if (calib_tap_inc_start && ~calib_tap_inc_start_r && load_done) begin\r\n skip_next_state = READ_PO_PI_COUNTER_VAL;\r\n\t end\r\n\t end\r\n\t\t\r\n\t\tREAD_PO_PI_COUNTER_VAL: begin\r\n\t\t skip_next_state = CALC_INC_DEC_CNT_VAL;\r\n\t\tend\r\n\t\t\r\n\t\tCALC_INC_DEC_CNT_VAL: begin\r\n\t\t skip_next_state = WAIT_STG3_SEL;\r\n\t\t po_sel_stg23 = 1'b1;\r\n\t\t po_stg3_cnt_load = 1'b1;\r\n\t\tend\r\n\t\t\r\n\t\tWAIT_STG3_SEL: begin\r\n\t\t if (wait_cnt_done) begin\r\n\t\t if (po_stg3_cnt_load)\r\n\t\t\t skip_next_state = PO_STG3_SEL;\r\n\t\t\telse\r\n\t\t\t skip_next_state = PO_COARSE_CNT_CHECK;\r\n\t\t end\r\n\t\tend\r\n\t\t\r\n\t\tPO_COARSE_CNT_CHECK: begin\r\n\t\t if (po_c_inc_cnt > 'd0) begin\r\n\t\t po_c_inc_active = 1'b1;\r\n\t\t\tskip_next_state = PO_COARSE_INC;\r\n\t\t end else begin\r\n\t\t po_c_inc_active = 1'b0;\r\n\t\t\tskip_next_state = PO_STG2_DEC_CNT_CHECK;\r\n\t\t end\r\n\t\tend\r\n\t\t\r\n\t\tPO_COARSE_INC: begin\r\n\t\t po_c_en = 1'b1;\r\n\t\t po_c_inc = 1'b1;\r\n\t\t skip_next_state = WAIT_TAP_INC_DEC;\r\n\t\tend\r\n\t\t\r\n\t\tPO_STG3_SEL: begin\r\n\t\t po_stg3_cnt_load = 1'b0;\r\n\t\t if (po_stg3_inc_cnt > 'd0) begin\r\n\t\t po_stg3_inc_active = 1'b1;\r\n\t\t\tskip_next_state = PO_STG3_INC;\r\n\t end else if (po_stg3_dec_cnt > 'd0) begin\r\n\t\t po_stg3_dec_active = 1'b1;\r\n\t\t\tskip_next_state = PO_STG3_DEC;\r\n\t\t end else begin\r\n\t\t po_sel_stg23 = 1'b0;\r\n\t\t skip_next_state = WAIT_STG3_SEL;\r\n\t\t\t\r\n\t\t end\r\n\t\tend\r\n\t\t\r\n\t\tPO_STG3_INC_CNT_CHECK: begin\r\n\t\t if (po_stg3_inc_cnt > 'd0) begin\r\n\t\t po_stg3_inc_active = 1'b1;\r\n\t\t\tskip_next_state = PO_STG3_INC;\r\n\t\t end else begin\r\n\t\t po_stg3_inc_active = 1'b0;\r\n\t\t\tpo_sel_stg23 = 1'b0;\r\n\t\t\tskip_next_state = WAIT_STG3_SEL;\r\n\t end\r\n\t\tend\r\n\t\t\r\n\t\tPO_STG3_INC: begin\r\n\t\t po_f_en = 1'b1;\r\n\t\t po_f_incdec = 1'b1;\r\n\t\t skip_next_state = WAIT_TAP_INC_DEC;\r\n\t\tend\r\n\t\t\r\n\t\tPO_STG3_DEC_CNT_CHECK: begin\t\t \r\n\t\t if (po_stg3_dec_cnt > 'd0) begin\r\n\t\t po_stg3_dec_active = 1'b1;\r\n\t\t\tskip_next_state = PO_STG3_DEC;\r\n\t\t end else begin\r\n\t\t po_stg3_dec_active = 1'b0;\r\n\t\t\tpo_sel_stg23 = 1'b0;\r\n\t\t\tskip_next_state = WAIT_STG3_SEL;\r\n\t\t end\r\n\t\tend\r\n\t\t\r\n\t\tPO_STG3_DEC: begin\r\n\t\t po_f_en = 1'b1;\r\n\t\t po_f_incdec = 1'b0;\r\n\t\t skip_next_state = WAIT_TAP_INC_DEC;\r\n\t\tend\r\n\t\t\r\n\t\tPO_STG2_DEC_CNT_CHECK: begin\r\n\t\t if (po_stg2_dec_cnt > 'd0) begin\r\n\t\t po_stg2_dec_active = 1'b1;\r\n\t\t\tskip_next_state = PO_STG2_DEC;\r\n\t\t end else if (po_stg2_inc_cnt > 'd0) begin\r\n\t\t po_stg2_dec_active = 1'b0;\r\n\t\t\tskip_next_state = PO_STG2_INC_CNT_CHECK;\r\n\t\t end else begin\r\n\t\t po_stg2_dec_active = 1'b0;\r\n\t\t\tskip_next_state = PI_STG2_DEC_CNT_CHECK;\r\n\t\t end\r\n\t\tend\r\n\t\t\r\n\t\tPO_STG2_DEC: begin\r\n\t\t po_f_en = 1'b1;\r\n\t\t po_f_incdec = 1'b0;\r\n\t\t skip_next_state = WAIT_TAP_INC_DEC;\r\n\t\tend\r\n\t\t\r\n\t\tPO_STG2_INC_CNT_CHECK: begin\r\n\t\t if (po_stg2_inc_cnt > 'd0) begin\r\n\t\t po_stg2_inc_active = 1'b1;\r\n\t\t\tskip_next_state = PO_STG2_INC;\r\n\t\t end else begin\r\n\t\t po_stg2_inc_active = 1'b0;\r\n\t\t\tskip_next_state = PI_STG2_DEC_CNT_CHECK;\r\n\t\t end\r\n\t\tend\r\n\t\t\r\n\t\tPO_STG2_INC: begin\r\n\t\t po_f_en = 1'b1;\r\n\t\t po_f_incdec = 1'b1;\r\n\t\t skip_next_state = WAIT_TAP_INC_DEC;\r\n\t\tend\r\n\t\t\r\n\t\tPI_STG2_DEC_CNT_CHECK: begin\r\n\t\t if (pi_stg2_dec_cnt > 'd0) begin\r\n\t\t pi_stg2_dec_active = 1'b1;\r\n\t\t\tskip_next_state = PI_STG2_DEC;\r\n\t\t end else if (pi_stg2_inc_cnt > 'd0) begin\r\n\t\t pi_stg2_dec_active = 1'b0;\r\n\t\t\tskip_next_state = PI_STG2_INC_CNT_CHECK;\r\n\t\t end else begin\r\n\t\t pi_stg2_dec_active = 1'b0;\r\n\t\t\tskip_next_state = IDELAY_CNT_CHECK;\r\n\t\t end\r\n\t\tend\r\n\t\t\r\n\t\tPI_STG2_DEC: begin\r\n\t\t pi_f_en = 1'b1;\r\n\t\t pi_f_incdec = 1'b0;\r\n\t\t skip_next_state = WAIT_TAP_INC_DEC;\r\n\t\tend\r\n\t\t\r\n\t\tPI_STG2_INC_CNT_CHECK: begin\r\n\t\t if (pi_stg2_inc_cnt > 'd0) begin\r\n\t\t pi_stg2_inc_active = 1'b1;\r\n\t\t\tskip_next_state = PI_STG2_INC;\r\n\t\t end else begin\r\n\t\t pi_stg2_inc_active = 1'b0;\r\n\t\t\tskip_next_state = IDELAY_CNT_CHECK;\r\n\t\t end\r\n\t\tend\r\n\t\t\r\n\t\tPI_STG2_INC: begin\r\n\t\t pi_f_en = 1'b1;\r\n\t\t pi_f_incdec = 1'b1;\r\n\t\t skip_next_state = WAIT_TAP_INC_DEC;\r\n\t\tend\r\n\t\t\r\n\t\tIDELAY_CNT_CHECK: begin\r\n\t\t if (idelay_inc_cnt > 'd0) begin\r\n\t\t idelay_inc_active = 1'b1;\r\n\t\t\tskip_next_state = IDELAY_TAP_INC;\r\n\t\t end else begin\r\n\t\t idelay_inc_active = 1'b0;\r\n\t\t\tskip_next_state = NEXT_BYTE;\r\n\t\t end\r\n\t\tend\r\n\t\t\r\n\t\tIDELAY_TAP_INC: begin\r\n\t\t idelay_ce = 1'b1;\r\n\t\t idelay_inc = 1'b1;\r\n\t\t skip_next_state = WAIT_TAP_INC_DEC;\r\n\t\tend\r\n\t\t\r\n\t\tWAIT_TAP_INC_DEC: begin\r\n\t\t po_c_en = 1'b0;\r\n\t\t po_c_inc = 1'b0;\r\n\t\t po_f_en = 1'b0;\r\n\t\t po_f_incdec = 1'b0;\r\n\t\t pi_f_en = 1'b0;\r\n\t\t pi_f_incdec = 1'b0;\r\n\t\t idelay_ce = 1'b0;\r\n\t\t idelay_inc = 1'b0;\r\n\t\t if (wait_cnt_done) begin\r\n\t\t if (po_c_inc_active_r)\r\n\t\t\t skip_next_state = PO_COARSE_CNT_CHECK;\r\n\t\t\telse if (po_stg3_inc_active_r)\r\n\t\t\t skip_next_state = PO_STG3_INC_CNT_CHECK;\r\n\t\t\telse if (po_stg3_dec_active_r)\r\n\t\t\t skip_next_state = PO_STG3_DEC_CNT_CHECK;\r\n\t\t\telse if (po_stg2_dec_active_r)\r\n\t\t\t skip_next_state = PO_STG2_DEC_CNT_CHECK;\r\n\t\t\telse if (po_stg2_inc_active_r)\r\n\t\t\t skip_next_state = PO_STG2_INC_CNT_CHECK;\r\n\t\t\telse if (pi_stg2_dec_active_r)\r\n\t\t\t skip_next_state = PI_STG2_DEC_CNT_CHECK;\r\n\t\t\telse if (pi_stg2_inc_active_r)\r\n\t\t\t skip_next_state = PI_STG2_INC_CNT_CHECK;\r\n\t\t\telse if (idelay_inc_active_r)\r\n\t\t\t skip_next_state = IDELAY_CNT_CHECK;\r\n\t\t end\r\n\t\tend\r\n\t\t\r\n\t\tNEXT_BYTE: begin\r\n\t\t if (byte_cnt_r >= DQS_WIDTH-1) begin\r\n\t\t skip_next_state = PO_PI_TAP_ADJ_DONE;\r\n\t\t end else begin\r\n\t\t byte_cnt = byte_cnt + 1;\r\n\t\t\tskip_next_state = WAIT_PO_PI_COUNTER_VAL;\r\n\t\t end\r\n\t\tend\r\n\t\t\r\n\t\tWAIT_PO_PI_COUNTER_VAL: begin\r\n\t\t if (wait_cnt_done)\r\n\t\t skip_next_state = READ_PO_PI_COUNTER_VAL;\r\n\t\tend\r\n\t\t\r\n\t\tPO_PI_TAP_ADJ_DONE: begin\r\n\t\t tap_adj_done = 1'b1;\r\n\t\tend\r\n\t\t\r\n\t\tdefault: begin\r\n\t skip_next_state = IDLE;\r\n\t end\r\n\t\t\r\n\t endcase\r\n end\t\t\r\n\r\n //Debug\r\n assign dbg_skip_cal[4:0] = skip_state_r;\r\n assign dbg_skip_cal[7:5] = po_c_inc_cnt;\r\n assign dbg_skip_cal[13:8] = po_stg3_inc_cnt;\r\n assign dbg_skip_cal[19:14] = po_stg3_dec_cnt;\r\n assign dbg_skip_cal[25:20] = po_stg2_inc_cnt;\r\n assign dbg_skip_cal[31:26] = po_stg2_dec_cnt;\r\n assign dbg_skip_cal[37:32] = pi_stg2_inc_cnt;\r\n assign dbg_skip_cal[43:38] = pi_stg2_dec_cnt;\r\n assign dbg_skip_cal[48:44] = idelay_inc_cnt;\r\n assign dbg_skip_cal[54:49] = byte_cnt_r;\r\n assign dbg_skip_cal[55] = po_c_inc_active;\r\n assign dbg_skip_cal[56] = po_stg3_inc_active;\r\n assign dbg_skip_cal[57] = po_stg3_dec_active;\r\n assign dbg_skip_cal[58] = po_stg2_inc_active;\r\n assign dbg_skip_cal[59] = po_stg2_dec_active;\r\n assign dbg_skip_cal[60] = pi_stg2_inc_active;\r\n assign dbg_skip_cal[61] = pi_stg2_dec_active;\r\n assign dbg_skip_cal[62] = idelay_inc_active;\r\n \r\nendmodule \n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_cc.v", "content": "//*****************************************************************************\n// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor: Xilinx\n// \\ \\ \\/ Version:%version\n// \\ \\ Application: MIG\n// / / Filename: mig_7series_v4_0_poc_cc.v\n// /___/ /\\ Date Last Modified: $$\n// \\ \\ / \\ Date Created:Tue 20 Jan 2014\n// \\___\\/\\___\\\n//\n//Device: Virtex-7\n//Design Name: DDR3 SDRAM\n//Purpose: Phaser out characterization and control. Logic to interface with\n// Chipscope and control. Intended to support real time observation. Largely\n// not generated for production implementations.\n//\n// Also generates debug bus. Concept is a dynamic portion that can be used\n// to examine the POC while it is operating, and a logging portion that\n// stores per lane results.\n//\n//Reference:\n//Revision History:\n//*****************************************************************************\n\n`timescale 1 ps / 1 ps\n\nmodule mig_7series_v4_0_poc_cc #\n (parameter TCQ = 100,\n parameter CCENABLE = 0,\n parameter LANE_CNT_WIDTH = 2,\n parameter PCT_SAMPS_SOLID = 95,\n parameter SAMPCNTRWIDTH = 8,\n parameter SAMPLES = 128,\n parameter SMWIDTH = 2,\n parameter TAPCNTRWIDTH = 7)\n (/*AUTOARG*/\n // Outputs\n samples, samps_solid_thresh, poc_error, dbg_poc,\n // Inputs\n psen, clk, rst, ktap_at_right_edge, ktap_at_left_edge,\n mmcm_lbclk_edge_aligned, mmcm_edge_detect_done, fall_lead_right,\n fall_trail_right, rise_lead_right, rise_trail_right, fall_lead_left,\n fall_trail_left, rise_lead_left, rise_trail_left, fall_lead_center,\n fall_trail_center, rise_lead_center, rise_trail_center, lane,\n mmcm_edge_detect_rdy, poc_backup, sm, tap, run, run_end,\n run_polarity, run_too_small, samp_cntr, samps_hi, samps_hi_held,\n samps_zero, samps_one, run_ends, diff, left, right, window_center,\n edge_center\n );\n\n // Remember SAMPLES is whole number counting. Zero corresponds to one sample.\n localparam integer SAMPS_SOLID_THRESH = (SAMPLES+1) * PCT_SAMPS_SOLID * 0.01;\n\n output [SAMPCNTRWIDTH:0] samples, samps_solid_thresh;\n input psen;\n\n input clk, rst;\n input ktap_at_right_edge, ktap_at_left_edge;\n\n input mmcm_lbclk_edge_aligned;\n wire reset_aligned_cnt = rst || ktap_at_right_edge || ktap_at_left_edge || mmcm_lbclk_edge_aligned;\n \n input mmcm_edge_detect_done;\n reg mmcm_edge_detect_done_r;\n always @(posedge clk) mmcm_edge_detect_done_r <= #TCQ mmcm_edge_detect_done;\n wire done = mmcm_edge_detect_done && ~mmcm_edge_detect_done_r;\n \n \n reg [6:0] aligned_cnt_r;\n wire [6:0] aligned_cnt_ns = reset_aligned_cnt ? 7'b0 : aligned_cnt_r + {6'b0, done};\n always @(posedge clk) aligned_cnt_r <= #TCQ aligned_cnt_ns;\n\n reg poc_error_r;\n wire poc_error_ns = ~rst && (aligned_cnt_r[6] || poc_error_r);\n always @(posedge clk) poc_error_r <= #TCQ poc_error_ns;\n output poc_error;\n assign poc_error = poc_error_r;\n \n input [TAPCNTRWIDTH-1:0] fall_lead_right, fall_trail_right, rise_lead_right, rise_trail_right;\n input [TAPCNTRWIDTH-1:0] fall_lead_left, fall_trail_left, rise_lead_left, rise_trail_left;\n input [TAPCNTRWIDTH-1:0] fall_lead_center, fall_trail_center, rise_lead_center, rise_trail_center;\n\n\n generate if (CCENABLE == 0) begin : no_characterization\n assign samples = SAMPLES[SAMPCNTRWIDTH:0];\n assign samps_solid_thresh = SAMPS_SOLID_THRESH[SAMPCNTRWIDTH:0];\n end else begin : characterization\n end endgenerate\n\n reg [1023:0] dbg_poc_r;\n output [1023:0] dbg_poc;\n assign dbg_poc = dbg_poc_r;\n input [LANE_CNT_WIDTH-1:0] lane;\n\n input mmcm_edge_detect_rdy;\n input poc_backup;\n input [SMWIDTH-1:0] sm;\n input [TAPCNTRWIDTH-1:0] tap;\n input [TAPCNTRWIDTH-1:0] run;\n input run_end;\n input run_polarity;\n input run_too_small;\n input [SAMPCNTRWIDTH-1:0] samp_cntr;\n input [SAMPCNTRWIDTH:0] samps_hi;\n input [SAMPCNTRWIDTH:0] samps_hi_held;\n input samps_zero, samps_one;\n input [1:0] run_ends;\n input [TAPCNTRWIDTH+1:0] diff;\n\n always @(*) begin\n dbg_poc_r[99:0] = 'b0;\n dbg_poc_r[1023:900] = 'b0;\n dbg_poc_r[0] = mmcm_edge_detect_rdy;\n dbg_poc_r[1] = mmcm_edge_detect_done;\n dbg_poc_r[2] = ktap_at_right_edge;\n dbg_poc_r[3] = ktap_at_left_edge;\n dbg_poc_r[4] = mmcm_lbclk_edge_aligned;\n dbg_poc_r[5] = poc_backup;\n dbg_poc_r[6+:SMWIDTH] = sm;\n dbg_poc_r[10+:TAPCNTRWIDTH] = tap;\n dbg_poc_r[20+:TAPCNTRWIDTH] = run;\n dbg_poc_r[30] = run_end;\n dbg_poc_r[31] = run_polarity;\n dbg_poc_r[32] = run_too_small;\n dbg_poc_r[33+:SAMPCNTRWIDTH] = samp_cntr;\n dbg_poc_r[49+:SAMPCNTRWIDTH+1] = samps_hi;\n dbg_poc_r[66+:SAMPCNTRWIDTH+1] = samps_hi_held;\n dbg_poc_r[83] = samps_zero;\n dbg_poc_r[84] = samps_one;\n dbg_poc_r[86:85] = run_ends;\n dbg_poc_r[87+:TAPCNTRWIDTH+2] = diff;\n end // always @ (*)\n\n input [TAPCNTRWIDTH-1:0] left, right;\n input [TAPCNTRWIDTH:0] window_center, edge_center;\n\n reg [899:100] dbg_poc_ns;\n always @(posedge clk) dbg_poc_r[899:100] <= #TCQ dbg_poc_ns;\n\n always @(*) begin\n if (rst) dbg_poc_ns = 'b0;\n else begin\n dbg_poc_ns = dbg_poc_r[899:100];\n if (mmcm_edge_detect_rdy && lane < 8) begin\n\tdbg_poc_ns[(lane+1)*100] = poc_backup;\n\tdbg_poc_ns[(lane+1)*100+1] = dbg_poc_ns[(lane+1)*100+1] || run_too_small;\n dbg_poc_ns[(lane+1)*100+10+:TAPCNTRWIDTH] = left;\n dbg_poc_ns[(lane+1)*100+20+:TAPCNTRWIDTH] = right;\n\tdbg_poc_ns[(lane+1)*100+30+:TAPCNTRWIDTH+1] = window_center;\n\tdbg_poc_ns[(lane+1)*100+41+:TAPCNTRWIDTH+1] = edge_center;\n end\n end\n end\n \nendmodule // mig_7series_v4_0_poc_cc\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_edge_store.v", "content": "//*****************************************************************************\n// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor: Xilinx\n// \\ \\ \\/ Version:%version\n// \\ \\ Application: MIG\n// / / Filename: mig_7series_v4_0_poc_meta.v\n// /___/ /\\ Date Last Modified: $$\n// \\ \\ / \\ Date Created:Fri 24 Jan 2014\n// \\___\\/\\___\\\n//\n//Device: Virtex-7\n//Design Name: DDR3 SDRAM\n//Purpose: Phaser output calibration edge store.\n//Reference:\n//Revision History:\n//*****************************************************************************\n\n`timescale 1 ps / 1 ps\n\nmodule mig_7series_v4_0_poc_edge_store #\n (parameter TCQ = 100,\n parameter TAPCNTRWIDTH = 7,\n parameter TAPSPERKCLK = 112)\n (/*AUTOARG*/\n // Outputs\n fall_lead, fall_trail, rise_lead, rise_trail,\n // Inputs\n clk, run_polarity, run_end, select0, select1, tap, run\n );\n \n input clk;\n\n input run_polarity;\n input run_end;\n input select0;\n input select1;\n input [TAPCNTRWIDTH-1:0] tap;\n input [TAPCNTRWIDTH-1:0] run;\n\n wire [TAPCNTRWIDTH:0] trailing_edge = run > tap ? tap + TAPSPERKCLK[TAPCNTRWIDTH-1:0] - run\n : tap - run;\n\n wire run_end_this = run_end && select0 && select1;\n\n reg [TAPCNTRWIDTH-1:0] fall_lead_r, fall_trail_r, rise_lead_r, rise_trail_r;\n output [TAPCNTRWIDTH-1:0] fall_lead, fall_trail, rise_lead, rise_trail;\n assign fall_lead = fall_lead_r;\n assign fall_trail = fall_trail_r;\n assign rise_lead = rise_lead_r;\n assign rise_trail = rise_trail_r;\n \n wire [TAPCNTRWIDTH-1:0] fall_lead_ns = run_end_this & run_polarity ? tap : fall_lead_r;\n wire [TAPCNTRWIDTH-1:0] rise_trail_ns = run_end_this & run_polarity ? trailing_edge[TAPCNTRWIDTH-1:0]\n : rise_trail_r;\n wire [TAPCNTRWIDTH-1:0] rise_lead_ns = run_end_this & ~run_polarity ? tap : rise_lead_r;\n wire [TAPCNTRWIDTH-1:0] fall_trail_ns = run_end_this & ~run_polarity ? trailing_edge[TAPCNTRWIDTH-1:0]\n : fall_trail_r;\n \n always @(posedge clk) fall_lead_r <= #TCQ fall_lead_ns;\n always @(posedge clk) fall_trail_r <= #TCQ fall_trail_ns;\n always @(posedge clk) rise_lead_r <= #TCQ rise_lead_ns;\n always @(posedge clk) rise_trail_r <= #TCQ rise_trail_ns;\n \nendmodule // mig_7series_v4_0_poc_edge_store\n\n// Local Variables:\n// verilog-library-directories:(\".\")\n// verilog-library-extensions:(\".v\")\n// End:\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_meta.v", "content": "//*****************************************************************************\n// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor: Xilinx\n// \\ \\ \\/ Version:%version\n// \\ \\ Application: MIG\n// / / Filename: mig_7series_v4_0_poc_meta.v\n// /___/ /\\ Date Last Modified: $$\n// \\ \\ / \\ Date Created:Tue 15 Jan 2014\n// \\___\\/\\___\\\n//\n//Device: Virtex-7\n//Design Name: DDR3 SDRAM\n//Purpose: Phaser output calibration meta controller.\n//\n// Compute center of the window set up with with the ktap_left, \n// ktap_right dance (hereafter \"the window\"). Also compute center of the \n// edge (hereafter \"the edge\") to be aligned in the center\n// of this window.\n//\n// Following the ktap_left/right dance, the to be centered edge is \n// always left at the right edge of the window\n// if SCANFROMRIGHT == 1, and the left edge otherwise. \n//\n// An assumption is the rise(0) case has a window wider than the noise on the\n// edge. The noise case with the possibly narrow window\n// will always be shifted by 90. And the fall(180) case is shifted by\n// 90 twice. Hence when we start, we can assume the center of the\n// edge is to the right/left of the the window center.\n//\n// The actual hardware does not necessarily monotonically appear to\n// move the window centers. Because of noise, it is possible for the\n// centered edge to move opposite the expected direction with a tap increment.\n//\n// This problem is solved by computing the absolute difference between\n// the centers and the circular distance between the centers. These will\n// be the same until the difference transits through zero. Then the circular\n// difference will jump to almost the value of TAPSPERKCLK.\n//\n// The window center computation is done at 1/2 tap increments to maintain\n// resolution through the divide by 2 for centering.\n//\n// There is a corner case of when the shift is greater than 180 degress. In\n// this case the absolute difference and the circular difference will be\n// unequal at the beginning of the alignment. This is solved by latching\n// if they are equal at the end of each cycle. The completion must see\n// that they were equal in the previous cycle, but are not equal in this cycle.\n//\n// Since the phaser out steps are of unknown size, it is possible to overshoot\n// the center. The previous difference is recorded and if its less than the current\n// difference, poc_backup is driven high.\n//\n//Reference:\n//Revision History:\n//*****************************************************************************\n\n`timescale 1 ps / 1 ps\n\nmodule mig_7series_v4_0_poc_meta #\n (parameter SCANFROMRIGHT = 0,\n parameter TCQ = 100,\n parameter TAPCNTRWIDTH = 7,\n parameter TAPSPERKCLK = 112)\n (/*AUTOARG*/\n // Outputs\n run_ends, mmcm_edge_detect_done, edge_center, left, right,\n window_center, diff, poc_backup, mmcm_lbclk_edge_aligned,\n // Inputs\n rst, clk, mmcm_edge_detect_rdy, run_too_small, run, run_end,\n run_polarity, rise_lead_right, rise_trail_left, rise_lead_center,\n rise_trail_center, rise_trail_right, rise_lead_left, ninety_offsets,\n use_noise_window, ktap_at_right_edge, ktap_at_left_edge\n );\n\n localparam NINETY = TAPSPERKCLK/4;\n \n function [TAPCNTRWIDTH-1:0] offset (input [TAPCNTRWIDTH-1:0] a, \n input [1:0] b,\n input integer base);\n integer offset_ii;\n begin\n offset_ii = (a + b * NINETY) < base\n ? (a + b * NINETY) \n : (a + b * NINETY - base);\n offset = offset_ii[TAPCNTRWIDTH-1:0];\n end\n endfunction // offset\n\n function [TAPCNTRWIDTH-1:0] mod_sub (input [TAPCNTRWIDTH-1:0] a, \n input [TAPCNTRWIDTH-1:0] b,\n input integer base); \n begin\n mod_sub = (a>=b) ? a-b : a+base-b;\n end\n endfunction // mod_sub\n\n function [TAPCNTRWIDTH:0] center (input [TAPCNTRWIDTH-1:0] left, \n input [TAPCNTRWIDTH-1:0] diff,\n input integer base);\n integer center_ii;\n begin\n center_ii = ({left, 1'b0} + diff < base * 2)\n ? {left, 1'b0} + diff + 32'h0\n\t : {left, 1'b0} + diff - base * 2;\n center = center_ii[TAPCNTRWIDTH:0];\n end\n endfunction // center\n\n input rst;\n input clk;\n\n\n input mmcm_edge_detect_rdy;\n\n reg [1:0] run_ends_r;\n\n input run_too_small;\n reg run_too_small_r1, run_too_small_r2, run_too_small_r3;\n\n always @ (posedge clk) run_too_small_r1 <= #TCQ run_too_small & (run_ends_r == 'd1); //align with run_end_r1;\n always @ (posedge clk) run_too_small_r2 <= #TCQ run_too_small_r1;\n always @ (posedge clk) run_too_small_r3 <= #TCQ run_too_small_r2;\n\n wire reset_run_ends = rst || ~mmcm_edge_detect_rdy || run_too_small_r3 ;\n\n // This input used only for the SVA.\n input [TAPCNTRWIDTH-1:0] run;\n \n input run_end;\n reg run_end_r, run_end_r1, run_end_r2, run_end_r3;\n always @(posedge clk) run_end_r <= #TCQ run_end;\n always @(posedge clk) run_end_r1 <= #TCQ run_end_r;\n always @(posedge clk) run_end_r2 <= #TCQ run_end_r1;\n always @(posedge clk) run_end_r3 <= #TCQ run_end_r2;\n\n input run_polarity;\n reg run_polarity_held_ns, run_polarity_held_r;\n always @(posedge clk) run_polarity_held_r <= #TCQ run_polarity_held_ns;\n always @(*) run_polarity_held_ns = run_end ? run_polarity : run_polarity_held_r;\n \n reg [1:0] run_ends_ns;\n always @(posedge clk) run_ends_r <= #TCQ run_ends_ns;\n always @(*) begin\n run_ends_ns = run_ends_r;\n if (reset_run_ends) run_ends_ns = 2'b0;\n else case (run_ends_r) \n 2'b00 : run_ends_ns = run_ends_r + {1'b0, run_end_r3 && run_polarity_held_r};\n\t 2'b01, 2'b10 : run_ends_ns = run_ends_r + {1'b0, run_end_r3};\n\t endcase // case (run_ends_r)\n end // always @ begin\n output [1:0] run_ends;\n assign run_ends = run_ends_r;\n\n reg done_r;\n wire done_ns = mmcm_edge_detect_rdy && &run_ends_r;\n always @(posedge clk) done_r <= #TCQ done_ns;\n output mmcm_edge_detect_done;\n assign mmcm_edge_detect_done = done_r; \n\n input [TAPCNTRWIDTH-1:0] rise_lead_right;\n input [TAPCNTRWIDTH-1:0] rise_trail_left;\n input [TAPCNTRWIDTH-1:0] rise_lead_center;\n input [TAPCNTRWIDTH-1:0] rise_trail_center;\n input [TAPCNTRWIDTH-1:0] rise_trail_right;\n input [TAPCNTRWIDTH-1:0] rise_lead_left;\n\n input [1:0] ninety_offsets;\n wire [1:0] offsets = SCANFROMRIGHT == 1 ? ninety_offsets : 2'b00 - ninety_offsets;\n\n wire [TAPCNTRWIDTH-1:0] rise_lead_center_offset_ns = offset(rise_lead_center, offsets, TAPSPERKCLK);\n wire [TAPCNTRWIDTH-1:0] rise_trail_center_offset_ns = offset(rise_trail_center, offsets, TAPSPERKCLK);\n reg [TAPCNTRWIDTH-1:0] rise_lead_center_offset_r, rise_trail_center_offset_r;\n always @(posedge clk) rise_lead_center_offset_r <= #TCQ rise_lead_center_offset_ns;\n always @(posedge clk) rise_trail_center_offset_r <= #TCQ rise_trail_center_offset_ns;\n\n wire [TAPCNTRWIDTH-1:0] edge_diff_ns = mod_sub(rise_trail_center_offset_r, rise_lead_center_offset_r, TAPSPERKCLK);\n reg [TAPCNTRWIDTH-1:0] edge_diff_r;\n always @(posedge clk) edge_diff_r <= #TCQ edge_diff_ns;\n \n wire [TAPCNTRWIDTH:0] edge_center_ns = center(rise_lead_center_offset_r, edge_diff_r, TAPSPERKCLK);\n reg [TAPCNTRWIDTH:0] edge_center_r;\n always @(posedge clk) edge_center_r <= #TCQ edge_center_ns;\n output [TAPCNTRWIDTH:0] edge_center;\n assign edge_center = edge_center_r;\n\n input use_noise_window;\n output [TAPCNTRWIDTH-1:0] left, right;\n assign left = use_noise_window ? rise_lead_left : rise_trail_left;\n assign right = use_noise_window ? rise_trail_right : rise_lead_right;\n\n wire [TAPCNTRWIDTH-1:0] center_diff_ns = mod_sub(right, left, TAPSPERKCLK);\n reg [TAPCNTRWIDTH-1:0] center_diff_r;\n always @(posedge clk) center_diff_r <= #TCQ center_diff_ns;\n \n wire [TAPCNTRWIDTH:0] window_center_ns = center(left, center_diff_r, TAPSPERKCLK);\n reg [TAPCNTRWIDTH:0] window_center_r;\n always @(posedge clk) window_center_r <= #TCQ window_center_ns;\n output [TAPCNTRWIDTH:0] window_center;\n assign window_center = window_center_r;\n\n localparam TAPSPERKCLKX2 = TAPSPERKCLK * 2;\n\n wire [TAPCNTRWIDTH+1:0] left_center = {1'b0, SCANFROMRIGHT == 1 ? window_center_r : edge_center_r};\n wire [TAPCNTRWIDTH+1:0] right_center = {1'b0, SCANFROMRIGHT == 1 ? edge_center_r : window_center_r};\n\t\t\t \n wire [TAPCNTRWIDTH+1:0] diff_ns = right_center >= left_center\n ? right_center - left_center\n : right_center + TAPSPERKCLKX2[TAPCNTRWIDTH+1:0] - left_center;\n \n reg [TAPCNTRWIDTH+1:0] diff_r;\n always @(posedge clk) diff_r <= #TCQ diff_ns;\n output [TAPCNTRWIDTH+1:0] diff;\n assign diff = diff_r;\n\n wire [TAPCNTRWIDTH+1:0] abs_diff = diff_r > TAPSPERKCLKX2[TAPCNTRWIDTH+1:0]/2\n ? TAPSPERKCLKX2[TAPCNTRWIDTH+1:0] - diff_r\n : diff_r;\n\n reg [TAPCNTRWIDTH+1:0] prev_ns, prev_r;\n always @(posedge clk) prev_r <= #TCQ prev_ns;\n always @(*) prev_ns = done_ns ? diff_r : prev_r;\n\n input ktap_at_right_edge;\n input ktap_at_left_edge;\n \n wire centering = !(ktap_at_right_edge || ktap_at_left_edge);\n wire diffs_eq = abs_diff == diff_r;\n reg diffs_eq_ns, diffs_eq_r;\n always @(*) diffs_eq_ns = centering && ((done_r && done_ns) ? diffs_eq : diffs_eq_r);\n always @(posedge clk) diffs_eq_r <= #TCQ diffs_eq_ns;\n\n reg edge_aligned_r;\n reg prev_valid_ns, prev_valid_r;\n always @(posedge clk) prev_valid_r <= #TCQ prev_valid_ns;\n always @(*) prev_valid_ns = (~rst && ~ktap_at_right_edge && ~ktap_at_left_edge && ~edge_aligned_r) && prev_valid_r | done_ns;\n\n wire indicate_alignment = ~rst && centering && done_ns;\n wire edge_aligned_ns = indicate_alignment && (~|diff_r || ~diffs_eq & diffs_eq_r);\n always @(posedge clk) edge_aligned_r <= #TCQ edge_aligned_ns;\n\n reg poc_backup_r;\n wire poc_backup_ns = edge_aligned_ns && abs_diff > prev_r;\n always @(posedge clk) poc_backup_r <= #TCQ poc_backup_ns;\n output poc_backup;\n assign poc_backup = poc_backup_r;\n\n output mmcm_lbclk_edge_aligned;\n assign mmcm_lbclk_edge_aligned = edge_aligned_r;\n \nendmodule // mig_7series_v4_0_poc_meta\n\n// Local Variables:\n// verilog-library-directories:(\".\")\n// verilog-library-extensions:(\".v\")\n// End:\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_pd.v", "content": "//*****************************************************************************\n// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor: Xilinx\n// \\ \\ \\/ Version:%version\n// \\ \\ Application: MIG\n// / / Filename: mig_7series_v4_0_poc_pd.v\n// /___/ /\\ Date Last Modified: $$\n// \\ \\ / \\ Date Created:Tue 15 Jan 2014\n// \\___\\/\\___\\\n//\n//Device: Virtex-7\n//Design Name: DDR3 SDRAM\n//Purpose: IDDR used as phase detector. The pos_edge and neg_edge stuff\n// prevents any noise that could happen when the phase shift clock is very\n// nearly aligned to the fabric clock.\n//Reference:\n//Revision History:\n//*****************************************************************************\n\n`timescale 1 ps / 1 ps\n\nmodule mig_7series_v4_0_poc_pd #\n (parameter POC_USE_METASTABLE_SAMP = \"FALSE\",\n parameter SIM_CAL_OPTION = \"NONE\",\n parameter TCQ = 100)\n (/*AUTOARG*/\n // Outputs\n pd_out,\n // Inputs\n iddr_rst, clk, kclk, mmcm_ps_clk\n );\n\n input iddr_rst;\n input clk;\n input kclk;\n input mmcm_ps_clk;\n\n wire q1;\n IDDR #\n (.DDR_CLK_EDGE (\"OPPOSITE_EDGE\"),\n .INIT_Q1 (1'b0),\n .INIT_Q2 (1'b0),\n .SRTYPE (\"SYNC\")) \n u_phase_detector \n (.Q1 (q1),\n .Q2 (),\n .C (mmcm_ps_clk),\n .CE (1'b1),\n .D (kclk),\n .R (iddr_rst),\n .S (1'b0));\n\n // Path from q1 to xxx_edge_samp must be constrained to be less than 1/4 cycle. FIXME\n\n reg pos_edge_samp;\n\n generate if (SIM_CAL_OPTION == \"NONE\" || POC_USE_METASTABLE_SAMP == \"TRUE\") begin : no_eXes\n always @(posedge clk) pos_edge_samp <= #TCQ q1;\n end else begin : eXes\n reg q1_delayed;\n reg rising_clk_seen;\n always @(posedge mmcm_ps_clk) begin\n rising_clk_seen <= 1'b0;\n q1_delayed <= 1'bx;\n end\n always @(posedge clk) begin\n rising_clk_seen = 1'b1;\n if (rising_clk_seen) q1_delayed <= q1;\n end\n always @(posedge clk) begin\n pos_edge_samp <= q1_delayed;\n end\n end endgenerate\n\n reg pd_out_r;\n always @(posedge clk) pd_out_r <= #TCQ pos_edge_samp;\n\n output pd_out;\n assign pd_out = pd_out_r;\n\n\nendmodule // mic_7series_v4_0_poc_pd\n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_tap_base.v", "content": "//*****************************************************************************\n// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor: Xilinx\n// \\ \\ \\/ Version:%version\n// \\ \\ Application: MIG\n// / / Filename: mig_7series_v4_0_poc_tap_base.v\n// /___/ /\\ Date Last Modified: $$\n// \\ \\ / \\ Date Created:Tue 15 Jan 2014\n// \\___\\/\\___\\\n//\n//Device: Virtex-7\n//Design Name: DDR3 SDRAM\n//Purpose: All your taps are belong to us.\n//\n//In general, this block should be able to start up with a random initialization of\n//the various counters. But its probably easier, more normative and quicker time to solution\n//to just initialize to zero with rst.\n//\n// Following deassertion of reset, endlessly increments the MMCM delay with PSEN. For\n// each MMCM tap it samples the phase detector output a programmable number of times. \n// When the sampling count is achieved, PSEN is pulsed and sampling of the next MMCM\n// tap begins.\n//\n// Following a PSEN, sampling pauses for MMCM_SAMP_WAIT clocks. This is workaround\n// for a bug in the MMCM where its output may have noise for a period following\n// the PSEN.\n//\n// Samples are taken every other fabric clock. This is because the MMCM phase shift\n// clock operates at half the fabric clock. The reason for this is unknown.\n//\n// At the end of the sampling period, a filtering step is implemented. samps_solid_thresh\n// is the minumum number of samples that must be seen to declare a solid zero or one. If\n// neithr the one and zero samples cross this threshold, then the sampple is declared fuzz.\n//\n// A \"run_polarity\" bit is maintained. It is set appropriately whenever a solid sample\n// is observed.\n//\n// A \"run\" counter is maintained. If the current sample is fuzz, or opposite polarity\n// from a previous sample, then the run counter is reset. If the current sample is the\n// same polarity run_polarity, then the run counter is incremented.\n//\n// If a run_polarity reversal or fuzz is observed and the run counter is not zero\n// then the run_end strobe is pulsed.\n// \n//Reference:\n//Revision History:\n//*****************************************************************************\n\n`timescale 1 ps / 1 ps\n\nmodule mig_7series_v4_0_poc_tap_base #\n (parameter MMCM_SAMP_WAIT = 10,\n parameter POC_USE_METASTABLE_SAMP = \"FALSE\",\n parameter TCQ = 100,\n parameter SAMPCNTRWIDTH = 8,\n parameter SMWIDTH = 2,\n parameter TAPCNTRWIDTH = 7,\n parameter TAPSPERKCLK = 112)\n (/*AUTOARG*/\n // Outputs\n psincdec, psen, run, run_end, run_too_small, run_polarity,\n samp_cntr, samps_hi, samps_hi_held, tap, sm, samps_zero, samps_one,\n // Inputs\n pd_out, clk, samples, samps_solid_thresh, psdone, rst,\n poc_sample_pd\n );\n\n \n function integer clogb2 (input integer size); // ceiling logb2\n begin\n size = size - 1;\n for (clogb2=1; size>1; clogb2=clogb2+1)\n size = size >> 1;\n end\n endfunction // clogb2\n \n input pd_out;\n input clk;\n input [SAMPCNTRWIDTH:0] samples, samps_solid_thresh;\n input psdone;\n input rst;\n\n localparam ONE = 1;\n\n localparam SAMP_WAIT_WIDTH = clogb2(MMCM_SAMP_WAIT);\n reg [SAMP_WAIT_WIDTH-1:0] samp_wait_ns, samp_wait_r;\n always @(posedge clk) samp_wait_r <= #TCQ samp_wait_ns;\n\n reg pd_out_r;\n always @(posedge clk) pd_out_r <= #TCQ pd_out;\n wire pd_out_sel = POC_USE_METASTABLE_SAMP == \"TRUE\" ? pd_out_r : pd_out;\n\n output psincdec;\n assign psincdec = 1'b1;\n output psen;\n reg psen_int;\n assign psen = psen_int;\n \n reg [TAPCNTRWIDTH-1:0] run_r;\n reg [TAPCNTRWIDTH-1:0] run_ns;\n always @(posedge clk) run_r <= #TCQ run_ns;\n output [TAPCNTRWIDTH-1:0] run;\n assign run = run_r;\n\n output run_end;\n reg run_end_int;\n assign run_end = run_end_int;\n\n output run_too_small;\n reg run_too_small_r, run_too_small_ns;\n always @(*) run_too_small_ns = run_end && (run < TAPSPERKCLK/4);\n always @(posedge clk) run_too_small_r <= #TCQ run_too_small_ns;\n assign run_too_small = run_too_small_r;\n \n reg run_polarity_r;\n reg run_polarity_ns;\n always @(posedge clk) run_polarity_r <= #TCQ run_polarity_ns;\n output run_polarity;\n assign run_polarity = run_polarity_r;\n\n reg [SAMPCNTRWIDTH-1:0] samp_cntr_r;\n reg [SAMPCNTRWIDTH-1:0] samp_cntr_ns;\n always @(posedge clk) samp_cntr_r <= #TCQ samp_cntr_ns;\n output [SAMPCNTRWIDTH-1:0] samp_cntr;\n assign samp_cntr = samp_cntr_r;\n\n reg [SAMPCNTRWIDTH:0] samps_hi_r;\n reg [SAMPCNTRWIDTH:0] samps_hi_ns;\n always @(posedge clk) samps_hi_r <= #TCQ samps_hi_ns;\n output [SAMPCNTRWIDTH:0] samps_hi;\n assign samps_hi = samps_hi_r;\n\n reg [SAMPCNTRWIDTH:0] samps_hi_held_r;\n reg [SAMPCNTRWIDTH:0] samps_hi_held_ns;\n always @(posedge clk) samps_hi_held_r <= #TCQ samps_hi_held_ns;\n output [SAMPCNTRWIDTH:0] samps_hi_held;\n assign samps_hi_held = samps_hi_held_r;\n\n reg [TAPCNTRWIDTH-1:0] tap_ns, tap_r;\n always @(posedge clk) tap_r <= #TCQ tap_ns;\n output [TAPCNTRWIDTH-1:0] tap;\n assign tap = tap_r;\n \n reg [SMWIDTH-1:0] sm_ns;\n reg [SMWIDTH-1:0] sm_r;\n always @(posedge clk) sm_r <= #TCQ sm_ns;\n output [SMWIDTH-1:0] sm;\n assign sm = sm_r;\n\n reg samps_zero_ns, samps_zero_r, samps_one_ns, samps_one_r;\n always @(posedge clk) samps_zero_r <= #TCQ samps_zero_ns;\n always @(posedge clk) samps_one_r <= #TCQ samps_one_ns;\n output samps_zero, samps_one;\n assign samps_zero = samps_zero_r;\n assign samps_one = samps_one_r;\n\n // Interesting corner case... what if both samps_zero and samps_one are\n // hi? Could happen for small sample counts and reasonable values of\n // PCT_SAMPS_SOLID. Doesn't affect samps_solid. run_polarity assignment\n // consistently breaks tie with samps_one_r.\n wire [SAMPCNTRWIDTH:0] samps_lo = samples + ONE[SAMPCNTRWIDTH:0] - samps_hi_r;\n always @(*) begin\n samps_zero_ns = samps_zero_r;\n samps_one_ns = samps_one_r;\n samps_zero_ns = samps_lo >= samps_solid_thresh;\n samps_one_ns = samps_hi_r >= samps_solid_thresh;\n end // always @ begin\n wire new_polarity = run_polarity_ns ^ run_polarity_r;\n\n input poc_sample_pd;\n\n always @(*) begin\n \n if (rst == 1'b1) begin\n \n // RESET next states\n psen_int = 1'b0;\n sm_ns = /*AUTOLINK(\"SAMPLE\")*/2'd0;\n run_polarity_ns = 1'b0;\n run_ns = {TAPCNTRWIDTH{1'b0}};\n run_end_int = 1'b0;\n samp_cntr_ns = {SAMPCNTRWIDTH{1'b0}};\n samps_hi_ns = {SAMPCNTRWIDTH+1{1'b0}};\n tap_ns = {TAPCNTRWIDTH{1'b0}};\n samp_wait_ns = MMCM_SAMP_WAIT[SAMP_WAIT_WIDTH-1:0];\n samps_hi_held_ns = {SAMPCNTRWIDTH+1{1'b0}};\n end else begin\n\n // Default next states;\n psen_int = 1'b0;\n sm_ns = sm_r;\n run_polarity_ns = run_polarity_r;\n run_ns = run_r;\n run_end_int = 1'b0;\n samp_cntr_ns = samp_cntr_r;\n samps_hi_ns = samps_hi_r;\n tap_ns = tap_r;\n samp_wait_ns = samp_wait_r;\n if (|samp_wait_r) samp_wait_ns = samp_wait_r - ONE[SAMP_WAIT_WIDTH-1:0];\n samps_hi_held_ns = samps_hi_held_r;\n\n// State based actions and next states. \n case (sm_r)\n /*AL(\"SAMPLE\")*/2'd0: begin\n\t if (~|samp_wait_r && poc_sample_pd | POC_USE_METASTABLE_SAMP == \"TRUE\") begin\n\t if (POC_USE_METASTABLE_SAMP == \"TRUE\") samp_wait_ns = ONE[SAMP_WAIT_WIDTH-1:0];\n\t if ({1'b0, samp_cntr_r} == samples) sm_ns = /*AK(\"COMPUTE\")*/2'd1;\n\t samps_hi_ns = samps_hi_r + {{SAMPCNTRWIDTH{1'b0}}, pd_out_sel};\n\t samp_cntr_ns = samp_cntr_r + ONE[SAMPCNTRWIDTH-1:0];\n\t end\n end\n\t\n\t/*AL(\"COMPUTE\")*/2'd1:begin\n\t sm_ns = /*AK(\"PSEN\")*/2'd2;\n end\n\n /*AL(\"PSEN\")*/2'd2:begin\n\t sm_ns = /*AK(\"PSDONE_WAIT\")*/2'd3;\n\t psen_int = 1'b1;\n\t samp_cntr_ns = {SAMPCNTRWIDTH{1'b0}};\n\t samps_hi_ns = {SAMPCNTRWIDTH+1{1'b0}};\n\t samps_hi_held_ns = samps_hi_r;\n\t tap_ns = (tap_r < TAPSPERKCLK[TAPCNTRWIDTH-1:0] - ONE[TAPCNTRWIDTH-1:0])\n\t ? tap_r + ONE[TAPCNTRWIDTH-1:0]\n\t\t : {TAPCNTRWIDTH{1'b0}};\n\n\t if (run_polarity_r) begin\n\t if (samps_zero_r) run_polarity_ns = 1'b0;\n\t end else begin\n\t if (samps_one_r) run_polarity_ns = 1'b1;\n\t end\n\t if (new_polarity) begin\n run_ns ={TAPCNTRWIDTH{1'b0}};\n\t run_end_int = 1'b1;\n\t end else run_ns = run_r + ONE[TAPCNTRWIDTH-1:0];\n end\n\n /*AL(\"PSDONE_WAIT\")*/2'd3:begin\n\t samp_wait_ns = MMCM_SAMP_WAIT[SAMP_WAIT_WIDTH-1:0] - ONE[SAMP_WAIT_WIDTH-1:0];\n\t if (psdone) sm_ns = /*AK(\"SAMPLE\")*/2'd0;\n end\n\t\n endcase // case (sm_r)\n end // else: !if(rst == 1'b1)\n end // always @ (*)\n\nendmodule // mig_7series_v4_0_poc_tap_base\n\n// Local Variables:\n// verilog-library-directories:(\".\")\n// verilog-library-extensions:(\".v\")\n// verilog-autolabel-prefix: \"2'd\"\n// End:\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/phy/mig_7series_v4_0_poc_top.v", "content": "//*****************************************************************************\n// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor: Xilinx\n// \\ \\ \\/ Version:%version\n// \\ \\ Application: MIG\n// / / Filename: mig_7series_v4_0_poc_top.v\n// /___/ /\\ Date Last Modified: $$\n// \\ \\ / \\ Date Created:Tue 15 Jan 2014\n// \\___\\/\\___\\\n//\n//Device: Virtex-7\n//Design Name: DDR3 SDRAM\n//Purpose: Phaser out calibration top.\n//Reference:\n//Revision History:\n//*****************************************************************************\n\n`timescale 1 ps / 1 ps\n\nmodule mig_7series_v4_0_poc_top #\n (parameter LANE_CNT_WIDTH = 2,\n parameter MMCM_SAMP_WAIT = 10,\n parameter PCT_SAMPS_SOLID = 95,\n parameter POC_USE_METASTABLE_SAMP = \"FALSE\",\n parameter TCQ = 100,\n parameter CCENABLE = 0,\n parameter SCANFROMRIGHT = 0,\n parameter SAMPCNTRWIDTH = 8,\n parameter SAMPLES = 128,\n parameter TAPCNTRWIDTH = 7,\n parameter TAPSPERKCLK\t\t=112)\n (/*AUTOARG*/\n // Outputs\n psincdec, poc_error, dbg_poc, psen, rise_lead_right,\n rise_trail_right, mmcm_edge_detect_done, mmcm_lbclk_edge_aligned,\n poc_backup,\n // Inputs\n use_noise_window, rst, psdone, poc_sample_pd, pd_out,\n ninety_offsets, mmcm_edge_detect_rdy, lane, ktap_at_right_edge,\n ktap_at_left_edge, clk\n );\n\n localparam SMWIDTH = 2;\n \n /*AUTOINPUT*/\n // Beginning of automatic inputs (from unused autoinst inputs)\n input\t\t\tclk;\t\t\t// To u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v, ...\n input\t\t\tktap_at_left_edge;\t// To u_poc_meta of mig_7series_v4_0_poc_meta.v, ...\n input\t\t\tktap_at_right_edge;\t// To u_poc_meta of mig_7series_v4_0_poc_meta.v, ...\n input [LANE_CNT_WIDTH-1:0] lane;\t\t// To u_poc_cc of mig_7series_v4_0_poc_cc.v\n input\t\t\tmmcm_edge_detect_rdy;\t// To u_poc_meta of mig_7series_v4_0_poc_meta.v, ...\n input [1:0]\t\tninety_offsets;\t\t// To u_poc_meta of mig_7series_v4_0_poc_meta.v\n input\t\t\tpd_out;\t\t\t// To u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v\n input\t\t\tpoc_sample_pd;\t\t// To u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v\n input\t\t\tpsdone;\t\t\t// To u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v\n input\t\t\trst;\t\t\t// To u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v, ...\n input\t\t\tuse_noise_window;\t// To u_poc_meta of mig_7series_v4_0_poc_meta.v\n // End of automatics\n /*AUTOOUTPUT*/\n // Beginning of automatic outputs (from unused autoinst outputs)\n output [1023:0]\tdbg_poc;\t\t// From u_poc_cc of mig_7series_v4_0_poc_cc.v\n output\t\tpoc_error;\t\t// From u_poc_cc of mig_7series_v4_0_poc_cc.v\n output\t\tpsincdec;\t\t// From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v\n // End of automatics\n /*AUTOwire*/\n // Beginning of automatic wires (for undeclared instantiated-module outputs)\n wire [TAPCNTRWIDTH+1:0] diff;\t\t\t// From u_poc_meta of mig_7series_v4_0_poc_meta.v\n wire [TAPCNTRWIDTH:0]\tedge_center;\t\t// From u_poc_meta of mig_7series_v4_0_poc_meta.v\n wire [TAPCNTRWIDTH-1:0] fall_lead_center;\t// From u_edge_center of mig_7series_v4_0_poc_edge_store.v\n wire [TAPCNTRWIDTH-1:0] fall_lead_left;\t// From u_edge_left of mig_7series_v4_0_poc_edge_store.v\n wire [TAPCNTRWIDTH-1:0] fall_lead_right;\t// From u_edge_right of mig_7series_v4_0_poc_edge_store.v\n wire [TAPCNTRWIDTH-1:0] fall_trail_center;\t// From u_edge_center of mig_7series_v4_0_poc_edge_store.v\n wire [TAPCNTRWIDTH-1:0] fall_trail_left;\t// From u_edge_left of mig_7series_v4_0_poc_edge_store.v\n wire [TAPCNTRWIDTH-1:0] fall_trail_right;\t// From u_edge_right of mig_7series_v4_0_poc_edge_store.v\n wire [TAPCNTRWIDTH-1:0] left;\t\t\t// From u_poc_meta of mig_7series_v4_0_poc_meta.v\n wire [TAPCNTRWIDTH-1:0] right;\t\t// From u_poc_meta of mig_7series_v4_0_poc_meta.v\n wire [TAPCNTRWIDTH-1:0] rise_lead_center;\t// From u_edge_center of mig_7series_v4_0_poc_edge_store.v\n wire [TAPCNTRWIDTH-1:0] rise_lead_left;\t// From u_edge_left of mig_7series_v4_0_poc_edge_store.v\n wire [TAPCNTRWIDTH-1:0] rise_trail_center;\t// From u_edge_center of mig_7series_v4_0_poc_edge_store.v\n wire [TAPCNTRWIDTH-1:0] rise_trail_left;\t// From u_edge_left of mig_7series_v4_0_poc_edge_store.v\n wire [TAPCNTRWIDTH-1:0] run;\t\t\t// From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v\n wire\t\t\trun_end;\t\t// From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v\n wire [1:0]\t\trun_ends;\t\t// From u_poc_meta of mig_7series_v4_0_poc_meta.v\n wire\t\t\trun_polarity;\t\t// From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v\n wire\t\t\trun_too_small;\t\t// From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v\n wire [SAMPCNTRWIDTH-1:0] samp_cntr;\t\t// From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v\n wire [SAMPCNTRWIDTH:0] samples;\t\t// From u_poc_cc of mig_7series_v4_0_poc_cc.v\n wire [SAMPCNTRWIDTH:0] samps_hi;\t\t// From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v\n wire [SAMPCNTRWIDTH:0] samps_hi_held;\t\t// From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v\n wire\t\t\tsamps_one;\t\t// From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v\n wire [SAMPCNTRWIDTH:0] samps_solid_thresh;\t// From u_poc_cc of mig_7series_v4_0_poc_cc.v\n wire\t\t\tsamps_zero;\t\t// From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v\n wire [SMWIDTH-1:0]\tsm;\t\t\t// From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v\n wire [TAPCNTRWIDTH-1:0] tap;\t\t\t// From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v\n wire [TAPCNTRWIDTH:0]\twindow_center;\t\t// From u_poc_meta of mig_7series_v4_0_poc_meta.v\n // End of automatics\n\n output psen;\n output [TAPCNTRWIDTH-1:0] rise_lead_right;\n output [TAPCNTRWIDTH-1:0] rise_trail_right;\n output mmcm_edge_detect_done;\n output mmcm_lbclk_edge_aligned;\n output poc_backup;\n\n mig_7series_v4_0_poc_tap_base #\n (/*AUTOINSTPARAM*/\n // Parameters\n .MMCM_SAMP_WAIT\t\t\t(MMCM_SAMP_WAIT),\n .POC_USE_METASTABLE_SAMP\t\t(POC_USE_METASTABLE_SAMP),\n .SAMPCNTRWIDTH\t\t\t(SAMPCNTRWIDTH),\n .SMWIDTH\t\t\t\t(SMWIDTH),\n .TAPCNTRWIDTH\t\t\t(TAPCNTRWIDTH),\n .TAPSPERKCLK\t\t\t(TAPSPERKCLK),\n .TCQ\t\t\t\t(TCQ))\n u_poc_tap_base\n (/*AUTOINST*/\n // Outputs\n .psen\t\t\t\t(psen),\n .psincdec\t\t\t\t(psincdec),\n .run\t\t\t\t(run[TAPCNTRWIDTH-1:0]),\n .run_end\t\t\t\t(run_end),\n .run_polarity\t\t\t(run_polarity),\n .run_too_small\t\t\t(run_too_small),\n .samp_cntr\t\t\t\t(samp_cntr[SAMPCNTRWIDTH-1:0]),\n .samps_hi\t\t\t\t(samps_hi[SAMPCNTRWIDTH:0]),\n .samps_hi_held\t\t\t(samps_hi_held[SAMPCNTRWIDTH:0]),\n .samps_one\t\t\t\t(samps_one),\n .samps_zero\t\t\t(samps_zero),\n .sm\t\t\t\t(sm[SMWIDTH-1:0]),\n .tap\t\t\t\t(tap[TAPCNTRWIDTH-1:0]),\n // Inputs\n .clk\t\t\t\t(clk),\n .pd_out\t\t\t\t(pd_out),\n .poc_sample_pd\t\t\t(poc_sample_pd),\n .psdone\t\t\t\t(psdone),\n .rst\t\t\t\t(rst),\n .samples\t\t\t\t(samples[SAMPCNTRWIDTH:0]),\n .samps_solid_thresh\t\t(samps_solid_thresh[SAMPCNTRWIDTH:0]));\n\n mig_7series_v4_0_poc_meta #\n (/*AUTOINSTPARAM*/\n // Parameters\n .SCANFROMRIGHT\t\t\t(SCANFROMRIGHT),\n .TAPCNTRWIDTH\t\t\t(TAPCNTRWIDTH),\n .TAPSPERKCLK\t\t\t(TAPSPERKCLK),\n .TCQ\t\t\t\t(TCQ))\n u_poc_meta\n (/*AUTOINST*/\n // Outputs\n .diff\t\t\t\t(diff[TAPCNTRWIDTH+1:0]),\n .edge_center\t\t\t(edge_center[TAPCNTRWIDTH:0]),\n .left\t\t\t\t(left[TAPCNTRWIDTH-1:0]),\n .mmcm_edge_detect_done\t\t(mmcm_edge_detect_done),\n .mmcm_lbclk_edge_aligned\t\t(mmcm_lbclk_edge_aligned),\n .poc_backup\t\t\t(poc_backup),\n .right\t\t\t\t(right[TAPCNTRWIDTH-1:0]),\n .run_ends\t\t\t\t(run_ends[1:0]),\n .window_center\t\t\t(window_center[TAPCNTRWIDTH:0]),\n // Inputs\n .clk\t\t\t\t(clk),\n .ktap_at_left_edge\t\t\t(ktap_at_left_edge),\n .ktap_at_right_edge\t\t(ktap_at_right_edge),\n .mmcm_edge_detect_rdy\t\t(mmcm_edge_detect_rdy),\n .ninety_offsets\t\t\t(ninety_offsets[1:0]),\n .rise_lead_center\t\t\t(rise_lead_center[TAPCNTRWIDTH-1:0]),\n .rise_lead_left\t\t\t(rise_lead_left[TAPCNTRWIDTH-1:0]),\n .rise_lead_right\t\t\t(rise_lead_right[TAPCNTRWIDTH-1:0]),\n .rise_trail_center\t\t\t(rise_trail_center[TAPCNTRWIDTH-1:0]),\n .rise_trail_left\t\t\t(rise_trail_left[TAPCNTRWIDTH-1:0]),\n .rise_trail_right\t\t\t(rise_trail_right[TAPCNTRWIDTH-1:0]),\n .rst\t\t\t\t(rst),\n .run\t\t\t\t(run[TAPCNTRWIDTH-1:0]),\n .run_end\t\t\t\t(run_end),\n .run_polarity\t\t\t(run_polarity),\n .run_too_small\t\t\t(run_too_small),\n .use_noise_window\t\t\t(use_noise_window));\n\n /*mig_7series_v4_0_poc_edge_store AUTO_TEMPLATE \"edge_\\(.*\\)$\" (\n .\\(.*\\)lead (\\1lead_@@\"vl-bits\"),\n .\\(.*\\)trail (\\1trail_@@\"vl-bits\"),\n .select0 (ktap_at_@_edge),\n .select1 (1'b1),)*/\n \n mig_7series_v4_0_poc_edge_store #\n (/*AUTOINSTPARAM*/\n // Parameters\n .TAPCNTRWIDTH\t\t\t(TAPCNTRWIDTH),\n .TAPSPERKCLK\t\t\t(TAPSPERKCLK),\n .TCQ\t\t\t\t(TCQ))\n u_edge_right\n (/*AUTOINST*/\n // Outputs\n .fall_lead\t\t\t\t(fall_lead_right[TAPCNTRWIDTH-1:0]), // Templated\n .fall_trail\t\t\t(fall_trail_right[TAPCNTRWIDTH-1:0]), // Templated\n .rise_lead\t\t\t\t(rise_lead_right[TAPCNTRWIDTH-1:0]), // Templated\n .rise_trail\t\t\t(rise_trail_right[TAPCNTRWIDTH-1:0]), // Templated\n // Inputs\n .clk\t\t\t\t(clk),\n .run\t\t\t\t(run[TAPCNTRWIDTH-1:0]),\n .run_end\t\t\t\t(run_end),\n .run_polarity\t\t\t(run_polarity),\n .select0\t\t\t\t(ktap_at_right_edge),\t // Templated\n .select1\t\t\t\t(1'b1),\t\t\t // Templated\n .tap\t\t\t\t(tap[TAPCNTRWIDTH-1:0]));\n\n mig_7series_v4_0_poc_edge_store #\n (/*AUTOINSTPARAM*/\n // Parameters\n .TAPCNTRWIDTH\t\t\t(TAPCNTRWIDTH),\n .TAPSPERKCLK\t\t\t(TAPSPERKCLK),\n .TCQ\t\t\t\t(TCQ))\n u_edge_left\n (/*AUTOINST*/\n // Outputs\n .fall_lead\t\t\t\t(fall_lead_left[TAPCNTRWIDTH-1:0]), // Templated\n .fall_trail\t\t\t(fall_trail_left[TAPCNTRWIDTH-1:0]), // Templated\n .rise_lead\t\t\t\t(rise_lead_left[TAPCNTRWIDTH-1:0]), // Templated\n .rise_trail\t\t\t(rise_trail_left[TAPCNTRWIDTH-1:0]), // Templated\n // Inputs\n .clk\t\t\t\t(clk),\n .run\t\t\t\t(run[TAPCNTRWIDTH-1:0]),\n .run_end\t\t\t\t(run_end),\n .run_polarity\t\t\t(run_polarity),\n .select0\t\t\t\t(ktap_at_left_edge),\t // Templated\n .select1\t\t\t\t(1'b1),\t\t\t // Templated\n .tap\t\t\t\t(tap[TAPCNTRWIDTH-1:0]));\n\n wire not_ktap_at_right_edge = ~ktap_at_right_edge;\n wire not_ktap_at_left_edge = ~ktap_at_left_edge;\n /*mig_7series_v4_0_poc_edge_store AUTO_TEMPLATE \"edge_\\(.*\\)$\" (\n .\\(.*\\)lead (\\1lead_@@\"vl-bits\"),\n .\\(.*\\)trail (\\1trail_@@\"vl-bits\"),\n .select0 (not_ktap_at_right_edge),\n .select1 (not_ktap_at_left_edge),)*/\n\n mig_7series_v4_0_poc_edge_store #\n (/*AUTOINSTPARAM*/\n // Parameters\n .TAPCNTRWIDTH\t\t\t(TAPCNTRWIDTH),\n .TAPSPERKCLK\t\t\t(TAPSPERKCLK),\n .TCQ\t\t\t\t(TCQ))\n u_edge_center\n (/*AUTOINST*/\n // Outputs\n .fall_lead\t\t\t\t(fall_lead_center[TAPCNTRWIDTH-1:0]), // Templated\n .fall_trail\t\t\t(fall_trail_center[TAPCNTRWIDTH-1:0]), // Templated\n .rise_lead\t\t\t\t(rise_lead_center[TAPCNTRWIDTH-1:0]), // Templated\n .rise_trail\t\t\t(rise_trail_center[TAPCNTRWIDTH-1:0]), // Templated\n // Inputs\n .clk\t\t\t\t(clk),\n .run\t\t\t\t(run[TAPCNTRWIDTH-1:0]),\n .run_end\t\t\t\t(run_end),\n .run_polarity\t\t\t(run_polarity),\n .select0\t\t\t\t(not_ktap_at_right_edge), // Templated\n .select1\t\t\t\t(not_ktap_at_left_edge), // Templated\n .tap\t\t\t\t(tap[TAPCNTRWIDTH-1:0]));\n\n mig_7series_v4_0_poc_cc #\n (/*AUTOINSTPARAM*/\n // Parameters\n .CCENABLE\t\t\t\t(CCENABLE),\n .LANE_CNT_WIDTH\t\t\t(LANE_CNT_WIDTH),\n .PCT_SAMPS_SOLID\t\t\t(PCT_SAMPS_SOLID),\n .SAMPCNTRWIDTH\t\t\t(SAMPCNTRWIDTH),\n .SAMPLES\t\t\t\t(SAMPLES),\n .SMWIDTH\t\t\t\t(SMWIDTH),\n .TAPCNTRWIDTH\t\t\t(TAPCNTRWIDTH),\n .TCQ\t\t\t\t(TCQ))\n u_poc_cc\n (/*AUTOINST*/\n // Outputs\n .dbg_poc\t\t\t\t(dbg_poc[1023:0]),\n .poc_error\t\t\t\t(poc_error),\n .samples\t\t\t\t(samples[SAMPCNTRWIDTH:0]),\n .samps_solid_thresh\t\t(samps_solid_thresh[SAMPCNTRWIDTH:0]),\n // Inputs\n .clk\t\t\t\t(clk),\n .diff\t\t\t\t(diff[TAPCNTRWIDTH+1:0]),\n .edge_center\t\t\t(edge_center[TAPCNTRWIDTH:0]),\n .fall_lead_center\t\t\t(fall_lead_center[TAPCNTRWIDTH-1:0]),\n .fall_lead_left\t\t\t(fall_lead_left[TAPCNTRWIDTH-1:0]),\n .fall_lead_right\t\t\t(fall_lead_right[TAPCNTRWIDTH-1:0]),\n .fall_trail_center\t\t\t(fall_trail_center[TAPCNTRWIDTH-1:0]),\n .fall_trail_left\t\t\t(fall_trail_left[TAPCNTRWIDTH-1:0]),\n .fall_trail_right\t\t\t(fall_trail_right[TAPCNTRWIDTH-1:0]),\n .ktap_at_left_edge\t\t\t(ktap_at_left_edge),\n .ktap_at_right_edge\t\t(ktap_at_right_edge),\n .lane\t\t\t\t(lane[LANE_CNT_WIDTH-1:0]),\n .left\t\t\t\t(left[TAPCNTRWIDTH-1:0]),\n .mmcm_edge_detect_done\t\t(mmcm_edge_detect_done),\n .mmcm_edge_detect_rdy\t\t(mmcm_edge_detect_rdy),\n .mmcm_lbclk_edge_aligned\t\t(mmcm_lbclk_edge_aligned),\n .poc_backup\t\t\t(poc_backup),\n .psen\t\t\t\t(psen),\n .right\t\t\t\t(right[TAPCNTRWIDTH-1:0]),\n .rise_lead_center\t\t\t(rise_lead_center[TAPCNTRWIDTH-1:0]),\n .rise_lead_left\t\t\t(rise_lead_left[TAPCNTRWIDTH-1:0]),\n .rise_lead_right\t\t\t(rise_lead_right[TAPCNTRWIDTH-1:0]),\n .rise_trail_center\t\t\t(rise_trail_center[TAPCNTRWIDTH-1:0]),\n .rise_trail_left\t\t\t(rise_trail_left[TAPCNTRWIDTH-1:0]),\n .rise_trail_right\t\t\t(rise_trail_right[TAPCNTRWIDTH-1:0]),\n .rst\t\t\t\t(rst),\n .run\t\t\t\t(run[TAPCNTRWIDTH-1:0]),\n .run_end\t\t\t\t(run_end),\n .run_ends\t\t\t\t(run_ends[1:0]),\n .run_polarity\t\t\t(run_polarity),\n .run_too_small\t\t\t(run_too_small),\n .samp_cntr\t\t\t\t(samp_cntr[SAMPCNTRWIDTH-1:0]),\n .samps_hi\t\t\t\t(samps_hi[SAMPCNTRWIDTH:0]),\n .samps_hi_held\t\t\t(samps_hi_held[SAMPCNTRWIDTH:0]),\n .samps_one\t\t\t\t(samps_one),\n .samps_zero\t\t\t(samps_zero),\n .sm\t\t\t\t(sm[SMWIDTH-1:0]),\n .tap\t\t\t\t(tap[TAPCNTRWIDTH-1:0]),\n .window_center\t\t\t(window_center[TAPCNTRWIDTH:0]));\n\nendmodule // mig_7series_v4_0_poc_top\n\n// Local Variables:\n// verilog-library-directories:(\".\")\n// verilog-library-extensions:(\".v\")\n// End:\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ui/mig_7series_v4_0_ui_cmd.v", "content": "//*****************************************************************************\n// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor : Xilinx\n// \\ \\ \\/ Version : %version\n// \\ \\ Application : MIG\n// / / Filename : ui_cmd.v\n// /___/ /\\ Date Last Modified : $date$\n// \\ \\ / \\ Date Created : Tue Jun 30 2009\n// \\___\\/\\___\\\n//\n//Device : 7-Series\n//Design Name : DDR3 SDRAM\n//Purpose :\n//Reference :\n//Revision History :\n//*****************************************************************************\n\n`timescale 1 ps / 1 ps\n\n// User interface command port.\n\nmodule mig_7series_v4_0_ui_cmd #\n (\n parameter TCQ = 100,\n parameter ADDR_WIDTH = 33,\n parameter BANK_WIDTH = 3,\n parameter COL_WIDTH = 12,\n parameter DATA_BUF_ADDR_WIDTH = 5,\n parameter RANK_WIDTH = 2,\n parameter ROW_WIDTH = 16,\n parameter RANKS = 4,\n parameter MEM_ADDR_ORDER = \"BANK_ROW_COLUMN\"\n )\n (/*AUTOARG*/\n // Outputs\n app_rdy, use_addr, rank, bank, row, col, size, cmd, hi_priority,\n rd_accepted, wr_accepted, data_buf_addr,\n // Inputs\n rst, clk, accept_ns, rd_buf_full, wr_req_16, app_addr, app_cmd,\n app_sz, app_hi_pri, app_en, wr_data_buf_addr, rd_data_buf_addr_r\n );\n\n input rst;\n input clk;\n\n input accept_ns;\n input rd_buf_full;\n input wr_req_16;\n wire app_rdy_ns = accept_ns && ~rd_buf_full && ~wr_req_16;\n reg app_rdy_r = 1'b0 /* synthesis syn_maxfan = 10 */;\n always @(posedge clk) app_rdy_r <= #TCQ app_rdy_ns;\n output wire app_rdy;\n assign app_rdy = app_rdy_r;\n\n input [ADDR_WIDTH-1:0] app_addr;\n input [2:0] app_cmd;\n input app_sz;\n input app_hi_pri;\n input app_en;\n\n reg [ADDR_WIDTH-1:0] app_addr_r1 = {ADDR_WIDTH{1'b0}};\n reg [ADDR_WIDTH-1:0] app_addr_r2 = {ADDR_WIDTH{1'b0}};\n reg [2:0] app_cmd_r1;\n reg [2:0] app_cmd_r2;\n reg app_sz_r1;\n reg app_sz_r2;\n reg app_hi_pri_r1;\n reg app_hi_pri_r2;\n reg app_en_r1;\n reg app_en_r2;\n\n wire [ADDR_WIDTH-1:0] app_addr_ns1 = app_rdy_r && app_en ? app_addr : app_addr_r1;\n wire [ADDR_WIDTH-1:0] app_addr_ns2 = app_rdy_r ? app_addr_r1 : app_addr_r2;\n wire [2:0] app_cmd_ns1 = app_rdy_r ? app_cmd : app_cmd_r1;\n wire [2:0] app_cmd_ns2 = app_rdy_r ? app_cmd_r1 : app_cmd_r2;\n wire app_sz_ns1 = app_rdy_r ? app_sz : app_sz_r1;\n wire app_sz_ns2 = app_rdy_r ? app_sz_r1 : app_sz_r2;\n wire app_hi_pri_ns1 = app_rdy_r ? app_hi_pri : app_hi_pri_r1;\n wire app_hi_pri_ns2 = app_rdy_r ? app_hi_pri_r1 : app_hi_pri_r2;\n wire app_en_ns1 = ~rst && (app_rdy_r ? app_en : app_en_r1);\n wire app_en_ns2 = ~rst && (app_rdy_r ? app_en_r1 : app_en_r2);\n\n always @(posedge clk) begin\n if (rst) begin\n app_addr_r1 <= #TCQ {ADDR_WIDTH{1'b0}};\n app_addr_r2 <= #TCQ {ADDR_WIDTH{1'b0}};\n end else begin\n app_addr_r1 <= #TCQ app_addr_ns1;\n app_addr_r2 <= #TCQ app_addr_ns2;\n end \n app_cmd_r1 <= #TCQ app_cmd_ns1;\n app_cmd_r2 <= #TCQ app_cmd_ns2;\n app_sz_r1 <= #TCQ app_sz_ns1;\n app_sz_r2 <= #TCQ app_sz_ns2;\n app_hi_pri_r1 <= #TCQ app_hi_pri_ns1;\n app_hi_pri_r2 <= #TCQ app_hi_pri_ns2;\n app_en_r1 <= #TCQ app_en_ns1;\n app_en_r2 <= #TCQ app_en_ns2;\n end // always @ (posedge clk)\n\n wire use_addr_lcl = app_en_r2 && app_rdy_r;\n output wire use_addr;\n assign use_addr = use_addr_lcl;\n\n output wire [RANK_WIDTH-1:0] rank;\n output wire [BANK_WIDTH-1:0] bank;\n output wire [ROW_WIDTH-1:0] row;\n output wire [COL_WIDTH-1:0] col;\n output wire size;\n output wire [2:0] cmd;\n output wire hi_priority;\n\n/* assign col = app_rdy_r\n ? app_addr_r1[0+:COL_WIDTH]\n : app_addr_r2[0+:COL_WIDTH];*/\n generate\n begin\n if (MEM_ADDR_ORDER == \"TG_TEST\")\n begin\n assign col[4:0] = app_rdy_r\n ? app_addr_r1[0+:5]\n : app_addr_r2[0+:5];\n\n if (RANKS==1)\n begin\n assign col[COL_WIDTH-1:COL_WIDTH-2] = app_rdy_r\n ? app_addr_r1[5+3+BANK_WIDTH+:2]\n : app_addr_r2[5+3+BANK_WIDTH+:2];\n assign col[COL_WIDTH-3:5] = app_rdy_r\n ? app_addr_r1[5+3+BANK_WIDTH+2+2+:COL_WIDTH-7]\n : app_addr_r2[5+3+BANK_WIDTH+2+2+:COL_WIDTH-7];\n end\n else\n begin\n assign col[COL_WIDTH-1:COL_WIDTH-2] = app_rdy_r\n ? app_addr_r1[5+3+BANK_WIDTH+RANK_WIDTH+:2]\n : app_addr_r2[5+3+BANK_WIDTH+RANK_WIDTH+:2];\n assign col[COL_WIDTH-3:5] = app_rdy_r\n ? app_addr_r1[5+3+BANK_WIDTH+RANK_WIDTH+2+2+:COL_WIDTH-7]\n : app_addr_r2[5+3+BANK_WIDTH+RANK_WIDTH+2+2+:COL_WIDTH-7];\n end\n assign row[2:0] = app_rdy_r\n ? app_addr_r1[5+:3]\n : app_addr_r2[5+:3];\n if (RANKS==1) \n begin\n assign row[ROW_WIDTH-1:ROW_WIDTH-2] = app_rdy_r\n ? app_addr_r1[5+3+BANK_WIDTH+2+:2]\n : app_addr_r2[5+3+BANK_WIDTH+2+:2];\n assign row[ROW_WIDTH-3:3] = app_rdy_r\n ? app_addr_r1[5+3+BANK_WIDTH+2+2+COL_WIDTH-7+:ROW_WIDTH-5]\n : app_addr_r2[5+3+BANK_WIDTH+2+2+COL_WIDTH-7+:ROW_WIDTH-5];\n end\n else\n begin\n assign row[ROW_WIDTH-1:ROW_WIDTH-2] = app_rdy_r\n ? app_addr_r1[5+3+BANK_WIDTH+RANK_WIDTH+2+:2]\n : app_addr_r2[5+3+BANK_WIDTH+RANK_WIDTH+2+:2];\n assign row[ROW_WIDTH-3:3] = app_rdy_r\n ? app_addr_r1[5+3+BANK_WIDTH+RANK_WIDTH+2+2+COL_WIDTH-7+:ROW_WIDTH-5]\n : app_addr_r2[5+3+BANK_WIDTH+RANK_WIDTH+2+2+COL_WIDTH-7+:ROW_WIDTH-5];\n end\n assign bank = app_rdy_r\n ? app_addr_r1[5+3+:BANK_WIDTH]\n : app_addr_r2[5+3+:BANK_WIDTH];\n assign rank = (RANKS == 1)\n ? 1'b0\n : app_rdy_r\n ? app_addr_r1[5+3+BANK_WIDTH+:RANK_WIDTH]\n : app_addr_r2[5+3+BANK_WIDTH+:RANK_WIDTH];\n end\n else if (MEM_ADDR_ORDER == \"ROW_BANK_COLUMN\")\n begin\n assign col = app_rdy_r\n ? app_addr_r1[0+:COL_WIDTH]\n : app_addr_r2[0+:COL_WIDTH];\n assign row = app_rdy_r\n ? app_addr_r1[COL_WIDTH+BANK_WIDTH+:ROW_WIDTH]\n : app_addr_r2[COL_WIDTH+BANK_WIDTH+:ROW_WIDTH];\n assign bank = app_rdy_r\n ? app_addr_r1[COL_WIDTH+:BANK_WIDTH]\n : app_addr_r2[COL_WIDTH+:BANK_WIDTH];\n assign rank = (RANKS == 1)\n ? 1'b0\n : app_rdy_r\n ? app_addr_r1[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH]\n : app_addr_r2[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH];\n end\n else\n begin\n assign col = app_rdy_r\n ? app_addr_r1[0+:COL_WIDTH]\n : app_addr_r2[0+:COL_WIDTH];\n assign row = app_rdy_r\n ? app_addr_r1[COL_WIDTH+:ROW_WIDTH]\n : app_addr_r2[COL_WIDTH+:ROW_WIDTH];\n assign bank = app_rdy_r\n ? app_addr_r1[COL_WIDTH+ROW_WIDTH+:BANK_WIDTH]\n : app_addr_r2[COL_WIDTH+ROW_WIDTH+:BANK_WIDTH];\n assign rank = (RANKS == 1)\n ? 1'b0\n : app_rdy_r\n ? app_addr_r1[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH]\n : app_addr_r2[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH];\n end\n end\n endgenerate\n\n/* assign rank = (RANKS == 1)\n ? 1'b0\n : app_rdy_r\n ? app_addr_r1[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH]\n : app_addr_r2[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH];*/\n assign size = app_rdy_r\n ? app_sz_r1\n : app_sz_r2;\n assign cmd = app_rdy_r\n ? app_cmd_r1\n : app_cmd_r2;\n assign hi_priority = app_rdy_r\n ? app_hi_pri_r1\n : app_hi_pri_r2;\n\n wire request_accepted = use_addr_lcl && app_rdy_r;\n wire rd = app_cmd_r2[1:0] == 2'b01;\n wire wr = app_cmd_r2[1:0] == 2'b00;\n wire wr_bytes = app_cmd_r2[1:0] == 2'b11;\n wire write = wr || wr_bytes;\n output wire rd_accepted;\n assign rd_accepted = request_accepted && rd;\n output wire wr_accepted;\n assign wr_accepted = request_accepted && write;\n\n input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_buf_addr;\n input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r;\n output wire [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr;\n\n assign data_buf_addr = ~write ? rd_data_buf_addr_r : wr_data_buf_addr;\n\nendmodule // ui_cmd\n\n// Local Variables:\n// verilog-library-directories:(\".\")\n// End:\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ui/mig_7series_v4_0_ui_rd_data.v", "content": "//*****************************************************************************\n// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor : Xilinx\n// \\ \\ \\/ Version : %version\n// \\ \\ Application : MIG\n// / / Filename : ui_rd_data.v\n// /___/ /\\ Date Last Modified : $date$\n// \\ \\ / \\ Date Created : Tue Jun 30 2009\n// \\___\\/\\___\\\n//\n//Device : 7-Series\n//Design Name : DDR3 SDRAM\n//Purpose :\n//Reference :\n//Revision History :\n//*****************************************************************************\n\n// User interface read buffer. Re orders read data returned from the\n// memory controller back to the request order.\n//\n// Consists of a large buffer for the data, a status RAM and two counters.\n//\n// The large buffer is implemented with distributed RAM in 6 bit wide,\n// 1 read, 1 write mode. The status RAM is implemented with a distributed\n// RAM configured as 2 bits wide 1 read/write, 1 read mode.\n//\n// As read requests are received from the application, the data_buf_addr\n// counter supplies the data_buf_addr sent into the memory controller.\n// With each read request, the counter is incremented, eventually rolling\n// over. This mechanism labels each read request with an incrementing number.\n//\n// When the memory controller returns read data, it echos the original\n// data_buf_addr with the read data.\n//\n// The status RAM is indexed with the same address as the data buffer\n// RAM. Each word of the data buffer RAM has an associated status bit\n// and \"end\" bit. Requests of size 1 return a data burst on two consecutive\n// states. Requests of size zero return with a single assertion of rd_data_en.\n//\n// Upon returning data, the status and end bits are updated for each\n// corresponding location in the status RAM indexed by the data_buf_addr\n// echoed on the rd_data_addr field.\n//\n// The other side of the status and data RAMs is indexed by the rd_buf_indx.\n// The rd_buf_indx constantly monitors the status bit it is currently\n// pointing to. When the status becomes set to the proper state (more on\n// this later) read data is returned to the application, and the rd_buf_indx\n// is incremented.\n//\n// At rst the rd_buf_indx is initialized to zero. Data will not have been\n// returned from the memory controller yet, so there is nothing to return\n// to the application. Evenutally, read requests will be made, and the\n// memory controller will return the corresponding data. The memory\n// controller may not return this data in the request order. In which\n// case, the status bit at location zero, will not indicate\n// the data for request zero is ready. Eventually, the memory controller\n// will return data for request zero. The data is forwarded on to the\n// application, and rd_buf_indx is incremented to point to the next status\n// bits and data in the buffers. The status bit will be examined, and if\n// data is valid, this data will be returned as well. This process\n// continues until the status bit indexed by rd_buf_indx indicates data\n// is not ready. This may be because the rd_data_buf\n// is empty, or that some data was returned out of order. Since rd_buf_indx\n// always increments sequentially, data is always returned to the application\n// in request order.\n//\n// Some further discussion of the status bit is in order. The rd_data_buf\n// is a circular buffer. The status bit is a single bit. Distributed RAM\n// supports only a single write port. The write port is consumed by\n// memory controller read data updates. If a simple '1' were used to\n// indicate the status, when rd_data_indx rolled over it would immediately\n// encounter a one for a request that may not be ready.\n//\n// This problem is solved by causing read data returns to flip the\n// status bit, and adding hi order bit beyond the size required to\n// index the rd_data_buf. Data is considered ready when the status bit\n// and this hi order bit are equal.\n//\n// The status RAM needs to be initialized to zero after reset. This is\n// accomplished by cycling through all rd_buf_indx valus and writing a\n// zero to the status bits directly following deassertion of reset. This\n// mechanism is used for similar purposes\n// for the wr_data_buf.\n//\n// When ORDERING == \"STRICT\", read data reordering is unnecessary. For thi\n// case, most of the logic in the block is not generated.\n\n`timescale 1 ps / 1 ps\n\n// User interface read data.\n\nmodule mig_7series_v4_0_ui_rd_data #\n (\n parameter TCQ = 100,\n parameter APP_DATA_WIDTH = 256,\n parameter DATA_BUF_ADDR_WIDTH = 5,\n parameter ECC = \"OFF\",\n parameter nCK_PER_CLK = 2 ,\n parameter ORDERING = \"NORM\"\n )\n (/*AUTOARG*/\n // Outputs\n ram_init_done_r, ram_init_addr, app_rd_data_valid, app_rd_data_end,\n app_rd_data, app_ecc_multiple_err, rd_buf_full, rd_data_buf_addr_r,\n app_ecc_single_err, \n // Inputs\n rst, clk, rd_data_en, rd_data_addr, rd_data_offset, rd_data_end,\n rd_data, ecc_multiple, ecc_single, rd_accepted\n );\n\n input rst;\n input clk;\n\n output wire ram_init_done_r;\n output wire [3:0] ram_init_addr;\n\n// rd_buf_indx points to the status and data storage rams for\n// reading data out to the app.\n reg [5:0] rd_buf_indx_r;\n reg ram_init_done_r_lcl /* synthesis syn_maxfan = 10 */;\n assign ram_init_done_r = ram_init_done_r_lcl;\n wire app_rd_data_valid_ns;\n wire single_data;\n reg [5:0] rd_buf_indx_ns;\n generate begin : rd_buf_indx\n wire upd_rd_buf_indx = ~ram_init_done_r_lcl || app_rd_data_valid_ns;\n// Loop through all status write addresses once after rst. Initializes\n// the status and pointer RAMs.\n wire ram_init_done_ns =\n ~rst && (ram_init_done_r_lcl || (rd_buf_indx_r[4:0] == 5'h1f));\n always @(posedge clk) ram_init_done_r_lcl <= #TCQ ram_init_done_ns;\n\n always @(/*AS*/rd_buf_indx_r or rst or single_data\n or upd_rd_buf_indx) begin\n rd_buf_indx_ns = rd_buf_indx_r;\n if (rst) rd_buf_indx_ns = 6'b0;\n else if (upd_rd_buf_indx) rd_buf_indx_ns =\n // need to use every slot of RAMB32 if all address bits are used\n rd_buf_indx_r + 6'h1 + (DATA_BUF_ADDR_WIDTH == 5 ? 0 : single_data);\n end\n always @(posedge clk) rd_buf_indx_r <= #TCQ rd_buf_indx_ns;\n end\n endgenerate\n assign ram_init_addr = rd_buf_indx_r[3:0];\n\n input rd_data_en;\n input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;\n input rd_data_offset;\n input rd_data_end;\n input [APP_DATA_WIDTH-1:0] rd_data;\n output reg app_rd_data_valid /* synthesis syn_maxfan = 10 */;\n output reg app_rd_data_end;\n output reg [APP_DATA_WIDTH-1:0] app_rd_data;\n input [(2*nCK_PER_CLK)-1:0] ecc_multiple;\n input [(2*nCK_PER_CLK)-1:0] ecc_single;\n reg [2*nCK_PER_CLK-1:0] app_ecc_multiple_err_r = 'b0;\n reg [2*nCK_PER_CLK-1:0] app_ecc_single_err_r = 'b0;\n output wire [2*nCK_PER_CLK-1:0] app_ecc_multiple_err;\n output wire [2*nCK_PER_CLK-1:0] app_ecc_single_err;\n assign app_ecc_multiple_err = app_ecc_multiple_err_r;\n assign app_ecc_single_err = app_ecc_single_err_r;\n input rd_accepted;\n output wire rd_buf_full;\n output wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r;\n\n// Compute dimensions of read data buffer. Depending on width of\n// DQ bus and DRAM CK\n// to fabric ratio, number of RAM32Ms is variable. RAM32Ms are used in\n// single write, single read, 6 bit wide mode.\n localparam RD_BUF_WIDTH = APP_DATA_WIDTH + (ECC == \"OFF\" ? 0 : 2*2*nCK_PER_CLK);\n localparam FULL_RAM_CNT = (RD_BUF_WIDTH/6);\n localparam REMAINDER = RD_BUF_WIDTH % 6;\n localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);\n localparam RAM_WIDTH = (RAM_CNT*6);\n generate\n if (ORDERING == \"STRICT\") begin : strict_mode\n assign app_rd_data_valid_ns = 1'b0;\n assign single_data = 1'b0;\n assign rd_buf_full = 1'b0;\n reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r_lcl;\n wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_ns =\n rst\n ? 0\n : rd_data_buf_addr_r_lcl + rd_accepted;\n always @(posedge clk) rd_data_buf_addr_r_lcl <=\n #TCQ rd_data_buf_addr_ns;\n assign rd_data_buf_addr_r = rd_data_buf_addr_ns;\n// app_* signals required to be registered. \n if (ECC == \"OFF\") begin : ecc_off\n always @(/*AS*/rd_data) app_rd_data = rd_data;\n always @(/*AS*/rd_data_en) app_rd_data_valid = rd_data_en;\n always @(/*AS*/rd_data_end) app_rd_data_end = rd_data_end;\n end\n else begin : ecc_on \n always @(posedge clk) app_rd_data <= #TCQ rd_data;\n always @(posedge clk) app_rd_data_valid <= #TCQ rd_data_en;\n always @(posedge clk) app_rd_data_end <= #TCQ rd_data_end;\n always @(posedge clk) app_ecc_multiple_err_r <= #TCQ ecc_multiple;\n always @(posedge clk) app_ecc_single_err_r <= #TCQ ecc_single;\n end\n end\n else begin : not_strict_mode\n wire rd_buf_we = ~ram_init_done_r_lcl || rd_data_en /* synthesis syn_maxfan = 10 */;\n // In configurations where read data is returned in a single fabric cycle\n // the offset is always zero and we can use the bit to get a deeper\n // FIFO. The RAMB32 has 5 address bits, so when the DATA_BUF_ADDR_WIDTH\n // is set to use them all, discard the offset. Otherwise, include the\n // offset.\n wire [4:0] rd_buf_wr_addr = DATA_BUF_ADDR_WIDTH == 5 ?\n rd_data_addr :\n {rd_data_addr, rd_data_offset};\n wire [1:0] rd_status;\n// Instantiate status RAM. One bit for status and one for \"end\".\n begin : status_ram\n// Turns out read to write back status is a timing path. Update\n// the status in the ram on the state following the read. Bypass\n// the write data into the status read path.\n wire [4:0] status_ram_wr_addr_ns = ram_init_done_r_lcl\n ? rd_buf_wr_addr\n : rd_buf_indx_r[4:0];\n reg [4:0] status_ram_wr_addr_r;\n always @(posedge clk) status_ram_wr_addr_r <=\n #TCQ status_ram_wr_addr_ns;\n wire [1:0] wr_status;\n// Not guaranteed to write second status bit. If it is written, always\n// copy in the first status bit.\n reg wr_status_r1;\n always @(posedge clk) wr_status_r1 <= #TCQ wr_status[0];\n wire [1:0] status_ram_wr_data_ns =\n ram_init_done_r_lcl\n ? {rd_data_end, ~(rd_data_offset\n ? wr_status_r1\n : wr_status[0])}\n : 2'b0;\n reg [1:0] status_ram_wr_data_r;\n always @(posedge clk) status_ram_wr_data_r <=\n #TCQ status_ram_wr_data_ns;\n reg rd_buf_we_r1;\n always @(posedge clk) rd_buf_we_r1 <= #TCQ rd_buf_we;\n RAM32M\n #(.INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000)\n ) RAM32M0 (\n .DOA(rd_status),\n .DOB(),\n .DOC(wr_status),\n .DOD(),\n .DIA(status_ram_wr_data_r),\n .DIB(2'b0),\n .DIC(status_ram_wr_data_r),\n .DID(status_ram_wr_data_r),\n .ADDRA(rd_buf_indx_r[4:0]),\n .ADDRB(5'b0),\n .ADDRC(status_ram_wr_addr_ns),\n .ADDRD(status_ram_wr_addr_r),\n .WE(rd_buf_we_r1),\n .WCLK(clk)\n );\n end // block: status_ram\n\n wire [RAM_WIDTH-1:0] rd_buf_out_data;\n begin : rd_buf\n wire [RAM_WIDTH-1:0] rd_buf_in_data;\n if (REMAINDER == 0)\n if (ECC == \"OFF\")\n assign rd_buf_in_data = rd_data;\n else\n assign rd_buf_in_data = {ecc_single, ecc_multiple, rd_data};\n else\n if (ECC == \"OFF\")\n assign rd_buf_in_data = {{6-REMAINDER{1'b0}}, rd_data};\n else\n assign rd_buf_in_data = \n {{6-REMAINDER{1'b0}}, ecc_single, ecc_multiple, rd_data};\n\n // Dedicated copy for driving distributed RAM.\n (* keep = \"true\" *) reg [4:0] rd_buf_indx_copy_r /* synthesis syn_keep = 1 */;\n always @(posedge clk) rd_buf_indx_copy_r <= #TCQ rd_buf_indx_ns[4:0];\n\n genvar i;\n for (i=0; i 4) begin\n assign wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:4] = 0;\n end\n endgenerate\n\n mig_7series_v4_0_ui_cmd #\n (/*AUTOINSTPARAM*/\n // Parameters\n .TCQ (TCQ),\n .ADDR_WIDTH (ADDR_WIDTH),\n .BANK_WIDTH (BANK_WIDTH),\n .COL_WIDTH (COL_WIDTH),\n .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),\n .RANK_WIDTH (RANK_WIDTH),\n .ROW_WIDTH (ROW_WIDTH),\n .RANKS (RANKS),\n .MEM_ADDR_ORDER (MEM_ADDR_ORDER))\n ui_cmd0\n (/*AUTOINST*/\n // Outputs\n .app_rdy (app_rdy),\n .use_addr (use_addr),\n .rank (rank[RANK_WIDTH-1:0]),\n .bank (bank[BANK_WIDTH-1:0]),\n .row (row[ROW_WIDTH-1:0]),\n .col (col[COL_WIDTH-1:0]),\n .size (size),\n .cmd (cmd[2:0]),\n .hi_priority (hi_priority),\n .rd_accepted (rd_accepted),\n .wr_accepted (wr_accepted),\n .data_buf_addr (data_buf_addr),\n // Inputs\n .rst (rst),\n .clk (clk),\n .accept_ns (accept_ns),\n .rd_buf_full (rd_buf_full),\n .wr_req_16 (wr_req_16),\n .app_addr (app_addr[ADDR_WIDTH-1:0]),\n .app_cmd (app_cmd[2:0]),\n .app_sz (app_sz),\n .app_hi_pri (app_hi_pri),\n .app_en (app_en),\n .wr_data_buf_addr (wr_data_buf_addr),\n .rd_data_buf_addr_r (rd_data_buf_addr_r));\n\n mig_7series_v4_0_ui_wr_data #\n (/*AUTOINSTPARAM*/\n // Parameters\n .TCQ (TCQ),\n .APP_DATA_WIDTH (APP_DATA_WIDTH),\n .APP_MASK_WIDTH (APP_MASK_WIDTH),\n .nCK_PER_CLK (nCK_PER_CLK),\n .ECC (ECC),\n .ECC_TEST (ECC_TEST),\n .CWL (CWL_M))\n ui_wr_data0\n (/*AUTOINST*/\n // Outputs\n .app_wdf_rdy (app_wdf_rdy),\n .wr_req_16 (wr_req_16),\n .wr_data_buf_addr (wr_data_buf_addr[3:0]),\n .wr_data (wr_data[APP_DATA_WIDTH-1:0]),\n .wr_data_mask (wr_data_mask[APP_MASK_WIDTH-1:0]),\n .raw_not_ecc (raw_not_ecc[2*nCK_PER_CLK-1:0]),\n // Inputs\n .rst (rst),\n .clk (clk),\n .app_wdf_data (app_wdf_data[APP_DATA_WIDTH-1:0]),\n .app_wdf_mask (app_wdf_mask[APP_MASK_WIDTH-1:0]),\n .app_raw_not_ecc (app_raw_not_ecc[2*nCK_PER_CLK-1:0]),\n .app_wdf_wren (app_wdf_wren),\n .app_wdf_end (app_wdf_end),\n .wr_data_offset (wr_data_offset),\n .wr_data_addr (wr_data_addr[3:0]),\n .wr_data_en (wr_data_en),\n .wr_accepted (wr_accepted),\n .ram_init_done_r (ram_init_done_r),\n .ram_init_addr (ram_init_addr));\n\n mig_7series_v4_0_ui_rd_data #\n (/*AUTOINSTPARAM*/\n // Parameters\n .TCQ (TCQ),\n .APP_DATA_WIDTH (APP_DATA_WIDTH),\n .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),\n .nCK_PER_CLK (nCK_PER_CLK),\n .ECC (ECC),\n .ORDERING (ORDERING))\n ui_rd_data0\n (/*AUTOINST*/\n // Outputs\n .ram_init_done_r (ram_init_done_r),\n .ram_init_addr (ram_init_addr),\n .app_rd_data_valid (app_rd_data_valid),\n .app_rd_data_end (app_rd_data_end),\n .app_rd_data (app_rd_data[APP_DATA_WIDTH-1:0]),\n .app_ecc_multiple_err (app_ecc_multiple_err[2*nCK_PER_CLK-1:0]),\n .app_ecc_single_err (app_ecc_single_err[2*nCK_PER_CLK-1:0]),\n .rd_buf_full (rd_buf_full),\n .rd_data_buf_addr_r (rd_data_buf_addr_r),\n // Inputs\n .rst (rst),\n .clk (clk),\n .rd_data_en (rd_data_en),\n .rd_data_addr (rd_data_addr),\n .rd_data_offset (rd_data_offset),\n .rd_data_end (rd_data_end),\n .rd_data (rd_data[APP_DATA_WIDTH-1:0]),\n .ecc_multiple (ecc_multiple),\n .ecc_single (ecc_single),\n .rd_accepted (rd_accepted));\n\n\nendmodule // ui_top\n\n// Local Variables:\n// verilog-library-directories:(\".\" \"../mc\")\n// End:\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/ui/mig_7series_v4_0_ui_wr_data.v", "content": "//*****************************************************************************\n// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n//\n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n//\n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n//\n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n//\n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n//\n//*****************************************************************************\n// ____ ____\n// / /\\/ /\n// /___/ \\ / Vendor : Xilinx\n// \\ \\ \\/ Version : %version\n// \\ \\ Application : MIG\n// / / Filename : ui_wr_data.v\n// /___/ /\\ Date Last Modified : $date$\n// \\ \\ / \\ Date Created : Tue Jun 30 2009\n// \\___\\/\\___\\\n//\n//Device : 7-Series\n//Design Name : DDR3 SDRAM\n//Purpose :\n//Reference :\n//Revision History :\n//*****************************************************************************\n\n// User interface write data buffer. Consists of four counters,\n// a pointer RAM and the write data storage RAM.\n//\n// All RAMs are implemented with distributed RAM.\n//\n// Whe ordering is set to STRICT or NORM, data moves through\n// the write data buffer in strictly FIFO order. In RELAXED\n// mode, data may be retired from the write data RAM in any\n// order relative to the input order. This implementation\n// supports all ordering modes.\n//\n// The pointer RAM stores a list of pointers to the write data storage RAM.\n// This is a list of vacant entries. As data is written into the RAM, a\n// pointer is pulled from the pointer RAM and used to index the write\n// operation. In a semi autonomously manner, pointers are also pulled, in\n// the same order, and provided to the command port as the data_buf_addr.\n//\n// When the MC reads data from the write data buffer, it uses the\n// data_buf_addr provided with the command to extract the data from the\n// write data buffer. It also writes this pointer into the end\n// of the pointer RAM.\n//\n// The occupancy counter keeps track of how many entries are valid\n// in the write data storage RAM. app_wdf_rdy and app_rdy will be\n// de-asserted when there is no more storage in the write data buffer.\n//\n// Three sequentially incrementing counters/indexes are used to maintain\n// and use the contents of the pointer RAM.\n//\n// The write buffer write data address index generates the pointer\n// used to extract the write data address from the pointer RAM. It\n// is incremented with each buffer write. The counter is actually one\n// ahead of the current write address so that the actual data buffer\n// write address can be registered to give a full state to propagate to\n// the write data distributed RAMs.\n//\n// The data_buf_addr counter is used to extract the data_buf_addr for\n// the command port. It is incremented as each command is written\n// into the MC.\n//\n// The read data index points to the end of the list of free\n// buffers. When the MC fetches data from the write data buffer, it\n// provides the buffer address. The buffer address is used to fetch\n// the data, but is also written into the pointer at the location indicated\n// by the read data index.\n//\n// Enter and exiting a buffer full condition generates corner cases. Upon\n// entering a full condition, incrementing the write buffer write data\n// address index must be inhibited. When exiting the full condition,\n// the just arrived pointer must propagate through the pointer RAM, then\n// indexed by the current value of the write buffer write data\n// address counter, the value is registered in the write buffer write\n// data address register, then the counter can be advanced.\n//\n// The pointer RAM must be initialized with valid data after reset. This is\n// accomplished by stepping through each pointer RAM entry and writing\n// the locations address into the pointer RAM. For the FIFO modes, this means\n// that buffer address will always proceed in a sequential order. In the\n// RELAXED mode, the original write traversal will be in sequential\n// order, but once the MC begins to retire out of order, the entries in\n// the pointer RAM will become randomized. The ui_rd_data module provides\n// the control information for the initialization process.\n\n`timescale 1 ps / 1 ps\n\nmodule mig_7series_v4_0_ui_wr_data #\n (\n parameter TCQ = 100,\n parameter APP_DATA_WIDTH = 256,\n parameter APP_MASK_WIDTH = 32,\n parameter ECC = \"OFF\",\n parameter nCK_PER_CLK = 2 ,\n parameter ECC_TEST = \"OFF\",\n parameter CWL = 5\n )\n (/*AUTOARG*/\n // Outputs\n app_wdf_rdy, wr_req_16, wr_data_buf_addr, wr_data, wr_data_mask,\n raw_not_ecc,\n // Inputs\n rst, clk, app_wdf_data, app_wdf_mask, app_raw_not_ecc, app_wdf_wren,\n app_wdf_end, wr_data_offset, wr_data_addr, wr_data_en, wr_accepted,\n ram_init_done_r, ram_init_addr\n );\n\n input rst;\n input clk;\n\n input [APP_DATA_WIDTH-1:0] app_wdf_data;\n input [APP_MASK_WIDTH-1:0] app_wdf_mask;\n input [2*nCK_PER_CLK-1:0] app_raw_not_ecc;\n input app_wdf_wren;\n input app_wdf_end;\n\n reg [APP_DATA_WIDTH-1:0] app_wdf_data_r1;\n reg [APP_MASK_WIDTH-1:0] app_wdf_mask_r1;\n reg [2*nCK_PER_CLK-1:0] app_raw_not_ecc_r1 = 4'b0;\n reg app_wdf_wren_r1;\n reg app_wdf_end_r1;\n\n reg app_wdf_rdy_r;\n\n //Adding few copies of the app_wdf_rdy_r signal in order to meet\n //timing. This is signal has a very high fanout. So grouped into\n //few functional groups and alloted one copy per group.\n (* equivalent_register_removal = \"no\" *)\n reg app_wdf_rdy_r_copy1;\n (* equivalent_register_removal = \"no\" *)\n reg app_wdf_rdy_r_copy2;\n (* equivalent_register_removal = \"no\" *)\n reg app_wdf_rdy_r_copy3;\n (* equivalent_register_removal = \"no\" *)\n reg app_wdf_rdy_r_copy4;\n\n wire [APP_DATA_WIDTH-1:0] app_wdf_data_ns1 =\n ~app_wdf_rdy_r_copy2 ? app_wdf_data_r1 : app_wdf_data;\n wire [APP_MASK_WIDTH-1:0] app_wdf_mask_ns1 =\n ~app_wdf_rdy_r_copy2 ? app_wdf_mask_r1 : app_wdf_mask;\n wire app_wdf_wren_ns1 =\n ~rst && (~app_wdf_rdy_r_copy2 ? app_wdf_wren_r1 : app_wdf_wren);\n wire app_wdf_end_ns1 =\n ~rst && (~app_wdf_rdy_r_copy2 ? app_wdf_end_r1 : app_wdf_end);\n\n generate\n if (ECC_TEST != \"OFF\") begin : ecc_on\n always @(app_raw_not_ecc) app_raw_not_ecc_r1 = app_raw_not_ecc;\n end\n endgenerate\n\n// Be explicit about the latch enable on these registers.\n always @(posedge clk) begin\n app_wdf_data_r1 <= #TCQ app_wdf_data_ns1;\n app_wdf_mask_r1 <= #TCQ app_wdf_mask_ns1;\n app_wdf_wren_r1 <= #TCQ app_wdf_wren_ns1;\n app_wdf_end_r1 <= #TCQ app_wdf_end_ns1;\n end\n\n// The signals wr_data_addr and wr_data_offset come at different\n// times depending on ECC and the value of CWL. The data portion\n// always needs to look a the raw wires, the control portion needs\n// to look at a delayed version when ECC is on and CWL != 8. The\n// currently supported write data delays do not require this\n// functionality, but preserve for future use.\n input wr_data_offset;\n input [3:0] wr_data_addr;\n reg wr_data_offset_r;\n reg [3:0] wr_data_addr_r;\n generate\n if (ECC == \"OFF\" || CWL >= 0) begin : pass_wr_addr\n always @(wr_data_offset) wr_data_offset_r = wr_data_offset;\n always @(wr_data_addr) wr_data_addr_r = wr_data_addr;\n end\n else begin : delay_wr_addr\n always @(posedge clk) wr_data_offset_r <= #TCQ wr_data_offset;\n always @(posedge clk) wr_data_addr_r <= #TCQ wr_data_addr;\n end\n endgenerate\n\n// rd_data_cnt is the pointer RAM index for data read from the write data\n// buffer. Ie, its the data on its way out to the DRAM.\n input wr_data_en;\n wire new_rd_data = wr_data_en && ~wr_data_offset_r;\n reg [3:0] rd_data_indx_r;\n reg rd_data_upd_indx_r;\n generate begin : read_data_indx\n reg [3:0] rd_data_indx_ns;\n always @(/*AS*/new_rd_data or rd_data_indx_r or rst) begin\n rd_data_indx_ns = rd_data_indx_r;\n if (rst) rd_data_indx_ns = 5'b0;\n else if (new_rd_data) rd_data_indx_ns = rd_data_indx_r + 5'h1;\n end\n always @(posedge clk) rd_data_indx_r <= #TCQ rd_data_indx_ns;\n always @(posedge clk) rd_data_upd_indx_r <= #TCQ new_rd_data;\n end\n endgenerate\n\n// data_buf_addr_cnt generates the pointer for the pointer RAM on behalf\n// of data buf address that comes with the wr_data_en.\n// The data buf address is written into the memory\n// controller along with the command and address.\n input wr_accepted;\n reg [3:0] data_buf_addr_cnt_r;\n generate begin : data_buf_address_counter\n\n reg [3:0] data_buf_addr_cnt_ns;\n always @(/*AS*/data_buf_addr_cnt_r or rst or wr_accepted) begin\n data_buf_addr_cnt_ns = data_buf_addr_cnt_r;\n if (rst) data_buf_addr_cnt_ns = 4'b0;\n else if (wr_accepted) data_buf_addr_cnt_ns =\n data_buf_addr_cnt_r + 4'h1;\n end\n always @(posedge clk) data_buf_addr_cnt_r <= #TCQ data_buf_addr_cnt_ns;\n\n end\n endgenerate\n\n// Control writing data into the write data buffer.\n wire wdf_rdy_ns;\n always @( posedge clk ) begin\n \tapp_wdf_rdy_r_copy1 <= #TCQ wdf_rdy_ns;\n \tapp_wdf_rdy_r_copy2 <= #TCQ wdf_rdy_ns;\n \tapp_wdf_rdy_r_copy3 <= #TCQ wdf_rdy_ns;\n \tapp_wdf_rdy_r_copy4 <= #TCQ wdf_rdy_ns;\n end\n wire wr_data_end = app_wdf_end_r1 && app_wdf_rdy_r_copy1 && app_wdf_wren_r1;\n wire [3:0] wr_data_pntr;\n wire [4:0] wb_wr_data_addr;\n wire [4:0] wb_wr_data_addr_w;\n reg [3:0] wr_data_indx_r;\n generate begin : write_data_control\n\n wire wr_data_addr_le = (wr_data_end && wdf_rdy_ns) ||\n (rd_data_upd_indx_r && ~app_wdf_rdy_r_copy1);\n\n// For pointer RAM. Initialize to one since this is one ahead of\n// what's being registered in wb_wr_data_addr. Assumes pointer RAM\n// has been initialized such that address equals contents.\n reg [3:0] wr_data_indx_ns;\n always @(/*AS*/rst or wr_data_addr_le or wr_data_indx_r) begin\n wr_data_indx_ns = wr_data_indx_r;\n if (rst) wr_data_indx_ns = 4'b1;\n else if (wr_data_addr_le) wr_data_indx_ns = wr_data_indx_r + 4'h1;\n end\n always @(posedge clk) wr_data_indx_r <= #TCQ wr_data_indx_ns;\n\n// Take pointer from pointer RAM and set into the write data address.\n// Needs to be split into zeroth bit and everything else because synthesis\n// tools don't always allow assigning bit vectors seperately. Bit zero of the\n// address is computed via an entirely different algorithm.\n reg [4:1] wb_wr_data_addr_ns;\n reg [4:1] wb_wr_data_addr_r;\n always @(/*AS*/rst or wb_wr_data_addr_r or wr_data_addr_le\n or wr_data_pntr) begin\n wb_wr_data_addr_ns = wb_wr_data_addr_r;\n if (rst) wb_wr_data_addr_ns = 4'b0;\n else if (wr_data_addr_le) wb_wr_data_addr_ns = wr_data_pntr;\n end\n always @(posedge clk) wb_wr_data_addr_r <= #TCQ wb_wr_data_addr_ns;\n\n// If we see the first getting accepted, then\n// second half is unconditionally accepted.\n reg wb_wr_data_addr0_r;\n wire wb_wr_data_addr0_ns = ~rst &&\n ((app_wdf_rdy_r_copy3 && app_wdf_wren_r1 && ~app_wdf_end_r1) ||\n (wb_wr_data_addr0_r && ~app_wdf_wren_r1));\n always @(posedge clk) wb_wr_data_addr0_r <= #TCQ wb_wr_data_addr0_ns;\n\n assign wb_wr_data_addr = {wb_wr_data_addr_r, wb_wr_data_addr0_r};\n assign wb_wr_data_addr_w = {wb_wr_data_addr_ns, wb_wr_data_addr0_ns};\n\n end\n endgenerate\n\n// Keep track of how many entries in the queue hold data.\n input ram_init_done_r;\n output wire app_wdf_rdy;\n generate begin : occupied_counter\n //reg [4:0] occ_cnt_ns;\n //reg [4:0] occ_cnt_r;\n //always @(/*AS*/occ_cnt_r or rd_data_upd_indx_r or rst\n // or wr_data_end) begin\n // occ_cnt_ns = occ_cnt_r;\n // if (rst) occ_cnt_ns = 5'b0;\n // else case ({wr_data_end, rd_data_upd_indx_r})\n // 2'b01 : occ_cnt_ns = occ_cnt_r - 5'b1;\n // 2'b10 : occ_cnt_ns = occ_cnt_r + 5'b1;\n // endcase // case ({wr_data_end, rd_data_upd_indx_r})\n //end\n //always @(posedge clk) occ_cnt_r <= #TCQ occ_cnt_ns;\n //assign wdf_rdy_ns = !(rst || ~ram_init_done_r || occ_cnt_ns[4]);\n //always @(posedge clk) app_wdf_rdy_r <= #TCQ wdf_rdy_ns;\n //assign app_wdf_rdy = app_wdf_rdy_r;\n reg [15:0] occ_cnt;\n always @(posedge clk) begin\n \tif ( rst )\n\t occ_cnt <= #TCQ 16'h0000;\n\telse case ({wr_data_end, rd_data_upd_indx_r})\n\t 2'b01 : occ_cnt <= #TCQ {1'b0,occ_cnt[15:1]};\n\t 2'b10 : occ_cnt <= #TCQ {occ_cnt[14:0],1'b1};\n endcase // case ({wr_data_end, rd_data_upd_indx_r})\n end\n assign wdf_rdy_ns = !(rst || ~ram_init_done_r || (occ_cnt[14] && wr_data_end && ~rd_data_upd_indx_r) || (occ_cnt[15] && ~rd_data_upd_indx_r));\n always @(posedge clk) app_wdf_rdy_r <= #TCQ wdf_rdy_ns;\n assign app_wdf_rdy = app_wdf_rdy_r;\n\n`ifdef MC_SVA\n wr_data_buffer_full: cover property (@(posedge clk)\n (~rst && ~app_wdf_rdy_r));\n// wr_data_buffer_inc_dec_15: cover property (@(posedge clk)\n// (~rst && wr_data_end && rd_data_upd_indx_r && (occ_cnt_r == 5'hf)));\n// wr_data_underflow: assert property (@(posedge clk)\n// (rst || !((occ_cnt_r == 5'b0) && (occ_cnt_ns == 5'h1f))));\n// wr_data_overflow: assert property (@(posedge clk)\n// (rst || !((occ_cnt_r == 5'h10) && (occ_cnt_ns == 5'h11))));\n`endif\n end // block: occupied_counter\n endgenerate\n\n// Keep track of how many write requests are in the memory controller. We\n// must limit this to 16 because we only have that many data_buf_addrs to\n// hand out. Since the memory controller queue and the write data buffer\n// queue are distinct, the number of valid entries can be different.\n// Throttle request acceptance once there are sixteen write requests in\n// the memory controller. Note that there is still a requirement\n// for a write reqeusts corresponding write data to be written into the\n// write data queue with two states of the request.\n output wire wr_req_16;\n generate begin : wr_req_counter\n reg [4:0] wr_req_cnt_ns;\n reg [4:0] wr_req_cnt_r;\n always @(/*AS*/rd_data_upd_indx_r or rst or wr_accepted\n or wr_req_cnt_r) begin\n wr_req_cnt_ns = wr_req_cnt_r;\n if (rst) wr_req_cnt_ns = 5'b0;\n else case ({wr_accepted, rd_data_upd_indx_r})\n 2'b01 : wr_req_cnt_ns = wr_req_cnt_r - 5'b1;\n 2'b10 : wr_req_cnt_ns = wr_req_cnt_r + 5'b1;\n endcase // case ({wr_accepted, rd_data_upd_indx_r})\n end\n always @(posedge clk) wr_req_cnt_r <= #TCQ wr_req_cnt_ns;\n assign wr_req_16 = (wr_req_cnt_ns == 5'h10);\n\n`ifdef MC_SVA\n wr_req_mc_full: cover property (@(posedge clk) (~rst && wr_req_16));\n wr_req_mc_full_inc_dec_15: cover property (@(posedge clk)\n (~rst && wr_accepted && rd_data_upd_indx_r && (wr_req_cnt_r == 5'hf)));\n wr_req_underflow: assert property (@(posedge clk)\n (rst || !((wr_req_cnt_r == 5'b0) && (wr_req_cnt_ns == 5'h1f))));\n wr_req_overflow: assert property (@(posedge clk)\n (rst || !((wr_req_cnt_r == 5'h10) && (wr_req_cnt_ns == 5'h11))));\n`endif\n end // block: wr_req_counter\n endgenerate\n\n\n\n// Instantiate pointer RAM. Made up of RAM32M in single write, two read\n// port mode, 2 bit wide mode.\n input [3:0] ram_init_addr;\n output wire [3:0] wr_data_buf_addr;\n localparam PNTR_RAM_CNT = 2;\n generate begin : pointer_ram\n wire pointer_we = new_rd_data || ~ram_init_done_r;\n wire [3:0] pointer_wr_data = ram_init_done_r\n ? wr_data_addr_r\n : ram_init_addr;\n wire [3:0] pointer_wr_addr = ram_init_done_r\n ? rd_data_indx_r\n : ram_init_addr;\n genvar i;\n for (i=0; i\n\n xilinx.com\n xci\n unknown\n 1.0\n \n \n ddr3_if\n \n \n 32\n 32\n 32\n 4\n 1048576\n 32\n 4\n 1048576\n 8\n 3\n 1\n 1\n 1\n 8\n OFF\n 1\n 1\n 1\n 8\n 1\n OFF\n 14\n 1\n 1\n 1\n 2\n 1\n 8\n 3\n 1\n 1\n 1\n 8\n OFF\n 1\n 1\n 1\n 8\n 1\n OFF\n 14\n 1\n 1\n 1\n 2\n 1\n 8\n 8\n 2\n OFF\n 1\n OFF\n 100.0\n FALSE\n 8\n 3\n 1\n 1\n 1\n 8\n OFF\n 1\n 1\n 1\n 8\n OFF\n 14\n 1\n 1\n 1\n 2\n 1\n DDR3\n FALSE\n 10.0\n FALSE\n 10\n FALSE\n 10\n FALSE\n 10\n FALSE\n 10\n 1200.0\n 0.000\n ACTIVE_LOW\n 29\n 1\n 8\n 18\n OFF\n 1\n 29\n 2\n 1\n 1\n 18\n OFF\n 1\n 1\n 1\n 8\n 1\n 29\n 1\n 29\n 2\n 1\n 1\n 18\n OFF\n 1\n 1\n 1\n 8\n 1\n 29\n 1\n 29\n 2\n 1\n 18\n 1\n 1\n DIFF\n FALSE\n 0\n 32\n 32\n 32\n 4\n 1048576\n 32\n 4\n 1048576\n 8\n 3\n 1\n 1\n 1\n 8\n OFF\n 1\n 1\n 1\n 8\n 1\n OFF\n 14\n 1\n 1\n 1\n 2\n 1\n 8\n 3\n 1\n 1\n 1\n 8\n OFF\n 1\n 1\n 1\n 8\n 1\n OFF\n 14\n 1\n 1\n 1\n 2\n 1\n 8\n 8\n 2\n OFF\n 1\n OFF\n 100.0\n FALSE\n 8\n 3\n 1\n 1\n 1\n 8\n OFF\n 1\n 1\n 1\n 8\n OFF\n 14\n 1\n 1\n 1\n 2\n 1\n DDR3\n FALSE\n 10.0\n FALSE\n 10\n FALSE\n 10\n FALSE\n 10\n FALSE\n 10\n 1200.0\n 0.000\n ACTIVE_LOW\n 29\n 1\n 8\n 18\n OFF\n 1\n 29\n 2\n 1\n 1\n 18\n OFF\n 1\n 1\n 1\n 8\n 1\n 29\n 1\n 29\n 2\n 1\n 1\n 18\n OFF\n 1\n 1\n 1\n 8\n 1\n 29\n 1\n 29\n 2\n 1\n 18\n 1\n 1\n DIFF\n FALSE\n 0\n 32\n 32\n 32\n 4\n 1048576\n 32\n 4\n 1048576\n 8\n 3\n 1\n 1\n 1\n 8\n OFF\n 1\n 1\n 1\n 8\n 1\n OFF\n 14\n 1\n 1\n 1\n 2\n 1\n 8\n 3\n 1\n 1\n 1\n 8\n OFF\n 1\n 1\n 1\n 8\n 1\n OFF\n 14\n 1\n 1\n 1\n 2\n 1\n 8\n 8\n 2\n OFF\n 1\n OFF\n 100.0\n FALSE\n 8\n 3\n 1\n 1\n 1\n 8\n OFF\n 1\n 1\n 1\n 8\n OFF\n 14\n 1\n 1\n 1\n 2\n 1\n DDR3\n FALSE\n 10.0\n FALSE\n 10\n FALSE\n 10\n FALSE\n 10\n FALSE\n 10\n 1200.0\n 0.000\n ACTIVE_LOW\n 29\n 1\n 8\n 18\n OFF\n 1\n 29\n 2\n 1\n 1\n 18\n OFF\n 1\n 1\n 1\n 8\n 1\n 29\n 1\n 29\n 2\n 1\n 1\n 18\n OFF\n 1\n 1\n 1\n 8\n 1\n 29\n 1\n 29\n 2\n 1\n 18\n 1\n 1\n DIFF\n FALSE\n 0\n 32\n 32\n 32\n 4\n 1048576\n 32\n 4\n 1048576\n 8\n 3\n 1\n 1\n 1\n 8\n OFF\n 1\n 1\n 1\n 8\n 1\n OFF\n 14\n 1\n 1\n 1\n 2\n 1\n 8\n 3\n 1\n 1\n 1\n 8\n OFF\n 1\n 1\n 1\n 8\n 1\n OFF\n 14\n 1\n 1\n 1\n 2\n 1\n 8\n 8\n 2\n OFF\n 1\n OFF\n 100.0\n FALSE\n 8\n 3\n 1\n 1\n 1\n 8\n OFF\n 1\n 1\n 1\n 8\n OFF\n 14\n 1\n 1\n 1\n 2\n 1\n DDR3\n FALSE\n 10.0\n FALSE\n 10\n FALSE\n 10\n FALSE\n 10\n FALSE\n 10\n 1200.0\n 0.000\n ACTIVE_LOW\n 29\n 1\n 8\n 18\n OFF\n 1\n 29\n 2\n 1\n 1\n 18\n OFF\n 1\n 1\n 1\n 8\n 1\n 29\n 1\n 29\n 2\n 1\n 1\n 18\n OFF\n 1\n 1\n 1\n 8\n 1\n 29\n 1\n 29\n 2\n 1\n 18\n 1\n 1\n DIFF\n FALSE\n 0\n 32\n 32\n 32\n 4\n 1048576\n 32\n 4\n 1048576\n 8\n 3\n 1\n 1\n 1\n 8\n OFF\n 1\n 1\n 1\n 8\n 1\n OFF\n 14\n 1\n 1\n 1\n 2\n 1\n 8\n 3\n 1\n 1\n 1\n 8\n OFF\n 1\n 1\n 1\n 8\n 1\n OFF\n 14\n 1\n 1\n 1\n 2\n 1\n 8\n 8\n 2\n OFF\n 1\n OFF\n 100.0\n FALSE\n 8\n 3\n 1\n 1\n 1\n 8\n OFF\n 1\n 1\n 1\n 8\n OFF\n 14\n 1\n 1\n 1\n 2\n 1\n DDR3\n FALSE\n 10.0\n FALSE\n 10\n FALSE\n 10\n FALSE\n 10\n FALSE\n 10\n 1200.0\n 0.000\n ACTIVE_LOW\n 29\n 1\n 8\n 18\n OFF\n 1\n 29\n 2\n 1\n 1\n 18\n OFF\n 1\n 1\n 1\n 8\n 1\n 29\n 1\n 29\n 2\n 1\n 1\n 18\n OFF\n 1\n 1\n 1\n 8\n 1\n 29\n 1\n 29\n 2\n 1\n 18\n 1\n 1\n DIFF\n FALSE\n 0\n 32\n 32\n 32\n 4\n 1048576\n 32\n 4\n 1048576\n 8\n 3\n 1\n 1\n 1\n 8\n OFF\n 1\n 1\n 1\n 8\n 1\n OFF\n 14\n 1\n 1\n 1\n 2\n 1\n 8\n 3\n 1\n 1\n 1\n 8\n OFF\n 1\n 1\n 1\n 8\n 1\n OFF\n 14\n 1\n 1\n 1\n 2\n 1\n 8\n 8\n 2\n OFF\n 1\n OFF\n 100.0\n FALSE\n 8\n 3\n 1\n 1\n 1\n 8\n OFF\n 1\n 1\n 1\n 8\n OFF\n 14\n 1\n 1\n 1\n 2\n 1\n DDR3\n FALSE\n 10.0\n FALSE\n 10\n FALSE\n 10\n FALSE\n 10\n FALSE\n 10\n 1200.0\n 0.000\n ACTIVE_LOW\n 29\n 1\n 8\n 18\n OFF\n 1\n 29\n 2\n 1\n 1\n 18\n OFF\n 1\n 1\n 1\n 8\n 1\n 29\n 1\n 29\n 2\n 1\n 1\n 18\n OFF\n 1\n 1\n 1\n 8\n 1\n 29\n 1\n 29\n 2\n 1\n 18\n 1\n 1\n DIFF\n FALSE\n 0\n 32\n 32\n 32\n 4\n 1048576\n 32\n 4\n 1048576\n 8\n 3\n 1\n 1\n 1\n 8\n OFF\n 1\n 1\n 1\n 8\n 1\n OFF\n 14\n 1\n 1\n 1\n 2\n 1\n 8\n 3\n 1\n 1\n 1\n 8\n OFF\n 1\n 1\n 1\n 8\n 1\n OFF\n 14\n 1\n 1\n 1\n 2\n 1\n 8\n 8\n 2\n OFF\n 1\n OFF\n 100.0\n FALSE\n 8\n 3\n 1\n 1\n 1\n 8\n OFF\n 1\n 1\n 1\n 8\n OFF\n 14\n 1\n 1\n 1\n 2\n 1\n DDR3\n FALSE\n 10.0\n FALSE\n 10\n FALSE\n 10\n FALSE\n 10\n FALSE\n 10\n 1200.0\n 0.000\n ACTIVE_LOW\n 29\n 1\n 8\n 18\n OFF\n 1\n 29\n 2\n 1\n 1\n 18\n OFF\n 1\n 1\n 1\n 8\n 1\n 29\n 1\n 29\n 2\n 1\n 1\n 18\n OFF\n 1\n 1\n 1\n 8\n 1\n 29\n 1\n 29\n 2\n 1\n 18\n 1\n 1\n DIFF\n FALSE\n 0\n 32\n 32\n 32\n 4\n 1048576\n 32\n 4\n 1048576\n 8\n 3\n 1\n 1\n 1\n 8\n OFF\n 1\n 1\n 1\n 8\n 1\n OFF\n 14\n 1\n 1\n 1\n 2\n 1\n 8\n 3\n 1\n 1\n 1\n 8\n OFF\n 1\n 1\n 1\n 8\n 1\n OFF\n 14\n 1\n 1\n 1\n 2\n 1\n 8\n 8\n 2\n OFF\n 1\n OFF\n 100.0\n FALSE\n 8\n 3\n 1\n 1\n 1\n 8\n OFF\n 1\n 1\n 1\n 8\n OFF\n 14\n 1\n 1\n 1\n 2\n 1\n DDR3\n FALSE\n 10.0\n FALSE\n 10\n FALSE\n 10\n FALSE\n 10\n FALSE\n 10\n 1200.0\n 0.000\n ACTIVE_LOW\n 29\n 1\n 8\n 18\n OFF\n 1\n 29\n 2\n 1\n 1\n 18\n OFF\n 1\n 1\n 1\n 8\n 1\n 29\n 1\n 29\n 2\n 1\n 1\n 18\n OFF\n 1\n 1\n 1\n 8\n 1\n 29\n 1\n 29\n 2\n 1\n 18\n 1\n 1\n DIFF\n FALSE\n 0\n 0\n 30\n 32\n 32\n 4\n 1048576\n 256\n 1\n 1073741824\n 8\n 3\n 1\n 1\n 1\n 8\n OFF\n 1\n 1\n 1\n 8\n 1\n OFF\n 14\n 1\n 1\n 1\n 2\n 1\n 29\n 3\n 1\n 1\n 1\n 32\n OFF\n 4\n 2\n 4\n 32\n 1\n OFF\n 15\n 1\n 1\n 1\n 4\n 1\n 8\n 8\n 2\n OFF\n 1\n OFF\n 224820144\n FALSE\n 8\n 3\n 1\n 1\n 1\n 8\n OFF\n 1\n 1\n 1\n 8\n OFF\n 14\n 1\n 1\n 1\n 2\n 1\n DDR3\n FALSE\n 10.0\n FALSE\n 10\n FALSE\n 10\n FALSE\n 10\n FALSE\n 10\n 899\n 1\n 0.000\n ACTIVE_LOW\n 29\n 1\n 8\n 18\n OFF\n 1\n NONE\n 29\n 2\n 1\n 1\n 18\n OFF\n 1\n 1\n 1\n 8\n 1\n 29\n 1\n 29\n 2\n 1\n 1\n 18\n OFF\n 1\n 1\n 1\n 8\n 1\n 29\n 1\n 29\n 2\n 1\n 18\n 1\n 1\n NOBUF\n INTERNAL\n FALSE\n 1\n Custom\n ddr3_if\n Custom\n Custom\n mig_a.prj\n kintex7\n \n xc7k325t\n ffg900\n VERILOG\n \n MIXED\n -2\n \n TRUE\n TRUE\n IP_Flow\n 1\n TRUE\n .\n \n .\n 2016.3\n OUT_OF_CONTEXT\n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if_sim_netlist.v", "content": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// --------------------------------------------------------------------------------\n// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016\n// Date : Tue Nov 15 09:09:09 2016\n// Host : david-xilinx-vm running 64-bit unknown\n// Command : write_verilog -force -mode funcsim -rename_top ddr3_if -prefix\n// ddr3_if_ ddr3_if_sim_netlist.v\n// Design : ddr3_if\n// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified\n// or synthesized. This netlist cannot be used for SDF annotated simulation.\n// Device : xc7k325tffg900-2\n// --------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* NotValidForBitStream *)\nmodule ddr3_if\n (ddr3_dq,\n ddr3_dqs_n,\n ddr3_dqs_p,\n ddr3_addr,\n ddr3_ba,\n ddr3_ras_n,\n ddr3_cas_n,\n ddr3_we_n,\n ddr3_reset_n,\n ddr3_ck_p,\n ddr3_ck_n,\n ddr3_cke,\n ddr3_cs_n,\n ddr3_dm,\n ddr3_odt,\n sys_clk_i,\n ui_clk,\n ui_clk_sync_rst,\n mmcm_locked,\n aresetn,\n app_sr_req,\n app_ref_req,\n app_zq_req,\n app_sr_active,\n app_ref_ack,\n app_zq_ack,\n s_axi_awid,\n s_axi_awaddr,\n s_axi_awlen,\n s_axi_awsize,\n s_axi_awburst,\n s_axi_awlock,\n s_axi_awcache,\n s_axi_awprot,\n s_axi_awqos,\n s_axi_awvalid,\n s_axi_awready,\n s_axi_wdata,\n s_axi_wstrb,\n s_axi_wlast,\n s_axi_wvalid,\n s_axi_wready,\n s_axi_bready,\n s_axi_bid,\n s_axi_bresp,\n s_axi_bvalid,\n s_axi_arid,\n s_axi_araddr,\n s_axi_arlen,\n s_axi_arsize,\n s_axi_arburst,\n s_axi_arlock,\n s_axi_arcache,\n s_axi_arprot,\n s_axi_arqos,\n s_axi_arvalid,\n s_axi_arready,\n s_axi_rready,\n s_axi_rid,\n s_axi_rdata,\n s_axi_rresp,\n s_axi_rlast,\n s_axi_rvalid,\n init_calib_complete,\n device_temp,\n sys_rst);\n inout [31:0]ddr3_dq;\n inout [3:0]ddr3_dqs_n;\n inout [3:0]ddr3_dqs_p;\n output [14:0]ddr3_addr;\n output [2:0]ddr3_ba;\n output ddr3_ras_n;\n output ddr3_cas_n;\n output ddr3_we_n;\n output ddr3_reset_n;\n output [0:0]ddr3_ck_p;\n output [0:0]ddr3_ck_n;\n output [0:0]ddr3_cke;\n output [0:0]ddr3_cs_n;\n output [3:0]ddr3_dm;\n output [0:0]ddr3_odt;\n input sys_clk_i;\n output ui_clk;\n output ui_clk_sync_rst;\n output mmcm_locked;\n input aresetn;\n input app_sr_req;\n input app_ref_req;\n input app_zq_req;\n output app_sr_active;\n output app_ref_ack;\n output app_zq_ack;\n input [0:0]s_axi_awid;\n input [29:0]s_axi_awaddr;\n input [7:0]s_axi_awlen;\n input [2:0]s_axi_awsize;\n input [1:0]s_axi_awburst;\n input [0:0]s_axi_awlock;\n input [3:0]s_axi_awcache;\n input [2:0]s_axi_awprot;\n input [3:0]s_axi_awqos;\n input s_axi_awvalid;\n output s_axi_awready;\n input [255:0]s_axi_wdata;\n input [31:0]s_axi_wstrb;\n input s_axi_wlast;\n input s_axi_wvalid;\n output s_axi_wready;\n input s_axi_bready;\n output [0:0]s_axi_bid;\n output [1:0]s_axi_bresp;\n output s_axi_bvalid;\n input [0:0]s_axi_arid;\n input [29:0]s_axi_araddr;\n input [7:0]s_axi_arlen;\n input [2:0]s_axi_arsize;\n input [1:0]s_axi_arburst;\n input [0:0]s_axi_arlock;\n input [3:0]s_axi_arcache;\n input [2:0]s_axi_arprot;\n input [3:0]s_axi_arqos;\n input s_axi_arvalid;\n output s_axi_arready;\n input s_axi_rready;\n output [0:0]s_axi_rid;\n output [255:0]s_axi_rdata;\n output [1:0]s_axi_rresp;\n output s_axi_rlast;\n output s_axi_rvalid;\n output init_calib_complete;\n output [11:0]device_temp;\n input sys_rst;\n\n wire \\ ;\n wire app_ref_ack;\n wire app_ref_req;\n wire app_sr_active;\n wire app_sr_req;\n wire app_zq_ack;\n wire app_zq_req;\n wire aresetn;\n wire [14:0]ddr3_addr;\n wire [2:0]ddr3_ba;\n wire ddr3_cas_n;\n wire [0:0]ddr3_ck_n;\n wire [0:0]ddr3_ck_p;\n wire [0:0]ddr3_cke;\n wire [0:0]ddr3_cs_n;\n wire [3:0]ddr3_dm;\n (* IBUF_LOW_PWR = 0 *) wire [31:0]ddr3_dq;\n (* DIFF_TERM = 0 *) (* IBUF_LOW_PWR = 0 *) wire [3:0]ddr3_dqs_n;\n (* DIFF_TERM = 0 *) (* IBUF_LOW_PWR = 0 *) wire [3:0]ddr3_dqs_p;\n wire [0:0]ddr3_odt;\n wire ddr3_ras_n;\n (* DRIVE = \"12\" *) wire ddr3_reset_n;\n wire ddr3_we_n;\n wire [11:0]device_temp;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire init_calib_complete;\n wire \\lim_state_reg[6]_i_23_n_0 ;\n wire mmcm_locked;\n wire [29:0]s_axi_araddr;\n wire [1:0]s_axi_arburst;\n wire [0:0]s_axi_arid;\n wire [7:0]s_axi_arlen;\n wire s_axi_arready;\n wire s_axi_arvalid;\n wire [29:0]s_axi_awaddr;\n wire [1:0]s_axi_awburst;\n wire [0:0]s_axi_awid;\n wire [7:0]s_axi_awlen;\n wire s_axi_awready;\n wire s_axi_awvalid;\n wire [0:0]s_axi_bid;\n wire s_axi_bready;\n wire s_axi_bvalid;\n wire [255:0]s_axi_rdata;\n wire [0:0]s_axi_rid;\n wire s_axi_rlast;\n wire s_axi_rready;\n wire [1:1]\\^s_axi_rresp ;\n wire s_axi_rvalid;\n wire [255:0]s_axi_wdata;\n wire s_axi_wready;\n wire [31:0]s_axi_wstrb;\n wire s_axi_wvalid;\n wire \\stg2_target_r_reg[1]_i_2_n_0 ;\n wire stg3_dec2init_val_r_reg_i_11_n_0;\n wire sys_clk_i;\n wire sys_rst;\n wire u_ddr3_if_mig_n_112;\n wire u_ddr3_if_mig_n_113;\n wire u_ddr3_if_mig_n_127;\n wire [49:0]\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address ;\n wire [11:0]\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank ;\n wire [2:0]\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cas_n ;\n wire [3:3]\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cke ;\n wire [2:0]\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cs_n ;\n wire [0:0]\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_odt ;\n wire [1:0]\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_ras_n ;\n wire [2:0]\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_we_n ;\n wire \\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk ;\n wire \\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk ;\n wire \\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk ;\n wire \\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk ;\n wire [23:0]\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out ;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) wire \\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ;\n wire [3:0]\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ;\n wire [3:0]\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr ;\n wire [59:2]\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out ;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) wire \\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ;\n wire [3:0]\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ;\n wire [3:0]\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr ;\n wire [77:2]\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out ;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) wire \\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ;\n wire [3:0]\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ;\n wire [3:0]\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr ;\n wire ui_clk;\n wire ui_clk_sync_rst;\n wire [1:0]\\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED ;\n\n assign s_axi_bresp[1] = \\ ;\n assign s_axi_bresp[0] = \\ ;\n assign s_axi_rresp[1] = \\^s_axi_rresp [1];\n assign s_axi_rresp[0] = \\ ;\n GND GND\n (.G(\\ ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M \\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cs_n [1:0]),\n .DIB({1'b1,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cs_n [2]}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [1:0]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [3:2]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [5:4]),\n .DOD(\\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M \\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({1'b0,1'b0}),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [13:12]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [15:14]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [23:22]),\n .DOD(\\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M \\ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({1'b0,1'b0}),\n .DIB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_we_n [1:0]),\n .DIC({1'b1,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_we_n [2]}),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [7:6]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [9:8]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [11:10]),\n .DOD(\\NLW_ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M \\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({1'b0,1'b0}),\n .DIB({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [29],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [14]}),\n .DIC({init_calib_complete,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [44]}),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [31:30]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [33:32]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [35:34]),\n .DOD(\\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M \\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({1'b0,1'b0}),\n .DIB({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_odt ,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_odt }),\n .DIC({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_odt ,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_odt }),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [43:42]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [45:44]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [47:46]),\n .DOD(\\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M \\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({1'b0,1'b0}),\n .DIB({1'b0,1'b0}),\n .DIC({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cke ,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cke }),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [49:48]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [51:50]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [53:52]),\n .DOD(\\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M \\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cke ,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cke }),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [55:54]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [57:56]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [59:58]),\n .DOD(\\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M \\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({1'b0,1'b0}),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [7:6]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [3:2]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [5:4]),\n .DOD(\\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M \\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({1'b0,1'b0}),\n .DIB({1'b0,1'b0}),\n .DIC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cas_n [1:0]),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [13:12]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [15:14]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [17:16]),\n .DOD(\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M \\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({1'b1,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cas_n [2]}),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [19:18]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [21:20]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [23:22]),\n .DOD(\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M \\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_ras_n ),\n .DIB({1'b1,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cs_n [2]}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [25:24]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [27:26]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [29:28]),\n .DOD(\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M \\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({1'b0,1'b0}),\n .DIB({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [3],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [0]}),\n .DIC({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [9],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [6]}),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [31:30]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [33:32]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [35:34]),\n .DOD(\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M \\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({1'b0,1'b0}),\n .DIB({1'b0,1'b0}),\n .DIC({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [19],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [4]}),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [37:36]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [39:38]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [41:40]),\n .DOD(\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M \\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [49],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [34]}),\n .DIB({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [5],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [2]}),\n .DIC({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [11],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [8]}),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [43:42]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [45:44]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [47:46]),\n .DOD(\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M \\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [16],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [1]}),\n .DIB({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [46],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [31]}),\n .DIC({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [15],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [0]}),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [49:48]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [51:50]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [53:52]),\n .DOD(\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M \\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [45],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [30]}),\n .DIB({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [17],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [2]}),\n .DIC({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [47],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [32]}),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [55:54]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [57:56]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [59:58]),\n .DOD(\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M \\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({1'b0,1'b0}),\n .DIB({1'b0,1'b0}),\n .DIC({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [18],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [3]}),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [61:60]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [63:62]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [65:64]),\n .DOD(\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M \\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [48],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [33]}),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [67:66]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [69:68]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [71:70]),\n .DOD(\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M \\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({1'b0,1'b0}),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [7:6]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [3:2]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [5:4]),\n .DOD(\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M \\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 \n (.ADDRA({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRB({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRC({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr }),\n .ADDRD({1'b0,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),\n .DIA({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [4],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [1]}),\n .DIB({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [10],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [7]}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [73:72]),\n .DOB(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [75:74]),\n .DOC(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [77:76]),\n .DOD(\\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED [1:0]),\n .WCLK(ui_clk),\n .WE(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));\n LUT1 #(\n .INIT(2'h1)) \n \\lim_state_reg[6]_i_23 \n (.I0(u_ddr3_if_mig_n_113),\n .O(\\lim_state_reg[6]_i_23_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\stg2_target_r_reg[1]_i_2 \n (.I0(u_ddr3_if_mig_n_127),\n .O(\\stg2_target_r_reg[1]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n stg3_dec2init_val_r_reg_i_11\n (.I0(u_ddr3_if_mig_n_112),\n .O(stg3_dec2init_val_r_reg_i_11_n_0));\n ddr3_if_ddr3_if_mig u_ddr3_if_mig\n (.CLKB0(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk ),\n .CLKB0_7(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk ),\n .CLKB0_8(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk ),\n .CLKB0_9(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk ),\n .D(u_ddr3_if_mig_n_127),\n .Q(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ),\n .app_ref_ack(app_ref_ack),\n .app_ref_req(app_ref_req),\n .app_sr_active(app_sr_active),\n .app_sr_req(app_sr_req),\n .app_zq_ack(app_zq_ack),\n .app_zq_req(app_zq_req),\n .aresetn(aresetn),\n .ddr3_addr(ddr3_addr),\n .ddr3_ba(ddr3_ba),\n .ddr3_cas_n(ddr3_cas_n),\n .ddr3_cke(ddr3_cke),\n .ddr3_cs_n(ddr3_cs_n),\n .ddr3_dm(ddr3_dm),\n .ddr3_dq(ddr3_dq),\n .ddr3_dqs_n(ddr3_dqs_n),\n .ddr3_dqs_p(ddr3_dqs_p),\n .ddr3_odt(ddr3_odt),\n .ddr3_ras_n(ddr3_ras_n),\n .ddr3_reset_n(ddr3_reset_n),\n .ddr3_we_n(ddr3_we_n),\n .ddr_ck_out({ddr3_ck_n,ddr3_ck_p}),\n .iserdes_clk(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk ),\n .iserdes_clk_2(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk ),\n .iserdes_clk_3(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk ),\n .iserdes_clk_4(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk ),\n .mem_out({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [23:22],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [15:0]}),\n .\\mmcm_current_reg[0] (stg3_dec2init_val_r_reg_i_11_n_0),\n .\\mmcm_init_trail_reg[0] (\\lim_state_reg[6]_i_23_n_0 ),\n .mmcm_locked(mmcm_locked),\n .out(device_temp),\n .phy_dout({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cke ,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_odt ,init_calib_complete,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [44],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [29],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [14]}),\n .rd_ptr(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr ),\n .rd_ptr_0(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_ptr ),\n .rd_ptr_1(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_ptr ),\n .\\rd_ptr_reg[3] ({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [77:12],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [5:2],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [7:6]}),\n .\\rd_ptr_reg[3]_0 ({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [59:42],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [35:30],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [5:2],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [7:6]}),\n .\\rd_ptr_timing_reg[0] ({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [10],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [7],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [4],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [1],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [48],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [33],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [18],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [3],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [47],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [32],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [17],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [2],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [45],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [30],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [15],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [0],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [46],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [31],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [16],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [1],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [11],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [8],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [5],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [2],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [49],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [34],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [19],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_address [4],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [9],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [6],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [3],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_bank [0],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cs_n [2],\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_ras_n ,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cas_n }),\n .\\rd_ptr_timing_reg[0]_0 ({\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_we_n ,\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/mux_cs_n [1:0]}),\n .s_axi_araddr(s_axi_araddr),\n .s_axi_arburst(s_axi_arburst[1]),\n .s_axi_arid(s_axi_arid),\n .s_axi_arlen(s_axi_arlen),\n .s_axi_arready(s_axi_arready),\n .s_axi_arvalid(s_axi_arvalid),\n .s_axi_awaddr(s_axi_awaddr),\n .s_axi_awburst(s_axi_awburst[1]),\n .s_axi_awid(s_axi_awid),\n .s_axi_awlen(s_axi_awlen),\n .s_axi_awready(s_axi_awready),\n .s_axi_awvalid(s_axi_awvalid),\n .s_axi_bid(s_axi_bid),\n .s_axi_bready(s_axi_bready),\n .s_axi_bvalid(s_axi_bvalid),\n .s_axi_rdata(s_axi_rdata),\n .s_axi_rid(s_axi_rid),\n .s_axi_rlast(s_axi_rlast),\n .s_axi_rready(s_axi_rready),\n .s_axi_rresp(\\^s_axi_rresp ),\n .s_axi_rvalid(s_axi_rvalid),\n .s_axi_wdata(s_axi_wdata),\n .s_axi_wready(s_axi_wready),\n .s_axi_wstrb(s_axi_wstrb),\n .s_axi_wvalid(s_axi_wvalid),\n .stg3_dec2init_val_r_reg(u_ddr3_if_mig_n_112),\n .stg3_inc2init_val_r_reg(u_ddr3_if_mig_n_113),\n .\\stg3_r_reg[0] (\\stg2_target_r_reg[1]_i_2_n_0 ),\n .sys_clk_i(sys_clk_i),\n .sys_rst(sys_rst),\n .ui_clk(ui_clk),\n .ui_clk_sync_rst(ui_clk_sync_rst),\n .wr_en(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ),\n .wr_en_5(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ),\n .wr_en_6(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ),\n .\\wr_ptr_timing_reg[2] (\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ),\n .\\wr_ptr_timing_reg[2]_0 (\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ));\nendmodule\n\nmodule ddr3_if_ddr3_if_mig\n (ui_clk,\n app_ref_ack,\n app_zq_ack,\n app_sr_active,\n ddr3_reset_n,\n ddr3_cas_n,\n ddr3_ras_n,\n ddr3_we_n,\n ddr3_addr,\n ddr3_ba,\n ddr3_cs_n,\n ddr3_odt,\n ddr3_cke,\n ddr3_dm,\n rd_ptr,\n rd_ptr_0,\n rd_ptr_1,\n ui_clk_sync_rst,\n iserdes_clk,\n iserdes_clk_2,\n iserdes_clk_3,\n iserdes_clk_4,\n phy_dout,\n out,\n mmcm_locked,\n \\rd_ptr_timing_reg[0] ,\n \\rd_ptr_timing_reg[0]_0 ,\n stg3_dec2init_val_r_reg,\n stg3_inc2init_val_r_reg,\n s_axi_arready,\n Q,\n \\wr_ptr_timing_reg[2] ,\n \\wr_ptr_timing_reg[2]_0 ,\n D,\n wr_en,\n wr_en_5,\n wr_en_6,\n ddr_ck_out,\n s_axi_awready,\n s_axi_wready,\n s_axi_rdata,\n s_axi_rresp,\n s_axi_rid,\n s_axi_bid,\n s_axi_bvalid,\n s_axi_rvalid,\n s_axi_rlast,\n ddr3_dq,\n ddr3_dqs_p,\n ddr3_dqs_n,\n app_ref_req,\n app_zq_req,\n app_sr_req,\n CLKB0,\n CLKB0_7,\n CLKB0_8,\n CLKB0_9,\n mem_out,\n \\rd_ptr_reg[3] ,\n \\rd_ptr_reg[3]_0 ,\n sys_rst,\n s_axi_arvalid,\n sys_clk_i,\n \\mmcm_init_trail_reg[0] ,\n \\mmcm_current_reg[0] ,\n \\stg3_r_reg[0] ,\n s_axi_awlen,\n s_axi_bready,\n s_axi_awvalid,\n s_axi_awaddr,\n s_axi_awburst,\n s_axi_wvalid,\n s_axi_awid,\n s_axi_arlen,\n s_axi_araddr,\n s_axi_arburst,\n s_axi_rready,\n s_axi_wstrb,\n s_axi_wdata,\n aresetn,\n s_axi_arid);\n output ui_clk;\n output app_ref_ack;\n output app_zq_ack;\n output app_sr_active;\n output ddr3_reset_n;\n output ddr3_cas_n;\n output ddr3_ras_n;\n output ddr3_we_n;\n output [14:0]ddr3_addr;\n output [2:0]ddr3_ba;\n output [0:0]ddr3_cs_n;\n output [0:0]ddr3_odt;\n output [0:0]ddr3_cke;\n output [3:0]ddr3_dm;\n output [3:0]rd_ptr;\n output [3:0]rd_ptr_0;\n output [3:0]rd_ptr_1;\n output ui_clk_sync_rst;\n output iserdes_clk;\n output iserdes_clk_2;\n output iserdes_clk_3;\n output iserdes_clk_4;\n output [5:0]phy_dout;\n output [11:0]out;\n output mmcm_locked;\n output [37:0]\\rd_ptr_timing_reg[0] ;\n output [4:0]\\rd_ptr_timing_reg[0]_0 ;\n output stg3_dec2init_val_r_reg;\n output stg3_inc2init_val_r_reg;\n output s_axi_arready;\n output [3:0]Q;\n output [3:0]\\wr_ptr_timing_reg[2] ;\n output [3:0]\\wr_ptr_timing_reg[2]_0 ;\n output [0:0]D;\n output wr_en;\n output wr_en_5;\n output wr_en_6;\n output [1:0]ddr_ck_out;\n output s_axi_awready;\n output s_axi_wready;\n output [255:0]s_axi_rdata;\n output [0:0]s_axi_rresp;\n output [0:0]s_axi_rid;\n output [0:0]s_axi_bid;\n output s_axi_bvalid;\n output s_axi_rvalid;\n output s_axi_rlast;\n inout [31:0]ddr3_dq;\n inout [3:0]ddr3_dqs_p;\n inout [3:0]ddr3_dqs_n;\n input app_ref_req;\n input app_zq_req;\n input app_sr_req;\n input CLKB0;\n input CLKB0_7;\n input CLKB0_8;\n input CLKB0_9;\n input [17:0]mem_out;\n input [71:0]\\rd_ptr_reg[3] ;\n input [29:0]\\rd_ptr_reg[3]_0 ;\n input sys_rst;\n input s_axi_arvalid;\n input sys_clk_i;\n input \\mmcm_init_trail_reg[0] ;\n input \\mmcm_current_reg[0] ;\n input \\stg3_r_reg[0] ;\n input [7:0]s_axi_awlen;\n input s_axi_bready;\n input s_axi_awvalid;\n input [29:0]s_axi_awaddr;\n input [0:0]s_axi_awburst;\n input s_axi_wvalid;\n input [0:0]s_axi_awid;\n input [7:0]s_axi_arlen;\n input [29:0]s_axi_araddr;\n input [0:0]s_axi_arburst;\n input s_axi_rready;\n input [31:0]s_axi_wstrb;\n input [255:0]s_axi_wdata;\n input aresetn;\n input [0:0]s_axi_arid;\n\n wire CLKB0;\n wire CLKB0_7;\n wire CLKB0_8;\n wire CLKB0_9;\n wire [0:0]D;\n wire [3:0]Q;\n wire app_ref_ack;\n wire app_ref_req;\n wire app_sr_active;\n wire app_sr_req;\n wire app_zq_ack;\n wire app_zq_req;\n wire aresetn;\n wire [14:0]ddr3_addr;\n wire [2:0]ddr3_ba;\n wire ddr3_cas_n;\n wire [0:0]ddr3_cke;\n wire [0:0]ddr3_cs_n;\n wire [3:0]ddr3_dm;\n wire [31:0]ddr3_dq;\n wire [3:0]ddr3_dqs_n;\n wire [3:0]ddr3_dqs_p;\n wire [0:0]ddr3_odt;\n wire ddr3_ras_n;\n wire ddr3_reset_n;\n wire ddr3_we_n;\n wire [1:0]ddr_ck_out;\n wire freq_refclk;\n wire [1:1]iodelay_ctrl_rdy;\n wire iserdes_clk;\n wire iserdes_clk_2;\n wire iserdes_clk_3;\n wire iserdes_clk_4;\n wire \\mem_intfc0/ddr_phy_top0/phy_mc_go ;\n wire \\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/pi_cnt_dec ;\n wire \\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/samp_edge_cnt0_en_r ;\n wire [11:0]\\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_100 ;\n wire \\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/po_cnt_dec ;\n wire \\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_samp/sm_r ;\n wire \\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/cnt_pwron_reset_done_r0 ;\n wire \\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/p_81_in ;\n wire \\mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/RST0 ;\n wire \\mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/bm_end_r1 ;\n wire \\mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/rtp_timer_ns1 ;\n wire \\mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/pass_open_bank_r ;\n wire \\mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/bm_end_r1 ;\n wire \\mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/pass_open_bank_r ;\n wire \\mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/bm_end_r1 ;\n wire \\mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/rtp_timer_ns1 ;\n wire \\mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/pass_open_bank_r ;\n wire \\mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/bm_end_r1 ;\n wire \\mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/rtp_timer_ns1 ;\n wire \\mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/pass_open_bank_r ;\n wire [17:0]mem_out;\n wire mem_refclk;\n wire \\mmcm_current_reg[0] ;\n wire \\mmcm_init_trail_reg[0] ;\n wire mmcm_locked;\n wire mmcm_ps_clk;\n wire [11:0]out;\n wire [5:0]phy_dout;\n wire pll_locked;\n wire poc_sample_pd;\n wire psdone;\n wire psen;\n wire [3:0]rd_ptr;\n wire [3:0]rd_ptr_0;\n wire [3:0]rd_ptr_1;\n wire [71:0]\\rd_ptr_reg[3] ;\n wire [29:0]\\rd_ptr_reg[3]_0 ;\n wire [37:0]\\rd_ptr_timing_reg[0] ;\n wire [4:0]\\rd_ptr_timing_reg[0]_0 ;\n (* MAX_FANOUT = \"10\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire rst_sync_r1;\n wire [29:0]s_axi_araddr;\n wire [0:0]s_axi_arburst;\n wire [0:0]s_axi_arid;\n wire [7:0]s_axi_arlen;\n wire s_axi_arready;\n wire s_axi_arvalid;\n wire [29:0]s_axi_awaddr;\n wire [0:0]s_axi_awburst;\n wire [0:0]s_axi_awid;\n wire [7:0]s_axi_awlen;\n wire s_axi_awready;\n wire s_axi_awvalid;\n wire [0:0]s_axi_bid;\n wire s_axi_bready;\n wire s_axi_bvalid;\n wire [255:0]s_axi_rdata;\n wire [0:0]s_axi_rid;\n wire s_axi_rlast;\n wire s_axi_rready;\n wire [0:0]s_axi_rresp;\n wire s_axi_rvalid;\n wire [255:0]s_axi_wdata;\n wire s_axi_wready;\n wire [31:0]s_axi_wstrb;\n wire s_axi_wvalid;\n wire stg3_dec2init_val_r_reg;\n wire stg3_inc2init_val_r_reg;\n wire \\stg3_r_reg[0] ;\n wire sync_pulse;\n wire sys_clk_i;\n wire sys_rst;\n wire sys_rst_act_hi;\n wire u_ddr3_clk_ibuf_n_0;\n wire u_ddr3_infrastructure_n_10;\n wire u_ddr3_infrastructure_n_11;\n wire u_ddr3_infrastructure_n_13;\n wire u_ddr3_infrastructure_n_14;\n wire u_ddr3_infrastructure_n_15;\n wire u_ddr3_infrastructure_n_16;\n wire u_ddr3_infrastructure_n_17;\n wire u_ddr3_infrastructure_n_18;\n wire u_ddr3_infrastructure_n_19;\n wire u_ddr3_infrastructure_n_20;\n wire u_ddr3_infrastructure_n_21;\n wire u_ddr3_infrastructure_n_22;\n wire u_ddr3_infrastructure_n_23;\n wire u_ddr3_infrastructure_n_24;\n wire u_ddr3_infrastructure_n_25;\n wire u_ddr3_infrastructure_n_26;\n wire u_ddr3_infrastructure_n_27;\n wire u_ddr3_infrastructure_n_28;\n wire u_ddr3_infrastructure_n_29;\n wire u_ddr3_infrastructure_n_30;\n wire u_ddr3_infrastructure_n_31;\n wire u_ddr3_infrastructure_n_32;\n wire u_ddr3_infrastructure_n_33;\n wire u_ddr3_infrastructure_n_34;\n wire u_ddr3_infrastructure_n_35;\n wire u_ddr3_infrastructure_n_36;\n wire u_ddr3_infrastructure_n_37;\n wire u_ddr3_infrastructure_n_38;\n wire u_ddr3_infrastructure_n_40;\n wire u_ddr3_infrastructure_n_41;\n wire u_ddr3_infrastructure_n_44;\n wire u_ddr3_infrastructure_n_47;\n wire u_ddr3_infrastructure_n_48;\n wire u_ddr3_infrastructure_n_49;\n wire u_ddr3_infrastructure_n_50;\n wire u_ddr3_infrastructure_n_51;\n wire u_ddr3_infrastructure_n_52;\n wire u_ddr3_infrastructure_n_53;\n wire u_ddr3_infrastructure_n_54;\n wire u_ddr3_infrastructure_n_56;\n wire u_ddr3_infrastructure_n_58;\n wire u_ddr3_infrastructure_n_9;\n wire u_memc_ui_top_axi_n_111;\n wire u_memc_ui_top_axi_n_114;\n wire u_memc_ui_top_axi_n_116;\n wire u_memc_ui_top_axi_n_117;\n wire u_memc_ui_top_axi_n_119;\n wire u_memc_ui_top_axi_n_120;\n wire u_memc_ui_top_axi_n_121;\n wire u_memc_ui_top_axi_n_64;\n wire ui_clk;\n wire ui_clk_sync_rst;\n wire wr_en;\n wire wr_en_5;\n wire wr_en_6;\n wire [3:0]\\wr_ptr_timing_reg[2] ;\n wire [3:0]\\wr_ptr_timing_reg[2]_0 ;\n\n ddr3_if_mig_7series_v4_0_tempmon \\temp_mon_enabled.u_tempmon \n (.CLK(ui_clk),\n .D(\\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_100 ),\n .in0(ui_clk_sync_rst),\n .mmcm_clk(u_ddr3_clk_ibuf_n_0),\n .out(out));\n ddr3_if_mig_7series_v4_0_clk_ibuf u_ddr3_clk_ibuf\n (.mmcm_clk(u_ddr3_clk_ibuf_n_0),\n .sys_clk_i(sys_clk_i));\n ddr3_if_mig_7series_v4_0_infrastructure u_ddr3_infrastructure\n (.AS(sys_rst_act_hi),\n .CLK(ui_clk),\n .E(psen),\n .RST0(\\mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/RST0 ),\n .SR(u_ddr3_infrastructure_n_14),\n .SS(u_ddr3_infrastructure_n_16),\n .bm_end_r1(\\mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/bm_end_r1 ),\n .bm_end_r1_5(\\mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/bm_end_r1 ),\n .bm_end_r1_6(\\mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/bm_end_r1 ),\n .bm_end_r1_7(\\mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/bm_end_r1 ),\n .cal2_done_r_reg(u_ddr3_infrastructure_n_18),\n .cal2_if_reset_reg(u_ddr3_infrastructure_n_17),\n .cnt_pwron_reset_done_r0(\\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/cnt_pwron_reset_done_r0 ),\n .\\complex_address_reg[0] (u_ddr3_infrastructure_n_24),\n .\\complex_num_reads_dec_reg[0] (u_ddr3_infrastructure_n_31),\n .complex_sample_cnt_inc_reg(u_ddr3_infrastructure_n_25),\n .\\dec_cnt_reg[0] (u_ddr3_infrastructure_n_26),\n .\\en_cnt_div4.enable_wrlvl_cnt_reg[2] (u_ddr3_infrastructure_n_23),\n .\\en_cnt_div4.enable_wrlvl_cnt_reg[4] (u_ddr3_infrastructure_n_54),\n .\\en_cnt_div4.wrlvl_odt_reg (u_memc_ui_top_axi_n_119),\n .fine_adjust_reg(u_memc_ui_top_axi_n_64),\n .\\fine_pi_dec_cnt_reg[0] (u_ddr3_infrastructure_n_21),\n .freq_refclk(freq_refclk),\n .\\gen_final_tap[2].final_val_reg[2][0] (u_ddr3_infrastructure_n_29),\n .in0(ui_clk_sync_rst),\n .\\last_master_r_reg[2] (u_ddr3_infrastructure_n_34),\n .\\lim_state_reg[0] (u_memc_ui_top_axi_n_116),\n .mem_refclk(mem_refclk),\n .mmcm_clk(u_ddr3_clk_ibuf_n_0),\n .mmcm_locked(mmcm_locked),\n .mmcm_ps_clk(mmcm_ps_clk),\n .mpr_rank_done_r_reg({u_ddr3_infrastructure_n_27,u_ddr3_infrastructure_n_28}),\n .\\oneeighty_r_reg[0] (u_ddr3_infrastructure_n_38),\n .\\oneeighty_r_reg[0]_0 (u_ddr3_infrastructure_n_41),\n .p_81_in(\\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/p_81_in ),\n .pass_open_bank_r(\\mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/pass_open_bank_r ),\n .pass_open_bank_r_2(\\mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/pass_open_bank_r ),\n .pass_open_bank_r_3(\\mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/pass_open_bank_r ),\n .pass_open_bank_r_4(\\mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/pass_open_bank_r ),\n .phy_mc_go(\\mem_intfc0/ddr_phy_top0/phy_mc_go ),\n .pi_cnt_dec(\\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/pi_cnt_dec ),\n .\\pi_rst_stg1_cal_r_reg[1] (u_ddr3_infrastructure_n_51),\n .pll_locked(pll_locked),\n .po_cnt_dec(\\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/po_cnt_dec ),\n .poc_backup_r_reg(u_memc_ui_top_axi_n_117),\n .poc_sample_pd(poc_sample_pd),\n .pre_wait_r_reg(u_ddr3_infrastructure_n_44),\n .psdone(psdone),\n .ras_timer_zero_r_reg(u_ddr3_infrastructure_n_47),\n .ras_timer_zero_r_reg_0(u_ddr3_infrastructure_n_48),\n .ras_timer_zero_r_reg_1(u_ddr3_infrastructure_n_49),\n .ras_timer_zero_r_reg_2(u_ddr3_infrastructure_n_50),\n .\\rd_ptr_timing_reg[2] (u_ddr3_infrastructure_n_15),\n .\\read_fifo.head_r_reg[0] (u_ddr3_infrastructure_n_13),\n .reset_reg(u_ddr3_infrastructure_n_10),\n .\\resume_wait_r_reg[10] (u_memc_ui_top_axi_n_111),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] (u_ddr3_infrastructure_n_35),\n .\\row_cnt_victim_rotate.complex_row_cnt_reg[7] (u_memc_ui_top_axi_n_121),\n .rst_out_reg(u_ddr3_infrastructure_n_22),\n .\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] (u_memc_ui_top_axi_n_114),\n .rst_sync_r1(rst_sync_r1),\n .rtp_timer_ns1(\\mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/rtp_timer_ns1 ),\n .rtp_timer_ns1_0(\\mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/rtp_timer_ns1 ),\n .rtp_timer_ns1_1(\\mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/rtp_timer_ns1 ),\n .\\rtp_timer_r_reg[0] (u_ddr3_infrastructure_n_33),\n .samp_edge_cnt0_en_r(\\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/samp_edge_cnt0_en_r ),\n .\\samp_edge_cnt0_r_reg[11] (u_ddr3_infrastructure_n_52),\n .\\simp_stg3_final_r_reg[17] (u_ddr3_infrastructure_n_11),\n .sm_r(\\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_samp/sm_r ),\n .\\stg3_r_reg[1] (u_ddr3_infrastructure_n_40),\n .\\stg3_tap_cnt_reg[0] (u_ddr3_infrastructure_n_9),\n .sync_pulse(sync_pulse),\n .\\two_dec_max_limit_reg[11] (u_ddr3_infrastructure_n_20),\n .\\victim_sel_rotate.sel_reg[31] (u_ddr3_infrastructure_n_32),\n .\\wait_cnt_r_reg[3] (u_ddr3_infrastructure_n_53),\n .\\wait_cnt_reg[3] (u_ddr3_infrastructure_n_36),\n .\\wait_cnt_reg[3]_0 (u_ddr3_infrastructure_n_58),\n .\\wl_tap_count_r_reg[0] (u_ddr3_infrastructure_n_30),\n .wr_victim_inc_reg(u_memc_ui_top_axi_n_120),\n .\\wr_victim_sel_ocal_reg[2] (u_ddr3_infrastructure_n_56),\n .\\wrcal_dqs_cnt_r_reg[2] (u_ddr3_infrastructure_n_19),\n .\\wrcal_reads_reg[0] (u_ddr3_infrastructure_n_37));\n ddr3_if_mig_7series_v4_0_iodelay_ctrl u_iodelay_ctrl\n (.AS(sys_rst_act_hi),\n .mmcm_clk(u_ddr3_clk_ibuf_n_0),\n .rst_sync_r1_reg(iodelay_ctrl_rdy),\n .sys_rst(sys_rst));\n (* X_CORE_INFO = \"mig_7series_v4_0_ddr3_7Series, ddr3_if, 2016.2\" *) \n ddr3_if_mig_7series_v4_0_memc_ui_top_axi u_memc_ui_top_axi\n (.CLK(ui_clk),\n .CLKB0(CLKB0),\n .CLKB0_7(CLKB0_7),\n .CLKB0_8(CLKB0_8),\n .CLKB0_9(CLKB0_9),\n .D(D),\n .E(psen),\n .Q(Q),\n .RST0(\\mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/RST0 ),\n .SR(u_ddr3_infrastructure_n_14),\n .SS(u_ddr3_infrastructure_n_16),\n .app_ref_ack(app_ref_ack),\n .app_ref_req(app_ref_req),\n .app_sr_active(app_sr_active),\n .app_sr_req(app_sr_req),\n .app_zq_ack(app_zq_ack),\n .app_zq_req(app_zq_req),\n .aresetn(aresetn),\n .bm_end_r1(\\mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/bm_end_r1 ),\n .bm_end_r1_0(\\mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/bm_end_r1 ),\n .bm_end_r1_2(\\mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/bm_end_r1 ),\n .bm_end_r1_4(\\mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/bm_end_r1 ),\n .bm_end_r1_reg(u_ddr3_infrastructure_n_49),\n .bm_end_r1_reg_0(u_ddr3_infrastructure_n_48),\n .bm_end_r1_reg_1(u_ddr3_infrastructure_n_47),\n .bm_end_r1_reg_2(u_ddr3_infrastructure_n_50),\n .cnt_pwron_reset_done_r0(\\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/cnt_pwron_reset_done_r0 ),\n .\\complex_row_cnt_ocal_reg[0] (u_memc_ui_top_axi_n_120),\n .ddr3_addr(ddr3_addr),\n .ddr3_ba(ddr3_ba),\n .ddr3_cas_n(ddr3_cas_n),\n .ddr3_cke(ddr3_cke),\n .ddr3_cs_n(ddr3_cs_n),\n .ddr3_dm(ddr3_dm),\n .ddr3_dq(ddr3_dq),\n .ddr3_dqs_n(ddr3_dqs_n),\n .ddr3_dqs_p(ddr3_dqs_p),\n .ddr3_odt(ddr3_odt),\n .ddr3_ras_n(ddr3_ras_n),\n .ddr3_reset_n(ddr3_reset_n),\n .ddr3_we_n(ddr3_we_n),\n .ddr_ck_out(ddr_ck_out),\n .\\device_temp_r_reg[11] (\\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_100 ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (iserdes_clk),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (iserdes_clk_2),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (iserdes_clk_3),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (iserdes_clk_4),\n .\\en_cnt_div4.enable_wrlvl_cnt_reg[3] (u_memc_ui_top_axi_n_119),\n .fine_adjust_reg(u_ddr3_infrastructure_n_51),\n .freq_refclk(freq_refclk),\n .in0(ui_clk_sync_rst),\n .mem_out(mem_out),\n .mem_refclk(mem_refclk),\n .\\mmcm_current_reg[0] (\\mmcm_current_reg[0] ),\n .\\mmcm_init_trail_reg[0] (\\mmcm_init_trail_reg[0] ),\n .mmcm_locked(mmcm_locked),\n .mmcm_ps_clk(mmcm_ps_clk),\n .out({s_axi_rresp,s_axi_rdata}),\n .p_81_in(\\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/p_81_in ),\n .pass_open_bank_r(\\mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/pass_open_bank_r ),\n .pass_open_bank_r_1(\\mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/pass_open_bank_r ),\n .pass_open_bank_r_3(\\mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/pass_open_bank_r ),\n .pass_open_bank_r_5(\\mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/pass_open_bank_r ),\n .pass_open_bank_r_lcl_reg(u_ddr3_infrastructure_n_44),\n .phy_dout(phy_dout),\n .phy_mc_go(\\mem_intfc0/ddr_phy_top0/phy_mc_go ),\n .pi_cnt_dec(\\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/pi_cnt_dec ),\n .pi_cnt_dec_reg(u_ddr3_infrastructure_n_53),\n .\\pi_rst_stg1_cal_r_reg[0] (u_memc_ui_top_axi_n_64),\n .pll_locked(pll_locked),\n .po_cnt_dec(\\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/po_cnt_dec ),\n .po_cnt_dec_reg(u_ddr3_infrastructure_n_58),\n .poc_sample_pd(poc_sample_pd),\n .psdone(psdone),\n .\\rd_ptr_reg[3] (\\rd_ptr_reg[3] ),\n .\\rd_ptr_reg[3]_0 (\\rd_ptr_reg[3]_0 ),\n .\\rd_ptr_timing_reg[0] (\\rd_ptr_timing_reg[0] ),\n .\\rd_ptr_timing_reg[0]_0 (\\rd_ptr_timing_reg[0]_0 ),\n .\\rd_ptr_timing_reg[2] (rd_ptr[3]),\n .\\rd_ptr_timing_reg[2]_0 (rd_ptr[2]),\n .\\rd_ptr_timing_reg[2]_1 (rd_ptr[1]),\n .\\rd_ptr_timing_reg[2]_10 (rd_ptr_1[3]),\n .\\rd_ptr_timing_reg[2]_2 (rd_ptr[0]),\n .\\rd_ptr_timing_reg[2]_3 (rd_ptr_0[3]),\n .\\rd_ptr_timing_reg[2]_4 (rd_ptr_0[2]),\n .\\rd_ptr_timing_reg[2]_5 (rd_ptr_0[1]),\n .\\rd_ptr_timing_reg[2]_6 (rd_ptr_0[0]),\n .\\rd_ptr_timing_reg[2]_7 (rd_ptr_1[0]),\n .\\rd_ptr_timing_reg[2]_8 (rd_ptr_1[1]),\n .\\rd_ptr_timing_reg[2]_9 (rd_ptr_1[2]),\n .\\resume_wait_r_reg[5] (u_memc_ui_top_axi_n_111),\n .\\row_cnt_victim_rotate.complex_row_cnt_reg[4] (u_memc_ui_top_axi_n_121),\n .\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] (iodelay_ctrl_rdy),\n .rst_sync_r1(rst_sync_r1),\n .rst_sync_r1_reg(u_memc_ui_top_axi_n_114),\n .rstdiv0_sync_r1_reg_rep__0(u_ddr3_infrastructure_n_13),\n .rstdiv0_sync_r1_reg_rep__10(u_ddr3_infrastructure_n_23),\n .rstdiv0_sync_r1_reg_rep__11(u_ddr3_infrastructure_n_24),\n .rstdiv0_sync_r1_reg_rep__12(u_ddr3_infrastructure_n_25),\n .rstdiv0_sync_r1_reg_rep__13(u_ddr3_infrastructure_n_26),\n .rstdiv0_sync_r1_reg_rep__14({u_ddr3_infrastructure_n_27,u_ddr3_infrastructure_n_28}),\n .rstdiv0_sync_r1_reg_rep__16(u_ddr3_infrastructure_n_29),\n .rstdiv0_sync_r1_reg_rep__17(u_ddr3_infrastructure_n_30),\n .rstdiv0_sync_r1_reg_rep__18(u_ddr3_infrastructure_n_31),\n .rstdiv0_sync_r1_reg_rep__19(u_ddr3_infrastructure_n_32),\n .rstdiv0_sync_r1_reg_rep__2(u_ddr3_infrastructure_n_15),\n .rstdiv0_sync_r1_reg_rep__20(u_ddr3_infrastructure_n_33),\n .rstdiv0_sync_r1_reg_rep__21(u_ddr3_infrastructure_n_34),\n .rstdiv0_sync_r1_reg_rep__22(u_ddr3_infrastructure_n_35),\n .rstdiv0_sync_r1_reg_rep__23(u_ddr3_infrastructure_n_36),\n .rstdiv0_sync_r1_reg_rep__24(u_ddr3_infrastructure_n_37),\n .rstdiv0_sync_r1_reg_rep__24_0(u_ddr3_infrastructure_n_54),\n .rstdiv0_sync_r1_reg_rep__24_1(u_ddr3_infrastructure_n_56),\n .rstdiv0_sync_r1_reg_rep__25(u_ddr3_infrastructure_n_38),\n .rstdiv0_sync_r1_reg_rep__26(u_ddr3_infrastructure_n_10),\n .rstdiv0_sync_r1_reg_rep__26_0(u_ddr3_infrastructure_n_11),\n .rstdiv0_sync_r1_reg_rep__26_1(u_ddr3_infrastructure_n_9),\n .rstdiv0_sync_r1_reg_rep__26_2(u_ddr3_infrastructure_n_40),\n .rstdiv0_sync_r1_reg_rep__4(u_ddr3_infrastructure_n_17),\n .rstdiv0_sync_r1_reg_rep__5(u_ddr3_infrastructure_n_18),\n .rstdiv0_sync_r1_reg_rep__6(u_ddr3_infrastructure_n_19),\n .rstdiv0_sync_r1_reg_rep__7(u_ddr3_infrastructure_n_20),\n .rstdiv0_sync_r1_reg_rep__8(u_ddr3_infrastructure_n_21),\n .rstdiv0_sync_r1_reg_rep__9(u_ddr3_infrastructure_n_22),\n .rtp_timer_ns1(\\mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/rtp_timer_ns1 ),\n .rtp_timer_ns1_6(\\mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/rtp_timer_ns1 ),\n .rtp_timer_ns1_7(\\mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/rtp_timer_ns1 ),\n .s_axi_araddr(s_axi_araddr),\n .s_axi_arburst(s_axi_arburst),\n .s_axi_arid(s_axi_arid),\n .s_axi_arlen(s_axi_arlen),\n .s_axi_arready(s_axi_arready),\n .s_axi_arvalid(s_axi_arvalid),\n .s_axi_awaddr(s_axi_awaddr),\n .s_axi_awburst(s_axi_awburst),\n .s_axi_awid(s_axi_awid),\n .s_axi_awlen(s_axi_awlen),\n .s_axi_awready(s_axi_awready),\n .s_axi_awvalid(s_axi_awvalid),\n .s_axi_bid(s_axi_bid),\n .s_axi_bready(s_axi_bready),\n .s_axi_bvalid(s_axi_bvalid),\n .s_axi_rid(s_axi_rid),\n .s_axi_rlast(s_axi_rlast),\n .s_axi_rready(s_axi_rready),\n .s_axi_rvalid(s_axi_rvalid),\n .s_axi_wdata(s_axi_wdata),\n .s_axi_wready(s_axi_wready),\n .s_axi_wstrb(s_axi_wstrb),\n .s_axi_wvalid(s_axi_wvalid),\n .samp_edge_cnt0_en_r(\\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/samp_edge_cnt0_en_r ),\n .samp_edge_cnt0_en_r_reg(u_ddr3_infrastructure_n_52),\n .sm_r(\\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_samp/sm_r ),\n .\\sm_r_reg[0] (u_memc_ui_top_axi_n_117),\n .\\sm_r_reg[0]_0 (u_ddr3_infrastructure_n_41),\n .\\stg2_tap_cnt_reg[0] (u_memc_ui_top_axi_n_116),\n .stg3_dec2init_val_r_reg(stg3_dec2init_val_r_reg),\n .stg3_inc2init_val_r_reg(stg3_inc2init_val_r_reg),\n .\\stg3_r_reg[0] (\\stg3_r_reg[0] ),\n .sync_pulse(sync_pulse),\n .sys_rst(sys_rst),\n .wr_en(wr_en),\n .wr_en_5(wr_en_5),\n .wr_en_6(wr_en_6),\n .\\wr_ptr_timing_reg[2] (\\wr_ptr_timing_reg[2] ),\n .\\wr_ptr_timing_reg[2]_0 (\\wr_ptr_timing_reg[2]_0 ));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_arb_mux\n (\\last_master_r_reg[2] ,\n \\cmd_pipe_plus.mc_cmd_reg[0] ,\n \\cmd_pipe_plus.mc_ras_n_reg[0] ,\n \\cmd_pipe_plus.mc_bank_reg[7] ,\n DIC,\n col_rd_wr,\n col_data_buf_addr,\n cke_r,\n rnk_config_valid_r_lcl_reg,\n \\cmd_pipe_plus.mc_data_offset_1_reg[0] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ,\n \\rtw_timer.rtw_cnt_r_reg[1] ,\n Q,\n \\periodic_rd_generation.periodic_rd_timer_r_reg[2] ,\n read_this_rank,\n \\grant_r_reg[3] ,\n E,\n \\rnk_config_strobe_r_reg[0] ,\n override_demand_ns,\n rnk_config_valid_r_lcl_reg_0,\n mc_we_n_ns,\n \\last_master_r_reg[3] ,\n mc_cas_n_ns,\n mc_ras_n_ns,\n \\cmd_pipe_plus.mc_bank_reg[8] ,\n \\cmd_pipe_plus.mc_bank_reg[1] ,\n \\cmd_pipe_plus.mc_address_reg[44] ,\n mc_cs_n_ns,\n \\grant_r_reg[2] ,\n \\grant_r_reg[3]_0 ,\n \\grant_r_reg[3]_1 ,\n \\last_master_r_reg[2]_0 ,\n \\last_master_r_reg[0] ,\n \\last_master_r_reg[3]_0 ,\n \\cmd_pipe_plus.mc_bank_reg[7]_0 ,\n \\grant_r_reg[1] ,\n \\grant_r_reg[3]_2 ,\n \\grant_r_reg[1]_0 ,\n \\grant_r_reg[1]_1 ,\n \\grant_r_reg[2]_0 ,\n \\last_master_r_reg[3]_1 ,\n act_this_rank,\n \\inhbt_act_faw.inhbt_act_faw_r_reg ,\n \\wtr_timer.wtr_cnt_r_reg[0] ,\n \\wtr_timer.wtr_cnt_r_reg[1] ,\n \\wtr_timer.wtr_cnt_r_reg[1]_0 ,\n demand_priority_r_reg,\n \\cmd_pipe_plus.mc_we_n_reg[1] ,\n granted_row_ns,\n CLK,\n granted_col_ns,\n \\generate_maint_cmds.insert_maint_r_lcl_reg ,\n granted_pre_ns,\n rstdiv0_sync_r1_reg_rep__0,\n mc_cke_ns,\n SR,\n rnk_config_valid_r_lcl_reg_1,\n rd_wr_r_lcl_reg,\n read_this_rank_r,\n rd_this_rank_r,\n rd_wr_r_lcl_reg_0,\n rd_wr_r_lcl_reg_1,\n rd_wr_r_lcl_reg_2,\n rd_wr_r_lcl_reg_3,\n rd_wr_r_lcl_reg_4,\n rstdiv0_sync_r1_reg_rep__21,\n rd_wr_r_lcl_reg_5,\n \\rtw_timer.rtw_cnt_r_reg[1]_0 ,\n rd_wr_r_lcl_reg_6,\n rd_wr_r_lcl_reg_7,\n demand_priority_r_reg_0,\n req_bank_rdy_ns,\n req_bank_rdy_ns_0,\n demand_priority_r_reg_1,\n demand_priority_r_reg_2,\n req_bank_rdy_ns_1,\n demand_priority_r_reg_3,\n req_bank_rdy_ns_2,\n req_periodic_rd_r,\n row_cmd_wr,\n maint_zq_r,\n act_wait_r_lcl_reg,\n granted_row_r_reg,\n maint_srx_r,\n \\req_bank_r_lcl_reg[2] ,\n granted_row_r_reg_0,\n \\req_bank_r_lcl_reg[2]_0 ,\n \\req_bank_r_lcl_reg[2]_1 ,\n \\req_bank_r_lcl_reg[2]_2 ,\n \\req_row_r_lcl_reg[14] ,\n req_row_r,\n act_wait_r_lcl_reg_0,\n act_wait_r_lcl_reg_1,\n act_wait_r_lcl_reg_2,\n ras_timer_zero_r_reg,\n ras_timer_zero_r_reg_0,\n ras_timer_zero_r_reg_1,\n \\last_master_r_reg[3]_2 ,\n ras_timer_zero_r_reg_2,\n ras_timer_zero_r_reg_3,\n inhbt_act_faw_r,\n \\last_master_r_reg[3]_3 ,\n auto_pre_r_lcl_reg,\n auto_pre_r_lcl_reg_0,\n ras_timer_zero_r_reg_4,\n ras_timer_zero_r_reg_5,\n ras_timer_zero_r_reg_6,\n auto_pre_r_lcl_reg_1,\n ras_timer_zero_r_reg_7,\n auto_pre_r_lcl_reg_2,\n rstdiv0_sync_r1_reg_rep__22,\n ofs_rdy_r,\n ofs_rdy_r_3,\n ofs_rdy_r_4,\n ofs_rdy_r_5,\n req_data_buf_addr_r,\n \\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ,\n act_this_rank_r,\n wr_this_rank_r,\n \\req_col_r_reg[9] ,\n \\req_col_r_reg[9]_0 ,\n \\req_col_r_reg[9]_1 ,\n \\req_col_r_reg[9]_2 ,\n auto_pre_r_lcl_reg_3,\n auto_pre_r_lcl_reg_4,\n auto_pre_r_lcl_reg_5,\n auto_pre_r_lcl_reg_6,\n \\req_bank_r_lcl_reg[2]_3 ,\n \\grant_r_reg[0] ,\n \\grant_r_reg[0]_0 ,\n \\grant_r_reg[0]_1 ,\n \\grant_r_reg[0]_2 ,\n \\grant_r_reg[0]_3 ,\n \\grant_r_reg[0]_4 ,\n \\grant_r_reg[0]_5 ,\n \\grant_r_reg[0]_6 ,\n \\grant_r_reg[0]_7 ,\n \\grant_r_reg[0]_8 ,\n \\grant_r_reg[0]_9 ,\n \\grant_r_reg[0]_10 ,\n \\grant_r_reg[0]_11 ,\n \\grant_r_reg[0]_12 ,\n \\req_bank_r_lcl_reg[0] ,\n \\req_bank_r_lcl_reg[1] ,\n req_bank_rdy_r);\n output \\last_master_r_reg[2] ;\n output \\cmd_pipe_plus.mc_cmd_reg[0] ;\n output \\cmd_pipe_plus.mc_ras_n_reg[0] ;\n output \\cmd_pipe_plus.mc_bank_reg[7] ;\n output [0:0]DIC;\n output col_rd_wr;\n output [4:0]col_data_buf_addr;\n output cke_r;\n output rnk_config_valid_r_lcl_reg;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[0] ;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ;\n output \\rtw_timer.rtw_cnt_r_reg[1] ;\n output [3:0]Q;\n output \\periodic_rd_generation.periodic_rd_timer_r_reg[2] ;\n output read_this_rank;\n output \\grant_r_reg[3] ;\n output [0:0]E;\n output \\rnk_config_strobe_r_reg[0] ;\n output override_demand_ns;\n output rnk_config_valid_r_lcl_reg_0;\n output [1:0]mc_we_n_ns;\n output [3:0]\\last_master_r_reg[3] ;\n output [1:0]mc_cas_n_ns;\n output [1:0]mc_ras_n_ns;\n output [8:0]\\cmd_pipe_plus.mc_bank_reg[8] ;\n output \\cmd_pipe_plus.mc_bank_reg[1] ;\n output [36:0]\\cmd_pipe_plus.mc_address_reg[44] ;\n output [0:0]mc_cs_n_ns;\n output \\grant_r_reg[2] ;\n output \\grant_r_reg[3]_0 ;\n output \\grant_r_reg[3]_1 ;\n output \\last_master_r_reg[2]_0 ;\n output \\last_master_r_reg[0] ;\n output [0:0]\\last_master_r_reg[3]_0 ;\n output [3:0]\\cmd_pipe_plus.mc_bank_reg[7]_0 ;\n output \\grant_r_reg[1] ;\n output \\grant_r_reg[3]_2 ;\n output \\grant_r_reg[1]_0 ;\n output \\grant_r_reg[1]_1 ;\n output \\grant_r_reg[2]_0 ;\n output [0:0]\\last_master_r_reg[3]_1 ;\n output act_this_rank;\n output \\inhbt_act_faw.inhbt_act_faw_r_reg ;\n output \\wtr_timer.wtr_cnt_r_reg[0] ;\n output \\wtr_timer.wtr_cnt_r_reg[1] ;\n output \\wtr_timer.wtr_cnt_r_reg[1]_0 ;\n output demand_priority_r_reg;\n output \\cmd_pipe_plus.mc_we_n_reg[1] ;\n input granted_row_ns;\n input CLK;\n input granted_col_ns;\n input \\generate_maint_cmds.insert_maint_r_lcl_reg ;\n input granted_pre_ns;\n input rstdiv0_sync_r1_reg_rep__0;\n input [0:0]mc_cke_ns;\n input [0:0]SR;\n input rnk_config_valid_r_lcl_reg_1;\n input rd_wr_r_lcl_reg;\n input read_this_rank_r;\n input [3:0]rd_this_rank_r;\n input rd_wr_r_lcl_reg_0;\n input rd_wr_r_lcl_reg_1;\n input rd_wr_r_lcl_reg_2;\n input rd_wr_r_lcl_reg_3;\n input rd_wr_r_lcl_reg_4;\n input rstdiv0_sync_r1_reg_rep__21;\n input rd_wr_r_lcl_reg_5;\n input [0:0]\\rtw_timer.rtw_cnt_r_reg[1]_0 ;\n input rd_wr_r_lcl_reg_6;\n input rd_wr_r_lcl_reg_7;\n input demand_priority_r_reg_0;\n input req_bank_rdy_ns;\n input req_bank_rdy_ns_0;\n input demand_priority_r_reg_1;\n input demand_priority_r_reg_2;\n input req_bank_rdy_ns_1;\n input demand_priority_r_reg_3;\n input req_bank_rdy_ns_2;\n input [3:0]req_periodic_rd_r;\n input [0:0]row_cmd_wr;\n input maint_zq_r;\n input act_wait_r_lcl_reg;\n input granted_row_r_reg;\n input maint_srx_r;\n input [2:0]\\req_bank_r_lcl_reg[2] ;\n input granted_row_r_reg_0;\n input [2:0]\\req_bank_r_lcl_reg[2]_0 ;\n input [2:0]\\req_bank_r_lcl_reg[2]_1 ;\n input [2:0]\\req_bank_r_lcl_reg[2]_2 ;\n input [27:0]\\req_row_r_lcl_reg[14] ;\n input [29:0]req_row_r;\n input act_wait_r_lcl_reg_0;\n input act_wait_r_lcl_reg_1;\n input act_wait_r_lcl_reg_2;\n input ras_timer_zero_r_reg;\n input ras_timer_zero_r_reg_0;\n input ras_timer_zero_r_reg_1;\n input \\last_master_r_reg[3]_2 ;\n input ras_timer_zero_r_reg_2;\n input ras_timer_zero_r_reg_3;\n input inhbt_act_faw_r;\n input \\last_master_r_reg[3]_3 ;\n input auto_pre_r_lcl_reg;\n input auto_pre_r_lcl_reg_0;\n input ras_timer_zero_r_reg_4;\n input ras_timer_zero_r_reg_5;\n input ras_timer_zero_r_reg_6;\n input auto_pre_r_lcl_reg_1;\n input ras_timer_zero_r_reg_7;\n input auto_pre_r_lcl_reg_2;\n input rstdiv0_sync_r1_reg_rep__22;\n input ofs_rdy_r;\n input ofs_rdy_r_3;\n input ofs_rdy_r_4;\n input ofs_rdy_r_5;\n input [19:0]req_data_buf_addr_r;\n input [3:0]\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ;\n input [3:0]act_this_rank_r;\n input [3:0]wr_this_rank_r;\n input [6:0]\\req_col_r_reg[9] ;\n input [6:0]\\req_col_r_reg[9]_0 ;\n input [6:0]\\req_col_r_reg[9]_1 ;\n input [6:0]\\req_col_r_reg[9]_2 ;\n input auto_pre_r_lcl_reg_3;\n input auto_pre_r_lcl_reg_4;\n input auto_pre_r_lcl_reg_5;\n input auto_pre_r_lcl_reg_6;\n input \\req_bank_r_lcl_reg[2]_3 ;\n input \\grant_r_reg[0] ;\n input \\grant_r_reg[0]_0 ;\n input \\grant_r_reg[0]_1 ;\n input \\grant_r_reg[0]_2 ;\n input \\grant_r_reg[0]_3 ;\n input \\grant_r_reg[0]_4 ;\n input \\grant_r_reg[0]_5 ;\n input \\grant_r_reg[0]_6 ;\n input \\grant_r_reg[0]_7 ;\n input \\grant_r_reg[0]_8 ;\n input \\grant_r_reg[0]_9 ;\n input \\grant_r_reg[0]_10 ;\n input \\grant_r_reg[0]_11 ;\n input \\grant_r_reg[0]_12 ;\n input \\req_bank_r_lcl_reg[0] ;\n input \\req_bank_r_lcl_reg[1] ;\n input req_bank_rdy_r;\n\n wire CLK;\n wire [0:0]DIC;\n wire [0:0]E;\n wire [3:0]Q;\n wire [0:0]SR;\n wire act_this_rank;\n wire [3:0]act_this_rank_r;\n wire act_wait_r_lcl_reg;\n wire act_wait_r_lcl_reg_0;\n wire act_wait_r_lcl_reg_1;\n wire act_wait_r_lcl_reg_2;\n wire auto_pre_r_lcl_reg;\n wire auto_pre_r_lcl_reg_0;\n wire auto_pre_r_lcl_reg_1;\n wire auto_pre_r_lcl_reg_2;\n wire auto_pre_r_lcl_reg_3;\n wire auto_pre_r_lcl_reg_4;\n wire auto_pre_r_lcl_reg_5;\n wire auto_pre_r_lcl_reg_6;\n wire cke_r;\n wire [36:0]\\cmd_pipe_plus.mc_address_reg[44] ;\n wire \\cmd_pipe_plus.mc_bank_reg[1] ;\n wire \\cmd_pipe_plus.mc_bank_reg[7] ;\n wire [3:0]\\cmd_pipe_plus.mc_bank_reg[7]_0 ;\n wire [8:0]\\cmd_pipe_plus.mc_bank_reg[8] ;\n wire \\cmd_pipe_plus.mc_cmd_reg[0] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[0] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ;\n wire \\cmd_pipe_plus.mc_ras_n_reg[0] ;\n wire \\cmd_pipe_plus.mc_we_n_reg[1] ;\n wire [4:0]col_data_buf_addr;\n wire [4:4]col_data_buf_addr_r;\n wire col_periodic_rd_r;\n wire col_rd_wr;\n wire col_rd_wr_r;\n wire [3:0]\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ;\n wire demand_priority_r_reg;\n wire demand_priority_r_reg_0;\n wire demand_priority_r_reg_1;\n wire demand_priority_r_reg_2;\n wire demand_priority_r_reg_3;\n wire \\generate_maint_cmds.insert_maint_r_lcl_reg ;\n wire \\grant_r_reg[0] ;\n wire \\grant_r_reg[0]_0 ;\n wire \\grant_r_reg[0]_1 ;\n wire \\grant_r_reg[0]_10 ;\n wire \\grant_r_reg[0]_11 ;\n wire \\grant_r_reg[0]_12 ;\n wire \\grant_r_reg[0]_2 ;\n wire \\grant_r_reg[0]_3 ;\n wire \\grant_r_reg[0]_4 ;\n wire \\grant_r_reg[0]_5 ;\n wire \\grant_r_reg[0]_6 ;\n wire \\grant_r_reg[0]_7 ;\n wire \\grant_r_reg[0]_8 ;\n wire \\grant_r_reg[0]_9 ;\n wire \\grant_r_reg[1] ;\n wire \\grant_r_reg[1]_0 ;\n wire \\grant_r_reg[1]_1 ;\n wire \\grant_r_reg[2] ;\n wire \\grant_r_reg[2]_0 ;\n wire \\grant_r_reg[3] ;\n wire \\grant_r_reg[3]_0 ;\n wire \\grant_r_reg[3]_1 ;\n wire \\grant_r_reg[3]_2 ;\n wire granted_col_ns;\n wire granted_pre_ns;\n wire granted_row_ns;\n wire granted_row_r_reg;\n wire granted_row_r_reg_0;\n wire \\inhbt_act_faw.inhbt_act_faw_r_reg ;\n wire inhbt_act_faw_r;\n wire \\last_master_r_reg[0] ;\n wire \\last_master_r_reg[2] ;\n wire \\last_master_r_reg[2]_0 ;\n wire [3:0]\\last_master_r_reg[3] ;\n wire [0:0]\\last_master_r_reg[3]_0 ;\n wire [0:0]\\last_master_r_reg[3]_1 ;\n wire \\last_master_r_reg[3]_2 ;\n wire \\last_master_r_reg[3]_3 ;\n wire maint_srx_r;\n wire maint_zq_r;\n wire [1:0]mc_cas_n_ns;\n wire [0:0]mc_cke_ns;\n wire [0:0]mc_cs_n_ns;\n wire [1:0]mc_ras_n_ns;\n wire [1:0]mc_we_n_ns;\n wire ofs_rdy_r;\n wire ofs_rdy_r_3;\n wire ofs_rdy_r_4;\n wire ofs_rdy_r_5;\n wire override_demand_ns;\n wire \\periodic_rd_generation.periodic_rd_timer_r_reg[2] ;\n wire ras_timer_zero_r_reg;\n wire ras_timer_zero_r_reg_0;\n wire ras_timer_zero_r_reg_1;\n wire ras_timer_zero_r_reg_2;\n wire ras_timer_zero_r_reg_3;\n wire ras_timer_zero_r_reg_4;\n wire ras_timer_zero_r_reg_5;\n wire ras_timer_zero_r_reg_6;\n wire ras_timer_zero_r_reg_7;\n wire [3:0]rd_this_rank_r;\n wire rd_wr_r_lcl_reg;\n wire rd_wr_r_lcl_reg_0;\n wire rd_wr_r_lcl_reg_1;\n wire rd_wr_r_lcl_reg_2;\n wire rd_wr_r_lcl_reg_3;\n wire rd_wr_r_lcl_reg_4;\n wire rd_wr_r_lcl_reg_5;\n wire rd_wr_r_lcl_reg_6;\n wire rd_wr_r_lcl_reg_7;\n wire read_this_rank;\n wire read_this_rank_r;\n wire \\req_bank_r_lcl_reg[0] ;\n wire \\req_bank_r_lcl_reg[1] ;\n wire [2:0]\\req_bank_r_lcl_reg[2] ;\n wire [2:0]\\req_bank_r_lcl_reg[2]_0 ;\n wire [2:0]\\req_bank_r_lcl_reg[2]_1 ;\n wire [2:0]\\req_bank_r_lcl_reg[2]_2 ;\n wire \\req_bank_r_lcl_reg[2]_3 ;\n wire req_bank_rdy_ns;\n wire req_bank_rdy_ns_0;\n wire req_bank_rdy_ns_1;\n wire req_bank_rdy_ns_2;\n wire req_bank_rdy_r;\n wire [6:0]\\req_col_r_reg[9] ;\n wire [6:0]\\req_col_r_reg[9]_0 ;\n wire [6:0]\\req_col_r_reg[9]_1 ;\n wire [6:0]\\req_col_r_reg[9]_2 ;\n wire [19:0]req_data_buf_addr_r;\n wire [3:0]req_periodic_rd_r;\n wire [29:0]req_row_r;\n wire [27:0]\\req_row_r_lcl_reg[14] ;\n wire \\rnk_config_strobe_r_reg[0] ;\n wire rnk_config_valid_r_lcl_reg;\n wire rnk_config_valid_r_lcl_reg_0;\n wire rnk_config_valid_r_lcl_reg_1;\n wire [0:0]row_cmd_wr;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire rstdiv0_sync_r1_reg_rep__22;\n wire \\rtw_timer.rtw_cnt_r_reg[1] ;\n wire [0:0]\\rtw_timer.rtw_cnt_r_reg[1]_0 ;\n wire [3:0]wr_this_rank_r;\n wire \\wtr_timer.wtr_cnt_r_reg[0] ;\n wire \\wtr_timer.wtr_cnt_r_reg[1] ;\n wire \\wtr_timer.wtr_cnt_r_reg[1]_0 ;\n\n ddr3_if_mig_7series_v4_0_arb_row_col arb_row_col0\n (.CLK(CLK),\n .D({\\last_master_r_reg[2]_0 ,\\last_master_r_reg[0] }),\n .DIC(DIC),\n .E(E),\n .Q(Q),\n .SR(SR),\n .act_this_rank(act_this_rank),\n .act_this_rank_r(act_this_rank_r),\n .act_wait_r_lcl_reg(act_wait_r_lcl_reg),\n .act_wait_r_lcl_reg_0(act_wait_r_lcl_reg_0),\n .act_wait_r_lcl_reg_1(act_wait_r_lcl_reg_1),\n .act_wait_r_lcl_reg_2(act_wait_r_lcl_reg_2),\n .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg),\n .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_0),\n .auto_pre_r_lcl_reg_1(auto_pre_r_lcl_reg_1),\n .auto_pre_r_lcl_reg_2(auto_pre_r_lcl_reg_2),\n .auto_pre_r_lcl_reg_3(auto_pre_r_lcl_reg_3),\n .auto_pre_r_lcl_reg_4(auto_pre_r_lcl_reg_4),\n .auto_pre_r_lcl_reg_5(auto_pre_r_lcl_reg_5),\n .auto_pre_r_lcl_reg_6(auto_pre_r_lcl_reg_6),\n .\\cmd_pipe_plus.mc_address_reg[44] (\\cmd_pipe_plus.mc_address_reg[44] ),\n .\\cmd_pipe_plus.mc_bank_reg[1] (\\cmd_pipe_plus.mc_bank_reg[1] ),\n .\\cmd_pipe_plus.mc_bank_reg[7] (\\cmd_pipe_plus.mc_bank_reg[7] ),\n .\\cmd_pipe_plus.mc_bank_reg[7]_0 (\\cmd_pipe_plus.mc_bank_reg[7]_0 ),\n .\\cmd_pipe_plus.mc_bank_reg[8] (\\cmd_pipe_plus.mc_bank_reg[8] ),\n .\\cmd_pipe_plus.mc_cmd_reg[0] (\\cmd_pipe_plus.mc_cmd_reg[0] ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[0] (\\cmd_pipe_plus.mc_data_offset_1_reg[0] ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 (\\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ),\n .\\cmd_pipe_plus.mc_ras_n_reg[0] (\\cmd_pipe_plus.mc_ras_n_reg[0] ),\n .\\cmd_pipe_plus.mc_we_n_reg[1] (\\cmd_pipe_plus.mc_we_n_reg[1] ),\n .col_data_buf_addr(col_data_buf_addr),\n .col_data_buf_addr_r(col_data_buf_addr_r),\n .col_periodic_rd_r(col_periodic_rd_r),\n .col_rd_wr(col_rd_wr),\n .col_rd_wr_r(col_rd_wr_r),\n .\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] (\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ),\n .demand_priority_r_reg(demand_priority_r_reg),\n .demand_priority_r_reg_0(demand_priority_r_reg_0),\n .demand_priority_r_reg_1(demand_priority_r_reg_1),\n .demand_priority_r_reg_2(demand_priority_r_reg_2),\n .demand_priority_r_reg_3(demand_priority_r_reg_3),\n .\\generate_maint_cmds.insert_maint_r_lcl_reg (\\generate_maint_cmds.insert_maint_r_lcl_reg ),\n .\\grant_r_reg[0] (\\grant_r_reg[0] ),\n .\\grant_r_reg[0]_0 (\\grant_r_reg[0]_0 ),\n .\\grant_r_reg[0]_1 (\\grant_r_reg[0]_1 ),\n .\\grant_r_reg[0]_10 (\\grant_r_reg[0]_10 ),\n .\\grant_r_reg[0]_11 (\\grant_r_reg[0]_11 ),\n .\\grant_r_reg[0]_12 (\\grant_r_reg[0]_12 ),\n .\\grant_r_reg[0]_2 (\\grant_r_reg[0]_2 ),\n .\\grant_r_reg[0]_3 (\\grant_r_reg[0]_3 ),\n .\\grant_r_reg[0]_4 (\\grant_r_reg[0]_4 ),\n .\\grant_r_reg[0]_5 (\\grant_r_reg[0]_5 ),\n .\\grant_r_reg[0]_6 (\\grant_r_reg[0]_6 ),\n .\\grant_r_reg[0]_7 (\\grant_r_reg[0]_7 ),\n .\\grant_r_reg[0]_8 (\\grant_r_reg[0]_8 ),\n .\\grant_r_reg[0]_9 (\\grant_r_reg[0]_9 ),\n .\\grant_r_reg[1] (\\grant_r_reg[1] ),\n .\\grant_r_reg[1]_0 (\\grant_r_reg[1]_0 ),\n .\\grant_r_reg[1]_1 (\\grant_r_reg[1]_1 ),\n .\\grant_r_reg[2] (\\grant_r_reg[2] ),\n .\\grant_r_reg[2]_0 (\\grant_r_reg[2]_0 ),\n .\\grant_r_reg[3] (\\grant_r_reg[3] ),\n .\\grant_r_reg[3]_0 (\\grant_r_reg[3]_0 ),\n .\\grant_r_reg[3]_1 (\\grant_r_reg[3]_1 ),\n .\\grant_r_reg[3]_2 (\\grant_r_reg[3]_2 ),\n .granted_col_ns(granted_col_ns),\n .granted_pre_ns(granted_pre_ns),\n .granted_row_ns(granted_row_ns),\n .granted_row_r_reg_0(granted_row_r_reg),\n .granted_row_r_reg_1(granted_row_r_reg_0),\n .\\inhbt_act_faw.inhbt_act_faw_r_reg (\\inhbt_act_faw.inhbt_act_faw_r_reg ),\n .inhbt_act_faw_r(inhbt_act_faw_r),\n .\\last_master_r_reg[2] (\\last_master_r_reg[2] ),\n .\\last_master_r_reg[3] (\\last_master_r_reg[3] ),\n .\\last_master_r_reg[3]_0 (\\last_master_r_reg[3]_0 ),\n .\\last_master_r_reg[3]_1 (\\last_master_r_reg[3]_1 ),\n .\\last_master_r_reg[3]_2 (\\last_master_r_reg[3]_2 ),\n .\\last_master_r_reg[3]_3 (\\last_master_r_reg[3]_3 ),\n .maint_srx_r(maint_srx_r),\n .maint_zq_r(maint_zq_r),\n .mc_cas_n_ns(mc_cas_n_ns),\n .mc_cs_n_ns(mc_cs_n_ns),\n .mc_ras_n_ns(mc_ras_n_ns),\n .mc_we_n_ns(mc_we_n_ns),\n .ofs_rdy_r(ofs_rdy_r),\n .ofs_rdy_r_3(ofs_rdy_r_3),\n .ofs_rdy_r_4(ofs_rdy_r_4),\n .ofs_rdy_r_5(ofs_rdy_r_5),\n .override_demand_ns(override_demand_ns),\n .\\periodic_rd_generation.periodic_rd_timer_r_reg[2] (\\periodic_rd_generation.periodic_rd_timer_r_reg[2] ),\n .ras_timer_zero_r_reg(ras_timer_zero_r_reg),\n .ras_timer_zero_r_reg_0(ras_timer_zero_r_reg_0),\n .ras_timer_zero_r_reg_1(ras_timer_zero_r_reg_1),\n .ras_timer_zero_r_reg_2(ras_timer_zero_r_reg_2),\n .ras_timer_zero_r_reg_3(ras_timer_zero_r_reg_3),\n .ras_timer_zero_r_reg_4(ras_timer_zero_r_reg_4),\n .ras_timer_zero_r_reg_5(ras_timer_zero_r_reg_5),\n .ras_timer_zero_r_reg_6(ras_timer_zero_r_reg_6),\n .ras_timer_zero_r_reg_7(ras_timer_zero_r_reg_7),\n .rd_this_rank_r(rd_this_rank_r),\n .rd_wr_r_lcl_reg(rd_wr_r_lcl_reg),\n .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg_0),\n .rd_wr_r_lcl_reg_1(rd_wr_r_lcl_reg_1),\n .rd_wr_r_lcl_reg_2(rd_wr_r_lcl_reg_2),\n .rd_wr_r_lcl_reg_3(rd_wr_r_lcl_reg_3),\n .rd_wr_r_lcl_reg_4(rd_wr_r_lcl_reg_4),\n .rd_wr_r_lcl_reg_5(rd_wr_r_lcl_reg_5),\n .rd_wr_r_lcl_reg_6(rd_wr_r_lcl_reg_6),\n .rd_wr_r_lcl_reg_7(rd_wr_r_lcl_reg_7),\n .read_this_rank(read_this_rank),\n .read_this_rank_r(read_this_rank_r),\n .\\req_bank_r_lcl_reg[0] (\\req_bank_r_lcl_reg[0] ),\n .\\req_bank_r_lcl_reg[1] (\\req_bank_r_lcl_reg[1] ),\n .\\req_bank_r_lcl_reg[2] (\\req_bank_r_lcl_reg[2] ),\n .\\req_bank_r_lcl_reg[2]_0 (\\req_bank_r_lcl_reg[2]_0 ),\n .\\req_bank_r_lcl_reg[2]_1 (\\req_bank_r_lcl_reg[2]_1 ),\n .\\req_bank_r_lcl_reg[2]_2 (\\req_bank_r_lcl_reg[2]_2 ),\n .\\req_bank_r_lcl_reg[2]_3 (\\req_bank_r_lcl_reg[2]_3 ),\n .req_bank_rdy_ns(req_bank_rdy_ns),\n .req_bank_rdy_ns_0(req_bank_rdy_ns_0),\n .req_bank_rdy_ns_1(req_bank_rdy_ns_1),\n .req_bank_rdy_ns_2(req_bank_rdy_ns_2),\n .req_bank_rdy_r(req_bank_rdy_r),\n .\\req_col_r_reg[9] (\\req_col_r_reg[9] ),\n .\\req_col_r_reg[9]_0 (\\req_col_r_reg[9]_0 ),\n .\\req_col_r_reg[9]_1 (\\req_col_r_reg[9]_1 ),\n .\\req_col_r_reg[9]_2 (\\req_col_r_reg[9]_2 ),\n .req_data_buf_addr_r(req_data_buf_addr_r),\n .req_periodic_rd_r(req_periodic_rd_r),\n .req_row_r(req_row_r),\n .\\req_row_r_lcl_reg[14] (\\req_row_r_lcl_reg[14] ),\n .\\rnk_config_strobe_r_reg[0]_0 (\\rnk_config_strobe_r_reg[0] ),\n .rnk_config_valid_r_lcl_reg_0(rnk_config_valid_r_lcl_reg),\n .rnk_config_valid_r_lcl_reg_1(rnk_config_valid_r_lcl_reg_0),\n .rnk_config_valid_r_lcl_reg_2(rnk_config_valid_r_lcl_reg_1),\n .row_cmd_wr(row_cmd_wr),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22),\n .\\rtw_timer.rtw_cnt_r_reg[1] (\\rtw_timer.rtw_cnt_r_reg[1] ),\n .\\rtw_timer.rtw_cnt_r_reg[1]_0 (\\rtw_timer.rtw_cnt_r_reg[1]_0 ),\n .wr_this_rank_r(wr_this_rank_r),\n .\\wtr_timer.wtr_cnt_r_reg[0] (\\wtr_timer.wtr_cnt_r_reg[0] ),\n .\\wtr_timer.wtr_cnt_r_reg[1] (\\wtr_timer.wtr_cnt_r_reg[1] ),\n .\\wtr_timer.wtr_cnt_r_reg[1]_0 (\\wtr_timer.wtr_cnt_r_reg[1]_0 ));\n ddr3_if_mig_7series_v4_0_arb_select arb_select0\n (.CLK(CLK),\n .DIC(DIC),\n .cke_r(cke_r),\n .col_data_buf_addr(col_data_buf_addr[4]),\n .col_data_buf_addr_r(col_data_buf_addr_r),\n .col_periodic_rd_r(col_periodic_rd_r),\n .col_rd_wr(col_rd_wr),\n .col_rd_wr_r(col_rd_wr_r),\n .mc_cke_ns(mc_cke_ns),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_arb_row_col\n (\\last_master_r_reg[2] ,\n \\cmd_pipe_plus.mc_cmd_reg[0] ,\n \\cmd_pipe_plus.mc_ras_n_reg[0] ,\n \\cmd_pipe_plus.mc_bank_reg[7] ,\n rnk_config_valid_r_lcl_reg_0,\n \\cmd_pipe_plus.mc_data_offset_1_reg[0] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ,\n \\rtw_timer.rtw_cnt_r_reg[1] ,\n Q,\n \\periodic_rd_generation.periodic_rd_timer_r_reg[2] ,\n read_this_rank,\n \\grant_r_reg[3] ,\n E,\n col_rd_wr,\n \\rnk_config_strobe_r_reg[0]_0 ,\n override_demand_ns,\n rnk_config_valid_r_lcl_reg_1,\n DIC,\n mc_we_n_ns,\n \\last_master_r_reg[3] ,\n mc_cas_n_ns,\n mc_ras_n_ns,\n \\cmd_pipe_plus.mc_bank_reg[8] ,\n \\cmd_pipe_plus.mc_bank_reg[1] ,\n \\cmd_pipe_plus.mc_address_reg[44] ,\n mc_cs_n_ns,\n \\grant_r_reg[2] ,\n \\grant_r_reg[3]_0 ,\n \\grant_r_reg[3]_1 ,\n D,\n \\last_master_r_reg[3]_0 ,\n \\cmd_pipe_plus.mc_bank_reg[7]_0 ,\n \\grant_r_reg[1] ,\n \\grant_r_reg[3]_2 ,\n \\grant_r_reg[1]_0 ,\n \\grant_r_reg[1]_1 ,\n \\grant_r_reg[2]_0 ,\n col_data_buf_addr,\n \\last_master_r_reg[3]_1 ,\n act_this_rank,\n \\inhbt_act_faw.inhbt_act_faw_r_reg ,\n \\wtr_timer.wtr_cnt_r_reg[0] ,\n \\wtr_timer.wtr_cnt_r_reg[1] ,\n \\wtr_timer.wtr_cnt_r_reg[1]_0 ,\n demand_priority_r_reg,\n \\cmd_pipe_plus.mc_we_n_reg[1] ,\n granted_row_ns,\n CLK,\n granted_col_ns,\n \\generate_maint_cmds.insert_maint_r_lcl_reg ,\n granted_pre_ns,\n SR,\n rnk_config_valid_r_lcl_reg_2,\n rd_wr_r_lcl_reg,\n read_this_rank_r,\n rd_this_rank_r,\n rd_wr_r_lcl_reg_0,\n rd_wr_r_lcl_reg_1,\n rd_wr_r_lcl_reg_2,\n rd_wr_r_lcl_reg_3,\n rd_wr_r_lcl_reg_4,\n rstdiv0_sync_r1_reg_rep__21,\n rd_wr_r_lcl_reg_5,\n \\rtw_timer.rtw_cnt_r_reg[1]_0 ,\n rd_wr_r_lcl_reg_6,\n rd_wr_r_lcl_reg_7,\n demand_priority_r_reg_0,\n req_bank_rdy_ns,\n req_bank_rdy_ns_0,\n demand_priority_r_reg_1,\n demand_priority_r_reg_2,\n req_bank_rdy_ns_1,\n demand_priority_r_reg_3,\n req_bank_rdy_ns_2,\n req_periodic_rd_r,\n col_periodic_rd_r,\n col_rd_wr_r,\n row_cmd_wr,\n maint_zq_r,\n act_wait_r_lcl_reg,\n granted_row_r_reg_0,\n maint_srx_r,\n \\req_bank_r_lcl_reg[2] ,\n granted_row_r_reg_1,\n \\req_bank_r_lcl_reg[2]_0 ,\n \\req_bank_r_lcl_reg[2]_1 ,\n \\req_bank_r_lcl_reg[2]_2 ,\n \\req_row_r_lcl_reg[14] ,\n req_row_r,\n act_wait_r_lcl_reg_0,\n act_wait_r_lcl_reg_1,\n act_wait_r_lcl_reg_2,\n ras_timer_zero_r_reg,\n ras_timer_zero_r_reg_0,\n ras_timer_zero_r_reg_1,\n \\last_master_r_reg[3]_2 ,\n ras_timer_zero_r_reg_2,\n ras_timer_zero_r_reg_3,\n inhbt_act_faw_r,\n \\last_master_r_reg[3]_3 ,\n auto_pre_r_lcl_reg,\n auto_pre_r_lcl_reg_0,\n ras_timer_zero_r_reg_4,\n ras_timer_zero_r_reg_5,\n ras_timer_zero_r_reg_6,\n auto_pre_r_lcl_reg_1,\n ras_timer_zero_r_reg_7,\n auto_pre_r_lcl_reg_2,\n rstdiv0_sync_r1_reg_rep__22,\n ofs_rdy_r,\n ofs_rdy_r_3,\n ofs_rdy_r_4,\n ofs_rdy_r_5,\n req_data_buf_addr_r,\n col_data_buf_addr_r,\n \\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ,\n act_this_rank_r,\n wr_this_rank_r,\n \\req_col_r_reg[9] ,\n \\req_col_r_reg[9]_0 ,\n \\req_col_r_reg[9]_1 ,\n \\req_col_r_reg[9]_2 ,\n auto_pre_r_lcl_reg_3,\n auto_pre_r_lcl_reg_4,\n auto_pre_r_lcl_reg_5,\n auto_pre_r_lcl_reg_6,\n \\req_bank_r_lcl_reg[2]_3 ,\n \\grant_r_reg[0] ,\n \\grant_r_reg[0]_0 ,\n \\grant_r_reg[0]_1 ,\n \\grant_r_reg[0]_2 ,\n \\grant_r_reg[0]_3 ,\n \\grant_r_reg[0]_4 ,\n \\grant_r_reg[0]_5 ,\n \\grant_r_reg[0]_6 ,\n \\grant_r_reg[0]_7 ,\n \\grant_r_reg[0]_8 ,\n \\grant_r_reg[0]_9 ,\n \\grant_r_reg[0]_10 ,\n \\grant_r_reg[0]_11 ,\n \\grant_r_reg[0]_12 ,\n \\req_bank_r_lcl_reg[0] ,\n \\req_bank_r_lcl_reg[1] ,\n req_bank_rdy_r);\n output \\last_master_r_reg[2] ;\n output \\cmd_pipe_plus.mc_cmd_reg[0] ;\n output \\cmd_pipe_plus.mc_ras_n_reg[0] ;\n output \\cmd_pipe_plus.mc_bank_reg[7] ;\n output rnk_config_valid_r_lcl_reg_0;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[0] ;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ;\n output \\rtw_timer.rtw_cnt_r_reg[1] ;\n output [3:0]Q;\n output \\periodic_rd_generation.periodic_rd_timer_r_reg[2] ;\n output read_this_rank;\n output \\grant_r_reg[3] ;\n output [0:0]E;\n output col_rd_wr;\n output \\rnk_config_strobe_r_reg[0]_0 ;\n output override_demand_ns;\n output rnk_config_valid_r_lcl_reg_1;\n output [0:0]DIC;\n output [1:0]mc_we_n_ns;\n output [3:0]\\last_master_r_reg[3] ;\n output [1:0]mc_cas_n_ns;\n output [1:0]mc_ras_n_ns;\n output [8:0]\\cmd_pipe_plus.mc_bank_reg[8] ;\n output \\cmd_pipe_plus.mc_bank_reg[1] ;\n output [36:0]\\cmd_pipe_plus.mc_address_reg[44] ;\n output [0:0]mc_cs_n_ns;\n output \\grant_r_reg[2] ;\n output \\grant_r_reg[3]_0 ;\n output \\grant_r_reg[3]_1 ;\n output [1:0]D;\n output [0:0]\\last_master_r_reg[3]_0 ;\n output [3:0]\\cmd_pipe_plus.mc_bank_reg[7]_0 ;\n output \\grant_r_reg[1] ;\n output \\grant_r_reg[3]_2 ;\n output \\grant_r_reg[1]_0 ;\n output \\grant_r_reg[1]_1 ;\n output \\grant_r_reg[2]_0 ;\n output [4:0]col_data_buf_addr;\n output [0:0]\\last_master_r_reg[3]_1 ;\n output act_this_rank;\n output \\inhbt_act_faw.inhbt_act_faw_r_reg ;\n output \\wtr_timer.wtr_cnt_r_reg[0] ;\n output \\wtr_timer.wtr_cnt_r_reg[1] ;\n output \\wtr_timer.wtr_cnt_r_reg[1]_0 ;\n output demand_priority_r_reg;\n output \\cmd_pipe_plus.mc_we_n_reg[1] ;\n input granted_row_ns;\n input CLK;\n input granted_col_ns;\n input \\generate_maint_cmds.insert_maint_r_lcl_reg ;\n input granted_pre_ns;\n input [0:0]SR;\n input rnk_config_valid_r_lcl_reg_2;\n input rd_wr_r_lcl_reg;\n input read_this_rank_r;\n input [3:0]rd_this_rank_r;\n input rd_wr_r_lcl_reg_0;\n input rd_wr_r_lcl_reg_1;\n input rd_wr_r_lcl_reg_2;\n input rd_wr_r_lcl_reg_3;\n input rd_wr_r_lcl_reg_4;\n input rstdiv0_sync_r1_reg_rep__21;\n input rd_wr_r_lcl_reg_5;\n input [0:0]\\rtw_timer.rtw_cnt_r_reg[1]_0 ;\n input rd_wr_r_lcl_reg_6;\n input rd_wr_r_lcl_reg_7;\n input demand_priority_r_reg_0;\n input req_bank_rdy_ns;\n input req_bank_rdy_ns_0;\n input demand_priority_r_reg_1;\n input demand_priority_r_reg_2;\n input req_bank_rdy_ns_1;\n input demand_priority_r_reg_3;\n input req_bank_rdy_ns_2;\n input [3:0]req_periodic_rd_r;\n input col_periodic_rd_r;\n input col_rd_wr_r;\n input [0:0]row_cmd_wr;\n input maint_zq_r;\n input act_wait_r_lcl_reg;\n input granted_row_r_reg_0;\n input maint_srx_r;\n input [2:0]\\req_bank_r_lcl_reg[2] ;\n input granted_row_r_reg_1;\n input [2:0]\\req_bank_r_lcl_reg[2]_0 ;\n input [2:0]\\req_bank_r_lcl_reg[2]_1 ;\n input [2:0]\\req_bank_r_lcl_reg[2]_2 ;\n input [27:0]\\req_row_r_lcl_reg[14] ;\n input [29:0]req_row_r;\n input act_wait_r_lcl_reg_0;\n input act_wait_r_lcl_reg_1;\n input act_wait_r_lcl_reg_2;\n input ras_timer_zero_r_reg;\n input ras_timer_zero_r_reg_0;\n input ras_timer_zero_r_reg_1;\n input \\last_master_r_reg[3]_2 ;\n input ras_timer_zero_r_reg_2;\n input ras_timer_zero_r_reg_3;\n input inhbt_act_faw_r;\n input \\last_master_r_reg[3]_3 ;\n input auto_pre_r_lcl_reg;\n input auto_pre_r_lcl_reg_0;\n input ras_timer_zero_r_reg_4;\n input ras_timer_zero_r_reg_5;\n input ras_timer_zero_r_reg_6;\n input auto_pre_r_lcl_reg_1;\n input ras_timer_zero_r_reg_7;\n input auto_pre_r_lcl_reg_2;\n input rstdiv0_sync_r1_reg_rep__22;\n input ofs_rdy_r;\n input ofs_rdy_r_3;\n input ofs_rdy_r_4;\n input ofs_rdy_r_5;\n input [19:0]req_data_buf_addr_r;\n input [0:0]col_data_buf_addr_r;\n input [3:0]\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ;\n input [3:0]act_this_rank_r;\n input [3:0]wr_this_rank_r;\n input [6:0]\\req_col_r_reg[9] ;\n input [6:0]\\req_col_r_reg[9]_0 ;\n input [6:0]\\req_col_r_reg[9]_1 ;\n input [6:0]\\req_col_r_reg[9]_2 ;\n input auto_pre_r_lcl_reg_3;\n input auto_pre_r_lcl_reg_4;\n input auto_pre_r_lcl_reg_5;\n input auto_pre_r_lcl_reg_6;\n input \\req_bank_r_lcl_reg[2]_3 ;\n input \\grant_r_reg[0] ;\n input \\grant_r_reg[0]_0 ;\n input \\grant_r_reg[0]_1 ;\n input \\grant_r_reg[0]_2 ;\n input \\grant_r_reg[0]_3 ;\n input \\grant_r_reg[0]_4 ;\n input \\grant_r_reg[0]_5 ;\n input \\grant_r_reg[0]_6 ;\n input \\grant_r_reg[0]_7 ;\n input \\grant_r_reg[0]_8 ;\n input \\grant_r_reg[0]_9 ;\n input \\grant_r_reg[0]_10 ;\n input \\grant_r_reg[0]_11 ;\n input \\grant_r_reg[0]_12 ;\n input \\req_bank_r_lcl_reg[0] ;\n input \\req_bank_r_lcl_reg[1] ;\n input req_bank_rdy_r;\n\n wire CLK;\n wire [1:0]D;\n wire [0:0]DIC;\n wire [0:0]E;\n wire [3:0]Q;\n wire [0:0]SR;\n wire act_this_rank;\n wire [3:0]act_this_rank_r;\n wire act_wait_r_lcl_reg;\n wire act_wait_r_lcl_reg_0;\n wire act_wait_r_lcl_reg_1;\n wire act_wait_r_lcl_reg_2;\n wire auto_pre_r_lcl_reg;\n wire auto_pre_r_lcl_reg_0;\n wire auto_pre_r_lcl_reg_1;\n wire auto_pre_r_lcl_reg_2;\n wire auto_pre_r_lcl_reg_3;\n wire auto_pre_r_lcl_reg_4;\n wire auto_pre_r_lcl_reg_5;\n wire auto_pre_r_lcl_reg_6;\n wire [36:0]\\cmd_pipe_plus.mc_address_reg[44] ;\n wire \\cmd_pipe_plus.mc_bank_reg[1] ;\n wire \\cmd_pipe_plus.mc_bank_reg[7] ;\n wire [3:0]\\cmd_pipe_plus.mc_bank_reg[7]_0 ;\n wire [8:0]\\cmd_pipe_plus.mc_bank_reg[8] ;\n wire \\cmd_pipe_plus.mc_cmd_reg[0] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[0] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ;\n wire \\cmd_pipe_plus.mc_ras_n_reg[0] ;\n wire \\cmd_pipe_plus.mc_we_n_reg[1] ;\n wire [4:0]col_data_buf_addr;\n wire [0:0]col_data_buf_addr_r;\n wire col_periodic_rd_r;\n wire col_rd_wr;\n wire col_rd_wr_r;\n wire [3:0]\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ;\n wire demand_priority_r_reg;\n wire demand_priority_r_reg_0;\n wire demand_priority_r_reg_1;\n wire demand_priority_r_reg_2;\n wire demand_priority_r_reg_3;\n wire \\genblk3[1].rnk_config_strobe_r_reg ;\n wire \\genblk3[2].rnk_config_strobe_r_reg ;\n wire \\generate_maint_cmds.insert_maint_r_lcl_reg ;\n wire \\grant_r_reg[0] ;\n wire \\grant_r_reg[0]_0 ;\n wire \\grant_r_reg[0]_1 ;\n wire \\grant_r_reg[0]_10 ;\n wire \\grant_r_reg[0]_11 ;\n wire \\grant_r_reg[0]_12 ;\n wire \\grant_r_reg[0]_2 ;\n wire \\grant_r_reg[0]_3 ;\n wire \\grant_r_reg[0]_4 ;\n wire \\grant_r_reg[0]_5 ;\n wire \\grant_r_reg[0]_6 ;\n wire \\grant_r_reg[0]_7 ;\n wire \\grant_r_reg[0]_8 ;\n wire \\grant_r_reg[0]_9 ;\n wire \\grant_r_reg[1] ;\n wire \\grant_r_reg[1]_0 ;\n wire \\grant_r_reg[1]_1 ;\n wire \\grant_r_reg[2] ;\n wire \\grant_r_reg[2]_0 ;\n wire \\grant_r_reg[3] ;\n wire \\grant_r_reg[3]_0 ;\n wire \\grant_r_reg[3]_1 ;\n wire \\grant_r_reg[3]_2 ;\n wire granted_col_ns;\n wire granted_pre_ns;\n wire granted_row_ns;\n wire granted_row_r_reg_0;\n wire granted_row_r_reg_1;\n wire \\inhbt_act_faw.inhbt_act_faw_r_reg ;\n wire inhbt_act_faw_r;\n wire \\last_master_r_reg[2] ;\n wire [3:0]\\last_master_r_reg[3] ;\n wire [0:0]\\last_master_r_reg[3]_0 ;\n wire [0:0]\\last_master_r_reg[3]_1 ;\n wire \\last_master_r_reg[3]_2 ;\n wire \\last_master_r_reg[3]_3 ;\n wire maint_srx_r;\n wire maint_zq_r;\n wire [1:0]mc_cas_n_ns;\n wire [0:0]mc_cs_n_ns;\n wire [1:0]mc_ras_n_ns;\n wire [1:0]mc_we_n_ns;\n wire ofs_rdy_r;\n wire ofs_rdy_r_3;\n wire ofs_rdy_r_4;\n wire ofs_rdy_r_5;\n wire override_demand_ns;\n wire \\periodic_rd_generation.periodic_rd_timer_r_reg[2] ;\n wire ras_timer_zero_r_reg;\n wire ras_timer_zero_r_reg_0;\n wire ras_timer_zero_r_reg_1;\n wire ras_timer_zero_r_reg_2;\n wire ras_timer_zero_r_reg_3;\n wire ras_timer_zero_r_reg_4;\n wire ras_timer_zero_r_reg_5;\n wire ras_timer_zero_r_reg_6;\n wire ras_timer_zero_r_reg_7;\n wire [3:0]rd_this_rank_r;\n wire rd_wr_r_lcl_reg;\n wire rd_wr_r_lcl_reg_0;\n wire rd_wr_r_lcl_reg_1;\n wire rd_wr_r_lcl_reg_2;\n wire rd_wr_r_lcl_reg_3;\n wire rd_wr_r_lcl_reg_4;\n wire rd_wr_r_lcl_reg_5;\n wire rd_wr_r_lcl_reg_6;\n wire rd_wr_r_lcl_reg_7;\n wire read_this_rank;\n wire read_this_rank_r;\n wire \\req_bank_r_lcl_reg[0] ;\n wire \\req_bank_r_lcl_reg[1] ;\n wire [2:0]\\req_bank_r_lcl_reg[2] ;\n wire [2:0]\\req_bank_r_lcl_reg[2]_0 ;\n wire [2:0]\\req_bank_r_lcl_reg[2]_1 ;\n wire [2:0]\\req_bank_r_lcl_reg[2]_2 ;\n wire \\req_bank_r_lcl_reg[2]_3 ;\n wire req_bank_rdy_ns;\n wire req_bank_rdy_ns_0;\n wire req_bank_rdy_ns_1;\n wire req_bank_rdy_ns_2;\n wire req_bank_rdy_r;\n wire [6:0]\\req_col_r_reg[9] ;\n wire [6:0]\\req_col_r_reg[9]_0 ;\n wire [6:0]\\req_col_r_reg[9]_1 ;\n wire [6:0]\\req_col_r_reg[9]_2 ;\n wire [19:0]req_data_buf_addr_r;\n wire [3:0]req_periodic_rd_r;\n wire [29:0]req_row_r;\n wire [27:0]\\req_row_r_lcl_reg[14] ;\n wire rnk_config_strobe;\n wire rnk_config_strobe_ns;\n wire \\rnk_config_strobe_r[0]_i_3_n_0 ;\n wire \\rnk_config_strobe_r_reg[0]_0 ;\n wire rnk_config_valid_r_lcl_reg_0;\n wire rnk_config_valid_r_lcl_reg_1;\n wire rnk_config_valid_r_lcl_reg_2;\n wire [0:0]row_cmd_wr;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire rstdiv0_sync_r1_reg_rep__22;\n wire \\rtw_timer.rtw_cnt_r_reg[1] ;\n wire [0:0]\\rtw_timer.rtw_cnt_r_reg[1]_0 ;\n wire [3:0]wr_this_rank_r;\n wire \\wtr_timer.wtr_cnt_r_reg[0] ;\n wire \\wtr_timer.wtr_cnt_r_reg[1] ;\n wire \\wtr_timer.wtr_cnt_r_reg[1]_0 ;\n\n LUT1 #(\n .INIT(2'h1)) \n \\cmd_pipe_plus.mc_cas_n[1]_i_1 \n (.I0(\\cmd_pipe_plus.mc_cmd_reg[0] ),\n .O(mc_cas_n_ns[1]));\n LUT2 #(\n .INIT(4'h1)) \n \\cmd_pipe_plus.mc_cs_n[0]_i_1 \n (.I0(\\cmd_pipe_plus.mc_ras_n_reg[0] ),\n .I1(\\last_master_r_reg[2] ),\n .O(mc_cs_n_ns));\n LUT1 #(\n .INIT(2'h1)) \n \\cmd_pipe_plus.mc_ras_n[2]_i_1 \n (.I0(\\cmd_pipe_plus.mc_bank_reg[7] ),\n .O(mc_ras_n_ns[1]));\n ddr3_if_mig_7series_v4_0_round_robin_arb__parameterized4 col_arb0\n (.CLK(CLK),\n .DIC(DIC),\n .E(E),\n .Q(Q),\n .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg_3),\n .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_4),\n .auto_pre_r_lcl_reg_1(auto_pre_r_lcl_reg_5),\n .auto_pre_r_lcl_reg_2(auto_pre_r_lcl_reg_6),\n .\\cmd_pipe_plus.mc_address_reg[25] (\\cmd_pipe_plus.mc_address_reg[44] [22:15]),\n .\\cmd_pipe_plus.mc_bank_reg[5] (\\cmd_pipe_plus.mc_bank_reg[8] [5:3]),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[0] (\\cmd_pipe_plus.mc_data_offset_1_reg[0] ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 (\\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ),\n .\\cmd_pipe_plus.mc_we_n_reg[1] (\\cmd_pipe_plus.mc_we_n_reg[1] ),\n .col_data_buf_addr(col_data_buf_addr),\n .col_data_buf_addr_r(col_data_buf_addr_r),\n .col_periodic_rd_r(col_periodic_rd_r),\n .col_rd_wr(col_rd_wr),\n .col_rd_wr_r(col_rd_wr_r),\n .\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] (\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ),\n .demand_priority_r_reg(demand_priority_r_reg),\n .\\genblk3[1].rnk_config_strobe_r_reg (\\genblk3[1].rnk_config_strobe_r_reg ),\n .\\genblk3[2].rnk_config_strobe_r_reg (\\genblk3[2].rnk_config_strobe_r_reg ),\n .\\grant_r_reg[1]_0 (\\grant_r_reg[1]_0 ),\n .\\grant_r_reg[1]_1 (\\grant_r_reg[1]_1 ),\n .\\grant_r_reg[2]_0 (\\grant_r_reg[2]_0 ),\n .\\grant_r_reg[3]_0 (\\grant_r_reg[3] ),\n .\\grant_r_reg[3]_1 (\\grant_r_reg[3]_2 ),\n .granted_col_r_reg(\\cmd_pipe_plus.mc_cmd_reg[0] ),\n .ofs_rdy_r(ofs_rdy_r),\n .ofs_rdy_r_3(ofs_rdy_r_3),\n .ofs_rdy_r_4(ofs_rdy_r_4),\n .ofs_rdy_r_5(ofs_rdy_r_5),\n .\\periodic_rd_generation.periodic_rd_timer_r_reg[2] (\\periodic_rd_generation.periodic_rd_timer_r_reg[2] ),\n .rd_this_rank_r(rd_this_rank_r),\n .rd_wr_r_lcl_reg(rd_wr_r_lcl_reg),\n .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg_0),\n .rd_wr_r_lcl_reg_1(rd_wr_r_lcl_reg_1),\n .rd_wr_r_lcl_reg_2(rd_wr_r_lcl_reg_2),\n .rd_wr_r_lcl_reg_3(rd_wr_r_lcl_reg_3),\n .rd_wr_r_lcl_reg_4(rd_wr_r_lcl_reg_4),\n .rd_wr_r_lcl_reg_5(rd_wr_r_lcl_reg_5),\n .rd_wr_r_lcl_reg_6(rd_wr_r_lcl_reg_6),\n .rd_wr_r_lcl_reg_7(rd_wr_r_lcl_reg_7),\n .read_this_rank(read_this_rank),\n .read_this_rank_r(read_this_rank_r),\n .\\req_bank_r_lcl_reg[2] (\\req_bank_r_lcl_reg[2]_2 ),\n .\\req_bank_r_lcl_reg[2]_0 (\\req_bank_r_lcl_reg[2] ),\n .\\req_bank_r_lcl_reg[2]_1 (\\req_bank_r_lcl_reg[2]_0 ),\n .\\req_bank_r_lcl_reg[2]_2 (\\req_bank_r_lcl_reg[2]_1 ),\n .req_bank_rdy_r(req_bank_rdy_r),\n .\\req_col_r_reg[9] (\\req_col_r_reg[9] ),\n .\\req_col_r_reg[9]_0 (\\req_col_r_reg[9]_0 ),\n .\\req_col_r_reg[9]_1 (\\req_col_r_reg[9]_1 ),\n .\\req_col_r_reg[9]_2 (\\req_col_r_reg[9]_2 ),\n .req_data_buf_addr_r(req_data_buf_addr_r),\n .req_periodic_rd_r(req_periodic_rd_r),\n .rnk_config_strobe(rnk_config_strobe),\n .rnk_config_valid_r_lcl_reg(rnk_config_valid_r_lcl_reg_0),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22),\n .\\rtw_timer.rtw_cnt_r_reg[1] (\\rtw_timer.rtw_cnt_r_reg[1] ),\n .\\rtw_timer.rtw_cnt_r_reg[1]_0 (\\rtw_timer.rtw_cnt_r_reg[1]_0 ),\n .wr_this_rank_r(wr_this_rank_r),\n .\\wtr_timer.wtr_cnt_r_reg[0] (\\wtr_timer.wtr_cnt_r_reg[0] ),\n .\\wtr_timer.wtr_cnt_r_reg[1] (\\wtr_timer.wtr_cnt_r_reg[1] ),\n .\\wtr_timer.wtr_cnt_r_reg[1]_0 (\\wtr_timer.wtr_cnt_r_reg[1]_0 ));\n FDRE \\genblk3[1].rnk_config_strobe_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(rnk_config_strobe),\n .Q(\\genblk3[1].rnk_config_strobe_r_reg ),\n .R(1'b0));\n FDRE \\genblk3[2].rnk_config_strobe_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk3[1].rnk_config_strobe_r_reg ),\n .Q(\\genblk3[2].rnk_config_strobe_r_reg ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n granted_col_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(granted_col_ns),\n .Q(\\cmd_pipe_plus.mc_cmd_reg[0] ),\n .R(1'b0));\n FDRE granted_row_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(granted_row_ns),\n .Q(\\last_master_r_reg[2] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFF0FFF7FFF7FFF7)) \n i___34_i_1\n (.I0(demand_priority_r_reg_2),\n .I1(req_bank_rdy_ns_1),\n .I2(rnk_config_valid_r_lcl_reg_0),\n .I3(override_demand_ns),\n .I4(demand_priority_r_reg_3),\n .I5(req_bank_rdy_ns_2),\n .O(\\rnk_config_strobe_r_reg[0]_0 ));\n LUT6 #(\n .INIT(64'h000000F800000088)) \n i___34_i_2\n (.I0(demand_priority_r_reg_1),\n .I1(req_bank_rdy_ns_0),\n .I2(req_bank_rdy_ns),\n .I3(rnk_config_valid_r_lcl_reg_0),\n .I4(override_demand_ns),\n .I5(demand_priority_r_reg_0),\n .O(rnk_config_valid_r_lcl_reg_1));\n FDRE insert_maint_r1_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\generate_maint_cmds.insert_maint_r_lcl_reg ),\n .Q(\\cmd_pipe_plus.mc_ras_n_reg[0] ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1049\" *) \n LUT3 #(\n .INIT(8'hFE)) \n override_demand_r_i_1\n (.I0(\\genblk3[1].rnk_config_strobe_r_reg ),\n .I1(\\genblk3[2].rnk_config_strobe_r_reg ),\n .I2(rnk_config_strobe),\n .O(override_demand_ns));\n FDRE #(\n .INIT(1'b0)) \n \\pre_4_1_1T_arb.granted_pre_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(granted_pre_ns),\n .Q(\\cmd_pipe_plus.mc_bank_reg[7] ),\n .R(1'b0));\n ddr3_if_mig_7series_v4_0_round_robin_arb__parameterized1 \\pre_4_1_1T_arb.pre_arb0 \n (.CLK(CLK),\n .D(D),\n .Q(\\cmd_pipe_plus.mc_bank_reg[7]_0 ),\n .act_wait_r_lcl_reg(act_wait_r_lcl_reg_2),\n .act_wait_r_lcl_reg_0(act_wait_r_lcl_reg_1),\n .act_wait_r_lcl_reg_1(act_wait_r_lcl_reg),\n .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg),\n .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_0),\n .auto_pre_r_lcl_reg_1(auto_pre_r_lcl_reg_1),\n .auto_pre_r_lcl_reg_2(auto_pre_r_lcl_reg_2),\n .\\cmd_pipe_plus.mc_address_reg[44] (\\cmd_pipe_plus.mc_address_reg[44] [36:23]),\n .\\cmd_pipe_plus.mc_bank_reg[8] (\\cmd_pipe_plus.mc_bank_reg[8] [8:6]),\n .\\grant_r_reg[0]_0 (\\grant_r_reg[0] ),\n .\\grant_r_reg[0]_1 (\\grant_r_reg[0]_0 ),\n .\\grant_r_reg[0]_10 (\\grant_r_reg[0]_9 ),\n .\\grant_r_reg[0]_11 (\\grant_r_reg[0]_10 ),\n .\\grant_r_reg[0]_12 (\\grant_r_reg[0]_11 ),\n .\\grant_r_reg[0]_13 (\\grant_r_reg[0]_12 ),\n .\\grant_r_reg[0]_2 (\\grant_r_reg[0]_1 ),\n .\\grant_r_reg[0]_3 (\\grant_r_reg[0]_2 ),\n .\\grant_r_reg[0]_4 (\\grant_r_reg[0]_3 ),\n .\\grant_r_reg[0]_5 (\\grant_r_reg[0]_4 ),\n .\\grant_r_reg[0]_6 (\\grant_r_reg[0]_5 ),\n .\\grant_r_reg[0]_7 (\\grant_r_reg[0]_6 ),\n .\\grant_r_reg[0]_8 (\\grant_r_reg[0]_7 ),\n .\\grant_r_reg[0]_9 (\\grant_r_reg[0]_8 ),\n .\\last_master_r_reg[3]_0 (\\last_master_r_reg[3]_0 ),\n .\\last_master_r_reg[3]_1 (\\last_master_r_reg[3]_3 ),\n .mc_we_n_ns(mc_we_n_ns[1]),\n .\\pre_4_1_1T_arb.granted_pre_r_reg (\\cmd_pipe_plus.mc_bank_reg[7] ),\n .ras_timer_zero_r_reg(ras_timer_zero_r_reg_4),\n .ras_timer_zero_r_reg_0(ras_timer_zero_r_reg_5),\n .ras_timer_zero_r_reg_1(ras_timer_zero_r_reg_6),\n .ras_timer_zero_r_reg_2(ras_timer_zero_r_reg_7),\n .\\req_bank_r_lcl_reg[0] (\\req_bank_r_lcl_reg[0] ),\n .\\req_bank_r_lcl_reg[1] (\\req_bank_r_lcl_reg[1] ),\n .\\req_bank_r_lcl_reg[2] (\\req_bank_r_lcl_reg[2]_3 ),\n .\\req_bank_r_lcl_reg[2]_0 (\\req_bank_r_lcl_reg[2]_2 ),\n .\\req_bank_r_lcl_reg[2]_1 (\\req_bank_r_lcl_reg[2]_1 ),\n .req_row_r({req_row_r[29:12],req_row_r[10:1]}),\n .row_cmd_wr(row_cmd_wr),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22));\n LUT6 #(\n .INIT(64'h33202020FFFFFFFF)) \n \\rnk_config_strobe_r[0]_i_1 \n (.I0(demand_priority_r_reg_0),\n .I1(\\rnk_config_strobe_r[0]_i_3_n_0 ),\n .I2(req_bank_rdy_ns),\n .I3(req_bank_rdy_ns_0),\n .I4(demand_priority_r_reg_1),\n .I5(\\rnk_config_strobe_r_reg[0]_0 ),\n .O(rnk_config_strobe_ns));\n (* SOFT_HLUTNM = \"soft_lutpair1049\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n \\rnk_config_strobe_r[0]_i_3 \n (.I0(rnk_config_strobe),\n .I1(\\genblk3[2].rnk_config_strobe_r_reg ),\n .I2(\\genblk3[1].rnk_config_strobe_r_reg ),\n .I3(rnk_config_valid_r_lcl_reg_0),\n .O(\\rnk_config_strobe_r[0]_i_3_n_0 ));\n FDRE \\rnk_config_strobe_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(rnk_config_strobe_ns),\n .Q(rnk_config_strobe),\n .R(1'b0));\n FDRE rnk_config_valid_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rnk_config_valid_r_lcl_reg_2),\n .Q(rnk_config_valid_r_lcl_reg_0),\n .R(SR));\n ddr3_if_mig_7series_v4_0_round_robin_arb__parameterized2 row_arb0\n (.CLK(CLK),\n .Q(\\last_master_r_reg[3] ),\n .act_this_rank(act_this_rank),\n .act_this_rank_r(act_this_rank_r),\n .act_wait_r_lcl_reg(act_wait_r_lcl_reg),\n .act_wait_r_lcl_reg_0(act_wait_r_lcl_reg_0),\n .act_wait_r_lcl_reg_1(act_wait_r_lcl_reg_1),\n .act_wait_r_lcl_reg_2(act_wait_r_lcl_reg_2),\n .\\cmd_pipe_plus.mc_address_reg[14] (\\cmd_pipe_plus.mc_address_reg[44] [14:0]),\n .\\cmd_pipe_plus.mc_bank_reg[1] (\\cmd_pipe_plus.mc_bank_reg[1] ),\n .\\cmd_pipe_plus.mc_bank_reg[2] (\\cmd_pipe_plus.mc_bank_reg[8] [2:0]),\n .\\generate_maint_cmds.insert_maint_r_lcl_reg (\\generate_maint_cmds.insert_maint_r_lcl_reg ),\n .\\grant_r_reg[1]_0 (\\grant_r_reg[1] ),\n .\\grant_r_reg[2]_0 (\\grant_r_reg[2] ),\n .\\grant_r_reg[3]_0 (\\grant_r_reg[3]_0 ),\n .\\grant_r_reg[3]_1 (\\grant_r_reg[3]_1 ),\n .granted_row_r_reg(granted_row_r_reg_0),\n .granted_row_r_reg_0(\\last_master_r_reg[2] ),\n .granted_row_r_reg_1(granted_row_r_reg_1),\n .\\inhbt_act_faw.inhbt_act_faw_r_reg (\\inhbt_act_faw.inhbt_act_faw_r_reg ),\n .inhbt_act_faw_r(inhbt_act_faw_r),\n .insert_maint_r1_lcl_reg(\\cmd_pipe_plus.mc_ras_n_reg[0] ),\n .\\last_master_r_reg[3]_0 (\\last_master_r_reg[3]_1 ),\n .\\last_master_r_reg[3]_1 (\\last_master_r_reg[3]_2 ),\n .maint_srx_r(maint_srx_r),\n .maint_zq_r(maint_zq_r),\n .mc_cas_n_ns(mc_cas_n_ns[0]),\n .mc_ras_n_ns(mc_ras_n_ns[0]),\n .mc_we_n_ns(mc_we_n_ns[0]),\n .ras_timer_zero_r_reg(ras_timer_zero_r_reg),\n .ras_timer_zero_r_reg_0(ras_timer_zero_r_reg_0),\n .ras_timer_zero_r_reg_1(ras_timer_zero_r_reg_1),\n .ras_timer_zero_r_reg_2(ras_timer_zero_r_reg_2),\n .ras_timer_zero_r_reg_3(ras_timer_zero_r_reg_3),\n .\\req_bank_r_lcl_reg[2] (\\req_bank_r_lcl_reg[2] ),\n .\\req_bank_r_lcl_reg[2]_0 (\\req_bank_r_lcl_reg[2]_0 ),\n .\\req_bank_r_lcl_reg[2]_1 (\\req_bank_r_lcl_reg[2]_1 ),\n .\\req_bank_r_lcl_reg[2]_2 (\\req_bank_r_lcl_reg[2]_2 ),\n .req_row_r(req_row_r),\n .\\req_row_r_lcl_reg[14] (\\req_row_r_lcl_reg[14] ),\n .row_cmd_wr(row_cmd_wr),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_arb_select\n (col_periodic_rd_r,\n col_rd_wr_r,\n col_data_buf_addr_r,\n cke_r,\n DIC,\n CLK,\n col_rd_wr,\n col_data_buf_addr,\n rstdiv0_sync_r1_reg_rep__0,\n mc_cke_ns);\n output col_periodic_rd_r;\n output col_rd_wr_r;\n output [0:0]col_data_buf_addr_r;\n output cke_r;\n input [0:0]DIC;\n input CLK;\n input col_rd_wr;\n input [0:0]col_data_buf_addr;\n input rstdiv0_sync_r1_reg_rep__0;\n input [0:0]mc_cke_ns;\n\n wire CLK;\n wire [0:0]DIC;\n wire cke_r;\n wire [0:0]col_data_buf_addr;\n wire [0:0]col_data_buf_addr_r;\n wire col_periodic_rd_r;\n wire col_rd_wr;\n wire col_rd_wr_r;\n wire [0:0]mc_cke_ns;\n wire rstdiv0_sync_r1_reg_rep__0;\n\n FDSE cke_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mc_cke_ns),\n .Q(cke_r),\n .S(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\col_mux.col_data_buf_addr_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(col_data_buf_addr),\n .Q(col_data_buf_addr_r),\n .R(1'b0));\n FDRE \\col_mux.col_periodic_rd_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(DIC),\n .Q(col_periodic_rd_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\col_mux.col_rd_wr_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(col_rd_wr),\n .Q(col_rd_wr_r),\n .R(1'b0));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_axi_mc\n (s_axi_arready,\n app_en_ns1,\n mc_app_cmd,\n E,\n s_axi_awready,\n s_axi_wready,\n mc_app_wdf_mask_reg,\n D,\n mc_app_wdf_data_reg,\n \\mc_app_wdf_data_reg_reg[255] ,\n out,\n s_axi_rid,\n s_axi_bid,\n s_axi_bvalid,\n w_cmd_rdy,\n \\app_addr_r1_reg[27] ,\n s_axi_rvalid,\n s_axi_rlast,\n app_wdf_mask,\n app_wdf_data,\n mc_app_wdf_wren_reg,\n s_axi_arvalid,\n app_rdy,\n reset_reg,\n app_en_r1,\n CLK,\n app_wdf_rdy,\n app_rd_data_valid,\n Q,\n mc_init_complete,\n s_axi_awlen,\n s_axi_bready,\n s_axi_awvalid,\n s_axi_awaddr,\n s_axi_awburst,\n s_axi_wvalid,\n s_axi_awid,\n s_axi_arlen,\n s_axi_araddr,\n s_axi_arburst,\n s_axi_rready,\n s_axi_wstrb,\n s_axi_wdata,\n aresetn,\n s_axi_arid);\n output s_axi_arready;\n output app_en_ns1;\n output [0:0]mc_app_cmd;\n output [0:0]E;\n output s_axi_awready;\n output s_axi_wready;\n output [31:0]mc_app_wdf_mask_reg;\n output [31:0]D;\n output [255:0]mc_app_wdf_data_reg;\n output [255:0]\\mc_app_wdf_data_reg_reg[255] ;\n output [256:0]out;\n output [0:0]s_axi_rid;\n output [0:0]s_axi_bid;\n output s_axi_bvalid;\n output w_cmd_rdy;\n output [24:0]\\app_addr_r1_reg[27] ;\n output s_axi_rvalid;\n output s_axi_rlast;\n output [31:0]app_wdf_mask;\n output [255:0]app_wdf_data;\n output mc_app_wdf_wren_reg;\n input s_axi_arvalid;\n input app_rdy;\n input reset_reg;\n input app_en_r1;\n input CLK;\n input app_wdf_rdy;\n input app_rd_data_valid;\n input [255:0]Q;\n input mc_init_complete;\n input [7:0]s_axi_awlen;\n input s_axi_bready;\n input s_axi_awvalid;\n input [29:0]s_axi_awaddr;\n input [0:0]s_axi_awburst;\n input s_axi_wvalid;\n input [0:0]s_axi_awid;\n input [7:0]s_axi_arlen;\n input [29:0]s_axi_araddr;\n input [0:0]s_axi_arburst;\n input s_axi_rready;\n input [31:0]s_axi_wstrb;\n input [255:0]s_axi_wdata;\n input aresetn;\n input [0:0]s_axi_arid;\n\n wire CLK;\n wire [31:0]D;\n wire [0:0]E;\n wire [255:0]Q;\n wire [24:0]\\app_addr_r1_reg[27] ;\n wire app_en_ns1;\n wire app_en_r1;\n wire app_rd_data_valid;\n wire app_rdy;\n wire [255:0]app_wdf_data;\n wire [31:0]app_wdf_mask;\n wire app_wdf_rdy;\n wire areset_d1;\n wire aresetn;\n wire awvalid_int;\n wire axi_mc_ar_channel_0_n_29;\n wire axi_mc_aw_channel_0_n_10;\n wire axi_mc_aw_channel_0_n_11;\n wire axi_mc_aw_channel_0_n_12;\n wire axi_mc_aw_channel_0_n_13;\n wire axi_mc_aw_channel_0_n_14;\n wire axi_mc_aw_channel_0_n_15;\n wire axi_mc_aw_channel_0_n_16;\n wire axi_mc_aw_channel_0_n_17;\n wire axi_mc_aw_channel_0_n_18;\n wire axi_mc_aw_channel_0_n_19;\n wire axi_mc_aw_channel_0_n_20;\n wire axi_mc_aw_channel_0_n_21;\n wire axi_mc_aw_channel_0_n_22;\n wire axi_mc_aw_channel_0_n_23;\n wire axi_mc_aw_channel_0_n_24;\n wire axi_mc_aw_channel_0_n_25;\n wire axi_mc_aw_channel_0_n_26;\n wire axi_mc_aw_channel_0_n_27;\n wire axi_mc_aw_channel_0_n_28;\n wire axi_mc_aw_channel_0_n_4;\n wire axi_mc_aw_channel_0_n_5;\n wire axi_mc_aw_channel_0_n_7;\n wire axi_mc_aw_channel_0_n_8;\n wire axi_mc_aw_channel_0_n_9;\n wire axi_mc_cmd_arbiter_0_n_3;\n wire axi_mc_cmd_arbiter_0_n_4;\n wire axi_mc_cmd_arbiter_0_n_5;\n wire axi_mc_cmd_arbiter_0_n_6;\n wire axvalid;\n wire b_awid;\n wire b_push;\n wire [0:0]mc_app_cmd;\n wire [255:0]mc_app_wdf_data_reg;\n wire [255:0]\\mc_app_wdf_data_reg_reg[255] ;\n wire [31:0]mc_app_wdf_mask_reg;\n wire mc_app_wdf_wren_reg;\n wire mc_init_complete;\n wire mc_init_complete_r;\n wire next;\n wire [256:0]out;\n wire p_0_in;\n wire r_arid;\n wire r_push;\n wire r_rlast;\n wire rd_cmd_en;\n wire rd_starve_cnt0;\n wire reset_reg;\n wire [29:0]s_axi_araddr;\n wire [0:0]s_axi_arburst;\n wire [0:0]s_axi_arid;\n wire [7:0]s_axi_arlen;\n wire s_axi_arready;\n wire s_axi_arvalid;\n wire [29:0]s_axi_awaddr;\n wire [0:0]s_axi_awburst;\n wire [0:0]s_axi_awid;\n wire [7:0]s_axi_awlen;\n wire s_axi_awready;\n wire s_axi_awvalid;\n wire [0:0]s_axi_bid;\n wire s_axi_bready;\n wire s_axi_bvalid;\n wire [0:0]s_axi_rid;\n wire s_axi_rlast;\n wire s_axi_rready;\n wire s_axi_rvalid;\n wire [255:0]s_axi_wdata;\n wire s_axi_wready;\n wire [31:0]s_axi_wstrb;\n wire s_axi_wvalid;\n wire w_cmd_rdy;\n wire wr_cmd_en;\n wire wvalid_int;\n\n LUT2 #(\n .INIT(4'h7)) \n areset_d1_i_1\n (.I0(mc_init_complete_r),\n .I1(aresetn),\n .O(p_0_in));\n (* equivalent_register_removal = \"no\" *) \n FDRE areset_d1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in),\n .Q(areset_d1),\n .R(1'b0));\n ddr3_if_mig_7series_v4_0_axi_mc_ar_channel axi_mc_ar_channel_0\n (.CLK(CLK),\n .\\RD_PRI_REG_STARVE.rnw_i_reg (mc_app_cmd),\n .\\app_addr_r1_reg[27] ({\\app_addr_r1_reg[27] [24:4],\\app_addr_r1_reg[27] [2:0]}),\n .\\app_addr_r1_reg[6] (axi_mc_ar_channel_0_n_29),\n .areset_d1(areset_d1),\n .\\axaddr_incr_reg[10] (axi_mc_aw_channel_0_n_8),\n .\\axaddr_incr_reg[11] (axi_mc_aw_channel_0_n_9),\n .\\axaddr_incr_reg[12] (axi_mc_aw_channel_0_n_10),\n .\\axaddr_incr_reg[13] (axi_mc_aw_channel_0_n_11),\n .\\axaddr_incr_reg[14] (axi_mc_aw_channel_0_n_12),\n .\\axaddr_incr_reg[15] (axi_mc_aw_channel_0_n_13),\n .\\axaddr_incr_reg[16] (axi_mc_aw_channel_0_n_14),\n .\\axaddr_incr_reg[17] (axi_mc_aw_channel_0_n_15),\n .\\axaddr_incr_reg[18] (axi_mc_aw_channel_0_n_16),\n .\\axaddr_incr_reg[19] (axi_mc_aw_channel_0_n_17),\n .\\axaddr_incr_reg[20] (axi_mc_aw_channel_0_n_18),\n .\\axaddr_incr_reg[21] (axi_mc_aw_channel_0_n_19),\n .\\axaddr_incr_reg[22] (axi_mc_aw_channel_0_n_20),\n .\\axaddr_incr_reg[23] (axi_mc_aw_channel_0_n_21),\n .\\axaddr_incr_reg[24] (axi_mc_aw_channel_0_n_22),\n .\\axaddr_incr_reg[25] (axi_mc_aw_channel_0_n_23),\n .\\axaddr_incr_reg[26] (axi_mc_aw_channel_0_n_24),\n .\\axaddr_incr_reg[27] (axi_mc_aw_channel_0_n_25),\n .\\axaddr_incr_reg[28] (axi_mc_aw_channel_0_n_26),\n .\\axaddr_incr_reg[29] (axi_mc_aw_channel_0_n_27),\n .\\axaddr_incr_reg[5] (axi_mc_aw_channel_0_n_28),\n .\\axaddr_incr_reg[6] (axi_mc_aw_channel_0_n_4),\n .\\axaddr_incr_reg[7] (axi_mc_aw_channel_0_n_5),\n .\\axaddr_incr_reg[9] (axi_mc_aw_channel_0_n_7),\n .axready_reg(axi_mc_cmd_arbiter_0_n_5),\n .axready_reg_0(axi_mc_cmd_arbiter_0_n_6),\n .axvalid(axvalid),\n .in({r_arid,r_rlast}),\n .next(next),\n .r_push(r_push),\n .s_axi_araddr(s_axi_araddr),\n .s_axi_arburst(s_axi_arburst),\n .s_axi_arid(s_axi_arid),\n .s_axi_arlen(s_axi_arlen),\n .s_axi_arready(s_axi_arready),\n .s_axi_arvalid(s_axi_arvalid));\n ddr3_if_mig_7series_v4_0_axi_mc_aw_channel axi_mc_aw_channel_0\n (.CLK(CLK),\n .\\RD_PRI_REG_STARVE.rnw_i_reg (w_cmd_rdy),\n .\\RD_PRI_REG_STARVE.rnw_i_reg_0 (mc_app_cmd),\n .\\app_addr_r1_reg[10] (axi_mc_aw_channel_0_n_10),\n .\\app_addr_r1_reg[11] (axi_mc_aw_channel_0_n_11),\n .\\app_addr_r1_reg[12] (axi_mc_aw_channel_0_n_12),\n .\\app_addr_r1_reg[13] (axi_mc_aw_channel_0_n_13),\n .\\app_addr_r1_reg[14] (axi_mc_aw_channel_0_n_14),\n .\\app_addr_r1_reg[15] (axi_mc_aw_channel_0_n_15),\n .\\app_addr_r1_reg[16] (axi_mc_aw_channel_0_n_16),\n .\\app_addr_r1_reg[17] (axi_mc_aw_channel_0_n_17),\n .\\app_addr_r1_reg[18] (axi_mc_aw_channel_0_n_18),\n .\\app_addr_r1_reg[19] (axi_mc_aw_channel_0_n_19),\n .\\app_addr_r1_reg[20] (axi_mc_aw_channel_0_n_20),\n .\\app_addr_r1_reg[21] (axi_mc_aw_channel_0_n_21),\n .\\app_addr_r1_reg[22] (axi_mc_aw_channel_0_n_22),\n .\\app_addr_r1_reg[23] (axi_mc_aw_channel_0_n_23),\n .\\app_addr_r1_reg[24] (axi_mc_aw_channel_0_n_24),\n .\\app_addr_r1_reg[25] (axi_mc_aw_channel_0_n_25),\n .\\app_addr_r1_reg[26] (axi_mc_aw_channel_0_n_26),\n .\\app_addr_r1_reg[27] (axi_mc_aw_channel_0_n_27),\n .\\app_addr_r1_reg[3] (axi_mc_aw_channel_0_n_28),\n .\\app_addr_r1_reg[4] (axi_mc_aw_channel_0_n_4),\n .\\app_addr_r1_reg[5] (axi_mc_aw_channel_0_n_5),\n .\\app_addr_r1_reg[6] (\\app_addr_r1_reg[27] [3]),\n .\\app_addr_r1_reg[7] (axi_mc_aw_channel_0_n_7),\n .\\app_addr_r1_reg[8] (axi_mc_aw_channel_0_n_8),\n .\\app_addr_r1_reg[9] (axi_mc_aw_channel_0_n_9),\n .areset_d1(areset_d1),\n .awvalid_int(awvalid_int),\n .axready_reg(axi_mc_cmd_arbiter_0_n_3),\n .axready_reg_0(axi_mc_cmd_arbiter_0_n_4),\n .b_awid(b_awid),\n .b_push(b_push),\n .\\int_addr_reg[3] (axi_mc_ar_channel_0_n_29),\n .s_axi_awaddr(s_axi_awaddr),\n .s_axi_awburst(s_axi_awburst),\n .s_axi_awid(s_axi_awid),\n .s_axi_awlen(s_axi_awlen),\n .s_axi_awready(s_axi_awready),\n .s_axi_awvalid(s_axi_awvalid));\n ddr3_if_mig_7series_v4_0_axi_mc_b_channel axi_mc_b_channel_0\n (.CLK(CLK),\n .E(E),\n .\\RD_PRI_REG_STARVE.rnw_i_reg (mc_app_cmd),\n .app_en_ns1(app_en_ns1),\n .app_en_r1(app_en_r1),\n .app_rdy(app_rdy),\n .app_wdf_rdy(app_wdf_rdy),\n .areset_d1(areset_d1),\n .awvalid_int(awvalid_int),\n .b_awid(b_awid),\n .b_push(b_push),\n .rd_cmd_en(rd_cmd_en),\n .reset_reg(reset_reg),\n .s_axi_bid(s_axi_bid),\n .s_axi_bready(s_axi_bready),\n .s_axi_bvalid(s_axi_bvalid),\n .wr_cmd_en(wr_cmd_en),\n .wvalid_int(wvalid_int));\n ddr3_if_mig_7series_v4_0_axi_mc_cmd_arbiter axi_mc_cmd_arbiter_0\n (.CLK(CLK),\n .E(rd_starve_cnt0),\n .\\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 (mc_app_cmd),\n .app_rdy(app_rdy),\n .areset_d1(areset_d1),\n .\\axaddr_incr_reg[29] (axi_mc_cmd_arbiter_0_n_3),\n .\\axaddr_incr_reg[29]_0 (axi_mc_cmd_arbiter_0_n_5),\n .\\axlen_cnt_reg[1] (axi_mc_cmd_arbiter_0_n_4),\n .\\axlen_cnt_reg[1]_0 (axi_mc_cmd_arbiter_0_n_6),\n .axready_reg(s_axi_arready),\n .mc_app_wdf_wren_reg_reg(w_cmd_rdy),\n .next(next),\n .rd_cmd_en(rd_cmd_en),\n .s_axi_arburst(s_axi_arburst),\n .s_axi_arvalid(s_axi_arvalid),\n .s_axi_awburst(s_axi_awburst),\n .s_axi_awready(s_axi_awready),\n .s_axi_awvalid(s_axi_awvalid),\n .wr_cmd_en(wr_cmd_en));\n ddr3_if_mig_7series_v4_0_axi_mc_r_channel axi_mc_r_channel_0\n (.CLK(CLK),\n .E(rd_starve_cnt0),\n .Q(Q),\n .app_rd_data_valid(app_rd_data_valid),\n .app_rdy(app_rdy),\n .areset_d1(areset_d1),\n .axvalid(axvalid),\n .in({r_arid,r_rlast}),\n .out(out),\n .r_push(r_push),\n .rd_cmd_en(rd_cmd_en),\n .s_axi_arready(s_axi_arready),\n .s_axi_arvalid(s_axi_arvalid),\n .s_axi_rid(s_axi_rid),\n .s_axi_rlast(s_axi_rlast),\n .s_axi_rready(s_axi_rready),\n .s_axi_rvalid(s_axi_rvalid));\n ddr3_if_mig_7series_v4_0_axi_mc_w_channel axi_mc_w_channel_0\n (.CLK(CLK),\n .D(D),\n .\\RD_PRI_REG_STARVE.rnw_i_reg (w_cmd_rdy),\n .app_wdf_data(app_wdf_data),\n .app_wdf_mask(app_wdf_mask),\n .app_wdf_rdy(app_wdf_rdy),\n .areset_d1(areset_d1),\n .mc_app_wdf_data_reg(mc_app_wdf_data_reg),\n .\\mc_app_wdf_data_reg_reg[255]_0 (\\mc_app_wdf_data_reg_reg[255] ),\n .mc_app_wdf_mask_reg(mc_app_wdf_mask_reg),\n .mc_app_wdf_wren_reg(mc_app_wdf_wren_reg),\n .s_axi_wdata(s_axi_wdata),\n .s_axi_wready(s_axi_wready),\n .s_axi_wstrb(s_axi_wstrb),\n .s_axi_wvalid(s_axi_wvalid),\n .wvalid_int(wvalid_int));\n FDRE mc_init_complete_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mc_init_complete),\n .Q(mc_init_complete_r),\n .R(1'b0));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_axi_mc_ar_channel\n (s_axi_arready,\n r_push,\n in,\n axvalid,\n \\app_addr_r1_reg[27] ,\n \\app_addr_r1_reg[6] ,\n areset_d1,\n CLK,\n next,\n \\axaddr_incr_reg[6] ,\n \\axaddr_incr_reg[7] ,\n \\axaddr_incr_reg[9] ,\n \\axaddr_incr_reg[10] ,\n \\axaddr_incr_reg[11] ,\n \\axaddr_incr_reg[12] ,\n \\axaddr_incr_reg[13] ,\n \\axaddr_incr_reg[14] ,\n \\axaddr_incr_reg[15] ,\n \\axaddr_incr_reg[16] ,\n \\axaddr_incr_reg[17] ,\n \\axaddr_incr_reg[18] ,\n \\axaddr_incr_reg[19] ,\n \\axaddr_incr_reg[20] ,\n \\axaddr_incr_reg[21] ,\n \\axaddr_incr_reg[22] ,\n \\axaddr_incr_reg[23] ,\n \\axaddr_incr_reg[24] ,\n \\axaddr_incr_reg[25] ,\n \\axaddr_incr_reg[26] ,\n \\axaddr_incr_reg[27] ,\n \\axaddr_incr_reg[28] ,\n \\axaddr_incr_reg[29] ,\n \\axaddr_incr_reg[5] ,\n axready_reg,\n s_axi_arlen,\n s_axi_arvalid,\n s_axi_araddr,\n \\RD_PRI_REG_STARVE.rnw_i_reg ,\n axready_reg_0,\n s_axi_arburst,\n s_axi_arid);\n output s_axi_arready;\n output r_push;\n output [1:0]in;\n output axvalid;\n output [23:0]\\app_addr_r1_reg[27] ;\n output \\app_addr_r1_reg[6] ;\n input areset_d1;\n input CLK;\n input next;\n input \\axaddr_incr_reg[6] ;\n input \\axaddr_incr_reg[7] ;\n input \\axaddr_incr_reg[9] ;\n input \\axaddr_incr_reg[10] ;\n input \\axaddr_incr_reg[11] ;\n input \\axaddr_incr_reg[12] ;\n input \\axaddr_incr_reg[13] ;\n input \\axaddr_incr_reg[14] ;\n input \\axaddr_incr_reg[15] ;\n input \\axaddr_incr_reg[16] ;\n input \\axaddr_incr_reg[17] ;\n input \\axaddr_incr_reg[18] ;\n input \\axaddr_incr_reg[19] ;\n input \\axaddr_incr_reg[20] ;\n input \\axaddr_incr_reg[21] ;\n input \\axaddr_incr_reg[22] ;\n input \\axaddr_incr_reg[23] ;\n input \\axaddr_incr_reg[24] ;\n input \\axaddr_incr_reg[25] ;\n input \\axaddr_incr_reg[26] ;\n input \\axaddr_incr_reg[27] ;\n input \\axaddr_incr_reg[28] ;\n input \\axaddr_incr_reg[29] ;\n input \\axaddr_incr_reg[5] ;\n input axready_reg;\n input [7:0]s_axi_arlen;\n input s_axi_arvalid;\n input [29:0]s_axi_araddr;\n input \\RD_PRI_REG_STARVE.rnw_i_reg ;\n input axready_reg_0;\n input [0:0]s_axi_arburst;\n input [0:0]s_axi_arid;\n\n wire CLK;\n wire \\RD_PRI_REG_STARVE.rnw_i_reg ;\n wire [23:0]\\app_addr_r1_reg[27] ;\n wire \\app_addr_r1_reg[6] ;\n wire ar_cmd_fsm_0_n_101;\n wire ar_cmd_fsm_0_n_102;\n wire ar_cmd_fsm_0_n_103;\n wire ar_cmd_fsm_0_n_134;\n wire ar_cmd_fsm_0_n_135;\n wire ar_cmd_fsm_0_n_136;\n wire ar_cmd_fsm_0_n_137;\n wire ar_cmd_fsm_0_n_138;\n wire ar_cmd_fsm_0_n_139;\n wire ar_cmd_fsm_0_n_140;\n wire ar_cmd_fsm_0_n_141;\n wire ar_cmd_fsm_0_n_145;\n wire ar_cmd_fsm_0_n_146;\n wire ar_cmd_fsm_0_n_86;\n wire ar_cmd_fsm_0_n_87;\n wire ar_cmd_fsm_0_n_88;\n wire ar_cmd_fsm_0_n_89;\n wire ar_cmd_fsm_0_n_90;\n wire ar_cmd_fsm_0_n_91;\n wire ar_cmd_fsm_0_n_92;\n wire ar_cmd_fsm_0_n_93;\n wire ar_cmd_fsm_0_n_94;\n wire ar_cmd_fsm_0_n_95;\n wire areset_d1;\n wire arvalid_int;\n wire [29:0]axaddr;\n wire [29:0]axaddr_incr;\n wire \\axaddr_incr_reg[10] ;\n wire \\axaddr_incr_reg[11] ;\n wire \\axaddr_incr_reg[12] ;\n wire \\axaddr_incr_reg[13] ;\n wire \\axaddr_incr_reg[14] ;\n wire \\axaddr_incr_reg[15] ;\n wire \\axaddr_incr_reg[16] ;\n wire \\axaddr_incr_reg[17] ;\n wire \\axaddr_incr_reg[18] ;\n wire \\axaddr_incr_reg[19] ;\n wire \\axaddr_incr_reg[20] ;\n wire \\axaddr_incr_reg[21] ;\n wire \\axaddr_incr_reg[22] ;\n wire \\axaddr_incr_reg[23] ;\n wire \\axaddr_incr_reg[24] ;\n wire \\axaddr_incr_reg[25] ;\n wire \\axaddr_incr_reg[26] ;\n wire \\axaddr_incr_reg[27] ;\n wire \\axaddr_incr_reg[28] ;\n wire \\axaddr_incr_reg[29] ;\n wire \\axaddr_incr_reg[5] ;\n wire \\axaddr_incr_reg[6] ;\n wire \\axaddr_incr_reg[7] ;\n wire \\axaddr_incr_reg[9] ;\n wire [8:5]axaddr_int;\n wire [29:0]axaddr_int__0;\n wire [1:1]axburst;\n wire axi_mc_cmd_translator_0_n_30;\n wire axi_mc_cmd_translator_0_n_31;\n wire axi_mc_cmd_translator_0_n_32;\n wire axi_mc_cmd_translator_0_n_33;\n wire axi_mc_cmd_translator_0_n_34;\n wire axi_mc_cmd_translator_0_n_35;\n wire axi_mc_cmd_translator_0_n_36;\n wire axi_mc_cmd_translator_0_n_37;\n wire axi_mc_cmd_translator_0_n_72;\n wire axi_mc_cmd_translator_0_n_73;\n wire axi_mc_cmd_translator_0_n_74;\n wire axi_mc_cmd_translator_0_n_75;\n wire \\axi_mc_incr_cmd_0/axlen_cnt ;\n wire [29:0]\\axi_mc_incr_cmd_0/p_0_in ;\n wire [3:0]axi_mc_incr_cmd_byte_addr;\n wire [29:4]axi_mc_incr_cmd_byte_addr__0;\n wire \\axi_mc_wrap_cmd_0/axlen_cnt ;\n wire [3:0]\\axi_mc_wrap_cmd_0/int_addr ;\n wire [7:0]axlen;\n wire [3:0]axlen_int;\n wire [7:4]axlen_int__0;\n wire axready_reg;\n wire axready_reg_0;\n wire axvalid;\n wire [1:0]in;\n wire next;\n wire [29:0]p_0_in;\n wire r_push;\n wire [29:0]s_axi_araddr;\n wire [0:0]s_axi_arburst;\n wire [0:0]s_axi_arid;\n wire [7:0]s_axi_arlen;\n wire s_axi_arready;\n wire s_axi_arvalid;\n\n ddr3_if_mig_7series_v4_0_axi_mc_cmd_fsm ar_cmd_fsm_0\n (.CLK(CLK),\n .D({axlen_int__0,axlen_int}),\n .DI(ar_cmd_fsm_0_n_145),\n .E(\\axi_mc_incr_cmd_0/axlen_cnt ),\n .Q({axi_mc_cmd_translator_0_n_30,axi_mc_cmd_translator_0_n_31,axi_mc_cmd_translator_0_n_32,axi_mc_cmd_translator_0_n_33,axi_mc_cmd_translator_0_n_34,axi_mc_cmd_translator_0_n_35,axi_mc_cmd_translator_0_n_36,axi_mc_cmd_translator_0_n_37}),\n .\\RD_PRI_REG_STARVE.rnw_i_reg (\\RD_PRI_REG_STARVE.rnw_i_reg ),\n .S({ar_cmd_fsm_0_n_101,ar_cmd_fsm_0_n_102,ar_cmd_fsm_0_n_103}),\n .\\app_addr_r1_reg[27] (\\app_addr_r1_reg[27] ),\n .\\app_addr_r1_reg[6] (\\app_addr_r1_reg[6] ),\n .areset_d1(areset_d1),\n .arvalid_int(arvalid_int),\n .\\axaddr_incr_reg[10] (\\axaddr_incr_reg[10] ),\n .\\axaddr_incr_reg[11] (\\axaddr_incr_reg[11] ),\n .\\axaddr_incr_reg[12] (\\axaddr_incr_reg[12] ),\n .\\axaddr_incr_reg[13] (\\axaddr_incr_reg[13] ),\n .\\axaddr_incr_reg[14] (\\axaddr_incr_reg[14] ),\n .\\axaddr_incr_reg[15] (\\axaddr_incr_reg[15] ),\n .\\axaddr_incr_reg[16] (\\axaddr_incr_reg[16] ),\n .\\axaddr_incr_reg[17] (\\axaddr_incr_reg[17] ),\n .\\axaddr_incr_reg[18] (\\axaddr_incr_reg[18] ),\n .\\axaddr_incr_reg[19] (\\axaddr_incr_reg[19] ),\n .\\axaddr_incr_reg[20] (\\axaddr_incr_reg[20] ),\n .\\axaddr_incr_reg[21] (\\axaddr_incr_reg[21] ),\n .\\axaddr_incr_reg[22] (\\axaddr_incr_reg[22] ),\n .\\axaddr_incr_reg[23] (\\axaddr_incr_reg[23] ),\n .\\axaddr_incr_reg[24] (\\axaddr_incr_reg[24] ),\n .\\axaddr_incr_reg[25] (\\axaddr_incr_reg[25] ),\n .\\axaddr_incr_reg[26] (\\axaddr_incr_reg[26] ),\n .\\axaddr_incr_reg[27] (\\axaddr_incr_reg[27] ),\n .\\axaddr_incr_reg[28] (\\axaddr_incr_reg[28] ),\n .\\axaddr_incr_reg[29] ({axi_mc_incr_cmd_byte_addr__0[29:8],axi_mc_incr_cmd_byte_addr__0[4]}),\n .\\axaddr_incr_reg[29]_0 (p_0_in),\n .\\axaddr_incr_reg[29]_1 (axaddr_incr),\n .\\axaddr_incr_reg[29]_2 (\\axaddr_incr_reg[29] ),\n .\\axaddr_incr_reg[5] (\\axaddr_incr_reg[5] ),\n .\\axaddr_incr_reg[6] (\\axaddr_incr_reg[6] ),\n .\\axaddr_incr_reg[7] (\\axaddr_incr_reg[7] ),\n .\\axaddr_incr_reg[9] (\\axaddr_incr_reg[9] ),\n .\\axaddr_reg[29] ({axaddr_int__0[29:9],axaddr_int,axaddr_int__0[4:0]}),\n .\\axaddr_reg[29]_0 (axaddr),\n .axburst(axburst),\n .\\axburst_reg[1] (ar_cmd_fsm_0_n_95),\n .\\axid_reg[0] (ar_cmd_fsm_0_n_146),\n .\\axlen_cnt_reg[0] (\\axi_mc_wrap_cmd_0/axlen_cnt ),\n .\\axlen_cnt_reg[3] ({ar_cmd_fsm_0_n_138,ar_cmd_fsm_0_n_139,ar_cmd_fsm_0_n_140,ar_cmd_fsm_0_n_141}),\n .\\axlen_cnt_reg[3]_0 ({axi_mc_cmd_translator_0_n_72,axi_mc_cmd_translator_0_n_73,axi_mc_cmd_translator_0_n_74,axi_mc_cmd_translator_0_n_75}),\n .\\axlen_cnt_reg[7] ({ar_cmd_fsm_0_n_86,ar_cmd_fsm_0_n_87,ar_cmd_fsm_0_n_88,ar_cmd_fsm_0_n_89,ar_cmd_fsm_0_n_90,ar_cmd_fsm_0_n_91,ar_cmd_fsm_0_n_92,ar_cmd_fsm_0_n_93}),\n .\\axlen_reg[7] (axlen),\n .axready_reg_0(axready_reg),\n .axready_reg_1(axready_reg_0),\n .axvalid(axvalid),\n .in(in[1]),\n .in0(axi_mc_incr_cmd_byte_addr),\n .\\int_addr_reg[3] ({ar_cmd_fsm_0_n_134,ar_cmd_fsm_0_n_135,ar_cmd_fsm_0_n_136,ar_cmd_fsm_0_n_137}),\n .\\int_addr_reg[3]_0 (\\axi_mc_wrap_cmd_0/int_addr ),\n .next(next),\n .out(\\axi_mc_incr_cmd_0/p_0_in ),\n .r_rlast_reg(ar_cmd_fsm_0_n_94),\n .s_axi_araddr(s_axi_araddr),\n .s_axi_arburst(s_axi_arburst),\n .s_axi_arid(s_axi_arid),\n .s_axi_arlen(s_axi_arlen),\n .s_axi_arready(s_axi_arready),\n .s_axi_arvalid(s_axi_arvalid));\n FDRE \\axaddr_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[0]),\n .Q(axaddr[0]),\n .R(1'b0));\n FDRE \\axaddr_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[10]),\n .Q(axaddr[10]),\n .R(1'b0));\n FDRE \\axaddr_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[11]),\n .Q(axaddr[11]),\n .R(1'b0));\n FDRE \\axaddr_reg[12] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[12]),\n .Q(axaddr[12]),\n .R(1'b0));\n FDRE \\axaddr_reg[13] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[13]),\n .Q(axaddr[13]),\n .R(1'b0));\n FDRE \\axaddr_reg[14] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[14]),\n .Q(axaddr[14]),\n .R(1'b0));\n FDRE \\axaddr_reg[15] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[15]),\n .Q(axaddr[15]),\n .R(1'b0));\n FDRE \\axaddr_reg[16] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[16]),\n .Q(axaddr[16]),\n .R(1'b0));\n FDRE \\axaddr_reg[17] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[17]),\n .Q(axaddr[17]),\n .R(1'b0));\n FDRE \\axaddr_reg[18] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[18]),\n .Q(axaddr[18]),\n .R(1'b0));\n FDRE \\axaddr_reg[19] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[19]),\n .Q(axaddr[19]),\n .R(1'b0));\n FDRE \\axaddr_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[1]),\n .Q(axaddr[1]),\n .R(1'b0));\n FDRE \\axaddr_reg[20] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[20]),\n .Q(axaddr[20]),\n .R(1'b0));\n FDRE \\axaddr_reg[21] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[21]),\n .Q(axaddr[21]),\n .R(1'b0));\n FDRE \\axaddr_reg[22] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[22]),\n .Q(axaddr[22]),\n .R(1'b0));\n FDRE \\axaddr_reg[23] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[23]),\n .Q(axaddr[23]),\n .R(1'b0));\n FDRE \\axaddr_reg[24] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[24]),\n .Q(axaddr[24]),\n .R(1'b0));\n FDRE \\axaddr_reg[25] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[25]),\n .Q(axaddr[25]),\n .R(1'b0));\n FDRE \\axaddr_reg[26] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[26]),\n .Q(axaddr[26]),\n .R(1'b0));\n FDRE \\axaddr_reg[27] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[27]),\n .Q(axaddr[27]),\n .R(1'b0));\n FDRE \\axaddr_reg[28] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[28]),\n .Q(axaddr[28]),\n .R(1'b0));\n FDRE \\axaddr_reg[29] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[29]),\n .Q(axaddr[29]),\n .R(1'b0));\n FDRE \\axaddr_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[2]),\n .Q(axaddr[2]),\n .R(1'b0));\n FDRE \\axaddr_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[3]),\n .Q(axaddr[3]),\n .R(1'b0));\n FDRE \\axaddr_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[4]),\n .Q(axaddr[4]),\n .R(1'b0));\n FDRE \\axaddr_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int[5]),\n .Q(axaddr[5]),\n .R(1'b0));\n FDRE \\axaddr_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int[6]),\n .Q(axaddr[6]),\n .R(1'b0));\n FDRE \\axaddr_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int[7]),\n .Q(axaddr[7]),\n .R(1'b0));\n FDRE \\axaddr_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int[8]),\n .Q(axaddr[8]),\n .R(1'b0));\n FDRE \\axaddr_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[9]),\n .Q(axaddr[9]),\n .R(1'b0));\n FDRE \\axburst_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(ar_cmd_fsm_0_n_95),\n .Q(axburst),\n .R(1'b0));\n ddr3_if_mig_7series_v4_0_axi_mc_cmd_translator__parameterized0 axi_mc_cmd_translator_0\n (.CLK(CLK),\n .D({ar_cmd_fsm_0_n_86,ar_cmd_fsm_0_n_87,ar_cmd_fsm_0_n_88,ar_cmd_fsm_0_n_89,ar_cmd_fsm_0_n_90,ar_cmd_fsm_0_n_91,ar_cmd_fsm_0_n_92,ar_cmd_fsm_0_n_93}),\n .DI(ar_cmd_fsm_0_n_145),\n .E(\\axi_mc_incr_cmd_0/axlen_cnt ),\n .Q({axi_mc_cmd_translator_0_n_30,axi_mc_cmd_translator_0_n_31,axi_mc_cmd_translator_0_n_32,axi_mc_cmd_translator_0_n_33,axi_mc_cmd_translator_0_n_34,axi_mc_cmd_translator_0_n_35,axi_mc_cmd_translator_0_n_36,axi_mc_cmd_translator_0_n_37}),\n .S({ar_cmd_fsm_0_n_101,ar_cmd_fsm_0_n_102,ar_cmd_fsm_0_n_103,axi_mc_incr_cmd_byte_addr__0[4]}),\n .\\app_addr_r1_reg[27] (axaddr_incr),\n .\\app_addr_r1_reg[6] (\\axi_mc_wrap_cmd_0/int_addr ),\n .areset_d1(areset_d1),\n .\\axlen_cnt_reg[3] ({axi_mc_cmd_translator_0_n_72,axi_mc_cmd_translator_0_n_73,axi_mc_cmd_translator_0_n_74,axi_mc_cmd_translator_0_n_75}),\n .\\axlen_cnt_reg[3]_0 ({ar_cmd_fsm_0_n_138,ar_cmd_fsm_0_n_139,ar_cmd_fsm_0_n_140,ar_cmd_fsm_0_n_141}),\n .axready_reg(axi_mc_incr_cmd_byte_addr__0[29:8]),\n .axready_reg_0(p_0_in),\n .axready_reg_1(\\axi_mc_wrap_cmd_0/axlen_cnt ),\n .axready_reg_2({ar_cmd_fsm_0_n_134,ar_cmd_fsm_0_n_135,ar_cmd_fsm_0_n_136,ar_cmd_fsm_0_n_137}),\n .in0(axi_mc_incr_cmd_byte_addr),\n .out(\\axi_mc_incr_cmd_0/p_0_in ));\n FDRE \\axid_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(ar_cmd_fsm_0_n_146),\n .Q(in[1]),\n .R(1'b0));\n FDRE \\axlen_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(axlen_int[0]),\n .Q(axlen[0]),\n .R(1'b0));\n FDRE \\axlen_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(axlen_int[1]),\n .Q(axlen[1]),\n .R(1'b0));\n FDRE \\axlen_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(axlen_int[2]),\n .Q(axlen[2]),\n .R(1'b0));\n FDRE \\axlen_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(axlen_int[3]),\n .Q(axlen[3]),\n .R(1'b0));\n FDRE \\axlen_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(axlen_int__0[4]),\n .Q(axlen[4]),\n .R(1'b0));\n FDRE \\axlen_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(axlen_int__0[5]),\n .Q(axlen[5]),\n .R(1'b0));\n FDRE \\axlen_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(axlen_int__0[6]),\n .Q(axlen[6]),\n .R(1'b0));\n FDRE \\axlen_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(axlen_int__0[7]),\n .Q(axlen[7]),\n .R(1'b0));\n FDRE axvalid_reg\n (.C(CLK),\n .CE(1'b1),\n .D(arvalid_int),\n .Q(axvalid),\n .R(areset_d1));\n FDRE r_push_reg\n (.C(CLK),\n .CE(1'b1),\n .D(next),\n .Q(r_push),\n .R(1'b0));\n FDRE r_rlast_reg\n (.C(CLK),\n .CE(1'b1),\n .D(ar_cmd_fsm_0_n_94),\n .Q(in[0]),\n .R(1'b0));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_axi_mc_aw_channel\n (s_axi_awready,\n awvalid_int,\n b_awid,\n b_push,\n \\app_addr_r1_reg[4] ,\n \\app_addr_r1_reg[5] ,\n \\app_addr_r1_reg[6] ,\n \\app_addr_r1_reg[7] ,\n \\app_addr_r1_reg[8] ,\n \\app_addr_r1_reg[9] ,\n \\app_addr_r1_reg[10] ,\n \\app_addr_r1_reg[11] ,\n \\app_addr_r1_reg[12] ,\n \\app_addr_r1_reg[13] ,\n \\app_addr_r1_reg[14] ,\n \\app_addr_r1_reg[15] ,\n \\app_addr_r1_reg[16] ,\n \\app_addr_r1_reg[17] ,\n \\app_addr_r1_reg[18] ,\n \\app_addr_r1_reg[19] ,\n \\app_addr_r1_reg[20] ,\n \\app_addr_r1_reg[21] ,\n \\app_addr_r1_reg[22] ,\n \\app_addr_r1_reg[23] ,\n \\app_addr_r1_reg[24] ,\n \\app_addr_r1_reg[25] ,\n \\app_addr_r1_reg[26] ,\n \\app_addr_r1_reg[27] ,\n \\app_addr_r1_reg[3] ,\n areset_d1,\n CLK,\n axready_reg,\n s_axi_awlen,\n s_axi_awvalid,\n \\RD_PRI_REG_STARVE.rnw_i_reg ,\n s_axi_awaddr,\n \\int_addr_reg[3] ,\n axready_reg_0,\n s_axi_awburst,\n \\RD_PRI_REG_STARVE.rnw_i_reg_0 ,\n s_axi_awid);\n output s_axi_awready;\n output awvalid_int;\n output b_awid;\n output b_push;\n output \\app_addr_r1_reg[4] ;\n output \\app_addr_r1_reg[5] ;\n output [0:0]\\app_addr_r1_reg[6] ;\n output \\app_addr_r1_reg[7] ;\n output \\app_addr_r1_reg[8] ;\n output \\app_addr_r1_reg[9] ;\n output \\app_addr_r1_reg[10] ;\n output \\app_addr_r1_reg[11] ;\n output \\app_addr_r1_reg[12] ;\n output \\app_addr_r1_reg[13] ;\n output \\app_addr_r1_reg[14] ;\n output \\app_addr_r1_reg[15] ;\n output \\app_addr_r1_reg[16] ;\n output \\app_addr_r1_reg[17] ;\n output \\app_addr_r1_reg[18] ;\n output \\app_addr_r1_reg[19] ;\n output \\app_addr_r1_reg[20] ;\n output \\app_addr_r1_reg[21] ;\n output \\app_addr_r1_reg[22] ;\n output \\app_addr_r1_reg[23] ;\n output \\app_addr_r1_reg[24] ;\n output \\app_addr_r1_reg[25] ;\n output \\app_addr_r1_reg[26] ;\n output \\app_addr_r1_reg[27] ;\n output \\app_addr_r1_reg[3] ;\n input areset_d1;\n input CLK;\n input axready_reg;\n input [7:0]s_axi_awlen;\n input s_axi_awvalid;\n input \\RD_PRI_REG_STARVE.rnw_i_reg ;\n input [29:0]s_axi_awaddr;\n input \\int_addr_reg[3] ;\n input axready_reg_0;\n input [0:0]s_axi_awburst;\n input \\RD_PRI_REG_STARVE.rnw_i_reg_0 ;\n input [0:0]s_axi_awid;\n\n wire CLK;\n wire \\RD_PRI_REG_STARVE.rnw_i_reg ;\n wire \\RD_PRI_REG_STARVE.rnw_i_reg_0 ;\n wire \\app_addr_r1_reg[10] ;\n wire \\app_addr_r1_reg[11] ;\n wire \\app_addr_r1_reg[12] ;\n wire \\app_addr_r1_reg[13] ;\n wire \\app_addr_r1_reg[14] ;\n wire \\app_addr_r1_reg[15] ;\n wire \\app_addr_r1_reg[16] ;\n wire \\app_addr_r1_reg[17] ;\n wire \\app_addr_r1_reg[18] ;\n wire \\app_addr_r1_reg[19] ;\n wire \\app_addr_r1_reg[20] ;\n wire \\app_addr_r1_reg[21] ;\n wire \\app_addr_r1_reg[22] ;\n wire \\app_addr_r1_reg[23] ;\n wire \\app_addr_r1_reg[24] ;\n wire \\app_addr_r1_reg[25] ;\n wire \\app_addr_r1_reg[26] ;\n wire \\app_addr_r1_reg[27] ;\n wire \\app_addr_r1_reg[3] ;\n wire \\app_addr_r1_reg[4] ;\n wire \\app_addr_r1_reg[5] ;\n wire [0:0]\\app_addr_r1_reg[6] ;\n wire \\app_addr_r1_reg[7] ;\n wire \\app_addr_r1_reg[8] ;\n wire \\app_addr_r1_reg[9] ;\n wire areset_d1;\n wire aw_cmd_fsm_0_n_10;\n wire aw_cmd_fsm_0_n_102;\n wire aw_cmd_fsm_0_n_11;\n wire aw_cmd_fsm_0_n_12;\n wire aw_cmd_fsm_0_n_134;\n wire aw_cmd_fsm_0_n_135;\n wire aw_cmd_fsm_0_n_136;\n wire aw_cmd_fsm_0_n_137;\n wire aw_cmd_fsm_0_n_138;\n wire aw_cmd_fsm_0_n_139;\n wire aw_cmd_fsm_0_n_14;\n wire aw_cmd_fsm_0_n_140;\n wire aw_cmd_fsm_0_n_141;\n wire aw_cmd_fsm_0_n_146;\n wire aw_cmd_fsm_0_n_5;\n wire aw_cmd_fsm_0_n_6;\n wire aw_cmd_fsm_0_n_7;\n wire aw_cmd_fsm_0_n_8;\n wire aw_cmd_fsm_0_n_9;\n wire awvalid_int;\n wire [29:0]axaddr;\n wire [29:0]axaddr_incr;\n wire [8:5]axaddr_int;\n wire [29:0]axaddr_int__0;\n wire [1:1]axburst;\n wire axi_mc_cmd_translator_0_n_30;\n wire axi_mc_cmd_translator_0_n_31;\n wire axi_mc_cmd_translator_0_n_32;\n wire axi_mc_cmd_translator_0_n_33;\n wire axi_mc_cmd_translator_0_n_34;\n wire axi_mc_cmd_translator_0_n_35;\n wire axi_mc_cmd_translator_0_n_36;\n wire axi_mc_cmd_translator_0_n_37;\n wire axi_mc_cmd_translator_0_n_72;\n wire axi_mc_cmd_translator_0_n_73;\n wire axi_mc_cmd_translator_0_n_74;\n wire axi_mc_cmd_translator_0_n_75;\n wire \\axi_mc_incr_cmd_0/axlen_cnt ;\n wire [29:0]\\axi_mc_incr_cmd_0/p_0_in ;\n wire [3:0]axi_mc_incr_cmd_byte_addr;\n wire [29:4]axi_mc_incr_cmd_byte_addr__0;\n wire \\axi_mc_wrap_cmd_0/axlen_cnt ;\n wire [3:0]\\axi_mc_wrap_cmd_0/int_addr ;\n wire axid;\n wire [7:0]axlen;\n wire [3:0]axlen_int;\n wire [7:4]axlen_int__0;\n wire axready_reg;\n wire axready_reg_0;\n wire axvalid;\n wire b_awid;\n wire b_push;\n wire \\int_addr_reg[3] ;\n wire [29:0]p_0_in;\n wire [29:0]s_axi_awaddr;\n wire [0:0]s_axi_awburst;\n wire [0:0]s_axi_awid;\n wire [7:0]s_axi_awlen;\n wire s_axi_awready;\n wire s_axi_awvalid;\n\n ddr3_if_mig_7series_v4_0_axi_mc_wr_cmd_fsm aw_cmd_fsm_0\n (.CLK(CLK),\n .D({aw_cmd_fsm_0_n_5,aw_cmd_fsm_0_n_6,aw_cmd_fsm_0_n_7,aw_cmd_fsm_0_n_8,aw_cmd_fsm_0_n_9,aw_cmd_fsm_0_n_10,aw_cmd_fsm_0_n_11,aw_cmd_fsm_0_n_12}),\n .E(\\axi_mc_incr_cmd_0/axlen_cnt ),\n .Q({axi_mc_cmd_translator_0_n_30,axi_mc_cmd_translator_0_n_31,axi_mc_cmd_translator_0_n_32,axi_mc_cmd_translator_0_n_33,axi_mc_cmd_translator_0_n_34,axi_mc_cmd_translator_0_n_35,axi_mc_cmd_translator_0_n_36,axi_mc_cmd_translator_0_n_37}),\n .\\RD_PRI_REG_STARVE.rnw_i_reg (\\RD_PRI_REG_STARVE.rnw_i_reg ),\n .\\RD_PRI_REG_STARVE.rnw_i_reg_0 (\\RD_PRI_REG_STARVE.rnw_i_reg_0 ),\n .S(aw_cmd_fsm_0_n_102),\n .\\app_addr_r1_reg[10] (\\app_addr_r1_reg[10] ),\n .\\app_addr_r1_reg[11] (\\app_addr_r1_reg[11] ),\n .\\app_addr_r1_reg[12] (\\app_addr_r1_reg[12] ),\n .\\app_addr_r1_reg[13] (\\app_addr_r1_reg[13] ),\n .\\app_addr_r1_reg[14] (\\app_addr_r1_reg[14] ),\n .\\app_addr_r1_reg[15] (\\app_addr_r1_reg[15] ),\n .\\app_addr_r1_reg[16] (\\app_addr_r1_reg[16] ),\n .\\app_addr_r1_reg[17] (\\app_addr_r1_reg[17] ),\n .\\app_addr_r1_reg[18] (\\app_addr_r1_reg[18] ),\n .\\app_addr_r1_reg[19] (\\app_addr_r1_reg[19] ),\n .\\app_addr_r1_reg[20] (\\app_addr_r1_reg[20] ),\n .\\app_addr_r1_reg[21] (\\app_addr_r1_reg[21] ),\n .\\app_addr_r1_reg[22] (\\app_addr_r1_reg[22] ),\n .\\app_addr_r1_reg[23] (\\app_addr_r1_reg[23] ),\n .\\app_addr_r1_reg[24] (\\app_addr_r1_reg[24] ),\n .\\app_addr_r1_reg[25] (\\app_addr_r1_reg[25] ),\n .\\app_addr_r1_reg[26] (\\app_addr_r1_reg[26] ),\n .\\app_addr_r1_reg[27] (\\app_addr_r1_reg[27] ),\n .\\app_addr_r1_reg[3] (\\app_addr_r1_reg[3] ),\n .\\app_addr_r1_reg[4] (\\app_addr_r1_reg[4] ),\n .\\app_addr_r1_reg[5] (\\app_addr_r1_reg[5] ),\n .\\app_addr_r1_reg[6] (\\app_addr_r1_reg[6] ),\n .\\app_addr_r1_reg[7] (\\app_addr_r1_reg[7] ),\n .\\app_addr_r1_reg[8] (\\app_addr_r1_reg[8] ),\n .\\app_addr_r1_reg[9] (\\app_addr_r1_reg[9] ),\n .areset_d1(areset_d1),\n .awvalid_int(awvalid_int),\n .\\axaddr_incr_reg[11] (aw_cmd_fsm_0_n_146),\n .\\axaddr_incr_reg[29] ({axi_mc_incr_cmd_byte_addr__0[29:9],axi_mc_incr_cmd_byte_addr__0[7:4]}),\n .\\axaddr_incr_reg[29]_0 (p_0_in),\n .\\axaddr_incr_reg[29]_1 (axaddr_incr),\n .\\axaddr_reg[29] ({axaddr_int__0[29:9],axaddr_int,axaddr_int__0[4:0]}),\n .\\axaddr_reg[29]_0 (axaddr),\n .axburst(axburst),\n .\\axburst_reg[1] (aw_cmd_fsm_0_n_14),\n .axid(axid),\n .\\axlen_cnt_reg[0] (\\axi_mc_wrap_cmd_0/axlen_cnt ),\n .\\axlen_cnt_reg[3] ({aw_cmd_fsm_0_n_138,aw_cmd_fsm_0_n_139,aw_cmd_fsm_0_n_140,aw_cmd_fsm_0_n_141}),\n .\\axlen_cnt_reg[3]_0 ({axi_mc_cmd_translator_0_n_72,axi_mc_cmd_translator_0_n_73,axi_mc_cmd_translator_0_n_74,axi_mc_cmd_translator_0_n_75}),\n .axlen_int(axlen_int),\n .\\axlen_reg[7] (axlen_int__0),\n .\\axlen_reg[7]_0 (axlen),\n .axready_reg_0(axready_reg),\n .axready_reg_1(axready_reg_0),\n .axvalid(axvalid),\n .b_awid(b_awid),\n .b_push(b_push),\n .in0(axi_mc_incr_cmd_byte_addr),\n .\\int_addr_reg[3] ({aw_cmd_fsm_0_n_134,aw_cmd_fsm_0_n_135,aw_cmd_fsm_0_n_136,aw_cmd_fsm_0_n_137}),\n .\\int_addr_reg[3]_0 (\\int_addr_reg[3] ),\n .\\int_addr_reg[3]_1 (\\axi_mc_wrap_cmd_0/int_addr ),\n .out(\\axi_mc_incr_cmd_0/p_0_in ),\n .s_axi_awaddr(s_axi_awaddr),\n .s_axi_awburst(s_axi_awburst),\n .s_axi_awid(s_axi_awid),\n .s_axi_awlen(s_axi_awlen),\n .s_axi_awready(s_axi_awready),\n .s_axi_awvalid(s_axi_awvalid));\n FDRE \\axaddr_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[0]),\n .Q(axaddr[0]),\n .R(1'b0));\n FDRE \\axaddr_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[10]),\n .Q(axaddr[10]),\n .R(1'b0));\n FDRE \\axaddr_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[11]),\n .Q(axaddr[11]),\n .R(1'b0));\n FDRE \\axaddr_reg[12] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[12]),\n .Q(axaddr[12]),\n .R(1'b0));\n FDRE \\axaddr_reg[13] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[13]),\n .Q(axaddr[13]),\n .R(1'b0));\n FDRE \\axaddr_reg[14] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[14]),\n .Q(axaddr[14]),\n .R(1'b0));\n FDRE \\axaddr_reg[15] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[15]),\n .Q(axaddr[15]),\n .R(1'b0));\n FDRE \\axaddr_reg[16] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[16]),\n .Q(axaddr[16]),\n .R(1'b0));\n FDRE \\axaddr_reg[17] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[17]),\n .Q(axaddr[17]),\n .R(1'b0));\n FDRE \\axaddr_reg[18] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[18]),\n .Q(axaddr[18]),\n .R(1'b0));\n FDRE \\axaddr_reg[19] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[19]),\n .Q(axaddr[19]),\n .R(1'b0));\n FDRE \\axaddr_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[1]),\n .Q(axaddr[1]),\n .R(1'b0));\n FDRE \\axaddr_reg[20] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[20]),\n .Q(axaddr[20]),\n .R(1'b0));\n FDRE \\axaddr_reg[21] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[21]),\n .Q(axaddr[21]),\n .R(1'b0));\n FDRE \\axaddr_reg[22] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[22]),\n .Q(axaddr[22]),\n .R(1'b0));\n FDRE \\axaddr_reg[23] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[23]),\n .Q(axaddr[23]),\n .R(1'b0));\n FDRE \\axaddr_reg[24] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[24]),\n .Q(axaddr[24]),\n .R(1'b0));\n FDRE \\axaddr_reg[25] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[25]),\n .Q(axaddr[25]),\n .R(1'b0));\n FDRE \\axaddr_reg[26] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[26]),\n .Q(axaddr[26]),\n .R(1'b0));\n FDRE \\axaddr_reg[27] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[27]),\n .Q(axaddr[27]),\n .R(1'b0));\n FDRE \\axaddr_reg[28] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[28]),\n .Q(axaddr[28]),\n .R(1'b0));\n FDRE \\axaddr_reg[29] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[29]),\n .Q(axaddr[29]),\n .R(1'b0));\n FDRE \\axaddr_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[2]),\n .Q(axaddr[2]),\n .R(1'b0));\n FDRE \\axaddr_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[3]),\n .Q(axaddr[3]),\n .R(1'b0));\n FDRE \\axaddr_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[4]),\n .Q(axaddr[4]),\n .R(1'b0));\n FDRE \\axaddr_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int[5]),\n .Q(axaddr[5]),\n .R(1'b0));\n FDRE \\axaddr_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int[6]),\n .Q(axaddr[6]),\n .R(1'b0));\n FDRE \\axaddr_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int[7]),\n .Q(axaddr[7]),\n .R(1'b0));\n FDRE \\axaddr_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int[8]),\n .Q(axaddr[8]),\n .R(1'b0));\n FDRE \\axaddr_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(axaddr_int__0[9]),\n .Q(axaddr[9]),\n .R(1'b0));\n FDRE \\axburst_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(aw_cmd_fsm_0_n_14),\n .Q(axburst),\n .R(1'b0));\n ddr3_if_mig_7series_v4_0_axi_mc_cmd_translator axi_mc_cmd_translator_0\n (.CLK(CLK),\n .D({aw_cmd_fsm_0_n_5,aw_cmd_fsm_0_n_6,aw_cmd_fsm_0_n_7,aw_cmd_fsm_0_n_8,aw_cmd_fsm_0_n_9,aw_cmd_fsm_0_n_10,aw_cmd_fsm_0_n_11,aw_cmd_fsm_0_n_12}),\n .E(\\axi_mc_incr_cmd_0/axlen_cnt ),\n .Q({axi_mc_cmd_translator_0_n_30,axi_mc_cmd_translator_0_n_31,axi_mc_cmd_translator_0_n_32,axi_mc_cmd_translator_0_n_33,axi_mc_cmd_translator_0_n_34,axi_mc_cmd_translator_0_n_35,axi_mc_cmd_translator_0_n_36,axi_mc_cmd_translator_0_n_37}),\n .S(aw_cmd_fsm_0_n_102),\n .\\app_addr_r1_reg[27] (axaddr_incr),\n .areset_d1(areset_d1),\n .\\axlen_cnt_reg[3] ({axi_mc_cmd_translator_0_n_72,axi_mc_cmd_translator_0_n_73,axi_mc_cmd_translator_0_n_74,axi_mc_cmd_translator_0_n_75}),\n .\\axlen_cnt_reg[3]_0 ({aw_cmd_fsm_0_n_138,aw_cmd_fsm_0_n_139,aw_cmd_fsm_0_n_140,aw_cmd_fsm_0_n_141}),\n .axready_reg({axi_mc_incr_cmd_byte_addr__0[29:9],axi_mc_incr_cmd_byte_addr__0[7:4]}),\n .axready_reg_0(aw_cmd_fsm_0_n_146),\n .axready_reg_1(p_0_in),\n .axready_reg_2(\\axi_mc_wrap_cmd_0/axlen_cnt ),\n .axready_reg_3({aw_cmd_fsm_0_n_134,aw_cmd_fsm_0_n_135,aw_cmd_fsm_0_n_136,aw_cmd_fsm_0_n_137}),\n .in0(axi_mc_incr_cmd_byte_addr),\n .\\int_addr_reg[3] (\\axi_mc_wrap_cmd_0/int_addr ),\n .out(\\axi_mc_incr_cmd_0/p_0_in ));\n FDRE \\axid_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(b_awid),\n .Q(axid),\n .R(1'b0));\n FDRE \\axlen_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(axlen_int[0]),\n .Q(axlen[0]),\n .R(1'b0));\n FDRE \\axlen_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(axlen_int[1]),\n .Q(axlen[1]),\n .R(1'b0));\n FDRE \\axlen_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(axlen_int[2]),\n .Q(axlen[2]),\n .R(1'b0));\n FDRE \\axlen_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(axlen_int[3]),\n .Q(axlen[3]),\n .R(1'b0));\n FDRE \\axlen_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(axlen_int__0[4]),\n .Q(axlen[4]),\n .R(1'b0));\n FDRE \\axlen_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(axlen_int__0[5]),\n .Q(axlen[5]),\n .R(1'b0));\n FDRE \\axlen_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(axlen_int__0[6]),\n .Q(axlen[6]),\n .R(1'b0));\n FDRE \\axlen_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(axlen_int__0[7]),\n .Q(axlen[7]),\n .R(1'b0));\n FDRE axvalid_reg\n (.C(CLK),\n .CE(1'b1),\n .D(awvalid_int),\n .Q(axvalid),\n .R(areset_d1));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_axi_mc_b_channel\n (s_axi_bid,\n s_axi_bvalid,\n app_en_ns1,\n wr_cmd_en,\n E,\n b_push,\n b_awid,\n CLK,\n areset_d1,\n app_rdy,\n \\RD_PRI_REG_STARVE.rnw_i_reg ,\n rd_cmd_en,\n reset_reg,\n app_en_r1,\n s_axi_bready,\n wvalid_int,\n awvalid_int,\n app_wdf_rdy);\n output [0:0]s_axi_bid;\n output s_axi_bvalid;\n output app_en_ns1;\n output wr_cmd_en;\n output [0:0]E;\n input b_push;\n input b_awid;\n input CLK;\n input areset_d1;\n input app_rdy;\n input \\RD_PRI_REG_STARVE.rnw_i_reg ;\n input rd_cmd_en;\n input reset_reg;\n input app_en_r1;\n input s_axi_bready;\n input wvalid_int;\n input awvalid_int;\n input app_wdf_rdy;\n\n wire CLK;\n wire [0:0]E;\n wire \\RD_PRI_REG_STARVE.rnw_i_reg ;\n wire app_en_ns1;\n wire app_en_r1;\n wire app_rdy;\n wire app_wdf_rdy;\n wire areset_d1;\n wire awvalid_int;\n wire b_awid;\n wire b_push;\n wire bhandshake;\n wire bid_fifo_0_n_5;\n wire bid_i;\n wire rd_cmd_en;\n wire reset_reg;\n wire [0:0]s_axi_bid;\n wire s_axi_bready;\n wire s_axi_bvalid;\n wire wr_cmd_en;\n wire wvalid_int;\n\n ddr3_if_mig_7series_v4_0_axi_mc_fifo bid_fifo_0\n (.CLK(CLK),\n .E(E),\n .\\RD_PRI_REG_STARVE.rnw_i_reg (\\RD_PRI_REG_STARVE.rnw_i_reg ),\n .app_en_ns1(app_en_ns1),\n .app_en_r1(app_en_r1),\n .app_rdy(app_rdy),\n .app_wdf_rdy(app_wdf_rdy),\n .areset_d1(areset_d1),\n .awvalid_int(awvalid_int),\n .b_awid(b_awid),\n .b_push(b_push),\n .bhandshake(bhandshake),\n .bid_i(bid_i),\n .bvalid_i_reg(bid_fifo_0_n_5),\n .bvalid_i_reg_0(s_axi_bvalid),\n .rd_cmd_en(rd_cmd_en),\n .reset_reg(reset_reg),\n .s_axi_bready(s_axi_bready),\n .wr_cmd_en(wr_cmd_en),\n .wvalid_int(wvalid_int));\n FDRE \\bid_t_reg[0] \n (.C(CLK),\n .CE(bhandshake),\n .D(bid_i),\n .Q(s_axi_bid),\n .R(areset_d1));\n FDRE bvalid_i_reg\n (.C(CLK),\n .CE(1'b1),\n .D(bid_fifo_0_n_5),\n .Q(s_axi_bvalid),\n .R(areset_d1));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_axi_mc_cmd_arbiter\n (\\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ,\n mc_app_wdf_wren_reg_reg,\n next,\n \\axaddr_incr_reg[29] ,\n \\axlen_cnt_reg[1] ,\n \\axaddr_incr_reg[29]_0 ,\n \\axlen_cnt_reg[1]_0 ,\n areset_d1,\n CLK,\n rd_cmd_en,\n wr_cmd_en,\n app_rdy,\n s_axi_awburst,\n s_axi_awready,\n s_axi_awvalid,\n s_axi_arburst,\n axready_reg,\n s_axi_arvalid,\n E);\n output \\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ;\n output mc_app_wdf_wren_reg_reg;\n output next;\n output \\axaddr_incr_reg[29] ;\n output \\axlen_cnt_reg[1] ;\n output \\axaddr_incr_reg[29]_0 ;\n output \\axlen_cnt_reg[1]_0 ;\n input areset_d1;\n input CLK;\n input rd_cmd_en;\n input wr_cmd_en;\n input app_rdy;\n input [0:0]s_axi_awburst;\n input s_axi_awready;\n input s_axi_awvalid;\n input [0:0]s_axi_arburst;\n input axready_reg;\n input s_axi_arvalid;\n input [0:0]E;\n\n wire CLK;\n wire [0:0]E;\n wire \\RD_PRI_REG_STARVE.rd_cmd_en_d1_i_1_n_0 ;\n wire \\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 ;\n wire \\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_4_n_0 ;\n wire [8:8]\\RD_PRI_REG_STARVE.rd_starve_cnt_reg__0 ;\n wire \\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ;\n wire \\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[1] ;\n wire \\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[2] ;\n wire \\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[3] ;\n wire \\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[4] ;\n wire \\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[5] ;\n wire \\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[6] ;\n wire \\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[7] ;\n wire \\RD_PRI_REG_STARVE.rnw_i_i_1_n_0 ;\n wire \\RD_PRI_REG_STARVE.wr_cmd_en_d1_i_1_n_0 ;\n wire \\RD_PRI_REG_STARVE.wr_enable_i_1_n_0 ;\n wire \\RD_PRI_REG_STARVE.wr_enable_i_2_n_0 ;\n wire \\RD_PRI_REG_STARVE.wr_enable_i_3_n_0 ;\n wire \\RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_4_n_0 ;\n wire \\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ;\n wire [7:0]\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 ;\n wire app_rdy;\n wire areset_d1;\n wire \\axaddr_incr_reg[29] ;\n wire \\axaddr_incr_reg[29]_0 ;\n wire \\axlen_cnt_reg[1] ;\n wire \\axlen_cnt_reg[1]_0 ;\n wire axready_reg;\n wire mc_app_wdf_wren_reg_reg;\n wire next;\n wire [8:0]p_0_in__0;\n wire [7:0]p_0_in__1;\n wire rd_cmd_en;\n wire rd_cmd_en_d1;\n wire [0:0]s_axi_arburst;\n wire s_axi_arvalid;\n wire [0:0]s_axi_awburst;\n wire s_axi_awready;\n wire s_axi_awvalid;\n wire wr_cmd_en;\n wire wr_cmd_en_d1;\n wire wr_enable;\n wire wr_starve_cnt;\n wire wr_starve_cnt0;\n\n (* SOFT_HLUTNM = \"soft_lutpair1187\" *) \n LUT4 #(\n .INIT(16'h8F80)) \n \\RD_PRI_REG_STARVE.rd_cmd_en_d1_i_1 \n (.I0(rd_cmd_en),\n .I1(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ),\n .I2(app_rdy),\n .I3(rd_cmd_en_d1),\n .O(\\RD_PRI_REG_STARVE.rd_cmd_en_d1_i_1_n_0 ));\n FDRE \\RD_PRI_REG_STARVE.rd_cmd_en_d1_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\RD_PRI_REG_STARVE.rd_cmd_en_d1_i_1_n_0 ),\n .Q(rd_cmd_en_d1),\n .R(areset_d1));\n LUT1 #(\n .INIT(2'h1)) \n \\RD_PRI_REG_STARVE.rd_starve_cnt[0]_i_1 \n (.I0(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ),\n .O(p_0_in__0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1191\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\RD_PRI_REG_STARVE.rd_starve_cnt[1]_i_1 \n (.I0(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ),\n .I1(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[1] ),\n .O(p_0_in__0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1191\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\RD_PRI_REG_STARVE.rd_starve_cnt[2]_i_1 \n (.I0(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ),\n .I1(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[1] ),\n .I2(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[2] ),\n .O(p_0_in__0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1184\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\RD_PRI_REG_STARVE.rd_starve_cnt[3]_i_1 \n (.I0(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[1] ),\n .I1(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ),\n .I2(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[2] ),\n .I3(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[3] ),\n .O(p_0_in__0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1184\" *) \n LUT5 #(\n .INIT(32'h7FFF8000)) \n \\RD_PRI_REG_STARVE.rd_starve_cnt[4]_i_1 \n (.I0(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[2] ),\n .I1(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ),\n .I2(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[1] ),\n .I3(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[3] ),\n .I4(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[4] ),\n .O(p_0_in__0[4]));\n LUT6 #(\n .INIT(64'h7FFFFFFF80000000)) \n \\RD_PRI_REG_STARVE.rd_starve_cnt[5]_i_1 \n (.I0(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[3] ),\n .I1(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[1] ),\n .I2(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ),\n .I3(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[2] ),\n .I4(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[4] ),\n .I5(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[5] ),\n .O(p_0_in__0[5]));\n LUT2 #(\n .INIT(4'h6)) \n \\RD_PRI_REG_STARVE.rd_starve_cnt[6]_i_1 \n (.I0(\\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_4_n_0 ),\n .I1(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[6] ),\n .O(p_0_in__0[6]));\n (* SOFT_HLUTNM = \"soft_lutpair1189\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\RD_PRI_REG_STARVE.rd_starve_cnt[7]_i_1 \n (.I0(\\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_4_n_0 ),\n .I1(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[6] ),\n .I2(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[7] ),\n .O(p_0_in__0[7]));\n LUT2 #(\n .INIT(4'hE)) \n \\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1 \n (.I0(areset_d1),\n .I1(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ),\n .O(\\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1189\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_3 \n (.I0(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[6] ),\n .I1(\\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_4_n_0 ),\n .I2(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[7] ),\n .I3(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg__0 ),\n .O(p_0_in__0[8]));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_4 \n (.I0(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[5] ),\n .I1(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[3] ),\n .I2(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[1] ),\n .I3(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ),\n .I4(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[2] ),\n .I5(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[4] ),\n .O(\\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_4_n_0 ));\n FDRE \\RD_PRI_REG_STARVE.rd_starve_cnt_reg[0] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__0[0]),\n .Q(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[0] ),\n .R(\\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 ));\n FDRE \\RD_PRI_REG_STARVE.rd_starve_cnt_reg[1] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__0[1]),\n .Q(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[1] ),\n .R(\\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 ));\n FDRE \\RD_PRI_REG_STARVE.rd_starve_cnt_reg[2] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__0[2]),\n .Q(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[2] ),\n .R(\\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 ));\n FDRE \\RD_PRI_REG_STARVE.rd_starve_cnt_reg[3] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__0[3]),\n .Q(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[3] ),\n .R(\\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 ));\n FDRE \\RD_PRI_REG_STARVE.rd_starve_cnt_reg[4] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__0[4]),\n .Q(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[4] ),\n .R(\\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 ));\n FDRE \\RD_PRI_REG_STARVE.rd_starve_cnt_reg[5] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__0[5]),\n .Q(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[5] ),\n .R(\\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 ));\n FDRE \\RD_PRI_REG_STARVE.rd_starve_cnt_reg[6] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__0[6]),\n .Q(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[6] ),\n .R(\\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 ));\n FDRE \\RD_PRI_REG_STARVE.rd_starve_cnt_reg[7] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__0[7]),\n .Q(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg_n_0_[7] ),\n .R(\\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 ));\n FDRE \\RD_PRI_REG_STARVE.rd_starve_cnt_reg[8] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__0[8]),\n .Q(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg__0 ),\n .R(\\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h55554445)) \n \\RD_PRI_REG_STARVE.rnw_i_i_1 \n (.I0(wr_enable),\n .I1(rd_cmd_en),\n .I2(wr_cmd_en_d1),\n .I3(wr_cmd_en),\n .I4(rd_cmd_en_d1),\n .O(\\RD_PRI_REG_STARVE.rnw_i_i_1_n_0 ));\n FDSE \\RD_PRI_REG_STARVE.rnw_i_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\RD_PRI_REG_STARVE.rnw_i_i_1_n_0 ),\n .Q(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ),\n .S(areset_d1));\n LUT4 #(\n .INIT(16'h2F20)) \n \\RD_PRI_REG_STARVE.wr_cmd_en_d1_i_1 \n (.I0(wr_cmd_en),\n .I1(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ),\n .I2(app_rdy),\n .I3(wr_cmd_en_d1),\n .O(\\RD_PRI_REG_STARVE.wr_cmd_en_d1_i_1_n_0 ));\n FDRE \\RD_PRI_REG_STARVE.wr_cmd_en_d1_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\RD_PRI_REG_STARVE.wr_cmd_en_d1_i_1_n_0 ),\n .Q(wr_cmd_en_d1),\n .R(areset_d1));\n LUT5 #(\n .INIT(32'h0000BAAA)) \n \\RD_PRI_REG_STARVE.wr_enable_i_1 \n (.I0(wr_enable),\n .I1(\\RD_PRI_REG_STARVE.wr_enable_i_2_n_0 ),\n .I2(app_rdy),\n .I3(wr_cmd_en),\n .I4(wr_starve_cnt0),\n .O(\\RD_PRI_REG_STARVE.wr_enable_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\RD_PRI_REG_STARVE.wr_enable_i_2 \n (.I0(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [4]),\n .I1(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [5]),\n .I2(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [7]),\n .I3(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [6]),\n .I4(\\RD_PRI_REG_STARVE.wr_enable_i_3_n_0 ),\n .O(\\RD_PRI_REG_STARVE.wr_enable_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1188\" *) \n LUT4 #(\n .INIT(16'h7FFF)) \n \\RD_PRI_REG_STARVE.wr_enable_i_3 \n (.I0(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [3]),\n .I1(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [2]),\n .I2(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [1]),\n .I3(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [0]),\n .O(\\RD_PRI_REG_STARVE.wr_enable_i_3_n_0 ));\n FDRE \\RD_PRI_REG_STARVE.wr_enable_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\RD_PRI_REG_STARVE.wr_enable_i_1_n_0 ),\n .Q(wr_enable),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h6)) \n \\RD_PRI_REG_STARVE.wr_starve_cnt[0]_i_1 \n (.I0(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [0]),\n .I1(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ),\n .O(p_0_in__1[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1188\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\RD_PRI_REG_STARVE.wr_starve_cnt[1]_i_1 \n (.I0(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [0]),\n .I1(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ),\n .I2(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [1]),\n .O(p_0_in__1[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1185\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\RD_PRI_REG_STARVE.wr_starve_cnt[2]_i_1 \n (.I0(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ),\n .I1(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [0]),\n .I2(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [1]),\n .I3(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [2]),\n .O(p_0_in__1[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1185\" *) \n LUT5 #(\n .INIT(32'h7FFF8000)) \n \\RD_PRI_REG_STARVE.wr_starve_cnt[3]_i_1 \n (.I0(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [1]),\n .I1(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [0]),\n .I2(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ),\n .I3(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [2]),\n .I4(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [3]),\n .O(p_0_in__1[3]));\n LUT6 #(\n .INIT(64'h7FFFFFFF80000000)) \n \\RD_PRI_REG_STARVE.wr_starve_cnt[4]_i_1 \n (.I0(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [2]),\n .I1(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ),\n .I2(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [0]),\n .I3(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [1]),\n .I4(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [3]),\n .I5(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [4]),\n .O(p_0_in__1[4]));\n LUT2 #(\n .INIT(4'h6)) \n \\RD_PRI_REG_STARVE.wr_starve_cnt[5]_i_1 \n (.I0(\\RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_4_n_0 ),\n .I1(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [5]),\n .O(p_0_in__1[5]));\n (* SOFT_HLUTNM = \"soft_lutpair1190\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\RD_PRI_REG_STARVE.wr_starve_cnt[6]_i_1 \n (.I0(\\RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_4_n_0 ),\n .I1(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [5]),\n .I2(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [6]),\n .O(p_0_in__1[6]));\n LUT4 #(\n .INIT(16'hEEEF)) \n \\RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_1 \n (.I0(areset_d1),\n .I1(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg__0 ),\n .I2(wr_cmd_en_d1),\n .I3(wr_cmd_en),\n .O(wr_starve_cnt0));\n LUT3 #(\n .INIT(8'h80)) \n \\RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_2 \n (.I0(app_rdy),\n .I1(\\RD_PRI_REG_STARVE.wr_enable_i_2_n_0 ),\n .I2(wr_cmd_en),\n .O(wr_starve_cnt));\n (* SOFT_HLUTNM = \"soft_lutpair1190\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_3 \n (.I0(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [5]),\n .I1(\\RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_4_n_0 ),\n .I2(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [6]),\n .I3(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [7]),\n .O(p_0_in__1[7]));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_4 \n (.I0(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [4]),\n .I1(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [2]),\n .I2(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ),\n .I3(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [0]),\n .I4(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [1]),\n .I5(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [3]),\n .O(\\RD_PRI_REG_STARVE.wr_starve_cnt[7]_i_4_n_0 ));\n FDRE \\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0] \n (.C(CLK),\n .CE(wr_starve_cnt),\n .D(p_0_in__1[0]),\n .Q(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [0]),\n .R(wr_starve_cnt0));\n FDRE \\RD_PRI_REG_STARVE.wr_starve_cnt_reg[1] \n (.C(CLK),\n .CE(wr_starve_cnt),\n .D(p_0_in__1[1]),\n .Q(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [1]),\n .R(wr_starve_cnt0));\n FDRE \\RD_PRI_REG_STARVE.wr_starve_cnt_reg[2] \n (.C(CLK),\n .CE(wr_starve_cnt),\n .D(p_0_in__1[2]),\n .Q(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [2]),\n .R(wr_starve_cnt0));\n FDRE \\RD_PRI_REG_STARVE.wr_starve_cnt_reg[3] \n (.C(CLK),\n .CE(wr_starve_cnt),\n .D(p_0_in__1[3]),\n .Q(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [3]),\n .R(wr_starve_cnt0));\n FDRE \\RD_PRI_REG_STARVE.wr_starve_cnt_reg[4] \n (.C(CLK),\n .CE(wr_starve_cnt),\n .D(p_0_in__1[4]),\n .Q(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [4]),\n .R(wr_starve_cnt0));\n FDRE \\RD_PRI_REG_STARVE.wr_starve_cnt_reg[5] \n (.C(CLK),\n .CE(wr_starve_cnt),\n .D(p_0_in__1[5]),\n .Q(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [5]),\n .R(wr_starve_cnt0));\n FDRE \\RD_PRI_REG_STARVE.wr_starve_cnt_reg[6] \n (.C(CLK),\n .CE(wr_starve_cnt),\n .D(p_0_in__1[6]),\n .Q(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [6]),\n .R(wr_starve_cnt0));\n FDRE \\RD_PRI_REG_STARVE.wr_starve_cnt_reg[7] \n (.C(CLK),\n .CE(wr_starve_cnt),\n .D(p_0_in__1[7]),\n .Q(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg__0 [7]),\n .R(wr_starve_cnt0));\n LUT4 #(\n .INIT(16'h1000)) \n \\axlen_cnt[7]_i_5 \n (.I0(mc_app_wdf_wren_reg_reg),\n .I1(s_axi_awburst),\n .I2(s_axi_awready),\n .I3(s_axi_awvalid),\n .O(\\axaddr_incr_reg[29] ));\n (* SOFT_HLUTNM = \"soft_lutpair1186\" *) \n LUT4 #(\n .INIT(16'h1000)) \n \\axlen_cnt[7]_i_5__0 \n (.I0(next),\n .I1(s_axi_arburst),\n .I2(axready_reg),\n .I3(s_axi_arvalid),\n .O(\\axaddr_incr_reg[29]_0 ));\n LUT4 #(\n .INIT(16'h4000)) \n \\int_addr[3]_i_3 \n (.I0(mc_app_wdf_wren_reg_reg),\n .I1(s_axi_awburst),\n .I2(s_axi_awready),\n .I3(s_axi_awvalid),\n .O(\\axlen_cnt_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair1186\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\int_addr[3]_i_3__0 \n (.I0(next),\n .I1(s_axi_arburst),\n .I2(axready_reg),\n .I3(s_axi_arvalid),\n .O(\\axlen_cnt_reg[1]_0 ));\n LUT3 #(\n .INIT(8'h40)) \n mc_app_wdf_wren_reg_i_1\n (.I0(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ),\n .I1(app_rdy),\n .I2(wr_cmd_en),\n .O(mc_app_wdf_wren_reg_reg));\n (* SOFT_HLUTNM = \"soft_lutpair1187\" *) \n LUT3 #(\n .INIT(8'h80)) \n r_push_i_1\n (.I0(\\RD_PRI_REG_STARVE.wr_starve_cnt_reg[0]_0 ),\n .I1(app_rdy),\n .I2(rd_cmd_en),\n .O(next));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_axi_mc_cmd_fsm\n (s_axi_arready,\n D,\n \\app_addr_r1_reg[27] ,\n \\axaddr_incr_reg[29] ,\n \\axaddr_reg[29] ,\n \\axlen_cnt_reg[7] ,\n r_rlast_reg,\n \\axburst_reg[1] ,\n in0,\n \\app_addr_r1_reg[6] ,\n S,\n \\axaddr_incr_reg[29]_0 ,\n \\int_addr_reg[3] ,\n \\axlen_cnt_reg[3] ,\n arvalid_int,\n E,\n \\axlen_cnt_reg[0] ,\n DI,\n \\axid_reg[0] ,\n areset_d1,\n CLK,\n Q,\n \\axaddr_incr_reg[6] ,\n \\axaddr_incr_reg[7] ,\n \\axaddr_incr_reg[29]_1 ,\n \\axaddr_incr_reg[9] ,\n \\axaddr_incr_reg[10] ,\n \\axaddr_incr_reg[11] ,\n \\axaddr_incr_reg[12] ,\n \\axaddr_incr_reg[13] ,\n \\axaddr_incr_reg[14] ,\n \\axaddr_incr_reg[15] ,\n \\axaddr_incr_reg[16] ,\n \\axaddr_incr_reg[17] ,\n \\axaddr_incr_reg[18] ,\n \\axaddr_incr_reg[19] ,\n \\axaddr_incr_reg[20] ,\n \\axaddr_incr_reg[21] ,\n \\axaddr_incr_reg[22] ,\n \\axaddr_incr_reg[23] ,\n \\axaddr_incr_reg[24] ,\n \\axaddr_incr_reg[25] ,\n \\axaddr_incr_reg[26] ,\n \\axaddr_incr_reg[27] ,\n \\axaddr_incr_reg[28] ,\n \\axaddr_incr_reg[29]_2 ,\n \\axaddr_incr_reg[5] ,\n axready_reg_0,\n s_axi_arlen,\n \\axlen_reg[7] ,\n next,\n axvalid,\n s_axi_arvalid,\n s_axi_araddr,\n \\axaddr_reg[29]_0 ,\n \\int_addr_reg[3]_0 ,\n \\RD_PRI_REG_STARVE.rnw_i_reg ,\n out,\n axready_reg_1,\n \\axlen_cnt_reg[3]_0 ,\n axburst,\n s_axi_arburst,\n s_axi_arid,\n in);\n output s_axi_arready;\n output [7:0]D;\n output [23:0]\\app_addr_r1_reg[27] ;\n output [22:0]\\axaddr_incr_reg[29] ;\n output [29:0]\\axaddr_reg[29] ;\n output [7:0]\\axlen_cnt_reg[7] ;\n output r_rlast_reg;\n output \\axburst_reg[1] ;\n output [3:0]in0;\n output \\app_addr_r1_reg[6] ;\n output [2:0]S;\n output [29:0]\\axaddr_incr_reg[29]_0 ;\n output [3:0]\\int_addr_reg[3] ;\n output [3:0]\\axlen_cnt_reg[3] ;\n output arvalid_int;\n output [0:0]E;\n output [0:0]\\axlen_cnt_reg[0] ;\n output [0:0]DI;\n output \\axid_reg[0] ;\n input areset_d1;\n input CLK;\n input [7:0]Q;\n input \\axaddr_incr_reg[6] ;\n input \\axaddr_incr_reg[7] ;\n input [29:0]\\axaddr_incr_reg[29]_1 ;\n input \\axaddr_incr_reg[9] ;\n input \\axaddr_incr_reg[10] ;\n input \\axaddr_incr_reg[11] ;\n input \\axaddr_incr_reg[12] ;\n input \\axaddr_incr_reg[13] ;\n input \\axaddr_incr_reg[14] ;\n input \\axaddr_incr_reg[15] ;\n input \\axaddr_incr_reg[16] ;\n input \\axaddr_incr_reg[17] ;\n input \\axaddr_incr_reg[18] ;\n input \\axaddr_incr_reg[19] ;\n input \\axaddr_incr_reg[20] ;\n input \\axaddr_incr_reg[21] ;\n input \\axaddr_incr_reg[22] ;\n input \\axaddr_incr_reg[23] ;\n input \\axaddr_incr_reg[24] ;\n input \\axaddr_incr_reg[25] ;\n input \\axaddr_incr_reg[26] ;\n input \\axaddr_incr_reg[27] ;\n input \\axaddr_incr_reg[28] ;\n input \\axaddr_incr_reg[29]_2 ;\n input \\axaddr_incr_reg[5] ;\n input axready_reg_0;\n input [7:0]s_axi_arlen;\n input [7:0]\\axlen_reg[7] ;\n input next;\n input axvalid;\n input s_axi_arvalid;\n input [29:0]s_axi_araddr;\n input [29:0]\\axaddr_reg[29]_0 ;\n input [3:0]\\int_addr_reg[3]_0 ;\n input \\RD_PRI_REG_STARVE.rnw_i_reg ;\n input [29:0]out;\n input axready_reg_1;\n input [3:0]\\axlen_cnt_reg[3]_0 ;\n input [0:0]axburst;\n input [0:0]s_axi_arburst;\n input [0:0]s_axi_arid;\n input [0:0]in;\n\n wire CLK;\n wire [7:0]D;\n wire [0:0]DI;\n wire [0:0]E;\n wire [7:0]Q;\n wire \\RD_PRI_REG_STARVE.rnw_i_reg ;\n wire [2:0]S;\n wire \\app_addr_r1[27]_i_3_n_0 ;\n wire \\app_addr_r1[27]_i_4_n_0 ;\n wire \\app_addr_r1[6]_i_6_n_0 ;\n wire [23:0]\\app_addr_r1_reg[27] ;\n wire \\app_addr_r1_reg[6] ;\n wire areset_d1;\n wire arvalid_int;\n wire \\axaddr_incr_reg[10] ;\n wire \\axaddr_incr_reg[11] ;\n wire \\axaddr_incr_reg[12] ;\n wire \\axaddr_incr_reg[13] ;\n wire \\axaddr_incr_reg[14] ;\n wire \\axaddr_incr_reg[15] ;\n wire \\axaddr_incr_reg[16] ;\n wire \\axaddr_incr_reg[17] ;\n wire \\axaddr_incr_reg[18] ;\n wire \\axaddr_incr_reg[19] ;\n wire \\axaddr_incr_reg[20] ;\n wire \\axaddr_incr_reg[21] ;\n wire \\axaddr_incr_reg[22] ;\n wire \\axaddr_incr_reg[23] ;\n wire \\axaddr_incr_reg[24] ;\n wire \\axaddr_incr_reg[25] ;\n wire \\axaddr_incr_reg[26] ;\n wire \\axaddr_incr_reg[27] ;\n wire \\axaddr_incr_reg[28] ;\n wire [22:0]\\axaddr_incr_reg[29] ;\n wire [29:0]\\axaddr_incr_reg[29]_0 ;\n wire [29:0]\\axaddr_incr_reg[29]_1 ;\n wire \\axaddr_incr_reg[29]_2 ;\n wire \\axaddr_incr_reg[5] ;\n wire \\axaddr_incr_reg[6] ;\n wire \\axaddr_incr_reg[7] ;\n wire \\axaddr_incr_reg[9] ;\n wire [29:0]\\axaddr_reg[29] ;\n wire [29:0]\\axaddr_reg[29]_0 ;\n wire [0:0]axburst;\n wire \\axburst_reg[1] ;\n wire [3:2]\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/axlen_cnt_t__3 ;\n wire [8:5]\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr ;\n wire \\axi_mc_cmd_translator_0/incr_axhandshake ;\n wire \\axi_mc_cmd_translator_0/wrap_axhandshake ;\n wire [7:5]axi_mc_incr_cmd_byte_addr__0;\n wire \\axid_reg[0] ;\n wire \\axlen_cnt[2]_i_2__1_n_0 ;\n wire \\axlen_cnt[2]_i_2__2_n_0 ;\n wire \\axlen_cnt[3]_i_2__1_n_0 ;\n wire \\axlen_cnt[3]_i_2__2_n_0 ;\n wire \\axlen_cnt[4]_i_2__0_n_0 ;\n wire \\axlen_cnt[4]_i_3__0_n_0 ;\n wire \\axlen_cnt[5]_i_2__0_n_0 ;\n wire \\axlen_cnt[5]_i_3__0_n_0 ;\n wire \\axlen_cnt[7]_i_3__0_n_0 ;\n wire \\axlen_cnt[7]_i_4__0_n_0 ;\n wire [0:0]\\axlen_cnt_reg[0] ;\n wire [3:0]\\axlen_cnt_reg[3] ;\n wire [3:0]\\axlen_cnt_reg[3]_0 ;\n wire [7:0]\\axlen_cnt_reg[7] ;\n wire [7:0]\\axlen_reg[7] ;\n wire axready_i_1__0_n_0;\n wire axready_reg_0;\n wire axready_reg_1;\n wire axvalid;\n wire [0:0]in;\n wire [3:0]in0;\n wire \\int_addr[3]_i_5__0_n_0 ;\n wire [3:0]\\int_addr_reg[3] ;\n wire [3:0]\\int_addr_reg[3]_0 ;\n wire next;\n wire [29:0]out;\n wire r_rlast_i_4_n_0;\n wire r_rlast_i_5_n_0;\n wire r_rlast_i_6_n_0;\n wire r_rlast_reg;\n wire [29:0]s_axi_araddr;\n wire [0:0]s_axi_arburst;\n wire [0:0]s_axi_arid;\n wire [7:0]s_axi_arlen;\n wire s_axi_arready;\n wire s_axi_arvalid;\n\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[10]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [12]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [12]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[12] ),\n .O(\\app_addr_r1_reg[27] [6]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[11]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [13]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [13]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[13] ),\n .O(\\app_addr_r1_reg[27] [7]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[12]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [14]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [14]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[14] ),\n .O(\\app_addr_r1_reg[27] [8]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[13]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [15]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [15]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[15] ),\n .O(\\app_addr_r1_reg[27] [9]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[14]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [16]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [16]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[16] ),\n .O(\\app_addr_r1_reg[27] [10]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[15]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [17]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [17]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[17] ),\n .O(\\app_addr_r1_reg[27] [11]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[16]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [18]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [18]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[18] ),\n .O(\\app_addr_r1_reg[27] [12]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[17]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [19]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [19]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[19] ),\n .O(\\app_addr_r1_reg[27] [13]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[18]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [20]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [20]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[20] ),\n .O(\\app_addr_r1_reg[27] [14]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[19]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [21]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [21]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[21] ),\n .O(\\app_addr_r1_reg[27] [15]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[20]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [22]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [22]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[22] ),\n .O(\\app_addr_r1_reg[27] [16]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[21]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [23]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [23]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[23] ),\n .O(\\app_addr_r1_reg[27] [17]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[22]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [24]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [24]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[24] ),\n .O(\\app_addr_r1_reg[27] [18]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[23]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [25]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [25]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[25] ),\n .O(\\app_addr_r1_reg[27] [19]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[24]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [26]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [26]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[26] ),\n .O(\\app_addr_r1_reg[27] [20]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[25]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [27]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [27]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[27] ),\n .O(\\app_addr_r1_reg[27] [21]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[26]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [28]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [28]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[28] ),\n .O(\\app_addr_r1_reg[27] [22]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[27]_i_2 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [29]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [29]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[29]_2 ),\n .O(\\app_addr_r1_reg[27] [23]));\n (* SOFT_HLUTNM = \"soft_lutpair1157\" *) \n LUT4 #(\n .INIT(16'h02A2)) \n \\app_addr_r1[27]_i_3 \n (.I0(\\RD_PRI_REG_STARVE.rnw_i_reg ),\n .I1(axburst),\n .I2(s_axi_arready),\n .I3(s_axi_arburst),\n .O(\\app_addr_r1[27]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1157\" *) \n LUT4 #(\n .INIT(16'hE200)) \n \\app_addr_r1[27]_i_4 \n (.I0(axburst),\n .I1(s_axi_arready),\n .I2(s_axi_arburst),\n .I3(\\RD_PRI_REG_STARVE.rnw_i_reg ),\n .O(\\app_addr_r1[27]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFF888)) \n \\app_addr_r1[3]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(axi_mc_incr_cmd_byte_addr__0[5]),\n .I2(\\app_addr_r1[27]_i_4_n_0 ),\n .I3(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]),\n .I4(\\axaddr_incr_reg[5] ),\n .O(\\app_addr_r1_reg[27] [0]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_addr_r1[3]_i_2 \n (.I0(s_axi_araddr[5]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [5]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [5]),\n .O(axi_mc_incr_cmd_byte_addr__0[5]));\n LUT5 #(\n .INIT(32'hFFFFF888)) \n \\app_addr_r1[4]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(axi_mc_incr_cmd_byte_addr__0[6]),\n .I2(\\app_addr_r1[27]_i_4_n_0 ),\n .I3(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [6]),\n .I4(\\axaddr_incr_reg[6] ),\n .O(\\app_addr_r1_reg[27] [1]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_addr_r1[4]_i_2 \n (.I0(s_axi_araddr[6]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [6]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [6]),\n .O(axi_mc_incr_cmd_byte_addr__0[6]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_addr_r1[4]_i_3 \n (.I0(s_axi_araddr[6]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [6]),\n .I3(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I4(\\int_addr_reg[3]_0 [1]),\n .O(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [6]));\n LUT5 #(\n .INIT(32'hFFFFF888)) \n \\app_addr_r1[5]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(axi_mc_incr_cmd_byte_addr__0[7]),\n .I2(\\app_addr_r1[27]_i_4_n_0 ),\n .I3(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [7]),\n .I4(\\axaddr_incr_reg[7] ),\n .O(\\app_addr_r1_reg[27] [2]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_addr_r1[5]_i_2 \n (.I0(s_axi_araddr[7]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [7]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [7]),\n .O(axi_mc_incr_cmd_byte_addr__0[7]));\n LUT6 #(\n .INIT(64'hCACFCAC000000000)) \n \\app_addr_r1[6]_i_2 \n (.I0(\\int_addr_reg[3]_0 [3]),\n .I1(\\axaddr_reg[29] [8]),\n .I2(\\app_addr_r1[6]_i_6_n_0 ),\n .I3(\\axburst_reg[1] ),\n .I4(\\axaddr_incr_reg[29]_1 [8]),\n .I5(\\RD_PRI_REG_STARVE.rnw_i_reg ),\n .O(\\app_addr_r1_reg[6] ));\n (* SOFT_HLUTNM = \"soft_lutpair1160\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\app_addr_r1[6]_i_6 \n (.I0(s_axi_arvalid),\n .I1(s_axi_arready),\n .O(\\app_addr_r1[6]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[7]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [9]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [9]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[9] ),\n .O(\\app_addr_r1_reg[27] [3]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[8]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [10]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [10]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[10] ),\n .O(\\app_addr_r1_reg[27] [4]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF08A808)) \n \\app_addr_r1[9]_i_1 \n (.I0(\\app_addr_r1[27]_i_3_n_0 ),\n .I1(\\axaddr_incr_reg[29]_1 [11]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_reg[29] [11]),\n .I4(\\app_addr_r1[27]_i_4_n_0 ),\n .I5(\\axaddr_incr_reg[11] ),\n .O(\\app_addr_r1_reg[27] [5]));\n (* SOFT_HLUTNM = \"soft_lutpair1125\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[0]_i_1__0 \n (.I0(s_axi_araddr[0]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [0]),\n .O(\\axaddr_reg[29] [0]));\n (* SOFT_HLUTNM = \"soft_lutpair1137\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[10]_i_1__0 \n (.I0(s_axi_araddr[10]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [10]),\n .O(\\axaddr_reg[29] [10]));\n (* SOFT_HLUTNM = \"soft_lutpair1138\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[11]_i_1__0 \n (.I0(s_axi_araddr[11]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [11]),\n .O(\\axaddr_reg[29] [11]));\n (* SOFT_HLUTNM = \"soft_lutpair1139\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[12]_i_1__0 \n (.I0(s_axi_araddr[12]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [12]),\n .O(\\axaddr_reg[29] [12]));\n (* SOFT_HLUTNM = \"soft_lutpair1145\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[13]_i_1__0 \n (.I0(s_axi_araddr[13]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [13]),\n .O(\\axaddr_reg[29] [13]));\n (* SOFT_HLUTNM = \"soft_lutpair1140\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[14]_i_1__0 \n (.I0(s_axi_araddr[14]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [14]),\n .O(\\axaddr_reg[29] [14]));\n (* SOFT_HLUTNM = \"soft_lutpair1142\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[15]_i_1__0 \n (.I0(s_axi_araddr[15]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [15]),\n .O(\\axaddr_reg[29] [15]));\n (* SOFT_HLUTNM = \"soft_lutpair1143\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[16]_i_1__0 \n (.I0(s_axi_araddr[16]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [16]),\n .O(\\axaddr_reg[29] [16]));\n (* SOFT_HLUTNM = \"soft_lutpair1149\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[17]_i_1__0 \n (.I0(s_axi_araddr[17]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [17]),\n .O(\\axaddr_reg[29] [17]));\n (* SOFT_HLUTNM = \"soft_lutpair1144\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[18]_i_1__0 \n (.I0(s_axi_araddr[18]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [18]),\n .O(\\axaddr_reg[29] [18]));\n (* SOFT_HLUTNM = \"soft_lutpair1146\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[19]_i_1__0 \n (.I0(s_axi_araddr[19]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [19]),\n .O(\\axaddr_reg[29] [19]));\n (* SOFT_HLUTNM = \"soft_lutpair1126\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[1]_i_1__0 \n (.I0(s_axi_araddr[1]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [1]),\n .O(\\axaddr_reg[29] [1]));\n (* SOFT_HLUTNM = \"soft_lutpair1147\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[20]_i_1__0 \n (.I0(s_axi_araddr[20]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [20]),\n .O(\\axaddr_reg[29] [20]));\n (* SOFT_HLUTNM = \"soft_lutpair1153\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[21]_i_1__0 \n (.I0(s_axi_araddr[21]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [21]),\n .O(\\axaddr_reg[29] [21]));\n (* SOFT_HLUTNM = \"soft_lutpair1148\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[22]_i_1__0 \n (.I0(s_axi_araddr[22]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [22]),\n .O(\\axaddr_reg[29] [22]));\n (* SOFT_HLUTNM = \"soft_lutpair1150\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[23]_i_1__0 \n (.I0(s_axi_araddr[23]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [23]),\n .O(\\axaddr_reg[29] [23]));\n (* SOFT_HLUTNM = \"soft_lutpair1151\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[24]_i_1__0 \n (.I0(s_axi_araddr[24]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [24]),\n .O(\\axaddr_reg[29] [24]));\n (* SOFT_HLUTNM = \"soft_lutpair1133\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[25]_i_1__0 \n (.I0(s_axi_araddr[25]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [25]),\n .O(\\axaddr_reg[29] [25]));\n (* SOFT_HLUTNM = \"soft_lutpair1152\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[26]_i_1__0 \n (.I0(s_axi_araddr[26]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [26]),\n .O(\\axaddr_reg[29] [26]));\n (* SOFT_HLUTNM = \"soft_lutpair1154\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[27]_i_1__0 \n (.I0(s_axi_araddr[27]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [27]),\n .O(\\axaddr_reg[29] [27]));\n (* SOFT_HLUTNM = \"soft_lutpair1155\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[28]_i_1__0 \n (.I0(s_axi_araddr[28]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [28]),\n .O(\\axaddr_reg[29] [28]));\n (* SOFT_HLUTNM = \"soft_lutpair1156\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[29]_i_1__0 \n (.I0(s_axi_araddr[29]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [29]),\n .O(\\axaddr_reg[29] [29]));\n (* SOFT_HLUTNM = \"soft_lutpair1127\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[2]_i_1__0 \n (.I0(s_axi_araddr[2]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [2]),\n .O(\\axaddr_reg[29] [2]));\n (* SOFT_HLUTNM = \"soft_lutpair1128\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[3]_i_1__0 \n (.I0(s_axi_araddr[3]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [3]),\n .O(\\axaddr_reg[29] [3]));\n (* SOFT_HLUTNM = \"soft_lutpair1131\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[4]_i_1__0 \n (.I0(s_axi_araddr[4]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [4]),\n .O(\\axaddr_reg[29] [4]));\n (* SOFT_HLUTNM = \"soft_lutpair1130\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[5]_i_1__0 \n (.I0(s_axi_araddr[5]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [5]),\n .O(\\axaddr_reg[29] [5]));\n (* SOFT_HLUTNM = \"soft_lutpair1132\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[6]_i_1__0 \n (.I0(s_axi_araddr[6]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [6]),\n .O(\\axaddr_reg[29] [6]));\n (* SOFT_HLUTNM = \"soft_lutpair1135\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[7]_i_1__0 \n (.I0(s_axi_araddr[7]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [7]),\n .O(\\axaddr_reg[29] [7]));\n (* SOFT_HLUTNM = \"soft_lutpair1136\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[8]_i_1__0 \n (.I0(s_axi_araddr[8]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [8]),\n .O(\\axaddr_reg[29] [8]));\n (* SOFT_HLUTNM = \"soft_lutpair1141\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[9]_i_1__0 \n (.I0(s_axi_araddr[9]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [9]),\n .O(\\axaddr_reg[29] [9]));\n (* SOFT_HLUTNM = \"soft_lutpair1125\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[0]_i_1__0 \n (.I0(s_axi_araddr[0]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [0]),\n .I3(axready_reg_0),\n .I4(out[0]),\n .O(\\axaddr_incr_reg[29]_0 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair1137\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[10]_i_1__0 \n (.I0(s_axi_araddr[10]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [10]),\n .I3(axready_reg_0),\n .I4(out[10]),\n .O(\\axaddr_incr_reg[29]_0 [10]));\n (* SOFT_HLUTNM = \"soft_lutpair1138\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[11]_i_1__0 \n (.I0(s_axi_araddr[11]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [11]),\n .I3(axready_reg_0),\n .I4(out[11]),\n .O(\\axaddr_incr_reg[29]_0 [11]));\n (* SOFT_HLUTNM = \"soft_lutpair1139\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[12]_i_1__0 \n (.I0(s_axi_araddr[12]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [12]),\n .I3(axready_reg_0),\n .I4(out[12]),\n .O(\\axaddr_incr_reg[29]_0 [12]));\n (* SOFT_HLUTNM = \"soft_lutpair1145\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[13]_i_1__0 \n (.I0(s_axi_araddr[13]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [13]),\n .I3(axready_reg_0),\n .I4(out[13]),\n .O(\\axaddr_incr_reg[29]_0 [13]));\n (* SOFT_HLUTNM = \"soft_lutpair1140\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[14]_i_1__0 \n (.I0(s_axi_araddr[14]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [14]),\n .I3(axready_reg_0),\n .I4(out[14]),\n .O(\\axaddr_incr_reg[29]_0 [14]));\n (* SOFT_HLUTNM = \"soft_lutpair1142\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[15]_i_1__0 \n (.I0(s_axi_araddr[15]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [15]),\n .I3(axready_reg_0),\n .I4(out[15]),\n .O(\\axaddr_incr_reg[29]_0 [15]));\n (* SOFT_HLUTNM = \"soft_lutpair1143\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[16]_i_1__0 \n (.I0(s_axi_araddr[16]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [16]),\n .I3(axready_reg_0),\n .I4(out[16]),\n .O(\\axaddr_incr_reg[29]_0 [16]));\n (* SOFT_HLUTNM = \"soft_lutpair1149\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[17]_i_1__0 \n (.I0(s_axi_araddr[17]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [17]),\n .I3(axready_reg_0),\n .I4(out[17]),\n .O(\\axaddr_incr_reg[29]_0 [17]));\n (* SOFT_HLUTNM = \"soft_lutpair1144\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[18]_i_1__0 \n (.I0(s_axi_araddr[18]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [18]),\n .I3(axready_reg_0),\n .I4(out[18]),\n .O(\\axaddr_incr_reg[29]_0 [18]));\n (* SOFT_HLUTNM = \"soft_lutpair1146\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[19]_i_1__0 \n (.I0(s_axi_araddr[19]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [19]),\n .I3(axready_reg_0),\n .I4(out[19]),\n .O(\\axaddr_incr_reg[29]_0 [19]));\n (* SOFT_HLUTNM = \"soft_lutpair1126\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[1]_i_1__0 \n (.I0(s_axi_araddr[1]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [1]),\n .I3(axready_reg_0),\n .I4(out[1]),\n .O(\\axaddr_incr_reg[29]_0 [1]));\n (* SOFT_HLUTNM = \"soft_lutpair1147\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[20]_i_1__0 \n (.I0(s_axi_araddr[20]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [20]),\n .I3(axready_reg_0),\n .I4(out[20]),\n .O(\\axaddr_incr_reg[29]_0 [20]));\n (* SOFT_HLUTNM = \"soft_lutpair1153\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[21]_i_1__0 \n (.I0(s_axi_araddr[21]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [21]),\n .I3(axready_reg_0),\n .I4(out[21]),\n .O(\\axaddr_incr_reg[29]_0 [21]));\n (* SOFT_HLUTNM = \"soft_lutpair1148\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[22]_i_1__0 \n (.I0(s_axi_araddr[22]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [22]),\n .I3(axready_reg_0),\n .I4(out[22]),\n .O(\\axaddr_incr_reg[29]_0 [22]));\n (* SOFT_HLUTNM = \"soft_lutpair1150\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[23]_i_1__0 \n (.I0(s_axi_araddr[23]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [23]),\n .I3(axready_reg_0),\n .I4(out[23]),\n .O(\\axaddr_incr_reg[29]_0 [23]));\n (* SOFT_HLUTNM = \"soft_lutpair1151\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[24]_i_1__0 \n (.I0(s_axi_araddr[24]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [24]),\n .I3(axready_reg_0),\n .I4(out[24]),\n .O(\\axaddr_incr_reg[29]_0 [24]));\n (* SOFT_HLUTNM = \"soft_lutpair1133\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[25]_i_1__0 \n (.I0(s_axi_araddr[25]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [25]),\n .I3(axready_reg_0),\n .I4(out[25]),\n .O(\\axaddr_incr_reg[29]_0 [25]));\n (* SOFT_HLUTNM = \"soft_lutpair1152\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[26]_i_1__0 \n (.I0(s_axi_araddr[26]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [26]),\n .I3(axready_reg_0),\n .I4(out[26]),\n .O(\\axaddr_incr_reg[29]_0 [26]));\n (* SOFT_HLUTNM = \"soft_lutpair1154\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[27]_i_1__0 \n (.I0(s_axi_araddr[27]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [27]),\n .I3(axready_reg_0),\n .I4(out[27]),\n .O(\\axaddr_incr_reg[29]_0 [27]));\n (* SOFT_HLUTNM = \"soft_lutpair1155\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[28]_i_1__0 \n (.I0(s_axi_araddr[28]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [28]),\n .I3(axready_reg_0),\n .I4(out[28]),\n .O(\\axaddr_incr_reg[29]_0 [28]));\n (* SOFT_HLUTNM = \"soft_lutpair1156\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[29]_i_1__0 \n (.I0(s_axi_araddr[29]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [29]),\n .I3(axready_reg_0),\n .I4(out[29]),\n .O(\\axaddr_incr_reg[29]_0 [29]));\n (* SOFT_HLUTNM = \"soft_lutpair1127\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[2]_i_1__0 \n (.I0(s_axi_araddr[2]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [2]),\n .I3(axready_reg_0),\n .I4(out[2]),\n .O(\\axaddr_incr_reg[29]_0 [2]));\n (* SOFT_HLUTNM = \"soft_lutpair1128\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[3]_i_1__0 \n (.I0(s_axi_araddr[3]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [3]),\n .I3(axready_reg_0),\n .I4(out[3]),\n .O(\\axaddr_incr_reg[29]_0 [3]));\n (* SOFT_HLUTNM = \"soft_lutpair1131\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[4]_i_1__0 \n (.I0(s_axi_araddr[4]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [4]),\n .I3(axready_reg_0),\n .I4(out[4]),\n .O(\\axaddr_incr_reg[29]_0 [4]));\n (* SOFT_HLUTNM = \"soft_lutpair1130\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[5]_i_1__0 \n (.I0(s_axi_araddr[5]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [5]),\n .I3(axready_reg_0),\n .I4(out[5]),\n .O(\\axaddr_incr_reg[29]_0 [5]));\n (* SOFT_HLUTNM = \"soft_lutpair1132\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[6]_i_1__0 \n (.I0(s_axi_araddr[6]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [6]),\n .I3(axready_reg_0),\n .I4(out[6]),\n .O(\\axaddr_incr_reg[29]_0 [6]));\n (* SOFT_HLUTNM = \"soft_lutpair1135\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[7]_i_1__0 \n (.I0(s_axi_araddr[7]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [7]),\n .I3(axready_reg_0),\n .I4(out[7]),\n .O(\\axaddr_incr_reg[29]_0 [7]));\n (* SOFT_HLUTNM = \"soft_lutpair1136\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[8]_i_1__0 \n (.I0(s_axi_araddr[8]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [8]),\n .I3(axready_reg_0),\n .I4(out[8]),\n .O(\\axaddr_incr_reg[29]_0 [8]));\n (* SOFT_HLUTNM = \"soft_lutpair1141\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[9]_i_1__0 \n (.I0(s_axi_araddr[9]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [9]),\n .I3(axready_reg_0),\n .I4(out[9]),\n .O(\\axaddr_incr_reg[29]_0 [9]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_inferred_i_1__0\n (.I0(s_axi_araddr[3]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [3]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [3]),\n .O(in0[3]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_inferred_i_2__0\n (.I0(s_axi_araddr[2]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [2]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [2]),\n .O(in0[2]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_inferred_i_3__0\n (.I0(s_axi_araddr[1]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [1]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [1]),\n .O(in0[1]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_inferred_i_4__0\n (.I0(s_axi_araddr[0]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [0]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [0]),\n .O(in0[0]));\n LUT3 #(\n .INIT(8'h08)) \n axaddr_incr_p_inferred_i_5__0\n (.I0(s_axi_arvalid),\n .I1(s_axi_arready),\n .I2(s_axi_arburst),\n .O(\\axi_mc_cmd_translator_0/incr_axhandshake ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__0_i_1__0\n (.I0(s_axi_araddr[11]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [11]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [11]),\n .O(\\axaddr_incr_reg[29] [4]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__0_i_2__0\n (.I0(s_axi_araddr[10]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [10]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [10]),\n .O(\\axaddr_incr_reg[29] [3]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__0_i_3__0\n (.I0(s_axi_araddr[9]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [9]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [9]),\n .O(\\axaddr_incr_reg[29] [2]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__0_i_4\n (.I0(s_axi_araddr[8]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [8]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [8]),\n .O(\\axaddr_incr_reg[29] [1]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__1_i_1__0\n (.I0(s_axi_araddr[15]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [15]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [15]),\n .O(\\axaddr_incr_reg[29] [8]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__1_i_2__0\n (.I0(s_axi_araddr[14]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [14]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [14]),\n .O(\\axaddr_incr_reg[29] [7]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__1_i_3__0\n (.I0(s_axi_araddr[13]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [13]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [13]),\n .O(\\axaddr_incr_reg[29] [6]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__1_i_4__0\n (.I0(s_axi_araddr[12]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [12]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [12]),\n .O(\\axaddr_incr_reg[29] [5]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__2_i_1__0\n (.I0(s_axi_araddr[19]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [19]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [19]),\n .O(\\axaddr_incr_reg[29] [12]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__2_i_2__0\n (.I0(s_axi_araddr[18]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [18]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [18]),\n .O(\\axaddr_incr_reg[29] [11]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__2_i_3__0\n (.I0(s_axi_araddr[17]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [17]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [17]),\n .O(\\axaddr_incr_reg[29] [10]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__2_i_4__0\n (.I0(s_axi_araddr[16]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [16]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [16]),\n .O(\\axaddr_incr_reg[29] [9]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__3_i_1__0\n (.I0(s_axi_araddr[23]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [23]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [23]),\n .O(\\axaddr_incr_reg[29] [16]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__3_i_2__0\n (.I0(s_axi_araddr[22]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [22]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [22]),\n .O(\\axaddr_incr_reg[29] [15]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__3_i_3__0\n (.I0(s_axi_araddr[21]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [21]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [21]),\n .O(\\axaddr_incr_reg[29] [14]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__3_i_4__0\n (.I0(s_axi_araddr[20]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [20]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [20]),\n .O(\\axaddr_incr_reg[29] [13]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__4_i_1__0\n (.I0(s_axi_araddr[27]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [27]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [27]),\n .O(\\axaddr_incr_reg[29] [20]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__4_i_2__0\n (.I0(s_axi_araddr[26]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [26]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [26]),\n .O(\\axaddr_incr_reg[29] [19]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__4_i_3__0\n (.I0(s_axi_araddr[25]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [25]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [25]),\n .O(\\axaddr_incr_reg[29] [18]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__4_i_4__0\n (.I0(s_axi_araddr[24]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [24]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [24]),\n .O(\\axaddr_incr_reg[29] [17]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__5_i_1__0\n (.I0(s_axi_araddr[29]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [29]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [29]),\n .O(\\axaddr_incr_reg[29] [22]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__5_i_2__0\n (.I0(s_axi_araddr[28]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [28]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [28]),\n .O(\\axaddr_incr_reg[29] [21]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry_i_1__0\n (.I0(s_axi_araddr[5]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [5]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [5]),\n .O(DI));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry_i_2__0\n (.I0(s_axi_araddr[7]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [7]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [7]),\n .O(S[2]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry_i_3__0\n (.I0(s_axi_araddr[6]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [6]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [6]),\n .O(S[1]));\n LUT5 #(\n .INIT(32'h111DDD1D)) \n axaddr_incr_p_reg0_carry_i_4__0\n (.I0(\\axaddr_incr_reg[29]_1 [5]),\n .I1(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I2(\\axaddr_reg[29]_0 [5]),\n .I3(s_axi_arready),\n .I4(s_axi_araddr[5]),\n .O(S[0]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry_i_5__0\n (.I0(s_axi_araddr[4]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [4]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [4]),\n .O(\\axaddr_incr_reg[29] [0]));\n (* SOFT_HLUTNM = \"soft_lutpair1159\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axburst[1]_i_1__0 \n (.I0(s_axi_arburst),\n .I1(s_axi_arready),\n .I2(axburst),\n .O(\\axburst_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair1160\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axid[0]_i_1__0 \n (.I0(s_axi_arid),\n .I1(s_axi_arready),\n .I2(in),\n .O(\\axid_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair1158\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axlen[0]_i_1__0 \n (.I0(s_axi_arlen[0]),\n .I1(s_axi_arready),\n .I2(\\axlen_reg[7] [0]),\n .O(D[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1159\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axlen[1]_i_1__0 \n (.I0(s_axi_arlen[1]),\n .I1(s_axi_arready),\n .I2(\\axlen_reg[7] [1]),\n .O(D[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1134\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axlen[2]_i_1__0 \n (.I0(s_axi_arlen[2]),\n .I1(s_axi_arready),\n .I2(\\axlen_reg[7] [2]),\n .O(D[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1122\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axlen[3]_i_1__0 \n (.I0(s_axi_arlen[3]),\n .I1(s_axi_arready),\n .I2(\\axlen_reg[7] [3]),\n .O(D[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1119\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axlen[4]_i_1__0 \n (.I0(s_axi_arlen[4]),\n .I1(s_axi_arready),\n .I2(\\axlen_reg[7] [4]),\n .O(D[4]));\n (* SOFT_HLUTNM = \"soft_lutpair1121\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axlen[5]_i_1__0 \n (.I0(s_axi_arlen[5]),\n .I1(s_axi_arready),\n .I2(\\axlen_reg[7] [5]),\n .O(D[5]));\n (* SOFT_HLUTNM = \"soft_lutpair1124\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axlen[6]_i_1__0 \n (.I0(s_axi_arlen[6]),\n .I1(s_axi_arready),\n .I2(\\axlen_reg[7] [6]),\n .O(D[6]));\n (* SOFT_HLUTNM = \"soft_lutpair1123\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axlen[7]_i_1__0 \n (.I0(s_axi_arlen[7]),\n .I1(s_axi_arready),\n .I2(\\axlen_reg[7] [7]),\n .O(D[7]));\n LUT6 #(\n .INIT(64'hABABAB515151AB51)) \n \\axlen_cnt[0]_i_1__1 \n (.I0(axready_reg_0),\n .I1(Q[0]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axlen_reg[7] [0]),\n .I4(s_axi_arready),\n .I5(s_axi_arlen[0]),\n .O(\\axlen_cnt_reg[7] [0]));\n LUT6 #(\n .INIT(64'hABABAB515151AB51)) \n \\axlen_cnt[0]_i_1__2 \n (.I0(axready_reg_1),\n .I1(\\axlen_cnt_reg[3]_0 [0]),\n .I2(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I3(\\axlen_reg[7] [0]),\n .I4(s_axi_arready),\n .I5(s_axi_arlen[0]),\n .O(\\axlen_cnt_reg[3] [0]));\n LUT6 #(\n .INIT(64'hFFFFE4B100004E1B)) \n \\axlen_cnt[1]_i_1__1 \n (.I0(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I1(Q[1]),\n .I2(D[0]),\n .I3(Q[0]),\n .I4(axready_reg_0),\n .I5(D[1]),\n .O(\\axlen_cnt_reg[7] [1]));\n LUT6 #(\n .INIT(64'hFFFFE4B100004E1B)) \n \\axlen_cnt[1]_i_1__2 \n (.I0(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I1(\\axlen_cnt_reg[3]_0 [1]),\n .I2(D[0]),\n .I3(\\axlen_cnt_reg[3]_0 [0]),\n .I4(axready_reg_1),\n .I5(D[1]),\n .O(\\axlen_cnt_reg[3] [1]));\n LUT5 #(\n .INIT(32'hFFE1004B)) \n \\axlen_cnt[2]_i_1__1 \n (.I0(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I1(Q[2]),\n .I2(\\axlen_cnt[2]_i_2__1_n_0 ),\n .I3(axready_reg_0),\n .I4(D[2]),\n .O(\\axlen_cnt_reg[7] [2]));\n LUT5 #(\n .INIT(32'hFFE1004B)) \n \\axlen_cnt[2]_i_1__2 \n (.I0(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I1(\\axlen_cnt_reg[3]_0 [2]),\n .I2(\\axlen_cnt[2]_i_2__2_n_0 ),\n .I3(axready_reg_1),\n .I4(D[2]),\n .O(\\axlen_cnt_reg[3] [2]));\n LUT5 #(\n .INIT(32'hFFFACCFA)) \n \\axlen_cnt[2]_i_2__1 \n (.I0(Q[0]),\n .I1(D[0]),\n .I2(Q[1]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(D[1]),\n .O(\\axlen_cnt[2]_i_2__1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFACCFA)) \n \\axlen_cnt[2]_i_2__2 \n (.I0(\\axlen_cnt_reg[3]_0 [0]),\n .I1(D[0]),\n .I2(\\axlen_cnt_reg[3]_0 [1]),\n .I3(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I4(D[1]),\n .O(\\axlen_cnt[2]_i_2__2_n_0 ));\n LUT5 #(\n .INIT(32'hFFE1004B)) \n \\axlen_cnt[3]_i_1__1 \n (.I0(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I1(Q[3]),\n .I2(\\axlen_cnt[3]_i_2__1_n_0 ),\n .I3(axready_reg_0),\n .I4(D[3]),\n .O(\\axlen_cnt_reg[7] [3]));\n LUT5 #(\n .INIT(32'hFFE1004B)) \n \\axlen_cnt[3]_i_1__2 \n (.I0(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I1(\\axlen_cnt_reg[3]_0 [3]),\n .I2(\\axlen_cnt[3]_i_2__2_n_0 ),\n .I3(axready_reg_1),\n .I4(D[3]),\n .O(\\axlen_cnt_reg[3] [3]));\n LUT6 #(\n .INIT(64'hFEFEFEAEAEAEFEAE)) \n \\axlen_cnt[3]_i_2__1 \n (.I0(\\axlen_cnt[2]_i_2__1_n_0 ),\n .I1(Q[2]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axlen_reg[7] [2]),\n .I4(s_axi_arready),\n .I5(s_axi_arlen[2]),\n .O(\\axlen_cnt[3]_i_2__1_n_0 ));\n LUT6 #(\n .INIT(64'hFEFEFEAEAEAEFEAE)) \n \\axlen_cnt[3]_i_2__2 \n (.I0(\\axlen_cnt[2]_i_2__2_n_0 ),\n .I1(\\axlen_cnt_reg[3]_0 [2]),\n .I2(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I3(\\axlen_reg[7] [2]),\n .I4(s_axi_arready),\n .I5(s_axi_arlen[2]),\n .O(\\axlen_cnt[3]_i_2__2_n_0 ));\n LUT6 #(\n .INIT(64'hF606F6F6F6060606)) \n \\axlen_cnt[4]_i_1__0 \n (.I0(\\axlen_cnt[4]_i_2__0_n_0 ),\n .I1(\\axlen_cnt[4]_i_3__0_n_0 ),\n .I2(axready_reg_0),\n .I3(s_axi_arlen[4]),\n .I4(s_axi_arready),\n .I5(\\axlen_reg[7] [4]),\n .O(\\axlen_cnt_reg[7] [4]));\n LUT6 #(\n .INIT(64'h0101015151510151)) \n \\axlen_cnt[4]_i_2__0 \n (.I0(\\axlen_cnt[3]_i_2__1_n_0 ),\n .I1(Q[3]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axlen_reg[7] [3]),\n .I4(s_axi_arready),\n .I5(s_axi_arlen[3]),\n .O(\\axlen_cnt[4]_i_2__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1119\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axlen_cnt[4]_i_3__0 \n (.I0(s_axi_arlen[4]),\n .I1(s_axi_arready),\n .I2(\\axlen_reg[7] [4]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(Q[4]),\n .O(\\axlen_cnt[4]_i_3__0_n_0 ));\n LUT6 #(\n .INIT(64'hF909F9F9F9090909)) \n \\axlen_cnt[5]_i_1__0 \n (.I0(\\axlen_cnt[5]_i_2__0_n_0 ),\n .I1(\\axlen_cnt[5]_i_3__0_n_0 ),\n .I2(axready_reg_0),\n .I3(s_axi_arlen[5]),\n .I4(s_axi_arready),\n .I5(\\axlen_reg[7] [5]),\n .O(\\axlen_cnt_reg[7] [5]));\n (* SOFT_HLUTNM = \"soft_lutpair1121\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axlen_cnt[5]_i_2__0 \n (.I0(s_axi_arlen[5]),\n .I1(s_axi_arready),\n .I2(\\axlen_reg[7] [5]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(Q[5]),\n .O(\\axlen_cnt[5]_i_2__0_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFCFFFCAA)) \n \\axlen_cnt[5]_i_3__0 \n (.I0(Q[4]),\n .I1(D[4]),\n .I2(D[3]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(Q[3]),\n .I5(\\axlen_cnt[3]_i_2__1_n_0 ),\n .O(\\axlen_cnt[5]_i_3__0_n_0 ));\n LUT6 #(\n .INIT(64'hF909F9F9F9090909)) \n \\axlen_cnt[6]_i_1__0 \n (.I0(\\axlen_cnt[7]_i_3__0_n_0 ),\n .I1(\\axlen_cnt[7]_i_4__0_n_0 ),\n .I2(axready_reg_0),\n .I3(s_axi_arlen[6]),\n .I4(s_axi_arready),\n .I5(\\axlen_reg[7] [6]),\n .O(\\axlen_cnt_reg[7] [6]));\n (* SOFT_HLUTNM = \"soft_lutpair1129\" *) \n LUT5 #(\n .INIT(32'h0E000ECC)) \n \\axlen_cnt[7]_i_1__0 \n (.I0(s_axi_arvalid),\n .I1(next),\n .I2(s_axi_arburst),\n .I3(s_axi_arready),\n .I4(axburst),\n .O(E));\n LUT6 #(\n .INIT(64'hFFFFEEE10000444B)) \n \\axlen_cnt[7]_i_2__0 \n (.I0(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I1(Q[7]),\n .I2(\\axlen_cnt[7]_i_3__0_n_0 ),\n .I3(\\axlen_cnt[7]_i_4__0_n_0 ),\n .I4(axready_reg_0),\n .I5(D[7]),\n .O(\\axlen_cnt_reg[7] [7]));\n (* SOFT_HLUTNM = \"soft_lutpair1124\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axlen_cnt[7]_i_3__0 \n (.I0(s_axi_arlen[6]),\n .I1(s_axi_arready),\n .I2(\\axlen_reg[7] [6]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(Q[6]),\n .O(\\axlen_cnt[7]_i_3__0_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFEAE)) \n \\axlen_cnt[7]_i_4__0 \n (.I0(\\axlen_cnt[3]_i_2__1_n_0 ),\n .I1(Q[3]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(D[3]),\n .I4(\\axlen_cnt[4]_i_3__0_n_0 ),\n .I5(\\axlen_cnt[5]_i_2__0_n_0 ),\n .O(\\axlen_cnt[7]_i_4__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1120\" *) \n LUT5 #(\n .INIT(32'h888FFF8F)) \n axready_i_1__0\n (.I0(next),\n .I1(r_rlast_reg),\n .I2(axvalid),\n .I3(s_axi_arready),\n .I4(s_axi_arvalid),\n .O(axready_i_1__0_n_0));\n FDRE axready_reg\n (.C(CLK),\n .CE(1'b1),\n .D(axready_i_1__0_n_0),\n .Q(s_axi_arready),\n .R(areset_d1));\n (* SOFT_HLUTNM = \"soft_lutpair1120\" *) \n LUT3 #(\n .INIT(8'hB8)) \n axvalid_i_1__0\n (.I0(s_axi_arvalid),\n .I1(s_axi_arready),\n .I2(axvalid),\n .O(arvalid_int));\n LUT6 #(\n .INIT(64'hF606F6F6F6060606)) \n \\int_addr[0]_i_1__0 \n (.I0(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]),\n .I1(D[0]),\n .I2(axready_reg_1),\n .I3(s_axi_araddr[5]),\n .I4(s_axi_arready),\n .I5(\\axaddr_reg[29]_0 [5]),\n .O(\\int_addr_reg[3] [0]));\n LUT6 #(\n .INIT(64'hBFBFBFEA40401540)) \n \\int_addr[1]_i_1__0 \n (.I0(axready_reg_1),\n .I1(D[1]),\n .I2(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]),\n .I3(\\int_addr_reg[3]_0 [1]),\n .I4(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I5(\\axaddr_reg[29] [6]),\n .O(\\int_addr_reg[3] [1]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\int_addr[1]_i_2__0 \n (.I0(s_axi_araddr[5]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [5]),\n .I3(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I4(\\int_addr_reg[3]_0 [0]),\n .O(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]));\n LUT6 #(\n .INIT(64'hBFBFBFEA40401540)) \n \\int_addr[2]_i_1__0 \n (.I0(axready_reg_1),\n .I1(D[2]),\n .I2(\\int_addr[3]_i_5__0_n_0 ),\n .I3(\\int_addr_reg[3]_0 [2]),\n .I4(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I5(\\axaddr_reg[29] [7]),\n .O(\\int_addr_reg[3] [2]));\n (* SOFT_HLUTNM = \"soft_lutpair1158\" *) \n LUT3 #(\n .INIT(8'h80)) \n \\int_addr[2]_i_2__0 \n (.I0(s_axi_arvalid),\n .I1(s_axi_arready),\n .I2(s_axi_arburst),\n .O(\\axi_mc_cmd_translator_0/wrap_axhandshake ));\n (* SOFT_HLUTNM = \"soft_lutpair1129\" *) \n LUT5 #(\n .INIT(32'hCFC08080)) \n \\int_addr[3]_i_1__0 \n (.I0(s_axi_arvalid),\n .I1(s_axi_arburst),\n .I2(s_axi_arready),\n .I3(axburst),\n .I4(next),\n .O(\\axlen_cnt_reg[0] ));\n LUT6 #(\n .INIT(64'h8BBBBBBBB8888888)) \n \\int_addr[3]_i_2__0 \n (.I0(\\axaddr_reg[29] [8]),\n .I1(axready_reg_1),\n .I2(D[3]),\n .I3(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [7]),\n .I4(\\int_addr[3]_i_5__0_n_0 ),\n .I5(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [8]),\n .O(\\int_addr_reg[3] [3]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\int_addr[3]_i_4__0 \n (.I0(s_axi_araddr[7]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [7]),\n .I3(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I4(\\int_addr_reg[3]_0 [2]),\n .O(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [7]));\n LUT6 #(\n .INIT(64'hEEE222E200000000)) \n \\int_addr[3]_i_5__0 \n (.I0(\\int_addr_reg[3]_0 [1]),\n .I1(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I2(\\axaddr_reg[29]_0 [6]),\n .I3(s_axi_arready),\n .I4(s_axi_araddr[6]),\n .I5(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]),\n .O(\\int_addr[3]_i_5__0_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\int_addr[3]_i_6__0 \n (.I0(s_axi_araddr[8]),\n .I1(s_axi_arready),\n .I2(\\axaddr_reg[29]_0 [8]),\n .I3(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I4(\\int_addr_reg[3]_0 [3]),\n .O(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [8]));\n LUT6 #(\n .INIT(64'h0010FFFF00100010)) \n r_rlast_i_1\n (.I0(\\axlen_cnt[2]_i_2__2_n_0 ),\n .I1(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/axlen_cnt_t__3 [2]),\n .I2(\\axburst_reg[1] ),\n .I3(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/axlen_cnt_t__3 [3]),\n .I4(\\axlen_cnt[3]_i_2__1_n_0 ),\n .I5(r_rlast_i_4_n_0),\n .O(r_rlast_reg));\n (* SOFT_HLUTNM = \"soft_lutpair1134\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n r_rlast_i_2\n (.I0(s_axi_arlen[2]),\n .I1(s_axi_arready),\n .I2(\\axlen_reg[7] [2]),\n .I3(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I4(\\axlen_cnt_reg[3]_0 [2]),\n .O(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/axlen_cnt_t__3 [2]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n r_rlast_i_3\n (.I0(s_axi_arlen[3]),\n .I1(s_axi_arready),\n .I2(\\axlen_reg[7] [3]),\n .I3(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I4(\\axlen_cnt_reg[3]_0 [3]),\n .O(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/axlen_cnt_t__3 [3]));\n LUT6 #(\n .INIT(64'h0000000000000001)) \n r_rlast_i_4\n (.I0(r_rlast_i_5_n_0),\n .I1(\\axlen_cnt[7]_i_3__0_n_0 ),\n .I2(\\axlen_cnt[4]_i_3__0_n_0 ),\n .I3(\\axlen_cnt[5]_i_2__0_n_0 ),\n .I4(\\axburst_reg[1] ),\n .I5(r_rlast_i_6_n_0),\n .O(r_rlast_i_4_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1123\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n r_rlast_i_5\n (.I0(s_axi_arlen[7]),\n .I1(s_axi_arready),\n .I2(\\axlen_reg[7] [7]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(Q[7]),\n .O(r_rlast_i_5_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1122\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n r_rlast_i_6\n (.I0(s_axi_arlen[3]),\n .I1(s_axi_arready),\n .I2(\\axlen_reg[7] [3]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(Q[3]),\n .O(r_rlast_i_6_n_0));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_axi_mc_cmd_translator\n (out,\n Q,\n \\app_addr_r1_reg[27] ,\n \\int_addr_reg[3] ,\n \\axlen_cnt_reg[3] ,\n in0,\n axready_reg,\n S,\n axready_reg_0,\n areset_d1,\n E,\n D,\n CLK,\n axready_reg_1,\n axready_reg_2,\n axready_reg_3,\n \\axlen_cnt_reg[3]_0 );\n output [29:0]out;\n output [7:0]Q;\n output [29:0]\\app_addr_r1_reg[27] ;\n output [3:0]\\int_addr_reg[3] ;\n output [3:0]\\axlen_cnt_reg[3] ;\n input [3:0]in0;\n input [24:0]axready_reg;\n input [0:0]S;\n input [0:0]axready_reg_0;\n input areset_d1;\n input [0:0]E;\n input [7:0]D;\n input CLK;\n input [29:0]axready_reg_1;\n input [0:0]axready_reg_2;\n input [3:0]axready_reg_3;\n input [3:0]\\axlen_cnt_reg[3]_0 ;\n\n wire CLK;\n wire [7:0]D;\n wire [0:0]E;\n wire [7:0]Q;\n wire [0:0]S;\n wire [29:0]\\app_addr_r1_reg[27] ;\n wire areset_d1;\n wire [3:0]\\axlen_cnt_reg[3] ;\n wire [3:0]\\axlen_cnt_reg[3]_0 ;\n wire [24:0]axready_reg;\n wire [0:0]axready_reg_0;\n wire [29:0]axready_reg_1;\n wire [0:0]axready_reg_2;\n wire [3:0]axready_reg_3;\n wire [3:0]in0;\n wire [3:0]\\int_addr_reg[3] ;\n wire [29:0]out;\n\n ddr3_if_mig_7series_v4_0_axi_mc_incr_cmd axi_mc_incr_cmd_0\n (.CLK(CLK),\n .D(D),\n .E(E),\n .Q(Q),\n .S(S),\n .\\app_addr_r1_reg[27] (\\app_addr_r1_reg[27] ),\n .areset_d1(areset_d1),\n .axready_reg(axready_reg),\n .axready_reg_0(axready_reg_0),\n .axready_reg_1(axready_reg_1),\n .in0(in0),\n .out(out));\n ddr3_if_mig_7series_v4_0_axi_mc_wrap_cmd axi_mc_wrap_cmd_0\n (.CLK(CLK),\n .areset_d1(areset_d1),\n .\\axlen_cnt_reg[3]_0 (\\axlen_cnt_reg[3] ),\n .\\axlen_cnt_reg[3]_1 (\\axlen_cnt_reg[3]_0 ),\n .axready_reg(axready_reg_2),\n .axready_reg_0(axready_reg_3),\n .\\int_addr_reg[3]_0 (\\int_addr_reg[3] ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_axi_mc_cmd_translator\" *) \nmodule ddr3_if_mig_7series_v4_0_axi_mc_cmd_translator__parameterized0\n (out,\n Q,\n \\app_addr_r1_reg[27] ,\n \\app_addr_r1_reg[6] ,\n \\axlen_cnt_reg[3] ,\n in0,\n DI,\n S,\n axready_reg,\n areset_d1,\n E,\n D,\n CLK,\n axready_reg_0,\n axready_reg_1,\n axready_reg_2,\n \\axlen_cnt_reg[3]_0 );\n output [29:0]out;\n output [7:0]Q;\n output [29:0]\\app_addr_r1_reg[27] ;\n output [3:0]\\app_addr_r1_reg[6] ;\n output [3:0]\\axlen_cnt_reg[3] ;\n input [3:0]in0;\n input [0:0]DI;\n input [3:0]S;\n input [21:0]axready_reg;\n input areset_d1;\n input [0:0]E;\n input [7:0]D;\n input CLK;\n input [29:0]axready_reg_0;\n input [0:0]axready_reg_1;\n input [3:0]axready_reg_2;\n input [3:0]\\axlen_cnt_reg[3]_0 ;\n\n wire CLK;\n wire [7:0]D;\n wire [0:0]DI;\n wire [0:0]E;\n wire [7:0]Q;\n wire [3:0]S;\n wire [29:0]\\app_addr_r1_reg[27] ;\n wire [3:0]\\app_addr_r1_reg[6] ;\n wire areset_d1;\n wire [3:0]\\axlen_cnt_reg[3] ;\n wire [3:0]\\axlen_cnt_reg[3]_0 ;\n wire [21:0]axready_reg;\n wire [29:0]axready_reg_0;\n wire [0:0]axready_reg_1;\n wire [3:0]axready_reg_2;\n wire [3:0]in0;\n wire [29:0]out;\n\n ddr3_if_mig_7series_v4_0_axi_mc_incr_cmd__parameterized0 axi_mc_incr_cmd_0\n (.CLK(CLK),\n .D(D),\n .DI(DI),\n .E(E),\n .Q(Q),\n .S(S),\n .\\app_addr_r1_reg[27] (\\app_addr_r1_reg[27] ),\n .areset_d1(areset_d1),\n .axready_reg(axready_reg),\n .axready_reg_0(axready_reg_0),\n .in0(in0),\n .out(out));\n ddr3_if_mig_7series_v4_0_axi_mc_wrap_cmd__parameterized0 axi_mc_wrap_cmd_0\n (.CLK(CLK),\n .\\app_addr_r1_reg[6] (\\app_addr_r1_reg[6] ),\n .areset_d1(areset_d1),\n .\\axlen_cnt_reg[3]_0 (\\axlen_cnt_reg[3] ),\n .\\axlen_cnt_reg[3]_1 (\\axlen_cnt_reg[3]_0 ),\n .axready_reg(axready_reg_1),\n .axready_reg_0(axready_reg_2));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_axi_mc_fifo\n (bid_i,\n app_en_ns1,\n wr_cmd_en,\n E,\n bhandshake,\n bvalid_i_reg,\n b_push,\n b_awid,\n CLK,\n app_rdy,\n \\RD_PRI_REG_STARVE.rnw_i_reg ,\n rd_cmd_en,\n reset_reg,\n app_en_r1,\n bvalid_i_reg_0,\n s_axi_bready,\n wvalid_int,\n awvalid_int,\n app_wdf_rdy,\n areset_d1);\n output bid_i;\n output app_en_ns1;\n output wr_cmd_en;\n output [0:0]E;\n output bhandshake;\n output bvalid_i_reg;\n input b_push;\n input b_awid;\n input CLK;\n input app_rdy;\n input \\RD_PRI_REG_STARVE.rnw_i_reg ;\n input rd_cmd_en;\n input reset_reg;\n input app_en_r1;\n input bvalid_i_reg_0;\n input s_axi_bready;\n input wvalid_int;\n input awvalid_int;\n input app_wdf_rdy;\n input areset_d1;\n\n wire CLK;\n wire [0:0]E;\n wire \\RD_PRI_REG_STARVE.rnw_i_reg ;\n wire app_en_ns1;\n wire app_en_r1;\n wire app_rdy;\n wire app_wdf_rdy;\n wire areset_d1;\n wire awvalid_int;\n wire b_awid;\n wire b_push;\n wire bhandshake;\n wire bid_i;\n wire bvalid_i_reg;\n wire bvalid_i_reg_0;\n wire \\cnt_read[0]_i_1__1_n_0 ;\n wire \\cnt_read[1]_i_1_n_0 ;\n wire \\cnt_read[2]_i_1__0_n_0 ;\n wire \\cnt_read[3]_i_1__0_n_0 ;\n wire \\cnt_read[3]_i_2_n_0 ;\n wire \\cnt_read[3]_i_3_n_0 ;\n wire [2:0]cnt_read_reg__0;\n wire [3:3]cnt_read_reg__0__0;\n wire rd_cmd_en;\n wire reset_reg;\n wire s_axi_bready;\n wire wr_cmd_en;\n wire wvalid_int;\n\n LUT6 #(\n .INIT(64'h8080808080008080)) \n \\RD_PRI_REG_STARVE.rnw_i_i_2 \n (.I0(wvalid_int),\n .I1(awvalid_int),\n .I2(app_wdf_rdy),\n .I3(\\cnt_read[3]_i_3_n_0 ),\n .I4(cnt_read_reg__0[0]),\n .I5(cnt_read_reg__0__0),\n .O(wr_cmd_en));\n LUT4 #(\n .INIT(16'hA808)) \n \\app_addr_r1[27]_i_1 \n (.I0(app_rdy),\n .I1(wr_cmd_en),\n .I2(\\RD_PRI_REG_STARVE.rnw_i_reg ),\n .I3(rd_cmd_en),\n .O(E));\n LUT6 #(\n .INIT(64'h0000FD5D0000A808)) \n app_en_r1_i_1\n (.I0(app_rdy),\n .I1(wr_cmd_en),\n .I2(\\RD_PRI_REG_STARVE.rnw_i_reg ),\n .I3(rd_cmd_en),\n .I4(reset_reg),\n .I5(app_en_r1),\n .O(app_en_ns1));\n LUT2 #(\n .INIT(4'hB)) \n \\bid_t[0]_i_1 \n (.I0(s_axi_bready),\n .I1(bvalid_i_reg_0),\n .O(bhandshake));\n LUT6 #(\n .INIT(64'h7FFFFFFF7FFF7FFF)) \n bvalid_i_i_1\n (.I0(cnt_read_reg__0__0),\n .I1(cnt_read_reg__0[1]),\n .I2(cnt_read_reg__0[2]),\n .I3(cnt_read_reg__0[0]),\n .I4(s_axi_bready),\n .I5(bvalid_i_reg_0),\n .O(bvalid_i_reg));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_read[0]_i_1__1 \n (.I0(cnt_read_reg__0[0]),\n .O(\\cnt_read[0]_i_1__1_n_0 ));\n LUT6 #(\n .INIT(64'h52D2D2D22D2D2D2D)) \n \\cnt_read[1]_i_1 \n (.I0(b_push),\n .I1(bhandshake),\n .I2(cnt_read_reg__0[0]),\n .I3(cnt_read_reg__0[2]),\n .I4(cnt_read_reg__0__0),\n .I5(cnt_read_reg__0[1]),\n .O(\\cnt_read[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h4FFFFF30300000CF)) \n \\cnt_read[2]_i_1__0 \n (.I0(cnt_read_reg__0__0),\n .I1(bhandshake),\n .I2(b_push),\n .I3(cnt_read_reg__0[0]),\n .I4(cnt_read_reg__0[1]),\n .I5(cnt_read_reg__0[2]),\n .O(\\cnt_read[2]_i_1__0_n_0 ));\n LUT6 #(\n .INIT(64'h5959AA5959595959)) \n \\cnt_read[3]_i_1__0 \n (.I0(b_push),\n .I1(bvalid_i_reg_0),\n .I2(s_axi_bready),\n .I3(cnt_read_reg__0[0]),\n .I4(\\cnt_read[3]_i_3_n_0 ),\n .I5(cnt_read_reg__0__0),\n .O(\\cnt_read[3]_i_1__0_n_0 ));\n LUT6 #(\n .INIT(64'h5FFF2000FFBA0045)) \n \\cnt_read[3]_i_2 \n (.I0(cnt_read_reg__0[1]),\n .I1(bhandshake),\n .I2(b_push),\n .I3(cnt_read_reg__0[0]),\n .I4(cnt_read_reg__0__0),\n .I5(cnt_read_reg__0[2]),\n .O(\\cnt_read[3]_i_2_n_0 ));\n LUT2 #(\n .INIT(4'h7)) \n \\cnt_read[3]_i_3 \n (.I0(cnt_read_reg__0[1]),\n .I1(cnt_read_reg__0[2]),\n .O(\\cnt_read[3]_i_3_n_0 ));\n FDSE \\cnt_read_reg[0] \n (.C(CLK),\n .CE(\\cnt_read[3]_i_1__0_n_0 ),\n .D(\\cnt_read[0]_i_1__1_n_0 ),\n .Q(cnt_read_reg__0[0]),\n .S(areset_d1));\n FDSE \\cnt_read_reg[1] \n (.C(CLK),\n .CE(\\cnt_read[3]_i_1__0_n_0 ),\n .D(\\cnt_read[1]_i_1_n_0 ),\n .Q(cnt_read_reg__0[1]),\n .S(areset_d1));\n FDSE \\cnt_read_reg[2] \n (.C(CLK),\n .CE(\\cnt_read[3]_i_1__0_n_0 ),\n .D(\\cnt_read[2]_i_1__0_n_0 ),\n .Q(cnt_read_reg__0[2]),\n .S(areset_d1));\n FDSE \\cnt_read_reg[3] \n (.C(CLK),\n .CE(\\cnt_read[3]_i_1__0_n_0 ),\n .D(\\cnt_read[3]_i_2_n_0 ),\n .Q(cnt_read_reg__0__0),\n .S(areset_d1));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_b_channel_0/bid_fifo_0/memory_reg[7] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_b_channel_0/bid_fifo_0/memory_reg[7][0]_srl8 \" *) \n SRL16E #(\n .INIT(16'h0000)) \n \\memory_reg[7][0]_srl8 \n (.A0(cnt_read_reg__0[0]),\n .A1(cnt_read_reg__0[1]),\n .A2(cnt_read_reg__0[2]),\n .A3(1'b0),\n .CE(b_push),\n .CLK(CLK),\n .D(b_awid),\n .Q(bid_i));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_axi_mc_fifo\" *) \nmodule ddr3_if_mig_7series_v4_0_axi_mc_fifo__parameterized0\n (rd_cmd_en,\n E,\n s_axi_rvalid,\n p_0_in,\n \\FSM_sequential_state_reg[1] ,\n \\FSM_sequential_state_reg[0] ,\n \\s_axi_rresp[1] ,\n s_axi_arvalid,\n s_axi_arready,\n axvalid,\n \\cnt_read_reg[5]_0 ,\n app_rdy,\n \\trans_buf_out_r_reg[0] ,\n app_rd_data_valid,\n s_axi_rready,\n out,\n tr_empty,\n in0,\n Q,\n CLK,\n areset_d1);\n output rd_cmd_en;\n output [0:0]E;\n output s_axi_rvalid;\n output p_0_in;\n output \\FSM_sequential_state_reg[1] ;\n output \\FSM_sequential_state_reg[0] ;\n output [256:0]\\s_axi_rresp[1] ;\n input s_axi_arvalid;\n input s_axi_arready;\n input axvalid;\n input \\cnt_read_reg[5]_0 ;\n input app_rdy;\n input \\trans_buf_out_r_reg[0] ;\n input app_rd_data_valid;\n input s_axi_rready;\n input [1:0]out;\n input tr_empty;\n input [1:0]in0;\n input [255:0]Q;\n input CLK;\n input areset_d1;\n\n wire CLK;\n wire [0:0]E;\n wire \\FSM_sequential_state_reg[0] ;\n wire \\FSM_sequential_state_reg[1] ;\n wire [255:0]Q;\n wire app_rd_data_valid;\n wire app_rdy;\n wire areset_d1;\n wire axvalid;\n wire \\cnt_read[0]_i_1_n_0 ;\n wire \\cnt_read[0]_rep_i_1_n_0 ;\n wire \\cnt_read[1]_i_1__0_n_0 ;\n wire \\cnt_read[1]_rep_i_1_n_0 ;\n wire \\cnt_read[2]_i_1__1_n_0 ;\n wire \\cnt_read[2]_rep_i_1_n_0 ;\n wire \\cnt_read[3]_i_1__1_n_0 ;\n wire \\cnt_read[3]_rep_i_1_n_0 ;\n wire \\cnt_read[4]_i_1__0_n_0 ;\n wire \\cnt_read[4]_rep_i_1_n_0 ;\n wire \\cnt_read[5]_i_1_n_0 ;\n wire \\cnt_read[5]_i_2__0_n_0 ;\n wire \\cnt_read[5]_i_3_n_0 ;\n wire \\cnt_read_reg[0]_rep_n_0 ;\n wire \\cnt_read_reg[1]_rep_n_0 ;\n wire \\cnt_read_reg[2]_rep_n_0 ;\n wire \\cnt_read_reg[3]_rep_n_0 ;\n wire \\cnt_read_reg[4]_rep_n_0 ;\n wire \\cnt_read_reg[5]_0 ;\n wire [5:5]cnt_read_reg__0;\n wire [4:0]cnt_read_reg__1;\n wire [1:0]in0;\n wire [1:0]out;\n wire p_0_in;\n wire r_push_i_4_n_0;\n wire rd_cmd_en;\n wire rvalid04_in;\n wire s_axi_arready;\n wire s_axi_arvalid;\n wire s_axi_rready;\n wire [256:0]\\s_axi_rresp[1] ;\n wire s_axi_rvalid;\n wire tr_empty;\n wire \\trans_buf_out_r_reg[0] ;\n wire \\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][100]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][101]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][102]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][103]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][104]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][105]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][106]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][107]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][108]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][109]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][110]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][111]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][112]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][113]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][114]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][115]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][116]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][117]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][118]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][119]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][120]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][121]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][122]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][123]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][124]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][125]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][126]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][127]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][128]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][129]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][130]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][131]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][132]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][133]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][134]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][135]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][136]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][137]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][138]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][139]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][140]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][141]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][142]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][143]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][144]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][145]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][146]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][147]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][148]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][149]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][150]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][151]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][152]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][153]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][154]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][155]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][156]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][157]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][158]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][159]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][160]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][161]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][162]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][163]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][164]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][165]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][166]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][167]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][168]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][169]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][170]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][171]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][172]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][173]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][174]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][175]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][176]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][177]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][178]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][179]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][180]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][181]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][182]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][183]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][184]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][185]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][186]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][187]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][188]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][189]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][190]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][191]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][192]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][193]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][194]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][195]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][196]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][197]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][198]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][199]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][200]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][201]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][202]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][203]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][204]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][205]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][206]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][207]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][208]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][209]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][210]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][211]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][212]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][213]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][214]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][215]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][216]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][217]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][218]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][219]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][220]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][221]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][222]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][223]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][224]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][225]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][226]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][227]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][228]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][229]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][230]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][231]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][232]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][233]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][234]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][235]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][236]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][237]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][238]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][239]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][240]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][241]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][242]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][243]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][244]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][245]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][246]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][247]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][248]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][249]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][250]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][251]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][252]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][253]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][254]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][255]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][256]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][34]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][35]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][36]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][37]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][38]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][39]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][40]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][41]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][42]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][43]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][44]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][45]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][46]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][47]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][48]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][49]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][50]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][51]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][52]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][53]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][54]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][55]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][56]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][57]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][58]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][59]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][60]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][61]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][62]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][63]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][64]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][65]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][66]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][67]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][68]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][69]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][70]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][71]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][72]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][73]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][74]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][75]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][76]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][77]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][78]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][79]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][80]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][81]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][82]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][83]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][84]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][85]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][86]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][87]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][88]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][89]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][90]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][91]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][92]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][93]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][94]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][95]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][96]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][97]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][98]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][99]_srl32_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ;\n\n LUT5 #(\n .INIT(32'hF7FD4045)) \n \\FSM_sequential_state[0]_i_1 \n (.I0(out[0]),\n .I1(p_0_in),\n .I2(out[1]),\n .I3(tr_empty),\n .I4(in0[0]),\n .O(\\FSM_sequential_state_reg[0] ));\n LUT5 #(\n .INIT(32'hB7BA0002)) \n \\FSM_sequential_state[1]_i_1 \n (.I0(out[0]),\n .I1(p_0_in),\n .I2(out[1]),\n .I3(tr_empty),\n .I4(in0[1]),\n .O(\\FSM_sequential_state_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair1194\" *) \n LUT3 #(\n .INIT(8'hC8)) \n \\FSM_sequential_state[1]_i_2 \n (.I0(\\trans_buf_out_r_reg[0] ),\n .I1(rvalid04_in),\n .I2(s_axi_rready),\n .O(p_0_in));\n LUT2 #(\n .INIT(4'h8)) \n \\RD_PRI_REG_STARVE.rd_starve_cnt[8]_i_2 \n (.I0(rd_cmd_en),\n .I1(app_rdy),\n .O(E));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_read[0]_i_1 \n (.I0(cnt_read_reg__1[0]),\n .O(\\cnt_read[0]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_read[0]_rep_i_1 \n (.I0(cnt_read_reg__1[0]),\n .O(\\cnt_read[0]_rep_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAAA6666655599999)) \n \\cnt_read[1]_i_1__0 \n (.I0(cnt_read_reg__1[0]),\n .I1(app_rd_data_valid),\n .I2(s_axi_rready),\n .I3(\\trans_buf_out_r_reg[0] ),\n .I4(rvalid04_in),\n .I5(cnt_read_reg__1[1]),\n .O(\\cnt_read[1]_i_1__0_n_0 ));\n LUT6 #(\n .INIT(64'hAAA6666655599999)) \n \\cnt_read[1]_rep_i_1 \n (.I0(cnt_read_reg__1[0]),\n .I1(app_rd_data_valid),\n .I2(s_axi_rready),\n .I3(\\trans_buf_out_r_reg[0] ),\n .I4(rvalid04_in),\n .I5(cnt_read_reg__1[1]),\n .O(\\cnt_read[1]_rep_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1193\" *) \n LUT3 #(\n .INIT(8'h69)) \n \\cnt_read[2]_i_1__1 \n (.I0(\\cnt_read[5]_i_3_n_0 ),\n .I1(cnt_read_reg__1[2]),\n .I2(cnt_read_reg__1[1]),\n .O(\\cnt_read[2]_i_1__1_n_0 ));\n LUT3 #(\n .INIT(8'h69)) \n \\cnt_read[2]_rep_i_1 \n (.I0(\\cnt_read[5]_i_3_n_0 ),\n .I1(cnt_read_reg__1[2]),\n .I2(cnt_read_reg__1[1]),\n .O(\\cnt_read[2]_rep_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1193\" *) \n LUT4 #(\n .INIT(16'h78E1)) \n \\cnt_read[3]_i_1__1 \n (.I0(cnt_read_reg__1[1]),\n .I1(\\cnt_read[5]_i_3_n_0 ),\n .I2(cnt_read_reg__1[3]),\n .I3(cnt_read_reg__1[2]),\n .O(\\cnt_read[3]_i_1__1_n_0 ));\n LUT4 #(\n .INIT(16'h78E1)) \n \\cnt_read[3]_rep_i_1 \n (.I0(cnt_read_reg__1[1]),\n .I1(\\cnt_read[5]_i_3_n_0 ),\n .I2(cnt_read_reg__1[3]),\n .I3(cnt_read_reg__1[2]),\n .O(\\cnt_read[3]_rep_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1192\" *) \n LUT5 #(\n .INIT(32'h7F80FE01)) \n \\cnt_read[4]_i_1__0 \n (.I0(cnt_read_reg__1[1]),\n .I1(\\cnt_read[5]_i_3_n_0 ),\n .I2(cnt_read_reg__1[2]),\n .I3(cnt_read_reg__1[4]),\n .I4(cnt_read_reg__1[3]),\n .O(\\cnt_read[4]_i_1__0_n_0 ));\n LUT5 #(\n .INIT(32'h7F80FE01)) \n \\cnt_read[4]_rep_i_1 \n (.I0(cnt_read_reg__1[1]),\n .I1(\\cnt_read[5]_i_3_n_0 ),\n .I2(cnt_read_reg__1[2]),\n .I3(cnt_read_reg__1[4]),\n .I4(cnt_read_reg__1[3]),\n .O(\\cnt_read[4]_rep_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h56AA)) \n \\cnt_read[5]_i_1 \n (.I0(app_rd_data_valid),\n .I1(s_axi_rready),\n .I2(\\trans_buf_out_r_reg[0] ),\n .I3(rvalid04_in),\n .O(\\cnt_read[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h7FFF8000FFFE0001)) \n \\cnt_read[5]_i_2__0 \n (.I0(cnt_read_reg__1[1]),\n .I1(\\cnt_read[5]_i_3_n_0 ),\n .I2(cnt_read_reg__1[2]),\n .I3(cnt_read_reg__1[3]),\n .I4(cnt_read_reg__0),\n .I5(cnt_read_reg__1[4]),\n .O(\\cnt_read[5]_i_2__0_n_0 ));\n LUT6 #(\n .INIT(64'h00088888AAAEEEEE)) \n \\cnt_read[5]_i_3 \n (.I0(cnt_read_reg__1[0]),\n .I1(app_rd_data_valid),\n .I2(s_axi_rready),\n .I3(\\trans_buf_out_r_reg[0] ),\n .I4(rvalid04_in),\n .I5(cnt_read_reg__1[1]),\n .O(\\cnt_read[5]_i_3_n_0 ));\n (* ORIG_CELL_NAME = \"cnt_read_reg[0]\" *) \n FDSE \\cnt_read_reg[0] \n (.C(CLK),\n .CE(\\cnt_read[5]_i_1_n_0 ),\n .D(\\cnt_read[0]_i_1_n_0 ),\n .Q(cnt_read_reg__1[0]),\n .S(areset_d1));\n (* ORIG_CELL_NAME = \"cnt_read_reg[0]\" *) \n FDSE \\cnt_read_reg[0]_rep \n (.C(CLK),\n .CE(\\cnt_read[5]_i_1_n_0 ),\n .D(\\cnt_read[0]_rep_i_1_n_0 ),\n .Q(\\cnt_read_reg[0]_rep_n_0 ),\n .S(areset_d1));\n (* ORIG_CELL_NAME = \"cnt_read_reg[1]\" *) \n FDSE \\cnt_read_reg[1] \n (.C(CLK),\n .CE(\\cnt_read[5]_i_1_n_0 ),\n .D(\\cnt_read[1]_i_1__0_n_0 ),\n .Q(cnt_read_reg__1[1]),\n .S(areset_d1));\n (* ORIG_CELL_NAME = \"cnt_read_reg[1]\" *) \n FDSE \\cnt_read_reg[1]_rep \n (.C(CLK),\n .CE(\\cnt_read[5]_i_1_n_0 ),\n .D(\\cnt_read[1]_rep_i_1_n_0 ),\n .Q(\\cnt_read_reg[1]_rep_n_0 ),\n .S(areset_d1));\n (* ORIG_CELL_NAME = \"cnt_read_reg[2]\" *) \n FDSE \\cnt_read_reg[2] \n (.C(CLK),\n .CE(\\cnt_read[5]_i_1_n_0 ),\n .D(\\cnt_read[2]_i_1__1_n_0 ),\n .Q(cnt_read_reg__1[2]),\n .S(areset_d1));\n (* ORIG_CELL_NAME = \"cnt_read_reg[2]\" *) \n FDSE \\cnt_read_reg[2]_rep \n (.C(CLK),\n .CE(\\cnt_read[5]_i_1_n_0 ),\n .D(\\cnt_read[2]_rep_i_1_n_0 ),\n .Q(\\cnt_read_reg[2]_rep_n_0 ),\n .S(areset_d1));\n (* ORIG_CELL_NAME = \"cnt_read_reg[3]\" *) \n FDSE \\cnt_read_reg[3] \n (.C(CLK),\n .CE(\\cnt_read[5]_i_1_n_0 ),\n .D(\\cnt_read[3]_i_1__1_n_0 ),\n .Q(cnt_read_reg__1[3]),\n .S(areset_d1));\n (* ORIG_CELL_NAME = \"cnt_read_reg[3]\" *) \n FDSE \\cnt_read_reg[3]_rep \n (.C(CLK),\n .CE(\\cnt_read[5]_i_1_n_0 ),\n .D(\\cnt_read[3]_rep_i_1_n_0 ),\n .Q(\\cnt_read_reg[3]_rep_n_0 ),\n .S(areset_d1));\n (* ORIG_CELL_NAME = \"cnt_read_reg[4]\" *) \n FDSE \\cnt_read_reg[4] \n (.C(CLK),\n .CE(\\cnt_read[5]_i_1_n_0 ),\n .D(\\cnt_read[4]_i_1__0_n_0 ),\n .Q(cnt_read_reg__1[4]),\n .S(areset_d1));\n (* ORIG_CELL_NAME = \"cnt_read_reg[4]\" *) \n FDSE \\cnt_read_reg[4]_rep \n (.C(CLK),\n .CE(\\cnt_read[5]_i_1_n_0 ),\n .D(\\cnt_read[4]_rep_i_1_n_0 ),\n .Q(\\cnt_read_reg[4]_rep_n_0 ),\n .S(areset_d1));\n FDSE \\cnt_read_reg[5] \n (.C(CLK),\n .CE(\\cnt_read[5]_i_1_n_0 ),\n .D(\\cnt_read[5]_i_2__0_n_0 ),\n .Q(cnt_read_reg__0),\n .S(areset_d1));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][0]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[0]),\n .Q(\\s_axi_rresp[1] [0]),\n .Q31(\\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][100]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][100]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[100]),\n .Q(\\s_axi_rresp[1] [100]),\n .Q31(\\NLW_memory_reg[31][100]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][101]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][101]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[101]),\n .Q(\\s_axi_rresp[1] [101]),\n .Q31(\\NLW_memory_reg[31][101]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][102]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][102]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[102]),\n .Q(\\s_axi_rresp[1] [102]),\n .Q31(\\NLW_memory_reg[31][102]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][103]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][103]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[103]),\n .Q(\\s_axi_rresp[1] [103]),\n .Q31(\\NLW_memory_reg[31][103]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][104]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][104]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[104]),\n .Q(\\s_axi_rresp[1] [104]),\n .Q31(\\NLW_memory_reg[31][104]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][105]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][105]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[105]),\n .Q(\\s_axi_rresp[1] [105]),\n .Q31(\\NLW_memory_reg[31][105]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][106]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][106]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[106]),\n .Q(\\s_axi_rresp[1] [106]),\n .Q31(\\NLW_memory_reg[31][106]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][107]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][107]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[107]),\n .Q(\\s_axi_rresp[1] [107]),\n .Q31(\\NLW_memory_reg[31][107]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][108]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][108]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[108]),\n .Q(\\s_axi_rresp[1] [108]),\n .Q31(\\NLW_memory_reg[31][108]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][109]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][109]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[109]),\n .Q(\\s_axi_rresp[1] [109]),\n .Q31(\\NLW_memory_reg[31][109]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][10]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[10]),\n .Q(\\s_axi_rresp[1] [10]),\n .Q31(\\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][110]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][110]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[110]),\n .Q(\\s_axi_rresp[1] [110]),\n .Q31(\\NLW_memory_reg[31][110]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][111]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][111]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[111]),\n .Q(\\s_axi_rresp[1] [111]),\n .Q31(\\NLW_memory_reg[31][111]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][112]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][112]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[112]),\n .Q(\\s_axi_rresp[1] [112]),\n .Q31(\\NLW_memory_reg[31][112]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][113]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][113]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[113]),\n .Q(\\s_axi_rresp[1] [113]),\n .Q31(\\NLW_memory_reg[31][113]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][114]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][114]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[114]),\n .Q(\\s_axi_rresp[1] [114]),\n .Q31(\\NLW_memory_reg[31][114]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][115]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][115]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[115]),\n .Q(\\s_axi_rresp[1] [115]),\n .Q31(\\NLW_memory_reg[31][115]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][116]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][116]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[116]),\n .Q(\\s_axi_rresp[1] [116]),\n .Q31(\\NLW_memory_reg[31][116]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][117]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][117]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[117]),\n .Q(\\s_axi_rresp[1] [117]),\n .Q31(\\NLW_memory_reg[31][117]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][118]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][118]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[118]),\n .Q(\\s_axi_rresp[1] [118]),\n .Q31(\\NLW_memory_reg[31][118]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][119]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][119]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[119]),\n .Q(\\s_axi_rresp[1] [119]),\n .Q31(\\NLW_memory_reg[31][119]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][11]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[11]),\n .Q(\\s_axi_rresp[1] [11]),\n .Q31(\\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][120]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][120]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[120]),\n .Q(\\s_axi_rresp[1] [120]),\n .Q31(\\NLW_memory_reg[31][120]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][121]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][121]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[121]),\n .Q(\\s_axi_rresp[1] [121]),\n .Q31(\\NLW_memory_reg[31][121]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][122]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][122]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[122]),\n .Q(\\s_axi_rresp[1] [122]),\n .Q31(\\NLW_memory_reg[31][122]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][123]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][123]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[123]),\n .Q(\\s_axi_rresp[1] [123]),\n .Q31(\\NLW_memory_reg[31][123]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][124]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][124]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[124]),\n .Q(\\s_axi_rresp[1] [124]),\n .Q31(\\NLW_memory_reg[31][124]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][125]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][125]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[125]),\n .Q(\\s_axi_rresp[1] [125]),\n .Q31(\\NLW_memory_reg[31][125]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][126]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][126]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[126]),\n .Q(\\s_axi_rresp[1] [126]),\n .Q31(\\NLW_memory_reg[31][126]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][127]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][127]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[127]),\n .Q(\\s_axi_rresp[1] [127]),\n .Q31(\\NLW_memory_reg[31][127]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][128]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][128]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[128]),\n .Q(\\s_axi_rresp[1] [128]),\n .Q31(\\NLW_memory_reg[31][128]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][129]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][129]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[129]),\n .Q(\\s_axi_rresp[1] [129]),\n .Q31(\\NLW_memory_reg[31][129]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][12]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[12]),\n .Q(\\s_axi_rresp[1] [12]),\n .Q31(\\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][130]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][130]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[130]),\n .Q(\\s_axi_rresp[1] [130]),\n .Q31(\\NLW_memory_reg[31][130]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][131]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][131]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[131]),\n .Q(\\s_axi_rresp[1] [131]),\n .Q31(\\NLW_memory_reg[31][131]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][132]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][132]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[132]),\n .Q(\\s_axi_rresp[1] [132]),\n .Q31(\\NLW_memory_reg[31][132]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][133]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][133]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[133]),\n .Q(\\s_axi_rresp[1] [133]),\n .Q31(\\NLW_memory_reg[31][133]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][134]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][134]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[134]),\n .Q(\\s_axi_rresp[1] [134]),\n .Q31(\\NLW_memory_reg[31][134]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][135]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][135]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[135]),\n .Q(\\s_axi_rresp[1] [135]),\n .Q31(\\NLW_memory_reg[31][135]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][136]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][136]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[136]),\n .Q(\\s_axi_rresp[1] [136]),\n .Q31(\\NLW_memory_reg[31][136]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][137]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][137]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[137]),\n .Q(\\s_axi_rresp[1] [137]),\n .Q31(\\NLW_memory_reg[31][137]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][138]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][138]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[138]),\n .Q(\\s_axi_rresp[1] [138]),\n .Q31(\\NLW_memory_reg[31][138]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][139]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][139]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[139]),\n .Q(\\s_axi_rresp[1] [139]),\n .Q31(\\NLW_memory_reg[31][139]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][13]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[13]),\n .Q(\\s_axi_rresp[1] [13]),\n .Q31(\\NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][140]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][140]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[140]),\n .Q(\\s_axi_rresp[1] [140]),\n .Q31(\\NLW_memory_reg[31][140]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][141]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][141]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[141]),\n .Q(\\s_axi_rresp[1] [141]),\n .Q31(\\NLW_memory_reg[31][141]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][142]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][142]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[142]),\n .Q(\\s_axi_rresp[1] [142]),\n .Q31(\\NLW_memory_reg[31][142]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][143]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][143]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[143]),\n .Q(\\s_axi_rresp[1] [143]),\n .Q31(\\NLW_memory_reg[31][143]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][144]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][144]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[144]),\n .Q(\\s_axi_rresp[1] [144]),\n .Q31(\\NLW_memory_reg[31][144]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][145]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][145]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[145]),\n .Q(\\s_axi_rresp[1] [145]),\n .Q31(\\NLW_memory_reg[31][145]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][146]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][146]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[146]),\n .Q(\\s_axi_rresp[1] [146]),\n .Q31(\\NLW_memory_reg[31][146]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][147]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][147]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[147]),\n .Q(\\s_axi_rresp[1] [147]),\n .Q31(\\NLW_memory_reg[31][147]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][148]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][148]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[148]),\n .Q(\\s_axi_rresp[1] [148]),\n .Q31(\\NLW_memory_reg[31][148]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][149]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][149]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[149]),\n .Q(\\s_axi_rresp[1] [149]),\n .Q31(\\NLW_memory_reg[31][149]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][14]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[14]),\n .Q(\\s_axi_rresp[1] [14]),\n .Q31(\\NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][150]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][150]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[150]),\n .Q(\\s_axi_rresp[1] [150]),\n .Q31(\\NLW_memory_reg[31][150]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][151]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][151]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[151]),\n .Q(\\s_axi_rresp[1] [151]),\n .Q31(\\NLW_memory_reg[31][151]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][152]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][152]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[152]),\n .Q(\\s_axi_rresp[1] [152]),\n .Q31(\\NLW_memory_reg[31][152]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][153]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][153]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[153]),\n .Q(\\s_axi_rresp[1] [153]),\n .Q31(\\NLW_memory_reg[31][153]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][154]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][154]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[154]),\n .Q(\\s_axi_rresp[1] [154]),\n .Q31(\\NLW_memory_reg[31][154]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][155]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][155]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[155]),\n .Q(\\s_axi_rresp[1] [155]),\n .Q31(\\NLW_memory_reg[31][155]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][156]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][156]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[156]),\n .Q(\\s_axi_rresp[1] [156]),\n .Q31(\\NLW_memory_reg[31][156]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][157]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][157]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[157]),\n .Q(\\s_axi_rresp[1] [157]),\n .Q31(\\NLW_memory_reg[31][157]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][158]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][158]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[158]),\n .Q(\\s_axi_rresp[1] [158]),\n .Q31(\\NLW_memory_reg[31][158]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][159]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][159]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[159]),\n .Q(\\s_axi_rresp[1] [159]),\n .Q31(\\NLW_memory_reg[31][159]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][15]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[15]),\n .Q(\\s_axi_rresp[1] [15]),\n .Q31(\\NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][160]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][160]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[160]),\n .Q(\\s_axi_rresp[1] [160]),\n .Q31(\\NLW_memory_reg[31][160]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][161]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][161]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[161]),\n .Q(\\s_axi_rresp[1] [161]),\n .Q31(\\NLW_memory_reg[31][161]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][162]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][162]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[162]),\n .Q(\\s_axi_rresp[1] [162]),\n .Q31(\\NLW_memory_reg[31][162]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][163]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][163]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[163]),\n .Q(\\s_axi_rresp[1] [163]),\n .Q31(\\NLW_memory_reg[31][163]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][164]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][164]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[164]),\n .Q(\\s_axi_rresp[1] [164]),\n .Q31(\\NLW_memory_reg[31][164]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][165]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][165]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[165]),\n .Q(\\s_axi_rresp[1] [165]),\n .Q31(\\NLW_memory_reg[31][165]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][166]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][166]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[166]),\n .Q(\\s_axi_rresp[1] [166]),\n .Q31(\\NLW_memory_reg[31][166]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][167]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][167]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[167]),\n .Q(\\s_axi_rresp[1] [167]),\n .Q31(\\NLW_memory_reg[31][167]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][168]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][168]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[168]),\n .Q(\\s_axi_rresp[1] [168]),\n .Q31(\\NLW_memory_reg[31][168]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][169]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][169]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[169]),\n .Q(\\s_axi_rresp[1] [169]),\n .Q31(\\NLW_memory_reg[31][169]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][16]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[16]),\n .Q(\\s_axi_rresp[1] [16]),\n .Q31(\\NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][170]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][170]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[170]),\n .Q(\\s_axi_rresp[1] [170]),\n .Q31(\\NLW_memory_reg[31][170]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][171]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][171]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[171]),\n .Q(\\s_axi_rresp[1] [171]),\n .Q31(\\NLW_memory_reg[31][171]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][172]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][172]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[172]),\n .Q(\\s_axi_rresp[1] [172]),\n .Q31(\\NLW_memory_reg[31][172]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][173]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][173]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[173]),\n .Q(\\s_axi_rresp[1] [173]),\n .Q31(\\NLW_memory_reg[31][173]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][174]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][174]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[174]),\n .Q(\\s_axi_rresp[1] [174]),\n .Q31(\\NLW_memory_reg[31][174]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][175]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][175]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[175]),\n .Q(\\s_axi_rresp[1] [175]),\n .Q31(\\NLW_memory_reg[31][175]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][176]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][176]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[176]),\n .Q(\\s_axi_rresp[1] [176]),\n .Q31(\\NLW_memory_reg[31][176]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][177]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][177]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[177]),\n .Q(\\s_axi_rresp[1] [177]),\n .Q31(\\NLW_memory_reg[31][177]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][178]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][178]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[178]),\n .Q(\\s_axi_rresp[1] [178]),\n .Q31(\\NLW_memory_reg[31][178]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][179]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][179]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[179]),\n .Q(\\s_axi_rresp[1] [179]),\n .Q31(\\NLW_memory_reg[31][179]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][17]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[17]),\n .Q(\\s_axi_rresp[1] [17]),\n .Q31(\\NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][180]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][180]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[180]),\n .Q(\\s_axi_rresp[1] [180]),\n .Q31(\\NLW_memory_reg[31][180]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][181]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][181]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[181]),\n .Q(\\s_axi_rresp[1] [181]),\n .Q31(\\NLW_memory_reg[31][181]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][182]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][182]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[182]),\n .Q(\\s_axi_rresp[1] [182]),\n .Q31(\\NLW_memory_reg[31][182]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][183]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][183]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[183]),\n .Q(\\s_axi_rresp[1] [183]),\n .Q31(\\NLW_memory_reg[31][183]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][184]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][184]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[184]),\n .Q(\\s_axi_rresp[1] [184]),\n .Q31(\\NLW_memory_reg[31][184]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][185]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][185]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[185]),\n .Q(\\s_axi_rresp[1] [185]),\n .Q31(\\NLW_memory_reg[31][185]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][186]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][186]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[186]),\n .Q(\\s_axi_rresp[1] [186]),\n .Q31(\\NLW_memory_reg[31][186]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][187]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][187]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[187]),\n .Q(\\s_axi_rresp[1] [187]),\n .Q31(\\NLW_memory_reg[31][187]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][188]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][188]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[188]),\n .Q(\\s_axi_rresp[1] [188]),\n .Q31(\\NLW_memory_reg[31][188]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][189]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][189]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[189]),\n .Q(\\s_axi_rresp[1] [189]),\n .Q31(\\NLW_memory_reg[31][189]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][18]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[18]),\n .Q(\\s_axi_rresp[1] [18]),\n .Q31(\\NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][190]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][190]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[190]),\n .Q(\\s_axi_rresp[1] [190]),\n .Q31(\\NLW_memory_reg[31][190]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][191]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][191]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[191]),\n .Q(\\s_axi_rresp[1] [191]),\n .Q31(\\NLW_memory_reg[31][191]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][192]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][192]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[192]),\n .Q(\\s_axi_rresp[1] [192]),\n .Q31(\\NLW_memory_reg[31][192]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][193]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][193]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[193]),\n .Q(\\s_axi_rresp[1] [193]),\n .Q31(\\NLW_memory_reg[31][193]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][194]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][194]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[194]),\n .Q(\\s_axi_rresp[1] [194]),\n .Q31(\\NLW_memory_reg[31][194]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][195]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][195]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[195]),\n .Q(\\s_axi_rresp[1] [195]),\n .Q31(\\NLW_memory_reg[31][195]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][196]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][196]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[196]),\n .Q(\\s_axi_rresp[1] [196]),\n .Q31(\\NLW_memory_reg[31][196]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][197]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][197]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[197]),\n .Q(\\s_axi_rresp[1] [197]),\n .Q31(\\NLW_memory_reg[31][197]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][198]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][198]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[198]),\n .Q(\\s_axi_rresp[1] [198]),\n .Q31(\\NLW_memory_reg[31][198]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][199]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][199]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[199]),\n .Q(\\s_axi_rresp[1] [199]),\n .Q31(\\NLW_memory_reg[31][199]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][19]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[19]),\n .Q(\\s_axi_rresp[1] [19]),\n .Q31(\\NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][1]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[1]),\n .Q(\\s_axi_rresp[1] [1]),\n .Q31(\\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][200]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][200]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[200]),\n .Q(\\s_axi_rresp[1] [200]),\n .Q31(\\NLW_memory_reg[31][200]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][201]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][201]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[201]),\n .Q(\\s_axi_rresp[1] [201]),\n .Q31(\\NLW_memory_reg[31][201]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][202]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][202]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[202]),\n .Q(\\s_axi_rresp[1] [202]),\n .Q31(\\NLW_memory_reg[31][202]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][203]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][203]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[203]),\n .Q(\\s_axi_rresp[1] [203]),\n .Q31(\\NLW_memory_reg[31][203]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][204]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][204]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[204]),\n .Q(\\s_axi_rresp[1] [204]),\n .Q31(\\NLW_memory_reg[31][204]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][205]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][205]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[205]),\n .Q(\\s_axi_rresp[1] [205]),\n .Q31(\\NLW_memory_reg[31][205]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][206]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][206]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[206]),\n .Q(\\s_axi_rresp[1] [206]),\n .Q31(\\NLW_memory_reg[31][206]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][207]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][207]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[207]),\n .Q(\\s_axi_rresp[1] [207]),\n .Q31(\\NLW_memory_reg[31][207]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][208]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][208]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[208]),\n .Q(\\s_axi_rresp[1] [208]),\n .Q31(\\NLW_memory_reg[31][208]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][209]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][209]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[209]),\n .Q(\\s_axi_rresp[1] [209]),\n .Q31(\\NLW_memory_reg[31][209]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][20]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[20]),\n .Q(\\s_axi_rresp[1] [20]),\n .Q31(\\NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][210]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][210]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[210]),\n .Q(\\s_axi_rresp[1] [210]),\n .Q31(\\NLW_memory_reg[31][210]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][211]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][211]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[211]),\n .Q(\\s_axi_rresp[1] [211]),\n .Q31(\\NLW_memory_reg[31][211]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][212]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][212]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[212]),\n .Q(\\s_axi_rresp[1] [212]),\n .Q31(\\NLW_memory_reg[31][212]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][213]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][213]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[213]),\n .Q(\\s_axi_rresp[1] [213]),\n .Q31(\\NLW_memory_reg[31][213]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][214]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][214]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[214]),\n .Q(\\s_axi_rresp[1] [214]),\n .Q31(\\NLW_memory_reg[31][214]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][215]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][215]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[215]),\n .Q(\\s_axi_rresp[1] [215]),\n .Q31(\\NLW_memory_reg[31][215]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][216]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][216]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[216]),\n .Q(\\s_axi_rresp[1] [216]),\n .Q31(\\NLW_memory_reg[31][216]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][217]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][217]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[217]),\n .Q(\\s_axi_rresp[1] [217]),\n .Q31(\\NLW_memory_reg[31][217]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][218]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][218]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[218]),\n .Q(\\s_axi_rresp[1] [218]),\n .Q31(\\NLW_memory_reg[31][218]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][219]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][219]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[219]),\n .Q(\\s_axi_rresp[1] [219]),\n .Q31(\\NLW_memory_reg[31][219]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][21]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[21]),\n .Q(\\s_axi_rresp[1] [21]),\n .Q31(\\NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][220]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][220]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[220]),\n .Q(\\s_axi_rresp[1] [220]),\n .Q31(\\NLW_memory_reg[31][220]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][221]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][221]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[221]),\n .Q(\\s_axi_rresp[1] [221]),\n .Q31(\\NLW_memory_reg[31][221]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][222]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][222]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[222]),\n .Q(\\s_axi_rresp[1] [222]),\n .Q31(\\NLW_memory_reg[31][222]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][223]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][223]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[223]),\n .Q(\\s_axi_rresp[1] [223]),\n .Q31(\\NLW_memory_reg[31][223]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][224]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][224]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[224]),\n .Q(\\s_axi_rresp[1] [224]),\n .Q31(\\NLW_memory_reg[31][224]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][225]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][225]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[225]),\n .Q(\\s_axi_rresp[1] [225]),\n .Q31(\\NLW_memory_reg[31][225]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][226]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][226]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[226]),\n .Q(\\s_axi_rresp[1] [226]),\n .Q31(\\NLW_memory_reg[31][226]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][227]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][227]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[227]),\n .Q(\\s_axi_rresp[1] [227]),\n .Q31(\\NLW_memory_reg[31][227]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][228]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][228]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[228]),\n .Q(\\s_axi_rresp[1] [228]),\n .Q31(\\NLW_memory_reg[31][228]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][229]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][229]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[229]),\n .Q(\\s_axi_rresp[1] [229]),\n .Q31(\\NLW_memory_reg[31][229]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][22]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[22]),\n .Q(\\s_axi_rresp[1] [22]),\n .Q31(\\NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][230]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][230]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[230]),\n .Q(\\s_axi_rresp[1] [230]),\n .Q31(\\NLW_memory_reg[31][230]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][231]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][231]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[231]),\n .Q(\\s_axi_rresp[1] [231]),\n .Q31(\\NLW_memory_reg[31][231]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][232]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][232]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[232]),\n .Q(\\s_axi_rresp[1] [232]),\n .Q31(\\NLW_memory_reg[31][232]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][233]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][233]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[233]),\n .Q(\\s_axi_rresp[1] [233]),\n .Q31(\\NLW_memory_reg[31][233]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][234]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][234]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[234]),\n .Q(\\s_axi_rresp[1] [234]),\n .Q31(\\NLW_memory_reg[31][234]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][235]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][235]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[235]),\n .Q(\\s_axi_rresp[1] [235]),\n .Q31(\\NLW_memory_reg[31][235]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][236]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][236]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[236]),\n .Q(\\s_axi_rresp[1] [236]),\n .Q31(\\NLW_memory_reg[31][236]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][237]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][237]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[237]),\n .Q(\\s_axi_rresp[1] [237]),\n .Q31(\\NLW_memory_reg[31][237]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][238]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][238]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[238]),\n .Q(\\s_axi_rresp[1] [238]),\n .Q31(\\NLW_memory_reg[31][238]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][239]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][239]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[239]),\n .Q(\\s_axi_rresp[1] [239]),\n .Q31(\\NLW_memory_reg[31][239]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][23]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[23]),\n .Q(\\s_axi_rresp[1] [23]),\n .Q31(\\NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][240]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][240]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[240]),\n .Q(\\s_axi_rresp[1] [240]),\n .Q31(\\NLW_memory_reg[31][240]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][241]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][241]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[241]),\n .Q(\\s_axi_rresp[1] [241]),\n .Q31(\\NLW_memory_reg[31][241]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][242]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][242]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[242]),\n .Q(\\s_axi_rresp[1] [242]),\n .Q31(\\NLW_memory_reg[31][242]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][243]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][243]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[243]),\n .Q(\\s_axi_rresp[1] [243]),\n .Q31(\\NLW_memory_reg[31][243]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][244]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][244]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[244]),\n .Q(\\s_axi_rresp[1] [244]),\n .Q31(\\NLW_memory_reg[31][244]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][245]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][245]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[245]),\n .Q(\\s_axi_rresp[1] [245]),\n .Q31(\\NLW_memory_reg[31][245]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][246]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][246]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[246]),\n .Q(\\s_axi_rresp[1] [246]),\n .Q31(\\NLW_memory_reg[31][246]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][247]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][247]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[247]),\n .Q(\\s_axi_rresp[1] [247]),\n .Q31(\\NLW_memory_reg[31][247]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][248]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][248]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[248]),\n .Q(\\s_axi_rresp[1] [248]),\n .Q31(\\NLW_memory_reg[31][248]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][249]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][249]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[249]),\n .Q(\\s_axi_rresp[1] [249]),\n .Q31(\\NLW_memory_reg[31][249]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][24]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[24]),\n .Q(\\s_axi_rresp[1] [24]),\n .Q31(\\NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][250]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][250]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[250]),\n .Q(\\s_axi_rresp[1] [250]),\n .Q31(\\NLW_memory_reg[31][250]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][251]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][251]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[251]),\n .Q(\\s_axi_rresp[1] [251]),\n .Q31(\\NLW_memory_reg[31][251]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][252]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][252]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[252]),\n .Q(\\s_axi_rresp[1] [252]),\n .Q31(\\NLW_memory_reg[31][252]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][253]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][253]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[253]),\n .Q(\\s_axi_rresp[1] [253]),\n .Q31(\\NLW_memory_reg[31][253]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][254]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][254]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[254]),\n .Q(\\s_axi_rresp[1] [254]),\n .Q31(\\NLW_memory_reg[31][254]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][255]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][255]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[255]),\n .Q(\\s_axi_rresp[1] [255]),\n .Q31(\\NLW_memory_reg[31][255]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][256]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][256]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(1'b0),\n .Q(\\s_axi_rresp[1] [256]),\n .Q31(\\NLW_memory_reg[31][256]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][25]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[25]),\n .Q(\\s_axi_rresp[1] [25]),\n .Q31(\\NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][26]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[26]),\n .Q(\\s_axi_rresp[1] [26]),\n .Q31(\\NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][27]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[27]),\n .Q(\\s_axi_rresp[1] [27]),\n .Q31(\\NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][28]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[28]),\n .Q(\\s_axi_rresp[1] [28]),\n .Q31(\\NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][29]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[29]),\n .Q(\\s_axi_rresp[1] [29]),\n .Q31(\\NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][2]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[2]),\n .Q(\\s_axi_rresp[1] [2]),\n .Q31(\\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][30]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[30]),\n .Q(\\s_axi_rresp[1] [30]),\n .Q31(\\NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][31]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[31]),\n .Q(\\s_axi_rresp[1] [31]),\n .Q31(\\NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][32]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[32]),\n .Q(\\s_axi_rresp[1] [32]),\n .Q31(\\NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][33]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[33]),\n .Q(\\s_axi_rresp[1] [33]),\n .Q31(\\NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][34]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][34]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[34]),\n .Q(\\s_axi_rresp[1] [34]),\n .Q31(\\NLW_memory_reg[31][34]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][35]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][35]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[35]),\n .Q(\\s_axi_rresp[1] [35]),\n .Q31(\\NLW_memory_reg[31][35]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][36]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][36]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[36]),\n .Q(\\s_axi_rresp[1] [36]),\n .Q31(\\NLW_memory_reg[31][36]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][37]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][37]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[37]),\n .Q(\\s_axi_rresp[1] [37]),\n .Q31(\\NLW_memory_reg[31][37]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][38]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][38]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[38]),\n .Q(\\s_axi_rresp[1] [38]),\n .Q31(\\NLW_memory_reg[31][38]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][39]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][39]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[39]),\n .Q(\\s_axi_rresp[1] [39]),\n .Q31(\\NLW_memory_reg[31][39]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][3]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[3]),\n .Q(\\s_axi_rresp[1] [3]),\n .Q31(\\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][40]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][40]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[40]),\n .Q(\\s_axi_rresp[1] [40]),\n .Q31(\\NLW_memory_reg[31][40]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][41]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][41]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[41]),\n .Q(\\s_axi_rresp[1] [41]),\n .Q31(\\NLW_memory_reg[31][41]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][42]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][42]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[42]),\n .Q(\\s_axi_rresp[1] [42]),\n .Q31(\\NLW_memory_reg[31][42]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][43]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][43]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[43]),\n .Q(\\s_axi_rresp[1] [43]),\n .Q31(\\NLW_memory_reg[31][43]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][44]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][44]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[44]),\n .Q(\\s_axi_rresp[1] [44]),\n .Q31(\\NLW_memory_reg[31][44]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][45]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][45]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[45]),\n .Q(\\s_axi_rresp[1] [45]),\n .Q31(\\NLW_memory_reg[31][45]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][46]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][46]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[46]),\n .Q(\\s_axi_rresp[1] [46]),\n .Q31(\\NLW_memory_reg[31][46]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][47]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][47]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[47]),\n .Q(\\s_axi_rresp[1] [47]),\n .Q31(\\NLW_memory_reg[31][47]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][48]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][48]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[48]),\n .Q(\\s_axi_rresp[1] [48]),\n .Q31(\\NLW_memory_reg[31][48]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][49]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][49]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[49]),\n .Q(\\s_axi_rresp[1] [49]),\n .Q31(\\NLW_memory_reg[31][49]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][4]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[4]),\n .Q(\\s_axi_rresp[1] [4]),\n .Q31(\\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][50]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][50]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[50]),\n .Q(\\s_axi_rresp[1] [50]),\n .Q31(\\NLW_memory_reg[31][50]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][51]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][51]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[51]),\n .Q(\\s_axi_rresp[1] [51]),\n .Q31(\\NLW_memory_reg[31][51]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][52]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][52]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[52]),\n .Q(\\s_axi_rresp[1] [52]),\n .Q31(\\NLW_memory_reg[31][52]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][53]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][53]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[53]),\n .Q(\\s_axi_rresp[1] [53]),\n .Q31(\\NLW_memory_reg[31][53]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][54]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][54]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[54]),\n .Q(\\s_axi_rresp[1] [54]),\n .Q31(\\NLW_memory_reg[31][54]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][55]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][55]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[55]),\n .Q(\\s_axi_rresp[1] [55]),\n .Q31(\\NLW_memory_reg[31][55]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][56]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][56]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[56]),\n .Q(\\s_axi_rresp[1] [56]),\n .Q31(\\NLW_memory_reg[31][56]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][57]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][57]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[57]),\n .Q(\\s_axi_rresp[1] [57]),\n .Q31(\\NLW_memory_reg[31][57]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][58]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][58]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[58]),\n .Q(\\s_axi_rresp[1] [58]),\n .Q31(\\NLW_memory_reg[31][58]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][59]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][59]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[59]),\n .Q(\\s_axi_rresp[1] [59]),\n .Q31(\\NLW_memory_reg[31][59]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][5]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[5]),\n .Q(\\s_axi_rresp[1] [5]),\n .Q31(\\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][60]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][60]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[60]),\n .Q(\\s_axi_rresp[1] [60]),\n .Q31(\\NLW_memory_reg[31][60]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][61]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][61]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[61]),\n .Q(\\s_axi_rresp[1] [61]),\n .Q31(\\NLW_memory_reg[31][61]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][62]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][62]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[62]),\n .Q(\\s_axi_rresp[1] [62]),\n .Q31(\\NLW_memory_reg[31][62]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][63]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][63]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[63]),\n .Q(\\s_axi_rresp[1] [63]),\n .Q31(\\NLW_memory_reg[31][63]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][64]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][64]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[64]),\n .Q(\\s_axi_rresp[1] [64]),\n .Q31(\\NLW_memory_reg[31][64]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][65]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][65]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[65]),\n .Q(\\s_axi_rresp[1] [65]),\n .Q31(\\NLW_memory_reg[31][65]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][66]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][66]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[66]),\n .Q(\\s_axi_rresp[1] [66]),\n .Q31(\\NLW_memory_reg[31][66]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][67]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][67]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[67]),\n .Q(\\s_axi_rresp[1] [67]),\n .Q31(\\NLW_memory_reg[31][67]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][68]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][68]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[68]),\n .Q(\\s_axi_rresp[1] [68]),\n .Q31(\\NLW_memory_reg[31][68]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][69]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][69]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[69]),\n .Q(\\s_axi_rresp[1] [69]),\n .Q31(\\NLW_memory_reg[31][69]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][6]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[6]),\n .Q(\\s_axi_rresp[1] [6]),\n .Q31(\\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][70]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][70]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[70]),\n .Q(\\s_axi_rresp[1] [70]),\n .Q31(\\NLW_memory_reg[31][70]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][71]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][71]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[71]),\n .Q(\\s_axi_rresp[1] [71]),\n .Q31(\\NLW_memory_reg[31][71]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][72]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][72]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[72]),\n .Q(\\s_axi_rresp[1] [72]),\n .Q31(\\NLW_memory_reg[31][72]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][73]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][73]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[73]),\n .Q(\\s_axi_rresp[1] [73]),\n .Q31(\\NLW_memory_reg[31][73]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][74]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][74]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[74]),\n .Q(\\s_axi_rresp[1] [74]),\n .Q31(\\NLW_memory_reg[31][74]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][75]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][75]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[75]),\n .Q(\\s_axi_rresp[1] [75]),\n .Q31(\\NLW_memory_reg[31][75]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][76]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][76]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[76]),\n .Q(\\s_axi_rresp[1] [76]),\n .Q31(\\NLW_memory_reg[31][76]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][77]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][77]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[77]),\n .Q(\\s_axi_rresp[1] [77]),\n .Q31(\\NLW_memory_reg[31][77]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][78]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][78]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[78]),\n .Q(\\s_axi_rresp[1] [78]),\n .Q31(\\NLW_memory_reg[31][78]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][79]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][79]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[79]),\n .Q(\\s_axi_rresp[1] [79]),\n .Q31(\\NLW_memory_reg[31][79]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][7]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[7]),\n .Q(\\s_axi_rresp[1] [7]),\n .Q31(\\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][80]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][80]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[80]),\n .Q(\\s_axi_rresp[1] [80]),\n .Q31(\\NLW_memory_reg[31][80]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][81]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][81]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[81]),\n .Q(\\s_axi_rresp[1] [81]),\n .Q31(\\NLW_memory_reg[31][81]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][82]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][82]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[82]),\n .Q(\\s_axi_rresp[1] [82]),\n .Q31(\\NLW_memory_reg[31][82]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][83]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][83]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[83]),\n .Q(\\s_axi_rresp[1] [83]),\n .Q31(\\NLW_memory_reg[31][83]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][84]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][84]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[84]),\n .Q(\\s_axi_rresp[1] [84]),\n .Q31(\\NLW_memory_reg[31][84]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][85]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][85]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[85]),\n .Q(\\s_axi_rresp[1] [85]),\n .Q31(\\NLW_memory_reg[31][85]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][86]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][86]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[86]),\n .Q(\\s_axi_rresp[1] [86]),\n .Q31(\\NLW_memory_reg[31][86]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][87]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][87]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[87]),\n .Q(\\s_axi_rresp[1] [87]),\n .Q31(\\NLW_memory_reg[31][87]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][88]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][88]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[88]),\n .Q(\\s_axi_rresp[1] [88]),\n .Q31(\\NLW_memory_reg[31][88]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][89]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][89]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[89]),\n .Q(\\s_axi_rresp[1] [89]),\n .Q31(\\NLW_memory_reg[31][89]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][8]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[8]),\n .Q(\\s_axi_rresp[1] [8]),\n .Q31(\\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][90]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][90]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[90]),\n .Q(\\s_axi_rresp[1] [90]),\n .Q31(\\NLW_memory_reg[31][90]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][91]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][91]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[91]),\n .Q(\\s_axi_rresp[1] [91]),\n .Q31(\\NLW_memory_reg[31][91]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][92]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][92]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[92]),\n .Q(\\s_axi_rresp[1] [92]),\n .Q31(\\NLW_memory_reg[31][92]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][93]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][93]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[93]),\n .Q(\\s_axi_rresp[1] [93]),\n .Q31(\\NLW_memory_reg[31][93]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][94]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][94]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[94]),\n .Q(\\s_axi_rresp[1] [94]),\n .Q31(\\NLW_memory_reg[31][94]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][95]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][95]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[95]),\n .Q(\\s_axi_rresp[1] [95]),\n .Q31(\\NLW_memory_reg[31][95]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][96]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][96]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[96]),\n .Q(\\s_axi_rresp[1] [96]),\n .Q31(\\NLW_memory_reg[31][96]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][97]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][97]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[97]),\n .Q(\\s_axi_rresp[1] [97]),\n .Q31(\\NLW_memory_reg[31][97]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][98]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][98]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[98]),\n .Q(\\s_axi_rresp[1] [98]),\n .Q31(\\NLW_memory_reg[31][98]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][99]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][99]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[99]),\n .Q(\\s_axi_rresp[1] [99]),\n .Q31(\\NLW_memory_reg[31][99]_srl32_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[31][9]_srl32 \n (.A({\\cnt_read_reg[4]_rep_n_0 ,\\cnt_read_reg[3]_rep_n_0 ,\\cnt_read_reg[2]_rep_n_0 ,\\cnt_read_reg[1]_rep_n_0 ,\\cnt_read_reg[0]_rep_n_0 }),\n .CE(app_rd_data_valid),\n .CLK(CLK),\n .D(Q[9]),\n .Q(\\s_axi_rresp[1] [9]),\n .Q31(\\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ));\n LUT6 #(\n .INIT(64'h00B8000000B800B8)) \n r_push_i_2\n (.I0(s_axi_arvalid),\n .I1(s_axi_arready),\n .I2(axvalid),\n .I3(\\cnt_read_reg[5]_0 ),\n .I4(cnt_read_reg__0),\n .I5(r_push_i_4_n_0),\n .O(rd_cmd_en));\n (* SOFT_HLUTNM = \"soft_lutpair1192\" *) \n LUT4 #(\n .INIT(16'h8000)) \n r_push_i_4\n (.I0(cnt_read_reg__1[2]),\n .I1(cnt_read_reg__1[1]),\n .I2(cnt_read_reg__1[4]),\n .I3(cnt_read_reg__1[3]),\n .O(r_push_i_4_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1194\" *) \n LUT2 #(\n .INIT(4'h2)) \n s_axi_rvalid_INST_0\n (.I0(rvalid04_in),\n .I1(\\trans_buf_out_r_reg[0] ),\n .O(s_axi_rvalid));\n LUT6 #(\n .INIT(64'h7FFFFFFFFFFFFFFF)) \n s_axi_rvalid_INST_0_i_1\n (.I0(cnt_read_reg__1[2]),\n .I1(cnt_read_reg__1[1]),\n .I2(cnt_read_reg__1[4]),\n .I3(cnt_read_reg__1[3]),\n .I4(cnt_read_reg__0),\n .I5(cnt_read_reg__1[0]),\n .O(rvalid04_in));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_axi_mc_fifo\" *) \nmodule ddr3_if_mig_7series_v4_0_axi_mc_fifo__parameterized1\n (E,\n tr_empty,\n \\RD_PRI_REG_STARVE.rd_starve_cnt_reg[8] ,\n \\trans_buf_out_r_reg[0] ,\n \\trans_buf_out_r1_reg[3] ,\n \\trans_buf_out_r_reg[2] ,\n \\trans_buf_out_r_reg[3] ,\n out,\n p_0_in,\n r_push,\n Q,\n \\trans_buf_out_r_reg[0]_0 ,\n assert_rlast,\n s_axi_rid,\n CLK,\n in,\n areset_d1);\n output [0:0]E;\n output tr_empty;\n output \\RD_PRI_REG_STARVE.rd_starve_cnt_reg[8] ;\n output \\trans_buf_out_r_reg[0] ;\n output [2:0]\\trans_buf_out_r1_reg[3] ;\n output \\trans_buf_out_r_reg[2] ;\n output \\trans_buf_out_r_reg[3] ;\n input [1:0]out;\n input p_0_in;\n input r_push;\n input [2:0]Q;\n input \\trans_buf_out_r_reg[0]_0 ;\n input assert_rlast;\n input [0:0]s_axi_rid;\n input CLK;\n input [1:0]in;\n input areset_d1;\n\n wire CLK;\n wire [0:0]E;\n wire [2:0]Q;\n wire \\RD_PRI_REG_STARVE.rd_starve_cnt_reg[8] ;\n wire areset_d1;\n wire assert_rlast;\n wire \\cnt_read[0]_i_1__0_n_0 ;\n wire \\cnt_read[1]_i_1__1_n_0 ;\n wire \\cnt_read[2]_i_1_n_0 ;\n wire \\cnt_read[3]_i_1_n_0 ;\n wire \\cnt_read[4]_i_1_n_0 ;\n wire \\cnt_read[5]_i_1__0_n_0 ;\n wire \\cnt_read[5]_i_2_n_0 ;\n wire \\cnt_read[5]_i_3__0_n_0 ;\n wire [4:0]cnt_read_reg__0;\n wire [5:5]cnt_read_reg__0__0;\n wire [1:0]in;\n wire load_stage1;\n wire [1:0]out;\n wire p_0_in;\n wire r_push;\n wire [0:0]s_axi_rid;\n wire tr_empty;\n wire [2:0]\\trans_buf_out_r1_reg[3] ;\n wire \\trans_buf_out_r_reg[0] ;\n wire \\trans_buf_out_r_reg[0]_0 ;\n wire \\trans_buf_out_r_reg[2] ;\n wire \\trans_buf_out_r_reg[3] ;\n wire \\NLW_memory_reg[29][0]_srl30_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[29][2]_srl30_Q31_UNCONNECTED ;\n wire \\NLW_memory_reg[29][3]_srl30_Q31_UNCONNECTED ;\n\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\FSM_sequential_state[1]_i_3 \n (.I0(cnt_read_reg__0[0]),\n .I1(cnt_read_reg__0[1]),\n .I2(cnt_read_reg__0__0),\n .I3(cnt_read_reg__0[2]),\n .I4(cnt_read_reg__0[3]),\n .I5(cnt_read_reg__0[4]),\n .O(tr_empty));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_read[0]_i_1__0 \n (.I0(cnt_read_reg__0[0]),\n .O(\\cnt_read[0]_i_1__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1195\" *) \n LUT5 #(\n .INIT(32'h56AAA955)) \n \\cnt_read[1]_i_1__1 \n (.I0(cnt_read_reg__0[0]),\n .I1(tr_empty),\n .I2(out[1]),\n .I3(r_push),\n .I4(cnt_read_reg__0[1]),\n .O(\\cnt_read[1]_i_1__1_n_0 ));\n LUT3 #(\n .INIT(8'h69)) \n \\cnt_read[2]_i_1 \n (.I0(\\cnt_read[5]_i_3__0_n_0 ),\n .I1(cnt_read_reg__0[2]),\n .I2(cnt_read_reg__0[1]),\n .O(\\cnt_read[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1196\" *) \n LUT4 #(\n .INIT(16'h78E1)) \n \\cnt_read[3]_i_1 \n (.I0(cnt_read_reg__0[1]),\n .I1(\\cnt_read[5]_i_3__0_n_0 ),\n .I2(cnt_read_reg__0[3]),\n .I3(cnt_read_reg__0[2]),\n .O(\\cnt_read[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1196\" *) \n LUT5 #(\n .INIT(32'h7F80FE01)) \n \\cnt_read[4]_i_1 \n (.I0(cnt_read_reg__0[1]),\n .I1(\\cnt_read[5]_i_3__0_n_0 ),\n .I2(cnt_read_reg__0[2]),\n .I3(cnt_read_reg__0[4]),\n .I4(cnt_read_reg__0[3]),\n .O(\\cnt_read[4]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hE1)) \n \\cnt_read[5]_i_1__0 \n (.I0(tr_empty),\n .I1(out[1]),\n .I2(r_push),\n .O(\\cnt_read[5]_i_1__0_n_0 ));\n LUT6 #(\n .INIT(64'h7FFF8000FFFE0001)) \n \\cnt_read[5]_i_2 \n (.I0(cnt_read_reg__0[1]),\n .I1(\\cnt_read[5]_i_3__0_n_0 ),\n .I2(cnt_read_reg__0[2]),\n .I3(cnt_read_reg__0[3]),\n .I4(cnt_read_reg__0__0),\n .I5(cnt_read_reg__0[4]),\n .O(\\cnt_read[5]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1195\" *) \n LUT5 #(\n .INIT(32'hA800FEAA)) \n \\cnt_read[5]_i_3__0 \n (.I0(cnt_read_reg__0[0]),\n .I1(tr_empty),\n .I2(out[1]),\n .I3(r_push),\n .I4(cnt_read_reg__0[1]),\n .O(\\cnt_read[5]_i_3__0_n_0 ));\n FDSE \\cnt_read_reg[0] \n (.C(CLK),\n .CE(\\cnt_read[5]_i_1__0_n_0 ),\n .D(\\cnt_read[0]_i_1__0_n_0 ),\n .Q(cnt_read_reg__0[0]),\n .S(areset_d1));\n FDSE \\cnt_read_reg[1] \n (.C(CLK),\n .CE(\\cnt_read[5]_i_1__0_n_0 ),\n .D(\\cnt_read[1]_i_1__1_n_0 ),\n .Q(cnt_read_reg__0[1]),\n .S(areset_d1));\n FDSE \\cnt_read_reg[2] \n (.C(CLK),\n .CE(\\cnt_read[5]_i_1__0_n_0 ),\n .D(\\cnt_read[2]_i_1_n_0 ),\n .Q(cnt_read_reg__0[2]),\n .S(areset_d1));\n FDSE \\cnt_read_reg[3] \n (.C(CLK),\n .CE(\\cnt_read[5]_i_1__0_n_0 ),\n .D(\\cnt_read[3]_i_1_n_0 ),\n .Q(cnt_read_reg__0[3]),\n .S(areset_d1));\n FDSE \\cnt_read_reg[4] \n (.C(CLK),\n .CE(\\cnt_read[5]_i_1__0_n_0 ),\n .D(\\cnt_read[4]_i_1_n_0 ),\n .Q(cnt_read_reg__0[4]),\n .S(areset_d1));\n FDSE \\cnt_read_reg[5] \n (.C(CLK),\n .CE(\\cnt_read[5]_i_1__0_n_0 ),\n .D(\\cnt_read[5]_i_2_n_0 ),\n .Q(cnt_read_reg__0__0),\n .S(areset_d1));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/transaction_fifo_0/memory_reg[29] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/transaction_fifo_0/memory_reg[29][0]_srl30 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[29][0]_srl30 \n (.A(cnt_read_reg__0),\n .CE(r_push),\n .CLK(CLK),\n .D(1'b0),\n .Q(\\trans_buf_out_r1_reg[3] [0]),\n .Q31(\\NLW_memory_reg[29][0]_srl30_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/transaction_fifo_0/memory_reg[29] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/transaction_fifo_0/memory_reg[29][2]_srl30 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[29][2]_srl30 \n (.A(cnt_read_reg__0),\n .CE(r_push),\n .CLK(CLK),\n .D(in[0]),\n .Q(\\trans_buf_out_r1_reg[3] [1]),\n .Q31(\\NLW_memory_reg[29][2]_srl30_Q31_UNCONNECTED ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/transaction_fifo_0/memory_reg[29] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/transaction_fifo_0/memory_reg[29][3]_srl30 \" *) \n SRLC32E #(\n .INIT(32'h00000000)) \n \\memory_reg[29][3]_srl30 \n (.A(cnt_read_reg__0),\n .CE(r_push),\n .CLK(CLK),\n .D(in[1]),\n .Q(\\trans_buf_out_r1_reg[3] [2]),\n .Q31(\\NLW_memory_reg[29][3]_srl30_Q31_UNCONNECTED ));\n LUT5 #(\n .INIT(32'h10000000)) \n r_push_i_3\n (.I0(cnt_read_reg__0__0),\n .I1(cnt_read_reg__0[1]),\n .I2(cnt_read_reg__0[2]),\n .I3(cnt_read_reg__0[3]),\n .I4(cnt_read_reg__0[4]),\n .O(\\RD_PRI_REG_STARVE.rd_starve_cnt_reg[8] ));\n (* SOFT_HLUTNM = \"soft_lutpair1197\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\trans_buf_out_r1[3]_i_1 \n (.I0(out[1]),\n .I1(tr_empty),\n .O(E));\n LUT6 #(\n .INIT(64'hFB08FFFFFB080000)) \n \\trans_buf_out_r[0]_i_1 \n (.I0(Q[0]),\n .I1(out[1]),\n .I2(out[0]),\n .I3(\\trans_buf_out_r1_reg[3] [0]),\n .I4(load_stage1),\n .I5(\\trans_buf_out_r_reg[0]_0 ),\n .O(\\trans_buf_out_r_reg[0] ));\n LUT6 #(\n .INIT(64'hFB08FFFFFB080000)) \n \\trans_buf_out_r[2]_i_1 \n (.I0(Q[1]),\n .I1(out[1]),\n .I2(out[0]),\n .I3(\\trans_buf_out_r1_reg[3] [1]),\n .I4(load_stage1),\n .I5(assert_rlast),\n .O(\\trans_buf_out_r_reg[2] ));\n LUT6 #(\n .INIT(64'hFB08FFFFFB080000)) \n \\trans_buf_out_r[3]_i_1 \n (.I0(Q[2]),\n .I1(out[1]),\n .I2(out[0]),\n .I3(\\trans_buf_out_r1_reg[3] [2]),\n .I4(load_stage1),\n .I5(s_axi_rid),\n .O(\\trans_buf_out_r_reg[3] ));\n (* SOFT_HLUTNM = \"soft_lutpair1197\" *) \n LUT4 #(\n .INIT(16'h1D01)) \n \\trans_buf_out_r[3]_i_2 \n (.I0(tr_empty),\n .I1(out[1]),\n .I2(out[0]),\n .I3(p_0_in),\n .O(load_stage1));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_axi_mc_incr_cmd\n (out,\n Q,\n \\app_addr_r1_reg[27] ,\n in0,\n axready_reg,\n S,\n axready_reg_0,\n areset_d1,\n E,\n D,\n CLK,\n axready_reg_1);\n output [29:0]out;\n output [7:0]Q;\n output [29:0]\\app_addr_r1_reg[27] ;\n input [3:0]in0;\n input [24:0]axready_reg;\n input [0:0]S;\n input [0:0]axready_reg_0;\n input areset_d1;\n input [0:0]E;\n input [7:0]D;\n input CLK;\n input [29:0]axready_reg_1;\n\n wire CLK;\n wire [7:0]D;\n wire [0:0]E;\n wire [7:0]Q;\n wire [0:0]S;\n wire [29:0]\\app_addr_r1_reg[27] ;\n wire areset_d1;\n (* RTL_KEEP = \"true\" *) wire [29:0]axaddr_incr_p;\n wire axaddr_incr_p_reg0_carry__0_n_0;\n wire axaddr_incr_p_reg0_carry__0_n_1;\n wire axaddr_incr_p_reg0_carry__0_n_2;\n wire axaddr_incr_p_reg0_carry__0_n_3;\n wire axaddr_incr_p_reg0_carry__1_n_0;\n wire axaddr_incr_p_reg0_carry__1_n_1;\n wire axaddr_incr_p_reg0_carry__1_n_2;\n wire axaddr_incr_p_reg0_carry__1_n_3;\n wire axaddr_incr_p_reg0_carry__2_n_0;\n wire axaddr_incr_p_reg0_carry__2_n_1;\n wire axaddr_incr_p_reg0_carry__2_n_2;\n wire axaddr_incr_p_reg0_carry__2_n_3;\n wire axaddr_incr_p_reg0_carry__3_n_0;\n wire axaddr_incr_p_reg0_carry__3_n_1;\n wire axaddr_incr_p_reg0_carry__3_n_2;\n wire axaddr_incr_p_reg0_carry__3_n_3;\n wire axaddr_incr_p_reg0_carry__4_n_0;\n wire axaddr_incr_p_reg0_carry__4_n_1;\n wire axaddr_incr_p_reg0_carry__4_n_2;\n wire axaddr_incr_p_reg0_carry__4_n_3;\n wire axaddr_incr_p_reg0_carry__5_n_3;\n wire axaddr_incr_p_reg0_carry_n_0;\n wire axaddr_incr_p_reg0_carry_n_1;\n wire axaddr_incr_p_reg0_carry_n_2;\n wire axaddr_incr_p_reg0_carry_n_3;\n wire [24:0]axready_reg;\n wire [0:0]axready_reg_0;\n wire [29:0]axready_reg_1;\n wire [3:1]NLW_axaddr_incr_p_reg0_carry__5_CO_UNCONNECTED;\n wire [3:2]NLW_axaddr_incr_p_reg0_carry__5_O_UNCONNECTED;\n\n assign axaddr_incr_p[3:0] = in0[3:0];\n assign out[29:0] = axaddr_incr_p;\n CARRY4 axaddr_incr_p_reg0_carry\n (.CI(1'b0),\n .CO({axaddr_incr_p_reg0_carry_n_0,axaddr_incr_p_reg0_carry_n_1,axaddr_incr_p_reg0_carry_n_2,axaddr_incr_p_reg0_carry_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,axready_reg[1],1'b0}),\n .O(axaddr_incr_p[7:4]),\n .S({axready_reg[3:2],S,axready_reg[0]}));\n CARRY4 axaddr_incr_p_reg0_carry__0\n (.CI(axaddr_incr_p_reg0_carry_n_0),\n .CO({axaddr_incr_p_reg0_carry__0_n_0,axaddr_incr_p_reg0_carry__0_n_1,axaddr_incr_p_reg0_carry__0_n_2,axaddr_incr_p_reg0_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(axaddr_incr_p[11:8]),\n .S({axready_reg[6:4],axready_reg_0}));\n CARRY4 axaddr_incr_p_reg0_carry__1\n (.CI(axaddr_incr_p_reg0_carry__0_n_0),\n .CO({axaddr_incr_p_reg0_carry__1_n_0,axaddr_incr_p_reg0_carry__1_n_1,axaddr_incr_p_reg0_carry__1_n_2,axaddr_incr_p_reg0_carry__1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(axaddr_incr_p[15:12]),\n .S(axready_reg[10:7]));\n CARRY4 axaddr_incr_p_reg0_carry__2\n (.CI(axaddr_incr_p_reg0_carry__1_n_0),\n .CO({axaddr_incr_p_reg0_carry__2_n_0,axaddr_incr_p_reg0_carry__2_n_1,axaddr_incr_p_reg0_carry__2_n_2,axaddr_incr_p_reg0_carry__2_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(axaddr_incr_p[19:16]),\n .S(axready_reg[14:11]));\n CARRY4 axaddr_incr_p_reg0_carry__3\n (.CI(axaddr_incr_p_reg0_carry__2_n_0),\n .CO({axaddr_incr_p_reg0_carry__3_n_0,axaddr_incr_p_reg0_carry__3_n_1,axaddr_incr_p_reg0_carry__3_n_2,axaddr_incr_p_reg0_carry__3_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(axaddr_incr_p[23:20]),\n .S(axready_reg[18:15]));\n CARRY4 axaddr_incr_p_reg0_carry__4\n (.CI(axaddr_incr_p_reg0_carry__3_n_0),\n .CO({axaddr_incr_p_reg0_carry__4_n_0,axaddr_incr_p_reg0_carry__4_n_1,axaddr_incr_p_reg0_carry__4_n_2,axaddr_incr_p_reg0_carry__4_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(axaddr_incr_p[27:24]),\n .S(axready_reg[22:19]));\n CARRY4 axaddr_incr_p_reg0_carry__5\n (.CI(axaddr_incr_p_reg0_carry__4_n_0),\n .CO({NLW_axaddr_incr_p_reg0_carry__5_CO_UNCONNECTED[3:1],axaddr_incr_p_reg0_carry__5_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({NLW_axaddr_incr_p_reg0_carry__5_O_UNCONNECTED[3:2],axaddr_incr_p[29:28]}),\n .S({1'b0,1'b0,axready_reg[24:23]}));\n FDRE \\axaddr_incr_reg[0] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[0]),\n .Q(\\app_addr_r1_reg[27] [0]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[10] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[10]),\n .Q(\\app_addr_r1_reg[27] [10]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[11] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[11]),\n .Q(\\app_addr_r1_reg[27] [11]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[12] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[12]),\n .Q(\\app_addr_r1_reg[27] [12]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[13] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[13]),\n .Q(\\app_addr_r1_reg[27] [13]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[14] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[14]),\n .Q(\\app_addr_r1_reg[27] [14]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[15] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[15]),\n .Q(\\app_addr_r1_reg[27] [15]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[16] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[16]),\n .Q(\\app_addr_r1_reg[27] [16]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[17] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[17]),\n .Q(\\app_addr_r1_reg[27] [17]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[18] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[18]),\n .Q(\\app_addr_r1_reg[27] [18]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[19] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[19]),\n .Q(\\app_addr_r1_reg[27] [19]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[1] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[1]),\n .Q(\\app_addr_r1_reg[27] [1]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[20] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[20]),\n .Q(\\app_addr_r1_reg[27] [20]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[21] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[21]),\n .Q(\\app_addr_r1_reg[27] [21]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[22] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[22]),\n .Q(\\app_addr_r1_reg[27] [22]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[23] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[23]),\n .Q(\\app_addr_r1_reg[27] [23]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[24] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[24]),\n .Q(\\app_addr_r1_reg[27] [24]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[25] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[25]),\n .Q(\\app_addr_r1_reg[27] [25]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[26] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[26]),\n .Q(\\app_addr_r1_reg[27] [26]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[27] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[27]),\n .Q(\\app_addr_r1_reg[27] [27]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[28] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[28]),\n .Q(\\app_addr_r1_reg[27] [28]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[29] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[29]),\n .Q(\\app_addr_r1_reg[27] [29]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[2] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[2]),\n .Q(\\app_addr_r1_reg[27] [2]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[3] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[3]),\n .Q(\\app_addr_r1_reg[27] [3]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[4] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[4]),\n .Q(\\app_addr_r1_reg[27] [4]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[5] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[5]),\n .Q(\\app_addr_r1_reg[27] [5]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[6] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[6]),\n .Q(\\app_addr_r1_reg[27] [6]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[7] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[7]),\n .Q(\\app_addr_r1_reg[27] [7]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[8] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[8]),\n .Q(\\app_addr_r1_reg[27] [8]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[9] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_1[9]),\n .Q(\\app_addr_r1_reg[27] [9]),\n .R(areset_d1));\n FDSE \\axlen_cnt_reg[0] \n (.C(CLK),\n .CE(E),\n .D(D[0]),\n .Q(Q[0]),\n .S(areset_d1));\n FDSE \\axlen_cnt_reg[1] \n (.C(CLK),\n .CE(E),\n .D(D[1]),\n .Q(Q[1]),\n .S(areset_d1));\n FDSE \\axlen_cnt_reg[2] \n (.C(CLK),\n .CE(E),\n .D(D[2]),\n .Q(Q[2]),\n .S(areset_d1));\n FDSE \\axlen_cnt_reg[3] \n (.C(CLK),\n .CE(E),\n .D(D[3]),\n .Q(Q[3]),\n .S(areset_d1));\n FDRE \\axlen_cnt_reg[4] \n (.C(CLK),\n .CE(E),\n .D(D[4]),\n .Q(Q[4]),\n .R(areset_d1));\n FDRE \\axlen_cnt_reg[5] \n (.C(CLK),\n .CE(E),\n .D(D[5]),\n .Q(Q[5]),\n .R(areset_d1));\n FDRE \\axlen_cnt_reg[6] \n (.C(CLK),\n .CE(E),\n .D(D[6]),\n .Q(Q[6]),\n .R(areset_d1));\n FDRE \\axlen_cnt_reg[7] \n (.C(CLK),\n .CE(E),\n .D(D[7]),\n .Q(Q[7]),\n .R(areset_d1));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_axi_mc_incr_cmd\" *) \nmodule ddr3_if_mig_7series_v4_0_axi_mc_incr_cmd__parameterized0\n (out,\n Q,\n \\app_addr_r1_reg[27] ,\n in0,\n DI,\n S,\n axready_reg,\n areset_d1,\n E,\n D,\n CLK,\n axready_reg_0);\n output [29:0]out;\n output [7:0]Q;\n output [29:0]\\app_addr_r1_reg[27] ;\n input [3:0]in0;\n input [0:0]DI;\n input [3:0]S;\n input [21:0]axready_reg;\n input areset_d1;\n input [0:0]E;\n input [7:0]D;\n input CLK;\n input [29:0]axready_reg_0;\n\n wire CLK;\n wire [7:0]D;\n wire [0:0]DI;\n wire [0:0]E;\n wire [7:0]Q;\n wire [3:0]S;\n wire [29:0]\\app_addr_r1_reg[27] ;\n wire areset_d1;\n (* RTL_KEEP = \"true\" *) wire [29:0]axaddr_incr_p;\n wire axaddr_incr_p_reg0_carry__0_n_0;\n wire axaddr_incr_p_reg0_carry__0_n_1;\n wire axaddr_incr_p_reg0_carry__0_n_2;\n wire axaddr_incr_p_reg0_carry__0_n_3;\n wire axaddr_incr_p_reg0_carry__1_n_0;\n wire axaddr_incr_p_reg0_carry__1_n_1;\n wire axaddr_incr_p_reg0_carry__1_n_2;\n wire axaddr_incr_p_reg0_carry__1_n_3;\n wire axaddr_incr_p_reg0_carry__2_n_0;\n wire axaddr_incr_p_reg0_carry__2_n_1;\n wire axaddr_incr_p_reg0_carry__2_n_2;\n wire axaddr_incr_p_reg0_carry__2_n_3;\n wire axaddr_incr_p_reg0_carry__3_n_0;\n wire axaddr_incr_p_reg0_carry__3_n_1;\n wire axaddr_incr_p_reg0_carry__3_n_2;\n wire axaddr_incr_p_reg0_carry__3_n_3;\n wire axaddr_incr_p_reg0_carry__4_n_0;\n wire axaddr_incr_p_reg0_carry__4_n_1;\n wire axaddr_incr_p_reg0_carry__4_n_2;\n wire axaddr_incr_p_reg0_carry__4_n_3;\n wire axaddr_incr_p_reg0_carry__5_n_3;\n wire axaddr_incr_p_reg0_carry_n_0;\n wire axaddr_incr_p_reg0_carry_n_1;\n wire axaddr_incr_p_reg0_carry_n_2;\n wire axaddr_incr_p_reg0_carry_n_3;\n wire [21:0]axready_reg;\n wire [29:0]axready_reg_0;\n wire [3:1]NLW_axaddr_incr_p_reg0_carry__5_CO_UNCONNECTED;\n wire [3:2]NLW_axaddr_incr_p_reg0_carry__5_O_UNCONNECTED;\n\n assign axaddr_incr_p[3:0] = in0[3:0];\n assign out[29:0] = axaddr_incr_p;\n CARRY4 axaddr_incr_p_reg0_carry\n (.CI(1'b0),\n .CO({axaddr_incr_p_reg0_carry_n_0,axaddr_incr_p_reg0_carry_n_1,axaddr_incr_p_reg0_carry_n_2,axaddr_incr_p_reg0_carry_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,DI,1'b0}),\n .O(axaddr_incr_p[7:4]),\n .S(S));\n CARRY4 axaddr_incr_p_reg0_carry__0\n (.CI(axaddr_incr_p_reg0_carry_n_0),\n .CO({axaddr_incr_p_reg0_carry__0_n_0,axaddr_incr_p_reg0_carry__0_n_1,axaddr_incr_p_reg0_carry__0_n_2,axaddr_incr_p_reg0_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(axaddr_incr_p[11:8]),\n .S(axready_reg[3:0]));\n CARRY4 axaddr_incr_p_reg0_carry__1\n (.CI(axaddr_incr_p_reg0_carry__0_n_0),\n .CO({axaddr_incr_p_reg0_carry__1_n_0,axaddr_incr_p_reg0_carry__1_n_1,axaddr_incr_p_reg0_carry__1_n_2,axaddr_incr_p_reg0_carry__1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(axaddr_incr_p[15:12]),\n .S(axready_reg[7:4]));\n CARRY4 axaddr_incr_p_reg0_carry__2\n (.CI(axaddr_incr_p_reg0_carry__1_n_0),\n .CO({axaddr_incr_p_reg0_carry__2_n_0,axaddr_incr_p_reg0_carry__2_n_1,axaddr_incr_p_reg0_carry__2_n_2,axaddr_incr_p_reg0_carry__2_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(axaddr_incr_p[19:16]),\n .S(axready_reg[11:8]));\n CARRY4 axaddr_incr_p_reg0_carry__3\n (.CI(axaddr_incr_p_reg0_carry__2_n_0),\n .CO({axaddr_incr_p_reg0_carry__3_n_0,axaddr_incr_p_reg0_carry__3_n_1,axaddr_incr_p_reg0_carry__3_n_2,axaddr_incr_p_reg0_carry__3_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(axaddr_incr_p[23:20]),\n .S(axready_reg[15:12]));\n CARRY4 axaddr_incr_p_reg0_carry__4\n (.CI(axaddr_incr_p_reg0_carry__3_n_0),\n .CO({axaddr_incr_p_reg0_carry__4_n_0,axaddr_incr_p_reg0_carry__4_n_1,axaddr_incr_p_reg0_carry__4_n_2,axaddr_incr_p_reg0_carry__4_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(axaddr_incr_p[27:24]),\n .S(axready_reg[19:16]));\n CARRY4 axaddr_incr_p_reg0_carry__5\n (.CI(axaddr_incr_p_reg0_carry__4_n_0),\n .CO({NLW_axaddr_incr_p_reg0_carry__5_CO_UNCONNECTED[3:1],axaddr_incr_p_reg0_carry__5_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({NLW_axaddr_incr_p_reg0_carry__5_O_UNCONNECTED[3:2],axaddr_incr_p[29:28]}),\n .S({1'b0,1'b0,axready_reg[21:20]}));\n FDRE \\axaddr_incr_reg[0] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[0]),\n .Q(\\app_addr_r1_reg[27] [0]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[10] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[10]),\n .Q(\\app_addr_r1_reg[27] [10]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[11] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[11]),\n .Q(\\app_addr_r1_reg[27] [11]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[12] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[12]),\n .Q(\\app_addr_r1_reg[27] [12]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[13] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[13]),\n .Q(\\app_addr_r1_reg[27] [13]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[14] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[14]),\n .Q(\\app_addr_r1_reg[27] [14]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[15] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[15]),\n .Q(\\app_addr_r1_reg[27] [15]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[16] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[16]),\n .Q(\\app_addr_r1_reg[27] [16]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[17] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[17]),\n .Q(\\app_addr_r1_reg[27] [17]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[18] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[18]),\n .Q(\\app_addr_r1_reg[27] [18]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[19] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[19]),\n .Q(\\app_addr_r1_reg[27] [19]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[1] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[1]),\n .Q(\\app_addr_r1_reg[27] [1]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[20] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[20]),\n .Q(\\app_addr_r1_reg[27] [20]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[21] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[21]),\n .Q(\\app_addr_r1_reg[27] [21]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[22] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[22]),\n .Q(\\app_addr_r1_reg[27] [22]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[23] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[23]),\n .Q(\\app_addr_r1_reg[27] [23]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[24] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[24]),\n .Q(\\app_addr_r1_reg[27] [24]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[25] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[25]),\n .Q(\\app_addr_r1_reg[27] [25]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[26] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[26]),\n .Q(\\app_addr_r1_reg[27] [26]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[27] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[27]),\n .Q(\\app_addr_r1_reg[27] [27]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[28] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[28]),\n .Q(\\app_addr_r1_reg[27] [28]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[29] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[29]),\n .Q(\\app_addr_r1_reg[27] [29]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[2] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[2]),\n .Q(\\app_addr_r1_reg[27] [2]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[3] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[3]),\n .Q(\\app_addr_r1_reg[27] [3]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[4] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[4]),\n .Q(\\app_addr_r1_reg[27] [4]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[5] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[5]),\n .Q(\\app_addr_r1_reg[27] [5]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[6] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[6]),\n .Q(\\app_addr_r1_reg[27] [6]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[7] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[7]),\n .Q(\\app_addr_r1_reg[27] [7]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[8] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[8]),\n .Q(\\app_addr_r1_reg[27] [8]),\n .R(areset_d1));\n FDRE \\axaddr_incr_reg[9] \n (.C(CLK),\n .CE(E),\n .D(axready_reg_0[9]),\n .Q(\\app_addr_r1_reg[27] [9]),\n .R(areset_d1));\n FDSE \\axlen_cnt_reg[0] \n (.C(CLK),\n .CE(E),\n .D(D[0]),\n .Q(Q[0]),\n .S(areset_d1));\n FDSE \\axlen_cnt_reg[1] \n (.C(CLK),\n .CE(E),\n .D(D[1]),\n .Q(Q[1]),\n .S(areset_d1));\n FDSE \\axlen_cnt_reg[2] \n (.C(CLK),\n .CE(E),\n .D(D[2]),\n .Q(Q[2]),\n .S(areset_d1));\n FDSE \\axlen_cnt_reg[3] \n (.C(CLK),\n .CE(E),\n .D(D[3]),\n .Q(Q[3]),\n .S(areset_d1));\n FDRE \\axlen_cnt_reg[4] \n (.C(CLK),\n .CE(E),\n .D(D[4]),\n .Q(Q[4]),\n .R(areset_d1));\n FDRE \\axlen_cnt_reg[5] \n (.C(CLK),\n .CE(E),\n .D(D[5]),\n .Q(Q[5]),\n .R(areset_d1));\n FDRE \\axlen_cnt_reg[6] \n (.C(CLK),\n .CE(E),\n .D(D[6]),\n .Q(Q[6]),\n .R(areset_d1));\n FDRE \\axlen_cnt_reg[7] \n (.C(CLK),\n .CE(E),\n .D(D[7]),\n .Q(Q[7]),\n .R(areset_d1));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_axi_mc_r_channel\n (rd_cmd_en,\n E,\n s_axi_rvalid,\n s_axi_rlast,\n out,\n s_axi_rid,\n s_axi_arvalid,\n s_axi_arready,\n axvalid,\n app_rdy,\n app_rd_data_valid,\n s_axi_rready,\n r_push,\n Q,\n CLK,\n in,\n areset_d1);\n output rd_cmd_en;\n output [0:0]E;\n output s_axi_rvalid;\n output s_axi_rlast;\n output [256:0]out;\n output [0:0]s_axi_rid;\n input s_axi_arvalid;\n input s_axi_arready;\n input axvalid;\n input app_rdy;\n input app_rd_data_valid;\n input s_axi_rready;\n input r_push;\n input [255:0]Q;\n input CLK;\n input [1:0]in;\n input areset_d1;\n\n wire CLK;\n wire [0:0]E;\n wire [255:0]Q;\n wire app_rd_data_valid;\n wire app_rdy;\n wire areset_d1;\n wire assert_rlast;\n wire axvalid;\n wire [1:0]in;\n wire [256:0]out;\n wire p_0_in;\n wire r_push;\n wire rd_cmd_en;\n wire rd_data_fifo_0_n_4;\n wire rd_data_fifo_0_n_5;\n wire s_axi_arready;\n wire s_axi_arvalid;\n wire [0:0]s_axi_rid;\n wire s_axi_rlast;\n wire s_axi_rready;\n wire s_axi_rvalid;\n (* RTL_KEEP = \"yes\" *) wire [1:0]state;\n wire tr_empty;\n wire [3:0]trans_buf_out_r1;\n wire \\trans_buf_out_r_reg_n_0_[0] ;\n wire [3:0]trans_out;\n wire transaction_fifo_0_n_0;\n wire transaction_fifo_0_n_2;\n wire transaction_fifo_0_n_3;\n wire transaction_fifo_0_n_7;\n wire transaction_fifo_0_n_8;\n\n (* KEEP = \"yes\" *) \n FDRE \\FSM_sequential_state_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data_fifo_0_n_5),\n .Q(state[0]),\n .R(areset_d1));\n (* KEEP = \"yes\" *) \n FDRE \\FSM_sequential_state_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data_fifo_0_n_4),\n .Q(state[1]),\n .R(areset_d1));\n ddr3_if_mig_7series_v4_0_axi_mc_fifo__parameterized0 rd_data_fifo_0\n (.CLK(CLK),\n .E(E),\n .\\FSM_sequential_state_reg[0] (rd_data_fifo_0_n_5),\n .\\FSM_sequential_state_reg[1] (rd_data_fifo_0_n_4),\n .Q(Q),\n .app_rd_data_valid(app_rd_data_valid),\n .app_rdy(app_rdy),\n .areset_d1(areset_d1),\n .axvalid(axvalid),\n .\\cnt_read_reg[5]_0 (transaction_fifo_0_n_2),\n .in0(state),\n .out(state),\n .p_0_in(p_0_in),\n .rd_cmd_en(rd_cmd_en),\n .s_axi_arready(s_axi_arready),\n .s_axi_arvalid(s_axi_arvalid),\n .s_axi_rready(s_axi_rready),\n .\\s_axi_rresp[1] (out),\n .s_axi_rvalid(s_axi_rvalid),\n .tr_empty(tr_empty),\n .\\trans_buf_out_r_reg[0] (\\trans_buf_out_r_reg_n_0_[0] ));\n LUT2 #(\n .INIT(4'h2)) \n s_axi_rlast_INST_0\n (.I0(assert_rlast),\n .I1(\\trans_buf_out_r_reg_n_0_[0] ),\n .O(s_axi_rlast));\n FDRE \\trans_buf_out_r1_reg[0] \n (.C(CLK),\n .CE(transaction_fifo_0_n_0),\n .D(trans_out[0]),\n .Q(trans_buf_out_r1[0]),\n .R(1'b0));\n FDRE \\trans_buf_out_r1_reg[2] \n (.C(CLK),\n .CE(transaction_fifo_0_n_0),\n .D(trans_out[2]),\n .Q(trans_buf_out_r1[2]),\n .R(1'b0));\n FDRE \\trans_buf_out_r1_reg[3] \n (.C(CLK),\n .CE(transaction_fifo_0_n_0),\n .D(trans_out[3]),\n .Q(trans_buf_out_r1[3]),\n .R(1'b0));\n FDRE \\trans_buf_out_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(transaction_fifo_0_n_3),\n .Q(\\trans_buf_out_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\trans_buf_out_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(transaction_fifo_0_n_7),\n .Q(assert_rlast),\n .R(1'b0));\n FDRE \\trans_buf_out_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(transaction_fifo_0_n_8),\n .Q(s_axi_rid),\n .R(1'b0));\n ddr3_if_mig_7series_v4_0_axi_mc_fifo__parameterized1 transaction_fifo_0\n (.CLK(CLK),\n .E(transaction_fifo_0_n_0),\n .Q({trans_buf_out_r1[3:2],trans_buf_out_r1[0]}),\n .\\RD_PRI_REG_STARVE.rd_starve_cnt_reg[8] (transaction_fifo_0_n_2),\n .areset_d1(areset_d1),\n .assert_rlast(assert_rlast),\n .in(in),\n .out(state),\n .p_0_in(p_0_in),\n .r_push(r_push),\n .s_axi_rid(s_axi_rid),\n .tr_empty(tr_empty),\n .\\trans_buf_out_r1_reg[3] ({trans_out[3:2],trans_out[0]}),\n .\\trans_buf_out_r_reg[0] (transaction_fifo_0_n_3),\n .\\trans_buf_out_r_reg[0]_0 (\\trans_buf_out_r_reg_n_0_[0] ),\n .\\trans_buf_out_r_reg[2] (transaction_fifo_0_n_7),\n .\\trans_buf_out_r_reg[3] (transaction_fifo_0_n_8));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_axi_mc_w_channel\n (wvalid_int,\n s_axi_wready,\n mc_app_wdf_wren_reg,\n app_wdf_mask,\n mc_app_wdf_mask_reg,\n D,\n app_wdf_data,\n mc_app_wdf_data_reg,\n \\mc_app_wdf_data_reg_reg[255]_0 ,\n areset_d1,\n CLK,\n app_wdf_rdy,\n \\RD_PRI_REG_STARVE.rnw_i_reg ,\n s_axi_wvalid,\n s_axi_wstrb,\n s_axi_wdata);\n output wvalid_int;\n output s_axi_wready;\n output mc_app_wdf_wren_reg;\n output [31:0]app_wdf_mask;\n output [31:0]mc_app_wdf_mask_reg;\n output [31:0]D;\n output [255:0]app_wdf_data;\n output [255:0]mc_app_wdf_data_reg;\n output [255:0]\\mc_app_wdf_data_reg_reg[255]_0 ;\n input areset_d1;\n input CLK;\n input app_wdf_rdy;\n input \\RD_PRI_REG_STARVE.rnw_i_reg ;\n input s_axi_wvalid;\n input [31:0]s_axi_wstrb;\n input [255:0]s_axi_wdata;\n\n wire CLK;\n wire [31:0]D;\n wire \\RD_PRI_REG_STARVE.rnw_i_reg ;\n wire [255:0]app_wdf_data;\n wire [31:0]app_wdf_mask;\n wire app_wdf_rdy;\n wire areset_d1;\n wire [255:0]mc_app_wdf_data_reg;\n wire [255:0]\\mc_app_wdf_data_reg_reg[255]_0 ;\n wire [31:0]mc_app_wdf_mask_reg;\n wire mc_app_wdf_wren_reg;\n wire [255:0]s_axi_wdata;\n wire s_axi_wready;\n wire [31:0]s_axi_wstrb;\n wire s_axi_wvalid;\n wire valid;\n wire [255:0]wdf_data;\n wire [31:0]wdf_mask;\n wire wready_i_1_n_0;\n wire wready_reg_rep__0_n_0;\n wire wready_reg_rep__1_n_0;\n wire wready_reg_rep__2_n_0;\n wire wready_reg_rep_n_0;\n wire wready_rep__0_i_1_n_0;\n wire wready_rep__1_i_1_n_0;\n wire wready_rep__2_i_1_n_0;\n wire wready_rep_i_1_n_0;\n wire wvalid_int;\n\n (* SOFT_HLUTNM = \"soft_lutpair1485\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[0]_i_1 \n (.I0(s_axi_wdata[0]),\n .I1(s_axi_wready),\n .I2(wdf_data[0]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[0]),\n .O(app_wdf_data[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1297\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[100]_i_1 \n (.I0(s_axi_wdata[100]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[100]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[100]),\n .O(app_wdf_data[100]));\n (* SOFT_HLUTNM = \"soft_lutpair1298\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[101]_i_1 \n (.I0(s_axi_wdata[101]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[101]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[101]),\n .O(app_wdf_data[101]));\n (* SOFT_HLUTNM = \"soft_lutpair1299\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[102]_i_1 \n (.I0(s_axi_wdata[102]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[102]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[102]),\n .O(app_wdf_data[102]));\n (* SOFT_HLUTNM = \"soft_lutpair1300\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[103]_i_1 \n (.I0(s_axi_wdata[103]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[103]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[103]),\n .O(app_wdf_data[103]));\n (* SOFT_HLUTNM = \"soft_lutpair1301\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[104]_i_1 \n (.I0(s_axi_wdata[104]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[104]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[104]),\n .O(app_wdf_data[104]));\n (* SOFT_HLUTNM = \"soft_lutpair1302\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[105]_i_1 \n (.I0(s_axi_wdata[105]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[105]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[105]),\n .O(app_wdf_data[105]));\n (* SOFT_HLUTNM = \"soft_lutpair1303\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[106]_i_1 \n (.I0(s_axi_wdata[106]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[106]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[106]),\n .O(app_wdf_data[106]));\n (* SOFT_HLUTNM = \"soft_lutpair1304\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[107]_i_1 \n (.I0(s_axi_wdata[107]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[107]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[107]),\n .O(app_wdf_data[107]));\n (* SOFT_HLUTNM = \"soft_lutpair1305\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[108]_i_1 \n (.I0(s_axi_wdata[108]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[108]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[108]),\n .O(app_wdf_data[108]));\n (* SOFT_HLUTNM = \"soft_lutpair1306\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[109]_i_1 \n (.I0(s_axi_wdata[109]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[109]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[109]),\n .O(app_wdf_data[109]));\n (* SOFT_HLUTNM = \"soft_lutpair1207\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[10]_i_1 \n (.I0(s_axi_wdata[10]),\n .I1(s_axi_wready),\n .I2(wdf_data[10]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[10]),\n .O(app_wdf_data[10]));\n (* SOFT_HLUTNM = \"soft_lutpair1307\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[110]_i_1 \n (.I0(s_axi_wdata[110]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[110]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[110]),\n .O(app_wdf_data[110]));\n (* SOFT_HLUTNM = \"soft_lutpair1308\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[111]_i_1 \n (.I0(s_axi_wdata[111]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[111]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[111]),\n .O(app_wdf_data[111]));\n (* SOFT_HLUTNM = \"soft_lutpair1309\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[112]_i_1 \n (.I0(s_axi_wdata[112]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[112]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[112]),\n .O(app_wdf_data[112]));\n (* SOFT_HLUTNM = \"soft_lutpair1310\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[113]_i_1 \n (.I0(s_axi_wdata[113]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[113]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[113]),\n .O(app_wdf_data[113]));\n (* SOFT_HLUTNM = \"soft_lutpair1311\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[114]_i_1 \n (.I0(s_axi_wdata[114]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[114]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[114]),\n .O(app_wdf_data[114]));\n (* SOFT_HLUTNM = \"soft_lutpair1312\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[115]_i_1 \n (.I0(s_axi_wdata[115]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[115]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[115]),\n .O(app_wdf_data[115]));\n (* SOFT_HLUTNM = \"soft_lutpair1313\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[116]_i_1 \n (.I0(s_axi_wdata[116]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[116]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[116]),\n .O(app_wdf_data[116]));\n (* SOFT_HLUTNM = \"soft_lutpair1314\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[117]_i_1 \n (.I0(s_axi_wdata[117]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[117]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[117]),\n .O(app_wdf_data[117]));\n (* SOFT_HLUTNM = \"soft_lutpair1315\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[118]_i_1 \n (.I0(s_axi_wdata[118]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[118]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[118]),\n .O(app_wdf_data[118]));\n (* SOFT_HLUTNM = \"soft_lutpair1316\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[119]_i_1 \n (.I0(s_axi_wdata[119]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[119]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[119]),\n .O(app_wdf_data[119]));\n (* SOFT_HLUTNM = \"soft_lutpair1208\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[11]_i_1 \n (.I0(s_axi_wdata[11]),\n .I1(s_axi_wready),\n .I2(wdf_data[11]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[11]),\n .O(app_wdf_data[11]));\n (* SOFT_HLUTNM = \"soft_lutpair1317\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[120]_i_1 \n (.I0(s_axi_wdata[120]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[120]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[120]),\n .O(app_wdf_data[120]));\n (* SOFT_HLUTNM = \"soft_lutpair1318\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[121]_i_1 \n (.I0(s_axi_wdata[121]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[121]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[121]),\n .O(app_wdf_data[121]));\n (* SOFT_HLUTNM = \"soft_lutpair1319\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[122]_i_1 \n (.I0(s_axi_wdata[122]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[122]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[122]),\n .O(app_wdf_data[122]));\n (* SOFT_HLUTNM = \"soft_lutpair1320\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[123]_i_1 \n (.I0(s_axi_wdata[123]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[123]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[123]),\n .O(app_wdf_data[123]));\n (* SOFT_HLUTNM = \"soft_lutpair1321\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[124]_i_1 \n (.I0(s_axi_wdata[124]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[124]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[124]),\n .O(app_wdf_data[124]));\n (* SOFT_HLUTNM = \"soft_lutpair1322\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[125]_i_1 \n (.I0(s_axi_wdata[125]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[125]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[125]),\n .O(app_wdf_data[125]));\n (* SOFT_HLUTNM = \"soft_lutpair1323\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[126]_i_1 \n (.I0(s_axi_wdata[126]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[126]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[126]),\n .O(app_wdf_data[126]));\n (* SOFT_HLUTNM = \"soft_lutpair1324\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[127]_i_1 \n (.I0(s_axi_wdata[127]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[127]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[127]),\n .O(app_wdf_data[127]));\n (* SOFT_HLUTNM = \"soft_lutpair1325\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[128]_i_1 \n (.I0(s_axi_wdata[128]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[128]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[128]),\n .O(app_wdf_data[128]));\n (* SOFT_HLUTNM = \"soft_lutpair1326\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[129]_i_1 \n (.I0(s_axi_wdata[129]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[129]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[129]),\n .O(app_wdf_data[129]));\n (* SOFT_HLUTNM = \"soft_lutpair1209\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[12]_i_1 \n (.I0(s_axi_wdata[12]),\n .I1(s_axi_wready),\n .I2(wdf_data[12]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[12]),\n .O(app_wdf_data[12]));\n (* SOFT_HLUTNM = \"soft_lutpair1327\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[130]_i_1 \n (.I0(s_axi_wdata[130]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[130]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[130]),\n .O(app_wdf_data[130]));\n (* SOFT_HLUTNM = \"soft_lutpair1328\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[131]_i_1 \n (.I0(s_axi_wdata[131]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[131]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[131]),\n .O(app_wdf_data[131]));\n (* SOFT_HLUTNM = \"soft_lutpair1329\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[132]_i_1 \n (.I0(s_axi_wdata[132]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[132]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[132]),\n .O(app_wdf_data[132]));\n (* SOFT_HLUTNM = \"soft_lutpair1330\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[133]_i_1 \n (.I0(s_axi_wdata[133]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[133]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[133]),\n .O(app_wdf_data[133]));\n (* SOFT_HLUTNM = \"soft_lutpair1331\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[134]_i_1 \n (.I0(s_axi_wdata[134]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[134]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[134]),\n .O(app_wdf_data[134]));\n (* SOFT_HLUTNM = \"soft_lutpair1332\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[135]_i_1 \n (.I0(s_axi_wdata[135]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[135]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[135]),\n .O(app_wdf_data[135]));\n (* SOFT_HLUTNM = \"soft_lutpair1333\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[136]_i_1 \n (.I0(s_axi_wdata[136]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[136]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[136]),\n .O(app_wdf_data[136]));\n (* SOFT_HLUTNM = \"soft_lutpair1334\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[137]_i_1 \n (.I0(s_axi_wdata[137]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[137]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[137]),\n .O(app_wdf_data[137]));\n (* SOFT_HLUTNM = \"soft_lutpair1335\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[138]_i_1 \n (.I0(s_axi_wdata[138]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[138]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[138]),\n .O(app_wdf_data[138]));\n (* SOFT_HLUTNM = \"soft_lutpair1336\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[139]_i_1 \n (.I0(s_axi_wdata[139]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[139]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[139]),\n .O(app_wdf_data[139]));\n (* SOFT_HLUTNM = \"soft_lutpair1210\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[13]_i_1 \n (.I0(s_axi_wdata[13]),\n .I1(s_axi_wready),\n .I2(wdf_data[13]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[13]),\n .O(app_wdf_data[13]));\n (* SOFT_HLUTNM = \"soft_lutpair1337\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[140]_i_1 \n (.I0(s_axi_wdata[140]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[140]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[140]),\n .O(app_wdf_data[140]));\n (* SOFT_HLUTNM = \"soft_lutpair1338\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[141]_i_1 \n (.I0(s_axi_wdata[141]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[141]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[141]),\n .O(app_wdf_data[141]));\n (* SOFT_HLUTNM = \"soft_lutpair1339\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[142]_i_1 \n (.I0(s_axi_wdata[142]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[142]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[142]),\n .O(app_wdf_data[142]));\n (* SOFT_HLUTNM = \"soft_lutpair1340\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[143]_i_1 \n (.I0(s_axi_wdata[143]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[143]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[143]),\n .O(app_wdf_data[143]));\n (* SOFT_HLUTNM = \"soft_lutpair1341\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[144]_i_1 \n (.I0(s_axi_wdata[144]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[144]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[144]),\n .O(app_wdf_data[144]));\n (* SOFT_HLUTNM = \"soft_lutpair1342\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[145]_i_1 \n (.I0(s_axi_wdata[145]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[145]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[145]),\n .O(app_wdf_data[145]));\n (* SOFT_HLUTNM = \"soft_lutpair1343\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[146]_i_1 \n (.I0(s_axi_wdata[146]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[146]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[146]),\n .O(app_wdf_data[146]));\n (* SOFT_HLUTNM = \"soft_lutpair1344\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[147]_i_1 \n (.I0(s_axi_wdata[147]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[147]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[147]),\n .O(app_wdf_data[147]));\n (* SOFT_HLUTNM = \"soft_lutpair1345\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[148]_i_1 \n (.I0(s_axi_wdata[148]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[148]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[148]),\n .O(app_wdf_data[148]));\n (* SOFT_HLUTNM = \"soft_lutpair1346\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[149]_i_1 \n (.I0(s_axi_wdata[149]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[149]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[149]),\n .O(app_wdf_data[149]));\n (* SOFT_HLUTNM = \"soft_lutpair1211\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[14]_i_1 \n (.I0(s_axi_wdata[14]),\n .I1(s_axi_wready),\n .I2(wdf_data[14]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[14]),\n .O(app_wdf_data[14]));\n (* SOFT_HLUTNM = \"soft_lutpair1347\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[150]_i_1 \n (.I0(s_axi_wdata[150]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[150]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[150]),\n .O(app_wdf_data[150]));\n (* SOFT_HLUTNM = \"soft_lutpair1348\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[151]_i_1 \n (.I0(s_axi_wdata[151]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[151]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[151]),\n .O(app_wdf_data[151]));\n (* SOFT_HLUTNM = \"soft_lutpair1349\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[152]_i_1 \n (.I0(s_axi_wdata[152]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[152]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[152]),\n .O(app_wdf_data[152]));\n (* SOFT_HLUTNM = \"soft_lutpair1350\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[153]_i_1 \n (.I0(s_axi_wdata[153]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[153]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[153]),\n .O(app_wdf_data[153]));\n (* SOFT_HLUTNM = \"soft_lutpair1351\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[154]_i_1 \n (.I0(s_axi_wdata[154]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[154]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[154]),\n .O(app_wdf_data[154]));\n (* SOFT_HLUTNM = \"soft_lutpair1352\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[155]_i_1 \n (.I0(s_axi_wdata[155]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[155]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[155]),\n .O(app_wdf_data[155]));\n (* SOFT_HLUTNM = \"soft_lutpair1353\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[156]_i_1 \n (.I0(s_axi_wdata[156]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[156]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[156]),\n .O(app_wdf_data[156]));\n (* SOFT_HLUTNM = \"soft_lutpair1354\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[157]_i_1 \n (.I0(s_axi_wdata[157]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[157]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[157]),\n .O(app_wdf_data[157]));\n (* SOFT_HLUTNM = \"soft_lutpair1355\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[158]_i_1 \n (.I0(s_axi_wdata[158]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[158]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[158]),\n .O(app_wdf_data[158]));\n (* SOFT_HLUTNM = \"soft_lutpair1356\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[159]_i_1 \n (.I0(s_axi_wdata[159]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[159]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[159]),\n .O(app_wdf_data[159]));\n (* SOFT_HLUTNM = \"soft_lutpair1212\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[15]_i_1 \n (.I0(s_axi_wdata[15]),\n .I1(s_axi_wready),\n .I2(wdf_data[15]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[15]),\n .O(app_wdf_data[15]));\n (* SOFT_HLUTNM = \"soft_lutpair1357\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[160]_i_1 \n (.I0(s_axi_wdata[160]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[160]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[160]),\n .O(app_wdf_data[160]));\n (* SOFT_HLUTNM = \"soft_lutpair1358\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[161]_i_1 \n (.I0(s_axi_wdata[161]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[161]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[161]),\n .O(app_wdf_data[161]));\n (* SOFT_HLUTNM = \"soft_lutpair1359\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[162]_i_1 \n (.I0(s_axi_wdata[162]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[162]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[162]),\n .O(app_wdf_data[162]));\n (* SOFT_HLUTNM = \"soft_lutpair1360\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[163]_i_1 \n (.I0(s_axi_wdata[163]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[163]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[163]),\n .O(app_wdf_data[163]));\n (* SOFT_HLUTNM = \"soft_lutpair1361\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[164]_i_1 \n (.I0(s_axi_wdata[164]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[164]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[164]),\n .O(app_wdf_data[164]));\n (* SOFT_HLUTNM = \"soft_lutpair1362\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[165]_i_1 \n (.I0(s_axi_wdata[165]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[165]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[165]),\n .O(app_wdf_data[165]));\n (* SOFT_HLUTNM = \"soft_lutpair1363\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[166]_i_1 \n (.I0(s_axi_wdata[166]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[166]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[166]),\n .O(app_wdf_data[166]));\n (* SOFT_HLUTNM = \"soft_lutpair1364\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[167]_i_1 \n (.I0(s_axi_wdata[167]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[167]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[167]),\n .O(app_wdf_data[167]));\n (* SOFT_HLUTNM = \"soft_lutpair1365\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[168]_i_1 \n (.I0(s_axi_wdata[168]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[168]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[168]),\n .O(app_wdf_data[168]));\n (* SOFT_HLUTNM = \"soft_lutpair1366\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[169]_i_1 \n (.I0(s_axi_wdata[169]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[169]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[169]),\n .O(app_wdf_data[169]));\n (* SOFT_HLUTNM = \"soft_lutpair1213\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[16]_i_1 \n (.I0(s_axi_wdata[16]),\n .I1(s_axi_wready),\n .I2(wdf_data[16]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[16]),\n .O(app_wdf_data[16]));\n (* SOFT_HLUTNM = \"soft_lutpair1367\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[170]_i_1 \n (.I0(s_axi_wdata[170]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[170]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[170]),\n .O(app_wdf_data[170]));\n (* SOFT_HLUTNM = \"soft_lutpair1368\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[171]_i_1 \n (.I0(s_axi_wdata[171]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[171]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[171]),\n .O(app_wdf_data[171]));\n (* SOFT_HLUTNM = \"soft_lutpair1369\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[172]_i_1 \n (.I0(s_axi_wdata[172]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[172]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[172]),\n .O(app_wdf_data[172]));\n (* SOFT_HLUTNM = \"soft_lutpair1370\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[173]_i_1 \n (.I0(s_axi_wdata[173]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[173]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[173]),\n .O(app_wdf_data[173]));\n (* SOFT_HLUTNM = \"soft_lutpair1371\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[174]_i_1 \n (.I0(s_axi_wdata[174]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[174]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[174]),\n .O(app_wdf_data[174]));\n (* SOFT_HLUTNM = \"soft_lutpair1372\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[175]_i_1 \n (.I0(s_axi_wdata[175]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[175]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[175]),\n .O(app_wdf_data[175]));\n (* SOFT_HLUTNM = \"soft_lutpair1373\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[176]_i_1 \n (.I0(s_axi_wdata[176]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[176]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[176]),\n .O(app_wdf_data[176]));\n (* SOFT_HLUTNM = \"soft_lutpair1374\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[177]_i_1 \n (.I0(s_axi_wdata[177]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[177]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[177]),\n .O(app_wdf_data[177]));\n (* SOFT_HLUTNM = \"soft_lutpair1375\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[178]_i_1 \n (.I0(s_axi_wdata[178]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[178]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[178]),\n .O(app_wdf_data[178]));\n (* SOFT_HLUTNM = \"soft_lutpair1376\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[179]_i_1 \n (.I0(s_axi_wdata[179]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[179]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[179]),\n .O(app_wdf_data[179]));\n (* SOFT_HLUTNM = \"soft_lutpair1214\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[17]_i_1 \n (.I0(s_axi_wdata[17]),\n .I1(s_axi_wready),\n .I2(wdf_data[17]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[17]),\n .O(app_wdf_data[17]));\n (* SOFT_HLUTNM = \"soft_lutpair1377\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[180]_i_1 \n (.I0(s_axi_wdata[180]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[180]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[180]),\n .O(app_wdf_data[180]));\n (* SOFT_HLUTNM = \"soft_lutpair1378\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[181]_i_1 \n (.I0(s_axi_wdata[181]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[181]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[181]),\n .O(app_wdf_data[181]));\n (* SOFT_HLUTNM = \"soft_lutpair1379\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[182]_i_1 \n (.I0(s_axi_wdata[182]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[182]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[182]),\n .O(app_wdf_data[182]));\n (* SOFT_HLUTNM = \"soft_lutpair1380\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[183]_i_1 \n (.I0(s_axi_wdata[183]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[183]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[183]),\n .O(app_wdf_data[183]));\n (* SOFT_HLUTNM = \"soft_lutpair1381\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[184]_i_1 \n (.I0(s_axi_wdata[184]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[184]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[184]),\n .O(app_wdf_data[184]));\n (* SOFT_HLUTNM = \"soft_lutpair1382\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[185]_i_1 \n (.I0(s_axi_wdata[185]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[185]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[185]),\n .O(app_wdf_data[185]));\n (* SOFT_HLUTNM = \"soft_lutpair1383\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[186]_i_1 \n (.I0(s_axi_wdata[186]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[186]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[186]),\n .O(app_wdf_data[186]));\n (* SOFT_HLUTNM = \"soft_lutpair1384\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[187]_i_1 \n (.I0(s_axi_wdata[187]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[187]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[187]),\n .O(app_wdf_data[187]));\n (* SOFT_HLUTNM = \"soft_lutpair1385\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[188]_i_1 \n (.I0(s_axi_wdata[188]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[188]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[188]),\n .O(app_wdf_data[188]));\n (* SOFT_HLUTNM = \"soft_lutpair1386\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[189]_i_1 \n (.I0(s_axi_wdata[189]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[189]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[189]),\n .O(app_wdf_data[189]));\n (* SOFT_HLUTNM = \"soft_lutpair1215\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[18]_i_1 \n (.I0(s_axi_wdata[18]),\n .I1(s_axi_wready),\n .I2(wdf_data[18]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[18]),\n .O(app_wdf_data[18]));\n (* SOFT_HLUTNM = \"soft_lutpair1387\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[190]_i_1 \n (.I0(s_axi_wdata[190]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[190]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[190]),\n .O(app_wdf_data[190]));\n (* SOFT_HLUTNM = \"soft_lutpair1388\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[191]_i_1 \n (.I0(s_axi_wdata[191]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[191]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[191]),\n .O(app_wdf_data[191]));\n (* SOFT_HLUTNM = \"soft_lutpair1389\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[192]_i_1 \n (.I0(s_axi_wdata[192]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[192]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[192]),\n .O(app_wdf_data[192]));\n (* SOFT_HLUTNM = \"soft_lutpair1390\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[193]_i_1 \n (.I0(s_axi_wdata[193]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[193]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[193]),\n .O(app_wdf_data[193]));\n (* SOFT_HLUTNM = \"soft_lutpair1391\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[194]_i_1 \n (.I0(s_axi_wdata[194]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[194]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[194]),\n .O(app_wdf_data[194]));\n (* SOFT_HLUTNM = \"soft_lutpair1392\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[195]_i_1 \n (.I0(s_axi_wdata[195]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[195]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[195]),\n .O(app_wdf_data[195]));\n (* SOFT_HLUTNM = \"soft_lutpair1393\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[196]_i_1 \n (.I0(s_axi_wdata[196]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[196]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[196]),\n .O(app_wdf_data[196]));\n (* SOFT_HLUTNM = \"soft_lutpair1394\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[197]_i_1 \n (.I0(s_axi_wdata[197]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[197]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[197]),\n .O(app_wdf_data[197]));\n (* SOFT_HLUTNM = \"soft_lutpair1395\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[198]_i_1 \n (.I0(s_axi_wdata[198]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[198]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[198]),\n .O(app_wdf_data[198]));\n (* SOFT_HLUTNM = \"soft_lutpair1396\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[199]_i_1 \n (.I0(s_axi_wdata[199]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[199]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[199]),\n .O(app_wdf_data[199]));\n (* SOFT_HLUTNM = \"soft_lutpair1216\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[19]_i_1 \n (.I0(s_axi_wdata[19]),\n .I1(s_axi_wready),\n .I2(wdf_data[19]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[19]),\n .O(app_wdf_data[19]));\n (* SOFT_HLUTNM = \"soft_lutpair1198\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[1]_i_1 \n (.I0(s_axi_wdata[1]),\n .I1(s_axi_wready),\n .I2(wdf_data[1]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[1]),\n .O(app_wdf_data[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1397\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[200]_i_1 \n (.I0(s_axi_wdata[200]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[200]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[200]),\n .O(app_wdf_data[200]));\n (* SOFT_HLUTNM = \"soft_lutpair1398\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[201]_i_1 \n (.I0(s_axi_wdata[201]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[201]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[201]),\n .O(app_wdf_data[201]));\n (* SOFT_HLUTNM = \"soft_lutpair1399\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[202]_i_1 \n (.I0(s_axi_wdata[202]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[202]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[202]),\n .O(app_wdf_data[202]));\n (* SOFT_HLUTNM = \"soft_lutpair1400\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[203]_i_1 \n (.I0(s_axi_wdata[203]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[203]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[203]),\n .O(app_wdf_data[203]));\n (* SOFT_HLUTNM = \"soft_lutpair1401\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[204]_i_1 \n (.I0(s_axi_wdata[204]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[204]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[204]),\n .O(app_wdf_data[204]));\n (* SOFT_HLUTNM = \"soft_lutpair1402\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[205]_i_1 \n (.I0(s_axi_wdata[205]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[205]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[205]),\n .O(app_wdf_data[205]));\n (* SOFT_HLUTNM = \"soft_lutpair1403\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[206]_i_1 \n (.I0(s_axi_wdata[206]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[206]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[206]),\n .O(app_wdf_data[206]));\n (* SOFT_HLUTNM = \"soft_lutpair1404\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[207]_i_1 \n (.I0(s_axi_wdata[207]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[207]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[207]),\n .O(app_wdf_data[207]));\n (* SOFT_HLUTNM = \"soft_lutpair1405\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[208]_i_1 \n (.I0(s_axi_wdata[208]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[208]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[208]),\n .O(app_wdf_data[208]));\n (* SOFT_HLUTNM = \"soft_lutpair1406\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[209]_i_1 \n (.I0(s_axi_wdata[209]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[209]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[209]),\n .O(app_wdf_data[209]));\n (* SOFT_HLUTNM = \"soft_lutpair1217\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[20]_i_1 \n (.I0(s_axi_wdata[20]),\n .I1(s_axi_wready),\n .I2(wdf_data[20]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[20]),\n .O(app_wdf_data[20]));\n (* SOFT_HLUTNM = \"soft_lutpair1407\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[210]_i_1 \n (.I0(s_axi_wdata[210]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[210]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[210]),\n .O(app_wdf_data[210]));\n (* SOFT_HLUTNM = \"soft_lutpair1408\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[211]_i_1 \n (.I0(s_axi_wdata[211]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[211]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[211]),\n .O(app_wdf_data[211]));\n (* SOFT_HLUTNM = \"soft_lutpair1409\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[212]_i_1 \n (.I0(s_axi_wdata[212]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[212]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[212]),\n .O(app_wdf_data[212]));\n (* SOFT_HLUTNM = \"soft_lutpair1410\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[213]_i_1 \n (.I0(s_axi_wdata[213]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[213]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[213]),\n .O(app_wdf_data[213]));\n (* SOFT_HLUTNM = \"soft_lutpair1411\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[214]_i_1 \n (.I0(s_axi_wdata[214]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[214]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[214]),\n .O(app_wdf_data[214]));\n (* SOFT_HLUTNM = \"soft_lutpair1412\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[215]_i_1 \n (.I0(s_axi_wdata[215]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[215]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[215]),\n .O(app_wdf_data[215]));\n (* SOFT_HLUTNM = \"soft_lutpair1413\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[216]_i_1 \n (.I0(s_axi_wdata[216]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[216]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[216]),\n .O(app_wdf_data[216]));\n (* SOFT_HLUTNM = \"soft_lutpair1414\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[217]_i_1 \n (.I0(s_axi_wdata[217]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[217]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[217]),\n .O(app_wdf_data[217]));\n (* SOFT_HLUTNM = \"soft_lutpair1415\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[218]_i_1 \n (.I0(s_axi_wdata[218]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[218]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[218]),\n .O(app_wdf_data[218]));\n (* SOFT_HLUTNM = \"soft_lutpair1416\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[219]_i_1 \n (.I0(s_axi_wdata[219]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[219]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[219]),\n .O(app_wdf_data[219]));\n (* SOFT_HLUTNM = \"soft_lutpair1218\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[21]_i_1 \n (.I0(s_axi_wdata[21]),\n .I1(s_axi_wready),\n .I2(wdf_data[21]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[21]),\n .O(app_wdf_data[21]));\n (* SOFT_HLUTNM = \"soft_lutpair1417\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[220]_i_1 \n (.I0(s_axi_wdata[220]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[220]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[220]),\n .O(app_wdf_data[220]));\n (* SOFT_HLUTNM = \"soft_lutpair1418\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[221]_i_1 \n (.I0(s_axi_wdata[221]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[221]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[221]),\n .O(app_wdf_data[221]));\n (* SOFT_HLUTNM = \"soft_lutpair1419\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[222]_i_1 \n (.I0(s_axi_wdata[222]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[222]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[222]),\n .O(app_wdf_data[222]));\n (* SOFT_HLUTNM = \"soft_lutpair1420\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[223]_i_1 \n (.I0(s_axi_wdata[223]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[223]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[223]),\n .O(app_wdf_data[223]));\n (* SOFT_HLUTNM = \"soft_lutpair1421\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[224]_i_1 \n (.I0(s_axi_wdata[224]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[224]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[224]),\n .O(app_wdf_data[224]));\n (* SOFT_HLUTNM = \"soft_lutpair1422\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[225]_i_1 \n (.I0(s_axi_wdata[225]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[225]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[225]),\n .O(app_wdf_data[225]));\n (* SOFT_HLUTNM = \"soft_lutpair1423\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[226]_i_1 \n (.I0(s_axi_wdata[226]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[226]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[226]),\n .O(app_wdf_data[226]));\n (* SOFT_HLUTNM = \"soft_lutpair1424\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[227]_i_1 \n (.I0(s_axi_wdata[227]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[227]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[227]),\n .O(app_wdf_data[227]));\n (* SOFT_HLUTNM = \"soft_lutpair1425\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[228]_i_1 \n (.I0(s_axi_wdata[228]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[228]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[228]),\n .O(app_wdf_data[228]));\n (* SOFT_HLUTNM = \"soft_lutpair1426\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[229]_i_1 \n (.I0(s_axi_wdata[229]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[229]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[229]),\n .O(app_wdf_data[229]));\n (* SOFT_HLUTNM = \"soft_lutpair1219\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[22]_i_1 \n (.I0(s_axi_wdata[22]),\n .I1(s_axi_wready),\n .I2(wdf_data[22]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[22]),\n .O(app_wdf_data[22]));\n (* SOFT_HLUTNM = \"soft_lutpair1427\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[230]_i_1 \n (.I0(s_axi_wdata[230]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[230]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[230]),\n .O(app_wdf_data[230]));\n (* SOFT_HLUTNM = \"soft_lutpair1428\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[231]_i_1 \n (.I0(s_axi_wdata[231]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[231]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[231]),\n .O(app_wdf_data[231]));\n (* SOFT_HLUTNM = \"soft_lutpair1429\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[232]_i_1 \n (.I0(s_axi_wdata[232]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[232]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[232]),\n .O(app_wdf_data[232]));\n (* SOFT_HLUTNM = \"soft_lutpair1430\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[233]_i_1 \n (.I0(s_axi_wdata[233]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[233]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[233]),\n .O(app_wdf_data[233]));\n (* SOFT_HLUTNM = \"soft_lutpair1431\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[234]_i_1 \n (.I0(s_axi_wdata[234]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[234]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[234]),\n .O(app_wdf_data[234]));\n (* SOFT_HLUTNM = \"soft_lutpair1432\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[235]_i_1 \n (.I0(s_axi_wdata[235]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[235]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[235]),\n .O(app_wdf_data[235]));\n (* SOFT_HLUTNM = \"soft_lutpair1433\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[236]_i_1 \n (.I0(s_axi_wdata[236]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[236]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[236]),\n .O(app_wdf_data[236]));\n (* SOFT_HLUTNM = \"soft_lutpair1434\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[237]_i_1 \n (.I0(s_axi_wdata[237]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[237]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[237]),\n .O(app_wdf_data[237]));\n (* SOFT_HLUTNM = \"soft_lutpair1435\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[238]_i_1 \n (.I0(s_axi_wdata[238]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[238]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[238]),\n .O(app_wdf_data[238]));\n (* SOFT_HLUTNM = \"soft_lutpair1436\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[239]_i_1 \n (.I0(s_axi_wdata[239]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[239]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[239]),\n .O(app_wdf_data[239]));\n (* SOFT_HLUTNM = \"soft_lutpair1220\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[23]_i_1 \n (.I0(s_axi_wdata[23]),\n .I1(s_axi_wready),\n .I2(wdf_data[23]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[23]),\n .O(app_wdf_data[23]));\n (* SOFT_HLUTNM = \"soft_lutpair1437\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[240]_i_1 \n (.I0(s_axi_wdata[240]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[240]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[240]),\n .O(app_wdf_data[240]));\n (* SOFT_HLUTNM = \"soft_lutpair1438\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[241]_i_1 \n (.I0(s_axi_wdata[241]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[241]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[241]),\n .O(app_wdf_data[241]));\n (* SOFT_HLUTNM = \"soft_lutpair1439\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[242]_i_1 \n (.I0(s_axi_wdata[242]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[242]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[242]),\n .O(app_wdf_data[242]));\n (* SOFT_HLUTNM = \"soft_lutpair1440\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[243]_i_1 \n (.I0(s_axi_wdata[243]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[243]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[243]),\n .O(app_wdf_data[243]));\n (* SOFT_HLUTNM = \"soft_lutpair1441\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[244]_i_1 \n (.I0(s_axi_wdata[244]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[244]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[244]),\n .O(app_wdf_data[244]));\n (* SOFT_HLUTNM = \"soft_lutpair1442\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[245]_i_1 \n (.I0(s_axi_wdata[245]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[245]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[245]),\n .O(app_wdf_data[245]));\n (* SOFT_HLUTNM = \"soft_lutpair1443\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[246]_i_1 \n (.I0(s_axi_wdata[246]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[246]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[246]),\n .O(app_wdf_data[246]));\n (* SOFT_HLUTNM = \"soft_lutpair1444\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[247]_i_1 \n (.I0(s_axi_wdata[247]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[247]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[247]),\n .O(app_wdf_data[247]));\n (* SOFT_HLUTNM = \"soft_lutpair1445\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[248]_i_1 \n (.I0(s_axi_wdata[248]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[248]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[248]),\n .O(app_wdf_data[248]));\n (* SOFT_HLUTNM = \"soft_lutpair1446\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[249]_i_1 \n (.I0(s_axi_wdata[249]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[249]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[249]),\n .O(app_wdf_data[249]));\n (* SOFT_HLUTNM = \"soft_lutpair1221\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[24]_i_1 \n (.I0(s_axi_wdata[24]),\n .I1(s_axi_wready),\n .I2(wdf_data[24]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[24]),\n .O(app_wdf_data[24]));\n (* SOFT_HLUTNM = \"soft_lutpair1447\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[250]_i_1 \n (.I0(s_axi_wdata[250]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[250]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[250]),\n .O(app_wdf_data[250]));\n (* SOFT_HLUTNM = \"soft_lutpair1448\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[251]_i_1 \n (.I0(s_axi_wdata[251]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[251]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[251]),\n .O(app_wdf_data[251]));\n (* SOFT_HLUTNM = \"soft_lutpair1449\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[252]_i_1 \n (.I0(s_axi_wdata[252]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[252]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[252]),\n .O(app_wdf_data[252]));\n (* SOFT_HLUTNM = \"soft_lutpair1450\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[253]_i_1 \n (.I0(s_axi_wdata[253]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[253]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[253]),\n .O(app_wdf_data[253]));\n (* SOFT_HLUTNM = \"soft_lutpair1451\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[254]_i_1 \n (.I0(s_axi_wdata[254]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[254]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[254]),\n .O(app_wdf_data[254]));\n (* SOFT_HLUTNM = \"soft_lutpair1452\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[255]_i_1 \n (.I0(s_axi_wdata[255]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[255]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[255]),\n .O(app_wdf_data[255]));\n (* SOFT_HLUTNM = \"soft_lutpair1222\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[25]_i_1 \n (.I0(s_axi_wdata[25]),\n .I1(s_axi_wready),\n .I2(wdf_data[25]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[25]),\n .O(app_wdf_data[25]));\n (* SOFT_HLUTNM = \"soft_lutpair1223\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[26]_i_1 \n (.I0(s_axi_wdata[26]),\n .I1(s_axi_wready),\n .I2(wdf_data[26]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[26]),\n .O(app_wdf_data[26]));\n (* SOFT_HLUTNM = \"soft_lutpair1224\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[27]_i_1 \n (.I0(s_axi_wdata[27]),\n .I1(s_axi_wready),\n .I2(wdf_data[27]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[27]),\n .O(app_wdf_data[27]));\n (* SOFT_HLUTNM = \"soft_lutpair1225\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[28]_i_1 \n (.I0(s_axi_wdata[28]),\n .I1(s_axi_wready),\n .I2(wdf_data[28]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[28]),\n .O(app_wdf_data[28]));\n (* SOFT_HLUTNM = \"soft_lutpair1226\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[29]_i_1 \n (.I0(s_axi_wdata[29]),\n .I1(s_axi_wready),\n .I2(wdf_data[29]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[29]),\n .O(app_wdf_data[29]));\n (* SOFT_HLUTNM = \"soft_lutpair1199\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[2]_i_1 \n (.I0(s_axi_wdata[2]),\n .I1(s_axi_wready),\n .I2(wdf_data[2]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[2]),\n .O(app_wdf_data[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1227\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[30]_i_1 \n (.I0(s_axi_wdata[30]),\n .I1(s_axi_wready),\n .I2(wdf_data[30]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[30]),\n .O(app_wdf_data[30]));\n (* SOFT_HLUTNM = \"soft_lutpair1228\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[31]_i_1 \n (.I0(s_axi_wdata[31]),\n .I1(s_axi_wready),\n .I2(wdf_data[31]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[31]),\n .O(app_wdf_data[31]));\n (* SOFT_HLUTNM = \"soft_lutpair1229\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[32]_i_1 \n (.I0(s_axi_wdata[32]),\n .I1(s_axi_wready),\n .I2(wdf_data[32]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[32]),\n .O(app_wdf_data[32]));\n (* SOFT_HLUTNM = \"soft_lutpair1230\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[33]_i_1 \n (.I0(s_axi_wdata[33]),\n .I1(s_axi_wready),\n .I2(wdf_data[33]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[33]),\n .O(app_wdf_data[33]));\n (* SOFT_HLUTNM = \"soft_lutpair1231\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[34]_i_1 \n (.I0(s_axi_wdata[34]),\n .I1(s_axi_wready),\n .I2(wdf_data[34]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[34]),\n .O(app_wdf_data[34]));\n (* SOFT_HLUTNM = \"soft_lutpair1232\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[35]_i_1 \n (.I0(s_axi_wdata[35]),\n .I1(s_axi_wready),\n .I2(wdf_data[35]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[35]),\n .O(app_wdf_data[35]));\n (* SOFT_HLUTNM = \"soft_lutpair1233\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[36]_i_1 \n (.I0(s_axi_wdata[36]),\n .I1(s_axi_wready),\n .I2(wdf_data[36]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[36]),\n .O(app_wdf_data[36]));\n (* SOFT_HLUTNM = \"soft_lutpair1234\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[37]_i_1 \n (.I0(s_axi_wdata[37]),\n .I1(s_axi_wready),\n .I2(wdf_data[37]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[37]),\n .O(app_wdf_data[37]));\n (* SOFT_HLUTNM = \"soft_lutpair1235\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[38]_i_1 \n (.I0(s_axi_wdata[38]),\n .I1(s_axi_wready),\n .I2(wdf_data[38]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[38]),\n .O(app_wdf_data[38]));\n (* SOFT_HLUTNM = \"soft_lutpair1236\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[39]_i_1 \n (.I0(s_axi_wdata[39]),\n .I1(s_axi_wready),\n .I2(wdf_data[39]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[39]),\n .O(app_wdf_data[39]));\n (* SOFT_HLUTNM = \"soft_lutpair1200\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[3]_i_1 \n (.I0(s_axi_wdata[3]),\n .I1(s_axi_wready),\n .I2(wdf_data[3]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[3]),\n .O(app_wdf_data[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1237\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[40]_i_1 \n (.I0(s_axi_wdata[40]),\n .I1(s_axi_wready),\n .I2(wdf_data[40]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[40]),\n .O(app_wdf_data[40]));\n (* SOFT_HLUTNM = \"soft_lutpair1238\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[41]_i_1 \n (.I0(s_axi_wdata[41]),\n .I1(s_axi_wready),\n .I2(wdf_data[41]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[41]),\n .O(app_wdf_data[41]));\n (* SOFT_HLUTNM = \"soft_lutpair1239\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[42]_i_1 \n (.I0(s_axi_wdata[42]),\n .I1(s_axi_wready),\n .I2(wdf_data[42]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[42]),\n .O(app_wdf_data[42]));\n (* SOFT_HLUTNM = \"soft_lutpair1240\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[43]_i_1 \n (.I0(s_axi_wdata[43]),\n .I1(s_axi_wready),\n .I2(wdf_data[43]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[43]),\n .O(app_wdf_data[43]));\n (* SOFT_HLUTNM = \"soft_lutpair1241\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[44]_i_1 \n (.I0(s_axi_wdata[44]),\n .I1(s_axi_wready),\n .I2(wdf_data[44]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[44]),\n .O(app_wdf_data[44]));\n (* SOFT_HLUTNM = \"soft_lutpair1242\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[45]_i_1 \n (.I0(s_axi_wdata[45]),\n .I1(s_axi_wready),\n .I2(wdf_data[45]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[45]),\n .O(app_wdf_data[45]));\n (* SOFT_HLUTNM = \"soft_lutpair1243\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[46]_i_1 \n (.I0(s_axi_wdata[46]),\n .I1(s_axi_wready),\n .I2(wdf_data[46]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[46]),\n .O(app_wdf_data[46]));\n (* SOFT_HLUTNM = \"soft_lutpair1244\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[47]_i_1 \n (.I0(s_axi_wdata[47]),\n .I1(s_axi_wready),\n .I2(wdf_data[47]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[47]),\n .O(app_wdf_data[47]));\n (* SOFT_HLUTNM = \"soft_lutpair1245\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[48]_i_1 \n (.I0(s_axi_wdata[48]),\n .I1(s_axi_wready),\n .I2(wdf_data[48]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[48]),\n .O(app_wdf_data[48]));\n (* SOFT_HLUTNM = \"soft_lutpair1246\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[49]_i_1 \n (.I0(s_axi_wdata[49]),\n .I1(s_axi_wready),\n .I2(wdf_data[49]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[49]),\n .O(app_wdf_data[49]));\n (* SOFT_HLUTNM = \"soft_lutpair1201\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[4]_i_1 \n (.I0(s_axi_wdata[4]),\n .I1(s_axi_wready),\n .I2(wdf_data[4]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[4]),\n .O(app_wdf_data[4]));\n (* SOFT_HLUTNM = \"soft_lutpair1247\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[50]_i_1 \n (.I0(s_axi_wdata[50]),\n .I1(s_axi_wready),\n .I2(wdf_data[50]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[50]),\n .O(app_wdf_data[50]));\n (* SOFT_HLUTNM = \"soft_lutpair1248\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[51]_i_1 \n (.I0(s_axi_wdata[51]),\n .I1(s_axi_wready),\n .I2(wdf_data[51]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[51]),\n .O(app_wdf_data[51]));\n (* SOFT_HLUTNM = \"soft_lutpair1249\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[52]_i_1 \n (.I0(s_axi_wdata[52]),\n .I1(s_axi_wready),\n .I2(wdf_data[52]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[52]),\n .O(app_wdf_data[52]));\n (* SOFT_HLUTNM = \"soft_lutpair1250\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[53]_i_1 \n (.I0(s_axi_wdata[53]),\n .I1(s_axi_wready),\n .I2(wdf_data[53]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[53]),\n .O(app_wdf_data[53]));\n (* SOFT_HLUTNM = \"soft_lutpair1251\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[54]_i_1 \n (.I0(s_axi_wdata[54]),\n .I1(s_axi_wready),\n .I2(wdf_data[54]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[54]),\n .O(app_wdf_data[54]));\n (* SOFT_HLUTNM = \"soft_lutpair1252\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[55]_i_1 \n (.I0(s_axi_wdata[55]),\n .I1(s_axi_wready),\n .I2(wdf_data[55]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[55]),\n .O(app_wdf_data[55]));\n (* SOFT_HLUTNM = \"soft_lutpair1253\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[56]_i_1 \n (.I0(s_axi_wdata[56]),\n .I1(s_axi_wready),\n .I2(wdf_data[56]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[56]),\n .O(app_wdf_data[56]));\n (* SOFT_HLUTNM = \"soft_lutpair1254\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[57]_i_1 \n (.I0(s_axi_wdata[57]),\n .I1(s_axi_wready),\n .I2(wdf_data[57]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[57]),\n .O(app_wdf_data[57]));\n (* SOFT_HLUTNM = \"soft_lutpair1255\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[58]_i_1 \n (.I0(s_axi_wdata[58]),\n .I1(s_axi_wready),\n .I2(wdf_data[58]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[58]),\n .O(app_wdf_data[58]));\n (* SOFT_HLUTNM = \"soft_lutpair1256\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[59]_i_1 \n (.I0(s_axi_wdata[59]),\n .I1(s_axi_wready),\n .I2(wdf_data[59]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[59]),\n .O(app_wdf_data[59]));\n (* SOFT_HLUTNM = \"soft_lutpair1202\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[5]_i_1 \n (.I0(s_axi_wdata[5]),\n .I1(s_axi_wready),\n .I2(wdf_data[5]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[5]),\n .O(app_wdf_data[5]));\n (* SOFT_HLUTNM = \"soft_lutpair1257\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[60]_i_1 \n (.I0(s_axi_wdata[60]),\n .I1(s_axi_wready),\n .I2(wdf_data[60]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[60]),\n .O(app_wdf_data[60]));\n (* SOFT_HLUTNM = \"soft_lutpair1258\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[61]_i_1 \n (.I0(s_axi_wdata[61]),\n .I1(s_axi_wready),\n .I2(wdf_data[61]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[61]),\n .O(app_wdf_data[61]));\n (* SOFT_HLUTNM = \"soft_lutpair1259\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[62]_i_1 \n (.I0(s_axi_wdata[62]),\n .I1(s_axi_wready),\n .I2(wdf_data[62]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[62]),\n .O(app_wdf_data[62]));\n (* SOFT_HLUTNM = \"soft_lutpair1260\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[63]_i_1 \n (.I0(s_axi_wdata[63]),\n .I1(s_axi_wready),\n .I2(wdf_data[63]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[63]),\n .O(app_wdf_data[63]));\n (* SOFT_HLUTNM = \"soft_lutpair1261\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[64]_i_1 \n (.I0(s_axi_wdata[64]),\n .I1(s_axi_wready),\n .I2(wdf_data[64]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[64]),\n .O(app_wdf_data[64]));\n (* SOFT_HLUTNM = \"soft_lutpair1262\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[65]_i_1 \n (.I0(s_axi_wdata[65]),\n .I1(s_axi_wready),\n .I2(wdf_data[65]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[65]),\n .O(app_wdf_data[65]));\n (* SOFT_HLUTNM = \"soft_lutpair1263\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[66]_i_1 \n (.I0(s_axi_wdata[66]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[66]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[66]),\n .O(app_wdf_data[66]));\n (* SOFT_HLUTNM = \"soft_lutpair1264\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[67]_i_1 \n (.I0(s_axi_wdata[67]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[67]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[67]),\n .O(app_wdf_data[67]));\n (* SOFT_HLUTNM = \"soft_lutpair1265\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[68]_i_1 \n (.I0(s_axi_wdata[68]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[68]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[68]),\n .O(app_wdf_data[68]));\n (* SOFT_HLUTNM = \"soft_lutpair1266\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[69]_i_1 \n (.I0(s_axi_wdata[69]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[69]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[69]),\n .O(app_wdf_data[69]));\n (* SOFT_HLUTNM = \"soft_lutpair1203\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[6]_i_1 \n (.I0(s_axi_wdata[6]),\n .I1(s_axi_wready),\n .I2(wdf_data[6]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[6]),\n .O(app_wdf_data[6]));\n (* SOFT_HLUTNM = \"soft_lutpair1267\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[70]_i_1 \n (.I0(s_axi_wdata[70]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[70]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[70]),\n .O(app_wdf_data[70]));\n (* SOFT_HLUTNM = \"soft_lutpair1268\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[71]_i_1 \n (.I0(s_axi_wdata[71]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[71]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[71]),\n .O(app_wdf_data[71]));\n (* SOFT_HLUTNM = \"soft_lutpair1269\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[72]_i_1 \n (.I0(s_axi_wdata[72]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[72]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[72]),\n .O(app_wdf_data[72]));\n (* SOFT_HLUTNM = \"soft_lutpair1270\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[73]_i_1 \n (.I0(s_axi_wdata[73]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[73]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[73]),\n .O(app_wdf_data[73]));\n (* SOFT_HLUTNM = \"soft_lutpair1271\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[74]_i_1 \n (.I0(s_axi_wdata[74]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[74]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[74]),\n .O(app_wdf_data[74]));\n (* SOFT_HLUTNM = \"soft_lutpair1272\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[75]_i_1 \n (.I0(s_axi_wdata[75]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[75]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[75]),\n .O(app_wdf_data[75]));\n (* SOFT_HLUTNM = \"soft_lutpair1273\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[76]_i_1 \n (.I0(s_axi_wdata[76]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[76]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[76]),\n .O(app_wdf_data[76]));\n (* SOFT_HLUTNM = \"soft_lutpair1274\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[77]_i_1 \n (.I0(s_axi_wdata[77]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[77]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[77]),\n .O(app_wdf_data[77]));\n (* SOFT_HLUTNM = \"soft_lutpair1275\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[78]_i_1 \n (.I0(s_axi_wdata[78]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[78]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[78]),\n .O(app_wdf_data[78]));\n (* SOFT_HLUTNM = \"soft_lutpair1276\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[79]_i_1 \n (.I0(s_axi_wdata[79]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[79]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[79]),\n .O(app_wdf_data[79]));\n (* SOFT_HLUTNM = \"soft_lutpair1204\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[7]_i_1 \n (.I0(s_axi_wdata[7]),\n .I1(s_axi_wready),\n .I2(wdf_data[7]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[7]),\n .O(app_wdf_data[7]));\n (* SOFT_HLUTNM = \"soft_lutpair1277\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[80]_i_1 \n (.I0(s_axi_wdata[80]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[80]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[80]),\n .O(app_wdf_data[80]));\n (* SOFT_HLUTNM = \"soft_lutpair1278\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[81]_i_1 \n (.I0(s_axi_wdata[81]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[81]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[81]),\n .O(app_wdf_data[81]));\n (* SOFT_HLUTNM = \"soft_lutpair1279\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[82]_i_1 \n (.I0(s_axi_wdata[82]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[82]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[82]),\n .O(app_wdf_data[82]));\n (* SOFT_HLUTNM = \"soft_lutpair1280\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[83]_i_1 \n (.I0(s_axi_wdata[83]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[83]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[83]),\n .O(app_wdf_data[83]));\n (* SOFT_HLUTNM = \"soft_lutpair1281\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[84]_i_1 \n (.I0(s_axi_wdata[84]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[84]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[84]),\n .O(app_wdf_data[84]));\n (* SOFT_HLUTNM = \"soft_lutpair1282\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[85]_i_1 \n (.I0(s_axi_wdata[85]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[85]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[85]),\n .O(app_wdf_data[85]));\n (* SOFT_HLUTNM = \"soft_lutpair1283\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[86]_i_1 \n (.I0(s_axi_wdata[86]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[86]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[86]),\n .O(app_wdf_data[86]));\n (* SOFT_HLUTNM = \"soft_lutpair1284\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[87]_i_1 \n (.I0(s_axi_wdata[87]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[87]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[87]),\n .O(app_wdf_data[87]));\n (* SOFT_HLUTNM = \"soft_lutpair1285\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[88]_i_1 \n (.I0(s_axi_wdata[88]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[88]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[88]),\n .O(app_wdf_data[88]));\n (* SOFT_HLUTNM = \"soft_lutpair1286\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[89]_i_1 \n (.I0(s_axi_wdata[89]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[89]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[89]),\n .O(app_wdf_data[89]));\n (* SOFT_HLUTNM = \"soft_lutpair1205\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[8]_i_1 \n (.I0(s_axi_wdata[8]),\n .I1(s_axi_wready),\n .I2(wdf_data[8]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[8]),\n .O(app_wdf_data[8]));\n (* SOFT_HLUTNM = \"soft_lutpair1287\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[90]_i_1 \n (.I0(s_axi_wdata[90]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[90]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[90]),\n .O(app_wdf_data[90]));\n (* SOFT_HLUTNM = \"soft_lutpair1288\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[91]_i_1 \n (.I0(s_axi_wdata[91]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[91]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[91]),\n .O(app_wdf_data[91]));\n (* SOFT_HLUTNM = \"soft_lutpair1289\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[92]_i_1 \n (.I0(s_axi_wdata[92]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[92]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[92]),\n .O(app_wdf_data[92]));\n (* SOFT_HLUTNM = \"soft_lutpair1290\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[93]_i_1 \n (.I0(s_axi_wdata[93]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[93]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[93]),\n .O(app_wdf_data[93]));\n (* SOFT_HLUTNM = \"soft_lutpair1291\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[94]_i_1 \n (.I0(s_axi_wdata[94]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[94]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[94]),\n .O(app_wdf_data[94]));\n (* SOFT_HLUTNM = \"soft_lutpair1292\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[95]_i_1 \n (.I0(s_axi_wdata[95]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[95]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[95]),\n .O(app_wdf_data[95]));\n (* SOFT_HLUTNM = \"soft_lutpair1293\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[96]_i_1 \n (.I0(s_axi_wdata[96]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[96]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[96]),\n .O(app_wdf_data[96]));\n (* SOFT_HLUTNM = \"soft_lutpair1294\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[97]_i_1 \n (.I0(s_axi_wdata[97]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[97]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[97]),\n .O(app_wdf_data[97]));\n (* SOFT_HLUTNM = \"soft_lutpair1295\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[98]_i_1 \n (.I0(s_axi_wdata[98]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[98]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[98]),\n .O(app_wdf_data[98]));\n (* SOFT_HLUTNM = \"soft_lutpair1296\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[99]_i_1 \n (.I0(s_axi_wdata[99]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[99]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[99]),\n .O(app_wdf_data[99]));\n (* SOFT_HLUTNM = \"soft_lutpair1206\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_wdf_data_r1[9]_i_1 \n (.I0(s_axi_wdata[9]),\n .I1(s_axi_wready),\n .I2(wdf_data[9]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_data_reg[9]),\n .O(app_wdf_data[9]));\n (* SOFT_HLUTNM = \"soft_lutpair1453\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[0]_i_1 \n (.I0(s_axi_wstrb[0]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_mask[0]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[0]),\n .O(app_wdf_mask[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1463\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[10]_i_1 \n (.I0(s_axi_wstrb[10]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[10]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[10]),\n .O(app_wdf_mask[10]));\n (* SOFT_HLUTNM = \"soft_lutpair1464\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[11]_i_1 \n (.I0(s_axi_wstrb[11]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[11]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[11]),\n .O(app_wdf_mask[11]));\n (* SOFT_HLUTNM = \"soft_lutpair1465\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[12]_i_1 \n (.I0(s_axi_wstrb[12]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[12]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[12]),\n .O(app_wdf_mask[12]));\n (* SOFT_HLUTNM = \"soft_lutpair1466\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[13]_i_1 \n (.I0(s_axi_wstrb[13]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[13]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[13]),\n .O(app_wdf_mask[13]));\n (* SOFT_HLUTNM = \"soft_lutpair1467\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[14]_i_1 \n (.I0(s_axi_wstrb[14]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[14]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[14]),\n .O(app_wdf_mask[14]));\n (* SOFT_HLUTNM = \"soft_lutpair1468\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[15]_i_1 \n (.I0(s_axi_wstrb[15]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[15]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[15]),\n .O(app_wdf_mask[15]));\n (* SOFT_HLUTNM = \"soft_lutpair1469\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[16]_i_1 \n (.I0(s_axi_wstrb[16]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[16]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[16]),\n .O(app_wdf_mask[16]));\n (* SOFT_HLUTNM = \"soft_lutpair1470\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[17]_i_1 \n (.I0(s_axi_wstrb[17]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[17]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[17]),\n .O(app_wdf_mask[17]));\n (* SOFT_HLUTNM = \"soft_lutpair1471\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[18]_i_1 \n (.I0(s_axi_wstrb[18]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[18]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[18]),\n .O(app_wdf_mask[18]));\n (* SOFT_HLUTNM = \"soft_lutpair1472\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[19]_i_1 \n (.I0(s_axi_wstrb[19]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[19]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[19]),\n .O(app_wdf_mask[19]));\n (* SOFT_HLUTNM = \"soft_lutpair1454\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[1]_i_1 \n (.I0(s_axi_wstrb[1]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_mask[1]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[1]),\n .O(app_wdf_mask[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1473\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[20]_i_1 \n (.I0(s_axi_wstrb[20]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[20]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[20]),\n .O(app_wdf_mask[20]));\n (* SOFT_HLUTNM = \"soft_lutpair1474\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[21]_i_1 \n (.I0(s_axi_wstrb[21]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[21]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[21]),\n .O(app_wdf_mask[21]));\n (* SOFT_HLUTNM = \"soft_lutpair1475\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[22]_i_1 \n (.I0(s_axi_wstrb[22]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[22]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[22]),\n .O(app_wdf_mask[22]));\n (* SOFT_HLUTNM = \"soft_lutpair1476\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[23]_i_1 \n (.I0(s_axi_wstrb[23]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[23]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[23]),\n .O(app_wdf_mask[23]));\n (* SOFT_HLUTNM = \"soft_lutpair1477\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[24]_i_1 \n (.I0(s_axi_wstrb[24]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[24]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[24]),\n .O(app_wdf_mask[24]));\n (* SOFT_HLUTNM = \"soft_lutpair1478\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[25]_i_1 \n (.I0(s_axi_wstrb[25]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[25]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[25]),\n .O(app_wdf_mask[25]));\n (* SOFT_HLUTNM = \"soft_lutpair1479\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[26]_i_1 \n (.I0(s_axi_wstrb[26]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[26]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[26]),\n .O(app_wdf_mask[26]));\n (* SOFT_HLUTNM = \"soft_lutpair1480\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[27]_i_1 \n (.I0(s_axi_wstrb[27]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[27]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[27]),\n .O(app_wdf_mask[27]));\n (* SOFT_HLUTNM = \"soft_lutpair1481\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[28]_i_1 \n (.I0(s_axi_wstrb[28]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[28]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[28]),\n .O(app_wdf_mask[28]));\n (* SOFT_HLUTNM = \"soft_lutpair1482\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[29]_i_1 \n (.I0(s_axi_wstrb[29]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[29]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[29]),\n .O(app_wdf_mask[29]));\n (* SOFT_HLUTNM = \"soft_lutpair1455\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[2]_i_1 \n (.I0(s_axi_wstrb[2]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_mask[2]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[2]),\n .O(app_wdf_mask[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1483\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[30]_i_1 \n (.I0(s_axi_wstrb[30]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[30]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[30]),\n .O(app_wdf_mask[30]));\n (* SOFT_HLUTNM = \"soft_lutpair1484\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[31]_i_1 \n (.I0(s_axi_wstrb[31]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[31]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[31]),\n .O(app_wdf_mask[31]));\n (* SOFT_HLUTNM = \"soft_lutpair1456\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[3]_i_1 \n (.I0(s_axi_wstrb[3]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_mask[3]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[3]),\n .O(app_wdf_mask[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1457\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[4]_i_1 \n (.I0(s_axi_wstrb[4]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_mask[4]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[4]),\n .O(app_wdf_mask[4]));\n (* SOFT_HLUTNM = \"soft_lutpair1458\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[5]_i_1 \n (.I0(s_axi_wstrb[5]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_mask[5]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[5]),\n .O(app_wdf_mask[5]));\n (* SOFT_HLUTNM = \"soft_lutpair1459\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[6]_i_1 \n (.I0(s_axi_wstrb[6]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_mask[6]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[6]),\n .O(app_wdf_mask[6]));\n (* SOFT_HLUTNM = \"soft_lutpair1460\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[7]_i_1 \n (.I0(s_axi_wstrb[7]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_mask[7]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[7]),\n .O(app_wdf_mask[7]));\n (* SOFT_HLUTNM = \"soft_lutpair1461\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[8]_i_1 \n (.I0(s_axi_wstrb[8]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[8]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[8]),\n .O(app_wdf_mask[8]));\n (* SOFT_HLUTNM = \"soft_lutpair1462\" *) \n LUT5 #(\n .INIT(32'h74FF7400)) \n \\app_wdf_mask_r1[9]_i_1 \n (.I0(s_axi_wstrb[9]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[9]),\n .I3(app_wdf_rdy),\n .I4(mc_app_wdf_mask_reg[9]),\n .O(app_wdf_mask[9]));\n (* SOFT_HLUTNM = \"soft_lutpair1485\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[0]_i_1 \n (.I0(s_axi_wdata[0]),\n .I1(s_axi_wready),\n .I2(wdf_data[0]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair1297\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[100]_i_1 \n (.I0(s_axi_wdata[100]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[100]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [100]));\n (* SOFT_HLUTNM = \"soft_lutpair1298\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[101]_i_1 \n (.I0(s_axi_wdata[101]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[101]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [101]));\n (* SOFT_HLUTNM = \"soft_lutpair1299\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[102]_i_1 \n (.I0(s_axi_wdata[102]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[102]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [102]));\n (* SOFT_HLUTNM = \"soft_lutpair1300\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[103]_i_1 \n (.I0(s_axi_wdata[103]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[103]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [103]));\n (* SOFT_HLUTNM = \"soft_lutpair1301\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[104]_i_1 \n (.I0(s_axi_wdata[104]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[104]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [104]));\n (* SOFT_HLUTNM = \"soft_lutpair1302\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[105]_i_1 \n (.I0(s_axi_wdata[105]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[105]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [105]));\n (* SOFT_HLUTNM = \"soft_lutpair1303\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[106]_i_1 \n (.I0(s_axi_wdata[106]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[106]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [106]));\n (* SOFT_HLUTNM = \"soft_lutpair1304\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[107]_i_1 \n (.I0(s_axi_wdata[107]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[107]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [107]));\n (* SOFT_HLUTNM = \"soft_lutpair1305\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[108]_i_1 \n (.I0(s_axi_wdata[108]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[108]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [108]));\n (* SOFT_HLUTNM = \"soft_lutpair1306\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[109]_i_1 \n (.I0(s_axi_wdata[109]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[109]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [109]));\n (* SOFT_HLUTNM = \"soft_lutpair1207\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[10]_i_1 \n (.I0(s_axi_wdata[10]),\n .I1(s_axi_wready),\n .I2(wdf_data[10]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [10]));\n (* SOFT_HLUTNM = \"soft_lutpair1307\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[110]_i_1 \n (.I0(s_axi_wdata[110]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[110]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [110]));\n (* SOFT_HLUTNM = \"soft_lutpair1308\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[111]_i_1 \n (.I0(s_axi_wdata[111]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[111]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [111]));\n (* SOFT_HLUTNM = \"soft_lutpair1309\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[112]_i_1 \n (.I0(s_axi_wdata[112]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[112]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [112]));\n (* SOFT_HLUTNM = \"soft_lutpair1310\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[113]_i_1 \n (.I0(s_axi_wdata[113]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[113]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [113]));\n (* SOFT_HLUTNM = \"soft_lutpair1311\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[114]_i_1 \n (.I0(s_axi_wdata[114]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[114]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [114]));\n (* SOFT_HLUTNM = \"soft_lutpair1312\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[115]_i_1 \n (.I0(s_axi_wdata[115]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[115]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [115]));\n (* SOFT_HLUTNM = \"soft_lutpair1313\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[116]_i_1 \n (.I0(s_axi_wdata[116]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[116]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [116]));\n (* SOFT_HLUTNM = \"soft_lutpair1314\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[117]_i_1 \n (.I0(s_axi_wdata[117]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[117]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [117]));\n (* SOFT_HLUTNM = \"soft_lutpair1315\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[118]_i_1 \n (.I0(s_axi_wdata[118]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[118]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [118]));\n (* SOFT_HLUTNM = \"soft_lutpair1316\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[119]_i_1 \n (.I0(s_axi_wdata[119]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[119]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [119]));\n (* SOFT_HLUTNM = \"soft_lutpair1208\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[11]_i_1 \n (.I0(s_axi_wdata[11]),\n .I1(s_axi_wready),\n .I2(wdf_data[11]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [11]));\n (* SOFT_HLUTNM = \"soft_lutpair1317\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[120]_i_1 \n (.I0(s_axi_wdata[120]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[120]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [120]));\n (* SOFT_HLUTNM = \"soft_lutpair1318\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[121]_i_1 \n (.I0(s_axi_wdata[121]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[121]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [121]));\n (* SOFT_HLUTNM = \"soft_lutpair1319\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[122]_i_1 \n (.I0(s_axi_wdata[122]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[122]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [122]));\n (* SOFT_HLUTNM = \"soft_lutpair1320\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[123]_i_1 \n (.I0(s_axi_wdata[123]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[123]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [123]));\n (* SOFT_HLUTNM = \"soft_lutpair1321\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[124]_i_1 \n (.I0(s_axi_wdata[124]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[124]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [124]));\n (* SOFT_HLUTNM = \"soft_lutpair1322\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[125]_i_1 \n (.I0(s_axi_wdata[125]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[125]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [125]));\n (* SOFT_HLUTNM = \"soft_lutpair1323\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[126]_i_1 \n (.I0(s_axi_wdata[126]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[126]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [126]));\n (* SOFT_HLUTNM = \"soft_lutpair1324\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[127]_i_1 \n (.I0(s_axi_wdata[127]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[127]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [127]));\n (* SOFT_HLUTNM = \"soft_lutpair1325\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[128]_i_1 \n (.I0(s_axi_wdata[128]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[128]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [128]));\n (* SOFT_HLUTNM = \"soft_lutpair1326\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[129]_i_1 \n (.I0(s_axi_wdata[129]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[129]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [129]));\n (* SOFT_HLUTNM = \"soft_lutpair1209\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[12]_i_1 \n (.I0(s_axi_wdata[12]),\n .I1(s_axi_wready),\n .I2(wdf_data[12]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [12]));\n (* SOFT_HLUTNM = \"soft_lutpair1327\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[130]_i_1 \n (.I0(s_axi_wdata[130]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[130]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [130]));\n (* SOFT_HLUTNM = \"soft_lutpair1328\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[131]_i_1 \n (.I0(s_axi_wdata[131]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[131]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [131]));\n (* SOFT_HLUTNM = \"soft_lutpair1329\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[132]_i_1 \n (.I0(s_axi_wdata[132]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[132]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [132]));\n (* SOFT_HLUTNM = \"soft_lutpair1330\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[133]_i_1 \n (.I0(s_axi_wdata[133]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[133]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [133]));\n (* SOFT_HLUTNM = \"soft_lutpair1331\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[134]_i_1 \n (.I0(s_axi_wdata[134]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[134]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [134]));\n (* SOFT_HLUTNM = \"soft_lutpair1332\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[135]_i_1 \n (.I0(s_axi_wdata[135]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[135]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [135]));\n (* SOFT_HLUTNM = \"soft_lutpair1333\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[136]_i_1 \n (.I0(s_axi_wdata[136]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[136]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [136]));\n (* SOFT_HLUTNM = \"soft_lutpair1334\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[137]_i_1 \n (.I0(s_axi_wdata[137]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[137]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [137]));\n (* SOFT_HLUTNM = \"soft_lutpair1335\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[138]_i_1 \n (.I0(s_axi_wdata[138]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[138]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [138]));\n (* SOFT_HLUTNM = \"soft_lutpair1336\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[139]_i_1 \n (.I0(s_axi_wdata[139]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[139]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [139]));\n (* SOFT_HLUTNM = \"soft_lutpair1210\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[13]_i_1 \n (.I0(s_axi_wdata[13]),\n .I1(s_axi_wready),\n .I2(wdf_data[13]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [13]));\n (* SOFT_HLUTNM = \"soft_lutpair1337\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[140]_i_1 \n (.I0(s_axi_wdata[140]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[140]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [140]));\n (* SOFT_HLUTNM = \"soft_lutpair1338\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[141]_i_1 \n (.I0(s_axi_wdata[141]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[141]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [141]));\n (* SOFT_HLUTNM = \"soft_lutpair1339\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[142]_i_1 \n (.I0(s_axi_wdata[142]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[142]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [142]));\n (* SOFT_HLUTNM = \"soft_lutpair1340\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[143]_i_1 \n (.I0(s_axi_wdata[143]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[143]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [143]));\n (* SOFT_HLUTNM = \"soft_lutpair1341\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[144]_i_1 \n (.I0(s_axi_wdata[144]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[144]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [144]));\n (* SOFT_HLUTNM = \"soft_lutpair1342\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[145]_i_1 \n (.I0(s_axi_wdata[145]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[145]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [145]));\n (* SOFT_HLUTNM = \"soft_lutpair1343\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[146]_i_1 \n (.I0(s_axi_wdata[146]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[146]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [146]));\n (* SOFT_HLUTNM = \"soft_lutpair1344\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[147]_i_1 \n (.I0(s_axi_wdata[147]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[147]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [147]));\n (* SOFT_HLUTNM = \"soft_lutpair1345\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[148]_i_1 \n (.I0(s_axi_wdata[148]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[148]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [148]));\n (* SOFT_HLUTNM = \"soft_lutpair1346\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[149]_i_1 \n (.I0(s_axi_wdata[149]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[149]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [149]));\n (* SOFT_HLUTNM = \"soft_lutpair1211\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[14]_i_1 \n (.I0(s_axi_wdata[14]),\n .I1(s_axi_wready),\n .I2(wdf_data[14]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [14]));\n (* SOFT_HLUTNM = \"soft_lutpair1347\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[150]_i_1 \n (.I0(s_axi_wdata[150]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[150]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [150]));\n (* SOFT_HLUTNM = \"soft_lutpair1348\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[151]_i_1 \n (.I0(s_axi_wdata[151]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[151]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [151]));\n (* SOFT_HLUTNM = \"soft_lutpair1349\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[152]_i_1 \n (.I0(s_axi_wdata[152]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[152]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [152]));\n (* SOFT_HLUTNM = \"soft_lutpair1350\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[153]_i_1 \n (.I0(s_axi_wdata[153]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[153]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [153]));\n (* SOFT_HLUTNM = \"soft_lutpair1351\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[154]_i_1 \n (.I0(s_axi_wdata[154]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[154]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [154]));\n (* SOFT_HLUTNM = \"soft_lutpair1352\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[155]_i_1 \n (.I0(s_axi_wdata[155]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[155]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [155]));\n (* SOFT_HLUTNM = \"soft_lutpair1353\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[156]_i_1 \n (.I0(s_axi_wdata[156]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[156]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [156]));\n (* SOFT_HLUTNM = \"soft_lutpair1354\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[157]_i_1 \n (.I0(s_axi_wdata[157]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[157]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [157]));\n (* SOFT_HLUTNM = \"soft_lutpair1355\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[158]_i_1 \n (.I0(s_axi_wdata[158]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[158]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [158]));\n (* SOFT_HLUTNM = \"soft_lutpair1356\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[159]_i_1 \n (.I0(s_axi_wdata[159]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[159]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [159]));\n (* SOFT_HLUTNM = \"soft_lutpair1212\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[15]_i_1 \n (.I0(s_axi_wdata[15]),\n .I1(s_axi_wready),\n .I2(wdf_data[15]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [15]));\n (* SOFT_HLUTNM = \"soft_lutpair1357\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[160]_i_1 \n (.I0(s_axi_wdata[160]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[160]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [160]));\n (* SOFT_HLUTNM = \"soft_lutpair1358\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[161]_i_1 \n (.I0(s_axi_wdata[161]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[161]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [161]));\n (* SOFT_HLUTNM = \"soft_lutpair1359\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[162]_i_1 \n (.I0(s_axi_wdata[162]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[162]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [162]));\n (* SOFT_HLUTNM = \"soft_lutpair1360\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[163]_i_1 \n (.I0(s_axi_wdata[163]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[163]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [163]));\n (* SOFT_HLUTNM = \"soft_lutpair1361\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[164]_i_1 \n (.I0(s_axi_wdata[164]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[164]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [164]));\n (* SOFT_HLUTNM = \"soft_lutpair1362\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[165]_i_1 \n (.I0(s_axi_wdata[165]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[165]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [165]));\n (* SOFT_HLUTNM = \"soft_lutpair1363\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[166]_i_1 \n (.I0(s_axi_wdata[166]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[166]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [166]));\n (* SOFT_HLUTNM = \"soft_lutpair1364\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[167]_i_1 \n (.I0(s_axi_wdata[167]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[167]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [167]));\n (* SOFT_HLUTNM = \"soft_lutpair1365\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[168]_i_1 \n (.I0(s_axi_wdata[168]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[168]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [168]));\n (* SOFT_HLUTNM = \"soft_lutpair1366\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[169]_i_1 \n (.I0(s_axi_wdata[169]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[169]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [169]));\n (* SOFT_HLUTNM = \"soft_lutpair1213\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[16]_i_1 \n (.I0(s_axi_wdata[16]),\n .I1(s_axi_wready),\n .I2(wdf_data[16]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [16]));\n (* SOFT_HLUTNM = \"soft_lutpair1367\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[170]_i_1 \n (.I0(s_axi_wdata[170]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[170]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [170]));\n (* SOFT_HLUTNM = \"soft_lutpair1368\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[171]_i_1 \n (.I0(s_axi_wdata[171]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[171]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [171]));\n (* SOFT_HLUTNM = \"soft_lutpair1369\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[172]_i_1 \n (.I0(s_axi_wdata[172]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[172]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [172]));\n (* SOFT_HLUTNM = \"soft_lutpair1370\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[173]_i_1 \n (.I0(s_axi_wdata[173]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[173]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [173]));\n (* SOFT_HLUTNM = \"soft_lutpair1371\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[174]_i_1 \n (.I0(s_axi_wdata[174]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[174]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [174]));\n (* SOFT_HLUTNM = \"soft_lutpair1372\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[175]_i_1 \n (.I0(s_axi_wdata[175]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[175]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [175]));\n (* SOFT_HLUTNM = \"soft_lutpair1373\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[176]_i_1 \n (.I0(s_axi_wdata[176]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[176]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [176]));\n (* SOFT_HLUTNM = \"soft_lutpair1374\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[177]_i_1 \n (.I0(s_axi_wdata[177]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[177]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [177]));\n (* SOFT_HLUTNM = \"soft_lutpair1375\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[178]_i_1 \n (.I0(s_axi_wdata[178]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[178]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [178]));\n (* SOFT_HLUTNM = \"soft_lutpair1376\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[179]_i_1 \n (.I0(s_axi_wdata[179]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[179]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [179]));\n (* SOFT_HLUTNM = \"soft_lutpair1214\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[17]_i_1 \n (.I0(s_axi_wdata[17]),\n .I1(s_axi_wready),\n .I2(wdf_data[17]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [17]));\n (* SOFT_HLUTNM = \"soft_lutpair1377\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[180]_i_1 \n (.I0(s_axi_wdata[180]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[180]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [180]));\n (* SOFT_HLUTNM = \"soft_lutpair1378\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[181]_i_1 \n (.I0(s_axi_wdata[181]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[181]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [181]));\n (* SOFT_HLUTNM = \"soft_lutpair1379\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[182]_i_1 \n (.I0(s_axi_wdata[182]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[182]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [182]));\n (* SOFT_HLUTNM = \"soft_lutpair1380\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[183]_i_1 \n (.I0(s_axi_wdata[183]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[183]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [183]));\n (* SOFT_HLUTNM = \"soft_lutpair1381\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[184]_i_1 \n (.I0(s_axi_wdata[184]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[184]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [184]));\n (* SOFT_HLUTNM = \"soft_lutpair1382\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[185]_i_1 \n (.I0(s_axi_wdata[185]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[185]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [185]));\n (* SOFT_HLUTNM = \"soft_lutpair1383\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[186]_i_1 \n (.I0(s_axi_wdata[186]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[186]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [186]));\n (* SOFT_HLUTNM = \"soft_lutpair1384\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[187]_i_1 \n (.I0(s_axi_wdata[187]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[187]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [187]));\n (* SOFT_HLUTNM = \"soft_lutpair1385\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[188]_i_1 \n (.I0(s_axi_wdata[188]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[188]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [188]));\n (* SOFT_HLUTNM = \"soft_lutpair1386\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[189]_i_1 \n (.I0(s_axi_wdata[189]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[189]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [189]));\n (* SOFT_HLUTNM = \"soft_lutpair1215\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[18]_i_1 \n (.I0(s_axi_wdata[18]),\n .I1(s_axi_wready),\n .I2(wdf_data[18]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [18]));\n (* SOFT_HLUTNM = \"soft_lutpair1387\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[190]_i_1 \n (.I0(s_axi_wdata[190]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[190]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [190]));\n (* SOFT_HLUTNM = \"soft_lutpair1388\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[191]_i_1 \n (.I0(s_axi_wdata[191]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[191]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [191]));\n (* SOFT_HLUTNM = \"soft_lutpair1389\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[192]_i_1 \n (.I0(s_axi_wdata[192]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[192]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [192]));\n (* SOFT_HLUTNM = \"soft_lutpair1390\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[193]_i_1 \n (.I0(s_axi_wdata[193]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[193]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [193]));\n (* SOFT_HLUTNM = \"soft_lutpair1391\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[194]_i_1 \n (.I0(s_axi_wdata[194]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[194]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [194]));\n (* SOFT_HLUTNM = \"soft_lutpair1392\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[195]_i_1 \n (.I0(s_axi_wdata[195]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[195]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [195]));\n (* SOFT_HLUTNM = \"soft_lutpair1393\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[196]_i_1 \n (.I0(s_axi_wdata[196]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[196]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [196]));\n (* SOFT_HLUTNM = \"soft_lutpair1394\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[197]_i_1 \n (.I0(s_axi_wdata[197]),\n .I1(wready_reg_rep__0_n_0),\n .I2(wdf_data[197]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [197]));\n (* SOFT_HLUTNM = \"soft_lutpair1395\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[198]_i_1 \n (.I0(s_axi_wdata[198]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[198]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [198]));\n (* SOFT_HLUTNM = \"soft_lutpair1396\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[199]_i_1 \n (.I0(s_axi_wdata[199]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[199]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [199]));\n (* SOFT_HLUTNM = \"soft_lutpair1216\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[19]_i_1 \n (.I0(s_axi_wdata[19]),\n .I1(s_axi_wready),\n .I2(wdf_data[19]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [19]));\n (* SOFT_HLUTNM = \"soft_lutpair1198\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[1]_i_1 \n (.I0(s_axi_wdata[1]),\n .I1(s_axi_wready),\n .I2(wdf_data[1]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [1]));\n (* SOFT_HLUTNM = \"soft_lutpair1397\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[200]_i_1 \n (.I0(s_axi_wdata[200]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[200]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [200]));\n (* SOFT_HLUTNM = \"soft_lutpair1398\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[201]_i_1 \n (.I0(s_axi_wdata[201]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[201]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [201]));\n (* SOFT_HLUTNM = \"soft_lutpair1399\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[202]_i_1 \n (.I0(s_axi_wdata[202]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[202]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [202]));\n (* SOFT_HLUTNM = \"soft_lutpair1400\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[203]_i_1 \n (.I0(s_axi_wdata[203]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[203]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [203]));\n (* SOFT_HLUTNM = \"soft_lutpair1401\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[204]_i_1 \n (.I0(s_axi_wdata[204]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[204]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [204]));\n (* SOFT_HLUTNM = \"soft_lutpair1402\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[205]_i_1 \n (.I0(s_axi_wdata[205]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[205]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [205]));\n (* SOFT_HLUTNM = \"soft_lutpair1403\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[206]_i_1 \n (.I0(s_axi_wdata[206]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[206]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [206]));\n (* SOFT_HLUTNM = \"soft_lutpair1404\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[207]_i_1 \n (.I0(s_axi_wdata[207]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[207]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [207]));\n (* SOFT_HLUTNM = \"soft_lutpair1405\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[208]_i_1 \n (.I0(s_axi_wdata[208]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[208]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [208]));\n (* SOFT_HLUTNM = \"soft_lutpair1406\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[209]_i_1 \n (.I0(s_axi_wdata[209]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[209]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [209]));\n (* SOFT_HLUTNM = \"soft_lutpair1217\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[20]_i_1 \n (.I0(s_axi_wdata[20]),\n .I1(s_axi_wready),\n .I2(wdf_data[20]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [20]));\n (* SOFT_HLUTNM = \"soft_lutpair1407\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[210]_i_1 \n (.I0(s_axi_wdata[210]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[210]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [210]));\n (* SOFT_HLUTNM = \"soft_lutpair1408\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[211]_i_1 \n (.I0(s_axi_wdata[211]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[211]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [211]));\n (* SOFT_HLUTNM = \"soft_lutpair1409\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[212]_i_1 \n (.I0(s_axi_wdata[212]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[212]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [212]));\n (* SOFT_HLUTNM = \"soft_lutpair1410\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[213]_i_1 \n (.I0(s_axi_wdata[213]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[213]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [213]));\n (* SOFT_HLUTNM = \"soft_lutpair1411\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[214]_i_1 \n (.I0(s_axi_wdata[214]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[214]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [214]));\n (* SOFT_HLUTNM = \"soft_lutpair1412\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[215]_i_1 \n (.I0(s_axi_wdata[215]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[215]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [215]));\n (* SOFT_HLUTNM = \"soft_lutpair1413\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[216]_i_1 \n (.I0(s_axi_wdata[216]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[216]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [216]));\n (* SOFT_HLUTNM = \"soft_lutpair1414\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[217]_i_1 \n (.I0(s_axi_wdata[217]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[217]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [217]));\n (* SOFT_HLUTNM = \"soft_lutpair1415\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[218]_i_1 \n (.I0(s_axi_wdata[218]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[218]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [218]));\n (* SOFT_HLUTNM = \"soft_lutpair1416\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[219]_i_1 \n (.I0(s_axi_wdata[219]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[219]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [219]));\n (* SOFT_HLUTNM = \"soft_lutpair1218\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[21]_i_1 \n (.I0(s_axi_wdata[21]),\n .I1(s_axi_wready),\n .I2(wdf_data[21]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [21]));\n (* SOFT_HLUTNM = \"soft_lutpair1417\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[220]_i_1 \n (.I0(s_axi_wdata[220]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[220]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [220]));\n (* SOFT_HLUTNM = \"soft_lutpair1418\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[221]_i_1 \n (.I0(s_axi_wdata[221]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[221]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [221]));\n (* SOFT_HLUTNM = \"soft_lutpair1419\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[222]_i_1 \n (.I0(s_axi_wdata[222]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[222]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [222]));\n (* SOFT_HLUTNM = \"soft_lutpair1420\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[223]_i_1 \n (.I0(s_axi_wdata[223]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[223]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [223]));\n (* SOFT_HLUTNM = \"soft_lutpair1421\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[224]_i_1 \n (.I0(s_axi_wdata[224]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[224]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [224]));\n (* SOFT_HLUTNM = \"soft_lutpair1422\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[225]_i_1 \n (.I0(s_axi_wdata[225]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[225]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [225]));\n (* SOFT_HLUTNM = \"soft_lutpair1423\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[226]_i_1 \n (.I0(s_axi_wdata[226]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[226]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [226]));\n (* SOFT_HLUTNM = \"soft_lutpair1424\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[227]_i_1 \n (.I0(s_axi_wdata[227]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[227]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [227]));\n (* SOFT_HLUTNM = \"soft_lutpair1425\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[228]_i_1 \n (.I0(s_axi_wdata[228]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[228]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [228]));\n (* SOFT_HLUTNM = \"soft_lutpair1426\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[229]_i_1 \n (.I0(s_axi_wdata[229]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[229]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [229]));\n (* SOFT_HLUTNM = \"soft_lutpair1219\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[22]_i_1 \n (.I0(s_axi_wdata[22]),\n .I1(s_axi_wready),\n .I2(wdf_data[22]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [22]));\n (* SOFT_HLUTNM = \"soft_lutpair1427\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[230]_i_1 \n (.I0(s_axi_wdata[230]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[230]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [230]));\n (* SOFT_HLUTNM = \"soft_lutpair1428\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[231]_i_1 \n (.I0(s_axi_wdata[231]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[231]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [231]));\n (* SOFT_HLUTNM = \"soft_lutpair1429\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[232]_i_1 \n (.I0(s_axi_wdata[232]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[232]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [232]));\n (* SOFT_HLUTNM = \"soft_lutpair1430\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[233]_i_1 \n (.I0(s_axi_wdata[233]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[233]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [233]));\n (* SOFT_HLUTNM = \"soft_lutpair1431\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[234]_i_1 \n (.I0(s_axi_wdata[234]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[234]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [234]));\n (* SOFT_HLUTNM = \"soft_lutpair1432\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[235]_i_1 \n (.I0(s_axi_wdata[235]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[235]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [235]));\n (* SOFT_HLUTNM = \"soft_lutpair1433\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[236]_i_1 \n (.I0(s_axi_wdata[236]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[236]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [236]));\n (* SOFT_HLUTNM = \"soft_lutpair1434\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[237]_i_1 \n (.I0(s_axi_wdata[237]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[237]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [237]));\n (* SOFT_HLUTNM = \"soft_lutpair1435\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[238]_i_1 \n (.I0(s_axi_wdata[238]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[238]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [238]));\n (* SOFT_HLUTNM = \"soft_lutpair1436\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[239]_i_1 \n (.I0(s_axi_wdata[239]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[239]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [239]));\n (* SOFT_HLUTNM = \"soft_lutpair1220\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[23]_i_1 \n (.I0(s_axi_wdata[23]),\n .I1(s_axi_wready),\n .I2(wdf_data[23]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [23]));\n (* SOFT_HLUTNM = \"soft_lutpair1437\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[240]_i_1 \n (.I0(s_axi_wdata[240]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[240]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [240]));\n (* SOFT_HLUTNM = \"soft_lutpair1438\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[241]_i_1 \n (.I0(s_axi_wdata[241]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[241]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [241]));\n (* SOFT_HLUTNM = \"soft_lutpair1439\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[242]_i_1 \n (.I0(s_axi_wdata[242]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[242]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [242]));\n (* SOFT_HLUTNM = \"soft_lutpair1440\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[243]_i_1 \n (.I0(s_axi_wdata[243]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[243]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [243]));\n (* SOFT_HLUTNM = \"soft_lutpair1441\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[244]_i_1 \n (.I0(s_axi_wdata[244]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[244]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [244]));\n (* SOFT_HLUTNM = \"soft_lutpair1442\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[245]_i_1 \n (.I0(s_axi_wdata[245]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[245]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [245]));\n (* SOFT_HLUTNM = \"soft_lutpair1443\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[246]_i_1 \n (.I0(s_axi_wdata[246]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[246]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [246]));\n (* SOFT_HLUTNM = \"soft_lutpair1444\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[247]_i_1 \n (.I0(s_axi_wdata[247]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[247]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [247]));\n (* SOFT_HLUTNM = \"soft_lutpair1445\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[248]_i_1 \n (.I0(s_axi_wdata[248]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[248]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [248]));\n (* SOFT_HLUTNM = \"soft_lutpair1446\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[249]_i_1 \n (.I0(s_axi_wdata[249]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[249]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [249]));\n (* SOFT_HLUTNM = \"soft_lutpair1221\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[24]_i_1 \n (.I0(s_axi_wdata[24]),\n .I1(s_axi_wready),\n .I2(wdf_data[24]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [24]));\n (* SOFT_HLUTNM = \"soft_lutpair1447\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[250]_i_1 \n (.I0(s_axi_wdata[250]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[250]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [250]));\n (* SOFT_HLUTNM = \"soft_lutpair1448\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[251]_i_1 \n (.I0(s_axi_wdata[251]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[251]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [251]));\n (* SOFT_HLUTNM = \"soft_lutpair1449\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[252]_i_1 \n (.I0(s_axi_wdata[252]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[252]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [252]));\n (* SOFT_HLUTNM = \"soft_lutpair1450\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[253]_i_1 \n (.I0(s_axi_wdata[253]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[253]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [253]));\n (* SOFT_HLUTNM = \"soft_lutpair1451\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[254]_i_1 \n (.I0(s_axi_wdata[254]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[254]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [254]));\n (* SOFT_HLUTNM = \"soft_lutpair1452\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[255]_i_1 \n (.I0(s_axi_wdata[255]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_data[255]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [255]));\n (* SOFT_HLUTNM = \"soft_lutpair1222\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[25]_i_1 \n (.I0(s_axi_wdata[25]),\n .I1(s_axi_wready),\n .I2(wdf_data[25]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [25]));\n (* SOFT_HLUTNM = \"soft_lutpair1223\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[26]_i_1 \n (.I0(s_axi_wdata[26]),\n .I1(s_axi_wready),\n .I2(wdf_data[26]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [26]));\n (* SOFT_HLUTNM = \"soft_lutpair1224\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[27]_i_1 \n (.I0(s_axi_wdata[27]),\n .I1(s_axi_wready),\n .I2(wdf_data[27]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [27]));\n (* SOFT_HLUTNM = \"soft_lutpair1225\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[28]_i_1 \n (.I0(s_axi_wdata[28]),\n .I1(s_axi_wready),\n .I2(wdf_data[28]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [28]));\n (* SOFT_HLUTNM = \"soft_lutpair1226\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[29]_i_1 \n (.I0(s_axi_wdata[29]),\n .I1(s_axi_wready),\n .I2(wdf_data[29]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [29]));\n (* SOFT_HLUTNM = \"soft_lutpair1199\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[2]_i_1 \n (.I0(s_axi_wdata[2]),\n .I1(s_axi_wready),\n .I2(wdf_data[2]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [2]));\n (* SOFT_HLUTNM = \"soft_lutpair1227\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[30]_i_1 \n (.I0(s_axi_wdata[30]),\n .I1(s_axi_wready),\n .I2(wdf_data[30]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [30]));\n (* SOFT_HLUTNM = \"soft_lutpair1228\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[31]_i_1 \n (.I0(s_axi_wdata[31]),\n .I1(s_axi_wready),\n .I2(wdf_data[31]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [31]));\n (* SOFT_HLUTNM = \"soft_lutpair1229\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[32]_i_1 \n (.I0(s_axi_wdata[32]),\n .I1(s_axi_wready),\n .I2(wdf_data[32]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [32]));\n (* SOFT_HLUTNM = \"soft_lutpair1230\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[33]_i_1 \n (.I0(s_axi_wdata[33]),\n .I1(s_axi_wready),\n .I2(wdf_data[33]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [33]));\n (* SOFT_HLUTNM = \"soft_lutpair1231\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[34]_i_1 \n (.I0(s_axi_wdata[34]),\n .I1(s_axi_wready),\n .I2(wdf_data[34]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [34]));\n (* SOFT_HLUTNM = \"soft_lutpair1232\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[35]_i_1 \n (.I0(s_axi_wdata[35]),\n .I1(s_axi_wready),\n .I2(wdf_data[35]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [35]));\n (* SOFT_HLUTNM = \"soft_lutpair1233\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[36]_i_1 \n (.I0(s_axi_wdata[36]),\n .I1(s_axi_wready),\n .I2(wdf_data[36]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [36]));\n (* SOFT_HLUTNM = \"soft_lutpair1234\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[37]_i_1 \n (.I0(s_axi_wdata[37]),\n .I1(s_axi_wready),\n .I2(wdf_data[37]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [37]));\n (* SOFT_HLUTNM = \"soft_lutpair1235\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[38]_i_1 \n (.I0(s_axi_wdata[38]),\n .I1(s_axi_wready),\n .I2(wdf_data[38]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [38]));\n (* SOFT_HLUTNM = \"soft_lutpair1236\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[39]_i_1 \n (.I0(s_axi_wdata[39]),\n .I1(s_axi_wready),\n .I2(wdf_data[39]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [39]));\n (* SOFT_HLUTNM = \"soft_lutpair1200\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[3]_i_1 \n (.I0(s_axi_wdata[3]),\n .I1(s_axi_wready),\n .I2(wdf_data[3]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [3]));\n (* SOFT_HLUTNM = \"soft_lutpair1237\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[40]_i_1 \n (.I0(s_axi_wdata[40]),\n .I1(s_axi_wready),\n .I2(wdf_data[40]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [40]));\n (* SOFT_HLUTNM = \"soft_lutpair1238\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[41]_i_1 \n (.I0(s_axi_wdata[41]),\n .I1(s_axi_wready),\n .I2(wdf_data[41]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [41]));\n (* SOFT_HLUTNM = \"soft_lutpair1239\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[42]_i_1 \n (.I0(s_axi_wdata[42]),\n .I1(s_axi_wready),\n .I2(wdf_data[42]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [42]));\n (* SOFT_HLUTNM = \"soft_lutpair1240\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[43]_i_1 \n (.I0(s_axi_wdata[43]),\n .I1(s_axi_wready),\n .I2(wdf_data[43]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [43]));\n (* SOFT_HLUTNM = \"soft_lutpair1241\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[44]_i_1 \n (.I0(s_axi_wdata[44]),\n .I1(s_axi_wready),\n .I2(wdf_data[44]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [44]));\n (* SOFT_HLUTNM = \"soft_lutpair1242\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[45]_i_1 \n (.I0(s_axi_wdata[45]),\n .I1(s_axi_wready),\n .I2(wdf_data[45]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [45]));\n (* SOFT_HLUTNM = \"soft_lutpair1243\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[46]_i_1 \n (.I0(s_axi_wdata[46]),\n .I1(s_axi_wready),\n .I2(wdf_data[46]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [46]));\n (* SOFT_HLUTNM = \"soft_lutpair1244\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[47]_i_1 \n (.I0(s_axi_wdata[47]),\n .I1(s_axi_wready),\n .I2(wdf_data[47]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [47]));\n (* SOFT_HLUTNM = \"soft_lutpair1245\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[48]_i_1 \n (.I0(s_axi_wdata[48]),\n .I1(s_axi_wready),\n .I2(wdf_data[48]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [48]));\n (* SOFT_HLUTNM = \"soft_lutpair1246\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[49]_i_1 \n (.I0(s_axi_wdata[49]),\n .I1(s_axi_wready),\n .I2(wdf_data[49]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [49]));\n (* SOFT_HLUTNM = \"soft_lutpair1201\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[4]_i_1 \n (.I0(s_axi_wdata[4]),\n .I1(s_axi_wready),\n .I2(wdf_data[4]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [4]));\n (* SOFT_HLUTNM = \"soft_lutpair1247\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[50]_i_1 \n (.I0(s_axi_wdata[50]),\n .I1(s_axi_wready),\n .I2(wdf_data[50]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [50]));\n (* SOFT_HLUTNM = \"soft_lutpair1248\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[51]_i_1 \n (.I0(s_axi_wdata[51]),\n .I1(s_axi_wready),\n .I2(wdf_data[51]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [51]));\n (* SOFT_HLUTNM = \"soft_lutpair1249\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[52]_i_1 \n (.I0(s_axi_wdata[52]),\n .I1(s_axi_wready),\n .I2(wdf_data[52]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [52]));\n (* SOFT_HLUTNM = \"soft_lutpair1250\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[53]_i_1 \n (.I0(s_axi_wdata[53]),\n .I1(s_axi_wready),\n .I2(wdf_data[53]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [53]));\n (* SOFT_HLUTNM = \"soft_lutpair1251\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[54]_i_1 \n (.I0(s_axi_wdata[54]),\n .I1(s_axi_wready),\n .I2(wdf_data[54]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [54]));\n (* SOFT_HLUTNM = \"soft_lutpair1252\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[55]_i_1 \n (.I0(s_axi_wdata[55]),\n .I1(s_axi_wready),\n .I2(wdf_data[55]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [55]));\n (* SOFT_HLUTNM = \"soft_lutpair1253\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[56]_i_1 \n (.I0(s_axi_wdata[56]),\n .I1(s_axi_wready),\n .I2(wdf_data[56]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [56]));\n (* SOFT_HLUTNM = \"soft_lutpair1254\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[57]_i_1 \n (.I0(s_axi_wdata[57]),\n .I1(s_axi_wready),\n .I2(wdf_data[57]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [57]));\n (* SOFT_HLUTNM = \"soft_lutpair1255\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[58]_i_1 \n (.I0(s_axi_wdata[58]),\n .I1(s_axi_wready),\n .I2(wdf_data[58]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [58]));\n (* SOFT_HLUTNM = \"soft_lutpair1256\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[59]_i_1 \n (.I0(s_axi_wdata[59]),\n .I1(s_axi_wready),\n .I2(wdf_data[59]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [59]));\n (* SOFT_HLUTNM = \"soft_lutpair1202\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[5]_i_1 \n (.I0(s_axi_wdata[5]),\n .I1(s_axi_wready),\n .I2(wdf_data[5]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [5]));\n (* SOFT_HLUTNM = \"soft_lutpair1257\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[60]_i_1 \n (.I0(s_axi_wdata[60]),\n .I1(s_axi_wready),\n .I2(wdf_data[60]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [60]));\n (* SOFT_HLUTNM = \"soft_lutpair1258\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[61]_i_1 \n (.I0(s_axi_wdata[61]),\n .I1(s_axi_wready),\n .I2(wdf_data[61]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [61]));\n (* SOFT_HLUTNM = \"soft_lutpair1259\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[62]_i_1 \n (.I0(s_axi_wdata[62]),\n .I1(s_axi_wready),\n .I2(wdf_data[62]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [62]));\n (* SOFT_HLUTNM = \"soft_lutpair1260\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[63]_i_1 \n (.I0(s_axi_wdata[63]),\n .I1(s_axi_wready),\n .I2(wdf_data[63]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [63]));\n (* SOFT_HLUTNM = \"soft_lutpair1261\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[64]_i_1 \n (.I0(s_axi_wdata[64]),\n .I1(s_axi_wready),\n .I2(wdf_data[64]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [64]));\n (* SOFT_HLUTNM = \"soft_lutpair1262\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[65]_i_1 \n (.I0(s_axi_wdata[65]),\n .I1(s_axi_wready),\n .I2(wdf_data[65]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [65]));\n (* SOFT_HLUTNM = \"soft_lutpair1263\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[66]_i_1 \n (.I0(s_axi_wdata[66]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[66]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [66]));\n (* SOFT_HLUTNM = \"soft_lutpair1264\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[67]_i_1 \n (.I0(s_axi_wdata[67]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[67]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [67]));\n (* SOFT_HLUTNM = \"soft_lutpair1265\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[68]_i_1 \n (.I0(s_axi_wdata[68]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[68]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [68]));\n (* SOFT_HLUTNM = \"soft_lutpair1266\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[69]_i_1 \n (.I0(s_axi_wdata[69]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[69]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [69]));\n (* SOFT_HLUTNM = \"soft_lutpair1203\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[6]_i_1 \n (.I0(s_axi_wdata[6]),\n .I1(s_axi_wready),\n .I2(wdf_data[6]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [6]));\n (* SOFT_HLUTNM = \"soft_lutpair1267\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[70]_i_1 \n (.I0(s_axi_wdata[70]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[70]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [70]));\n (* SOFT_HLUTNM = \"soft_lutpair1268\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[71]_i_1 \n (.I0(s_axi_wdata[71]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[71]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [71]));\n (* SOFT_HLUTNM = \"soft_lutpair1269\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[72]_i_1 \n (.I0(s_axi_wdata[72]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[72]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [72]));\n (* SOFT_HLUTNM = \"soft_lutpair1270\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[73]_i_1 \n (.I0(s_axi_wdata[73]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[73]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [73]));\n (* SOFT_HLUTNM = \"soft_lutpair1271\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[74]_i_1 \n (.I0(s_axi_wdata[74]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[74]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [74]));\n (* SOFT_HLUTNM = \"soft_lutpair1272\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[75]_i_1 \n (.I0(s_axi_wdata[75]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[75]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [75]));\n (* SOFT_HLUTNM = \"soft_lutpair1273\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[76]_i_1 \n (.I0(s_axi_wdata[76]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[76]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [76]));\n (* SOFT_HLUTNM = \"soft_lutpair1274\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[77]_i_1 \n (.I0(s_axi_wdata[77]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[77]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [77]));\n (* SOFT_HLUTNM = \"soft_lutpair1275\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[78]_i_1 \n (.I0(s_axi_wdata[78]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[78]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [78]));\n (* SOFT_HLUTNM = \"soft_lutpair1276\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[79]_i_1 \n (.I0(s_axi_wdata[79]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[79]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [79]));\n (* SOFT_HLUTNM = \"soft_lutpair1204\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[7]_i_1 \n (.I0(s_axi_wdata[7]),\n .I1(s_axi_wready),\n .I2(wdf_data[7]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [7]));\n (* SOFT_HLUTNM = \"soft_lutpair1277\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[80]_i_1 \n (.I0(s_axi_wdata[80]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[80]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [80]));\n (* SOFT_HLUTNM = \"soft_lutpair1278\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[81]_i_1 \n (.I0(s_axi_wdata[81]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[81]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [81]));\n (* SOFT_HLUTNM = \"soft_lutpair1279\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[82]_i_1 \n (.I0(s_axi_wdata[82]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[82]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [82]));\n (* SOFT_HLUTNM = \"soft_lutpair1280\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[83]_i_1 \n (.I0(s_axi_wdata[83]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[83]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [83]));\n (* SOFT_HLUTNM = \"soft_lutpair1281\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[84]_i_1 \n (.I0(s_axi_wdata[84]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[84]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [84]));\n (* SOFT_HLUTNM = \"soft_lutpair1282\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[85]_i_1 \n (.I0(s_axi_wdata[85]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[85]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [85]));\n (* SOFT_HLUTNM = \"soft_lutpair1283\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[86]_i_1 \n (.I0(s_axi_wdata[86]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[86]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [86]));\n (* SOFT_HLUTNM = \"soft_lutpair1284\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[87]_i_1 \n (.I0(s_axi_wdata[87]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[87]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [87]));\n (* SOFT_HLUTNM = \"soft_lutpair1285\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[88]_i_1 \n (.I0(s_axi_wdata[88]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[88]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [88]));\n (* SOFT_HLUTNM = \"soft_lutpair1286\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[89]_i_1 \n (.I0(s_axi_wdata[89]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[89]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [89]));\n (* SOFT_HLUTNM = \"soft_lutpair1205\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[8]_i_1 \n (.I0(s_axi_wdata[8]),\n .I1(s_axi_wready),\n .I2(wdf_data[8]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [8]));\n (* SOFT_HLUTNM = \"soft_lutpair1287\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[90]_i_1 \n (.I0(s_axi_wdata[90]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[90]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [90]));\n (* SOFT_HLUTNM = \"soft_lutpair1288\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[91]_i_1 \n (.I0(s_axi_wdata[91]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[91]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [91]));\n (* SOFT_HLUTNM = \"soft_lutpair1289\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[92]_i_1 \n (.I0(s_axi_wdata[92]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[92]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [92]));\n (* SOFT_HLUTNM = \"soft_lutpair1290\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[93]_i_1 \n (.I0(s_axi_wdata[93]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[93]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [93]));\n (* SOFT_HLUTNM = \"soft_lutpair1291\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[94]_i_1 \n (.I0(s_axi_wdata[94]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[94]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [94]));\n (* SOFT_HLUTNM = \"soft_lutpair1292\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[95]_i_1 \n (.I0(s_axi_wdata[95]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[95]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [95]));\n (* SOFT_HLUTNM = \"soft_lutpair1293\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[96]_i_1 \n (.I0(s_axi_wdata[96]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[96]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [96]));\n (* SOFT_HLUTNM = \"soft_lutpair1294\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[97]_i_1 \n (.I0(s_axi_wdata[97]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[97]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [97]));\n (* SOFT_HLUTNM = \"soft_lutpair1295\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[98]_i_1 \n (.I0(s_axi_wdata[98]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[98]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [98]));\n (* SOFT_HLUTNM = \"soft_lutpair1296\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[99]_i_1 \n (.I0(s_axi_wdata[99]),\n .I1(wready_reg_rep_n_0),\n .I2(wdf_data[99]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [99]));\n (* SOFT_HLUTNM = \"soft_lutpair1206\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mc_app_wdf_data_reg[9]_i_1 \n (.I0(s_axi_wdata[9]),\n .I1(s_axi_wready),\n .I2(wdf_data[9]),\n .O(\\mc_app_wdf_data_reg_reg[255]_0 [9]));\n FDRE \\mc_app_wdf_data_reg_reg[0] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [0]),\n .Q(mc_app_wdf_data_reg[0]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[100] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [100]),\n .Q(mc_app_wdf_data_reg[100]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[101] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [101]),\n .Q(mc_app_wdf_data_reg[101]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[102] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [102]),\n .Q(mc_app_wdf_data_reg[102]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[103] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [103]),\n .Q(mc_app_wdf_data_reg[103]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[104] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [104]),\n .Q(mc_app_wdf_data_reg[104]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[105] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [105]),\n .Q(mc_app_wdf_data_reg[105]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[106] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [106]),\n .Q(mc_app_wdf_data_reg[106]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[107] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [107]),\n .Q(mc_app_wdf_data_reg[107]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[108] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [108]),\n .Q(mc_app_wdf_data_reg[108]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[109] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [109]),\n .Q(mc_app_wdf_data_reg[109]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[10] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [10]),\n .Q(mc_app_wdf_data_reg[10]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[110] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [110]),\n .Q(mc_app_wdf_data_reg[110]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[111] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [111]),\n .Q(mc_app_wdf_data_reg[111]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[112] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [112]),\n .Q(mc_app_wdf_data_reg[112]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[113] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [113]),\n .Q(mc_app_wdf_data_reg[113]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[114] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [114]),\n .Q(mc_app_wdf_data_reg[114]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[115] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [115]),\n .Q(mc_app_wdf_data_reg[115]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[116] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [116]),\n .Q(mc_app_wdf_data_reg[116]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[117] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [117]),\n .Q(mc_app_wdf_data_reg[117]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[118] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [118]),\n .Q(mc_app_wdf_data_reg[118]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[119] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [119]),\n .Q(mc_app_wdf_data_reg[119]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[11] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [11]),\n .Q(mc_app_wdf_data_reg[11]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[120] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [120]),\n .Q(mc_app_wdf_data_reg[120]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[121] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [121]),\n .Q(mc_app_wdf_data_reg[121]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[122] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [122]),\n .Q(mc_app_wdf_data_reg[122]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[123] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [123]),\n .Q(mc_app_wdf_data_reg[123]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[124] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [124]),\n .Q(mc_app_wdf_data_reg[124]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[125] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [125]),\n .Q(mc_app_wdf_data_reg[125]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[126] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [126]),\n .Q(mc_app_wdf_data_reg[126]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[127] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [127]),\n .Q(mc_app_wdf_data_reg[127]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[128] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [128]),\n .Q(mc_app_wdf_data_reg[128]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[129] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [129]),\n .Q(mc_app_wdf_data_reg[129]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[12] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [12]),\n .Q(mc_app_wdf_data_reg[12]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[130] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [130]),\n .Q(mc_app_wdf_data_reg[130]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[131] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [131]),\n .Q(mc_app_wdf_data_reg[131]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[132] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [132]),\n .Q(mc_app_wdf_data_reg[132]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[133] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [133]),\n .Q(mc_app_wdf_data_reg[133]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[134] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [134]),\n .Q(mc_app_wdf_data_reg[134]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[135] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [135]),\n .Q(mc_app_wdf_data_reg[135]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[136] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [136]),\n .Q(mc_app_wdf_data_reg[136]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[137] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [137]),\n .Q(mc_app_wdf_data_reg[137]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[138] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [138]),\n .Q(mc_app_wdf_data_reg[138]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[139] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [139]),\n .Q(mc_app_wdf_data_reg[139]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[13] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [13]),\n .Q(mc_app_wdf_data_reg[13]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[140] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [140]),\n .Q(mc_app_wdf_data_reg[140]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[141] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [141]),\n .Q(mc_app_wdf_data_reg[141]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[142] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [142]),\n .Q(mc_app_wdf_data_reg[142]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[143] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [143]),\n .Q(mc_app_wdf_data_reg[143]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[144] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [144]),\n .Q(mc_app_wdf_data_reg[144]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[145] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [145]),\n .Q(mc_app_wdf_data_reg[145]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[146] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [146]),\n .Q(mc_app_wdf_data_reg[146]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[147] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [147]),\n .Q(mc_app_wdf_data_reg[147]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[148] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [148]),\n .Q(mc_app_wdf_data_reg[148]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[149] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [149]),\n .Q(mc_app_wdf_data_reg[149]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[14] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [14]),\n .Q(mc_app_wdf_data_reg[14]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[150] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [150]),\n .Q(mc_app_wdf_data_reg[150]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[151] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [151]),\n .Q(mc_app_wdf_data_reg[151]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[152] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [152]),\n .Q(mc_app_wdf_data_reg[152]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[153] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [153]),\n .Q(mc_app_wdf_data_reg[153]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[154] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [154]),\n .Q(mc_app_wdf_data_reg[154]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[155] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [155]),\n .Q(mc_app_wdf_data_reg[155]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[156] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [156]),\n .Q(mc_app_wdf_data_reg[156]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[157] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [157]),\n .Q(mc_app_wdf_data_reg[157]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[158] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [158]),\n .Q(mc_app_wdf_data_reg[158]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[159] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [159]),\n .Q(mc_app_wdf_data_reg[159]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[15] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [15]),\n .Q(mc_app_wdf_data_reg[15]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[160] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [160]),\n .Q(mc_app_wdf_data_reg[160]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[161] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [161]),\n .Q(mc_app_wdf_data_reg[161]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[162] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [162]),\n .Q(mc_app_wdf_data_reg[162]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[163] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [163]),\n .Q(mc_app_wdf_data_reg[163]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[164] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [164]),\n .Q(mc_app_wdf_data_reg[164]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[165] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [165]),\n .Q(mc_app_wdf_data_reg[165]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[166] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [166]),\n .Q(mc_app_wdf_data_reg[166]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[167] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [167]),\n .Q(mc_app_wdf_data_reg[167]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[168] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [168]),\n .Q(mc_app_wdf_data_reg[168]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[169] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [169]),\n .Q(mc_app_wdf_data_reg[169]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[16] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [16]),\n .Q(mc_app_wdf_data_reg[16]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[170] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [170]),\n .Q(mc_app_wdf_data_reg[170]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[171] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [171]),\n .Q(mc_app_wdf_data_reg[171]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[172] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [172]),\n .Q(mc_app_wdf_data_reg[172]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[173] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [173]),\n .Q(mc_app_wdf_data_reg[173]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[174] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [174]),\n .Q(mc_app_wdf_data_reg[174]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[175] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [175]),\n .Q(mc_app_wdf_data_reg[175]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[176] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [176]),\n .Q(mc_app_wdf_data_reg[176]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[177] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [177]),\n .Q(mc_app_wdf_data_reg[177]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[178] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [178]),\n .Q(mc_app_wdf_data_reg[178]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[179] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [179]),\n .Q(mc_app_wdf_data_reg[179]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[17] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [17]),\n .Q(mc_app_wdf_data_reg[17]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[180] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [180]),\n .Q(mc_app_wdf_data_reg[180]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[181] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [181]),\n .Q(mc_app_wdf_data_reg[181]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[182] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [182]),\n .Q(mc_app_wdf_data_reg[182]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[183] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [183]),\n .Q(mc_app_wdf_data_reg[183]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[184] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [184]),\n .Q(mc_app_wdf_data_reg[184]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[185] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [185]),\n .Q(mc_app_wdf_data_reg[185]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[186] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [186]),\n .Q(mc_app_wdf_data_reg[186]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[187] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [187]),\n .Q(mc_app_wdf_data_reg[187]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[188] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [188]),\n .Q(mc_app_wdf_data_reg[188]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[189] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [189]),\n .Q(mc_app_wdf_data_reg[189]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[18] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [18]),\n .Q(mc_app_wdf_data_reg[18]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[190] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [190]),\n .Q(mc_app_wdf_data_reg[190]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[191] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [191]),\n .Q(mc_app_wdf_data_reg[191]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[192] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [192]),\n .Q(mc_app_wdf_data_reg[192]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[193] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [193]),\n .Q(mc_app_wdf_data_reg[193]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[194] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [194]),\n .Q(mc_app_wdf_data_reg[194]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[195] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [195]),\n .Q(mc_app_wdf_data_reg[195]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[196] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [196]),\n .Q(mc_app_wdf_data_reg[196]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[197] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [197]),\n .Q(mc_app_wdf_data_reg[197]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[198] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [198]),\n .Q(mc_app_wdf_data_reg[198]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[199] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [199]),\n .Q(mc_app_wdf_data_reg[199]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[19] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [19]),\n .Q(mc_app_wdf_data_reg[19]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[1] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [1]),\n .Q(mc_app_wdf_data_reg[1]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[200] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [200]),\n .Q(mc_app_wdf_data_reg[200]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[201] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [201]),\n .Q(mc_app_wdf_data_reg[201]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[202] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [202]),\n .Q(mc_app_wdf_data_reg[202]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[203] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [203]),\n .Q(mc_app_wdf_data_reg[203]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[204] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [204]),\n .Q(mc_app_wdf_data_reg[204]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[205] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [205]),\n .Q(mc_app_wdf_data_reg[205]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[206] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [206]),\n .Q(mc_app_wdf_data_reg[206]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[207] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [207]),\n .Q(mc_app_wdf_data_reg[207]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[208] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [208]),\n .Q(mc_app_wdf_data_reg[208]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[209] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [209]),\n .Q(mc_app_wdf_data_reg[209]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[20] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [20]),\n .Q(mc_app_wdf_data_reg[20]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[210] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [210]),\n .Q(mc_app_wdf_data_reg[210]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[211] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [211]),\n .Q(mc_app_wdf_data_reg[211]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[212] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [212]),\n .Q(mc_app_wdf_data_reg[212]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[213] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [213]),\n .Q(mc_app_wdf_data_reg[213]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[214] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [214]),\n .Q(mc_app_wdf_data_reg[214]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[215] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [215]),\n .Q(mc_app_wdf_data_reg[215]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[216] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [216]),\n .Q(mc_app_wdf_data_reg[216]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[217] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [217]),\n .Q(mc_app_wdf_data_reg[217]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[218] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [218]),\n .Q(mc_app_wdf_data_reg[218]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[219] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [219]),\n .Q(mc_app_wdf_data_reg[219]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[21] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [21]),\n .Q(mc_app_wdf_data_reg[21]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[220] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [220]),\n .Q(mc_app_wdf_data_reg[220]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[221] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [221]),\n .Q(mc_app_wdf_data_reg[221]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[222] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [222]),\n .Q(mc_app_wdf_data_reg[222]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[223] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [223]),\n .Q(mc_app_wdf_data_reg[223]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[224] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [224]),\n .Q(mc_app_wdf_data_reg[224]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[225] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [225]),\n .Q(mc_app_wdf_data_reg[225]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[226] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [226]),\n .Q(mc_app_wdf_data_reg[226]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[227] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [227]),\n .Q(mc_app_wdf_data_reg[227]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[228] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [228]),\n .Q(mc_app_wdf_data_reg[228]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[229] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [229]),\n .Q(mc_app_wdf_data_reg[229]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[22] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [22]),\n .Q(mc_app_wdf_data_reg[22]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[230] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [230]),\n .Q(mc_app_wdf_data_reg[230]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[231] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [231]),\n .Q(mc_app_wdf_data_reg[231]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[232] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [232]),\n .Q(mc_app_wdf_data_reg[232]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[233] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [233]),\n .Q(mc_app_wdf_data_reg[233]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[234] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [234]),\n .Q(mc_app_wdf_data_reg[234]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[235] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [235]),\n .Q(mc_app_wdf_data_reg[235]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[236] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [236]),\n .Q(mc_app_wdf_data_reg[236]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[237] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [237]),\n .Q(mc_app_wdf_data_reg[237]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[238] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [238]),\n .Q(mc_app_wdf_data_reg[238]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[239] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [239]),\n .Q(mc_app_wdf_data_reg[239]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[23] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [23]),\n .Q(mc_app_wdf_data_reg[23]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[240] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [240]),\n .Q(mc_app_wdf_data_reg[240]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[241] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [241]),\n .Q(mc_app_wdf_data_reg[241]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[242] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [242]),\n .Q(mc_app_wdf_data_reg[242]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[243] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [243]),\n .Q(mc_app_wdf_data_reg[243]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[244] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [244]),\n .Q(mc_app_wdf_data_reg[244]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[245] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [245]),\n .Q(mc_app_wdf_data_reg[245]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[246] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [246]),\n .Q(mc_app_wdf_data_reg[246]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[247] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [247]),\n .Q(mc_app_wdf_data_reg[247]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[248] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [248]),\n .Q(mc_app_wdf_data_reg[248]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[249] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [249]),\n .Q(mc_app_wdf_data_reg[249]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[24] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [24]),\n .Q(mc_app_wdf_data_reg[24]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[250] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [250]),\n .Q(mc_app_wdf_data_reg[250]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[251] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [251]),\n .Q(mc_app_wdf_data_reg[251]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[252] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [252]),\n .Q(mc_app_wdf_data_reg[252]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[253] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [253]),\n .Q(mc_app_wdf_data_reg[253]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[254] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [254]),\n .Q(mc_app_wdf_data_reg[254]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[255] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [255]),\n .Q(mc_app_wdf_data_reg[255]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[25] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [25]),\n .Q(mc_app_wdf_data_reg[25]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[26] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [26]),\n .Q(mc_app_wdf_data_reg[26]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[27] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [27]),\n .Q(mc_app_wdf_data_reg[27]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[28] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [28]),\n .Q(mc_app_wdf_data_reg[28]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[29] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [29]),\n .Q(mc_app_wdf_data_reg[29]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[2] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [2]),\n .Q(mc_app_wdf_data_reg[2]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[30] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [30]),\n .Q(mc_app_wdf_data_reg[30]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[31] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [31]),\n .Q(mc_app_wdf_data_reg[31]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[32] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [32]),\n .Q(mc_app_wdf_data_reg[32]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[33] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [33]),\n .Q(mc_app_wdf_data_reg[33]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[34] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [34]),\n .Q(mc_app_wdf_data_reg[34]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[35] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [35]),\n .Q(mc_app_wdf_data_reg[35]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[36] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [36]),\n .Q(mc_app_wdf_data_reg[36]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[37] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [37]),\n .Q(mc_app_wdf_data_reg[37]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[38] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [38]),\n .Q(mc_app_wdf_data_reg[38]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[39] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [39]),\n .Q(mc_app_wdf_data_reg[39]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[3] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [3]),\n .Q(mc_app_wdf_data_reg[3]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[40] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [40]),\n .Q(mc_app_wdf_data_reg[40]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[41] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [41]),\n .Q(mc_app_wdf_data_reg[41]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[42] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [42]),\n .Q(mc_app_wdf_data_reg[42]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[43] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [43]),\n .Q(mc_app_wdf_data_reg[43]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[44] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [44]),\n .Q(mc_app_wdf_data_reg[44]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[45] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [45]),\n .Q(mc_app_wdf_data_reg[45]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[46] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [46]),\n .Q(mc_app_wdf_data_reg[46]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[47] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [47]),\n .Q(mc_app_wdf_data_reg[47]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[48] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [48]),\n .Q(mc_app_wdf_data_reg[48]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[49] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [49]),\n .Q(mc_app_wdf_data_reg[49]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[4] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [4]),\n .Q(mc_app_wdf_data_reg[4]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[50] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [50]),\n .Q(mc_app_wdf_data_reg[50]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[51] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [51]),\n .Q(mc_app_wdf_data_reg[51]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[52] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [52]),\n .Q(mc_app_wdf_data_reg[52]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[53] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [53]),\n .Q(mc_app_wdf_data_reg[53]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[54] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [54]),\n .Q(mc_app_wdf_data_reg[54]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[55] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [55]),\n .Q(mc_app_wdf_data_reg[55]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[56] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [56]),\n .Q(mc_app_wdf_data_reg[56]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[57] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [57]),\n .Q(mc_app_wdf_data_reg[57]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[58] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [58]),\n .Q(mc_app_wdf_data_reg[58]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[59] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [59]),\n .Q(mc_app_wdf_data_reg[59]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[5] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [5]),\n .Q(mc_app_wdf_data_reg[5]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[60] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [60]),\n .Q(mc_app_wdf_data_reg[60]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[61] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [61]),\n .Q(mc_app_wdf_data_reg[61]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[62] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [62]),\n .Q(mc_app_wdf_data_reg[62]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[63] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [63]),\n .Q(mc_app_wdf_data_reg[63]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[64] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [64]),\n .Q(mc_app_wdf_data_reg[64]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[65] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [65]),\n .Q(mc_app_wdf_data_reg[65]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[66] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [66]),\n .Q(mc_app_wdf_data_reg[66]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[67] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [67]),\n .Q(mc_app_wdf_data_reg[67]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[68] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [68]),\n .Q(mc_app_wdf_data_reg[68]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[69] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [69]),\n .Q(mc_app_wdf_data_reg[69]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[6] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [6]),\n .Q(mc_app_wdf_data_reg[6]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[70] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [70]),\n .Q(mc_app_wdf_data_reg[70]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[71] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [71]),\n .Q(mc_app_wdf_data_reg[71]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[72] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [72]),\n .Q(mc_app_wdf_data_reg[72]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[73] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [73]),\n .Q(mc_app_wdf_data_reg[73]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[74] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [74]),\n .Q(mc_app_wdf_data_reg[74]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[75] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [75]),\n .Q(mc_app_wdf_data_reg[75]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[76] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [76]),\n .Q(mc_app_wdf_data_reg[76]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[77] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [77]),\n .Q(mc_app_wdf_data_reg[77]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[78] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [78]),\n .Q(mc_app_wdf_data_reg[78]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[79] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [79]),\n .Q(mc_app_wdf_data_reg[79]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[7] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [7]),\n .Q(mc_app_wdf_data_reg[7]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[80] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [80]),\n .Q(mc_app_wdf_data_reg[80]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[81] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [81]),\n .Q(mc_app_wdf_data_reg[81]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[82] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [82]),\n .Q(mc_app_wdf_data_reg[82]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[83] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [83]),\n .Q(mc_app_wdf_data_reg[83]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[84] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [84]),\n .Q(mc_app_wdf_data_reg[84]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[85] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [85]),\n .Q(mc_app_wdf_data_reg[85]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[86] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [86]),\n .Q(mc_app_wdf_data_reg[86]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[87] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [87]),\n .Q(mc_app_wdf_data_reg[87]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[88] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [88]),\n .Q(mc_app_wdf_data_reg[88]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[89] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [89]),\n .Q(mc_app_wdf_data_reg[89]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[8] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [8]),\n .Q(mc_app_wdf_data_reg[8]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[90] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [90]),\n .Q(mc_app_wdf_data_reg[90]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[91] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [91]),\n .Q(mc_app_wdf_data_reg[91]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[92] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [92]),\n .Q(mc_app_wdf_data_reg[92]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[93] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [93]),\n .Q(mc_app_wdf_data_reg[93]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[94] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [94]),\n .Q(mc_app_wdf_data_reg[94]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[95] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [95]),\n .Q(mc_app_wdf_data_reg[95]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[96] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [96]),\n .Q(mc_app_wdf_data_reg[96]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[97] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [97]),\n .Q(mc_app_wdf_data_reg[97]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[98] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [98]),\n .Q(mc_app_wdf_data_reg[98]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[99] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [99]),\n .Q(mc_app_wdf_data_reg[99]),\n .R(1'b0));\n FDRE \\mc_app_wdf_data_reg_reg[9] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [9]),\n .Q(mc_app_wdf_data_reg[9]),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1453\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[0]_i_1 \n (.I0(s_axi_wstrb[0]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_mask[0]),\n .O(D[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1463\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[10]_i_1 \n (.I0(s_axi_wstrb[10]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[10]),\n .O(D[10]));\n (* SOFT_HLUTNM = \"soft_lutpair1464\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[11]_i_1 \n (.I0(s_axi_wstrb[11]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[11]),\n .O(D[11]));\n (* SOFT_HLUTNM = \"soft_lutpair1465\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[12]_i_1 \n (.I0(s_axi_wstrb[12]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[12]),\n .O(D[12]));\n (* SOFT_HLUTNM = \"soft_lutpair1466\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[13]_i_1 \n (.I0(s_axi_wstrb[13]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[13]),\n .O(D[13]));\n (* SOFT_HLUTNM = \"soft_lutpair1467\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[14]_i_1 \n (.I0(s_axi_wstrb[14]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[14]),\n .O(D[14]));\n (* SOFT_HLUTNM = \"soft_lutpair1468\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[15]_i_1 \n (.I0(s_axi_wstrb[15]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[15]),\n .O(D[15]));\n (* SOFT_HLUTNM = \"soft_lutpair1469\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[16]_i_1 \n (.I0(s_axi_wstrb[16]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[16]),\n .O(D[16]));\n (* SOFT_HLUTNM = \"soft_lutpair1470\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[17]_i_1 \n (.I0(s_axi_wstrb[17]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[17]),\n .O(D[17]));\n (* SOFT_HLUTNM = \"soft_lutpair1471\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[18]_i_1 \n (.I0(s_axi_wstrb[18]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[18]),\n .O(D[18]));\n (* SOFT_HLUTNM = \"soft_lutpair1472\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[19]_i_1 \n (.I0(s_axi_wstrb[19]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[19]),\n .O(D[19]));\n (* SOFT_HLUTNM = \"soft_lutpair1454\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[1]_i_1 \n (.I0(s_axi_wstrb[1]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_mask[1]),\n .O(D[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1473\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[20]_i_1 \n (.I0(s_axi_wstrb[20]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[20]),\n .O(D[20]));\n (* SOFT_HLUTNM = \"soft_lutpair1474\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[21]_i_1 \n (.I0(s_axi_wstrb[21]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[21]),\n .O(D[21]));\n (* SOFT_HLUTNM = \"soft_lutpair1475\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[22]_i_1 \n (.I0(s_axi_wstrb[22]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[22]),\n .O(D[22]));\n (* SOFT_HLUTNM = \"soft_lutpair1476\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[23]_i_1 \n (.I0(s_axi_wstrb[23]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[23]),\n .O(D[23]));\n (* SOFT_HLUTNM = \"soft_lutpair1477\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[24]_i_1 \n (.I0(s_axi_wstrb[24]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[24]),\n .O(D[24]));\n (* SOFT_HLUTNM = \"soft_lutpair1478\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[25]_i_1 \n (.I0(s_axi_wstrb[25]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[25]),\n .O(D[25]));\n (* SOFT_HLUTNM = \"soft_lutpair1479\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[26]_i_1 \n (.I0(s_axi_wstrb[26]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[26]),\n .O(D[26]));\n (* SOFT_HLUTNM = \"soft_lutpair1480\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[27]_i_1 \n (.I0(s_axi_wstrb[27]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[27]),\n .O(D[27]));\n (* SOFT_HLUTNM = \"soft_lutpair1481\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[28]_i_1 \n (.I0(s_axi_wstrb[28]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[28]),\n .O(D[28]));\n (* SOFT_HLUTNM = \"soft_lutpair1482\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[29]_i_1 \n (.I0(s_axi_wstrb[29]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[29]),\n .O(D[29]));\n (* SOFT_HLUTNM = \"soft_lutpair1455\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[2]_i_1 \n (.I0(s_axi_wstrb[2]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_mask[2]),\n .O(D[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1483\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[30]_i_1 \n (.I0(s_axi_wstrb[30]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[30]),\n .O(D[30]));\n (* SOFT_HLUTNM = \"soft_lutpair1484\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[31]_i_1 \n (.I0(s_axi_wstrb[31]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[31]),\n .O(D[31]));\n (* SOFT_HLUTNM = \"soft_lutpair1456\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[3]_i_1 \n (.I0(s_axi_wstrb[3]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_mask[3]),\n .O(D[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1457\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[4]_i_1 \n (.I0(s_axi_wstrb[4]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_mask[4]),\n .O(D[4]));\n (* SOFT_HLUTNM = \"soft_lutpair1458\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[5]_i_1 \n (.I0(s_axi_wstrb[5]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_mask[5]),\n .O(D[5]));\n (* SOFT_HLUTNM = \"soft_lutpair1459\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[6]_i_1 \n (.I0(s_axi_wstrb[6]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_mask[6]),\n .O(D[6]));\n (* SOFT_HLUTNM = \"soft_lutpair1460\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[7]_i_1 \n (.I0(s_axi_wstrb[7]),\n .I1(wready_reg_rep__1_n_0),\n .I2(wdf_mask[7]),\n .O(D[7]));\n (* SOFT_HLUTNM = \"soft_lutpair1461\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[8]_i_1 \n (.I0(s_axi_wstrb[8]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[8]),\n .O(D[8]));\n (* SOFT_HLUTNM = \"soft_lutpair1462\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\mc_app_wdf_mask_reg[9]_i_1 \n (.I0(s_axi_wstrb[9]),\n .I1(wready_reg_rep__2_n_0),\n .I2(wdf_mask[9]),\n .O(D[9]));\n FDRE \\mc_app_wdf_mask_reg_reg[0] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[0]),\n .Q(mc_app_wdf_mask_reg[0]),\n .R(areset_d1));\n FDRE \\mc_app_wdf_mask_reg_reg[10] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[10]),\n .Q(mc_app_wdf_mask_reg[10]),\n .R(areset_d1));\n FDRE \\mc_app_wdf_mask_reg_reg[11] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[11]),\n .Q(mc_app_wdf_mask_reg[11]),\n .R(areset_d1));\n FDRE \\mc_app_wdf_mask_reg_reg[12] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[12]),\n .Q(mc_app_wdf_mask_reg[12]),\n .R(areset_d1));\n FDRE \\mc_app_wdf_mask_reg_reg[13] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[13]),\n .Q(mc_app_wdf_mask_reg[13]),\n .R(areset_d1));\n FDRE \\mc_app_wdf_mask_reg_reg[14] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[14]),\n .Q(mc_app_wdf_mask_reg[14]),\n .R(areset_d1));\n FDRE \\mc_app_wdf_mask_reg_reg[15] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[15]),\n .Q(mc_app_wdf_mask_reg[15]),\n .R(areset_d1));\n FDRE \\mc_app_wdf_mask_reg_reg[16] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[16]),\n .Q(mc_app_wdf_mask_reg[16]),\n .R(areset_d1));\n FDRE \\mc_app_wdf_mask_reg_reg[17] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[17]),\n .Q(mc_app_wdf_mask_reg[17]),\n .R(areset_d1));\n FDRE \\mc_app_wdf_mask_reg_reg[18] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[18]),\n .Q(mc_app_wdf_mask_reg[18]),\n .R(areset_d1));\n FDRE \\mc_app_wdf_mask_reg_reg[19] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[19]),\n .Q(mc_app_wdf_mask_reg[19]),\n .R(areset_d1));\n FDRE \\mc_app_wdf_mask_reg_reg[1] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[1]),\n .Q(mc_app_wdf_mask_reg[1]),\n .R(areset_d1));\n FDRE \\mc_app_wdf_mask_reg_reg[20] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[20]),\n .Q(mc_app_wdf_mask_reg[20]),\n .R(areset_d1));\n FDRE \\mc_app_wdf_mask_reg_reg[21] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[21]),\n .Q(mc_app_wdf_mask_reg[21]),\n .R(areset_d1));\n FDRE \\mc_app_wdf_mask_reg_reg[22] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[22]),\n .Q(mc_app_wdf_mask_reg[22]),\n .R(areset_d1));\n FDRE \\mc_app_wdf_mask_reg_reg[23] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[23]),\n .Q(mc_app_wdf_mask_reg[23]),\n .R(areset_d1));\n FDRE \\mc_app_wdf_mask_reg_reg[24] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[24]),\n .Q(mc_app_wdf_mask_reg[24]),\n .R(areset_d1));\n FDRE \\mc_app_wdf_mask_reg_reg[25] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[25]),\n .Q(mc_app_wdf_mask_reg[25]),\n .R(areset_d1));\n FDRE \\mc_app_wdf_mask_reg_reg[26] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[26]),\n .Q(mc_app_wdf_mask_reg[26]),\n .R(areset_d1));\n FDRE \\mc_app_wdf_mask_reg_reg[27] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[27]),\n .Q(mc_app_wdf_mask_reg[27]),\n .R(areset_d1));\n FDRE \\mc_app_wdf_mask_reg_reg[28] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[28]),\n .Q(mc_app_wdf_mask_reg[28]),\n .R(areset_d1));\n FDRE \\mc_app_wdf_mask_reg_reg[29] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[29]),\n .Q(mc_app_wdf_mask_reg[29]),\n .R(areset_d1));\n FDRE \\mc_app_wdf_mask_reg_reg[2] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[2]),\n .Q(mc_app_wdf_mask_reg[2]),\n .R(areset_d1));\n FDRE \\mc_app_wdf_mask_reg_reg[30] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[30]),\n .Q(mc_app_wdf_mask_reg[30]),\n .R(areset_d1));\n FDRE \\mc_app_wdf_mask_reg_reg[31] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[31]),\n .Q(mc_app_wdf_mask_reg[31]),\n .R(areset_d1));\n FDRE \\mc_app_wdf_mask_reg_reg[3] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[3]),\n .Q(mc_app_wdf_mask_reg[3]),\n .R(areset_d1));\n FDRE \\mc_app_wdf_mask_reg_reg[4] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[4]),\n .Q(mc_app_wdf_mask_reg[4]),\n .R(areset_d1));\n FDRE \\mc_app_wdf_mask_reg_reg[5] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[5]),\n .Q(mc_app_wdf_mask_reg[5]),\n .R(areset_d1));\n FDRE \\mc_app_wdf_mask_reg_reg[6] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[6]),\n .Q(mc_app_wdf_mask_reg[6]),\n .R(areset_d1));\n FDRE \\mc_app_wdf_mask_reg_reg[7] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[7]),\n .Q(mc_app_wdf_mask_reg[7]),\n .R(areset_d1));\n FDRE \\mc_app_wdf_mask_reg_reg[8] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[8]),\n .Q(mc_app_wdf_mask_reg[8]),\n .R(areset_d1));\n FDRE \\mc_app_wdf_mask_reg_reg[9] \n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(D[9]),\n .Q(mc_app_wdf_mask_reg[9]),\n .R(areset_d1));\n FDRE mc_app_wdf_wren_reg_reg\n (.C(CLK),\n .CE(app_wdf_rdy),\n .D(\\RD_PRI_REG_STARVE.rnw_i_reg ),\n .Q(mc_app_wdf_wren_reg),\n .R(areset_d1));\n LUT3 #(\n .INIT(8'hB8)) \n valid_i_1\n (.I0(s_axi_wvalid),\n .I1(s_axi_wready),\n .I2(valid),\n .O(wvalid_int));\n FDRE valid_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wvalid_int),\n .Q(valid),\n .R(areset_d1));\n FDRE \\wdf_data_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [0]),\n .Q(wdf_data[0]),\n .R(1'b0));\n FDRE \\wdf_data_reg[100] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [100]),\n .Q(wdf_data[100]),\n .R(1'b0));\n FDRE \\wdf_data_reg[101] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [101]),\n .Q(wdf_data[101]),\n .R(1'b0));\n FDRE \\wdf_data_reg[102] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [102]),\n .Q(wdf_data[102]),\n .R(1'b0));\n FDRE \\wdf_data_reg[103] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [103]),\n .Q(wdf_data[103]),\n .R(1'b0));\n FDRE \\wdf_data_reg[104] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [104]),\n .Q(wdf_data[104]),\n .R(1'b0));\n FDRE \\wdf_data_reg[105] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [105]),\n .Q(wdf_data[105]),\n .R(1'b0));\n FDRE \\wdf_data_reg[106] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [106]),\n .Q(wdf_data[106]),\n .R(1'b0));\n FDRE \\wdf_data_reg[107] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [107]),\n .Q(wdf_data[107]),\n .R(1'b0));\n FDRE \\wdf_data_reg[108] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [108]),\n .Q(wdf_data[108]),\n .R(1'b0));\n FDRE \\wdf_data_reg[109] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [109]),\n .Q(wdf_data[109]),\n .R(1'b0));\n FDRE \\wdf_data_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [10]),\n .Q(wdf_data[10]),\n .R(1'b0));\n FDRE \\wdf_data_reg[110] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [110]),\n .Q(wdf_data[110]),\n .R(1'b0));\n FDRE \\wdf_data_reg[111] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [111]),\n .Q(wdf_data[111]),\n .R(1'b0));\n FDRE \\wdf_data_reg[112] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [112]),\n .Q(wdf_data[112]),\n .R(1'b0));\n FDRE \\wdf_data_reg[113] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [113]),\n .Q(wdf_data[113]),\n .R(1'b0));\n FDRE \\wdf_data_reg[114] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [114]),\n .Q(wdf_data[114]),\n .R(1'b0));\n FDRE \\wdf_data_reg[115] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [115]),\n .Q(wdf_data[115]),\n .R(1'b0));\n FDRE \\wdf_data_reg[116] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [116]),\n .Q(wdf_data[116]),\n .R(1'b0));\n FDRE \\wdf_data_reg[117] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [117]),\n .Q(wdf_data[117]),\n .R(1'b0));\n FDRE \\wdf_data_reg[118] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [118]),\n .Q(wdf_data[118]),\n .R(1'b0));\n FDRE \\wdf_data_reg[119] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [119]),\n .Q(wdf_data[119]),\n .R(1'b0));\n FDRE \\wdf_data_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [11]),\n .Q(wdf_data[11]),\n .R(1'b0));\n FDRE \\wdf_data_reg[120] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [120]),\n .Q(wdf_data[120]),\n .R(1'b0));\n FDRE \\wdf_data_reg[121] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [121]),\n .Q(wdf_data[121]),\n .R(1'b0));\n FDRE \\wdf_data_reg[122] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [122]),\n .Q(wdf_data[122]),\n .R(1'b0));\n FDRE \\wdf_data_reg[123] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [123]),\n .Q(wdf_data[123]),\n .R(1'b0));\n FDRE \\wdf_data_reg[124] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [124]),\n .Q(wdf_data[124]),\n .R(1'b0));\n FDRE \\wdf_data_reg[125] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [125]),\n .Q(wdf_data[125]),\n .R(1'b0));\n FDRE \\wdf_data_reg[126] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [126]),\n .Q(wdf_data[126]),\n .R(1'b0));\n FDRE \\wdf_data_reg[127] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [127]),\n .Q(wdf_data[127]),\n .R(1'b0));\n FDRE \\wdf_data_reg[128] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [128]),\n .Q(wdf_data[128]),\n .R(1'b0));\n FDRE \\wdf_data_reg[129] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [129]),\n .Q(wdf_data[129]),\n .R(1'b0));\n FDRE \\wdf_data_reg[12] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [12]),\n .Q(wdf_data[12]),\n .R(1'b0));\n FDRE \\wdf_data_reg[130] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [130]),\n .Q(wdf_data[130]),\n .R(1'b0));\n FDRE \\wdf_data_reg[131] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [131]),\n .Q(wdf_data[131]),\n .R(1'b0));\n FDRE \\wdf_data_reg[132] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [132]),\n .Q(wdf_data[132]),\n .R(1'b0));\n FDRE \\wdf_data_reg[133] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [133]),\n .Q(wdf_data[133]),\n .R(1'b0));\n FDRE \\wdf_data_reg[134] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [134]),\n .Q(wdf_data[134]),\n .R(1'b0));\n FDRE \\wdf_data_reg[135] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [135]),\n .Q(wdf_data[135]),\n .R(1'b0));\n FDRE \\wdf_data_reg[136] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [136]),\n .Q(wdf_data[136]),\n .R(1'b0));\n FDRE \\wdf_data_reg[137] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [137]),\n .Q(wdf_data[137]),\n .R(1'b0));\n FDRE \\wdf_data_reg[138] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [138]),\n .Q(wdf_data[138]),\n .R(1'b0));\n FDRE \\wdf_data_reg[139] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [139]),\n .Q(wdf_data[139]),\n .R(1'b0));\n FDRE \\wdf_data_reg[13] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [13]),\n .Q(wdf_data[13]),\n .R(1'b0));\n FDRE \\wdf_data_reg[140] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [140]),\n .Q(wdf_data[140]),\n .R(1'b0));\n FDRE \\wdf_data_reg[141] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [141]),\n .Q(wdf_data[141]),\n .R(1'b0));\n FDRE \\wdf_data_reg[142] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [142]),\n .Q(wdf_data[142]),\n .R(1'b0));\n FDRE \\wdf_data_reg[143] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [143]),\n .Q(wdf_data[143]),\n .R(1'b0));\n FDRE \\wdf_data_reg[144] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [144]),\n .Q(wdf_data[144]),\n .R(1'b0));\n FDRE \\wdf_data_reg[145] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [145]),\n .Q(wdf_data[145]),\n .R(1'b0));\n FDRE \\wdf_data_reg[146] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [146]),\n .Q(wdf_data[146]),\n .R(1'b0));\n FDRE \\wdf_data_reg[147] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [147]),\n .Q(wdf_data[147]),\n .R(1'b0));\n FDRE \\wdf_data_reg[148] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [148]),\n .Q(wdf_data[148]),\n .R(1'b0));\n FDRE \\wdf_data_reg[149] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [149]),\n .Q(wdf_data[149]),\n .R(1'b0));\n FDRE \\wdf_data_reg[14] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [14]),\n .Q(wdf_data[14]),\n .R(1'b0));\n FDRE \\wdf_data_reg[150] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [150]),\n .Q(wdf_data[150]),\n .R(1'b0));\n FDRE \\wdf_data_reg[151] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [151]),\n .Q(wdf_data[151]),\n .R(1'b0));\n FDRE \\wdf_data_reg[152] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [152]),\n .Q(wdf_data[152]),\n .R(1'b0));\n FDRE \\wdf_data_reg[153] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [153]),\n .Q(wdf_data[153]),\n .R(1'b0));\n FDRE \\wdf_data_reg[154] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [154]),\n .Q(wdf_data[154]),\n .R(1'b0));\n FDRE \\wdf_data_reg[155] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [155]),\n .Q(wdf_data[155]),\n .R(1'b0));\n FDRE \\wdf_data_reg[156] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [156]),\n .Q(wdf_data[156]),\n .R(1'b0));\n FDRE \\wdf_data_reg[157] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [157]),\n .Q(wdf_data[157]),\n .R(1'b0));\n FDRE \\wdf_data_reg[158] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [158]),\n .Q(wdf_data[158]),\n .R(1'b0));\n FDRE \\wdf_data_reg[159] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [159]),\n .Q(wdf_data[159]),\n .R(1'b0));\n FDRE \\wdf_data_reg[15] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [15]),\n .Q(wdf_data[15]),\n .R(1'b0));\n FDRE \\wdf_data_reg[160] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [160]),\n .Q(wdf_data[160]),\n .R(1'b0));\n FDRE \\wdf_data_reg[161] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [161]),\n .Q(wdf_data[161]),\n .R(1'b0));\n FDRE \\wdf_data_reg[162] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [162]),\n .Q(wdf_data[162]),\n .R(1'b0));\n FDRE \\wdf_data_reg[163] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [163]),\n .Q(wdf_data[163]),\n .R(1'b0));\n FDRE \\wdf_data_reg[164] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [164]),\n .Q(wdf_data[164]),\n .R(1'b0));\n FDRE \\wdf_data_reg[165] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [165]),\n .Q(wdf_data[165]),\n .R(1'b0));\n FDRE \\wdf_data_reg[166] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [166]),\n .Q(wdf_data[166]),\n .R(1'b0));\n FDRE \\wdf_data_reg[167] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [167]),\n .Q(wdf_data[167]),\n .R(1'b0));\n FDRE \\wdf_data_reg[168] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [168]),\n .Q(wdf_data[168]),\n .R(1'b0));\n FDRE \\wdf_data_reg[169] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [169]),\n .Q(wdf_data[169]),\n .R(1'b0));\n FDRE \\wdf_data_reg[16] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [16]),\n .Q(wdf_data[16]),\n .R(1'b0));\n FDRE \\wdf_data_reg[170] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [170]),\n .Q(wdf_data[170]),\n .R(1'b0));\n FDRE \\wdf_data_reg[171] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [171]),\n .Q(wdf_data[171]),\n .R(1'b0));\n FDRE \\wdf_data_reg[172] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [172]),\n .Q(wdf_data[172]),\n .R(1'b0));\n FDRE \\wdf_data_reg[173] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [173]),\n .Q(wdf_data[173]),\n .R(1'b0));\n FDRE \\wdf_data_reg[174] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [174]),\n .Q(wdf_data[174]),\n .R(1'b0));\n FDRE \\wdf_data_reg[175] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [175]),\n .Q(wdf_data[175]),\n .R(1'b0));\n FDRE \\wdf_data_reg[176] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [176]),\n .Q(wdf_data[176]),\n .R(1'b0));\n FDRE \\wdf_data_reg[177] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [177]),\n .Q(wdf_data[177]),\n .R(1'b0));\n FDRE \\wdf_data_reg[178] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [178]),\n .Q(wdf_data[178]),\n .R(1'b0));\n FDRE \\wdf_data_reg[179] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [179]),\n .Q(wdf_data[179]),\n .R(1'b0));\n FDRE \\wdf_data_reg[17] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [17]),\n .Q(wdf_data[17]),\n .R(1'b0));\n FDRE \\wdf_data_reg[180] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [180]),\n .Q(wdf_data[180]),\n .R(1'b0));\n FDRE \\wdf_data_reg[181] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [181]),\n .Q(wdf_data[181]),\n .R(1'b0));\n FDRE \\wdf_data_reg[182] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [182]),\n .Q(wdf_data[182]),\n .R(1'b0));\n FDRE \\wdf_data_reg[183] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [183]),\n .Q(wdf_data[183]),\n .R(1'b0));\n FDRE \\wdf_data_reg[184] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [184]),\n .Q(wdf_data[184]),\n .R(1'b0));\n FDRE \\wdf_data_reg[185] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [185]),\n .Q(wdf_data[185]),\n .R(1'b0));\n FDRE \\wdf_data_reg[186] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [186]),\n .Q(wdf_data[186]),\n .R(1'b0));\n FDRE \\wdf_data_reg[187] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [187]),\n .Q(wdf_data[187]),\n .R(1'b0));\n FDRE \\wdf_data_reg[188] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [188]),\n .Q(wdf_data[188]),\n .R(1'b0));\n FDRE \\wdf_data_reg[189] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [189]),\n .Q(wdf_data[189]),\n .R(1'b0));\n FDRE \\wdf_data_reg[18] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [18]),\n .Q(wdf_data[18]),\n .R(1'b0));\n FDRE \\wdf_data_reg[190] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [190]),\n .Q(wdf_data[190]),\n .R(1'b0));\n FDRE \\wdf_data_reg[191] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [191]),\n .Q(wdf_data[191]),\n .R(1'b0));\n FDRE \\wdf_data_reg[192] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [192]),\n .Q(wdf_data[192]),\n .R(1'b0));\n FDRE \\wdf_data_reg[193] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [193]),\n .Q(wdf_data[193]),\n .R(1'b0));\n FDRE \\wdf_data_reg[194] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [194]),\n .Q(wdf_data[194]),\n .R(1'b0));\n FDRE \\wdf_data_reg[195] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [195]),\n .Q(wdf_data[195]),\n .R(1'b0));\n FDRE \\wdf_data_reg[196] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [196]),\n .Q(wdf_data[196]),\n .R(1'b0));\n FDRE \\wdf_data_reg[197] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [197]),\n .Q(wdf_data[197]),\n .R(1'b0));\n FDRE \\wdf_data_reg[198] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [198]),\n .Q(wdf_data[198]),\n .R(1'b0));\n FDRE \\wdf_data_reg[199] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [199]),\n .Q(wdf_data[199]),\n .R(1'b0));\n FDRE \\wdf_data_reg[19] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [19]),\n .Q(wdf_data[19]),\n .R(1'b0));\n FDRE \\wdf_data_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [1]),\n .Q(wdf_data[1]),\n .R(1'b0));\n FDRE \\wdf_data_reg[200] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [200]),\n .Q(wdf_data[200]),\n .R(1'b0));\n FDRE \\wdf_data_reg[201] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [201]),\n .Q(wdf_data[201]),\n .R(1'b0));\n FDRE \\wdf_data_reg[202] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [202]),\n .Q(wdf_data[202]),\n .R(1'b0));\n FDRE \\wdf_data_reg[203] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [203]),\n .Q(wdf_data[203]),\n .R(1'b0));\n FDRE \\wdf_data_reg[204] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [204]),\n .Q(wdf_data[204]),\n .R(1'b0));\n FDRE \\wdf_data_reg[205] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [205]),\n .Q(wdf_data[205]),\n .R(1'b0));\n FDRE \\wdf_data_reg[206] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [206]),\n .Q(wdf_data[206]),\n .R(1'b0));\n FDRE \\wdf_data_reg[207] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [207]),\n .Q(wdf_data[207]),\n .R(1'b0));\n FDRE \\wdf_data_reg[208] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [208]),\n .Q(wdf_data[208]),\n .R(1'b0));\n FDRE \\wdf_data_reg[209] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [209]),\n .Q(wdf_data[209]),\n .R(1'b0));\n FDRE \\wdf_data_reg[20] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [20]),\n .Q(wdf_data[20]),\n .R(1'b0));\n FDRE \\wdf_data_reg[210] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [210]),\n .Q(wdf_data[210]),\n .R(1'b0));\n FDRE \\wdf_data_reg[211] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [211]),\n .Q(wdf_data[211]),\n .R(1'b0));\n FDRE \\wdf_data_reg[212] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [212]),\n .Q(wdf_data[212]),\n .R(1'b0));\n FDRE \\wdf_data_reg[213] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [213]),\n .Q(wdf_data[213]),\n .R(1'b0));\n FDRE \\wdf_data_reg[214] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [214]),\n .Q(wdf_data[214]),\n .R(1'b0));\n FDRE \\wdf_data_reg[215] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [215]),\n .Q(wdf_data[215]),\n .R(1'b0));\n FDRE \\wdf_data_reg[216] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [216]),\n .Q(wdf_data[216]),\n .R(1'b0));\n FDRE \\wdf_data_reg[217] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [217]),\n .Q(wdf_data[217]),\n .R(1'b0));\n FDRE \\wdf_data_reg[218] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [218]),\n .Q(wdf_data[218]),\n .R(1'b0));\n FDRE \\wdf_data_reg[219] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [219]),\n .Q(wdf_data[219]),\n .R(1'b0));\n FDRE \\wdf_data_reg[21] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [21]),\n .Q(wdf_data[21]),\n .R(1'b0));\n FDRE \\wdf_data_reg[220] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [220]),\n .Q(wdf_data[220]),\n .R(1'b0));\n FDRE \\wdf_data_reg[221] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [221]),\n .Q(wdf_data[221]),\n .R(1'b0));\n FDRE \\wdf_data_reg[222] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [222]),\n .Q(wdf_data[222]),\n .R(1'b0));\n FDRE \\wdf_data_reg[223] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [223]),\n .Q(wdf_data[223]),\n .R(1'b0));\n FDRE \\wdf_data_reg[224] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [224]),\n .Q(wdf_data[224]),\n .R(1'b0));\n FDRE \\wdf_data_reg[225] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [225]),\n .Q(wdf_data[225]),\n .R(1'b0));\n FDRE \\wdf_data_reg[226] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [226]),\n .Q(wdf_data[226]),\n .R(1'b0));\n FDRE \\wdf_data_reg[227] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [227]),\n .Q(wdf_data[227]),\n .R(1'b0));\n FDRE \\wdf_data_reg[228] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [228]),\n .Q(wdf_data[228]),\n .R(1'b0));\n FDRE \\wdf_data_reg[229] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [229]),\n .Q(wdf_data[229]),\n .R(1'b0));\n FDRE \\wdf_data_reg[22] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [22]),\n .Q(wdf_data[22]),\n .R(1'b0));\n FDRE \\wdf_data_reg[230] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [230]),\n .Q(wdf_data[230]),\n .R(1'b0));\n FDRE \\wdf_data_reg[231] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [231]),\n .Q(wdf_data[231]),\n .R(1'b0));\n FDRE \\wdf_data_reg[232] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [232]),\n .Q(wdf_data[232]),\n .R(1'b0));\n FDRE \\wdf_data_reg[233] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [233]),\n .Q(wdf_data[233]),\n .R(1'b0));\n FDRE \\wdf_data_reg[234] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [234]),\n .Q(wdf_data[234]),\n .R(1'b0));\n FDRE \\wdf_data_reg[235] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [235]),\n .Q(wdf_data[235]),\n .R(1'b0));\n FDRE \\wdf_data_reg[236] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [236]),\n .Q(wdf_data[236]),\n .R(1'b0));\n FDRE \\wdf_data_reg[237] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [237]),\n .Q(wdf_data[237]),\n .R(1'b0));\n FDRE \\wdf_data_reg[238] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [238]),\n .Q(wdf_data[238]),\n .R(1'b0));\n FDRE \\wdf_data_reg[239] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [239]),\n .Q(wdf_data[239]),\n .R(1'b0));\n FDRE \\wdf_data_reg[23] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [23]),\n .Q(wdf_data[23]),\n .R(1'b0));\n FDRE \\wdf_data_reg[240] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [240]),\n .Q(wdf_data[240]),\n .R(1'b0));\n FDRE \\wdf_data_reg[241] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [241]),\n .Q(wdf_data[241]),\n .R(1'b0));\n FDRE \\wdf_data_reg[242] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [242]),\n .Q(wdf_data[242]),\n .R(1'b0));\n FDRE \\wdf_data_reg[243] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [243]),\n .Q(wdf_data[243]),\n .R(1'b0));\n FDRE \\wdf_data_reg[244] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [244]),\n .Q(wdf_data[244]),\n .R(1'b0));\n FDRE \\wdf_data_reg[245] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [245]),\n .Q(wdf_data[245]),\n .R(1'b0));\n FDRE \\wdf_data_reg[246] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [246]),\n .Q(wdf_data[246]),\n .R(1'b0));\n FDRE \\wdf_data_reg[247] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [247]),\n .Q(wdf_data[247]),\n .R(1'b0));\n FDRE \\wdf_data_reg[248] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [248]),\n .Q(wdf_data[248]),\n .R(1'b0));\n FDRE \\wdf_data_reg[249] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [249]),\n .Q(wdf_data[249]),\n .R(1'b0));\n FDRE \\wdf_data_reg[24] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [24]),\n .Q(wdf_data[24]),\n .R(1'b0));\n FDRE \\wdf_data_reg[250] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [250]),\n .Q(wdf_data[250]),\n .R(1'b0));\n FDRE \\wdf_data_reg[251] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [251]),\n .Q(wdf_data[251]),\n .R(1'b0));\n FDRE \\wdf_data_reg[252] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [252]),\n .Q(wdf_data[252]),\n .R(1'b0));\n FDRE \\wdf_data_reg[253] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [253]),\n .Q(wdf_data[253]),\n .R(1'b0));\n FDRE \\wdf_data_reg[254] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [254]),\n .Q(wdf_data[254]),\n .R(1'b0));\n FDRE \\wdf_data_reg[255] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [255]),\n .Q(wdf_data[255]),\n .R(1'b0));\n FDRE \\wdf_data_reg[25] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [25]),\n .Q(wdf_data[25]),\n .R(1'b0));\n FDRE \\wdf_data_reg[26] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [26]),\n .Q(wdf_data[26]),\n .R(1'b0));\n FDRE \\wdf_data_reg[27] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [27]),\n .Q(wdf_data[27]),\n .R(1'b0));\n FDRE \\wdf_data_reg[28] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [28]),\n .Q(wdf_data[28]),\n .R(1'b0));\n FDRE \\wdf_data_reg[29] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [29]),\n .Q(wdf_data[29]),\n .R(1'b0));\n FDRE \\wdf_data_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [2]),\n .Q(wdf_data[2]),\n .R(1'b0));\n FDRE \\wdf_data_reg[30] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [30]),\n .Q(wdf_data[30]),\n .R(1'b0));\n FDRE \\wdf_data_reg[31] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [31]),\n .Q(wdf_data[31]),\n .R(1'b0));\n FDRE \\wdf_data_reg[32] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [32]),\n .Q(wdf_data[32]),\n .R(1'b0));\n FDRE \\wdf_data_reg[33] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [33]),\n .Q(wdf_data[33]),\n .R(1'b0));\n FDRE \\wdf_data_reg[34] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [34]),\n .Q(wdf_data[34]),\n .R(1'b0));\n FDRE \\wdf_data_reg[35] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [35]),\n .Q(wdf_data[35]),\n .R(1'b0));\n FDRE \\wdf_data_reg[36] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [36]),\n .Q(wdf_data[36]),\n .R(1'b0));\n FDRE \\wdf_data_reg[37] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [37]),\n .Q(wdf_data[37]),\n .R(1'b0));\n FDRE \\wdf_data_reg[38] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [38]),\n .Q(wdf_data[38]),\n .R(1'b0));\n FDRE \\wdf_data_reg[39] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [39]),\n .Q(wdf_data[39]),\n .R(1'b0));\n FDRE \\wdf_data_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [3]),\n .Q(wdf_data[3]),\n .R(1'b0));\n FDRE \\wdf_data_reg[40] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [40]),\n .Q(wdf_data[40]),\n .R(1'b0));\n FDRE \\wdf_data_reg[41] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [41]),\n .Q(wdf_data[41]),\n .R(1'b0));\n FDRE \\wdf_data_reg[42] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [42]),\n .Q(wdf_data[42]),\n .R(1'b0));\n FDRE \\wdf_data_reg[43] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [43]),\n .Q(wdf_data[43]),\n .R(1'b0));\n FDRE \\wdf_data_reg[44] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [44]),\n .Q(wdf_data[44]),\n .R(1'b0));\n FDRE \\wdf_data_reg[45] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [45]),\n .Q(wdf_data[45]),\n .R(1'b0));\n FDRE \\wdf_data_reg[46] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [46]),\n .Q(wdf_data[46]),\n .R(1'b0));\n FDRE \\wdf_data_reg[47] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [47]),\n .Q(wdf_data[47]),\n .R(1'b0));\n FDRE \\wdf_data_reg[48] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [48]),\n .Q(wdf_data[48]),\n .R(1'b0));\n FDRE \\wdf_data_reg[49] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [49]),\n .Q(wdf_data[49]),\n .R(1'b0));\n FDRE \\wdf_data_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [4]),\n .Q(wdf_data[4]),\n .R(1'b0));\n FDRE \\wdf_data_reg[50] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [50]),\n .Q(wdf_data[50]),\n .R(1'b0));\n FDRE \\wdf_data_reg[51] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [51]),\n .Q(wdf_data[51]),\n .R(1'b0));\n FDRE \\wdf_data_reg[52] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [52]),\n .Q(wdf_data[52]),\n .R(1'b0));\n FDRE \\wdf_data_reg[53] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [53]),\n .Q(wdf_data[53]),\n .R(1'b0));\n FDRE \\wdf_data_reg[54] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [54]),\n .Q(wdf_data[54]),\n .R(1'b0));\n FDRE \\wdf_data_reg[55] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [55]),\n .Q(wdf_data[55]),\n .R(1'b0));\n FDRE \\wdf_data_reg[56] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [56]),\n .Q(wdf_data[56]),\n .R(1'b0));\n FDRE \\wdf_data_reg[57] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [57]),\n .Q(wdf_data[57]),\n .R(1'b0));\n FDRE \\wdf_data_reg[58] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [58]),\n .Q(wdf_data[58]),\n .R(1'b0));\n FDRE \\wdf_data_reg[59] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [59]),\n .Q(wdf_data[59]),\n .R(1'b0));\n FDRE \\wdf_data_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [5]),\n .Q(wdf_data[5]),\n .R(1'b0));\n FDRE \\wdf_data_reg[60] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [60]),\n .Q(wdf_data[60]),\n .R(1'b0));\n FDRE \\wdf_data_reg[61] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [61]),\n .Q(wdf_data[61]),\n .R(1'b0));\n FDRE \\wdf_data_reg[62] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [62]),\n .Q(wdf_data[62]),\n .R(1'b0));\n FDRE \\wdf_data_reg[63] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [63]),\n .Q(wdf_data[63]),\n .R(1'b0));\n FDRE \\wdf_data_reg[64] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [64]),\n .Q(wdf_data[64]),\n .R(1'b0));\n FDRE \\wdf_data_reg[65] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [65]),\n .Q(wdf_data[65]),\n .R(1'b0));\n FDRE \\wdf_data_reg[66] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [66]),\n .Q(wdf_data[66]),\n .R(1'b0));\n FDRE \\wdf_data_reg[67] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [67]),\n .Q(wdf_data[67]),\n .R(1'b0));\n FDRE \\wdf_data_reg[68] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [68]),\n .Q(wdf_data[68]),\n .R(1'b0));\n FDRE \\wdf_data_reg[69] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [69]),\n .Q(wdf_data[69]),\n .R(1'b0));\n FDRE \\wdf_data_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [6]),\n .Q(wdf_data[6]),\n .R(1'b0));\n FDRE \\wdf_data_reg[70] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [70]),\n .Q(wdf_data[70]),\n .R(1'b0));\n FDRE \\wdf_data_reg[71] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [71]),\n .Q(wdf_data[71]),\n .R(1'b0));\n FDRE \\wdf_data_reg[72] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [72]),\n .Q(wdf_data[72]),\n .R(1'b0));\n FDRE \\wdf_data_reg[73] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [73]),\n .Q(wdf_data[73]),\n .R(1'b0));\n FDRE \\wdf_data_reg[74] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [74]),\n .Q(wdf_data[74]),\n .R(1'b0));\n FDRE \\wdf_data_reg[75] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [75]),\n .Q(wdf_data[75]),\n .R(1'b0));\n FDRE \\wdf_data_reg[76] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [76]),\n .Q(wdf_data[76]),\n .R(1'b0));\n FDRE \\wdf_data_reg[77] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [77]),\n .Q(wdf_data[77]),\n .R(1'b0));\n FDRE \\wdf_data_reg[78] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [78]),\n .Q(wdf_data[78]),\n .R(1'b0));\n FDRE \\wdf_data_reg[79] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [79]),\n .Q(wdf_data[79]),\n .R(1'b0));\n FDRE \\wdf_data_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [7]),\n .Q(wdf_data[7]),\n .R(1'b0));\n FDRE \\wdf_data_reg[80] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [80]),\n .Q(wdf_data[80]),\n .R(1'b0));\n FDRE \\wdf_data_reg[81] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [81]),\n .Q(wdf_data[81]),\n .R(1'b0));\n FDRE \\wdf_data_reg[82] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [82]),\n .Q(wdf_data[82]),\n .R(1'b0));\n FDRE \\wdf_data_reg[83] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [83]),\n .Q(wdf_data[83]),\n .R(1'b0));\n FDRE \\wdf_data_reg[84] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [84]),\n .Q(wdf_data[84]),\n .R(1'b0));\n FDRE \\wdf_data_reg[85] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [85]),\n .Q(wdf_data[85]),\n .R(1'b0));\n FDRE \\wdf_data_reg[86] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [86]),\n .Q(wdf_data[86]),\n .R(1'b0));\n FDRE \\wdf_data_reg[87] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [87]),\n .Q(wdf_data[87]),\n .R(1'b0));\n FDRE \\wdf_data_reg[88] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [88]),\n .Q(wdf_data[88]),\n .R(1'b0));\n FDRE \\wdf_data_reg[89] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [89]),\n .Q(wdf_data[89]),\n .R(1'b0));\n FDRE \\wdf_data_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [8]),\n .Q(wdf_data[8]),\n .R(1'b0));\n FDRE \\wdf_data_reg[90] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [90]),\n .Q(wdf_data[90]),\n .R(1'b0));\n FDRE \\wdf_data_reg[91] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [91]),\n .Q(wdf_data[91]),\n .R(1'b0));\n FDRE \\wdf_data_reg[92] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [92]),\n .Q(wdf_data[92]),\n .R(1'b0));\n FDRE \\wdf_data_reg[93] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [93]),\n .Q(wdf_data[93]),\n .R(1'b0));\n FDRE \\wdf_data_reg[94] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [94]),\n .Q(wdf_data[94]),\n .R(1'b0));\n FDRE \\wdf_data_reg[95] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [95]),\n .Q(wdf_data[95]),\n .R(1'b0));\n FDRE \\wdf_data_reg[96] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [96]),\n .Q(wdf_data[96]),\n .R(1'b0));\n FDRE \\wdf_data_reg[97] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [97]),\n .Q(wdf_data[97]),\n .R(1'b0));\n FDRE \\wdf_data_reg[98] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [98]),\n .Q(wdf_data[98]),\n .R(1'b0));\n FDRE \\wdf_data_reg[99] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [99]),\n .Q(wdf_data[99]),\n .R(1'b0));\n FDRE \\wdf_data_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mc_app_wdf_data_reg_reg[255]_0 [9]),\n .Q(wdf_data[9]),\n .R(1'b0));\n FDRE \\wdf_mask_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(D[0]),\n .Q(wdf_mask[0]),\n .R(1'b0));\n FDRE \\wdf_mask_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(D[10]),\n .Q(wdf_mask[10]),\n .R(1'b0));\n FDRE \\wdf_mask_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(D[11]),\n .Q(wdf_mask[11]),\n .R(1'b0));\n FDRE \\wdf_mask_reg[12] \n (.C(CLK),\n .CE(1'b1),\n .D(D[12]),\n .Q(wdf_mask[12]),\n .R(1'b0));\n FDRE \\wdf_mask_reg[13] \n (.C(CLK),\n .CE(1'b1),\n .D(D[13]),\n .Q(wdf_mask[13]),\n .R(1'b0));\n FDRE \\wdf_mask_reg[14] \n (.C(CLK),\n .CE(1'b1),\n .D(D[14]),\n .Q(wdf_mask[14]),\n .R(1'b0));\n FDRE \\wdf_mask_reg[15] \n (.C(CLK),\n .CE(1'b1),\n .D(D[15]),\n .Q(wdf_mask[15]),\n .R(1'b0));\n FDRE \\wdf_mask_reg[16] \n (.C(CLK),\n .CE(1'b1),\n .D(D[16]),\n .Q(wdf_mask[16]),\n .R(1'b0));\n FDRE \\wdf_mask_reg[17] \n (.C(CLK),\n .CE(1'b1),\n .D(D[17]),\n .Q(wdf_mask[17]),\n .R(1'b0));\n FDRE \\wdf_mask_reg[18] \n (.C(CLK),\n .CE(1'b1),\n .D(D[18]),\n .Q(wdf_mask[18]),\n .R(1'b0));\n FDRE \\wdf_mask_reg[19] \n (.C(CLK),\n .CE(1'b1),\n .D(D[19]),\n .Q(wdf_mask[19]),\n .R(1'b0));\n FDRE \\wdf_mask_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(D[1]),\n .Q(wdf_mask[1]),\n .R(1'b0));\n FDRE \\wdf_mask_reg[20] \n (.C(CLK),\n .CE(1'b1),\n .D(D[20]),\n .Q(wdf_mask[20]),\n .R(1'b0));\n FDRE \\wdf_mask_reg[21] \n (.C(CLK),\n .CE(1'b1),\n .D(D[21]),\n .Q(wdf_mask[21]),\n .R(1'b0));\n FDRE \\wdf_mask_reg[22] \n (.C(CLK),\n .CE(1'b1),\n .D(D[22]),\n .Q(wdf_mask[22]),\n .R(1'b0));\n FDRE \\wdf_mask_reg[23] \n (.C(CLK),\n .CE(1'b1),\n .D(D[23]),\n .Q(wdf_mask[23]),\n .R(1'b0));\n FDRE \\wdf_mask_reg[24] \n (.C(CLK),\n .CE(1'b1),\n .D(D[24]),\n .Q(wdf_mask[24]),\n .R(1'b0));\n FDRE \\wdf_mask_reg[25] \n (.C(CLK),\n .CE(1'b1),\n .D(D[25]),\n .Q(wdf_mask[25]),\n .R(1'b0));\n FDRE \\wdf_mask_reg[26] \n (.C(CLK),\n .CE(1'b1),\n .D(D[26]),\n .Q(wdf_mask[26]),\n .R(1'b0));\n FDRE \\wdf_mask_reg[27] \n (.C(CLK),\n .CE(1'b1),\n .D(D[27]),\n .Q(wdf_mask[27]),\n .R(1'b0));\n FDRE \\wdf_mask_reg[28] \n (.C(CLK),\n .CE(1'b1),\n .D(D[28]),\n .Q(wdf_mask[28]),\n .R(1'b0));\n FDRE \\wdf_mask_reg[29] \n (.C(CLK),\n .CE(1'b1),\n .D(D[29]),\n .Q(wdf_mask[29]),\n .R(1'b0));\n FDRE \\wdf_mask_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(D[2]),\n .Q(wdf_mask[2]),\n .R(1'b0));\n FDRE \\wdf_mask_reg[30] \n (.C(CLK),\n .CE(1'b1),\n .D(D[30]),\n .Q(wdf_mask[30]),\n .R(1'b0));\n FDRE \\wdf_mask_reg[31] \n (.C(CLK),\n .CE(1'b1),\n .D(D[31]),\n .Q(wdf_mask[31]),\n .R(1'b0));\n FDRE \\wdf_mask_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(D[3]),\n .Q(wdf_mask[3]),\n .R(1'b0));\n FDRE \\wdf_mask_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(D[4]),\n .Q(wdf_mask[4]),\n .R(1'b0));\n FDRE \\wdf_mask_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(D[5]),\n .Q(wdf_mask[5]),\n .R(1'b0));\n FDRE \\wdf_mask_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(D[6]),\n .Q(wdf_mask[6]),\n .R(1'b0));\n FDRE \\wdf_mask_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(D[7]),\n .Q(wdf_mask[7]),\n .R(1'b0));\n FDRE \\wdf_mask_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(D[8]),\n .Q(wdf_mask[8]),\n .R(1'b0));\n FDRE \\wdf_mask_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(D[9]),\n .Q(wdf_mask[9]),\n .R(1'b0));\n LUT4 #(\n .INIT(16'hABFB)) \n wready_i_1\n (.I0(\\RD_PRI_REG_STARVE.rnw_i_reg ),\n .I1(valid),\n .I2(s_axi_wready),\n .I3(s_axi_wvalid),\n .O(wready_i_1_n_0));\n (* ORIG_CELL_NAME = \"wready_reg\" *) \n FDRE wready_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wready_i_1_n_0),\n .Q(s_axi_wready),\n .R(areset_d1));\n (* ORIG_CELL_NAME = \"wready_reg\" *) \n FDRE wready_reg_rep\n (.C(CLK),\n .CE(1'b1),\n .D(wready_rep_i_1_n_0),\n .Q(wready_reg_rep_n_0),\n .R(areset_d1));\n (* ORIG_CELL_NAME = \"wready_reg\" *) \n FDRE wready_reg_rep__0\n (.C(CLK),\n .CE(1'b1),\n .D(wready_rep__0_i_1_n_0),\n .Q(wready_reg_rep__0_n_0),\n .R(areset_d1));\n (* ORIG_CELL_NAME = \"wready_reg\" *) \n FDRE wready_reg_rep__1\n (.C(CLK),\n .CE(1'b1),\n .D(wready_rep__1_i_1_n_0),\n .Q(wready_reg_rep__1_n_0),\n .R(areset_d1));\n (* ORIG_CELL_NAME = \"wready_reg\" *) \n FDRE wready_reg_rep__2\n (.C(CLK),\n .CE(1'b1),\n .D(wready_rep__2_i_1_n_0),\n .Q(wready_reg_rep__2_n_0),\n .R(areset_d1));\n LUT4 #(\n .INIT(16'hABFB)) \n wready_rep__0_i_1\n (.I0(\\RD_PRI_REG_STARVE.rnw_i_reg ),\n .I1(valid),\n .I2(s_axi_wready),\n .I3(s_axi_wvalid),\n .O(wready_rep__0_i_1_n_0));\n LUT4 #(\n .INIT(16'hABFB)) \n wready_rep__1_i_1\n (.I0(\\RD_PRI_REG_STARVE.rnw_i_reg ),\n .I1(valid),\n .I2(s_axi_wready),\n .I3(s_axi_wvalid),\n .O(wready_rep__1_i_1_n_0));\n LUT4 #(\n .INIT(16'hABFB)) \n wready_rep__2_i_1\n (.I0(\\RD_PRI_REG_STARVE.rnw_i_reg ),\n .I1(valid),\n .I2(s_axi_wready),\n .I3(s_axi_wvalid),\n .O(wready_rep__2_i_1_n_0));\n LUT4 #(\n .INIT(16'hABFB)) \n wready_rep_i_1\n (.I0(\\RD_PRI_REG_STARVE.rnw_i_reg ),\n .I1(valid),\n .I2(s_axi_wready),\n .I3(s_axi_wvalid),\n .O(wready_rep_i_1_n_0));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_axi_mc_wr_cmd_fsm\n (s_axi_awready,\n axlen_int,\n D,\n b_push,\n \\axburst_reg[1] ,\n \\axlen_reg[7] ,\n in0,\n \\axaddr_incr_reg[29] ,\n \\app_addr_r1_reg[4] ,\n \\axaddr_reg[29] ,\n \\app_addr_r1_reg[5] ,\n \\app_addr_r1_reg[6] ,\n \\app_addr_r1_reg[7] ,\n \\app_addr_r1_reg[8] ,\n \\app_addr_r1_reg[9] ,\n \\app_addr_r1_reg[10] ,\n \\app_addr_r1_reg[11] ,\n \\app_addr_r1_reg[12] ,\n \\app_addr_r1_reg[13] ,\n \\app_addr_r1_reg[14] ,\n \\app_addr_r1_reg[15] ,\n \\app_addr_r1_reg[16] ,\n \\app_addr_r1_reg[17] ,\n \\app_addr_r1_reg[18] ,\n \\app_addr_r1_reg[19] ,\n \\app_addr_r1_reg[20] ,\n \\app_addr_r1_reg[21] ,\n \\app_addr_r1_reg[22] ,\n \\app_addr_r1_reg[23] ,\n \\app_addr_r1_reg[24] ,\n \\app_addr_r1_reg[25] ,\n \\app_addr_r1_reg[26] ,\n \\app_addr_r1_reg[27] ,\n S,\n \\app_addr_r1_reg[3] ,\n \\axaddr_incr_reg[29]_0 ,\n \\int_addr_reg[3] ,\n \\axlen_cnt_reg[3] ,\n awvalid_int,\n b_awid,\n E,\n \\axlen_cnt_reg[0] ,\n \\axaddr_incr_reg[11] ,\n areset_d1,\n CLK,\n Q,\n axready_reg_0,\n \\axlen_reg[7]_0 ,\n s_axi_awlen,\n axvalid,\n s_axi_awvalid,\n \\RD_PRI_REG_STARVE.rnw_i_reg ,\n s_axi_awaddr,\n \\axaddr_reg[29]_0 ,\n \\axaddr_incr_reg[29]_1 ,\n \\int_addr_reg[3]_0 ,\n out,\n axready_reg_1,\n \\int_addr_reg[3]_1 ,\n \\axlen_cnt_reg[3]_0 ,\n axburst,\n s_axi_awburst,\n \\RD_PRI_REG_STARVE.rnw_i_reg_0 ,\n s_axi_awid,\n axid);\n output s_axi_awready;\n output [3:0]axlen_int;\n output [7:0]D;\n output b_push;\n output \\axburst_reg[1] ;\n output [3:0]\\axlen_reg[7] ;\n output [3:0]in0;\n output [24:0]\\axaddr_incr_reg[29] ;\n output \\app_addr_r1_reg[4] ;\n output [29:0]\\axaddr_reg[29] ;\n output \\app_addr_r1_reg[5] ;\n output [0:0]\\app_addr_r1_reg[6] ;\n output \\app_addr_r1_reg[7] ;\n output \\app_addr_r1_reg[8] ;\n output \\app_addr_r1_reg[9] ;\n output \\app_addr_r1_reg[10] ;\n output \\app_addr_r1_reg[11] ;\n output \\app_addr_r1_reg[12] ;\n output \\app_addr_r1_reg[13] ;\n output \\app_addr_r1_reg[14] ;\n output \\app_addr_r1_reg[15] ;\n output \\app_addr_r1_reg[16] ;\n output \\app_addr_r1_reg[17] ;\n output \\app_addr_r1_reg[18] ;\n output \\app_addr_r1_reg[19] ;\n output \\app_addr_r1_reg[20] ;\n output \\app_addr_r1_reg[21] ;\n output \\app_addr_r1_reg[22] ;\n output \\app_addr_r1_reg[23] ;\n output \\app_addr_r1_reg[24] ;\n output \\app_addr_r1_reg[25] ;\n output \\app_addr_r1_reg[26] ;\n output \\app_addr_r1_reg[27] ;\n output [0:0]S;\n output \\app_addr_r1_reg[3] ;\n output [29:0]\\axaddr_incr_reg[29]_0 ;\n output [3:0]\\int_addr_reg[3] ;\n output [3:0]\\axlen_cnt_reg[3] ;\n output awvalid_int;\n output b_awid;\n output [0:0]E;\n output [0:0]\\axlen_cnt_reg[0] ;\n output [0:0]\\axaddr_incr_reg[11] ;\n input areset_d1;\n input CLK;\n input [7:0]Q;\n input axready_reg_0;\n input [7:0]\\axlen_reg[7]_0 ;\n input [7:0]s_axi_awlen;\n input axvalid;\n input s_axi_awvalid;\n input \\RD_PRI_REG_STARVE.rnw_i_reg ;\n input [29:0]s_axi_awaddr;\n input [29:0]\\axaddr_reg[29]_0 ;\n input [29:0]\\axaddr_incr_reg[29]_1 ;\n input \\int_addr_reg[3]_0 ;\n input [29:0]out;\n input axready_reg_1;\n input [3:0]\\int_addr_reg[3]_1 ;\n input [3:0]\\axlen_cnt_reg[3]_0 ;\n input [0:0]axburst;\n input [0:0]s_axi_awburst;\n input \\RD_PRI_REG_STARVE.rnw_i_reg_0 ;\n input [0:0]s_axi_awid;\n input axid;\n\n wire CLK;\n wire [7:0]D;\n wire [0:0]E;\n wire [7:0]Q;\n wire \\RD_PRI_REG_STARVE.rnw_i_reg ;\n wire \\RD_PRI_REG_STARVE.rnw_i_reg_0 ;\n wire [0:0]S;\n wire \\app_addr_r1[6]_i_3_n_0 ;\n wire \\app_addr_r1[6]_i_5_n_0 ;\n wire \\app_addr_r1_reg[10] ;\n wire \\app_addr_r1_reg[11] ;\n wire \\app_addr_r1_reg[12] ;\n wire \\app_addr_r1_reg[13] ;\n wire \\app_addr_r1_reg[14] ;\n wire \\app_addr_r1_reg[15] ;\n wire \\app_addr_r1_reg[16] ;\n wire \\app_addr_r1_reg[17] ;\n wire \\app_addr_r1_reg[18] ;\n wire \\app_addr_r1_reg[19] ;\n wire \\app_addr_r1_reg[20] ;\n wire \\app_addr_r1_reg[21] ;\n wire \\app_addr_r1_reg[22] ;\n wire \\app_addr_r1_reg[23] ;\n wire \\app_addr_r1_reg[24] ;\n wire \\app_addr_r1_reg[25] ;\n wire \\app_addr_r1_reg[26] ;\n wire \\app_addr_r1_reg[27] ;\n wire \\app_addr_r1_reg[3] ;\n wire \\app_addr_r1_reg[4] ;\n wire \\app_addr_r1_reg[5] ;\n wire [0:0]\\app_addr_r1_reg[6] ;\n wire \\app_addr_r1_reg[7] ;\n wire \\app_addr_r1_reg[8] ;\n wire \\app_addr_r1_reg[9] ;\n wire areset_d1;\n wire awvalid_int;\n wire [0:0]\\axaddr_incr_reg[11] ;\n wire [24:0]\\axaddr_incr_reg[29] ;\n wire [29:0]\\axaddr_incr_reg[29]_0 ;\n wire [29:0]\\axaddr_incr_reg[29]_1 ;\n wire [29:0]\\axaddr_reg[29] ;\n wire [29:0]\\axaddr_reg[29]_0 ;\n wire [0:0]axburst;\n wire \\axburst_reg[1] ;\n wire [8:5]\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr ;\n wire \\axi_mc_cmd_translator_0/incr_axhandshake ;\n wire \\axi_mc_cmd_translator_0/wrap_axhandshake ;\n wire [8:8]axi_mc_incr_cmd_byte_addr__0;\n wire axid;\n wire \\axlen_cnt[2]_i_2__0_n_0 ;\n wire \\axlen_cnt[2]_i_2_n_0 ;\n wire \\axlen_cnt[3]_i_2__0_n_0 ;\n wire \\axlen_cnt[3]_i_2_n_0 ;\n wire \\axlen_cnt[4]_i_2_n_0 ;\n wire \\axlen_cnt[4]_i_3_n_0 ;\n wire \\axlen_cnt[5]_i_2_n_0 ;\n wire \\axlen_cnt[5]_i_3_n_0 ;\n wire \\axlen_cnt[7]_i_3_n_0 ;\n wire \\axlen_cnt[7]_i_4_n_0 ;\n wire [0:0]\\axlen_cnt_reg[0] ;\n wire [3:0]\\axlen_cnt_reg[3] ;\n wire [3:0]\\axlen_cnt_reg[3]_0 ;\n wire [3:0]axlen_int;\n wire [3:0]\\axlen_reg[7] ;\n wire [7:0]\\axlen_reg[7]_0 ;\n wire axready_i_1_n_0;\n wire axready_reg_0;\n wire axready_reg_1;\n wire axvalid;\n wire b_awid;\n wire b_push;\n wire [3:0]in0;\n wire \\int_addr[3]_i_5_n_0 ;\n wire [3:0]\\int_addr_reg[3] ;\n wire \\int_addr_reg[3]_0 ;\n wire [3:0]\\int_addr_reg[3]_1 ;\n wire \\memory_reg[7][0]_srl8_i_2_n_0 ;\n wire \\memory_reg[7][0]_srl8_i_3_n_0 ;\n wire \\memory_reg[7][0]_srl8_i_4_n_0 ;\n wire \\memory_reg[7][0]_srl8_i_5_n_0 ;\n wire [29:0]out;\n wire [29:0]s_axi_awaddr;\n wire [0:0]s_axi_awburst;\n wire [0:0]s_axi_awid;\n wire [7:0]s_axi_awlen;\n wire s_axi_awready;\n wire s_axi_awvalid;\n\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[10]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [12]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [12]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[10] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[11]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [13]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [13]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[11] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[12]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [14]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [14]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[12] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[13]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [15]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [15]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[13] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[14]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [16]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [16]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[14] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[15]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [17]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [17]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[15] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[16]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [18]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [18]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[16] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[17]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [19]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [19]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[17] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[18]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [20]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [20]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[18] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[19]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [21]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [21]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[19] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[20]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [22]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [22]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[20] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[21]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [23]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [23]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[21] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[22]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [24]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [24]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[22] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[23]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [25]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [25]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[23] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[24]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [26]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [26]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[24] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[25]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [27]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [27]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[25] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[26]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [28]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [28]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[26] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[27]_i_5 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [29]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [29]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[27] ));\n LUT6 #(\n .INIT(64'hF8FFF88888888888)) \n \\app_addr_r1[3]_i_3 \n (.I0(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]),\n .I1(\\app_addr_r1[6]_i_5_n_0 ),\n .I2(\\axaddr_reg[29] [5]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [5]),\n .I5(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[3] ));\n LUT6 #(\n .INIT(64'hF8FFF88888888888)) \n \\app_addr_r1[4]_i_4 \n (.I0(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [6]),\n .I1(\\app_addr_r1[6]_i_5_n_0 ),\n .I2(\\axaddr_reg[29] [6]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [6]),\n .I5(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[4] ));\n (* SOFT_HLUTNM = \"soft_lutpair1163\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_addr_r1[4]_i_5 \n (.I0(s_axi_awaddr[6]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [6]),\n .I3(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I4(\\int_addr_reg[3]_1 [1]),\n .O(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [6]));\n LUT6 #(\n .INIT(64'hF8FFF88888888888)) \n \\app_addr_r1[5]_i_3 \n (.I0(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [7]),\n .I1(\\app_addr_r1[6]_i_5_n_0 ),\n .I2(\\axaddr_reg[29] [7]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [7]),\n .I5(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[5] ));\n LUT5 #(\n .INIT(32'hFFEAEAEA)) \n \\app_addr_r1[6]_i_1 \n (.I0(\\int_addr_reg[3]_0 ),\n .I1(\\app_addr_r1[6]_i_3_n_0 ),\n .I2(axi_mc_incr_cmd_byte_addr__0),\n .I3(\\app_addr_r1[6]_i_5_n_0 ),\n .I4(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [8]),\n .O(\\app_addr_r1_reg[6] ));\n (* SOFT_HLUTNM = \"soft_lutpair1169\" *) \n LUT4 #(\n .INIT(16'h001D)) \n \\app_addr_r1[6]_i_3 \n (.I0(axburst),\n .I1(s_axi_awready),\n .I2(s_axi_awburst),\n .I3(\\RD_PRI_REG_STARVE.rnw_i_reg_0 ),\n .O(\\app_addr_r1[6]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\app_addr_r1[6]_i_4 \n (.I0(s_axi_awaddr[8]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [8]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [8]),\n .O(axi_mc_incr_cmd_byte_addr__0));\n (* SOFT_HLUTNM = \"soft_lutpair1169\" *) \n LUT4 #(\n .INIT(16'h00E2)) \n \\app_addr_r1[6]_i_5 \n (.I0(axburst),\n .I1(s_axi_awready),\n .I2(s_axi_awburst),\n .I3(\\RD_PRI_REG_STARVE.rnw_i_reg_0 ),\n .O(\\app_addr_r1[6]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[7]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [9]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [9]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[7] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[8]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [10]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [10]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[8] ));\n LUT5 #(\n .INIT(32'hCFC88888)) \n \\app_addr_r1[9]_i_2 \n (.I0(\\app_addr_r1[6]_i_5_n_0 ),\n .I1(\\axaddr_reg[29] [11]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axaddr_incr_reg[29]_1 [11]),\n .I4(\\app_addr_r1[6]_i_3_n_0 ),\n .O(\\app_addr_r1_reg[9] ));\n (* SOFT_HLUTNM = \"soft_lutpair1165\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[0]_i_1 \n (.I0(s_axi_awaddr[0]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [0]),\n .O(\\axaddr_reg[29] [0]));\n (* SOFT_HLUTNM = \"soft_lutpair1180\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[10]_i_1 \n (.I0(s_axi_awaddr[10]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [10]),\n .O(\\axaddr_reg[29] [10]));\n (* SOFT_HLUTNM = \"soft_lutpair1180\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[11]_i_1 \n (.I0(s_axi_awaddr[11]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [11]),\n .O(\\axaddr_reg[29] [11]));\n (* SOFT_HLUTNM = \"soft_lutpair1179\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[12]_i_1 \n (.I0(s_axi_awaddr[12]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [12]),\n .O(\\axaddr_reg[29] [12]));\n (* SOFT_HLUTNM = \"soft_lutpair1179\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[13]_i_1 \n (.I0(s_axi_awaddr[13]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [13]),\n .O(\\axaddr_reg[29] [13]));\n (* SOFT_HLUTNM = \"soft_lutpair1178\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[14]_i_1 \n (.I0(s_axi_awaddr[14]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [14]),\n .O(\\axaddr_reg[29] [14]));\n (* SOFT_HLUTNM = \"soft_lutpair1178\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[15]_i_1 \n (.I0(s_axi_awaddr[15]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [15]),\n .O(\\axaddr_reg[29] [15]));\n (* SOFT_HLUTNM = \"soft_lutpair1177\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[16]_i_1 \n (.I0(s_axi_awaddr[16]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [16]),\n .O(\\axaddr_reg[29] [16]));\n (* SOFT_HLUTNM = \"soft_lutpair1177\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[17]_i_1 \n (.I0(s_axi_awaddr[17]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [17]),\n .O(\\axaddr_reg[29] [17]));\n (* SOFT_HLUTNM = \"soft_lutpair1176\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[18]_i_1 \n (.I0(s_axi_awaddr[18]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [18]),\n .O(\\axaddr_reg[29] [18]));\n (* SOFT_HLUTNM = \"soft_lutpair1176\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[19]_i_1 \n (.I0(s_axi_awaddr[19]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [19]),\n .O(\\axaddr_reg[29] [19]));\n (* SOFT_HLUTNM = \"soft_lutpair1166\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[1]_i_1 \n (.I0(s_axi_awaddr[1]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [1]),\n .O(\\axaddr_reg[29] [1]));\n (* SOFT_HLUTNM = \"soft_lutpair1175\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[20]_i_1 \n (.I0(s_axi_awaddr[20]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [20]),\n .O(\\axaddr_reg[29] [20]));\n (* SOFT_HLUTNM = \"soft_lutpair1175\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[21]_i_1 \n (.I0(s_axi_awaddr[21]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [21]),\n .O(\\axaddr_reg[29] [21]));\n (* SOFT_HLUTNM = \"soft_lutpair1174\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[22]_i_1 \n (.I0(s_axi_awaddr[22]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [22]),\n .O(\\axaddr_reg[29] [22]));\n (* SOFT_HLUTNM = \"soft_lutpair1174\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[23]_i_1 \n (.I0(s_axi_awaddr[23]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [23]),\n .O(\\axaddr_reg[29] [23]));\n (* SOFT_HLUTNM = \"soft_lutpair1173\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[24]_i_1 \n (.I0(s_axi_awaddr[24]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [24]),\n .O(\\axaddr_reg[29] [24]));\n (* SOFT_HLUTNM = \"soft_lutpair1173\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[25]_i_1 \n (.I0(s_axi_awaddr[25]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [25]),\n .O(\\axaddr_reg[29] [25]));\n (* SOFT_HLUTNM = \"soft_lutpair1172\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[26]_i_1 \n (.I0(s_axi_awaddr[26]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [26]),\n .O(\\axaddr_reg[29] [26]));\n (* SOFT_HLUTNM = \"soft_lutpair1172\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[27]_i_1 \n (.I0(s_axi_awaddr[27]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [27]),\n .O(\\axaddr_reg[29] [27]));\n (* SOFT_HLUTNM = \"soft_lutpair1171\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[28]_i_1 \n (.I0(s_axi_awaddr[28]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [28]),\n .O(\\axaddr_reg[29] [28]));\n (* SOFT_HLUTNM = \"soft_lutpair1171\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[29]_i_1 \n (.I0(s_axi_awaddr[29]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [29]),\n .O(\\axaddr_reg[29] [29]));\n (* SOFT_HLUTNM = \"soft_lutpair1167\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[2]_i_1 \n (.I0(s_axi_awaddr[2]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [2]),\n .O(\\axaddr_reg[29] [2]));\n (* SOFT_HLUTNM = \"soft_lutpair1168\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[3]_i_1 \n (.I0(s_axi_awaddr[3]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [3]),\n .O(\\axaddr_reg[29] [3]));\n (* SOFT_HLUTNM = \"soft_lutpair1182\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[4]_i_1 \n (.I0(s_axi_awaddr[4]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [4]),\n .O(\\axaddr_reg[29] [4]));\n (* SOFT_HLUTNM = \"soft_lutpair1164\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[5]_i_1 \n (.I0(s_axi_awaddr[5]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [5]),\n .O(\\axaddr_reg[29] [5]));\n (* SOFT_HLUTNM = \"soft_lutpair1163\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[6]_i_1 \n (.I0(s_axi_awaddr[6]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [6]),\n .O(\\axaddr_reg[29] [6]));\n (* SOFT_HLUTNM = \"soft_lutpair1162\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[7]_i_1 \n (.I0(s_axi_awaddr[7]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [7]),\n .O(\\axaddr_reg[29] [7]));\n (* SOFT_HLUTNM = \"soft_lutpair1161\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[8]_i_1 \n (.I0(s_axi_awaddr[8]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [8]),\n .O(\\axaddr_reg[29] [8]));\n (* SOFT_HLUTNM = \"soft_lutpair1181\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axaddr[9]_i_1 \n (.I0(s_axi_awaddr[9]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [9]),\n .O(\\axaddr_reg[29] [9]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[0]_i_1 \n (.I0(s_axi_awaddr[0]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [0]),\n .I3(axready_reg_0),\n .I4(out[0]),\n .O(\\axaddr_incr_reg[29]_0 [0]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[10]_i_1 \n (.I0(s_axi_awaddr[10]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [10]),\n .I3(axready_reg_0),\n .I4(out[10]),\n .O(\\axaddr_incr_reg[29]_0 [10]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[11]_i_1 \n (.I0(s_axi_awaddr[11]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [11]),\n .I3(axready_reg_0),\n .I4(out[11]),\n .O(\\axaddr_incr_reg[29]_0 [11]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[12]_i_1 \n (.I0(s_axi_awaddr[12]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [12]),\n .I3(axready_reg_0),\n .I4(out[12]),\n .O(\\axaddr_incr_reg[29]_0 [12]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[13]_i_1 \n (.I0(s_axi_awaddr[13]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [13]),\n .I3(axready_reg_0),\n .I4(out[13]),\n .O(\\axaddr_incr_reg[29]_0 [13]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[14]_i_1 \n (.I0(s_axi_awaddr[14]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [14]),\n .I3(axready_reg_0),\n .I4(out[14]),\n .O(\\axaddr_incr_reg[29]_0 [14]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[15]_i_1 \n (.I0(s_axi_awaddr[15]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [15]),\n .I3(axready_reg_0),\n .I4(out[15]),\n .O(\\axaddr_incr_reg[29]_0 [15]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[16]_i_1 \n (.I0(s_axi_awaddr[16]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [16]),\n .I3(axready_reg_0),\n .I4(out[16]),\n .O(\\axaddr_incr_reg[29]_0 [16]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[17]_i_1 \n (.I0(s_axi_awaddr[17]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [17]),\n .I3(axready_reg_0),\n .I4(out[17]),\n .O(\\axaddr_incr_reg[29]_0 [17]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[18]_i_1 \n (.I0(s_axi_awaddr[18]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [18]),\n .I3(axready_reg_0),\n .I4(out[18]),\n .O(\\axaddr_incr_reg[29]_0 [18]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[19]_i_1 \n (.I0(s_axi_awaddr[19]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [19]),\n .I3(axready_reg_0),\n .I4(out[19]),\n .O(\\axaddr_incr_reg[29]_0 [19]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[1]_i_1 \n (.I0(s_axi_awaddr[1]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [1]),\n .I3(axready_reg_0),\n .I4(out[1]),\n .O(\\axaddr_incr_reg[29]_0 [1]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[20]_i_1 \n (.I0(s_axi_awaddr[20]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [20]),\n .I3(axready_reg_0),\n .I4(out[20]),\n .O(\\axaddr_incr_reg[29]_0 [20]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[21]_i_1 \n (.I0(s_axi_awaddr[21]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [21]),\n .I3(axready_reg_0),\n .I4(out[21]),\n .O(\\axaddr_incr_reg[29]_0 [21]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[22]_i_1 \n (.I0(s_axi_awaddr[22]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [22]),\n .I3(axready_reg_0),\n .I4(out[22]),\n .O(\\axaddr_incr_reg[29]_0 [22]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[23]_i_1 \n (.I0(s_axi_awaddr[23]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [23]),\n .I3(axready_reg_0),\n .I4(out[23]),\n .O(\\axaddr_incr_reg[29]_0 [23]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[24]_i_1 \n (.I0(s_axi_awaddr[24]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [24]),\n .I3(axready_reg_0),\n .I4(out[24]),\n .O(\\axaddr_incr_reg[29]_0 [24]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[25]_i_1 \n (.I0(s_axi_awaddr[25]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [25]),\n .I3(axready_reg_0),\n .I4(out[25]),\n .O(\\axaddr_incr_reg[29]_0 [25]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[26]_i_1 \n (.I0(s_axi_awaddr[26]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [26]),\n .I3(axready_reg_0),\n .I4(out[26]),\n .O(\\axaddr_incr_reg[29]_0 [26]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[27]_i_1 \n (.I0(s_axi_awaddr[27]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [27]),\n .I3(axready_reg_0),\n .I4(out[27]),\n .O(\\axaddr_incr_reg[29]_0 [27]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[28]_i_1 \n (.I0(s_axi_awaddr[28]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [28]),\n .I3(axready_reg_0),\n .I4(out[28]),\n .O(\\axaddr_incr_reg[29]_0 [28]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[29]_i_1 \n (.I0(s_axi_awaddr[29]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [29]),\n .I3(axready_reg_0),\n .I4(out[29]),\n .O(\\axaddr_incr_reg[29]_0 [29]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[2]_i_1 \n (.I0(s_axi_awaddr[2]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [2]),\n .I3(axready_reg_0),\n .I4(out[2]),\n .O(\\axaddr_incr_reg[29]_0 [2]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[3]_i_1 \n (.I0(s_axi_awaddr[3]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [3]),\n .I3(axready_reg_0),\n .I4(out[3]),\n .O(\\axaddr_incr_reg[29]_0 [3]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[4]_i_1 \n (.I0(s_axi_awaddr[4]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [4]),\n .I3(axready_reg_0),\n .I4(out[4]),\n .O(\\axaddr_incr_reg[29]_0 [4]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[5]_i_1 \n (.I0(s_axi_awaddr[5]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [5]),\n .I3(axready_reg_0),\n .I4(out[5]),\n .O(\\axaddr_incr_reg[29]_0 [5]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[6]_i_1 \n (.I0(s_axi_awaddr[6]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [6]),\n .I3(axready_reg_0),\n .I4(out[6]),\n .O(\\axaddr_incr_reg[29]_0 [6]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[7]_i_1 \n (.I0(s_axi_awaddr[7]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [7]),\n .I3(axready_reg_0),\n .I4(out[7]),\n .O(\\axaddr_incr_reg[29]_0 [7]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[8]_i_1 \n (.I0(s_axi_awaddr[8]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [8]),\n .I3(axready_reg_0),\n .I4(out[8]),\n .O(\\axaddr_incr_reg[29]_0 [8]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axaddr_incr[9]_i_1 \n (.I0(s_axi_awaddr[9]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [9]),\n .I3(axready_reg_0),\n .I4(out[9]),\n .O(\\axaddr_incr_reg[29]_0 [9]));\n (* SOFT_HLUTNM = \"soft_lutpair1168\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_inferred_i_1\n (.I0(s_axi_awaddr[3]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [3]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [3]),\n .O(in0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1167\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_inferred_i_2\n (.I0(s_axi_awaddr[2]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [2]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [2]),\n .O(in0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1166\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_inferred_i_3\n (.I0(s_axi_awaddr[1]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [1]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [1]),\n .O(in0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1165\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_inferred_i_4\n (.I0(s_axi_awaddr[0]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [0]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [0]),\n .O(in0[0]));\n LUT3 #(\n .INIT(8'h08)) \n axaddr_incr_p_inferred_i_5\n (.I0(s_axi_awvalid),\n .I1(s_axi_awready),\n .I2(s_axi_awburst),\n .O(\\axi_mc_cmd_translator_0/incr_axhandshake ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__0_i_1\n (.I0(s_axi_awaddr[11]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [11]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [11]),\n .O(\\axaddr_incr_reg[29] [6]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__0_i_2\n (.I0(s_axi_awaddr[10]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [10]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [10]),\n .O(\\axaddr_incr_reg[29] [5]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__0_i_3\n (.I0(s_axi_awaddr[9]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [9]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [9]),\n .O(\\axaddr_incr_reg[29] [4]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__0_i_4__0\n (.I0(s_axi_awaddr[8]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [8]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [8]),\n .O(\\axaddr_incr_reg[11] ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__1_i_1\n (.I0(s_axi_awaddr[15]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [15]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [15]),\n .O(\\axaddr_incr_reg[29] [10]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__1_i_2\n (.I0(s_axi_awaddr[14]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [14]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [14]),\n .O(\\axaddr_incr_reg[29] [9]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__1_i_3\n (.I0(s_axi_awaddr[13]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [13]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [13]),\n .O(\\axaddr_incr_reg[29] [8]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__1_i_4\n (.I0(s_axi_awaddr[12]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [12]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [12]),\n .O(\\axaddr_incr_reg[29] [7]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__2_i_1\n (.I0(s_axi_awaddr[19]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [19]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [19]),\n .O(\\axaddr_incr_reg[29] [14]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__2_i_2\n (.I0(s_axi_awaddr[18]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [18]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [18]),\n .O(\\axaddr_incr_reg[29] [13]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__2_i_3\n (.I0(s_axi_awaddr[17]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [17]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [17]),\n .O(\\axaddr_incr_reg[29] [12]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__2_i_4\n (.I0(s_axi_awaddr[16]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [16]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [16]),\n .O(\\axaddr_incr_reg[29] [11]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__3_i_1\n (.I0(s_axi_awaddr[23]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [23]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [23]),\n .O(\\axaddr_incr_reg[29] [18]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__3_i_2\n (.I0(s_axi_awaddr[22]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [22]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [22]),\n .O(\\axaddr_incr_reg[29] [17]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__3_i_3\n (.I0(s_axi_awaddr[21]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [21]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [21]),\n .O(\\axaddr_incr_reg[29] [16]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__3_i_4\n (.I0(s_axi_awaddr[20]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [20]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [20]),\n .O(\\axaddr_incr_reg[29] [15]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__4_i_1\n (.I0(s_axi_awaddr[27]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [27]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [27]),\n .O(\\axaddr_incr_reg[29] [22]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__4_i_2\n (.I0(s_axi_awaddr[26]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [26]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [26]),\n .O(\\axaddr_incr_reg[29] [21]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__4_i_3\n (.I0(s_axi_awaddr[25]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [25]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [25]),\n .O(\\axaddr_incr_reg[29] [20]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__4_i_4\n (.I0(s_axi_awaddr[24]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [24]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [24]),\n .O(\\axaddr_incr_reg[29] [19]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__5_i_1\n (.I0(s_axi_awaddr[29]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [29]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [29]),\n .O(\\axaddr_incr_reg[29] [24]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry__5_i_2\n (.I0(s_axi_awaddr[28]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [28]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [28]),\n .O(\\axaddr_incr_reg[29] [23]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry_i_1\n (.I0(s_axi_awaddr[5]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [5]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [5]),\n .O(\\axaddr_incr_reg[29] [1]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry_i_2\n (.I0(s_axi_awaddr[7]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [7]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [7]),\n .O(\\axaddr_incr_reg[29] [3]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry_i_3\n (.I0(s_axi_awaddr[6]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [6]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [6]),\n .O(\\axaddr_incr_reg[29] [2]));\n LUT5 #(\n .INIT(32'h111DDD1D)) \n axaddr_incr_p_reg0_carry_i_4\n (.I0(\\axaddr_incr_reg[29]_1 [5]),\n .I1(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I2(\\axaddr_reg[29]_0 [5]),\n .I3(s_axi_awready),\n .I4(s_axi_awaddr[5]),\n .O(S));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n axaddr_incr_p_reg0_carry_i_5\n (.I0(s_axi_awaddr[4]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [4]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(\\axaddr_incr_reg[29]_1 [4]),\n .O(\\axaddr_incr_reg[29] [0]));\n (* SOFT_HLUTNM = \"soft_lutpair1170\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axburst[1]_i_1 \n (.I0(s_axi_awburst),\n .I1(s_axi_awready),\n .I2(axburst),\n .O(\\axburst_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair1170\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axid[0]_i_1 \n (.I0(s_axi_awid),\n .I1(s_axi_awready),\n .I2(axid),\n .O(b_awid));\n LUT3 #(\n .INIT(8'hB8)) \n \\axlen[0]_i_1 \n (.I0(s_axi_awlen[0]),\n .I1(s_axi_awready),\n .I2(\\axlen_reg[7]_0 [0]),\n .O(axlen_int[0]));\n LUT3 #(\n .INIT(8'hB8)) \n \\axlen[1]_i_1 \n (.I0(s_axi_awlen[1]),\n .I1(s_axi_awready),\n .I2(\\axlen_reg[7]_0 [1]),\n .O(axlen_int[1]));\n LUT3 #(\n .INIT(8'hB8)) \n \\axlen[2]_i_1 \n (.I0(s_axi_awlen[2]),\n .I1(s_axi_awready),\n .I2(\\axlen_reg[7]_0 [2]),\n .O(axlen_int[2]));\n LUT3 #(\n .INIT(8'hB8)) \n \\axlen[3]_i_1 \n (.I0(s_axi_awlen[3]),\n .I1(s_axi_awready),\n .I2(\\axlen_reg[7]_0 [3]),\n .O(axlen_int[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1183\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axlen[4]_i_1 \n (.I0(s_axi_awlen[4]),\n .I1(s_axi_awready),\n .I2(\\axlen_reg[7]_0 [4]),\n .O(\\axlen_reg[7] [0]));\n (* SOFT_HLUTNM = \"soft_lutpair1183\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axlen[5]_i_1 \n (.I0(s_axi_awlen[5]),\n .I1(s_axi_awready),\n .I2(\\axlen_reg[7]_0 [5]),\n .O(\\axlen_reg[7] [1]));\n (* SOFT_HLUTNM = \"soft_lutpair1182\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axlen[6]_i_1 \n (.I0(s_axi_awlen[6]),\n .I1(s_axi_awready),\n .I2(\\axlen_reg[7]_0 [6]),\n .O(\\axlen_reg[7] [2]));\n (* SOFT_HLUTNM = \"soft_lutpair1181\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\axlen[7]_i_1 \n (.I0(s_axi_awlen[7]),\n .I1(s_axi_awready),\n .I2(\\axlen_reg[7]_0 [7]),\n .O(\\axlen_reg[7] [3]));\n LUT6 #(\n .INIT(64'hABABAB515151AB51)) \n \\axlen_cnt[0]_i_1 \n (.I0(axready_reg_0),\n .I1(Q[0]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axlen_reg[7]_0 [0]),\n .I4(s_axi_awready),\n .I5(s_axi_awlen[0]),\n .O(D[0]));\n LUT6 #(\n .INIT(64'hABABAB515151AB51)) \n \\axlen_cnt[0]_i_1__0 \n (.I0(axready_reg_1),\n .I1(\\axlen_cnt_reg[3]_0 [0]),\n .I2(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I3(\\axlen_reg[7]_0 [0]),\n .I4(s_axi_awready),\n .I5(s_axi_awlen[0]),\n .O(\\axlen_cnt_reg[3] [0]));\n LUT6 #(\n .INIT(64'hFFFFE4B100004E1B)) \n \\axlen_cnt[1]_i_1 \n (.I0(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I1(Q[1]),\n .I2(axlen_int[0]),\n .I3(Q[0]),\n .I4(axready_reg_0),\n .I5(axlen_int[1]),\n .O(D[1]));\n LUT6 #(\n .INIT(64'hFFFFE4B100004E1B)) \n \\axlen_cnt[1]_i_1__0 \n (.I0(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I1(\\axlen_cnt_reg[3]_0 [1]),\n .I2(axlen_int[0]),\n .I3(\\axlen_cnt_reg[3]_0 [0]),\n .I4(axready_reg_1),\n .I5(axlen_int[1]),\n .O(\\axlen_cnt_reg[3] [1]));\n LUT5 #(\n .INIT(32'hFFE1004B)) \n \\axlen_cnt[2]_i_1 \n (.I0(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I1(Q[2]),\n .I2(\\axlen_cnt[2]_i_2_n_0 ),\n .I3(axready_reg_0),\n .I4(axlen_int[2]),\n .O(D[2]));\n LUT5 #(\n .INIT(32'hFFE1004B)) \n \\axlen_cnt[2]_i_1__0 \n (.I0(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I1(\\axlen_cnt_reg[3]_0 [2]),\n .I2(\\axlen_cnt[2]_i_2__0_n_0 ),\n .I3(axready_reg_1),\n .I4(axlen_int[2]),\n .O(\\axlen_cnt_reg[3] [2]));\n LUT5 #(\n .INIT(32'hFFFACCFA)) \n \\axlen_cnt[2]_i_2 \n (.I0(Q[0]),\n .I1(axlen_int[0]),\n .I2(Q[1]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(axlen_int[1]),\n .O(\\axlen_cnt[2]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFACCFA)) \n \\axlen_cnt[2]_i_2__0 \n (.I0(\\axlen_cnt_reg[3]_0 [0]),\n .I1(axlen_int[0]),\n .I2(\\axlen_cnt_reg[3]_0 [1]),\n .I3(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I4(axlen_int[1]),\n .O(\\axlen_cnt[2]_i_2__0_n_0 ));\n LUT5 #(\n .INIT(32'hFFE1004B)) \n \\axlen_cnt[3]_i_1 \n (.I0(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I1(Q[3]),\n .I2(\\axlen_cnt[3]_i_2_n_0 ),\n .I3(axready_reg_0),\n .I4(axlen_int[3]),\n .O(D[3]));\n LUT5 #(\n .INIT(32'hFF1E00B4)) \n \\axlen_cnt[3]_i_1__0 \n (.I0(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I1(\\axlen_cnt_reg[3]_0 [3]),\n .I2(\\axlen_cnt[3]_i_2__0_n_0 ),\n .I3(axready_reg_1),\n .I4(axlen_int[3]),\n .O(\\axlen_cnt_reg[3] [3]));\n LUT6 #(\n .INIT(64'hFEFEFEAEAEAEFEAE)) \n \\axlen_cnt[3]_i_2 \n (.I0(\\axlen_cnt[2]_i_2_n_0 ),\n .I1(Q[2]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axlen_reg[7]_0 [2]),\n .I4(s_axi_awready),\n .I5(s_axi_awlen[2]),\n .O(\\axlen_cnt[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0101015151510151)) \n \\axlen_cnt[3]_i_2__0 \n (.I0(\\axlen_cnt[2]_i_2__0_n_0 ),\n .I1(\\axlen_cnt_reg[3]_0 [2]),\n .I2(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I3(\\axlen_reg[7]_0 [2]),\n .I4(s_axi_awready),\n .I5(s_axi_awlen[2]),\n .O(\\axlen_cnt[3]_i_2__0_n_0 ));\n LUT6 #(\n .INIT(64'hF606F6F6F6060606)) \n \\axlen_cnt[4]_i_1 \n (.I0(\\axlen_cnt[4]_i_2_n_0 ),\n .I1(\\axlen_cnt[4]_i_3_n_0 ),\n .I2(axready_reg_0),\n .I3(s_axi_awlen[4]),\n .I4(s_axi_awready),\n .I5(\\axlen_reg[7]_0 [4]),\n .O(D[4]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axlen_cnt[4]_i_2 \n (.I0(s_axi_awlen[4]),\n .I1(s_axi_awready),\n .I2(\\axlen_reg[7]_0 [4]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(Q[4]),\n .O(\\axlen_cnt[4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0101015151510151)) \n \\axlen_cnt[4]_i_3 \n (.I0(\\axlen_cnt[3]_i_2_n_0 ),\n .I1(Q[3]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(\\axlen_reg[7]_0 [3]),\n .I4(s_axi_awready),\n .I5(s_axi_awlen[3]),\n .O(\\axlen_cnt[4]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hF909F9F9F9090909)) \n \\axlen_cnt[5]_i_1 \n (.I0(\\axlen_cnt[5]_i_2_n_0 ),\n .I1(\\axlen_cnt[5]_i_3_n_0 ),\n .I2(axready_reg_0),\n .I3(s_axi_awlen[5]),\n .I4(s_axi_awready),\n .I5(\\axlen_reg[7]_0 [5]),\n .O(D[5]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axlen_cnt[5]_i_2 \n (.I0(s_axi_awlen[5]),\n .I1(s_axi_awready),\n .I2(\\axlen_reg[7]_0 [5]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(Q[5]),\n .O(\\axlen_cnt[5]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFEFEA)) \n \\axlen_cnt[5]_i_3 \n (.I0(\\axlen_cnt[4]_i_2_n_0 ),\n .I1(axlen_int[3]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(Q[3]),\n .I4(\\axlen_cnt[3]_i_2_n_0 ),\n .O(\\axlen_cnt[5]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hF909F9F9F9090909)) \n \\axlen_cnt[6]_i_1 \n (.I0(\\axlen_cnt[7]_i_3_n_0 ),\n .I1(\\axlen_cnt[7]_i_4_n_0 ),\n .I2(axready_reg_0),\n .I3(s_axi_awlen[6]),\n .I4(s_axi_awready),\n .I5(\\axlen_reg[7]_0 [6]),\n .O(D[6]));\n LUT5 #(\n .INIT(32'h0E000ECC)) \n \\axlen_cnt[7]_i_1 \n (.I0(s_axi_awvalid),\n .I1(\\RD_PRI_REG_STARVE.rnw_i_reg ),\n .I2(s_axi_awburst),\n .I3(s_axi_awready),\n .I4(axburst),\n .O(E));\n LUT6 #(\n .INIT(64'hFFFFEEE10000444B)) \n \\axlen_cnt[7]_i_2 \n (.I0(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I1(Q[7]),\n .I2(\\axlen_cnt[7]_i_3_n_0 ),\n .I3(\\axlen_cnt[7]_i_4_n_0 ),\n .I4(axready_reg_0),\n .I5(\\axlen_reg[7] [3]),\n .O(D[7]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\axlen_cnt[7]_i_3 \n (.I0(s_axi_awlen[6]),\n .I1(s_axi_awready),\n .I2(\\axlen_reg[7]_0 [6]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(Q[6]),\n .O(\\axlen_cnt[7]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFEAE)) \n \\axlen_cnt[7]_i_4 \n (.I0(\\axlen_cnt[3]_i_2_n_0 ),\n .I1(Q[3]),\n .I2(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I3(axlen_int[3]),\n .I4(\\axlen_cnt[4]_i_2_n_0 ),\n .I5(\\axlen_cnt[5]_i_2_n_0 ),\n .O(\\axlen_cnt[7]_i_4_n_0 ));\n LUT4 #(\n .INIT(16'hABFB)) \n axready_i_1\n (.I0(b_push),\n .I1(axvalid),\n .I2(s_axi_awready),\n .I3(s_axi_awvalid),\n .O(axready_i_1_n_0));\n FDRE axready_reg\n (.C(CLK),\n .CE(1'b1),\n .D(axready_i_1_n_0),\n .Q(s_axi_awready),\n .R(areset_d1));\n LUT3 #(\n .INIT(8'hB8)) \n axvalid_i_1\n (.I0(s_axi_awvalid),\n .I1(s_axi_awready),\n .I2(axvalid),\n .O(awvalid_int));\n LUT6 #(\n .INIT(64'hF606F6F6F6060606)) \n \\int_addr[0]_i_1 \n (.I0(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]),\n .I1(axlen_int[0]),\n .I2(axready_reg_1),\n .I3(s_axi_awaddr[5]),\n .I4(s_axi_awready),\n .I5(\\axaddr_reg[29]_0 [5]),\n .O(\\int_addr_reg[3] [0]));\n LUT6 #(\n .INIT(64'hBFBFBFEA40401540)) \n \\int_addr[1]_i_1 \n (.I0(axready_reg_1),\n .I1(axlen_int[1]),\n .I2(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]),\n .I3(\\int_addr_reg[3]_1 [1]),\n .I4(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I5(\\axaddr_reg[29] [6]),\n .O(\\int_addr_reg[3] [1]));\n (* SOFT_HLUTNM = \"soft_lutpair1164\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\int_addr[1]_i_2 \n (.I0(s_axi_awaddr[5]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [5]),\n .I3(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I4(\\int_addr_reg[3]_1 [0]),\n .O(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]));\n LUT6 #(\n .INIT(64'hBFBFBFEA40401540)) \n \\int_addr[2]_i_1 \n (.I0(axready_reg_1),\n .I1(axlen_int[2]),\n .I2(\\int_addr[3]_i_5_n_0 ),\n .I3(\\int_addr_reg[3]_1 [2]),\n .I4(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I5(\\axaddr_reg[29] [7]),\n .O(\\int_addr_reg[3] [2]));\n LUT3 #(\n .INIT(8'h80)) \n \\int_addr[2]_i_2 \n (.I0(s_axi_awvalid),\n .I1(s_axi_awready),\n .I2(s_axi_awburst),\n .O(\\axi_mc_cmd_translator_0/wrap_axhandshake ));\n LUT5 #(\n .INIT(32'hCFC08080)) \n \\int_addr[3]_i_1 \n (.I0(s_axi_awvalid),\n .I1(s_axi_awburst),\n .I2(s_axi_awready),\n .I3(axburst),\n .I4(\\RD_PRI_REG_STARVE.rnw_i_reg ),\n .O(\\axlen_cnt_reg[0] ));\n LUT6 #(\n .INIT(64'h8BBBBBBBB8888888)) \n \\int_addr[3]_i_2 \n (.I0(\\axaddr_reg[29] [8]),\n .I1(axready_reg_1),\n .I2(axlen_int[3]),\n .I3(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [7]),\n .I4(\\int_addr[3]_i_5_n_0 ),\n .I5(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [8]),\n .O(\\int_addr_reg[3] [3]));\n (* SOFT_HLUTNM = \"soft_lutpair1162\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\int_addr[3]_i_4 \n (.I0(s_axi_awaddr[7]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [7]),\n .I3(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I4(\\int_addr_reg[3]_1 [2]),\n .O(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [7]));\n LUT6 #(\n .INIT(64'hEEE222E200000000)) \n \\int_addr[3]_i_5 \n (.I0(\\int_addr_reg[3]_1 [1]),\n .I1(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I2(\\axaddr_reg[29]_0 [6]),\n .I3(s_axi_awready),\n .I4(s_axi_awaddr[6]),\n .I5(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [5]),\n .O(\\int_addr[3]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1161\" *) \n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\int_addr[3]_i_6 \n (.I0(s_axi_awaddr[8]),\n .I1(s_axi_awready),\n .I2(\\axaddr_reg[29]_0 [8]),\n .I3(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I4(\\int_addr_reg[3]_1 [3]),\n .O(\\axi_mc_cmd_translator_0/axi_mc_wrap_cmd_byte_addr [8]));\n LUT5 #(\n .INIT(32'hAA000C00)) \n \\memory_reg[7][0]_srl8_i_1 \n (.I0(\\memory_reg[7][0]_srl8_i_2_n_0 ),\n .I1(\\memory_reg[7][0]_srl8_i_3_n_0 ),\n .I2(\\axlen_cnt[3]_i_2_n_0 ),\n .I3(\\RD_PRI_REG_STARVE.rnw_i_reg ),\n .I4(\\axburst_reg[1] ),\n .O(b_push));\n LUT6 #(\n .INIT(64'h0000000000440347)) \n \\memory_reg[7][0]_srl8_i_2 \n (.I0(axlen_int[2]),\n .I1(\\axi_mc_cmd_translator_0/wrap_axhandshake ),\n .I2(\\axlen_cnt_reg[3]_0 [2]),\n .I3(axlen_int[3]),\n .I4(\\axlen_cnt_reg[3]_0 [3]),\n .I5(\\axlen_cnt[2]_i_2__0_n_0 ),\n .O(\\memory_reg[7][0]_srl8_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h00000001)) \n \\memory_reg[7][0]_srl8_i_3 \n (.I0(\\axlen_cnt[4]_i_2_n_0 ),\n .I1(\\axlen_cnt[5]_i_2_n_0 ),\n .I2(\\memory_reg[7][0]_srl8_i_4_n_0 ),\n .I3(\\memory_reg[7][0]_srl8_i_5_n_0 ),\n .I4(\\axlen_cnt[7]_i_3_n_0 ),\n .O(\\memory_reg[7][0]_srl8_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\memory_reg[7][0]_srl8_i_4 \n (.I0(s_axi_awlen[7]),\n .I1(s_axi_awready),\n .I2(\\axlen_reg[7]_0 [7]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(Q[7]),\n .O(\\memory_reg[7][0]_srl8_i_4_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\memory_reg[7][0]_srl8_i_5 \n (.I0(s_axi_awlen[3]),\n .I1(s_axi_awready),\n .I2(\\axlen_reg[7]_0 [3]),\n .I3(\\axi_mc_cmd_translator_0/incr_axhandshake ),\n .I4(Q[3]),\n .O(\\memory_reg[7][0]_srl8_i_5_n_0 ));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_axi_mc_wrap_cmd\n (\\int_addr_reg[3]_0 ,\n \\axlen_cnt_reg[3]_0 ,\n areset_d1,\n axready_reg,\n axready_reg_0,\n CLK,\n \\axlen_cnt_reg[3]_1 );\n output [3:0]\\int_addr_reg[3]_0 ;\n output [3:0]\\axlen_cnt_reg[3]_0 ;\n input areset_d1;\n input [0:0]axready_reg;\n input [3:0]axready_reg_0;\n input CLK;\n input [3:0]\\axlen_cnt_reg[3]_1 ;\n\n wire CLK;\n wire areset_d1;\n wire [3:0]\\axlen_cnt_reg[3]_0 ;\n wire [3:0]\\axlen_cnt_reg[3]_1 ;\n wire [0:0]axready_reg;\n wire [3:0]axready_reg_0;\n wire [3:0]\\int_addr_reg[3]_0 ;\n\n FDSE \\axlen_cnt_reg[0] \n (.C(CLK),\n .CE(axready_reg),\n .D(\\axlen_cnt_reg[3]_1 [0]),\n .Q(\\axlen_cnt_reg[3]_0 [0]),\n .S(areset_d1));\n FDSE \\axlen_cnt_reg[1] \n (.C(CLK),\n .CE(axready_reg),\n .D(\\axlen_cnt_reg[3]_1 [1]),\n .Q(\\axlen_cnt_reg[3]_0 [1]),\n .S(areset_d1));\n FDSE \\axlen_cnt_reg[2] \n (.C(CLK),\n .CE(axready_reg),\n .D(\\axlen_cnt_reg[3]_1 [2]),\n .Q(\\axlen_cnt_reg[3]_0 [2]),\n .S(areset_d1));\n FDSE \\axlen_cnt_reg[3] \n (.C(CLK),\n .CE(axready_reg),\n .D(\\axlen_cnt_reg[3]_1 [3]),\n .Q(\\axlen_cnt_reg[3]_0 [3]),\n .S(areset_d1));\n FDRE \\int_addr_reg[0] \n (.C(CLK),\n .CE(axready_reg),\n .D(axready_reg_0[0]),\n .Q(\\int_addr_reg[3]_0 [0]),\n .R(areset_d1));\n FDRE \\int_addr_reg[1] \n (.C(CLK),\n .CE(axready_reg),\n .D(axready_reg_0[1]),\n .Q(\\int_addr_reg[3]_0 [1]),\n .R(areset_d1));\n FDRE \\int_addr_reg[2] \n (.C(CLK),\n .CE(axready_reg),\n .D(axready_reg_0[2]),\n .Q(\\int_addr_reg[3]_0 [2]),\n .R(areset_d1));\n FDRE \\int_addr_reg[3] \n (.C(CLK),\n .CE(axready_reg),\n .D(axready_reg_0[3]),\n .Q(\\int_addr_reg[3]_0 [3]),\n .R(areset_d1));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_axi_mc_wrap_cmd\" *) \nmodule ddr3_if_mig_7series_v4_0_axi_mc_wrap_cmd__parameterized0\n (\\app_addr_r1_reg[6] ,\n \\axlen_cnt_reg[3]_0 ,\n areset_d1,\n axready_reg,\n axready_reg_0,\n CLK,\n \\axlen_cnt_reg[3]_1 );\n output [3:0]\\app_addr_r1_reg[6] ;\n output [3:0]\\axlen_cnt_reg[3]_0 ;\n input areset_d1;\n input [0:0]axready_reg;\n input [3:0]axready_reg_0;\n input CLK;\n input [3:0]\\axlen_cnt_reg[3]_1 ;\n\n wire CLK;\n wire [3:0]\\app_addr_r1_reg[6] ;\n wire areset_d1;\n wire [3:0]\\axlen_cnt_reg[3]_0 ;\n wire [3:0]\\axlen_cnt_reg[3]_1 ;\n wire [0:0]axready_reg;\n wire [3:0]axready_reg_0;\n\n FDSE \\axlen_cnt_reg[0] \n (.C(CLK),\n .CE(axready_reg),\n .D(\\axlen_cnt_reg[3]_1 [0]),\n .Q(\\axlen_cnt_reg[3]_0 [0]),\n .S(areset_d1));\n FDSE \\axlen_cnt_reg[1] \n (.C(CLK),\n .CE(axready_reg),\n .D(\\axlen_cnt_reg[3]_1 [1]),\n .Q(\\axlen_cnt_reg[3]_0 [1]),\n .S(areset_d1));\n FDSE \\axlen_cnt_reg[2] \n (.C(CLK),\n .CE(axready_reg),\n .D(\\axlen_cnt_reg[3]_1 [2]),\n .Q(\\axlen_cnt_reg[3]_0 [2]),\n .S(areset_d1));\n FDSE \\axlen_cnt_reg[3] \n (.C(CLK),\n .CE(axready_reg),\n .D(\\axlen_cnt_reg[3]_1 [3]),\n .Q(\\axlen_cnt_reg[3]_0 [3]),\n .S(areset_d1));\n FDRE \\int_addr_reg[0] \n (.C(CLK),\n .CE(axready_reg),\n .D(axready_reg_0[0]),\n .Q(\\app_addr_r1_reg[6] [0]),\n .R(areset_d1));\n FDRE \\int_addr_reg[1] \n (.C(CLK),\n .CE(axready_reg),\n .D(axready_reg_0[1]),\n .Q(\\app_addr_r1_reg[6] [1]),\n .R(areset_d1));\n FDRE \\int_addr_reg[2] \n (.C(CLK),\n .CE(axready_reg),\n .D(axready_reg_0[2]),\n .Q(\\app_addr_r1_reg[6] [2]),\n .R(areset_d1));\n FDRE \\int_addr_reg[3] \n (.C(CLK),\n .CE(axready_reg),\n .D(axready_reg_0[3]),\n .Q(\\app_addr_r1_reg[6] [3]),\n .R(areset_d1));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_bank_cntrl\n (E,\n req_periodic_rd_r,\n \\rd_this_rank_r_reg[0] ,\n bm_end_r1_reg,\n q_has_priority_r_reg,\n row_hit_r,\n bm_end_r1,\n \\act_this_rank_r_reg[0] ,\n \\rp_timer.rp_timer_r_reg[1] ,\n act_this_rank_r,\n req_bank_rdy_ns,\n demand_priority_r_reg,\n demanded_prior_r_reg,\n ofs_rdy_r,\n wr_this_rank_r,\n rd_this_rank_r,\n act_wait_r_lcl_reg,\n pre_bm_end_r,\n q_has_rd,\n q_has_priority,\n wait_for_maint_r,\n \\starve_limit_cntr_r_reg[2] ,\n tail_r,\n wait_for_maint_r_lcl_reg,\n \\rp_timer.rp_timer_r_reg[1]_0 ,\n ordered_r,\n D,\n accept_internal_r_reg,\n \\q_entry_r_reg[0] ,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ,\n granted_col_ns,\n granted_col_r_reg,\n \\grant_r_reg[1] ,\n \\ras_timer_r_reg[0] ,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ,\n \\ras_timer_r_reg[1] ,\n \\ras_timer_r_reg[2] ,\n \\ras_timer_r_reg[0]_0 ,\n \\q_entry_r_reg[1] ,\n q_entry_ns,\n \\q_entry_r_reg[1]_0 ,\n \\q_entry_r_reg[1]_1 ,\n \\q_entry_r_reg[0]_0 ,\n p_9_in,\n head_r_lcl_reg,\n head_r_lcl_reg_0,\n head_r_lcl_reg_1,\n head_r_lcl_reg_2,\n \\q_entry_r_reg[1]_2 ,\n \\grant_r_reg[2] ,\n \\ras_timer_r_reg[0]_1 ,\n \\ras_timer_r_reg[0]_2 ,\n \\ras_timer_r_reg[0]_3 ,\n \\pre_4_1_1T_arb.granted_pre_r_reg ,\n auto_pre_r_lcl_reg,\n head_r_lcl_reg_3,\n \\cmd_pipe_plus.mc_address_reg[14] ,\n \\rnk_config_strobe_r_reg[0] ,\n demanded_prior_r_reg_0,\n \\col_mux.col_data_buf_addr_r_reg[4] ,\n \\cmd_pipe_plus.mc_bank_reg[2] ,\n \\cmd_pipe_plus.mc_address_reg[24] ,\n CLK,\n periodic_rd_insert,\n hi_priority,\n SR,\n ofs_rdy_r0,\n q_has_rd_r_reg,\n q_has_priority_r_reg_0,\n \\maintenance_request.maint_req_r_lcl_reg ,\n wait_for_maint_r_lcl_reg_0,\n idle_r_lcl_reg,\n rstdiv0_sync_r1_reg_rep__0,\n head_r_lcl_reg_4,\n auto_pre_r_lcl_reg_0,\n ordered_r_lcl_reg,\n \\req_bank_r_lcl_reg[0] ,\n idle_r_lcl_reg_0,\n Q,\n rstdiv0_sync_r1_reg_rep__20,\n idle_r_lcl_reg_1,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ,\n idle_r_lcl_reg_2,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ,\n rd_wr_r_lcl_reg,\n rd_wr_r_lcl_reg_0,\n \\rtw_timer.rtw_cnt_r_reg[1] ,\n col_wait_r_reg,\n override_demand_r_reg,\n \\wtr_timer.wtr_cnt_r_reg[1] ,\n rd_wr_r_lcl_reg_1,\n \\ras_timer_r_reg[1]_0 ,\n \\ras_timer_r_reg[1]_1 ,\n bm_end_r1_reg_0,\n bm_end_r1_reg_1,\n bm_end_r1_reg_2,\n \\ras_timer_r_reg[2]_0 ,\n \\ras_timer_r_reg[2]_1 ,\n \\ras_timer_r_reg[2]_2 ,\n req_wr_r_lcl_reg,\n rd_wr_r_lcl_reg_2,\n req_wr_r_lcl_reg_0,\n rnk_config_valid_r_lcl_reg,\n \\grant_r_reg[2]_0 ,\n \\grant_r_reg[0] ,\n bm_end_r1_reg_3,\n pre_passing_open_bank_r_reg,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ,\n pre_passing_open_bank_r_reg_0,\n \\q_entry_r_reg[1]_3 ,\n pre_bm_end_r_reg,\n pre_bm_end_r_reg_0,\n \\q_entry_r_reg[1]_4 ,\n periodic_rd_ack_r_lcl_reg,\n init_calib_complete_reg_rep__6,\n accept_r_reg,\n periodic_rd_ack_r_lcl_reg_0,\n pre_bm_end_r_reg_1,\n \\app_cmd_r2_reg[1] ,\n \\app_cmd_r1_reg[0] ,\n periodic_rd_ack_r_lcl_reg_1,\n periodic_rd_cntr_r_reg,\n periodic_rd_r,\n periodic_rd_ack_r_lcl_reg_2,\n use_addr,\n accept_internal_r_reg_0,\n req_wr_r_lcl_reg_1,\n rtp_timer_ns1,\n accept_r_reg_0,\n rstdiv0_sync_r1_reg_rep__21,\n \\grant_r_reg[0]_0 ,\n rstdiv0_sync_r1_reg_rep__22,\n idle_r_lcl_reg_3,\n idle_r_lcl_reg_4,\n idle_r_lcl_reg_5,\n maint_req_r,\n \\maint_controller.maint_wip_r_lcl_reg ,\n \\app_addr_r1_reg[27] ,\n demand_priority_r_reg_0,\n demanded_prior_r_reg_1,\n demanded_prior_r_reg_2,\n granted_col_r_reg_0,\n rb_hit_busy_r_reg,\n rb_hit_busy_r_reg_0,\n rb_hit_busy_r_reg_1,\n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ,\n \\app_addr_r1_reg[12] ,\n \\app_addr_r1_reg[9] ,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ,\n rb_hit_busy_r_reg_2,\n idle_r_lcl_reg_6,\n ordered_r_lcl_reg_0,\n ordered_r_lcl_reg_1);\n output [0:0]E;\n output [0:0]req_periodic_rd_r;\n output \\rd_this_rank_r_reg[0] ;\n output bm_end_r1_reg;\n output q_has_priority_r_reg;\n output row_hit_r;\n output bm_end_r1;\n output \\act_this_rank_r_reg[0] ;\n output \\rp_timer.rp_timer_r_reg[1] ;\n output [0:0]act_this_rank_r;\n output req_bank_rdy_ns;\n output demand_priority_r_reg;\n output demanded_prior_r_reg;\n output ofs_rdy_r;\n output [0:0]wr_this_rank_r;\n output [0:0]rd_this_rank_r;\n output act_wait_r_lcl_reg;\n output pre_bm_end_r;\n output q_has_rd;\n output q_has_priority;\n output wait_for_maint_r;\n output \\starve_limit_cntr_r_reg[2] ;\n output tail_r;\n output wait_for_maint_r_lcl_reg;\n output \\rp_timer.rp_timer_r_reg[1]_0 ;\n output [0:0]ordered_r;\n output [0:0]D;\n output accept_internal_r_reg;\n output \\q_entry_r_reg[0] ;\n output [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;\n output [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;\n output granted_col_ns;\n output granted_col_r_reg;\n output \\grant_r_reg[1] ;\n output \\ras_timer_r_reg[0] ;\n output [2:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;\n output \\ras_timer_r_reg[1] ;\n output \\ras_timer_r_reg[2] ;\n output \\ras_timer_r_reg[0]_0 ;\n output \\q_entry_r_reg[1] ;\n output [0:0]q_entry_ns;\n output \\q_entry_r_reg[1]_0 ;\n output \\q_entry_r_reg[1]_1 ;\n output \\q_entry_r_reg[0]_0 ;\n output p_9_in;\n output head_r_lcl_reg;\n output head_r_lcl_reg_0;\n output head_r_lcl_reg_1;\n output head_r_lcl_reg_2;\n output \\q_entry_r_reg[1]_2 ;\n output \\grant_r_reg[2] ;\n output \\ras_timer_r_reg[0]_1 ;\n output \\ras_timer_r_reg[0]_2 ;\n output \\ras_timer_r_reg[0]_3 ;\n output \\pre_4_1_1T_arb.granted_pre_r_reg ;\n output auto_pre_r_lcl_reg;\n output head_r_lcl_reg_3;\n output [14:0]\\cmd_pipe_plus.mc_address_reg[14] ;\n output \\rnk_config_strobe_r_reg[0] ;\n output demanded_prior_r_reg_0;\n output [4:0]\\col_mux.col_data_buf_addr_r_reg[4] ;\n output [2:0]\\cmd_pipe_plus.mc_bank_reg[2] ;\n output [6:0]\\cmd_pipe_plus.mc_address_reg[24] ;\n input CLK;\n input periodic_rd_insert;\n input hi_priority;\n input [0:0]SR;\n input ofs_rdy_r0;\n input q_has_rd_r_reg;\n input q_has_priority_r_reg_0;\n input \\maintenance_request.maint_req_r_lcl_reg ;\n input wait_for_maint_r_lcl_reg_0;\n input idle_r_lcl_reg;\n input rstdiv0_sync_r1_reg_rep__0;\n input head_r_lcl_reg_4;\n input auto_pre_r_lcl_reg_0;\n input ordered_r_lcl_reg;\n input \\req_bank_r_lcl_reg[0] ;\n input idle_r_lcl_reg_0;\n input [0:0]Q;\n input rstdiv0_sync_r1_reg_rep__20;\n input idle_r_lcl_reg_1;\n input [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ;\n input idle_r_lcl_reg_2;\n input [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ;\n input rd_wr_r_lcl_reg;\n input rd_wr_r_lcl_reg_0;\n input \\rtw_timer.rtw_cnt_r_reg[1] ;\n input col_wait_r_reg;\n input override_demand_r_reg;\n input \\wtr_timer.wtr_cnt_r_reg[1] ;\n input rd_wr_r_lcl_reg_1;\n input \\ras_timer_r_reg[1]_0 ;\n input \\ras_timer_r_reg[1]_1 ;\n input bm_end_r1_reg_0;\n input bm_end_r1_reg_1;\n input bm_end_r1_reg_2;\n input \\ras_timer_r_reg[2]_0 ;\n input \\ras_timer_r_reg[2]_1 ;\n input \\ras_timer_r_reg[2]_2 ;\n input req_wr_r_lcl_reg;\n input rd_wr_r_lcl_reg_2;\n input req_wr_r_lcl_reg_0;\n input rnk_config_valid_r_lcl_reg;\n input [1:0]\\grant_r_reg[2]_0 ;\n input [0:0]\\grant_r_reg[0] ;\n input bm_end_r1_reg_3;\n input pre_passing_open_bank_r_reg;\n input \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ;\n input pre_passing_open_bank_r_reg_0;\n input \\q_entry_r_reg[1]_3 ;\n input pre_bm_end_r_reg;\n input pre_bm_end_r_reg_0;\n input \\q_entry_r_reg[1]_4 ;\n input periodic_rd_ack_r_lcl_reg;\n input init_calib_complete_reg_rep__6;\n input accept_r_reg;\n input periodic_rd_ack_r_lcl_reg_0;\n input pre_bm_end_r_reg_1;\n input [0:0]\\app_cmd_r2_reg[1] ;\n input \\app_cmd_r1_reg[0] ;\n input periodic_rd_ack_r_lcl_reg_1;\n input periodic_rd_cntr_r_reg;\n input periodic_rd_r;\n input periodic_rd_ack_r_lcl_reg_2;\n input use_addr;\n input accept_internal_r_reg_0;\n input req_wr_r_lcl_reg_1;\n input rtp_timer_ns1;\n input accept_r_reg_0;\n input rstdiv0_sync_r1_reg_rep__21;\n input [0:0]\\grant_r_reg[0]_0 ;\n input rstdiv0_sync_r1_reg_rep__22;\n input [0:0]idle_r_lcl_reg_3;\n input [0:0]idle_r_lcl_reg_4;\n input [0:0]idle_r_lcl_reg_5;\n input maint_req_r;\n input \\maint_controller.maint_wip_r_lcl_reg ;\n input [14:0]\\app_addr_r1_reg[27] ;\n input demand_priority_r_reg_0;\n input demanded_prior_r_reg_1;\n input demanded_prior_r_reg_2;\n input granted_col_r_reg_0;\n input rb_hit_busy_r_reg;\n input rb_hit_busy_r_reg_0;\n input rb_hit_busy_r_reg_1;\n input [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n input [2:0]\\app_addr_r1_reg[12] ;\n input [6:0]\\app_addr_r1_reg[9] ;\n input [2:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;\n input rb_hit_busy_r_reg_2;\n input idle_r_lcl_reg_6;\n input ordered_r_lcl_reg_0;\n input ordered_r_lcl_reg_1;\n\n wire CLK;\n wire [0:0]D;\n wire [0:0]E;\n wire [0:0]Q;\n wire [0:0]SR;\n wire accept_internal_r_reg;\n wire accept_internal_r_reg_0;\n wire accept_r_reg;\n wire accept_r_reg_0;\n wire [0:0]act_this_rank_r;\n wire \\act_this_rank_r_reg[0] ;\n wire act_wait_ns;\n wire act_wait_r_lcl_reg;\n wire [2:0]\\app_addr_r1_reg[12] ;\n wire [14:0]\\app_addr_r1_reg[27] ;\n wire [6:0]\\app_addr_r1_reg[9] ;\n wire \\app_cmd_r1_reg[0] ;\n wire [0:0]\\app_cmd_r2_reg[1] ;\n wire auto_pre_r_lcl_reg;\n wire auto_pre_r_lcl_reg_0;\n wire bank_compare0_n_12;\n wire bank_queue0_n_23;\n wire bank_queue0_n_27;\n wire bm_end_r1;\n wire bm_end_r1_reg;\n wire bm_end_r1_reg_0;\n wire bm_end_r1_reg_1;\n wire bm_end_r1_reg_2;\n wire bm_end_r1_reg_3;\n wire [14:0]\\cmd_pipe_plus.mc_address_reg[14] ;\n wire [6:0]\\cmd_pipe_plus.mc_address_reg[24] ;\n wire [2:0]\\cmd_pipe_plus.mc_bank_reg[2] ;\n wire [4:0]\\col_mux.col_data_buf_addr_r_reg[4] ;\n wire col_wait_r_reg;\n wire demand_priority_r_reg;\n wire demand_priority_r_reg_0;\n wire demanded_prior_r_reg;\n wire demanded_prior_r_reg_0;\n wire demanded_prior_r_reg_1;\n wire demanded_prior_r_reg_2;\n wire [0:0]\\grant_r_reg[0] ;\n wire [0:0]\\grant_r_reg[0]_0 ;\n wire \\grant_r_reg[1] ;\n wire \\grant_r_reg[2] ;\n wire [1:0]\\grant_r_reg[2]_0 ;\n wire granted_col_ns;\n wire granted_col_r_reg;\n wire granted_col_r_reg_0;\n wire head_r_lcl_reg;\n wire head_r_lcl_reg_0;\n wire head_r_lcl_reg_1;\n wire head_r_lcl_reg_2;\n wire head_r_lcl_reg_3;\n wire head_r_lcl_reg_4;\n wire hi_priority;\n wire [0:0]idle_ns;\n wire idle_r_lcl_reg;\n wire idle_r_lcl_reg_0;\n wire idle_r_lcl_reg_1;\n wire idle_r_lcl_reg_2;\n wire [0:0]idle_r_lcl_reg_3;\n wire [0:0]idle_r_lcl_reg_4;\n wire [0:0]idle_r_lcl_reg_5;\n wire idle_r_lcl_reg_6;\n wire init_calib_complete_reg_rep__6;\n wire \\maint_controller.maint_wip_r_lcl_reg ;\n wire maint_req_r;\n wire \\maintenance_request.maint_req_r_lcl_reg ;\n wire [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n wire ofs_rdy_r;\n wire ofs_rdy_r0;\n wire [0:0]ordered_r;\n wire ordered_r_lcl_reg;\n wire ordered_r_lcl_reg_0;\n wire ordered_r_lcl_reg_1;\n wire override_demand_r_reg;\n wire p_130_out;\n wire p_145_out;\n wire p_9_in;\n wire pass_open_bank_ns;\n wire periodic_rd_ack_r_lcl_reg;\n wire periodic_rd_ack_r_lcl_reg_0;\n wire periodic_rd_ack_r_lcl_reg_1;\n wire periodic_rd_ack_r_lcl_reg_2;\n wire periodic_rd_cntr_r_reg;\n wire periodic_rd_insert;\n wire periodic_rd_r;\n wire \\pre_4_1_1T_arb.granted_pre_r_reg ;\n wire pre_bm_end_ns;\n wire pre_bm_end_r;\n wire pre_bm_end_r_reg;\n wire pre_bm_end_r_reg_0;\n wire pre_bm_end_r_reg_1;\n wire pre_passing_open_bank_ns;\n wire pre_passing_open_bank_r;\n wire pre_passing_open_bank_r_reg;\n wire pre_passing_open_bank_r_reg_0;\n wire pre_wait_r;\n wire [0:0]q_entry_ns;\n wire \\q_entry_r_reg[0] ;\n wire \\q_entry_r_reg[0]_0 ;\n wire \\q_entry_r_reg[1] ;\n wire \\q_entry_r_reg[1]_0 ;\n wire \\q_entry_r_reg[1]_1 ;\n wire \\q_entry_r_reg[1]_2 ;\n wire \\q_entry_r_reg[1]_3 ;\n wire \\q_entry_r_reg[1]_4 ;\n wire q_has_priority;\n wire q_has_priority_r_reg;\n wire q_has_priority_r_reg_0;\n wire q_has_rd;\n wire q_has_rd_r_reg;\n wire [2:0]ras_timer_passed_ns;\n wire \\ras_timer_r_reg[0] ;\n wire \\ras_timer_r_reg[0]_0 ;\n wire \\ras_timer_r_reg[0]_1 ;\n wire \\ras_timer_r_reg[0]_2 ;\n wire \\ras_timer_r_reg[0]_3 ;\n wire \\ras_timer_r_reg[1] ;\n wire \\ras_timer_r_reg[1]_0 ;\n wire \\ras_timer_r_reg[1]_1 ;\n wire \\ras_timer_r_reg[2] ;\n wire \\ras_timer_r_reg[2]_0 ;\n wire \\ras_timer_r_reg[2]_1 ;\n wire \\ras_timer_r_reg[2]_2 ;\n wire \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ;\n wire [2:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;\n wire [2:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ;\n wire rb_hit_busy_r_reg;\n wire rb_hit_busy_r_reg_0;\n wire rb_hit_busy_r_reg_1;\n wire rb_hit_busy_r_reg_2;\n wire [0:0]rd_this_rank_r;\n wire \\rd_this_rank_r_reg[0] ;\n wire rd_wr_r_lcl_reg;\n wire rd_wr_r_lcl_reg_0;\n wire rd_wr_r_lcl_reg_1;\n wire rd_wr_r_lcl_reg_2;\n wire \\req_bank_r_lcl_reg[0] ;\n wire req_bank_rdy_ns;\n wire [0:0]req_periodic_rd_r;\n wire req_priority_r;\n wire req_wr_r_lcl_reg;\n wire req_wr_r_lcl_reg_0;\n wire req_wr_r_lcl_reg_1;\n wire \\rnk_config_strobe_r_reg[0] ;\n wire rnk_config_valid_r_lcl_reg;\n wire row_hit_r;\n wire \\rp_timer.rp_timer_r_reg[1] ;\n wire \\rp_timer.rp_timer_r_reg[1]_0 ;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire rstdiv0_sync_r1_reg_rep__22;\n wire rtp_timer_ns1;\n wire \\rtw_timer.rtw_cnt_r_reg[1] ;\n wire start_wtp_timer0;\n wire \\starve_limit_cntr_r_reg[2] ;\n wire tail_r;\n wire use_addr;\n wire wait_for_maint_r;\n wire wait_for_maint_r_lcl_reg;\n wire wait_for_maint_r_lcl_reg_0;\n wire [0:0]wr_this_rank_r;\n wire \\wtr_timer.wtr_cnt_r_reg[1] ;\n\n ddr3_if_mig_7series_v4_0_bank_compare_2 bank_compare0\n (.CLK(CLK),\n .E(idle_ns),\n .Q(Q),\n .accept_r_reg(accept_r_reg_0),\n .\\app_addr_r1_reg[12] (\\app_addr_r1_reg[12] ),\n .\\app_addr_r1_reg[27] (\\app_addr_r1_reg[27] ),\n .\\app_addr_r1_reg[9] (\\app_addr_r1_reg[9] ),\n .\\app_cmd_r1_reg[0] (\\app_cmd_r1_reg[0] ),\n .\\app_cmd_r2_reg[1] (\\app_cmd_r2_reg[1] ),\n .bm_end_r1_reg(bm_end_r1_reg),\n .\\cmd_pipe_plus.mc_address_reg[14] (\\cmd_pipe_plus.mc_address_reg[14] ),\n .\\cmd_pipe_plus.mc_address_reg[24] (\\cmd_pipe_plus.mc_address_reg[24] ),\n .\\cmd_pipe_plus.mc_bank_reg[2] (\\cmd_pipe_plus.mc_bank_reg[2] ),\n .\\col_mux.col_data_buf_addr_r_reg[4] (\\col_mux.col_data_buf_addr_r_reg[4] ),\n .\\grant_r_reg[0] (\\grant_r_reg[2]_0 [0]),\n .\\grant_r_reg[2] (\\grant_r_reg[2] ),\n .head_r_lcl_reg(head_r_lcl_reg_0),\n .head_r_lcl_reg_0(head_r_lcl_reg_1),\n .hi_priority(hi_priority),\n .idle_r_lcl_reg(accept_internal_r_reg),\n .idle_r_lcl_reg_0(E),\n .\\maint_controller.maint_wip_r_lcl_reg (\\maint_controller.maint_wip_r_lcl_reg ),\n .maint_req_r(maint_req_r),\n .\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),\n .p_130_out(p_130_out),\n .p_145_out(p_145_out),\n .pass_open_bank_ns(pass_open_bank_ns),\n .pass_open_bank_r_lcl_reg(act_wait_r_lcl_reg),\n .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg_1),\n .periodic_rd_ack_r_lcl_reg_0(periodic_rd_ack_r_lcl_reg_2),\n .periodic_rd_cntr_r_reg(periodic_rd_cntr_r_reg),\n .periodic_rd_insert(periodic_rd_insert),\n .periodic_rd_r(periodic_rd_r),\n .pre_bm_end_r(pre_bm_end_r),\n .pre_passing_open_bank_r(pre_passing_open_bank_r),\n .pre_wait_r(pre_wait_r),\n .q_has_priority_r_reg(q_has_priority_r_reg),\n .\\ras_timer_r_reg[0] (\\ras_timer_r_reg[0]_1 ),\n .\\ras_timer_r_reg[0]_0 (\\ras_timer_r_reg[0]_2 ),\n .ras_timer_zero_r_reg(bank_compare0_n_12),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ),\n .rb_hit_busy_r_reg_0(rb_hit_busy_r_reg),\n .rb_hit_busy_r_reg_1(rb_hit_busy_r_reg_0),\n .rb_hit_busy_r_reg_2(rb_hit_busy_r_reg_1),\n .\\rd_this_rank_r_reg[0] (\\rd_this_rank_r_reg[0] ),\n .req_periodic_rd_r(req_periodic_rd_r),\n .req_priority_r(req_priority_r),\n .req_wr_r_lcl_reg_0(req_wr_r_lcl_reg_1),\n .row_hit_r(row_hit_r),\n .start_wtp_timer0(start_wtp_timer0),\n .tail_r(tail_r),\n .wait_for_maint_r(wait_for_maint_r));\n ddr3_if_mig_7series_v4_0_bank_queue bank_queue0\n (.CLK(CLK),\n .D(D),\n .E(idle_ns),\n .Q(Q),\n .SR(SR),\n .accept_internal_r_reg(accept_internal_r_reg),\n .accept_internal_r_reg_0(accept_internal_r_reg_0),\n .accept_r_reg(accept_r_reg),\n .act_wait_ns(act_wait_ns),\n .act_wait_r_lcl_reg(act_wait_r_lcl_reg),\n .act_wait_r_lcl_reg_0(\\act_this_rank_r_reg[0] ),\n .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_0),\n .bm_end_r1_reg(\\ras_timer_r_reg[1] ),\n .bm_end_r1_reg_0(bm_end_r1_reg_0),\n .bm_end_r1_reg_1(bm_end_r1_reg_1),\n .bm_end_r1_reg_2(bm_end_r1_reg_2),\n .bm_end_r1_reg_3(\\ras_timer_r_reg[2] ),\n .bm_end_r1_reg_4(bm_end_r1_reg_3),\n .col_wait_r_reg(col_wait_r_reg),\n .col_wait_r_reg_0(\\starve_limit_cntr_r_reg[2] ),\n .demand_priority_r_reg(bank_queue0_n_27),\n .\\grant_r_reg[0] (\\grant_r_reg[0] ),\n .\\grant_r_reg[0]_0 (\\grant_r_reg[2]_0 [0]),\n .\\grant_r_reg[1] (\\grant_r_reg[1] ),\n .granted_col_ns(granted_col_ns),\n .granted_col_r_reg(granted_col_r_reg),\n .head_r_lcl_reg_0(head_r_lcl_reg),\n .head_r_lcl_reg_1(head_r_lcl_reg_2),\n .head_r_lcl_reg_2(head_r_lcl_reg_3),\n .head_r_lcl_reg_3(head_r_lcl_reg_4),\n .idle_r_lcl_reg_0(idle_r_lcl_reg),\n .idle_r_lcl_reg_1(idle_r_lcl_reg_0),\n .idle_r_lcl_reg_2(idle_r_lcl_reg_1),\n .idle_r_lcl_reg_3(idle_r_lcl_reg_2),\n .idle_r_lcl_reg_4(idle_r_lcl_reg_3),\n .idle_r_lcl_reg_5(idle_r_lcl_reg_4),\n .idle_r_lcl_reg_6(idle_r_lcl_reg_5),\n .idle_r_lcl_reg_7(idle_r_lcl_reg_6),\n .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6),\n .\\maintenance_request.maint_req_r_lcl_reg (\\maintenance_request.maint_req_r_lcl_reg ),\n .ordered_r(ordered_r),\n .ordered_r_lcl_reg_0(ordered_r_lcl_reg),\n .ordered_r_lcl_reg_1(ordered_r_lcl_reg_0),\n .ordered_r_lcl_reg_2(ordered_r_lcl_reg_1),\n .override_demand_r_reg(override_demand_r_reg),\n .p_145_out(p_145_out),\n .p_9_in(p_9_in),\n .pass_open_bank_ns(pass_open_bank_ns),\n .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg),\n .periodic_rd_ack_r_lcl_reg_0(periodic_rd_ack_r_lcl_reg_0),\n .periodic_rd_ack_r_lcl_reg_1(periodic_rd_ack_r_lcl_reg_1),\n .pre_bm_end_ns(pre_bm_end_ns),\n .pre_bm_end_r(pre_bm_end_r),\n .pre_bm_end_r_reg_0(pre_bm_end_r_reg),\n .pre_bm_end_r_reg_1(pre_bm_end_r_reg_0),\n .pre_bm_end_r_reg_2(pre_bm_end_r_reg_1),\n .pre_passing_open_bank_ns(pre_passing_open_bank_ns),\n .pre_passing_open_bank_r(pre_passing_open_bank_r),\n .pre_passing_open_bank_r_reg_0(pre_passing_open_bank_r_reg),\n .pre_passing_open_bank_r_reg_1(pre_passing_open_bank_r_reg_0),\n .q_entry_ns(q_entry_ns),\n .\\q_entry_r_reg[0]_0 (\\q_entry_r_reg[0] ),\n .\\q_entry_r_reg[0]_1 (\\q_entry_r_reg[0]_0 ),\n .\\q_entry_r_reg[1]_0 (\\q_entry_r_reg[1] ),\n .\\q_entry_r_reg[1]_1 (\\q_entry_r_reg[1]_0 ),\n .\\q_entry_r_reg[1]_2 (\\q_entry_r_reg[1]_1 ),\n .\\q_entry_r_reg[1]_3 (\\q_entry_r_reg[1]_2 ),\n .\\q_entry_r_reg[1]_4 (\\q_entry_r_reg[1]_3 ),\n .\\q_entry_r_reg[1]_5 (\\q_entry_r_reg[1]_4 ),\n .q_has_priority(q_has_priority),\n .q_has_priority_r_reg_0(q_has_priority_r_reg_0),\n .q_has_rd(q_has_rd),\n .q_has_rd_r_reg_0(q_has_rd_r_reg),\n .\\ras_timer_r_reg[0] (bank_queue0_n_23),\n .\\ras_timer_r_reg[0]_0 (\\ras_timer_r_reg[0]_0 ),\n .\\ras_timer_r_reg[0]_1 (\\ras_timer_r_reg[0]_3 ),\n .\\ras_timer_r_reg[1] (\\ras_timer_r_reg[0] ),\n .\\ras_timer_r_reg[1]_0 (\\ras_timer_r_reg[1]_0 ),\n .\\ras_timer_r_reg[1]_1 (\\ras_timer_r_reg[1]_1 ),\n .\\ras_timer_r_reg[2] (ras_timer_passed_ns),\n .\\ras_timer_r_reg[2]_0 (\\ras_timer_r_reg[2]_0 ),\n .\\ras_timer_r_reg[2]_1 (\\ras_timer_r_reg[2]_1 ),\n .\\ras_timer_r_reg[2]_2 (\\ras_timer_r_reg[2]_2 ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ),\n .rb_hit_busy_r_reg(head_r_lcl_reg_0),\n .rb_hit_busy_r_reg_0(head_r_lcl_reg_1),\n .rb_hit_busy_r_reg_1(rb_hit_busy_r_reg_2),\n .rd_wr_r_lcl_reg(rd_wr_r_lcl_reg),\n .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg_0),\n .rd_wr_r_lcl_reg_1(\\rd_this_rank_r_reg[0] ),\n .rd_wr_r_lcl_reg_2(rd_wr_r_lcl_reg_1),\n .rd_wr_r_lcl_reg_3(rd_wr_r_lcl_reg_2),\n .\\req_bank_r_lcl_reg[0] (\\req_bank_r_lcl_reg[0] ),\n .req_bank_rdy_ns(req_bank_rdy_ns),\n .\\req_data_buf_addr_r_reg[4] (E),\n .req_priority_r(req_priority_r),\n .req_wr_r_lcl_reg(req_wr_r_lcl_reg),\n .req_wr_r_lcl_reg_0(req_wr_r_lcl_reg_0),\n .req_wr_r_lcl_reg_1(req_wr_r_lcl_reg_1),\n .req_wr_r_lcl_reg_2(bm_end_r1_reg),\n .rnk_config_valid_r_lcl_reg(rnk_config_valid_r_lcl_reg),\n .\\rp_timer.rp_timer_r_reg[1] (\\rp_timer.rp_timer_r_reg[1]_0 ),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .\\rtw_timer.rtw_cnt_r_reg[1] (\\rtw_timer.rtw_cnt_r_reg[1] ),\n .tail_r(tail_r),\n .use_addr(use_addr),\n .wait_for_maint_r(wait_for_maint_r),\n .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg),\n .wait_for_maint_r_lcl_reg_1(wait_for_maint_r_lcl_reg_0),\n .\\wtr_timer.wtr_cnt_r_reg[1] (\\wtr_timer.wtr_cnt_r_reg[1] ));\n ddr3_if_mig_7series_v4_0_bank_state bank_state0\n (.CLK(CLK),\n .D(ras_timer_passed_ns),\n .SR(SR),\n .accept_r_reg(accept_r_reg_0),\n .act_this_rank_r(act_this_rank_r),\n .\\act_this_rank_r_reg[0]_0 (\\act_this_rank_r_reg[0] ),\n .act_wait_ns(act_wait_ns),\n .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg),\n .auto_pre_r_lcl_reg_0(\\rp_timer.rp_timer_r_reg[1]_0 ),\n .bm_end_r1(bm_end_r1),\n .bm_end_r1_reg_0(bm_end_r1_reg_3),\n .demand_priority_r_reg_0(demand_priority_r_reg),\n .demand_priority_r_reg_1(demand_priority_r_reg_0),\n .demanded_prior_r_reg_0(demanded_prior_r_reg),\n .demanded_prior_r_reg_1(demanded_prior_r_reg_0),\n .demanded_prior_r_reg_2(demanded_prior_r_reg_1),\n .demanded_prior_r_reg_3(demanded_prior_r_reg_2),\n .\\grant_r_reg[0] (\\grant_r_reg[0] ),\n .\\grant_r_reg[0]_0 (\\grant_r_reg[0]_0 ),\n .\\grant_r_reg[2] (\\grant_r_reg[2]_0 ),\n .granted_col_r_reg(granted_col_r_reg_0),\n .idle_r_lcl_reg(accept_internal_r_reg),\n .ofs_rdy_r(ofs_rdy_r),\n .ofs_rdy_r0(ofs_rdy_r0),\n .p_130_out(p_130_out),\n .pass_open_bank_ns(pass_open_bank_ns),\n .pass_open_bank_r_lcl_reg(act_wait_r_lcl_reg),\n .\\pre_4_1_1T_arb.granted_pre_r_reg (\\pre_4_1_1T_arb.granted_pre_r_reg ),\n .pre_bm_end_ns(pre_bm_end_ns),\n .pre_passing_open_bank_ns(pre_passing_open_bank_ns),\n .pre_wait_r(pre_wait_r),\n .q_has_rd(q_has_rd),\n .\\ras_timer_r_reg[0]_0 (\\ras_timer_r_reg[0] ),\n .\\ras_timer_r_reg[1]_0 (\\ras_timer_r_reg[1] ),\n .\\ras_timer_r_reg[2]_0 (\\ras_timer_r_reg[2] ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] (bank_queue0_n_23),\n .rd_this_rank_r(rd_this_rank_r),\n .rd_wr_r_lcl_reg(\\rd_this_rank_r_reg[0] ),\n .rd_wr_r_lcl_reg_0(bank_compare0_n_12),\n .req_bank_rdy_ns(req_bank_rdy_ns),\n .req_priority_r_reg(bank_queue0_n_27),\n .req_wr_r_lcl_reg(bm_end_r1_reg),\n .\\rnk_config_strobe_r_reg[0] (\\rnk_config_strobe_r_reg[0] ),\n .\\rp_timer.rp_timer_r_reg[1]_0 (\\rp_timer.rp_timer_r_reg[1] ),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22),\n .rtp_timer_ns1(rtp_timer_ns1),\n .start_wtp_timer0(start_wtp_timer0),\n .\\starve_limit_cntr_r_reg[2]_0 (\\starve_limit_cntr_r_reg[2] ),\n .tail_r(tail_r),\n .wr_this_rank_r(wr_this_rank_r));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_bank_cntrl\" *) \nmodule ddr3_if_mig_7series_v4_0_bank_cntrl__parameterized0\n (E,\n req_periodic_rd_r,\n \\rd_this_rank_r_reg[0] ,\n bm_end_r1_reg,\n rb_hit_busy_r,\n row_hit_r_0,\n bm_end_r1_0,\n row_cmd_wr,\n act_this_rank_r,\n req_bank_rdy_ns,\n demand_priority_r_reg,\n demanded_prior_r,\n ofs_rdy_r,\n wr_this_rank_r,\n rd_this_rank_r,\n act_wait_r_lcl_reg,\n bm_end_r1_reg_0,\n q_has_rd_3,\n q_has_priority_4,\n wait_for_maint_r_18,\n \\starve_limit_cntr_r_reg[2] ,\n tail_r_24,\n wait_for_maint_r_lcl_reg,\n \\rp_timer.rp_timer_r_reg[1] ,\n ordered_r,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] ,\n rb_hit_busy_r_reg,\n \\q_entry_r_reg[0] ,\n D,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ,\n \\grant_r_reg[1] ,\n \\ras_timer_r_reg[0] ,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ,\n \\ras_timer_r_reg[1] ,\n \\ras_timer_r_reg[2] ,\n req_bank_rdy_r_reg,\n \\ras_timer_r_reg[0]_0 ,\n pre_passing_open_bank_r_reg,\n pre_passing_open_bank_r_reg_0,\n \\q_entry_r_reg[1] ,\n \\q_entry_r_reg[1]_0 ,\n \\q_entry_r_reg[0]_0 ,\n head_r_lcl_reg,\n head_r_lcl_reg_0,\n \\q_entry_r_reg[1]_1 ,\n \\ras_timer_r_reg[0]_1 ,\n granted_pre_ns,\n \\grant_r_reg[2] ,\n auto_pre_r_lcl_reg,\n \\grant_r_reg[2]_0 ,\n \\grant_r_reg[1]_0 ,\n \\grant_r_reg[1]_1 ,\n \\cmd_pipe_plus.mc_address_reg[14] ,\n \\rnk_config_strobe_r_reg[0] ,\n \\grant_r_reg[3] ,\n \\cmd_pipe_plus.mc_address_reg[40] ,\n \\col_mux.col_data_buf_addr_r_reg[4] ,\n \\cmd_pipe_plus.mc_bank_reg[2] ,\n \\cmd_pipe_plus.mc_address_reg[24] ,\n CLK,\n periodic_rd_insert,\n hi_priority,\n SR,\n ofs_rdy_r0,\n q_has_rd_r_reg,\n q_has_priority_r_reg,\n \\maintenance_request.maint_req_r_lcl_reg ,\n wait_for_maint_r_lcl_reg_0,\n idle_r_lcl_reg,\n rstdiv0_sync_r1_reg_rep__0,\n head_r_lcl_reg_1,\n auto_pre_r_lcl_reg_0,\n ordered_r_lcl_reg,\n \\req_bank_r_lcl_reg[2] ,\n idle_r_lcl_reg_0,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ,\n rstdiv0_sync_r1_reg_rep__20,\n idle_r_lcl_reg_1,\n Q,\n idle_r_lcl_reg_2,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ,\n \\rtw_timer.rtw_cnt_r_reg[1] ,\n col_wait_r_reg,\n override_demand_r_reg,\n \\wtr_timer.wtr_cnt_r_reg[1] ,\n \\ras_timer_r_reg[1]_0 ,\n rd_wr_r_lcl_reg,\n \\ras_timer_r_reg[1]_1 ,\n bm_end_r1_reg_1,\n bm_end_r1_reg_2,\n bm_end_r1_reg_3,\n bm_end_r1_reg_4,\n \\ras_timer_r_reg[2]_0 ,\n \\ras_timer_r_reg[2]_1 ,\n req_wr_r_lcl_reg,\n req_wr_r_lcl_reg_0,\n rnk_config_valid_r_lcl_reg,\n \\grant_r_reg[3]_0 ,\n pass_open_bank_r_lcl_reg,\n req_wr_r_lcl_reg_1,\n accept_r_reg,\n \\app_cmd_r2_reg[1] ,\n \\app_cmd_r1_reg[0] ,\n periodic_rd_ack_r_lcl_reg,\n periodic_rd_cntr_r_reg,\n periodic_rd_r,\n periodic_rd_ack_r_lcl_reg_0,\n use_addr,\n accept_internal_r_reg,\n pre_bm_end_r_reg,\n idle_r_lcl_reg_3,\n idle_r_lcl_reg_4,\n idle_r_lcl_reg_5,\n periodic_rd_ack_r_lcl_reg_1,\n periodic_rd_ack_r_lcl_reg_2,\n \\grant_r_reg[1]_2 ,\n bm_end_r1_reg_5,\n rb_hit_busy_r_reg_0,\n rb_hit_busy_r_reg_1,\n accept_r_reg_0,\n pre_passing_open_bank_r_reg_1,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ,\n pre_passing_open_bank_r_reg_2,\n pre_bm_end_r_reg_0,\n pre_bm_end_r_reg_1,\n auto_pre_r_lcl_reg_1,\n \\grant_r_reg[1]_3 ,\n ras_timer_zero_r_reg,\n rd_wr_r_lcl_reg_0,\n req_wr_r,\n rstdiv0_sync_r1_reg_rep__22,\n maint_req_r,\n \\maint_controller.maint_wip_r_lcl_reg ,\n \\last_master_r_reg[0] ,\n \\app_addr_r1_reg[27] ,\n demanded_prior_r_reg,\n demand_priority_r_reg_0,\n demanded_prior_r_reg_0,\n act_wait_r_lcl_reg_0,\n \\req_row_r_lcl_reg[10] ,\n granted_col_r_reg,\n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ,\n \\app_addr_r1_reg[12] ,\n \\app_addr_r1_reg[9] ,\n pass_open_bank_r_lcl_reg_0,\n rstdiv0_sync_r1_reg_rep__21,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ,\n q_entry_ns,\n idle_r_lcl_reg_6,\n ordered_r_lcl_reg_0,\n ordered_r_lcl_reg_1);\n output [0:0]E;\n output [0:0]req_periodic_rd_r;\n output \\rd_this_rank_r_reg[0] ;\n output bm_end_r1_reg;\n output [0:0]rb_hit_busy_r;\n output row_hit_r_0;\n output bm_end_r1_0;\n output [0:0]row_cmd_wr;\n output [0:0]act_this_rank_r;\n output req_bank_rdy_ns;\n output demand_priority_r_reg;\n output demanded_prior_r;\n output ofs_rdy_r;\n output [0:0]wr_this_rank_r;\n output [0:0]rd_this_rank_r;\n output act_wait_r_lcl_reg;\n output bm_end_r1_reg_0;\n output q_has_rd_3;\n output q_has_priority_4;\n output wait_for_maint_r_18;\n output \\starve_limit_cntr_r_reg[2] ;\n output tail_r_24;\n output wait_for_maint_r_lcl_reg;\n output \\rp_timer.rp_timer_r_reg[1] ;\n output [0:0]ordered_r;\n output [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] ;\n output rb_hit_busy_r_reg;\n output \\q_entry_r_reg[0] ;\n output [0:0]D;\n output [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;\n output \\grant_r_reg[1] ;\n output \\ras_timer_r_reg[0] ;\n output [2:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;\n output \\ras_timer_r_reg[1] ;\n output \\ras_timer_r_reg[2] ;\n output req_bank_rdy_r_reg;\n output \\ras_timer_r_reg[0]_0 ;\n output pre_passing_open_bank_r_reg;\n output pre_passing_open_bank_r_reg_0;\n output \\q_entry_r_reg[1] ;\n output \\q_entry_r_reg[1]_0 ;\n output \\q_entry_r_reg[0]_0 ;\n output head_r_lcl_reg;\n output head_r_lcl_reg_0;\n output \\q_entry_r_reg[1]_1 ;\n output \\ras_timer_r_reg[0]_1 ;\n output granted_pre_ns;\n output \\grant_r_reg[2] ;\n output auto_pre_r_lcl_reg;\n output \\grant_r_reg[2]_0 ;\n output \\grant_r_reg[1]_0 ;\n output \\grant_r_reg[1]_1 ;\n output [14:0]\\cmd_pipe_plus.mc_address_reg[14] ;\n output \\rnk_config_strobe_r_reg[0] ;\n output \\grant_r_reg[3] ;\n output \\cmd_pipe_plus.mc_address_reg[40] ;\n output [4:0]\\col_mux.col_data_buf_addr_r_reg[4] ;\n output [2:0]\\cmd_pipe_plus.mc_bank_reg[2] ;\n output [6:0]\\cmd_pipe_plus.mc_address_reg[24] ;\n input CLK;\n input periodic_rd_insert;\n input hi_priority;\n input [0:0]SR;\n input ofs_rdy_r0;\n input q_has_rd_r_reg;\n input q_has_priority_r_reg;\n input \\maintenance_request.maint_req_r_lcl_reg ;\n input wait_for_maint_r_lcl_reg_0;\n input idle_r_lcl_reg;\n input rstdiv0_sync_r1_reg_rep__0;\n input head_r_lcl_reg_1;\n input auto_pre_r_lcl_reg_0;\n input ordered_r_lcl_reg;\n input \\req_bank_r_lcl_reg[2] ;\n input idle_r_lcl_reg_0;\n input [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ;\n input rstdiv0_sync_r1_reg_rep__20;\n input idle_r_lcl_reg_1;\n input [0:0]Q;\n input idle_r_lcl_reg_2;\n input [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;\n input \\rtw_timer.rtw_cnt_r_reg[1] ;\n input col_wait_r_reg;\n input override_demand_r_reg;\n input \\wtr_timer.wtr_cnt_r_reg[1] ;\n input \\ras_timer_r_reg[1]_0 ;\n input rd_wr_r_lcl_reg;\n input \\ras_timer_r_reg[1]_1 ;\n input bm_end_r1_reg_1;\n input bm_end_r1_reg_2;\n input bm_end_r1_reg_3;\n input bm_end_r1_reg_4;\n input \\ras_timer_r_reg[2]_0 ;\n input \\ras_timer_r_reg[2]_1 ;\n input req_wr_r_lcl_reg;\n input req_wr_r_lcl_reg_0;\n input rnk_config_valid_r_lcl_reg;\n input [2:0]\\grant_r_reg[3]_0 ;\n input pass_open_bank_r_lcl_reg;\n input req_wr_r_lcl_reg_1;\n input accept_r_reg;\n input [0:0]\\app_cmd_r2_reg[1] ;\n input \\app_cmd_r1_reg[0] ;\n input periodic_rd_ack_r_lcl_reg;\n input periodic_rd_cntr_r_reg;\n input periodic_rd_r;\n input periodic_rd_ack_r_lcl_reg_0;\n input use_addr;\n input accept_internal_r_reg;\n input pre_bm_end_r_reg;\n input [0:0]idle_r_lcl_reg_3;\n input [0:0]idle_r_lcl_reg_4;\n input [0:0]idle_r_lcl_reg_5;\n input periodic_rd_ack_r_lcl_reg_1;\n input periodic_rd_ack_r_lcl_reg_2;\n input [0:0]\\grant_r_reg[1]_2 ;\n input bm_end_r1_reg_5;\n input rb_hit_busy_r_reg_0;\n input rb_hit_busy_r_reg_1;\n input accept_r_reg_0;\n input pre_passing_open_bank_r_reg_1;\n input \\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;\n input pre_passing_open_bank_r_reg_2;\n input pre_bm_end_r_reg_0;\n input pre_bm_end_r_reg_1;\n input auto_pre_r_lcl_reg_1;\n input [1:0]\\grant_r_reg[1]_3 ;\n input ras_timer_zero_r_reg;\n input rd_wr_r_lcl_reg_0;\n input [0:0]req_wr_r;\n input rstdiv0_sync_r1_reg_rep__22;\n input maint_req_r;\n input \\maint_controller.maint_wip_r_lcl_reg ;\n input \\last_master_r_reg[0] ;\n input [14:0]\\app_addr_r1_reg[27] ;\n input demanded_prior_r_reg;\n input demand_priority_r_reg_0;\n input demanded_prior_r_reg_0;\n input [0:0]act_wait_r_lcl_reg_0;\n input [0:0]\\req_row_r_lcl_reg[10] ;\n input granted_col_r_reg;\n input [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n input [2:0]\\app_addr_r1_reg[12] ;\n input [6:0]\\app_addr_r1_reg[9] ;\n input pass_open_bank_r_lcl_reg_0;\n input rstdiv0_sync_r1_reg_rep__21;\n input [2:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ;\n input [0:0]q_entry_ns;\n input idle_r_lcl_reg_6;\n input ordered_r_lcl_reg_0;\n input ordered_r_lcl_reg_1;\n\n wire CLK;\n wire [0:0]D;\n wire [0:0]E;\n wire [0:0]Q;\n wire [0:0]SR;\n wire accept_internal_r_reg;\n wire accept_r_reg;\n wire accept_r_reg_0;\n wire [0:0]act_this_rank_r;\n wire act_wait_ns;\n wire act_wait_r_lcl_reg;\n wire [0:0]act_wait_r_lcl_reg_0;\n wire [2:0]\\app_addr_r1_reg[12] ;\n wire [14:0]\\app_addr_r1_reg[27] ;\n wire [6:0]\\app_addr_r1_reg[9] ;\n wire \\app_cmd_r1_reg[0] ;\n wire [0:0]\\app_cmd_r2_reg[1] ;\n wire auto_pre_r_lcl_reg;\n wire auto_pre_r_lcl_reg_0;\n wire auto_pre_r_lcl_reg_1;\n wire bank_compare0_n_11;\n wire bank_queue0_n_19;\n wire bank_queue0_n_23;\n wire bm_end_r1_0;\n wire bm_end_r1_reg;\n wire bm_end_r1_reg_0;\n wire bm_end_r1_reg_1;\n wire bm_end_r1_reg_2;\n wire bm_end_r1_reg_3;\n wire bm_end_r1_reg_4;\n wire bm_end_r1_reg_5;\n wire [14:0]\\cmd_pipe_plus.mc_address_reg[14] ;\n wire [6:0]\\cmd_pipe_plus.mc_address_reg[24] ;\n wire \\cmd_pipe_plus.mc_address_reg[40] ;\n wire [2:0]\\cmd_pipe_plus.mc_bank_reg[2] ;\n wire [4:0]\\col_mux.col_data_buf_addr_r_reg[4] ;\n wire col_wait_r_reg;\n wire demand_priority_r_reg;\n wire demand_priority_r_reg_0;\n wire demanded_prior_r;\n wire demanded_prior_r_reg;\n wire demanded_prior_r_reg_0;\n wire \\grant_r_reg[1] ;\n wire \\grant_r_reg[1]_0 ;\n wire \\grant_r_reg[1]_1 ;\n wire [0:0]\\grant_r_reg[1]_2 ;\n wire [1:0]\\grant_r_reg[1]_3 ;\n wire \\grant_r_reg[2] ;\n wire \\grant_r_reg[2]_0 ;\n wire \\grant_r_reg[3] ;\n wire [2:0]\\grant_r_reg[3]_0 ;\n wire granted_col_r_reg;\n wire granted_pre_ns;\n wire head_r_lcl_reg;\n wire head_r_lcl_reg_0;\n wire head_r_lcl_reg_1;\n wire hi_priority;\n wire [1:1]idle_ns;\n wire idle_r_lcl_reg;\n wire idle_r_lcl_reg_0;\n wire idle_r_lcl_reg_1;\n wire idle_r_lcl_reg_2;\n wire [0:0]idle_r_lcl_reg_3;\n wire [0:0]idle_r_lcl_reg_4;\n wire [0:0]idle_r_lcl_reg_5;\n wire idle_r_lcl_reg_6;\n wire \\last_master_r_reg[0] ;\n wire \\maint_controller.maint_wip_r_lcl_reg ;\n wire maint_req_r;\n wire \\maintenance_request.maint_req_r_lcl_reg ;\n wire [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n wire ofs_rdy_r;\n wire ofs_rdy_r0;\n wire [1:0]order_q_r;\n wire [0:0]ordered_r;\n wire ordered_r_lcl_reg;\n wire ordered_r_lcl_reg_0;\n wire ordered_r_lcl_reg_1;\n wire override_demand_r_reg;\n wire p_106_out;\n wire p_91_out;\n wire pass_open_bank_ns;\n wire pass_open_bank_r_lcl_reg;\n wire pass_open_bank_r_lcl_reg_0;\n wire periodic_rd_ack_r_lcl_reg;\n wire periodic_rd_ack_r_lcl_reg_0;\n wire periodic_rd_ack_r_lcl_reg_1;\n wire periodic_rd_ack_r_lcl_reg_2;\n wire periodic_rd_cntr_r_reg;\n wire periodic_rd_insert;\n wire periodic_rd_r;\n wire pre_bm_end_ns;\n wire pre_bm_end_r_reg;\n wire pre_bm_end_r_reg_0;\n wire pre_bm_end_r_reg_1;\n wire pre_passing_open_bank_ns;\n wire pre_passing_open_bank_r_reg;\n wire pre_passing_open_bank_r_reg_0;\n wire pre_passing_open_bank_r_reg_1;\n wire pre_passing_open_bank_r_reg_2;\n wire pre_wait_r;\n wire [0:0]q_entry_ns;\n wire \\q_entry_r_reg[0] ;\n wire \\q_entry_r_reg[0]_0 ;\n wire \\q_entry_r_reg[1] ;\n wire \\q_entry_r_reg[1]_0 ;\n wire \\q_entry_r_reg[1]_1 ;\n wire q_has_priority_4;\n wire q_has_priority_r_reg;\n wire q_has_rd_3;\n wire q_has_rd_r_reg;\n wire [2:0]ras_timer_passed_ns;\n wire \\ras_timer_r_reg[0] ;\n wire \\ras_timer_r_reg[0]_0 ;\n wire \\ras_timer_r_reg[0]_1 ;\n wire \\ras_timer_r_reg[1] ;\n wire \\ras_timer_r_reg[1]_0 ;\n wire \\ras_timer_r_reg[1]_1 ;\n wire \\ras_timer_r_reg[2] ;\n wire \\ras_timer_r_reg[2]_0 ;\n wire \\ras_timer_r_reg[2]_1 ;\n wire ras_timer_zero_r;\n wire ras_timer_zero_r_reg;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ;\n wire [2:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;\n wire \\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;\n wire [2:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;\n wire [0:0]rb_hit_busy_r;\n wire rb_hit_busy_r_reg;\n wire rb_hit_busy_r_reg_0;\n wire rb_hit_busy_r_reg_1;\n wire [0:0]rd_this_rank_r;\n wire \\rd_this_rank_r_reg[0] ;\n wire rd_wr_r_lcl_reg;\n wire rd_wr_r_lcl_reg_0;\n wire \\req_bank_r_lcl_reg[2] ;\n wire req_bank_rdy_ns;\n wire req_bank_rdy_r_reg;\n wire [0:0]req_periodic_rd_r;\n wire req_priority_r;\n wire [0:0]\\req_row_r_lcl_reg[10] ;\n wire [0:0]req_wr_r;\n wire req_wr_r_lcl_reg;\n wire req_wr_r_lcl_reg_0;\n wire req_wr_r_lcl_reg_1;\n wire \\rnk_config_strobe_r_reg[0] ;\n wire rnk_config_valid_r_lcl_reg;\n wire [0:0]row_cmd_wr;\n wire row_hit_r_0;\n wire \\rp_timer.rp_timer_r_reg[1] ;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire rstdiv0_sync_r1_reg_rep__22;\n wire \\rtw_timer.rtw_cnt_r_reg[1] ;\n wire start_wtp_timer0;\n wire \\starve_limit_cntr_r_reg[2] ;\n wire tail_r_24;\n wire use_addr;\n wire wait_for_maint_r_18;\n wire wait_for_maint_r_lcl_reg;\n wire wait_for_maint_r_lcl_reg_0;\n wire [0:0]wr_this_rank_r;\n wire \\wtr_timer.wtr_cnt_r_reg[1] ;\n\n ddr3_if_mig_7series_v4_0_bank_compare_1 bank_compare0\n (.CLK(CLK),\n .E(idle_ns),\n .accept_r_reg(accept_r_reg),\n .act_wait_r_lcl_reg(row_cmd_wr),\n .act_wait_r_lcl_reg_0(act_wait_r_lcl_reg_0),\n .\\app_addr_r1_reg[12] (\\app_addr_r1_reg[12] ),\n .\\app_addr_r1_reg[27] (\\app_addr_r1_reg[27] ),\n .\\app_addr_r1_reg[9] (\\app_addr_r1_reg[9] ),\n .\\app_cmd_r1_reg[0] (\\app_cmd_r1_reg[0] ),\n .\\app_cmd_r2_reg[1] (\\app_cmd_r2_reg[1] ),\n .bm_end_r1_reg(bm_end_r1_reg),\n .\\cmd_pipe_plus.mc_address_reg[14] (\\cmd_pipe_plus.mc_address_reg[14] ),\n .\\cmd_pipe_plus.mc_address_reg[24] (\\cmd_pipe_plus.mc_address_reg[24] ),\n .\\cmd_pipe_plus.mc_address_reg[40] (\\cmd_pipe_plus.mc_address_reg[40] ),\n .\\cmd_pipe_plus.mc_bank_reg[2] (\\cmd_pipe_plus.mc_bank_reg[2] ),\n .\\col_mux.col_data_buf_addr_r_reg[4] (\\col_mux.col_data_buf_addr_r_reg[4] ),\n .col_wait_r_reg(col_wait_r_reg),\n .\\grant_r_reg[1] (\\grant_r_reg[1] ),\n .\\grant_r_reg[1]_0 (\\grant_r_reg[3]_0 [1:0]),\n .\\grant_r_reg[1]_1 (\\grant_r_reg[1]_3 ),\n .head_r_lcl_reg(head_r_lcl_reg),\n .hi_priority(hi_priority),\n .idle_r_lcl_reg(rb_hit_busy_r_reg),\n .idle_r_lcl_reg_0(E),\n .\\maint_controller.maint_wip_r_lcl_reg (\\maint_controller.maint_wip_r_lcl_reg ),\n .maint_req_r(maint_req_r),\n .\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),\n .order_q_r(order_q_r),\n .override_demand_r_reg(override_demand_r_reg),\n .p_106_out(p_106_out),\n .p_91_out(p_91_out),\n .pass_open_bank_ns(pass_open_bank_ns),\n .pass_open_bank_r_lcl_reg(act_wait_r_lcl_reg),\n .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg),\n .periodic_rd_ack_r_lcl_reg_0(periodic_rd_ack_r_lcl_reg_0),\n .periodic_rd_cntr_r_reg(periodic_rd_cntr_r_reg),\n .periodic_rd_insert(periodic_rd_insert),\n .periodic_rd_r(periodic_rd_r),\n .pre_bm_end_r_reg(pre_bm_end_r_reg),\n .pre_bm_end_r_reg_0(bm_end_r1_reg_0),\n .pre_wait_r(pre_wait_r),\n .ras_timer_zero_r_reg(bank_compare0_n_11),\n .rb_hit_busy_r(rb_hit_busy_r),\n .\\rd_this_rank_r_reg[0] (\\rd_this_rank_r_reg[0] ),\n .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg_0),\n .req_bank_rdy_r_reg(req_bank_rdy_r_reg),\n .req_periodic_rd_r(req_periodic_rd_r),\n .req_priority_r(req_priority_r),\n .\\req_row_r_lcl_reg[10]_0 (\\req_row_r_lcl_reg[10] ),\n .req_wr_r(req_wr_r),\n .req_wr_r_lcl_reg_0(req_wr_r_lcl_reg_0),\n .req_wr_r_lcl_reg_1(req_wr_r_lcl_reg_1),\n .rnk_config_valid_r_lcl_reg(rnk_config_valid_r_lcl_reg),\n .row_hit_r_0(row_hit_r_0),\n .\\rtw_timer.rtw_cnt_r_reg[1] (\\rtw_timer.rtw_cnt_r_reg[1] ),\n .start_wtp_timer0(start_wtp_timer0),\n .tail_r_24(tail_r_24),\n .wait_for_maint_r_18(wait_for_maint_r_18),\n .\\wtr_timer.wtr_cnt_r_reg[1] (\\wtr_timer.wtr_cnt_r_reg[1] ));\n ddr3_if_mig_7series_v4_0_bank_queue__parameterized0 bank_queue0\n (.CLK(CLK),\n .D(D),\n .E(idle_ns),\n .Q(Q),\n .SR(SR),\n .accept_internal_r_reg(accept_internal_r_reg),\n .accept_r_reg(accept_r_reg_0),\n .act_wait_ns(act_wait_ns),\n .act_wait_r_lcl_reg(act_wait_r_lcl_reg),\n .act_wait_r_lcl_reg_0(row_cmd_wr),\n .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_0),\n .bm_end_r1_reg(bm_end_r1_reg_0),\n .bm_end_r1_reg_0(\\ras_timer_r_reg[1] ),\n .bm_end_r1_reg_1(bm_end_r1_reg_1),\n .bm_end_r1_reg_2(bm_end_r1_reg_2),\n .bm_end_r1_reg_3(bm_end_r1_reg_3),\n .bm_end_r1_reg_4(bm_end_r1_reg_4),\n .bm_end_r1_reg_5(bm_end_r1_reg_5),\n .col_wait_r_reg(\\starve_limit_cntr_r_reg[2] ),\n .demand_priority_r_reg(bank_queue0_n_23),\n .\\grant_r_reg[1] (\\grant_r_reg[1]_1 ),\n .\\grant_r_reg[1]_0 (\\grant_r_reg[3]_0 [1]),\n .\\grant_r_reg[1]_1 (\\grant_r_reg[1]_2 ),\n .head_r_lcl_reg_0(head_r_lcl_reg_0),\n .head_r_lcl_reg_1(head_r_lcl_reg_1),\n .idle_r_lcl_reg_0(idle_r_lcl_reg),\n .idle_r_lcl_reg_1(idle_r_lcl_reg_0),\n .idle_r_lcl_reg_2(idle_r_lcl_reg_1),\n .idle_r_lcl_reg_3(idle_r_lcl_reg_2),\n .idle_r_lcl_reg_4(idle_r_lcl_reg_3),\n .idle_r_lcl_reg_5(idle_r_lcl_reg_4),\n .idle_r_lcl_reg_6(idle_r_lcl_reg_5),\n .idle_r_lcl_reg_7(idle_r_lcl_reg_6),\n .\\maintenance_request.maint_req_r_lcl_reg (\\maintenance_request.maint_req_r_lcl_reg ),\n .order_q_r(order_q_r),\n .ordered_r(ordered_r),\n .ordered_r_lcl_reg_0(ordered_r_lcl_reg),\n .ordered_r_lcl_reg_1(ordered_r_lcl_reg_0),\n .ordered_r_lcl_reg_2(ordered_r_lcl_reg_1),\n .p_106_out(p_106_out),\n .pass_open_bank_ns(pass_open_bank_ns),\n .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg),\n .periodic_rd_ack_r_lcl_reg_0(periodic_rd_ack_r_lcl_reg_1),\n .periodic_rd_ack_r_lcl_reg_1(periodic_rd_ack_r_lcl_reg_2),\n .pre_bm_end_ns(pre_bm_end_ns),\n .pre_bm_end_r_reg_0(pre_bm_end_r_reg),\n .pre_bm_end_r_reg_1(pre_bm_end_r_reg_0),\n .pre_bm_end_r_reg_2(pre_bm_end_r_reg_1),\n .pre_passing_open_bank_ns(pre_passing_open_bank_ns),\n .pre_passing_open_bank_r_reg_0(pre_passing_open_bank_r_reg_1),\n .pre_passing_open_bank_r_reg_1(pre_passing_open_bank_r_reg_2),\n .q_entry_ns(q_entry_ns),\n .\\q_entry_r_reg[0]_0 (\\q_entry_r_reg[0] ),\n .\\q_entry_r_reg[0]_1 (\\q_entry_r_reg[0]_0 ),\n .\\q_entry_r_reg[1]_0 (\\q_entry_r_reg[1] ),\n .\\q_entry_r_reg[1]_1 (\\q_entry_r_reg[1]_0 ),\n .\\q_entry_r_reg[1]_2 (\\q_entry_r_reg[1]_1 ),\n .q_has_priority_4(q_has_priority_4),\n .q_has_priority_r_reg_0(q_has_priority_r_reg),\n .q_has_rd_3(q_has_rd_3),\n .q_has_rd_r_reg_0(q_has_rd_r_reg),\n .\\ras_timer_r_reg[0] (bank_queue0_n_19),\n .\\ras_timer_r_reg[0]_0 (\\ras_timer_r_reg[0]_0 ),\n .\\ras_timer_r_reg[0]_1 (\\ras_timer_r_reg[0]_1 ),\n .\\ras_timer_r_reg[1] (\\ras_timer_r_reg[0] ),\n .\\ras_timer_r_reg[1]_0 (\\ras_timer_r_reg[1]_0 ),\n .\\ras_timer_r_reg[1]_1 (\\ras_timer_r_reg[1]_1 ),\n .\\ras_timer_r_reg[2] (ras_timer_passed_ns),\n .\\ras_timer_r_reg[2]_0 (\\ras_timer_r_reg[2] ),\n .\\ras_timer_r_reg[2]_1 (\\ras_timer_r_reg[2]_0 ),\n .\\ras_timer_r_reg[2]_2 (\\ras_timer_r_reg[2]_1 ),\n .ras_timer_zero_r(ras_timer_zero_r),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),\n .rb_hit_busy_r_reg(rb_hit_busy_r_reg),\n .rb_hit_busy_r_reg_0(rb_hit_busy_r_reg_0),\n .rb_hit_busy_r_reg_1(rb_hit_busy_r_reg_1),\n .rd_wr_r_lcl_reg(rd_wr_r_lcl_reg),\n .rd_wr_r_lcl_reg_0(\\rd_this_rank_r_reg[0] ),\n .\\req_bank_r_lcl_reg[2] (\\req_bank_r_lcl_reg[2] ),\n .req_bank_rdy_ns(req_bank_rdy_ns),\n .\\req_data_buf_addr_r_reg[4] (E),\n .req_priority_r(req_priority_r),\n .req_wr_r_lcl_reg(req_wr_r_lcl_reg),\n .req_wr_r_lcl_reg_0(bm_end_r1_reg),\n .req_wr_r_lcl_reg_1(req_wr_r_lcl_reg_1),\n .\\rp_timer.rp_timer_r_reg[1] (\\rp_timer.rp_timer_r_reg[1] ),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .tail_r_24(tail_r_24),\n .use_addr(use_addr),\n .wait_for_maint_r_18(wait_for_maint_r_18),\n .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg),\n .wait_for_maint_r_lcl_reg_1(wait_for_maint_r_lcl_reg_0));\n ddr3_if_mig_7series_v4_0_bank_state__parameterized0 bank_state0\n (.CLK(CLK),\n .D(ras_timer_passed_ns),\n .SR(SR),\n .accept_r_reg(accept_r_reg),\n .act_this_rank_r(act_this_rank_r),\n .\\act_this_rank_r_reg[0]_0 (row_cmd_wr),\n .act_wait_ns(act_wait_ns),\n .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg),\n .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_1),\n .auto_pre_r_lcl_reg_1(\\rp_timer.rp_timer_r_reg[1] ),\n .bm_end_r1_0(bm_end_r1_0),\n .bm_end_r1_reg_0(bm_end_r1_reg_5),\n .demand_priority_r_reg_0(demand_priority_r_reg),\n .demand_priority_r_reg_1(demand_priority_r_reg_0),\n .demanded_prior_r_reg_0(demanded_prior_r),\n .demanded_prior_r_reg_1(demanded_prior_r_reg),\n .demanded_prior_r_reg_2(demanded_prior_r_reg_0),\n .\\grant_r_reg[1] (\\grant_r_reg[1]_0 ),\n .\\grant_r_reg[1]_0 (\\grant_r_reg[1]_3 [1]),\n .\\grant_r_reg[1]_1 (\\grant_r_reg[1]_2 ),\n .\\grant_r_reg[2] (\\grant_r_reg[2] ),\n .\\grant_r_reg[2]_0 (\\grant_r_reg[2]_0 ),\n .\\grant_r_reg[3] (\\grant_r_reg[3] ),\n .\\grant_r_reg[3]_0 (\\grant_r_reg[3]_0 [2:1]),\n .granted_col_r_reg(granted_col_r_reg),\n .granted_pre_ns(granted_pre_ns),\n .idle_r_lcl_reg(rb_hit_busy_r_reg),\n .\\last_master_r_reg[0] (\\last_master_r_reg[0] ),\n .ofs_rdy_r(ofs_rdy_r),\n .ofs_rdy_r0(ofs_rdy_r0),\n .p_91_out(p_91_out),\n .pass_open_bank_ns(pass_open_bank_ns),\n .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg),\n .pass_open_bank_r_lcl_reg_0(act_wait_r_lcl_reg),\n .pass_open_bank_r_lcl_reg_1(pass_open_bank_r_lcl_reg_0),\n .pre_bm_end_ns(pre_bm_end_ns),\n .pre_passing_open_bank_ns(pre_passing_open_bank_ns),\n .pre_passing_open_bank_r_reg(pre_passing_open_bank_r_reg),\n .pre_passing_open_bank_r_reg_0(pre_passing_open_bank_r_reg_0),\n .pre_wait_r(pre_wait_r),\n .q_has_rd_3(q_has_rd_3),\n .\\ras_timer_r_reg[0]_0 (\\ras_timer_r_reg[0] ),\n .\\ras_timer_r_reg[1]_0 (\\ras_timer_r_reg[1] ),\n .\\ras_timer_r_reg[2]_0 (\\ras_timer_r_reg[2] ),\n .ras_timer_zero_r(ras_timer_zero_r),\n .ras_timer_zero_r_reg_0(ras_timer_zero_r_reg),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] (bank_queue0_n_19),\n .rd_this_rank_r(rd_this_rank_r),\n .rd_wr_r_lcl_reg(\\rd_this_rank_r_reg[0] ),\n .rd_wr_r_lcl_reg_0(bank_compare0_n_11),\n .req_bank_rdy_ns(req_bank_rdy_ns),\n .req_priority_r_reg(bank_queue0_n_23),\n .req_wr_r_lcl_reg(bm_end_r1_reg),\n .\\rnk_config_strobe_r_reg[0] (\\rnk_config_strobe_r_reg[0] ),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22),\n .start_wtp_timer0(start_wtp_timer0),\n .\\starve_limit_cntr_r_reg[2]_0 (\\starve_limit_cntr_r_reg[2] ),\n .tail_r_24(tail_r_24),\n .wr_this_rank_r(wr_this_rank_r));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_bank_cntrl\" *) \nmodule ddr3_if_mig_7series_v4_0_bank_cntrl__parameterized1\n (E,\n req_periodic_rd_r,\n \\rd_this_rank_r_reg[0] ,\n bm_end_r1_reg,\n q_has_priority_r_reg,\n row_hit_r_5,\n \\ras_timer_r_reg[2] ,\n \\act_this_rank_r_reg[0] ,\n \\rp_timer.rp_timer_r_reg[1] ,\n act_this_rank_r,\n req_bank_rdy_ns,\n demand_priority_r_reg,\n demanded_prior_r_reg,\n override_demand_r,\n ofs_rdy_r,\n wr_this_rank_r,\n rd_this_rank_r,\n act_wait_r_lcl_reg,\n pre_bm_end_r_9,\n q_has_rd_10,\n q_has_priority_11,\n wait_for_maint_r_19,\n \\starve_limit_cntr_r_reg[2] ,\n tail_r_26,\n wait_for_maint_r_lcl_reg,\n \\rp_timer.rp_timer_r_reg[1]_0 ,\n ordered_r,\n D,\n rb_hit_busy_r_reg,\n \\q_entry_r_reg[1] ,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ,\n ofs_rdy_r0,\n ofs_rdy_r0_0,\n ofs_rdy_r0_1,\n \\grant_r_reg[2] ,\n \\ras_timer_r_reg[0] ,\n \\ras_timer_r_reg[1] ,\n \\ras_timer_r_reg[2]_0 ,\n \\order_q_r_reg[0] ,\n req_bank_rdy_r_reg,\n \\order_q_r_reg[1] ,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ,\n \\q_entry_r_reg[1]_0 ,\n \\q_entry_r_reg[1]_1 ,\n \\q_entry_r_reg[0] ,\n head_r_lcl_reg,\n \\q_entry_r_reg[1]_2 ,\n \\compute_tail.tail_r_lcl_reg ,\n \\ras_timer_r_reg[0]_0 ,\n \\grant_r_reg[1] ,\n \\grant_r_reg[3] ,\n \\ras_timer_r_reg[0]_1 ,\n granted_row_ns,\n granted_row_r_reg,\n auto_pre_r_lcl_reg,\n \\grant_r_reg[2]_0 ,\n \\cmd_pipe_plus.mc_address_reg[44] ,\n \\rnk_config_strobe_r_reg[0] ,\n \\cmd_pipe_plus.mc_address_reg[40] ,\n \\col_mux.col_data_buf_addr_r_reg[4] ,\n \\cmd_pipe_plus.mc_bank_reg[8] ,\n \\cmd_pipe_plus.mc_address_reg[24] ,\n CLK,\n periodic_rd_insert,\n hi_priority,\n override_demand_ns,\n SR,\n q_has_rd_r_reg,\n q_has_priority_r_reg_0,\n rstdiv0_sync_r1_reg_rep__0,\n of_ctl_full_v,\n phy_mc_ctl_full,\n \\maintenance_request.maint_req_r_lcl_reg ,\n wait_for_maint_r_lcl_reg_0,\n idle_r_lcl_reg,\n head_r_lcl_reg_0,\n auto_pre_r_lcl_reg_0,\n ordered_r_lcl_reg,\n \\req_bank_r_lcl_reg[2] ,\n idle_r_lcl_reg_0,\n Q,\n rstdiv0_sync_r1_reg_rep__20,\n idle_r_lcl_reg_1,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ,\n idle_r_lcl_reg_2,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 ,\n \\entry_cnt_reg[2] ,\n \\entry_cnt_reg[2]_0 ,\n rd_wr_r_lcl_reg,\n rd_wr_r_lcl_reg_0,\n rd_wr_r,\n \\rtw_timer.rtw_cnt_r_reg[1] ,\n \\wtr_timer.wtr_cnt_r_reg[1] ,\n override_demand_r_reg,\n col_wait_r_reg,\n bm_end_r1_reg_0,\n rstdiv0_sync_r1_reg_rep__21,\n \\grant_r_reg[3]_0 ,\n ordered_r_lcl_reg_0,\n rd_wr_r_lcl_reg_1,\n req_wr_r_lcl_reg,\n rnk_config_valid_r_lcl_reg,\n req_wr_r_lcl_reg_0,\n \\ras_timer_r_reg[1]_0 ,\n \\ras_timer_r_reg[1]_1 ,\n rd_wr_r_lcl_reg_2,\n bm_end_r1_reg_1,\n bm_end_r1_reg_2,\n bm_end_r1_reg_3,\n \\ras_timer_r_reg[2]_1 ,\n bm_end_r1_reg_4,\n \\ras_timer_r_reg[2]_2 ,\n \\grant_r_reg[2]_1 ,\n pre_passing_open_bank_r_reg,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ,\n pre_passing_open_bank_r_reg_0,\n idle_r_lcl_reg_3,\n rb_hit_busy_r_reg_0,\n rb_hit_busy_r_reg_1,\n periodic_rd_ack_r_lcl_reg,\n accept_r_reg,\n periodic_rd_ack_r_lcl_reg_0,\n pre_bm_end_r_reg,\n pre_bm_end_r_reg_0,\n pre_bm_end_r_reg_1,\n \\app_cmd_r2_reg[1] ,\n \\app_cmd_r1_reg[0] ,\n periodic_rd_ack_r_lcl_reg_1,\n periodic_rd_cntr_r_reg,\n periodic_rd_r,\n periodic_rd_ack_r_lcl_reg_2,\n use_addr,\n accept_internal_r_reg,\n req_wr_r_lcl_reg_1,\n rtp_timer_ns1_7,\n rb_hit_busy_r_reg_2,\n \\grant_r_reg[1]_0 ,\n ras_timer_zero_r_reg,\n \\grant_r_reg[3]_1 ,\n maint_req_r,\n \\maint_controller.maint_wip_r_lcl_reg ,\n \\grant_r_reg[3]_2 ,\n rstdiv0_sync_r1_reg_rep__22,\n \\app_addr_r1_reg[27] ,\n demand_priority_r,\n demanded_prior_r_reg_0,\n demanded_prior_r,\n \\req_row_r_lcl_reg[10] ,\n act_wait_r_lcl_reg_0,\n granted_col_r_reg,\n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ,\n \\app_addr_r1_reg[12] ,\n \\app_addr_r1_reg[9] ,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ,\n idle_r_lcl_reg_4,\n \\q_entry_r_reg[1]_3 ,\n idle_r_lcl_reg_5);\n output [0:0]E;\n output [0:0]req_periodic_rd_r;\n output \\rd_this_rank_r_reg[0] ;\n output bm_end_r1_reg;\n output q_has_priority_r_reg;\n output row_hit_r_5;\n output \\ras_timer_r_reg[2] ;\n output \\act_this_rank_r_reg[0] ;\n output \\rp_timer.rp_timer_r_reg[1] ;\n output [0:0]act_this_rank_r;\n output req_bank_rdy_ns;\n output demand_priority_r_reg;\n output demanded_prior_r_reg;\n output override_demand_r;\n output ofs_rdy_r;\n output [0:0]wr_this_rank_r;\n output [0:0]rd_this_rank_r;\n output act_wait_r_lcl_reg;\n output pre_bm_end_r_9;\n output q_has_rd_10;\n output q_has_priority_11;\n output wait_for_maint_r_19;\n output \\starve_limit_cntr_r_reg[2] ;\n output tail_r_26;\n output wait_for_maint_r_lcl_reg;\n output \\rp_timer.rp_timer_r_reg[1]_0 ;\n output [0:0]ordered_r;\n output [0:0]D;\n output rb_hit_busy_r_reg;\n output \\q_entry_r_reg[1] ;\n output [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ;\n output [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ;\n output ofs_rdy_r0;\n output ofs_rdy_r0_0;\n output ofs_rdy_r0_1;\n output \\grant_r_reg[2] ;\n output \\ras_timer_r_reg[0] ;\n output \\ras_timer_r_reg[1] ;\n output \\ras_timer_r_reg[2]_0 ;\n output \\order_q_r_reg[0] ;\n output req_bank_rdy_r_reg;\n output \\order_q_r_reg[1] ;\n output [2:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;\n output \\q_entry_r_reg[1]_0 ;\n output \\q_entry_r_reg[1]_1 ;\n output \\q_entry_r_reg[0] ;\n output head_r_lcl_reg;\n output \\q_entry_r_reg[1]_2 ;\n output \\compute_tail.tail_r_lcl_reg ;\n output \\ras_timer_r_reg[0]_0 ;\n output \\grant_r_reg[1] ;\n output \\grant_r_reg[3] ;\n output \\ras_timer_r_reg[0]_1 ;\n output granted_row_ns;\n output granted_row_r_reg;\n output auto_pre_r_lcl_reg;\n output \\grant_r_reg[2]_0 ;\n output [14:0]\\cmd_pipe_plus.mc_address_reg[44] ;\n output \\rnk_config_strobe_r_reg[0] ;\n output [0:0]\\cmd_pipe_plus.mc_address_reg[40] ;\n output [4:0]\\col_mux.col_data_buf_addr_r_reg[4] ;\n output [2:0]\\cmd_pipe_plus.mc_bank_reg[8] ;\n output [6:0]\\cmd_pipe_plus.mc_address_reg[24] ;\n input CLK;\n input periodic_rd_insert;\n input hi_priority;\n input override_demand_ns;\n input [0:0]SR;\n input q_has_rd_r_reg;\n input q_has_priority_r_reg_0;\n input rstdiv0_sync_r1_reg_rep__0;\n input [0:0]of_ctl_full_v;\n input phy_mc_ctl_full;\n input \\maintenance_request.maint_req_r_lcl_reg ;\n input wait_for_maint_r_lcl_reg_0;\n input idle_r_lcl_reg;\n input head_r_lcl_reg_0;\n input auto_pre_r_lcl_reg_0;\n input ordered_r_lcl_reg;\n input \\req_bank_r_lcl_reg[2] ;\n input idle_r_lcl_reg_0;\n input [0:0]Q;\n input rstdiv0_sync_r1_reg_rep__20;\n input idle_r_lcl_reg_1;\n input [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ;\n input idle_r_lcl_reg_2;\n input [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 ;\n input \\entry_cnt_reg[2] ;\n input \\entry_cnt_reg[2]_0 ;\n input rd_wr_r_lcl_reg;\n input rd_wr_r_lcl_reg_0;\n input [0:0]rd_wr_r;\n input \\rtw_timer.rtw_cnt_r_reg[1] ;\n input \\wtr_timer.wtr_cnt_r_reg[1] ;\n input override_demand_r_reg;\n input col_wait_r_reg;\n input bm_end_r1_reg_0;\n input rstdiv0_sync_r1_reg_rep__21;\n input [2:0]\\grant_r_reg[3]_0 ;\n input [2:0]ordered_r_lcl_reg_0;\n input rd_wr_r_lcl_reg_1;\n input req_wr_r_lcl_reg;\n input rnk_config_valid_r_lcl_reg;\n input req_wr_r_lcl_reg_0;\n input \\ras_timer_r_reg[1]_0 ;\n input \\ras_timer_r_reg[1]_1 ;\n input rd_wr_r_lcl_reg_2;\n input bm_end_r1_reg_1;\n input bm_end_r1_reg_2;\n input bm_end_r1_reg_3;\n input \\ras_timer_r_reg[2]_1 ;\n input bm_end_r1_reg_4;\n input \\ras_timer_r_reg[2]_2 ;\n input [0:0]\\grant_r_reg[2]_1 ;\n input pre_passing_open_bank_r_reg;\n input \\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;\n input pre_passing_open_bank_r_reg_0;\n input idle_r_lcl_reg_3;\n input rb_hit_busy_r_reg_0;\n input rb_hit_busy_r_reg_1;\n input periodic_rd_ack_r_lcl_reg;\n input accept_r_reg;\n input periodic_rd_ack_r_lcl_reg_0;\n input pre_bm_end_r_reg;\n input pre_bm_end_r_reg_0;\n input pre_bm_end_r_reg_1;\n input [0:0]\\app_cmd_r2_reg[1] ;\n input \\app_cmd_r1_reg[0] ;\n input periodic_rd_ack_r_lcl_reg_1;\n input periodic_rd_cntr_r_reg;\n input periodic_rd_r;\n input periodic_rd_ack_r_lcl_reg_2;\n input use_addr;\n input accept_internal_r_reg;\n input req_wr_r_lcl_reg_1;\n input rtp_timer_ns1_7;\n input rb_hit_busy_r_reg_2;\n input \\grant_r_reg[1]_0 ;\n input ras_timer_zero_r_reg;\n input \\grant_r_reg[3]_1 ;\n input maint_req_r;\n input \\maint_controller.maint_wip_r_lcl_reg ;\n input [1:0]\\grant_r_reg[3]_2 ;\n input rstdiv0_sync_r1_reg_rep__22;\n input [14:0]\\app_addr_r1_reg[27] ;\n input demand_priority_r;\n input demanded_prior_r_reg_0;\n input demanded_prior_r;\n input \\req_row_r_lcl_reg[10] ;\n input act_wait_r_lcl_reg_0;\n input granted_col_r_reg;\n input [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n input [2:0]\\app_addr_r1_reg[12] ;\n input [6:0]\\app_addr_r1_reg[9] ;\n input [2:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;\n input idle_r_lcl_reg_4;\n input \\q_entry_r_reg[1]_3 ;\n input idle_r_lcl_reg_5;\n\n wire CLK;\n wire [0:0]D;\n wire [0:0]E;\n wire [0:0]Q;\n wire [0:0]SR;\n wire accept_internal_r_reg;\n wire accept_r_reg;\n wire [0:0]act_this_rank_r;\n wire \\act_this_rank_r_reg[0] ;\n wire act_wait_ns;\n wire act_wait_r_lcl_reg;\n wire act_wait_r_lcl_reg_0;\n wire [2:0]\\app_addr_r1_reg[12] ;\n wire [14:0]\\app_addr_r1_reg[27] ;\n wire [6:0]\\app_addr_r1_reg[9] ;\n wire \\app_cmd_r1_reg[0] ;\n wire [0:0]\\app_cmd_r2_reg[1] ;\n wire auto_pre_r_lcl_reg;\n wire auto_pre_r_lcl_reg_0;\n wire bank_compare0_n_10;\n wire bank_compare0_n_8;\n wire bank_queue0_n_21;\n wire bm_end_r1_reg;\n wire bm_end_r1_reg_0;\n wire bm_end_r1_reg_1;\n wire bm_end_r1_reg_2;\n wire bm_end_r1_reg_3;\n wire bm_end_r1_reg_4;\n wire [6:0]\\cmd_pipe_plus.mc_address_reg[24] ;\n wire [0:0]\\cmd_pipe_plus.mc_address_reg[40] ;\n wire [14:0]\\cmd_pipe_plus.mc_address_reg[44] ;\n wire [2:0]\\cmd_pipe_plus.mc_bank_reg[8] ;\n wire [4:0]\\col_mux.col_data_buf_addr_r_reg[4] ;\n wire col_wait_r_reg;\n wire \\compute_tail.tail_r_lcl_reg ;\n wire demand_priority_r;\n wire demand_priority_r_reg;\n wire demanded_prior_r;\n wire demanded_prior_r_reg;\n wire demanded_prior_r_reg_0;\n wire \\entry_cnt_reg[2] ;\n wire \\entry_cnt_reg[2]_0 ;\n wire \\grant_r_reg[1] ;\n wire \\grant_r_reg[1]_0 ;\n wire \\grant_r_reg[2] ;\n wire \\grant_r_reg[2]_0 ;\n wire [0:0]\\grant_r_reg[2]_1 ;\n wire \\grant_r_reg[3] ;\n wire [2:0]\\grant_r_reg[3]_0 ;\n wire \\grant_r_reg[3]_1 ;\n wire [1:0]\\grant_r_reg[3]_2 ;\n wire granted_col_r_reg;\n wire granted_row_ns;\n wire granted_row_r_reg;\n wire head_r_lcl_reg;\n wire head_r_lcl_reg_0;\n wire hi_priority;\n wire [2:2]idle_ns;\n wire idle_r_lcl_reg;\n wire idle_r_lcl_reg_0;\n wire idle_r_lcl_reg_1;\n wire idle_r_lcl_reg_2;\n wire idle_r_lcl_reg_3;\n wire idle_r_lcl_reg_4;\n wire idle_r_lcl_reg_5;\n wire \\maint_controller.maint_wip_r_lcl_reg ;\n wire maint_req_r;\n wire \\maintenance_request.maint_req_r_lcl_reg ;\n wire [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n wire [0:0]of_ctl_full_v;\n wire ofs_rdy_r;\n wire ofs_rdy_r0;\n wire ofs_rdy_r0_0;\n wire ofs_rdy_r0_1;\n wire [1:0]order_q_r;\n wire \\order_q_r_reg[0] ;\n wire \\order_q_r_reg[1] ;\n wire [0:0]ordered_r;\n wire ordered_r_lcl_reg;\n wire [2:0]ordered_r_lcl_reg_0;\n wire override_demand_ns;\n wire override_demand_r;\n wire override_demand_r_reg;\n wire p_52_out;\n wire p_67_out;\n wire pass_open_bank_ns;\n wire periodic_rd_ack_r_lcl_reg;\n wire periodic_rd_ack_r_lcl_reg_0;\n wire periodic_rd_ack_r_lcl_reg_1;\n wire periodic_rd_ack_r_lcl_reg_2;\n wire periodic_rd_cntr_r_reg;\n wire periodic_rd_insert;\n wire periodic_rd_r;\n wire phy_mc_ctl_full;\n wire pre_bm_end_ns;\n wire pre_bm_end_r_9;\n wire pre_bm_end_r_reg;\n wire pre_bm_end_r_reg_0;\n wire pre_bm_end_r_reg_1;\n wire pre_passing_open_bank_ns;\n wire pre_passing_open_bank_r;\n wire pre_passing_open_bank_r_reg;\n wire pre_passing_open_bank_r_reg_0;\n wire pre_wait_r;\n wire \\q_entry_r_reg[0] ;\n wire \\q_entry_r_reg[1] ;\n wire \\q_entry_r_reg[1]_0 ;\n wire \\q_entry_r_reg[1]_1 ;\n wire \\q_entry_r_reg[1]_2 ;\n wire \\q_entry_r_reg[1]_3 ;\n wire q_has_priority_11;\n wire q_has_priority_r_reg;\n wire q_has_priority_r_reg_0;\n wire q_has_rd_10;\n wire q_has_rd_r_reg;\n wire [2:0]ras_timer_passed_ns;\n wire \\ras_timer_r_reg[0] ;\n wire \\ras_timer_r_reg[0]_0 ;\n wire \\ras_timer_r_reg[0]_1 ;\n wire \\ras_timer_r_reg[1] ;\n wire \\ras_timer_r_reg[1]_0 ;\n wire \\ras_timer_r_reg[1]_1 ;\n wire \\ras_timer_r_reg[2] ;\n wire \\ras_timer_r_reg[2]_0 ;\n wire \\ras_timer_r_reg[2]_1 ;\n wire \\ras_timer_r_reg[2]_2 ;\n wire ras_timer_zero_r_reg;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 ;\n wire \\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;\n wire [2:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;\n wire [2:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;\n wire rb_hit_busy_r_reg;\n wire rb_hit_busy_r_reg_0;\n wire rb_hit_busy_r_reg_1;\n wire rb_hit_busy_r_reg_2;\n wire [0:0]rd_this_rank_r;\n wire \\rd_this_rank_r_reg[0] ;\n wire [0:0]rd_wr_r;\n wire rd_wr_r_lcl_reg;\n wire rd_wr_r_lcl_reg_0;\n wire rd_wr_r_lcl_reg_1;\n wire rd_wr_r_lcl_reg_2;\n wire \\req_bank_r_lcl_reg[2] ;\n wire req_bank_rdy_ns;\n wire req_bank_rdy_r_reg;\n wire [0:0]req_periodic_rd_r;\n wire \\req_row_r_lcl_reg[10] ;\n wire req_wr_r_lcl_reg;\n wire req_wr_r_lcl_reg_0;\n wire req_wr_r_lcl_reg_1;\n wire \\rnk_config_strobe_r_reg[0] ;\n wire rnk_config_valid_r_lcl_reg;\n wire row_hit_r_5;\n wire \\rp_timer.rp_timer_r_reg[1] ;\n wire \\rp_timer.rp_timer_r_reg[1]_0 ;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire rstdiv0_sync_r1_reg_rep__22;\n wire rtp_timer_ns1_7;\n wire \\rtw_timer.rtw_cnt_r_reg[1] ;\n wire start_wtp_timer0;\n wire \\starve_limit_cntr_r_reg[2] ;\n wire tail_r_26;\n wire use_addr;\n wire wait_for_maint_r_19;\n wire wait_for_maint_r_lcl_reg;\n wire wait_for_maint_r_lcl_reg_0;\n wire [0:0]wr_this_rank_r;\n wire \\wtr_timer.wtr_cnt_r_reg[1] ;\n\n ddr3_if_mig_7series_v4_0_bank_compare_0 bank_compare0\n (.CLK(CLK),\n .E(idle_ns),\n .Q(Q),\n .act_wait_r_lcl_reg(act_wait_r_lcl_reg_0),\n .act_wait_r_lcl_reg_0(\\act_this_rank_r_reg[0] ),\n .\\app_addr_r1_reg[12] (\\app_addr_r1_reg[12] ),\n .\\app_addr_r1_reg[27] (\\app_addr_r1_reg[27] ),\n .\\app_addr_r1_reg[9] (\\app_addr_r1_reg[9] ),\n .\\app_cmd_r1_reg[0] (\\app_cmd_r1_reg[0] ),\n .\\app_cmd_r2_reg[1] (\\app_cmd_r2_reg[1] ),\n .bm_end_r1_reg(bm_end_r1_reg),\n .\\cmd_pipe_plus.mc_address_reg[24] (\\cmd_pipe_plus.mc_address_reg[24] ),\n .\\cmd_pipe_plus.mc_address_reg[40] (\\cmd_pipe_plus.mc_address_reg[40] ),\n .\\cmd_pipe_plus.mc_address_reg[44] (\\cmd_pipe_plus.mc_address_reg[44] ),\n .\\cmd_pipe_plus.mc_bank_reg[8] (\\cmd_pipe_plus.mc_bank_reg[8] ),\n .\\col_mux.col_data_buf_addr_r_reg[4] (\\col_mux.col_data_buf_addr_r_reg[4] ),\n .col_wait_r_reg(\\starve_limit_cntr_r_reg[2] ),\n .demand_priority_r_reg(bank_compare0_n_8),\n .\\grant_r_reg[1] (\\grant_r_reg[1] ),\n .\\grant_r_reg[3] (\\grant_r_reg[3] ),\n .\\grant_r_reg[3]_0 (\\grant_r_reg[3]_0 [2:1]),\n .\\grant_r_reg[3]_1 (\\grant_r_reg[3]_2 ),\n .hi_priority(hi_priority),\n .idle_r_lcl_reg(rb_hit_busy_r_reg),\n .idle_r_lcl_reg_0(E),\n .\\maint_controller.maint_wip_r_lcl_reg (\\maint_controller.maint_wip_r_lcl_reg ),\n .maint_req_r(maint_req_r),\n .\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),\n .order_q_r(order_q_r),\n .\\order_q_r_reg[0] (\\order_q_r_reg[0] ),\n .\\order_q_r_reg[1] (\\order_q_r_reg[1] ),\n .ordered_r(ordered_r),\n .ordered_r_lcl_reg(ordered_r_lcl_reg_0),\n .p_52_out(p_52_out),\n .p_67_out(p_67_out),\n .pass_open_bank_ns(pass_open_bank_ns),\n .pass_open_bank_r_lcl_reg(act_wait_r_lcl_reg),\n .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg_1),\n .periodic_rd_ack_r_lcl_reg_0(periodic_rd_ack_r_lcl_reg_2),\n .periodic_rd_cntr_r_reg(periodic_rd_cntr_r_reg),\n .periodic_rd_insert(periodic_rd_insert),\n .periodic_rd_r(periodic_rd_r),\n .pre_bm_end_r_9(pre_bm_end_r_9),\n .pre_passing_open_bank_r(pre_passing_open_bank_r),\n .pre_wait_r(pre_wait_r),\n .q_has_priority_11(q_has_priority_11),\n .q_has_priority_r_reg(q_has_priority_r_reg),\n .\\ras_timer_r_reg[0] (\\ras_timer_r_reg[0]_0 ),\n .ras_timer_zero_r_reg(bank_compare0_n_10),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 ),\n .rb_hit_busy_r_reg_0(rb_hit_busy_r_reg_2),\n .\\rd_this_rank_r_reg[0] (\\rd_this_rank_r_reg[0] ),\n .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg_0),\n .rd_wr_r_lcl_reg_1(rd_wr_r_lcl_reg_1),\n .req_bank_rdy_ns(req_bank_rdy_ns),\n .req_bank_rdy_r_reg(req_bank_rdy_r_reg),\n .req_periodic_rd_r(req_periodic_rd_r),\n .\\req_row_r_lcl_reg[10]_0 (\\req_row_r_lcl_reg[10] ),\n .req_wr_r_lcl_reg_0(req_wr_r_lcl_reg_0),\n .req_wr_r_lcl_reg_1(req_wr_r_lcl_reg_1),\n .row_hit_r_5(row_hit_r_5),\n .start_wtp_timer0(start_wtp_timer0),\n .tail_r_26(tail_r_26),\n .wait_for_maint_r_19(wait_for_maint_r_19));\n ddr3_if_mig_7series_v4_0_bank_queue__parameterized1 bank_queue0\n (.CLK(CLK),\n .D(D),\n .E(idle_ns),\n .Q(Q),\n .SR(SR),\n .accept_internal_r_reg(accept_internal_r_reg),\n .accept_r_reg(accept_r_reg),\n .act_wait_ns(act_wait_ns),\n .act_wait_r_lcl_reg(act_wait_r_lcl_reg),\n .act_wait_r_lcl_reg_0(\\act_this_rank_r_reg[0] ),\n .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_0),\n .bm_end_r1_reg(\\ras_timer_r_reg[1] ),\n .bm_end_r1_reg_0(bm_end_r1_reg_1),\n .bm_end_r1_reg_1(bm_end_r1_reg_2),\n .bm_end_r1_reg_2(bm_end_r1_reg_3),\n .bm_end_r1_reg_3(bm_end_r1_reg_4),\n .bm_end_r1_reg_4(bm_end_r1_reg_0),\n .col_wait_r_reg(col_wait_r_reg),\n .\\compute_tail.tail_r_lcl_reg_0 (\\compute_tail.tail_r_lcl_reg ),\n .\\grant_r_reg[1] (\\grant_r_reg[1]_0 ),\n .\\grant_r_reg[2] (\\grant_r_reg[2] ),\n .\\grant_r_reg[2]_0 (\\grant_r_reg[2]_1 ),\n .\\grant_r_reg[2]_1 (\\grant_r_reg[3]_0 [1]),\n .\\grant_r_reg[3] (\\grant_r_reg[3]_1 ),\n .granted_row_ns(granted_row_ns),\n .granted_row_r_reg(granted_row_r_reg),\n .head_r_lcl_reg_0(head_r_lcl_reg),\n .head_r_lcl_reg_1(head_r_lcl_reg_0),\n .idle_r_lcl_reg_0(idle_r_lcl_reg),\n .idle_r_lcl_reg_1(idle_r_lcl_reg_0),\n .idle_r_lcl_reg_2(idle_r_lcl_reg_1),\n .idle_r_lcl_reg_3(idle_r_lcl_reg_2),\n .idle_r_lcl_reg_4(idle_r_lcl_reg_3),\n .idle_r_lcl_reg_5(idle_r_lcl_reg_4),\n .idle_r_lcl_reg_6(idle_r_lcl_reg_5),\n .\\maintenance_request.maint_req_r_lcl_reg (\\maintenance_request.maint_req_r_lcl_reg ),\n .order_q_r(order_q_r),\n .ordered_r(ordered_r),\n .ordered_r_lcl_reg_0(ordered_r_lcl_reg),\n .ordered_r_lcl_reg_1(\\order_q_r_reg[1] ),\n .ordered_r_lcl_reg_2(\\order_q_r_reg[0] ),\n .override_demand_r_reg(override_demand_r_reg),\n .p_67_out(p_67_out),\n .pass_open_bank_ns(pass_open_bank_ns),\n .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg),\n .periodic_rd_ack_r_lcl_reg_0(periodic_rd_ack_r_lcl_reg_0),\n .periodic_rd_ack_r_lcl_reg_1(periodic_rd_ack_r_lcl_reg_1),\n .pre_bm_end_ns(pre_bm_end_ns),\n .pre_bm_end_r_9(pre_bm_end_r_9),\n .pre_bm_end_r_reg_0(pre_bm_end_r_reg),\n .pre_bm_end_r_reg_1(pre_bm_end_r_reg_0),\n .pre_bm_end_r_reg_2(pre_bm_end_r_reg_1),\n .pre_passing_open_bank_ns(pre_passing_open_bank_ns),\n .pre_passing_open_bank_r(pre_passing_open_bank_r),\n .pre_passing_open_bank_r_reg_0(pre_passing_open_bank_r_reg),\n .pre_passing_open_bank_r_reg_1(pre_passing_open_bank_r_reg_0),\n .\\q_entry_r_reg[0]_0 (\\q_entry_r_reg[0] ),\n .\\q_entry_r_reg[1]_0 (\\q_entry_r_reg[1] ),\n .\\q_entry_r_reg[1]_1 (\\q_entry_r_reg[1]_0 ),\n .\\q_entry_r_reg[1]_2 (\\q_entry_r_reg[1]_1 ),\n .\\q_entry_r_reg[1]_3 (\\q_entry_r_reg[1]_2 ),\n .\\q_entry_r_reg[1]_4 (\\q_entry_r_reg[1]_3 ),\n .q_has_priority_11(q_has_priority_11),\n .q_has_priority_r_reg_0(q_has_priority_r_reg_0),\n .q_has_rd_10(q_has_rd_10),\n .q_has_rd_r_reg_0(q_has_rd_r_reg),\n .\\ras_timer_r_reg[0] (bank_queue0_n_21),\n .\\ras_timer_r_reg[0]_0 (\\ras_timer_r_reg[0]_1 ),\n .\\ras_timer_r_reg[1] (\\ras_timer_r_reg[0] ),\n .\\ras_timer_r_reg[1]_0 (\\ras_timer_r_reg[1]_0 ),\n .\\ras_timer_r_reg[1]_1 (\\ras_timer_r_reg[1]_1 ),\n .\\ras_timer_r_reg[2] (ras_timer_passed_ns),\n .\\ras_timer_r_reg[2]_0 (\\ras_timer_r_reg[2]_0 ),\n .\\ras_timer_r_reg[2]_1 (\\ras_timer_r_reg[2]_1 ),\n .\\ras_timer_r_reg[2]_2 (\\ras_timer_r_reg[2]_2 ),\n .ras_timer_zero_r_reg(ras_timer_zero_r_reg),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),\n .rb_hit_busy_r_reg(rb_hit_busy_r_reg),\n .rb_hit_busy_r_reg_0(rb_hit_busy_r_reg_0),\n .rb_hit_busy_r_reg_1(rb_hit_busy_r_reg_1),\n .rd_wr_r_lcl_reg(\\rd_this_rank_r_reg[0] ),\n .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg_1),\n .rd_wr_r_lcl_reg_1(rd_wr_r_lcl_reg_2),\n .\\req_bank_r_lcl_reg[2] (\\req_bank_r_lcl_reg[2] ),\n .\\req_data_buf_addr_r_reg[4] (E),\n .req_wr_r_lcl_reg(req_wr_r_lcl_reg),\n .req_wr_r_lcl_reg_0(req_wr_r_lcl_reg_1),\n .req_wr_r_lcl_reg_1(bm_end_r1_reg),\n .req_wr_r_lcl_reg_2(req_bank_rdy_r_reg),\n .rnk_config_valid_r_lcl_reg(rnk_config_valid_r_lcl_reg),\n .\\rp_timer.rp_timer_r_reg[1] (\\rp_timer.rp_timer_r_reg[1]_0 ),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .\\rtw_timer.rtw_cnt_r_reg[1] (\\rtw_timer.rtw_cnt_r_reg[1] ),\n .tail_r_26(tail_r_26),\n .use_addr(use_addr),\n .wait_for_maint_r_19(wait_for_maint_r_19),\n .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg),\n .wait_for_maint_r_lcl_reg_1(wait_for_maint_r_lcl_reg_0),\n .\\wtr_timer.wtr_cnt_r_reg[1] (\\wtr_timer.wtr_cnt_r_reg[1] ));\n ddr3_if_mig_7series_v4_0_bank_state__parameterized1 bank_state0\n (.CLK(CLK),\n .D(ras_timer_passed_ns),\n .SR(SR),\n .act_this_rank_r(act_this_rank_r),\n .\\act_this_rank_r_reg[0]_0 (\\act_this_rank_r_reg[0] ),\n .act_wait_ns(act_wait_ns),\n .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg),\n .auto_pre_r_lcl_reg_0(\\rp_timer.rp_timer_r_reg[1]_0 ),\n .bm_end_r1_reg_0(bm_end_r1_reg_0),\n .demand_priority_r(demand_priority_r),\n .demand_priority_r_reg_0(demand_priority_r_reg),\n .demanded_prior_r(demanded_prior_r),\n .demanded_prior_r_reg_0(demanded_prior_r_reg),\n .demanded_prior_r_reg_1(demanded_prior_r_reg_0),\n .\\entry_cnt_reg[2] (\\entry_cnt_reg[2] ),\n .\\entry_cnt_reg[2]_0 (\\entry_cnt_reg[2]_0 ),\n .\\grant_r_reg[2] (\\grant_r_reg[2]_0 ),\n .\\grant_r_reg[2]_0 (\\grant_r_reg[3]_0 [1:0]),\n .\\grant_r_reg[2]_1 (\\grant_r_reg[2]_1 ),\n .\\grant_r_reg[2]_2 (\\grant_r_reg[3]_2 [0]),\n .granted_col_r_reg(granted_col_r_reg),\n .idle_r_lcl_reg(rb_hit_busy_r_reg),\n .of_ctl_full_v(of_ctl_full_v),\n .ofs_rdy_r(ofs_rdy_r),\n .ofs_rdy_r0(ofs_rdy_r0),\n .ofs_rdy_r0_0(ofs_rdy_r0_0),\n .ofs_rdy_r0_1(ofs_rdy_r0_1),\n .override_demand_ns(override_demand_ns),\n .override_demand_r(override_demand_r),\n .p_52_out(p_52_out),\n .pass_open_bank_ns(pass_open_bank_ns),\n .pass_open_bank_r_lcl_reg(act_wait_r_lcl_reg),\n .phy_mc_ctl_full(phy_mc_ctl_full),\n .pre_bm_end_ns(pre_bm_end_ns),\n .pre_passing_open_bank_ns(pre_passing_open_bank_ns),\n .pre_wait_r(pre_wait_r),\n .q_has_rd_10(q_has_rd_10),\n .\\ras_timer_r_reg[0]_0 (\\ras_timer_r_reg[0] ),\n .\\ras_timer_r_reg[1]_0 (\\ras_timer_r_reg[1] ),\n .\\ras_timer_r_reg[2]_0 (\\ras_timer_r_reg[2] ),\n .\\ras_timer_r_reg[2]_1 (\\ras_timer_r_reg[2]_0 ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] (bank_queue0_n_21),\n .rb_hit_busy_r_reg(rb_hit_busy_r_reg_2),\n .rd_this_rank_r(rd_this_rank_r),\n .rd_wr_r(rd_wr_r),\n .rd_wr_r_lcl_reg(\\rd_this_rank_r_reg[0] ),\n .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg),\n .rd_wr_r_lcl_reg_1(rd_wr_r_lcl_reg_0),\n .rd_wr_r_lcl_reg_2(bank_compare0_n_10),\n .req_bank_rdy_ns(req_bank_rdy_ns),\n .req_priority_r_reg(bank_compare0_n_8),\n .req_wr_r_lcl_reg(bm_end_r1_reg),\n .\\rnk_config_strobe_r_reg[0] (\\rnk_config_strobe_r_reg[0] ),\n .\\rp_timer.rp_timer_r_reg[1]_0 (\\rp_timer.rp_timer_r_reg[1] ),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22),\n .rtp_timer_ns1_7(rtp_timer_ns1_7),\n .start_wtp_timer0(start_wtp_timer0),\n .\\starve_limit_cntr_r_reg[2]_0 (\\starve_limit_cntr_r_reg[2] ),\n .tail_r_26(tail_r_26),\n .wr_this_rank_r(wr_this_rank_r));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_bank_cntrl\" *) \nmodule ddr3_if_mig_7series_v4_0_bank_cntrl__parameterized2\n (E,\n req_periodic_rd_r,\n \\rd_this_rank_r_reg[0] ,\n bm_end_r1_reg,\n q_has_priority_r_reg,\n row_hit_r_12,\n bm_end_r1_4,\n \\act_this_rank_r_reg[0] ,\n act_this_rank_r,\n req_bank_rdy_r,\n req_bank_rdy_ns,\n demand_priority_r_reg,\n demanded_prior_r_reg,\n ofs_rdy_r,\n wr_this_rank_r,\n rd_this_rank_r,\n act_wait_r_lcl_reg,\n pre_bm_end_r_15,\n q_has_rd_16,\n q_has_priority_17,\n wait_for_maint_r_20,\n \\starve_limit_cntr_r_reg[2] ,\n tail_r_28,\n wait_for_maint_r_lcl_reg,\n \\rp_timer.rp_timer_r_reg[1] ,\n ordered_r,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ,\n rb_hit_busy_r_reg,\n \\q_entry_r_reg[1] ,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ,\n granted_col_r_reg,\n \\grant_r_reg[3] ,\n \\ras_timer_r_reg[0] ,\n Q,\n \\ras_timer_r_reg[1] ,\n \\ras_timer_r_reg[2] ,\n \\grant_r_reg[3]_0 ,\n \\q_entry_r_reg[1]_0 ,\n \\q_entry_r_reg[0] ,\n head_r_lcl_reg,\n \\q_entry_r_reg[1]_1 ,\n \\ras_timer_r_reg[0]_0 ,\n \\grant_r_reg[1] ,\n \\ras_timer_r_reg[0]_1 ,\n auto_pre_r_lcl_reg,\n \\pre_4_1_1T_arb.granted_pre_r_reg ,\n \\cmd_pipe_plus.mc_address_reg[10] ,\n \\cmd_pipe_plus.mc_address_reg[44] ,\n \\grant_r_reg[0] ,\n \\grant_r_reg[2] ,\n \\grant_r_reg[3]_1 ,\n demanded_prior_r_reg_0,\n \\rnk_config_strobe_r_reg[0] ,\n \\col_mux.col_data_buf_addr_r_reg[4] ,\n \\cmd_pipe_plus.mc_bank_reg[8] ,\n \\cmd_pipe_plus.mc_address_reg[24] ,\n CLK,\n periodic_rd_insert,\n hi_priority,\n SR,\n ofs_rdy_r0,\n q_has_rd_r_reg,\n q_has_priority_r_reg_0,\n \\maintenance_request.maint_req_r_lcl_reg ,\n wait_for_maint_r_lcl_reg_0,\n idle_r_lcl_reg,\n rstdiv0_sync_r1_reg_rep__0,\n head_r_lcl_reg_0,\n auto_pre_r_lcl_reg_0,\n ordered_r_lcl_reg,\n \\req_bank_r_lcl_reg[0] ,\n idle_r_lcl_reg_0,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ,\n rstdiv0_sync_r1_reg_rep__20,\n idle_r_lcl_reg_1,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 ,\n idle_r_lcl_reg_2,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4 ,\n rd_wr_r_lcl_reg,\n \\rtw_timer.rtw_cnt_r_reg[1] ,\n \\wtr_timer.wtr_cnt_r_reg[1] ,\n col_wait_r_reg,\n \\ras_timer_r_reg[1]_0 ,\n \\ras_timer_r_reg[1]_1 ,\n \\ras_timer_r_reg[1]_2 ,\n bm_end_r1_reg_0,\n bm_end_r1_reg_1,\n bm_end_r1_reg_2,\n \\ras_timer_r_reg[2]_0 ,\n \\ras_timer_r_reg[2]_1 ,\n bm_end_r1_reg_3,\n req_wr_r_lcl_reg,\n rd_wr_r_lcl_reg_0,\n \\grant_r_reg[3]_2 ,\n rd_wr_r,\n req_wr_r,\n bm_end_r1_reg_4,\n rstdiv0_sync_r1_reg_rep__21,\n \\grant_r_reg[3]_3 ,\n pre_passing_open_bank_r_reg,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ,\n pre_passing_open_bank_r_reg_0,\n idle_r_lcl_reg_3,\n periodic_rd_ack_r_lcl_reg,\n idle_r_lcl_reg_4,\n rb_hit_busy_r,\n accept_r_reg,\n rb_hit_busy_r_reg_0,\n rb_hit_busy_r_reg_1,\n periodic_rd_ack_r_lcl_reg_0,\n pre_bm_end_r_reg,\n pre_bm_end_r_reg_0,\n pre_bm_end_r_reg_1,\n \\app_cmd_r2_reg[1] ,\n \\app_cmd_r1_reg[0] ,\n periodic_rd_ack_r_lcl_reg_1,\n periodic_rd_cntr_r_reg,\n periodic_rd_r,\n periodic_rd_ack_r_lcl_reg_2,\n use_addr,\n accept_internal_r_reg,\n req_wr_r_lcl_reg_0,\n rtp_timer_ns1_6,\n rb_hit_busy_r_reg_2,\n maint_req_r,\n \\maint_controller.maint_wip_r_lcl_reg ,\n \\grant_r_reg[3]_4 ,\n auto_pre_r_lcl_reg_1,\n demanded_prior_r_reg_1,\n \\grant_r_reg[1]_0 ,\n override_demand_r,\n rnk_config_valid_r_lcl_reg,\n \\req_row_r_lcl_reg[10] ,\n row_cmd_wr,\n \\grant_r_reg[3]_5 ,\n \\last_master_r_reg[2] ,\n rstdiv0_sync_r1_reg_rep__22,\n \\app_addr_r1_reg[27] ,\n demand_priority_r_reg_0,\n demanded_prior_r,\n req_bank_rdy_r_reg,\n granted_col_r_reg_0,\n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ,\n \\app_addr_r1_reg[12] ,\n \\app_addr_r1_reg[9] ,\n D,\n idle_r_lcl_reg_5,\n pre_bm_end_r_reg_2,\n ordered_r_lcl_reg_0,\n idle_r_lcl_reg_6,\n ordered_r_lcl_reg_1);\n output [0:0]E;\n output [0:0]req_periodic_rd_r;\n output \\rd_this_rank_r_reg[0] ;\n output bm_end_r1_reg;\n output q_has_priority_r_reg;\n output row_hit_r_12;\n output bm_end_r1_4;\n output \\act_this_rank_r_reg[0] ;\n output [0:0]act_this_rank_r;\n output req_bank_rdy_r;\n output req_bank_rdy_ns;\n output demand_priority_r_reg;\n output demanded_prior_r_reg;\n output ofs_rdy_r;\n output [0:0]wr_this_rank_r;\n output [0:0]rd_this_rank_r;\n output act_wait_r_lcl_reg;\n output pre_bm_end_r_15;\n output q_has_rd_16;\n output q_has_priority_17;\n output wait_for_maint_r_20;\n output \\starve_limit_cntr_r_reg[2] ;\n output tail_r_28;\n output wait_for_maint_r_lcl_reg;\n output \\rp_timer.rp_timer_r_reg[1] ;\n output [0:0]ordered_r;\n output [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;\n output rb_hit_busy_r_reg;\n output \\q_entry_r_reg[1] ;\n output [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;\n output [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ;\n output granted_col_r_reg;\n output \\grant_r_reg[3] ;\n output \\ras_timer_r_reg[0] ;\n output [2:0]Q;\n output \\ras_timer_r_reg[1] ;\n output \\ras_timer_r_reg[2] ;\n output \\grant_r_reg[3]_0 ;\n output \\q_entry_r_reg[1]_0 ;\n output \\q_entry_r_reg[0] ;\n output head_r_lcl_reg;\n output \\q_entry_r_reg[1]_1 ;\n output \\ras_timer_r_reg[0]_0 ;\n output \\grant_r_reg[1] ;\n output \\ras_timer_r_reg[0]_1 ;\n output auto_pre_r_lcl_reg;\n output \\pre_4_1_1T_arb.granted_pre_r_reg ;\n output \\cmd_pipe_plus.mc_address_reg[10] ;\n output [14:0]\\cmd_pipe_plus.mc_address_reg[44] ;\n output \\grant_r_reg[0] ;\n output \\grant_r_reg[2] ;\n output \\grant_r_reg[3]_1 ;\n output demanded_prior_r_reg_0;\n output \\rnk_config_strobe_r_reg[0] ;\n output [4:0]\\col_mux.col_data_buf_addr_r_reg[4] ;\n output [2:0]\\cmd_pipe_plus.mc_bank_reg[8] ;\n output [6:0]\\cmd_pipe_plus.mc_address_reg[24] ;\n input CLK;\n input periodic_rd_insert;\n input hi_priority;\n input [0:0]SR;\n input ofs_rdy_r0;\n input q_has_rd_r_reg;\n input q_has_priority_r_reg_0;\n input \\maintenance_request.maint_req_r_lcl_reg ;\n input wait_for_maint_r_lcl_reg_0;\n input idle_r_lcl_reg;\n input rstdiv0_sync_r1_reg_rep__0;\n input head_r_lcl_reg_0;\n input auto_pre_r_lcl_reg_0;\n input ordered_r_lcl_reg;\n input \\req_bank_r_lcl_reg[0] ;\n input idle_r_lcl_reg_0;\n input [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ;\n input rstdiv0_sync_r1_reg_rep__20;\n input idle_r_lcl_reg_1;\n input [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 ;\n input idle_r_lcl_reg_2;\n input [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4 ;\n input rd_wr_r_lcl_reg;\n input \\rtw_timer.rtw_cnt_r_reg[1] ;\n input \\wtr_timer.wtr_cnt_r_reg[1] ;\n input col_wait_r_reg;\n input \\ras_timer_r_reg[1]_0 ;\n input \\ras_timer_r_reg[1]_1 ;\n input \\ras_timer_r_reg[1]_2 ;\n input bm_end_r1_reg_0;\n input bm_end_r1_reg_1;\n input bm_end_r1_reg_2;\n input \\ras_timer_r_reg[2]_0 ;\n input \\ras_timer_r_reg[2]_1 ;\n input bm_end_r1_reg_3;\n input req_wr_r_lcl_reg;\n input rd_wr_r_lcl_reg_0;\n input [2:0]\\grant_r_reg[3]_2 ;\n input [0:0]rd_wr_r;\n input [0:0]req_wr_r;\n input bm_end_r1_reg_4;\n input rstdiv0_sync_r1_reg_rep__21;\n input [0:0]\\grant_r_reg[3]_3 ;\n input pre_passing_open_bank_r_reg;\n input \\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;\n input pre_passing_open_bank_r_reg_0;\n input idle_r_lcl_reg_3;\n input periodic_rd_ack_r_lcl_reg;\n input idle_r_lcl_reg_4;\n input [2:0]rb_hit_busy_r;\n input accept_r_reg;\n input rb_hit_busy_r_reg_0;\n input rb_hit_busy_r_reg_1;\n input periodic_rd_ack_r_lcl_reg_0;\n input pre_bm_end_r_reg;\n input pre_bm_end_r_reg_0;\n input pre_bm_end_r_reg_1;\n input [0:0]\\app_cmd_r2_reg[1] ;\n input \\app_cmd_r1_reg[0] ;\n input periodic_rd_ack_r_lcl_reg_1;\n input periodic_rd_cntr_r_reg;\n input periodic_rd_r;\n input periodic_rd_ack_r_lcl_reg_2;\n input use_addr;\n input accept_internal_r_reg;\n input req_wr_r_lcl_reg_0;\n input rtp_timer_ns1_6;\n input rb_hit_busy_r_reg_2;\n input maint_req_r;\n input \\maint_controller.maint_wip_r_lcl_reg ;\n input [0:0]\\grant_r_reg[3]_4 ;\n input auto_pre_r_lcl_reg_1;\n input demanded_prior_r_reg_1;\n input \\grant_r_reg[1]_0 ;\n input override_demand_r;\n input rnk_config_valid_r_lcl_reg;\n input [0:0]\\req_row_r_lcl_reg[10] ;\n input [0:0]row_cmd_wr;\n input \\grant_r_reg[3]_5 ;\n input \\last_master_r_reg[2] ;\n input rstdiv0_sync_r1_reg_rep__22;\n input [14:0]\\app_addr_r1_reg[27] ;\n input demand_priority_r_reg_0;\n input demanded_prior_r;\n input req_bank_rdy_r_reg;\n input granted_col_r_reg_0;\n input [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n input [2:0]\\app_addr_r1_reg[12] ;\n input [6:0]\\app_addr_r1_reg[9] ;\n input [2:0]D;\n input idle_r_lcl_reg_5;\n input pre_bm_end_r_reg_2;\n input ordered_r_lcl_reg_0;\n input idle_r_lcl_reg_6;\n input ordered_r_lcl_reg_1;\n\n wire CLK;\n wire [2:0]D;\n wire [0:0]E;\n wire [2:0]Q;\n wire [0:0]SR;\n wire accept_internal_r_reg;\n wire accept_r_reg;\n wire [0:0]act_this_rank_r;\n wire \\act_this_rank_r_reg[0] ;\n wire act_wait_ns;\n wire act_wait_r_lcl_reg;\n wire [2:0]\\app_addr_r1_reg[12] ;\n wire [14:0]\\app_addr_r1_reg[27] ;\n wire [6:0]\\app_addr_r1_reg[9] ;\n wire \\app_cmd_r1_reg[0] ;\n wire [0:0]\\app_cmd_r2_reg[1] ;\n wire auto_pre_r_lcl_reg;\n wire auto_pre_r_lcl_reg_0;\n wire auto_pre_r_lcl_reg_1;\n wire bank_compare0_n_9;\n wire bank_queue0_n_20;\n wire bank_queue0_n_24;\n wire bank_state0_n_19;\n wire bm_end_r1_4;\n wire bm_end_r1_reg;\n wire bm_end_r1_reg_0;\n wire bm_end_r1_reg_1;\n wire bm_end_r1_reg_2;\n wire bm_end_r1_reg_3;\n wire bm_end_r1_reg_4;\n wire \\cmd_pipe_plus.mc_address_reg[10] ;\n wire [6:0]\\cmd_pipe_plus.mc_address_reg[24] ;\n wire [14:0]\\cmd_pipe_plus.mc_address_reg[44] ;\n wire [2:0]\\cmd_pipe_plus.mc_bank_reg[8] ;\n wire [4:0]\\col_mux.col_data_buf_addr_r_reg[4] ;\n wire col_wait_r_reg;\n wire demand_priority_r_reg;\n wire demand_priority_r_reg_0;\n wire demanded_prior_r;\n wire demanded_prior_r_reg;\n wire demanded_prior_r_reg_0;\n wire demanded_prior_r_reg_1;\n wire \\grant_r_reg[0] ;\n wire \\grant_r_reg[1] ;\n wire \\grant_r_reg[1]_0 ;\n wire \\grant_r_reg[2] ;\n wire \\grant_r_reg[3] ;\n wire \\grant_r_reg[3]_0 ;\n wire \\grant_r_reg[3]_1 ;\n wire [2:0]\\grant_r_reg[3]_2 ;\n wire [0:0]\\grant_r_reg[3]_3 ;\n wire [0:0]\\grant_r_reg[3]_4 ;\n wire \\grant_r_reg[3]_5 ;\n wire granted_col_r_reg;\n wire granted_col_r_reg_0;\n wire head_r_lcl_reg;\n wire head_r_lcl_reg_0;\n wire hi_priority;\n wire [3:3]idle_ns;\n wire idle_r_lcl_reg;\n wire idle_r_lcl_reg_0;\n wire idle_r_lcl_reg_1;\n wire idle_r_lcl_reg_2;\n wire idle_r_lcl_reg_3;\n wire idle_r_lcl_reg_4;\n wire idle_r_lcl_reg_5;\n wire idle_r_lcl_reg_6;\n wire \\last_master_r_reg[2] ;\n wire \\maint_controller.maint_wip_r_lcl_reg ;\n wire maint_req_r;\n wire \\maintenance_request.maint_req_r_lcl_reg ;\n wire [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n wire ofs_rdy_r;\n wire ofs_rdy_r0;\n wire [1:0]order_q_r;\n wire [0:0]ordered_r;\n wire ordered_r_lcl_reg;\n wire ordered_r_lcl_reg_0;\n wire ordered_r_lcl_reg_1;\n wire override_demand_r;\n wire p_13_out;\n wire p_28_out;\n wire pass_open_bank_ns;\n wire periodic_rd_ack_r_lcl_reg;\n wire periodic_rd_ack_r_lcl_reg_0;\n wire periodic_rd_ack_r_lcl_reg_1;\n wire periodic_rd_ack_r_lcl_reg_2;\n wire periodic_rd_cntr_r_reg;\n wire periodic_rd_insert;\n wire periodic_rd_r;\n wire \\pre_4_1_1T_arb.granted_pre_r_reg ;\n wire pre_bm_end_ns;\n wire pre_bm_end_r_15;\n wire pre_bm_end_r_reg;\n wire pre_bm_end_r_reg_0;\n wire pre_bm_end_r_reg_1;\n wire pre_bm_end_r_reg_2;\n wire pre_passing_open_bank_ns;\n wire pre_passing_open_bank_r;\n wire pre_passing_open_bank_r_reg;\n wire pre_passing_open_bank_r_reg_0;\n wire pre_wait_r;\n wire \\q_entry_r_reg[0] ;\n wire \\q_entry_r_reg[1] ;\n wire \\q_entry_r_reg[1]_0 ;\n wire \\q_entry_r_reg[1]_1 ;\n wire q_has_priority_17;\n wire q_has_priority_r_reg;\n wire q_has_priority_r_reg_0;\n wire q_has_rd_16;\n wire q_has_rd_r_reg;\n wire [2:0]ras_timer_passed_ns;\n wire \\ras_timer_r_reg[0] ;\n wire \\ras_timer_r_reg[0]_0 ;\n wire \\ras_timer_r_reg[0]_1 ;\n wire \\ras_timer_r_reg[1] ;\n wire \\ras_timer_r_reg[1]_0 ;\n wire \\ras_timer_r_reg[1]_1 ;\n wire \\ras_timer_r_reg[1]_2 ;\n wire \\ras_timer_r_reg[2] ;\n wire \\ras_timer_r_reg[2]_0 ;\n wire \\ras_timer_r_reg[2]_1 ;\n wire ras_timer_zero_r;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4 ;\n wire \\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;\n wire [2:0]rb_hit_busy_r;\n wire rb_hit_busy_r_reg;\n wire rb_hit_busy_r_reg_0;\n wire rb_hit_busy_r_reg_1;\n wire rb_hit_busy_r_reg_2;\n wire [0:0]rd_this_rank_r;\n wire \\rd_this_rank_r_reg[0] ;\n wire [0:0]rd_wr_r;\n wire rd_wr_r_lcl_reg;\n wire rd_wr_r_lcl_reg_0;\n wire \\req_bank_r_lcl_reg[0] ;\n wire req_bank_rdy_ns;\n wire req_bank_rdy_r;\n wire req_bank_rdy_r_reg;\n wire [0:0]req_periodic_rd_r;\n wire req_priority_r;\n wire [0:0]\\req_row_r_lcl_reg[10] ;\n wire [0:0]req_wr_r;\n wire req_wr_r_lcl_reg;\n wire req_wr_r_lcl_reg_0;\n wire \\rnk_config_strobe_r_reg[0] ;\n wire rnk_config_valid_r_lcl_reg;\n wire [0:0]row_cmd_wr;\n wire row_hit_r_12;\n wire \\rp_timer.rp_timer_r_reg[1] ;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire rstdiv0_sync_r1_reg_rep__22;\n wire rtp_timer_ns1_6;\n wire \\rtw_timer.rtw_cnt_r_reg[1] ;\n wire start_wtp_timer0;\n wire \\starve_limit_cntr_r_reg[2] ;\n wire tail_r_28;\n wire use_addr;\n wire wait_for_maint_r_20;\n wire wait_for_maint_r_lcl_reg;\n wire wait_for_maint_r_lcl_reg_0;\n wire [0:0]wr_this_rank_r;\n wire \\wtr_timer.wtr_cnt_r_reg[1] ;\n\n ddr3_if_mig_7series_v4_0_bank_compare bank_compare0\n (.CLK(CLK),\n .E(idle_ns),\n .\\app_addr_r1_reg[12] (\\app_addr_r1_reg[12] ),\n .\\app_addr_r1_reg[27] (\\app_addr_r1_reg[27] ),\n .\\app_addr_r1_reg[9] (\\app_addr_r1_reg[9] ),\n .\\app_cmd_r1_reg[0] (\\app_cmd_r1_reg[0] ),\n .\\app_cmd_r2_reg[1] (\\app_cmd_r2_reg[1] ),\n .bm_end_r1_reg(bm_end_r1_reg),\n .\\cmd_pipe_plus.mc_address_reg[24] (\\cmd_pipe_plus.mc_address_reg[24] ),\n .\\cmd_pipe_plus.mc_address_reg[44] (\\cmd_pipe_plus.mc_address_reg[44] ),\n .\\cmd_pipe_plus.mc_bank_reg[8] (\\cmd_pipe_plus.mc_bank_reg[8] ),\n .\\col_mux.col_data_buf_addr_r_reg[4] (\\col_mux.col_data_buf_addr_r_reg[4] ),\n .col_wait_r_reg(col_wait_r_reg),\n .demand_priority_r_reg(bank_state0_n_19),\n .\\grant_r_reg[1] (\\grant_r_reg[1] ),\n .\\grant_r_reg[3] (\\grant_r_reg[3] ),\n .\\grant_r_reg[3]_0 (\\grant_r_reg[3]_0 ),\n .\\grant_r_reg[3]_1 (\\grant_r_reg[3]_2 [2:1]),\n .granted_col_r_reg(granted_col_r_reg),\n .hi_priority(hi_priority),\n .idle_r_lcl_reg(rb_hit_busy_r_reg),\n .idle_r_lcl_reg_0(E),\n .\\maint_controller.maint_wip_r_lcl_reg (\\maint_controller.maint_wip_r_lcl_reg ),\n .maint_req_r(maint_req_r),\n .\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),\n .order_q_r(order_q_r),\n .p_13_out(p_13_out),\n .p_28_out(p_28_out),\n .pass_open_bank_ns(pass_open_bank_ns),\n .pass_open_bank_r_lcl_reg(act_wait_r_lcl_reg),\n .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg_1),\n .periodic_rd_ack_r_lcl_reg_0(periodic_rd_ack_r_lcl_reg_2),\n .periodic_rd_cntr_r_reg(periodic_rd_cntr_r_reg),\n .periodic_rd_insert(periodic_rd_insert),\n .periodic_rd_r(periodic_rd_r),\n .pre_bm_end_r_15(pre_bm_end_r_15),\n .pre_passing_open_bank_r(pre_passing_open_bank_r),\n .pre_wait_r(pre_wait_r),\n .q_has_priority_r_reg(q_has_priority_r_reg),\n .\\ras_timer_r_reg[0] (\\ras_timer_r_reg[0]_0 ),\n .ras_timer_zero_r_reg(bank_compare0_n_9),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ),\n .rb_hit_busy_r_reg_0(rb_hit_busy_r_reg_2),\n .\\rd_this_rank_r_reg[0] (\\rd_this_rank_r_reg[0] ),\n .rd_wr_r(rd_wr_r),\n .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg),\n .rd_wr_r_lcl_reg_1(rd_wr_r_lcl_reg_0),\n .req_periodic_rd_r(req_periodic_rd_r),\n .req_priority_r(req_priority_r),\n .req_wr_r(req_wr_r),\n .req_wr_r_lcl_reg_0(req_wr_r_lcl_reg_0),\n .row_hit_r_12(row_hit_r_12),\n .\\rtw_timer.rtw_cnt_r_reg[1] (\\rtw_timer.rtw_cnt_r_reg[1] ),\n .start_wtp_timer0(start_wtp_timer0),\n .tail_r_28(tail_r_28),\n .wait_for_maint_r_20(wait_for_maint_r_20),\n .\\wtr_timer.wtr_cnt_r_reg[1] (\\wtr_timer.wtr_cnt_r_reg[1] ));\n ddr3_if_mig_7series_v4_0_bank_queue__parameterized2 bank_queue0\n (.CLK(CLK),\n .D(ras_timer_passed_ns),\n .E(idle_ns),\n .Q(Q),\n .SR(SR),\n .accept_internal_r_reg(accept_internal_r_reg),\n .accept_r_reg(accept_r_reg),\n .act_wait_ns(act_wait_ns),\n .act_wait_r_lcl_reg(act_wait_r_lcl_reg),\n .act_wait_r_lcl_reg_0(\\act_this_rank_r_reg[0] ),\n .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_0),\n .bm_end_r1_reg(\\ras_timer_r_reg[1] ),\n .bm_end_r1_reg_0(bm_end_r1_reg_0),\n .bm_end_r1_reg_1(bm_end_r1_reg_1),\n .bm_end_r1_reg_2(bm_end_r1_reg_2),\n .bm_end_r1_reg_3(bm_end_r1_reg_3),\n .bm_end_r1_reg_4(bm_end_r1_reg_4),\n .col_wait_r_reg(\\starve_limit_cntr_r_reg[2] ),\n .demand_priority_r_reg(bank_queue0_n_24),\n .\\grant_r_reg[3] (\\grant_r_reg[3]_1 ),\n .\\grant_r_reg[3]_0 (\\grant_r_reg[3]_3 ),\n .\\grant_r_reg[3]_1 (\\grant_r_reg[3]_2 [2]),\n .head_r_lcl_reg_0(head_r_lcl_reg),\n .head_r_lcl_reg_1(head_r_lcl_reg_0),\n .idle_r_lcl_reg_0(idle_r_lcl_reg),\n .idle_r_lcl_reg_1(idle_r_lcl_reg_0),\n .idle_r_lcl_reg_2(idle_r_lcl_reg_1),\n .idle_r_lcl_reg_3(idle_r_lcl_reg_2),\n .idle_r_lcl_reg_4(idle_r_lcl_reg_3),\n .idle_r_lcl_reg_5(idle_r_lcl_reg_4),\n .idle_r_lcl_reg_6(idle_r_lcl_reg_5),\n .idle_r_lcl_reg_7(idle_r_lcl_reg_6),\n .\\maintenance_request.maint_req_r_lcl_reg (\\maintenance_request.maint_req_r_lcl_reg ),\n .order_q_r(order_q_r),\n .ordered_r(ordered_r),\n .ordered_r_lcl_reg_0(ordered_r_lcl_reg),\n .ordered_r_lcl_reg_1(ordered_r_lcl_reg_0),\n .ordered_r_lcl_reg_2(ordered_r_lcl_reg_1),\n .p_28_out(p_28_out),\n .pass_open_bank_ns(pass_open_bank_ns),\n .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg),\n .periodic_rd_ack_r_lcl_reg_0(periodic_rd_ack_r_lcl_reg_0),\n .periodic_rd_ack_r_lcl_reg_1(periodic_rd_ack_r_lcl_reg_1),\n .pre_bm_end_ns(pre_bm_end_ns),\n .pre_bm_end_r_15(pre_bm_end_r_15),\n .pre_bm_end_r_reg_0(pre_bm_end_r_reg),\n .pre_bm_end_r_reg_1(pre_bm_end_r_reg_0),\n .pre_bm_end_r_reg_2(pre_bm_end_r_reg_1),\n .pre_bm_end_r_reg_3(pre_bm_end_r_reg_2),\n .pre_passing_open_bank_ns(pre_passing_open_bank_ns),\n .pre_passing_open_bank_r(pre_passing_open_bank_r),\n .pre_passing_open_bank_r_reg_0(pre_passing_open_bank_r_reg),\n .pre_passing_open_bank_r_reg_1(pre_passing_open_bank_r_reg_0),\n .\\q_entry_r_reg[0]_0 (\\q_entry_r_reg[0] ),\n .\\q_entry_r_reg[1]_0 (\\q_entry_r_reg[1] ),\n .\\q_entry_r_reg[1]_1 (\\q_entry_r_reg[1]_0 ),\n .\\q_entry_r_reg[1]_2 (\\q_entry_r_reg[1]_1 ),\n .q_has_priority_17(q_has_priority_17),\n .q_has_priority_r_reg_0(q_has_priority_r_reg_0),\n .q_has_rd_16(q_has_rd_16),\n .q_has_rd_r_reg_0(q_has_rd_r_reg),\n .\\ras_timer_r_reg[0] (bank_queue0_n_20),\n .\\ras_timer_r_reg[0]_0 (\\ras_timer_r_reg[0]_1 ),\n .\\ras_timer_r_reg[1] (\\ras_timer_r_reg[1]_0 ),\n .\\ras_timer_r_reg[1]_0 (\\ras_timer_r_reg[1]_1 ),\n .\\ras_timer_r_reg[1]_1 (\\ras_timer_r_reg[1]_2 ),\n .\\ras_timer_r_reg[2] (\\ras_timer_r_reg[2] ),\n .\\ras_timer_r_reg[2]_0 (\\ras_timer_r_reg[2]_0 ),\n .\\ras_timer_r_reg[2]_1 (\\ras_timer_r_reg[2]_1 ),\n .ras_timer_zero_r(ras_timer_zero_r),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4 (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4 ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 (D),\n .rb_hit_busy_r(rb_hit_busy_r),\n .rb_hit_busy_r_reg(rb_hit_busy_r_reg),\n .rb_hit_busy_r_reg_0(q_has_priority_r_reg),\n .rb_hit_busy_r_reg_1(rb_hit_busy_r_reg_0),\n .rb_hit_busy_r_reg_2(rb_hit_busy_r_reg_1),\n .rd_wr_r_lcl_reg(\\ras_timer_r_reg[0] ),\n .rd_wr_r_lcl_reg_0(\\rd_this_rank_r_reg[0] ),\n .\\req_bank_r_lcl_reg[0] (\\req_bank_r_lcl_reg[0] ),\n .req_bank_rdy_ns(req_bank_rdy_ns),\n .\\req_data_buf_addr_r_reg[4] (E),\n .req_priority_r(req_priority_r),\n .req_wr_r_lcl_reg(req_wr_r_lcl_reg),\n .req_wr_r_lcl_reg_0(req_wr_r_lcl_reg_0),\n .req_wr_r_lcl_reg_1(bm_end_r1_reg),\n .\\rp_timer.rp_timer_r_reg[1] (\\rp_timer.rp_timer_r_reg[1] ),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .tail_r_28(tail_r_28),\n .use_addr(use_addr),\n .wait_for_maint_r_20(wait_for_maint_r_20),\n .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg),\n .wait_for_maint_r_lcl_reg_1(wait_for_maint_r_lcl_reg_0));\n ddr3_if_mig_7series_v4_0_bank_state__parameterized2 bank_state0\n (.CLK(CLK),\n .D(ras_timer_passed_ns),\n .SR(SR),\n .act_this_rank_r(act_this_rank_r),\n .\\act_this_rank_r_reg[0]_0 (\\act_this_rank_r_reg[0] ),\n .act_wait_ns(act_wait_ns),\n .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg),\n .auto_pre_r_lcl_reg_0(\\rp_timer.rp_timer_r_reg[1] ),\n .auto_pre_r_lcl_reg_1(auto_pre_r_lcl_reg_1),\n .bm_end_r1_4(bm_end_r1_4),\n .bm_end_r1_reg_0(bm_end_r1_reg_4),\n .\\cmd_pipe_plus.mc_address_reg[10] (\\cmd_pipe_plus.mc_address_reg[10] ),\n .demand_priority_r_reg_0(demand_priority_r_reg),\n .demand_priority_r_reg_1(demand_priority_r_reg_0),\n .demanded_prior_r(demanded_prior_r),\n .demanded_prior_r_reg_0(demanded_prior_r_reg),\n .demanded_prior_r_reg_1(demanded_prior_r_reg_0),\n .demanded_prior_r_reg_2(demanded_prior_r_reg_1),\n .\\grant_r_reg[0] (\\grant_r_reg[0] ),\n .\\grant_r_reg[1] (\\grant_r_reg[1]_0 ),\n .\\grant_r_reg[2] (\\grant_r_reg[2] ),\n .\\grant_r_reg[3] (bank_state0_n_19),\n .\\grant_r_reg[3]_0 ({\\grant_r_reg[3]_2 [2],\\grant_r_reg[3]_2 [0]}),\n .\\grant_r_reg[3]_1 (\\grant_r_reg[3]_4 ),\n .\\grant_r_reg[3]_2 (\\grant_r_reg[3]_3 ),\n .\\grant_r_reg[3]_3 (\\grant_r_reg[3]_5 ),\n .granted_col_r_reg(granted_col_r_reg_0),\n .idle_r_lcl_reg(rb_hit_busy_r_reg),\n .\\last_master_r_reg[2] (\\last_master_r_reg[2] ),\n .ofs_rdy_r(ofs_rdy_r),\n .ofs_rdy_r0(ofs_rdy_r0),\n .override_demand_r(override_demand_r),\n .p_13_out(p_13_out),\n .pass_open_bank_ns(pass_open_bank_ns),\n .pass_open_bank_r_lcl_reg(act_wait_r_lcl_reg),\n .\\pre_4_1_1T_arb.granted_pre_r_reg (\\pre_4_1_1T_arb.granted_pre_r_reg ),\n .pre_bm_end_ns(pre_bm_end_ns),\n .pre_passing_open_bank_ns(pre_passing_open_bank_ns),\n .pre_wait_r(pre_wait_r),\n .q_has_rd_16(q_has_rd_16),\n .\\ras_timer_r_reg[0]_0 (\\ras_timer_r_reg[0] ),\n .\\ras_timer_r_reg[1]_0 (\\ras_timer_r_reg[1] ),\n .\\ras_timer_r_reg[2]_0 (\\ras_timer_r_reg[2] ),\n .ras_timer_zero_r(ras_timer_zero_r),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] (bank_queue0_n_20),\n .rb_hit_busy_r_reg(rb_hit_busy_r_reg_2),\n .rd_this_rank_r(rd_this_rank_r),\n .rd_wr_r_lcl_reg(\\rd_this_rank_r_reg[0] ),\n .rd_wr_r_lcl_reg_0(bank_compare0_n_9),\n .req_bank_rdy_ns(req_bank_rdy_ns),\n .req_bank_rdy_r(req_bank_rdy_r),\n .req_bank_rdy_r_reg_0(req_bank_rdy_r_reg),\n .req_priority_r_reg(bank_queue0_n_24),\n .\\req_row_r_lcl_reg[10] (\\cmd_pipe_plus.mc_address_reg[44] [10]),\n .\\req_row_r_lcl_reg[10]_0 (\\req_row_r_lcl_reg[10] ),\n .req_wr_r_lcl_reg(bm_end_r1_reg),\n .\\rnk_config_strobe_r_reg[0] (\\rnk_config_strobe_r_reg[0] ),\n .rnk_config_valid_r_lcl_reg(rnk_config_valid_r_lcl_reg),\n .row_cmd_wr(row_cmd_wr),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22),\n .rtp_timer_ns1_6(rtp_timer_ns1_6),\n .start_wtp_timer0(start_wtp_timer0),\n .\\starve_limit_cntr_r_reg[2]_0 (\\starve_limit_cntr_r_reg[2] ),\n .tail_r_28(tail_r_28),\n .wr_this_rank_r(wr_this_rank_r));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_bank_common\n (wait_for_maint_r_lcl_reg,\n was_wr_reg_0,\n \\q_entry_r_reg[1] ,\n accept_ns,\n was_wr,\n insert_maint_r1_lcl_reg,\n \\maint_controller.maint_wip_r_lcl_reg_0 ,\n req_periodic_rd_r_lcl_reg,\n clear_periodic_rd_request,\n \\maint_controller.maint_rdy_r1_reg_0 ,\n head_r_lcl_reg,\n \\q_entry_r_reg[0] ,\n head_r_lcl_reg_0,\n ordered_r_lcl_reg,\n head_r_lcl_reg_1,\n ordered_r_lcl_reg_0,\n head_r_lcl_reg_2,\n ordered_r_lcl_reg_1,\n periodic_rd_insert,\n \\q_entry_r_reg[0]_0 ,\n \\q_entry_r_reg[1]_0 ,\n pass_open_bank_r_lcl_reg,\n pass_open_bank_r_lcl_reg_0,\n Q,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ,\n \\maint_controller.maint_hit_busies_r_reg[3]_0 ,\n p_9_in,\n CLK,\n maint_srx_r,\n \\maintenance_request.maint_req_r_lcl_reg ,\n SR,\n \\periodic_read_request.periodic_rd_r_lcl_reg ,\n periodic_rd_grant_r,\n D,\n periodic_rd_r,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ,\n use_addr,\n E,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ,\n idle_r_lcl_reg,\n head_r,\n idle_r_lcl_reg_0,\n idle_r_lcl_reg_1,\n rb_hit_busy_r,\n maint_req_r,\n rstdiv0_sync_r1_reg_rep__22,\n \\generate_maint_cmds.insert_maint_r_lcl_reg_0 ,\n \\maintenance_request.maint_zq_r_lcl_reg ,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0 ,\n \\app_cmd_r1_reg[0] ,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 );\n output wait_for_maint_r_lcl_reg;\n output was_wr_reg_0;\n output \\q_entry_r_reg[1] ;\n output accept_ns;\n output was_wr;\n output insert_maint_r1_lcl_reg;\n output \\maint_controller.maint_wip_r_lcl_reg_0 ;\n output req_periodic_rd_r_lcl_reg;\n output clear_periodic_rd_request;\n output \\maint_controller.maint_rdy_r1_reg_0 ;\n output head_r_lcl_reg;\n output \\q_entry_r_reg[0] ;\n output head_r_lcl_reg_0;\n output ordered_r_lcl_reg;\n output head_r_lcl_reg_1;\n output ordered_r_lcl_reg_0;\n output head_r_lcl_reg_2;\n output ordered_r_lcl_reg_1;\n output periodic_rd_insert;\n output \\q_entry_r_reg[0]_0 ;\n output \\q_entry_r_reg[1]_0 ;\n output pass_open_bank_r_lcl_reg;\n output pass_open_bank_r_lcl_reg_0;\n output [4:0]Q;\n output [0:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ;\n output [3:0]\\maint_controller.maint_hit_busies_r_reg[3]_0 ;\n input p_9_in;\n input CLK;\n input maint_srx_r;\n input \\maintenance_request.maint_req_r_lcl_reg ;\n input [0:0]SR;\n input \\periodic_read_request.periodic_rd_r_lcl_reg ;\n input periodic_rd_grant_r;\n input [3:0]D;\n input periodic_rd_r;\n input \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ;\n input use_addr;\n input [0:0]E;\n input \\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;\n input [0:0]idle_r_lcl_reg;\n input [3:0]head_r;\n input [0:0]idle_r_lcl_reg_0;\n input [0:0]idle_r_lcl_reg_1;\n input [1:0]rb_hit_busy_r;\n input maint_req_r;\n input rstdiv0_sync_r1_reg_rep__22;\n input \\generate_maint_cmds.insert_maint_r_lcl_reg_0 ;\n input \\maintenance_request.maint_zq_r_lcl_reg ;\n input \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0 ;\n input \\app_cmd_r1_reg[0] ;\n input [2:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 ;\n\n wire CLK;\n wire [3:0]D;\n wire [0:0]E;\n wire [4:0]Q;\n wire [0:0]SR;\n wire accept_ns;\n wire \\app_cmd_r1_reg[0] ;\n wire clear_periodic_rd_request;\n wire \\generate_maint_cmds.insert_maint_r_lcl_reg_0 ;\n wire [3:0]head_r;\n wire head_r_lcl_reg;\n wire head_r_lcl_reg_0;\n wire head_r_lcl_reg_1;\n wire head_r_lcl_reg_2;\n wire [0:0]idle_r_lcl_reg;\n wire [0:0]idle_r_lcl_reg_0;\n wire [0:0]idle_r_lcl_reg_1;\n wire insert_maint_ns;\n wire insert_maint_r1_lcl_reg;\n wire [3:0]\\maint_controller.maint_hit_busies_r_reg[3]_0 ;\n wire \\maint_controller.maint_rdy_r1_reg_0 ;\n wire \\maint_controller.maint_wip_r_lcl_i_1_n_0 ;\n wire \\maint_controller.maint_wip_r_lcl_reg_0 ;\n wire maint_rdy;\n wire maint_rdy_r1;\n wire maint_req_r;\n wire maint_srx_r;\n wire maint_srx_r1;\n wire \\maintenance_request.maint_req_r_lcl_reg ;\n wire \\maintenance_request.maint_zq_r_lcl_reg ;\n wire ordered_r_lcl_reg;\n wire ordered_r_lcl_reg_0;\n wire ordered_r_lcl_reg_1;\n wire p_9_in;\n wire pass_open_bank_r_lcl_reg;\n wire pass_open_bank_r_lcl_reg_0;\n wire periodic_rd_ack_ns;\n wire periodic_rd_grant_r;\n wire periodic_rd_insert;\n wire periodic_rd_r;\n wire \\periodic_read_request.periodic_rd_r_lcl_reg ;\n wire \\q_entry_r_reg[0] ;\n wire \\q_entry_r_reg[0]_0 ;\n wire \\q_entry_r_reg[1] ;\n wire \\q_entry_r_reg[1]_0 ;\n wire \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ;\n wire \\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;\n wire [1:0]rb_hit_busy_r;\n wire req_periodic_rd_r_lcl_reg;\n wire \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_2_n_0 ;\n wire \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3_n_0 ;\n wire \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_4_n_0 ;\n wire [0:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ;\n wire \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0 ;\n wire [2:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 ;\n wire [7:2]rfc_zq_xsdll_timer_ns;\n wire [7:5]rfc_zq_xsdll_timer_r;\n wire rstdiv0_sync_r1_reg_rep__22;\n wire use_addr;\n wire wait_for_maint_r_lcl_reg;\n wire was_wr;\n wire was_wr0;\n wire was_wr_reg_0;\n\n FDRE accept_internal_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(p_9_in),\n .Q(wait_for_maint_r_lcl_reg),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1096\" *) \n LUT4 #(\n .INIT(16'h80AA)) \n accept_r_i_1\n (.I0(p_9_in),\n .I1(was_wr_reg_0),\n .I2(req_periodic_rd_r_lcl_reg),\n .I3(periodic_rd_r),\n .O(accept_ns));\n FDRE accept_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(accept_ns),\n .Q(\\q_entry_r_reg[1] ),\n .R(1'b0));\n LUT4 #(\n .INIT(16'h4F44)) \n \\generate_maint_cmds.insert_maint_r_lcl_i_1 \n (.I0(maint_srx_r1),\n .I1(maint_srx_r),\n .I2(maint_rdy_r1),\n .I3(maint_rdy),\n .O(insert_maint_ns));\n FDRE \\generate_maint_cmds.insert_maint_r_lcl_reg \n (.C(CLK),\n .CE(1'b1),\n .D(insert_maint_ns),\n .Q(insert_maint_r1_lcl_reg),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hE0000000)) \n i___0_i_2\n (.I0(was_wr_reg_0),\n .I1(use_addr),\n .I2(wait_for_maint_r_lcl_reg),\n .I3(head_r[0]),\n .I4(E),\n .O(\\q_entry_r_reg[0] ));\n LUT6 #(\n .INIT(64'h0CCC0CCC08880000)) \n i___10_i_6\n (.I0(\\q_entry_r_reg[1] ),\n .I1(idle_r_lcl_reg_0),\n .I2(head_r[2]),\n .I3(wait_for_maint_r_lcl_reg),\n .I4(use_addr),\n .I5(was_wr_reg_0),\n .O(head_r_lcl_reg_1));\n LUT5 #(\n .INIT(32'hE0000000)) \n i___13_i_2\n (.I0(was_wr_reg_0),\n .I1(use_addr),\n .I2(wait_for_maint_r_lcl_reg),\n .I3(head_r[3]),\n .I4(idle_r_lcl_reg_1),\n .O(ordered_r_lcl_reg_1));\n (* SOFT_HLUTNM = \"soft_lutpair1097\" *) \n LUT4 #(\n .INIT(16'hAA80)) \n i___13_i_3\n (.I0(rb_hit_busy_r[1]),\n .I1(use_addr),\n .I2(\\q_entry_r_reg[1] ),\n .I3(was_wr_reg_0),\n .O(pass_open_bank_r_lcl_reg));\n LUT6 #(\n .INIT(64'h0CCC0CCC08880000)) \n i___14_i_5\n (.I0(\\q_entry_r_reg[1] ),\n .I1(idle_r_lcl_reg_1),\n .I2(head_r[3]),\n .I3(wait_for_maint_r_lcl_reg),\n .I4(use_addr),\n .I5(was_wr_reg_0),\n .O(head_r_lcl_reg_2));\n LUT6 #(\n .INIT(64'h3333300055555555)) \n i___1_i_6\n (.I0(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ),\n .I1(\\q_entry_r_reg[0] ),\n .I2(use_addr),\n .I3(\\q_entry_r_reg[1] ),\n .I4(was_wr_reg_0),\n .I5(E),\n .O(head_r_lcl_reg));\n (* SOFT_HLUTNM = \"soft_lutpair1099\" *) \n LUT3 #(\n .INIT(8'hBA)) \n i___2_i_2\n (.I0(\\maint_controller.maint_wip_r_lcl_reg_0 ),\n .I1(req_periodic_rd_r_lcl_reg),\n .I2(maint_req_r),\n .O(\\maint_controller.maint_rdy_r1_reg_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1098\" *) \n LUT2 #(\n .INIT(4'h8)) \n i___30_i_3\n (.I0(was_wr_reg_0),\n .I1(periodic_rd_grant_r),\n .O(clear_periodic_rd_request));\n (* SOFT_HLUTNM = \"soft_lutpair1097\" *) \n LUT3 #(\n .INIT(8'hEA)) \n i___42_i_1\n (.I0(was_wr_reg_0),\n .I1(\\q_entry_r_reg[1] ),\n .I2(use_addr),\n .O(\\q_entry_r_reg[1]_0 ));\n LUT5 #(\n .INIT(32'hE0000000)) \n i___5_i_2\n (.I0(was_wr_reg_0),\n .I1(use_addr),\n .I2(wait_for_maint_r_lcl_reg),\n .I3(head_r[1]),\n .I4(idle_r_lcl_reg),\n .O(ordered_r_lcl_reg));\n LUT6 #(\n .INIT(64'h3333300055555555)) \n i___6_i_4\n (.I0(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ),\n .I1(ordered_r_lcl_reg),\n .I2(use_addr),\n .I3(\\q_entry_r_reg[1] ),\n .I4(was_wr_reg_0),\n .I5(idle_r_lcl_reg),\n .O(head_r_lcl_reg_0));\n LUT5 #(\n .INIT(32'hE0000000)) \n i___9_i_2\n (.I0(was_wr_reg_0),\n .I1(use_addr),\n .I2(wait_for_maint_r_lcl_reg),\n .I3(head_r[2]),\n .I4(idle_r_lcl_reg_0),\n .O(ordered_r_lcl_reg_0));\n (* SOFT_HLUTNM = \"soft_lutpair1098\" *) \n LUT4 #(\n .INIT(16'hAA80)) \n i___9_i_3\n (.I0(rb_hit_busy_r[0]),\n .I1(use_addr),\n .I2(\\q_entry_r_reg[1] ),\n .I3(was_wr_reg_0),\n .O(pass_open_bank_r_lcl_reg_0));\n FDRE \\maint_controller.maint_hit_busies_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(D[0]),\n .Q(\\maint_controller.maint_hit_busies_r_reg[3]_0 [0]),\n .R(1'b0));\n FDRE \\maint_controller.maint_hit_busies_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(D[1]),\n .Q(\\maint_controller.maint_hit_busies_r_reg[3]_0 [1]),\n .R(1'b0));\n FDRE \\maint_controller.maint_hit_busies_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(D[2]),\n .Q(\\maint_controller.maint_hit_busies_r_reg[3]_0 [2]),\n .R(1'b0));\n FDRE \\maint_controller.maint_hit_busies_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(D[3]),\n .Q(\\maint_controller.maint_hit_busies_r_reg[3]_0 [3]),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00000002)) \n \\maint_controller.maint_rdy_r1_i_1 \n (.I0(\\maint_controller.maint_rdy_r1_reg_0 ),\n .I1(D[2]),\n .I2(D[1]),\n .I3(D[0]),\n .I4(D[3]),\n .O(maint_rdy));\n FDRE \\maint_controller.maint_rdy_r1_reg \n (.C(CLK),\n .CE(1'b1),\n .D(maint_rdy),\n .Q(maint_rdy_r1),\n .R(1'b0));\n FDRE \\maint_controller.maint_srx_r1_reg \n (.C(CLK),\n .CE(1'b1),\n .D(maint_srx_r),\n .Q(maint_srx_r1),\n .R(1'b0));\n LUT4 #(\n .INIT(16'hFFBF)) \n \\maint_controller.maint_wip_r_lcl_i_1 \n (.I0(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3_n_0 ),\n .I1(Q[0]),\n .I2(Q[1]),\n .I3(Q[2]),\n .O(\\maint_controller.maint_wip_r_lcl_i_1_n_0 ));\n FDRE \\maint_controller.maint_wip_r_lcl_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\maint_controller.maint_wip_r_lcl_i_1_n_0 ),\n .Q(\\maint_controller.maint_wip_r_lcl_reg_0 ),\n .R(\\maintenance_request.maint_req_r_lcl_reg ));\n (* SOFT_HLUTNM = \"soft_lutpair1096\" *) \n LUT4 #(\n .INIT(16'h2A00)) \n periodic_rd_ack_r_lcl_i_1\n (.I0(p_9_in),\n .I1(was_wr_reg_0),\n .I2(req_periodic_rd_r_lcl_reg),\n .I3(periodic_rd_r),\n .O(periodic_rd_ack_ns));\n FDRE periodic_rd_ack_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(periodic_rd_ack_ns),\n .Q(was_wr_reg_0),\n .R(1'b0));\n FDRE periodic_rd_cntr_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\periodic_read_request.periodic_rd_r_lcl_reg ),\n .Q(req_periodic_rd_r_lcl_reg),\n .R(SR));\n LUT5 #(\n .INIT(32'h96696996)) \n \\q_entry_r[0]_i_2__2 \n (.I0(\\q_entry_r_reg[1]_0 ),\n .I1(idle_r_lcl_reg_1),\n .I2(idle_r_lcl_reg_0),\n .I3(idle_r_lcl_reg),\n .I4(E),\n .O(\\q_entry_r_reg[0]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1099\" *) \n LUT3 #(\n .INIT(8'h2A)) \n req_periodic_rd_r_lcl_i_1\n (.I0(periodic_rd_r),\n .I1(req_periodic_rd_r_lcl_reg),\n .I2(was_wr_reg_0),\n .O(periodic_rd_insert));\n (* SOFT_HLUTNM = \"soft_lutpair1095\" *) \n LUT5 #(\n .INIT(32'h11100001)) \n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[2]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__22),\n .I1(insert_maint_r1_lcl_reg),\n .I2(Q[0]),\n .I3(Q[1]),\n .I4(Q[2]),\n .O(rfc_zq_xsdll_timer_ns[2]));\n LUT6 #(\n .INIT(64'hEEEEEEEBAAAAAAAA)) \n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_1 \n (.I0(\\maintenance_request.maint_zq_r_lcl_reg ),\n .I1(Q[3]),\n .I2(Q[2]),\n .I3(Q[0]),\n .I4(Q[1]),\n .I5(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_2_n_0 ),\n .O(rfc_zq_xsdll_timer_ns[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1095\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_2 \n (.I0(insert_maint_r1_lcl_reg),\n .I1(rstdiv0_sync_r1_reg_rep__22),\n .O(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAAEEEB)) \n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[5]_i_1 \n (.I0(\\maintenance_request.maint_zq_r_lcl_reg ),\n .I1(rfc_zq_xsdll_timer_r[5]),\n .I2(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0 ),\n .I3(Q[4]),\n .I4(insert_maint_r1_lcl_reg),\n .I5(rstdiv0_sync_r1_reg_rep__22),\n .O(rfc_zq_xsdll_timer_ns[5]));\n LUT6 #(\n .INIT(64'h1111111000000001)) \n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__22),\n .I1(insert_maint_r1_lcl_reg),\n .I2(Q[4]),\n .I3(rfc_zq_xsdll_timer_r[5]),\n .I4(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0 ),\n .I5(rfc_zq_xsdll_timer_r[6]),\n .O(rfc_zq_xsdll_timer_ns[6]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1 \n (.I0(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3_n_0 ),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(Q[2]),\n .I4(insert_maint_r1_lcl_reg),\n .I5(rstdiv0_sync_r1_reg_rep__22),\n .O(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF02000202)) \n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_2 \n (.I0(rfc_zq_xsdll_timer_r[7]),\n .I1(rstdiv0_sync_r1_reg_rep__22),\n .I2(insert_maint_r1_lcl_reg),\n .I3(rfc_zq_xsdll_timer_r[6]),\n .I4(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_4_n_0 ),\n .I5(\\generate_maint_cmds.insert_maint_r_lcl_reg_0 ),\n .O(rfc_zq_xsdll_timer_ns[7]));\n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3 \n (.I0(Q[4]),\n .I1(rfc_zq_xsdll_timer_r[5]),\n .I2(rfc_zq_xsdll_timer_r[7]),\n .I3(Q[3]),\n .I4(rfc_zq_xsdll_timer_r[6]),\n .O(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000001)) \n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_4 \n (.I0(Q[4]),\n .I1(rfc_zq_xsdll_timer_r[5]),\n .I2(Q[1]),\n .I3(Q[0]),\n .I4(Q[2]),\n .I5(Q[3]),\n .O(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_4_n_0 ));\n FDRE \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] \n (.C(CLK),\n .CE(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ),\n .D(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 [0]),\n .Q(Q[0]),\n .R(1'b0));\n FDRE \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] \n (.C(CLK),\n .CE(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ),\n .D(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 [1]),\n .Q(Q[1]),\n .R(1'b0));\n FDRE \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[2] \n (.C(CLK),\n .CE(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ),\n .D(rfc_zq_xsdll_timer_ns[2]),\n .Q(Q[2]),\n .R(1'b0));\n FDRE \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] \n (.C(CLK),\n .CE(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ),\n .D(rfc_zq_xsdll_timer_ns[3]),\n .Q(Q[3]),\n .R(1'b0));\n FDRE \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] \n (.C(CLK),\n .CE(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ),\n .D(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 [2]),\n .Q(Q[4]),\n .R(1'b0));\n FDRE \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] \n (.C(CLK),\n .CE(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ),\n .D(rfc_zq_xsdll_timer_ns[5]),\n .Q(rfc_zq_xsdll_timer_r[5]),\n .R(1'b0));\n FDRE \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6] \n (.C(CLK),\n .CE(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ),\n .D(rfc_zq_xsdll_timer_ns[6]),\n .Q(rfc_zq_xsdll_timer_r[6]),\n .R(1'b0));\n FDRE \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] \n (.C(CLK),\n .CE(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ),\n .D(rfc_zq_xsdll_timer_ns[7]),\n .Q(rfc_zq_xsdll_timer_r[7]),\n .R(1'b0));\n LUT3 #(\n .INIT(8'h8A)) \n was_wr_i_1\n (.I0(\\app_cmd_r1_reg[0] ),\n .I1(was_wr_reg_0),\n .I2(periodic_rd_r),\n .O(was_wr0));\n FDRE was_wr_reg\n (.C(CLK),\n .CE(1'b1),\n .D(was_wr0),\n .Q(was_wr),\n .R(1'b0));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_bank_compare\n (req_periodic_rd_r,\n \\rd_this_rank_r_reg[0] ,\n bm_end_r1_reg,\n req_priority_r,\n q_has_priority_r_reg,\n row_hit_r_12,\n granted_col_r_reg,\n \\grant_r_reg[3] ,\n \\grant_r_reg[3]_0 ,\n ras_timer_zero_r_reg,\n \\ras_timer_r_reg[0] ,\n \\grant_r_reg[1] ,\n pass_open_bank_ns,\n p_13_out,\n start_wtp_timer0,\n \\cmd_pipe_plus.mc_address_reg[44] ,\n \\col_mux.col_data_buf_addr_r_reg[4] ,\n \\cmd_pipe_plus.mc_bank_reg[8] ,\n \\cmd_pipe_plus.mc_address_reg[24] ,\n E,\n periodic_rd_insert,\n CLK,\n hi_priority,\n p_28_out,\n rd_wr_r_lcl_reg_0,\n \\rtw_timer.rtw_cnt_r_reg[1] ,\n \\wtr_timer.wtr_cnt_r_reg[1] ,\n demand_priority_r_reg,\n col_wait_r_reg,\n rd_wr_r_lcl_reg_1,\n order_q_r,\n \\grant_r_reg[3]_1 ,\n rd_wr_r,\n req_wr_r,\n \\app_cmd_r2_reg[1] ,\n \\app_cmd_r1_reg[0] ,\n idle_r_lcl_reg,\n periodic_rd_ack_r_lcl_reg,\n periodic_rd_cntr_r_reg,\n periodic_rd_r,\n periodic_rd_ack_r_lcl_reg_0,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ,\n pass_open_bank_r_lcl_reg,\n pre_passing_open_bank_r,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ,\n req_wr_r_lcl_reg_0,\n tail_r_28,\n rb_hit_busy_r_reg_0,\n pre_wait_r,\n pre_bm_end_r_15,\n maint_req_r,\n \\maint_controller.maint_wip_r_lcl_reg ,\n wait_for_maint_r_20,\n \\app_addr_r1_reg[27] ,\n idle_r_lcl_reg_0,\n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ,\n \\app_addr_r1_reg[12] ,\n \\app_addr_r1_reg[9] );\n output [0:0]req_periodic_rd_r;\n output \\rd_this_rank_r_reg[0] ;\n output bm_end_r1_reg;\n output req_priority_r;\n output q_has_priority_r_reg;\n output row_hit_r_12;\n output granted_col_r_reg;\n output \\grant_r_reg[3] ;\n output \\grant_r_reg[3]_0 ;\n output ras_timer_zero_r_reg;\n output \\ras_timer_r_reg[0] ;\n output \\grant_r_reg[1] ;\n output pass_open_bank_ns;\n output p_13_out;\n output start_wtp_timer0;\n output [14:0]\\cmd_pipe_plus.mc_address_reg[44] ;\n output [4:0]\\col_mux.col_data_buf_addr_r_reg[4] ;\n output [2:0]\\cmd_pipe_plus.mc_bank_reg[8] ;\n output [6:0]\\cmd_pipe_plus.mc_address_reg[24] ;\n input [0:0]E;\n input periodic_rd_insert;\n input CLK;\n input hi_priority;\n input p_28_out;\n input rd_wr_r_lcl_reg_0;\n input \\rtw_timer.rtw_cnt_r_reg[1] ;\n input \\wtr_timer.wtr_cnt_r_reg[1] ;\n input demand_priority_r_reg;\n input col_wait_r_reg;\n input rd_wr_r_lcl_reg_1;\n input [1:0]order_q_r;\n input [1:0]\\grant_r_reg[3]_1 ;\n input [0:0]rd_wr_r;\n input [0:0]req_wr_r;\n input [0:0]\\app_cmd_r2_reg[1] ;\n input \\app_cmd_r1_reg[0] ;\n input idle_r_lcl_reg;\n input periodic_rd_ack_r_lcl_reg;\n input periodic_rd_cntr_r_reg;\n input periodic_rd_r;\n input periodic_rd_ack_r_lcl_reg_0;\n input [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;\n input pass_open_bank_r_lcl_reg;\n input pre_passing_open_bank_r;\n input [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;\n input req_wr_r_lcl_reg_0;\n input tail_r_28;\n input rb_hit_busy_r_reg_0;\n input pre_wait_r;\n input pre_bm_end_r_15;\n input maint_req_r;\n input \\maint_controller.maint_wip_r_lcl_reg ;\n input wait_for_maint_r_20;\n input [14:0]\\app_addr_r1_reg[27] ;\n input idle_r_lcl_reg_0;\n input [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n input [2:0]\\app_addr_r1_reg[12] ;\n input [6:0]\\app_addr_r1_reg[9] ;\n\n wire CLK;\n wire [0:0]E;\n wire [2:0]\\app_addr_r1_reg[12] ;\n wire [14:0]\\app_addr_r1_reg[27] ;\n wire [6:0]\\app_addr_r1_reg[9] ;\n wire \\app_cmd_r1_reg[0] ;\n wire [0:0]\\app_cmd_r2_reg[1] ;\n wire bm_end_r1_reg;\n wire [6:0]\\cmd_pipe_plus.mc_address_reg[24] ;\n wire [14:0]\\cmd_pipe_plus.mc_address_reg[44] ;\n wire [2:0]\\cmd_pipe_plus.mc_bank_reg[8] ;\n wire [4:0]\\col_mux.col_data_buf_addr_r_reg[4] ;\n wire col_wait_r_reg;\n wire demand_priority_r_reg;\n wire \\grant_r[3]_i_11_n_0 ;\n wire \\grant_r_reg[1] ;\n wire \\grant_r_reg[3] ;\n wire \\grant_r_reg[3]_0 ;\n wire [1:0]\\grant_r_reg[3]_1 ;\n wire granted_col_r_reg;\n wire hi_priority;\n wire idle_r_lcl_reg;\n wire idle_r_lcl_reg_0;\n wire \\maint_controller.maint_wip_r_lcl_reg ;\n wire maint_req_r;\n wire [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n wire [1:0]order_q_r;\n wire p_13_out;\n wire p_28_out;\n wire pass_open_bank_ns;\n wire pass_open_bank_r_lcl_i_2__2_n_0;\n wire pass_open_bank_r_lcl_reg;\n wire periodic_rd_ack_r_lcl_reg;\n wire periodic_rd_ack_r_lcl_reg_0;\n wire periodic_rd_cntr_r_reg;\n wire periodic_rd_insert;\n wire periodic_rd_r;\n wire pre_bm_end_r_15;\n wire pre_passing_open_bank_r;\n wire pre_wait_r;\n wire q_has_priority_r_reg;\n wire \\ras_timer_r_reg[0] ;\n wire ras_timer_zero_r_reg;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;\n wire rb_hit_busy_r_reg_0;\n wire \\rd_this_rank_r_reg[0] ;\n wire rd_wr_ns;\n wire [0:0]rd_wr_r;\n wire rd_wr_r_lcl_reg_0;\n wire rd_wr_r_lcl_reg_1;\n wire [1:0]req_cmd_r;\n wire \\req_cmd_r[0]_i_1__1_n_0 ;\n wire \\req_cmd_r[1]_i_1__1_n_0 ;\n wire [0:0]req_periodic_rd_r;\n wire req_priority_r;\n wire [0:0]req_wr_r;\n wire req_wr_r_lcl0;\n wire req_wr_r_lcl_reg_0;\n wire row_hit_ns;\n wire row_hit_ns_carry__0_i_1__2_n_0;\n wire row_hit_ns_carry_i_1__2_n_0;\n wire row_hit_ns_carry_i_2__2_n_0;\n wire row_hit_ns_carry_i_3__2_n_0;\n wire row_hit_ns_carry_i_4__2_n_0;\n wire row_hit_ns_carry_n_0;\n wire row_hit_ns_carry_n_1;\n wire row_hit_ns_carry_n_2;\n wire row_hit_ns_carry_n_3;\n wire row_hit_r_12;\n wire \\rtw_timer.rtw_cnt_r_reg[1] ;\n wire start_wtp_timer0;\n wire tail_r_28;\n wire wait_for_maint_r_20;\n wire \\wtr_timer.wtr_cnt_r_reg[1] ;\n wire [3:0]NLW_row_hit_ns_carry_O_UNCONNECTED;\n wire [3:1]NLW_row_hit_ns_carry__0_CO_UNCONNECTED;\n wire [3:0]NLW_row_hit_ns_carry__0_O_UNCONNECTED;\n\n (* SOFT_HLUTNM = \"soft_lutpair1087\" *) \n LUT5 #(\n .INIT(32'hFFFF7000)) \n bm_end_r1_i_1__1\n (.I0(bm_end_r1_reg),\n .I1(\\rd_this_rank_r_reg[0] ),\n .I2(pass_open_bank_r_lcl_reg),\n .I3(\\grant_r_reg[3]_1 [1]),\n .I4(pre_bm_end_r_15),\n .O(p_13_out));\n LUT2 #(\n .INIT(4'h2)) \n \\grant_r[1]_i_2 \n (.I0(\\grant_r_reg[3] ),\n .I1(rd_wr_r_lcl_reg_0),\n .O(granted_col_r_reg));\n (* SOFT_HLUTNM = \"soft_lutpair1086\" *) \n LUT5 #(\n .INIT(32'h0000FF20)) \n \\grant_r[3]_i_11 \n (.I0(\\grant_r_reg[3]_0 ),\n .I1(rd_wr_r_lcl_reg_1),\n .I2(order_q_r[0]),\n .I3(order_q_r[1]),\n .I4(\\rd_this_rank_r_reg[0] ),\n .O(\\grant_r[3]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'hDF00DFDFDFDFDFDF)) \n \\grant_r[3]_i_13 \n (.I0(bm_end_r1_reg),\n .I1(\\rd_this_rank_r_reg[0] ),\n .I2(\\grant_r_reg[3]_1 [1]),\n .I3(rd_wr_r),\n .I4(\\grant_r_reg[3]_1 [0]),\n .I5(req_wr_r),\n .O(\\grant_r_reg[3]_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFF35)) \n \\grant_r[3]_i_5 \n (.I0(\\rtw_timer.rtw_cnt_r_reg[1] ),\n .I1(\\wtr_timer.wtr_cnt_r_reg[1] ),\n .I2(\\rd_this_rank_r_reg[0] ),\n .I3(demand_priority_r_reg),\n .I4(\\grant_r[3]_i_11_n_0 ),\n .I5(col_wait_r_reg),\n .O(\\grant_r_reg[3] ));\n LUT6 #(\n .INIT(64'hAAAAAAAA2A000000)) \n i___36_i_2\n (.I0(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ),\n .I1(bm_end_r1_reg),\n .I2(\\rd_this_rank_r_reg[0] ),\n .I3(pass_open_bank_r_lcl_reg),\n .I4(\\grant_r_reg[3]_1 [1]),\n .I5(pre_passing_open_bank_r),\n .O(\\ras_timer_r_reg[0] ));\n LUT6 #(\n .INIT(64'hAAAAAAAA2A000000)) \n i___37_i_3\n (.I0(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ),\n .I1(bm_end_r1_reg),\n .I2(\\rd_this_rank_r_reg[0] ),\n .I3(pass_open_bank_r_lcl_reg),\n .I4(\\grant_r_reg[3]_1 [1]),\n .I5(pre_passing_open_bank_r),\n .O(\\grant_r_reg[1] ));\n LUT6 #(\n .INIT(64'h4444544444444444)) \n pass_open_bank_r_lcl_i_1__1\n (.I0(req_wr_r_lcl_reg_0),\n .I1(pass_open_bank_r_lcl_reg),\n .I2(tail_r_28),\n .I3(rb_hit_busy_r_reg_0),\n .I4(pre_wait_r),\n .I5(pass_open_bank_r_lcl_i_2__2_n_0),\n .O(pass_open_bank_ns));\n LUT5 #(\n .INIT(32'hAAAA00A2)) \n pass_open_bank_r_lcl_i_2__2\n (.I0(row_hit_r_12),\n .I1(maint_req_r),\n .I2(periodic_rd_cntr_r_reg),\n .I3(\\maint_controller.maint_wip_r_lcl_reg ),\n .I4(wait_for_maint_r_20),\n .O(pass_open_bank_r_lcl_i_2__2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1087\" *) \n LUT2 #(\n .INIT(4'hB)) \n ras_timer_zero_r_i_2__0\n (.I0(\\rd_this_rank_r_reg[0] ),\n .I1(\\grant_r_reg[3]_1 [1]),\n .O(ras_timer_zero_r_reg));\n FDRE rb_hit_busy_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(p_28_out),\n .Q(q_has_priority_r_reg),\n .R(1'b0));\n LUT4 #(\n .INIT(16'h2F20)) \n rd_wr_r_lcl_i_1__1\n (.I0(\\rd_this_rank_r_reg[0] ),\n .I1(\\grant_r_reg[3]_1 [1]),\n .I2(idle_r_lcl_reg),\n .I3(periodic_rd_ack_r_lcl_reg_0),\n .O(rd_wr_ns));\n FDRE rd_wr_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rd_wr_ns),\n .Q(\\rd_this_rank_r_reg[0] ),\n .R(1'b0));\n FDRE \\req_bank_r_lcl_reg[0] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[12] [0]),\n .Q(\\cmd_pipe_plus.mc_bank_reg[8] [0]),\n .R(1'b0));\n FDRE \\req_bank_r_lcl_reg[1] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[12] [1]),\n .Q(\\cmd_pipe_plus.mc_bank_reg[8] [1]),\n .R(1'b0));\n FDRE \\req_bank_r_lcl_reg[2] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[12] [2]),\n .Q(\\cmd_pipe_plus.mc_bank_reg[8] [2]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hB8BBBBBBB8B8B8B8)) \n \\req_cmd_r[0]_i_1__1 \n (.I0(req_cmd_r[0]),\n .I1(idle_r_lcl_reg),\n .I2(\\app_cmd_r1_reg[0] ),\n .I3(periodic_rd_ack_r_lcl_reg),\n .I4(periodic_rd_cntr_r_reg),\n .I5(periodic_rd_r),\n .O(\\req_cmd_r[0]_i_1__1_n_0 ));\n LUT6 #(\n .INIT(64'hB8888888B8B8B8B8)) \n \\req_cmd_r[1]_i_1__1 \n (.I0(req_cmd_r[1]),\n .I1(idle_r_lcl_reg),\n .I2(\\app_cmd_r2_reg[1] ),\n .I3(periodic_rd_ack_r_lcl_reg),\n .I4(periodic_rd_cntr_r_reg),\n .I5(periodic_rd_r),\n .O(\\req_cmd_r[1]_i_1__1_n_0 ));\n FDRE \\req_cmd_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\req_cmd_r[0]_i_1__1_n_0 ),\n .Q(req_cmd_r[0]),\n .R(1'b0));\n FDRE \\req_cmd_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\req_cmd_r[1]_i_1__1_n_0 ),\n .Q(req_cmd_r[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[3] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[9] [0]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[4] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[9] [1]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[5] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[9] [2]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[6] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[9] [3]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[7] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[9] [4]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[8] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[9] [5]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[9] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[9] [6]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [6]),\n .R(1'b0));\n FDRE \\req_data_buf_addr_r_reg[0] \n (.C(CLK),\n .CE(idle_r_lcl_reg_0),\n .D(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [0]),\n .Q(\\col_mux.col_data_buf_addr_r_reg[4] [0]),\n .R(1'b0));\n FDRE \\req_data_buf_addr_r_reg[1] \n (.C(CLK),\n .CE(idle_r_lcl_reg_0),\n .D(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [1]),\n .Q(\\col_mux.col_data_buf_addr_r_reg[4] [1]),\n .R(1'b0));\n FDRE \\req_data_buf_addr_r_reg[2] \n (.C(CLK),\n .CE(idle_r_lcl_reg_0),\n .D(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [2]),\n .Q(\\col_mux.col_data_buf_addr_r_reg[4] [2]),\n .R(1'b0));\n FDRE \\req_data_buf_addr_r_reg[3] \n (.C(CLK),\n .CE(idle_r_lcl_reg_0),\n .D(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [3]),\n .Q(\\col_mux.col_data_buf_addr_r_reg[4] [3]),\n .R(1'b0));\n FDRE \\req_data_buf_addr_r_reg[4] \n (.C(CLK),\n .CE(idle_r_lcl_reg_0),\n .D(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [4]),\n .Q(\\col_mux.col_data_buf_addr_r_reg[4] [4]),\n .R(1'b0));\n FDRE req_periodic_rd_r_lcl_reg\n (.C(CLK),\n .CE(E),\n .D(periodic_rd_insert),\n .Q(req_periodic_rd_r),\n .R(1'b0));\n FDRE req_priority_r_reg\n (.C(CLK),\n .CE(E),\n .D(hi_priority),\n .Q(req_priority_r),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[0] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [0]),\n .Q(\\cmd_pipe_plus.mc_address_reg[44] [0]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[10] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [10]),\n .Q(\\cmd_pipe_plus.mc_address_reg[44] [10]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[11] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [11]),\n .Q(\\cmd_pipe_plus.mc_address_reg[44] [11]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[12] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [12]),\n .Q(\\cmd_pipe_plus.mc_address_reg[44] [12]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[13] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [13]),\n .Q(\\cmd_pipe_plus.mc_address_reg[44] [13]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[14] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [14]),\n .Q(\\cmd_pipe_plus.mc_address_reg[44] [14]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[1] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [1]),\n .Q(\\cmd_pipe_plus.mc_address_reg[44] [1]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[2] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [2]),\n .Q(\\cmd_pipe_plus.mc_address_reg[44] [2]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[3] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [3]),\n .Q(\\cmd_pipe_plus.mc_address_reg[44] [3]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[4] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [4]),\n .Q(\\cmd_pipe_plus.mc_address_reg[44] [4]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[5] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [5]),\n .Q(\\cmd_pipe_plus.mc_address_reg[44] [5]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[6] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [6]),\n .Q(\\cmd_pipe_plus.mc_address_reg[44] [6]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[7] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [7]),\n .Q(\\cmd_pipe_plus.mc_address_reg[44] [7]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[8] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [8]),\n .Q(\\cmd_pipe_plus.mc_address_reg[44] [8]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[9] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [9]),\n .Q(\\cmd_pipe_plus.mc_address_reg[44] [9]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hCCCC0A0FFFFF0A0F)) \n req_wr_r_lcl_i_1__1\n (.I0(\\app_cmd_r2_reg[1] ),\n .I1(req_cmd_r[1]),\n .I2(periodic_rd_insert),\n .I3(\\app_cmd_r1_reg[0] ),\n .I4(idle_r_lcl_reg),\n .I5(req_cmd_r[0]),\n .O(req_wr_r_lcl0));\n FDRE req_wr_r_lcl_reg\n (.C(CLK),\n .CE(E),\n .D(req_wr_r_lcl0),\n .Q(bm_end_r1_reg),\n .R(1'b0));\n CARRY4 row_hit_ns_carry\n (.CI(1'b0),\n .CO({row_hit_ns_carry_n_0,row_hit_ns_carry_n_1,row_hit_ns_carry_n_2,row_hit_ns_carry_n_3}),\n .CYINIT(1'b1),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(NLW_row_hit_ns_carry_O_UNCONNECTED[3:0]),\n .S({row_hit_ns_carry_i_1__2_n_0,row_hit_ns_carry_i_2__2_n_0,row_hit_ns_carry_i_3__2_n_0,row_hit_ns_carry_i_4__2_n_0}));\n CARRY4 row_hit_ns_carry__0\n (.CI(row_hit_ns_carry_n_0),\n .CO({NLW_row_hit_ns_carry__0_CO_UNCONNECTED[3:1],row_hit_ns}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(NLW_row_hit_ns_carry__0_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,1'b0,row_hit_ns_carry__0_i_1__2_n_0}));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n row_hit_ns_carry__0_i_1__2\n (.I0(\\cmd_pipe_plus.mc_address_reg[44] [14]),\n .I1(\\app_addr_r1_reg[27] [14]),\n .I2(\\cmd_pipe_plus.mc_address_reg[44] [13]),\n .I3(\\app_addr_r1_reg[27] [13]),\n .I4(\\app_addr_r1_reg[27] [12]),\n .I5(\\cmd_pipe_plus.mc_address_reg[44] [12]),\n .O(row_hit_ns_carry__0_i_1__2_n_0));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n row_hit_ns_carry_i_1__2\n (.I0(\\cmd_pipe_plus.mc_address_reg[44] [11]),\n .I1(\\app_addr_r1_reg[27] [11]),\n .I2(\\cmd_pipe_plus.mc_address_reg[44] [10]),\n .I3(\\app_addr_r1_reg[27] [10]),\n .I4(\\app_addr_r1_reg[27] [9]),\n .I5(\\cmd_pipe_plus.mc_address_reg[44] [9]),\n .O(row_hit_ns_carry_i_1__2_n_0));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n row_hit_ns_carry_i_2__2\n (.I0(\\cmd_pipe_plus.mc_address_reg[44] [8]),\n .I1(\\app_addr_r1_reg[27] [8]),\n .I2(\\cmd_pipe_plus.mc_address_reg[44] [7]),\n .I3(\\app_addr_r1_reg[27] [7]),\n .I4(\\app_addr_r1_reg[27] [6]),\n .I5(\\cmd_pipe_plus.mc_address_reg[44] [6]),\n .O(row_hit_ns_carry_i_2__2_n_0));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n row_hit_ns_carry_i_3__2\n (.I0(\\cmd_pipe_plus.mc_address_reg[44] [5]),\n .I1(\\app_addr_r1_reg[27] [5]),\n .I2(\\cmd_pipe_plus.mc_address_reg[44] [3]),\n .I3(\\app_addr_r1_reg[27] [3]),\n .I4(\\app_addr_r1_reg[27] [4]),\n .I5(\\cmd_pipe_plus.mc_address_reg[44] [4]),\n .O(row_hit_ns_carry_i_3__2_n_0));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n row_hit_ns_carry_i_4__2\n (.I0(\\cmd_pipe_plus.mc_address_reg[44] [2]),\n .I1(\\app_addr_r1_reg[27] [2]),\n .I2(\\cmd_pipe_plus.mc_address_reg[44] [1]),\n .I3(\\app_addr_r1_reg[27] [1]),\n .I4(\\app_addr_r1_reg[27] [0]),\n .I5(\\cmd_pipe_plus.mc_address_reg[44] [0]),\n .O(row_hit_ns_carry_i_4__2_n_0));\n FDRE row_hit_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(row_hit_ns),\n .Q(row_hit_r_12),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1086\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\wr_this_rank_r[0]_i_1__2 \n (.I0(\\rd_this_rank_r_reg[0] ),\n .O(start_wtp_timer0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_bank_compare\" *) \nmodule ddr3_if_mig_7series_v4_0_bank_compare_0\n (req_periodic_rd_r,\n \\rd_this_rank_r_reg[0] ,\n bm_end_r1_reg,\n q_has_priority_r_reg,\n row_hit_r_5,\n \\order_q_r_reg[0] ,\n req_bank_rdy_r_reg,\n \\order_q_r_reg[1] ,\n demand_priority_r_reg,\n req_bank_rdy_ns,\n ras_timer_zero_r_reg,\n \\ras_timer_r_reg[0] ,\n \\grant_r_reg[1] ,\n \\grant_r_reg[3] ,\n pass_open_bank_ns,\n p_52_out,\n start_wtp_timer0,\n \\cmd_pipe_plus.mc_address_reg[44] ,\n \\cmd_pipe_plus.mc_address_reg[40] ,\n \\col_mux.col_data_buf_addr_r_reg[4] ,\n \\cmd_pipe_plus.mc_bank_reg[8] ,\n \\cmd_pipe_plus.mc_address_reg[24] ,\n E,\n periodic_rd_insert,\n CLK,\n hi_priority,\n p_67_out,\n ordered_r_lcl_reg,\n ordered_r,\n q_has_priority_11,\n order_q_r,\n col_wait_r_reg,\n \\grant_r_reg[3]_0 ,\n rd_wr_r_lcl_reg_0,\n req_wr_r_lcl_reg_0,\n rd_wr_r_lcl_reg_1,\n \\app_cmd_r2_reg[1] ,\n \\app_cmd_r1_reg[0] ,\n idle_r_lcl_reg,\n periodic_rd_ack_r_lcl_reg,\n periodic_rd_cntr_r_reg,\n periodic_rd_r,\n periodic_rd_ack_r_lcl_reg_0,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ,\n pass_open_bank_r_lcl_reg,\n pre_passing_open_bank_r,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ,\n Q,\n req_wr_r_lcl_reg_1,\n tail_r_26,\n rb_hit_busy_r_reg_0,\n pre_wait_r,\n pre_bm_end_r_9,\n maint_req_r,\n \\maint_controller.maint_wip_r_lcl_reg ,\n wait_for_maint_r_19,\n \\app_addr_r1_reg[27] ,\n \\req_row_r_lcl_reg[10]_0 ,\n act_wait_r_lcl_reg,\n \\grant_r_reg[3]_1 ,\n act_wait_r_lcl_reg_0,\n idle_r_lcl_reg_0,\n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ,\n \\app_addr_r1_reg[12] ,\n \\app_addr_r1_reg[9] );\n output [0:0]req_periodic_rd_r;\n output \\rd_this_rank_r_reg[0] ;\n output bm_end_r1_reg;\n output q_has_priority_r_reg;\n output row_hit_r_5;\n output \\order_q_r_reg[0] ;\n output req_bank_rdy_r_reg;\n output \\order_q_r_reg[1] ;\n output demand_priority_r_reg;\n output req_bank_rdy_ns;\n output ras_timer_zero_r_reg;\n output \\ras_timer_r_reg[0] ;\n output \\grant_r_reg[1] ;\n output \\grant_r_reg[3] ;\n output pass_open_bank_ns;\n output p_52_out;\n output start_wtp_timer0;\n output [14:0]\\cmd_pipe_plus.mc_address_reg[44] ;\n output [0:0]\\cmd_pipe_plus.mc_address_reg[40] ;\n output [4:0]\\col_mux.col_data_buf_addr_r_reg[4] ;\n output [2:0]\\cmd_pipe_plus.mc_bank_reg[8] ;\n output [6:0]\\cmd_pipe_plus.mc_address_reg[24] ;\n input [0:0]E;\n input periodic_rd_insert;\n input CLK;\n input hi_priority;\n input p_67_out;\n input [2:0]ordered_r_lcl_reg;\n input [0:0]ordered_r;\n input q_has_priority_11;\n input [1:0]order_q_r;\n input col_wait_r_reg;\n input [1:0]\\grant_r_reg[3]_0 ;\n input rd_wr_r_lcl_reg_0;\n input req_wr_r_lcl_reg_0;\n input rd_wr_r_lcl_reg_1;\n input [0:0]\\app_cmd_r2_reg[1] ;\n input \\app_cmd_r1_reg[0] ;\n input idle_r_lcl_reg;\n input periodic_rd_ack_r_lcl_reg;\n input periodic_rd_cntr_r_reg;\n input periodic_rd_r;\n input periodic_rd_ack_r_lcl_reg_0;\n input [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ;\n input pass_open_bank_r_lcl_reg;\n input pre_passing_open_bank_r;\n input [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ;\n input [0:0]Q;\n input req_wr_r_lcl_reg_1;\n input tail_r_26;\n input rb_hit_busy_r_reg_0;\n input pre_wait_r;\n input pre_bm_end_r_9;\n input maint_req_r;\n input \\maint_controller.maint_wip_r_lcl_reg ;\n input wait_for_maint_r_19;\n input [14:0]\\app_addr_r1_reg[27] ;\n input \\req_row_r_lcl_reg[10]_0 ;\n input act_wait_r_lcl_reg;\n input [1:0]\\grant_r_reg[3]_1 ;\n input act_wait_r_lcl_reg_0;\n input idle_r_lcl_reg_0;\n input [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n input [2:0]\\app_addr_r1_reg[12] ;\n input [6:0]\\app_addr_r1_reg[9] ;\n\n wire CLK;\n wire [0:0]E;\n wire [0:0]Q;\n wire act_wait_r_lcl_reg;\n wire act_wait_r_lcl_reg_0;\n wire [2:0]\\app_addr_r1_reg[12] ;\n wire [14:0]\\app_addr_r1_reg[27] ;\n wire [6:0]\\app_addr_r1_reg[9] ;\n wire \\app_cmd_r1_reg[0] ;\n wire [0:0]\\app_cmd_r2_reg[1] ;\n wire bm_end_r1_reg;\n wire [6:0]\\cmd_pipe_plus.mc_address_reg[24] ;\n wire [0:0]\\cmd_pipe_plus.mc_address_reg[40] ;\n wire [14:0]\\cmd_pipe_plus.mc_address_reg[44] ;\n wire [2:0]\\cmd_pipe_plus.mc_bank_reg[8] ;\n wire [4:0]\\col_mux.col_data_buf_addr_r_reg[4] ;\n wire col_wait_r_reg;\n wire demand_priority_r_reg;\n wire \\grant_r_reg[1] ;\n wire \\grant_r_reg[3] ;\n wire [1:0]\\grant_r_reg[3]_0 ;\n wire [1:0]\\grant_r_reg[3]_1 ;\n wire hi_priority;\n wire idle_r_lcl_reg;\n wire idle_r_lcl_reg_0;\n wire \\maint_controller.maint_wip_r_lcl_reg ;\n wire maint_req_r;\n wire [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n wire [1:0]order_q_r;\n wire \\order_q_r_reg[0] ;\n wire \\order_q_r_reg[1] ;\n wire [0:0]ordered_r;\n wire [2:0]ordered_r_lcl_reg;\n wire p_52_out;\n wire p_67_out;\n wire pass_open_bank_ns;\n wire pass_open_bank_r_lcl_i_2__1_n_0;\n wire pass_open_bank_r_lcl_reg;\n wire periodic_rd_ack_r_lcl_reg;\n wire periodic_rd_ack_r_lcl_reg_0;\n wire periodic_rd_cntr_r_reg;\n wire periodic_rd_insert;\n wire periodic_rd_r;\n wire pre_bm_end_r_9;\n wire pre_passing_open_bank_r;\n wire pre_wait_r;\n wire q_has_priority_11;\n wire q_has_priority_r_reg;\n wire \\ras_timer_r_reg[0] ;\n wire ras_timer_zero_r_reg;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ;\n wire rb_hit_busy_r_reg_0;\n wire \\rd_this_rank_r_reg[0] ;\n wire rd_wr_ns;\n wire rd_wr_r_lcl_reg_0;\n wire rd_wr_r_lcl_reg_1;\n wire req_bank_rdy_ns;\n wire req_bank_rdy_r_reg;\n wire [1:0]req_cmd_r;\n wire \\req_cmd_r[0]_i_1__0_n_0 ;\n wire \\req_cmd_r[1]_i_1__0_n_0 ;\n wire [0:0]req_periodic_rd_r;\n wire req_priority_r;\n wire \\req_row_r_lcl_reg[10]_0 ;\n wire req_wr_r_lcl0;\n wire req_wr_r_lcl_reg_0;\n wire req_wr_r_lcl_reg_1;\n wire row_hit_ns;\n wire row_hit_ns_carry__0_i_1__1_n_0;\n wire row_hit_ns_carry_i_1__1_n_0;\n wire row_hit_ns_carry_i_2__1_n_0;\n wire row_hit_ns_carry_i_3__1_n_0;\n wire row_hit_ns_carry_i_4__1_n_0;\n wire row_hit_ns_carry_n_0;\n wire row_hit_ns_carry_n_1;\n wire row_hit_ns_carry_n_2;\n wire row_hit_ns_carry_n_3;\n wire row_hit_r_5;\n wire start_wtp_timer0;\n wire tail_r_26;\n wire wait_for_maint_r_19;\n wire [3:0]NLW_row_hit_ns_carry_O_UNCONNECTED;\n wire [3:1]NLW_row_hit_ns_carry__0_CO_UNCONNECTED;\n wire [3:0]NLW_row_hit_ns_carry__0_O_UNCONNECTED;\n\n (* SOFT_HLUTNM = \"soft_lutpair1078\" *) \n LUT5 #(\n .INIT(32'hFFFF7000)) \n bm_end_r1_i_1__2\n (.I0(bm_end_r1_reg),\n .I1(\\rd_this_rank_r_reg[0] ),\n .I2(pass_open_bank_r_lcl_reg),\n .I3(\\grant_r_reg[3]_0 [0]),\n .I4(pre_bm_end_r_9),\n .O(p_52_out));\n LUT6 #(\n .INIT(64'hCCFCCCDDCCCCCCDD)) \n \\cmd_pipe_plus.mc_address[40]_i_1 \n (.I0(\\req_row_r_lcl_reg[10]_0 ),\n .I1(act_wait_r_lcl_reg),\n .I2(\\cmd_pipe_plus.mc_address_reg[44] [10]),\n .I3(\\grant_r_reg[3]_1 [1]),\n .I4(\\grant_r_reg[3]_1 [0]),\n .I5(act_wait_r_lcl_reg_0),\n .O(\\cmd_pipe_plus.mc_address_reg[40] ));\n LUT6 #(\n .INIT(64'hE0E0E0EEE0EEE0EE)) \n demand_priority_r_i_3\n (.I0(req_priority_r),\n .I1(q_has_priority_11),\n .I2(\\rd_this_rank_r_reg[0] ),\n .I3(order_q_r[1]),\n .I4(order_q_r[0]),\n .I5(req_bank_rdy_r_reg),\n .O(demand_priority_r_reg));\n LUT6 #(\n .INIT(64'hAAAAAAAA2A000000)) \n i___37_i_2\n (.I0(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ),\n .I1(bm_end_r1_reg),\n .I2(\\rd_this_rank_r_reg[0] ),\n .I3(pass_open_bank_r_lcl_reg),\n .I4(\\grant_r_reg[3]_0 [0]),\n .I5(pre_passing_open_bank_r),\n .O(\\ras_timer_r_reg[0] ));\n LUT6 #(\n .INIT(64'hAAAAAAAA2A000000)) \n i___38_i_2\n (.I0(Q),\n .I1(bm_end_r1_reg),\n .I2(\\rd_this_rank_r_reg[0] ),\n .I3(pass_open_bank_r_lcl_reg),\n .I4(\\grant_r_reg[3]_0 [0]),\n .I5(pre_passing_open_bank_r),\n .O(\\grant_r_reg[3] ));\n LUT6 #(\n .INIT(64'hAAAAAAAA2A000000)) \n i___56_i_4\n (.I0(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ),\n .I1(bm_end_r1_reg),\n .I2(\\rd_this_rank_r_reg[0] ),\n .I3(pass_open_bank_r_lcl_reg),\n .I4(\\grant_r_reg[3]_0 [0]),\n .I5(pre_passing_open_bank_r),\n .O(\\grant_r_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair1076\" *) \n LUT5 #(\n .INIT(32'h96696996)) \n \\order_q_r[0]_i_2 \n (.I0(req_bank_rdy_r_reg),\n .I1(ordered_r_lcl_reg[2]),\n .I2(ordered_r),\n .I3(ordered_r_lcl_reg[1]),\n .I4(ordered_r_lcl_reg[0]),\n .O(\\order_q_r_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair1076\" *) \n LUT5 #(\n .INIT(32'h7EE8E881)) \n \\order_q_r[1]_i_2 \n (.I0(req_bank_rdy_r_reg),\n .I1(ordered_r_lcl_reg[0]),\n .I2(ordered_r_lcl_reg[1]),\n .I3(ordered_r),\n .I4(ordered_r_lcl_reg[2]),\n .O(\\order_q_r_reg[1] ));\n LUT6 #(\n .INIT(64'h4444544444444444)) \n pass_open_bank_r_lcl_i_1__2\n (.I0(req_wr_r_lcl_reg_1),\n .I1(pass_open_bank_r_lcl_reg),\n .I2(tail_r_26),\n .I3(rb_hit_busy_r_reg_0),\n .I4(pre_wait_r),\n .I5(pass_open_bank_r_lcl_i_2__1_n_0),\n .O(pass_open_bank_ns));\n LUT5 #(\n .INIT(32'hAAAA00A2)) \n pass_open_bank_r_lcl_i_2__1\n (.I0(row_hit_r_5),\n .I1(maint_req_r),\n .I2(periodic_rd_cntr_r_reg),\n .I3(\\maint_controller.maint_wip_r_lcl_reg ),\n .I4(wait_for_maint_r_19),\n .O(pass_open_bank_r_lcl_i_2__1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1078\" *) \n LUT2 #(\n .INIT(4'hB)) \n ras_timer_zero_r_i_2\n (.I0(\\rd_this_rank_r_reg[0] ),\n .I1(\\grant_r_reg[3]_0 [0]),\n .O(ras_timer_zero_r_reg));\n FDRE rb_hit_busy_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(p_67_out),\n .Q(q_has_priority_r_reg),\n .R(1'b0));\n LUT4 #(\n .INIT(16'h2F20)) \n rd_wr_r_lcl_i_1__0\n (.I0(\\rd_this_rank_r_reg[0] ),\n .I1(\\grant_r_reg[3]_0 [0]),\n .I2(idle_r_lcl_reg),\n .I3(periodic_rd_ack_r_lcl_reg_0),\n .O(rd_wr_ns));\n FDRE rd_wr_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rd_wr_ns),\n .Q(\\rd_this_rank_r_reg[0] ),\n .R(1'b0));\n FDRE \\req_bank_r_lcl_reg[0] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[12] [0]),\n .Q(\\cmd_pipe_plus.mc_bank_reg[8] [0]),\n .R(1'b0));\n FDRE \\req_bank_r_lcl_reg[1] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[12] [1]),\n .Q(\\cmd_pipe_plus.mc_bank_reg[8] [1]),\n .R(1'b0));\n FDRE \\req_bank_r_lcl_reg[2] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[12] [2]),\n .Q(\\cmd_pipe_plus.mc_bank_reg[8] [2]),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1077\" *) \n LUT5 #(\n .INIT(32'h888A8A8A)) \n req_bank_rdy_r_i_1__0\n (.I0(col_wait_r_reg),\n .I1(\\rd_this_rank_r_reg[0] ),\n .I2(order_q_r[1]),\n .I3(order_q_r[0]),\n .I4(req_bank_rdy_r_reg),\n .O(req_bank_rdy_ns));\n LUT6 #(\n .INIT(64'h00000000DD0DDDDD)) \n req_bank_rdy_r_i_2\n (.I0(bm_end_r1_reg),\n .I1(ras_timer_zero_r_reg),\n .I2(\\grant_r_reg[3]_0 [1]),\n .I3(rd_wr_r_lcl_reg_0),\n .I4(req_wr_r_lcl_reg_0),\n .I5(rd_wr_r_lcl_reg_1),\n .O(req_bank_rdy_r_reg));\n LUT6 #(\n .INIT(64'hB8BBBBBBB8B8B8B8)) \n \\req_cmd_r[0]_i_1__0 \n (.I0(req_cmd_r[0]),\n .I1(idle_r_lcl_reg),\n .I2(\\app_cmd_r1_reg[0] ),\n .I3(periodic_rd_ack_r_lcl_reg),\n .I4(periodic_rd_cntr_r_reg),\n .I5(periodic_rd_r),\n .O(\\req_cmd_r[0]_i_1__0_n_0 ));\n LUT6 #(\n .INIT(64'hB8888888B8B8B8B8)) \n \\req_cmd_r[1]_i_1__0 \n (.I0(req_cmd_r[1]),\n .I1(idle_r_lcl_reg),\n .I2(\\app_cmd_r2_reg[1] ),\n .I3(periodic_rd_ack_r_lcl_reg),\n .I4(periodic_rd_cntr_r_reg),\n .I5(periodic_rd_r),\n .O(\\req_cmd_r[1]_i_1__0_n_0 ));\n FDRE \\req_cmd_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\req_cmd_r[0]_i_1__0_n_0 ),\n .Q(req_cmd_r[0]),\n .R(1'b0));\n FDRE \\req_cmd_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\req_cmd_r[1]_i_1__0_n_0 ),\n .Q(req_cmd_r[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[3] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[9] [0]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[4] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[9] [1]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[5] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[9] [2]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[6] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[9] [3]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[7] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[9] [4]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[8] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[9] [5]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[9] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[9] [6]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [6]),\n .R(1'b0));\n FDRE \\req_data_buf_addr_r_reg[0] \n (.C(CLK),\n .CE(idle_r_lcl_reg_0),\n .D(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [0]),\n .Q(\\col_mux.col_data_buf_addr_r_reg[4] [0]),\n .R(1'b0));\n FDRE \\req_data_buf_addr_r_reg[1] \n (.C(CLK),\n .CE(idle_r_lcl_reg_0),\n .D(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [1]),\n .Q(\\col_mux.col_data_buf_addr_r_reg[4] [1]),\n .R(1'b0));\n FDRE \\req_data_buf_addr_r_reg[2] \n (.C(CLK),\n .CE(idle_r_lcl_reg_0),\n .D(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [2]),\n .Q(\\col_mux.col_data_buf_addr_r_reg[4] [2]),\n .R(1'b0));\n FDRE \\req_data_buf_addr_r_reg[3] \n (.C(CLK),\n .CE(idle_r_lcl_reg_0),\n .D(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [3]),\n .Q(\\col_mux.col_data_buf_addr_r_reg[4] [3]),\n .R(1'b0));\n FDRE \\req_data_buf_addr_r_reg[4] \n (.C(CLK),\n .CE(idle_r_lcl_reg_0),\n .D(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [4]),\n .Q(\\col_mux.col_data_buf_addr_r_reg[4] [4]),\n .R(1'b0));\n FDRE req_periodic_rd_r_lcl_reg\n (.C(CLK),\n .CE(E),\n .D(periodic_rd_insert),\n .Q(req_periodic_rd_r),\n .R(1'b0));\n FDRE req_priority_r_reg\n (.C(CLK),\n .CE(E),\n .D(hi_priority),\n .Q(req_priority_r),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[0] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [0]),\n .Q(\\cmd_pipe_plus.mc_address_reg[44] [0]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[10] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [10]),\n .Q(\\cmd_pipe_plus.mc_address_reg[44] [10]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[11] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [11]),\n .Q(\\cmd_pipe_plus.mc_address_reg[44] [11]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[12] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [12]),\n .Q(\\cmd_pipe_plus.mc_address_reg[44] [12]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[13] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [13]),\n .Q(\\cmd_pipe_plus.mc_address_reg[44] [13]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[14] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [14]),\n .Q(\\cmd_pipe_plus.mc_address_reg[44] [14]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[1] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [1]),\n .Q(\\cmd_pipe_plus.mc_address_reg[44] [1]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[2] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [2]),\n .Q(\\cmd_pipe_plus.mc_address_reg[44] [2]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[3] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [3]),\n .Q(\\cmd_pipe_plus.mc_address_reg[44] [3]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[4] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [4]),\n .Q(\\cmd_pipe_plus.mc_address_reg[44] [4]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[5] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [5]),\n .Q(\\cmd_pipe_plus.mc_address_reg[44] [5]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[6] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [6]),\n .Q(\\cmd_pipe_plus.mc_address_reg[44] [6]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[7] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [7]),\n .Q(\\cmd_pipe_plus.mc_address_reg[44] [7]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[8] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [8]),\n .Q(\\cmd_pipe_plus.mc_address_reg[44] [8]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[9] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [9]),\n .Q(\\cmd_pipe_plus.mc_address_reg[44] [9]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hCCCC0A0FFFFF0A0F)) \n req_wr_r_lcl_i_1__0\n (.I0(\\app_cmd_r2_reg[1] ),\n .I1(req_cmd_r[1]),\n .I2(periodic_rd_insert),\n .I3(\\app_cmd_r1_reg[0] ),\n .I4(idle_r_lcl_reg),\n .I5(req_cmd_r[0]),\n .O(req_wr_r_lcl0));\n FDRE req_wr_r_lcl_reg\n (.C(CLK),\n .CE(E),\n .D(req_wr_r_lcl0),\n .Q(bm_end_r1_reg),\n .R(1'b0));\n CARRY4 row_hit_ns_carry\n (.CI(1'b0),\n .CO({row_hit_ns_carry_n_0,row_hit_ns_carry_n_1,row_hit_ns_carry_n_2,row_hit_ns_carry_n_3}),\n .CYINIT(1'b1),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(NLW_row_hit_ns_carry_O_UNCONNECTED[3:0]),\n .S({row_hit_ns_carry_i_1__1_n_0,row_hit_ns_carry_i_2__1_n_0,row_hit_ns_carry_i_3__1_n_0,row_hit_ns_carry_i_4__1_n_0}));\n CARRY4 row_hit_ns_carry__0\n (.CI(row_hit_ns_carry_n_0),\n .CO({NLW_row_hit_ns_carry__0_CO_UNCONNECTED[3:1],row_hit_ns}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(NLW_row_hit_ns_carry__0_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,1'b0,row_hit_ns_carry__0_i_1__1_n_0}));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n row_hit_ns_carry__0_i_1__1\n (.I0(\\cmd_pipe_plus.mc_address_reg[44] [14]),\n .I1(\\app_addr_r1_reg[27] [14]),\n .I2(\\cmd_pipe_plus.mc_address_reg[44] [13]),\n .I3(\\app_addr_r1_reg[27] [13]),\n .I4(\\app_addr_r1_reg[27] [12]),\n .I5(\\cmd_pipe_plus.mc_address_reg[44] [12]),\n .O(row_hit_ns_carry__0_i_1__1_n_0));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n row_hit_ns_carry_i_1__1\n (.I0(\\cmd_pipe_plus.mc_address_reg[44] [11]),\n .I1(\\app_addr_r1_reg[27] [11]),\n .I2(\\cmd_pipe_plus.mc_address_reg[44] [10]),\n .I3(\\app_addr_r1_reg[27] [10]),\n .I4(\\app_addr_r1_reg[27] [9]),\n .I5(\\cmd_pipe_plus.mc_address_reg[44] [9]),\n .O(row_hit_ns_carry_i_1__1_n_0));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n row_hit_ns_carry_i_2__1\n (.I0(\\cmd_pipe_plus.mc_address_reg[44] [8]),\n .I1(\\app_addr_r1_reg[27] [8]),\n .I2(\\cmd_pipe_plus.mc_address_reg[44] [6]),\n .I3(\\app_addr_r1_reg[27] [6]),\n .I4(\\app_addr_r1_reg[27] [7]),\n .I5(\\cmd_pipe_plus.mc_address_reg[44] [7]),\n .O(row_hit_ns_carry_i_2__1_n_0));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n row_hit_ns_carry_i_3__1\n (.I0(\\cmd_pipe_plus.mc_address_reg[44] [5]),\n .I1(\\app_addr_r1_reg[27] [5]),\n .I2(\\cmd_pipe_plus.mc_address_reg[44] [4]),\n .I3(\\app_addr_r1_reg[27] [4]),\n .I4(\\app_addr_r1_reg[27] [3]),\n .I5(\\cmd_pipe_plus.mc_address_reg[44] [3]),\n .O(row_hit_ns_carry_i_3__1_n_0));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n row_hit_ns_carry_i_4__1\n (.I0(\\cmd_pipe_plus.mc_address_reg[44] [2]),\n .I1(\\app_addr_r1_reg[27] [2]),\n .I2(\\cmd_pipe_plus.mc_address_reg[44] [1]),\n .I3(\\app_addr_r1_reg[27] [1]),\n .I4(\\app_addr_r1_reg[27] [0]),\n .I5(\\cmd_pipe_plus.mc_address_reg[44] [0]),\n .O(row_hit_ns_carry_i_4__1_n_0));\n FDRE row_hit_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(row_hit_ns),\n .Q(row_hit_r_5),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1077\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\wr_this_rank_r[0]_i_1__1 \n (.I0(\\rd_this_rank_r_reg[0] ),\n .O(start_wtp_timer0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_bank_compare\" *) \nmodule ddr3_if_mig_7series_v4_0_bank_compare_1\n (req_periodic_rd_r,\n \\rd_this_rank_r_reg[0] ,\n bm_end_r1_reg,\n req_priority_r,\n rb_hit_busy_r,\n row_hit_r_0,\n \\grant_r_reg[1] ,\n req_bank_rdy_r_reg,\n pass_open_bank_ns,\n head_r_lcl_reg,\n p_91_out,\n ras_timer_zero_r_reg,\n start_wtp_timer0,\n \\cmd_pipe_plus.mc_address_reg[14] ,\n \\cmd_pipe_plus.mc_address_reg[40] ,\n \\col_mux.col_data_buf_addr_r_reg[4] ,\n \\cmd_pipe_plus.mc_bank_reg[2] ,\n \\cmd_pipe_plus.mc_address_reg[24] ,\n E,\n periodic_rd_insert,\n CLK,\n hi_priority,\n p_106_out,\n \\rtw_timer.rtw_cnt_r_reg[1] ,\n col_wait_r_reg,\n override_demand_r_reg,\n \\wtr_timer.wtr_cnt_r_reg[1] ,\n order_q_r,\n req_wr_r_lcl_reg_0,\n rnk_config_valid_r_lcl_reg,\n req_wr_r_lcl_reg_1,\n pass_open_bank_r_lcl_reg,\n tail_r_24,\n accept_r_reg,\n pre_wait_r,\n \\app_cmd_r2_reg[1] ,\n \\app_cmd_r1_reg[0] ,\n idle_r_lcl_reg,\n periodic_rd_ack_r_lcl_reg,\n periodic_rd_cntr_r_reg,\n periodic_rd_r,\n \\grant_r_reg[1]_0 ,\n periodic_rd_ack_r_lcl_reg_0,\n pre_bm_end_r_reg,\n pre_bm_end_r_reg_0,\n rd_wr_r_lcl_reg_0,\n req_wr_r,\n maint_req_r,\n \\maint_controller.maint_wip_r_lcl_reg ,\n wait_for_maint_r_18,\n \\app_addr_r1_reg[27] ,\n act_wait_r_lcl_reg,\n \\grant_r_reg[1]_1 ,\n act_wait_r_lcl_reg_0,\n \\req_row_r_lcl_reg[10]_0 ,\n idle_r_lcl_reg_0,\n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ,\n \\app_addr_r1_reg[12] ,\n \\app_addr_r1_reg[9] );\n output [0:0]req_periodic_rd_r;\n output \\rd_this_rank_r_reg[0] ;\n output bm_end_r1_reg;\n output req_priority_r;\n output [0:0]rb_hit_busy_r;\n output row_hit_r_0;\n output \\grant_r_reg[1] ;\n output req_bank_rdy_r_reg;\n output pass_open_bank_ns;\n output head_r_lcl_reg;\n output p_91_out;\n output ras_timer_zero_r_reg;\n output start_wtp_timer0;\n output [14:0]\\cmd_pipe_plus.mc_address_reg[14] ;\n output \\cmd_pipe_plus.mc_address_reg[40] ;\n output [4:0]\\col_mux.col_data_buf_addr_r_reg[4] ;\n output [2:0]\\cmd_pipe_plus.mc_bank_reg[2] ;\n output [6:0]\\cmd_pipe_plus.mc_address_reg[24] ;\n input [0:0]E;\n input periodic_rd_insert;\n input CLK;\n input hi_priority;\n input p_106_out;\n input \\rtw_timer.rtw_cnt_r_reg[1] ;\n input col_wait_r_reg;\n input override_demand_r_reg;\n input \\wtr_timer.wtr_cnt_r_reg[1] ;\n input [1:0]order_q_r;\n input req_wr_r_lcl_reg_0;\n input rnk_config_valid_r_lcl_reg;\n input req_wr_r_lcl_reg_1;\n input pass_open_bank_r_lcl_reg;\n input tail_r_24;\n input accept_r_reg;\n input pre_wait_r;\n input [0:0]\\app_cmd_r2_reg[1] ;\n input \\app_cmd_r1_reg[0] ;\n input idle_r_lcl_reg;\n input periodic_rd_ack_r_lcl_reg;\n input periodic_rd_cntr_r_reg;\n input periodic_rd_r;\n input [1:0]\\grant_r_reg[1]_0 ;\n input periodic_rd_ack_r_lcl_reg_0;\n input pre_bm_end_r_reg;\n input pre_bm_end_r_reg_0;\n input rd_wr_r_lcl_reg_0;\n input [0:0]req_wr_r;\n input maint_req_r;\n input \\maint_controller.maint_wip_r_lcl_reg ;\n input wait_for_maint_r_18;\n input [14:0]\\app_addr_r1_reg[27] ;\n input act_wait_r_lcl_reg;\n input [1:0]\\grant_r_reg[1]_1 ;\n input [0:0]act_wait_r_lcl_reg_0;\n input [0:0]\\req_row_r_lcl_reg[10]_0 ;\n input idle_r_lcl_reg_0;\n input [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n input [2:0]\\app_addr_r1_reg[12] ;\n input [6:0]\\app_addr_r1_reg[9] ;\n\n wire CLK;\n wire [0:0]E;\n wire accept_r_reg;\n wire act_wait_r_lcl_reg;\n wire [0:0]act_wait_r_lcl_reg_0;\n wire [2:0]\\app_addr_r1_reg[12] ;\n wire [14:0]\\app_addr_r1_reg[27] ;\n wire [6:0]\\app_addr_r1_reg[9] ;\n wire \\app_cmd_r1_reg[0] ;\n wire [0:0]\\app_cmd_r2_reg[1] ;\n wire bm_end_r1_reg;\n wire [14:0]\\cmd_pipe_plus.mc_address_reg[14] ;\n wire [6:0]\\cmd_pipe_plus.mc_address_reg[24] ;\n wire \\cmd_pipe_plus.mc_address_reg[40] ;\n wire [2:0]\\cmd_pipe_plus.mc_bank_reg[2] ;\n wire [4:0]\\col_mux.col_data_buf_addr_r_reg[4] ;\n wire col_wait_r_reg;\n wire \\grant_r[1]_i_5_n_0 ;\n wire \\grant_r_reg[1] ;\n wire [1:0]\\grant_r_reg[1]_0 ;\n wire [1:0]\\grant_r_reg[1]_1 ;\n wire head_r_lcl_reg;\n wire hi_priority;\n wire idle_r_lcl_reg;\n wire idle_r_lcl_reg_0;\n wire \\maint_controller.maint_wip_r_lcl_reg ;\n wire maint_req_r;\n wire [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n wire [1:0]order_q_r;\n wire override_demand_r_reg;\n wire p_106_out;\n wire p_91_out;\n wire pass_open_bank_ns;\n wire pass_open_bank_r_lcl_i_2__0_n_0;\n wire pass_open_bank_r_lcl_reg;\n wire periodic_rd_ack_r_lcl_reg;\n wire periodic_rd_ack_r_lcl_reg_0;\n wire periodic_rd_cntr_r_reg;\n wire periodic_rd_insert;\n wire periodic_rd_r;\n wire pre_bm_end_r_reg;\n wire pre_bm_end_r_reg_0;\n wire pre_wait_r;\n wire ras_timer_zero_r_reg;\n wire [0:0]rb_hit_busy_r;\n wire \\rd_this_rank_r_reg[0] ;\n wire rd_wr_ns;\n wire rd_wr_r_lcl_reg_0;\n wire req_bank_rdy_r_reg;\n wire [1:0]req_cmd_r;\n wire \\req_cmd_r[0]_i_1_n_0 ;\n wire \\req_cmd_r[1]_i_1_n_0 ;\n wire [0:0]req_periodic_rd_r;\n wire req_priority_r;\n wire [0:0]\\req_row_r_lcl_reg[10]_0 ;\n wire [0:0]req_wr_r;\n wire req_wr_r_lcl0;\n wire req_wr_r_lcl_reg_0;\n wire req_wr_r_lcl_reg_1;\n wire rnk_config_valid_r_lcl_reg;\n wire row_hit_ns;\n wire row_hit_ns_carry__0_i_1__0_n_0;\n wire row_hit_ns_carry_i_1__0_n_0;\n wire row_hit_ns_carry_i_2__0_n_0;\n wire row_hit_ns_carry_i_3__0_n_0;\n wire row_hit_ns_carry_i_4__0_n_0;\n wire row_hit_ns_carry_n_0;\n wire row_hit_ns_carry_n_1;\n wire row_hit_ns_carry_n_2;\n wire row_hit_ns_carry_n_3;\n wire row_hit_r_0;\n wire \\rtw_timer.rtw_cnt_r_reg[1] ;\n wire start_wtp_timer0;\n wire tail_r_24;\n wire wait_for_maint_r_18;\n wire \\wtr_timer.wtr_cnt_r_reg[1] ;\n wire [3:0]NLW_row_hit_ns_carry_O_UNCONNECTED;\n wire [3:1]NLW_row_hit_ns_carry__0_CO_UNCONNECTED;\n wire [3:0]NLW_row_hit_ns_carry__0_O_UNCONNECTED;\n\n (* SOFT_HLUTNM = \"soft_lutpair1064\" *) \n LUT5 #(\n .INIT(32'hFFFF7000)) \n bm_end_r1_i_1\n (.I0(bm_end_r1_reg),\n .I1(\\rd_this_rank_r_reg[0] ),\n .I2(pass_open_bank_r_lcl_reg),\n .I3(\\grant_r_reg[1]_0 [1]),\n .I4(pre_bm_end_r_reg_0),\n .O(p_91_out));\n LUT6 #(\n .INIT(64'h707F7F7F7F7F7F7F)) \n \\cmd_pipe_plus.mc_address[40]_i_2 \n (.I0(\\cmd_pipe_plus.mc_address_reg[14] [10]),\n .I1(act_wait_r_lcl_reg),\n .I2(\\grant_r_reg[1]_1 [1]),\n .I3(\\grant_r_reg[1]_1 [0]),\n .I4(act_wait_r_lcl_reg_0),\n .I5(\\req_row_r_lcl_reg[10]_0 ),\n .O(\\cmd_pipe_plus.mc_address_reg[40] ));\n LUT6 #(\n .INIT(64'hFFFCFFFDFFFFFFFD)) \n \\grant_r[1]_i_3 \n (.I0(\\rtw_timer.rtw_cnt_r_reg[1] ),\n .I1(col_wait_r_reg),\n .I2(\\grant_r[1]_i_5_n_0 ),\n .I3(override_demand_r_reg),\n .I4(\\rd_this_rank_r_reg[0] ),\n .I5(\\wtr_timer.wtr_cnt_r_reg[1] ),\n .O(\\grant_r_reg[1] ));\n LUT6 #(\n .INIT(64'hFFFFFFFF44544444)) \n \\grant_r[1]_i_5 \n (.I0(\\rd_this_rank_r_reg[0] ),\n .I1(order_q_r[1]),\n .I2(order_q_r[0]),\n .I3(req_bank_rdy_r_reg),\n .I4(req_wr_r_lcl_reg_0),\n .I5(rnk_config_valid_r_lcl_reg),\n .O(\\grant_r[1]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h0000000080AAAAAA)) \n i___10_i_2\n (.I0(pre_bm_end_r_reg),\n .I1(bm_end_r1_reg),\n .I2(\\rd_this_rank_r_reg[0] ),\n .I3(pass_open_bank_r_lcl_reg),\n .I4(\\grant_r_reg[1]_0 [1]),\n .I5(pre_bm_end_r_reg_0),\n .O(head_r_lcl_reg));\n LUT6 #(\n .INIT(64'h4444544444444444)) \n pass_open_bank_r_lcl_i_1\n (.I0(req_wr_r_lcl_reg_1),\n .I1(pass_open_bank_r_lcl_reg),\n .I2(tail_r_24),\n .I3(accept_r_reg),\n .I4(pre_wait_r),\n .I5(pass_open_bank_r_lcl_i_2__0_n_0),\n .O(pass_open_bank_ns));\n LUT5 #(\n .INIT(32'hAAAA00A2)) \n pass_open_bank_r_lcl_i_2__0\n (.I0(row_hit_r_0),\n .I1(maint_req_r),\n .I2(periodic_rd_cntr_r_reg),\n .I3(\\maint_controller.maint_wip_r_lcl_reg ),\n .I4(wait_for_maint_r_18),\n .O(pass_open_bank_r_lcl_i_2__0_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1064\" *) \n LUT2 #(\n .INIT(4'hB)) \n ras_timer_zero_r_i_2__2\n (.I0(\\rd_this_rank_r_reg[0] ),\n .I1(\\grant_r_reg[1]_0 [1]),\n .O(ras_timer_zero_r_reg));\n FDRE rb_hit_busy_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(p_106_out),\n .Q(rb_hit_busy_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1065\" *) \n LUT4 #(\n .INIT(16'h2F20)) \n rd_wr_r_lcl_i_1\n (.I0(\\rd_this_rank_r_reg[0] ),\n .I1(\\grant_r_reg[1]_0 [1]),\n .I2(idle_r_lcl_reg),\n .I3(periodic_rd_ack_r_lcl_reg_0),\n .O(rd_wr_ns));\n FDRE rd_wr_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rd_wr_ns),\n .Q(\\rd_this_rank_r_reg[0] ),\n .R(1'b0));\n FDRE \\req_bank_r_lcl_reg[0] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[12] [0]),\n .Q(\\cmd_pipe_plus.mc_bank_reg[2] [0]),\n .R(1'b0));\n FDRE \\req_bank_r_lcl_reg[1] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[12] [1]),\n .Q(\\cmd_pipe_plus.mc_bank_reg[2] [1]),\n .R(1'b0));\n FDRE \\req_bank_r_lcl_reg[2] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[12] [2]),\n .Q(\\cmd_pipe_plus.mc_bank_reg[2] [2]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h40FF404040404040)) \n req_bank_rdy_r_i_3\n (.I0(\\rd_this_rank_r_reg[0] ),\n .I1(\\grant_r_reg[1]_0 [1]),\n .I2(bm_end_r1_reg),\n .I3(rd_wr_r_lcl_reg_0),\n .I4(\\grant_r_reg[1]_0 [0]),\n .I5(req_wr_r),\n .O(req_bank_rdy_r_reg));\n LUT6 #(\n .INIT(64'hB8BBBBBBB8B8B8B8)) \n \\req_cmd_r[0]_i_1 \n (.I0(req_cmd_r[0]),\n .I1(idle_r_lcl_reg),\n .I2(\\app_cmd_r1_reg[0] ),\n .I3(periodic_rd_ack_r_lcl_reg),\n .I4(periodic_rd_cntr_r_reg),\n .I5(periodic_rd_r),\n .O(\\req_cmd_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hB8888888B8B8B8B8)) \n \\req_cmd_r[1]_i_1 \n (.I0(req_cmd_r[1]),\n .I1(idle_r_lcl_reg),\n .I2(\\app_cmd_r2_reg[1] ),\n .I3(periodic_rd_ack_r_lcl_reg),\n .I4(periodic_rd_cntr_r_reg),\n .I5(periodic_rd_r),\n .O(\\req_cmd_r[1]_i_1_n_0 ));\n FDRE \\req_cmd_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\req_cmd_r[0]_i_1_n_0 ),\n .Q(req_cmd_r[0]),\n .R(1'b0));\n FDRE \\req_cmd_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\req_cmd_r[1]_i_1_n_0 ),\n .Q(req_cmd_r[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[3] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[9] [0]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[4] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[9] [1]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[5] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[9] [2]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[6] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[9] [3]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[7] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[9] [4]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[8] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[9] [5]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[9] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[9] [6]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [6]),\n .R(1'b0));\n FDRE \\req_data_buf_addr_r_reg[0] \n (.C(CLK),\n .CE(idle_r_lcl_reg_0),\n .D(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [0]),\n .Q(\\col_mux.col_data_buf_addr_r_reg[4] [0]),\n .R(1'b0));\n FDRE \\req_data_buf_addr_r_reg[1] \n (.C(CLK),\n .CE(idle_r_lcl_reg_0),\n .D(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [1]),\n .Q(\\col_mux.col_data_buf_addr_r_reg[4] [1]),\n .R(1'b0));\n FDRE \\req_data_buf_addr_r_reg[2] \n (.C(CLK),\n .CE(idle_r_lcl_reg_0),\n .D(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [2]),\n .Q(\\col_mux.col_data_buf_addr_r_reg[4] [2]),\n .R(1'b0));\n FDRE \\req_data_buf_addr_r_reg[3] \n (.C(CLK),\n .CE(idle_r_lcl_reg_0),\n .D(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [3]),\n .Q(\\col_mux.col_data_buf_addr_r_reg[4] [3]),\n .R(1'b0));\n FDRE \\req_data_buf_addr_r_reg[4] \n (.C(CLK),\n .CE(idle_r_lcl_reg_0),\n .D(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [4]),\n .Q(\\col_mux.col_data_buf_addr_r_reg[4] [4]),\n .R(1'b0));\n FDRE req_periodic_rd_r_lcl_reg\n (.C(CLK),\n .CE(E),\n .D(periodic_rd_insert),\n .Q(req_periodic_rd_r),\n .R(1'b0));\n FDRE req_priority_r_reg\n (.C(CLK),\n .CE(E),\n .D(hi_priority),\n .Q(req_priority_r),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[0] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [0]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [0]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[10] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [10]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [10]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[11] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [11]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [11]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[12] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [12]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [12]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[13] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [13]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [13]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[14] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [14]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [14]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[1] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [1]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [1]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[2] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [2]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [2]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[3] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [3]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [3]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[4] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [4]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [4]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[5] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [5]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [5]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[6] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [6]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [6]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[7] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [7]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [7]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[8] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [8]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [8]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[9] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [9]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [9]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hCCCC0A0FFFFF0A0F)) \n req_wr_r_lcl_i_1\n (.I0(\\app_cmd_r2_reg[1] ),\n .I1(req_cmd_r[1]),\n .I2(periodic_rd_insert),\n .I3(\\app_cmd_r1_reg[0] ),\n .I4(idle_r_lcl_reg),\n .I5(req_cmd_r[0]),\n .O(req_wr_r_lcl0));\n FDRE req_wr_r_lcl_reg\n (.C(CLK),\n .CE(E),\n .D(req_wr_r_lcl0),\n .Q(bm_end_r1_reg),\n .R(1'b0));\n CARRY4 row_hit_ns_carry\n (.CI(1'b0),\n .CO({row_hit_ns_carry_n_0,row_hit_ns_carry_n_1,row_hit_ns_carry_n_2,row_hit_ns_carry_n_3}),\n .CYINIT(1'b1),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(NLW_row_hit_ns_carry_O_UNCONNECTED[3:0]),\n .S({row_hit_ns_carry_i_1__0_n_0,row_hit_ns_carry_i_2__0_n_0,row_hit_ns_carry_i_3__0_n_0,row_hit_ns_carry_i_4__0_n_0}));\n CARRY4 row_hit_ns_carry__0\n (.CI(row_hit_ns_carry_n_0),\n .CO({NLW_row_hit_ns_carry__0_CO_UNCONNECTED[3:1],row_hit_ns}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(NLW_row_hit_ns_carry__0_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,1'b0,row_hit_ns_carry__0_i_1__0_n_0}));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n row_hit_ns_carry__0_i_1__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[14] [14]),\n .I1(\\app_addr_r1_reg[27] [14]),\n .I2(\\cmd_pipe_plus.mc_address_reg[14] [13]),\n .I3(\\app_addr_r1_reg[27] [13]),\n .I4(\\app_addr_r1_reg[27] [12]),\n .I5(\\cmd_pipe_plus.mc_address_reg[14] [12]),\n .O(row_hit_ns_carry__0_i_1__0_n_0));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n row_hit_ns_carry_i_1__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[14] [11]),\n .I1(\\app_addr_r1_reg[27] [11]),\n .I2(\\cmd_pipe_plus.mc_address_reg[14] [9]),\n .I3(\\app_addr_r1_reg[27] [9]),\n .I4(\\app_addr_r1_reg[27] [10]),\n .I5(\\cmd_pipe_plus.mc_address_reg[14] [10]),\n .O(row_hit_ns_carry_i_1__0_n_0));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n row_hit_ns_carry_i_2__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[14] [8]),\n .I1(\\app_addr_r1_reg[27] [8]),\n .I2(\\cmd_pipe_plus.mc_address_reg[14] [7]),\n .I3(\\app_addr_r1_reg[27] [7]),\n .I4(\\app_addr_r1_reg[27] [6]),\n .I5(\\cmd_pipe_plus.mc_address_reg[14] [6]),\n .O(row_hit_ns_carry_i_2__0_n_0));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n row_hit_ns_carry_i_3__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[14] [5]),\n .I1(\\app_addr_r1_reg[27] [5]),\n .I2(\\cmd_pipe_plus.mc_address_reg[14] [3]),\n .I3(\\app_addr_r1_reg[27] [3]),\n .I4(\\app_addr_r1_reg[27] [4]),\n .I5(\\cmd_pipe_plus.mc_address_reg[14] [4]),\n .O(row_hit_ns_carry_i_3__0_n_0));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n row_hit_ns_carry_i_4__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[14] [2]),\n .I1(\\app_addr_r1_reg[27] [2]),\n .I2(\\cmd_pipe_plus.mc_address_reg[14] [1]),\n .I3(\\app_addr_r1_reg[27] [1]),\n .I4(\\app_addr_r1_reg[27] [0]),\n .I5(\\cmd_pipe_plus.mc_address_reg[14] [0]),\n .O(row_hit_ns_carry_i_4__0_n_0));\n FDRE row_hit_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(row_hit_ns),\n .Q(row_hit_r_0),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1065\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\wr_this_rank_r[0]_i_1__0 \n (.I0(\\rd_this_rank_r_reg[0] ),\n .O(start_wtp_timer0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_bank_compare\" *) \nmodule ddr3_if_mig_7series_v4_0_bank_compare_2\n (req_periodic_rd_r,\n \\rd_this_rank_r_reg[0] ,\n bm_end_r1_reg,\n req_priority_r,\n q_has_priority_r_reg,\n row_hit_r,\n \\grant_r_reg[2] ,\n \\ras_timer_r_reg[0] ,\n \\ras_timer_r_reg[0]_0 ,\n pass_open_bank_ns,\n p_130_out,\n start_wtp_timer0,\n ras_timer_zero_r_reg,\n \\cmd_pipe_plus.mc_address_reg[14] ,\n head_r_lcl_reg,\n head_r_lcl_reg_0,\n \\col_mux.col_data_buf_addr_r_reg[4] ,\n \\cmd_pipe_plus.mc_bank_reg[2] ,\n \\cmd_pipe_plus.mc_address_reg[24] ,\n E,\n periodic_rd_insert,\n CLK,\n hi_priority,\n p_145_out,\n \\app_cmd_r2_reg[1] ,\n \\app_cmd_r1_reg[0] ,\n idle_r_lcl_reg,\n periodic_rd_ack_r_lcl_reg,\n periodic_rd_cntr_r_reg,\n periodic_rd_r,\n \\grant_r_reg[0] ,\n periodic_rd_ack_r_lcl_reg_0,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ,\n pass_open_bank_r_lcl_reg,\n pre_passing_open_bank_r,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ,\n Q,\n req_wr_r_lcl_reg_0,\n tail_r,\n accept_r_reg,\n pre_wait_r,\n pre_bm_end_r,\n maint_req_r,\n \\maint_controller.maint_wip_r_lcl_reg ,\n wait_for_maint_r,\n \\app_addr_r1_reg[27] ,\n rb_hit_busy_r_reg_0,\n rb_hit_busy_r_reg_1,\n rb_hit_busy_r_reg_2,\n idle_r_lcl_reg_0,\n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ,\n \\app_addr_r1_reg[12] ,\n \\app_addr_r1_reg[9] );\n output [0:0]req_periodic_rd_r;\n output \\rd_this_rank_r_reg[0] ;\n output bm_end_r1_reg;\n output req_priority_r;\n output q_has_priority_r_reg;\n output row_hit_r;\n output \\grant_r_reg[2] ;\n output \\ras_timer_r_reg[0] ;\n output \\ras_timer_r_reg[0]_0 ;\n output pass_open_bank_ns;\n output p_130_out;\n output start_wtp_timer0;\n output ras_timer_zero_r_reg;\n output [14:0]\\cmd_pipe_plus.mc_address_reg[14] ;\n output head_r_lcl_reg;\n output head_r_lcl_reg_0;\n output [4:0]\\col_mux.col_data_buf_addr_r_reg[4] ;\n output [2:0]\\cmd_pipe_plus.mc_bank_reg[2] ;\n output [6:0]\\cmd_pipe_plus.mc_address_reg[24] ;\n input [0:0]E;\n input periodic_rd_insert;\n input CLK;\n input hi_priority;\n input p_145_out;\n input [0:0]\\app_cmd_r2_reg[1] ;\n input \\app_cmd_r1_reg[0] ;\n input idle_r_lcl_reg;\n input periodic_rd_ack_r_lcl_reg;\n input periodic_rd_cntr_r_reg;\n input periodic_rd_r;\n input [0:0]\\grant_r_reg[0] ;\n input periodic_rd_ack_r_lcl_reg_0;\n input [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;\n input pass_open_bank_r_lcl_reg;\n input pre_passing_open_bank_r;\n input [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;\n input [0:0]Q;\n input req_wr_r_lcl_reg_0;\n input tail_r;\n input accept_r_reg;\n input pre_wait_r;\n input pre_bm_end_r;\n input maint_req_r;\n input \\maint_controller.maint_wip_r_lcl_reg ;\n input wait_for_maint_r;\n input [14:0]\\app_addr_r1_reg[27] ;\n input rb_hit_busy_r_reg_0;\n input rb_hit_busy_r_reg_1;\n input rb_hit_busy_r_reg_2;\n input idle_r_lcl_reg_0;\n input [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n input [2:0]\\app_addr_r1_reg[12] ;\n input [6:0]\\app_addr_r1_reg[9] ;\n\n wire CLK;\n wire [0:0]E;\n wire [0:0]Q;\n wire accept_r_reg;\n wire [2:0]\\app_addr_r1_reg[12] ;\n wire [14:0]\\app_addr_r1_reg[27] ;\n wire [6:0]\\app_addr_r1_reg[9] ;\n wire \\app_cmd_r1_reg[0] ;\n wire [0:0]\\app_cmd_r2_reg[1] ;\n wire bm_end_r1_reg;\n wire [14:0]\\cmd_pipe_plus.mc_address_reg[14] ;\n wire [6:0]\\cmd_pipe_plus.mc_address_reg[24] ;\n wire [2:0]\\cmd_pipe_plus.mc_bank_reg[2] ;\n wire [4:0]\\col_mux.col_data_buf_addr_r_reg[4] ;\n wire [0:0]\\grant_r_reg[0] ;\n wire \\grant_r_reg[2] ;\n wire head_r_lcl_reg;\n wire head_r_lcl_reg_0;\n wire hi_priority;\n wire idle_r_lcl_reg;\n wire idle_r_lcl_reg_0;\n wire \\maint_controller.maint_wip_r_lcl_reg ;\n wire maint_req_r;\n wire [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n wire p_130_out;\n wire p_145_out;\n wire pass_open_bank_ns;\n wire pass_open_bank_r_lcl_i_2_n_0;\n wire pass_open_bank_r_lcl_reg;\n wire periodic_rd_ack_r_lcl_reg;\n wire periodic_rd_ack_r_lcl_reg_0;\n wire periodic_rd_cntr_r_reg;\n wire periodic_rd_insert;\n wire periodic_rd_r;\n wire pre_bm_end_r;\n wire pre_passing_open_bank_r;\n wire pre_wait_r;\n wire q_has_priority_r_reg;\n wire \\ras_timer_r_reg[0] ;\n wire \\ras_timer_r_reg[0]_0 ;\n wire ras_timer_zero_r_reg;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;\n wire rb_hit_busy_r_reg_0;\n wire rb_hit_busy_r_reg_1;\n wire rb_hit_busy_r_reg_2;\n wire \\rd_this_rank_r_reg[0] ;\n wire rd_wr_ns;\n wire [1:0]req_cmd_r;\n wire \\req_cmd_r[0]_i_1__2_n_0 ;\n wire \\req_cmd_r[1]_i_1__2_n_0 ;\n wire [0:0]req_periodic_rd_r;\n wire req_priority_r;\n wire req_wr_r_lcl0;\n wire req_wr_r_lcl_reg_0;\n wire row_hit_ns;\n wire row_hit_ns_carry__0_i_1_n_0;\n wire row_hit_ns_carry_i_1_n_0;\n wire row_hit_ns_carry_i_2_n_0;\n wire row_hit_ns_carry_i_3_n_0;\n wire row_hit_ns_carry_i_4_n_0;\n wire row_hit_ns_carry_n_0;\n wire row_hit_ns_carry_n_1;\n wire row_hit_ns_carry_n_2;\n wire row_hit_ns_carry_n_3;\n wire row_hit_r;\n wire start_wtp_timer0;\n wire tail_r;\n wire wait_for_maint_r;\n wire [3:0]NLW_row_hit_ns_carry_O_UNCONNECTED;\n wire [3:1]NLW_row_hit_ns_carry__0_CO_UNCONNECTED;\n wire [3:0]NLW_row_hit_ns_carry__0_O_UNCONNECTED;\n\n (* SOFT_HLUTNM = \"soft_lutpair1050\" *) \n LUT5 #(\n .INIT(32'hFFFF7000)) \n bm_end_r1_i_1__0\n (.I0(bm_end_r1_reg),\n .I1(\\rd_this_rank_r_reg[0] ),\n .I2(pass_open_bank_r_lcl_reg),\n .I3(\\grant_r_reg[0] ),\n .I4(pre_bm_end_r),\n .O(p_130_out));\n (* SOFT_HLUTNM = \"soft_lutpair1052\" *) \n LUT4 #(\n .INIT(16'h7EE8)) \n i___1_i_4\n (.I0(q_has_priority_r_reg),\n .I1(rb_hit_busy_r_reg_0),\n .I2(rb_hit_busy_r_reg_1),\n .I3(rb_hit_busy_r_reg_2),\n .O(head_r_lcl_reg));\n (* SOFT_HLUTNM = \"soft_lutpair1052\" *) \n LUT4 #(\n .INIT(16'h6996)) \n i___1_i_5\n (.I0(q_has_priority_r_reg),\n .I1(rb_hit_busy_r_reg_2),\n .I2(rb_hit_busy_r_reg_1),\n .I3(rb_hit_busy_r_reg_0),\n .O(head_r_lcl_reg_0));\n LUT6 #(\n .INIT(64'hAAAAAAAA2A000000)) \n i___36_i_3\n (.I0(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ),\n .I1(bm_end_r1_reg),\n .I2(\\rd_this_rank_r_reg[0] ),\n .I3(pass_open_bank_r_lcl_reg),\n .I4(\\grant_r_reg[0] ),\n .I5(pre_passing_open_bank_r),\n .O(\\grant_r_reg[2] ));\n LUT6 #(\n .INIT(64'hAAAAAAAA2A000000)) \n i___38_i_1\n (.I0(Q),\n .I1(bm_end_r1_reg),\n .I2(\\rd_this_rank_r_reg[0] ),\n .I3(pass_open_bank_r_lcl_reg),\n .I4(\\grant_r_reg[0] ),\n .I5(pre_passing_open_bank_r),\n .O(\\ras_timer_r_reg[0]_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAA2A000000)) \n i___56_i_3\n (.I0(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ),\n .I1(bm_end_r1_reg),\n .I2(\\rd_this_rank_r_reg[0] ),\n .I3(pass_open_bank_r_lcl_reg),\n .I4(\\grant_r_reg[0] ),\n .I5(pre_passing_open_bank_r),\n .O(\\ras_timer_r_reg[0] ));\n LUT6 #(\n .INIT(64'h4444544444444444)) \n pass_open_bank_r_lcl_i_1__0\n (.I0(req_wr_r_lcl_reg_0),\n .I1(pass_open_bank_r_lcl_reg),\n .I2(tail_r),\n .I3(accept_r_reg),\n .I4(pre_wait_r),\n .I5(pass_open_bank_r_lcl_i_2_n_0),\n .O(pass_open_bank_ns));\n LUT5 #(\n .INIT(32'hAAAA00A2)) \n pass_open_bank_r_lcl_i_2\n (.I0(row_hit_r),\n .I1(maint_req_r),\n .I2(periodic_rd_cntr_r_reg),\n .I3(\\maint_controller.maint_wip_r_lcl_reg ),\n .I4(wait_for_maint_r),\n .O(pass_open_bank_r_lcl_i_2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1050\" *) \n LUT2 #(\n .INIT(4'hB)) \n ras_timer_zero_r_i_2__1\n (.I0(\\rd_this_rank_r_reg[0] ),\n .I1(\\grant_r_reg[0] ),\n .O(ras_timer_zero_r_reg));\n FDRE rb_hit_busy_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(p_145_out),\n .Q(q_has_priority_r_reg),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1051\" *) \n LUT4 #(\n .INIT(16'h2F20)) \n rd_wr_r_lcl_i_1__2\n (.I0(\\rd_this_rank_r_reg[0] ),\n .I1(\\grant_r_reg[0] ),\n .I2(idle_r_lcl_reg),\n .I3(periodic_rd_ack_r_lcl_reg_0),\n .O(rd_wr_ns));\n FDRE rd_wr_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rd_wr_ns),\n .Q(\\rd_this_rank_r_reg[0] ),\n .R(1'b0));\n FDRE \\req_bank_r_lcl_reg[0] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[12] [0]),\n .Q(\\cmd_pipe_plus.mc_bank_reg[2] [0]),\n .R(1'b0));\n FDRE \\req_bank_r_lcl_reg[1] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[12] [1]),\n .Q(\\cmd_pipe_plus.mc_bank_reg[2] [1]),\n .R(1'b0));\n FDRE \\req_bank_r_lcl_reg[2] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[12] [2]),\n .Q(\\cmd_pipe_plus.mc_bank_reg[2] [2]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hB8BBBBBBB8B8B8B8)) \n \\req_cmd_r[0]_i_1__2 \n (.I0(req_cmd_r[0]),\n .I1(idle_r_lcl_reg),\n .I2(\\app_cmd_r1_reg[0] ),\n .I3(periodic_rd_ack_r_lcl_reg),\n .I4(periodic_rd_cntr_r_reg),\n .I5(periodic_rd_r),\n .O(\\req_cmd_r[0]_i_1__2_n_0 ));\n LUT6 #(\n .INIT(64'hB8888888B8B8B8B8)) \n \\req_cmd_r[1]_i_1__2 \n (.I0(req_cmd_r[1]),\n .I1(idle_r_lcl_reg),\n .I2(\\app_cmd_r2_reg[1] ),\n .I3(periodic_rd_ack_r_lcl_reg),\n .I4(periodic_rd_cntr_r_reg),\n .I5(periodic_rd_r),\n .O(\\req_cmd_r[1]_i_1__2_n_0 ));\n FDRE \\req_cmd_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\req_cmd_r[0]_i_1__2_n_0 ),\n .Q(req_cmd_r[0]),\n .R(1'b0));\n FDRE \\req_cmd_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\req_cmd_r[1]_i_1__2_n_0 ),\n .Q(req_cmd_r[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[3] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[9] [0]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[4] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[9] [1]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[5] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[9] [2]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [2]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[6] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[9] [3]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [3]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[7] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[9] [4]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [4]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[8] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[9] [5]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [5]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\req_col_r_reg[9] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[9] [6]),\n .Q(\\cmd_pipe_plus.mc_address_reg[24] [6]),\n .R(1'b0));\n FDRE \\req_data_buf_addr_r_reg[0] \n (.C(CLK),\n .CE(idle_r_lcl_reg_0),\n .D(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [0]),\n .Q(\\col_mux.col_data_buf_addr_r_reg[4] [0]),\n .R(1'b0));\n FDRE \\req_data_buf_addr_r_reg[1] \n (.C(CLK),\n .CE(idle_r_lcl_reg_0),\n .D(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [1]),\n .Q(\\col_mux.col_data_buf_addr_r_reg[4] [1]),\n .R(1'b0));\n FDRE \\req_data_buf_addr_r_reg[2] \n (.C(CLK),\n .CE(idle_r_lcl_reg_0),\n .D(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [2]),\n .Q(\\col_mux.col_data_buf_addr_r_reg[4] [2]),\n .R(1'b0));\n FDRE \\req_data_buf_addr_r_reg[3] \n (.C(CLK),\n .CE(idle_r_lcl_reg_0),\n .D(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [3]),\n .Q(\\col_mux.col_data_buf_addr_r_reg[4] [3]),\n .R(1'b0));\n FDRE \\req_data_buf_addr_r_reg[4] \n (.C(CLK),\n .CE(idle_r_lcl_reg_0),\n .D(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [4]),\n .Q(\\col_mux.col_data_buf_addr_r_reg[4] [4]),\n .R(1'b0));\n FDRE req_periodic_rd_r_lcl_reg\n (.C(CLK),\n .CE(E),\n .D(periodic_rd_insert),\n .Q(req_periodic_rd_r),\n .R(1'b0));\n FDRE req_priority_r_reg\n (.C(CLK),\n .CE(E),\n .D(hi_priority),\n .Q(req_priority_r),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[0] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [0]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [0]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[10] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [10]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [10]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[11] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [11]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [11]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[12] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [12]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [12]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[13] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [13]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [13]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[14] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [14]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [14]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[1] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [1]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [1]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[2] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [2]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [2]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[3] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [3]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [3]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[4] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [4]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [4]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[5] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [5]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [5]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[6] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [6]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [6]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[7] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [7]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [7]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[8] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [8]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [8]),\n .R(1'b0));\n FDRE \\req_row_r_lcl_reg[9] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg[27] [9]),\n .Q(\\cmd_pipe_plus.mc_address_reg[14] [9]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hCCCC0A0FFFFF0A0F)) \n req_wr_r_lcl_i_1__2\n (.I0(\\app_cmd_r2_reg[1] ),\n .I1(req_cmd_r[1]),\n .I2(periodic_rd_insert),\n .I3(\\app_cmd_r1_reg[0] ),\n .I4(idle_r_lcl_reg),\n .I5(req_cmd_r[0]),\n .O(req_wr_r_lcl0));\n FDRE req_wr_r_lcl_reg\n (.C(CLK),\n .CE(E),\n .D(req_wr_r_lcl0),\n .Q(bm_end_r1_reg),\n .R(1'b0));\n CARRY4 row_hit_ns_carry\n (.CI(1'b0),\n .CO({row_hit_ns_carry_n_0,row_hit_ns_carry_n_1,row_hit_ns_carry_n_2,row_hit_ns_carry_n_3}),\n .CYINIT(1'b1),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(NLW_row_hit_ns_carry_O_UNCONNECTED[3:0]),\n .S({row_hit_ns_carry_i_1_n_0,row_hit_ns_carry_i_2_n_0,row_hit_ns_carry_i_3_n_0,row_hit_ns_carry_i_4_n_0}));\n CARRY4 row_hit_ns_carry__0\n (.CI(row_hit_ns_carry_n_0),\n .CO({NLW_row_hit_ns_carry__0_CO_UNCONNECTED[3:1],row_hit_ns}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(NLW_row_hit_ns_carry__0_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,1'b0,row_hit_ns_carry__0_i_1_n_0}));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n row_hit_ns_carry__0_i_1\n (.I0(\\cmd_pipe_plus.mc_address_reg[14] [14]),\n .I1(\\app_addr_r1_reg[27] [14]),\n .I2(\\cmd_pipe_plus.mc_address_reg[14] [12]),\n .I3(\\app_addr_r1_reg[27] [12]),\n .I4(\\app_addr_r1_reg[27] [13]),\n .I5(\\cmd_pipe_plus.mc_address_reg[14] [13]),\n .O(row_hit_ns_carry__0_i_1_n_0));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n row_hit_ns_carry_i_1\n (.I0(\\cmd_pipe_plus.mc_address_reg[14] [11]),\n .I1(\\app_addr_r1_reg[27] [11]),\n .I2(\\cmd_pipe_plus.mc_address_reg[14] [10]),\n .I3(\\app_addr_r1_reg[27] [10]),\n .I4(\\app_addr_r1_reg[27] [9]),\n .I5(\\cmd_pipe_plus.mc_address_reg[14] [9]),\n .O(row_hit_ns_carry_i_1_n_0));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n row_hit_ns_carry_i_2\n (.I0(\\cmd_pipe_plus.mc_address_reg[14] [8]),\n .I1(\\app_addr_r1_reg[27] [8]),\n .I2(\\cmd_pipe_plus.mc_address_reg[14] [7]),\n .I3(\\app_addr_r1_reg[27] [7]),\n .I4(\\app_addr_r1_reg[27] [6]),\n .I5(\\cmd_pipe_plus.mc_address_reg[14] [6]),\n .O(row_hit_ns_carry_i_2_n_0));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n row_hit_ns_carry_i_3\n (.I0(\\cmd_pipe_plus.mc_address_reg[14] [5]),\n .I1(\\app_addr_r1_reg[27] [5]),\n .I2(\\cmd_pipe_plus.mc_address_reg[14] [4]),\n .I3(\\app_addr_r1_reg[27] [4]),\n .I4(\\app_addr_r1_reg[27] [3]),\n .I5(\\cmd_pipe_plus.mc_address_reg[14] [3]),\n .O(row_hit_ns_carry_i_3_n_0));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n row_hit_ns_carry_i_4\n (.I0(\\cmd_pipe_plus.mc_address_reg[14] [2]),\n .I1(\\app_addr_r1_reg[27] [2]),\n .I2(\\cmd_pipe_plus.mc_address_reg[14] [1]),\n .I3(\\app_addr_r1_reg[27] [1]),\n .I4(\\app_addr_r1_reg[27] [0]),\n .I5(\\cmd_pipe_plus.mc_address_reg[14] [0]),\n .O(row_hit_ns_carry_i_4_n_0));\n FDRE row_hit_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(row_hit_ns),\n .Q(row_hit_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1051\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\wr_this_rank_r[0]_i_1 \n (.I0(\\rd_this_rank_r_reg[0] ),\n .O(start_wtp_timer0));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_bank_mach\n (accept_internal_r,\n periodic_rd_ack_r,\n \\q_entry_r_reg[1] ,\n accept_ns,\n was_wr,\n insert_maint_r,\n sent_row,\n \\cmd_pipe_plus.mc_cmd_reg[0] ,\n insert_maint_r1,\n cs_en2,\n DIC,\n col_rd_wr,\n col_data_buf_addr,\n cke_r,\n idle_r,\n rd_wr_r,\n req_wr_r,\n rb_hit_busy_r,\n row_hit_r,\n bm_end_r1,\n \\act_this_rank_r_reg[0] ,\n ras_timer_zero_r,\n demand_priority_r,\n demanded_prior_r,\n act_wait_r_lcl_reg,\n pre_bm_end_r,\n q_has_rd,\n q_has_priority,\n row_hit_r_0,\n bm_end_r1_0,\n demand_priority_r_1,\n act_wait_r_lcl_reg_0,\n pre_bm_end_r_2,\n q_has_rd_3,\n q_has_priority_4,\n row_hit_r_5,\n \\ras_timer_r_reg[2] ,\n ras_timer_zero_r_6,\n demand_priority_r_7,\n demanded_prior_r_8,\n override_demand_r,\n act_wait_r_lcl_reg_1,\n pre_bm_end_r_9,\n q_has_rd_10,\n q_has_priority_11,\n row_hit_r_12,\n bm_end_r1_4,\n demand_priority_r_13,\n demanded_prior_r_14,\n act_wait_r_lcl_reg_2,\n pre_bm_end_r_15,\n q_has_rd_16,\n q_has_priority_17,\n maint_wip_r,\n wait_for_maint_r,\n wait_for_maint_r_18,\n wait_for_maint_r_19,\n wait_for_maint_r_20,\n rnk_config_valid_r,\n col_wait_r,\n col_wait_r_21,\n col_wait_r_22,\n col_wait_r_23,\n periodic_rd_cntr_r,\n tail_r,\n head_r,\n auto_pre_r,\n ordered_r,\n tail_r_24,\n auto_pre_r_25,\n tail_r_26,\n auto_pre_r_27,\n tail_r_28,\n auto_pre_r_29,\n \\cmd_pipe_plus.mc_data_offset_1_reg[0] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ,\n \\rtw_timer.rtw_cnt_r_reg[1] ,\n Q,\n rb_hit_busy_r_reg,\n accept_internal_r_reg,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] ,\n \\q_entry_r_reg[0] ,\n rb_hit_busy_r_reg_0,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ,\n rb_hit_busy_r_reg_1,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ,\n \\q_entry_r_reg[1]_0 ,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ,\n \\q_entry_r_reg[1]_1 ,\n \\q_entry_r_reg[0]_0 ,\n clear_periodic_rd_request,\n \\periodic_rd_generation.periodic_rd_timer_r_reg[2] ,\n read_this_rank,\n E,\n \\rnk_config_strobe_r_reg[0] ,\n rnk_config_valid_r_lcl_reg,\n \\last_master_r_reg[3] ,\n \\ras_timer_r_reg[0] ,\n \\ras_timer_r_reg[0]_0 ,\n \\ras_timer_r_reg[0]_1 ,\n \\ras_timer_r_reg[0]_2 ,\n \\ras_timer_r_reg[0]_3 ,\n \\ras_timer_r_reg[0]_4 ,\n ordered_r_lcl_reg,\n q_entry_r,\n head_r_lcl_reg,\n \\q_entry_r_reg[1]_2 ,\n \\q_entry_r_reg[1]_3 ,\n ordered_r_lcl_reg_0,\n q_entry_r_30,\n \\maint_controller.maint_rdy_r1_reg ,\n rtp_timer_r,\n head_r_lcl_reg_0,\n \\q_entry_r_reg[1]_4 ,\n \\q_entry_r_reg[1]_5 ,\n ordered_r_lcl_reg_1,\n head_r_lcl_reg_1,\n head_r_lcl_reg_2,\n \\q_entry_r_reg[1]_6 ,\n \\q_entry_r_reg[0]_1 ,\n head_r_lcl_reg_3,\n head_r_lcl_reg_4,\n \\grant_r_reg[2] ,\n \\ras_timer_r_reg[0]_5 ,\n \\ras_timer_r_reg[0]_6 ,\n \\compute_tail.tail_r_lcl_reg ,\n \\grant_r_reg[1] ,\n pass_open_bank_r_lcl_reg,\n \\grant_r_reg[1]_0 ,\n \\grant_r_reg[3] ,\n pass_open_bank_r_lcl_reg_0,\n mc_we_n_ns,\n mc_cas_n_ns,\n mc_ras_n_ns,\n \\cmd_pipe_plus.mc_bank_reg[8] ,\n \\cmd_pipe_plus.mc_bank_reg[2] ,\n \\cmd_pipe_plus.mc_bank_reg[2]_0 ,\n \\cmd_pipe_plus.mc_bank_reg[8]_0 ,\n \\cmd_pipe_plus.mc_bank_reg[8]_1 ,\n \\cmd_pipe_plus.mc_address_reg[44] ,\n \\cmd_pipe_plus.mc_address_reg[10] ,\n mc_cs_n_ns,\n \\last_master_r_reg[3]_0 ,\n \\grant_r_reg[3]_0 ,\n \\cmd_pipe_plus.mc_bank_reg[7] ,\n \\last_master_r_reg[3]_1 ,\n auto_pre_r_lcl_reg,\n auto_pre_r_lcl_reg_0,\n head_r_lcl_reg_5,\n auto_pre_r_lcl_reg_1,\n auto_pre_r_lcl_reg_2,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6] ,\n \\grant_r_reg[1]_1 ,\n demanded_prior_r_reg,\n act_this_rank,\n \\inhbt_act_faw.inhbt_act_faw_r_reg ,\n \\wtr_timer.wtr_cnt_r_reg[0] ,\n \\wtr_timer.wtr_cnt_r_reg[1] ,\n \\wtr_timer.wtr_cnt_r_reg[1]_0 ,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ,\n demanded_prior_r_reg_0,\n \\cmd_pipe_plus.mc_we_n_reg[1] ,\n \\maint_controller.maint_hit_busies_r_reg[3] ,\n CLK,\n maint_srx_r,\n rstdiv0_sync_r1_reg_rep__0,\n mc_cke_ns,\n hi_priority,\n SR,\n q_has_rd_r_reg,\n q_has_priority_r_reg,\n q_has_rd_r_reg_0,\n q_has_priority_r_reg_0,\n q_has_rd_r_reg_1,\n q_has_priority_r_reg_1,\n q_has_rd_r_reg_2,\n q_has_priority_r_reg_2,\n of_ctl_full_v,\n phy_mc_ctl_full,\n \\maintenance_request.maint_req_r_lcl_reg ,\n wait_for_maint_r_lcl_reg,\n wait_for_maint_r_lcl_reg_0,\n wait_for_maint_r_lcl_reg_1,\n wait_for_maint_r_lcl_reg_2,\n rnk_config_valid_r_lcl_reg_0,\n \\periodic_read_request.periodic_rd_r_lcl_reg ,\n idle_r_lcl_reg,\n head_r_lcl_reg_6,\n auto_pre_r_lcl_reg_3,\n ordered_r_lcl_reg_2,\n idle_r_lcl_reg_0,\n head_r_lcl_reg_7,\n auto_pre_r_lcl_reg_4,\n ordered_r_lcl_reg_3,\n idle_r_lcl_reg_1,\n head_r_lcl_reg_8,\n auto_pre_r_lcl_reg_5,\n ordered_r_lcl_reg_4,\n idle_r_lcl_reg_2,\n head_r_lcl_reg_9,\n auto_pre_r_lcl_reg_6,\n ordered_r_lcl_reg_5,\n rd_wr_r_lcl_reg,\n \\req_bank_r_lcl_reg[2] ,\n rstdiv0_sync_r1_reg_rep__20,\n \\req_bank_r_lcl_reg[2]_0 ,\n \\req_bank_r_lcl_reg[0] ,\n \\req_bank_r_lcl_reg[0]_0 ,\n \\entry_cnt_reg[2] ,\n \\entry_cnt_reg[2]_0 ,\n periodic_rd_grant_r,\n read_this_rank_r,\n rstdiv0_sync_r1_reg_rep__21,\n \\wtr_timer.wtr_cnt_r_reg[1]_1 ,\n col_wait_r_reg,\n col_wait_r_reg_0,\n override_demand_r_reg,\n override_demand_r_reg_0,\n col_wait_r_reg_1,\n col_wait_r_reg_2,\n override_demand_r_reg_1,\n \\rtw_timer.rtw_cnt_r_reg[1]_0 ,\n bm_end_r1_reg,\n bm_end_r1_reg_0,\n idle_r_lcl_reg_3,\n bm_end_r1_reg_1,\n idle_r_lcl_reg_4,\n D,\n pass_open_bank_r_lcl_reg_1,\n req_wr_r_lcl_reg,\n accept_r_reg,\n \\app_cmd_r2_reg[1] ,\n \\app_cmd_r1_reg[0] ,\n periodic_rd_r,\n periodic_rd_ack_r_lcl_reg,\n init_calib_complete_reg_rep__6,\n use_addr,\n bm_end_r1_reg_2,\n req_wr_r_lcl_reg_0,\n req_wr_r_lcl_reg_1,\n req_wr_r_lcl_reg_2,\n rtp_timer_ns1,\n accept_r_reg_0,\n rtp_timer_ns1_6,\n rtp_timer_ns1_7,\n maint_zq_r,\n granted_row_r_reg,\n granted_row_r_reg_0,\n ras_timer_zero_r_reg,\n ras_timer_zero_r_reg_0,\n \\last_master_r_reg[3]_2 ,\n inhbt_act_faw_r,\n \\last_master_r_reg[3]_3 ,\n rstdiv0_sync_r1_reg_rep__22,\n maint_req_r,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ,\n \\generate_maint_cmds.insert_maint_r_lcl_reg ,\n \\maintenance_request.maint_zq_r_lcl_reg ,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ,\n \\app_addr_r1_reg[27] ,\n \\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ,\n act_wait_r_lcl_reg_3,\n \\req_bank_r_lcl_reg[2]_1 ,\n \\grant_r_reg[0] ,\n \\grant_r_reg[0]_0 ,\n \\grant_r_reg[0]_1 ,\n \\grant_r_reg[0]_2 ,\n \\grant_r_reg[0]_3 ,\n \\grant_r_reg[0]_4 ,\n \\grant_r_reg[0]_5 ,\n \\grant_r_reg[0]_6 ,\n \\grant_r_reg[0]_7 ,\n \\grant_r_reg[0]_8 ,\n \\grant_r_reg[0]_9 ,\n \\grant_r_reg[0]_10 ,\n \\grant_r_reg[0]_11 ,\n \\grant_r_reg[0]_12 ,\n \\req_bank_r_lcl_reg[0]_1 ,\n \\req_bank_r_lcl_reg[1] ,\n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ,\n \\app_addr_r1_reg[12] ,\n \\app_addr_r1_reg[9] ,\n rb_hit_busy_r_reg_2,\n pass_open_bank_r_lcl_reg_2,\n idle_r_lcl_reg_5,\n idle_r_lcl_reg_6,\n idle_r_lcl_reg_7);\n output accept_internal_r;\n output periodic_rd_ack_r;\n output \\q_entry_r_reg[1] ;\n output accept_ns;\n output was_wr;\n output insert_maint_r;\n output sent_row;\n output \\cmd_pipe_plus.mc_cmd_reg[0] ;\n output insert_maint_r1;\n output cs_en2;\n output [0:0]DIC;\n output col_rd_wr;\n output [4:0]col_data_buf_addr;\n output cke_r;\n output [3:0]idle_r;\n output [3:0]rd_wr_r;\n output [3:0]req_wr_r;\n output [3:0]rb_hit_busy_r;\n output row_hit_r;\n output bm_end_r1;\n output [2:0]\\act_this_rank_r_reg[0] ;\n output ras_timer_zero_r;\n output demand_priority_r;\n output demanded_prior_r;\n output act_wait_r_lcl_reg;\n output pre_bm_end_r;\n output q_has_rd;\n output q_has_priority;\n output row_hit_r_0;\n output bm_end_r1_0;\n output demand_priority_r_1;\n output act_wait_r_lcl_reg_0;\n output pre_bm_end_r_2;\n output q_has_rd_3;\n output q_has_priority_4;\n output row_hit_r_5;\n output \\ras_timer_r_reg[2] ;\n output ras_timer_zero_r_6;\n output demand_priority_r_7;\n output demanded_prior_r_8;\n output override_demand_r;\n output act_wait_r_lcl_reg_1;\n output pre_bm_end_r_9;\n output q_has_rd_10;\n output q_has_priority_11;\n output row_hit_r_12;\n output bm_end_r1_4;\n output demand_priority_r_13;\n output demanded_prior_r_14;\n output act_wait_r_lcl_reg_2;\n output pre_bm_end_r_15;\n output q_has_rd_16;\n output q_has_priority_17;\n output maint_wip_r;\n output wait_for_maint_r;\n output wait_for_maint_r_18;\n output wait_for_maint_r_19;\n output wait_for_maint_r_20;\n output rnk_config_valid_r;\n output col_wait_r;\n output col_wait_r_21;\n output col_wait_r_22;\n output col_wait_r_23;\n output periodic_rd_cntr_r;\n output tail_r;\n output [3:0]head_r;\n output auto_pre_r;\n output [3:0]ordered_r;\n output tail_r_24;\n output auto_pre_r_25;\n output tail_r_26;\n output auto_pre_r_27;\n output tail_r_28;\n output auto_pre_r_29;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[0] ;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ;\n output \\rtw_timer.rtw_cnt_r_reg[1] ;\n output [3:0]Q;\n output rb_hit_busy_r_reg;\n output accept_internal_r_reg;\n output [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] ;\n output \\q_entry_r_reg[0] ;\n output rb_hit_busy_r_reg_0;\n output [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;\n output rb_hit_busy_r_reg_1;\n output [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;\n output \\q_entry_r_reg[1]_0 ;\n output [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;\n output \\q_entry_r_reg[1]_1 ;\n output \\q_entry_r_reg[0]_0 ;\n output clear_periodic_rd_request;\n output \\periodic_rd_generation.periodic_rd_timer_r_reg[2] ;\n output read_this_rank;\n output [0:0]E;\n output \\rnk_config_strobe_r_reg[0] ;\n output rnk_config_valid_r_lcl_reg;\n output [2:0]\\last_master_r_reg[3] ;\n output \\ras_timer_r_reg[0] ;\n output \\ras_timer_r_reg[0]_0 ;\n output \\ras_timer_r_reg[0]_1 ;\n output \\ras_timer_r_reg[0]_2 ;\n output \\ras_timer_r_reg[0]_3 ;\n output \\ras_timer_r_reg[0]_4 ;\n output ordered_r_lcl_reg;\n output [1:0]q_entry_r;\n output head_r_lcl_reg;\n output \\q_entry_r_reg[1]_2 ;\n output \\q_entry_r_reg[1]_3 ;\n output ordered_r_lcl_reg_0;\n output [1:0]q_entry_r_30;\n output \\maint_controller.maint_rdy_r1_reg ;\n output [1:0]rtp_timer_r;\n output head_r_lcl_reg_0;\n output \\q_entry_r_reg[1]_4 ;\n output \\q_entry_r_reg[1]_5 ;\n output ordered_r_lcl_reg_1;\n output head_r_lcl_reg_1;\n output head_r_lcl_reg_2;\n output \\q_entry_r_reg[1]_6 ;\n output \\q_entry_r_reg[0]_1 ;\n output head_r_lcl_reg_3;\n output head_r_lcl_reg_4;\n output \\grant_r_reg[2] ;\n output \\ras_timer_r_reg[0]_5 ;\n output \\ras_timer_r_reg[0]_6 ;\n output \\compute_tail.tail_r_lcl_reg ;\n output \\grant_r_reg[1] ;\n output pass_open_bank_r_lcl_reg;\n output \\grant_r_reg[1]_0 ;\n output \\grant_r_reg[3] ;\n output pass_open_bank_r_lcl_reg_0;\n output [1:0]mc_we_n_ns;\n output [1:0]mc_cas_n_ns;\n output [1:0]mc_ras_n_ns;\n output [8:0]\\cmd_pipe_plus.mc_bank_reg[8] ;\n output [2:0]\\cmd_pipe_plus.mc_bank_reg[2] ;\n output [2:0]\\cmd_pipe_plus.mc_bank_reg[2]_0 ;\n output [2:0]\\cmd_pipe_plus.mc_bank_reg[8]_0 ;\n output [2:0]\\cmd_pipe_plus.mc_bank_reg[8]_1 ;\n output [37:0]\\cmd_pipe_plus.mc_address_reg[44] ;\n output [28:0]\\cmd_pipe_plus.mc_address_reg[10] ;\n output [0:0]mc_cs_n_ns;\n output [0:0]\\last_master_r_reg[3]_0 ;\n output \\grant_r_reg[3]_0 ;\n output [3:0]\\cmd_pipe_plus.mc_bank_reg[7] ;\n output [0:0]\\last_master_r_reg[3]_1 ;\n output auto_pre_r_lcl_reg;\n output auto_pre_r_lcl_reg_0;\n output head_r_lcl_reg_5;\n output auto_pre_r_lcl_reg_1;\n output auto_pre_r_lcl_reg_2;\n output [4:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6] ;\n output \\grant_r_reg[1]_1 ;\n output demanded_prior_r_reg;\n output act_this_rank;\n output \\inhbt_act_faw.inhbt_act_faw_r_reg ;\n output \\wtr_timer.wtr_cnt_r_reg[0] ;\n output \\wtr_timer.wtr_cnt_r_reg[1] ;\n output \\wtr_timer.wtr_cnt_r_reg[1]_0 ;\n output [0:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ;\n output demanded_prior_r_reg_0;\n output \\cmd_pipe_plus.mc_we_n_reg[1] ;\n output [3:0]\\maint_controller.maint_hit_busies_r_reg[3] ;\n input CLK;\n input maint_srx_r;\n input rstdiv0_sync_r1_reg_rep__0;\n input [0:0]mc_cke_ns;\n input hi_priority;\n input [0:0]SR;\n input q_has_rd_r_reg;\n input q_has_priority_r_reg;\n input q_has_rd_r_reg_0;\n input q_has_priority_r_reg_0;\n input q_has_rd_r_reg_1;\n input q_has_priority_r_reg_1;\n input q_has_rd_r_reg_2;\n input q_has_priority_r_reg_2;\n input [0:0]of_ctl_full_v;\n input phy_mc_ctl_full;\n input \\maintenance_request.maint_req_r_lcl_reg ;\n input wait_for_maint_r_lcl_reg;\n input wait_for_maint_r_lcl_reg_0;\n input wait_for_maint_r_lcl_reg_1;\n input wait_for_maint_r_lcl_reg_2;\n input rnk_config_valid_r_lcl_reg_0;\n input \\periodic_read_request.periodic_rd_r_lcl_reg ;\n input idle_r_lcl_reg;\n input head_r_lcl_reg_6;\n input auto_pre_r_lcl_reg_3;\n input ordered_r_lcl_reg_2;\n input idle_r_lcl_reg_0;\n input head_r_lcl_reg_7;\n input auto_pre_r_lcl_reg_4;\n input ordered_r_lcl_reg_3;\n input idle_r_lcl_reg_1;\n input head_r_lcl_reg_8;\n input auto_pre_r_lcl_reg_5;\n input ordered_r_lcl_reg_4;\n input idle_r_lcl_reg_2;\n input head_r_lcl_reg_9;\n input auto_pre_r_lcl_reg_6;\n input ordered_r_lcl_reg_5;\n input rd_wr_r_lcl_reg;\n input \\req_bank_r_lcl_reg[2] ;\n input rstdiv0_sync_r1_reg_rep__20;\n input \\req_bank_r_lcl_reg[2]_0 ;\n input \\req_bank_r_lcl_reg[0] ;\n input \\req_bank_r_lcl_reg[0]_0 ;\n input \\entry_cnt_reg[2] ;\n input \\entry_cnt_reg[2]_0 ;\n input periodic_rd_grant_r;\n input read_this_rank_r;\n input rstdiv0_sync_r1_reg_rep__21;\n input \\wtr_timer.wtr_cnt_r_reg[1]_1 ;\n input col_wait_r_reg;\n input col_wait_r_reg_0;\n input override_demand_r_reg;\n input override_demand_r_reg_0;\n input col_wait_r_reg_1;\n input col_wait_r_reg_2;\n input override_demand_r_reg_1;\n input [0:0]\\rtw_timer.rtw_cnt_r_reg[1]_0 ;\n input bm_end_r1_reg;\n input bm_end_r1_reg_0;\n input idle_r_lcl_reg_3;\n input bm_end_r1_reg_1;\n input idle_r_lcl_reg_4;\n input [3:0]D;\n input pass_open_bank_r_lcl_reg_1;\n input req_wr_r_lcl_reg;\n input accept_r_reg;\n input [0:0]\\app_cmd_r2_reg[1] ;\n input \\app_cmd_r1_reg[0] ;\n input periodic_rd_r;\n input periodic_rd_ack_r_lcl_reg;\n input init_calib_complete_reg_rep__6;\n input use_addr;\n input bm_end_r1_reg_2;\n input req_wr_r_lcl_reg_0;\n input req_wr_r_lcl_reg_1;\n input req_wr_r_lcl_reg_2;\n input rtp_timer_ns1;\n input accept_r_reg_0;\n input rtp_timer_ns1_6;\n input rtp_timer_ns1_7;\n input maint_zq_r;\n input granted_row_r_reg;\n input granted_row_r_reg_0;\n input ras_timer_zero_r_reg;\n input ras_timer_zero_r_reg_0;\n input \\last_master_r_reg[3]_2 ;\n input inhbt_act_faw_r;\n input \\last_master_r_reg[3]_3 ;\n input rstdiv0_sync_r1_reg_rep__22;\n input maint_req_r;\n input [2:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ;\n input \\generate_maint_cmds.insert_maint_r_lcl_reg ;\n input \\maintenance_request.maint_zq_r_lcl_reg ;\n input \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ;\n input [14:0]\\app_addr_r1_reg[27] ;\n input [3:0]\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ;\n input act_wait_r_lcl_reg_3;\n input \\req_bank_r_lcl_reg[2]_1 ;\n input \\grant_r_reg[0] ;\n input \\grant_r_reg[0]_0 ;\n input \\grant_r_reg[0]_1 ;\n input \\grant_r_reg[0]_2 ;\n input \\grant_r_reg[0]_3 ;\n input \\grant_r_reg[0]_4 ;\n input \\grant_r_reg[0]_5 ;\n input \\grant_r_reg[0]_6 ;\n input \\grant_r_reg[0]_7 ;\n input \\grant_r_reg[0]_8 ;\n input \\grant_r_reg[0]_9 ;\n input \\grant_r_reg[0]_10 ;\n input \\grant_r_reg[0]_11 ;\n input \\grant_r_reg[0]_12 ;\n input \\req_bank_r_lcl_reg[0]_1 ;\n input \\req_bank_r_lcl_reg[1] ;\n input [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n input [2:0]\\app_addr_r1_reg[12] ;\n input [6:0]\\app_addr_r1_reg[9] ;\n input rb_hit_busy_r_reg_2;\n input pass_open_bank_r_lcl_reg_2;\n input idle_r_lcl_reg_5;\n input idle_r_lcl_reg_6;\n input idle_r_lcl_reg_7;\n\n wire CLK;\n wire [3:0]D;\n wire [0:0]DIC;\n wire [0:0]E;\n wire [3:0]Q;\n wire [0:0]SR;\n wire accept_internal_r;\n wire accept_internal_r_reg;\n wire accept_ns;\n wire accept_r_reg;\n wire accept_r_reg_0;\n wire act_this_rank;\n wire [3:0]act_this_rank_r;\n wire [2:0]\\act_this_rank_r_reg[0] ;\n wire act_wait_r_lcl_reg;\n wire act_wait_r_lcl_reg_0;\n wire act_wait_r_lcl_reg_1;\n wire act_wait_r_lcl_reg_2;\n wire act_wait_r_lcl_reg_3;\n wire [2:0]\\app_addr_r1_reg[12] ;\n wire [14:0]\\app_addr_r1_reg[27] ;\n wire [6:0]\\app_addr_r1_reg[9] ;\n wire \\app_cmd_r1_reg[0] ;\n wire [0:0]\\app_cmd_r2_reg[1] ;\n wire arb_mux0_n_106;\n wire arb_mux0_n_22;\n wire arb_mux0_n_46;\n wire arb_mux0_n_85;\n wire arb_mux0_n_86;\n wire arb_mux0_n_88;\n wire arb_mux0_n_89;\n wire arb_mux0_n_96;\n wire arb_mux0_n_97;\n wire arb_mux0_n_98;\n wire arb_mux0_n_99;\n wire \\arb_row_col0/granted_col_ns ;\n wire auto_pre_r;\n wire auto_pre_r_25;\n wire auto_pre_r_27;\n wire auto_pre_r_29;\n wire auto_pre_r_lcl_reg;\n wire auto_pre_r_lcl_reg_0;\n wire auto_pre_r_lcl_reg_1;\n wire auto_pre_r_lcl_reg_2;\n wire auto_pre_r_lcl_reg_3;\n wire auto_pre_r_lcl_reg_4;\n wire auto_pre_r_lcl_reg_5;\n wire auto_pre_r_lcl_reg_6;\n wire \\bank_cntrl[0].bank0_n_32 ;\n wire \\bank_cntrl[0].bank0_n_33 ;\n wire \\bank_cntrl[0].bank0_n_34 ;\n wire \\bank_cntrl[0].bank0_n_38 ;\n wire \\bank_cntrl[0].bank0_n_39 ;\n wire \\bank_cntrl[0].bank0_n_41 ;\n wire \\bank_cntrl[0].bank0_n_43 ;\n wire \\bank_cntrl[0].bank0_n_44 ;\n wire \\bank_cntrl[0].bank0_n_45 ;\n wire \\bank_cntrl[0].bank0_n_48 ;\n wire \\bank_cntrl[0].bank0_n_49 ;\n wire \\bank_cntrl[0].bank0_n_55 ;\n wire \\bank_cntrl[0].bank0_n_56 ;\n wire \\bank_cntrl[0].bank0_n_74 ;\n wire \\bank_cntrl[1].bank0_n_30 ;\n wire \\bank_cntrl[1].bank0_n_31 ;\n wire \\bank_cntrl[1].bank0_n_35 ;\n wire \\bank_cntrl[1].bank0_n_36 ;\n wire \\bank_cntrl[1].bank0_n_37 ;\n wire \\bank_cntrl[1].bank0_n_41 ;\n wire \\bank_cntrl[1].bank0_n_43 ;\n wire \\bank_cntrl[1].bank0_n_46 ;\n wire \\bank_cntrl[1].bank0_n_49 ;\n wire \\bank_cntrl[1].bank0_n_51 ;\n wire \\bank_cntrl[1].bank0_n_52 ;\n wire \\bank_cntrl[1].bank0_n_53 ;\n wire \\bank_cntrl[1].bank0_n_69 ;\n wire \\bank_cntrl[1].bank0_n_70 ;\n wire \\bank_cntrl[1].bank0_n_71 ;\n wire \\bank_cntrl[2].bank0_n_35 ;\n wire \\bank_cntrl[2].bank0_n_36 ;\n wire \\bank_cntrl[2].bank0_n_37 ;\n wire \\bank_cntrl[2].bank0_n_38 ;\n wire \\bank_cntrl[2].bank0_n_39 ;\n wire \\bank_cntrl[2].bank0_n_40 ;\n wire \\bank_cntrl[2].bank0_n_41 ;\n wire \\bank_cntrl[2].bank0_n_45 ;\n wire \\bank_cntrl[2].bank0_n_54 ;\n wire \\bank_cntrl[2].bank0_n_56 ;\n wire \\bank_cntrl[2].bank0_n_58 ;\n wire \\bank_cntrl[2].bank0_n_74 ;\n wire \\bank_cntrl[3].bank0_n_31 ;\n wire \\bank_cntrl[3].bank0_n_32 ;\n wire \\bank_cntrl[3].bank0_n_33 ;\n wire \\bank_cntrl[3].bank0_n_37 ;\n wire \\bank_cntrl[3].bank0_n_38 ;\n wire \\bank_cntrl[3].bank0_n_39 ;\n wire \\bank_cntrl[3].bank0_n_48 ;\n wire \\bank_cntrl[3].bank0_n_49 ;\n wire \\bank_cntrl[3].bank0_n_65 ;\n wire \\bank_cntrl[3].bank0_n_66 ;\n wire \\bank_cntrl[3].bank0_n_67 ;\n wire \\bank_cntrl[3].bank0_n_69 ;\n wire bank_common0_n_10;\n wire bank_common0_n_12;\n wire bank_common0_n_14;\n wire bank_common0_n_16;\n wire bank_common0_n_19;\n wire [9:3]\\bank_compare0/req_col_r ;\n wire [9:3]\\bank_compare0/req_col_r_13 ;\n wire [9:3]\\bank_compare0/req_col_r_2 ;\n wire [9:3]\\bank_compare0/req_col_r_7 ;\n wire [1:1]\\bank_queue0/q_entry_ns ;\n wire [4:2]\\bank_queue0/rb_hit_busies_ns ;\n wire [5:3]\\bank_queue0/rb_hit_busies_ns_0 ;\n wire [6:4]\\bank_queue0/rb_hit_busies_ns_1 ;\n wire [3:1]\\bank_queue0/rb_hit_busies_ns_4 ;\n wire \\bank_state0/demanded_prior_r ;\n wire \\bank_state0/ofs_rdy_r ;\n wire \\bank_state0/ofs_rdy_r0 ;\n wire \\bank_state0/ofs_rdy_r0_10 ;\n wire \\bank_state0/ofs_rdy_r0_9 ;\n wire \\bank_state0/ofs_rdy_r_11 ;\n wire \\bank_state0/ofs_rdy_r_15 ;\n wire \\bank_state0/ofs_rdy_r_5 ;\n wire \\bank_state0/override_demand_ns ;\n wire \\bank_state0/req_bank_rdy_ns ;\n wire \\bank_state0/req_bank_rdy_ns_12 ;\n wire \\bank_state0/req_bank_rdy_ns_16 ;\n wire \\bank_state0/req_bank_rdy_ns_6 ;\n wire \\bank_state0/req_bank_rdy_r ;\n wire bm_end_r1;\n wire bm_end_r1_0;\n wire bm_end_r1_4;\n wire bm_end_r1_reg;\n wire bm_end_r1_reg_0;\n wire bm_end_r1_reg_1;\n wire bm_end_r1_reg_2;\n wire cke_r;\n wire clear_periodic_rd_request;\n wire [28:0]\\cmd_pipe_plus.mc_address_reg[10] ;\n wire [37:0]\\cmd_pipe_plus.mc_address_reg[44] ;\n wire [2:0]\\cmd_pipe_plus.mc_bank_reg[2] ;\n wire [2:0]\\cmd_pipe_plus.mc_bank_reg[2]_0 ;\n wire [3:0]\\cmd_pipe_plus.mc_bank_reg[7] ;\n wire [8:0]\\cmd_pipe_plus.mc_bank_reg[8] ;\n wire [2:0]\\cmd_pipe_plus.mc_bank_reg[8]_0 ;\n wire [2:0]\\cmd_pipe_plus.mc_bank_reg[8]_1 ;\n wire \\cmd_pipe_plus.mc_cmd_reg[0] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[0] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ;\n wire \\cmd_pipe_plus.mc_we_n_reg[1] ;\n wire [4:0]col_data_buf_addr;\n wire col_rd_wr;\n wire col_wait_r;\n wire col_wait_r_21;\n wire col_wait_r_22;\n wire col_wait_r_23;\n wire col_wait_r_reg;\n wire col_wait_r_reg_0;\n wire col_wait_r_reg_1;\n wire col_wait_r_reg_2;\n wire \\compute_tail.tail_r_lcl_reg ;\n wire cs_en2;\n wire [3:0]\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ;\n wire demand_priority_r;\n wire demand_priority_r_1;\n wire demand_priority_r_13;\n wire demand_priority_r_7;\n wire demanded_prior_r;\n wire demanded_prior_r_14;\n wire demanded_prior_r_8;\n wire demanded_prior_r_reg;\n wire demanded_prior_r_reg_0;\n wire \\entry_cnt_reg[2] ;\n wire \\entry_cnt_reg[2]_0 ;\n wire \\generate_maint_cmds.insert_maint_r_lcl_reg ;\n wire \\grant_r_reg[0] ;\n wire \\grant_r_reg[0]_0 ;\n wire \\grant_r_reg[0]_1 ;\n wire \\grant_r_reg[0]_10 ;\n wire \\grant_r_reg[0]_11 ;\n wire \\grant_r_reg[0]_12 ;\n wire \\grant_r_reg[0]_2 ;\n wire \\grant_r_reg[0]_3 ;\n wire \\grant_r_reg[0]_4 ;\n wire \\grant_r_reg[0]_5 ;\n wire \\grant_r_reg[0]_6 ;\n wire \\grant_r_reg[0]_7 ;\n wire \\grant_r_reg[0]_8 ;\n wire \\grant_r_reg[0]_9 ;\n wire \\grant_r_reg[1] ;\n wire \\grant_r_reg[1]_0 ;\n wire \\grant_r_reg[1]_1 ;\n wire \\grant_r_reg[2] ;\n wire \\grant_r_reg[3] ;\n wire \\grant_r_reg[3]_0 ;\n wire granted_pre_ns;\n wire granted_row_ns;\n wire granted_row_r_reg;\n wire granted_row_r_reg_0;\n wire [3:0]head_r;\n wire head_r_lcl_reg;\n wire head_r_lcl_reg_0;\n wire head_r_lcl_reg_1;\n wire head_r_lcl_reg_2;\n wire head_r_lcl_reg_3;\n wire head_r_lcl_reg_4;\n wire head_r_lcl_reg_5;\n wire head_r_lcl_reg_6;\n wire head_r_lcl_reg_7;\n wire head_r_lcl_reg_8;\n wire head_r_lcl_reg_9;\n wire hi_priority;\n wire [3:0]idle_r;\n wire idle_r_lcl_reg;\n wire idle_r_lcl_reg_0;\n wire idle_r_lcl_reg_1;\n wire idle_r_lcl_reg_2;\n wire idle_r_lcl_reg_3;\n wire idle_r_lcl_reg_4;\n wire idle_r_lcl_reg_5;\n wire idle_r_lcl_reg_6;\n wire idle_r_lcl_reg_7;\n wire \\inhbt_act_faw.inhbt_act_faw_r_reg ;\n wire inhbt_act_faw_r;\n wire init_calib_complete_reg_rep__6;\n wire insert_maint_r;\n wire insert_maint_r1;\n wire [2:0]\\last_master_r_reg[3] ;\n wire [0:0]\\last_master_r_reg[3]_0 ;\n wire [0:0]\\last_master_r_reg[3]_1 ;\n wire \\last_master_r_reg[3]_2 ;\n wire \\last_master_r_reg[3]_3 ;\n wire [3:0]\\maint_controller.maint_hit_busies_r_reg[3] ;\n wire \\maint_controller.maint_rdy_r1_reg ;\n wire maint_req_r;\n wire maint_srx_r;\n wire maint_wip_r;\n wire maint_zq_r;\n wire \\maintenance_request.maint_req_r_lcl_reg ;\n wire \\maintenance_request.maint_zq_r_lcl_reg ;\n wire [1:0]mc_cas_n_ns;\n wire [0:0]mc_cke_ns;\n wire [0:0]mc_cs_n_ns;\n wire [1:0]mc_ras_n_ns;\n wire [1:0]mc_we_n_ns;\n wire [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n wire [0:0]of_ctl_full_v;\n wire [3:0]ordered_r;\n wire ordered_r_lcl_reg;\n wire ordered_r_lcl_reg_0;\n wire ordered_r_lcl_reg_1;\n wire ordered_r_lcl_reg_2;\n wire ordered_r_lcl_reg_3;\n wire ordered_r_lcl_reg_4;\n wire ordered_r_lcl_reg_5;\n wire override_demand_r;\n wire override_demand_r_reg;\n wire override_demand_r_reg_0;\n wire override_demand_r_reg_1;\n wire p_9_in;\n wire pass_open_bank_r_lcl_reg;\n wire pass_open_bank_r_lcl_reg_0;\n wire pass_open_bank_r_lcl_reg_1;\n wire pass_open_bank_r_lcl_reg_2;\n wire periodic_rd_ack_r;\n wire periodic_rd_ack_r_lcl_reg;\n wire periodic_rd_cntr_r;\n wire \\periodic_rd_generation.periodic_rd_timer_r_reg[2] ;\n wire periodic_rd_grant_r;\n wire periodic_rd_insert;\n wire periodic_rd_r;\n wire \\periodic_read_request.periodic_rd_r_lcl_reg ;\n wire phy_mc_ctl_full;\n wire pre_bm_end_r;\n wire pre_bm_end_r_15;\n wire pre_bm_end_r_2;\n wire pre_bm_end_r_9;\n wire [1:0]q_entry_r;\n wire [1:0]q_entry_r_30;\n wire \\q_entry_r_reg[0] ;\n wire \\q_entry_r_reg[0]_0 ;\n wire \\q_entry_r_reg[0]_1 ;\n wire \\q_entry_r_reg[1] ;\n wire \\q_entry_r_reg[1]_0 ;\n wire \\q_entry_r_reg[1]_1 ;\n wire \\q_entry_r_reg[1]_2 ;\n wire \\q_entry_r_reg[1]_3 ;\n wire \\q_entry_r_reg[1]_4 ;\n wire \\q_entry_r_reg[1]_5 ;\n wire \\q_entry_r_reg[1]_6 ;\n wire q_has_priority;\n wire q_has_priority_11;\n wire q_has_priority_17;\n wire q_has_priority_4;\n wire q_has_priority_r_reg;\n wire q_has_priority_r_reg_0;\n wire q_has_priority_r_reg_1;\n wire q_has_priority_r_reg_2;\n wire q_has_rd;\n wire q_has_rd_10;\n wire q_has_rd_16;\n wire q_has_rd_3;\n wire q_has_rd_r_reg;\n wire q_has_rd_r_reg_0;\n wire q_has_rd_r_reg_1;\n wire q_has_rd_r_reg_2;\n wire \\ras_timer_r_reg[0] ;\n wire \\ras_timer_r_reg[0]_0 ;\n wire \\ras_timer_r_reg[0]_1 ;\n wire \\ras_timer_r_reg[0]_2 ;\n wire \\ras_timer_r_reg[0]_3 ;\n wire \\ras_timer_r_reg[0]_4 ;\n wire \\ras_timer_r_reg[0]_5 ;\n wire \\ras_timer_r_reg[0]_6 ;\n wire \\ras_timer_r_reg[2] ;\n wire ras_timer_zero_r;\n wire ras_timer_zero_r_6;\n wire ras_timer_zero_r_reg;\n wire ras_timer_zero_r_reg_0;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;\n wire [3:2]rb_hit_busies_r;\n wire [6:4]rb_hit_busies_r_14;\n wire [4:2]rb_hit_busies_r_3;\n wire [4:3]rb_hit_busies_r_8;\n wire [3:0]rb_hit_busy_r;\n wire rb_hit_busy_r_reg;\n wire rb_hit_busy_r_reg_0;\n wire rb_hit_busy_r_reg_1;\n wire rb_hit_busy_r_reg_2;\n wire [3:0]rd_this_rank_r;\n wire [3:0]rd_wr_r;\n wire rd_wr_r_lcl_reg;\n wire read_this_rank;\n wire read_this_rank_r;\n wire \\req_bank_r_lcl_reg[0] ;\n wire \\req_bank_r_lcl_reg[0]_0 ;\n wire \\req_bank_r_lcl_reg[0]_1 ;\n wire \\req_bank_r_lcl_reg[1] ;\n wire \\req_bank_r_lcl_reg[2] ;\n wire \\req_bank_r_lcl_reg[2]_0 ;\n wire \\req_bank_r_lcl_reg[2]_1 ;\n wire [19:0]req_data_buf_addr_r;\n wire [3:0]req_periodic_rd_r;\n wire [59:10]req_row_r;\n wire [3:0]req_wr_r;\n wire req_wr_r_lcl_reg;\n wire req_wr_r_lcl_reg_0;\n wire req_wr_r_lcl_reg_1;\n wire req_wr_r_lcl_reg_2;\n wire [0:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ;\n wire \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ;\n wire [2:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ;\n wire [4:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6] ;\n wire \\rnk_config_strobe_r_reg[0] ;\n wire rnk_config_valid_r;\n wire rnk_config_valid_r_lcl_reg;\n wire rnk_config_valid_r_lcl_reg_0;\n wire [1:1]row_cmd_wr;\n wire row_hit_r;\n wire row_hit_r_0;\n wire row_hit_r_12;\n wire row_hit_r_5;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire rstdiv0_sync_r1_reg_rep__22;\n wire rtp_timer_ns1;\n wire rtp_timer_ns1_6;\n wire rtp_timer_ns1_7;\n wire [1:0]rtp_timer_r;\n wire \\rtw_timer.rtw_cnt_r_reg[1] ;\n wire [0:0]\\rtw_timer.rtw_cnt_r_reg[1]_0 ;\n wire [0:0]sending_row;\n wire sent_row;\n wire tail_r;\n wire tail_r_24;\n wire tail_r_26;\n wire tail_r_28;\n wire use_addr;\n wire wait_for_maint_r;\n wire wait_for_maint_r_18;\n wire wait_for_maint_r_19;\n wire wait_for_maint_r_20;\n wire wait_for_maint_r_lcl_reg;\n wire wait_for_maint_r_lcl_reg_0;\n wire wait_for_maint_r_lcl_reg_1;\n wire wait_for_maint_r_lcl_reg_2;\n wire was_wr;\n wire [3:0]wr_this_rank_r;\n wire \\wtr_timer.wtr_cnt_r_reg[0] ;\n wire \\wtr_timer.wtr_cnt_r_reg[1] ;\n wire \\wtr_timer.wtr_cnt_r_reg[1]_0 ;\n wire \\wtr_timer.wtr_cnt_r_reg[1]_1 ;\n\n ddr3_if_mig_7series_v4_0_arb_mux arb_mux0\n (.CLK(CLK),\n .DIC(DIC),\n .E(E),\n .Q(Q),\n .SR(SR),\n .act_this_rank(act_this_rank),\n .act_this_rank_r(act_this_rank_r),\n .act_wait_r_lcl_reg(\\act_this_rank_r_reg[0] [0]),\n .act_wait_r_lcl_reg_0(\\bank_cntrl[3].bank0_n_49 ),\n .act_wait_r_lcl_reg_1(\\act_this_rank_r_reg[0] [1]),\n .act_wait_r_lcl_reg_2(\\act_this_rank_r_reg[0] [2]),\n .auto_pre_r_lcl_reg(\\bank_cntrl[0].bank0_n_56 ),\n .auto_pre_r_lcl_reg_0(\\bank_cntrl[1].bank0_n_52 ),\n .auto_pre_r_lcl_reg_1(\\bank_cntrl[2].bank0_n_58 ),\n .auto_pre_r_lcl_reg_2(\\bank_cntrl[3].bank0_n_66 ),\n .auto_pre_r_lcl_reg_3(auto_pre_r_29),\n .auto_pre_r_lcl_reg_4(auto_pre_r),\n .auto_pre_r_lcl_reg_5(auto_pre_r_25),\n .auto_pre_r_lcl_reg_6(auto_pre_r_27),\n .cke_r(cke_r),\n .\\cmd_pipe_plus.mc_address_reg[44] ({\\cmd_pipe_plus.mc_address_reg[44] [37:34],\\cmd_pipe_plus.mc_address_reg[44] [32:0]}),\n .\\cmd_pipe_plus.mc_bank_reg[1] (arb_mux0_n_46),\n .\\cmd_pipe_plus.mc_bank_reg[7] (cs_en2),\n .\\cmd_pipe_plus.mc_bank_reg[7]_0 (\\cmd_pipe_plus.mc_bank_reg[7] ),\n .\\cmd_pipe_plus.mc_bank_reg[8] (\\cmd_pipe_plus.mc_bank_reg[8] ),\n .\\cmd_pipe_plus.mc_cmd_reg[0] (\\cmd_pipe_plus.mc_cmd_reg[0] ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[0] (\\cmd_pipe_plus.mc_data_offset_1_reg[0] ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 (\\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ),\n .\\cmd_pipe_plus.mc_ras_n_reg[0] (insert_maint_r1),\n .\\cmd_pipe_plus.mc_we_n_reg[1] (\\cmd_pipe_plus.mc_we_n_reg[1] ),\n .col_data_buf_addr(col_data_buf_addr),\n .col_rd_wr(col_rd_wr),\n .\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] (\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ),\n .demand_priority_r_reg(arb_mux0_n_106),\n .demand_priority_r_reg_0(\\bank_cntrl[3].bank0_n_69 ),\n .demand_priority_r_reg_1(\\bank_cntrl[2].bank0_n_74 ),\n .demand_priority_r_reg_2(\\bank_cntrl[0].bank0_n_74 ),\n .demand_priority_r_reg_3(\\bank_cntrl[1].bank0_n_69 ),\n .\\generate_maint_cmds.insert_maint_r_lcl_reg (insert_maint_r),\n .\\grant_r_reg[0] (\\grant_r_reg[0] ),\n .\\grant_r_reg[0]_0 (\\grant_r_reg[0]_0 ),\n .\\grant_r_reg[0]_1 (\\grant_r_reg[0]_1 ),\n .\\grant_r_reg[0]_10 (\\grant_r_reg[0]_10 ),\n .\\grant_r_reg[0]_11 (\\grant_r_reg[0]_11 ),\n .\\grant_r_reg[0]_12 (\\grant_r_reg[0]_12 ),\n .\\grant_r_reg[0]_2 (\\grant_r_reg[0]_2 ),\n .\\grant_r_reg[0]_3 (\\grant_r_reg[0]_3 ),\n .\\grant_r_reg[0]_4 (\\grant_r_reg[0]_4 ),\n .\\grant_r_reg[0]_5 (\\grant_r_reg[0]_5 ),\n .\\grant_r_reg[0]_6 (\\grant_r_reg[0]_6 ),\n .\\grant_r_reg[0]_7 (\\grant_r_reg[0]_7 ),\n .\\grant_r_reg[0]_8 (\\grant_r_reg[0]_8 ),\n .\\grant_r_reg[0]_9 (\\grant_r_reg[0]_9 ),\n .\\grant_r_reg[1] (\\grant_r_reg[1]_1 ),\n .\\grant_r_reg[1]_0 (arb_mux0_n_97),\n .\\grant_r_reg[1]_1 (arb_mux0_n_98),\n .\\grant_r_reg[2] (arb_mux0_n_85),\n .\\grant_r_reg[2]_0 (arb_mux0_n_99),\n .\\grant_r_reg[3] (arb_mux0_n_22),\n .\\grant_r_reg[3]_0 (arb_mux0_n_86),\n .\\grant_r_reg[3]_1 (\\grant_r_reg[3]_0 ),\n .\\grant_r_reg[3]_2 (arb_mux0_n_96),\n .granted_col_ns(\\arb_row_col0/granted_col_ns ),\n .granted_pre_ns(granted_pre_ns),\n .granted_row_ns(granted_row_ns),\n .granted_row_r_reg(granted_row_r_reg),\n .granted_row_r_reg_0(granted_row_r_reg_0),\n .\\inhbt_act_faw.inhbt_act_faw_r_reg (\\inhbt_act_faw.inhbt_act_faw_r_reg ),\n .inhbt_act_faw_r(inhbt_act_faw_r),\n .\\last_master_r_reg[0] (arb_mux0_n_89),\n .\\last_master_r_reg[2] (sent_row),\n .\\last_master_r_reg[2]_0 (arb_mux0_n_88),\n .\\last_master_r_reg[3] ({\\last_master_r_reg[3] ,sending_row}),\n .\\last_master_r_reg[3]_0 (\\last_master_r_reg[3]_1 ),\n .\\last_master_r_reg[3]_1 (\\last_master_r_reg[3]_0 ),\n .\\last_master_r_reg[3]_2 (\\last_master_r_reg[3]_2 ),\n .\\last_master_r_reg[3]_3 (\\last_master_r_reg[3]_3 ),\n .maint_srx_r(maint_srx_r),\n .maint_zq_r(maint_zq_r),\n .mc_cas_n_ns(mc_cas_n_ns),\n .mc_cke_ns(mc_cke_ns),\n .mc_cs_n_ns(mc_cs_n_ns),\n .mc_ras_n_ns(mc_ras_n_ns),\n .mc_we_n_ns(mc_we_n_ns),\n .ofs_rdy_r(\\bank_state0/ofs_rdy_r_15 ),\n .ofs_rdy_r_3(\\bank_state0/ofs_rdy_r_5 ),\n .ofs_rdy_r_4(\\bank_state0/ofs_rdy_r ),\n .ofs_rdy_r_5(\\bank_state0/ofs_rdy_r_11 ),\n .override_demand_ns(\\bank_state0/override_demand_ns ),\n .\\periodic_rd_generation.periodic_rd_timer_r_reg[2] (\\periodic_rd_generation.periodic_rd_timer_r_reg[2] ),\n .ras_timer_zero_r_reg(\\bank_cntrl[2].bank0_n_56 ),\n .ras_timer_zero_r_reg_0(ras_timer_zero_r_reg),\n .ras_timer_zero_r_reg_1(ras_timer_zero_r_reg_0),\n .ras_timer_zero_r_reg_2(\\bank_cntrl[1].bank0_n_53 ),\n .ras_timer_zero_r_reg_3(\\bank_cntrl[3].bank0_n_67 ),\n .ras_timer_zero_r_reg_4(\\bank_cntrl[3].bank0_n_65 ),\n .ras_timer_zero_r_reg_5(\\bank_cntrl[3].bank0_n_48 ),\n .ras_timer_zero_r_reg_6(\\bank_cntrl[1].bank0_n_51 ),\n .ras_timer_zero_r_reg_7(\\bank_cntrl[1].bank0_n_49 ),\n .rd_this_rank_r(rd_this_rank_r),\n .rd_wr_r_lcl_reg(rd_wr_r_lcl_reg),\n .rd_wr_r_lcl_reg_0(\\bank_cntrl[3].bank0_n_31 ),\n .rd_wr_r_lcl_reg_1(\\bank_cntrl[1].bank0_n_30 ),\n .rd_wr_r_lcl_reg_2(\\bank_cntrl[0].bank0_n_33 ),\n .rd_wr_r_lcl_reg_3(\\bank_cntrl[2].bank0_n_35 ),\n .rd_wr_r_lcl_reg_4(\\bank_cntrl[0].bank0_n_32 ),\n .rd_wr_r_lcl_reg_5(\\bank_cntrl[3].bank0_n_32 ),\n .rd_wr_r_lcl_reg_6(rd_wr_r[0]),\n .rd_wr_r_lcl_reg_7(rd_wr_r[1]),\n .read_this_rank(read_this_rank),\n .read_this_rank_r(read_this_rank_r),\n .\\req_bank_r_lcl_reg[0] (\\req_bank_r_lcl_reg[0]_1 ),\n .\\req_bank_r_lcl_reg[1] (\\req_bank_r_lcl_reg[1] ),\n .\\req_bank_r_lcl_reg[2] (\\cmd_pipe_plus.mc_bank_reg[2] ),\n .\\req_bank_r_lcl_reg[2]_0 (\\cmd_pipe_plus.mc_bank_reg[2]_0 ),\n .\\req_bank_r_lcl_reg[2]_1 (\\cmd_pipe_plus.mc_bank_reg[8]_0 ),\n .\\req_bank_r_lcl_reg[2]_2 (\\cmd_pipe_plus.mc_bank_reg[8]_1 ),\n .\\req_bank_r_lcl_reg[2]_3 (\\req_bank_r_lcl_reg[2]_1 ),\n .req_bank_rdy_ns(\\bank_state0/req_bank_rdy_ns_6 ),\n .req_bank_rdy_ns_0(\\bank_state0/req_bank_rdy_ns ),\n .req_bank_rdy_ns_1(\\bank_state0/req_bank_rdy_ns_12 ),\n .req_bank_rdy_ns_2(\\bank_state0/req_bank_rdy_ns_16 ),\n .req_bank_rdy_r(\\bank_state0/req_bank_rdy_r ),\n .\\req_col_r_reg[9] (\\bank_compare0/req_col_r_13 ),\n .\\req_col_r_reg[9]_0 (\\bank_compare0/req_col_r ),\n .\\req_col_r_reg[9]_1 (\\bank_compare0/req_col_r_2 ),\n .\\req_col_r_reg[9]_2 (\\bank_compare0/req_col_r_7 ),\n .req_data_buf_addr_r(req_data_buf_addr_r),\n .req_periodic_rd_r(req_periodic_rd_r),\n .req_row_r({req_row_r[59:56],req_row_r[54:30],req_row_r[10]}),\n .\\req_row_r_lcl_reg[14] (\\cmd_pipe_plus.mc_address_reg[10] [27:0]),\n .\\rnk_config_strobe_r_reg[0] (\\rnk_config_strobe_r_reg[0] ),\n .rnk_config_valid_r_lcl_reg(rnk_config_valid_r),\n .rnk_config_valid_r_lcl_reg_0(rnk_config_valid_r_lcl_reg),\n .rnk_config_valid_r_lcl_reg_1(rnk_config_valid_r_lcl_reg_0),\n .row_cmd_wr(row_cmd_wr),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22),\n .\\rtw_timer.rtw_cnt_r_reg[1] (\\rtw_timer.rtw_cnt_r_reg[1] ),\n .\\rtw_timer.rtw_cnt_r_reg[1]_0 (\\rtw_timer.rtw_cnt_r_reg[1]_0 ),\n .wr_this_rank_r(wr_this_rank_r),\n .\\wtr_timer.wtr_cnt_r_reg[0] (\\wtr_timer.wtr_cnt_r_reg[0] ),\n .\\wtr_timer.wtr_cnt_r_reg[1] (\\wtr_timer.wtr_cnt_r_reg[1] ),\n .\\wtr_timer.wtr_cnt_r_reg[1]_0 (\\wtr_timer.wtr_cnt_r_reg[1]_0 ));\n ddr3_if_mig_7series_v4_0_bank_cntrl \\bank_cntrl[0].bank0 \n (.CLK(CLK),\n .D(\\bank_queue0/rb_hit_busies_ns_1 [4]),\n .E(idle_r[0]),\n .Q(rb_hit_busies_r_14[4]),\n .SR(SR),\n .accept_internal_r_reg(accept_internal_r_reg),\n .accept_internal_r_reg_0(accept_internal_r),\n .accept_r_reg(bank_common0_n_10),\n .accept_r_reg_0(accept_r_reg_0),\n .act_this_rank_r(act_this_rank_r[0]),\n .\\act_this_rank_r_reg[0] (\\act_this_rank_r_reg[0] [0]),\n .act_wait_r_lcl_reg(act_wait_r_lcl_reg),\n .\\app_addr_r1_reg[12] (\\app_addr_r1_reg[12] ),\n .\\app_addr_r1_reg[27] (\\app_addr_r1_reg[27] ),\n .\\app_addr_r1_reg[9] (\\app_addr_r1_reg[9] ),\n .\\app_cmd_r1_reg[0] (\\app_cmd_r1_reg[0] ),\n .\\app_cmd_r2_reg[1] (\\app_cmd_r2_reg[1] ),\n .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg_0),\n .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_3),\n .bm_end_r1(bm_end_r1),\n .bm_end_r1_reg(req_wr_r[0]),\n .bm_end_r1_reg_0(\\bank_cntrl[3].bank0_n_37 ),\n .bm_end_r1_reg_1(\\bank_cntrl[2].bank0_n_37 ),\n .bm_end_r1_reg_2(\\bank_cntrl[1].bank0_n_35 ),\n .bm_end_r1_reg_3(bm_end_r1_reg_1),\n .\\cmd_pipe_plus.mc_address_reg[14] ({\\cmd_pipe_plus.mc_address_reg[10] [13:10],req_row_r[10],\\cmd_pipe_plus.mc_address_reg[10] [9:0]}),\n .\\cmd_pipe_plus.mc_address_reg[24] (\\bank_compare0/req_col_r ),\n .\\cmd_pipe_plus.mc_bank_reg[2] (\\cmd_pipe_plus.mc_bank_reg[2] ),\n .\\col_mux.col_data_buf_addr_r_reg[4] (req_data_buf_addr_r[4:0]),\n .col_wait_r_reg(col_wait_r_reg_2),\n .demand_priority_r_reg(demand_priority_r),\n .demand_priority_r_reg_0(demand_priority_r_7),\n .demanded_prior_r_reg(demanded_prior_r),\n .demanded_prior_r_reg_0(demanded_prior_r_reg),\n .demanded_prior_r_reg_1(demanded_prior_r_8),\n .demanded_prior_r_reg_2(demanded_prior_r_reg_0),\n .\\grant_r_reg[0] (sending_row),\n .\\grant_r_reg[0]_0 (\\cmd_pipe_plus.mc_bank_reg[7] [0]),\n .\\grant_r_reg[1] (\\bank_cntrl[0].bank0_n_33 ),\n .\\grant_r_reg[2] (\\grant_r_reg[2] ),\n .\\grant_r_reg[2]_0 ({Q[2],Q[0]}),\n .granted_col_ns(\\arb_row_col0/granted_col_ns ),\n .granted_col_r_reg(\\bank_cntrl[0].bank0_n_32 ),\n .granted_col_r_reg_0(\\cmd_pipe_plus.mc_cmd_reg[0] ),\n .head_r_lcl_reg(head_r_lcl_reg_1),\n .head_r_lcl_reg_0(\\bank_cntrl[0].bank0_n_48 ),\n .head_r_lcl_reg_1(\\bank_cntrl[0].bank0_n_49 ),\n .head_r_lcl_reg_2(head_r_lcl_reg_2),\n .head_r_lcl_reg_3(head_r_lcl_reg_5),\n .head_r_lcl_reg_4(head_r_lcl_reg_6),\n .hi_priority(hi_priority),\n .idle_r_lcl_reg(idle_r_lcl_reg),\n .idle_r_lcl_reg_0(rb_hit_busy_r_reg_1),\n .idle_r_lcl_reg_1(rb_hit_busy_r_reg_0),\n .idle_r_lcl_reg_2(rb_hit_busy_r_reg),\n .idle_r_lcl_reg_3(idle_r[1]),\n .idle_r_lcl_reg_4(idle_r[2]),\n .idle_r_lcl_reg_5(idle_r[3]),\n .idle_r_lcl_reg_6(bank_common0_n_19),\n .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6),\n .\\maint_controller.maint_wip_r_lcl_reg (maint_wip_r),\n .maint_req_r(maint_req_r),\n .\\maintenance_request.maint_req_r_lcl_reg (\\maintenance_request.maint_req_r_lcl_reg ),\n .\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),\n .ofs_rdy_r(\\bank_state0/ofs_rdy_r ),\n .ofs_rdy_r0(\\bank_state0/ofs_rdy_r0_10 ),\n .ordered_r(ordered_r[0]),\n .ordered_r_lcl_reg(ordered_r_lcl_reg_2),\n .ordered_r_lcl_reg_0(\\bank_cntrl[2].bank0_n_41 ),\n .ordered_r_lcl_reg_1(\\bank_cntrl[2].bank0_n_39 ),\n .override_demand_r_reg(override_demand_r_reg_1),\n .p_9_in(p_9_in),\n .periodic_rd_ack_r_lcl_reg(\\q_entry_r_reg[1]_2 ),\n .periodic_rd_ack_r_lcl_reg_0(\\q_entry_r_reg[0]_1 ),\n .periodic_rd_ack_r_lcl_reg_1(periodic_rd_ack_r),\n .periodic_rd_ack_r_lcl_reg_2(periodic_rd_ack_r_lcl_reg),\n .periodic_rd_cntr_r_reg(periodic_rd_cntr_r),\n .periodic_rd_insert(periodic_rd_insert),\n .periodic_rd_r(periodic_rd_r),\n .\\pre_4_1_1T_arb.granted_pre_r_reg (\\bank_cntrl[0].bank0_n_56 ),\n .pre_bm_end_r(pre_bm_end_r),\n .pre_bm_end_r_reg(\\q_entry_r_reg[0] ),\n .pre_bm_end_r_reg_0(\\q_entry_r_reg[1]_0 ),\n .pre_bm_end_r_reg_1(\\q_entry_r_reg[1]_1 ),\n .pre_passing_open_bank_r_reg(\\ras_timer_r_reg[0]_1 ),\n .pre_passing_open_bank_r_reg_0(\\ras_timer_r_reg[0]_0 ),\n .q_entry_ns(\\bank_queue0/q_entry_ns ),\n .\\q_entry_r_reg[0] (\\q_entry_r_reg[0]_0 ),\n .\\q_entry_r_reg[0]_0 (\\bank_cntrl[0].bank0_n_45 ),\n .\\q_entry_r_reg[1] (\\bank_cntrl[0].bank0_n_41 ),\n .\\q_entry_r_reg[1]_0 (\\bank_cntrl[0].bank0_n_43 ),\n .\\q_entry_r_reg[1]_1 (\\bank_cntrl[0].bank0_n_44 ),\n .\\q_entry_r_reg[1]_2 (\\q_entry_r_reg[1]_6 ),\n .\\q_entry_r_reg[1]_3 (\\bank_cntrl[2].bank0_n_45 ),\n .\\q_entry_r_reg[1]_4 (\\bank_cntrl[1].bank0_n_46 ),\n .q_has_priority(q_has_priority),\n .q_has_priority_r_reg(rb_hit_busy_r[0]),\n .q_has_priority_r_reg_0(q_has_priority_r_reg),\n .q_has_rd(q_has_rd),\n .q_has_rd_r_reg(q_has_rd_r_reg),\n .\\ras_timer_r_reg[0] (\\bank_cntrl[0].bank0_n_34 ),\n .\\ras_timer_r_reg[0]_0 (\\ras_timer_r_reg[0]_3 ),\n .\\ras_timer_r_reg[0]_1 (\\ras_timer_r_reg[0]_5 ),\n .\\ras_timer_r_reg[0]_2 (\\ras_timer_r_reg[0]_4 ),\n .\\ras_timer_r_reg[0]_3 (\\bank_cntrl[0].bank0_n_55 ),\n .\\ras_timer_r_reg[1] (\\bank_cntrl[0].bank0_n_38 ),\n .\\ras_timer_r_reg[1]_0 (\\bank_cntrl[2].bank0_n_36 ),\n .\\ras_timer_r_reg[1]_1 (\\bank_cntrl[1].bank0_n_31 ),\n .\\ras_timer_r_reg[2] (\\bank_cntrl[0].bank0_n_39 ),\n .\\ras_timer_r_reg[2]_0 (\\bank_cntrl[3].bank0_n_38 ),\n .\\ras_timer_r_reg[2]_1 (\\bank_cntrl[1].bank0_n_36 ),\n .\\ras_timer_r_reg[2]_2 (\\bank_cntrl[2].bank0_n_38 ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] (\\ras_timer_r_reg[0]_2 ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ({rb_hit_busies_r,\\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] }),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 (\\bank_queue0/rb_hit_busies_ns_4 ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] (\\bank_queue0/rb_hit_busies_ns_0 [4]),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 (\\bank_queue0/rb_hit_busies_ns [4]),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 (rb_hit_busies_r_8[4]),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 (rb_hit_busies_r_3[4]),\n .rb_hit_busy_r_reg(rb_hit_busy_r[3]),\n .rb_hit_busy_r_reg_0(rb_hit_busy_r[2]),\n .rb_hit_busy_r_reg_1(rb_hit_busy_r[1]),\n .rb_hit_busy_r_reg_2(rb_hit_busy_r_reg_2),\n .rd_this_rank_r(rd_this_rank_r[0]),\n .\\rd_this_rank_r_reg[0] (rd_wr_r[0]),\n .rd_wr_r_lcl_reg(\\bank_cntrl[3].bank0_n_31 ),\n .rd_wr_r_lcl_reg_0(\\bank_cntrl[1].bank0_n_30 ),\n .rd_wr_r_lcl_reg_1(\\bank_cntrl[3].bank0_n_33 ),\n .rd_wr_r_lcl_reg_2(\\bank_cntrl[1].bank0_n_37 ),\n .\\req_bank_r_lcl_reg[0] (\\req_bank_r_lcl_reg[0]_0 ),\n .req_bank_rdy_ns(\\bank_state0/req_bank_rdy_ns ),\n .req_periodic_rd_r(req_periodic_rd_r[0]),\n .req_wr_r_lcl_reg(\\bank_cntrl[2].bank0_n_40 ),\n .req_wr_r_lcl_reg_0(\\bank_cntrl[3].bank0_n_39 ),\n .req_wr_r_lcl_reg_1(req_wr_r_lcl_reg_2),\n .\\rnk_config_strobe_r_reg[0] (\\bank_cntrl[0].bank0_n_74 ),\n .rnk_config_valid_r_lcl_reg(arb_mux0_n_98),\n .row_hit_r(row_hit_r),\n .\\rp_timer.rp_timer_r_reg[1] (ras_timer_zero_r),\n .\\rp_timer.rp_timer_r_reg[1]_0 (auto_pre_r),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22),\n .rtp_timer_ns1(rtp_timer_ns1),\n .\\rtw_timer.rtw_cnt_r_reg[1] (arb_mux0_n_22),\n .\\starve_limit_cntr_r_reg[2] (col_wait_r),\n .tail_r(tail_r),\n .use_addr(use_addr),\n .wait_for_maint_r(wait_for_maint_r),\n .wait_for_maint_r_lcl_reg(head_r[0]),\n .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg),\n .wr_this_rank_r(wr_this_rank_r[0]),\n .\\wtr_timer.wtr_cnt_r_reg[1] (\\wtr_timer.wtr_cnt_r_reg[1]_1 ));\n ddr3_if_mig_7series_v4_0_bank_cntrl__parameterized0 \\bank_cntrl[1].bank0 \n (.CLK(CLK),\n .D(\\bank_queue0/rb_hit_busies_ns_0 [5]),\n .E(idle_r[1]),\n .Q(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ),\n .SR(SR),\n .accept_internal_r_reg(accept_internal_r),\n .accept_r_reg(accept_r_reg),\n .accept_r_reg_0(bank_common0_n_12),\n .act_this_rank_r(act_this_rank_r[1]),\n .act_wait_r_lcl_reg(act_wait_r_lcl_reg_0),\n .act_wait_r_lcl_reg_0(\\act_this_rank_r_reg[0] [0]),\n .\\app_addr_r1_reg[12] (\\app_addr_r1_reg[12] ),\n .\\app_addr_r1_reg[27] (\\app_addr_r1_reg[27] ),\n .\\app_addr_r1_reg[9] (\\app_addr_r1_reg[9] ),\n .\\app_cmd_r1_reg[0] (\\app_cmd_r1_reg[0] ),\n .\\app_cmd_r2_reg[1] (\\app_cmd_r2_reg[1] ),\n .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg),\n .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_4),\n .auto_pre_r_lcl_reg_1(\\bank_cntrl[0].bank0_n_56 ),\n .bm_end_r1_0(bm_end_r1_0),\n .bm_end_r1_reg(req_wr_r[1]),\n .bm_end_r1_reg_0(pre_bm_end_r_2),\n .bm_end_r1_reg_1(\\bank_cntrl[0].bank0_n_38 ),\n .bm_end_r1_reg_2(\\bank_cntrl[2].bank0_n_37 ),\n .bm_end_r1_reg_3(\\bank_cntrl[3].bank0_n_37 ),\n .bm_end_r1_reg_4(\\bank_cntrl[0].bank0_n_39 ),\n .bm_end_r1_reg_5(bm_end_r1_reg_2),\n .\\cmd_pipe_plus.mc_address_reg[14] ({\\cmd_pipe_plus.mc_address_reg[10] [27:24],req_row_r[25],\\cmd_pipe_plus.mc_address_reg[10] [23:14]}),\n .\\cmd_pipe_plus.mc_address_reg[24] (\\bank_compare0/req_col_r_2 ),\n .\\cmd_pipe_plus.mc_address_reg[40] (\\bank_cntrl[1].bank0_n_71 ),\n .\\cmd_pipe_plus.mc_bank_reg[2] (\\cmd_pipe_plus.mc_bank_reg[2]_0 ),\n .\\col_mux.col_data_buf_addr_r_reg[4] (req_data_buf_addr_r[9:5]),\n .col_wait_r_reg(col_wait_r_reg_0),\n .demand_priority_r_reg(demand_priority_r_1),\n .demand_priority_r_reg_0(demand_priority_r_13),\n .demanded_prior_r(\\bank_state0/demanded_prior_r ),\n .demanded_prior_r_reg(demanded_prior_r_reg),\n .demanded_prior_r_reg_0(demanded_prior_r_14),\n .\\grant_r_reg[1] (\\bank_cntrl[1].bank0_n_30 ),\n .\\grant_r_reg[1]_0 (\\bank_cntrl[1].bank0_n_52 ),\n .\\grant_r_reg[1]_1 (\\bank_cntrl[1].bank0_n_53 ),\n .\\grant_r_reg[1]_2 (\\last_master_r_reg[3] [0]),\n .\\grant_r_reg[1]_3 (\\cmd_pipe_plus.mc_bank_reg[7] [1:0]),\n .\\grant_r_reg[2] (\\bank_cntrl[1].bank0_n_49 ),\n .\\grant_r_reg[2]_0 (\\bank_cntrl[1].bank0_n_51 ),\n .\\grant_r_reg[3] (\\bank_cntrl[1].bank0_n_70 ),\n .\\grant_r_reg[3]_0 ({Q[3],Q[1:0]}),\n .granted_col_r_reg(\\cmd_pipe_plus.mc_cmd_reg[0] ),\n .granted_pre_ns(granted_pre_ns),\n .head_r_lcl_reg(head_r_lcl_reg_3),\n .head_r_lcl_reg_0(head_r_lcl_reg_4),\n .head_r_lcl_reg_1(head_r_lcl_reg_7),\n .hi_priority(hi_priority),\n .idle_r_lcl_reg(idle_r_lcl_reg_0),\n .idle_r_lcl_reg_0(accept_internal_r_reg),\n .idle_r_lcl_reg_1(rb_hit_busy_r_reg_0),\n .idle_r_lcl_reg_2(rb_hit_busy_r_reg_1),\n .idle_r_lcl_reg_3(idle_r[3]),\n .idle_r_lcl_reg_4(idle_r[2]),\n .idle_r_lcl_reg_5(idle_r[0]),\n .idle_r_lcl_reg_6(idle_r_lcl_reg_5),\n .\\last_master_r_reg[0] (arb_mux0_n_89),\n .\\maint_controller.maint_wip_r_lcl_reg (maint_wip_r),\n .maint_req_r(maint_req_r),\n .\\maintenance_request.maint_req_r_lcl_reg (\\maintenance_request.maint_req_r_lcl_reg ),\n .\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),\n .ofs_rdy_r(\\bank_state0/ofs_rdy_r_5 ),\n .ofs_rdy_r0(\\bank_state0/ofs_rdy_r0 ),\n .ordered_r(ordered_r[1]),\n .ordered_r_lcl_reg(ordered_r_lcl_reg_3),\n .ordered_r_lcl_reg_0(\\bank_cntrl[2].bank0_n_41 ),\n .ordered_r_lcl_reg_1(\\bank_cntrl[2].bank0_n_39 ),\n .override_demand_r_reg(override_demand_r_reg),\n .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg_1),\n .pass_open_bank_r_lcl_reg_0(pass_open_bank_r_lcl_reg_2),\n .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r),\n .periodic_rd_ack_r_lcl_reg_0(periodic_rd_ack_r_lcl_reg),\n .periodic_rd_ack_r_lcl_reg_1(\\q_entry_r_reg[1]_2 ),\n .periodic_rd_ack_r_lcl_reg_2(ordered_r_lcl_reg_1),\n .periodic_rd_cntr_r_reg(periodic_rd_cntr_r),\n .periodic_rd_insert(periodic_rd_insert),\n .periodic_rd_r(periodic_rd_r),\n .pre_bm_end_r_reg(\\q_entry_r_reg[0]_0 ),\n .pre_bm_end_r_reg_0(\\q_entry_r_reg[1]_1 ),\n .pre_bm_end_r_reg_1(\\q_entry_r_reg[1]_0 ),\n .pre_passing_open_bank_r_reg(rtp_timer_r[1]),\n .pre_passing_open_bank_r_reg_0(rtp_timer_r[0]),\n .pre_passing_open_bank_r_reg_1(\\bank_cntrl[2].bank0_n_54 ),\n .pre_passing_open_bank_r_reg_2(\\ras_timer_r_reg[0]_1 ),\n .q_entry_ns(\\bank_queue0/q_entry_ns ),\n .\\q_entry_r_reg[0] (\\q_entry_r_reg[0] ),\n .\\q_entry_r_reg[0]_0 (\\bank_cntrl[1].bank0_n_43 ),\n .\\q_entry_r_reg[1] (\\bank_cntrl[1].bank0_n_41 ),\n .\\q_entry_r_reg[1]_0 (\\q_entry_r_reg[1]_5 ),\n .\\q_entry_r_reg[1]_1 (\\bank_cntrl[1].bank0_n_46 ),\n .q_has_priority_4(q_has_priority_4),\n .q_has_priority_r_reg(q_has_priority_r_reg_0),\n .q_has_rd_3(q_has_rd_3),\n .q_has_rd_r_reg(q_has_rd_r_reg_0),\n .\\ras_timer_r_reg[0] (\\bank_cntrl[1].bank0_n_31 ),\n .\\ras_timer_r_reg[0]_0 (\\ras_timer_r_reg[0]_0 ),\n .\\ras_timer_r_reg[0]_1 (\\ras_timer_r_reg[0]_6 ),\n .\\ras_timer_r_reg[1] (\\bank_cntrl[1].bank0_n_35 ),\n .\\ras_timer_r_reg[1]_0 (\\bank_cntrl[0].bank0_n_34 ),\n .\\ras_timer_r_reg[1]_1 (\\bank_cntrl[2].bank0_n_36 ),\n .\\ras_timer_r_reg[2] (\\bank_cntrl[1].bank0_n_36 ),\n .\\ras_timer_r_reg[2]_0 (\\bank_cntrl[2].bank0_n_38 ),\n .\\ras_timer_r_reg[2]_1 (\\bank_cntrl[3].bank0_n_38 ),\n .ras_timer_zero_r_reg(\\bank_cntrl[3].bank0_n_48 ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] (\\bank_queue0/rb_hit_busies_ns_4 [1]),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ({rb_hit_busies_r_3[4],\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ,rb_hit_busies_r_3[2]}),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 (\\ras_timer_r_reg[0]_5 ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 (\\bank_queue0/rb_hit_busies_ns ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] (\\bank_queue0/rb_hit_busies_ns_1 [5]),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),\n .rb_hit_busy_r(rb_hit_busy_r[1]),\n .rb_hit_busy_r_reg(rb_hit_busy_r_reg),\n .rb_hit_busy_r_reg_0(\\bank_cntrl[0].bank0_n_48 ),\n .rb_hit_busy_r_reg_1(\\bank_cntrl[0].bank0_n_49 ),\n .rd_this_rank_r(rd_this_rank_r[1]),\n .\\rd_this_rank_r_reg[0] (rd_wr_r[1]),\n .rd_wr_r_lcl_reg(\\bank_cntrl[3].bank0_n_33 ),\n .rd_wr_r_lcl_reg_0(rd_wr_r[0]),\n .\\req_bank_r_lcl_reg[2] (\\req_bank_r_lcl_reg[2] ),\n .req_bank_rdy_ns(\\bank_state0/req_bank_rdy_ns_6 ),\n .req_bank_rdy_r_reg(\\bank_cntrl[1].bank0_n_37 ),\n .req_periodic_rd_r(req_periodic_rd_r[1]),\n .\\req_row_r_lcl_reg[10] (req_row_r[10]),\n .req_wr_r(req_wr_r[0]),\n .req_wr_r_lcl_reg(\\bank_cntrl[2].bank0_n_40 ),\n .req_wr_r_lcl_reg_0(\\bank_cntrl[3].bank0_n_39 ),\n .req_wr_r_lcl_reg_1(req_wr_r_lcl_reg),\n .\\rnk_config_strobe_r_reg[0] (\\bank_cntrl[1].bank0_n_69 ),\n .rnk_config_valid_r_lcl_reg(arb_mux0_n_97),\n .row_cmd_wr(row_cmd_wr),\n .row_hit_r_0(row_hit_r_0),\n .\\rp_timer.rp_timer_r_reg[1] (auto_pre_r_25),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22),\n .\\rtw_timer.rtw_cnt_r_reg[1] (arb_mux0_n_22),\n .\\starve_limit_cntr_r_reg[2] (col_wait_r_21),\n .tail_r_24(tail_r_24),\n .use_addr(use_addr),\n .wait_for_maint_r_18(wait_for_maint_r_18),\n .wait_for_maint_r_lcl_reg(head_r[1]),\n .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg_0),\n .wr_this_rank_r(wr_this_rank_r[1]),\n .\\wtr_timer.wtr_cnt_r_reg[1] (\\wtr_timer.wtr_cnt_r_reg[1]_1 ));\n ddr3_if_mig_7series_v4_0_bank_cntrl__parameterized1 \\bank_cntrl[2].bank0 \n (.CLK(CLK),\n .D(\\bank_queue0/rb_hit_busies_ns_1 [6]),\n .E(idle_r[2]),\n .Q(rb_hit_busies_r_14[6]),\n .SR(SR),\n .accept_internal_r_reg(accept_internal_r),\n .accept_r_reg(bank_common0_n_14),\n .act_this_rank_r(act_this_rank_r[2]),\n .\\act_this_rank_r_reg[0] (\\act_this_rank_r_reg[0] [1]),\n .act_wait_r_lcl_reg(act_wait_r_lcl_reg_1),\n .act_wait_r_lcl_reg_0(act_wait_r_lcl_reg_3),\n .\\app_addr_r1_reg[12] (\\app_addr_r1_reg[12] ),\n .\\app_addr_r1_reg[27] (\\app_addr_r1_reg[27] ),\n .\\app_addr_r1_reg[9] (\\app_addr_r1_reg[9] ),\n .\\app_cmd_r1_reg[0] (\\app_cmd_r1_reg[0] ),\n .\\app_cmd_r2_reg[1] (\\app_cmd_r2_reg[1] ),\n .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg_2),\n .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_5),\n .bm_end_r1_reg(req_wr_r[2]),\n .bm_end_r1_reg_0(bm_end_r1_reg),\n .bm_end_r1_reg_1(\\bank_cntrl[0].bank0_n_38 ),\n .bm_end_r1_reg_2(\\bank_cntrl[3].bank0_n_37 ),\n .bm_end_r1_reg_3(\\bank_cntrl[1].bank0_n_35 ),\n .bm_end_r1_reg_4(\\bank_cntrl[0].bank0_n_39 ),\n .\\cmd_pipe_plus.mc_address_reg[24] (\\bank_compare0/req_col_r_7 ),\n .\\cmd_pipe_plus.mc_address_reg[40] (\\cmd_pipe_plus.mc_address_reg[44] [33]),\n .\\cmd_pipe_plus.mc_address_reg[44] (req_row_r[44:30]),\n .\\cmd_pipe_plus.mc_bank_reg[8] (\\cmd_pipe_plus.mc_bank_reg[8]_0 ),\n .\\col_mux.col_data_buf_addr_r_reg[4] (req_data_buf_addr_r[14:10]),\n .col_wait_r_reg(col_wait_r_reg_1),\n .\\compute_tail.tail_r_lcl_reg (\\compute_tail.tail_r_lcl_reg ),\n .demand_priority_r(demand_priority_r),\n .demand_priority_r_reg(demand_priority_r_7),\n .demanded_prior_r(demanded_prior_r),\n .demanded_prior_r_reg(demanded_prior_r_8),\n .demanded_prior_r_reg_0(demanded_prior_r_reg_0),\n .\\entry_cnt_reg[2] (\\entry_cnt_reg[2] ),\n .\\entry_cnt_reg[2]_0 (\\entry_cnt_reg[2]_0 ),\n .\\grant_r_reg[1] (\\grant_r_reg[1]_0 ),\n .\\grant_r_reg[1]_0 (arb_mux0_n_85),\n .\\grant_r_reg[2] (\\bank_cntrl[2].bank0_n_35 ),\n .\\grant_r_reg[2]_0 (\\bank_cntrl[2].bank0_n_58 ),\n .\\grant_r_reg[2]_1 (\\last_master_r_reg[3] [1]),\n .\\grant_r_reg[3] (\\grant_r_reg[3] ),\n .\\grant_r_reg[3]_0 ({Q[3:2],Q[0]}),\n .\\grant_r_reg[3]_1 (arb_mux0_n_86),\n .\\grant_r_reg[3]_2 (\\cmd_pipe_plus.mc_bank_reg[7] [3:2]),\n .granted_col_r_reg(\\cmd_pipe_plus.mc_cmd_reg[0] ),\n .granted_row_ns(granted_row_ns),\n .granted_row_r_reg(\\bank_cntrl[2].bank0_n_56 ),\n .head_r_lcl_reg(head_r_lcl_reg),\n .head_r_lcl_reg_0(head_r_lcl_reg_8),\n .hi_priority(hi_priority),\n .idle_r_lcl_reg(idle_r_lcl_reg_1),\n .idle_r_lcl_reg_0(rb_hit_busy_r_reg_1),\n .idle_r_lcl_reg_1(accept_internal_r_reg),\n .idle_r_lcl_reg_2(rb_hit_busy_r_reg),\n .idle_r_lcl_reg_3(idle_r_lcl_reg_3),\n .idle_r_lcl_reg_4(\\bank_cntrl[1].bank0_n_41 ),\n .idle_r_lcl_reg_5(idle_r_lcl_reg_6),\n .\\maint_controller.maint_wip_r_lcl_reg (maint_wip_r),\n .maint_req_r(maint_req_r),\n .\\maintenance_request.maint_req_r_lcl_reg (\\maintenance_request.maint_req_r_lcl_reg ),\n .\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),\n .of_ctl_full_v(of_ctl_full_v),\n .ofs_rdy_r(\\bank_state0/ofs_rdy_r_11 ),\n .ofs_rdy_r0(\\bank_state0/ofs_rdy_r0_10 ),\n .ofs_rdy_r0_0(\\bank_state0/ofs_rdy_r0_9 ),\n .ofs_rdy_r0_1(\\bank_state0/ofs_rdy_r0 ),\n .\\order_q_r_reg[0] (\\bank_cntrl[2].bank0_n_39 ),\n .\\order_q_r_reg[1] (\\bank_cntrl[2].bank0_n_41 ),\n .ordered_r(ordered_r[2]),\n .ordered_r_lcl_reg(ordered_r_lcl_reg_4),\n .ordered_r_lcl_reg_0({ordered_r[3],ordered_r[1:0]}),\n .override_demand_ns(\\bank_state0/override_demand_ns ),\n .override_demand_r(override_demand_r),\n .override_demand_r_reg(override_demand_r_reg_0),\n .periodic_rd_ack_r_lcl_reg(ordered_r_lcl_reg),\n .periodic_rd_ack_r_lcl_reg_0(\\q_entry_r_reg[1]_2 ),\n .periodic_rd_ack_r_lcl_reg_1(periodic_rd_ack_r),\n .periodic_rd_ack_r_lcl_reg_2(periodic_rd_ack_r_lcl_reg),\n .periodic_rd_cntr_r_reg(periodic_rd_cntr_r),\n .periodic_rd_insert(periodic_rd_insert),\n .periodic_rd_r(periodic_rd_r),\n .phy_mc_ctl_full(phy_mc_ctl_full),\n .pre_bm_end_r_9(pre_bm_end_r_9),\n .pre_bm_end_r_reg(\\q_entry_r_reg[0] ),\n .pre_bm_end_r_reg_0(\\q_entry_r_reg[0]_0 ),\n .pre_bm_end_r_reg_1(\\q_entry_r_reg[1]_1 ),\n .pre_passing_open_bank_r_reg(\\bank_cntrl[0].bank0_n_55 ),\n .pre_passing_open_bank_r_reg_0(\\ras_timer_r_reg[0]_0 ),\n .\\q_entry_r_reg[0] (q_entry_r[0]),\n .\\q_entry_r_reg[1] (\\q_entry_r_reg[1]_0 ),\n .\\q_entry_r_reg[1]_0 (\\bank_cntrl[2].bank0_n_45 ),\n .\\q_entry_r_reg[1]_1 (q_entry_r[1]),\n .\\q_entry_r_reg[1]_2 (\\q_entry_r_reg[1]_3 ),\n .\\q_entry_r_reg[1]_3 (\\bank_cntrl[0].bank0_n_41 ),\n .q_has_priority_11(q_has_priority_11),\n .q_has_priority_r_reg(rb_hit_busy_r[2]),\n .q_has_priority_r_reg_0(q_has_priority_r_reg_1),\n .q_has_rd_10(q_has_rd_10),\n .q_has_rd_r_reg(q_has_rd_r_reg_1),\n .\\ras_timer_r_reg[0] (\\bank_cntrl[2].bank0_n_36 ),\n .\\ras_timer_r_reg[0]_0 (\\ras_timer_r_reg[0]_2 ),\n .\\ras_timer_r_reg[0]_1 (\\bank_cntrl[2].bank0_n_54 ),\n .\\ras_timer_r_reg[1] (\\bank_cntrl[2].bank0_n_37 ),\n .\\ras_timer_r_reg[1]_0 (\\bank_cntrl[1].bank0_n_31 ),\n .\\ras_timer_r_reg[1]_1 (\\bank_cntrl[0].bank0_n_34 ),\n .\\ras_timer_r_reg[2] (\\ras_timer_r_reg[2] ),\n .\\ras_timer_r_reg[2]_0 (\\bank_cntrl[2].bank0_n_38 ),\n .\\ras_timer_r_reg[2]_1 (\\bank_cntrl[1].bank0_n_36 ),\n .\\ras_timer_r_reg[2]_2 (\\bank_cntrl[3].bank0_n_38 ),\n .ras_timer_zero_r_reg(ras_timer_zero_r_reg_0),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] (\\bank_queue0/rb_hit_busies_ns_4 [2]),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 (\\bank_queue0/rb_hit_busies_ns [2]),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 (rb_hit_busies_r[2]),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 (rb_hit_busies_r_3[2]),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] (\\ras_timer_r_reg[0] ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ({\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ,rb_hit_busies_r_8}),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 (\\bank_queue0/rb_hit_busies_ns_0 ),\n .rb_hit_busy_r_reg(rb_hit_busy_r_reg_0),\n .rb_hit_busy_r_reg_0(\\bank_cntrl[0].bank0_n_48 ),\n .rb_hit_busy_r_reg_1(\\bank_cntrl[0].bank0_n_49 ),\n .rb_hit_busy_r_reg_2(pass_open_bank_r_lcl_reg_0),\n .rd_this_rank_r(rd_this_rank_r[2]),\n .\\rd_this_rank_r_reg[0] (rd_wr_r[2]),\n .rd_wr_r(rd_wr_r[1]),\n .rd_wr_r_lcl_reg(rd_wr_r[0]),\n .rd_wr_r_lcl_reg_0(rd_wr_r[3]),\n .rd_wr_r_lcl_reg_1(\\bank_cntrl[1].bank0_n_37 ),\n .rd_wr_r_lcl_reg_2(\\bank_cntrl[3].bank0_n_33 ),\n .\\req_bank_r_lcl_reg[2] (\\req_bank_r_lcl_reg[2]_0 ),\n .req_bank_rdy_ns(\\bank_state0/req_bank_rdy_ns_12 ),\n .req_bank_rdy_r_reg(\\bank_cntrl[2].bank0_n_40 ),\n .req_periodic_rd_r(req_periodic_rd_r[2]),\n .\\req_row_r_lcl_reg[10] (\\bank_cntrl[1].bank0_n_71 ),\n .req_wr_r_lcl_reg(\\bank_cntrl[3].bank0_n_39 ),\n .req_wr_r_lcl_reg_0(req_wr_r[3]),\n .req_wr_r_lcl_reg_1(req_wr_r_lcl_reg_0),\n .\\rnk_config_strobe_r_reg[0] (\\bank_cntrl[2].bank0_n_74 ),\n .rnk_config_valid_r_lcl_reg(arb_mux0_n_99),\n .row_hit_r_5(row_hit_r_5),\n .\\rp_timer.rp_timer_r_reg[1] (ras_timer_zero_r_6),\n .\\rp_timer.rp_timer_r_reg[1]_0 (auto_pre_r_27),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22),\n .rtp_timer_ns1_7(rtp_timer_ns1_7),\n .\\rtw_timer.rtw_cnt_r_reg[1] (arb_mux0_n_22),\n .\\starve_limit_cntr_r_reg[2] (col_wait_r_22),\n .tail_r_26(tail_r_26),\n .use_addr(use_addr),\n .wait_for_maint_r_19(wait_for_maint_r_19),\n .wait_for_maint_r_lcl_reg(head_r[2]),\n .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg_1),\n .wr_this_rank_r(wr_this_rank_r[2]),\n .\\wtr_timer.wtr_cnt_r_reg[1] (\\wtr_timer.wtr_cnt_r_reg[1]_1 ));\n ddr3_if_mig_7series_v4_0_bank_cntrl__parameterized2 \\bank_cntrl[3].bank0 \n (.CLK(CLK),\n .D(\\bank_queue0/rb_hit_busies_ns_1 ),\n .E(idle_r[3]),\n .Q({rb_hit_busies_r_14[6],\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ,rb_hit_busies_r_14[4]}),\n .SR(SR),\n .accept_internal_r_reg(accept_internal_r),\n .accept_r_reg(bank_common0_n_16),\n .act_this_rank_r(act_this_rank_r[3]),\n .\\act_this_rank_r_reg[0] (\\act_this_rank_r_reg[0] [2]),\n .act_wait_r_lcl_reg(act_wait_r_lcl_reg_2),\n .\\app_addr_r1_reg[12] (\\app_addr_r1_reg[12] ),\n .\\app_addr_r1_reg[27] (\\app_addr_r1_reg[27] ),\n .\\app_addr_r1_reg[9] (\\app_addr_r1_reg[9] ),\n .\\app_cmd_r1_reg[0] (\\app_cmd_r1_reg[0] ),\n .\\app_cmd_r2_reg[1] (\\app_cmd_r2_reg[1] ),\n .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg_1),\n .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg_6),\n .auto_pre_r_lcl_reg_1(\\bank_cntrl[2].bank0_n_58 ),\n .bm_end_r1_4(bm_end_r1_4),\n .bm_end_r1_reg(req_wr_r[3]),\n .bm_end_r1_reg_0(\\bank_cntrl[2].bank0_n_37 ),\n .bm_end_r1_reg_1(\\bank_cntrl[1].bank0_n_35 ),\n .bm_end_r1_reg_2(\\bank_cntrl[0].bank0_n_38 ),\n .bm_end_r1_reg_3(\\bank_cntrl[0].bank0_n_39 ),\n .bm_end_r1_reg_4(bm_end_r1_reg_0),\n .\\cmd_pipe_plus.mc_address_reg[10] (\\bank_cntrl[3].bank0_n_49 ),\n .\\cmd_pipe_plus.mc_address_reg[24] (\\bank_compare0/req_col_r_13 ),\n .\\cmd_pipe_plus.mc_address_reg[44] ({req_row_r[59:56],\\cmd_pipe_plus.mc_address_reg[10] [28],req_row_r[54:45]}),\n .\\cmd_pipe_plus.mc_bank_reg[8] (\\cmd_pipe_plus.mc_bank_reg[8]_1 ),\n .\\col_mux.col_data_buf_addr_r_reg[4] (req_data_buf_addr_r[19:15]),\n .col_wait_r_reg(col_wait_r_reg),\n .demand_priority_r_reg(demand_priority_r_13),\n .demand_priority_r_reg_0(demand_priority_r_1),\n .demanded_prior_r(\\bank_state0/demanded_prior_r ),\n .demanded_prior_r_reg(demanded_prior_r_14),\n .demanded_prior_r_reg_0(demanded_prior_r_reg_0),\n .demanded_prior_r_reg_1(demanded_prior_r_reg),\n .\\grant_r_reg[0] (\\bank_cntrl[3].bank0_n_65 ),\n .\\grant_r_reg[1] (\\grant_r_reg[1] ),\n .\\grant_r_reg[1]_0 (\\bank_cntrl[1].bank0_n_70 ),\n .\\grant_r_reg[2] (\\bank_cntrl[3].bank0_n_66 ),\n .\\grant_r_reg[3] (\\bank_cntrl[3].bank0_n_32 ),\n .\\grant_r_reg[3]_0 (\\bank_cntrl[3].bank0_n_39 ),\n .\\grant_r_reg[3]_1 (\\bank_cntrl[3].bank0_n_67 ),\n .\\grant_r_reg[3]_2 (Q[3:1]),\n .\\grant_r_reg[3]_3 (\\last_master_r_reg[3] [2]),\n .\\grant_r_reg[3]_4 (\\cmd_pipe_plus.mc_bank_reg[7] [3]),\n .\\grant_r_reg[3]_5 (arb_mux0_n_46),\n .granted_col_r_reg(\\bank_cntrl[3].bank0_n_31 ),\n .granted_col_r_reg_0(\\cmd_pipe_plus.mc_cmd_reg[0] ),\n .head_r_lcl_reg(head_r_lcl_reg_0),\n .head_r_lcl_reg_0(head_r_lcl_reg_9),\n .hi_priority(hi_priority),\n .idle_r_lcl_reg(idle_r_lcl_reg_2),\n .idle_r_lcl_reg_0(accept_internal_r_reg),\n .idle_r_lcl_reg_1(rb_hit_busy_r_reg_0),\n .idle_r_lcl_reg_2(rb_hit_busy_r_reg),\n .idle_r_lcl_reg_3(idle_r_lcl_reg_4),\n .idle_r_lcl_reg_4(\\bank_cntrl[0].bank0_n_44 ),\n .idle_r_lcl_reg_5(\\bank_cntrl[0].bank0_n_43 ),\n .idle_r_lcl_reg_6(idle_r_lcl_reg_7),\n .\\last_master_r_reg[2] (arb_mux0_n_88),\n .\\maint_controller.maint_wip_r_lcl_reg (maint_wip_r),\n .maint_req_r(maint_req_r),\n .\\maintenance_request.maint_req_r_lcl_reg (\\maintenance_request.maint_req_r_lcl_reg ),\n .\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),\n .ofs_rdy_r(\\bank_state0/ofs_rdy_r_15 ),\n .ofs_rdy_r0(\\bank_state0/ofs_rdy_r0_9 ),\n .ordered_r(ordered_r[3]),\n .ordered_r_lcl_reg(ordered_r_lcl_reg_5),\n .ordered_r_lcl_reg_0(\\bank_cntrl[2].bank0_n_41 ),\n .ordered_r_lcl_reg_1(\\bank_cntrl[2].bank0_n_39 ),\n .override_demand_r(override_demand_r),\n .periodic_rd_ack_r_lcl_reg(ordered_r_lcl_reg_0),\n .periodic_rd_ack_r_lcl_reg_0(\\q_entry_r_reg[1]_2 ),\n .periodic_rd_ack_r_lcl_reg_1(periodic_rd_ack_r),\n .periodic_rd_ack_r_lcl_reg_2(periodic_rd_ack_r_lcl_reg),\n .periodic_rd_cntr_r_reg(periodic_rd_cntr_r),\n .periodic_rd_insert(periodic_rd_insert),\n .periodic_rd_r(periodic_rd_r),\n .\\pre_4_1_1T_arb.granted_pre_r_reg (\\bank_cntrl[3].bank0_n_48 ),\n .pre_bm_end_r_15(pre_bm_end_r_15),\n .pre_bm_end_r_reg(\\q_entry_r_reg[0]_0 ),\n .pre_bm_end_r_reg_0(\\q_entry_r_reg[1]_0 ),\n .pre_bm_end_r_reg_1(\\q_entry_r_reg[0] ),\n .pre_bm_end_r_reg_2(\\bank_cntrl[0].bank0_n_45 ),\n .pre_passing_open_bank_r_reg(\\bank_cntrl[2].bank0_n_54 ),\n .pre_passing_open_bank_r_reg_0(\\ras_timer_r_reg[0]_0 ),\n .\\q_entry_r_reg[0] (q_entry_r_30[0]),\n .\\q_entry_r_reg[1] (\\q_entry_r_reg[1]_1 ),\n .\\q_entry_r_reg[1]_0 (q_entry_r_30[1]),\n .\\q_entry_r_reg[1]_1 (\\q_entry_r_reg[1]_4 ),\n .q_has_priority_17(q_has_priority_17),\n .q_has_priority_r_reg(rb_hit_busy_r[3]),\n .q_has_priority_r_reg_0(q_has_priority_r_reg_2),\n .q_has_rd_16(q_has_rd_16),\n .q_has_rd_r_reg(q_has_rd_r_reg_2),\n .\\ras_timer_r_reg[0] (\\bank_cntrl[3].bank0_n_33 ),\n .\\ras_timer_r_reg[0]_0 (\\ras_timer_r_reg[0] ),\n .\\ras_timer_r_reg[0]_1 (\\ras_timer_r_reg[0]_1 ),\n .\\ras_timer_r_reg[1] (\\bank_cntrl[3].bank0_n_37 ),\n .\\ras_timer_r_reg[1]_0 (\\bank_cntrl[2].bank0_n_36 ),\n .\\ras_timer_r_reg[1]_1 (\\bank_cntrl[1].bank0_n_31 ),\n .\\ras_timer_r_reg[1]_2 (\\bank_cntrl[0].bank0_n_34 ),\n .\\ras_timer_r_reg[2] (\\bank_cntrl[3].bank0_n_38 ),\n .\\ras_timer_r_reg[2]_0 (\\bank_cntrl[2].bank0_n_38 ),\n .\\ras_timer_r_reg[2]_1 (\\bank_cntrl[1].bank0_n_36 ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] (\\bank_queue0/rb_hit_busies_ns_4 [3]),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 (\\bank_queue0/rb_hit_busies_ns_0 [3]),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 (\\bank_queue0/rb_hit_busies_ns [3]),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 (rb_hit_busies_r[3]),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 (rb_hit_busies_r_8[3]),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4 (\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] (\\ras_timer_r_reg[0]_4 ),\n .rb_hit_busy_r(rb_hit_busy_r[2:0]),\n .rb_hit_busy_r_reg(rb_hit_busy_r_reg_1),\n .rb_hit_busy_r_reg_0(\\bank_cntrl[0].bank0_n_48 ),\n .rb_hit_busy_r_reg_1(\\bank_cntrl[0].bank0_n_49 ),\n .rb_hit_busy_r_reg_2(pass_open_bank_r_lcl_reg),\n .rd_this_rank_r(rd_this_rank_r[3]),\n .\\rd_this_rank_r_reg[0] (rd_wr_r[3]),\n .rd_wr_r(rd_wr_r[2]),\n .rd_wr_r_lcl_reg(\\bank_cntrl[2].bank0_n_35 ),\n .rd_wr_r_lcl_reg_0(\\bank_cntrl[1].bank0_n_37 ),\n .\\req_bank_r_lcl_reg[0] (\\req_bank_r_lcl_reg[0] ),\n .req_bank_rdy_ns(\\bank_state0/req_bank_rdy_ns_16 ),\n .req_bank_rdy_r(\\bank_state0/req_bank_rdy_r ),\n .req_bank_rdy_r_reg(arb_mux0_n_106),\n .req_periodic_rd_r(req_periodic_rd_r[3]),\n .\\req_row_r_lcl_reg[10] (req_row_r[25]),\n .req_wr_r(req_wr_r[2]),\n .req_wr_r_lcl_reg(\\bank_cntrl[2].bank0_n_40 ),\n .req_wr_r_lcl_reg_0(req_wr_r_lcl_reg_1),\n .\\rnk_config_strobe_r_reg[0] (\\bank_cntrl[3].bank0_n_69 ),\n .rnk_config_valid_r_lcl_reg(arb_mux0_n_96),\n .row_cmd_wr(row_cmd_wr),\n .row_hit_r_12(row_hit_r_12),\n .\\rp_timer.rp_timer_r_reg[1] (auto_pre_r_29),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22),\n .rtp_timer_ns1_6(rtp_timer_ns1_6),\n .\\rtw_timer.rtw_cnt_r_reg[1] (arb_mux0_n_22),\n .\\starve_limit_cntr_r_reg[2] (col_wait_r_23),\n .tail_r_28(tail_r_28),\n .use_addr(use_addr),\n .wait_for_maint_r_20(wait_for_maint_r_20),\n .wait_for_maint_r_lcl_reg(head_r[3]),\n .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg_2),\n .wr_this_rank_r(wr_this_rank_r[3]),\n .\\wtr_timer.wtr_cnt_r_reg[1] (\\wtr_timer.wtr_cnt_r_reg[1]_1 ));\n ddr3_if_mig_7series_v4_0_bank_common bank_common0\n (.CLK(CLK),\n .D(D),\n .E(idle_r[0]),\n .Q(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6] ),\n .SR(SR),\n .accept_ns(accept_ns),\n .\\app_cmd_r1_reg[0] (\\app_cmd_r1_reg[0] ),\n .clear_periodic_rd_request(clear_periodic_rd_request),\n .\\generate_maint_cmds.insert_maint_r_lcl_reg_0 (\\generate_maint_cmds.insert_maint_r_lcl_reg ),\n .head_r(head_r),\n .head_r_lcl_reg(bank_common0_n_10),\n .head_r_lcl_reg_0(bank_common0_n_12),\n .head_r_lcl_reg_1(bank_common0_n_14),\n .head_r_lcl_reg_2(bank_common0_n_16),\n .idle_r_lcl_reg(idle_r[1]),\n .idle_r_lcl_reg_0(idle_r[2]),\n .idle_r_lcl_reg_1(idle_r[3]),\n .insert_maint_r1_lcl_reg(insert_maint_r),\n .\\maint_controller.maint_hit_busies_r_reg[3]_0 (\\maint_controller.maint_hit_busies_r_reg[3] ),\n .\\maint_controller.maint_rdy_r1_reg_0 (\\maint_controller.maint_rdy_r1_reg ),\n .\\maint_controller.maint_wip_r_lcl_reg_0 (maint_wip_r),\n .maint_req_r(maint_req_r),\n .maint_srx_r(maint_srx_r),\n .\\maintenance_request.maint_req_r_lcl_reg (\\maintenance_request.maint_req_r_lcl_reg ),\n .\\maintenance_request.maint_zq_r_lcl_reg (\\maintenance_request.maint_zq_r_lcl_reg ),\n .ordered_r_lcl_reg(ordered_r_lcl_reg_1),\n .ordered_r_lcl_reg_0(ordered_r_lcl_reg),\n .ordered_r_lcl_reg_1(ordered_r_lcl_reg_0),\n .p_9_in(p_9_in),\n .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg),\n .pass_open_bank_r_lcl_reg_0(pass_open_bank_r_lcl_reg_0),\n .periodic_rd_grant_r(periodic_rd_grant_r),\n .periodic_rd_insert(periodic_rd_insert),\n .periodic_rd_r(periodic_rd_r),\n .\\periodic_read_request.periodic_rd_r_lcl_reg (\\periodic_read_request.periodic_rd_r_lcl_reg ),\n .\\q_entry_r_reg[0] (\\q_entry_r_reg[0]_1 ),\n .\\q_entry_r_reg[0]_0 (bank_common0_n_19),\n .\\q_entry_r_reg[1] (\\q_entry_r_reg[1] ),\n .\\q_entry_r_reg[1]_0 (\\q_entry_r_reg[1]_2 ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] (head_r_lcl_reg_2),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] (\\bank_cntrl[1].bank0_n_43 ),\n .rb_hit_busy_r(rb_hit_busy_r[3:2]),\n .req_periodic_rd_r_lcl_reg(periodic_rd_cntr_r),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 (\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0 (\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 (\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ),\n .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22),\n .use_addr(use_addr),\n .wait_for_maint_r_lcl_reg(accept_internal_r),\n .was_wr(was_wr),\n .was_wr_reg_0(periodic_rd_ack_r));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_bank_queue\n (\\req_data_buf_addr_r_reg[4] ,\n E,\n act_wait_r_lcl_reg,\n pre_bm_end_r,\n pre_passing_open_bank_r,\n q_has_rd,\n q_has_priority,\n wait_for_maint_r,\n tail_r,\n wait_for_maint_r_lcl_reg_0,\n \\rp_timer.rp_timer_r_reg[1] ,\n ordered_r,\n D,\n accept_internal_r_reg,\n \\q_entry_r_reg[0]_0 ,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ,\n granted_col_ns,\n granted_col_r_reg,\n \\grant_r_reg[1] ,\n \\ras_timer_r_reg[2] ,\n \\ras_timer_r_reg[0] ,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ,\n demand_priority_r_reg,\n req_bank_rdy_ns,\n act_wait_ns,\n \\ras_timer_r_reg[0]_0 ,\n \\q_entry_r_reg[1]_0 ,\n q_entry_ns,\n \\q_entry_r_reg[1]_1 ,\n \\q_entry_r_reg[1]_2 ,\n \\q_entry_r_reg[0]_1 ,\n p_9_in,\n head_r_lcl_reg_0,\n head_r_lcl_reg_1,\n \\q_entry_r_reg[1]_3 ,\n p_145_out,\n \\ras_timer_r_reg[0]_1 ,\n head_r_lcl_reg_2,\n CLK,\n pass_open_bank_ns,\n pre_bm_end_ns,\n pre_passing_open_bank_ns,\n q_has_rd_r_reg_0,\n q_has_priority_r_reg_0,\n \\maintenance_request.maint_req_r_lcl_reg ,\n wait_for_maint_r_lcl_reg_1,\n SR,\n idle_r_lcl_reg_0,\n rstdiv0_sync_r1_reg_rep__0,\n head_r_lcl_reg_3,\n auto_pre_r_lcl_reg_0,\n ordered_r_lcl_reg_0,\n \\req_bank_r_lcl_reg[0] ,\n idle_r_lcl_reg_1,\n Q,\n rstdiv0_sync_r1_reg_rep__20,\n idle_r_lcl_reg_2,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ,\n idle_r_lcl_reg_3,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ,\n rd_wr_r_lcl_reg,\n rd_wr_r_lcl_reg_0,\n \\rtw_timer.rtw_cnt_r_reg[1] ,\n col_wait_r_reg,\n override_demand_r_reg,\n rd_wr_r_lcl_reg_1,\n \\wtr_timer.wtr_cnt_r_reg[1] ,\n \\ras_timer_r_reg[1] ,\n rd_wr_r_lcl_reg_2,\n \\ras_timer_r_reg[1]_0 ,\n \\ras_timer_r_reg[1]_1 ,\n bm_end_r1_reg,\n bm_end_r1_reg_0,\n bm_end_r1_reg_1,\n bm_end_r1_reg_2,\n bm_end_r1_reg_3,\n \\ras_timer_r_reg[2]_0 ,\n \\ras_timer_r_reg[2]_1 ,\n \\ras_timer_r_reg[2]_2 ,\n req_priority_r,\n req_wr_r_lcl_reg,\n rd_wr_r_lcl_reg_3,\n req_wr_r_lcl_reg_0,\n rnk_config_valid_r_lcl_reg,\n col_wait_r_reg_0,\n act_wait_r_lcl_reg_0,\n \\grant_r_reg[0] ,\n bm_end_r1_reg_4,\n pre_passing_open_bank_r_reg_0,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ,\n pre_passing_open_bank_r_reg_1,\n \\q_entry_r_reg[1]_4 ,\n pre_bm_end_r_reg_0,\n pre_bm_end_r_reg_1,\n \\q_entry_r_reg[1]_5 ,\n periodic_rd_ack_r_lcl_reg,\n init_calib_complete_reg_rep__6,\n rb_hit_busy_r_reg,\n rb_hit_busy_r_reg_0,\n accept_r_reg,\n periodic_rd_ack_r_lcl_reg_0,\n pre_bm_end_r_reg_2,\n periodic_rd_ack_r_lcl_reg_1,\n use_addr,\n accept_internal_r_reg_0,\n req_wr_r_lcl_reg_1,\n req_wr_r_lcl_reg_2,\n \\grant_r_reg[0]_0 ,\n idle_r_lcl_reg_4,\n idle_r_lcl_reg_5,\n idle_r_lcl_reg_6,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ,\n rb_hit_busy_r_reg_1,\n idle_r_lcl_reg_7,\n ordered_r_lcl_reg_1,\n ordered_r_lcl_reg_2);\n output \\req_data_buf_addr_r_reg[4] ;\n output [0:0]E;\n output act_wait_r_lcl_reg;\n output pre_bm_end_r;\n output pre_passing_open_bank_r;\n output q_has_rd;\n output q_has_priority;\n output wait_for_maint_r;\n output tail_r;\n output wait_for_maint_r_lcl_reg_0;\n output \\rp_timer.rp_timer_r_reg[1] ;\n output [0:0]ordered_r;\n output [0:0]D;\n output accept_internal_r_reg;\n output \\q_entry_r_reg[0]_0 ;\n output [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;\n output [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;\n output granted_col_ns;\n output granted_col_r_reg;\n output \\grant_r_reg[1] ;\n output [2:0]\\ras_timer_r_reg[2] ;\n output \\ras_timer_r_reg[0] ;\n output [2:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;\n output demand_priority_r_reg;\n output req_bank_rdy_ns;\n output act_wait_ns;\n output \\ras_timer_r_reg[0]_0 ;\n output \\q_entry_r_reg[1]_0 ;\n output [0:0]q_entry_ns;\n output \\q_entry_r_reg[1]_1 ;\n output \\q_entry_r_reg[1]_2 ;\n output \\q_entry_r_reg[0]_1 ;\n output p_9_in;\n output head_r_lcl_reg_0;\n output head_r_lcl_reg_1;\n output \\q_entry_r_reg[1]_3 ;\n output p_145_out;\n output \\ras_timer_r_reg[0]_1 ;\n output head_r_lcl_reg_2;\n input CLK;\n input pass_open_bank_ns;\n input pre_bm_end_ns;\n input pre_passing_open_bank_ns;\n input q_has_rd_r_reg_0;\n input q_has_priority_r_reg_0;\n input \\maintenance_request.maint_req_r_lcl_reg ;\n input wait_for_maint_r_lcl_reg_1;\n input [0:0]SR;\n input idle_r_lcl_reg_0;\n input rstdiv0_sync_r1_reg_rep__0;\n input head_r_lcl_reg_3;\n input auto_pre_r_lcl_reg_0;\n input ordered_r_lcl_reg_0;\n input \\req_bank_r_lcl_reg[0] ;\n input idle_r_lcl_reg_1;\n input [0:0]Q;\n input rstdiv0_sync_r1_reg_rep__20;\n input idle_r_lcl_reg_2;\n input [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ;\n input idle_r_lcl_reg_3;\n input [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ;\n input rd_wr_r_lcl_reg;\n input rd_wr_r_lcl_reg_0;\n input \\rtw_timer.rtw_cnt_r_reg[1] ;\n input col_wait_r_reg;\n input override_demand_r_reg;\n input rd_wr_r_lcl_reg_1;\n input \\wtr_timer.wtr_cnt_r_reg[1] ;\n input \\ras_timer_r_reg[1] ;\n input rd_wr_r_lcl_reg_2;\n input \\ras_timer_r_reg[1]_0 ;\n input \\ras_timer_r_reg[1]_1 ;\n input bm_end_r1_reg;\n input bm_end_r1_reg_0;\n input bm_end_r1_reg_1;\n input bm_end_r1_reg_2;\n input bm_end_r1_reg_3;\n input \\ras_timer_r_reg[2]_0 ;\n input \\ras_timer_r_reg[2]_1 ;\n input \\ras_timer_r_reg[2]_2 ;\n input req_priority_r;\n input req_wr_r_lcl_reg;\n input rd_wr_r_lcl_reg_3;\n input req_wr_r_lcl_reg_0;\n input rnk_config_valid_r_lcl_reg;\n input col_wait_r_reg_0;\n input act_wait_r_lcl_reg_0;\n input [0:0]\\grant_r_reg[0] ;\n input bm_end_r1_reg_4;\n input pre_passing_open_bank_r_reg_0;\n input \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ;\n input pre_passing_open_bank_r_reg_1;\n input \\q_entry_r_reg[1]_4 ;\n input pre_bm_end_r_reg_0;\n input pre_bm_end_r_reg_1;\n input \\q_entry_r_reg[1]_5 ;\n input periodic_rd_ack_r_lcl_reg;\n input init_calib_complete_reg_rep__6;\n input rb_hit_busy_r_reg;\n input rb_hit_busy_r_reg_0;\n input accept_r_reg;\n input periodic_rd_ack_r_lcl_reg_0;\n input pre_bm_end_r_reg_2;\n input periodic_rd_ack_r_lcl_reg_1;\n input use_addr;\n input accept_internal_r_reg_0;\n input req_wr_r_lcl_reg_1;\n input req_wr_r_lcl_reg_2;\n input [0:0]\\grant_r_reg[0]_0 ;\n input [0:0]idle_r_lcl_reg_4;\n input [0:0]idle_r_lcl_reg_5;\n input [0:0]idle_r_lcl_reg_6;\n input [2:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ;\n input rb_hit_busy_r_reg_1;\n input idle_r_lcl_reg_7;\n input ordered_r_lcl_reg_1;\n input ordered_r_lcl_reg_2;\n\n wire CLK;\n wire [0:0]D;\n wire [0:0]E;\n wire [0:0]Q;\n wire [0:0]SR;\n wire accept_internal_r_reg;\n wire accept_internal_r_reg_0;\n wire accept_r_reg;\n wire act_wait_ns;\n wire act_wait_r_lcl_reg;\n wire act_wait_r_lcl_reg_0;\n wire auto_pre_r_lcl_reg_0;\n wire bm_end_r1_reg;\n wire bm_end_r1_reg_0;\n wire bm_end_r1_reg_1;\n wire bm_end_r1_reg_2;\n wire bm_end_r1_reg_3;\n wire bm_end_r1_reg_4;\n wire col_wait_r_reg;\n wire col_wait_r_reg_0;\n wire demand_priority_r_reg;\n wire \\grant_r[1]_i_6_n_0 ;\n wire [0:0]\\grant_r_reg[0] ;\n wire [0:0]\\grant_r_reg[0]_0 ;\n wire \\grant_r_reg[1] ;\n wire granted_col_ns;\n wire granted_col_r_reg;\n wire head_r_lcl_reg_0;\n wire head_r_lcl_reg_1;\n wire head_r_lcl_reg_2;\n wire head_r_lcl_reg_3;\n wire idle_r_lcl_reg_0;\n wire idle_r_lcl_reg_1;\n wire idle_r_lcl_reg_2;\n wire idle_r_lcl_reg_3;\n wire [0:0]idle_r_lcl_reg_4;\n wire [0:0]idle_r_lcl_reg_5;\n wire [0:0]idle_r_lcl_reg_6;\n wire idle_r_lcl_reg_7;\n wire init_calib_complete_reg_rep__6;\n wire \\maintenance_request.maint_req_r_lcl_reg ;\n wire [1:0]order_q_r;\n wire \\order_q_r[0]_i_1_n_0 ;\n wire \\order_q_r[1]_i_1_n_0 ;\n wire [0:0]ordered_r;\n wire ordered_r_lcl_reg_0;\n wire ordered_r_lcl_reg_1;\n wire ordered_r_lcl_reg_2;\n wire override_demand_r_reg;\n wire p_145_out;\n wire p_9_in;\n wire pass_open_bank_ns;\n wire periodic_rd_ack_r_lcl_reg;\n wire periodic_rd_ack_r_lcl_reg_0;\n wire periodic_rd_ack_r_lcl_reg_1;\n wire pre_bm_end_ns;\n wire pre_bm_end_r;\n wire pre_bm_end_r_reg_0;\n wire pre_bm_end_r_reg_1;\n wire pre_bm_end_r_reg_2;\n wire pre_passing_open_bank_ns;\n wire pre_passing_open_bank_r;\n wire pre_passing_open_bank_r_reg_0;\n wire pre_passing_open_bank_r_reg_1;\n wire [0:0]q_entry_ns;\n wire [1:1]q_entry_ns_0;\n wire [1:0]q_entry_r;\n wire \\q_entry_r[0]_i_1_n_0 ;\n wire \\q_entry_r[1]_i_1_n_0 ;\n wire \\q_entry_r[1]_i_3__2_n_0 ;\n wire \\q_entry_r[1]_i_4__1_n_0 ;\n wire \\q_entry_r[1]_i_5__0_n_0 ;\n wire \\q_entry_r_reg[0]_0 ;\n wire \\q_entry_r_reg[0]_1 ;\n wire \\q_entry_r_reg[1]_0 ;\n wire \\q_entry_r_reg[1]_1 ;\n wire \\q_entry_r_reg[1]_2 ;\n wire \\q_entry_r_reg[1]_3 ;\n wire \\q_entry_r_reg[1]_4 ;\n wire \\q_entry_r_reg[1]_5 ;\n wire q_has_priority;\n wire q_has_priority_r_reg_0;\n wire q_has_rd;\n wire q_has_rd_r_reg_0;\n wire \\ras_timer_r[0]_i_2_n_0 ;\n wire \\ras_timer_r[1]_i_2_n_0 ;\n wire \\ras_timer_r[2]_i_2_n_0 ;\n wire \\ras_timer_r_reg[0] ;\n wire \\ras_timer_r_reg[0]_0 ;\n wire \\ras_timer_r_reg[0]_1 ;\n wire \\ras_timer_r_reg[1] ;\n wire \\ras_timer_r_reg[1]_0 ;\n wire \\ras_timer_r_reg[1]_1 ;\n wire [2:0]\\ras_timer_r_reg[2] ;\n wire \\ras_timer_r_reg[2]_0 ;\n wire \\ras_timer_r_reg[2]_1 ;\n wire \\ras_timer_r_reg[2]_2 ;\n wire \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ;\n wire [2:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;\n wire [2:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ;\n wire rb_hit_busy_r_reg;\n wire rb_hit_busy_r_reg_0;\n wire rb_hit_busy_r_reg_1;\n wire rd_wr_r_lcl_reg;\n wire rd_wr_r_lcl_reg_0;\n wire rd_wr_r_lcl_reg_1;\n wire rd_wr_r_lcl_reg_2;\n wire rd_wr_r_lcl_reg_3;\n wire \\req_bank_r_lcl_reg[0] ;\n wire req_bank_rdy_ns;\n wire \\req_data_buf_addr_r_reg[4] ;\n wire req_priority_r;\n wire req_wr_r_lcl_reg;\n wire req_wr_r_lcl_reg_0;\n wire req_wr_r_lcl_reg_1;\n wire req_wr_r_lcl_reg_2;\n wire rnk_config_valid_r_lcl_reg;\n wire \\rp_timer.rp_timer_r_reg[1] ;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire \\rtw_timer.rtw_cnt_r_reg[1] ;\n wire set_order_q;\n wire tail_r;\n wire use_addr;\n wire wait_for_maint_r;\n wire wait_for_maint_r_lcl_reg_0;\n wire wait_for_maint_r_lcl_reg_1;\n wire \\wtr_timer.wtr_cnt_r_reg[1] ;\n\n (* SOFT_HLUTNM = \"soft_lutpair1053\" *) \n LUT5 #(\n .INIT(32'h2AAAAAAA)) \n accept_internal_r_i_1\n (.I0(init_calib_complete_reg_rep__6),\n .I1(accept_internal_r_reg),\n .I2(idle_r_lcl_reg_3),\n .I3(idle_r_lcl_reg_2),\n .I4(idle_r_lcl_reg_1),\n .O(p_9_in));\n LUT6 #(\n .INIT(64'hFFFFFFFF0404FF04)) \n act_wait_r_lcl_i_1__0\n (.I0(\\ras_timer_r_reg[0] ),\n .I1(act_wait_r_lcl_reg_0),\n .I2(\\grant_r_reg[0] ),\n .I3(act_wait_r_lcl_reg),\n .I4(\\q_entry_r_reg[0]_0 ),\n .I5(bm_end_r1_reg_4),\n .O(act_wait_ns));\n LUT6 #(\n .INIT(64'h00000000F4F4FFF4)) \n act_wait_r_lcl_i_2__0\n (.I0(pre_passing_open_bank_r_reg_0),\n .I1(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 [2]),\n .I2(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ),\n .I3(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 [0]),\n .I4(pre_passing_open_bank_r_reg_1),\n .I5(\\ras_timer_r_reg[0]_0 ),\n .O(\\ras_timer_r_reg[0] ));\n LUT5 #(\n .INIT(32'h55151515)) \n act_wait_r_lcl_i_4\n (.I0(pre_passing_open_bank_r),\n .I1(\\grant_r_reg[0]_0 ),\n .I2(act_wait_r_lcl_reg),\n .I3(rd_wr_r_lcl_reg_1),\n .I4(req_wr_r_lcl_reg_2),\n .O(\\ras_timer_r_reg[0]_1 ));\n FDRE auto_pre_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(auto_pre_r_lcl_reg_0),\n .Q(\\rp_timer.rp_timer_r_reg[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b1)) \n \\compute_tail.tail_r_lcl_reg \n (.C(CLK),\n .CE(1'b1),\n .D(idle_r_lcl_reg_0),\n .Q(tail_r),\n .R(SR));\n LUT6 #(\n .INIT(64'hE0E0E0EEE0EEE0EE)) \n demand_priority_r_i_3__1\n (.I0(req_priority_r),\n .I1(q_has_priority),\n .I2(rd_wr_r_lcl_reg_1),\n .I3(order_q_r[1]),\n .I4(order_q_r[0]),\n .I5(req_wr_r_lcl_reg),\n .O(demand_priority_r_reg));\n LUT6 #(\n .INIT(64'h0003000200000002)) \n \\grant_r[1]_i_4 \n (.I0(\\rtw_timer.rtw_cnt_r_reg[1] ),\n .I1(col_wait_r_reg),\n .I2(\\grant_r[1]_i_6_n_0 ),\n .I3(override_demand_r_reg),\n .I4(rd_wr_r_lcl_reg_1),\n .I5(\\wtr_timer.wtr_cnt_r_reg[1] ),\n .O(\\grant_r_reg[1] ));\n LUT6 #(\n .INIT(64'hFFFFFFFF44544444)) \n \\grant_r[1]_i_6 \n (.I0(rd_wr_r_lcl_reg_1),\n .I1(order_q_r[1]),\n .I2(order_q_r[0]),\n .I3(rd_wr_r_lcl_reg_3),\n .I4(req_wr_r_lcl_reg_0),\n .I5(rnk_config_valid_r_lcl_reg),\n .O(\\grant_r[1]_i_6_n_0 ));\n LUT2 #(\n .INIT(4'hB)) \n \\grant_r[3]_i_3 \n (.I0(\\grant_r_reg[1] ),\n .I1(rd_wr_r_lcl_reg_0),\n .O(granted_col_r_reg));\n LUT2 #(\n .INIT(4'hB)) \n granted_col_r_i_1\n (.I0(granted_col_r_reg),\n .I1(rd_wr_r_lcl_reg),\n .O(granted_col_ns));\n FDSE head_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(head_r_lcl_reg_3),\n .Q(wait_for_maint_r_lcl_reg_0),\n .S(rstdiv0_sync_r1_reg_rep__0));\n LUT5 #(\n .INIT(32'h55151515)) \n i___0_i_1\n (.I0(pre_bm_end_r),\n .I1(\\grant_r_reg[0]_0 ),\n .I2(act_wait_r_lcl_reg),\n .I3(rd_wr_r_lcl_reg_1),\n .I4(req_wr_r_lcl_reg_2),\n .O(\\q_entry_r_reg[0]_0 ));\n LUT6 #(\n .INIT(64'h00FF000014141414)) \n i___1_i_1\n (.I0(rb_hit_busy_r_reg),\n .I1(rb_hit_busy_r_reg_0),\n .I2(head_r_lcl_reg_1),\n .I3(q_entry_r[1]),\n .I4(q_entry_r[0]),\n .I5(accept_r_reg),\n .O(head_r_lcl_reg_0));\n (* SOFT_HLUTNM = \"soft_lutpair1054\" *) \n LUT5 #(\n .INIT(32'h01168001)) \n i___1_i_2\n (.I0(\\req_data_buf_addr_r_reg[4] ),\n .I1(idle_r_lcl_reg_4),\n .I2(idle_r_lcl_reg_5),\n .I3(idle_r_lcl_reg_6),\n .I4(periodic_rd_ack_r_lcl_reg),\n .O(head_r_lcl_reg_2));\n LUT5 #(\n .INIT(32'hFFC5FFFF)) \n i___1_i_3\n (.I0(head_r_lcl_reg_1),\n .I1(periodic_rd_ack_r_lcl_reg),\n .I2(\\req_data_buf_addr_r_reg[4] ),\n .I3(periodic_rd_ack_r_lcl_reg_0),\n .I4(\\q_entry_r_reg[0]_0 ),\n .O(\\q_entry_r_reg[1]_3 ));\n (* SOFT_HLUTNM = \"soft_lutpair1057\" *) \n LUT3 #(\n .INIT(8'hFB)) \n i___37_i_1\n (.I0(\\req_data_buf_addr_r_reg[4] ),\n .I1(q_entry_r[0]),\n .I2(q_entry_r[1]),\n .O(\\ras_timer_r_reg[0]_0 ));\n LUT6 #(\n .INIT(64'hBB0BBB0B0000BB0B)) \n i___44_i_1\n (.I0(pre_bm_end_r_reg_1),\n .I1(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 [1]),\n .I2(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 [2]),\n .I3(pre_bm_end_r_reg_2),\n .I4(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 [0]),\n .I5(pre_bm_end_r_reg_0),\n .O(head_r_lcl_reg_1));\n LUT6 #(\n .INIT(64'h00000000FD555555)) \n i___55_i_1\n (.I0(\\req_data_buf_addr_r_reg[4] ),\n .I1(periodic_rd_ack_r_lcl_reg_1),\n .I2(use_addr),\n .I3(accept_internal_r_reg_0),\n .I4(wait_for_maint_r_lcl_reg_0),\n .I5(req_wr_r_lcl_reg_1),\n .O(accept_internal_r_reg));\n (* SOFT_HLUTNM = \"soft_lutpair1053\" *) \n LUT1 #(\n .INIT(2'h1)) \n idle_r_lcl_i_1__2\n (.I0(accept_internal_r_reg),\n .O(E));\n FDRE idle_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(E),\n .Q(\\req_data_buf_addr_r_reg[4] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h553100305531CC30)) \n \\order_q_r[0]_i_1 \n (.I0(ordered_r_lcl_reg_2),\n .I1(order_q_r[0]),\n .I2(order_q_r[1]),\n .I3(req_wr_r_lcl_reg),\n .I4(set_order_q),\n .I5(rstdiv0_sync_r1_reg_rep__20),\n .O(\\order_q_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAAC200C0AAC2F0C0)) \n \\order_q_r[1]_i_1 \n (.I0(ordered_r_lcl_reg_1),\n .I1(order_q_r[0]),\n .I2(order_q_r[1]),\n .I3(req_wr_r_lcl_reg),\n .I4(set_order_q),\n .I5(rstdiv0_sync_r1_reg_rep__20),\n .O(\\order_q_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8000800080000000)) \n \\order_q_r[1]_i_3 \n (.I0(req_wr_r_lcl_reg_2),\n .I1(\\req_data_buf_addr_r_reg[4] ),\n .I2(wait_for_maint_r_lcl_reg_0),\n .I3(accept_internal_r_reg_0),\n .I4(use_addr),\n .I5(periodic_rd_ack_r_lcl_reg_1),\n .O(set_order_q));\n FDRE \\order_q_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\order_q_r[0]_i_1_n_0 ),\n .Q(order_q_r[0]),\n .R(1'b0));\n FDRE \\order_q_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\order_q_r[1]_i_1_n_0 ),\n .Q(order_q_r[1]),\n .R(1'b0));\n FDRE ordered_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(ordered_r_lcl_reg_0),\n .Q(ordered_r),\n .R(1'b0));\n FDRE pass_open_bank_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pass_open_bank_ns),\n .Q(act_wait_r_lcl_reg),\n .R(1'b0));\n FDRE pre_bm_end_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pre_bm_end_ns),\n .Q(pre_bm_end_r),\n .R(1'b0));\n FDRE pre_passing_open_bank_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pre_passing_open_bank_ns),\n .Q(pre_passing_open_bank_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hB380FFFFBF8C0000)) \n \\q_entry_r[0]_i_1 \n (.I0(rb_hit_busy_r_reg_1),\n .I1(\\q_entry_r_reg[0]_0 ),\n .I2(periodic_rd_ack_r_lcl_reg_0),\n .I3(idle_r_lcl_reg_7),\n .I4(\\q_entry_r_reg[1]_3 ),\n .I5(q_entry_r[0]),\n .O(\\q_entry_r[0]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h6996)) \n \\q_entry_r[0]_i_3 \n (.I0(pre_bm_end_r_reg_1),\n .I1(\\q_entry_r_reg[0]_0 ),\n .I2(\\q_entry_r[1]_i_3__2_n_0 ),\n .I3(pre_bm_end_r_reg_0),\n .O(\\q_entry_r_reg[0]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair1057\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\q_entry_r[1]_i_1 \n (.I0(q_entry_ns_0),\n .I1(\\q_entry_r_reg[1]_3 ),\n .I2(q_entry_r[1]),\n .O(\\q_entry_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hBB888BB8B88BBB88)) \n \\q_entry_r[1]_i_2 \n (.I0(\\q_entry_r_reg[1]_5 ),\n .I1(pre_bm_end_r_reg_0),\n .I2(periodic_rd_ack_r_lcl_reg),\n .I3(\\q_entry_r[1]_i_5__0_n_0 ),\n .I4(\\q_entry_r[1]_i_3__2_n_0 ),\n .I5(\\q_entry_r_reg[0]_0 ),\n .O(q_entry_ns));\n (* SOFT_HLUTNM = \"soft_lutpair1055\" *) \n LUT5 #(\n .INIT(32'hA9956AA9)) \n \\q_entry_r[1]_i_2__0 \n (.I0(\\q_entry_r[1]_i_5__0_n_0 ),\n .I1(pre_bm_end_r_reg_1),\n .I2(pre_bm_end_r_reg_0),\n .I3(\\q_entry_r_reg[0]_0 ),\n .I4(\\q_entry_r[1]_i_3__2_n_0 ),\n .O(\\q_entry_r_reg[1]_1 ));\n LUT5 #(\n .INIT(32'h0BFB04F4)) \n \\q_entry_r[1]_i_2__2 \n (.I0(\\q_entry_r[1]_i_3__2_n_0 ),\n .I1(periodic_rd_ack_r_lcl_reg),\n .I2(\\q_entry_r_reg[0]_0 ),\n .I3(\\q_entry_r[1]_i_4__1_n_0 ),\n .I4(\\q_entry_r[1]_i_5__0_n_0 ),\n .O(q_entry_ns_0));\n LUT6 #(\n .INIT(64'h55555555C3CC33C3)) \n \\q_entry_r[1]_i_3 \n (.I0(\\q_entry_r_reg[1]_4 ),\n .I1(\\q_entry_r[1]_i_5__0_n_0 ),\n .I2(pre_bm_end_r_reg_0),\n .I3(\\q_entry_r[1]_i_3__2_n_0 ),\n .I4(\\q_entry_r_reg[0]_0 ),\n .I5(pre_bm_end_r_reg_1),\n .O(\\q_entry_r_reg[1]_0 ));\n LUT4 #(\n .INIT(16'h6996)) \n \\q_entry_r[1]_i_3__2 \n (.I0(\\req_data_buf_addr_r_reg[4] ),\n .I1(idle_r_lcl_reg_4),\n .I2(idle_r_lcl_reg_5),\n .I3(idle_r_lcl_reg_6),\n .O(\\q_entry_r[1]_i_3__2_n_0 ));\n LUT6 #(\n .INIT(64'h1E001EFF1EFF1E00)) \n \\q_entry_r[1]_i_4__1 \n (.I0(rb_hit_busy_r_reg_0),\n .I1(head_r_lcl_reg_1),\n .I2(rb_hit_busy_r_reg),\n .I3(periodic_rd_ack_r_lcl_reg_0),\n .I4(q_entry_r[1]),\n .I5(q_entry_r[0]),\n .O(\\q_entry_r[1]_i_4__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1055\" *) \n LUT5 #(\n .INIT(32'hD4422BBD)) \n \\q_entry_r[1]_i_5 \n (.I0(\\q_entry_r[1]_i_3__2_n_0 ),\n .I1(\\q_entry_r_reg[0]_0 ),\n .I2(pre_bm_end_r_reg_0),\n .I3(pre_bm_end_r_reg_1),\n .I4(\\q_entry_r[1]_i_5__0_n_0 ),\n .O(\\q_entry_r_reg[1]_2 ));\n (* SOFT_HLUTNM = \"soft_lutpair1054\" *) \n LUT4 #(\n .INIT(16'h7EE8)) \n \\q_entry_r[1]_i_5__0 \n (.I0(\\req_data_buf_addr_r_reg[4] ),\n .I1(idle_r_lcl_reg_6),\n .I2(idle_r_lcl_reg_5),\n .I3(idle_r_lcl_reg_4),\n .O(\\q_entry_r[1]_i_5__0_n_0 ));\n FDRE \\q_entry_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\q_entry_r[0]_i_1_n_0 ),\n .Q(q_entry_r[0]),\n .R(SR));\n FDRE \\q_entry_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\q_entry_r[1]_i_1_n_0 ),\n .Q(q_entry_r[1]),\n .R(SR));\n FDRE q_has_priority_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(q_has_priority_r_reg_0),\n .Q(q_has_priority),\n .R(1'b0));\n FDRE q_has_rd_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(q_has_rd_r_reg_0),\n .Q(q_has_rd),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1056\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\ras_timer_r[0]_i_1 \n (.I0(\\ras_timer_r[0]_i_2_n_0 ),\n .I1(\\ras_timer_r_reg[0] ),\n .I2(\\ras_timer_r_reg[1] ),\n .O(\\ras_timer_r_reg[2] [0]));\n LUT6 #(\n .INIT(64'hB8B8B8B8BB888888)) \n \\ras_timer_r[0]_i_2 \n (.I0(rd_wr_r_lcl_reg_2),\n .I1(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 [2]),\n .I2(\\ras_timer_r_reg[1]_0 ),\n .I3(\\ras_timer_r_reg[1]_1 ),\n .I4(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 [0]),\n .I5(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 [1]),\n .O(\\ras_timer_r[0]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1056\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\ras_timer_r[1]_i_1__0 \n (.I0(\\ras_timer_r[1]_i_2_n_0 ),\n .I1(\\ras_timer_r_reg[0] ),\n .I2(bm_end_r1_reg),\n .O(\\ras_timer_r_reg[2] [1]));\n LUT6 #(\n .INIT(64'hB8B8B8B888BB8888)) \n \\ras_timer_r[1]_i_2 \n (.I0(bm_end_r1_reg_0),\n .I1(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 [2]),\n .I2(bm_end_r1_reg_1),\n .I3(bm_end_r1_reg_2),\n .I4(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 [0]),\n .I5(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 [1]),\n .O(\\ras_timer_r[1]_i_2_n_0 ));\n LUT3 #(\n .INIT(8'hB8)) \n \\ras_timer_r[2]_i_1__0 \n (.I0(\\ras_timer_r[2]_i_2_n_0 ),\n .I1(\\ras_timer_r_reg[0] ),\n .I2(bm_end_r1_reg_3),\n .O(\\ras_timer_r_reg[2] [2]));\n LUT6 #(\n .INIT(64'hBBBBB8888888B888)) \n \\ras_timer_r[2]_i_2 \n (.I0(\\ras_timer_r_reg[2]_0 ),\n .I1(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 [2]),\n .I2(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 [0]),\n .I3(\\ras_timer_r_reg[2]_1 ),\n .I4(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 [1]),\n .I5(\\ras_timer_r_reg[2]_2 ),\n .O(\\ras_timer_r[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00000000F2020000)) \n \\rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1 \n (.I0(accept_internal_r_reg),\n .I1(\\req_bank_r_lcl_reg[0] ),\n .I2(idle_r_lcl_reg_1),\n .I3(Q),\n .I4(\\q_entry_r_reg[0]_0 ),\n .I5(rstdiv0_sync_r1_reg_rep__20),\n .O(D));\n LUT6 #(\n .INIT(64'h00000000F2020000)) \n \\rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__0 \n (.I0(accept_internal_r_reg),\n .I1(\\req_bank_r_lcl_reg[0] ),\n .I2(idle_r_lcl_reg_2),\n .I3(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ),\n .I4(\\q_entry_r_reg[0]_0 ),\n .I5(rstdiv0_sync_r1_reg_rep__20),\n .O(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ));\n LUT6 #(\n .INIT(64'h00000000F2020000)) \n \\rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__1 \n (.I0(accept_internal_r_reg),\n .I1(\\req_bank_r_lcl_reg[0] ),\n .I2(idle_r_lcl_reg_3),\n .I3(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ),\n .I4(\\q_entry_r_reg[0]_0 ),\n .I5(rstdiv0_sync_r1_reg_rep__20),\n .O(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 [0]),\n .Q(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 [1]),\n .Q(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 [2]),\n .Q(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 [2]),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h2)) \n rb_hit_busy_r_i_1__2\n (.I0(accept_internal_r_reg),\n .I1(\\req_bank_r_lcl_reg[0] ),\n .O(p_145_out));\n LUT5 #(\n .INIT(32'h888A8A8A)) \n req_bank_rdy_r_i_1__2\n (.I0(col_wait_r_reg_0),\n .I1(rd_wr_r_lcl_reg_1),\n .I2(order_q_r[1]),\n .I3(order_q_r[0]),\n .I4(req_wr_r_lcl_reg),\n .O(req_bank_rdy_ns));\n FDRE wait_for_maint_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wait_for_maint_r_lcl_reg_1),\n .Q(wait_for_maint_r),\n .R(\\maintenance_request.maint_req_r_lcl_reg ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_bank_queue\" *) \nmodule ddr3_if_mig_7series_v4_0_bank_queue__parameterized0\n (\\req_data_buf_addr_r_reg[4] ,\n E,\n act_wait_r_lcl_reg,\n bm_end_r1_reg,\n q_has_rd_3,\n q_has_priority_4,\n wait_for_maint_r_18,\n tail_r_24,\n wait_for_maint_r_lcl_reg_0,\n \\rp_timer.rp_timer_r_reg[1] ,\n ordered_r,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] ,\n rb_hit_busy_r_reg,\n \\q_entry_r_reg[0]_0 ,\n D,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ,\n \\ras_timer_r_reg[2] ,\n \\ras_timer_r_reg[0] ,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ,\n demand_priority_r_reg,\n order_q_r,\n req_bank_rdy_ns,\n \\ras_timer_r_reg[0]_0 ,\n p_106_out,\n \\q_entry_r_reg[1]_0 ,\n \\q_entry_r_reg[1]_1 ,\n \\q_entry_r_reg[0]_1 ,\n act_wait_ns,\n head_r_lcl_reg_0,\n \\q_entry_r_reg[1]_2 ,\n \\ras_timer_r_reg[0]_1 ,\n \\grant_r_reg[1] ,\n CLK,\n pass_open_bank_ns,\n pre_bm_end_ns,\n pre_passing_open_bank_ns,\n q_has_rd_r_reg_0,\n q_has_priority_r_reg_0,\n \\maintenance_request.maint_req_r_lcl_reg ,\n wait_for_maint_r_lcl_reg_1,\n SR,\n idle_r_lcl_reg_0,\n rstdiv0_sync_r1_reg_rep__0,\n head_r_lcl_reg_1,\n auto_pre_r_lcl_reg_0,\n ordered_r_lcl_reg_0,\n \\req_bank_r_lcl_reg[2] ,\n idle_r_lcl_reg_1,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ,\n rstdiv0_sync_r1_reg_rep__20,\n idle_r_lcl_reg_2,\n Q,\n idle_r_lcl_reg_3,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ,\n \\ras_timer_r_reg[1] ,\n \\ras_timer_r_reg[1]_0 ,\n rd_wr_r_lcl_reg,\n \\ras_timer_r_reg[1]_1 ,\n bm_end_r1_reg_0,\n bm_end_r1_reg_1,\n bm_end_r1_reg_2,\n bm_end_r1_reg_3,\n \\ras_timer_r_reg[2]_0 ,\n bm_end_r1_reg_4,\n \\ras_timer_r_reg[2]_1 ,\n \\ras_timer_r_reg[2]_2 ,\n req_priority_r,\n rd_wr_r_lcl_reg_0,\n req_wr_r_lcl_reg,\n col_wait_r_reg,\n \\grant_r_reg[1]_0 ,\n req_wr_r_lcl_reg_0,\n periodic_rd_ack_r_lcl_reg,\n use_addr,\n accept_internal_r_reg,\n req_wr_r_lcl_reg_1,\n pre_bm_end_r_reg_0,\n idle_r_lcl_reg_4,\n idle_r_lcl_reg_5,\n idle_r_lcl_reg_6,\n periodic_rd_ack_r_lcl_reg_0,\n periodic_rd_ack_r_lcl_reg_1,\n act_wait_r_lcl_reg_0,\n \\grant_r_reg[1]_1 ,\n bm_end_r1_reg_5,\n rb_hit_busy_r_reg_0,\n rb_hit_busy_r_reg_1,\n accept_r_reg,\n pre_passing_open_bank_r_reg_0,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ,\n pre_passing_open_bank_r_reg_1,\n pre_bm_end_r_reg_1,\n pre_bm_end_r_reg_2,\n ras_timer_zero_r,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ,\n q_entry_ns,\n idle_r_lcl_reg_7,\n ordered_r_lcl_reg_1,\n rstdiv0_sync_r1_reg_rep__21,\n ordered_r_lcl_reg_2);\n output \\req_data_buf_addr_r_reg[4] ;\n output [0:0]E;\n output act_wait_r_lcl_reg;\n output bm_end_r1_reg;\n output q_has_rd_3;\n output q_has_priority_4;\n output wait_for_maint_r_18;\n output tail_r_24;\n output wait_for_maint_r_lcl_reg_0;\n output \\rp_timer.rp_timer_r_reg[1] ;\n output [0:0]ordered_r;\n output [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] ;\n output rb_hit_busy_r_reg;\n output \\q_entry_r_reg[0]_0 ;\n output [0:0]D;\n output [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;\n output [2:0]\\ras_timer_r_reg[2] ;\n output \\ras_timer_r_reg[0] ;\n output [2:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;\n output demand_priority_r_reg;\n output [1:0]order_q_r;\n output req_bank_rdy_ns;\n output \\ras_timer_r_reg[0]_0 ;\n output p_106_out;\n output \\q_entry_r_reg[1]_0 ;\n output \\q_entry_r_reg[1]_1 ;\n output \\q_entry_r_reg[0]_1 ;\n output act_wait_ns;\n output head_r_lcl_reg_0;\n output \\q_entry_r_reg[1]_2 ;\n output \\ras_timer_r_reg[0]_1 ;\n output \\grant_r_reg[1] ;\n input CLK;\n input pass_open_bank_ns;\n input pre_bm_end_ns;\n input pre_passing_open_bank_ns;\n input q_has_rd_r_reg_0;\n input q_has_priority_r_reg_0;\n input \\maintenance_request.maint_req_r_lcl_reg ;\n input wait_for_maint_r_lcl_reg_1;\n input [0:0]SR;\n input idle_r_lcl_reg_0;\n input rstdiv0_sync_r1_reg_rep__0;\n input head_r_lcl_reg_1;\n input auto_pre_r_lcl_reg_0;\n input ordered_r_lcl_reg_0;\n input \\req_bank_r_lcl_reg[2] ;\n input idle_r_lcl_reg_1;\n input [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ;\n input rstdiv0_sync_r1_reg_rep__20;\n input idle_r_lcl_reg_2;\n input [0:0]Q;\n input idle_r_lcl_reg_3;\n input [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;\n input \\ras_timer_r_reg[1] ;\n input \\ras_timer_r_reg[1]_0 ;\n input rd_wr_r_lcl_reg;\n input \\ras_timer_r_reg[1]_1 ;\n input bm_end_r1_reg_0;\n input bm_end_r1_reg_1;\n input bm_end_r1_reg_2;\n input bm_end_r1_reg_3;\n input \\ras_timer_r_reg[2]_0 ;\n input bm_end_r1_reg_4;\n input \\ras_timer_r_reg[2]_1 ;\n input \\ras_timer_r_reg[2]_2 ;\n input req_priority_r;\n input rd_wr_r_lcl_reg_0;\n input req_wr_r_lcl_reg;\n input col_wait_r_reg;\n input [0:0]\\grant_r_reg[1]_0 ;\n input req_wr_r_lcl_reg_0;\n input periodic_rd_ack_r_lcl_reg;\n input use_addr;\n input accept_internal_r_reg;\n input req_wr_r_lcl_reg_1;\n input pre_bm_end_r_reg_0;\n input [0:0]idle_r_lcl_reg_4;\n input [0:0]idle_r_lcl_reg_5;\n input [0:0]idle_r_lcl_reg_6;\n input periodic_rd_ack_r_lcl_reg_0;\n input periodic_rd_ack_r_lcl_reg_1;\n input act_wait_r_lcl_reg_0;\n input [0:0]\\grant_r_reg[1]_1 ;\n input bm_end_r1_reg_5;\n input rb_hit_busy_r_reg_0;\n input rb_hit_busy_r_reg_1;\n input accept_r_reg;\n input pre_passing_open_bank_r_reg_0;\n input \\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ;\n input pre_passing_open_bank_r_reg_1;\n input pre_bm_end_r_reg_1;\n input pre_bm_end_r_reg_2;\n input ras_timer_zero_r;\n input [2:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ;\n input [0:0]q_entry_ns;\n input idle_r_lcl_reg_7;\n input ordered_r_lcl_reg_1;\n input rstdiv0_sync_r1_reg_rep__21;\n input ordered_r_lcl_reg_2;\n\n wire CLK;\n wire [0:0]D;\n wire [0:0]E;\n wire [0:0]Q;\n wire [0:0]SR;\n wire accept_internal_r_reg;\n wire accept_r_reg;\n wire act_wait_ns;\n wire act_wait_r_lcl_reg;\n wire act_wait_r_lcl_reg_0;\n wire auto_pre_r_lcl_reg_0;\n wire bm_end_r1_reg;\n wire bm_end_r1_reg_0;\n wire bm_end_r1_reg_1;\n wire bm_end_r1_reg_2;\n wire bm_end_r1_reg_3;\n wire bm_end_r1_reg_4;\n wire bm_end_r1_reg_5;\n wire col_wait_r_reg;\n wire demand_priority_r_reg;\n wire \\grant_r_reg[1] ;\n wire [0:0]\\grant_r_reg[1]_0 ;\n wire [0:0]\\grant_r_reg[1]_1 ;\n wire head_r_lcl_reg_0;\n wire head_r_lcl_reg_1;\n wire idle_r_lcl_reg_0;\n wire idle_r_lcl_reg_1;\n wire idle_r_lcl_reg_2;\n wire idle_r_lcl_reg_3;\n wire [0:0]idle_r_lcl_reg_4;\n wire [0:0]idle_r_lcl_reg_5;\n wire [0:0]idle_r_lcl_reg_6;\n wire idle_r_lcl_reg_7;\n wire \\maintenance_request.maint_req_r_lcl_reg ;\n wire [1:0]order_q_r;\n wire \\order_q_r[0]_i_1__0_n_0 ;\n wire \\order_q_r[1]_i_1__0_n_0 ;\n wire [0:0]ordered_r;\n wire ordered_r_lcl_reg_0;\n wire ordered_r_lcl_reg_1;\n wire ordered_r_lcl_reg_2;\n wire p_106_out;\n wire pass_open_bank_ns;\n wire periodic_rd_ack_r_lcl_reg;\n wire periodic_rd_ack_r_lcl_reg_0;\n wire periodic_rd_ack_r_lcl_reg_1;\n wire pre_bm_end_ns;\n wire pre_bm_end_r_reg_0;\n wire pre_bm_end_r_reg_1;\n wire pre_bm_end_r_reg_2;\n wire pre_passing_open_bank_ns;\n wire pre_passing_open_bank_r;\n wire pre_passing_open_bank_r_reg_0;\n wire pre_passing_open_bank_r_reg_1;\n wire [0:0]q_entry_ns;\n wire [1:0]q_entry_r;\n wire \\q_entry_r[0]_i_1__0_n_0 ;\n wire \\q_entry_r[0]_i_2__1_n_0 ;\n wire \\q_entry_r[1]_i_1__0_n_0 ;\n wire \\q_entry_r_reg[0]_0 ;\n wire \\q_entry_r_reg[0]_1 ;\n wire \\q_entry_r_reg[1]_0 ;\n wire \\q_entry_r_reg[1]_1 ;\n wire \\q_entry_r_reg[1]_2 ;\n wire q_has_priority_4;\n wire q_has_priority_r_reg_0;\n wire q_has_rd_3;\n wire q_has_rd_r_reg_0;\n wire \\ras_timer_r[0]_i_2__1_n_0 ;\n wire \\ras_timer_r[1]_i_3_n_0 ;\n wire \\ras_timer_r[2]_i_2__1_n_0 ;\n wire \\ras_timer_r_reg[0] ;\n wire \\ras_timer_r_reg[0]_0 ;\n wire \\ras_timer_r_reg[0]_1 ;\n wire \\ras_timer_r_reg[1] ;\n wire \\ras_timer_r_reg[1]_0 ;\n wire \\ras_timer_r_reg[1]_1 ;\n wire [2:0]\\ras_timer_r_reg[2] ;\n wire \\ras_timer_r_reg[2]_0 ;\n wire \\ras_timer_r_reg[2]_1 ;\n wire \\ras_timer_r_reg[2]_2 ;\n wire ras_timer_zero_r;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ;\n wire [2:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;\n wire \\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ;\n wire [2:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;\n wire rb_hit_busy_r_reg;\n wire rb_hit_busy_r_reg_0;\n wire rb_hit_busy_r_reg_1;\n wire rd_wr_r_lcl_reg;\n wire rd_wr_r_lcl_reg_0;\n wire \\req_bank_r_lcl_reg[2] ;\n wire req_bank_rdy_ns;\n wire \\req_data_buf_addr_r_reg[4] ;\n wire req_priority_r;\n wire req_wr_r_lcl_reg;\n wire req_wr_r_lcl_reg_0;\n wire req_wr_r_lcl_reg_1;\n wire \\rp_timer.rp_timer_r_reg[1] ;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire set_order_q;\n wire tail_r_24;\n wire use_addr;\n wire wait_for_maint_r_18;\n wire wait_for_maint_r_lcl_reg_0;\n wire wait_for_maint_r_lcl_reg_1;\n\n LUT6 #(\n .INIT(64'hFFFFFFFF0404FF04)) \n act_wait_r_lcl_i_1__2\n (.I0(\\ras_timer_r_reg[0] ),\n .I1(act_wait_r_lcl_reg_0),\n .I2(\\grant_r_reg[1]_1 ),\n .I3(act_wait_r_lcl_reg),\n .I4(\\q_entry_r_reg[0]_0 ),\n .I5(bm_end_r1_reg_5),\n .O(act_wait_ns));\n LUT6 #(\n .INIT(64'h00000000F4F4FFF4)) \n act_wait_r_lcl_i_2__2\n (.I0(pre_passing_open_bank_r_reg_0),\n .I1(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 [0]),\n .I2(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ),\n .I3(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 [1]),\n .I4(pre_passing_open_bank_r_reg_1),\n .I5(\\ras_timer_r_reg[0]_1 ),\n .O(\\ras_timer_r_reg[0] ));\n FDRE auto_pre_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(auto_pre_r_lcl_reg_0),\n .Q(\\rp_timer.rp_timer_r_reg[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b1)) \n \\compute_tail.tail_r_lcl_reg \n (.C(CLK),\n .CE(1'b1),\n .D(idle_r_lcl_reg_0),\n .Q(tail_r_24),\n .R(SR));\n LUT6 #(\n .INIT(64'hE0E0E0EEE0EEE0EE)) \n demand_priority_r_i_3__0\n (.I0(req_priority_r),\n .I1(q_has_priority_4),\n .I2(rd_wr_r_lcl_reg_0),\n .I3(order_q_r[1]),\n .I4(order_q_r[0]),\n .I5(req_wr_r_lcl_reg),\n .O(demand_priority_r_reg));\n LUT5 #(\n .INIT(32'hFFDFFFFF)) \n \\grant_r[1]_i_4__1 \n (.I0(ras_timer_zero_r),\n .I1(\\req_data_buf_addr_r_reg[4] ),\n .I2(act_wait_r_lcl_reg_0),\n .I3(wait_for_maint_r_18),\n .I4(wait_for_maint_r_lcl_reg_0),\n .O(\\grant_r_reg[1] ));\n FDRE head_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(head_r_lcl_reg_1),\n .Q(wait_for_maint_r_lcl_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__0));\n LUT5 #(\n .INIT(32'h55151515)) \n i___36_i_1\n (.I0(pre_passing_open_bank_r),\n .I1(\\grant_r_reg[1]_0 ),\n .I2(act_wait_r_lcl_reg),\n .I3(rd_wr_r_lcl_reg_0),\n .I4(req_wr_r_lcl_reg_0),\n .O(\\ras_timer_r_reg[0]_0 ));\n LUT6 #(\n .INIT(64'h00000000FD555555)) \n i___40_i_1\n (.I0(\\req_data_buf_addr_r_reg[4] ),\n .I1(periodic_rd_ack_r_lcl_reg),\n .I2(use_addr),\n .I3(accept_internal_r_reg),\n .I4(wait_for_maint_r_lcl_reg_0),\n .I5(req_wr_r_lcl_reg_1),\n .O(rb_hit_busy_r_reg));\n (* SOFT_HLUTNM = \"soft_lutpair1067\" *) \n LUT3 #(\n .INIT(8'hFB)) \n i___56_i_1\n (.I0(\\req_data_buf_addr_r_reg[4] ),\n .I1(q_entry_r[0]),\n .I2(q_entry_r[1]),\n .O(\\ras_timer_r_reg[0]_1 ));\n LUT5 #(\n .INIT(32'h55151515)) \n i___5_i_1\n (.I0(bm_end_r1_reg),\n .I1(\\grant_r_reg[1]_0 ),\n .I2(act_wait_r_lcl_reg),\n .I3(rd_wr_r_lcl_reg_0),\n .I4(req_wr_r_lcl_reg_0),\n .O(\\q_entry_r_reg[0]_0 ));\n LUT6 #(\n .INIT(64'h00FF000014141414)) \n i___6_i_1\n (.I0(rb_hit_busy_r_reg_0),\n .I1(\\q_entry_r_reg[0]_1 ),\n .I2(rb_hit_busy_r_reg_1),\n .I3(q_entry_r[1]),\n .I4(q_entry_r[0]),\n .I5(accept_r_reg),\n .O(head_r_lcl_reg_0));\n LUT5 #(\n .INIT(32'hFFC5FFFF)) \n i___6_i_2\n (.I0(\\q_entry_r_reg[0]_1 ),\n .I1(periodic_rd_ack_r_lcl_reg_0),\n .I2(\\req_data_buf_addr_r_reg[4] ),\n .I3(periodic_rd_ack_r_lcl_reg_1),\n .I4(\\q_entry_r_reg[0]_0 ),\n .O(\\q_entry_r_reg[1]_1 ));\n LUT6 #(\n .INIT(64'hDD0DDD0D0000DD0D)) \n i___6_i_3\n (.I0(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 [1]),\n .I1(pre_bm_end_r_reg_1),\n .I2(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 [0]),\n .I3(pre_bm_end_r_reg_2),\n .I4(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 [2]),\n .I5(pre_bm_end_r_reg_0),\n .O(\\q_entry_r_reg[0]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair1068\" *) \n LUT1 #(\n .INIT(2'h1)) \n idle_r_lcl_i_1\n (.I0(rb_hit_busy_r_reg),\n .O(E));\n FDRE idle_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(E),\n .Q(\\req_data_buf_addr_r_reg[4] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h553100305531CC30)) \n \\order_q_r[0]_i_1__0 \n (.I0(ordered_r_lcl_reg_2),\n .I1(order_q_r[0]),\n .I2(order_q_r[1]),\n .I3(req_wr_r_lcl_reg),\n .I4(set_order_q),\n .I5(rstdiv0_sync_r1_reg_rep__21),\n .O(\\order_q_r[0]_i_1__0_n_0 ));\n LUT6 #(\n .INIT(64'hAAC200C0AAC2F0C0)) \n \\order_q_r[1]_i_1__0 \n (.I0(ordered_r_lcl_reg_1),\n .I1(order_q_r[0]),\n .I2(order_q_r[1]),\n .I3(req_wr_r_lcl_reg),\n .I4(set_order_q),\n .I5(rstdiv0_sync_r1_reg_rep__21),\n .O(\\order_q_r[1]_i_1__0_n_0 ));\n LUT6 #(\n .INIT(64'h8000800080000000)) \n \\order_q_r[1]_i_2__0 \n (.I0(req_wr_r_lcl_reg_0),\n .I1(\\req_data_buf_addr_r_reg[4] ),\n .I2(wait_for_maint_r_lcl_reg_0),\n .I3(accept_internal_r_reg),\n .I4(use_addr),\n .I5(periodic_rd_ack_r_lcl_reg),\n .O(set_order_q));\n FDRE \\order_q_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\order_q_r[0]_i_1__0_n_0 ),\n .Q(order_q_r[0]),\n .R(1'b0));\n FDRE \\order_q_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\order_q_r[1]_i_1__0_n_0 ),\n .Q(order_q_r[1]),\n .R(1'b0));\n FDRE ordered_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(ordered_r_lcl_reg_0),\n .Q(ordered_r),\n .R(1'b0));\n FDRE pass_open_bank_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pass_open_bank_ns),\n .Q(act_wait_r_lcl_reg),\n .R(1'b0));\n FDRE pre_bm_end_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pre_bm_end_ns),\n .Q(bm_end_r1_reg),\n .R(1'b0));\n FDRE pre_passing_open_bank_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pre_passing_open_bank_ns),\n .Q(pre_passing_open_bank_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h8BB8FFFF8BB80000)) \n \\q_entry_r[0]_i_1__0 \n (.I0(\\q_entry_r[0]_i_2__1_n_0 ),\n .I1(\\q_entry_r_reg[0]_0 ),\n .I2(idle_r_lcl_reg_7),\n .I3(periodic_rd_ack_r_lcl_reg_0),\n .I4(\\q_entry_r_reg[1]_1 ),\n .I5(q_entry_r[0]),\n .O(\\q_entry_r[0]_i_1__0_n_0 ));\n LUT4 #(\n .INIT(16'h909F)) \n \\q_entry_r[0]_i_2__1 \n (.I0(rb_hit_busy_r_reg_1),\n .I1(\\q_entry_r_reg[0]_1 ),\n .I2(periodic_rd_ack_r_lcl_reg_1),\n .I3(q_entry_r[0]),\n .O(\\q_entry_r[0]_i_2__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1067\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\q_entry_r[1]_i_1__0 \n (.I0(q_entry_ns),\n .I1(\\q_entry_r_reg[1]_1 ),\n .I2(q_entry_r[1]),\n .O(\\q_entry_r[1]_i_1__0_n_0 ));\n LUT6 #(\n .INIT(64'h8EE7E771E7717118)) \n \\q_entry_r[1]_i_2__1 \n (.I0(\\q_entry_r_reg[0]_0 ),\n .I1(pre_bm_end_r_reg_0),\n .I2(idle_r_lcl_reg_4),\n .I3(idle_r_lcl_reg_5),\n .I4(\\req_data_buf_addr_r_reg[4] ),\n .I5(idle_r_lcl_reg_6),\n .O(\\q_entry_r_reg[1]_0 ));\n LUT6 #(\n .INIT(64'hA9FFA900A900A9FF)) \n \\q_entry_r[1]_i_3__1 \n (.I0(rb_hit_busy_r_reg_0),\n .I1(\\q_entry_r_reg[0]_1 ),\n .I2(rb_hit_busy_r_reg_1),\n .I3(periodic_rd_ack_r_lcl_reg_1),\n .I4(q_entry_r[1]),\n .I5(q_entry_r[0]),\n .O(\\q_entry_r_reg[1]_2 ));\n FDSE \\q_entry_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\q_entry_r[0]_i_1__0_n_0 ),\n .Q(q_entry_r[0]),\n .S(SR));\n FDRE \\q_entry_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\q_entry_r[1]_i_1__0_n_0 ),\n .Q(q_entry_r[1]),\n .R(SR));\n FDRE q_has_priority_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(q_has_priority_r_reg_0),\n .Q(q_has_priority_4),\n .R(1'b0));\n FDRE q_has_rd_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(q_has_rd_r_reg_0),\n .Q(q_has_rd_3),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1066\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\ras_timer_r[0]_i_1__2 \n (.I0(\\ras_timer_r[0]_i_2__1_n_0 ),\n .I1(\\ras_timer_r_reg[0] ),\n .I2(\\ras_timer_r_reg[1] ),\n .O(\\ras_timer_r_reg[2] [0]));\n LUT6 #(\n .INIT(64'hB8BBB888B888B888)) \n \\ras_timer_r[0]_i_2__1 \n (.I0(\\ras_timer_r_reg[1]_0 ),\n .I1(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 [2]),\n .I2(rd_wr_r_lcl_reg),\n .I3(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 [1]),\n .I4(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 [0]),\n .I5(\\ras_timer_r_reg[1]_1 ),\n .O(\\ras_timer_r[0]_i_2__1_n_0 ));\n LUT3 #(\n .INIT(8'hC5)) \n \\ras_timer_r[1]_i_1__2 \n (.I0(bm_end_r1_reg_0),\n .I1(\\ras_timer_r[1]_i_3_n_0 ),\n .I2(\\ras_timer_r_reg[0] ),\n .O(\\ras_timer_r_reg[2] [1]));\n LUT6 #(\n .INIT(64'hBBBBB8888888B888)) \n \\ras_timer_r[1]_i_3 \n (.I0(bm_end_r1_reg_1),\n .I1(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 [2]),\n .I2(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 [0]),\n .I3(bm_end_r1_reg_2),\n .I4(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 [1]),\n .I5(bm_end_r1_reg_3),\n .O(\\ras_timer_r[1]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1066\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\ras_timer_r[2]_i_1__2 \n (.I0(\\ras_timer_r[2]_i_2__1_n_0 ),\n .I1(\\ras_timer_r_reg[0] ),\n .I2(\\ras_timer_r_reg[2]_0 ),\n .O(\\ras_timer_r_reg[2] [2]));\n LUT6 #(\n .INIT(64'hBBBBB8888888B888)) \n \\ras_timer_r[2]_i_2__1 \n (.I0(bm_end_r1_reg_4),\n .I1(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 [2]),\n .I2(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 [0]),\n .I3(\\ras_timer_r_reg[2]_1 ),\n .I4(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 [1]),\n .I5(\\ras_timer_r_reg[2]_2 ),\n .O(\\ras_timer_r[2]_i_2__1_n_0 ));\n LUT6 #(\n .INIT(64'h00000000F2020000)) \n \\rb_hit_busies.rb_hit_busies_r_lcl[1]_i_1 \n (.I0(rb_hit_busy_r_reg),\n .I1(\\req_bank_r_lcl_reg[2] ),\n .I2(idle_r_lcl_reg_1),\n .I3(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ),\n .I4(\\q_entry_r_reg[0]_0 ),\n .I5(rstdiv0_sync_r1_reg_rep__20),\n .O(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] ));\n LUT6 #(\n .INIT(64'h00000000F2020000)) \n \\rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1 \n (.I0(rb_hit_busy_r_reg),\n .I1(\\req_bank_r_lcl_reg[2] ),\n .I2(idle_r_lcl_reg_2),\n .I3(Q),\n .I4(\\q_entry_r_reg[0]_0 ),\n .I5(rstdiv0_sync_r1_reg_rep__20),\n .O(D));\n LUT6 #(\n .INIT(64'h00000000F2020000)) \n \\rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1__0 \n (.I0(rb_hit_busy_r_reg),\n .I1(\\req_bank_r_lcl_reg[2] ),\n .I2(idle_r_lcl_reg_3),\n .I3(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),\n .I4(\\q_entry_r_reg[0]_0 ),\n .I5(rstdiv0_sync_r1_reg_rep__20),\n .O(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ));\n FDRE #(\n .INIT(1'b0)) \n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 [0]),\n .Q(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 [1]),\n .Q(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 [2]),\n .Q(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 [2]),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1068\" *) \n LUT2 #(\n .INIT(4'h2)) \n rb_hit_busy_r_i_1\n (.I0(rb_hit_busy_r_reg),\n .I1(\\req_bank_r_lcl_reg[2] ),\n .O(p_106_out));\n LUT5 #(\n .INIT(32'h888A8A8A)) \n req_bank_rdy_r_i_1__1\n (.I0(col_wait_r_reg),\n .I1(rd_wr_r_lcl_reg_0),\n .I2(order_q_r[1]),\n .I3(order_q_r[0]),\n .I4(req_wr_r_lcl_reg),\n .O(req_bank_rdy_ns));\n FDRE wait_for_maint_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wait_for_maint_r_lcl_reg_1),\n .Q(wait_for_maint_r_18),\n .R(\\maintenance_request.maint_req_r_lcl_reg ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_bank_queue\" *) \nmodule ddr3_if_mig_7series_v4_0_bank_queue__parameterized1\n (\\req_data_buf_addr_r_reg[4] ,\n E,\n act_wait_r_lcl_reg,\n pre_bm_end_r_9,\n pre_passing_open_bank_r,\n q_has_rd_10,\n q_has_priority_11,\n wait_for_maint_r_19,\n tail_r_26,\n wait_for_maint_r_lcl_reg_0,\n \\rp_timer.rp_timer_r_reg[1] ,\n ordered_r,\n D,\n rb_hit_busy_r_reg,\n \\q_entry_r_reg[1]_0 ,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ,\n \\grant_r_reg[2] ,\n \\ras_timer_r_reg[2] ,\n \\ras_timer_r_reg[0] ,\n order_q_r,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ,\n act_wait_ns,\n \\q_entry_r_reg[1]_1 ,\n \\q_entry_r_reg[1]_2 ,\n \\q_entry_r_reg[0]_0 ,\n head_r_lcl_reg_0,\n \\q_entry_r_reg[1]_3 ,\n p_67_out,\n \\compute_tail.tail_r_lcl_reg_0 ,\n \\ras_timer_r_reg[0]_0 ,\n granted_row_ns,\n granted_row_r_reg,\n CLK,\n pass_open_bank_ns,\n pre_bm_end_ns,\n pre_passing_open_bank_ns,\n q_has_rd_r_reg_0,\n q_has_priority_r_reg_0,\n \\maintenance_request.maint_req_r_lcl_reg ,\n wait_for_maint_r_lcl_reg_1,\n SR,\n idle_r_lcl_reg_0,\n rstdiv0_sync_r1_reg_rep__0,\n head_r_lcl_reg_1,\n auto_pre_r_lcl_reg_0,\n ordered_r_lcl_reg_0,\n \\req_bank_r_lcl_reg[2] ,\n idle_r_lcl_reg_1,\n Q,\n rstdiv0_sync_r1_reg_rep__20,\n idle_r_lcl_reg_2,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ,\n idle_r_lcl_reg_3,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 ,\n \\rtw_timer.rtw_cnt_r_reg[1] ,\n \\wtr_timer.wtr_cnt_r_reg[1] ,\n rd_wr_r_lcl_reg,\n override_demand_r_reg,\n col_wait_r_reg,\n \\ras_timer_r_reg[1] ,\n bm_end_r1_reg,\n \\ras_timer_r_reg[2]_0 ,\n rd_wr_r_lcl_reg_0,\n req_wr_r_lcl_reg,\n rnk_config_valid_r_lcl_reg,\n \\ras_timer_r_reg[1]_0 ,\n \\ras_timer_r_reg[1]_1 ,\n rd_wr_r_lcl_reg_1,\n bm_end_r1_reg_0,\n bm_end_r1_reg_1,\n bm_end_r1_reg_2,\n \\ras_timer_r_reg[2]_1 ,\n bm_end_r1_reg_3,\n \\ras_timer_r_reg[2]_2 ,\n act_wait_r_lcl_reg_0,\n \\grant_r_reg[2]_0 ,\n bm_end_r1_reg_4,\n pre_passing_open_bank_r_reg_0,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ,\n pre_passing_open_bank_r_reg_1,\n idle_r_lcl_reg_4,\n rb_hit_busy_r_reg_0,\n rb_hit_busy_r_reg_1,\n periodic_rd_ack_r_lcl_reg,\n accept_r_reg,\n periodic_rd_ack_r_lcl_reg_0,\n pre_bm_end_r_reg_0,\n pre_bm_end_r_reg_1,\n pre_bm_end_r_reg_2,\n periodic_rd_ack_r_lcl_reg_1,\n use_addr,\n accept_internal_r_reg,\n req_wr_r_lcl_reg_0,\n req_wr_r_lcl_reg_1,\n \\grant_r_reg[2]_1 ,\n \\grant_r_reg[1] ,\n ras_timer_zero_r_reg,\n \\grant_r_reg[3] ,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ,\n idle_r_lcl_reg_5,\n \\q_entry_r_reg[1]_4 ,\n idle_r_lcl_reg_6,\n ordered_r_lcl_reg_1,\n req_wr_r_lcl_reg_2,\n rstdiv0_sync_r1_reg_rep__21,\n ordered_r_lcl_reg_2);\n output \\req_data_buf_addr_r_reg[4] ;\n output [0:0]E;\n output act_wait_r_lcl_reg;\n output pre_bm_end_r_9;\n output pre_passing_open_bank_r;\n output q_has_rd_10;\n output q_has_priority_11;\n output wait_for_maint_r_19;\n output tail_r_26;\n output wait_for_maint_r_lcl_reg_0;\n output \\rp_timer.rp_timer_r_reg[1] ;\n output [0:0]ordered_r;\n output [0:0]D;\n output rb_hit_busy_r_reg;\n output \\q_entry_r_reg[1]_0 ;\n output [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ;\n output [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ;\n output \\grant_r_reg[2] ;\n output [2:0]\\ras_timer_r_reg[2] ;\n output \\ras_timer_r_reg[0] ;\n output [1:0]order_q_r;\n output [2:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;\n output act_wait_ns;\n output \\q_entry_r_reg[1]_1 ;\n output \\q_entry_r_reg[1]_2 ;\n output \\q_entry_r_reg[0]_0 ;\n output head_r_lcl_reg_0;\n output \\q_entry_r_reg[1]_3 ;\n output p_67_out;\n output \\compute_tail.tail_r_lcl_reg_0 ;\n output \\ras_timer_r_reg[0]_0 ;\n output granted_row_ns;\n output granted_row_r_reg;\n input CLK;\n input pass_open_bank_ns;\n input pre_bm_end_ns;\n input pre_passing_open_bank_ns;\n input q_has_rd_r_reg_0;\n input q_has_priority_r_reg_0;\n input \\maintenance_request.maint_req_r_lcl_reg ;\n input wait_for_maint_r_lcl_reg_1;\n input [0:0]SR;\n input idle_r_lcl_reg_0;\n input rstdiv0_sync_r1_reg_rep__0;\n input head_r_lcl_reg_1;\n input auto_pre_r_lcl_reg_0;\n input ordered_r_lcl_reg_0;\n input \\req_bank_r_lcl_reg[2] ;\n input idle_r_lcl_reg_1;\n input [0:0]Q;\n input rstdiv0_sync_r1_reg_rep__20;\n input idle_r_lcl_reg_2;\n input [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ;\n input idle_r_lcl_reg_3;\n input [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 ;\n input \\rtw_timer.rtw_cnt_r_reg[1] ;\n input \\wtr_timer.wtr_cnt_r_reg[1] ;\n input rd_wr_r_lcl_reg;\n input override_demand_r_reg;\n input col_wait_r_reg;\n input \\ras_timer_r_reg[1] ;\n input bm_end_r1_reg;\n input \\ras_timer_r_reg[2]_0 ;\n input rd_wr_r_lcl_reg_0;\n input req_wr_r_lcl_reg;\n input rnk_config_valid_r_lcl_reg;\n input \\ras_timer_r_reg[1]_0 ;\n input \\ras_timer_r_reg[1]_1 ;\n input rd_wr_r_lcl_reg_1;\n input bm_end_r1_reg_0;\n input bm_end_r1_reg_1;\n input bm_end_r1_reg_2;\n input \\ras_timer_r_reg[2]_1 ;\n input bm_end_r1_reg_3;\n input \\ras_timer_r_reg[2]_2 ;\n input act_wait_r_lcl_reg_0;\n input [0:0]\\grant_r_reg[2]_0 ;\n input bm_end_r1_reg_4;\n input pre_passing_open_bank_r_reg_0;\n input \\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;\n input pre_passing_open_bank_r_reg_1;\n input idle_r_lcl_reg_4;\n input rb_hit_busy_r_reg_0;\n input rb_hit_busy_r_reg_1;\n input periodic_rd_ack_r_lcl_reg;\n input accept_r_reg;\n input periodic_rd_ack_r_lcl_reg_0;\n input pre_bm_end_r_reg_0;\n input pre_bm_end_r_reg_1;\n input pre_bm_end_r_reg_2;\n input periodic_rd_ack_r_lcl_reg_1;\n input use_addr;\n input accept_internal_r_reg;\n input req_wr_r_lcl_reg_0;\n input req_wr_r_lcl_reg_1;\n input [0:0]\\grant_r_reg[2]_1 ;\n input \\grant_r_reg[1] ;\n input ras_timer_zero_r_reg;\n input \\grant_r_reg[3] ;\n input [2:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ;\n input idle_r_lcl_reg_5;\n input \\q_entry_r_reg[1]_4 ;\n input idle_r_lcl_reg_6;\n input ordered_r_lcl_reg_1;\n input req_wr_r_lcl_reg_2;\n input rstdiv0_sync_r1_reg_rep__21;\n input ordered_r_lcl_reg_2;\n\n wire CLK;\n wire [0:0]D;\n wire [0:0]E;\n wire [0:0]Q;\n wire [0:0]SR;\n wire accept_internal_r_reg;\n wire accept_r_reg;\n wire act_wait_ns;\n wire act_wait_r_lcl_reg;\n wire act_wait_r_lcl_reg_0;\n wire auto_pre_r_lcl_reg_0;\n wire bm_end_r1_reg;\n wire bm_end_r1_reg_0;\n wire bm_end_r1_reg_1;\n wire bm_end_r1_reg_2;\n wire bm_end_r1_reg_3;\n wire bm_end_r1_reg_4;\n wire col_wait_r_reg;\n wire \\compute_tail.tail_r_lcl_reg_0 ;\n wire \\grant_r[3]_i_9_n_0 ;\n wire \\grant_r_reg[1] ;\n wire \\grant_r_reg[2] ;\n wire [0:0]\\grant_r_reg[2]_0 ;\n wire [0:0]\\grant_r_reg[2]_1 ;\n wire \\grant_r_reg[3] ;\n wire granted_row_ns;\n wire granted_row_r_reg;\n wire head_r_lcl_reg_0;\n wire head_r_lcl_reg_1;\n wire i___10_i_4_n_0;\n wire i___10_i_5_n_0;\n wire idle_r_lcl_reg_0;\n wire idle_r_lcl_reg_1;\n wire idle_r_lcl_reg_2;\n wire idle_r_lcl_reg_3;\n wire idle_r_lcl_reg_4;\n wire idle_r_lcl_reg_5;\n wire idle_r_lcl_reg_6;\n wire \\maintenance_request.maint_req_r_lcl_reg ;\n wire [1:0]order_q_r;\n wire \\order_q_r[0]_i_1__1_n_0 ;\n wire \\order_q_r[1]_i_1__1_n_0 ;\n wire [0:0]ordered_r;\n wire ordered_r_lcl_reg_0;\n wire ordered_r_lcl_reg_1;\n wire ordered_r_lcl_reg_2;\n wire override_demand_r_reg;\n wire p_67_out;\n wire pass_open_bank_ns;\n wire periodic_rd_ack_r_lcl_reg;\n wire periodic_rd_ack_r_lcl_reg_0;\n wire periodic_rd_ack_r_lcl_reg_1;\n wire pre_bm_end_ns;\n wire pre_bm_end_r_9;\n wire pre_bm_end_r_reg_0;\n wire pre_bm_end_r_reg_1;\n wire pre_bm_end_r_reg_2;\n wire pre_passing_open_bank_ns;\n wire pre_passing_open_bank_r;\n wire pre_passing_open_bank_r_reg_0;\n wire pre_passing_open_bank_r_reg_1;\n wire \\q_entry_r[0]_i_1__1_n_0 ;\n wire \\q_entry_r[0]_i_2_n_0 ;\n wire \\q_entry_r[1]_i_1__1_n_0 ;\n wire \\q_entry_r_reg[0]_0 ;\n wire \\q_entry_r_reg[1]_0 ;\n wire \\q_entry_r_reg[1]_1 ;\n wire \\q_entry_r_reg[1]_2 ;\n wire \\q_entry_r_reg[1]_3 ;\n wire \\q_entry_r_reg[1]_4 ;\n wire q_has_priority_11;\n wire q_has_priority_r_reg_0;\n wire q_has_rd_10;\n wire q_has_rd_r_reg_0;\n wire \\ras_timer_r[0]_i_2__2_n_0 ;\n wire \\ras_timer_r[1]_i_2__1_n_0 ;\n wire \\ras_timer_r[2]_i_2__2_n_0 ;\n wire \\ras_timer_r_reg[0] ;\n wire \\ras_timer_r_reg[0]_0 ;\n wire \\ras_timer_r_reg[1] ;\n wire \\ras_timer_r_reg[1]_0 ;\n wire \\ras_timer_r_reg[1]_1 ;\n wire [2:0]\\ras_timer_r_reg[2] ;\n wire \\ras_timer_r_reg[2]_0 ;\n wire \\ras_timer_r_reg[2]_1 ;\n wire \\ras_timer_r_reg[2]_2 ;\n wire ras_timer_zero_r_reg;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 ;\n wire \\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;\n wire [2:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;\n wire [2:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ;\n wire rb_hit_busy_r_reg;\n wire rb_hit_busy_r_reg_0;\n wire rb_hit_busy_r_reg_1;\n wire rd_wr_r_lcl_reg;\n wire rd_wr_r_lcl_reg_0;\n wire rd_wr_r_lcl_reg_1;\n wire \\req_bank_r_lcl_reg[2] ;\n wire \\req_data_buf_addr_r_reg[4] ;\n wire req_wr_r_lcl_reg;\n wire req_wr_r_lcl_reg_0;\n wire req_wr_r_lcl_reg_1;\n wire req_wr_r_lcl_reg_2;\n wire rnk_config_valid_r_lcl_reg;\n wire \\rp_timer.rp_timer_r_reg[1] ;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire \\rtw_timer.rtw_cnt_r_reg[1] ;\n wire set_order_q;\n wire tail_r_26;\n wire use_addr;\n wire wait_for_maint_r_19;\n wire wait_for_maint_r_lcl_reg_0;\n wire wait_for_maint_r_lcl_reg_1;\n wire \\wtr_timer.wtr_cnt_r_reg[1] ;\n\n LUT6 #(\n .INIT(64'hFFFFFFFF0404FF04)) \n act_wait_r_lcl_i_1\n (.I0(\\ras_timer_r_reg[0] ),\n .I1(act_wait_r_lcl_reg_0),\n .I2(\\grant_r_reg[2]_0 ),\n .I3(act_wait_r_lcl_reg),\n .I4(\\q_entry_r_reg[1]_0 ),\n .I5(bm_end_r1_reg_4),\n .O(act_wait_ns));\n LUT6 #(\n .INIT(64'h00000000F4F4FFF4)) \n act_wait_r_lcl_i_2\n (.I0(pre_passing_open_bank_r_reg_0),\n .I1(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [1]),\n .I2(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ),\n .I3(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [2]),\n .I4(pre_passing_open_bank_r_reg_1),\n .I5(idle_r_lcl_reg_4),\n .O(\\ras_timer_r_reg[0] ));\n LUT5 #(\n .INIT(32'h55151515)) \n act_wait_r_lcl_i_4__0\n (.I0(pre_passing_open_bank_r),\n .I1(\\grant_r_reg[2]_1 ),\n .I2(act_wait_r_lcl_reg),\n .I3(rd_wr_r_lcl_reg),\n .I4(req_wr_r_lcl_reg_1),\n .O(\\ras_timer_r_reg[0]_0 ));\n FDRE auto_pre_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(auto_pre_r_lcl_reg_0),\n .Q(\\rp_timer.rp_timer_r_reg[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b1)) \n \\compute_tail.tail_r_lcl_reg \n (.C(CLK),\n .CE(1'b1),\n .D(idle_r_lcl_reg_0),\n .Q(tail_r_26),\n .R(SR));\n LUT2 #(\n .INIT(4'hB)) \n \\grant_r[1]_i_2__0 \n (.I0(ras_timer_zero_r_reg),\n .I1(\\grant_r_reg[3] ),\n .O(granted_row_r_reg));\n LUT6 #(\n .INIT(64'h00000000000000CA)) \n \\grant_r[3]_i_2 \n (.I0(\\rtw_timer.rtw_cnt_r_reg[1] ),\n .I1(\\wtr_timer.wtr_cnt_r_reg[1] ),\n .I2(rd_wr_r_lcl_reg),\n .I3(\\grant_r[3]_i_9_n_0 ),\n .I4(override_demand_r_reg),\n .I5(col_wait_r_reg),\n .O(\\grant_r_reg[2] ));\n LUT6 #(\n .INIT(64'hFFFFFFFF44544444)) \n \\grant_r[3]_i_9 \n (.I0(rd_wr_r_lcl_reg),\n .I1(order_q_r[1]),\n .I2(order_q_r[0]),\n .I3(rd_wr_r_lcl_reg_0),\n .I4(req_wr_r_lcl_reg),\n .I5(rnk_config_valid_r_lcl_reg),\n .O(\\grant_r[3]_i_9_n_0 ));\n LUT2 #(\n .INIT(4'hB)) \n granted_row_r_i_1\n (.I0(granted_row_r_reg),\n .I1(\\grant_r_reg[1] ),\n .O(granted_row_ns));\n FDRE head_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(head_r_lcl_reg_1),\n .Q(wait_for_maint_r_lcl_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__0));\n LUT6 #(\n .INIT(64'hAA02AA32AA02AACE)) \n i___10_i_1\n (.I0(i___10_i_4_n_0),\n .I1(i___10_i_5_n_0),\n .I2(\\req_data_buf_addr_r_reg[4] ),\n .I3(accept_r_reg),\n .I4(rb_hit_busy_r_reg_0),\n .I5(rb_hit_busy_r_reg_1),\n .O(head_r_lcl_reg_0));\n LUT5 #(\n .INIT(32'hFFC5FFFF)) \n i___10_i_3\n (.I0(i___10_i_5_n_0),\n .I1(periodic_rd_ack_r_lcl_reg_0),\n .I2(\\req_data_buf_addr_r_reg[4] ),\n .I3(periodic_rd_ack_r_lcl_reg),\n .I4(\\q_entry_r_reg[1]_0 ),\n .O(\\q_entry_r_reg[1]_3 ));\n LUT2 #(\n .INIT(4'h2)) \n i___10_i_4\n (.I0(\\q_entry_r_reg[0]_0 ),\n .I1(\\q_entry_r_reg[1]_2 ),\n .O(i___10_i_4_n_0));\n LUT6 #(\n .INIT(64'hDD0DDD0D0000DD0D)) \n i___10_i_5\n (.I0(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [2]),\n .I1(pre_bm_end_r_reg_0),\n .I2(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [1]),\n .I3(pre_bm_end_r_reg_1),\n .I4(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [0]),\n .I5(pre_bm_end_r_reg_2),\n .O(i___10_i_5_n_0));\n LUT6 #(\n .INIT(64'h00000000FD555555)) \n i___50_i_1\n (.I0(\\req_data_buf_addr_r_reg[4] ),\n .I1(periodic_rd_ack_r_lcl_reg_1),\n .I2(use_addr),\n .I3(accept_internal_r_reg),\n .I4(wait_for_maint_r_lcl_reg_0),\n .I5(req_wr_r_lcl_reg_0),\n .O(rb_hit_busy_r_reg));\n LUT3 #(\n .INIT(8'h80)) \n i___5_i_3\n (.I0(\\q_entry_r_reg[1]_0 ),\n .I1(pre_bm_end_r_reg_1),\n .I2(pre_bm_end_r_reg_2),\n .O(\\compute_tail.tail_r_lcl_reg_0 ));\n LUT5 #(\n .INIT(32'h55151515)) \n i___9_i_1\n (.I0(pre_bm_end_r_9),\n .I1(\\grant_r_reg[2]_1 ),\n .I2(act_wait_r_lcl_reg),\n .I3(rd_wr_r_lcl_reg),\n .I4(req_wr_r_lcl_reg_1),\n .O(\\q_entry_r_reg[1]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1080\" *) \n LUT1 #(\n .INIT(2'h1)) \n idle_r_lcl_i_1__0\n (.I0(rb_hit_busy_r_reg),\n .O(E));\n FDRE idle_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(E),\n .Q(\\req_data_buf_addr_r_reg[4] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h553100305531CC30)) \n \\order_q_r[0]_i_1__1 \n (.I0(ordered_r_lcl_reg_2),\n .I1(order_q_r[0]),\n .I2(order_q_r[1]),\n .I3(req_wr_r_lcl_reg_2),\n .I4(set_order_q),\n .I5(rstdiv0_sync_r1_reg_rep__21),\n .O(\\order_q_r[0]_i_1__1_n_0 ));\n LUT6 #(\n .INIT(64'hAAC200C0AAC2F0C0)) \n \\order_q_r[1]_i_1__1 \n (.I0(ordered_r_lcl_reg_1),\n .I1(order_q_r[0]),\n .I2(order_q_r[1]),\n .I3(req_wr_r_lcl_reg_2),\n .I4(set_order_q),\n .I5(rstdiv0_sync_r1_reg_rep__21),\n .O(\\order_q_r[1]_i_1__1_n_0 ));\n LUT6 #(\n .INIT(64'h8000800080000000)) \n \\order_q_r[1]_i_2__1 \n (.I0(req_wr_r_lcl_reg_1),\n .I1(\\req_data_buf_addr_r_reg[4] ),\n .I2(wait_for_maint_r_lcl_reg_0),\n .I3(accept_internal_r_reg),\n .I4(use_addr),\n .I5(periodic_rd_ack_r_lcl_reg_1),\n .O(set_order_q));\n FDRE \\order_q_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\order_q_r[0]_i_1__1_n_0 ),\n .Q(order_q_r[0]),\n .R(1'b0));\n FDRE \\order_q_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\order_q_r[1]_i_1__1_n_0 ),\n .Q(order_q_r[1]),\n .R(1'b0));\n FDRE ordered_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(ordered_r_lcl_reg_0),\n .Q(ordered_r),\n .R(1'b0));\n FDRE pass_open_bank_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pass_open_bank_ns),\n .Q(act_wait_r_lcl_reg),\n .R(1'b0));\n FDRE pre_bm_end_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pre_bm_end_ns),\n .Q(pre_bm_end_r_9),\n .R(1'b0));\n FDRE pre_passing_open_bank_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pre_passing_open_bank_ns),\n .Q(pre_passing_open_bank_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hF704FFFFF7040000)) \n \\q_entry_r[0]_i_1__1 \n (.I0(periodic_rd_ack_r_lcl_reg_0),\n .I1(idle_r_lcl_reg_6),\n .I2(\\q_entry_r_reg[1]_0 ),\n .I3(\\q_entry_r[0]_i_2_n_0 ),\n .I4(\\q_entry_r_reg[1]_3 ),\n .I5(\\q_entry_r_reg[0]_0 ),\n .O(\\q_entry_r[0]_i_1__1_n_0 ));\n LUT6 #(\n .INIT(64'h99FF0FFF99000F00)) \n \\q_entry_r[0]_i_2 \n (.I0(rb_hit_busy_r_reg_1),\n .I1(i___10_i_5_n_0),\n .I2(\\q_entry_r_reg[0]_0 ),\n .I3(\\q_entry_r_reg[1]_0 ),\n .I4(periodic_rd_ack_r_lcl_reg),\n .I5(periodic_rd_ack_r_lcl_reg_0),\n .O(\\q_entry_r[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFB08FFFFFB080000)) \n \\q_entry_r[1]_i_1__1 \n (.I0(idle_r_lcl_reg_5),\n .I1(periodic_rd_ack_r_lcl_reg_0),\n .I2(\\q_entry_r_reg[1]_0 ),\n .I3(\\q_entry_r_reg[1]_4 ),\n .I4(\\q_entry_r_reg[1]_3 ),\n .I5(\\q_entry_r_reg[1]_2 ),\n .O(\\q_entry_r[1]_i_1__1_n_0 ));\n LUT6 #(\n .INIT(64'h560056FF56FF5600)) \n \\q_entry_r[1]_i_4 \n (.I0(rb_hit_busy_r_reg_0),\n .I1(i___10_i_5_n_0),\n .I2(rb_hit_busy_r_reg_1),\n .I3(periodic_rd_ack_r_lcl_reg),\n .I4(\\q_entry_r_reg[1]_2 ),\n .I5(\\q_entry_r_reg[0]_0 ),\n .O(\\q_entry_r_reg[1]_1 ));\n FDRE \\q_entry_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\q_entry_r[0]_i_1__1_n_0 ),\n .Q(\\q_entry_r_reg[0]_0 ),\n .R(SR));\n FDSE \\q_entry_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\q_entry_r[1]_i_1__1_n_0 ),\n .Q(\\q_entry_r_reg[1]_2 ),\n .S(SR));\n FDRE q_has_priority_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(q_has_priority_r_reg_0),\n .Q(q_has_priority_11),\n .R(1'b0));\n FDRE q_has_rd_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(q_has_rd_r_reg_0),\n .Q(q_has_rd_10),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1079\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\ras_timer_r[0]_i_1__1 \n (.I0(\\ras_timer_r[0]_i_2__2_n_0 ),\n .I1(\\ras_timer_r_reg[0] ),\n .I2(\\ras_timer_r_reg[1] ),\n .O(\\ras_timer_r_reg[2] [0]));\n LUT6 #(\n .INIT(64'hB8BBB888B888B888)) \n \\ras_timer_r[0]_i_2__2 \n (.I0(\\ras_timer_r_reg[1]_0 ),\n .I1(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [2]),\n .I2(\\ras_timer_r_reg[1]_1 ),\n .I3(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [1]),\n .I4(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [0]),\n .I5(rd_wr_r_lcl_reg_1),\n .O(\\ras_timer_r[0]_i_2__2_n_0 ));\n LUT3 #(\n .INIT(8'hB8)) \n \\ras_timer_r[1]_i_1 \n (.I0(\\ras_timer_r[1]_i_2__1_n_0 ),\n .I1(\\ras_timer_r_reg[0] ),\n .I2(bm_end_r1_reg),\n .O(\\ras_timer_r_reg[2] [1]));\n LUT6 #(\n .INIT(64'h0000B888FFFFB888)) \n \\ras_timer_r[1]_i_2__1 \n (.I0(bm_end_r1_reg_0),\n .I1(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [1]),\n .I2(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [0]),\n .I3(bm_end_r1_reg_1),\n .I4(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [2]),\n .I5(bm_end_r1_reg_2),\n .O(\\ras_timer_r[1]_i_2__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1079\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\ras_timer_r[2]_i_1 \n (.I0(\\ras_timer_r[2]_i_2__2_n_0 ),\n .I1(\\ras_timer_r_reg[0] ),\n .I2(\\ras_timer_r_reg[2]_0 ),\n .O(\\ras_timer_r_reg[2] [2]));\n LUT6 #(\n .INIT(64'hB8B8BB88B8B88888)) \n \\ras_timer_r[2]_i_2__2 \n (.I0(\\ras_timer_r_reg[2]_1 ),\n .I1(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [2]),\n .I2(bm_end_r1_reg_3),\n .I3(\\ras_timer_r_reg[2]_2 ),\n .I4(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [1]),\n .I5(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [0]),\n .O(\\ras_timer_r[2]_i_2__2_n_0 ));\n LUT6 #(\n .INIT(64'h00000000F2020000)) \n \\rb_hit_busies.rb_hit_busies_r_lcl[2]_i_1 \n (.I0(rb_hit_busy_r_reg),\n .I1(\\req_bank_r_lcl_reg[2] ),\n .I2(idle_r_lcl_reg_2),\n .I3(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ),\n .I4(\\q_entry_r_reg[1]_0 ),\n .I5(rstdiv0_sync_r1_reg_rep__20),\n .O(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ));\n LUT6 #(\n .INIT(64'h00000000F2020000)) \n \\rb_hit_busies.rb_hit_busies_r_lcl[2]_i_1__0 \n (.I0(rb_hit_busy_r_reg),\n .I1(\\req_bank_r_lcl_reg[2] ),\n .I2(idle_r_lcl_reg_3),\n .I3(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 ),\n .I4(\\q_entry_r_reg[1]_0 ),\n .I5(rstdiv0_sync_r1_reg_rep__20),\n .O(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ));\n LUT6 #(\n .INIT(64'h00000000F2020000)) \n \\rb_hit_busies.rb_hit_busies_r_lcl[6]_i_1 \n (.I0(rb_hit_busy_r_reg),\n .I1(\\req_bank_r_lcl_reg[2] ),\n .I2(idle_r_lcl_reg_1),\n .I3(Q),\n .I4(\\q_entry_r_reg[1]_0 ),\n .I5(rstdiv0_sync_r1_reg_rep__20),\n .O(D));\n FDRE #(\n .INIT(1'b0)) \n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 [0]),\n .Q(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 [1]),\n .Q(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 [2]),\n .Q(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 [2]),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1080\" *) \n LUT2 #(\n .INIT(4'h2)) \n rb_hit_busy_r_i_1__0\n (.I0(rb_hit_busy_r_reg),\n .I1(\\req_bank_r_lcl_reg[2] ),\n .O(p_67_out));\n FDRE wait_for_maint_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wait_for_maint_r_lcl_reg_1),\n .Q(wait_for_maint_r_19),\n .R(\\maintenance_request.maint_req_r_lcl_reg ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_bank_queue\" *) \nmodule ddr3_if_mig_7series_v4_0_bank_queue__parameterized2\n (\\req_data_buf_addr_r_reg[4] ,\n E,\n act_wait_r_lcl_reg,\n pre_bm_end_r_15,\n pre_passing_open_bank_r,\n q_has_rd_16,\n q_has_priority_17,\n wait_for_maint_r_20,\n tail_r_28,\n wait_for_maint_r_lcl_reg_0,\n \\rp_timer.rp_timer_r_reg[1] ,\n ordered_r,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ,\n rb_hit_busy_r_reg,\n \\q_entry_r_reg[1]_0 ,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ,\n D,\n \\ras_timer_r_reg[0] ,\n Q,\n demand_priority_r_reg,\n order_q_r,\n req_bank_rdy_ns,\n act_wait_ns,\n \\q_entry_r_reg[1]_1 ,\n \\q_entry_r_reg[0]_0 ,\n head_r_lcl_reg_0,\n \\q_entry_r_reg[1]_2 ,\n p_28_out,\n \\ras_timer_r_reg[0]_0 ,\n \\grant_r_reg[3] ,\n CLK,\n pass_open_bank_ns,\n pre_bm_end_ns,\n pre_passing_open_bank_ns,\n q_has_rd_r_reg_0,\n q_has_priority_r_reg_0,\n \\maintenance_request.maint_req_r_lcl_reg ,\n wait_for_maint_r_lcl_reg_1,\n SR,\n idle_r_lcl_reg_0,\n rstdiv0_sync_r1_reg_rep__0,\n head_r_lcl_reg_1,\n auto_pre_r_lcl_reg_0,\n ordered_r_lcl_reg_0,\n \\req_bank_r_lcl_reg[0] ,\n idle_r_lcl_reg_1,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ,\n rstdiv0_sync_r1_reg_rep__20,\n idle_r_lcl_reg_2,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 ,\n idle_r_lcl_reg_3,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4 ,\n rd_wr_r_lcl_reg,\n \\ras_timer_r_reg[1] ,\n \\ras_timer_r_reg[1]_0 ,\n \\ras_timer_r_reg[1]_1 ,\n bm_end_r1_reg,\n bm_end_r1_reg_0,\n bm_end_r1_reg_1,\n bm_end_r1_reg_2,\n \\ras_timer_r_reg[2] ,\n \\ras_timer_r_reg[2]_0 ,\n \\ras_timer_r_reg[2]_1 ,\n bm_end_r1_reg_3,\n req_priority_r,\n rd_wr_r_lcl_reg_0,\n req_wr_r_lcl_reg,\n col_wait_r_reg,\n act_wait_r_lcl_reg_0,\n \\grant_r_reg[3]_0 ,\n bm_end_r1_reg_4,\n pre_passing_open_bank_r_reg_0,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ,\n pre_passing_open_bank_r_reg_1,\n idle_r_lcl_reg_4,\n periodic_rd_ack_r_lcl_reg,\n idle_r_lcl_reg_5,\n rb_hit_busy_r,\n rb_hit_busy_r_reg_0,\n accept_r_reg,\n rb_hit_busy_r_reg_1,\n rb_hit_busy_r_reg_2,\n periodic_rd_ack_r_lcl_reg_0,\n pre_bm_end_r_reg_0,\n pre_bm_end_r_reg_1,\n pre_bm_end_r_reg_2,\n periodic_rd_ack_r_lcl_reg_1,\n use_addr,\n accept_internal_r_reg,\n req_wr_r_lcl_reg_0,\n \\grant_r_reg[3]_1 ,\n req_wr_r_lcl_reg_1,\n ras_timer_zero_r,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ,\n idle_r_lcl_reg_6,\n pre_bm_end_r_reg_3,\n ordered_r_lcl_reg_1,\n idle_r_lcl_reg_7,\n rstdiv0_sync_r1_reg_rep__21,\n ordered_r_lcl_reg_2);\n output \\req_data_buf_addr_r_reg[4] ;\n output [0:0]E;\n output act_wait_r_lcl_reg;\n output pre_bm_end_r_15;\n output pre_passing_open_bank_r;\n output q_has_rd_16;\n output q_has_priority_17;\n output wait_for_maint_r_20;\n output tail_r_28;\n output wait_for_maint_r_lcl_reg_0;\n output \\rp_timer.rp_timer_r_reg[1] ;\n output [0:0]ordered_r;\n output [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;\n output rb_hit_busy_r_reg;\n output \\q_entry_r_reg[1]_0 ;\n output [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;\n output [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ;\n output [2:0]D;\n output \\ras_timer_r_reg[0] ;\n output [2:0]Q;\n output demand_priority_r_reg;\n output [1:0]order_q_r;\n output req_bank_rdy_ns;\n output act_wait_ns;\n output \\q_entry_r_reg[1]_1 ;\n output \\q_entry_r_reg[0]_0 ;\n output head_r_lcl_reg_0;\n output \\q_entry_r_reg[1]_2 ;\n output p_28_out;\n output \\ras_timer_r_reg[0]_0 ;\n output \\grant_r_reg[3] ;\n input CLK;\n input pass_open_bank_ns;\n input pre_bm_end_ns;\n input pre_passing_open_bank_ns;\n input q_has_rd_r_reg_0;\n input q_has_priority_r_reg_0;\n input \\maintenance_request.maint_req_r_lcl_reg ;\n input wait_for_maint_r_lcl_reg_1;\n input [0:0]SR;\n input idle_r_lcl_reg_0;\n input rstdiv0_sync_r1_reg_rep__0;\n input head_r_lcl_reg_1;\n input auto_pre_r_lcl_reg_0;\n input ordered_r_lcl_reg_0;\n input \\req_bank_r_lcl_reg[0] ;\n input idle_r_lcl_reg_1;\n input [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ;\n input rstdiv0_sync_r1_reg_rep__20;\n input idle_r_lcl_reg_2;\n input [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 ;\n input idle_r_lcl_reg_3;\n input [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4 ;\n input rd_wr_r_lcl_reg;\n input \\ras_timer_r_reg[1] ;\n input \\ras_timer_r_reg[1]_0 ;\n input \\ras_timer_r_reg[1]_1 ;\n input bm_end_r1_reg;\n input bm_end_r1_reg_0;\n input bm_end_r1_reg_1;\n input bm_end_r1_reg_2;\n input \\ras_timer_r_reg[2] ;\n input \\ras_timer_r_reg[2]_0 ;\n input \\ras_timer_r_reg[2]_1 ;\n input bm_end_r1_reg_3;\n input req_priority_r;\n input rd_wr_r_lcl_reg_0;\n input req_wr_r_lcl_reg;\n input col_wait_r_reg;\n input act_wait_r_lcl_reg_0;\n input [0:0]\\grant_r_reg[3]_0 ;\n input bm_end_r1_reg_4;\n input pre_passing_open_bank_r_reg_0;\n input \\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;\n input pre_passing_open_bank_r_reg_1;\n input idle_r_lcl_reg_4;\n input periodic_rd_ack_r_lcl_reg;\n input idle_r_lcl_reg_5;\n input [2:0]rb_hit_busy_r;\n input rb_hit_busy_r_reg_0;\n input accept_r_reg;\n input rb_hit_busy_r_reg_1;\n input rb_hit_busy_r_reg_2;\n input periodic_rd_ack_r_lcl_reg_0;\n input pre_bm_end_r_reg_0;\n input pre_bm_end_r_reg_1;\n input pre_bm_end_r_reg_2;\n input periodic_rd_ack_r_lcl_reg_1;\n input use_addr;\n input accept_internal_r_reg;\n input req_wr_r_lcl_reg_0;\n input [0:0]\\grant_r_reg[3]_1 ;\n input req_wr_r_lcl_reg_1;\n input ras_timer_zero_r;\n input [2:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ;\n input idle_r_lcl_reg_6;\n input pre_bm_end_r_reg_3;\n input ordered_r_lcl_reg_1;\n input idle_r_lcl_reg_7;\n input rstdiv0_sync_r1_reg_rep__21;\n input ordered_r_lcl_reg_2;\n\n wire CLK;\n wire [2:0]D;\n wire [0:0]E;\n wire [2:0]Q;\n wire [0:0]SR;\n wire accept_internal_r_reg;\n wire accept_r_reg;\n wire act_wait_ns;\n wire act_wait_r_lcl_reg;\n wire act_wait_r_lcl_reg_0;\n wire auto_pre_r_lcl_reg_0;\n wire bm_end_r1_reg;\n wire bm_end_r1_reg_0;\n wire bm_end_r1_reg_1;\n wire bm_end_r1_reg_2;\n wire bm_end_r1_reg_3;\n wire bm_end_r1_reg_4;\n wire col_wait_r_reg;\n wire demand_priority_r_reg;\n wire \\grant_r_reg[3] ;\n wire [0:0]\\grant_r_reg[3]_0 ;\n wire [0:0]\\grant_r_reg[3]_1 ;\n wire head_r_lcl_reg_0;\n wire head_r_lcl_reg_1;\n wire i___14_i_3_n_0;\n wire i___14_i_4_n_0;\n wire idle_r_lcl_reg_0;\n wire idle_r_lcl_reg_1;\n wire idle_r_lcl_reg_2;\n wire idle_r_lcl_reg_3;\n wire idle_r_lcl_reg_4;\n wire idle_r_lcl_reg_5;\n wire idle_r_lcl_reg_6;\n wire idle_r_lcl_reg_7;\n wire \\maintenance_request.maint_req_r_lcl_reg ;\n wire [1:0]order_q_r;\n wire \\order_q_r[0]_i_1__2_n_0 ;\n wire \\order_q_r[1]_i_1__2_n_0 ;\n wire [0:0]ordered_r;\n wire ordered_r_lcl_reg_0;\n wire ordered_r_lcl_reg_1;\n wire ordered_r_lcl_reg_2;\n wire p_28_out;\n wire pass_open_bank_ns;\n wire periodic_rd_ack_r_lcl_reg;\n wire periodic_rd_ack_r_lcl_reg_0;\n wire periodic_rd_ack_r_lcl_reg_1;\n wire pre_bm_end_ns;\n wire pre_bm_end_r_15;\n wire pre_bm_end_r_reg_0;\n wire pre_bm_end_r_reg_1;\n wire pre_bm_end_r_reg_2;\n wire pre_bm_end_r_reg_3;\n wire pre_passing_open_bank_ns;\n wire pre_passing_open_bank_r;\n wire pre_passing_open_bank_r_reg_0;\n wire pre_passing_open_bank_r_reg_1;\n wire \\q_entry_r[0]_i_1__2_n_0 ;\n wire \\q_entry_r[0]_i_2__0_n_0 ;\n wire \\q_entry_r[1]_i_1__2_n_0 ;\n wire \\q_entry_r[1]_i_3__0_n_0 ;\n wire \\q_entry_r[1]_i_4__0_n_0 ;\n wire \\q_entry_r_reg[0]_0 ;\n wire \\q_entry_r_reg[1]_0 ;\n wire \\q_entry_r_reg[1]_1 ;\n wire \\q_entry_r_reg[1]_2 ;\n wire q_has_priority_17;\n wire q_has_priority_r_reg_0;\n wire q_has_rd_16;\n wire q_has_rd_r_reg_0;\n wire \\ras_timer_r[0]_i_2__0_n_0 ;\n wire \\ras_timer_r[1]_i_2__0_n_0 ;\n wire \\ras_timer_r[2]_i_2__0_n_0 ;\n wire \\ras_timer_r_reg[0] ;\n wire \\ras_timer_r_reg[0]_0 ;\n wire \\ras_timer_r_reg[1] ;\n wire \\ras_timer_r_reg[1]_0 ;\n wire \\ras_timer_r_reg[1]_1 ;\n wire \\ras_timer_r_reg[2] ;\n wire \\ras_timer_r_reg[2]_0 ;\n wire \\ras_timer_r_reg[2]_1 ;\n wire ras_timer_zero_r;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 ;\n wire [0:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4 ;\n wire \\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;\n wire [2:0]\\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ;\n wire [2:0]rb_hit_busy_r;\n wire rb_hit_busy_r_reg;\n wire rb_hit_busy_r_reg_0;\n wire rb_hit_busy_r_reg_1;\n wire rb_hit_busy_r_reg_2;\n wire rd_wr_r_lcl_reg;\n wire rd_wr_r_lcl_reg_0;\n wire \\req_bank_r_lcl_reg[0] ;\n wire req_bank_rdy_ns;\n wire \\req_data_buf_addr_r_reg[4] ;\n wire req_priority_r;\n wire req_wr_r_lcl_reg;\n wire req_wr_r_lcl_reg_0;\n wire req_wr_r_lcl_reg_1;\n wire \\rp_timer.rp_timer_r_reg[1] ;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire tail_r_28;\n wire use_addr;\n wire wait_for_maint_r_20;\n wire wait_for_maint_r_lcl_reg_0;\n wire wait_for_maint_r_lcl_reg_1;\n\n LUT6 #(\n .INIT(64'hFFFFFFFF0404FF04)) \n act_wait_r_lcl_i_1__1\n (.I0(\\ras_timer_r_reg[0] ),\n .I1(act_wait_r_lcl_reg_0),\n .I2(\\grant_r_reg[3]_0 ),\n .I3(act_wait_r_lcl_reg),\n .I4(\\q_entry_r_reg[1]_0 ),\n .I5(bm_end_r1_reg_4),\n .O(act_wait_ns));\n LUT6 #(\n .INIT(64'h00000000F4F4FFF4)) \n act_wait_r_lcl_i_2__1\n (.I0(pre_passing_open_bank_r_reg_0),\n .I1(Q[2]),\n .I2(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ),\n .I3(Q[1]),\n .I4(pre_passing_open_bank_r_reg_1),\n .I5(idle_r_lcl_reg_4),\n .O(\\ras_timer_r_reg[0] ));\n FDRE auto_pre_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(auto_pre_r_lcl_reg_0),\n .Q(\\rp_timer.rp_timer_r_reg[1] ),\n .R(1'b0));\n FDRE #(\n .INIT(1'b1)) \n \\compute_tail.tail_r_lcl_reg \n (.C(CLK),\n .CE(1'b1),\n .D(idle_r_lcl_reg_0),\n .Q(tail_r_28),\n .R(SR));\n LUT6 #(\n .INIT(64'hE0E0E0EEE0EEE0EE)) \n demand_priority_r_i_2\n (.I0(req_priority_r),\n .I1(q_has_priority_17),\n .I2(rd_wr_r_lcl_reg_0),\n .I3(order_q_r[1]),\n .I4(order_q_r[0]),\n .I5(req_wr_r_lcl_reg),\n .O(demand_priority_r_reg));\n LUT5 #(\n .INIT(32'hFFDFFFFF)) \n \\grant_r[3]_i_7__0 \n (.I0(ras_timer_zero_r),\n .I1(\\req_data_buf_addr_r_reg[4] ),\n .I2(act_wait_r_lcl_reg_0),\n .I3(wait_for_maint_r_20),\n .I4(wait_for_maint_r_lcl_reg_0),\n .O(\\grant_r_reg[3] ));\n FDRE head_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(head_r_lcl_reg_1),\n .Q(wait_for_maint_r_lcl_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__0));\n LUT5 #(\n .INIT(32'h55151515)) \n i___13_i_1\n (.I0(pre_bm_end_r_15),\n .I1(\\grant_r_reg[3]_1 ),\n .I2(act_wait_r_lcl_reg),\n .I3(rd_wr_r_lcl_reg_0),\n .I4(req_wr_r_lcl_reg_1),\n .O(\\q_entry_r_reg[1]_0 ));\n LUT6 #(\n .INIT(64'hAA02AA32AA02AACE)) \n i___14_i_1\n (.I0(i___14_i_3_n_0),\n .I1(i___14_i_4_n_0),\n .I2(\\req_data_buf_addr_r_reg[4] ),\n .I3(accept_r_reg),\n .I4(rb_hit_busy_r_reg_1),\n .I5(rb_hit_busy_r_reg_2),\n .O(head_r_lcl_reg_0));\n LUT5 #(\n .INIT(32'hFFFFD1FF)) \n i___14_i_2\n (.I0(i___14_i_4_n_0),\n .I1(\\req_data_buf_addr_r_reg[4] ),\n .I2(periodic_rd_ack_r_lcl_reg_0),\n .I3(\\q_entry_r_reg[1]_0 ),\n .I4(periodic_rd_ack_r_lcl_reg),\n .O(\\q_entry_r_reg[1]_2 ));\n LUT2 #(\n .INIT(4'h2)) \n i___14_i_3\n (.I0(\\q_entry_r_reg[0]_0 ),\n .I1(\\q_entry_r_reg[1]_1 ),\n .O(i___14_i_3_n_0));\n LUT6 #(\n .INIT(64'hDD0DDD0D0000DD0D)) \n i___14_i_4\n (.I0(Q[0]),\n .I1(pre_bm_end_r_reg_0),\n .I2(Q[2]),\n .I3(pre_bm_end_r_reg_1),\n .I4(Q[1]),\n .I5(pre_bm_end_r_reg_2),\n .O(i___14_i_4_n_0));\n LUT6 #(\n .INIT(64'h00000000FD555555)) \n i___53_i_1\n (.I0(\\req_data_buf_addr_r_reg[4] ),\n .I1(periodic_rd_ack_r_lcl_reg_1),\n .I2(use_addr),\n .I3(accept_internal_r_reg),\n .I4(wait_for_maint_r_lcl_reg_0),\n .I5(req_wr_r_lcl_reg_0),\n .O(rb_hit_busy_r_reg));\n LUT5 #(\n .INIT(32'h55151515)) \n i___56_i_2\n (.I0(pre_passing_open_bank_r),\n .I1(\\grant_r_reg[3]_1 ),\n .I2(act_wait_r_lcl_reg),\n .I3(rd_wr_r_lcl_reg_0),\n .I4(req_wr_r_lcl_reg_1),\n .O(\\ras_timer_r_reg[0]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1089\" *) \n LUT1 #(\n .INIT(2'h1)) \n idle_r_lcl_i_1__1\n (.I0(rb_hit_busy_r_reg),\n .O(E));\n FDRE idle_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(E),\n .Q(\\req_data_buf_addr_r_reg[4] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h553100305531CC30)) \n \\order_q_r[0]_i_1__2 \n (.I0(ordered_r_lcl_reg_2),\n .I1(order_q_r[0]),\n .I2(order_q_r[1]),\n .I3(req_wr_r_lcl_reg),\n .I4(idle_r_lcl_reg_7),\n .I5(rstdiv0_sync_r1_reg_rep__21),\n .O(\\order_q_r[0]_i_1__2_n_0 ));\n LUT6 #(\n .INIT(64'hAAC200C0AAC2F0C0)) \n \\order_q_r[1]_i_1__2 \n (.I0(ordered_r_lcl_reg_1),\n .I1(order_q_r[0]),\n .I2(order_q_r[1]),\n .I3(req_wr_r_lcl_reg),\n .I4(idle_r_lcl_reg_7),\n .I5(rstdiv0_sync_r1_reg_rep__21),\n .O(\\order_q_r[1]_i_1__2_n_0 ));\n FDRE \\order_q_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\order_q_r[0]_i_1__2_n_0 ),\n .Q(order_q_r[0]),\n .R(1'b0));\n FDRE \\order_q_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\order_q_r[1]_i_1__2_n_0 ),\n .Q(order_q_r[1]),\n .R(1'b0));\n FDRE ordered_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(ordered_r_lcl_reg_0),\n .Q(ordered_r),\n .R(1'b0));\n FDRE pass_open_bank_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pass_open_bank_ns),\n .Q(act_wait_r_lcl_reg),\n .R(1'b0));\n FDRE pre_bm_end_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pre_bm_end_ns),\n .Q(pre_bm_end_r_15),\n .R(1'b0));\n FDRE pre_passing_open_bank_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pre_passing_open_bank_ns),\n .Q(pre_passing_open_bank_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hF2D1FFFFF2D10000)) \n \\q_entry_r[0]_i_1__2 \n (.I0(periodic_rd_ack_r_lcl_reg_0),\n .I1(\\q_entry_r_reg[1]_0 ),\n .I2(\\q_entry_r[0]_i_2__0_n_0 ),\n .I3(pre_bm_end_r_reg_3),\n .I4(\\q_entry_r_reg[1]_2 ),\n .I5(\\q_entry_r_reg[0]_0 ),\n .O(\\q_entry_r[0]_i_1__2_n_0 ));\n LUT5 #(\n .INIT(32'h909000F0)) \n \\q_entry_r[0]_i_2__0 \n (.I0(rb_hit_busy_r_reg_2),\n .I1(i___14_i_4_n_0),\n .I2(\\q_entry_r_reg[1]_0 ),\n .I3(\\q_entry_r_reg[0]_0 ),\n .I4(periodic_rd_ack_r_lcl_reg),\n .O(\\q_entry_r[0]_i_2__0_n_0 ));\n LUT6 #(\n .INIT(64'hFB08FFFFFB080000)) \n \\q_entry_r[1]_i_1__2 \n (.I0(idle_r_lcl_reg_6),\n .I1(periodic_rd_ack_r_lcl_reg_0),\n .I2(\\q_entry_r_reg[1]_0 ),\n .I3(\\q_entry_r[1]_i_3__0_n_0 ),\n .I4(\\q_entry_r_reg[1]_2 ),\n .I5(\\q_entry_r_reg[1]_1 ),\n .O(\\q_entry_r[1]_i_1__2_n_0 ));\n LUT6 #(\n .INIT(64'hB88BFFFFB88B0000)) \n \\q_entry_r[1]_i_3__0 \n (.I0(\\q_entry_r[1]_i_4__0_n_0 ),\n .I1(periodic_rd_ack_r_lcl_reg),\n .I2(\\q_entry_r_reg[1]_1 ),\n .I3(\\q_entry_r_reg[0]_0 ),\n .I4(\\q_entry_r_reg[1]_0 ),\n .I5(idle_r_lcl_reg_5),\n .O(\\q_entry_r[1]_i_3__0_n_0 ));\n LUT5 #(\n .INIT(32'h7EE8E881)) \n \\q_entry_r[1]_i_4__0 \n (.I0(i___14_i_4_n_0),\n .I1(rb_hit_busy_r[0]),\n .I2(rb_hit_busy_r[1]),\n .I3(rb_hit_busy_r[2]),\n .I4(rb_hit_busy_r_reg_0),\n .O(\\q_entry_r[1]_i_4__0_n_0 ));\n FDSE \\q_entry_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\q_entry_r[0]_i_1__2_n_0 ),\n .Q(\\q_entry_r_reg[0]_0 ),\n .S(SR));\n FDSE \\q_entry_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\q_entry_r[1]_i_1__2_n_0 ),\n .Q(\\q_entry_r_reg[1]_1 ),\n .S(SR));\n FDRE q_has_priority_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(q_has_priority_r_reg_0),\n .Q(q_has_priority_17),\n .R(1'b0));\n FDRE q_has_rd_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(q_has_rd_r_reg_0),\n .Q(q_has_rd_16),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1088\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\ras_timer_r[0]_i_1__0 \n (.I0(\\ras_timer_r[0]_i_2__0_n_0 ),\n .I1(\\ras_timer_r_reg[0] ),\n .I2(rd_wr_r_lcl_reg),\n .O(D[0]));\n LUT6 #(\n .INIT(64'hB8BBB888B888B888)) \n \\ras_timer_r[0]_i_2__0 \n (.I0(\\ras_timer_r_reg[1] ),\n .I1(Q[2]),\n .I2(\\ras_timer_r_reg[1]_0 ),\n .I3(Q[1]),\n .I4(Q[0]),\n .I5(\\ras_timer_r_reg[1]_1 ),\n .O(\\ras_timer_r[0]_i_2__0_n_0 ));\n LUT3 #(\n .INIT(8'hB8)) \n \\ras_timer_r[1]_i_1__1 \n (.I0(\\ras_timer_r[1]_i_2__0_n_0 ),\n .I1(\\ras_timer_r_reg[0] ),\n .I2(bm_end_r1_reg),\n .O(D[1]));\n LUT6 #(\n .INIT(64'h8BBB8B888B888B88)) \n \\ras_timer_r[1]_i_2__0 \n (.I0(bm_end_r1_reg_0),\n .I1(Q[2]),\n .I2(bm_end_r1_reg_1),\n .I3(Q[1]),\n .I4(Q[0]),\n .I5(bm_end_r1_reg_2),\n .O(\\ras_timer_r[1]_i_2__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1088\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\ras_timer_r[2]_i_1__1 \n (.I0(\\ras_timer_r[2]_i_2__0_n_0 ),\n .I1(\\ras_timer_r_reg[0] ),\n .I2(\\ras_timer_r_reg[2] ),\n .O(D[2]));\n LUT6 #(\n .INIT(64'hB8BBB888B888B888)) \n \\ras_timer_r[2]_i_2__0 \n (.I0(\\ras_timer_r_reg[2]_0 ),\n .I1(Q[2]),\n .I2(\\ras_timer_r_reg[2]_1 ),\n .I3(Q[1]),\n .I4(Q[0]),\n .I5(bm_end_r1_reg_3),\n .O(\\ras_timer_r[2]_i_2__0_n_0 ));\n LUT6 #(\n .INIT(64'h00000000F2020000)) \n \\rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1 \n (.I0(rb_hit_busy_r_reg),\n .I1(\\req_bank_r_lcl_reg[0] ),\n .I2(idle_r_lcl_reg_1),\n .I3(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ),\n .I4(\\q_entry_r_reg[1]_0 ),\n .I5(rstdiv0_sync_r1_reg_rep__20),\n .O(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ));\n LUT6 #(\n .INIT(64'h00000000F2020000)) \n \\rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1__0 \n (.I0(rb_hit_busy_r_reg),\n .I1(\\req_bank_r_lcl_reg[0] ),\n .I2(idle_r_lcl_reg_2),\n .I3(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 ),\n .I4(\\q_entry_r_reg[1]_0 ),\n .I5(rstdiv0_sync_r1_reg_rep__20),\n .O(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ));\n LUT6 #(\n .INIT(64'h00000000F2020000)) \n \\rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1__1 \n (.I0(rb_hit_busy_r_reg),\n .I1(\\req_bank_r_lcl_reg[0] ),\n .I2(idle_r_lcl_reg_3),\n .I3(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4 ),\n .I4(\\q_entry_r_reg[1]_0 ),\n .I5(rstdiv0_sync_r1_reg_rep__20),\n .O(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ));\n FDRE #(\n .INIT(1'b0)) \n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 [0]),\n .Q(Q[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 [1]),\n .Q(Q[1]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 [2]),\n .Q(Q[2]),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1089\" *) \n LUT2 #(\n .INIT(4'h2)) \n rb_hit_busy_r_i_1__1\n (.I0(rb_hit_busy_r_reg),\n .I1(\\req_bank_r_lcl_reg[0] ),\n .O(p_28_out));\n LUT5 #(\n .INIT(32'h888A8A8A)) \n req_bank_rdy_r_i_1\n (.I0(col_wait_r_reg),\n .I1(rd_wr_r_lcl_reg_0),\n .I2(order_q_r[1]),\n .I3(order_q_r[0]),\n .I4(req_wr_r_lcl_reg),\n .O(req_bank_rdy_ns));\n FDRE wait_for_maint_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wait_for_maint_r_lcl_reg_1),\n .Q(wait_for_maint_r_20),\n .R(\\maintenance_request.maint_req_r_lcl_reg ));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_bank_state\n (bm_end_r1,\n \\act_this_rank_r_reg[0]_0 ,\n \\rp_timer.rp_timer_r_reg[1]_0 ,\n pre_wait_r,\n act_this_rank_r,\n demand_priority_r_reg_0,\n demanded_prior_r_reg_0,\n ofs_rdy_r,\n wr_this_rank_r,\n rd_this_rank_r,\n \\starve_limit_cntr_r_reg[2]_0 ,\n pre_bm_end_ns,\n pre_passing_open_bank_ns,\n \\ras_timer_r_reg[1]_0 ,\n \\ras_timer_r_reg[2]_0 ,\n \\pre_4_1_1T_arb.granted_pre_r_reg ,\n \\ras_timer_r_reg[0]_0 ,\n auto_pre_r_lcl_reg,\n \\rnk_config_strobe_r_reg[0] ,\n demanded_prior_r_reg_1,\n p_130_out,\n CLK,\n act_wait_ns,\n req_bank_rdy_ns,\n SR,\n ofs_rdy_r0,\n start_wtp_timer0,\n rd_wr_r_lcl_reg,\n req_priority_r_reg,\n idle_r_lcl_reg,\n \\grant_r_reg[2] ,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ,\n pass_open_bank_ns,\n rtp_timer_ns1,\n rd_wr_r_lcl_reg_0,\n bm_end_r1_reg_0,\n rstdiv0_sync_r1_reg_rep__21,\n \\grant_r_reg[0] ,\n auto_pre_r_lcl_reg_0,\n \\grant_r_reg[0]_0 ,\n rstdiv0_sync_r1_reg_rep__22,\n accept_r_reg,\n tail_r,\n demand_priority_r_reg_1,\n demanded_prior_r_reg_2,\n demanded_prior_r_reg_3,\n req_wr_r_lcl_reg,\n q_has_rd,\n granted_col_r_reg,\n D,\n pass_open_bank_r_lcl_reg,\n rstdiv0_sync_r1_reg_rep__20,\n rstdiv0_sync_r1_reg_rep__0);\n output bm_end_r1;\n output \\act_this_rank_r_reg[0]_0 ;\n output \\rp_timer.rp_timer_r_reg[1]_0 ;\n output pre_wait_r;\n output [0:0]act_this_rank_r;\n output demand_priority_r_reg_0;\n output demanded_prior_r_reg_0;\n output ofs_rdy_r;\n output [0:0]wr_this_rank_r;\n output [0:0]rd_this_rank_r;\n output \\starve_limit_cntr_r_reg[2]_0 ;\n output pre_bm_end_ns;\n output pre_passing_open_bank_ns;\n output \\ras_timer_r_reg[1]_0 ;\n output \\ras_timer_r_reg[2]_0 ;\n output \\pre_4_1_1T_arb.granted_pre_r_reg ;\n output \\ras_timer_r_reg[0]_0 ;\n output auto_pre_r_lcl_reg;\n output \\rnk_config_strobe_r_reg[0] ;\n output demanded_prior_r_reg_1;\n input p_130_out;\n input CLK;\n input act_wait_ns;\n input req_bank_rdy_ns;\n input [0:0]SR;\n input ofs_rdy_r0;\n input start_wtp_timer0;\n input rd_wr_r_lcl_reg;\n input req_priority_r_reg;\n input idle_r_lcl_reg;\n input [1:0]\\grant_r_reg[2] ;\n input \\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;\n input pass_open_bank_ns;\n input rtp_timer_ns1;\n input rd_wr_r_lcl_reg_0;\n input bm_end_r1_reg_0;\n input rstdiv0_sync_r1_reg_rep__21;\n input [0:0]\\grant_r_reg[0] ;\n input auto_pre_r_lcl_reg_0;\n input [0:0]\\grant_r_reg[0]_0 ;\n input rstdiv0_sync_r1_reg_rep__22;\n input accept_r_reg;\n input tail_r;\n input demand_priority_r_reg_1;\n input demanded_prior_r_reg_2;\n input demanded_prior_r_reg_3;\n input req_wr_r_lcl_reg;\n input q_has_rd;\n input granted_col_r_reg;\n input [2:0]D;\n input pass_open_bank_r_lcl_reg;\n input rstdiv0_sync_r1_reg_rep__20;\n input rstdiv0_sync_r1_reg_rep__0;\n\n wire CLK;\n wire [2:0]D;\n wire [0:0]SR;\n wire accept_r_reg;\n wire [0:0]act_this_rank_r;\n wire \\act_this_rank_r_reg[0]_0 ;\n wire act_wait_ns;\n wire auto_pre_r_lcl_reg;\n wire auto_pre_r_lcl_reg_0;\n wire bm_end_r1;\n wire bm_end_r1_reg_0;\n wire col_wait_r_i_1__0_n_0;\n wire demand_priority_ns;\n wire demand_priority_r_i_2__0_n_0;\n wire demand_priority_r_i_4__0_n_0;\n wire demand_priority_r_i_5_n_0;\n wire demand_priority_r_reg_0;\n wire demand_priority_r_reg_1;\n wire demanded_prior_ns;\n wire demanded_prior_r_reg_0;\n wire demanded_prior_r_reg_1;\n wire demanded_prior_r_reg_2;\n wire demanded_prior_r_reg_3;\n wire [0:0]\\grant_r_reg[0] ;\n wire [0:0]\\grant_r_reg[0]_0 ;\n wire [1:0]\\grant_r_reg[2] ;\n wire granted_col_r_reg;\n wire idle_r_lcl_reg;\n wire ofs_rdy_r;\n wire ofs_rdy_r0;\n wire p_130_out;\n wire pass_open_bank_ns;\n wire pass_open_bank_r_lcl_reg;\n wire \\pre_4_1_1T_arb.granted_pre_r_reg ;\n wire pre_bm_end_ns;\n wire pre_passing_open_bank_ns;\n wire pre_wait_ns;\n wire pre_wait_r;\n wire q_has_rd;\n wire [2:0]ras_timer_r;\n wire \\ras_timer_r[2]_i_4__1_n_0 ;\n wire \\ras_timer_r_reg[0]_0 ;\n wire \\ras_timer_r_reg[1]_0 ;\n wire \\ras_timer_r_reg[2]_0 ;\n wire ras_timer_zero_ns;\n wire \\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;\n wire rcd_active_r;\n wire \\rcd_timer_gt_2.rcd_timer_r[0]_i_1_n_0 ;\n wire [0:0]rd_this_rank_r;\n wire rd_wr_r_lcl_reg;\n wire rd_wr_r_lcl_reg_0;\n wire req_bank_rdy_ns;\n wire req_bank_rdy_r;\n wire req_priority_r_reg;\n wire req_wr_r_lcl_reg;\n wire \\rnk_config_strobe_r_reg[0] ;\n wire \\rp_timer.rp_timer_r[0]_i_1_n_0 ;\n wire \\rp_timer.rp_timer_r[1]_i_1_n_0 ;\n wire \\rp_timer.rp_timer_r_reg[1]_0 ;\n wire [0:0]rp_timer_ns;\n wire [1:0]rp_timer_r;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire rstdiv0_sync_r1_reg_rep__22;\n wire rtp_timer_ns1;\n wire [1:0]rtp_timer_r;\n wire \\rtp_timer_r[0]_i_1_n_0 ;\n wire \\rtp_timer_r[1]_i_1_n_0 ;\n wire start_pre;\n wire start_wtp_timer0;\n wire [2:0]starve_limit_cntr_r;\n wire starve_limit_cntr_r0;\n wire \\starve_limit_cntr_r[0]_i_1_n_0 ;\n wire \\starve_limit_cntr_r[1]_i_1_n_0 ;\n wire \\starve_limit_cntr_r[2]_i_1_n_0 ;\n wire \\starve_limit_cntr_r_reg[2]_0 ;\n wire tail_r;\n wire [0:0]wr_this_rank_r;\n\n FDRE \\act_this_rank_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\act_this_rank_r_reg[0]_0 ),\n .Q(act_this_rank_r),\n .R(1'b0));\n FDRE act_wait_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(act_wait_ns),\n .Q(\\act_this_rank_r_reg[0]_0 ),\n .R(1'b0));\n FDRE bm_end_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(p_130_out),\n .Q(bm_end_r1),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1061\" *) \n LUT4 #(\n .INIT(16'hFFBA)) \n col_wait_r_i_1__0\n (.I0(rcd_active_r),\n .I1(\\grant_r_reg[2] [0]),\n .I2(\\starve_limit_cntr_r_reg[2]_0 ),\n .I3(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ),\n .O(col_wait_r_i_1__0_n_0));\n FDRE col_wait_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(col_wait_r_i_1__0_n_0),\n .Q(\\starve_limit_cntr_r_reg[2]_0 ),\n .R(SR));\n LUT5 #(\n .INIT(32'h0000FB00)) \n demand_priority_r_i_1__2\n (.I0(demand_priority_r_reg_0),\n .I1(demand_priority_r_i_2__0_n_0),\n .I2(req_priority_r_reg),\n .I3(idle_r_lcl_reg),\n .I4(demand_priority_r_i_4__0_n_0),\n .O(demand_priority_ns));\n LUT6 #(\n .INIT(64'hFF2FFFFFFFFFFFFF)) \n demand_priority_r_i_2__0\n (.I0(req_wr_r_lcl_reg),\n .I1(q_has_rd),\n .I2(req_bank_rdy_r),\n .I3(\\grant_r_reg[2] [0]),\n .I4(granted_col_r_reg),\n .I5(demand_priority_r_i_5_n_0),\n .O(demand_priority_r_i_2__0_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1061\" *) \n LUT4 #(\n .INIT(16'h0051)) \n demand_priority_r_i_4__0\n (.I0(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ),\n .I1(\\starve_limit_cntr_r_reg[2]_0 ),\n .I2(\\grant_r_reg[2] [0]),\n .I3(rcd_active_r),\n .O(demand_priority_r_i_4__0_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1063\" *) \n LUT3 #(\n .INIT(8'h80)) \n demand_priority_r_i_5\n (.I0(starve_limit_cntr_r[2]),\n .I1(starve_limit_cntr_r[1]),\n .I2(starve_limit_cntr_r[0]),\n .O(demand_priority_r_i_5_n_0));\n FDRE demand_priority_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(demand_priority_ns),\n .Q(demand_priority_r_reg_0),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hDDDDDDDD00000D00)) \n demanded_prior_r_i_1__1\n (.I0(demand_priority_r_reg_0),\n .I1(demanded_prior_r_reg_0),\n .I2(\\grant_r_reg[2] [1]),\n .I3(demand_priority_r_reg_1),\n .I4(demanded_prior_r_reg_2),\n .I5(demanded_prior_r_reg_3),\n .O(demanded_prior_ns));\n FDRE demanded_prior_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(demanded_prior_ns),\n .Q(demanded_prior_r_reg_0),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1058\" *) \n LUT4 #(\n .INIT(16'h1000)) \n \\grant_r[1]_i_3__1 \n (.I0(auto_pre_r_lcl_reg_0),\n .I1(\\grant_r_reg[0]_0 ),\n .I2(pre_wait_r),\n .I3(\\rp_timer.rp_timer_r_reg[1]_0 ),\n .O(\\pre_4_1_1T_arb.granted_pre_r_reg ));\n LUT6 #(\n .INIT(64'h8888888880888080)) \n i___2_i_1\n (.I0(accept_r_reg),\n .I1(tail_r),\n .I2(rcd_active_r),\n .I3(\\grant_r_reg[2] [0]),\n .I4(\\starve_limit_cntr_r_reg[2]_0 ),\n .I5(\\act_this_rank_r_reg[0]_0 ),\n .O(auto_pre_r_lcl_reg));\n LUT5 #(\n .INIT(32'hBBBBBABB)) \n i___34_i_3\n (.I0(demand_priority_r_reg_1),\n .I1(demanded_prior_r_reg_3),\n .I2(\\grant_r_reg[2] [0]),\n .I3(demand_priority_r_reg_0),\n .I4(demanded_prior_r_reg_0),\n .O(\\rnk_config_strobe_r_reg[0] ));\n LUT6 #(\n .INIT(64'h0404040404FF0404)) \n i___90_i_1\n (.I0(demanded_prior_r_reg_0),\n .I1(demand_priority_r_reg_0),\n .I2(\\grant_r_reg[2] [0]),\n .I3(demanded_prior_r_reg_2),\n .I4(demand_priority_r_reg_1),\n .I5(\\grant_r_reg[2] [1]),\n .O(demanded_prior_r_reg_1));\n FDRE #(\n .INIT(1'b0)) \n ofs_rdy_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(ofs_rdy_r0),\n .Q(ofs_rdy_r),\n .R(SR));\n (* SOFT_HLUTNM = \"soft_lutpair1062\" *) \n LUT3 #(\n .INIT(8'hBA)) \n pre_bm_end_r_i_1__0\n (.I0(pre_passing_open_bank_ns),\n .I1(rp_timer_r[1]),\n .I2(rp_timer_r[0]),\n .O(pre_bm_end_ns));\n LUT6 #(\n .INIT(64'hAAA8AAAAAAA8AAA8)) \n pre_passing_open_bank_r_i_1__0\n (.I0(pass_open_bank_ns),\n .I1(\\grant_r_reg[2] [0]),\n .I2(rtp_timer_r[1]),\n .I3(rtp_timer_r[0]),\n .I4(\\rp_timer.rp_timer_r_reg[1]_0 ),\n .I5(pre_wait_r),\n .O(pre_passing_open_bank_ns));\n LUT6 #(\n .INIT(64'h0404040404550404)) \n pre_wait_r_i_1__0\n (.I0(pass_open_bank_ns),\n .I1(pre_wait_r),\n .I2(rp_timer_ns),\n .I3(rtp_timer_ns1),\n .I4(rtp_timer_r[0]),\n .I5(rtp_timer_r[1]),\n .O(pre_wait_ns));\n (* SOFT_HLUTNM = \"soft_lutpair1058\" *) \n LUT5 #(\n .INIT(32'hEAEAEAAA)) \n pre_wait_r_i_2\n (.I0(rstdiv0_sync_r1_reg_rep__22),\n .I1(\\rp_timer.rp_timer_r_reg[1]_0 ),\n .I2(pre_wait_r),\n .I3(\\grant_r_reg[0]_0 ),\n .I4(auto_pre_r_lcl_reg_0),\n .O(rp_timer_ns));\n FDRE pre_wait_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pre_wait_ns),\n .Q(pre_wait_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h000000000E0E000E)) \n \\ras_timer_r[0]_i_3__1 \n (.I0(ras_timer_r[1]),\n .I1(ras_timer_r[2]),\n .I2(ras_timer_r[0]),\n .I3(\\grant_r_reg[2] [0]),\n .I4(rd_wr_r_lcl_reg),\n .I5(bm_end_r1_reg_0),\n .O(\\ras_timer_r_reg[0]_0 ));\n LUT6 #(\n .INIT(64'h1100001011111111)) \n \\ras_timer_r[1]_i_3__2 \n (.I0(bm_end_r1),\n .I1(rstdiv0_sync_r1_reg_rep__21),\n .I2(ras_timer_r[2]),\n .I3(ras_timer_r[1]),\n .I4(ras_timer_r[0]),\n .I5(\\ras_timer_r[2]_i_4__1_n_0 ),\n .O(\\ras_timer_r_reg[1]_0 ));\n LUT6 #(\n .INIT(64'h1010100011111111)) \n \\ras_timer_r[2]_i_3__1 \n (.I0(bm_end_r1),\n .I1(rstdiv0_sync_r1_reg_rep__21),\n .I2(ras_timer_r[2]),\n .I3(ras_timer_r[1]),\n .I4(ras_timer_r[0]),\n .I5(\\ras_timer_r[2]_i_4__1_n_0 ),\n .O(\\ras_timer_r_reg[2]_0 ));\n LUT6 #(\n .INIT(64'hDDDDDDD0DDDDDDDD)) \n \\ras_timer_r[2]_i_4__1 \n (.I0(\\grant_r_reg[2] [0]),\n .I1(rd_wr_r_lcl_reg),\n .I2(ras_timer_r[2]),\n .I3(ras_timer_r[1]),\n .I4(ras_timer_r[0]),\n .I5(\\rcd_timer_gt_2.rcd_timer_r[0]_i_1_n_0 ),\n .O(\\ras_timer_r[2]_i_4__1_n_0 ));\n FDRE \\ras_timer_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(D[0]),\n .Q(ras_timer_r[0]),\n .R(1'b0));\n FDRE \\ras_timer_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(D[1]),\n .Q(ras_timer_r[1]),\n .R(1'b0));\n FDRE \\ras_timer_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(D[2]),\n .Q(ras_timer_r[2]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFFF1000FFFF1100)) \n ras_timer_zero_r_i_1__1\n (.I0(ras_timer_r[1]),\n .I1(ras_timer_r[2]),\n .I2(ras_timer_r[0]),\n .I3(rd_wr_r_lcl_reg_0),\n .I4(bm_end_r1_reg_0),\n .I5(\\rcd_timer_gt_2.rcd_timer_r[0]_i_1_n_0 ),\n .O(ras_timer_zero_ns));\n FDRE ras_timer_zero_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(ras_timer_zero_ns),\n .Q(\\rp_timer.rp_timer_r_reg[1]_0 ),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h8)) \n \\rcd_timer_gt_2.rcd_timer_r[0]_i_1 \n (.I0(\\act_this_rank_r_reg[0]_0 ),\n .I1(\\grant_r_reg[0] ),\n .O(\\rcd_timer_gt_2.rcd_timer_r[0]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rcd_timer_gt_2.rcd_timer_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rcd_timer_gt_2.rcd_timer_r[0]_i_1_n_0 ),\n .Q(rcd_active_r),\n .R(SR));\n FDRE \\rd_this_rank_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_wr_r_lcl_reg),\n .Q(rd_this_rank_r),\n .R(1'b0));\n FDRE req_bank_rdy_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(req_bank_rdy_ns),\n .Q(req_bank_rdy_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1062\" *) \n LUT4 #(\n .INIT(16'h0004)) \n \\rp_timer.rp_timer_r[0]_i_1 \n (.I0(rp_timer_r[0]),\n .I1(rp_timer_r[1]),\n .I2(start_pre),\n .I3(rstdiv0_sync_r1_reg_rep__20),\n .O(\\rp_timer.rp_timer_r[0]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hE000)) \n \\rp_timer.rp_timer_r[0]_i_2 \n (.I0(auto_pre_r_lcl_reg_0),\n .I1(\\grant_r_reg[0]_0 ),\n .I2(pre_wait_r),\n .I3(\\rp_timer.rp_timer_r_reg[1]_0 ),\n .O(start_pre));\n LUT6 #(\n .INIT(64'hF888F888F8888888)) \n \\rp_timer.rp_timer_r[1]_i_1 \n (.I0(rp_timer_r[1]),\n .I1(rp_timer_r[0]),\n .I2(\\rp_timer.rp_timer_r_reg[1]_0 ),\n .I3(pre_wait_r),\n .I4(\\grant_r_reg[0]_0 ),\n .I5(auto_pre_r_lcl_reg_0),\n .O(\\rp_timer.rp_timer_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rp_timer.rp_timer_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rp_timer.rp_timer_r[0]_i_1_n_0 ),\n .Q(rp_timer_r[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rp_timer.rp_timer_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rp_timer.rp_timer_r[1]_i_1_n_0 ),\n .Q(rp_timer_r[1]),\n .R(rstdiv0_sync_r1_reg_rep__0));\n (* SOFT_HLUTNM = \"soft_lutpair1059\" *) \n LUT4 #(\n .INIT(16'h0002)) \n \\rtp_timer_r[0]_i_1 \n (.I0(rtp_timer_r[1]),\n .I1(rtp_timer_r[0]),\n .I2(rstdiv0_sync_r1_reg_rep__20),\n .I3(pass_open_bank_r_lcl_reg),\n .O(\\rtp_timer_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1059\" *) \n LUT5 #(\n .INIT(32'h000000C2)) \n \\rtp_timer_r[1]_i_1 \n (.I0(\\grant_r_reg[2] [0]),\n .I1(rtp_timer_r[1]),\n .I2(rtp_timer_r[0]),\n .I3(pass_open_bank_r_lcl_reg),\n .I4(rstdiv0_sync_r1_reg_rep__20),\n .O(\\rtp_timer_r[1]_i_1_n_0 ));\n FDRE \\rtp_timer_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rtp_timer_r[0]_i_1_n_0 ),\n .Q(rtp_timer_r[0]),\n .R(1'b0));\n FDRE \\rtp_timer_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rtp_timer_r[1]_i_1_n_0 ),\n .Q(rtp_timer_r[1]),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1063\" *) \n LUT3 #(\n .INIT(8'h60)) \n \\starve_limit_cntr_r[0]_i_1 \n (.I0(starve_limit_cntr_r[0]),\n .I1(starve_limit_cntr_r0),\n .I2(\\starve_limit_cntr_r_reg[2]_0 ),\n .O(\\starve_limit_cntr_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1060\" *) \n LUT4 #(\n .INIT(16'h6A00)) \n \\starve_limit_cntr_r[1]_i_1 \n (.I0(starve_limit_cntr_r[1]),\n .I1(starve_limit_cntr_r0),\n .I2(starve_limit_cntr_r[0]),\n .I3(\\starve_limit_cntr_r_reg[2]_0 ),\n .O(\\starve_limit_cntr_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1060\" *) \n LUT5 #(\n .INIT(32'h6AAA0000)) \n \\starve_limit_cntr_r[2]_i_1 \n (.I0(starve_limit_cntr_r[2]),\n .I1(starve_limit_cntr_r0),\n .I2(starve_limit_cntr_r[0]),\n .I3(starve_limit_cntr_r[1]),\n .I4(\\starve_limit_cntr_r_reg[2]_0 ),\n .O(\\starve_limit_cntr_r[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00007F0000000000)) \n \\starve_limit_cntr_r[2]_i_2 \n (.I0(starve_limit_cntr_r[0]),\n .I1(starve_limit_cntr_r[1]),\n .I2(starve_limit_cntr_r[2]),\n .I3(granted_col_r_reg),\n .I4(\\grant_r_reg[2] [0]),\n .I5(req_bank_rdy_r),\n .O(starve_limit_cntr_r0));\n FDRE \\starve_limit_cntr_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\starve_limit_cntr_r[0]_i_1_n_0 ),\n .Q(starve_limit_cntr_r[0]),\n .R(1'b0));\n FDRE \\starve_limit_cntr_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\starve_limit_cntr_r[1]_i_1_n_0 ),\n .Q(starve_limit_cntr_r[1]),\n .R(1'b0));\n FDRE \\starve_limit_cntr_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\starve_limit_cntr_r[2]_i_1_n_0 ),\n .Q(starve_limit_cntr_r[2]),\n .R(1'b0));\n FDRE \\wr_this_rank_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(start_wtp_timer0),\n .Q(wr_this_rank_r),\n .R(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_bank_state\" *) \nmodule ddr3_if_mig_7series_v4_0_bank_state__parameterized0\n (bm_end_r1_0,\n \\act_this_rank_r_reg[0]_0 ,\n ras_timer_zero_r,\n pre_wait_r,\n act_this_rank_r,\n demand_priority_r_reg_0,\n demanded_prior_r_reg_0,\n ofs_rdy_r,\n wr_this_rank_r,\n rd_this_rank_r,\n \\starve_limit_cntr_r_reg[2]_0 ,\n pre_bm_end_ns,\n pre_passing_open_bank_ns,\n pre_passing_open_bank_r_reg,\n pre_passing_open_bank_r_reg_0,\n granted_pre_ns,\n \\grant_r_reg[2] ,\n \\ras_timer_r_reg[0]_0 ,\n \\ras_timer_r_reg[1]_0 ,\n \\ras_timer_r_reg[2]_0 ,\n auto_pre_r_lcl_reg,\n \\grant_r_reg[2]_0 ,\n \\grant_r_reg[1] ,\n \\rnk_config_strobe_r_reg[0] ,\n \\grant_r_reg[3] ,\n p_91_out,\n CLK,\n act_wait_ns,\n req_bank_rdy_ns,\n SR,\n ofs_rdy_r0,\n start_wtp_timer0,\n rd_wr_r_lcl_reg,\n req_priority_r_reg,\n idle_r_lcl_reg,\n pass_open_bank_ns,\n \\grant_r_reg[3]_0 ,\n pass_open_bank_r_lcl_reg,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ,\n auto_pre_r_lcl_reg_0,\n auto_pre_r_lcl_reg_1,\n \\grant_r_reg[1]_0 ,\n ras_timer_zero_r_reg_0,\n rd_wr_r_lcl_reg_0,\n bm_end_r1_reg_0,\n rstdiv0_sync_r1_reg_rep__22,\n accept_r_reg,\n tail_r_24,\n \\grant_r_reg[1]_1 ,\n \\last_master_r_reg[0] ,\n demanded_prior_r_reg_1,\n demand_priority_r_reg_1,\n demanded_prior_r_reg_2,\n req_wr_r_lcl_reg,\n q_has_rd_3,\n granted_col_r_reg,\n D,\n rstdiv0_sync_r1_reg_rep__20,\n pass_open_bank_r_lcl_reg_0,\n pass_open_bank_r_lcl_reg_1,\n rstdiv0_sync_r1_reg_rep__21,\n rstdiv0_sync_r1_reg_rep__0);\n output bm_end_r1_0;\n output \\act_this_rank_r_reg[0]_0 ;\n output ras_timer_zero_r;\n output pre_wait_r;\n output [0:0]act_this_rank_r;\n output demand_priority_r_reg_0;\n output demanded_prior_r_reg_0;\n output ofs_rdy_r;\n output [0:0]wr_this_rank_r;\n output [0:0]rd_this_rank_r;\n output \\starve_limit_cntr_r_reg[2]_0 ;\n output pre_bm_end_ns;\n output pre_passing_open_bank_ns;\n output pre_passing_open_bank_r_reg;\n output pre_passing_open_bank_r_reg_0;\n output granted_pre_ns;\n output \\grant_r_reg[2] ;\n output \\ras_timer_r_reg[0]_0 ;\n output \\ras_timer_r_reg[1]_0 ;\n output \\ras_timer_r_reg[2]_0 ;\n output auto_pre_r_lcl_reg;\n output \\grant_r_reg[2]_0 ;\n output \\grant_r_reg[1] ;\n output \\rnk_config_strobe_r_reg[0] ;\n output \\grant_r_reg[3] ;\n input p_91_out;\n input CLK;\n input act_wait_ns;\n input req_bank_rdy_ns;\n input [0:0]SR;\n input ofs_rdy_r0;\n input start_wtp_timer0;\n input rd_wr_r_lcl_reg;\n input req_priority_r_reg;\n input idle_r_lcl_reg;\n input pass_open_bank_ns;\n input [1:0]\\grant_r_reg[3]_0 ;\n input pass_open_bank_r_lcl_reg;\n input \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ;\n input auto_pre_r_lcl_reg_0;\n input auto_pre_r_lcl_reg_1;\n input [0:0]\\grant_r_reg[1]_0 ;\n input ras_timer_zero_r_reg_0;\n input rd_wr_r_lcl_reg_0;\n input bm_end_r1_reg_0;\n input rstdiv0_sync_r1_reg_rep__22;\n input accept_r_reg;\n input tail_r_24;\n input [0:0]\\grant_r_reg[1]_1 ;\n input \\last_master_r_reg[0] ;\n input demanded_prior_r_reg_1;\n input demand_priority_r_reg_1;\n input demanded_prior_r_reg_2;\n input req_wr_r_lcl_reg;\n input q_has_rd_3;\n input granted_col_r_reg;\n input [2:0]D;\n input rstdiv0_sync_r1_reg_rep__20;\n input pass_open_bank_r_lcl_reg_0;\n input pass_open_bank_r_lcl_reg_1;\n input rstdiv0_sync_r1_reg_rep__21;\n input rstdiv0_sync_r1_reg_rep__0;\n\n wire CLK;\n wire [2:0]D;\n wire [0:0]SR;\n wire accept_r_reg;\n wire [0:0]act_this_rank_r;\n wire \\act_this_rank_r_reg[0]_0 ;\n wire act_wait_ns;\n wire auto_pre_r_lcl_reg;\n wire auto_pre_r_lcl_reg_0;\n wire auto_pre_r_lcl_reg_1;\n wire bm_end_r1_0;\n wire bm_end_r1_reg_0;\n wire col_wait_r_i_1__2_n_0;\n wire demand_priority_ns;\n wire demand_priority_r_i_2__1_n_0;\n wire demand_priority_r_i_4__2_n_0;\n wire demand_priority_r_i_5__0_n_0;\n wire demand_priority_r_reg_0;\n wire demand_priority_r_reg_1;\n wire demanded_prior_ns;\n wire demanded_prior_r_reg_0;\n wire demanded_prior_r_reg_1;\n wire demanded_prior_r_reg_2;\n wire \\grant_r_reg[1] ;\n wire [0:0]\\grant_r_reg[1]_0 ;\n wire [0:0]\\grant_r_reg[1]_1 ;\n wire \\grant_r_reg[2] ;\n wire \\grant_r_reg[2]_0 ;\n wire \\grant_r_reg[3] ;\n wire [1:0]\\grant_r_reg[3]_0 ;\n wire granted_col_r_reg;\n wire granted_pre_ns;\n wire idle_r_lcl_reg;\n wire \\last_master_r_reg[0] ;\n wire ofs_rdy_r;\n wire ofs_rdy_r0;\n wire p_91_out;\n wire pass_open_bank_ns;\n wire pass_open_bank_r_lcl_reg;\n wire pass_open_bank_r_lcl_reg_0;\n wire pass_open_bank_r_lcl_reg_1;\n wire pre_bm_end_ns;\n wire pre_passing_open_bank_ns;\n wire pre_passing_open_bank_r_reg;\n wire pre_passing_open_bank_r_reg_0;\n wire pre_wait_ns;\n wire pre_wait_r;\n wire q_has_rd_3;\n wire [2:0]ras_timer_r;\n wire \\ras_timer_r[2]_i_4__2_n_0 ;\n wire \\ras_timer_r_reg[0]_0 ;\n wire \\ras_timer_r_reg[1]_0 ;\n wire \\ras_timer_r_reg[2]_0 ;\n wire ras_timer_zero_ns;\n wire ras_timer_zero_r;\n wire ras_timer_zero_r_reg_0;\n wire \\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ;\n wire rcd_active_r;\n wire \\rcd_timer_gt_2.rcd_timer_r[0]_i_1__0_n_0 ;\n wire [0:0]rd_this_rank_r;\n wire rd_wr_r_lcl_reg;\n wire rd_wr_r_lcl_reg_0;\n wire req_bank_rdy_ns;\n wire req_bank_rdy_r;\n wire req_priority_r_reg;\n wire req_wr_r_lcl_reg;\n wire \\rnk_config_strobe_r_reg[0] ;\n wire \\rp_timer.rp_timer_r[0]_i_1__0_n_0 ;\n wire \\rp_timer.rp_timer_r[1]_i_1__0_n_0 ;\n wire [0:0]rp_timer_ns;\n wire [1:0]rp_timer_r;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire rstdiv0_sync_r1_reg_rep__22;\n wire \\rtp_timer_r[0]_i_1__0_n_0 ;\n wire start_pre;\n wire start_wtp_timer0;\n wire [2:0]starve_limit_cntr_r;\n wire starve_limit_cntr_r0;\n wire \\starve_limit_cntr_r[0]_i_1__0_n_0 ;\n wire \\starve_limit_cntr_r[1]_i_1__0_n_0 ;\n wire \\starve_limit_cntr_r[2]_i_1__0_n_0 ;\n wire \\starve_limit_cntr_r_reg[2]_0 ;\n wire tail_r_24;\n wire [0:0]wr_this_rank_r;\n\n FDRE \\act_this_rank_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\act_this_rank_r_reg[0]_0 ),\n .Q(act_this_rank_r),\n .R(1'b0));\n FDRE act_wait_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(act_wait_ns),\n .Q(\\act_this_rank_r_reg[0]_0 ),\n .R(1'b0));\n FDRE bm_end_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(p_91_out),\n .Q(bm_end_r1_0),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1073\" *) \n LUT4 #(\n .INIT(16'hFFBA)) \n col_wait_r_i_1__2\n (.I0(rcd_active_r),\n .I1(\\grant_r_reg[3]_0 [0]),\n .I2(\\starve_limit_cntr_r_reg[2]_0 ),\n .I3(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ),\n .O(col_wait_r_i_1__2_n_0));\n FDRE col_wait_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(col_wait_r_i_1__2_n_0),\n .Q(\\starve_limit_cntr_r_reg[2]_0 ),\n .R(SR));\n LUT5 #(\n .INIT(32'h0000FB00)) \n demand_priority_r_i_1__1\n (.I0(demand_priority_r_reg_0),\n .I1(demand_priority_r_i_2__1_n_0),\n .I2(req_priority_r_reg),\n .I3(idle_r_lcl_reg),\n .I4(demand_priority_r_i_4__2_n_0),\n .O(demand_priority_ns));\n LUT6 #(\n .INIT(64'hFF2FFFFFFFFFFFFF)) \n demand_priority_r_i_2__1\n (.I0(req_wr_r_lcl_reg),\n .I1(q_has_rd_3),\n .I2(req_bank_rdy_r),\n .I3(\\grant_r_reg[3]_0 [0]),\n .I4(granted_col_r_reg),\n .I5(demand_priority_r_i_5__0_n_0),\n .O(demand_priority_r_i_2__1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1073\" *) \n LUT4 #(\n .INIT(16'h0051)) \n demand_priority_r_i_4__2\n (.I0(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ),\n .I1(\\starve_limit_cntr_r_reg[2]_0 ),\n .I2(\\grant_r_reg[3]_0 [0]),\n .I3(rcd_active_r),\n .O(demand_priority_r_i_4__2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1075\" *) \n LUT3 #(\n .INIT(8'h80)) \n demand_priority_r_i_5__0\n (.I0(starve_limit_cntr_r[2]),\n .I1(starve_limit_cntr_r[1]),\n .I2(starve_limit_cntr_r[0]),\n .O(demand_priority_r_i_5__0_n_0));\n FDRE demand_priority_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(demand_priority_ns),\n .Q(demand_priority_r_reg_0),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hD0D0D0D0D0DDD0D0)) \n demanded_prior_r_i_1\n (.I0(demand_priority_r_reg_0),\n .I1(demanded_prior_r_reg_0),\n .I2(demanded_prior_r_reg_1),\n .I3(\\grant_r_reg[3]_0 [1]),\n .I4(demand_priority_r_reg_1),\n .I5(demanded_prior_r_reg_2),\n .O(demanded_prior_ns));\n FDRE demanded_prior_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(demanded_prior_ns),\n .Q(demanded_prior_r_reg_0),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1069\" *) \n LUT4 #(\n .INIT(16'h1000)) \n \\grant_r[1]_i_4__0 \n (.I0(auto_pre_r_lcl_reg_1),\n .I1(\\grant_r_reg[1]_0 ),\n .I2(pre_wait_r),\n .I3(ras_timer_zero_r),\n .O(\\grant_r_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair1070\" *) \n LUT5 #(\n .INIT(32'h00000080)) \n \\grant_r[2]_i_2__0 \n (.I0(\\last_master_r_reg[0] ),\n .I1(ras_timer_zero_r),\n .I2(pre_wait_r),\n .I3(\\grant_r_reg[1]_0 ),\n .I4(auto_pre_r_lcl_reg_1),\n .O(\\grant_r_reg[2]_0 ));\n LUT5 #(\n .INIT(32'h0000FFF7)) \n \\grant_r[2]_i_3__0 \n (.I0(ras_timer_zero_r),\n .I1(pre_wait_r),\n .I2(\\grant_r_reg[1]_0 ),\n .I3(auto_pre_r_lcl_reg_1),\n .I4(auto_pre_r_lcl_reg_0),\n .O(\\grant_r_reg[2] ));\n (* SOFT_HLUTNM = \"soft_lutpair1071\" *) \n LUT3 #(\n .INIT(8'hFB)) \n \\grant_r[3]_i_15 \n (.I0(\\grant_r_reg[3]_0 [0]),\n .I1(demand_priority_r_reg_0),\n .I2(demanded_prior_r_reg_0),\n .O(\\grant_r_reg[3] ));\n (* SOFT_HLUTNM = \"soft_lutpair1071\" *) \n LUT5 #(\n .INIT(32'hBBBBBABB)) \n i___34_i_4\n (.I0(demand_priority_r_reg_1),\n .I1(demanded_prior_r_reg_1),\n .I2(\\grant_r_reg[3]_0 [0]),\n .I3(demand_priority_r_reg_0),\n .I4(demanded_prior_r_reg_0),\n .O(\\rnk_config_strobe_r_reg[0] ));\n LUT6 #(\n .INIT(64'h8888888880888080)) \n i___7_i_1\n (.I0(accept_r_reg),\n .I1(tail_r_24),\n .I2(rcd_active_r),\n .I3(\\grant_r_reg[3]_0 [0]),\n .I4(\\starve_limit_cntr_r_reg[2]_0 ),\n .I5(\\act_this_rank_r_reg[0]_0 ),\n .O(auto_pre_r_lcl_reg));\n FDRE #(\n .INIT(1'b0)) \n ofs_rdy_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(ofs_rdy_r0),\n .Q(ofs_rdy_r),\n .R(SR));\n LUT6 #(\n .INIT(64'hABAAAAAAFFFFFFFF)) \n \\pre_4_1_1T_arb.granted_pre_r_i_1 \n (.I0(auto_pre_r_lcl_reg_0),\n .I1(auto_pre_r_lcl_reg_1),\n .I2(\\grant_r_reg[1]_0 ),\n .I3(pre_wait_r),\n .I4(ras_timer_zero_r),\n .I5(ras_timer_zero_r_reg_0),\n .O(granted_pre_ns));\n (* SOFT_HLUTNM = \"soft_lutpair1074\" *) \n LUT3 #(\n .INIT(8'hBA)) \n pre_bm_end_r_i_1\n (.I0(pre_passing_open_bank_ns),\n .I1(rp_timer_r[1]),\n .I2(rp_timer_r[0]),\n .O(pre_bm_end_ns));\n LUT6 #(\n .INIT(64'hAAA8AAAAAAA8AAA8)) \n pre_passing_open_bank_r_i_1\n (.I0(pass_open_bank_ns),\n .I1(\\grant_r_reg[3]_0 [0]),\n .I2(pre_passing_open_bank_r_reg),\n .I3(pre_passing_open_bank_r_reg_0),\n .I4(ras_timer_zero_r),\n .I5(pre_wait_r),\n .O(pre_passing_open_bank_ns));\n LUT6 #(\n .INIT(64'h0040555500400040)) \n pre_wait_r_i_1\n (.I0(pass_open_bank_ns),\n .I1(pass_open_bank_r_lcl_reg),\n .I2(pre_passing_open_bank_r_reg_0),\n .I3(pre_passing_open_bank_r_reg),\n .I4(rp_timer_ns),\n .I5(pre_wait_r),\n .O(pre_wait_ns));\n (* SOFT_HLUTNM = \"soft_lutpair1069\" *) \n LUT5 #(\n .INIT(32'hEAEAEAAA)) \n pre_wait_r_i_3__0\n (.I0(rstdiv0_sync_r1_reg_rep__22),\n .I1(ras_timer_zero_r),\n .I2(pre_wait_r),\n .I3(\\grant_r_reg[1]_0 ),\n .I4(auto_pre_r_lcl_reg_1),\n .O(rp_timer_ns));\n FDRE pre_wait_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pre_wait_ns),\n .Q(pre_wait_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h000000000E0E000E)) \n \\ras_timer_r[0]_i_3__2 \n (.I0(ras_timer_r[1]),\n .I1(ras_timer_r[2]),\n .I2(ras_timer_r[0]),\n .I3(\\grant_r_reg[3]_0 [0]),\n .I4(rd_wr_r_lcl_reg),\n .I5(bm_end_r1_reg_0),\n .O(\\ras_timer_r_reg[0]_0 ));\n LUT6 #(\n .INIT(64'hEEFFFFEFEEEEEEEE)) \n \\ras_timer_r[1]_i_2__2 \n (.I0(bm_end_r1_0),\n .I1(rstdiv0_sync_r1_reg_rep__22),\n .I2(ras_timer_r[2]),\n .I3(ras_timer_r[1]),\n .I4(ras_timer_r[0]),\n .I5(\\ras_timer_r[2]_i_4__2_n_0 ),\n .O(\\ras_timer_r_reg[1]_0 ));\n LUT6 #(\n .INIT(64'h000000000000DDD5)) \n \\ras_timer_r[2]_i_3__2 \n (.I0(\\ras_timer_r[2]_i_4__2_n_0 ),\n .I1(ras_timer_r[2]),\n .I2(ras_timer_r[1]),\n .I3(ras_timer_r[0]),\n .I4(bm_end_r1_0),\n .I5(rstdiv0_sync_r1_reg_rep__22),\n .O(\\ras_timer_r_reg[2]_0 ));\n LUT6 #(\n .INIT(64'hDDDDDDD0DDDDDDDD)) \n \\ras_timer_r[2]_i_4__2 \n (.I0(\\grant_r_reg[3]_0 [0]),\n .I1(rd_wr_r_lcl_reg),\n .I2(ras_timer_r[2]),\n .I3(ras_timer_r[1]),\n .I4(ras_timer_r[0]),\n .I5(\\rcd_timer_gt_2.rcd_timer_r[0]_i_1__0_n_0 ),\n .O(\\ras_timer_r[2]_i_4__2_n_0 ));\n FDRE \\ras_timer_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(D[0]),\n .Q(ras_timer_r[0]),\n .R(1'b0));\n FDRE \\ras_timer_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(D[1]),\n .Q(ras_timer_r[1]),\n .R(1'b0));\n FDRE \\ras_timer_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(D[2]),\n .Q(ras_timer_r[2]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFFF1000FFFF1100)) \n ras_timer_zero_r_i_1__2\n (.I0(ras_timer_r[1]),\n .I1(ras_timer_r[2]),\n .I2(ras_timer_r[0]),\n .I3(rd_wr_r_lcl_reg_0),\n .I4(bm_end_r1_reg_0),\n .I5(\\rcd_timer_gt_2.rcd_timer_r[0]_i_1__0_n_0 ),\n .O(ras_timer_zero_ns));\n FDRE ras_timer_zero_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(ras_timer_zero_ns),\n .Q(ras_timer_zero_r),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h8)) \n \\rcd_timer_gt_2.rcd_timer_r[0]_i_1__0 \n (.I0(\\act_this_rank_r_reg[0]_0 ),\n .I1(\\grant_r_reg[1]_1 ),\n .O(\\rcd_timer_gt_2.rcd_timer_r[0]_i_1__0_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rcd_timer_gt_2.rcd_timer_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rcd_timer_gt_2.rcd_timer_r[0]_i_1__0_n_0 ),\n .Q(rcd_active_r),\n .R(SR));\n FDRE \\rd_this_rank_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_wr_r_lcl_reg),\n .Q(rd_this_rank_r),\n .R(1'b0));\n FDRE req_bank_rdy_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(req_bank_rdy_ns),\n .Q(req_bank_rdy_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1074\" *) \n LUT4 #(\n .INIT(16'h0004)) \n \\rp_timer.rp_timer_r[0]_i_1__0 \n (.I0(rp_timer_r[0]),\n .I1(rp_timer_r[1]),\n .I2(start_pre),\n .I3(rstdiv0_sync_r1_reg_rep__21),\n .O(\\rp_timer.rp_timer_r[0]_i_1__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1070\" *) \n LUT4 #(\n .INIT(16'hE000)) \n \\rp_timer.rp_timer_r[0]_i_2__0 \n (.I0(auto_pre_r_lcl_reg_1),\n .I1(\\grant_r_reg[1]_0 ),\n .I2(pre_wait_r),\n .I3(ras_timer_zero_r),\n .O(start_pre));\n LUT6 #(\n .INIT(64'hF888F888F8888888)) \n \\rp_timer.rp_timer_r[1]_i_1__0 \n (.I0(rp_timer_r[1]),\n .I1(rp_timer_r[0]),\n .I2(ras_timer_zero_r),\n .I3(pre_wait_r),\n .I4(\\grant_r_reg[1]_0 ),\n .I5(auto_pre_r_lcl_reg_1),\n .O(\\rp_timer.rp_timer_r[1]_i_1__0_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rp_timer.rp_timer_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rp_timer.rp_timer_r[0]_i_1__0_n_0 ),\n .Q(rp_timer_r[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rp_timer.rp_timer_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rp_timer.rp_timer_r[1]_i_1__0_n_0 ),\n .Q(rp_timer_r[1]),\n .R(rstdiv0_sync_r1_reg_rep__0));\n LUT4 #(\n .INIT(16'h0010)) \n \\rtp_timer_r[0]_i_1__0 \n (.I0(rstdiv0_sync_r1_reg_rep__20),\n .I1(pass_open_bank_r_lcl_reg_0),\n .I2(pre_passing_open_bank_r_reg),\n .I3(pre_passing_open_bank_r_reg_0),\n .O(\\rtp_timer_r[0]_i_1__0_n_0 ));\n FDRE \\rtp_timer_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rtp_timer_r[0]_i_1__0_n_0 ),\n .Q(pre_passing_open_bank_r_reg_0),\n .R(1'b0));\n FDRE \\rtp_timer_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(pass_open_bank_r_lcl_reg_1),\n .Q(pre_passing_open_bank_r_reg),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1075\" *) \n LUT3 #(\n .INIT(8'h60)) \n \\starve_limit_cntr_r[0]_i_1__0 \n (.I0(starve_limit_cntr_r[0]),\n .I1(starve_limit_cntr_r0),\n .I2(\\starve_limit_cntr_r_reg[2]_0 ),\n .O(\\starve_limit_cntr_r[0]_i_1__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1072\" *) \n LUT4 #(\n .INIT(16'h6A00)) \n \\starve_limit_cntr_r[1]_i_1__0 \n (.I0(starve_limit_cntr_r[1]),\n .I1(starve_limit_cntr_r0),\n .I2(starve_limit_cntr_r[0]),\n .I3(\\starve_limit_cntr_r_reg[2]_0 ),\n .O(\\starve_limit_cntr_r[1]_i_1__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1072\" *) \n LUT5 #(\n .INIT(32'h6AAA0000)) \n \\starve_limit_cntr_r[2]_i_1__0 \n (.I0(starve_limit_cntr_r[2]),\n .I1(starve_limit_cntr_r0),\n .I2(starve_limit_cntr_r[0]),\n .I3(starve_limit_cntr_r[1]),\n .I4(\\starve_limit_cntr_r_reg[2]_0 ),\n .O(\\starve_limit_cntr_r[2]_i_1__0_n_0 ));\n LUT6 #(\n .INIT(64'h00007F0000000000)) \n \\starve_limit_cntr_r[2]_i_2__0 \n (.I0(starve_limit_cntr_r[0]),\n .I1(starve_limit_cntr_r[1]),\n .I2(starve_limit_cntr_r[2]),\n .I3(granted_col_r_reg),\n .I4(\\grant_r_reg[3]_0 [0]),\n .I5(req_bank_rdy_r),\n .O(starve_limit_cntr_r0));\n FDRE \\starve_limit_cntr_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\starve_limit_cntr_r[0]_i_1__0_n_0 ),\n .Q(starve_limit_cntr_r[0]),\n .R(1'b0));\n FDRE \\starve_limit_cntr_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\starve_limit_cntr_r[1]_i_1__0_n_0 ),\n .Q(starve_limit_cntr_r[1]),\n .R(1'b0));\n FDRE \\starve_limit_cntr_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\starve_limit_cntr_r[2]_i_1__0_n_0 ),\n .Q(starve_limit_cntr_r[2]),\n .R(1'b0));\n FDRE \\wr_this_rank_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(start_wtp_timer0),\n .Q(wr_this_rank_r),\n .R(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_bank_state\" *) \nmodule ddr3_if_mig_7series_v4_0_bank_state__parameterized1\n (\\ras_timer_r_reg[2]_0 ,\n \\act_this_rank_r_reg[0]_0 ,\n \\rp_timer.rp_timer_r_reg[1]_0 ,\n pre_wait_r,\n act_this_rank_r,\n demand_priority_r_reg_0,\n demanded_prior_r_reg_0,\n override_demand_r,\n ofs_rdy_r,\n wr_this_rank_r,\n rd_this_rank_r,\n \\starve_limit_cntr_r_reg[2]_0 ,\n ofs_rdy_r0,\n ofs_rdy_r0_0,\n ofs_rdy_r0_1,\n \\ras_timer_r_reg[0]_0 ,\n \\ras_timer_r_reg[1]_0 ,\n \\ras_timer_r_reg[2]_1 ,\n pre_bm_end_ns,\n pre_passing_open_bank_ns,\n auto_pre_r_lcl_reg,\n \\grant_r_reg[2] ,\n \\rnk_config_strobe_r_reg[0] ,\n p_52_out,\n CLK,\n act_wait_ns,\n req_bank_rdy_ns,\n override_demand_ns,\n SR,\n start_wtp_timer0,\n rd_wr_r_lcl_reg,\n rstdiv0_sync_r1_reg_rep__0,\n of_ctl_full_v,\n phy_mc_ctl_full,\n \\entry_cnt_reg[2] ,\n \\entry_cnt_reg[2]_0 ,\n rd_wr_r_lcl_reg_0,\n rd_wr_r_lcl_reg_1,\n rd_wr_r,\n rd_wr_r_lcl_reg_2,\n bm_end_r1_reg_0,\n rstdiv0_sync_r1_reg_rep__21,\n \\grant_r_reg[2]_0 ,\n req_priority_r_reg,\n idle_r_lcl_reg,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ,\n pass_open_bank_ns,\n rtp_timer_ns1_7,\n rb_hit_busy_r_reg,\n tail_r_26,\n \\grant_r_reg[2]_1 ,\n auto_pre_r_lcl_reg_0,\n \\grant_r_reg[2]_2 ,\n rstdiv0_sync_r1_reg_rep__22,\n demand_priority_r,\n demanded_prior_r_reg_1,\n demanded_prior_r,\n req_wr_r_lcl_reg,\n q_has_rd_10,\n granted_col_r_reg,\n D,\n pass_open_bank_r_lcl_reg,\n rstdiv0_sync_r1_reg_rep__20);\n output \\ras_timer_r_reg[2]_0 ;\n output \\act_this_rank_r_reg[0]_0 ;\n output \\rp_timer.rp_timer_r_reg[1]_0 ;\n output pre_wait_r;\n output [0:0]act_this_rank_r;\n output demand_priority_r_reg_0;\n output demanded_prior_r_reg_0;\n output override_demand_r;\n output ofs_rdy_r;\n output [0:0]wr_this_rank_r;\n output [0:0]rd_this_rank_r;\n output \\starve_limit_cntr_r_reg[2]_0 ;\n output ofs_rdy_r0;\n output ofs_rdy_r0_0;\n output ofs_rdy_r0_1;\n output \\ras_timer_r_reg[0]_0 ;\n output \\ras_timer_r_reg[1]_0 ;\n output \\ras_timer_r_reg[2]_1 ;\n output pre_bm_end_ns;\n output pre_passing_open_bank_ns;\n output auto_pre_r_lcl_reg;\n output \\grant_r_reg[2] ;\n output \\rnk_config_strobe_r_reg[0] ;\n input p_52_out;\n input CLK;\n input act_wait_ns;\n input req_bank_rdy_ns;\n input override_demand_ns;\n input [0:0]SR;\n input start_wtp_timer0;\n input rd_wr_r_lcl_reg;\n input rstdiv0_sync_r1_reg_rep__0;\n input [0:0]of_ctl_full_v;\n input phy_mc_ctl_full;\n input \\entry_cnt_reg[2] ;\n input \\entry_cnt_reg[2]_0 ;\n input rd_wr_r_lcl_reg_0;\n input rd_wr_r_lcl_reg_1;\n input [0:0]rd_wr_r;\n input rd_wr_r_lcl_reg_2;\n input bm_end_r1_reg_0;\n input rstdiv0_sync_r1_reg_rep__21;\n input [1:0]\\grant_r_reg[2]_0 ;\n input req_priority_r_reg;\n input idle_r_lcl_reg;\n input \\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;\n input pass_open_bank_ns;\n input rtp_timer_ns1_7;\n input rb_hit_busy_r_reg;\n input tail_r_26;\n input [0:0]\\grant_r_reg[2]_1 ;\n input auto_pre_r_lcl_reg_0;\n input [0:0]\\grant_r_reg[2]_2 ;\n input rstdiv0_sync_r1_reg_rep__22;\n input demand_priority_r;\n input demanded_prior_r_reg_1;\n input demanded_prior_r;\n input req_wr_r_lcl_reg;\n input q_has_rd_10;\n input granted_col_r_reg;\n input [2:0]D;\n input pass_open_bank_r_lcl_reg;\n input rstdiv0_sync_r1_reg_rep__20;\n\n wire CLK;\n wire [2:0]D;\n wire [0:0]SR;\n wire [0:0]act_this_rank_r;\n wire \\act_this_rank_r_reg[0]_0 ;\n wire act_wait_ns;\n wire auto_pre_r_lcl_reg;\n wire auto_pre_r_lcl_reg_0;\n wire bm_end_r1_reg_0;\n wire col_wait_r_i_1_n_0;\n wire demand_priority_ns;\n wire demand_priority_r;\n wire demand_priority_r_i_2__2_n_0;\n wire demand_priority_r_i_4_n_0;\n wire demand_priority_r_i_5__1_n_0;\n wire demand_priority_r_reg_0;\n wire demanded_prior_ns;\n wire demanded_prior_r;\n wire demanded_prior_r_reg_0;\n wire demanded_prior_r_reg_1;\n wire \\entry_cnt_reg[2] ;\n wire \\entry_cnt_reg[2]_0 ;\n wire \\grant_r_reg[2] ;\n wire [1:0]\\grant_r_reg[2]_0 ;\n wire [0:0]\\grant_r_reg[2]_1 ;\n wire [0:0]\\grant_r_reg[2]_2 ;\n wire granted_col_r_reg;\n wire idle_r_lcl_reg;\n wire [0:0]of_ctl_full_v;\n wire ofs_rdy_r;\n wire ofs_rdy_r0;\n wire ofs_rdy_r0_0;\n wire ofs_rdy_r0_1;\n wire ofs_rdy_r0_2;\n wire override_demand_ns;\n wire override_demand_r;\n wire p_52_out;\n wire pass_open_bank_ns;\n wire pass_open_bank_r_lcl_reg;\n wire phy_mc_cmd_full_r;\n wire phy_mc_ctl_full;\n wire phy_mc_ctl_full_r;\n wire pre_bm_end_ns;\n wire pre_passing_open_bank_ns;\n wire pre_wait_ns;\n wire pre_wait_r;\n wire q_has_rd_10;\n wire [2:0]ras_timer_r;\n wire \\ras_timer_r[2]_i_4_n_0 ;\n wire \\ras_timer_r_reg[0]_0 ;\n wire \\ras_timer_r_reg[1]_0 ;\n wire \\ras_timer_r_reg[2]_0 ;\n wire \\ras_timer_r_reg[2]_1 ;\n wire ras_timer_zero_ns;\n wire \\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;\n wire rb_hit_busy_r_reg;\n wire rcd_active_r;\n wire \\rcd_timer_gt_2.rcd_timer_r[0]_i_1__1_n_0 ;\n wire [0:0]rd_this_rank_r;\n wire [0:0]rd_wr_r;\n wire rd_wr_r_lcl_reg;\n wire rd_wr_r_lcl_reg_0;\n wire rd_wr_r_lcl_reg_1;\n wire rd_wr_r_lcl_reg_2;\n wire req_bank_rdy_ns;\n wire req_bank_rdy_r;\n wire req_priority_r_reg;\n wire req_wr_r_lcl_reg;\n wire \\rnk_config_strobe_r_reg[0] ;\n wire \\rp_timer.rp_timer_r[0]_i_1__1_n_0 ;\n wire \\rp_timer.rp_timer_r[1]_i_1__1_n_0 ;\n wire \\rp_timer.rp_timer_r_reg[1]_0 ;\n wire [0:0]rp_timer_ns;\n wire [1:0]rp_timer_r;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire rstdiv0_sync_r1_reg_rep__22;\n wire rtp_timer_ns1_7;\n wire [1:0]rtp_timer_r;\n wire \\rtp_timer_r[0]_i_1__1_n_0 ;\n wire \\rtp_timer_r[1]_i_1__0_n_0 ;\n wire start_pre;\n wire start_wtp_timer0;\n wire [2:0]starve_limit_cntr_r;\n wire starve_limit_cntr_r0;\n wire \\starve_limit_cntr_r[0]_i_1__1_n_0 ;\n wire \\starve_limit_cntr_r[1]_i_1__1_n_0 ;\n wire \\starve_limit_cntr_r[2]_i_1__1_n_0 ;\n wire \\starve_limit_cntr_r_reg[2]_0 ;\n wire tail_r_26;\n wire [0:0]wr_this_rank_r;\n\n FDRE \\act_this_rank_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\act_this_rank_r_reg[0]_0 ),\n .Q(act_this_rank_r),\n .R(1'b0));\n FDRE act_wait_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(act_wait_ns),\n .Q(\\act_this_rank_r_reg[0]_0 ),\n .R(1'b0));\n FDRE bm_end_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(p_52_out),\n .Q(\\ras_timer_r_reg[2]_0 ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1084\" *) \n LUT4 #(\n .INIT(16'hFFBA)) \n col_wait_r_i_1\n (.I0(rcd_active_r),\n .I1(\\grant_r_reg[2]_0 [1]),\n .I2(\\starve_limit_cntr_r_reg[2]_0 ),\n .I3(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ),\n .O(col_wait_r_i_1_n_0));\n FDRE col_wait_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(col_wait_r_i_1_n_0),\n .Q(\\starve_limit_cntr_r_reg[2]_0 ),\n .R(SR));\n LUT5 #(\n .INIT(32'h0000FB00)) \n demand_priority_r_i_1__0\n (.I0(demand_priority_r_reg_0),\n .I1(demand_priority_r_i_2__2_n_0),\n .I2(req_priority_r_reg),\n .I3(idle_r_lcl_reg),\n .I4(demand_priority_r_i_4_n_0),\n .O(demand_priority_ns));\n LUT6 #(\n .INIT(64'hFF2FFFFFFFFFFFFF)) \n demand_priority_r_i_2__2\n (.I0(req_wr_r_lcl_reg),\n .I1(q_has_rd_10),\n .I2(req_bank_rdy_r),\n .I3(\\grant_r_reg[2]_0 [1]),\n .I4(granted_col_r_reg),\n .I5(demand_priority_r_i_5__1_n_0),\n .O(demand_priority_r_i_2__2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1084\" *) \n LUT4 #(\n .INIT(16'h0051)) \n demand_priority_r_i_4\n (.I0(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ),\n .I1(\\starve_limit_cntr_r_reg[2]_0 ),\n .I2(\\grant_r_reg[2]_0 [1]),\n .I3(rcd_active_r),\n .O(demand_priority_r_i_4_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1085\" *) \n LUT3 #(\n .INIT(8'h80)) \n demand_priority_r_i_5__1\n (.I0(starve_limit_cntr_r[2]),\n .I1(starve_limit_cntr_r[1]),\n .I2(starve_limit_cntr_r[0]),\n .O(demand_priority_r_i_5__1_n_0));\n FDRE demand_priority_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(demand_priority_ns),\n .Q(demand_priority_r_reg_0),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hD0D0D0D0D0DDD0D0)) \n demanded_prior_r_i_1__2\n (.I0(demand_priority_r_reg_0),\n .I1(demanded_prior_r_reg_0),\n .I2(demanded_prior_r_reg_1),\n .I3(\\grant_r_reg[2]_0 [0]),\n .I4(demand_priority_r),\n .I5(demanded_prior_r),\n .O(demanded_prior_ns));\n FDRE demanded_prior_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(demanded_prior_ns),\n .Q(demanded_prior_r_reg_0),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1081\" *) \n LUT4 #(\n .INIT(16'h1000)) \n \\grant_r[3]_i_3__1 \n (.I0(auto_pre_r_lcl_reg_0),\n .I1(\\grant_r_reg[2]_2 ),\n .I2(pre_wait_r),\n .I3(\\rp_timer.rp_timer_r_reg[1]_0 ),\n .O(\\grant_r_reg[2] ));\n LUT6 #(\n .INIT(64'h8888888880888080)) \n i___11_i_1\n (.I0(rb_hit_busy_r_reg),\n .I1(tail_r_26),\n .I2(rcd_active_r),\n .I3(\\grant_r_reg[2]_0 [1]),\n .I4(\\starve_limit_cntr_r_reg[2]_0 ),\n .I5(\\act_this_rank_r_reg[0]_0 ),\n .O(auto_pre_r_lcl_reg));\n LUT5 #(\n .INIT(32'h000F0001)) \n ofs_rdy_r_i_1__0\n (.I0(\\entry_cnt_reg[2] ),\n .I1(\\entry_cnt_reg[2]_0 ),\n .I2(phy_mc_ctl_full_r),\n .I3(phy_mc_cmd_full_r),\n .I4(rd_wr_r_lcl_reg_1),\n .O(ofs_rdy_r0_0));\n LUT5 #(\n .INIT(32'h000F0001)) \n ofs_rdy_r_i_1__1\n (.I0(\\entry_cnt_reg[2] ),\n .I1(\\entry_cnt_reg[2]_0 ),\n .I2(phy_mc_ctl_full_r),\n .I3(phy_mc_cmd_full_r),\n .I4(rd_wr_r_lcl_reg),\n .O(ofs_rdy_r0_2));\n LUT5 #(\n .INIT(32'h000F0001)) \n ofs_rdy_r_i_1__2\n (.I0(\\entry_cnt_reg[2] ),\n .I1(\\entry_cnt_reg[2]_0 ),\n .I2(phy_mc_ctl_full_r),\n .I3(phy_mc_cmd_full_r),\n .I4(rd_wr_r),\n .O(ofs_rdy_r0_1));\n LUT5 #(\n .INIT(32'h000F0001)) \n ofs_rdy_r_i_2\n (.I0(\\entry_cnt_reg[2] ),\n .I1(\\entry_cnt_reg[2]_0 ),\n .I2(phy_mc_ctl_full_r),\n .I3(phy_mc_cmd_full_r),\n .I4(rd_wr_r_lcl_reg_0),\n .O(ofs_rdy_r0));\n FDRE #(\n .INIT(1'b0)) \n ofs_rdy_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(ofs_rdy_r0_2),\n .Q(ofs_rdy_r),\n .R(SR));\n FDRE override_demand_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(override_demand_ns),\n .Q(override_demand_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n phy_mc_cmd_full_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(of_ctl_full_v),\n .Q(phy_mc_cmd_full_r),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE #(\n .INIT(1'b0)) \n phy_mc_ctl_full_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(phy_mc_ctl_full),\n .Q(phy_mc_ctl_full_r),\n .R(SR));\n (* SOFT_HLUTNM = \"soft_lutpair1083\" *) \n LUT3 #(\n .INIT(8'hBA)) \n pre_bm_end_r_i_1__2\n (.I0(pre_passing_open_bank_ns),\n .I1(rp_timer_r[1]),\n .I2(rp_timer_r[0]),\n .O(pre_bm_end_ns));\n LUT6 #(\n .INIT(64'hAAA8AAAAAAA8AAA8)) \n pre_passing_open_bank_r_i_1__2\n (.I0(pass_open_bank_ns),\n .I1(\\grant_r_reg[2]_0 [1]),\n .I2(rtp_timer_r[1]),\n .I3(rtp_timer_r[0]),\n .I4(\\rp_timer.rp_timer_r_reg[1]_0 ),\n .I5(pre_wait_r),\n .O(pre_passing_open_bank_ns));\n LUT6 #(\n .INIT(64'h0404040404550404)) \n pre_wait_r_i_1__2\n (.I0(pass_open_bank_ns),\n .I1(pre_wait_r),\n .I2(rp_timer_ns),\n .I3(rtp_timer_ns1_7),\n .I4(rtp_timer_r[0]),\n .I5(rtp_timer_r[1]),\n .O(pre_wait_ns));\n (* SOFT_HLUTNM = \"soft_lutpair1081\" *) \n LUT5 #(\n .INIT(32'hEAEAEAAA)) \n pre_wait_r_i_2__1\n (.I0(rstdiv0_sync_r1_reg_rep__22),\n .I1(\\rp_timer.rp_timer_r_reg[1]_0 ),\n .I2(pre_wait_r),\n .I3(\\grant_r_reg[2]_2 ),\n .I4(auto_pre_r_lcl_reg_0),\n .O(rp_timer_ns));\n FDRE pre_wait_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pre_wait_ns),\n .Q(pre_wait_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0000000000000E00)) \n \\ras_timer_r[0]_i_3 \n (.I0(ras_timer_r[1]),\n .I1(ras_timer_r[2]),\n .I2(ras_timer_r[0]),\n .I3(rd_wr_r_lcl_reg_2),\n .I4(rstdiv0_sync_r1_reg_rep__21),\n .I5(\\ras_timer_r_reg[2]_0 ),\n .O(\\ras_timer_r_reg[0]_0 ));\n LUT6 #(\n .INIT(64'h1100001011111111)) \n \\ras_timer_r[1]_i_3__0 \n (.I0(\\ras_timer_r_reg[2]_0 ),\n .I1(rstdiv0_sync_r1_reg_rep__21),\n .I2(ras_timer_r[2]),\n .I3(ras_timer_r[1]),\n .I4(ras_timer_r[0]),\n .I5(\\ras_timer_r[2]_i_4_n_0 ),\n .O(\\ras_timer_r_reg[1]_0 ));\n LUT6 #(\n .INIT(64'h000000000000DDD5)) \n \\ras_timer_r[2]_i_3 \n (.I0(\\ras_timer_r[2]_i_4_n_0 ),\n .I1(ras_timer_r[2]),\n .I2(ras_timer_r[1]),\n .I3(ras_timer_r[0]),\n .I4(\\ras_timer_r_reg[2]_0 ),\n .I5(rstdiv0_sync_r1_reg_rep__21),\n .O(\\ras_timer_r_reg[2]_1 ));\n LUT6 #(\n .INIT(64'hDDDDDDD0DDDDDDDD)) \n \\ras_timer_r[2]_i_4 \n (.I0(\\grant_r_reg[2]_0 [1]),\n .I1(rd_wr_r_lcl_reg),\n .I2(ras_timer_r[2]),\n .I3(ras_timer_r[1]),\n .I4(ras_timer_r[0]),\n .I5(\\rcd_timer_gt_2.rcd_timer_r[0]_i_1__1_n_0 ),\n .O(\\ras_timer_r[2]_i_4_n_0 ));\n FDRE \\ras_timer_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(D[0]),\n .Q(ras_timer_r[0]),\n .R(1'b0));\n FDRE \\ras_timer_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(D[1]),\n .Q(ras_timer_r[1]),\n .R(1'b0));\n FDRE \\ras_timer_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(D[2]),\n .Q(ras_timer_r[2]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFFF1000FFFF1100)) \n ras_timer_zero_r_i_1\n (.I0(ras_timer_r[1]),\n .I1(ras_timer_r[2]),\n .I2(ras_timer_r[0]),\n .I3(rd_wr_r_lcl_reg_2),\n .I4(bm_end_r1_reg_0),\n .I5(\\rcd_timer_gt_2.rcd_timer_r[0]_i_1__1_n_0 ),\n .O(ras_timer_zero_ns));\n FDRE ras_timer_zero_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(ras_timer_zero_ns),\n .Q(\\rp_timer.rp_timer_r_reg[1]_0 ),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h8)) \n \\rcd_timer_gt_2.rcd_timer_r[0]_i_1__1 \n (.I0(\\act_this_rank_r_reg[0]_0 ),\n .I1(\\grant_r_reg[2]_1 ),\n .O(\\rcd_timer_gt_2.rcd_timer_r[0]_i_1__1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rcd_timer_gt_2.rcd_timer_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rcd_timer_gt_2.rcd_timer_r[0]_i_1__1_n_0 ),\n .Q(rcd_active_r),\n .R(SR));\n FDRE \\rd_this_rank_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_wr_r_lcl_reg),\n .Q(rd_this_rank_r),\n .R(1'b0));\n FDRE req_bank_rdy_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(req_bank_rdy_ns),\n .Q(req_bank_rdy_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hAAAAFFEF)) \n \\rnk_config_strobe_r[0]_i_4 \n (.I0(demand_priority_r),\n .I1(\\grant_r_reg[2]_0 [1]),\n .I2(demand_priority_r_reg_0),\n .I3(demanded_prior_r_reg_0),\n .I4(demanded_prior_r_reg_1),\n .O(\\rnk_config_strobe_r_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair1083\" *) \n LUT4 #(\n .INIT(16'h0004)) \n \\rp_timer.rp_timer_r[0]_i_1__1 \n (.I0(rp_timer_r[0]),\n .I1(rp_timer_r[1]),\n .I2(start_pre),\n .I3(rstdiv0_sync_r1_reg_rep__21),\n .O(\\rp_timer.rp_timer_r[0]_i_1__1_n_0 ));\n LUT4 #(\n .INIT(16'hE000)) \n \\rp_timer.rp_timer_r[0]_i_2__1 \n (.I0(auto_pre_r_lcl_reg_0),\n .I1(\\grant_r_reg[2]_2 ),\n .I2(pre_wait_r),\n .I3(\\rp_timer.rp_timer_r_reg[1]_0 ),\n .O(start_pre));\n LUT6 #(\n .INIT(64'hF888F888F8888888)) \n \\rp_timer.rp_timer_r[1]_i_1__1 \n (.I0(rp_timer_r[1]),\n .I1(rp_timer_r[0]),\n .I2(\\rp_timer.rp_timer_r_reg[1]_0 ),\n .I3(pre_wait_r),\n .I4(\\grant_r_reg[2]_2 ),\n .I5(auto_pre_r_lcl_reg_0),\n .O(\\rp_timer.rp_timer_r[1]_i_1__1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rp_timer.rp_timer_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rp_timer.rp_timer_r[0]_i_1__1_n_0 ),\n .Q(rp_timer_r[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rp_timer.rp_timer_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rp_timer.rp_timer_r[1]_i_1__1_n_0 ),\n .Q(rp_timer_r[1]),\n .R(rstdiv0_sync_r1_reg_rep__0));\n LUT4 #(\n .INIT(16'h0002)) \n \\rtp_timer_r[0]_i_1__1 \n (.I0(rtp_timer_r[1]),\n .I1(rtp_timer_r[0]),\n .I2(rstdiv0_sync_r1_reg_rep__20),\n .I3(pass_open_bank_r_lcl_reg),\n .O(\\rtp_timer_r[0]_i_1__1_n_0 ));\n LUT5 #(\n .INIT(32'h000000C2)) \n \\rtp_timer_r[1]_i_1__0 \n (.I0(\\grant_r_reg[2]_0 [1]),\n .I1(rtp_timer_r[1]),\n .I2(rtp_timer_r[0]),\n .I3(pass_open_bank_r_lcl_reg),\n .I4(rstdiv0_sync_r1_reg_rep__21),\n .O(\\rtp_timer_r[1]_i_1__0_n_0 ));\n FDRE \\rtp_timer_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rtp_timer_r[0]_i_1__1_n_0 ),\n .Q(rtp_timer_r[0]),\n .R(1'b0));\n FDRE \\rtp_timer_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rtp_timer_r[1]_i_1__0_n_0 ),\n .Q(rtp_timer_r[1]),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1085\" *) \n LUT3 #(\n .INIT(8'h60)) \n \\starve_limit_cntr_r[0]_i_1__1 \n (.I0(starve_limit_cntr_r[0]),\n .I1(starve_limit_cntr_r0),\n .I2(\\starve_limit_cntr_r_reg[2]_0 ),\n .O(\\starve_limit_cntr_r[0]_i_1__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1082\" *) \n LUT4 #(\n .INIT(16'h6A00)) \n \\starve_limit_cntr_r[1]_i_1__1 \n (.I0(starve_limit_cntr_r[1]),\n .I1(starve_limit_cntr_r0),\n .I2(starve_limit_cntr_r[0]),\n .I3(\\starve_limit_cntr_r_reg[2]_0 ),\n .O(\\starve_limit_cntr_r[1]_i_1__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1082\" *) \n LUT5 #(\n .INIT(32'h6AAA0000)) \n \\starve_limit_cntr_r[2]_i_1__1 \n (.I0(starve_limit_cntr_r[2]),\n .I1(starve_limit_cntr_r0),\n .I2(starve_limit_cntr_r[0]),\n .I3(starve_limit_cntr_r[1]),\n .I4(\\starve_limit_cntr_r_reg[2]_0 ),\n .O(\\starve_limit_cntr_r[2]_i_1__1_n_0 ));\n LUT6 #(\n .INIT(64'h00007F0000000000)) \n \\starve_limit_cntr_r[2]_i_2__1 \n (.I0(starve_limit_cntr_r[0]),\n .I1(starve_limit_cntr_r[1]),\n .I2(starve_limit_cntr_r[2]),\n .I3(granted_col_r_reg),\n .I4(\\grant_r_reg[2]_0 [1]),\n .I5(req_bank_rdy_r),\n .O(starve_limit_cntr_r0));\n FDRE \\starve_limit_cntr_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\starve_limit_cntr_r[0]_i_1__1_n_0 ),\n .Q(starve_limit_cntr_r[0]),\n .R(1'b0));\n FDRE \\starve_limit_cntr_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\starve_limit_cntr_r[1]_i_1__1_n_0 ),\n .Q(starve_limit_cntr_r[1]),\n .R(1'b0));\n FDRE \\starve_limit_cntr_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\starve_limit_cntr_r[2]_i_1__1_n_0 ),\n .Q(starve_limit_cntr_r[2]),\n .R(1'b0));\n FDRE \\wr_this_rank_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(start_wtp_timer0),\n .Q(wr_this_rank_r),\n .R(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_bank_state\" *) \nmodule ddr3_if_mig_7series_v4_0_bank_state__parameterized2\n (bm_end_r1_4,\n \\act_this_rank_r_reg[0]_0 ,\n ras_timer_zero_r,\n pre_wait_r,\n act_this_rank_r,\n req_bank_rdy_r,\n demand_priority_r_reg_0,\n demanded_prior_r_reg_0,\n ofs_rdy_r,\n wr_this_rank_r,\n rd_this_rank_r,\n \\starve_limit_cntr_r_reg[2]_0 ,\n \\ras_timer_r_reg[0]_0 ,\n \\ras_timer_r_reg[1]_0 ,\n \\ras_timer_r_reg[2]_0 ,\n pre_bm_end_ns,\n pre_passing_open_bank_ns,\n auto_pre_r_lcl_reg,\n \\pre_4_1_1T_arb.granted_pre_r_reg ,\n \\grant_r_reg[3] ,\n \\cmd_pipe_plus.mc_address_reg[10] ,\n \\grant_r_reg[0] ,\n \\grant_r_reg[2] ,\n demanded_prior_r_reg_1,\n \\rnk_config_strobe_r_reg[0] ,\n p_13_out,\n CLK,\n act_wait_ns,\n req_bank_rdy_ns,\n SR,\n ofs_rdy_r0,\n start_wtp_timer0,\n rd_wr_r_lcl_reg,\n req_priority_r_reg,\n idle_r_lcl_reg,\n rd_wr_r_lcl_reg_0,\n bm_end_r1_reg_0,\n \\grant_r_reg[3]_0 ,\n rstdiv0_sync_r1_reg_rep__21,\n \\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ,\n pass_open_bank_ns,\n rtp_timer_ns1_6,\n rb_hit_busy_r_reg,\n tail_r_28,\n \\grant_r_reg[3]_1 ,\n auto_pre_r_lcl_reg_0,\n auto_pre_r_lcl_reg_1,\n demanded_prior_r_reg_2,\n \\grant_r_reg[1] ,\n override_demand_r,\n rnk_config_valid_r_lcl_reg,\n \\grant_r_reg[3]_2 ,\n \\req_row_r_lcl_reg[10] ,\n \\req_row_r_lcl_reg[10]_0 ,\n row_cmd_wr,\n \\grant_r_reg[3]_3 ,\n \\last_master_r_reg[2] ,\n rstdiv0_sync_r1_reg_rep__22,\n demand_priority_r_reg_1,\n demanded_prior_r,\n req_wr_r_lcl_reg,\n q_has_rd_16,\n req_bank_rdy_r_reg_0,\n granted_col_r_reg,\n D,\n pass_open_bank_r_lcl_reg,\n rstdiv0_sync_r1_reg_rep__20,\n rstdiv0_sync_r1_reg_rep__0);\n output bm_end_r1_4;\n output \\act_this_rank_r_reg[0]_0 ;\n output ras_timer_zero_r;\n output pre_wait_r;\n output [0:0]act_this_rank_r;\n output req_bank_rdy_r;\n output demand_priority_r_reg_0;\n output demanded_prior_r_reg_0;\n output ofs_rdy_r;\n output [0:0]wr_this_rank_r;\n output [0:0]rd_this_rank_r;\n output \\starve_limit_cntr_r_reg[2]_0 ;\n output \\ras_timer_r_reg[0]_0 ;\n output \\ras_timer_r_reg[1]_0 ;\n output \\ras_timer_r_reg[2]_0 ;\n output pre_bm_end_ns;\n output pre_passing_open_bank_ns;\n output auto_pre_r_lcl_reg;\n output \\pre_4_1_1T_arb.granted_pre_r_reg ;\n output \\grant_r_reg[3] ;\n output \\cmd_pipe_plus.mc_address_reg[10] ;\n output \\grant_r_reg[0] ;\n output \\grant_r_reg[2] ;\n output demanded_prior_r_reg_1;\n output \\rnk_config_strobe_r_reg[0] ;\n input p_13_out;\n input CLK;\n input act_wait_ns;\n input req_bank_rdy_ns;\n input [0:0]SR;\n input ofs_rdy_r0;\n input start_wtp_timer0;\n input rd_wr_r_lcl_reg;\n input req_priority_r_reg;\n input idle_r_lcl_reg;\n input rd_wr_r_lcl_reg_0;\n input bm_end_r1_reg_0;\n input [1:0]\\grant_r_reg[3]_0 ;\n input rstdiv0_sync_r1_reg_rep__21;\n input \\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ;\n input pass_open_bank_ns;\n input rtp_timer_ns1_6;\n input rb_hit_busy_r_reg;\n input tail_r_28;\n input [0:0]\\grant_r_reg[3]_1 ;\n input auto_pre_r_lcl_reg_0;\n input auto_pre_r_lcl_reg_1;\n input demanded_prior_r_reg_2;\n input \\grant_r_reg[1] ;\n input override_demand_r;\n input rnk_config_valid_r_lcl_reg;\n input [0:0]\\grant_r_reg[3]_2 ;\n input [0:0]\\req_row_r_lcl_reg[10] ;\n input [0:0]\\req_row_r_lcl_reg[10]_0 ;\n input [0:0]row_cmd_wr;\n input \\grant_r_reg[3]_3 ;\n input \\last_master_r_reg[2] ;\n input rstdiv0_sync_r1_reg_rep__22;\n input demand_priority_r_reg_1;\n input demanded_prior_r;\n input req_wr_r_lcl_reg;\n input q_has_rd_16;\n input req_bank_rdy_r_reg_0;\n input granted_col_r_reg;\n input [2:0]D;\n input pass_open_bank_r_lcl_reg;\n input rstdiv0_sync_r1_reg_rep__20;\n input rstdiv0_sync_r1_reg_rep__0;\n\n wire CLK;\n wire [2:0]D;\n wire [0:0]SR;\n wire [0:0]act_this_rank_r;\n wire \\act_this_rank_r_reg[0]_0 ;\n wire act_wait_ns;\n wire auto_pre_r_lcl_reg;\n wire auto_pre_r_lcl_reg_0;\n wire auto_pre_r_lcl_reg_1;\n wire bm_end_r1_4;\n wire bm_end_r1_reg_0;\n wire \\cmd_pipe_plus.mc_address_reg[10] ;\n wire col_wait_r_i_1__1_n_0;\n wire demand_priority_ns;\n wire demand_priority_r_i_3__2_n_0;\n wire demand_priority_r_i_4__1_n_0;\n wire demand_priority_r_reg_0;\n wire demand_priority_r_reg_1;\n wire demanded_prior_ns;\n wire demanded_prior_r;\n wire demanded_prior_r_reg_0;\n wire demanded_prior_r_reg_1;\n wire demanded_prior_r_reg_2;\n wire \\grant_r_reg[0] ;\n wire \\grant_r_reg[1] ;\n wire \\grant_r_reg[2] ;\n wire \\grant_r_reg[3] ;\n wire [1:0]\\grant_r_reg[3]_0 ;\n wire [0:0]\\grant_r_reg[3]_1 ;\n wire [0:0]\\grant_r_reg[3]_2 ;\n wire \\grant_r_reg[3]_3 ;\n wire granted_col_r_reg;\n wire idle_r_lcl_reg;\n wire \\last_master_r_reg[2] ;\n wire ofs_rdy_r;\n wire ofs_rdy_r0;\n wire override_demand_r;\n wire p_13_out;\n wire pass_open_bank_ns;\n wire pass_open_bank_r_lcl_reg;\n wire \\pre_4_1_1T_arb.granted_pre_r_reg ;\n wire pre_bm_end_ns;\n wire pre_passing_open_bank_ns;\n wire pre_wait_ns;\n wire pre_wait_r;\n wire q_has_rd_16;\n wire [2:0]ras_timer_r;\n wire \\ras_timer_r[2]_i_4__0_n_0 ;\n wire \\ras_timer_r_reg[0]_0 ;\n wire \\ras_timer_r_reg[1]_0 ;\n wire \\ras_timer_r_reg[2]_0 ;\n wire ras_timer_zero_ns;\n wire ras_timer_zero_r;\n wire \\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ;\n wire rb_hit_busy_r_reg;\n wire rcd_active_r;\n wire \\rcd_timer_gt_2.rcd_timer_r[0]_i_1__2_n_0 ;\n wire [0:0]rd_this_rank_r;\n wire rd_wr_r_lcl_reg;\n wire rd_wr_r_lcl_reg_0;\n wire req_bank_rdy_ns;\n wire req_bank_rdy_r;\n wire req_bank_rdy_r_reg_0;\n wire req_priority_r_reg;\n wire [0:0]\\req_row_r_lcl_reg[10] ;\n wire [0:0]\\req_row_r_lcl_reg[10]_0 ;\n wire req_wr_r_lcl_reg;\n wire \\rnk_config_strobe_r_reg[0] ;\n wire rnk_config_valid_r_lcl_reg;\n wire [0:0]row_cmd_wr;\n wire \\rp_timer.rp_timer_r[0]_i_1__2_n_0 ;\n wire \\rp_timer.rp_timer_r[1]_i_1__2_n_0 ;\n wire [0:0]rp_timer_ns;\n wire [1:0]rp_timer_r;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire rstdiv0_sync_r1_reg_rep__22;\n wire rtp_timer_ns1_6;\n wire [1:0]rtp_timer_r;\n wire \\rtp_timer_r[0]_i_1__2_n_0 ;\n wire \\rtp_timer_r[1]_i_1__1_n_0 ;\n wire start_pre;\n wire start_wtp_timer0;\n wire [2:0]starve_limit_cntr_r;\n wire starve_limit_cntr_r0;\n wire \\starve_limit_cntr_r[0]_i_1__2_n_0 ;\n wire \\starve_limit_cntr_r[1]_i_1__2_n_0 ;\n wire \\starve_limit_cntr_r[2]_i_1__2_n_0 ;\n wire \\starve_limit_cntr_r_reg[2]_0 ;\n wire tail_r_28;\n wire [0:0]wr_this_rank_r;\n\n FDRE \\act_this_rank_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\act_this_rank_r_reg[0]_0 ),\n .Q(act_this_rank_r),\n .R(1'b0));\n FDRE act_wait_r_lcl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(act_wait_ns),\n .Q(\\act_this_rank_r_reg[0]_0 ),\n .R(1'b0));\n FDRE bm_end_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(p_13_out),\n .Q(bm_end_r1_4),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h7F7F7F7F007F7F7F)) \n \\cmd_pipe_plus.mc_address[10]_i_3 \n (.I0(\\act_this_rank_r_reg[0]_0 ),\n .I1(\\grant_r_reg[3]_2 ),\n .I2(\\req_row_r_lcl_reg[10] ),\n .I3(\\req_row_r_lcl_reg[10]_0 ),\n .I4(row_cmd_wr),\n .I5(\\grant_r_reg[3]_3 ),\n .O(\\cmd_pipe_plus.mc_address_reg[10] ));\n (* SOFT_HLUTNM = \"soft_lutpair1093\" *) \n LUT4 #(\n .INIT(16'hFFBA)) \n col_wait_r_i_1__1\n (.I0(rcd_active_r),\n .I1(\\grant_r_reg[3]_0 [1]),\n .I2(\\starve_limit_cntr_r_reg[2]_0 ),\n .I3(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ),\n .O(col_wait_r_i_1__1_n_0));\n FDRE col_wait_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(col_wait_r_i_1__1_n_0),\n .Q(\\starve_limit_cntr_r_reg[2]_0 ),\n .R(SR));\n LUT5 #(\n .INIT(32'h0000FE00)) \n demand_priority_r_i_1\n (.I0(req_priority_r_reg),\n .I1(demand_priority_r_reg_0),\n .I2(demand_priority_r_i_3__2_n_0),\n .I3(idle_r_lcl_reg),\n .I4(demand_priority_r_i_4__1_n_0),\n .O(demand_priority_ns));\n LUT6 #(\n .INIT(64'h0000000080800080)) \n demand_priority_r_i_3__2\n (.I0(starve_limit_cntr_r[0]),\n .I1(starve_limit_cntr_r[1]),\n .I2(starve_limit_cntr_r[2]),\n .I3(req_wr_r_lcl_reg),\n .I4(q_has_rd_16),\n .I5(req_bank_rdy_r_reg_0),\n .O(demand_priority_r_i_3__2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1093\" *) \n LUT4 #(\n .INIT(16'h0051)) \n demand_priority_r_i_4__1\n (.I0(\\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ),\n .I1(\\starve_limit_cntr_r_reg[2]_0 ),\n .I2(\\grant_r_reg[3]_0 [1]),\n .I3(rcd_active_r),\n .O(demand_priority_r_i_4__1_n_0));\n FDRE demand_priority_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(demand_priority_ns),\n .Q(demand_priority_r_reg_0),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hD0D0D0D0D0DDD0D0)) \n demanded_prior_r_i_1__0\n (.I0(demand_priority_r_reg_0),\n .I1(demanded_prior_r_reg_0),\n .I2(demanded_prior_r_reg_2),\n .I3(\\grant_r_reg[3]_0 [0]),\n .I4(demand_priority_r_reg_1),\n .I5(demanded_prior_r),\n .O(demanded_prior_ns));\n FDRE demanded_prior_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(demanded_prior_ns),\n .Q(demanded_prior_r_reg_0),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1091\" *) \n LUT5 #(\n .INIT(32'h00000080)) \n \\grant_r[0]_i_2 \n (.I0(\\last_master_r_reg[2] ),\n .I1(ras_timer_zero_r),\n .I2(pre_wait_r),\n .I3(\\grant_r_reg[3]_1 ),\n .I4(auto_pre_r_lcl_reg_0),\n .O(\\grant_r_reg[0] ));\n LUT5 #(\n .INIT(32'h0000FFF7)) \n \\grant_r[0]_i_3 \n (.I0(ras_timer_zero_r),\n .I1(pre_wait_r),\n .I2(\\grant_r_reg[3]_1 ),\n .I3(auto_pre_r_lcl_reg_0),\n .I4(auto_pre_r_lcl_reg_1),\n .O(\\pre_4_1_1T_arb.granted_pre_r_reg ));\n LUT5 #(\n .INIT(32'hFFFF0045)) \n \\grant_r[3]_i_10 \n (.I0(demand_priority_r_reg_0),\n .I1(demanded_prior_r_reg_2),\n .I2(\\grant_r_reg[1] ),\n .I3(override_demand_r),\n .I4(rnk_config_valid_r_lcl_reg),\n .O(\\grant_r_reg[3] ));\n (* SOFT_HLUTNM = \"soft_lutpair1090\" *) \n LUT4 #(\n .INIT(16'h1000)) \n \\grant_r[3]_i_4 \n (.I0(auto_pre_r_lcl_reg_0),\n .I1(\\grant_r_reg[3]_1 ),\n .I2(pre_wait_r),\n .I3(ras_timer_zero_r),\n .O(\\grant_r_reg[2] ));\n LUT6 #(\n .INIT(64'h8888888880888080)) \n i___15_i_1\n (.I0(rb_hit_busy_r_reg),\n .I1(tail_r_28),\n .I2(rcd_active_r),\n .I3(\\grant_r_reg[3]_0 [1]),\n .I4(\\starve_limit_cntr_r_reg[2]_0 ),\n .I5(\\act_this_rank_r_reg[0]_0 ),\n .O(auto_pre_r_lcl_reg));\n LUT6 #(\n .INIT(64'h0404040404FF0404)) \n i___88_i_1\n (.I0(demanded_prior_r_reg_0),\n .I1(demand_priority_r_reg_0),\n .I2(\\grant_r_reg[3]_0 [1]),\n .I3(demanded_prior_r),\n .I4(demand_priority_r_reg_1),\n .I5(\\grant_r_reg[3]_0 [0]),\n .O(demanded_prior_r_reg_1));\n FDRE #(\n .INIT(1'b0)) \n ofs_rdy_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(ofs_rdy_r0),\n .Q(ofs_rdy_r),\n .R(SR));\n (* SOFT_HLUTNM = \"soft_lutpair1094\" *) \n LUT3 #(\n .INIT(8'hBA)) \n pre_bm_end_r_i_1__1\n (.I0(pre_passing_open_bank_ns),\n .I1(rp_timer_r[1]),\n .I2(rp_timer_r[0]),\n .O(pre_bm_end_ns));\n LUT6 #(\n .INIT(64'hAAA8AAAAAAA8AAA8)) \n pre_passing_open_bank_r_i_1__1\n (.I0(pass_open_bank_ns),\n .I1(\\grant_r_reg[3]_0 [1]),\n .I2(rtp_timer_r[1]),\n .I3(rtp_timer_r[0]),\n .I4(ras_timer_zero_r),\n .I5(pre_wait_r),\n .O(pre_passing_open_bank_ns));\n LUT6 #(\n .INIT(64'h0404040404550404)) \n pre_wait_r_i_1__1\n (.I0(pass_open_bank_ns),\n .I1(pre_wait_r),\n .I2(rp_timer_ns),\n .I3(rtp_timer_ns1_6),\n .I4(rtp_timer_r[0]),\n .I5(rtp_timer_r[1]),\n .O(pre_wait_ns));\n (* SOFT_HLUTNM = \"soft_lutpair1090\" *) \n LUT5 #(\n .INIT(32'hEAEAEAAA)) \n pre_wait_r_i_2__2\n (.I0(rstdiv0_sync_r1_reg_rep__22),\n .I1(ras_timer_zero_r),\n .I2(pre_wait_r),\n .I3(\\grant_r_reg[3]_1 ),\n .I4(auto_pre_r_lcl_reg_0),\n .O(rp_timer_ns));\n FDRE pre_wait_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pre_wait_ns),\n .Q(pre_wait_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h000000000000BBB0)) \n \\ras_timer_r[0]_i_3__0 \n (.I0(rd_wr_r_lcl_reg),\n .I1(\\grant_r_reg[3]_0 [1]),\n .I2(ras_timer_r[2]),\n .I3(ras_timer_r[1]),\n .I4(bm_end_r1_reg_0),\n .I5(ras_timer_r[0]),\n .O(\\ras_timer_r_reg[0]_0 ));\n LUT6 #(\n .INIT(64'h1100001011111111)) \n \\ras_timer_r[1]_i_3__1 \n (.I0(bm_end_r1_4),\n .I1(rstdiv0_sync_r1_reg_rep__21),\n .I2(ras_timer_r[2]),\n .I3(ras_timer_r[1]),\n .I4(ras_timer_r[0]),\n .I5(\\ras_timer_r[2]_i_4__0_n_0 ),\n .O(\\ras_timer_r_reg[1]_0 ));\n LUT6 #(\n .INIT(64'h000000000000DDD5)) \n \\ras_timer_r[2]_i_3__0 \n (.I0(\\ras_timer_r[2]_i_4__0_n_0 ),\n .I1(ras_timer_r[2]),\n .I2(ras_timer_r[1]),\n .I3(ras_timer_r[0]),\n .I4(bm_end_r1_4),\n .I5(rstdiv0_sync_r1_reg_rep__21),\n .O(\\ras_timer_r_reg[2]_0 ));\n LUT6 #(\n .INIT(64'hDDDDDDD0DDDDDDDD)) \n \\ras_timer_r[2]_i_4__0 \n (.I0(\\grant_r_reg[3]_0 [1]),\n .I1(rd_wr_r_lcl_reg),\n .I2(ras_timer_r[2]),\n .I3(ras_timer_r[1]),\n .I4(ras_timer_r[0]),\n .I5(\\rcd_timer_gt_2.rcd_timer_r[0]_i_1__2_n_0 ),\n .O(\\ras_timer_r[2]_i_4__0_n_0 ));\n FDRE \\ras_timer_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(D[0]),\n .Q(ras_timer_r[0]),\n .R(1'b0));\n FDRE \\ras_timer_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(D[1]),\n .Q(ras_timer_r[1]),\n .R(1'b0));\n FDRE \\ras_timer_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(D[2]),\n .Q(ras_timer_r[2]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFF02FF00FF02FF02)) \n ras_timer_zero_r_i_1__0\n (.I0(rd_wr_r_lcl_reg_0),\n .I1(ras_timer_r[2]),\n .I2(ras_timer_r[1]),\n .I3(bm_end_r1_reg_0),\n .I4(ras_timer_r[0]),\n .I5(\\rcd_timer_gt_2.rcd_timer_r[0]_i_1__2_n_0 ),\n .O(ras_timer_zero_ns));\n FDRE ras_timer_zero_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(ras_timer_zero_ns),\n .Q(ras_timer_zero_r),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h8)) \n \\rcd_timer_gt_2.rcd_timer_r[0]_i_1__2 \n (.I0(\\act_this_rank_r_reg[0]_0 ),\n .I1(\\grant_r_reg[3]_2 ),\n .O(\\rcd_timer_gt_2.rcd_timer_r[0]_i_1__2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rcd_timer_gt_2.rcd_timer_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rcd_timer_gt_2.rcd_timer_r[0]_i_1__2_n_0 ),\n .Q(rcd_active_r),\n .R(SR));\n FDRE \\rd_this_rank_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_wr_r_lcl_reg),\n .Q(rd_this_rank_r),\n .R(1'b0));\n FDRE req_bank_rdy_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(req_bank_rdy_ns),\n .Q(req_bank_rdy_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hBBBBBABB)) \n \\rnk_config_strobe_r[0]_i_2 \n (.I0(demand_priority_r_reg_1),\n .I1(demanded_prior_r_reg_2),\n .I2(\\grant_r_reg[3]_0 [1]),\n .I3(demand_priority_r_reg_0),\n .I4(demanded_prior_r_reg_0),\n .O(\\rnk_config_strobe_r_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair1094\" *) \n LUT4 #(\n .INIT(16'h0004)) \n \\rp_timer.rp_timer_r[0]_i_1__2 \n (.I0(rp_timer_r[0]),\n .I1(rp_timer_r[1]),\n .I2(start_pre),\n .I3(rstdiv0_sync_r1_reg_rep__21),\n .O(\\rp_timer.rp_timer_r[0]_i_1__2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1091\" *) \n LUT4 #(\n .INIT(16'hE000)) \n \\rp_timer.rp_timer_r[0]_i_2__2 \n (.I0(auto_pre_r_lcl_reg_0),\n .I1(\\grant_r_reg[3]_1 ),\n .I2(pre_wait_r),\n .I3(ras_timer_zero_r),\n .O(start_pre));\n LUT6 #(\n .INIT(64'hF888F888F8888888)) \n \\rp_timer.rp_timer_r[1]_i_1__2 \n (.I0(rp_timer_r[1]),\n .I1(rp_timer_r[0]),\n .I2(ras_timer_zero_r),\n .I3(pre_wait_r),\n .I4(\\grant_r_reg[3]_1 ),\n .I5(auto_pre_r_lcl_reg_0),\n .O(\\rp_timer.rp_timer_r[1]_i_1__2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\rp_timer.rp_timer_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rp_timer.rp_timer_r[0]_i_1__2_n_0 ),\n .Q(rp_timer_r[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\rp_timer.rp_timer_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rp_timer.rp_timer_r[1]_i_1__2_n_0 ),\n .Q(rp_timer_r[1]),\n .R(rstdiv0_sync_r1_reg_rep__0));\n LUT4 #(\n .INIT(16'h0002)) \n \\rtp_timer_r[0]_i_1__2 \n (.I0(rtp_timer_r[1]),\n .I1(rtp_timer_r[0]),\n .I2(rstdiv0_sync_r1_reg_rep__20),\n .I3(pass_open_bank_r_lcl_reg),\n .O(\\rtp_timer_r[0]_i_1__2_n_0 ));\n LUT5 #(\n .INIT(32'h000000C2)) \n \\rtp_timer_r[1]_i_1__1 \n (.I0(\\grant_r_reg[3]_0 [1]),\n .I1(rtp_timer_r[1]),\n .I2(rtp_timer_r[0]),\n .I3(pass_open_bank_r_lcl_reg),\n .I4(rstdiv0_sync_r1_reg_rep__21),\n .O(\\rtp_timer_r[1]_i_1__1_n_0 ));\n FDRE \\rtp_timer_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rtp_timer_r[0]_i_1__2_n_0 ),\n .Q(rtp_timer_r[0]),\n .R(1'b0));\n FDRE \\rtp_timer_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rtp_timer_r[1]_i_1__1_n_0 ),\n .Q(rtp_timer_r[1]),\n .R(1'b0));\n LUT3 #(\n .INIT(8'h60)) \n \\starve_limit_cntr_r[0]_i_1__2 \n (.I0(starve_limit_cntr_r[0]),\n .I1(starve_limit_cntr_r0),\n .I2(\\starve_limit_cntr_r_reg[2]_0 ),\n .O(\\starve_limit_cntr_r[0]_i_1__2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1092\" *) \n LUT4 #(\n .INIT(16'h6A00)) \n \\starve_limit_cntr_r[1]_i_1__2 \n (.I0(starve_limit_cntr_r[1]),\n .I1(starve_limit_cntr_r0),\n .I2(starve_limit_cntr_r[0]),\n .I3(\\starve_limit_cntr_r_reg[2]_0 ),\n .O(\\starve_limit_cntr_r[1]_i_1__2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1092\" *) \n LUT5 #(\n .INIT(32'h6AAA0000)) \n \\starve_limit_cntr_r[2]_i_1__2 \n (.I0(starve_limit_cntr_r[2]),\n .I1(starve_limit_cntr_r0),\n .I2(starve_limit_cntr_r[0]),\n .I3(starve_limit_cntr_r[1]),\n .I4(\\starve_limit_cntr_r_reg[2]_0 ),\n .O(\\starve_limit_cntr_r[2]_i_1__2_n_0 ));\n LUT6 #(\n .INIT(64'h00007F0000000000)) \n \\starve_limit_cntr_r[2]_i_2__2 \n (.I0(starve_limit_cntr_r[0]),\n .I1(starve_limit_cntr_r[1]),\n .I2(starve_limit_cntr_r[2]),\n .I3(granted_col_r_reg),\n .I4(\\grant_r_reg[3]_0 [1]),\n .I5(req_bank_rdy_r),\n .O(starve_limit_cntr_r0));\n FDRE \\starve_limit_cntr_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\starve_limit_cntr_r[0]_i_1__2_n_0 ),\n .Q(starve_limit_cntr_r[0]),\n .R(1'b0));\n FDRE \\starve_limit_cntr_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\starve_limit_cntr_r[1]_i_1__2_n_0 ),\n .Q(starve_limit_cntr_r[1]),\n .R(1'b0));\n FDRE \\starve_limit_cntr_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\starve_limit_cntr_r[2]_i_1__2_n_0 ),\n .Q(starve_limit_cntr_r[2]),\n .R(1'b0));\n FDRE \\wr_this_rank_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(start_wtp_timer0),\n .Q(wr_this_rank_r),\n .R(1'b0));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_clk_ibuf\n (mmcm_clk,\n sys_clk_i);\n output mmcm_clk;\n input sys_clk_i;\n\n (* RTL_KEEP = \"true\" *) (* syn_keep = \"true\" *) wire sys_clk_ibufg;\n\n assign mmcm_clk = sys_clk_ibufg;\n assign sys_clk_ibufg = sys_clk_i;\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_col_mach\n (col_rd_wr_r1,\n col_rd_wr_r2,\n sent_col_r2,\n D,\n bypass__0,\n \\not_strict_mode.app_rd_data_end_reg ,\n mc_read_idle_r_reg,\n \\read_fifo.tail_r_reg[2]_0 ,\n mc_ref_zq_wip_ns,\n \\read_fifo.tail_r_reg[1]_0 ,\n \\read_fifo.fifo_out_data_r_reg[7]_0 ,\n app_rd_data_end_ns,\n CLK,\n col_data_buf_addr,\n ADDRA,\n DIC,\n col_rd_wr,\n mc_cmd,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,\n \\rd_buf_indx.rd_buf_indx_r_reg[4] ,\n maint_ref_zq_wip,\n rstdiv0_sync_r1_reg_rep__23,\n \\not_strict_mode.status_ram.rd_buf_we_r1_reg ,\n SR,\n \\read_fifo.tail_r_reg[0]_0 ,\n rstdiv0_sync_r1_reg_rep__0,\n E);\n output col_rd_wr_r1;\n output col_rd_wr_r2;\n output sent_col_r2;\n output [3:0]D;\n output bypass__0;\n output [7:0]\\not_strict_mode.app_rd_data_end_reg ;\n output mc_read_idle_r_reg;\n output [1:0]\\read_fifo.tail_r_reg[2]_0 ;\n output mc_ref_zq_wip_ns;\n output \\read_fifo.tail_r_reg[1]_0 ;\n output \\read_fifo.fifo_out_data_r_reg[7]_0 ;\n output app_rd_data_end_ns;\n input CLK;\n input [4:0]col_data_buf_addr;\n input [2:0]ADDRA;\n input [0:0]DIC;\n input col_rd_wr;\n input [0:0]mc_cmd;\n input \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n input [4:0]\\rd_buf_indx.rd_buf_indx_r_reg[4] ;\n input maint_ref_zq_wip;\n input rstdiv0_sync_r1_reg_rep__23;\n input [0:0]\\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n input [0:0]SR;\n input \\read_fifo.tail_r_reg[0]_0 ;\n input rstdiv0_sync_r1_reg_rep__0;\n input [0:0]E;\n\n wire [2:0]ADDRA;\n wire CLK;\n wire [3:0]D;\n wire [0:0]DIC;\n wire [0:0]E;\n wire [0:0]SR;\n wire app_rd_data_end_ns;\n wire bypass__0;\n wire [4:0]col_data_buf_addr;\n wire col_rd_wr;\n wire col_rd_wr_r1;\n wire col_rd_wr_r2;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n wire [7:0]fifo_out_data_ns;\n wire [4:0]head_r;\n wire maint_ref_zq_wip;\n wire [0:0]mc_cmd;\n wire mc_read_idle_r_reg;\n wire mc_ref_zq_wip_ns;\n wire mc_ref_zq_wip_r_i_2_n_0;\n wire [7:0]\\not_strict_mode.app_rd_data_end_reg ;\n wire [0:0]\\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n wire [4:0]p_0_in;\n wire \\rd_buf_indx.rd_buf_indx_r[0]_i_3_n_0 ;\n wire \\rd_buf_indx.rd_buf_indx_r[0]_i_4_n_0 ;\n wire [4:0]\\rd_buf_indx.rd_buf_indx_r_reg[4] ;\n wire \\read_fifo.fifo_out_data_r_reg[7]_0 ;\n wire \\read_fifo.tail_r[1]_i_1_n_0 ;\n wire \\read_fifo.tail_r[2]_i_1_n_0 ;\n wire \\read_fifo.tail_r[3]_i_1_n_0 ;\n wire \\read_fifo.tail_r[4]_i_1_n_0 ;\n wire \\read_fifo.tail_r_reg[0]_0 ;\n wire \\read_fifo.tail_r_reg[1]_0 ;\n wire [1:0]\\read_fifo.tail_r_reg[2]_0 ;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__23;\n wire sent_col_r2;\n wire [3:0]tail_ns;\n wire [4:3]tail_r;\n wire [1:0]\\NLW_read_fifo.fifo_ram[0].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_read_fifo.fifo_ram[1].RAM32M0_DOA_UNCONNECTED ;\n wire [1:0]\\NLW_read_fifo.fifo_ram[1].RAM32M0_DOB_UNCONNECTED ;\n wire [1:0]\\NLW_read_fifo.fifo_ram[1].RAM32M0_DOD_UNCONNECTED ;\n\n FDRE \\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(col_data_buf_addr[0]),\n .Q(D[0]),\n .R(1'b0));\n FDRE \\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(col_data_buf_addr[1]),\n .Q(D[1]),\n .R(1'b0));\n FDRE \\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(col_data_buf_addr[2]),\n .Q(D[2]),\n .R(1'b0));\n FDRE \\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(col_data_buf_addr[3]),\n .Q(D[3]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h9555555555555555)) \n i___115_i_1\n (.I0(tail_r[4]),\n .I1(\\read_fifo.tail_r_reg[2]_0 [0]),\n .I2(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I3(\\read_fifo.tail_r_reg[1]_0 ),\n .I4(\\read_fifo.tail_r_reg[2]_0 [1]),\n .I5(tail_r[3]),\n .O(\\read_fifo.fifo_out_data_r_reg[7]_0 ));\n LUT5 #(\n .INIT(32'h09000009)) \n mc_read_idle_r_i_1\n (.I0(tail_r[4]),\n .I1(head_r[4]),\n .I2(mc_ref_zq_wip_r_i_2_n_0),\n .I3(head_r[3]),\n .I4(tail_r[3]),\n .O(mc_read_idle_r_reg));\n LUT6 #(\n .INIT(64'h0082000000000082)) \n mc_ref_zq_wip_r_i_1\n (.I0(maint_ref_zq_wip),\n .I1(tail_r[4]),\n .I2(head_r[4]),\n .I3(mc_ref_zq_wip_r_i_2_n_0),\n .I4(head_r[3]),\n .I5(tail_r[3]),\n .O(mc_ref_zq_wip_ns));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n mc_ref_zq_wip_r_i_2\n (.I0(\\read_fifo.tail_r_reg[1]_0 ),\n .I1(head_r[0]),\n .I2(head_r[1]),\n .I3(\\read_fifo.tail_r_reg[2]_0 [0]),\n .I4(head_r[2]),\n .I5(\\read_fifo.tail_r_reg[2]_0 [1]),\n .O(mc_ref_zq_wip_r_i_2_n_0));\n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data_end_i_1 \n (.I0(\\not_strict_mode.app_rd_data_end_reg [7]),\n .I1(bypass__0),\n .I2(\\not_strict_mode.status_ram.rd_buf_we_r1_reg ),\n .O(app_rd_data_end_ns));\n FDRE \\offset_pipe_0.col_rd_wr_r1_reg \n (.C(CLK),\n .CE(1'b1),\n .D(col_rd_wr),\n .Q(col_rd_wr_r1),\n .R(1'b0));\n FDRE \\offset_pipe_1.col_rd_wr_r2_reg \n (.C(CLK),\n .CE(1'b1),\n .D(col_rd_wr_r1),\n .Q(col_rd_wr_r2),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h2000000000002000)) \n \\rd_buf_indx.rd_buf_indx_r[0]_i_2 \n (.I0(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I1(\\not_strict_mode.app_rd_data_end_reg [6]),\n .I2(\\rd_buf_indx.rd_buf_indx_r[0]_i_3_n_0 ),\n .I3(\\rd_buf_indx.rd_buf_indx_r[0]_i_4_n_0 ),\n .I4(\\rd_buf_indx.rd_buf_indx_r_reg[4] [1]),\n .I5(\\not_strict_mode.app_rd_data_end_reg [2]),\n .O(bypass__0));\n LUT4 #(\n .INIT(16'h9009)) \n \\rd_buf_indx.rd_buf_indx_r[0]_i_3 \n (.I0(\\not_strict_mode.app_rd_data_end_reg [5]),\n .I1(\\rd_buf_indx.rd_buf_indx_r_reg[4] [4]),\n .I2(\\not_strict_mode.app_rd_data_end_reg [1]),\n .I3(\\rd_buf_indx.rd_buf_indx_r_reg[4] [0]),\n .O(\\rd_buf_indx.rd_buf_indx_r[0]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'h9009)) \n \\rd_buf_indx.rd_buf_indx_r[0]_i_4 \n (.I0(\\not_strict_mode.app_rd_data_end_reg [3]),\n .I1(\\rd_buf_indx.rd_buf_indx_r_reg[4] [2]),\n .I2(\\not_strict_mode.app_rd_data_end_reg [4]),\n .I3(\\rd_buf_indx.rd_buf_indx_r_reg[4] [3]),\n .O(\\rd_buf_indx.rd_buf_indx_r[0]_i_4_n_0 ));\n FDRE \\read_fifo.fifo_out_data_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(fifo_out_data_ns[0]),\n .Q(\\not_strict_mode.app_rd_data_end_reg [0]),\n .R(1'b0));\n FDRE \\read_fifo.fifo_out_data_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(fifo_out_data_ns[1]),\n .Q(\\not_strict_mode.app_rd_data_end_reg [1]),\n .R(1'b0));\n FDRE \\read_fifo.fifo_out_data_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(fifo_out_data_ns[2]),\n .Q(\\not_strict_mode.app_rd_data_end_reg [2]),\n .R(1'b0));\n FDRE \\read_fifo.fifo_out_data_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(fifo_out_data_ns[3]),\n .Q(\\not_strict_mode.app_rd_data_end_reg [3]),\n .R(1'b0));\n FDRE \\read_fifo.fifo_out_data_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(fifo_out_data_ns[4]),\n .Q(\\not_strict_mode.app_rd_data_end_reg [4]),\n .R(1'b0));\n FDRE \\read_fifo.fifo_out_data_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(fifo_out_data_ns[5]),\n .Q(\\not_strict_mode.app_rd_data_end_reg [5]),\n .R(1'b0));\n FDRE \\read_fifo.fifo_out_data_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(fifo_out_data_ns[6]),\n .Q(\\not_strict_mode.app_rd_data_end_reg [6]),\n .R(1'b0));\n FDRE \\read_fifo.fifo_out_data_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(fifo_out_data_ns[7]),\n .Q(\\not_strict_mode.app_rd_data_end_reg [7]),\n .R(1'b0));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\read_fifo.fifo_ram[0].RAM32M0 \n (.ADDRA({ADDRA[2],tail_ns[3],ADDRA[1:0],tail_ns[0]}),\n .ADDRB({ADDRA[2],tail_ns[3],ADDRA[1:0],tail_ns[0]}),\n .ADDRC({ADDRA[2],tail_ns[3],ADDRA[1:0],tail_ns[0]}),\n .ADDRD(head_r),\n .DIA(col_data_buf_addr[4:3]),\n .DIB(col_data_buf_addr[2:1]),\n .DIC({col_data_buf_addr[0],1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(fifo_out_data_ns[5:4]),\n .DOB(fifo_out_data_ns[3:2]),\n .DOC(fifo_out_data_ns[1:0]),\n .DOD(\\NLW_read_fifo.fifo_ram[0].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(1'b1));\n LUT6 #(\n .INIT(64'h000000007FFF8000)) \n \\read_fifo.fifo_ram[0].RAM32M0_i_5 \n (.I0(\\read_fifo.tail_r_reg[2]_0 [0]),\n .I1(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I2(\\read_fifo.tail_r_reg[1]_0 ),\n .I3(\\read_fifo.tail_r_reg[2]_0 [1]),\n .I4(tail_r[3]),\n .I5(rstdiv0_sync_r1_reg_rep__23),\n .O(tail_ns[3]));\n LUT3 #(\n .INIT(8'h06)) \n \\read_fifo.fifo_ram[0].RAM32M0_i_6 \n (.I0(\\read_fifo.tail_r_reg[1]_0 ),\n .I1(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I2(rstdiv0_sync_r1_reg_rep__23),\n .O(tail_ns[0]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\read_fifo.fifo_ram[1].RAM32M0 \n (.ADDRA({ADDRA[2],tail_ns[3],ADDRA[1:0],tail_ns[0]}),\n .ADDRB({ADDRA[2],tail_ns[3],ADDRA[1:0],tail_ns[0]}),\n .ADDRC({ADDRA[2],tail_ns[3],ADDRA[1:0],tail_ns[0]}),\n .ADDRD(head_r),\n .DIA({1'b0,1'b0}),\n .DIB({1'b0,1'b0}),\n .DIC({1'b1,DIC}),\n .DID({1'b0,1'b0}),\n .DOA(\\NLW_read_fifo.fifo_ram[1].RAM32M0_DOA_UNCONNECTED [1:0]),\n .DOB(\\NLW_read_fifo.fifo_ram[1].RAM32M0_DOB_UNCONNECTED [1:0]),\n .DOC(fifo_out_data_ns[7:6]),\n .DOD(\\NLW_read_fifo.fifo_ram[1].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(1'b1));\n LUT1 #(\n .INIT(2'h1)) \n \\read_fifo.head_r[0]_i_1 \n (.I0(head_r[0]),\n .O(p_0_in[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1102\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\read_fifo.head_r[1]_i_1 \n (.I0(head_r[0]),\n .I1(head_r[1]),\n .O(p_0_in[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1102\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\read_fifo.head_r[2]_i_1 \n (.I0(head_r[2]),\n .I1(head_r[1]),\n .I2(head_r[0]),\n .O(p_0_in[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1101\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\read_fifo.head_r[3]_i_1 \n (.I0(head_r[3]),\n .I1(head_r[0]),\n .I2(head_r[1]),\n .I3(head_r[2]),\n .O(p_0_in[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1101\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\read_fifo.head_r[4]_i_1 \n (.I0(head_r[4]),\n .I1(head_r[2]),\n .I2(head_r[1]),\n .I3(head_r[0]),\n .I4(head_r[3]),\n .O(p_0_in[4]));\n FDRE \\read_fifo.head_r_reg[0] \n (.C(CLK),\n .CE(E),\n .D(p_0_in[0]),\n .Q(head_r[0]),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\read_fifo.head_r_reg[1] \n (.C(CLK),\n .CE(E),\n .D(p_0_in[1]),\n .Q(head_r[1]),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\read_fifo.head_r_reg[2] \n (.C(CLK),\n .CE(E),\n .D(p_0_in[2]),\n .Q(head_r[2]),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\read_fifo.head_r_reg[3] \n (.C(CLK),\n .CE(E),\n .D(p_0_in[3]),\n .Q(head_r[3]),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\read_fifo.head_r_reg[4] \n (.C(CLK),\n .CE(E),\n .D(p_0_in[4]),\n .Q(head_r[4]),\n .R(rstdiv0_sync_r1_reg_rep__0));\n LUT3 #(\n .INIT(8'h78)) \n \\read_fifo.tail_r[1]_i_1 \n (.I0(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I1(\\read_fifo.tail_r_reg[1]_0 ),\n .I2(\\read_fifo.tail_r_reg[2]_0 [0]),\n .O(\\read_fifo.tail_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1100\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\read_fifo.tail_r[2]_i_1 \n (.I0(\\read_fifo.tail_r_reg[1]_0 ),\n .I1(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I2(\\read_fifo.tail_r_reg[2]_0 [0]),\n .I3(\\read_fifo.tail_r_reg[2]_0 [1]),\n .O(\\read_fifo.tail_r[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1100\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\read_fifo.tail_r[3]_i_1 \n (.I0(tail_r[3]),\n .I1(\\read_fifo.tail_r_reg[2]_0 [1]),\n .I2(\\read_fifo.tail_r_reg[1]_0 ),\n .I3(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I4(\\read_fifo.tail_r_reg[2]_0 [0]),\n .O(\\read_fifo.tail_r[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h7FFFFFFF80000000)) \n \\read_fifo.tail_r[4]_i_1 \n (.I0(tail_r[3]),\n .I1(\\read_fifo.tail_r_reg[2]_0 [1]),\n .I2(\\read_fifo.tail_r_reg[1]_0 ),\n .I3(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I4(\\read_fifo.tail_r_reg[2]_0 [0]),\n .I5(tail_r[4]),\n .O(\\read_fifo.tail_r[4]_i_1_n_0 ));\n FDRE \\read_fifo.tail_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\read_fifo.tail_r_reg[0]_0 ),\n .Q(\\read_fifo.tail_r_reg[1]_0 ),\n .R(SR));\n FDRE \\read_fifo.tail_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\read_fifo.tail_r[1]_i_1_n_0 ),\n .Q(\\read_fifo.tail_r_reg[2]_0 [0]),\n .R(SR));\n FDRE \\read_fifo.tail_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\read_fifo.tail_r[2]_i_1_n_0 ),\n .Q(\\read_fifo.tail_r_reg[2]_0 [1]),\n .R(SR));\n FDRE \\read_fifo.tail_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\read_fifo.tail_r[3]_i_1_n_0 ),\n .Q(tail_r[3]),\n .R(SR));\n FDRE \\read_fifo.tail_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\read_fifo.tail_r[4]_i_1_n_0 ),\n .Q(tail_r[4]),\n .R(SR));\n FDRE sent_col_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mc_cmd),\n .Q(sent_col_r2),\n .R(1'b0));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_ddr_byte_group_io\n (mem_dqs_out,\n mem_dqs_ts,\n D0,\n D1,\n D2,\n D3,\n D4,\n D5,\n D6,\n D7,\n mem_dq_out,\n mem_dq_ts,\n idelay_ld_rst,\n rst_r4,\n oserdes_clk,\n oserdes_clkdiv,\n po_oserdes_rst,\n DTSBUS,\n oserdes_clk_delayed,\n DQSBUS,\n CTSBUS,\n CLK,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n mem_dq_in,\n idelay_inc,\n LD0,\n A_rst_primitives,\n A_rst_primitives_reg,\n CLKB0,\n iserdes_clkdiv,\n of_dqbus,\n E,\n \\fine_delay_mod_reg[23] );\n output [0:0]mem_dqs_out;\n output [0:0]mem_dqs_ts;\n output [3:0]D0;\n output [3:0]D1;\n output [3:0]D2;\n output [3:0]D3;\n output [3:0]D4;\n output [3:0]D5;\n output [3:0]D6;\n output [3:0]D7;\n output [8:0]mem_dq_out;\n output [8:0]mem_dq_ts;\n output idelay_ld_rst;\n output rst_r4;\n input oserdes_clk;\n input oserdes_clkdiv;\n input po_oserdes_rst;\n input [1:0]DTSBUS;\n input oserdes_clk_delayed;\n input [1:0]DQSBUS;\n input [0:0]CTSBUS;\n input CLK;\n input \\gen_byte_sel_div1.calib_in_common_reg ;\n input [7:0]mem_dq_in;\n input idelay_inc;\n input LD0;\n input A_rst_primitives;\n input A_rst_primitives_reg;\n input CLKB0;\n input iserdes_clkdiv;\n input [35:0]of_dqbus;\n input [0:0]E;\n input [7:0]\\fine_delay_mod_reg[23] ;\n\n wire A_rst_primitives;\n wire A_rst_primitives_reg;\n wire CLK;\n wire CLKB0;\n wire [0:0]CTSBUS;\n wire [3:0]D0;\n wire [3:0]D1;\n wire [3:0]D2;\n wire [3:0]D3;\n wire [3:0]D4;\n wire [3:0]D5;\n wire [3:0]D6;\n wire [3:0]D7;\n wire [1:0]DQSBUS;\n wire [1:0]DTSBUS;\n wire [0:0]E;\n wire LD0;\n wire data_in_dly_0;\n wire data_in_dly_1;\n wire data_in_dly_2;\n wire data_in_dly_3;\n wire data_in_dly_4;\n wire data_in_dly_5;\n wire data_in_dly_6;\n wire data_in_dly_7;\n wire [7:0]\\fine_delay_mod_reg[23] ;\n wire [23:2]fine_delay_r;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire idelay_inc;\n wire idelay_ld_rst;\n wire idelay_ld_rst_i_1_n_0;\n wire iserdes_clkdiv;\n wire [7:0]mem_dq_in;\n wire [8:0]mem_dq_out;\n wire [8:0]mem_dq_ts;\n wire [0:0]mem_dqs_out;\n wire [0:0]mem_dqs_ts;\n wire [35:0]of_dqbus;\n wire oserdes_clk;\n wire oserdes_clk_delayed;\n wire oserdes_clkdiv;\n wire po_oserdes_rst;\n wire rst_r3_reg_srl3_n_0;\n wire rst_r4;\n wire tbyte_out;\n wire \\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ;\n wire \\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ;\n wire [4:0]\\NLW_input_[0].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[0].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[0].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[0].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[0].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[0].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[0].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[0].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[0].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ;\n\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* __SRVAL = \"FALSE\" *) \n ODDR #(\n .DDR_CLK_EDGE(\"SAME_EDGE\"),\n .INIT(1'b0),\n .IS_C_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .SRTYPE(\"SYNC\")) \n \\dqs_gen.oddr_dqs \n (.C(oserdes_clk_delayed),\n .CE(1'b1),\n .D1(DQSBUS[0]),\n .D2(DQSBUS[1]),\n .Q(mem_dqs_out),\n .R(1'b0),\n .S(\\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* __SRVAL = \"TRUE\" *) \n ODDR #(\n .DDR_CLK_EDGE(\"SAME_EDGE\"),\n .INIT(1'b0),\n .IS_C_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .SRTYPE(\"SYNC\")) \n \\dqs_gen.oddr_dqsts \n (.C(oserdes_clk_delayed),\n .CE(1'b1),\n .D1(CTSBUS),\n .D2(CTSBUS),\n .Q(mem_dqs_ts),\n .R(\\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ),\n .S(1'b0));\n FDRE \\fine_delay_r_reg[11] \n (.C(CLK),\n .CE(E),\n .D(\\fine_delay_mod_reg[23] [3]),\n .Q(fine_delay_r[11]),\n .R(A_rst_primitives));\n FDRE \\fine_delay_r_reg[14] \n (.C(CLK),\n .CE(E),\n .D(\\fine_delay_mod_reg[23] [4]),\n .Q(fine_delay_r[14]),\n .R(A_rst_primitives));\n FDRE \\fine_delay_r_reg[17] \n (.C(CLK),\n .CE(E),\n .D(\\fine_delay_mod_reg[23] [5]),\n .Q(fine_delay_r[17]),\n .R(A_rst_primitives));\n FDRE \\fine_delay_r_reg[20] \n (.C(CLK),\n .CE(E),\n .D(\\fine_delay_mod_reg[23] [6]),\n .Q(fine_delay_r[20]),\n .R(A_rst_primitives));\n FDRE \\fine_delay_r_reg[23] \n (.C(CLK),\n .CE(E),\n .D(\\fine_delay_mod_reg[23] [7]),\n .Q(fine_delay_r[23]),\n .R(A_rst_primitives));\n FDRE \\fine_delay_r_reg[2] \n (.C(CLK),\n .CE(E),\n .D(\\fine_delay_mod_reg[23] [0]),\n .Q(fine_delay_r[2]),\n .R(A_rst_primitives));\n FDRE \\fine_delay_r_reg[5] \n (.C(CLK),\n .CE(E),\n .D(\\fine_delay_mod_reg[23] [1]),\n .Q(fine_delay_r[5]),\n .R(A_rst_primitives));\n FDRE \\fine_delay_r_reg[8] \n (.C(CLK),\n .CE(E),\n .D(\\fine_delay_mod_reg[23] [2]),\n .Q(fine_delay_r[8]),\n .R(A_rst_primitives));\n LUT2 #(\n .INIT(4'h2)) \n idelay_ld_rst_i_1\n (.I0(idelay_ld_rst),\n .I1(rst_r4),\n .O(idelay_ld_rst_i_1_n_0));\n FDSE idelay_ld_rst_reg\n (.C(CLK),\n .CE(1'b1),\n .D(idelay_ld_rst_i_1_n_0),\n .Q(idelay_ld_rst),\n .S(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[0].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[0].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_0),\n .IDATAIN(mem_dq_in[0]),\n .IFDLY({fine_delay_r[2],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[0].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0),\n .CLKDIV(\\NLW_input_[0].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[0]),\n .DDLY(data_in_dly_0),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[0].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[0].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[0].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D0[3]),\n .Q2(D0[2]),\n .Q3(D0[1]),\n .Q4(D0[0]),\n .Q5(\\NLW_input_[0].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[0].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[0].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[0].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_1),\n .IDATAIN(mem_dq_in[1]),\n .IFDLY({fine_delay_r[5],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[1].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0),\n .CLKDIV(\\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[1]),\n .DDLY(data_in_dly_1),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D1[3]),\n .Q2(D1[2]),\n .Q3(D1[1]),\n .Q4(D1[0]),\n .Q5(\\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_2),\n .IDATAIN(mem_dq_in[2]),\n .IFDLY({fine_delay_r[8],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[2].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0),\n .CLKDIV(\\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[2]),\n .DDLY(data_in_dly_2),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D2[3]),\n .Q2(D2[2]),\n .Q3(D2[1]),\n .Q4(D2[0]),\n .Q5(\\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_3),\n .IDATAIN(mem_dq_in[3]),\n .IFDLY({fine_delay_r[11],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[3].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0),\n .CLKDIV(\\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[3]),\n .DDLY(data_in_dly_3),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D3[3]),\n .Q2(D3[2]),\n .Q3(D3[1]),\n .Q4(D3[0]),\n .Q5(\\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_4),\n .IDATAIN(mem_dq_in[4]),\n .IFDLY({fine_delay_r[14],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[4].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0),\n .CLKDIV(\\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[4]),\n .DDLY(data_in_dly_4),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D4[3]),\n .Q2(D4[2]),\n .Q3(D4[1]),\n .Q4(D4[0]),\n .Q5(\\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_5),\n .IDATAIN(mem_dq_in[5]),\n .IFDLY({fine_delay_r[17],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[5].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0),\n .CLKDIV(\\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[5]),\n .DDLY(data_in_dly_5),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D5[3]),\n .Q2(D5[2]),\n .Q3(D5[1]),\n .Q4(D5[0]),\n .Q5(\\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_6),\n .IDATAIN(mem_dq_in[6]),\n .IFDLY({fine_delay_r[20],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[6].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0),\n .CLKDIV(\\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[6]),\n .DDLY(data_in_dly_6),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D6[3]),\n .Q2(D6[2]),\n .Q3(D6[1]),\n .Q4(D6[0]),\n .Q5(\\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_7),\n .IDATAIN(mem_dq_in[7]),\n .IFDLY({fine_delay_r[23],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[7].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0),\n .CLKDIV(\\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[7]),\n .DDLY(data_in_dly_7),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D7[3]),\n .Q2(D7[2]),\n .Q3(D7[1]),\n .Q4(D7[0]),\n .Q5(\\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[0].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[0]),\n .D2(of_dqbus[1]),\n .D3(of_dqbus[2]),\n .D4(of_dqbus[3]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[0]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[0]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[1].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[4]),\n .D2(of_dqbus[5]),\n .D3(of_dqbus[6]),\n .D4(of_dqbus[7]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[1]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[1]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[2].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[8]),\n .D2(of_dqbus[9]),\n .D3(of_dqbus[10]),\n .D4(of_dqbus[11]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[2]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[2]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[3].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[12]),\n .D2(of_dqbus[13]),\n .D3(of_dqbus[14]),\n .D4(of_dqbus[15]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[3]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[3]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[4].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[16]),\n .D2(of_dqbus[17]),\n .D3(of_dqbus[18]),\n .D4(of_dqbus[19]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[4]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[4]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[5].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[20]),\n .D2(of_dqbus[21]),\n .D3(of_dqbus[22]),\n .D4(of_dqbus[23]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[5]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[5]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[6].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[24]),\n .D2(of_dqbus[25]),\n .D3(of_dqbus[26]),\n .D4(of_dqbus[27]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[6]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[6]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[7].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[28]),\n .D2(of_dqbus[29]),\n .D3(of_dqbus[30]),\n .D4(of_dqbus[31]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[7]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[7]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[9].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[32]),\n .D2(of_dqbus[33]),\n .D3(of_dqbus[34]),\n .D4(of_dqbus[35]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[8]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[8]));\n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/rst_r3_reg_srl3 \" *) \n SRL16E rst_r3_reg_srl3\n (.A0(1'b0),\n .A1(1'b1),\n .A2(1'b0),\n .A3(1'b0),\n .CE(1'b1),\n .CLK(CLK),\n .D(A_rst_primitives),\n .Q(rst_r3_reg_srl3_n_0));\n FDRE rst_r4_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rst_r3_reg_srl3_n_0),\n .Q(rst_r4),\n .R(1'b0));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"TRUE\"),\n .TRISTATE_WIDTH(4)) \n \\slave_ts.oserdes_slave_ts \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(1'b0),\n .D2(1'b0),\n .D3(1'b0),\n .D4(1'b0),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ),\n .OQ(\\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ),\n .T1(DTSBUS[0]),\n .T2(DTSBUS[0]),\n .T3(DTSBUS[1]),\n .T4(DTSBUS[1]),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(tbyte_out),\n .TCE(1'b1),\n .TFB(\\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ),\n .TQ(\\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_byte_group_io\" *) \nmodule ddr3_if_mig_7series_v4_0_ddr_byte_group_io__parameterized0\n (mem_dqs_out,\n mem_dqs_ts,\n D1,\n D2,\n D3,\n D4,\n D5,\n D6,\n D7,\n D8,\n mem_dq_out,\n mem_dq_ts,\n idelay_ld_rst_0,\n oserdes_clk,\n oserdes_clkdiv,\n po_oserdes_rst,\n DTSBUS,\n oserdes_clk_delayed,\n DQSBUS,\n CTSBUS,\n CLK,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n mem_dq_in,\n idelay_inc,\n LD0_3,\n A_rst_primitives,\n A_rst_primitives_reg,\n CLKB0_7,\n iserdes_clkdiv,\n of_dqbus,\n rst_r4,\n \\gen_byte_sel_div1.calib_in_common_reg_0 ,\n \\calib_sel_reg[0] );\n output [0:0]mem_dqs_out;\n output [0:0]mem_dqs_ts;\n output [3:0]D1;\n output [3:0]D2;\n output [3:0]D3;\n output [3:0]D4;\n output [3:0]D5;\n output [3:0]D6;\n output [3:0]D7;\n output [3:0]D8;\n output [8:0]mem_dq_out;\n output [8:0]mem_dq_ts;\n output idelay_ld_rst_0;\n input oserdes_clk;\n input oserdes_clkdiv;\n input po_oserdes_rst;\n input [1:0]DTSBUS;\n input oserdes_clk_delayed;\n input [1:0]DQSBUS;\n input [0:0]CTSBUS;\n input CLK;\n input \\gen_byte_sel_div1.calib_in_common_reg ;\n input [7:0]mem_dq_in;\n input idelay_inc;\n input LD0_3;\n input A_rst_primitives;\n input A_rst_primitives_reg;\n input CLKB0_7;\n input iserdes_clkdiv;\n input [35:0]of_dqbus;\n input rst_r4;\n input [0:0]\\gen_byte_sel_div1.calib_in_common_reg_0 ;\n input [7:0]\\calib_sel_reg[0] ;\n\n wire A_rst_primitives;\n wire A_rst_primitives_reg;\n wire CLK;\n wire CLKB0_7;\n wire [0:0]CTSBUS;\n wire [3:0]D1;\n wire [3:0]D2;\n wire [3:0]D3;\n wire [3:0]D4;\n wire [3:0]D5;\n wire [3:0]D6;\n wire [3:0]D7;\n wire [3:0]D8;\n wire [1:0]DQSBUS;\n wire [1:0]DTSBUS;\n wire LD0_3;\n wire [7:0]\\calib_sel_reg[0] ;\n wire data_in_dly_1;\n wire data_in_dly_2;\n wire data_in_dly_3;\n wire data_in_dly_4;\n wire data_in_dly_5;\n wire data_in_dly_6;\n wire data_in_dly_7;\n wire data_in_dly_8;\n wire [26:5]fine_delay_r;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire [0:0]\\gen_byte_sel_div1.calib_in_common_reg_0 ;\n wire idelay_inc;\n wire idelay_ld_rst_0;\n wire idelay_ld_rst_i_1__0_n_0;\n wire iserdes_clkdiv;\n wire [7:0]mem_dq_in;\n wire [8:0]mem_dq_out;\n wire [8:0]mem_dq_ts;\n wire [0:0]mem_dqs_out;\n wire [0:0]mem_dqs_ts;\n wire [35:0]of_dqbus;\n wire oserdes_clk;\n wire oserdes_clk_delayed;\n wire oserdes_clkdiv;\n wire po_oserdes_rst;\n wire rst_r4;\n wire tbyte_out;\n wire \\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ;\n wire \\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ;\n wire [4:0]\\NLW_input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ;\n\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* __SRVAL = \"FALSE\" *) \n ODDR #(\n .DDR_CLK_EDGE(\"SAME_EDGE\"),\n .INIT(1'b0),\n .IS_C_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .SRTYPE(\"SYNC\")) \n \\dqs_gen.oddr_dqs \n (.C(oserdes_clk_delayed),\n .CE(1'b1),\n .D1(DQSBUS[0]),\n .D2(DQSBUS[1]),\n .Q(mem_dqs_out),\n .R(1'b0),\n .S(\\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* __SRVAL = \"TRUE\" *) \n ODDR #(\n .DDR_CLK_EDGE(\"SAME_EDGE\"),\n .INIT(1'b0),\n .IS_C_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .SRTYPE(\"SYNC\")) \n \\dqs_gen.oddr_dqsts \n (.C(oserdes_clk_delayed),\n .CE(1'b1),\n .D1(CTSBUS),\n .D2(CTSBUS),\n .Q(mem_dqs_ts),\n .R(\\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ),\n .S(1'b0));\n FDRE \\fine_delay_r_reg[11] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[0] [2]),\n .Q(fine_delay_r[11]),\n .R(A_rst_primitives));\n FDRE \\fine_delay_r_reg[14] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[0] [3]),\n .Q(fine_delay_r[14]),\n .R(A_rst_primitives));\n FDRE \\fine_delay_r_reg[17] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[0] [4]),\n .Q(fine_delay_r[17]),\n .R(A_rst_primitives));\n FDRE \\fine_delay_r_reg[20] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[0] [5]),\n .Q(fine_delay_r[20]),\n .R(A_rst_primitives));\n FDRE \\fine_delay_r_reg[23] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[0] [6]),\n .Q(fine_delay_r[23]),\n .R(A_rst_primitives));\n FDRE \\fine_delay_r_reg[26] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[0] [7]),\n .Q(fine_delay_r[26]),\n .R(A_rst_primitives));\n FDRE \\fine_delay_r_reg[5] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[0] [0]),\n .Q(fine_delay_r[5]),\n .R(A_rst_primitives));\n FDRE \\fine_delay_r_reg[8] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[0] [1]),\n .Q(fine_delay_r[8]),\n .R(A_rst_primitives));\n LUT2 #(\n .INIT(4'h2)) \n idelay_ld_rst_i_1__0\n (.I0(idelay_ld_rst_0),\n .I1(rst_r4),\n .O(idelay_ld_rst_i_1__0_n_0));\n FDSE idelay_ld_rst_reg\n (.C(CLK),\n .CE(1'b1),\n .D(idelay_ld_rst_i_1__0_n_0),\n .Q(idelay_ld_rst_0),\n .S(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_1),\n .IDATAIN(mem_dq_in[0]),\n .IFDLY({fine_delay_r[5],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_3),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[1].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_7),\n .CLKDIV(\\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[0]),\n .DDLY(data_in_dly_1),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D1[3]),\n .Q2(D1[2]),\n .Q3(D1[1]),\n .Q4(D1[0]),\n .Q5(\\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_2),\n .IDATAIN(mem_dq_in[1]),\n .IFDLY({fine_delay_r[8],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_3),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[2].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_7),\n .CLKDIV(\\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[1]),\n .DDLY(data_in_dly_2),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D2[3]),\n .Q2(D2[2]),\n .Q3(D2[1]),\n .Q4(D2[0]),\n .Q5(\\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_3),\n .IDATAIN(mem_dq_in[2]),\n .IFDLY({fine_delay_r[11],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_3),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[3].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_7),\n .CLKDIV(\\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[2]),\n .DDLY(data_in_dly_3),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D3[3]),\n .Q2(D3[2]),\n .Q3(D3[1]),\n .Q4(D3[0]),\n .Q5(\\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_4),\n .IDATAIN(mem_dq_in[3]),\n .IFDLY({fine_delay_r[14],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_3),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[4].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_7),\n .CLKDIV(\\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[3]),\n .DDLY(data_in_dly_4),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D4[3]),\n .Q2(D4[2]),\n .Q3(D4[1]),\n .Q4(D4[0]),\n .Q5(\\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_5),\n .IDATAIN(mem_dq_in[4]),\n .IFDLY({fine_delay_r[17],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_3),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[5].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_7),\n .CLKDIV(\\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[4]),\n .DDLY(data_in_dly_5),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D5[3]),\n .Q2(D5[2]),\n .Q3(D5[1]),\n .Q4(D5[0]),\n .Q5(\\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_6),\n .IDATAIN(mem_dq_in[5]),\n .IFDLY({fine_delay_r[20],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_3),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[6].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_7),\n .CLKDIV(\\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[5]),\n .DDLY(data_in_dly_6),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D6[3]),\n .Q2(D6[2]),\n .Q3(D6[1]),\n .Q4(D6[0]),\n .Q5(\\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_7),\n .IDATAIN(mem_dq_in[6]),\n .IFDLY({fine_delay_r[23],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_3),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[7].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_7),\n .CLKDIV(\\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[6]),\n .DDLY(data_in_dly_7),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D7[3]),\n .Q2(D7[2]),\n .Q3(D7[1]),\n .Q4(D7[0]),\n .Q5(\\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_8),\n .IDATAIN(mem_dq_in[7]),\n .IFDLY({fine_delay_r[26],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_3),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[8].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_7),\n .CLKDIV(\\NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[7]),\n .DDLY(data_in_dly_8),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D8[3]),\n .Q2(D8[2]),\n .Q3(D8[1]),\n .Q4(D8[0]),\n .Q5(\\NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[1].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[0]),\n .D2(of_dqbus[1]),\n .D3(of_dqbus[2]),\n .D4(of_dqbus[3]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[0]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[0]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[2].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[4]),\n .D2(of_dqbus[5]),\n .D3(of_dqbus[6]),\n .D4(of_dqbus[7]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[1]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[1]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[3].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[8]),\n .D2(of_dqbus[9]),\n .D3(of_dqbus[10]),\n .D4(of_dqbus[11]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[2]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[2]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[4].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[12]),\n .D2(of_dqbus[13]),\n .D3(of_dqbus[14]),\n .D4(of_dqbus[15]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[3]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[3]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[5].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[16]),\n .D2(of_dqbus[17]),\n .D3(of_dqbus[18]),\n .D4(of_dqbus[19]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[4]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[4]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[6].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[20]),\n .D2(of_dqbus[21]),\n .D3(of_dqbus[22]),\n .D4(of_dqbus[23]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[5]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[5]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[7].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[24]),\n .D2(of_dqbus[25]),\n .D3(of_dqbus[26]),\n .D4(of_dqbus[27]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[6]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[6]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[8].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[28]),\n .D2(of_dqbus[29]),\n .D3(of_dqbus[30]),\n .D4(of_dqbus[31]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[7]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[7]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[9].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[32]),\n .D2(of_dqbus[33]),\n .D3(of_dqbus[34]),\n .D4(of_dqbus[35]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[8]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[8]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"TRUE\"),\n .TRISTATE_WIDTH(4)) \n \\slave_ts.oserdes_slave_ts \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(1'b0),\n .D2(1'b0),\n .D3(1'b0),\n .D4(1'b0),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ),\n .OQ(\\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ),\n .T1(DTSBUS[0]),\n .T2(DTSBUS[0]),\n .T3(DTSBUS[1]),\n .T4(DTSBUS[1]),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(tbyte_out),\n .TCE(1'b1),\n .TFB(\\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ),\n .TQ(\\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_byte_group_io\" *) \nmodule ddr3_if_mig_7series_v4_0_ddr_byte_group_io__parameterized1\n (mem_dqs_out,\n mem_dqs_ts,\n D1,\n D2,\n D3,\n D4,\n D5,\n D6,\n D7,\n D8,\n mem_dq_out,\n mem_dq_ts,\n idelay_ld_rst_1,\n oserdes_clk,\n oserdes_clkdiv,\n po_oserdes_rst,\n DTSBUS,\n oserdes_clk_delayed,\n DQSBUS,\n CTSBUS,\n CLK,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n mem_dq_in,\n idelay_inc,\n LD0_4,\n A_rst_primitives,\n A_rst_primitives_reg,\n CLKB0_8,\n iserdes_clkdiv,\n of_dqbus,\n rst_r4,\n \\gen_byte_sel_div1.calib_in_common_reg_0 ,\n \\calib_sel_reg[1] );\n output [0:0]mem_dqs_out;\n output [0:0]mem_dqs_ts;\n output [3:0]D1;\n output [3:0]D2;\n output [3:0]D3;\n output [3:0]D4;\n output [3:0]D5;\n output [3:0]D6;\n output [3:0]D7;\n output [3:0]D8;\n output [8:0]mem_dq_out;\n output [8:0]mem_dq_ts;\n output idelay_ld_rst_1;\n input oserdes_clk;\n input oserdes_clkdiv;\n input po_oserdes_rst;\n input [1:0]DTSBUS;\n input oserdes_clk_delayed;\n input [1:0]DQSBUS;\n input [0:0]CTSBUS;\n input CLK;\n input \\gen_byte_sel_div1.calib_in_common_reg ;\n input [7:0]mem_dq_in;\n input idelay_inc;\n input LD0_4;\n input A_rst_primitives;\n input A_rst_primitives_reg;\n input CLKB0_8;\n input iserdes_clkdiv;\n input [35:0]of_dqbus;\n input rst_r4;\n input [0:0]\\gen_byte_sel_div1.calib_in_common_reg_0 ;\n input [7:0]\\calib_sel_reg[1] ;\n\n wire A_rst_primitives;\n wire A_rst_primitives_reg;\n wire CLK;\n wire CLKB0_8;\n wire [0:0]CTSBUS;\n wire [3:0]D1;\n wire [3:0]D2;\n wire [3:0]D3;\n wire [3:0]D4;\n wire [3:0]D5;\n wire [3:0]D6;\n wire [3:0]D7;\n wire [3:0]D8;\n wire [1:0]DQSBUS;\n wire [1:0]DTSBUS;\n wire LD0_4;\n wire [7:0]\\calib_sel_reg[1] ;\n wire data_in_dly_1;\n wire data_in_dly_2;\n wire data_in_dly_3;\n wire data_in_dly_4;\n wire data_in_dly_5;\n wire data_in_dly_6;\n wire data_in_dly_7;\n wire data_in_dly_8;\n wire [26:5]fine_delay_r;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire [0:0]\\gen_byte_sel_div1.calib_in_common_reg_0 ;\n wire idelay_inc;\n wire idelay_ld_rst_1;\n wire idelay_ld_rst_i_1__1_n_0;\n wire iserdes_clkdiv;\n wire [7:0]mem_dq_in;\n wire [8:0]mem_dq_out;\n wire [8:0]mem_dq_ts;\n wire [0:0]mem_dqs_out;\n wire [0:0]mem_dqs_ts;\n wire [35:0]of_dqbus;\n wire oserdes_clk;\n wire oserdes_clk_delayed;\n wire oserdes_clkdiv;\n wire po_oserdes_rst;\n wire rst_r4;\n wire tbyte_out;\n wire \\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ;\n wire \\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ;\n wire [4:0]\\NLW_input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ;\n\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* __SRVAL = \"FALSE\" *) \n ODDR #(\n .DDR_CLK_EDGE(\"SAME_EDGE\"),\n .INIT(1'b0),\n .IS_C_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .SRTYPE(\"SYNC\")) \n \\dqs_gen.oddr_dqs \n (.C(oserdes_clk_delayed),\n .CE(1'b1),\n .D1(DQSBUS[0]),\n .D2(DQSBUS[1]),\n .Q(mem_dqs_out),\n .R(1'b0),\n .S(\\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* __SRVAL = \"TRUE\" *) \n ODDR #(\n .DDR_CLK_EDGE(\"SAME_EDGE\"),\n .INIT(1'b0),\n .IS_C_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .SRTYPE(\"SYNC\")) \n \\dqs_gen.oddr_dqsts \n (.C(oserdes_clk_delayed),\n .CE(1'b1),\n .D1(CTSBUS),\n .D2(CTSBUS),\n .Q(mem_dqs_ts),\n .R(\\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ),\n .S(1'b0));\n FDRE \\fine_delay_r_reg[11] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[1] [2]),\n .Q(fine_delay_r[11]),\n .R(A_rst_primitives));\n FDRE \\fine_delay_r_reg[14] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[1] [3]),\n .Q(fine_delay_r[14]),\n .R(A_rst_primitives));\n FDRE \\fine_delay_r_reg[17] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[1] [4]),\n .Q(fine_delay_r[17]),\n .R(A_rst_primitives));\n FDRE \\fine_delay_r_reg[20] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[1] [5]),\n .Q(fine_delay_r[20]),\n .R(A_rst_primitives));\n FDRE \\fine_delay_r_reg[23] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[1] [6]),\n .Q(fine_delay_r[23]),\n .R(A_rst_primitives));\n FDRE \\fine_delay_r_reg[26] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[1] [7]),\n .Q(fine_delay_r[26]),\n .R(A_rst_primitives));\n FDRE \\fine_delay_r_reg[5] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[1] [0]),\n .Q(fine_delay_r[5]),\n .R(A_rst_primitives));\n FDRE \\fine_delay_r_reg[8] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[1] [1]),\n .Q(fine_delay_r[8]),\n .R(A_rst_primitives));\n LUT2 #(\n .INIT(4'h2)) \n idelay_ld_rst_i_1__1\n (.I0(idelay_ld_rst_1),\n .I1(rst_r4),\n .O(idelay_ld_rst_i_1__1_n_0));\n FDSE idelay_ld_rst_reg\n (.C(CLK),\n .CE(1'b1),\n .D(idelay_ld_rst_i_1__1_n_0),\n .Q(idelay_ld_rst_1),\n .S(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_1),\n .IDATAIN(mem_dq_in[0]),\n .IFDLY({fine_delay_r[5],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_4),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[1].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_8),\n .CLKDIV(\\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[0]),\n .DDLY(data_in_dly_1),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D1[3]),\n .Q2(D1[2]),\n .Q3(D1[1]),\n .Q4(D1[0]),\n .Q5(\\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_2),\n .IDATAIN(mem_dq_in[1]),\n .IFDLY({fine_delay_r[8],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_4),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[2].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_8),\n .CLKDIV(\\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[1]),\n .DDLY(data_in_dly_2),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D2[3]),\n .Q2(D2[2]),\n .Q3(D2[1]),\n .Q4(D2[0]),\n .Q5(\\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_3),\n .IDATAIN(mem_dq_in[2]),\n .IFDLY({fine_delay_r[11],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_4),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[3].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_8),\n .CLKDIV(\\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[2]),\n .DDLY(data_in_dly_3),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D3[3]),\n .Q2(D3[2]),\n .Q3(D3[1]),\n .Q4(D3[0]),\n .Q5(\\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_4),\n .IDATAIN(mem_dq_in[3]),\n .IFDLY({fine_delay_r[14],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_4),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[4].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_8),\n .CLKDIV(\\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[3]),\n .DDLY(data_in_dly_4),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D4[3]),\n .Q2(D4[2]),\n .Q3(D4[1]),\n .Q4(D4[0]),\n .Q5(\\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_5),\n .IDATAIN(mem_dq_in[4]),\n .IFDLY({fine_delay_r[17],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_4),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[5].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_8),\n .CLKDIV(\\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[4]),\n .DDLY(data_in_dly_5),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D5[3]),\n .Q2(D5[2]),\n .Q3(D5[1]),\n .Q4(D5[0]),\n .Q5(\\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_6),\n .IDATAIN(mem_dq_in[5]),\n .IFDLY({fine_delay_r[20],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_4),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[6].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_8),\n .CLKDIV(\\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[5]),\n .DDLY(data_in_dly_6),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D6[3]),\n .Q2(D6[2]),\n .Q3(D6[1]),\n .Q4(D6[0]),\n .Q5(\\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_7),\n .IDATAIN(mem_dq_in[6]),\n .IFDLY({fine_delay_r[23],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_4),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[7].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_8),\n .CLKDIV(\\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[6]),\n .DDLY(data_in_dly_7),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D7[3]),\n .Q2(D7[2]),\n .Q3(D7[1]),\n .Q4(D7[0]),\n .Q5(\\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_8),\n .IDATAIN(mem_dq_in[7]),\n .IFDLY({fine_delay_r[26],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_4),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[8].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_8),\n .CLKDIV(\\NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[7]),\n .DDLY(data_in_dly_8),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D8[3]),\n .Q2(D8[2]),\n .Q3(D8[1]),\n .Q4(D8[0]),\n .Q5(\\NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[1].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[0]),\n .D2(of_dqbus[1]),\n .D3(of_dqbus[2]),\n .D4(of_dqbus[3]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[0]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[0]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[2].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[4]),\n .D2(of_dqbus[5]),\n .D3(of_dqbus[6]),\n .D4(of_dqbus[7]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[1]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[1]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[3].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[8]),\n .D2(of_dqbus[9]),\n .D3(of_dqbus[10]),\n .D4(of_dqbus[11]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[2]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[2]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[4].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[12]),\n .D2(of_dqbus[13]),\n .D3(of_dqbus[14]),\n .D4(of_dqbus[15]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[3]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[3]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[5].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[16]),\n .D2(of_dqbus[17]),\n .D3(of_dqbus[18]),\n .D4(of_dqbus[19]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[4]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[4]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[6].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[20]),\n .D2(of_dqbus[21]),\n .D3(of_dqbus[22]),\n .D4(of_dqbus[23]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[5]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[5]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[7].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[24]),\n .D2(of_dqbus[25]),\n .D3(of_dqbus[26]),\n .D4(of_dqbus[27]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[6]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[6]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[8].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[28]),\n .D2(of_dqbus[29]),\n .D3(of_dqbus[30]),\n .D4(of_dqbus[31]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[7]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[7]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[9].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[32]),\n .D2(of_dqbus[33]),\n .D3(of_dqbus[34]),\n .D4(of_dqbus[35]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[8]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[8]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"TRUE\"),\n .TRISTATE_WIDTH(4)) \n \\slave_ts.oserdes_slave_ts \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(1'b0),\n .D2(1'b0),\n .D3(1'b0),\n .D4(1'b0),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ),\n .OQ(\\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ),\n .T1(DTSBUS[0]),\n .T2(DTSBUS[0]),\n .T3(DTSBUS[1]),\n .T4(DTSBUS[1]),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(tbyte_out),\n .TCE(1'b1),\n .TFB(\\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ),\n .TQ(\\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_byte_group_io\" *) \nmodule ddr3_if_mig_7series_v4_0_ddr_byte_group_io__parameterized2\n (mem_dqs_out,\n mem_dqs_ts,\n D1,\n D2,\n D3,\n D4,\n D5,\n D6,\n D7,\n D8,\n mem_dq_out,\n mem_dq_ts,\n idelay_ld_rst_2,\n oserdes_clk,\n oserdes_clkdiv,\n po_oserdes_rst,\n DTSBUS,\n oserdes_clk_delayed,\n DQSBUS,\n CTSBUS,\n CLK,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n mem_dq_in,\n idelay_inc,\n LD0_5,\n A_rst_primitives,\n A_rst_primitives_reg,\n CLKB0_9,\n iserdes_clkdiv,\n of_dqbus,\n rst_r4,\n \\gen_byte_sel_div1.calib_in_common_reg_0 ,\n \\calib_sel_reg[0] );\n output [0:0]mem_dqs_out;\n output [0:0]mem_dqs_ts;\n output [3:0]D1;\n output [3:0]D2;\n output [3:0]D3;\n output [3:0]D4;\n output [3:0]D5;\n output [3:0]D6;\n output [3:0]D7;\n output [3:0]D8;\n output [8:0]mem_dq_out;\n output [8:0]mem_dq_ts;\n output idelay_ld_rst_2;\n input oserdes_clk;\n input oserdes_clkdiv;\n input po_oserdes_rst;\n input [1:0]DTSBUS;\n input oserdes_clk_delayed;\n input [1:0]DQSBUS;\n input [0:0]CTSBUS;\n input CLK;\n input \\gen_byte_sel_div1.calib_in_common_reg ;\n input [7:0]mem_dq_in;\n input idelay_inc;\n input LD0_5;\n input A_rst_primitives;\n input A_rst_primitives_reg;\n input CLKB0_9;\n input iserdes_clkdiv;\n input [35:0]of_dqbus;\n input rst_r4;\n input [0:0]\\gen_byte_sel_div1.calib_in_common_reg_0 ;\n input [7:0]\\calib_sel_reg[0] ;\n\n wire A_rst_primitives;\n wire A_rst_primitives_reg;\n wire CLK;\n wire CLKB0_9;\n wire [0:0]CTSBUS;\n wire [3:0]D1;\n wire [3:0]D2;\n wire [3:0]D3;\n wire [3:0]D4;\n wire [3:0]D5;\n wire [3:0]D6;\n wire [3:0]D7;\n wire [3:0]D8;\n wire [1:0]DQSBUS;\n wire [1:0]DTSBUS;\n wire LD0_5;\n wire [7:0]\\calib_sel_reg[0] ;\n wire data_in_dly_1;\n wire data_in_dly_2;\n wire data_in_dly_3;\n wire data_in_dly_4;\n wire data_in_dly_5;\n wire data_in_dly_6;\n wire data_in_dly_7;\n wire data_in_dly_8;\n wire [26:5]fine_delay_r;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire [0:0]\\gen_byte_sel_div1.calib_in_common_reg_0 ;\n wire idelay_inc;\n wire idelay_ld_rst_2;\n wire idelay_ld_rst_i_1__2_n_0;\n wire iserdes_clkdiv;\n wire [7:0]mem_dq_in;\n wire [8:0]mem_dq_out;\n wire [8:0]mem_dq_ts;\n wire [0:0]mem_dqs_out;\n wire [0:0]mem_dqs_ts;\n wire [35:0]of_dqbus;\n wire oserdes_clk;\n wire oserdes_clk_delayed;\n wire oserdes_clkdiv;\n wire po_oserdes_rst;\n wire rst_r4;\n wire tbyte_out;\n wire \\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ;\n wire \\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ;\n wire [4:0]\\NLW_input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire [4:0]\\NLW_input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ;\n wire \\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ;\n\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* __SRVAL = \"FALSE\" *) \n ODDR #(\n .DDR_CLK_EDGE(\"SAME_EDGE\"),\n .INIT(1'b0),\n .IS_C_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .SRTYPE(\"SYNC\")) \n \\dqs_gen.oddr_dqs \n (.C(oserdes_clk_delayed),\n .CE(1'b1),\n .D1(DQSBUS[0]),\n .D2(DQSBUS[1]),\n .Q(mem_dqs_out),\n .R(1'b0),\n .S(\\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* __SRVAL = \"TRUE\" *) \n ODDR #(\n .DDR_CLK_EDGE(\"SAME_EDGE\"),\n .INIT(1'b0),\n .IS_C_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .SRTYPE(\"SYNC\")) \n \\dqs_gen.oddr_dqsts \n (.C(oserdes_clk_delayed),\n .CE(1'b1),\n .D1(CTSBUS),\n .D2(CTSBUS),\n .Q(mem_dqs_ts),\n .R(\\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ),\n .S(1'b0));\n FDRE \\fine_delay_r_reg[11] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[0] [2]),\n .Q(fine_delay_r[11]),\n .R(A_rst_primitives));\n FDRE \\fine_delay_r_reg[14] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[0] [3]),\n .Q(fine_delay_r[14]),\n .R(A_rst_primitives));\n FDRE \\fine_delay_r_reg[17] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[0] [4]),\n .Q(fine_delay_r[17]),\n .R(A_rst_primitives));\n FDRE \\fine_delay_r_reg[20] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[0] [5]),\n .Q(fine_delay_r[20]),\n .R(A_rst_primitives));\n FDRE \\fine_delay_r_reg[23] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[0] [6]),\n .Q(fine_delay_r[23]),\n .R(A_rst_primitives));\n FDRE \\fine_delay_r_reg[26] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[0] [7]),\n .Q(fine_delay_r[26]),\n .R(A_rst_primitives));\n FDRE \\fine_delay_r_reg[5] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[0] [0]),\n .Q(fine_delay_r[5]),\n .R(A_rst_primitives));\n FDRE \\fine_delay_r_reg[8] \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .D(\\calib_sel_reg[0] [1]),\n .Q(fine_delay_r[8]),\n .R(A_rst_primitives));\n LUT2 #(\n .INIT(4'h2)) \n idelay_ld_rst_i_1__2\n (.I0(idelay_ld_rst_2),\n .I1(rst_r4),\n .O(idelay_ld_rst_i_1__2_n_0));\n FDSE idelay_ld_rst_reg\n (.C(CLK),\n .CE(1'b1),\n .D(idelay_ld_rst_i_1__2_n_0),\n .Q(idelay_ld_rst_2),\n .S(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_1),\n .IDATAIN(mem_dq_in[0]),\n .IFDLY({fine_delay_r[5],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_5),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[1].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_9),\n .CLKDIV(\\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[0]),\n .DDLY(data_in_dly_1),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D1[3]),\n .Q2(D1[2]),\n .Q3(D1[1]),\n .Q4(D1[0]),\n .Q5(\\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_2),\n .IDATAIN(mem_dq_in[1]),\n .IFDLY({fine_delay_r[8],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_5),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[2].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_9),\n .CLKDIV(\\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[1]),\n .DDLY(data_in_dly_2),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D2[3]),\n .Q2(D2[2]),\n .Q3(D2[1]),\n .Q4(D2[0]),\n .Q5(\\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_3),\n .IDATAIN(mem_dq_in[2]),\n .IFDLY({fine_delay_r[11],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_5),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[3].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_9),\n .CLKDIV(\\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[2]),\n .DDLY(data_in_dly_3),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D3[3]),\n .Q2(D3[2]),\n .Q3(D3[1]),\n .Q4(D3[0]),\n .Q5(\\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_4),\n .IDATAIN(mem_dq_in[3]),\n .IFDLY({fine_delay_r[14],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_5),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[4].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_9),\n .CLKDIV(\\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[3]),\n .DDLY(data_in_dly_4),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D4[3]),\n .Q2(D4[2]),\n .Q3(D4[1]),\n .Q4(D4[0]),\n .Q5(\\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_5),\n .IDATAIN(mem_dq_in[4]),\n .IFDLY({fine_delay_r[17],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_5),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[5].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_9),\n .CLKDIV(\\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[4]),\n .DDLY(data_in_dly_5),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D5[3]),\n .Q2(D5[2]),\n .Q3(D5[1]),\n .Q4(D5[0]),\n .Q5(\\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_6),\n .IDATAIN(mem_dq_in[5]),\n .IFDLY({fine_delay_r[20],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_5),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[6].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_9),\n .CLKDIV(\\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[5]),\n .DDLY(data_in_dly_6),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D6[3]),\n .Q2(D6[2]),\n .Q3(D6[1]),\n .Q4(D6[0]),\n .Q5(\\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_7),\n .IDATAIN(mem_dq_in[6]),\n .IFDLY({fine_delay_r[23],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_5),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[7].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_9),\n .CLKDIV(\\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[6]),\n .DDLY(data_in_dly_7),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D7[3]),\n .Q2(D7[2]),\n .Q3(D7[1]),\n .Q4(D7[0]),\n .Q5(\\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n IDELAYE2_FINEDELAY #(\n .CINVCTRL_SEL(\"FALSE\"),\n .DELAY_SRC(\"IDATAIN\"),\n .FINEDELAY(\"ADD_DLY\"),\n .HIGH_PERFORMANCE_MODE(\"TRUE\"),\n .IDELAY_TYPE(\"VARIABLE\"),\n .IDELAY_VALUE(0),\n .IS_C_INVERTED(1'b0),\n .IS_DATAIN_INVERTED(1'b0),\n .IS_IDATAIN_INVERTED(1'b0),\n .PIPE_SEL(\"FALSE\"),\n .REFCLK_FREQUENCY(400.000000),\n .SIGNAL_PATTERN(\"DATA\")) \n \\input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2 \n (.C(CLK),\n .CE(\\gen_byte_sel_div1.calib_in_common_reg ),\n .CINVCTRL(1'b0),\n .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .CNTVALUEOUT(\\NLW_input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),\n .DATAIN(1'b0),\n .DATAOUT(data_in_dly_8),\n .IDATAIN(mem_dq_in[7]),\n .IFDLY({fine_delay_r[26],1'b0,1'b0}),\n .INC(idelay_inc),\n .LD(LD0_5),\n .LDPIPEEN(1'b0),\n .REGRST(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n ISERDESE2 #(\n .DATA_RATE(\"DDR\"),\n .DATA_WIDTH(4),\n .DYN_CLKDIV_INV_EN(\"FALSE\"),\n .DYN_CLK_INV_EN(\"FALSE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .INIT_Q3(1'b0),\n .INIT_Q4(1'b0),\n .INTERFACE_TYPE(\"MEMORY_DDR3\"),\n .IOBDELAY(\"IFD\"),\n .IS_CLKB_INVERTED(1'b1),\n .IS_CLKDIVP_INVERTED(1'b0),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .IS_OCLKB_INVERTED(1'b0),\n .IS_OCLK_INVERTED(1'b0),\n .NUM_CE(2),\n .OFB_USED(\"FALSE\"),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_Q1(1'b0),\n .SRVAL_Q2(1'b0),\n .SRVAL_Q3(1'b0),\n .SRVAL_Q4(1'b0)) \n \\input_[8].iserdes_dq_.iserdesdq \n (.BITSLIP(1'b0),\n .CE1(1'b1),\n .CE2(1'b1),\n .CLK(A_rst_primitives_reg),\n .CLKB(CLKB0_9),\n .CLKDIV(\\NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),\n .CLKDIVP(iserdes_clkdiv),\n .D(mem_dq_in[7]),\n .DDLY(data_in_dly_8),\n .DYNCLKDIVSEL(1'b0),\n .DYNCLKSEL(1'b0),\n .O(\\NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ),\n .OCLK(oserdes_clk),\n .OCLKB(\\NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),\n .OFB(\\NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),\n .Q1(D8[3]),\n .Q2(D8[2]),\n .Q3(D8[1]),\n .Q4(D8[0]),\n .Q5(\\NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),\n .Q6(\\NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),\n .Q7(\\NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),\n .Q8(\\NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),\n .RST(1'b0),\n .SHIFTIN1(1'b0),\n .SHIFTIN2(1'b0),\n .SHIFTOUT1(\\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[1].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[0]),\n .D2(of_dqbus[1]),\n .D3(of_dqbus[2]),\n .D4(of_dqbus[3]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[0]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[0]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[2].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[4]),\n .D2(of_dqbus[5]),\n .D3(of_dqbus[6]),\n .D4(of_dqbus[7]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[1]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[1]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[3].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[8]),\n .D2(of_dqbus[9]),\n .D3(of_dqbus[10]),\n .D4(of_dqbus[11]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[2]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[2]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[4].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[12]),\n .D2(of_dqbus[13]),\n .D3(of_dqbus[14]),\n .D4(of_dqbus[15]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[3]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[3]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[5].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[16]),\n .D2(of_dqbus[17]),\n .D3(of_dqbus[18]),\n .D4(of_dqbus[19]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[4]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[4]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[6].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[20]),\n .D2(of_dqbus[21]),\n .D3(of_dqbus[22]),\n .D4(of_dqbus[23]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[5]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[5]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[7].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[24]),\n .D2(of_dqbus[25]),\n .D3(of_dqbus[26]),\n .D4(of_dqbus[27]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[6]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[6]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[8].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[28]),\n .D2(of_dqbus[29]),\n .D3(of_dqbus[30]),\n .D4(of_dqbus[31]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[7]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[7]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(4)) \n \\output_[9].oserdes_dq_.ddr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(of_dqbus[32]),\n .D2(of_dqbus[33]),\n .D3(of_dqbus[34]),\n .D4(of_dqbus[35]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[8]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(mem_dq_ts[8]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"DDR\"),\n .DATA_RATE_TQ(\"DDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b1),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b1),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"TRUE\"),\n .TBYTE_SRC(\"TRUE\"),\n .TRISTATE_WIDTH(4)) \n \\slave_ts.oserdes_slave_ts \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(1'b0),\n .D2(1'b0),\n .D3(1'b0),\n .D4(1'b0),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ),\n .OQ(\\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ),\n .T1(DTSBUS[0]),\n .T2(DTSBUS[0]),\n .T3(DTSBUS[1]),\n .T4(DTSBUS[1]),\n .TBYTEIN(tbyte_out),\n .TBYTEOUT(tbyte_out),\n .TCE(1'b1),\n .TFB(\\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ),\n .TQ(\\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_byte_group_io\" *) \nmodule ddr3_if_mig_7series_v4_0_ddr_byte_group_io__parameterized3\n (mem_dq_out,\n oserdes_clk,\n oserdes_clkdiv,\n oserdes_dq,\n oserdes_rst);\n output [1:0]mem_dq_out;\n input oserdes_clk;\n input oserdes_clkdiv;\n input [7:0]oserdes_dq;\n input oserdes_rst;\n\n wire [1:0]mem_dq_out;\n wire oserdes_clk;\n wire oserdes_clkdiv;\n wire [7:0]oserdes_dq;\n wire oserdes_rst;\n wire \\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[0].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[0]),\n .D2(oserdes_dq[1]),\n .D3(oserdes_dq[2]),\n .D4(oserdes_dq[3]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[0]),\n .RST(oserdes_rst),\n .SHIFTIN1(\\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[1].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[4]),\n .D2(oserdes_dq[5]),\n .D3(oserdes_dq[6]),\n .D4(oserdes_dq[7]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[1]),\n .RST(oserdes_rst),\n .SHIFTIN1(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_byte_group_io\" *) \nmodule ddr3_if_mig_7series_v4_0_ddr_byte_group_io__parameterized4\n (mem_dq_out,\n oserdes_clk,\n oserdes_clkdiv,\n oserdes_dq,\n oserdes_rst);\n output [2:0]mem_dq_out;\n input oserdes_clk;\n input oserdes_clkdiv;\n input [11:0]oserdes_dq;\n input oserdes_rst;\n\n wire [2:0]mem_dq_out;\n wire oserdes_clk;\n wire oserdes_clkdiv;\n wire [11:0]oserdes_dq;\n wire oserdes_rst;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[10].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[4]),\n .D2(oserdes_dq[5]),\n .D3(oserdes_dq[6]),\n .D4(oserdes_dq[7]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[1]),\n .RST(oserdes_rst),\n .SHIFTIN1(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[11].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[8]),\n .D2(oserdes_dq[9]),\n .D3(oserdes_dq[10]),\n .D4(oserdes_dq[11]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[2]),\n .RST(oserdes_rst),\n .SHIFTIN1(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[4].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[0]),\n .D2(oserdes_dq[1]),\n .D3(oserdes_dq[2]),\n .D4(oserdes_dq[3]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[0]),\n .RST(oserdes_rst),\n .SHIFTIN1(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_byte_group_io\" *) \nmodule ddr3_if_mig_7series_v4_0_ddr_byte_group_io__parameterized5\n (mem_dq_out,\n oserdes_clk,\n oserdes_clkdiv,\n oserdes_dq,\n po_oserdes_rst);\n output [9:0]mem_dq_out;\n input oserdes_clk;\n input oserdes_clkdiv;\n input [39:0]oserdes_dq;\n input po_oserdes_rst;\n\n wire [9:0]mem_dq_out;\n wire oserdes_clk;\n wire oserdes_clkdiv;\n wire [39:0]oserdes_dq;\n wire po_oserdes_rst;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[10].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[32]),\n .D2(oserdes_dq[33]),\n .D3(oserdes_dq[34]),\n .D4(oserdes_dq[35]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[8]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[11].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[36]),\n .D2(oserdes_dq[37]),\n .D3(oserdes_dq[38]),\n .D4(oserdes_dq[39]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[9]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[2].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[0]),\n .D2(oserdes_dq[1]),\n .D3(oserdes_dq[2]),\n .D4(oserdes_dq[3]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[0]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[3].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[4]),\n .D2(oserdes_dq[5]),\n .D3(oserdes_dq[6]),\n .D4(oserdes_dq[7]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[1]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[4].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[8]),\n .D2(oserdes_dq[9]),\n .D3(oserdes_dq[10]),\n .D4(oserdes_dq[11]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[2]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[5].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[12]),\n .D2(oserdes_dq[13]),\n .D3(oserdes_dq[14]),\n .D4(oserdes_dq[15]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[3]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[6].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[16]),\n .D2(oserdes_dq[17]),\n .D3(oserdes_dq[18]),\n .D4(oserdes_dq[19]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[4]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[7].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[20]),\n .D2(oserdes_dq[21]),\n .D3(oserdes_dq[22]),\n .D4(oserdes_dq[23]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[5]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[8].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[24]),\n .D2(oserdes_dq[25]),\n .D3(oserdes_dq[26]),\n .D4(oserdes_dq[27]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[6]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[9].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[28]),\n .D2(oserdes_dq[29]),\n .D3(oserdes_dq[30]),\n .D4(oserdes_dq[31]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[7]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_byte_group_io\" *) \nmodule ddr3_if_mig_7series_v4_0_ddr_byte_group_io__parameterized6\n (mem_dq_out,\n oserdes_clk,\n oserdes_clkdiv,\n oserdes_dq,\n po_oserdes_rst);\n output [8:0]mem_dq_out;\n input oserdes_clk;\n input oserdes_clkdiv;\n input [35:0]oserdes_dq;\n input po_oserdes_rst;\n\n wire [8:0]mem_dq_out;\n wire oserdes_clk;\n wire oserdes_clkdiv;\n wire [35:0]oserdes_dq;\n wire po_oserdes_rst;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;\n wire \\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;\n\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[1].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[0]),\n .D2(oserdes_dq[1]),\n .D3(oserdes_dq[2]),\n .D4(oserdes_dq[3]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[0]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[2].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[4]),\n .D2(oserdes_dq[5]),\n .D3(oserdes_dq[6]),\n .D4(oserdes_dq[7]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[1]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[3].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[8]),\n .D2(oserdes_dq[9]),\n .D3(oserdes_dq[10]),\n .D4(oserdes_dq[11]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[2]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[4].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[12]),\n .D2(oserdes_dq[13]),\n .D3(oserdes_dq[14]),\n .D4(oserdes_dq[15]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[3]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[5].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[16]),\n .D2(oserdes_dq[17]),\n .D3(oserdes_dq[18]),\n .D4(oserdes_dq[19]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[4]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[6].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[20]),\n .D2(oserdes_dq[21]),\n .D3(oserdes_dq[22]),\n .D4(oserdes_dq[23]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[5]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[7].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[24]),\n .D2(oserdes_dq[25]),\n .D3(oserdes_dq[26]),\n .D4(oserdes_dq[27]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[6]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[8].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[28]),\n .D2(oserdes_dq[29]),\n .D3(oserdes_dq[30]),\n .D4(oserdes_dq[31]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[7]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n OSERDESE2 #(\n .DATA_RATE_OQ(\"SDR\"),\n .DATA_RATE_TQ(\"SDR\"),\n .DATA_WIDTH(4),\n .INIT_OQ(1'b0),\n .INIT_TQ(1'b1),\n .IS_CLKDIV_INVERTED(1'b0),\n .IS_CLK_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .IS_D3_INVERTED(1'b0),\n .IS_D4_INVERTED(1'b0),\n .IS_D5_INVERTED(1'b0),\n .IS_D6_INVERTED(1'b0),\n .IS_D7_INVERTED(1'b0),\n .IS_D8_INVERTED(1'b0),\n .IS_T1_INVERTED(1'b0),\n .IS_T2_INVERTED(1'b0),\n .IS_T3_INVERTED(1'b0),\n .IS_T4_INVERTED(1'b0),\n .SERDES_MODE(\"MASTER\"),\n .SRVAL_OQ(1'b0),\n .SRVAL_TQ(1'b1),\n .TBYTE_CTL(\"FALSE\"),\n .TBYTE_SRC(\"FALSE\"),\n .TRISTATE_WIDTH(1)) \n \\output_[9].oserdes_dq_.sdr.oserdes_dq_i \n (.CLK(oserdes_clk),\n .CLKDIV(oserdes_clkdiv),\n .D1(oserdes_dq[32]),\n .D2(oserdes_dq[33]),\n .D3(oserdes_dq[34]),\n .D4(oserdes_dq[35]),\n .D5(1'b0),\n .D6(1'b0),\n .D7(1'b0),\n .D8(1'b0),\n .OCE(1'b1),\n .OFB(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),\n .OQ(mem_dq_out[8]),\n .RST(po_oserdes_rst),\n .SHIFTIN1(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),\n .SHIFTIN2(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),\n .SHIFTOUT1(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),\n .SHIFTOUT2(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),\n .T1(1'b0),\n .T2(1'b0),\n .T3(1'b0),\n .T4(1'b0),\n .TBYTEIN(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),\n .TBYTEOUT(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),\n .TCE(1'b1),\n .TFB(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),\n .TQ(\\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_ddr_byte_lane\n (\\pi_dqs_found_lanes_r1_reg[0] ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,\n pi_phase_locked_all_r1_reg,\n COUNTERREADVAL,\n \\po_counter_read_val_reg[8] ,\n mem_dqs_out,\n mem_dqs_ts,\n mem_dq_out,\n mem_dq_ts,\n if_empty_r,\n \\wr_ptr_reg[1] ,\n idelay_ld_rst,\n rst_r4,\n \\not_strict_mode.app_rd_data_reg[252] ,\n \\my_empty_reg[1] ,\n \\data_bytes_r_reg[63] ,\n \\not_strict_mode.app_rd_data_reg[255] ,\n \\not_strict_mode.app_rd_data_reg[254] ,\n \\not_strict_mode.app_rd_data_reg[253] ,\n \\not_strict_mode.app_rd_data_reg[252]_0 ,\n \\not_strict_mode.app_rd_data_reg[251] ,\n \\not_strict_mode.app_rd_data_reg[250] ,\n \\not_strict_mode.app_rd_data_reg[249] ,\n \\not_strict_mode.app_rd_data_reg[248] ,\n \\not_strict_mode.app_rd_data_reg[223] ,\n \\not_strict_mode.app_rd_data_reg[222] ,\n \\not_strict_mode.app_rd_data_reg[221] ,\n \\not_strict_mode.app_rd_data_reg[220] ,\n \\not_strict_mode.app_rd_data_reg[219] ,\n \\not_strict_mode.app_rd_data_reg[218] ,\n \\not_strict_mode.app_rd_data_reg[217] ,\n \\not_strict_mode.app_rd_data_reg[216] ,\n \\not_strict_mode.app_rd_data_reg[191] ,\n \\not_strict_mode.app_rd_data_reg[190] ,\n \\not_strict_mode.app_rd_data_reg[189] ,\n \\not_strict_mode.app_rd_data_reg[188] ,\n \\not_strict_mode.app_rd_data_reg[187] ,\n \\not_strict_mode.app_rd_data_reg[186] ,\n \\not_strict_mode.app_rd_data_reg[185] ,\n \\not_strict_mode.app_rd_data_reg[184] ,\n \\not_strict_mode.app_rd_data_reg[159] ,\n \\not_strict_mode.app_rd_data_reg[158] ,\n \\not_strict_mode.app_rd_data_reg[157] ,\n \\not_strict_mode.app_rd_data_reg[156] ,\n \\not_strict_mode.app_rd_data_reg[155] ,\n \\not_strict_mode.app_rd_data_reg[154] ,\n \\not_strict_mode.app_rd_data_reg[153] ,\n \\not_strict_mode.app_rd_data_reg[152] ,\n \\not_strict_mode.app_rd_data_reg[127] ,\n \\not_strict_mode.app_rd_data_reg[126] ,\n \\not_strict_mode.app_rd_data_reg[125] ,\n \\not_strict_mode.app_rd_data_reg[124] ,\n \\not_strict_mode.app_rd_data_reg[123] ,\n \\not_strict_mode.app_rd_data_reg[122] ,\n \\not_strict_mode.app_rd_data_reg[121] ,\n \\not_strict_mode.app_rd_data_reg[120] ,\n \\not_strict_mode.app_rd_data_reg[95] ,\n \\not_strict_mode.app_rd_data_reg[94] ,\n \\not_strict_mode.app_rd_data_reg[93] ,\n \\not_strict_mode.app_rd_data_reg[92] ,\n \\not_strict_mode.app_rd_data_reg[91] ,\n \\not_strict_mode.app_rd_data_reg[90] ,\n \\not_strict_mode.app_rd_data_reg[89] ,\n \\not_strict_mode.app_rd_data_reg[88] ,\n \\not_strict_mode.app_rd_data_reg[63] ,\n \\not_strict_mode.app_rd_data_reg[62] ,\n \\not_strict_mode.app_rd_data_reg[61] ,\n \\not_strict_mode.app_rd_data_reg[60] ,\n \\not_strict_mode.app_rd_data_reg[59] ,\n \\not_strict_mode.app_rd_data_reg[58] ,\n \\not_strict_mode.app_rd_data_reg[57] ,\n \\not_strict_mode.app_rd_data_reg[56] ,\n \\not_strict_mode.app_rd_data_reg[31] ,\n \\not_strict_mode.app_rd_data_reg[30] ,\n \\not_strict_mode.app_rd_data_reg[29] ,\n \\not_strict_mode.app_rd_data_reg[28] ,\n \\not_strict_mode.app_rd_data_reg[27] ,\n \\not_strict_mode.app_rd_data_reg[26] ,\n \\not_strict_mode.app_rd_data_reg[25] ,\n \\not_strict_mode.app_rd_data_reg[24] ,\n \\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,\n \\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,\n \\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,\n \\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,\n \\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,\n \\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,\n \\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,\n \\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,\n \\not_strict_mode.app_rd_data_reg[255]_0 ,\n \\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ,\n \\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ,\n \\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ,\n \\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ,\n \\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ,\n \\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ,\n \\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ,\n \\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ,\n \\not_strict_mode.app_rd_data_reg[31]_0 ,\n \\not_strict_mode.app_rd_data_reg[31]_1 ,\n \\my_empty_reg[7] ,\n A_byte_rd_en,\n p_0_out,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,\n \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,\n \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,\n \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,\n \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,\n Q,\n phaser_ctl_bus,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n \\calib_sel_reg[0] ,\n pi_en_stg2_f_reg,\n pi_stg2_f_incdec_reg,\n freq_refclk,\n mem_refclk,\n mem_dqs_in,\n A_rst_primitives,\n \\gen_byte_sel_div1.calib_in_common_reg_0 ,\n sync_pulse,\n CLK,\n PCENABLECALIB,\n COUNTERLOADVAL,\n \\gen_byte_sel_div1.calib_in_common_reg_1 ,\n ck_po_stg2_f_en_reg,\n ck_po_stg2_f_indec_reg,\n delay_done_r4_reg,\n \\write_buffer.wr_buf_out_data_reg[255] ,\n \\write_buffer.wr_buf_out_data_reg[254] ,\n \\write_buffer.wr_buf_out_data_reg[253] ,\n \\write_buffer.wr_buf_out_data_reg[252] ,\n \\write_buffer.wr_buf_out_data_reg[251] ,\n \\write_buffer.wr_buf_out_data_reg[250] ,\n \\write_buffer.wr_buf_out_data_reg[249] ,\n \\write_buffer.wr_buf_out_data_reg[248] ,\n \\gen_byte_sel_div1.calib_in_common_reg_2 ,\n mem_dq_in,\n idelay_inc,\n LD0,\n CLKB0,\n phy_if_reset,\n mux_wrdata_en,\n init_calib_complete_reg_rep,\n \\write_buffer.wr_buf_out_data_reg[287] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ,\n \\byte_r_reg[0] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ,\n \\byte_r_reg[1] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ,\n \\rd_mux_sel_r_reg[1] ,\n \\read_fifo.fifo_out_data_r_reg[6] ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,\n A,\n phy_dout,\n E,\n \\fine_delay_mod_reg[23] ,\n D_byte_rd_en,\n B_byte_rd_en,\n if_empty_r_0,\n my_empty,\n \\po_stg2_wrcal_cnt_reg[1] );\n output [0:0]\\pi_dqs_found_lanes_r1_reg[0] ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n output pi_phase_locked_all_r1_reg;\n output [5:0]COUNTERREADVAL;\n output [8:0]\\po_counter_read_val_reg[8] ;\n output [0:0]mem_dqs_out;\n output [0:0]mem_dqs_ts;\n output [8:0]mem_dq_out;\n output [8:0]mem_dq_ts;\n output [0:0]if_empty_r;\n output [0:0]\\wr_ptr_reg[1] ;\n output idelay_ld_rst;\n output rst_r4;\n output \\not_strict_mode.app_rd_data_reg[252] ;\n output \\my_empty_reg[1] ;\n output [63:0]\\data_bytes_r_reg[63] ;\n output \\not_strict_mode.app_rd_data_reg[255] ;\n output \\not_strict_mode.app_rd_data_reg[254] ;\n output \\not_strict_mode.app_rd_data_reg[253] ;\n output \\not_strict_mode.app_rd_data_reg[252]_0 ;\n output \\not_strict_mode.app_rd_data_reg[251] ;\n output \\not_strict_mode.app_rd_data_reg[250] ;\n output \\not_strict_mode.app_rd_data_reg[249] ;\n output \\not_strict_mode.app_rd_data_reg[248] ;\n output \\not_strict_mode.app_rd_data_reg[223] ;\n output \\not_strict_mode.app_rd_data_reg[222] ;\n output \\not_strict_mode.app_rd_data_reg[221] ;\n output \\not_strict_mode.app_rd_data_reg[220] ;\n output \\not_strict_mode.app_rd_data_reg[219] ;\n output \\not_strict_mode.app_rd_data_reg[218] ;\n output \\not_strict_mode.app_rd_data_reg[217] ;\n output \\not_strict_mode.app_rd_data_reg[216] ;\n output \\not_strict_mode.app_rd_data_reg[191] ;\n output \\not_strict_mode.app_rd_data_reg[190] ;\n output \\not_strict_mode.app_rd_data_reg[189] ;\n output \\not_strict_mode.app_rd_data_reg[188] ;\n output \\not_strict_mode.app_rd_data_reg[187] ;\n output \\not_strict_mode.app_rd_data_reg[186] ;\n output \\not_strict_mode.app_rd_data_reg[185] ;\n output \\not_strict_mode.app_rd_data_reg[184] ;\n output \\not_strict_mode.app_rd_data_reg[159] ;\n output \\not_strict_mode.app_rd_data_reg[158] ;\n output \\not_strict_mode.app_rd_data_reg[157] ;\n output \\not_strict_mode.app_rd_data_reg[156] ;\n output \\not_strict_mode.app_rd_data_reg[155] ;\n output \\not_strict_mode.app_rd_data_reg[154] ;\n output \\not_strict_mode.app_rd_data_reg[153] ;\n output \\not_strict_mode.app_rd_data_reg[152] ;\n output \\not_strict_mode.app_rd_data_reg[127] ;\n output \\not_strict_mode.app_rd_data_reg[126] ;\n output \\not_strict_mode.app_rd_data_reg[125] ;\n output \\not_strict_mode.app_rd_data_reg[124] ;\n output \\not_strict_mode.app_rd_data_reg[123] ;\n output \\not_strict_mode.app_rd_data_reg[122] ;\n output \\not_strict_mode.app_rd_data_reg[121] ;\n output \\not_strict_mode.app_rd_data_reg[120] ;\n output \\not_strict_mode.app_rd_data_reg[95] ;\n output \\not_strict_mode.app_rd_data_reg[94] ;\n output \\not_strict_mode.app_rd_data_reg[93] ;\n output \\not_strict_mode.app_rd_data_reg[92] ;\n output \\not_strict_mode.app_rd_data_reg[91] ;\n output \\not_strict_mode.app_rd_data_reg[90] ;\n output \\not_strict_mode.app_rd_data_reg[89] ;\n output \\not_strict_mode.app_rd_data_reg[88] ;\n output \\not_strict_mode.app_rd_data_reg[63] ;\n output \\not_strict_mode.app_rd_data_reg[62] ;\n output \\not_strict_mode.app_rd_data_reg[61] ;\n output \\not_strict_mode.app_rd_data_reg[60] ;\n output \\not_strict_mode.app_rd_data_reg[59] ;\n output \\not_strict_mode.app_rd_data_reg[58] ;\n output \\not_strict_mode.app_rd_data_reg[57] ;\n output \\not_strict_mode.app_rd_data_reg[56] ;\n output \\not_strict_mode.app_rd_data_reg[31] ;\n output \\not_strict_mode.app_rd_data_reg[30] ;\n output \\not_strict_mode.app_rd_data_reg[29] ;\n output \\not_strict_mode.app_rd_data_reg[28] ;\n output \\not_strict_mode.app_rd_data_reg[27] ;\n output \\not_strict_mode.app_rd_data_reg[26] ;\n output \\not_strict_mode.app_rd_data_reg[25] ;\n output \\not_strict_mode.app_rd_data_reg[24] ;\n output \\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n output \\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n output \\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n output \\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n output \\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n output \\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n output \\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n output \\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n output [63:0]\\not_strict_mode.app_rd_data_reg[255]_0 ;\n output \\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ;\n output \\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ;\n output \\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ;\n output \\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ;\n output \\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ;\n output \\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ;\n output \\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ;\n output \\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[31]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[31]_1 ;\n output [63:0]\\my_empty_reg[7] ;\n output A_byte_rd_en;\n output p_0_out;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n output \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n output \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n output \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n output \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n output [2:0]Q;\n input [3:0]phaser_ctl_bus;\n input \\gen_byte_sel_div1.calib_in_common_reg ;\n input \\calib_sel_reg[0] ;\n input pi_en_stg2_f_reg;\n input pi_stg2_f_incdec_reg;\n input freq_refclk;\n input mem_refclk;\n input [0:0]mem_dqs_in;\n input A_rst_primitives;\n input \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n input sync_pulse;\n input CLK;\n input [1:0]PCENABLECALIB;\n input [5:0]COUNTERLOADVAL;\n input \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n input ck_po_stg2_f_en_reg;\n input ck_po_stg2_f_indec_reg;\n input delay_done_r4_reg;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[255] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[254] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[253] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[252] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[251] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[250] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[249] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[248] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n input [7:0]mem_dq_in;\n input idelay_inc;\n input LD0;\n input CLKB0;\n input phy_if_reset;\n input mux_wrdata_en;\n input init_calib_complete_reg_rep;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[287] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;\n input \\byte_r_reg[0] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ;\n input \\byte_r_reg[1] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ;\n input [1:0]\\rd_mux_sel_r_reg[1] ;\n input \\read_fifo.fifo_out_data_r_reg[6] ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n input [1:0]A;\n input [71:0]phy_dout;\n input [0:0]E;\n input [7:0]\\fine_delay_mod_reg[23] ;\n input D_byte_rd_en;\n input B_byte_rd_en;\n input [0:0]if_empty_r_0;\n input [0:0]my_empty;\n input [1:0]\\po_stg2_wrcal_cnt_reg[1] ;\n\n wire [1:0]A;\n wire A_byte_rd_en;\n wire A_rst_primitives;\n wire B_byte_rd_en;\n wire CLK;\n wire CLKB0;\n wire [5:0]COUNTERLOADVAL;\n wire [5:0]COUNTERREADVAL;\n wire D_byte_rd_en;\n wire [0:0]E;\n wire LD0;\n wire [1:0]PCENABLECALIB;\n wire [2:0]Q;\n wire \\byte_r_reg[0] ;\n wire \\byte_r_reg[1] ;\n wire \\calib_sel_reg[0] ;\n wire ck_po_stg2_f_en_reg;\n wire ck_po_stg2_f_indec_reg;\n wire [63:0]\\data_bytes_r_reg[63] ;\n wire delay_done_r4_reg;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2 ;\n wire [7:0]\\fine_delay_mod_reg[23] ;\n wire freq_refclk;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n wire \\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n wire \\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n wire \\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n wire \\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;\n wire \\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n wire \\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n wire \\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n wire \\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ;\n wire idelay_inc;\n wire idelay_ld_rst;\n wire [3:0]if_d0;\n wire [3:0]if_d1;\n wire [3:0]if_d2;\n wire [3:0]if_d3;\n wire [3:0]if_d4;\n wire [3:0]if_d5;\n wire [3:0]if_d6;\n wire [3:0]if_d7;\n wire if_empty_;\n wire [0:0]if_empty_r;\n wire [0:0]if_empty_r_0;\n wire ififo_rst;\n wire ififo_wr_enable;\n wire \\in_fifo_gen.in_fifo_n_0 ;\n wire \\in_fifo_gen.in_fifo_n_1 ;\n wire \\in_fifo_gen.in_fifo_n_3 ;\n wire init_calib_complete_reg_rep;\n wire iserdes_clkdiv;\n wire [7:0]mem_dq_in;\n wire [8:0]mem_dq_out;\n wire [8:0]mem_dq_ts;\n wire [0:0]mem_dqs_in;\n wire [0:0]mem_dqs_out;\n wire [0:0]mem_dqs_ts;\n wire mem_refclk;\n wire mux_wrdata_en;\n wire [0:0]my_empty;\n wire \\my_empty_reg[1] ;\n wire [63:0]\\my_empty_reg[7] ;\n wire \\not_strict_mode.app_rd_data_reg[120] ;\n wire \\not_strict_mode.app_rd_data_reg[121] ;\n wire \\not_strict_mode.app_rd_data_reg[122] ;\n wire \\not_strict_mode.app_rd_data_reg[123] ;\n wire \\not_strict_mode.app_rd_data_reg[124] ;\n wire \\not_strict_mode.app_rd_data_reg[125] ;\n wire \\not_strict_mode.app_rd_data_reg[126] ;\n wire \\not_strict_mode.app_rd_data_reg[127] ;\n wire \\not_strict_mode.app_rd_data_reg[152] ;\n wire \\not_strict_mode.app_rd_data_reg[153] ;\n wire \\not_strict_mode.app_rd_data_reg[154] ;\n wire \\not_strict_mode.app_rd_data_reg[155] ;\n wire \\not_strict_mode.app_rd_data_reg[156] ;\n wire \\not_strict_mode.app_rd_data_reg[157] ;\n wire \\not_strict_mode.app_rd_data_reg[158] ;\n wire \\not_strict_mode.app_rd_data_reg[159] ;\n wire \\not_strict_mode.app_rd_data_reg[184] ;\n wire \\not_strict_mode.app_rd_data_reg[185] ;\n wire \\not_strict_mode.app_rd_data_reg[186] ;\n wire \\not_strict_mode.app_rd_data_reg[187] ;\n wire \\not_strict_mode.app_rd_data_reg[188] ;\n wire \\not_strict_mode.app_rd_data_reg[189] ;\n wire \\not_strict_mode.app_rd_data_reg[190] ;\n wire \\not_strict_mode.app_rd_data_reg[191] ;\n wire \\not_strict_mode.app_rd_data_reg[216] ;\n wire \\not_strict_mode.app_rd_data_reg[217] ;\n wire \\not_strict_mode.app_rd_data_reg[218] ;\n wire \\not_strict_mode.app_rd_data_reg[219] ;\n wire \\not_strict_mode.app_rd_data_reg[220] ;\n wire \\not_strict_mode.app_rd_data_reg[221] ;\n wire \\not_strict_mode.app_rd_data_reg[222] ;\n wire \\not_strict_mode.app_rd_data_reg[223] ;\n wire \\not_strict_mode.app_rd_data_reg[248] ;\n wire \\not_strict_mode.app_rd_data_reg[249] ;\n wire \\not_strict_mode.app_rd_data_reg[24] ;\n wire \\not_strict_mode.app_rd_data_reg[250] ;\n wire \\not_strict_mode.app_rd_data_reg[251] ;\n wire \\not_strict_mode.app_rd_data_reg[252] ;\n wire \\not_strict_mode.app_rd_data_reg[252]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[253] ;\n wire \\not_strict_mode.app_rd_data_reg[254] ;\n wire \\not_strict_mode.app_rd_data_reg[255] ;\n wire [63:0]\\not_strict_mode.app_rd_data_reg[255]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[25] ;\n wire \\not_strict_mode.app_rd_data_reg[26] ;\n wire \\not_strict_mode.app_rd_data_reg[27] ;\n wire \\not_strict_mode.app_rd_data_reg[28] ;\n wire \\not_strict_mode.app_rd_data_reg[29] ;\n wire \\not_strict_mode.app_rd_data_reg[30] ;\n wire \\not_strict_mode.app_rd_data_reg[31] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[31]_0 ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[31]_1 ;\n wire \\not_strict_mode.app_rd_data_reg[56] ;\n wire \\not_strict_mode.app_rd_data_reg[57] ;\n wire \\not_strict_mode.app_rd_data_reg[58] ;\n wire \\not_strict_mode.app_rd_data_reg[59] ;\n wire \\not_strict_mode.app_rd_data_reg[60] ;\n wire \\not_strict_mode.app_rd_data_reg[61] ;\n wire \\not_strict_mode.app_rd_data_reg[62] ;\n wire \\not_strict_mode.app_rd_data_reg[63] ;\n wire \\not_strict_mode.app_rd_data_reg[88] ;\n wire \\not_strict_mode.app_rd_data_reg[89] ;\n wire \\not_strict_mode.app_rd_data_reg[90] ;\n wire \\not_strict_mode.app_rd_data_reg[91] ;\n wire \\not_strict_mode.app_rd_data_reg[92] ;\n wire \\not_strict_mode.app_rd_data_reg[93] ;\n wire \\not_strict_mode.app_rd_data_reg[94] ;\n wire \\not_strict_mode.app_rd_data_reg[95] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n wire [7:0]of_d9;\n wire [39:0]of_dqbus;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ;\n wire ofifo_rst;\n wire oserdes_clk;\n wire oserdes_clk_delayed;\n wire oserdes_clkdiv;\n wire [1:0]oserdes_dq_ts;\n wire [1:0]oserdes_dqs;\n wire [1:0]oserdes_dqs_ts;\n wire out_fifo_n_0;\n wire out_fifo_n_1;\n wire out_fifo_n_2;\n wire out_fifo_n_3;\n wire p_0_out;\n wire [3:0]phaser_ctl_bus;\n wire \\phaser_in_gen.phaser_in_n_1 ;\n wire \\phaser_in_gen.phaser_in_n_2 ;\n wire \\phaser_in_gen.phaser_in_n_5 ;\n wire \\phaser_in_gen.phaser_in_n_7 ;\n wire phaser_out_n_0;\n wire phaser_out_n_1;\n wire [71:0]phy_dout;\n wire phy_if_reset;\n wire [0:0]\\pi_dqs_found_lanes_r1_reg[0] ;\n wire pi_en_stg2_f_reg;\n wire pi_phase_locked_all_r1_reg;\n wire pi_stg2_f_incdec_reg;\n wire [8:0]\\po_counter_read_val_reg[8] ;\n wire po_oserdes_rst;\n wire po_rd_enable;\n wire [1:0]\\po_stg2_wrcal_cnt_reg[1] ;\n wire [79:0]rd_data;\n wire [65:1]rd_data_r;\n wire [1:0]\\rd_mux_sel_r_reg[1] ;\n wire \\read_fifo.fifo_out_data_r_reg[6] ;\n wire rst_r4;\n wire sync_pulse;\n wire [0:0]\\wr_ptr_reg[1] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[248] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[249] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[250] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[251] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[252] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[253] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[254] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[255] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[287] ;\n wire [7:4]\\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED ;\n wire [7:4]\\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED ;\n wire [7:4]NLW_out_fifo_Q5_UNCONNECTED;\n wire [7:4]NLW_out_fifo_Q6_UNCONNECTED;\n wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;\n\n ddr3_if_mig_7series_v4_0_ddr_byte_group_io ddr_byte_group_io\n (.A_rst_primitives(A_rst_primitives),\n .A_rst_primitives_reg(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),\n .CLK(CLK),\n .CLKB0(CLKB0),\n .CTSBUS(oserdes_dqs_ts[0]),\n .D0(if_d0),\n .D1(if_d1),\n .D2(if_d2),\n .D3(if_d3),\n .D4(if_d4),\n .D5(if_d5),\n .D6(if_d6),\n .D7(if_d7),\n .DQSBUS(oserdes_dqs),\n .DTSBUS(oserdes_dq_ts),\n .E(E),\n .LD0(LD0),\n .\\fine_delay_mod_reg[23] (\\fine_delay_mod_reg[23] ),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\gen_byte_sel_div1.calib_in_common_reg_2 ),\n .idelay_inc(idelay_inc),\n .idelay_ld_rst(idelay_ld_rst),\n .iserdes_clkdiv(iserdes_clkdiv),\n .mem_dq_in(mem_dq_in),\n .mem_dq_out(mem_dq_out),\n .mem_dq_ts(mem_dq_ts),\n .mem_dqs_out(mem_dqs_out),\n .mem_dqs_ts(mem_dqs_ts),\n .of_dqbus({of_dqbus[39:36],of_dqbus[31:0]}),\n .oserdes_clk(oserdes_clk),\n .oserdes_clk_delayed(oserdes_clk_delayed),\n .oserdes_clkdiv(oserdes_clkdiv),\n .po_oserdes_rst(po_oserdes_rst),\n .rst_r4(rst_r4));\n (* syn_maxfan = \"3\" *) \n FDRE \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(if_empty_),\n .Q(if_empty_r),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[0]),\n .Q(\\not_strict_mode.app_rd_data_reg[31]_0 ),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[10]),\n .Q(rd_data_r[10]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[11]),\n .Q(rd_data_r[11]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[12]),\n .Q(rd_data_r[12]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[13]),\n .Q(rd_data_r[13]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[14]),\n .Q(rd_data_r[14]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[15]),\n .Q(rd_data_r[15]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[16]),\n .Q(rd_data_r[16]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[17]),\n .Q(rd_data_r[17]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[18]),\n .Q(rd_data_r[18]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[19]),\n .Q(rd_data_r[19]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[1]),\n .Q(rd_data_r[1]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[20]),\n .Q(rd_data_r[20]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[21]),\n .Q(rd_data_r[21]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[22]),\n .Q(rd_data_r[22]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[23]),\n .Q(rd_data_r[23]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[24]),\n .Q(rd_data_r[24]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[25]),\n .Q(rd_data_r[25]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[26]),\n .Q(rd_data_r[26]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[27]),\n .Q(rd_data_r[27]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[28]),\n .Q(rd_data_r[28]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[29]),\n .Q(rd_data_r[29]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[2]),\n .Q(rd_data_r[2]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[30]),\n .Q(rd_data_r[30]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[31]),\n .Q(rd_data_r[31]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[32]),\n .Q(rd_data_r[32]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[33]),\n .Q(rd_data_r[33]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[34]),\n .Q(rd_data_r[34]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[35]),\n .Q(rd_data_r[35]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[36]),\n .Q(rd_data_r[36]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[37]),\n .Q(rd_data_r[37]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[38]),\n .Q(rd_data_r[38]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[39]),\n .Q(rd_data_r[39]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[3]),\n .Q(rd_data_r[3]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[40]),\n .Q(rd_data_r[40]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[41]),\n .Q(rd_data_r[41]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[42]),\n .Q(rd_data_r[42]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[43]),\n .Q(rd_data_r[43]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[44]),\n .Q(rd_data_r[44]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[45]),\n .Q(rd_data_r[45]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[46]),\n .Q(rd_data_r[46]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[47]),\n .Q(rd_data_r[47]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[48]),\n .Q(rd_data_r[48]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[49]),\n .Q(rd_data_r[49]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[4]),\n .Q(rd_data_r[4]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[50]),\n .Q(rd_data_r[50]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[51]),\n .Q(rd_data_r[51]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[52]),\n .Q(rd_data_r[52]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[53]),\n .Q(rd_data_r[53]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[54]),\n .Q(rd_data_r[54]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[55]),\n .Q(rd_data_r[55]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[56]),\n .Q(rd_data_r[56]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[57]),\n .Q(rd_data_r[57]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[58]),\n .Q(rd_data_r[58]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[59]),\n .Q(rd_data_r[59]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[5]),\n .Q(rd_data_r[5]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[60]),\n .Q(rd_data_r[60]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[61]),\n .Q(rd_data_r[61]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[62]),\n .Q(rd_data_r[62]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[63]),\n .Q(rd_data_r[63]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[64]),\n .Q(rd_data_r[64]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[65]),\n .Q(rd_data_r[65]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[6]),\n .Q(rd_data_r[6]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[7]),\n .Q(rd_data_r[7]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[8]),\n .Q(rd_data_r[8]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[9]),\n .Q(rd_data_r[9]),\n .R(1'b0));\n ddr3_if_mig_7series_v4_0_ddr_if_post_fifo_8 \\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo \n (.A(A),\n .A_byte_rd_en(A_byte_rd_en),\n .B_byte_rd_en(B_byte_rd_en),\n .CLK(CLK),\n .D_byte_rd_en(D_byte_rd_en),\n .Q({rd_data_r,\\not_strict_mode.app_rd_data_reg[31]_0 }),\n .\\byte_r_reg[0] (\\byte_r_reg[0] ),\n .\\byte_r_reg[1] (\\byte_r_reg[1] ),\n .\\data_bytes_r_reg[63] (\\data_bytes_r_reg[63] ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (if_empty_r),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2 ),\n .\\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] (\\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] (\\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] (\\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] (\\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] (\\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] (\\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] (\\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] (\\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),\n .\\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] (\\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] (\\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] (\\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] (\\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] (\\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] (\\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] (\\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] (\\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),\n .\\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] (\\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] (\\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] (\\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] (\\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] (\\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] (\\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] (\\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] (\\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),\n .\\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] (\\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] (\\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] (\\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] (\\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] (\\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] (\\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] (\\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] (\\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),\n .\\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] (\\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] (\\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] (\\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] (\\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] (\\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] (\\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] (\\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] (\\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),\n .\\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] (\\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] (\\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] (\\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] (\\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] (\\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] (\\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] (\\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] (\\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),\n .\\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] (\\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] (\\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] (\\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] (\\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] (\\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] (\\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] (\\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] (\\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),\n .\\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] (\\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] (\\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] (\\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] (\\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] (\\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] (\\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] (\\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] (\\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),\n .\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] (\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ),\n .\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] (\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ),\n .\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] (\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ),\n .\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] (\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ),\n .if_empty_r_0(if_empty_r_0),\n .ififo_rst(ififo_rst),\n .my_empty(my_empty),\n .\\not_strict_mode.app_rd_data_reg[120] (\\not_strict_mode.app_rd_data_reg[120] ),\n .\\not_strict_mode.app_rd_data_reg[121] (\\not_strict_mode.app_rd_data_reg[121] ),\n .\\not_strict_mode.app_rd_data_reg[122] (\\not_strict_mode.app_rd_data_reg[122] ),\n .\\not_strict_mode.app_rd_data_reg[123] (\\not_strict_mode.app_rd_data_reg[123] ),\n .\\not_strict_mode.app_rd_data_reg[124] (\\not_strict_mode.app_rd_data_reg[124] ),\n .\\not_strict_mode.app_rd_data_reg[125] (\\not_strict_mode.app_rd_data_reg[125] ),\n .\\not_strict_mode.app_rd_data_reg[126] (\\not_strict_mode.app_rd_data_reg[126] ),\n .\\not_strict_mode.app_rd_data_reg[127] (\\not_strict_mode.app_rd_data_reg[127] ),\n .\\not_strict_mode.app_rd_data_reg[152] (\\not_strict_mode.app_rd_data_reg[152] ),\n .\\not_strict_mode.app_rd_data_reg[153] (\\not_strict_mode.app_rd_data_reg[153] ),\n .\\not_strict_mode.app_rd_data_reg[154] (\\not_strict_mode.app_rd_data_reg[154] ),\n .\\not_strict_mode.app_rd_data_reg[155] (\\not_strict_mode.app_rd_data_reg[155] ),\n .\\not_strict_mode.app_rd_data_reg[156] (\\not_strict_mode.app_rd_data_reg[156] ),\n .\\not_strict_mode.app_rd_data_reg[157] (\\not_strict_mode.app_rd_data_reg[157] ),\n .\\not_strict_mode.app_rd_data_reg[158] (\\not_strict_mode.app_rd_data_reg[158] ),\n .\\not_strict_mode.app_rd_data_reg[159] (\\not_strict_mode.app_rd_data_reg[159] ),\n .\\not_strict_mode.app_rd_data_reg[184] (\\not_strict_mode.app_rd_data_reg[184] ),\n .\\not_strict_mode.app_rd_data_reg[185] (\\not_strict_mode.app_rd_data_reg[185] ),\n .\\not_strict_mode.app_rd_data_reg[186] (\\not_strict_mode.app_rd_data_reg[186] ),\n .\\not_strict_mode.app_rd_data_reg[187] (\\not_strict_mode.app_rd_data_reg[187] ),\n .\\not_strict_mode.app_rd_data_reg[188] (\\not_strict_mode.app_rd_data_reg[188] ),\n .\\not_strict_mode.app_rd_data_reg[189] (\\not_strict_mode.app_rd_data_reg[189] ),\n .\\not_strict_mode.app_rd_data_reg[190] (\\not_strict_mode.app_rd_data_reg[190] ),\n .\\not_strict_mode.app_rd_data_reg[191] (\\not_strict_mode.app_rd_data_reg[191] ),\n .\\not_strict_mode.app_rd_data_reg[216] (\\not_strict_mode.app_rd_data_reg[216] ),\n .\\not_strict_mode.app_rd_data_reg[217] (\\not_strict_mode.app_rd_data_reg[217] ),\n .\\not_strict_mode.app_rd_data_reg[218] (\\not_strict_mode.app_rd_data_reg[218] ),\n .\\not_strict_mode.app_rd_data_reg[219] (\\not_strict_mode.app_rd_data_reg[219] ),\n .\\not_strict_mode.app_rd_data_reg[220] (\\not_strict_mode.app_rd_data_reg[220] ),\n .\\not_strict_mode.app_rd_data_reg[221] (\\not_strict_mode.app_rd_data_reg[221] ),\n .\\not_strict_mode.app_rd_data_reg[222] (\\not_strict_mode.app_rd_data_reg[222] ),\n .\\not_strict_mode.app_rd_data_reg[223] (\\not_strict_mode.app_rd_data_reg[223] ),\n .\\not_strict_mode.app_rd_data_reg[248] (\\not_strict_mode.app_rd_data_reg[248] ),\n .\\not_strict_mode.app_rd_data_reg[249] (\\not_strict_mode.app_rd_data_reg[249] ),\n .\\not_strict_mode.app_rd_data_reg[24] (\\not_strict_mode.app_rd_data_reg[24] ),\n .\\not_strict_mode.app_rd_data_reg[250] (\\not_strict_mode.app_rd_data_reg[250] ),\n .\\not_strict_mode.app_rd_data_reg[251] (\\not_strict_mode.app_rd_data_reg[251] ),\n .\\not_strict_mode.app_rd_data_reg[252] (\\not_strict_mode.app_rd_data_reg[252] ),\n .\\not_strict_mode.app_rd_data_reg[252]_0 (\\not_strict_mode.app_rd_data_reg[252]_0 ),\n .\\not_strict_mode.app_rd_data_reg[253] (\\not_strict_mode.app_rd_data_reg[253] ),\n .\\not_strict_mode.app_rd_data_reg[254] (\\not_strict_mode.app_rd_data_reg[254] ),\n .\\not_strict_mode.app_rd_data_reg[255] (\\not_strict_mode.app_rd_data_reg[255] ),\n .\\not_strict_mode.app_rd_data_reg[255]_0 (\\not_strict_mode.app_rd_data_reg[255]_0 ),\n .\\not_strict_mode.app_rd_data_reg[25] (\\not_strict_mode.app_rd_data_reg[25] ),\n .\\not_strict_mode.app_rd_data_reg[26] (\\not_strict_mode.app_rd_data_reg[26] ),\n .\\not_strict_mode.app_rd_data_reg[27] (\\not_strict_mode.app_rd_data_reg[27] ),\n .\\not_strict_mode.app_rd_data_reg[28] (\\not_strict_mode.app_rd_data_reg[28] ),\n .\\not_strict_mode.app_rd_data_reg[29] (\\not_strict_mode.app_rd_data_reg[29] ),\n .\\not_strict_mode.app_rd_data_reg[30] (\\not_strict_mode.app_rd_data_reg[30] ),\n .\\not_strict_mode.app_rd_data_reg[31] (\\not_strict_mode.app_rd_data_reg[31] ),\n .\\not_strict_mode.app_rd_data_reg[31]_0 (\\not_strict_mode.app_rd_data_reg[31]_1 ),\n .\\not_strict_mode.app_rd_data_reg[56] (\\not_strict_mode.app_rd_data_reg[56] ),\n .\\not_strict_mode.app_rd_data_reg[57] (\\not_strict_mode.app_rd_data_reg[57] ),\n .\\not_strict_mode.app_rd_data_reg[58] (\\not_strict_mode.app_rd_data_reg[58] ),\n .\\not_strict_mode.app_rd_data_reg[59] (\\not_strict_mode.app_rd_data_reg[59] ),\n .\\not_strict_mode.app_rd_data_reg[60] (\\not_strict_mode.app_rd_data_reg[60] ),\n .\\not_strict_mode.app_rd_data_reg[61] (\\not_strict_mode.app_rd_data_reg[61] ),\n .\\not_strict_mode.app_rd_data_reg[62] (\\not_strict_mode.app_rd_data_reg[62] ),\n .\\not_strict_mode.app_rd_data_reg[63] (\\not_strict_mode.app_rd_data_reg[63] ),\n .\\not_strict_mode.app_rd_data_reg[88] (\\not_strict_mode.app_rd_data_reg[88] ),\n .\\not_strict_mode.app_rd_data_reg[89] (\\not_strict_mode.app_rd_data_reg[89] ),\n .\\not_strict_mode.app_rd_data_reg[90] (\\not_strict_mode.app_rd_data_reg[90] ),\n .\\not_strict_mode.app_rd_data_reg[91] (\\not_strict_mode.app_rd_data_reg[91] ),\n .\\not_strict_mode.app_rd_data_reg[92] (\\not_strict_mode.app_rd_data_reg[92] ),\n .\\not_strict_mode.app_rd_data_reg[93] (\\not_strict_mode.app_rd_data_reg[93] ),\n .\\not_strict_mode.app_rd_data_reg[94] (\\not_strict_mode.app_rd_data_reg[94] ),\n .\\not_strict_mode.app_rd_data_reg[95] (\\not_strict_mode.app_rd_data_reg[95] ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ),\n .p_0_out(p_0_out),\n .\\po_stg2_wrcal_cnt_reg[1] (\\po_stg2_wrcal_cnt_reg[1] ),\n .\\rd_mux_sel_r_reg[1] (\\rd_mux_sel_r_reg[1] ),\n .\\read_fifo.fifo_out_data_r_reg[6] (\\read_fifo.fifo_out_data_r_reg[6] ),\n .\\wr_ptr_reg[1]_0 (\\wr_ptr_reg[1] ));\n FDSE #(\n .INIT(1'b1)) \n ififo_rst_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .Q(ififo_rst),\n .S(phy_if_reset));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n IN_FIFO #(\n .ALMOST_EMPTY_VALUE(1),\n .ALMOST_FULL_VALUE(1),\n .ARRAY_MODE(\"ARRAY_MODE_4_X_8\"),\n .SYNCHRONOUS_MODE(\"FALSE\")) \n \\in_fifo_gen.in_fifo \n (.ALMOSTEMPTY(\\in_fifo_gen.in_fifo_n_0 ),\n .ALMOSTFULL(\\in_fifo_gen.in_fifo_n_1 ),\n .D0(if_d0),\n .D1(if_d1),\n .D2(if_d2),\n .D3(if_d3),\n .D4(if_d4),\n .D5({\\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED [7:4],if_d5}),\n .D6({\\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED [7:4],if_d6}),\n .D7(if_d7),\n .D8({1'b0,1'b0,1'b0,1'b0}),\n .D9({1'b0,1'b0,1'b0,1'b0}),\n .EMPTY(if_empty_),\n .FULL(\\in_fifo_gen.in_fifo_n_3 ),\n .Q0(rd_data[7:0]),\n .Q1(rd_data[15:8]),\n .Q2(rd_data[23:16]),\n .Q3(rd_data[31:24]),\n .Q4(rd_data[39:32]),\n .Q5(rd_data[47:40]),\n .Q6(rd_data[55:48]),\n .Q7(rd_data[63:56]),\n .Q8(rd_data[71:64]),\n .Q9(rd_data[79:72]),\n .RDCLK(CLK),\n .RDEN(1'b1),\n .RESET(ififo_rst),\n .WRCLK(iserdes_clkdiv),\n .WREN(ififo_wr_enable));\n ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized2 \\of_pre_fifo_gen.u_ddr_of_pre_fifo \n (.CLK(CLK),\n .D8({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }),\n .D9(of_d9),\n .Q(Q),\n .init_calib_complete_reg_rep(init_calib_complete_reg_rep),\n .mux_wrdata_en(mux_wrdata_en),\n .\\my_empty_reg[1]_0 (\\my_empty_reg[1] ),\n .\\my_empty_reg[7]_0 (\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ),\n .\\my_empty_reg[7]_1 (\\my_empty_reg[7] ),\n .ofifo_rst(ofifo_rst),\n .ofifo_rst_reg(out_fifo_n_3),\n .phy_dout(phy_dout),\n .\\write_buffer.wr_buf_out_data_reg[287] (\\write_buffer.wr_buf_out_data_reg[287] ));\n FDSE #(\n .INIT(1'b1)) \n ofifo_rst_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .Q(ofifo_rst),\n .S(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n OUT_FIFO #(\n .ALMOST_EMPTY_VALUE(1),\n .ALMOST_FULL_VALUE(1),\n .ARRAY_MODE(\"ARRAY_MODE_8_X_4\"),\n .OUTPUT_DISABLE(\"FALSE\"),\n .SYNCHRONOUS_MODE(\"FALSE\")) \n out_fifo\n (.ALMOSTEMPTY(out_fifo_n_0),\n .ALMOSTFULL(out_fifo_n_1),\n .D0(\\write_buffer.wr_buf_out_data_reg[255] ),\n .D1(\\write_buffer.wr_buf_out_data_reg[254] ),\n .D2(\\write_buffer.wr_buf_out_data_reg[253] ),\n .D3(\\write_buffer.wr_buf_out_data_reg[252] ),\n .D4(\\write_buffer.wr_buf_out_data_reg[251] ),\n .D5(\\write_buffer.wr_buf_out_data_reg[250] ),\n .D6(\\write_buffer.wr_buf_out_data_reg[249] ),\n .D7(\\write_buffer.wr_buf_out_data_reg[248] ),\n .D8({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }),\n .D9(of_d9),\n .EMPTY(out_fifo_n_2),\n .FULL(out_fifo_n_3),\n .Q0(of_dqbus[3:0]),\n .Q1(of_dqbus[7:4]),\n .Q2(of_dqbus[11:8]),\n .Q3(of_dqbus[15:12]),\n .Q4(of_dqbus[19:16]),\n .Q5({NLW_out_fifo_Q5_UNCONNECTED[7:4],of_dqbus[23:20]}),\n .Q6({NLW_out_fifo_Q6_UNCONNECTED[7:4],of_dqbus[27:24]}),\n .Q7(of_dqbus[31:28]),\n .Q8(of_dqbus[35:32]),\n .Q9(of_dqbus[39:36]),\n .RDCLK(oserdes_clkdiv),\n .RDEN(po_rd_enable),\n .RESET(ofifo_rst),\n .WRCLK(CLK),\n .WREN(\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n PHASER_IN_PHY #(\n .BURST_MODE(\"TRUE\"),\n .CLKOUT_DIV(2),\n .DQS_BIAS_MODE(\"FALSE\"),\n .DQS_FIND_PATTERN(3'b000),\n .FINE_DELAY(33),\n .FREQ_REF_DIV(\"NONE\"),\n .IS_RST_INVERTED(1'b0),\n .MEMREFCLK_PERIOD(1.112000),\n .OUTPUT_CLK_SRC(\"DELAYED_REF\"),\n .PHASEREFCLK_PERIOD(1.112000),\n .REFCLK_PERIOD(1.112000),\n .SEL_CLK_OFFSET(6),\n .SYNC_IN_DIV_RST(\"TRUE\"),\n .WR_CYCLES(\"FALSE\")) \n \\phaser_in_gen.phaser_in \n (.BURSTPENDINGPHY(phaser_ctl_bus[1]),\n .COUNTERLOADEN(\\gen_byte_sel_div1.calib_in_common_reg ),\n .COUNTERLOADVAL(COUNTERLOADVAL),\n .COUNTERREADEN(\\calib_sel_reg[0] ),\n .COUNTERREADVAL(COUNTERREADVAL),\n .DQSFOUND(\\pi_dqs_found_lanes_r1_reg[0] ),\n .DQSOUTOFRANGE(\\phaser_in_gen.phaser_in_n_1 ),\n .ENCALIBPHY(PCENABLECALIB),\n .FINEENABLE(pi_en_stg2_f_reg),\n .FINEINC(pi_stg2_f_incdec_reg),\n .FINEOVERFLOW(\\phaser_in_gen.phaser_in_n_2 ),\n .FREQREFCLK(freq_refclk),\n .ICLK(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),\n .ICLKDIV(iserdes_clkdiv),\n .ISERDESRST(\\phaser_in_gen.phaser_in_n_5 ),\n .MEMREFCLK(mem_refclk),\n .PHASELOCKED(pi_phase_locked_all_r1_reg),\n .PHASEREFCLK(mem_dqs_in),\n .RANKSELPHY(phaser_ctl_bus[3:2]),\n .RCLK(\\phaser_in_gen.phaser_in_n_7 ),\n .RST(A_rst_primitives),\n .RSTDQSFIND(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .SYNCIN(sync_pulse),\n .SYSCLK(CLK),\n .WRENABLE(ififo_wr_enable));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n PHASER_OUT_PHY #(\n .CLKOUT_DIV(2),\n .COARSE_BYPASS(\"FALSE\"),\n .COARSE_DELAY(0),\n .DATA_CTL_N(\"TRUE\"),\n .DATA_RD_CYCLES(\"FALSE\"),\n .FINE_DELAY(60),\n .IS_RST_INVERTED(1'b0),\n .MEMREFCLK_PERIOD(1.112000),\n .OCLKDELAY_INV(\"TRUE\"),\n .OCLK_DELAY(28),\n .OUTPUT_CLK_SRC(\"DELAYED_REF\"),\n .PHASEREFCLK_PERIOD(1.000000),\n .PO(3'b111),\n .REFCLK_PERIOD(1.112000),\n .SYNC_IN_DIV_RST(\"TRUE\")) \n phaser_out\n (.BURSTPENDINGPHY(phaser_ctl_bus[0]),\n .COARSEENABLE(\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .COARSEINC(\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .COARSEOVERFLOW(phaser_out_n_0),\n .COUNTERLOADEN(1'b0),\n .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .COUNTERREADEN(\\calib_sel_reg[0] ),\n .COUNTERREADVAL(\\po_counter_read_val_reg[8] ),\n .CTSBUS(oserdes_dqs_ts),\n .DQSBUS(oserdes_dqs),\n .DTSBUS(oserdes_dq_ts),\n .ENCALIBPHY(PCENABLECALIB),\n .FINEENABLE(ck_po_stg2_f_en_reg),\n .FINEINC(ck_po_stg2_f_indec_reg),\n .FINEOVERFLOW(phaser_out_n_1),\n .FREQREFCLK(freq_refclk),\n .MEMREFCLK(mem_refclk),\n .OCLK(oserdes_clk),\n .OCLKDELAYED(oserdes_clk_delayed),\n .OCLKDIV(oserdes_clkdiv),\n .OSERDESRST(po_oserdes_rst),\n .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),\n .RDENABLE(po_rd_enable),\n .RST(A_rst_primitives),\n .SELFINEOCLKDELAY(delay_done_r4_reg),\n .SYNCIN(sync_pulse),\n .SYSCLK(CLK));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_byte_lane\" *) \nmodule ddr3_if_mig_7series_v4_0_ddr_byte_lane__parameterized0\n (\\pi_dqs_found_lanes_r1_reg[1] ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,\n B_rclk,\n COUNTERREADVAL,\n \\po_counter_read_val_reg[8] ,\n mem_dqs_out,\n mem_dqs_ts,\n mem_dq_out,\n mem_dq_ts,\n if_empty_r,\n \\rd_ptr_timing_reg[1] ,\n idelay_ld_rst_0,\n \\not_strict_mode.app_rd_data_reg[244] ,\n \\my_empty_reg[1] ,\n rd_buf_we,\n \\not_strict_mode.status_ram.rd_buf_we_r1_reg ,\n phy_rddata_en,\n mux_rd_valid_r_reg,\n \\read_fifo.tail_r_reg[0] ,\n \\not_strict_mode.app_rd_data_reg[247] ,\n \\not_strict_mode.app_rd_data_reg[16] ,\n \\not_strict_mode.app_rd_data_reg[17] ,\n \\not_strict_mode.app_rd_data_reg[18] ,\n \\not_strict_mode.app_rd_data_reg[19] ,\n \\not_strict_mode.app_rd_data_reg[20] ,\n \\not_strict_mode.app_rd_data_reg[21] ,\n \\not_strict_mode.app_rd_data_reg[22] ,\n \\not_strict_mode.app_rd_data_reg[23] ,\n \\not_strict_mode.app_rd_data_reg[48] ,\n \\not_strict_mode.app_rd_data_reg[49] ,\n \\not_strict_mode.app_rd_data_reg[50] ,\n \\not_strict_mode.app_rd_data_reg[51] ,\n \\not_strict_mode.app_rd_data_reg[52] ,\n \\not_strict_mode.app_rd_data_reg[53] ,\n \\not_strict_mode.app_rd_data_reg[54] ,\n \\not_strict_mode.app_rd_data_reg[55] ,\n \\not_strict_mode.app_rd_data_reg[80] ,\n \\not_strict_mode.app_rd_data_reg[81] ,\n \\not_strict_mode.app_rd_data_reg[82] ,\n \\not_strict_mode.app_rd_data_reg[83] ,\n \\not_strict_mode.app_rd_data_reg[84] ,\n \\not_strict_mode.app_rd_data_reg[85] ,\n \\not_strict_mode.app_rd_data_reg[86] ,\n \\not_strict_mode.app_rd_data_reg[87] ,\n \\not_strict_mode.app_rd_data_reg[112] ,\n \\not_strict_mode.app_rd_data_reg[113] ,\n \\not_strict_mode.app_rd_data_reg[114] ,\n \\not_strict_mode.app_rd_data_reg[115] ,\n \\not_strict_mode.app_rd_data_reg[116] ,\n \\not_strict_mode.app_rd_data_reg[117] ,\n \\not_strict_mode.app_rd_data_reg[118] ,\n \\not_strict_mode.app_rd_data_reg[119] ,\n \\not_strict_mode.app_rd_data_reg[144] ,\n \\not_strict_mode.app_rd_data_reg[145] ,\n \\not_strict_mode.app_rd_data_reg[146] ,\n \\not_strict_mode.app_rd_data_reg[147] ,\n \\not_strict_mode.app_rd_data_reg[148] ,\n \\not_strict_mode.app_rd_data_reg[149] ,\n \\not_strict_mode.app_rd_data_reg[150] ,\n \\not_strict_mode.app_rd_data_reg[151] ,\n \\not_strict_mode.app_rd_data_reg[176] ,\n \\not_strict_mode.app_rd_data_reg[177] ,\n \\not_strict_mode.app_rd_data_reg[178] ,\n \\not_strict_mode.app_rd_data_reg[179] ,\n \\not_strict_mode.app_rd_data_reg[180] ,\n \\not_strict_mode.app_rd_data_reg[181] ,\n \\not_strict_mode.app_rd_data_reg[182] ,\n \\not_strict_mode.app_rd_data_reg[183] ,\n \\not_strict_mode.app_rd_data_reg[208] ,\n \\not_strict_mode.app_rd_data_reg[209] ,\n \\not_strict_mode.app_rd_data_reg[210] ,\n \\not_strict_mode.app_rd_data_reg[211] ,\n \\not_strict_mode.app_rd_data_reg[212] ,\n \\not_strict_mode.app_rd_data_reg[213] ,\n \\not_strict_mode.app_rd_data_reg[214] ,\n \\not_strict_mode.app_rd_data_reg[215] ,\n \\not_strict_mode.app_rd_data_reg[240] ,\n \\not_strict_mode.app_rd_data_reg[241] ,\n \\not_strict_mode.app_rd_data_reg[242] ,\n \\not_strict_mode.app_rd_data_reg[243] ,\n \\not_strict_mode.app_rd_data_reg[244]_0 ,\n \\not_strict_mode.app_rd_data_reg[245] ,\n \\not_strict_mode.app_rd_data_reg[246] ,\n \\not_strict_mode.app_rd_data_reg[247]_0 ,\n pi_phase_locked_all_r1_reg,\n phy_if_empty_r_reg,\n \\not_strict_mode.app_rd_data_reg[23]_0 ,\n \\not_strict_mode.app_rd_data_reg[23]_1 ,\n \\my_empty_reg[7] ,\n B_byte_rd_en,\n Q,\n phaser_ctl_bus,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n \\calib_sel_reg[0] ,\n pi_en_stg2_f_reg,\n pi_stg2_f_incdec_reg,\n freq_refclk,\n mem_refclk,\n mem_dqs_in,\n A_rst_primitives,\n \\gen_byte_sel_div1.calib_in_common_reg_0 ,\n sync_pulse,\n CLK,\n PCENABLECALIB,\n \\calib_zero_inputs_reg[0] ,\n \\gen_byte_sel_div1.calib_in_common_reg_1 ,\n ck_po_stg2_f_en_reg,\n ck_po_stg2_f_indec_reg,\n delay_done_r4_reg,\n \\write_buffer.wr_buf_out_data_reg[247] ,\n \\write_buffer.wr_buf_out_data_reg[246] ,\n \\write_buffer.wr_buf_out_data_reg[245] ,\n \\write_buffer.wr_buf_out_data_reg[244] ,\n \\write_buffer.wr_buf_out_data_reg[243] ,\n \\write_buffer.wr_buf_out_data_reg[242] ,\n \\write_buffer.wr_buf_out_data_reg[241] ,\n \\write_buffer.wr_buf_out_data_reg[240] ,\n \\gen_byte_sel_div1.calib_in_common_reg_2 ,\n mem_dq_in,\n idelay_inc,\n LD0_3,\n CLKB0_7,\n phy_if_reset,\n mux_wrdata_en,\n rst_r4,\n \\read_fifo.fifo_out_data_r_reg[6] ,\n ram_init_done_r,\n init_calib_complete_reg_rep,\n \\write_buffer.wr_buf_out_data_reg[286] ,\n if_empty_r_0,\n my_empty,\n \\my_empty_reg[4] ,\n prbs_rdlvl_start_reg,\n out,\n tail_r,\n \\read_fifo.fifo_out_data_r_reg[6]_0 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,\n A_rst_primitives_reg,\n A_rst_primitives_reg_0,\n A_rst_primitives_reg_1,\n phy_dout,\n \\gen_byte_sel_div1.calib_in_common_reg_3 ,\n \\calib_sel_reg[0]_0 ,\n D_byte_rd_en,\n A_byte_rd_en);\n output [0:0]\\pi_dqs_found_lanes_r1_reg[1] ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n output B_rclk;\n output [5:0]COUNTERREADVAL;\n output [8:0]\\po_counter_read_val_reg[8] ;\n output [0:0]mem_dqs_out;\n output [0:0]mem_dqs_ts;\n output [8:0]mem_dq_out;\n output [8:0]mem_dq_ts;\n output [0:0]if_empty_r;\n output [0:0]\\rd_ptr_timing_reg[1] ;\n output idelay_ld_rst_0;\n output \\not_strict_mode.app_rd_data_reg[244] ;\n output \\my_empty_reg[1] ;\n output rd_buf_we;\n output \\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n output phy_rddata_en;\n output mux_rd_valid_r_reg;\n output \\read_fifo.tail_r_reg[0] ;\n output [63:0]\\not_strict_mode.app_rd_data_reg[247] ;\n output \\not_strict_mode.app_rd_data_reg[16] ;\n output \\not_strict_mode.app_rd_data_reg[17] ;\n output \\not_strict_mode.app_rd_data_reg[18] ;\n output \\not_strict_mode.app_rd_data_reg[19] ;\n output \\not_strict_mode.app_rd_data_reg[20] ;\n output \\not_strict_mode.app_rd_data_reg[21] ;\n output \\not_strict_mode.app_rd_data_reg[22] ;\n output \\not_strict_mode.app_rd_data_reg[23] ;\n output \\not_strict_mode.app_rd_data_reg[48] ;\n output \\not_strict_mode.app_rd_data_reg[49] ;\n output \\not_strict_mode.app_rd_data_reg[50] ;\n output \\not_strict_mode.app_rd_data_reg[51] ;\n output \\not_strict_mode.app_rd_data_reg[52] ;\n output \\not_strict_mode.app_rd_data_reg[53] ;\n output \\not_strict_mode.app_rd_data_reg[54] ;\n output \\not_strict_mode.app_rd_data_reg[55] ;\n output \\not_strict_mode.app_rd_data_reg[80] ;\n output \\not_strict_mode.app_rd_data_reg[81] ;\n output \\not_strict_mode.app_rd_data_reg[82] ;\n output \\not_strict_mode.app_rd_data_reg[83] ;\n output \\not_strict_mode.app_rd_data_reg[84] ;\n output \\not_strict_mode.app_rd_data_reg[85] ;\n output \\not_strict_mode.app_rd_data_reg[86] ;\n output \\not_strict_mode.app_rd_data_reg[87] ;\n output \\not_strict_mode.app_rd_data_reg[112] ;\n output \\not_strict_mode.app_rd_data_reg[113] ;\n output \\not_strict_mode.app_rd_data_reg[114] ;\n output \\not_strict_mode.app_rd_data_reg[115] ;\n output \\not_strict_mode.app_rd_data_reg[116] ;\n output \\not_strict_mode.app_rd_data_reg[117] ;\n output \\not_strict_mode.app_rd_data_reg[118] ;\n output \\not_strict_mode.app_rd_data_reg[119] ;\n output \\not_strict_mode.app_rd_data_reg[144] ;\n output \\not_strict_mode.app_rd_data_reg[145] ;\n output \\not_strict_mode.app_rd_data_reg[146] ;\n output \\not_strict_mode.app_rd_data_reg[147] ;\n output \\not_strict_mode.app_rd_data_reg[148] ;\n output \\not_strict_mode.app_rd_data_reg[149] ;\n output \\not_strict_mode.app_rd_data_reg[150] ;\n output \\not_strict_mode.app_rd_data_reg[151] ;\n output \\not_strict_mode.app_rd_data_reg[176] ;\n output \\not_strict_mode.app_rd_data_reg[177] ;\n output \\not_strict_mode.app_rd_data_reg[178] ;\n output \\not_strict_mode.app_rd_data_reg[179] ;\n output \\not_strict_mode.app_rd_data_reg[180] ;\n output \\not_strict_mode.app_rd_data_reg[181] ;\n output \\not_strict_mode.app_rd_data_reg[182] ;\n output \\not_strict_mode.app_rd_data_reg[183] ;\n output \\not_strict_mode.app_rd_data_reg[208] ;\n output \\not_strict_mode.app_rd_data_reg[209] ;\n output \\not_strict_mode.app_rd_data_reg[210] ;\n output \\not_strict_mode.app_rd_data_reg[211] ;\n output \\not_strict_mode.app_rd_data_reg[212] ;\n output \\not_strict_mode.app_rd_data_reg[213] ;\n output \\not_strict_mode.app_rd_data_reg[214] ;\n output \\not_strict_mode.app_rd_data_reg[215] ;\n output \\not_strict_mode.app_rd_data_reg[240] ;\n output \\not_strict_mode.app_rd_data_reg[241] ;\n output \\not_strict_mode.app_rd_data_reg[242] ;\n output \\not_strict_mode.app_rd_data_reg[243] ;\n output \\not_strict_mode.app_rd_data_reg[244]_0 ;\n output \\not_strict_mode.app_rd_data_reg[245] ;\n output \\not_strict_mode.app_rd_data_reg[246] ;\n output \\not_strict_mode.app_rd_data_reg[247]_0 ;\n output pi_phase_locked_all_r1_reg;\n output phy_if_empty_r_reg;\n output [0:0]\\not_strict_mode.app_rd_data_reg[23]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[23]_1 ;\n output [63:0]\\my_empty_reg[7] ;\n output B_byte_rd_en;\n output [2:0]Q;\n input [3:0]phaser_ctl_bus;\n input \\gen_byte_sel_div1.calib_in_common_reg ;\n input \\calib_sel_reg[0] ;\n input pi_en_stg2_f_reg;\n input pi_stg2_f_incdec_reg;\n input freq_refclk;\n input mem_refclk;\n input [0:0]mem_dqs_in;\n input A_rst_primitives;\n input \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n input sync_pulse;\n input CLK;\n input [1:0]PCENABLECALIB;\n input [5:0]\\calib_zero_inputs_reg[0] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n input ck_po_stg2_f_en_reg;\n input ck_po_stg2_f_indec_reg;\n input delay_done_r4_reg;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[247] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[246] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[245] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[244] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[243] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[242] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[241] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[240] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n input [7:0]mem_dq_in;\n input idelay_inc;\n input LD0_3;\n input CLKB0_7;\n input phy_if_reset;\n input mux_wrdata_en;\n input rst_r4;\n input [0:0]\\read_fifo.fifo_out_data_r_reg[6] ;\n input ram_init_done_r;\n input init_calib_complete_reg_rep;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[286] ;\n input [0:0]if_empty_r_0;\n input [1:0]my_empty;\n input \\my_empty_reg[4] ;\n input prbs_rdlvl_start_reg;\n input out;\n input [0:0]tail_r;\n input \\read_fifo.fifo_out_data_r_reg[6]_0 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n input A_rst_primitives_reg;\n input A_rst_primitives_reg_0;\n input A_rst_primitives_reg_1;\n input [71:0]phy_dout;\n input [0:0]\\gen_byte_sel_div1.calib_in_common_reg_3 ;\n input [7:0]\\calib_sel_reg[0]_0 ;\n input D_byte_rd_en;\n input A_byte_rd_en;\n\n wire A_byte_rd_en;\n wire A_rst_primitives;\n wire A_rst_primitives_reg;\n wire A_rst_primitives_reg_0;\n wire A_rst_primitives_reg_1;\n wire B_byte_rd_en;\n wire B_rclk;\n wire CLK;\n wire CLKB0_7;\n wire [5:0]COUNTERREADVAL;\n wire D_byte_rd_en;\n wire LD0_3;\n wire [1:0]PCENABLECALIB;\n wire [2:0]Q;\n wire \\calib_sel_reg[0] ;\n wire [7:0]\\calib_sel_reg[0]_0 ;\n wire [5:0]\\calib_zero_inputs_reg[0] ;\n wire ck_po_stg2_f_en_reg;\n wire ck_po_stg2_f_indec_reg;\n wire delay_done_r4_reg;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n wire freq_refclk;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n wire [0:0]\\gen_byte_sel_div1.calib_in_common_reg_3 ;\n wire idelay_inc;\n wire idelay_ld_rst_0;\n wire [3:0]if_d1;\n wire [3:0]if_d2;\n wire [3:0]if_d3;\n wire [3:0]if_d4;\n wire [3:0]if_d5;\n wire [3:0]if_d6;\n wire [3:0]if_d7;\n wire [3:0]if_d8;\n wire if_empty_;\n wire [0:0]if_empty_r;\n wire [0:0]if_empty_r_0;\n wire ififo_rst;\n wire ififo_wr_enable;\n wire \\in_fifo_gen.in_fifo_n_0 ;\n wire \\in_fifo_gen.in_fifo_n_1 ;\n wire \\in_fifo_gen.in_fifo_n_3 ;\n wire init_calib_complete_reg_rep;\n wire iserdes_clkdiv;\n wire [7:0]mem_dq_in;\n wire [8:0]mem_dq_out;\n wire [8:0]mem_dq_ts;\n wire [0:0]mem_dqs_in;\n wire [0:0]mem_dqs_out;\n wire [0:0]mem_dqs_ts;\n wire mem_refclk;\n wire mux_rd_valid_r_reg;\n wire mux_wrdata_en;\n wire [1:0]my_empty;\n wire \\my_empty_reg[1] ;\n wire \\my_empty_reg[4] ;\n wire [63:0]\\my_empty_reg[7] ;\n wire \\not_strict_mode.app_rd_data_reg[112] ;\n wire \\not_strict_mode.app_rd_data_reg[113] ;\n wire \\not_strict_mode.app_rd_data_reg[114] ;\n wire \\not_strict_mode.app_rd_data_reg[115] ;\n wire \\not_strict_mode.app_rd_data_reg[116] ;\n wire \\not_strict_mode.app_rd_data_reg[117] ;\n wire \\not_strict_mode.app_rd_data_reg[118] ;\n wire \\not_strict_mode.app_rd_data_reg[119] ;\n wire \\not_strict_mode.app_rd_data_reg[144] ;\n wire \\not_strict_mode.app_rd_data_reg[145] ;\n wire \\not_strict_mode.app_rd_data_reg[146] ;\n wire \\not_strict_mode.app_rd_data_reg[147] ;\n wire \\not_strict_mode.app_rd_data_reg[148] ;\n wire \\not_strict_mode.app_rd_data_reg[149] ;\n wire \\not_strict_mode.app_rd_data_reg[150] ;\n wire \\not_strict_mode.app_rd_data_reg[151] ;\n wire \\not_strict_mode.app_rd_data_reg[16] ;\n wire \\not_strict_mode.app_rd_data_reg[176] ;\n wire \\not_strict_mode.app_rd_data_reg[177] ;\n wire \\not_strict_mode.app_rd_data_reg[178] ;\n wire \\not_strict_mode.app_rd_data_reg[179] ;\n wire \\not_strict_mode.app_rd_data_reg[17] ;\n wire \\not_strict_mode.app_rd_data_reg[180] ;\n wire \\not_strict_mode.app_rd_data_reg[181] ;\n wire \\not_strict_mode.app_rd_data_reg[182] ;\n wire \\not_strict_mode.app_rd_data_reg[183] ;\n wire \\not_strict_mode.app_rd_data_reg[18] ;\n wire \\not_strict_mode.app_rd_data_reg[19] ;\n wire \\not_strict_mode.app_rd_data_reg[208] ;\n wire \\not_strict_mode.app_rd_data_reg[209] ;\n wire \\not_strict_mode.app_rd_data_reg[20] ;\n wire \\not_strict_mode.app_rd_data_reg[210] ;\n wire \\not_strict_mode.app_rd_data_reg[211] ;\n wire \\not_strict_mode.app_rd_data_reg[212] ;\n wire \\not_strict_mode.app_rd_data_reg[213] ;\n wire \\not_strict_mode.app_rd_data_reg[214] ;\n wire \\not_strict_mode.app_rd_data_reg[215] ;\n wire \\not_strict_mode.app_rd_data_reg[21] ;\n wire \\not_strict_mode.app_rd_data_reg[22] ;\n wire \\not_strict_mode.app_rd_data_reg[23] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[23]_0 ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[23]_1 ;\n wire \\not_strict_mode.app_rd_data_reg[240] ;\n wire \\not_strict_mode.app_rd_data_reg[241] ;\n wire \\not_strict_mode.app_rd_data_reg[242] ;\n wire \\not_strict_mode.app_rd_data_reg[243] ;\n wire \\not_strict_mode.app_rd_data_reg[244] ;\n wire \\not_strict_mode.app_rd_data_reg[244]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[245] ;\n wire \\not_strict_mode.app_rd_data_reg[246] ;\n wire [63:0]\\not_strict_mode.app_rd_data_reg[247] ;\n wire \\not_strict_mode.app_rd_data_reg[247]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[48] ;\n wire \\not_strict_mode.app_rd_data_reg[49] ;\n wire \\not_strict_mode.app_rd_data_reg[50] ;\n wire \\not_strict_mode.app_rd_data_reg[51] ;\n wire \\not_strict_mode.app_rd_data_reg[52] ;\n wire \\not_strict_mode.app_rd_data_reg[53] ;\n wire \\not_strict_mode.app_rd_data_reg[54] ;\n wire \\not_strict_mode.app_rd_data_reg[55] ;\n wire \\not_strict_mode.app_rd_data_reg[80] ;\n wire \\not_strict_mode.app_rd_data_reg[81] ;\n wire \\not_strict_mode.app_rd_data_reg[82] ;\n wire \\not_strict_mode.app_rd_data_reg[83] ;\n wire \\not_strict_mode.app_rd_data_reg[84] ;\n wire \\not_strict_mode.app_rd_data_reg[85] ;\n wire \\not_strict_mode.app_rd_data_reg[86] ;\n wire \\not_strict_mode.app_rd_data_reg[87] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n wire \\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n wire [7:0]of_d9;\n wire [39:0]of_dqbus;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ;\n wire ofifo_rst;\n wire oserdes_clk;\n wire oserdes_clk_delayed;\n wire oserdes_clkdiv;\n wire [1:0]oserdes_dq_ts;\n wire [1:0]oserdes_dqs;\n wire [1:0]oserdes_dqs_ts;\n wire out;\n wire out_fifo_n_0;\n wire out_fifo_n_1;\n wire out_fifo_n_2;\n wire out_fifo_n_3;\n wire [3:0]phaser_ctl_bus;\n wire \\phaser_in_gen.phaser_in_n_1 ;\n wire \\phaser_in_gen.phaser_in_n_2 ;\n wire \\phaser_in_gen.phaser_in_n_5 ;\n wire \\phaser_in_gen.phaser_in_n_6 ;\n wire phaser_out_n_0;\n wire phaser_out_n_1;\n wire [71:0]phy_dout;\n wire phy_if_empty_r_reg;\n wire phy_if_reset;\n wire phy_rddata_en;\n wire [0:0]\\pi_dqs_found_lanes_r1_reg[1] ;\n wire pi_en_stg2_f_reg;\n wire pi_phase_locked_all_r1_reg;\n wire pi_stg2_f_incdec_reg;\n wire [8:0]\\po_counter_read_val_reg[8] ;\n wire po_oserdes_rst;\n wire po_rd_enable;\n wire prbs_rdlvl_start_reg;\n wire ram_init_done_r;\n wire rd_buf_we;\n wire [79:0]rd_data;\n wire [71:6]rd_data_r;\n wire [0:0]\\rd_ptr_timing_reg[1] ;\n wire [0:0]\\read_fifo.fifo_out_data_r_reg[6] ;\n wire \\read_fifo.fifo_out_data_r_reg[6]_0 ;\n wire \\read_fifo.tail_r_reg[0] ;\n wire rst_r4;\n wire sync_pulse;\n wire [0:0]tail_r;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[240] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[241] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[242] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[243] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[244] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[245] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[246] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[247] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[286] ;\n wire [7:4]\\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED ;\n wire [7:4]\\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED ;\n wire [7:4]NLW_out_fifo_Q5_UNCONNECTED;\n wire [7:4]NLW_out_fifo_Q6_UNCONNECTED;\n wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;\n\n ddr3_if_mig_7series_v4_0_ddr_byte_group_io__parameterized0 ddr_byte_group_io\n (.A_rst_primitives(A_rst_primitives),\n .A_rst_primitives_reg(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),\n .CLK(CLK),\n .CLKB0_7(CLKB0_7),\n .CTSBUS(oserdes_dqs_ts[0]),\n .D1(if_d1),\n .D2(if_d2),\n .D3(if_d3),\n .D4(if_d4),\n .D5(if_d5),\n .D6(if_d6),\n .D7(if_d7),\n .D8(if_d8),\n .DQSBUS(oserdes_dqs),\n .DTSBUS(oserdes_dq_ts),\n .LD0_3(LD0_3),\n .\\calib_sel_reg[0] (\\calib_sel_reg[0]_0 ),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\gen_byte_sel_div1.calib_in_common_reg_2 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_0 (\\gen_byte_sel_div1.calib_in_common_reg_3 ),\n .idelay_inc(idelay_inc),\n .idelay_ld_rst_0(idelay_ld_rst_0),\n .iserdes_clkdiv(iserdes_clkdiv),\n .mem_dq_in(mem_dq_in),\n .mem_dq_out(mem_dq_out),\n .mem_dq_ts(mem_dq_ts),\n .mem_dqs_out(mem_dqs_out),\n .mem_dqs_ts(mem_dqs_ts),\n .of_dqbus(of_dqbus[39:4]),\n .oserdes_clk(oserdes_clk),\n .oserdes_clk_delayed(oserdes_clk_delayed),\n .oserdes_clkdiv(oserdes_clkdiv),\n .po_oserdes_rst(po_oserdes_rst),\n .rst_r4(rst_r4));\n (* syn_maxfan = \"3\" *) \n FDRE \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(if_empty_),\n .Q(if_empty_r),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[10]),\n .Q(rd_data_r[10]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[11]),\n .Q(rd_data_r[11]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[12]),\n .Q(rd_data_r[12]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[13]),\n .Q(rd_data_r[13]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[14]),\n .Q(rd_data_r[14]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[15]),\n .Q(rd_data_r[15]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[16]),\n .Q(rd_data_r[16]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[17]),\n .Q(rd_data_r[17]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[18]),\n .Q(rd_data_r[18]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[19]),\n .Q(rd_data_r[19]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[20]),\n .Q(rd_data_r[20]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[21]),\n .Q(rd_data_r[21]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[22]),\n .Q(rd_data_r[22]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[23]),\n .Q(rd_data_r[23]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[24]),\n .Q(rd_data_r[24]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[25]),\n .Q(rd_data_r[25]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[26]),\n .Q(rd_data_r[26]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[27]),\n .Q(rd_data_r[27]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[28]),\n .Q(rd_data_r[28]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[29]),\n .Q(rd_data_r[29]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[30]),\n .Q(rd_data_r[30]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[31]),\n .Q(rd_data_r[31]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[32]),\n .Q(rd_data_r[32]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[33]),\n .Q(rd_data_r[33]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[34]),\n .Q(rd_data_r[34]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[35]),\n .Q(rd_data_r[35]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[36]),\n .Q(rd_data_r[36]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[37]),\n .Q(rd_data_r[37]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[38]),\n .Q(rd_data_r[38]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[39]),\n .Q(rd_data_r[39]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[40]),\n .Q(rd_data_r[40]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[41]),\n .Q(rd_data_r[41]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[42]),\n .Q(rd_data_r[42]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[43]),\n .Q(rd_data_r[43]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[44]),\n .Q(rd_data_r[44]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[45]),\n .Q(rd_data_r[45]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[46]),\n .Q(rd_data_r[46]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[47]),\n .Q(rd_data_r[47]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[48]),\n .Q(rd_data_r[48]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[49]),\n .Q(rd_data_r[49]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[50]),\n .Q(rd_data_r[50]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[51]),\n .Q(rd_data_r[51]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[52]),\n .Q(rd_data_r[52]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[53]),\n .Q(rd_data_r[53]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[54]),\n .Q(rd_data_r[54]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[55]),\n .Q(rd_data_r[55]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[56]),\n .Q(rd_data_r[56]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[57]),\n .Q(rd_data_r[57]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[58]),\n .Q(rd_data_r[58]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[59]),\n .Q(rd_data_r[59]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[60]),\n .Q(rd_data_r[60]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[61]),\n .Q(rd_data_r[61]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[62]),\n .Q(rd_data_r[62]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[63]),\n .Q(rd_data_r[63]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[64]),\n .Q(rd_data_r[64]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[65]),\n .Q(rd_data_r[65]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[66]),\n .Q(rd_data_r[66]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[67]),\n .Q(rd_data_r[67]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[68]),\n .Q(rd_data_r[68]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[69]),\n .Q(rd_data_r[69]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[6]),\n .Q(rd_data_r[6]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[70]),\n .Q(rd_data_r[70]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[71]),\n .Q(rd_data_r[71]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[7]),\n .Q(rd_data_r[7]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[8]),\n .Q(\\not_strict_mode.app_rd_data_reg[23]_0 ),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[9]),\n .Q(rd_data_r[9]),\n .R(1'b0));\n ddr3_if_mig_7series_v4_0_ddr_if_post_fifo_7 \\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo \n (.A_byte_rd_en(A_byte_rd_en),\n .B_byte_rd_en(B_byte_rd_en),\n .CLK(CLK),\n .D_byte_rd_en(D_byte_rd_en),\n .Q({rd_data_r[71:9],\\not_strict_mode.app_rd_data_reg[23]_0 ,rd_data_r[7:6]}),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (if_empty_r),\n .if_empty_r_0(if_empty_r_0),\n .ififo_rst(ififo_rst),\n .mux_rd_valid_r_reg(mux_rd_valid_r_reg),\n .my_empty(my_empty),\n .\\my_empty_reg[4]_0 (\\my_empty_reg[4] ),\n .\\not_strict_mode.app_rd_data_reg[112] (\\not_strict_mode.app_rd_data_reg[112] ),\n .\\not_strict_mode.app_rd_data_reg[113] (\\not_strict_mode.app_rd_data_reg[113] ),\n .\\not_strict_mode.app_rd_data_reg[114] (\\not_strict_mode.app_rd_data_reg[114] ),\n .\\not_strict_mode.app_rd_data_reg[115] (\\not_strict_mode.app_rd_data_reg[115] ),\n .\\not_strict_mode.app_rd_data_reg[116] (\\not_strict_mode.app_rd_data_reg[116] ),\n .\\not_strict_mode.app_rd_data_reg[117] (\\not_strict_mode.app_rd_data_reg[117] ),\n .\\not_strict_mode.app_rd_data_reg[118] (\\not_strict_mode.app_rd_data_reg[118] ),\n .\\not_strict_mode.app_rd_data_reg[119] (\\not_strict_mode.app_rd_data_reg[119] ),\n .\\not_strict_mode.app_rd_data_reg[144] (\\not_strict_mode.app_rd_data_reg[144] ),\n .\\not_strict_mode.app_rd_data_reg[145] (\\not_strict_mode.app_rd_data_reg[145] ),\n .\\not_strict_mode.app_rd_data_reg[146] (\\not_strict_mode.app_rd_data_reg[146] ),\n .\\not_strict_mode.app_rd_data_reg[147] (\\not_strict_mode.app_rd_data_reg[147] ),\n .\\not_strict_mode.app_rd_data_reg[148] (\\not_strict_mode.app_rd_data_reg[148] ),\n .\\not_strict_mode.app_rd_data_reg[149] (\\not_strict_mode.app_rd_data_reg[149] ),\n .\\not_strict_mode.app_rd_data_reg[150] (\\not_strict_mode.app_rd_data_reg[150] ),\n .\\not_strict_mode.app_rd_data_reg[151] (\\not_strict_mode.app_rd_data_reg[151] ),\n .\\not_strict_mode.app_rd_data_reg[16] (\\not_strict_mode.app_rd_data_reg[16] ),\n .\\not_strict_mode.app_rd_data_reg[176] (\\not_strict_mode.app_rd_data_reg[176] ),\n .\\not_strict_mode.app_rd_data_reg[177] (\\not_strict_mode.app_rd_data_reg[177] ),\n .\\not_strict_mode.app_rd_data_reg[178] (\\not_strict_mode.app_rd_data_reg[178] ),\n .\\not_strict_mode.app_rd_data_reg[179] (\\not_strict_mode.app_rd_data_reg[179] ),\n .\\not_strict_mode.app_rd_data_reg[17] (\\not_strict_mode.app_rd_data_reg[17] ),\n .\\not_strict_mode.app_rd_data_reg[180] (\\not_strict_mode.app_rd_data_reg[180] ),\n .\\not_strict_mode.app_rd_data_reg[181] (\\not_strict_mode.app_rd_data_reg[181] ),\n .\\not_strict_mode.app_rd_data_reg[182] (\\not_strict_mode.app_rd_data_reg[182] ),\n .\\not_strict_mode.app_rd_data_reg[183] (\\not_strict_mode.app_rd_data_reg[183] ),\n .\\not_strict_mode.app_rd_data_reg[18] (\\not_strict_mode.app_rd_data_reg[18] ),\n .\\not_strict_mode.app_rd_data_reg[19] (\\not_strict_mode.app_rd_data_reg[19] ),\n .\\not_strict_mode.app_rd_data_reg[208] (\\not_strict_mode.app_rd_data_reg[208] ),\n .\\not_strict_mode.app_rd_data_reg[209] (\\not_strict_mode.app_rd_data_reg[209] ),\n .\\not_strict_mode.app_rd_data_reg[20] (\\not_strict_mode.app_rd_data_reg[20] ),\n .\\not_strict_mode.app_rd_data_reg[210] (\\not_strict_mode.app_rd_data_reg[210] ),\n .\\not_strict_mode.app_rd_data_reg[211] (\\not_strict_mode.app_rd_data_reg[211] ),\n .\\not_strict_mode.app_rd_data_reg[212] (\\not_strict_mode.app_rd_data_reg[212] ),\n .\\not_strict_mode.app_rd_data_reg[213] (\\not_strict_mode.app_rd_data_reg[213] ),\n .\\not_strict_mode.app_rd_data_reg[214] (\\not_strict_mode.app_rd_data_reg[214] ),\n .\\not_strict_mode.app_rd_data_reg[215] (\\not_strict_mode.app_rd_data_reg[215] ),\n .\\not_strict_mode.app_rd_data_reg[21] (\\not_strict_mode.app_rd_data_reg[21] ),\n .\\not_strict_mode.app_rd_data_reg[22] (\\not_strict_mode.app_rd_data_reg[22] ),\n .\\not_strict_mode.app_rd_data_reg[23] (\\not_strict_mode.app_rd_data_reg[23] ),\n .\\not_strict_mode.app_rd_data_reg[23]_0 (\\not_strict_mode.app_rd_data_reg[23]_1 ),\n .\\not_strict_mode.app_rd_data_reg[240] (\\not_strict_mode.app_rd_data_reg[240] ),\n .\\not_strict_mode.app_rd_data_reg[241] (\\not_strict_mode.app_rd_data_reg[241] ),\n .\\not_strict_mode.app_rd_data_reg[242] (\\not_strict_mode.app_rd_data_reg[242] ),\n .\\not_strict_mode.app_rd_data_reg[243] (\\not_strict_mode.app_rd_data_reg[243] ),\n .\\not_strict_mode.app_rd_data_reg[244] (\\not_strict_mode.app_rd_data_reg[244] ),\n .\\not_strict_mode.app_rd_data_reg[244]_0 (\\not_strict_mode.app_rd_data_reg[244]_0 ),\n .\\not_strict_mode.app_rd_data_reg[245] (\\not_strict_mode.app_rd_data_reg[245] ),\n .\\not_strict_mode.app_rd_data_reg[246] (\\not_strict_mode.app_rd_data_reg[246] ),\n .\\not_strict_mode.app_rd_data_reg[247] (\\not_strict_mode.app_rd_data_reg[247] ),\n .\\not_strict_mode.app_rd_data_reg[247]_0 (\\not_strict_mode.app_rd_data_reg[247]_0 ),\n .\\not_strict_mode.app_rd_data_reg[48] (\\not_strict_mode.app_rd_data_reg[48] ),\n .\\not_strict_mode.app_rd_data_reg[49] (\\not_strict_mode.app_rd_data_reg[49] ),\n .\\not_strict_mode.app_rd_data_reg[50] (\\not_strict_mode.app_rd_data_reg[50] ),\n .\\not_strict_mode.app_rd_data_reg[51] (\\not_strict_mode.app_rd_data_reg[51] ),\n .\\not_strict_mode.app_rd_data_reg[52] (\\not_strict_mode.app_rd_data_reg[52] ),\n .\\not_strict_mode.app_rd_data_reg[53] (\\not_strict_mode.app_rd_data_reg[53] ),\n .\\not_strict_mode.app_rd_data_reg[54] (\\not_strict_mode.app_rd_data_reg[54] ),\n .\\not_strict_mode.app_rd_data_reg[55] (\\not_strict_mode.app_rd_data_reg[55] ),\n .\\not_strict_mode.app_rd_data_reg[80] (\\not_strict_mode.app_rd_data_reg[80] ),\n .\\not_strict_mode.app_rd_data_reg[81] (\\not_strict_mode.app_rd_data_reg[81] ),\n .\\not_strict_mode.app_rd_data_reg[82] (\\not_strict_mode.app_rd_data_reg[82] ),\n .\\not_strict_mode.app_rd_data_reg[83] (\\not_strict_mode.app_rd_data_reg[83] ),\n .\\not_strict_mode.app_rd_data_reg[84] (\\not_strict_mode.app_rd_data_reg[84] ),\n .\\not_strict_mode.app_rd_data_reg[85] (\\not_strict_mode.app_rd_data_reg[85] ),\n .\\not_strict_mode.app_rd_data_reg[86] (\\not_strict_mode.app_rd_data_reg[86] ),\n .\\not_strict_mode.app_rd_data_reg[87] (\\not_strict_mode.app_rd_data_reg[87] ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ),\n .\\not_strict_mode.status_ram.rd_buf_we_r1_reg (\\not_strict_mode.status_ram.rd_buf_we_r1_reg ),\n .out(out),\n .phy_if_empty_r_reg(phy_if_empty_r_reg),\n .phy_rddata_en(phy_rddata_en),\n .prbs_rdlvl_start_reg(prbs_rdlvl_start_reg),\n .ram_init_done_r(ram_init_done_r),\n .rd_buf_we(rd_buf_we),\n .\\rd_ptr_timing_reg[1]_0 (\\rd_ptr_timing_reg[1] ),\n .\\read_fifo.fifo_out_data_r_reg[6] (\\read_fifo.fifo_out_data_r_reg[6] ),\n .\\read_fifo.fifo_out_data_r_reg[6]_0 (\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .\\read_fifo.tail_r_reg[0] (\\read_fifo.tail_r_reg[0] ),\n .tail_r(tail_r));\n FDSE #(\n .INIT(1'b1)) \n ififo_rst_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .Q(ififo_rst),\n .S(phy_if_reset));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n IN_FIFO #(\n .ALMOST_EMPTY_VALUE(1),\n .ALMOST_FULL_VALUE(1),\n .ARRAY_MODE(\"ARRAY_MODE_4_X_8\"),\n .SYNCHRONOUS_MODE(\"FALSE\")) \n \\in_fifo_gen.in_fifo \n (.ALMOSTEMPTY(\\in_fifo_gen.in_fifo_n_0 ),\n .ALMOSTFULL(\\in_fifo_gen.in_fifo_n_1 ),\n .D0({1'b0,1'b0,1'b0,1'b0}),\n .D1(if_d1),\n .D2(if_d2),\n .D3(if_d3),\n .D4(if_d4),\n .D5({\\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED [7:4],if_d5}),\n .D6({\\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED [7:4],if_d6}),\n .D7(if_d7),\n .D8(if_d8),\n .D9({1'b0,1'b0,1'b0,1'b0}),\n .EMPTY(if_empty_),\n .FULL(\\in_fifo_gen.in_fifo_n_3 ),\n .Q0(rd_data[7:0]),\n .Q1(rd_data[15:8]),\n .Q2(rd_data[23:16]),\n .Q3(rd_data[31:24]),\n .Q4(rd_data[39:32]),\n .Q5(rd_data[47:40]),\n .Q6(rd_data[55:48]),\n .Q7(rd_data[63:56]),\n .Q8(rd_data[71:64]),\n .Q9(rd_data[79:72]),\n .RDCLK(CLK),\n .RDEN(1'b1),\n .RESET(ififo_rst),\n .WRCLK(iserdes_clkdiv),\n .WREN(ififo_wr_enable));\n ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized3 \\of_pre_fifo_gen.u_ddr_of_pre_fifo \n (.CLK(CLK),\n .D0({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }),\n .D9(of_d9),\n .Q(Q),\n .init_calib_complete_reg_rep(init_calib_complete_reg_rep),\n .mux_wrdata_en(mux_wrdata_en),\n .\\my_empty_reg[1]_0 (\\my_empty_reg[1] ),\n .\\my_empty_reg[7]_0 (\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ),\n .\\my_empty_reg[7]_1 (\\my_empty_reg[7] ),\n .ofifo_rst(ofifo_rst),\n .ofifo_rst_reg(out_fifo_n_3),\n .phy_dout(phy_dout),\n .\\write_buffer.wr_buf_out_data_reg[286] (\\write_buffer.wr_buf_out_data_reg[286] ));\n FDSE #(\n .INIT(1'b1)) \n ofifo_rst_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .Q(ofifo_rst),\n .S(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n OUT_FIFO #(\n .ALMOST_EMPTY_VALUE(1),\n .ALMOST_FULL_VALUE(1),\n .ARRAY_MODE(\"ARRAY_MODE_8_X_4\"),\n .OUTPUT_DISABLE(\"FALSE\"),\n .SYNCHRONOUS_MODE(\"FALSE\")) \n out_fifo\n (.ALMOSTEMPTY(out_fifo_n_0),\n .ALMOSTFULL(out_fifo_n_1),\n .D0({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }),\n .D1(\\write_buffer.wr_buf_out_data_reg[247] ),\n .D2(\\write_buffer.wr_buf_out_data_reg[246] ),\n .D3(\\write_buffer.wr_buf_out_data_reg[245] ),\n .D4(\\write_buffer.wr_buf_out_data_reg[244] ),\n .D5(\\write_buffer.wr_buf_out_data_reg[243] ),\n .D6(\\write_buffer.wr_buf_out_data_reg[242] ),\n .D7(\\write_buffer.wr_buf_out_data_reg[241] ),\n .D8(\\write_buffer.wr_buf_out_data_reg[240] ),\n .D9(of_d9),\n .EMPTY(out_fifo_n_2),\n .FULL(out_fifo_n_3),\n .Q0(of_dqbus[3:0]),\n .Q1(of_dqbus[7:4]),\n .Q2(of_dqbus[11:8]),\n .Q3(of_dqbus[15:12]),\n .Q4(of_dqbus[19:16]),\n .Q5({NLW_out_fifo_Q5_UNCONNECTED[7:4],of_dqbus[23:20]}),\n .Q6({NLW_out_fifo_Q6_UNCONNECTED[7:4],of_dqbus[27:24]}),\n .Q7(of_dqbus[31:28]),\n .Q8(of_dqbus[35:32]),\n .Q9(of_dqbus[39:36]),\n .RDCLK(oserdes_clkdiv),\n .RDEN(po_rd_enable),\n .RESET(ofifo_rst),\n .WRCLK(CLK),\n .WREN(\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n PHASER_IN_PHY #(\n .BURST_MODE(\"TRUE\"),\n .CLKOUT_DIV(2),\n .DQS_BIAS_MODE(\"FALSE\"),\n .DQS_FIND_PATTERN(3'b000),\n .FINE_DELAY(33),\n .FREQ_REF_DIV(\"NONE\"),\n .IS_RST_INVERTED(1'b0),\n .MEMREFCLK_PERIOD(1.112000),\n .OUTPUT_CLK_SRC(\"DELAYED_REF\"),\n .PHASEREFCLK_PERIOD(1.112000),\n .REFCLK_PERIOD(1.112000),\n .SEL_CLK_OFFSET(6),\n .SYNC_IN_DIV_RST(\"TRUE\"),\n .WR_CYCLES(\"FALSE\")) \n \\phaser_in_gen.phaser_in \n (.BURSTPENDINGPHY(phaser_ctl_bus[1]),\n .COUNTERLOADEN(\\gen_byte_sel_div1.calib_in_common_reg ),\n .COUNTERLOADVAL(\\calib_zero_inputs_reg[0] ),\n .COUNTERREADEN(\\calib_sel_reg[0] ),\n .COUNTERREADVAL(COUNTERREADVAL),\n .DQSFOUND(\\pi_dqs_found_lanes_r1_reg[1] ),\n .DQSOUTOFRANGE(\\phaser_in_gen.phaser_in_n_1 ),\n .ENCALIBPHY(PCENABLECALIB),\n .FINEENABLE(pi_en_stg2_f_reg),\n .FINEINC(pi_stg2_f_incdec_reg),\n .FINEOVERFLOW(\\phaser_in_gen.phaser_in_n_2 ),\n .FREQREFCLK(freq_refclk),\n .ICLK(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),\n .ICLKDIV(iserdes_clkdiv),\n .ISERDESRST(\\phaser_in_gen.phaser_in_n_5 ),\n .MEMREFCLK(mem_refclk),\n .PHASELOCKED(\\phaser_in_gen.phaser_in_n_6 ),\n .PHASEREFCLK(mem_dqs_in),\n .RANKSELPHY(phaser_ctl_bus[3:2]),\n .RCLK(B_rclk),\n .RST(A_rst_primitives),\n .RSTDQSFIND(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .SYNCIN(sync_pulse),\n .SYSCLK(CLK),\n .WRENABLE(ififo_wr_enable));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n PHASER_OUT_PHY #(\n .CLKOUT_DIV(2),\n .COARSE_BYPASS(\"FALSE\"),\n .COARSE_DELAY(0),\n .DATA_CTL_N(\"TRUE\"),\n .DATA_RD_CYCLES(\"FALSE\"),\n .FINE_DELAY(60),\n .IS_RST_INVERTED(1'b0),\n .MEMREFCLK_PERIOD(1.112000),\n .OCLKDELAY_INV(\"TRUE\"),\n .OCLK_DELAY(28),\n .OUTPUT_CLK_SRC(\"DELAYED_REF\"),\n .PHASEREFCLK_PERIOD(1.000000),\n .PO(3'b111),\n .REFCLK_PERIOD(1.112000),\n .SYNC_IN_DIV_RST(\"TRUE\")) \n phaser_out\n (.BURSTPENDINGPHY(phaser_ctl_bus[0]),\n .COARSEENABLE(\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .COARSEINC(\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .COARSEOVERFLOW(phaser_out_n_0),\n .COUNTERLOADEN(1'b0),\n .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .COUNTERREADEN(\\calib_sel_reg[0] ),\n .COUNTERREADVAL(\\po_counter_read_val_reg[8] ),\n .CTSBUS(oserdes_dqs_ts),\n .DQSBUS(oserdes_dqs),\n .DTSBUS(oserdes_dq_ts),\n .ENCALIBPHY(PCENABLECALIB),\n .FINEENABLE(ck_po_stg2_f_en_reg),\n .FINEINC(ck_po_stg2_f_indec_reg),\n .FINEOVERFLOW(phaser_out_n_1),\n .FREQREFCLK(freq_refclk),\n .MEMREFCLK(mem_refclk),\n .OCLK(oserdes_clk),\n .OCLKDELAYED(oserdes_clk_delayed),\n .OCLKDIV(oserdes_clkdiv),\n .OSERDESRST(po_oserdes_rst),\n .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),\n .RDENABLE(po_rd_enable),\n .RST(A_rst_primitives),\n .SELFINEOCLKDELAY(delay_done_r4_reg),\n .SYNCIN(sync_pulse),\n .SYSCLK(CLK));\n LUT4 #(\n .INIT(16'h8000)) \n pi_phase_locked_all_inferred_i_1\n (.I0(\\phaser_in_gen.phaser_in_n_6 ),\n .I1(A_rst_primitives_reg),\n .I2(A_rst_primitives_reg_0),\n .I3(A_rst_primitives_reg_1),\n .O(pi_phase_locked_all_r1_reg));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_byte_lane\" *) \nmodule ddr3_if_mig_7series_v4_0_ddr_byte_lane__parameterized1\n (\\pi_dqs_found_lanes_r1_reg[2] ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,\n pi_phase_locked_all_r1_reg,\n COUNTERREADVAL,\n \\po_counter_read_val_reg[8] ,\n mem_dqs_out,\n mem_dqs_ts,\n mem_dq_out,\n mem_dq_ts,\n if_empty_r,\n \\rd_ptr_timing_reg[1] ,\n idelay_ld_rst_1,\n \\not_strict_mode.app_rd_data_reg[236] ,\n \\my_empty_reg[1] ,\n \\not_strict_mode.app_rd_data_reg[239] ,\n \\not_strict_mode.app_rd_data_reg[8] ,\n \\not_strict_mode.app_rd_data_reg[9] ,\n \\not_strict_mode.app_rd_data_reg[10] ,\n \\not_strict_mode.app_rd_data_reg[11] ,\n \\not_strict_mode.app_rd_data_reg[12] ,\n \\not_strict_mode.app_rd_data_reg[13] ,\n \\not_strict_mode.app_rd_data_reg[14] ,\n \\not_strict_mode.app_rd_data_reg[15] ,\n \\not_strict_mode.app_rd_data_reg[40] ,\n \\not_strict_mode.app_rd_data_reg[41] ,\n \\not_strict_mode.app_rd_data_reg[42] ,\n \\not_strict_mode.app_rd_data_reg[43] ,\n \\not_strict_mode.app_rd_data_reg[44] ,\n \\not_strict_mode.app_rd_data_reg[45] ,\n \\not_strict_mode.app_rd_data_reg[46] ,\n \\not_strict_mode.app_rd_data_reg[47] ,\n \\not_strict_mode.app_rd_data_reg[72] ,\n \\not_strict_mode.app_rd_data_reg[73] ,\n \\not_strict_mode.app_rd_data_reg[74] ,\n \\not_strict_mode.app_rd_data_reg[75] ,\n \\not_strict_mode.app_rd_data_reg[76] ,\n \\not_strict_mode.app_rd_data_reg[77] ,\n \\not_strict_mode.app_rd_data_reg[78] ,\n \\not_strict_mode.app_rd_data_reg[79] ,\n \\not_strict_mode.app_rd_data_reg[104] ,\n \\not_strict_mode.app_rd_data_reg[105] ,\n \\not_strict_mode.app_rd_data_reg[106] ,\n \\not_strict_mode.app_rd_data_reg[107] ,\n \\not_strict_mode.app_rd_data_reg[108] ,\n \\not_strict_mode.app_rd_data_reg[109] ,\n \\not_strict_mode.app_rd_data_reg[110] ,\n \\not_strict_mode.app_rd_data_reg[111] ,\n \\not_strict_mode.app_rd_data_reg[136] ,\n \\not_strict_mode.app_rd_data_reg[137] ,\n \\not_strict_mode.app_rd_data_reg[138] ,\n \\not_strict_mode.app_rd_data_reg[139] ,\n \\not_strict_mode.app_rd_data_reg[140] ,\n \\not_strict_mode.app_rd_data_reg[141] ,\n \\not_strict_mode.app_rd_data_reg[142] ,\n \\not_strict_mode.app_rd_data_reg[143] ,\n \\not_strict_mode.app_rd_data_reg[168] ,\n \\not_strict_mode.app_rd_data_reg[169] ,\n \\not_strict_mode.app_rd_data_reg[170] ,\n \\not_strict_mode.app_rd_data_reg[171] ,\n \\not_strict_mode.app_rd_data_reg[172] ,\n \\not_strict_mode.app_rd_data_reg[173] ,\n \\not_strict_mode.app_rd_data_reg[174] ,\n \\not_strict_mode.app_rd_data_reg[175] ,\n \\not_strict_mode.app_rd_data_reg[200] ,\n \\not_strict_mode.app_rd_data_reg[201] ,\n \\not_strict_mode.app_rd_data_reg[202] ,\n \\not_strict_mode.app_rd_data_reg[203] ,\n \\not_strict_mode.app_rd_data_reg[204] ,\n \\not_strict_mode.app_rd_data_reg[205] ,\n \\not_strict_mode.app_rd_data_reg[206] ,\n \\not_strict_mode.app_rd_data_reg[207] ,\n \\not_strict_mode.app_rd_data_reg[232] ,\n \\not_strict_mode.app_rd_data_reg[233] ,\n \\not_strict_mode.app_rd_data_reg[234] ,\n \\not_strict_mode.app_rd_data_reg[235] ,\n \\not_strict_mode.app_rd_data_reg[236]_0 ,\n \\not_strict_mode.app_rd_data_reg[237] ,\n \\not_strict_mode.app_rd_data_reg[238] ,\n \\not_strict_mode.app_rd_data_reg[239]_0 ,\n \\not_strict_mode.app_rd_data_reg[15]_0 ,\n \\not_strict_mode.app_rd_data_reg[15]_1 ,\n \\my_empty_reg[7] ,\n C_byte_rd_en,\n Q,\n phaser_ctl_bus,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n \\calib_sel_reg[1] ,\n pi_en_stg2_f_reg,\n pi_stg2_f_incdec_reg,\n freq_refclk,\n mem_refclk,\n mem_dqs_in,\n A_rst_primitives,\n \\gen_byte_sel_div1.calib_in_common_reg_0 ,\n sync_pulse,\n CLK,\n PCENABLECALIB,\n \\calib_zero_inputs_reg[0] ,\n \\gen_byte_sel_div1.calib_in_common_reg_1 ,\n ck_po_stg2_f_en_reg,\n ck_po_stg2_f_indec_reg,\n delay_done_r4_reg,\n \\write_buffer.wr_buf_out_data_reg[239] ,\n \\write_buffer.wr_buf_out_data_reg[238] ,\n \\write_buffer.wr_buf_out_data_reg[237] ,\n \\write_buffer.wr_buf_out_data_reg[236] ,\n \\write_buffer.wr_buf_out_data_reg[235] ,\n \\write_buffer.wr_buf_out_data_reg[234] ,\n \\write_buffer.wr_buf_out_data_reg[233] ,\n \\write_buffer.wr_buf_out_data_reg[232] ,\n \\gen_byte_sel_div1.calib_in_common_reg_2 ,\n mem_dq_in,\n idelay_inc,\n LD0_4,\n CLKB0_8,\n phy_if_reset,\n mux_wrdata_en,\n rst_r4,\n init_calib_complete_reg_rep,\n \\write_buffer.wr_buf_out_data_reg[285] ,\n \\read_fifo.fifo_out_data_r_reg[6] ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,\n phy_dout,\n \\gen_byte_sel_div1.calib_in_common_reg_3 ,\n \\calib_sel_reg[1]_0 ,\n D_byte_rd_en,\n A_byte_rd_en,\n if_empty_r_0,\n \\my_empty_reg[4] );\n output [0:0]\\pi_dqs_found_lanes_r1_reg[2] ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n output pi_phase_locked_all_r1_reg;\n output [5:0]COUNTERREADVAL;\n output [8:0]\\po_counter_read_val_reg[8] ;\n output [0:0]mem_dqs_out;\n output [0:0]mem_dqs_ts;\n output [8:0]mem_dq_out;\n output [8:0]mem_dq_ts;\n output [0:0]if_empty_r;\n output [1:0]\\rd_ptr_timing_reg[1] ;\n output idelay_ld_rst_1;\n output \\not_strict_mode.app_rd_data_reg[236] ;\n output \\my_empty_reg[1] ;\n output [63:0]\\not_strict_mode.app_rd_data_reg[239] ;\n output \\not_strict_mode.app_rd_data_reg[8] ;\n output \\not_strict_mode.app_rd_data_reg[9] ;\n output \\not_strict_mode.app_rd_data_reg[10] ;\n output \\not_strict_mode.app_rd_data_reg[11] ;\n output \\not_strict_mode.app_rd_data_reg[12] ;\n output \\not_strict_mode.app_rd_data_reg[13] ;\n output \\not_strict_mode.app_rd_data_reg[14] ;\n output \\not_strict_mode.app_rd_data_reg[15] ;\n output \\not_strict_mode.app_rd_data_reg[40] ;\n output \\not_strict_mode.app_rd_data_reg[41] ;\n output \\not_strict_mode.app_rd_data_reg[42] ;\n output \\not_strict_mode.app_rd_data_reg[43] ;\n output \\not_strict_mode.app_rd_data_reg[44] ;\n output \\not_strict_mode.app_rd_data_reg[45] ;\n output \\not_strict_mode.app_rd_data_reg[46] ;\n output \\not_strict_mode.app_rd_data_reg[47] ;\n output \\not_strict_mode.app_rd_data_reg[72] ;\n output \\not_strict_mode.app_rd_data_reg[73] ;\n output \\not_strict_mode.app_rd_data_reg[74] ;\n output \\not_strict_mode.app_rd_data_reg[75] ;\n output \\not_strict_mode.app_rd_data_reg[76] ;\n output \\not_strict_mode.app_rd_data_reg[77] ;\n output \\not_strict_mode.app_rd_data_reg[78] ;\n output \\not_strict_mode.app_rd_data_reg[79] ;\n output \\not_strict_mode.app_rd_data_reg[104] ;\n output \\not_strict_mode.app_rd_data_reg[105] ;\n output \\not_strict_mode.app_rd_data_reg[106] ;\n output \\not_strict_mode.app_rd_data_reg[107] ;\n output \\not_strict_mode.app_rd_data_reg[108] ;\n output \\not_strict_mode.app_rd_data_reg[109] ;\n output \\not_strict_mode.app_rd_data_reg[110] ;\n output \\not_strict_mode.app_rd_data_reg[111] ;\n output \\not_strict_mode.app_rd_data_reg[136] ;\n output \\not_strict_mode.app_rd_data_reg[137] ;\n output \\not_strict_mode.app_rd_data_reg[138] ;\n output \\not_strict_mode.app_rd_data_reg[139] ;\n output \\not_strict_mode.app_rd_data_reg[140] ;\n output \\not_strict_mode.app_rd_data_reg[141] ;\n output \\not_strict_mode.app_rd_data_reg[142] ;\n output \\not_strict_mode.app_rd_data_reg[143] ;\n output \\not_strict_mode.app_rd_data_reg[168] ;\n output \\not_strict_mode.app_rd_data_reg[169] ;\n output \\not_strict_mode.app_rd_data_reg[170] ;\n output \\not_strict_mode.app_rd_data_reg[171] ;\n output \\not_strict_mode.app_rd_data_reg[172] ;\n output \\not_strict_mode.app_rd_data_reg[173] ;\n output \\not_strict_mode.app_rd_data_reg[174] ;\n output \\not_strict_mode.app_rd_data_reg[175] ;\n output \\not_strict_mode.app_rd_data_reg[200] ;\n output \\not_strict_mode.app_rd_data_reg[201] ;\n output \\not_strict_mode.app_rd_data_reg[202] ;\n output \\not_strict_mode.app_rd_data_reg[203] ;\n output \\not_strict_mode.app_rd_data_reg[204] ;\n output \\not_strict_mode.app_rd_data_reg[205] ;\n output \\not_strict_mode.app_rd_data_reg[206] ;\n output \\not_strict_mode.app_rd_data_reg[207] ;\n output \\not_strict_mode.app_rd_data_reg[232] ;\n output \\not_strict_mode.app_rd_data_reg[233] ;\n output \\not_strict_mode.app_rd_data_reg[234] ;\n output \\not_strict_mode.app_rd_data_reg[235] ;\n output \\not_strict_mode.app_rd_data_reg[236]_0 ;\n output \\not_strict_mode.app_rd_data_reg[237] ;\n output \\not_strict_mode.app_rd_data_reg[238] ;\n output \\not_strict_mode.app_rd_data_reg[239]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[15]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[15]_1 ;\n output [63:0]\\my_empty_reg[7] ;\n output C_byte_rd_en;\n output [2:0]Q;\n input [3:0]phaser_ctl_bus;\n input \\gen_byte_sel_div1.calib_in_common_reg ;\n input \\calib_sel_reg[1] ;\n input pi_en_stg2_f_reg;\n input pi_stg2_f_incdec_reg;\n input freq_refclk;\n input mem_refclk;\n input [0:0]mem_dqs_in;\n input A_rst_primitives;\n input \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n input sync_pulse;\n input CLK;\n input [1:0]PCENABLECALIB;\n input [5:0]\\calib_zero_inputs_reg[0] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n input ck_po_stg2_f_en_reg;\n input ck_po_stg2_f_indec_reg;\n input delay_done_r4_reg;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[239] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[238] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[237] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[236] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[235] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[234] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[233] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[232] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n input [7:0]mem_dq_in;\n input idelay_inc;\n input LD0_4;\n input CLKB0_8;\n input phy_if_reset;\n input mux_wrdata_en;\n input rst_r4;\n input init_calib_complete_reg_rep;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[285] ;\n input \\read_fifo.fifo_out_data_r_reg[6] ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n input [71:0]phy_dout;\n input [0:0]\\gen_byte_sel_div1.calib_in_common_reg_3 ;\n input [7:0]\\calib_sel_reg[1]_0 ;\n input D_byte_rd_en;\n input A_byte_rd_en;\n input [0:0]if_empty_r_0;\n input [0:0]\\my_empty_reg[4] ;\n\n wire A_byte_rd_en;\n wire A_rst_primitives;\n wire CLK;\n wire CLKB0_8;\n wire [5:0]COUNTERREADVAL;\n wire C_byte_rd_en;\n wire D_byte_rd_en;\n wire LD0_4;\n wire [1:0]PCENABLECALIB;\n wire [2:0]Q;\n wire \\calib_sel_reg[1] ;\n wire [7:0]\\calib_sel_reg[1]_0 ;\n wire [5:0]\\calib_zero_inputs_reg[0] ;\n wire ck_po_stg2_f_en_reg;\n wire ck_po_stg2_f_indec_reg;\n wire delay_done_r4_reg;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n wire freq_refclk;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n wire [0:0]\\gen_byte_sel_div1.calib_in_common_reg_3 ;\n wire idelay_inc;\n wire idelay_ld_rst_1;\n wire [3:0]if_d1;\n wire [3:0]if_d2;\n wire [3:0]if_d3;\n wire [3:0]if_d4;\n wire [3:0]if_d5;\n wire [3:0]if_d6;\n wire [3:0]if_d7;\n wire [3:0]if_d8;\n wire if_empty_;\n wire [0:0]if_empty_r;\n wire [0:0]if_empty_r_0;\n wire ififo_rst;\n wire ififo_wr_enable;\n wire \\in_fifo_gen.in_fifo_n_0 ;\n wire \\in_fifo_gen.in_fifo_n_1 ;\n wire \\in_fifo_gen.in_fifo_n_3 ;\n wire init_calib_complete_reg_rep;\n wire iserdes_clkdiv;\n wire [7:0]mem_dq_in;\n wire [8:0]mem_dq_out;\n wire [8:0]mem_dq_ts;\n wire [0:0]mem_dqs_in;\n wire [0:0]mem_dqs_out;\n wire [0:0]mem_dqs_ts;\n wire mem_refclk;\n wire mux_wrdata_en;\n wire \\my_empty_reg[1] ;\n wire [0:0]\\my_empty_reg[4] ;\n wire [63:0]\\my_empty_reg[7] ;\n wire \\not_strict_mode.app_rd_data_reg[104] ;\n wire \\not_strict_mode.app_rd_data_reg[105] ;\n wire \\not_strict_mode.app_rd_data_reg[106] ;\n wire \\not_strict_mode.app_rd_data_reg[107] ;\n wire \\not_strict_mode.app_rd_data_reg[108] ;\n wire \\not_strict_mode.app_rd_data_reg[109] ;\n wire \\not_strict_mode.app_rd_data_reg[10] ;\n wire \\not_strict_mode.app_rd_data_reg[110] ;\n wire \\not_strict_mode.app_rd_data_reg[111] ;\n wire \\not_strict_mode.app_rd_data_reg[11] ;\n wire \\not_strict_mode.app_rd_data_reg[12] ;\n wire \\not_strict_mode.app_rd_data_reg[136] ;\n wire \\not_strict_mode.app_rd_data_reg[137] ;\n wire \\not_strict_mode.app_rd_data_reg[138] ;\n wire \\not_strict_mode.app_rd_data_reg[139] ;\n wire \\not_strict_mode.app_rd_data_reg[13] ;\n wire \\not_strict_mode.app_rd_data_reg[140] ;\n wire \\not_strict_mode.app_rd_data_reg[141] ;\n wire \\not_strict_mode.app_rd_data_reg[142] ;\n wire \\not_strict_mode.app_rd_data_reg[143] ;\n wire \\not_strict_mode.app_rd_data_reg[14] ;\n wire \\not_strict_mode.app_rd_data_reg[15] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[15]_0 ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[15]_1 ;\n wire \\not_strict_mode.app_rd_data_reg[168] ;\n wire \\not_strict_mode.app_rd_data_reg[169] ;\n wire \\not_strict_mode.app_rd_data_reg[170] ;\n wire \\not_strict_mode.app_rd_data_reg[171] ;\n wire \\not_strict_mode.app_rd_data_reg[172] ;\n wire \\not_strict_mode.app_rd_data_reg[173] ;\n wire \\not_strict_mode.app_rd_data_reg[174] ;\n wire \\not_strict_mode.app_rd_data_reg[175] ;\n wire \\not_strict_mode.app_rd_data_reg[200] ;\n wire \\not_strict_mode.app_rd_data_reg[201] ;\n wire \\not_strict_mode.app_rd_data_reg[202] ;\n wire \\not_strict_mode.app_rd_data_reg[203] ;\n wire \\not_strict_mode.app_rd_data_reg[204] ;\n wire \\not_strict_mode.app_rd_data_reg[205] ;\n wire \\not_strict_mode.app_rd_data_reg[206] ;\n wire \\not_strict_mode.app_rd_data_reg[207] ;\n wire \\not_strict_mode.app_rd_data_reg[232] ;\n wire \\not_strict_mode.app_rd_data_reg[233] ;\n wire \\not_strict_mode.app_rd_data_reg[234] ;\n wire \\not_strict_mode.app_rd_data_reg[235] ;\n wire \\not_strict_mode.app_rd_data_reg[236] ;\n wire \\not_strict_mode.app_rd_data_reg[236]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[237] ;\n wire \\not_strict_mode.app_rd_data_reg[238] ;\n wire [63:0]\\not_strict_mode.app_rd_data_reg[239] ;\n wire \\not_strict_mode.app_rd_data_reg[239]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[40] ;\n wire \\not_strict_mode.app_rd_data_reg[41] ;\n wire \\not_strict_mode.app_rd_data_reg[42] ;\n wire \\not_strict_mode.app_rd_data_reg[43] ;\n wire \\not_strict_mode.app_rd_data_reg[44] ;\n wire \\not_strict_mode.app_rd_data_reg[45] ;\n wire \\not_strict_mode.app_rd_data_reg[46] ;\n wire \\not_strict_mode.app_rd_data_reg[47] ;\n wire \\not_strict_mode.app_rd_data_reg[72] ;\n wire \\not_strict_mode.app_rd_data_reg[73] ;\n wire \\not_strict_mode.app_rd_data_reg[74] ;\n wire \\not_strict_mode.app_rd_data_reg[75] ;\n wire \\not_strict_mode.app_rd_data_reg[76] ;\n wire \\not_strict_mode.app_rd_data_reg[77] ;\n wire \\not_strict_mode.app_rd_data_reg[78] ;\n wire \\not_strict_mode.app_rd_data_reg[79] ;\n wire \\not_strict_mode.app_rd_data_reg[8] ;\n wire \\not_strict_mode.app_rd_data_reg[9] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n wire [7:0]of_d9;\n wire [39:0]of_dqbus;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ;\n wire ofifo_rst;\n wire oserdes_clk;\n wire oserdes_clk_delayed;\n wire oserdes_clkdiv;\n wire [1:0]oserdes_dq_ts;\n wire [1:0]oserdes_dqs;\n wire [1:0]oserdes_dqs_ts;\n wire out_fifo_n_0;\n wire out_fifo_n_1;\n wire out_fifo_n_2;\n wire out_fifo_n_3;\n wire [3:0]phaser_ctl_bus;\n wire \\phaser_in_gen.phaser_in_n_1 ;\n wire \\phaser_in_gen.phaser_in_n_2 ;\n wire \\phaser_in_gen.phaser_in_n_5 ;\n wire \\phaser_in_gen.phaser_in_n_7 ;\n wire phaser_out_n_0;\n wire phaser_out_n_1;\n wire [71:0]phy_dout;\n wire phy_if_reset;\n wire [0:0]\\pi_dqs_found_lanes_r1_reg[2] ;\n wire pi_en_stg2_f_reg;\n wire pi_phase_locked_all_r1_reg;\n wire pi_stg2_f_incdec_reg;\n wire [8:0]\\po_counter_read_val_reg[8] ;\n wire po_oserdes_rst;\n wire po_rd_enable;\n wire [79:0]rd_data;\n wire [71:6]rd_data_r;\n wire [1:0]\\rd_ptr_timing_reg[1] ;\n wire \\read_fifo.fifo_out_data_r_reg[6] ;\n wire rst_r4;\n wire sync_pulse;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[232] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[233] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[234] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[235] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[236] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[237] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[238] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[239] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[285] ;\n wire [7:4]\\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED ;\n wire [7:4]\\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED ;\n wire [7:4]NLW_out_fifo_Q5_UNCONNECTED;\n wire [7:4]NLW_out_fifo_Q6_UNCONNECTED;\n wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;\n\n ddr3_if_mig_7series_v4_0_ddr_byte_group_io__parameterized1 ddr_byte_group_io\n (.A_rst_primitives(A_rst_primitives),\n .A_rst_primitives_reg(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),\n .CLK(CLK),\n .CLKB0_8(CLKB0_8),\n .CTSBUS(oserdes_dqs_ts[0]),\n .D1(if_d1),\n .D2(if_d2),\n .D3(if_d3),\n .D4(if_d4),\n .D5(if_d5),\n .D6(if_d6),\n .D7(if_d7),\n .D8(if_d8),\n .DQSBUS(oserdes_dqs),\n .DTSBUS(oserdes_dq_ts),\n .LD0_4(LD0_4),\n .\\calib_sel_reg[1] (\\calib_sel_reg[1]_0 ),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\gen_byte_sel_div1.calib_in_common_reg_2 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_0 (\\gen_byte_sel_div1.calib_in_common_reg_3 ),\n .idelay_inc(idelay_inc),\n .idelay_ld_rst_1(idelay_ld_rst_1),\n .iserdes_clkdiv(iserdes_clkdiv),\n .mem_dq_in(mem_dq_in),\n .mem_dq_out(mem_dq_out),\n .mem_dq_ts(mem_dq_ts),\n .mem_dqs_out(mem_dqs_out),\n .mem_dqs_ts(mem_dqs_ts),\n .of_dqbus(of_dqbus[39:4]),\n .oserdes_clk(oserdes_clk),\n .oserdes_clk_delayed(oserdes_clk_delayed),\n .oserdes_clkdiv(oserdes_clkdiv),\n .po_oserdes_rst(po_oserdes_rst),\n .rst_r4(rst_r4));\n (* syn_maxfan = \"3\" *) \n FDRE \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(if_empty_),\n .Q(if_empty_r),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[10]),\n .Q(rd_data_r[10]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[11]),\n .Q(rd_data_r[11]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[12]),\n .Q(rd_data_r[12]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[13]),\n .Q(rd_data_r[13]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[14]),\n .Q(rd_data_r[14]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[15]),\n .Q(rd_data_r[15]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[16]),\n .Q(rd_data_r[16]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[17]),\n .Q(rd_data_r[17]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[18]),\n .Q(rd_data_r[18]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[19]),\n .Q(rd_data_r[19]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[20]),\n .Q(rd_data_r[20]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[21]),\n .Q(rd_data_r[21]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[22]),\n .Q(rd_data_r[22]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[23]),\n .Q(rd_data_r[23]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[24]),\n .Q(rd_data_r[24]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[25]),\n .Q(rd_data_r[25]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[26]),\n .Q(rd_data_r[26]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[27]),\n .Q(rd_data_r[27]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[28]),\n .Q(rd_data_r[28]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[29]),\n .Q(rd_data_r[29]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[30]),\n .Q(rd_data_r[30]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[31]),\n .Q(rd_data_r[31]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[32]),\n .Q(rd_data_r[32]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[33]),\n .Q(rd_data_r[33]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[34]),\n .Q(rd_data_r[34]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[35]),\n .Q(rd_data_r[35]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[36]),\n .Q(rd_data_r[36]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[37]),\n .Q(rd_data_r[37]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[38]),\n .Q(rd_data_r[38]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[39]),\n .Q(rd_data_r[39]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[40]),\n .Q(rd_data_r[40]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[41]),\n .Q(rd_data_r[41]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[42]),\n .Q(rd_data_r[42]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[43]),\n .Q(rd_data_r[43]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[44]),\n .Q(rd_data_r[44]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[45]),\n .Q(rd_data_r[45]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[46]),\n .Q(rd_data_r[46]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[47]),\n .Q(rd_data_r[47]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[48]),\n .Q(rd_data_r[48]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[49]),\n .Q(rd_data_r[49]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[50]),\n .Q(rd_data_r[50]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[51]),\n .Q(rd_data_r[51]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[52]),\n .Q(rd_data_r[52]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[53]),\n .Q(rd_data_r[53]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[54]),\n .Q(rd_data_r[54]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[55]),\n .Q(rd_data_r[55]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[56]),\n .Q(rd_data_r[56]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[57]),\n .Q(rd_data_r[57]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[58]),\n .Q(rd_data_r[58]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[59]),\n .Q(rd_data_r[59]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[60]),\n .Q(rd_data_r[60]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[61]),\n .Q(rd_data_r[61]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[62]),\n .Q(rd_data_r[62]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[63]),\n .Q(rd_data_r[63]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[64]),\n .Q(rd_data_r[64]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[65]),\n .Q(rd_data_r[65]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[66]),\n .Q(rd_data_r[66]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[67]),\n .Q(rd_data_r[67]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[68]),\n .Q(rd_data_r[68]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[69]),\n .Q(rd_data_r[69]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[6]),\n .Q(rd_data_r[6]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[70]),\n .Q(rd_data_r[70]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[71]),\n .Q(rd_data_r[71]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[7]),\n .Q(rd_data_r[7]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[8]),\n .Q(\\not_strict_mode.app_rd_data_reg[15]_0 ),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[9]),\n .Q(rd_data_r[9]),\n .R(1'b0));\n ddr3_if_mig_7series_v4_0_ddr_if_post_fifo_6 \\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo \n (.A_byte_rd_en(A_byte_rd_en),\n .CLK(CLK),\n .C_byte_rd_en(C_byte_rd_en),\n .D_byte_rd_en(D_byte_rd_en),\n .Q({rd_data_r[71:9],\\not_strict_mode.app_rd_data_reg[15]_0 ,rd_data_r[7:6]}),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (if_empty_r),\n .if_empty_r_0(if_empty_r_0),\n .ififo_rst(ififo_rst),\n .\\my_empty_reg[4]_0 (\\my_empty_reg[4] ),\n .\\not_strict_mode.app_rd_data_reg[104] (\\not_strict_mode.app_rd_data_reg[104] ),\n .\\not_strict_mode.app_rd_data_reg[105] (\\not_strict_mode.app_rd_data_reg[105] ),\n .\\not_strict_mode.app_rd_data_reg[106] (\\not_strict_mode.app_rd_data_reg[106] ),\n .\\not_strict_mode.app_rd_data_reg[107] (\\not_strict_mode.app_rd_data_reg[107] ),\n .\\not_strict_mode.app_rd_data_reg[108] (\\not_strict_mode.app_rd_data_reg[108] ),\n .\\not_strict_mode.app_rd_data_reg[109] (\\not_strict_mode.app_rd_data_reg[109] ),\n .\\not_strict_mode.app_rd_data_reg[10] (\\not_strict_mode.app_rd_data_reg[10] ),\n .\\not_strict_mode.app_rd_data_reg[110] (\\not_strict_mode.app_rd_data_reg[110] ),\n .\\not_strict_mode.app_rd_data_reg[111] (\\not_strict_mode.app_rd_data_reg[111] ),\n .\\not_strict_mode.app_rd_data_reg[11] (\\not_strict_mode.app_rd_data_reg[11] ),\n .\\not_strict_mode.app_rd_data_reg[12] (\\not_strict_mode.app_rd_data_reg[12] ),\n .\\not_strict_mode.app_rd_data_reg[136] (\\not_strict_mode.app_rd_data_reg[136] ),\n .\\not_strict_mode.app_rd_data_reg[137] (\\not_strict_mode.app_rd_data_reg[137] ),\n .\\not_strict_mode.app_rd_data_reg[138] (\\not_strict_mode.app_rd_data_reg[138] ),\n .\\not_strict_mode.app_rd_data_reg[139] (\\not_strict_mode.app_rd_data_reg[139] ),\n .\\not_strict_mode.app_rd_data_reg[13] (\\not_strict_mode.app_rd_data_reg[13] ),\n .\\not_strict_mode.app_rd_data_reg[140] (\\not_strict_mode.app_rd_data_reg[140] ),\n .\\not_strict_mode.app_rd_data_reg[141] (\\not_strict_mode.app_rd_data_reg[141] ),\n .\\not_strict_mode.app_rd_data_reg[142] (\\not_strict_mode.app_rd_data_reg[142] ),\n .\\not_strict_mode.app_rd_data_reg[143] (\\not_strict_mode.app_rd_data_reg[143] ),\n .\\not_strict_mode.app_rd_data_reg[14] (\\not_strict_mode.app_rd_data_reg[14] ),\n .\\not_strict_mode.app_rd_data_reg[15] (\\not_strict_mode.app_rd_data_reg[15] ),\n .\\not_strict_mode.app_rd_data_reg[15]_0 (\\not_strict_mode.app_rd_data_reg[15]_1 ),\n .\\not_strict_mode.app_rd_data_reg[168] (\\not_strict_mode.app_rd_data_reg[168] ),\n .\\not_strict_mode.app_rd_data_reg[169] (\\not_strict_mode.app_rd_data_reg[169] ),\n .\\not_strict_mode.app_rd_data_reg[170] (\\not_strict_mode.app_rd_data_reg[170] ),\n .\\not_strict_mode.app_rd_data_reg[171] (\\not_strict_mode.app_rd_data_reg[171] ),\n .\\not_strict_mode.app_rd_data_reg[172] (\\not_strict_mode.app_rd_data_reg[172] ),\n .\\not_strict_mode.app_rd_data_reg[173] (\\not_strict_mode.app_rd_data_reg[173] ),\n .\\not_strict_mode.app_rd_data_reg[174] (\\not_strict_mode.app_rd_data_reg[174] ),\n .\\not_strict_mode.app_rd_data_reg[175] (\\not_strict_mode.app_rd_data_reg[175] ),\n .\\not_strict_mode.app_rd_data_reg[200] (\\not_strict_mode.app_rd_data_reg[200] ),\n .\\not_strict_mode.app_rd_data_reg[201] (\\not_strict_mode.app_rd_data_reg[201] ),\n .\\not_strict_mode.app_rd_data_reg[202] (\\not_strict_mode.app_rd_data_reg[202] ),\n .\\not_strict_mode.app_rd_data_reg[203] (\\not_strict_mode.app_rd_data_reg[203] ),\n .\\not_strict_mode.app_rd_data_reg[204] (\\not_strict_mode.app_rd_data_reg[204] ),\n .\\not_strict_mode.app_rd_data_reg[205] (\\not_strict_mode.app_rd_data_reg[205] ),\n .\\not_strict_mode.app_rd_data_reg[206] (\\not_strict_mode.app_rd_data_reg[206] ),\n .\\not_strict_mode.app_rd_data_reg[207] (\\not_strict_mode.app_rd_data_reg[207] ),\n .\\not_strict_mode.app_rd_data_reg[232] (\\not_strict_mode.app_rd_data_reg[232] ),\n .\\not_strict_mode.app_rd_data_reg[233] (\\not_strict_mode.app_rd_data_reg[233] ),\n .\\not_strict_mode.app_rd_data_reg[234] (\\not_strict_mode.app_rd_data_reg[234] ),\n .\\not_strict_mode.app_rd_data_reg[235] (\\not_strict_mode.app_rd_data_reg[235] ),\n .\\not_strict_mode.app_rd_data_reg[236] (\\not_strict_mode.app_rd_data_reg[236] ),\n .\\not_strict_mode.app_rd_data_reg[236]_0 (\\not_strict_mode.app_rd_data_reg[236]_0 ),\n .\\not_strict_mode.app_rd_data_reg[237] (\\not_strict_mode.app_rd_data_reg[237] ),\n .\\not_strict_mode.app_rd_data_reg[238] (\\not_strict_mode.app_rd_data_reg[238] ),\n .\\not_strict_mode.app_rd_data_reg[239] (\\not_strict_mode.app_rd_data_reg[239] ),\n .\\not_strict_mode.app_rd_data_reg[239]_0 (\\not_strict_mode.app_rd_data_reg[239]_0 ),\n .\\not_strict_mode.app_rd_data_reg[40] (\\not_strict_mode.app_rd_data_reg[40] ),\n .\\not_strict_mode.app_rd_data_reg[41] (\\not_strict_mode.app_rd_data_reg[41] ),\n .\\not_strict_mode.app_rd_data_reg[42] (\\not_strict_mode.app_rd_data_reg[42] ),\n .\\not_strict_mode.app_rd_data_reg[43] (\\not_strict_mode.app_rd_data_reg[43] ),\n .\\not_strict_mode.app_rd_data_reg[44] (\\not_strict_mode.app_rd_data_reg[44] ),\n .\\not_strict_mode.app_rd_data_reg[45] (\\not_strict_mode.app_rd_data_reg[45] ),\n .\\not_strict_mode.app_rd_data_reg[46] (\\not_strict_mode.app_rd_data_reg[46] ),\n .\\not_strict_mode.app_rd_data_reg[47] (\\not_strict_mode.app_rd_data_reg[47] ),\n .\\not_strict_mode.app_rd_data_reg[72] (\\not_strict_mode.app_rd_data_reg[72] ),\n .\\not_strict_mode.app_rd_data_reg[73] (\\not_strict_mode.app_rd_data_reg[73] ),\n .\\not_strict_mode.app_rd_data_reg[74] (\\not_strict_mode.app_rd_data_reg[74] ),\n .\\not_strict_mode.app_rd_data_reg[75] (\\not_strict_mode.app_rd_data_reg[75] ),\n .\\not_strict_mode.app_rd_data_reg[76] (\\not_strict_mode.app_rd_data_reg[76] ),\n .\\not_strict_mode.app_rd_data_reg[77] (\\not_strict_mode.app_rd_data_reg[77] ),\n .\\not_strict_mode.app_rd_data_reg[78] (\\not_strict_mode.app_rd_data_reg[78] ),\n .\\not_strict_mode.app_rd_data_reg[79] (\\not_strict_mode.app_rd_data_reg[79] ),\n .\\not_strict_mode.app_rd_data_reg[8] (\\not_strict_mode.app_rd_data_reg[8] ),\n .\\not_strict_mode.app_rd_data_reg[9] (\\not_strict_mode.app_rd_data_reg[9] ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ),\n .phy_if_empty_r_reg(\\rd_ptr_timing_reg[1] [0]),\n .\\rd_ptr_timing_reg[1]_0 (\\rd_ptr_timing_reg[1] [1]),\n .\\read_fifo.fifo_out_data_r_reg[6] (\\read_fifo.fifo_out_data_r_reg[6] ));\n FDSE #(\n .INIT(1'b1)) \n ififo_rst_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .Q(ififo_rst),\n .S(phy_if_reset));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n IN_FIFO #(\n .ALMOST_EMPTY_VALUE(1),\n .ALMOST_FULL_VALUE(1),\n .ARRAY_MODE(\"ARRAY_MODE_4_X_8\"),\n .SYNCHRONOUS_MODE(\"FALSE\")) \n \\in_fifo_gen.in_fifo \n (.ALMOSTEMPTY(\\in_fifo_gen.in_fifo_n_0 ),\n .ALMOSTFULL(\\in_fifo_gen.in_fifo_n_1 ),\n .D0({1'b0,1'b0,1'b0,1'b0}),\n .D1(if_d1),\n .D2(if_d2),\n .D3(if_d3),\n .D4(if_d4),\n .D5({\\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED [7:4],if_d5}),\n .D6({\\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED [7:4],if_d6}),\n .D7(if_d7),\n .D8(if_d8),\n .D9({1'b0,1'b0,1'b0,1'b0}),\n .EMPTY(if_empty_),\n .FULL(\\in_fifo_gen.in_fifo_n_3 ),\n .Q0(rd_data[7:0]),\n .Q1(rd_data[15:8]),\n .Q2(rd_data[23:16]),\n .Q3(rd_data[31:24]),\n .Q4(rd_data[39:32]),\n .Q5(rd_data[47:40]),\n .Q6(rd_data[55:48]),\n .Q7(rd_data[63:56]),\n .Q8(rd_data[71:64]),\n .Q9(rd_data[79:72]),\n .RDCLK(CLK),\n .RDEN(1'b1),\n .RESET(ififo_rst),\n .WRCLK(iserdes_clkdiv),\n .WREN(ififo_wr_enable));\n ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized4 \\of_pre_fifo_gen.u_ddr_of_pre_fifo \n (.CLK(CLK),\n .D0({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }),\n .D9(of_d9),\n .Q(Q),\n .init_calib_complete_reg_rep(init_calib_complete_reg_rep),\n .mux_wrdata_en(mux_wrdata_en),\n .\\my_empty_reg[1]_0 (\\my_empty_reg[1] ),\n .\\my_empty_reg[7]_0 (\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ),\n .\\my_empty_reg[7]_1 (\\my_empty_reg[7] ),\n .ofifo_rst(ofifo_rst),\n .ofifo_rst_reg(out_fifo_n_3),\n .phy_dout(phy_dout),\n .\\write_buffer.wr_buf_out_data_reg[285] (\\write_buffer.wr_buf_out_data_reg[285] ));\n FDSE #(\n .INIT(1'b1)) \n ofifo_rst_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .Q(ofifo_rst),\n .S(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n OUT_FIFO #(\n .ALMOST_EMPTY_VALUE(1),\n .ALMOST_FULL_VALUE(1),\n .ARRAY_MODE(\"ARRAY_MODE_8_X_4\"),\n .OUTPUT_DISABLE(\"FALSE\"),\n .SYNCHRONOUS_MODE(\"FALSE\")) \n out_fifo\n (.ALMOSTEMPTY(out_fifo_n_0),\n .ALMOSTFULL(out_fifo_n_1),\n .D0({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }),\n .D1(\\write_buffer.wr_buf_out_data_reg[239] ),\n .D2(\\write_buffer.wr_buf_out_data_reg[238] ),\n .D3(\\write_buffer.wr_buf_out_data_reg[237] ),\n .D4(\\write_buffer.wr_buf_out_data_reg[236] ),\n .D5(\\write_buffer.wr_buf_out_data_reg[235] ),\n .D6(\\write_buffer.wr_buf_out_data_reg[234] ),\n .D7(\\write_buffer.wr_buf_out_data_reg[233] ),\n .D8(\\write_buffer.wr_buf_out_data_reg[232] ),\n .D9(of_d9),\n .EMPTY(out_fifo_n_2),\n .FULL(out_fifo_n_3),\n .Q0(of_dqbus[3:0]),\n .Q1(of_dqbus[7:4]),\n .Q2(of_dqbus[11:8]),\n .Q3(of_dqbus[15:12]),\n .Q4(of_dqbus[19:16]),\n .Q5({NLW_out_fifo_Q5_UNCONNECTED[7:4],of_dqbus[23:20]}),\n .Q6({NLW_out_fifo_Q6_UNCONNECTED[7:4],of_dqbus[27:24]}),\n .Q7(of_dqbus[31:28]),\n .Q8(of_dqbus[35:32]),\n .Q9(of_dqbus[39:36]),\n .RDCLK(oserdes_clkdiv),\n .RDEN(po_rd_enable),\n .RESET(ofifo_rst),\n .WRCLK(CLK),\n .WREN(\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n PHASER_IN_PHY #(\n .BURST_MODE(\"TRUE\"),\n .CLKOUT_DIV(2),\n .DQS_BIAS_MODE(\"FALSE\"),\n .DQS_FIND_PATTERN(3'b000),\n .FINE_DELAY(33),\n .FREQ_REF_DIV(\"NONE\"),\n .IS_RST_INVERTED(1'b0),\n .MEMREFCLK_PERIOD(1.112000),\n .OUTPUT_CLK_SRC(\"DELAYED_REF\"),\n .PHASEREFCLK_PERIOD(1.112000),\n .REFCLK_PERIOD(1.112000),\n .SEL_CLK_OFFSET(6),\n .SYNC_IN_DIV_RST(\"TRUE\"),\n .WR_CYCLES(\"FALSE\")) \n \\phaser_in_gen.phaser_in \n (.BURSTPENDINGPHY(phaser_ctl_bus[1]),\n .COUNTERLOADEN(\\gen_byte_sel_div1.calib_in_common_reg ),\n .COUNTERLOADVAL(\\calib_zero_inputs_reg[0] ),\n .COUNTERREADEN(\\calib_sel_reg[1] ),\n .COUNTERREADVAL(COUNTERREADVAL),\n .DQSFOUND(\\pi_dqs_found_lanes_r1_reg[2] ),\n .DQSOUTOFRANGE(\\phaser_in_gen.phaser_in_n_1 ),\n .ENCALIBPHY(PCENABLECALIB),\n .FINEENABLE(pi_en_stg2_f_reg),\n .FINEINC(pi_stg2_f_incdec_reg),\n .FINEOVERFLOW(\\phaser_in_gen.phaser_in_n_2 ),\n .FREQREFCLK(freq_refclk),\n .ICLK(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),\n .ICLKDIV(iserdes_clkdiv),\n .ISERDESRST(\\phaser_in_gen.phaser_in_n_5 ),\n .MEMREFCLK(mem_refclk),\n .PHASELOCKED(pi_phase_locked_all_r1_reg),\n .PHASEREFCLK(mem_dqs_in),\n .RANKSELPHY(phaser_ctl_bus[3:2]),\n .RCLK(\\phaser_in_gen.phaser_in_n_7 ),\n .RST(A_rst_primitives),\n .RSTDQSFIND(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .SYNCIN(sync_pulse),\n .SYSCLK(CLK),\n .WRENABLE(ififo_wr_enable));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n PHASER_OUT_PHY #(\n .CLKOUT_DIV(2),\n .COARSE_BYPASS(\"FALSE\"),\n .COARSE_DELAY(0),\n .DATA_CTL_N(\"TRUE\"),\n .DATA_RD_CYCLES(\"FALSE\"),\n .FINE_DELAY(60),\n .IS_RST_INVERTED(1'b0),\n .MEMREFCLK_PERIOD(1.112000),\n .OCLKDELAY_INV(\"TRUE\"),\n .OCLK_DELAY(28),\n .OUTPUT_CLK_SRC(\"DELAYED_REF\"),\n .PHASEREFCLK_PERIOD(1.000000),\n .PO(3'b111),\n .REFCLK_PERIOD(1.112000),\n .SYNC_IN_DIV_RST(\"TRUE\")) \n phaser_out\n (.BURSTPENDINGPHY(phaser_ctl_bus[0]),\n .COARSEENABLE(\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .COARSEINC(\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .COARSEOVERFLOW(phaser_out_n_0),\n .COUNTERLOADEN(1'b0),\n .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .COUNTERREADEN(\\calib_sel_reg[1] ),\n .COUNTERREADVAL(\\po_counter_read_val_reg[8] ),\n .CTSBUS(oserdes_dqs_ts),\n .DQSBUS(oserdes_dqs),\n .DTSBUS(oserdes_dq_ts),\n .ENCALIBPHY(PCENABLECALIB),\n .FINEENABLE(ck_po_stg2_f_en_reg),\n .FINEINC(ck_po_stg2_f_indec_reg),\n .FINEOVERFLOW(phaser_out_n_1),\n .FREQREFCLK(freq_refclk),\n .MEMREFCLK(mem_refclk),\n .OCLK(oserdes_clk),\n .OCLKDELAYED(oserdes_clk_delayed),\n .OCLKDIV(oserdes_clkdiv),\n .OSERDESRST(po_oserdes_rst),\n .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),\n .RDENABLE(po_rd_enable),\n .RST(A_rst_primitives),\n .SELFINEOCLKDELAY(delay_done_r4_reg),\n .SYNCIN(sync_pulse),\n .SYSCLK(CLK));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_byte_lane\" *) \nmodule ddr3_if_mig_7series_v4_0_ddr_byte_lane__parameterized2\n (\\pi_dqs_found_lanes_r1_reg[3] ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,\n pi_phase_locked_all_r1_reg,\n mem_dqs_out,\n mem_dqs_ts,\n mem_dq_out,\n mem_dq_ts,\n idelay_ld_rst_2,\n \\not_strict_mode.app_rd_data_reg[228] ,\n \\my_empty_reg[1] ,\n \\not_strict_mode.app_rd_data_reg[231] ,\n \\not_strict_mode.app_rd_data_reg[0] ,\n \\not_strict_mode.app_rd_data_reg[1] ,\n \\not_strict_mode.app_rd_data_reg[2] ,\n \\not_strict_mode.app_rd_data_reg[3] ,\n \\not_strict_mode.app_rd_data_reg[4] ,\n \\not_strict_mode.app_rd_data_reg[5] ,\n \\not_strict_mode.app_rd_data_reg[6] ,\n \\not_strict_mode.app_rd_data_reg[7] ,\n \\not_strict_mode.app_rd_data_reg[32] ,\n \\not_strict_mode.app_rd_data_reg[33] ,\n \\not_strict_mode.app_rd_data_reg[34] ,\n \\not_strict_mode.app_rd_data_reg[35] ,\n \\not_strict_mode.app_rd_data_reg[36] ,\n \\not_strict_mode.app_rd_data_reg[37] ,\n \\not_strict_mode.app_rd_data_reg[38] ,\n \\not_strict_mode.app_rd_data_reg[39] ,\n \\not_strict_mode.app_rd_data_reg[64] ,\n \\not_strict_mode.app_rd_data_reg[65] ,\n \\not_strict_mode.app_rd_data_reg[66] ,\n \\not_strict_mode.app_rd_data_reg[67] ,\n \\not_strict_mode.app_rd_data_reg[68] ,\n \\not_strict_mode.app_rd_data_reg[69] ,\n \\not_strict_mode.app_rd_data_reg[70] ,\n \\not_strict_mode.app_rd_data_reg[71] ,\n \\not_strict_mode.app_rd_data_reg[96] ,\n \\not_strict_mode.app_rd_data_reg[97] ,\n \\not_strict_mode.app_rd_data_reg[98] ,\n \\not_strict_mode.app_rd_data_reg[99] ,\n \\not_strict_mode.app_rd_data_reg[100] ,\n \\not_strict_mode.app_rd_data_reg[101] ,\n \\not_strict_mode.app_rd_data_reg[102] ,\n \\not_strict_mode.app_rd_data_reg[103] ,\n \\not_strict_mode.app_rd_data_reg[128] ,\n \\not_strict_mode.app_rd_data_reg[129] ,\n \\not_strict_mode.app_rd_data_reg[130] ,\n \\not_strict_mode.app_rd_data_reg[131] ,\n \\not_strict_mode.app_rd_data_reg[132] ,\n \\not_strict_mode.app_rd_data_reg[133] ,\n \\not_strict_mode.app_rd_data_reg[134] ,\n \\not_strict_mode.app_rd_data_reg[135] ,\n \\not_strict_mode.app_rd_data_reg[160] ,\n \\not_strict_mode.app_rd_data_reg[161] ,\n \\not_strict_mode.app_rd_data_reg[162] ,\n \\not_strict_mode.app_rd_data_reg[163] ,\n \\not_strict_mode.app_rd_data_reg[164] ,\n \\not_strict_mode.app_rd_data_reg[165] ,\n \\not_strict_mode.app_rd_data_reg[166] ,\n \\not_strict_mode.app_rd_data_reg[167] ,\n \\not_strict_mode.app_rd_data_reg[192] ,\n \\not_strict_mode.app_rd_data_reg[193] ,\n \\not_strict_mode.app_rd_data_reg[194] ,\n \\not_strict_mode.app_rd_data_reg[195] ,\n \\not_strict_mode.app_rd_data_reg[196] ,\n \\not_strict_mode.app_rd_data_reg[197] ,\n \\not_strict_mode.app_rd_data_reg[198] ,\n \\not_strict_mode.app_rd_data_reg[199] ,\n \\not_strict_mode.app_rd_data_reg[224] ,\n \\not_strict_mode.app_rd_data_reg[225] ,\n \\not_strict_mode.app_rd_data_reg[226] ,\n \\not_strict_mode.app_rd_data_reg[227] ,\n \\not_strict_mode.app_rd_data_reg[228]_0 ,\n \\not_strict_mode.app_rd_data_reg[229] ,\n \\not_strict_mode.app_rd_data_reg[230] ,\n \\not_strict_mode.app_rd_data_reg[231]_0 ,\n mux_rd_valid_r_reg,\n \\not_strict_mode.app_rd_data_reg[7]_0 ,\n \\not_strict_mode.app_rd_data_reg[7]_1 ,\n \\my_empty_reg[7] ,\n D_byte_rd_en,\n D,\n \\po_counter_read_val_reg[8] ,\n Q,\n phaser_ctl_bus,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n \\calib_sel_reg[0] ,\n pi_en_stg2_f_reg,\n pi_stg2_f_incdec_reg,\n freq_refclk,\n mem_refclk,\n mem_dqs_in,\n A_rst_primitives,\n \\gen_byte_sel_div1.calib_in_common_reg_0 ,\n sync_pulse,\n CLK,\n PCENABLECALIB,\n \\calib_zero_inputs_reg[0] ,\n \\gen_byte_sel_div1.calib_in_common_reg_1 ,\n ck_po_stg2_f_en_reg,\n ck_po_stg2_f_indec_reg,\n delay_done_r4_reg,\n \\write_buffer.wr_buf_out_data_reg[231] ,\n \\write_buffer.wr_buf_out_data_reg[230] ,\n \\write_buffer.wr_buf_out_data_reg[229] ,\n \\write_buffer.wr_buf_out_data_reg[228] ,\n \\write_buffer.wr_buf_out_data_reg[227] ,\n \\write_buffer.wr_buf_out_data_reg[226] ,\n \\write_buffer.wr_buf_out_data_reg[225] ,\n \\write_buffer.wr_buf_out_data_reg[224] ,\n \\gen_byte_sel_div1.calib_in_common_reg_2 ,\n mem_dq_in,\n idelay_inc,\n LD0_5,\n CLKB0_9,\n phy_if_reset,\n mux_wrdata_en,\n rst_r4,\n init_calib_complete_reg_rep,\n \\write_buffer.wr_buf_out_data_reg[284] ,\n \\read_fifo.fifo_out_data_r_reg[6] ,\n DOC,\n DOB,\n DOA,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,\n \\my_empty_reg[4] ,\n if_empty_r,\n phy_dout,\n \\gen_byte_sel_div1.calib_in_common_reg_3 ,\n \\calib_sel_reg[0]_0 ,\n C_byte_rd_en,\n A_byte_rd_en,\n if_empty_r_0,\n \\my_empty_reg[4]_0 ,\n COUNTERREADVAL,\n \\calib_sel_reg[1] ,\n A_rst_primitives_reg,\n A_rst_primitives_reg_0,\n A_rst_primitives_reg_1,\n A_rst_primitives_reg_2,\n A_rst_primitives_reg_3);\n output [0:0]\\pi_dqs_found_lanes_r1_reg[3] ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n output pi_phase_locked_all_r1_reg;\n output [0:0]mem_dqs_out;\n output [0:0]mem_dqs_ts;\n output [8:0]mem_dq_out;\n output [8:0]mem_dq_ts;\n output idelay_ld_rst_2;\n output \\not_strict_mode.app_rd_data_reg[228] ;\n output \\my_empty_reg[1] ;\n output [63:0]\\not_strict_mode.app_rd_data_reg[231] ;\n output \\not_strict_mode.app_rd_data_reg[0] ;\n output \\not_strict_mode.app_rd_data_reg[1] ;\n output \\not_strict_mode.app_rd_data_reg[2] ;\n output \\not_strict_mode.app_rd_data_reg[3] ;\n output \\not_strict_mode.app_rd_data_reg[4] ;\n output \\not_strict_mode.app_rd_data_reg[5] ;\n output \\not_strict_mode.app_rd_data_reg[6] ;\n output \\not_strict_mode.app_rd_data_reg[7] ;\n output \\not_strict_mode.app_rd_data_reg[32] ;\n output \\not_strict_mode.app_rd_data_reg[33] ;\n output \\not_strict_mode.app_rd_data_reg[34] ;\n output \\not_strict_mode.app_rd_data_reg[35] ;\n output \\not_strict_mode.app_rd_data_reg[36] ;\n output \\not_strict_mode.app_rd_data_reg[37] ;\n output \\not_strict_mode.app_rd_data_reg[38] ;\n output \\not_strict_mode.app_rd_data_reg[39] ;\n output \\not_strict_mode.app_rd_data_reg[64] ;\n output \\not_strict_mode.app_rd_data_reg[65] ;\n output \\not_strict_mode.app_rd_data_reg[66] ;\n output \\not_strict_mode.app_rd_data_reg[67] ;\n output \\not_strict_mode.app_rd_data_reg[68] ;\n output \\not_strict_mode.app_rd_data_reg[69] ;\n output \\not_strict_mode.app_rd_data_reg[70] ;\n output \\not_strict_mode.app_rd_data_reg[71] ;\n output \\not_strict_mode.app_rd_data_reg[96] ;\n output \\not_strict_mode.app_rd_data_reg[97] ;\n output \\not_strict_mode.app_rd_data_reg[98] ;\n output \\not_strict_mode.app_rd_data_reg[99] ;\n output \\not_strict_mode.app_rd_data_reg[100] ;\n output \\not_strict_mode.app_rd_data_reg[101] ;\n output \\not_strict_mode.app_rd_data_reg[102] ;\n output \\not_strict_mode.app_rd_data_reg[103] ;\n output \\not_strict_mode.app_rd_data_reg[128] ;\n output \\not_strict_mode.app_rd_data_reg[129] ;\n output \\not_strict_mode.app_rd_data_reg[130] ;\n output \\not_strict_mode.app_rd_data_reg[131] ;\n output \\not_strict_mode.app_rd_data_reg[132] ;\n output \\not_strict_mode.app_rd_data_reg[133] ;\n output \\not_strict_mode.app_rd_data_reg[134] ;\n output \\not_strict_mode.app_rd_data_reg[135] ;\n output \\not_strict_mode.app_rd_data_reg[160] ;\n output \\not_strict_mode.app_rd_data_reg[161] ;\n output \\not_strict_mode.app_rd_data_reg[162] ;\n output \\not_strict_mode.app_rd_data_reg[163] ;\n output \\not_strict_mode.app_rd_data_reg[164] ;\n output \\not_strict_mode.app_rd_data_reg[165] ;\n output \\not_strict_mode.app_rd_data_reg[166] ;\n output \\not_strict_mode.app_rd_data_reg[167] ;\n output \\not_strict_mode.app_rd_data_reg[192] ;\n output \\not_strict_mode.app_rd_data_reg[193] ;\n output \\not_strict_mode.app_rd_data_reg[194] ;\n output \\not_strict_mode.app_rd_data_reg[195] ;\n output \\not_strict_mode.app_rd_data_reg[196] ;\n output \\not_strict_mode.app_rd_data_reg[197] ;\n output \\not_strict_mode.app_rd_data_reg[198] ;\n output \\not_strict_mode.app_rd_data_reg[199] ;\n output \\not_strict_mode.app_rd_data_reg[224] ;\n output \\not_strict_mode.app_rd_data_reg[225] ;\n output \\not_strict_mode.app_rd_data_reg[226] ;\n output \\not_strict_mode.app_rd_data_reg[227] ;\n output \\not_strict_mode.app_rd_data_reg[228]_0 ;\n output \\not_strict_mode.app_rd_data_reg[229] ;\n output \\not_strict_mode.app_rd_data_reg[230] ;\n output \\not_strict_mode.app_rd_data_reg[231]_0 ;\n output mux_rd_valid_r_reg;\n output [0:0]\\not_strict_mode.app_rd_data_reg[7]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[7]_1 ;\n output [63:0]\\my_empty_reg[7] ;\n output D_byte_rd_en;\n output [5:0]D;\n output [8:0]\\po_counter_read_val_reg[8] ;\n output [2:0]Q;\n input [3:0]phaser_ctl_bus;\n input \\gen_byte_sel_div1.calib_in_common_reg ;\n input \\calib_sel_reg[0] ;\n input pi_en_stg2_f_reg;\n input pi_stg2_f_incdec_reg;\n input freq_refclk;\n input mem_refclk;\n input [0:0]mem_dqs_in;\n input A_rst_primitives;\n input \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n input sync_pulse;\n input CLK;\n input [1:0]PCENABLECALIB;\n input [5:0]\\calib_zero_inputs_reg[0] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n input ck_po_stg2_f_en_reg;\n input ck_po_stg2_f_indec_reg;\n input delay_done_r4_reg;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[231] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[230] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[229] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[228] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[227] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[226] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[225] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[224] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n input [7:0]mem_dq_in;\n input idelay_inc;\n input LD0_5;\n input CLKB0_9;\n input phy_if_reset;\n input mux_wrdata_en;\n input rst_r4;\n input init_calib_complete_reg_rep;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[284] ;\n input \\read_fifo.fifo_out_data_r_reg[6] ;\n input [1:0]DOC;\n input [1:0]DOB;\n input [1:0]DOA;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n input [0:0]\\my_empty_reg[4] ;\n input [0:0]if_empty_r;\n input [71:0]phy_dout;\n input [0:0]\\gen_byte_sel_div1.calib_in_common_reg_3 ;\n input [7:0]\\calib_sel_reg[0]_0 ;\n input C_byte_rd_en;\n input A_byte_rd_en;\n input [0:0]if_empty_r_0;\n input [0:0]\\my_empty_reg[4]_0 ;\n input [5:0]COUNTERREADVAL;\n input [1:0]\\calib_sel_reg[1] ;\n input [5:0]A_rst_primitives_reg;\n input [5:0]A_rst_primitives_reg_0;\n input [8:0]A_rst_primitives_reg_1;\n input [8:0]A_rst_primitives_reg_2;\n input [8:0]A_rst_primitives_reg_3;\n\n wire A_byte_rd_en;\n wire A_rst_primitives;\n wire [5:0]A_rst_primitives_reg;\n wire [5:0]A_rst_primitives_reg_0;\n wire [8:0]A_rst_primitives_reg_1;\n wire [8:0]A_rst_primitives_reg_2;\n wire [8:0]A_rst_primitives_reg_3;\n wire CLK;\n wire CLKB0_9;\n wire [5:0]COUNTERREADVAL;\n wire C_byte_rd_en;\n wire [5:0]D;\n wire [1:0]DOA;\n wire [1:0]DOB;\n wire [1:0]DOC;\n wire D_byte_rd_en;\n wire [5:0]D_pi_counter_read_val;\n wire [8:0]D_po_counter_read_val;\n wire LD0_5;\n wire [1:0]PCENABLECALIB;\n wire [2:0]Q;\n wire \\calib_sel_reg[0] ;\n wire [7:0]\\calib_sel_reg[0]_0 ;\n wire [1:0]\\calib_sel_reg[1] ;\n wire [5:0]\\calib_zero_inputs_reg[0] ;\n wire ck_po_stg2_f_en_reg;\n wire ck_po_stg2_f_indec_reg;\n wire delay_done_r4_reg;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n wire freq_refclk;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n wire [0:0]\\gen_byte_sel_div1.calib_in_common_reg_3 ;\n wire idelay_inc;\n wire idelay_ld_rst_2;\n wire [3:0]if_d1;\n wire [3:0]if_d2;\n wire [3:0]if_d3;\n wire [3:0]if_d4;\n wire [3:0]if_d5;\n wire [3:0]if_d6;\n wire [3:0]if_d7;\n wire [3:0]if_d8;\n wire if_empty_;\n wire [0:0]if_empty_r;\n wire [0:0]if_empty_r_0;\n wire [3:3]if_empty_r_1;\n wire ififo_rst;\n wire ififo_wr_enable;\n wire \\in_fifo_gen.in_fifo_n_0 ;\n wire \\in_fifo_gen.in_fifo_n_1 ;\n wire \\in_fifo_gen.in_fifo_n_3 ;\n wire init_calib_complete_reg_rep;\n wire iserdes_clkdiv;\n wire [7:0]mem_dq_in;\n wire [8:0]mem_dq_out;\n wire [8:0]mem_dq_ts;\n wire [0:0]mem_dqs_in;\n wire [0:0]mem_dqs_out;\n wire [0:0]mem_dqs_ts;\n wire mem_refclk;\n wire mux_rd_valid_r_reg;\n wire mux_wrdata_en;\n wire \\my_empty_reg[1] ;\n wire [0:0]\\my_empty_reg[4] ;\n wire [0:0]\\my_empty_reg[4]_0 ;\n wire [63:0]\\my_empty_reg[7] ;\n wire \\not_strict_mode.app_rd_data_reg[0] ;\n wire \\not_strict_mode.app_rd_data_reg[100] ;\n wire \\not_strict_mode.app_rd_data_reg[101] ;\n wire \\not_strict_mode.app_rd_data_reg[102] ;\n wire \\not_strict_mode.app_rd_data_reg[103] ;\n wire \\not_strict_mode.app_rd_data_reg[128] ;\n wire \\not_strict_mode.app_rd_data_reg[129] ;\n wire \\not_strict_mode.app_rd_data_reg[130] ;\n wire \\not_strict_mode.app_rd_data_reg[131] ;\n wire \\not_strict_mode.app_rd_data_reg[132] ;\n wire \\not_strict_mode.app_rd_data_reg[133] ;\n wire \\not_strict_mode.app_rd_data_reg[134] ;\n wire \\not_strict_mode.app_rd_data_reg[135] ;\n wire \\not_strict_mode.app_rd_data_reg[160] ;\n wire \\not_strict_mode.app_rd_data_reg[161] ;\n wire \\not_strict_mode.app_rd_data_reg[162] ;\n wire \\not_strict_mode.app_rd_data_reg[163] ;\n wire \\not_strict_mode.app_rd_data_reg[164] ;\n wire \\not_strict_mode.app_rd_data_reg[165] ;\n wire \\not_strict_mode.app_rd_data_reg[166] ;\n wire \\not_strict_mode.app_rd_data_reg[167] ;\n wire \\not_strict_mode.app_rd_data_reg[192] ;\n wire \\not_strict_mode.app_rd_data_reg[193] ;\n wire \\not_strict_mode.app_rd_data_reg[194] ;\n wire \\not_strict_mode.app_rd_data_reg[195] ;\n wire \\not_strict_mode.app_rd_data_reg[196] ;\n wire \\not_strict_mode.app_rd_data_reg[197] ;\n wire \\not_strict_mode.app_rd_data_reg[198] ;\n wire \\not_strict_mode.app_rd_data_reg[199] ;\n wire \\not_strict_mode.app_rd_data_reg[1] ;\n wire \\not_strict_mode.app_rd_data_reg[224] ;\n wire \\not_strict_mode.app_rd_data_reg[225] ;\n wire \\not_strict_mode.app_rd_data_reg[226] ;\n wire \\not_strict_mode.app_rd_data_reg[227] ;\n wire \\not_strict_mode.app_rd_data_reg[228] ;\n wire \\not_strict_mode.app_rd_data_reg[228]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[229] ;\n wire \\not_strict_mode.app_rd_data_reg[230] ;\n wire [63:0]\\not_strict_mode.app_rd_data_reg[231] ;\n wire \\not_strict_mode.app_rd_data_reg[231]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[2] ;\n wire \\not_strict_mode.app_rd_data_reg[32] ;\n wire \\not_strict_mode.app_rd_data_reg[33] ;\n wire \\not_strict_mode.app_rd_data_reg[34] ;\n wire \\not_strict_mode.app_rd_data_reg[35] ;\n wire \\not_strict_mode.app_rd_data_reg[36] ;\n wire \\not_strict_mode.app_rd_data_reg[37] ;\n wire \\not_strict_mode.app_rd_data_reg[38] ;\n wire \\not_strict_mode.app_rd_data_reg[39] ;\n wire \\not_strict_mode.app_rd_data_reg[3] ;\n wire \\not_strict_mode.app_rd_data_reg[4] ;\n wire \\not_strict_mode.app_rd_data_reg[5] ;\n wire \\not_strict_mode.app_rd_data_reg[64] ;\n wire \\not_strict_mode.app_rd_data_reg[65] ;\n wire \\not_strict_mode.app_rd_data_reg[66] ;\n wire \\not_strict_mode.app_rd_data_reg[67] ;\n wire \\not_strict_mode.app_rd_data_reg[68] ;\n wire \\not_strict_mode.app_rd_data_reg[69] ;\n wire \\not_strict_mode.app_rd_data_reg[6] ;\n wire \\not_strict_mode.app_rd_data_reg[70] ;\n wire \\not_strict_mode.app_rd_data_reg[71] ;\n wire \\not_strict_mode.app_rd_data_reg[7] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[7]_0 ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[7]_1 ;\n wire \\not_strict_mode.app_rd_data_reg[96] ;\n wire \\not_strict_mode.app_rd_data_reg[97] ;\n wire \\not_strict_mode.app_rd_data_reg[98] ;\n wire \\not_strict_mode.app_rd_data_reg[99] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n wire [7:0]of_d9;\n wire [39:0]of_dqbus;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ;\n wire ofifo_rst;\n wire oserdes_clk;\n wire oserdes_clk_delayed;\n wire oserdes_clkdiv;\n wire [1:0]oserdes_dq_ts;\n wire [1:0]oserdes_dqs;\n wire [1:0]oserdes_dqs_ts;\n wire out_fifo_n_0;\n wire out_fifo_n_1;\n wire out_fifo_n_2;\n wire out_fifo_n_3;\n wire [3:0]phaser_ctl_bus;\n wire \\phaser_in_gen.phaser_in_n_1 ;\n wire \\phaser_in_gen.phaser_in_n_2 ;\n wire \\phaser_in_gen.phaser_in_n_5 ;\n wire \\phaser_in_gen.phaser_in_n_7 ;\n wire phaser_out_n_0;\n wire phaser_out_n_1;\n wire [71:0]phy_dout;\n wire phy_if_reset;\n wire [0:0]\\pi_dqs_found_lanes_r1_reg[3] ;\n wire pi_en_stg2_f_reg;\n wire pi_phase_locked_all_r1_reg;\n wire pi_stg2_f_incdec_reg;\n wire [8:0]\\po_counter_read_val_reg[8] ;\n wire po_oserdes_rst;\n wire po_rd_enable;\n wire [79:0]rd_data;\n wire [71:6]rd_data_r;\n wire \\read_fifo.fifo_out_data_r_reg[6] ;\n wire rst_r4;\n wire sync_pulse;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[224] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[225] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[226] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[227] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[228] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[229] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[230] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[231] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[284] ;\n wire [7:4]\\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED ;\n wire [7:4]\\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED ;\n wire [7:4]NLW_out_fifo_Q5_UNCONNECTED;\n wire [7:4]NLW_out_fifo_Q6_UNCONNECTED;\n wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;\n\n ddr3_if_mig_7series_v4_0_ddr_byte_group_io__parameterized2 ddr_byte_group_io\n (.A_rst_primitives(A_rst_primitives),\n .A_rst_primitives_reg(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),\n .CLK(CLK),\n .CLKB0_9(CLKB0_9),\n .CTSBUS(oserdes_dqs_ts[0]),\n .D1(if_d1),\n .D2(if_d2),\n .D3(if_d3),\n .D4(if_d4),\n .D5(if_d5),\n .D6(if_d6),\n .D7(if_d7),\n .D8(if_d8),\n .DQSBUS(oserdes_dqs),\n .DTSBUS(oserdes_dq_ts),\n .LD0_5(LD0_5),\n .\\calib_sel_reg[0] (\\calib_sel_reg[0]_0 ),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\gen_byte_sel_div1.calib_in_common_reg_2 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_0 (\\gen_byte_sel_div1.calib_in_common_reg_3 ),\n .idelay_inc(idelay_inc),\n .idelay_ld_rst_2(idelay_ld_rst_2),\n .iserdes_clkdiv(iserdes_clkdiv),\n .mem_dq_in(mem_dq_in),\n .mem_dq_out(mem_dq_out),\n .mem_dq_ts(mem_dq_ts),\n .mem_dqs_out(mem_dqs_out),\n .mem_dqs_ts(mem_dqs_ts),\n .of_dqbus(of_dqbus[39:4]),\n .oserdes_clk(oserdes_clk),\n .oserdes_clk_delayed(oserdes_clk_delayed),\n .oserdes_clkdiv(oserdes_clkdiv),\n .po_oserdes_rst(po_oserdes_rst),\n .rst_r4(rst_r4));\n (* syn_maxfan = \"3\" *) \n FDRE \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(if_empty_),\n .Q(if_empty_r_1),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[10]),\n .Q(rd_data_r[10]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[11]),\n .Q(rd_data_r[11]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[12]),\n .Q(rd_data_r[12]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[13]),\n .Q(rd_data_r[13]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[14]),\n .Q(rd_data_r[14]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[15]),\n .Q(rd_data_r[15]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[16]),\n .Q(rd_data_r[16]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[17]),\n .Q(rd_data_r[17]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[18]),\n .Q(rd_data_r[18]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[19]),\n .Q(rd_data_r[19]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[20]),\n .Q(rd_data_r[20]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[21]),\n .Q(rd_data_r[21]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[22]),\n .Q(rd_data_r[22]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[23]),\n .Q(rd_data_r[23]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[24]),\n .Q(rd_data_r[24]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[25]),\n .Q(rd_data_r[25]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[26]),\n .Q(rd_data_r[26]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[27]),\n .Q(rd_data_r[27]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[28]),\n .Q(rd_data_r[28]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[29]),\n .Q(rd_data_r[29]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[30]),\n .Q(rd_data_r[30]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[31]),\n .Q(rd_data_r[31]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[32]),\n .Q(rd_data_r[32]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[33]),\n .Q(rd_data_r[33]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[34]),\n .Q(rd_data_r[34]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[35]),\n .Q(rd_data_r[35]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[36]),\n .Q(rd_data_r[36]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[37]),\n .Q(rd_data_r[37]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[38]),\n .Q(rd_data_r[38]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[39]),\n .Q(rd_data_r[39]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[40]),\n .Q(rd_data_r[40]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[41]),\n .Q(rd_data_r[41]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[42]),\n .Q(rd_data_r[42]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[43]),\n .Q(rd_data_r[43]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[44]),\n .Q(rd_data_r[44]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[45]),\n .Q(rd_data_r[45]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[46]),\n .Q(rd_data_r[46]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[47]),\n .Q(rd_data_r[47]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[48]),\n .Q(rd_data_r[48]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[49]),\n .Q(rd_data_r[49]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[50]),\n .Q(rd_data_r[50]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[51]),\n .Q(rd_data_r[51]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[52]),\n .Q(rd_data_r[52]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[53]),\n .Q(rd_data_r[53]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[54]),\n .Q(rd_data_r[54]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[55]),\n .Q(rd_data_r[55]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[56]),\n .Q(rd_data_r[56]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[57]),\n .Q(rd_data_r[57]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[58]),\n .Q(rd_data_r[58]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[59]),\n .Q(rd_data_r[59]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[60]),\n .Q(rd_data_r[60]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[61]),\n .Q(rd_data_r[61]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[62]),\n .Q(rd_data_r[62]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[63]),\n .Q(rd_data_r[63]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[64]),\n .Q(rd_data_r[64]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[65]),\n .Q(rd_data_r[65]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[66]),\n .Q(rd_data_r[66]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[67]),\n .Q(rd_data_r[67]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[68]),\n .Q(rd_data_r[68]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[69]),\n .Q(rd_data_r[69]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[6]),\n .Q(rd_data_r[6]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[70]),\n .Q(rd_data_r[70]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[71]),\n .Q(rd_data_r[71]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[7]),\n .Q(rd_data_r[7]),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[8]),\n .Q(\\not_strict_mode.app_rd_data_reg[7]_0 ),\n .R(1'b0));\n FDRE \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_data[9]),\n .Q(rd_data_r[9]),\n .R(1'b0));\n ddr3_if_mig_7series_v4_0_ddr_if_post_fifo \\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo \n (.A_byte_rd_en(A_byte_rd_en),\n .CLK(CLK),\n .C_byte_rd_en(C_byte_rd_en),\n .DOA(DOA),\n .DOB(DOB),\n .DOC(DOC),\n .D_byte_rd_en(D_byte_rd_en),\n .Q({rd_data_r[71:9],\\not_strict_mode.app_rd_data_reg[7]_0 ,rd_data_r[7:6]}),\n .if_empty_r(if_empty_r),\n .if_empty_r_0(if_empty_r_0),\n .if_empty_r_1(if_empty_r_1),\n .ififo_rst(ififo_rst),\n .mux_rd_valid_r_reg(mux_rd_valid_r_reg),\n .\\my_empty_reg[4]_0 (\\my_empty_reg[4] ),\n .\\my_empty_reg[4]_1 (\\my_empty_reg[4]_0 ),\n .\\not_strict_mode.app_rd_data_reg[0] (\\not_strict_mode.app_rd_data_reg[0] ),\n .\\not_strict_mode.app_rd_data_reg[100] (\\not_strict_mode.app_rd_data_reg[100] ),\n .\\not_strict_mode.app_rd_data_reg[101] (\\not_strict_mode.app_rd_data_reg[101] ),\n .\\not_strict_mode.app_rd_data_reg[102] (\\not_strict_mode.app_rd_data_reg[102] ),\n .\\not_strict_mode.app_rd_data_reg[103] (\\not_strict_mode.app_rd_data_reg[103] ),\n .\\not_strict_mode.app_rd_data_reg[128] (\\not_strict_mode.app_rd_data_reg[128] ),\n .\\not_strict_mode.app_rd_data_reg[129] (\\not_strict_mode.app_rd_data_reg[129] ),\n .\\not_strict_mode.app_rd_data_reg[130] (\\not_strict_mode.app_rd_data_reg[130] ),\n .\\not_strict_mode.app_rd_data_reg[131] (\\not_strict_mode.app_rd_data_reg[131] ),\n .\\not_strict_mode.app_rd_data_reg[132] (\\not_strict_mode.app_rd_data_reg[132] ),\n .\\not_strict_mode.app_rd_data_reg[133] (\\not_strict_mode.app_rd_data_reg[133] ),\n .\\not_strict_mode.app_rd_data_reg[134] (\\not_strict_mode.app_rd_data_reg[134] ),\n .\\not_strict_mode.app_rd_data_reg[135] (\\not_strict_mode.app_rd_data_reg[135] ),\n .\\not_strict_mode.app_rd_data_reg[160] (\\not_strict_mode.app_rd_data_reg[160] ),\n .\\not_strict_mode.app_rd_data_reg[161] (\\not_strict_mode.app_rd_data_reg[161] ),\n .\\not_strict_mode.app_rd_data_reg[162] (\\not_strict_mode.app_rd_data_reg[162] ),\n .\\not_strict_mode.app_rd_data_reg[163] (\\not_strict_mode.app_rd_data_reg[163] ),\n .\\not_strict_mode.app_rd_data_reg[164] (\\not_strict_mode.app_rd_data_reg[164] ),\n .\\not_strict_mode.app_rd_data_reg[165] (\\not_strict_mode.app_rd_data_reg[165] ),\n .\\not_strict_mode.app_rd_data_reg[166] (\\not_strict_mode.app_rd_data_reg[166] ),\n .\\not_strict_mode.app_rd_data_reg[167] (\\not_strict_mode.app_rd_data_reg[167] ),\n .\\not_strict_mode.app_rd_data_reg[192] (\\not_strict_mode.app_rd_data_reg[192] ),\n .\\not_strict_mode.app_rd_data_reg[193] (\\not_strict_mode.app_rd_data_reg[193] ),\n .\\not_strict_mode.app_rd_data_reg[194] (\\not_strict_mode.app_rd_data_reg[194] ),\n .\\not_strict_mode.app_rd_data_reg[195] (\\not_strict_mode.app_rd_data_reg[195] ),\n .\\not_strict_mode.app_rd_data_reg[196] (\\not_strict_mode.app_rd_data_reg[196] ),\n .\\not_strict_mode.app_rd_data_reg[197] (\\not_strict_mode.app_rd_data_reg[197] ),\n .\\not_strict_mode.app_rd_data_reg[198] (\\not_strict_mode.app_rd_data_reg[198] ),\n .\\not_strict_mode.app_rd_data_reg[199] (\\not_strict_mode.app_rd_data_reg[199] ),\n .\\not_strict_mode.app_rd_data_reg[1] (\\not_strict_mode.app_rd_data_reg[1] ),\n .\\not_strict_mode.app_rd_data_reg[224] (\\not_strict_mode.app_rd_data_reg[224] ),\n .\\not_strict_mode.app_rd_data_reg[225] (\\not_strict_mode.app_rd_data_reg[225] ),\n .\\not_strict_mode.app_rd_data_reg[226] (\\not_strict_mode.app_rd_data_reg[226] ),\n .\\not_strict_mode.app_rd_data_reg[227] (\\not_strict_mode.app_rd_data_reg[227] ),\n .\\not_strict_mode.app_rd_data_reg[228] (\\not_strict_mode.app_rd_data_reg[228] ),\n .\\not_strict_mode.app_rd_data_reg[228]_0 (\\not_strict_mode.app_rd_data_reg[228]_0 ),\n .\\not_strict_mode.app_rd_data_reg[229] (\\not_strict_mode.app_rd_data_reg[229] ),\n .\\not_strict_mode.app_rd_data_reg[230] (\\not_strict_mode.app_rd_data_reg[230] ),\n .\\not_strict_mode.app_rd_data_reg[231] (\\not_strict_mode.app_rd_data_reg[231] ),\n .\\not_strict_mode.app_rd_data_reg[231]_0 (\\not_strict_mode.app_rd_data_reg[231]_0 ),\n .\\not_strict_mode.app_rd_data_reg[2] (\\not_strict_mode.app_rd_data_reg[2] ),\n .\\not_strict_mode.app_rd_data_reg[32] (\\not_strict_mode.app_rd_data_reg[32] ),\n .\\not_strict_mode.app_rd_data_reg[33] (\\not_strict_mode.app_rd_data_reg[33] ),\n .\\not_strict_mode.app_rd_data_reg[34] (\\not_strict_mode.app_rd_data_reg[34] ),\n .\\not_strict_mode.app_rd_data_reg[35] (\\not_strict_mode.app_rd_data_reg[35] ),\n .\\not_strict_mode.app_rd_data_reg[36] (\\not_strict_mode.app_rd_data_reg[36] ),\n .\\not_strict_mode.app_rd_data_reg[37] (\\not_strict_mode.app_rd_data_reg[37] ),\n .\\not_strict_mode.app_rd_data_reg[38] (\\not_strict_mode.app_rd_data_reg[38] ),\n .\\not_strict_mode.app_rd_data_reg[39] (\\not_strict_mode.app_rd_data_reg[39] ),\n .\\not_strict_mode.app_rd_data_reg[3] (\\not_strict_mode.app_rd_data_reg[3] ),\n .\\not_strict_mode.app_rd_data_reg[4] (\\not_strict_mode.app_rd_data_reg[4] ),\n .\\not_strict_mode.app_rd_data_reg[5] (\\not_strict_mode.app_rd_data_reg[5] ),\n .\\not_strict_mode.app_rd_data_reg[64] (\\not_strict_mode.app_rd_data_reg[64] ),\n .\\not_strict_mode.app_rd_data_reg[65] (\\not_strict_mode.app_rd_data_reg[65] ),\n .\\not_strict_mode.app_rd_data_reg[66] (\\not_strict_mode.app_rd_data_reg[66] ),\n .\\not_strict_mode.app_rd_data_reg[67] (\\not_strict_mode.app_rd_data_reg[67] ),\n .\\not_strict_mode.app_rd_data_reg[68] (\\not_strict_mode.app_rd_data_reg[68] ),\n .\\not_strict_mode.app_rd_data_reg[69] (\\not_strict_mode.app_rd_data_reg[69] ),\n .\\not_strict_mode.app_rd_data_reg[6] (\\not_strict_mode.app_rd_data_reg[6] ),\n .\\not_strict_mode.app_rd_data_reg[70] (\\not_strict_mode.app_rd_data_reg[70] ),\n .\\not_strict_mode.app_rd_data_reg[71] (\\not_strict_mode.app_rd_data_reg[71] ),\n .\\not_strict_mode.app_rd_data_reg[7] (\\not_strict_mode.app_rd_data_reg[7] ),\n .\\not_strict_mode.app_rd_data_reg[7]_0 (\\not_strict_mode.app_rd_data_reg[7]_1 ),\n .\\not_strict_mode.app_rd_data_reg[96] (\\not_strict_mode.app_rd_data_reg[96] ),\n .\\not_strict_mode.app_rd_data_reg[97] (\\not_strict_mode.app_rd_data_reg[97] ),\n .\\not_strict_mode.app_rd_data_reg[98] (\\not_strict_mode.app_rd_data_reg[98] ),\n .\\not_strict_mode.app_rd_data_reg[99] (\\not_strict_mode.app_rd_data_reg[99] ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ),\n .\\read_fifo.fifo_out_data_r_reg[6] (\\read_fifo.fifo_out_data_r_reg[6] ));\n FDSE #(\n .INIT(1'b1)) \n ififo_rst_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .Q(ififo_rst),\n .S(phy_if_reset));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n IN_FIFO #(\n .ALMOST_EMPTY_VALUE(1),\n .ALMOST_FULL_VALUE(1),\n .ARRAY_MODE(\"ARRAY_MODE_4_X_8\"),\n .SYNCHRONOUS_MODE(\"FALSE\")) \n \\in_fifo_gen.in_fifo \n (.ALMOSTEMPTY(\\in_fifo_gen.in_fifo_n_0 ),\n .ALMOSTFULL(\\in_fifo_gen.in_fifo_n_1 ),\n .D0({1'b0,1'b0,1'b0,1'b0}),\n .D1(if_d1),\n .D2(if_d2),\n .D3(if_d3),\n .D4(if_d4),\n .D5({\\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED [7:4],if_d5}),\n .D6({\\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED [7:4],if_d6}),\n .D7(if_d7),\n .D8(if_d8),\n .D9({1'b0,1'b0,1'b0,1'b0}),\n .EMPTY(if_empty_),\n .FULL(\\in_fifo_gen.in_fifo_n_3 ),\n .Q0(rd_data[7:0]),\n .Q1(rd_data[15:8]),\n .Q2(rd_data[23:16]),\n .Q3(rd_data[31:24]),\n .Q4(rd_data[39:32]),\n .Q5(rd_data[47:40]),\n .Q6(rd_data[55:48]),\n .Q7(rd_data[63:56]),\n .Q8(rd_data[71:64]),\n .Q9(rd_data[79:72]),\n .RDCLK(CLK),\n .RDEN(1'b1),\n .RESET(ififo_rst),\n .WRCLK(iserdes_clkdiv),\n .WREN(ififo_wr_enable));\n ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized5 \\of_pre_fifo_gen.u_ddr_of_pre_fifo \n (.CLK(CLK),\n .D0({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }),\n .D9(of_d9),\n .Q(Q),\n .init_calib_complete_reg_rep(init_calib_complete_reg_rep),\n .mux_wrdata_en(mux_wrdata_en),\n .\\my_empty_reg[1]_0 (\\my_empty_reg[1] ),\n .\\my_empty_reg[7]_0 (\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ),\n .\\my_empty_reg[7]_1 (\\my_empty_reg[7] ),\n .ofifo_rst(ofifo_rst),\n .ofifo_rst_reg(out_fifo_n_3),\n .phy_dout(phy_dout),\n .\\write_buffer.wr_buf_out_data_reg[284] (\\write_buffer.wr_buf_out_data_reg[284] ));\n FDSE #(\n .INIT(1'b1)) \n ofifo_rst_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .Q(ofifo_rst),\n .S(A_rst_primitives));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n OUT_FIFO #(\n .ALMOST_EMPTY_VALUE(1),\n .ALMOST_FULL_VALUE(1),\n .ARRAY_MODE(\"ARRAY_MODE_8_X_4\"),\n .OUTPUT_DISABLE(\"FALSE\"),\n .SYNCHRONOUS_MODE(\"FALSE\")) \n out_fifo\n (.ALMOSTEMPTY(out_fifo_n_0),\n .ALMOSTFULL(out_fifo_n_1),\n .D0({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }),\n .D1(\\write_buffer.wr_buf_out_data_reg[231] ),\n .D2(\\write_buffer.wr_buf_out_data_reg[230] ),\n .D3(\\write_buffer.wr_buf_out_data_reg[229] ),\n .D4(\\write_buffer.wr_buf_out_data_reg[228] ),\n .D5(\\write_buffer.wr_buf_out_data_reg[227] ),\n .D6(\\write_buffer.wr_buf_out_data_reg[226] ),\n .D7(\\write_buffer.wr_buf_out_data_reg[225] ),\n .D8(\\write_buffer.wr_buf_out_data_reg[224] ),\n .D9(of_d9),\n .EMPTY(out_fifo_n_2),\n .FULL(out_fifo_n_3),\n .Q0(of_dqbus[3:0]),\n .Q1(of_dqbus[7:4]),\n .Q2(of_dqbus[11:8]),\n .Q3(of_dqbus[15:12]),\n .Q4(of_dqbus[19:16]),\n .Q5({NLW_out_fifo_Q5_UNCONNECTED[7:4],of_dqbus[23:20]}),\n .Q6({NLW_out_fifo_Q6_UNCONNECTED[7:4],of_dqbus[27:24]}),\n .Q7(of_dqbus[31:28]),\n .Q8(of_dqbus[35:32]),\n .Q9(of_dqbus[39:36]),\n .RDCLK(oserdes_clkdiv),\n .RDEN(po_rd_enable),\n .RESET(ofifo_rst),\n .WRCLK(CLK),\n .WREN(\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n PHASER_IN_PHY #(\n .BURST_MODE(\"TRUE\"),\n .CLKOUT_DIV(2),\n .DQS_BIAS_MODE(\"FALSE\"),\n .DQS_FIND_PATTERN(3'b000),\n .FINE_DELAY(33),\n .FREQ_REF_DIV(\"NONE\"),\n .IS_RST_INVERTED(1'b0),\n .MEMREFCLK_PERIOD(1.112000),\n .OUTPUT_CLK_SRC(\"DELAYED_REF\"),\n .PHASEREFCLK_PERIOD(1.112000),\n .REFCLK_PERIOD(1.112000),\n .SEL_CLK_OFFSET(6),\n .SYNC_IN_DIV_RST(\"TRUE\"),\n .WR_CYCLES(\"FALSE\")) \n \\phaser_in_gen.phaser_in \n (.BURSTPENDINGPHY(phaser_ctl_bus[1]),\n .COUNTERLOADEN(\\gen_byte_sel_div1.calib_in_common_reg ),\n .COUNTERLOADVAL(\\calib_zero_inputs_reg[0] ),\n .COUNTERREADEN(\\calib_sel_reg[0] ),\n .COUNTERREADVAL(D_pi_counter_read_val),\n .DQSFOUND(\\pi_dqs_found_lanes_r1_reg[3] ),\n .DQSOUTOFRANGE(\\phaser_in_gen.phaser_in_n_1 ),\n .ENCALIBPHY(PCENABLECALIB),\n .FINEENABLE(pi_en_stg2_f_reg),\n .FINEINC(pi_stg2_f_incdec_reg),\n .FINEOVERFLOW(\\phaser_in_gen.phaser_in_n_2 ),\n .FREQREFCLK(freq_refclk),\n .ICLK(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),\n .ICLKDIV(iserdes_clkdiv),\n .ISERDESRST(\\phaser_in_gen.phaser_in_n_5 ),\n .MEMREFCLK(mem_refclk),\n .PHASELOCKED(pi_phase_locked_all_r1_reg),\n .PHASEREFCLK(mem_dqs_in),\n .RANKSELPHY(phaser_ctl_bus[3:2]),\n .RCLK(\\phaser_in_gen.phaser_in_n_7 ),\n .RST(A_rst_primitives),\n .RSTDQSFIND(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .SYNCIN(sync_pulse),\n .SYSCLK(CLK),\n .WRENABLE(ififo_wr_enable));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n PHASER_OUT_PHY #(\n .CLKOUT_DIV(2),\n .COARSE_BYPASS(\"FALSE\"),\n .COARSE_DELAY(0),\n .DATA_CTL_N(\"TRUE\"),\n .DATA_RD_CYCLES(\"FALSE\"),\n .FINE_DELAY(60),\n .IS_RST_INVERTED(1'b0),\n .MEMREFCLK_PERIOD(1.112000),\n .OCLKDELAY_INV(\"TRUE\"),\n .OCLK_DELAY(28),\n .OUTPUT_CLK_SRC(\"DELAYED_REF\"),\n .PHASEREFCLK_PERIOD(1.000000),\n .PO(3'b111),\n .REFCLK_PERIOD(1.112000),\n .SYNC_IN_DIV_RST(\"TRUE\")) \n phaser_out\n (.BURSTPENDINGPHY(phaser_ctl_bus[0]),\n .COARSEENABLE(\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .COARSEINC(\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .COARSEOVERFLOW(phaser_out_n_0),\n .COUNTERLOADEN(1'b0),\n .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .COUNTERREADEN(\\calib_sel_reg[0] ),\n .COUNTERREADVAL(D_po_counter_read_val),\n .CTSBUS(oserdes_dqs_ts),\n .DQSBUS(oserdes_dqs),\n .DTSBUS(oserdes_dq_ts),\n .ENCALIBPHY(PCENABLECALIB),\n .FINEENABLE(ck_po_stg2_f_en_reg),\n .FINEINC(ck_po_stg2_f_indec_reg),\n .FINEOVERFLOW(phaser_out_n_1),\n .FREQREFCLK(freq_refclk),\n .MEMREFCLK(mem_refclk),\n .OCLK(oserdes_clk),\n .OCLKDELAYED(oserdes_clk_delayed),\n .OCLKDIV(oserdes_clkdiv),\n .OSERDESRST(po_oserdes_rst),\n .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),\n .RDENABLE(po_rd_enable),\n .RST(A_rst_primitives),\n .SELFINEOCLKDELAY(delay_done_r4_reg),\n .SYNCIN(sync_pulse),\n .SYSCLK(CLK));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\pi_counter_read_val[0]_i_1 \n (.I0(D_pi_counter_read_val[0]),\n .I1(COUNTERREADVAL[0]),\n .I2(\\calib_sel_reg[1] [0]),\n .I3(A_rst_primitives_reg[0]),\n .I4(\\calib_sel_reg[1] [1]),\n .I5(A_rst_primitives_reg_0[0]),\n .O(D[0]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\pi_counter_read_val[1]_i_1 \n (.I0(D_pi_counter_read_val[1]),\n .I1(COUNTERREADVAL[1]),\n .I2(\\calib_sel_reg[1] [0]),\n .I3(A_rst_primitives_reg[1]),\n .I4(\\calib_sel_reg[1] [1]),\n .I5(A_rst_primitives_reg_0[1]),\n .O(D[1]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\pi_counter_read_val[2]_i_1 \n (.I0(D_pi_counter_read_val[2]),\n .I1(COUNTERREADVAL[2]),\n .I2(\\calib_sel_reg[1] [0]),\n .I3(A_rst_primitives_reg[2]),\n .I4(\\calib_sel_reg[1] [1]),\n .I5(A_rst_primitives_reg_0[2]),\n .O(D[2]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\pi_counter_read_val[3]_i_1 \n (.I0(D_pi_counter_read_val[3]),\n .I1(COUNTERREADVAL[3]),\n .I2(\\calib_sel_reg[1] [0]),\n .I3(A_rst_primitives_reg[3]),\n .I4(\\calib_sel_reg[1] [1]),\n .I5(A_rst_primitives_reg_0[3]),\n .O(D[3]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\pi_counter_read_val[4]_i_1 \n (.I0(D_pi_counter_read_val[4]),\n .I1(COUNTERREADVAL[4]),\n .I2(\\calib_sel_reg[1] [0]),\n .I3(A_rst_primitives_reg[4]),\n .I4(\\calib_sel_reg[1] [1]),\n .I5(A_rst_primitives_reg_0[4]),\n .O(D[4]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\pi_counter_read_val[5]_i_1 \n (.I0(D_pi_counter_read_val[5]),\n .I1(COUNTERREADVAL[5]),\n .I2(\\calib_sel_reg[1] [0]),\n .I3(A_rst_primitives_reg[5]),\n .I4(\\calib_sel_reg[1] [1]),\n .I5(A_rst_primitives_reg_0[5]),\n .O(D[5]));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[0]_i_1__0 \n (.I0(D_po_counter_read_val[0]),\n .I1(A_rst_primitives_reg_1[0]),\n .I2(A_rst_primitives_reg_2[0]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_3[0]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(\\po_counter_read_val_reg[8] [0]));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[1]_i_1__0 \n (.I0(D_po_counter_read_val[1]),\n .I1(A_rst_primitives_reg_1[1]),\n .I2(A_rst_primitives_reg_2[1]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_3[1]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(\\po_counter_read_val_reg[8] [1]));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[2]_i_1__0 \n (.I0(D_po_counter_read_val[2]),\n .I1(A_rst_primitives_reg_1[2]),\n .I2(A_rst_primitives_reg_2[2]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_3[2]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(\\po_counter_read_val_reg[8] [2]));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[3]_i_1__0 \n (.I0(D_po_counter_read_val[3]),\n .I1(A_rst_primitives_reg_1[3]),\n .I2(A_rst_primitives_reg_2[3]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_3[3]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(\\po_counter_read_val_reg[8] [3]));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[4]_i_1__0 \n (.I0(D_po_counter_read_val[4]),\n .I1(A_rst_primitives_reg_1[4]),\n .I2(A_rst_primitives_reg_2[4]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_3[4]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(\\po_counter_read_val_reg[8] [4]));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[5]_i_1__0 \n (.I0(D_po_counter_read_val[5]),\n .I1(A_rst_primitives_reg_1[5]),\n .I2(A_rst_primitives_reg_2[5]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_3[5]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(\\po_counter_read_val_reg[8] [5]));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[6]_i_1__0 \n (.I0(D_po_counter_read_val[6]),\n .I1(A_rst_primitives_reg_1[6]),\n .I2(A_rst_primitives_reg_2[6]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_3[6]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(\\po_counter_read_val_reg[8] [6]));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[7]_i_1__0 \n (.I0(D_po_counter_read_val[7]),\n .I1(A_rst_primitives_reg_1[7]),\n .I2(A_rst_primitives_reg_2[7]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_3[7]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(\\po_counter_read_val_reg[8] [7]));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[8]_i_1__0 \n (.I0(D_po_counter_read_val[8]),\n .I1(A_rst_primitives_reg_1[8]),\n .I2(A_rst_primitives_reg_2[8]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_3[8]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(\\po_counter_read_val_reg[8] [8]));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_byte_lane\" *) \nmodule ddr3_if_mig_7series_v4_0_ddr_byte_lane__parameterized3\n (SR,\n \\rd_ptr_timing_reg[2] ,\n \\rd_ptr_timing_reg[2]_0 ,\n \\rd_ptr_timing_reg[2]_1 ,\n \\rd_ptr_timing_reg[2]_2 ,\n A_of_full,\n COUNTERREADVAL,\n wr_en,\n \\my_empty_reg[1] ,\n Q,\n mem_dq_out,\n A_rst_primitives,\n CLK,\n D0,\n D1,\n OUTBURSTPENDING,\n \\calib_sel_reg[1] ,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n \\calib_sel_reg[1]_0 ,\n \\calib_sel_reg[1]_1 ,\n freq_refclk,\n mem_refclk,\n \\calib_sel_reg[1]_2 ,\n sync_pulse,\n PCENABLECALIB,\n mux_cmd_wren,\n mem_out);\n output [0:0]SR;\n output \\rd_ptr_timing_reg[2] ;\n output \\rd_ptr_timing_reg[2]_0 ;\n output \\rd_ptr_timing_reg[2]_1 ;\n output \\rd_ptr_timing_reg[2]_2 ;\n output A_of_full;\n output [8:0]COUNTERREADVAL;\n output wr_en;\n output \\my_empty_reg[1] ;\n output [3:0]Q;\n output [1:0]mem_dq_out;\n input A_rst_primitives;\n input CLK;\n input [2:0]D0;\n input [2:0]D1;\n input [0:0]OUTBURSTPENDING;\n input \\calib_sel_reg[1] ;\n input \\gen_byte_sel_div1.calib_in_common_reg ;\n input \\calib_sel_reg[1]_0 ;\n input \\calib_sel_reg[1]_1 ;\n input freq_refclk;\n input mem_refclk;\n input \\calib_sel_reg[1]_2 ;\n input sync_pulse;\n input [1:0]PCENABLECALIB;\n input mux_cmd_wren;\n input [11:0]mem_out;\n\n wire A_of_a_full;\n wire A_of_full;\n wire A_po_coarse_overflow;\n wire A_po_fine_overflow;\n wire A_rst_primitives;\n wire CLK;\n wire [8:0]COUNTERREADVAL;\n wire [2:0]D0;\n wire [2:0]D1;\n wire [0:0]OUTBURSTPENDING;\n wire [1:0]PCENABLECALIB;\n wire [3:0]Q;\n wire [0:0]SR;\n wire \\calib_sel_reg[1] ;\n wire \\calib_sel_reg[1]_0 ;\n wire \\calib_sel_reg[1]_1 ;\n wire \\calib_sel_reg[1]_2 ;\n wire freq_refclk;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire [1:0]mem_dq_out;\n wire [11:0]mem_out;\n wire mem_refclk;\n wire mux_cmd_wren;\n wire \\my_empty_reg[1] ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ;\n wire [3:0]of_q0;\n wire [3:0]of_q1;\n wire [3:0]of_q2;\n wire [3:0]of_q3;\n wire [3:0]of_q4;\n wire [7:0]of_q5;\n wire [7:0]of_q6;\n wire [3:0]of_q7;\n wire [3:0]of_q8;\n wire [3:0]of_q9;\n wire oserdes_clk;\n wire oserdes_clk_delayed;\n wire oserdes_clkdiv;\n wire [1:0]oserdes_dq_ts;\n wire [1:0]oserdes_dqs;\n wire [1:0]oserdes_dqs_ts;\n wire out_fifo_n_0;\n wire out_fifo_n_2;\n wire po_oserdes_rst;\n wire po_rd_enable;\n wire \\rd_ptr_timing_reg[2] ;\n wire \\rd_ptr_timing_reg[2]_0 ;\n wire \\rd_ptr_timing_reg[2]_1 ;\n wire \\rd_ptr_timing_reg[2]_2 ;\n wire sync_pulse;\n wire wr_en;\n wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;\n\n ddr3_if_mig_7series_v4_0_ddr_byte_group_io__parameterized3 ddr_byte_group_io\n (.mem_dq_out(mem_dq_out),\n .oserdes_clk(oserdes_clk),\n .oserdes_clkdiv(oserdes_clkdiv),\n .oserdes_dq({of_q1,of_q0}),\n .oserdes_rst(po_oserdes_rst));\n ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized6 \\of_pre_fifo_gen.u_ddr_of_pre_fifo \n (.CLK(CLK),\n .D0({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 }),\n .D1({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 }),\n .D2({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 }),\n .Q(Q),\n .SR(SR),\n .mem_out(mem_out),\n .mux_cmd_wren(mux_cmd_wren),\n .\\my_empty_reg[1]_0 (\\my_empty_reg[1] ),\n .ofifo_rst_reg(A_of_full),\n .\\rd_ptr_timing_reg[0]_0 (\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ),\n .\\rd_ptr_timing_reg[2]_0 (\\rd_ptr_timing_reg[2] ),\n .\\rd_ptr_timing_reg[2]_1 (\\rd_ptr_timing_reg[2]_0 ),\n .\\rd_ptr_timing_reg[2]_2 (\\rd_ptr_timing_reg[2]_1 ),\n .\\rd_ptr_timing_reg[2]_3 (\\rd_ptr_timing_reg[2]_2 ),\n .wr_en(wr_en));\n FDRE #(\n .INIT(1'b1)) \n ofifo_rst_reg\n (.C(CLK),\n .CE(1'b1),\n .D(A_rst_primitives),\n .Q(SR),\n .R(1'b0));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n OUT_FIFO #(\n .ALMOST_EMPTY_VALUE(1),\n .ALMOST_FULL_VALUE(1),\n .ARRAY_MODE(\"ARRAY_MODE_4_X_4\"),\n .OUTPUT_DISABLE(\"FALSE\"),\n .SYNCHRONOUS_MODE(\"FALSE\")) \n out_fifo\n (.ALMOSTEMPTY(out_fifo_n_0),\n .ALMOSTFULL(A_of_a_full),\n .D0({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,D0}),\n .D1({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ,D1}),\n .D2({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 }),\n .D3({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 }),\n .D4({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 }),\n .D5({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 }),\n .D6({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 }),\n .D7({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 }),\n .D8({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 }),\n .D9({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 }),\n .EMPTY(out_fifo_n_2),\n .FULL(A_of_full),\n .Q0(of_q0),\n .Q1(of_q1),\n .Q2(of_q2),\n .Q3(of_q3),\n .Q4(of_q4),\n .Q5(of_q5),\n .Q6(of_q6),\n .Q7(of_q7),\n .Q8(of_q8),\n .Q9(of_q9),\n .RDCLK(oserdes_clkdiv),\n .RDEN(po_rd_enable),\n .RESET(SR),\n .WRCLK(CLK),\n .WREN(\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n PHASER_OUT_PHY #(\n .CLKOUT_DIV(4),\n .COARSE_BYPASS(\"FALSE\"),\n .COARSE_DELAY(0),\n .DATA_CTL_N(\"FALSE\"),\n .DATA_RD_CYCLES(\"FALSE\"),\n .FINE_DELAY(60),\n .IS_RST_INVERTED(1'b0),\n .MEMREFCLK_PERIOD(1.112000),\n .OCLKDELAY_INV(\"TRUE\"),\n .OCLK_DELAY(28),\n .OUTPUT_CLK_SRC(\"DELAYED_REF\"),\n .PHASEREFCLK_PERIOD(1.000000),\n .PO(3'b111),\n .REFCLK_PERIOD(1.112000),\n .SYNC_IN_DIV_RST(\"TRUE\")) \n phaser_out\n (.BURSTPENDINGPHY(OUTBURSTPENDING),\n .COARSEENABLE(\\calib_sel_reg[1] ),\n .COARSEINC(\\calib_sel_reg[1] ),\n .COARSEOVERFLOW(A_po_coarse_overflow),\n .COUNTERLOADEN(1'b0),\n .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .COUNTERREADEN(\\gen_byte_sel_div1.calib_in_common_reg ),\n .COUNTERREADVAL(COUNTERREADVAL),\n .CTSBUS(oserdes_dqs_ts),\n .DQSBUS(oserdes_dqs),\n .DTSBUS(oserdes_dq_ts),\n .ENCALIBPHY(PCENABLECALIB),\n .FINEENABLE(\\calib_sel_reg[1]_0 ),\n .FINEINC(\\calib_sel_reg[1]_1 ),\n .FINEOVERFLOW(A_po_fine_overflow),\n .FREQREFCLK(freq_refclk),\n .MEMREFCLK(mem_refclk),\n .OCLK(oserdes_clk),\n .OCLKDELAYED(oserdes_clk_delayed),\n .OCLKDIV(oserdes_clkdiv),\n .OSERDESRST(po_oserdes_rst),\n .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),\n .RDENABLE(po_rd_enable),\n .RST(A_rst_primitives),\n .SELFINEOCLKDELAY(\\calib_sel_reg[1]_2 ),\n .SYNCIN(sync_pulse),\n .SYSCLK(CLK));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_byte_lane\" *) \nmodule ddr3_if_mig_7series_v4_0_ddr_byte_lane__parameterized4\n (\\rd_ptr_timing_reg[2] ,\n \\rd_ptr_timing_reg[2]_0 ,\n \\rd_ptr_timing_reg[2]_1 ,\n \\rd_ptr_timing_reg[2]_2 ,\n COUNTERREADVAL,\n wr_en_5,\n \\my_empty_reg[1] ,\n of_ctl_full_v,\n Q,\n mem_dq_out,\n SR,\n CLK,\n init_calib_complete_reg_rep__6,\n D5,\n D6,\n OUTBURSTPENDING,\n \\calib_sel_reg[1] ,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n \\calib_sel_reg[1]_0 ,\n \\calib_sel_reg[1]_1 ,\n freq_refclk,\n mem_refclk,\n A_rst_primitives,\n \\calib_sel_reg[1]_2 ,\n sync_pulse,\n PCENABLECALIB,\n mux_cmd_wren,\n \\rd_ptr_reg[3] ,\n C_of_full,\n A_of_full,\n D_of_full);\n output \\rd_ptr_timing_reg[2] ;\n output \\rd_ptr_timing_reg[2]_0 ;\n output \\rd_ptr_timing_reg[2]_1 ;\n output \\rd_ptr_timing_reg[2]_2 ;\n output [8:0]COUNTERREADVAL;\n output wr_en_5;\n output \\my_empty_reg[1] ;\n output [0:0]of_ctl_full_v;\n output [3:0]Q;\n output [2:0]mem_dq_out;\n input [0:0]SR;\n input CLK;\n input [3:0]init_calib_complete_reg_rep__6;\n input [3:0]D5;\n input [3:0]D6;\n input [0:0]OUTBURSTPENDING;\n input \\calib_sel_reg[1] ;\n input \\gen_byte_sel_div1.calib_in_common_reg ;\n input \\calib_sel_reg[1]_0 ;\n input \\calib_sel_reg[1]_1 ;\n input freq_refclk;\n input mem_refclk;\n input A_rst_primitives;\n input \\calib_sel_reg[1]_2 ;\n input sync_pulse;\n input [1:0]PCENABLECALIB;\n input mux_cmd_wren;\n input [17:0]\\rd_ptr_reg[3] ;\n input C_of_full;\n input A_of_full;\n input D_of_full;\n\n wire A_of_full;\n wire A_rst_primitives;\n wire B_of_a_full;\n wire B_of_full;\n wire B_po_coarse_overflow;\n wire B_po_fine_overflow;\n wire CLK;\n wire [8:0]COUNTERREADVAL;\n wire C_of_full;\n wire [3:0]D5;\n wire [3:0]D6;\n wire D_of_full;\n wire [0:0]OUTBURSTPENDING;\n wire [1:0]PCENABLECALIB;\n wire [3:0]Q;\n wire [0:0]SR;\n wire \\calib_sel_reg[1] ;\n wire \\calib_sel_reg[1]_0 ;\n wire \\calib_sel_reg[1]_1 ;\n wire \\calib_sel_reg[1]_2 ;\n wire freq_refclk;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire [3:0]init_calib_complete_reg_rep__6;\n wire [2:0]mem_dq_out;\n wire mem_refclk;\n wire mux_cmd_wren;\n wire \\my_empty_reg[1] ;\n wire [0:0]of_ctl_full_v;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ;\n wire [3:0]of_q0;\n wire [3:0]of_q1;\n wire [3:0]of_q2;\n wire [3:0]of_q3;\n wire [3:0]of_q4;\n wire [7:0]of_q5;\n wire [7:0]of_q6;\n wire [3:0]of_q7;\n wire [3:0]of_q8;\n wire [3:0]of_q9;\n wire oserdes_clk;\n wire oserdes_clk_delayed;\n wire oserdes_clkdiv;\n wire [1:0]oserdes_dq_ts;\n wire [1:0]oserdes_dqs;\n wire [1:0]oserdes_dqs_ts;\n wire out_fifo_n_0;\n wire out_fifo_n_2;\n wire po_oserdes_rst;\n wire po_rd_enable;\n wire [17:0]\\rd_ptr_reg[3] ;\n wire \\rd_ptr_timing_reg[2] ;\n wire \\rd_ptr_timing_reg[2]_0 ;\n wire \\rd_ptr_timing_reg[2]_1 ;\n wire \\rd_ptr_timing_reg[2]_2 ;\n wire sync_pulse;\n wire wr_en_5;\n wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;\n\n ddr3_if_mig_7series_v4_0_ddr_byte_group_io__parameterized4 ddr_byte_group_io\n (.mem_dq_out(mem_dq_out),\n .oserdes_clk(oserdes_clk),\n .oserdes_clkdiv(oserdes_clkdiv),\n .oserdes_dq({of_q6[7:4],of_q5[7:4],of_q4}),\n .oserdes_rst(po_oserdes_rst));\n ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized7 \\of_pre_fifo_gen.u_ddr_of_pre_fifo \n (.B_of_full(B_of_full),\n .CLK(CLK),\n .D0({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 }),\n .D3({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 }),\n .D5({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 }),\n .D6({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 }),\n .D7({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 }),\n .Q(Q),\n .SR(SR),\n .mux_cmd_wren(mux_cmd_wren),\n .\\my_empty_reg[1]_0 (\\my_empty_reg[1] ),\n .\\my_full_reg[3]_0 (\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ),\n .\\rd_ptr_reg[3]_0 (\\rd_ptr_reg[3] ),\n .\\rd_ptr_timing_reg[2]_0 (\\rd_ptr_timing_reg[2] ),\n .\\rd_ptr_timing_reg[2]_1 (\\rd_ptr_timing_reg[2]_0 ),\n .\\rd_ptr_timing_reg[2]_2 (\\rd_ptr_timing_reg[2]_1 ),\n .\\rd_ptr_timing_reg[2]_3 (\\rd_ptr_timing_reg[2]_2 ),\n .wr_en_5(wr_en_5));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n OUT_FIFO #(\n .ALMOST_EMPTY_VALUE(1),\n .ALMOST_FULL_VALUE(1),\n .ARRAY_MODE(\"ARRAY_MODE_4_X_4\"),\n .OUTPUT_DISABLE(\"FALSE\"),\n .SYNCHRONOUS_MODE(\"FALSE\")) \n out_fifo\n (.ALMOSTEMPTY(out_fifo_n_0),\n .ALMOSTFULL(B_of_a_full),\n .D0({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 }),\n .D1({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 }),\n .D2({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 }),\n .D3({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 }),\n .D4({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,init_calib_complete_reg_rep__6}),\n .D5({D5,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 }),\n .D6({D6,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 }),\n .D7({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 }),\n .D8({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 }),\n .D9({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 }),\n .EMPTY(out_fifo_n_2),\n .FULL(B_of_full),\n .Q0(of_q0),\n .Q1(of_q1),\n .Q2(of_q2),\n .Q3(of_q3),\n .Q4(of_q4),\n .Q5(of_q5),\n .Q6(of_q6),\n .Q7(of_q7),\n .Q8(of_q8),\n .Q9(of_q9),\n .RDCLK(oserdes_clkdiv),\n .RDEN(po_rd_enable),\n .RESET(SR),\n .WRCLK(CLK),\n .WREN(\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n PHASER_OUT_PHY #(\n .CLKOUT_DIV(4),\n .COARSE_BYPASS(\"FALSE\"),\n .COARSE_DELAY(0),\n .DATA_CTL_N(\"FALSE\"),\n .DATA_RD_CYCLES(\"FALSE\"),\n .FINE_DELAY(60),\n .IS_RST_INVERTED(1'b0),\n .MEMREFCLK_PERIOD(1.112000),\n .OCLKDELAY_INV(\"TRUE\"),\n .OCLK_DELAY(28),\n .OUTPUT_CLK_SRC(\"DELAYED_REF\"),\n .PHASEREFCLK_PERIOD(1.000000),\n .PO(3'b111),\n .REFCLK_PERIOD(1.112000),\n .SYNC_IN_DIV_RST(\"TRUE\")) \n phaser_out\n (.BURSTPENDINGPHY(OUTBURSTPENDING),\n .COARSEENABLE(\\calib_sel_reg[1] ),\n .COARSEINC(\\calib_sel_reg[1] ),\n .COARSEOVERFLOW(B_po_coarse_overflow),\n .COUNTERLOADEN(1'b0),\n .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .COUNTERREADEN(\\gen_byte_sel_div1.calib_in_common_reg ),\n .COUNTERREADVAL(COUNTERREADVAL),\n .CTSBUS(oserdes_dqs_ts),\n .DQSBUS(oserdes_dqs),\n .DTSBUS(oserdes_dq_ts),\n .ENCALIBPHY(PCENABLECALIB),\n .FINEENABLE(\\calib_sel_reg[1]_0 ),\n .FINEINC(\\calib_sel_reg[1]_1 ),\n .FINEOVERFLOW(B_po_fine_overflow),\n .FREQREFCLK(freq_refclk),\n .MEMREFCLK(mem_refclk),\n .OCLK(oserdes_clk),\n .OCLKDELAYED(oserdes_clk_delayed),\n .OCLKDIV(oserdes_clkdiv),\n .OSERDESRST(po_oserdes_rst),\n .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),\n .RDENABLE(po_rd_enable),\n .RST(A_rst_primitives),\n .SELFINEOCLKDELAY(\\calib_sel_reg[1]_2 ),\n .SYNCIN(sync_pulse),\n .SYSCLK(CLK));\n LUT4 #(\n .INIT(16'hFFFE)) \n phy_mc_cmd_full_r_i_1\n (.I0(B_of_full),\n .I1(C_of_full),\n .I2(A_of_full),\n .I3(D_of_full),\n .O(of_ctl_full_v));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_byte_lane\" *) \nmodule ddr3_if_mig_7series_v4_0_ddr_byte_lane__parameterized5\n (C_of_full,\n \\rd_ptr_timing_reg[2] ,\n \\rd_ptr_timing_reg[2]_0 ,\n \\rd_ptr_timing_reg[2]_1 ,\n \\rd_ptr_timing_reg[2]_2 ,\n COUNTERREADVAL,\n wr_en_6,\n \\my_empty_reg[1] ,\n Q,\n mem_dq_out,\n SR,\n CLK,\n D2,\n D3,\n \\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ,\n \\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ,\n D7,\n D8,\n D9,\n OUTBURSTPENDING,\n \\calib_sel_reg[0] ,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n \\calib_sel_reg[0]_0 ,\n \\calib_sel_reg[0]_1 ,\n freq_refclk,\n mem_refclk,\n A_rst_primitives,\n \\calib_sel_reg[0]_2 ,\n sync_pulse,\n PCENABLECALIB,\n mux_cmd_wren,\n \\rd_ptr_reg[3] );\n output C_of_full;\n output \\rd_ptr_timing_reg[2] ;\n output \\rd_ptr_timing_reg[2]_0 ;\n output \\rd_ptr_timing_reg[2]_1 ;\n output \\rd_ptr_timing_reg[2]_2 ;\n output [8:0]COUNTERREADVAL;\n output wr_en_6;\n output \\my_empty_reg[1] ;\n output [3:0]Q;\n output [9:0]mem_dq_out;\n input [0:0]SR;\n input CLK;\n input [2:0]D2;\n input [2:0]D3;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ;\n input [7:0]\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ;\n input [7:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ;\n input [3:0]D7;\n input [3:0]D8;\n input [3:0]D9;\n input [0:0]OUTBURSTPENDING;\n input \\calib_sel_reg[0] ;\n input \\gen_byte_sel_div1.calib_in_common_reg ;\n input \\calib_sel_reg[0]_0 ;\n input \\calib_sel_reg[0]_1 ;\n input freq_refclk;\n input mem_refclk;\n input A_rst_primitives;\n input \\calib_sel_reg[0]_2 ;\n input sync_pulse;\n input [1:0]PCENABLECALIB;\n input mux_cmd_wren;\n input [33:0]\\rd_ptr_reg[3] ;\n\n wire A_rst_primitives;\n wire CLK;\n wire [8:0]COUNTERREADVAL;\n wire C_of_a_full;\n wire C_of_full;\n wire C_po_coarse_overflow;\n wire C_po_fine_overflow;\n wire [2:0]D2;\n wire [2:0]D3;\n wire [3:0]D7;\n wire [3:0]D8;\n wire [3:0]D9;\n wire [0:0]OUTBURSTPENDING;\n wire [1:0]PCENABLECALIB;\n wire [3:0]Q;\n wire [0:0]SR;\n wire \\calib_sel_reg[0] ;\n wire \\calib_sel_reg[0]_0 ;\n wire \\calib_sel_reg[0]_1 ;\n wire \\calib_sel_reg[0]_2 ;\n wire freq_refclk;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire [7:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ;\n wire [7:0]\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ;\n wire [9:0]mem_dq_out;\n wire mem_refclk;\n wire mux_cmd_wren;\n wire \\my_empty_reg[1] ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_40 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ;\n wire [3:0]of_q0;\n wire [3:0]of_q1;\n wire [3:0]of_q2;\n wire [3:0]of_q3;\n wire [3:0]of_q4;\n wire [7:0]of_q5;\n wire [7:0]of_q6;\n wire [3:0]of_q7;\n wire [3:0]of_q8;\n wire [3:0]of_q9;\n wire oserdes_clk;\n wire oserdes_clk_delayed;\n wire oserdes_clkdiv;\n wire [1:0]oserdes_dq_ts;\n wire [1:0]oserdes_dqs;\n wire [1:0]oserdes_dqs_ts;\n wire out_fifo_n_0;\n wire out_fifo_n_2;\n wire po_oserdes_rst;\n wire po_rd_enable;\n wire [33:0]\\rd_ptr_reg[3] ;\n wire \\rd_ptr_timing_reg[2] ;\n wire \\rd_ptr_timing_reg[2]_0 ;\n wire \\rd_ptr_timing_reg[2]_1 ;\n wire \\rd_ptr_timing_reg[2]_2 ;\n wire sync_pulse;\n wire wr_en_6;\n wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;\n\n ddr3_if_mig_7series_v4_0_ddr_byte_group_io__parameterized5 ddr_byte_group_io\n (.mem_dq_out(mem_dq_out),\n .oserdes_clk(oserdes_clk),\n .oserdes_clkdiv(oserdes_clkdiv),\n .oserdes_dq({of_q6[7:4],of_q5[7:4],of_q9,of_q8,of_q7,of_q6[3:0],of_q5[3:0],of_q4,of_q3,of_q2}),\n .po_oserdes_rst(po_oserdes_rst));\n ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized8 \\of_pre_fifo_gen.u_ddr_of_pre_fifo \n (.CLK(CLK),\n .D0({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 }),\n .D1({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 }),\n .D2({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 }),\n .D3({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 }),\n .D4({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 }),\n .D7({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 }),\n .D8({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 }),\n .D9({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_40 }),\n .Q(Q),\n .SR(SR),\n .mux_cmd_wren(mux_cmd_wren),\n .\\my_empty_reg[1]_0 (\\my_empty_reg[1] ),\n .ofifo_rst_reg(C_of_full),\n .\\rd_ptr_reg[3]_0 (\\rd_ptr_reg[3] ),\n .\\rd_ptr_timing_reg[0]_0 (\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ),\n .\\rd_ptr_timing_reg[2]_0 (\\rd_ptr_timing_reg[2] ),\n .\\rd_ptr_timing_reg[2]_1 (\\rd_ptr_timing_reg[2]_0 ),\n .\\rd_ptr_timing_reg[2]_2 (\\rd_ptr_timing_reg[2]_1 ),\n .\\rd_ptr_timing_reg[2]_3 (\\rd_ptr_timing_reg[2]_2 ),\n .wr_en_6(wr_en_6));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n OUT_FIFO #(\n .ALMOST_EMPTY_VALUE(1),\n .ALMOST_FULL_VALUE(1),\n .ARRAY_MODE(\"ARRAY_MODE_4_X_4\"),\n .OUTPUT_DISABLE(\"FALSE\"),\n .SYNCHRONOUS_MODE(\"FALSE\")) \n out_fifo\n (.ALMOSTEMPTY(out_fifo_n_0),\n .ALMOSTFULL(C_of_a_full),\n .D0({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 }),\n .D1({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 }),\n .D2({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,D2}),\n .D3({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ,D3}),\n .D4({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 ,\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] }),\n .D5(\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ),\n .D6(\\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ),\n .D7({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ,D7}),\n .D8({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ,D8}),\n .D9({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_40 ,D9}),\n .EMPTY(out_fifo_n_2),\n .FULL(C_of_full),\n .Q0(of_q0),\n .Q1(of_q1),\n .Q2(of_q2),\n .Q3(of_q3),\n .Q4(of_q4),\n .Q5(of_q5),\n .Q6(of_q6),\n .Q7(of_q7),\n .Q8(of_q8),\n .Q9(of_q9),\n .RDCLK(oserdes_clkdiv),\n .RDEN(po_rd_enable),\n .RESET(SR),\n .WRCLK(CLK),\n .WREN(\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n PHASER_OUT_PHY #(\n .CLKOUT_DIV(4),\n .COARSE_BYPASS(\"FALSE\"),\n .COARSE_DELAY(0),\n .DATA_CTL_N(\"FALSE\"),\n .DATA_RD_CYCLES(\"FALSE\"),\n .FINE_DELAY(60),\n .IS_RST_INVERTED(1'b0),\n .MEMREFCLK_PERIOD(1.112000),\n .OCLKDELAY_INV(\"TRUE\"),\n .OCLK_DELAY(28),\n .OUTPUT_CLK_SRC(\"DELAYED_REF\"),\n .PHASEREFCLK_PERIOD(1.000000),\n .PO(3'b111),\n .REFCLK_PERIOD(1.112000),\n .SYNC_IN_DIV_RST(\"TRUE\")) \n phaser_out\n (.BURSTPENDINGPHY(OUTBURSTPENDING),\n .COARSEENABLE(\\calib_sel_reg[0] ),\n .COARSEINC(\\calib_sel_reg[0] ),\n .COARSEOVERFLOW(C_po_coarse_overflow),\n .COUNTERLOADEN(1'b0),\n .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .COUNTERREADEN(\\gen_byte_sel_div1.calib_in_common_reg ),\n .COUNTERREADVAL(COUNTERREADVAL),\n .CTSBUS(oserdes_dqs_ts),\n .DQSBUS(oserdes_dqs),\n .DTSBUS(oserdes_dq_ts),\n .ENCALIBPHY(PCENABLECALIB),\n .FINEENABLE(\\calib_sel_reg[0]_0 ),\n .FINEINC(\\calib_sel_reg[0]_1 ),\n .FINEOVERFLOW(C_po_fine_overflow),\n .FREQREFCLK(freq_refclk),\n .MEMREFCLK(mem_refclk),\n .OCLK(oserdes_clk),\n .OCLKDELAYED(oserdes_clk_delayed),\n .OCLKDIV(oserdes_clkdiv),\n .OSERDESRST(po_oserdes_rst),\n .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),\n .RDENABLE(po_rd_enable),\n .RST(A_rst_primitives),\n .SELFINEOCLKDELAY(\\calib_sel_reg[0]_2 ),\n .SYNCIN(sync_pulse),\n .SYSCLK(CLK));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_byte_lane\" *) \nmodule ddr3_if_mig_7series_v4_0_ddr_byte_lane__parameterized6\n (\\my_empty_reg[1] ,\n D,\n ddr_ck_out,\n D_of_full,\n mem_dq_out,\n \\my_empty_reg[7] ,\n init_calib_complete_reg_rep__5,\n mc_cas_n,\n \\cmd_pipe_plus.mc_address_reg[43] ,\n init_calib_complete_reg_rep,\n COUNTERREADVAL,\n A_rst_primitives_reg,\n \\calib_sel_reg[1] ,\n A_rst_primitives_reg_0,\n SR,\n CLK,\n OUTBURSTPENDING,\n D_po_coarse_enable110_out,\n D_po_counter_read_en122_out,\n D_po_fine_enable107_out,\n D_po_fine_inc113_out,\n freq_refclk,\n mem_refclk,\n A_rst_primitives,\n D_po_sel_fine_oclk_delay125_out,\n sync_pulse,\n PCENABLECALIB,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ,\n D4,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ,\n mux_cmd_wren,\n phy_dout,\n init_calib_complete_reg_rep__6);\n output \\my_empty_reg[1] ;\n output [8:0]D;\n output [1:0]ddr_ck_out;\n output D_of_full;\n output [8:0]mem_dq_out;\n output [31:0]\\my_empty_reg[7] ;\n input init_calib_complete_reg_rep__5;\n input [0:0]mc_cas_n;\n input [1:0]\\cmd_pipe_plus.mc_address_reg[43] ;\n input init_calib_complete_reg_rep;\n input [8:0]COUNTERREADVAL;\n input [8:0]A_rst_primitives_reg;\n input [1:0]\\calib_sel_reg[1] ;\n input [8:0]A_rst_primitives_reg_0;\n input [0:0]SR;\n input CLK;\n input [0:0]OUTBURSTPENDING;\n input D_po_coarse_enable110_out;\n input D_po_counter_read_en122_out;\n input D_po_fine_enable107_out;\n input D_po_fine_inc113_out;\n input freq_refclk;\n input mem_refclk;\n input A_rst_primitives;\n input D_po_sel_fine_oclk_delay125_out;\n input sync_pulse;\n input [1:0]PCENABLECALIB;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ;\n input [3:0]D4;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ;\n input mux_cmd_wren;\n input [35:0]phy_dout;\n input init_calib_complete_reg_rep__6;\n\n wire A_rst_primitives;\n wire [8:0]A_rst_primitives_reg;\n wire [8:0]A_rst_primitives_reg_0;\n wire CLK;\n wire [8:0]COUNTERREADVAL;\n wire [8:0]D;\n wire [3:0]D4;\n wire D_of_full;\n wire D_po_coarse_enable110_out;\n wire D_po_counter_read_en122_out;\n wire [8:0]D_po_counter_read_val;\n wire D_po_fine_enable107_out;\n wire D_po_fine_inc113_out;\n wire D_po_sel_fine_oclk_delay125_out;\n wire [0:0]OUTBURSTPENDING;\n wire [1:0]PCENABLECALIB;\n wire [0:0]SR;\n wire [1:0]\\calib_sel_reg[1] ;\n wire [1:0]\\cmd_pipe_plus.mc_address_reg[43] ;\n wire [1:0]ddr_ck_out;\n wire [0:0]ddr_ck_out_q;\n wire freq_refclk;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ;\n wire init_calib_complete_reg_rep;\n wire init_calib_complete_reg_rep__5;\n wire init_calib_complete_reg_rep__6;\n wire [0:0]mc_cas_n;\n wire [8:0]mem_dq_out;\n wire mem_refclk;\n wire mux_cmd_wren;\n wire \\my_empty_reg[1] ;\n wire [31:0]\\my_empty_reg[7] ;\n wire [3:0]of_d9;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_40 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_41 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_42 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_43 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_44 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_45 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_46 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_47 ;\n wire \\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ;\n wire [3:0]of_q0;\n wire [3:0]of_q1;\n wire [3:0]of_q2;\n wire [3:0]of_q3;\n wire [3:0]of_q4;\n wire [7:0]of_q5;\n wire [7:0]of_q6;\n wire [3:0]of_q7;\n wire [3:0]of_q8;\n wire [3:0]of_q9;\n wire oserdes_clk;\n wire oserdes_clk_delayed;\n wire oserdes_clkdiv;\n wire [1:0]oserdes_dq_ts;\n wire [1:0]oserdes_dqs;\n wire [1:0]oserdes_dqs_ts;\n wire out_fifo_n_0;\n wire out_fifo_n_1;\n wire out_fifo_n_2;\n wire phaser_out_n_0;\n wire phaser_out_n_1;\n wire [35:0]phy_dout;\n wire po_oserdes_rst;\n wire po_rd_enable;\n wire sync_pulse;\n wire \\NLW_ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_S_UNCONNECTED ;\n wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;\n\n ddr3_if_mig_7series_v4_0_ddr_byte_group_io__parameterized6 ddr_byte_group_io\n (.mem_dq_out(mem_dq_out),\n .oserdes_clk(oserdes_clk),\n .oserdes_clkdiv(oserdes_clkdiv),\n .oserdes_dq({of_q9,of_q8,of_q7,of_q6[3:0],of_q5[3:0],of_q4,of_q3,of_q2,of_q1}),\n .po_oserdes_rst(po_oserdes_rst));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* __SRVAL = \"FALSE\" *) \n ODDR #(\n .DDR_CLK_EDGE(\"SAME_EDGE\"),\n .INIT(1'b0),\n .IS_C_INVERTED(1'b0),\n .IS_D1_INVERTED(1'b0),\n .IS_D2_INVERTED(1'b0),\n .SRTYPE(\"SYNC\")) \n \\ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck \n (.C(oserdes_clk),\n .CE(1'b1),\n .D1(1'b0),\n .D2(1'b1),\n .Q(ddr_ck_out_q),\n .R(1'b0),\n .S(\\NLW_ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_S_UNCONNECTED ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CAPACITANCE = \"DONT_CARE\" *) \n (* XILINX_LEGACY_PRIM = \"OBUFDS\" *) \n OBUFDS #(\n .IOSTANDARD(\"DEFAULT\")) \n \\ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_obuf \n (.I(ddr_ck_out_q),\n .O(ddr_ck_out[0]),\n .OB(ddr_ck_out[1]));\n ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized9 \\of_pre_fifo_gen.u_ddr_of_pre_fifo \n (.CLK(CLK),\n .D0({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 }),\n .D1({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 }),\n .D2({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 }),\n .D3({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 }),\n .D4({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 }),\n .D5({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 }),\n .D6({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 }),\n .D7({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_40 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_41 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_42 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_43 }),\n .D8({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_44 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_45 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_46 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_47 }),\n .D9({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,of_d9}),\n .SR(SR),\n .\\cmd_pipe_plus.mc_address_reg[43] (\\cmd_pipe_plus.mc_address_reg[43] ),\n .init_calib_complete_reg_rep(init_calib_complete_reg_rep),\n .init_calib_complete_reg_rep__5(init_calib_complete_reg_rep__5),\n .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6),\n .mc_cas_n(mc_cas_n),\n .mux_cmd_wren(mux_cmd_wren),\n .\\my_empty_reg[1]_0 (\\my_empty_reg[1] ),\n .\\my_empty_reg[7]_0 (\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ),\n .\\my_empty_reg[7]_1 (\\my_empty_reg[7] ),\n .ofifo_rst_reg(D_of_full),\n .phy_dout(phy_dout));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n OUT_FIFO #(\n .ALMOST_EMPTY_VALUE(1),\n .ALMOST_FULL_VALUE(1),\n .ARRAY_MODE(\"ARRAY_MODE_4_X_4\"),\n .OUTPUT_DISABLE(\"FALSE\"),\n .SYNCHRONOUS_MODE(\"FALSE\")) \n out_fifo\n (.ALMOSTEMPTY(out_fifo_n_0),\n .ALMOSTFULL(out_fifo_n_1),\n .D0({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1 }),\n .D1({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ,\\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] }),\n .D2({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ,\\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] }),\n .D3({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ,\\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] }),\n .D4({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 ,D4}),\n .D5({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ,\\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] }),\n .D6({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 ,\\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] }),\n .D7({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_40 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_41 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_42 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_43 ,\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] }),\n .D8({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_44 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_45 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_46 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_47 ,\\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] }),\n .D9({\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,of_d9}),\n .EMPTY(out_fifo_n_2),\n .FULL(D_of_full),\n .Q0(of_q0),\n .Q1(of_q1),\n .Q2(of_q2),\n .Q3(of_q3),\n .Q4(of_q4),\n .Q5(of_q5),\n .Q6(of_q6),\n .Q7(of_q7),\n .Q8(of_q8),\n .Q9(of_q9),\n .RDCLK(oserdes_clkdiv),\n .RDEN(po_rd_enable),\n .RESET(SR),\n .WRCLK(CLK),\n .WREN(\\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n PHASER_OUT_PHY #(\n .CLKOUT_DIV(4),\n .COARSE_BYPASS(\"FALSE\"),\n .COARSE_DELAY(0),\n .DATA_CTL_N(\"FALSE\"),\n .DATA_RD_CYCLES(\"FALSE\"),\n .FINE_DELAY(60),\n .IS_RST_INVERTED(1'b0),\n .MEMREFCLK_PERIOD(1.112000),\n .OCLKDELAY_INV(\"TRUE\"),\n .OCLK_DELAY(28),\n .OUTPUT_CLK_SRC(\"DELAYED_REF\"),\n .PHASEREFCLK_PERIOD(1.000000),\n .PO(3'b111),\n .REFCLK_PERIOD(1.112000),\n .SYNC_IN_DIV_RST(\"TRUE\")) \n phaser_out\n (.BURSTPENDINGPHY(OUTBURSTPENDING),\n .COARSEENABLE(D_po_coarse_enable110_out),\n .COARSEINC(D_po_coarse_enable110_out),\n .COARSEOVERFLOW(phaser_out_n_0),\n .COUNTERLOADEN(1'b0),\n .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .COUNTERREADEN(D_po_counter_read_en122_out),\n .COUNTERREADVAL(D_po_counter_read_val),\n .CTSBUS(oserdes_dqs_ts),\n .DQSBUS(oserdes_dqs),\n .DTSBUS(oserdes_dq_ts),\n .ENCALIBPHY(PCENABLECALIB),\n .FINEENABLE(D_po_fine_enable107_out),\n .FINEINC(D_po_fine_inc113_out),\n .FINEOVERFLOW(phaser_out_n_1),\n .FREQREFCLK(freq_refclk),\n .MEMREFCLK(mem_refclk),\n .OCLK(oserdes_clk),\n .OCLKDELAYED(oserdes_clk_delayed),\n .OCLKDIV(oserdes_clkdiv),\n .OSERDESRST(po_oserdes_rst),\n .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),\n .RDENABLE(po_rd_enable),\n .RST(A_rst_primitives),\n .SELFINEOCLKDELAY(D_po_sel_fine_oclk_delay125_out),\n .SYNCIN(sync_pulse),\n .SYSCLK(CLK));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[0]_i_1 \n (.I0(D_po_counter_read_val[0]),\n .I1(COUNTERREADVAL[0]),\n .I2(A_rst_primitives_reg[0]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_0[0]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(D[0]));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[1]_i_1 \n (.I0(D_po_counter_read_val[1]),\n .I1(COUNTERREADVAL[1]),\n .I2(A_rst_primitives_reg[1]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_0[1]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(D[1]));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[2]_i_1 \n (.I0(D_po_counter_read_val[2]),\n .I1(COUNTERREADVAL[2]),\n .I2(A_rst_primitives_reg[2]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_0[2]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(D[2]));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[3]_i_1 \n (.I0(D_po_counter_read_val[3]),\n .I1(COUNTERREADVAL[3]),\n .I2(A_rst_primitives_reg[3]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_0[3]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(D[3]));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[4]_i_1 \n (.I0(D_po_counter_read_val[4]),\n .I1(COUNTERREADVAL[4]),\n .I2(A_rst_primitives_reg[4]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_0[4]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(D[4]));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[5]_i_1 \n (.I0(D_po_counter_read_val[5]),\n .I1(COUNTERREADVAL[5]),\n .I2(A_rst_primitives_reg[5]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_0[5]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(D[5]));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[6]_i_1 \n (.I0(D_po_counter_read_val[6]),\n .I1(COUNTERREADVAL[6]),\n .I2(A_rst_primitives_reg[6]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_0[6]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(D[6]));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[7]_i_1 \n (.I0(D_po_counter_read_val[7]),\n .I1(COUNTERREADVAL[7]),\n .I2(A_rst_primitives_reg[7]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_0[7]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(D[7]));\n LUT6 #(\n .INIT(64'hAACCAACCF0FFF000)) \n \\po_counter_read_val[8]_i_1 \n (.I0(D_po_counter_read_val[8]),\n .I1(COUNTERREADVAL[8]),\n .I2(A_rst_primitives_reg[8]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(A_rst_primitives_reg_0[8]),\n .I5(\\calib_sel_reg[1] [0]),\n .O(D[8]));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_ddr_calib_top\n (idelay_inc,\n phy_dout,\n phy_if_reset,\n \\samps_r_reg[9] ,\n \\my_empty_reg[7] ,\n \\rd_ptr_timing_reg[0] ,\n app_zq_r_reg,\n \\my_empty_reg[7]_0 ,\n init_calib_complete_r_reg,\n \\pi_rst_stg1_cal_r_reg[0] ,\n samp_edge_cnt0_en_r,\n pi_en_stg2_f_timing_reg,\n out,\n dqs_po_en_stg2_f_reg,\n prbs_rdlvl_start_r_reg,\n A,\n fine_delay_sel_r_reg,\n \\rd_ptr_timing_reg[0]_0 ,\n \\my_empty_reg[7]_1 ,\n \\my_empty_reg[7]_2 ,\n \\my_empty_reg[7]_3 ,\n \\my_empty_reg[7]_4 ,\n LD0,\n \\po_rdval_cnt_reg[8] ,\n LD0_0,\n LD0_1,\n LD0_2,\n D_po_counter_read_en122_out,\n D_po_fine_enable107_out,\n D_po_coarse_enable110_out,\n D_po_fine_inc113_out,\n D_po_sel_fine_oclk_delay125_out,\n \\po_counter_read_val_reg[8] ,\n \\po_counter_read_val_reg[8]_0 ,\n \\po_counter_read_val_reg[8]_1 ,\n \\po_counter_read_val_reg[8]_2 ,\n \\po_counter_read_val_reg[8]_3 ,\n \\po_counter_read_val_reg[8]_4 ,\n \\po_counter_read_val_reg[8]_5 ,\n \\po_counter_read_val_reg[8]_6 ,\n \\po_counter_read_val_reg[8]_7 ,\n \\po_counter_read_val_reg[8]_8 ,\n \\po_counter_read_val_reg[8]_9 ,\n \\po_counter_read_val_reg[8]_10 ,\n \\po_counter_read_val_reg[8]_11 ,\n E,\n \\po_counter_read_val_reg[8]_12 ,\n \\po_counter_read_val_reg[8]_13 ,\n \\po_counter_read_val_reg[8]_14 ,\n \\po_counter_read_val_reg[8]_15 ,\n \\pi_dqs_found_lanes_r1_reg[3] ,\n \\fine_delay_r_reg[5] ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,\n \\po_counter_read_val_reg[8]_16 ,\n \\po_counter_read_val_reg[8]_17 ,\n \\po_counter_read_val_reg[8]_18 ,\n ififo_rst_reg,\n \\pi_dqs_found_lanes_r1_reg[3]_0 ,\n \\pi_dqs_found_lanes_r1_reg[3]_1 ,\n \\pi_dqs_found_lanes_r1_reg[3]_2 ,\n \\pi_dqs_found_lanes_r1_reg[2] ,\n \\fine_delay_r_reg[5]_0 ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,\n \\po_counter_read_val_reg[8]_19 ,\n \\po_counter_read_val_reg[8]_20 ,\n \\po_counter_read_val_reg[8]_21 ,\n ififo_rst_reg_0,\n \\pi_dqs_found_lanes_r1_reg[2]_0 ,\n \\pi_dqs_found_lanes_r1_reg[2]_1 ,\n \\pi_dqs_found_lanes_r1_reg[2]_2 ,\n \\pi_dqs_found_lanes_r1_reg[1] ,\n \\fine_delay_r_reg[5]_1 ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,\n \\po_counter_read_val_reg[8]_22 ,\n \\po_counter_read_val_reg[8]_23 ,\n \\po_counter_read_val_reg[8]_24 ,\n ififo_rst_reg_1,\n \\pi_dqs_found_lanes_r1_reg[1]_0 ,\n \\pi_dqs_found_lanes_r1_reg[1]_1 ,\n \\pi_dqs_found_lanes_r1_reg[1]_2 ,\n D,\n COUNTERLOADVAL,\n \\pi_dqs_found_lanes_r1_reg[0] ,\n \\fine_delay_r_reg[2] ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,\n \\po_counter_read_val_reg[8]_25 ,\n \\po_counter_read_val_reg[8]_26 ,\n \\po_counter_read_val_reg[8]_27 ,\n ififo_rst_reg_2,\n \\pi_dqs_found_lanes_r1_reg[0]_0 ,\n \\pi_dqs_found_lanes_r1_reg[0]_1 ,\n \\pi_dqs_found_lanes_r1_reg[0]_2 ,\n \\po_counter_read_val_reg[8]_28 ,\n \\po_counter_read_val_reg[8]_29 ,\n stg3_dec2init_val_r_reg,\n stg3_inc2init_val_r_reg,\n A_1__s_port_,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 ,\n \\A[1]__4 ,\n D2,\n D0,\n D3,\n D5,\n D6,\n D1,\n \\rd_ptr_timing_reg[0]_1 ,\n D7,\n D8,\n \\rd_ptr_timing_reg[0]_2 ,\n \\my_empty_reg[7]_5 ,\n \\my_empty_reg[7]_6 ,\n \\my_empty_reg[7]_7 ,\n D4,\n \\my_empty_reg[7]_8 ,\n \\my_empty_reg[7]_9 ,\n \\my_empty_reg[7]_10 ,\n \\my_empty_reg[7]_11 ,\n \\my_full_reg[3] ,\n \\rd_ptr_timing_reg[0]_3 ,\n D9,\n \\my_empty_reg[7]_12 ,\n \\my_empty_reg[7]_13 ,\n \\my_empty_reg[7]_14 ,\n \\my_empty_reg[7]_15 ,\n \\my_empty_reg[7]_16 ,\n \\my_empty_reg[7]_17 ,\n \\my_empty_reg[7]_18 ,\n \\my_empty_reg[7]_19 ,\n \\my_empty_reg[7]_20 ,\n \\my_empty_reg[7]_21 ,\n \\my_empty_reg[7]_22 ,\n \\my_empty_reg[7]_23 ,\n \\my_empty_reg[7]_24 ,\n \\my_empty_reg[7]_25 ,\n \\my_empty_reg[7]_26 ,\n \\my_empty_reg[7]_27 ,\n \\my_empty_reg[7]_28 ,\n \\my_empty_reg[7]_29 ,\n \\my_empty_reg[7]_30 ,\n \\my_empty_reg[7]_31 ,\n \\my_empty_reg[7]_32 ,\n \\my_empty_reg[7]_33 ,\n \\my_empty_reg[7]_34 ,\n \\my_empty_reg[7]_35 ,\n \\my_empty_reg[7]_36 ,\n \\my_empty_reg[7]_37 ,\n \\my_empty_reg[7]_38 ,\n \\my_empty_reg[7]_39 ,\n \\my_empty_reg[7]_40 ,\n \\my_empty_reg[7]_41 ,\n \\my_empty_reg[7]_42 ,\n \\my_empty_reg[7]_43 ,\n \\byte_r_reg[0] ,\n \\byte_r_reg[1] ,\n \\stg2_tap_cnt_reg[0] ,\n \\sm_r_reg[0] ,\n \\zero2fuzz_r_reg[0] ,\n maint_prescaler_r1,\n \\cmd_pipe_plus.mc_data_offset_reg[3] ,\n \\cmd_pipe_plus.mc_data_offset_reg[5] ,\n \\cmd_pipe_plus.mc_data_offset_reg[4] ,\n \\cmd_pipe_plus.mc_data_offset_reg[2] ,\n \\cmd_pipe_plus.mc_data_offset_reg[1] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[3] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[5] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[4] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[2] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[1] ,\n \\cmd_pipe_plus.mc_data_offset_reg[0] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[0] ,\n \\rdlvl_dqs_tap_cnt_r_reg[0][3][0] ,\n \\idelay_tap_cnt_r_reg[0][3][0] ,\n \\en_cnt_div4.enable_wrlvl_cnt_reg[3] ,\n \\complex_row_cnt_ocal_reg[0] ,\n \\row_cnt_victim_rotate.complex_row_cnt_reg[4] ,\n \\fine_delay_mod_reg[5] ,\n \\fine_delay_mod_reg[20] ,\n \\phy_ctl_wd_i1_reg[24] ,\n phy_write_calib,\n phy_read_calib,\n \\fine_delay_mod_reg[26] ,\n \\genblk9[1].fine_delay_incdec_pb_reg[1] ,\n \\genblk9[2].fine_delay_incdec_pb_reg[2] ,\n \\genblk9[3].fine_delay_incdec_pb_reg[3] ,\n \\genblk9[5].fine_delay_incdec_pb_reg[5] ,\n \\genblk9[6].fine_delay_incdec_pb_reg[6] ,\n \\genblk9[7].fine_delay_incdec_pb_reg[7] ,\n mux_wrdata_en,\n mux_cmd_wren,\n mux_reset_n,\n \\data_offset_1_i1_reg[5] ,\n \\rd_ptr_timing_reg[0]_4 ,\n \\my_full_reg[3]_0 ,\n \\byte_sel_data_map_reg[1] ,\n \\A[0]__4 ,\n \\A[0]__0 ,\n \\A[2]__2 ,\n \\A[1]__0 ,\n \\A[1]__4_0 ,\n \\A[1]__3 ,\n \\A[2]__1 ,\n \\pi_dqs_found_lanes_r1_reg[1]_3 ,\n \\pi_dqs_found_lanes_r1_reg[2]_3 ,\n \\pi_dqs_found_lanes_r1_reg[3]_3 ,\n \\fine_delay_r_reg[26] ,\n \\fine_delay_r_reg[26]_0 ,\n \\fine_delay_r_reg[26]_1 ,\n \\qcntr_r_reg[0] ,\n CLK,\n rstdiv0_sync_r1_reg_rep__20,\n poc_sample_pd,\n rstdiv0_sync_r1_reg_rep__10,\n rstdiv0_sync_r1_reg_rep__9,\n phy_rddata_en,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ,\n \\po_stg2_wrcal_cnt_reg[1] ,\n \\po_stg2_wrcal_cnt_reg[1]_0 ,\n \\po_stg2_wrcal_cnt_reg[1]_1 ,\n \\po_stg2_wrcal_cnt_reg[1]_2 ,\n \\mcGo_r_reg[15] ,\n in0,\n rstdiv0_sync_r1_reg_rep__12,\n rstdiv0_sync_r1_reg_rep__2,\n rstdiv0_sync_r1_reg_rep__24,\n rstdiv0_sync_r1_reg_rep__13,\n rstdiv0_sync_r1_reg_rep__14,\n \\rd_mux_sel_r_reg[1] ,\n \\rd_mux_sel_r_reg[1]_0 ,\n \\rd_mux_sel_r_reg[1]_1 ,\n \\rd_mux_sel_r_reg[1]_2 ,\n \\rd_mux_sel_r_reg[1]_3 ,\n \\rd_mux_sel_r_reg[1]_4 ,\n \\rd_mux_sel_r_reg[1]_5 ,\n \\rd_mux_sel_r_reg[1]_6 ,\n \\rd_mux_sel_r_reg[1]_7 ,\n \\rd_mux_sel_r_reg[1]_8 ,\n \\rd_mux_sel_r_reg[1]_9 ,\n \\rd_mux_sel_r_reg[1]_10 ,\n \\rd_mux_sel_r_reg[1]_11 ,\n \\rd_mux_sel_r_reg[1]_12 ,\n \\rd_mux_sel_r_reg[1]_13 ,\n \\rd_mux_sel_r_reg[1]_14 ,\n \\rd_mux_sel_r_reg[1]_15 ,\n \\rd_mux_sel_r_reg[1]_16 ,\n \\rd_mux_sel_r_reg[1]_17 ,\n \\rd_mux_sel_r_reg[1]_18 ,\n \\rd_mux_sel_r_reg[1]_19 ,\n \\rd_mux_sel_r_reg[1]_20 ,\n \\rd_mux_sel_r_reg[1]_21 ,\n \\rd_mux_sel_r_reg[1]_22 ,\n \\rd_mux_sel_r_reg[1]_23 ,\n \\rd_mux_sel_r_reg[1]_24 ,\n \\rd_mux_sel_r_reg[1]_25 ,\n \\rd_mux_sel_r_reg[1]_26 ,\n \\rd_mux_sel_r_reg[1]_27 ,\n \\rd_mux_sel_r_reg[1]_28 ,\n \\rd_mux_sel_r_reg[1]_29 ,\n \\rd_mux_sel_r_reg[1]_30 ,\n \\rd_mux_sel_r_reg[1]_31 ,\n \\rd_mux_sel_r_reg[1]_32 ,\n \\rd_mux_sel_r_reg[1]_33 ,\n \\rd_mux_sel_r_reg[1]_34 ,\n \\rd_mux_sel_r_reg[1]_35 ,\n \\rd_mux_sel_r_reg[1]_36 ,\n \\rd_mux_sel_r_reg[1]_37 ,\n \\rd_mux_sel_r_reg[1]_38 ,\n \\rd_mux_sel_r_reg[1]_39 ,\n \\rd_mux_sel_r_reg[1]_40 ,\n \\rd_mux_sel_r_reg[1]_41 ,\n \\rd_mux_sel_r_reg[1]_42 ,\n \\rd_mux_sel_r_reg[1]_43 ,\n \\rd_mux_sel_r_reg[1]_44 ,\n \\rd_mux_sel_r_reg[1]_45 ,\n \\rd_mux_sel_r_reg[1]_46 ,\n \\rd_mux_sel_r_reg[1]_47 ,\n \\rd_mux_sel_r_reg[1]_48 ,\n \\rd_mux_sel_r_reg[1]_49 ,\n \\rd_mux_sel_r_reg[1]_50 ,\n \\rd_mux_sel_r_reg[1]_51 ,\n \\rd_mux_sel_r_reg[1]_52 ,\n \\rd_mux_sel_r_reg[1]_53 ,\n \\rd_mux_sel_r_reg[1]_54 ,\n \\rd_mux_sel_r_reg[1]_55 ,\n \\rd_mux_sel_r_reg[1]_56 ,\n \\rd_mux_sel_r_reg[1]_57 ,\n \\rd_mux_sel_r_reg[1]_58 ,\n \\rd_mux_sel_r_reg[1]_59 ,\n \\rd_mux_sel_r_reg[1]_60 ,\n \\rd_mux_sel_r_reg[1]_61 ,\n \\rd_mux_sel_r_reg[1]_62 ,\n rstdiv0_sync_r1_reg_rep__23,\n SR,\n A_rst_primitives_reg,\n rstdiv0_sync_r1_reg_rep__11,\n cnt_pwron_reset_done_r0,\n rstdiv0_sync_r1_reg_rep__18,\n rstdiv0_sync_r1_reg_rep__16,\n SS,\n tempmon_sample_en,\n rstdiv0_sync_r1_reg_rep__7,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ,\n \\A[1]_0 ,\n \\A[1]_1 ,\n \\A[1]_2 ,\n \\A[1]_3 ,\n \\A[1]_4 ,\n \\A[1]_5 ,\n \\A[1]_6 ,\n \\A[1]_7 ,\n \\A[1]_8 ,\n \\A[1]_9 ,\n \\A[1]_10 ,\n \\A[1]_11 ,\n \\A[1]_12 ,\n \\A[1]_13 ,\n \\A[1]_14 ,\n \\A[1]_15 ,\n \\A[1]_16 ,\n \\A[1]_17 ,\n \\A[1]_18 ,\n \\A[1]_19 ,\n \\A[1]_20 ,\n \\A[1]_21 ,\n \\A[1]_22 ,\n \\A[1]_23 ,\n \\A[1]_24 ,\n \\A[1]_25 ,\n \\A[1]_26 ,\n \\A[1]_27 ,\n \\A[1]_28 ,\n \\A[1]_29 ,\n \\A[1]_30 ,\n \\A[1]_31 ,\n \\A[1]_32 ,\n \\A[1]_33 ,\n \\A[1]_34 ,\n \\A[1]_35 ,\n \\A[1]_36 ,\n \\A[1]_37 ,\n \\A[1]_38 ,\n \\A[1]_39 ,\n \\A[1]_40 ,\n \\A[1]_41 ,\n \\A[1]_42 ,\n \\A[1]_43 ,\n \\A[1]_44 ,\n \\A[1]_45 ,\n \\A[1]_46 ,\n \\A[1]_47 ,\n \\A[1]_48 ,\n \\A[1]_49 ,\n \\A[1]_50 ,\n \\A[1]_51 ,\n \\A[1]_52 ,\n \\A[1]_53 ,\n \\A[1]_54 ,\n \\A[1]_55 ,\n \\A[1]_56 ,\n \\A[1]_57 ,\n \\A[1]_58 ,\n \\A[1]_59 ,\n \\A[1]_60 ,\n \\A[1]_61 ,\n \\A[1]_62 ,\n \\A[1]_63 ,\n rstdiv0_sync_r1_reg_rep__8,\n rstdiv0_sync_r1_reg_rep,\n p_0_out,\n \\po_stg2_wrcal_cnt_reg[1]_3 ,\n \\po_stg2_wrcal_cnt_reg[1]_4 ,\n \\po_stg2_wrcal_cnt_reg[1]_5 ,\n \\po_stg2_wrcal_cnt_reg[1]_6 ,\n \\po_stg2_wrcal_cnt_reg[1]_7 ,\n \\po_stg2_wrcal_cnt_reg[1]_8 ,\n \\po_stg2_wrcal_cnt_reg[1]_9 ,\n \\po_stg2_wrcal_cnt_reg[1]_10 ,\n \\po_stg2_wrcal_cnt_reg[1]_11 ,\n \\po_stg2_wrcal_cnt_reg[1]_12 ,\n \\po_stg2_wrcal_cnt_reg[1]_13 ,\n \\po_stg2_wrcal_cnt_reg[1]_14 ,\n \\po_stg2_wrcal_cnt_reg[1]_15 ,\n \\po_stg2_wrcal_cnt_reg[1]_16 ,\n \\po_stg2_wrcal_cnt_reg[1]_17 ,\n \\po_stg2_wrcal_cnt_reg[1]_18 ,\n \\po_stg2_wrcal_cnt_reg[1]_19 ,\n \\po_stg2_wrcal_cnt_reg[1]_20 ,\n \\po_stg2_wrcal_cnt_reg[1]_21 ,\n \\po_stg2_wrcal_cnt_reg[1]_22 ,\n \\po_stg2_wrcal_cnt_reg[1]_23 ,\n \\po_stg2_wrcal_cnt_reg[1]_24 ,\n \\po_stg2_wrcal_cnt_reg[1]_25 ,\n \\po_stg2_wrcal_cnt_reg[1]_26 ,\n \\po_stg2_wrcal_cnt_reg[1]_27 ,\n \\po_stg2_wrcal_cnt_reg[1]_28 ,\n \\po_stg2_wrcal_cnt_reg[1]_29 ,\n \\po_stg2_wrcal_cnt_reg[1]_30 ,\n \\po_stg2_wrcal_cnt_reg[1]_31 ,\n \\po_stg2_wrcal_cnt_reg[1]_32 ,\n \\po_stg2_wrcal_cnt_reg[1]_33 ,\n \\po_stg2_wrcal_cnt_reg[1]_34 ,\n \\po_stg2_wrcal_cnt_reg[1]_35 ,\n \\po_stg2_wrcal_cnt_reg[1]_36 ,\n \\po_stg2_wrcal_cnt_reg[1]_37 ,\n \\po_stg2_wrcal_cnt_reg[1]_38 ,\n \\po_stg2_wrcal_cnt_reg[1]_39 ,\n \\po_stg2_wrcal_cnt_reg[1]_40 ,\n \\po_stg2_wrcal_cnt_reg[1]_41 ,\n \\po_stg2_wrcal_cnt_reg[1]_42 ,\n \\po_stg2_wrcal_cnt_reg[1]_43 ,\n \\po_stg2_wrcal_cnt_reg[1]_44 ,\n \\po_stg2_wrcal_cnt_reg[1]_45 ,\n \\po_stg2_wrcal_cnt_reg[1]_46 ,\n \\po_stg2_wrcal_cnt_reg[1]_47 ,\n \\po_stg2_wrcal_cnt_reg[1]_48 ,\n \\po_stg2_wrcal_cnt_reg[1]_49 ,\n \\po_stg2_wrcal_cnt_reg[1]_50 ,\n \\po_stg2_wrcal_cnt_reg[1]_51 ,\n \\po_stg2_wrcal_cnt_reg[1]_52 ,\n \\po_stg2_wrcal_cnt_reg[1]_53 ,\n \\po_stg2_wrcal_cnt_reg[1]_54 ,\n \\po_stg2_wrcal_cnt_reg[1]_55 ,\n \\po_stg2_wrcal_cnt_reg[1]_56 ,\n \\po_stg2_wrcal_cnt_reg[1]_57 ,\n \\po_stg2_wrcal_cnt_reg[1]_58 ,\n \\po_stg2_wrcal_cnt_reg[1]_59 ,\n \\po_stg2_wrcal_cnt_reg[1]_60 ,\n \\po_stg2_wrcal_cnt_reg[1]_61 ,\n rstdiv0_sync_r1_reg_rep__4,\n rstdiv0_sync_r1_reg_rep__6,\n rstdiv0_sync_r1_reg_rep__5,\n Q,\n idelay_ld_rst,\n idelay_ld_rst_3,\n idelay_ld_rst_4,\n idelay_ld_rst_5,\n rstdiv0_sync_r1_reg_rep__26,\n rstdiv0_sync_r1_reg_rep__26_0,\n rstdiv0_sync_r1_reg_rep__25,\n \\sm_r_reg[0]_0 ,\n fine_delay_sel_r,\n fine_delay_mod,\n mc_cas_n,\n \\rd_ptr_reg[3] ,\n \\my_empty_reg[1] ,\n mem_out,\n \\my_empty_reg[1]_0 ,\n mc_ras_n,\n mc_odt,\n \\rd_ptr_reg[3]_0 ,\n \\my_empty_reg[1]_1 ,\n mc_cke,\n mc_we_n,\n \\cmd_pipe_plus.mc_address_reg[44] ,\n \\rd_ptr_reg[3]_1 ,\n \\my_empty_reg[1]_2 ,\n \\cmd_pipe_plus.mc_bank_reg[8] ,\n \\rd_ptr_reg[3]_2 ,\n \\my_empty_reg[1]_3 ,\n \\rd_ptr_reg[3]_3 ,\n \\my_empty_reg[1]_4 ,\n \\rd_ptr_reg[3]_4 ,\n \\my_empty_reg[1]_5 ,\n \\rd_ptr_reg[3]_5 ,\n \\my_empty_reg[1]_6 ,\n mc_cs_n,\n \\pi_counter_read_val_reg[5] ,\n \\po_counter_read_val_reg[2] ,\n rstdiv0_sync_r1_reg_rep__26_1,\n rstdiv0_sync_r1_reg_rep__26_2,\n \\mmcm_init_trail_reg[0] ,\n \\mmcm_current_reg[0] ,\n sent_col,\n \\po_counter_read_val_reg[8]_30 ,\n \\po_counter_read_val_reg[8]_31 ,\n \\po_counter_read_val_reg[5] ,\n \\A[2]__2_0 ,\n psdone,\n rstdiv0_sync_r1_reg_rep__0,\n rstdiv0_sync_r1_reg_rep__19,\n \\byte_r_reg[0]_0 ,\n fine_adjust_reg,\n samp_edge_cnt0_en_r_reg,\n pi_cnt_dec_reg,\n rstdiv0_sync_r1_reg_rep__24_0,\n p_81_in,\n rstdiv0_sync_r1_reg_rep__24_1,\n rstdiv0_sync_r1_reg_rep__17,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ,\n my_empty,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ,\n my_empty_6,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ,\n my_empty_7,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ,\n my_empty_8,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ,\n po_cnt_dec_reg,\n \\device_temp_r_reg[11] ,\n mc_wrdata_en,\n \\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[2]_0 ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[3]_0 ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ,\n mc_cmd,\n \\cmd_pipe_plus.mc_data_offset_reg[0]_0 ,\n \\cmd_pipe_plus.mc_data_offset_reg[1]_0 ,\n \\cmd_pipe_plus.mc_data_offset_reg[2]_0 ,\n \\cmd_pipe_plus.mc_data_offset_reg[3]_0 ,\n \\cmd_pipe_plus.mc_data_offset_reg[4]_0 ,\n \\cmd_pipe_plus.mc_data_offset_reg[5]_0 ,\n \\stg3_r_reg[0] ,\n pd_out);\n output idelay_inc;\n output [33:0]phy_dout;\n output phy_if_reset;\n output \\samps_r_reg[9] ;\n output \\my_empty_reg[7] ;\n output \\rd_ptr_timing_reg[0] ;\n output app_zq_r_reg;\n output \\my_empty_reg[7]_0 ;\n output init_calib_complete_r_reg;\n output \\pi_rst_stg1_cal_r_reg[0] ;\n output samp_edge_cnt0_en_r;\n output pi_en_stg2_f_timing_reg;\n output out;\n output dqs_po_en_stg2_f_reg;\n output prbs_rdlvl_start_r_reg;\n output [1:0]A;\n output fine_delay_sel_r_reg;\n output [33:0]\\rd_ptr_timing_reg[0]_0 ;\n output [71:0]\\my_empty_reg[7]_1 ;\n output [71:0]\\my_empty_reg[7]_2 ;\n output [71:0]\\my_empty_reg[7]_3 ;\n output [71:0]\\my_empty_reg[7]_4 ;\n output LD0;\n output [2:0]\\po_rdval_cnt_reg[8] ;\n output LD0_0;\n output LD0_1;\n output LD0_2;\n output D_po_counter_read_en122_out;\n output D_po_fine_enable107_out;\n output D_po_coarse_enable110_out;\n output D_po_fine_inc113_out;\n output D_po_sel_fine_oclk_delay125_out;\n output \\po_counter_read_val_reg[8] ;\n output \\po_counter_read_val_reg[8]_0 ;\n output \\po_counter_read_val_reg[8]_1 ;\n output \\po_counter_read_val_reg[8]_2 ;\n output \\po_counter_read_val_reg[8]_3 ;\n output \\po_counter_read_val_reg[8]_4 ;\n output \\po_counter_read_val_reg[8]_5 ;\n output \\po_counter_read_val_reg[8]_6 ;\n output \\po_counter_read_val_reg[8]_7 ;\n output \\po_counter_read_val_reg[8]_8 ;\n output \\po_counter_read_val_reg[8]_9 ;\n output \\po_counter_read_val_reg[8]_10 ;\n output \\po_counter_read_val_reg[8]_11 ;\n output [0:0]E;\n output \\po_counter_read_val_reg[8]_12 ;\n output \\po_counter_read_val_reg[8]_13 ;\n output \\po_counter_read_val_reg[8]_14 ;\n output \\po_counter_read_val_reg[8]_15 ;\n output \\pi_dqs_found_lanes_r1_reg[3] ;\n output [0:0]\\fine_delay_r_reg[5] ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n output \\po_counter_read_val_reg[8]_16 ;\n output \\po_counter_read_val_reg[8]_17 ;\n output \\po_counter_read_val_reg[8]_18 ;\n output ififo_rst_reg;\n output \\pi_dqs_found_lanes_r1_reg[3]_0 ;\n output \\pi_dqs_found_lanes_r1_reg[3]_1 ;\n output \\pi_dqs_found_lanes_r1_reg[3]_2 ;\n output \\pi_dqs_found_lanes_r1_reg[2] ;\n output [0:0]\\fine_delay_r_reg[5]_0 ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n output \\po_counter_read_val_reg[8]_19 ;\n output \\po_counter_read_val_reg[8]_20 ;\n output \\po_counter_read_val_reg[8]_21 ;\n output ififo_rst_reg_0;\n output \\pi_dqs_found_lanes_r1_reg[2]_0 ;\n output \\pi_dqs_found_lanes_r1_reg[2]_1 ;\n output \\pi_dqs_found_lanes_r1_reg[2]_2 ;\n output \\pi_dqs_found_lanes_r1_reg[1] ;\n output [0:0]\\fine_delay_r_reg[5]_1 ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;\n output \\po_counter_read_val_reg[8]_22 ;\n output \\po_counter_read_val_reg[8]_23 ;\n output \\po_counter_read_val_reg[8]_24 ;\n output ififo_rst_reg_1;\n output \\pi_dqs_found_lanes_r1_reg[1]_0 ;\n output \\pi_dqs_found_lanes_r1_reg[1]_1 ;\n output \\pi_dqs_found_lanes_r1_reg[1]_2 ;\n output [7:0]D;\n output [5:0]COUNTERLOADVAL;\n output \\pi_dqs_found_lanes_r1_reg[0] ;\n output [0:0]\\fine_delay_r_reg[2] ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;\n output \\po_counter_read_val_reg[8]_25 ;\n output \\po_counter_read_val_reg[8]_26 ;\n output \\po_counter_read_val_reg[8]_27 ;\n output ififo_rst_reg_2;\n output \\pi_dqs_found_lanes_r1_reg[0]_0 ;\n output \\pi_dqs_found_lanes_r1_reg[0]_1 ;\n output \\pi_dqs_found_lanes_r1_reg[0]_2 ;\n output \\po_counter_read_val_reg[8]_28 ;\n output \\po_counter_read_val_reg[8]_29 ;\n output stg3_dec2init_val_r_reg;\n output stg3_inc2init_val_r_reg;\n output A_1__s_port_;\n output [1:0]\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 ;\n output \\A[1]__4 ;\n output [2:0]D2;\n output [2:0]D0;\n output [2:0]D3;\n output [3:0]D5;\n output [3:0]D6;\n output [2:0]D1;\n output [7:0]\\rd_ptr_timing_reg[0]_1 ;\n output [3:0]D7;\n output [3:0]D8;\n output [7:0]\\rd_ptr_timing_reg[0]_2 ;\n output [3:0]\\my_empty_reg[7]_5 ;\n output [3:0]\\my_empty_reg[7]_6 ;\n output [3:0]\\my_empty_reg[7]_7 ;\n output [3:0]D4;\n output [3:0]\\my_empty_reg[7]_8 ;\n output [3:0]\\my_empty_reg[7]_9 ;\n output [3:0]\\my_empty_reg[7]_10 ;\n output [3:0]\\my_empty_reg[7]_11 ;\n output [3:0]\\my_full_reg[3] ;\n output [3:0]\\rd_ptr_timing_reg[0]_3 ;\n output [3:0]D9;\n output [7:0]\\my_empty_reg[7]_12 ;\n output [7:0]\\my_empty_reg[7]_13 ;\n output [7:0]\\my_empty_reg[7]_14 ;\n output [7:0]\\my_empty_reg[7]_15 ;\n output [7:0]\\my_empty_reg[7]_16 ;\n output [7:0]\\my_empty_reg[7]_17 ;\n output [7:0]\\my_empty_reg[7]_18 ;\n output [7:0]\\my_empty_reg[7]_19 ;\n output [7:0]\\my_empty_reg[7]_20 ;\n output [7:0]\\my_empty_reg[7]_21 ;\n output [7:0]\\my_empty_reg[7]_22 ;\n output [7:0]\\my_empty_reg[7]_23 ;\n output [7:0]\\my_empty_reg[7]_24 ;\n output [7:0]\\my_empty_reg[7]_25 ;\n output [7:0]\\my_empty_reg[7]_26 ;\n output [7:0]\\my_empty_reg[7]_27 ;\n output [7:0]\\my_empty_reg[7]_28 ;\n output [7:0]\\my_empty_reg[7]_29 ;\n output [7:0]\\my_empty_reg[7]_30 ;\n output [7:0]\\my_empty_reg[7]_31 ;\n output [7:0]\\my_empty_reg[7]_32 ;\n output [7:0]\\my_empty_reg[7]_33 ;\n output [7:0]\\my_empty_reg[7]_34 ;\n output [7:0]\\my_empty_reg[7]_35 ;\n output [7:0]\\my_empty_reg[7]_36 ;\n output [7:0]\\my_empty_reg[7]_37 ;\n output [7:0]\\my_empty_reg[7]_38 ;\n output [7:0]\\my_empty_reg[7]_39 ;\n output [7:0]\\my_empty_reg[7]_40 ;\n output [7:0]\\my_empty_reg[7]_41 ;\n output [7:0]\\my_empty_reg[7]_42 ;\n output [7:0]\\my_empty_reg[7]_43 ;\n output \\byte_r_reg[0] ;\n output \\byte_r_reg[1] ;\n output \\stg2_tap_cnt_reg[0] ;\n output \\sm_r_reg[0] ;\n output [0:0]\\zero2fuzz_r_reg[0] ;\n output maint_prescaler_r1;\n output \\cmd_pipe_plus.mc_data_offset_reg[3] ;\n output [5:0]\\cmd_pipe_plus.mc_data_offset_reg[5] ;\n output \\cmd_pipe_plus.mc_data_offset_reg[4] ;\n output \\cmd_pipe_plus.mc_data_offset_reg[2] ;\n output \\cmd_pipe_plus.mc_data_offset_reg[1] ;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[3] ;\n output [5:0]\\cmd_pipe_plus.mc_data_offset_1_reg[5] ;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[4] ;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[2] ;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[1] ;\n output \\cmd_pipe_plus.mc_data_offset_reg[0] ;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[0] ;\n output [1:0]\\rdlvl_dqs_tap_cnt_r_reg[0][3][0] ;\n output [1:0]\\idelay_tap_cnt_r_reg[0][3][0] ;\n output \\en_cnt_div4.enable_wrlvl_cnt_reg[3] ;\n output \\complex_row_cnt_ocal_reg[0] ;\n output \\row_cnt_victim_rotate.complex_row_cnt_reg[4] ;\n output \\fine_delay_mod_reg[5] ;\n output \\fine_delay_mod_reg[20] ;\n output [10:0]\\phy_ctl_wd_i1_reg[24] ;\n output phy_write_calib;\n output phy_read_calib;\n output \\fine_delay_mod_reg[26] ;\n output \\genblk9[1].fine_delay_incdec_pb_reg[1] ;\n output \\genblk9[2].fine_delay_incdec_pb_reg[2] ;\n output \\genblk9[3].fine_delay_incdec_pb_reg[3] ;\n output \\genblk9[5].fine_delay_incdec_pb_reg[5] ;\n output \\genblk9[6].fine_delay_incdec_pb_reg[6] ;\n output \\genblk9[7].fine_delay_incdec_pb_reg[7] ;\n output mux_wrdata_en;\n output mux_cmd_wren;\n output mux_reset_n;\n output [5:0]\\data_offset_1_i1_reg[5] ;\n output [1:0]\\rd_ptr_timing_reg[0]_4 ;\n output [1:0]\\my_full_reg[3]_0 ;\n output \\byte_sel_data_map_reg[1] ;\n output \\A[0]__4 ;\n output \\A[0]__0 ;\n output \\A[2]__2 ;\n output \\A[1]__0 ;\n output \\A[1]__4_0 ;\n output \\A[1]__3 ;\n output \\A[2]__1 ;\n output [5:0]\\pi_dqs_found_lanes_r1_reg[1]_3 ;\n output [5:0]\\pi_dqs_found_lanes_r1_reg[2]_3 ;\n output [5:0]\\pi_dqs_found_lanes_r1_reg[3]_3 ;\n output [7:0]\\fine_delay_r_reg[26] ;\n output [7:0]\\fine_delay_r_reg[26]_0 ;\n output [7:0]\\fine_delay_r_reg[26]_1 ;\n output [0:0]\\qcntr_r_reg[0] ;\n input CLK;\n input rstdiv0_sync_r1_reg_rep__20;\n input poc_sample_pd;\n input rstdiv0_sync_r1_reg_rep__10;\n input rstdiv0_sync_r1_reg_rep__9;\n input phy_rddata_en;\n input \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;\n input \\po_stg2_wrcal_cnt_reg[1] ;\n input \\po_stg2_wrcal_cnt_reg[1]_0 ;\n input \\po_stg2_wrcal_cnt_reg[1]_1 ;\n input \\po_stg2_wrcal_cnt_reg[1]_2 ;\n input \\mcGo_r_reg[15] ;\n input [3:0]in0;\n input rstdiv0_sync_r1_reg_rep__12;\n input rstdiv0_sync_r1_reg_rep__2;\n input rstdiv0_sync_r1_reg_rep__24;\n input rstdiv0_sync_r1_reg_rep__13;\n input [1:0]rstdiv0_sync_r1_reg_rep__14;\n input \\rd_mux_sel_r_reg[1] ;\n input \\rd_mux_sel_r_reg[1]_0 ;\n input \\rd_mux_sel_r_reg[1]_1 ;\n input \\rd_mux_sel_r_reg[1]_2 ;\n input \\rd_mux_sel_r_reg[1]_3 ;\n input \\rd_mux_sel_r_reg[1]_4 ;\n input \\rd_mux_sel_r_reg[1]_5 ;\n input \\rd_mux_sel_r_reg[1]_6 ;\n input \\rd_mux_sel_r_reg[1]_7 ;\n input \\rd_mux_sel_r_reg[1]_8 ;\n input \\rd_mux_sel_r_reg[1]_9 ;\n input \\rd_mux_sel_r_reg[1]_10 ;\n input \\rd_mux_sel_r_reg[1]_11 ;\n input \\rd_mux_sel_r_reg[1]_12 ;\n input \\rd_mux_sel_r_reg[1]_13 ;\n input \\rd_mux_sel_r_reg[1]_14 ;\n input \\rd_mux_sel_r_reg[1]_15 ;\n input \\rd_mux_sel_r_reg[1]_16 ;\n input \\rd_mux_sel_r_reg[1]_17 ;\n input \\rd_mux_sel_r_reg[1]_18 ;\n input \\rd_mux_sel_r_reg[1]_19 ;\n input \\rd_mux_sel_r_reg[1]_20 ;\n input \\rd_mux_sel_r_reg[1]_21 ;\n input \\rd_mux_sel_r_reg[1]_22 ;\n input \\rd_mux_sel_r_reg[1]_23 ;\n input \\rd_mux_sel_r_reg[1]_24 ;\n input \\rd_mux_sel_r_reg[1]_25 ;\n input \\rd_mux_sel_r_reg[1]_26 ;\n input \\rd_mux_sel_r_reg[1]_27 ;\n input \\rd_mux_sel_r_reg[1]_28 ;\n input \\rd_mux_sel_r_reg[1]_29 ;\n input \\rd_mux_sel_r_reg[1]_30 ;\n input \\rd_mux_sel_r_reg[1]_31 ;\n input \\rd_mux_sel_r_reg[1]_32 ;\n input \\rd_mux_sel_r_reg[1]_33 ;\n input \\rd_mux_sel_r_reg[1]_34 ;\n input \\rd_mux_sel_r_reg[1]_35 ;\n input \\rd_mux_sel_r_reg[1]_36 ;\n input \\rd_mux_sel_r_reg[1]_37 ;\n input \\rd_mux_sel_r_reg[1]_38 ;\n input \\rd_mux_sel_r_reg[1]_39 ;\n input \\rd_mux_sel_r_reg[1]_40 ;\n input \\rd_mux_sel_r_reg[1]_41 ;\n input \\rd_mux_sel_r_reg[1]_42 ;\n input \\rd_mux_sel_r_reg[1]_43 ;\n input \\rd_mux_sel_r_reg[1]_44 ;\n input \\rd_mux_sel_r_reg[1]_45 ;\n input \\rd_mux_sel_r_reg[1]_46 ;\n input \\rd_mux_sel_r_reg[1]_47 ;\n input \\rd_mux_sel_r_reg[1]_48 ;\n input \\rd_mux_sel_r_reg[1]_49 ;\n input \\rd_mux_sel_r_reg[1]_50 ;\n input \\rd_mux_sel_r_reg[1]_51 ;\n input \\rd_mux_sel_r_reg[1]_52 ;\n input \\rd_mux_sel_r_reg[1]_53 ;\n input \\rd_mux_sel_r_reg[1]_54 ;\n input \\rd_mux_sel_r_reg[1]_55 ;\n input \\rd_mux_sel_r_reg[1]_56 ;\n input \\rd_mux_sel_r_reg[1]_57 ;\n input \\rd_mux_sel_r_reg[1]_58 ;\n input \\rd_mux_sel_r_reg[1]_59 ;\n input \\rd_mux_sel_r_reg[1]_60 ;\n input \\rd_mux_sel_r_reg[1]_61 ;\n input \\rd_mux_sel_r_reg[1]_62 ;\n input rstdiv0_sync_r1_reg_rep__23;\n input [0:0]SR;\n input A_rst_primitives_reg;\n input [0:0]rstdiv0_sync_r1_reg_rep__11;\n input cnt_pwron_reset_done_r0;\n input [0:0]rstdiv0_sync_r1_reg_rep__18;\n input [0:0]rstdiv0_sync_r1_reg_rep__16;\n input [0:0]SS;\n input tempmon_sample_en;\n input rstdiv0_sync_r1_reg_rep__7;\n input \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ;\n input \\A[1]_0 ;\n input \\A[1]_1 ;\n input \\A[1]_2 ;\n input \\A[1]_3 ;\n input \\A[1]_4 ;\n input \\A[1]_5 ;\n input \\A[1]_6 ;\n input \\A[1]_7 ;\n input \\A[1]_8 ;\n input \\A[1]_9 ;\n input \\A[1]_10 ;\n input \\A[1]_11 ;\n input \\A[1]_12 ;\n input \\A[1]_13 ;\n input \\A[1]_14 ;\n input \\A[1]_15 ;\n input \\A[1]_16 ;\n input \\A[1]_17 ;\n input \\A[1]_18 ;\n input \\A[1]_19 ;\n input \\A[1]_20 ;\n input \\A[1]_21 ;\n input \\A[1]_22 ;\n input \\A[1]_23 ;\n input \\A[1]_24 ;\n input \\A[1]_25 ;\n input \\A[1]_26 ;\n input \\A[1]_27 ;\n input \\A[1]_28 ;\n input \\A[1]_29 ;\n input \\A[1]_30 ;\n input \\A[1]_31 ;\n input \\A[1]_32 ;\n input \\A[1]_33 ;\n input \\A[1]_34 ;\n input \\A[1]_35 ;\n input \\A[1]_36 ;\n input \\A[1]_37 ;\n input \\A[1]_38 ;\n input \\A[1]_39 ;\n input \\A[1]_40 ;\n input \\A[1]_41 ;\n input \\A[1]_42 ;\n input \\A[1]_43 ;\n input \\A[1]_44 ;\n input \\A[1]_45 ;\n input \\A[1]_46 ;\n input \\A[1]_47 ;\n input \\A[1]_48 ;\n input \\A[1]_49 ;\n input \\A[1]_50 ;\n input \\A[1]_51 ;\n input \\A[1]_52 ;\n input \\A[1]_53 ;\n input \\A[1]_54 ;\n input \\A[1]_55 ;\n input \\A[1]_56 ;\n input \\A[1]_57 ;\n input \\A[1]_58 ;\n input \\A[1]_59 ;\n input \\A[1]_60 ;\n input \\A[1]_61 ;\n input \\A[1]_62 ;\n input \\A[1]_63 ;\n input rstdiv0_sync_r1_reg_rep__8;\n input rstdiv0_sync_r1_reg_rep;\n input p_0_out;\n input \\po_stg2_wrcal_cnt_reg[1]_3 ;\n input \\po_stg2_wrcal_cnt_reg[1]_4 ;\n input \\po_stg2_wrcal_cnt_reg[1]_5 ;\n input \\po_stg2_wrcal_cnt_reg[1]_6 ;\n input \\po_stg2_wrcal_cnt_reg[1]_7 ;\n input \\po_stg2_wrcal_cnt_reg[1]_8 ;\n input \\po_stg2_wrcal_cnt_reg[1]_9 ;\n input \\po_stg2_wrcal_cnt_reg[1]_10 ;\n input \\po_stg2_wrcal_cnt_reg[1]_11 ;\n input \\po_stg2_wrcal_cnt_reg[1]_12 ;\n input \\po_stg2_wrcal_cnt_reg[1]_13 ;\n input \\po_stg2_wrcal_cnt_reg[1]_14 ;\n input \\po_stg2_wrcal_cnt_reg[1]_15 ;\n input \\po_stg2_wrcal_cnt_reg[1]_16 ;\n input \\po_stg2_wrcal_cnt_reg[1]_17 ;\n input \\po_stg2_wrcal_cnt_reg[1]_18 ;\n input \\po_stg2_wrcal_cnt_reg[1]_19 ;\n input \\po_stg2_wrcal_cnt_reg[1]_20 ;\n input \\po_stg2_wrcal_cnt_reg[1]_21 ;\n input \\po_stg2_wrcal_cnt_reg[1]_22 ;\n input \\po_stg2_wrcal_cnt_reg[1]_23 ;\n input \\po_stg2_wrcal_cnt_reg[1]_24 ;\n input \\po_stg2_wrcal_cnt_reg[1]_25 ;\n input \\po_stg2_wrcal_cnt_reg[1]_26 ;\n input \\po_stg2_wrcal_cnt_reg[1]_27 ;\n input \\po_stg2_wrcal_cnt_reg[1]_28 ;\n input \\po_stg2_wrcal_cnt_reg[1]_29 ;\n input \\po_stg2_wrcal_cnt_reg[1]_30 ;\n input \\po_stg2_wrcal_cnt_reg[1]_31 ;\n input \\po_stg2_wrcal_cnt_reg[1]_32 ;\n input \\po_stg2_wrcal_cnt_reg[1]_33 ;\n input \\po_stg2_wrcal_cnt_reg[1]_34 ;\n input \\po_stg2_wrcal_cnt_reg[1]_35 ;\n input \\po_stg2_wrcal_cnt_reg[1]_36 ;\n input \\po_stg2_wrcal_cnt_reg[1]_37 ;\n input \\po_stg2_wrcal_cnt_reg[1]_38 ;\n input \\po_stg2_wrcal_cnt_reg[1]_39 ;\n input \\po_stg2_wrcal_cnt_reg[1]_40 ;\n input \\po_stg2_wrcal_cnt_reg[1]_41 ;\n input \\po_stg2_wrcal_cnt_reg[1]_42 ;\n input \\po_stg2_wrcal_cnt_reg[1]_43 ;\n input \\po_stg2_wrcal_cnt_reg[1]_44 ;\n input \\po_stg2_wrcal_cnt_reg[1]_45 ;\n input \\po_stg2_wrcal_cnt_reg[1]_46 ;\n input \\po_stg2_wrcal_cnt_reg[1]_47 ;\n input \\po_stg2_wrcal_cnt_reg[1]_48 ;\n input \\po_stg2_wrcal_cnt_reg[1]_49 ;\n input \\po_stg2_wrcal_cnt_reg[1]_50 ;\n input \\po_stg2_wrcal_cnt_reg[1]_51 ;\n input \\po_stg2_wrcal_cnt_reg[1]_52 ;\n input \\po_stg2_wrcal_cnt_reg[1]_53 ;\n input \\po_stg2_wrcal_cnt_reg[1]_54 ;\n input \\po_stg2_wrcal_cnt_reg[1]_55 ;\n input \\po_stg2_wrcal_cnt_reg[1]_56 ;\n input \\po_stg2_wrcal_cnt_reg[1]_57 ;\n input \\po_stg2_wrcal_cnt_reg[1]_58 ;\n input \\po_stg2_wrcal_cnt_reg[1]_59 ;\n input \\po_stg2_wrcal_cnt_reg[1]_60 ;\n input \\po_stg2_wrcal_cnt_reg[1]_61 ;\n input rstdiv0_sync_r1_reg_rep__4;\n input rstdiv0_sync_r1_reg_rep__6;\n input [0:0]rstdiv0_sync_r1_reg_rep__5;\n input [287:0]Q;\n input idelay_ld_rst;\n input idelay_ld_rst_3;\n input idelay_ld_rst_4;\n input idelay_ld_rst_5;\n input rstdiv0_sync_r1_reg_rep__26;\n input rstdiv0_sync_r1_reg_rep__26_0;\n input rstdiv0_sync_r1_reg_rep__25;\n input [0:0]\\sm_r_reg[0]_0 ;\n input fine_delay_sel_r;\n input [8:0]fine_delay_mod;\n input [2:0]mc_cas_n;\n input [37:0]\\rd_ptr_reg[3] ;\n input \\my_empty_reg[1] ;\n input [5:0]mem_out;\n input \\my_empty_reg[1]_0 ;\n input [2:0]mc_ras_n;\n input [0:0]mc_odt;\n input [11:0]\\rd_ptr_reg[3]_0 ;\n input \\my_empty_reg[1]_1 ;\n input [0:0]mc_cke;\n input [2:0]mc_we_n;\n input [35:0]\\cmd_pipe_plus.mc_address_reg[44] ;\n input [31:0]\\rd_ptr_reg[3]_1 ;\n input \\my_empty_reg[1]_2 ;\n input [8:0]\\cmd_pipe_plus.mc_bank_reg[8] ;\n input [63:0]\\rd_ptr_reg[3]_2 ;\n input \\my_empty_reg[1]_3 ;\n input [63:0]\\rd_ptr_reg[3]_3 ;\n input \\my_empty_reg[1]_4 ;\n input [63:0]\\rd_ptr_reg[3]_4 ;\n input \\my_empty_reg[1]_5 ;\n input [63:0]\\rd_ptr_reg[3]_5 ;\n input \\my_empty_reg[1]_6 ;\n input [0:0]mc_cs_n;\n input [5:0]\\pi_counter_read_val_reg[5] ;\n input \\po_counter_read_val_reg[2] ;\n input rstdiv0_sync_r1_reg_rep__26_1;\n input rstdiv0_sync_r1_reg_rep__26_2;\n input \\mmcm_init_trail_reg[0] ;\n input \\mmcm_current_reg[0] ;\n input sent_col;\n input [4:0]\\po_counter_read_val_reg[8]_30 ;\n input [4:0]\\po_counter_read_val_reg[8]_31 ;\n input [5:0]\\po_counter_read_val_reg[5] ;\n input \\A[2]__2_0 ;\n input psdone;\n input rstdiv0_sync_r1_reg_rep__0;\n input [0:0]rstdiv0_sync_r1_reg_rep__19;\n input [63:0]\\byte_r_reg[0]_0 ;\n input fine_adjust_reg;\n input samp_edge_cnt0_en_r_reg;\n input [0:0]pi_cnt_dec_reg;\n input rstdiv0_sync_r1_reg_rep__24_0;\n input p_81_in;\n input rstdiv0_sync_r1_reg_rep__24_1;\n input [0:0]rstdiv0_sync_r1_reg_rep__17;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;\n input [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;\n input [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ;\n input [0:0]my_empty;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;\n input [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;\n input [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ;\n input [0:0]my_empty_6;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;\n input [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;\n input [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ;\n input [0:0]my_empty_7;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ;\n input [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ;\n input [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ;\n input [0:0]my_empty_8;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;\n input [0:0]po_cnt_dec_reg;\n input [11:0]\\device_temp_r_reg[11] ;\n input mc_wrdata_en;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[2]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[3]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ;\n input [1:0]mc_cmd;\n input \\cmd_pipe_plus.mc_data_offset_reg[0]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_reg[1]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_reg[2]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_reg[3]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_reg[4]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_reg[5]_0 ;\n input \\stg3_r_reg[0] ;\n input pd_out;\n\n wire [1:0]A;\n wire \\A[0]__0 ;\n wire \\A[0]__4 ;\n wire \\A[1]_0 ;\n wire \\A[1]_1 ;\n wire \\A[1]_10 ;\n wire \\A[1]_11 ;\n wire \\A[1]_12 ;\n wire \\A[1]_13 ;\n wire \\A[1]_14 ;\n wire \\A[1]_15 ;\n wire \\A[1]_16 ;\n wire \\A[1]_17 ;\n wire \\A[1]_18 ;\n wire \\A[1]_19 ;\n wire \\A[1]_2 ;\n wire \\A[1]_20 ;\n wire \\A[1]_21 ;\n wire \\A[1]_22 ;\n wire \\A[1]_23 ;\n wire \\A[1]_24 ;\n wire \\A[1]_25 ;\n wire \\A[1]_26 ;\n wire \\A[1]_27 ;\n wire \\A[1]_28 ;\n wire \\A[1]_29 ;\n wire \\A[1]_3 ;\n wire \\A[1]_30 ;\n wire \\A[1]_31 ;\n wire \\A[1]_32 ;\n wire \\A[1]_33 ;\n wire \\A[1]_34 ;\n wire \\A[1]_35 ;\n wire \\A[1]_36 ;\n wire \\A[1]_37 ;\n wire \\A[1]_38 ;\n wire \\A[1]_39 ;\n wire \\A[1]_4 ;\n wire \\A[1]_40 ;\n wire \\A[1]_41 ;\n wire \\A[1]_42 ;\n wire \\A[1]_43 ;\n wire \\A[1]_44 ;\n wire \\A[1]_45 ;\n wire \\A[1]_46 ;\n wire \\A[1]_47 ;\n wire \\A[1]_48 ;\n wire \\A[1]_49 ;\n wire \\A[1]_5 ;\n wire \\A[1]_50 ;\n wire \\A[1]_51 ;\n wire \\A[1]_52 ;\n wire \\A[1]_53 ;\n wire \\A[1]_54 ;\n wire \\A[1]_55 ;\n wire \\A[1]_56 ;\n wire \\A[1]_57 ;\n wire \\A[1]_58 ;\n wire \\A[1]_59 ;\n wire \\A[1]_6 ;\n wire \\A[1]_60 ;\n wire \\A[1]_61 ;\n wire \\A[1]_62 ;\n wire \\A[1]_63 ;\n wire \\A[1]_7 ;\n wire \\A[1]_8 ;\n wire \\A[1]_9 ;\n wire \\A[1]__0 ;\n wire \\A[1]__3 ;\n wire \\A[1]__4 ;\n wire \\A[1]__4_0 ;\n wire \\A[2]__1 ;\n wire \\A[2]__2 ;\n wire \\A[2]__2_0 ;\n wire A_1__s_net_1;\n wire A_rst_primitives_reg;\n wire CLK;\n wire [5:0]COUNTERLOADVAL;\n wire [7:0]D;\n wire [2:0]D0;\n wire [2:0]D1;\n wire [2:0]D2;\n wire [2:0]D3;\n wire [3:0]D4;\n wire [3:0]D5;\n wire [3:0]D6;\n wire [3:0]D7;\n wire [3:0]D8;\n wire [3:0]D9;\n wire D_po_coarse_enable110_out;\n wire D_po_counter_read_en122_out;\n wire D_po_fine_enable107_out;\n wire D_po_fine_inc113_out;\n wire D_po_sel_fine_oclk_delay125_out;\n wire [0:0]E;\n wire LD0;\n wire LD0_0;\n wire LD0_1;\n wire LD0_2;\n wire [287:0]Q;\n wire [0:0]SR;\n wire [0:0]SS;\n wire app_zq_r_reg;\n wire bit_cnt;\n wire burst_addr_r_i_1_n_0;\n wire \\byte_r_reg[0] ;\n wire [63:0]\\byte_r_reg[0]_0 ;\n wire \\byte_r_reg[1] ;\n wire [2:2]byte_sel_cnt;\n wire \\byte_sel_data_map_reg[1] ;\n wire cal1_cnt_cpt_r1;\n wire cal1_state_r1535_out;\n wire cal1_wait_r;\n wire cal2_done_r;\n wire cal2_done_r_i_1_n_0;\n wire cal2_if_reset_i_1_n_0;\n wire calib_complete;\n wire calib_in_common;\n wire [1:1]calib_zero_inputs;\n wire [0:0]calib_zero_inputs__0;\n wire ck_addr_cmd_delay_done;\n wire ck_po_stg2_f_en;\n wire ck_po_stg2_f_en_i_1_n_0;\n wire ck_po_stg2_f_indec;\n wire ck_po_stg2_f_indec_i_1_n_0;\n wire cmd_delay_start0;\n wire [35:0]\\cmd_pipe_plus.mc_address_reg[44] ;\n wire [8:0]\\cmd_pipe_plus.mc_bank_reg[8] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[0] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[1] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[2] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[2]_0 ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[3] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[3]_0 ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[4] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ;\n wire [5:0]\\cmd_pipe_plus.mc_data_offset_1_reg[5] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[0] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[0]_0 ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[1] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[1]_0 ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[2] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[2]_0 ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[3] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[3]_0 ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[4] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[4]_0 ;\n wire [5:0]\\cmd_pipe_plus.mc_data_offset_reg[5] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[5]_0 ;\n wire cmd_po_en_stg2_f;\n wire cnt_cmd_done_r;\n wire cnt_dllk_zqinit_done_r;\n wire cnt_dllk_zqinit_done_r_i_1_n_0;\n wire [7:6]cnt_dllk_zqinit_r_reg__0;\n wire cnt_init_af_done_r;\n wire cnt_init_af_done_r_i_1_n_0;\n wire [1:0]cnt_init_af_r;\n wire cnt_init_mr_done_r;\n wire cnt_init_mr_done_r_i_1_n_0;\n wire [1:0]cnt_init_mr_r;\n wire cnt_init_mr_r1;\n wire cnt_pwron_cke_done_r;\n wire cnt_pwron_cke_done_r_i_1_n_0;\n wire [7:0]cnt_pwron_r_reg__0;\n wire cnt_pwron_reset_done_r;\n wire cnt_pwron_reset_done_r0;\n wire cnt_pwron_reset_done_r_i_1_n_0;\n wire cnt_shift_r0;\n wire cnt_txpr_done_r;\n wire cnt_txpr_done_r_i_1_n_0;\n wire [2:0]cnt_txpr_r_reg__0;\n wire cnt_wait_state;\n wire complex_act_start;\n wire complex_init_pi_dec_done;\n wire complex_init_pi_dec_done_r_i_1_n_0;\n wire complex_ocal_num_samples_done_r;\n wire [2:0]complex_ocal_rd_victim_sel;\n wire complex_ocal_ref_req;\n wire complex_ocal_reset_rd_addr;\n wire complex_oclk_calib_resume;\n wire complex_pi_incdec_done;\n wire complex_pi_incdec_done_i_1_n_0;\n wire \\complex_row_cnt_ocal_reg[0] ;\n wire [2:0]ctl_lane_cnt;\n wire ctl_lane_sel;\n wire [5:0]\\data_offset_1_i1_reg[5] ;\n wire ddr2_pre_flag_r_i_1_n_0;\n wire ddr2_refresh_flag_r;\n wire ddr2_refresh_flag_r_i_1_n_0;\n wire ddr3_lm_done_r;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_1 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_10 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_100 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_102 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_103 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_104 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_105 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_106 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_107 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_108 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_109 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_11 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_110 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_111 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_112 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_113 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_115 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_116 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_117 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_13 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_14 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_15 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_16 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_17 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_18 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_19 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_2 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_20 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_21 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_22 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_23 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_24 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_25 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_26 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_27 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_28 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_29 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_30 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_32 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_34 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_35 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_4 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_44 ;\n (* MAX_FANOUT = \"100\" *) (* RTL_MAX_FANOUT = \"found\" *) wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_45 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_50 ;\n (* MAX_FANOUT = \"100\" *) (* RTL_MAX_FANOUT = \"found\" *) wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_51 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_58 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_59 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_64 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_65 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_68 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_69 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_78 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_79 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_84 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_85 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_87 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_88 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_89 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_9 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_90 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_93 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_94 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_95 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_98 ;\n wire \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_99 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_1 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_101 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_102 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_106 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_107 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_108 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_110 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_112 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_114 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_116 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_118 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_120 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_122 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_124 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_126 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_128 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_130 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_132 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_134 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_136 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_137 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_138 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_139 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_140 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_141 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_142 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_144 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_145 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_146 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_147 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_148 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_149 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_150 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_151 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_152 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_153 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_154 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_155 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_156 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_157 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_158 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_159 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_161 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_180 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_183 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_184 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_185 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_186 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_188 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_189 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_190 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_2 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_3 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_30 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_39 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_4 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_40 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_41 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_42 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_43 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_44 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_45 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_46 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_47 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_50 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_51 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_52 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_56 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_6 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_60 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_79 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_80 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_81 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_82 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_83 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_84 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_85 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_86 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_87 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_88 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_9 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_91 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_92 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_93 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_94 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_95 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_96 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ;\n wire \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_99 ;\n wire ddr_phy_tempmon_0_n_2;\n wire ddr_phy_tempmon_0_n_3;\n wire ddr_phy_tempmon_0_n_4;\n wire ddr_phy_tempmon_0_n_5;\n wire ddr_phy_tempmon_0_n_6;\n wire [5:0]dec_cnt_reg;\n wire detect_edge_done_r;\n wire detect_pi_found_dqs;\n wire [11:0]\\device_temp_r_reg[11] ;\n wire done_dqs_dec239_out;\n wire done_dqs_tap_inc;\n wire dq_cnt_inc_i_1_n_0;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ;\n wire [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ;\n wire [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;\n wire [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ;\n wire [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ;\n wire [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ;\n wire [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;\n wire [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;\n wire [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ;\n wire dqs_found_prech_req;\n wire dqs_found_prech_req_i_1_n_0;\n wire dqs_po_dec_done;\n wire dqs_po_dec_done_r2;\n wire dqs_po_en_stg2_f;\n wire dqs_po_en_stg2_f_reg;\n wire dqs_po_stg2_f_incdec;\n wire dqs_wl_po_stg2_c_incdec;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_10 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_100 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_101 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_102 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_103 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_104 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_105 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_106 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_109 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_110 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_111 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_112 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_12 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_13 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_14 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_27 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_41 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_42 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_43 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_44 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_46 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_5 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_73 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_74 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_76 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_78 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_79 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_80 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_85 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_86 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_87 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_88 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_89 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_9 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_90 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_91 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_92 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_93 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_94 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_95 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_96 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_97 ;\n wire \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_98 ;\n wire early1_data_i_1_n_0;\n wire early2_data_i_1_n_0;\n wire \\en_cnt_div4.enable_wrlvl_cnt_reg[3] ;\n wire [2:1]final_coarse_tap;\n wire final_dec_done_i_1_n_0;\n wire fine_adj_state_r144_out;\n wire fine_adj_state_r16_out;\n wire fine_adjust_done_r_i_1_n_0;\n wire fine_adjust_i_1_n_0;\n wire fine_adjust_reg;\n wire [8:0]fine_delay_mod;\n wire \\fine_delay_mod_reg[20] ;\n wire \\fine_delay_mod_reg[26] ;\n wire \\fine_delay_mod_reg[5] ;\n wire [7:0]\\fine_delay_r_reg[26] ;\n wire [7:0]\\fine_delay_r_reg[26]_0 ;\n wire [7:0]\\fine_delay_r_reg[26]_1 ;\n wire [0:0]\\fine_delay_r_reg[2] ;\n wire [0:0]\\fine_delay_r_reg[5] ;\n wire [0:0]\\fine_delay_r_reg[5]_0 ;\n wire [0:0]\\fine_delay_r_reg[5]_1 ;\n wire fine_delay_sel_i_1_n_0;\n wire fine_delay_sel_r;\n wire fine_delay_sel_r_reg;\n wire fine_dly_error_i_1_n_0;\n wire first_rdlvl_pat_r;\n wire first_wrcal_pat_r;\n wire flag_ck_negedge09_out;\n wire flag_ck_negedge_i_1_n_0;\n wire found_first_edge_r_i_1_n_0;\n wire found_second_edge_r_i_1_n_0;\n wire found_stable_eye_last_r;\n wire found_stable_eye_last_r_i_1_n_0;\n wire [1:0]\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 ;\n wire \\gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[0] ;\n wire \\gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[1] ;\n wire \\gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[2] ;\n wire \\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1_n_0 ;\n wire \\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 ;\n wire \\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 ;\n wire \\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 ;\n wire \\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 ;\n wire \\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 ;\n wire \\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 ;\n wire \\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 ;\n wire \\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 ;\n wire \\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 ;\n wire \\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 ;\n wire \\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 ;\n wire \\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 ;\n wire \\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 ;\n wire \\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 ;\n wire \\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 ;\n wire \\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 ;\n wire \\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 ;\n wire \\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 ;\n wire \\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 ;\n wire \\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 ;\n wire \\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 ;\n wire \\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 ;\n wire \\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 ;\n wire \\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 ;\n wire \\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 ;\n wire \\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 ;\n wire \\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_208 ;\n wire \\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 ;\n wire \\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 ;\n wire \\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 ;\n wire \\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 ;\n wire \\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 ;\n wire \\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 ;\n wire \\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 ;\n wire \\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 ;\n wire \\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 ;\n wire \\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 ;\n wire \\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 ;\n wire \\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 ;\n wire \\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 ;\n wire \\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 ;\n wire \\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 ;\n wire \\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 ;\n wire \\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 ;\n wire \\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 ;\n wire \\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 ;\n wire \\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 ;\n wire \\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 ;\n wire \\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 ;\n wire \\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 ;\n wire \\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 ;\n wire \\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 ;\n wire \\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 ;\n wire \\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 ;\n wire \\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 ;\n wire \\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 ;\n wire \\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_212 ;\n wire \\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 ;\n wire \\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 ;\n wire \\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 ;\n wire \\gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1_n_0 ;\n wire \\gen_track_left_edge[0].pb_found_edge_r[0]_i_1_n_0 ;\n wire \\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1_n_0 ;\n wire \\gen_track_left_edge[0].pb_found_stable_eye_r_reg ;\n wire \\gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1_n_0 ;\n wire \\gen_track_left_edge[1].pb_found_edge_r[1]_i_1_n_0 ;\n wire \\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1_n_0 ;\n wire \\gen_track_left_edge[1].pb_found_stable_eye_r_reg ;\n wire \\gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1_n_0 ;\n wire \\gen_track_left_edge[2].pb_found_edge_r[2]_i_1_n_0 ;\n wire \\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1_n_0 ;\n wire \\gen_track_left_edge[2].pb_found_stable_eye_r_reg ;\n wire \\gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1_n_0 ;\n wire \\gen_track_left_edge[3].pb_found_edge_r[3]_i_1_n_0 ;\n wire \\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1_n_0 ;\n wire \\gen_track_left_edge[3].pb_found_stable_eye_r_reg ;\n wire \\gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1_n_0 ;\n wire \\gen_track_left_edge[4].pb_found_edge_r[4]_i_1_n_0 ;\n wire \\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1_n_0 ;\n wire \\gen_track_left_edge[4].pb_found_stable_eye_r_reg ;\n wire \\gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1_n_0 ;\n wire \\gen_track_left_edge[5].pb_found_edge_r[5]_i_1_n_0 ;\n wire \\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1_n_0 ;\n wire \\gen_track_left_edge[5].pb_found_stable_eye_r_reg ;\n wire \\gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1_n_0 ;\n wire \\gen_track_left_edge[6].pb_found_edge_r[6]_i_1_n_0 ;\n wire \\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1_n_0 ;\n wire \\gen_track_left_edge[6].pb_found_stable_eye_r_reg ;\n wire \\gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_2_n_0 ;\n wire \\gen_track_left_edge[7].pb_found_edge_r[7]_i_1_n_0 ;\n wire \\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1_n_0 ;\n wire \\gen_track_left_edge[7].pb_found_stable_eye_r_reg ;\n wire \\genblk8[0].left_edge_found_pb[0]_i_1_n_0 ;\n wire \\genblk8[0].left_edge_updated[0]_i_1_n_0 ;\n wire \\genblk8[0].right_edge_found_pb[0]_i_1_n_0 ;\n wire \\genblk8[1].left_edge_found_pb[1]_i_1_n_0 ;\n wire \\genblk8[1].left_edge_updated[1]_i_1_n_0 ;\n wire \\genblk8[1].right_edge_found_pb[1]_i_1_n_0 ;\n wire \\genblk8[2].left_edge_found_pb[2]_i_1_n_0 ;\n wire \\genblk8[2].left_edge_updated[2]_i_1_n_0 ;\n wire \\genblk8[2].right_edge_found_pb[2]_i_1_n_0 ;\n wire \\genblk8[3].left_edge_found_pb[3]_i_1_n_0 ;\n wire \\genblk8[3].left_edge_updated[3]_i_1_n_0 ;\n wire \\genblk8[3].right_edge_found_pb[3]_i_1_n_0 ;\n wire \\genblk8[4].left_edge_found_pb[4]_i_1_n_0 ;\n wire \\genblk8[4].left_edge_updated[4]_i_1_n_0 ;\n wire \\genblk8[4].right_edge_found_pb[4]_i_1_n_0 ;\n wire \\genblk8[5].left_edge_found_pb[5]_i_1_n_0 ;\n wire \\genblk8[5].left_edge_updated[5]_i_1_n_0 ;\n wire \\genblk8[5].right_edge_found_pb[5]_i_1_n_0 ;\n wire \\genblk8[6].left_edge_found_pb[6]_i_1_n_0 ;\n wire \\genblk8[6].left_edge_updated[6]_i_1_n_0 ;\n wire \\genblk8[6].right_edge_found_pb[6]_i_1_n_0 ;\n wire \\genblk8[7].left_edge_found_pb[7]_i_1_n_0 ;\n wire \\genblk8[7].left_edge_updated[7]_i_1_n_0 ;\n wire \\genblk8[7].right_edge_found_pb[7]_i_1_n_0 ;\n wire \\genblk9[0].fine_delay_incdec_pb[0]_i_7_n_0 ;\n wire \\genblk9[1].fine_delay_incdec_pb_reg[1] ;\n wire \\genblk9[2].fine_delay_incdec_pb_reg[2] ;\n wire \\genblk9[3].fine_delay_incdec_pb_reg[3] ;\n wire \\genblk9[5].fine_delay_incdec_pb_reg[5] ;\n wire \\genblk9[6].fine_delay_incdec_pb_reg[6] ;\n wire \\genblk9[7].fine_delay_incdec_pb_reg[7] ;\n wire idel_adj_inc_i_1_n_0;\n wire idel_pat_detect_valid_r_i_1_n_0;\n wire idelay_ce;\n wire idelay_ce_int;\n wire idelay_ce_r1;\n wire idelay_inc;\n wire idelay_inc_int;\n wire idelay_inc_r1;\n wire idelay_ld;\n wire idelay_ld_done_i_1_n_0;\n wire idelay_ld_i_1_n_0;\n wire idelay_ld_rst;\n wire idelay_ld_rst_3;\n wire idelay_ld_rst_4;\n wire idelay_ld_rst_5;\n wire [1:0]\\idelay_tap_cnt_r_reg[0][3][0] ;\n wire ififo_rst_reg;\n wire ififo_rst_reg_0;\n wire ififo_rst_reg_1;\n wire ififo_rst_reg_2;\n wire [3:0]in0;\n wire inhibit_edge_detect_r;\n wire inhibit_edge_detect_r_i_1_n_0;\n wire init_calib_complete_r_reg;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire init_calib_complete_reg_rep__0_n_0;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire init_calib_complete_reg_rep__10_n_0;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire init_calib_complete_reg_rep__11_n_0;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire init_calib_complete_reg_rep__12_n_0;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire init_calib_complete_reg_rep__13_n_0;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire init_calib_complete_reg_rep__1_n_0;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire init_calib_complete_reg_rep__2_n_0;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire init_calib_complete_reg_rep__3_n_0;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire init_calib_complete_reg_rep__4_n_0;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire init_calib_complete_reg_rep__8_n_0;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire init_calib_complete_reg_rep__9_n_0;\n wire init_complete_r_i_1_n_0;\n wire init_complete_r_timing_i_1_n_0;\n wire init_complete_r_timing_orig;\n wire init_dec_done_i_1_n_0;\n wire init_dqsfound_done_r2;\n wire init_dqsfound_done_r5;\n wire init_dqsfound_done_r_i_1_n_0;\n wire [6:6]init_state_r;\n wire [7:0]left_edge_updated;\n wire lim2init_prech_req;\n wire maint_prescaler_r1;\n wire \\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_11 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_12 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_13 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_17 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_0 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_10 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_12 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_24 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_25 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_26 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_27 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_28 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_29 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_30 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_31 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_36 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_37 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_38 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_40 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_41 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_42 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_46 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_47 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_48 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_49 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_50 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_54 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_55 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_56 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_58 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_7 ;\n wire \\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_8 ;\n wire \\mcGo_r_reg[15] ;\n wire [2:0]mc_cas_n;\n wire [0:0]mc_cke;\n wire [1:0]mc_cmd;\n wire [0:0]mc_cs_n;\n wire [0:0]mc_odt;\n wire [2:0]mc_ras_n;\n wire [2:0]mc_we_n;\n wire mc_wrdata_en;\n wire mem_init_done_r;\n wire [5:0]mem_out;\n wire \\mmcm_current_reg[0] ;\n wire \\mmcm_init_trail_reg[0] ;\n wire mpr_dec_cpt_r_i_1_n_0;\n wire mpr_end_if_reset;\n wire mpr_last_byte_done;\n wire mpr_last_byte_done_i_1_n_0;\n wire mpr_rank_done_r_i_1_n_0;\n wire mpr_rdlvl_done_r_i_1_n_0;\n wire mpr_rdlvl_start_r;\n wire mpr_rnk_done;\n wire mux_cmd_wren;\n wire mux_reset_n;\n wire mux_wrdata_en;\n wire [0:0]my_empty;\n wire [0:0]my_empty_6;\n wire [0:0]my_empty_7;\n wire [0:0]my_empty_8;\n wire \\my_empty_reg[1] ;\n wire \\my_empty_reg[1]_0 ;\n wire \\my_empty_reg[1]_1 ;\n wire \\my_empty_reg[1]_2 ;\n wire \\my_empty_reg[1]_3 ;\n wire \\my_empty_reg[1]_4 ;\n wire \\my_empty_reg[1]_5 ;\n wire \\my_empty_reg[1]_6 ;\n wire \\my_empty_reg[7] ;\n wire \\my_empty_reg[7]_0 ;\n wire [71:0]\\my_empty_reg[7]_1 ;\n wire [3:0]\\my_empty_reg[7]_10 ;\n wire [3:0]\\my_empty_reg[7]_11 ;\n wire [7:0]\\my_empty_reg[7]_12 ;\n wire [7:0]\\my_empty_reg[7]_13 ;\n wire [7:0]\\my_empty_reg[7]_14 ;\n wire [7:0]\\my_empty_reg[7]_15 ;\n wire [7:0]\\my_empty_reg[7]_16 ;\n wire [7:0]\\my_empty_reg[7]_17 ;\n wire [7:0]\\my_empty_reg[7]_18 ;\n wire [7:0]\\my_empty_reg[7]_19 ;\n wire [71:0]\\my_empty_reg[7]_2 ;\n wire [7:0]\\my_empty_reg[7]_20 ;\n wire [7:0]\\my_empty_reg[7]_21 ;\n wire [7:0]\\my_empty_reg[7]_22 ;\n wire [7:0]\\my_empty_reg[7]_23 ;\n wire [7:0]\\my_empty_reg[7]_24 ;\n wire [7:0]\\my_empty_reg[7]_25 ;\n wire [7:0]\\my_empty_reg[7]_26 ;\n wire [7:0]\\my_empty_reg[7]_27 ;\n wire [7:0]\\my_empty_reg[7]_28 ;\n wire [7:0]\\my_empty_reg[7]_29 ;\n wire [71:0]\\my_empty_reg[7]_3 ;\n wire [7:0]\\my_empty_reg[7]_30 ;\n wire [7:0]\\my_empty_reg[7]_31 ;\n wire [7:0]\\my_empty_reg[7]_32 ;\n wire [7:0]\\my_empty_reg[7]_33 ;\n wire [7:0]\\my_empty_reg[7]_34 ;\n wire [7:0]\\my_empty_reg[7]_35 ;\n wire [7:0]\\my_empty_reg[7]_36 ;\n wire [7:0]\\my_empty_reg[7]_37 ;\n wire [7:0]\\my_empty_reg[7]_38 ;\n wire [7:0]\\my_empty_reg[7]_39 ;\n wire [71:0]\\my_empty_reg[7]_4 ;\n wire [7:0]\\my_empty_reg[7]_40 ;\n wire [7:0]\\my_empty_reg[7]_41 ;\n wire [7:0]\\my_empty_reg[7]_42 ;\n wire [7:0]\\my_empty_reg[7]_43 ;\n wire [3:0]\\my_empty_reg[7]_5 ;\n wire [3:0]\\my_empty_reg[7]_6 ;\n wire [3:0]\\my_empty_reg[7]_7 ;\n wire [3:0]\\my_empty_reg[7]_8 ;\n wire [3:0]\\my_empty_reg[7]_9 ;\n wire [3:0]\\my_full_reg[3] ;\n wire [1:0]\\my_full_reg[3]_0 ;\n wire new_cnt_dqs_r;\n wire new_cnt_dqs_r_i_1_n_0;\n wire no_err_win_detected_latch_i_1_n_0;\n wire num_samples_done_ind_i_1_n_0;\n wire num_samples_done_r;\n wire ocal_last_byte_done;\n wire ocd_prech_req;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_0 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_1 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_13 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_15 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_2 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_28 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_29 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_3 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_30 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_31 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_4 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_47 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_48 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_49 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_50 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_51 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_52 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_53 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_54 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_55 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_56 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_57 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_58 ;\n wire \\oclk_calib.u_ddr_phy_oclkdelay_cal_n_59 ;\n wire out;\n wire p_0_in;\n wire p_0_in102_in;\n wire p_0_in10_in;\n wire p_0_in13_in;\n wire p_0_in16_in;\n wire p_0_in1_in;\n wire p_0_in23_in;\n wire p_0_in4_in;\n wire p_0_in7_in;\n wire p_0_in84_in;\n wire p_0_in87_in;\n wire p_0_in90_in;\n wire p_0_in93_in;\n wire p_0_in96_in;\n wire p_0_in99_in;\n wire [3:2]p_0_in_0;\n wire p_0_in_2;\n wire p_0_out;\n wire p_103_out;\n wire p_106_out;\n wire p_119_out;\n wire p_122_out;\n wire p_127_out;\n wire p_130_out;\n wire p_143_out;\n wire p_146_out;\n wire p_154_out;\n wire p_1_in;\n wire p_1_in27_in;\n wire p_1_in50_in;\n wire p_2_in24_in;\n wire p_3_in25_in;\n wire p_81_in;\n wire p_95_out;\n wire p_98_out;\n wire [7:0]pb_detect_edge_done_r;\n wire pb_found_stable_eye_r52_out;\n wire pb_found_stable_eye_r56_out;\n wire pb_found_stable_eye_r60_out;\n wire pb_found_stable_eye_r64_out;\n wire pb_found_stable_eye_r68_out;\n wire pb_found_stable_eye_r72_out;\n wire pb_found_stable_eye_r76_out;\n wire pd_out;\n wire \\phaser_in_gen.phaser_in_i_12__0_n_0 ;\n wire \\phaser_in_gen.phaser_in_i_12__1_n_0 ;\n wire \\phaser_in_gen.phaser_in_i_12__2_n_0 ;\n wire \\phaser_in_gen.phaser_in_i_12_n_0 ;\n wire [10:0]\\phy_ctl_wd_i1_reg[24] ;\n wire [33:0]phy_dout;\n wire phy_if_reset;\n wire phy_if_reset0__0;\n wire phy_if_reset_w;\n wire phy_rddata_en;\n wire phy_rddata_en_1;\n wire phy_read_calib;\n wire phy_write_calib;\n wire pi_calib_done;\n wire pi_cnt_dec_i_1_n_0;\n wire [0:0]pi_cnt_dec_reg;\n wire [5:0]\\pi_counter_read_val_reg[5] ;\n wire [1:1]pi_dqs_found_all_bank;\n wire [1:0]pi_dqs_found_all_bank_r;\n wire [0:0]pi_dqs_found_any_bank;\n wire \\pi_dqs_found_any_bank[0]_i_1_n_0 ;\n wire pi_dqs_found_done_r1;\n wire \\pi_dqs_found_lanes_r1_reg[0] ;\n wire \\pi_dqs_found_lanes_r1_reg[0]_0 ;\n wire \\pi_dqs_found_lanes_r1_reg[0]_1 ;\n wire \\pi_dqs_found_lanes_r1_reg[0]_2 ;\n wire \\pi_dqs_found_lanes_r1_reg[1] ;\n wire \\pi_dqs_found_lanes_r1_reg[1]_0 ;\n wire \\pi_dqs_found_lanes_r1_reg[1]_1 ;\n wire \\pi_dqs_found_lanes_r1_reg[1]_2 ;\n wire [5:0]\\pi_dqs_found_lanes_r1_reg[1]_3 ;\n wire \\pi_dqs_found_lanes_r1_reg[2] ;\n wire \\pi_dqs_found_lanes_r1_reg[2]_0 ;\n wire \\pi_dqs_found_lanes_r1_reg[2]_1 ;\n wire \\pi_dqs_found_lanes_r1_reg[2]_2 ;\n wire [5:0]\\pi_dqs_found_lanes_r1_reg[2]_3 ;\n wire \\pi_dqs_found_lanes_r1_reg[3] ;\n wire \\pi_dqs_found_lanes_r1_reg[3]_0 ;\n wire \\pi_dqs_found_lanes_r1_reg[3]_1 ;\n wire \\pi_dqs_found_lanes_r1_reg[3]_2 ;\n wire [5:0]\\pi_dqs_found_lanes_r1_reg[3]_3 ;\n wire pi_dqs_found_rank_done;\n wire pi_en_stg2_f_timing_reg;\n wire pi_fine_dly_dec_done;\n wire \\pi_rst_stg1_cal_r_reg[0] ;\n wire pi_stg2_f_incdec_timing_i_1_n_0;\n wire pi_stg2_load_timing_i_1_n_0;\n wire [1:0]pi_stg2_rdlvl_cnt;\n wire po_cnt_dec_i_1__0_n_0;\n wire po_cnt_dec_i_1_n_0;\n wire [0:0]po_cnt_dec_reg;\n wire po_cnt_inc_i_1_n_0;\n wire \\po_counter_read_val_reg[2] ;\n wire [5:0]\\po_counter_read_val_reg[5] ;\n wire \\po_counter_read_val_reg[8] ;\n wire \\po_counter_read_val_reg[8]_0 ;\n wire \\po_counter_read_val_reg[8]_1 ;\n wire \\po_counter_read_val_reg[8]_10 ;\n wire \\po_counter_read_val_reg[8]_11 ;\n wire \\po_counter_read_val_reg[8]_12 ;\n wire \\po_counter_read_val_reg[8]_13 ;\n wire \\po_counter_read_val_reg[8]_14 ;\n wire \\po_counter_read_val_reg[8]_15 ;\n wire \\po_counter_read_val_reg[8]_16 ;\n wire \\po_counter_read_val_reg[8]_17 ;\n wire \\po_counter_read_val_reg[8]_18 ;\n wire \\po_counter_read_val_reg[8]_19 ;\n wire \\po_counter_read_val_reg[8]_2 ;\n wire \\po_counter_read_val_reg[8]_20 ;\n wire \\po_counter_read_val_reg[8]_21 ;\n wire \\po_counter_read_val_reg[8]_22 ;\n wire \\po_counter_read_val_reg[8]_23 ;\n wire \\po_counter_read_val_reg[8]_24 ;\n wire \\po_counter_read_val_reg[8]_25 ;\n wire \\po_counter_read_val_reg[8]_26 ;\n wire \\po_counter_read_val_reg[8]_27 ;\n wire \\po_counter_read_val_reg[8]_28 ;\n wire \\po_counter_read_val_reg[8]_29 ;\n wire \\po_counter_read_val_reg[8]_3 ;\n wire [4:0]\\po_counter_read_val_reg[8]_30 ;\n wire [4:0]\\po_counter_read_val_reg[8]_31 ;\n wire \\po_counter_read_val_reg[8]_4 ;\n wire \\po_counter_read_val_reg[8]_5 ;\n wire \\po_counter_read_val_reg[8]_6 ;\n wire \\po_counter_read_val_reg[8]_7 ;\n wire \\po_counter_read_val_reg[8]_8 ;\n wire \\po_counter_read_val_reg[8]_9 ;\n wire po_en_stg23;\n wire [0:0]po_enstg2_f;\n wire [2:0]\\po_rdval_cnt_reg[8] ;\n wire po_stg23_incdec;\n wire [0:0]po_stg2_fincdec;\n wire [2:2]po_stg2_wrcal_cnt;\n wire \\po_stg2_wrcal_cnt_reg[1] ;\n wire \\po_stg2_wrcal_cnt_reg[1]_0 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_1 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_10 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_11 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_12 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_13 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_14 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_15 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_16 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_17 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_18 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_19 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_2 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_20 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_21 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_22 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_23 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_24 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_25 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_26 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_27 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_28 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_29 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_3 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_30 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_31 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_32 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_33 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_34 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_35 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_36 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_37 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_38 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_39 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_4 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_40 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_41 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_42 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_43 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_44 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_45 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_46 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_47 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_48 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_49 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_5 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_50 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_51 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_52 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_53 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_54 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_55 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_56 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_57 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_58 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_59 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_6 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_60 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_61 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_7 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_8 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_9 ;\n wire poc_sample_pd;\n wire \\prbs_dqs_cnt_r[0]_i_1_n_0 ;\n wire \\prbs_dqs_cnt_r[1]_i_1_n_0 ;\n wire \\prbs_dqs_cnt_r[2]_i_1_n_0 ;\n wire prbs_dqs_tap_limit_r_i_1_n_0;\n wire prbs_found_1st_edge_r_i_1_n_0;\n wire prbs_last_byte_done;\n wire prbs_last_byte_done_i_1_n_0;\n wire prbs_last_byte_done_r;\n wire prbs_pi_stg2_f_en;\n wire prbs_pi_stg2_f_incdec;\n wire prbs_prech_req_r;\n wire prbs_prech_req_r_i_1_n_0;\n wire prbs_rdlvl_done_i_1_n_0;\n wire prbs_rdlvl_done_pulse0;\n wire prbs_rdlvl_done_r1;\n wire prbs_rdlvl_start_r;\n wire prbs_rdlvl_start_r_reg;\n wire [4:0]prbs_state_r;\n wire prbs_state_r178_out;\n wire prbs_tap_en_r;\n wire prbs_tap_en_r_i_1_n_0;\n wire prbs_tap_inc_r;\n wire prbs_tap_inc_r_i_1_n_0;\n wire prech_done;\n wire prech_pending_r;\n wire prech_pending_r_i_1_n_0;\n wire prech_req;\n wire psdone;\n wire [0:0]\\qcntr_r_reg[0] ;\n wire rank_done_r_i_1_n_0;\n wire rd_active_r1;\n wire rd_active_r2;\n wire \\rd_addr[7]_i_1_n_0 ;\n wire \\rd_byte_data_offset_reg[0]_3 ;\n wire rd_data_offset_cal_done;\n wire [3:2]rd_data_offset_ranks_0;\n wire [3:2]rd_data_offset_ranks_1;\n wire \\rd_mux_sel_r_reg[1] ;\n wire \\rd_mux_sel_r_reg[1]_0 ;\n wire \\rd_mux_sel_r_reg[1]_1 ;\n wire \\rd_mux_sel_r_reg[1]_10 ;\n wire \\rd_mux_sel_r_reg[1]_11 ;\n wire \\rd_mux_sel_r_reg[1]_12 ;\n wire \\rd_mux_sel_r_reg[1]_13 ;\n wire \\rd_mux_sel_r_reg[1]_14 ;\n wire \\rd_mux_sel_r_reg[1]_15 ;\n wire \\rd_mux_sel_r_reg[1]_16 ;\n wire \\rd_mux_sel_r_reg[1]_17 ;\n wire \\rd_mux_sel_r_reg[1]_18 ;\n wire \\rd_mux_sel_r_reg[1]_19 ;\n wire \\rd_mux_sel_r_reg[1]_2 ;\n wire \\rd_mux_sel_r_reg[1]_20 ;\n wire \\rd_mux_sel_r_reg[1]_21 ;\n wire \\rd_mux_sel_r_reg[1]_22 ;\n wire \\rd_mux_sel_r_reg[1]_23 ;\n wire \\rd_mux_sel_r_reg[1]_24 ;\n wire \\rd_mux_sel_r_reg[1]_25 ;\n wire \\rd_mux_sel_r_reg[1]_26 ;\n wire \\rd_mux_sel_r_reg[1]_27 ;\n wire \\rd_mux_sel_r_reg[1]_28 ;\n wire \\rd_mux_sel_r_reg[1]_29 ;\n wire \\rd_mux_sel_r_reg[1]_3 ;\n wire \\rd_mux_sel_r_reg[1]_30 ;\n wire \\rd_mux_sel_r_reg[1]_31 ;\n wire \\rd_mux_sel_r_reg[1]_32 ;\n wire \\rd_mux_sel_r_reg[1]_33 ;\n wire \\rd_mux_sel_r_reg[1]_34 ;\n wire \\rd_mux_sel_r_reg[1]_35 ;\n wire \\rd_mux_sel_r_reg[1]_36 ;\n wire \\rd_mux_sel_r_reg[1]_37 ;\n wire \\rd_mux_sel_r_reg[1]_38 ;\n wire \\rd_mux_sel_r_reg[1]_39 ;\n wire \\rd_mux_sel_r_reg[1]_4 ;\n wire \\rd_mux_sel_r_reg[1]_40 ;\n wire \\rd_mux_sel_r_reg[1]_41 ;\n wire \\rd_mux_sel_r_reg[1]_42 ;\n wire \\rd_mux_sel_r_reg[1]_43 ;\n wire \\rd_mux_sel_r_reg[1]_44 ;\n wire \\rd_mux_sel_r_reg[1]_45 ;\n wire \\rd_mux_sel_r_reg[1]_46 ;\n wire \\rd_mux_sel_r_reg[1]_47 ;\n wire \\rd_mux_sel_r_reg[1]_48 ;\n wire \\rd_mux_sel_r_reg[1]_49 ;\n wire \\rd_mux_sel_r_reg[1]_5 ;\n wire \\rd_mux_sel_r_reg[1]_50 ;\n wire \\rd_mux_sel_r_reg[1]_51 ;\n wire \\rd_mux_sel_r_reg[1]_52 ;\n wire \\rd_mux_sel_r_reg[1]_53 ;\n wire \\rd_mux_sel_r_reg[1]_54 ;\n wire \\rd_mux_sel_r_reg[1]_55 ;\n wire \\rd_mux_sel_r_reg[1]_56 ;\n wire \\rd_mux_sel_r_reg[1]_57 ;\n wire \\rd_mux_sel_r_reg[1]_58 ;\n wire \\rd_mux_sel_r_reg[1]_59 ;\n wire \\rd_mux_sel_r_reg[1]_6 ;\n wire \\rd_mux_sel_r_reg[1]_60 ;\n wire \\rd_mux_sel_r_reg[1]_61 ;\n wire \\rd_mux_sel_r_reg[1]_62 ;\n wire \\rd_mux_sel_r_reg[1]_7 ;\n wire \\rd_mux_sel_r_reg[1]_8 ;\n wire \\rd_mux_sel_r_reg[1]_9 ;\n wire [37:0]\\rd_ptr_reg[3] ;\n wire [11:0]\\rd_ptr_reg[3]_0 ;\n wire [31:0]\\rd_ptr_reg[3]_1 ;\n wire [63:0]\\rd_ptr_reg[3]_2 ;\n wire [63:0]\\rd_ptr_reg[3]_3 ;\n wire [63:0]\\rd_ptr_reg[3]_4 ;\n wire [63:0]\\rd_ptr_reg[3]_5 ;\n wire \\rd_ptr_timing_reg[0] ;\n wire [33:0]\\rd_ptr_timing_reg[0]_0 ;\n wire [7:0]\\rd_ptr_timing_reg[0]_1 ;\n wire [7:0]\\rd_ptr_timing_reg[0]_2 ;\n wire [3:0]\\rd_ptr_timing_reg[0]_3 ;\n wire [1:0]\\rd_ptr_timing_reg[0]_4 ;\n wire [1:0]\\rdlvl_dqs_tap_cnt_r_reg[0][3][0] ;\n wire rdlvl_last_byte_done;\n wire rdlvl_last_byte_done_int_i_1_n_0;\n wire rdlvl_pi_incdec;\n wire rdlvl_pi_incdec_i_1_n_0;\n wire rdlvl_prech_req;\n wire rdlvl_rank_done_r_i_1_n_0;\n wire [14:14]rdlvl_start_dly0_r;\n wire rdlvl_start_pre;\n wire rdlvl_start_pre_i_1_n_0;\n wire rdlvl_stg1_done_int;\n wire rdlvl_stg1_done_int_i_1_n_0;\n wire rdlvl_stg1_rank_done;\n wire rdlvl_stg1_start_i_1_n_0;\n wire rdlvl_stg1_start_int;\n wire [2:2]regl_dqs_cnt;\n wire reset_if;\n wire reset_if_r8_reg_srl8_n_0;\n wire reset_if_r9;\n wire reset_rd_addr;\n wire reset_rd_addr0;\n wire reset_rd_addr_i_1_n_0;\n wire right_edge_found;\n wire right_edge_found_i_1_n_0;\n wire right_gain_pb;\n wire \\row_cnt_victim_rotate.complex_row_cnt_reg[4] ;\n wire rst_dqs_find;\n wire rst_dqs_find_i_1_n_0;\n wire rstdiv0_sync_r1_reg_rep;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__10;\n wire [0:0]rstdiv0_sync_r1_reg_rep__11;\n wire rstdiv0_sync_r1_reg_rep__12;\n wire rstdiv0_sync_r1_reg_rep__13;\n wire [1:0]rstdiv0_sync_r1_reg_rep__14;\n wire [0:0]rstdiv0_sync_r1_reg_rep__16;\n wire [0:0]rstdiv0_sync_r1_reg_rep__17;\n wire [0:0]rstdiv0_sync_r1_reg_rep__18;\n wire [0:0]rstdiv0_sync_r1_reg_rep__19;\n wire rstdiv0_sync_r1_reg_rep__2;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__23;\n wire rstdiv0_sync_r1_reg_rep__24;\n wire rstdiv0_sync_r1_reg_rep__24_0;\n wire rstdiv0_sync_r1_reg_rep__24_1;\n wire rstdiv0_sync_r1_reg_rep__25;\n wire rstdiv0_sync_r1_reg_rep__26;\n wire rstdiv0_sync_r1_reg_rep__26_0;\n wire rstdiv0_sync_r1_reg_rep__26_1;\n wire rstdiv0_sync_r1_reg_rep__26_2;\n wire rstdiv0_sync_r1_reg_rep__4;\n wire [0:0]rstdiv0_sync_r1_reg_rep__5;\n wire rstdiv0_sync_r1_reg_rep__6;\n wire rstdiv0_sync_r1_reg_rep__7;\n wire rstdiv0_sync_r1_reg_rep__8;\n wire rstdiv0_sync_r1_reg_rep__9;\n wire samp_edge_cnt0_en_r;\n wire samp_edge_cnt0_en_r_reg;\n wire samples_cnt_r;\n wire \\samps_r_reg[9] ;\n wire sel;\n wire sent_col;\n wire \\sm_r_reg[0] ;\n wire [0:0]\\sm_r_reg[0]_0 ;\n wire sr_valid_r108_out;\n wire stable_cnt1;\n wire stable_cnt227_in;\n wire stg1_wr_done;\n wire \\stg2_tap_cnt_reg[0] ;\n wire stg3_dec2init_val_r_reg;\n wire stg3_inc2init_val_r_reg;\n wire \\stg3_r_reg[0] ;\n wire store_sr_r_i_1_n_0;\n wire temp_lmr_done;\n wire tempmon_pi_f_en_r;\n wire tempmon_pi_f_inc;\n wire tempmon_pi_f_inc_r;\n wire tempmon_sample_en;\n wire tempmon_sel_pi_incdec;\n wire u_ddr_phy_init_n_101;\n wire u_ddr_phy_init_n_102;\n wire u_ddr_phy_init_n_104;\n wire u_ddr_phy_init_n_105;\n wire u_ddr_phy_init_n_106;\n wire u_ddr_phy_init_n_107;\n wire u_ddr_phy_init_n_108;\n wire u_ddr_phy_init_n_109;\n wire u_ddr_phy_init_n_110;\n wire u_ddr_phy_init_n_111;\n wire u_ddr_phy_init_n_114;\n wire u_ddr_phy_init_n_115;\n wire u_ddr_phy_init_n_116;\n wire u_ddr_phy_init_n_117;\n wire u_ddr_phy_init_n_120;\n wire u_ddr_phy_init_n_121;\n wire u_ddr_phy_init_n_122;\n wire u_ddr_phy_init_n_123;\n wire u_ddr_phy_init_n_124;\n wire u_ddr_phy_init_n_125;\n wire u_ddr_phy_init_n_126;\n wire u_ddr_phy_init_n_127;\n wire u_ddr_phy_init_n_18;\n wire u_ddr_phy_init_n_24;\n wire u_ddr_phy_init_n_29;\n wire u_ddr_phy_init_n_31;\n wire u_ddr_phy_init_n_33;\n wire u_ddr_phy_init_n_462;\n wire u_ddr_phy_init_n_464;\n wire u_ddr_phy_init_n_465;\n wire u_ddr_phy_init_n_468;\n wire u_ddr_phy_init_n_469;\n wire u_ddr_phy_init_n_470;\n wire u_ddr_phy_init_n_473;\n wire u_ddr_phy_init_n_474;\n wire u_ddr_phy_init_n_475;\n wire u_ddr_phy_init_n_476;\n wire u_ddr_phy_init_n_477;\n wire u_ddr_phy_init_n_478;\n wire u_ddr_phy_init_n_479;\n wire u_ddr_phy_init_n_480;\n wire u_ddr_phy_init_n_485;\n wire u_ddr_phy_init_n_490;\n wire u_ddr_phy_init_n_496;\n wire u_ddr_phy_init_n_497;\n wire u_ddr_phy_init_n_499;\n wire u_ddr_phy_init_n_500;\n wire u_ddr_phy_init_n_501;\n wire u_ddr_phy_init_n_502;\n wire u_ddr_phy_init_n_784;\n wire u_ddr_phy_init_n_785;\n wire u_ddr_phy_init_n_786;\n wire u_ddr_phy_init_n_790;\n wire u_ddr_phy_init_n_791;\n wire u_ddr_phy_init_n_9;\n wire u_ddr_phy_wrcal_n_100;\n wire u_ddr_phy_wrcal_n_101;\n wire u_ddr_phy_wrcal_n_102;\n wire u_ddr_phy_wrcal_n_103;\n wire u_ddr_phy_wrcal_n_104;\n wire u_ddr_phy_wrcal_n_105;\n wire u_ddr_phy_wrcal_n_106;\n wire u_ddr_phy_wrcal_n_107;\n wire u_ddr_phy_wrcal_n_108;\n wire u_ddr_phy_wrcal_n_109;\n wire u_ddr_phy_wrcal_n_110;\n wire u_ddr_phy_wrcal_n_111;\n wire u_ddr_phy_wrcal_n_112;\n wire u_ddr_phy_wrcal_n_113;\n wire u_ddr_phy_wrcal_n_114;\n wire u_ddr_phy_wrcal_n_115;\n wire u_ddr_phy_wrcal_n_116;\n wire u_ddr_phy_wrcal_n_117;\n wire u_ddr_phy_wrcal_n_118;\n wire u_ddr_phy_wrcal_n_119;\n wire u_ddr_phy_wrcal_n_120;\n wire u_ddr_phy_wrcal_n_4;\n wire u_ddr_phy_wrcal_n_5;\n wire u_ddr_phy_wrcal_n_66;\n wire u_ddr_phy_wrcal_n_67;\n wire u_ddr_phy_wrcal_n_69;\n wire u_ddr_phy_wrcal_n_71;\n wire u_ddr_phy_wrcal_n_73;\n wire u_ddr_phy_wrcal_n_74;\n wire u_ddr_phy_wrcal_n_81;\n wire u_ddr_phy_wrcal_n_82;\n wire u_ddr_phy_wrcal_n_83;\n wire u_ddr_phy_wrcal_n_84;\n wire u_ddr_phy_wrcal_n_85;\n wire u_ddr_phy_wrcal_n_89;\n wire u_ddr_phy_wrcal_n_90;\n wire u_ddr_phy_wrcal_n_91;\n wire u_ddr_phy_wrcal_n_92;\n wire u_ddr_phy_wrcal_n_93;\n wire u_ddr_phy_wrcal_n_94;\n wire u_ddr_phy_wrcal_n_95;\n wire u_ddr_phy_wrcal_n_96;\n wire u_ddr_phy_wrcal_n_97;\n wire u_ddr_phy_wrcal_n_98;\n wire u_ddr_prbs_gen_n_0;\n wire u_ddr_prbs_gen_n_1;\n wire u_ddr_prbs_gen_n_10;\n wire u_ddr_prbs_gen_n_100;\n wire u_ddr_prbs_gen_n_101;\n wire u_ddr_prbs_gen_n_102;\n wire u_ddr_prbs_gen_n_103;\n wire u_ddr_prbs_gen_n_104;\n wire u_ddr_prbs_gen_n_105;\n wire u_ddr_prbs_gen_n_106;\n wire u_ddr_prbs_gen_n_107;\n wire u_ddr_prbs_gen_n_108;\n wire u_ddr_prbs_gen_n_109;\n wire u_ddr_prbs_gen_n_11;\n wire u_ddr_prbs_gen_n_110;\n wire u_ddr_prbs_gen_n_111;\n wire u_ddr_prbs_gen_n_112;\n wire u_ddr_prbs_gen_n_113;\n wire u_ddr_prbs_gen_n_114;\n wire u_ddr_prbs_gen_n_115;\n wire u_ddr_prbs_gen_n_116;\n wire u_ddr_prbs_gen_n_117;\n wire u_ddr_prbs_gen_n_118;\n wire u_ddr_prbs_gen_n_119;\n wire u_ddr_prbs_gen_n_12;\n wire u_ddr_prbs_gen_n_120;\n wire u_ddr_prbs_gen_n_121;\n wire u_ddr_prbs_gen_n_13;\n wire u_ddr_prbs_gen_n_14;\n wire u_ddr_prbs_gen_n_15;\n wire u_ddr_prbs_gen_n_16;\n wire u_ddr_prbs_gen_n_17;\n wire u_ddr_prbs_gen_n_18;\n wire u_ddr_prbs_gen_n_19;\n wire u_ddr_prbs_gen_n_2;\n wire u_ddr_prbs_gen_n_20;\n wire u_ddr_prbs_gen_n_21;\n wire u_ddr_prbs_gen_n_22;\n wire u_ddr_prbs_gen_n_23;\n wire u_ddr_prbs_gen_n_24;\n wire u_ddr_prbs_gen_n_25;\n wire u_ddr_prbs_gen_n_26;\n wire u_ddr_prbs_gen_n_27;\n wire u_ddr_prbs_gen_n_28;\n wire u_ddr_prbs_gen_n_29;\n wire u_ddr_prbs_gen_n_3;\n wire u_ddr_prbs_gen_n_30;\n wire u_ddr_prbs_gen_n_31;\n wire u_ddr_prbs_gen_n_32;\n wire u_ddr_prbs_gen_n_33;\n wire u_ddr_prbs_gen_n_34;\n wire u_ddr_prbs_gen_n_35;\n wire u_ddr_prbs_gen_n_36;\n wire u_ddr_prbs_gen_n_37;\n wire u_ddr_prbs_gen_n_38;\n wire u_ddr_prbs_gen_n_39;\n wire u_ddr_prbs_gen_n_4;\n wire u_ddr_prbs_gen_n_40;\n wire u_ddr_prbs_gen_n_41;\n wire u_ddr_prbs_gen_n_42;\n wire u_ddr_prbs_gen_n_43;\n wire u_ddr_prbs_gen_n_44;\n wire u_ddr_prbs_gen_n_45;\n wire u_ddr_prbs_gen_n_46;\n wire u_ddr_prbs_gen_n_47;\n wire u_ddr_prbs_gen_n_48;\n wire u_ddr_prbs_gen_n_49;\n wire u_ddr_prbs_gen_n_5;\n wire u_ddr_prbs_gen_n_50;\n wire u_ddr_prbs_gen_n_51;\n wire u_ddr_prbs_gen_n_52;\n wire u_ddr_prbs_gen_n_53;\n wire u_ddr_prbs_gen_n_54;\n wire u_ddr_prbs_gen_n_55;\n wire u_ddr_prbs_gen_n_56;\n wire u_ddr_prbs_gen_n_57;\n wire u_ddr_prbs_gen_n_58;\n wire u_ddr_prbs_gen_n_59;\n wire u_ddr_prbs_gen_n_6;\n wire u_ddr_prbs_gen_n_60;\n wire u_ddr_prbs_gen_n_61;\n wire u_ddr_prbs_gen_n_62;\n wire u_ddr_prbs_gen_n_63;\n wire u_ddr_prbs_gen_n_64;\n wire u_ddr_prbs_gen_n_65;\n wire u_ddr_prbs_gen_n_66;\n wire u_ddr_prbs_gen_n_67;\n wire u_ddr_prbs_gen_n_68;\n wire u_ddr_prbs_gen_n_69;\n wire u_ddr_prbs_gen_n_7;\n wire u_ddr_prbs_gen_n_70;\n wire u_ddr_prbs_gen_n_71;\n wire u_ddr_prbs_gen_n_72;\n wire u_ddr_prbs_gen_n_73;\n wire u_ddr_prbs_gen_n_74;\n wire u_ddr_prbs_gen_n_75;\n wire u_ddr_prbs_gen_n_76;\n wire u_ddr_prbs_gen_n_77;\n wire u_ddr_prbs_gen_n_78;\n wire u_ddr_prbs_gen_n_79;\n wire u_ddr_prbs_gen_n_8;\n wire u_ddr_prbs_gen_n_80;\n wire u_ddr_prbs_gen_n_81;\n wire u_ddr_prbs_gen_n_82;\n wire u_ddr_prbs_gen_n_83;\n wire u_ddr_prbs_gen_n_84;\n wire u_ddr_prbs_gen_n_85;\n wire u_ddr_prbs_gen_n_86;\n wire u_ddr_prbs_gen_n_87;\n wire u_ddr_prbs_gen_n_88;\n wire u_ddr_prbs_gen_n_89;\n wire u_ddr_prbs_gen_n_9;\n wire u_ddr_prbs_gen_n_90;\n wire u_ddr_prbs_gen_n_91;\n wire u_ddr_prbs_gen_n_92;\n wire u_ddr_prbs_gen_n_93;\n wire u_ddr_prbs_gen_n_94;\n wire u_ddr_prbs_gen_n_95;\n wire u_ddr_prbs_gen_n_96;\n wire u_ddr_prbs_gen_n_97;\n wire u_ddr_prbs_gen_n_98;\n wire u_ddr_prbs_gen_n_99;\n wire [2:0]\\u_ocd_lim/stg2_tap_cnt_reg ;\n wire [2:0]\\u_ocd_lim/stg3_dec_val00_out ;\n wire [2:0]\\u_ocd_lim/stg3_init_val ;\n wire [8:2]\\u_ocd_po_cntlr/stg2_target_ns ;\n wire [1:0]wait_cnt_r_reg__0;\n wire [0:0]wait_cnt_r_reg__0_1;\n wire wl_edge_detect_valid_r_i_1_n_0;\n wire [0:0]wl_po_fine_cnt_sel_0;\n wire [2:1]wl_po_fine_cnt_sel_0__0;\n wire wl_sm_start;\n wire wr_level_done_i_1_n_0;\n wire wr_level_done_r_i_1_n_0;\n wire wrcal_pat_resume_r;\n wire wrcal_pat_resume_r_i_1_n_0;\n wire wrcal_prech_req;\n wire wrcal_rd_wait;\n wire wrcal_resume_r;\n wire wrcal_resume_w;\n wire wrcal_sanity_chk;\n wire wrcal_sanity_chk_done_i_1_n_0;\n wire wrlvl_byte_done;\n wire wrlvl_byte_redo;\n wire wrlvl_byte_redo_i_1_n_0;\n wire wrlvl_byte_redo_r;\n wire wrlvl_done_r1;\n wire wrlvl_final_if_rst;\n wire wrlvl_final_mux;\n wire wrlvl_final_r;\n wire wrlvl_rank_done;\n wire wrlvl_rank_done_r_i_1_n_0;\n wire [0:0]\\zero2fuzz_r_reg[0] ;\n\n assign A_1__s_port_ = A_1__s_net_1;\n (* SOFT_HLUTNM = \"soft_lutpair730\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\A[0]__0_i_1 \n (.I0(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]),\n .I1(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]),\n .I2(byte_sel_cnt),\n .O(\\A[0]__0 ));\n (* SOFT_HLUTNM = \"soft_lutpair729\" *) \n LUT3 #(\n .INIT(8'h20)) \n \\A[0]__4_i_1 \n (.I0(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]),\n .I1(byte_sel_cnt),\n .I2(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]),\n .O(\\A[0]__4 ));\n (* SOFT_HLUTNM = \"soft_lutpair729\" *) \n LUT3 #(\n .INIT(8'h02)) \n \\A[1]__0_i_1 \n (.I0(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]),\n .I1(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]),\n .I2(byte_sel_cnt),\n .O(\\A[1]__0 ));\n (* SOFT_HLUTNM = \"soft_lutpair733\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\A[1]__3_i_1 \n (.I0(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]),\n .I1(byte_sel_cnt),\n .O(\\A[1]__3 ));\n (* SOFT_HLUTNM = \"soft_lutpair728\" *) \n LUT3 #(\n .INIT(8'h02)) \n \\A[1]__4_i_1 \n (.I0(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]),\n .I1(byte_sel_cnt),\n .I2(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]),\n .O(\\A[1]__4_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair732\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\A[1]_i_1 \n (.I0(byte_sel_cnt),\n .I1(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]),\n .O(\\A[1]__4 ));\n (* SOFT_HLUTNM = \"soft_lutpair732\" *) \n LUT2 #(\n .INIT(4'h4)) \n \\A[1]_i_2 \n (.I0(byte_sel_cnt),\n .I1(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]),\n .O(A_1__s_net_1));\n (* SOFT_HLUTNM = \"soft_lutpair733\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\A[2]__1_i_1 \n (.I0(byte_sel_cnt),\n .O(\\A[2]__1 ));\n (* SOFT_HLUTNM = \"soft_lutpair730\" *) \n LUT3 #(\n .INIT(8'h07)) \n \\A[2]__2_i_1 \n (.I0(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]),\n .I1(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]),\n .I2(byte_sel_cnt),\n .O(\\A[2]__2 ));\n LUT5 #(\n .INIT(32'h000000AB)) \n burst_addr_r_i_1\n (.I0(u_ddr_phy_init_n_476),\n .I1(u_ddr_phy_init_n_31),\n .I2(u_ddr_phy_init_n_109),\n .I3(u_ddr_phy_wrcal_n_82),\n .I4(rstdiv0_sync_r1_reg_rep__24),\n .O(burst_addr_r_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair728\" *) \n LUT3 #(\n .INIT(8'h40)) \n \\byte_sel_data_map[1]_i_1 \n (.I0(byte_sel_cnt),\n .I1(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]),\n .I2(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]),\n .O(\\byte_sel_data_map_reg[1] ));\n LUT4 #(\n .INIT(16'hBFB0)) \n cal2_done_r_i_1\n (.I0(u_ddr_phy_wrcal_n_5),\n .I1(wrcal_sanity_chk),\n .I2(u_ddr_phy_wrcal_n_117),\n .I3(cal2_done_r),\n .O(cal2_done_r_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFFBABF00008A80)) \n cal2_if_reset_i_1\n (.I0(u_ddr_phy_wrcal_n_120),\n .I1(u_ddr_phy_wrcal_n_115),\n .I2(u_ddr_phy_wrcal_n_111),\n .I3(u_ddr_phy_wrcal_n_114),\n .I4(u_ddr_phy_wrcal_n_108),\n .I5(phy_if_reset_w),\n .O(cal2_if_reset_i_1_n_0));\n (* syn_maxfan = \"10\" *) \n FDRE \\calib_sel_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_104 ),\n .Q(\\po_rdval_cnt_reg[8] [0]),\n .R(1'b0));\n (* syn_maxfan = \"10\" *) \n FDRE \\calib_sel_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_103 ),\n .Q(\\po_rdval_cnt_reg[8] [1]),\n .R(1'b0));\n (* syn_maxfan = \"10\" *) \n FDRE \\calib_sel_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(ddr_phy_tempmon_0_n_3),\n .Q(\\po_rdval_cnt_reg[8] [2]),\n .R(1'b0));\n (* syn_maxfan = \"10\" *) \n FDRE \\calib_zero_inputs_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_105 ),\n .Q(calib_zero_inputs__0),\n .R(1'b0));\n (* syn_maxfan = \"10\" *) \n FDRE \\calib_zero_inputs_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(ddr_phy_tempmon_0_n_4),\n .Q(calib_zero_inputs),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hDFBF0820)) \n ck_po_stg2_f_en_i_1\n (.I0(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ),\n .I1(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_43 ),\n .I2(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_44 ),\n .I3(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_46 ),\n .I4(ck_po_stg2_f_en),\n .O(ck_po_stg2_f_en_i_1_n_0));\n LUT5 #(\n .INIT(32'hD7BF0020)) \n ck_po_stg2_f_indec_i_1\n (.I0(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ),\n .I1(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_43 ),\n .I2(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_44 ),\n .I3(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_46 ),\n .I4(ck_po_stg2_f_indec),\n .O(ck_po_stg2_f_indec_i_1_n_0));\n LUT4 #(\n .INIT(16'hEAAA)) \n cnt_dllk_zqinit_done_r_i_1\n (.I0(cnt_dllk_zqinit_done_r),\n .I1(cnt_dllk_zqinit_r_reg__0[6]),\n .I2(u_ddr_phy_init_n_496),\n .I3(cnt_dllk_zqinit_r_reg__0[7]),\n .O(cnt_dllk_zqinit_done_r_i_1_n_0));\n LUT6 #(\n .INIT(64'h00000000BA8A8A8A)) \n cnt_init_af_done_r_i_1\n (.I0(cnt_init_af_done_r),\n .I1(mem_init_done_r),\n .I2(u_ddr_phy_init_n_110),\n .I3(cnt_init_af_r[1]),\n .I4(cnt_init_af_r[0]),\n .I5(u_ddr_phy_init_n_115),\n .O(cnt_init_af_done_r_i_1_n_0));\n LUT6 #(\n .INIT(64'h000000000000E222)) \n cnt_init_mr_done_r_i_1\n (.I0(cnt_init_mr_done_r),\n .I1(temp_lmr_done),\n .I2(cnt_init_mr_r[0]),\n .I3(cnt_init_mr_r[1]),\n .I4(cnt_init_mr_r1),\n .I5(u_ddr_phy_init_n_115),\n .O(cnt_init_mr_done_r_i_1_n_0));\n LUT6 #(\n .INIT(64'h00000000AAAABAAA)) \n cnt_pwron_cke_done_r_i_1\n (.I0(cnt_pwron_cke_done_r),\n .I1(u_ddr_phy_init_n_490),\n .I2(cnt_pwron_r_reg__0[7]),\n .I3(cnt_pwron_r_reg__0[1]),\n .I4(cnt_pwron_r_reg__0[0]),\n .I5(cnt_pwron_reset_done_r0),\n .O(cnt_pwron_cke_done_r_i_1_n_0));\n LUT6 #(\n .INIT(64'h00000000FFFF0040)) \n cnt_pwron_reset_done_r_i_1\n (.I0(cnt_pwron_r_reg__0[7]),\n .I1(cnt_pwron_r_reg__0[5]),\n .I2(cnt_pwron_r_reg__0[0]),\n .I3(u_ddr_phy_init_n_485),\n .I4(cnt_pwron_reset_done_r),\n .I5(cnt_pwron_reset_done_r0),\n .O(cnt_pwron_reset_done_r_i_1_n_0));\n LUT5 #(\n .INIT(32'hBAAAAAAA)) \n cnt_txpr_done_r_i_1\n (.I0(cnt_txpr_done_r),\n .I1(u_ddr_phy_init_n_500),\n .I2(cnt_txpr_r_reg__0[2]),\n .I3(cnt_txpr_r_reg__0[0]),\n .I4(cnt_txpr_r_reg__0[1]),\n .O(cnt_txpr_done_r_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFB00000020)) \n complex_init_pi_dec_done_r_i_1\n (.I0(prbs_state_r[4]),\n .I1(prbs_state_r[3]),\n .I2(prbs_state_r[0]),\n .I3(prbs_state_r[2]),\n .I4(prbs_state_r[1]),\n .I5(complex_init_pi_dec_done),\n .O(complex_init_pi_dec_done_r_i_1_n_0));\n LUT6 #(\n .INIT(64'h4474FFFF44740000)) \n complex_pi_incdec_done_i_1\n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_109 ),\n .I1(prbs_state_r[0]),\n .I2(cnt_wait_state),\n .I3(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_107 ),\n .I4(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_105 ),\n .I5(complex_pi_incdec_done),\n .O(complex_pi_incdec_done_i_1_n_0));\n LUT4 #(\n .INIT(16'h00CE)) \n ddr2_pre_flag_r_i_1\n (.I0(u_ddr_phy_init_n_29),\n .I1(temp_lmr_done),\n .I2(u_ddr_phy_init_n_479),\n .I3(u_ddr_phy_init_n_115),\n .O(ddr2_pre_flag_r_i_1_n_0));\n LUT6 #(\n .INIT(64'h00000000FFFF70F0)) \n ddr2_refresh_flag_r_i_1\n (.I0(u_ddr_phy_init_n_480),\n .I1(cnt_cmd_done_r),\n .I2(ddr2_refresh_flag_r),\n .I3(cnt_init_mr_done_r),\n .I4(cnt_init_mr_r1),\n .I5(u_ddr_phy_init_n_115),\n .O(ddr2_refresh_flag_r_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair727\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/d_out \n (.I0(app_zq_r_reg),\n .I1(\\rd_ptr_reg[3]_0 [3]),\n .I2(\\my_empty_reg[1]_1 ),\n .O(\\my_full_reg[3] [3]));\n ddr3_if_mig_7series_v4_0_ddr_phy_prbs_rdlvl \\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl \n (.A(A),\n .\\A[0]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_9 ),\n .\\A[1]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_10 ),\n .\\A[1]_1 (\\A[1]_0 ),\n .\\A[1]_10 (\\A[1]_9 ),\n .\\A[1]_11 (\\A[1]_10 ),\n .\\A[1]_12 (\\A[1]_11 ),\n .\\A[1]_13 (\\A[1]_12 ),\n .\\A[1]_14 (\\A[1]_13 ),\n .\\A[1]_15 (\\A[1]_14 ),\n .\\A[1]_16 (\\A[1]_15 ),\n .\\A[1]_17 (\\A[1]_16 ),\n .\\A[1]_18 (\\A[1]_17 ),\n .\\A[1]_19 (\\A[1]_18 ),\n .\\A[1]_2 (\\A[1]_1 ),\n .\\A[1]_20 (\\A[1]_19 ),\n .\\A[1]_21 (\\A[1]_20 ),\n .\\A[1]_22 (\\A[1]_21 ),\n .\\A[1]_23 (\\A[1]_22 ),\n .\\A[1]_24 (\\A[1]_23 ),\n .\\A[1]_25 (\\A[1]_24 ),\n .\\A[1]_26 (\\A[1]_25 ),\n .\\A[1]_27 (\\A[1]_26 ),\n .\\A[1]_28 (\\A[1]_27 ),\n .\\A[1]_29 (\\A[1]_28 ),\n .\\A[1]_3 (\\A[1]_2 ),\n .\\A[1]_30 (\\A[1]_29 ),\n .\\A[1]_31 (\\A[1]_30 ),\n .\\A[1]_32 (\\A[1]_31 ),\n .\\A[1]_33 (\\A[1]_32 ),\n .\\A[1]_34 (\\A[1]_33 ),\n .\\A[1]_35 (\\A[1]_34 ),\n .\\A[1]_36 (\\A[1]_35 ),\n .\\A[1]_37 (\\A[1]_36 ),\n .\\A[1]_38 (\\A[1]_37 ),\n .\\A[1]_39 (\\A[1]_38 ),\n .\\A[1]_4 (\\A[1]_3 ),\n .\\A[1]_40 (\\A[1]_39 ),\n .\\A[1]_41 (\\A[1]_40 ),\n .\\A[1]_42 (\\A[1]_41 ),\n .\\A[1]_43 (\\A[1]_42 ),\n .\\A[1]_44 (\\A[1]_43 ),\n .\\A[1]_45 (\\A[1]_44 ),\n .\\A[1]_46 (\\A[1]_45 ),\n .\\A[1]_47 (\\A[1]_46 ),\n .\\A[1]_48 (\\A[1]_47 ),\n .\\A[1]_49 (\\A[1]_48 ),\n .\\A[1]_5 (\\A[1]_4 ),\n .\\A[1]_50 (\\A[1]_49 ),\n .\\A[1]_51 (\\A[1]_50 ),\n .\\A[1]_52 (\\A[1]_51 ),\n .\\A[1]_53 (\\A[1]_52 ),\n .\\A[1]_54 (\\A[1]_53 ),\n .\\A[1]_55 (\\A[1]_54 ),\n .\\A[1]_56 (\\A[1]_55 ),\n .\\A[1]_57 (\\A[1]_56 ),\n .\\A[1]_58 (\\A[1]_57 ),\n .\\A[1]_59 (\\A[1]_58 ),\n .\\A[1]_6 (\\A[1]_5 ),\n .\\A[1]_60 (\\A[1]_59 ),\n .\\A[1]_61 (\\A[1]_60 ),\n .\\A[1]_62 (\\A[1]_61 ),\n .\\A[1]_63 (\\A[1]_62 ),\n .\\A[1]_64 (\\A[1]_63 ),\n .\\A[1]_7 (\\A[1]_6 ),\n .\\A[1]_8 (\\A[1]_7 ),\n .\\A[1]_9 (\\A[1]_8 ),\n .\\A[2]__2 (\\A[2]__2_0 ),\n .CLK(CLK),\n .D(left_edge_updated),\n .E(samples_cnt_r),\n .Q(prbs_state_r),\n .bit_cnt(bit_cnt),\n .\\calib_sel_reg[3] (\\po_rdval_cnt_reg[8] [2]),\n .\\calib_sel_reg[3]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_94 ),\n .\\calib_sel_reg[3]_1 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_95 ),\n .\\calib_sel_reg[3]_2 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_93 ),\n .cnt_wait_state(cnt_wait_state),\n .compare_err_latch_reg_0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_109 ),\n .complex_act_start(complex_act_start),\n .complex_init_pi_dec_done(complex_init_pi_dec_done),\n .complex_ocal_reset_rd_addr(complex_ocal_reset_rd_addr),\n .complex_oclkdelay_calib_done_r1_reg(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_51 ),\n .complex_pi_incdec_done(complex_pi_incdec_done),\n .complex_pi_incdec_done_reg_0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_105 ),\n .complex_pi_incdec_done_reg_1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_107 ),\n .\\dec_cnt_reg[0]_0 (fine_dly_error_i_1_n_0),\n .\\dout_o_reg[0] (u_ddr_prbs_gen_n_114),\n .\\dout_o_reg[0]_0 (u_ddr_prbs_gen_n_115),\n .\\dout_o_reg[0]_1 (u_ddr_prbs_gen_n_116),\n .\\dout_o_reg[0]_2 (u_ddr_prbs_gen_n_117),\n .\\dout_o_reg[0]_3 (u_ddr_prbs_gen_n_118),\n .\\dout_o_reg[0]_4 (u_ddr_prbs_gen_n_119),\n .\\dout_o_reg[0]_5 (u_ddr_prbs_gen_n_120),\n .\\dout_o_reg[0]_6 (u_ddr_prbs_gen_n_121),\n .\\dout_o_reg[1] (u_ddr_prbs_gen_n_106),\n .\\dout_o_reg[1]_0 (u_ddr_prbs_gen_n_107),\n .\\dout_o_reg[1]_1 (u_ddr_prbs_gen_n_108),\n .\\dout_o_reg[1]_2 (u_ddr_prbs_gen_n_109),\n .\\dout_o_reg[1]_3 (u_ddr_prbs_gen_n_110),\n .\\dout_o_reg[1]_4 (u_ddr_prbs_gen_n_111),\n .\\dout_o_reg[1]_5 (u_ddr_prbs_gen_n_112),\n .\\dout_o_reg[1]_6 (u_ddr_prbs_gen_n_113),\n .\\dout_o_reg[2] (u_ddr_prbs_gen_n_98),\n .\\dout_o_reg[2]_0 (u_ddr_prbs_gen_n_99),\n .\\dout_o_reg[2]_1 (u_ddr_prbs_gen_n_100),\n .\\dout_o_reg[2]_2 (u_ddr_prbs_gen_n_101),\n .\\dout_o_reg[2]_3 (u_ddr_prbs_gen_n_102),\n .\\dout_o_reg[2]_4 (u_ddr_prbs_gen_n_103),\n .\\dout_o_reg[2]_5 (u_ddr_prbs_gen_n_104),\n .\\dout_o_reg[2]_6 (u_ddr_prbs_gen_n_105),\n .\\dout_o_reg[3] (u_ddr_prbs_gen_n_90),\n .\\dout_o_reg[3]_0 (u_ddr_prbs_gen_n_91),\n .\\dout_o_reg[3]_1 (u_ddr_prbs_gen_n_92),\n .\\dout_o_reg[3]_2 (u_ddr_prbs_gen_n_93),\n .\\dout_o_reg[3]_3 (u_ddr_prbs_gen_n_94),\n .\\dout_o_reg[3]_4 (u_ddr_prbs_gen_n_95),\n .\\dout_o_reg[3]_5 (u_ddr_prbs_gen_n_96),\n .\\dout_o_reg[3]_6 (u_ddr_prbs_gen_n_97),\n .\\dout_o_reg[4] (u_ddr_prbs_gen_n_82),\n .\\dout_o_reg[4]_0 (u_ddr_prbs_gen_n_83),\n .\\dout_o_reg[4]_1 (u_ddr_prbs_gen_n_84),\n .\\dout_o_reg[4]_2 (u_ddr_prbs_gen_n_85),\n .\\dout_o_reg[4]_3 (u_ddr_prbs_gen_n_86),\n .\\dout_o_reg[4]_4 (u_ddr_prbs_gen_n_87),\n .\\dout_o_reg[4]_5 (u_ddr_prbs_gen_n_88),\n .\\dout_o_reg[4]_6 (u_ddr_prbs_gen_n_89),\n .\\dout_o_reg[5] (u_ddr_prbs_gen_n_74),\n .\\dout_o_reg[5]_0 (u_ddr_prbs_gen_n_75),\n .\\dout_o_reg[5]_1 (u_ddr_prbs_gen_n_76),\n .\\dout_o_reg[5]_2 (u_ddr_prbs_gen_n_77),\n .\\dout_o_reg[5]_3 (u_ddr_prbs_gen_n_78),\n .\\dout_o_reg[5]_4 (u_ddr_prbs_gen_n_79),\n .\\dout_o_reg[5]_5 (u_ddr_prbs_gen_n_80),\n .\\dout_o_reg[5]_6 (u_ddr_prbs_gen_n_81),\n .\\dout_o_reg[6] (u_ddr_prbs_gen_n_66),\n .\\dout_o_reg[6]_0 (u_ddr_prbs_gen_n_67),\n .\\dout_o_reg[6]_1 (u_ddr_prbs_gen_n_68),\n .\\dout_o_reg[6]_2 (u_ddr_prbs_gen_n_69),\n .\\dout_o_reg[6]_3 (u_ddr_prbs_gen_n_70),\n .\\dout_o_reg[6]_4 (u_ddr_prbs_gen_n_71),\n .\\dout_o_reg[6]_5 (u_ddr_prbs_gen_n_72),\n .\\dout_o_reg[6]_6 (u_ddr_prbs_gen_n_73),\n .\\dout_o_reg[7] (u_ddr_prbs_gen_n_58),\n .\\dout_o_reg[7]_0 (u_ddr_prbs_gen_n_59),\n .\\dout_o_reg[7]_1 (u_ddr_prbs_gen_n_60),\n .\\dout_o_reg[7]_2 (u_ddr_prbs_gen_n_61),\n .\\dout_o_reg[7]_3 (u_ddr_prbs_gen_n_62),\n .\\dout_o_reg[7]_4 (u_ddr_prbs_gen_n_63),\n .\\dout_o_reg[7]_5 (u_ddr_prbs_gen_n_64),\n .\\dout_o_reg[7]_6 (u_ddr_prbs_gen_n_65),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 ),\n .dqs_found_done_r_reg(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_10 ),\n .\\fine_delay_mod_reg[20] (\\fine_delay_mod_reg[20] ),\n .\\fine_delay_mod_reg[26] (\\fine_delay_mod_reg[26] ),\n .\\fine_delay_mod_reg[5] (\\fine_delay_mod_reg[5] ),\n .fine_delay_sel_r_reg(fine_delay_sel_r_reg),\n .fine_delay_sel_reg_0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_102 ),\n .fine_delay_sel_reg_1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_104 ),\n .fine_dly_error_reg_0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_108 ),\n .fine_dly_error_reg_1(prbs_rdlvl_done_i_1_n_0),\n .\\genblk8[0].left_edge_found_pb_reg[0]_0 (\\genblk8[0].left_edge_found_pb[0]_i_1_n_0 ),\n .\\genblk8[0].left_edge_updated_reg[0]_0 (\\genblk8[0].left_edge_updated[0]_i_1_n_0 ),\n .\\genblk8[0].left_loss_pb_reg[0]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_15 ),\n .\\genblk8[0].left_loss_pb_reg[0]_1 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_69 ),\n .\\genblk8[0].right_edge_found_pb_reg[0]_0 (\\genblk8[0].right_edge_found_pb[0]_i_1_n_0 ),\n .\\genblk8[0].right_edge_pb_reg[0]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_23 ),\n .\\genblk8[0].right_edge_pb_reg[0]_1 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_68 ),\n .\\genblk8[1].left_edge_found_pb_reg[1]_0 (\\genblk8[1].left_edge_found_pb[1]_i_1_n_0 ),\n .\\genblk8[1].left_edge_updated_reg[1]_0 (\\genblk8[1].left_edge_updated[1]_i_1_n_0 ),\n .\\genblk8[1].left_loss_pb_reg[6]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_16 ),\n .\\genblk8[1].right_edge_found_pb_reg[1]_0 (\\genblk8[1].right_edge_found_pb[1]_i_1_n_0 ),\n .\\genblk8[1].right_edge_pb_reg[6]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_24 ),\n .\\genblk8[2].left_edge_found_pb_reg[2]_0 (\\genblk8[2].left_edge_found_pb[2]_i_1_n_0 ),\n .\\genblk8[2].left_edge_updated_reg[2]_0 (\\genblk8[2].left_edge_updated[2]_i_1_n_0 ),\n .\\genblk8[2].left_loss_pb_reg[12]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_17 ),\n .\\genblk8[2].right_edge_found_pb_reg[2]_0 (\\genblk8[2].right_edge_found_pb[2]_i_1_n_0 ),\n .\\genblk8[2].right_edge_pb_reg[12]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_25 ),\n .\\genblk8[2].right_edge_pb_reg[12]_1 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_64 ),\n .\\genblk8[2].right_edge_pb_reg[12]_2 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_65 ),\n .\\genblk8[3].left_edge_found_pb_reg[3]_0 (\\genblk8[3].left_edge_found_pb[3]_i_1_n_0 ),\n .\\genblk8[3].left_edge_updated_reg[3]_0 (\\genblk8[3].left_edge_updated[3]_i_1_n_0 ),\n .\\genblk8[3].left_loss_pb_reg[18]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_18 ),\n .\\genblk8[3].right_edge_found_pb_reg[3]_0 (\\genblk8[3].right_edge_found_pb[3]_i_1_n_0 ),\n .\\genblk8[3].right_edge_pb_reg[18]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_26 ),\n .\\genblk8[4].left_edge_found_pb_reg[4]_0 (\\genblk8[4].left_edge_found_pb[4]_i_1_n_0 ),\n .\\genblk8[4].left_edge_updated_reg[4]_0 (\\genblk8[4].left_edge_updated[4]_i_1_n_0 ),\n .\\genblk8[4].left_loss_pb_reg[24]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_19 ),\n .\\genblk8[4].right_edge_found_pb_reg[4]_0 (\\genblk8[4].right_edge_found_pb[4]_i_1_n_0 ),\n .\\genblk8[4].right_edge_pb_reg[24]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_27 ),\n .\\genblk8[5].left_edge_found_pb_reg[5]_0 (\\genblk8[5].left_edge_found_pb[5]_i_1_n_0 ),\n .\\genblk8[5].left_edge_updated_reg[5]_0 (\\genblk8[5].left_edge_updated[5]_i_1_n_0 ),\n .\\genblk8[5].left_loss_pb_reg[30]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_20 ),\n .\\genblk8[5].right_edge_found_pb_reg[5]_0 (\\genblk8[5].right_edge_found_pb[5]_i_1_n_0 ),\n .\\genblk8[5].right_edge_pb_reg[30]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_28 ),\n .\\genblk8[5].right_edge_pb_reg[30]_1 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_58 ),\n .\\genblk8[5].right_gain_pb_reg[30]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_59 ),\n .\\genblk8[6].left_edge_found_pb_reg[6]_0 (\\genblk8[6].left_edge_found_pb[6]_i_1_n_0 ),\n .\\genblk8[6].left_edge_updated_reg[6]_0 (\\genblk8[6].left_edge_updated[6]_i_1_n_0 ),\n .\\genblk8[6].left_loss_pb_reg[36]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_21 ),\n .\\genblk8[6].right_edge_found_pb_reg[6]_0 (\\genblk8[6].right_edge_found_pb[6]_i_1_n_0 ),\n .\\genblk8[6].right_edge_pb_reg[36]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_29 ),\n .\\genblk8[7].left_edge_found_pb_reg[7]_0 (\\genblk8[7].left_edge_found_pb[7]_i_1_n_0 ),\n .\\genblk8[7].left_edge_updated_reg[7]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ),\n .\\genblk8[7].left_edge_updated_reg[7]_1 (\\genblk8[7].left_edge_updated[7]_i_1_n_0 ),\n .\\genblk8[7].left_loss_pb_reg[42]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_22 ),\n .\\genblk8[7].right_edge_found_pb_reg[7]_0 (\\genblk8[7].right_edge_found_pb[7]_i_1_n_0 ),\n .\\genblk8[7].right_edge_pb_reg[42]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_30 ),\n .\\genblk8[7].right_edge_pb_reg[42]_1 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ),\n .\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_78 ),\n .\\genblk9[1].fine_delay_incdec_pb_reg[1]_0 (\\genblk9[1].fine_delay_incdec_pb_reg[1] ),\n .\\genblk9[2].fine_delay_incdec_pb_reg[2]_0 (\\genblk9[2].fine_delay_incdec_pb_reg[2] ),\n .\\genblk9[3].fine_delay_incdec_pb_reg[3]_0 (\\genblk9[3].fine_delay_incdec_pb_reg[3] ),\n .\\genblk9[5].fine_delay_incdec_pb_reg[5]_0 (\\genblk9[5].fine_delay_incdec_pb_reg[5] ),\n .\\genblk9[6].fine_delay_incdec_pb_reg[6]_0 (\\genblk9[6].fine_delay_incdec_pb_reg[6] ),\n .\\genblk9[7].fine_delay_incdec_pb_reg[7]_0 (\\genblk9[7].fine_delay_incdec_pb_reg[7] ),\n .\\init_state_r_reg[0] (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_87 ),\n .\\init_state_r_reg[0]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_89 ),\n .\\init_state_r_reg[1] (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_88 ),\n .\\init_state_r_reg[1]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_90 ),\n .\\largest_left_edge_reg[0]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_35 ),\n .\\match_flag_or_reg[0]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_34 ),\n .new_cnt_dqs_r(new_cnt_dqs_r),\n .new_cnt_dqs_r_reg_0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_113 ),\n .new_cnt_dqs_r_reg_1(prbs_dqs_tap_limit_r_i_1_n_0),\n .no_err_win_detected_latch_reg_0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_11 ),\n .no_err_win_detected_latch_reg_1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_103 ),\n .no_err_win_detected_reg_0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_98 ),\n .no_err_win_detected_reg_1(right_edge_found_i_1_n_0),\n .\\num_refresh_reg[1] (u_ddr_phy_init_n_117),\n .num_samples_done_ind_reg_0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_106 ),\n .num_samples_done_r(num_samples_done_r),\n .ocal_last_byte_done(ocal_last_byte_done),\n .oclkdelay_center_calib_done_r_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_4 ),\n .\\oclkdelay_ref_cnt_reg[0] (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_85 ),\n .\\one_rank.stg1_wr_done_reg (u_ddr_phy_init_n_116),\n .p_103_out(p_103_out),\n .p_106_out(p_106_out),\n .p_119_out(p_119_out),\n .p_122_out(p_122_out),\n .p_127_out(p_127_out),\n .p_130_out(p_130_out),\n .p_143_out(p_143_out),\n .p_146_out(p_146_out),\n .p_154_out(p_154_out),\n .p_95_out(p_95_out),\n .p_98_out(p_98_out),\n .\\pi_counter_read_val_reg[5] ({\\pi_counter_read_val_reg[5] [5],\\pi_counter_read_val_reg[5] [3],\\pi_counter_read_val_reg[5] [1:0]}),\n .pi_en_stg2_f_timing_reg_0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_4 ),\n .\\prbs_dec_tap_cnt_reg[1]_0 ({dec_cnt_reg[5],dec_cnt_reg[0]}),\n .\\prbs_dqs_cnt_r_reg[0]_0 (\\prbs_dqs_cnt_r[1]_i_1_n_0 ),\n .\\prbs_dqs_cnt_r_reg[0]_1 (\\prbs_dqs_cnt_r[0]_i_1_n_0 ),\n .\\prbs_dqs_cnt_r_reg[0]_2 (\\prbs_dqs_cnt_r[2]_i_1_n_0 ),\n .\\prbs_dqs_cnt_r_reg[1]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_110 ),\n .\\prbs_dqs_cnt_r_reg[2]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_50 ),\n .prbs_found_1st_edge_r_reg_0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_14 ),\n .prbs_found_1st_edge_r_reg_1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_99 ),\n .prbs_last_byte_done(prbs_last_byte_done),\n .prbs_last_byte_done_reg_0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_112 ),\n .prbs_pi_stg2_f_en(prbs_pi_stg2_f_en),\n .prbs_pi_stg2_f_incdec(prbs_pi_stg2_f_incdec),\n .prbs_prech_req_r(prbs_prech_req_r),\n .prbs_rdlvl_done_pulse0(prbs_rdlvl_done_pulse0),\n .prbs_rdlvl_done_r1(prbs_rdlvl_done_r1),\n .prbs_rdlvl_done_reg_0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_44 ),\n .prbs_rdlvl_done_reg_1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_111 ),\n .prbs_rdlvl_start_r(prbs_rdlvl_start_r),\n .prbs_rdlvl_start_reg(prbs_rdlvl_start_r_reg),\n .prbs_rdlvl_start_reg_0(u_ddr_phy_init_n_127),\n .prbs_state_r178_out(prbs_state_r178_out),\n .\\prbs_state_r_reg[0]_0 (fine_delay_sel_i_1_n_0),\n .\\prbs_state_r_reg[0]_1 (prbs_tap_inc_r_i_1_n_0),\n .\\prbs_state_r_reg[0]_2 (prbs_tap_en_r_i_1_n_0),\n .\\prbs_state_r_reg[0]_3 (prbs_last_byte_done_i_1_n_0),\n .\\prbs_state_r_reg[0]_4 (complex_pi_incdec_done_i_1_n_0),\n .\\prbs_state_r_reg[3]_0 (prbs_found_1st_edge_r_i_1_n_0),\n .\\prbs_state_r_reg[3]_1 (no_err_win_detected_latch_i_1_n_0),\n .\\prbs_state_r_reg[4]_0 (new_cnt_dqs_r_i_1_n_0),\n .\\prbs_state_r_reg[4]_1 (num_samples_done_ind_i_1_n_0),\n .\\prbs_state_r_reg[4]_2 (reset_rd_addr_i_1_n_0),\n .\\prbs_state_r_reg[4]_3 (complex_init_pi_dec_done_r_i_1_n_0),\n .prbs_tap_en_r(prbs_tap_en_r),\n .prbs_tap_en_r_reg_0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_100 ),\n .prbs_tap_inc_r(prbs_tap_inc_r),\n .prbs_tap_inc_r_reg_0(pi_stg2_f_incdec_timing_i_1_n_0),\n .prech_done(prech_done),\n .prech_done_reg(prbs_prech_req_r_i_1_n_0),\n .prech_req_r_reg(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_2 ),\n .\\rd_victim_sel_reg[2]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_84 ),\n .\\rd_victim_sel_reg[2]_1 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_115 ),\n .\\rd_victim_sel_reg[2]_2 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_116 ),\n .\\rd_victim_sel_reg[2]_3 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_117 ),\n .\\rdlvl_cpt_tap_cnt_reg[5]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_13 ),\n .\\rdlvl_cpt_tap_cnt_reg[5]_1 ({\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_93 ,\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_94 ,\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_95 }),\n .rdlvl_last_byte_done(rdlvl_last_byte_done),\n .rdlvl_stg1_done_int_reg(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_56 ),\n .rdlvl_stg1_start_int(rdlvl_stg1_start_int),\n .reset_rd_addr(reset_rd_addr),\n .reset_rd_addr0(reset_rd_addr0),\n .right_edge_found(right_edge_found),\n .right_edge_found_reg_0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_32 ),\n .right_edge_found_reg_1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_79 ),\n .right_gain_pb(right_gain_pb),\n .\\row_cnt_victim_rotate.complex_row_cnt_reg[4] (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_1 ),\n .rstdiv0_sync_r1_reg_rep(rstdiv0_sync_r1_reg_rep),\n .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2),\n .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23),\n .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),\n .rstdiv0_sync_r1_reg_rep__7(rstdiv0_sync_r1_reg_rep__7),\n .rstdiv0_sync_r1_reg_rep__8(rstdiv0_sync_r1_reg_rep__8),\n .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9),\n .\\stage_cnt_reg[1]_0 (\\genblk9[0].fine_delay_incdec_pb[0]_i_7_n_0 ),\n .\\stg1_wr_rd_cnt_reg[3] (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_45 ),\n .wrcal_done_reg(u_ddr_phy_wrcal_n_82),\n .wrlvl_final_mux(wrlvl_final_mux));\n ddr3_if_mig_7series_v4_0_ddr_phy_rdlvl \\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl \n (.CLK(CLK),\n .COUNTERLOADVAL(COUNTERLOADVAL),\n .D({\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_155 ,\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_156 }),\n .E(u_ddr_phy_init_n_465),\n .\\FSM_sequential_cal1_state_r_reg[1]_0 (rdlvl_pi_incdec_i_1_n_0),\n .\\FSM_sequential_cal1_state_r_reg[2]_0 (idel_adj_inc_i_1_n_0),\n .\\FSM_sequential_cal1_state_r_reg[3]_0 (mpr_dec_cpt_r_i_1_n_0),\n .\\FSM_sequential_cal1_state_r_reg[4]_0 (idel_pat_detect_valid_r_i_1_n_0),\n .\\FSM_sequential_cal1_state_r_reg[4]_1 (mpr_last_byte_done_i_1_n_0),\n .\\FSM_sequential_cal1_state_r_reg[4]_2 (mpr_rank_done_r_i_1_n_0),\n .\\FSM_sequential_cal1_state_r_reg[4]_3 (rdlvl_rank_done_r_i_1_n_0),\n .\\FSM_sequential_cal1_state_r_reg[4]_4 (rdlvl_last_byte_done_int_i_1_n_0),\n .Q(calib_zero_inputs__0),\n .SR(SR),\n .cal1_cnt_cpt_r1(cal1_cnt_cpt_r1),\n .cal1_dq_idel_ce_reg_0(u_ddr_phy_wrcal_n_89),\n .cal1_state_r1535_out(cal1_state_r1535_out),\n .cal1_wait_r(cal1_wait_r),\n .calib_in_common(calib_in_common),\n .\\calib_sel_reg[3] (\\po_rdval_cnt_reg[8] ),\n .\\calib_sel_reg[3]_0 ({\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_93 ,\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_94 ,\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_95 }),\n .cmd_delay_start0(cmd_delay_start0),\n .\\cnt_idel_dec_cpt_r_reg[0]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_60 ),\n .cnt_init_af_done_r(cnt_init_af_done_r),\n .complex_ocal_ref_req(complex_ocal_ref_req),\n .detect_edge_done_r(detect_edge_done_r),\n .\\dout_o_reg[6] (u_ddr_prbs_gen_n_70),\n .\\dout_o_reg[6]_0 (u_ddr_prbs_gen_n_66),\n .dqs_found_done_r_reg(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_10 ),\n .dqs_found_done_r_reg_0(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_86 ),\n .dqs_found_prech_req(dqs_found_prech_req),\n .dqs_po_dec_done(dqs_po_dec_done),\n .dqs_po_dec_done_r2(dqs_po_dec_done_r2),\n .first_wrcal_pat_r(first_wrcal_pat_r),\n .found_edge_r_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_40 ),\n .found_edge_r_reg_1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_41 ),\n .found_edge_r_reg_2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_42 ),\n .found_edge_r_reg_3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_44 ),\n .found_edge_r_reg_4(found_first_edge_r_i_1_n_0),\n .found_first_edge_r_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_4 ),\n .found_stable_eye_last_r(found_stable_eye_last_r),\n .found_stable_eye_last_r_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_3 ),\n .found_stable_eye_last_r_reg_1(found_second_edge_r_i_1_n_0),\n .found_stable_eye_r_reg_0(found_stable_eye_last_r_i_1_n_0),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[2] (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_158 ),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_159 ),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_157 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_0 (\\phaser_in_gen.phaser_in_i_12_n_0 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_1 (\\phaser_in_gen.phaser_in_i_12__0_n_0 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_2 (\\phaser_in_gen.phaser_in_i_12__1_n_0 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_3 (\\phaser_in_gen.phaser_in_i_12__2_n_0 ),\n .\\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_30 ),\n .\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg[0]_0 (\\gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1_n_0 ),\n .\\gen_track_left_edge[0].pb_detect_edge_done_r_reg[0]_0 (\\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1_n_0 ),\n .\\gen_track_left_edge[0].pb_found_edge_r_reg[0]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_39 ),\n .\\gen_track_left_edge[0].pb_found_edge_r_reg[0]_1 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_108 ),\n .\\gen_track_left_edge[0].pb_found_edge_r_reg[0]_2 (\\gen_track_left_edge[0].pb_found_edge_r[0]_i_1_n_0 ),\n .\\gen_track_left_edge[0].pb_found_stable_eye_r_reg (\\gen_track_left_edge[0].pb_found_stable_eye_r_reg ),\n .\\gen_track_left_edge[0].pb_found_stable_eye_r_reg[0]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_124 ),\n .\\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_9 ),\n .\\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_107 ),\n .\\gen_track_left_edge[1].pb_detect_edge_done_r_reg[1]_0 (\\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1_n_0 ),\n .\\gen_track_left_edge[1].pb_found_edge_r_reg[1]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_110 ),\n .\\gen_track_left_edge[1].pb_found_edge_r_reg[1]_1 (\\gen_track_left_edge[1].pb_found_edge_r[1]_i_1_n_0 ),\n .\\gen_track_left_edge[1].pb_found_stable_eye_r_reg (\\gen_track_left_edge[1].pb_found_stable_eye_r_reg ),\n .\\gen_track_left_edge[1].pb_found_stable_eye_r_reg[1]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_126 ),\n .\\gen_track_left_edge[2].pb_detect_edge_done_r_reg[2]_0 (\\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1_n_0 ),\n .\\gen_track_left_edge[2].pb_found_edge_r_reg[2]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_112 ),\n .\\gen_track_left_edge[2].pb_found_edge_r_reg[2]_1 (\\gen_track_left_edge[2].pb_found_edge_r[2]_i_1_n_0 ),\n .\\gen_track_left_edge[2].pb_found_stable_eye_r_reg (\\gen_track_left_edge[2].pb_found_stable_eye_r_reg ),\n .\\gen_track_left_edge[2].pb_found_stable_eye_r_reg[2]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_128 ),\n .\\gen_track_left_edge[3].pb_detect_edge_done_r_reg[3]_0 (\\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1_n_0 ),\n .\\gen_track_left_edge[3].pb_found_edge_r_reg[3]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_114 ),\n .\\gen_track_left_edge[3].pb_found_edge_r_reg[3]_1 (\\gen_track_left_edge[3].pb_found_edge_r[3]_i_1_n_0 ),\n .\\gen_track_left_edge[3].pb_found_stable_eye_r_reg (\\gen_track_left_edge[3].pb_found_stable_eye_r_reg ),\n .\\gen_track_left_edge[3].pb_found_stable_eye_r_reg[3]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_130 ),\n .\\gen_track_left_edge[4].pb_detect_edge_done_r_reg[4]_0 (\\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1_n_0 ),\n .\\gen_track_left_edge[4].pb_found_edge_r_reg[4]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_43 ),\n .\\gen_track_left_edge[4].pb_found_edge_r_reg[4]_1 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_116 ),\n .\\gen_track_left_edge[4].pb_found_edge_r_reg[4]_2 (\\gen_track_left_edge[4].pb_found_edge_r[4]_i_1_n_0 ),\n .\\gen_track_left_edge[4].pb_found_stable_eye_r_reg (\\gen_track_left_edge[4].pb_found_stable_eye_r_reg ),\n .\\gen_track_left_edge[4].pb_found_stable_eye_r_reg[4]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_132 ),\n .\\gen_track_left_edge[5].pb_detect_edge_done_r_reg[5]_0 (\\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1_n_0 ),\n .\\gen_track_left_edge[5].pb_found_edge_r_reg[5]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_118 ),\n .\\gen_track_left_edge[5].pb_found_edge_r_reg[5]_1 (\\gen_track_left_edge[5].pb_found_edge_r[5]_i_1_n_0 ),\n .\\gen_track_left_edge[5].pb_found_stable_eye_r_reg (\\gen_track_left_edge[5].pb_found_stable_eye_r_reg ),\n .\\gen_track_left_edge[5].pb_found_stable_eye_r_reg[5]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_134 ),\n .\\gen_track_left_edge[6].pb_detect_edge_done_r_reg[6]_0 (\\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1_n_0 ),\n .\\gen_track_left_edge[6].pb_found_edge_r_reg[6]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_45 ),\n .\\gen_track_left_edge[6].pb_found_edge_r_reg[6]_1 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_120 ),\n .\\gen_track_left_edge[6].pb_found_edge_r_reg[6]_2 (\\gen_track_left_edge[6].pb_found_edge_r[6]_i_1_n_0 ),\n .\\gen_track_left_edge[6].pb_found_stable_eye_r_reg (\\gen_track_left_edge[6].pb_found_stable_eye_r_reg ),\n .\\gen_track_left_edge[6].pb_found_stable_eye_r_reg[6]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_136 ),\n .\\gen_track_left_edge[7].pb_detect_edge_done_r_reg[7]_0 (\\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1_n_0 ),\n .\\gen_track_left_edge[7].pb_found_edge_r_reg[7]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_46 ),\n .\\gen_track_left_edge[7].pb_found_edge_r_reg[7]_1 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_122 ),\n .\\gen_track_left_edge[7].pb_found_edge_r_reg[7]_2 (\\gen_track_left_edge[7].pb_found_edge_r[7]_i_1_n_0 ),\n .\\gen_track_left_edge[7].pb_found_stable_eye_r_reg (\\gen_track_left_edge[7].pb_found_stable_eye_r_reg ),\n .\\gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_137 ),\n .\\gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_1 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_138 ),\n .\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ),\n .\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .idel_adj_inc_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_52 ),\n .idel_adj_inc_reg_1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_88 ),\n .idel_adj_inc_reg_2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_140 ),\n .\\idel_dec_cnt_reg[0]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_186 ),\n .idelay_ce_int(idelay_ce_int),\n .idelay_inc_int(idelay_inc_int),\n .\\init_state_r_reg[0] (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_80 ),\n .\\init_state_r_reg[0]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_81 ),\n .\\init_state_r_reg[0]_1 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_82 ),\n .\\init_state_r_reg[0]_2 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_148 ),\n .\\init_state_r_reg[0]_3 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_150 ),\n .\\init_state_r_reg[0]_4 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_152 ),\n .\\init_state_r_reg[1] (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_142 ),\n .\\init_state_r_reg[1]_0 ({u_ddr_phy_init_n_107,u_ddr_phy_init_n_108}),\n .\\init_state_r_reg[2] (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_144 ),\n .\\init_state_r_reg[2]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_145 ),\n .\\init_state_r_reg[2]_1 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_146 ),\n .\\init_state_r_reg[2]_2 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_154 ),\n .\\init_state_r_reg[3] (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_149 ),\n .\\init_state_r_reg[3]_0 (u_ddr_phy_init_n_111),\n .\\init_state_r_reg[4] (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_151 ),\n .\\init_state_r_reg[5] (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_147 ),\n .\\init_state_r_reg[5]_0 (u_ddr_phy_init_n_474),\n .mem_init_done_r(mem_init_done_r),\n .mpr_dec_cpt_r_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_51 ),\n .mpr_dec_cpt_r_reg_1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_190 ),\n .mpr_last_byte_done(mpr_last_byte_done),\n .mpr_last_byte_done_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_183 ),\n .mpr_rank_done_r_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_184 ),\n .mpr_rank_done_r_reg_1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_189 ),\n .mpr_rd_rise0_prev_r_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_50 ),\n .mpr_rd_rise0_prev_r_reg_1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_102 ),\n .mpr_rdlvl_done_r1_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ),\n .mpr_rdlvl_done_r_reg_0(mpr_rdlvl_done_r_i_1_n_0),\n .mpr_rdlvl_done_r_reg_1(rdlvl_stg1_done_int_i_1_n_0),\n .mpr_rdlvl_start_r(mpr_rdlvl_start_r),\n .mpr_rdlvl_start_reg(u_ddr_phy_init_n_464),\n .mpr_rnk_done(mpr_rnk_done),\n .mpr_valid_r1_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_6 ),\n .mpr_valid_r_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_106 ),\n .\\num_refresh_reg[1] (u_ddr_phy_init_n_117),\n .oclkdelay_calib_done_r_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ),\n .oclkdelay_center_calib_done_r_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_4 ),\n .\\one_rank.stg1_wr_done_reg (u_ddr_phy_init_n_116),\n .out({\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_83 ,\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_84 ,\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_85 ,\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_86 ,\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_87 }),\n .p_0_in(p_0_in),\n .p_0_in102_in(p_0_in102_in),\n .p_0_in10_in(p_0_in10_in),\n .p_0_in13_in(p_0_in13_in),\n .p_0_in16_in(p_0_in16_in),\n .p_0_in1_in(p_0_in1_in),\n .p_0_in4_in(p_0_in4_in),\n .p_0_in7_in(p_0_in7_in),\n .p_0_in84_in(p_0_in84_in),\n .p_0_in87_in(p_0_in87_in),\n .p_0_in90_in(p_0_in90_in),\n .p_0_in93_in(p_0_in93_in),\n .p_0_in96_in(p_0_in96_in),\n .p_0_in99_in(p_0_in99_in),\n .pb_detect_edge_done_r(pb_detect_edge_done_r),\n .pb_found_stable_eye_r52_out(pb_found_stable_eye_r52_out),\n .pb_found_stable_eye_r56_out(pb_found_stable_eye_r56_out),\n .pb_found_stable_eye_r60_out(pb_found_stable_eye_r60_out),\n .pb_found_stable_eye_r64_out(pb_found_stable_eye_r64_out),\n .pb_found_stable_eye_r68_out(pb_found_stable_eye_r68_out),\n .pb_found_stable_eye_r72_out(pb_found_stable_eye_r72_out),\n .pb_found_stable_eye_r76_out(pb_found_stable_eye_r76_out),\n .phy_rddata_en_1(phy_rddata_en_1),\n .pi_cnt_dec_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_141 ),\n .pi_cnt_dec_reg_1(pi_cnt_dec_reg),\n .\\pi_counter_read_val_reg[5] ({\\pi_counter_read_val_reg[5] [5:4],\\pi_counter_read_val_reg[5] [2:0]}),\n .\\pi_dqs_found_lanes_r1_reg[0] (\\pi_dqs_found_lanes_r1_reg[0]_0 ),\n .\\pi_dqs_found_lanes_r1_reg[0]_0 (\\pi_dqs_found_lanes_r1_reg[0]_1 ),\n .\\pi_dqs_found_lanes_r1_reg[0]_1 (\\pi_dqs_found_lanes_r1_reg[0]_2 ),\n .\\pi_dqs_found_lanes_r1_reg[1] (\\pi_dqs_found_lanes_r1_reg[1]_0 ),\n .\\pi_dqs_found_lanes_r1_reg[1]_0 (\\pi_dqs_found_lanes_r1_reg[1]_1 ),\n .\\pi_dqs_found_lanes_r1_reg[1]_1 (\\pi_dqs_found_lanes_r1_reg[1]_2 ),\n .\\pi_dqs_found_lanes_r1_reg[1]_2 (\\pi_dqs_found_lanes_r1_reg[1]_3 ),\n .\\pi_dqs_found_lanes_r1_reg[2] (\\pi_dqs_found_lanes_r1_reg[2]_0 ),\n .\\pi_dqs_found_lanes_r1_reg[2]_0 (\\pi_dqs_found_lanes_r1_reg[2]_1 ),\n .\\pi_dqs_found_lanes_r1_reg[2]_1 (\\pi_dqs_found_lanes_r1_reg[2]_2 ),\n .\\pi_dqs_found_lanes_r1_reg[2]_2 (\\pi_dqs_found_lanes_r1_reg[2]_3 ),\n .\\pi_dqs_found_lanes_r1_reg[3] (\\pi_dqs_found_lanes_r1_reg[3]_0 ),\n .\\pi_dqs_found_lanes_r1_reg[3]_0 (\\pi_dqs_found_lanes_r1_reg[3]_1 ),\n .\\pi_dqs_found_lanes_r1_reg[3]_1 (\\pi_dqs_found_lanes_r1_reg[3]_2 ),\n .\\pi_dqs_found_lanes_r1_reg[3]_2 (\\pi_dqs_found_lanes_r1_reg[3]_3 ),\n .pi_en_stg2_f_timing_reg_0(pi_en_stg2_f_timing_reg),\n .pi_fine_dly_dec_done(pi_fine_dly_dec_done),\n .\\pi_rdval_cnt_reg[1]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_96 ),\n .pi_stg2_rdlvl_cnt(pi_stg2_rdlvl_cnt),\n .\\pi_stg2_reg_l_timing_reg[0]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_99 ),\n .\\po_stg2_wrcal_cnt_reg[0] (u_ddr_phy_wrcal_n_85),\n .\\po_stg2_wrcal_cnt_reg[1] (\\idelay_tap_cnt_r_reg[0][3][0] [1]),\n .\\po_stg2_wrcal_cnt_reg[2] (u_ddr_phy_wrcal_n_107),\n .\\prbs_dqs_cnt_r_reg[2] (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_50 ),\n .prbs_last_byte_done_r(prbs_last_byte_done_r),\n .prbs_pi_stg2_f_en(prbs_pi_stg2_f_en),\n .prbs_pi_stg2_f_incdec(prbs_pi_stg2_f_incdec),\n .prbs_rdlvl_done_reg(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_45 ),\n .prbs_rdlvl_done_reg_rep(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_51 ),\n .prbs_rdlvl_done_reg_rep_0(u_ddr_phy_init_n_497),\n .prbs_rdlvl_done_reg_rep_1(u_ddr_phy_wrcal_n_94),\n .prbs_rdlvl_prech_req_reg(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_2 ),\n .prech_done(prech_done),\n .prech_req(prech_req),\n .\\rd_mux_sel_r_reg[1]_0 (\\rd_mux_sel_r_reg[1] ),\n .\\rd_mux_sel_r_reg[1]_1 (\\rd_mux_sel_r_reg[1]_0 ),\n .\\rd_mux_sel_r_reg[1]_10 (\\rd_mux_sel_r_reg[1]_9 ),\n .\\rd_mux_sel_r_reg[1]_11 (\\rd_mux_sel_r_reg[1]_10 ),\n .\\rd_mux_sel_r_reg[1]_12 (\\rd_mux_sel_r_reg[1]_11 ),\n .\\rd_mux_sel_r_reg[1]_13 (\\rd_mux_sel_r_reg[1]_12 ),\n .\\rd_mux_sel_r_reg[1]_14 (\\rd_mux_sel_r_reg[1]_13 ),\n .\\rd_mux_sel_r_reg[1]_15 (\\rd_mux_sel_r_reg[1]_14 ),\n .\\rd_mux_sel_r_reg[1]_16 (\\rd_mux_sel_r_reg[1]_15 ),\n .\\rd_mux_sel_r_reg[1]_17 (\\rd_mux_sel_r_reg[1]_16 ),\n .\\rd_mux_sel_r_reg[1]_18 (\\rd_mux_sel_r_reg[1]_17 ),\n .\\rd_mux_sel_r_reg[1]_19 (\\rd_mux_sel_r_reg[1]_18 ),\n .\\rd_mux_sel_r_reg[1]_2 (\\rd_mux_sel_r_reg[1]_1 ),\n .\\rd_mux_sel_r_reg[1]_20 (\\rd_mux_sel_r_reg[1]_19 ),\n .\\rd_mux_sel_r_reg[1]_21 (\\rd_mux_sel_r_reg[1]_20 ),\n .\\rd_mux_sel_r_reg[1]_22 (\\rd_mux_sel_r_reg[1]_21 ),\n .\\rd_mux_sel_r_reg[1]_23 (\\rd_mux_sel_r_reg[1]_22 ),\n .\\rd_mux_sel_r_reg[1]_24 (\\rd_mux_sel_r_reg[1]_23 ),\n .\\rd_mux_sel_r_reg[1]_25 (\\rd_mux_sel_r_reg[1]_24 ),\n .\\rd_mux_sel_r_reg[1]_26 (\\rd_mux_sel_r_reg[1]_25 ),\n .\\rd_mux_sel_r_reg[1]_27 (\\rd_mux_sel_r_reg[1]_26 ),\n .\\rd_mux_sel_r_reg[1]_28 (\\rd_mux_sel_r_reg[1]_27 ),\n .\\rd_mux_sel_r_reg[1]_29 (\\rd_mux_sel_r_reg[1]_28 ),\n .\\rd_mux_sel_r_reg[1]_3 (\\rd_mux_sel_r_reg[1]_2 ),\n .\\rd_mux_sel_r_reg[1]_30 (\\rd_mux_sel_r_reg[1]_29 ),\n .\\rd_mux_sel_r_reg[1]_31 (\\rd_mux_sel_r_reg[1]_30 ),\n .\\rd_mux_sel_r_reg[1]_32 (\\rd_mux_sel_r_reg[1]_31 ),\n .\\rd_mux_sel_r_reg[1]_33 (\\rd_mux_sel_r_reg[1]_32 ),\n .\\rd_mux_sel_r_reg[1]_34 (\\rd_mux_sel_r_reg[1]_33 ),\n .\\rd_mux_sel_r_reg[1]_35 (\\rd_mux_sel_r_reg[1]_34 ),\n .\\rd_mux_sel_r_reg[1]_36 (\\rd_mux_sel_r_reg[1]_35 ),\n .\\rd_mux_sel_r_reg[1]_37 (\\rd_mux_sel_r_reg[1]_36 ),\n .\\rd_mux_sel_r_reg[1]_38 (\\rd_mux_sel_r_reg[1]_37 ),\n .\\rd_mux_sel_r_reg[1]_39 (\\rd_mux_sel_r_reg[1]_38 ),\n .\\rd_mux_sel_r_reg[1]_4 (\\rd_mux_sel_r_reg[1]_3 ),\n .\\rd_mux_sel_r_reg[1]_40 (\\rd_mux_sel_r_reg[1]_39 ),\n .\\rd_mux_sel_r_reg[1]_41 (\\rd_mux_sel_r_reg[1]_40 ),\n .\\rd_mux_sel_r_reg[1]_42 (\\rd_mux_sel_r_reg[1]_41 ),\n .\\rd_mux_sel_r_reg[1]_43 (\\rd_mux_sel_r_reg[1]_42 ),\n .\\rd_mux_sel_r_reg[1]_44 (\\rd_mux_sel_r_reg[1]_43 ),\n .\\rd_mux_sel_r_reg[1]_45 (\\rd_mux_sel_r_reg[1]_44 ),\n .\\rd_mux_sel_r_reg[1]_46 (\\rd_mux_sel_r_reg[1]_45 ),\n .\\rd_mux_sel_r_reg[1]_47 (\\rd_mux_sel_r_reg[1]_46 ),\n .\\rd_mux_sel_r_reg[1]_48 (\\rd_mux_sel_r_reg[1]_47 ),\n .\\rd_mux_sel_r_reg[1]_49 (\\rd_mux_sel_r_reg[1]_48 ),\n .\\rd_mux_sel_r_reg[1]_5 (\\rd_mux_sel_r_reg[1]_4 ),\n .\\rd_mux_sel_r_reg[1]_50 (\\rd_mux_sel_r_reg[1]_49 ),\n .\\rd_mux_sel_r_reg[1]_51 (\\rd_mux_sel_r_reg[1]_50 ),\n .\\rd_mux_sel_r_reg[1]_52 (\\rd_mux_sel_r_reg[1]_51 ),\n .\\rd_mux_sel_r_reg[1]_53 (\\rd_mux_sel_r_reg[1]_52 ),\n .\\rd_mux_sel_r_reg[1]_54 (\\rd_mux_sel_r_reg[1]_53 ),\n .\\rd_mux_sel_r_reg[1]_55 (\\rd_mux_sel_r_reg[1]_54 ),\n .\\rd_mux_sel_r_reg[1]_56 (\\rd_mux_sel_r_reg[1]_55 ),\n .\\rd_mux_sel_r_reg[1]_57 (\\rd_mux_sel_r_reg[1]_56 ),\n .\\rd_mux_sel_r_reg[1]_58 (\\rd_mux_sel_r_reg[1]_57 ),\n .\\rd_mux_sel_r_reg[1]_59 (\\rd_mux_sel_r_reg[1]_58 ),\n .\\rd_mux_sel_r_reg[1]_6 (\\rd_mux_sel_r_reg[1]_5 ),\n .\\rd_mux_sel_r_reg[1]_60 (\\rd_mux_sel_r_reg[1]_59 ),\n .\\rd_mux_sel_r_reg[1]_61 (\\rd_mux_sel_r_reg[1]_60 ),\n .\\rd_mux_sel_r_reg[1]_62 (\\rd_mux_sel_r_reg[1]_61 ),\n .\\rd_mux_sel_r_reg[1]_63 (\\rd_mux_sel_r_reg[1]_62 ),\n .\\rd_mux_sel_r_reg[1]_7 (\\rd_mux_sel_r_reg[1]_6 ),\n .\\rd_mux_sel_r_reg[1]_8 (\\rd_mux_sel_r_reg[1]_7 ),\n .\\rd_mux_sel_r_reg[1]_9 (\\rd_mux_sel_r_reg[1]_8 ),\n .\\rdlvl_cpt_tap_cnt_reg[1] (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_94 ),\n .\\rdlvl_cpt_tap_cnt_reg[2] (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_95 ),\n .\\rdlvl_cpt_tap_cnt_reg[4] (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_93 ),\n .\\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 (\\rdlvl_dqs_tap_cnt_r_reg[0][3][0] ),\n .rdlvl_last_byte_done(rdlvl_last_byte_done),\n .rdlvl_pi_incdec(rdlvl_pi_incdec),\n .rdlvl_pi_incdec_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_180 ),\n .rdlvl_pi_incdec_reg_1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_185 ),\n .rdlvl_prech_req(rdlvl_prech_req),\n .rdlvl_rank_done_r_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_188 ),\n .rdlvl_stg1_done_int(rdlvl_stg1_done_int),\n .rdlvl_stg1_done_r1_reg(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_56 ),\n .rdlvl_stg1_rank_done(rdlvl_stg1_rank_done),\n .rdlvl_stg1_start_reg(u_ddr_phy_init_n_33),\n .rdlvl_stg1_start_reg_0(cnt_shift_r0),\n .\\regl_dqs_cnt_r_reg[2]_0 (regl_dqs_cnt),\n .\\regl_dqs_cnt_reg[0]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_101 ),\n .\\regl_dqs_cnt_reg[2]_0 (pi_stg2_load_timing_i_1_n_0),\n .\\right_edge_taps_r_reg[0]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_47 ),\n .\\right_edge_taps_r_reg[0]_1 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_91 ),\n .\\right_edge_taps_r_reg[0]_2 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_139 ),\n .rstdiv0_sync_r1_reg_rep__13(rstdiv0_sync_r1_reg_rep__13),\n .rstdiv0_sync_r1_reg_rep__14(rstdiv0_sync_r1_reg_rep__14),\n .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23),\n .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),\n .samp_cnt_done_r_reg_0(\\gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_2_n_0 ),\n .samp_cnt_done_r_reg_1(\\gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1_n_0 ),\n .samp_cnt_done_r_reg_2(\\gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1_n_0 ),\n .samp_cnt_done_r_reg_3(\\gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1_n_0 ),\n .samp_cnt_done_r_reg_4(\\gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1_n_0 ),\n .samp_cnt_done_r_reg_5(\\gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1_n_0 ),\n .samp_cnt_done_r_reg_6(\\gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1_n_0 ),\n .samp_edge_cnt0_en_r(samp_edge_cnt0_en_r),\n .samp_edge_cnt0_en_r_reg_0(samp_edge_cnt0_en_r_reg),\n .\\second_edge_taps_r_reg[5]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_161 ),\n .sr_valid_r108_out(sr_valid_r108_out),\n .sr_valid_r1_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_2 ),\n .stg1_wr_done(stg1_wr_done),\n .\\stg1_wr_rd_cnt_reg[3] (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_79 ),\n .store_sr_r_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_1 ),\n .store_sr_req_r_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_92 ),\n .store_sr_req_r_reg_1(store_sr_r_i_1_n_0),\n .tempmon_pi_f_en_r(tempmon_pi_f_en_r),\n .tempmon_pi_f_inc_r(tempmon_pi_f_inc_r),\n .\\wait_cnt_r_reg[0]_0 (wait_cnt_r_reg__0),\n .\\wait_cnt_r_reg[0]_1 (pi_cnt_dec_i_1_n_0),\n .wr_level_done_reg(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_12 ),\n .wrcal_done_reg(u_ddr_phy_wrcal_n_82),\n .wrcal_prech_req(wrcal_prech_req),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[254] (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_153 ),\n .wrlvl_byte_redo(wrlvl_byte_redo),\n .wrlvl_byte_redo_reg(u_ddr_phy_wrcal_n_95),\n .wrlvl_done_r1(wrlvl_done_r1),\n .wrlvl_done_r1_reg(u_ddr_phy_wrcal_n_91),\n .wrlvl_done_r1_reg_0(u_ddr_phy_init_n_499),\n .wrlvl_final_mux(wrlvl_final_mux),\n .wrlvl_final_mux_reg(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_88 ));\n ddr3_if_mig_7series_v4_0_ddr_phy_tempmon ddr_phy_tempmon_0\n (.CLK(CLK),\n .D(ddr_phy_tempmon_0_n_3),\n .SS(SS),\n .calib_complete(calib_complete),\n .calib_in_common(calib_in_common),\n .\\calib_zero_inputs_reg[1] (ddr_phy_tempmon_0_n_4),\n .\\calib_zero_inputs_reg[1]_0 (ddr_phy_tempmon_0_n_5),\n .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done),\n .cmd_delay_start0(cmd_delay_start0),\n .ctl_lane_sel(ctl_lane_sel),\n .delay_done_r4_reg(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_102 ),\n .\\device_temp_r_reg[11] (\\device_temp_r_reg[11] ),\n .fine_adjust_done_r_reg(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_12 ),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[0] (ddr_phy_tempmon_0_n_2),\n .\\gen_byte_sel_div1.calib_in_common_reg (ddr_phy_tempmon_0_n_6),\n .oclkdelay_calib_done_r_reg(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_157 ),\n .rd_data_offset_cal_done(rd_data_offset_cal_done),\n .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2),\n .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25),\n .rstdiv0_sync_r1_reg_rep__4(rstdiv0_sync_r1_reg_rep__4),\n .rstdiv0_sync_r1_reg_rep__5(rstdiv0_sync_r1_reg_rep__5),\n .rstdiv0_sync_r1_reg_rep__6(rstdiv0_sync_r1_reg_rep__6),\n .rstdiv0_sync_r1_reg_rep__7(rstdiv0_sync_r1_reg_rep__7),\n .tempmon_pi_f_inc(tempmon_pi_f_inc),\n .tempmon_sample_en(tempmon_sample_en),\n .tempmon_sel_pi_incdec(tempmon_sel_pi_incdec));\n LUT6 #(\n .INIT(64'hFEFFFFFF02000000)) \n dq_cnt_inc_i_1\n (.I0(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_56 ),\n .I1(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_30 ),\n .I2(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_29 ),\n .I3(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_31 ),\n .I4(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_27 ),\n .I5(p_0_in_2),\n .O(dq_cnt_inc_i_1_n_0));\n LUT6 #(\n .INIT(64'h00E2FFFF00E20000)) \n dqs_found_prech_req_i_1\n (.I0(fine_adj_state_r16_out),\n .I1(fine_adj_state_r144_out),\n .I2(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_78 ),\n .I3(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_44 ),\n .I4(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_110 ),\n .I5(dqs_found_prech_req),\n .O(dqs_found_prech_req_i_1_n_0));\n ddr3_if_mig_7series_v4_0_ddr_phy_dqs_found_cal \\dqsfind_calib_right.u_ddr_phy_dqs_found_cal \n (.CLK(CLK),\n .D({\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_103 ,\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_104 }),\n .D_po_fine_enable107_out(D_po_fine_enable107_out),\n .D_po_fine_inc113_out(D_po_fine_inc113_out),\n .\\FSM_sequential_fine_adj_state_r_reg[0]_0 ({\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_43 ,\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_44 ,\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ,\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_46 }),\n .\\FSM_sequential_fine_adj_state_r_reg[0]_1 (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_80 ),\n .\\FSM_sequential_fine_adj_state_r_reg[0]_2 (fine_adjust_i_1_n_0),\n .\\FSM_sequential_fine_adj_state_r_reg[0]_3 (fine_adjust_done_r_i_1_n_0),\n .\\FSM_sequential_fine_adj_state_r_reg[1]_0 (rst_dqs_find_i_1_n_0),\n .\\FSM_sequential_fine_adj_state_r_reg[1]_1 (final_dec_done_i_1_n_0),\n .\\FSM_sequential_fine_adj_state_r_reg[1]_2 (ck_po_stg2_f_indec_i_1_n_0),\n .\\FSM_sequential_fine_adj_state_r_reg[1]_3 (ck_po_stg2_f_en_i_1_n_0),\n .\\FSM_sequential_fine_adj_state_r_reg[2]_0 (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_41 ),\n .\\FSM_sequential_fine_adj_state_r_reg[2]_1 (dqs_found_prech_req_i_1_n_0),\n .Q(\\po_rdval_cnt_reg[8] [1:0]),\n .byte_sel_cnt(byte_sel_cnt),\n .\\calib_data_offset_0_reg[0] (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_93 ),\n .\\calib_data_offset_0_reg[1] (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_92 ),\n .\\calib_data_offset_0_reg[4] (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_91 ),\n .\\calib_data_offset_0_reg[5] (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_90 ),\n .\\calib_data_offset_1_reg[0] (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_97 ),\n .\\calib_data_offset_1_reg[1] (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_96 ),\n .\\calib_data_offset_1_reg[4] (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_95 ),\n .\\calib_data_offset_1_reg[5] (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_94 ),\n .calib_in_common(calib_in_common),\n .\\calib_zero_inputs_reg[0] (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_105 ),\n .\\calib_zero_inputs_reg[1] (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_102 ),\n .\\calib_zero_inputs_reg[1]_0 ({calib_zero_inputs,calib_zero_inputs__0}),\n .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done),\n .ck_po_stg2_f_en(ck_po_stg2_f_en),\n .ck_po_stg2_f_indec(ck_po_stg2_f_indec),\n .cmd_delay_start0(cmd_delay_start0),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[0] (\\cmd_pipe_plus.mc_data_offset_1_reg[0] ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[1] (\\cmd_pipe_plus.mc_data_offset_1_reg[1] ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[2] (\\cmd_pipe_plus.mc_data_offset_1_reg[2] ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[3] (\\cmd_pipe_plus.mc_data_offset_1_reg[3] ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[4] (\\cmd_pipe_plus.mc_data_offset_1_reg[4] ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[5] (\\cmd_pipe_plus.mc_data_offset_1_reg[5] ),\n .\\cmd_pipe_plus.mc_data_offset_reg[0] (\\cmd_pipe_plus.mc_data_offset_reg[0] ),\n .\\cmd_pipe_plus.mc_data_offset_reg[1] (\\cmd_pipe_plus.mc_data_offset_reg[1] ),\n .\\cmd_pipe_plus.mc_data_offset_reg[2] (\\cmd_pipe_plus.mc_data_offset_reg[2] ),\n .\\cmd_pipe_plus.mc_data_offset_reg[3] (\\cmd_pipe_plus.mc_data_offset_reg[3] ),\n .\\cmd_pipe_plus.mc_data_offset_reg[4] (\\cmd_pipe_plus.mc_data_offset_reg[4] ),\n .\\cmd_pipe_plus.mc_data_offset_reg[5] (\\cmd_pipe_plus.mc_data_offset_reg[5] ),\n .cnt_cmd_done_r(cnt_cmd_done_r),\n .ctl_lane_cnt(ctl_lane_cnt),\n .ctl_lane_sel(ctl_lane_sel),\n .\\dec_cnt_reg[0]_0 (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_42 ),\n .detect_pi_found_dqs(detect_pi_found_dqs),\n .dqs_found_prech_req(dqs_found_prech_req),\n .dqs_found_prech_req_reg_0(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_78 ),\n .dqs_found_prech_req_reg_1(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_110 ),\n .dqs_po_dec_done(dqs_po_dec_done),\n .dqs_po_en_stg2_f(dqs_po_en_stg2_f),\n .dqs_po_stg2_f_incdec(dqs_po_stg2_f_incdec),\n .final_dec_done_reg_0(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_14 ),\n .final_dec_done_reg_1(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_79 ),\n .fine_adj_state_r144_out(fine_adj_state_r144_out),\n .fine_adj_state_r16_out(fine_adj_state_r16_out),\n .fine_adjust_done_r_reg_0(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_12 ),\n .fine_adjust_reg_0(fine_adjust_reg),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[0] (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_106 ),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 (\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[1] (\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_27 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_0 (\\phaser_in_gen.phaser_in_i_12_n_0 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_1 (\\phaser_in_gen.phaser_in_i_12__0_n_0 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_2 (\\phaser_in_gen.phaser_in_i_12__1_n_0 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_3 (\\phaser_in_gen.phaser_in_i_12__2_n_0 ),\n .\\gen_byte_sel_div1.ctl_lane_sel_reg[0] (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_98 ),\n .\\gen_byte_sel_div1.ctl_lane_sel_reg[0]_0 (\\gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[0] ),\n .\\gen_byte_sel_div1.ctl_lane_sel_reg[1] (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_100 ),\n .\\gen_byte_sel_div1.ctl_lane_sel_reg[1]_0 (\\gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[1] ),\n .\\gen_byte_sel_div1.ctl_lane_sel_reg[2] (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_101 ),\n .\\gen_byte_sel_div1.ctl_lane_sel_reg[2]_0 (\\gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[2] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_87 ),\n .ififo_rst_reg(ififo_rst_reg),\n .ififo_rst_reg_0(ififo_rst_reg_0),\n .ififo_rst_reg_1(ififo_rst_reg_1),\n .ififo_rst_reg_2(ififo_rst_reg_2),\n .in0(in0),\n .init_calib_complete_reg(ddr_phy_tempmon_0_n_5),\n .init_dec_done_reg_0(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_13 ),\n .init_dec_done_reg_1(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_112 ),\n .init_dec_done_reg_2(init_dec_done_i_1_n_0),\n .init_dqsfound_done_r2(init_dqsfound_done_r2),\n .init_dqsfound_done_r5(init_dqsfound_done_r5),\n .init_dqsfound_done_r_reg_0(init_dqsfound_done_r_i_1_n_0),\n .\\init_state_r_reg[1] (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_85 ),\n .\\init_state_r_reg[1]_0 (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_88 ),\n .\\init_state_r_reg[1]_1 (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_89 ),\n .\\init_state_r_reg[2] (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_86 ),\n .mpr_rdlvl_done_r_reg(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_147 ),\n .\\num_refresh_reg[1] (u_ddr_phy_init_n_117),\n .oclkdelay_calib_done_r_reg(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_157 ),\n .oclkdelay_calib_done_r_reg_0(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ),\n .oclkdelay_center_calib_done_r_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_4 ),\n .out({p_3_in25_in,p_2_in24_in,p_0_in23_in,\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_5 }),\n .p_1_in27_in(p_1_in27_in),\n .p_1_in50_in(p_1_in50_in),\n .pi_calib_done(pi_calib_done),\n .\\pi_dqs_found_all_bank_r_reg[1]_0 (pi_dqs_found_all_bank),\n .\\pi_dqs_found_all_bank_r_reg[1]_1 (rank_done_r_i_1_n_0),\n .pi_dqs_found_any_bank(pi_dqs_found_any_bank),\n .pi_dqs_found_done_r1(pi_dqs_found_done_r1),\n .pi_dqs_found_done_r1_reg(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_10 ),\n .\\pi_dqs_found_lanes_r3_reg[3]_0 (\\pi_dqs_found_any_bank[0]_i_1_n_0 ),\n .pi_dqs_found_rank_done(pi_dqs_found_rank_done),\n .pi_dqs_found_start_reg(u_ddr_phy_init_n_502),\n .pi_dqs_found_start_reg_0(u_ddr_phy_init_n_501),\n .pi_f_inc_reg(ddr_phy_tempmon_0_n_6),\n .pi_fine_dly_dec_done(pi_fine_dly_dec_done),\n .\\pi_rst_stg1_cal_r_reg[0]_0 (\\pi_rst_stg1_cal_r_reg[0] ),\n .\\pi_rst_stg1_cal_r_reg[0]_1 (\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_76 ),\n .\\po_counter_read_val_reg[8] (\\po_counter_read_val_reg[8]_1 ),\n .\\po_counter_read_val_reg[8]_0 (\\po_counter_read_val_reg[8]_2 ),\n .\\po_counter_read_val_reg[8]_1 (\\po_counter_read_val_reg[8]_6 ),\n .\\po_counter_read_val_reg[8]_10 (\\po_counter_read_val_reg[8]_23 ),\n .\\po_counter_read_val_reg[8]_11 (\\po_counter_read_val_reg[8]_25 ),\n .\\po_counter_read_val_reg[8]_12 (\\po_counter_read_val_reg[8]_26 ),\n .\\po_counter_read_val_reg[8]_2 (\\po_counter_read_val_reg[8]_7 ),\n .\\po_counter_read_val_reg[8]_3 (\\po_counter_read_val_reg[8]_9 ),\n .\\po_counter_read_val_reg[8]_4 (\\po_counter_read_val_reg[8]_10 ),\n .\\po_counter_read_val_reg[8]_5 (\\po_counter_read_val_reg[8]_16 ),\n .\\po_counter_read_val_reg[8]_6 (\\po_counter_read_val_reg[8]_17 ),\n .\\po_counter_read_val_reg[8]_7 (\\po_counter_read_val_reg[8]_19 ),\n .\\po_counter_read_val_reg[8]_8 (\\po_counter_read_val_reg[8]_20 ),\n .\\po_counter_read_val_reg[8]_9 (\\po_counter_read_val_reg[8]_22 ),\n .po_en_stg23(po_en_stg23),\n .po_en_stg2_f(cmd_po_en_stg2_f),\n .po_enstg2_f(po_enstg2_f),\n .po_stg23_incdec(po_stg23_incdec),\n .po_stg2_fincdec(po_stg2_fincdec),\n .prbs_last_byte_done_r(prbs_last_byte_done_r),\n .prbs_rdlvl_done_reg_rep(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_51 ),\n .prech_done(prech_done),\n .rank_done_r_reg_0(pi_dqs_found_all_bank_r),\n .\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 ({\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_73 ,\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_74 }),\n .\\rank_final_loop[0].final_do_max_reg[0][3]_0 (rd_data_offset_ranks_0),\n .\\rank_final_loop[0].final_do_max_reg[0][3]_1 (rd_data_offset_ranks_1),\n .\\rd_byte_data_offset_reg[0][9]_0 (p_0_in_0),\n .\\rd_byte_data_offset_reg[0]_3 (\\rd_byte_data_offset_reg[0]_3 ),\n .rd_data_offset_cal_done(rd_data_offset_cal_done),\n .rdlvl_stg1_done_int_reg(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_56 ),\n .rst_dqs_find(rst_dqs_find),\n .rst_dqs_find_r1_reg_0(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_9 ),\n .rst_dqs_find_reg_0(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_109 ),\n .rst_dqs_find_reg_1(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_111 ),\n .rstdiv0_sync_r1_reg_rep__12(rstdiv0_sync_r1_reg_rep__12),\n .rstdiv0_sync_r1_reg_rep__13(rstdiv0_sync_r1_reg_rep__13),\n .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),\n .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2),\n .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),\n .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25),\n .sent_col(sent_col),\n .tempmon_sel_pi_incdec(tempmon_sel_pi_incdec),\n .wrcal_done_reg(u_ddr_phy_wrcal_n_82),\n .wrlvl_byte_redo(wrlvl_byte_redo),\n .wrlvl_done_r1(wrlvl_done_r1),\n .wrlvl_final_mux(wrlvl_final_mux));\n LUT4 #(\n .INIT(16'h2F20)) \n early1_data_i_1\n (.I0(u_ddr_phy_wrcal_n_67),\n .I1(u_ddr_phy_wrcal_n_110),\n .I2(u_ddr_phy_wrcal_n_119),\n .I3(u_ddr_phy_wrcal_n_73),\n .O(early1_data_i_1_n_0));\n LUT5 #(\n .INIT(32'h04FF0400)) \n early2_data_i_1\n (.I0(u_ddr_phy_wrcal_n_67),\n .I1(u_ddr_phy_wrcal_n_66),\n .I2(u_ddr_phy_wrcal_n_110),\n .I3(u_ddr_phy_wrcal_n_119),\n .I4(u_ddr_phy_wrcal_n_74),\n .O(early2_data_i_1_n_0));\n LUT5 #(\n .INIT(32'hFFFF0400)) \n final_dec_done_i_1\n (.I0(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ),\n .I1(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_112 ),\n .I2(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_79 ),\n .I3(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_13 ),\n .I4(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_14 ),\n .O(final_dec_done_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFF00100000)) \n fine_adjust_done_r_i_1\n (.I0(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_46 ),\n .I1(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_44 ),\n .I2(p_1_in27_in),\n .I3(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_43 ),\n .I4(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ),\n .I5(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_12 ),\n .O(fine_adjust_done_r_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFF00000100)) \n fine_adjust_i_1\n (.I0(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_46 ),\n .I1(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_43 ),\n .I2(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_44 ),\n .I3(init_dqsfound_done_r5),\n .I4(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ),\n .I5(\\pi_rst_stg1_cal_r_reg[0] ),\n .O(fine_adjust_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair714\" *) \n LUT5 #(\n .INIT(32'h0000F200)) \n \\fine_delay_r[11]_i_1 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[3]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26] [2]));\n (* SOFT_HLUTNM = \"soft_lutpair702\" *) \n LUT5 #(\n .INIT(32'h0000F200)) \n \\fine_delay_r[11]_i_1__0 \n (.I0(\\po_rdval_cnt_reg[8] [1]),\n .I1(\\po_rdval_cnt_reg[8] [0]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[3]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26]_0 [2]));\n (* SOFT_HLUTNM = \"soft_lutpair714\" *) \n LUT5 #(\n .INIT(32'h0000F800)) \n \\fine_delay_r[11]_i_1__1 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[3]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26]_1 [2]));\n (* SOFT_HLUTNM = \"soft_lutpair702\" *) \n LUT5 #(\n .INIT(32'h22220002)) \n \\fine_delay_r[11]_i_1__2 \n (.I0(fine_delay_mod[3]),\n .I1(calib_zero_inputs__0),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .I3(\\po_rdval_cnt_reg[8] [1]),\n .I4(calib_in_common),\n .O(D[3]));\n (* SOFT_HLUTNM = \"soft_lutpair713\" *) \n LUT5 #(\n .INIT(32'h0000F200)) \n \\fine_delay_r[14]_i_1 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[4]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26] [3]));\n (* SOFT_HLUTNM = \"soft_lutpair703\" *) \n LUT5 #(\n .INIT(32'h0000F200)) \n \\fine_delay_r[14]_i_1__0 \n (.I0(\\po_rdval_cnt_reg[8] [1]),\n .I1(\\po_rdval_cnt_reg[8] [0]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[4]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26]_0 [3]));\n (* SOFT_HLUTNM = \"soft_lutpair713\" *) \n LUT5 #(\n .INIT(32'h0000F800)) \n \\fine_delay_r[14]_i_1__1 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[4]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26]_1 [3]));\n (* SOFT_HLUTNM = \"soft_lutpair703\" *) \n LUT5 #(\n .INIT(32'h22220002)) \n \\fine_delay_r[14]_i_1__2 \n (.I0(fine_delay_mod[4]),\n .I1(calib_zero_inputs__0),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .I3(\\po_rdval_cnt_reg[8] [1]),\n .I4(calib_in_common),\n .O(D[4]));\n (* SOFT_HLUTNM = \"soft_lutpair705\" *) \n LUT5 #(\n .INIT(32'h0000F200)) \n \\fine_delay_r[17]_i_1 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[5]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26] [4]));\n (* SOFT_HLUTNM = \"soft_lutpair711\" *) \n LUT5 #(\n .INIT(32'h0000F200)) \n \\fine_delay_r[17]_i_1__0 \n (.I0(\\po_rdval_cnt_reg[8] [1]),\n .I1(\\po_rdval_cnt_reg[8] [0]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[5]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26]_0 [4]));\n (* SOFT_HLUTNM = \"soft_lutpair711\" *) \n LUT5 #(\n .INIT(32'h0000F800)) \n \\fine_delay_r[17]_i_1__1 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[5]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26]_1 [4]));\n (* SOFT_HLUTNM = \"soft_lutpair705\" *) \n LUT5 #(\n .INIT(32'h22220002)) \n \\fine_delay_r[17]_i_1__2 \n (.I0(fine_delay_mod[5]),\n .I1(calib_zero_inputs__0),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .I3(\\po_rdval_cnt_reg[8] [1]),\n .I4(calib_in_common),\n .O(D[5]));\n (* SOFT_HLUTNM = \"soft_lutpair704\" *) \n LUT5 #(\n .INIT(32'h0000F200)) \n \\fine_delay_r[20]_i_1 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[6]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26] [5]));\n (* SOFT_HLUTNM = \"soft_lutpair712\" *) \n LUT5 #(\n .INIT(32'h0000F200)) \n \\fine_delay_r[20]_i_1__0 \n (.I0(\\po_rdval_cnt_reg[8] [1]),\n .I1(\\po_rdval_cnt_reg[8] [0]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[6]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26]_0 [5]));\n (* SOFT_HLUTNM = \"soft_lutpair712\" *) \n LUT5 #(\n .INIT(32'h0000F800)) \n \\fine_delay_r[20]_i_1__1 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[6]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26]_1 [5]));\n (* SOFT_HLUTNM = \"soft_lutpair704\" *) \n LUT5 #(\n .INIT(32'h22220002)) \n \\fine_delay_r[20]_i_1__2 \n (.I0(fine_delay_mod[6]),\n .I1(calib_zero_inputs__0),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .I3(\\po_rdval_cnt_reg[8] [1]),\n .I4(calib_in_common),\n .O(D[6]));\n (* SOFT_HLUTNM = \"soft_lutpair706\" *) \n LUT5 #(\n .INIT(32'h0000F200)) \n \\fine_delay_r[23]_i_1 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[7]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26] [6]));\n (* SOFT_HLUTNM = \"soft_lutpair715\" *) \n LUT5 #(\n .INIT(32'h0000F200)) \n \\fine_delay_r[23]_i_1__0 \n (.I0(\\po_rdval_cnt_reg[8] [1]),\n .I1(\\po_rdval_cnt_reg[8] [0]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[7]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26]_0 [6]));\n (* SOFT_HLUTNM = \"soft_lutpair715\" *) \n LUT5 #(\n .INIT(32'h0000F800)) \n \\fine_delay_r[23]_i_1__1 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[7]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26]_1 [6]));\n (* SOFT_HLUTNM = \"soft_lutpair700\" *) \n LUT5 #(\n .INIT(32'h0000AB00)) \n \\fine_delay_r[23]_i_1__2 \n (.I0(calib_in_common),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .I3(fine_delay_sel_r),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[2] ));\n (* SOFT_HLUTNM = \"soft_lutpair706\" *) \n LUT5 #(\n .INIT(32'h22220002)) \n \\fine_delay_r[23]_i_2 \n (.I0(fine_delay_mod[7]),\n .I1(calib_zero_inputs__0),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .I3(\\po_rdval_cnt_reg[8] [1]),\n .I4(calib_in_common),\n .O(D[7]));\n (* SOFT_HLUTNM = \"soft_lutpair697\" *) \n LUT5 #(\n .INIT(32'h0000EA00)) \n \\fine_delay_r[26]_i_1 \n (.I0(calib_in_common),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .I3(fine_delay_sel_r),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[5] ));\n (* SOFT_HLUTNM = \"soft_lutpair700\" *) \n LUT5 #(\n .INIT(32'h0000BA00)) \n \\fine_delay_r[26]_i_1__0 \n (.I0(calib_in_common),\n .I1(\\po_rdval_cnt_reg[8] [0]),\n .I2(\\po_rdval_cnt_reg[8] [1]),\n .I3(fine_delay_sel_r),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[5]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair697\" *) \n LUT5 #(\n .INIT(32'h0000BA00)) \n \\fine_delay_r[26]_i_1__1 \n (.I0(calib_in_common),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .I3(fine_delay_sel_r),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[5]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair709\" *) \n LUT5 #(\n .INIT(32'h0000F200)) \n \\fine_delay_r[26]_i_2 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[8]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26] [7]));\n (* SOFT_HLUTNM = \"soft_lutpair709\" *) \n LUT5 #(\n .INIT(32'h0000F200)) \n \\fine_delay_r[26]_i_2__0 \n (.I0(\\po_rdval_cnt_reg[8] [1]),\n .I1(\\po_rdval_cnt_reg[8] [0]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[8]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26]_0 [7]));\n (* SOFT_HLUTNM = \"soft_lutpair717\" *) \n LUT5 #(\n .INIT(32'h0000F800)) \n \\fine_delay_r[26]_i_2__1 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[8]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26]_1 [7]));\n (* SOFT_HLUTNM = \"soft_lutpair708\" *) \n LUT5 #(\n .INIT(32'h44440004)) \n \\fine_delay_r[2]_i_1 \n (.I0(calib_zero_inputs__0),\n .I1(fine_delay_mod[0]),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .I3(\\po_rdval_cnt_reg[8] [1]),\n .I4(calib_in_common),\n .O(D[0]));\n (* SOFT_HLUTNM = \"soft_lutpair707\" *) \n LUT5 #(\n .INIT(32'h0000F200)) \n \\fine_delay_r[5]_i_1 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[1]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26] [0]));\n (* SOFT_HLUTNM = \"soft_lutpair716\" *) \n LUT5 #(\n .INIT(32'h0000F200)) \n \\fine_delay_r[5]_i_1__0 \n (.I0(\\po_rdval_cnt_reg[8] [1]),\n .I1(\\po_rdval_cnt_reg[8] [0]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[1]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26]_0 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair716\" *) \n LUT5 #(\n .INIT(32'h0000F800)) \n \\fine_delay_r[5]_i_1__1 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[1]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26]_1 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair707\" *) \n LUT5 #(\n .INIT(32'h22220002)) \n \\fine_delay_r[5]_i_1__2 \n (.I0(fine_delay_mod[1]),\n .I1(calib_zero_inputs__0),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .I3(\\po_rdval_cnt_reg[8] [1]),\n .I4(calib_in_common),\n .O(D[1]));\n (* SOFT_HLUTNM = \"soft_lutpair710\" *) \n LUT5 #(\n .INIT(32'h0000F200)) \n \\fine_delay_r[8]_i_1 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[2]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26] [1]));\n (* SOFT_HLUTNM = \"soft_lutpair710\" *) \n LUT5 #(\n .INIT(32'h0000F200)) \n \\fine_delay_r[8]_i_1__0 \n (.I0(\\po_rdval_cnt_reg[8] [1]),\n .I1(\\po_rdval_cnt_reg[8] [0]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[2]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26]_0 [1]));\n (* SOFT_HLUTNM = \"soft_lutpair701\" *) \n LUT5 #(\n .INIT(32'h0000F800)) \n \\fine_delay_r[8]_i_1__1 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(fine_delay_mod[2]),\n .I4(calib_zero_inputs__0),\n .O(\\fine_delay_r_reg[26]_1 [1]));\n (* SOFT_HLUTNM = \"soft_lutpair701\" *) \n LUT5 #(\n .INIT(32'h22220002)) \n \\fine_delay_r[8]_i_1__2 \n (.I0(fine_delay_mod[2]),\n .I1(calib_zero_inputs__0),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .I3(\\po_rdval_cnt_reg[8] [1]),\n .I4(calib_in_common),\n .O(D[2]));\n LUT6 #(\n .INIT(64'hFFFFDFDD00000008)) \n fine_delay_sel_i_1\n (.I0(prbs_state_r[0]),\n .I1(prbs_state_r[4]),\n .I2(prbs_state_r[3]),\n .I3(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_102 ),\n .I4(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_104 ),\n .I5(fine_delay_sel_r_reg),\n .O(fine_delay_sel_i_1_n_0));\n LUT6 #(\n .INIT(64'h8FFFFFFF80000000)) \n fine_dly_error_i_1\n (.I0(dec_cnt_reg[0]),\n .I1(dec_cnt_reg[5]),\n .I2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_108 ),\n .I3(prbs_state_r[1]),\n .I4(prbs_state_r[0]),\n .I5(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_44 ),\n .O(fine_dly_error_i_1_n_0));\n LUT6 #(\n .INIT(64'h00000000FFFFAAA8)) \n flag_ck_negedge_i_1\n (.I0(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_7 ),\n .I1(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_40 ),\n .I2(stable_cnt1),\n .I3(stable_cnt227_in),\n .I4(flag_ck_negedge09_out),\n .I5(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_47 ),\n .O(flag_ck_negedge_i_1_n_0));\n LUT6 #(\n .INIT(64'h3F3FFBFF00000800)) \n found_first_edge_r_i_1\n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_4 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_91 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_84 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_139 ),\n .I4(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_85 ),\n .I5(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_47 ),\n .O(found_first_edge_r_i_1_n_0));\n LUT5 #(\n .INIT(32'h08FF0800)) \n found_second_edge_r_i_1\n (.I0(found_stable_eye_last_r),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_47 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_84 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_161 ),\n .I4(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_60 ),\n .O(found_second_edge_r_i_1_n_0));\n LUT3 #(\n .INIT(8'hB8)) \n found_stable_eye_last_r_i_1\n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_3 ),\n .I1(detect_edge_done_r),\n .I2(found_stable_eye_last_r),\n .O(found_stable_eye_last_r_i_1_n_0));\n FDRE \\gen_byte_sel_div1.byte_sel_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_48 ),\n .Q(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]),\n .R(1'b0));\n FDRE \\gen_byte_sel_div1.byte_sel_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_49 ),\n .Q(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]),\n .R(1'b0));\n FDRE \\gen_byte_sel_div1.byte_sel_cnt_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_50 ),\n .Q(byte_sel_cnt),\n .R(1'b0));\n (* syn_maxfan = \"10\" *) \n FDRE \\gen_byte_sel_div1.calib_in_common_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_27 ),\n .Q(calib_in_common),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE \\gen_byte_sel_div1.ctl_lane_sel_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_98 ),\n .Q(\\gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE \\gen_byte_sel_div1.ctl_lane_sel_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_100 ),\n .Q(\\gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE \\gen_byte_sel_div1.ctl_lane_sel_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_101 ),\n .Q(\\gen_byte_sel_div1.ctl_lane_sel_reg_n_0_[2] ),\n .R(rstdiv0_sync_r1_reg_rep__9));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 ),\n .O(\\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 ),\n .O(\\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 ),\n .O(\\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 ),\n .O(\\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 ),\n .O(\\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 ),\n .O(\\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 ),\n .O(\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 ),\n .O(\\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 ),\n .O(\\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 ),\n .O(\\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 ),\n .O(\\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 ),\n .O(\\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 ),\n .O(\\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 ),\n .O(\\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 ),\n .O(\\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 ),\n .O(\\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 ),\n .O(\\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 ),\n .O(\\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 ),\n .O(\\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 ),\n .O(\\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 ),\n .O(\\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 ),\n .O(\\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 ),\n .O(\\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 ),\n .O(\\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 ),\n .O(\\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 ),\n .O(\\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 ),\n .O(\\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 ),\n .O(\\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_208 ),\n .O(\\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 ),\n .O(\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 ),\n .O(\\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 ),\n .O(\\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 ),\n .O(\\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 ),\n .O(\\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 ),\n .O(\\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 ),\n .O(\\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 ),\n .O(\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 ),\n .O(\\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 ),\n .O(\\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 ),\n .O(\\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 ),\n .O(\\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 ),\n .O(\\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 ),\n .O(\\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 ),\n .O(\\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 ),\n .O(\\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 ),\n .O(\\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 ),\n .O(\\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 ),\n .O(\\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 ),\n .O(\\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 ),\n .O(\\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 ),\n .O(\\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 ),\n .O(\\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 ),\n .O(\\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 ),\n .O(\\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 ),\n .O(\\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 ),\n .O(\\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 ),\n .O(\\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 ),\n .O(\\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_212 ),\n .O(\\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1 \n (.I0(\\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 ),\n .O(\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h5554)) \n \\gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_9 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ),\n .I3(pb_detect_edge_done_r[0]),\n .O(\\gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h5050505051515051)) \n \\gen_track_left_edge[0].pb_found_edge_r[0]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_108 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_39 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ),\n .I4(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_107 ),\n .I5(pb_detect_edge_done_r[0]),\n .O(\\gen_track_left_edge[0].pb_found_edge_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFEFE01000000)) \n \\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_108 ),\n .I1(pb_detect_edge_done_r[0]),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_124 ),\n .I4(pb_found_stable_eye_r76_out),\n .I5(\\gen_track_left_edge[0].pb_found_stable_eye_r_reg ),\n .O(\\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h5554)) \n \\gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ),\n .I2(p_0_in102_in),\n .I3(pb_detect_edge_done_r[1]),\n .O(\\gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h5050505051515051)) \n \\gen_track_left_edge[1].pb_found_edge_r[1]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_110 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_40 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ),\n .I4(p_0_in16_in),\n .I5(pb_detect_edge_done_r[1]),\n .O(\\gen_track_left_edge[1].pb_found_edge_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFEFE01000000)) \n \\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_110 ),\n .I1(pb_detect_edge_done_r[1]),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_126 ),\n .I4(pb_found_stable_eye_r72_out),\n .I5(\\gen_track_left_edge[1].pb_found_stable_eye_r_reg ),\n .O(\\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h5554)) \n \\gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ),\n .I2(p_0_in99_in),\n .I3(pb_detect_edge_done_r[2]),\n .O(\\gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h5050505051515051)) \n \\gen_track_left_edge[2].pb_found_edge_r[2]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_112 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_41 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ),\n .I4(p_0_in13_in),\n .I5(pb_detect_edge_done_r[2]),\n .O(\\gen_track_left_edge[2].pb_found_edge_r[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFEFE01000000)) \n \\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_112 ),\n .I1(pb_detect_edge_done_r[2]),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_128 ),\n .I4(pb_found_stable_eye_r68_out),\n .I5(\\gen_track_left_edge[2].pb_found_stable_eye_r_reg ),\n .O(\\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h5554)) \n \\gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ),\n .I2(p_0_in96_in),\n .I3(pb_detect_edge_done_r[3]),\n .O(\\gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h5050505051515051)) \n \\gen_track_left_edge[3].pb_found_edge_r[3]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_114 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_42 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ),\n .I4(p_0_in10_in),\n .I5(pb_detect_edge_done_r[3]),\n .O(\\gen_track_left_edge[3].pb_found_edge_r[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFEFE01000000)) \n \\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_114 ),\n .I1(pb_detect_edge_done_r[3]),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_130 ),\n .I4(pb_found_stable_eye_r64_out),\n .I5(\\gen_track_left_edge[3].pb_found_stable_eye_r_reg ),\n .O(\\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h5554)) \n \\gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ),\n .I2(p_0_in93_in),\n .I3(pb_detect_edge_done_r[4]),\n .O(\\gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h5050505051515051)) \n \\gen_track_left_edge[4].pb_found_edge_r[4]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_116 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_43 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ),\n .I4(p_0_in7_in),\n .I5(pb_detect_edge_done_r[4]),\n .O(\\gen_track_left_edge[4].pb_found_edge_r[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFEFE01000000)) \n \\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_116 ),\n .I1(pb_detect_edge_done_r[4]),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_132 ),\n .I4(pb_found_stable_eye_r60_out),\n .I5(\\gen_track_left_edge[4].pb_found_stable_eye_r_reg ),\n .O(\\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h5554)) \n \\gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ),\n .I2(p_0_in90_in),\n .I3(pb_detect_edge_done_r[5]),\n .O(\\gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h5050505051515051)) \n \\gen_track_left_edge[5].pb_found_edge_r[5]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_118 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_44 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ),\n .I4(p_0_in4_in),\n .I5(pb_detect_edge_done_r[5]),\n .O(\\gen_track_left_edge[5].pb_found_edge_r[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFEFE01000000)) \n \\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_118 ),\n .I1(pb_detect_edge_done_r[5]),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_134 ),\n .I4(pb_found_stable_eye_r56_out),\n .I5(\\gen_track_left_edge[5].pb_found_stable_eye_r_reg ),\n .O(\\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h5554)) \n \\gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ),\n .I2(p_0_in87_in),\n .I3(pb_detect_edge_done_r[6]),\n .O(\\gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h5050505051515051)) \n \\gen_track_left_edge[6].pb_found_edge_r[6]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_120 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_45 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ),\n .I4(p_0_in1_in),\n .I5(pb_detect_edge_done_r[6]),\n .O(\\gen_track_left_edge[6].pb_found_edge_r[6]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFEFE01000000)) \n \\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_120 ),\n .I1(pb_detect_edge_done_r[6]),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_136 ),\n .I4(pb_found_stable_eye_r52_out),\n .I5(\\gen_track_left_edge[6].pb_found_stable_eye_r_reg ),\n .O(\\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h5554)) \n \\gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_2 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ),\n .I2(p_0_in84_in),\n .I3(pb_detect_edge_done_r[7]),\n .O(\\gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h5050505051515051)) \n \\gen_track_left_edge[7].pb_found_edge_r[7]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_122 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_46 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_97 ),\n .I4(p_0_in),\n .I5(pb_detect_edge_done_r[7]),\n .O(\\gen_track_left_edge[7].pb_found_edge_r[7]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFEFE01000000)) \n \\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1 \n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_122 ),\n .I1(pb_detect_edge_done_r[7]),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_98 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_138 ),\n .I4(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_137 ),\n .I5(\\gen_track_left_edge[7].pb_found_stable_eye_r_reg ),\n .O(\\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hCF88)) \n \\genblk8[0].left_edge_found_pb[0]_i_1 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_69 ),\n .I1(p_154_out),\n .I2(right_gain_pb),\n .I3(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_15 ),\n .O(\\genblk8[0].left_edge_found_pb[0]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hCF88)) \n \\genblk8[0].left_edge_updated[0]_i_1 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_69 ),\n .I1(p_154_out),\n .I2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ),\n .I3(left_edge_updated[0]),\n .O(\\genblk8[0].left_edge_updated[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hCCFE0000CCFECCCC)) \n \\genblk8[0].right_edge_found_pb[0]_i_1 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ),\n .I1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_23 ),\n .I2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_68 ),\n .I3(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_69 ),\n .I4(p_154_out),\n .I5(right_gain_pb),\n .O(\\genblk8[0].right_edge_found_pb[0]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hCF88)) \n \\genblk8[1].left_edge_found_pb[1]_i_1 \n (.I0(p_146_out),\n .I1(p_154_out),\n .I2(right_gain_pb),\n .I3(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_16 ),\n .O(\\genblk8[1].left_edge_found_pb[1]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hCF88)) \n \\genblk8[1].left_edge_updated[1]_i_1 \n (.I0(p_146_out),\n .I1(p_154_out),\n .I2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ),\n .I3(left_edge_updated[1]),\n .O(\\genblk8[1].left_edge_updated[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hCCFE0000CCFECCCC)) \n \\genblk8[1].right_edge_found_pb[1]_i_1 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ),\n .I1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_24 ),\n .I2(p_143_out),\n .I3(p_146_out),\n .I4(p_154_out),\n .I5(right_gain_pb),\n .O(\\genblk8[1].right_edge_found_pb[1]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hCF88)) \n \\genblk8[2].left_edge_found_pb[2]_i_1 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_65 ),\n .I1(p_154_out),\n .I2(right_gain_pb),\n .I3(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_17 ),\n .O(\\genblk8[2].left_edge_found_pb[2]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hCF88)) \n \\genblk8[2].left_edge_updated[2]_i_1 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_65 ),\n .I1(p_154_out),\n .I2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ),\n .I3(left_edge_updated[2]),\n .O(\\genblk8[2].left_edge_updated[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hCCFE0000CCFECCCC)) \n \\genblk8[2].right_edge_found_pb[2]_i_1 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ),\n .I1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_25 ),\n .I2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_64 ),\n .I3(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_65 ),\n .I4(p_154_out),\n .I5(right_gain_pb),\n .O(\\genblk8[2].right_edge_found_pb[2]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hCF88)) \n \\genblk8[3].left_edge_found_pb[3]_i_1 \n (.I0(p_130_out),\n .I1(p_154_out),\n .I2(right_gain_pb),\n .I3(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_18 ),\n .O(\\genblk8[3].left_edge_found_pb[3]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hCF88)) \n \\genblk8[3].left_edge_updated[3]_i_1 \n (.I0(p_130_out),\n .I1(p_154_out),\n .I2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ),\n .I3(left_edge_updated[3]),\n .O(\\genblk8[3].left_edge_updated[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hCCFE0000CCFECCCC)) \n \\genblk8[3].right_edge_found_pb[3]_i_1 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ),\n .I1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_26 ),\n .I2(p_127_out),\n .I3(p_130_out),\n .I4(p_154_out),\n .I5(right_gain_pb),\n .O(\\genblk8[3].right_edge_found_pb[3]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hCF88)) \n \\genblk8[4].left_edge_found_pb[4]_i_1 \n (.I0(p_122_out),\n .I1(p_154_out),\n .I2(right_gain_pb),\n .I3(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_19 ),\n .O(\\genblk8[4].left_edge_found_pb[4]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hCF88)) \n \\genblk8[4].left_edge_updated[4]_i_1 \n (.I0(p_122_out),\n .I1(p_154_out),\n .I2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ),\n .I3(left_edge_updated[4]),\n .O(\\genblk8[4].left_edge_updated[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hCCFE0000CCFECCCC)) \n \\genblk8[4].right_edge_found_pb[4]_i_1 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ),\n .I1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_27 ),\n .I2(p_119_out),\n .I3(p_122_out),\n .I4(p_154_out),\n .I5(right_gain_pb),\n .O(\\genblk8[4].right_edge_found_pb[4]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hCF88)) \n \\genblk8[5].left_edge_found_pb[5]_i_1 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_59 ),\n .I1(p_154_out),\n .I2(right_gain_pb),\n .I3(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_20 ),\n .O(\\genblk8[5].left_edge_found_pb[5]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hCF88)) \n \\genblk8[5].left_edge_updated[5]_i_1 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_59 ),\n .I1(p_154_out),\n .I2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ),\n .I3(left_edge_updated[5]),\n .O(\\genblk8[5].left_edge_updated[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hCCFE0000CCFECCCC)) \n \\genblk8[5].right_edge_found_pb[5]_i_1 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ),\n .I1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_28 ),\n .I2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_58 ),\n .I3(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_59 ),\n .I4(p_154_out),\n .I5(right_gain_pb),\n .O(\\genblk8[5].right_edge_found_pb[5]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hCF88)) \n \\genblk8[6].left_edge_found_pb[6]_i_1 \n (.I0(p_106_out),\n .I1(p_154_out),\n .I2(right_gain_pb),\n .I3(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_21 ),\n .O(\\genblk8[6].left_edge_found_pb[6]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hCF88)) \n \\genblk8[6].left_edge_updated[6]_i_1 \n (.I0(p_106_out),\n .I1(p_154_out),\n .I2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ),\n .I3(left_edge_updated[6]),\n .O(\\genblk8[6].left_edge_updated[6]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hCCFE0000CCFECCCC)) \n \\genblk8[6].right_edge_found_pb[6]_i_1 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ),\n .I1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_29 ),\n .I2(p_103_out),\n .I3(p_106_out),\n .I4(p_154_out),\n .I5(right_gain_pb),\n .O(\\genblk8[6].right_edge_found_pb[6]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hCF88)) \n \\genblk8[7].left_edge_found_pb[7]_i_1 \n (.I0(p_98_out),\n .I1(p_154_out),\n .I2(right_gain_pb),\n .I3(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_22 ),\n .O(\\genblk8[7].left_edge_found_pb[7]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hCF88)) \n \\genblk8[7].left_edge_updated[7]_i_1 \n (.I0(p_98_out),\n .I1(p_154_out),\n .I2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_83 ),\n .I3(left_edge_updated[7]),\n .O(\\genblk8[7].left_edge_updated[7]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hCCFE0000CCFECCCC)) \n \\genblk8[7].right_edge_found_pb[7]_i_1 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ),\n .I1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_30 ),\n .I2(p_95_out),\n .I3(p_98_out),\n .I4(p_154_out),\n .I5(right_gain_pb),\n .O(\\genblk8[7].right_edge_found_pb[7]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h4)) \n \\genblk9[0].fine_delay_incdec_pb[0]_i_7 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_78 ),\n .I1(bit_cnt),\n .O(\\genblk9[0].fine_delay_incdec_pb[0]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hFFDF77DF00000000)) \n idel_adj_inc_i_1\n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_88 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_85 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_140 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_86 ),\n .I4(cal1_wait_r),\n .I5(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_52 ),\n .O(idel_adj_inc_i_1_n_0));\n LUT6 #(\n .INIT(64'hF0F0B1F0F0B0F0F0)) \n idel_pat_detect_valid_r_i_1\n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_186 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_83 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_50 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_86 ),\n .I4(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_85 ),\n .I5(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_87 ),\n .O(idel_pat_detect_valid_r_i_1_n_0));\n FDRE idelay_ce_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(idelay_ce_int),\n .Q(idelay_ce_r1),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE idelay_ce_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(idelay_ce_r1),\n .Q(idelay_ce),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE idelay_inc_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(idelay_inc_int),\n .Q(idelay_inc_r1),\n .R(rstdiv0_sync_r1_reg_rep__9));\n (* syn_maxfan = \"30\" *) \n FDRE idelay_inc_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(idelay_inc_r1),\n .Q(idelay_inc),\n .R(rstdiv0_sync_r1_reg_rep__9));\n LUT6 #(\n .INIT(64'hFFFFFCFF00000080)) \n idelay_ld_done_i_1\n (.I0(u_ddr_phy_wrcal_n_113),\n .I1(u_ddr_phy_wrcal_n_111),\n .I2(u_ddr_phy_wrcal_n_109),\n .I3(u_ddr_phy_wrcal_n_110),\n .I4(u_ddr_phy_wrcal_n_108),\n .I5(u_ddr_phy_wrcal_n_69),\n .O(idelay_ld_done_i_1_n_0));\n LUT4 #(\n .INIT(16'h2F20)) \n idelay_ld_i_1\n (.I0(u_ddr_phy_wrcal_n_4),\n .I1(u_ddr_phy_wrcal_n_109),\n .I2(u_ddr_phy_wrcal_n_116),\n .I3(idelay_ld),\n .O(idelay_ld_i_1_n_0));\n LUT3 #(\n .INIT(8'hB8)) \n inhibit_edge_detect_r_i_1\n (.I0(inhibit_edge_detect_r),\n .I1(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_58 ),\n .I2(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_10 ),\n .O(inhibit_edge_detect_r_i_1_n_0));\n (* ORIG_CELL_NAME = \"init_calib_complete_reg\" *) \n FDRE init_calib_complete_reg\n (.C(CLK),\n .CE(1'b1),\n .D(calib_complete),\n .Q(phy_dout[33]),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* ORIG_CELL_NAME = \"init_calib_complete_reg\" *) \n FDRE init_calib_complete_reg_rep\n (.C(CLK),\n .CE(1'b1),\n .D(calib_complete),\n .Q(\\my_empty_reg[7] ),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* ORIG_CELL_NAME = \"init_calib_complete_reg\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE init_calib_complete_reg_rep__0\n (.C(CLK),\n .CE(1'b1),\n .D(calib_complete),\n .Q(init_calib_complete_reg_rep__0_n_0),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* ORIG_CELL_NAME = \"init_calib_complete_reg\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE init_calib_complete_reg_rep__1\n (.C(CLK),\n .CE(1'b1),\n .D(calib_complete),\n .Q(init_calib_complete_reg_rep__1_n_0),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* ORIG_CELL_NAME = \"init_calib_complete_reg\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE init_calib_complete_reg_rep__10\n (.C(CLK),\n .CE(1'b1),\n .D(calib_complete),\n .Q(init_calib_complete_reg_rep__10_n_0),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* ORIG_CELL_NAME = \"init_calib_complete_reg\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE init_calib_complete_reg_rep__11\n (.C(CLK),\n .CE(1'b1),\n .D(calib_complete),\n .Q(init_calib_complete_reg_rep__11_n_0),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* ORIG_CELL_NAME = \"init_calib_complete_reg\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE init_calib_complete_reg_rep__12\n (.C(CLK),\n .CE(1'b1),\n .D(calib_complete),\n .Q(init_calib_complete_reg_rep__12_n_0),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* ORIG_CELL_NAME = \"init_calib_complete_reg\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE init_calib_complete_reg_rep__13\n (.C(CLK),\n .CE(1'b1),\n .D(calib_complete),\n .Q(init_calib_complete_reg_rep__13_n_0),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* ORIG_CELL_NAME = \"init_calib_complete_reg\" *) \n FDRE init_calib_complete_reg_rep__14\n (.C(CLK),\n .CE(1'b1),\n .D(calib_complete),\n .Q(init_calib_complete_r_reg),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* ORIG_CELL_NAME = \"init_calib_complete_reg\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE init_calib_complete_reg_rep__2\n (.C(CLK),\n .CE(1'b1),\n .D(calib_complete),\n .Q(init_calib_complete_reg_rep__2_n_0),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* ORIG_CELL_NAME = \"init_calib_complete_reg\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE init_calib_complete_reg_rep__3\n (.C(CLK),\n .CE(1'b1),\n .D(calib_complete),\n .Q(init_calib_complete_reg_rep__3_n_0),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* ORIG_CELL_NAME = \"init_calib_complete_reg\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE init_calib_complete_reg_rep__4\n (.C(CLK),\n .CE(1'b1),\n .D(calib_complete),\n .Q(init_calib_complete_reg_rep__4_n_0),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* ORIG_CELL_NAME = \"init_calib_complete_reg\" *) \n FDRE init_calib_complete_reg_rep__5\n (.C(CLK),\n .CE(1'b1),\n .D(calib_complete),\n .Q(\\rd_ptr_timing_reg[0] ),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* ORIG_CELL_NAME = \"init_calib_complete_reg\" *) \n FDRE init_calib_complete_reg_rep__6\n (.C(CLK),\n .CE(1'b1),\n .D(calib_complete),\n .Q(app_zq_r_reg),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* ORIG_CELL_NAME = \"init_calib_complete_reg\" *) \n FDRE init_calib_complete_reg_rep__7\n (.C(CLK),\n .CE(1'b1),\n .D(calib_complete),\n .Q(\\my_empty_reg[7]_0 ),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* ORIG_CELL_NAME = \"init_calib_complete_reg\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE init_calib_complete_reg_rep__8\n (.C(CLK),\n .CE(1'b1),\n .D(calib_complete),\n .Q(init_calib_complete_reg_rep__8_n_0),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* ORIG_CELL_NAME = \"init_calib_complete_reg\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE init_calib_complete_reg_rep__9\n (.C(CLK),\n .CE(1'b1),\n .D(calib_complete),\n .Q(init_calib_complete_reg_rep__9_n_0),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hFFFF0004)) \n init_complete_r_i_1\n (.I0(init_state_r),\n .I1(u_ddr_phy_init_n_105),\n .I2(u_ddr_phy_init_n_104),\n .I3(u_ddr_phy_init_n_470),\n .I4(u_ddr_phy_init_n_18),\n .O(init_complete_r_i_1_n_0));\n LUT5 #(\n .INIT(32'hFFFF0004)) \n init_complete_r_timing_i_1\n (.I0(init_state_r),\n .I1(u_ddr_phy_init_n_105),\n .I2(u_ddr_phy_init_n_104),\n .I3(u_ddr_phy_init_n_470),\n .I4(init_complete_r_timing_orig),\n .O(init_complete_r_timing_i_1_n_0));\n LUT6 #(\n .INIT(64'hAAAAAAAAAABAAAAA)) \n init_dec_done_i_1\n (.I0(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_13 ),\n .I1(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_41 ),\n .I2(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_80 ),\n .I3(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_42 ),\n .I4(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_112 ),\n .I5(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ),\n .O(init_dec_done_i_1_n_0));\n LUT6 #(\n .INIT(64'h00000000000000E2)) \n init_dqsfound_done_r_i_1\n (.I0(rd_data_offset_cal_done),\n .I1(p_1_in27_in),\n .I2(\\rd_byte_data_offset_reg[0]_3 ),\n .I3(rstdiv0_sync_r1_reg_rep__24),\n .I4(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_76 ),\n .I5(p_1_in50_in),\n .O(init_dqsfound_done_r_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair699\" *) \n LUT5 #(\n .INIT(32'h0000AB00)) \n \\input_[0].iserdes_dq_.idelay_finedelay_dq.idelaye2_i_1 \n (.I0(calib_in_common),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .I3(idelay_ce),\n .I4(calib_zero_inputs__0),\n .O(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ));\n (* SOFT_HLUTNM = \"soft_lutpair698\" *) \n LUT5 #(\n .INIT(32'h0000EA00)) \n \\input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_i_1 \n (.I0(calib_in_common),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .I3(idelay_ce),\n .I4(calib_zero_inputs__0),\n .O(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ));\n (* SOFT_HLUTNM = \"soft_lutpair698\" *) \n LUT5 #(\n .INIT(32'h0000BA00)) \n \\input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_i_1__0 \n (.I0(calib_in_common),\n .I1(\\po_rdval_cnt_reg[8] [0]),\n .I2(\\po_rdval_cnt_reg[8] [1]),\n .I3(idelay_ce),\n .I4(calib_zero_inputs__0),\n .O(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair699\" *) \n LUT5 #(\n .INIT(32'h0000BA00)) \n \\input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_i_1__1 \n (.I0(calib_in_common),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .I3(idelay_ce),\n .I4(calib_zero_inputs__0),\n .O(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ));\n ddr3_if_mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay \\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay \n (.CLK(CLK),\n .D_po_coarse_enable110_out(D_po_coarse_enable110_out),\n .Q(\\po_rdval_cnt_reg[8] [1:0]),\n .calib_in_common(calib_in_common),\n .\\calib_zero_inputs_reg[1] ({calib_zero_inputs,calib_zero_inputs__0}),\n .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done),\n .cmd_delay_start0(cmd_delay_start0),\n .cnt_pwron_cke_done_r(cnt_pwron_cke_done_r),\n .ctl_lane_cnt(ctl_lane_cnt),\n .delay_dec_done_reg_0(\\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_12 ),\n .delay_dec_done_reg_1(\\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_13 ),\n .dqs_po_dec_done(dqs_po_dec_done),\n .dqs_wl_po_stg2_c_incdec(dqs_wl_po_stg2_c_incdec),\n .\\init_state_r_reg[0] (\\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_11 ),\n .\\mcGo_r_reg[15] (\\mcGo_r_reg[15] ),\n .p_1_in(p_1_in),\n .pi_fine_dly_dec_done(pi_fine_dly_dec_done),\n .po_cnt_inc_reg_0(\\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_17 ),\n .\\po_counter_read_val_reg[8] (\\po_counter_read_val_reg[8]_0 ),\n .\\po_counter_read_val_reg[8]_0 (\\po_counter_read_val_reg[8]_4 ),\n .\\po_counter_read_val_reg[8]_1 (\\po_counter_read_val_reg[8]_5 ),\n .\\po_counter_read_val_reg[8]_2 (\\po_counter_read_val_reg[8]_18 ),\n .\\po_counter_read_val_reg[8]_3 (\\po_counter_read_val_reg[8]_21 ),\n .\\po_counter_read_val_reg[8]_4 (\\po_counter_read_val_reg[8]_24 ),\n .\\po_counter_read_val_reg[8]_5 (\\po_counter_read_val_reg[8]_27 ),\n .po_en_stg2_f(cmd_po_en_stg2_f),\n .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),\n .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25),\n .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9),\n .\\wait_cnt_r_reg[0]_0 (wait_cnt_r_reg__0_1),\n .\\wait_cnt_r_reg[0]_1 (po_cnt_inc_i_1_n_0),\n .\\wait_cnt_r_reg[0]_2 (po_cnt_dec_i_1_n_0));\n ddr3_if_mig_7series_v4_0_ddr_phy_wrlvl \\mb_wrlvl_inst.u_ddr_phy_wrlvl \n (.CLK(CLK),\n .D({\\u_ocd_po_cntlr/stg2_target_ns ,wl_po_fine_cnt_sel_0}),\n .\\FSM_sequential_wl_state_r_reg[0]_0 (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_8 ),\n .\\FSM_sequential_wl_state_r_reg[0]_1 (wr_level_done_r_i_1_n_0),\n .\\FSM_sequential_wl_state_r_reg[1]_0 (dq_cnt_inc_i_1_n_0),\n .\\FSM_sequential_wl_state_r_reg[2]_0 (wl_edge_detect_valid_r_i_1_n_0),\n .\\FSM_sequential_wl_state_r_reg[2]_1 (wrlvl_rank_done_r_i_1_n_0),\n .O({\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_0 ,\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_1 ,\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_2 ,\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_3 }),\n .Q(\\u_ocd_lim/stg3_init_val ),\n .S(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_59 ),\n .\\byte_r_reg[0] (\\byte_r_reg[0] ),\n .\\byte_r_reg[1] (\\byte_r_reg[1] ),\n .byte_sel_cnt(byte_sel_cnt),\n .\\calib_sel_reg[3] (\\po_rdval_cnt_reg[8] [2]),\n .delay_done_r4_reg(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_106 ),\n .done_dqs_dec239_out(done_dqs_dec239_out),\n .done_dqs_tap_inc(done_dqs_tap_inc),\n .dq_cnt_inc_reg_0(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_56 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ),\n .dqs_po_dec_done(dqs_po_dec_done),\n .dqs_po_en_stg2_f(dqs_po_en_stg2_f),\n .dqs_po_en_stg2_f_reg_0(dqs_po_en_stg2_f_reg),\n .dqs_po_stg2_f_incdec(dqs_po_stg2_f_incdec),\n .dqs_wl_po_stg2_c_incdec(dqs_wl_po_stg2_c_incdec),\n .early1_data_reg(u_ddr_phy_wrcal_n_101),\n .early1_data_reg_0(u_ddr_phy_wrcal_n_73),\n .flag_ck_negedge09_out(flag_ck_negedge09_out),\n .flag_ck_negedge_reg_0(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_47 ),\n .flag_ck_negedge_reg_1(flag_ck_negedge_i_1_n_0),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[0] (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_48 ),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 (\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [0]),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[1] (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_49 ),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 (\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 [1]),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[2] (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_50 ),\n .inhibit_edge_detect_r(inhibit_edge_detect_r),\n .inhibit_edge_detect_r_reg_0(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_58 ),\n .inhibit_edge_detect_r_reg_1(inhibit_edge_detect_r_i_1_n_0),\n .\\lim_state_reg[12] (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_36 ),\n .\\mcGo_r_reg[15] (\\mcGo_r_reg[15] ),\n .my_empty(my_empty),\n .my_empty_6(my_empty_6),\n .my_empty_7(my_empty_7),\n .my_empty_8(my_empty_8),\n .oclkdelay_calib_done_r_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ),\n .oclkdelay_calib_done_r_reg_0(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_56 ),\n .oclkdelay_calib_done_r_reg_1(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_57 ),\n .out({\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_27 ,\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_28 ,\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_29 ,\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_30 ,\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_31 }),\n .p_0_in(p_0_in_2),\n .p_1_in(p_1_in),\n .pi_f_inc_reg(ddr_phy_tempmon_0_n_2),\n .pi_fine_dly_dec_done(pi_fine_dly_dec_done),\n .po_cnt_dec_reg_0(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_46 ),\n .po_cnt_dec_reg_1(po_cnt_dec_reg),\n .\\po_counter_read_val_reg[5] ({\\po_counter_read_val_reg[5] [5:4],\\po_counter_read_val_reg[5] [2:1]}),\n .\\po_counter_read_val_reg[8] (\\po_counter_read_val_reg[8]_30 ),\n .\\po_counter_read_val_reg[8]_0 (\\po_counter_read_val_reg[8]_31 ),\n .\\po_rdval_cnt_reg[0]_0 (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_38 ),\n .\\po_stg2_wrcal_cnt_reg[0] (u_ddr_phy_wrcal_n_100),\n .\\po_stg2_wrcal_cnt_reg[1] (u_ddr_phy_wrcal_n_98),\n .\\po_stg2_wrcal_cnt_reg[2] ({po_stg2_wrcal_cnt,\\idelay_tap_cnt_r_reg[0][3][0] }),\n .\\po_stg2_wrcal_cnt_reg[2]_0 (u_ddr_phy_wrcal_n_97),\n .\\prbs_dqs_cnt_r_reg[2] (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_158 ),\n .\\rank_cnt_r_reg[0]_0 (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_41 ),\n .\\rank_cnt_r_reg[0]_1 (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_42 ),\n .\\rd_data_edge_detect_r_reg[0]_0 (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_7 ),\n .\\rd_data_edge_detect_r_reg[0]_1 (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_10 ),\n .rstdiv0_sync_r1_reg_rep(rstdiv0_sync_r1_reg_rep),\n .rstdiv0_sync_r1_reg_rep__15(rstdiv0_sync_r1_reg_rep__14[0]),\n .rstdiv0_sync_r1_reg_rep__16(rstdiv0_sync_r1_reg_rep__16),\n .rstdiv0_sync_r1_reg_rep__17(rstdiv0_sync_r1_reg_rep__17),\n .rstdiv0_sync_r1_reg_rep__18(rstdiv0_sync_r1_reg_rep__18),\n .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23),\n .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25),\n .\\single_rank.done_dqs_dec_reg_0 (wr_level_done_i_1_n_0),\n .stable_cnt1(stable_cnt1),\n .stable_cnt227_in(stable_cnt227_in),\n .\\stable_cnt_reg[3]_0 (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_40 ),\n .\\stg2_r_reg[0] (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_37 ),\n .\\stg2_r_reg[4] (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_24 ),\n .\\stg2_r_reg[5] (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_26 ),\n .\\stg2_tap_cnt_reg[2] (\\u_ocd_lim/stg2_tap_cnt_reg ),\n .\\stg2_target_r_reg[4] (wl_po_fine_cnt_sel_0__0),\n .\\stg3_dec_val_reg[2] (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_25 ),\n .\\stg3_dec_val_reg[2]_0 (\\u_ocd_lim/stg3_dec_val00_out ),\n .\\stg3_r_reg[5] ({\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_29 ,\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_30 ,\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_31 }),\n .\\wait_cnt_reg[0]_0 (po_cnt_dec_i_1__0_n_0),\n .wl_sm_start(wl_sm_start),\n .wr_level_done_r1_reg_0(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_0 ),\n .wr_level_done_r_reg_0(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_54 ),\n .wr_lvl_start_reg(u_ddr_phy_init_n_790),\n .wrlvl_byte_done(wrlvl_byte_done),\n .wrlvl_byte_redo(wrlvl_byte_redo),\n .wrlvl_byte_redo_r(wrlvl_byte_redo_r),\n .wrlvl_byte_redo_reg(u_ddr_phy_wrcal_n_102),\n .wrlvl_done_r_reg(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_12 ),\n .wrlvl_final_mux(wrlvl_final_mux),\n .wrlvl_final_r(wrlvl_final_r),\n .wrlvl_rank_done(wrlvl_rank_done),\n .wrlvl_rank_done_r_reg_0(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_55 ),\n .\\wrlvl_redo_corse_inc_reg[2]_0 (final_coarse_tap));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_1\n (.I0(init_calib_complete_reg_rep__13_n_0),\n .I1(mc_cas_n[1]),\n .O(phy_dout[32]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_1__1\n (.I0(\\my_empty_reg[7]_0 ),\n .I1(Q[260]),\n .O(\\my_empty_reg[7]_1 [65]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_1__2\n (.I0(\\my_empty_reg[7]_0 ),\n .I1(Q[261]),\n .O(\\my_empty_reg[7]_2 [65]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_1__3\n (.I0(\\my_empty_reg[7]_0 ),\n .I1(Q[262]),\n .O(\\my_empty_reg[7]_3 [65]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_1__4\n (.I0(\\my_empty_reg[7]_0 ),\n .I1(Q[263]),\n .O(\\my_empty_reg[7]_4 [65]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_2__1\n (.I0(\\my_empty_reg[7]_0 ),\n .I1(Q[256]),\n .O(\\my_empty_reg[7]_1 [64]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_2__2\n (.I0(\\my_empty_reg[7]_0 ),\n .I1(Q[257]),\n .O(\\my_empty_reg[7]_2 [64]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_2__3\n (.I0(\\my_empty_reg[7]_0 ),\n .I1(Q[258]),\n .O(\\my_empty_reg[7]_3 [64]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_2__4\n (.I0(\\my_empty_reg[7]_0 ),\n .I1(Q[259]),\n .O(\\my_empty_reg[7]_4 [64]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_3__1\n (.I0(\\my_empty_reg[7]_0 ),\n .I1(Q[268]),\n .O(\\my_empty_reg[7]_1 [67]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_3__2\n (.I0(\\my_empty_reg[7]_0 ),\n .I1(Q[269]),\n .O(\\my_empty_reg[7]_2 [67]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_3__3\n (.I0(\\my_empty_reg[7]_0 ),\n .I1(Q[270]),\n .O(\\my_empty_reg[7]_3 [67]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_3__4\n (.I0(\\my_empty_reg[7]_0 ),\n .I1(Q[271]),\n .O(\\my_empty_reg[7]_4 [67]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_4__0\n (.I0(\\my_empty_reg[7]_0 ),\n .I1(Q[264]),\n .O(\\my_empty_reg[7]_1 [66]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_4__1\n (.I0(\\my_empty_reg[7]_0 ),\n .I1(Q[265]),\n .O(\\my_empty_reg[7]_2 [66]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_4__2\n (.I0(\\my_empty_reg[7]_0 ),\n .I1(Q[266]),\n .O(\\my_empty_reg[7]_3 [66]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_4__3\n (.I0(\\my_empty_reg[7]_0 ),\n .I1(Q[267]),\n .O(\\my_empty_reg[7]_4 [66]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_5\n (.I0(\\my_empty_reg[7]_0 ),\n .I1(Q[276]),\n .O(\\my_empty_reg[7]_1 [69]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_5__0\n (.I0(\\my_empty_reg[7]_0 ),\n .I1(Q[277]),\n .O(\\my_empty_reg[7]_2 [69]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_5__1\n (.I0(\\my_empty_reg[7]_0 ),\n .I1(Q[278]),\n .O(\\my_empty_reg[7]_3 [69]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_5__2\n (.I0(\\my_empty_reg[7]_0 ),\n .I1(Q[279]),\n .O(\\my_empty_reg[7]_4 [69]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_6\n (.I0(\\my_empty_reg[7]_0 ),\n .I1(Q[272]),\n .O(\\my_empty_reg[7]_1 [68]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_6__0\n (.I0(\\my_empty_reg[7]_0 ),\n .I1(Q[273]),\n .O(\\my_empty_reg[7]_2 [68]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_6__1\n (.I0(\\my_empty_reg[7]_0 ),\n .I1(Q[274]),\n .O(\\my_empty_reg[7]_3 [68]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_6__2\n (.I0(\\my_empty_reg[7]_0 ),\n .I1(Q[275]),\n .O(\\my_empty_reg[7]_4 [68]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_78_79_i_1\n (.I0(\\my_empty_reg[7]_0 ),\n .I1(Q[284]),\n .O(\\my_empty_reg[7]_1 [71]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_78_79_i_1__0\n (.I0(\\my_empty_reg[7]_0 ),\n .I1(Q[285]),\n .O(\\my_empty_reg[7]_2 [71]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_78_79_i_1__1\n (.I0(\\my_empty_reg[7]_0 ),\n .I1(Q[286]),\n .O(\\my_empty_reg[7]_3 [71]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_78_79_i_1__2\n (.I0(\\my_empty_reg[7]_0 ),\n .I1(Q[287]),\n .O(\\my_empty_reg[7]_4 [71]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_78_79_i_2\n (.I0(\\my_empty_reg[7]_0 ),\n .I1(Q[280]),\n .O(\\my_empty_reg[7]_1 [70]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_78_79_i_2__0\n (.I0(\\my_empty_reg[7]_0 ),\n .I1(Q[281]),\n .O(\\my_empty_reg[7]_2 [70]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_78_79_i_2__1\n (.I0(\\my_empty_reg[7]_0 ),\n .I1(Q[282]),\n .O(\\my_empty_reg[7]_3 [70]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_78_79_i_2__2\n (.I0(\\my_empty_reg[7]_0 ),\n .I1(Q[283]),\n .O(\\my_empty_reg[7]_4 [70]));\n LUT6 #(\n .INIT(64'hAFFFFFFF04000000)) \n mpr_dec_cpt_r_i_1\n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_84 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_92 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_85 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_102 ),\n .I4(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_190 ),\n .I5(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_51 ),\n .O(mpr_dec_cpt_r_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair718\" *) \n LUT4 #(\n .INIT(16'h2F20)) \n mpr_last_byte_done_i_1\n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_83 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_183 ),\n .I3(mpr_last_byte_done),\n .O(mpr_last_byte_done_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFFFC8C00000080)) \n mpr_rank_done_r_i_1\n (.I0(cal1_cnt_cpt_r1),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_83 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_84 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_189 ),\n .I4(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_184 ),\n .I5(mpr_rnk_done),\n .O(mpr_rank_done_r_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair731\" *) \n LUT2 #(\n .INIT(4'hE)) \n mpr_rdlvl_done_r_i_1\n (.I0(rdlvl_stg1_done_int),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ),\n .O(mpr_rdlvl_done_r_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFEFFFF00020000)) \n new_cnt_dqs_r_i_1\n (.I0(new_cnt_dqs_r),\n .I1(prbs_state_r[4]),\n .I2(prbs_state_r[1]),\n .I3(prbs_state_r[2]),\n .I4(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_113 ),\n .I5(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_13 ),\n .O(new_cnt_dqs_r_i_1_n_0));\n LUT6 #(\n .INIT(64'h8F888FFF80888000)) \n no_err_win_detected_latch_i_1\n (.I0(prbs_state_r[3]),\n .I1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_11 ),\n .I2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_103 ),\n .I3(prbs_state_r[0]),\n .I4(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_98 ),\n .I5(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_35 ),\n .O(no_err_win_detected_latch_i_1_n_0));\n LUT6 #(\n .INIT(64'hF0F0F4F0B0B0F0F0)) \n num_samples_done_ind_i_1\n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_106 ),\n .I1(prbs_state_r[4]),\n .I2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_34 ),\n .I3(num_samples_done_r),\n .I4(prbs_state_r[1]),\n .I5(prbs_state_r[0]),\n .O(num_samples_done_ind_i_1_n_0));\n ddr3_if_mig_7series_v4_0_ddr_phy_oclkdelay_cal \\oclk_calib.u_ddr_phy_oclkdelay_cal \n (.CLK(CLK),\n .D(\\u_ocd_lim/stg3_dec_val00_out ),\n .D_po_sel_fine_oclk_delay125_out(D_po_sel_fine_oclk_delay125_out),\n .O({\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_0 ,\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_1 ,\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_2 ,\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_3 }),\n .Q(\\po_rdval_cnt_reg[8] [1:0]),\n .S(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_59 ),\n .\\byte_r_reg[0] (\\byte_r_reg[0] ),\n .\\byte_r_reg[0]_0 (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_24 ),\n .\\byte_r_reg[0]_1 (\\byte_r_reg[0]_0 ),\n .\\byte_r_reg[1] (\\byte_r_reg[1] ),\n .\\cal2_state_r_reg[0] (\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_58 ),\n .calib_in_common(calib_in_common),\n .\\calib_zero_inputs_reg[1] ({calib_zero_inputs,calib_zero_inputs__0}),\n .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done),\n .cnt_cmd_done_r(cnt_cmd_done_r),\n .\\cnt_shift_r_reg[0] (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_106 ),\n .complex_ocal_num_samples_done_r(complex_ocal_num_samples_done_r),\n .complex_ocal_rd_victim_sel(complex_ocal_rd_victim_sel),\n .complex_ocal_ref_req(complex_ocal_ref_req),\n .complex_oclk_calib_resume(complex_oclk_calib_resume),\n .done_r_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_13 ),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[0] (\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_56 ),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[1] (\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_57 ),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\phaser_in_gen.phaser_in_i_12__0_n_0 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_0 (\\phaser_in_gen.phaser_in_i_12__2_n_0 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_1 (\\phaser_in_gen.phaser_in_i_12__1_n_0 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_2 (\\phaser_in_gen.phaser_in_i_12_n_0 ),\n .\\init_state_r_reg[0] (\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_49 ),\n .\\init_state_r_reg[0]_0 (u_ddr_phy_init_n_114),\n .\\init_state_r_reg[0]_1 (u_ddr_phy_init_n_478),\n .\\init_state_r_reg[2] (\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_48 ),\n .\\init_state_r_reg[4] (\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_47 ),\n .\\init_state_r_reg[4]_0 (\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_54 ),\n .\\init_state_r_reg[4]_1 ({u_ddr_phy_init_n_105,u_ddr_phy_init_n_106,u_ddr_phy_init_n_108}),\n .\\init_state_r_reg[5] (\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_50 ),\n .\\init_state_r_reg[5]_0 (\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_51 ),\n .\\init_state_r_reg[5]_1 (\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_53 ),\n .\\init_state_r_reg[6] (\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_52 ),\n .lim2init_prech_req(lim2init_prech_req),\n .\\mmcm_current_reg[0] (\\mmcm_current_reg[0] ),\n .\\mmcm_init_trail_reg[0] (\\mmcm_init_trail_reg[0] ),\n .mpr_rdlvl_done_r_reg(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ),\n .ocal_last_byte_done(ocal_last_byte_done),\n .ocal_last_byte_done_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_4 ),\n .ocal_last_byte_done_reg_0(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_55 ),\n .ocd_prech_req(ocd_prech_req),\n .oclkdelay_calib_done_r_reg(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_159 ),\n .oclkdelay_calib_start_int_reg(u_ddr_phy_init_n_462),\n .oclkdelay_calib_start_int_reg_0(u_ddr_phy_init_n_24),\n .oclkdelay_center_calib_start_r_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_15 ),\n .oclkdelay_int_ref_req_reg(u_ddr_phy_init_n_477),\n .pd_out(pd_out),\n .phy_rddata_en(phy_rddata_en),\n .phy_rddata_en_1(phy_rddata_en_1),\n .pi_stg2_rdlvl_cnt(pi_stg2_rdlvl_cnt),\n .\\po_counter_read_val_reg[2] (\\po_counter_read_val_reg[2] ),\n .\\po_counter_read_val_reg[5] (\\po_counter_read_val_reg[5] ),\n .\\po_counter_read_val_reg[8] (\\po_counter_read_val_reg[8]_3 ),\n .\\po_counter_read_val_reg[8]_0 (\\po_counter_read_val_reg[8]_8 ),\n .\\po_counter_read_val_reg[8]_1 (\\po_counter_read_val_reg[8]_11 ),\n .\\po_counter_read_val_reg[8]_2 (\\po_counter_read_val_reg[8]_12 ),\n .\\po_counter_read_val_reg[8]_3 (\\po_counter_read_val_reg[8]_13 ),\n .\\po_counter_read_val_reg[8]_4 (\\po_counter_read_val_reg[8]_14 ),\n .\\po_counter_read_val_reg[8]_5 (\\po_counter_read_val_reg[8]_15 ),\n .po_en_stg23(po_en_stg23),\n .po_stg23_incdec(po_stg23_incdec),\n .\\po_stg2_wrcal_cnt_reg[0] (u_ddr_phy_wrcal_n_105),\n .\\po_stg2_wrcal_cnt_reg[1] (u_ddr_phy_wrcal_n_106),\n .poc_sample_pd(poc_sample_pd),\n .prbs_rdlvl_done_reg(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_45 ),\n .prbs_rdlvl_done_reg_rep(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_51 ),\n .prech_done(prech_done),\n .prech_req_posedge_r_reg(u_ddr_phy_init_n_9),\n .psdone(psdone),\n .\\qcntr_r_reg[0] (\\qcntr_r_reg[0] ),\n .rd_active_r1(rd_active_r1),\n .rd_active_r2(rd_active_r2),\n .rdlvl_stg1_start_reg(u_ddr_phy_init_n_33),\n .\\resume_wait_r_reg[5] (E),\n .rstdiv0_sync_r1_reg_rep(rstdiv0_sync_r1_reg_rep),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10),\n .rstdiv0_sync_r1_reg_rep__11(rstdiv0_sync_r1_reg_rep__11),\n .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),\n .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25),\n .rstdiv0_sync_r1_reg_rep__26(rstdiv0_sync_r1_reg_rep__26),\n .rstdiv0_sync_r1_reg_rep__26_0(rstdiv0_sync_r1_reg_rep__26_0),\n .rstdiv0_sync_r1_reg_rep__26_1(rstdiv0_sync_r1_reg_rep__26_1),\n .rstdiv0_sync_r1_reg_rep__26_2(rstdiv0_sync_r1_reg_rep__26_2),\n .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9),\n .\\samps_r_reg[9] (\\samps_r_reg[9] ),\n .\\sm_r_reg[0] (\\sm_r_reg[0] ),\n .\\sm_r_reg[0]_0 (\\sm_r_reg[0]_0 ),\n .sr_valid_r108_out(sr_valid_r108_out),\n .\\stg2_tap_cnt_reg[0] (\\stg2_tap_cnt_reg[0] ),\n .\\stg2_tap_cnt_reg[2] (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_36 ),\n .\\stg2_tap_cnt_reg[3] (\\u_ocd_lim/stg2_tap_cnt_reg ),\n .\\stg2_target_r_reg[8] ({\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_29 ,\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_30 ,\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_31 }),\n .stg3_dec2init_val_r_reg(stg3_dec2init_val_r_reg),\n .stg3_inc2init_val_r_reg(stg3_inc2init_val_r_reg),\n .\\stg3_r_reg[0] (\\stg3_r_reg[0] ),\n .\\stg3_tap_cnt_reg[2] (\\u_ocd_lim/stg3_init_val ),\n .\\wl_po_fine_cnt_reg[14] (wl_po_fine_cnt_sel_0__0),\n .\\wl_po_fine_cnt_reg[17] (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_26 ),\n .\\wl_po_fine_cnt_reg[18] (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_37 ),\n .\\wl_po_fine_cnt_reg[23] ({\\u_ocd_po_cntlr/stg2_target_ns ,wl_po_fine_cnt_sel_0}),\n .\\wl_po_fine_cnt_reg[3] (\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_25 ),\n .wr_level_done_reg(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_12 ),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] (\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_28 ),\n .wrlvl_byte_done(wrlvl_byte_done),\n .wrlvl_final_mux(wrlvl_final_mux),\n .wrlvl_final_mux_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ),\n .\\zero2fuzz_r_reg[0] (\\zero2fuzz_r_reg[0] ));\n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_10__6\n (.I0(\\cmd_pipe_plus.mc_address_reg[44] [35]),\n .I1(\\my_empty_reg[7] ),\n .I2(\\rd_ptr_reg[3]_0 [2]),\n .I3(\\my_empty_reg[1]_1 ),\n .O(\\my_full_reg[3] [2]));\n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_11__2\n (.I0(\\rd_ptr_timing_reg[0] ),\n .I1(mc_cas_n[1]),\n .I2(\\rd_ptr_reg[3]_0 [1]),\n .I3(\\my_empty_reg[1]_1 ),\n .O(\\my_full_reg[3] [1]));\n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_12__6\n (.I0(\\cmd_pipe_plus.mc_address_reg[44] [13]),\n .I1(\\my_empty_reg[7] ),\n .I2(\\rd_ptr_reg[3]_0 [0]),\n .I3(\\my_empty_reg[1]_1 ),\n .O(\\my_full_reg[3] [0]));\n LUT4 #(\n .INIT(16'hBBF0)) \n out_fifo_i_15__6\n (.I0(mc_we_n[2]),\n .I1(\\my_empty_reg[7] ),\n .I2(mem_out[5]),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D1[2]));\n LUT4 #(\n .INIT(16'hBBF0)) \n out_fifo_i_17__5\n (.I0(mc_we_n[0]),\n .I1(\\my_empty_reg[7] ),\n .I2(mem_out[3]),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D1[0]));\n LUT4 #(\n .INIT(16'hBBF0)) \n out_fifo_i_17__6\n (.I0(mc_cas_n[2]),\n .I1(\\my_empty_reg[7] ),\n .I2(\\rd_ptr_reg[3] [2]),\n .I3(\\my_empty_reg[1] ),\n .O(D2[2]));\n LUT4 #(\n .INIT(16'hBBF0)) \n out_fifo_i_19__6\n (.I0(mc_cas_n[0]),\n .I1(\\my_empty_reg[7] ),\n .I2(\\rd_ptr_reg[3] [0]),\n .I3(\\my_empty_reg[1] ),\n .O(D2[0]));\n LUT4 #(\n .INIT(16'hBBF0)) \n out_fifo_i_25__5\n (.I0(mc_ras_n[2]),\n .I1(\\my_empty_reg[7] ),\n .I2(\\rd_ptr_reg[3] [5]),\n .I3(\\my_empty_reg[1] ),\n .O(D3[2]));\n LUT4 #(\n .INIT(16'hBBF0)) \n out_fifo_i_27__5\n (.I0(mc_ras_n[0]),\n .I1(\\my_empty_reg[7] ),\n .I2(\\rd_ptr_reg[3] [3]),\n .I3(\\my_empty_reg[1] ),\n .O(D3[0]));\n LUT4 #(\n .INIT(16'hBBF0)) \n out_fifo_i_7__6\n (.I0(mc_ras_n[2]),\n .I1(\\my_empty_reg[7] ),\n .I2(mem_out[2]),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D0[2]));\n LUT4 #(\n .INIT(16'hBBF0)) \n out_fifo_i_9__6\n (.I0(mc_cs_n),\n .I1(\\my_empty_reg[7] ),\n .I2(mem_out[0]),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair727\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\periodic_read_request.periodic_rd_r_lcl_i_1 \n (.I0(app_zq_r_reg),\n .O(maint_prescaler_r1));\n (* SOFT_HLUTNM = \"soft_lutpair724\" *) \n LUT3 #(\n .INIT(8'hEA)) \n \\phaser_in_gen.phaser_in_i_12 \n (.I0(calib_in_common),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .O(\\phaser_in_gen.phaser_in_i_12_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair725\" *) \n LUT3 #(\n .INIT(8'hBA)) \n \\phaser_in_gen.phaser_in_i_12__0 \n (.I0(calib_in_common),\n .I1(\\po_rdval_cnt_reg[8] [0]),\n .I2(\\po_rdval_cnt_reg[8] [1]),\n .O(\\phaser_in_gen.phaser_in_i_12__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair725\" *) \n LUT3 #(\n .INIT(8'hBA)) \n \\phaser_in_gen.phaser_in_i_12__1 \n (.I0(calib_in_common),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .O(\\phaser_in_gen.phaser_in_i_12__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair724\" *) \n LUT3 #(\n .INIT(8'hAB)) \n \\phaser_in_gen.phaser_in_i_12__2 \n (.I0(calib_in_common),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .O(\\phaser_in_gen.phaser_in_i_12__2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair708\" *) \n LUT4 #(\n .INIT(16'h00F8)) \n \\phaser_in_gen.phaser_in_i_2 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(calib_zero_inputs__0),\n .O(\\pi_dqs_found_lanes_r1_reg[3] ));\n (* SOFT_HLUTNM = \"soft_lutpair717\" *) \n LUT4 #(\n .INIT(16'h00F2)) \n \\phaser_in_gen.phaser_in_i_2__0 \n (.I0(\\po_rdval_cnt_reg[8] [1]),\n .I1(\\po_rdval_cnt_reg[8] [0]),\n .I2(calib_in_common),\n .I3(calib_zero_inputs__0),\n .O(\\pi_dqs_found_lanes_r1_reg[2] ));\n (* SOFT_HLUTNM = \"soft_lutpair721\" *) \n LUT4 #(\n .INIT(16'h00F2)) \n \\phaser_in_gen.phaser_in_i_2__1 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(calib_zero_inputs__0),\n .O(\\pi_dqs_found_lanes_r1_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair721\" *) \n LUT4 #(\n .INIT(16'h00F1)) \n \\phaser_in_gen.phaser_in_i_2__2 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(calib_in_common),\n .I3(calib_zero_inputs__0),\n .O(\\pi_dqs_found_lanes_r1_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair720\" *) \n LUT4 #(\n .INIT(16'h0040)) \n phaser_out_i_2\n (.I0(calib_in_common),\n .I1(\\po_rdval_cnt_reg[8] [0]),\n .I2(\\po_rdval_cnt_reg[8] [1]),\n .I3(calib_zero_inputs),\n .O(D_po_counter_read_en122_out));\n (* SOFT_HLUTNM = \"soft_lutpair722\" *) \n LUT4 #(\n .INIT(16'h0001)) \n phaser_out_i_2__0\n (.I0(calib_in_common),\n .I1(\\po_rdval_cnt_reg[8] [0]),\n .I2(\\po_rdval_cnt_reg[8] [1]),\n .I3(calib_zero_inputs),\n .O(\\po_counter_read_val_reg[8] ));\n (* SOFT_HLUTNM = \"soft_lutpair720\" *) \n LUT4 #(\n .INIT(16'h0004)) \n phaser_out_i_2__5\n (.I0(calib_in_common),\n .I1(\\po_rdval_cnt_reg[8] [1]),\n .I2(\\po_rdval_cnt_reg[8] [0]),\n .I3(calib_zero_inputs),\n .O(\\po_counter_read_val_reg[8]_28 ));\n (* SOFT_HLUTNM = \"soft_lutpair722\" *) \n LUT4 #(\n .INIT(16'h0004)) \n phaser_out_i_2__6\n (.I0(calib_in_common),\n .I1(\\po_rdval_cnt_reg[8] [0]),\n .I2(\\po_rdval_cnt_reg[8] [1]),\n .I3(calib_zero_inputs),\n .O(\\po_counter_read_val_reg[8]_29 ));\n LUT4 #(\n .INIT(16'hFFFE)) \n phy_if_reset0\n (.I0(reset_if),\n .I1(phy_if_reset_w),\n .I2(mpr_end_if_reset),\n .I3(wrlvl_final_if_rst),\n .O(phy_if_reset0__0));\n FDRE phy_if_reset_reg\n (.C(CLK),\n .CE(1'b1),\n .D(phy_if_reset0__0),\n .Q(phy_if_reset),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0000000000400000)) \n pi_cnt_dec_i_1\n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_141 ),\n .I1(wait_cnt_r_reg__0[0]),\n .I2(dqs_po_dec_done_r2),\n .I3(wait_cnt_r_reg__0[1]),\n .I4(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_96 ),\n .I5(rstdiv0_sync_r1_reg_rep__23),\n .O(pi_cnt_dec_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFEFFFFFFFE0000)) \n \\pi_dqs_found_any_bank[0]_i_1 \n (.I0(p_3_in25_in),\n .I1(p_2_in24_in),\n .I2(p_0_in23_in),\n .I3(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_5 ),\n .I4(u_ddr_phy_init_n_502),\n .I5(pi_dqs_found_any_bank),\n .O(\\pi_dqs_found_any_bank[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair726\" *) \n LUT3 #(\n .INIT(8'h08)) \n pi_stg2_f_incdec_timing_i_1\n (.I0(prbs_tap_inc_r),\n .I1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_4 ),\n .I2(rstdiv0_sync_r1_reg_rep__23),\n .O(pi_stg2_f_incdec_timing_i_1_n_0));\n LUT3 #(\n .INIT(8'h04)) \n pi_stg2_load_timing_i_1\n (.I0(regl_dqs_cnt),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_101 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_99 ),\n .O(pi_stg2_load_timing_i_1_n_0));\n LUT6 #(\n .INIT(64'h0000000000800000)) \n po_cnt_dec_i_1\n (.I0(wait_cnt_r_reg__0_1),\n .I1(pi_fine_dly_dec_done),\n .I2(dqs_po_dec_done),\n .I3(\\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_17 ),\n .I4(\\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_12 ),\n .I5(rstdiv0_sync_r1_reg_rep__25),\n .O(po_cnt_dec_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair723\" *) \n LUT3 #(\n .INIT(8'h04)) \n po_cnt_dec_i_1__0\n (.I0(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_46 ),\n .I1(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_38 ),\n .I2(rstdiv0_sync_r1_reg_rep__23),\n .O(po_cnt_dec_i_1__0_n_0));\n LUT5 #(\n .INIT(32'h00000020)) \n po_cnt_inc_i_1\n (.I0(wait_cnt_r_reg__0_1),\n .I1(\\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_17 ),\n .I2(\\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_13 ),\n .I3(\\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_12 ),\n .I4(rstdiv0_sync_r1_reg_rep__24),\n .O(po_cnt_inc_i_1_n_0));\n LUT4 #(\n .INIT(16'hFFFE)) \n po_en_stg2_f0\n (.I0(ck_po_stg2_f_en),\n .I1(dqs_po_en_stg2_f),\n .I2(cmd_po_en_stg2_f),\n .I3(po_en_stg23),\n .O(po_enstg2_f));\n LUT3 #(\n .INIT(8'hFE)) \n po_stg2_f_incdec0\n (.I0(ck_po_stg2_f_indec),\n .I1(dqs_po_stg2_f_incdec),\n .I2(po_stg23_incdec),\n .O(po_stg2_fincdec));\n LUT2 #(\n .INIT(4'h6)) \n \\prbs_dqs_cnt_r[0]_i_1 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_110 ),\n .I1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_9 ),\n .O(\\prbs_dqs_cnt_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair719\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\prbs_dqs_cnt_r[1]_i_1 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_9 ),\n .I1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_110 ),\n .I2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_10 ),\n .O(\\prbs_dqs_cnt_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair719\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\prbs_dqs_cnt_r[2]_i_1 \n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_9 ),\n .I1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_10 ),\n .I2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_110 ),\n .I3(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_50 ),\n .O(\\prbs_dqs_cnt_r[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair726\" *) \n LUT3 #(\n .INIT(8'h02)) \n prbs_dqs_tap_limit_r_i_1\n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_54 ),\n .I1(rstdiv0_sync_r1_reg_rep__23),\n .I2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_13 ),\n .O(prbs_dqs_tap_limit_r_i_1_n_0));\n LUT6 #(\n .INIT(64'hF2FFFFFF02000000)) \n prbs_found_1st_edge_r_i_1\n (.I0(prbs_state_r178_out),\n .I1(prbs_state_r[3]),\n .I2(prbs_state_r[0]),\n .I3(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_107 ),\n .I4(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_99 ),\n .I5(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_14 ),\n .O(prbs_found_1st_edge_r_i_1_n_0));\n LUT6 #(\n .INIT(64'hDFDFF5F502000000)) \n prbs_last_byte_done_i_1\n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_107 ),\n .I1(prbs_state_r[0]),\n .I2(prbs_state_r[1]),\n .I3(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_112 ),\n .I4(prbs_state_r[3]),\n .I5(prbs_last_byte_done),\n .O(prbs_last_byte_done_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFF337F300000400)) \n prbs_prech_req_r_i_1\n (.I0(prech_done),\n .I1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_107 ),\n .I2(prbs_state_r[1]),\n .I3(prbs_state_r[3]),\n .I4(prbs_state_r[0]),\n .I5(prbs_prech_req_r),\n .O(prbs_prech_req_r_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFF7FFF00004000)) \n prbs_rdlvl_done_i_1\n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_44 ),\n .I1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_111 ),\n .I2(prbs_state_r[3]),\n .I3(prbs_state_r[1]),\n .I4(prbs_state_r[2]),\n .I5(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_51 ),\n .O(prbs_rdlvl_done_i_1_n_0));\n LUT6 #(\n .INIT(64'hA8AAFFFFA8AA0000)) \n prbs_tap_en_r_i_1\n (.I0(prbs_state_r[0]),\n .I1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_100 ),\n .I2(prbs_state_r[1]),\n .I3(prbs_state_r[3]),\n .I4(prbs_tap_en_r),\n .I5(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_4 ),\n .O(prbs_tap_en_r_i_1_n_0));\n LUT6 #(\n .INIT(64'h8A00FFFF8A000000)) \n prbs_tap_inc_r_i_1\n (.I0(prbs_state_r[0]),\n .I1(prbs_state_r[1]),\n .I2(prbs_state_r[3]),\n .I3(prbs_state_r[2]),\n .I4(prbs_tap_en_r),\n .I5(prbs_tap_inc_r),\n .O(prbs_tap_inc_r_i_1_n_0));\n LUT3 #(\n .INIT(8'hBA)) \n prech_pending_r_i_1\n (.I0(u_ddr_phy_init_n_9),\n .I1(u_ddr_phy_init_n_468),\n .I2(prech_pending_r),\n .O(prech_pending_r_i_1_n_0));\n LUT6 #(\n .INIT(64'h0000000000707070)) \n rank_done_r_i_1\n (.I0(pi_dqs_found_all_bank_r[1]),\n .I1(pi_dqs_found_all_bank_r[0]),\n .I2(p_1_in27_in),\n .I3(rd_data_offset_cal_done),\n .I4(\\rd_byte_data_offset_reg[0]_3 ),\n .I5(rstdiv0_sync_r1_reg_rep__24),\n .O(rank_done_r_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair723\" *) \n LUT3 #(\n .INIT(8'hFE)) \n \\rd_addr[7]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__23),\n .I1(complex_ocal_reset_rd_addr),\n .I2(reset_rd_addr),\n .O(\\rd_addr[7]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair718\" *) \n LUT4 #(\n .INIT(16'h8F80)) \n rdlvl_last_byte_done_int_i_1\n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_83 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_183 ),\n .I3(rdlvl_last_byte_done),\n .O(rdlvl_last_byte_done_int_i_1_n_0));\n LUT5 #(\n .INIT(32'h70FF7000)) \n rdlvl_pi_incdec_i_1\n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_86 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_87 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_180 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_185 ),\n .I4(rdlvl_pi_incdec),\n .O(rdlvl_pi_incdec_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFFFC8C00000080)) \n rdlvl_rank_done_r_i_1\n (.I0(cal1_cnt_cpt_r1),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_83 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_84 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_188 ),\n .I4(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_184 ),\n .I5(rdlvl_stg1_rank_done),\n .O(rdlvl_rank_done_r_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFF00010000)) \n rdlvl_start_pre_i_1\n (.I0(u_ddr_phy_init_n_102),\n .I1(u_ddr_phy_init_n_469),\n .I2(u_ddr_phy_init_n_108),\n .I3(u_ddr_phy_init_n_107),\n .I4(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_10 ),\n .I5(rdlvl_start_pre),\n .O(rdlvl_start_pre_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair731\" *) \n LUT3 #(\n .INIT(8'hB8)) \n rdlvl_stg1_done_int_i_1\n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ),\n .I1(rdlvl_stg1_done_int),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_56 ),\n .O(rdlvl_stg1_done_int_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFEFFFF00020000)) \n rdlvl_stg1_start_i_1\n (.I0(rdlvl_start_dly0_r),\n .I1(u_ddr_phy_init_n_473),\n .I2(u_ddr_phy_init_n_108),\n .I3(u_ddr_phy_init_n_107),\n .I4(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_10 ),\n .I5(u_ddr_phy_init_n_33),\n .O(rdlvl_stg1_start_i_1_n_0));\n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/reset_if_r8_reg_srl8 \" *) \n SRL16E reset_if_r8_reg_srl8\n (.A0(1'b1),\n .A1(1'b1),\n .A2(1'b1),\n .A3(1'b0),\n .CE(1'b1),\n .CLK(CLK),\n .D(reset_if),\n .Q(reset_if_r8_reg_srl8_n_0));\n FDRE reset_if_r9_reg\n (.C(CLK),\n .CE(1'b1),\n .D(reset_if_r8_reg_srl8_n_0),\n .Q(reset_if_r9),\n .R(1'b0));\n FDRE reset_if_reg\n (.C(CLK),\n .CE(1'b1),\n .D(u_ddr_phy_init_n_101),\n .Q(reset_if),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFEFFEFF00000010)) \n reset_rd_addr_i_1\n (.I0(prbs_state_r[4]),\n .I1(prbs_state_r[2]),\n .I2(prbs_state_r[3]),\n .I3(prbs_state_r[0]),\n .I4(prbs_state_r[1]),\n .I5(reset_rd_addr),\n .O(reset_rd_addr_i_1_n_0));\n LUT5 #(\n .INIT(32'h04FF0400)) \n right_edge_found_i_1\n (.I0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_11 ),\n .I1(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_79 ),\n .I2(prbs_state_r[4]),\n .I3(right_edge_found),\n .I4(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_32 ),\n .O(right_edge_found_i_1_n_0));\n LUT5 #(\n .INIT(32'hBABF8A80)) \n rst_dqs_find_i_1\n (.I0(rst_dqs_find),\n .I1(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_111 ),\n .I2(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_45 ),\n .I3(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_109 ),\n .I4(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_9 ),\n .O(rst_dqs_find_i_1_n_0));\n LUT4 #(\n .INIT(16'hABAA)) \n store_sr_r_i_1\n (.I0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_1 ),\n .I1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_6 ),\n .I2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_2 ),\n .I3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_30 ),\n .O(store_sr_r_i_1_n_0));\n FDRE tempmon_pi_f_en_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(tempmon_sel_pi_incdec),\n .Q(tempmon_pi_f_en_r),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE tempmon_pi_f_inc_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(tempmon_pi_f_inc),\n .Q(tempmon_pi_f_inc_r),\n .R(rstdiv0_sync_r1_reg_rep__9));\n ddr3_if_mig_7series_v4_0_ddr_phy_init u_ddr_phy_init\n (.A_rst_primitives_reg(A_rst_primitives_reg),\n .CLK(CLK),\n .D({\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_155 ,\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_156 }),\n .D0(D0[1]),\n .D1(D1[1]),\n .D2(D2[1]),\n .D3(D3[1]),\n .D4(D4),\n .D5(D5),\n .D6(D6),\n .D7(D7),\n .D8(D8),\n .D9(D9),\n .E(u_ddr_phy_init_n_465),\n .Q({init_state_r,u_ddr_phy_init_n_104,u_ddr_phy_init_n_105,u_ddr_phy_init_n_106,u_ddr_phy_init_n_107,u_ddr_phy_init_n_108}),\n .\\back_to_back_reads_4_1.num_reads_reg[0]_0 (u_ddr_phy_init_n_473),\n .\\back_to_back_reads_4_1.num_reads_reg[1]_0 (u_ddr_phy_init_n_474),\n .burst_addr_r_reg_0(u_ddr_phy_init_n_31),\n .burst_addr_r_reg_1(u_ddr_phy_init_n_476),\n .burst_addr_r_reg_2(burst_addr_r_i_1_n_0),\n .cal1_state_r1535_out(cal1_state_r1535_out),\n .calib_complete(calib_complete),\n .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done),\n .\\cmd_pipe_plus.mc_address_reg[42] ({\\cmd_pipe_plus.mc_address_reg[44] [34:14],\\cmd_pipe_plus.mc_address_reg[44] [12:0]}),\n .\\cmd_pipe_plus.mc_bank_reg[8] (\\cmd_pipe_plus.mc_bank_reg[8] ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[0] (\\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[1] (\\cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[2] (\\cmd_pipe_plus.mc_data_offset_1_reg[2]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[3] (\\cmd_pipe_plus.mc_data_offset_1_reg[3]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[4] (\\cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[5] (\\cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_reg[0] (\\cmd_pipe_plus.mc_data_offset_reg[0]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_reg[1] (\\cmd_pipe_plus.mc_data_offset_reg[1]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_reg[2] (\\cmd_pipe_plus.mc_data_offset_reg[2]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_reg[3] (\\cmd_pipe_plus.mc_data_offset_reg[3]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_reg[4] (\\cmd_pipe_plus.mc_data_offset_reg[4]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_reg[5] (\\cmd_pipe_plus.mc_data_offset_reg[5]_0 ),\n .cnt_cmd_done_r(cnt_cmd_done_r),\n .cnt_cmd_done_r_reg_0(ddr2_refresh_flag_r_i_1_n_0),\n .cnt_cmd_done_r_reg_1(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_54 ),\n .cnt_dllk_zqinit_done_r(cnt_dllk_zqinit_done_r),\n .cnt_dllk_zqinit_done_r_reg_0(cnt_dllk_zqinit_done_r_i_1_n_0),\n .cnt_init_af_done_r(cnt_init_af_done_r),\n .cnt_init_af_done_r_reg_0(cnt_init_af_done_r_i_1_n_0),\n .cnt_init_af_done_r_reg_1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_144 ),\n .cnt_init_af_r(cnt_init_af_r),\n .cnt_init_mr_done_r(cnt_init_mr_done_r),\n .cnt_init_mr_done_r_reg_0(cnt_init_mr_done_r_i_1_n_0),\n .cnt_init_mr_r(cnt_init_mr_r),\n .cnt_init_mr_r1(cnt_init_mr_r1),\n .\\cnt_init_mr_r_reg[1]_0 (u_ddr_phy_init_n_110),\n .cnt_pwron_cke_done_r(cnt_pwron_cke_done_r),\n .cnt_pwron_cke_done_r_reg_0(u_ddr_phy_init_n_490),\n .cnt_pwron_cke_done_r_reg_1(cnt_pwron_cke_done_r_i_1_n_0),\n .\\cnt_pwron_r_reg[7]_0 ({cnt_pwron_r_reg__0[7],cnt_pwron_r_reg__0[5],cnt_pwron_r_reg__0[1:0]}),\n .\\cnt_pwron_r_reg[7]_1 (cnt_pwron_reset_done_r_i_1_n_0),\n .cnt_pwron_reset_done_r(cnt_pwron_reset_done_r),\n .cnt_pwron_reset_done_r_reg_0(u_ddr_phy_init_n_485),\n .\\cnt_shift_r_reg[0] (cnt_shift_r0),\n .\\cnt_shift_r_reg[0]_0 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_106 ),\n .cnt_txpr_done_r(cnt_txpr_done_r),\n .cnt_txpr_done_r_reg_0(u_ddr_phy_init_n_500),\n .cnt_txpr_done_r_reg_1(cnt_txpr_done_r_i_1_n_0),\n .\\cnt_txpr_r_reg[2]_0 (cnt_txpr_r_reg__0),\n .complex_act_start(complex_act_start),\n .complex_init_pi_dec_done(complex_init_pi_dec_done),\n .complex_ocal_num_samples_done_r(complex_ocal_num_samples_done_r),\n .complex_ocal_rd_victim_sel(complex_ocal_rd_victim_sel),\n .complex_ocal_ref_req(complex_ocal_ref_req),\n .complex_ocal_reset_rd_addr(complex_ocal_reset_rd_addr),\n .complex_oclk_calib_resume(complex_oclk_calib_resume),\n .complex_oclkdelay_calib_start_int_reg_0(u_ddr_phy_init_n_114),\n .complex_pi_incdec_done(complex_pi_incdec_done),\n .\\complex_row_cnt_ocal_reg[0]_0 (\\complex_row_cnt_ocal_reg[0] ),\n .complex_victim_inc_reg(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_1 ),\n .\\data_offset_1_i1_reg[5] (\\data_offset_1_i1_reg[5] ),\n .ddr2_pre_flag_r_reg_0(u_ddr_phy_init_n_29),\n .ddr2_pre_flag_r_reg_1(u_ddr_phy_init_n_479),\n .ddr2_pre_flag_r_reg_2(ddr2_pre_flag_r_i_1_n_0),\n .ddr2_refresh_flag_r(ddr2_refresh_flag_r),\n .ddr2_refresh_flag_r_reg_0(u_ddr_phy_init_n_480),\n .ddr3_lm_done_r(ddr3_lm_done_r),\n .delay_done_r4_reg(\\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_11 ),\n .detect_pi_found_dqs(detect_pi_found_dqs),\n .done_dqs_tap_inc(done_dqs_tap_inc),\n .done_r_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_13 ),\n .\\dout_o_reg[0] (u_ddr_prbs_gen_n_120),\n .\\dout_o_reg[0]_0 (u_ddr_prbs_gen_n_116),\n .\\dout_o_reg[10] (u_ddr_prbs_gen_n_6),\n .\\dout_o_reg[10]_0 (u_ddr_prbs_gen_n_5),\n .\\dout_o_reg[11] (u_ddr_prbs_gen_n_41),\n .\\dout_o_reg[11]_0 (u_ddr_prbs_gen_n_42),\n .\\dout_o_reg[11]_1 (u_ddr_prbs_gen_n_51),\n .\\dout_o_reg[11]_2 (u_ddr_prbs_gen_n_52),\n .\\dout_o_reg[11]_3 (u_ddr_prbs_gen_n_16),\n .\\dout_o_reg[11]_4 (u_ddr_prbs_gen_n_15),\n .\\dout_o_reg[12] (u_ddr_prbs_gen_n_2),\n .\\dout_o_reg[12]_0 (u_ddr_prbs_gen_n_1),\n .\\dout_o_reg[13] (u_ddr_prbs_gen_n_53),\n .\\dout_o_reg[13]_0 (u_ddr_prbs_gen_n_54),\n .\\dout_o_reg[13]_1 (u_ddr_prbs_gen_n_28),\n .\\dout_o_reg[13]_2 (u_ddr_prbs_gen_n_27),\n .\\dout_o_reg[13]_3 (u_ddr_prbs_gen_n_18),\n .\\dout_o_reg[13]_4 (u_ddr_prbs_gen_n_17),\n .\\dout_o_reg[13]_5 (u_ddr_prbs_gen_n_14),\n .\\dout_o_reg[13]_6 (u_ddr_prbs_gen_n_13),\n .\\dout_o_reg[14] (u_ddr_prbs_gen_n_46),\n .\\dout_o_reg[14]_0 (u_ddr_prbs_gen_n_45),\n .\\dout_o_reg[14]_1 (u_ddr_prbs_gen_n_44),\n .\\dout_o_reg[14]_2 (u_ddr_prbs_gen_n_43),\n .\\dout_o_reg[15] (u_ddr_prbs_gen_n_12),\n .\\dout_o_reg[15]_0 (u_ddr_prbs_gen_n_11),\n .\\dout_o_reg[15]_1 (u_ddr_prbs_gen_n_10),\n .\\dout_o_reg[15]_2 (u_ddr_prbs_gen_n_9),\n .\\dout_o_reg[1] (u_ddr_prbs_gen_n_19),\n .\\dout_o_reg[1]_0 (u_ddr_prbs_gen_n_20),\n .\\dout_o_reg[2] (u_ddr_prbs_gen_n_105),\n .\\dout_o_reg[2]_0 (u_ddr_prbs_gen_n_101),\n .\\dout_o_reg[3] (u_ddr_prbs_gen_n_21),\n .\\dout_o_reg[3]_0 (u_ddr_prbs_gen_n_22),\n .\\dout_o_reg[4] (u_ddr_prbs_gen_n_88),\n .\\dout_o_reg[4]_0 (u_ddr_prbs_gen_n_84),\n .\\dout_o_reg[6] (u_ddr_prbs_gen_n_56),\n .\\dout_o_reg[7] (u_ddr_prbs_gen_n_24),\n .\\dout_o_reg[7]_0 (u_ddr_prbs_gen_n_23),\n .\\dout_o_reg[7]_1 (u_ddr_prbs_gen_n_25),\n .\\dout_o_reg[7]_2 (u_ddr_prbs_gen_n_26),\n .\\dout_o_reg[8] (u_ddr_prbs_gen_n_48),\n .\\dout_o_reg[8]_0 (u_ddr_prbs_gen_n_47),\n .\\dout_o_reg[8]_1 (u_ddr_prbs_gen_n_8),\n .\\dout_o_reg[8]_2 (u_ddr_prbs_gen_n_7),\n .\\dout_o_reg[8]_3 (u_ddr_prbs_gen_n_4),\n .\\dout_o_reg[8]_4 (u_ddr_prbs_gen_n_3),\n .\\dout_o_reg[9] (u_ddr_prbs_gen_n_49),\n .\\dout_o_reg[9]_0 (u_ddr_prbs_gen_n_50),\n .\\dout_o_reg[9]_1 (u_ddr_prbs_gen_n_38),\n .\\dout_o_reg[9]_2 (u_ddr_prbs_gen_n_37),\n .\\dout_o_reg[9]_3 (u_ddr_prbs_gen_n_36),\n .\\dout_o_reg[9]_4 (u_ddr_prbs_gen_n_35),\n .dqs_found_done_r_reg(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_10 ),\n .dqs_found_done_r_reg_0(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_87 ),\n .dqs_found_done_r_reg_1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_149 ),\n .dqs_found_done_r_reg_2(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_89 ),\n .dqs_found_prech_req(dqs_found_prech_req),\n .dqs_found_start_r_reg(u_ddr_phy_init_n_502),\n .\\en_cnt_div4.enable_wrlvl_cnt_reg[3]_0 (\\en_cnt_div4.enable_wrlvl_cnt_reg[3] ),\n .first_rdlvl_pat_r(first_rdlvl_pat_r),\n .first_rdlvl_pat_r_reg_0(u_ddr_prbs_gen_n_55),\n .first_wrcal_pat_r(first_wrcal_pat_r),\n .in0(init_complete_r_timing_orig),\n .init_calib_complete_reg_rep(\\my_empty_reg[7] ),\n .init_calib_complete_reg_rep__0(init_calib_complete_reg_rep__0_n_0),\n .init_calib_complete_reg_rep__1(init_calib_complete_reg_rep__1_n_0),\n .init_calib_complete_reg_rep__10(init_calib_complete_reg_rep__10_n_0),\n .init_calib_complete_reg_rep__11(init_calib_complete_reg_rep__11_n_0),\n .init_calib_complete_reg_rep__12(init_calib_complete_reg_rep__12_n_0),\n .init_calib_complete_reg_rep__13(init_calib_complete_reg_rep__13_n_0),\n .init_calib_complete_reg_rep__14(init_calib_complete_r_reg),\n .init_calib_complete_reg_rep__2(init_calib_complete_reg_rep__2_n_0),\n .init_calib_complete_reg_rep__3(init_calib_complete_reg_rep__3_n_0),\n .init_calib_complete_reg_rep__4(init_calib_complete_reg_rep__4_n_0),\n .init_calib_complete_reg_rep__5(\\rd_ptr_timing_reg[0] ),\n .init_calib_complete_reg_rep__6(app_zq_r_reg),\n .init_calib_complete_reg_rep__7(\\my_empty_reg[7]_0 ),\n .init_calib_complete_reg_rep__8(init_calib_complete_reg_rep__8_n_0),\n .init_calib_complete_reg_rep__9(init_calib_complete_reg_rep__9_n_0),\n .init_complete_r1_reg_0(u_ddr_phy_init_n_18),\n .init_dqsfound_done_r2(init_dqsfound_done_r2),\n .\\init_state_r_reg[0]_0 (u_ddr_phy_init_n_497),\n .\\init_state_r_reg[0]_1 (rdlvl_start_pre_i_1_n_0),\n .\\init_state_r_reg[1]_0 (u_ddr_phy_init_n_111),\n .\\init_state_r_reg[1]_1 (\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_80 ),\n .\\init_state_r_reg[2]_0 (u_ddr_phy_init_n_117),\n .\\init_state_r_reg[2]_1 (u_ddr_phy_init_n_499),\n .\\init_state_r_reg[2]_2 (\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_48 ),\n .\\init_state_r_reg[4]_0 (u_ddr_phy_init_n_475),\n .\\init_state_r_reg[5]_0 (u_ddr_phy_init_n_478),\n .\\init_state_r_reg[6]_0 (init_complete_r_i_1_n_0),\n .\\init_state_r_reg[6]_1 (init_complete_r_timing_i_1_n_0),\n .lim2init_prech_req(lim2init_prech_req),\n .lim_start_r_reg(u_ddr_phy_init_n_462),\n .\\mcGo_r_reg[15] (\\mcGo_r_reg[15] ),\n .mc_cas_n(mc_cas_n[1]),\n .mc_cke(mc_cke),\n .mc_cmd(mc_cmd),\n .mc_odt(mc_odt),\n .mc_ras_n(mc_ras_n[1]),\n .mc_we_n(mc_we_n[1]),\n .mc_wrdata_en(mc_wrdata_en),\n .mem_init_done_r(mem_init_done_r),\n .mem_init_done_r_reg_0(cnt_dllk_zqinit_r_reg__0),\n .mem_init_done_r_reg_1(u_ddr_phy_init_n_496),\n .mem_init_done_r_reg_2(u_ddr_phy_wrcal_n_92),\n .mem_out({mem_out[4],mem_out[1]}),\n .mpr_end_if_reset(mpr_end_if_reset),\n .mpr_last_byte_done(mpr_last_byte_done),\n .mpr_rdlvl_done_r_reg(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ),\n .mpr_rdlvl_done_r_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_142 ),\n .mpr_rdlvl_done_r_reg_1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_146 ),\n .mpr_rdlvl_done_r_reg_2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_147 ),\n .mpr_rdlvl_start_r(mpr_rdlvl_start_r),\n .mpr_rdlvl_start_r_reg(u_ddr_phy_init_n_464),\n .mux_cmd_wren(mux_cmd_wren),\n .mux_reset_n(mux_reset_n),\n .mux_wrdata_en(mux_wrdata_en),\n .\\my_empty_reg[1] (\\my_empty_reg[1] ),\n .\\my_empty_reg[1]_0 (\\my_empty_reg[1]_0 ),\n .\\my_empty_reg[1]_1 (\\my_empty_reg[1]_1 ),\n .\\my_empty_reg[1]_2 (\\my_empty_reg[1]_2 ),\n .\\my_empty_reg[1]_3 (\\my_empty_reg[1]_3 ),\n .\\my_empty_reg[1]_4 (\\my_empty_reg[1]_4 ),\n .\\my_empty_reg[1]_5 (\\my_empty_reg[1]_5 ),\n .\\my_empty_reg[1]_6 (\\my_empty_reg[1]_6 ),\n .\\my_empty_reg[7] (\\my_empty_reg[7]_5 ),\n .\\my_empty_reg[7]_0 (\\my_empty_reg[7]_6 ),\n .\\my_empty_reg[7]_1 (\\my_empty_reg[7]_7 ),\n .\\my_empty_reg[7]_10 (\\my_empty_reg[7]_16 ),\n .\\my_empty_reg[7]_11 (\\my_empty_reg[7]_17 ),\n .\\my_empty_reg[7]_12 (\\my_empty_reg[7]_18 ),\n .\\my_empty_reg[7]_13 (\\my_empty_reg[7]_19 ),\n .\\my_empty_reg[7]_14 (\\my_empty_reg[7]_20 ),\n .\\my_empty_reg[7]_15 (\\my_empty_reg[7]_21 ),\n .\\my_empty_reg[7]_16 (\\my_empty_reg[7]_22 ),\n .\\my_empty_reg[7]_17 (\\my_empty_reg[7]_23 ),\n .\\my_empty_reg[7]_18 (\\my_empty_reg[7]_24 ),\n .\\my_empty_reg[7]_19 (\\my_empty_reg[7]_25 ),\n .\\my_empty_reg[7]_2 (\\my_empty_reg[7]_8 ),\n .\\my_empty_reg[7]_20 (\\my_empty_reg[7]_26 ),\n .\\my_empty_reg[7]_21 (\\my_empty_reg[7]_27 ),\n .\\my_empty_reg[7]_22 (\\my_empty_reg[7]_28 ),\n .\\my_empty_reg[7]_23 (\\my_empty_reg[7]_29 ),\n .\\my_empty_reg[7]_24 (\\my_empty_reg[7]_30 ),\n .\\my_empty_reg[7]_25 (\\my_empty_reg[7]_31 ),\n .\\my_empty_reg[7]_26 (\\my_empty_reg[7]_32 ),\n .\\my_empty_reg[7]_27 (\\my_empty_reg[7]_33 ),\n .\\my_empty_reg[7]_28 (\\my_empty_reg[7]_34 ),\n .\\my_empty_reg[7]_29 (\\my_empty_reg[7]_35 ),\n .\\my_empty_reg[7]_3 (\\my_empty_reg[7]_9 ),\n .\\my_empty_reg[7]_30 (\\my_empty_reg[7]_36 ),\n .\\my_empty_reg[7]_31 (\\my_empty_reg[7]_37 ),\n .\\my_empty_reg[7]_32 (\\my_empty_reg[7]_38 ),\n .\\my_empty_reg[7]_33 (\\my_empty_reg[7]_39 ),\n .\\my_empty_reg[7]_34 (\\my_empty_reg[7]_40 ),\n .\\my_empty_reg[7]_35 (\\my_empty_reg[7]_41 ),\n .\\my_empty_reg[7]_36 (\\my_empty_reg[7]_42 ),\n .\\my_empty_reg[7]_37 (\\my_empty_reg[7]_43 ),\n .\\my_empty_reg[7]_38 (\\my_empty_reg[7]_1 [63:0]),\n .\\my_empty_reg[7]_39 (\\my_empty_reg[7]_2 [63:0]),\n .\\my_empty_reg[7]_4 (\\my_empty_reg[7]_10 ),\n .\\my_empty_reg[7]_40 (\\my_empty_reg[7]_3 [63:0]),\n .\\my_empty_reg[7]_41 (\\my_empty_reg[7]_4 [63:0]),\n .\\my_empty_reg[7]_5 (\\my_empty_reg[7]_11 ),\n .\\my_empty_reg[7]_6 (\\my_empty_reg[7]_12 ),\n .\\my_empty_reg[7]_7 (\\my_empty_reg[7]_13 ),\n .\\my_empty_reg[7]_8 (\\my_empty_reg[7]_14 ),\n .\\my_empty_reg[7]_9 (\\my_empty_reg[7]_15 ),\n .\\my_full_reg[3] (\\my_full_reg[3]_0 ),\n .new_cnt_dqs_r_reg(u_ddr_phy_init_n_127),\n .num_samples_done_r(num_samples_done_r),\n .ocal_last_byte_done(ocal_last_byte_done),\n .ocd_prech_req(ocd_prech_req),\n .oclk_calib_resume_level_reg_0(u_ddr_phy_init_n_102),\n .oclk_calib_resume_r_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_47 ),\n .oclk_calib_resume_r_reg_0(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_51 ),\n .oclkdelay_calib_done_r_reg(u_ddr_prbs_gen_n_40),\n .oclkdelay_calib_done_r_reg_0(u_ddr_prbs_gen_n_39),\n .oclkdelay_calib_done_r_reg_1(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_28 ),\n .oclkdelay_calib_done_r_reg_2(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ),\n .oclkdelay_calib_done_r_reg_3(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_50 ),\n .oclkdelay_calib_done_r_reg_4(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_85 ),\n .oclkdelay_calib_done_r_reg_5(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_81 ),\n .oclkdelay_center_calib_done_r_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_55 ),\n .oclkdelay_center_calib_done_r_reg_0(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_4 ),\n .oclkdelay_center_calib_start_r_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_15 ),\n .oclkdelay_center_calib_start_r_reg_0(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_49 ),\n .oclkdelay_int_ref_req_reg_0(u_ddr_phy_init_n_477),\n .\\oclkdelay_ref_cnt_reg[13]_0 (u_ddr_phy_init_n_24),\n .\\odd_cwl.phy_cas_n_reg[1]_0 (u_ddr_phy_init_n_109),\n .\\one_rank.stg1_wr_done_reg_0 (u_ddr_phy_init_n_116),\n .out(out),\n .p_81_in(p_81_in),\n .\\phy_ctl_wd_i1_reg[24] (\\phy_ctl_wd_i1_reg[24] ),\n .phy_dout(phy_dout[31:0]),\n .phy_if_empty_r_reg(u_ddr_prbs_gen_n_0),\n .phy_rddata_en_1(phy_rddata_en_1),\n .phy_read_calib(phy_read_calib),\n .phy_write_calib(phy_write_calib),\n .pi_calib_done(pi_calib_done),\n .\\pi_dqs_found_all_bank_reg[1] (u_ddr_phy_init_n_501),\n .\\pi_dqs_found_all_bank_reg[1]_0 (pi_dqs_found_all_bank),\n .pi_dqs_found_done_r1(pi_dqs_found_done_r1),\n .pi_dqs_found_done_r1_reg_0(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_90 ),\n .pi_dqs_found_done_r1_reg_1(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_91 ),\n .pi_dqs_found_done_r1_reg_2(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_92 ),\n .pi_dqs_found_done_r1_reg_3(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_93 ),\n .pi_dqs_found_done_r1_reg_4(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_94 ),\n .pi_dqs_found_done_r1_reg_5(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_95 ),\n .pi_dqs_found_done_r1_reg_6(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_96 ),\n .pi_dqs_found_done_r1_reg_7(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_97 ),\n .pi_dqs_found_rank_done(pi_dqs_found_rank_done),\n .prbs_last_byte_done(prbs_last_byte_done),\n .prbs_last_byte_done_r(prbs_last_byte_done_r),\n .prbs_last_byte_done_reg(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_90 ),\n .prbs_rdlvl_done_pulse0(prbs_rdlvl_done_pulse0),\n .prbs_rdlvl_done_r1(prbs_rdlvl_done_r1),\n .prbs_rdlvl_done_reg(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_45 ),\n .prbs_rdlvl_done_reg_0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_85 ),\n .prbs_rdlvl_done_reg_rep(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_51 ),\n .prbs_rdlvl_done_reg_rep_0(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_52 ),\n .prbs_rdlvl_done_reg_rep_1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_145 ),\n .prbs_rdlvl_done_reg_rep_2(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_87 ),\n .prbs_rdlvl_done_reg_rep_3(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_88 ),\n .prbs_rdlvl_prech_req_reg(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_2 ),\n .prbs_rdlvl_start_r(prbs_rdlvl_start_r),\n .prbs_rdlvl_start_r_reg(prbs_rdlvl_start_r_reg),\n .prech_done(prech_done),\n .prech_pending_r(prech_pending_r),\n .prech_pending_r_reg_0(u_ddr_phy_init_n_9),\n .prech_pending_r_reg_1(u_ddr_phy_init_n_468),\n .prech_req(prech_req),\n .prech_req_posedge_r_reg_0(prech_pending_r_i_1_n_0),\n .\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3] (rd_data_offset_ranks_0),\n .\\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] (rd_data_offset_ranks_1),\n .\\rd_addr_reg[0] (u_ddr_phy_init_n_786),\n .\\rd_addr_reg[3] (u_ddr_prbs_gen_n_57),\n .\\rd_addr_reg_rep[7] (u_ddr_phy_init_n_785),\n .\\rd_byte_data_offset_reg[0][3] ({\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_73 ,\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_74 }),\n .\\rd_byte_data_offset_reg[0][9] (p_0_in_0),\n .\\rd_ptr_reg[3] ({\\rd_ptr_reg[3] [37:6],\\rd_ptr_reg[3] [4],\\rd_ptr_reg[3] [1]}),\n .\\rd_ptr_reg[3]_0 (\\rd_ptr_reg[3]_0 [11:4]),\n .\\rd_ptr_reg[3]_1 (\\rd_ptr_reg[3]_1 ),\n .\\rd_ptr_reg[3]_2 (\\rd_ptr_reg[3]_2 ),\n .\\rd_ptr_reg[3]_3 (\\rd_ptr_reg[3]_3 ),\n .\\rd_ptr_reg[3]_4 (\\rd_ptr_reg[3]_4 ),\n .\\rd_ptr_reg[3]_5 (\\rd_ptr_reg[3]_5 ),\n .\\rd_ptr_timing_reg[0] (\\rd_ptr_timing_reg[0]_0 ),\n .\\rd_ptr_timing_reg[0]_0 (\\rd_ptr_timing_reg[0]_1 ),\n .\\rd_ptr_timing_reg[0]_1 (\\rd_ptr_timing_reg[0]_2 ),\n .\\rd_ptr_timing_reg[0]_2 (\\rd_ptr_timing_reg[0]_3 ),\n .\\rd_ptr_timing_reg[0]_3 (\\rd_ptr_timing_reg[0]_4 ),\n .\\rd_victim_sel_reg[0] (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_116 ),\n .\\rd_victim_sel_reg[1] (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_115 ),\n .\\rd_victim_sel_reg[2] (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_117 ),\n .rdlvl_last_byte_done(rdlvl_last_byte_done),\n .rdlvl_pi_incdec(rdlvl_pi_incdec),\n .rdlvl_prech_req(rdlvl_prech_req),\n .rdlvl_start_dly0_r(rdlvl_start_dly0_r),\n .\\rdlvl_start_dly0_r_reg[14]_0 (rdlvl_stg1_start_i_1_n_0),\n .rdlvl_start_pre(rdlvl_start_pre),\n .rdlvl_start_pre_reg_0(u_ddr_phy_init_n_469),\n .rdlvl_stg1_done_int_reg(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_56 ),\n .rdlvl_stg1_done_int_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_153 ),\n .rdlvl_stg1_done_int_reg_1(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_79 ),\n .rdlvl_stg1_done_int_reg_2(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_154 ),\n .rdlvl_stg1_done_int_reg_3(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_151 ),\n .rdlvl_stg1_done_int_reg_4(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_82 ),\n .rdlvl_stg1_rank_done(rdlvl_stg1_rank_done),\n .rdlvl_stg1_start_int(rdlvl_stg1_start_int),\n .rdlvl_stg1_start_r_reg(u_ddr_phy_init_n_33),\n .read_calib_reg_0(u_ddr_phy_init_n_470),\n .\\reg_ctrl_cnt_r_reg[3]_0 (u_ddr_phy_init_n_115),\n .reset_if(reset_if),\n .reset_if_r9(reset_if_r9),\n .reset_if_reg(u_ddr_phy_init_n_101),\n .reset_rd_addr(reset_rd_addr),\n .reset_rd_addr0(reset_rd_addr0),\n .\\row_cnt_victim_rotate.complex_row_cnt_reg[4]_0 (\\row_cnt_victim_rotate.complex_row_cnt_reg[4] ),\n .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10),\n .rstdiv0_sync_r1_reg_rep__11(rstdiv0_sync_r1_reg_rep__11),\n .rstdiv0_sync_r1_reg_rep__12(rstdiv0_sync_r1_reg_rep__12),\n .rstdiv0_sync_r1_reg_rep__18(rstdiv0_sync_r1_reg_rep__18),\n .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23),\n .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),\n .rstdiv0_sync_r1_reg_rep__24_0(rstdiv0_sync_r1_reg_rep__24_0),\n .rstdiv0_sync_r1_reg_rep__24_1(rstdiv0_sync_r1_reg_rep__24_1),\n .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25),\n .\\samples_cnt_r_reg[11] (samples_cnt_r),\n .\\samples_cnt_r_reg[11]_0 (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_84 ),\n .stg1_wr_done(stg1_wr_done),\n .temp_lmr_done(temp_lmr_done),\n .\\victim_sel_rotate.sel_reg[31] ({sel,u_ddr_phy_init_n_120,u_ddr_phy_init_n_121,u_ddr_phy_init_n_122,u_ddr_phy_init_n_123,u_ddr_phy_init_n_124,u_ddr_phy_init_n_125,u_ddr_phy_init_n_126}),\n .wl_sm_start(wl_sm_start),\n .wr_level_done_reg(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_12 ),\n .wr_level_start_r_reg(u_ddr_phy_init_n_790),\n .wrcal_done_reg(u_ddr_phy_wrcal_n_103),\n .wrcal_done_reg_0(u_ddr_phy_wrcal_n_83),\n .wrcal_done_reg_1(u_ddr_phy_wrcal_n_84),\n .wrcal_done_reg_10(u_ddr_phy_wrcal_n_82),\n .wrcal_done_reg_11(u_ddr_phy_wrcal_n_81),\n .wrcal_done_reg_2(u_ddr_phy_wrcal_n_104),\n .wrcal_done_reg_3(u_ddr_prbs_gen_n_34),\n .wrcal_done_reg_4(u_ddr_prbs_gen_n_33),\n .wrcal_done_reg_5(u_ddr_prbs_gen_n_32),\n .wrcal_done_reg_6(u_ddr_prbs_gen_n_31),\n .wrcal_done_reg_7(u_ddr_prbs_gen_n_30),\n .wrcal_done_reg_8(u_ddr_prbs_gen_n_29),\n .wrcal_done_reg_9(u_ddr_phy_wrcal_n_93),\n .\\wrcal_dqs_cnt_r_reg[0] (u_ddr_phy_init_n_784),\n .wrcal_prech_req(wrcal_prech_req),\n .wrcal_rd_wait(wrcal_rd_wait),\n .wrcal_resume_r(wrcal_resume_r),\n .wrcal_resume_w(wrcal_resume_w),\n .wrcal_sanity_chk(wrcal_sanity_chk),\n .wrcal_sanity_chk_done_reg(u_ddr_phy_wrcal_n_96),\n .wrcal_sanity_chk_done_reg_0(u_ddr_phy_wrcal_n_71),\n .wrcal_sanity_chk_r_reg(u_ddr_phy_wrcal_n_5),\n .wrcal_start_reg_0(u_ddr_phy_init_n_791),\n .\\write_buffer.wr_buf_out_data_reg[255] (Q[255:0]),\n .write_request_r_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_53 ),\n .wrlvl_byte_redo(wrlvl_byte_redo),\n .wrlvl_byte_redo_reg(u_ddr_phy_wrcal_n_95),\n .wrlvl_byte_redo_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_148 ),\n .wrlvl_done_r1(wrlvl_done_r1),\n .wrlvl_final_if_rst(wrlvl_final_if_rst),\n .wrlvl_final_mux(wrlvl_final_mux),\n .wrlvl_final_mux_reg(u_ddr_phy_wrcal_n_90),\n .wrlvl_final_mux_reg_0(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_88 ),\n .wrlvl_rank_done(wrlvl_rank_done));\n ddr3_if_mig_7series_v4_0_ddr_phy_wrcal u_ddr_phy_wrcal\n (.CLK(CLK),\n .\\FSM_sequential_wl_state_r_reg[0] (u_ddr_phy_wrcal_n_102),\n .LD0(LD0),\n .LD0_0(LD0_0),\n .LD0_1(LD0_1),\n .LD0_2(LD0_2),\n .Q(calib_zero_inputs__0),\n .cal2_done_r(cal2_done_r),\n .cal2_done_r_reg_0(u_ddr_phy_wrcal_n_117),\n .cal2_if_reset_reg_0(u_ddr_phy_wrcal_n_114),\n .cal2_if_reset_reg_1(u_ddr_phy_wrcal_n_115),\n .cal2_if_reset_reg_2(u_ddr_phy_wrcal_n_120),\n .\\cal2_state_r_reg[0]_0 (idelay_ld_done_i_1_n_0),\n .\\cal2_state_r_reg[0]_1 (cal2_if_reset_i_1_n_0),\n .\\cal2_state_r_reg[2]_0 (wrcal_pat_resume_r_i_1_n_0),\n .\\cal2_state_r_reg[3]_0 (wrcal_sanity_chk_done_i_1_n_0),\n .calib_in_common(calib_in_common),\n .\\calib_sel_reg[1] (\\po_rdval_cnt_reg[8] [1:0]),\n .\\corse_cnt_reg[0][2] (u_ddr_phy_wrcal_n_100),\n .\\corse_cnt_reg[1][2] (u_ddr_phy_wrcal_n_97),\n .\\corse_cnt_reg[2][2] (u_ddr_phy_wrcal_n_98),\n .ddr3_lm_done_r(ddr3_lm_done_r),\n .done_dqs_dec239_out(done_dqs_dec239_out),\n .dqs_found_done_r_reg(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_10 ),\n .dqs_found_done_r_reg_0(\\dqsfind_calib_right.u_ddr_phy_dqs_found_cal_n_86 ),\n .early1_data_reg_0(u_ddr_phy_wrcal_n_67),\n .early1_data_reg_1(u_ddr_phy_wrcal_n_73),\n .early1_data_reg_2(u_ddr_phy_wrcal_n_119),\n .early2_data_reg_0(u_ddr_phy_wrcal_n_66),\n .early2_data_reg_1(u_ddr_phy_wrcal_n_74),\n .\\final_coarse_tap_reg[3][2] (final_coarse_tap),\n .first_wrcal_pat_r(first_wrcal_pat_r),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[0] (u_ddr_phy_wrcal_n_105),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[1] (u_ddr_phy_wrcal_n_106),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[2] (u_ddr_phy_wrcal_n_107),\n .\\gen_pat_match_div4.early1_data_match_r_reg_0 (early1_data_i_1_n_0),\n .\\gen_pat_match_div4.early1_data_match_r_reg_1 (early2_data_i_1_n_0),\n .\\gen_pat_match_div4.early2_data_match_r_reg_0 (wrlvl_byte_redo_i_1_n_0),\n .\\gen_pat_match_div4.pat_data_match_valid_r_reg_0 (idelay_ld_i_1_n_0),\n .\\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0][0]_0 (\\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 (\\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 ),\n .\\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0][0]_0 (\\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 (\\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 ),\n .\\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0][0]_0 (\\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 (\\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 ),\n .\\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0][0]_0 (\\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 (\\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 ),\n .\\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0][0]_0 (\\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 (\\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 ),\n .\\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0][0]_0 (\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 (\\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 ),\n .\\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0][0]_0 (\\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 (\\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 ),\n .\\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1][0]_0 (\\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 (\\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 ),\n .\\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1][0]_0 (\\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 (\\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 ),\n .\\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1][0]_0 (\\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 (\\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 ),\n .\\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1][0]_0 (\\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 (\\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 ),\n .\\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1][0]_0 (\\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 (\\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 ),\n .\\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1][0]_0 (\\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 (\\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 ),\n .\\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1][0]_0 (\\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 (\\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 ),\n .\\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1][0]_0 (\\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 (\\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 ),\n .\\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2][0]_0 (\\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 (\\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 ),\n .\\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2][0]_0 (\\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 (\\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 ),\n .\\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2][0]_0 (\\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 (\\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 ),\n .\\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2][0]_0 (\\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 (\\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 ),\n .\\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2][0]_0 (\\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 (\\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 ),\n .\\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2][0]_0 (\\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 (\\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 ),\n .\\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2][0]_0 (\\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 (\\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 ),\n .\\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2][0]_0 (\\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 (\\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 ),\n .\\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3][0]_0 (\\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 (\\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 ),\n .\\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3][0]_0 (\\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 (\\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 ),\n .\\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3][0]_0 (\\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 (\\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 ),\n .\\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3][0]_0 (\\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_208 (\\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_208 ),\n .\\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3][0]_0 (\\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 (\\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 ),\n .\\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3][0]_0 (\\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 (\\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 ),\n .\\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3][0]_0 (\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 (\\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 ),\n .\\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4][0]_0 (\\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 (\\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 ),\n .\\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4][0]_0 (\\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 (\\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 ),\n .\\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4][0]_0 (\\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 (\\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 ),\n .\\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4][0]_0 (\\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 (\\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 ),\n .\\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4][0]_0 (\\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 (\\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 ),\n .\\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4][0]_0 (\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 (\\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 ),\n .\\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4][0]_0 (\\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 (\\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 ),\n .\\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5][0]_0 (\\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 (\\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 ),\n .\\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5][0]_0 (\\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 (\\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 ),\n .\\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5][0]_0 (\\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 (\\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 ),\n .\\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5][0]_0 (\\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 (\\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 ),\n .\\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5][0]_0 (\\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 (\\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 ),\n .\\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5][0]_0 (\\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 (\\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 ),\n .\\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5][0]_0 (\\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 (\\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 ),\n .\\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5][0]_0 (\\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 (\\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 ),\n .\\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6][0]_0 (\\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 (\\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 ),\n .\\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6][0]_0 (\\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 (\\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 ),\n .\\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6][0]_0 (\\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 (\\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 ),\n .\\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6][0]_0 (\\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 (\\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 ),\n .\\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6][0]_0 (\\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 (\\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 ),\n .\\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6][0]_0 (\\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 (\\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 ),\n .\\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6][0]_0 (\\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 (\\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 ),\n .\\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6][0]_0 (\\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 (\\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 ),\n .\\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7][0]_0 (\\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 (\\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 ),\n .\\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7][0]_0 (\\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 (\\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 ),\n .\\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7][0]_0 (\\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 (\\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 ),\n .\\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7][0]_0 (\\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_212 (\\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_212 ),\n .\\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7][0]_0 (\\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 (\\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 ),\n .\\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7][0]_0 (\\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 (\\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 ),\n .\\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7][0]_0 (\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1_n_0 ),\n .\\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 (\\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 ),\n .idelay_ce_int(idelay_ce_int),\n .idelay_ld(idelay_ld),\n .idelay_ld_done_reg_0(u_ddr_phy_wrcal_n_113),\n .idelay_ld_reg_0(u_ddr_phy_wrcal_n_4),\n .idelay_ld_reg_1(u_ddr_phy_wrcal_n_116),\n .idelay_ld_rst(idelay_ld_rst),\n .idelay_ld_rst_3(idelay_ld_rst_3),\n .idelay_ld_rst_4(idelay_ld_rst_4),\n .idelay_ld_rst_5(idelay_ld_rst_5),\n .\\idelay_tap_cnt_r_reg[0][1][0] (u_ddr_phy_wrcal_n_89),\n .\\idelay_tap_cnt_r_reg[0][2][0] (u_ddr_phy_wrcal_n_85),\n .\\idelay_tap_cnt_r_reg[0][2][0]_0 ({po_stg2_wrcal_cnt,\\idelay_tap_cnt_r_reg[0][3][0] }),\n .\\init_state_r_reg[0] (u_ddr_phy_wrcal_n_90),\n .\\init_state_r_reg[0]_0 (u_ddr_phy_wrcal_n_93),\n .\\init_state_r_reg[0]_1 (u_ddr_phy_wrcal_n_94),\n .\\init_state_r_reg[0]_2 (u_ddr_phy_wrcal_n_96),\n .\\init_state_r_reg[2] (u_ddr_phy_wrcal_n_91),\n .\\init_state_r_reg[3] (u_ddr_phy_wrcal_n_81),\n .\\init_state_r_reg[4] (u_ddr_phy_wrcal_n_92),\n .\\init_state_r_reg[5] (u_ddr_phy_wrcal_n_95),\n .mem_init_done_r(mem_init_done_r),\n .mpr_last_byte_done(mpr_last_byte_done),\n .mpr_rdlvl_done_r_reg(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_0 ),\n .\\not_empty_wait_cnt_reg[0]_0 ({u_ddr_phy_wrcal_n_108,u_ddr_phy_wrcal_n_109,u_ddr_phy_wrcal_n_110,u_ddr_phy_wrcal_n_111}),\n .oclkdelay_calib_done_r_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ),\n .oclkdelay_calib_done_r_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_150 ),\n .oclkdelay_center_calib_done_r_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_4 ),\n .p_0_out(p_0_out),\n .phy_if_reset_w(phy_if_reset_w),\n .phy_rddata_en_1(phy_rddata_en_1),\n .phy_rddata_en_r1_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_58 ),\n .\\po_stg2_wrcal_cnt_reg[1]_0 (\\po_stg2_wrcal_cnt_reg[1] ),\n .\\po_stg2_wrcal_cnt_reg[1]_1 (\\po_stg2_wrcal_cnt_reg[1]_0 ),\n .\\po_stg2_wrcal_cnt_reg[1]_10 (\\po_stg2_wrcal_cnt_reg[1]_9 ),\n .\\po_stg2_wrcal_cnt_reg[1]_11 (\\po_stg2_wrcal_cnt_reg[1]_10 ),\n .\\po_stg2_wrcal_cnt_reg[1]_12 (\\po_stg2_wrcal_cnt_reg[1]_11 ),\n .\\po_stg2_wrcal_cnt_reg[1]_13 (\\po_stg2_wrcal_cnt_reg[1]_12 ),\n .\\po_stg2_wrcal_cnt_reg[1]_14 (\\po_stg2_wrcal_cnt_reg[1]_13 ),\n .\\po_stg2_wrcal_cnt_reg[1]_15 (\\po_stg2_wrcal_cnt_reg[1]_14 ),\n .\\po_stg2_wrcal_cnt_reg[1]_16 (\\po_stg2_wrcal_cnt_reg[1]_15 ),\n .\\po_stg2_wrcal_cnt_reg[1]_17 (\\po_stg2_wrcal_cnt_reg[1]_16 ),\n .\\po_stg2_wrcal_cnt_reg[1]_18 (\\po_stg2_wrcal_cnt_reg[1]_17 ),\n .\\po_stg2_wrcal_cnt_reg[1]_19 (\\po_stg2_wrcal_cnt_reg[1]_18 ),\n .\\po_stg2_wrcal_cnt_reg[1]_2 (\\po_stg2_wrcal_cnt_reg[1]_1 ),\n .\\po_stg2_wrcal_cnt_reg[1]_20 (\\po_stg2_wrcal_cnt_reg[1]_19 ),\n .\\po_stg2_wrcal_cnt_reg[1]_21 (\\po_stg2_wrcal_cnt_reg[1]_20 ),\n .\\po_stg2_wrcal_cnt_reg[1]_22 (\\po_stg2_wrcal_cnt_reg[1]_21 ),\n .\\po_stg2_wrcal_cnt_reg[1]_23 (\\po_stg2_wrcal_cnt_reg[1]_22 ),\n .\\po_stg2_wrcal_cnt_reg[1]_24 (\\po_stg2_wrcal_cnt_reg[1]_23 ),\n .\\po_stg2_wrcal_cnt_reg[1]_25 (\\po_stg2_wrcal_cnt_reg[1]_24 ),\n .\\po_stg2_wrcal_cnt_reg[1]_26 (\\po_stg2_wrcal_cnt_reg[1]_25 ),\n .\\po_stg2_wrcal_cnt_reg[1]_27 (\\po_stg2_wrcal_cnt_reg[1]_26 ),\n .\\po_stg2_wrcal_cnt_reg[1]_28 (\\po_stg2_wrcal_cnt_reg[1]_27 ),\n .\\po_stg2_wrcal_cnt_reg[1]_29 (\\po_stg2_wrcal_cnt_reg[1]_28 ),\n .\\po_stg2_wrcal_cnt_reg[1]_3 (\\po_stg2_wrcal_cnt_reg[1]_2 ),\n .\\po_stg2_wrcal_cnt_reg[1]_30 (\\po_stg2_wrcal_cnt_reg[1]_29 ),\n .\\po_stg2_wrcal_cnt_reg[1]_31 (\\po_stg2_wrcal_cnt_reg[1]_30 ),\n .\\po_stg2_wrcal_cnt_reg[1]_32 (\\po_stg2_wrcal_cnt_reg[1]_31 ),\n .\\po_stg2_wrcal_cnt_reg[1]_33 (\\po_stg2_wrcal_cnt_reg[1]_32 ),\n .\\po_stg2_wrcal_cnt_reg[1]_34 (\\po_stg2_wrcal_cnt_reg[1]_33 ),\n .\\po_stg2_wrcal_cnt_reg[1]_35 (\\po_stg2_wrcal_cnt_reg[1]_34 ),\n .\\po_stg2_wrcal_cnt_reg[1]_36 (\\po_stg2_wrcal_cnt_reg[1]_35 ),\n .\\po_stg2_wrcal_cnt_reg[1]_37 (\\po_stg2_wrcal_cnt_reg[1]_36 ),\n .\\po_stg2_wrcal_cnt_reg[1]_38 (\\po_stg2_wrcal_cnt_reg[1]_37 ),\n .\\po_stg2_wrcal_cnt_reg[1]_39 (\\po_stg2_wrcal_cnt_reg[1]_38 ),\n .\\po_stg2_wrcal_cnt_reg[1]_4 (\\po_stg2_wrcal_cnt_reg[1]_3 ),\n .\\po_stg2_wrcal_cnt_reg[1]_40 (\\po_stg2_wrcal_cnt_reg[1]_39 ),\n .\\po_stg2_wrcal_cnt_reg[1]_41 (\\po_stg2_wrcal_cnt_reg[1]_40 ),\n .\\po_stg2_wrcal_cnt_reg[1]_42 (\\po_stg2_wrcal_cnt_reg[1]_41 ),\n .\\po_stg2_wrcal_cnt_reg[1]_43 (\\po_stg2_wrcal_cnt_reg[1]_42 ),\n .\\po_stg2_wrcal_cnt_reg[1]_44 (\\po_stg2_wrcal_cnt_reg[1]_43 ),\n .\\po_stg2_wrcal_cnt_reg[1]_45 (\\po_stg2_wrcal_cnt_reg[1]_44 ),\n .\\po_stg2_wrcal_cnt_reg[1]_46 (\\po_stg2_wrcal_cnt_reg[1]_45 ),\n .\\po_stg2_wrcal_cnt_reg[1]_47 (\\po_stg2_wrcal_cnt_reg[1]_46 ),\n .\\po_stg2_wrcal_cnt_reg[1]_48 (\\po_stg2_wrcal_cnt_reg[1]_47 ),\n .\\po_stg2_wrcal_cnt_reg[1]_49 (\\po_stg2_wrcal_cnt_reg[1]_48 ),\n .\\po_stg2_wrcal_cnt_reg[1]_5 (\\po_stg2_wrcal_cnt_reg[1]_4 ),\n .\\po_stg2_wrcal_cnt_reg[1]_50 (\\po_stg2_wrcal_cnt_reg[1]_49 ),\n .\\po_stg2_wrcal_cnt_reg[1]_51 (\\po_stg2_wrcal_cnt_reg[1]_50 ),\n .\\po_stg2_wrcal_cnt_reg[1]_52 (\\po_stg2_wrcal_cnt_reg[1]_51 ),\n .\\po_stg2_wrcal_cnt_reg[1]_53 (\\po_stg2_wrcal_cnt_reg[1]_52 ),\n .\\po_stg2_wrcal_cnt_reg[1]_54 (\\po_stg2_wrcal_cnt_reg[1]_53 ),\n .\\po_stg2_wrcal_cnt_reg[1]_55 (\\po_stg2_wrcal_cnt_reg[1]_54 ),\n .\\po_stg2_wrcal_cnt_reg[1]_56 (\\po_stg2_wrcal_cnt_reg[1]_55 ),\n .\\po_stg2_wrcal_cnt_reg[1]_57 (\\po_stg2_wrcal_cnt_reg[1]_56 ),\n .\\po_stg2_wrcal_cnt_reg[1]_58 (\\po_stg2_wrcal_cnt_reg[1]_57 ),\n .\\po_stg2_wrcal_cnt_reg[1]_59 (\\po_stg2_wrcal_cnt_reg[1]_58 ),\n .\\po_stg2_wrcal_cnt_reg[1]_6 (\\po_stg2_wrcal_cnt_reg[1]_5 ),\n .\\po_stg2_wrcal_cnt_reg[1]_60 (\\po_stg2_wrcal_cnt_reg[1]_59 ),\n .\\po_stg2_wrcal_cnt_reg[1]_61 (\\po_stg2_wrcal_cnt_reg[1]_60 ),\n .\\po_stg2_wrcal_cnt_reg[1]_62 (\\po_stg2_wrcal_cnt_reg[1]_61 ),\n .\\po_stg2_wrcal_cnt_reg[1]_7 (\\po_stg2_wrcal_cnt_reg[1]_6 ),\n .\\po_stg2_wrcal_cnt_reg[1]_8 (\\po_stg2_wrcal_cnt_reg[1]_7 ),\n .\\po_stg2_wrcal_cnt_reg[1]_9 (\\po_stg2_wrcal_cnt_reg[1]_8 ),\n .\\prbs_dqs_cnt_r_reg[0] (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_9 ),\n .\\prbs_dqs_cnt_r_reg[1] (\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_10 ),\n .prbs_rdlvl_done_reg(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_45 ),\n .prbs_rdlvl_done_reg_rep(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_51 ),\n .prbs_rdlvl_done_reg_rep_0(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_89 ),\n .prech_done(prech_done),\n .prech_req_posedge_r_reg(u_ddr_phy_init_n_9),\n .rd_active_r1(rd_active_r1),\n .rd_active_r2(rd_active_r2),\n .rdlvl_stg1_done_int_reg(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_56 ),\n .rdlvl_stg1_done_int_reg_0(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_152 ),\n .rdlvl_stg1_start_int_reg(u_ddr_phy_init_n_475),\n .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2),\n .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23),\n .rstdiv0_sync_r1_reg_rep__4(rstdiv0_sync_r1_reg_rep__4),\n .rstdiv0_sync_r1_reg_rep__5(rstdiv0_sync_r1_reg_rep__5),\n .rstdiv0_sync_r1_reg_rep__6(rstdiv0_sync_r1_reg_rep__6),\n .wl_sm_start(wl_sm_start),\n .wrcal_done_reg_0(u_ddr_phy_wrcal_n_5),\n .wrcal_done_reg_1(u_ddr_phy_wrcal_n_82),\n .wrcal_pat_resume_r(wrcal_pat_resume_r),\n .wrcal_pat_resume_r_reg_0(u_ddr_phy_wrcal_n_69),\n .wrcal_pat_resume_r_reg_1(u_ddr_phy_wrcal_n_112),\n .wrcal_prech_req(wrcal_prech_req),\n .wrcal_rd_wait(wrcal_rd_wait),\n .wrcal_resume_r(wrcal_resume_r),\n .wrcal_resume_w(wrcal_resume_w),\n .wrcal_sanity_chk(wrcal_sanity_chk),\n .wrcal_sanity_chk_done_reg_0(u_ddr_phy_wrcal_n_71),\n .wrcal_sanity_chk_r_reg_0(cal2_done_r_i_1_n_0),\n .wrcal_sanity_chk_reg(u_ddr_phy_init_n_784),\n .wrcal_start_reg(u_ddr_phy_init_n_791),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] (u_ddr_phy_wrcal_n_84),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] (u_ddr_phy_wrcal_n_104),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] (u_ddr_phy_wrcal_n_103),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] (u_ddr_phy_wrcal_n_83),\n .wrlvl_byte_done(wrlvl_byte_done),\n .wrlvl_byte_redo(wrlvl_byte_redo),\n .wrlvl_byte_redo_r(wrlvl_byte_redo_r),\n .wrlvl_byte_redo_reg_0(u_ddr_phy_wrcal_n_118),\n .wrlvl_done_r1(wrlvl_done_r1),\n .wrlvl_final_mux(wrlvl_final_mux),\n .\\wrlvl_redo_corse_inc_reg[2] (u_ddr_phy_wrcal_n_101));\n ddr3_if_mig_7series_v4_0_ddr_prbs_gen u_ddr_prbs_gen\n (.CLK(CLK),\n .D({sel,u_ddr_phy_init_n_120,u_ddr_phy_init_n_121,u_ddr_phy_init_n_122,u_ddr_phy_init_n_123,u_ddr_phy_init_n_124,u_ddr_phy_init_n_125,u_ddr_phy_init_n_126}),\n .E(u_ddr_phy_init_n_786),\n .Q(u_ddr_prbs_gen_n_57),\n .SR(\\rd_addr[7]_i_1_n_0 ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ),\n .first_rdlvl_pat_r(first_rdlvl_pat_r),\n .\\gen_mux_rd[0].compare_data_fall0_r1_reg[0] (u_ddr_prbs_gen_n_66),\n .\\gen_mux_rd[0].compare_data_fall1_r1_reg[0] (u_ddr_prbs_gen_n_82),\n .\\gen_mux_rd[0].compare_data_fall2_r1_reg[0] (u_ddr_prbs_gen_n_98),\n .\\gen_mux_rd[0].compare_data_fall3_r1_reg[0] (u_ddr_prbs_gen_n_114),\n .\\gen_mux_rd[0].compare_data_rise0_r1_reg[0] (u_ddr_prbs_gen_n_58),\n .\\gen_mux_rd[0].compare_data_rise1_r1_reg[0] (u_ddr_prbs_gen_n_74),\n .\\gen_mux_rd[0].compare_data_rise2_r1_reg[0] (u_ddr_prbs_gen_n_90),\n .\\gen_mux_rd[0].compare_data_rise3_r1_reg[0] (u_ddr_prbs_gen_n_106),\n .\\gen_mux_rd[1].compare_data_fall0_r1_reg[1] (u_ddr_prbs_gen_n_67),\n .\\gen_mux_rd[1].compare_data_fall1_r1_reg[1] (u_ddr_prbs_gen_n_83),\n .\\gen_mux_rd[1].compare_data_fall2_r1_reg[1] (u_ddr_prbs_gen_n_99),\n .\\gen_mux_rd[1].compare_data_fall3_r1_reg[1] (u_ddr_prbs_gen_n_115),\n .\\gen_mux_rd[1].compare_data_rise0_r1_reg[1] (u_ddr_prbs_gen_n_59),\n .\\gen_mux_rd[1].compare_data_rise1_r1_reg[1] (u_ddr_prbs_gen_n_75),\n .\\gen_mux_rd[1].compare_data_rise2_r1_reg[1] (u_ddr_prbs_gen_n_91),\n .\\gen_mux_rd[1].compare_data_rise3_r1_reg[1] (u_ddr_prbs_gen_n_107),\n .\\gen_mux_rd[2].compare_data_fall0_r1_reg[2] (u_ddr_prbs_gen_n_68),\n .\\gen_mux_rd[2].compare_data_fall2_r1_reg[2] (u_ddr_prbs_gen_n_100),\n .\\gen_mux_rd[2].compare_data_fall3_r1_reg[2] (u_ddr_prbs_gen_n_116),\n .\\gen_mux_rd[2].compare_data_rise0_r1_reg[2] (u_ddr_prbs_gen_n_60),\n .\\gen_mux_rd[2].compare_data_rise1_r1_reg[2] (u_ddr_prbs_gen_n_76),\n .\\gen_mux_rd[2].compare_data_rise2_r1_reg[2] (u_ddr_prbs_gen_n_92),\n .\\gen_mux_rd[2].compare_data_rise3_r1_reg[2] (u_ddr_prbs_gen_n_108),\n .\\gen_mux_rd[3].compare_data_fall0_r1_reg[3] (u_ddr_prbs_gen_n_69),\n .\\gen_mux_rd[3].compare_data_fall1_r1_reg[3] (u_ddr_prbs_gen_n_85),\n .\\gen_mux_rd[3].compare_data_fall3_r1_reg[3] (u_ddr_prbs_gen_n_117),\n .\\gen_mux_rd[3].compare_data_rise0_r1_reg[3] (u_ddr_prbs_gen_n_61),\n .\\gen_mux_rd[3].compare_data_rise1_r1_reg[3] (u_ddr_prbs_gen_n_77),\n .\\gen_mux_rd[3].compare_data_rise2_r1_reg[3] (u_ddr_prbs_gen_n_93),\n .\\gen_mux_rd[3].compare_data_rise3_r1_reg[3] (u_ddr_prbs_gen_n_109),\n .\\gen_mux_rd[4].compare_data_fall0_r1_reg[4] (u_ddr_prbs_gen_n_70),\n .\\gen_mux_rd[4].compare_data_fall1_r1_reg[4] (u_ddr_prbs_gen_n_86),\n .\\gen_mux_rd[4].compare_data_fall2_r1_reg[4] (u_ddr_prbs_gen_n_102),\n .\\gen_mux_rd[4].compare_data_fall3_r1_reg[4] (u_ddr_prbs_gen_n_118),\n .\\gen_mux_rd[4].compare_data_rise0_r1_reg[4] (u_ddr_prbs_gen_n_62),\n .\\gen_mux_rd[4].compare_data_rise1_r1_reg[4] (u_ddr_prbs_gen_n_78),\n .\\gen_mux_rd[4].compare_data_rise2_r1_reg[4] (u_ddr_prbs_gen_n_94),\n .\\gen_mux_rd[4].compare_data_rise3_r1_reg[4] (u_ddr_prbs_gen_n_110),\n .\\gen_mux_rd[5].compare_data_fall0_r1_reg[5] (u_ddr_prbs_gen_n_71),\n .\\gen_mux_rd[5].compare_data_fall1_r1_reg[5] (u_ddr_prbs_gen_n_87),\n .\\gen_mux_rd[5].compare_data_fall2_r1_reg[5] (u_ddr_prbs_gen_n_103),\n .\\gen_mux_rd[5].compare_data_fall3_r1_reg[5] (u_ddr_prbs_gen_n_119),\n .\\gen_mux_rd[5].compare_data_rise0_r1_reg[5] (u_ddr_prbs_gen_n_63),\n .\\gen_mux_rd[5].compare_data_rise1_r1_reg[5] (u_ddr_prbs_gen_n_79),\n .\\gen_mux_rd[5].compare_data_rise2_r1_reg[5] (u_ddr_prbs_gen_n_95),\n .\\gen_mux_rd[5].compare_data_rise3_r1_reg[5] (u_ddr_prbs_gen_n_111),\n .\\gen_mux_rd[6].compare_data_fall0_r1_reg[6] (u_ddr_prbs_gen_n_72),\n .\\gen_mux_rd[6].compare_data_fall2_r1_reg[6] (u_ddr_prbs_gen_n_104),\n .\\gen_mux_rd[6].compare_data_fall3_r1_reg[6] (u_ddr_prbs_gen_n_120),\n .\\gen_mux_rd[6].compare_data_rise0_r1_reg[6] (u_ddr_prbs_gen_n_64),\n .\\gen_mux_rd[6].compare_data_rise1_r1_reg[6] (u_ddr_prbs_gen_n_80),\n .\\gen_mux_rd[6].compare_data_rise2_r1_reg[6] (u_ddr_prbs_gen_n_96),\n .\\gen_mux_rd[6].compare_data_rise3_r1_reg[6] (u_ddr_prbs_gen_n_112),\n .\\gen_mux_rd[7].compare_data_fall0_r1_reg[7] (u_ddr_prbs_gen_n_73),\n .\\gen_mux_rd[7].compare_data_fall1_r1_reg[7] (u_ddr_prbs_gen_n_89),\n .\\gen_mux_rd[7].compare_data_fall3_r1_reg[7] (u_ddr_prbs_gen_n_121),\n .\\gen_mux_rd[7].compare_data_rise0_r1_reg[7] (u_ddr_prbs_gen_n_65),\n .\\gen_mux_rd[7].compare_data_rise1_r1_reg[7] (u_ddr_prbs_gen_n_81),\n .\\gen_mux_rd[7].compare_data_rise2_r1_reg[7] (u_ddr_prbs_gen_n_97),\n .\\gen_mux_rd[7].compare_data_rise3_r1_reg[7] (u_ddr_prbs_gen_n_113),\n .oclkdelay_calib_done_r_reg(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ),\n .\\rd_addr_reg[0]_0 (u_ddr_prbs_gen_n_0),\n .\\rd_addr_reg[3]_0 (u_ddr_phy_init_n_785),\n .rdlvl_stg1_done_int_reg(\\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_56 ),\n .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),\n .wrcal_done_reg(u_ddr_phy_wrcal_n_82),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[120] (u_ddr_prbs_gen_n_1),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[121] (u_ddr_prbs_gen_n_29),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[122] (u_ddr_prbs_gen_n_84),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[123] (u_ddr_prbs_gen_n_30),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[124] (u_ddr_prbs_gen_n_2),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[125] (u_ddr_prbs_gen_n_31),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[126] (u_ddr_prbs_gen_n_88),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[127] (u_ddr_prbs_gen_n_32),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[152] (u_ddr_prbs_gen_n_22),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[153] (u_ddr_prbs_gen_n_42),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[154] (u_ddr_prbs_gen_n_15),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[155] (u_ddr_prbs_gen_n_52),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[156] (u_ddr_prbs_gen_n_21),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[157] (u_ddr_prbs_gen_n_41),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[158] (u_ddr_prbs_gen_n_16),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[159] (u_ddr_prbs_gen_n_51),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[184] (u_ddr_prbs_gen_n_33),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[185] (u_ddr_prbs_gen_n_39),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] (u_ddr_prbs_gen_n_5),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187] (u_ddr_prbs_gen_n_101),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[188] (u_ddr_prbs_gen_n_34),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[189] (u_ddr_prbs_gen_n_40),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[190] (u_ddr_prbs_gen_n_6),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] (u_ddr_prbs_gen_n_105),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[216] (u_ddr_prbs_gen_n_35),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[217] (u_ddr_prbs_gen_n_50),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[218] (u_ddr_prbs_gen_n_20),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[219] (u_ddr_prbs_gen_n_36),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[220] (u_ddr_prbs_gen_n_37),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] (u_ddr_prbs_gen_n_49),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[222] (u_ddr_prbs_gen_n_19),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[223] (u_ddr_prbs_gen_n_38),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[248] (u_ddr_prbs_gen_n_47),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[249] (u_ddr_prbs_gen_n_3),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[24] (u_ddr_prbs_gen_n_9),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[251] (u_ddr_prbs_gen_n_7),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[252] (u_ddr_prbs_gen_n_48),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[253] (u_ddr_prbs_gen_n_4),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[255] (u_ddr_prbs_gen_n_8),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[25] (u_ddr_prbs_gen_n_23),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[26] (u_ddr_prbs_gen_n_26),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[27] (u_ddr_prbs_gen_n_10),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[28] (u_ddr_prbs_gen_n_11),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[29] (u_ddr_prbs_gen_n_24),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[30] (u_ddr_prbs_gen_n_25),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[31] (u_ddr_prbs_gen_n_12),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] (u_ddr_prbs_gen_n_55),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[58] (u_ddr_prbs_gen_n_43),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[59] (u_ddr_prbs_gen_n_44),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[61] (u_ddr_prbs_gen_n_56),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[62] (u_ddr_prbs_gen_n_45),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[63] (u_ddr_prbs_gen_n_46),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[88] (u_ddr_prbs_gen_n_54),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[89] (u_ddr_prbs_gen_n_13),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[90] (u_ddr_prbs_gen_n_17),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] (u_ddr_prbs_gen_n_27),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[92] (u_ddr_prbs_gen_n_53),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[93] (u_ddr_prbs_gen_n_14),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[94] (u_ddr_prbs_gen_n_18),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[95] (u_ddr_prbs_gen_n_28));\n LUT6 #(\n .INIT(64'hEEBAFFFF00001000)) \n wl_edge_detect_valid_r_i_1\n (.I0(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_29 ),\n .I1(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_30 ),\n .I2(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_28 ),\n .I3(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_27 ),\n .I4(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_31 ),\n .I5(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_8 ),\n .O(wl_edge_detect_valid_r_i_1_n_0));\n LUT5 #(\n .INIT(32'hA2A200A2)) \n wr_level_done_i_1\n (.I0(done_dqs_tap_inc),\n .I1(wrlvl_final_mux),\n .I2(wrlvl_final_r),\n .I3(wrlvl_byte_redo),\n .I4(wrlvl_byte_redo_r),\n .O(wr_level_done_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFFFF0200000002)) \n wr_level_done_r_i_1\n (.I0(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_31 ),\n .I1(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_41 ),\n .I2(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_42 ),\n .I3(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_29 ),\n .I4(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_54 ),\n .I5(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_0 ),\n .O(wr_level_done_r_i_1_n_0));\n LUT5 #(\n .INIT(32'hF8FFF800)) \n wrcal_pat_resume_r_i_1\n (.I0(u_ddr_phy_wrcal_n_109),\n .I1(u_ddr_phy_wrcal_n_69),\n .I2(u_ddr_phy_wrcal_n_110),\n .I3(u_ddr_phy_wrcal_n_112),\n .I4(wrcal_pat_resume_r),\n .O(wrcal_pat_resume_r_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFF00004000)) \n wrcal_sanity_chk_done_i_1\n (.I0(u_ddr_phy_wrcal_n_108),\n .I1(u_ddr_phy_wrcal_n_109),\n .I2(u_ddr_phy_wrcal_n_5),\n .I3(u_ddr_phy_wrcal_n_110),\n .I4(u_ddr_phy_wrcal_n_111),\n .I5(u_ddr_phy_wrcal_n_71),\n .O(wrcal_sanity_chk_done_i_1_n_0));\n LUT6 #(\n .INIT(64'h0EFFFFFF0E000000)) \n wrlvl_byte_redo_i_1\n (.I0(u_ddr_phy_wrcal_n_66),\n .I1(u_ddr_phy_wrcal_n_67),\n .I2(u_ddr_phy_wrcal_n_110),\n .I3(u_ddr_phy_wrcal_n_118),\n .I4(u_ddr_phy_wrcal_n_111),\n .I5(wrlvl_byte_redo),\n .O(wrlvl_byte_redo_i_1_n_0));\n FDRE wrlvl_final_mux_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\oclk_calib.u_ddr_phy_oclkdelay_cal_n_11 ),\n .Q(wrlvl_final_mux),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h40FF4000)) \n wrlvl_rank_done_r_i_1\n (.I0(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_29 ),\n .I1(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_31 ),\n .I2(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_27 ),\n .I3(\\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_55 ),\n .I4(wrlvl_rank_done),\n .O(wrlvl_rank_done_r_i_1_n_0));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_ddr_if_post_fifo\n (\\not_strict_mode.app_rd_data_reg[228] ,\n \\not_strict_mode.app_rd_data_reg[231] ,\n \\not_strict_mode.app_rd_data_reg[0] ,\n \\not_strict_mode.app_rd_data_reg[1] ,\n \\not_strict_mode.app_rd_data_reg[2] ,\n \\not_strict_mode.app_rd_data_reg[3] ,\n \\not_strict_mode.app_rd_data_reg[4] ,\n \\not_strict_mode.app_rd_data_reg[5] ,\n \\not_strict_mode.app_rd_data_reg[6] ,\n \\not_strict_mode.app_rd_data_reg[7] ,\n \\not_strict_mode.app_rd_data_reg[32] ,\n \\not_strict_mode.app_rd_data_reg[33] ,\n \\not_strict_mode.app_rd_data_reg[34] ,\n \\not_strict_mode.app_rd_data_reg[35] ,\n \\not_strict_mode.app_rd_data_reg[36] ,\n \\not_strict_mode.app_rd_data_reg[37] ,\n \\not_strict_mode.app_rd_data_reg[38] ,\n \\not_strict_mode.app_rd_data_reg[39] ,\n \\not_strict_mode.app_rd_data_reg[64] ,\n \\not_strict_mode.app_rd_data_reg[65] ,\n \\not_strict_mode.app_rd_data_reg[66] ,\n \\not_strict_mode.app_rd_data_reg[67] ,\n \\not_strict_mode.app_rd_data_reg[68] ,\n \\not_strict_mode.app_rd_data_reg[69] ,\n \\not_strict_mode.app_rd_data_reg[70] ,\n \\not_strict_mode.app_rd_data_reg[71] ,\n \\not_strict_mode.app_rd_data_reg[96] ,\n \\not_strict_mode.app_rd_data_reg[97] ,\n \\not_strict_mode.app_rd_data_reg[98] ,\n \\not_strict_mode.app_rd_data_reg[99] ,\n \\not_strict_mode.app_rd_data_reg[100] ,\n \\not_strict_mode.app_rd_data_reg[101] ,\n \\not_strict_mode.app_rd_data_reg[102] ,\n \\not_strict_mode.app_rd_data_reg[103] ,\n \\not_strict_mode.app_rd_data_reg[128] ,\n \\not_strict_mode.app_rd_data_reg[129] ,\n \\not_strict_mode.app_rd_data_reg[130] ,\n \\not_strict_mode.app_rd_data_reg[131] ,\n \\not_strict_mode.app_rd_data_reg[132] ,\n \\not_strict_mode.app_rd_data_reg[133] ,\n \\not_strict_mode.app_rd_data_reg[134] ,\n \\not_strict_mode.app_rd_data_reg[135] ,\n \\not_strict_mode.app_rd_data_reg[160] ,\n \\not_strict_mode.app_rd_data_reg[161] ,\n \\not_strict_mode.app_rd_data_reg[162] ,\n \\not_strict_mode.app_rd_data_reg[163] ,\n \\not_strict_mode.app_rd_data_reg[164] ,\n \\not_strict_mode.app_rd_data_reg[165] ,\n \\not_strict_mode.app_rd_data_reg[166] ,\n \\not_strict_mode.app_rd_data_reg[167] ,\n \\not_strict_mode.app_rd_data_reg[192] ,\n \\not_strict_mode.app_rd_data_reg[193] ,\n \\not_strict_mode.app_rd_data_reg[194] ,\n \\not_strict_mode.app_rd_data_reg[195] ,\n \\not_strict_mode.app_rd_data_reg[196] ,\n \\not_strict_mode.app_rd_data_reg[197] ,\n \\not_strict_mode.app_rd_data_reg[198] ,\n \\not_strict_mode.app_rd_data_reg[199] ,\n \\not_strict_mode.app_rd_data_reg[224] ,\n \\not_strict_mode.app_rd_data_reg[225] ,\n \\not_strict_mode.app_rd_data_reg[226] ,\n \\not_strict_mode.app_rd_data_reg[227] ,\n \\not_strict_mode.app_rd_data_reg[228]_0 ,\n \\not_strict_mode.app_rd_data_reg[229] ,\n \\not_strict_mode.app_rd_data_reg[230] ,\n \\not_strict_mode.app_rd_data_reg[231]_0 ,\n mux_rd_valid_r_reg,\n \\not_strict_mode.app_rd_data_reg[7]_0 ,\n D_byte_rd_en,\n ififo_rst,\n CLK,\n if_empty_r_1,\n \\read_fifo.fifo_out_data_r_reg[6] ,\n DOC,\n DOB,\n DOA,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,\n \\my_empty_reg[4]_0 ,\n if_empty_r,\n Q,\n C_byte_rd_en,\n A_byte_rd_en,\n if_empty_r_0,\n \\my_empty_reg[4]_1 );\n output \\not_strict_mode.app_rd_data_reg[228] ;\n output [63:0]\\not_strict_mode.app_rd_data_reg[231] ;\n output \\not_strict_mode.app_rd_data_reg[0] ;\n output \\not_strict_mode.app_rd_data_reg[1] ;\n output \\not_strict_mode.app_rd_data_reg[2] ;\n output \\not_strict_mode.app_rd_data_reg[3] ;\n output \\not_strict_mode.app_rd_data_reg[4] ;\n output \\not_strict_mode.app_rd_data_reg[5] ;\n output \\not_strict_mode.app_rd_data_reg[6] ;\n output \\not_strict_mode.app_rd_data_reg[7] ;\n output \\not_strict_mode.app_rd_data_reg[32] ;\n output \\not_strict_mode.app_rd_data_reg[33] ;\n output \\not_strict_mode.app_rd_data_reg[34] ;\n output \\not_strict_mode.app_rd_data_reg[35] ;\n output \\not_strict_mode.app_rd_data_reg[36] ;\n output \\not_strict_mode.app_rd_data_reg[37] ;\n output \\not_strict_mode.app_rd_data_reg[38] ;\n output \\not_strict_mode.app_rd_data_reg[39] ;\n output \\not_strict_mode.app_rd_data_reg[64] ;\n output \\not_strict_mode.app_rd_data_reg[65] ;\n output \\not_strict_mode.app_rd_data_reg[66] ;\n output \\not_strict_mode.app_rd_data_reg[67] ;\n output \\not_strict_mode.app_rd_data_reg[68] ;\n output \\not_strict_mode.app_rd_data_reg[69] ;\n output \\not_strict_mode.app_rd_data_reg[70] ;\n output \\not_strict_mode.app_rd_data_reg[71] ;\n output \\not_strict_mode.app_rd_data_reg[96] ;\n output \\not_strict_mode.app_rd_data_reg[97] ;\n output \\not_strict_mode.app_rd_data_reg[98] ;\n output \\not_strict_mode.app_rd_data_reg[99] ;\n output \\not_strict_mode.app_rd_data_reg[100] ;\n output \\not_strict_mode.app_rd_data_reg[101] ;\n output \\not_strict_mode.app_rd_data_reg[102] ;\n output \\not_strict_mode.app_rd_data_reg[103] ;\n output \\not_strict_mode.app_rd_data_reg[128] ;\n output \\not_strict_mode.app_rd_data_reg[129] ;\n output \\not_strict_mode.app_rd_data_reg[130] ;\n output \\not_strict_mode.app_rd_data_reg[131] ;\n output \\not_strict_mode.app_rd_data_reg[132] ;\n output \\not_strict_mode.app_rd_data_reg[133] ;\n output \\not_strict_mode.app_rd_data_reg[134] ;\n output \\not_strict_mode.app_rd_data_reg[135] ;\n output \\not_strict_mode.app_rd_data_reg[160] ;\n output \\not_strict_mode.app_rd_data_reg[161] ;\n output \\not_strict_mode.app_rd_data_reg[162] ;\n output \\not_strict_mode.app_rd_data_reg[163] ;\n output \\not_strict_mode.app_rd_data_reg[164] ;\n output \\not_strict_mode.app_rd_data_reg[165] ;\n output \\not_strict_mode.app_rd_data_reg[166] ;\n output \\not_strict_mode.app_rd_data_reg[167] ;\n output \\not_strict_mode.app_rd_data_reg[192] ;\n output \\not_strict_mode.app_rd_data_reg[193] ;\n output \\not_strict_mode.app_rd_data_reg[194] ;\n output \\not_strict_mode.app_rd_data_reg[195] ;\n output \\not_strict_mode.app_rd_data_reg[196] ;\n output \\not_strict_mode.app_rd_data_reg[197] ;\n output \\not_strict_mode.app_rd_data_reg[198] ;\n output \\not_strict_mode.app_rd_data_reg[199] ;\n output \\not_strict_mode.app_rd_data_reg[224] ;\n output \\not_strict_mode.app_rd_data_reg[225] ;\n output \\not_strict_mode.app_rd_data_reg[226] ;\n output \\not_strict_mode.app_rd_data_reg[227] ;\n output \\not_strict_mode.app_rd_data_reg[228]_0 ;\n output \\not_strict_mode.app_rd_data_reg[229] ;\n output \\not_strict_mode.app_rd_data_reg[230] ;\n output \\not_strict_mode.app_rd_data_reg[231]_0 ;\n output mux_rd_valid_r_reg;\n output [0:0]\\not_strict_mode.app_rd_data_reg[7]_0 ;\n output D_byte_rd_en;\n input ififo_rst;\n input CLK;\n input [0:0]if_empty_r_1;\n input \\read_fifo.fifo_out_data_r_reg[6] ;\n input [1:0]DOC;\n input [1:0]DOB;\n input [1:0]DOA;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n input [0:0]\\my_empty_reg[4]_0 ;\n input [0:0]if_empty_r;\n input [65:0]Q;\n input C_byte_rd_en;\n input A_byte_rd_en;\n input [0:0]if_empty_r_0;\n input [0:0]\\my_empty_reg[4]_1 ;\n\n wire A_byte_rd_en;\n wire CLK;\n wire C_byte_rd_en;\n wire [1:0]DOA;\n wire [1:0]DOB;\n wire [1:0]DOC;\n wire D_byte_rd_en;\n wire [65:0]Q;\n wire [0:0]if_empty_r;\n wire [0:0]if_empty_r_0;\n wire [0:0]if_empty_r_1;\n wire ififo_rst;\n wire [71:9]mem_out;\n wire mem_reg_0_3_6_11_n_0;\n wire mem_reg_0_3_6_11_n_1;\n wire mux_rd_valid_r_reg;\n wire [3:0]my_empty;\n wire \\my_empty[4]_i_1_n_0 ;\n wire \\my_empty[4]_i_2__2_n_0 ;\n wire [0:0]\\my_empty_reg[4]_0 ;\n wire [0:0]\\my_empty_reg[4]_1 ;\n wire \\my_empty_reg[4]_rep__0_n_0 ;\n wire \\my_empty_reg[4]_rep_n_0 ;\n wire [1:0]my_full;\n wire \\my_full[0]_i_1__2_n_0 ;\n wire \\my_full[0]_i_2__2_n_0 ;\n wire \\my_full[1]_i_1__2_n_0 ;\n wire \\my_full[1]_i_2__2_n_0 ;\n wire \\not_strict_mode.app_rd_data_reg[0] ;\n wire \\not_strict_mode.app_rd_data_reg[100] ;\n wire \\not_strict_mode.app_rd_data_reg[101] ;\n wire \\not_strict_mode.app_rd_data_reg[102] ;\n wire \\not_strict_mode.app_rd_data_reg[103] ;\n wire \\not_strict_mode.app_rd_data_reg[128] ;\n wire \\not_strict_mode.app_rd_data_reg[129] ;\n wire \\not_strict_mode.app_rd_data_reg[130] ;\n wire \\not_strict_mode.app_rd_data_reg[131] ;\n wire \\not_strict_mode.app_rd_data_reg[132] ;\n wire \\not_strict_mode.app_rd_data_reg[133] ;\n wire \\not_strict_mode.app_rd_data_reg[134] ;\n wire \\not_strict_mode.app_rd_data_reg[135] ;\n wire \\not_strict_mode.app_rd_data_reg[160] ;\n wire \\not_strict_mode.app_rd_data_reg[161] ;\n wire \\not_strict_mode.app_rd_data_reg[162] ;\n wire \\not_strict_mode.app_rd_data_reg[163] ;\n wire \\not_strict_mode.app_rd_data_reg[164] ;\n wire \\not_strict_mode.app_rd_data_reg[165] ;\n wire \\not_strict_mode.app_rd_data_reg[166] ;\n wire \\not_strict_mode.app_rd_data_reg[167] ;\n wire \\not_strict_mode.app_rd_data_reg[192] ;\n wire \\not_strict_mode.app_rd_data_reg[193] ;\n wire \\not_strict_mode.app_rd_data_reg[194] ;\n wire \\not_strict_mode.app_rd_data_reg[195] ;\n wire \\not_strict_mode.app_rd_data_reg[196] ;\n wire \\not_strict_mode.app_rd_data_reg[197] ;\n wire \\not_strict_mode.app_rd_data_reg[198] ;\n wire \\not_strict_mode.app_rd_data_reg[199] ;\n wire \\not_strict_mode.app_rd_data_reg[1] ;\n wire \\not_strict_mode.app_rd_data_reg[224] ;\n wire \\not_strict_mode.app_rd_data_reg[225] ;\n wire \\not_strict_mode.app_rd_data_reg[226] ;\n wire \\not_strict_mode.app_rd_data_reg[227] ;\n wire \\not_strict_mode.app_rd_data_reg[228] ;\n wire \\not_strict_mode.app_rd_data_reg[228]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[229] ;\n wire \\not_strict_mode.app_rd_data_reg[230] ;\n wire [63:0]\\not_strict_mode.app_rd_data_reg[231] ;\n wire \\not_strict_mode.app_rd_data_reg[231]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[2] ;\n wire \\not_strict_mode.app_rd_data_reg[32] ;\n wire \\not_strict_mode.app_rd_data_reg[33] ;\n wire \\not_strict_mode.app_rd_data_reg[34] ;\n wire \\not_strict_mode.app_rd_data_reg[35] ;\n wire \\not_strict_mode.app_rd_data_reg[36] ;\n wire \\not_strict_mode.app_rd_data_reg[37] ;\n wire \\not_strict_mode.app_rd_data_reg[38] ;\n wire \\not_strict_mode.app_rd_data_reg[39] ;\n wire \\not_strict_mode.app_rd_data_reg[3] ;\n wire \\not_strict_mode.app_rd_data_reg[4] ;\n wire \\not_strict_mode.app_rd_data_reg[5] ;\n wire \\not_strict_mode.app_rd_data_reg[64] ;\n wire \\not_strict_mode.app_rd_data_reg[65] ;\n wire \\not_strict_mode.app_rd_data_reg[66] ;\n wire \\not_strict_mode.app_rd_data_reg[67] ;\n wire \\not_strict_mode.app_rd_data_reg[68] ;\n wire \\not_strict_mode.app_rd_data_reg[69] ;\n wire \\not_strict_mode.app_rd_data_reg[6] ;\n wire \\not_strict_mode.app_rd_data_reg[70] ;\n wire \\not_strict_mode.app_rd_data_reg[71] ;\n wire \\not_strict_mode.app_rd_data_reg[7] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[7]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[96] ;\n wire \\not_strict_mode.app_rd_data_reg[97] ;\n wire \\not_strict_mode.app_rd_data_reg[98] ;\n wire \\not_strict_mode.app_rd_data_reg[99] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n wire \\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ;\n wire [1:0]rd_ptr;\n wire \\rd_ptr[0]_i_1__2_n_0 ;\n wire \\rd_ptr[1]_i_1__2_n_0 ;\n (* RTL_KEEP = \"true\" *) (* syn_maxfan = \"10\" *) wire [1:0]rd_ptr_timing;\n wire \\rd_ptr_timing[0]_i_1__6_n_0 ;\n wire \\rd_ptr_timing[1]_i_1__7_n_0 ;\n wire \\read_fifo.fifo_out_data_r_reg[6] ;\n (* MAX_FANOUT = \"40\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire wr_en;\n wire [1:0]wr_ptr;\n wire \\wr_ptr[0]_i_1__8_n_0 ;\n wire \\wr_ptr[1]_i_1__8_n_0 ;\n wire \\wr_ptr[1]_i_3__2_n_0 ;\n wire [1:0]NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED;\n\n (* SOFT_HLUTNM = \"soft_lutpair890\" *) \n LUT4 #(\n .INIT(16'hF888)) \n i___114_i_3\n (.I0(my_empty[0]),\n .I1(if_empty_r_1),\n .I2(\\my_empty_reg[4]_0 ),\n .I3(if_empty_r),\n .O(mux_rd_valid_r_reg));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_12_17\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[7:6]),\n .DIB(Q[9:8]),\n .DIC(Q[11:10]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[13:12]),\n .DOB(mem_out[15:14]),\n .DOC(mem_out[17:16]),\n .DOD(NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_18_23\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[13:12]),\n .DIB(Q[15:14]),\n .DIC(Q[17:16]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[19:18]),\n .DOB(mem_out[21:20]),\n .DOC(mem_out[23:22]),\n .DOD(NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_24_29\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[19:18]),\n .DIB(Q[21:20]),\n .DIC(Q[23:22]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[25:24]),\n .DOB(mem_out[27:26]),\n .DOC(mem_out[29:28]),\n .DOD(NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_30_35\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[25:24]),\n .DIB(Q[27:26]),\n .DIC(Q[29:28]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[31:30]),\n .DOB(mem_out[33:32]),\n .DOC(mem_out[35:34]),\n .DOD(NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_36_41\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[31:30]),\n .DIB(Q[33:32]),\n .DIC(Q[35:34]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[37:36]),\n .DOB(mem_out[39:38]),\n .DOC(mem_out[41:40]),\n .DOD(NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_42_47\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[37:36]),\n .DIB(Q[39:38]),\n .DIC(Q[41:40]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[43:42]),\n .DOB(mem_out[45:44]),\n .DOC(mem_out[47:46]),\n .DOD(NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_48_53\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[43:42]),\n .DIB(Q[45:44]),\n .DIC(Q[47:46]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[49:48]),\n .DOB(mem_out[51:50]),\n .DOC(mem_out[53:52]),\n .DOD(NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_54_59\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[49:48]),\n .DIB(Q[51:50]),\n .DIC(Q[53:52]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[55:54]),\n .DOB(mem_out[57:56]),\n .DOC(mem_out[59:58]),\n .DOD(NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_60_65\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[55:54]),\n .DIB(Q[57:56]),\n .DIC(Q[59:58]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[61:60]),\n .DOB(mem_out[63:62]),\n .DOC(mem_out[65:64]),\n .DOD(NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_66_71\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[61:60]),\n .DIB(Q[63:62]),\n .DIC(Q[65:64]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[67:66]),\n .DOB(mem_out[69:68]),\n .DOC(mem_out[71:70]),\n .DOD(NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_6_11\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[1:0]),\n .DIB(Q[3:2]),\n .DIC(Q[5:4]),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_3_6_11_n_0,mem_reg_0_3_6_11_n_1}),\n .DOB({mem_out[9],\\not_strict_mode.app_rd_data_reg[7]_0 }),\n .DOC(mem_out[11:10]),\n .DOD(NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n LUT4 #(\n .INIT(16'h0151)) \n mem_reg_0_3_6_11_i_1__1\n (.I0(if_empty_r_1),\n .I1(my_full[0]),\n .I2(\\wr_ptr[1]_i_3__2_n_0 ),\n .I3(my_empty[2]),\n .O(wr_en));\n (* SOFT_HLUTNM = \"soft_lutpair923\" *) \n LUT1 #(\n .INIT(2'h2)) \n mem_reg_0_3_6_11_i_2__1\n (.I0(my_empty[0]),\n .O(my_empty[2]));\n LUT4 #(\n .INIT(16'h0140)) \n \\my_empty[4]_i_1 \n (.I0(my_full[1]),\n .I1(if_empty_r_1),\n .I2(\\wr_ptr[1]_i_3__2_n_0 ),\n .I3(my_empty[1]),\n .O(\\my_empty[4]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h00000960)) \n \\my_empty[4]_i_2__2 \n (.I0(wr_ptr[1]),\n .I1(rd_ptr[1]),\n .I2(rd_ptr[0]),\n .I3(wr_ptr[0]),\n .I4(my_empty[1]),\n .O(\\my_empty[4]_i_2__2_n_0 ));\n (* ORIG_CELL_NAME = \"my_empty_reg[4]\" *) \n FDSE \\my_empty_reg[4] \n (.C(CLK),\n .CE(\\my_empty[4]_i_1_n_0 ),\n .D(\\my_empty[4]_i_2__2_n_0 ),\n .Q(my_empty[0]),\n .S(ififo_rst));\n (* ORIG_CELL_NAME = \"my_empty_reg[4]\" *) \n FDSE \\my_empty_reg[4]_rep \n (.C(CLK),\n .CE(\\my_empty[4]_i_1_n_0 ),\n .D(\\my_empty[4]_i_2__2_n_0 ),\n .Q(\\my_empty_reg[4]_rep_n_0 ),\n .S(ififo_rst));\n (* ORIG_CELL_NAME = \"my_empty_reg[4]\" *) \n FDSE \\my_empty_reg[4]_rep__0 \n (.C(CLK),\n .CE(\\my_empty[4]_i_1_n_0 ),\n .D(\\my_empty[4]_i_2__2_n_0 ),\n .Q(\\my_empty_reg[4]_rep__0_n_0 ),\n .S(ififo_rst));\n LUT6 #(\n .INIT(64'hBAAAAAAB8AAAAAA8)) \n \\my_full[0]_i_1__2 \n (.I0(my_full[0]),\n .I1(my_empty[1]),\n .I2(my_full[1]),\n .I3(if_empty_r_1),\n .I4(\\wr_ptr[1]_i_3__2_n_0 ),\n .I5(\\my_full[0]_i_2__2_n_0 ),\n .O(\\my_full[0]_i_1__2_n_0 ));\n LUT5 #(\n .INIT(32'h00000960)) \n \\my_full[0]_i_2__2 \n (.I0(rd_ptr[1]),\n .I1(wr_ptr[1]),\n .I2(wr_ptr[0]),\n .I3(rd_ptr[0]),\n .I4(my_full[1]),\n .O(\\my_full[0]_i_2__2_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAA00411400)) \n \\my_full[1]_i_1__2 \n (.I0(\\my_full[1]_i_2__2_n_0 ),\n .I1(rd_ptr[1]),\n .I2(wr_ptr[1]),\n .I3(wr_ptr[0]),\n .I4(rd_ptr[0]),\n .I5(my_full[1]),\n .O(\\my_full[1]_i_1__2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair888\" *) \n LUT4 #(\n .INIT(16'hBFFE)) \n \\my_full[1]_i_2__2 \n (.I0(my_empty[1]),\n .I1(my_full[1]),\n .I2(if_empty_r_1),\n .I3(\\wr_ptr[1]_i_3__2_n_0 ),\n .O(\\my_full[1]_i_2__2_n_0 ));\n FDRE \\my_full_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_full[0]_i_1__2_n_0 ),\n .Q(my_full[0]),\n .R(ififo_rst));\n FDRE \\my_full_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_full[1]_i_1__2_n_0 ),\n .Q(my_full[1]),\n .R(ififo_rst));\n (* SOFT_HLUTNM = \"soft_lutpair891\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[0] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(DOC[0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [0]));\n (* SOFT_HLUTNM = \"soft_lutpair905\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[100]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[100] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [28]));\n (* SOFT_HLUTNM = \"soft_lutpair905\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[101]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[101] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [29]));\n (* SOFT_HLUTNM = \"soft_lutpair906\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[102]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[102] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [30]));\n (* SOFT_HLUTNM = \"soft_lutpair906\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[103]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[103] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [31]));\n (* SOFT_HLUTNM = \"soft_lutpair907\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[128]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[128] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [32]));\n (* SOFT_HLUTNM = \"soft_lutpair907\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[129]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[129] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [33]));\n (* SOFT_HLUTNM = \"soft_lutpair908\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[130]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[130] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [34]));\n (* SOFT_HLUTNM = \"soft_lutpair909\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[131]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[131] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [35]));\n (* SOFT_HLUTNM = \"soft_lutpair908\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[132]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[132] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [36]));\n (* SOFT_HLUTNM = \"soft_lutpair909\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[133]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[133] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [37]));\n (* SOFT_HLUTNM = \"soft_lutpair910\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[134]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[134] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [38]));\n (* SOFT_HLUTNM = \"soft_lutpair910\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[135]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[135] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [39]));\n (* SOFT_HLUTNM = \"soft_lutpair911\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[160]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[160] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [40]));\n (* SOFT_HLUTNM = \"soft_lutpair911\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[161]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[161] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [41]));\n (* SOFT_HLUTNM = \"soft_lutpair912\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[162]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[162] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [42]));\n (* SOFT_HLUTNM = \"soft_lutpair912\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[163]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[163] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [43]));\n (* SOFT_HLUTNM = \"soft_lutpair913\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[164]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[164] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [44]));\n (* SOFT_HLUTNM = \"soft_lutpair913\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[165]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[165] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [45]));\n (* SOFT_HLUTNM = \"soft_lutpair914\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[166]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[166] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [46]));\n (* SOFT_HLUTNM = \"soft_lutpair914\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[167]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[167] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [47]));\n (* SOFT_HLUTNM = \"soft_lutpair915\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[192]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[192] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [48]));\n (* SOFT_HLUTNM = \"soft_lutpair915\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[193]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[193] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [49]));\n (* SOFT_HLUTNM = \"soft_lutpair916\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[194]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[194] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [50]));\n (* SOFT_HLUTNM = \"soft_lutpair916\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[195]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[195] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [51]));\n (* SOFT_HLUTNM = \"soft_lutpair917\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[196]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[196] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [52]));\n (* SOFT_HLUTNM = \"soft_lutpair917\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[197]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[197] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [53]));\n (* SOFT_HLUTNM = \"soft_lutpair918\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[198]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[198] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [54]));\n (* SOFT_HLUTNM = \"soft_lutpair918\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[199]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[199] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [55]));\n (* SOFT_HLUTNM = \"soft_lutpair892\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[1] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(DOC[1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [1]));\n (* SOFT_HLUTNM = \"soft_lutpair919\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[224]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[224] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [56]));\n (* SOFT_HLUTNM = \"soft_lutpair919\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[225]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[225] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [57]));\n (* SOFT_HLUTNM = \"soft_lutpair920\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[226]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[226] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [58]));\n (* SOFT_HLUTNM = \"soft_lutpair920\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[227]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[227] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [59]));\n (* SOFT_HLUTNM = \"soft_lutpair921\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[228]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[228]_0 ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [60]));\n (* SOFT_HLUTNM = \"soft_lutpair921\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[229]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[229] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [61]));\n (* SOFT_HLUTNM = \"soft_lutpair922\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[230]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[230] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [62]));\n (* SOFT_HLUTNM = \"soft_lutpair922\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[231]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[231]_0 ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [63]));\n (* SOFT_HLUTNM = \"soft_lutpair893\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[2] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(DOB[0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [2]));\n (* SOFT_HLUTNM = \"soft_lutpair894\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[32]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[32] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [8]));\n (* SOFT_HLUTNM = \"soft_lutpair895\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[33]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[33] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [9]));\n (* SOFT_HLUTNM = \"soft_lutpair896\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[34]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[34] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [10]));\n (* SOFT_HLUTNM = \"soft_lutpair896\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[35]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[35] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [11]));\n (* SOFT_HLUTNM = \"soft_lutpair897\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[36]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[36] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [12]));\n (* SOFT_HLUTNM = \"soft_lutpair897\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[37]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[37] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [13]));\n (* SOFT_HLUTNM = \"soft_lutpair898\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[38]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[38] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [14]));\n (* SOFT_HLUTNM = \"soft_lutpair898\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[39]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[39] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [15]));\n (* SOFT_HLUTNM = \"soft_lutpair894\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[3] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(DOB[1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [3]));\n (* SOFT_HLUTNM = \"soft_lutpair895\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[4] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(DOA[0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [4]));\n (* SOFT_HLUTNM = \"soft_lutpair891\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[5] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(DOA[1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [5]));\n (* SOFT_HLUTNM = \"soft_lutpair899\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[64]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[64] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [16]));\n (* SOFT_HLUTNM = \"soft_lutpair899\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[65]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[65] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [17]));\n (* SOFT_HLUTNM = \"soft_lutpair900\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[66]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[66] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [18]));\n (* SOFT_HLUTNM = \"soft_lutpair900\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[67]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[67] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [19]));\n (* SOFT_HLUTNM = \"soft_lutpair901\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[68]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[68] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [20]));\n (* SOFT_HLUTNM = \"soft_lutpair901\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[69]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[69] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [21]));\n (* SOFT_HLUTNM = \"soft_lutpair892\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[6] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [6]));\n (* SOFT_HLUTNM = \"soft_lutpair902\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[70]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[70] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [22]));\n (* SOFT_HLUTNM = \"soft_lutpair902\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[71]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[71] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [23]));\n (* SOFT_HLUTNM = \"soft_lutpair893\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[7] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [7]));\n (* SOFT_HLUTNM = \"soft_lutpair903\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[96]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[96] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [24]));\n (* SOFT_HLUTNM = \"soft_lutpair903\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[97]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[97] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [25]));\n (* SOFT_HLUTNM = \"soft_lutpair904\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[98]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[98] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [26]));\n (* SOFT_HLUTNM = \"soft_lutpair904\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[99]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[99] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[231] [27]));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_2 \n (.I0(Q[18]),\n .I1(mem_out[24]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[5] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_3 \n (.I0(Q[26]),\n .I1(mem_out[32]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[4] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_4 \n (.I0(Q[34]),\n .I1(mem_out[40]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[3] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_5 \n (.I0(Q[42]),\n .I1(mem_out[48]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[2] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_6 \n (.I0(Q[50]),\n .I1(mem_out[56]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[1] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_7 \n (.I0(Q[58]),\n .I1(mem_out[64]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[0] ));\n LUT1 #(\n .INIT(2'h2)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_8 \n (.I0(\\my_empty_reg[4]_rep_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[228] ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9 \n (.I0(\\my_empty_reg[4]_rep__0_n_0 ),\n .O(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_1 \n (.I0(Q[52]),\n .I1(mem_out[58]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[65] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_2 \n (.I0(Q[60]),\n .I1(mem_out[66]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[64] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_1 \n (.I0(Q[4]),\n .I1(mem_out[10]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[71] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_2 \n (.I0(Q[12]),\n .I1(mem_out[18]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[70] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_3 \n (.I0(Q[20]),\n .I1(mem_out[26]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[69] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_4 \n (.I0(Q[28]),\n .I1(mem_out[34]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[68] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_5 \n (.I0(Q[36]),\n .I1(mem_out[42]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[67] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_6 \n (.I0(Q[44]),\n .I1(mem_out[50]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[66] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_1 \n (.I0(Q[21]),\n .I1(mem_out[27]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[101] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_2 \n (.I0(Q[29]),\n .I1(mem_out[35]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[100] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_3 \n (.I0(Q[37]),\n .I1(mem_out[43]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[99] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_4 \n (.I0(Q[45]),\n .I1(mem_out[51]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[98] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_5 \n (.I0(Q[53]),\n .I1(mem_out[59]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[97] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_6 \n (.I0(Q[61]),\n .I1(mem_out[67]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[96] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_5 \n (.I0(Q[5]),\n .I1(mem_out[11]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[103] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_6 \n (.I0(Q[13]),\n .I1(mem_out[19]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[102] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_5 \n (.I0(Q[2]),\n .I1(\\not_strict_mode.app_rd_data_reg[7]_0 ),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[7] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_6 \n (.I0(Q[10]),\n .I1(mem_out[16]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[6] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_1 \n (.I0(Q[38]),\n .I1(mem_out[44]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[131] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_2 \n (.I0(Q[46]),\n .I1(mem_out[52]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[130] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_3 \n (.I0(Q[54]),\n .I1(mem_out[60]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[129] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_4 \n (.I0(Q[62]),\n .I1(mem_out[68]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[128] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_3 \n (.I0(Q[6]),\n .I1(mem_out[12]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[135] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_4 \n (.I0(Q[14]),\n .I1(mem_out[20]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[134] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_5 \n (.I0(Q[22]),\n .I1(mem_out[28]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[133] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_6 \n (.I0(Q[30]),\n .I1(mem_out[36]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[132] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_1 \n (.I0(Q[55]),\n .I1(mem_out[61]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[161] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_2 \n (.I0(Q[63]),\n .I1(mem_out[69]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[160] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_1 \n (.I0(Q[7]),\n .I1(mem_out[13]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[167] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_2 \n (.I0(Q[15]),\n .I1(mem_out[21]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[166] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_3 \n (.I0(Q[23]),\n .I1(mem_out[29]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[165] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_4 \n (.I0(Q[31]),\n .I1(mem_out[37]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[164] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_5 \n (.I0(Q[39]),\n .I1(mem_out[45]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[163] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_6 \n (.I0(Q[47]),\n .I1(mem_out[53]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[162] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_1 \n (.I0(Q[24]),\n .I1(mem_out[30]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[197] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_2 \n (.I0(Q[32]),\n .I1(mem_out[38]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[196] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_3 \n (.I0(Q[40]),\n .I1(mem_out[46]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[195] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_4 \n (.I0(Q[48]),\n .I1(mem_out[54]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[194] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_5 \n (.I0(Q[56]),\n .I1(mem_out[62]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[193] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_6 \n (.I0(Q[64]),\n .I1(mem_out[70]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[192] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_5 \n (.I0(Q[8]),\n .I1(mem_out[14]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[199] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_6 \n (.I0(Q[16]),\n .I1(mem_out[22]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[198] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_1 \n (.I0(Q[41]),\n .I1(mem_out[47]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[227] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_2 \n (.I0(Q[49]),\n .I1(mem_out[55]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[226] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_3 \n (.I0(Q[57]),\n .I1(mem_out[63]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[225] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_4 \n (.I0(Q[65]),\n .I1(mem_out[71]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[224] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_3 \n (.I0(Q[9]),\n .I1(mem_out[15]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[231]_0 ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_4 \n (.I0(Q[17]),\n .I1(mem_out[23]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[230] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_5 \n (.I0(Q[25]),\n .I1(mem_out[31]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[229] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_6 \n (.I0(Q[33]),\n .I1(mem_out[39]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[228]_0 ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_1 \n (.I0(Q[35]),\n .I1(mem_out[41]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[35] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_2 \n (.I0(Q[43]),\n .I1(mem_out[49]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[34] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_3 \n (.I0(Q[51]),\n .I1(mem_out[57]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[33] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_4 \n (.I0(Q[59]),\n .I1(mem_out[65]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_9_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[32] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_3 \n (.I0(Q[3]),\n .I1(mem_out[9]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[39] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_4 \n (.I0(Q[11]),\n .I1(mem_out[17]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[38] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_5 \n (.I0(Q[19]),\n .I1(mem_out[25]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[37] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_6 \n (.I0(Q[27]),\n .I1(mem_out[33]),\n .I2(\\not_strict_mode.app_rd_data_reg[228] ),\n .O(\\not_strict_mode.app_rd_data_reg[36] ));\n (* SOFT_HLUTNM = \"soft_lutpair889\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\rd_ptr[0]_i_1__2 \n (.I0(my_empty[1]),\n .I1(\\wr_ptr[1]_i_3__2_n_0 ),\n .I2(rd_ptr[0]),\n .O(\\rd_ptr[0]_i_1__2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair889\" *) \n LUT4 #(\n .INIT(16'hDF20)) \n \\rd_ptr[1]_i_1__2 \n (.I0(rd_ptr[0]),\n .I1(my_empty[1]),\n .I2(\\wr_ptr[1]_i_3__2_n_0 ),\n .I3(rd_ptr[1]),\n .O(\\rd_ptr[1]_i_1__2_n_0 ));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_ptr[0]_i_1__2_n_0 ),\n .Q(rd_ptr[0]),\n .R(ififo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_ptr[1]_i_1__2_n_0 ),\n .Q(rd_ptr[1]),\n .R(ififo_rst));\n LUT4 #(\n .INIT(16'hA2AE)) \n \\rd_ptr_timing[0]_i_1__6 \n (.I0(rd_ptr_timing[0]),\n .I1(\\wr_ptr[1]_i_3__2_n_0 ),\n .I2(my_empty[1]),\n .I3(rd_ptr[0]),\n .O(\\rd_ptr_timing[0]_i_1__6_n_0 ));\n LUT5 #(\n .INIT(32'hF0F066F0)) \n \\rd_ptr_timing[1]_i_1__7 \n (.I0(rd_ptr[0]),\n .I1(rd_ptr[1]),\n .I2(rd_ptr_timing[1]),\n .I3(\\wr_ptr[1]_i_3__2_n_0 ),\n .I4(my_empty[1]),\n .O(\\rd_ptr_timing[1]_i_1__7_n_0 ));\n (* KEEP = \"yes\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_ptr_timing[0]_i_1__6_n_0 ),\n .Q(rd_ptr_timing[0]),\n .R(ififo_rst));\n (* KEEP = \"yes\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_ptr_timing[1]_i_1__7_n_0 ),\n .Q(rd_ptr_timing[1]),\n .R(ififo_rst));\n (* SOFT_HLUTNM = \"soft_lutpair888\" *) \n LUT5 #(\n .INIT(32'hEEFA1105)) \n \\wr_ptr[0]_i_1__8 \n (.I0(if_empty_r_1),\n .I1(my_empty[1]),\n .I2(my_full[1]),\n .I3(\\wr_ptr[1]_i_3__2_n_0 ),\n .I4(wr_ptr[0]),\n .O(\\wr_ptr[0]_i_1__8_n_0 ));\n LUT6 #(\n .INIT(64'hFDFDFFDD02020022)) \n \\wr_ptr[1]_i_1__8 \n (.I0(wr_ptr[0]),\n .I1(if_empty_r_1),\n .I2(my_empty[1]),\n .I3(my_full[1]),\n .I4(\\wr_ptr[1]_i_3__2_n_0 ),\n .I5(wr_ptr[1]),\n .O(\\wr_ptr[1]_i_1__8_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair923\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\wr_ptr[1]_i_2__2 \n (.I0(my_empty[0]),\n .O(my_empty[1]));\n LUT6 #(\n .INIT(64'h0000700070007000)) \n \\wr_ptr[1]_i_3__2 \n (.I0(my_empty[3]),\n .I1(if_empty_r_1),\n .I2(C_byte_rd_en),\n .I3(A_byte_rd_en),\n .I4(if_empty_r_0),\n .I5(\\my_empty_reg[4]_1 ),\n .O(\\wr_ptr[1]_i_3__2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair890\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\wr_ptr[1]_i_4__1 \n (.I0(my_empty[0]),\n .O(my_empty[3]));\n LUT2 #(\n .INIT(4'h7)) \n \\wr_ptr[1]_i_5__1 \n (.I0(if_empty_r_1),\n .I1(my_empty[3]),\n .O(D_byte_rd_en));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_ptr[0]_i_1__8_n_0 ),\n .Q(wr_ptr[0]),\n .R(ififo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_ptr[1]_i_1__8_n_0 ),\n .Q(wr_ptr[1]),\n .R(ififo_rst));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_if_post_fifo\" *) \nmodule ddr3_if_mig_7series_v4_0_ddr_if_post_fifo_6\n (phy_if_empty_r_reg,\n \\not_strict_mode.app_rd_data_reg[236] ,\n \\rd_ptr_timing_reg[1]_0 ,\n \\not_strict_mode.app_rd_data_reg[239] ,\n \\not_strict_mode.app_rd_data_reg[8] ,\n \\not_strict_mode.app_rd_data_reg[9] ,\n \\not_strict_mode.app_rd_data_reg[10] ,\n \\not_strict_mode.app_rd_data_reg[11] ,\n \\not_strict_mode.app_rd_data_reg[12] ,\n \\not_strict_mode.app_rd_data_reg[13] ,\n \\not_strict_mode.app_rd_data_reg[14] ,\n \\not_strict_mode.app_rd_data_reg[15] ,\n \\not_strict_mode.app_rd_data_reg[40] ,\n \\not_strict_mode.app_rd_data_reg[41] ,\n \\not_strict_mode.app_rd_data_reg[42] ,\n \\not_strict_mode.app_rd_data_reg[43] ,\n \\not_strict_mode.app_rd_data_reg[44] ,\n \\not_strict_mode.app_rd_data_reg[45] ,\n \\not_strict_mode.app_rd_data_reg[46] ,\n \\not_strict_mode.app_rd_data_reg[47] ,\n \\not_strict_mode.app_rd_data_reg[72] ,\n \\not_strict_mode.app_rd_data_reg[73] ,\n \\not_strict_mode.app_rd_data_reg[74] ,\n \\not_strict_mode.app_rd_data_reg[75] ,\n \\not_strict_mode.app_rd_data_reg[76] ,\n \\not_strict_mode.app_rd_data_reg[77] ,\n \\not_strict_mode.app_rd_data_reg[78] ,\n \\not_strict_mode.app_rd_data_reg[79] ,\n \\not_strict_mode.app_rd_data_reg[104] ,\n \\not_strict_mode.app_rd_data_reg[105] ,\n \\not_strict_mode.app_rd_data_reg[106] ,\n \\not_strict_mode.app_rd_data_reg[107] ,\n \\not_strict_mode.app_rd_data_reg[108] ,\n \\not_strict_mode.app_rd_data_reg[109] ,\n \\not_strict_mode.app_rd_data_reg[110] ,\n \\not_strict_mode.app_rd_data_reg[111] ,\n \\not_strict_mode.app_rd_data_reg[136] ,\n \\not_strict_mode.app_rd_data_reg[137] ,\n \\not_strict_mode.app_rd_data_reg[138] ,\n \\not_strict_mode.app_rd_data_reg[139] ,\n \\not_strict_mode.app_rd_data_reg[140] ,\n \\not_strict_mode.app_rd_data_reg[141] ,\n \\not_strict_mode.app_rd_data_reg[142] ,\n \\not_strict_mode.app_rd_data_reg[143] ,\n \\not_strict_mode.app_rd_data_reg[168] ,\n \\not_strict_mode.app_rd_data_reg[169] ,\n \\not_strict_mode.app_rd_data_reg[170] ,\n \\not_strict_mode.app_rd_data_reg[171] ,\n \\not_strict_mode.app_rd_data_reg[172] ,\n \\not_strict_mode.app_rd_data_reg[173] ,\n \\not_strict_mode.app_rd_data_reg[174] ,\n \\not_strict_mode.app_rd_data_reg[175] ,\n \\not_strict_mode.app_rd_data_reg[200] ,\n \\not_strict_mode.app_rd_data_reg[201] ,\n \\not_strict_mode.app_rd_data_reg[202] ,\n \\not_strict_mode.app_rd_data_reg[203] ,\n \\not_strict_mode.app_rd_data_reg[204] ,\n \\not_strict_mode.app_rd_data_reg[205] ,\n \\not_strict_mode.app_rd_data_reg[206] ,\n \\not_strict_mode.app_rd_data_reg[207] ,\n \\not_strict_mode.app_rd_data_reg[232] ,\n \\not_strict_mode.app_rd_data_reg[233] ,\n \\not_strict_mode.app_rd_data_reg[234] ,\n \\not_strict_mode.app_rd_data_reg[235] ,\n \\not_strict_mode.app_rd_data_reg[236]_0 ,\n \\not_strict_mode.app_rd_data_reg[237] ,\n \\not_strict_mode.app_rd_data_reg[238] ,\n \\not_strict_mode.app_rd_data_reg[239]_0 ,\n \\not_strict_mode.app_rd_data_reg[15]_0 ,\n C_byte_rd_en,\n ififo_rst,\n CLK,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,\n \\read_fifo.fifo_out_data_r_reg[6] ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,\n Q,\n D_byte_rd_en,\n A_byte_rd_en,\n if_empty_r_0,\n \\my_empty_reg[4]_0 );\n output phy_if_empty_r_reg;\n output \\not_strict_mode.app_rd_data_reg[236] ;\n output [0:0]\\rd_ptr_timing_reg[1]_0 ;\n output [63:0]\\not_strict_mode.app_rd_data_reg[239] ;\n output \\not_strict_mode.app_rd_data_reg[8] ;\n output \\not_strict_mode.app_rd_data_reg[9] ;\n output \\not_strict_mode.app_rd_data_reg[10] ;\n output \\not_strict_mode.app_rd_data_reg[11] ;\n output \\not_strict_mode.app_rd_data_reg[12] ;\n output \\not_strict_mode.app_rd_data_reg[13] ;\n output \\not_strict_mode.app_rd_data_reg[14] ;\n output \\not_strict_mode.app_rd_data_reg[15] ;\n output \\not_strict_mode.app_rd_data_reg[40] ;\n output \\not_strict_mode.app_rd_data_reg[41] ;\n output \\not_strict_mode.app_rd_data_reg[42] ;\n output \\not_strict_mode.app_rd_data_reg[43] ;\n output \\not_strict_mode.app_rd_data_reg[44] ;\n output \\not_strict_mode.app_rd_data_reg[45] ;\n output \\not_strict_mode.app_rd_data_reg[46] ;\n output \\not_strict_mode.app_rd_data_reg[47] ;\n output \\not_strict_mode.app_rd_data_reg[72] ;\n output \\not_strict_mode.app_rd_data_reg[73] ;\n output \\not_strict_mode.app_rd_data_reg[74] ;\n output \\not_strict_mode.app_rd_data_reg[75] ;\n output \\not_strict_mode.app_rd_data_reg[76] ;\n output \\not_strict_mode.app_rd_data_reg[77] ;\n output \\not_strict_mode.app_rd_data_reg[78] ;\n output \\not_strict_mode.app_rd_data_reg[79] ;\n output \\not_strict_mode.app_rd_data_reg[104] ;\n output \\not_strict_mode.app_rd_data_reg[105] ;\n output \\not_strict_mode.app_rd_data_reg[106] ;\n output \\not_strict_mode.app_rd_data_reg[107] ;\n output \\not_strict_mode.app_rd_data_reg[108] ;\n output \\not_strict_mode.app_rd_data_reg[109] ;\n output \\not_strict_mode.app_rd_data_reg[110] ;\n output \\not_strict_mode.app_rd_data_reg[111] ;\n output \\not_strict_mode.app_rd_data_reg[136] ;\n output \\not_strict_mode.app_rd_data_reg[137] ;\n output \\not_strict_mode.app_rd_data_reg[138] ;\n output \\not_strict_mode.app_rd_data_reg[139] ;\n output \\not_strict_mode.app_rd_data_reg[140] ;\n output \\not_strict_mode.app_rd_data_reg[141] ;\n output \\not_strict_mode.app_rd_data_reg[142] ;\n output \\not_strict_mode.app_rd_data_reg[143] ;\n output \\not_strict_mode.app_rd_data_reg[168] ;\n output \\not_strict_mode.app_rd_data_reg[169] ;\n output \\not_strict_mode.app_rd_data_reg[170] ;\n output \\not_strict_mode.app_rd_data_reg[171] ;\n output \\not_strict_mode.app_rd_data_reg[172] ;\n output \\not_strict_mode.app_rd_data_reg[173] ;\n output \\not_strict_mode.app_rd_data_reg[174] ;\n output \\not_strict_mode.app_rd_data_reg[175] ;\n output \\not_strict_mode.app_rd_data_reg[200] ;\n output \\not_strict_mode.app_rd_data_reg[201] ;\n output \\not_strict_mode.app_rd_data_reg[202] ;\n output \\not_strict_mode.app_rd_data_reg[203] ;\n output \\not_strict_mode.app_rd_data_reg[204] ;\n output \\not_strict_mode.app_rd_data_reg[205] ;\n output \\not_strict_mode.app_rd_data_reg[206] ;\n output \\not_strict_mode.app_rd_data_reg[207] ;\n output \\not_strict_mode.app_rd_data_reg[232] ;\n output \\not_strict_mode.app_rd_data_reg[233] ;\n output \\not_strict_mode.app_rd_data_reg[234] ;\n output \\not_strict_mode.app_rd_data_reg[235] ;\n output \\not_strict_mode.app_rd_data_reg[236]_0 ;\n output \\not_strict_mode.app_rd_data_reg[237] ;\n output \\not_strict_mode.app_rd_data_reg[238] ;\n output \\not_strict_mode.app_rd_data_reg[239]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[15]_0 ;\n output C_byte_rd_en;\n input ififo_rst;\n input CLK;\n input \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n input \\read_fifo.fifo_out_data_r_reg[6] ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n input [65:0]Q;\n input D_byte_rd_en;\n input A_byte_rd_en;\n input [0:0]if_empty_r_0;\n input [0:0]\\my_empty_reg[4]_0 ;\n\n wire A_byte_rd_en;\n wire CLK;\n wire C_byte_rd_en;\n wire D_byte_rd_en;\n wire [65:0]Q;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n wire [0:0]if_empty_r_0;\n wire ififo_rst;\n wire [71:9]mem_out;\n wire mem_reg_0_3_6_11_n_0;\n wire mem_reg_0_3_6_11_n_1;\n wire [2:1]my_empty;\n wire \\my_empty[4]_i_1__0_n_0 ;\n wire \\my_empty[4]_i_2__1_n_0 ;\n wire [0:0]\\my_empty_reg[4]_0 ;\n wire \\my_empty_reg[4]_rep__0_n_0 ;\n wire \\my_empty_reg[4]_rep_n_0 ;\n wire [1:0]my_full;\n wire \\my_full[0]_i_1__1_n_0 ;\n wire \\my_full[0]_i_2__1_n_0 ;\n wire \\my_full[1]_i_1__1_n_0 ;\n wire \\my_full[1]_i_2__1_n_0 ;\n wire \\not_strict_mode.app_rd_data_reg[104] ;\n wire \\not_strict_mode.app_rd_data_reg[105] ;\n wire \\not_strict_mode.app_rd_data_reg[106] ;\n wire \\not_strict_mode.app_rd_data_reg[107] ;\n wire \\not_strict_mode.app_rd_data_reg[108] ;\n wire \\not_strict_mode.app_rd_data_reg[109] ;\n wire \\not_strict_mode.app_rd_data_reg[10] ;\n wire \\not_strict_mode.app_rd_data_reg[110] ;\n wire \\not_strict_mode.app_rd_data_reg[111] ;\n wire \\not_strict_mode.app_rd_data_reg[11] ;\n wire \\not_strict_mode.app_rd_data_reg[12] ;\n wire \\not_strict_mode.app_rd_data_reg[136] ;\n wire \\not_strict_mode.app_rd_data_reg[137] ;\n wire \\not_strict_mode.app_rd_data_reg[138] ;\n wire \\not_strict_mode.app_rd_data_reg[139] ;\n wire \\not_strict_mode.app_rd_data_reg[13] ;\n wire \\not_strict_mode.app_rd_data_reg[140] ;\n wire \\not_strict_mode.app_rd_data_reg[141] ;\n wire \\not_strict_mode.app_rd_data_reg[142] ;\n wire \\not_strict_mode.app_rd_data_reg[143] ;\n wire \\not_strict_mode.app_rd_data_reg[14] ;\n wire \\not_strict_mode.app_rd_data_reg[15] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[15]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[168] ;\n wire \\not_strict_mode.app_rd_data_reg[169] ;\n wire \\not_strict_mode.app_rd_data_reg[170] ;\n wire \\not_strict_mode.app_rd_data_reg[171] ;\n wire \\not_strict_mode.app_rd_data_reg[172] ;\n wire \\not_strict_mode.app_rd_data_reg[173] ;\n wire \\not_strict_mode.app_rd_data_reg[174] ;\n wire \\not_strict_mode.app_rd_data_reg[175] ;\n wire \\not_strict_mode.app_rd_data_reg[200] ;\n wire \\not_strict_mode.app_rd_data_reg[201] ;\n wire \\not_strict_mode.app_rd_data_reg[202] ;\n wire \\not_strict_mode.app_rd_data_reg[203] ;\n wire \\not_strict_mode.app_rd_data_reg[204] ;\n wire \\not_strict_mode.app_rd_data_reg[205] ;\n wire \\not_strict_mode.app_rd_data_reg[206] ;\n wire \\not_strict_mode.app_rd_data_reg[207] ;\n wire \\not_strict_mode.app_rd_data_reg[232] ;\n wire \\not_strict_mode.app_rd_data_reg[233] ;\n wire \\not_strict_mode.app_rd_data_reg[234] ;\n wire \\not_strict_mode.app_rd_data_reg[235] ;\n wire \\not_strict_mode.app_rd_data_reg[236] ;\n wire \\not_strict_mode.app_rd_data_reg[236]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[237] ;\n wire \\not_strict_mode.app_rd_data_reg[238] ;\n wire [63:0]\\not_strict_mode.app_rd_data_reg[239] ;\n wire \\not_strict_mode.app_rd_data_reg[239]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[40] ;\n wire \\not_strict_mode.app_rd_data_reg[41] ;\n wire \\not_strict_mode.app_rd_data_reg[42] ;\n wire \\not_strict_mode.app_rd_data_reg[43] ;\n wire \\not_strict_mode.app_rd_data_reg[44] ;\n wire \\not_strict_mode.app_rd_data_reg[45] ;\n wire \\not_strict_mode.app_rd_data_reg[46] ;\n wire \\not_strict_mode.app_rd_data_reg[47] ;\n wire \\not_strict_mode.app_rd_data_reg[72] ;\n wire \\not_strict_mode.app_rd_data_reg[73] ;\n wire \\not_strict_mode.app_rd_data_reg[74] ;\n wire \\not_strict_mode.app_rd_data_reg[75] ;\n wire \\not_strict_mode.app_rd_data_reg[76] ;\n wire \\not_strict_mode.app_rd_data_reg[77] ;\n wire \\not_strict_mode.app_rd_data_reg[78] ;\n wire \\not_strict_mode.app_rd_data_reg[79] ;\n wire \\not_strict_mode.app_rd_data_reg[8] ;\n wire \\not_strict_mode.app_rd_data_reg[9] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n wire \\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ;\n wire phy_if_empty_r_reg;\n wire [1:0]rd_ptr;\n wire \\rd_ptr[0]_i_1__1_n_0 ;\n wire \\rd_ptr[1]_i_1__1_n_0 ;\n (* RTL_KEEP = \"true\" *) (* syn_maxfan = \"10\" *) wire [1:0]rd_ptr_timing;\n wire \\rd_ptr_timing[0]_i_1__4_n_0 ;\n wire \\rd_ptr_timing[1]_i_1__6_n_0 ;\n wire [0:0]\\rd_ptr_timing_reg[1]_0 ;\n wire \\read_fifo.fifo_out_data_r_reg[6] ;\n (* MAX_FANOUT = \"40\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire wr_en;\n wire [1:0]wr_ptr;\n wire \\wr_ptr[0]_i_1__6_n_0 ;\n wire \\wr_ptr[1]_i_1__6_n_0 ;\n wire \\wr_ptr[1]_i_3__1_n_0 ;\n wire [1:0]NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED;\n\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_12_17\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[7:6]),\n .DIB(Q[9:8]),\n .DIC(Q[11:10]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[13:12]),\n .DOB(mem_out[15:14]),\n .DOC(mem_out[17:16]),\n .DOD(NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_18_23\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[13:12]),\n .DIB(Q[15:14]),\n .DIC(Q[17:16]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[19:18]),\n .DOB(mem_out[21:20]),\n .DOC(mem_out[23:22]),\n .DOD(NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_24_29\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[19:18]),\n .DIB(Q[21:20]),\n .DIC(Q[23:22]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[25:24]),\n .DOB(mem_out[27:26]),\n .DOC(mem_out[29:28]),\n .DOD(NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_30_35\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[25:24]),\n .DIB(Q[27:26]),\n .DIC(Q[29:28]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[31:30]),\n .DOB(mem_out[33:32]),\n .DOC(mem_out[35:34]),\n .DOD(NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_36_41\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[31:30]),\n .DIB(Q[33:32]),\n .DIC(Q[35:34]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[37:36]),\n .DOB(mem_out[39:38]),\n .DOC(mem_out[41:40]),\n .DOD(NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_42_47\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[37:36]),\n .DIB(Q[39:38]),\n .DIC(Q[41:40]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[43:42]),\n .DOB(mem_out[45:44]),\n .DOC(mem_out[47:46]),\n .DOD(NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_48_53\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[43:42]),\n .DIB(Q[45:44]),\n .DIC(Q[47:46]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[49:48]),\n .DOB(mem_out[51:50]),\n .DOC(mem_out[53:52]),\n .DOD(NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_54_59\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[49:48]),\n .DIB(Q[51:50]),\n .DIC(Q[53:52]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[55:54]),\n .DOB(mem_out[57:56]),\n .DOC(mem_out[59:58]),\n .DOD(NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_60_65\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[55:54]),\n .DIB(Q[57:56]),\n .DIC(Q[59:58]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[61:60]),\n .DOB(mem_out[63:62]),\n .DOC(mem_out[65:64]),\n .DOD(NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_66_71\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[61:60]),\n .DIB(Q[63:62]),\n .DIC(Q[65:64]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[67:66]),\n .DOB(mem_out[69:68]),\n .DOC(mem_out[71:70]),\n .DOD(NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_6_11\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[1:0]),\n .DIB(Q[3:2]),\n .DIC(Q[5:4]),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_3_6_11_n_0,mem_reg_0_3_6_11_n_1}),\n .DOB({mem_out[9],\\not_strict_mode.app_rd_data_reg[15]_0 }),\n .DOC(mem_out[11:10]),\n .DOD(NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n LUT4 #(\n .INIT(16'h0151)) \n mem_reg_0_3_6_11_i_1__0\n (.I0(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I1(my_full[0]),\n .I2(\\wr_ptr[1]_i_3__1_n_0 ),\n .I3(my_empty[2]),\n .O(wr_en));\n (* SOFT_HLUTNM = \"soft_lutpair871\" *) \n LUT1 #(\n .INIT(2'h2)) \n mem_reg_0_3_6_11_i_2__0\n (.I0(phy_if_empty_r_reg),\n .O(my_empty[2]));\n LUT4 #(\n .INIT(16'h0140)) \n \\my_empty[4]_i_1__0 \n (.I0(my_full[1]),\n .I1(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I2(\\wr_ptr[1]_i_3__1_n_0 ),\n .I3(my_empty[1]),\n .O(\\my_empty[4]_i_1__0_n_0 ));\n LUT5 #(\n .INIT(32'h00000960)) \n \\my_empty[4]_i_2__1 \n (.I0(wr_ptr[1]),\n .I1(rd_ptr[1]),\n .I2(rd_ptr[0]),\n .I3(wr_ptr[0]),\n .I4(my_empty[1]),\n .O(\\my_empty[4]_i_2__1_n_0 ));\n (* ORIG_CELL_NAME = \"my_empty_reg[4]\" *) \n FDSE \\my_empty_reg[4] \n (.C(CLK),\n .CE(\\my_empty[4]_i_1__0_n_0 ),\n .D(\\my_empty[4]_i_2__1_n_0 ),\n .Q(phy_if_empty_r_reg),\n .S(ififo_rst));\n (* ORIG_CELL_NAME = \"my_empty_reg[4]\" *) \n FDSE \\my_empty_reg[4]_rep \n (.C(CLK),\n .CE(\\my_empty[4]_i_1__0_n_0 ),\n .D(\\my_empty[4]_i_2__1_n_0 ),\n .Q(\\my_empty_reg[4]_rep_n_0 ),\n .S(ififo_rst));\n (* ORIG_CELL_NAME = \"my_empty_reg[4]\" *) \n FDSE \\my_empty_reg[4]_rep__0 \n (.C(CLK),\n .CE(\\my_empty[4]_i_1__0_n_0 ),\n .D(\\my_empty[4]_i_2__1_n_0 ),\n .Q(\\my_empty_reg[4]_rep__0_n_0 ),\n .S(ififo_rst));\n LUT6 #(\n .INIT(64'hBAAAAAAB8AAAAAA8)) \n \\my_full[0]_i_1__1 \n (.I0(my_full[0]),\n .I1(my_empty[1]),\n .I2(my_full[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I4(\\wr_ptr[1]_i_3__1_n_0 ),\n .I5(\\my_full[0]_i_2__1_n_0 ),\n .O(\\my_full[0]_i_1__1_n_0 ));\n LUT5 #(\n .INIT(32'h00000960)) \n \\my_full[0]_i_2__1 \n (.I0(rd_ptr[1]),\n .I1(wr_ptr[1]),\n .I2(wr_ptr[0]),\n .I3(rd_ptr[0]),\n .I4(my_full[1]),\n .O(\\my_full[0]_i_2__1_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAA00411400)) \n \\my_full[1]_i_1__1 \n (.I0(\\my_full[1]_i_2__1_n_0 ),\n .I1(rd_ptr[1]),\n .I2(wr_ptr[1]),\n .I3(wr_ptr[0]),\n .I4(rd_ptr[0]),\n .I5(my_full[1]),\n .O(\\my_full[1]_i_1__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair837\" *) \n LUT4 #(\n .INIT(16'hBFFE)) \n \\my_full[1]_i_2__1 \n (.I0(my_empty[1]),\n .I1(my_full[1]),\n .I2(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I3(\\wr_ptr[1]_i_3__1_n_0 ),\n .O(\\my_full[1]_i_2__1_n_0 ));\n FDRE \\my_full_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_full[0]_i_1__1_n_0 ),\n .Q(my_full[0]),\n .R(ififo_rst));\n FDRE \\my_full_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_full[1]_i_1__1_n_0 ),\n .Q(my_full[1]),\n .R(ififo_rst));\n (* SOFT_HLUTNM = \"soft_lutpair851\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[104]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[104] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [24]));\n (* SOFT_HLUTNM = \"soft_lutpair851\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[105]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[105] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [25]));\n (* SOFT_HLUTNM = \"soft_lutpair852\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[106]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[106] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [26]));\n (* SOFT_HLUTNM = \"soft_lutpair852\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[107]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[107] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [27]));\n (* SOFT_HLUTNM = \"soft_lutpair853\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[108]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[108] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [28]));\n (* SOFT_HLUTNM = \"soft_lutpair853\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[109]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[109] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [29]));\n (* SOFT_HLUTNM = \"soft_lutpair841\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[10]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[10] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [2]));\n (* SOFT_HLUTNM = \"soft_lutpair854\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[110]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[110] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [30]));\n (* SOFT_HLUTNM = \"soft_lutpair854\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[111]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[111] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [31]));\n (* SOFT_HLUTNM = \"soft_lutpair842\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[11]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[11] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [3]));\n (* SOFT_HLUTNM = \"soft_lutpair843\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[12]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[12] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [4]));\n (* SOFT_HLUTNM = \"soft_lutpair855\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[136]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[136] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [32]));\n (* SOFT_HLUTNM = \"soft_lutpair855\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[137]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[137] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [33]));\n (* SOFT_HLUTNM = \"soft_lutpair856\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[138]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[138] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [34]));\n (* SOFT_HLUTNM = \"soft_lutpair856\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[139]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[139] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [35]));\n (* SOFT_HLUTNM = \"soft_lutpair840\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[13]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[13] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [5]));\n (* SOFT_HLUTNM = \"soft_lutpair857\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[140]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[140] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [36]));\n (* SOFT_HLUTNM = \"soft_lutpair857\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[141]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[141] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [37]));\n (* SOFT_HLUTNM = \"soft_lutpair858\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[142]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[142] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [38]));\n (* SOFT_HLUTNM = \"soft_lutpair858\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[143]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[143] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [39]));\n (* SOFT_HLUTNM = \"soft_lutpair841\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[14]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[14] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [6]));\n (* SOFT_HLUTNM = \"soft_lutpair842\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[15]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[15] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [7]));\n (* SOFT_HLUTNM = \"soft_lutpair859\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[168]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[168] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [40]));\n (* SOFT_HLUTNM = \"soft_lutpair859\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[169]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[169] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [41]));\n (* SOFT_HLUTNM = \"soft_lutpair860\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[170]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[170] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [42]));\n (* SOFT_HLUTNM = \"soft_lutpair860\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[171]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[171] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [43]));\n (* SOFT_HLUTNM = \"soft_lutpair861\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[172]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[172] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [44]));\n (* SOFT_HLUTNM = \"soft_lutpair861\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[173]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[173] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [45]));\n (* SOFT_HLUTNM = \"soft_lutpair862\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[174]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[174] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [46]));\n (* SOFT_HLUTNM = \"soft_lutpair862\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[175]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[175] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [47]));\n (* SOFT_HLUTNM = \"soft_lutpair863\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[200]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[200] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [48]));\n (* SOFT_HLUTNM = \"soft_lutpair863\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[201]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[201] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [49]));\n (* SOFT_HLUTNM = \"soft_lutpair864\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[202]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[202] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [50]));\n (* SOFT_HLUTNM = \"soft_lutpair864\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[203]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[203] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [51]));\n (* SOFT_HLUTNM = \"soft_lutpair865\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[204]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[204] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [52]));\n (* SOFT_HLUTNM = \"soft_lutpair865\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[205]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[205] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [53]));\n (* SOFT_HLUTNM = \"soft_lutpair866\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[206]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[206] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [54]));\n (* SOFT_HLUTNM = \"soft_lutpair866\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[207]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[207] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [55]));\n (* SOFT_HLUTNM = \"soft_lutpair867\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[232]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[232] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [56]));\n (* SOFT_HLUTNM = \"soft_lutpair867\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[233]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[233] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [57]));\n (* SOFT_HLUTNM = \"soft_lutpair868\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[234]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[234] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [58]));\n (* SOFT_HLUTNM = \"soft_lutpair868\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[235]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[235] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [59]));\n (* SOFT_HLUTNM = \"soft_lutpair869\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[236]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[236]_0 ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [60]));\n (* SOFT_HLUTNM = \"soft_lutpair869\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[237]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[237] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [61]));\n (* SOFT_HLUTNM = \"soft_lutpair870\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[238]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[238] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [62]));\n (* SOFT_HLUTNM = \"soft_lutpair870\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[239]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[239]_0 ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [63]));\n (* SOFT_HLUTNM = \"soft_lutpair839\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[40]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[40] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [8]));\n (* SOFT_HLUTNM = \"soft_lutpair843\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[41]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[41] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [9]));\n (* SOFT_HLUTNM = \"soft_lutpair844\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[42]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[42] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [10]));\n (* SOFT_HLUTNM = \"soft_lutpair844\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[43]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[43] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [11]));\n (* SOFT_HLUTNM = \"soft_lutpair845\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[44]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[44] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [12]));\n (* SOFT_HLUTNM = \"soft_lutpair845\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[45]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[45] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [13]));\n (* SOFT_HLUTNM = \"soft_lutpair846\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[46]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[46] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [14]));\n (* SOFT_HLUTNM = \"soft_lutpair846\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[47]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[47] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [15]));\n (* SOFT_HLUTNM = \"soft_lutpair847\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[72]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[72] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [16]));\n (* SOFT_HLUTNM = \"soft_lutpair847\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[73]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[73] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [17]));\n (* SOFT_HLUTNM = \"soft_lutpair848\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[74]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[74] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [18]));\n (* SOFT_HLUTNM = \"soft_lutpair848\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[75]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[75] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [19]));\n (* SOFT_HLUTNM = \"soft_lutpair849\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[76]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[76] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [20]));\n (* SOFT_HLUTNM = \"soft_lutpair849\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[77]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[77] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [21]));\n (* SOFT_HLUTNM = \"soft_lutpair850\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[78]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[78] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [22]));\n (* SOFT_HLUTNM = \"soft_lutpair850\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[79]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[79] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [23]));\n (* SOFT_HLUTNM = \"soft_lutpair839\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[8]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[8] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [0]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [0]));\n (* SOFT_HLUTNM = \"soft_lutpair840\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[9]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[9] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [1]),\n .O(\\not_strict_mode.app_rd_data_reg[239] [1]));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_1 \n (.I0(Q[20]),\n .I1(mem_out[26]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[77] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_2 \n (.I0(Q[28]),\n .I1(mem_out[34]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[76] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_3 \n (.I0(Q[36]),\n .I1(mem_out[42]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[75] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_4 \n (.I0(Q[44]),\n .I1(mem_out[50]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[74] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_5 \n (.I0(Q[52]),\n .I1(mem_out[58]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[73] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_6 \n (.I0(Q[60]),\n .I1(mem_out[66]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[72] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_5 \n (.I0(Q[4]),\n .I1(mem_out[10]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[79] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_6 \n (.I0(Q[12]),\n .I1(mem_out[18]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[78] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_1 \n (.I0(Q[37]),\n .I1(mem_out[43]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[107] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_2 \n (.I0(Q[45]),\n .I1(mem_out[51]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[106] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_3 \n (.I0(Q[53]),\n .I1(mem_out[59]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[105] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_4 \n (.I0(Q[61]),\n .I1(mem_out[67]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[104] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_3 \n (.I0(Q[5]),\n .I1(mem_out[11]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[111] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_4 \n (.I0(Q[13]),\n .I1(mem_out[19]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[110] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_5 \n (.I0(Q[21]),\n .I1(mem_out[27]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[109] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_6 \n (.I0(Q[29]),\n .I1(mem_out[35]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[108] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_1 \n (.I0(Q[34]),\n .I1(mem_out[40]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[11] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_2 \n (.I0(Q[42]),\n .I1(mem_out[48]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[10] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_3 \n (.I0(Q[50]),\n .I1(mem_out[56]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[9] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_4 \n (.I0(Q[58]),\n .I1(mem_out[64]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[8] ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7 \n (.I0(\\my_empty_reg[4]_rep__0_n_0 ),\n .O(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_1 \n (.I0(Q[54]),\n .I1(mem_out[60]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[137] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_2 \n (.I0(Q[62]),\n .I1(mem_out[68]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[136] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_1 \n (.I0(Q[6]),\n .I1(mem_out[12]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[143] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_2 \n (.I0(Q[14]),\n .I1(mem_out[20]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[142] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_3 \n (.I0(Q[22]),\n .I1(mem_out[28]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[141] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_4 \n (.I0(Q[30]),\n .I1(mem_out[36]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[140] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_5 \n (.I0(Q[38]),\n .I1(mem_out[44]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[139] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_6 \n (.I0(Q[46]),\n .I1(mem_out[52]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[138] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_1 \n (.I0(Q[23]),\n .I1(mem_out[29]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[173] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_2 \n (.I0(Q[31]),\n .I1(mem_out[37]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[172] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_3 \n (.I0(Q[39]),\n .I1(mem_out[45]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[171] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_4 \n (.I0(Q[47]),\n .I1(mem_out[53]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[170] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_5 \n (.I0(Q[55]),\n .I1(mem_out[61]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[169] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_6 \n (.I0(Q[63]),\n .I1(mem_out[69]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[168] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_5 \n (.I0(Q[7]),\n .I1(mem_out[13]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[175] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_6 \n (.I0(Q[15]),\n .I1(mem_out[21]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[174] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_3 \n (.I0(Q[2]),\n .I1(\\not_strict_mode.app_rd_data_reg[15]_0 ),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[15] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_4 \n (.I0(Q[10]),\n .I1(mem_out[16]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[14] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_5 \n (.I0(Q[18]),\n .I1(mem_out[24]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[13] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_6 \n (.I0(Q[26]),\n .I1(mem_out[32]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[12] ));\n LUT1 #(\n .INIT(2'h2)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_8 \n (.I0(\\my_empty_reg[4]_rep_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[236] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_1 \n (.I0(Q[40]),\n .I1(mem_out[46]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[203] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_2 \n (.I0(Q[48]),\n .I1(mem_out[54]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[202] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_3 \n (.I0(Q[56]),\n .I1(mem_out[62]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[201] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_4 \n (.I0(Q[64]),\n .I1(mem_out[70]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[200] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_3 \n (.I0(Q[8]),\n .I1(mem_out[14]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[207] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_4 \n (.I0(Q[16]),\n .I1(mem_out[22]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[206] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_5 \n (.I0(Q[24]),\n .I1(mem_out[30]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[205] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_6 \n (.I0(Q[32]),\n .I1(mem_out[38]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[204] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_1 \n (.I0(Q[57]),\n .I1(mem_out[63]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[233] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_2 \n (.I0(Q[65]),\n .I1(mem_out[71]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[232] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_1 \n (.I0(Q[9]),\n .I1(mem_out[15]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[239]_0 ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_2 \n (.I0(Q[17]),\n .I1(mem_out[23]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[238] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_3 \n (.I0(Q[25]),\n .I1(mem_out[31]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[237] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_4 \n (.I0(Q[33]),\n .I1(mem_out[39]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[236]_0 ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_5 \n (.I0(Q[41]),\n .I1(mem_out[47]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[235] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_6 \n (.I0(Q[49]),\n .I1(mem_out[55]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[234] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_1 \n (.I0(Q[51]),\n .I1(mem_out[57]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[41] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_2 \n (.I0(Q[59]),\n .I1(mem_out[65]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[40] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_1 \n (.I0(Q[3]),\n .I1(mem_out[9]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[47] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_2 \n (.I0(Q[11]),\n .I1(mem_out[17]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[46] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_3 \n (.I0(Q[19]),\n .I1(mem_out[25]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[45] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_4 \n (.I0(Q[27]),\n .I1(mem_out[33]),\n .I2(\\not_strict_mode.app_rd_data_reg[236] ),\n .O(\\not_strict_mode.app_rd_data_reg[44] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_5 \n (.I0(Q[35]),\n .I1(mem_out[41]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[43] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_6 \n (.I0(Q[43]),\n .I1(mem_out[49]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[42] ));\n (* SOFT_HLUTNM = \"soft_lutpair838\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\rd_ptr[0]_i_1__1 \n (.I0(my_empty[1]),\n .I1(\\wr_ptr[1]_i_3__1_n_0 ),\n .I2(rd_ptr[0]),\n .O(\\rd_ptr[0]_i_1__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair838\" *) \n LUT4 #(\n .INIT(16'hDF20)) \n \\rd_ptr[1]_i_1__1 \n (.I0(rd_ptr[0]),\n .I1(my_empty[1]),\n .I2(\\wr_ptr[1]_i_3__1_n_0 ),\n .I3(rd_ptr[1]),\n .O(\\rd_ptr[1]_i_1__1_n_0 ));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_ptr[0]_i_1__1_n_0 ),\n .Q(rd_ptr[0]),\n .R(ififo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_ptr[1]_i_1__1_n_0 ),\n .Q(rd_ptr[1]),\n .R(ififo_rst));\n LUT4 #(\n .INIT(16'hA2AE)) \n \\rd_ptr_timing[0]_i_1__4 \n (.I0(rd_ptr_timing[0]),\n .I1(\\wr_ptr[1]_i_3__1_n_0 ),\n .I2(my_empty[1]),\n .I3(rd_ptr[0]),\n .O(\\rd_ptr_timing[0]_i_1__4_n_0 ));\n LUT5 #(\n .INIT(32'hF0F066F0)) \n \\rd_ptr_timing[1]_i_1__6 \n (.I0(rd_ptr[0]),\n .I1(rd_ptr[1]),\n .I2(rd_ptr_timing[1]),\n .I3(\\wr_ptr[1]_i_3__1_n_0 ),\n .I4(my_empty[1]),\n .O(\\rd_ptr_timing[1]_i_1__6_n_0 ));\n (* KEEP = \"yes\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_ptr_timing[0]_i_1__4_n_0 ),\n .Q(rd_ptr_timing[0]),\n .R(ififo_rst));\n (* KEEP = \"yes\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_ptr_timing[1]_i_1__6_n_0 ),\n .Q(rd_ptr_timing[1]),\n .R(ififo_rst));\n (* SOFT_HLUTNM = \"soft_lutpair837\" *) \n LUT5 #(\n .INIT(32'hEEFA1105)) \n \\wr_ptr[0]_i_1__6 \n (.I0(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I1(my_empty[1]),\n .I2(my_full[1]),\n .I3(\\wr_ptr[1]_i_3__1_n_0 ),\n .I4(wr_ptr[0]),\n .O(\\wr_ptr[0]_i_1__6_n_0 ));\n LUT6 #(\n .INIT(64'hFDFDFFDD02020022)) \n \\wr_ptr[1]_i_1__6 \n (.I0(wr_ptr[0]),\n .I1(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I2(my_empty[1]),\n .I3(my_full[1]),\n .I4(\\wr_ptr[1]_i_3__1_n_0 ),\n .I5(wr_ptr[1]),\n .O(\\wr_ptr[1]_i_1__6_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\wr_ptr[1]_i_2__1 \n (.I0(phy_if_empty_r_reg),\n .O(my_empty[1]));\n LUT6 #(\n .INIT(64'h0000700070007000)) \n \\wr_ptr[1]_i_3__1 \n (.I0(\\rd_ptr_timing_reg[1]_0 ),\n .I1(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I2(D_byte_rd_en),\n .I3(A_byte_rd_en),\n .I4(if_empty_r_0),\n .I5(\\my_empty_reg[4]_0 ),\n .O(\\wr_ptr[1]_i_3__1_n_0 ));\n LUT2 #(\n .INIT(4'h7)) \n \\wr_ptr[1]_i_5__0 \n (.I0(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I1(\\rd_ptr_timing_reg[1]_0 ),\n .O(C_byte_rd_en));\n (* SOFT_HLUTNM = \"soft_lutpair871\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\wr_ptr[1]_i_7 \n (.I0(phy_if_empty_r_reg),\n .O(\\rd_ptr_timing_reg[1]_0 ));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_ptr[0]_i_1__6_n_0 ),\n .Q(wr_ptr[0]),\n .R(ififo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_ptr[1]_i_1__6_n_0 ),\n .Q(wr_ptr[1]),\n .R(ififo_rst));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_if_post_fifo\" *) \nmodule ddr3_if_mig_7series_v4_0_ddr_if_post_fifo_7\n (\\not_strict_mode.app_rd_data_reg[244] ,\n \\rd_ptr_timing_reg[1]_0 ,\n rd_buf_we,\n \\not_strict_mode.status_ram.rd_buf_we_r1_reg ,\n phy_rddata_en,\n mux_rd_valid_r_reg,\n \\read_fifo.tail_r_reg[0] ,\n \\not_strict_mode.app_rd_data_reg[247] ,\n \\not_strict_mode.app_rd_data_reg[16] ,\n \\not_strict_mode.app_rd_data_reg[17] ,\n \\not_strict_mode.app_rd_data_reg[18] ,\n \\not_strict_mode.app_rd_data_reg[19] ,\n \\not_strict_mode.app_rd_data_reg[20] ,\n \\not_strict_mode.app_rd_data_reg[21] ,\n \\not_strict_mode.app_rd_data_reg[22] ,\n \\not_strict_mode.app_rd_data_reg[23] ,\n \\not_strict_mode.app_rd_data_reg[48] ,\n \\not_strict_mode.app_rd_data_reg[49] ,\n \\not_strict_mode.app_rd_data_reg[50] ,\n \\not_strict_mode.app_rd_data_reg[51] ,\n \\not_strict_mode.app_rd_data_reg[52] ,\n \\not_strict_mode.app_rd_data_reg[53] ,\n \\not_strict_mode.app_rd_data_reg[54] ,\n \\not_strict_mode.app_rd_data_reg[55] ,\n \\not_strict_mode.app_rd_data_reg[80] ,\n \\not_strict_mode.app_rd_data_reg[81] ,\n \\not_strict_mode.app_rd_data_reg[82] ,\n \\not_strict_mode.app_rd_data_reg[83] ,\n \\not_strict_mode.app_rd_data_reg[84] ,\n \\not_strict_mode.app_rd_data_reg[85] ,\n \\not_strict_mode.app_rd_data_reg[86] ,\n \\not_strict_mode.app_rd_data_reg[87] ,\n \\not_strict_mode.app_rd_data_reg[112] ,\n \\not_strict_mode.app_rd_data_reg[113] ,\n \\not_strict_mode.app_rd_data_reg[114] ,\n \\not_strict_mode.app_rd_data_reg[115] ,\n \\not_strict_mode.app_rd_data_reg[116] ,\n \\not_strict_mode.app_rd_data_reg[117] ,\n \\not_strict_mode.app_rd_data_reg[118] ,\n \\not_strict_mode.app_rd_data_reg[119] ,\n \\not_strict_mode.app_rd_data_reg[144] ,\n \\not_strict_mode.app_rd_data_reg[145] ,\n \\not_strict_mode.app_rd_data_reg[146] ,\n \\not_strict_mode.app_rd_data_reg[147] ,\n \\not_strict_mode.app_rd_data_reg[148] ,\n \\not_strict_mode.app_rd_data_reg[149] ,\n \\not_strict_mode.app_rd_data_reg[150] ,\n \\not_strict_mode.app_rd_data_reg[151] ,\n \\not_strict_mode.app_rd_data_reg[176] ,\n \\not_strict_mode.app_rd_data_reg[177] ,\n \\not_strict_mode.app_rd_data_reg[178] ,\n \\not_strict_mode.app_rd_data_reg[179] ,\n \\not_strict_mode.app_rd_data_reg[180] ,\n \\not_strict_mode.app_rd_data_reg[181] ,\n \\not_strict_mode.app_rd_data_reg[182] ,\n \\not_strict_mode.app_rd_data_reg[183] ,\n \\not_strict_mode.app_rd_data_reg[208] ,\n \\not_strict_mode.app_rd_data_reg[209] ,\n \\not_strict_mode.app_rd_data_reg[210] ,\n \\not_strict_mode.app_rd_data_reg[211] ,\n \\not_strict_mode.app_rd_data_reg[212] ,\n \\not_strict_mode.app_rd_data_reg[213] ,\n \\not_strict_mode.app_rd_data_reg[214] ,\n \\not_strict_mode.app_rd_data_reg[215] ,\n \\not_strict_mode.app_rd_data_reg[240] ,\n \\not_strict_mode.app_rd_data_reg[241] ,\n \\not_strict_mode.app_rd_data_reg[242] ,\n \\not_strict_mode.app_rd_data_reg[243] ,\n \\not_strict_mode.app_rd_data_reg[244]_0 ,\n \\not_strict_mode.app_rd_data_reg[245] ,\n \\not_strict_mode.app_rd_data_reg[246] ,\n \\not_strict_mode.app_rd_data_reg[247]_0 ,\n phy_if_empty_r_reg,\n \\not_strict_mode.app_rd_data_reg[23]_0 ,\n B_byte_rd_en,\n ififo_rst,\n CLK,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,\n \\read_fifo.fifo_out_data_r_reg[6] ,\n ram_init_done_r,\n if_empty_r_0,\n my_empty,\n \\my_empty_reg[4]_0 ,\n prbs_rdlvl_start_reg,\n out,\n tail_r,\n \\read_fifo.fifo_out_data_r_reg[6]_0 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,\n Q,\n D_byte_rd_en,\n A_byte_rd_en);\n output \\not_strict_mode.app_rd_data_reg[244] ;\n output [0:0]\\rd_ptr_timing_reg[1]_0 ;\n output rd_buf_we;\n output \\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n output phy_rddata_en;\n output mux_rd_valid_r_reg;\n output \\read_fifo.tail_r_reg[0] ;\n output [63:0]\\not_strict_mode.app_rd_data_reg[247] ;\n output \\not_strict_mode.app_rd_data_reg[16] ;\n output \\not_strict_mode.app_rd_data_reg[17] ;\n output \\not_strict_mode.app_rd_data_reg[18] ;\n output \\not_strict_mode.app_rd_data_reg[19] ;\n output \\not_strict_mode.app_rd_data_reg[20] ;\n output \\not_strict_mode.app_rd_data_reg[21] ;\n output \\not_strict_mode.app_rd_data_reg[22] ;\n output \\not_strict_mode.app_rd_data_reg[23] ;\n output \\not_strict_mode.app_rd_data_reg[48] ;\n output \\not_strict_mode.app_rd_data_reg[49] ;\n output \\not_strict_mode.app_rd_data_reg[50] ;\n output \\not_strict_mode.app_rd_data_reg[51] ;\n output \\not_strict_mode.app_rd_data_reg[52] ;\n output \\not_strict_mode.app_rd_data_reg[53] ;\n output \\not_strict_mode.app_rd_data_reg[54] ;\n output \\not_strict_mode.app_rd_data_reg[55] ;\n output \\not_strict_mode.app_rd_data_reg[80] ;\n output \\not_strict_mode.app_rd_data_reg[81] ;\n output \\not_strict_mode.app_rd_data_reg[82] ;\n output \\not_strict_mode.app_rd_data_reg[83] ;\n output \\not_strict_mode.app_rd_data_reg[84] ;\n output \\not_strict_mode.app_rd_data_reg[85] ;\n output \\not_strict_mode.app_rd_data_reg[86] ;\n output \\not_strict_mode.app_rd_data_reg[87] ;\n output \\not_strict_mode.app_rd_data_reg[112] ;\n output \\not_strict_mode.app_rd_data_reg[113] ;\n output \\not_strict_mode.app_rd_data_reg[114] ;\n output \\not_strict_mode.app_rd_data_reg[115] ;\n output \\not_strict_mode.app_rd_data_reg[116] ;\n output \\not_strict_mode.app_rd_data_reg[117] ;\n output \\not_strict_mode.app_rd_data_reg[118] ;\n output \\not_strict_mode.app_rd_data_reg[119] ;\n output \\not_strict_mode.app_rd_data_reg[144] ;\n output \\not_strict_mode.app_rd_data_reg[145] ;\n output \\not_strict_mode.app_rd_data_reg[146] ;\n output \\not_strict_mode.app_rd_data_reg[147] ;\n output \\not_strict_mode.app_rd_data_reg[148] ;\n output \\not_strict_mode.app_rd_data_reg[149] ;\n output \\not_strict_mode.app_rd_data_reg[150] ;\n output \\not_strict_mode.app_rd_data_reg[151] ;\n output \\not_strict_mode.app_rd_data_reg[176] ;\n output \\not_strict_mode.app_rd_data_reg[177] ;\n output \\not_strict_mode.app_rd_data_reg[178] ;\n output \\not_strict_mode.app_rd_data_reg[179] ;\n output \\not_strict_mode.app_rd_data_reg[180] ;\n output \\not_strict_mode.app_rd_data_reg[181] ;\n output \\not_strict_mode.app_rd_data_reg[182] ;\n output \\not_strict_mode.app_rd_data_reg[183] ;\n output \\not_strict_mode.app_rd_data_reg[208] ;\n output \\not_strict_mode.app_rd_data_reg[209] ;\n output \\not_strict_mode.app_rd_data_reg[210] ;\n output \\not_strict_mode.app_rd_data_reg[211] ;\n output \\not_strict_mode.app_rd_data_reg[212] ;\n output \\not_strict_mode.app_rd_data_reg[213] ;\n output \\not_strict_mode.app_rd_data_reg[214] ;\n output \\not_strict_mode.app_rd_data_reg[215] ;\n output \\not_strict_mode.app_rd_data_reg[240] ;\n output \\not_strict_mode.app_rd_data_reg[241] ;\n output \\not_strict_mode.app_rd_data_reg[242] ;\n output \\not_strict_mode.app_rd_data_reg[243] ;\n output \\not_strict_mode.app_rd_data_reg[244]_0 ;\n output \\not_strict_mode.app_rd_data_reg[245] ;\n output \\not_strict_mode.app_rd_data_reg[246] ;\n output \\not_strict_mode.app_rd_data_reg[247]_0 ;\n output phy_if_empty_r_reg;\n output [0:0]\\not_strict_mode.app_rd_data_reg[23]_0 ;\n output B_byte_rd_en;\n input ififo_rst;\n input CLK;\n input \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n input [0:0]\\read_fifo.fifo_out_data_r_reg[6] ;\n input ram_init_done_r;\n input [0:0]if_empty_r_0;\n input [1:0]my_empty;\n input \\my_empty_reg[4]_0 ;\n input prbs_rdlvl_start_reg;\n input out;\n input [0:0]tail_r;\n input \\read_fifo.fifo_out_data_r_reg[6]_0 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n input [65:0]Q;\n input D_byte_rd_en;\n input A_byte_rd_en;\n\n wire A_byte_rd_en;\n wire B_byte_rd_en;\n wire CLK;\n wire D_byte_rd_en;\n wire [65:0]Q;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n wire [0:0]if_empty_r_0;\n wire ififo_rst;\n wire [71:9]mem_out;\n wire mem_reg_0_3_6_11_n_0;\n wire mem_reg_0_3_6_11_n_1;\n wire mux_rd_valid_r_reg;\n wire [1:0]my_empty;\n wire \\my_empty[4]_i_1__1_n_0 ;\n wire \\my_empty[4]_i_2__0_n_0 ;\n wire [2:0]my_empty_0;\n wire \\my_empty_reg[4]_0 ;\n wire \\my_empty_reg[4]_rep__0_n_0 ;\n wire \\my_empty_reg[4]_rep_n_0 ;\n wire [1:0]my_full;\n wire \\my_full[0]_i_1__0_n_0 ;\n wire \\my_full[0]_i_2__0_n_0 ;\n wire \\my_full[1]_i_1__0_n_0 ;\n wire \\my_full[1]_i_2__0_n_0 ;\n wire \\not_strict_mode.app_rd_data_reg[112] ;\n wire \\not_strict_mode.app_rd_data_reg[113] ;\n wire \\not_strict_mode.app_rd_data_reg[114] ;\n wire \\not_strict_mode.app_rd_data_reg[115] ;\n wire \\not_strict_mode.app_rd_data_reg[116] ;\n wire \\not_strict_mode.app_rd_data_reg[117] ;\n wire \\not_strict_mode.app_rd_data_reg[118] ;\n wire \\not_strict_mode.app_rd_data_reg[119] ;\n wire \\not_strict_mode.app_rd_data_reg[144] ;\n wire \\not_strict_mode.app_rd_data_reg[145] ;\n wire \\not_strict_mode.app_rd_data_reg[146] ;\n wire \\not_strict_mode.app_rd_data_reg[147] ;\n wire \\not_strict_mode.app_rd_data_reg[148] ;\n wire \\not_strict_mode.app_rd_data_reg[149] ;\n wire \\not_strict_mode.app_rd_data_reg[150] ;\n wire \\not_strict_mode.app_rd_data_reg[151] ;\n wire \\not_strict_mode.app_rd_data_reg[16] ;\n wire \\not_strict_mode.app_rd_data_reg[176] ;\n wire \\not_strict_mode.app_rd_data_reg[177] ;\n wire \\not_strict_mode.app_rd_data_reg[178] ;\n wire \\not_strict_mode.app_rd_data_reg[179] ;\n wire \\not_strict_mode.app_rd_data_reg[17] ;\n wire \\not_strict_mode.app_rd_data_reg[180] ;\n wire \\not_strict_mode.app_rd_data_reg[181] ;\n wire \\not_strict_mode.app_rd_data_reg[182] ;\n wire \\not_strict_mode.app_rd_data_reg[183] ;\n wire \\not_strict_mode.app_rd_data_reg[18] ;\n wire \\not_strict_mode.app_rd_data_reg[19] ;\n wire \\not_strict_mode.app_rd_data_reg[208] ;\n wire \\not_strict_mode.app_rd_data_reg[209] ;\n wire \\not_strict_mode.app_rd_data_reg[20] ;\n wire \\not_strict_mode.app_rd_data_reg[210] ;\n wire \\not_strict_mode.app_rd_data_reg[211] ;\n wire \\not_strict_mode.app_rd_data_reg[212] ;\n wire \\not_strict_mode.app_rd_data_reg[213] ;\n wire \\not_strict_mode.app_rd_data_reg[214] ;\n wire \\not_strict_mode.app_rd_data_reg[215] ;\n wire \\not_strict_mode.app_rd_data_reg[21] ;\n wire \\not_strict_mode.app_rd_data_reg[22] ;\n wire \\not_strict_mode.app_rd_data_reg[23] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[23]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[240] ;\n wire \\not_strict_mode.app_rd_data_reg[241] ;\n wire \\not_strict_mode.app_rd_data_reg[242] ;\n wire \\not_strict_mode.app_rd_data_reg[243] ;\n wire \\not_strict_mode.app_rd_data_reg[244] ;\n wire \\not_strict_mode.app_rd_data_reg[244]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[245] ;\n wire \\not_strict_mode.app_rd_data_reg[246] ;\n wire [63:0]\\not_strict_mode.app_rd_data_reg[247] ;\n wire \\not_strict_mode.app_rd_data_reg[247]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[48] ;\n wire \\not_strict_mode.app_rd_data_reg[49] ;\n wire \\not_strict_mode.app_rd_data_reg[50] ;\n wire \\not_strict_mode.app_rd_data_reg[51] ;\n wire \\not_strict_mode.app_rd_data_reg[52] ;\n wire \\not_strict_mode.app_rd_data_reg[53] ;\n wire \\not_strict_mode.app_rd_data_reg[54] ;\n wire \\not_strict_mode.app_rd_data_reg[55] ;\n wire \\not_strict_mode.app_rd_data_reg[80] ;\n wire \\not_strict_mode.app_rd_data_reg[81] ;\n wire \\not_strict_mode.app_rd_data_reg[82] ;\n wire \\not_strict_mode.app_rd_data_reg[83] ;\n wire \\not_strict_mode.app_rd_data_reg[84] ;\n wire \\not_strict_mode.app_rd_data_reg[85] ;\n wire \\not_strict_mode.app_rd_data_reg[86] ;\n wire \\not_strict_mode.app_rd_data_reg[87] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n wire \\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ;\n wire \\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n wire out;\n wire phy_if_empty_r_reg;\n wire phy_rddata_en;\n wire prbs_rdlvl_start_reg;\n wire ram_init_done_r;\n wire rd_buf_we;\n wire [1:0]rd_ptr;\n wire \\rd_ptr[0]_i_1__0_n_0 ;\n wire \\rd_ptr[1]_i_1__0_n_0 ;\n (* RTL_KEEP = \"true\" *) (* syn_maxfan = \"10\" *) wire [1:0]rd_ptr_timing;\n wire \\rd_ptr_timing[0]_i_1__2_n_0 ;\n wire \\rd_ptr_timing[1]_i_1__5_n_0 ;\n wire [0:0]\\rd_ptr_timing_reg[1]_0 ;\n wire [0:0]\\read_fifo.fifo_out_data_r_reg[6] ;\n wire \\read_fifo.fifo_out_data_r_reg[6]_0 ;\n wire \\read_fifo.tail_r_reg[0] ;\n wire [0:0]tail_r;\n (* MAX_FANOUT = \"40\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire wr_en;\n wire [1:0]wr_ptr;\n wire \\wr_ptr[0]_i_1__4_n_0 ;\n wire \\wr_ptr[1]_i_1__4_n_0 ;\n wire \\wr_ptr[1]_i_3__0_n_0 ;\n wire [1:0]NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED;\n\n LUT6 #(\n .INIT(64'h0000077700000000)) \n i___114_i_2\n (.I0(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I1(my_empty_0[0]),\n .I2(if_empty_r_0),\n .I3(my_empty[0]),\n .I4(\\my_empty_reg[4]_0 ),\n .I5(out),\n .O(\\not_strict_mode.status_ram.rd_buf_we_r1_reg ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_12_17\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[7:6]),\n .DIB(Q[9:8]),\n .DIC(Q[11:10]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[13:12]),\n .DOB(mem_out[15:14]),\n .DOC(mem_out[17:16]),\n .DOD(NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_18_23\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[13:12]),\n .DIB(Q[15:14]),\n .DIC(Q[17:16]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[19:18]),\n .DOB(mem_out[21:20]),\n .DOC(mem_out[23:22]),\n .DOD(NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_24_29\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[19:18]),\n .DIB(Q[21:20]),\n .DIC(Q[23:22]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[25:24]),\n .DOB(mem_out[27:26]),\n .DOC(mem_out[29:28]),\n .DOD(NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_30_35\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[25:24]),\n .DIB(Q[27:26]),\n .DIC(Q[29:28]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[31:30]),\n .DOB(mem_out[33:32]),\n .DOC(mem_out[35:34]),\n .DOD(NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_36_41\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[31:30]),\n .DIB(Q[33:32]),\n .DIC(Q[35:34]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[37:36]),\n .DOB(mem_out[39:38]),\n .DOC(mem_out[41:40]),\n .DOD(NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_42_47\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[37:36]),\n .DIB(Q[39:38]),\n .DIC(Q[41:40]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[43:42]),\n .DOB(mem_out[45:44]),\n .DOC(mem_out[47:46]),\n .DOD(NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_48_53\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[43:42]),\n .DIB(Q[45:44]),\n .DIC(Q[47:46]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[49:48]),\n .DOB(mem_out[51:50]),\n .DOC(mem_out[53:52]),\n .DOD(NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_54_59\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[49:48]),\n .DIB(Q[51:50]),\n .DIC(Q[53:52]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[55:54]),\n .DOB(mem_out[57:56]),\n .DOC(mem_out[59:58]),\n .DOD(NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_60_65\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[55:54]),\n .DIB(Q[57:56]),\n .DIC(Q[59:58]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[61:60]),\n .DOB(mem_out[63:62]),\n .DOC(mem_out[65:64]),\n .DOD(NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_66_71\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[61:60]),\n .DIB(Q[63:62]),\n .DIC(Q[65:64]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[67:66]),\n .DOB(mem_out[69:68]),\n .DOC(mem_out[71:70]),\n .DOD(NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_6_11\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[1:0]),\n .DIB(Q[3:2]),\n .DIC(Q[5:4]),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_3_6_11_n_0,mem_reg_0_3_6_11_n_1}),\n .DOB({mem_out[9],\\not_strict_mode.app_rd_data_reg[23]_0 }),\n .DOC(mem_out[11:10]),\n .DOD(NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n LUT4 #(\n .INIT(16'h0151)) \n mem_reg_0_3_6_11_i_1\n (.I0(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I1(my_full[0]),\n .I2(\\wr_ptr[1]_i_3__0_n_0 ),\n .I3(my_empty_0[2]),\n .O(wr_en));\n (* SOFT_HLUTNM = \"soft_lutpair820\" *) \n LUT1 #(\n .INIT(2'h2)) \n mem_reg_0_3_6_11_i_2\n (.I0(my_empty_0[0]),\n .O(my_empty_0[2]));\n LUT6 #(\n .INIT(64'h0000077700000000)) \n mux_rd_valid_r_i_1\n (.I0(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I1(my_empty_0[0]),\n .I2(if_empty_r_0),\n .I3(my_empty[0]),\n .I4(\\my_empty_reg[4]_0 ),\n .I5(prbs_rdlvl_start_reg),\n .O(mux_rd_valid_r_reg));\n LUT4 #(\n .INIT(16'h0140)) \n \\my_empty[4]_i_1__1 \n (.I0(my_full[1]),\n .I1(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I2(\\wr_ptr[1]_i_3__0_n_0 ),\n .I3(my_empty_0[1]),\n .O(\\my_empty[4]_i_1__1_n_0 ));\n LUT5 #(\n .INIT(32'h00000960)) \n \\my_empty[4]_i_2__0 \n (.I0(wr_ptr[1]),\n .I1(rd_ptr[1]),\n .I2(rd_ptr[0]),\n .I3(wr_ptr[0]),\n .I4(my_empty_0[1]),\n .O(\\my_empty[4]_i_2__0_n_0 ));\n (* ORIG_CELL_NAME = \"my_empty_reg[4]\" *) \n FDSE \\my_empty_reg[4] \n (.C(CLK),\n .CE(\\my_empty[4]_i_1__1_n_0 ),\n .D(\\my_empty[4]_i_2__0_n_0 ),\n .Q(my_empty_0[0]),\n .S(ififo_rst));\n (* ORIG_CELL_NAME = \"my_empty_reg[4]\" *) \n FDSE \\my_empty_reg[4]_rep \n (.C(CLK),\n .CE(\\my_empty[4]_i_1__1_n_0 ),\n .D(\\my_empty[4]_i_2__0_n_0 ),\n .Q(\\my_empty_reg[4]_rep_n_0 ),\n .S(ififo_rst));\n (* ORIG_CELL_NAME = \"my_empty_reg[4]\" *) \n FDSE \\my_empty_reg[4]_rep__0 \n (.C(CLK),\n .CE(\\my_empty[4]_i_1__1_n_0 ),\n .D(\\my_empty[4]_i_2__0_n_0 ),\n .Q(\\my_empty_reg[4]_rep__0_n_0 ),\n .S(ififo_rst));\n LUT6 #(\n .INIT(64'hBAAAAAAB8AAAAAA8)) \n \\my_full[0]_i_1__0 \n (.I0(my_full[0]),\n .I1(my_empty_0[1]),\n .I2(my_full[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I4(\\wr_ptr[1]_i_3__0_n_0 ),\n .I5(\\my_full[0]_i_2__0_n_0 ),\n .O(\\my_full[0]_i_1__0_n_0 ));\n LUT5 #(\n .INIT(32'h00000960)) \n \\my_full[0]_i_2__0 \n (.I0(rd_ptr[1]),\n .I1(wr_ptr[1]),\n .I2(wr_ptr[0]),\n .I3(rd_ptr[0]),\n .I4(my_full[1]),\n .O(\\my_full[0]_i_2__0_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAA00411400)) \n \\my_full[1]_i_1__0 \n (.I0(\\my_full[1]_i_2__0_n_0 ),\n .I1(rd_ptr[1]),\n .I2(wr_ptr[1]),\n .I3(wr_ptr[0]),\n .I4(rd_ptr[0]),\n .I5(my_full[1]),\n .O(\\my_full[1]_i_1__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair786\" *) \n LUT4 #(\n .INIT(16'hBFFE)) \n \\my_full[1]_i_2__0 \n (.I0(my_empty_0[1]),\n .I1(my_full[1]),\n .I2(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I3(\\wr_ptr[1]_i_3__0_n_0 ),\n .O(\\my_full[1]_i_2__0_n_0 ));\n FDRE \\my_full_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_full[0]_i_1__0_n_0 ),\n .Q(my_full[0]),\n .R(ififo_rst));\n FDRE \\my_full_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_full[1]_i_1__0_n_0 ),\n .Q(my_full[1]),\n .R(ififo_rst));\n (* SOFT_HLUTNM = \"soft_lutpair800\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[112]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[112] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [24]));\n (* SOFT_HLUTNM = \"soft_lutpair800\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[113]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[113] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [25]));\n (* SOFT_HLUTNM = \"soft_lutpair801\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[114]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[114] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [26]));\n (* SOFT_HLUTNM = \"soft_lutpair801\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[115]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[115] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [27]));\n (* SOFT_HLUTNM = \"soft_lutpair802\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[116]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[116] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [28]));\n (* SOFT_HLUTNM = \"soft_lutpair802\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[117]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[117] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [29]));\n (* SOFT_HLUTNM = \"soft_lutpair803\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[118]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[118] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [30]));\n (* SOFT_HLUTNM = \"soft_lutpair803\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[119]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[119] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [31]));\n (* SOFT_HLUTNM = \"soft_lutpair804\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[144]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[144] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [32]));\n (* SOFT_HLUTNM = \"soft_lutpair804\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[145]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[145] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [33]));\n (* SOFT_HLUTNM = \"soft_lutpair805\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[146]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[146] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [34]));\n (* SOFT_HLUTNM = \"soft_lutpair805\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[147]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[147] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [35]));\n (* SOFT_HLUTNM = \"soft_lutpair806\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[148]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[148] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [36]));\n (* SOFT_HLUTNM = \"soft_lutpair807\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[149]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[149] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [37]));\n (* SOFT_HLUTNM = \"soft_lutpair806\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[150]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[150] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [38]));\n (* SOFT_HLUTNM = \"soft_lutpair807\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[151]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[151] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [39]));\n (* SOFT_HLUTNM = \"soft_lutpair788\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[16]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[16] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [0]));\n (* SOFT_HLUTNM = \"soft_lutpair808\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[176]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[176] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [40]));\n (* SOFT_HLUTNM = \"soft_lutpair808\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[177]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[177] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [41]));\n (* SOFT_HLUTNM = \"soft_lutpair809\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[178]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[178] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [42]));\n (* SOFT_HLUTNM = \"soft_lutpair809\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[179]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[179] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [43]));\n (* SOFT_HLUTNM = \"soft_lutpair789\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[17]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[17] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [1]));\n (* SOFT_HLUTNM = \"soft_lutpair810\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[180]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[180] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [44]));\n (* SOFT_HLUTNM = \"soft_lutpair810\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[181]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[181] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [45]));\n (* SOFT_HLUTNM = \"soft_lutpair811\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[182]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[182] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [46]));\n (* SOFT_HLUTNM = \"soft_lutpair811\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[183]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[183] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [47]));\n (* SOFT_HLUTNM = \"soft_lutpair790\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[18]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[18] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [2]));\n (* SOFT_HLUTNM = \"soft_lutpair791\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[19]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[19] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [3]));\n (* SOFT_HLUTNM = \"soft_lutpair812\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[208]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[208] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [48]));\n (* SOFT_HLUTNM = \"soft_lutpair812\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[209]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[209] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [49]));\n (* SOFT_HLUTNM = \"soft_lutpair792\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[20]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[20] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [4]));\n (* SOFT_HLUTNM = \"soft_lutpair813\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[210]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[210] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [50]));\n (* SOFT_HLUTNM = \"soft_lutpair813\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[211]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[211] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [51]));\n (* SOFT_HLUTNM = \"soft_lutpair814\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[212]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[212] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [52]));\n (* SOFT_HLUTNM = \"soft_lutpair814\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[213]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[213] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [53]));\n (* SOFT_HLUTNM = \"soft_lutpair815\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[214]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[214] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [54]));\n (* SOFT_HLUTNM = \"soft_lutpair815\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[215]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[215] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [55]));\n (* SOFT_HLUTNM = \"soft_lutpair793\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[21]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[21] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [5]));\n (* SOFT_HLUTNM = \"soft_lutpair794\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[22]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[22] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [6]));\n (* SOFT_HLUTNM = \"soft_lutpair795\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[23]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[23] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [7]));\n (* SOFT_HLUTNM = \"soft_lutpair816\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[240]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[240] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [56]));\n (* SOFT_HLUTNM = \"soft_lutpair816\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[241]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[241] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [57]));\n (* SOFT_HLUTNM = \"soft_lutpair817\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[242]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[242] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [58]));\n (* SOFT_HLUTNM = \"soft_lutpair817\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[243]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[243] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [59]));\n (* SOFT_HLUTNM = \"soft_lutpair818\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[244]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[244]_0 ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [60]));\n (* SOFT_HLUTNM = \"soft_lutpair818\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[245]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[245] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [61]));\n (* SOFT_HLUTNM = \"soft_lutpair819\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[246]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[246] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [62]));\n (* SOFT_HLUTNM = \"soft_lutpair819\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[247]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[247]_0 ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [63]));\n (* SOFT_HLUTNM = \"soft_lutpair788\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[48]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[48] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [8]));\n (* SOFT_HLUTNM = \"soft_lutpair789\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[49]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[49] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [9]));\n (* SOFT_HLUTNM = \"soft_lutpair790\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[50]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[50] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [10]));\n (* SOFT_HLUTNM = \"soft_lutpair791\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[51]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[51] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [11]));\n (* SOFT_HLUTNM = \"soft_lutpair792\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[52]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[52] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [12]));\n (* SOFT_HLUTNM = \"soft_lutpair793\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[53]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[53] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [13]));\n (* SOFT_HLUTNM = \"soft_lutpair794\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[54]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[54] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [14]));\n (* SOFT_HLUTNM = \"soft_lutpair795\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[55]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[55] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [15]));\n (* SOFT_HLUTNM = \"soft_lutpair796\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[80]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[80] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [16]));\n (* SOFT_HLUTNM = \"soft_lutpair796\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[81]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[81] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [17]));\n (* SOFT_HLUTNM = \"soft_lutpair797\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[82]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[82] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [18]));\n (* SOFT_HLUTNM = \"soft_lutpair797\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[83]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[83] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [19]));\n (* SOFT_HLUTNM = \"soft_lutpair798\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[84]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[84] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [20]));\n (* SOFT_HLUTNM = \"soft_lutpair798\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[85]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[85] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [21]));\n (* SOFT_HLUTNM = \"soft_lutpair799\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[86]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[86] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [22]));\n (* SOFT_HLUTNM = \"soft_lutpair799\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[87]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[87] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[247] [23]));\n LUT3 #(\n .INIT(8'h2F)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_1 \n (.I0(\\not_strict_mode.status_ram.rd_buf_we_r1_reg ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(ram_init_done_r),\n .O(rd_buf_we));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_1 \n (.I0(Q[36]),\n .I1(mem_out[42]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[83] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_2 \n (.I0(Q[44]),\n .I1(mem_out[50]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[82] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_3 \n (.I0(Q[52]),\n .I1(mem_out[58]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[81] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_4 \n (.I0(Q[60]),\n .I1(mem_out[66]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[80] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_3 \n (.I0(Q[4]),\n .I1(mem_out[10]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[87] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_4 \n (.I0(Q[12]),\n .I1(mem_out[18]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[86] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_5 \n (.I0(Q[20]),\n .I1(mem_out[26]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[85] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_6 \n (.I0(Q[28]),\n .I1(mem_out[34]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[84] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_1 \n (.I0(Q[53]),\n .I1(mem_out[59]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[113] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_2 \n (.I0(Q[61]),\n .I1(mem_out[67]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[112] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_1 \n (.I0(Q[5]),\n .I1(mem_out[11]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[119] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_2 \n (.I0(Q[13]),\n .I1(mem_out[19]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[118] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_3 \n (.I0(Q[21]),\n .I1(mem_out[27]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[117] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_4 \n (.I0(Q[29]),\n .I1(mem_out[35]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[116] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_5 \n (.I0(Q[37]),\n .I1(mem_out[43]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[115] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_6 \n (.I0(Q[45]),\n .I1(mem_out[51]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[114] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_1 \n (.I0(Q[22]),\n .I1(mem_out[28]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[149] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_2 \n (.I0(Q[30]),\n .I1(mem_out[36]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[148] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_3 \n (.I0(Q[38]),\n .I1(mem_out[44]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[147] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_4 \n (.I0(Q[46]),\n .I1(mem_out[52]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[146] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_5 \n (.I0(Q[54]),\n .I1(mem_out[60]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[145] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_6 \n (.I0(Q[62]),\n .I1(mem_out[68]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[144] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_5 \n (.I0(Q[6]),\n .I1(mem_out[12]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[151] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_6 \n (.I0(Q[14]),\n .I1(mem_out[20]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[150] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_1 \n (.I0(Q[39]),\n .I1(mem_out[45]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[179] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_2 \n (.I0(Q[47]),\n .I1(mem_out[53]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[178] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_3 \n (.I0(Q[55]),\n .I1(mem_out[61]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[177] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_4 \n (.I0(Q[63]),\n .I1(mem_out[69]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[176] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_1 \n (.I0(Q[50]),\n .I1(mem_out[56]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[17] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_2 \n (.I0(Q[58]),\n .I1(mem_out[64]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[16] ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7 \n (.I0(\\my_empty_reg[4]_rep__0_n_0 ),\n .O(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_3 \n (.I0(Q[7]),\n .I1(mem_out[13]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[183] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_4 \n (.I0(Q[15]),\n .I1(mem_out[21]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[182] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_5 \n (.I0(Q[23]),\n .I1(mem_out[29]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[181] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_6 \n (.I0(Q[31]),\n .I1(mem_out[37]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[180] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_1 \n (.I0(Q[56]),\n .I1(mem_out[62]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[209] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_2 \n (.I0(Q[64]),\n .I1(mem_out[70]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[208] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_1 \n (.I0(Q[8]),\n .I1(mem_out[14]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[215] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_2 \n (.I0(Q[16]),\n .I1(mem_out[22]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[214] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_3 \n (.I0(Q[24]),\n .I1(mem_out[30]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[213] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_4 \n (.I0(Q[32]),\n .I1(mem_out[38]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[212] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_5 \n (.I0(Q[40]),\n .I1(mem_out[46]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[211] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_6 \n (.I0(Q[48]),\n .I1(mem_out[54]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[210] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_1 \n (.I0(Q[2]),\n .I1(\\not_strict_mode.app_rd_data_reg[23]_0 ),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[23] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_2 \n (.I0(Q[10]),\n .I1(mem_out[16]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[22] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_3 \n (.I0(Q[18]),\n .I1(mem_out[24]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[21] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_4 \n (.I0(Q[26]),\n .I1(mem_out[32]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[20] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_5 \n (.I0(Q[34]),\n .I1(mem_out[40]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[19] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_6 \n (.I0(Q[42]),\n .I1(mem_out[48]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[18] ));\n LUT1 #(\n .INIT(2'h2)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_7 \n (.I0(\\my_empty_reg[4]_rep_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[244] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_1 \n (.I0(Q[25]),\n .I1(mem_out[31]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[245] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_2 \n (.I0(Q[33]),\n .I1(mem_out[39]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[244]_0 ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_3 \n (.I0(Q[41]),\n .I1(mem_out[47]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[243] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_4 \n (.I0(Q[49]),\n .I1(mem_out[55]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[242] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_5 \n (.I0(Q[57]),\n .I1(mem_out[63]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[241] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_6 \n (.I0(Q[65]),\n .I1(mem_out[71]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[240] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_5 \n (.I0(Q[9]),\n .I1(mem_out[15]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[247]_0 ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_6 \n (.I0(Q[17]),\n .I1(mem_out[23]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[246] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_1 \n (.I0(Q[19]),\n .I1(mem_out[25]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[53] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_2 \n (.I0(Q[27]),\n .I1(mem_out[33]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[52] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_3 \n (.I0(Q[35]),\n .I1(mem_out[41]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[51] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_4 \n (.I0(Q[43]),\n .I1(mem_out[49]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[50] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_5 \n (.I0(Q[51]),\n .I1(mem_out[57]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[49] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_6 \n (.I0(Q[59]),\n .I1(mem_out[65]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_7_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[48] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_5 \n (.I0(Q[3]),\n .I1(mem_out[9]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[55] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_6 \n (.I0(Q[11]),\n .I1(mem_out[17]),\n .I2(\\not_strict_mode.app_rd_data_reg[244] ),\n .O(\\not_strict_mode.app_rd_data_reg[54] ));\n (* SOFT_HLUTNM = \"soft_lutpair785\" *) \n LUT5 #(\n .INIT(32'hFFFFF888)) \n phy_if_empty_r_i_1\n (.I0(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I1(my_empty_0[0]),\n .I2(if_empty_r_0),\n .I3(my_empty[0]),\n .I4(\\my_empty_reg[4]_0 ),\n .O(phy_if_empty_r_reg));\n (* SOFT_HLUTNM = \"soft_lutpair785\" *) \n LUT5 #(\n .INIT(32'h00000777)) \n phy_rddata_en_r1_i_1\n (.I0(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I1(my_empty_0[0]),\n .I2(if_empty_r_0),\n .I3(my_empty[0]),\n .I4(\\my_empty_reg[4]_0 ),\n .O(phy_rddata_en));\n (* SOFT_HLUTNM = \"soft_lutpair787\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\rd_ptr[0]_i_1__0 \n (.I0(my_empty_0[1]),\n .I1(\\wr_ptr[1]_i_3__0_n_0 ),\n .I2(rd_ptr[0]),\n .O(\\rd_ptr[0]_i_1__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair787\" *) \n LUT4 #(\n .INIT(16'hDF20)) \n \\rd_ptr[1]_i_1__0 \n (.I0(rd_ptr[0]),\n .I1(my_empty_0[1]),\n .I2(\\wr_ptr[1]_i_3__0_n_0 ),\n .I3(rd_ptr[1]),\n .O(\\rd_ptr[1]_i_1__0_n_0 ));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_ptr[0]_i_1__0_n_0 ),\n .Q(rd_ptr[0]),\n .R(ififo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_ptr[1]_i_1__0_n_0 ),\n .Q(rd_ptr[1]),\n .R(ififo_rst));\n LUT4 #(\n .INIT(16'hA2AE)) \n \\rd_ptr_timing[0]_i_1__2 \n (.I0(rd_ptr_timing[0]),\n .I1(\\wr_ptr[1]_i_3__0_n_0 ),\n .I2(my_empty_0[1]),\n .I3(rd_ptr[0]),\n .O(\\rd_ptr_timing[0]_i_1__2_n_0 ));\n LUT5 #(\n .INIT(32'hF0F066F0)) \n \\rd_ptr_timing[1]_i_1__5 \n (.I0(rd_ptr[0]),\n .I1(rd_ptr[1]),\n .I2(rd_ptr_timing[1]),\n .I3(\\wr_ptr[1]_i_3__0_n_0 ),\n .I4(my_empty_0[1]),\n .O(\\rd_ptr_timing[1]_i_1__5_n_0 ));\n (* KEEP = \"yes\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_ptr_timing[0]_i_1__2_n_0 ),\n .Q(rd_ptr_timing[0]),\n .R(ififo_rst));\n (* KEEP = \"yes\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_ptr_timing[1]_i_1__5_n_0 ),\n .Q(rd_ptr_timing[1]),\n .R(ififo_rst));\n LUT2 #(\n .INIT(4'h6)) \n \\read_fifo.tail_r[0]_i_1 \n (.I0(\\not_strict_mode.status_ram.rd_buf_we_r1_reg ),\n .I1(tail_r),\n .O(\\read_fifo.tail_r_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair786\" *) \n LUT5 #(\n .INIT(32'hEEFA1105)) \n \\wr_ptr[0]_i_1__4 \n (.I0(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I1(my_empty_0[1]),\n .I2(my_full[1]),\n .I3(\\wr_ptr[1]_i_3__0_n_0 ),\n .I4(wr_ptr[0]),\n .O(\\wr_ptr[0]_i_1__4_n_0 ));\n LUT6 #(\n .INIT(64'hFDFDFFDD02020022)) \n \\wr_ptr[1]_i_1__4 \n (.I0(wr_ptr[0]),\n .I1(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I2(my_empty_0[1]),\n .I3(my_full[1]),\n .I4(\\wr_ptr[1]_i_3__0_n_0 ),\n .I5(wr_ptr[1]),\n .O(\\wr_ptr[1]_i_1__4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\wr_ptr[1]_i_2__0 \n (.I0(my_empty_0[0]),\n .O(my_empty_0[1]));\n LUT6 #(\n .INIT(64'h0000700070007000)) \n \\wr_ptr[1]_i_3__0 \n (.I0(\\rd_ptr_timing_reg[1]_0 ),\n .I1(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I2(D_byte_rd_en),\n .I3(A_byte_rd_en),\n .I4(if_empty_r_0),\n .I5(my_empty[1]),\n .O(\\wr_ptr[1]_i_3__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair820\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\wr_ptr[1]_i_4__0 \n (.I0(my_empty_0[0]),\n .O(\\rd_ptr_timing_reg[1]_0 ));\n LUT2 #(\n .INIT(4'h7)) \n \\wr_ptr[1]_i_6 \n (.I0(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I1(\\rd_ptr_timing_reg[1]_0 ),\n .O(B_byte_rd_en));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_ptr[0]_i_1__4_n_0 ),\n .Q(wr_ptr[0]),\n .R(ififo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_ptr[1]_i_1__4_n_0 ),\n .Q(wr_ptr[1]),\n .R(ififo_rst));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_if_post_fifo\" *) \nmodule ddr3_if_mig_7series_v4_0_ddr_if_post_fifo_8\n (\\wr_ptr_reg[1]_0 ,\n \\not_strict_mode.app_rd_data_reg[252] ,\n \\data_bytes_r_reg[63] ,\n \\not_strict_mode.app_rd_data_reg[255] ,\n \\not_strict_mode.app_rd_data_reg[254] ,\n \\not_strict_mode.app_rd_data_reg[253] ,\n \\not_strict_mode.app_rd_data_reg[252]_0 ,\n \\not_strict_mode.app_rd_data_reg[251] ,\n \\not_strict_mode.app_rd_data_reg[250] ,\n \\not_strict_mode.app_rd_data_reg[249] ,\n \\not_strict_mode.app_rd_data_reg[248] ,\n \\not_strict_mode.app_rd_data_reg[223] ,\n \\not_strict_mode.app_rd_data_reg[222] ,\n \\not_strict_mode.app_rd_data_reg[221] ,\n \\not_strict_mode.app_rd_data_reg[220] ,\n \\not_strict_mode.app_rd_data_reg[219] ,\n \\not_strict_mode.app_rd_data_reg[218] ,\n \\not_strict_mode.app_rd_data_reg[217] ,\n \\not_strict_mode.app_rd_data_reg[216] ,\n \\not_strict_mode.app_rd_data_reg[191] ,\n \\not_strict_mode.app_rd_data_reg[190] ,\n \\not_strict_mode.app_rd_data_reg[189] ,\n \\not_strict_mode.app_rd_data_reg[188] ,\n \\not_strict_mode.app_rd_data_reg[187] ,\n \\not_strict_mode.app_rd_data_reg[186] ,\n \\not_strict_mode.app_rd_data_reg[185] ,\n \\not_strict_mode.app_rd_data_reg[184] ,\n \\not_strict_mode.app_rd_data_reg[159] ,\n \\not_strict_mode.app_rd_data_reg[158] ,\n \\not_strict_mode.app_rd_data_reg[157] ,\n \\not_strict_mode.app_rd_data_reg[156] ,\n \\not_strict_mode.app_rd_data_reg[155] ,\n \\not_strict_mode.app_rd_data_reg[154] ,\n \\not_strict_mode.app_rd_data_reg[153] ,\n \\not_strict_mode.app_rd_data_reg[152] ,\n \\not_strict_mode.app_rd_data_reg[127] ,\n \\not_strict_mode.app_rd_data_reg[126] ,\n \\not_strict_mode.app_rd_data_reg[125] ,\n \\not_strict_mode.app_rd_data_reg[124] ,\n \\not_strict_mode.app_rd_data_reg[123] ,\n \\not_strict_mode.app_rd_data_reg[122] ,\n \\not_strict_mode.app_rd_data_reg[121] ,\n \\not_strict_mode.app_rd_data_reg[120] ,\n \\not_strict_mode.app_rd_data_reg[95] ,\n \\not_strict_mode.app_rd_data_reg[94] ,\n \\not_strict_mode.app_rd_data_reg[93] ,\n \\not_strict_mode.app_rd_data_reg[92] ,\n \\not_strict_mode.app_rd_data_reg[91] ,\n \\not_strict_mode.app_rd_data_reg[90] ,\n \\not_strict_mode.app_rd_data_reg[89] ,\n \\not_strict_mode.app_rd_data_reg[88] ,\n \\not_strict_mode.app_rd_data_reg[63] ,\n \\not_strict_mode.app_rd_data_reg[62] ,\n \\not_strict_mode.app_rd_data_reg[61] ,\n \\not_strict_mode.app_rd_data_reg[60] ,\n \\not_strict_mode.app_rd_data_reg[59] ,\n \\not_strict_mode.app_rd_data_reg[58] ,\n \\not_strict_mode.app_rd_data_reg[57] ,\n \\not_strict_mode.app_rd_data_reg[56] ,\n \\not_strict_mode.app_rd_data_reg[31] ,\n \\not_strict_mode.app_rd_data_reg[30] ,\n \\not_strict_mode.app_rd_data_reg[29] ,\n \\not_strict_mode.app_rd_data_reg[28] ,\n \\not_strict_mode.app_rd_data_reg[27] ,\n \\not_strict_mode.app_rd_data_reg[26] ,\n \\not_strict_mode.app_rd_data_reg[25] ,\n \\not_strict_mode.app_rd_data_reg[24] ,\n \\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,\n \\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,\n \\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,\n \\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,\n \\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,\n \\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,\n \\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,\n \\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,\n \\not_strict_mode.app_rd_data_reg[255]_0 ,\n \\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ,\n \\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ,\n \\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ,\n \\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ,\n \\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ,\n \\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ,\n \\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ,\n \\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ,\n \\not_strict_mode.app_rd_data_reg[31]_0 ,\n A_byte_rd_en,\n p_0_out,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,\n \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,\n \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,\n \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,\n \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,\n ififo_rst,\n CLK,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ,\n \\byte_r_reg[0] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ,\n \\byte_r_reg[1] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ,\n \\rd_mux_sel_r_reg[1] ,\n \\read_fifo.fifo_out_data_r_reg[6] ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,\n A,\n Q,\n D_byte_rd_en,\n B_byte_rd_en,\n if_empty_r_0,\n my_empty,\n \\po_stg2_wrcal_cnt_reg[1] );\n output \\wr_ptr_reg[1]_0 ;\n output \\not_strict_mode.app_rd_data_reg[252] ;\n output [63:0]\\data_bytes_r_reg[63] ;\n output \\not_strict_mode.app_rd_data_reg[255] ;\n output \\not_strict_mode.app_rd_data_reg[254] ;\n output \\not_strict_mode.app_rd_data_reg[253] ;\n output \\not_strict_mode.app_rd_data_reg[252]_0 ;\n output \\not_strict_mode.app_rd_data_reg[251] ;\n output \\not_strict_mode.app_rd_data_reg[250] ;\n output \\not_strict_mode.app_rd_data_reg[249] ;\n output \\not_strict_mode.app_rd_data_reg[248] ;\n output \\not_strict_mode.app_rd_data_reg[223] ;\n output \\not_strict_mode.app_rd_data_reg[222] ;\n output \\not_strict_mode.app_rd_data_reg[221] ;\n output \\not_strict_mode.app_rd_data_reg[220] ;\n output \\not_strict_mode.app_rd_data_reg[219] ;\n output \\not_strict_mode.app_rd_data_reg[218] ;\n output \\not_strict_mode.app_rd_data_reg[217] ;\n output \\not_strict_mode.app_rd_data_reg[216] ;\n output \\not_strict_mode.app_rd_data_reg[191] ;\n output \\not_strict_mode.app_rd_data_reg[190] ;\n output \\not_strict_mode.app_rd_data_reg[189] ;\n output \\not_strict_mode.app_rd_data_reg[188] ;\n output \\not_strict_mode.app_rd_data_reg[187] ;\n output \\not_strict_mode.app_rd_data_reg[186] ;\n output \\not_strict_mode.app_rd_data_reg[185] ;\n output \\not_strict_mode.app_rd_data_reg[184] ;\n output \\not_strict_mode.app_rd_data_reg[159] ;\n output \\not_strict_mode.app_rd_data_reg[158] ;\n output \\not_strict_mode.app_rd_data_reg[157] ;\n output \\not_strict_mode.app_rd_data_reg[156] ;\n output \\not_strict_mode.app_rd_data_reg[155] ;\n output \\not_strict_mode.app_rd_data_reg[154] ;\n output \\not_strict_mode.app_rd_data_reg[153] ;\n output \\not_strict_mode.app_rd_data_reg[152] ;\n output \\not_strict_mode.app_rd_data_reg[127] ;\n output \\not_strict_mode.app_rd_data_reg[126] ;\n output \\not_strict_mode.app_rd_data_reg[125] ;\n output \\not_strict_mode.app_rd_data_reg[124] ;\n output \\not_strict_mode.app_rd_data_reg[123] ;\n output \\not_strict_mode.app_rd_data_reg[122] ;\n output \\not_strict_mode.app_rd_data_reg[121] ;\n output \\not_strict_mode.app_rd_data_reg[120] ;\n output \\not_strict_mode.app_rd_data_reg[95] ;\n output \\not_strict_mode.app_rd_data_reg[94] ;\n output \\not_strict_mode.app_rd_data_reg[93] ;\n output \\not_strict_mode.app_rd_data_reg[92] ;\n output \\not_strict_mode.app_rd_data_reg[91] ;\n output \\not_strict_mode.app_rd_data_reg[90] ;\n output \\not_strict_mode.app_rd_data_reg[89] ;\n output \\not_strict_mode.app_rd_data_reg[88] ;\n output \\not_strict_mode.app_rd_data_reg[63] ;\n output \\not_strict_mode.app_rd_data_reg[62] ;\n output \\not_strict_mode.app_rd_data_reg[61] ;\n output \\not_strict_mode.app_rd_data_reg[60] ;\n output \\not_strict_mode.app_rd_data_reg[59] ;\n output \\not_strict_mode.app_rd_data_reg[58] ;\n output \\not_strict_mode.app_rd_data_reg[57] ;\n output \\not_strict_mode.app_rd_data_reg[56] ;\n output \\not_strict_mode.app_rd_data_reg[31] ;\n output \\not_strict_mode.app_rd_data_reg[30] ;\n output \\not_strict_mode.app_rd_data_reg[29] ;\n output \\not_strict_mode.app_rd_data_reg[28] ;\n output \\not_strict_mode.app_rd_data_reg[27] ;\n output \\not_strict_mode.app_rd_data_reg[26] ;\n output \\not_strict_mode.app_rd_data_reg[25] ;\n output \\not_strict_mode.app_rd_data_reg[24] ;\n output \\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n output \\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n output \\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n output \\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n output \\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n output \\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n output \\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n output \\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n output [63:0]\\not_strict_mode.app_rd_data_reg[255]_0 ;\n output \\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ;\n output \\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ;\n output \\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ;\n output \\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ;\n output \\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ;\n output \\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ;\n output \\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ;\n output \\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[31]_0 ;\n output A_byte_rd_en;\n output p_0_out;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n output \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n output \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n output \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n output \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n input ififo_rst;\n input CLK;\n input \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;\n input \\byte_r_reg[0] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;\n input \\byte_r_reg[1] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;\n input [1:0]\\rd_mux_sel_r_reg[1] ;\n input \\read_fifo.fifo_out_data_r_reg[6] ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n input [1:0]A;\n input [65:0]Q;\n input D_byte_rd_en;\n input B_byte_rd_en;\n input [0:0]if_empty_r_0;\n input [0:0]my_empty;\n input [1:0]\\po_stg2_wrcal_cnt_reg[1] ;\n\n wire [1:0]A;\n wire A_byte_rd_en;\n wire B_byte_rd_en;\n wire CLK;\n wire D_byte_rd_en;\n wire [65:0]Q;\n wire \\byte_r_reg[0] ;\n wire \\byte_r_reg[1] ;\n wire [63:0]\\data_bytes_r_reg[63] ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ;\n wire \\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n wire \\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n wire \\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n wire \\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;\n wire \\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n wire \\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n wire \\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n wire \\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ;\n wire [0:0]if_empty_r_0;\n wire ififo_rst;\n wire [63:1]mem_out;\n wire mem_reg_0_3_60_65_n_4;\n wire mem_reg_0_3_60_65_n_5;\n wire [0:0]my_empty;\n wire \\my_empty[4]_i_1__2_n_0 ;\n wire \\my_empty[4]_i_2_n_0 ;\n wire [3:1]my_empty_0;\n wire \\my_empty_reg[4]_rep__0_n_0 ;\n wire \\my_empty_reg[4]_rep_n_0 ;\n wire [1:0]my_full;\n wire \\my_full[0]_i_1_n_0 ;\n wire \\my_full[0]_i_2_n_0 ;\n wire \\my_full[1]_i_1_n_0 ;\n wire \\my_full[1]_i_2_n_0 ;\n wire \\not_strict_mode.app_rd_data_reg[120] ;\n wire \\not_strict_mode.app_rd_data_reg[121] ;\n wire \\not_strict_mode.app_rd_data_reg[122] ;\n wire \\not_strict_mode.app_rd_data_reg[123] ;\n wire \\not_strict_mode.app_rd_data_reg[124] ;\n wire \\not_strict_mode.app_rd_data_reg[125] ;\n wire \\not_strict_mode.app_rd_data_reg[126] ;\n wire \\not_strict_mode.app_rd_data_reg[127] ;\n wire \\not_strict_mode.app_rd_data_reg[152] ;\n wire \\not_strict_mode.app_rd_data_reg[153] ;\n wire \\not_strict_mode.app_rd_data_reg[154] ;\n wire \\not_strict_mode.app_rd_data_reg[155] ;\n wire \\not_strict_mode.app_rd_data_reg[156] ;\n wire \\not_strict_mode.app_rd_data_reg[157] ;\n wire \\not_strict_mode.app_rd_data_reg[158] ;\n wire \\not_strict_mode.app_rd_data_reg[159] ;\n wire \\not_strict_mode.app_rd_data_reg[184] ;\n wire \\not_strict_mode.app_rd_data_reg[185] ;\n wire \\not_strict_mode.app_rd_data_reg[186] ;\n wire \\not_strict_mode.app_rd_data_reg[187] ;\n wire \\not_strict_mode.app_rd_data_reg[188] ;\n wire \\not_strict_mode.app_rd_data_reg[189] ;\n wire \\not_strict_mode.app_rd_data_reg[190] ;\n wire \\not_strict_mode.app_rd_data_reg[191] ;\n wire \\not_strict_mode.app_rd_data_reg[216] ;\n wire \\not_strict_mode.app_rd_data_reg[217] ;\n wire \\not_strict_mode.app_rd_data_reg[218] ;\n wire \\not_strict_mode.app_rd_data_reg[219] ;\n wire \\not_strict_mode.app_rd_data_reg[220] ;\n wire \\not_strict_mode.app_rd_data_reg[221] ;\n wire \\not_strict_mode.app_rd_data_reg[222] ;\n wire \\not_strict_mode.app_rd_data_reg[223] ;\n wire \\not_strict_mode.app_rd_data_reg[248] ;\n wire \\not_strict_mode.app_rd_data_reg[249] ;\n wire \\not_strict_mode.app_rd_data_reg[24] ;\n wire \\not_strict_mode.app_rd_data_reg[250] ;\n wire \\not_strict_mode.app_rd_data_reg[251] ;\n wire \\not_strict_mode.app_rd_data_reg[252] ;\n wire \\not_strict_mode.app_rd_data_reg[252]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[253] ;\n wire \\not_strict_mode.app_rd_data_reg[254] ;\n wire \\not_strict_mode.app_rd_data_reg[255] ;\n wire [63:0]\\not_strict_mode.app_rd_data_reg[255]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[25] ;\n wire \\not_strict_mode.app_rd_data_reg[26] ;\n wire \\not_strict_mode.app_rd_data_reg[27] ;\n wire \\not_strict_mode.app_rd_data_reg[28] ;\n wire \\not_strict_mode.app_rd_data_reg[29] ;\n wire \\not_strict_mode.app_rd_data_reg[30] ;\n wire \\not_strict_mode.app_rd_data_reg[31] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[31]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[56] ;\n wire \\not_strict_mode.app_rd_data_reg[57] ;\n wire \\not_strict_mode.app_rd_data_reg[58] ;\n wire \\not_strict_mode.app_rd_data_reg[59] ;\n wire \\not_strict_mode.app_rd_data_reg[60] ;\n wire \\not_strict_mode.app_rd_data_reg[61] ;\n wire \\not_strict_mode.app_rd_data_reg[62] ;\n wire \\not_strict_mode.app_rd_data_reg[63] ;\n wire \\not_strict_mode.app_rd_data_reg[88] ;\n wire \\not_strict_mode.app_rd_data_reg[89] ;\n wire \\not_strict_mode.app_rd_data_reg[90] ;\n wire \\not_strict_mode.app_rd_data_reg[91] ;\n wire \\not_strict_mode.app_rd_data_reg[92] ;\n wire \\not_strict_mode.app_rd_data_reg[93] ;\n wire \\not_strict_mode.app_rd_data_reg[94] ;\n wire \\not_strict_mode.app_rd_data_reg[95] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n wire \\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ;\n wire p_0_out;\n wire [1:0]\\po_stg2_wrcal_cnt_reg[1] ;\n wire [1:0]\\rd_mux_sel_r_reg[1] ;\n wire [1:0]rd_ptr;\n wire \\rd_ptr[0]_i_1_n_0 ;\n wire \\rd_ptr[1]_i_1_n_0 ;\n (* RTL_KEEP = \"true\" *) (* syn_maxfan = \"10\" *) wire [1:0]rd_ptr_timing;\n wire \\rd_ptr_timing[0]_i_1__0_n_0 ;\n wire \\rd_ptr_timing[1]_i_1__4_n_0 ;\n wire \\read_fifo.fifo_out_data_r_reg[6] ;\n (* MAX_FANOUT = \"40\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire wr_en;\n wire [1:0]wr_ptr;\n wire \\wr_ptr[0]_i_1__2_n_0 ;\n wire \\wr_ptr[1]_i_1__2_n_0 ;\n wire \\wr_ptr[1]_i_3_n_0 ;\n wire \\wr_ptr_reg[1]_0 ;\n wire [1:0]NLW_mem_reg_0_3_0_5_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED;\n\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[24] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ),\n .O(\\data_bytes_r_reg[63] [0]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[10]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[58] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ),\n .O(\\data_bytes_r_reg[63] [10]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[11]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[59] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ),\n .O(\\data_bytes_r_reg[63] [11]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[12]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[60] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ),\n .O(\\data_bytes_r_reg[63] [12]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[13]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[61] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ),\n .O(\\data_bytes_r_reg[63] [13]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[14]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[62] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ),\n .O(\\data_bytes_r_reg[63] [14]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[15]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[63] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ),\n .O(\\data_bytes_r_reg[63] [15]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[16]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[88] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ),\n .O(\\data_bytes_r_reg[63] [16]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[17]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[89] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ),\n .O(\\data_bytes_r_reg[63] [17]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[18]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[90] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ),\n .O(\\data_bytes_r_reg[63] [18]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[19]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[91] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ),\n .O(\\data_bytes_r_reg[63] [19]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[25] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ),\n .O(\\data_bytes_r_reg[63] [1]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[20]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[92] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ),\n .O(\\data_bytes_r_reg[63] [20]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[21]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[93] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ),\n .O(\\data_bytes_r_reg[63] [21]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[22]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[94] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ),\n .O(\\data_bytes_r_reg[63] [22]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[23]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[95] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ),\n .O(\\data_bytes_r_reg[63] [23]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[24]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[120] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ),\n .O(\\data_bytes_r_reg[63] [24]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[25]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[121] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ),\n .O(\\data_bytes_r_reg[63] [25]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[26]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[122] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ),\n .O(\\data_bytes_r_reg[63] [26]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[27]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[123] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ),\n .O(\\data_bytes_r_reg[63] [27]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[28]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[124] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ),\n .O(\\data_bytes_r_reg[63] [28]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[29]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[125] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ),\n .O(\\data_bytes_r_reg[63] [29]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[26] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),\n .O(\\data_bytes_r_reg[63] [2]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[30]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[126] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ),\n .O(\\data_bytes_r_reg[63] [30]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[31]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[127] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ),\n .O(\\data_bytes_r_reg[63] [31]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[32]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[152] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ),\n .O(\\data_bytes_r_reg[63] [32]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[33]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[153] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ),\n .O(\\data_bytes_r_reg[63] [33]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[34]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[154] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ),\n .O(\\data_bytes_r_reg[63] [34]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[35]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[155] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ),\n .O(\\data_bytes_r_reg[63] [35]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[36]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[156] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ),\n .O(\\data_bytes_r_reg[63] [36]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[37]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[157] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ),\n .O(\\data_bytes_r_reg[63] [37]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[38]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[158] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ),\n .O(\\data_bytes_r_reg[63] [38]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[39]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[159] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ),\n .O(\\data_bytes_r_reg[63] [39]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[27] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ),\n .O(\\data_bytes_r_reg[63] [3]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[40]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[184] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ),\n .O(\\data_bytes_r_reg[63] [40]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[41]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[185] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ),\n .O(\\data_bytes_r_reg[63] [41]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[42]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[186] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ),\n .O(\\data_bytes_r_reg[63] [42]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[43]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[187] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ),\n .O(\\data_bytes_r_reg[63] [43]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[44]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[188] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ),\n .O(\\data_bytes_r_reg[63] [44]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[45]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[189] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ),\n .O(\\data_bytes_r_reg[63] [45]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[46]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[190] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ),\n .O(\\data_bytes_r_reg[63] [46]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[47]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[191] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ),\n .O(\\data_bytes_r_reg[63] [47]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[48]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[216] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ),\n .O(\\data_bytes_r_reg[63] [48]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[49]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[217] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ),\n .O(\\data_bytes_r_reg[63] [49]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[28] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),\n .O(\\data_bytes_r_reg[63] [4]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[50]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[218] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ),\n .O(\\data_bytes_r_reg[63] [50]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[51]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[219] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ),\n .O(\\data_bytes_r_reg[63] [51]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[52]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[220] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ),\n .O(\\data_bytes_r_reg[63] [52]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[53]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[221] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ),\n .O(\\data_bytes_r_reg[63] [53]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[54]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[222] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ),\n .O(\\data_bytes_r_reg[63] [54]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[55]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[223] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ),\n .O(\\data_bytes_r_reg[63] [55]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[56]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[248] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ),\n .O(\\data_bytes_r_reg[63] [56]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[57]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[249] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ),\n .O(\\data_bytes_r_reg[63] [57]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[58]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[250] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ),\n .O(\\data_bytes_r_reg[63] [58]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[59]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[251] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ),\n .O(\\data_bytes_r_reg[63] [59]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[29] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),\n .O(\\data_bytes_r_reg[63] [5]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[60]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[252]_0 ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ),\n .O(\\data_bytes_r_reg[63] [60]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[61]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[253] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ),\n .O(\\data_bytes_r_reg[63] [61]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[62]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[254] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ),\n .O(\\data_bytes_r_reg[63] [62]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[63]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[255] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ),\n .O(\\data_bytes_r_reg[63] [63]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[30] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),\n .O(\\data_bytes_r_reg[63] [6]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[31] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ),\n .O(\\data_bytes_r_reg[63] [7]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[8]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[56] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ),\n .O(\\data_bytes_r_reg[63] [8]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\data_bytes_r[9]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[57] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ),\n .I2(\\byte_r_reg[0] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ),\n .O(\\data_bytes_r_reg[63] [9]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[0].mux_rd_fall0_r1[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[56] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ),\n .O(\\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[0].mux_rd_fall0_r[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[56] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ),\n .O(\\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[0].mux_rd_fall1_r1[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[120] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ),\n .O(\\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[0].mux_rd_fall1_r[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[120] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ),\n .O(\\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[0].mux_rd_fall2_r1[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[184] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ),\n .O(\\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[0].mux_rd_fall2_r[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[184] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ),\n .O(\\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[0].mux_rd_fall3_r1[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[248] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ),\n .O(\\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[0].mux_rd_fall3_r[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[248] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ),\n .O(\\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[0].mux_rd_rise0_r1[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[24] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ),\n .O(\\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[0].mux_rd_rise0_r[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[24] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ),\n .O(\\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[0].mux_rd_rise1_r1[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[88] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ),\n .O(\\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[0].mux_rd_rise1_r[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[88] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ),\n .O(\\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[0].mux_rd_rise2_r1[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[152] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ),\n .O(\\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[0].mux_rd_rise2_r[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[152] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ),\n .O(\\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[0].mux_rd_rise3_r1[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[216] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ),\n .O(\\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[0].mux_rd_rise3_r[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[216] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ),\n .O(\\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[1].mux_rd_fall0_r1[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[57] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ),\n .O(\\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[1].mux_rd_fall0_r[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[57] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ),\n .O(\\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[1].mux_rd_fall1_r1[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[121] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ),\n .O(\\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[1].mux_rd_fall1_r[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[121] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ),\n .O(\\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[1].mux_rd_fall2_r1[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[185] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ),\n .O(\\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[1].mux_rd_fall2_r[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[185] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ),\n .O(\\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[1].mux_rd_fall3_r1[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[249] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ),\n .O(\\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[1].mux_rd_fall3_r[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[249] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ),\n .O(\\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[1].mux_rd_rise0_r1[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[25] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ),\n .O(\\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[1].mux_rd_rise0_r[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[25] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ),\n .O(\\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[1].mux_rd_rise1_r1[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[89] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ),\n .O(\\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[1].mux_rd_rise1_r[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[89] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ),\n .O(\\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[1].mux_rd_rise2_r1[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[153] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ),\n .O(\\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[1].mux_rd_rise2_r[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[153] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ),\n .O(\\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[1].mux_rd_rise3_r1[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[217] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ),\n .O(\\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[1].mux_rd_rise3_r[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[217] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ),\n .O(\\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[2].mux_rd_fall0_r1[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[58] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ),\n .O(\\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[2].mux_rd_fall0_r[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[58] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ),\n .O(\\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[2].mux_rd_fall1_r1[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[122] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ),\n .O(\\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[2].mux_rd_fall1_r[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[122] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ),\n .O(\\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[2].mux_rd_fall2_r1[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[186] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ),\n .O(\\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[2].mux_rd_fall2_r[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[186] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ),\n .O(\\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[2].mux_rd_fall3_r1[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[250] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ),\n .O(\\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[2].mux_rd_fall3_r[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[250] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ),\n .O(\\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[2].mux_rd_rise0_r1[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[26] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),\n .O(\\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[2].mux_rd_rise0_r[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[26] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),\n .O(\\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[2].mux_rd_rise1_r1[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[90] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ),\n .O(\\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[2].mux_rd_rise1_r[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[90] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ),\n .O(\\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[2].mux_rd_rise2_r1[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[154] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ),\n .O(\\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[2].mux_rd_rise2_r[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[154] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ),\n .O(\\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[2].mux_rd_rise3_r1[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[218] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ),\n .O(\\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[2].mux_rd_rise3_r[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[218] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ),\n .O(\\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[3].mux_rd_fall0_r1[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[59] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ),\n .O(\\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[3].mux_rd_fall0_r[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[59] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ),\n .O(\\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[3].mux_rd_fall1_r1[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[123] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ),\n .O(\\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[3].mux_rd_fall1_r[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[123] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ),\n .O(\\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[3].mux_rd_fall2_r1[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[187] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ),\n .O(\\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[3].mux_rd_fall2_r[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[187] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ),\n .O(\\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[3].mux_rd_fall3_r1[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[251] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ),\n .O(\\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[3].mux_rd_fall3_r[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[251] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ),\n .O(\\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[3].mux_rd_rise0_r1[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[27] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ),\n .O(\\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[3].mux_rd_rise0_r[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[27] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ),\n .O(\\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[3].mux_rd_rise1_r1[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[91] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ),\n .O(\\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[3].mux_rd_rise1_r[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[91] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ),\n .O(\\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[3].mux_rd_rise2_r1[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[155] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ),\n .O(\\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[3].mux_rd_rise2_r[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[155] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ),\n .O(\\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[3].mux_rd_rise3_r1[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[219] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ),\n .O(\\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[3].mux_rd_rise3_r[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[219] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ),\n .O(\\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[4].mux_rd_fall0_r1[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[60] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ),\n .O(\\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[4].mux_rd_fall0_r[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[60] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ),\n .O(\\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[4].mux_rd_fall1_r1[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[124] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ),\n .O(\\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[4].mux_rd_fall1_r[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[124] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ),\n .O(\\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[4].mux_rd_fall2_r1[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[188] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ),\n .O(\\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[4].mux_rd_fall2_r[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[188] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ),\n .O(\\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[4].mux_rd_fall3_r1[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[252]_0 ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ),\n .O(\\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[4].mux_rd_fall3_r[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[252]_0 ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ),\n .O(\\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[4].mux_rd_rise0_r1[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[28] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),\n .O(\\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[4].mux_rd_rise0_r[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[28] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),\n .O(\\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[4].mux_rd_rise1_r1[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[92] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ),\n .O(\\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[4].mux_rd_rise1_r[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[92] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ),\n .O(\\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[4].mux_rd_rise2_r1[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[156] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ),\n .O(\\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[4].mux_rd_rise2_r[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[156] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ),\n .O(\\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[4].mux_rd_rise3_r1[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[220] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ),\n .O(\\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[4].mux_rd_rise3_r[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[220] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ),\n .O(\\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[5].mux_rd_fall0_r1[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[61] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ),\n .O(\\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[5].mux_rd_fall0_r[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[61] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ),\n .O(\\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[5].mux_rd_fall1_r1[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[125] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ),\n .O(\\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[5].mux_rd_fall1_r[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[125] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ),\n .O(\\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[5].mux_rd_fall2_r1[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[189] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ),\n .O(\\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[5].mux_rd_fall2_r[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[189] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ),\n .O(\\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[5].mux_rd_fall3_r1[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[253] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ),\n .O(\\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[5].mux_rd_fall3_r[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[253] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ),\n .O(\\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[5].mux_rd_rise0_r1[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[29] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),\n .O(\\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[5].mux_rd_rise0_r[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[29] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),\n .O(\\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[5].mux_rd_rise1_r1[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[93] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ),\n .O(\\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[5].mux_rd_rise1_r[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[93] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ),\n .O(\\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[5].mux_rd_rise2_r1[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[157] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ),\n .O(\\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[5].mux_rd_rise2_r[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[157] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ),\n .O(\\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[5].mux_rd_rise3_r1[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[221] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ),\n .O(\\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[5].mux_rd_rise3_r[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[221] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ),\n .O(\\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[6].mux_rd_fall0_r1[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[62] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ),\n .O(\\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[6].mux_rd_fall0_r[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[62] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ),\n .O(\\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[6].mux_rd_fall1_r1[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[126] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ),\n .O(\\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[6].mux_rd_fall1_r[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[126] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ),\n .O(\\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[6].mux_rd_fall2_r1[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[190] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ),\n .O(\\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[6].mux_rd_fall2_r[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[190] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ),\n .O(\\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[6].mux_rd_fall3_r1[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[254] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ),\n .O(\\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[6].mux_rd_fall3_r[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[254] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ),\n .O(\\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[6].mux_rd_rise0_r1[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[30] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),\n .O(\\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[6].mux_rd_rise0_r[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[30] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),\n .O(\\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[6].mux_rd_rise1_r1[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[94] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ),\n .O(\\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[6].mux_rd_rise1_r[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[94] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ),\n .O(\\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[6].mux_rd_rise2_r1[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[158] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ),\n .O(\\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[6].mux_rd_rise2_r[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[158] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ),\n .O(\\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[6].mux_rd_rise3_r1[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[222] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ),\n .O(\\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[6].mux_rd_rise3_r[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[222] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ),\n .O(\\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[7].mux_rd_fall0_r1[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[63] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ),\n .O(\\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[7].mux_rd_fall0_r[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[63] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ),\n .O(\\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[7].mux_rd_fall1_r1[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[127] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ),\n .O(\\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[7].mux_rd_fall1_r[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[127] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ),\n .O(\\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[7].mux_rd_fall2_r1[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[191] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ),\n .O(\\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[7].mux_rd_fall2_r[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[191] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ),\n .O(\\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[7].mux_rd_fall3_r1[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[255] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ),\n .O(\\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[7].mux_rd_fall3_r[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[255] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ),\n .O(\\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[7].mux_rd_rise0_r1[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[31] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ),\n .O(\\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[7].mux_rd_rise0_r[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[31] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ),\n .O(\\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[7].mux_rd_rise1_r1[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[95] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ),\n .O(\\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[7].mux_rd_rise1_r[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[95] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ),\n .O(\\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[7].mux_rd_rise2_r1[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[159] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ),\n .O(\\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[7].mux_rd_rise2_r[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[159] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ),\n .O(\\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[7].mux_rd_rise3_r1[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[223] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ),\n .I2(A[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ),\n .I4(A[0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ),\n .O(\\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd[7].mux_rd_rise3_r[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[223] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ),\n .I2(\\rd_mux_sel_r_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ),\n .I4(\\rd_mux_sel_r_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ),\n .O(\\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[56] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[120] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[184] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[248] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[24] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[88] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ),\n .O(p_0_out));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r[0]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[216] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[57] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[121] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[185] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[249] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[25] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[89] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[153] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r[1]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[217] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[58] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[122] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[186] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[250] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[26] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[90] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[154] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r[2]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[218] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[59] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[123] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[187] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[251] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[27] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[91] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r[3]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[155] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[60] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[124] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[188] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[252]_0 ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[28] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[92] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r[4]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[220] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[61] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[125] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[189] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[253] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[29] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[93] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[157] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r[5]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[221] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[62] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[126] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[190] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[254] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[30] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[94] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[158] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r[6]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[222] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[63] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[127] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[191] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[255] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[31] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[95] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r[7]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[159] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ),\n .O(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[152] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ),\n .O(\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[219] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ),\n .O(\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[156] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ),\n .O(\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[223] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] [1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ),\n .I4(\\po_stg2_wrcal_cnt_reg[1] [0]),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ),\n .O(\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_0_5\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[1:0]),\n .DIB(Q[3:2]),\n .DIC(Q[5:4]),\n .DID({1'b0,1'b0}),\n .DOA({mem_out[1],\\not_strict_mode.app_rd_data_reg[31]_0 }),\n .DOB(mem_out[3:2]),\n .DOC(mem_out[5:4]),\n .DOD(NLW_mem_reg_0_3_0_5_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n LUT4 #(\n .INIT(16'h0151)) \n mem_reg_0_3_0_5_i_1\n (.I0(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I1(my_full[0]),\n .I2(\\wr_ptr[1]_i_3_n_0 ),\n .I3(my_empty_0[2]),\n .O(wr_en));\n LUT1 #(\n .INIT(2'h2)) \n mem_reg_0_3_0_5_i_2\n (.I0(\\wr_ptr_reg[1]_0 ),\n .O(my_empty_0[2]));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_12_17\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[13:12]),\n .DIB(Q[15:14]),\n .DIC(Q[17:16]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[13:12]),\n .DOB(mem_out[15:14]),\n .DOC(mem_out[17:16]),\n .DOD(NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_18_23\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[19:18]),\n .DIB(Q[21:20]),\n .DIC(Q[23:22]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[19:18]),\n .DOB(mem_out[21:20]),\n .DOC(mem_out[23:22]),\n .DOD(NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_24_29\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[25:24]),\n .DIB(Q[27:26]),\n .DIC(Q[29:28]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[25:24]),\n .DOB(mem_out[27:26]),\n .DOC(mem_out[29:28]),\n .DOD(NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_30_35\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[31:30]),\n .DIB(Q[33:32]),\n .DIC(Q[35:34]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[31:30]),\n .DOB(mem_out[33:32]),\n .DOC(mem_out[35:34]),\n .DOD(NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_36_41\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[37:36]),\n .DIB(Q[39:38]),\n .DIC(Q[41:40]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[37:36]),\n .DOB(mem_out[39:38]),\n .DOC(mem_out[41:40]),\n .DOD(NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_42_47\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[43:42]),\n .DIB(Q[45:44]),\n .DIC(Q[47:46]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[43:42]),\n .DOB(mem_out[45:44]),\n .DOC(mem_out[47:46]),\n .DOD(NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_48_53\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[49:48]),\n .DIB(Q[51:50]),\n .DIC(Q[53:52]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[49:48]),\n .DOB(mem_out[51:50]),\n .DOC(mem_out[53:52]),\n .DOD(NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_54_59\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[55:54]),\n .DIB(Q[57:56]),\n .DIC(Q[59:58]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[55:54]),\n .DOB(mem_out[57:56]),\n .DOC(mem_out[59:58]),\n .DOD(NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_60_65\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[61:60]),\n .DIB(Q[63:62]),\n .DIC(Q[65:64]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[61:60]),\n .DOB(mem_out[63:62]),\n .DOC({mem_reg_0_3_60_65_n_4,mem_reg_0_3_60_65_n_5}),\n .DOD(NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_3_6_11\n (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),\n .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),\n .DIA(Q[7:6]),\n .DIB(Q[9:8]),\n .DIC(Q[11:10]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[7:6]),\n .DOB(mem_out[9:8]),\n .DOC(mem_out[11:10]),\n .DOD(NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n LUT4 #(\n .INIT(16'h0140)) \n \\my_empty[4]_i_1__2 \n (.I0(my_full[1]),\n .I1(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I2(\\wr_ptr[1]_i_3_n_0 ),\n .I3(my_empty_0[1]),\n .O(\\my_empty[4]_i_1__2_n_0 ));\n LUT5 #(\n .INIT(32'h00000960)) \n \\my_empty[4]_i_2 \n (.I0(wr_ptr[1]),\n .I1(rd_ptr[1]),\n .I2(rd_ptr[0]),\n .I3(wr_ptr[0]),\n .I4(my_empty_0[1]),\n .O(\\my_empty[4]_i_2_n_0 ));\n (* ORIG_CELL_NAME = \"my_empty_reg[4]\" *) \n FDSE \\my_empty_reg[4] \n (.C(CLK),\n .CE(\\my_empty[4]_i_1__2_n_0 ),\n .D(\\my_empty[4]_i_2_n_0 ),\n .Q(\\wr_ptr_reg[1]_0 ),\n .S(ififo_rst));\n (* ORIG_CELL_NAME = \"my_empty_reg[4]\" *) \n FDSE \\my_empty_reg[4]_rep \n (.C(CLK),\n .CE(\\my_empty[4]_i_1__2_n_0 ),\n .D(\\my_empty[4]_i_2_n_0 ),\n .Q(\\my_empty_reg[4]_rep_n_0 ),\n .S(ififo_rst));\n (* ORIG_CELL_NAME = \"my_empty_reg[4]\" *) \n FDSE \\my_empty_reg[4]_rep__0 \n (.C(CLK),\n .CE(\\my_empty[4]_i_1__2_n_0 ),\n .D(\\my_empty[4]_i_2_n_0 ),\n .Q(\\my_empty_reg[4]_rep__0_n_0 ),\n .S(ififo_rst));\n LUT6 #(\n .INIT(64'hBAAAAAAB8AAAAAA8)) \n \\my_full[0]_i_1 \n (.I0(my_full[0]),\n .I1(my_empty_0[1]),\n .I2(my_full[1]),\n .I3(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I4(\\wr_ptr[1]_i_3_n_0 ),\n .I5(\\my_full[0]_i_2_n_0 ),\n .O(\\my_full[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h00000960)) \n \\my_full[0]_i_2 \n (.I0(rd_ptr[1]),\n .I1(wr_ptr[1]),\n .I2(wr_ptr[0]),\n .I3(rd_ptr[0]),\n .I4(my_full[1]),\n .O(\\my_full[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAA00411400)) \n \\my_full[1]_i_1 \n (.I0(\\my_full[1]_i_2_n_0 ),\n .I1(rd_ptr[1]),\n .I2(wr_ptr[1]),\n .I3(wr_ptr[0]),\n .I4(rd_ptr[0]),\n .I5(my_full[1]),\n .O(\\my_full[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair734\" *) \n LUT4 #(\n .INIT(16'hBFFE)) \n \\my_full[1]_i_2 \n (.I0(my_empty_0[1]),\n .I1(my_full[1]),\n .I2(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I3(\\wr_ptr[1]_i_3_n_0 ),\n .O(\\my_full[1]_i_2_n_0 ));\n FDRE \\my_full_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_full[0]_i_1_n_0 ),\n .Q(my_full[0]),\n .R(ififo_rst));\n FDRE \\my_full_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_full[1]_i_1_n_0 ),\n .Q(my_full[1]),\n .R(ififo_rst));\n (* SOFT_HLUTNM = \"soft_lutpair760\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[120]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[120] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [24]));\n (* SOFT_HLUTNM = \"soft_lutpair761\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[121]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[121] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [25]));\n (* SOFT_HLUTNM = \"soft_lutpair762\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[122]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[122] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [26]));\n (* SOFT_HLUTNM = \"soft_lutpair763\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[123]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[123] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [27]));\n (* SOFT_HLUTNM = \"soft_lutpair764\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[124]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[124] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [28]));\n (* SOFT_HLUTNM = \"soft_lutpair765\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[125]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[125] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [29]));\n (* SOFT_HLUTNM = \"soft_lutpair766\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[126]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[126] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [30]));\n (* SOFT_HLUTNM = \"soft_lutpair767\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[127]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[127] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [31]));\n (* SOFT_HLUTNM = \"soft_lutpair767\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[152]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[152] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [32]));\n (* SOFT_HLUTNM = \"soft_lutpair766\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[153]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[153] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [33]));\n (* SOFT_HLUTNM = \"soft_lutpair765\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[154]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[154] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [34]));\n (* SOFT_HLUTNM = \"soft_lutpair764\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[155]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[155] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [35]));\n (* SOFT_HLUTNM = \"soft_lutpair763\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[156]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[156] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [36]));\n (* SOFT_HLUTNM = \"soft_lutpair762\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[157]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[157] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [37]));\n (* SOFT_HLUTNM = \"soft_lutpair761\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[158]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[158] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [38]));\n (* SOFT_HLUTNM = \"soft_lutpair760\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[159]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[159] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [39]));\n (* SOFT_HLUTNM = \"soft_lutpair759\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[184]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[184] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [40]));\n (* SOFT_HLUTNM = \"soft_lutpair758\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[185]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[185] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [41]));\n (* SOFT_HLUTNM = \"soft_lutpair757\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[186]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[186] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [42]));\n (* SOFT_HLUTNM = \"soft_lutpair756\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[187]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[187] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [43]));\n (* SOFT_HLUTNM = \"soft_lutpair755\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[188]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[188] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [44]));\n (* SOFT_HLUTNM = \"soft_lutpair754\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[189]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[189] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [45]));\n (* SOFT_HLUTNM = \"soft_lutpair753\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[190]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[190] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [46]));\n (* SOFT_HLUTNM = \"soft_lutpair752\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[191]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[191] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [47]));\n (* SOFT_HLUTNM = \"soft_lutpair751\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[216]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[216] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [48]));\n (* SOFT_HLUTNM = \"soft_lutpair750\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[217]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[217] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [49]));\n (* SOFT_HLUTNM = \"soft_lutpair749\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[218]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[218] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [50]));\n (* SOFT_HLUTNM = \"soft_lutpair748\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[219]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[219] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [51]));\n (* SOFT_HLUTNM = \"soft_lutpair747\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[220]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[220] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [52]));\n (* SOFT_HLUTNM = \"soft_lutpair746\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[221]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[221] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [53]));\n (* SOFT_HLUTNM = \"soft_lutpair745\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[222]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[222] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [54]));\n (* SOFT_HLUTNM = \"soft_lutpair744\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[223]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[223] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [55]));\n (* SOFT_HLUTNM = \"soft_lutpair743\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[248]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[248] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [56]));\n (* SOFT_HLUTNM = \"soft_lutpair742\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[249]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[249] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [57]));\n (* SOFT_HLUTNM = \"soft_lutpair736\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[24]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[24] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair741\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[250]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[250] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [58]));\n (* SOFT_HLUTNM = \"soft_lutpair740\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[251]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[251] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [59]));\n (* SOFT_HLUTNM = \"soft_lutpair739\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[252]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[252]_0 ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [60]));\n (* SOFT_HLUTNM = \"soft_lutpair738\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[253]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[253] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [61]));\n (* SOFT_HLUTNM = \"soft_lutpair737\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[254]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[254] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [62]));\n (* SOFT_HLUTNM = \"soft_lutpair736\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[255]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[255] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [63]));\n (* SOFT_HLUTNM = \"soft_lutpair737\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[25]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[25] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [1]));\n (* SOFT_HLUTNM = \"soft_lutpair738\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[26]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[26] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [2]));\n (* SOFT_HLUTNM = \"soft_lutpair739\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[27]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[27] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [3]));\n (* SOFT_HLUTNM = \"soft_lutpair740\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[28]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[28] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [4]));\n (* SOFT_HLUTNM = \"soft_lutpair741\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[29]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[29] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [5]));\n (* SOFT_HLUTNM = \"soft_lutpair742\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[30]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[30] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [6]));\n (* SOFT_HLUTNM = \"soft_lutpair743\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[31]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[31] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [7]));\n (* SOFT_HLUTNM = \"soft_lutpair744\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[56]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[56] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [8]));\n (* SOFT_HLUTNM = \"soft_lutpair745\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[57]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[57] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [9]));\n (* SOFT_HLUTNM = \"soft_lutpair746\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[58]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[58] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [10]));\n (* SOFT_HLUTNM = \"soft_lutpair747\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[59]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[59] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [11]));\n (* SOFT_HLUTNM = \"soft_lutpair748\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[60]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[60] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [12]));\n (* SOFT_HLUTNM = \"soft_lutpair749\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[61]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[61] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [13]));\n (* SOFT_HLUTNM = \"soft_lutpair750\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[62]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[62] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [14]));\n (* SOFT_HLUTNM = \"soft_lutpair751\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[63]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[63] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [15]));\n (* SOFT_HLUTNM = \"soft_lutpair752\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[88]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[88] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [16]));\n (* SOFT_HLUTNM = \"soft_lutpair753\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[89]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[89] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [17]));\n (* SOFT_HLUTNM = \"soft_lutpair754\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[90]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[90] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [18]));\n (* SOFT_HLUTNM = \"soft_lutpair755\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[91]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[91] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [19]));\n (* SOFT_HLUTNM = \"soft_lutpair756\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[92]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[92] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [20]));\n (* SOFT_HLUTNM = \"soft_lutpair757\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[93]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[93] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [21]));\n (* SOFT_HLUTNM = \"soft_lutpair758\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[94]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[94] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [0]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [22]));\n (* SOFT_HLUTNM = \"soft_lutpair759\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.app_rd_data[95]_i_1 \n (.I0(\\not_strict_mode.app_rd_data_reg[95] ),\n .I1(\\read_fifo.fifo_out_data_r_reg[6] ),\n .I2(\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 [1]),\n .O(\\not_strict_mode.app_rd_data_reg[255]_0 [23]));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_3 \n (.I0(Q[1]),\n .I1(mem_out[1]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[63] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_4 \n (.I0(Q[9]),\n .I1(mem_out[9]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[62] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_5 \n (.I0(Q[17]),\n .I1(mem_out[17]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[61] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_6 \n (.I0(Q[25]),\n .I1(mem_out[25]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[60] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_1 \n (.I0(Q[50]),\n .I1(mem_out[50]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[89] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_2 \n (.I0(Q[58]),\n .I1(mem_out[58]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[88] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_1 \n (.I0(Q[2]),\n .I1(mem_out[2]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[95] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_2 \n (.I0(Q[10]),\n .I1(mem_out[10]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[94] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_3 \n (.I0(Q[18]),\n .I1(mem_out[18]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[93] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_4 \n (.I0(Q[26]),\n .I1(mem_out[26]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[92] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_5 \n (.I0(Q[34]),\n .I1(mem_out[34]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[91] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_6 \n (.I0(Q[42]),\n .I1(mem_out[42]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[90] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_1 \n (.I0(Q[19]),\n .I1(mem_out[19]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[125] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_2 \n (.I0(Q[27]),\n .I1(mem_out[27]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[124] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_3 \n (.I0(Q[35]),\n .I1(mem_out[35]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[123] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_4 \n (.I0(Q[43]),\n .I1(mem_out[43]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[122] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_5 \n (.I0(Q[51]),\n .I1(mem_out[51]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[121] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_6 \n (.I0(Q[59]),\n .I1(mem_out[59]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[120] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_5 \n (.I0(Q[3]),\n .I1(mem_out[3]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[127] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_6 \n (.I0(Q[11]),\n .I1(mem_out[11]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[126] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_1 \n (.I0(Q[36]),\n .I1(mem_out[36]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[155] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_2 \n (.I0(Q[44]),\n .I1(mem_out[44]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[154] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_3 \n (.I0(Q[52]),\n .I1(mem_out[52]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[153] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_4 \n (.I0(Q[60]),\n .I1(mem_out[60]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[152] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_3 \n (.I0(Q[4]),\n .I1(mem_out[4]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[159] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_4 \n (.I0(Q[12]),\n .I1(mem_out[12]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[158] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_5 \n (.I0(Q[20]),\n .I1(mem_out[20]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[157] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_6 \n (.I0(Q[28]),\n .I1(mem_out[28]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[156] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_1 \n (.I0(Q[53]),\n .I1(mem_out[53]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[185] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_2 \n (.I0(Q[61]),\n .I1(mem_out[61]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[184] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_1 \n (.I0(Q[5]),\n .I1(mem_out[5]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[191] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_2 \n (.I0(Q[13]),\n .I1(mem_out[13]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[190] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_3 \n (.I0(Q[21]),\n .I1(mem_out[21]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[189] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_4 \n (.I0(Q[29]),\n .I1(mem_out[29]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[188] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_5 \n (.I0(Q[37]),\n .I1(mem_out[37]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[187] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_6 \n (.I0(Q[45]),\n .I1(mem_out[45]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[186] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_1 \n (.I0(Q[22]),\n .I1(mem_out[22]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[221] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_2 \n (.I0(Q[30]),\n .I1(mem_out[30]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[220] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_3 \n (.I0(Q[38]),\n .I1(mem_out[38]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[219] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_4 \n (.I0(Q[46]),\n .I1(mem_out[46]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[218] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_5 \n (.I0(Q[54]),\n .I1(mem_out[54]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[217] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_6 \n (.I0(Q[62]),\n .I1(mem_out[62]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[216] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_5 \n (.I0(Q[6]),\n .I1(mem_out[6]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[223] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_6 \n (.I0(Q[14]),\n .I1(mem_out[14]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[222] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_1 \n (.I0(Q[39]),\n .I1(mem_out[39]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[251] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_2 \n (.I0(Q[47]),\n .I1(mem_out[47]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[250] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_3 \n (.I0(Q[55]),\n .I1(mem_out[55]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[249] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_4 \n (.I0(Q[63]),\n .I1(mem_out[63]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[248] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_1 \n (.I0(Q[7]),\n .I1(mem_out[7]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[255] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_2 \n (.I0(Q[15]),\n .I1(mem_out[15]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[254] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_3 \n (.I0(Q[23]),\n .I1(mem_out[23]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[253] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_4 \n (.I0(Q[31]),\n .I1(mem_out[31]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[252]_0 ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_1 \n (.I0(Q[16]),\n .I1(mem_out[16]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[29] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_2 \n (.I0(Q[24]),\n .I1(mem_out[24]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[28] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_3 \n (.I0(Q[32]),\n .I1(mem_out[32]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[27] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_4 \n (.I0(Q[40]),\n .I1(mem_out[40]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[26] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_5 \n (.I0(Q[48]),\n .I1(mem_out[48]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[25] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_6 \n (.I0(Q[56]),\n .I1(mem_out[56]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[24] ));\n LUT1 #(\n .INIT(2'h2)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_7 \n (.I0(\\my_empty_reg[4]_rep_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[252] ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8 \n (.I0(\\my_empty_reg[4]_rep__0_n_0 ),\n .O(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_5 \n (.I0(Q[0]),\n .I1(\\not_strict_mode.app_rd_data_reg[31]_0 ),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[31] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_6 \n (.I0(Q[8]),\n .I1(mem_out[8]),\n .I2(\\not_strict_mode.app_rd_data_reg[252] ),\n .O(\\not_strict_mode.app_rd_data_reg[30] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_1 \n (.I0(Q[33]),\n .I1(mem_out[33]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[59] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_2 \n (.I0(Q[41]),\n .I1(mem_out[41]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[58] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_3 \n (.I0(Q[49]),\n .I1(mem_out[49]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[57] ));\n LUT3 #(\n .INIT(8'hAC)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_4 \n (.I0(Q[57]),\n .I1(mem_out[57]),\n .I2(\\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_8_n_0 ),\n .O(\\not_strict_mode.app_rd_data_reg[56] ));\n (* SOFT_HLUTNM = \"soft_lutpair735\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\rd_ptr[0]_i_1 \n (.I0(my_empty_0[1]),\n .I1(\\wr_ptr[1]_i_3_n_0 ),\n .I2(rd_ptr[0]),\n .O(\\rd_ptr[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair735\" *) \n LUT4 #(\n .INIT(16'hDF20)) \n \\rd_ptr[1]_i_1 \n (.I0(rd_ptr[0]),\n .I1(my_empty_0[1]),\n .I2(\\wr_ptr[1]_i_3_n_0 ),\n .I3(rd_ptr[1]),\n .O(\\rd_ptr[1]_i_1_n_0 ));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_ptr[0]_i_1_n_0 ),\n .Q(rd_ptr[0]),\n .R(ififo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_ptr[1]_i_1_n_0 ),\n .Q(rd_ptr[1]),\n .R(ififo_rst));\n LUT4 #(\n .INIT(16'hA2AE)) \n \\rd_ptr_timing[0]_i_1__0 \n (.I0(rd_ptr_timing[0]),\n .I1(\\wr_ptr[1]_i_3_n_0 ),\n .I2(my_empty_0[1]),\n .I3(rd_ptr[0]),\n .O(\\rd_ptr_timing[0]_i_1__0_n_0 ));\n LUT5 #(\n .INIT(32'hF0F066F0)) \n \\rd_ptr_timing[1]_i_1__4 \n (.I0(rd_ptr[0]),\n .I1(rd_ptr[1]),\n .I2(rd_ptr_timing[1]),\n .I3(\\wr_ptr[1]_i_3_n_0 ),\n .I4(my_empty_0[1]),\n .O(\\rd_ptr_timing[1]_i_1__4_n_0 ));\n (* KEEP = \"yes\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_ptr_timing[0]_i_1__0_n_0 ),\n .Q(rd_ptr_timing[0]),\n .R(ififo_rst));\n (* KEEP = \"yes\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_ptr_timing[1]_i_1__4_n_0 ),\n .Q(rd_ptr_timing[1]),\n .R(ififo_rst));\n (* SOFT_HLUTNM = \"soft_lutpair734\" *) \n LUT5 #(\n .INIT(32'hEEFA1105)) \n \\wr_ptr[0]_i_1__2 \n (.I0(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I1(my_empty_0[1]),\n .I2(my_full[1]),\n .I3(\\wr_ptr[1]_i_3_n_0 ),\n .I4(wr_ptr[0]),\n .O(\\wr_ptr[0]_i_1__2_n_0 ));\n LUT6 #(\n .INIT(64'hFDFDFFDD02020022)) \n \\wr_ptr[1]_i_1__2 \n (.I0(wr_ptr[0]),\n .I1(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I2(my_empty_0[1]),\n .I3(my_full[1]),\n .I4(\\wr_ptr[1]_i_3_n_0 ),\n .I5(wr_ptr[1]),\n .O(\\wr_ptr[1]_i_1__2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair768\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\wr_ptr[1]_i_2 \n (.I0(\\wr_ptr_reg[1]_0 ),\n .O(my_empty_0[1]));\n LUT6 #(\n .INIT(64'h0000700070007000)) \n \\wr_ptr[1]_i_3 \n (.I0(my_empty_0[3]),\n .I1(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I2(D_byte_rd_en),\n .I3(B_byte_rd_en),\n .I4(if_empty_r_0),\n .I5(my_empty),\n .O(\\wr_ptr[1]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair768\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\wr_ptr[1]_i_4 \n (.I0(\\wr_ptr_reg[1]_0 ),\n .O(my_empty_0[3]));\n LUT2 #(\n .INIT(4'h7)) \n \\wr_ptr[1]_i_5 \n (.I0(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I1(my_empty_0[3]),\n .O(A_byte_rd_en));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_ptr[0]_i_1__2_n_0 ),\n .Q(wr_ptr[0]),\n .R(ififo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_ptr[1]_i_1__2_n_0 ),\n .Q(wr_ptr[1]),\n .R(ififo_rst));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_ddr_mc_phy\n (\\rd_ptr_timing_reg[2] ,\n \\rd_ptr_timing_reg[2]_0 ,\n \\rd_ptr_timing_reg[2]_1 ,\n \\rd_ptr_timing_reg[2]_2 ,\n \\rd_ptr_timing_reg[2]_3 ,\n \\rd_ptr_timing_reg[2]_4 ,\n \\rd_ptr_timing_reg[2]_5 ,\n \\rd_ptr_timing_reg[2]_6 ,\n \\rd_ptr_timing_reg[2]_7 ,\n \\rd_ptr_timing_reg[2]_8 ,\n \\rd_ptr_timing_reg[2]_9 ,\n \\rd_ptr_timing_reg[2]_10 ,\n \\pi_dqs_found_lanes_r1_reg[3] ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,\n mem_dqs_out,\n mem_dqs_ts,\n mem_dq_out,\n mem_dq_ts,\n idelay_ld_rst,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,\n idelay_ld_rst_0,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,\n idelay_ld_rst_1,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,\n idelay_ld_rst_2,\n \\calib_seq_reg[0] ,\n \\not_strict_mode.app_rd_data_reg[252] ,\n \\not_strict_mode.app_rd_data_reg[244] ,\n \\not_strict_mode.app_rd_data_reg[236] ,\n \\not_strict_mode.app_rd_data_reg[228] ,\n \\my_empty_reg[1] ,\n \\my_empty_reg[1]_0 ,\n phy_mc_ctl_full,\n \\my_empty_reg[1]_1 ,\n \\my_empty_reg[1]_2 ,\n \\my_empty_reg[1]_3 ,\n \\my_empty_reg[1]_4 ,\n \\my_empty_reg[1]_5 ,\n rd_buf_we,\n \\not_strict_mode.status_ram.rd_buf_we_r1_reg ,\n \\my_empty_reg[1]_6 ,\n phy_rddata_en,\n mux_rd_valid_r_reg,\n rst_sync_r1_reg,\n \\byte_r_reg[0] ,\n \\po_counter_read_val_r_reg[5] ,\n \\data_bytes_r_reg[63] ,\n \\not_strict_mode.app_rd_data_reg[255] ,\n \\not_strict_mode.app_rd_data_reg[239] ,\n \\not_strict_mode.app_rd_data_reg[247] ,\n \\not_strict_mode.app_rd_data_reg[231] ,\n \\not_strict_mode.app_rd_data_reg[254] ,\n \\not_strict_mode.app_rd_data_reg[238] ,\n \\not_strict_mode.app_rd_data_reg[246] ,\n \\not_strict_mode.app_rd_data_reg[230] ,\n \\not_strict_mode.app_rd_data_reg[253] ,\n \\not_strict_mode.app_rd_data_reg[237] ,\n \\not_strict_mode.app_rd_data_reg[245] ,\n \\not_strict_mode.app_rd_data_reg[229] ,\n \\not_strict_mode.app_rd_data_reg[252]_0 ,\n \\not_strict_mode.app_rd_data_reg[236]_0 ,\n \\not_strict_mode.app_rd_data_reg[244]_0 ,\n \\not_strict_mode.app_rd_data_reg[228]_0 ,\n \\not_strict_mode.app_rd_data_reg[251] ,\n \\not_strict_mode.app_rd_data_reg[235] ,\n \\not_strict_mode.app_rd_data_reg[243] ,\n \\not_strict_mode.app_rd_data_reg[227] ,\n \\not_strict_mode.app_rd_data_reg[250] ,\n \\not_strict_mode.app_rd_data_reg[234] ,\n \\not_strict_mode.app_rd_data_reg[242] ,\n \\not_strict_mode.app_rd_data_reg[226] ,\n \\not_strict_mode.app_rd_data_reg[249] ,\n \\not_strict_mode.app_rd_data_reg[233] ,\n \\not_strict_mode.app_rd_data_reg[241] ,\n \\not_strict_mode.app_rd_data_reg[225] ,\n \\not_strict_mode.app_rd_data_reg[248] ,\n \\not_strict_mode.app_rd_data_reg[232] ,\n \\not_strict_mode.app_rd_data_reg[240] ,\n \\not_strict_mode.app_rd_data_reg[224] ,\n \\not_strict_mode.app_rd_data_reg[223] ,\n \\not_strict_mode.app_rd_data_reg[207] ,\n \\not_strict_mode.app_rd_data_reg[215] ,\n \\not_strict_mode.app_rd_data_reg[199] ,\n \\not_strict_mode.app_rd_data_reg[222] ,\n \\not_strict_mode.app_rd_data_reg[206] ,\n \\not_strict_mode.app_rd_data_reg[214] ,\n \\not_strict_mode.app_rd_data_reg[198] ,\n \\not_strict_mode.app_rd_data_reg[221] ,\n \\not_strict_mode.app_rd_data_reg[205] ,\n \\not_strict_mode.app_rd_data_reg[213] ,\n \\not_strict_mode.app_rd_data_reg[197] ,\n \\not_strict_mode.app_rd_data_reg[220] ,\n \\not_strict_mode.app_rd_data_reg[204] ,\n \\not_strict_mode.app_rd_data_reg[212] ,\n \\not_strict_mode.app_rd_data_reg[196] ,\n \\not_strict_mode.app_rd_data_reg[219] ,\n \\not_strict_mode.app_rd_data_reg[203] ,\n \\not_strict_mode.app_rd_data_reg[211] ,\n \\not_strict_mode.app_rd_data_reg[195] ,\n \\not_strict_mode.app_rd_data_reg[218] ,\n \\not_strict_mode.app_rd_data_reg[202] ,\n \\not_strict_mode.app_rd_data_reg[210] ,\n \\not_strict_mode.app_rd_data_reg[194] ,\n \\not_strict_mode.app_rd_data_reg[217] ,\n \\not_strict_mode.app_rd_data_reg[201] ,\n \\not_strict_mode.app_rd_data_reg[209] ,\n \\not_strict_mode.app_rd_data_reg[193] ,\n \\not_strict_mode.app_rd_data_reg[216] ,\n \\not_strict_mode.app_rd_data_reg[200] ,\n \\not_strict_mode.app_rd_data_reg[208] ,\n \\not_strict_mode.app_rd_data_reg[192] ,\n \\not_strict_mode.app_rd_data_reg[191] ,\n \\not_strict_mode.app_rd_data_reg[175] ,\n \\not_strict_mode.app_rd_data_reg[183] ,\n \\not_strict_mode.app_rd_data_reg[167] ,\n \\not_strict_mode.app_rd_data_reg[190] ,\n \\not_strict_mode.app_rd_data_reg[174] ,\n \\not_strict_mode.app_rd_data_reg[182] ,\n \\not_strict_mode.app_rd_data_reg[166] ,\n \\not_strict_mode.app_rd_data_reg[189] ,\n \\not_strict_mode.app_rd_data_reg[173] ,\n \\not_strict_mode.app_rd_data_reg[181] ,\n \\not_strict_mode.app_rd_data_reg[165] ,\n \\not_strict_mode.app_rd_data_reg[188] ,\n \\not_strict_mode.app_rd_data_reg[172] ,\n \\not_strict_mode.app_rd_data_reg[180] ,\n \\not_strict_mode.app_rd_data_reg[164] ,\n \\not_strict_mode.app_rd_data_reg[187] ,\n \\not_strict_mode.app_rd_data_reg[171] ,\n \\not_strict_mode.app_rd_data_reg[179] ,\n \\not_strict_mode.app_rd_data_reg[163] ,\n \\not_strict_mode.app_rd_data_reg[186] ,\n \\not_strict_mode.app_rd_data_reg[170] ,\n \\not_strict_mode.app_rd_data_reg[178] ,\n \\not_strict_mode.app_rd_data_reg[162] ,\n \\not_strict_mode.app_rd_data_reg[185] ,\n \\not_strict_mode.app_rd_data_reg[169] ,\n \\not_strict_mode.app_rd_data_reg[177] ,\n \\not_strict_mode.app_rd_data_reg[161] ,\n \\not_strict_mode.app_rd_data_reg[184] ,\n \\not_strict_mode.app_rd_data_reg[168] ,\n \\not_strict_mode.app_rd_data_reg[176] ,\n \\not_strict_mode.app_rd_data_reg[160] ,\n \\not_strict_mode.app_rd_data_reg[159] ,\n \\not_strict_mode.app_rd_data_reg[143] ,\n \\not_strict_mode.app_rd_data_reg[151] ,\n \\not_strict_mode.app_rd_data_reg[135] ,\n \\not_strict_mode.app_rd_data_reg[158] ,\n \\not_strict_mode.app_rd_data_reg[142] ,\n \\not_strict_mode.app_rd_data_reg[150] ,\n \\not_strict_mode.app_rd_data_reg[134] ,\n \\not_strict_mode.app_rd_data_reg[157] ,\n \\not_strict_mode.app_rd_data_reg[141] ,\n \\not_strict_mode.app_rd_data_reg[149] ,\n \\not_strict_mode.app_rd_data_reg[133] ,\n \\not_strict_mode.app_rd_data_reg[156] ,\n \\not_strict_mode.app_rd_data_reg[140] ,\n \\not_strict_mode.app_rd_data_reg[148] ,\n \\not_strict_mode.app_rd_data_reg[132] ,\n \\not_strict_mode.app_rd_data_reg[155] ,\n \\not_strict_mode.app_rd_data_reg[139] ,\n \\not_strict_mode.app_rd_data_reg[147] ,\n \\not_strict_mode.app_rd_data_reg[131] ,\n \\not_strict_mode.app_rd_data_reg[154] ,\n \\not_strict_mode.app_rd_data_reg[138] ,\n \\not_strict_mode.app_rd_data_reg[146] ,\n \\not_strict_mode.app_rd_data_reg[130] ,\n \\not_strict_mode.app_rd_data_reg[153] ,\n \\not_strict_mode.app_rd_data_reg[137] ,\n \\not_strict_mode.app_rd_data_reg[145] ,\n \\not_strict_mode.app_rd_data_reg[129] ,\n \\not_strict_mode.app_rd_data_reg[152] ,\n \\not_strict_mode.app_rd_data_reg[136] ,\n \\not_strict_mode.app_rd_data_reg[144] ,\n \\not_strict_mode.app_rd_data_reg[128] ,\n \\not_strict_mode.app_rd_data_reg[127] ,\n \\not_strict_mode.app_rd_data_reg[111] ,\n \\not_strict_mode.app_rd_data_reg[119] ,\n \\not_strict_mode.app_rd_data_reg[103] ,\n \\not_strict_mode.app_rd_data_reg[126] ,\n \\not_strict_mode.app_rd_data_reg[110] ,\n \\not_strict_mode.app_rd_data_reg[118] ,\n \\not_strict_mode.app_rd_data_reg[102] ,\n \\not_strict_mode.app_rd_data_reg[125] ,\n \\not_strict_mode.app_rd_data_reg[109] ,\n \\not_strict_mode.app_rd_data_reg[117] ,\n \\not_strict_mode.app_rd_data_reg[101] ,\n \\not_strict_mode.app_rd_data_reg[124] ,\n \\not_strict_mode.app_rd_data_reg[108] ,\n \\not_strict_mode.app_rd_data_reg[116] ,\n \\not_strict_mode.app_rd_data_reg[100] ,\n \\not_strict_mode.app_rd_data_reg[123] ,\n \\not_strict_mode.app_rd_data_reg[107] ,\n \\not_strict_mode.app_rd_data_reg[115] ,\n \\not_strict_mode.app_rd_data_reg[99] ,\n \\not_strict_mode.app_rd_data_reg[122] ,\n \\not_strict_mode.app_rd_data_reg[106] ,\n \\not_strict_mode.app_rd_data_reg[114] ,\n \\not_strict_mode.app_rd_data_reg[98] ,\n \\not_strict_mode.app_rd_data_reg[121] ,\n \\not_strict_mode.app_rd_data_reg[105] ,\n \\not_strict_mode.app_rd_data_reg[113] ,\n \\not_strict_mode.app_rd_data_reg[97] ,\n \\not_strict_mode.app_rd_data_reg[120] ,\n \\not_strict_mode.app_rd_data_reg[104] ,\n \\not_strict_mode.app_rd_data_reg[112] ,\n \\not_strict_mode.app_rd_data_reg[96] ,\n \\not_strict_mode.app_rd_data_reg[95] ,\n \\not_strict_mode.app_rd_data_reg[79] ,\n \\not_strict_mode.app_rd_data_reg[87] ,\n \\not_strict_mode.app_rd_data_reg[71] ,\n \\not_strict_mode.app_rd_data_reg[94] ,\n \\not_strict_mode.app_rd_data_reg[78] ,\n \\not_strict_mode.app_rd_data_reg[86] ,\n \\not_strict_mode.app_rd_data_reg[70] ,\n \\not_strict_mode.app_rd_data_reg[93] ,\n \\not_strict_mode.app_rd_data_reg[77] ,\n \\not_strict_mode.app_rd_data_reg[85] ,\n \\not_strict_mode.app_rd_data_reg[69] ,\n \\not_strict_mode.app_rd_data_reg[92] ,\n \\not_strict_mode.app_rd_data_reg[76] ,\n \\not_strict_mode.app_rd_data_reg[84] ,\n \\not_strict_mode.app_rd_data_reg[68] ,\n \\not_strict_mode.app_rd_data_reg[91] ,\n \\not_strict_mode.app_rd_data_reg[75] ,\n \\not_strict_mode.app_rd_data_reg[83] ,\n \\not_strict_mode.app_rd_data_reg[67] ,\n \\not_strict_mode.app_rd_data_reg[90] ,\n \\not_strict_mode.app_rd_data_reg[74] ,\n \\not_strict_mode.app_rd_data_reg[82] ,\n \\not_strict_mode.app_rd_data_reg[66] ,\n \\not_strict_mode.app_rd_data_reg[89] ,\n \\not_strict_mode.app_rd_data_reg[73] ,\n \\not_strict_mode.app_rd_data_reg[81] ,\n \\not_strict_mode.app_rd_data_reg[65] ,\n \\not_strict_mode.app_rd_data_reg[88] ,\n \\not_strict_mode.app_rd_data_reg[72] ,\n \\not_strict_mode.app_rd_data_reg[80] ,\n \\not_strict_mode.app_rd_data_reg[64] ,\n \\not_strict_mode.app_rd_data_reg[63] ,\n \\not_strict_mode.app_rd_data_reg[47] ,\n \\not_strict_mode.app_rd_data_reg[55] ,\n \\not_strict_mode.app_rd_data_reg[39] ,\n \\not_strict_mode.app_rd_data_reg[62] ,\n \\not_strict_mode.app_rd_data_reg[46] ,\n \\not_strict_mode.app_rd_data_reg[54] ,\n \\not_strict_mode.app_rd_data_reg[38] ,\n \\not_strict_mode.app_rd_data_reg[61] ,\n \\not_strict_mode.app_rd_data_reg[45] ,\n \\not_strict_mode.app_rd_data_reg[53] ,\n \\not_strict_mode.app_rd_data_reg[37] ,\n \\not_strict_mode.app_rd_data_reg[60] ,\n \\not_strict_mode.app_rd_data_reg[44] ,\n \\not_strict_mode.app_rd_data_reg[52] ,\n \\not_strict_mode.app_rd_data_reg[36] ,\n \\not_strict_mode.app_rd_data_reg[59] ,\n \\not_strict_mode.app_rd_data_reg[43] ,\n \\not_strict_mode.app_rd_data_reg[51] ,\n \\not_strict_mode.app_rd_data_reg[35] ,\n \\not_strict_mode.app_rd_data_reg[58] ,\n \\not_strict_mode.app_rd_data_reg[42] ,\n \\not_strict_mode.app_rd_data_reg[50] ,\n \\not_strict_mode.app_rd_data_reg[34] ,\n \\not_strict_mode.app_rd_data_reg[57] ,\n \\not_strict_mode.app_rd_data_reg[41] ,\n \\not_strict_mode.app_rd_data_reg[49] ,\n \\not_strict_mode.app_rd_data_reg[33] ,\n \\not_strict_mode.app_rd_data_reg[56] ,\n \\not_strict_mode.app_rd_data_reg[40] ,\n \\not_strict_mode.app_rd_data_reg[48] ,\n \\not_strict_mode.app_rd_data_reg[32] ,\n \\not_strict_mode.app_rd_data_reg[31] ,\n \\not_strict_mode.app_rd_data_reg[15] ,\n \\not_strict_mode.app_rd_data_reg[23] ,\n \\not_strict_mode.app_rd_data_reg[7] ,\n \\not_strict_mode.app_rd_data_reg[30] ,\n \\not_strict_mode.app_rd_data_reg[14] ,\n \\not_strict_mode.app_rd_data_reg[22] ,\n \\not_strict_mode.app_rd_data_reg[6] ,\n \\not_strict_mode.app_rd_data_reg[29] ,\n \\not_strict_mode.app_rd_data_reg[13] ,\n \\not_strict_mode.app_rd_data_reg[21] ,\n \\not_strict_mode.app_rd_data_reg[5] ,\n \\not_strict_mode.app_rd_data_reg[28] ,\n \\not_strict_mode.app_rd_data_reg[12] ,\n \\not_strict_mode.app_rd_data_reg[20] ,\n \\not_strict_mode.app_rd_data_reg[4] ,\n \\not_strict_mode.app_rd_data_reg[27] ,\n \\not_strict_mode.app_rd_data_reg[11] ,\n \\not_strict_mode.app_rd_data_reg[19] ,\n \\not_strict_mode.app_rd_data_reg[3] ,\n \\not_strict_mode.app_rd_data_reg[26] ,\n \\not_strict_mode.app_rd_data_reg[10] ,\n \\not_strict_mode.app_rd_data_reg[18] ,\n \\not_strict_mode.app_rd_data_reg[2] ,\n \\not_strict_mode.app_rd_data_reg[25] ,\n \\not_strict_mode.app_rd_data_reg[9] ,\n \\not_strict_mode.app_rd_data_reg[17] ,\n \\not_strict_mode.app_rd_data_reg[1] ,\n \\not_strict_mode.app_rd_data_reg[24] ,\n \\not_strict_mode.app_rd_data_reg[8] ,\n \\not_strict_mode.app_rd_data_reg[16] ,\n \\not_strict_mode.app_rd_data_reg[0] ,\n \\read_fifo.tail_r_reg[0] ,\n \\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,\n \\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,\n \\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,\n \\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,\n \\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,\n \\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,\n \\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,\n \\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,\n \\not_strict_mode.app_rd_data_reg[255]_0 ,\n of_ctl_full_v,\n pi_phase_locked_all_r1_reg,\n \\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ,\n \\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ,\n \\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ,\n \\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ,\n \\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ,\n \\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ,\n \\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ,\n \\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ,\n wr_en,\n wr_en_5,\n wr_en_6,\n \\not_strict_mode.app_rd_data_reg[31]_0 ,\n \\not_strict_mode.app_rd_data_reg[31]_1 ,\n \\my_empty_reg[7] ,\n \\not_strict_mode.app_rd_data_reg[23]_0 ,\n \\not_strict_mode.app_rd_data_reg[23]_1 ,\n \\my_empty_reg[7]_0 ,\n \\not_strict_mode.app_rd_data_reg[15]_0 ,\n \\not_strict_mode.app_rd_data_reg[15]_1 ,\n \\my_empty_reg[7]_1 ,\n \\not_strict_mode.app_rd_data_reg[7]_0 ,\n \\not_strict_mode.app_rd_data_reg[7]_1 ,\n \\my_empty_reg[7]_2 ,\n ofs_rdy_r_reg,\n ofs_rdy_r_reg_0,\n \\po_rdval_cnt_reg[8] ,\n \\pi_rdval_cnt_reg[5] ,\n \\wr_ptr_timing_reg[2] ,\n \\wr_ptr_timing_reg[2]_0 ,\n \\wr_ptr_timing_reg[2]_1 ,\n \\po_rdval_cnt_reg[8]_0 ,\n phy_if_empty_r_reg,\n p_0_out,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,\n \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,\n \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,\n \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,\n \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,\n ddr_ck_out,\n \\my_empty_reg[7]_3 ,\n CLK,\n init_calib_complete_reg_rep__6,\n D5,\n D6,\n D2,\n D3,\n \\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ,\n \\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ,\n D7,\n D8,\n D9,\n D0,\n D1,\n \\calib_sel_reg[0] ,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n \\calib_sel_reg[0]_0 ,\n \\calib_sel_reg[0]_1 ,\n freq_refclk,\n mem_refclk,\n \\calib_sel_reg[0]_2 ,\n sync_pulse,\n \\calib_sel_reg[1] ,\n \\gen_byte_sel_div1.calib_in_common_reg_0 ,\n \\calib_sel_reg[1]_0 ,\n \\calib_sel_reg[1]_1 ,\n \\calib_sel_reg[1]_2 ,\n \\calib_sel_reg[1]_3 ,\n \\gen_byte_sel_div1.calib_in_common_reg_1 ,\n \\calib_sel_reg[1]_4 ,\n \\calib_sel_reg[1]_5 ,\n \\calib_sel_reg[1]_6 ,\n phy_ctl_wr_i2,\n pll_locked,\n phy_read_calib,\n in0,\n phy_write_calib,\n Q,\n \\data_offset_1_i2_reg[5] ,\n \\gen_byte_sel_div1.calib_in_common_reg_2 ,\n \\calib_sel_reg[0]_3 ,\n pi_en_stg2_f_reg,\n pi_stg2_f_incdec_reg,\n mem_dqs_in,\n \\gen_byte_sel_div1.calib_in_common_reg_3 ,\n COUNTERLOADVAL,\n \\gen_byte_sel_div1.calib_in_common_reg_4 ,\n ck_po_stg2_f_en_reg,\n ck_po_stg2_f_indec_reg,\n delay_done_r4_reg,\n \\write_buffer.wr_buf_out_data_reg[255] ,\n \\write_buffer.wr_buf_out_data_reg[254] ,\n \\write_buffer.wr_buf_out_data_reg[253] ,\n \\write_buffer.wr_buf_out_data_reg[252] ,\n \\write_buffer.wr_buf_out_data_reg[251] ,\n \\write_buffer.wr_buf_out_data_reg[250] ,\n \\write_buffer.wr_buf_out_data_reg[249] ,\n \\write_buffer.wr_buf_out_data_reg[248] ,\n \\gen_byte_sel_div1.calib_in_common_reg_5 ,\n mem_dq_in,\n idelay_inc,\n LD0,\n CLKB0,\n phy_if_reset,\n \\gen_byte_sel_div1.calib_in_common_reg_6 ,\n \\calib_sel_reg[0]_4 ,\n pi_en_stg2_f_reg_0,\n pi_stg2_f_incdec_reg_0,\n \\gen_byte_sel_div1.calib_in_common_reg_7 ,\n \\calib_zero_inputs_reg[0] ,\n \\gen_byte_sel_div1.calib_in_common_reg_8 ,\n ck_po_stg2_f_en_reg_0,\n ck_po_stg2_f_indec_reg_0,\n delay_done_r4_reg_0,\n \\write_buffer.wr_buf_out_data_reg[247] ,\n \\write_buffer.wr_buf_out_data_reg[246] ,\n \\write_buffer.wr_buf_out_data_reg[245] ,\n \\write_buffer.wr_buf_out_data_reg[244] ,\n \\write_buffer.wr_buf_out_data_reg[243] ,\n \\write_buffer.wr_buf_out_data_reg[242] ,\n \\write_buffer.wr_buf_out_data_reg[241] ,\n \\write_buffer.wr_buf_out_data_reg[240] ,\n \\gen_byte_sel_div1.calib_in_common_reg_9 ,\n LD0_3,\n CLKB0_7,\n \\gen_byte_sel_div1.calib_in_common_reg_10 ,\n \\calib_sel_reg[1]_7 ,\n pi_en_stg2_f_reg_1,\n pi_stg2_f_incdec_reg_1,\n \\gen_byte_sel_div1.calib_in_common_reg_11 ,\n \\calib_zero_inputs_reg[0]_0 ,\n \\gen_byte_sel_div1.calib_in_common_reg_12 ,\n ck_po_stg2_f_en_reg_1,\n ck_po_stg2_f_indec_reg_1,\n delay_done_r4_reg_1,\n \\write_buffer.wr_buf_out_data_reg[239] ,\n \\write_buffer.wr_buf_out_data_reg[238] ,\n \\write_buffer.wr_buf_out_data_reg[237] ,\n \\write_buffer.wr_buf_out_data_reg[236] ,\n \\write_buffer.wr_buf_out_data_reg[235] ,\n \\write_buffer.wr_buf_out_data_reg[234] ,\n \\write_buffer.wr_buf_out_data_reg[233] ,\n \\write_buffer.wr_buf_out_data_reg[232] ,\n \\gen_byte_sel_div1.calib_in_common_reg_13 ,\n LD0_4,\n CLKB0_8,\n \\gen_byte_sel_div1.calib_in_common_reg_14 ,\n \\calib_sel_reg[0]_5 ,\n pi_en_stg2_f_reg_2,\n pi_stg2_f_incdec_reg_2,\n \\gen_byte_sel_div1.calib_in_common_reg_15 ,\n \\calib_zero_inputs_reg[0]_1 ,\n \\gen_byte_sel_div1.calib_in_common_reg_16 ,\n ck_po_stg2_f_en_reg_2,\n ck_po_stg2_f_indec_reg_2,\n delay_done_r4_reg_2,\n \\write_buffer.wr_buf_out_data_reg[231] ,\n \\write_buffer.wr_buf_out_data_reg[230] ,\n \\write_buffer.wr_buf_out_data_reg[229] ,\n \\write_buffer.wr_buf_out_data_reg[228] ,\n \\write_buffer.wr_buf_out_data_reg[227] ,\n \\write_buffer.wr_buf_out_data_reg[226] ,\n \\write_buffer.wr_buf_out_data_reg[225] ,\n \\write_buffer.wr_buf_out_data_reg[224] ,\n \\gen_byte_sel_div1.calib_in_common_reg_17 ,\n LD0_5,\n CLKB0_9,\n RST0,\n rstdiv0_sync_r1_reg_rep__9,\n mux_cmd_wren,\n mem_out,\n \\rd_ptr_reg[3] ,\n mux_wrdata_en,\n \\rd_ptr_reg[3]_0 ,\n \\read_fifo.fifo_out_data_r_reg[6] ,\n ram_init_done_r,\n init_calib_complete_reg_rep__5,\n mc_cas_n,\n \\cmd_pipe_plus.mc_address_reg[43] ,\n init_calib_complete_reg_rep,\n \\write_buffer.wr_buf_out_data_reg[287] ,\n prbs_rdlvl_start_reg,\n out,\n sys_rst,\n \\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ,\n mmcm_locked,\n \\byte_r_reg[0]_0 ,\n \\byte_r_reg[1] ,\n tail_r,\n \\rd_mux_sel_r_reg[1] ,\n \\read_fifo.fifo_out_data_r_reg[6]_0 ,\n DOC,\n DOB,\n DOA,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ,\n A,\n mux_wrdata,\n mux_wrdata_mask,\n E,\n \\fine_delay_mod_reg[23] ,\n \\gen_byte_sel_div1.calib_in_common_reg_18 ,\n \\calib_sel_reg[0]_6 ,\n \\gen_byte_sel_div1.calib_in_common_reg_19 ,\n \\calib_sel_reg[1]_8 ,\n \\gen_byte_sel_div1.calib_in_common_reg_20 ,\n \\calib_sel_reg[0]_7 ,\n \\calib_sel_reg[3] ,\n \\po_stg2_wrcal_cnt_reg[1] ,\n D_po_coarse_enable110_out,\n D_po_counter_read_en122_out,\n D_po_fine_enable107_out,\n D_po_fine_inc113_out,\n D_po_sel_fine_oclk_delay125_out,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ,\n D4,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ,\n phy_dout,\n init_calib_complete_reg_rep__6_0);\n output \\rd_ptr_timing_reg[2] ;\n output \\rd_ptr_timing_reg[2]_0 ;\n output \\rd_ptr_timing_reg[2]_1 ;\n output \\rd_ptr_timing_reg[2]_2 ;\n output \\rd_ptr_timing_reg[2]_3 ;\n output \\rd_ptr_timing_reg[2]_4 ;\n output \\rd_ptr_timing_reg[2]_5 ;\n output \\rd_ptr_timing_reg[2]_6 ;\n output \\rd_ptr_timing_reg[2]_7 ;\n output \\rd_ptr_timing_reg[2]_8 ;\n output \\rd_ptr_timing_reg[2]_9 ;\n output \\rd_ptr_timing_reg[2]_10 ;\n output [3:0]\\pi_dqs_found_lanes_r1_reg[3] ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n output [3:0]mem_dqs_out;\n output [3:0]mem_dqs_ts;\n output [59:0]mem_dq_out;\n output [35:0]mem_dq_ts;\n output idelay_ld_rst;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n output idelay_ld_rst_0;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;\n output idelay_ld_rst_1;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;\n output idelay_ld_rst_2;\n output \\calib_seq_reg[0] ;\n output \\not_strict_mode.app_rd_data_reg[252] ;\n output \\not_strict_mode.app_rd_data_reg[244] ;\n output \\not_strict_mode.app_rd_data_reg[236] ;\n output \\not_strict_mode.app_rd_data_reg[228] ;\n output \\my_empty_reg[1] ;\n output \\my_empty_reg[1]_0 ;\n output phy_mc_ctl_full;\n output \\my_empty_reg[1]_1 ;\n output \\my_empty_reg[1]_2 ;\n output \\my_empty_reg[1]_3 ;\n output \\my_empty_reg[1]_4 ;\n output \\my_empty_reg[1]_5 ;\n output rd_buf_we;\n output \\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n output \\my_empty_reg[1]_6 ;\n output phy_rddata_en;\n output mux_rd_valid_r_reg;\n output rst_sync_r1_reg;\n output \\byte_r_reg[0] ;\n output [5:0]\\po_counter_read_val_r_reg[5] ;\n output [63:0]\\data_bytes_r_reg[63] ;\n output \\not_strict_mode.app_rd_data_reg[255] ;\n output \\not_strict_mode.app_rd_data_reg[239] ;\n output \\not_strict_mode.app_rd_data_reg[247] ;\n output \\not_strict_mode.app_rd_data_reg[231] ;\n output \\not_strict_mode.app_rd_data_reg[254] ;\n output \\not_strict_mode.app_rd_data_reg[238] ;\n output \\not_strict_mode.app_rd_data_reg[246] ;\n output \\not_strict_mode.app_rd_data_reg[230] ;\n output \\not_strict_mode.app_rd_data_reg[253] ;\n output \\not_strict_mode.app_rd_data_reg[237] ;\n output \\not_strict_mode.app_rd_data_reg[245] ;\n output \\not_strict_mode.app_rd_data_reg[229] ;\n output \\not_strict_mode.app_rd_data_reg[252]_0 ;\n output \\not_strict_mode.app_rd_data_reg[236]_0 ;\n output \\not_strict_mode.app_rd_data_reg[244]_0 ;\n output \\not_strict_mode.app_rd_data_reg[228]_0 ;\n output \\not_strict_mode.app_rd_data_reg[251] ;\n output \\not_strict_mode.app_rd_data_reg[235] ;\n output \\not_strict_mode.app_rd_data_reg[243] ;\n output \\not_strict_mode.app_rd_data_reg[227] ;\n output \\not_strict_mode.app_rd_data_reg[250] ;\n output \\not_strict_mode.app_rd_data_reg[234] ;\n output \\not_strict_mode.app_rd_data_reg[242] ;\n output \\not_strict_mode.app_rd_data_reg[226] ;\n output \\not_strict_mode.app_rd_data_reg[249] ;\n output \\not_strict_mode.app_rd_data_reg[233] ;\n output \\not_strict_mode.app_rd_data_reg[241] ;\n output \\not_strict_mode.app_rd_data_reg[225] ;\n output \\not_strict_mode.app_rd_data_reg[248] ;\n output \\not_strict_mode.app_rd_data_reg[232] ;\n output \\not_strict_mode.app_rd_data_reg[240] ;\n output \\not_strict_mode.app_rd_data_reg[224] ;\n output \\not_strict_mode.app_rd_data_reg[223] ;\n output \\not_strict_mode.app_rd_data_reg[207] ;\n output \\not_strict_mode.app_rd_data_reg[215] ;\n output \\not_strict_mode.app_rd_data_reg[199] ;\n output \\not_strict_mode.app_rd_data_reg[222] ;\n output \\not_strict_mode.app_rd_data_reg[206] ;\n output \\not_strict_mode.app_rd_data_reg[214] ;\n output \\not_strict_mode.app_rd_data_reg[198] ;\n output \\not_strict_mode.app_rd_data_reg[221] ;\n output \\not_strict_mode.app_rd_data_reg[205] ;\n output \\not_strict_mode.app_rd_data_reg[213] ;\n output \\not_strict_mode.app_rd_data_reg[197] ;\n output \\not_strict_mode.app_rd_data_reg[220] ;\n output \\not_strict_mode.app_rd_data_reg[204] ;\n output \\not_strict_mode.app_rd_data_reg[212] ;\n output \\not_strict_mode.app_rd_data_reg[196] ;\n output \\not_strict_mode.app_rd_data_reg[219] ;\n output \\not_strict_mode.app_rd_data_reg[203] ;\n output \\not_strict_mode.app_rd_data_reg[211] ;\n output \\not_strict_mode.app_rd_data_reg[195] ;\n output \\not_strict_mode.app_rd_data_reg[218] ;\n output \\not_strict_mode.app_rd_data_reg[202] ;\n output \\not_strict_mode.app_rd_data_reg[210] ;\n output \\not_strict_mode.app_rd_data_reg[194] ;\n output \\not_strict_mode.app_rd_data_reg[217] ;\n output \\not_strict_mode.app_rd_data_reg[201] ;\n output \\not_strict_mode.app_rd_data_reg[209] ;\n output \\not_strict_mode.app_rd_data_reg[193] ;\n output \\not_strict_mode.app_rd_data_reg[216] ;\n output \\not_strict_mode.app_rd_data_reg[200] ;\n output \\not_strict_mode.app_rd_data_reg[208] ;\n output \\not_strict_mode.app_rd_data_reg[192] ;\n output \\not_strict_mode.app_rd_data_reg[191] ;\n output \\not_strict_mode.app_rd_data_reg[175] ;\n output \\not_strict_mode.app_rd_data_reg[183] ;\n output \\not_strict_mode.app_rd_data_reg[167] ;\n output \\not_strict_mode.app_rd_data_reg[190] ;\n output \\not_strict_mode.app_rd_data_reg[174] ;\n output \\not_strict_mode.app_rd_data_reg[182] ;\n output \\not_strict_mode.app_rd_data_reg[166] ;\n output \\not_strict_mode.app_rd_data_reg[189] ;\n output \\not_strict_mode.app_rd_data_reg[173] ;\n output \\not_strict_mode.app_rd_data_reg[181] ;\n output \\not_strict_mode.app_rd_data_reg[165] ;\n output \\not_strict_mode.app_rd_data_reg[188] ;\n output \\not_strict_mode.app_rd_data_reg[172] ;\n output \\not_strict_mode.app_rd_data_reg[180] ;\n output \\not_strict_mode.app_rd_data_reg[164] ;\n output \\not_strict_mode.app_rd_data_reg[187] ;\n output \\not_strict_mode.app_rd_data_reg[171] ;\n output \\not_strict_mode.app_rd_data_reg[179] ;\n output \\not_strict_mode.app_rd_data_reg[163] ;\n output \\not_strict_mode.app_rd_data_reg[186] ;\n output \\not_strict_mode.app_rd_data_reg[170] ;\n output \\not_strict_mode.app_rd_data_reg[178] ;\n output \\not_strict_mode.app_rd_data_reg[162] ;\n output \\not_strict_mode.app_rd_data_reg[185] ;\n output \\not_strict_mode.app_rd_data_reg[169] ;\n output \\not_strict_mode.app_rd_data_reg[177] ;\n output \\not_strict_mode.app_rd_data_reg[161] ;\n output \\not_strict_mode.app_rd_data_reg[184] ;\n output \\not_strict_mode.app_rd_data_reg[168] ;\n output \\not_strict_mode.app_rd_data_reg[176] ;\n output \\not_strict_mode.app_rd_data_reg[160] ;\n output \\not_strict_mode.app_rd_data_reg[159] ;\n output \\not_strict_mode.app_rd_data_reg[143] ;\n output \\not_strict_mode.app_rd_data_reg[151] ;\n output \\not_strict_mode.app_rd_data_reg[135] ;\n output \\not_strict_mode.app_rd_data_reg[158] ;\n output \\not_strict_mode.app_rd_data_reg[142] ;\n output \\not_strict_mode.app_rd_data_reg[150] ;\n output \\not_strict_mode.app_rd_data_reg[134] ;\n output \\not_strict_mode.app_rd_data_reg[157] ;\n output \\not_strict_mode.app_rd_data_reg[141] ;\n output \\not_strict_mode.app_rd_data_reg[149] ;\n output \\not_strict_mode.app_rd_data_reg[133] ;\n output \\not_strict_mode.app_rd_data_reg[156] ;\n output \\not_strict_mode.app_rd_data_reg[140] ;\n output \\not_strict_mode.app_rd_data_reg[148] ;\n output \\not_strict_mode.app_rd_data_reg[132] ;\n output \\not_strict_mode.app_rd_data_reg[155] ;\n output \\not_strict_mode.app_rd_data_reg[139] ;\n output \\not_strict_mode.app_rd_data_reg[147] ;\n output \\not_strict_mode.app_rd_data_reg[131] ;\n output \\not_strict_mode.app_rd_data_reg[154] ;\n output \\not_strict_mode.app_rd_data_reg[138] ;\n output \\not_strict_mode.app_rd_data_reg[146] ;\n output \\not_strict_mode.app_rd_data_reg[130] ;\n output \\not_strict_mode.app_rd_data_reg[153] ;\n output \\not_strict_mode.app_rd_data_reg[137] ;\n output \\not_strict_mode.app_rd_data_reg[145] ;\n output \\not_strict_mode.app_rd_data_reg[129] ;\n output \\not_strict_mode.app_rd_data_reg[152] ;\n output \\not_strict_mode.app_rd_data_reg[136] ;\n output \\not_strict_mode.app_rd_data_reg[144] ;\n output \\not_strict_mode.app_rd_data_reg[128] ;\n output \\not_strict_mode.app_rd_data_reg[127] ;\n output \\not_strict_mode.app_rd_data_reg[111] ;\n output \\not_strict_mode.app_rd_data_reg[119] ;\n output \\not_strict_mode.app_rd_data_reg[103] ;\n output \\not_strict_mode.app_rd_data_reg[126] ;\n output \\not_strict_mode.app_rd_data_reg[110] ;\n output \\not_strict_mode.app_rd_data_reg[118] ;\n output \\not_strict_mode.app_rd_data_reg[102] ;\n output \\not_strict_mode.app_rd_data_reg[125] ;\n output \\not_strict_mode.app_rd_data_reg[109] ;\n output \\not_strict_mode.app_rd_data_reg[117] ;\n output \\not_strict_mode.app_rd_data_reg[101] ;\n output \\not_strict_mode.app_rd_data_reg[124] ;\n output \\not_strict_mode.app_rd_data_reg[108] ;\n output \\not_strict_mode.app_rd_data_reg[116] ;\n output \\not_strict_mode.app_rd_data_reg[100] ;\n output \\not_strict_mode.app_rd_data_reg[123] ;\n output \\not_strict_mode.app_rd_data_reg[107] ;\n output \\not_strict_mode.app_rd_data_reg[115] ;\n output \\not_strict_mode.app_rd_data_reg[99] ;\n output \\not_strict_mode.app_rd_data_reg[122] ;\n output \\not_strict_mode.app_rd_data_reg[106] ;\n output \\not_strict_mode.app_rd_data_reg[114] ;\n output \\not_strict_mode.app_rd_data_reg[98] ;\n output \\not_strict_mode.app_rd_data_reg[121] ;\n output \\not_strict_mode.app_rd_data_reg[105] ;\n output \\not_strict_mode.app_rd_data_reg[113] ;\n output \\not_strict_mode.app_rd_data_reg[97] ;\n output \\not_strict_mode.app_rd_data_reg[120] ;\n output \\not_strict_mode.app_rd_data_reg[104] ;\n output \\not_strict_mode.app_rd_data_reg[112] ;\n output \\not_strict_mode.app_rd_data_reg[96] ;\n output \\not_strict_mode.app_rd_data_reg[95] ;\n output \\not_strict_mode.app_rd_data_reg[79] ;\n output \\not_strict_mode.app_rd_data_reg[87] ;\n output \\not_strict_mode.app_rd_data_reg[71] ;\n output \\not_strict_mode.app_rd_data_reg[94] ;\n output \\not_strict_mode.app_rd_data_reg[78] ;\n output \\not_strict_mode.app_rd_data_reg[86] ;\n output \\not_strict_mode.app_rd_data_reg[70] ;\n output \\not_strict_mode.app_rd_data_reg[93] ;\n output \\not_strict_mode.app_rd_data_reg[77] ;\n output \\not_strict_mode.app_rd_data_reg[85] ;\n output \\not_strict_mode.app_rd_data_reg[69] ;\n output \\not_strict_mode.app_rd_data_reg[92] ;\n output \\not_strict_mode.app_rd_data_reg[76] ;\n output \\not_strict_mode.app_rd_data_reg[84] ;\n output \\not_strict_mode.app_rd_data_reg[68] ;\n output \\not_strict_mode.app_rd_data_reg[91] ;\n output \\not_strict_mode.app_rd_data_reg[75] ;\n output \\not_strict_mode.app_rd_data_reg[83] ;\n output \\not_strict_mode.app_rd_data_reg[67] ;\n output \\not_strict_mode.app_rd_data_reg[90] ;\n output \\not_strict_mode.app_rd_data_reg[74] ;\n output \\not_strict_mode.app_rd_data_reg[82] ;\n output \\not_strict_mode.app_rd_data_reg[66] ;\n output \\not_strict_mode.app_rd_data_reg[89] ;\n output \\not_strict_mode.app_rd_data_reg[73] ;\n output \\not_strict_mode.app_rd_data_reg[81] ;\n output \\not_strict_mode.app_rd_data_reg[65] ;\n output \\not_strict_mode.app_rd_data_reg[88] ;\n output \\not_strict_mode.app_rd_data_reg[72] ;\n output \\not_strict_mode.app_rd_data_reg[80] ;\n output \\not_strict_mode.app_rd_data_reg[64] ;\n output \\not_strict_mode.app_rd_data_reg[63] ;\n output \\not_strict_mode.app_rd_data_reg[47] ;\n output \\not_strict_mode.app_rd_data_reg[55] ;\n output \\not_strict_mode.app_rd_data_reg[39] ;\n output \\not_strict_mode.app_rd_data_reg[62] ;\n output \\not_strict_mode.app_rd_data_reg[46] ;\n output \\not_strict_mode.app_rd_data_reg[54] ;\n output \\not_strict_mode.app_rd_data_reg[38] ;\n output \\not_strict_mode.app_rd_data_reg[61] ;\n output \\not_strict_mode.app_rd_data_reg[45] ;\n output \\not_strict_mode.app_rd_data_reg[53] ;\n output \\not_strict_mode.app_rd_data_reg[37] ;\n output \\not_strict_mode.app_rd_data_reg[60] ;\n output \\not_strict_mode.app_rd_data_reg[44] ;\n output \\not_strict_mode.app_rd_data_reg[52] ;\n output \\not_strict_mode.app_rd_data_reg[36] ;\n output \\not_strict_mode.app_rd_data_reg[59] ;\n output \\not_strict_mode.app_rd_data_reg[43] ;\n output \\not_strict_mode.app_rd_data_reg[51] ;\n output \\not_strict_mode.app_rd_data_reg[35] ;\n output \\not_strict_mode.app_rd_data_reg[58] ;\n output \\not_strict_mode.app_rd_data_reg[42] ;\n output \\not_strict_mode.app_rd_data_reg[50] ;\n output \\not_strict_mode.app_rd_data_reg[34] ;\n output \\not_strict_mode.app_rd_data_reg[57] ;\n output \\not_strict_mode.app_rd_data_reg[41] ;\n output \\not_strict_mode.app_rd_data_reg[49] ;\n output \\not_strict_mode.app_rd_data_reg[33] ;\n output \\not_strict_mode.app_rd_data_reg[56] ;\n output \\not_strict_mode.app_rd_data_reg[40] ;\n output \\not_strict_mode.app_rd_data_reg[48] ;\n output \\not_strict_mode.app_rd_data_reg[32] ;\n output \\not_strict_mode.app_rd_data_reg[31] ;\n output \\not_strict_mode.app_rd_data_reg[15] ;\n output \\not_strict_mode.app_rd_data_reg[23] ;\n output \\not_strict_mode.app_rd_data_reg[7] ;\n output \\not_strict_mode.app_rd_data_reg[30] ;\n output \\not_strict_mode.app_rd_data_reg[14] ;\n output \\not_strict_mode.app_rd_data_reg[22] ;\n output \\not_strict_mode.app_rd_data_reg[6] ;\n output \\not_strict_mode.app_rd_data_reg[29] ;\n output \\not_strict_mode.app_rd_data_reg[13] ;\n output \\not_strict_mode.app_rd_data_reg[21] ;\n output \\not_strict_mode.app_rd_data_reg[5] ;\n output \\not_strict_mode.app_rd_data_reg[28] ;\n output \\not_strict_mode.app_rd_data_reg[12] ;\n output \\not_strict_mode.app_rd_data_reg[20] ;\n output \\not_strict_mode.app_rd_data_reg[4] ;\n output \\not_strict_mode.app_rd_data_reg[27] ;\n output \\not_strict_mode.app_rd_data_reg[11] ;\n output \\not_strict_mode.app_rd_data_reg[19] ;\n output \\not_strict_mode.app_rd_data_reg[3] ;\n output \\not_strict_mode.app_rd_data_reg[26] ;\n output \\not_strict_mode.app_rd_data_reg[10] ;\n output \\not_strict_mode.app_rd_data_reg[18] ;\n output \\not_strict_mode.app_rd_data_reg[2] ;\n output \\not_strict_mode.app_rd_data_reg[25] ;\n output \\not_strict_mode.app_rd_data_reg[9] ;\n output \\not_strict_mode.app_rd_data_reg[17] ;\n output \\not_strict_mode.app_rd_data_reg[1] ;\n output \\not_strict_mode.app_rd_data_reg[24] ;\n output \\not_strict_mode.app_rd_data_reg[8] ;\n output \\not_strict_mode.app_rd_data_reg[16] ;\n output \\not_strict_mode.app_rd_data_reg[0] ;\n output \\read_fifo.tail_r_reg[0] ;\n output \\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n output \\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n output \\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n output \\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n output \\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n output \\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n output \\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n output \\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n output [255:0]\\not_strict_mode.app_rd_data_reg[255]_0 ;\n output [0:0]of_ctl_full_v;\n output pi_phase_locked_all_r1_reg;\n output \\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ;\n output \\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ;\n output \\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ;\n output \\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ;\n output \\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ;\n output \\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ;\n output \\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ;\n output \\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ;\n output wr_en;\n output wr_en_5;\n output wr_en_6;\n output [0:0]\\not_strict_mode.app_rd_data_reg[31]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[31]_1 ;\n output [63:0]\\my_empty_reg[7] ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[23]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[23]_1 ;\n output [63:0]\\my_empty_reg[7]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[15]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[15]_1 ;\n output [63:0]\\my_empty_reg[7]_1 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[7]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[7]_1 ;\n output [63:0]\\my_empty_reg[7]_2 ;\n output ofs_rdy_r_reg;\n output ofs_rdy_r_reg_0;\n output [4:0]\\po_rdval_cnt_reg[8] ;\n output [5:0]\\pi_rdval_cnt_reg[5] ;\n output [3:0]\\wr_ptr_timing_reg[2] ;\n output [3:0]\\wr_ptr_timing_reg[2]_0 ;\n output [3:0]\\wr_ptr_timing_reg[2]_1 ;\n output [4:0]\\po_rdval_cnt_reg[8]_0 ;\n output phy_if_empty_r_reg;\n output p_0_out;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n output \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n output \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n output \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n output \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n output [1:0]ddr_ck_out;\n output [31:0]\\my_empty_reg[7]_3 ;\n input CLK;\n input [3:0]init_calib_complete_reg_rep__6;\n input [3:0]D5;\n input [3:0]D6;\n input [2:0]D2;\n input [2:0]D3;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ;\n input [7:0]\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ;\n input [7:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ;\n input [3:0]D7;\n input [3:0]D8;\n input [3:0]D9;\n input [2:0]D0;\n input [2:0]D1;\n input \\calib_sel_reg[0] ;\n input \\gen_byte_sel_div1.calib_in_common_reg ;\n input \\calib_sel_reg[0]_0 ;\n input \\calib_sel_reg[0]_1 ;\n input freq_refclk;\n input mem_refclk;\n input \\calib_sel_reg[0]_2 ;\n input sync_pulse;\n input \\calib_sel_reg[1] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n input \\calib_sel_reg[1]_0 ;\n input \\calib_sel_reg[1]_1 ;\n input \\calib_sel_reg[1]_2 ;\n input \\calib_sel_reg[1]_3 ;\n input \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n input \\calib_sel_reg[1]_4 ;\n input \\calib_sel_reg[1]_5 ;\n input \\calib_sel_reg[1]_6 ;\n input phy_ctl_wr_i2;\n input pll_locked;\n input phy_read_calib;\n input in0;\n input phy_write_calib;\n input [10:0]Q;\n input [5:0]\\data_offset_1_i2_reg[5] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n input \\calib_sel_reg[0]_3 ;\n input pi_en_stg2_f_reg;\n input pi_stg2_f_incdec_reg;\n input [3:0]mem_dqs_in;\n input \\gen_byte_sel_div1.calib_in_common_reg_3 ;\n input [5:0]COUNTERLOADVAL;\n input \\gen_byte_sel_div1.calib_in_common_reg_4 ;\n input ck_po_stg2_f_en_reg;\n input ck_po_stg2_f_indec_reg;\n input delay_done_r4_reg;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[255] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[254] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[253] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[252] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[251] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[250] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[249] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[248] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_5 ;\n input [31:0]mem_dq_in;\n input idelay_inc;\n input LD0;\n input CLKB0;\n input phy_if_reset;\n input \\gen_byte_sel_div1.calib_in_common_reg_6 ;\n input \\calib_sel_reg[0]_4 ;\n input pi_en_stg2_f_reg_0;\n input pi_stg2_f_incdec_reg_0;\n input \\gen_byte_sel_div1.calib_in_common_reg_7 ;\n input [5:0]\\calib_zero_inputs_reg[0] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_8 ;\n input ck_po_stg2_f_en_reg_0;\n input ck_po_stg2_f_indec_reg_0;\n input delay_done_r4_reg_0;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[247] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[246] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[245] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[244] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[243] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[242] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[241] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[240] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_9 ;\n input LD0_3;\n input CLKB0_7;\n input \\gen_byte_sel_div1.calib_in_common_reg_10 ;\n input \\calib_sel_reg[1]_7 ;\n input pi_en_stg2_f_reg_1;\n input pi_stg2_f_incdec_reg_1;\n input \\gen_byte_sel_div1.calib_in_common_reg_11 ;\n input [5:0]\\calib_zero_inputs_reg[0]_0 ;\n input \\gen_byte_sel_div1.calib_in_common_reg_12 ;\n input ck_po_stg2_f_en_reg_1;\n input ck_po_stg2_f_indec_reg_1;\n input delay_done_r4_reg_1;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[239] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[238] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[237] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[236] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[235] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[234] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[233] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[232] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_13 ;\n input LD0_4;\n input CLKB0_8;\n input \\gen_byte_sel_div1.calib_in_common_reg_14 ;\n input \\calib_sel_reg[0]_5 ;\n input pi_en_stg2_f_reg_2;\n input pi_stg2_f_incdec_reg_2;\n input \\gen_byte_sel_div1.calib_in_common_reg_15 ;\n input [5:0]\\calib_zero_inputs_reg[0]_1 ;\n input \\gen_byte_sel_div1.calib_in_common_reg_16 ;\n input ck_po_stg2_f_en_reg_2;\n input ck_po_stg2_f_indec_reg_2;\n input delay_done_r4_reg_2;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[231] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[230] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[229] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[228] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[227] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[226] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[225] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[224] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_17 ;\n input LD0_5;\n input CLKB0_9;\n input RST0;\n input rstdiv0_sync_r1_reg_rep__9;\n input mux_cmd_wren;\n input [11:0]mem_out;\n input [33:0]\\rd_ptr_reg[3] ;\n input mux_wrdata_en;\n input [17:0]\\rd_ptr_reg[3]_0 ;\n input [0:0]\\read_fifo.fifo_out_data_r_reg[6] ;\n input ram_init_done_r;\n input init_calib_complete_reg_rep__5;\n input [0:0]mc_cas_n;\n input [1:0]\\cmd_pipe_plus.mc_address_reg[43] ;\n input init_calib_complete_reg_rep;\n input [31:0]\\write_buffer.wr_buf_out_data_reg[287] ;\n input prbs_rdlvl_start_reg;\n input out;\n input sys_rst;\n input [0:0]\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ;\n input mmcm_locked;\n input \\byte_r_reg[0]_0 ;\n input \\byte_r_reg[1] ;\n input [0:0]tail_r;\n input [1:0]\\rd_mux_sel_r_reg[1] ;\n input \\read_fifo.fifo_out_data_r_reg[6]_0 ;\n input [1:0]DOC;\n input [1:0]DOB;\n input [1:0]DOA;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ;\n input [1:0]A;\n input [255:0]mux_wrdata;\n input [31:0]mux_wrdata_mask;\n input [0:0]E;\n input [7:0]\\fine_delay_mod_reg[23] ;\n input [0:0]\\gen_byte_sel_div1.calib_in_common_reg_18 ;\n input [7:0]\\calib_sel_reg[0]_6 ;\n input [0:0]\\gen_byte_sel_div1.calib_in_common_reg_19 ;\n input [7:0]\\calib_sel_reg[1]_8 ;\n input [0:0]\\gen_byte_sel_div1.calib_in_common_reg_20 ;\n input [7:0]\\calib_sel_reg[0]_7 ;\n input [2:0]\\calib_sel_reg[3] ;\n input [1:0]\\po_stg2_wrcal_cnt_reg[1] ;\n input D_po_coarse_enable110_out;\n input D_po_counter_read_en122_out;\n input D_po_fine_enable107_out;\n input D_po_fine_inc113_out;\n input D_po_sel_fine_oclk_delay125_out;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ;\n input [3:0]D4;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ;\n input [35:0]phy_dout;\n input init_calib_complete_reg_rep__6_0;\n\n wire [1:0]A;\n wire CLK;\n wire CLKB0;\n wire CLKB0_7;\n wire CLKB0_8;\n wire CLKB0_9;\n wire [5:0]COUNTERLOADVAL;\n wire [2:0]D0;\n wire [2:0]D1;\n wire [2:0]D2;\n wire [2:0]D3;\n wire [3:0]D4;\n wire [3:0]D5;\n wire [3:0]D6;\n wire [3:0]D7;\n wire [3:0]D8;\n wire [3:0]D9;\n wire [1:0]DOA;\n wire [1:0]DOB;\n wire [1:0]DOC;\n wire D_po_coarse_enable110_out;\n wire D_po_counter_read_en122_out;\n wire D_po_fine_enable107_out;\n wire D_po_fine_inc113_out;\n wire D_po_sel_fine_oclk_delay125_out;\n wire [0:0]E;\n wire LD0;\n wire LD0_3;\n wire LD0_4;\n wire LD0_5;\n wire [10:0]Q;\n wire RST0;\n wire [0:0]_phy_ctl_full_p__0;\n wire \\byte_r_reg[0] ;\n wire \\byte_r_reg[0]_0 ;\n wire \\byte_r_reg[1] ;\n wire \\calib_sel_reg[0] ;\n wire \\calib_sel_reg[0]_0 ;\n wire \\calib_sel_reg[0]_1 ;\n wire \\calib_sel_reg[0]_2 ;\n wire \\calib_sel_reg[0]_3 ;\n wire \\calib_sel_reg[0]_4 ;\n wire \\calib_sel_reg[0]_5 ;\n wire [7:0]\\calib_sel_reg[0]_6 ;\n wire [7:0]\\calib_sel_reg[0]_7 ;\n wire \\calib_sel_reg[1] ;\n wire \\calib_sel_reg[1]_0 ;\n wire \\calib_sel_reg[1]_1 ;\n wire \\calib_sel_reg[1]_2 ;\n wire \\calib_sel_reg[1]_3 ;\n wire \\calib_sel_reg[1]_4 ;\n wire \\calib_sel_reg[1]_5 ;\n wire \\calib_sel_reg[1]_6 ;\n wire \\calib_sel_reg[1]_7 ;\n wire [7:0]\\calib_sel_reg[1]_8 ;\n wire [2:0]\\calib_sel_reg[3] ;\n wire \\calib_seq_reg[0] ;\n wire [5:0]\\calib_zero_inputs_reg[0] ;\n wire [5:0]\\calib_zero_inputs_reg[0]_0 ;\n wire [5:0]\\calib_zero_inputs_reg[0]_1 ;\n wire ck_po_stg2_f_en_reg;\n wire ck_po_stg2_f_en_reg_0;\n wire ck_po_stg2_f_en_reg_1;\n wire ck_po_stg2_f_en_reg_2;\n wire ck_po_stg2_f_indec_reg;\n wire ck_po_stg2_f_indec_reg_0;\n wire ck_po_stg2_f_indec_reg_1;\n wire ck_po_stg2_f_indec_reg_2;\n wire [1:0]\\cmd_pipe_plus.mc_address_reg[43] ;\n wire [63:0]\\data_bytes_r_reg[63] ;\n wire [5:0]\\data_offset_1_i2_reg[5] ;\n wire [1:0]ddr_ck_out;\n wire \\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_105 ;\n wire \\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_93 ;\n wire \\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_95 ;\n wire delay_done_r4_reg;\n wire delay_done_r4_reg_0;\n wire delay_done_r4_reg_1;\n wire delay_done_r4_reg_2;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;\n wire [7:0]\\fine_delay_mod_reg[23] ;\n wire freq_refclk;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_10 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_11 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_12 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_13 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_14 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_15 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_16 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_17 ;\n wire [0:0]\\gen_byte_sel_div1.calib_in_common_reg_18 ;\n wire [0:0]\\gen_byte_sel_div1.calib_in_common_reg_19 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n wire [0:0]\\gen_byte_sel_div1.calib_in_common_reg_20 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_3 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_4 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_5 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_6 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_7 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_8 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_9 ;\n wire \\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n wire \\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n wire \\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n wire \\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;\n wire \\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n wire \\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n wire \\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n wire \\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n wire [7:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ;\n wire [7:0]\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ;\n wire idelay_inc;\n wire idelay_ld_rst;\n wire idelay_ld_rst_0;\n wire idelay_ld_rst_1;\n wire idelay_ld_rst_2;\n wire in0;\n wire init_calib_complete_reg_rep;\n wire init_calib_complete_reg_rep__5;\n wire [3:0]init_calib_complete_reg_rep__6;\n wire init_calib_complete_reg_rep__6_0;\n wire \\mcGo_r_reg[13]_srl14___u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12_n_0 ;\n wire \\mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13_n_0 ;\n wire mcGo_r_reg_gate_n_0;\n wire mcGo_r_reg_r_0_n_0;\n wire mcGo_r_reg_r_10_n_0;\n wire mcGo_r_reg_r_11_n_0;\n wire mcGo_r_reg_r_12_n_0;\n wire mcGo_r_reg_r_13_n_0;\n wire mcGo_r_reg_r_1_n_0;\n wire mcGo_r_reg_r_2_n_0;\n wire mcGo_r_reg_r_3_n_0;\n wire mcGo_r_reg_r_4_n_0;\n wire mcGo_r_reg_r_5_n_0;\n wire mcGo_r_reg_r_6_n_0;\n wire mcGo_r_reg_r_7_n_0;\n wire mcGo_r_reg_r_8_n_0;\n wire mcGo_r_reg_r_9_n_0;\n wire mcGo_r_reg_r_n_0;\n wire [1:1]mcGo_w__0;\n wire [0:0]mc_cas_n;\n wire [31:0]mem_dq_in;\n wire [59:0]mem_dq_out;\n wire [35:0]mem_dq_ts;\n wire [3:0]mem_dqs_in;\n wire [3:0]mem_dqs_out;\n wire [3:0]mem_dqs_ts;\n wire [11:0]mem_out;\n wire mem_refclk;\n wire mmcm_locked;\n wire mux_cmd_wren;\n wire mux_rd_valid_r_reg;\n wire [255:0]mux_wrdata;\n wire mux_wrdata_en;\n wire [31:0]mux_wrdata_mask;\n wire \\my_empty_reg[1] ;\n wire \\my_empty_reg[1]_0 ;\n wire \\my_empty_reg[1]_1 ;\n wire \\my_empty_reg[1]_2 ;\n wire \\my_empty_reg[1]_3 ;\n wire \\my_empty_reg[1]_4 ;\n wire \\my_empty_reg[1]_5 ;\n wire \\my_empty_reg[1]_6 ;\n wire [63:0]\\my_empty_reg[7] ;\n wire [63:0]\\my_empty_reg[7]_0 ;\n wire [63:0]\\my_empty_reg[7]_1 ;\n wire [63:0]\\my_empty_reg[7]_2 ;\n wire [31:0]\\my_empty_reg[7]_3 ;\n wire \\not_strict_mode.app_rd_data_reg[0] ;\n wire \\not_strict_mode.app_rd_data_reg[100] ;\n wire \\not_strict_mode.app_rd_data_reg[101] ;\n wire \\not_strict_mode.app_rd_data_reg[102] ;\n wire \\not_strict_mode.app_rd_data_reg[103] ;\n wire \\not_strict_mode.app_rd_data_reg[104] ;\n wire \\not_strict_mode.app_rd_data_reg[105] ;\n wire \\not_strict_mode.app_rd_data_reg[106] ;\n wire \\not_strict_mode.app_rd_data_reg[107] ;\n wire \\not_strict_mode.app_rd_data_reg[108] ;\n wire \\not_strict_mode.app_rd_data_reg[109] ;\n wire \\not_strict_mode.app_rd_data_reg[10] ;\n wire \\not_strict_mode.app_rd_data_reg[110] ;\n wire \\not_strict_mode.app_rd_data_reg[111] ;\n wire \\not_strict_mode.app_rd_data_reg[112] ;\n wire \\not_strict_mode.app_rd_data_reg[113] ;\n wire \\not_strict_mode.app_rd_data_reg[114] ;\n wire \\not_strict_mode.app_rd_data_reg[115] ;\n wire \\not_strict_mode.app_rd_data_reg[116] ;\n wire \\not_strict_mode.app_rd_data_reg[117] ;\n wire \\not_strict_mode.app_rd_data_reg[118] ;\n wire \\not_strict_mode.app_rd_data_reg[119] ;\n wire \\not_strict_mode.app_rd_data_reg[11] ;\n wire \\not_strict_mode.app_rd_data_reg[120] ;\n wire \\not_strict_mode.app_rd_data_reg[121] ;\n wire \\not_strict_mode.app_rd_data_reg[122] ;\n wire \\not_strict_mode.app_rd_data_reg[123] ;\n wire \\not_strict_mode.app_rd_data_reg[124] ;\n wire \\not_strict_mode.app_rd_data_reg[125] ;\n wire \\not_strict_mode.app_rd_data_reg[126] ;\n wire \\not_strict_mode.app_rd_data_reg[127] ;\n wire \\not_strict_mode.app_rd_data_reg[128] ;\n wire \\not_strict_mode.app_rd_data_reg[129] ;\n wire \\not_strict_mode.app_rd_data_reg[12] ;\n wire \\not_strict_mode.app_rd_data_reg[130] ;\n wire \\not_strict_mode.app_rd_data_reg[131] ;\n wire \\not_strict_mode.app_rd_data_reg[132] ;\n wire \\not_strict_mode.app_rd_data_reg[133] ;\n wire \\not_strict_mode.app_rd_data_reg[134] ;\n wire \\not_strict_mode.app_rd_data_reg[135] ;\n wire \\not_strict_mode.app_rd_data_reg[136] ;\n wire \\not_strict_mode.app_rd_data_reg[137] ;\n wire \\not_strict_mode.app_rd_data_reg[138] ;\n wire \\not_strict_mode.app_rd_data_reg[139] ;\n wire \\not_strict_mode.app_rd_data_reg[13] ;\n wire \\not_strict_mode.app_rd_data_reg[140] ;\n wire \\not_strict_mode.app_rd_data_reg[141] ;\n wire \\not_strict_mode.app_rd_data_reg[142] ;\n wire \\not_strict_mode.app_rd_data_reg[143] ;\n wire \\not_strict_mode.app_rd_data_reg[144] ;\n wire \\not_strict_mode.app_rd_data_reg[145] ;\n wire \\not_strict_mode.app_rd_data_reg[146] ;\n wire \\not_strict_mode.app_rd_data_reg[147] ;\n wire \\not_strict_mode.app_rd_data_reg[148] ;\n wire \\not_strict_mode.app_rd_data_reg[149] ;\n wire \\not_strict_mode.app_rd_data_reg[14] ;\n wire \\not_strict_mode.app_rd_data_reg[150] ;\n wire \\not_strict_mode.app_rd_data_reg[151] ;\n wire \\not_strict_mode.app_rd_data_reg[152] ;\n wire \\not_strict_mode.app_rd_data_reg[153] ;\n wire \\not_strict_mode.app_rd_data_reg[154] ;\n wire \\not_strict_mode.app_rd_data_reg[155] ;\n wire \\not_strict_mode.app_rd_data_reg[156] ;\n wire \\not_strict_mode.app_rd_data_reg[157] ;\n wire \\not_strict_mode.app_rd_data_reg[158] ;\n wire \\not_strict_mode.app_rd_data_reg[159] ;\n wire \\not_strict_mode.app_rd_data_reg[15] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[15]_0 ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[15]_1 ;\n wire \\not_strict_mode.app_rd_data_reg[160] ;\n wire \\not_strict_mode.app_rd_data_reg[161] ;\n wire \\not_strict_mode.app_rd_data_reg[162] ;\n wire \\not_strict_mode.app_rd_data_reg[163] ;\n wire \\not_strict_mode.app_rd_data_reg[164] ;\n wire \\not_strict_mode.app_rd_data_reg[165] ;\n wire \\not_strict_mode.app_rd_data_reg[166] ;\n wire \\not_strict_mode.app_rd_data_reg[167] ;\n wire \\not_strict_mode.app_rd_data_reg[168] ;\n wire \\not_strict_mode.app_rd_data_reg[169] ;\n wire \\not_strict_mode.app_rd_data_reg[16] ;\n wire \\not_strict_mode.app_rd_data_reg[170] ;\n wire \\not_strict_mode.app_rd_data_reg[171] ;\n wire \\not_strict_mode.app_rd_data_reg[172] ;\n wire \\not_strict_mode.app_rd_data_reg[173] ;\n wire \\not_strict_mode.app_rd_data_reg[174] ;\n wire \\not_strict_mode.app_rd_data_reg[175] ;\n wire \\not_strict_mode.app_rd_data_reg[176] ;\n wire \\not_strict_mode.app_rd_data_reg[177] ;\n wire \\not_strict_mode.app_rd_data_reg[178] ;\n wire \\not_strict_mode.app_rd_data_reg[179] ;\n wire \\not_strict_mode.app_rd_data_reg[17] ;\n wire \\not_strict_mode.app_rd_data_reg[180] ;\n wire \\not_strict_mode.app_rd_data_reg[181] ;\n wire \\not_strict_mode.app_rd_data_reg[182] ;\n wire \\not_strict_mode.app_rd_data_reg[183] ;\n wire \\not_strict_mode.app_rd_data_reg[184] ;\n wire \\not_strict_mode.app_rd_data_reg[185] ;\n wire \\not_strict_mode.app_rd_data_reg[186] ;\n wire \\not_strict_mode.app_rd_data_reg[187] ;\n wire \\not_strict_mode.app_rd_data_reg[188] ;\n wire \\not_strict_mode.app_rd_data_reg[189] ;\n wire \\not_strict_mode.app_rd_data_reg[18] ;\n wire \\not_strict_mode.app_rd_data_reg[190] ;\n wire \\not_strict_mode.app_rd_data_reg[191] ;\n wire \\not_strict_mode.app_rd_data_reg[192] ;\n wire \\not_strict_mode.app_rd_data_reg[193] ;\n wire \\not_strict_mode.app_rd_data_reg[194] ;\n wire \\not_strict_mode.app_rd_data_reg[195] ;\n wire \\not_strict_mode.app_rd_data_reg[196] ;\n wire \\not_strict_mode.app_rd_data_reg[197] ;\n wire \\not_strict_mode.app_rd_data_reg[198] ;\n wire \\not_strict_mode.app_rd_data_reg[199] ;\n wire \\not_strict_mode.app_rd_data_reg[19] ;\n wire \\not_strict_mode.app_rd_data_reg[1] ;\n wire \\not_strict_mode.app_rd_data_reg[200] ;\n wire \\not_strict_mode.app_rd_data_reg[201] ;\n wire \\not_strict_mode.app_rd_data_reg[202] ;\n wire \\not_strict_mode.app_rd_data_reg[203] ;\n wire \\not_strict_mode.app_rd_data_reg[204] ;\n wire \\not_strict_mode.app_rd_data_reg[205] ;\n wire \\not_strict_mode.app_rd_data_reg[206] ;\n wire \\not_strict_mode.app_rd_data_reg[207] ;\n wire \\not_strict_mode.app_rd_data_reg[208] ;\n wire \\not_strict_mode.app_rd_data_reg[209] ;\n wire \\not_strict_mode.app_rd_data_reg[20] ;\n wire \\not_strict_mode.app_rd_data_reg[210] ;\n wire \\not_strict_mode.app_rd_data_reg[211] ;\n wire \\not_strict_mode.app_rd_data_reg[212] ;\n wire \\not_strict_mode.app_rd_data_reg[213] ;\n wire \\not_strict_mode.app_rd_data_reg[214] ;\n wire \\not_strict_mode.app_rd_data_reg[215] ;\n wire \\not_strict_mode.app_rd_data_reg[216] ;\n wire \\not_strict_mode.app_rd_data_reg[217] ;\n wire \\not_strict_mode.app_rd_data_reg[218] ;\n wire \\not_strict_mode.app_rd_data_reg[219] ;\n wire \\not_strict_mode.app_rd_data_reg[21] ;\n wire \\not_strict_mode.app_rd_data_reg[220] ;\n wire \\not_strict_mode.app_rd_data_reg[221] ;\n wire \\not_strict_mode.app_rd_data_reg[222] ;\n wire \\not_strict_mode.app_rd_data_reg[223] ;\n wire \\not_strict_mode.app_rd_data_reg[224] ;\n wire \\not_strict_mode.app_rd_data_reg[225] ;\n wire \\not_strict_mode.app_rd_data_reg[226] ;\n wire \\not_strict_mode.app_rd_data_reg[227] ;\n wire \\not_strict_mode.app_rd_data_reg[228] ;\n wire \\not_strict_mode.app_rd_data_reg[228]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[229] ;\n wire \\not_strict_mode.app_rd_data_reg[22] ;\n wire \\not_strict_mode.app_rd_data_reg[230] ;\n wire \\not_strict_mode.app_rd_data_reg[231] ;\n wire \\not_strict_mode.app_rd_data_reg[232] ;\n wire \\not_strict_mode.app_rd_data_reg[233] ;\n wire \\not_strict_mode.app_rd_data_reg[234] ;\n wire \\not_strict_mode.app_rd_data_reg[235] ;\n wire \\not_strict_mode.app_rd_data_reg[236] ;\n wire \\not_strict_mode.app_rd_data_reg[236]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[237] ;\n wire \\not_strict_mode.app_rd_data_reg[238] ;\n wire \\not_strict_mode.app_rd_data_reg[239] ;\n wire \\not_strict_mode.app_rd_data_reg[23] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[23]_0 ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[23]_1 ;\n wire \\not_strict_mode.app_rd_data_reg[240] ;\n wire \\not_strict_mode.app_rd_data_reg[241] ;\n wire \\not_strict_mode.app_rd_data_reg[242] ;\n wire \\not_strict_mode.app_rd_data_reg[243] ;\n wire \\not_strict_mode.app_rd_data_reg[244] ;\n wire \\not_strict_mode.app_rd_data_reg[244]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[245] ;\n wire \\not_strict_mode.app_rd_data_reg[246] ;\n wire \\not_strict_mode.app_rd_data_reg[247] ;\n wire \\not_strict_mode.app_rd_data_reg[248] ;\n wire \\not_strict_mode.app_rd_data_reg[249] ;\n wire \\not_strict_mode.app_rd_data_reg[24] ;\n wire \\not_strict_mode.app_rd_data_reg[250] ;\n wire \\not_strict_mode.app_rd_data_reg[251] ;\n wire \\not_strict_mode.app_rd_data_reg[252] ;\n wire \\not_strict_mode.app_rd_data_reg[252]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[253] ;\n wire \\not_strict_mode.app_rd_data_reg[254] ;\n wire \\not_strict_mode.app_rd_data_reg[255] ;\n wire [255:0]\\not_strict_mode.app_rd_data_reg[255]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[25] ;\n wire \\not_strict_mode.app_rd_data_reg[26] ;\n wire \\not_strict_mode.app_rd_data_reg[27] ;\n wire \\not_strict_mode.app_rd_data_reg[28] ;\n wire \\not_strict_mode.app_rd_data_reg[29] ;\n wire \\not_strict_mode.app_rd_data_reg[2] ;\n wire \\not_strict_mode.app_rd_data_reg[30] ;\n wire \\not_strict_mode.app_rd_data_reg[31] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[31]_0 ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[31]_1 ;\n wire \\not_strict_mode.app_rd_data_reg[32] ;\n wire \\not_strict_mode.app_rd_data_reg[33] ;\n wire \\not_strict_mode.app_rd_data_reg[34] ;\n wire \\not_strict_mode.app_rd_data_reg[35] ;\n wire \\not_strict_mode.app_rd_data_reg[36] ;\n wire \\not_strict_mode.app_rd_data_reg[37] ;\n wire \\not_strict_mode.app_rd_data_reg[38] ;\n wire \\not_strict_mode.app_rd_data_reg[39] ;\n wire \\not_strict_mode.app_rd_data_reg[3] ;\n wire \\not_strict_mode.app_rd_data_reg[40] ;\n wire \\not_strict_mode.app_rd_data_reg[41] ;\n wire \\not_strict_mode.app_rd_data_reg[42] ;\n wire \\not_strict_mode.app_rd_data_reg[43] ;\n wire \\not_strict_mode.app_rd_data_reg[44] ;\n wire \\not_strict_mode.app_rd_data_reg[45] ;\n wire \\not_strict_mode.app_rd_data_reg[46] ;\n wire \\not_strict_mode.app_rd_data_reg[47] ;\n wire \\not_strict_mode.app_rd_data_reg[48] ;\n wire \\not_strict_mode.app_rd_data_reg[49] ;\n wire \\not_strict_mode.app_rd_data_reg[4] ;\n wire \\not_strict_mode.app_rd_data_reg[50] ;\n wire \\not_strict_mode.app_rd_data_reg[51] ;\n wire \\not_strict_mode.app_rd_data_reg[52] ;\n wire \\not_strict_mode.app_rd_data_reg[53] ;\n wire \\not_strict_mode.app_rd_data_reg[54] ;\n wire \\not_strict_mode.app_rd_data_reg[55] ;\n wire \\not_strict_mode.app_rd_data_reg[56] ;\n wire \\not_strict_mode.app_rd_data_reg[57] ;\n wire \\not_strict_mode.app_rd_data_reg[58] ;\n wire \\not_strict_mode.app_rd_data_reg[59] ;\n wire \\not_strict_mode.app_rd_data_reg[5] ;\n wire \\not_strict_mode.app_rd_data_reg[60] ;\n wire \\not_strict_mode.app_rd_data_reg[61] ;\n wire \\not_strict_mode.app_rd_data_reg[62] ;\n wire \\not_strict_mode.app_rd_data_reg[63] ;\n wire \\not_strict_mode.app_rd_data_reg[64] ;\n wire \\not_strict_mode.app_rd_data_reg[65] ;\n wire \\not_strict_mode.app_rd_data_reg[66] ;\n wire \\not_strict_mode.app_rd_data_reg[67] ;\n wire \\not_strict_mode.app_rd_data_reg[68] ;\n wire \\not_strict_mode.app_rd_data_reg[69] ;\n wire \\not_strict_mode.app_rd_data_reg[6] ;\n wire \\not_strict_mode.app_rd_data_reg[70] ;\n wire \\not_strict_mode.app_rd_data_reg[71] ;\n wire \\not_strict_mode.app_rd_data_reg[72] ;\n wire \\not_strict_mode.app_rd_data_reg[73] ;\n wire \\not_strict_mode.app_rd_data_reg[74] ;\n wire \\not_strict_mode.app_rd_data_reg[75] ;\n wire \\not_strict_mode.app_rd_data_reg[76] ;\n wire \\not_strict_mode.app_rd_data_reg[77] ;\n wire \\not_strict_mode.app_rd_data_reg[78] ;\n wire \\not_strict_mode.app_rd_data_reg[79] ;\n wire \\not_strict_mode.app_rd_data_reg[7] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[7]_0 ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[7]_1 ;\n wire \\not_strict_mode.app_rd_data_reg[80] ;\n wire \\not_strict_mode.app_rd_data_reg[81] ;\n wire \\not_strict_mode.app_rd_data_reg[82] ;\n wire \\not_strict_mode.app_rd_data_reg[83] ;\n wire \\not_strict_mode.app_rd_data_reg[84] ;\n wire \\not_strict_mode.app_rd_data_reg[85] ;\n wire \\not_strict_mode.app_rd_data_reg[86] ;\n wire \\not_strict_mode.app_rd_data_reg[87] ;\n wire \\not_strict_mode.app_rd_data_reg[88] ;\n wire \\not_strict_mode.app_rd_data_reg[89] ;\n wire \\not_strict_mode.app_rd_data_reg[8] ;\n wire \\not_strict_mode.app_rd_data_reg[90] ;\n wire \\not_strict_mode.app_rd_data_reg[91] ;\n wire \\not_strict_mode.app_rd_data_reg[92] ;\n wire \\not_strict_mode.app_rd_data_reg[93] ;\n wire \\not_strict_mode.app_rd_data_reg[94] ;\n wire \\not_strict_mode.app_rd_data_reg[95] ;\n wire \\not_strict_mode.app_rd_data_reg[96] ;\n wire \\not_strict_mode.app_rd_data_reg[97] ;\n wire \\not_strict_mode.app_rd_data_reg[98] ;\n wire \\not_strict_mode.app_rd_data_reg[99] ;\n wire \\not_strict_mode.app_rd_data_reg[9] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ;\n wire \\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n wire [0:0]of_ctl_full_v;\n wire ofs_rdy_r_reg;\n wire ofs_rdy_r_reg_0;\n wire out;\n wire p_0_out;\n wire phy_ctl_mstr_empty;\n wire phy_ctl_wr_i2;\n wire [35:0]phy_dout;\n wire phy_if_empty_r_reg;\n wire phy_if_reset;\n wire phy_mc_ctl_full;\n wire phy_rddata_en;\n wire phy_read_calib;\n wire phy_write_calib;\n wire [3:0]\\pi_dqs_found_lanes_r1_reg[3] ;\n wire pi_en_stg2_f_reg;\n wire pi_en_stg2_f_reg_0;\n wire pi_en_stg2_f_reg_1;\n wire pi_en_stg2_f_reg_2;\n wire pi_phase_locked_all_r1_reg;\n wire [5:0]\\pi_rdval_cnt_reg[5] ;\n wire pi_stg2_f_incdec_reg;\n wire pi_stg2_f_incdec_reg_0;\n wire pi_stg2_f_incdec_reg_1;\n wire pi_stg2_f_incdec_reg_2;\n wire pll_locked;\n wire [5:0]\\po_counter_read_val_r_reg[5] ;\n wire [5:1]\\po_counter_read_val_w[0]_0 ;\n wire [4:0]\\po_rdval_cnt_reg[8] ;\n wire [4:0]\\po_rdval_cnt_reg[8]_0 ;\n wire [1:0]\\po_stg2_wrcal_cnt_reg[1] ;\n wire prbs_rdlvl_start_reg;\n wire ram_init_done_r;\n wire rclk_delay_11;\n wire \\rclk_delay_reg[10]_srl11_i_1_n_0 ;\n wire rd_buf_we;\n wire [1:0]\\rd_mux_sel_r_reg[1] ;\n wire [33:0]\\rd_ptr_reg[3] ;\n wire [17:0]\\rd_ptr_reg[3]_0 ;\n wire \\rd_ptr_timing_reg[2] ;\n wire \\rd_ptr_timing_reg[2]_0 ;\n wire \\rd_ptr_timing_reg[2]_1 ;\n wire \\rd_ptr_timing_reg[2]_10 ;\n wire \\rd_ptr_timing_reg[2]_2 ;\n wire \\rd_ptr_timing_reg[2]_3 ;\n wire \\rd_ptr_timing_reg[2]_4 ;\n wire \\rd_ptr_timing_reg[2]_5 ;\n wire \\rd_ptr_timing_reg[2]_6 ;\n wire \\rd_ptr_timing_reg[2]_7 ;\n wire \\rd_ptr_timing_reg[2]_8 ;\n wire \\rd_ptr_timing_reg[2]_9 ;\n wire [0:0]\\read_fifo.fifo_out_data_r_reg[6] ;\n wire \\read_fifo.fifo_out_data_r_reg[6]_0 ;\n wire \\read_fifo.tail_r_reg[0] ;\n wire [1:1]ref_dll_lock_w;\n wire rst_out_i_1_n_0;\n wire rst_primitives;\n wire rst_primitives_i_1_n_0;\n wire [0:0]\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ;\n wire rst_sync_r1_reg;\n wire rstdiv0_sync_r1_reg_rep__9;\n wire sync_pulse;\n wire sys_rst;\n wire [0:0]tail_r;\n wire wr_en;\n wire wr_en_5;\n wire wr_en_6;\n wire [3:0]\\wr_ptr_timing_reg[2] ;\n wire [3:0]\\wr_ptr_timing_reg[2]_0 ;\n wire [3:0]\\wr_ptr_timing_reg[2]_1 ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[224] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[225] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[226] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[227] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[228] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[229] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[230] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[231] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[232] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[233] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[234] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[235] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[236] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[237] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[238] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[239] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[240] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[241] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[242] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[243] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[244] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[245] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[246] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[247] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[248] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[249] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[250] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[251] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[252] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[253] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[254] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[255] ;\n wire [31:0]\\write_buffer.wr_buf_out_data_reg[287] ;\n\n ddr3_if_mig_7series_v4_0_ddr_phy_4lanes \\ddr_phy_4lanes_0.u_ddr_phy_4lanes \n (.A(A),\n .CLK(CLK),\n .CLKB0(CLKB0),\n .CLKB0_7(CLKB0_7),\n .CLKB0_8(CLKB0_8),\n .CLKB0_9(CLKB0_9),\n .COUNTERLOADVAL(COUNTERLOADVAL),\n .DOA(DOA),\n .DOB(DOB),\n .DOC(DOC),\n .E(E),\n .LD0(LD0),\n .LD0_3(LD0_3),\n .LD0_4(LD0_4),\n .LD0_5(LD0_5),\n .Q(Q),\n .RST0(RST0),\n ._phy_ctl_full_p__0(_phy_ctl_full_p__0),\n .\\byte_r_reg[0] (\\byte_r_reg[0]_0 ),\n .\\byte_r_reg[1] (\\byte_r_reg[1] ),\n .\\calib_sel_reg[0] (\\calib_sel_reg[0]_3 ),\n .\\calib_sel_reg[0]_0 (\\calib_sel_reg[0]_4 ),\n .\\calib_sel_reg[0]_1 (\\calib_sel_reg[0]_5 ),\n .\\calib_sel_reg[0]_2 (\\calib_sel_reg[0]_6 ),\n .\\calib_sel_reg[0]_3 (\\calib_sel_reg[0]_7 ),\n .\\calib_sel_reg[1] (\\calib_sel_reg[1]_7 ),\n .\\calib_sel_reg[1]_0 (\\calib_sel_reg[1]_8 ),\n .\\calib_sel_reg[1]_1 (\\calib_sel_reg[3] [1:0]),\n .\\calib_zero_inputs_reg[0] (\\calib_zero_inputs_reg[0] ),\n .\\calib_zero_inputs_reg[0]_0 (\\calib_zero_inputs_reg[0]_0 ),\n .\\calib_zero_inputs_reg[0]_1 (\\calib_zero_inputs_reg[0]_1 ),\n .ck_po_stg2_f_en_reg(ck_po_stg2_f_en_reg),\n .ck_po_stg2_f_en_reg_0(ck_po_stg2_f_en_reg_0),\n .ck_po_stg2_f_en_reg_1(ck_po_stg2_f_en_reg_1),\n .ck_po_stg2_f_en_reg_2(ck_po_stg2_f_en_reg_2),\n .ck_po_stg2_f_indec_reg(ck_po_stg2_f_indec_reg),\n .ck_po_stg2_f_indec_reg_0(ck_po_stg2_f_indec_reg_0),\n .ck_po_stg2_f_indec_reg_1(ck_po_stg2_f_indec_reg_1),\n .ck_po_stg2_f_indec_reg_2(ck_po_stg2_f_indec_reg_2),\n .\\data_bytes_r_reg[63] (\\data_bytes_r_reg[63] ),\n .delay_done_r4_reg(delay_done_r4_reg),\n .delay_done_r4_reg_0(delay_done_r4_reg_0),\n .delay_done_r4_reg_1(delay_done_r4_reg_1),\n .delay_done_r4_reg_2(delay_done_r4_reg_2),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ),\n .\\fine_delay_mod_reg[23] (\\fine_delay_mod_reg[23] ),\n .freq_refclk(freq_refclk),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\gen_byte_sel_div1.calib_in_common_reg_2 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_0 (\\gen_byte_sel_div1.calib_in_common_reg_3 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_1 (\\gen_byte_sel_div1.calib_in_common_reg_4 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_10 (\\gen_byte_sel_div1.calib_in_common_reg_13 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_11 (\\gen_byte_sel_div1.calib_in_common_reg_14 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_12 (\\gen_byte_sel_div1.calib_in_common_reg_15 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_13 (\\gen_byte_sel_div1.calib_in_common_reg_16 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_14 (\\gen_byte_sel_div1.calib_in_common_reg_17 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_15 (\\gen_byte_sel_div1.calib_in_common_reg_18 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_16 (\\gen_byte_sel_div1.calib_in_common_reg_19 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_17 (\\gen_byte_sel_div1.calib_in_common_reg_20 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_2 (\\gen_byte_sel_div1.calib_in_common_reg_5 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_3 (\\gen_byte_sel_div1.calib_in_common_reg_6 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_4 (\\gen_byte_sel_div1.calib_in_common_reg_7 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_5 (\\gen_byte_sel_div1.calib_in_common_reg_8 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_6 (\\gen_byte_sel_div1.calib_in_common_reg_9 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_7 (\\gen_byte_sel_div1.calib_in_common_reg_10 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_8 (\\gen_byte_sel_div1.calib_in_common_reg_11 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_9 (\\gen_byte_sel_div1.calib_in_common_reg_12 ),\n .\\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] (\\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] (\\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] (\\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] (\\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] (\\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] (\\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] (\\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] (\\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),\n .\\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] (\\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] (\\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] (\\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] (\\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] (\\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] (\\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] (\\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] (\\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),\n .\\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] (\\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] (\\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] (\\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] (\\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] (\\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] (\\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] (\\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] (\\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),\n .\\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] (\\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] (\\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] (\\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] (\\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] (\\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] (\\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] (\\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] (\\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),\n .\\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] (\\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] (\\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] (\\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] (\\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] (\\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] (\\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] (\\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] (\\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),\n .\\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] (\\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] (\\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] (\\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] (\\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] (\\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] (\\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] (\\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] (\\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),\n .\\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] (\\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] (\\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] (\\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] (\\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] (\\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] (\\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] (\\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] (\\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),\n .\\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] (\\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] (\\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] (\\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] (\\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] (\\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] (\\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] (\\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] (\\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),\n .\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] (\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ),\n .\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] (\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ),\n .\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] (\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ),\n .\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] (\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ),\n .idelay_inc(idelay_inc),\n .idelay_ld_rst(idelay_ld_rst),\n .idelay_ld_rst_0(idelay_ld_rst_0),\n .idelay_ld_rst_1(idelay_ld_rst_1),\n .idelay_ld_rst_2(idelay_ld_rst_2),\n .in0(in0),\n .init_calib_complete_reg_rep(init_calib_complete_reg_rep),\n .\\mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13 (\\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_105 ),\n .mcGo_reg_0(\\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_95 ),\n .mcGo_w__0(mcGo_w__0),\n .mem_dq_in(mem_dq_in),\n .mem_dq_out(mem_dq_out[35:0]),\n .mem_dq_ts(mem_dq_ts),\n .mem_dqs_in(mem_dqs_in),\n .mem_dqs_out(mem_dqs_out),\n .mem_dqs_ts(mem_dqs_ts),\n .mem_refclk(mem_refclk),\n .mmcm_locked(mmcm_locked),\n .mux_rd_valid_r_reg(mux_rd_valid_r_reg),\n .mux_wrdata(mux_wrdata),\n .mux_wrdata_en(mux_wrdata_en),\n .mux_wrdata_mask(mux_wrdata_mask),\n .\\my_empty_reg[1] (\\my_empty_reg[1]_2 ),\n .\\my_empty_reg[1]_0 (\\my_empty_reg[1]_3 ),\n .\\my_empty_reg[1]_1 (\\my_empty_reg[1]_4 ),\n .\\my_empty_reg[1]_2 (\\my_empty_reg[1]_5 ),\n .\\my_empty_reg[7] (\\my_empty_reg[7] ),\n .\\my_empty_reg[7]_0 (\\my_empty_reg[7]_0 ),\n .\\my_empty_reg[7]_1 (\\my_empty_reg[7]_1 ),\n .\\my_empty_reg[7]_2 (\\my_empty_reg[7]_2 ),\n .\\not_strict_mode.app_rd_data_reg[0] (\\not_strict_mode.app_rd_data_reg[0] ),\n .\\not_strict_mode.app_rd_data_reg[100] (\\not_strict_mode.app_rd_data_reg[100] ),\n .\\not_strict_mode.app_rd_data_reg[101] (\\not_strict_mode.app_rd_data_reg[101] ),\n .\\not_strict_mode.app_rd_data_reg[102] (\\not_strict_mode.app_rd_data_reg[102] ),\n .\\not_strict_mode.app_rd_data_reg[103] (\\not_strict_mode.app_rd_data_reg[103] ),\n .\\not_strict_mode.app_rd_data_reg[104] (\\not_strict_mode.app_rd_data_reg[104] ),\n .\\not_strict_mode.app_rd_data_reg[105] (\\not_strict_mode.app_rd_data_reg[105] ),\n .\\not_strict_mode.app_rd_data_reg[106] (\\not_strict_mode.app_rd_data_reg[106] ),\n .\\not_strict_mode.app_rd_data_reg[107] (\\not_strict_mode.app_rd_data_reg[107] ),\n .\\not_strict_mode.app_rd_data_reg[108] (\\not_strict_mode.app_rd_data_reg[108] ),\n .\\not_strict_mode.app_rd_data_reg[109] (\\not_strict_mode.app_rd_data_reg[109] ),\n .\\not_strict_mode.app_rd_data_reg[10] (\\not_strict_mode.app_rd_data_reg[10] ),\n .\\not_strict_mode.app_rd_data_reg[110] (\\not_strict_mode.app_rd_data_reg[110] ),\n .\\not_strict_mode.app_rd_data_reg[111] (\\not_strict_mode.app_rd_data_reg[111] ),\n .\\not_strict_mode.app_rd_data_reg[112] (\\not_strict_mode.app_rd_data_reg[112] ),\n .\\not_strict_mode.app_rd_data_reg[113] (\\not_strict_mode.app_rd_data_reg[113] ),\n .\\not_strict_mode.app_rd_data_reg[114] (\\not_strict_mode.app_rd_data_reg[114] ),\n .\\not_strict_mode.app_rd_data_reg[115] (\\not_strict_mode.app_rd_data_reg[115] ),\n .\\not_strict_mode.app_rd_data_reg[116] (\\not_strict_mode.app_rd_data_reg[116] ),\n .\\not_strict_mode.app_rd_data_reg[117] (\\not_strict_mode.app_rd_data_reg[117] ),\n .\\not_strict_mode.app_rd_data_reg[118] (\\not_strict_mode.app_rd_data_reg[118] ),\n .\\not_strict_mode.app_rd_data_reg[119] (\\not_strict_mode.app_rd_data_reg[119] ),\n .\\not_strict_mode.app_rd_data_reg[11] (\\not_strict_mode.app_rd_data_reg[11] ),\n .\\not_strict_mode.app_rd_data_reg[120] (\\not_strict_mode.app_rd_data_reg[120] ),\n .\\not_strict_mode.app_rd_data_reg[121] (\\not_strict_mode.app_rd_data_reg[121] ),\n .\\not_strict_mode.app_rd_data_reg[122] (\\not_strict_mode.app_rd_data_reg[122] ),\n .\\not_strict_mode.app_rd_data_reg[123] (\\not_strict_mode.app_rd_data_reg[123] ),\n .\\not_strict_mode.app_rd_data_reg[124] (\\not_strict_mode.app_rd_data_reg[124] ),\n .\\not_strict_mode.app_rd_data_reg[125] (\\not_strict_mode.app_rd_data_reg[125] ),\n .\\not_strict_mode.app_rd_data_reg[126] (\\not_strict_mode.app_rd_data_reg[126] ),\n .\\not_strict_mode.app_rd_data_reg[127] (\\not_strict_mode.app_rd_data_reg[127] ),\n .\\not_strict_mode.app_rd_data_reg[128] (\\not_strict_mode.app_rd_data_reg[128] ),\n .\\not_strict_mode.app_rd_data_reg[129] (\\not_strict_mode.app_rd_data_reg[129] ),\n .\\not_strict_mode.app_rd_data_reg[12] (\\not_strict_mode.app_rd_data_reg[12] ),\n .\\not_strict_mode.app_rd_data_reg[130] (\\not_strict_mode.app_rd_data_reg[130] ),\n .\\not_strict_mode.app_rd_data_reg[131] (\\not_strict_mode.app_rd_data_reg[131] ),\n .\\not_strict_mode.app_rd_data_reg[132] (\\not_strict_mode.app_rd_data_reg[132] ),\n .\\not_strict_mode.app_rd_data_reg[133] (\\not_strict_mode.app_rd_data_reg[133] ),\n .\\not_strict_mode.app_rd_data_reg[134] (\\not_strict_mode.app_rd_data_reg[134] ),\n .\\not_strict_mode.app_rd_data_reg[135] (\\not_strict_mode.app_rd_data_reg[135] ),\n .\\not_strict_mode.app_rd_data_reg[136] (\\not_strict_mode.app_rd_data_reg[136] ),\n .\\not_strict_mode.app_rd_data_reg[137] (\\not_strict_mode.app_rd_data_reg[137] ),\n .\\not_strict_mode.app_rd_data_reg[138] (\\not_strict_mode.app_rd_data_reg[138] ),\n .\\not_strict_mode.app_rd_data_reg[139] (\\not_strict_mode.app_rd_data_reg[139] ),\n .\\not_strict_mode.app_rd_data_reg[13] (\\not_strict_mode.app_rd_data_reg[13] ),\n .\\not_strict_mode.app_rd_data_reg[140] (\\not_strict_mode.app_rd_data_reg[140] ),\n .\\not_strict_mode.app_rd_data_reg[141] (\\not_strict_mode.app_rd_data_reg[141] ),\n .\\not_strict_mode.app_rd_data_reg[142] (\\not_strict_mode.app_rd_data_reg[142] ),\n .\\not_strict_mode.app_rd_data_reg[143] (\\not_strict_mode.app_rd_data_reg[143] ),\n .\\not_strict_mode.app_rd_data_reg[144] (\\not_strict_mode.app_rd_data_reg[144] ),\n .\\not_strict_mode.app_rd_data_reg[145] (\\not_strict_mode.app_rd_data_reg[145] ),\n .\\not_strict_mode.app_rd_data_reg[146] (\\not_strict_mode.app_rd_data_reg[146] ),\n .\\not_strict_mode.app_rd_data_reg[147] (\\not_strict_mode.app_rd_data_reg[147] ),\n .\\not_strict_mode.app_rd_data_reg[148] (\\not_strict_mode.app_rd_data_reg[148] ),\n .\\not_strict_mode.app_rd_data_reg[149] (\\not_strict_mode.app_rd_data_reg[149] ),\n .\\not_strict_mode.app_rd_data_reg[14] (\\not_strict_mode.app_rd_data_reg[14] ),\n .\\not_strict_mode.app_rd_data_reg[150] (\\not_strict_mode.app_rd_data_reg[150] ),\n .\\not_strict_mode.app_rd_data_reg[151] (\\not_strict_mode.app_rd_data_reg[151] ),\n .\\not_strict_mode.app_rd_data_reg[152] (\\not_strict_mode.app_rd_data_reg[152] ),\n .\\not_strict_mode.app_rd_data_reg[153] (\\not_strict_mode.app_rd_data_reg[153] ),\n .\\not_strict_mode.app_rd_data_reg[154] (\\not_strict_mode.app_rd_data_reg[154] ),\n .\\not_strict_mode.app_rd_data_reg[155] (\\not_strict_mode.app_rd_data_reg[155] ),\n .\\not_strict_mode.app_rd_data_reg[156] (\\not_strict_mode.app_rd_data_reg[156] ),\n .\\not_strict_mode.app_rd_data_reg[157] (\\not_strict_mode.app_rd_data_reg[157] ),\n .\\not_strict_mode.app_rd_data_reg[158] (\\not_strict_mode.app_rd_data_reg[158] ),\n .\\not_strict_mode.app_rd_data_reg[159] (\\not_strict_mode.app_rd_data_reg[159] ),\n .\\not_strict_mode.app_rd_data_reg[15] (\\not_strict_mode.app_rd_data_reg[15] ),\n .\\not_strict_mode.app_rd_data_reg[15]_0 (\\not_strict_mode.app_rd_data_reg[15]_0 ),\n .\\not_strict_mode.app_rd_data_reg[15]_1 (\\not_strict_mode.app_rd_data_reg[15]_1 ),\n .\\not_strict_mode.app_rd_data_reg[160] (\\not_strict_mode.app_rd_data_reg[160] ),\n .\\not_strict_mode.app_rd_data_reg[161] (\\not_strict_mode.app_rd_data_reg[161] ),\n .\\not_strict_mode.app_rd_data_reg[162] (\\not_strict_mode.app_rd_data_reg[162] ),\n .\\not_strict_mode.app_rd_data_reg[163] (\\not_strict_mode.app_rd_data_reg[163] ),\n .\\not_strict_mode.app_rd_data_reg[164] (\\not_strict_mode.app_rd_data_reg[164] ),\n .\\not_strict_mode.app_rd_data_reg[165] (\\not_strict_mode.app_rd_data_reg[165] ),\n .\\not_strict_mode.app_rd_data_reg[166] (\\not_strict_mode.app_rd_data_reg[166] ),\n .\\not_strict_mode.app_rd_data_reg[167] (\\not_strict_mode.app_rd_data_reg[167] ),\n .\\not_strict_mode.app_rd_data_reg[168] (\\not_strict_mode.app_rd_data_reg[168] ),\n .\\not_strict_mode.app_rd_data_reg[169] (\\not_strict_mode.app_rd_data_reg[169] ),\n .\\not_strict_mode.app_rd_data_reg[16] (\\not_strict_mode.app_rd_data_reg[16] ),\n .\\not_strict_mode.app_rd_data_reg[170] (\\not_strict_mode.app_rd_data_reg[170] ),\n .\\not_strict_mode.app_rd_data_reg[171] (\\not_strict_mode.app_rd_data_reg[171] ),\n .\\not_strict_mode.app_rd_data_reg[172] (\\not_strict_mode.app_rd_data_reg[172] ),\n .\\not_strict_mode.app_rd_data_reg[173] (\\not_strict_mode.app_rd_data_reg[173] ),\n .\\not_strict_mode.app_rd_data_reg[174] (\\not_strict_mode.app_rd_data_reg[174] ),\n .\\not_strict_mode.app_rd_data_reg[175] (\\not_strict_mode.app_rd_data_reg[175] ),\n .\\not_strict_mode.app_rd_data_reg[176] (\\not_strict_mode.app_rd_data_reg[176] ),\n .\\not_strict_mode.app_rd_data_reg[177] (\\not_strict_mode.app_rd_data_reg[177] ),\n .\\not_strict_mode.app_rd_data_reg[178] (\\not_strict_mode.app_rd_data_reg[178] ),\n .\\not_strict_mode.app_rd_data_reg[179] (\\not_strict_mode.app_rd_data_reg[179] ),\n .\\not_strict_mode.app_rd_data_reg[17] (\\not_strict_mode.app_rd_data_reg[17] ),\n .\\not_strict_mode.app_rd_data_reg[180] (\\not_strict_mode.app_rd_data_reg[180] ),\n .\\not_strict_mode.app_rd_data_reg[181] (\\not_strict_mode.app_rd_data_reg[181] ),\n .\\not_strict_mode.app_rd_data_reg[182] (\\not_strict_mode.app_rd_data_reg[182] ),\n .\\not_strict_mode.app_rd_data_reg[183] (\\not_strict_mode.app_rd_data_reg[183] ),\n .\\not_strict_mode.app_rd_data_reg[184] (\\not_strict_mode.app_rd_data_reg[184] ),\n .\\not_strict_mode.app_rd_data_reg[185] (\\not_strict_mode.app_rd_data_reg[185] ),\n .\\not_strict_mode.app_rd_data_reg[186] (\\not_strict_mode.app_rd_data_reg[186] ),\n .\\not_strict_mode.app_rd_data_reg[187] (\\not_strict_mode.app_rd_data_reg[187] ),\n .\\not_strict_mode.app_rd_data_reg[188] (\\not_strict_mode.app_rd_data_reg[188] ),\n .\\not_strict_mode.app_rd_data_reg[189] (\\not_strict_mode.app_rd_data_reg[189] ),\n .\\not_strict_mode.app_rd_data_reg[18] (\\not_strict_mode.app_rd_data_reg[18] ),\n .\\not_strict_mode.app_rd_data_reg[190] (\\not_strict_mode.app_rd_data_reg[190] ),\n .\\not_strict_mode.app_rd_data_reg[191] (\\not_strict_mode.app_rd_data_reg[191] ),\n .\\not_strict_mode.app_rd_data_reg[192] (\\not_strict_mode.app_rd_data_reg[192] ),\n .\\not_strict_mode.app_rd_data_reg[193] (\\not_strict_mode.app_rd_data_reg[193] ),\n .\\not_strict_mode.app_rd_data_reg[194] (\\not_strict_mode.app_rd_data_reg[194] ),\n .\\not_strict_mode.app_rd_data_reg[195] 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.\\not_strict_mode.app_rd_data_reg[92] (\\not_strict_mode.app_rd_data_reg[92] ),\n .\\not_strict_mode.app_rd_data_reg[93] (\\not_strict_mode.app_rd_data_reg[93] ),\n .\\not_strict_mode.app_rd_data_reg[94] (\\not_strict_mode.app_rd_data_reg[94] ),\n .\\not_strict_mode.app_rd_data_reg[95] (\\not_strict_mode.app_rd_data_reg[95] ),\n .\\not_strict_mode.app_rd_data_reg[96] (\\not_strict_mode.app_rd_data_reg[96] ),\n .\\not_strict_mode.app_rd_data_reg[97] (\\not_strict_mode.app_rd_data_reg[97] ),\n .\\not_strict_mode.app_rd_data_reg[98] (\\not_strict_mode.app_rd_data_reg[98] ),\n .\\not_strict_mode.app_rd_data_reg[99] (\\not_strict_mode.app_rd_data_reg[99] ),\n .\\not_strict_mode.app_rd_data_reg[9] (\\not_strict_mode.app_rd_data_reg[9] ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ),\n .\\not_strict_mode.status_ram.rd_buf_we_r1_reg (\\not_strict_mode.status_ram.rd_buf_we_r1_reg ),\n .ofs_rdy_r_reg(ofs_rdy_r_reg),\n .ofs_rdy_r_reg_0(ofs_rdy_r_reg_0),\n .out(out),\n .p_0_out(p_0_out),\n .phy_ctl_mstr_empty(phy_ctl_mstr_empty),\n .phy_ctl_wr_i2(phy_ctl_wr_i2),\n .phy_ctl_wr_i2_reg(rst_primitives_i_1_n_0),\n .phy_if_empty_r_reg(phy_if_empty_r_reg),\n .phy_if_reset(phy_if_reset),\n .phy_rddata_en(phy_rddata_en),\n .phy_read_calib(phy_read_calib),\n .phy_write_calib(phy_write_calib),\n .\\pi_dqs_found_lanes_r1_reg[3] (\\pi_dqs_found_lanes_r1_reg[3] ),\n .pi_en_stg2_f_reg(pi_en_stg2_f_reg),\n .pi_en_stg2_f_reg_0(pi_en_stg2_f_reg_0),\n .pi_en_stg2_f_reg_1(pi_en_stg2_f_reg_1),\n .pi_en_stg2_f_reg_2(pi_en_stg2_f_reg_2),\n .pi_phase_locked_all_r1_reg(pi_phase_locked_all_r1_reg),\n .\\pi_rdval_cnt_reg[5] (\\pi_rdval_cnt_reg[5] ),\n .pi_stg2_f_incdec_reg(pi_stg2_f_incdec_reg),\n .pi_stg2_f_incdec_reg_0(pi_stg2_f_incdec_reg_0),\n .pi_stg2_f_incdec_reg_1(pi_stg2_f_incdec_reg_1),\n .pi_stg2_f_incdec_reg_2(pi_stg2_f_incdec_reg_2),\n .pll_locked(pll_locked),\n .\\po_rdval_cnt_reg[8] ({\\po_rdval_cnt_reg[8] [4:2],\\po_counter_read_val_w[0]_0 [5:4],\\po_rdval_cnt_reg[8] [1],\\po_counter_read_val_w[0]_0 [2:1],\\po_rdval_cnt_reg[8] [0]}),\n .\\po_stg2_wrcal_cnt_reg[1] (\\po_stg2_wrcal_cnt_reg[1] ),\n .prbs_rdlvl_start_reg(prbs_rdlvl_start_reg),\n .ram_init_done_r(ram_init_done_r),\n .rclk_delay_11(rclk_delay_11),\n .\\rclk_delay_reg[11]_0 (rst_out_i_1_n_0),\n .rd_buf_we(rd_buf_we),\n .\\rd_mux_sel_r_reg[1] (\\rd_mux_sel_r_reg[1] ),\n .\\read_fifo.fifo_out_data_r_reg[6] (\\read_fifo.fifo_out_data_r_reg[6] ),\n .\\read_fifo.fifo_out_data_r_reg[6]_0 (\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .\\read_fifo.tail_r_reg[0] (\\read_fifo.tail_r_reg[0] ),\n .ref_dll_lock_w(ref_dll_lock_w),\n .rst_primitives(rst_primitives),\n .rst_primitives_reg_0(\\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_93 ),\n .rst_primitives_reg_1(\\rclk_delay_reg[10]_srl11_i_1_n_0 ),\n .\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] (\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .rst_sync_r1_reg(rst_sync_r1_reg),\n .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9),\n .sync_pulse(sync_pulse),\n .sys_rst(sys_rst),\n .tail_r(tail_r),\n .\\write_buffer.wr_buf_out_data_reg[224] (\\write_buffer.wr_buf_out_data_reg[224] ),\n .\\write_buffer.wr_buf_out_data_reg[225] (\\write_buffer.wr_buf_out_data_reg[225] ),\n .\\write_buffer.wr_buf_out_data_reg[226] (\\write_buffer.wr_buf_out_data_reg[226] ),\n .\\write_buffer.wr_buf_out_data_reg[227] (\\write_buffer.wr_buf_out_data_reg[227] ),\n .\\write_buffer.wr_buf_out_data_reg[228] (\\write_buffer.wr_buf_out_data_reg[228] ),\n .\\write_buffer.wr_buf_out_data_reg[229] (\\write_buffer.wr_buf_out_data_reg[229] ),\n .\\write_buffer.wr_buf_out_data_reg[230] (\\write_buffer.wr_buf_out_data_reg[230] ),\n .\\write_buffer.wr_buf_out_data_reg[231] (\\write_buffer.wr_buf_out_data_reg[231] ),\n .\\write_buffer.wr_buf_out_data_reg[232] (\\write_buffer.wr_buf_out_data_reg[232] ),\n .\\write_buffer.wr_buf_out_data_reg[233] (\\write_buffer.wr_buf_out_data_reg[233] ),\n .\\write_buffer.wr_buf_out_data_reg[234] (\\write_buffer.wr_buf_out_data_reg[234] ),\n .\\write_buffer.wr_buf_out_data_reg[235] (\\write_buffer.wr_buf_out_data_reg[235] ),\n .\\write_buffer.wr_buf_out_data_reg[236] (\\write_buffer.wr_buf_out_data_reg[236] ),\n .\\write_buffer.wr_buf_out_data_reg[237] (\\write_buffer.wr_buf_out_data_reg[237] ),\n .\\write_buffer.wr_buf_out_data_reg[238] (\\write_buffer.wr_buf_out_data_reg[238] ),\n .\\write_buffer.wr_buf_out_data_reg[239] (\\write_buffer.wr_buf_out_data_reg[239] ),\n .\\write_buffer.wr_buf_out_data_reg[240] (\\write_buffer.wr_buf_out_data_reg[240] ),\n .\\write_buffer.wr_buf_out_data_reg[241] (\\write_buffer.wr_buf_out_data_reg[241] ),\n .\\write_buffer.wr_buf_out_data_reg[242] (\\write_buffer.wr_buf_out_data_reg[242] ),\n .\\write_buffer.wr_buf_out_data_reg[243] (\\write_buffer.wr_buf_out_data_reg[243] ),\n .\\write_buffer.wr_buf_out_data_reg[244] (\\write_buffer.wr_buf_out_data_reg[244] ),\n .\\write_buffer.wr_buf_out_data_reg[245] (\\write_buffer.wr_buf_out_data_reg[245] ),\n .\\write_buffer.wr_buf_out_data_reg[246] (\\write_buffer.wr_buf_out_data_reg[246] ),\n .\\write_buffer.wr_buf_out_data_reg[247] (\\write_buffer.wr_buf_out_data_reg[247] ),\n .\\write_buffer.wr_buf_out_data_reg[248] (\\write_buffer.wr_buf_out_data_reg[248] ),\n .\\write_buffer.wr_buf_out_data_reg[249] (\\write_buffer.wr_buf_out_data_reg[249] ),\n .\\write_buffer.wr_buf_out_data_reg[250] (\\write_buffer.wr_buf_out_data_reg[250] ),\n .\\write_buffer.wr_buf_out_data_reg[251] (\\write_buffer.wr_buf_out_data_reg[251] ),\n .\\write_buffer.wr_buf_out_data_reg[252] (\\write_buffer.wr_buf_out_data_reg[252] ),\n .\\write_buffer.wr_buf_out_data_reg[253] (\\write_buffer.wr_buf_out_data_reg[253] ),\n .\\write_buffer.wr_buf_out_data_reg[254] (\\write_buffer.wr_buf_out_data_reg[254] ),\n .\\write_buffer.wr_buf_out_data_reg[255] (\\write_buffer.wr_buf_out_data_reg[255] ),\n .\\write_buffer.wr_buf_out_data_reg[287] (\\write_buffer.wr_buf_out_data_reg[287] ));\n ddr3_if_mig_7series_v4_0_ddr_phy_4lanes__parameterized0 \\ddr_phy_4lanes_1.u_ddr_phy_4lanes \n (.CLK(CLK),\n .D0(D0),\n .D1(D1),\n .D2(D2),\n .D3(D3),\n .D4(D4),\n .D5(D5),\n .D6(D6),\n .D7(D7),\n .D8(D8),\n .D9(D9),\n .D_po_coarse_enable110_out(D_po_coarse_enable110_out),\n .D_po_counter_read_en122_out(D_po_counter_read_en122_out),\n .D_po_fine_enable107_out(D_po_fine_enable107_out),\n .D_po_fine_inc113_out(D_po_fine_inc113_out),\n .D_po_sel_fine_oclk_delay125_out(D_po_sel_fine_oclk_delay125_out),\n .PHYCTLWD({Q[10:9],\\data_offset_1_i2_reg[5] ,Q[2:0]}),\n .Q(\\wr_ptr_timing_reg[2] ),\n .RST0(RST0),\n ._phy_ctl_full_p__0(_phy_ctl_full_p__0),\n .\\byte_r_reg[0] (\\byte_r_reg[0] ),\n .\\calib_sel_reg[0] (\\calib_sel_reg[0] ),\n .\\calib_sel_reg[0]_0 (\\calib_sel_reg[0]_0 ),\n .\\calib_sel_reg[0]_1 (\\calib_sel_reg[0]_1 ),\n .\\calib_sel_reg[0]_2 (\\calib_sel_reg[0]_2 ),\n .\\calib_sel_reg[1] (\\calib_sel_reg[1] ),\n .\\calib_sel_reg[1]_0 (\\calib_sel_reg[1]_0 ),\n .\\calib_sel_reg[1]_1 (\\calib_sel_reg[1]_1 ),\n .\\calib_sel_reg[1]_2 (\\calib_sel_reg[1]_2 ),\n .\\calib_sel_reg[1]_3 (\\calib_sel_reg[1]_3 ),\n .\\calib_sel_reg[1]_4 (\\calib_sel_reg[1]_4 ),\n .\\calib_sel_reg[1]_5 (\\calib_sel_reg[1]_5 ),\n .\\calib_sel_reg[1]_6 (\\calib_sel_reg[1]_6 ),\n .\\calib_sel_reg[3] (\\calib_sel_reg[3] ),\n .\\cmd_pipe_plus.mc_address_reg[43] (\\cmd_pipe_plus.mc_address_reg[43] ),\n .ddr_ck_out(ddr_ck_out),\n .freq_refclk(freq_refclk),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\gen_byte_sel_div1.calib_in_common_reg ),\n .\\gen_byte_sel_div1.calib_in_common_reg_0 (\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_1 (\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] (\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] (\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ),\n .in0(in0),\n .init_calib_complete_reg_rep(init_calib_complete_reg_rep),\n .init_calib_complete_reg_rep__5(init_calib_complete_reg_rep__5),\n .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6),\n .init_calib_complete_reg_rep__6_0(init_calib_complete_reg_rep__6_0),\n .mcGo_w__0(mcGo_w__0),\n .mc_cas_n(mc_cas_n),\n .mem_dq_out(mem_dq_out[59:36]),\n .mem_out(mem_out),\n .mem_refclk(mem_refclk),\n .mux_cmd_wren(mux_cmd_wren),\n .\\my_empty_reg[1] (\\my_empty_reg[1] ),\n .\\my_empty_reg[1]_0 (\\my_empty_reg[1]_0 ),\n .\\my_empty_reg[1]_1 (\\my_empty_reg[1]_1 ),\n .\\my_empty_reg[1]_2 (\\my_empty_reg[1]_6 ),\n .\\my_empty_reg[7] (\\my_empty_reg[7]_3 ),\n .of_ctl_full_v(of_ctl_full_v),\n .phy_ctl_mstr_empty(phy_ctl_mstr_empty),\n .phy_ctl_wr_i2(phy_ctl_wr_i2),\n .phy_dout(phy_dout),\n .phy_mc_ctl_full(phy_mc_ctl_full),\n .phy_read_calib(phy_read_calib),\n .phy_write_calib(phy_write_calib),\n .pll_locked(pll_locked),\n .\\po_counter_read_val_r_reg[5] (\\po_counter_read_val_r_reg[5] ),\n .\\po_counter_read_val_reg[5]_0 ({\\po_counter_read_val_w[0]_0 [5:4],\\po_rdval_cnt_reg[8] [1],\\po_counter_read_val_w[0]_0 [2:1],\\po_rdval_cnt_reg[8] [0]}),\n .\\po_rdval_cnt_reg[8] (\\po_rdval_cnt_reg[8]_0 ),\n .\\rd_ptr_reg[3] (\\rd_ptr_reg[3] ),\n .\\rd_ptr_reg[3]_0 (\\rd_ptr_reg[3]_0 ),\n .\\rd_ptr_timing_reg[2] (\\rd_ptr_timing_reg[2] ),\n .\\rd_ptr_timing_reg[2]_0 (\\rd_ptr_timing_reg[2]_0 ),\n .\\rd_ptr_timing_reg[2]_1 (\\rd_ptr_timing_reg[2]_1 ),\n .\\rd_ptr_timing_reg[2]_10 (\\rd_ptr_timing_reg[2]_10 ),\n .\\rd_ptr_timing_reg[2]_2 (\\rd_ptr_timing_reg[2]_2 ),\n .\\rd_ptr_timing_reg[2]_3 (\\rd_ptr_timing_reg[2]_3 ),\n .\\rd_ptr_timing_reg[2]_4 (\\rd_ptr_timing_reg[2]_4 ),\n .\\rd_ptr_timing_reg[2]_5 (\\rd_ptr_timing_reg[2]_5 ),\n .\\rd_ptr_timing_reg[2]_6 (\\rd_ptr_timing_reg[2]_6 ),\n .\\rd_ptr_timing_reg[2]_7 (\\rd_ptr_timing_reg[2]_7 ),\n .\\rd_ptr_timing_reg[2]_8 (\\rd_ptr_timing_reg[2]_8 ),\n .\\rd_ptr_timing_reg[2]_9 (\\rd_ptr_timing_reg[2]_9 ),\n .ref_dll_lock_w(ref_dll_lock_w),\n .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9),\n .sync_pulse(sync_pulse),\n .wr_en(wr_en),\n .wr_en_5(wr_en_5),\n .wr_en_6(wr_en_6),\n .\\wr_ptr_timing_reg[2] (\\wr_ptr_timing_reg[2]_0 ),\n .\\wr_ptr_timing_reg[2]_0 (\\wr_ptr_timing_reg[2]_1 ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/mcGo_r_reg \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/mcGo_r_reg[13]_srl14___u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12 \" *) \n SRL16E \\mcGo_r_reg[13]_srl14___u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12 \n (.A0(1'b1),\n .A1(1'b0),\n .A2(1'b1),\n .A3(1'b1),\n .CE(1'b1),\n .CLK(CLK),\n .D(\\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_105 ),\n .Q(\\mcGo_r_reg[13]_srl14___u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12_n_0 ));\n FDRE \\mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13 \n (.C(CLK),\n .CE(1'b1),\n .D(\\mcGo_r_reg[13]_srl14___u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12_n_0 ),\n .Q(\\mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13_n_0 ),\n .R(1'b0));\n FDRE \\mcGo_r_reg[15] \n (.C(CLK),\n .CE(1'b1),\n .D(mcGo_r_reg_gate_n_0),\n .Q(\\calib_seq_reg[0] ),\n .R(in0));\n LUT2 #(\n .INIT(4'h8)) \n mcGo_r_reg_gate\n (.I0(\\mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13_n_0 ),\n .I1(mcGo_r_reg_r_13_n_0),\n .O(mcGo_r_reg_gate_n_0));\n FDRE mcGo_r_reg_r\n (.C(CLK),\n .CE(1'b1),\n .D(1'b1),\n .Q(mcGo_r_reg_r_n_0),\n .R(in0));\n FDRE mcGo_r_reg_r_0\n (.C(CLK),\n .CE(1'b1),\n .D(mcGo_r_reg_r_n_0),\n .Q(mcGo_r_reg_r_0_n_0),\n .R(in0));\n FDRE mcGo_r_reg_r_1\n (.C(CLK),\n .CE(1'b1),\n .D(mcGo_r_reg_r_0_n_0),\n .Q(mcGo_r_reg_r_1_n_0),\n .R(in0));\n FDRE mcGo_r_reg_r_10\n (.C(CLK),\n .CE(1'b1),\n .D(mcGo_r_reg_r_9_n_0),\n .Q(mcGo_r_reg_r_10_n_0),\n .R(in0));\n FDRE mcGo_r_reg_r_11\n (.C(CLK),\n .CE(1'b1),\n .D(mcGo_r_reg_r_10_n_0),\n .Q(mcGo_r_reg_r_11_n_0),\n .R(in0));\n FDRE mcGo_r_reg_r_12\n (.C(CLK),\n .CE(1'b1),\n .D(mcGo_r_reg_r_11_n_0),\n .Q(mcGo_r_reg_r_12_n_0),\n .R(in0));\n FDRE mcGo_r_reg_r_13\n (.C(CLK),\n .CE(1'b1),\n .D(mcGo_r_reg_r_12_n_0),\n .Q(mcGo_r_reg_r_13_n_0),\n .R(in0));\n FDRE mcGo_r_reg_r_2\n (.C(CLK),\n .CE(1'b1),\n .D(mcGo_r_reg_r_1_n_0),\n .Q(mcGo_r_reg_r_2_n_0),\n .R(in0));\n FDRE mcGo_r_reg_r_3\n (.C(CLK),\n .CE(1'b1),\n .D(mcGo_r_reg_r_2_n_0),\n .Q(mcGo_r_reg_r_3_n_0),\n .R(in0));\n FDRE mcGo_r_reg_r_4\n (.C(CLK),\n .CE(1'b1),\n .D(mcGo_r_reg_r_3_n_0),\n .Q(mcGo_r_reg_r_4_n_0),\n .R(in0));\n FDRE mcGo_r_reg_r_5\n (.C(CLK),\n .CE(1'b1),\n .D(mcGo_r_reg_r_4_n_0),\n .Q(mcGo_r_reg_r_5_n_0),\n .R(in0));\n FDRE mcGo_r_reg_r_6\n (.C(CLK),\n .CE(1'b1),\n .D(mcGo_r_reg_r_5_n_0),\n .Q(mcGo_r_reg_r_6_n_0),\n .R(in0));\n FDRE mcGo_r_reg_r_7\n (.C(CLK),\n .CE(1'b1),\n .D(mcGo_r_reg_r_6_n_0),\n .Q(mcGo_r_reg_r_7_n_0),\n .R(in0));\n FDRE mcGo_r_reg_r_8\n (.C(CLK),\n .CE(1'b1),\n .D(mcGo_r_reg_r_7_n_0),\n .Q(mcGo_r_reg_r_8_n_0),\n .R(in0));\n FDRE mcGo_r_reg_r_9\n (.C(CLK),\n .CE(1'b1),\n .D(mcGo_r_reg_r_8_n_0),\n .Q(mcGo_r_reg_r_9_n_0),\n .R(in0));\n LUT1 #(\n .INIT(2'h1)) \n \\rclk_delay_reg[10]_srl11_i_1 \n (.I0(rst_primitives),\n .O(\\rclk_delay_reg[10]_srl11_i_1_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n rst_out_i_1\n (.I0(rclk_delay_11),\n .I1(\\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_95 ),\n .O(rst_out_i_1_n_0));\n LUT1 #(\n .INIT(2'h1)) \n rst_primitives_i_1\n (.I0(\\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_93 ),\n .O(rst_primitives_i_1_n_0));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_ddr_mc_phy_wrapper\n (ddr3_reset_n,\n ddr3_cas_n,\n ddr3_ras_n,\n ddr3_we_n,\n ddr3_addr,\n ddr3_ba,\n ddr3_cs_n,\n ddr3_odt,\n ddr3_cke,\n ddr3_dm,\n fine_delay_sel_r,\n \\fine_delay_mod_reg[26]_0 ,\n \\rd_ptr_timing_reg[2] ,\n \\rd_ptr_timing_reg[2]_0 ,\n \\rd_ptr_timing_reg[2]_1 ,\n \\rd_ptr_timing_reg[2]_2 ,\n \\rd_ptr_timing_reg[2]_3 ,\n \\rd_ptr_timing_reg[2]_4 ,\n \\rd_ptr_timing_reg[2]_5 ,\n \\rd_ptr_timing_reg[2]_6 ,\n \\rd_ptr_timing_reg[2]_7 ,\n \\rd_ptr_timing_reg[2]_8 ,\n \\rd_ptr_timing_reg[2]_9 ,\n \\rd_ptr_timing_reg[2]_10 ,\n \\pi_dqs_found_lanes_r1_reg[3] ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,\n \\not_strict_mode.app_rd_data_reg[252] ,\n idelay_ld_rst,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,\n \\not_strict_mode.app_rd_data_reg[244] ,\n idelay_ld_rst_0,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,\n \\not_strict_mode.app_rd_data_reg[236] ,\n idelay_ld_rst_1,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,\n \\not_strict_mode.app_rd_data_reg[228] ,\n idelay_ld_rst_2,\n \\calib_seq_reg[0] ,\n \\my_empty_reg[1] ,\n \\my_empty_reg[1]_0 ,\n phy_mc_ctl_full,\n \\my_empty_reg[1]_1 ,\n \\my_empty_reg[1]_2 ,\n \\my_empty_reg[1]_3 ,\n \\my_empty_reg[1]_4 ,\n \\my_empty_reg[1]_5 ,\n rd_buf_we,\n \\not_strict_mode.status_ram.rd_buf_we_r1_reg ,\n \\my_empty_reg[7] ,\n \\my_empty_reg[1]_6 ,\n phy_rddata_en,\n mux_rd_valid_r_reg,\n rst_sync_r1_reg,\n \\byte_r_reg[0] ,\n \\po_counter_read_val_r_reg[5] ,\n \\data_bytes_r_reg[63] ,\n \\not_strict_mode.app_rd_data_reg[255] ,\n \\not_strict_mode.app_rd_data_reg[239] ,\n \\not_strict_mode.app_rd_data_reg[247] ,\n \\not_strict_mode.app_rd_data_reg[231] ,\n \\not_strict_mode.app_rd_data_reg[254] ,\n \\not_strict_mode.app_rd_data_reg[238] ,\n \\not_strict_mode.app_rd_data_reg[246] ,\n \\not_strict_mode.app_rd_data_reg[230] ,\n \\not_strict_mode.app_rd_data_reg[253] ,\n \\not_strict_mode.app_rd_data_reg[237] ,\n \\not_strict_mode.app_rd_data_reg[245] ,\n \\not_strict_mode.app_rd_data_reg[229] ,\n \\not_strict_mode.app_rd_data_reg[252]_0 ,\n \\not_strict_mode.app_rd_data_reg[236]_0 ,\n \\not_strict_mode.app_rd_data_reg[244]_0 ,\n \\not_strict_mode.app_rd_data_reg[228]_0 ,\n \\not_strict_mode.app_rd_data_reg[251] ,\n \\not_strict_mode.app_rd_data_reg[235] ,\n \\not_strict_mode.app_rd_data_reg[243] ,\n \\not_strict_mode.app_rd_data_reg[227] ,\n \\not_strict_mode.app_rd_data_reg[250] ,\n \\not_strict_mode.app_rd_data_reg[234] ,\n \\not_strict_mode.app_rd_data_reg[242] ,\n \\not_strict_mode.app_rd_data_reg[226] ,\n \\not_strict_mode.app_rd_data_reg[249] ,\n \\not_strict_mode.app_rd_data_reg[233] ,\n \\not_strict_mode.app_rd_data_reg[241] ,\n \\not_strict_mode.app_rd_data_reg[225] ,\n \\not_strict_mode.app_rd_data_reg[248] ,\n \\not_strict_mode.app_rd_data_reg[232] ,\n \\not_strict_mode.app_rd_data_reg[240] ,\n \\not_strict_mode.app_rd_data_reg[224] ,\n \\not_strict_mode.app_rd_data_reg[223] ,\n \\not_strict_mode.app_rd_data_reg[207] ,\n \\not_strict_mode.app_rd_data_reg[215] ,\n \\not_strict_mode.app_rd_data_reg[199] ,\n \\not_strict_mode.app_rd_data_reg[222] ,\n \\not_strict_mode.app_rd_data_reg[206] ,\n \\not_strict_mode.app_rd_data_reg[214] ,\n \\not_strict_mode.app_rd_data_reg[198] ,\n \\not_strict_mode.app_rd_data_reg[221] ,\n \\not_strict_mode.app_rd_data_reg[205] ,\n \\not_strict_mode.app_rd_data_reg[213] ,\n \\not_strict_mode.app_rd_data_reg[197] ,\n \\not_strict_mode.app_rd_data_reg[220] ,\n \\not_strict_mode.app_rd_data_reg[204] ,\n \\not_strict_mode.app_rd_data_reg[212] ,\n \\not_strict_mode.app_rd_data_reg[196] ,\n \\not_strict_mode.app_rd_data_reg[219] ,\n \\not_strict_mode.app_rd_data_reg[203] ,\n \\not_strict_mode.app_rd_data_reg[211] ,\n \\not_strict_mode.app_rd_data_reg[195] ,\n \\not_strict_mode.app_rd_data_reg[218] ,\n \\not_strict_mode.app_rd_data_reg[202] ,\n \\not_strict_mode.app_rd_data_reg[210] ,\n \\not_strict_mode.app_rd_data_reg[194] ,\n \\not_strict_mode.app_rd_data_reg[217] ,\n \\not_strict_mode.app_rd_data_reg[201] ,\n \\not_strict_mode.app_rd_data_reg[209] ,\n \\not_strict_mode.app_rd_data_reg[193] ,\n \\not_strict_mode.app_rd_data_reg[216] ,\n \\not_strict_mode.app_rd_data_reg[200] ,\n \\not_strict_mode.app_rd_data_reg[208] ,\n \\not_strict_mode.app_rd_data_reg[192] ,\n \\not_strict_mode.app_rd_data_reg[191] ,\n \\not_strict_mode.app_rd_data_reg[175] ,\n \\not_strict_mode.app_rd_data_reg[183] ,\n \\not_strict_mode.app_rd_data_reg[167] ,\n \\not_strict_mode.app_rd_data_reg[190] ,\n \\not_strict_mode.app_rd_data_reg[174] ,\n \\not_strict_mode.app_rd_data_reg[182] ,\n \\not_strict_mode.app_rd_data_reg[166] ,\n \\not_strict_mode.app_rd_data_reg[189] ,\n \\not_strict_mode.app_rd_data_reg[173] ,\n \\not_strict_mode.app_rd_data_reg[181] ,\n \\not_strict_mode.app_rd_data_reg[165] ,\n \\not_strict_mode.app_rd_data_reg[188] ,\n \\not_strict_mode.app_rd_data_reg[172] ,\n \\not_strict_mode.app_rd_data_reg[180] ,\n \\not_strict_mode.app_rd_data_reg[164] ,\n \\not_strict_mode.app_rd_data_reg[187] ,\n \\not_strict_mode.app_rd_data_reg[171] ,\n \\not_strict_mode.app_rd_data_reg[179] ,\n \\not_strict_mode.app_rd_data_reg[163] ,\n \\not_strict_mode.app_rd_data_reg[186] ,\n \\not_strict_mode.app_rd_data_reg[170] ,\n \\not_strict_mode.app_rd_data_reg[178] ,\n \\not_strict_mode.app_rd_data_reg[162] ,\n \\not_strict_mode.app_rd_data_reg[185] ,\n \\not_strict_mode.app_rd_data_reg[169] ,\n \\not_strict_mode.app_rd_data_reg[177] ,\n \\not_strict_mode.app_rd_data_reg[161] ,\n \\not_strict_mode.app_rd_data_reg[184] ,\n \\not_strict_mode.app_rd_data_reg[168] ,\n \\not_strict_mode.app_rd_data_reg[176] ,\n \\not_strict_mode.app_rd_data_reg[160] ,\n \\not_strict_mode.app_rd_data_reg[159] ,\n \\not_strict_mode.app_rd_data_reg[143] ,\n \\not_strict_mode.app_rd_data_reg[151] ,\n \\not_strict_mode.app_rd_data_reg[135] ,\n \\not_strict_mode.app_rd_data_reg[158] ,\n \\not_strict_mode.app_rd_data_reg[142] ,\n \\not_strict_mode.app_rd_data_reg[150] ,\n \\not_strict_mode.app_rd_data_reg[134] ,\n \\not_strict_mode.app_rd_data_reg[157] ,\n \\not_strict_mode.app_rd_data_reg[141] ,\n \\not_strict_mode.app_rd_data_reg[149] ,\n \\not_strict_mode.app_rd_data_reg[133] ,\n \\not_strict_mode.app_rd_data_reg[156] ,\n \\not_strict_mode.app_rd_data_reg[140] ,\n \\not_strict_mode.app_rd_data_reg[148] ,\n \\not_strict_mode.app_rd_data_reg[132] ,\n \\not_strict_mode.app_rd_data_reg[155] ,\n \\not_strict_mode.app_rd_data_reg[139] ,\n \\not_strict_mode.app_rd_data_reg[147] ,\n \\not_strict_mode.app_rd_data_reg[131] ,\n \\not_strict_mode.app_rd_data_reg[154] ,\n \\not_strict_mode.app_rd_data_reg[138] ,\n \\not_strict_mode.app_rd_data_reg[146] ,\n \\not_strict_mode.app_rd_data_reg[130] ,\n \\not_strict_mode.app_rd_data_reg[153] ,\n \\not_strict_mode.app_rd_data_reg[137] ,\n \\not_strict_mode.app_rd_data_reg[145] ,\n \\not_strict_mode.app_rd_data_reg[129] ,\n \\not_strict_mode.app_rd_data_reg[152] ,\n \\not_strict_mode.app_rd_data_reg[136] ,\n \\not_strict_mode.app_rd_data_reg[144] ,\n \\not_strict_mode.app_rd_data_reg[128] ,\n \\not_strict_mode.app_rd_data_reg[127] ,\n \\not_strict_mode.app_rd_data_reg[111] ,\n \\not_strict_mode.app_rd_data_reg[119] ,\n \\not_strict_mode.app_rd_data_reg[103] ,\n \\not_strict_mode.app_rd_data_reg[126] ,\n \\not_strict_mode.app_rd_data_reg[110] ,\n \\not_strict_mode.app_rd_data_reg[118] ,\n \\not_strict_mode.app_rd_data_reg[102] ,\n \\not_strict_mode.app_rd_data_reg[125] ,\n \\not_strict_mode.app_rd_data_reg[109] ,\n \\not_strict_mode.app_rd_data_reg[117] ,\n \\not_strict_mode.app_rd_data_reg[101] ,\n \\not_strict_mode.app_rd_data_reg[124] ,\n \\not_strict_mode.app_rd_data_reg[108] ,\n \\not_strict_mode.app_rd_data_reg[116] ,\n \\not_strict_mode.app_rd_data_reg[100] ,\n \\not_strict_mode.app_rd_data_reg[123] ,\n \\not_strict_mode.app_rd_data_reg[107] ,\n \\not_strict_mode.app_rd_data_reg[115] ,\n \\not_strict_mode.app_rd_data_reg[99] ,\n \\not_strict_mode.app_rd_data_reg[122] ,\n \\not_strict_mode.app_rd_data_reg[106] ,\n \\not_strict_mode.app_rd_data_reg[114] ,\n \\not_strict_mode.app_rd_data_reg[98] ,\n \\not_strict_mode.app_rd_data_reg[121] ,\n \\not_strict_mode.app_rd_data_reg[105] ,\n \\not_strict_mode.app_rd_data_reg[113] ,\n \\not_strict_mode.app_rd_data_reg[97] ,\n \\not_strict_mode.app_rd_data_reg[120] ,\n \\not_strict_mode.app_rd_data_reg[104] ,\n \\not_strict_mode.app_rd_data_reg[112] ,\n \\not_strict_mode.app_rd_data_reg[96] ,\n \\not_strict_mode.app_rd_data_reg[95] ,\n \\not_strict_mode.app_rd_data_reg[79] ,\n \\not_strict_mode.app_rd_data_reg[87] ,\n \\not_strict_mode.app_rd_data_reg[71] ,\n \\not_strict_mode.app_rd_data_reg[94] ,\n \\not_strict_mode.app_rd_data_reg[78] ,\n \\not_strict_mode.app_rd_data_reg[86] ,\n \\not_strict_mode.app_rd_data_reg[70] ,\n \\not_strict_mode.app_rd_data_reg[93] ,\n \\not_strict_mode.app_rd_data_reg[77] ,\n \\not_strict_mode.app_rd_data_reg[85] ,\n \\not_strict_mode.app_rd_data_reg[69] ,\n \\not_strict_mode.app_rd_data_reg[92] ,\n \\not_strict_mode.app_rd_data_reg[76] ,\n \\not_strict_mode.app_rd_data_reg[84] ,\n \\not_strict_mode.app_rd_data_reg[68] ,\n \\not_strict_mode.app_rd_data_reg[91] ,\n \\not_strict_mode.app_rd_data_reg[75] ,\n \\not_strict_mode.app_rd_data_reg[83] ,\n \\not_strict_mode.app_rd_data_reg[67] ,\n \\not_strict_mode.app_rd_data_reg[90] ,\n \\not_strict_mode.app_rd_data_reg[74] ,\n \\not_strict_mode.app_rd_data_reg[82] ,\n \\not_strict_mode.app_rd_data_reg[66] ,\n \\not_strict_mode.app_rd_data_reg[89] ,\n \\not_strict_mode.app_rd_data_reg[73] ,\n \\not_strict_mode.app_rd_data_reg[81] ,\n \\not_strict_mode.app_rd_data_reg[65] ,\n \\not_strict_mode.app_rd_data_reg[88] ,\n \\not_strict_mode.app_rd_data_reg[72] ,\n \\not_strict_mode.app_rd_data_reg[80] ,\n \\not_strict_mode.app_rd_data_reg[64] ,\n \\not_strict_mode.app_rd_data_reg[63] ,\n \\not_strict_mode.app_rd_data_reg[47] ,\n \\not_strict_mode.app_rd_data_reg[55] ,\n \\not_strict_mode.app_rd_data_reg[39] ,\n \\not_strict_mode.app_rd_data_reg[62] ,\n \\not_strict_mode.app_rd_data_reg[46] ,\n \\not_strict_mode.app_rd_data_reg[54] ,\n \\not_strict_mode.app_rd_data_reg[38] ,\n \\not_strict_mode.app_rd_data_reg[61] ,\n \\not_strict_mode.app_rd_data_reg[45] ,\n \\not_strict_mode.app_rd_data_reg[53] ,\n \\not_strict_mode.app_rd_data_reg[37] ,\n \\not_strict_mode.app_rd_data_reg[60] ,\n \\not_strict_mode.app_rd_data_reg[44] ,\n \\not_strict_mode.app_rd_data_reg[52] ,\n \\not_strict_mode.app_rd_data_reg[36] ,\n \\not_strict_mode.app_rd_data_reg[59] ,\n \\not_strict_mode.app_rd_data_reg[43] ,\n \\not_strict_mode.app_rd_data_reg[51] ,\n \\not_strict_mode.app_rd_data_reg[35] ,\n \\not_strict_mode.app_rd_data_reg[58] ,\n \\not_strict_mode.app_rd_data_reg[42] ,\n \\not_strict_mode.app_rd_data_reg[50] ,\n \\not_strict_mode.app_rd_data_reg[34] ,\n \\not_strict_mode.app_rd_data_reg[57] ,\n \\not_strict_mode.app_rd_data_reg[41] ,\n \\not_strict_mode.app_rd_data_reg[49] ,\n \\not_strict_mode.app_rd_data_reg[33] ,\n \\not_strict_mode.app_rd_data_reg[56] ,\n \\not_strict_mode.app_rd_data_reg[40] ,\n \\not_strict_mode.app_rd_data_reg[48] ,\n \\not_strict_mode.app_rd_data_reg[32] ,\n \\not_strict_mode.app_rd_data_reg[31] ,\n \\not_strict_mode.app_rd_data_reg[15] ,\n \\not_strict_mode.app_rd_data_reg[23] ,\n \\not_strict_mode.app_rd_data_reg[7] ,\n \\not_strict_mode.app_rd_data_reg[30] ,\n \\not_strict_mode.app_rd_data_reg[14] ,\n \\not_strict_mode.app_rd_data_reg[22] ,\n \\not_strict_mode.app_rd_data_reg[6] ,\n \\not_strict_mode.app_rd_data_reg[29] ,\n \\not_strict_mode.app_rd_data_reg[13] ,\n \\not_strict_mode.app_rd_data_reg[21] ,\n \\not_strict_mode.app_rd_data_reg[5] ,\n \\not_strict_mode.app_rd_data_reg[28] ,\n \\not_strict_mode.app_rd_data_reg[12] ,\n \\not_strict_mode.app_rd_data_reg[20] ,\n \\not_strict_mode.app_rd_data_reg[4] ,\n \\not_strict_mode.app_rd_data_reg[27] ,\n \\not_strict_mode.app_rd_data_reg[11] ,\n \\not_strict_mode.app_rd_data_reg[19] ,\n \\not_strict_mode.app_rd_data_reg[3] ,\n \\not_strict_mode.app_rd_data_reg[26] ,\n \\not_strict_mode.app_rd_data_reg[10] ,\n \\not_strict_mode.app_rd_data_reg[18] ,\n \\not_strict_mode.app_rd_data_reg[2] ,\n \\not_strict_mode.app_rd_data_reg[25] ,\n \\not_strict_mode.app_rd_data_reg[9] ,\n \\not_strict_mode.app_rd_data_reg[17] ,\n \\not_strict_mode.app_rd_data_reg[1] ,\n \\not_strict_mode.app_rd_data_reg[24] ,\n \\not_strict_mode.app_rd_data_reg[8] ,\n \\not_strict_mode.app_rd_data_reg[16] ,\n \\not_strict_mode.app_rd_data_reg[0] ,\n \\read_fifo.tail_r_reg[0] ,\n \\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,\n \\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,\n \\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,\n \\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,\n \\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,\n \\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,\n \\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,\n \\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,\n \\not_strict_mode.app_rd_data_reg[255]_0 ,\n of_ctl_full_v,\n pd_out,\n pi_phase_locked_all_r1_reg,\n \\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ,\n \\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ,\n \\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ,\n \\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ,\n \\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ,\n \\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ,\n \\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ,\n \\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ,\n wr_en,\n wr_en_5,\n wr_en_6,\n fine_delay_mod,\n \\not_strict_mode.app_rd_data_reg[31]_0 ,\n \\not_strict_mode.app_rd_data_reg[31]_1 ,\n \\my_empty_reg[7]_0 ,\n \\not_strict_mode.app_rd_data_reg[23]_0 ,\n \\not_strict_mode.app_rd_data_reg[23]_1 ,\n \\my_empty_reg[7]_1 ,\n \\not_strict_mode.app_rd_data_reg[15]_0 ,\n \\not_strict_mode.app_rd_data_reg[15]_1 ,\n \\my_empty_reg[7]_2 ,\n \\not_strict_mode.app_rd_data_reg[7]_0 ,\n \\not_strict_mode.app_rd_data_reg[7]_1 ,\n \\my_empty_reg[7]_3 ,\n ofs_rdy_r_reg,\n ofs_rdy_r_reg_0,\n \\po_rdval_cnt_reg[8] ,\n \\pi_rdval_cnt_reg[5] ,\n \\wr_ptr_timing_reg[2] ,\n \\wr_ptr_timing_reg[2]_0 ,\n \\wr_ptr_timing_reg[2]_1 ,\n \\po_rdval_cnt_reg[8]_0 ,\n phy_if_empty_r_reg,\n p_0_out,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,\n \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,\n \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,\n \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,\n \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,\n ddr_ck_out,\n ddr3_dq,\n ddr3_dqs_p,\n ddr3_dqs_n,\n mux_reset_n,\n idle,\n mmcm_ps_clk,\n rst_sync_r1,\n CLK,\n mux_cmd_wren,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[2] ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 ,\n fine_delay_sel_reg,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[2]_1 ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_1 ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_2 ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_3 ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_4 ,\n init_calib_complete_reg_rep__6,\n D5,\n D6,\n D2,\n D3,\n \\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ,\n \\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ,\n D7,\n D8,\n D9,\n D0,\n D1,\n \\calib_sel_reg[0] ,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n \\calib_sel_reg[0]_0 ,\n \\calib_sel_reg[0]_1 ,\n freq_refclk,\n mem_refclk,\n \\calib_sel_reg[0]_2 ,\n sync_pulse,\n \\calib_sel_reg[1] ,\n \\gen_byte_sel_div1.calib_in_common_reg_0 ,\n \\calib_sel_reg[1]_0 ,\n \\calib_sel_reg[1]_1 ,\n \\calib_sel_reg[1]_2 ,\n \\calib_sel_reg[1]_3 ,\n \\gen_byte_sel_div1.calib_in_common_reg_1 ,\n \\calib_sel_reg[1]_4 ,\n \\calib_sel_reg[1]_5 ,\n \\calib_sel_reg[1]_6 ,\n pll_locked,\n phy_read_calib,\n in0,\n phy_write_calib,\n \\gen_byte_sel_div1.calib_in_common_reg_2 ,\n \\calib_sel_reg[0]_3 ,\n pi_en_stg2_f_reg,\n pi_stg2_f_incdec_reg,\n \\gen_byte_sel_div1.calib_in_common_reg_3 ,\n COUNTERLOADVAL,\n \\gen_byte_sel_div1.calib_in_common_reg_4 ,\n ck_po_stg2_f_en_reg,\n ck_po_stg2_f_indec_reg,\n delay_done_r4_reg,\n \\write_buffer.wr_buf_out_data_reg[255] ,\n \\write_buffer.wr_buf_out_data_reg[254] ,\n \\write_buffer.wr_buf_out_data_reg[253] ,\n \\write_buffer.wr_buf_out_data_reg[252] ,\n \\write_buffer.wr_buf_out_data_reg[251] ,\n \\write_buffer.wr_buf_out_data_reg[250] ,\n \\write_buffer.wr_buf_out_data_reg[249] ,\n \\write_buffer.wr_buf_out_data_reg[248] ,\n \\gen_byte_sel_div1.calib_in_common_reg_5 ,\n idelay_inc,\n LD0,\n CLKB0,\n phy_if_reset,\n \\gen_byte_sel_div1.calib_in_common_reg_6 ,\n \\calib_sel_reg[0]_4 ,\n pi_en_stg2_f_reg_0,\n pi_stg2_f_incdec_reg_0,\n \\gen_byte_sel_div1.calib_in_common_reg_7 ,\n \\calib_zero_inputs_reg[0] ,\n \\gen_byte_sel_div1.calib_in_common_reg_8 ,\n ck_po_stg2_f_en_reg_0,\n ck_po_stg2_f_indec_reg_0,\n delay_done_r4_reg_0,\n \\write_buffer.wr_buf_out_data_reg[247] ,\n \\write_buffer.wr_buf_out_data_reg[246] ,\n \\write_buffer.wr_buf_out_data_reg[245] ,\n \\write_buffer.wr_buf_out_data_reg[244] ,\n \\write_buffer.wr_buf_out_data_reg[243] ,\n \\write_buffer.wr_buf_out_data_reg[242] ,\n \\write_buffer.wr_buf_out_data_reg[241] ,\n \\write_buffer.wr_buf_out_data_reg[240] ,\n \\gen_byte_sel_div1.calib_in_common_reg_9 ,\n LD0_3,\n CLKB0_7,\n \\gen_byte_sel_div1.calib_in_common_reg_10 ,\n \\calib_sel_reg[1]_7 ,\n pi_en_stg2_f_reg_1,\n pi_stg2_f_incdec_reg_1,\n \\gen_byte_sel_div1.calib_in_common_reg_11 ,\n \\calib_zero_inputs_reg[0]_0 ,\n \\gen_byte_sel_div1.calib_in_common_reg_12 ,\n ck_po_stg2_f_en_reg_1,\n ck_po_stg2_f_indec_reg_1,\n delay_done_r4_reg_1,\n \\write_buffer.wr_buf_out_data_reg[239] ,\n \\write_buffer.wr_buf_out_data_reg[238] ,\n \\write_buffer.wr_buf_out_data_reg[237] ,\n \\write_buffer.wr_buf_out_data_reg[236] ,\n \\write_buffer.wr_buf_out_data_reg[235] ,\n \\write_buffer.wr_buf_out_data_reg[234] ,\n \\write_buffer.wr_buf_out_data_reg[233] ,\n \\write_buffer.wr_buf_out_data_reg[232] ,\n \\gen_byte_sel_div1.calib_in_common_reg_13 ,\n LD0_4,\n CLKB0_8,\n \\gen_byte_sel_div1.calib_in_common_reg_14 ,\n \\calib_sel_reg[0]_5 ,\n pi_en_stg2_f_reg_2,\n pi_stg2_f_incdec_reg_2,\n \\gen_byte_sel_div1.calib_in_common_reg_15 ,\n \\calib_zero_inputs_reg[0]_1 ,\n \\gen_byte_sel_div1.calib_in_common_reg_16 ,\n ck_po_stg2_f_en_reg_2,\n ck_po_stg2_f_indec_reg_2,\n delay_done_r4_reg_2,\n \\write_buffer.wr_buf_out_data_reg[231] ,\n \\write_buffer.wr_buf_out_data_reg[230] ,\n \\write_buffer.wr_buf_out_data_reg[229] ,\n \\write_buffer.wr_buf_out_data_reg[228] ,\n \\write_buffer.wr_buf_out_data_reg[227] ,\n \\write_buffer.wr_buf_out_data_reg[226] ,\n \\write_buffer.wr_buf_out_data_reg[225] ,\n \\write_buffer.wr_buf_out_data_reg[224] ,\n \\gen_byte_sel_div1.calib_in_common_reg_17 ,\n LD0_5,\n CLKB0_9,\n RST0,\n rstdiv0_sync_r1_reg_rep__9,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[2]_2 ,\n mem_out,\n \\rd_ptr_reg[3] ,\n mux_wrdata_en,\n \\rd_ptr_reg[3]_0 ,\n \\read_fifo.fifo_out_data_r_reg[6] ,\n ram_init_done_r,\n \\genblk9[6].fine_delay_incdec_pb_reg[6] ,\n \\genblk9[5].fine_delay_incdec_pb_reg[5] ,\n \\genblk9[7].fine_delay_incdec_pb_reg[7] ,\n \\genblk9[4].fine_delay_incdec_pb_reg[4] ,\n \\genblk9[3].fine_delay_incdec_pb_reg[3] ,\n \\genblk9[4].fine_delay_incdec_pb_reg[4]_0 ,\n init_calib_complete_reg_rep__5,\n mc_cas_n,\n \\cmd_pipe_plus.mc_address_reg[43] ,\n init_calib_complete_reg_rep,\n Q,\n prbs_rdlvl_start_reg,\n out,\n sys_rst,\n \\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ,\n mmcm_locked,\n \\byte_r_reg[0]_0 ,\n \\byte_r_reg[1] ,\n tail_r,\n \\rd_mux_sel_r_reg[1] ,\n \\read_fifo.fifo_out_data_r_reg[6]_0 ,\n DOC,\n DOB,\n DOA,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ,\n \\genblk9[0].fine_delay_incdec_pb_reg[0] ,\n \\genblk9[1].fine_delay_incdec_pb_reg[1] ,\n \\genblk9[2].fine_delay_incdec_pb_reg[2] ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[1] ,\n A,\n rstdiv0_sync_r1_reg_rep__2,\n SR,\n D,\n \\cmd_pipe_plus.mc_data_offset_1_reg[5] ,\n mux_wrdata,\n mux_wrdata_mask,\n E,\n \\fine_delay_mod_reg[23]_0 ,\n \\gen_byte_sel_div1.calib_in_common_reg_18 ,\n \\calib_sel_reg[0]_6 ,\n \\gen_byte_sel_div1.calib_in_common_reg_19 ,\n \\calib_sel_reg[1]_8 ,\n \\gen_byte_sel_div1.calib_in_common_reg_20 ,\n \\calib_sel_reg[0]_7 ,\n \\calib_sel_reg[3] ,\n \\po_stg2_wrcal_cnt_reg[1] ,\n D_po_coarse_enable110_out,\n D_po_counter_read_en122_out,\n D_po_fine_enable107_out,\n D_po_fine_inc113_out,\n D_po_sel_fine_oclk_delay125_out,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ,\n D4,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ,\n phy_dout,\n init_calib_complete_reg_rep__6_0);\n output ddr3_reset_n;\n output ddr3_cas_n;\n output ddr3_ras_n;\n output ddr3_we_n;\n output [14:0]ddr3_addr;\n output [2:0]ddr3_ba;\n output [0:0]ddr3_cs_n;\n output [0:0]ddr3_odt;\n output [0:0]ddr3_cke;\n output [3:0]ddr3_dm;\n output fine_delay_sel_r;\n output \\fine_delay_mod_reg[26]_0 ;\n output \\rd_ptr_timing_reg[2] ;\n output \\rd_ptr_timing_reg[2]_0 ;\n output \\rd_ptr_timing_reg[2]_1 ;\n output \\rd_ptr_timing_reg[2]_2 ;\n output \\rd_ptr_timing_reg[2]_3 ;\n output \\rd_ptr_timing_reg[2]_4 ;\n output \\rd_ptr_timing_reg[2]_5 ;\n output \\rd_ptr_timing_reg[2]_6 ;\n output \\rd_ptr_timing_reg[2]_7 ;\n output \\rd_ptr_timing_reg[2]_8 ;\n output \\rd_ptr_timing_reg[2]_9 ;\n output \\rd_ptr_timing_reg[2]_10 ;\n output [3:0]\\pi_dqs_found_lanes_r1_reg[3] ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[252] ;\n output idelay_ld_rst;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[244] ;\n output idelay_ld_rst_0;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[236] ;\n output idelay_ld_rst_1;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[228] ;\n output idelay_ld_rst_2;\n output \\calib_seq_reg[0] ;\n output \\my_empty_reg[1] ;\n output \\my_empty_reg[1]_0 ;\n output phy_mc_ctl_full;\n output \\my_empty_reg[1]_1 ;\n output \\my_empty_reg[1]_2 ;\n output \\my_empty_reg[1]_3 ;\n output \\my_empty_reg[1]_4 ;\n output \\my_empty_reg[1]_5 ;\n output rd_buf_we;\n output \\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n output [31:0]\\my_empty_reg[7] ;\n output \\my_empty_reg[1]_6 ;\n output phy_rddata_en;\n output mux_rd_valid_r_reg;\n output rst_sync_r1_reg;\n output \\byte_r_reg[0] ;\n output [5:0]\\po_counter_read_val_r_reg[5] ;\n output [63:0]\\data_bytes_r_reg[63] ;\n output \\not_strict_mode.app_rd_data_reg[255] ;\n output \\not_strict_mode.app_rd_data_reg[239] ;\n output \\not_strict_mode.app_rd_data_reg[247] ;\n output \\not_strict_mode.app_rd_data_reg[231] ;\n output \\not_strict_mode.app_rd_data_reg[254] ;\n output \\not_strict_mode.app_rd_data_reg[238] ;\n output \\not_strict_mode.app_rd_data_reg[246] ;\n output \\not_strict_mode.app_rd_data_reg[230] ;\n output \\not_strict_mode.app_rd_data_reg[253] ;\n output \\not_strict_mode.app_rd_data_reg[237] ;\n output \\not_strict_mode.app_rd_data_reg[245] ;\n output \\not_strict_mode.app_rd_data_reg[229] ;\n output \\not_strict_mode.app_rd_data_reg[252]_0 ;\n output \\not_strict_mode.app_rd_data_reg[236]_0 ;\n output \\not_strict_mode.app_rd_data_reg[244]_0 ;\n output \\not_strict_mode.app_rd_data_reg[228]_0 ;\n output \\not_strict_mode.app_rd_data_reg[251] ;\n output \\not_strict_mode.app_rd_data_reg[235] ;\n output \\not_strict_mode.app_rd_data_reg[243] ;\n output \\not_strict_mode.app_rd_data_reg[227] ;\n output \\not_strict_mode.app_rd_data_reg[250] ;\n output \\not_strict_mode.app_rd_data_reg[234] ;\n output \\not_strict_mode.app_rd_data_reg[242] ;\n output \\not_strict_mode.app_rd_data_reg[226] ;\n output \\not_strict_mode.app_rd_data_reg[249] ;\n output \\not_strict_mode.app_rd_data_reg[233] ;\n output \\not_strict_mode.app_rd_data_reg[241] ;\n output \\not_strict_mode.app_rd_data_reg[225] ;\n output \\not_strict_mode.app_rd_data_reg[248] ;\n output \\not_strict_mode.app_rd_data_reg[232] ;\n output \\not_strict_mode.app_rd_data_reg[240] ;\n output \\not_strict_mode.app_rd_data_reg[224] ;\n output \\not_strict_mode.app_rd_data_reg[223] ;\n output \\not_strict_mode.app_rd_data_reg[207] ;\n output \\not_strict_mode.app_rd_data_reg[215] ;\n output \\not_strict_mode.app_rd_data_reg[199] ;\n output \\not_strict_mode.app_rd_data_reg[222] ;\n output \\not_strict_mode.app_rd_data_reg[206] ;\n output \\not_strict_mode.app_rd_data_reg[214] ;\n output \\not_strict_mode.app_rd_data_reg[198] ;\n output \\not_strict_mode.app_rd_data_reg[221] ;\n output \\not_strict_mode.app_rd_data_reg[205] ;\n output \\not_strict_mode.app_rd_data_reg[213] ;\n output \\not_strict_mode.app_rd_data_reg[197] ;\n output \\not_strict_mode.app_rd_data_reg[220] ;\n output \\not_strict_mode.app_rd_data_reg[204] ;\n output \\not_strict_mode.app_rd_data_reg[212] ;\n output \\not_strict_mode.app_rd_data_reg[196] ;\n output \\not_strict_mode.app_rd_data_reg[219] ;\n output \\not_strict_mode.app_rd_data_reg[203] ;\n output \\not_strict_mode.app_rd_data_reg[211] ;\n output \\not_strict_mode.app_rd_data_reg[195] ;\n output \\not_strict_mode.app_rd_data_reg[218] ;\n output \\not_strict_mode.app_rd_data_reg[202] ;\n output \\not_strict_mode.app_rd_data_reg[210] ;\n output \\not_strict_mode.app_rd_data_reg[194] ;\n output \\not_strict_mode.app_rd_data_reg[217] ;\n output \\not_strict_mode.app_rd_data_reg[201] ;\n output \\not_strict_mode.app_rd_data_reg[209] ;\n output \\not_strict_mode.app_rd_data_reg[193] ;\n output \\not_strict_mode.app_rd_data_reg[216] ;\n output \\not_strict_mode.app_rd_data_reg[200] ;\n output \\not_strict_mode.app_rd_data_reg[208] ;\n output \\not_strict_mode.app_rd_data_reg[192] ;\n output \\not_strict_mode.app_rd_data_reg[191] ;\n output \\not_strict_mode.app_rd_data_reg[175] ;\n output \\not_strict_mode.app_rd_data_reg[183] ;\n output \\not_strict_mode.app_rd_data_reg[167] ;\n output \\not_strict_mode.app_rd_data_reg[190] ;\n output \\not_strict_mode.app_rd_data_reg[174] ;\n output \\not_strict_mode.app_rd_data_reg[182] ;\n output \\not_strict_mode.app_rd_data_reg[166] ;\n output \\not_strict_mode.app_rd_data_reg[189] ;\n output \\not_strict_mode.app_rd_data_reg[173] ;\n output \\not_strict_mode.app_rd_data_reg[181] ;\n output \\not_strict_mode.app_rd_data_reg[165] ;\n output \\not_strict_mode.app_rd_data_reg[188] ;\n output \\not_strict_mode.app_rd_data_reg[172] ;\n output \\not_strict_mode.app_rd_data_reg[180] ;\n output \\not_strict_mode.app_rd_data_reg[164] ;\n output \\not_strict_mode.app_rd_data_reg[187] ;\n output \\not_strict_mode.app_rd_data_reg[171] ;\n output \\not_strict_mode.app_rd_data_reg[179] ;\n output \\not_strict_mode.app_rd_data_reg[163] ;\n output \\not_strict_mode.app_rd_data_reg[186] ;\n output \\not_strict_mode.app_rd_data_reg[170] ;\n output \\not_strict_mode.app_rd_data_reg[178] ;\n output \\not_strict_mode.app_rd_data_reg[162] ;\n output \\not_strict_mode.app_rd_data_reg[185] ;\n output \\not_strict_mode.app_rd_data_reg[169] ;\n output \\not_strict_mode.app_rd_data_reg[177] ;\n output \\not_strict_mode.app_rd_data_reg[161] ;\n output \\not_strict_mode.app_rd_data_reg[184] ;\n output \\not_strict_mode.app_rd_data_reg[168] ;\n output \\not_strict_mode.app_rd_data_reg[176] ;\n output \\not_strict_mode.app_rd_data_reg[160] ;\n output \\not_strict_mode.app_rd_data_reg[159] ;\n output \\not_strict_mode.app_rd_data_reg[143] ;\n output \\not_strict_mode.app_rd_data_reg[151] ;\n output \\not_strict_mode.app_rd_data_reg[135] ;\n output \\not_strict_mode.app_rd_data_reg[158] ;\n output \\not_strict_mode.app_rd_data_reg[142] ;\n output \\not_strict_mode.app_rd_data_reg[150] ;\n output \\not_strict_mode.app_rd_data_reg[134] ;\n output \\not_strict_mode.app_rd_data_reg[157] ;\n output \\not_strict_mode.app_rd_data_reg[141] ;\n output \\not_strict_mode.app_rd_data_reg[149] ;\n output \\not_strict_mode.app_rd_data_reg[133] ;\n output \\not_strict_mode.app_rd_data_reg[156] ;\n output \\not_strict_mode.app_rd_data_reg[140] ;\n output \\not_strict_mode.app_rd_data_reg[148] ;\n output \\not_strict_mode.app_rd_data_reg[132] ;\n output \\not_strict_mode.app_rd_data_reg[155] ;\n output \\not_strict_mode.app_rd_data_reg[139] ;\n output \\not_strict_mode.app_rd_data_reg[147] ;\n output \\not_strict_mode.app_rd_data_reg[131] ;\n output \\not_strict_mode.app_rd_data_reg[154] ;\n output \\not_strict_mode.app_rd_data_reg[138] ;\n output \\not_strict_mode.app_rd_data_reg[146] ;\n output \\not_strict_mode.app_rd_data_reg[130] ;\n output \\not_strict_mode.app_rd_data_reg[153] ;\n output \\not_strict_mode.app_rd_data_reg[137] ;\n output \\not_strict_mode.app_rd_data_reg[145] ;\n output \\not_strict_mode.app_rd_data_reg[129] ;\n output \\not_strict_mode.app_rd_data_reg[152] ;\n output \\not_strict_mode.app_rd_data_reg[136] ;\n output \\not_strict_mode.app_rd_data_reg[144] ;\n output \\not_strict_mode.app_rd_data_reg[128] ;\n output \\not_strict_mode.app_rd_data_reg[127] ;\n output \\not_strict_mode.app_rd_data_reg[111] ;\n output \\not_strict_mode.app_rd_data_reg[119] ;\n output \\not_strict_mode.app_rd_data_reg[103] ;\n output \\not_strict_mode.app_rd_data_reg[126] ;\n output \\not_strict_mode.app_rd_data_reg[110] ;\n output \\not_strict_mode.app_rd_data_reg[118] ;\n output \\not_strict_mode.app_rd_data_reg[102] ;\n output \\not_strict_mode.app_rd_data_reg[125] ;\n output \\not_strict_mode.app_rd_data_reg[109] ;\n output \\not_strict_mode.app_rd_data_reg[117] ;\n output \\not_strict_mode.app_rd_data_reg[101] ;\n output \\not_strict_mode.app_rd_data_reg[124] ;\n output \\not_strict_mode.app_rd_data_reg[108] ;\n output \\not_strict_mode.app_rd_data_reg[116] ;\n output \\not_strict_mode.app_rd_data_reg[100] ;\n output \\not_strict_mode.app_rd_data_reg[123] ;\n output \\not_strict_mode.app_rd_data_reg[107] ;\n output \\not_strict_mode.app_rd_data_reg[115] ;\n output \\not_strict_mode.app_rd_data_reg[99] ;\n output \\not_strict_mode.app_rd_data_reg[122] ;\n output \\not_strict_mode.app_rd_data_reg[106] ;\n output \\not_strict_mode.app_rd_data_reg[114] ;\n output \\not_strict_mode.app_rd_data_reg[98] ;\n output \\not_strict_mode.app_rd_data_reg[121] ;\n output \\not_strict_mode.app_rd_data_reg[105] ;\n output \\not_strict_mode.app_rd_data_reg[113] ;\n output \\not_strict_mode.app_rd_data_reg[97] ;\n output \\not_strict_mode.app_rd_data_reg[120] ;\n output \\not_strict_mode.app_rd_data_reg[104] ;\n output \\not_strict_mode.app_rd_data_reg[112] ;\n output \\not_strict_mode.app_rd_data_reg[96] ;\n output \\not_strict_mode.app_rd_data_reg[95] ;\n output \\not_strict_mode.app_rd_data_reg[79] ;\n output \\not_strict_mode.app_rd_data_reg[87] ;\n output \\not_strict_mode.app_rd_data_reg[71] ;\n output \\not_strict_mode.app_rd_data_reg[94] ;\n output \\not_strict_mode.app_rd_data_reg[78] ;\n output \\not_strict_mode.app_rd_data_reg[86] ;\n output \\not_strict_mode.app_rd_data_reg[70] ;\n output \\not_strict_mode.app_rd_data_reg[93] ;\n output \\not_strict_mode.app_rd_data_reg[77] ;\n output \\not_strict_mode.app_rd_data_reg[85] ;\n output \\not_strict_mode.app_rd_data_reg[69] ;\n output \\not_strict_mode.app_rd_data_reg[92] ;\n output \\not_strict_mode.app_rd_data_reg[76] ;\n output \\not_strict_mode.app_rd_data_reg[84] ;\n output \\not_strict_mode.app_rd_data_reg[68] ;\n output \\not_strict_mode.app_rd_data_reg[91] ;\n output \\not_strict_mode.app_rd_data_reg[75] ;\n output \\not_strict_mode.app_rd_data_reg[83] ;\n output \\not_strict_mode.app_rd_data_reg[67] ;\n output \\not_strict_mode.app_rd_data_reg[90] ;\n output \\not_strict_mode.app_rd_data_reg[74] ;\n output \\not_strict_mode.app_rd_data_reg[82] ;\n output \\not_strict_mode.app_rd_data_reg[66] ;\n output \\not_strict_mode.app_rd_data_reg[89] ;\n output \\not_strict_mode.app_rd_data_reg[73] ;\n output \\not_strict_mode.app_rd_data_reg[81] ;\n output \\not_strict_mode.app_rd_data_reg[65] ;\n output \\not_strict_mode.app_rd_data_reg[88] ;\n output \\not_strict_mode.app_rd_data_reg[72] ;\n output \\not_strict_mode.app_rd_data_reg[80] ;\n output \\not_strict_mode.app_rd_data_reg[64] ;\n output \\not_strict_mode.app_rd_data_reg[63] ;\n output \\not_strict_mode.app_rd_data_reg[47] ;\n output \\not_strict_mode.app_rd_data_reg[55] ;\n output \\not_strict_mode.app_rd_data_reg[39] ;\n output \\not_strict_mode.app_rd_data_reg[62] ;\n output \\not_strict_mode.app_rd_data_reg[46] ;\n output \\not_strict_mode.app_rd_data_reg[54] ;\n output \\not_strict_mode.app_rd_data_reg[38] ;\n output \\not_strict_mode.app_rd_data_reg[61] ;\n output \\not_strict_mode.app_rd_data_reg[45] ;\n output \\not_strict_mode.app_rd_data_reg[53] ;\n output \\not_strict_mode.app_rd_data_reg[37] ;\n output \\not_strict_mode.app_rd_data_reg[60] ;\n output \\not_strict_mode.app_rd_data_reg[44] ;\n output \\not_strict_mode.app_rd_data_reg[52] ;\n output \\not_strict_mode.app_rd_data_reg[36] ;\n output \\not_strict_mode.app_rd_data_reg[59] ;\n output \\not_strict_mode.app_rd_data_reg[43] ;\n output \\not_strict_mode.app_rd_data_reg[51] ;\n output \\not_strict_mode.app_rd_data_reg[35] ;\n output \\not_strict_mode.app_rd_data_reg[58] ;\n output \\not_strict_mode.app_rd_data_reg[42] ;\n output \\not_strict_mode.app_rd_data_reg[50] ;\n output \\not_strict_mode.app_rd_data_reg[34] ;\n output \\not_strict_mode.app_rd_data_reg[57] ;\n output \\not_strict_mode.app_rd_data_reg[41] ;\n output \\not_strict_mode.app_rd_data_reg[49] ;\n output \\not_strict_mode.app_rd_data_reg[33] ;\n output \\not_strict_mode.app_rd_data_reg[56] ;\n output \\not_strict_mode.app_rd_data_reg[40] ;\n output \\not_strict_mode.app_rd_data_reg[48] ;\n output \\not_strict_mode.app_rd_data_reg[32] ;\n output \\not_strict_mode.app_rd_data_reg[31] ;\n output \\not_strict_mode.app_rd_data_reg[15] ;\n output \\not_strict_mode.app_rd_data_reg[23] ;\n output \\not_strict_mode.app_rd_data_reg[7] ;\n output \\not_strict_mode.app_rd_data_reg[30] ;\n output \\not_strict_mode.app_rd_data_reg[14] ;\n output \\not_strict_mode.app_rd_data_reg[22] ;\n output \\not_strict_mode.app_rd_data_reg[6] ;\n output \\not_strict_mode.app_rd_data_reg[29] ;\n output \\not_strict_mode.app_rd_data_reg[13] ;\n output \\not_strict_mode.app_rd_data_reg[21] ;\n output \\not_strict_mode.app_rd_data_reg[5] ;\n output \\not_strict_mode.app_rd_data_reg[28] ;\n output \\not_strict_mode.app_rd_data_reg[12] ;\n output \\not_strict_mode.app_rd_data_reg[20] ;\n output \\not_strict_mode.app_rd_data_reg[4] ;\n output \\not_strict_mode.app_rd_data_reg[27] ;\n output \\not_strict_mode.app_rd_data_reg[11] ;\n output \\not_strict_mode.app_rd_data_reg[19] ;\n output \\not_strict_mode.app_rd_data_reg[3] ;\n output \\not_strict_mode.app_rd_data_reg[26] ;\n output \\not_strict_mode.app_rd_data_reg[10] ;\n output \\not_strict_mode.app_rd_data_reg[18] ;\n output \\not_strict_mode.app_rd_data_reg[2] ;\n output \\not_strict_mode.app_rd_data_reg[25] ;\n output \\not_strict_mode.app_rd_data_reg[9] ;\n output \\not_strict_mode.app_rd_data_reg[17] ;\n output \\not_strict_mode.app_rd_data_reg[1] ;\n output \\not_strict_mode.app_rd_data_reg[24] ;\n output \\not_strict_mode.app_rd_data_reg[8] ;\n output \\not_strict_mode.app_rd_data_reg[16] ;\n output \\not_strict_mode.app_rd_data_reg[0] ;\n output \\read_fifo.tail_r_reg[0] ;\n output \\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n output \\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n output \\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n output \\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n output \\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n output \\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n output \\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n output \\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n output [255:0]\\not_strict_mode.app_rd_data_reg[255]_0 ;\n output [0:0]of_ctl_full_v;\n output pd_out;\n output pi_phase_locked_all_r1_reg;\n output \\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ;\n output \\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ;\n output \\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ;\n output \\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ;\n output \\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ;\n output \\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ;\n output \\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ;\n output \\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ;\n output wr_en;\n output wr_en_5;\n output wr_en_6;\n output [8:0]fine_delay_mod;\n output [0:0]\\not_strict_mode.app_rd_data_reg[31]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[31]_1 ;\n output [63:0]\\my_empty_reg[7]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[23]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[23]_1 ;\n output [63:0]\\my_empty_reg[7]_1 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[15]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[15]_1 ;\n output [63:0]\\my_empty_reg[7]_2 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[7]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[7]_1 ;\n output [63:0]\\my_empty_reg[7]_3 ;\n output ofs_rdy_r_reg;\n output ofs_rdy_r_reg_0;\n output [4:0]\\po_rdval_cnt_reg[8] ;\n output [5:0]\\pi_rdval_cnt_reg[5] ;\n output [3:0]\\wr_ptr_timing_reg[2] ;\n output [3:0]\\wr_ptr_timing_reg[2]_0 ;\n output [3:0]\\wr_ptr_timing_reg[2]_1 ;\n output [4:0]\\po_rdval_cnt_reg[8]_0 ;\n output phy_if_empty_r_reg;\n output p_0_out;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n output \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n output \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n output \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n output \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n output [1:0]ddr_ck_out;\n inout [31:0]ddr3_dq;\n inout [3:0]ddr3_dqs_p;\n inout [3:0]ddr3_dqs_n;\n input mux_reset_n;\n input idle;\n input mmcm_ps_clk;\n input rst_sync_r1;\n input CLK;\n input mux_cmd_wren;\n input \\gen_byte_sel_div1.byte_sel_cnt_reg[2] ;\n input \\gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 ;\n input fine_delay_sel_reg;\n input \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ;\n input \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ;\n input \\gen_byte_sel_div1.byte_sel_cnt_reg[2]_1 ;\n input \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_1 ;\n input \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_2 ;\n input \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_3 ;\n input \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_4 ;\n input [3:0]init_calib_complete_reg_rep__6;\n input [3:0]D5;\n input [3:0]D6;\n input [2:0]D2;\n input [2:0]D3;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ;\n input [7:0]\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ;\n input [7:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ;\n input [3:0]D7;\n input [3:0]D8;\n input [3:0]D9;\n input [2:0]D0;\n input [2:0]D1;\n input \\calib_sel_reg[0] ;\n input \\gen_byte_sel_div1.calib_in_common_reg ;\n input \\calib_sel_reg[0]_0 ;\n input \\calib_sel_reg[0]_1 ;\n input freq_refclk;\n input mem_refclk;\n input \\calib_sel_reg[0]_2 ;\n input sync_pulse;\n input \\calib_sel_reg[1] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n input \\calib_sel_reg[1]_0 ;\n input \\calib_sel_reg[1]_1 ;\n input \\calib_sel_reg[1]_2 ;\n input \\calib_sel_reg[1]_3 ;\n input \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n input \\calib_sel_reg[1]_4 ;\n input \\calib_sel_reg[1]_5 ;\n input \\calib_sel_reg[1]_6 ;\n input pll_locked;\n input phy_read_calib;\n input in0;\n input phy_write_calib;\n input \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n input \\calib_sel_reg[0]_3 ;\n input pi_en_stg2_f_reg;\n input pi_stg2_f_incdec_reg;\n input \\gen_byte_sel_div1.calib_in_common_reg_3 ;\n input [5:0]COUNTERLOADVAL;\n input \\gen_byte_sel_div1.calib_in_common_reg_4 ;\n input ck_po_stg2_f_en_reg;\n input ck_po_stg2_f_indec_reg;\n input delay_done_r4_reg;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[255] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[254] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[253] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[252] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[251] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[250] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[249] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[248] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_5 ;\n input idelay_inc;\n input LD0;\n input CLKB0;\n input phy_if_reset;\n input \\gen_byte_sel_div1.calib_in_common_reg_6 ;\n input \\calib_sel_reg[0]_4 ;\n input pi_en_stg2_f_reg_0;\n input pi_stg2_f_incdec_reg_0;\n input \\gen_byte_sel_div1.calib_in_common_reg_7 ;\n input [5:0]\\calib_zero_inputs_reg[0] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_8 ;\n input ck_po_stg2_f_en_reg_0;\n input ck_po_stg2_f_indec_reg_0;\n input delay_done_r4_reg_0;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[247] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[246] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[245] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[244] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[243] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[242] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[241] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[240] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_9 ;\n input LD0_3;\n input CLKB0_7;\n input \\gen_byte_sel_div1.calib_in_common_reg_10 ;\n input \\calib_sel_reg[1]_7 ;\n input pi_en_stg2_f_reg_1;\n input pi_stg2_f_incdec_reg_1;\n input \\gen_byte_sel_div1.calib_in_common_reg_11 ;\n input [5:0]\\calib_zero_inputs_reg[0]_0 ;\n input \\gen_byte_sel_div1.calib_in_common_reg_12 ;\n input ck_po_stg2_f_en_reg_1;\n input ck_po_stg2_f_indec_reg_1;\n input delay_done_r4_reg_1;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[239] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[238] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[237] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[236] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[235] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[234] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[233] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[232] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_13 ;\n input LD0_4;\n input CLKB0_8;\n input \\gen_byte_sel_div1.calib_in_common_reg_14 ;\n input \\calib_sel_reg[0]_5 ;\n input pi_en_stg2_f_reg_2;\n input pi_stg2_f_incdec_reg_2;\n input \\gen_byte_sel_div1.calib_in_common_reg_15 ;\n input [5:0]\\calib_zero_inputs_reg[0]_1 ;\n input \\gen_byte_sel_div1.calib_in_common_reg_16 ;\n input ck_po_stg2_f_en_reg_2;\n input ck_po_stg2_f_indec_reg_2;\n input delay_done_r4_reg_2;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[231] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[230] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[229] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[228] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[227] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[226] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[225] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[224] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_17 ;\n input LD0_5;\n input CLKB0_9;\n input RST0;\n input rstdiv0_sync_r1_reg_rep__9;\n input \\gen_byte_sel_div1.byte_sel_cnt_reg[2]_2 ;\n input [11:0]mem_out;\n input [33:0]\\rd_ptr_reg[3] ;\n input mux_wrdata_en;\n input [17:0]\\rd_ptr_reg[3]_0 ;\n input [0:0]\\read_fifo.fifo_out_data_r_reg[6] ;\n input ram_init_done_r;\n input \\genblk9[6].fine_delay_incdec_pb_reg[6] ;\n input \\genblk9[5].fine_delay_incdec_pb_reg[5] ;\n input \\genblk9[7].fine_delay_incdec_pb_reg[7] ;\n input \\genblk9[4].fine_delay_incdec_pb_reg[4] ;\n input \\genblk9[3].fine_delay_incdec_pb_reg[3] ;\n input \\genblk9[4].fine_delay_incdec_pb_reg[4]_0 ;\n input init_calib_complete_reg_rep__5;\n input [0:0]mc_cas_n;\n input [1:0]\\cmd_pipe_plus.mc_address_reg[43] ;\n input init_calib_complete_reg_rep;\n input [31:0]Q;\n input prbs_rdlvl_start_reg;\n input out;\n input sys_rst;\n input [0:0]\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ;\n input mmcm_locked;\n input \\byte_r_reg[0]_0 ;\n input \\byte_r_reg[1] ;\n input [0:0]tail_r;\n input [1:0]\\rd_mux_sel_r_reg[1] ;\n input \\read_fifo.fifo_out_data_r_reg[6]_0 ;\n input [1:0]DOC;\n input [1:0]DOB;\n input [1:0]DOA;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ;\n input \\genblk9[0].fine_delay_incdec_pb_reg[0] ;\n input \\genblk9[1].fine_delay_incdec_pb_reg[1] ;\n input \\genblk9[2].fine_delay_incdec_pb_reg[2] ;\n input [1:0]\\gen_byte_sel_div1.byte_sel_cnt_reg[1] ;\n input [1:0]A;\n input rstdiv0_sync_r1_reg_rep__2;\n input [0:0]SR;\n input [10:0]D;\n input [5:0]\\cmd_pipe_plus.mc_data_offset_1_reg[5] ;\n input [255:0]mux_wrdata;\n input [31:0]mux_wrdata_mask;\n input [0:0]E;\n input [7:0]\\fine_delay_mod_reg[23]_0 ;\n input [0:0]\\gen_byte_sel_div1.calib_in_common_reg_18 ;\n input [7:0]\\calib_sel_reg[0]_6 ;\n input [0:0]\\gen_byte_sel_div1.calib_in_common_reg_19 ;\n input [7:0]\\calib_sel_reg[1]_8 ;\n input [0:0]\\gen_byte_sel_div1.calib_in_common_reg_20 ;\n input [7:0]\\calib_sel_reg[0]_7 ;\n input [2:0]\\calib_sel_reg[3] ;\n input [1:0]\\po_stg2_wrcal_cnt_reg[1] ;\n input D_po_coarse_enable110_out;\n input D_po_counter_read_en122_out;\n input D_po_fine_enable107_out;\n input D_po_fine_inc113_out;\n input D_po_sel_fine_oclk_delay125_out;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ;\n input [3:0]D4;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ;\n input [35:0]phy_dout;\n input init_calib_complete_reg_rep__6_0;\n\n wire [1:0]A;\n wire \\A[0]__0_n_0 ;\n wire \\A[0]__4_n_0 ;\n wire \\A[1]__0_n_0 ;\n wire \\A[1]__3_n_0 ;\n wire \\A[1]__4_n_0 ;\n wire \\A[2]__1_n_0 ;\n wire \\A_n_0_[1] ;\n wire CLK;\n wire CLKB0;\n wire CLKB0_7;\n wire CLKB0_8;\n wire CLKB0_9;\n wire [5:0]COUNTERLOADVAL;\n wire [10:0]D;\n wire [2:0]D0;\n wire [2:0]D1;\n wire [2:0]D2;\n wire [2:0]D3;\n wire [3:0]D4;\n wire [3:0]D5;\n wire [3:0]D6;\n wire [3:0]D7;\n wire [3:0]D8;\n wire [3:0]D9;\n wire [1:0]DOA;\n wire [1:0]DOB;\n wire [1:0]DOC;\n wire D_po_coarse_enable110_out;\n wire D_po_counter_read_en122_out;\n wire D_po_fine_enable107_out;\n wire D_po_fine_inc113_out;\n wire D_po_sel_fine_oclk_delay125_out;\n wire [0:0]E;\n wire LD0;\n wire LD0_3;\n wire LD0_4;\n wire LD0_5;\n wire [31:0]Q;\n wire RST0;\n wire [0:0]SR;\n wire \\byte_r_reg[0] ;\n wire \\byte_r_reg[0]_0 ;\n wire \\byte_r_reg[1] ;\n wire [1:1]byte_sel_data_map;\n wire \\calib_sel_reg[0] ;\n wire \\calib_sel_reg[0]_0 ;\n wire \\calib_sel_reg[0]_1 ;\n wire \\calib_sel_reg[0]_2 ;\n wire \\calib_sel_reg[0]_3 ;\n wire \\calib_sel_reg[0]_4 ;\n wire \\calib_sel_reg[0]_5 ;\n wire [7:0]\\calib_sel_reg[0]_6 ;\n wire [7:0]\\calib_sel_reg[0]_7 ;\n wire \\calib_sel_reg[1] ;\n wire \\calib_sel_reg[1]_0 ;\n wire \\calib_sel_reg[1]_1 ;\n wire \\calib_sel_reg[1]_2 ;\n wire \\calib_sel_reg[1]_3 ;\n wire \\calib_sel_reg[1]_4 ;\n wire \\calib_sel_reg[1]_5 ;\n wire \\calib_sel_reg[1]_6 ;\n wire \\calib_sel_reg[1]_7 ;\n wire [7:0]\\calib_sel_reg[1]_8 ;\n wire [2:0]\\calib_sel_reg[3] ;\n wire \\calib_seq_reg[0] ;\n wire [5:0]\\calib_zero_inputs_reg[0] ;\n wire [5:0]\\calib_zero_inputs_reg[0]_0 ;\n wire [5:0]\\calib_zero_inputs_reg[0]_1 ;\n wire ck_po_stg2_f_en_reg;\n wire ck_po_stg2_f_en_reg_0;\n wire ck_po_stg2_f_en_reg_1;\n wire ck_po_stg2_f_en_reg_2;\n wire ck_po_stg2_f_indec_reg;\n wire ck_po_stg2_f_indec_reg_0;\n wire ck_po_stg2_f_indec_reg_1;\n wire ck_po_stg2_f_indec_reg_2;\n wire [1:0]\\cmd_pipe_plus.mc_address_reg[43] ;\n wire [5:0]\\cmd_pipe_plus.mc_data_offset_1_reg[5] ;\n wire [63:0]\\data_bytes_r_reg[63] ;\n wire [5:0]data_offset_1_i1;\n wire [5:0]data_offset_1_i2;\n wire [14:0]ddr3_addr;\n wire [2:0]ddr3_ba;\n wire ddr3_cas_n;\n wire [0:0]ddr3_cke;\n wire [0:0]ddr3_cs_n;\n wire [3:0]ddr3_dm;\n wire [31:0]ddr3_dq;\n wire [3:0]ddr3_dqs_n;\n wire [3:0]ddr3_dqs_p;\n wire [0:0]ddr3_odt;\n wire ddr3_ras_n;\n wire ddr3_reset_n;\n wire ddr3_we_n;\n wire [1:0]ddr_ck_out;\n wire delay_done_r4_reg;\n wire delay_done_r4_reg_0;\n wire delay_done_r4_reg_1;\n wire delay_done_r4_reg_2;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;\n wire [8:0]fine_delay_mod;\n wire [11:2]fine_delay_mod0;\n wire \\fine_delay_mod[11]_i_10_n_0 ;\n wire \\fine_delay_mod[11]_i_11_n_0 ;\n wire \\fine_delay_mod[11]_i_12_n_0 ;\n wire \\fine_delay_mod[11]_i_1_n_0 ;\n wire \\fine_delay_mod[11]_i_2_n_0 ;\n wire \\fine_delay_mod[11]_i_3_n_0 ;\n wire \\fine_delay_mod[11]_i_4_n_0 ;\n wire \\fine_delay_mod[11]_i_5_n_0 ;\n wire \\fine_delay_mod[11]_i_7_n_0 ;\n wire \\fine_delay_mod[11]_i_9_n_0 ;\n wire \\fine_delay_mod[14]_i_1_n_0 ;\n wire \\fine_delay_mod[14]_i_2_n_0 ;\n wire \\fine_delay_mod[14]_i_3_n_0 ;\n wire \\fine_delay_mod[14]_i_4_n_0 ;\n wire \\fine_delay_mod[14]_i_5_n_0 ;\n wire \\fine_delay_mod[14]_i_6_n_0 ;\n wire \\fine_delay_mod[14]_i_7_n_0 ;\n wire \\fine_delay_mod[14]_i_8_n_0 ;\n wire \\fine_delay_mod[17]_i_1_n_0 ;\n wire \\fine_delay_mod[17]_i_2_n_0 ;\n wire \\fine_delay_mod[17]_i_3_n_0 ;\n wire \\fine_delay_mod[17]_i_4_n_0 ;\n wire \\fine_delay_mod[17]_i_5_n_0 ;\n wire \\fine_delay_mod[17]_i_6_n_0 ;\n wire \\fine_delay_mod[17]_i_7_n_0 ;\n wire \\fine_delay_mod[17]_i_8_n_0 ;\n wire \\fine_delay_mod[17]_i_9_n_0 ;\n wire \\fine_delay_mod[20]_i_1_n_0 ;\n wire \\fine_delay_mod[20]_i_2_n_0 ;\n wire \\fine_delay_mod[20]_i_3_n_0 ;\n wire \\fine_delay_mod[20]_i_4_n_0 ;\n wire \\fine_delay_mod[20]_i_5_n_0 ;\n wire \\fine_delay_mod[20]_i_6_n_0 ;\n wire \\fine_delay_mod[20]_i_7_n_0 ;\n wire \\fine_delay_mod[20]_i_8_n_0 ;\n wire \\fine_delay_mod[20]_i_9_n_0 ;\n wire \\fine_delay_mod[23]_i_10_n_0 ;\n wire \\fine_delay_mod[23]_i_1_n_0 ;\n wire \\fine_delay_mod[23]_i_2_n_0 ;\n wire \\fine_delay_mod[23]_i_3_n_0 ;\n wire \\fine_delay_mod[23]_i_4_n_0 ;\n wire \\fine_delay_mod[23]_i_5_n_0 ;\n wire \\fine_delay_mod[23]_i_6_n_0 ;\n wire \\fine_delay_mod[23]_i_7_n_0 ;\n wire \\fine_delay_mod[23]_i_8_n_0 ;\n wire \\fine_delay_mod[23]_i_9_n_0 ;\n wire \\fine_delay_mod[26]_i_1_n_0 ;\n wire \\fine_delay_mod[2]_i_10_n_0 ;\n wire \\fine_delay_mod[2]_i_1_n_0 ;\n wire \\fine_delay_mod[2]_i_2_n_0 ;\n wire \\fine_delay_mod[2]_i_3_n_0 ;\n wire \\fine_delay_mod[2]_i_4_n_0 ;\n wire \\fine_delay_mod[2]_i_5_n_0 ;\n wire \\fine_delay_mod[2]_i_7_n_0 ;\n wire \\fine_delay_mod[2]_i_8_n_0 ;\n wire \\fine_delay_mod[2]_i_9_n_0 ;\n wire \\fine_delay_mod[5]_i_10_n_0 ;\n wire \\fine_delay_mod[5]_i_11_n_0 ;\n wire \\fine_delay_mod[5]_i_12_n_0 ;\n wire \\fine_delay_mod[5]_i_1_n_0 ;\n wire \\fine_delay_mod[5]_i_2_n_0 ;\n wire \\fine_delay_mod[5]_i_3_n_0 ;\n wire \\fine_delay_mod[5]_i_4_n_0 ;\n wire \\fine_delay_mod[5]_i_5_n_0 ;\n wire \\fine_delay_mod[5]_i_7_n_0 ;\n wire \\fine_delay_mod[5]_i_8_n_0 ;\n wire \\fine_delay_mod[5]_i_9_n_0 ;\n wire \\fine_delay_mod[8]_i_10_n_0 ;\n wire \\fine_delay_mod[8]_i_1_n_0 ;\n wire \\fine_delay_mod[8]_i_2_n_0 ;\n wire \\fine_delay_mod[8]_i_3_n_0 ;\n wire \\fine_delay_mod[8]_i_4_n_0 ;\n wire \\fine_delay_mod[8]_i_5_n_0 ;\n wire \\fine_delay_mod[8]_i_7_n_0 ;\n wire \\fine_delay_mod[8]_i_8_n_0 ;\n wire \\fine_delay_mod[8]_i_9_n_0 ;\n wire [7:0]\\fine_delay_mod_reg[23]_0 ;\n wire \\fine_delay_mod_reg[26]_0 ;\n wire fine_delay_sel_r;\n wire fine_delay_sel_reg;\n wire freq_refclk;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_1 ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_2 ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_3 ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_4 ;\n wire [1:0]\\gen_byte_sel_div1.byte_sel_cnt_reg[1] ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[2] ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[2]_1 ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[2]_2 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_10 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_11 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_12 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_13 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_14 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_15 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_16 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_17 ;\n wire [0:0]\\gen_byte_sel_div1.calib_in_common_reg_18 ;\n wire [0:0]\\gen_byte_sel_div1.calib_in_common_reg_19 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n wire [0:0]\\gen_byte_sel_div1.calib_in_common_reg_20 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_3 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_4 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_5 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_6 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_7 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_8 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_9 ;\n wire \\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n wire \\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n wire \\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n wire \\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;\n wire \\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n wire \\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n wire \\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n wire \\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n wire [7:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ;\n wire [7:0]\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ;\n wire \\genblk9[0].fine_delay_incdec_pb_reg[0] ;\n wire \\genblk9[1].fine_delay_incdec_pb_reg[1] ;\n wire \\genblk9[2].fine_delay_incdec_pb_reg[2] ;\n wire \\genblk9[3].fine_delay_incdec_pb_reg[3] ;\n wire \\genblk9[4].fine_delay_incdec_pb_reg[4] ;\n wire \\genblk9[4].fine_delay_incdec_pb_reg[4]_0 ;\n wire \\genblk9[5].fine_delay_incdec_pb_reg[5] ;\n wire \\genblk9[6].fine_delay_incdec_pb_reg[6] ;\n wire \\genblk9[7].fine_delay_incdec_pb_reg[7] ;\n wire idelay_inc;\n wire idelay_ld_rst;\n wire idelay_ld_rst_0;\n wire idelay_ld_rst_1;\n wire idelay_ld_rst_2;\n wire idle;\n wire in0;\n wire in_dqs_lpbk_to_iddr_0;\n wire in_dqs_lpbk_to_iddr_1;\n wire in_dqs_lpbk_to_iddr_2;\n wire in_dqs_lpbk_to_iddr_3;\n wire init_calib_complete_reg_rep;\n wire init_calib_complete_reg_rep__5;\n wire [3:0]init_calib_complete_reg_rep__6;\n wire init_calib_complete_reg_rep__6_0;\n wire [0:0]mc_cas_n;\n wire [38:0]mem_dq_in;\n wire [93:0]mem_dq_out;\n wire [45:0]mem_dq_ts;\n wire [3:0]mem_dqs_in;\n wire [3:0]mem_dqs_out;\n wire [3:0]mem_dqs_ts;\n wire [11:0]mem_out;\n wire mem_refclk;\n wire mmcm_locked;\n wire mmcm_ps_clk;\n wire mux_cmd_wren;\n wire mux_rd_valid_r_reg;\n wire mux_reset_n;\n wire [255:0]mux_wrdata;\n wire mux_wrdata_en;\n wire [31:0]mux_wrdata_mask;\n wire \\my_empty_reg[1] ;\n wire \\my_empty_reg[1]_0 ;\n wire \\my_empty_reg[1]_1 ;\n wire \\my_empty_reg[1]_2 ;\n wire \\my_empty_reg[1]_3 ;\n wire \\my_empty_reg[1]_4 ;\n wire \\my_empty_reg[1]_5 ;\n wire \\my_empty_reg[1]_6 ;\n wire [31:0]\\my_empty_reg[7] ;\n wire [63:0]\\my_empty_reg[7]_0 ;\n wire [63:0]\\my_empty_reg[7]_1 ;\n wire [63:0]\\my_empty_reg[7]_2 ;\n wire [63:0]\\my_empty_reg[7]_3 ;\n wire \\not_strict_mode.app_rd_data_reg[0] ;\n wire \\not_strict_mode.app_rd_data_reg[100] ;\n wire \\not_strict_mode.app_rd_data_reg[101] ;\n wire \\not_strict_mode.app_rd_data_reg[102] ;\n wire \\not_strict_mode.app_rd_data_reg[103] ;\n wire \\not_strict_mode.app_rd_data_reg[104] ;\n wire \\not_strict_mode.app_rd_data_reg[105] ;\n wire \\not_strict_mode.app_rd_data_reg[106] ;\n wire \\not_strict_mode.app_rd_data_reg[107] ;\n wire \\not_strict_mode.app_rd_data_reg[108] ;\n wire \\not_strict_mode.app_rd_data_reg[109] ;\n wire \\not_strict_mode.app_rd_data_reg[10] ;\n wire \\not_strict_mode.app_rd_data_reg[110] ;\n wire \\not_strict_mode.app_rd_data_reg[111] ;\n wire \\not_strict_mode.app_rd_data_reg[112] ;\n wire \\not_strict_mode.app_rd_data_reg[113] ;\n wire \\not_strict_mode.app_rd_data_reg[114] ;\n wire \\not_strict_mode.app_rd_data_reg[115] ;\n wire \\not_strict_mode.app_rd_data_reg[116] ;\n wire \\not_strict_mode.app_rd_data_reg[117] ;\n wire \\not_strict_mode.app_rd_data_reg[118] ;\n wire \\not_strict_mode.app_rd_data_reg[119] ;\n wire \\not_strict_mode.app_rd_data_reg[11] ;\n wire \\not_strict_mode.app_rd_data_reg[120] ;\n wire \\not_strict_mode.app_rd_data_reg[121] ;\n wire \\not_strict_mode.app_rd_data_reg[122] ;\n wire \\not_strict_mode.app_rd_data_reg[123] ;\n wire \\not_strict_mode.app_rd_data_reg[124] ;\n wire \\not_strict_mode.app_rd_data_reg[125] ;\n wire \\not_strict_mode.app_rd_data_reg[126] ;\n wire \\not_strict_mode.app_rd_data_reg[127] ;\n wire \\not_strict_mode.app_rd_data_reg[128] ;\n wire \\not_strict_mode.app_rd_data_reg[129] ;\n wire \\not_strict_mode.app_rd_data_reg[12] ;\n wire \\not_strict_mode.app_rd_data_reg[130] ;\n wire \\not_strict_mode.app_rd_data_reg[131] ;\n wire \\not_strict_mode.app_rd_data_reg[132] ;\n wire \\not_strict_mode.app_rd_data_reg[133] ;\n wire \\not_strict_mode.app_rd_data_reg[134] ;\n wire \\not_strict_mode.app_rd_data_reg[135] ;\n wire \\not_strict_mode.app_rd_data_reg[136] ;\n wire \\not_strict_mode.app_rd_data_reg[137] ;\n wire \\not_strict_mode.app_rd_data_reg[138] ;\n wire \\not_strict_mode.app_rd_data_reg[139] ;\n wire \\not_strict_mode.app_rd_data_reg[13] ;\n wire \\not_strict_mode.app_rd_data_reg[140] ;\n wire \\not_strict_mode.app_rd_data_reg[141] ;\n wire \\not_strict_mode.app_rd_data_reg[142] ;\n wire \\not_strict_mode.app_rd_data_reg[143] ;\n wire \\not_strict_mode.app_rd_data_reg[144] ;\n wire \\not_strict_mode.app_rd_data_reg[145] ;\n wire \\not_strict_mode.app_rd_data_reg[146] ;\n wire \\not_strict_mode.app_rd_data_reg[147] ;\n wire \\not_strict_mode.app_rd_data_reg[148] ;\n wire \\not_strict_mode.app_rd_data_reg[149] ;\n wire \\not_strict_mode.app_rd_data_reg[14] ;\n wire \\not_strict_mode.app_rd_data_reg[150] ;\n wire \\not_strict_mode.app_rd_data_reg[151] ;\n wire \\not_strict_mode.app_rd_data_reg[152] ;\n wire \\not_strict_mode.app_rd_data_reg[153] ;\n wire \\not_strict_mode.app_rd_data_reg[154] ;\n wire \\not_strict_mode.app_rd_data_reg[155] ;\n wire \\not_strict_mode.app_rd_data_reg[156] ;\n wire \\not_strict_mode.app_rd_data_reg[157] ;\n wire \\not_strict_mode.app_rd_data_reg[158] ;\n wire \\not_strict_mode.app_rd_data_reg[159] ;\n wire \\not_strict_mode.app_rd_data_reg[15] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[15]_0 ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[15]_1 ;\n wire \\not_strict_mode.app_rd_data_reg[160] ;\n wire \\not_strict_mode.app_rd_data_reg[161] ;\n wire \\not_strict_mode.app_rd_data_reg[162] ;\n wire \\not_strict_mode.app_rd_data_reg[163] ;\n wire \\not_strict_mode.app_rd_data_reg[164] ;\n wire \\not_strict_mode.app_rd_data_reg[165] ;\n wire \\not_strict_mode.app_rd_data_reg[166] ;\n wire \\not_strict_mode.app_rd_data_reg[167] ;\n wire \\not_strict_mode.app_rd_data_reg[168] ;\n wire \\not_strict_mode.app_rd_data_reg[169] ;\n wire \\not_strict_mode.app_rd_data_reg[16] ;\n wire \\not_strict_mode.app_rd_data_reg[170] ;\n wire \\not_strict_mode.app_rd_data_reg[171] ;\n wire \\not_strict_mode.app_rd_data_reg[172] ;\n wire \\not_strict_mode.app_rd_data_reg[173] ;\n wire \\not_strict_mode.app_rd_data_reg[174] ;\n wire \\not_strict_mode.app_rd_data_reg[175] ;\n wire \\not_strict_mode.app_rd_data_reg[176] ;\n wire \\not_strict_mode.app_rd_data_reg[177] ;\n wire \\not_strict_mode.app_rd_data_reg[178] ;\n wire \\not_strict_mode.app_rd_data_reg[179] ;\n wire \\not_strict_mode.app_rd_data_reg[17] ;\n wire \\not_strict_mode.app_rd_data_reg[180] ;\n wire \\not_strict_mode.app_rd_data_reg[181] ;\n wire \\not_strict_mode.app_rd_data_reg[182] ;\n wire \\not_strict_mode.app_rd_data_reg[183] ;\n wire \\not_strict_mode.app_rd_data_reg[184] ;\n wire \\not_strict_mode.app_rd_data_reg[185] ;\n wire \\not_strict_mode.app_rd_data_reg[186] ;\n wire \\not_strict_mode.app_rd_data_reg[187] ;\n wire \\not_strict_mode.app_rd_data_reg[188] ;\n wire \\not_strict_mode.app_rd_data_reg[189] ;\n wire \\not_strict_mode.app_rd_data_reg[18] ;\n wire \\not_strict_mode.app_rd_data_reg[190] ;\n wire \\not_strict_mode.app_rd_data_reg[191] ;\n wire \\not_strict_mode.app_rd_data_reg[192] ;\n wire \\not_strict_mode.app_rd_data_reg[193] ;\n wire \\not_strict_mode.app_rd_data_reg[194] ;\n wire \\not_strict_mode.app_rd_data_reg[195] ;\n wire \\not_strict_mode.app_rd_data_reg[196] ;\n wire \\not_strict_mode.app_rd_data_reg[197] ;\n wire \\not_strict_mode.app_rd_data_reg[198] ;\n wire \\not_strict_mode.app_rd_data_reg[199] ;\n wire \\not_strict_mode.app_rd_data_reg[19] ;\n wire \\not_strict_mode.app_rd_data_reg[1] ;\n wire \\not_strict_mode.app_rd_data_reg[200] ;\n wire \\not_strict_mode.app_rd_data_reg[201] ;\n wire \\not_strict_mode.app_rd_data_reg[202] ;\n wire \\not_strict_mode.app_rd_data_reg[203] ;\n wire \\not_strict_mode.app_rd_data_reg[204] ;\n wire \\not_strict_mode.app_rd_data_reg[205] ;\n wire \\not_strict_mode.app_rd_data_reg[206] ;\n wire \\not_strict_mode.app_rd_data_reg[207] ;\n wire \\not_strict_mode.app_rd_data_reg[208] ;\n wire \\not_strict_mode.app_rd_data_reg[209] ;\n wire \\not_strict_mode.app_rd_data_reg[20] ;\n wire \\not_strict_mode.app_rd_data_reg[210] ;\n wire \\not_strict_mode.app_rd_data_reg[211] ;\n wire \\not_strict_mode.app_rd_data_reg[212] ;\n wire \\not_strict_mode.app_rd_data_reg[213] ;\n wire \\not_strict_mode.app_rd_data_reg[214] ;\n wire \\not_strict_mode.app_rd_data_reg[215] ;\n wire \\not_strict_mode.app_rd_data_reg[216] ;\n wire \\not_strict_mode.app_rd_data_reg[217] ;\n wire \\not_strict_mode.app_rd_data_reg[218] ;\n wire \\not_strict_mode.app_rd_data_reg[219] ;\n wire \\not_strict_mode.app_rd_data_reg[21] ;\n wire \\not_strict_mode.app_rd_data_reg[220] ;\n wire \\not_strict_mode.app_rd_data_reg[221] ;\n wire \\not_strict_mode.app_rd_data_reg[222] ;\n wire \\not_strict_mode.app_rd_data_reg[223] ;\n wire \\not_strict_mode.app_rd_data_reg[224] ;\n wire \\not_strict_mode.app_rd_data_reg[225] ;\n wire \\not_strict_mode.app_rd_data_reg[226] ;\n wire \\not_strict_mode.app_rd_data_reg[227] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[228] ;\n wire \\not_strict_mode.app_rd_data_reg[228]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[229] ;\n wire \\not_strict_mode.app_rd_data_reg[22] ;\n wire \\not_strict_mode.app_rd_data_reg[230] ;\n wire \\not_strict_mode.app_rd_data_reg[231] ;\n wire \\not_strict_mode.app_rd_data_reg[232] ;\n wire \\not_strict_mode.app_rd_data_reg[233] ;\n wire \\not_strict_mode.app_rd_data_reg[234] ;\n wire \\not_strict_mode.app_rd_data_reg[235] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[236] ;\n wire \\not_strict_mode.app_rd_data_reg[236]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[237] ;\n wire \\not_strict_mode.app_rd_data_reg[238] ;\n wire \\not_strict_mode.app_rd_data_reg[239] ;\n wire \\not_strict_mode.app_rd_data_reg[23] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[23]_0 ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[23]_1 ;\n wire \\not_strict_mode.app_rd_data_reg[240] ;\n wire \\not_strict_mode.app_rd_data_reg[241] ;\n wire \\not_strict_mode.app_rd_data_reg[242] ;\n wire \\not_strict_mode.app_rd_data_reg[243] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[244] ;\n wire \\not_strict_mode.app_rd_data_reg[244]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[245] ;\n wire \\not_strict_mode.app_rd_data_reg[246] ;\n wire \\not_strict_mode.app_rd_data_reg[247] ;\n wire \\not_strict_mode.app_rd_data_reg[248] ;\n wire \\not_strict_mode.app_rd_data_reg[249] ;\n wire \\not_strict_mode.app_rd_data_reg[24] ;\n wire \\not_strict_mode.app_rd_data_reg[250] ;\n wire \\not_strict_mode.app_rd_data_reg[251] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[252] ;\n wire \\not_strict_mode.app_rd_data_reg[252]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[253] ;\n wire \\not_strict_mode.app_rd_data_reg[254] ;\n wire \\not_strict_mode.app_rd_data_reg[255] ;\n wire [255:0]\\not_strict_mode.app_rd_data_reg[255]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[25] ;\n wire \\not_strict_mode.app_rd_data_reg[26] ;\n wire \\not_strict_mode.app_rd_data_reg[27] ;\n wire \\not_strict_mode.app_rd_data_reg[28] ;\n wire \\not_strict_mode.app_rd_data_reg[29] ;\n wire \\not_strict_mode.app_rd_data_reg[2] ;\n wire \\not_strict_mode.app_rd_data_reg[30] ;\n wire \\not_strict_mode.app_rd_data_reg[31] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[31]_0 ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[31]_1 ;\n wire \\not_strict_mode.app_rd_data_reg[32] ;\n wire \\not_strict_mode.app_rd_data_reg[33] ;\n wire \\not_strict_mode.app_rd_data_reg[34] ;\n wire \\not_strict_mode.app_rd_data_reg[35] ;\n wire \\not_strict_mode.app_rd_data_reg[36] ;\n wire \\not_strict_mode.app_rd_data_reg[37] ;\n wire \\not_strict_mode.app_rd_data_reg[38] ;\n wire \\not_strict_mode.app_rd_data_reg[39] ;\n wire \\not_strict_mode.app_rd_data_reg[3] ;\n wire \\not_strict_mode.app_rd_data_reg[40] ;\n wire \\not_strict_mode.app_rd_data_reg[41] ;\n wire \\not_strict_mode.app_rd_data_reg[42] ;\n wire \\not_strict_mode.app_rd_data_reg[43] ;\n wire \\not_strict_mode.app_rd_data_reg[44] ;\n wire \\not_strict_mode.app_rd_data_reg[45] ;\n wire \\not_strict_mode.app_rd_data_reg[46] ;\n wire \\not_strict_mode.app_rd_data_reg[47] ;\n wire \\not_strict_mode.app_rd_data_reg[48] ;\n wire \\not_strict_mode.app_rd_data_reg[49] ;\n wire \\not_strict_mode.app_rd_data_reg[4] ;\n wire \\not_strict_mode.app_rd_data_reg[50] ;\n wire \\not_strict_mode.app_rd_data_reg[51] ;\n wire \\not_strict_mode.app_rd_data_reg[52] ;\n wire \\not_strict_mode.app_rd_data_reg[53] ;\n wire \\not_strict_mode.app_rd_data_reg[54] ;\n wire \\not_strict_mode.app_rd_data_reg[55] ;\n wire \\not_strict_mode.app_rd_data_reg[56] ;\n wire \\not_strict_mode.app_rd_data_reg[57] ;\n wire \\not_strict_mode.app_rd_data_reg[58] ;\n wire \\not_strict_mode.app_rd_data_reg[59] ;\n wire \\not_strict_mode.app_rd_data_reg[5] ;\n wire \\not_strict_mode.app_rd_data_reg[60] ;\n wire \\not_strict_mode.app_rd_data_reg[61] ;\n wire \\not_strict_mode.app_rd_data_reg[62] ;\n wire \\not_strict_mode.app_rd_data_reg[63] ;\n wire \\not_strict_mode.app_rd_data_reg[64] ;\n wire \\not_strict_mode.app_rd_data_reg[65] ;\n wire \\not_strict_mode.app_rd_data_reg[66] ;\n wire \\not_strict_mode.app_rd_data_reg[67] ;\n wire \\not_strict_mode.app_rd_data_reg[68] ;\n wire \\not_strict_mode.app_rd_data_reg[69] ;\n wire \\not_strict_mode.app_rd_data_reg[6] ;\n wire \\not_strict_mode.app_rd_data_reg[70] ;\n wire \\not_strict_mode.app_rd_data_reg[71] ;\n wire \\not_strict_mode.app_rd_data_reg[72] ;\n wire \\not_strict_mode.app_rd_data_reg[73] ;\n wire \\not_strict_mode.app_rd_data_reg[74] ;\n wire \\not_strict_mode.app_rd_data_reg[75] ;\n wire \\not_strict_mode.app_rd_data_reg[76] ;\n wire \\not_strict_mode.app_rd_data_reg[77] ;\n wire \\not_strict_mode.app_rd_data_reg[78] ;\n wire \\not_strict_mode.app_rd_data_reg[79] ;\n wire \\not_strict_mode.app_rd_data_reg[7] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[7]_0 ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[7]_1 ;\n wire \\not_strict_mode.app_rd_data_reg[80] ;\n wire \\not_strict_mode.app_rd_data_reg[81] ;\n wire \\not_strict_mode.app_rd_data_reg[82] ;\n wire \\not_strict_mode.app_rd_data_reg[83] ;\n wire \\not_strict_mode.app_rd_data_reg[84] ;\n wire \\not_strict_mode.app_rd_data_reg[85] ;\n wire \\not_strict_mode.app_rd_data_reg[86] ;\n wire \\not_strict_mode.app_rd_data_reg[87] ;\n wire \\not_strict_mode.app_rd_data_reg[88] ;\n wire \\not_strict_mode.app_rd_data_reg[89] ;\n wire \\not_strict_mode.app_rd_data_reg[8] ;\n wire \\not_strict_mode.app_rd_data_reg[90] ;\n wire \\not_strict_mode.app_rd_data_reg[91] ;\n wire \\not_strict_mode.app_rd_data_reg[92] ;\n wire \\not_strict_mode.app_rd_data_reg[93] ;\n wire \\not_strict_mode.app_rd_data_reg[94] ;\n wire \\not_strict_mode.app_rd_data_reg[95] ;\n wire \\not_strict_mode.app_rd_data_reg[96] ;\n wire \\not_strict_mode.app_rd_data_reg[97] ;\n wire \\not_strict_mode.app_rd_data_reg[98] ;\n wire \\not_strict_mode.app_rd_data_reg[99] ;\n wire \\not_strict_mode.app_rd_data_reg[9] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ;\n wire \\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n wire [0:0]of_ctl_full_v;\n wire ofs_rdy_r_reg;\n wire ofs_rdy_r_reg_0;\n wire out;\n wire p_0_out;\n wire pd_out;\n wire [2:0]pd_out_pre;\n wire [24:0]phy_ctl_wd_i1;\n wire [24:0]phy_ctl_wd_i2;\n wire phy_ctl_wr_i1;\n wire phy_ctl_wr_i2;\n wire [35:0]phy_dout;\n wire phy_if_empty_r_reg;\n wire phy_if_reset;\n wire phy_mc_ctl_full;\n wire phy_rddata_en;\n wire phy_read_calib;\n wire phy_write_calib;\n wire [3:0]\\pi_dqs_found_lanes_r1_reg[3] ;\n wire pi_en_stg2_f_reg;\n wire pi_en_stg2_f_reg_0;\n wire pi_en_stg2_f_reg_1;\n wire pi_en_stg2_f_reg_2;\n wire pi_phase_locked_all_r1_reg;\n wire [5:0]\\pi_rdval_cnt_reg[5] ;\n wire pi_stg2_f_incdec_reg;\n wire pi_stg2_f_incdec_reg_0;\n wire pi_stg2_f_incdec_reg_1;\n wire pi_stg2_f_incdec_reg_2;\n wire pll_locked;\n wire [5:0]\\po_counter_read_val_r_reg[5] ;\n wire [4:0]\\po_rdval_cnt_reg[8] ;\n wire [4:0]\\po_rdval_cnt_reg[8]_0 ;\n wire [1:0]\\po_stg2_wrcal_cnt_reg[1] ;\n wire prbs_rdlvl_start_reg;\n wire ram_init_done_r;\n wire rd_buf_we;\n wire [1:0]\\rd_mux_sel_r_reg[1] ;\n wire [33:0]\\rd_ptr_reg[3] ;\n wire [17:0]\\rd_ptr_reg[3]_0 ;\n wire \\rd_ptr_timing_reg[2] ;\n wire \\rd_ptr_timing_reg[2]_0 ;\n wire \\rd_ptr_timing_reg[2]_1 ;\n wire \\rd_ptr_timing_reg[2]_10 ;\n wire \\rd_ptr_timing_reg[2]_2 ;\n wire \\rd_ptr_timing_reg[2]_3 ;\n wire \\rd_ptr_timing_reg[2]_4 ;\n wire \\rd_ptr_timing_reg[2]_5 ;\n wire \\rd_ptr_timing_reg[2]_6 ;\n wire \\rd_ptr_timing_reg[2]_7 ;\n wire \\rd_ptr_timing_reg[2]_8 ;\n wire \\rd_ptr_timing_reg[2]_9 ;\n wire [0:0]\\read_fifo.fifo_out_data_r_reg[6] ;\n wire \\read_fifo.fifo_out_data_r_reg[6]_0 ;\n wire \\read_fifo.tail_r_reg[0] ;\n wire [0:0]\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ;\n wire rst_sync_r1;\n wire rst_sync_r1_reg;\n wire rstdiv0_sync_r1_reg_rep__2;\n wire rstdiv0_sync_r1_reg_rep__9;\n wire sync_pulse;\n wire sys_rst;\n wire [0:0]tail_r;\n wire wr_en;\n wire wr_en_5;\n wire wr_en_6;\n wire [3:0]\\wr_ptr_timing_reg[2] ;\n wire [3:0]\\wr_ptr_timing_reg[2]_0 ;\n wire [3:0]\\wr_ptr_timing_reg[2]_1 ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[224] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[225] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[226] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[227] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[228] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[229] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[230] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[231] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[232] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[233] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[234] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[235] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[236] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[237] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[238] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[239] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[240] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[241] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[242] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[243] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[244] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[245] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[246] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[247] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[248] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[249] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[250] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[251] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[252] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[253] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[254] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[255] ;\n\n FDRE \\A[0]__0 \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ),\n .Q(\\A[0]__0_n_0 ),\n .R(1'b0));\n FDRE \\A[0]__4 \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_byte_sel_div1.byte_sel_cnt_reg[0]_1 ),\n .Q(\\A[0]__4_n_0 ),\n .R(1'b0));\n FDSE \\A[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 ),\n .Q(\\A_n_0_[1] ),\n .S(\\gen_byte_sel_div1.byte_sel_cnt_reg[2] ));\n FDSE \\A[1]__0 \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_byte_sel_div1.byte_sel_cnt_reg[0]_2 ),\n .Q(\\A[1]__0_n_0 ),\n .S(\\gen_byte_sel_div1.byte_sel_cnt_reg[2] ));\n FDSE \\A[1]__3 \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_byte_sel_div1.byte_sel_cnt_reg[0]_3 ),\n .Q(\\A[1]__3_n_0 ),\n .S(\\gen_byte_sel_div1.byte_sel_cnt_reg[2] ));\n FDSE \\A[1]__4 \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_byte_sel_div1.byte_sel_cnt_reg[0]_4 ),\n .Q(\\A[1]__4_n_0 ),\n .S(\\gen_byte_sel_div1.byte_sel_cnt_reg[2] ));\n FDRE \\A[2]__1 \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_byte_sel_div1.byte_sel_cnt_reg[2]_1 ),\n .Q(\\A[2]__1_n_0 ),\n .R(1'b0));\n FDRE \\A[2]__2 \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_byte_sel_div1.byte_sel_cnt_reg[0] ),\n .Q(\\fine_delay_mod_reg[26]_0 ),\n .R(1'b0));\n FDRE \\byte_sel_data_map_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_byte_sel_div1.byte_sel_cnt_reg[2]_2 ),\n .Q(byte_sel_data_map),\n .R(1'b0));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CAPACITANCE = \"DONT_CARE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\cke_odt_thru_outfifo.gen_cke_obuf[0].u_cs_n_obuf \n (.I(mem_dq_out[71]),\n .O(ddr3_cke));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CAPACITANCE = \"DONT_CARE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\cke_odt_thru_outfifo.gen_odt_obuf.gen_odt_obuf[0].u_cs_n_obuf \n (.I(mem_dq_out[70]),\n .O(ddr3_odt));\n FDRE \\data_offset_1_i1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [0]),\n .Q(data_offset_1_i1[0]),\n .R(1'b0));\n FDRE \\data_offset_1_i1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [1]),\n .Q(data_offset_1_i1[1]),\n .R(1'b0));\n FDRE \\data_offset_1_i1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [2]),\n .Q(data_offset_1_i1[2]),\n .R(1'b0));\n FDRE \\data_offset_1_i1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [3]),\n .Q(data_offset_1_i1[3]),\n .R(1'b0));\n FDRE \\data_offset_1_i1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [4]),\n .Q(data_offset_1_i1[4]),\n .R(1'b0));\n FDRE \\data_offset_1_i1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [5]),\n .Q(data_offset_1_i1[5]),\n .R(1'b0));\n FDRE \\data_offset_1_i2_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(data_offset_1_i1[0]),\n .Q(data_offset_1_i2[0]),\n .R(1'b0));\n FDRE \\data_offset_1_i2_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(data_offset_1_i1[1]),\n .Q(data_offset_1_i2[1]),\n .R(1'b0));\n FDRE \\data_offset_1_i2_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(data_offset_1_i1[2]),\n .Q(data_offset_1_i2[2]),\n .R(1'b0));\n FDRE \\data_offset_1_i2_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(data_offset_1_i1[3]),\n .Q(data_offset_1_i2[3]),\n .R(1'b0));\n FDRE \\data_offset_1_i2_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(data_offset_1_i1[4]),\n .Q(data_offset_1_i2[4]),\n .R(1'b0));\n FDRE \\data_offset_1_i2_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(data_offset_1_i1[5]),\n .Q(data_offset_1_i2[5]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFFEFFFFFFFE0000)) \n \\fine_delay_mod[11]_i_1 \n (.I0(\\fine_delay_mod[11]_i_2_n_0 ),\n .I1(\\fine_delay_mod[11]_i_3_n_0 ),\n .I2(\\fine_delay_mod[11]_i_4_n_0 ),\n .I3(\\fine_delay_mod[11]_i_5_n_0 ),\n .I4(fine_delay_mod0[11]),\n .I5(fine_delay_mod[3]),\n .O(\\fine_delay_mod[11]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1027\" *) \n LUT5 #(\n .INIT(32'h00575757)) \n \\fine_delay_mod[11]_i_10 \n (.I0(\\A[0]__4_n_0 ),\n .I1(\\A[1]__4_n_0 ),\n .I2(byte_sel_data_map),\n .I3(\\fine_delay_mod_reg[26]_0 ),\n .I4(\\A[1]__3_n_0 ),\n .O(\\fine_delay_mod[11]_i_10_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1026\" *) \n LUT5 #(\n .INIT(32'h0000F888)) \n \\fine_delay_mod[11]_i_11 \n (.I0(\\A[1]__0_n_0 ),\n .I1(\\A[0]__0_n_0 ),\n .I2(\\fine_delay_mod_reg[26]_0 ),\n .I3(\\A_n_0_[1] ),\n .I4(\\A[2]__1_n_0 ),\n .O(\\fine_delay_mod[11]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'h0088008800F80088)) \n \\fine_delay_mod[11]_i_12 \n (.I0(\\A[0]__4_n_0 ),\n .I1(byte_sel_data_map),\n .I2(\\A[0]__0_n_0 ),\n .I3(\\fine_delay_mod_reg[26]_0 ),\n .I4(byte_sel_data_map),\n .I5(\\A[0]__0_n_0 ),\n .O(\\fine_delay_mod[11]_i_12_n_0 ));\n LUT6 #(\n .INIT(64'hF780808080808080)) \n \\fine_delay_mod[11]_i_2 \n (.I0(\\A[1]__4_n_0 ),\n .I1(\\A[0]__4_n_0 ),\n .I2(\\genblk9[6].fine_delay_incdec_pb_reg[6] ),\n .I3(\\A[1]__3_n_0 ),\n .I4(\\genblk9[5].fine_delay_incdec_pb_reg[5] ),\n .I5(\\fine_delay_mod_reg[26]_0 ),\n .O(\\fine_delay_mod[11]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000770400000000)) \n \\fine_delay_mod[11]_i_3 \n (.I0(\\A[1]__3_n_0 ),\n .I1(\\fine_delay_mod_reg[26]_0 ),\n .I2(\\A[1]__4_n_0 ),\n .I3(\\fine_delay_mod[11]_i_7_n_0 ),\n .I4(\\A[2]__1_n_0 ),\n .I5(\\fine_delay_mod[23]_i_6_n_0 ),\n .O(\\fine_delay_mod[11]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0700000000000000)) \n \\fine_delay_mod[11]_i_4 \n (.I0(\\A[1]__3_n_0 ),\n .I1(\\fine_delay_mod_reg[26]_0 ),\n .I2(\\A[1]__4_n_0 ),\n .I3(\\A[0]__4_n_0 ),\n .I4(byte_sel_data_map),\n .I5(\\genblk9[4].fine_delay_incdec_pb_reg[4] ),\n .O(\\fine_delay_mod[11]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h8000800088008000)) \n \\fine_delay_mod[11]_i_5 \n (.I0(\\fine_delay_mod[11]_i_9_n_0 ),\n .I1(\\fine_delay_mod[11]_i_10_n_0 ),\n .I2(\\A[2]__1_n_0 ),\n .I3(\\A[0]__0_n_0 ),\n .I4(\\fine_delay_mod[23]_i_8_n_0 ),\n .I5(\\A[1]__0_n_0 ),\n .O(\\fine_delay_mod[11]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFF888)) \n \\fine_delay_mod[11]_i_6 \n (.I0(\\A[1]__4_n_0 ),\n .I1(\\A[0]__4_n_0 ),\n .I2(\\fine_delay_mod_reg[26]_0 ),\n .I3(\\A[1]__3_n_0 ),\n .I4(\\fine_delay_mod[11]_i_11_n_0 ),\n .I5(\\fine_delay_mod[11]_i_12_n_0 ),\n .O(fine_delay_mod0[11]));\n (* SOFT_HLUTNM = \"soft_lutpair1038\" *) \n LUT3 #(\n .INIT(8'h1F)) \n \\fine_delay_mod[11]_i_7 \n (.I0(byte_sel_data_map),\n .I1(\\A[1]__4_n_0 ),\n .I2(\\A[0]__4_n_0 ),\n .O(\\fine_delay_mod[11]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1032\" *) \n LUT4 #(\n .INIT(16'h0008)) \n \\fine_delay_mod[11]_i_9 \n (.I0(byte_sel_data_map),\n .I1(\\genblk9[0].fine_delay_incdec_pb_reg[0] ),\n .I2(\\fine_delay_mod_reg[26]_0 ),\n .I3(\\A[0]__0_n_0 ),\n .O(\\fine_delay_mod[11]_i_9_n_0 ));\n LUT5 #(\n .INIT(32'hEEEFEEE0)) \n \\fine_delay_mod[14]_i_1 \n (.I0(\\fine_delay_mod[14]_i_2_n_0 ),\n .I1(\\fine_delay_mod[14]_i_3_n_0 ),\n .I2(\\fine_delay_mod[14]_i_4_n_0 ),\n .I3(\\fine_delay_mod[14]_i_5_n_0 ),\n .I4(fine_delay_mod[4]),\n .O(\\fine_delay_mod[14]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hC480FFFFC4800000)) \n \\fine_delay_mod[14]_i_2 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(\\A[2]__1_n_0 ),\n .I2(\\fine_delay_mod[14]_i_6_n_0 ),\n .I3(\\genblk9[3].fine_delay_incdec_pb_reg[3] ),\n .I4(\\fine_delay_mod[14]_i_7_n_0 ),\n .I5(\\genblk9[4].fine_delay_incdec_pb_reg[4]_0 ),\n .O(\\fine_delay_mod[14]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00B0003000300030)) \n \\fine_delay_mod[14]_i_3 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(\\A[2]__1_n_0 ),\n .I2(\\fine_delay_mod[17]_i_8_n_0 ),\n .I3(\\A[0]__0_n_0 ),\n .I4(\\A[1]__0_n_0 ),\n .I5(\\fine_delay_mod[14]_i_8_n_0 ),\n .O(\\fine_delay_mod[14]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1035\" *) \n LUT4 #(\n .INIT(16'h444C)) \n \\fine_delay_mod[14]_i_4 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(\\A[2]__1_n_0 ),\n .I2(\\A[0]__0_n_0 ),\n .I3(\\A[1]__0_n_0 ),\n .O(\\fine_delay_mod[14]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h000000FF02020202)) \n \\fine_delay_mod[14]_i_5 \n (.I0(\\A[0]__0_n_0 ),\n .I1(byte_sel_data_map),\n .I2(\\A[0]__0_n_0 ),\n .I3(\\A[0]__4_n_0 ),\n .I4(byte_sel_data_map),\n .I5(\\fine_delay_mod_reg[26]_0 ),\n .O(\\fine_delay_mod[14]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h020202FF02020200)) \n \\fine_delay_mod[14]_i_6 \n (.I0(\\genblk9[1].fine_delay_incdec_pb_reg[1] ),\n .I1(\\A_n_0_[1] ),\n .I2(\\fine_delay_mod_reg[26]_0 ),\n .I3(\\A[1]__0_n_0 ),\n .I4(\\A[0]__0_n_0 ),\n .I5(\\genblk9[2].fine_delay_incdec_pb_reg[2] ),\n .O(\\fine_delay_mod[14]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1040\" *) \n LUT3 #(\n .INIT(8'hFD)) \n \\fine_delay_mod[14]_i_7 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(byte_sel_data_map),\n .I2(\\A[0]__4_n_0 ),\n .O(\\fine_delay_mod[14]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\fine_delay_mod[14]_i_8 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(\\A_n_0_[1] ),\n .O(\\fine_delay_mod[14]_i_8_n_0 ));\n LUT5 #(\n .INIT(32'hEEEFEEE0)) \n \\fine_delay_mod[17]_i_1 \n (.I0(\\fine_delay_mod[17]_i_2_n_0 ),\n .I1(\\fine_delay_mod[17]_i_3_n_0 ),\n .I2(\\fine_delay_mod[17]_i_4_n_0 ),\n .I3(\\fine_delay_mod[17]_i_5_n_0 ),\n .I4(fine_delay_mod[5]),\n .O(\\fine_delay_mod[17]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hC840FFFFC8400000)) \n \\fine_delay_mod[17]_i_2 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(\\A[2]__1_n_0 ),\n .I2(\\fine_delay_mod[17]_i_6_n_0 ),\n .I3(\\genblk9[3].fine_delay_incdec_pb_reg[3] ),\n .I4(\\fine_delay_mod[17]_i_7_n_0 ),\n .I5(\\genblk9[4].fine_delay_incdec_pb_reg[4]_0 ),\n .O(\\fine_delay_mod[17]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h7030000030300000)) \n \\fine_delay_mod[17]_i_3 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(\\A[2]__1_n_0 ),\n .I2(\\fine_delay_mod[17]_i_8_n_0 ),\n .I3(\\A[1]__0_n_0 ),\n .I4(\\A[0]__0_n_0 ),\n .I5(\\fine_delay_mod[17]_i_9_n_0 ),\n .O(\\fine_delay_mod[17]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1035\" *) \n LUT4 #(\n .INIT(16'h88C8)) \n \\fine_delay_mod[17]_i_4 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(\\A[2]__1_n_0 ),\n .I2(\\A[0]__0_n_0 ),\n .I3(\\A[1]__0_n_0 ),\n .O(\\fine_delay_mod[17]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h0000FF0020202020)) \n \\fine_delay_mod[17]_i_5 \n (.I0(\\A[0]__0_n_0 ),\n .I1(byte_sel_data_map),\n .I2(\\A[0]__0_n_0 ),\n .I3(\\A[0]__4_n_0 ),\n .I4(byte_sel_data_map),\n .I5(\\fine_delay_mod_reg[26]_0 ),\n .O(\\fine_delay_mod[17]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h08FF080808000808)) \n \\fine_delay_mod[17]_i_6 \n (.I0(\\genblk9[1].fine_delay_incdec_pb_reg[1] ),\n .I1(\\fine_delay_mod_reg[26]_0 ),\n .I2(\\A_n_0_[1] ),\n .I3(\\A[1]__0_n_0 ),\n .I4(\\A[0]__0_n_0 ),\n .I5(\\genblk9[2].fine_delay_incdec_pb_reg[2] ),\n .O(\\fine_delay_mod[17]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1041\" *) \n LUT3 #(\n .INIT(8'hDF)) \n \\fine_delay_mod[17]_i_7 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(byte_sel_data_map),\n .I2(\\A[0]__4_n_0 ),\n .O(\\fine_delay_mod[17]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1029\" *) \n LUT4 #(\n .INIT(16'h0400)) \n \\fine_delay_mod[17]_i_8 \n (.I0(byte_sel_data_map),\n .I1(\\A[0]__0_n_0 ),\n .I2(\\fine_delay_mod_reg[26]_0 ),\n .I3(\\genblk9[0].fine_delay_incdec_pb_reg[0] ),\n .O(\\fine_delay_mod[17]_i_8_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1043\" *) \n LUT2 #(\n .INIT(4'hB)) \n \\fine_delay_mod[17]_i_9 \n (.I0(\\A_n_0_[1] ),\n .I1(\\fine_delay_mod_reg[26]_0 ),\n .O(\\fine_delay_mod[17]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hFCFFFEFEFC00FEFE)) \n \\fine_delay_mod[20]_i_1 \n (.I0(\\genblk9[4].fine_delay_incdec_pb_reg[4]_0 ),\n .I1(\\fine_delay_mod[20]_i_2_n_0 ),\n .I2(\\fine_delay_mod[20]_i_3_n_0 ),\n .I3(\\fine_delay_mod[20]_i_4_n_0 ),\n .I4(\\fine_delay_mod[20]_i_5_n_0 ),\n .I5(fine_delay_mod[6]),\n .O(\\fine_delay_mod[20]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1039\" *) \n LUT3 #(\n .INIT(8'h80)) \n \\fine_delay_mod[20]_i_2 \n (.I0(\\fine_delay_mod[20]_i_6_n_0 ),\n .I1(\\A[2]__1_n_0 ),\n .I2(\\fine_delay_mod[20]_i_5_n_0 ),\n .O(\\fine_delay_mod[20]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h004400C4)) \n \\fine_delay_mod[20]_i_3 \n (.I0(\\A[2]__1_n_0 ),\n .I1(\\fine_delay_mod[23]_i_7_n_0 ),\n .I2(\\fine_delay_mod[20]_i_7_n_0 ),\n .I3(\\A[0]__0_n_0 ),\n .I4(\\A[1]__0_n_0 ),\n .O(\\fine_delay_mod[20]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hFF808080)) \n \\fine_delay_mod[20]_i_4 \n (.I0(\\A[0]__0_n_0 ),\n .I1(byte_sel_data_map),\n .I2(\\fine_delay_mod[20]_i_8_n_0 ),\n .I3(\\A[2]__1_n_0 ),\n .I4(\\fine_delay_mod[20]_i_9_n_0 ),\n .O(\\fine_delay_mod[20]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1040\" *) \n LUT3 #(\n .INIT(8'hF7)) \n \\fine_delay_mod[20]_i_5 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(byte_sel_data_map),\n .I2(\\A[0]__4_n_0 ),\n .O(\\fine_delay_mod[20]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h08FF080808000808)) \n \\fine_delay_mod[20]_i_6 \n (.I0(\\genblk9[1].fine_delay_incdec_pb_reg[1] ),\n .I1(\\A_n_0_[1] ),\n .I2(\\fine_delay_mod_reg[26]_0 ),\n .I3(\\A[0]__0_n_0 ),\n .I4(\\A[1]__0_n_0 ),\n .I5(\\genblk9[2].fine_delay_incdec_pb_reg[2] ),\n .O(\\fine_delay_mod[20]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1043\" *) \n LUT2 #(\n .INIT(4'hB)) \n \\fine_delay_mod[20]_i_7 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(\\A_n_0_[1] ),\n .O(\\fine_delay_mod[20]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1042\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\fine_delay_mod[20]_i_8 \n (.I0(\\A[0]__0_n_0 ),\n .I1(\\fine_delay_mod_reg[26]_0 ),\n .O(\\fine_delay_mod[20]_i_8_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1033\" *) \n LUT4 #(\n .INIT(16'h22F2)) \n \\fine_delay_mod[20]_i_9 \n (.I0(\\A_n_0_[1] ),\n .I1(\\fine_delay_mod_reg[26]_0 ),\n .I2(\\A[1]__0_n_0 ),\n .I3(\\A[0]__0_n_0 ),\n .O(\\fine_delay_mod[20]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hFCFFFEFEFC00FEFE)) \n \\fine_delay_mod[23]_i_1 \n (.I0(\\genblk9[4].fine_delay_incdec_pb_reg[4]_0 ),\n .I1(\\fine_delay_mod[23]_i_2_n_0 ),\n .I2(\\fine_delay_mod[23]_i_3_n_0 ),\n .I3(\\fine_delay_mod[23]_i_4_n_0 ),\n .I4(\\fine_delay_mod[23]_i_5_n_0 ),\n .I5(fine_delay_mod[7]),\n .O(\\fine_delay_mod[23]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1030\" *) \n LUT4 #(\n .INIT(16'hF888)) \n \\fine_delay_mod[23]_i_10 \n (.I0(\\A_n_0_[1] ),\n .I1(\\fine_delay_mod_reg[26]_0 ),\n .I2(\\A[0]__0_n_0 ),\n .I3(\\A[1]__0_n_0 ),\n .O(\\fine_delay_mod[23]_i_10_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1039\" *) \n LUT3 #(\n .INIT(8'h80)) \n \\fine_delay_mod[23]_i_2 \n (.I0(\\fine_delay_mod[23]_i_6_n_0 ),\n .I1(\\A[2]__1_n_0 ),\n .I2(\\fine_delay_mod[23]_i_5_n_0 ),\n .O(\\fine_delay_mod[23]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h4400C400)) \n \\fine_delay_mod[23]_i_3 \n (.I0(\\A[2]__1_n_0 ),\n .I1(\\fine_delay_mod[23]_i_7_n_0 ),\n .I2(\\fine_delay_mod[23]_i_8_n_0 ),\n .I3(\\A[0]__0_n_0 ),\n .I4(\\A[1]__0_n_0 ),\n .O(\\fine_delay_mod[23]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1028\" *) \n LUT5 #(\n .INIT(32'hFF808080)) \n \\fine_delay_mod[23]_i_4 \n (.I0(\\A[0]__0_n_0 ),\n .I1(byte_sel_data_map),\n .I2(\\fine_delay_mod[23]_i_9_n_0 ),\n .I3(\\A[2]__1_n_0 ),\n .I4(\\fine_delay_mod[23]_i_10_n_0 ),\n .O(\\fine_delay_mod[23]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1041\" *) \n LUT3 #(\n .INIT(8'h7F)) \n \\fine_delay_mod[23]_i_5 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(byte_sel_data_map),\n .I2(\\A[0]__4_n_0 ),\n .O(\\fine_delay_mod[23]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFF80808000808080)) \n \\fine_delay_mod[23]_i_6 \n (.I0(\\genblk9[1].fine_delay_incdec_pb_reg[1] ),\n .I1(\\A_n_0_[1] ),\n .I2(\\fine_delay_mod_reg[26]_0 ),\n .I3(\\A[1]__0_n_0 ),\n .I4(\\A[0]__0_n_0 ),\n .I5(\\genblk9[2].fine_delay_incdec_pb_reg[2] ),\n .O(\\fine_delay_mod[23]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1032\" *) \n LUT4 #(\n .INIT(16'h0800)) \n \\fine_delay_mod[23]_i_7 \n (.I0(byte_sel_data_map),\n .I1(\\genblk9[0].fine_delay_incdec_pb_reg[0] ),\n .I2(\\fine_delay_mod_reg[26]_0 ),\n .I3(\\A[0]__0_n_0 ),\n .O(\\fine_delay_mod[23]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1034\" *) \n LUT2 #(\n .INIT(4'h7)) \n \\fine_delay_mod[23]_i_8 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(\\A_n_0_[1] ),\n .O(\\fine_delay_mod[23]_i_8_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1042\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\fine_delay_mod[23]_i_9 \n (.I0(\\A[0]__0_n_0 ),\n .I1(\\fine_delay_mod_reg[26]_0 ),\n .O(\\fine_delay_mod[23]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFEF00000020)) \n \\fine_delay_mod[26]_i_1 \n (.I0(\\genblk9[0].fine_delay_incdec_pb_reg[0] ),\n .I1(\\A[0]__0_n_0 ),\n .I2(\\fine_delay_mod_reg[26]_0 ),\n .I3(\\A[0]__0_n_0 ),\n .I4(byte_sel_data_map),\n .I5(fine_delay_mod[8]),\n .O(\\fine_delay_mod[26]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFEFFFFFFFE0000)) \n \\fine_delay_mod[2]_i_1 \n (.I0(\\fine_delay_mod[2]_i_2_n_0 ),\n .I1(\\fine_delay_mod[2]_i_3_n_0 ),\n .I2(\\fine_delay_mod[2]_i_4_n_0 ),\n .I3(\\fine_delay_mod[2]_i_5_n_0 ),\n .I4(fine_delay_mod0[2]),\n .I5(fine_delay_mod[0]),\n .O(\\fine_delay_mod[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1030\" *) \n LUT4 #(\n .INIT(16'h111F)) \n \\fine_delay_mod[2]_i_10 \n (.I0(\\A_n_0_[1] ),\n .I1(\\fine_delay_mod_reg[26]_0 ),\n .I2(\\A[0]__0_n_0 ),\n .I3(\\A[1]__0_n_0 ),\n .O(\\fine_delay_mod[2]_i_10_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1036\" *) \n LUT4 #(\n .INIT(16'h1000)) \n \\fine_delay_mod[2]_i_2 \n (.I0(\\A[1]__4_n_0 ),\n .I1(\\A[0]__4_n_0 ),\n .I2(\\genblk9[6].fine_delay_incdec_pb_reg[6] ),\n .I3(\\fine_delay_mod_reg[26]_0 ),\n .O(\\fine_delay_mod[2]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h00A80000)) \n \\fine_delay_mod[2]_i_3 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(\\A[1]__4_n_0 ),\n .I2(\\fine_delay_mod[2]_i_7_n_0 ),\n .I3(\\A[2]__1_n_0 ),\n .I4(\\fine_delay_mod[14]_i_6_n_0 ),\n .O(\\fine_delay_mod[2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h5500752055005500)) \n \\fine_delay_mod[2]_i_4 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(\\A[0]__4_n_0 ),\n .I2(\\A[1]__4_n_0 ),\n .I3(\\genblk9[7].fine_delay_incdec_pb_reg[7] ),\n .I4(byte_sel_data_map),\n .I5(\\genblk9[4].fine_delay_incdec_pb_reg[4] ),\n .O(\\fine_delay_mod[2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hAA80000000000000)) \n \\fine_delay_mod[2]_i_5 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(byte_sel_data_map),\n .I2(\\A[1]__4_n_0 ),\n .I3(\\A[0]__4_n_0 ),\n .I4(\\fine_delay_mod[5]_i_8_n_0 ),\n .I5(\\fine_delay_mod[2]_i_8_n_0 ),\n .O(\\fine_delay_mod[2]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFDDDFDDDFFFFFDDD)) \n \\fine_delay_mod[2]_i_6 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(\\fine_delay_mod[2]_i_9_n_0 ),\n .I2(\\fine_delay_mod[5]_i_11_n_0 ),\n .I3(\\fine_delay_mod[20]_i_8_n_0 ),\n .I4(\\fine_delay_mod[2]_i_10_n_0 ),\n .I5(\\A[2]__1_n_0 ),\n .O(fine_delay_mod0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1037\" *) \n LUT3 #(\n .INIT(8'hF8)) \n \\fine_delay_mod[2]_i_7 \n (.I0(byte_sel_data_map),\n .I1(\\A[1]__4_n_0 ),\n .I2(\\A[0]__4_n_0 ),\n .O(\\fine_delay_mod[2]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1025\" *) \n LUT5 #(\n .INIT(32'h00FF00A8)) \n \\fine_delay_mod[2]_i_8 \n (.I0(\\A[1]__0_n_0 ),\n .I1(\\fine_delay_mod_reg[26]_0 ),\n .I2(\\A_n_0_[1] ),\n .I3(\\A[0]__0_n_0 ),\n .I4(\\A[2]__1_n_0 ),\n .O(\\fine_delay_mod[2]_i_8_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1031\" *) \n LUT4 #(\n .INIT(16'h010F)) \n \\fine_delay_mod[2]_i_9 \n (.I0(byte_sel_data_map),\n .I1(\\fine_delay_mod_reg[26]_0 ),\n .I2(\\A[0]__4_n_0 ),\n .I3(\\A[1]__4_n_0 ),\n .O(\\fine_delay_mod[2]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hFFFEFFFFFFFE0000)) \n \\fine_delay_mod[5]_i_1 \n (.I0(\\fine_delay_mod[5]_i_2_n_0 ),\n .I1(\\fine_delay_mod[5]_i_3_n_0 ),\n .I2(\\fine_delay_mod[5]_i_4_n_0 ),\n .I3(\\fine_delay_mod[5]_i_5_n_0 ),\n .I4(fine_delay_mod0[5]),\n .I5(fine_delay_mod[1]),\n .O(\\fine_delay_mod[5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1031\" *) \n LUT4 #(\n .INIT(16'h10F0)) \n \\fine_delay_mod[5]_i_10 \n (.I0(byte_sel_data_map),\n .I1(\\fine_delay_mod_reg[26]_0 ),\n .I2(\\A[0]__4_n_0 ),\n .I3(\\A[1]__4_n_0 ),\n .O(\\fine_delay_mod[5]_i_10_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1028\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\fine_delay_mod[5]_i_11 \n (.I0(byte_sel_data_map),\n .I1(\\A[0]__0_n_0 ),\n .O(\\fine_delay_mod[5]_i_11_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1033\" *) \n LUT4 #(\n .INIT(16'h22F2)) \n \\fine_delay_mod[5]_i_12 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(\\A_n_0_[1] ),\n .I2(\\A[0]__0_n_0 ),\n .I3(\\A[1]__0_n_0 ),\n .O(\\fine_delay_mod[5]_i_12_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1036\" *) \n LUT4 #(\n .INIT(16'h0040)) \n \\fine_delay_mod[5]_i_2 \n (.I0(\\A[1]__4_n_0 ),\n .I1(\\A[0]__4_n_0 ),\n .I2(\\genblk9[6].fine_delay_incdec_pb_reg[6] ),\n .I3(\\fine_delay_mod_reg[26]_0 ),\n .O(\\fine_delay_mod[5]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1034\" *) \n LUT4 #(\n .INIT(16'h0400)) \n \\fine_delay_mod[5]_i_3 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(\\fine_delay_mod[5]_i_7_n_0 ),\n .I2(\\A[2]__1_n_0 ),\n .I3(\\fine_delay_mod[17]_i_6_n_0 ),\n .O(\\fine_delay_mod[5]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hAA00EA40AA00AA00)) \n \\fine_delay_mod[5]_i_4 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(\\A[1]__4_n_0 ),\n .I2(\\A[0]__4_n_0 ),\n .I3(\\genblk9[7].fine_delay_incdec_pb_reg[7] ),\n .I4(byte_sel_data_map),\n .I5(\\genblk9[4].fine_delay_incdec_pb_reg[4] ),\n .O(\\fine_delay_mod[5]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h4055000000000000)) \n \\fine_delay_mod[5]_i_5 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(byte_sel_data_map),\n .I2(\\A[1]__4_n_0 ),\n .I3(\\A[0]__4_n_0 ),\n .I4(\\fine_delay_mod[5]_i_8_n_0 ),\n .I5(\\fine_delay_mod[5]_i_9_n_0 ),\n .O(\\fine_delay_mod[5]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFEEEFEEEFFFFFEEE)) \n \\fine_delay_mod[5]_i_6 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(\\fine_delay_mod[5]_i_10_n_0 ),\n .I2(\\fine_delay_mod[5]_i_11_n_0 ),\n .I3(\\fine_delay_mod[23]_i_9_n_0 ),\n .I4(\\fine_delay_mod[5]_i_12_n_0 ),\n .I5(\\A[2]__1_n_0 ),\n .O(fine_delay_mod0[5]));\n (* SOFT_HLUTNM = \"soft_lutpair1038\" *) \n LUT3 #(\n .INIT(8'h8F)) \n \\fine_delay_mod[5]_i_7 \n (.I0(byte_sel_data_map),\n .I1(\\A[1]__4_n_0 ),\n .I2(\\A[0]__4_n_0 ),\n .O(\\fine_delay_mod[5]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1029\" *) \n LUT4 #(\n .INIT(16'h0004)) \n \\fine_delay_mod[5]_i_8 \n (.I0(\\fine_delay_mod_reg[26]_0 ),\n .I1(\\genblk9[0].fine_delay_incdec_pb_reg[0] ),\n .I2(\\A[0]__0_n_0 ),\n .I3(byte_sel_data_map),\n .O(\\fine_delay_mod[5]_i_8_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1025\" *) \n LUT5 #(\n .INIT(32'hFF008A00)) \n \\fine_delay_mod[5]_i_9 \n (.I0(\\A[1]__0_n_0 ),\n .I1(\\A_n_0_[1] ),\n .I2(\\fine_delay_mod_reg[26]_0 ),\n .I3(\\A[0]__0_n_0 ),\n .I4(\\A[2]__1_n_0 ),\n .O(\\fine_delay_mod[5]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hFFFEFFFFFFFE0000)) \n \\fine_delay_mod[8]_i_1 \n (.I0(\\fine_delay_mod[8]_i_2_n_0 ),\n .I1(\\fine_delay_mod[8]_i_3_n_0 ),\n .I2(\\fine_delay_mod[8]_i_4_n_0 ),\n .I3(\\fine_delay_mod[8]_i_5_n_0 ),\n .I4(fine_delay_mod0[8]),\n .I5(fine_delay_mod[2]),\n .O(\\fine_delay_mod[8]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00440044004F0044)) \n \\fine_delay_mod[8]_i_10 \n (.I0(\\A[0]__4_n_0 ),\n .I1(byte_sel_data_map),\n .I2(\\A[0]__0_n_0 ),\n .I3(\\fine_delay_mod_reg[26]_0 ),\n .I4(byte_sel_data_map),\n .I5(\\A[0]__0_n_0 ),\n .O(\\fine_delay_mod[8]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'h40404040FB404040)) \n \\fine_delay_mod[8]_i_2 \n (.I0(\\A[0]__4_n_0 ),\n .I1(\\A[1]__4_n_0 ),\n .I2(\\genblk9[6].fine_delay_incdec_pb_reg[6] ),\n .I3(\\A[1]__3_n_0 ),\n .I4(\\genblk9[5].fine_delay_incdec_pb_reg[5] ),\n .I5(\\fine_delay_mod_reg[26]_0 ),\n .O(\\fine_delay_mod[8]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000DD0C00000000)) \n \\fine_delay_mod[8]_i_3 \n (.I0(\\A[1]__3_n_0 ),\n .I1(\\fine_delay_mod_reg[26]_0 ),\n .I2(\\A[1]__4_n_0 ),\n .I3(\\fine_delay_mod[8]_i_7_n_0 ),\n .I4(\\A[2]__1_n_0 ),\n .I5(\\fine_delay_mod[20]_i_6_n_0 ),\n .O(\\fine_delay_mod[8]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h000D000000000000)) \n \\fine_delay_mod[8]_i_4 \n (.I0(\\A[1]__3_n_0 ),\n .I1(\\fine_delay_mod_reg[26]_0 ),\n .I2(\\A[1]__4_n_0 ),\n .I3(\\A[0]__4_n_0 ),\n .I4(byte_sel_data_map),\n .I5(\\genblk9[4].fine_delay_incdec_pb_reg[4] ),\n .O(\\fine_delay_mod[8]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h0080008000880080)) \n \\fine_delay_mod[8]_i_5 \n (.I0(\\fine_delay_mod[11]_i_9_n_0 ),\n .I1(\\fine_delay_mod[8]_i_8_n_0 ),\n .I2(\\A[2]__1_n_0 ),\n .I3(\\A[0]__0_n_0 ),\n .I4(\\fine_delay_mod[20]_i_7_n_0 ),\n .I5(\\A[1]__0_n_0 ),\n .O(\\fine_delay_mod[8]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF4F44)) \n \\fine_delay_mod[8]_i_6 \n (.I0(\\A[0]__4_n_0 ),\n .I1(\\A[1]__4_n_0 ),\n .I2(\\fine_delay_mod_reg[26]_0 ),\n .I3(\\A[1]__3_n_0 ),\n .I4(\\fine_delay_mod[8]_i_9_n_0 ),\n .I5(\\fine_delay_mod[8]_i_10_n_0 ),\n .O(fine_delay_mod0[8]));\n (* SOFT_HLUTNM = \"soft_lutpair1037\" *) \n LUT3 #(\n .INIT(8'hF1)) \n \\fine_delay_mod[8]_i_7 \n (.I0(byte_sel_data_map),\n .I1(\\A[1]__4_n_0 ),\n .I2(\\A[0]__4_n_0 ),\n .O(\\fine_delay_mod[8]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1027\" *) \n LUT5 #(\n .INIT(32'hAB00ABAB)) \n \\fine_delay_mod[8]_i_8 \n (.I0(\\A[0]__4_n_0 ),\n .I1(\\A[1]__4_n_0 ),\n .I2(byte_sel_data_map),\n .I3(\\fine_delay_mod_reg[26]_0 ),\n .I4(\\A[1]__3_n_0 ),\n .O(\\fine_delay_mod[8]_i_8_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1026\" *) \n LUT5 #(\n .INIT(32'h00004F44)) \n \\fine_delay_mod[8]_i_9 \n (.I0(\\A[0]__0_n_0 ),\n .I1(\\A[1]__0_n_0 ),\n .I2(\\fine_delay_mod_reg[26]_0 ),\n .I3(\\A_n_0_[1] ),\n .I4(\\A[2]__1_n_0 ),\n .O(\\fine_delay_mod[8]_i_9_n_0 ));\n FDRE \\fine_delay_mod_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(\\fine_delay_mod[11]_i_1_n_0 ),\n .Q(fine_delay_mod[3]),\n .R(1'b0));\n FDRE \\fine_delay_mod_reg[14] \n (.C(CLK),\n .CE(1'b1),\n .D(\\fine_delay_mod[14]_i_1_n_0 ),\n .Q(fine_delay_mod[4]),\n .R(1'b0));\n FDRE \\fine_delay_mod_reg[17] \n (.C(CLK),\n .CE(1'b1),\n .D(\\fine_delay_mod[17]_i_1_n_0 ),\n .Q(fine_delay_mod[5]),\n .R(1'b0));\n FDRE \\fine_delay_mod_reg[20] \n (.C(CLK),\n .CE(1'b1),\n .D(\\fine_delay_mod[20]_i_1_n_0 ),\n .Q(fine_delay_mod[6]),\n .R(1'b0));\n FDRE \\fine_delay_mod_reg[23] \n (.C(CLK),\n .CE(1'b1),\n .D(\\fine_delay_mod[23]_i_1_n_0 ),\n .Q(fine_delay_mod[7]),\n .R(1'b0));\n FDRE \\fine_delay_mod_reg[26] \n (.C(CLK),\n .CE(1'b1),\n .D(\\fine_delay_mod[26]_i_1_n_0 ),\n .Q(fine_delay_mod[8]),\n .R(1'b0));\n FDRE \\fine_delay_mod_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\fine_delay_mod[2]_i_1_n_0 ),\n .Q(fine_delay_mod[0]),\n .R(1'b0));\n FDRE \\fine_delay_mod_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\fine_delay_mod[5]_i_1_n_0 ),\n .Q(fine_delay_mod[1]),\n .R(1'b0));\n FDRE \\fine_delay_mod_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(\\fine_delay_mod[8]_i_1_n_0 ),\n .Q(fine_delay_mod[2]),\n .R(1'b0));\n FDRE fine_delay_sel_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(fine_delay_sel_reg),\n .Q(fine_delay_sel_r),\n .R(1'b0));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CAPACITANCE = \"DONT_CARE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_addr_obuf[0].u_addr_obuf \n (.I(mem_dq_out[83]),\n .O(ddr3_addr[0]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CAPACITANCE = \"DONT_CARE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_addr_obuf[10].u_addr_obuf \n (.I(mem_dq_out[90]),\n .O(ddr3_addr[10]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CAPACITANCE = \"DONT_CARE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_addr_obuf[11].u_addr_obuf \n (.I(mem_dq_out[91]),\n .O(ddr3_addr[11]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CAPACITANCE = \"DONT_CARE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_addr_obuf[12].u_addr_obuf \n (.I(mem_dq_out[92]),\n .O(ddr3_addr[12]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CAPACITANCE = \"DONT_CARE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_addr_obuf[13].u_addr_obuf \n (.I(mem_dq_out[93]),\n .O(ddr3_addr[13]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CAPACITANCE = \"DONT_CARE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_addr_obuf[14].u_addr_obuf \n (.I(mem_dq_out[64]),\n .O(ddr3_addr[14]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CAPACITANCE = \"DONT_CARE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_addr_obuf[1].u_addr_obuf \n (.I(mem_dq_out[78]),\n .O(ddr3_addr[1]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CAPACITANCE = \"DONT_CARE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_addr_obuf[2].u_addr_obuf \n (.I(mem_dq_out[79]),\n .O(ddr3_addr[2]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CAPACITANCE = \"DONT_CARE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_addr_obuf[3].u_addr_obuf \n (.I(mem_dq_out[80]),\n .O(ddr3_addr[3]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CAPACITANCE = \"DONT_CARE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_addr_obuf[4].u_addr_obuf \n (.I(mem_dq_out[77]),\n .O(ddr3_addr[4]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CAPACITANCE = \"DONT_CARE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_addr_obuf[5].u_addr_obuf \n (.I(mem_dq_out[85]),\n .O(ddr3_addr[5]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CAPACITANCE = \"DONT_CARE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_addr_obuf[6].u_addr_obuf \n (.I(mem_dq_out[86]),\n .O(ddr3_addr[6]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CAPACITANCE = \"DONT_CARE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_addr_obuf[7].u_addr_obuf \n (.I(mem_dq_out[87]),\n .O(ddr3_addr[7]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CAPACITANCE = \"DONT_CARE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_addr_obuf[8].u_addr_obuf \n (.I(mem_dq_out[88]),\n .O(ddr3_addr[8]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CAPACITANCE = \"DONT_CARE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_addr_obuf[9].u_addr_obuf \n (.I(mem_dq_out[89]),\n .O(ddr3_addr[9]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CAPACITANCE = \"DONT_CARE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_bank_obuf[0].u_bank_obuf \n (.I(mem_dq_out[76]),\n .O(ddr3_ba[0]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CAPACITANCE = \"DONT_CARE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_bank_obuf[1].u_bank_obuf \n (.I(mem_dq_out[81]),\n .O(ddr3_ba[1]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CAPACITANCE = \"DONT_CARE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_bank_obuf[2].u_bank_obuf \n (.I(mem_dq_out[82]),\n .O(ddr3_ba[2]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CAPACITANCE = \"DONT_CARE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_cs_n_obuf.gen_cs_obuf[0].u_cs_n_obuf \n (.I(mem_dq_out[48]),\n .O(ddr3_cs_n));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CAPACITANCE = \"DONT_CARE\" *) \n OBUFT #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_dm_obuf.loop_dm[0].u_dm_obuf \n (.I(mem_dq_out[45]),\n .O(ddr3_dm[0]),\n .T(mem_dq_ts[45]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CAPACITANCE = \"DONT_CARE\" *) \n OBUFT #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_dm_obuf.loop_dm[1].u_dm_obuf \n (.I(mem_dq_out[33]),\n .O(ddr3_dm[1]),\n .T(mem_dq_ts[33]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CAPACITANCE = \"DONT_CARE\" *) \n OBUFT #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_dm_obuf.loop_dm[2].u_dm_obuf \n (.I(mem_dq_out[21]),\n .O(ddr3_dm[2]),\n .T(mem_dq_ts[21]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CAPACITANCE = \"DONT_CARE\" *) \n OBUFT #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_dm_obuf.loop_dm[3].u_dm_obuf \n (.I(mem_dq_out[9]),\n .O(ddr3_dm[3]),\n .T(mem_dq_ts[9]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[0].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[44]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[0]),\n .O(mem_dq_in[38]),\n .T(mem_dq_ts[44]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[10].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[30]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[10]),\n .O(mem_dq_in[26]),\n .T(mem_dq_ts[30]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[11].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[29]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[11]),\n .O(mem_dq_in[25]),\n .T(mem_dq_ts[29]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[12].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[28]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[12]),\n .O(mem_dq_in[24]),\n .T(mem_dq_ts[28]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[13].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[27]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[13]),\n .O(mem_dq_in[23]),\n .T(mem_dq_ts[27]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[14].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[26]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[14]),\n .O(mem_dq_in[22]),\n .T(mem_dq_ts[26]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[15].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[25]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[15]),\n .O(mem_dq_in[21]),\n .T(mem_dq_ts[25]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[16].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[20]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[16]),\n .O(mem_dq_in[18]),\n .T(mem_dq_ts[20]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[17].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[19]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[17]),\n .O(mem_dq_in[17]),\n .T(mem_dq_ts[19]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[18].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[18]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[18]),\n .O(mem_dq_in[16]),\n .T(mem_dq_ts[18]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[19].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[17]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[19]),\n .O(mem_dq_in[15]),\n .T(mem_dq_ts[17]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[1].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[43]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[1]),\n .O(mem_dq_in[37]),\n .T(mem_dq_ts[43]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[20].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[16]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[20]),\n .O(mem_dq_in[14]),\n .T(mem_dq_ts[16]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[21].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[15]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[21]),\n .O(mem_dq_in[13]),\n .T(mem_dq_ts[15]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[22].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[14]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[22]),\n .O(mem_dq_in[12]),\n .T(mem_dq_ts[14]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[23].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[13]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[23]),\n .O(mem_dq_in[11]),\n .T(mem_dq_ts[13]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[24].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[7]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[24]),\n .O(mem_dq_in[7]),\n .T(mem_dq_ts[7]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[25].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[6]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[25]),\n .O(mem_dq_in[6]),\n .T(mem_dq_ts[6]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[26].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[5]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[26]),\n .O(mem_dq_in[5]),\n .T(mem_dq_ts[5]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[27].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[4]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[27]),\n .O(mem_dq_in[4]),\n .T(mem_dq_ts[4]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[28].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[3]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[28]),\n .O(mem_dq_in[3]),\n .T(mem_dq_ts[3]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[29].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[2]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[29]),\n .O(mem_dq_in[2]),\n .T(mem_dq_ts[2]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[2].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[42]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[2]),\n .O(mem_dq_in[36]),\n .T(mem_dq_ts[42]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[30].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[1]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[30]),\n .O(mem_dq_in[1]),\n .T(mem_dq_ts[1]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[31].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[0]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[31]),\n .O(mem_dq_in[0]),\n .T(mem_dq_ts[0]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[3].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[41]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[3]),\n .O(mem_dq_in[35]),\n .T(mem_dq_ts[41]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[4].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[40]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[4]),\n .O(mem_dq_in[34]),\n .T(mem_dq_ts[40]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[5].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[39]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[5]),\n .O(mem_dq_in[33]),\n .T(mem_dq_ts[39]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[6].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[38]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[6]),\n .O(mem_dq_in[32]),\n .T(mem_dq_ts[38]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[7].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[37]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[7]),\n .O(mem_dq_in[31]),\n .T(mem_dq_ts[37]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[8].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[32]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[8]),\n .O(mem_dq_in[28]),\n .T(mem_dq_ts[32]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUF_DCIEN #(\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"TRUE\")) \n \\gen_dq_iobuf_HP.gen_dq_iobuf[9].u_iobuf_dq \n (.DCITERMDISABLE(idle),\n .I(mem_dq_out[31]),\n .IBUFDISABLE(idle),\n .IO(ddr3_dq[9]),\n .O(mem_dq_in[27]),\n .T(mem_dq_ts[31]));\n ddr3_if_mig_7series_v4_0_poc_pd \\gen_dqs_iobuf_HP.gen_dqs_iobuf[0].gen_dqs_diff.u_iddr_edge_det \n (.CLK(CLK),\n .in_dqs_lpbk_to_iddr_0(in_dqs_lpbk_to_iddr_0),\n .mmcm_ps_clk(mmcm_ps_clk),\n .pd_out_pre(pd_out_pre[0]),\n .rst_sync_r1(rst_sync_r1));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUFDS_DIFF_OUT_DCIEN #(\n .DQS_BIAS(\"TRUE\"),\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"FALSE\")) \n \\gen_dqs_iobuf_HP.gen_dqs_iobuf[0].gen_dqs_diff.u_iobuf_dqs \n (.DCITERMDISABLE(idle),\n .I(mem_dqs_out[3]),\n .IBUFDISABLE(1'b0),\n .IO(ddr3_dqs_p[0]),\n .IOB(ddr3_dqs_n[0]),\n .O(mem_dqs_in[3]),\n .OB(in_dqs_lpbk_to_iddr_0),\n .TM(mem_dqs_ts[3]),\n .TS(mem_dqs_ts[3]));\n ddr3_if_mig_7series_v4_0_poc_pd_3 \\gen_dqs_iobuf_HP.gen_dqs_iobuf[1].gen_dqs_diff.u_iddr_edge_det \n (.CLK(CLK),\n .in_dqs_lpbk_to_iddr_1(in_dqs_lpbk_to_iddr_1),\n .mmcm_ps_clk(mmcm_ps_clk),\n .pd_out_pre(pd_out_pre[1]),\n .rst_sync_r1(rst_sync_r1));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUFDS_DIFF_OUT_DCIEN #(\n .DQS_BIAS(\"TRUE\"),\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"FALSE\")) \n \\gen_dqs_iobuf_HP.gen_dqs_iobuf[1].gen_dqs_diff.u_iobuf_dqs \n (.DCITERMDISABLE(idle),\n .I(mem_dqs_out[2]),\n .IBUFDISABLE(1'b0),\n .IO(ddr3_dqs_p[1]),\n .IOB(ddr3_dqs_n[1]),\n .O(mem_dqs_in[2]),\n .OB(in_dqs_lpbk_to_iddr_1),\n .TM(mem_dqs_ts[2]),\n .TS(mem_dqs_ts[2]));\n ddr3_if_mig_7series_v4_0_poc_pd_4 \\gen_dqs_iobuf_HP.gen_dqs_iobuf[2].gen_dqs_diff.u_iddr_edge_det \n (.CLK(CLK),\n .in_dqs_lpbk_to_iddr_2(in_dqs_lpbk_to_iddr_2),\n .mmcm_ps_clk(mmcm_ps_clk),\n .pd_out_pre(pd_out_pre[2]),\n .rst_sync_r1(rst_sync_r1));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUFDS_DIFF_OUT_DCIEN #(\n .DQS_BIAS(\"TRUE\"),\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"FALSE\")) \n \\gen_dqs_iobuf_HP.gen_dqs_iobuf[2].gen_dqs_diff.u_iobuf_dqs \n (.DCITERMDISABLE(idle),\n .I(mem_dqs_out[1]),\n .IBUFDISABLE(1'b0),\n .IO(ddr3_dqs_p[2]),\n .IOB(ddr3_dqs_n[2]),\n .O(mem_dqs_in[1]),\n .OB(in_dqs_lpbk_to_iddr_2),\n .TM(mem_dqs_ts[1]),\n .TS(mem_dqs_ts[1]));\n ddr3_if_mig_7series_v4_0_poc_pd_5 \\gen_dqs_iobuf_HP.gen_dqs_iobuf[3].gen_dqs_diff.u_iddr_edge_det \n (.CLK(CLK),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[1] (\\gen_byte_sel_div1.byte_sel_cnt_reg[1] ),\n .in_dqs_lpbk_to_iddr_3(in_dqs_lpbk_to_iddr_3),\n .mmcm_ps_clk(mmcm_ps_clk),\n .pd_out(pd_out),\n .pd_out_r_reg_0(pd_out_pre),\n .rst_sync_r1(rst_sync_r1));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n IOBUFDS_DIFF_OUT_DCIEN #(\n .DQS_BIAS(\"TRUE\"),\n .IOSTANDARD(\"DEFAULT\"),\n .SIM_DEVICE(\"7SERIES\"),\n .USE_IBUFDISABLE(\"FALSE\")) \n \\gen_dqs_iobuf_HP.gen_dqs_iobuf[3].gen_dqs_diff.u_iobuf_dqs \n (.DCITERMDISABLE(idle),\n .I(mem_dqs_out[0]),\n .IBUFDISABLE(1'b0),\n .IO(ddr3_dqs_p[3]),\n .IOB(ddr3_dqs_n[3]),\n .O(mem_dqs_in[0]),\n .OB(in_dqs_lpbk_to_iddr_3),\n .TM(mem_dqs_ts[0]),\n .TS(mem_dqs_ts[0]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CAPACITANCE = \"DONT_CARE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n \\gen_reset_obuf.u_reset_obuf \n (.I(mux_reset_n),\n .O(ddr3_reset_n));\n ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo \\genblk24.phy_ctl_pre_fifo_0 \n (.CLK(CLK),\n .SR(SR),\n .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2));\n ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized0 \\genblk24.phy_ctl_pre_fifo_1 \n (.CLK(CLK),\n .SR(SR),\n .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2));\n ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized1 \\genblk24.phy_ctl_pre_fifo_2 \n (.CLK(CLK),\n .SR(SR),\n .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2));\n FDRE \\phy_ctl_wd_i1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(D[0]),\n .Q(phy_ctl_wd_i1[0]),\n .R(1'b0));\n FDRE \\phy_ctl_wd_i1_reg[17] \n (.C(CLK),\n .CE(1'b1),\n .D(D[3]),\n .Q(phy_ctl_wd_i1[17]),\n .R(1'b0));\n FDRE \\phy_ctl_wd_i1_reg[18] \n (.C(CLK),\n .CE(1'b1),\n .D(D[4]),\n .Q(phy_ctl_wd_i1[18]),\n .R(1'b0));\n FDRE \\phy_ctl_wd_i1_reg[19] \n (.C(CLK),\n .CE(1'b1),\n .D(D[5]),\n .Q(phy_ctl_wd_i1[19]),\n .R(1'b0));\n FDRE \\phy_ctl_wd_i1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(D[1]),\n .Q(phy_ctl_wd_i1[1]),\n .R(1'b0));\n FDRE \\phy_ctl_wd_i1_reg[20] \n (.C(CLK),\n .CE(1'b1),\n .D(D[6]),\n .Q(phy_ctl_wd_i1[20]),\n .R(1'b0));\n FDRE \\phy_ctl_wd_i1_reg[21] \n (.C(CLK),\n .CE(1'b1),\n .D(D[7]),\n .Q(phy_ctl_wd_i1[21]),\n .R(1'b0));\n FDRE \\phy_ctl_wd_i1_reg[22] \n (.C(CLK),\n .CE(1'b1),\n .D(D[8]),\n .Q(phy_ctl_wd_i1[22]),\n .R(1'b0));\n FDRE \\phy_ctl_wd_i1_reg[23] \n (.C(CLK),\n .CE(1'b1),\n .D(D[9]),\n .Q(phy_ctl_wd_i1[23]),\n .R(1'b0));\n FDRE \\phy_ctl_wd_i1_reg[24] \n (.C(CLK),\n .CE(1'b1),\n .D(D[10]),\n .Q(phy_ctl_wd_i1[24]),\n .R(1'b0));\n FDRE \\phy_ctl_wd_i1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(D[2]),\n .Q(phy_ctl_wd_i1[2]),\n .R(1'b0));\n FDRE \\phy_ctl_wd_i2_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(phy_ctl_wd_i1[0]),\n .Q(phy_ctl_wd_i2[0]),\n .R(1'b0));\n FDRE \\phy_ctl_wd_i2_reg[17] \n (.C(CLK),\n .CE(1'b1),\n .D(phy_ctl_wd_i1[17]),\n .Q(phy_ctl_wd_i2[17]),\n .R(1'b0));\n FDRE \\phy_ctl_wd_i2_reg[18] \n (.C(CLK),\n .CE(1'b1),\n .D(phy_ctl_wd_i1[18]),\n .Q(phy_ctl_wd_i2[18]),\n .R(1'b0));\n FDRE \\phy_ctl_wd_i2_reg[19] \n (.C(CLK),\n .CE(1'b1),\n .D(phy_ctl_wd_i1[19]),\n .Q(phy_ctl_wd_i2[19]),\n .R(1'b0));\n FDRE \\phy_ctl_wd_i2_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(phy_ctl_wd_i1[1]),\n .Q(phy_ctl_wd_i2[1]),\n .R(1'b0));\n FDRE \\phy_ctl_wd_i2_reg[20] \n (.C(CLK),\n .CE(1'b1),\n .D(phy_ctl_wd_i1[20]),\n .Q(phy_ctl_wd_i2[20]),\n .R(1'b0));\n FDRE \\phy_ctl_wd_i2_reg[21] \n (.C(CLK),\n .CE(1'b1),\n .D(phy_ctl_wd_i1[21]),\n .Q(phy_ctl_wd_i2[21]),\n .R(1'b0));\n FDRE \\phy_ctl_wd_i2_reg[22] \n (.C(CLK),\n .CE(1'b1),\n .D(phy_ctl_wd_i1[22]),\n .Q(phy_ctl_wd_i2[22]),\n .R(1'b0));\n FDRE \\phy_ctl_wd_i2_reg[23] \n (.C(CLK),\n .CE(1'b1),\n .D(phy_ctl_wd_i1[23]),\n .Q(phy_ctl_wd_i2[23]),\n .R(1'b0));\n FDRE \\phy_ctl_wd_i2_reg[24] \n (.C(CLK),\n .CE(1'b1),\n .D(phy_ctl_wd_i1[24]),\n .Q(phy_ctl_wd_i2[24]),\n .R(1'b0));\n FDRE \\phy_ctl_wd_i2_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(phy_ctl_wd_i1[2]),\n .Q(phy_ctl_wd_i2[2]),\n .R(1'b0));\n FDRE phy_ctl_wr_i1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mux_cmd_wren),\n .Q(phy_ctl_wr_i1),\n .R(1'b0));\n FDRE phy_ctl_wr_i2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(phy_ctl_wr_i1),\n .Q(phy_ctl_wr_i2),\n .R(1'b0));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CAPACITANCE = \"DONT_CARE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n u_cas_n_obuf\n (.I(mem_dq_out[74]),\n .O(ddr3_cas_n));\n ddr3_if_mig_7series_v4_0_ddr_mc_phy u_ddr_mc_phy\n (.A(A),\n .CLK(CLK),\n .CLKB0(CLKB0),\n .CLKB0_7(CLKB0_7),\n .CLKB0_8(CLKB0_8),\n .CLKB0_9(CLKB0_9),\n .COUNTERLOADVAL(COUNTERLOADVAL),\n .D0(D0),\n .D1(D1),\n .D2(D2),\n .D3(D3),\n .D4(D4),\n .D5(D5),\n .D6(D6),\n .D7(D7),\n .D8(D8),\n .D9(D9),\n .DOA(DOA),\n .DOB(DOB),\n .DOC(DOC),\n .D_po_coarse_enable110_out(D_po_coarse_enable110_out),\n .D_po_counter_read_en122_out(D_po_counter_read_en122_out),\n .D_po_fine_enable107_out(D_po_fine_enable107_out),\n .D_po_fine_inc113_out(D_po_fine_inc113_out),\n .D_po_sel_fine_oclk_delay125_out(D_po_sel_fine_oclk_delay125_out),\n .E(E),\n .LD0(LD0),\n .LD0_3(LD0_3),\n .LD0_4(LD0_4),\n .LD0_5(LD0_5),\n .Q({phy_ctl_wd_i2[24:17],phy_ctl_wd_i2[2:0]}),\n .RST0(RST0),\n .\\byte_r_reg[0] (\\byte_r_reg[0] ),\n .\\byte_r_reg[0]_0 (\\byte_r_reg[0]_0 ),\n .\\byte_r_reg[1] (\\byte_r_reg[1] ),\n .\\calib_sel_reg[0] (\\calib_sel_reg[0] ),\n .\\calib_sel_reg[0]_0 (\\calib_sel_reg[0]_0 ),\n .\\calib_sel_reg[0]_1 (\\calib_sel_reg[0]_1 ),\n .\\calib_sel_reg[0]_2 (\\calib_sel_reg[0]_2 ),\n .\\calib_sel_reg[0]_3 (\\calib_sel_reg[0]_3 ),\n .\\calib_sel_reg[0]_4 (\\calib_sel_reg[0]_4 ),\n .\\calib_sel_reg[0]_5 (\\calib_sel_reg[0]_5 ),\n .\\calib_sel_reg[0]_6 (\\calib_sel_reg[0]_6 ),\n .\\calib_sel_reg[0]_7 (\\calib_sel_reg[0]_7 ),\n .\\calib_sel_reg[1] (\\calib_sel_reg[1] ),\n .\\calib_sel_reg[1]_0 (\\calib_sel_reg[1]_0 ),\n .\\calib_sel_reg[1]_1 (\\calib_sel_reg[1]_1 ),\n .\\calib_sel_reg[1]_2 (\\calib_sel_reg[1]_2 ),\n .\\calib_sel_reg[1]_3 (\\calib_sel_reg[1]_3 ),\n .\\calib_sel_reg[1]_4 (\\calib_sel_reg[1]_4 ),\n .\\calib_sel_reg[1]_5 (\\calib_sel_reg[1]_5 ),\n .\\calib_sel_reg[1]_6 (\\calib_sel_reg[1]_6 ),\n .\\calib_sel_reg[1]_7 (\\calib_sel_reg[1]_7 ),\n .\\calib_sel_reg[1]_8 (\\calib_sel_reg[1]_8 ),\n .\\calib_sel_reg[3] (\\calib_sel_reg[3] ),\n .\\calib_seq_reg[0] (\\calib_seq_reg[0] ),\n .\\calib_zero_inputs_reg[0] (\\calib_zero_inputs_reg[0] ),\n .\\calib_zero_inputs_reg[0]_0 (\\calib_zero_inputs_reg[0]_0 ),\n .\\calib_zero_inputs_reg[0]_1 (\\calib_zero_inputs_reg[0]_1 ),\n .ck_po_stg2_f_en_reg(ck_po_stg2_f_en_reg),\n .ck_po_stg2_f_en_reg_0(ck_po_stg2_f_en_reg_0),\n .ck_po_stg2_f_en_reg_1(ck_po_stg2_f_en_reg_1),\n .ck_po_stg2_f_en_reg_2(ck_po_stg2_f_en_reg_2),\n .ck_po_stg2_f_indec_reg(ck_po_stg2_f_indec_reg),\n .ck_po_stg2_f_indec_reg_0(ck_po_stg2_f_indec_reg_0),\n .ck_po_stg2_f_indec_reg_1(ck_po_stg2_f_indec_reg_1),\n .ck_po_stg2_f_indec_reg_2(ck_po_stg2_f_indec_reg_2),\n .\\cmd_pipe_plus.mc_address_reg[43] (\\cmd_pipe_plus.mc_address_reg[43] ),\n .\\data_bytes_r_reg[63] (\\data_bytes_r_reg[63] ),\n .\\data_offset_1_i2_reg[5] (data_offset_1_i2),\n .ddr_ck_out(ddr_ck_out),\n .delay_done_r4_reg(delay_done_r4_reg),\n .delay_done_r4_reg_0(delay_done_r4_reg_0),\n .delay_done_r4_reg_1(delay_done_r4_reg_1),\n .delay_done_r4_reg_2(delay_done_r4_reg_2),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ),\n .\\fine_delay_mod_reg[23] (\\fine_delay_mod_reg[23]_0 ),\n .freq_refclk(freq_refclk),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\gen_byte_sel_div1.calib_in_common_reg ),\n .\\gen_byte_sel_div1.calib_in_common_reg_0 (\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_1 (\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_10 (\\gen_byte_sel_div1.calib_in_common_reg_10 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_11 (\\gen_byte_sel_div1.calib_in_common_reg_11 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_12 (\\gen_byte_sel_div1.calib_in_common_reg_12 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_13 (\\gen_byte_sel_div1.calib_in_common_reg_13 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_14 (\\gen_byte_sel_div1.calib_in_common_reg_14 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_15 (\\gen_byte_sel_div1.calib_in_common_reg_15 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_16 (\\gen_byte_sel_div1.calib_in_common_reg_16 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_17 (\\gen_byte_sel_div1.calib_in_common_reg_17 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_18 (\\gen_byte_sel_div1.calib_in_common_reg_18 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_19 (\\gen_byte_sel_div1.calib_in_common_reg_19 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_2 (\\gen_byte_sel_div1.calib_in_common_reg_2 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_20 (\\gen_byte_sel_div1.calib_in_common_reg_20 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_3 (\\gen_byte_sel_div1.calib_in_common_reg_3 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_4 (\\gen_byte_sel_div1.calib_in_common_reg_4 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_5 (\\gen_byte_sel_div1.calib_in_common_reg_5 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_6 (\\gen_byte_sel_div1.calib_in_common_reg_6 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_7 (\\gen_byte_sel_div1.calib_in_common_reg_7 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_8 (\\gen_byte_sel_div1.calib_in_common_reg_8 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_9 (\\gen_byte_sel_div1.calib_in_common_reg_9 ),\n .\\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] (\\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] (\\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] (\\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] (\\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] (\\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] (\\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] (\\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] (\\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),\n .\\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] (\\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] (\\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] (\\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] (\\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] (\\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] (\\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] (\\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] (\\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),\n .\\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] (\\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] (\\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] (\\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] (\\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] (\\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] (\\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] (\\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] (\\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),\n .\\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] (\\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] (\\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] (\\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] (\\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] (\\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] (\\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] (\\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] (\\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),\n .\\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] (\\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] (\\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] (\\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] (\\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] (\\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] (\\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] (\\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] (\\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),\n .\\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] (\\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] (\\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] (\\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] (\\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] (\\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] (\\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] (\\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] (\\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),\n .\\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] (\\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] (\\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] (\\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] (\\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] (\\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] (\\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] (\\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] (\\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),\n .\\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] (\\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] (\\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] (\\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] (\\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] (\\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] (\\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] (\\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] (\\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] (\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] (\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ),\n .\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] (\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ),\n .\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] (\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ),\n .\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] (\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ),\n .\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] (\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ),\n .idelay_inc(idelay_inc),\n .idelay_ld_rst(idelay_ld_rst),\n .idelay_ld_rst_0(idelay_ld_rst_0),\n .idelay_ld_rst_1(idelay_ld_rst_1),\n .idelay_ld_rst_2(idelay_ld_rst_2),\n .in0(in0),\n .init_calib_complete_reg_rep(init_calib_complete_reg_rep),\n .init_calib_complete_reg_rep__5(init_calib_complete_reg_rep__5),\n .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6),\n .init_calib_complete_reg_rep__6_0(init_calib_complete_reg_rep__6_0),\n .mc_cas_n(mc_cas_n),\n .mem_dq_in({mem_dq_in[38:31],mem_dq_in[28:21],mem_dq_in[18:11],mem_dq_in[7:0]}),\n .mem_dq_out({mem_dq_out[93:85],mem_dq_out[83:74],mem_dq_out[71:70],mem_dq_out[64],mem_dq_out[49:48],mem_dq_out[45:37],mem_dq_out[33:25],mem_dq_out[21:13],mem_dq_out[9],mem_dq_out[7:0]}),\n .mem_dq_ts({mem_dq_ts[45:37],mem_dq_ts[33:25],mem_dq_ts[21:13],mem_dq_ts[9],mem_dq_ts[7:0]}),\n .mem_dqs_in(mem_dqs_in),\n .mem_dqs_out(mem_dqs_out),\n .mem_dqs_ts(mem_dqs_ts),\n .mem_out(mem_out),\n .mem_refclk(mem_refclk),\n .mmcm_locked(mmcm_locked),\n .mux_cmd_wren(mux_cmd_wren),\n .mux_rd_valid_r_reg(mux_rd_valid_r_reg),\n .mux_wrdata(mux_wrdata),\n .mux_wrdata_en(mux_wrdata_en),\n .mux_wrdata_mask(mux_wrdata_mask),\n .\\my_empty_reg[1] (\\my_empty_reg[1] ),\n .\\my_empty_reg[1]_0 (\\my_empty_reg[1]_0 ),\n .\\my_empty_reg[1]_1 (\\my_empty_reg[1]_1 ),\n .\\my_empty_reg[1]_2 (\\my_empty_reg[1]_2 ),\n .\\my_empty_reg[1]_3 (\\my_empty_reg[1]_3 ),\n .\\my_empty_reg[1]_4 (\\my_empty_reg[1]_4 ),\n .\\my_empty_reg[1]_5 (\\my_empty_reg[1]_5 ),\n .\\my_empty_reg[1]_6 (\\my_empty_reg[1]_6 ),\n .\\my_empty_reg[7] (\\my_empty_reg[7]_0 ),\n .\\my_empty_reg[7]_0 (\\my_empty_reg[7]_1 ),\n .\\my_empty_reg[7]_1 (\\my_empty_reg[7]_2 ),\n .\\my_empty_reg[7]_2 (\\my_empty_reg[7]_3 ),\n .\\my_empty_reg[7]_3 (\\my_empty_reg[7] ),\n .\\not_strict_mode.app_rd_data_reg[0] (\\not_strict_mode.app_rd_data_reg[0] ),\n .\\not_strict_mode.app_rd_data_reg[100] (\\not_strict_mode.app_rd_data_reg[100] ),\n .\\not_strict_mode.app_rd_data_reg[101] (\\not_strict_mode.app_rd_data_reg[101] ),\n .\\not_strict_mode.app_rd_data_reg[102] (\\not_strict_mode.app_rd_data_reg[102] ),\n .\\not_strict_mode.app_rd_data_reg[103] (\\not_strict_mode.app_rd_data_reg[103] ),\n .\\not_strict_mode.app_rd_data_reg[104] (\\not_strict_mode.app_rd_data_reg[104] ),\n .\\not_strict_mode.app_rd_data_reg[105] (\\not_strict_mode.app_rd_data_reg[105] ),\n .\\not_strict_mode.app_rd_data_reg[106] (\\not_strict_mode.app_rd_data_reg[106] ),\n .\\not_strict_mode.app_rd_data_reg[107] (\\not_strict_mode.app_rd_data_reg[107] ),\n .\\not_strict_mode.app_rd_data_reg[108] (\\not_strict_mode.app_rd_data_reg[108] ),\n .\\not_strict_mode.app_rd_data_reg[109] (\\not_strict_mode.app_rd_data_reg[109] ),\n .\\not_strict_mode.app_rd_data_reg[10] (\\not_strict_mode.app_rd_data_reg[10] ),\n .\\not_strict_mode.app_rd_data_reg[110] (\\not_strict_mode.app_rd_data_reg[110] ),\n .\\not_strict_mode.app_rd_data_reg[111] (\\not_strict_mode.app_rd_data_reg[111] ),\n .\\not_strict_mode.app_rd_data_reg[112] (\\not_strict_mode.app_rd_data_reg[112] ),\n .\\not_strict_mode.app_rd_data_reg[113] (\\not_strict_mode.app_rd_data_reg[113] ),\n .\\not_strict_mode.app_rd_data_reg[114] (\\not_strict_mode.app_rd_data_reg[114] ),\n .\\not_strict_mode.app_rd_data_reg[115] (\\not_strict_mode.app_rd_data_reg[115] ),\n .\\not_strict_mode.app_rd_data_reg[116] (\\not_strict_mode.app_rd_data_reg[116] ),\n .\\not_strict_mode.app_rd_data_reg[117] (\\not_strict_mode.app_rd_data_reg[117] ),\n .\\not_strict_mode.app_rd_data_reg[118] (\\not_strict_mode.app_rd_data_reg[118] ),\n .\\not_strict_mode.app_rd_data_reg[119] (\\not_strict_mode.app_rd_data_reg[119] ),\n .\\not_strict_mode.app_rd_data_reg[11] (\\not_strict_mode.app_rd_data_reg[11] ),\n .\\not_strict_mode.app_rd_data_reg[120] (\\not_strict_mode.app_rd_data_reg[120] ),\n .\\not_strict_mode.app_rd_data_reg[121] (\\not_strict_mode.app_rd_data_reg[121] ),\n .\\not_strict_mode.app_rd_data_reg[122] (\\not_strict_mode.app_rd_data_reg[122] ),\n .\\not_strict_mode.app_rd_data_reg[123] (\\not_strict_mode.app_rd_data_reg[123] ),\n .\\not_strict_mode.app_rd_data_reg[124] (\\not_strict_mode.app_rd_data_reg[124] ),\n .\\not_strict_mode.app_rd_data_reg[125] (\\not_strict_mode.app_rd_data_reg[125] ),\n .\\not_strict_mode.app_rd_data_reg[126] (\\not_strict_mode.app_rd_data_reg[126] ),\n .\\not_strict_mode.app_rd_data_reg[127] (\\not_strict_mode.app_rd_data_reg[127] ),\n .\\not_strict_mode.app_rd_data_reg[128] (\\not_strict_mode.app_rd_data_reg[128] ),\n .\\not_strict_mode.app_rd_data_reg[129] (\\not_strict_mode.app_rd_data_reg[129] ),\n .\\not_strict_mode.app_rd_data_reg[12] (\\not_strict_mode.app_rd_data_reg[12] ),\n .\\not_strict_mode.app_rd_data_reg[130] (\\not_strict_mode.app_rd_data_reg[130] ),\n .\\not_strict_mode.app_rd_data_reg[131] (\\not_strict_mode.app_rd_data_reg[131] ),\n .\\not_strict_mode.app_rd_data_reg[132] (\\not_strict_mode.app_rd_data_reg[132] ),\n .\\not_strict_mode.app_rd_data_reg[133] (\\not_strict_mode.app_rd_data_reg[133] ),\n .\\not_strict_mode.app_rd_data_reg[134] (\\not_strict_mode.app_rd_data_reg[134] ),\n .\\not_strict_mode.app_rd_data_reg[135] (\\not_strict_mode.app_rd_data_reg[135] ),\n .\\not_strict_mode.app_rd_data_reg[136] (\\not_strict_mode.app_rd_data_reg[136] ),\n .\\not_strict_mode.app_rd_data_reg[137] (\\not_strict_mode.app_rd_data_reg[137] ),\n .\\not_strict_mode.app_rd_data_reg[138] (\\not_strict_mode.app_rd_data_reg[138] ),\n .\\not_strict_mode.app_rd_data_reg[139] (\\not_strict_mode.app_rd_data_reg[139] ),\n .\\not_strict_mode.app_rd_data_reg[13] (\\not_strict_mode.app_rd_data_reg[13] ),\n .\\not_strict_mode.app_rd_data_reg[140] (\\not_strict_mode.app_rd_data_reg[140] ),\n .\\not_strict_mode.app_rd_data_reg[141] (\\not_strict_mode.app_rd_data_reg[141] ),\n .\\not_strict_mode.app_rd_data_reg[142] (\\not_strict_mode.app_rd_data_reg[142] ),\n .\\not_strict_mode.app_rd_data_reg[143] (\\not_strict_mode.app_rd_data_reg[143] ),\n .\\not_strict_mode.app_rd_data_reg[144] (\\not_strict_mode.app_rd_data_reg[144] ),\n .\\not_strict_mode.app_rd_data_reg[145] (\\not_strict_mode.app_rd_data_reg[145] ),\n .\\not_strict_mode.app_rd_data_reg[146] (\\not_strict_mode.app_rd_data_reg[146] ),\n .\\not_strict_mode.app_rd_data_reg[147] (\\not_strict_mode.app_rd_data_reg[147] ),\n .\\not_strict_mode.app_rd_data_reg[148] (\\not_strict_mode.app_rd_data_reg[148] ),\n .\\not_strict_mode.app_rd_data_reg[149] (\\not_strict_mode.app_rd_data_reg[149] ),\n .\\not_strict_mode.app_rd_data_reg[14] (\\not_strict_mode.app_rd_data_reg[14] ),\n .\\not_strict_mode.app_rd_data_reg[150] (\\not_strict_mode.app_rd_data_reg[150] ),\n .\\not_strict_mode.app_rd_data_reg[151] (\\not_strict_mode.app_rd_data_reg[151] ),\n .\\not_strict_mode.app_rd_data_reg[152] (\\not_strict_mode.app_rd_data_reg[152] ),\n .\\not_strict_mode.app_rd_data_reg[153] (\\not_strict_mode.app_rd_data_reg[153] ),\n .\\not_strict_mode.app_rd_data_reg[154] (\\not_strict_mode.app_rd_data_reg[154] ),\n .\\not_strict_mode.app_rd_data_reg[155] (\\not_strict_mode.app_rd_data_reg[155] ),\n .\\not_strict_mode.app_rd_data_reg[156] (\\not_strict_mode.app_rd_data_reg[156] ),\n .\\not_strict_mode.app_rd_data_reg[157] (\\not_strict_mode.app_rd_data_reg[157] ),\n .\\not_strict_mode.app_rd_data_reg[158] (\\not_strict_mode.app_rd_data_reg[158] ),\n .\\not_strict_mode.app_rd_data_reg[159] (\\not_strict_mode.app_rd_data_reg[159] ),\n .\\not_strict_mode.app_rd_data_reg[15] (\\not_strict_mode.app_rd_data_reg[15] ),\n .\\not_strict_mode.app_rd_data_reg[15]_0 (\\not_strict_mode.app_rd_data_reg[15]_0 ),\n .\\not_strict_mode.app_rd_data_reg[15]_1 (\\not_strict_mode.app_rd_data_reg[15]_1 ),\n .\\not_strict_mode.app_rd_data_reg[160] (\\not_strict_mode.app_rd_data_reg[160] ),\n .\\not_strict_mode.app_rd_data_reg[161] (\\not_strict_mode.app_rd_data_reg[161] ),\n .\\not_strict_mode.app_rd_data_reg[162] (\\not_strict_mode.app_rd_data_reg[162] ),\n .\\not_strict_mode.app_rd_data_reg[163] (\\not_strict_mode.app_rd_data_reg[163] ),\n .\\not_strict_mode.app_rd_data_reg[164] (\\not_strict_mode.app_rd_data_reg[164] ),\n .\\not_strict_mode.app_rd_data_reg[165] (\\not_strict_mode.app_rd_data_reg[165] ),\n .\\not_strict_mode.app_rd_data_reg[166] (\\not_strict_mode.app_rd_data_reg[166] ),\n .\\not_strict_mode.app_rd_data_reg[167] (\\not_strict_mode.app_rd_data_reg[167] ),\n .\\not_strict_mode.app_rd_data_reg[168] (\\not_strict_mode.app_rd_data_reg[168] ),\n .\\not_strict_mode.app_rd_data_reg[169] (\\not_strict_mode.app_rd_data_reg[169] ),\n .\\not_strict_mode.app_rd_data_reg[16] (\\not_strict_mode.app_rd_data_reg[16] ),\n .\\not_strict_mode.app_rd_data_reg[170] (\\not_strict_mode.app_rd_data_reg[170] ),\n .\\not_strict_mode.app_rd_data_reg[171] (\\not_strict_mode.app_rd_data_reg[171] ),\n .\\not_strict_mode.app_rd_data_reg[172] (\\not_strict_mode.app_rd_data_reg[172] ),\n .\\not_strict_mode.app_rd_data_reg[173] (\\not_strict_mode.app_rd_data_reg[173] ),\n .\\not_strict_mode.app_rd_data_reg[174] (\\not_strict_mode.app_rd_data_reg[174] ),\n .\\not_strict_mode.app_rd_data_reg[175] (\\not_strict_mode.app_rd_data_reg[175] ),\n .\\not_strict_mode.app_rd_data_reg[176] (\\not_strict_mode.app_rd_data_reg[176] ),\n .\\not_strict_mode.app_rd_data_reg[177] (\\not_strict_mode.app_rd_data_reg[177] ),\n .\\not_strict_mode.app_rd_data_reg[178] (\\not_strict_mode.app_rd_data_reg[178] ),\n .\\not_strict_mode.app_rd_data_reg[179] (\\not_strict_mode.app_rd_data_reg[179] ),\n .\\not_strict_mode.app_rd_data_reg[17] (\\not_strict_mode.app_rd_data_reg[17] ),\n .\\not_strict_mode.app_rd_data_reg[180] (\\not_strict_mode.app_rd_data_reg[180] ),\n .\\not_strict_mode.app_rd_data_reg[181] (\\not_strict_mode.app_rd_data_reg[181] ),\n .\\not_strict_mode.app_rd_data_reg[182] (\\not_strict_mode.app_rd_data_reg[182] ),\n .\\not_strict_mode.app_rd_data_reg[183] (\\not_strict_mode.app_rd_data_reg[183] ),\n .\\not_strict_mode.app_rd_data_reg[184] (\\not_strict_mode.app_rd_data_reg[184] ),\n .\\not_strict_mode.app_rd_data_reg[185] (\\not_strict_mode.app_rd_data_reg[185] ),\n .\\not_strict_mode.app_rd_data_reg[186] (\\not_strict_mode.app_rd_data_reg[186] ),\n .\\not_strict_mode.app_rd_data_reg[187] (\\not_strict_mode.app_rd_data_reg[187] ),\n .\\not_strict_mode.app_rd_data_reg[188] (\\not_strict_mode.app_rd_data_reg[188] ),\n .\\not_strict_mode.app_rd_data_reg[189] (\\not_strict_mode.app_rd_data_reg[189] ),\n .\\not_strict_mode.app_rd_data_reg[18] (\\not_strict_mode.app_rd_data_reg[18] ),\n .\\not_strict_mode.app_rd_data_reg[190] (\\not_strict_mode.app_rd_data_reg[190] ),\n .\\not_strict_mode.app_rd_data_reg[191] (\\not_strict_mode.app_rd_data_reg[191] ),\n .\\not_strict_mode.app_rd_data_reg[192] (\\not_strict_mode.app_rd_data_reg[192] ),\n .\\not_strict_mode.app_rd_data_reg[193] (\\not_strict_mode.app_rd_data_reg[193] ),\n .\\not_strict_mode.app_rd_data_reg[194] (\\not_strict_mode.app_rd_data_reg[194] ),\n .\\not_strict_mode.app_rd_data_reg[195] (\\not_strict_mode.app_rd_data_reg[195] ),\n .\\not_strict_mode.app_rd_data_reg[196] (\\not_strict_mode.app_rd_data_reg[196] ),\n .\\not_strict_mode.app_rd_data_reg[197] (\\not_strict_mode.app_rd_data_reg[197] ),\n .\\not_strict_mode.app_rd_data_reg[198] (\\not_strict_mode.app_rd_data_reg[198] ),\n .\\not_strict_mode.app_rd_data_reg[199] (\\not_strict_mode.app_rd_data_reg[199] ),\n .\\not_strict_mode.app_rd_data_reg[19] (\\not_strict_mode.app_rd_data_reg[19] ),\n .\\not_strict_mode.app_rd_data_reg[1] (\\not_strict_mode.app_rd_data_reg[1] ),\n .\\not_strict_mode.app_rd_data_reg[200] (\\not_strict_mode.app_rd_data_reg[200] ),\n .\\not_strict_mode.app_rd_data_reg[201] (\\not_strict_mode.app_rd_data_reg[201] ),\n .\\not_strict_mode.app_rd_data_reg[202] (\\not_strict_mode.app_rd_data_reg[202] ),\n .\\not_strict_mode.app_rd_data_reg[203] (\\not_strict_mode.app_rd_data_reg[203] ),\n .\\not_strict_mode.app_rd_data_reg[204] (\\not_strict_mode.app_rd_data_reg[204] ),\n .\\not_strict_mode.app_rd_data_reg[205] (\\not_strict_mode.app_rd_data_reg[205] ),\n .\\not_strict_mode.app_rd_data_reg[206] (\\not_strict_mode.app_rd_data_reg[206] ),\n .\\not_strict_mode.app_rd_data_reg[207] (\\not_strict_mode.app_rd_data_reg[207] ),\n .\\not_strict_mode.app_rd_data_reg[208] (\\not_strict_mode.app_rd_data_reg[208] ),\n .\\not_strict_mode.app_rd_data_reg[209] (\\not_strict_mode.app_rd_data_reg[209] ),\n .\\not_strict_mode.app_rd_data_reg[20] (\\not_strict_mode.app_rd_data_reg[20] ),\n .\\not_strict_mode.app_rd_data_reg[210] (\\not_strict_mode.app_rd_data_reg[210] ),\n .\\not_strict_mode.app_rd_data_reg[211] (\\not_strict_mode.app_rd_data_reg[211] ),\n .\\not_strict_mode.app_rd_data_reg[212] (\\not_strict_mode.app_rd_data_reg[212] ),\n .\\not_strict_mode.app_rd_data_reg[213] (\\not_strict_mode.app_rd_data_reg[213] ),\n .\\not_strict_mode.app_rd_data_reg[214] (\\not_strict_mode.app_rd_data_reg[214] ),\n .\\not_strict_mode.app_rd_data_reg[215] (\\not_strict_mode.app_rd_data_reg[215] ),\n .\\not_strict_mode.app_rd_data_reg[216] (\\not_strict_mode.app_rd_data_reg[216] ),\n .\\not_strict_mode.app_rd_data_reg[217] (\\not_strict_mode.app_rd_data_reg[217] ),\n .\\not_strict_mode.app_rd_data_reg[218] (\\not_strict_mode.app_rd_data_reg[218] ),\n .\\not_strict_mode.app_rd_data_reg[219] (\\not_strict_mode.app_rd_data_reg[219] ),\n .\\not_strict_mode.app_rd_data_reg[21] (\\not_strict_mode.app_rd_data_reg[21] ),\n .\\not_strict_mode.app_rd_data_reg[220] (\\not_strict_mode.app_rd_data_reg[220] ),\n .\\not_strict_mode.app_rd_data_reg[221] (\\not_strict_mode.app_rd_data_reg[221] ),\n .\\not_strict_mode.app_rd_data_reg[222] (\\not_strict_mode.app_rd_data_reg[222] ),\n .\\not_strict_mode.app_rd_data_reg[223] (\\not_strict_mode.app_rd_data_reg[223] ),\n .\\not_strict_mode.app_rd_data_reg[224] (\\not_strict_mode.app_rd_data_reg[224] ),\n .\\not_strict_mode.app_rd_data_reg[225] (\\not_strict_mode.app_rd_data_reg[225] ),\n .\\not_strict_mode.app_rd_data_reg[226] (\\not_strict_mode.app_rd_data_reg[226] ),\n .\\not_strict_mode.app_rd_data_reg[227] (\\not_strict_mode.app_rd_data_reg[227] ),\n .\\not_strict_mode.app_rd_data_reg[228] (\\not_strict_mode.app_rd_data_reg[228] ),\n .\\not_strict_mode.app_rd_data_reg[228]_0 (\\not_strict_mode.app_rd_data_reg[228]_0 ),\n .\\not_strict_mode.app_rd_data_reg[229] (\\not_strict_mode.app_rd_data_reg[229] ),\n .\\not_strict_mode.app_rd_data_reg[22] (\\not_strict_mode.app_rd_data_reg[22] ),\n .\\not_strict_mode.app_rd_data_reg[230] (\\not_strict_mode.app_rd_data_reg[230] ),\n .\\not_strict_mode.app_rd_data_reg[231] (\\not_strict_mode.app_rd_data_reg[231] ),\n .\\not_strict_mode.app_rd_data_reg[232] (\\not_strict_mode.app_rd_data_reg[232] ),\n .\\not_strict_mode.app_rd_data_reg[233] (\\not_strict_mode.app_rd_data_reg[233] ),\n .\\not_strict_mode.app_rd_data_reg[234] (\\not_strict_mode.app_rd_data_reg[234] ),\n .\\not_strict_mode.app_rd_data_reg[235] (\\not_strict_mode.app_rd_data_reg[235] ),\n .\\not_strict_mode.app_rd_data_reg[236] (\\not_strict_mode.app_rd_data_reg[236] ),\n .\\not_strict_mode.app_rd_data_reg[236]_0 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.\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ),\n .\\not_strict_mode.status_ram.rd_buf_we_r1_reg (\\not_strict_mode.status_ram.rd_buf_we_r1_reg ),\n .of_ctl_full_v(of_ctl_full_v),\n .ofs_rdy_r_reg(ofs_rdy_r_reg),\n .ofs_rdy_r_reg_0(ofs_rdy_r_reg_0),\n .out(out),\n .p_0_out(p_0_out),\n .phy_ctl_wr_i2(phy_ctl_wr_i2),\n .phy_dout(phy_dout),\n .phy_if_empty_r_reg(phy_if_empty_r_reg),\n .phy_if_reset(phy_if_reset),\n .phy_mc_ctl_full(phy_mc_ctl_full),\n .phy_rddata_en(phy_rddata_en),\n .phy_read_calib(phy_read_calib),\n .phy_write_calib(phy_write_calib),\n .\\pi_dqs_found_lanes_r1_reg[3] (\\pi_dqs_found_lanes_r1_reg[3] ),\n .pi_en_stg2_f_reg(pi_en_stg2_f_reg),\n .pi_en_stg2_f_reg_0(pi_en_stg2_f_reg_0),\n .pi_en_stg2_f_reg_1(pi_en_stg2_f_reg_1),\n .pi_en_stg2_f_reg_2(pi_en_stg2_f_reg_2),\n .pi_phase_locked_all_r1_reg(pi_phase_locked_all_r1_reg),\n .\\pi_rdval_cnt_reg[5] (\\pi_rdval_cnt_reg[5] ),\n .pi_stg2_f_incdec_reg(pi_stg2_f_incdec_reg),\n .pi_stg2_f_incdec_reg_0(pi_stg2_f_incdec_reg_0),\n .pi_stg2_f_incdec_reg_1(pi_stg2_f_incdec_reg_1),\n .pi_stg2_f_incdec_reg_2(pi_stg2_f_incdec_reg_2),\n .pll_locked(pll_locked),\n .\\po_counter_read_val_r_reg[5] (\\po_counter_read_val_r_reg[5] ),\n .\\po_rdval_cnt_reg[8] (\\po_rdval_cnt_reg[8] ),\n .\\po_rdval_cnt_reg[8]_0 (\\po_rdval_cnt_reg[8]_0 ),\n .\\po_stg2_wrcal_cnt_reg[1] (\\po_stg2_wrcal_cnt_reg[1] ),\n .prbs_rdlvl_start_reg(prbs_rdlvl_start_reg),\n .ram_init_done_r(ram_init_done_r),\n .rd_buf_we(rd_buf_we),\n .\\rd_mux_sel_r_reg[1] (\\rd_mux_sel_r_reg[1] ),\n .\\rd_ptr_reg[3] (\\rd_ptr_reg[3] ),\n .\\rd_ptr_reg[3]_0 (\\rd_ptr_reg[3]_0 ),\n .\\rd_ptr_timing_reg[2] (\\rd_ptr_timing_reg[2] ),\n .\\rd_ptr_timing_reg[2]_0 (\\rd_ptr_timing_reg[2]_0 ),\n .\\rd_ptr_timing_reg[2]_1 (\\rd_ptr_timing_reg[2]_1 ),\n .\\rd_ptr_timing_reg[2]_10 (\\rd_ptr_timing_reg[2]_10 ),\n .\\rd_ptr_timing_reg[2]_2 (\\rd_ptr_timing_reg[2]_2 ),\n .\\rd_ptr_timing_reg[2]_3 (\\rd_ptr_timing_reg[2]_3 ),\n .\\rd_ptr_timing_reg[2]_4 (\\rd_ptr_timing_reg[2]_4 ),\n .\\rd_ptr_timing_reg[2]_5 (\\rd_ptr_timing_reg[2]_5 ),\n .\\rd_ptr_timing_reg[2]_6 (\\rd_ptr_timing_reg[2]_6 ),\n .\\rd_ptr_timing_reg[2]_7 (\\rd_ptr_timing_reg[2]_7 ),\n .\\rd_ptr_timing_reg[2]_8 (\\rd_ptr_timing_reg[2]_8 ),\n .\\rd_ptr_timing_reg[2]_9 (\\rd_ptr_timing_reg[2]_9 ),\n .\\read_fifo.fifo_out_data_r_reg[6] (\\read_fifo.fifo_out_data_r_reg[6] ),\n .\\read_fifo.fifo_out_data_r_reg[6]_0 (\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .\\read_fifo.tail_r_reg[0] (\\read_fifo.tail_r_reg[0] ),\n .\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] (\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .rst_sync_r1_reg(rst_sync_r1_reg),\n .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9),\n .sync_pulse(sync_pulse),\n .sys_rst(sys_rst),\n .tail_r(tail_r),\n .wr_en(wr_en),\n .wr_en_5(wr_en_5),\n .wr_en_6(wr_en_6),\n .\\wr_ptr_timing_reg[2] (\\wr_ptr_timing_reg[2] ),\n .\\wr_ptr_timing_reg[2]_0 (\\wr_ptr_timing_reg[2]_0 ),\n .\\wr_ptr_timing_reg[2]_1 (\\wr_ptr_timing_reg[2]_1 ),\n .\\write_buffer.wr_buf_out_data_reg[224] (\\write_buffer.wr_buf_out_data_reg[224] ),\n .\\write_buffer.wr_buf_out_data_reg[225] (\\write_buffer.wr_buf_out_data_reg[225] ),\n .\\write_buffer.wr_buf_out_data_reg[226] (\\write_buffer.wr_buf_out_data_reg[226] ),\n .\\write_buffer.wr_buf_out_data_reg[227] (\\write_buffer.wr_buf_out_data_reg[227] ),\n .\\write_buffer.wr_buf_out_data_reg[228] (\\write_buffer.wr_buf_out_data_reg[228] ),\n .\\write_buffer.wr_buf_out_data_reg[229] (\\write_buffer.wr_buf_out_data_reg[229] ),\n .\\write_buffer.wr_buf_out_data_reg[230] (\\write_buffer.wr_buf_out_data_reg[230] ),\n .\\write_buffer.wr_buf_out_data_reg[231] (\\write_buffer.wr_buf_out_data_reg[231] ),\n .\\write_buffer.wr_buf_out_data_reg[232] (\\write_buffer.wr_buf_out_data_reg[232] ),\n .\\write_buffer.wr_buf_out_data_reg[233] (\\write_buffer.wr_buf_out_data_reg[233] ),\n .\\write_buffer.wr_buf_out_data_reg[234] (\\write_buffer.wr_buf_out_data_reg[234] ),\n .\\write_buffer.wr_buf_out_data_reg[235] (\\write_buffer.wr_buf_out_data_reg[235] ),\n .\\write_buffer.wr_buf_out_data_reg[236] (\\write_buffer.wr_buf_out_data_reg[236] ),\n .\\write_buffer.wr_buf_out_data_reg[237] (\\write_buffer.wr_buf_out_data_reg[237] ),\n .\\write_buffer.wr_buf_out_data_reg[238] (\\write_buffer.wr_buf_out_data_reg[238] ),\n .\\write_buffer.wr_buf_out_data_reg[239] (\\write_buffer.wr_buf_out_data_reg[239] ),\n .\\write_buffer.wr_buf_out_data_reg[240] (\\write_buffer.wr_buf_out_data_reg[240] ),\n .\\write_buffer.wr_buf_out_data_reg[241] (\\write_buffer.wr_buf_out_data_reg[241] ),\n .\\write_buffer.wr_buf_out_data_reg[242] (\\write_buffer.wr_buf_out_data_reg[242] ),\n .\\write_buffer.wr_buf_out_data_reg[243] (\\write_buffer.wr_buf_out_data_reg[243] ),\n .\\write_buffer.wr_buf_out_data_reg[244] (\\write_buffer.wr_buf_out_data_reg[244] ),\n .\\write_buffer.wr_buf_out_data_reg[245] (\\write_buffer.wr_buf_out_data_reg[245] ),\n .\\write_buffer.wr_buf_out_data_reg[246] (\\write_buffer.wr_buf_out_data_reg[246] ),\n .\\write_buffer.wr_buf_out_data_reg[247] (\\write_buffer.wr_buf_out_data_reg[247] ),\n .\\write_buffer.wr_buf_out_data_reg[248] (\\write_buffer.wr_buf_out_data_reg[248] ),\n .\\write_buffer.wr_buf_out_data_reg[249] (\\write_buffer.wr_buf_out_data_reg[249] ),\n .\\write_buffer.wr_buf_out_data_reg[250] (\\write_buffer.wr_buf_out_data_reg[250] ),\n .\\write_buffer.wr_buf_out_data_reg[251] (\\write_buffer.wr_buf_out_data_reg[251] ),\n .\\write_buffer.wr_buf_out_data_reg[252] (\\write_buffer.wr_buf_out_data_reg[252] ),\n .\\write_buffer.wr_buf_out_data_reg[253] (\\write_buffer.wr_buf_out_data_reg[253] ),\n .\\write_buffer.wr_buf_out_data_reg[254] (\\write_buffer.wr_buf_out_data_reg[254] ),\n .\\write_buffer.wr_buf_out_data_reg[255] (\\write_buffer.wr_buf_out_data_reg[255] ),\n .\\write_buffer.wr_buf_out_data_reg[287] (Q));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CAPACITANCE = \"DONT_CARE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n u_ras_n_obuf\n (.I(mem_dq_out[75]),\n .O(ddr3_ras_n));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* CAPACITANCE = \"DONT_CARE\" *) \n OBUF #(\n .IOSTANDARD(\"DEFAULT\")) \n u_we_n_obuf\n (.I(mem_dq_out[49]),\n .O(ddr3_we_n));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo\n (rstdiv0_sync_r1_reg_rep__2,\n CLK,\n SR);\n input rstdiv0_sync_r1_reg_rep__2;\n input CLK;\n input [0:0]SR;\n\n wire CLK;\n wire [0:0]SR;\n (* MAX_FANOUT = \"50\" *) (* RTL_KEEP = \"true\" *) (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) wire [2:0]rd_ptr_timing;\n wire rstdiv0_sync_r1_reg_rep__2;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) wire wr_en;\n (* MAX_FANOUT = \"50\" *) (* RTL_KEEP = \"true\" *) (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) wire [2:0]wr_ptr_timing;\n\n LUT1 #(\n .INIT(2'h2)) \n i_0\n (.I0(1'b0),\n .O(wr_en));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[0] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b1),\n .Q(rd_ptr_timing[0]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[1] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b0),\n .Q(rd_ptr_timing[1]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[2] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b0),\n .Q(rd_ptr_timing[2]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[0] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b1),\n .Q(wr_ptr_timing[0]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[1] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b0),\n .Q(wr_ptr_timing[1]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[2] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b0),\n .Q(wr_ptr_timing[2]),\n .R(SR));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_of_pre_fifo\" *) \nmodule ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized0\n (SR,\n CLK,\n rstdiv0_sync_r1_reg_rep__2);\n input [0:0]SR;\n input CLK;\n input rstdiv0_sync_r1_reg_rep__2;\n\n wire CLK;\n wire [0:0]SR;\n (* MAX_FANOUT = \"50\" *) (* RTL_KEEP = \"true\" *) (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) wire [2:0]rd_ptr_timing;\n wire rstdiv0_sync_r1_reg_rep__2;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) wire wr_en;\n (* MAX_FANOUT = \"50\" *) (* RTL_KEEP = \"true\" *) (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) wire [2:0]wr_ptr_timing;\n\n LUT1 #(\n .INIT(2'h2)) \n i_0\n (.I0(1'b0),\n .O(wr_en));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[0] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b1),\n .Q(rd_ptr_timing[0]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[1] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b0),\n .Q(rd_ptr_timing[1]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[2] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b0),\n .Q(rd_ptr_timing[2]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[0] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b1),\n .Q(wr_ptr_timing[0]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[1] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b0),\n .Q(wr_ptr_timing[1]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[2] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b0),\n .Q(wr_ptr_timing[2]),\n .R(rstdiv0_sync_r1_reg_rep__2));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_of_pre_fifo\" *) \nmodule ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized1\n (rstdiv0_sync_r1_reg_rep__2,\n CLK,\n SR);\n input rstdiv0_sync_r1_reg_rep__2;\n input CLK;\n input [0:0]SR;\n\n wire CLK;\n wire [0:0]SR;\n (* MAX_FANOUT = \"50\" *) (* RTL_KEEP = \"true\" *) (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) wire [2:0]rd_ptr_timing;\n wire rstdiv0_sync_r1_reg_rep__2;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) wire wr_en;\n (* MAX_FANOUT = \"50\" *) (* RTL_KEEP = \"true\" *) (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) wire [2:0]wr_ptr_timing;\n\n LUT1 #(\n .INIT(2'h2)) \n i_0\n (.I0(1'b0),\n .O(wr_en));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[0] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b1),\n .Q(rd_ptr_timing[0]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[1] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b0),\n .Q(rd_ptr_timing[1]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[2] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b0),\n .Q(rd_ptr_timing[2]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[0] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b1),\n .Q(wr_ptr_timing[0]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[1] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b0),\n .Q(wr_ptr_timing[1]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[2] \n (.C(CLK),\n .CE(1'b0),\n .D(1'b0),\n .Q(wr_ptr_timing[2]),\n .R(SR));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_of_pre_fifo\" *) \nmodule ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized2\n (\\my_empty_reg[7]_0 ,\n \\my_empty_reg[1]_0 ,\n D8,\n D9,\n \\my_empty_reg[7]_1 ,\n Q,\n ofifo_rst,\n CLK,\n ofifo_rst_reg,\n mux_wrdata_en,\n init_calib_complete_reg_rep,\n \\write_buffer.wr_buf_out_data_reg[287] ,\n phy_dout);\n output \\my_empty_reg[7]_0 ;\n output \\my_empty_reg[1]_0 ;\n output [7:0]D8;\n output [7:0]D9;\n output [63:0]\\my_empty_reg[7]_1 ;\n output [2:0]Q;\n input ofifo_rst;\n input CLK;\n input ofifo_rst_reg;\n input mux_wrdata_en;\n input init_calib_complete_reg_rep;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[287] ;\n input [71:0]phy_dout;\n\n wire CLK;\n wire [7:0]D8;\n wire [7:0]D9;\n wire [2:0]Q;\n wire \\entry_cnt[0]_i_1_n_0 ;\n wire \\entry_cnt[1]_i_1_n_0 ;\n wire \\entry_cnt[2]_i_1_n_0 ;\n wire \\entry_cnt[3]_i_1_n_0 ;\n wire \\entry_cnt[4]_i_1_n_0 ;\n wire \\entry_cnt[4]_i_2_n_0 ;\n wire \\entry_cnt[4]_i_3_n_0 ;\n wire \\entry_cnt_reg_n_0_[0] ;\n wire \\entry_cnt_reg_n_0_[1] ;\n wire init_calib_complete_reg_rep;\n wire mem_reg_0_15_60_65_n_4;\n wire mem_reg_0_15_60_65_n_5;\n wire mem_reg_0_15_66_71_n_0;\n wire mem_reg_0_15_66_71_n_1;\n wire mem_reg_0_15_66_71_n_2;\n wire mem_reg_0_15_66_71_n_3;\n wire mem_reg_0_15_66_71_n_4;\n wire mem_reg_0_15_66_71_n_5;\n wire mem_reg_0_15_72_77_n_0;\n wire mem_reg_0_15_72_77_n_1;\n wire mem_reg_0_15_72_77_n_2;\n wire mem_reg_0_15_72_77_n_3;\n wire mem_reg_0_15_72_77_n_4;\n wire mem_reg_0_15_72_77_n_5;\n wire mem_reg_0_15_78_79_n_0;\n wire mem_reg_0_15_78_79_n_1;\n wire mux_wrdata_en;\n wire my_empty0;\n wire \\my_empty[1]_i_1__0_n_0 ;\n wire \\my_empty[7]_i_1__0_n_0 ;\n wire \\my_empty[7]_i_3__0_n_0 ;\n wire \\my_empty[7]_i_4__0_n_0 ;\n wire \\my_empty_reg[1]_0 ;\n wire \\my_empty_reg[7]_0 ;\n wire [63:0]\\my_empty_reg[7]_1 ;\n wire \\my_empty_reg_n_0_[7] ;\n wire my_full0;\n wire \\my_full[4]_i_1_n_0 ;\n wire \\my_full[4]_i_3__0_n_0 ;\n wire \\my_full[4]_i_4__0_n_0 ;\n wire \\my_full_reg_n_0_[4] ;\n wire [3:0]nxt_rd_ptr;\n wire [3:0]nxt_wr_ptr;\n wire ofifo_rst;\n wire ofifo_rst_reg;\n wire [71:0]phy_dout;\n wire \\rd_ptr_reg_n_0_[0] ;\n wire \\rd_ptr_reg_n_0_[1] ;\n wire \\rd_ptr_reg_n_0_[2] ;\n wire \\rd_ptr_reg_n_0_[3] ;\n wire [3:0]rd_ptr_timing;\n wire \\rd_ptr_timing[3]_i_1__0_n_0 ;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) wire wr_en;\n wire [3:0]wr_ptr;\n wire wr_ptr0;\n wire [3:0]wr_ptr_timing;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[287] ;\n wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED;\n\n (* SOFT_HLUTNM = \"soft_lutpair772\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\entry_cnt[0]_i_1 \n (.I0(\\entry_cnt_reg_n_0_[0] ),\n .O(\\entry_cnt[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair769\" *) \n LUT5 #(\n .INIT(32'hAA6A5595)) \n \\entry_cnt[1]_i_1 \n (.I0(\\entry_cnt_reg_n_0_[0] ),\n .I1(ofifo_rst_reg),\n .I2(mux_wrdata_en),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(\\entry_cnt_reg_n_0_[1] ),\n .O(\\entry_cnt[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFF7F0080AAEA5515)) \n \\entry_cnt[2]_i_1 \n (.I0(\\entry_cnt_reg_n_0_[0] ),\n .I1(ofifo_rst_reg),\n .I2(mux_wrdata_en),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(Q[0]),\n .I5(\\entry_cnt_reg_n_0_[1] ),\n .O(\\entry_cnt[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair772\" *) \n LUT5 #(\n .INIT(32'h7F80FE01)) \n \\entry_cnt[3]_i_1 \n (.I0(\\entry_cnt[4]_i_3_n_0 ),\n .I1(\\entry_cnt_reg_n_0_[0] ),\n .I2(\\entry_cnt_reg_n_0_[1] ),\n .I3(Q[1]),\n .I4(Q[0]),\n .O(\\entry_cnt[3]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h5003)) \n \\entry_cnt[4]_i_1 \n (.I0(\\my_full_reg_n_0_[4] ),\n .I1(\\my_empty_reg_n_0_[7] ),\n .I2(mux_wrdata_en),\n .I3(ofifo_rst_reg),\n .O(\\entry_cnt[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h7FFF8000FFFE0001)) \n \\entry_cnt[4]_i_2 \n (.I0(\\entry_cnt_reg_n_0_[1] ),\n .I1(\\entry_cnt_reg_n_0_[0] ),\n .I2(\\entry_cnt[4]_i_3_n_0 ),\n .I3(Q[0]),\n .I4(Q[2]),\n .I5(Q[1]),\n .O(\\entry_cnt[4]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair769\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\entry_cnt[4]_i_3 \n (.I0(ofifo_rst_reg),\n .I1(mux_wrdata_en),\n .I2(\\my_full_reg_n_0_[4] ),\n .O(\\entry_cnt[4]_i_3_n_0 ));\n FDRE \\entry_cnt_reg[0] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1_n_0 ),\n .D(\\entry_cnt[0]_i_1_n_0 ),\n .Q(\\entry_cnt_reg_n_0_[0] ),\n .R(ofifo_rst));\n FDRE \\entry_cnt_reg[1] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1_n_0 ),\n .D(\\entry_cnt[1]_i_1_n_0 ),\n .Q(\\entry_cnt_reg_n_0_[1] ),\n .R(ofifo_rst));\n FDRE \\entry_cnt_reg[2] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1_n_0 ),\n .D(\\entry_cnt[2]_i_1_n_0 ),\n .Q(Q[0]),\n .R(ofifo_rst));\n FDRE \\entry_cnt_reg[3] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1_n_0 ),\n .D(\\entry_cnt[3]_i_1_n_0 ),\n .Q(Q[1]),\n .R(ofifo_rst));\n FDRE \\entry_cnt_reg[4] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1_n_0 ),\n .D(\\entry_cnt[4]_i_2_n_0 ),\n .Q(Q[2]),\n .R(ofifo_rst));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_0_5\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[1:0]),\n .DIB(phy_dout[3:2]),\n .DIC(phy_dout[5:4]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [1:0]),\n .DOB(\\my_empty_reg[7]_1 [3:2]),\n .DOC(\\my_empty_reg[7]_1 [5:4]),\n .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n LUT4 #(\n .INIT(16'h082A)) \n mem_reg_0_15_0_5_i_1__0\n (.I0(mux_wrdata_en),\n .I1(ofifo_rst_reg),\n .I2(\\my_full_reg_n_0_[4] ),\n .I3(\\my_empty_reg[1]_0 ),\n .O(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_12_17\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[13:12]),\n .DIB(phy_dout[15:14]),\n .DIC(phy_dout[17:16]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [13:12]),\n .DOB(\\my_empty_reg[7]_1 [15:14]),\n .DOC(\\my_empty_reg[7]_1 [17:16]),\n .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_18_23\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[19:18]),\n .DIB(phy_dout[21:20]),\n .DIC(phy_dout[23:22]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [19:18]),\n .DOB(\\my_empty_reg[7]_1 [21:20]),\n .DOC(\\my_empty_reg[7]_1 [23:22]),\n .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_24_29\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[25:24]),\n .DIB(phy_dout[27:26]),\n .DIC(phy_dout[29:28]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [25:24]),\n .DOB(\\my_empty_reg[7]_1 [27:26]),\n .DOC(\\my_empty_reg[7]_1 [29:28]),\n .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_30_35\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[31:30]),\n .DIB(phy_dout[33:32]),\n .DIC(phy_dout[35:34]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [31:30]),\n .DOB(\\my_empty_reg[7]_1 [33:32]),\n .DOC(\\my_empty_reg[7]_1 [35:34]),\n .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_36_41\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[37:36]),\n .DIB(phy_dout[39:38]),\n .DIC(phy_dout[41:40]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [37:36]),\n .DOB(\\my_empty_reg[7]_1 [39:38]),\n .DOC(\\my_empty_reg[7]_1 [41:40]),\n .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_42_47\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[43:42]),\n .DIB(phy_dout[45:44]),\n .DIC(phy_dout[47:46]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [43:42]),\n .DOB(\\my_empty_reg[7]_1 [45:44]),\n .DOC(\\my_empty_reg[7]_1 [47:46]),\n .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_48_53\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[49:48]),\n .DIB(phy_dout[51:50]),\n .DIC(phy_dout[53:52]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [49:48]),\n .DOB(\\my_empty_reg[7]_1 [51:50]),\n .DOC(\\my_empty_reg[7]_1 [53:52]),\n .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_54_59\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[55:54]),\n .DIB(phy_dout[57:56]),\n .DIC(phy_dout[59:58]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [55:54]),\n .DOB(\\my_empty_reg[7]_1 [57:56]),\n .DOC(\\my_empty_reg[7]_1 [59:58]),\n .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_60_65\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[61:60]),\n .DIB(phy_dout[63:62]),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [61:60]),\n .DOB(\\my_empty_reg[7]_1 [63:62]),\n .DOC({mem_reg_0_15_60_65_n_4,mem_reg_0_15_60_65_n_5}),\n .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_66_71\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA({1'b0,1'b0}),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_15_66_71_n_0,mem_reg_0_15_66_71_n_1}),\n .DOB({mem_reg_0_15_66_71_n_2,mem_reg_0_15_66_71_n_3}),\n .DOC({mem_reg_0_15_66_71_n_4,mem_reg_0_15_66_71_n_5}),\n .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_6_11\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[7:6]),\n .DIB(phy_dout[9:8]),\n .DIC(phy_dout[11:10]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [7:6]),\n .DOB(\\my_empty_reg[7]_1 [9:8]),\n .DOC(\\my_empty_reg[7]_1 [11:10]),\n .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_72_77\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[65:64]),\n .DIB(phy_dout[67:66]),\n .DIC(phy_dout[69:68]),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_15_72_77_n_0,mem_reg_0_15_72_77_n_1}),\n .DOB({mem_reg_0_15_72_77_n_2,mem_reg_0_15_72_77_n_3}),\n .DOC({mem_reg_0_15_72_77_n_4,mem_reg_0_15_72_77_n_5}),\n .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_78_79\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[71:70]),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_15_78_79_n_0,mem_reg_0_15_78_79_n_1}),\n .DOB(NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED[1:0]),\n .DOC(NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED[1:0]),\n .DOD(NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n LUT6 #(\n .INIT(64'hFFFFFFFFF071F070)) \n \\my_empty[1]_i_1__0 \n (.I0(mux_wrdata_en),\n .I1(ofifo_rst_reg),\n .I2(\\my_empty_reg[1]_0 ),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(my_empty0),\n .I5(ofifo_rst),\n .O(\\my_empty[1]_i_1__0_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFF071F070)) \n \\my_empty[7]_i_1__0 \n (.I0(mux_wrdata_en),\n .I1(ofifo_rst_reg),\n .I2(\\my_empty_reg_n_0_[7] ),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(my_empty0),\n .I5(ofifo_rst),\n .O(\\my_empty[7]_i_1__0_n_0 ));\n LUT5 #(\n .INIT(32'h4A400D08)) \n \\my_empty[7]_i_2__0 \n (.I0(wr_ptr_timing[2]),\n .I1(\\my_empty[7]_i_3__0_n_0 ),\n .I2(wr_ptr_timing[3]),\n .I3(\\my_empty[7]_i_4__0_n_0 ),\n .I4(\\rd_ptr_reg_n_0_[2] ),\n .O(my_empty0));\n (* SOFT_HLUTNM = \"soft_lutpair771\" *) \n LUT5 #(\n .INIT(32'h00000040)) \n \\my_empty[7]_i_3__0 \n (.I0(wr_ptr_timing[1]),\n .I1(\\rd_ptr_reg_n_0_[0] ),\n .I2(\\rd_ptr_reg_n_0_[1] ),\n .I3(\\rd_ptr_reg_n_0_[3] ),\n .I4(wr_ptr_timing[0]),\n .O(\\my_empty[7]_i_3__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair771\" *) \n LUT5 #(\n .INIT(32'h84210842)) \n \\my_empty[7]_i_4__0 \n (.I0(wr_ptr_timing[0]),\n .I1(wr_ptr_timing[1]),\n .I2(\\rd_ptr_reg_n_0_[0] ),\n .I3(\\rd_ptr_reg_n_0_[1] ),\n .I4(\\rd_ptr_reg_n_0_[3] ),\n .O(\\my_empty[7]_i_4__0_n_0 ));\n (* syn_maxfan = \"3\" *) \n FDRE \\my_empty_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_empty[1]_i_1__0_n_0 ),\n .Q(\\my_empty_reg[1]_0 ),\n .R(1'b0));\n (* syn_maxfan = \"3\" *) \n FDRE \\my_empty_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_empty[7]_i_1__0_n_0 ),\n .Q(\\my_empty_reg_n_0_[7] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000FF00FC80)) \n \\my_full[4]_i_1 \n (.I0(my_full0),\n .I1(mux_wrdata_en),\n .I2(ofifo_rst_reg),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(\\my_empty_reg_n_0_[7] ),\n .I5(ofifo_rst),\n .O(\\my_full[4]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h4A400D08)) \n \\my_full[4]_i_2__0 \n (.I0(rd_ptr_timing[2]),\n .I1(\\my_full[4]_i_3__0_n_0 ),\n .I2(rd_ptr_timing[3]),\n .I3(\\my_full[4]_i_4__0_n_0 ),\n .I4(wr_ptr[2]),\n .O(my_full0));\n (* SOFT_HLUTNM = \"soft_lutpair770\" *) \n LUT5 #(\n .INIT(32'h00000040)) \n \\my_full[4]_i_3__0 \n (.I0(rd_ptr_timing[1]),\n .I1(wr_ptr[0]),\n .I2(wr_ptr[1]),\n .I3(wr_ptr[3]),\n .I4(rd_ptr_timing[0]),\n .O(\\my_full[4]_i_3__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair770\" *) \n LUT5 #(\n .INIT(32'h84210842)) \n \\my_full[4]_i_4__0 \n (.I0(rd_ptr_timing[0]),\n .I1(rd_ptr_timing[1]),\n .I2(wr_ptr[0]),\n .I3(wr_ptr[1]),\n .I4(wr_ptr[3]),\n .O(\\my_full[4]_i_4__0_n_0 ));\n (* syn_maxfan = \"3\" *) \n FDRE \\my_full_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_full[4]_i_1_n_0 ),\n .Q(\\my_full_reg_n_0_[4] ),\n .R(1'b0));\n LUT3 #(\n .INIT(8'h0D)) \n out_fifo_i_1__3\n (.I0(\\my_empty_reg[1]_0 ),\n .I1(mux_wrdata_en),\n .I2(ofifo_rst_reg),\n .O(\\my_empty_reg[7]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair778\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_66__0\n (.I0(mem_reg_0_15_66_71_n_4),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D8[7]));\n (* SOFT_HLUTNM = \"soft_lutpair775\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_67__0\n (.I0(mem_reg_0_15_66_71_n_5),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D8[6]));\n (* SOFT_HLUTNM = \"soft_lutpair777\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_68__1\n (.I0(mem_reg_0_15_66_71_n_2),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D8[5]));\n (* SOFT_HLUTNM = \"soft_lutpair773\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_69__1\n (.I0(mem_reg_0_15_66_71_n_3),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D8[4]));\n (* SOFT_HLUTNM = \"soft_lutpair781\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_70\n (.I0(mem_reg_0_15_66_71_n_0),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D8[3]));\n (* SOFT_HLUTNM = \"soft_lutpair774\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_71\n (.I0(mem_reg_0_15_66_71_n_1),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D8[2]));\n (* SOFT_HLUTNM = \"soft_lutpair782\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_72\n (.I0(mem_reg_0_15_60_65_n_4),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D8[1]));\n (* SOFT_HLUTNM = \"soft_lutpair776\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_73\n (.I0(mem_reg_0_15_60_65_n_5),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D8[0]));\n (* SOFT_HLUTNM = \"soft_lutpair775\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_74__3\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[287] [7]),\n .I2(mem_reg_0_15_78_79_n_0),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[7]));\n (* SOFT_HLUTNM = \"soft_lutpair778\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_75__3\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[287] [6]),\n .I2(mem_reg_0_15_78_79_n_1),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[6]));\n (* SOFT_HLUTNM = \"soft_lutpair776\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_76__3\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[287] [5]),\n .I2(mem_reg_0_15_72_77_n_4),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[5]));\n (* SOFT_HLUTNM = \"soft_lutpair774\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_77__3\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[287] [4]),\n .I2(mem_reg_0_15_72_77_n_5),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[4]));\n (* SOFT_HLUTNM = \"soft_lutpair777\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_78__3\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[287] [3]),\n .I2(mem_reg_0_15_72_77_n_2),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[3]));\n (* SOFT_HLUTNM = \"soft_lutpair781\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_79__2\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[287] [2]),\n .I2(mem_reg_0_15_72_77_n_3),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[2]));\n (* SOFT_HLUTNM = \"soft_lutpair773\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_80__2\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[287] [1]),\n .I2(mem_reg_0_15_72_77_n_0),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[1]));\n (* SOFT_HLUTNM = \"soft_lutpair782\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_81__2\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[287] [0]),\n .I2(mem_reg_0_15_72_77_n_1),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[0]));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[0] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__0_n_0 ),\n .D(nxt_rd_ptr[0]),\n .Q(\\rd_ptr_reg_n_0_[0] ),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[1] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__0_n_0 ),\n .D(nxt_rd_ptr[1]),\n .Q(\\rd_ptr_reg_n_0_[1] ),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[2] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__0_n_0 ),\n .D(nxt_rd_ptr[2]),\n .Q(\\rd_ptr_reg_n_0_[2] ),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[3] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__0_n_0 ),\n .D(nxt_rd_ptr[3]),\n .Q(\\rd_ptr_reg_n_0_[3] ),\n .R(ofifo_rst));\n (* SOFT_HLUTNM = \"soft_lutpair783\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\rd_ptr_timing[0]_i_1__1 \n (.I0(\\rd_ptr_reg_n_0_[3] ),\n .I1(\\rd_ptr_reg_n_0_[0] ),\n .O(nxt_rd_ptr[0]));\n (* SOFT_HLUTNM = \"soft_lutpair783\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\rd_ptr_timing[1]_i_1__0 \n (.I0(\\rd_ptr_reg_n_0_[3] ),\n .I1(\\rd_ptr_reg_n_0_[0] ),\n .I2(\\rd_ptr_reg_n_0_[1] ),\n .O(nxt_rd_ptr[1]));\n (* SOFT_HLUTNM = \"soft_lutpair780\" *) \n LUT4 #(\n .INIT(16'hAA6A)) \n \\rd_ptr_timing[2]_i_1__0 \n (.I0(\\rd_ptr_reg_n_0_[2] ),\n .I1(\\rd_ptr_reg_n_0_[0] ),\n .I2(\\rd_ptr_reg_n_0_[1] ),\n .I3(\\rd_ptr_reg_n_0_[3] ),\n .O(nxt_rd_ptr[2]));\n LUT2 #(\n .INIT(4'h1)) \n \\rd_ptr_timing[3]_i_1__0 \n (.I0(\\my_empty_reg_n_0_[7] ),\n .I1(ofifo_rst_reg),\n .O(\\rd_ptr_timing[3]_i_1__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair780\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\rd_ptr_timing[3]_i_2__0 \n (.I0(\\rd_ptr_reg_n_0_[3] ),\n .I1(\\rd_ptr_reg_n_0_[1] ),\n .I2(\\rd_ptr_reg_n_0_[0] ),\n .I3(\\rd_ptr_reg_n_0_[2] ),\n .O(nxt_rd_ptr[3]));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[0] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__0_n_0 ),\n .D(nxt_rd_ptr[0]),\n .Q(rd_ptr_timing[0]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[1] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__0_n_0 ),\n .D(nxt_rd_ptr[1]),\n .Q(rd_ptr_timing[1]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[2] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__0_n_0 ),\n .D(nxt_rd_ptr[2]),\n .Q(rd_ptr_timing[2]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[3] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__0_n_0 ),\n .D(nxt_rd_ptr[3]),\n .Q(rd_ptr_timing[3]),\n .R(ofifo_rst));\n (* SOFT_HLUTNM = \"soft_lutpair784\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\wr_ptr[0]_i_1__3 \n (.I0(wr_ptr[3]),\n .I1(wr_ptr[0]),\n .O(nxt_wr_ptr[0]));\n (* SOFT_HLUTNM = \"soft_lutpair784\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\wr_ptr[1]_i_1__3 \n (.I0(wr_ptr[3]),\n .I1(wr_ptr[0]),\n .I2(wr_ptr[1]),\n .O(nxt_wr_ptr[1]));\n (* SOFT_HLUTNM = \"soft_lutpair779\" *) \n LUT4 #(\n .INIT(16'hAA6A)) \n \\wr_ptr[2]_i_1__2 \n (.I0(wr_ptr[2]),\n .I1(wr_ptr[0]),\n .I2(wr_ptr[1]),\n .I3(wr_ptr[3]),\n .O(nxt_wr_ptr[2]));\n LUT4 #(\n .INIT(16'h082A)) \n \\wr_ptr[3]_i_1__2 \n (.I0(mux_wrdata_en),\n .I1(ofifo_rst_reg),\n .I2(\\my_full_reg_n_0_[4] ),\n .I3(\\my_empty_reg_n_0_[7] ),\n .O(wr_ptr0));\n (* SOFT_HLUTNM = \"soft_lutpair779\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\wr_ptr[3]_i_2 \n (.I0(wr_ptr[3]),\n .I1(wr_ptr[1]),\n .I2(wr_ptr[0]),\n .I3(wr_ptr[2]),\n .O(nxt_wr_ptr[3]));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[0] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[0]),\n .Q(wr_ptr[0]),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[1] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[1]),\n .Q(wr_ptr[1]),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[2] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[2]),\n .Q(wr_ptr[2]),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[3] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[3]),\n .Q(wr_ptr[3]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[0] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[0]),\n .Q(wr_ptr_timing[0]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[1] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[1]),\n .Q(wr_ptr_timing[1]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[2] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[2]),\n .Q(wr_ptr_timing[2]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[3] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[3]),\n .Q(wr_ptr_timing[3]),\n .R(ofifo_rst));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_of_pre_fifo\" *) \nmodule ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized3\n (\\my_empty_reg[7]_0 ,\n \\my_empty_reg[1]_0 ,\n D0,\n D9,\n \\my_empty_reg[7]_1 ,\n Q,\n ofifo_rst,\n CLK,\n ofifo_rst_reg,\n mux_wrdata_en,\n init_calib_complete_reg_rep,\n \\write_buffer.wr_buf_out_data_reg[286] ,\n phy_dout);\n output \\my_empty_reg[7]_0 ;\n output \\my_empty_reg[1]_0 ;\n output [7:0]D0;\n output [7:0]D9;\n output [63:0]\\my_empty_reg[7]_1 ;\n output [2:0]Q;\n input ofifo_rst;\n input CLK;\n input ofifo_rst_reg;\n input mux_wrdata_en;\n input init_calib_complete_reg_rep;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[286] ;\n input [71:0]phy_dout;\n\n wire CLK;\n wire [7:0]D0;\n wire [7:0]D9;\n wire [2:0]Q;\n wire \\entry_cnt[0]_i_1__0_n_0 ;\n wire \\entry_cnt[1]_i_1__0_n_0 ;\n wire \\entry_cnt[2]_i_1__0_n_0 ;\n wire \\entry_cnt[3]_i_1__0_n_0 ;\n wire \\entry_cnt[4]_i_1__0_n_0 ;\n wire \\entry_cnt[4]_i_2__0_n_0 ;\n wire \\entry_cnt[4]_i_3__0_n_0 ;\n wire \\entry_cnt_reg_n_0_[0] ;\n wire \\entry_cnt_reg_n_0_[1] ;\n wire init_calib_complete_reg_rep;\n wire mem_reg_0_15_0_5_n_0;\n wire mem_reg_0_15_0_5_n_1;\n wire mem_reg_0_15_0_5_n_2;\n wire mem_reg_0_15_0_5_n_3;\n wire mem_reg_0_15_0_5_n_4;\n wire mem_reg_0_15_0_5_n_5;\n wire mem_reg_0_15_6_11_n_0;\n wire mem_reg_0_15_6_11_n_1;\n wire mem_reg_0_15_72_77_n_0;\n wire mem_reg_0_15_72_77_n_1;\n wire mem_reg_0_15_72_77_n_2;\n wire mem_reg_0_15_72_77_n_3;\n wire mem_reg_0_15_72_77_n_4;\n wire mem_reg_0_15_72_77_n_5;\n wire mem_reg_0_15_78_79_n_0;\n wire mem_reg_0_15_78_79_n_1;\n wire mux_wrdata_en;\n wire my_empty0;\n wire \\my_empty[1]_i_1__1_n_0 ;\n wire \\my_empty[7]_i_1__1_n_0 ;\n wire \\my_empty[7]_i_3__1_n_0 ;\n wire \\my_empty[7]_i_4__1_n_0 ;\n wire \\my_empty_reg[1]_0 ;\n wire \\my_empty_reg[7]_0 ;\n wire [63:0]\\my_empty_reg[7]_1 ;\n wire \\my_empty_reg_n_0_[7] ;\n wire my_full0;\n wire \\my_full[4]_i_1__0_n_0 ;\n wire \\my_full[4]_i_3__1_n_0 ;\n wire \\my_full[4]_i_4__1_n_0 ;\n wire \\my_full_reg_n_0_[4] ;\n wire [3:0]nxt_rd_ptr;\n wire [3:0]nxt_wr_ptr;\n wire ofifo_rst;\n wire ofifo_rst_reg;\n wire [71:0]phy_dout;\n wire \\rd_ptr_reg_n_0_[0] ;\n wire \\rd_ptr_reg_n_0_[1] ;\n wire \\rd_ptr_reg_n_0_[2] ;\n wire \\rd_ptr_reg_n_0_[3] ;\n wire [3:0]rd_ptr_timing;\n wire \\rd_ptr_timing[3]_i_1__1_n_0 ;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) wire wr_en;\n wire [3:0]wr_ptr;\n wire wr_ptr0;\n wire [3:0]wr_ptr_timing;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[286] ;\n wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED;\n\n (* SOFT_HLUTNM = \"soft_lutpair823\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\entry_cnt[0]_i_1__0 \n (.I0(\\entry_cnt_reg_n_0_[0] ),\n .O(\\entry_cnt[0]_i_1__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair821\" *) \n LUT5 #(\n .INIT(32'hAA6A5595)) \n \\entry_cnt[1]_i_1__0 \n (.I0(\\entry_cnt_reg_n_0_[0] ),\n .I1(ofifo_rst_reg),\n .I2(mux_wrdata_en),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(\\entry_cnt_reg_n_0_[1] ),\n .O(\\entry_cnt[1]_i_1__0_n_0 ));\n LUT6 #(\n .INIT(64'hFF7F0080AAEA5515)) \n \\entry_cnt[2]_i_1__0 \n (.I0(\\entry_cnt_reg_n_0_[0] ),\n .I1(ofifo_rst_reg),\n .I2(mux_wrdata_en),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(Q[0]),\n .I5(\\entry_cnt_reg_n_0_[1] ),\n .O(\\entry_cnt[2]_i_1__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair823\" *) \n LUT5 #(\n .INIT(32'h7F80FE01)) \n \\entry_cnt[3]_i_1__0 \n (.I0(\\entry_cnt[4]_i_3__0_n_0 ),\n .I1(\\entry_cnt_reg_n_0_[0] ),\n .I2(\\entry_cnt_reg_n_0_[1] ),\n .I3(Q[1]),\n .I4(Q[0]),\n .O(\\entry_cnt[3]_i_1__0_n_0 ));\n LUT4 #(\n .INIT(16'h5003)) \n \\entry_cnt[4]_i_1__0 \n (.I0(\\my_full_reg_n_0_[4] ),\n .I1(\\my_empty_reg_n_0_[7] ),\n .I2(mux_wrdata_en),\n .I3(ofifo_rst_reg),\n .O(\\entry_cnt[4]_i_1__0_n_0 ));\n LUT6 #(\n .INIT(64'h7FFF8000FFFE0001)) \n \\entry_cnt[4]_i_2__0 \n (.I0(\\entry_cnt_reg_n_0_[1] ),\n .I1(\\entry_cnt_reg_n_0_[0] ),\n .I2(\\entry_cnt[4]_i_3__0_n_0 ),\n .I3(Q[0]),\n .I4(Q[2]),\n .I5(Q[1]),\n .O(\\entry_cnt[4]_i_2__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair821\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\entry_cnt[4]_i_3__0 \n (.I0(ofifo_rst_reg),\n .I1(mux_wrdata_en),\n .I2(\\my_full_reg_n_0_[4] ),\n .O(\\entry_cnt[4]_i_3__0_n_0 ));\n FDRE \\entry_cnt_reg[0] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1__0_n_0 ),\n .D(\\entry_cnt[0]_i_1__0_n_0 ),\n .Q(\\entry_cnt_reg_n_0_[0] ),\n .R(ofifo_rst));\n FDRE \\entry_cnt_reg[1] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1__0_n_0 ),\n .D(\\entry_cnt[1]_i_1__0_n_0 ),\n .Q(\\entry_cnt_reg_n_0_[1] ),\n .R(ofifo_rst));\n FDRE \\entry_cnt_reg[2] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1__0_n_0 ),\n .D(\\entry_cnt[2]_i_1__0_n_0 ),\n .Q(Q[0]),\n .R(ofifo_rst));\n FDRE \\entry_cnt_reg[3] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1__0_n_0 ),\n .D(\\entry_cnt[3]_i_1__0_n_0 ),\n .Q(Q[1]),\n .R(ofifo_rst));\n FDRE \\entry_cnt_reg[4] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1__0_n_0 ),\n .D(\\entry_cnt[4]_i_2__0_n_0 ),\n .Q(Q[2]),\n .R(ofifo_rst));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_0_5\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA({1'b0,1'b0}),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_15_0_5_n_0,mem_reg_0_15_0_5_n_1}),\n .DOB({mem_reg_0_15_0_5_n_2,mem_reg_0_15_0_5_n_3}),\n .DOC({mem_reg_0_15_0_5_n_4,mem_reg_0_15_0_5_n_5}),\n .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n LUT4 #(\n .INIT(16'h082A)) \n mem_reg_0_15_0_5_i_1__1\n (.I0(mux_wrdata_en),\n .I1(ofifo_rst_reg),\n .I2(\\my_full_reg_n_0_[4] ),\n .I3(\\my_empty_reg[1]_0 ),\n .O(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_12_17\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[5:4]),\n .DIB(phy_dout[7:6]),\n .DIC(phy_dout[9:8]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [5:4]),\n .DOB(\\my_empty_reg[7]_1 [7:6]),\n .DOC(\\my_empty_reg[7]_1 [9:8]),\n .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_18_23\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[11:10]),\n .DIB(phy_dout[13:12]),\n .DIC(phy_dout[15:14]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [11:10]),\n .DOB(\\my_empty_reg[7]_1 [13:12]),\n .DOC(\\my_empty_reg[7]_1 [15:14]),\n .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_24_29\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[17:16]),\n .DIB(phy_dout[19:18]),\n .DIC(phy_dout[21:20]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [17:16]),\n .DOB(\\my_empty_reg[7]_1 [19:18]),\n .DOC(\\my_empty_reg[7]_1 [21:20]),\n .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_30_35\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[23:22]),\n .DIB(phy_dout[25:24]),\n .DIC(phy_dout[27:26]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [23:22]),\n .DOB(\\my_empty_reg[7]_1 [25:24]),\n .DOC(\\my_empty_reg[7]_1 [27:26]),\n .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_36_41\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[29:28]),\n .DIB(phy_dout[31:30]),\n .DIC(phy_dout[33:32]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [29:28]),\n .DOB(\\my_empty_reg[7]_1 [31:30]),\n .DOC(\\my_empty_reg[7]_1 [33:32]),\n .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_42_47\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[35:34]),\n .DIB(phy_dout[37:36]),\n .DIC(phy_dout[39:38]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [35:34]),\n .DOB(\\my_empty_reg[7]_1 [37:36]),\n .DOC(\\my_empty_reg[7]_1 [39:38]),\n .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_48_53\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[41:40]),\n .DIB(phy_dout[43:42]),\n .DIC(phy_dout[45:44]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [41:40]),\n .DOB(\\my_empty_reg[7]_1 [43:42]),\n .DOC(\\my_empty_reg[7]_1 [45:44]),\n .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_54_59\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[47:46]),\n .DIB(phy_dout[49:48]),\n .DIC(phy_dout[51:50]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [47:46]),\n .DOB(\\my_empty_reg[7]_1 [49:48]),\n .DOC(\\my_empty_reg[7]_1 [51:50]),\n .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_60_65\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[53:52]),\n .DIB(phy_dout[55:54]),\n .DIC(phy_dout[57:56]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [53:52]),\n .DOB(\\my_empty_reg[7]_1 [55:54]),\n .DOC(\\my_empty_reg[7]_1 [57:56]),\n .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_66_71\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[59:58]),\n .DIB(phy_dout[61:60]),\n .DIC(phy_dout[63:62]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [59:58]),\n .DOB(\\my_empty_reg[7]_1 [61:60]),\n .DOC(\\my_empty_reg[7]_1 [63:62]),\n .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_6_11\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA({1'b0,1'b0}),\n .DIB(phy_dout[1:0]),\n .DIC(phy_dout[3:2]),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_15_6_11_n_0,mem_reg_0_15_6_11_n_1}),\n .DOB(\\my_empty_reg[7]_1 [1:0]),\n .DOC(\\my_empty_reg[7]_1 [3:2]),\n .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_72_77\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[65:64]),\n .DIB(phy_dout[67:66]),\n .DIC(phy_dout[69:68]),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_15_72_77_n_0,mem_reg_0_15_72_77_n_1}),\n .DOB({mem_reg_0_15_72_77_n_2,mem_reg_0_15_72_77_n_3}),\n .DOC({mem_reg_0_15_72_77_n_4,mem_reg_0_15_72_77_n_5}),\n .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_78_79\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[71:70]),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_15_78_79_n_0,mem_reg_0_15_78_79_n_1}),\n .DOB(NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED[1:0]),\n .DOC(NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED[1:0]),\n .DOD(NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n LUT6 #(\n .INIT(64'hFFFFFFFFF071F070)) \n \\my_empty[1]_i_1__1 \n (.I0(mux_wrdata_en),\n .I1(ofifo_rst_reg),\n .I2(\\my_empty_reg[1]_0 ),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(my_empty0),\n .I5(ofifo_rst),\n .O(\\my_empty[1]_i_1__1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFF071F070)) \n \\my_empty[7]_i_1__1 \n (.I0(mux_wrdata_en),\n .I1(ofifo_rst_reg),\n .I2(\\my_empty_reg_n_0_[7] ),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(my_empty0),\n .I5(ofifo_rst),\n .O(\\my_empty[7]_i_1__1_n_0 ));\n LUT5 #(\n .INIT(32'h4A400D08)) \n \\my_empty[7]_i_2__1 \n (.I0(wr_ptr_timing[2]),\n .I1(\\my_empty[7]_i_3__1_n_0 ),\n .I2(wr_ptr_timing[3]),\n .I3(\\my_empty[7]_i_4__1_n_0 ),\n .I4(\\rd_ptr_reg_n_0_[2] ),\n .O(my_empty0));\n (* SOFT_HLUTNM = \"soft_lutpair824\" *) \n LUT5 #(\n .INIT(32'h00000040)) \n \\my_empty[7]_i_3__1 \n (.I0(wr_ptr_timing[1]),\n .I1(\\rd_ptr_reg_n_0_[0] ),\n .I2(\\rd_ptr_reg_n_0_[1] ),\n .I3(\\rd_ptr_reg_n_0_[3] ),\n .I4(wr_ptr_timing[0]),\n .O(\\my_empty[7]_i_3__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair824\" *) \n LUT5 #(\n .INIT(32'h84210842)) \n \\my_empty[7]_i_4__1 \n (.I0(wr_ptr_timing[0]),\n .I1(wr_ptr_timing[1]),\n .I2(\\rd_ptr_reg_n_0_[0] ),\n .I3(\\rd_ptr_reg_n_0_[1] ),\n .I4(\\rd_ptr_reg_n_0_[3] ),\n .O(\\my_empty[7]_i_4__1_n_0 ));\n (* syn_maxfan = \"3\" *) \n FDRE \\my_empty_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_empty[1]_i_1__1_n_0 ),\n .Q(\\my_empty_reg[1]_0 ),\n .R(1'b0));\n (* syn_maxfan = \"3\" *) \n FDRE \\my_empty_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_empty[7]_i_1__1_n_0 ),\n .Q(\\my_empty_reg_n_0_[7] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000FF00FC80)) \n \\my_full[4]_i_1__0 \n (.I0(my_full0),\n .I1(mux_wrdata_en),\n .I2(ofifo_rst_reg),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(\\my_empty_reg_n_0_[7] ),\n .I5(ofifo_rst),\n .O(\\my_full[4]_i_1__0_n_0 ));\n LUT5 #(\n .INIT(32'h4A400D08)) \n \\my_full[4]_i_2__1 \n (.I0(rd_ptr_timing[2]),\n .I1(\\my_full[4]_i_3__1_n_0 ),\n .I2(rd_ptr_timing[3]),\n .I3(\\my_full[4]_i_4__1_n_0 ),\n .I4(wr_ptr[2]),\n .O(my_full0));\n (* SOFT_HLUTNM = \"soft_lutpair822\" *) \n LUT5 #(\n .INIT(32'h00000040)) \n \\my_full[4]_i_3__1 \n (.I0(rd_ptr_timing[1]),\n .I1(wr_ptr[0]),\n .I2(wr_ptr[1]),\n .I3(wr_ptr[3]),\n .I4(rd_ptr_timing[0]),\n .O(\\my_full[4]_i_3__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair822\" *) \n LUT5 #(\n .INIT(32'h84210842)) \n \\my_full[4]_i_4__1 \n (.I0(rd_ptr_timing[0]),\n .I1(rd_ptr_timing[1]),\n .I2(wr_ptr[0]),\n .I3(wr_ptr[1]),\n .I4(wr_ptr[3]),\n .O(\\my_full[4]_i_4__1_n_0 ));\n (* syn_maxfan = \"3\" *) \n FDRE \\my_full_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_full[4]_i_1__0_n_0 ),\n .Q(\\my_full_reg_n_0_[4] ),\n .R(1'b0));\n LUT3 #(\n .INIT(8'h0D)) \n out_fifo_i_1__4\n (.I0(\\my_empty_reg[1]_0 ),\n .I1(mux_wrdata_en),\n .I2(ofifo_rst_reg),\n .O(\\my_empty_reg[7]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair830\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_2__3\n (.I0(mem_reg_0_15_6_11_n_0),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[7]));\n (* SOFT_HLUTNM = \"soft_lutpair826\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_3__3\n (.I0(mem_reg_0_15_6_11_n_1),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[6]));\n (* SOFT_HLUTNM = \"soft_lutpair831\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_4__3\n (.I0(mem_reg_0_15_0_5_n_4),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[5]));\n (* SOFT_HLUTNM = \"soft_lutpair828\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_5__3\n (.I0(mem_reg_0_15_0_5_n_5),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[4]));\n (* SOFT_HLUTNM = \"soft_lutpair829\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_6__3\n (.I0(mem_reg_0_15_0_5_n_2),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair827\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_74__2\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[286] [7]),\n .I2(mem_reg_0_15_78_79_n_0),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[7]));\n (* SOFT_HLUTNM = \"soft_lutpair830\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_75__2\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[286] [6]),\n .I2(mem_reg_0_15_78_79_n_1),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[6]));\n (* SOFT_HLUTNM = \"soft_lutpair828\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_76__2\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[286] [5]),\n .I2(mem_reg_0_15_72_77_n_4),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[5]));\n (* SOFT_HLUTNM = \"soft_lutpair829\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_77__2\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[286] [4]),\n .I2(mem_reg_0_15_72_77_n_5),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[4]));\n (* SOFT_HLUTNM = \"soft_lutpair826\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_78__2\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[286] [3]),\n .I2(mem_reg_0_15_72_77_n_2),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[3]));\n (* SOFT_HLUTNM = \"soft_lutpair832\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_79__1\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[286] [2]),\n .I2(mem_reg_0_15_72_77_n_3),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[2]));\n (* SOFT_HLUTNM = \"soft_lutpair825\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_7__2\n (.I0(mem_reg_0_15_0_5_n_3),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair825\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_80__1\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[286] [1]),\n .I2(mem_reg_0_15_72_77_n_0),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[1]));\n (* SOFT_HLUTNM = \"soft_lutpair831\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_81__1\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[286] [0]),\n .I2(mem_reg_0_15_72_77_n_1),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[0]));\n (* SOFT_HLUTNM = \"soft_lutpair832\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_8__2\n (.I0(mem_reg_0_15_0_5_n_0),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair827\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_9__2\n (.I0(mem_reg_0_15_0_5_n_1),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[0]));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[0] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[0]),\n .Q(\\rd_ptr_reg_n_0_[0] ),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[1] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[1]),\n .Q(\\rd_ptr_reg_n_0_[1] ),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[2] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[2]),\n .Q(\\rd_ptr_reg_n_0_[2] ),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[3] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[3]),\n .Q(\\rd_ptr_reg_n_0_[3] ),\n .R(ofifo_rst));\n (* SOFT_HLUTNM = \"soft_lutpair836\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\rd_ptr_timing[0]_i_1__3 \n (.I0(\\rd_ptr_reg_n_0_[3] ),\n .I1(\\rd_ptr_reg_n_0_[0] ),\n .O(nxt_rd_ptr[0]));\n (* SOFT_HLUTNM = \"soft_lutpair836\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\rd_ptr_timing[1]_i_1__1 \n (.I0(\\rd_ptr_reg_n_0_[3] ),\n .I1(\\rd_ptr_reg_n_0_[0] ),\n .I2(\\rd_ptr_reg_n_0_[1] ),\n .O(nxt_rd_ptr[1]));\n (* SOFT_HLUTNM = \"soft_lutpair834\" *) \n LUT4 #(\n .INIT(16'hAA6A)) \n \\rd_ptr_timing[2]_i_1__1 \n (.I0(\\rd_ptr_reg_n_0_[2] ),\n .I1(\\rd_ptr_reg_n_0_[0] ),\n .I2(\\rd_ptr_reg_n_0_[1] ),\n .I3(\\rd_ptr_reg_n_0_[3] ),\n .O(nxt_rd_ptr[2]));\n LUT2 #(\n .INIT(4'h1)) \n \\rd_ptr_timing[3]_i_1__1 \n (.I0(\\my_empty_reg_n_0_[7] ),\n .I1(ofifo_rst_reg),\n .O(\\rd_ptr_timing[3]_i_1__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair834\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\rd_ptr_timing[3]_i_2__1 \n (.I0(\\rd_ptr_reg_n_0_[3] ),\n .I1(\\rd_ptr_reg_n_0_[1] ),\n .I2(\\rd_ptr_reg_n_0_[0] ),\n .I3(\\rd_ptr_reg_n_0_[2] ),\n .O(nxt_rd_ptr[3]));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[0] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[0]),\n .Q(rd_ptr_timing[0]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[1] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[1]),\n .Q(rd_ptr_timing[1]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[2] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[2]),\n .Q(rd_ptr_timing[2]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[3] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[3]),\n .Q(rd_ptr_timing[3]),\n .R(ofifo_rst));\n (* SOFT_HLUTNM = \"soft_lutpair835\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\wr_ptr[0]_i_1__5 \n (.I0(wr_ptr[3]),\n .I1(wr_ptr[0]),\n .O(nxt_wr_ptr[0]));\n (* SOFT_HLUTNM = \"soft_lutpair835\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\wr_ptr[1]_i_1__5 \n (.I0(wr_ptr[3]),\n .I1(wr_ptr[0]),\n .I2(wr_ptr[1]),\n .O(nxt_wr_ptr[1]));\n (* SOFT_HLUTNM = \"soft_lutpair833\" *) \n LUT4 #(\n .INIT(16'hAA6A)) \n \\wr_ptr[2]_i_1__3 \n (.I0(wr_ptr[2]),\n .I1(wr_ptr[0]),\n .I2(wr_ptr[1]),\n .I3(wr_ptr[3]),\n .O(nxt_wr_ptr[2]));\n LUT4 #(\n .INIT(16'h082A)) \n \\wr_ptr[3]_i_1__3 \n (.I0(mux_wrdata_en),\n .I1(ofifo_rst_reg),\n .I2(\\my_full_reg_n_0_[4] ),\n .I3(\\my_empty_reg_n_0_[7] ),\n .O(wr_ptr0));\n (* SOFT_HLUTNM = \"soft_lutpair833\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\wr_ptr[3]_i_2__0 \n (.I0(wr_ptr[3]),\n .I1(wr_ptr[1]),\n .I2(wr_ptr[0]),\n .I3(wr_ptr[2]),\n .O(nxt_wr_ptr[3]));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[0] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[0]),\n .Q(wr_ptr[0]),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[1] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[1]),\n .Q(wr_ptr[1]),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[2] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[2]),\n .Q(wr_ptr[2]),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[3] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[3]),\n .Q(wr_ptr[3]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[0] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[0]),\n .Q(wr_ptr_timing[0]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[1] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[1]),\n .Q(wr_ptr_timing[1]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[2] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[2]),\n .Q(wr_ptr_timing[2]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[3] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[3]),\n .Q(wr_ptr_timing[3]),\n .R(ofifo_rst));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_of_pre_fifo\" *) \nmodule ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized4\n (\\my_empty_reg[7]_0 ,\n \\my_empty_reg[1]_0 ,\n D0,\n D9,\n \\my_empty_reg[7]_1 ,\n Q,\n ofifo_rst,\n CLK,\n ofifo_rst_reg,\n mux_wrdata_en,\n init_calib_complete_reg_rep,\n \\write_buffer.wr_buf_out_data_reg[285] ,\n phy_dout);\n output \\my_empty_reg[7]_0 ;\n output \\my_empty_reg[1]_0 ;\n output [7:0]D0;\n output [7:0]D9;\n output [63:0]\\my_empty_reg[7]_1 ;\n output [2:0]Q;\n input ofifo_rst;\n input CLK;\n input ofifo_rst_reg;\n input mux_wrdata_en;\n input init_calib_complete_reg_rep;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[285] ;\n input [71:0]phy_dout;\n\n wire CLK;\n wire [7:0]D0;\n wire [7:0]D9;\n wire [2:0]Q;\n wire \\entry_cnt[0]_i_1__1_n_0 ;\n wire \\entry_cnt[1]_i_1__1_n_0 ;\n wire \\entry_cnt[2]_i_1__1_n_0 ;\n wire \\entry_cnt[3]_i_1__1_n_0 ;\n wire \\entry_cnt[4]_i_1__1_n_0 ;\n wire \\entry_cnt[4]_i_2__1_n_0 ;\n wire \\entry_cnt[4]_i_3__1_n_0 ;\n wire \\entry_cnt_reg_n_0_[0] ;\n wire \\entry_cnt_reg_n_0_[1] ;\n wire init_calib_complete_reg_rep;\n wire mem_reg_0_15_0_5_n_0;\n wire mem_reg_0_15_0_5_n_1;\n wire mem_reg_0_15_0_5_n_2;\n wire mem_reg_0_15_0_5_n_3;\n wire mem_reg_0_15_0_5_n_4;\n wire mem_reg_0_15_0_5_n_5;\n wire mem_reg_0_15_6_11_n_0;\n wire mem_reg_0_15_6_11_n_1;\n wire mem_reg_0_15_72_77_n_0;\n wire mem_reg_0_15_72_77_n_1;\n wire mem_reg_0_15_72_77_n_2;\n wire mem_reg_0_15_72_77_n_3;\n wire mem_reg_0_15_72_77_n_4;\n wire mem_reg_0_15_72_77_n_5;\n wire mem_reg_0_15_78_79_n_0;\n wire mem_reg_0_15_78_79_n_1;\n wire mux_wrdata_en;\n wire my_empty0;\n wire \\my_empty[1]_i_1__2_n_0 ;\n wire \\my_empty[7]_i_1__2_n_0 ;\n wire \\my_empty[7]_i_3__2_n_0 ;\n wire \\my_empty[7]_i_4__2_n_0 ;\n wire \\my_empty_reg[1]_0 ;\n wire \\my_empty_reg[7]_0 ;\n wire [63:0]\\my_empty_reg[7]_1 ;\n wire \\my_empty_reg_n_0_[7] ;\n wire my_full0;\n wire \\my_full[4]_i_1__1_n_0 ;\n wire \\my_full[4]_i_3__2_n_0 ;\n wire \\my_full[4]_i_4__2_n_0 ;\n wire \\my_full_reg_n_0_[4] ;\n wire [3:0]nxt_rd_ptr;\n wire [3:0]nxt_wr_ptr;\n wire ofifo_rst;\n wire ofifo_rst_reg;\n wire [71:0]phy_dout;\n wire \\rd_ptr_reg_n_0_[0] ;\n wire \\rd_ptr_reg_n_0_[1] ;\n wire \\rd_ptr_reg_n_0_[2] ;\n wire \\rd_ptr_reg_n_0_[3] ;\n wire [3:0]rd_ptr_timing;\n wire \\rd_ptr_timing[3]_i_1__2_n_0 ;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) wire wr_en;\n wire [3:0]wr_ptr;\n wire wr_ptr0;\n wire [3:0]wr_ptr_timing;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[285] ;\n wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED;\n\n (* SOFT_HLUTNM = \"soft_lutpair874\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\entry_cnt[0]_i_1__1 \n (.I0(\\entry_cnt_reg_n_0_[0] ),\n .O(\\entry_cnt[0]_i_1__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair872\" *) \n LUT5 #(\n .INIT(32'hAA6A5595)) \n \\entry_cnt[1]_i_1__1 \n (.I0(\\entry_cnt_reg_n_0_[0] ),\n .I1(ofifo_rst_reg),\n .I2(mux_wrdata_en),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(\\entry_cnt_reg_n_0_[1] ),\n .O(\\entry_cnt[1]_i_1__1_n_0 ));\n LUT6 #(\n .INIT(64'hFF7F0080AAEA5515)) \n \\entry_cnt[2]_i_1__1 \n (.I0(\\entry_cnt_reg_n_0_[0] ),\n .I1(ofifo_rst_reg),\n .I2(mux_wrdata_en),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(Q[0]),\n .I5(\\entry_cnt_reg_n_0_[1] ),\n .O(\\entry_cnt[2]_i_1__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair874\" *) \n LUT5 #(\n .INIT(32'h7F80FE01)) \n \\entry_cnt[3]_i_1__1 \n (.I0(\\entry_cnt[4]_i_3__1_n_0 ),\n .I1(\\entry_cnt_reg_n_0_[0] ),\n .I2(\\entry_cnt_reg_n_0_[1] ),\n .I3(Q[1]),\n .I4(Q[0]),\n .O(\\entry_cnt[3]_i_1__1_n_0 ));\n LUT4 #(\n .INIT(16'h5003)) \n \\entry_cnt[4]_i_1__1 \n (.I0(\\my_full_reg_n_0_[4] ),\n .I1(\\my_empty_reg_n_0_[7] ),\n .I2(mux_wrdata_en),\n .I3(ofifo_rst_reg),\n .O(\\entry_cnt[4]_i_1__1_n_0 ));\n LUT6 #(\n .INIT(64'h7FFF8000FFFE0001)) \n \\entry_cnt[4]_i_2__1 \n (.I0(\\entry_cnt_reg_n_0_[1] ),\n .I1(\\entry_cnt_reg_n_0_[0] ),\n .I2(\\entry_cnt[4]_i_3__1_n_0 ),\n .I3(Q[0]),\n .I4(Q[2]),\n .I5(Q[1]),\n .O(\\entry_cnt[4]_i_2__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair872\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\entry_cnt[4]_i_3__1 \n (.I0(ofifo_rst_reg),\n .I1(mux_wrdata_en),\n .I2(\\my_full_reg_n_0_[4] ),\n .O(\\entry_cnt[4]_i_3__1_n_0 ));\n FDRE \\entry_cnt_reg[0] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1__1_n_0 ),\n .D(\\entry_cnt[0]_i_1__1_n_0 ),\n .Q(\\entry_cnt_reg_n_0_[0] ),\n .R(ofifo_rst));\n FDRE \\entry_cnt_reg[1] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1__1_n_0 ),\n .D(\\entry_cnt[1]_i_1__1_n_0 ),\n .Q(\\entry_cnt_reg_n_0_[1] ),\n .R(ofifo_rst));\n FDRE \\entry_cnt_reg[2] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1__1_n_0 ),\n .D(\\entry_cnt[2]_i_1__1_n_0 ),\n .Q(Q[0]),\n .R(ofifo_rst));\n FDRE \\entry_cnt_reg[3] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1__1_n_0 ),\n .D(\\entry_cnt[3]_i_1__1_n_0 ),\n .Q(Q[1]),\n .R(ofifo_rst));\n FDRE \\entry_cnt_reg[4] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1__1_n_0 ),\n .D(\\entry_cnt[4]_i_2__1_n_0 ),\n .Q(Q[2]),\n .R(ofifo_rst));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_0_5\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA({1'b0,1'b0}),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_15_0_5_n_0,mem_reg_0_15_0_5_n_1}),\n .DOB({mem_reg_0_15_0_5_n_2,mem_reg_0_15_0_5_n_3}),\n .DOC({mem_reg_0_15_0_5_n_4,mem_reg_0_15_0_5_n_5}),\n .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n LUT4 #(\n .INIT(16'h082A)) \n mem_reg_0_15_0_5_i_1__2\n (.I0(mux_wrdata_en),\n .I1(ofifo_rst_reg),\n .I2(\\my_full_reg_n_0_[4] ),\n .I3(\\my_empty_reg[1]_0 ),\n .O(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_12_17\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[5:4]),\n .DIB(phy_dout[7:6]),\n .DIC(phy_dout[9:8]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [5:4]),\n .DOB(\\my_empty_reg[7]_1 [7:6]),\n .DOC(\\my_empty_reg[7]_1 [9:8]),\n .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_18_23\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[11:10]),\n .DIB(phy_dout[13:12]),\n .DIC(phy_dout[15:14]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [11:10]),\n .DOB(\\my_empty_reg[7]_1 [13:12]),\n .DOC(\\my_empty_reg[7]_1 [15:14]),\n .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_24_29\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[17:16]),\n .DIB(phy_dout[19:18]),\n .DIC(phy_dout[21:20]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [17:16]),\n .DOB(\\my_empty_reg[7]_1 [19:18]),\n .DOC(\\my_empty_reg[7]_1 [21:20]),\n .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_30_35\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[23:22]),\n .DIB(phy_dout[25:24]),\n .DIC(phy_dout[27:26]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [23:22]),\n .DOB(\\my_empty_reg[7]_1 [25:24]),\n .DOC(\\my_empty_reg[7]_1 [27:26]),\n .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_36_41\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[29:28]),\n .DIB(phy_dout[31:30]),\n .DIC(phy_dout[33:32]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [29:28]),\n .DOB(\\my_empty_reg[7]_1 [31:30]),\n .DOC(\\my_empty_reg[7]_1 [33:32]),\n .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_42_47\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[35:34]),\n .DIB(phy_dout[37:36]),\n .DIC(phy_dout[39:38]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [35:34]),\n .DOB(\\my_empty_reg[7]_1 [37:36]),\n .DOC(\\my_empty_reg[7]_1 [39:38]),\n .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_48_53\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[41:40]),\n .DIB(phy_dout[43:42]),\n .DIC(phy_dout[45:44]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [41:40]),\n .DOB(\\my_empty_reg[7]_1 [43:42]),\n .DOC(\\my_empty_reg[7]_1 [45:44]),\n .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_54_59\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[47:46]),\n .DIB(phy_dout[49:48]),\n .DIC(phy_dout[51:50]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [47:46]),\n .DOB(\\my_empty_reg[7]_1 [49:48]),\n .DOC(\\my_empty_reg[7]_1 [51:50]),\n .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_60_65\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[53:52]),\n .DIB(phy_dout[55:54]),\n .DIC(phy_dout[57:56]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [53:52]),\n .DOB(\\my_empty_reg[7]_1 [55:54]),\n .DOC(\\my_empty_reg[7]_1 [57:56]),\n .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_66_71\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[59:58]),\n .DIB(phy_dout[61:60]),\n .DIC(phy_dout[63:62]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [59:58]),\n .DOB(\\my_empty_reg[7]_1 [61:60]),\n .DOC(\\my_empty_reg[7]_1 [63:62]),\n .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_6_11\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA({1'b0,1'b0}),\n .DIB(phy_dout[1:0]),\n .DIC(phy_dout[3:2]),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_15_6_11_n_0,mem_reg_0_15_6_11_n_1}),\n .DOB(\\my_empty_reg[7]_1 [1:0]),\n .DOC(\\my_empty_reg[7]_1 [3:2]),\n .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_72_77\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[65:64]),\n .DIB(phy_dout[67:66]),\n .DIC(phy_dout[69:68]),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_15_72_77_n_0,mem_reg_0_15_72_77_n_1}),\n .DOB({mem_reg_0_15_72_77_n_2,mem_reg_0_15_72_77_n_3}),\n .DOC({mem_reg_0_15_72_77_n_4,mem_reg_0_15_72_77_n_5}),\n .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_78_79\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[71:70]),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_15_78_79_n_0,mem_reg_0_15_78_79_n_1}),\n .DOB(NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED[1:0]),\n .DOC(NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED[1:0]),\n .DOD(NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n LUT6 #(\n .INIT(64'hFFFFFFFFF071F070)) \n \\my_empty[1]_i_1__2 \n (.I0(mux_wrdata_en),\n .I1(ofifo_rst_reg),\n .I2(\\my_empty_reg[1]_0 ),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(my_empty0),\n .I5(ofifo_rst),\n .O(\\my_empty[1]_i_1__2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFF071F070)) \n \\my_empty[7]_i_1__2 \n (.I0(mux_wrdata_en),\n .I1(ofifo_rst_reg),\n .I2(\\my_empty_reg_n_0_[7] ),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(my_empty0),\n .I5(ofifo_rst),\n .O(\\my_empty[7]_i_1__2_n_0 ));\n LUT5 #(\n .INIT(32'h4A400D08)) \n \\my_empty[7]_i_2__2 \n (.I0(wr_ptr_timing[2]),\n .I1(\\my_empty[7]_i_3__2_n_0 ),\n .I2(wr_ptr_timing[3]),\n .I3(\\my_empty[7]_i_4__2_n_0 ),\n .I4(\\rd_ptr_reg_n_0_[2] ),\n .O(my_empty0));\n (* SOFT_HLUTNM = \"soft_lutpair875\" *) \n LUT5 #(\n .INIT(32'h00000040)) \n \\my_empty[7]_i_3__2 \n (.I0(wr_ptr_timing[1]),\n .I1(\\rd_ptr_reg_n_0_[0] ),\n .I2(\\rd_ptr_reg_n_0_[1] ),\n .I3(\\rd_ptr_reg_n_0_[3] ),\n .I4(wr_ptr_timing[0]),\n .O(\\my_empty[7]_i_3__2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair875\" *) \n LUT5 #(\n .INIT(32'h84210842)) \n \\my_empty[7]_i_4__2 \n (.I0(wr_ptr_timing[0]),\n .I1(wr_ptr_timing[1]),\n .I2(\\rd_ptr_reg_n_0_[0] ),\n .I3(\\rd_ptr_reg_n_0_[1] ),\n .I4(\\rd_ptr_reg_n_0_[3] ),\n .O(\\my_empty[7]_i_4__2_n_0 ));\n (* syn_maxfan = \"3\" *) \n FDRE \\my_empty_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_empty[1]_i_1__2_n_0 ),\n .Q(\\my_empty_reg[1]_0 ),\n .R(1'b0));\n (* syn_maxfan = \"3\" *) \n FDRE \\my_empty_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_empty[7]_i_1__2_n_0 ),\n .Q(\\my_empty_reg_n_0_[7] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000FF00FC80)) \n \\my_full[4]_i_1__1 \n (.I0(my_full0),\n .I1(mux_wrdata_en),\n .I2(ofifo_rst_reg),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(\\my_empty_reg_n_0_[7] ),\n .I5(ofifo_rst),\n .O(\\my_full[4]_i_1__1_n_0 ));\n LUT5 #(\n .INIT(32'h4A400D08)) \n \\my_full[4]_i_2__2 \n (.I0(rd_ptr_timing[2]),\n .I1(\\my_full[4]_i_3__2_n_0 ),\n .I2(rd_ptr_timing[3]),\n .I3(\\my_full[4]_i_4__2_n_0 ),\n .I4(wr_ptr[2]),\n .O(my_full0));\n (* SOFT_HLUTNM = \"soft_lutpair873\" *) \n LUT5 #(\n .INIT(32'h00000040)) \n \\my_full[4]_i_3__2 \n (.I0(rd_ptr_timing[1]),\n .I1(wr_ptr[0]),\n .I2(wr_ptr[1]),\n .I3(wr_ptr[3]),\n .I4(rd_ptr_timing[0]),\n .O(\\my_full[4]_i_3__2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair873\" *) \n LUT5 #(\n .INIT(32'h84210842)) \n \\my_full[4]_i_4__2 \n (.I0(rd_ptr_timing[0]),\n .I1(rd_ptr_timing[1]),\n .I2(wr_ptr[0]),\n .I3(wr_ptr[1]),\n .I4(wr_ptr[3]),\n .O(\\my_full[4]_i_4__2_n_0 ));\n (* syn_maxfan = \"3\" *) \n FDRE \\my_full_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_full[4]_i_1__1_n_0 ),\n .Q(\\my_full_reg_n_0_[4] ),\n .R(1'b0));\n LUT3 #(\n .INIT(8'h0D)) \n out_fifo_i_1__5\n (.I0(\\my_empty_reg[1]_0 ),\n .I1(mux_wrdata_en),\n .I2(ofifo_rst_reg),\n .O(\\my_empty_reg[7]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair881\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_2__4\n (.I0(mem_reg_0_15_6_11_n_0),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[7]));\n (* SOFT_HLUTNM = \"soft_lutpair877\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_3__4\n (.I0(mem_reg_0_15_6_11_n_1),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[6]));\n (* SOFT_HLUTNM = \"soft_lutpair882\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_4__4\n (.I0(mem_reg_0_15_0_5_n_4),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[5]));\n (* SOFT_HLUTNM = \"soft_lutpair879\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_5__4\n (.I0(mem_reg_0_15_0_5_n_5),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[4]));\n (* SOFT_HLUTNM = \"soft_lutpair880\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_6__4\n (.I0(mem_reg_0_15_0_5_n_2),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair878\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_74__1\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[285] [7]),\n .I2(mem_reg_0_15_78_79_n_0),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[7]));\n (* SOFT_HLUTNM = \"soft_lutpair881\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_75__1\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[285] [6]),\n .I2(mem_reg_0_15_78_79_n_1),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[6]));\n (* SOFT_HLUTNM = \"soft_lutpair879\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_76__1\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[285] [5]),\n .I2(mem_reg_0_15_72_77_n_4),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[5]));\n (* SOFT_HLUTNM = \"soft_lutpair880\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_77__1\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[285] [4]),\n .I2(mem_reg_0_15_72_77_n_5),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[4]));\n (* SOFT_HLUTNM = \"soft_lutpair877\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_78__1\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[285] [3]),\n .I2(mem_reg_0_15_72_77_n_2),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[3]));\n (* SOFT_HLUTNM = \"soft_lutpair883\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_79__0\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[285] [2]),\n .I2(mem_reg_0_15_72_77_n_3),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[2]));\n (* SOFT_HLUTNM = \"soft_lutpair876\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_7__3\n (.I0(mem_reg_0_15_0_5_n_3),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair876\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_80__0\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[285] [1]),\n .I2(mem_reg_0_15_72_77_n_0),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[1]));\n (* SOFT_HLUTNM = \"soft_lutpair882\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_81__0\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[285] [0]),\n .I2(mem_reg_0_15_72_77_n_1),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[0]));\n (* SOFT_HLUTNM = \"soft_lutpair883\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_8__3\n (.I0(mem_reg_0_15_0_5_n_0),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair878\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_9__3\n (.I0(mem_reg_0_15_0_5_n_1),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[0]));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[0] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__2_n_0 ),\n .D(nxt_rd_ptr[0]),\n .Q(\\rd_ptr_reg_n_0_[0] ),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[1] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__2_n_0 ),\n .D(nxt_rd_ptr[1]),\n .Q(\\rd_ptr_reg_n_0_[1] ),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[2] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__2_n_0 ),\n .D(nxt_rd_ptr[2]),\n .Q(\\rd_ptr_reg_n_0_[2] ),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[3] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__2_n_0 ),\n .D(nxt_rd_ptr[3]),\n .Q(\\rd_ptr_reg_n_0_[3] ),\n .R(ofifo_rst));\n (* SOFT_HLUTNM = \"soft_lutpair887\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\rd_ptr_timing[0]_i_1__5 \n (.I0(\\rd_ptr_reg_n_0_[3] ),\n .I1(\\rd_ptr_reg_n_0_[0] ),\n .O(nxt_rd_ptr[0]));\n (* SOFT_HLUTNM = \"soft_lutpair887\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\rd_ptr_timing[1]_i_1__2 \n (.I0(\\rd_ptr_reg_n_0_[3] ),\n .I1(\\rd_ptr_reg_n_0_[0] ),\n .I2(\\rd_ptr_reg_n_0_[1] ),\n .O(nxt_rd_ptr[1]));\n (* SOFT_HLUTNM = \"soft_lutpair885\" *) \n LUT4 #(\n .INIT(16'hAA6A)) \n \\rd_ptr_timing[2]_i_1__2 \n (.I0(\\rd_ptr_reg_n_0_[2] ),\n .I1(\\rd_ptr_reg_n_0_[0] ),\n .I2(\\rd_ptr_reg_n_0_[1] ),\n .I3(\\rd_ptr_reg_n_0_[3] ),\n .O(nxt_rd_ptr[2]));\n LUT2 #(\n .INIT(4'h1)) \n \\rd_ptr_timing[3]_i_1__2 \n (.I0(\\my_empty_reg_n_0_[7] ),\n .I1(ofifo_rst_reg),\n .O(\\rd_ptr_timing[3]_i_1__2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair885\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\rd_ptr_timing[3]_i_2__2 \n (.I0(\\rd_ptr_reg_n_0_[3] ),\n .I1(\\rd_ptr_reg_n_0_[1] ),\n .I2(\\rd_ptr_reg_n_0_[0] ),\n .I3(\\rd_ptr_reg_n_0_[2] ),\n .O(nxt_rd_ptr[3]));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[0] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__2_n_0 ),\n .D(nxt_rd_ptr[0]),\n .Q(rd_ptr_timing[0]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[1] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__2_n_0 ),\n .D(nxt_rd_ptr[1]),\n .Q(rd_ptr_timing[1]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[2] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__2_n_0 ),\n .D(nxt_rd_ptr[2]),\n .Q(rd_ptr_timing[2]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[3] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__2_n_0 ),\n .D(nxt_rd_ptr[3]),\n .Q(rd_ptr_timing[3]),\n .R(ofifo_rst));\n (* SOFT_HLUTNM = \"soft_lutpair886\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\wr_ptr[0]_i_1__7 \n (.I0(wr_ptr[3]),\n .I1(wr_ptr[0]),\n .O(nxt_wr_ptr[0]));\n (* SOFT_HLUTNM = \"soft_lutpair886\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\wr_ptr[1]_i_1__7 \n (.I0(wr_ptr[3]),\n .I1(wr_ptr[0]),\n .I2(wr_ptr[1]),\n .O(nxt_wr_ptr[1]));\n (* SOFT_HLUTNM = \"soft_lutpair884\" *) \n LUT4 #(\n .INIT(16'hAA6A)) \n \\wr_ptr[2]_i_1__4 \n (.I0(wr_ptr[2]),\n .I1(wr_ptr[0]),\n .I2(wr_ptr[1]),\n .I3(wr_ptr[3]),\n .O(nxt_wr_ptr[2]));\n LUT4 #(\n .INIT(16'h082A)) \n \\wr_ptr[3]_i_1__4 \n (.I0(mux_wrdata_en),\n .I1(ofifo_rst_reg),\n .I2(\\my_full_reg_n_0_[4] ),\n .I3(\\my_empty_reg_n_0_[7] ),\n .O(wr_ptr0));\n (* SOFT_HLUTNM = \"soft_lutpair884\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\wr_ptr[3]_i_2__1 \n (.I0(wr_ptr[3]),\n .I1(wr_ptr[1]),\n .I2(wr_ptr[0]),\n .I3(wr_ptr[2]),\n .O(nxt_wr_ptr[3]));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[0] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[0]),\n .Q(wr_ptr[0]),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[1] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[1]),\n .Q(wr_ptr[1]),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[2] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[2]),\n .Q(wr_ptr[2]),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[3] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[3]),\n .Q(wr_ptr[3]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[0] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[0]),\n .Q(wr_ptr_timing[0]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[1] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[1]),\n .Q(wr_ptr_timing[1]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[2] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[2]),\n .Q(wr_ptr_timing[2]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[3] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[3]),\n .Q(wr_ptr_timing[3]),\n .R(ofifo_rst));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_of_pre_fifo\" *) \nmodule ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized5\n (\\my_empty_reg[7]_0 ,\n \\my_empty_reg[1]_0 ,\n D0,\n D9,\n \\my_empty_reg[7]_1 ,\n Q,\n ofifo_rst,\n CLK,\n ofifo_rst_reg,\n mux_wrdata_en,\n init_calib_complete_reg_rep,\n \\write_buffer.wr_buf_out_data_reg[284] ,\n phy_dout);\n output \\my_empty_reg[7]_0 ;\n output \\my_empty_reg[1]_0 ;\n output [7:0]D0;\n output [7:0]D9;\n output [63:0]\\my_empty_reg[7]_1 ;\n output [2:0]Q;\n input ofifo_rst;\n input CLK;\n input ofifo_rst_reg;\n input mux_wrdata_en;\n input init_calib_complete_reg_rep;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[284] ;\n input [71:0]phy_dout;\n\n wire CLK;\n wire [7:0]D0;\n wire [7:0]D9;\n wire [2:0]Q;\n wire \\entry_cnt[0]_i_1__2_n_0 ;\n wire \\entry_cnt[1]_i_1__2_n_0 ;\n wire \\entry_cnt[2]_i_1__2_n_0 ;\n wire \\entry_cnt[3]_i_1__2_n_0 ;\n wire \\entry_cnt[4]_i_1__2_n_0 ;\n wire \\entry_cnt[4]_i_2__2_n_0 ;\n wire \\entry_cnt[4]_i_3__2_n_0 ;\n wire \\entry_cnt_reg_n_0_[0] ;\n wire \\entry_cnt_reg_n_0_[1] ;\n wire init_calib_complete_reg_rep;\n wire mem_reg_0_15_0_5_n_0;\n wire mem_reg_0_15_0_5_n_1;\n wire mem_reg_0_15_0_5_n_2;\n wire mem_reg_0_15_0_5_n_3;\n wire mem_reg_0_15_0_5_n_4;\n wire mem_reg_0_15_0_5_n_5;\n wire mem_reg_0_15_6_11_n_0;\n wire mem_reg_0_15_6_11_n_1;\n wire mem_reg_0_15_72_77_n_0;\n wire mem_reg_0_15_72_77_n_1;\n wire mem_reg_0_15_72_77_n_2;\n wire mem_reg_0_15_72_77_n_3;\n wire mem_reg_0_15_72_77_n_4;\n wire mem_reg_0_15_72_77_n_5;\n wire mem_reg_0_15_78_79_n_0;\n wire mem_reg_0_15_78_79_n_1;\n wire mux_wrdata_en;\n wire my_empty0;\n wire \\my_empty[1]_i_1__3_n_0 ;\n wire \\my_empty[7]_i_1__3_n_0 ;\n wire \\my_empty[7]_i_3__3_n_0 ;\n wire \\my_empty[7]_i_4__3_n_0 ;\n wire \\my_empty_reg[1]_0 ;\n wire \\my_empty_reg[7]_0 ;\n wire [63:0]\\my_empty_reg[7]_1 ;\n wire \\my_empty_reg_n_0_[7] ;\n wire my_full0;\n wire \\my_full[4]_i_1__2_n_0 ;\n wire \\my_full[4]_i_3__3_n_0 ;\n wire \\my_full[4]_i_4__3_n_0 ;\n wire \\my_full_reg_n_0_[4] ;\n wire [3:0]nxt_rd_ptr;\n wire [3:0]nxt_wr_ptr;\n wire ofifo_rst;\n wire ofifo_rst_reg;\n wire [71:0]phy_dout;\n wire \\rd_ptr_reg_n_0_[0] ;\n wire \\rd_ptr_reg_n_0_[1] ;\n wire \\rd_ptr_reg_n_0_[2] ;\n wire \\rd_ptr_reg_n_0_[3] ;\n wire [3:0]rd_ptr_timing;\n wire \\rd_ptr_timing[3]_i_1__3_n_0 ;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) wire wr_en;\n wire [3:0]wr_ptr;\n wire wr_ptr0;\n wire [3:0]wr_ptr_timing;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[284] ;\n wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED;\n\n (* SOFT_HLUTNM = \"soft_lutpair926\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\entry_cnt[0]_i_1__2 \n (.I0(\\entry_cnt_reg_n_0_[0] ),\n .O(\\entry_cnt[0]_i_1__2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair924\" *) \n LUT5 #(\n .INIT(32'hAA6A5595)) \n \\entry_cnt[1]_i_1__2 \n (.I0(\\entry_cnt_reg_n_0_[0] ),\n .I1(ofifo_rst_reg),\n .I2(mux_wrdata_en),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(\\entry_cnt_reg_n_0_[1] ),\n .O(\\entry_cnt[1]_i_1__2_n_0 ));\n LUT6 #(\n .INIT(64'hFF7F0080AAEA5515)) \n \\entry_cnt[2]_i_1__2 \n (.I0(\\entry_cnt_reg_n_0_[0] ),\n .I1(ofifo_rst_reg),\n .I2(mux_wrdata_en),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(Q[0]),\n .I5(\\entry_cnt_reg_n_0_[1] ),\n .O(\\entry_cnt[2]_i_1__2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair926\" *) \n LUT5 #(\n .INIT(32'h7F80FE01)) \n \\entry_cnt[3]_i_1__2 \n (.I0(\\entry_cnt[4]_i_3__2_n_0 ),\n .I1(\\entry_cnt_reg_n_0_[0] ),\n .I2(\\entry_cnt_reg_n_0_[1] ),\n .I3(Q[1]),\n .I4(Q[0]),\n .O(\\entry_cnt[3]_i_1__2_n_0 ));\n LUT4 #(\n .INIT(16'h5003)) \n \\entry_cnt[4]_i_1__2 \n (.I0(\\my_full_reg_n_0_[4] ),\n .I1(\\my_empty_reg_n_0_[7] ),\n .I2(mux_wrdata_en),\n .I3(ofifo_rst_reg),\n .O(\\entry_cnt[4]_i_1__2_n_0 ));\n LUT6 #(\n .INIT(64'h7FFF8000FFFE0001)) \n \\entry_cnt[4]_i_2__2 \n (.I0(\\entry_cnt_reg_n_0_[1] ),\n .I1(\\entry_cnt_reg_n_0_[0] ),\n .I2(\\entry_cnt[4]_i_3__2_n_0 ),\n .I3(Q[0]),\n .I4(Q[2]),\n .I5(Q[1]),\n .O(\\entry_cnt[4]_i_2__2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair924\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\entry_cnt[4]_i_3__2 \n (.I0(ofifo_rst_reg),\n .I1(mux_wrdata_en),\n .I2(\\my_full_reg_n_0_[4] ),\n .O(\\entry_cnt[4]_i_3__2_n_0 ));\n FDRE \\entry_cnt_reg[0] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1__2_n_0 ),\n .D(\\entry_cnt[0]_i_1__2_n_0 ),\n .Q(\\entry_cnt_reg_n_0_[0] ),\n .R(ofifo_rst));\n FDRE \\entry_cnt_reg[1] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1__2_n_0 ),\n .D(\\entry_cnt[1]_i_1__2_n_0 ),\n .Q(\\entry_cnt_reg_n_0_[1] ),\n .R(ofifo_rst));\n FDRE \\entry_cnt_reg[2] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1__2_n_0 ),\n .D(\\entry_cnt[2]_i_1__2_n_0 ),\n .Q(Q[0]),\n .R(ofifo_rst));\n FDRE \\entry_cnt_reg[3] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1__2_n_0 ),\n .D(\\entry_cnt[3]_i_1__2_n_0 ),\n .Q(Q[1]),\n .R(ofifo_rst));\n FDRE \\entry_cnt_reg[4] \n (.C(CLK),\n .CE(\\entry_cnt[4]_i_1__2_n_0 ),\n .D(\\entry_cnt[4]_i_2__2_n_0 ),\n .Q(Q[2]),\n .R(ofifo_rst));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_0_5\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA({1'b0,1'b0}),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_15_0_5_n_0,mem_reg_0_15_0_5_n_1}),\n .DOB({mem_reg_0_15_0_5_n_2,mem_reg_0_15_0_5_n_3}),\n .DOC({mem_reg_0_15_0_5_n_4,mem_reg_0_15_0_5_n_5}),\n .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n LUT4 #(\n .INIT(16'h082A)) \n mem_reg_0_15_0_5_i_1__3\n (.I0(mux_wrdata_en),\n .I1(ofifo_rst_reg),\n .I2(\\my_full_reg_n_0_[4] ),\n .I3(\\my_empty_reg[1]_0 ),\n .O(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_12_17\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[5:4]),\n .DIB(phy_dout[7:6]),\n .DIC(phy_dout[9:8]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [5:4]),\n .DOB(\\my_empty_reg[7]_1 [7:6]),\n .DOC(\\my_empty_reg[7]_1 [9:8]),\n .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_18_23\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[11:10]),\n .DIB(phy_dout[13:12]),\n .DIC(phy_dout[15:14]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [11:10]),\n .DOB(\\my_empty_reg[7]_1 [13:12]),\n .DOC(\\my_empty_reg[7]_1 [15:14]),\n .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_24_29\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[17:16]),\n .DIB(phy_dout[19:18]),\n .DIC(phy_dout[21:20]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [17:16]),\n .DOB(\\my_empty_reg[7]_1 [19:18]),\n .DOC(\\my_empty_reg[7]_1 [21:20]),\n .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_30_35\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[23:22]),\n .DIB(phy_dout[25:24]),\n .DIC(phy_dout[27:26]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [23:22]),\n .DOB(\\my_empty_reg[7]_1 [25:24]),\n .DOC(\\my_empty_reg[7]_1 [27:26]),\n .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_36_41\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[29:28]),\n .DIB(phy_dout[31:30]),\n .DIC(phy_dout[33:32]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [29:28]),\n .DOB(\\my_empty_reg[7]_1 [31:30]),\n .DOC(\\my_empty_reg[7]_1 [33:32]),\n .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_42_47\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[35:34]),\n .DIB(phy_dout[37:36]),\n .DIC(phy_dout[39:38]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [35:34]),\n .DOB(\\my_empty_reg[7]_1 [37:36]),\n .DOC(\\my_empty_reg[7]_1 [39:38]),\n .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_48_53\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[41:40]),\n .DIB(phy_dout[43:42]),\n .DIC(phy_dout[45:44]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [41:40]),\n .DOB(\\my_empty_reg[7]_1 [43:42]),\n .DOC(\\my_empty_reg[7]_1 [45:44]),\n .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_54_59\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[47:46]),\n .DIB(phy_dout[49:48]),\n .DIC(phy_dout[51:50]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [47:46]),\n .DOB(\\my_empty_reg[7]_1 [49:48]),\n .DOC(\\my_empty_reg[7]_1 [51:50]),\n .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_60_65\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[53:52]),\n .DIB(phy_dout[55:54]),\n .DIC(phy_dout[57:56]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [53:52]),\n .DOB(\\my_empty_reg[7]_1 [55:54]),\n .DOC(\\my_empty_reg[7]_1 [57:56]),\n .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_66_71\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[59:58]),\n .DIB(phy_dout[61:60]),\n .DIC(phy_dout[63:62]),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [59:58]),\n .DOB(\\my_empty_reg[7]_1 [61:60]),\n .DOC(\\my_empty_reg[7]_1 [63:62]),\n .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_6_11\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA({1'b0,1'b0}),\n .DIB(phy_dout[1:0]),\n .DIC(phy_dout[3:2]),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_15_6_11_n_0,mem_reg_0_15_6_11_n_1}),\n .DOB(\\my_empty_reg[7]_1 [1:0]),\n .DOC(\\my_empty_reg[7]_1 [3:2]),\n .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_72_77\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[65:64]),\n .DIB(phy_dout[67:66]),\n .DIC(phy_dout[69:68]),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_15_72_77_n_0,mem_reg_0_15_72_77_n_1}),\n .DOB({mem_reg_0_15_72_77_n_2,mem_reg_0_15_72_77_n_3}),\n .DOC({mem_reg_0_15_72_77_n_4,mem_reg_0_15_72_77_n_5}),\n .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_78_79\n (.ADDRA({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRB({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRC({1'b0,\\rd_ptr_reg_n_0_[3] ,\\rd_ptr_reg_n_0_[2] ,\\rd_ptr_reg_n_0_[1] ,\\rd_ptr_reg_n_0_[0] }),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[71:70]),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA({mem_reg_0_15_78_79_n_0,mem_reg_0_15_78_79_n_1}),\n .DOB(NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED[1:0]),\n .DOC(NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED[1:0]),\n .DOD(NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n LUT6 #(\n .INIT(64'hFFFFFFFFF071F070)) \n \\my_empty[1]_i_1__3 \n (.I0(mux_wrdata_en),\n .I1(ofifo_rst_reg),\n .I2(\\my_empty_reg[1]_0 ),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(my_empty0),\n .I5(ofifo_rst),\n .O(\\my_empty[1]_i_1__3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFF071F070)) \n \\my_empty[7]_i_1__3 \n (.I0(mux_wrdata_en),\n .I1(ofifo_rst_reg),\n .I2(\\my_empty_reg_n_0_[7] ),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(my_empty0),\n .I5(ofifo_rst),\n .O(\\my_empty[7]_i_1__3_n_0 ));\n LUT5 #(\n .INIT(32'h4A400D08)) \n \\my_empty[7]_i_2__3 \n (.I0(wr_ptr_timing[2]),\n .I1(\\my_empty[7]_i_3__3_n_0 ),\n .I2(wr_ptr_timing[3]),\n .I3(\\my_empty[7]_i_4__3_n_0 ),\n .I4(\\rd_ptr_reg_n_0_[2] ),\n .O(my_empty0));\n (* SOFT_HLUTNM = \"soft_lutpair927\" *) \n LUT5 #(\n .INIT(32'h00000040)) \n \\my_empty[7]_i_3__3 \n (.I0(wr_ptr_timing[1]),\n .I1(\\rd_ptr_reg_n_0_[0] ),\n .I2(\\rd_ptr_reg_n_0_[1] ),\n .I3(\\rd_ptr_reg_n_0_[3] ),\n .I4(wr_ptr_timing[0]),\n .O(\\my_empty[7]_i_3__3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair927\" *) \n LUT5 #(\n .INIT(32'h84210842)) \n \\my_empty[7]_i_4__3 \n (.I0(wr_ptr_timing[0]),\n .I1(wr_ptr_timing[1]),\n .I2(\\rd_ptr_reg_n_0_[0] ),\n .I3(\\rd_ptr_reg_n_0_[1] ),\n .I4(\\rd_ptr_reg_n_0_[3] ),\n .O(\\my_empty[7]_i_4__3_n_0 ));\n (* syn_maxfan = \"3\" *) \n FDRE \\my_empty_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_empty[1]_i_1__3_n_0 ),\n .Q(\\my_empty_reg[1]_0 ),\n .R(1'b0));\n (* syn_maxfan = \"3\" *) \n FDRE \\my_empty_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_empty[7]_i_1__3_n_0 ),\n .Q(\\my_empty_reg_n_0_[7] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000FF00FC80)) \n \\my_full[4]_i_1__2 \n (.I0(my_full0),\n .I1(mux_wrdata_en),\n .I2(ofifo_rst_reg),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(\\my_empty_reg_n_0_[7] ),\n .I5(ofifo_rst),\n .O(\\my_full[4]_i_1__2_n_0 ));\n LUT5 #(\n .INIT(32'h4A400D08)) \n \\my_full[4]_i_2__3 \n (.I0(rd_ptr_timing[2]),\n .I1(\\my_full[4]_i_3__3_n_0 ),\n .I2(rd_ptr_timing[3]),\n .I3(\\my_full[4]_i_4__3_n_0 ),\n .I4(wr_ptr[2]),\n .O(my_full0));\n (* SOFT_HLUTNM = \"soft_lutpair925\" *) \n LUT5 #(\n .INIT(32'h00000040)) \n \\my_full[4]_i_3__3 \n (.I0(rd_ptr_timing[1]),\n .I1(wr_ptr[0]),\n .I2(wr_ptr[1]),\n .I3(wr_ptr[3]),\n .I4(rd_ptr_timing[0]),\n .O(\\my_full[4]_i_3__3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair925\" *) \n LUT5 #(\n .INIT(32'h84210842)) \n \\my_full[4]_i_4__3 \n (.I0(rd_ptr_timing[0]),\n .I1(rd_ptr_timing[1]),\n .I2(wr_ptr[0]),\n .I3(wr_ptr[1]),\n .I4(wr_ptr[3]),\n .O(\\my_full[4]_i_4__3_n_0 ));\n (* syn_maxfan = \"3\" *) \n FDRE \\my_full_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_full[4]_i_1__2_n_0 ),\n .Q(\\my_full_reg_n_0_[4] ),\n .R(1'b0));\n LUT3 #(\n .INIT(8'h0D)) \n out_fifo_i_1__6\n (.I0(\\my_empty_reg[1]_0 ),\n .I1(mux_wrdata_en),\n .I2(ofifo_rst_reg),\n .O(\\my_empty_reg[7]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair933\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_2__5\n (.I0(mem_reg_0_15_6_11_n_0),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[7]));\n (* SOFT_HLUTNM = \"soft_lutpair929\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_3__5\n (.I0(mem_reg_0_15_6_11_n_1),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[6]));\n (* SOFT_HLUTNM = \"soft_lutpair934\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_4__5\n (.I0(mem_reg_0_15_0_5_n_4),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[5]));\n (* SOFT_HLUTNM = \"soft_lutpair931\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_5__5\n (.I0(mem_reg_0_15_0_5_n_5),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[4]));\n (* SOFT_HLUTNM = \"soft_lutpair932\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_6__5\n (.I0(mem_reg_0_15_0_5_n_2),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair930\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_74__0\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[284] [7]),\n .I2(mem_reg_0_15_78_79_n_0),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[7]));\n (* SOFT_HLUTNM = \"soft_lutpair933\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_75__0\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[284] [6]),\n .I2(mem_reg_0_15_78_79_n_1),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[6]));\n (* SOFT_HLUTNM = \"soft_lutpair931\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_76__0\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[284] [5]),\n .I2(mem_reg_0_15_72_77_n_4),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[5]));\n (* SOFT_HLUTNM = \"soft_lutpair932\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_77__0\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[284] [4]),\n .I2(mem_reg_0_15_72_77_n_5),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[4]));\n (* SOFT_HLUTNM = \"soft_lutpair929\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_78__0\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[284] [3]),\n .I2(mem_reg_0_15_72_77_n_2),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[3]));\n (* SOFT_HLUTNM = \"soft_lutpair935\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_79\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[284] [2]),\n .I2(mem_reg_0_15_72_77_n_3),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[2]));\n (* SOFT_HLUTNM = \"soft_lutpair928\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_7__4\n (.I0(mem_reg_0_15_0_5_n_3),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair928\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_80\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[284] [1]),\n .I2(mem_reg_0_15_72_77_n_0),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[1]));\n (* SOFT_HLUTNM = \"soft_lutpair934\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_81\n (.I0(init_calib_complete_reg_rep),\n .I1(\\write_buffer.wr_buf_out_data_reg[284] [0]),\n .I2(mem_reg_0_15_72_77_n_1),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[0]));\n (* SOFT_HLUTNM = \"soft_lutpair935\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_8__4\n (.I0(mem_reg_0_15_0_5_n_0),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair930\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_9__4\n (.I0(mem_reg_0_15_0_5_n_1),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[0]));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[0] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__3_n_0 ),\n .D(nxt_rd_ptr[0]),\n .Q(\\rd_ptr_reg_n_0_[0] ),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[1] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__3_n_0 ),\n .D(nxt_rd_ptr[1]),\n .Q(\\rd_ptr_reg_n_0_[1] ),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[2] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__3_n_0 ),\n .D(nxt_rd_ptr[2]),\n .Q(\\rd_ptr_reg_n_0_[2] ),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[3] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__3_n_0 ),\n .D(nxt_rd_ptr[3]),\n .Q(\\rd_ptr_reg_n_0_[3] ),\n .R(ofifo_rst));\n (* SOFT_HLUTNM = \"soft_lutpair939\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\rd_ptr_timing[0]_i_1__7 \n (.I0(\\rd_ptr_reg_n_0_[3] ),\n .I1(\\rd_ptr_reg_n_0_[0] ),\n .O(nxt_rd_ptr[0]));\n (* SOFT_HLUTNM = \"soft_lutpair939\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\rd_ptr_timing[1]_i_1__3 \n (.I0(\\rd_ptr_reg_n_0_[3] ),\n .I1(\\rd_ptr_reg_n_0_[0] ),\n .I2(\\rd_ptr_reg_n_0_[1] ),\n .O(nxt_rd_ptr[1]));\n (* SOFT_HLUTNM = \"soft_lutpair937\" *) \n LUT4 #(\n .INIT(16'hAA6A)) \n \\rd_ptr_timing[2]_i_1__3 \n (.I0(\\rd_ptr_reg_n_0_[2] ),\n .I1(\\rd_ptr_reg_n_0_[0] ),\n .I2(\\rd_ptr_reg_n_0_[1] ),\n .I3(\\rd_ptr_reg_n_0_[3] ),\n .O(nxt_rd_ptr[2]));\n LUT2 #(\n .INIT(4'h1)) \n \\rd_ptr_timing[3]_i_1__3 \n (.I0(\\my_empty_reg_n_0_[7] ),\n .I1(ofifo_rst_reg),\n .O(\\rd_ptr_timing[3]_i_1__3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair937\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\rd_ptr_timing[3]_i_2__3 \n (.I0(\\rd_ptr_reg_n_0_[3] ),\n .I1(\\rd_ptr_reg_n_0_[1] ),\n .I2(\\rd_ptr_reg_n_0_[0] ),\n .I3(\\rd_ptr_reg_n_0_[2] ),\n .O(nxt_rd_ptr[3]));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[0] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__3_n_0 ),\n .D(nxt_rd_ptr[0]),\n .Q(rd_ptr_timing[0]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[1] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__3_n_0 ),\n .D(nxt_rd_ptr[1]),\n .Q(rd_ptr_timing[1]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[2] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__3_n_0 ),\n .D(nxt_rd_ptr[2]),\n .Q(rd_ptr_timing[2]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[3] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1__3_n_0 ),\n .D(nxt_rd_ptr[3]),\n .Q(rd_ptr_timing[3]),\n .R(ofifo_rst));\n (* SOFT_HLUTNM = \"soft_lutpair938\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\wr_ptr[0]_i_1__9 \n (.I0(wr_ptr[3]),\n .I1(wr_ptr[0]),\n .O(nxt_wr_ptr[0]));\n (* SOFT_HLUTNM = \"soft_lutpair938\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\wr_ptr[1]_i_1__9 \n (.I0(wr_ptr[3]),\n .I1(wr_ptr[0]),\n .I2(wr_ptr[1]),\n .O(nxt_wr_ptr[1]));\n (* SOFT_HLUTNM = \"soft_lutpair936\" *) \n LUT4 #(\n .INIT(16'hAA6A)) \n \\wr_ptr[2]_i_1__5 \n (.I0(wr_ptr[2]),\n .I1(wr_ptr[0]),\n .I2(wr_ptr[1]),\n .I3(wr_ptr[3]),\n .O(nxt_wr_ptr[2]));\n LUT4 #(\n .INIT(16'h082A)) \n \\wr_ptr[3]_i_1__5 \n (.I0(mux_wrdata_en),\n .I1(ofifo_rst_reg),\n .I2(\\my_full_reg_n_0_[4] ),\n .I3(\\my_empty_reg_n_0_[7] ),\n .O(wr_ptr0));\n (* SOFT_HLUTNM = \"soft_lutpair936\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\wr_ptr[3]_i_2__2 \n (.I0(wr_ptr[3]),\n .I1(wr_ptr[1]),\n .I2(wr_ptr[0]),\n .I3(wr_ptr[2]),\n .O(nxt_wr_ptr[3]));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[0] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[0]),\n .Q(wr_ptr[0]),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[1] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[1]),\n .Q(wr_ptr[1]),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[2] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[2]),\n .Q(wr_ptr[2]),\n .R(ofifo_rst));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[3] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[3]),\n .Q(wr_ptr[3]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[0] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[0]),\n .Q(wr_ptr_timing[0]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[1] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[1]),\n .Q(wr_ptr_timing[1]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[2] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[2]),\n .Q(wr_ptr_timing[2]),\n .R(ofifo_rst));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[3] \n (.C(CLK),\n .CE(wr_ptr0),\n .D(nxt_wr_ptr[3]),\n .Q(wr_ptr_timing[3]),\n .R(ofifo_rst));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_of_pre_fifo\" *) \nmodule ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized6\n (\\rd_ptr_timing_reg[2]_0 ,\n \\rd_ptr_timing_reg[2]_1 ,\n \\rd_ptr_timing_reg[2]_2 ,\n \\rd_ptr_timing_reg[2]_3 ,\n wr_en,\n \\my_empty_reg[1]_0 ,\n D0,\n D1,\n \\rd_ptr_timing_reg[0]_0 ,\n D2,\n Q,\n SR,\n CLK,\n mux_cmd_wren,\n ofifo_rst_reg,\n mem_out);\n output \\rd_ptr_timing_reg[2]_0 ;\n output \\rd_ptr_timing_reg[2]_1 ;\n output \\rd_ptr_timing_reg[2]_2 ;\n output \\rd_ptr_timing_reg[2]_3 ;\n output wr_en;\n output \\my_empty_reg[1]_0 ;\n output [4:0]D0;\n output [4:0]D1;\n output \\rd_ptr_timing_reg[0]_0 ;\n output [1:0]D2;\n output [3:0]Q;\n input [0:0]SR;\n input CLK;\n input mux_cmd_wren;\n input ofifo_rst_reg;\n input [11:0]mem_out;\n\n wire CLK;\n wire [4:0]D0;\n wire [4:0]D1;\n wire [1:0]D2;\n wire [3:0]Q;\n wire [0:0]SR;\n wire [11:0]mem_out;\n wire mux_cmd_wren;\n wire my_empty0;\n wire \\my_empty[1]_i_1__6_n_0 ;\n wire \\my_empty[6]_i_1__1_n_0 ;\n wire \\my_empty[6]_i_3_n_0 ;\n wire \\my_empty[6]_i_4_n_0 ;\n wire \\my_empty_reg[1]_0 ;\n wire \\my_empty_reg_n_0_[6] ;\n wire my_full0;\n wire \\my_full[3]_i_1_n_0 ;\n wire \\my_full[3]_i_3_n_0 ;\n wire \\my_full[3]_i_4_n_0 ;\n wire \\my_full_reg_n_0_[3] ;\n wire [3:0]nxt_rd_ptr;\n wire [3:0]nxt_wr_ptr;\n wire ofifo_rst_reg;\n wire \\rd_ptr[0]_i_1__1_n_0 ;\n wire [3:0]rd_ptr_timing;\n wire \\rd_ptr_timing_reg[0]_0 ;\n wire \\rd_ptr_timing_reg[2]_0 ;\n wire \\rd_ptr_timing_reg[2]_1 ;\n wire \\rd_ptr_timing_reg[2]_2 ;\n wire \\rd_ptr_timing_reg[2]_3 ;\n wire wr_en;\n wire wr_ptr0__0;\n wire [3:0]wr_ptr_timing;\n\n (* SOFT_HLUTNM = \"soft_lutpair940\" *) \n LUT5 #(\n .INIT(32'hC0F0F0F2)) \n \\my_empty[1]_i_1__6 \n (.I0(my_empty0),\n .I1(\\my_full_reg_n_0_[3] ),\n .I2(\\my_empty_reg[1]_0 ),\n .I3(ofifo_rst_reg),\n .I4(mux_cmd_wren),\n .O(\\my_empty[1]_i_1__6_n_0 ));\n LUT5 #(\n .INIT(32'hC0F0F0F2)) \n \\my_empty[6]_i_1__1 \n (.I0(my_empty0),\n .I1(\\my_full_reg_n_0_[3] ),\n .I2(\\my_empty_reg_n_0_[6] ),\n .I3(ofifo_rst_reg),\n .I4(mux_cmd_wren),\n .O(\\my_empty[6]_i_1__1_n_0 ));\n LUT5 #(\n .INIT(32'h4A400D08)) \n \\my_empty[6]_i_2 \n (.I0(wr_ptr_timing[2]),\n .I1(\\my_empty[6]_i_3_n_0 ),\n .I2(wr_ptr_timing[3]),\n .I3(\\my_empty[6]_i_4_n_0 ),\n .I4(\\rd_ptr_timing_reg[2]_2 ),\n .O(my_empty0));\n (* SOFT_HLUTNM = \"soft_lutpair941\" *) \n LUT5 #(\n .INIT(32'h00000040)) \n \\my_empty[6]_i_3 \n (.I0(wr_ptr_timing[1]),\n .I1(\\rd_ptr_timing_reg[2]_0 ),\n .I2(\\rd_ptr_timing_reg[2]_1 ),\n .I3(\\rd_ptr_timing_reg[2]_3 ),\n .I4(wr_ptr_timing[0]),\n .O(\\my_empty[6]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair941\" *) \n LUT5 #(\n .INIT(32'h84210842)) \n \\my_empty[6]_i_4 \n (.I0(wr_ptr_timing[0]),\n .I1(wr_ptr_timing[1]),\n .I2(\\rd_ptr_timing_reg[2]_0 ),\n .I3(\\rd_ptr_timing_reg[2]_1 ),\n .I4(\\rd_ptr_timing_reg[2]_3 ),\n .O(\\my_empty[6]_i_4_n_0 ));\n (* syn_maxfan = \"3\" *) \n FDSE \\my_empty_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_empty[1]_i_1__6_n_0 ),\n .Q(\\my_empty_reg[1]_0 ),\n .S(SR));\n (* syn_maxfan = \"3\" *) \n FDSE \\my_empty_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_empty[6]_i_1__1_n_0 ),\n .Q(\\my_empty_reg_n_0_[6] ),\n .S(SR));\n LUT6 #(\n .INIT(64'h00000000FF00FC80)) \n \\my_full[3]_i_1 \n (.I0(my_full0),\n .I1(mux_cmd_wren),\n .I2(ofifo_rst_reg),\n .I3(\\my_full_reg_n_0_[3] ),\n .I4(\\my_empty_reg_n_0_[6] ),\n .I5(SR),\n .O(\\my_full[3]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h4A400D08)) \n \\my_full[3]_i_2 \n (.I0(rd_ptr_timing[2]),\n .I1(\\my_full[3]_i_3_n_0 ),\n .I2(rd_ptr_timing[3]),\n .I3(\\my_full[3]_i_4_n_0 ),\n .I4(Q[2]),\n .O(my_full0));\n (* SOFT_HLUTNM = \"soft_lutpair942\" *) \n LUT5 #(\n .INIT(32'h00000040)) \n \\my_full[3]_i_3 \n (.I0(rd_ptr_timing[1]),\n .I1(Q[0]),\n .I2(Q[1]),\n .I3(Q[3]),\n .I4(rd_ptr_timing[0]),\n .O(\\my_full[3]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair942\" *) \n LUT5 #(\n .INIT(32'h84210842)) \n \\my_full[3]_i_4 \n (.I0(rd_ptr_timing[0]),\n .I1(rd_ptr_timing[1]),\n .I2(Q[0]),\n .I3(Q[1]),\n .I4(Q[3]),\n .O(\\my_full[3]_i_4_n_0 ));\n (* syn_maxfan = \"3\" *) \n FDRE \\my_full_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_full[3]_i_1_n_0 ),\n .Q(\\my_full_reg_n_0_[3] ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair951\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_10__0\n (.I0(mem_out[9]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D1[4]));\n (* SOFT_HLUTNM = \"soft_lutpair947\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_11__0\n (.I0(mem_out[8]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D1[3]));\n (* SOFT_HLUTNM = \"soft_lutpair950\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_12__0\n (.I0(mem_out[7]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D1[2]));\n (* SOFT_HLUTNM = \"soft_lutpair948\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_13__0\n (.I0(mem_out[6]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D1[1]));\n (* SOFT_HLUTNM = \"soft_lutpair952\" *) \n LUT2 #(\n .INIT(4'hE)) \n out_fifo_i_14\n (.I0(mem_out[5]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D1[0]));\n (* SOFT_HLUTNM = \"soft_lutpair949\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_18__0\n (.I0(mem_out[11]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D2[1]));\n (* SOFT_HLUTNM = \"soft_lutpair949\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_19__0\n (.I0(mem_out[10]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D2[0]));\n (* SOFT_HLUTNM = \"soft_lutpair940\" *) \n LUT3 #(\n .INIT(8'h0D)) \n out_fifo_i_1__0\n (.I0(\\my_empty_reg[1]_0 ),\n .I1(mux_cmd_wren),\n .I2(ofifo_rst_reg),\n .O(\\rd_ptr_timing_reg[0]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair951\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_2__0\n (.I0(mem_out[4]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[4]));\n (* SOFT_HLUTNM = \"soft_lutpair947\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_3__0\n (.I0(mem_out[3]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair952\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_4__0\n (.I0(mem_out[2]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair948\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_5__0\n (.I0(mem_out[1]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair950\" *) \n LUT2 #(\n .INIT(4'hE)) \n out_fifo_i_6__0\n (.I0(mem_out[0]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[0]));\n LUT4 #(\n .INIT(16'h082A)) \n p_17_out\n (.I0(mux_cmd_wren),\n .I1(ofifo_rst_reg),\n .I2(\\my_full_reg_n_0_[3] ),\n .I3(\\my_empty_reg[1]_0 ),\n .O(wr_en));\n LUT2 #(\n .INIT(4'h1)) \n \\rd_ptr[0]_i_1__1 \n (.I0(\\my_empty_reg_n_0_[6] ),\n .I1(ofifo_rst_reg),\n .O(\\rd_ptr[0]_i_1__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair945\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\rd_ptr[0]_i_2 \n (.I0(\\rd_ptr_timing_reg[2]_3 ),\n .I1(\\rd_ptr_timing_reg[2]_0 ),\n .O(nxt_rd_ptr[0]));\n (* SOFT_HLUTNM = \"soft_lutpair945\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\rd_ptr[1]_i_1 \n (.I0(\\rd_ptr_timing_reg[2]_3 ),\n .I1(\\rd_ptr_timing_reg[2]_0 ),\n .I2(\\rd_ptr_timing_reg[2]_1 ),\n .O(nxt_rd_ptr[1]));\n (* SOFT_HLUTNM = \"soft_lutpair944\" *) \n LUT4 #(\n .INIT(16'hAA6A)) \n \\rd_ptr[2]_i_1 \n (.I0(\\rd_ptr_timing_reg[2]_2 ),\n .I1(\\rd_ptr_timing_reg[2]_0 ),\n .I2(\\rd_ptr_timing_reg[2]_1 ),\n .I3(\\rd_ptr_timing_reg[2]_3 ),\n .O(nxt_rd_ptr[2]));\n (* SOFT_HLUTNM = \"soft_lutpair944\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\rd_ptr[3]_i_1 \n (.I0(\\rd_ptr_timing_reg[2]_3 ),\n .I1(\\rd_ptr_timing_reg[2]_1 ),\n .I2(\\rd_ptr_timing_reg[2]_0 ),\n .I3(\\rd_ptr_timing_reg[2]_2 ),\n .O(nxt_rd_ptr[3]));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[0] \n (.C(CLK),\n .CE(\\rd_ptr[0]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[0]),\n .Q(\\rd_ptr_timing_reg[2]_0 ),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[1] \n (.C(CLK),\n .CE(\\rd_ptr[0]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[1]),\n .Q(\\rd_ptr_timing_reg[2]_1 ),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[2] \n (.C(CLK),\n .CE(\\rd_ptr[0]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[2]),\n .Q(\\rd_ptr_timing_reg[2]_2 ),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[3] \n (.C(CLK),\n .CE(\\rd_ptr[0]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[3]),\n .Q(\\rd_ptr_timing_reg[2]_3 ),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[0] \n (.C(CLK),\n .CE(\\rd_ptr[0]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[0]),\n .Q(rd_ptr_timing[0]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[1] \n (.C(CLK),\n .CE(\\rd_ptr[0]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[1]),\n .Q(rd_ptr_timing[1]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[2] \n (.C(CLK),\n .CE(\\rd_ptr[0]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[2]),\n .Q(rd_ptr_timing[2]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[3] \n (.C(CLK),\n .CE(\\rd_ptr[0]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[3]),\n .Q(rd_ptr_timing[3]),\n .R(SR));\n LUT4 #(\n .INIT(16'h082A)) \n wr_ptr0\n (.I0(mux_cmd_wren),\n .I1(ofifo_rst_reg),\n .I2(\\my_full_reg_n_0_[3] ),\n .I3(\\my_empty_reg_n_0_[6] ),\n .O(wr_ptr0__0));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[0] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[0]),\n .Q(Q[0]),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[1] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[1]),\n .Q(Q[1]),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[2] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[2]),\n .Q(Q[2]),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[3] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[3]),\n .Q(Q[3]),\n .R(SR));\n (* SOFT_HLUTNM = \"soft_lutpair946\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\wr_ptr_timing[0]_i_1 \n (.I0(Q[3]),\n .I1(Q[0]),\n .O(nxt_wr_ptr[0]));\n (* SOFT_HLUTNM = \"soft_lutpair946\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\wr_ptr_timing[1]_i_1 \n (.I0(Q[3]),\n .I1(Q[0]),\n .I2(Q[1]),\n .O(nxt_wr_ptr[1]));\n (* SOFT_HLUTNM = \"soft_lutpair943\" *) \n LUT4 #(\n .INIT(16'hAA6A)) \n \\wr_ptr_timing[2]_i_1 \n (.I0(Q[2]),\n .I1(Q[0]),\n .I2(Q[1]),\n .I3(Q[3]),\n .O(nxt_wr_ptr[2]));\n (* SOFT_HLUTNM = \"soft_lutpair943\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\wr_ptr_timing[3]_i_1 \n (.I0(Q[3]),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(Q[2]),\n .O(nxt_wr_ptr[3]));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[0] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[0]),\n .Q(wr_ptr_timing[0]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[1] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[1]),\n .Q(wr_ptr_timing[1]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[2] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[2]),\n .Q(wr_ptr_timing[2]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[3] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[3]),\n .Q(wr_ptr_timing[3]),\n .R(SR));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_of_pre_fifo\" *) \nmodule ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized7\n (\\rd_ptr_timing_reg[2]_0 ,\n \\rd_ptr_timing_reg[2]_1 ,\n \\rd_ptr_timing_reg[2]_2 ,\n \\rd_ptr_timing_reg[2]_3 ,\n wr_en_5,\n \\my_empty_reg[1]_0 ,\n \\my_full_reg[3]_0 ,\n D0,\n D3,\n D5,\n D6,\n D7,\n Q,\n SR,\n CLK,\n mux_cmd_wren,\n B_of_full,\n \\rd_ptr_reg[3]_0 );\n output \\rd_ptr_timing_reg[2]_0 ;\n output \\rd_ptr_timing_reg[2]_1 ;\n output \\rd_ptr_timing_reg[2]_2 ;\n output \\rd_ptr_timing_reg[2]_3 ;\n output wr_en_5;\n output \\my_empty_reg[1]_0 ;\n output \\my_full_reg[3]_0 ;\n output [5:0]D0;\n output [1:0]D3;\n output [1:0]D5;\n output [3:0]D6;\n output [3:0]D7;\n output [3:0]Q;\n input [0:0]SR;\n input CLK;\n input mux_cmd_wren;\n input B_of_full;\n input [17:0]\\rd_ptr_reg[3]_0 ;\n\n wire B_of_full;\n wire CLK;\n wire [5:0]D0;\n wire [1:0]D3;\n wire [1:0]D5;\n wire [3:0]D6;\n wire [3:0]D7;\n wire [3:0]Q;\n wire [0:0]SR;\n wire mux_cmd_wren;\n wire my_empty0;\n wire \\my_empty[1]_i_1__4_n_0 ;\n wire \\my_empty[6]_i_1_n_0 ;\n wire \\my_empty[6]_i_3__0_n_0 ;\n wire \\my_empty[6]_i_4__0_n_0 ;\n wire \\my_empty_reg[1]_0 ;\n wire \\my_empty_reg_n_0_[6] ;\n wire my_full0;\n wire \\my_full[3]_i_1__0_n_0 ;\n wire \\my_full[3]_i_3__0_n_0 ;\n wire \\my_full[3]_i_4__0_n_0 ;\n wire \\my_full_reg[3]_0 ;\n wire \\my_full_reg_n_0_[3] ;\n wire [3:0]nxt_rd_ptr;\n wire [3:0]nxt_wr_ptr;\n wire \\rd_ptr[3]_i_1__0_n_0 ;\n wire [17:0]\\rd_ptr_reg[3]_0 ;\n wire [3:0]rd_ptr_timing;\n wire \\rd_ptr_timing_reg[2]_0 ;\n wire \\rd_ptr_timing_reg[2]_1 ;\n wire \\rd_ptr_timing_reg[2]_2 ;\n wire \\rd_ptr_timing_reg[2]_3 ;\n wire wr_en_5;\n wire wr_ptr0__0;\n wire [3:0]wr_ptr_timing;\n\n (* SOFT_HLUTNM = \"soft_lutpair955\" *) \n LUT5 #(\n .INIT(32'hC0F0F0F2)) \n \\my_empty[1]_i_1__4 \n (.I0(my_empty0),\n .I1(\\my_full_reg_n_0_[3] ),\n .I2(\\my_empty_reg[1]_0 ),\n .I3(B_of_full),\n .I4(mux_cmd_wren),\n .O(\\my_empty[1]_i_1__4_n_0 ));\n LUT5 #(\n .INIT(32'hC0F0F0F2)) \n \\my_empty[6]_i_1 \n (.I0(my_empty0),\n .I1(\\my_full_reg_n_0_[3] ),\n .I2(\\my_empty_reg_n_0_[6] ),\n .I3(B_of_full),\n .I4(mux_cmd_wren),\n .O(\\my_empty[6]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h4A400D08)) \n \\my_empty[6]_i_2__0 \n (.I0(wr_ptr_timing[2]),\n .I1(\\my_empty[6]_i_3__0_n_0 ),\n .I2(wr_ptr_timing[3]),\n .I3(\\my_empty[6]_i_4__0_n_0 ),\n .I4(\\rd_ptr_timing_reg[2]_1 ),\n .O(my_empty0));\n (* SOFT_HLUTNM = \"soft_lutpair954\" *) \n LUT5 #(\n .INIT(32'h00000040)) \n \\my_empty[6]_i_3__0 \n (.I0(wr_ptr_timing[1]),\n .I1(\\rd_ptr_timing_reg[2]_3 ),\n .I2(\\rd_ptr_timing_reg[2]_2 ),\n .I3(\\rd_ptr_timing_reg[2]_0 ),\n .I4(wr_ptr_timing[0]),\n .O(\\my_empty[6]_i_3__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair954\" *) \n LUT5 #(\n .INIT(32'h84210842)) \n \\my_empty[6]_i_4__0 \n (.I0(wr_ptr_timing[0]),\n .I1(wr_ptr_timing[1]),\n .I2(\\rd_ptr_timing_reg[2]_3 ),\n .I3(\\rd_ptr_timing_reg[2]_2 ),\n .I4(\\rd_ptr_timing_reg[2]_0 ),\n .O(\\my_empty[6]_i_4__0_n_0 ));\n (* syn_maxfan = \"3\" *) \n FDSE \\my_empty_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_empty[1]_i_1__4_n_0 ),\n .Q(\\my_empty_reg[1]_0 ),\n .S(SR));\n (* syn_maxfan = \"3\" *) \n FDSE \\my_empty_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_empty[6]_i_1_n_0 ),\n .Q(\\my_empty_reg_n_0_[6] ),\n .S(SR));\n LUT6 #(\n .INIT(64'h00000000FF00FC80)) \n \\my_full[3]_i_1__0 \n (.I0(my_full0),\n .I1(mux_cmd_wren),\n .I2(B_of_full),\n .I3(\\my_full_reg_n_0_[3] ),\n .I4(\\my_empty_reg_n_0_[6] ),\n .I5(SR),\n .O(\\my_full[3]_i_1__0_n_0 ));\n LUT5 #(\n .INIT(32'h4A400D08)) \n \\my_full[3]_i_2__0 \n (.I0(rd_ptr_timing[2]),\n .I1(\\my_full[3]_i_3__0_n_0 ),\n .I2(rd_ptr_timing[3]),\n .I3(\\my_full[3]_i_4__0_n_0 ),\n .I4(Q[2]),\n .O(my_full0));\n (* SOFT_HLUTNM = \"soft_lutpair953\" *) \n LUT5 #(\n .INIT(32'h00000040)) \n \\my_full[3]_i_3__0 \n (.I0(rd_ptr_timing[1]),\n .I1(Q[0]),\n .I2(Q[1]),\n .I3(Q[3]),\n .I4(rd_ptr_timing[0]),\n .O(\\my_full[3]_i_3__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair953\" *) \n LUT5 #(\n .INIT(32'h84210842)) \n \\my_full[3]_i_4__0 \n (.I0(rd_ptr_timing[0]),\n .I1(rd_ptr_timing[1]),\n .I2(Q[0]),\n .I3(Q[1]),\n .I4(Q[3]),\n .O(\\my_full[3]_i_4__0_n_0 ));\n (* syn_maxfan = \"3\" *) \n FDRE \\my_full_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_full[3]_i_1__0_n_0 ),\n .Q(\\my_full_reg_n_0_[3] ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair961\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_17\n (.I0(\\rd_ptr_reg[3]_0 [9]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D5[1]));\n (* SOFT_HLUTNM = \"soft_lutpair967\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_18__1\n (.I0(\\rd_ptr_reg[3]_0 [8]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D5[0]));\n (* SOFT_HLUTNM = \"soft_lutpair955\" *) \n LUT3 #(\n .INIT(8'h0D)) \n out_fifo_i_1__1\n (.I0(\\my_empty_reg[1]_0 ),\n .I1(mux_cmd_wren),\n .I2(B_of_full),\n .O(\\my_full_reg[3]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair963\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_23\n (.I0(\\rd_ptr_reg[3]_0 [13]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D6[3]));\n (* SOFT_HLUTNM = \"soft_lutpair967\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_24__0\n (.I0(\\rd_ptr_reg[3]_0 [12]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D6[2]));\n (* SOFT_HLUTNM = \"soft_lutpair962\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_25\n (.I0(\\rd_ptr_reg[3]_0 [11]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D6[1]));\n (* SOFT_HLUTNM = \"soft_lutpair965\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_26__0\n (.I0(\\rd_ptr_reg[3]_0 [10]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D6[0]));\n (* SOFT_HLUTNM = \"soft_lutpair968\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_27__0\n (.I0(\\rd_ptr_reg[3]_0 [17]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D7[3]));\n (* SOFT_HLUTNM = \"soft_lutpair964\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_28__0\n (.I0(\\rd_ptr_reg[3]_0 [16]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D7[2]));\n (* SOFT_HLUTNM = \"soft_lutpair960\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_29__0\n (.I0(\\rd_ptr_reg[3]_0 [15]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D7[1]));\n (* SOFT_HLUTNM = \"soft_lutpair964\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_2__1\n (.I0(\\rd_ptr_reg[3]_0 [1]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[5]));\n (* SOFT_HLUTNM = \"soft_lutpair968\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_30\n (.I0(\\rd_ptr_reg[3]_0 [14]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D7[0]));\n (* SOFT_HLUTNM = \"soft_lutpair961\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_3__1\n (.I0(\\rd_ptr_reg[3]_0 [0]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[4]));\n (* SOFT_HLUTNM = \"soft_lutpair965\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_4__1\n (.I0(\\rd_ptr_reg[3]_0 [5]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair962\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_5__1\n (.I0(\\rd_ptr_reg[3]_0 [4]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair963\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_6__1\n (.I0(\\rd_ptr_reg[3]_0 [3]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair960\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_7__0\n (.I0(\\rd_ptr_reg[3]_0 [2]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair966\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_8__0\n (.I0(\\rd_ptr_reg[3]_0 [7]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D3[1]));\n (* SOFT_HLUTNM = \"soft_lutpair966\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_9__0\n (.I0(\\rd_ptr_reg[3]_0 [6]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D3[0]));\n LUT4 #(\n .INIT(16'h082A)) \n p_17_out\n (.I0(mux_cmd_wren),\n .I1(B_of_full),\n .I2(\\my_full_reg_n_0_[3] ),\n .I3(\\my_empty_reg[1]_0 ),\n .O(wr_en_5));\n (* SOFT_HLUTNM = \"soft_lutpair958\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\rd_ptr[0]_i_1 \n (.I0(\\rd_ptr_timing_reg[2]_0 ),\n .I1(\\rd_ptr_timing_reg[2]_3 ),\n .O(nxt_rd_ptr[0]));\n (* SOFT_HLUTNM = \"soft_lutpair958\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\rd_ptr[1]_i_1__0 \n (.I0(\\rd_ptr_timing_reg[2]_0 ),\n .I1(\\rd_ptr_timing_reg[2]_3 ),\n .I2(\\rd_ptr_timing_reg[2]_2 ),\n .O(nxt_rd_ptr[1]));\n (* SOFT_HLUTNM = \"soft_lutpair956\" *) \n LUT4 #(\n .INIT(16'hAA6A)) \n \\rd_ptr[2]_i_1__0 \n (.I0(\\rd_ptr_timing_reg[2]_1 ),\n .I1(\\rd_ptr_timing_reg[2]_3 ),\n .I2(\\rd_ptr_timing_reg[2]_2 ),\n .I3(\\rd_ptr_timing_reg[2]_0 ),\n .O(nxt_rd_ptr[2]));\n LUT2 #(\n .INIT(4'h1)) \n \\rd_ptr[3]_i_1__0 \n (.I0(\\my_empty_reg_n_0_[6] ),\n .I1(B_of_full),\n .O(\\rd_ptr[3]_i_1__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair956\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\rd_ptr[3]_i_2 \n (.I0(\\rd_ptr_timing_reg[2]_0 ),\n .I1(\\rd_ptr_timing_reg[2]_2 ),\n .I2(\\rd_ptr_timing_reg[2]_3 ),\n .I3(\\rd_ptr_timing_reg[2]_1 ),\n .O(nxt_rd_ptr[3]));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[0] \n (.C(CLK),\n .CE(\\rd_ptr[3]_i_1__0_n_0 ),\n .D(nxt_rd_ptr[0]),\n .Q(\\rd_ptr_timing_reg[2]_3 ),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[1] \n (.C(CLK),\n .CE(\\rd_ptr[3]_i_1__0_n_0 ),\n .D(nxt_rd_ptr[1]),\n .Q(\\rd_ptr_timing_reg[2]_2 ),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[2] \n (.C(CLK),\n .CE(\\rd_ptr[3]_i_1__0_n_0 ),\n .D(nxt_rd_ptr[2]),\n .Q(\\rd_ptr_timing_reg[2]_1 ),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[3] \n (.C(CLK),\n .CE(\\rd_ptr[3]_i_1__0_n_0 ),\n .D(nxt_rd_ptr[3]),\n .Q(\\rd_ptr_timing_reg[2]_0 ),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[0] \n (.C(CLK),\n .CE(\\rd_ptr[3]_i_1__0_n_0 ),\n .D(nxt_rd_ptr[0]),\n .Q(rd_ptr_timing[0]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[1] \n (.C(CLK),\n .CE(\\rd_ptr[3]_i_1__0_n_0 ),\n .D(nxt_rd_ptr[1]),\n .Q(rd_ptr_timing[1]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[2] \n (.C(CLK),\n .CE(\\rd_ptr[3]_i_1__0_n_0 ),\n .D(nxt_rd_ptr[2]),\n .Q(rd_ptr_timing[2]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[3] \n (.C(CLK),\n .CE(\\rd_ptr[3]_i_1__0_n_0 ),\n .D(nxt_rd_ptr[3]),\n .Q(rd_ptr_timing[3]),\n .R(SR));\n LUT4 #(\n .INIT(16'h082A)) \n wr_ptr0\n (.I0(mux_cmd_wren),\n .I1(B_of_full),\n .I2(\\my_full_reg_n_0_[3] ),\n .I3(\\my_empty_reg_n_0_[6] ),\n .O(wr_ptr0__0));\n (* SOFT_HLUTNM = \"soft_lutpair959\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\wr_ptr[0]_i_1__0 \n (.I0(Q[3]),\n .I1(Q[0]),\n .O(nxt_wr_ptr[0]));\n (* SOFT_HLUTNM = \"soft_lutpair959\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\wr_ptr[1]_i_1__0 \n (.I0(Q[3]),\n .I1(Q[0]),\n .I2(Q[1]),\n .O(nxt_wr_ptr[1]));\n (* SOFT_HLUTNM = \"soft_lutpair957\" *) \n LUT4 #(\n .INIT(16'hAA6A)) \n \\wr_ptr[2]_i_1__0 \n (.I0(Q[2]),\n .I1(Q[0]),\n .I2(Q[1]),\n .I3(Q[3]),\n .O(nxt_wr_ptr[2]));\n (* SOFT_HLUTNM = \"soft_lutpair957\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\wr_ptr[3]_i_1__0 \n (.I0(Q[3]),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(Q[2]),\n .O(nxt_wr_ptr[3]));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[0] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[0]),\n .Q(Q[0]),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[1] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[1]),\n .Q(Q[1]),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[2] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[2]),\n .Q(Q[2]),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[3] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[3]),\n .Q(Q[3]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[0] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[0]),\n .Q(wr_ptr_timing[0]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[1] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[1]),\n .Q(wr_ptr_timing[1]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[2] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[2]),\n .Q(wr_ptr_timing[2]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[3] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[3]),\n .Q(wr_ptr_timing[3]),\n .R(SR));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_of_pre_fifo\" *) \nmodule ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized8\n (\\rd_ptr_timing_reg[2]_0 ,\n \\rd_ptr_timing_reg[2]_1 ,\n \\rd_ptr_timing_reg[2]_2 ,\n \\rd_ptr_timing_reg[2]_3 ,\n wr_en_6,\n \\my_empty_reg[1]_0 ,\n D2,\n D3,\n \\rd_ptr_timing_reg[0]_0 ,\n D0,\n D1,\n D4,\n D7,\n D8,\n D9,\n Q,\n SR,\n CLK,\n mux_cmd_wren,\n ofifo_rst_reg,\n \\rd_ptr_reg[3]_0 );\n output \\rd_ptr_timing_reg[2]_0 ;\n output \\rd_ptr_timing_reg[2]_1 ;\n output \\rd_ptr_timing_reg[2]_2 ;\n output \\rd_ptr_timing_reg[2]_3 ;\n output wr_en_6;\n output \\my_empty_reg[1]_0 ;\n output [4:0]D2;\n output [4:0]D3;\n output \\rd_ptr_timing_reg[0]_0 ;\n output [5:0]D0;\n output [3:0]D1;\n output [3:0]D4;\n output [3:0]D7;\n output [3:0]D8;\n output [1:0]D9;\n output [3:0]Q;\n input [0:0]SR;\n input CLK;\n input mux_cmd_wren;\n input ofifo_rst_reg;\n input [33:0]\\rd_ptr_reg[3]_0 ;\n\n wire CLK;\n wire [5:0]D0;\n wire [3:0]D1;\n wire [4:0]D2;\n wire [4:0]D3;\n wire [3:0]D4;\n wire [3:0]D7;\n wire [3:0]D8;\n wire [1:0]D9;\n wire [3:0]Q;\n wire [0:0]SR;\n wire mux_cmd_wren;\n wire my_empty0;\n wire \\my_empty[1]_i_1__5_n_0 ;\n wire \\my_empty[6]_i_1__0_n_0 ;\n wire \\my_empty[6]_i_3__1_n_0 ;\n wire \\my_empty[6]_i_4__1_n_0 ;\n wire \\my_empty_reg[1]_0 ;\n wire \\my_empty_reg_n_0_[6] ;\n wire my_full0;\n wire \\my_full[3]_i_1__1_n_0 ;\n wire \\my_full[3]_i_3__1_n_0 ;\n wire \\my_full[3]_i_4__1_n_0 ;\n wire \\my_full_reg_n_0_[3] ;\n wire [3:0]nxt_rd_ptr;\n wire [3:0]nxt_wr_ptr;\n wire ofifo_rst_reg;\n wire \\rd_ptr[3]_i_1__1_n_0 ;\n wire [33:0]\\rd_ptr_reg[3]_0 ;\n wire [3:0]rd_ptr_timing;\n wire \\rd_ptr_timing_reg[0]_0 ;\n wire \\rd_ptr_timing_reg[2]_0 ;\n wire \\rd_ptr_timing_reg[2]_1 ;\n wire \\rd_ptr_timing_reg[2]_2 ;\n wire \\rd_ptr_timing_reg[2]_3 ;\n wire wr_en_6;\n wire wr_ptr0__0;\n wire [3:0]wr_ptr_timing;\n\n (* SOFT_HLUTNM = \"soft_lutpair971\" *) \n LUT5 #(\n .INIT(32'hC0F0F0F2)) \n \\my_empty[1]_i_1__5 \n (.I0(my_empty0),\n .I1(\\my_full_reg_n_0_[3] ),\n .I2(\\my_empty_reg[1]_0 ),\n .I3(ofifo_rst_reg),\n .I4(mux_cmd_wren),\n .O(\\my_empty[1]_i_1__5_n_0 ));\n LUT5 #(\n .INIT(32'hC0F0F0F2)) \n \\my_empty[6]_i_1__0 \n (.I0(my_empty0),\n .I1(\\my_full_reg_n_0_[3] ),\n .I2(\\my_empty_reg_n_0_[6] ),\n .I3(ofifo_rst_reg),\n .I4(mux_cmd_wren),\n .O(\\my_empty[6]_i_1__0_n_0 ));\n LUT5 #(\n .INIT(32'h4A400D08)) \n \\my_empty[6]_i_2__1 \n (.I0(wr_ptr_timing[2]),\n .I1(\\my_empty[6]_i_3__1_n_0 ),\n .I2(wr_ptr_timing[3]),\n .I3(\\my_empty[6]_i_4__1_n_0 ),\n .I4(\\rd_ptr_timing_reg[2]_1 ),\n .O(my_empty0));\n (* SOFT_HLUTNM = \"soft_lutpair969\" *) \n LUT5 #(\n .INIT(32'h00000040)) \n \\my_empty[6]_i_3__1 \n (.I0(wr_ptr_timing[1]),\n .I1(\\rd_ptr_timing_reg[2]_3 ),\n .I2(\\rd_ptr_timing_reg[2]_2 ),\n .I3(\\rd_ptr_timing_reg[2]_0 ),\n .I4(wr_ptr_timing[0]),\n .O(\\my_empty[6]_i_3__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair969\" *) \n LUT5 #(\n .INIT(32'h84210842)) \n \\my_empty[6]_i_4__1 \n (.I0(wr_ptr_timing[0]),\n .I1(wr_ptr_timing[1]),\n .I2(\\rd_ptr_timing_reg[2]_3 ),\n .I3(\\rd_ptr_timing_reg[2]_2 ),\n .I4(\\rd_ptr_timing_reg[2]_0 ),\n .O(\\my_empty[6]_i_4__1_n_0 ));\n (* syn_maxfan = \"3\" *) \n FDSE \\my_empty_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_empty[1]_i_1__5_n_0 ),\n .Q(\\my_empty_reg[1]_0 ),\n .S(SR));\n (* syn_maxfan = \"3\" *) \n FDSE \\my_empty_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_empty[6]_i_1__0_n_0 ),\n .Q(\\my_empty_reg_n_0_[6] ),\n .S(SR));\n LUT6 #(\n .INIT(64'h00000000FF00FC80)) \n \\my_full[3]_i_1__1 \n (.I0(my_full0),\n .I1(mux_cmd_wren),\n .I2(ofifo_rst_reg),\n .I3(\\my_full_reg_n_0_[3] ),\n .I4(\\my_empty_reg_n_0_[6] ),\n .I5(SR),\n .O(\\my_full[3]_i_1__1_n_0 ));\n LUT5 #(\n .INIT(32'h4A400D08)) \n \\my_full[3]_i_2__1 \n (.I0(rd_ptr_timing[2]),\n .I1(\\my_full[3]_i_3__1_n_0 ),\n .I2(rd_ptr_timing[3]),\n .I3(\\my_full[3]_i_4__1_n_0 ),\n .I4(Q[2]),\n .O(my_full0));\n (* SOFT_HLUTNM = \"soft_lutpair970\" *) \n LUT5 #(\n .INIT(32'h00000040)) \n \\my_full[3]_i_3__1 \n (.I0(rd_ptr_timing[1]),\n .I1(Q[0]),\n .I2(Q[1]),\n .I3(Q[3]),\n .I4(rd_ptr_timing[0]),\n .O(\\my_full[3]_i_3__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair970\" *) \n LUT5 #(\n .INIT(32'h84210842)) \n \\my_full[3]_i_4__1 \n (.I0(rd_ptr_timing[0]),\n .I1(rd_ptr_timing[1]),\n .I2(Q[0]),\n .I3(Q[1]),\n .I4(Q[3]),\n .O(\\my_full[3]_i_4__1_n_0 ));\n (* syn_maxfan = \"3\" *) \n FDRE \\my_full_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_full[3]_i_1__1_n_0 ),\n .Q(\\my_full_reg_n_0_[3] ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair985\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_10__1\n (.I0(\\rd_ptr_reg[3]_0 [7]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D1[1]));\n (* SOFT_HLUTNM = \"soft_lutpair979\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_11__1\n (.I0(\\rd_ptr_reg[3]_0 [6]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D1[0]));\n (* SOFT_HLUTNM = \"soft_lutpair986\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_12__1\n (.I0(\\rd_ptr_reg[3]_0 [14]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D2[4]));\n (* SOFT_HLUTNM = \"soft_lutpair982\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_13__1\n (.I0(\\rd_ptr_reg[3]_0 [13]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D2[3]));\n (* SOFT_HLUTNM = \"soft_lutpair979\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_14__0\n (.I0(\\rd_ptr_reg[3]_0 [12]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D2[2]));\n (* SOFT_HLUTNM = \"soft_lutpair981\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_15\n (.I0(\\rd_ptr_reg[3]_0 [11]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D2[1]));\n (* SOFT_HLUTNM = \"soft_lutpair978\" *) \n LUT2 #(\n .INIT(4'hE)) \n out_fifo_i_16\n (.I0(\\rd_ptr_reg[3]_0 [10]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D2[0]));\n (* SOFT_HLUTNM = \"soft_lutpair971\" *) \n LUT3 #(\n .INIT(8'h0D)) \n out_fifo_i_1__2\n (.I0(\\my_empty_reg[1]_0 ),\n .I1(mux_cmd_wren),\n .I2(ofifo_rst_reg),\n .O(\\rd_ptr_timing_reg[0]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair989\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_20__0\n (.I0(\\rd_ptr_reg[3]_0 [19]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D3[4]));\n (* SOFT_HLUTNM = \"soft_lutpair982\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_21__0\n (.I0(\\rd_ptr_reg[3]_0 [18]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D3[3]));\n (* SOFT_HLUTNM = \"soft_lutpair990\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_22\n (.I0(\\rd_ptr_reg[3]_0 [17]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D3[2]));\n (* SOFT_HLUTNM = \"soft_lutpair981\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_23__0\n (.I0(\\rd_ptr_reg[3]_0 [16]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D3[1]));\n (* SOFT_HLUTNM = \"soft_lutpair988\" *) \n LUT2 #(\n .INIT(4'hE)) \n out_fifo_i_24\n (.I0(\\rd_ptr_reg[3]_0 [15]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D3[0]));\n (* SOFT_HLUTNM = \"soft_lutpair991\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_28__1\n (.I0(\\rd_ptr_reg[3]_0 [23]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D4[3]));\n (* SOFT_HLUTNM = \"soft_lutpair976\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_29__1\n (.I0(\\rd_ptr_reg[3]_0 [22]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D4[2]));\n (* SOFT_HLUTNM = \"soft_lutpair983\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_2__2\n (.I0(\\rd_ptr_reg[3]_0 [1]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[5]));\n (* SOFT_HLUTNM = \"soft_lutpair992\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_30__0\n (.I0(\\rd_ptr_reg[3]_0 [21]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D4[1]));\n (* SOFT_HLUTNM = \"soft_lutpair986\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_31\n (.I0(\\rd_ptr_reg[3]_0 [20]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D4[0]));\n (* SOFT_HLUTNM = \"soft_lutpair978\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_3__2\n (.I0(\\rd_ptr_reg[3]_0 [0]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[4]));\n (* SOFT_HLUTNM = \"soft_lutpair985\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_4__2\n (.I0(\\rd_ptr_reg[3]_0 [5]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair991\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_52__0\n (.I0(\\rd_ptr_reg[3]_0 [27]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D7[3]));\n (* SOFT_HLUTNM = \"soft_lutpair980\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_53__0\n (.I0(\\rd_ptr_reg[3]_0 [26]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D7[2]));\n (* SOFT_HLUTNM = \"soft_lutpair988\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_54\n (.I0(\\rd_ptr_reg[3]_0 [25]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D7[1]));\n (* SOFT_HLUTNM = \"soft_lutpair984\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_55\n (.I0(\\rd_ptr_reg[3]_0 [24]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D7[0]));\n (* SOFT_HLUTNM = \"soft_lutpair980\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_5__2\n (.I0(\\rd_ptr_reg[3]_0 [4]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair989\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_60__0\n (.I0(\\rd_ptr_reg[3]_0 [31]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D8[3]));\n (* SOFT_HLUTNM = \"soft_lutpair987\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_61__0\n (.I0(\\rd_ptr_reg[3]_0 [30]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D8[2]));\n (* SOFT_HLUTNM = \"soft_lutpair992\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_62\n (.I0(\\rd_ptr_reg[3]_0 [29]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D8[1]));\n (* SOFT_HLUTNM = \"soft_lutpair977\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_63\n (.I0(\\rd_ptr_reg[3]_0 [28]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D8[0]));\n (* SOFT_HLUTNM = \"soft_lutpair990\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_68__0\n (.I0(\\rd_ptr_reg[3]_0 [33]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D9[1]));\n (* SOFT_HLUTNM = \"soft_lutpair987\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_69__0\n (.I0(\\rd_ptr_reg[3]_0 [32]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D9[0]));\n (* SOFT_HLUTNM = \"soft_lutpair983\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_6__2\n (.I0(\\rd_ptr_reg[3]_0 [3]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair976\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_7__1\n (.I0(\\rd_ptr_reg[3]_0 [2]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair984\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_8__1\n (.I0(\\rd_ptr_reg[3]_0 [9]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D1[3]));\n (* SOFT_HLUTNM = \"soft_lutpair977\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_9__1\n (.I0(\\rd_ptr_reg[3]_0 [8]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D1[2]));\n LUT4 #(\n .INIT(16'h082A)) \n p_17_out\n (.I0(mux_cmd_wren),\n .I1(ofifo_rst_reg),\n .I2(\\my_full_reg_n_0_[3] ),\n .I3(\\my_empty_reg[1]_0 ),\n .O(wr_en_6));\n (* SOFT_HLUTNM = \"soft_lutpair975\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\rd_ptr[0]_i_1__0 \n (.I0(\\rd_ptr_timing_reg[2]_0 ),\n .I1(\\rd_ptr_timing_reg[2]_3 ),\n .O(nxt_rd_ptr[0]));\n (* SOFT_HLUTNM = \"soft_lutpair975\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\rd_ptr[1]_i_1__1 \n (.I0(\\rd_ptr_timing_reg[2]_0 ),\n .I1(\\rd_ptr_timing_reg[2]_3 ),\n .I2(\\rd_ptr_timing_reg[2]_2 ),\n .O(nxt_rd_ptr[1]));\n (* SOFT_HLUTNM = \"soft_lutpair972\" *) \n LUT4 #(\n .INIT(16'hAA6A)) \n \\rd_ptr[2]_i_1__1 \n (.I0(\\rd_ptr_timing_reg[2]_1 ),\n .I1(\\rd_ptr_timing_reg[2]_3 ),\n .I2(\\rd_ptr_timing_reg[2]_2 ),\n .I3(\\rd_ptr_timing_reg[2]_0 ),\n .O(nxt_rd_ptr[2]));\n LUT2 #(\n .INIT(4'h1)) \n \\rd_ptr[3]_i_1__1 \n (.I0(\\my_empty_reg_n_0_[6] ),\n .I1(ofifo_rst_reg),\n .O(\\rd_ptr[3]_i_1__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair972\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\rd_ptr[3]_i_2__0 \n (.I0(\\rd_ptr_timing_reg[2]_0 ),\n .I1(\\rd_ptr_timing_reg[2]_2 ),\n .I2(\\rd_ptr_timing_reg[2]_3 ),\n .I3(\\rd_ptr_timing_reg[2]_1 ),\n .O(nxt_rd_ptr[3]));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[0] \n (.C(CLK),\n .CE(\\rd_ptr[3]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[0]),\n .Q(\\rd_ptr_timing_reg[2]_3 ),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[1] \n (.C(CLK),\n .CE(\\rd_ptr[3]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[1]),\n .Q(\\rd_ptr_timing_reg[2]_2 ),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[2] \n (.C(CLK),\n .CE(\\rd_ptr[3]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[2]),\n .Q(\\rd_ptr_timing_reg[2]_1 ),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[3] \n (.C(CLK),\n .CE(\\rd_ptr[3]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[3]),\n .Q(\\rd_ptr_timing_reg[2]_0 ),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[0] \n (.C(CLK),\n .CE(\\rd_ptr[3]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[0]),\n .Q(rd_ptr_timing[0]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[1] \n (.C(CLK),\n .CE(\\rd_ptr[3]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[1]),\n .Q(rd_ptr_timing[1]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[2] \n (.C(CLK),\n .CE(\\rd_ptr[3]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[2]),\n .Q(rd_ptr_timing[2]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[3] \n (.C(CLK),\n .CE(\\rd_ptr[3]_i_1__1_n_0 ),\n .D(nxt_rd_ptr[3]),\n .Q(rd_ptr_timing[3]),\n .R(SR));\n LUT4 #(\n .INIT(16'h082A)) \n wr_ptr0\n (.I0(mux_cmd_wren),\n .I1(ofifo_rst_reg),\n .I2(\\my_full_reg_n_0_[3] ),\n .I3(\\my_empty_reg_n_0_[6] ),\n .O(wr_ptr0__0));\n (* SOFT_HLUTNM = \"soft_lutpair974\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\wr_ptr[0]_i_1__1 \n (.I0(Q[3]),\n .I1(Q[0]),\n .O(nxt_wr_ptr[0]));\n (* SOFT_HLUTNM = \"soft_lutpair974\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\wr_ptr[1]_i_1__1 \n (.I0(Q[3]),\n .I1(Q[0]),\n .I2(Q[1]),\n .O(nxt_wr_ptr[1]));\n (* SOFT_HLUTNM = \"soft_lutpair973\" *) \n LUT4 #(\n .INIT(16'hAA6A)) \n \\wr_ptr[2]_i_1__1 \n (.I0(Q[2]),\n .I1(Q[0]),\n .I2(Q[1]),\n .I3(Q[3]),\n .O(nxt_wr_ptr[2]));\n (* SOFT_HLUTNM = \"soft_lutpair973\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\wr_ptr[3]_i_1__1 \n (.I0(Q[3]),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(Q[2]),\n .O(nxt_wr_ptr[3]));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[0] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[0]),\n .Q(Q[0]),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[1] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[1]),\n .Q(Q[1]),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[2] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[2]),\n .Q(Q[2]),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[3] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[3]),\n .Q(Q[3]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[0] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[0]),\n .Q(wr_ptr_timing[0]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[1] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[1]),\n .Q(wr_ptr_timing[1]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[2] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[2]),\n .Q(wr_ptr_timing[2]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[3] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[3]),\n .Q(wr_ptr_timing[3]),\n .R(SR));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_of_pre_fifo\" *) \nmodule ddr3_if_mig_7series_v4_0_ddr_of_pre_fifo__parameterized9\n (D9,\n \\my_empty_reg[1]_0 ,\n \\my_empty_reg[7]_0 ,\n D0,\n D1,\n D2,\n D3,\n D4,\n D5,\n D6,\n D7,\n D8,\n \\my_empty_reg[7]_1 ,\n SR,\n CLK,\n init_calib_complete_reg_rep__5,\n mc_cas_n,\n \\cmd_pipe_plus.mc_address_reg[43] ,\n init_calib_complete_reg_rep,\n mux_cmd_wren,\n ofifo_rst_reg,\n phy_dout,\n init_calib_complete_reg_rep__6);\n output [7:0]D9;\n output \\my_empty_reg[1]_0 ;\n output \\my_empty_reg[7]_0 ;\n output [5:0]D0;\n output [3:0]D1;\n output [3:0]D2;\n output [3:0]D3;\n output [3:0]D4;\n output [3:0]D5;\n output [3:0]D6;\n output [3:0]D7;\n output [3:0]D8;\n output [31:0]\\my_empty_reg[7]_1 ;\n input [0:0]SR;\n input CLK;\n input init_calib_complete_reg_rep__5;\n input [0:0]mc_cas_n;\n input [1:0]\\cmd_pipe_plus.mc_address_reg[43] ;\n input init_calib_complete_reg_rep;\n input mux_cmd_wren;\n input ofifo_rst_reg;\n input [35:0]phy_dout;\n input init_calib_complete_reg_rep__6;\n\n wire CLK;\n wire [5:0]D0;\n wire [3:0]D1;\n wire [3:0]D2;\n wire [3:0]D3;\n wire [3:0]D4;\n wire [3:0]D5;\n wire [3:0]D6;\n wire [3:0]D7;\n wire [3:0]D8;\n wire [7:0]D9;\n wire [0:0]SR;\n wire [1:0]\\cmd_pipe_plus.mc_address_reg[43] ;\n wire init_calib_complete_reg_rep;\n wire init_calib_complete_reg_rep__5;\n wire init_calib_complete_reg_rep__6;\n wire [0:0]mc_cas_n;\n wire [77:0]mem_out;\n wire mux_cmd_wren;\n wire my_empty0;\n wire \\my_empty[1]_i_1_n_0 ;\n wire \\my_empty[7]_i_1_n_0 ;\n wire \\my_empty[7]_i_3_n_0 ;\n wire \\my_empty[7]_i_4_n_0 ;\n wire \\my_empty_reg[1]_0 ;\n wire \\my_empty_reg[7]_0 ;\n wire [31:0]\\my_empty_reg[7]_1 ;\n wire \\my_empty_reg_n_0_[7] ;\n wire my_full0;\n wire \\my_full[4]_i_1_n_0 ;\n wire \\my_full[4]_i_3_n_0 ;\n wire \\my_full[4]_i_4_n_0 ;\n wire \\my_full_reg_n_0_[4] ;\n wire [3:0]nxt_rd_ptr;\n wire [3:0]nxt_wr_ptr;\n wire ofifo_rst_reg;\n wire [35:0]phy_dout;\n wire [3:0]rd_ptr;\n wire [3:0]rd_ptr_timing;\n wire \\rd_ptr_timing[3]_i_1_n_0 ;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) wire wr_en;\n wire [3:0]wr_ptr;\n wire wr_ptr0__0;\n wire [3:0]wr_ptr_timing;\n wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED;\n wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED;\n\n (* SOFT_HLUTNM = \"soft_lutpair1003\" *) \n LUT3 #(\n .INIT(8'hAC)) \n d_out\n (.I0(init_calib_complete_reg_rep__6),\n .I1(mem_out[75]),\n .I2(\\my_empty_reg[1]_0 ),\n .O(D9[3]));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_0_5\n (.ADDRA({1'b0,rd_ptr}),\n .ADDRB({1'b0,rd_ptr}),\n .ADDRC({1'b0,rd_ptr}),\n .ADDRD({1'b0,wr_ptr}),\n .DIA({1'b0,1'b0}),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[1:0]),\n .DOB(mem_out[3:2]),\n .DOC(mem_out[5:4]),\n .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_12_17\n (.ADDRA({1'b0,rd_ptr}),\n .ADDRB({1'b0,rd_ptr}),\n .ADDRC({1'b0,rd_ptr}),\n .ADDRD({1'b0,wr_ptr}),\n .DIA({1'b0,1'b0}),\n .DIB({1'b0,1'b0}),\n .DIC(phy_dout[5:4]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[13:12]),\n .DOB(mem_out[15:14]),\n .DOC(\\my_empty_reg[7]_1 [5:4]),\n .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_18_23\n (.ADDRA({1'b0,rd_ptr}),\n .ADDRB({1'b0,rd_ptr}),\n .ADDRC({1'b0,rd_ptr}),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[7:6]),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [7:6]),\n .DOB(mem_out[21:20]),\n .DOC(mem_out[23:22]),\n .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_24_29\n (.ADDRA({1'b0,rd_ptr}),\n .ADDRB({1'b0,rd_ptr}),\n .ADDRC({1'b0,rd_ptr}),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[9:8]),\n .DIB(phy_dout[11:10]),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [9:8]),\n .DOB(\\my_empty_reg[7]_1 [11:10]),\n .DOC(mem_out[29:28]),\n .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_30_35\n (.ADDRA({1'b0,rd_ptr}),\n .ADDRB({1'b0,rd_ptr}),\n .ADDRC({1'b0,rd_ptr}),\n .ADDRD({1'b0,wr_ptr}),\n .DIA({1'b0,1'b0}),\n .DIB(phy_dout[13:12]),\n .DIC(phy_dout[15:14]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[31:30]),\n .DOB(\\my_empty_reg[7]_1 [13:12]),\n .DOC(\\my_empty_reg[7]_1 [15:14]),\n .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_36_41\n (.ADDRA({1'b0,rd_ptr}),\n .ADDRB({1'b0,rd_ptr}),\n .ADDRC({1'b0,rd_ptr}),\n .ADDRD({1'b0,wr_ptr}),\n .DIA({1'b0,1'b0}),\n .DIB({1'b0,1'b0}),\n .DIC(phy_dout[17:16]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[37:36]),\n .DOB(mem_out[39:38]),\n .DOC(\\my_empty_reg[7]_1 [17:16]),\n .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_42_47\n (.ADDRA({1'b0,rd_ptr}),\n .ADDRB({1'b0,rd_ptr}),\n .ADDRC({1'b0,rd_ptr}),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[19:18]),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [19:18]),\n .DOB(mem_out[45:44]),\n .DOC(mem_out[47:46]),\n .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_48_53\n (.ADDRA({1'b0,rd_ptr}),\n .ADDRB({1'b0,rd_ptr}),\n .ADDRC({1'b0,rd_ptr}),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[21:20]),\n .DIB(phy_dout[23:22]),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [21:20]),\n .DOB(\\my_empty_reg[7]_1 [23:22]),\n .DOC(mem_out[53:52]),\n .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_54_59\n (.ADDRA({1'b0,rd_ptr}),\n .ADDRB({1'b0,rd_ptr}),\n .ADDRC({1'b0,rd_ptr}),\n .ADDRD({1'b0,wr_ptr}),\n .DIA({1'b0,1'b0}),\n .DIB(phy_dout[25:24]),\n .DIC(phy_dout[27:26]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[55:54]),\n .DOB(\\my_empty_reg[7]_1 [25:24]),\n .DOC(\\my_empty_reg[7]_1 [27:26]),\n .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_60_65\n (.ADDRA({1'b0,rd_ptr}),\n .ADDRB({1'b0,rd_ptr}),\n .ADDRC({1'b0,rd_ptr}),\n .ADDRD({1'b0,wr_ptr}),\n .DIA({1'b0,1'b0}),\n .DIB({1'b0,1'b0}),\n .DIC(phy_dout[29:28]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[61:60]),\n .DOB(mem_out[63:62]),\n .DOC(\\my_empty_reg[7]_1 [29:28]),\n .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_66_71\n (.ADDRA({1'b0,rd_ptr}),\n .ADDRB({1'b0,rd_ptr}),\n .ADDRC({1'b0,rd_ptr}),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[31:30]),\n .DIB({1'b0,1'b0}),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(\\my_empty_reg[7]_1 [31:30]),\n .DOB(mem_out[69:68]),\n .DOC(mem_out[71:70]),\n .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_6_11\n (.ADDRA({1'b0,rd_ptr}),\n .ADDRB({1'b0,rd_ptr}),\n .ADDRC({1'b0,rd_ptr}),\n .ADDRD({1'b0,wr_ptr}),\n .DIA({1'b0,1'b0}),\n .DIB(phy_dout[1:0]),\n .DIC(phy_dout[3:2]),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[7:6]),\n .DOB(\\my_empty_reg[7]_1 [1:0]),\n .DOC(\\my_empty_reg[7]_1 [3:2]),\n .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n (* METHODOLOGY_DRC_VIOS = \"\" *) \n RAM32M mem_reg_0_15_72_77\n (.ADDRA({1'b0,rd_ptr}),\n .ADDRB({1'b0,rd_ptr}),\n .ADDRC({1'b0,rd_ptr}),\n .ADDRD({1'b0,wr_ptr}),\n .DIA(phy_dout[33:32]),\n .DIB(phy_dout[35:34]),\n .DIC({1'b0,1'b0}),\n .DID({1'b0,1'b0}),\n .DOA(mem_out[73:72]),\n .DOB(mem_out[75:74]),\n .DOC(mem_out[77:76]),\n .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]),\n .WCLK(CLK),\n .WE(wr_en));\n LUT6 #(\n .INIT(64'hFFFFFFFFF071F070)) \n \\my_empty[1]_i_1 \n (.I0(mux_cmd_wren),\n .I1(ofifo_rst_reg),\n .I2(\\my_empty_reg[1]_0 ),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(my_empty0),\n .I5(SR),\n .O(\\my_empty[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFF071F070)) \n \\my_empty[7]_i_1 \n (.I0(mux_cmd_wren),\n .I1(ofifo_rst_reg),\n .I2(\\my_empty_reg_n_0_[7] ),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(my_empty0),\n .I5(SR),\n .O(\\my_empty[7]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h4A400D08)) \n \\my_empty[7]_i_2 \n (.I0(wr_ptr_timing[2]),\n .I1(\\my_empty[7]_i_3_n_0 ),\n .I2(wr_ptr_timing[3]),\n .I3(\\my_empty[7]_i_4_n_0 ),\n .I4(rd_ptr[2]),\n .O(my_empty0));\n (* SOFT_HLUTNM = \"soft_lutpair993\" *) \n LUT5 #(\n .INIT(32'h00000040)) \n \\my_empty[7]_i_3 \n (.I0(wr_ptr_timing[1]),\n .I1(rd_ptr[0]),\n .I2(rd_ptr[1]),\n .I3(rd_ptr[3]),\n .I4(wr_ptr_timing[0]),\n .O(\\my_empty[7]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair993\" *) \n LUT5 #(\n .INIT(32'h84210842)) \n \\my_empty[7]_i_4 \n (.I0(wr_ptr_timing[0]),\n .I1(wr_ptr_timing[1]),\n .I2(rd_ptr[0]),\n .I3(rd_ptr[1]),\n .I4(rd_ptr[3]),\n .O(\\my_empty[7]_i_4_n_0 ));\n (* syn_maxfan = \"3\" *) \n FDRE \\my_empty_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_empty[1]_i_1_n_0 ),\n .Q(\\my_empty_reg[1]_0 ),\n .R(1'b0));\n (* syn_maxfan = \"3\" *) \n FDRE \\my_empty_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_empty[7]_i_1_n_0 ),\n .Q(\\my_empty_reg_n_0_[7] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000FF00FC80)) \n \\my_full[4]_i_1 \n (.I0(my_full0),\n .I1(mux_cmd_wren),\n .I2(ofifo_rst_reg),\n .I3(\\my_full_reg_n_0_[4] ),\n .I4(\\my_empty_reg_n_0_[7] ),\n .I5(SR),\n .O(\\my_full[4]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h4A400D08)) \n \\my_full[4]_i_2 \n (.I0(rd_ptr_timing[2]),\n .I1(\\my_full[4]_i_3_n_0 ),\n .I2(rd_ptr_timing[3]),\n .I3(\\my_full[4]_i_4_n_0 ),\n .I4(wr_ptr[2]),\n .O(my_full0));\n (* SOFT_HLUTNM = \"soft_lutpair994\" *) \n LUT5 #(\n .INIT(32'h00000040)) \n \\my_full[4]_i_3 \n (.I0(rd_ptr_timing[1]),\n .I1(wr_ptr[0]),\n .I2(wr_ptr[1]),\n .I3(wr_ptr[3]),\n .I4(rd_ptr_timing[0]),\n .O(\\my_full[4]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair994\" *) \n LUT5 #(\n .INIT(32'h84210842)) \n \\my_full[4]_i_4 \n (.I0(rd_ptr_timing[0]),\n .I1(rd_ptr_timing[1]),\n .I2(wr_ptr[0]),\n .I3(wr_ptr[1]),\n .I4(wr_ptr[3]),\n .O(\\my_full[4]_i_4_n_0 ));\n (* syn_maxfan = \"3\" *) \n FDRE \\my_full_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\my_full[4]_i_1_n_0 ),\n .Q(\\my_full_reg_n_0_[4] ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1001\" *) \n LUT3 #(\n .INIT(8'h0D)) \n out_fifo_i_1\n (.I0(\\my_empty_reg[1]_0 ),\n .I1(mux_cmd_wren),\n .I2(ofifo_rst_reg),\n .O(\\my_empty_reg[7]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1009\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_10\n (.I0(mem_out[15]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D1[3]));\n (* SOFT_HLUTNM = \"soft_lutpair998\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_11\n (.I0(mem_out[14]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D1[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1012\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_12\n (.I0(mem_out[13]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D1[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1003\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_13\n (.I0(mem_out[12]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D1[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1013\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_18\n (.I0(mem_out[23]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D2[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1006\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_19\n (.I0(mem_out[22]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D2[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1010\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_2\n (.I0(mem_out[7]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[5]));\n (* SOFT_HLUTNM = \"soft_lutpair1013\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_20\n (.I0(mem_out[21]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D2[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1005\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_21\n (.I0(mem_out[20]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D2[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1018\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_26\n (.I0(mem_out[31]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D3[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1006\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_27\n (.I0(mem_out[30]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D3[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1019\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_28\n (.I0(mem_out[29]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D3[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1008\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_29\n (.I0(mem_out[28]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D3[0]));\n (* SOFT_HLUTNM = \"soft_lutpair999\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_3\n (.I0(mem_out[6]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[4]));\n (* SOFT_HLUTNM = \"soft_lutpair1021\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_34\n (.I0(mem_out[39]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D4[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1007\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_35\n (.I0(mem_out[38]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D4[2]));\n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_36\n (.I0(mem_out[37]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D4[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1011\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_37\n (.I0(mem_out[36]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D4[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1011\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_4\n (.I0(mem_out[5]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1020\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_42\n (.I0(mem_out[47]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D5[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1009\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_43\n (.I0(mem_out[46]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D5[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1017\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_44\n (.I0(mem_out[45]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D5[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1007\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_45\n (.I0(mem_out[44]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D5[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1004\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_5\n (.I0(mem_out[4]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1017\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_50\n (.I0(mem_out[55]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D6[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1014\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_51\n (.I0(mem_out[54]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D6[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1018\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_52\n (.I0(mem_out[53]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D6[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1014\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_53\n (.I0(mem_out[52]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D6[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1015\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_58\n (.I0(mem_out[63]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D7[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1005\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_59\n (.I0(mem_out[62]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D7[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1008\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_6\n (.I0(mem_out[3]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1019\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_60\n (.I0(mem_out[61]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D7[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1010\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_61\n (.I0(mem_out[60]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D7[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1020\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_66\n (.I0(mem_out[71]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D8[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1015\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_67\n (.I0(mem_out[70]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D8[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1016\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_68\n (.I0(mem_out[69]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D8[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1004\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_69\n (.I0(mem_out[68]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D8[0]));\n (* SOFT_HLUTNM = \"soft_lutpair997\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_7\n (.I0(mem_out[2]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1021\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_74\n (.I0(mem_out[77]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D9[5]));\n (* SOFT_HLUTNM = \"soft_lutpair1016\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_75\n (.I0(mem_out[76]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D9[4]));\n (* SOFT_HLUTNM = \"soft_lutpair999\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_76\n (.I0(\\cmd_pipe_plus.mc_address_reg[43] [1]),\n .I1(init_calib_complete_reg_rep),\n .I2(mem_out[74]),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[2]));\n (* SOFT_HLUTNM = \"soft_lutpair998\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_77\n (.I0(init_calib_complete_reg_rep__5),\n .I1(mc_cas_n),\n .I2(mem_out[73]),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[1]));\n (* SOFT_HLUTNM = \"soft_lutpair997\" *) \n LUT4 #(\n .INIT(16'h88F0)) \n out_fifo_i_78\n (.I0(\\cmd_pipe_plus.mc_address_reg[43] [0]),\n .I1(init_calib_complete_reg_rep),\n .I2(mem_out[72]),\n .I3(\\my_empty_reg[1]_0 ),\n .O(D9[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1012\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_8\n (.I0(mem_out[1]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D9[7]));\n (* SOFT_HLUTNM = \"soft_lutpair1001\" *) \n LUT2 #(\n .INIT(4'h2)) \n out_fifo_i_9\n (.I0(mem_out[0]),\n .I1(\\my_empty_reg[1]_0 ),\n .O(D9[6]));\n LUT4 #(\n .INIT(16'h082A)) \n p_17_out\n (.I0(mux_cmd_wren),\n .I1(ofifo_rst_reg),\n .I2(\\my_full_reg_n_0_[4] ),\n .I3(\\my_empty_reg[1]_0 ),\n .O(wr_en));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[0] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1_n_0 ),\n .D(nxt_rd_ptr[0]),\n .Q(rd_ptr[0]),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[1] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1_n_0 ),\n .D(nxt_rd_ptr[1]),\n .Q(rd_ptr[1]),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[2] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1_n_0 ),\n .D(nxt_rd_ptr[2]),\n .Q(rd_ptr[2]),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_reg[3] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1_n_0 ),\n .D(nxt_rd_ptr[3]),\n .Q(rd_ptr[3]),\n .R(SR));\n (* SOFT_HLUTNM = \"soft_lutpair1002\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\rd_ptr_timing[0]_i_1 \n (.I0(rd_ptr[3]),\n .I1(rd_ptr[0]),\n .O(nxt_rd_ptr[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1002\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\rd_ptr_timing[1]_i_1 \n (.I0(rd_ptr[3]),\n .I1(rd_ptr[0]),\n .I2(rd_ptr[1]),\n .O(nxt_rd_ptr[1]));\n (* SOFT_HLUTNM = \"soft_lutpair996\" *) \n LUT4 #(\n .INIT(16'hAA6A)) \n \\rd_ptr_timing[2]_i_1 \n (.I0(rd_ptr[2]),\n .I1(rd_ptr[0]),\n .I2(rd_ptr[1]),\n .I3(rd_ptr[3]),\n .O(nxt_rd_ptr[2]));\n LUT2 #(\n .INIT(4'h1)) \n \\rd_ptr_timing[3]_i_1 \n (.I0(\\my_empty_reg_n_0_[7] ),\n .I1(ofifo_rst_reg),\n .O(\\rd_ptr_timing[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair996\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\rd_ptr_timing[3]_i_2 \n (.I0(rd_ptr[3]),\n .I1(rd_ptr[1]),\n .I2(rd_ptr[0]),\n .I3(rd_ptr[2]),\n .O(nxt_rd_ptr[3]));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[0] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1_n_0 ),\n .D(nxt_rd_ptr[0]),\n .Q(rd_ptr_timing[0]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[1] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1_n_0 ),\n .D(nxt_rd_ptr[1]),\n .Q(rd_ptr_timing[1]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[2] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1_n_0 ),\n .D(nxt_rd_ptr[2]),\n .Q(rd_ptr_timing[2]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\rd_ptr_timing_reg[3] \n (.C(CLK),\n .CE(\\rd_ptr_timing[3]_i_1_n_0 ),\n .D(nxt_rd_ptr[3]),\n .Q(rd_ptr_timing[3]),\n .R(SR));\n LUT4 #(\n .INIT(16'h082A)) \n wr_ptr0\n (.I0(mux_cmd_wren),\n .I1(ofifo_rst_reg),\n .I2(\\my_full_reg_n_0_[4] ),\n .I3(\\my_empty_reg_n_0_[7] ),\n .O(wr_ptr0__0));\n (* SOFT_HLUTNM = \"soft_lutpair1000\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\wr_ptr[0]_i_1 \n (.I0(wr_ptr[3]),\n .I1(wr_ptr[0]),\n .O(nxt_wr_ptr[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1000\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\wr_ptr[1]_i_1 \n (.I0(wr_ptr[3]),\n .I1(wr_ptr[0]),\n .I2(wr_ptr[1]),\n .O(nxt_wr_ptr[1]));\n (* SOFT_HLUTNM = \"soft_lutpair995\" *) \n LUT4 #(\n .INIT(16'hAA6A)) \n \\wr_ptr[2]_i_1 \n (.I0(wr_ptr[2]),\n .I1(wr_ptr[0]),\n .I2(wr_ptr[1]),\n .I3(wr_ptr[3]),\n .O(nxt_wr_ptr[2]));\n (* SOFT_HLUTNM = \"soft_lutpair995\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\wr_ptr[3]_i_1 \n (.I0(wr_ptr[3]),\n .I1(wr_ptr[1]),\n .I2(wr_ptr[0]),\n .I3(wr_ptr[2]),\n .O(nxt_wr_ptr[3]));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[0] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[0]),\n .Q(wr_ptr[0]),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[1] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[1]),\n .Q(wr_ptr[1]),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[2] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[2]),\n .Q(wr_ptr[2]),\n .R(SR));\n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_reg[3] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[3]),\n .Q(wr_ptr[3]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[0] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[0]),\n .Q(wr_ptr_timing[0]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[1] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[1]),\n .Q(wr_ptr_timing[1]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[2] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[2]),\n .Q(wr_ptr_timing[2]),\n .R(SR));\n (* KEEP = \"yes\" *) \n (* MAX_FANOUT = \"50\" *) \n (* syn_maxfan = \"10\" *) \n FDRE \\wr_ptr_timing_reg[3] \n (.C(CLK),\n .CE(wr_ptr0__0),\n .D(nxt_wr_ptr[3]),\n .Q(wr_ptr_timing[3]),\n .R(SR));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_ddr_phy_4lanes\n (\\pi_dqs_found_lanes_r1_reg[3] ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,\n mem_dqs_out,\n mem_dqs_ts,\n mem_dq_out,\n mem_dq_ts,\n idelay_ld_rst,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,\n idelay_ld_rst_0,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,\n idelay_ld_rst_1,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,\n idelay_ld_rst_2,\n _phy_ctl_full_p__0,\n rst_primitives_reg_0,\n rst_primitives,\n mcGo_reg_0,\n rclk_delay_11,\n \\not_strict_mode.app_rd_data_reg[252] ,\n \\not_strict_mode.app_rd_data_reg[244] ,\n \\not_strict_mode.app_rd_data_reg[236] ,\n \\not_strict_mode.app_rd_data_reg[228] ,\n \\my_empty_reg[1] ,\n \\my_empty_reg[1]_0 ,\n \\my_empty_reg[1]_1 ,\n \\my_empty_reg[1]_2 ,\n \\mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13 ,\n rd_buf_we,\n \\not_strict_mode.status_ram.rd_buf_we_r1_reg ,\n phy_rddata_en,\n mux_rd_valid_r_reg,\n rst_sync_r1_reg,\n \\data_bytes_r_reg[63] ,\n \\not_strict_mode.app_rd_data_reg[255] ,\n \\not_strict_mode.app_rd_data_reg[239] ,\n \\not_strict_mode.app_rd_data_reg[247] ,\n \\not_strict_mode.app_rd_data_reg[231] ,\n \\not_strict_mode.app_rd_data_reg[254] ,\n \\not_strict_mode.app_rd_data_reg[238] ,\n \\not_strict_mode.app_rd_data_reg[246] ,\n \\not_strict_mode.app_rd_data_reg[230] ,\n \\not_strict_mode.app_rd_data_reg[253] ,\n \\not_strict_mode.app_rd_data_reg[237] ,\n \\not_strict_mode.app_rd_data_reg[245] ,\n \\not_strict_mode.app_rd_data_reg[229] ,\n \\not_strict_mode.app_rd_data_reg[252]_0 ,\n \\not_strict_mode.app_rd_data_reg[236]_0 ,\n \\not_strict_mode.app_rd_data_reg[244]_0 ,\n \\not_strict_mode.app_rd_data_reg[228]_0 ,\n \\not_strict_mode.app_rd_data_reg[251] ,\n \\not_strict_mode.app_rd_data_reg[235] ,\n \\not_strict_mode.app_rd_data_reg[243] ,\n \\not_strict_mode.app_rd_data_reg[227] ,\n \\not_strict_mode.app_rd_data_reg[250] ,\n \\not_strict_mode.app_rd_data_reg[234] ,\n \\not_strict_mode.app_rd_data_reg[242] ,\n \\not_strict_mode.app_rd_data_reg[226] ,\n \\not_strict_mode.app_rd_data_reg[249] ,\n \\not_strict_mode.app_rd_data_reg[233] ,\n \\not_strict_mode.app_rd_data_reg[241] ,\n \\not_strict_mode.app_rd_data_reg[225] ,\n \\not_strict_mode.app_rd_data_reg[248] ,\n \\not_strict_mode.app_rd_data_reg[232] ,\n \\not_strict_mode.app_rd_data_reg[240] ,\n \\not_strict_mode.app_rd_data_reg[224] ,\n \\not_strict_mode.app_rd_data_reg[223] ,\n \\not_strict_mode.app_rd_data_reg[207] ,\n \\not_strict_mode.app_rd_data_reg[215] ,\n \\not_strict_mode.app_rd_data_reg[199] ,\n \\not_strict_mode.app_rd_data_reg[222] ,\n \\not_strict_mode.app_rd_data_reg[206] ,\n \\not_strict_mode.app_rd_data_reg[214] ,\n \\not_strict_mode.app_rd_data_reg[198] ,\n \\not_strict_mode.app_rd_data_reg[221] ,\n \\not_strict_mode.app_rd_data_reg[205] ,\n \\not_strict_mode.app_rd_data_reg[213] ,\n \\not_strict_mode.app_rd_data_reg[197] ,\n \\not_strict_mode.app_rd_data_reg[220] ,\n \\not_strict_mode.app_rd_data_reg[204] ,\n \\not_strict_mode.app_rd_data_reg[212] ,\n \\not_strict_mode.app_rd_data_reg[196] ,\n \\not_strict_mode.app_rd_data_reg[219] ,\n \\not_strict_mode.app_rd_data_reg[203] ,\n \\not_strict_mode.app_rd_data_reg[211] ,\n \\not_strict_mode.app_rd_data_reg[195] ,\n \\not_strict_mode.app_rd_data_reg[218] ,\n \\not_strict_mode.app_rd_data_reg[202] ,\n \\not_strict_mode.app_rd_data_reg[210] ,\n \\not_strict_mode.app_rd_data_reg[194] ,\n \\not_strict_mode.app_rd_data_reg[217] ,\n \\not_strict_mode.app_rd_data_reg[201] ,\n \\not_strict_mode.app_rd_data_reg[209] ,\n \\not_strict_mode.app_rd_data_reg[193] ,\n \\not_strict_mode.app_rd_data_reg[216] ,\n \\not_strict_mode.app_rd_data_reg[200] ,\n \\not_strict_mode.app_rd_data_reg[208] ,\n \\not_strict_mode.app_rd_data_reg[192] ,\n \\not_strict_mode.app_rd_data_reg[191] ,\n \\not_strict_mode.app_rd_data_reg[175] ,\n \\not_strict_mode.app_rd_data_reg[183] ,\n \\not_strict_mode.app_rd_data_reg[167] ,\n \\not_strict_mode.app_rd_data_reg[190] ,\n \\not_strict_mode.app_rd_data_reg[174] ,\n \\not_strict_mode.app_rd_data_reg[182] ,\n \\not_strict_mode.app_rd_data_reg[166] ,\n \\not_strict_mode.app_rd_data_reg[189] ,\n \\not_strict_mode.app_rd_data_reg[173] ,\n \\not_strict_mode.app_rd_data_reg[181] ,\n \\not_strict_mode.app_rd_data_reg[165] ,\n \\not_strict_mode.app_rd_data_reg[188] ,\n \\not_strict_mode.app_rd_data_reg[172] ,\n \\not_strict_mode.app_rd_data_reg[180] ,\n \\not_strict_mode.app_rd_data_reg[164] ,\n \\not_strict_mode.app_rd_data_reg[187] ,\n \\not_strict_mode.app_rd_data_reg[171] ,\n \\not_strict_mode.app_rd_data_reg[179] ,\n \\not_strict_mode.app_rd_data_reg[163] ,\n \\not_strict_mode.app_rd_data_reg[186] ,\n \\not_strict_mode.app_rd_data_reg[170] ,\n \\not_strict_mode.app_rd_data_reg[178] ,\n \\not_strict_mode.app_rd_data_reg[162] ,\n \\not_strict_mode.app_rd_data_reg[185] ,\n \\not_strict_mode.app_rd_data_reg[169] ,\n \\not_strict_mode.app_rd_data_reg[177] ,\n \\not_strict_mode.app_rd_data_reg[161] ,\n \\not_strict_mode.app_rd_data_reg[184] ,\n \\not_strict_mode.app_rd_data_reg[168] ,\n \\not_strict_mode.app_rd_data_reg[176] ,\n \\not_strict_mode.app_rd_data_reg[160] ,\n \\not_strict_mode.app_rd_data_reg[159] ,\n \\not_strict_mode.app_rd_data_reg[143] ,\n \\not_strict_mode.app_rd_data_reg[151] ,\n \\not_strict_mode.app_rd_data_reg[135] ,\n \\not_strict_mode.app_rd_data_reg[158] ,\n \\not_strict_mode.app_rd_data_reg[142] ,\n \\not_strict_mode.app_rd_data_reg[150] ,\n \\not_strict_mode.app_rd_data_reg[134] ,\n \\not_strict_mode.app_rd_data_reg[157] ,\n \\not_strict_mode.app_rd_data_reg[141] ,\n \\not_strict_mode.app_rd_data_reg[149] ,\n \\not_strict_mode.app_rd_data_reg[133] ,\n \\not_strict_mode.app_rd_data_reg[156] ,\n \\not_strict_mode.app_rd_data_reg[140] ,\n \\not_strict_mode.app_rd_data_reg[148] ,\n \\not_strict_mode.app_rd_data_reg[132] ,\n \\not_strict_mode.app_rd_data_reg[155] ,\n \\not_strict_mode.app_rd_data_reg[139] ,\n \\not_strict_mode.app_rd_data_reg[147] ,\n \\not_strict_mode.app_rd_data_reg[131] ,\n \\not_strict_mode.app_rd_data_reg[154] ,\n \\not_strict_mode.app_rd_data_reg[138] ,\n \\not_strict_mode.app_rd_data_reg[146] ,\n \\not_strict_mode.app_rd_data_reg[130] ,\n \\not_strict_mode.app_rd_data_reg[153] ,\n \\not_strict_mode.app_rd_data_reg[137] ,\n \\not_strict_mode.app_rd_data_reg[145] ,\n \\not_strict_mode.app_rd_data_reg[129] ,\n \\not_strict_mode.app_rd_data_reg[152] ,\n \\not_strict_mode.app_rd_data_reg[136] ,\n \\not_strict_mode.app_rd_data_reg[144] ,\n \\not_strict_mode.app_rd_data_reg[128] ,\n \\not_strict_mode.app_rd_data_reg[127] ,\n \\not_strict_mode.app_rd_data_reg[111] ,\n \\not_strict_mode.app_rd_data_reg[119] ,\n \\not_strict_mode.app_rd_data_reg[103] ,\n \\not_strict_mode.app_rd_data_reg[126] ,\n \\not_strict_mode.app_rd_data_reg[110] ,\n \\not_strict_mode.app_rd_data_reg[118] ,\n \\not_strict_mode.app_rd_data_reg[102] ,\n \\not_strict_mode.app_rd_data_reg[125] ,\n \\not_strict_mode.app_rd_data_reg[109] ,\n \\not_strict_mode.app_rd_data_reg[117] ,\n \\not_strict_mode.app_rd_data_reg[101] ,\n \\not_strict_mode.app_rd_data_reg[124] ,\n \\not_strict_mode.app_rd_data_reg[108] ,\n \\not_strict_mode.app_rd_data_reg[116] ,\n \\not_strict_mode.app_rd_data_reg[100] ,\n \\not_strict_mode.app_rd_data_reg[123] ,\n \\not_strict_mode.app_rd_data_reg[107] ,\n \\not_strict_mode.app_rd_data_reg[115] ,\n \\not_strict_mode.app_rd_data_reg[99] ,\n \\not_strict_mode.app_rd_data_reg[122] ,\n \\not_strict_mode.app_rd_data_reg[106] ,\n \\not_strict_mode.app_rd_data_reg[114] ,\n \\not_strict_mode.app_rd_data_reg[98] ,\n \\not_strict_mode.app_rd_data_reg[121] ,\n \\not_strict_mode.app_rd_data_reg[105] ,\n \\not_strict_mode.app_rd_data_reg[113] ,\n \\not_strict_mode.app_rd_data_reg[97] ,\n \\not_strict_mode.app_rd_data_reg[120] ,\n \\not_strict_mode.app_rd_data_reg[104] ,\n \\not_strict_mode.app_rd_data_reg[112] ,\n \\not_strict_mode.app_rd_data_reg[96] ,\n \\not_strict_mode.app_rd_data_reg[95] ,\n \\not_strict_mode.app_rd_data_reg[79] ,\n \\not_strict_mode.app_rd_data_reg[87] ,\n \\not_strict_mode.app_rd_data_reg[71] ,\n \\not_strict_mode.app_rd_data_reg[94] ,\n \\not_strict_mode.app_rd_data_reg[78] ,\n \\not_strict_mode.app_rd_data_reg[86] ,\n \\not_strict_mode.app_rd_data_reg[70] ,\n \\not_strict_mode.app_rd_data_reg[93] ,\n \\not_strict_mode.app_rd_data_reg[77] ,\n \\not_strict_mode.app_rd_data_reg[85] ,\n \\not_strict_mode.app_rd_data_reg[69] ,\n \\not_strict_mode.app_rd_data_reg[92] ,\n \\not_strict_mode.app_rd_data_reg[76] ,\n \\not_strict_mode.app_rd_data_reg[84] ,\n \\not_strict_mode.app_rd_data_reg[68] ,\n \\not_strict_mode.app_rd_data_reg[91] ,\n \\not_strict_mode.app_rd_data_reg[75] ,\n \\not_strict_mode.app_rd_data_reg[83] ,\n \\not_strict_mode.app_rd_data_reg[67] ,\n \\not_strict_mode.app_rd_data_reg[90] ,\n \\not_strict_mode.app_rd_data_reg[74] ,\n \\not_strict_mode.app_rd_data_reg[82] ,\n \\not_strict_mode.app_rd_data_reg[66] ,\n \\not_strict_mode.app_rd_data_reg[89] ,\n \\not_strict_mode.app_rd_data_reg[73] ,\n \\not_strict_mode.app_rd_data_reg[81] ,\n \\not_strict_mode.app_rd_data_reg[65] ,\n \\not_strict_mode.app_rd_data_reg[88] ,\n \\not_strict_mode.app_rd_data_reg[72] ,\n \\not_strict_mode.app_rd_data_reg[80] ,\n \\not_strict_mode.app_rd_data_reg[64] ,\n \\not_strict_mode.app_rd_data_reg[63] ,\n \\not_strict_mode.app_rd_data_reg[47] ,\n \\not_strict_mode.app_rd_data_reg[55] ,\n \\not_strict_mode.app_rd_data_reg[39] ,\n \\not_strict_mode.app_rd_data_reg[62] ,\n \\not_strict_mode.app_rd_data_reg[46] ,\n \\not_strict_mode.app_rd_data_reg[54] ,\n \\not_strict_mode.app_rd_data_reg[38] ,\n \\not_strict_mode.app_rd_data_reg[61] ,\n \\not_strict_mode.app_rd_data_reg[45] ,\n \\not_strict_mode.app_rd_data_reg[53] ,\n \\not_strict_mode.app_rd_data_reg[37] ,\n \\not_strict_mode.app_rd_data_reg[60] ,\n \\not_strict_mode.app_rd_data_reg[44] ,\n \\not_strict_mode.app_rd_data_reg[52] ,\n \\not_strict_mode.app_rd_data_reg[36] ,\n \\not_strict_mode.app_rd_data_reg[59] ,\n \\not_strict_mode.app_rd_data_reg[43] ,\n \\not_strict_mode.app_rd_data_reg[51] ,\n \\not_strict_mode.app_rd_data_reg[35] ,\n \\not_strict_mode.app_rd_data_reg[58] ,\n \\not_strict_mode.app_rd_data_reg[42] ,\n \\not_strict_mode.app_rd_data_reg[50] ,\n \\not_strict_mode.app_rd_data_reg[34] ,\n \\not_strict_mode.app_rd_data_reg[57] ,\n \\not_strict_mode.app_rd_data_reg[41] ,\n \\not_strict_mode.app_rd_data_reg[49] ,\n \\not_strict_mode.app_rd_data_reg[33] ,\n \\not_strict_mode.app_rd_data_reg[56] ,\n \\not_strict_mode.app_rd_data_reg[40] ,\n \\not_strict_mode.app_rd_data_reg[48] ,\n \\not_strict_mode.app_rd_data_reg[32] ,\n \\not_strict_mode.app_rd_data_reg[31] ,\n \\not_strict_mode.app_rd_data_reg[15] ,\n \\not_strict_mode.app_rd_data_reg[23] ,\n \\not_strict_mode.app_rd_data_reg[7] ,\n \\not_strict_mode.app_rd_data_reg[30] ,\n \\not_strict_mode.app_rd_data_reg[14] ,\n \\not_strict_mode.app_rd_data_reg[22] ,\n \\not_strict_mode.app_rd_data_reg[6] ,\n \\not_strict_mode.app_rd_data_reg[29] ,\n \\not_strict_mode.app_rd_data_reg[13] ,\n \\not_strict_mode.app_rd_data_reg[21] ,\n \\not_strict_mode.app_rd_data_reg[5] ,\n \\not_strict_mode.app_rd_data_reg[28] ,\n \\not_strict_mode.app_rd_data_reg[12] ,\n \\not_strict_mode.app_rd_data_reg[20] ,\n \\not_strict_mode.app_rd_data_reg[4] ,\n \\not_strict_mode.app_rd_data_reg[27] ,\n \\not_strict_mode.app_rd_data_reg[11] ,\n \\not_strict_mode.app_rd_data_reg[19] ,\n \\not_strict_mode.app_rd_data_reg[3] ,\n \\not_strict_mode.app_rd_data_reg[26] ,\n \\not_strict_mode.app_rd_data_reg[10] ,\n \\not_strict_mode.app_rd_data_reg[18] ,\n \\not_strict_mode.app_rd_data_reg[2] ,\n \\not_strict_mode.app_rd_data_reg[25] ,\n \\not_strict_mode.app_rd_data_reg[9] ,\n \\not_strict_mode.app_rd_data_reg[17] ,\n \\not_strict_mode.app_rd_data_reg[1] ,\n \\not_strict_mode.app_rd_data_reg[24] ,\n \\not_strict_mode.app_rd_data_reg[8] ,\n \\not_strict_mode.app_rd_data_reg[16] ,\n \\not_strict_mode.app_rd_data_reg[0] ,\n \\read_fifo.tail_r_reg[0] ,\n \\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,\n \\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,\n \\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,\n \\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,\n \\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,\n \\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,\n \\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,\n \\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,\n \\not_strict_mode.app_rd_data_reg[255]_0 ,\n pi_phase_locked_all_r1_reg,\n \\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ,\n \\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ,\n \\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ,\n \\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ,\n \\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ,\n \\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ,\n \\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ,\n \\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ,\n \\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ,\n \\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ,\n \\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ,\n \\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ,\n \\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ,\n \\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ,\n \\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ,\n \\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ,\n \\not_strict_mode.app_rd_data_reg[31]_0 ,\n \\not_strict_mode.app_rd_data_reg[31]_1 ,\n \\my_empty_reg[7] ,\n \\not_strict_mode.app_rd_data_reg[23]_0 ,\n \\not_strict_mode.app_rd_data_reg[23]_1 ,\n \\my_empty_reg[7]_0 ,\n \\not_strict_mode.app_rd_data_reg[15]_0 ,\n \\not_strict_mode.app_rd_data_reg[15]_1 ,\n \\my_empty_reg[7]_1 ,\n \\not_strict_mode.app_rd_data_reg[7]_0 ,\n \\not_strict_mode.app_rd_data_reg[7]_1 ,\n \\my_empty_reg[7]_2 ,\n ofs_rdy_r_reg,\n ofs_rdy_r_reg_0,\n \\po_rdval_cnt_reg[8] ,\n \\pi_rdval_cnt_reg[5] ,\n phy_if_empty_r_reg,\n p_0_out,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,\n \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,\n \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,\n \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,\n \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,\n \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,\n \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,\n \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,\n \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,\n \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,\n \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,\n \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,\n \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n \\calib_sel_reg[0] ,\n pi_en_stg2_f_reg,\n pi_stg2_f_incdec_reg,\n freq_refclk,\n mem_refclk,\n mem_dqs_in,\n \\gen_byte_sel_div1.calib_in_common_reg_0 ,\n sync_pulse,\n CLK,\n COUNTERLOADVAL,\n \\gen_byte_sel_div1.calib_in_common_reg_1 ,\n ck_po_stg2_f_en_reg,\n ck_po_stg2_f_indec_reg,\n delay_done_r4_reg,\n \\write_buffer.wr_buf_out_data_reg[255] ,\n \\write_buffer.wr_buf_out_data_reg[254] ,\n \\write_buffer.wr_buf_out_data_reg[253] ,\n \\write_buffer.wr_buf_out_data_reg[252] ,\n \\write_buffer.wr_buf_out_data_reg[251] ,\n \\write_buffer.wr_buf_out_data_reg[250] ,\n \\write_buffer.wr_buf_out_data_reg[249] ,\n \\write_buffer.wr_buf_out_data_reg[248] ,\n \\gen_byte_sel_div1.calib_in_common_reg_2 ,\n mem_dq_in,\n idelay_inc,\n LD0,\n CLKB0,\n phy_if_reset,\n \\gen_byte_sel_div1.calib_in_common_reg_3 ,\n \\calib_sel_reg[0]_0 ,\n pi_en_stg2_f_reg_0,\n pi_stg2_f_incdec_reg_0,\n \\gen_byte_sel_div1.calib_in_common_reg_4 ,\n \\calib_zero_inputs_reg[0] ,\n \\gen_byte_sel_div1.calib_in_common_reg_5 ,\n ck_po_stg2_f_en_reg_0,\n ck_po_stg2_f_indec_reg_0,\n delay_done_r4_reg_0,\n \\write_buffer.wr_buf_out_data_reg[247] ,\n \\write_buffer.wr_buf_out_data_reg[246] ,\n \\write_buffer.wr_buf_out_data_reg[245] ,\n \\write_buffer.wr_buf_out_data_reg[244] ,\n \\write_buffer.wr_buf_out_data_reg[243] ,\n \\write_buffer.wr_buf_out_data_reg[242] ,\n \\write_buffer.wr_buf_out_data_reg[241] ,\n \\write_buffer.wr_buf_out_data_reg[240] ,\n \\gen_byte_sel_div1.calib_in_common_reg_6 ,\n LD0_3,\n CLKB0_7,\n \\gen_byte_sel_div1.calib_in_common_reg_7 ,\n \\calib_sel_reg[1] ,\n pi_en_stg2_f_reg_1,\n pi_stg2_f_incdec_reg_1,\n \\gen_byte_sel_div1.calib_in_common_reg_8 ,\n \\calib_zero_inputs_reg[0]_0 ,\n \\gen_byte_sel_div1.calib_in_common_reg_9 ,\n ck_po_stg2_f_en_reg_1,\n ck_po_stg2_f_indec_reg_1,\n delay_done_r4_reg_1,\n \\write_buffer.wr_buf_out_data_reg[239] ,\n \\write_buffer.wr_buf_out_data_reg[238] ,\n \\write_buffer.wr_buf_out_data_reg[237] ,\n \\write_buffer.wr_buf_out_data_reg[236] ,\n \\write_buffer.wr_buf_out_data_reg[235] ,\n \\write_buffer.wr_buf_out_data_reg[234] ,\n \\write_buffer.wr_buf_out_data_reg[233] ,\n \\write_buffer.wr_buf_out_data_reg[232] ,\n \\gen_byte_sel_div1.calib_in_common_reg_10 ,\n LD0_4,\n CLKB0_8,\n \\gen_byte_sel_div1.calib_in_common_reg_11 ,\n \\calib_sel_reg[0]_1 ,\n pi_en_stg2_f_reg_2,\n pi_stg2_f_incdec_reg_2,\n \\gen_byte_sel_div1.calib_in_common_reg_12 ,\n \\calib_zero_inputs_reg[0]_1 ,\n \\gen_byte_sel_div1.calib_in_common_reg_13 ,\n ck_po_stg2_f_en_reg_2,\n ck_po_stg2_f_indec_reg_2,\n delay_done_r4_reg_2,\n \\write_buffer.wr_buf_out_data_reg[231] ,\n \\write_buffer.wr_buf_out_data_reg[230] ,\n \\write_buffer.wr_buf_out_data_reg[229] ,\n \\write_buffer.wr_buf_out_data_reg[228] ,\n \\write_buffer.wr_buf_out_data_reg[227] ,\n \\write_buffer.wr_buf_out_data_reg[226] ,\n \\write_buffer.wr_buf_out_data_reg[225] ,\n \\write_buffer.wr_buf_out_data_reg[224] ,\n \\gen_byte_sel_div1.calib_in_common_reg_14 ,\n LD0_5,\n CLKB0_9,\n phy_ctl_mstr_empty,\n phy_ctl_wr_i2,\n pll_locked,\n phy_read_calib,\n in0,\n phy_write_calib,\n Q,\n RST0,\n phy_ctl_wr_i2_reg,\n \\rclk_delay_reg[11]_0 ,\n rstdiv0_sync_r1_reg_rep__9,\n rst_primitives_reg_1,\n mux_wrdata_en,\n mcGo_w__0,\n \\read_fifo.fifo_out_data_r_reg[6] ,\n ram_init_done_r,\n init_calib_complete_reg_rep,\n \\write_buffer.wr_buf_out_data_reg[287] ,\n prbs_rdlvl_start_reg,\n out,\n ref_dll_lock_w,\n sys_rst,\n \\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ,\n mmcm_locked,\n \\byte_r_reg[0] ,\n \\byte_r_reg[1] ,\n tail_r,\n \\rd_mux_sel_r_reg[1] ,\n \\read_fifo.fifo_out_data_r_reg[6]_0 ,\n DOC,\n DOB,\n DOA,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ,\n A,\n mux_wrdata,\n mux_wrdata_mask,\n E,\n \\fine_delay_mod_reg[23] ,\n \\gen_byte_sel_div1.calib_in_common_reg_15 ,\n \\calib_sel_reg[0]_2 ,\n \\gen_byte_sel_div1.calib_in_common_reg_16 ,\n \\calib_sel_reg[1]_0 ,\n \\gen_byte_sel_div1.calib_in_common_reg_17 ,\n \\calib_sel_reg[0]_3 ,\n \\calib_sel_reg[1]_1 ,\n \\po_stg2_wrcal_cnt_reg[1] );\n output [3:0]\\pi_dqs_found_lanes_r1_reg[3] ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n output [3:0]mem_dqs_out;\n output [3:0]mem_dqs_ts;\n output [35:0]mem_dq_out;\n output [35:0]mem_dq_ts;\n output idelay_ld_rst;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n output idelay_ld_rst_0;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;\n output idelay_ld_rst_1;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;\n output idelay_ld_rst_2;\n output [0:0]_phy_ctl_full_p__0;\n output rst_primitives_reg_0;\n output rst_primitives;\n output mcGo_reg_0;\n output rclk_delay_11;\n output \\not_strict_mode.app_rd_data_reg[252] ;\n output \\not_strict_mode.app_rd_data_reg[244] ;\n output \\not_strict_mode.app_rd_data_reg[236] ;\n output \\not_strict_mode.app_rd_data_reg[228] ;\n output \\my_empty_reg[1] ;\n output \\my_empty_reg[1]_0 ;\n output \\my_empty_reg[1]_1 ;\n output \\my_empty_reg[1]_2 ;\n output \\mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13 ;\n output rd_buf_we;\n output \\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n output phy_rddata_en;\n output mux_rd_valid_r_reg;\n output rst_sync_r1_reg;\n output [63:0]\\data_bytes_r_reg[63] ;\n output \\not_strict_mode.app_rd_data_reg[255] ;\n output \\not_strict_mode.app_rd_data_reg[239] ;\n output \\not_strict_mode.app_rd_data_reg[247] ;\n output \\not_strict_mode.app_rd_data_reg[231] ;\n output \\not_strict_mode.app_rd_data_reg[254] ;\n output \\not_strict_mode.app_rd_data_reg[238] ;\n output \\not_strict_mode.app_rd_data_reg[246] ;\n output \\not_strict_mode.app_rd_data_reg[230] ;\n output \\not_strict_mode.app_rd_data_reg[253] ;\n output \\not_strict_mode.app_rd_data_reg[237] ;\n output \\not_strict_mode.app_rd_data_reg[245] ;\n output \\not_strict_mode.app_rd_data_reg[229] ;\n output \\not_strict_mode.app_rd_data_reg[252]_0 ;\n output \\not_strict_mode.app_rd_data_reg[236]_0 ;\n output \\not_strict_mode.app_rd_data_reg[244]_0 ;\n output \\not_strict_mode.app_rd_data_reg[228]_0 ;\n output \\not_strict_mode.app_rd_data_reg[251] ;\n output \\not_strict_mode.app_rd_data_reg[235] ;\n output \\not_strict_mode.app_rd_data_reg[243] ;\n output \\not_strict_mode.app_rd_data_reg[227] ;\n output \\not_strict_mode.app_rd_data_reg[250] ;\n output \\not_strict_mode.app_rd_data_reg[234] ;\n output \\not_strict_mode.app_rd_data_reg[242] ;\n output \\not_strict_mode.app_rd_data_reg[226] ;\n output \\not_strict_mode.app_rd_data_reg[249] ;\n output \\not_strict_mode.app_rd_data_reg[233] ;\n output \\not_strict_mode.app_rd_data_reg[241] ;\n output \\not_strict_mode.app_rd_data_reg[225] ;\n output \\not_strict_mode.app_rd_data_reg[248] ;\n output \\not_strict_mode.app_rd_data_reg[232] ;\n output \\not_strict_mode.app_rd_data_reg[240] ;\n output \\not_strict_mode.app_rd_data_reg[224] ;\n output \\not_strict_mode.app_rd_data_reg[223] ;\n output \\not_strict_mode.app_rd_data_reg[207] ;\n output \\not_strict_mode.app_rd_data_reg[215] ;\n output \\not_strict_mode.app_rd_data_reg[199] ;\n output \\not_strict_mode.app_rd_data_reg[222] ;\n output \\not_strict_mode.app_rd_data_reg[206] ;\n output \\not_strict_mode.app_rd_data_reg[214] ;\n output \\not_strict_mode.app_rd_data_reg[198] ;\n output \\not_strict_mode.app_rd_data_reg[221] ;\n output \\not_strict_mode.app_rd_data_reg[205] ;\n output \\not_strict_mode.app_rd_data_reg[213] ;\n output \\not_strict_mode.app_rd_data_reg[197] ;\n output \\not_strict_mode.app_rd_data_reg[220] ;\n output \\not_strict_mode.app_rd_data_reg[204] ;\n output \\not_strict_mode.app_rd_data_reg[212] ;\n output \\not_strict_mode.app_rd_data_reg[196] ;\n output \\not_strict_mode.app_rd_data_reg[219] ;\n output \\not_strict_mode.app_rd_data_reg[203] ;\n output \\not_strict_mode.app_rd_data_reg[211] ;\n output \\not_strict_mode.app_rd_data_reg[195] ;\n output \\not_strict_mode.app_rd_data_reg[218] ;\n output \\not_strict_mode.app_rd_data_reg[202] ;\n output \\not_strict_mode.app_rd_data_reg[210] ;\n output \\not_strict_mode.app_rd_data_reg[194] ;\n output \\not_strict_mode.app_rd_data_reg[217] ;\n output \\not_strict_mode.app_rd_data_reg[201] ;\n output \\not_strict_mode.app_rd_data_reg[209] ;\n output \\not_strict_mode.app_rd_data_reg[193] ;\n output \\not_strict_mode.app_rd_data_reg[216] ;\n output \\not_strict_mode.app_rd_data_reg[200] ;\n output \\not_strict_mode.app_rd_data_reg[208] ;\n output \\not_strict_mode.app_rd_data_reg[192] ;\n output \\not_strict_mode.app_rd_data_reg[191] ;\n output \\not_strict_mode.app_rd_data_reg[175] ;\n output \\not_strict_mode.app_rd_data_reg[183] ;\n output \\not_strict_mode.app_rd_data_reg[167] ;\n output \\not_strict_mode.app_rd_data_reg[190] ;\n output \\not_strict_mode.app_rd_data_reg[174] ;\n output \\not_strict_mode.app_rd_data_reg[182] ;\n output \\not_strict_mode.app_rd_data_reg[166] ;\n output \\not_strict_mode.app_rd_data_reg[189] ;\n output \\not_strict_mode.app_rd_data_reg[173] ;\n output \\not_strict_mode.app_rd_data_reg[181] ;\n output \\not_strict_mode.app_rd_data_reg[165] ;\n output \\not_strict_mode.app_rd_data_reg[188] ;\n output \\not_strict_mode.app_rd_data_reg[172] ;\n output \\not_strict_mode.app_rd_data_reg[180] ;\n output \\not_strict_mode.app_rd_data_reg[164] ;\n output \\not_strict_mode.app_rd_data_reg[187] ;\n output \\not_strict_mode.app_rd_data_reg[171] ;\n output \\not_strict_mode.app_rd_data_reg[179] ;\n output \\not_strict_mode.app_rd_data_reg[163] ;\n output \\not_strict_mode.app_rd_data_reg[186] ;\n output \\not_strict_mode.app_rd_data_reg[170] ;\n output \\not_strict_mode.app_rd_data_reg[178] ;\n output \\not_strict_mode.app_rd_data_reg[162] ;\n output \\not_strict_mode.app_rd_data_reg[185] ;\n output \\not_strict_mode.app_rd_data_reg[169] ;\n output \\not_strict_mode.app_rd_data_reg[177] ;\n output \\not_strict_mode.app_rd_data_reg[161] ;\n output \\not_strict_mode.app_rd_data_reg[184] ;\n output \\not_strict_mode.app_rd_data_reg[168] ;\n output \\not_strict_mode.app_rd_data_reg[176] ;\n output \\not_strict_mode.app_rd_data_reg[160] ;\n output \\not_strict_mode.app_rd_data_reg[159] ;\n output \\not_strict_mode.app_rd_data_reg[143] ;\n output \\not_strict_mode.app_rd_data_reg[151] ;\n output \\not_strict_mode.app_rd_data_reg[135] ;\n output \\not_strict_mode.app_rd_data_reg[158] ;\n output \\not_strict_mode.app_rd_data_reg[142] ;\n output \\not_strict_mode.app_rd_data_reg[150] ;\n output \\not_strict_mode.app_rd_data_reg[134] ;\n output \\not_strict_mode.app_rd_data_reg[157] ;\n output \\not_strict_mode.app_rd_data_reg[141] ;\n output \\not_strict_mode.app_rd_data_reg[149] ;\n output \\not_strict_mode.app_rd_data_reg[133] ;\n output \\not_strict_mode.app_rd_data_reg[156] ;\n output \\not_strict_mode.app_rd_data_reg[140] ;\n output \\not_strict_mode.app_rd_data_reg[148] ;\n output \\not_strict_mode.app_rd_data_reg[132] ;\n output \\not_strict_mode.app_rd_data_reg[155] ;\n output \\not_strict_mode.app_rd_data_reg[139] ;\n output \\not_strict_mode.app_rd_data_reg[147] ;\n output \\not_strict_mode.app_rd_data_reg[131] ;\n output \\not_strict_mode.app_rd_data_reg[154] ;\n output \\not_strict_mode.app_rd_data_reg[138] ;\n output \\not_strict_mode.app_rd_data_reg[146] ;\n output \\not_strict_mode.app_rd_data_reg[130] ;\n output \\not_strict_mode.app_rd_data_reg[153] ;\n output \\not_strict_mode.app_rd_data_reg[137] ;\n output \\not_strict_mode.app_rd_data_reg[145] ;\n output \\not_strict_mode.app_rd_data_reg[129] ;\n output \\not_strict_mode.app_rd_data_reg[152] ;\n output \\not_strict_mode.app_rd_data_reg[136] ;\n output \\not_strict_mode.app_rd_data_reg[144] ;\n output \\not_strict_mode.app_rd_data_reg[128] ;\n output \\not_strict_mode.app_rd_data_reg[127] ;\n output \\not_strict_mode.app_rd_data_reg[111] ;\n output \\not_strict_mode.app_rd_data_reg[119] ;\n output \\not_strict_mode.app_rd_data_reg[103] ;\n output \\not_strict_mode.app_rd_data_reg[126] ;\n output \\not_strict_mode.app_rd_data_reg[110] ;\n output \\not_strict_mode.app_rd_data_reg[118] ;\n output \\not_strict_mode.app_rd_data_reg[102] ;\n output \\not_strict_mode.app_rd_data_reg[125] ;\n output \\not_strict_mode.app_rd_data_reg[109] ;\n output \\not_strict_mode.app_rd_data_reg[117] ;\n output \\not_strict_mode.app_rd_data_reg[101] ;\n output \\not_strict_mode.app_rd_data_reg[124] ;\n output \\not_strict_mode.app_rd_data_reg[108] ;\n output \\not_strict_mode.app_rd_data_reg[116] ;\n output \\not_strict_mode.app_rd_data_reg[100] ;\n output \\not_strict_mode.app_rd_data_reg[123] ;\n output \\not_strict_mode.app_rd_data_reg[107] ;\n output \\not_strict_mode.app_rd_data_reg[115] ;\n output \\not_strict_mode.app_rd_data_reg[99] ;\n output \\not_strict_mode.app_rd_data_reg[122] ;\n output \\not_strict_mode.app_rd_data_reg[106] ;\n output \\not_strict_mode.app_rd_data_reg[114] ;\n output \\not_strict_mode.app_rd_data_reg[98] ;\n output \\not_strict_mode.app_rd_data_reg[121] ;\n output \\not_strict_mode.app_rd_data_reg[105] ;\n output \\not_strict_mode.app_rd_data_reg[113] ;\n output \\not_strict_mode.app_rd_data_reg[97] ;\n output \\not_strict_mode.app_rd_data_reg[120] ;\n output \\not_strict_mode.app_rd_data_reg[104] ;\n output \\not_strict_mode.app_rd_data_reg[112] ;\n output \\not_strict_mode.app_rd_data_reg[96] ;\n output \\not_strict_mode.app_rd_data_reg[95] ;\n output \\not_strict_mode.app_rd_data_reg[79] ;\n output \\not_strict_mode.app_rd_data_reg[87] ;\n output \\not_strict_mode.app_rd_data_reg[71] ;\n output \\not_strict_mode.app_rd_data_reg[94] ;\n output \\not_strict_mode.app_rd_data_reg[78] ;\n output \\not_strict_mode.app_rd_data_reg[86] ;\n output \\not_strict_mode.app_rd_data_reg[70] ;\n output \\not_strict_mode.app_rd_data_reg[93] ;\n output \\not_strict_mode.app_rd_data_reg[77] ;\n output \\not_strict_mode.app_rd_data_reg[85] ;\n output \\not_strict_mode.app_rd_data_reg[69] ;\n output \\not_strict_mode.app_rd_data_reg[92] ;\n output \\not_strict_mode.app_rd_data_reg[76] ;\n output \\not_strict_mode.app_rd_data_reg[84] ;\n output \\not_strict_mode.app_rd_data_reg[68] ;\n output \\not_strict_mode.app_rd_data_reg[91] ;\n output \\not_strict_mode.app_rd_data_reg[75] ;\n output \\not_strict_mode.app_rd_data_reg[83] ;\n output \\not_strict_mode.app_rd_data_reg[67] ;\n output \\not_strict_mode.app_rd_data_reg[90] ;\n output \\not_strict_mode.app_rd_data_reg[74] ;\n output \\not_strict_mode.app_rd_data_reg[82] ;\n output \\not_strict_mode.app_rd_data_reg[66] ;\n output \\not_strict_mode.app_rd_data_reg[89] ;\n output \\not_strict_mode.app_rd_data_reg[73] ;\n output \\not_strict_mode.app_rd_data_reg[81] ;\n output \\not_strict_mode.app_rd_data_reg[65] ;\n output \\not_strict_mode.app_rd_data_reg[88] ;\n output \\not_strict_mode.app_rd_data_reg[72] ;\n output \\not_strict_mode.app_rd_data_reg[80] ;\n output \\not_strict_mode.app_rd_data_reg[64] ;\n output \\not_strict_mode.app_rd_data_reg[63] ;\n output \\not_strict_mode.app_rd_data_reg[47] ;\n output \\not_strict_mode.app_rd_data_reg[55] ;\n output \\not_strict_mode.app_rd_data_reg[39] ;\n output \\not_strict_mode.app_rd_data_reg[62] ;\n output \\not_strict_mode.app_rd_data_reg[46] ;\n output \\not_strict_mode.app_rd_data_reg[54] ;\n output \\not_strict_mode.app_rd_data_reg[38] ;\n output \\not_strict_mode.app_rd_data_reg[61] ;\n output \\not_strict_mode.app_rd_data_reg[45] ;\n output \\not_strict_mode.app_rd_data_reg[53] ;\n output \\not_strict_mode.app_rd_data_reg[37] ;\n output \\not_strict_mode.app_rd_data_reg[60] ;\n output \\not_strict_mode.app_rd_data_reg[44] ;\n output \\not_strict_mode.app_rd_data_reg[52] ;\n output \\not_strict_mode.app_rd_data_reg[36] ;\n output \\not_strict_mode.app_rd_data_reg[59] ;\n output \\not_strict_mode.app_rd_data_reg[43] ;\n output \\not_strict_mode.app_rd_data_reg[51] ;\n output \\not_strict_mode.app_rd_data_reg[35] ;\n output \\not_strict_mode.app_rd_data_reg[58] ;\n output \\not_strict_mode.app_rd_data_reg[42] ;\n output \\not_strict_mode.app_rd_data_reg[50] ;\n output \\not_strict_mode.app_rd_data_reg[34] ;\n output \\not_strict_mode.app_rd_data_reg[57] ;\n output \\not_strict_mode.app_rd_data_reg[41] ;\n output \\not_strict_mode.app_rd_data_reg[49] ;\n output \\not_strict_mode.app_rd_data_reg[33] ;\n output \\not_strict_mode.app_rd_data_reg[56] ;\n output \\not_strict_mode.app_rd_data_reg[40] ;\n output \\not_strict_mode.app_rd_data_reg[48] ;\n output \\not_strict_mode.app_rd_data_reg[32] ;\n output \\not_strict_mode.app_rd_data_reg[31] ;\n output \\not_strict_mode.app_rd_data_reg[15] ;\n output \\not_strict_mode.app_rd_data_reg[23] ;\n output \\not_strict_mode.app_rd_data_reg[7] ;\n output \\not_strict_mode.app_rd_data_reg[30] ;\n output \\not_strict_mode.app_rd_data_reg[14] ;\n output \\not_strict_mode.app_rd_data_reg[22] ;\n output \\not_strict_mode.app_rd_data_reg[6] ;\n output \\not_strict_mode.app_rd_data_reg[29] ;\n output \\not_strict_mode.app_rd_data_reg[13] ;\n output \\not_strict_mode.app_rd_data_reg[21] ;\n output \\not_strict_mode.app_rd_data_reg[5] ;\n output \\not_strict_mode.app_rd_data_reg[28] ;\n output \\not_strict_mode.app_rd_data_reg[12] ;\n output \\not_strict_mode.app_rd_data_reg[20] ;\n output \\not_strict_mode.app_rd_data_reg[4] ;\n output \\not_strict_mode.app_rd_data_reg[27] ;\n output \\not_strict_mode.app_rd_data_reg[11] ;\n output \\not_strict_mode.app_rd_data_reg[19] ;\n output \\not_strict_mode.app_rd_data_reg[3] ;\n output \\not_strict_mode.app_rd_data_reg[26] ;\n output \\not_strict_mode.app_rd_data_reg[10] ;\n output \\not_strict_mode.app_rd_data_reg[18] ;\n output \\not_strict_mode.app_rd_data_reg[2] ;\n output \\not_strict_mode.app_rd_data_reg[25] ;\n output \\not_strict_mode.app_rd_data_reg[9] ;\n output \\not_strict_mode.app_rd_data_reg[17] ;\n output \\not_strict_mode.app_rd_data_reg[1] ;\n output \\not_strict_mode.app_rd_data_reg[24] ;\n output \\not_strict_mode.app_rd_data_reg[8] ;\n output \\not_strict_mode.app_rd_data_reg[16] ;\n output \\not_strict_mode.app_rd_data_reg[0] ;\n output \\read_fifo.tail_r_reg[0] ;\n output \\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n output \\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n output \\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n output \\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n output \\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n output \\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n output \\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n output \\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n output [255:0]\\not_strict_mode.app_rd_data_reg[255]_0 ;\n output pi_phase_locked_all_r1_reg;\n output \\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ;\n output \\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ;\n output \\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ;\n output \\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ;\n output \\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ;\n output \\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ;\n output \\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ;\n output \\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ;\n output \\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ;\n output \\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ;\n output \\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ;\n output \\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ;\n output \\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ;\n output \\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ;\n output \\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ;\n output \\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[31]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[31]_1 ;\n output [63:0]\\my_empty_reg[7] ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[23]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[23]_1 ;\n output [63:0]\\my_empty_reg[7]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[15]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[15]_1 ;\n output [63:0]\\my_empty_reg[7]_1 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[7]_0 ;\n output [0:0]\\not_strict_mode.app_rd_data_reg[7]_1 ;\n output [63:0]\\my_empty_reg[7]_2 ;\n output ofs_rdy_r_reg;\n output ofs_rdy_r_reg_0;\n output [8:0]\\po_rdval_cnt_reg[8] ;\n output [5:0]\\pi_rdval_cnt_reg[5] ;\n output phy_if_empty_r_reg;\n output p_0_out;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n output \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n output \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n output \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n output \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n output \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n output \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n output \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n output \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n output \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n output \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n output \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n output \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n input \\gen_byte_sel_div1.calib_in_common_reg ;\n input \\calib_sel_reg[0] ;\n input pi_en_stg2_f_reg;\n input pi_stg2_f_incdec_reg;\n input freq_refclk;\n input mem_refclk;\n input [3:0]mem_dqs_in;\n input \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n input sync_pulse;\n input CLK;\n input [5:0]COUNTERLOADVAL;\n input \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n input ck_po_stg2_f_en_reg;\n input ck_po_stg2_f_indec_reg;\n input delay_done_r4_reg;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[255] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[254] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[253] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[252] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[251] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[250] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[249] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[248] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n input [31:0]mem_dq_in;\n input idelay_inc;\n input LD0;\n input CLKB0;\n input phy_if_reset;\n input \\gen_byte_sel_div1.calib_in_common_reg_3 ;\n input \\calib_sel_reg[0]_0 ;\n input pi_en_stg2_f_reg_0;\n input pi_stg2_f_incdec_reg_0;\n input \\gen_byte_sel_div1.calib_in_common_reg_4 ;\n input [5:0]\\calib_zero_inputs_reg[0] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_5 ;\n input ck_po_stg2_f_en_reg_0;\n input ck_po_stg2_f_indec_reg_0;\n input delay_done_r4_reg_0;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[247] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[246] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[245] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[244] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[243] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[242] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[241] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[240] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_6 ;\n input LD0_3;\n input CLKB0_7;\n input \\gen_byte_sel_div1.calib_in_common_reg_7 ;\n input \\calib_sel_reg[1] ;\n input pi_en_stg2_f_reg_1;\n input pi_stg2_f_incdec_reg_1;\n input \\gen_byte_sel_div1.calib_in_common_reg_8 ;\n input [5:0]\\calib_zero_inputs_reg[0]_0 ;\n input \\gen_byte_sel_div1.calib_in_common_reg_9 ;\n input ck_po_stg2_f_en_reg_1;\n input ck_po_stg2_f_indec_reg_1;\n input delay_done_r4_reg_1;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[239] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[238] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[237] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[236] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[235] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[234] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[233] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[232] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_10 ;\n input LD0_4;\n input CLKB0_8;\n input \\gen_byte_sel_div1.calib_in_common_reg_11 ;\n input \\calib_sel_reg[0]_1 ;\n input pi_en_stg2_f_reg_2;\n input pi_stg2_f_incdec_reg_2;\n input \\gen_byte_sel_div1.calib_in_common_reg_12 ;\n input [5:0]\\calib_zero_inputs_reg[0]_1 ;\n input \\gen_byte_sel_div1.calib_in_common_reg_13 ;\n input ck_po_stg2_f_en_reg_2;\n input ck_po_stg2_f_indec_reg_2;\n input delay_done_r4_reg_2;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[231] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[230] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[229] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[228] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[227] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[226] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[225] ;\n input [7:0]\\write_buffer.wr_buf_out_data_reg[224] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_14 ;\n input LD0_5;\n input CLKB0_9;\n input phy_ctl_mstr_empty;\n input phy_ctl_wr_i2;\n input pll_locked;\n input phy_read_calib;\n input in0;\n input phy_write_calib;\n input [10:0]Q;\n input RST0;\n input phy_ctl_wr_i2_reg;\n input \\rclk_delay_reg[11]_0 ;\n input rstdiv0_sync_r1_reg_rep__9;\n input rst_primitives_reg_1;\n input mux_wrdata_en;\n input [0:0]mcGo_w__0;\n input [0:0]\\read_fifo.fifo_out_data_r_reg[6] ;\n input ram_init_done_r;\n input init_calib_complete_reg_rep;\n input [31:0]\\write_buffer.wr_buf_out_data_reg[287] ;\n input prbs_rdlvl_start_reg;\n input out;\n input [0:0]ref_dll_lock_w;\n input sys_rst;\n input [0:0]\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ;\n input mmcm_locked;\n input \\byte_r_reg[0] ;\n input \\byte_r_reg[1] ;\n input [0:0]tail_r;\n input [1:0]\\rd_mux_sel_r_reg[1] ;\n input \\read_fifo.fifo_out_data_r_reg[6]_0 ;\n input [1:0]DOC;\n input [1:0]DOB;\n input [1:0]DOA;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ;\n input [1:0]A;\n input [255:0]mux_wrdata;\n input [31:0]mux_wrdata_mask;\n input [0:0]E;\n input [7:0]\\fine_delay_mod_reg[23] ;\n input [0:0]\\gen_byte_sel_div1.calib_in_common_reg_15 ;\n input [7:0]\\calib_sel_reg[0]_2 ;\n input [0:0]\\gen_byte_sel_div1.calib_in_common_reg_16 ;\n input [7:0]\\calib_sel_reg[1]_0 ;\n input [0:0]\\gen_byte_sel_div1.calib_in_common_reg_17 ;\n input [7:0]\\calib_sel_reg[0]_3 ;\n input [1:0]\\calib_sel_reg[1]_1 ;\n input [1:0]\\po_stg2_wrcal_cnt_reg[1] ;\n\n wire [1:0]A;\n wire A_byte_rd_en;\n wire [5:0]A_pi_counter_read_val;\n (* async_reg = \"true\" *) wire A_pi_rst_div2;\n wire [8:0]A_po_counter_read_val;\n wire A_rst_primitives;\n wire B_byte_rd_en;\n wire [5:0]B_pi_counter_read_val;\n (* async_reg = \"true\" *) wire B_pi_rst_div2;\n wire [8:0]B_po_counter_read_val;\n wire B_rclk;\n wire CLK;\n wire CLKB0;\n wire CLKB0_7;\n wire CLKB0_8;\n wire CLKB0_9;\n wire [5:0]COUNTERLOADVAL;\n wire C_byte_rd_en;\n wire [5:0]C_pi_counter_read_val;\n (* async_reg = \"true\" *) wire C_pi_rst_div2;\n wire [8:0]C_po_counter_read_val;\n wire [1:0]DOA;\n wire [1:0]DOB;\n wire [1:0]DOC;\n wire D_byte_rd_en;\n (* async_reg = \"true\" *) wire D_pi_rst_div2;\n wire [0:0]E;\n wire LD0;\n wire LD0_3;\n wire LD0_4;\n wire LD0_5;\n wire [10:0]Q;\n wire RST0;\n wire [0:0]_phy_ctl_full_p__0;\n wire \\byte_r_reg[0] ;\n wire \\byte_r_reg[1] ;\n wire \\calib_sel_reg[0] ;\n wire \\calib_sel_reg[0]_0 ;\n wire \\calib_sel_reg[0]_1 ;\n wire [7:0]\\calib_sel_reg[0]_2 ;\n wire [7:0]\\calib_sel_reg[0]_3 ;\n wire \\calib_sel_reg[1] ;\n wire [7:0]\\calib_sel_reg[1]_0 ;\n wire [1:0]\\calib_sel_reg[1]_1 ;\n wire [5:0]\\calib_zero_inputs_reg[0] ;\n wire [5:0]\\calib_zero_inputs_reg[0]_0 ;\n wire [5:0]\\calib_zero_inputs_reg[0]_1 ;\n wire ck_po_stg2_f_en_reg;\n wire ck_po_stg2_f_en_reg_0;\n wire ck_po_stg2_f_en_reg_1;\n wire ck_po_stg2_f_en_reg_2;\n wire ck_po_stg2_f_indec_reg;\n wire ck_po_stg2_f_indec_reg_0;\n wire ck_po_stg2_f_indec_reg_1;\n wire ck_po_stg2_f_indec_reg_2;\n wire [63:0]\\data_bytes_r_reg[63] ;\n wire \\ddr_byte_lane_A.ddr_byte_lane_A_n_2 ;\n wire \\ddr_byte_lane_C.ddr_byte_lane_C_n_2 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_154 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_2 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_222 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_223 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_224 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_225 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_226 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_227 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_228 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_229 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_230 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_231 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_232 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_233 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_234 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_235 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_236 ;\n wire delay_done_r4_reg;\n wire delay_done_r4_reg_0;\n wire delay_done_r4_reg_1;\n wire delay_done_r4_reg_2;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;\n wire [0:0]\\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ;\n wire [3:3]\\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1 ;\n wire [3:0]\\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4 ;\n wire [7:0]\\fine_delay_mod_reg[23] ;\n wire freq_refclk;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_10 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_11 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_12 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_13 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_14 ;\n wire [0:0]\\gen_byte_sel_div1.calib_in_common_reg_15 ;\n wire [0:0]\\gen_byte_sel_div1.calib_in_common_reg_16 ;\n wire [0:0]\\gen_byte_sel_div1.calib_in_common_reg_17 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_3 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_4 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_5 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_6 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_7 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_8 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_9 ;\n wire \\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n wire \\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n wire \\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n wire \\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;\n wire \\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n wire \\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n wire \\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n wire \\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ;\n wire idelay_inc;\n wire idelay_ld_rst;\n wire idelay_ld_rst_0;\n wire idelay_ld_rst_1;\n wire idelay_ld_rst_2;\n wire [3:3]if_empty_r;\n wire [3:3]if_empty_r_2;\n wire [3:3]if_empty_r_5;\n wire in0;\n wire init_calib_complete_reg_rep;\n wire \\mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13 ;\n wire mcGo_reg_0;\n wire [0:0]mcGo_w;\n wire [0:0]mcGo_w__0;\n wire [31:0]mem_dq_in;\n wire [35:0]mem_dq_out;\n wire [35:0]mem_dq_ts;\n wire [3:0]mem_dqs_in;\n wire [3:0]mem_dqs_out;\n wire [3:0]mem_dqs_ts;\n wire mem_refclk;\n wire mmcm_locked;\n wire mux_rd_valid_r_reg;\n wire [255:0]mux_wrdata;\n wire mux_wrdata_en;\n wire [31:0]mux_wrdata_mask;\n wire \\my_empty_reg[1] ;\n wire \\my_empty_reg[1]_0 ;\n wire \\my_empty_reg[1]_1 ;\n wire \\my_empty_reg[1]_2 ;\n wire [63:0]\\my_empty_reg[7] ;\n wire [63:0]\\my_empty_reg[7]_0 ;\n wire [63:0]\\my_empty_reg[7]_1 ;\n wire [63:0]\\my_empty_reg[7]_2 ;\n wire \\not_strict_mode.app_rd_data_reg[0] ;\n wire \\not_strict_mode.app_rd_data_reg[100] ;\n wire \\not_strict_mode.app_rd_data_reg[101] ;\n wire \\not_strict_mode.app_rd_data_reg[102] ;\n wire \\not_strict_mode.app_rd_data_reg[103] ;\n wire \\not_strict_mode.app_rd_data_reg[104] ;\n wire \\not_strict_mode.app_rd_data_reg[105] ;\n wire \\not_strict_mode.app_rd_data_reg[106] ;\n wire \\not_strict_mode.app_rd_data_reg[107] ;\n wire \\not_strict_mode.app_rd_data_reg[108] ;\n wire \\not_strict_mode.app_rd_data_reg[109] ;\n wire \\not_strict_mode.app_rd_data_reg[10] ;\n wire \\not_strict_mode.app_rd_data_reg[110] ;\n wire \\not_strict_mode.app_rd_data_reg[111] ;\n wire \\not_strict_mode.app_rd_data_reg[112] ;\n wire \\not_strict_mode.app_rd_data_reg[113] ;\n wire \\not_strict_mode.app_rd_data_reg[114] ;\n wire \\not_strict_mode.app_rd_data_reg[115] ;\n wire \\not_strict_mode.app_rd_data_reg[116] ;\n wire \\not_strict_mode.app_rd_data_reg[117] ;\n wire \\not_strict_mode.app_rd_data_reg[118] ;\n wire \\not_strict_mode.app_rd_data_reg[119] ;\n wire \\not_strict_mode.app_rd_data_reg[11] ;\n wire \\not_strict_mode.app_rd_data_reg[120] ;\n wire \\not_strict_mode.app_rd_data_reg[121] ;\n wire \\not_strict_mode.app_rd_data_reg[122] ;\n wire \\not_strict_mode.app_rd_data_reg[123] ;\n wire \\not_strict_mode.app_rd_data_reg[124] ;\n wire \\not_strict_mode.app_rd_data_reg[125] ;\n wire \\not_strict_mode.app_rd_data_reg[126] ;\n wire \\not_strict_mode.app_rd_data_reg[127] ;\n wire \\not_strict_mode.app_rd_data_reg[128] ;\n wire \\not_strict_mode.app_rd_data_reg[129] ;\n wire \\not_strict_mode.app_rd_data_reg[12] ;\n wire \\not_strict_mode.app_rd_data_reg[130] ;\n wire \\not_strict_mode.app_rd_data_reg[131] ;\n wire \\not_strict_mode.app_rd_data_reg[132] ;\n wire \\not_strict_mode.app_rd_data_reg[133] ;\n wire \\not_strict_mode.app_rd_data_reg[134] ;\n wire \\not_strict_mode.app_rd_data_reg[135] ;\n wire \\not_strict_mode.app_rd_data_reg[136] ;\n wire \\not_strict_mode.app_rd_data_reg[137] ;\n wire \\not_strict_mode.app_rd_data_reg[138] ;\n wire \\not_strict_mode.app_rd_data_reg[139] ;\n wire \\not_strict_mode.app_rd_data_reg[13] ;\n wire \\not_strict_mode.app_rd_data_reg[140] ;\n wire \\not_strict_mode.app_rd_data_reg[141] ;\n wire \\not_strict_mode.app_rd_data_reg[142] ;\n wire \\not_strict_mode.app_rd_data_reg[143] ;\n wire \\not_strict_mode.app_rd_data_reg[144] ;\n wire \\not_strict_mode.app_rd_data_reg[145] ;\n wire \\not_strict_mode.app_rd_data_reg[146] ;\n wire \\not_strict_mode.app_rd_data_reg[147] ;\n wire \\not_strict_mode.app_rd_data_reg[148] ;\n wire \\not_strict_mode.app_rd_data_reg[149] ;\n wire \\not_strict_mode.app_rd_data_reg[14] ;\n wire \\not_strict_mode.app_rd_data_reg[150] ;\n wire \\not_strict_mode.app_rd_data_reg[151] ;\n wire \\not_strict_mode.app_rd_data_reg[152] ;\n wire \\not_strict_mode.app_rd_data_reg[153] ;\n wire \\not_strict_mode.app_rd_data_reg[154] ;\n wire \\not_strict_mode.app_rd_data_reg[155] ;\n wire \\not_strict_mode.app_rd_data_reg[156] ;\n wire \\not_strict_mode.app_rd_data_reg[157] ;\n wire \\not_strict_mode.app_rd_data_reg[158] ;\n wire \\not_strict_mode.app_rd_data_reg[159] ;\n wire \\not_strict_mode.app_rd_data_reg[15] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[15]_0 ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[15]_1 ;\n wire \\not_strict_mode.app_rd_data_reg[160] ;\n wire \\not_strict_mode.app_rd_data_reg[161] ;\n wire \\not_strict_mode.app_rd_data_reg[162] ;\n wire \\not_strict_mode.app_rd_data_reg[163] ;\n wire \\not_strict_mode.app_rd_data_reg[164] ;\n wire \\not_strict_mode.app_rd_data_reg[165] ;\n wire \\not_strict_mode.app_rd_data_reg[166] ;\n wire \\not_strict_mode.app_rd_data_reg[167] ;\n wire \\not_strict_mode.app_rd_data_reg[168] ;\n wire \\not_strict_mode.app_rd_data_reg[169] ;\n wire \\not_strict_mode.app_rd_data_reg[16] ;\n wire \\not_strict_mode.app_rd_data_reg[170] ;\n wire \\not_strict_mode.app_rd_data_reg[171] ;\n wire \\not_strict_mode.app_rd_data_reg[172] ;\n wire \\not_strict_mode.app_rd_data_reg[173] ;\n wire \\not_strict_mode.app_rd_data_reg[174] ;\n wire \\not_strict_mode.app_rd_data_reg[175] ;\n wire \\not_strict_mode.app_rd_data_reg[176] ;\n wire \\not_strict_mode.app_rd_data_reg[177] ;\n wire \\not_strict_mode.app_rd_data_reg[178] ;\n wire \\not_strict_mode.app_rd_data_reg[179] ;\n wire \\not_strict_mode.app_rd_data_reg[17] ;\n wire \\not_strict_mode.app_rd_data_reg[180] ;\n wire \\not_strict_mode.app_rd_data_reg[181] ;\n wire \\not_strict_mode.app_rd_data_reg[182] ;\n wire \\not_strict_mode.app_rd_data_reg[183] ;\n wire \\not_strict_mode.app_rd_data_reg[184] ;\n wire \\not_strict_mode.app_rd_data_reg[185] ;\n wire \\not_strict_mode.app_rd_data_reg[186] ;\n wire \\not_strict_mode.app_rd_data_reg[187] ;\n wire \\not_strict_mode.app_rd_data_reg[188] ;\n wire \\not_strict_mode.app_rd_data_reg[189] ;\n wire \\not_strict_mode.app_rd_data_reg[18] ;\n wire \\not_strict_mode.app_rd_data_reg[190] ;\n wire \\not_strict_mode.app_rd_data_reg[191] ;\n wire \\not_strict_mode.app_rd_data_reg[192] ;\n wire \\not_strict_mode.app_rd_data_reg[193] ;\n wire \\not_strict_mode.app_rd_data_reg[194] ;\n wire \\not_strict_mode.app_rd_data_reg[195] ;\n wire \\not_strict_mode.app_rd_data_reg[196] ;\n wire \\not_strict_mode.app_rd_data_reg[197] ;\n wire \\not_strict_mode.app_rd_data_reg[198] ;\n wire \\not_strict_mode.app_rd_data_reg[199] ;\n wire \\not_strict_mode.app_rd_data_reg[19] ;\n wire \\not_strict_mode.app_rd_data_reg[1] ;\n wire \\not_strict_mode.app_rd_data_reg[200] ;\n wire \\not_strict_mode.app_rd_data_reg[201] ;\n wire \\not_strict_mode.app_rd_data_reg[202] ;\n wire \\not_strict_mode.app_rd_data_reg[203] ;\n wire \\not_strict_mode.app_rd_data_reg[204] ;\n wire \\not_strict_mode.app_rd_data_reg[205] ;\n wire \\not_strict_mode.app_rd_data_reg[206] ;\n wire \\not_strict_mode.app_rd_data_reg[207] ;\n wire \\not_strict_mode.app_rd_data_reg[208] ;\n wire \\not_strict_mode.app_rd_data_reg[209] ;\n wire \\not_strict_mode.app_rd_data_reg[20] ;\n wire \\not_strict_mode.app_rd_data_reg[210] ;\n wire \\not_strict_mode.app_rd_data_reg[211] ;\n wire \\not_strict_mode.app_rd_data_reg[212] ;\n wire \\not_strict_mode.app_rd_data_reg[213] ;\n wire \\not_strict_mode.app_rd_data_reg[214] ;\n wire \\not_strict_mode.app_rd_data_reg[215] ;\n wire \\not_strict_mode.app_rd_data_reg[216] ;\n wire \\not_strict_mode.app_rd_data_reg[217] ;\n wire \\not_strict_mode.app_rd_data_reg[218] ;\n wire \\not_strict_mode.app_rd_data_reg[219] ;\n wire \\not_strict_mode.app_rd_data_reg[21] ;\n wire \\not_strict_mode.app_rd_data_reg[220] ;\n wire \\not_strict_mode.app_rd_data_reg[221] ;\n wire \\not_strict_mode.app_rd_data_reg[222] ;\n wire \\not_strict_mode.app_rd_data_reg[223] ;\n wire \\not_strict_mode.app_rd_data_reg[224] ;\n wire \\not_strict_mode.app_rd_data_reg[225] ;\n wire \\not_strict_mode.app_rd_data_reg[226] ;\n wire \\not_strict_mode.app_rd_data_reg[227] ;\n wire \\not_strict_mode.app_rd_data_reg[228] ;\n wire \\not_strict_mode.app_rd_data_reg[228]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[229] ;\n wire \\not_strict_mode.app_rd_data_reg[22] ;\n wire \\not_strict_mode.app_rd_data_reg[230] ;\n wire \\not_strict_mode.app_rd_data_reg[231] ;\n wire \\not_strict_mode.app_rd_data_reg[232] ;\n wire \\not_strict_mode.app_rd_data_reg[233] ;\n wire \\not_strict_mode.app_rd_data_reg[234] ;\n wire \\not_strict_mode.app_rd_data_reg[235] ;\n wire \\not_strict_mode.app_rd_data_reg[236] ;\n wire \\not_strict_mode.app_rd_data_reg[236]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[237] ;\n wire \\not_strict_mode.app_rd_data_reg[238] ;\n wire \\not_strict_mode.app_rd_data_reg[239] ;\n wire \\not_strict_mode.app_rd_data_reg[23] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[23]_0 ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[23]_1 ;\n wire \\not_strict_mode.app_rd_data_reg[240] ;\n wire \\not_strict_mode.app_rd_data_reg[241] ;\n wire \\not_strict_mode.app_rd_data_reg[242] ;\n wire \\not_strict_mode.app_rd_data_reg[243] ;\n wire \\not_strict_mode.app_rd_data_reg[244] ;\n wire \\not_strict_mode.app_rd_data_reg[244]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[245] ;\n wire \\not_strict_mode.app_rd_data_reg[246] ;\n wire \\not_strict_mode.app_rd_data_reg[247] ;\n wire \\not_strict_mode.app_rd_data_reg[248] ;\n wire \\not_strict_mode.app_rd_data_reg[249] ;\n wire \\not_strict_mode.app_rd_data_reg[24] ;\n wire \\not_strict_mode.app_rd_data_reg[250] ;\n wire \\not_strict_mode.app_rd_data_reg[251] ;\n wire \\not_strict_mode.app_rd_data_reg[252] ;\n wire \\not_strict_mode.app_rd_data_reg[252]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[253] ;\n wire \\not_strict_mode.app_rd_data_reg[254] ;\n wire \\not_strict_mode.app_rd_data_reg[255] ;\n wire [255:0]\\not_strict_mode.app_rd_data_reg[255]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[25] ;\n wire \\not_strict_mode.app_rd_data_reg[26] ;\n wire \\not_strict_mode.app_rd_data_reg[27] ;\n wire \\not_strict_mode.app_rd_data_reg[28] ;\n wire \\not_strict_mode.app_rd_data_reg[29] ;\n wire \\not_strict_mode.app_rd_data_reg[2] ;\n wire \\not_strict_mode.app_rd_data_reg[30] ;\n wire \\not_strict_mode.app_rd_data_reg[31] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[31]_0 ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[31]_1 ;\n wire \\not_strict_mode.app_rd_data_reg[32] ;\n wire \\not_strict_mode.app_rd_data_reg[33] ;\n wire \\not_strict_mode.app_rd_data_reg[34] ;\n wire \\not_strict_mode.app_rd_data_reg[35] ;\n wire \\not_strict_mode.app_rd_data_reg[36] ;\n wire \\not_strict_mode.app_rd_data_reg[37] ;\n wire \\not_strict_mode.app_rd_data_reg[38] ;\n wire \\not_strict_mode.app_rd_data_reg[39] ;\n wire \\not_strict_mode.app_rd_data_reg[3] ;\n wire \\not_strict_mode.app_rd_data_reg[40] ;\n wire \\not_strict_mode.app_rd_data_reg[41] ;\n wire \\not_strict_mode.app_rd_data_reg[42] ;\n wire \\not_strict_mode.app_rd_data_reg[43] ;\n wire \\not_strict_mode.app_rd_data_reg[44] ;\n wire \\not_strict_mode.app_rd_data_reg[45] ;\n wire \\not_strict_mode.app_rd_data_reg[46] ;\n wire \\not_strict_mode.app_rd_data_reg[47] ;\n wire \\not_strict_mode.app_rd_data_reg[48] ;\n wire \\not_strict_mode.app_rd_data_reg[49] ;\n wire \\not_strict_mode.app_rd_data_reg[4] ;\n wire \\not_strict_mode.app_rd_data_reg[50] ;\n wire \\not_strict_mode.app_rd_data_reg[51] ;\n wire \\not_strict_mode.app_rd_data_reg[52] ;\n wire \\not_strict_mode.app_rd_data_reg[53] ;\n wire \\not_strict_mode.app_rd_data_reg[54] ;\n wire \\not_strict_mode.app_rd_data_reg[55] ;\n wire \\not_strict_mode.app_rd_data_reg[56] ;\n wire \\not_strict_mode.app_rd_data_reg[57] ;\n wire \\not_strict_mode.app_rd_data_reg[58] ;\n wire \\not_strict_mode.app_rd_data_reg[59] ;\n wire \\not_strict_mode.app_rd_data_reg[5] ;\n wire \\not_strict_mode.app_rd_data_reg[60] ;\n wire \\not_strict_mode.app_rd_data_reg[61] ;\n wire \\not_strict_mode.app_rd_data_reg[62] ;\n wire \\not_strict_mode.app_rd_data_reg[63] ;\n wire \\not_strict_mode.app_rd_data_reg[64] ;\n wire \\not_strict_mode.app_rd_data_reg[65] ;\n wire \\not_strict_mode.app_rd_data_reg[66] ;\n wire \\not_strict_mode.app_rd_data_reg[67] ;\n wire \\not_strict_mode.app_rd_data_reg[68] ;\n wire \\not_strict_mode.app_rd_data_reg[69] ;\n wire \\not_strict_mode.app_rd_data_reg[6] ;\n wire \\not_strict_mode.app_rd_data_reg[70] ;\n wire \\not_strict_mode.app_rd_data_reg[71] ;\n wire \\not_strict_mode.app_rd_data_reg[72] ;\n wire \\not_strict_mode.app_rd_data_reg[73] ;\n wire \\not_strict_mode.app_rd_data_reg[74] ;\n wire \\not_strict_mode.app_rd_data_reg[75] ;\n wire \\not_strict_mode.app_rd_data_reg[76] ;\n wire \\not_strict_mode.app_rd_data_reg[77] ;\n wire \\not_strict_mode.app_rd_data_reg[78] ;\n wire \\not_strict_mode.app_rd_data_reg[79] ;\n wire \\not_strict_mode.app_rd_data_reg[7] ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[7]_0 ;\n wire [0:0]\\not_strict_mode.app_rd_data_reg[7]_1 ;\n wire \\not_strict_mode.app_rd_data_reg[80] ;\n wire \\not_strict_mode.app_rd_data_reg[81] ;\n wire \\not_strict_mode.app_rd_data_reg[82] ;\n wire \\not_strict_mode.app_rd_data_reg[83] ;\n wire \\not_strict_mode.app_rd_data_reg[84] ;\n wire \\not_strict_mode.app_rd_data_reg[85] ;\n wire \\not_strict_mode.app_rd_data_reg[86] ;\n wire \\not_strict_mode.app_rd_data_reg[87] ;\n wire \\not_strict_mode.app_rd_data_reg[88] ;\n wire \\not_strict_mode.app_rd_data_reg[89] ;\n wire \\not_strict_mode.app_rd_data_reg[8] ;\n wire \\not_strict_mode.app_rd_data_reg[90] ;\n wire \\not_strict_mode.app_rd_data_reg[91] ;\n wire \\not_strict_mode.app_rd_data_reg[92] ;\n wire \\not_strict_mode.app_rd_data_reg[93] ;\n wire \\not_strict_mode.app_rd_data_reg[94] ;\n wire \\not_strict_mode.app_rd_data_reg[95] ;\n wire \\not_strict_mode.app_rd_data_reg[96] ;\n wire \\not_strict_mode.app_rd_data_reg[97] ;\n wire \\not_strict_mode.app_rd_data_reg[98] ;\n wire \\not_strict_mode.app_rd_data_reg[99] ;\n wire \\not_strict_mode.app_rd_data_reg[9] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ;\n wire \\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n wire [4:2]\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0 ;\n wire [4:2]\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_0 ;\n wire [4:2]\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_3 ;\n wire [4:2]\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_6 ;\n wire ofs_rdy_r_reg;\n wire ofs_rdy_r_reg_0;\n wire out;\n wire p_0_out;\n wire [15:0]phaser_ctl_bus;\n wire phy_control_i_n_0;\n wire phy_control_i_n_1;\n wire phy_control_i_n_14;\n wire phy_control_i_n_15;\n wire phy_control_i_n_16;\n wire phy_control_i_n_17;\n wire phy_ctl_mstr_empty;\n wire phy_ctl_wr_i2;\n wire phy_ctl_wr_i2_reg;\n wire [1:0]phy_encalib;\n wire phy_if_empty_r_reg;\n wire phy_if_reset;\n wire phy_rddata_en;\n wire phy_read_calib;\n wire phy_write_calib;\n wire [3:0]\\pi_dqs_found_lanes_r1_reg[3] ;\n wire pi_en_stg2_f_reg;\n wire pi_en_stg2_f_reg_0;\n wire pi_en_stg2_f_reg_1;\n wire pi_en_stg2_f_reg_2;\n wire pi_phase_locked_all_r1_reg;\n wire [5:0]\\pi_rdval_cnt_reg[5] ;\n wire pi_stg2_f_incdec_reg;\n wire pi_stg2_f_incdec_reg_0;\n wire pi_stg2_f_incdec_reg_1;\n wire pi_stg2_f_incdec_reg_2;\n wire pll_locked;\n wire [8:0]\\po_rdval_cnt_reg[8] ;\n wire [1:0]\\po_stg2_wrcal_cnt_reg[1] ;\n wire prbs_rdlvl_start_reg;\n wire ram_init_done_r;\n wire rclk_delay_11;\n wire \\rclk_delay_reg[10]_srl11_n_0 ;\n wire \\rclk_delay_reg[11]_0 ;\n wire rd_buf_we;\n wire [1:0]\\rd_mux_sel_r_reg[1] ;\n wire [0:0]\\read_fifo.fifo_out_data_r_reg[6] ;\n wire \\read_fifo.fifo_out_data_r_reg[6]_0 ;\n wire \\read_fifo.tail_r_reg[0] ;\n wire [0:0]ref_dll_lock_w;\n wire [0:0]ref_dll_lock_w__0;\n wire rst_primitives;\n wire rst_primitives_reg_0;\n wire rst_primitives_reg_1;\n wire rst_r4;\n wire [0:0]\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ;\n wire rst_sync_r1_reg;\n wire rstdiv0_sync_r1_reg_rep__9;\n wire sync_pulse;\n wire sys_rst;\n wire [0:0]tail_r;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[224] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[225] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[226] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[227] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[228] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[229] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[230] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[231] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[232] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[233] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[234] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[235] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[236] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[237] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[238] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[239] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[240] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[241] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[242] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[243] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[244] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[245] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[246] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[247] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[248] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[249] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[250] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[251] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[252] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[253] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[254] ;\n wire [7:0]\\write_buffer.wr_buf_out_data_reg[255] ;\n wire [31:0]\\write_buffer.wr_buf_out_data_reg[287] ;\n\n FDRE #(\n .INIT(1'b0)) \n A_rst_primitives_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rst_primitives),\n .Q(A_rst_primitives),\n .R(1'b0));\n ddr3_if_mig_7series_v4_0_ddr_byte_lane \\ddr_byte_lane_A.ddr_byte_lane_A \n (.A(A),\n .A_byte_rd_en(A_byte_rd_en),\n .A_rst_primitives(A_rst_primitives),\n .B_byte_rd_en(B_byte_rd_en),\n .CLK(CLK),\n .CLKB0(CLKB0),\n .COUNTERLOADVAL(COUNTERLOADVAL),\n .COUNTERREADVAL(A_pi_counter_read_val),\n .D_byte_rd_en(D_byte_rd_en),\n .E(E),\n .LD0(LD0),\n .PCENABLECALIB(phy_encalib),\n .Q(\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0 ),\n .\\byte_r_reg[0] (\\byte_r_reg[0] ),\n .\\byte_r_reg[1] (\\byte_r_reg[1] ),\n .\\calib_sel_reg[0] (\\calib_sel_reg[0] ),\n .ck_po_stg2_f_en_reg(ck_po_stg2_f_en_reg),\n .ck_po_stg2_f_indec_reg(ck_po_stg2_f_indec_reg),\n .\\data_bytes_r_reg[63] (\\data_bytes_r_reg[63] ),\n .delay_done_r4_reg(delay_done_r4_reg),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 (\\not_strict_mode.app_rd_data_reg[79] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 (\\not_strict_mode.app_rd_data_reg[87] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_2 (\\not_strict_mode.app_rd_data_reg[71] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 (\\not_strict_mode.app_rd_data_reg[111] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 (\\not_strict_mode.app_rd_data_reg[119] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_2 (\\not_strict_mode.app_rd_data_reg[103] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 (\\not_strict_mode.app_rd_data_reg[143] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 (\\not_strict_mode.app_rd_data_reg[151] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_2 (\\not_strict_mode.app_rd_data_reg[135] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 (\\not_strict_mode.app_rd_data_reg[175] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 (\\not_strict_mode.app_rd_data_reg[183] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_2 (\\not_strict_mode.app_rd_data_reg[167] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 (\\not_strict_mode.app_rd_data_reg[207] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 (\\not_strict_mode.app_rd_data_reg[215] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_2 (\\not_strict_mode.app_rd_data_reg[199] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 (\\not_strict_mode.app_rd_data_reg[239] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 (\\not_strict_mode.app_rd_data_reg[247] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_2 (\\not_strict_mode.app_rd_data_reg[231] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\\not_strict_mode.app_rd_data_reg[14] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 (\\not_strict_mode.app_rd_data_reg[22] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 (\\not_strict_mode.app_rd_data_reg[6] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 (\\not_strict_mode.app_rd_data_reg[46] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 (\\not_strict_mode.app_rd_data_reg[54] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 (\\not_strict_mode.app_rd_data_reg[38] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 (\\not_strict_mode.app_rd_data_reg[78] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 (\\not_strict_mode.app_rd_data_reg[86] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 (\\not_strict_mode.app_rd_data_reg[70] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 (\\not_strict_mode.app_rd_data_reg[110] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 (\\not_strict_mode.app_rd_data_reg[118] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 (\\not_strict_mode.app_rd_data_reg[102] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 (\\not_strict_mode.app_rd_data_reg[142] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 (\\not_strict_mode.app_rd_data_reg[150] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 (\\not_strict_mode.app_rd_data_reg[134] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 (\\not_strict_mode.app_rd_data_reg[174] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 (\\not_strict_mode.app_rd_data_reg[182] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 (\\not_strict_mode.app_rd_data_reg[166] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 (\\not_strict_mode.app_rd_data_reg[206] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 (\\not_strict_mode.app_rd_data_reg[214] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 (\\not_strict_mode.app_rd_data_reg[198] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 (\\not_strict_mode.app_rd_data_reg[238] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 (\\not_strict_mode.app_rd_data_reg[246] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 (\\not_strict_mode.app_rd_data_reg[230] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\\not_strict_mode.app_rd_data_reg[13] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 (\\not_strict_mode.app_rd_data_reg[21] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 (\\not_strict_mode.app_rd_data_reg[5] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 (\\not_strict_mode.app_rd_data_reg[45] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 (\\not_strict_mode.app_rd_data_reg[53] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 (\\not_strict_mode.app_rd_data_reg[37] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 (\\not_strict_mode.app_rd_data_reg[77] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 (\\not_strict_mode.app_rd_data_reg[85] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 (\\not_strict_mode.app_rd_data_reg[69] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 (\\not_strict_mode.app_rd_data_reg[109] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 (\\not_strict_mode.app_rd_data_reg[117] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 (\\not_strict_mode.app_rd_data_reg[101] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 (\\not_strict_mode.app_rd_data_reg[141] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 (\\not_strict_mode.app_rd_data_reg[149] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 (\\not_strict_mode.app_rd_data_reg[133] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 (\\not_strict_mode.app_rd_data_reg[173] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 (\\not_strict_mode.app_rd_data_reg[181] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 (\\not_strict_mode.app_rd_data_reg[165] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 (\\not_strict_mode.app_rd_data_reg[205] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 (\\not_strict_mode.app_rd_data_reg[213] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 (\\not_strict_mode.app_rd_data_reg[197] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 (\\not_strict_mode.app_rd_data_reg[237] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 (\\not_strict_mode.app_rd_data_reg[245] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 (\\not_strict_mode.app_rd_data_reg[229] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\\not_strict_mode.app_rd_data_reg[12] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 (\\not_strict_mode.app_rd_data_reg[20] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 (\\not_strict_mode.app_rd_data_reg[4] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 (\\not_strict_mode.app_rd_data_reg[44] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 (\\not_strict_mode.app_rd_data_reg[52] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 (\\not_strict_mode.app_rd_data_reg[36] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 (\\not_strict_mode.app_rd_data_reg[76] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 (\\not_strict_mode.app_rd_data_reg[84] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 (\\not_strict_mode.app_rd_data_reg[68] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 (\\not_strict_mode.app_rd_data_reg[108] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 (\\not_strict_mode.app_rd_data_reg[116] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 (\\not_strict_mode.app_rd_data_reg[100] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 (\\not_strict_mode.app_rd_data_reg[140] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 (\\not_strict_mode.app_rd_data_reg[148] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 (\\not_strict_mode.app_rd_data_reg[132] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 (\\not_strict_mode.app_rd_data_reg[172] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 (\\not_strict_mode.app_rd_data_reg[180] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 (\\not_strict_mode.app_rd_data_reg[164] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 (\\not_strict_mode.app_rd_data_reg[204] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 (\\not_strict_mode.app_rd_data_reg[212] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 (\\not_strict_mode.app_rd_data_reg[196] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 (\\not_strict_mode.app_rd_data_reg[236]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 (\\not_strict_mode.app_rd_data_reg[244]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 (\\not_strict_mode.app_rd_data_reg[228]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\\not_strict_mode.app_rd_data_reg[11] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 (\\not_strict_mode.app_rd_data_reg[19] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 (\\not_strict_mode.app_rd_data_reg[3] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 (\\not_strict_mode.app_rd_data_reg[43] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 (\\not_strict_mode.app_rd_data_reg[51] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 (\\not_strict_mode.app_rd_data_reg[35] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 (\\not_strict_mode.app_rd_data_reg[75] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 (\\not_strict_mode.app_rd_data_reg[83] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 (\\not_strict_mode.app_rd_data_reg[67] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 (\\not_strict_mode.app_rd_data_reg[107] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 (\\not_strict_mode.app_rd_data_reg[115] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 (\\not_strict_mode.app_rd_data_reg[99] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 (\\not_strict_mode.app_rd_data_reg[139] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 (\\not_strict_mode.app_rd_data_reg[147] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 (\\not_strict_mode.app_rd_data_reg[131] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 (\\not_strict_mode.app_rd_data_reg[171] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 (\\not_strict_mode.app_rd_data_reg[179] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 (\\not_strict_mode.app_rd_data_reg[163] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 (\\not_strict_mode.app_rd_data_reg[203] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 (\\not_strict_mode.app_rd_data_reg[211] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 (\\not_strict_mode.app_rd_data_reg[195] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 (\\not_strict_mode.app_rd_data_reg[235] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 (\\not_strict_mode.app_rd_data_reg[243] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 (\\not_strict_mode.app_rd_data_reg[227] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\\not_strict_mode.app_rd_data_reg[10] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 (\\not_strict_mode.app_rd_data_reg[18] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 (\\not_strict_mode.app_rd_data_reg[2] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 (\\not_strict_mode.app_rd_data_reg[42] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 (\\not_strict_mode.app_rd_data_reg[50] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 (\\not_strict_mode.app_rd_data_reg[34] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 (\\not_strict_mode.app_rd_data_reg[74] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 (\\not_strict_mode.app_rd_data_reg[82] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 (\\not_strict_mode.app_rd_data_reg[66] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 (\\not_strict_mode.app_rd_data_reg[106] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 (\\not_strict_mode.app_rd_data_reg[114] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 (\\not_strict_mode.app_rd_data_reg[98] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 (\\not_strict_mode.app_rd_data_reg[138] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 (\\not_strict_mode.app_rd_data_reg[146] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 (\\not_strict_mode.app_rd_data_reg[130] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 (\\not_strict_mode.app_rd_data_reg[170] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 (\\not_strict_mode.app_rd_data_reg[178] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 (\\not_strict_mode.app_rd_data_reg[162] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 (\\not_strict_mode.app_rd_data_reg[202] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 (\\not_strict_mode.app_rd_data_reg[210] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 (\\not_strict_mode.app_rd_data_reg[194] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 (\\not_strict_mode.app_rd_data_reg[234] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 (\\not_strict_mode.app_rd_data_reg[242] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 (\\not_strict_mode.app_rd_data_reg[226] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\\not_strict_mode.app_rd_data_reg[9] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 (\\not_strict_mode.app_rd_data_reg[17] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 (\\not_strict_mode.app_rd_data_reg[1] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 (\\not_strict_mode.app_rd_data_reg[41] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 (\\not_strict_mode.app_rd_data_reg[49] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 (\\not_strict_mode.app_rd_data_reg[33] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 (\\not_strict_mode.app_rd_data_reg[73] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 (\\not_strict_mode.app_rd_data_reg[81] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 (\\not_strict_mode.app_rd_data_reg[65] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 (\\not_strict_mode.app_rd_data_reg[105] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 (\\not_strict_mode.app_rd_data_reg[113] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 (\\not_strict_mode.app_rd_data_reg[97] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 (\\not_strict_mode.app_rd_data_reg[137] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 (\\not_strict_mode.app_rd_data_reg[145] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 (\\not_strict_mode.app_rd_data_reg[129] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 (\\not_strict_mode.app_rd_data_reg[169] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 (\\not_strict_mode.app_rd_data_reg[177] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 (\\not_strict_mode.app_rd_data_reg[161] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 (\\not_strict_mode.app_rd_data_reg[201] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 (\\not_strict_mode.app_rd_data_reg[209] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 (\\not_strict_mode.app_rd_data_reg[193] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 (\\not_strict_mode.app_rd_data_reg[233] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 (\\not_strict_mode.app_rd_data_reg[241] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 (\\not_strict_mode.app_rd_data_reg[225] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (\\not_strict_mode.app_rd_data_reg[8] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 (\\not_strict_mode.app_rd_data_reg[16] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 (\\not_strict_mode.app_rd_data_reg[0] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 (\\not_strict_mode.app_rd_data_reg[40] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 (\\not_strict_mode.app_rd_data_reg[48] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 (\\not_strict_mode.app_rd_data_reg[32] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] (\\not_strict_mode.app_rd_data_reg[72] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 (\\not_strict_mode.app_rd_data_reg[80] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 (\\not_strict_mode.app_rd_data_reg[64] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (\\not_strict_mode.app_rd_data_reg[104] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 (\\not_strict_mode.app_rd_data_reg[112] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 (\\not_strict_mode.app_rd_data_reg[96] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] (\\not_strict_mode.app_rd_data_reg[136] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 (\\not_strict_mode.app_rd_data_reg[144] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 (\\not_strict_mode.app_rd_data_reg[128] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] (\\not_strict_mode.app_rd_data_reg[168] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 (\\not_strict_mode.app_rd_data_reg[176] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 (\\not_strict_mode.app_rd_data_reg[160] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] (\\not_strict_mode.app_rd_data_reg[200] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 (\\not_strict_mode.app_rd_data_reg[208] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 (\\not_strict_mode.app_rd_data_reg[192] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] (\\not_strict_mode.app_rd_data_reg[232] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 (\\not_strict_mode.app_rd_data_reg[240] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 (\\not_strict_mode.app_rd_data_reg[224] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (\\not_strict_mode.app_rd_data_reg[15] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 (\\not_strict_mode.app_rd_data_reg[23] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 (\\not_strict_mode.app_rd_data_reg[7] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 (\\not_strict_mode.app_rd_data_reg[47] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 (\\not_strict_mode.app_rd_data_reg[55] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_2 (\\not_strict_mode.app_rd_data_reg[39] ),\n .\\fine_delay_mod_reg[23] (\\fine_delay_mod_reg[23] ),\n .freq_refclk(freq_refclk),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\gen_byte_sel_div1.calib_in_common_reg ),\n .\\gen_byte_sel_div1.calib_in_common_reg_0 (\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_1 (\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_2 (\\gen_byte_sel_div1.calib_in_common_reg_2 ),\n .\\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] (\\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] (\\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] (\\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] (\\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] (\\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] (\\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] (\\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] (\\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ),\n .\\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),\n .\\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] (\\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] (\\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] (\\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] (\\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] (\\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] (\\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] (\\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] (\\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ),\n .\\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),\n .\\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] (\\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] (\\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] (\\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] (\\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] (\\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] (\\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] (\\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] (\\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ),\n .\\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),\n .\\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] (\\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] (\\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] (\\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] (\\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] (\\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] (\\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] (\\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] (\\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ),\n .\\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),\n .\\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] (\\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] (\\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] (\\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] (\\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] (\\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] (\\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] (\\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] (\\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ),\n .\\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),\n .\\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] (\\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] (\\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] (\\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] (\\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] (\\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] (\\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] (\\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] (\\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ),\n .\\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),\n .\\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] (\\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] (\\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] (\\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] (\\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] (\\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] (\\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] (\\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] (\\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ),\n .\\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),\n .\\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] (\\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] (\\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] (\\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] (\\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] (\\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] (\\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] (\\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] (\\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ),\n .\\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),\n .\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] (\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] ),\n .\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] (\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] ),\n .\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] (\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] ),\n .\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] (\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] ),\n .idelay_inc(idelay_inc),\n .idelay_ld_rst(idelay_ld_rst),\n .if_empty_r(if_empty_r),\n .if_empty_r_0(if_empty_r_5),\n .init_calib_complete_reg_rep(init_calib_complete_reg_rep),\n .mem_dq_in(mem_dq_in[7:0]),\n .mem_dq_out(mem_dq_out[8:0]),\n .mem_dq_ts(mem_dq_ts[8:0]),\n .mem_dqs_in(mem_dqs_in[0]),\n .mem_dqs_out(mem_dqs_out[0]),\n .mem_dqs_ts(mem_dqs_ts[0]),\n .mem_refclk(mem_refclk),\n .mux_wrdata_en(mux_wrdata_en),\n .my_empty(\\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4 [3]),\n .\\my_empty_reg[1] (\\my_empty_reg[1] ),\n .\\my_empty_reg[7] (\\my_empty_reg[7] ),\n .\\not_strict_mode.app_rd_data_reg[120] (\\not_strict_mode.app_rd_data_reg[120] ),\n .\\not_strict_mode.app_rd_data_reg[121] (\\not_strict_mode.app_rd_data_reg[121] ),\n .\\not_strict_mode.app_rd_data_reg[122] (\\not_strict_mode.app_rd_data_reg[122] ),\n .\\not_strict_mode.app_rd_data_reg[123] (\\not_strict_mode.app_rd_data_reg[123] ),\n .\\not_strict_mode.app_rd_data_reg[124] (\\not_strict_mode.app_rd_data_reg[124] ),\n .\\not_strict_mode.app_rd_data_reg[125] (\\not_strict_mode.app_rd_data_reg[125] ),\n .\\not_strict_mode.app_rd_data_reg[126] (\\not_strict_mode.app_rd_data_reg[126] ),\n .\\not_strict_mode.app_rd_data_reg[127] (\\not_strict_mode.app_rd_data_reg[127] ),\n .\\not_strict_mode.app_rd_data_reg[152] (\\not_strict_mode.app_rd_data_reg[152] ),\n .\\not_strict_mode.app_rd_data_reg[153] (\\not_strict_mode.app_rd_data_reg[153] ),\n .\\not_strict_mode.app_rd_data_reg[154] (\\not_strict_mode.app_rd_data_reg[154] ),\n .\\not_strict_mode.app_rd_data_reg[155] (\\not_strict_mode.app_rd_data_reg[155] ),\n .\\not_strict_mode.app_rd_data_reg[156] (\\not_strict_mode.app_rd_data_reg[156] ),\n .\\not_strict_mode.app_rd_data_reg[157] (\\not_strict_mode.app_rd_data_reg[157] ),\n .\\not_strict_mode.app_rd_data_reg[158] (\\not_strict_mode.app_rd_data_reg[158] ),\n .\\not_strict_mode.app_rd_data_reg[159] (\\not_strict_mode.app_rd_data_reg[159] ),\n .\\not_strict_mode.app_rd_data_reg[184] (\\not_strict_mode.app_rd_data_reg[184] ),\n .\\not_strict_mode.app_rd_data_reg[185] (\\not_strict_mode.app_rd_data_reg[185] ),\n .\\not_strict_mode.app_rd_data_reg[186] (\\not_strict_mode.app_rd_data_reg[186] ),\n .\\not_strict_mode.app_rd_data_reg[187] (\\not_strict_mode.app_rd_data_reg[187] ),\n .\\not_strict_mode.app_rd_data_reg[188] (\\not_strict_mode.app_rd_data_reg[188] ),\n .\\not_strict_mode.app_rd_data_reg[189] (\\not_strict_mode.app_rd_data_reg[189] ),\n .\\not_strict_mode.app_rd_data_reg[190] (\\not_strict_mode.app_rd_data_reg[190] ),\n .\\not_strict_mode.app_rd_data_reg[191] (\\not_strict_mode.app_rd_data_reg[191] ),\n .\\not_strict_mode.app_rd_data_reg[216] (\\not_strict_mode.app_rd_data_reg[216] ),\n .\\not_strict_mode.app_rd_data_reg[217] (\\not_strict_mode.app_rd_data_reg[217] ),\n .\\not_strict_mode.app_rd_data_reg[218] (\\not_strict_mode.app_rd_data_reg[218] ),\n .\\not_strict_mode.app_rd_data_reg[219] (\\not_strict_mode.app_rd_data_reg[219] ),\n .\\not_strict_mode.app_rd_data_reg[220] (\\not_strict_mode.app_rd_data_reg[220] ),\n .\\not_strict_mode.app_rd_data_reg[221] (\\not_strict_mode.app_rd_data_reg[221] ),\n .\\not_strict_mode.app_rd_data_reg[222] (\\not_strict_mode.app_rd_data_reg[222] ),\n .\\not_strict_mode.app_rd_data_reg[223] (\\not_strict_mode.app_rd_data_reg[223] ),\n .\\not_strict_mode.app_rd_data_reg[248] (\\not_strict_mode.app_rd_data_reg[248] ),\n .\\not_strict_mode.app_rd_data_reg[249] (\\not_strict_mode.app_rd_data_reg[249] ),\n .\\not_strict_mode.app_rd_data_reg[24] (\\not_strict_mode.app_rd_data_reg[24] ),\n .\\not_strict_mode.app_rd_data_reg[250] (\\not_strict_mode.app_rd_data_reg[250] ),\n .\\not_strict_mode.app_rd_data_reg[251] (\\not_strict_mode.app_rd_data_reg[251] ),\n .\\not_strict_mode.app_rd_data_reg[252] (\\not_strict_mode.app_rd_data_reg[252] ),\n .\\not_strict_mode.app_rd_data_reg[252]_0 (\\not_strict_mode.app_rd_data_reg[252]_0 ),\n .\\not_strict_mode.app_rd_data_reg[253] (\\not_strict_mode.app_rd_data_reg[253] ),\n .\\not_strict_mode.app_rd_data_reg[254] (\\not_strict_mode.app_rd_data_reg[254] ),\n .\\not_strict_mode.app_rd_data_reg[255] (\\not_strict_mode.app_rd_data_reg[255] ),\n .\\not_strict_mode.app_rd_data_reg[255]_0 ({\\not_strict_mode.app_rd_data_reg[255]_0 [255:248],\\not_strict_mode.app_rd_data_reg[255]_0 [223:216],\\not_strict_mode.app_rd_data_reg[255]_0 [191:184],\\not_strict_mode.app_rd_data_reg[255]_0 [159:152],\\not_strict_mode.app_rd_data_reg[255]_0 [127:120],\\not_strict_mode.app_rd_data_reg[255]_0 [95:88],\\not_strict_mode.app_rd_data_reg[255]_0 [63:56],\\not_strict_mode.app_rd_data_reg[255]_0 [31:24]}),\n .\\not_strict_mode.app_rd_data_reg[25] (\\not_strict_mode.app_rd_data_reg[25] ),\n .\\not_strict_mode.app_rd_data_reg[26] (\\not_strict_mode.app_rd_data_reg[26] ),\n .\\not_strict_mode.app_rd_data_reg[27] (\\not_strict_mode.app_rd_data_reg[27] ),\n .\\not_strict_mode.app_rd_data_reg[28] (\\not_strict_mode.app_rd_data_reg[28] ),\n .\\not_strict_mode.app_rd_data_reg[29] (\\not_strict_mode.app_rd_data_reg[29] ),\n .\\not_strict_mode.app_rd_data_reg[30] (\\not_strict_mode.app_rd_data_reg[30] ),\n .\\not_strict_mode.app_rd_data_reg[31] (\\not_strict_mode.app_rd_data_reg[31] ),\n .\\not_strict_mode.app_rd_data_reg[31]_0 (\\not_strict_mode.app_rd_data_reg[31]_0 ),\n .\\not_strict_mode.app_rd_data_reg[31]_1 (\\not_strict_mode.app_rd_data_reg[31]_1 ),\n .\\not_strict_mode.app_rd_data_reg[56] (\\not_strict_mode.app_rd_data_reg[56] ),\n .\\not_strict_mode.app_rd_data_reg[57] (\\not_strict_mode.app_rd_data_reg[57] ),\n .\\not_strict_mode.app_rd_data_reg[58] (\\not_strict_mode.app_rd_data_reg[58] ),\n .\\not_strict_mode.app_rd_data_reg[59] (\\not_strict_mode.app_rd_data_reg[59] ),\n .\\not_strict_mode.app_rd_data_reg[60] (\\not_strict_mode.app_rd_data_reg[60] ),\n .\\not_strict_mode.app_rd_data_reg[61] (\\not_strict_mode.app_rd_data_reg[61] ),\n .\\not_strict_mode.app_rd_data_reg[62] (\\not_strict_mode.app_rd_data_reg[62] ),\n .\\not_strict_mode.app_rd_data_reg[63] (\\not_strict_mode.app_rd_data_reg[63] ),\n .\\not_strict_mode.app_rd_data_reg[88] (\\not_strict_mode.app_rd_data_reg[88] ),\n .\\not_strict_mode.app_rd_data_reg[89] (\\not_strict_mode.app_rd_data_reg[89] ),\n .\\not_strict_mode.app_rd_data_reg[90] (\\not_strict_mode.app_rd_data_reg[90] ),\n .\\not_strict_mode.app_rd_data_reg[91] (\\not_strict_mode.app_rd_data_reg[91] ),\n .\\not_strict_mode.app_rd_data_reg[92] (\\not_strict_mode.app_rd_data_reg[92] ),\n .\\not_strict_mode.app_rd_data_reg[93] (\\not_strict_mode.app_rd_data_reg[93] ),\n .\\not_strict_mode.app_rd_data_reg[94] (\\not_strict_mode.app_rd_data_reg[94] ),\n .\\not_strict_mode.app_rd_data_reg[95] (\\not_strict_mode.app_rd_data_reg[95] ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ),\n .p_0_out(p_0_out),\n .phaser_ctl_bus({phaser_ctl_bus[9:8],phaser_ctl_bus[4],phaser_ctl_bus[0]}),\n .phy_dout({mux_wrdata_mask[31],mux_wrdata_mask[27],mux_wrdata_mask[23],mux_wrdata_mask[19],mux_wrdata_mask[15],mux_wrdata_mask[11],mux_wrdata_mask[7],mux_wrdata_mask[3],mux_wrdata[248],mux_wrdata[216],mux_wrdata[184],mux_wrdata[152],mux_wrdata[120],mux_wrdata[88],mux_wrdata[56],mux_wrdata[24],mux_wrdata[249],mux_wrdata[217],mux_wrdata[185],mux_wrdata[153],mux_wrdata[121],mux_wrdata[89],mux_wrdata[57],mux_wrdata[25],mux_wrdata[250],mux_wrdata[218],mux_wrdata[186],mux_wrdata[154],mux_wrdata[122],mux_wrdata[90],mux_wrdata[58],mux_wrdata[26],mux_wrdata[251],mux_wrdata[219],mux_wrdata[187],mux_wrdata[155],mux_wrdata[123],mux_wrdata[91],mux_wrdata[59],mux_wrdata[27],mux_wrdata[252],mux_wrdata[220],mux_wrdata[188],mux_wrdata[156],mux_wrdata[124],mux_wrdata[92],mux_wrdata[60],mux_wrdata[28],mux_wrdata[253],mux_wrdata[221],mux_wrdata[189],mux_wrdata[157],mux_wrdata[125],mux_wrdata[93],mux_wrdata[61],mux_wrdata[29],mux_wrdata[254],mux_wrdata[222],mux_wrdata[190],mux_wrdata[158],mux_wrdata[126],mux_wrdata[94],mux_wrdata[62],mux_wrdata[30],mux_wrdata[255],mux_wrdata[223],mux_wrdata[191],mux_wrdata[159],mux_wrdata[127],mux_wrdata[95],mux_wrdata[63],mux_wrdata[31]}),\n .phy_if_reset(phy_if_reset),\n .\\pi_dqs_found_lanes_r1_reg[0] (\\pi_dqs_found_lanes_r1_reg[3] [0]),\n .pi_en_stg2_f_reg(pi_en_stg2_f_reg),\n .pi_phase_locked_all_r1_reg(\\ddr_byte_lane_A.ddr_byte_lane_A_n_2 ),\n .pi_stg2_f_incdec_reg(pi_stg2_f_incdec_reg),\n .\\po_counter_read_val_reg[8] (A_po_counter_read_val),\n .\\po_stg2_wrcal_cnt_reg[1] (\\po_stg2_wrcal_cnt_reg[1] ),\n .\\rd_mux_sel_r_reg[1] (\\rd_mux_sel_r_reg[1] ),\n .\\read_fifo.fifo_out_data_r_reg[6] (\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .rst_r4(rst_r4),\n .sync_pulse(sync_pulse),\n .\\wr_ptr_reg[1] (\\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ),\n .\\write_buffer.wr_buf_out_data_reg[248] (\\write_buffer.wr_buf_out_data_reg[248] ),\n .\\write_buffer.wr_buf_out_data_reg[249] (\\write_buffer.wr_buf_out_data_reg[249] ),\n .\\write_buffer.wr_buf_out_data_reg[250] (\\write_buffer.wr_buf_out_data_reg[250] ),\n .\\write_buffer.wr_buf_out_data_reg[251] (\\write_buffer.wr_buf_out_data_reg[251] ),\n .\\write_buffer.wr_buf_out_data_reg[252] (\\write_buffer.wr_buf_out_data_reg[252] ),\n .\\write_buffer.wr_buf_out_data_reg[253] (\\write_buffer.wr_buf_out_data_reg[253] ),\n .\\write_buffer.wr_buf_out_data_reg[254] (\\write_buffer.wr_buf_out_data_reg[254] ),\n .\\write_buffer.wr_buf_out_data_reg[255] (\\write_buffer.wr_buf_out_data_reg[255] ),\n .\\write_buffer.wr_buf_out_data_reg[287] ({\\write_buffer.wr_buf_out_data_reg[287] [31],\\write_buffer.wr_buf_out_data_reg[287] [27],\\write_buffer.wr_buf_out_data_reg[287] [23],\\write_buffer.wr_buf_out_data_reg[287] [19],\\write_buffer.wr_buf_out_data_reg[287] [15],\\write_buffer.wr_buf_out_data_reg[287] [11],\\write_buffer.wr_buf_out_data_reg[287] [7],\\write_buffer.wr_buf_out_data_reg[287] [3]}));\n ddr3_if_mig_7series_v4_0_ddr_byte_lane__parameterized0 \\ddr_byte_lane_B.ddr_byte_lane_B \n (.A_byte_rd_en(A_byte_rd_en),\n .A_rst_primitives(A_rst_primitives),\n .A_rst_primitives_reg(\\ddr_byte_lane_C.ddr_byte_lane_C_n_2 ),\n .A_rst_primitives_reg_0(\\ddr_byte_lane_A.ddr_byte_lane_A_n_2 ),\n .A_rst_primitives_reg_1(\\ddr_byte_lane_D.ddr_byte_lane_D_n_2 ),\n .B_byte_rd_en(B_byte_rd_en),\n .B_rclk(B_rclk),\n .CLK(CLK),\n .CLKB0_7(CLKB0_7),\n .COUNTERREADVAL(B_pi_counter_read_val),\n .D_byte_rd_en(D_byte_rd_en),\n .LD0_3(LD0_3),\n .PCENABLECALIB(phy_encalib),\n .Q(\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_0 ),\n .\\calib_sel_reg[0] (\\calib_sel_reg[0]_0 ),\n .\\calib_sel_reg[0]_0 (\\calib_sel_reg[0]_2 ),\n .\\calib_zero_inputs_reg[0] (\\calib_zero_inputs_reg[0] ),\n .ck_po_stg2_f_en_reg(ck_po_stg2_f_en_reg_0),\n .ck_po_stg2_f_indec_reg(ck_po_stg2_f_indec_reg_0),\n .delay_done_r4_reg(delay_done_r4_reg_0),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),\n .freq_refclk(freq_refclk),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\gen_byte_sel_div1.calib_in_common_reg_3 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_0 (\\gen_byte_sel_div1.calib_in_common_reg_4 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_1 (\\gen_byte_sel_div1.calib_in_common_reg_5 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_2 (\\gen_byte_sel_div1.calib_in_common_reg_6 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_3 (\\gen_byte_sel_div1.calib_in_common_reg_15 ),\n .idelay_inc(idelay_inc),\n .idelay_ld_rst_0(idelay_ld_rst_0),\n .if_empty_r(if_empty_r_2),\n .if_empty_r_0(if_empty_r_5),\n .init_calib_complete_reg_rep(init_calib_complete_reg_rep),\n .mem_dq_in(mem_dq_in[15:8]),\n .mem_dq_out(mem_dq_out[17:9]),\n .mem_dq_ts(mem_dq_ts[17:9]),\n .mem_dqs_in(mem_dqs_in[1]),\n .mem_dqs_out(mem_dqs_out[1]),\n .mem_dqs_ts(mem_dqs_ts[1]),\n .mem_refclk(mem_refclk),\n .mux_rd_valid_r_reg(mux_rd_valid_r_reg),\n .mux_wrdata_en(mux_wrdata_en),\n .my_empty({\\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4 [3],\\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4 [0]}),\n .\\my_empty_reg[1] (\\my_empty_reg[1]_0 ),\n .\\my_empty_reg[4] (\\ddr_byte_lane_D.ddr_byte_lane_D_n_154 ),\n .\\my_empty_reg[7] (\\my_empty_reg[7]_0 ),\n .\\not_strict_mode.app_rd_data_reg[112] (\\not_strict_mode.app_rd_data_reg[112] ),\n .\\not_strict_mode.app_rd_data_reg[113] (\\not_strict_mode.app_rd_data_reg[113] ),\n .\\not_strict_mode.app_rd_data_reg[114] (\\not_strict_mode.app_rd_data_reg[114] ),\n .\\not_strict_mode.app_rd_data_reg[115] (\\not_strict_mode.app_rd_data_reg[115] ),\n .\\not_strict_mode.app_rd_data_reg[116] (\\not_strict_mode.app_rd_data_reg[116] ),\n .\\not_strict_mode.app_rd_data_reg[117] (\\not_strict_mode.app_rd_data_reg[117] ),\n .\\not_strict_mode.app_rd_data_reg[118] (\\not_strict_mode.app_rd_data_reg[118] ),\n .\\not_strict_mode.app_rd_data_reg[119] (\\not_strict_mode.app_rd_data_reg[119] ),\n .\\not_strict_mode.app_rd_data_reg[144] (\\not_strict_mode.app_rd_data_reg[144] ),\n .\\not_strict_mode.app_rd_data_reg[145] (\\not_strict_mode.app_rd_data_reg[145] ),\n .\\not_strict_mode.app_rd_data_reg[146] (\\not_strict_mode.app_rd_data_reg[146] ),\n .\\not_strict_mode.app_rd_data_reg[147] (\\not_strict_mode.app_rd_data_reg[147] ),\n .\\not_strict_mode.app_rd_data_reg[148] (\\not_strict_mode.app_rd_data_reg[148] ),\n .\\not_strict_mode.app_rd_data_reg[149] (\\not_strict_mode.app_rd_data_reg[149] ),\n .\\not_strict_mode.app_rd_data_reg[150] (\\not_strict_mode.app_rd_data_reg[150] ),\n .\\not_strict_mode.app_rd_data_reg[151] (\\not_strict_mode.app_rd_data_reg[151] ),\n .\\not_strict_mode.app_rd_data_reg[16] (\\not_strict_mode.app_rd_data_reg[16] ),\n .\\not_strict_mode.app_rd_data_reg[176] (\\not_strict_mode.app_rd_data_reg[176] ),\n .\\not_strict_mode.app_rd_data_reg[177] (\\not_strict_mode.app_rd_data_reg[177] ),\n .\\not_strict_mode.app_rd_data_reg[178] (\\not_strict_mode.app_rd_data_reg[178] ),\n .\\not_strict_mode.app_rd_data_reg[179] (\\not_strict_mode.app_rd_data_reg[179] ),\n .\\not_strict_mode.app_rd_data_reg[17] (\\not_strict_mode.app_rd_data_reg[17] ),\n .\\not_strict_mode.app_rd_data_reg[180] (\\not_strict_mode.app_rd_data_reg[180] ),\n .\\not_strict_mode.app_rd_data_reg[181] (\\not_strict_mode.app_rd_data_reg[181] ),\n .\\not_strict_mode.app_rd_data_reg[182] (\\not_strict_mode.app_rd_data_reg[182] ),\n .\\not_strict_mode.app_rd_data_reg[183] (\\not_strict_mode.app_rd_data_reg[183] ),\n .\\not_strict_mode.app_rd_data_reg[18] (\\not_strict_mode.app_rd_data_reg[18] ),\n .\\not_strict_mode.app_rd_data_reg[19] (\\not_strict_mode.app_rd_data_reg[19] ),\n .\\not_strict_mode.app_rd_data_reg[208] (\\not_strict_mode.app_rd_data_reg[208] ),\n .\\not_strict_mode.app_rd_data_reg[209] (\\not_strict_mode.app_rd_data_reg[209] ),\n .\\not_strict_mode.app_rd_data_reg[20] (\\not_strict_mode.app_rd_data_reg[20] ),\n .\\not_strict_mode.app_rd_data_reg[210] (\\not_strict_mode.app_rd_data_reg[210] ),\n .\\not_strict_mode.app_rd_data_reg[211] (\\not_strict_mode.app_rd_data_reg[211] ),\n .\\not_strict_mode.app_rd_data_reg[212] (\\not_strict_mode.app_rd_data_reg[212] ),\n .\\not_strict_mode.app_rd_data_reg[213] (\\not_strict_mode.app_rd_data_reg[213] ),\n .\\not_strict_mode.app_rd_data_reg[214] (\\not_strict_mode.app_rd_data_reg[214] ),\n .\\not_strict_mode.app_rd_data_reg[215] (\\not_strict_mode.app_rd_data_reg[215] ),\n .\\not_strict_mode.app_rd_data_reg[21] (\\not_strict_mode.app_rd_data_reg[21] ),\n .\\not_strict_mode.app_rd_data_reg[22] (\\not_strict_mode.app_rd_data_reg[22] ),\n .\\not_strict_mode.app_rd_data_reg[23] (\\not_strict_mode.app_rd_data_reg[23] ),\n .\\not_strict_mode.app_rd_data_reg[23]_0 (\\not_strict_mode.app_rd_data_reg[23]_0 ),\n .\\not_strict_mode.app_rd_data_reg[23]_1 (\\not_strict_mode.app_rd_data_reg[23]_1 ),\n .\\not_strict_mode.app_rd_data_reg[240] (\\not_strict_mode.app_rd_data_reg[240] ),\n .\\not_strict_mode.app_rd_data_reg[241] (\\not_strict_mode.app_rd_data_reg[241] ),\n .\\not_strict_mode.app_rd_data_reg[242] (\\not_strict_mode.app_rd_data_reg[242] ),\n .\\not_strict_mode.app_rd_data_reg[243] (\\not_strict_mode.app_rd_data_reg[243] ),\n .\\not_strict_mode.app_rd_data_reg[244] (\\not_strict_mode.app_rd_data_reg[244] ),\n .\\not_strict_mode.app_rd_data_reg[244]_0 (\\not_strict_mode.app_rd_data_reg[244]_0 ),\n .\\not_strict_mode.app_rd_data_reg[245] (\\not_strict_mode.app_rd_data_reg[245] ),\n .\\not_strict_mode.app_rd_data_reg[246] (\\not_strict_mode.app_rd_data_reg[246] ),\n .\\not_strict_mode.app_rd_data_reg[247] ({\\not_strict_mode.app_rd_data_reg[255]_0 [247:240],\\not_strict_mode.app_rd_data_reg[255]_0 [215:208],\\not_strict_mode.app_rd_data_reg[255]_0 [183:176],\\not_strict_mode.app_rd_data_reg[255]_0 [151:144],\\not_strict_mode.app_rd_data_reg[255]_0 [119:112],\\not_strict_mode.app_rd_data_reg[255]_0 [87:80],\\not_strict_mode.app_rd_data_reg[255]_0 [55:48],\\not_strict_mode.app_rd_data_reg[255]_0 [23:16]}),\n .\\not_strict_mode.app_rd_data_reg[247]_0 (\\not_strict_mode.app_rd_data_reg[247] ),\n .\\not_strict_mode.app_rd_data_reg[48] (\\not_strict_mode.app_rd_data_reg[48] ),\n .\\not_strict_mode.app_rd_data_reg[49] (\\not_strict_mode.app_rd_data_reg[49] ),\n .\\not_strict_mode.app_rd_data_reg[50] (\\not_strict_mode.app_rd_data_reg[50] ),\n .\\not_strict_mode.app_rd_data_reg[51] (\\not_strict_mode.app_rd_data_reg[51] ),\n .\\not_strict_mode.app_rd_data_reg[52] (\\not_strict_mode.app_rd_data_reg[52] ),\n .\\not_strict_mode.app_rd_data_reg[53] (\\not_strict_mode.app_rd_data_reg[53] ),\n .\\not_strict_mode.app_rd_data_reg[54] (\\not_strict_mode.app_rd_data_reg[54] ),\n .\\not_strict_mode.app_rd_data_reg[55] (\\not_strict_mode.app_rd_data_reg[55] ),\n .\\not_strict_mode.app_rd_data_reg[80] (\\not_strict_mode.app_rd_data_reg[80] ),\n .\\not_strict_mode.app_rd_data_reg[81] (\\not_strict_mode.app_rd_data_reg[81] ),\n .\\not_strict_mode.app_rd_data_reg[82] (\\not_strict_mode.app_rd_data_reg[82] ),\n .\\not_strict_mode.app_rd_data_reg[83] (\\not_strict_mode.app_rd_data_reg[83] ),\n .\\not_strict_mode.app_rd_data_reg[84] (\\not_strict_mode.app_rd_data_reg[84] ),\n .\\not_strict_mode.app_rd_data_reg[85] (\\not_strict_mode.app_rd_data_reg[85] ),\n .\\not_strict_mode.app_rd_data_reg[86] (\\not_strict_mode.app_rd_data_reg[86] ),\n .\\not_strict_mode.app_rd_data_reg[87] (\\not_strict_mode.app_rd_data_reg[87] ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ),\n .\\not_strict_mode.status_ram.rd_buf_we_r1_reg (\\not_strict_mode.status_ram.rd_buf_we_r1_reg ),\n .out(out),\n .phaser_ctl_bus({phaser_ctl_bus[11:10],phaser_ctl_bus[5],phaser_ctl_bus[1]}),\n .phy_dout({mux_wrdata_mask[30],mux_wrdata_mask[26],mux_wrdata_mask[22],mux_wrdata_mask[18],mux_wrdata_mask[14],mux_wrdata_mask[10],mux_wrdata_mask[6],mux_wrdata_mask[2],mux_wrdata[240],mux_wrdata[208],mux_wrdata[176],mux_wrdata[144],mux_wrdata[112],mux_wrdata[80],mux_wrdata[48],mux_wrdata[16],mux_wrdata[241],mux_wrdata[209],mux_wrdata[177],mux_wrdata[145],mux_wrdata[113],mux_wrdata[81],mux_wrdata[49],mux_wrdata[17],mux_wrdata[242],mux_wrdata[210],mux_wrdata[178],mux_wrdata[146],mux_wrdata[114],mux_wrdata[82],mux_wrdata[50],mux_wrdata[18],mux_wrdata[243],mux_wrdata[211],mux_wrdata[179],mux_wrdata[147],mux_wrdata[115],mux_wrdata[83],mux_wrdata[51],mux_wrdata[19],mux_wrdata[244],mux_wrdata[212],mux_wrdata[180],mux_wrdata[148],mux_wrdata[116],mux_wrdata[84],mux_wrdata[52],mux_wrdata[20],mux_wrdata[245],mux_wrdata[213],mux_wrdata[181],mux_wrdata[149],mux_wrdata[117],mux_wrdata[85],mux_wrdata[53],mux_wrdata[21],mux_wrdata[246],mux_wrdata[214],mux_wrdata[182],mux_wrdata[150],mux_wrdata[118],mux_wrdata[86],mux_wrdata[54],mux_wrdata[22],mux_wrdata[247],mux_wrdata[215],mux_wrdata[183],mux_wrdata[151],mux_wrdata[119],mux_wrdata[87],mux_wrdata[55],mux_wrdata[23]}),\n .phy_if_empty_r_reg(phy_if_empty_r_reg),\n .phy_if_reset(phy_if_reset),\n .phy_rddata_en(phy_rddata_en),\n .\\pi_dqs_found_lanes_r1_reg[1] (\\pi_dqs_found_lanes_r1_reg[3] [1]),\n .pi_en_stg2_f_reg(pi_en_stg2_f_reg_0),\n .pi_phase_locked_all_r1_reg(pi_phase_locked_all_r1_reg),\n .pi_stg2_f_incdec_reg(pi_stg2_f_incdec_reg_0),\n .\\po_counter_read_val_reg[8] (B_po_counter_read_val),\n .prbs_rdlvl_start_reg(prbs_rdlvl_start_reg),\n .ram_init_done_r(ram_init_done_r),\n .rd_buf_we(rd_buf_we),\n .\\rd_ptr_timing_reg[1] (\\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1 ),\n .\\read_fifo.fifo_out_data_r_reg[6] (\\read_fifo.fifo_out_data_r_reg[6] ),\n .\\read_fifo.fifo_out_data_r_reg[6]_0 (\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .\\read_fifo.tail_r_reg[0] (\\read_fifo.tail_r_reg[0] ),\n .rst_r4(rst_r4),\n .sync_pulse(sync_pulse),\n .tail_r(tail_r),\n .\\write_buffer.wr_buf_out_data_reg[240] (\\write_buffer.wr_buf_out_data_reg[240] ),\n .\\write_buffer.wr_buf_out_data_reg[241] (\\write_buffer.wr_buf_out_data_reg[241] ),\n .\\write_buffer.wr_buf_out_data_reg[242] (\\write_buffer.wr_buf_out_data_reg[242] ),\n .\\write_buffer.wr_buf_out_data_reg[243] (\\write_buffer.wr_buf_out_data_reg[243] ),\n .\\write_buffer.wr_buf_out_data_reg[244] (\\write_buffer.wr_buf_out_data_reg[244] ),\n .\\write_buffer.wr_buf_out_data_reg[245] (\\write_buffer.wr_buf_out_data_reg[245] ),\n .\\write_buffer.wr_buf_out_data_reg[246] (\\write_buffer.wr_buf_out_data_reg[246] ),\n .\\write_buffer.wr_buf_out_data_reg[247] (\\write_buffer.wr_buf_out_data_reg[247] ),\n .\\write_buffer.wr_buf_out_data_reg[286] ({\\write_buffer.wr_buf_out_data_reg[287] [30],\\write_buffer.wr_buf_out_data_reg[287] [26],\\write_buffer.wr_buf_out_data_reg[287] [22],\\write_buffer.wr_buf_out_data_reg[287] [18],\\write_buffer.wr_buf_out_data_reg[287] [14],\\write_buffer.wr_buf_out_data_reg[287] [10],\\write_buffer.wr_buf_out_data_reg[287] [6],\\write_buffer.wr_buf_out_data_reg[287] [2]}));\n ddr3_if_mig_7series_v4_0_ddr_byte_lane__parameterized1 \\ddr_byte_lane_C.ddr_byte_lane_C \n (.A_byte_rd_en(A_byte_rd_en),\n .A_rst_primitives(A_rst_primitives),\n .CLK(CLK),\n .CLKB0_8(CLKB0_8),\n .COUNTERREADVAL(C_pi_counter_read_val),\n .C_byte_rd_en(C_byte_rd_en),\n .D_byte_rd_en(D_byte_rd_en),\n .LD0_4(LD0_4),\n .PCENABLECALIB(phy_encalib),\n .Q(\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_3 ),\n .\\calib_sel_reg[1] (\\calib_sel_reg[1] ),\n .\\calib_sel_reg[1]_0 (\\calib_sel_reg[1]_0 ),\n .\\calib_zero_inputs_reg[0] (\\calib_zero_inputs_reg[0]_0 ),\n .ck_po_stg2_f_en_reg(ck_po_stg2_f_en_reg_1),\n .ck_po_stg2_f_indec_reg(ck_po_stg2_f_indec_reg_1),\n .delay_done_r4_reg(delay_done_r4_reg_1),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),\n .freq_refclk(freq_refclk),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\gen_byte_sel_div1.calib_in_common_reg_7 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_0 (\\gen_byte_sel_div1.calib_in_common_reg_8 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_1 (\\gen_byte_sel_div1.calib_in_common_reg_9 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_2 (\\gen_byte_sel_div1.calib_in_common_reg_10 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_3 (\\gen_byte_sel_div1.calib_in_common_reg_16 ),\n .idelay_inc(idelay_inc),\n .idelay_ld_rst_1(idelay_ld_rst_1),\n .if_empty_r(if_empty_r_5),\n .if_empty_r_0(if_empty_r_2),\n .init_calib_complete_reg_rep(init_calib_complete_reg_rep),\n .mem_dq_in(mem_dq_in[23:16]),\n .mem_dq_out(mem_dq_out[26:18]),\n .mem_dq_ts(mem_dq_ts[26:18]),\n .mem_dqs_in(mem_dqs_in[2]),\n .mem_dqs_out(mem_dqs_out[2]),\n .mem_dqs_ts(mem_dqs_ts[2]),\n .mem_refclk(mem_refclk),\n .mux_wrdata_en(mux_wrdata_en),\n .\\my_empty_reg[1] (\\my_empty_reg[1]_1 ),\n .\\my_empty_reg[4] (\\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1 ),\n .\\my_empty_reg[7] (\\my_empty_reg[7]_1 ),\n .\\not_strict_mode.app_rd_data_reg[104] (\\not_strict_mode.app_rd_data_reg[104] ),\n .\\not_strict_mode.app_rd_data_reg[105] (\\not_strict_mode.app_rd_data_reg[105] ),\n .\\not_strict_mode.app_rd_data_reg[106] (\\not_strict_mode.app_rd_data_reg[106] ),\n .\\not_strict_mode.app_rd_data_reg[107] (\\not_strict_mode.app_rd_data_reg[107] ),\n .\\not_strict_mode.app_rd_data_reg[108] (\\not_strict_mode.app_rd_data_reg[108] ),\n .\\not_strict_mode.app_rd_data_reg[109] (\\not_strict_mode.app_rd_data_reg[109] ),\n .\\not_strict_mode.app_rd_data_reg[10] (\\not_strict_mode.app_rd_data_reg[10] ),\n .\\not_strict_mode.app_rd_data_reg[110] (\\not_strict_mode.app_rd_data_reg[110] ),\n .\\not_strict_mode.app_rd_data_reg[111] (\\not_strict_mode.app_rd_data_reg[111] ),\n .\\not_strict_mode.app_rd_data_reg[11] (\\not_strict_mode.app_rd_data_reg[11] ),\n .\\not_strict_mode.app_rd_data_reg[12] (\\not_strict_mode.app_rd_data_reg[12] ),\n .\\not_strict_mode.app_rd_data_reg[136] (\\not_strict_mode.app_rd_data_reg[136] ),\n .\\not_strict_mode.app_rd_data_reg[137] (\\not_strict_mode.app_rd_data_reg[137] ),\n .\\not_strict_mode.app_rd_data_reg[138] (\\not_strict_mode.app_rd_data_reg[138] ),\n .\\not_strict_mode.app_rd_data_reg[139] (\\not_strict_mode.app_rd_data_reg[139] ),\n .\\not_strict_mode.app_rd_data_reg[13] (\\not_strict_mode.app_rd_data_reg[13] ),\n .\\not_strict_mode.app_rd_data_reg[140] (\\not_strict_mode.app_rd_data_reg[140] ),\n .\\not_strict_mode.app_rd_data_reg[141] (\\not_strict_mode.app_rd_data_reg[141] ),\n .\\not_strict_mode.app_rd_data_reg[142] (\\not_strict_mode.app_rd_data_reg[142] ),\n .\\not_strict_mode.app_rd_data_reg[143] (\\not_strict_mode.app_rd_data_reg[143] ),\n .\\not_strict_mode.app_rd_data_reg[14] (\\not_strict_mode.app_rd_data_reg[14] ),\n .\\not_strict_mode.app_rd_data_reg[15] (\\not_strict_mode.app_rd_data_reg[15] ),\n .\\not_strict_mode.app_rd_data_reg[15]_0 (\\not_strict_mode.app_rd_data_reg[15]_0 ),\n .\\not_strict_mode.app_rd_data_reg[15]_1 (\\not_strict_mode.app_rd_data_reg[15]_1 ),\n .\\not_strict_mode.app_rd_data_reg[168] (\\not_strict_mode.app_rd_data_reg[168] ),\n .\\not_strict_mode.app_rd_data_reg[169] (\\not_strict_mode.app_rd_data_reg[169] ),\n .\\not_strict_mode.app_rd_data_reg[170] (\\not_strict_mode.app_rd_data_reg[170] ),\n .\\not_strict_mode.app_rd_data_reg[171] (\\not_strict_mode.app_rd_data_reg[171] ),\n .\\not_strict_mode.app_rd_data_reg[172] (\\not_strict_mode.app_rd_data_reg[172] ),\n .\\not_strict_mode.app_rd_data_reg[173] (\\not_strict_mode.app_rd_data_reg[173] ),\n .\\not_strict_mode.app_rd_data_reg[174] (\\not_strict_mode.app_rd_data_reg[174] ),\n .\\not_strict_mode.app_rd_data_reg[175] (\\not_strict_mode.app_rd_data_reg[175] ),\n .\\not_strict_mode.app_rd_data_reg[200] (\\not_strict_mode.app_rd_data_reg[200] ),\n .\\not_strict_mode.app_rd_data_reg[201] (\\not_strict_mode.app_rd_data_reg[201] ),\n .\\not_strict_mode.app_rd_data_reg[202] (\\not_strict_mode.app_rd_data_reg[202] ),\n .\\not_strict_mode.app_rd_data_reg[203] (\\not_strict_mode.app_rd_data_reg[203] ),\n .\\not_strict_mode.app_rd_data_reg[204] (\\not_strict_mode.app_rd_data_reg[204] ),\n .\\not_strict_mode.app_rd_data_reg[205] (\\not_strict_mode.app_rd_data_reg[205] ),\n .\\not_strict_mode.app_rd_data_reg[206] (\\not_strict_mode.app_rd_data_reg[206] ),\n .\\not_strict_mode.app_rd_data_reg[207] (\\not_strict_mode.app_rd_data_reg[207] ),\n .\\not_strict_mode.app_rd_data_reg[232] (\\not_strict_mode.app_rd_data_reg[232] ),\n .\\not_strict_mode.app_rd_data_reg[233] (\\not_strict_mode.app_rd_data_reg[233] ),\n .\\not_strict_mode.app_rd_data_reg[234] (\\not_strict_mode.app_rd_data_reg[234] ),\n .\\not_strict_mode.app_rd_data_reg[235] (\\not_strict_mode.app_rd_data_reg[235] ),\n .\\not_strict_mode.app_rd_data_reg[236] (\\not_strict_mode.app_rd_data_reg[236] ),\n .\\not_strict_mode.app_rd_data_reg[236]_0 (\\not_strict_mode.app_rd_data_reg[236]_0 ),\n .\\not_strict_mode.app_rd_data_reg[237] (\\not_strict_mode.app_rd_data_reg[237] ),\n .\\not_strict_mode.app_rd_data_reg[238] (\\not_strict_mode.app_rd_data_reg[238] ),\n .\\not_strict_mode.app_rd_data_reg[239] ({\\not_strict_mode.app_rd_data_reg[255]_0 [239:232],\\not_strict_mode.app_rd_data_reg[255]_0 [207:200],\\not_strict_mode.app_rd_data_reg[255]_0 [175:168],\\not_strict_mode.app_rd_data_reg[255]_0 [143:136],\\not_strict_mode.app_rd_data_reg[255]_0 [111:104],\\not_strict_mode.app_rd_data_reg[255]_0 [79:72],\\not_strict_mode.app_rd_data_reg[255]_0 [47:40],\\not_strict_mode.app_rd_data_reg[255]_0 [15:8]}),\n .\\not_strict_mode.app_rd_data_reg[239]_0 (\\not_strict_mode.app_rd_data_reg[239] ),\n .\\not_strict_mode.app_rd_data_reg[40] (\\not_strict_mode.app_rd_data_reg[40] ),\n .\\not_strict_mode.app_rd_data_reg[41] (\\not_strict_mode.app_rd_data_reg[41] ),\n .\\not_strict_mode.app_rd_data_reg[42] (\\not_strict_mode.app_rd_data_reg[42] ),\n .\\not_strict_mode.app_rd_data_reg[43] (\\not_strict_mode.app_rd_data_reg[43] ),\n .\\not_strict_mode.app_rd_data_reg[44] (\\not_strict_mode.app_rd_data_reg[44] ),\n .\\not_strict_mode.app_rd_data_reg[45] (\\not_strict_mode.app_rd_data_reg[45] ),\n .\\not_strict_mode.app_rd_data_reg[46] (\\not_strict_mode.app_rd_data_reg[46] ),\n .\\not_strict_mode.app_rd_data_reg[47] (\\not_strict_mode.app_rd_data_reg[47] ),\n .\\not_strict_mode.app_rd_data_reg[72] (\\not_strict_mode.app_rd_data_reg[72] ),\n .\\not_strict_mode.app_rd_data_reg[73] (\\not_strict_mode.app_rd_data_reg[73] ),\n .\\not_strict_mode.app_rd_data_reg[74] (\\not_strict_mode.app_rd_data_reg[74] ),\n .\\not_strict_mode.app_rd_data_reg[75] (\\not_strict_mode.app_rd_data_reg[75] ),\n .\\not_strict_mode.app_rd_data_reg[76] (\\not_strict_mode.app_rd_data_reg[76] ),\n .\\not_strict_mode.app_rd_data_reg[77] (\\not_strict_mode.app_rd_data_reg[77] ),\n .\\not_strict_mode.app_rd_data_reg[78] (\\not_strict_mode.app_rd_data_reg[78] ),\n .\\not_strict_mode.app_rd_data_reg[79] (\\not_strict_mode.app_rd_data_reg[79] ),\n .\\not_strict_mode.app_rd_data_reg[8] (\\not_strict_mode.app_rd_data_reg[8] ),\n .\\not_strict_mode.app_rd_data_reg[9] (\\not_strict_mode.app_rd_data_reg[9] ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ),\n .phaser_ctl_bus({phaser_ctl_bus[13:12],phaser_ctl_bus[6],phaser_ctl_bus[2]}),\n .phy_dout({mux_wrdata_mask[29],mux_wrdata_mask[25],mux_wrdata_mask[21],mux_wrdata_mask[17],mux_wrdata_mask[13],mux_wrdata_mask[9],mux_wrdata_mask[5],mux_wrdata_mask[1],mux_wrdata[232],mux_wrdata[200],mux_wrdata[168],mux_wrdata[136],mux_wrdata[104],mux_wrdata[72],mux_wrdata[40],mux_wrdata[8],mux_wrdata[233],mux_wrdata[201],mux_wrdata[169],mux_wrdata[137],mux_wrdata[105],mux_wrdata[73],mux_wrdata[41],mux_wrdata[9],mux_wrdata[234],mux_wrdata[202],mux_wrdata[170],mux_wrdata[138],mux_wrdata[106],mux_wrdata[74],mux_wrdata[42],mux_wrdata[10],mux_wrdata[235],mux_wrdata[203],mux_wrdata[171],mux_wrdata[139],mux_wrdata[107],mux_wrdata[75],mux_wrdata[43],mux_wrdata[11],mux_wrdata[236],mux_wrdata[204],mux_wrdata[172],mux_wrdata[140],mux_wrdata[108],mux_wrdata[76],mux_wrdata[44],mux_wrdata[12],mux_wrdata[237],mux_wrdata[205],mux_wrdata[173],mux_wrdata[141],mux_wrdata[109],mux_wrdata[77],mux_wrdata[45],mux_wrdata[13],mux_wrdata[238],mux_wrdata[206],mux_wrdata[174],mux_wrdata[142],mux_wrdata[110],mux_wrdata[78],mux_wrdata[46],mux_wrdata[14],mux_wrdata[239],mux_wrdata[207],mux_wrdata[175],mux_wrdata[143],mux_wrdata[111],mux_wrdata[79],mux_wrdata[47],mux_wrdata[15]}),\n .phy_if_reset(phy_if_reset),\n .\\pi_dqs_found_lanes_r1_reg[2] (\\pi_dqs_found_lanes_r1_reg[3] [2]),\n .pi_en_stg2_f_reg(pi_en_stg2_f_reg_1),\n .pi_phase_locked_all_r1_reg(\\ddr_byte_lane_C.ddr_byte_lane_C_n_2 ),\n .pi_stg2_f_incdec_reg(pi_stg2_f_incdec_reg_1),\n .\\po_counter_read_val_reg[8] (C_po_counter_read_val),\n .\\rd_ptr_timing_reg[1] ({\\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4 [3],\\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4 [0]}),\n .\\read_fifo.fifo_out_data_r_reg[6] (\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .rst_r4(rst_r4),\n .sync_pulse(sync_pulse),\n .\\write_buffer.wr_buf_out_data_reg[232] (\\write_buffer.wr_buf_out_data_reg[232] ),\n .\\write_buffer.wr_buf_out_data_reg[233] (\\write_buffer.wr_buf_out_data_reg[233] ),\n .\\write_buffer.wr_buf_out_data_reg[234] (\\write_buffer.wr_buf_out_data_reg[234] ),\n .\\write_buffer.wr_buf_out_data_reg[235] (\\write_buffer.wr_buf_out_data_reg[235] ),\n .\\write_buffer.wr_buf_out_data_reg[236] (\\write_buffer.wr_buf_out_data_reg[236] ),\n .\\write_buffer.wr_buf_out_data_reg[237] (\\write_buffer.wr_buf_out_data_reg[237] ),\n .\\write_buffer.wr_buf_out_data_reg[238] (\\write_buffer.wr_buf_out_data_reg[238] ),\n .\\write_buffer.wr_buf_out_data_reg[239] (\\write_buffer.wr_buf_out_data_reg[239] ),\n .\\write_buffer.wr_buf_out_data_reg[285] ({\\write_buffer.wr_buf_out_data_reg[287] [29],\\write_buffer.wr_buf_out_data_reg[287] [25],\\write_buffer.wr_buf_out_data_reg[287] [21],\\write_buffer.wr_buf_out_data_reg[287] [17],\\write_buffer.wr_buf_out_data_reg[287] [13],\\write_buffer.wr_buf_out_data_reg[287] [9],\\write_buffer.wr_buf_out_data_reg[287] [5],\\write_buffer.wr_buf_out_data_reg[287] [1]}));\n ddr3_if_mig_7series_v4_0_ddr_byte_lane__parameterized2 \\ddr_byte_lane_D.ddr_byte_lane_D \n (.A_byte_rd_en(A_byte_rd_en),\n .A_rst_primitives(A_rst_primitives),\n .A_rst_primitives_reg(C_pi_counter_read_val),\n .A_rst_primitives_reg_0(A_pi_counter_read_val),\n .A_rst_primitives_reg_1(B_po_counter_read_val),\n .A_rst_primitives_reg_2(C_po_counter_read_val),\n .A_rst_primitives_reg_3(A_po_counter_read_val),\n .CLK(CLK),\n .CLKB0_9(CLKB0_9),\n .COUNTERREADVAL(B_pi_counter_read_val),\n .C_byte_rd_en(C_byte_rd_en),\n .D({\\ddr_byte_lane_D.ddr_byte_lane_D_n_222 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_223 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_224 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_225 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_226 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_227 }),\n .DOA(DOA),\n .DOB(DOB),\n .DOC(DOC),\n .D_byte_rd_en(D_byte_rd_en),\n .LD0_5(LD0_5),\n .PCENABLECALIB(phy_encalib),\n .Q(\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_6 ),\n .\\calib_sel_reg[0] (\\calib_sel_reg[0]_1 ),\n .\\calib_sel_reg[0]_0 (\\calib_sel_reg[0]_3 ),\n .\\calib_sel_reg[1] (\\calib_sel_reg[1]_1 ),\n .\\calib_zero_inputs_reg[0] (\\calib_zero_inputs_reg[0]_1 ),\n .ck_po_stg2_f_en_reg(ck_po_stg2_f_en_reg_2),\n .ck_po_stg2_f_indec_reg(ck_po_stg2_f_indec_reg_2),\n .delay_done_r4_reg(delay_done_r4_reg_2),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ),\n .freq_refclk(freq_refclk),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\gen_byte_sel_div1.calib_in_common_reg_11 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_0 (\\gen_byte_sel_div1.calib_in_common_reg_12 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_1 (\\gen_byte_sel_div1.calib_in_common_reg_13 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_2 (\\gen_byte_sel_div1.calib_in_common_reg_14 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_3 (\\gen_byte_sel_div1.calib_in_common_reg_17 ),\n .idelay_inc(idelay_inc),\n .idelay_ld_rst_2(idelay_ld_rst_2),\n .if_empty_r(if_empty_r),\n .if_empty_r_0(if_empty_r_2),\n .init_calib_complete_reg_rep(init_calib_complete_reg_rep),\n .mem_dq_in(mem_dq_in[31:24]),\n .mem_dq_out(mem_dq_out[35:27]),\n .mem_dq_ts(mem_dq_ts[35:27]),\n .mem_dqs_in(mem_dqs_in[3]),\n .mem_dqs_out(mem_dqs_out[3]),\n .mem_dqs_ts(mem_dqs_ts[3]),\n .mem_refclk(mem_refclk),\n .mux_rd_valid_r_reg(\\ddr_byte_lane_D.ddr_byte_lane_D_n_154 ),\n .mux_wrdata_en(mux_wrdata_en),\n .\\my_empty_reg[1] (\\my_empty_reg[1]_2 ),\n .\\my_empty_reg[4] (\\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ),\n .\\my_empty_reg[4]_0 (\\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1 ),\n .\\my_empty_reg[7] (\\my_empty_reg[7]_2 ),\n .\\not_strict_mode.app_rd_data_reg[0] (\\not_strict_mode.app_rd_data_reg[0] ),\n .\\not_strict_mode.app_rd_data_reg[100] (\\not_strict_mode.app_rd_data_reg[100] ),\n .\\not_strict_mode.app_rd_data_reg[101] (\\not_strict_mode.app_rd_data_reg[101] ),\n .\\not_strict_mode.app_rd_data_reg[102] (\\not_strict_mode.app_rd_data_reg[102] ),\n .\\not_strict_mode.app_rd_data_reg[103] (\\not_strict_mode.app_rd_data_reg[103] ),\n .\\not_strict_mode.app_rd_data_reg[128] (\\not_strict_mode.app_rd_data_reg[128] ),\n .\\not_strict_mode.app_rd_data_reg[129] (\\not_strict_mode.app_rd_data_reg[129] ),\n .\\not_strict_mode.app_rd_data_reg[130] (\\not_strict_mode.app_rd_data_reg[130] ),\n .\\not_strict_mode.app_rd_data_reg[131] (\\not_strict_mode.app_rd_data_reg[131] ),\n .\\not_strict_mode.app_rd_data_reg[132] (\\not_strict_mode.app_rd_data_reg[132] ),\n .\\not_strict_mode.app_rd_data_reg[133] (\\not_strict_mode.app_rd_data_reg[133] ),\n .\\not_strict_mode.app_rd_data_reg[134] (\\not_strict_mode.app_rd_data_reg[134] ),\n .\\not_strict_mode.app_rd_data_reg[135] (\\not_strict_mode.app_rd_data_reg[135] ),\n .\\not_strict_mode.app_rd_data_reg[160] (\\not_strict_mode.app_rd_data_reg[160] ),\n .\\not_strict_mode.app_rd_data_reg[161] (\\not_strict_mode.app_rd_data_reg[161] ),\n .\\not_strict_mode.app_rd_data_reg[162] (\\not_strict_mode.app_rd_data_reg[162] ),\n .\\not_strict_mode.app_rd_data_reg[163] (\\not_strict_mode.app_rd_data_reg[163] ),\n .\\not_strict_mode.app_rd_data_reg[164] (\\not_strict_mode.app_rd_data_reg[164] ),\n .\\not_strict_mode.app_rd_data_reg[165] (\\not_strict_mode.app_rd_data_reg[165] ),\n .\\not_strict_mode.app_rd_data_reg[166] (\\not_strict_mode.app_rd_data_reg[166] ),\n .\\not_strict_mode.app_rd_data_reg[167] (\\not_strict_mode.app_rd_data_reg[167] ),\n .\\not_strict_mode.app_rd_data_reg[192] (\\not_strict_mode.app_rd_data_reg[192] ),\n .\\not_strict_mode.app_rd_data_reg[193] (\\not_strict_mode.app_rd_data_reg[193] ),\n .\\not_strict_mode.app_rd_data_reg[194] (\\not_strict_mode.app_rd_data_reg[194] ),\n .\\not_strict_mode.app_rd_data_reg[195] (\\not_strict_mode.app_rd_data_reg[195] ),\n .\\not_strict_mode.app_rd_data_reg[196] (\\not_strict_mode.app_rd_data_reg[196] ),\n .\\not_strict_mode.app_rd_data_reg[197] (\\not_strict_mode.app_rd_data_reg[197] ),\n .\\not_strict_mode.app_rd_data_reg[198] (\\not_strict_mode.app_rd_data_reg[198] ),\n .\\not_strict_mode.app_rd_data_reg[199] (\\not_strict_mode.app_rd_data_reg[199] ),\n .\\not_strict_mode.app_rd_data_reg[1] (\\not_strict_mode.app_rd_data_reg[1] ),\n .\\not_strict_mode.app_rd_data_reg[224] (\\not_strict_mode.app_rd_data_reg[224] ),\n .\\not_strict_mode.app_rd_data_reg[225] (\\not_strict_mode.app_rd_data_reg[225] ),\n .\\not_strict_mode.app_rd_data_reg[226] (\\not_strict_mode.app_rd_data_reg[226] ),\n .\\not_strict_mode.app_rd_data_reg[227] (\\not_strict_mode.app_rd_data_reg[227] ),\n .\\not_strict_mode.app_rd_data_reg[228] (\\not_strict_mode.app_rd_data_reg[228] ),\n .\\not_strict_mode.app_rd_data_reg[228]_0 (\\not_strict_mode.app_rd_data_reg[228]_0 ),\n .\\not_strict_mode.app_rd_data_reg[229] (\\not_strict_mode.app_rd_data_reg[229] ),\n .\\not_strict_mode.app_rd_data_reg[230] (\\not_strict_mode.app_rd_data_reg[230] ),\n .\\not_strict_mode.app_rd_data_reg[231] ({\\not_strict_mode.app_rd_data_reg[255]_0 [231:224],\\not_strict_mode.app_rd_data_reg[255]_0 [199:192],\\not_strict_mode.app_rd_data_reg[255]_0 [167:160],\\not_strict_mode.app_rd_data_reg[255]_0 [135:128],\\not_strict_mode.app_rd_data_reg[255]_0 [103:96],\\not_strict_mode.app_rd_data_reg[255]_0 [71:64],\\not_strict_mode.app_rd_data_reg[255]_0 [39:32],\\not_strict_mode.app_rd_data_reg[255]_0 [7:0]}),\n .\\not_strict_mode.app_rd_data_reg[231]_0 (\\not_strict_mode.app_rd_data_reg[231] ),\n .\\not_strict_mode.app_rd_data_reg[2] (\\not_strict_mode.app_rd_data_reg[2] ),\n .\\not_strict_mode.app_rd_data_reg[32] (\\not_strict_mode.app_rd_data_reg[32] ),\n .\\not_strict_mode.app_rd_data_reg[33] (\\not_strict_mode.app_rd_data_reg[33] ),\n .\\not_strict_mode.app_rd_data_reg[34] (\\not_strict_mode.app_rd_data_reg[34] ),\n .\\not_strict_mode.app_rd_data_reg[35] (\\not_strict_mode.app_rd_data_reg[35] ),\n .\\not_strict_mode.app_rd_data_reg[36] (\\not_strict_mode.app_rd_data_reg[36] ),\n .\\not_strict_mode.app_rd_data_reg[37] (\\not_strict_mode.app_rd_data_reg[37] ),\n .\\not_strict_mode.app_rd_data_reg[38] (\\not_strict_mode.app_rd_data_reg[38] ),\n .\\not_strict_mode.app_rd_data_reg[39] (\\not_strict_mode.app_rd_data_reg[39] ),\n .\\not_strict_mode.app_rd_data_reg[3] (\\not_strict_mode.app_rd_data_reg[3] ),\n .\\not_strict_mode.app_rd_data_reg[4] (\\not_strict_mode.app_rd_data_reg[4] ),\n .\\not_strict_mode.app_rd_data_reg[5] (\\not_strict_mode.app_rd_data_reg[5] ),\n .\\not_strict_mode.app_rd_data_reg[64] (\\not_strict_mode.app_rd_data_reg[64] ),\n .\\not_strict_mode.app_rd_data_reg[65] (\\not_strict_mode.app_rd_data_reg[65] ),\n .\\not_strict_mode.app_rd_data_reg[66] (\\not_strict_mode.app_rd_data_reg[66] ),\n .\\not_strict_mode.app_rd_data_reg[67] (\\not_strict_mode.app_rd_data_reg[67] ),\n .\\not_strict_mode.app_rd_data_reg[68] (\\not_strict_mode.app_rd_data_reg[68] ),\n .\\not_strict_mode.app_rd_data_reg[69] (\\not_strict_mode.app_rd_data_reg[69] ),\n .\\not_strict_mode.app_rd_data_reg[6] (\\not_strict_mode.app_rd_data_reg[6] ),\n .\\not_strict_mode.app_rd_data_reg[70] (\\not_strict_mode.app_rd_data_reg[70] ),\n .\\not_strict_mode.app_rd_data_reg[71] (\\not_strict_mode.app_rd_data_reg[71] ),\n .\\not_strict_mode.app_rd_data_reg[7] (\\not_strict_mode.app_rd_data_reg[7] ),\n .\\not_strict_mode.app_rd_data_reg[7]_0 (\\not_strict_mode.app_rd_data_reg[7]_0 ),\n .\\not_strict_mode.app_rd_data_reg[7]_1 (\\not_strict_mode.app_rd_data_reg[7]_1 ),\n .\\not_strict_mode.app_rd_data_reg[96] (\\not_strict_mode.app_rd_data_reg[96] ),\n .\\not_strict_mode.app_rd_data_reg[97] (\\not_strict_mode.app_rd_data_reg[97] ),\n .\\not_strict_mode.app_rd_data_reg[98] (\\not_strict_mode.app_rd_data_reg[98] ),\n .\\not_strict_mode.app_rd_data_reg[99] (\\not_strict_mode.app_rd_data_reg[99] ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ),\n .phaser_ctl_bus({phaser_ctl_bus[15:14],phaser_ctl_bus[7],phaser_ctl_bus[3]}),\n .phy_dout({mux_wrdata_mask[28],mux_wrdata_mask[24],mux_wrdata_mask[20],mux_wrdata_mask[16],mux_wrdata_mask[12],mux_wrdata_mask[8],mux_wrdata_mask[4],mux_wrdata_mask[0],mux_wrdata[224],mux_wrdata[192],mux_wrdata[160],mux_wrdata[128],mux_wrdata[96],mux_wrdata[64],mux_wrdata[32],mux_wrdata[0],mux_wrdata[225],mux_wrdata[193],mux_wrdata[161],mux_wrdata[129],mux_wrdata[97],mux_wrdata[65],mux_wrdata[33],mux_wrdata[1],mux_wrdata[226],mux_wrdata[194],mux_wrdata[162],mux_wrdata[130],mux_wrdata[98],mux_wrdata[66],mux_wrdata[34],mux_wrdata[2],mux_wrdata[227],mux_wrdata[195],mux_wrdata[163],mux_wrdata[131],mux_wrdata[99],mux_wrdata[67],mux_wrdata[35],mux_wrdata[3],mux_wrdata[228],mux_wrdata[196],mux_wrdata[164],mux_wrdata[132],mux_wrdata[100],mux_wrdata[68],mux_wrdata[36],mux_wrdata[4],mux_wrdata[229],mux_wrdata[197],mux_wrdata[165],mux_wrdata[133],mux_wrdata[101],mux_wrdata[69],mux_wrdata[37],mux_wrdata[5],mux_wrdata[230],mux_wrdata[198],mux_wrdata[166],mux_wrdata[134],mux_wrdata[102],mux_wrdata[70],mux_wrdata[38],mux_wrdata[6],mux_wrdata[231],mux_wrdata[199],mux_wrdata[167],mux_wrdata[135],mux_wrdata[103],mux_wrdata[71],mux_wrdata[39],mux_wrdata[7]}),\n .phy_if_reset(phy_if_reset),\n .\\pi_dqs_found_lanes_r1_reg[3] (\\pi_dqs_found_lanes_r1_reg[3] [3]),\n .pi_en_stg2_f_reg(pi_en_stg2_f_reg_2),\n .pi_phase_locked_all_r1_reg(\\ddr_byte_lane_D.ddr_byte_lane_D_n_2 ),\n .pi_stg2_f_incdec_reg(pi_stg2_f_incdec_reg_2),\n .\\po_counter_read_val_reg[8] ({\\ddr_byte_lane_D.ddr_byte_lane_D_n_228 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_229 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_230 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_231 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_232 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_233 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_234 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_235 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_236 }),\n .\\read_fifo.fifo_out_data_r_reg[6] (\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .rst_r4(rst_r4),\n .sync_pulse(sync_pulse),\n .\\write_buffer.wr_buf_out_data_reg[224] (\\write_buffer.wr_buf_out_data_reg[224] ),\n .\\write_buffer.wr_buf_out_data_reg[225] (\\write_buffer.wr_buf_out_data_reg[225] ),\n .\\write_buffer.wr_buf_out_data_reg[226] (\\write_buffer.wr_buf_out_data_reg[226] ),\n .\\write_buffer.wr_buf_out_data_reg[227] (\\write_buffer.wr_buf_out_data_reg[227] ),\n .\\write_buffer.wr_buf_out_data_reg[228] (\\write_buffer.wr_buf_out_data_reg[228] ),\n .\\write_buffer.wr_buf_out_data_reg[229] (\\write_buffer.wr_buf_out_data_reg[229] ),\n .\\write_buffer.wr_buf_out_data_reg[230] (\\write_buffer.wr_buf_out_data_reg[230] ),\n .\\write_buffer.wr_buf_out_data_reg[231] (\\write_buffer.wr_buf_out_data_reg[231] ),\n .\\write_buffer.wr_buf_out_data_reg[284] ({\\write_buffer.wr_buf_out_data_reg[287] [28],\\write_buffer.wr_buf_out_data_reg[287] [24],\\write_buffer.wr_buf_out_data_reg[287] [20],\\write_buffer.wr_buf_out_data_reg[287] [16],\\write_buffer.wr_buf_out_data_reg[287] [12],\\write_buffer.wr_buf_out_data_reg[287] [8],\\write_buffer.wr_buf_out_data_reg[287] [4],\\write_buffer.wr_buf_out_data_reg[287] [0]}));\n LUT1 #(\n .INIT(2'h2)) \n i_0\n (.I0(1'b0),\n .O(A_pi_rst_div2));\n LUT1 #(\n .INIT(2'h2)) \n i_1\n (.I0(1'b0),\n .O(B_pi_rst_div2));\n LUT1 #(\n .INIT(2'h2)) \n i_2\n (.I0(1'b0),\n .O(C_pi_rst_div2));\n LUT1 #(\n .INIT(2'h2)) \n i_3\n (.I0(1'b0),\n .O(D_pi_rst_div2));\n LUT2 #(\n .INIT(4'h8)) \n \\mcGo_r_reg[13]_srl14___u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_12_i_1 \n (.I0(mcGo_w),\n .I1(mcGo_w__0),\n .O(\\mcGo_r_reg[14]_u_ddr3_if_mig_u_memc_ui_top_axi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_mcGo_r_reg_r_13 ));\n FDRE #(\n .INIT(1'b0)) \n mcGo_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mcGo_reg_0),\n .Q(mcGo_w),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n ofs_rdy_r_i_3\n (.I0(\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_3 [2]),\n .I1(\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_3 [4]),\n .I2(\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_3 [3]),\n .I3(\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_0 [2]),\n .I4(\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_0 [4]),\n .I5(\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_0 [3]),\n .O(ofs_rdy_r_reg_0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n ofs_rdy_r_i_4\n (.I0(\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_6 [2]),\n .I1(\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_6 [4]),\n .I2(\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0_6 [3]),\n .I3(\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0 [2]),\n .I4(\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0 [4]),\n .I5(\\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg__0 [3]),\n .O(ofs_rdy_r_reg));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n PHASER_REF #(\n .IS_PWRDWN_INVERTED(1'b0),\n .IS_RST_INVERTED(1'b0)) \n phaser_ref_i\n (.CLKIN(freq_refclk),\n .LOCKED(ref_dll_lock_w__0),\n .PWRDWN(1'b0),\n .RST(RST0));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n PHY_CONTROL #(\n .AO_TOGGLE(1),\n .BURST_MODE(\"TRUE\"),\n .CLK_RATIO(4),\n .CMD_OFFSET(8),\n .CO_DURATION(1),\n .DATA_CTL_A_N(\"TRUE\"),\n .DATA_CTL_B_N(\"TRUE\"),\n .DATA_CTL_C_N(\"TRUE\"),\n .DATA_CTL_D_N(\"TRUE\"),\n .DISABLE_SEQ_MATCH(\"TRUE\"),\n .DI_DURATION(1),\n .DO_DURATION(1),\n .EVENTS_DELAY(18),\n .FOUR_WINDOW_CLOCKS(63),\n .MULTI_REGION(\"TRUE\"),\n .PHY_COUNT_ENABLE(\"FALSE\"),\n .RD_CMD_OFFSET_0(10),\n .RD_CMD_OFFSET_1(10),\n .RD_CMD_OFFSET_2(10),\n .RD_CMD_OFFSET_3(10),\n .RD_DURATION_0(6),\n .RD_DURATION_1(6),\n .RD_DURATION_2(6),\n .RD_DURATION_3(6),\n .SYNC_MODE(\"FALSE\"),\n .WR_CMD_OFFSET_0(8),\n .WR_CMD_OFFSET_1(8),\n .WR_CMD_OFFSET_2(8),\n .WR_CMD_OFFSET_3(8),\n .WR_DURATION_0(7),\n .WR_DURATION_1(7),\n .WR_DURATION_2(7),\n .WR_DURATION_3(7)) \n phy_control_i\n (.AUXOUTPUT({phy_control_i_n_14,phy_control_i_n_15,phy_control_i_n_16,phy_control_i_n_17}),\n .INBURSTPENDING(phaser_ctl_bus[7:4]),\n .INRANKA(phaser_ctl_bus[9:8]),\n .INRANKB(phaser_ctl_bus[11:10]),\n .INRANKC(phaser_ctl_bus[13:12]),\n .INRANKD(phaser_ctl_bus[15:14]),\n .MEMREFCLK(mem_refclk),\n .OUTBURSTPENDING(phaser_ctl_bus[3:0]),\n .PCENABLECALIB(phy_encalib),\n .PHYCLK(CLK),\n .PHYCTLALMOSTFULL(phy_control_i_n_0),\n .PHYCTLEMPTY(phy_control_i_n_1),\n .PHYCTLFULL(_phy_ctl_full_p__0),\n .PHYCTLMSTREMPTY(phy_ctl_mstr_empty),\n .PHYCTLREADY(rst_primitives_reg_0),\n .PHYCTLWD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,Q[10:3],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,Q[2:0]}),\n .PHYCTLWRENABLE(phy_ctl_wr_i2),\n .PLLLOCK(pll_locked),\n .READCALIBENABLE(phy_read_calib),\n .REFDLLLOCK(ref_dll_lock_w__0),\n .RESET(in0),\n .SYNCIN(sync_pulse),\n .WRITECALIBENABLE(phy_write_calib));\n FDRE \\pi_counter_read_val_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_227 ),\n .Q(\\pi_rdval_cnt_reg[5] [0]),\n .R(1'b0));\n FDRE \\pi_counter_read_val_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_226 ),\n .Q(\\pi_rdval_cnt_reg[5] [1]),\n .R(1'b0));\n FDRE \\pi_counter_read_val_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_225 ),\n .Q(\\pi_rdval_cnt_reg[5] [2]),\n .R(1'b0));\n FDRE \\pi_counter_read_val_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_224 ),\n .Q(\\pi_rdval_cnt_reg[5] [3]),\n .R(1'b0));\n FDRE \\pi_counter_read_val_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_223 ),\n .Q(\\pi_rdval_cnt_reg[5] [4]),\n .R(1'b0));\n FDRE \\pi_counter_read_val_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_222 ),\n .Q(\\pi_rdval_cnt_reg[5] [5]),\n .R(1'b0));\n FDRE \\po_counter_read_val_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_236 ),\n .Q(\\po_rdval_cnt_reg[8] [0]),\n .R(1'b0));\n FDRE \\po_counter_read_val_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_235 ),\n .Q(\\po_rdval_cnt_reg[8] [1]),\n .R(1'b0));\n FDRE \\po_counter_read_val_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_234 ),\n .Q(\\po_rdval_cnt_reg[8] [2]),\n .R(1'b0));\n FDRE \\po_counter_read_val_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_233 ),\n .Q(\\po_rdval_cnt_reg[8] [3]),\n .R(1'b0));\n FDRE \\po_counter_read_val_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_232 ),\n .Q(\\po_rdval_cnt_reg[8] [4]),\n .R(1'b0));\n FDRE \\po_counter_read_val_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_231 ),\n .Q(\\po_rdval_cnt_reg[8] [5]),\n .R(1'b0));\n FDRE \\po_counter_read_val_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_230 ),\n .Q(\\po_rdval_cnt_reg[8] [6]),\n .R(1'b0));\n FDRE \\po_counter_read_val_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_229 ),\n .Q(\\po_rdval_cnt_reg[8] [7]),\n .R(1'b0));\n FDRE \\po_counter_read_val_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_228 ),\n .Q(\\po_rdval_cnt_reg[8] [8]),\n .R(1'b0));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rclk_delay_reg \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rclk_delay_reg[10]_srl11 \" *) \n SRL16E \\rclk_delay_reg[10]_srl11 \n (.A0(1'b0),\n .A1(1'b1),\n .A2(1'b0),\n .A3(1'b1),\n .CE(1'b1),\n .CLK(CLK),\n .D(rst_primitives_reg_1),\n .Q(\\rclk_delay_reg[10]_srl11_n_0 ));\n FDRE \\rclk_delay_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rclk_delay_reg[10]_srl11_n_0 ),\n .Q(rclk_delay_11),\n .R(1'b0));\n FDCE #(\n .INIT(1'b0)) \n rst_out_reg\n (.C(CLK),\n .CE(1'b1),\n .CLR(rstdiv0_sync_r1_reg_rep__9),\n .D(\\rclk_delay_reg[11]_0 ),\n .Q(mcGo_reg_0));\n FDRE #(\n .INIT(1'b0)) \n rst_primitives_reg\n (.C(CLK),\n .CE(1'b1),\n .D(phy_ctl_wr_i2_reg),\n .Q(rst_primitives),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h7FFFFFFF)) \n \\rstdiv2_sync_r[11]_i_1 \n (.I0(ref_dll_lock_w__0),\n .I1(ref_dll_lock_w),\n .I2(sys_rst),\n .I3(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .I4(mmcm_locked),\n .O(rst_sync_r1_reg));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_ddr_phy_4lanes\" *) \nmodule ddr3_if_mig_7series_v4_0_ddr_phy_4lanes__parameterized0\n (\\rd_ptr_timing_reg[2] ,\n \\rd_ptr_timing_reg[2]_0 ,\n \\rd_ptr_timing_reg[2]_1 ,\n \\rd_ptr_timing_reg[2]_2 ,\n \\rd_ptr_timing_reg[2]_3 ,\n \\rd_ptr_timing_reg[2]_4 ,\n \\rd_ptr_timing_reg[2]_5 ,\n \\rd_ptr_timing_reg[2]_6 ,\n \\rd_ptr_timing_reg[2]_7 ,\n \\rd_ptr_timing_reg[2]_8 ,\n \\rd_ptr_timing_reg[2]_9 ,\n \\rd_ptr_timing_reg[2]_10 ,\n phy_ctl_mstr_empty,\n ref_dll_lock_w,\n mcGo_w__0,\n \\my_empty_reg[1] ,\n \\my_empty_reg[1]_0 ,\n phy_mc_ctl_full,\n \\my_empty_reg[1]_1 ,\n \\my_empty_reg[1]_2 ,\n \\byte_r_reg[0] ,\n \\po_counter_read_val_r_reg[5] ,\n of_ctl_full_v,\n wr_en,\n wr_en_5,\n wr_en_6,\n Q,\n \\wr_ptr_timing_reg[2] ,\n \\wr_ptr_timing_reg[2]_0 ,\n mem_dq_out,\n \\po_rdval_cnt_reg[8] ,\n ddr_ck_out,\n \\my_empty_reg[7] ,\n CLK,\n init_calib_complete_reg_rep__6,\n D5,\n D6,\n D2,\n D3,\n \\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ,\n \\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ,\n D7,\n D8,\n D9,\n D0,\n D1,\n \\calib_sel_reg[0] ,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n \\calib_sel_reg[0]_0 ,\n \\calib_sel_reg[0]_1 ,\n freq_refclk,\n mem_refclk,\n \\calib_sel_reg[0]_2 ,\n sync_pulse,\n \\calib_sel_reg[1] ,\n \\gen_byte_sel_div1.calib_in_common_reg_0 ,\n \\calib_sel_reg[1]_0 ,\n \\calib_sel_reg[1]_1 ,\n \\calib_sel_reg[1]_2 ,\n \\calib_sel_reg[1]_3 ,\n \\gen_byte_sel_div1.calib_in_common_reg_1 ,\n \\calib_sel_reg[1]_4 ,\n \\calib_sel_reg[1]_5 ,\n \\calib_sel_reg[1]_6 ,\n phy_ctl_wr_i2,\n pll_locked,\n phy_read_calib,\n in0,\n phy_write_calib,\n PHYCTLWD,\n RST0,\n rstdiv0_sync_r1_reg_rep__9,\n mux_cmd_wren,\n mem_out,\n \\rd_ptr_reg[3] ,\n _phy_ctl_full_p__0,\n \\rd_ptr_reg[3]_0 ,\n init_calib_complete_reg_rep__5,\n mc_cas_n,\n \\cmd_pipe_plus.mc_address_reg[43] ,\n init_calib_complete_reg_rep,\n \\calib_sel_reg[3] ,\n \\po_counter_read_val_reg[5]_0 ,\n D_po_coarse_enable110_out,\n D_po_counter_read_en122_out,\n D_po_fine_enable107_out,\n D_po_fine_inc113_out,\n D_po_sel_fine_oclk_delay125_out,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ,\n D4,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ,\n phy_dout,\n init_calib_complete_reg_rep__6_0);\n output \\rd_ptr_timing_reg[2] ;\n output \\rd_ptr_timing_reg[2]_0 ;\n output \\rd_ptr_timing_reg[2]_1 ;\n output \\rd_ptr_timing_reg[2]_2 ;\n output \\rd_ptr_timing_reg[2]_3 ;\n output \\rd_ptr_timing_reg[2]_4 ;\n output \\rd_ptr_timing_reg[2]_5 ;\n output \\rd_ptr_timing_reg[2]_6 ;\n output \\rd_ptr_timing_reg[2]_7 ;\n output \\rd_ptr_timing_reg[2]_8 ;\n output \\rd_ptr_timing_reg[2]_9 ;\n output \\rd_ptr_timing_reg[2]_10 ;\n output phy_ctl_mstr_empty;\n output [0:0]ref_dll_lock_w;\n output [0:0]mcGo_w__0;\n output \\my_empty_reg[1] ;\n output \\my_empty_reg[1]_0 ;\n output phy_mc_ctl_full;\n output \\my_empty_reg[1]_1 ;\n output \\my_empty_reg[1]_2 ;\n output \\byte_r_reg[0] ;\n output [5:0]\\po_counter_read_val_r_reg[5] ;\n output [0:0]of_ctl_full_v;\n output wr_en;\n output wr_en_5;\n output wr_en_6;\n output [3:0]Q;\n output [3:0]\\wr_ptr_timing_reg[2] ;\n output [3:0]\\wr_ptr_timing_reg[2]_0 ;\n output [23:0]mem_dq_out;\n output [4:0]\\po_rdval_cnt_reg[8] ;\n output [1:0]ddr_ck_out;\n output [31:0]\\my_empty_reg[7] ;\n input CLK;\n input [3:0]init_calib_complete_reg_rep__6;\n input [3:0]D5;\n input [3:0]D6;\n input [2:0]D2;\n input [2:0]D3;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ;\n input [7:0]\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ;\n input [7:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ;\n input [3:0]D7;\n input [3:0]D8;\n input [3:0]D9;\n input [2:0]D0;\n input [2:0]D1;\n input \\calib_sel_reg[0] ;\n input \\gen_byte_sel_div1.calib_in_common_reg ;\n input \\calib_sel_reg[0]_0 ;\n input \\calib_sel_reg[0]_1 ;\n input freq_refclk;\n input mem_refclk;\n input \\calib_sel_reg[0]_2 ;\n input sync_pulse;\n input \\calib_sel_reg[1] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n input \\calib_sel_reg[1]_0 ;\n input \\calib_sel_reg[1]_1 ;\n input \\calib_sel_reg[1]_2 ;\n input \\calib_sel_reg[1]_3 ;\n input \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n input \\calib_sel_reg[1]_4 ;\n input \\calib_sel_reg[1]_5 ;\n input \\calib_sel_reg[1]_6 ;\n input phy_ctl_wr_i2;\n input pll_locked;\n input phy_read_calib;\n input in0;\n input phy_write_calib;\n input [10:0]PHYCTLWD;\n input RST0;\n input rstdiv0_sync_r1_reg_rep__9;\n input mux_cmd_wren;\n input [11:0]mem_out;\n input [33:0]\\rd_ptr_reg[3] ;\n input [0:0]_phy_ctl_full_p__0;\n input [17:0]\\rd_ptr_reg[3]_0 ;\n input init_calib_complete_reg_rep__5;\n input [0:0]mc_cas_n;\n input [1:0]\\cmd_pipe_plus.mc_address_reg[43] ;\n input init_calib_complete_reg_rep;\n input [2:0]\\calib_sel_reg[3] ;\n input [5:0]\\po_counter_read_val_reg[5]_0 ;\n input D_po_coarse_enable110_out;\n input D_po_counter_read_en122_out;\n input D_po_fine_enable107_out;\n input D_po_fine_inc113_out;\n input D_po_sel_fine_oclk_delay125_out;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ;\n input [3:0]D4;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ;\n input [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ;\n input [35:0]phy_dout;\n input init_calib_complete_reg_rep__6_0;\n\n wire A_of_full;\n (* async_reg = \"true\" *) wire A_pi_rst_div2;\n wire [8:0]A_po_counter_read_val;\n wire A_rst_primitives;\n (* async_reg = \"true\" *) wire B_pi_rst_div2;\n wire [8:0]B_po_counter_read_val;\n wire CLK;\n wire C_of_full;\n (* async_reg = \"true\" *) wire C_pi_rst_div2;\n wire [8:0]C_po_counter_read_val;\n wire [2:0]D0;\n wire [2:0]D1;\n wire [2:0]D2;\n wire [2:0]D3;\n wire [3:0]D4;\n wire [3:0]D5;\n wire [3:0]D6;\n wire [3:0]D7;\n wire [3:0]D8;\n wire [3:0]D9;\n wire D_of_full;\n (* async_reg = \"true\" *) wire D_pi_rst_div2;\n wire D_po_coarse_enable110_out;\n wire D_po_counter_read_en122_out;\n wire D_po_fine_enable107_out;\n wire D_po_fine_inc113_out;\n wire D_po_sel_fine_oclk_delay125_out;\n wire [10:0]PHYCTLWD;\n wire [3:0]Q;\n wire RST0;\n wire [1:1]_phy_ctl_full_p;\n wire [0:0]_phy_ctl_full_p__0;\n wire \\byte_r_reg[0] ;\n wire \\calib_sel_reg[0] ;\n wire \\calib_sel_reg[0]_0 ;\n wire \\calib_sel_reg[0]_1 ;\n wire \\calib_sel_reg[0]_2 ;\n wire \\calib_sel_reg[1] ;\n wire \\calib_sel_reg[1]_0 ;\n wire \\calib_sel_reg[1]_1 ;\n wire \\calib_sel_reg[1]_2 ;\n wire \\calib_sel_reg[1]_3 ;\n wire \\calib_sel_reg[1]_4 ;\n wire \\calib_sel_reg[1]_5 ;\n wire \\calib_sel_reg[1]_6 ;\n wire [2:0]\\calib_sel_reg[3] ;\n wire [1:0]\\cmd_pipe_plus.mc_address_reg[43] ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_1 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_2 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_3 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_4 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_5 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_6 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_7 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_8 ;\n wire \\ddr_byte_lane_D.ddr_byte_lane_D_n_9 ;\n wire [1:0]ddr_ck_out;\n wire freq_refclk;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n wire [7:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ;\n wire [3:0]\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ;\n wire [7:0]\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ;\n wire in0;\n wire init_calib_complete_reg_rep;\n wire init_calib_complete_reg_rep__5;\n wire [3:0]init_calib_complete_reg_rep__6;\n wire init_calib_complete_reg_rep__6_0;\n wire [0:0]mcGo_w__0;\n wire [0:0]mc_cas_n;\n wire [23:0]mem_dq_out;\n wire [11:0]mem_out;\n wire mem_refclk;\n wire mux_cmd_wren;\n wire \\my_empty_reg[1] ;\n wire \\my_empty_reg[1]_0 ;\n wire \\my_empty_reg[1]_1 ;\n wire \\my_empty_reg[1]_2 ;\n wire [31:0]\\my_empty_reg[7] ;\n wire [0:0]of_ctl_full_v;\n wire ofifo_rst;\n wire [3:3]phaser_ctl_bus;\n wire phy_control_i_n_0;\n wire phy_control_i_n_10;\n wire phy_control_i_n_11;\n wire phy_control_i_n_14;\n wire phy_control_i_n_15;\n wire phy_control_i_n_16;\n wire phy_control_i_n_17;\n wire phy_control_i_n_18;\n wire phy_control_i_n_19;\n wire phy_control_i_n_20;\n wire phy_control_i_n_21;\n wire phy_control_i_n_23;\n wire phy_control_i_n_24;\n wire phy_control_i_n_25;\n wire phy_control_i_n_3;\n wire phy_control_i_n_4;\n wire phy_control_i_n_5;\n wire phy_control_i_n_6;\n wire phy_control_i_n_7;\n wire phy_control_i_n_8;\n wire phy_control_i_n_9;\n wire phy_ctl_mstr_empty;\n wire phy_ctl_wr_i2;\n wire [35:0]phy_dout;\n wire [1:0]phy_encalib;\n wire phy_mc_ctl_full;\n wire phy_read_calib;\n wire phy_write_calib;\n wire pll_locked;\n wire [5:0]\\po_counter_read_val_r_reg[5] ;\n wire [5:0]\\po_counter_read_val_reg[5]_0 ;\n wire [5:1]\\po_counter_read_val_w[1]_2 ;\n wire [4:0]\\po_rdval_cnt_reg[8] ;\n wire rclk_delay_11;\n wire \\rclk_delay_reg[10]_srl11_i_1__0_n_0 ;\n wire \\rclk_delay_reg[10]_srl11_n_0 ;\n wire [33:0]\\rd_ptr_reg[3] ;\n wire [17:0]\\rd_ptr_reg[3]_0 ;\n wire \\rd_ptr_timing_reg[2] ;\n wire \\rd_ptr_timing_reg[2]_0 ;\n wire \\rd_ptr_timing_reg[2]_1 ;\n wire \\rd_ptr_timing_reg[2]_10 ;\n wire \\rd_ptr_timing_reg[2]_2 ;\n wire \\rd_ptr_timing_reg[2]_3 ;\n wire \\rd_ptr_timing_reg[2]_4 ;\n wire \\rd_ptr_timing_reg[2]_5 ;\n wire \\rd_ptr_timing_reg[2]_6 ;\n wire \\rd_ptr_timing_reg[2]_7 ;\n wire \\rd_ptr_timing_reg[2]_8 ;\n wire \\rd_ptr_timing_reg[2]_9 ;\n wire [0:0]ref_dll_lock_w;\n wire rst_out_i_1__0_n_0;\n wire rst_out_reg_n_0;\n wire rst_primitives;\n wire rst_primitives_i_1__0_n_0;\n wire rstdiv0_sync_r1_reg_rep__9;\n wire sync_pulse;\n wire wr_en;\n wire wr_en_5;\n wire wr_en_6;\n wire [3:0]\\wr_ptr_timing_reg[2] ;\n wire [3:0]\\wr_ptr_timing_reg[2]_0 ;\n\n FDRE #(\n .INIT(1'b0)) \n A_rst_primitives_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rst_primitives),\n .Q(A_rst_primitives),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\byte_r[0]_i_3 \n (.I0(\\po_counter_read_val_r_reg[5] [2]),\n .I1(\\po_counter_read_val_r_reg[5] [5]),\n .I2(\\po_counter_read_val_r_reg[5] [0]),\n .I3(\\po_counter_read_val_r_reg[5] [3]),\n .I4(\\po_counter_read_val_r_reg[5] [1]),\n .I5(\\po_counter_read_val_r_reg[5] [4]),\n .O(\\byte_r_reg[0] ));\n ddr3_if_mig_7series_v4_0_ddr_byte_lane__parameterized3 \\ddr_byte_lane_A.ddr_byte_lane_A \n (.A_of_full(A_of_full),\n .A_rst_primitives(A_rst_primitives),\n .CLK(CLK),\n .COUNTERREADVAL(A_po_counter_read_val),\n .D0(D0),\n .D1(D1),\n .OUTBURSTPENDING(phy_control_i_n_25),\n .PCENABLECALIB(phy_encalib),\n .Q(\\wr_ptr_timing_reg[2]_0 ),\n .SR(ofifo_rst),\n .\\calib_sel_reg[1] (\\calib_sel_reg[1] ),\n .\\calib_sel_reg[1]_0 (\\calib_sel_reg[1]_0 ),\n .\\calib_sel_reg[1]_1 (\\calib_sel_reg[1]_1 ),\n .\\calib_sel_reg[1]_2 (\\calib_sel_reg[1]_2 ),\n .freq_refclk(freq_refclk),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .mem_dq_out(mem_dq_out[1:0]),\n .mem_out(mem_out),\n .mem_refclk(mem_refclk),\n .mux_cmd_wren(mux_cmd_wren),\n .\\my_empty_reg[1] (\\my_empty_reg[1] ),\n .\\rd_ptr_timing_reg[2] (\\rd_ptr_timing_reg[2]_7 ),\n .\\rd_ptr_timing_reg[2]_0 (\\rd_ptr_timing_reg[2]_8 ),\n .\\rd_ptr_timing_reg[2]_1 (\\rd_ptr_timing_reg[2]_9 ),\n .\\rd_ptr_timing_reg[2]_2 (\\rd_ptr_timing_reg[2]_10 ),\n .sync_pulse(sync_pulse),\n .wr_en(wr_en));\n ddr3_if_mig_7series_v4_0_ddr_byte_lane__parameterized4 \\ddr_byte_lane_B.ddr_byte_lane_B \n (.A_of_full(A_of_full),\n .A_rst_primitives(A_rst_primitives),\n .CLK(CLK),\n .COUNTERREADVAL(B_po_counter_read_val),\n .C_of_full(C_of_full),\n .D5(D5),\n .D6(D6),\n .D_of_full(D_of_full),\n .OUTBURSTPENDING(phy_control_i_n_24),\n .PCENABLECALIB(phy_encalib),\n .Q(Q),\n .SR(ofifo_rst),\n .\\calib_sel_reg[1] (\\calib_sel_reg[1]_3 ),\n .\\calib_sel_reg[1]_0 (\\calib_sel_reg[1]_4 ),\n .\\calib_sel_reg[1]_1 (\\calib_sel_reg[1]_5 ),\n .\\calib_sel_reg[1]_2 (\\calib_sel_reg[1]_6 ),\n .freq_refclk(freq_refclk),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6),\n .mem_dq_out(mem_dq_out[4:2]),\n .mem_refclk(mem_refclk),\n .mux_cmd_wren(mux_cmd_wren),\n .\\my_empty_reg[1] (\\my_empty_reg[1]_1 ),\n .of_ctl_full_v(of_ctl_full_v),\n .\\rd_ptr_reg[3] (\\rd_ptr_reg[3]_0 ),\n .\\rd_ptr_timing_reg[2] (\\rd_ptr_timing_reg[2] ),\n .\\rd_ptr_timing_reg[2]_0 (\\rd_ptr_timing_reg[2]_0 ),\n .\\rd_ptr_timing_reg[2]_1 (\\rd_ptr_timing_reg[2]_1 ),\n .\\rd_ptr_timing_reg[2]_2 (\\rd_ptr_timing_reg[2]_2 ),\n .sync_pulse(sync_pulse),\n .wr_en_5(wr_en_5));\n ddr3_if_mig_7series_v4_0_ddr_byte_lane__parameterized5 \\ddr_byte_lane_C.ddr_byte_lane_C \n (.A_rst_primitives(A_rst_primitives),\n .CLK(CLK),\n .COUNTERREADVAL(C_po_counter_read_val),\n .C_of_full(C_of_full),\n .D2(D2),\n .D3(D3),\n .D7(D7),\n .D8(D8),\n .D9(D9),\n .OUTBURSTPENDING(phy_control_i_n_23),\n .PCENABLECALIB(phy_encalib),\n .Q(\\wr_ptr_timing_reg[2] ),\n .SR(ofifo_rst),\n .\\calib_sel_reg[0] (\\calib_sel_reg[0] ),\n .\\calib_sel_reg[0]_0 (\\calib_sel_reg[0]_0 ),\n .\\calib_sel_reg[0]_1 (\\calib_sel_reg[0]_1 ),\n .\\calib_sel_reg[0]_2 (\\calib_sel_reg[0]_2 ),\n .freq_refclk(freq_refclk),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\gen_byte_sel_div1.calib_in_common_reg ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] (\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] (\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ),\n .mem_dq_out(mem_dq_out[14:5]),\n .mem_refclk(mem_refclk),\n .mux_cmd_wren(mux_cmd_wren),\n .\\my_empty_reg[1] (\\my_empty_reg[1]_0 ),\n .\\rd_ptr_reg[3] (\\rd_ptr_reg[3] ),\n .\\rd_ptr_timing_reg[2] (\\rd_ptr_timing_reg[2]_3 ),\n .\\rd_ptr_timing_reg[2]_0 (\\rd_ptr_timing_reg[2]_4 ),\n .\\rd_ptr_timing_reg[2]_1 (\\rd_ptr_timing_reg[2]_5 ),\n .\\rd_ptr_timing_reg[2]_2 (\\rd_ptr_timing_reg[2]_6 ),\n .sync_pulse(sync_pulse),\n .wr_en_6(wr_en_6));\n ddr3_if_mig_7series_v4_0_ddr_byte_lane__parameterized6 \\ddr_byte_lane_D.ddr_byte_lane_D \n (.A_rst_primitives(A_rst_primitives),\n .A_rst_primitives_reg(C_po_counter_read_val),\n .A_rst_primitives_reg_0(A_po_counter_read_val),\n .CLK(CLK),\n .COUNTERREADVAL(B_po_counter_read_val),\n .D({\\ddr_byte_lane_D.ddr_byte_lane_D_n_1 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_2 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_3 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_4 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_5 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_6 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_7 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_8 ,\\ddr_byte_lane_D.ddr_byte_lane_D_n_9 }),\n .D4(D4),\n .D_of_full(D_of_full),\n .D_po_coarse_enable110_out(D_po_coarse_enable110_out),\n .D_po_counter_read_en122_out(D_po_counter_read_en122_out),\n .D_po_fine_enable107_out(D_po_fine_enable107_out),\n .D_po_fine_inc113_out(D_po_fine_inc113_out),\n .D_po_sel_fine_oclk_delay125_out(D_po_sel_fine_oclk_delay125_out),\n .OUTBURSTPENDING(phaser_ctl_bus),\n .PCENABLECALIB(phy_encalib),\n .SR(ofifo_rst),\n .\\calib_sel_reg[1] (\\calib_sel_reg[3] [1:0]),\n .\\cmd_pipe_plus.mc_address_reg[43] (\\cmd_pipe_plus.mc_address_reg[43] ),\n .ddr_ck_out(ddr_ck_out),\n .freq_refclk(freq_refclk),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] (\\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ),\n .init_calib_complete_reg_rep(init_calib_complete_reg_rep),\n .init_calib_complete_reg_rep__5(init_calib_complete_reg_rep__5),\n .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6_0),\n .mc_cas_n(mc_cas_n),\n .mem_dq_out(mem_dq_out[23:15]),\n .mem_refclk(mem_refclk),\n .mux_cmd_wren(mux_cmd_wren),\n .\\my_empty_reg[1] (\\my_empty_reg[1]_2 ),\n .\\my_empty_reg[7] (\\my_empty_reg[7] ),\n .phy_dout(phy_dout),\n .sync_pulse(sync_pulse));\n LUT1 #(\n .INIT(2'h2)) \n i_0\n (.I0(1'b0),\n .O(A_pi_rst_div2));\n LUT1 #(\n .INIT(2'h2)) \n i_1\n (.I0(1'b0),\n .O(B_pi_rst_div2));\n LUT1 #(\n .INIT(2'h2)) \n i_2\n (.I0(1'b0),\n .O(C_pi_rst_div2));\n LUT1 #(\n .INIT(2'h2)) \n i_3\n (.I0(1'b0),\n .O(D_pi_rst_div2));\n FDRE #(\n .INIT(1'b0)) \n mcGo_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rst_out_reg_n_0),\n .Q(mcGo_w__0),\n .R(1'b0));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n PHASER_REF #(\n .IS_PWRDWN_INVERTED(1'b0),\n .IS_RST_INVERTED(1'b0)) \n phaser_ref_i\n (.CLKIN(freq_refclk),\n .LOCKED(ref_dll_lock_w),\n .PWRDWN(1'b0),\n .RST(RST0));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n PHY_CONTROL #(\n .AO_TOGGLE(1),\n .BURST_MODE(\"TRUE\"),\n .CLK_RATIO(4),\n .CMD_OFFSET(8),\n .CO_DURATION(1),\n .DATA_CTL_A_N(\"FALSE\"),\n .DATA_CTL_B_N(\"FALSE\"),\n .DATA_CTL_C_N(\"FALSE\"),\n .DATA_CTL_D_N(\"FALSE\"),\n .DISABLE_SEQ_MATCH(\"TRUE\"),\n .DI_DURATION(1),\n .DO_DURATION(1),\n .EVENTS_DELAY(18),\n .FOUR_WINDOW_CLOCKS(63),\n .MULTI_REGION(\"TRUE\"),\n .PHY_COUNT_ENABLE(\"FALSE\"),\n .RD_CMD_OFFSET_0(10),\n .RD_CMD_OFFSET_1(10),\n .RD_CMD_OFFSET_2(10),\n .RD_CMD_OFFSET_3(10),\n .RD_DURATION_0(6),\n .RD_DURATION_1(6),\n .RD_DURATION_2(6),\n .RD_DURATION_3(6),\n .SYNC_MODE(\"FALSE\"),\n .WR_CMD_OFFSET_0(8),\n .WR_CMD_OFFSET_1(8),\n .WR_CMD_OFFSET_2(8),\n .WR_CMD_OFFSET_3(8),\n .WR_DURATION_0(7),\n .WR_DURATION_1(7),\n .WR_DURATION_2(7),\n .WR_DURATION_3(7)) \n phy_control_i\n (.AUXOUTPUT({phy_control_i_n_14,phy_control_i_n_15,phy_control_i_n_16,phy_control_i_n_17}),\n .INBURSTPENDING({phy_control_i_n_18,phy_control_i_n_19,phy_control_i_n_20,phy_control_i_n_21}),\n .INRANKA({phy_control_i_n_4,phy_control_i_n_5}),\n .INRANKB({phy_control_i_n_6,phy_control_i_n_7}),\n .INRANKC({phy_control_i_n_8,phy_control_i_n_9}),\n .INRANKD({phy_control_i_n_10,phy_control_i_n_11}),\n .MEMREFCLK(mem_refclk),\n .OUTBURSTPENDING({phaser_ctl_bus,phy_control_i_n_23,phy_control_i_n_24,phy_control_i_n_25}),\n .PCENABLECALIB(phy_encalib),\n .PHYCLK(CLK),\n .PHYCTLALMOSTFULL(phy_control_i_n_0),\n .PHYCTLEMPTY(phy_ctl_mstr_empty),\n .PHYCTLFULL(_phy_ctl_full_p),\n .PHYCTLMSTREMPTY(phy_ctl_mstr_empty),\n .PHYCTLREADY(phy_control_i_n_3),\n .PHYCTLWD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,PHYCTLWD[10:3],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PHYCTLWD[2:0]}),\n .PHYCTLWRENABLE(phy_ctl_wr_i2),\n .PLLLOCK(pll_locked),\n .READCALIBENABLE(phy_read_calib),\n .REFDLLLOCK(ref_dll_lock_w),\n .RESET(in0),\n .SYNCIN(sync_pulse),\n .WRITECALIBENABLE(phy_write_calib));\n LUT2 #(\n .INIT(4'hE)) \n phy_mc_ctl_full_r_i_1\n (.I0(_phy_ctl_full_p),\n .I1(_phy_ctl_full_p__0),\n .O(phy_mc_ctl_full));\n (* SOFT_HLUTNM = \"soft_lutpair1022\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\po_counter_read_val_r[0]_i_1 \n (.I0(\\po_rdval_cnt_reg[8] [0]),\n .I1(\\po_counter_read_val_reg[5]_0 [0]),\n .I2(\\calib_sel_reg[3] [2]),\n .O(\\po_counter_read_val_r_reg[5] [0]));\n (* SOFT_HLUTNM = \"soft_lutpair1022\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\po_counter_read_val_r[1]_i_1 \n (.I0(\\po_counter_read_val_w[1]_2 [1]),\n .I1(\\po_counter_read_val_reg[5]_0 [1]),\n .I2(\\calib_sel_reg[3] [2]),\n .O(\\po_counter_read_val_r_reg[5] [1]));\n (* SOFT_HLUTNM = \"soft_lutpair1023\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\po_counter_read_val_r[2]_i_1 \n (.I0(\\po_counter_read_val_w[1]_2 [2]),\n .I1(\\po_counter_read_val_reg[5]_0 [2]),\n .I2(\\calib_sel_reg[3] [2]),\n .O(\\po_counter_read_val_r_reg[5] [2]));\n (* SOFT_HLUTNM = \"soft_lutpair1023\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\po_counter_read_val_r[3]_i_1 \n (.I0(\\po_rdval_cnt_reg[8] [1]),\n .I1(\\po_counter_read_val_reg[5]_0 [3]),\n .I2(\\calib_sel_reg[3] [2]),\n .O(\\po_counter_read_val_r_reg[5] [3]));\n (* SOFT_HLUTNM = \"soft_lutpair1024\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\po_counter_read_val_r[4]_i_1 \n (.I0(\\po_counter_read_val_w[1]_2 [4]),\n .I1(\\po_counter_read_val_reg[5]_0 [4]),\n .I2(\\calib_sel_reg[3] [2]),\n .O(\\po_counter_read_val_r_reg[5] [4]));\n (* SOFT_HLUTNM = \"soft_lutpair1024\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\po_counter_read_val_r[5]_i_1 \n (.I0(\\po_counter_read_val_w[1]_2 [5]),\n .I1(\\po_counter_read_val_reg[5]_0 [5]),\n .I2(\\calib_sel_reg[3] [2]),\n .O(\\po_counter_read_val_r_reg[5] [5]));\n FDRE \\po_counter_read_val_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_9 ),\n .Q(\\po_rdval_cnt_reg[8] [0]),\n .R(1'b0));\n FDRE \\po_counter_read_val_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_8 ),\n .Q(\\po_counter_read_val_w[1]_2 [1]),\n .R(1'b0));\n FDRE \\po_counter_read_val_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_7 ),\n .Q(\\po_counter_read_val_w[1]_2 [2]),\n .R(1'b0));\n FDRE \\po_counter_read_val_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_6 ),\n .Q(\\po_rdval_cnt_reg[8] [1]),\n .R(1'b0));\n FDRE \\po_counter_read_val_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_5 ),\n .Q(\\po_counter_read_val_w[1]_2 [4]),\n .R(1'b0));\n FDRE \\po_counter_read_val_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_4 ),\n .Q(\\po_counter_read_val_w[1]_2 [5]),\n .R(1'b0));\n FDRE \\po_counter_read_val_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_3 ),\n .Q(\\po_rdval_cnt_reg[8] [2]),\n .R(1'b0));\n FDRE \\po_counter_read_val_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_2 ),\n .Q(\\po_rdval_cnt_reg[8] [3]),\n .R(1'b0));\n FDRE \\po_counter_read_val_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ddr_byte_lane_D.ddr_byte_lane_D_n_1 ),\n .Q(\\po_rdval_cnt_reg[8] [4]),\n .R(1'b0));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/rclk_delay_reg \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/rclk_delay_reg[10]_srl11 \" *) \n SRL16E \\rclk_delay_reg[10]_srl11 \n (.A0(1'b0),\n .A1(1'b1),\n .A2(1'b0),\n .A3(1'b1),\n .CE(1'b1),\n .CLK(CLK),\n .D(\\rclk_delay_reg[10]_srl11_i_1__0_n_0 ),\n .Q(\\rclk_delay_reg[10]_srl11_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\rclk_delay_reg[10]_srl11_i_1__0 \n (.I0(rst_primitives),\n .O(\\rclk_delay_reg[10]_srl11_i_1__0_n_0 ));\n FDRE \\rclk_delay_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rclk_delay_reg[10]_srl11_n_0 ),\n .Q(rclk_delay_11),\n .R(1'b0));\n LUT2 #(\n .INIT(4'hE)) \n rst_out_i_1__0\n (.I0(rclk_delay_11),\n .I1(rst_out_reg_n_0),\n .O(rst_out_i_1__0_n_0));\n FDCE #(\n .INIT(1'b0)) \n rst_out_reg\n (.C(CLK),\n .CE(1'b1),\n .CLR(rstdiv0_sync_r1_reg_rep__9),\n .D(rst_out_i_1__0_n_0),\n .Q(rst_out_reg_n_0));\n LUT1 #(\n .INIT(2'h1)) \n rst_primitives_i_1__0\n (.I0(phy_control_i_n_3),\n .O(rst_primitives_i_1__0_n_0));\n FDRE #(\n .INIT(1'b0)) \n rst_primitives_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rst_primitives_i_1__0_n_0),\n .Q(rst_primitives),\n .R(1'b0));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay\n (ck_addr_cmd_delay_done,\n po_en_stg2_f,\n D_po_coarse_enable110_out,\n \\po_counter_read_val_reg[8] ,\n \\po_counter_read_val_reg[8]_0 ,\n \\po_counter_read_val_reg[8]_1 ,\n \\po_counter_read_val_reg[8]_2 ,\n \\po_counter_read_val_reg[8]_3 ,\n \\po_counter_read_val_reg[8]_4 ,\n \\po_counter_read_val_reg[8]_5 ,\n \\wait_cnt_r_reg[0]_0 ,\n \\init_state_r_reg[0] ,\n delay_dec_done_reg_0,\n delay_dec_done_reg_1,\n ctl_lane_cnt,\n po_cnt_inc_reg_0,\n CLK,\n rstdiv0_sync_r1_reg_rep__9,\n \\wait_cnt_r_reg[0]_1 ,\n \\wait_cnt_r_reg[0]_2 ,\n Q,\n calib_in_common,\n dqs_wl_po_stg2_c_incdec,\n \\calib_zero_inputs_reg[1] ,\n cnt_pwron_cke_done_r,\n \\mcGo_r_reg[15] ,\n pi_fine_dly_dec_done,\n dqs_po_dec_done,\n rstdiv0_sync_r1_reg_rep__25,\n rstdiv0_sync_r1_reg_rep__24,\n cmd_delay_start0,\n p_1_in);\n output ck_addr_cmd_delay_done;\n output po_en_stg2_f;\n output D_po_coarse_enable110_out;\n output \\po_counter_read_val_reg[8] ;\n output \\po_counter_read_val_reg[8]_0 ;\n output \\po_counter_read_val_reg[8]_1 ;\n output \\po_counter_read_val_reg[8]_2 ;\n output \\po_counter_read_val_reg[8]_3 ;\n output \\po_counter_read_val_reg[8]_4 ;\n output \\po_counter_read_val_reg[8]_5 ;\n output [0:0]\\wait_cnt_r_reg[0]_0 ;\n output \\init_state_r_reg[0] ;\n output delay_dec_done_reg_0;\n output delay_dec_done_reg_1;\n output [2:0]ctl_lane_cnt;\n output po_cnt_inc_reg_0;\n input CLK;\n input rstdiv0_sync_r1_reg_rep__9;\n input \\wait_cnt_r_reg[0]_1 ;\n input \\wait_cnt_r_reg[0]_2 ;\n input [1:0]Q;\n input calib_in_common;\n input dqs_wl_po_stg2_c_incdec;\n input [1:0]\\calib_zero_inputs_reg[1] ;\n input cnt_pwron_cke_done_r;\n input \\mcGo_r_reg[15] ;\n input pi_fine_dly_dec_done;\n input dqs_po_dec_done;\n input rstdiv0_sync_r1_reg_rep__25;\n input rstdiv0_sync_r1_reg_rep__24;\n input cmd_delay_start0;\n input p_1_in;\n\n wire CLK;\n wire D_po_coarse_enable110_out;\n wire [1:0]Q;\n wire calib_in_common;\n wire [1:0]\\calib_zero_inputs_reg[1] ;\n wire ck_addr_cmd_delay_done;\n wire cmd_delay_start0;\n wire cnt_pwron_cke_done_r;\n wire [2:0]ctl_lane_cnt;\n wire ctl_lane_cnt1;\n wire \\ctl_lane_cnt[0]_i_1_n_0 ;\n wire \\ctl_lane_cnt[1]_i_1_n_0 ;\n wire \\ctl_lane_cnt[2]_i_1_n_0 ;\n wire \\ctl_lane_cnt[2]_i_4_n_0 ;\n wire \\ctl_lane_cnt[3]_i_1_n_0 ;\n wire \\ctl_lane_cnt[3]_i_3_n_0 ;\n wire \\ctl_lane_cnt_reg_n_0_[3] ;\n wire delay_cnt_r0;\n wire \\delay_cnt_r[0]_i_1_n_0 ;\n wire \\delay_cnt_r[0]_i_2_n_0 ;\n wire \\delay_cnt_r[1]_i_1_n_0 ;\n wire \\delay_cnt_r[2]_i_1_n_0 ;\n wire \\delay_cnt_r[3]_i_1_n_0 ;\n wire \\delay_cnt_r[4]_i_1_n_0 ;\n wire \\delay_cnt_r[5]_i_1_n_0 ;\n wire \\delay_cnt_r[5]_i_3_n_0 ;\n wire \\delay_cnt_r[5]_i_5_n_0 ;\n wire \\delay_cnt_r_reg_n_0_[0] ;\n wire \\delay_cnt_r_reg_n_0_[1] ;\n wire \\delay_cnt_r_reg_n_0_[2] ;\n wire \\delay_cnt_r_reg_n_0_[3] ;\n wire \\delay_cnt_r_reg_n_0_[4] ;\n wire \\delay_cnt_r_reg_n_0_[5] ;\n wire delay_dec_done;\n wire delay_dec_done_i_1_n_0;\n wire delay_dec_done_reg_0;\n wire delay_dec_done_reg_1;\n wire delay_done_r3_reg_srl3_n_0;\n wire delaydec_cnt_r0;\n wire delaydec_cnt_r10_in;\n wire \\delaydec_cnt_r[0]_i_1_n_0 ;\n wire \\delaydec_cnt_r[1]_i_1_n_0 ;\n wire \\delaydec_cnt_r[2]_i_1_n_0 ;\n wire \\delaydec_cnt_r[3]_i_1_n_0 ;\n wire \\delaydec_cnt_r[4]_i_1_n_0 ;\n wire \\delaydec_cnt_r[5]_i_1_n_0 ;\n wire \\delaydec_cnt_r[5]_i_3_n_0 ;\n wire [5:0]delaydec_cnt_r_reg__0;\n wire dqs_po_dec_done;\n wire dqs_wl_po_stg2_c_incdec;\n wire \\init_state_r_reg[0] ;\n wire \\mcGo_r_reg[15] ;\n wire p_1_in;\n wire p_3_in;\n wire pi_fine_dly_dec_done;\n wire po_cnt_dec;\n wire po_cnt_inc;\n wire po_cnt_inc_reg_0;\n wire \\po_counter_read_val_reg[8] ;\n wire \\po_counter_read_val_reg[8]_0 ;\n wire \\po_counter_read_val_reg[8]_1 ;\n wire \\po_counter_read_val_reg[8]_2 ;\n wire \\po_counter_read_val_reg[8]_3 ;\n wire \\po_counter_read_val_reg[8]_4 ;\n wire \\po_counter_read_val_reg[8]_5 ;\n wire po_en_stg2_f;\n wire rstdiv0_sync_r1_reg_rep__24;\n wire rstdiv0_sync_r1_reg_rep__25;\n wire rstdiv0_sync_r1_reg_rep__9;\n wire wait_cnt_r0;\n wire [0:0]wait_cnt_r0__0;\n wire \\wait_cnt_r[1]_i_1__0_n_0 ;\n wire \\wait_cnt_r[2]_i_1__1_n_0 ;\n wire \\wait_cnt_r[3]_i_1__0_n_0 ;\n wire \\wait_cnt_r[3]_i_3__0_n_0 ;\n wire [0:0]\\wait_cnt_r_reg[0]_0 ;\n wire \\wait_cnt_r_reg[0]_1 ;\n wire \\wait_cnt_r_reg[0]_2 ;\n wire [3:1]wait_cnt_r_reg__0__0;\n\n LUT6 #(\n .INIT(64'h00000000DE000000)) \n \\ctl_lane_cnt[0]_i_1 \n (.I0(ctl_lane_cnt[0]),\n .I1(ctl_lane_cnt1),\n .I2(delaydec_cnt_r10_in),\n .I3(pi_fine_dly_dec_done),\n .I4(dqs_po_dec_done),\n .I5(rstdiv0_sync_r1_reg_rep__25),\n .O(\\ctl_lane_cnt[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00000000DEEE0000)) \n \\ctl_lane_cnt[1]_i_1 \n (.I0(ctl_lane_cnt[1]),\n .I1(ctl_lane_cnt1),\n .I2(delaydec_cnt_r10_in),\n .I3(ctl_lane_cnt[0]),\n .I4(cmd_delay_start0),\n .I5(rstdiv0_sync_r1_reg_rep__25),\n .O(\\ctl_lane_cnt[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000006AAA)) \n \\ctl_lane_cnt[2]_i_1 \n (.I0(ctl_lane_cnt[2]),\n .I1(delaydec_cnt_r10_in),\n .I2(ctl_lane_cnt[0]),\n .I3(ctl_lane_cnt[1]),\n .I4(p_1_in),\n .I5(ctl_lane_cnt1),\n .O(\\ctl_lane_cnt[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair308\" *) \n LUT4 #(\n .INIT(16'h0004)) \n \\ctl_lane_cnt[2]_i_3 \n (.I0(\\delay_cnt_r[0]_i_2_n_0 ),\n .I1(delaydec_cnt_r_reg__0[0]),\n .I2(delay_dec_done),\n .I3(\\ctl_lane_cnt[2]_i_4_n_0 ),\n .O(ctl_lane_cnt1));\n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n \\ctl_lane_cnt[2]_i_4 \n (.I0(delaydec_cnt_r_reg__0[4]),\n .I1(delaydec_cnt_r_reg__0[2]),\n .I2(delaydec_cnt_r_reg__0[1]),\n .I3(delaydec_cnt_r_reg__0[3]),\n .I4(delaydec_cnt_r_reg__0[5]),\n .O(\\ctl_lane_cnt[2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h000000006AAAAAAA)) \n \\ctl_lane_cnt[3]_i_1 \n (.I0(\\ctl_lane_cnt_reg_n_0_[3] ),\n .I1(delaydec_cnt_r10_in),\n .I2(ctl_lane_cnt[2]),\n .I3(ctl_lane_cnt[1]),\n .I4(ctl_lane_cnt[0]),\n .I5(\\ctl_lane_cnt[3]_i_3_n_0 ),\n .O(\\ctl_lane_cnt[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000054555555)) \n \\ctl_lane_cnt[3]_i_2 \n (.I0(delay_dec_done_reg_1),\n .I1(\\ctl_lane_cnt_reg_n_0_[3] ),\n .I2(ctl_lane_cnt[2]),\n .I3(ctl_lane_cnt[1]),\n .I4(ctl_lane_cnt[0]),\n .I5(delay_dec_done_reg_0),\n .O(delaydec_cnt_r10_in));\n LUT4 #(\n .INIT(16'hFFBF)) \n \\ctl_lane_cnt[3]_i_3 \n (.I0(ctl_lane_cnt1),\n .I1(pi_fine_dly_dec_done),\n .I2(dqs_po_dec_done),\n .I3(rstdiv0_sync_r1_reg_rep__25),\n .O(\\ctl_lane_cnt[3]_i_3_n_0 ));\n FDRE \\ctl_lane_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ctl_lane_cnt[0]_i_1_n_0 ),\n .Q(ctl_lane_cnt[0]),\n .R(1'b0));\n FDRE \\ctl_lane_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ctl_lane_cnt[1]_i_1_n_0 ),\n .Q(ctl_lane_cnt[1]),\n .R(1'b0));\n FDRE \\ctl_lane_cnt_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ctl_lane_cnt[2]_i_1_n_0 ),\n .Q(ctl_lane_cnt[2]),\n .R(1'b0));\n FDRE \\ctl_lane_cnt_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ctl_lane_cnt[3]_i_1_n_0 ),\n .Q(\\ctl_lane_cnt_reg_n_0_[3] ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hDDFFEEFC)) \n \\delay_cnt_r[0]_i_1 \n (.I0(po_cnt_inc),\n .I1(delay_dec_done_reg_0),\n .I2(\\delay_cnt_r[0]_i_2_n_0 ),\n .I3(delay_dec_done_reg_1),\n .I4(\\delay_cnt_r_reg_n_0_[0] ),\n .O(\\delay_cnt_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair305\" *) \n LUT4 #(\n .INIT(16'hEFFF)) \n \\delay_cnt_r[0]_i_2 \n (.I0(\\ctl_lane_cnt_reg_n_0_[3] ),\n .I1(ctl_lane_cnt[2]),\n .I2(ctl_lane_cnt[1]),\n .I3(ctl_lane_cnt[0]),\n .O(\\delay_cnt_r[0]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair310\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\delay_cnt_r[1]_i_1 \n (.I0(\\delay_cnt_r_reg_n_0_[0] ),\n .I1(\\delay_cnt_r_reg_n_0_[1] ),\n .O(\\delay_cnt_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair310\" *) \n LUT3 #(\n .INIT(8'hE1)) \n \\delay_cnt_r[2]_i_1 \n (.I0(\\delay_cnt_r_reg_n_0_[1] ),\n .I1(\\delay_cnt_r_reg_n_0_[0] ),\n .I2(\\delay_cnt_r_reg_n_0_[2] ),\n .O(\\delay_cnt_r[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair306\" *) \n LUT4 #(\n .INIT(16'hFE01)) \n \\delay_cnt_r[3]_i_1 \n (.I0(\\delay_cnt_r_reg_n_0_[2] ),\n .I1(\\delay_cnt_r_reg_n_0_[0] ),\n .I2(\\delay_cnt_r_reg_n_0_[1] ),\n .I3(\\delay_cnt_r_reg_n_0_[3] ),\n .O(\\delay_cnt_r[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair306\" *) \n LUT5 #(\n .INIT(32'hFFFE0001)) \n \\delay_cnt_r[4]_i_1 \n (.I0(\\delay_cnt_r_reg_n_0_[3] ),\n .I1(\\delay_cnt_r_reg_n_0_[1] ),\n .I2(\\delay_cnt_r_reg_n_0_[0] ),\n .I3(\\delay_cnt_r_reg_n_0_[2] ),\n .I4(\\delay_cnt_r_reg_n_0_[4] ),\n .O(\\delay_cnt_r[4]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hFE)) \n \\delay_cnt_r[5]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__24),\n .I1(delay_dec_done_reg_0),\n .I2(\\delay_cnt_r[5]_i_5_n_0 ),\n .O(\\delay_cnt_r[5]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\delay_cnt_r[5]_i_2 \n (.I0(delay_dec_done_reg_1),\n .I1(po_cnt_inc),\n .O(delay_cnt_r0));\n LUT6 #(\n .INIT(64'hFFFFFFFE00000001)) \n \\delay_cnt_r[5]_i_3 \n (.I0(\\delay_cnt_r_reg_n_0_[4] ),\n .I1(\\delay_cnt_r_reg_n_0_[2] ),\n .I2(\\delay_cnt_r_reg_n_0_[0] ),\n .I3(\\delay_cnt_r_reg_n_0_[1] ),\n .I4(\\delay_cnt_r_reg_n_0_[3] ),\n .I5(\\delay_cnt_r_reg_n_0_[5] ),\n .O(\\delay_cnt_r[5]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\delay_cnt_r[5]_i_4 \n (.I0(delaydec_cnt_r_reg__0[5]),\n .I1(delaydec_cnt_r_reg__0[3]),\n .I2(delaydec_cnt_r_reg__0[1]),\n .I3(delaydec_cnt_r_reg__0[2]),\n .I4(delaydec_cnt_r_reg__0[4]),\n .I5(delaydec_cnt_r_reg__0[0]),\n .O(delay_dec_done_reg_0));\n (* SOFT_HLUTNM = \"soft_lutpair305\" *) \n LUT5 #(\n .INIT(32'h0000FFF7)) \n \\delay_cnt_r[5]_i_5 \n (.I0(ctl_lane_cnt[0]),\n .I1(ctl_lane_cnt[1]),\n .I2(ctl_lane_cnt[2]),\n .I3(\\ctl_lane_cnt_reg_n_0_[3] ),\n .I4(delay_dec_done_reg_1),\n .O(\\delay_cnt_r[5]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\delay_cnt_r[5]_i_6 \n (.I0(\\delay_cnt_r_reg_n_0_[4] ),\n .I1(\\delay_cnt_r_reg_n_0_[2] ),\n .I2(\\delay_cnt_r_reg_n_0_[0] ),\n .I3(\\delay_cnt_r_reg_n_0_[1] ),\n .I4(\\delay_cnt_r_reg_n_0_[3] ),\n .I5(\\delay_cnt_r_reg_n_0_[5] ),\n .O(delay_dec_done_reg_1));\n FDRE \\delay_cnt_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\delay_cnt_r[0]_i_1_n_0 ),\n .Q(\\delay_cnt_r_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE \\delay_cnt_r_reg[1] \n (.C(CLK),\n .CE(delay_cnt_r0),\n .D(\\delay_cnt_r[1]_i_1_n_0 ),\n .Q(\\delay_cnt_r_reg_n_0_[1] ),\n .R(\\delay_cnt_r[5]_i_1_n_0 ));\n FDRE \\delay_cnt_r_reg[2] \n (.C(CLK),\n .CE(delay_cnt_r0),\n .D(\\delay_cnt_r[2]_i_1_n_0 ),\n .Q(\\delay_cnt_r_reg_n_0_[2] ),\n .R(\\delay_cnt_r[5]_i_1_n_0 ));\n FDRE \\delay_cnt_r_reg[3] \n (.C(CLK),\n .CE(delay_cnt_r0),\n .D(\\delay_cnt_r[3]_i_1_n_0 ),\n .Q(\\delay_cnt_r_reg_n_0_[3] ),\n .R(\\delay_cnt_r[5]_i_1_n_0 ));\n FDRE \\delay_cnt_r_reg[4] \n (.C(CLK),\n .CE(delay_cnt_r0),\n .D(\\delay_cnt_r[4]_i_1_n_0 ),\n .Q(\\delay_cnt_r_reg_n_0_[4] ),\n .R(\\delay_cnt_r[5]_i_1_n_0 ));\n FDRE \\delay_cnt_r_reg[5] \n (.C(CLK),\n .CE(delay_cnt_r0),\n .D(\\delay_cnt_r[5]_i_3_n_0 ),\n .Q(\\delay_cnt_r_reg_n_0_[5] ),\n .R(\\delay_cnt_r[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00000000AAAB0000)) \n delay_dec_done_i_1\n (.I0(delay_dec_done),\n .I1(\\delay_cnt_r[0]_i_2_n_0 ),\n .I2(delay_dec_done_reg_0),\n .I3(delay_dec_done_reg_1),\n .I4(cmd_delay_start0),\n .I5(rstdiv0_sync_r1_reg_rep__25),\n .O(delay_dec_done_i_1_n_0));\n FDRE delay_dec_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(delay_dec_done_i_1_n_0),\n .Q(delay_dec_done),\n .R(1'b0));\n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/delay_done_r3_reg_srl3 \" *) \n SRL16E delay_done_r3_reg_srl3\n (.A0(1'b0),\n .A1(1'b1),\n .A2(1'b0),\n .A3(1'b0),\n .CE(1'b1),\n .CLK(CLK),\n .D(delay_dec_done),\n .Q(delay_done_r3_reg_srl3_n_0));\n (* syn_maxfan = \"10\" *) \n FDRE delay_done_r4_reg\n (.C(CLK),\n .CE(1'b1),\n .D(delay_done_r3_reg_srl3_n_0),\n .Q(ck_addr_cmd_delay_done),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair312\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\delaydec_cnt_r[0]_i_1 \n (.I0(delaydec_cnt_r_reg__0[0]),\n .O(\\delaydec_cnt_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair308\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\delaydec_cnt_r[1]_i_1 \n (.I0(delaydec_cnt_r_reg__0[0]),\n .I1(delaydec_cnt_r_reg__0[1]),\n .O(\\delaydec_cnt_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair312\" *) \n LUT3 #(\n .INIT(8'hE1)) \n \\delaydec_cnt_r[2]_i_1 \n (.I0(delaydec_cnt_r_reg__0[0]),\n .I1(delaydec_cnt_r_reg__0[1]),\n .I2(delaydec_cnt_r_reg__0[2]),\n .O(\\delaydec_cnt_r[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair307\" *) \n LUT4 #(\n .INIT(16'hFE01)) \n \\delaydec_cnt_r[3]_i_1 \n (.I0(delaydec_cnt_r_reg__0[0]),\n .I1(delaydec_cnt_r_reg__0[1]),\n .I2(delaydec_cnt_r_reg__0[2]),\n .I3(delaydec_cnt_r_reg__0[3]),\n .O(\\delaydec_cnt_r[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair307\" *) \n LUT5 #(\n .INIT(32'hFFFE0001)) \n \\delaydec_cnt_r[4]_i_1 \n (.I0(delaydec_cnt_r_reg__0[0]),\n .I1(delaydec_cnt_r_reg__0[2]),\n .I2(delaydec_cnt_r_reg__0[1]),\n .I3(delaydec_cnt_r_reg__0[3]),\n .I4(delaydec_cnt_r_reg__0[4]),\n .O(\\delaydec_cnt_r[4]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hFFBF)) \n \\delaydec_cnt_r[5]_i_1 \n (.I0(delaydec_cnt_r10_in),\n .I1(pi_fine_dly_dec_done),\n .I2(dqs_po_dec_done),\n .I3(rstdiv0_sync_r1_reg_rep__25),\n .O(\\delaydec_cnt_r[5]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\delaydec_cnt_r[5]_i_2 \n (.I0(delay_dec_done_reg_0),\n .I1(po_cnt_dec),\n .O(delaydec_cnt_r0));\n LUT6 #(\n .INIT(64'hFFFFFFFE00000001)) \n \\delaydec_cnt_r[5]_i_3 \n (.I0(delaydec_cnt_r_reg__0[0]),\n .I1(delaydec_cnt_r_reg__0[3]),\n .I2(delaydec_cnt_r_reg__0[1]),\n .I3(delaydec_cnt_r_reg__0[2]),\n .I4(delaydec_cnt_r_reg__0[4]),\n .I5(delaydec_cnt_r_reg__0[5]),\n .O(\\delaydec_cnt_r[5]_i_3_n_0 ));\n FDSE \\delaydec_cnt_r_reg[0] \n (.C(CLK),\n .CE(delaydec_cnt_r0),\n .D(\\delaydec_cnt_r[0]_i_1_n_0 ),\n .Q(delaydec_cnt_r_reg__0[0]),\n .S(\\delaydec_cnt_r[5]_i_1_n_0 ));\n FDRE \\delaydec_cnt_r_reg[1] \n (.C(CLK),\n .CE(delaydec_cnt_r0),\n .D(\\delaydec_cnt_r[1]_i_1_n_0 ),\n .Q(delaydec_cnt_r_reg__0[1]),\n .R(\\delaydec_cnt_r[5]_i_1_n_0 ));\n FDSE \\delaydec_cnt_r_reg[2] \n (.C(CLK),\n .CE(delaydec_cnt_r0),\n .D(\\delaydec_cnt_r[2]_i_1_n_0 ),\n .Q(delaydec_cnt_r_reg__0[2]),\n .S(\\delaydec_cnt_r[5]_i_1_n_0 ));\n FDSE \\delaydec_cnt_r_reg[3] \n (.C(CLK),\n .CE(delaydec_cnt_r0),\n .D(\\delaydec_cnt_r[3]_i_1_n_0 ),\n .Q(delaydec_cnt_r_reg__0[3]),\n .S(\\delaydec_cnt_r[5]_i_1_n_0 ));\n FDSE \\delaydec_cnt_r_reg[4] \n (.C(CLK),\n .CE(delaydec_cnt_r0),\n .D(\\delaydec_cnt_r[4]_i_1_n_0 ),\n .Q(delaydec_cnt_r_reg__0[4]),\n .S(\\delaydec_cnt_r[5]_i_1_n_0 ));\n FDRE \\delaydec_cnt_r_reg[5] \n (.C(CLK),\n .CE(delaydec_cnt_r0),\n .D(\\delaydec_cnt_r[5]_i_3_n_0 ),\n .Q(delaydec_cnt_r_reg__0[5]),\n .R(\\delaydec_cnt_r[5]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h80)) \n \\init_state_r[0]_i_39 \n (.I0(ck_addr_cmd_delay_done),\n .I1(cnt_pwron_cke_done_r),\n .I2(\\mcGo_r_reg[15] ),\n .O(\\init_state_r_reg[0] ));\n LUT6 #(\n .INIT(64'h0000000008080800)) \n phaser_out_i_1\n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(calib_in_common),\n .I3(p_3_in),\n .I4(dqs_wl_po_stg2_c_incdec),\n .I5(\\calib_zero_inputs_reg[1] [1]),\n .O(D_po_coarse_enable110_out));\n LUT6 #(\n .INIT(64'h0000000001010100)) \n phaser_out_i_1__0\n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(calib_in_common),\n .I3(p_3_in),\n .I4(dqs_wl_po_stg2_c_incdec),\n .I5(\\calib_zero_inputs_reg[1] [1]),\n .O(\\po_counter_read_val_reg[8] ));\n LUT6 #(\n .INIT(64'h0000000004040400)) \n phaser_out_i_1__1\n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(calib_in_common),\n .I3(p_3_in),\n .I4(dqs_wl_po_stg2_c_incdec),\n .I5(\\calib_zero_inputs_reg[1] [1]),\n .O(\\po_counter_read_val_reg[8]_0 ));\n LUT6 #(\n .INIT(64'h0000000004040400)) \n phaser_out_i_1__2\n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(calib_in_common),\n .I3(p_3_in),\n .I4(dqs_wl_po_stg2_c_incdec),\n .I5(\\calib_zero_inputs_reg[1] [1]),\n .O(\\po_counter_read_val_reg[8]_1 ));\n LUT6 #(\n .INIT(64'h00000000EAEAEA00)) \n phaser_out_i_1__3\n (.I0(calib_in_common),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(p_3_in),\n .I4(dqs_wl_po_stg2_c_incdec),\n .I5(\\calib_zero_inputs_reg[1] [0]),\n .O(\\po_counter_read_val_reg[8]_2 ));\n LUT6 #(\n .INIT(64'h00000000BABABA00)) \n phaser_out_i_1__4\n (.I0(calib_in_common),\n .I1(Q[0]),\n .I2(Q[1]),\n .I3(p_3_in),\n .I4(dqs_wl_po_stg2_c_incdec),\n .I5(\\calib_zero_inputs_reg[1] [0]),\n .O(\\po_counter_read_val_reg[8]_3 ));\n LUT6 #(\n .INIT(64'h00000000BABABA00)) \n phaser_out_i_1__5\n (.I0(calib_in_common),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(p_3_in),\n .I4(dqs_wl_po_stg2_c_incdec),\n .I5(\\calib_zero_inputs_reg[1] [0]),\n .O(\\po_counter_read_val_reg[8]_4 ));\n LUT6 #(\n .INIT(64'h00000000ABABAB00)) \n phaser_out_i_1__6\n (.I0(calib_in_common),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(p_3_in),\n .I4(dqs_wl_po_stg2_c_incdec),\n .I5(\\calib_zero_inputs_reg[1] [0]),\n .O(\\po_counter_read_val_reg[8]_5 ));\n FDRE po_cnt_dec_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\wait_cnt_r_reg[0]_2 ),\n .Q(po_cnt_dec),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair309\" *) \n LUT3 #(\n .INIT(8'hFE)) \n po_cnt_inc_i_2\n (.I0(wait_cnt_r_reg__0__0[2]),\n .I1(wait_cnt_r_reg__0__0[1]),\n .I2(wait_cnt_r_reg__0__0[3]),\n .O(po_cnt_inc_reg_0));\n FDRE po_cnt_inc_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\wait_cnt_r_reg[0]_1 ),\n .Q(po_cnt_inc),\n .R(1'b0));\n FDRE po_en_stg2_f_reg\n (.C(CLK),\n .CE(1'b1),\n .D(po_cnt_dec),\n .Q(po_en_stg2_f),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE po_stg2_c_incdec_reg\n (.C(CLK),\n .CE(1'b1),\n .D(po_cnt_inc),\n .Q(p_3_in),\n .R(rstdiv0_sync_r1_reg_rep__9));\n LUT1 #(\n .INIT(2'h1)) \n \\wait_cnt_r[0]_i_1__0 \n (.I0(\\wait_cnt_r_reg[0]_0 ),\n .O(wait_cnt_r0__0));\n (* SOFT_HLUTNM = \"soft_lutpair311\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\wait_cnt_r[1]_i_1__0 \n (.I0(\\wait_cnt_r_reg[0]_0 ),\n .I1(wait_cnt_r_reg__0__0[1]),\n .O(\\wait_cnt_r[1]_i_1__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair311\" *) \n LUT3 #(\n .INIT(8'hE1)) \n \\wait_cnt_r[2]_i_1__1 \n (.I0(wait_cnt_r_reg__0__0[1]),\n .I1(\\wait_cnt_r_reg[0]_0 ),\n .I2(wait_cnt_r_reg__0__0[2]),\n .O(\\wait_cnt_r[2]_i_1__1_n_0 ));\n LUT3 #(\n .INIT(8'hFE)) \n \\wait_cnt_r[3]_i_1__0 \n (.I0(rstdiv0_sync_r1_reg_rep__24),\n .I1(po_cnt_dec),\n .I2(po_cnt_inc),\n .O(\\wait_cnt_r[3]_i_1__0_n_0 ));\n LUT6 #(\n .INIT(64'hC0C0C0C0C0C0C080)) \n \\wait_cnt_r[3]_i_2__0 \n (.I0(\\wait_cnt_r_reg[0]_0 ),\n .I1(pi_fine_dly_dec_done),\n .I2(dqs_po_dec_done),\n .I3(wait_cnt_r_reg__0__0[2]),\n .I4(wait_cnt_r_reg__0__0[1]),\n .I5(wait_cnt_r_reg__0__0[3]),\n .O(wait_cnt_r0));\n (* SOFT_HLUTNM = \"soft_lutpair309\" *) \n LUT4 #(\n .INIT(16'hFE01)) \n \\wait_cnt_r[3]_i_3__0 \n (.I0(\\wait_cnt_r_reg[0]_0 ),\n .I1(wait_cnt_r_reg__0__0[1]),\n .I2(wait_cnt_r_reg__0__0[2]),\n .I3(wait_cnt_r_reg__0__0[3]),\n .O(\\wait_cnt_r[3]_i_3__0_n_0 ));\n FDRE \\wait_cnt_r_reg[0] \n (.C(CLK),\n .CE(wait_cnt_r0),\n .D(wait_cnt_r0__0),\n .Q(\\wait_cnt_r_reg[0]_0 ),\n .R(\\wait_cnt_r[3]_i_1__0_n_0 ));\n FDRE \\wait_cnt_r_reg[1] \n (.C(CLK),\n .CE(wait_cnt_r0),\n .D(\\wait_cnt_r[1]_i_1__0_n_0 ),\n .Q(wait_cnt_r_reg__0__0[1]),\n .R(\\wait_cnt_r[3]_i_1__0_n_0 ));\n FDRE \\wait_cnt_r_reg[2] \n (.C(CLK),\n .CE(wait_cnt_r0),\n .D(\\wait_cnt_r[2]_i_1__1_n_0 ),\n .Q(wait_cnt_r_reg__0__0[2]),\n .R(\\wait_cnt_r[3]_i_1__0_n_0 ));\n FDSE \\wait_cnt_r_reg[3] \n (.C(CLK),\n .CE(wait_cnt_r0),\n .D(\\wait_cnt_r[3]_i_3__0_n_0 ),\n .Q(wait_cnt_r_reg__0__0[3]),\n .S(\\wait_cnt_r[3]_i_1__0_n_0 ));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_ddr_phy_dqs_found_cal\n (init_dqsfound_done_r2,\n init_dqsfound_done_r5,\n out,\n pi_dqs_found_any_bank,\n pi_dqs_found_rank_done,\n rd_data_offset_cal_done,\n rst_dqs_find_r1_reg_0,\n pi_dqs_found_done_r1_reg,\n \\pi_rst_stg1_cal_r_reg[0]_0 ,\n fine_adjust_done_r_reg_0,\n init_dec_done_reg_0,\n final_dec_done_reg_0,\n dqs_found_prech_req,\n ck_po_stg2_f_indec,\n ck_po_stg2_f_en,\n \\pi_dqs_found_all_bank_r_reg[1]_0 ,\n D_po_fine_enable107_out,\n D_po_fine_inc113_out,\n \\po_counter_read_val_reg[8] ,\n \\po_counter_read_val_reg[8]_0 ,\n \\po_counter_read_val_reg[8]_1 ,\n \\po_counter_read_val_reg[8]_2 ,\n \\po_counter_read_val_reg[8]_3 ,\n \\po_counter_read_val_reg[8]_4 ,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n \\po_counter_read_val_reg[8]_5 ,\n \\po_counter_read_val_reg[8]_6 ,\n ififo_rst_reg,\n \\po_counter_read_val_reg[8]_7 ,\n \\po_counter_read_val_reg[8]_8 ,\n ififo_rst_reg_0,\n \\po_counter_read_val_reg[8]_9 ,\n \\po_counter_read_val_reg[8]_10 ,\n ififo_rst_reg_1,\n \\po_counter_read_val_reg[8]_11 ,\n \\po_counter_read_val_reg[8]_12 ,\n ififo_rst_reg_2,\n fine_adj_state_r144_out,\n \\FSM_sequential_fine_adj_state_r_reg[2]_0 ,\n \\dec_cnt_reg[0]_0 ,\n \\FSM_sequential_fine_adj_state_r_reg[0]_0 ,\n \\rd_byte_data_offset_reg[0][9]_0 ,\n \\cmd_pipe_plus.mc_data_offset_reg[3] ,\n \\cmd_pipe_plus.mc_data_offset_reg[5] ,\n \\cmd_pipe_plus.mc_data_offset_reg[4] ,\n \\cmd_pipe_plus.mc_data_offset_reg[2] ,\n \\cmd_pipe_plus.mc_data_offset_reg[1] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[3] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[5] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[4] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[2] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[1] ,\n \\cmd_pipe_plus.mc_data_offset_reg[0] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[0] ,\n \\rd_byte_data_offset_reg[0]_3 ,\n p_1_in27_in,\n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 ,\n p_1_in50_in,\n \\pi_rst_stg1_cal_r_reg[0]_1 ,\n fine_adj_state_r16_out,\n dqs_found_prech_req_reg_0,\n final_dec_done_reg_1,\n \\FSM_sequential_fine_adj_state_r_reg[0]_1 ,\n \\rank_final_loop[0].final_do_max_reg[0][3]_0 ,\n \\rank_final_loop[0].final_do_max_reg[0][3]_1 ,\n \\init_state_r_reg[1] ,\n \\init_state_r_reg[2] ,\n \\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ,\n \\init_state_r_reg[1]_0 ,\n \\init_state_r_reg[1]_1 ,\n \\calib_data_offset_0_reg[5] ,\n \\calib_data_offset_0_reg[4] ,\n \\calib_data_offset_0_reg[1] ,\n \\calib_data_offset_0_reg[0] ,\n \\calib_data_offset_1_reg[5] ,\n \\calib_data_offset_1_reg[4] ,\n \\calib_data_offset_1_reg[1] ,\n \\calib_data_offset_1_reg[0] ,\n \\gen_byte_sel_div1.ctl_lane_sel_reg[0] ,\n ctl_lane_sel,\n \\gen_byte_sel_div1.ctl_lane_sel_reg[1] ,\n \\gen_byte_sel_div1.ctl_lane_sel_reg[2] ,\n \\calib_zero_inputs_reg[1] ,\n D,\n \\calib_zero_inputs_reg[0] ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ,\n rank_done_r_reg_0,\n rst_dqs_find_reg_0,\n dqs_found_prech_req_reg_1,\n rst_dqs_find_reg_1,\n init_dec_done_reg_1,\n rst_dqs_find,\n CLK,\n in0,\n pi_dqs_found_start_reg,\n rstdiv0_sync_r1_reg_rep__12,\n rstdiv0_sync_r1_reg_rep__2,\n \\pi_dqs_found_lanes_r3_reg[3]_0 ,\n \\pi_dqs_found_all_bank_r_reg[1]_1 ,\n init_dqsfound_done_r_reg_0,\n rstdiv0_sync_r1_reg_rep__13,\n \\FSM_sequential_fine_adj_state_r_reg[0]_2 ,\n \\FSM_sequential_fine_adj_state_r_reg[1]_0 ,\n \\FSM_sequential_fine_adj_state_r_reg[0]_3 ,\n init_dec_done_reg_2,\n \\FSM_sequential_fine_adj_state_r_reg[1]_1 ,\n \\FSM_sequential_fine_adj_state_r_reg[2]_1 ,\n \\FSM_sequential_fine_adj_state_r_reg[1]_2 ,\n \\FSM_sequential_fine_adj_state_r_reg[1]_3 ,\n pi_dqs_found_start_reg_0,\n Q,\n calib_in_common,\n po_enstg2_f,\n \\calib_zero_inputs_reg[1]_0 ,\n po_stg2_fincdec,\n pi_calib_done,\n oclkdelay_calib_done_r_reg,\n pi_f_inc_reg,\n \\gen_byte_sel_div1.calib_in_common_reg_0 ,\n dqs_po_stg2_f_incdec,\n po_stg23_incdec,\n dqs_po_en_stg2_f,\n po_en_stg2_f,\n po_en_stg23,\n \\gen_byte_sel_div1.calib_in_common_reg_1 ,\n \\gen_byte_sel_div1.calib_in_common_reg_2 ,\n \\gen_byte_sel_div1.calib_in_common_reg_3 ,\n wrcal_done_reg,\n rdlvl_stg1_done_int_reg,\n prbs_rdlvl_done_reg_rep,\n sent_col,\n rstdiv0_sync_r1_reg_rep__24,\n detect_pi_found_dqs,\n \\num_refresh_reg[1] ,\n oclkdelay_calib_done_r_reg_0,\n mpr_rdlvl_done_r_reg,\n cnt_cmd_done_r,\n prbs_last_byte_done_r,\n wrlvl_byte_redo,\n wrlvl_done_r1,\n oclkdelay_center_calib_done_r_reg,\n wrlvl_final_mux,\n pi_dqs_found_done_r1,\n ck_addr_cmd_delay_done,\n ctl_lane_cnt,\n \\gen_byte_sel_div1.ctl_lane_sel_reg[0]_0 ,\n \\gen_byte_sel_div1.ctl_lane_sel_reg[1]_0 ,\n \\gen_byte_sel_div1.ctl_lane_sel_reg[2]_0 ,\n pi_fine_dly_dec_done,\n dqs_po_dec_done,\n tempmon_sel_pi_incdec,\n byte_sel_cnt,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[1] ,\n init_calib_complete_reg,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ,\n cmd_delay_start0,\n rstdiv0_sync_r1_reg_rep__25,\n fine_adjust_reg_0,\n rstdiv0_sync_r1_reg_rep__19,\n prech_done);\n output init_dqsfound_done_r2;\n output init_dqsfound_done_r5;\n output [3:0]out;\n output [0:0]pi_dqs_found_any_bank;\n output pi_dqs_found_rank_done;\n output rd_data_offset_cal_done;\n output rst_dqs_find_r1_reg_0;\n output pi_dqs_found_done_r1_reg;\n output \\pi_rst_stg1_cal_r_reg[0]_0 ;\n output fine_adjust_done_r_reg_0;\n output init_dec_done_reg_0;\n output final_dec_done_reg_0;\n output dqs_found_prech_req;\n output ck_po_stg2_f_indec;\n output ck_po_stg2_f_en;\n output [0:0]\\pi_dqs_found_all_bank_r_reg[1]_0 ;\n output D_po_fine_enable107_out;\n output D_po_fine_inc113_out;\n output \\po_counter_read_val_reg[8] ;\n output \\po_counter_read_val_reg[8]_0 ;\n output \\po_counter_read_val_reg[8]_1 ;\n output \\po_counter_read_val_reg[8]_2 ;\n output \\po_counter_read_val_reg[8]_3 ;\n output \\po_counter_read_val_reg[8]_4 ;\n output \\gen_byte_sel_div1.calib_in_common_reg ;\n output \\po_counter_read_val_reg[8]_5 ;\n output \\po_counter_read_val_reg[8]_6 ;\n output ififo_rst_reg;\n output \\po_counter_read_val_reg[8]_7 ;\n output \\po_counter_read_val_reg[8]_8 ;\n output ififo_rst_reg_0;\n output \\po_counter_read_val_reg[8]_9 ;\n output \\po_counter_read_val_reg[8]_10 ;\n output ififo_rst_reg_1;\n output \\po_counter_read_val_reg[8]_11 ;\n output \\po_counter_read_val_reg[8]_12 ;\n output ififo_rst_reg_2;\n output fine_adj_state_r144_out;\n output \\FSM_sequential_fine_adj_state_r_reg[2]_0 ;\n output \\dec_cnt_reg[0]_0 ;\n output [3:0]\\FSM_sequential_fine_adj_state_r_reg[0]_0 ;\n output [1:0]\\rd_byte_data_offset_reg[0][9]_0 ;\n output \\cmd_pipe_plus.mc_data_offset_reg[3] ;\n output [5:0]\\cmd_pipe_plus.mc_data_offset_reg[5] ;\n output \\cmd_pipe_plus.mc_data_offset_reg[4] ;\n output \\cmd_pipe_plus.mc_data_offset_reg[2] ;\n output \\cmd_pipe_plus.mc_data_offset_reg[1] ;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[3] ;\n output [5:0]\\cmd_pipe_plus.mc_data_offset_1_reg[5] ;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[4] ;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[2] ;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[1] ;\n output \\cmd_pipe_plus.mc_data_offset_reg[0] ;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[0] ;\n output \\rd_byte_data_offset_reg[0]_3 ;\n output p_1_in27_in;\n output [1:0]\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 ;\n output p_1_in50_in;\n output \\pi_rst_stg1_cal_r_reg[0]_1 ;\n output fine_adj_state_r16_out;\n output dqs_found_prech_req_reg_0;\n output final_dec_done_reg_1;\n output \\FSM_sequential_fine_adj_state_r_reg[0]_1 ;\n output [1:0]\\rank_final_loop[0].final_do_max_reg[0][3]_0 ;\n output [1:0]\\rank_final_loop[0].final_do_max_reg[0][3]_1 ;\n output \\init_state_r_reg[1] ;\n output \\init_state_r_reg[2] ;\n output \\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ;\n output \\init_state_r_reg[1]_0 ;\n output \\init_state_r_reg[1]_1 ;\n output \\calib_data_offset_0_reg[5] ;\n output \\calib_data_offset_0_reg[4] ;\n output \\calib_data_offset_0_reg[1] ;\n output \\calib_data_offset_0_reg[0] ;\n output \\calib_data_offset_1_reg[5] ;\n output \\calib_data_offset_1_reg[4] ;\n output \\calib_data_offset_1_reg[1] ;\n output \\calib_data_offset_1_reg[0] ;\n output \\gen_byte_sel_div1.ctl_lane_sel_reg[0] ;\n output ctl_lane_sel;\n output \\gen_byte_sel_div1.ctl_lane_sel_reg[1] ;\n output \\gen_byte_sel_div1.ctl_lane_sel_reg[2] ;\n output \\calib_zero_inputs_reg[1] ;\n output [1:0]D;\n output [0:0]\\calib_zero_inputs_reg[0] ;\n output \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ;\n output [1:0]rank_done_r_reg_0;\n output rst_dqs_find_reg_0;\n output dqs_found_prech_req_reg_1;\n output rst_dqs_find_reg_1;\n output init_dec_done_reg_1;\n output rst_dqs_find;\n input CLK;\n input [3:0]in0;\n input pi_dqs_found_start_reg;\n input rstdiv0_sync_r1_reg_rep__12;\n input rstdiv0_sync_r1_reg_rep__2;\n input \\pi_dqs_found_lanes_r3_reg[3]_0 ;\n input \\pi_dqs_found_all_bank_r_reg[1]_1 ;\n input init_dqsfound_done_r_reg_0;\n input rstdiv0_sync_r1_reg_rep__13;\n input \\FSM_sequential_fine_adj_state_r_reg[0]_2 ;\n input \\FSM_sequential_fine_adj_state_r_reg[1]_0 ;\n input \\FSM_sequential_fine_adj_state_r_reg[0]_3 ;\n input init_dec_done_reg_2;\n input \\FSM_sequential_fine_adj_state_r_reg[1]_1 ;\n input \\FSM_sequential_fine_adj_state_r_reg[2]_1 ;\n input \\FSM_sequential_fine_adj_state_r_reg[1]_2 ;\n input \\FSM_sequential_fine_adj_state_r_reg[1]_3 ;\n input pi_dqs_found_start_reg_0;\n input [1:0]Q;\n input calib_in_common;\n input [0:0]po_enstg2_f;\n input [1:0]\\calib_zero_inputs_reg[1]_0 ;\n input [0:0]po_stg2_fincdec;\n input pi_calib_done;\n input oclkdelay_calib_done_r_reg;\n input pi_f_inc_reg;\n input \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n input dqs_po_stg2_f_incdec;\n input po_stg23_incdec;\n input dqs_po_en_stg2_f;\n input po_en_stg2_f;\n input po_en_stg23;\n input \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n input \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n input \\gen_byte_sel_div1.calib_in_common_reg_3 ;\n input wrcal_done_reg;\n input rdlvl_stg1_done_int_reg;\n input prbs_rdlvl_done_reg_rep;\n input sent_col;\n input rstdiv0_sync_r1_reg_rep__24;\n input detect_pi_found_dqs;\n input \\num_refresh_reg[1] ;\n input oclkdelay_calib_done_r_reg_0;\n input mpr_rdlvl_done_r_reg;\n input cnt_cmd_done_r;\n input prbs_last_byte_done_r;\n input wrlvl_byte_redo;\n input wrlvl_done_r1;\n input oclkdelay_center_calib_done_r_reg;\n input wrlvl_final_mux;\n input pi_dqs_found_done_r1;\n input ck_addr_cmd_delay_done;\n input [2:0]ctl_lane_cnt;\n input \\gen_byte_sel_div1.ctl_lane_sel_reg[0]_0 ;\n input \\gen_byte_sel_div1.ctl_lane_sel_reg[1]_0 ;\n input \\gen_byte_sel_div1.ctl_lane_sel_reg[2]_0 ;\n input pi_fine_dly_dec_done;\n input dqs_po_dec_done;\n input tempmon_sel_pi_incdec;\n input [0:0]byte_sel_cnt;\n input \\gen_byte_sel_div1.byte_sel_cnt_reg[1] ;\n input init_calib_complete_reg;\n input \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ;\n input cmd_delay_start0;\n input rstdiv0_sync_r1_reg_rep__25;\n input fine_adjust_reg_0;\n input [0:0]rstdiv0_sync_r1_reg_rep__19;\n input prech_done;\n\n wire CLK;\n wire [1:0]D;\n wire D_po_fine_enable107_out;\n wire D_po_fine_inc113_out;\n wire \\FSM_sequential_fine_adj_state_r[0]_i_1_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r[0]_i_4_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r[0]_i_5_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r[1]_i_2_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r[1]_i_3_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r[1]_i_5_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r[2]_i_1_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r[2]_i_2_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r[2]_i_4_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r[3]_i_1_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r[3]_i_2_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r[3]_i_3_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r[3]_i_4_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r[3]_i_5_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r[3]_i_6_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r[3]_i_8_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r[3]_i_9_n_0 ;\n (* RTL_KEEP = \"yes\" *) wire [3:0]\\FSM_sequential_fine_adj_state_r_reg[0]_0 ;\n wire \\FSM_sequential_fine_adj_state_r_reg[0]_1 ;\n wire \\FSM_sequential_fine_adj_state_r_reg[0]_2 ;\n wire \\FSM_sequential_fine_adj_state_r_reg[0]_3 ;\n wire \\FSM_sequential_fine_adj_state_r_reg[0]_i_3_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r_reg[1]_0 ;\n wire \\FSM_sequential_fine_adj_state_r_reg[1]_1 ;\n wire \\FSM_sequential_fine_adj_state_r_reg[1]_2 ;\n wire \\FSM_sequential_fine_adj_state_r_reg[1]_3 ;\n wire \\FSM_sequential_fine_adj_state_r_reg[1]_i_1_n_0 ;\n wire \\FSM_sequential_fine_adj_state_r_reg[2]_0 ;\n wire \\FSM_sequential_fine_adj_state_r_reg[2]_1 ;\n wire [1:0]Q;\n wire [0:0]byte_sel_cnt;\n wire \\calib_data_offset_0_reg[0] ;\n wire \\calib_data_offset_0_reg[1] ;\n wire \\calib_data_offset_0_reg[4] ;\n wire \\calib_data_offset_0_reg[5] ;\n wire \\calib_data_offset_1_reg[0] ;\n wire \\calib_data_offset_1_reg[1] ;\n wire \\calib_data_offset_1_reg[4] ;\n wire \\calib_data_offset_1_reg[5] ;\n wire calib_in_common;\n wire [0:0]\\calib_zero_inputs_reg[0] ;\n wire \\calib_zero_inputs_reg[1] ;\n wire [1:0]\\calib_zero_inputs_reg[1]_0 ;\n wire ck_addr_cmd_delay_done;\n wire ck_po_stg2_f_en;\n wire ck_po_stg2_f_indec;\n wire cmd_delay_start0;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[0] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[1] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[2] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[3] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[4] ;\n wire [5:0]\\cmd_pipe_plus.mc_data_offset_1_reg[5] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[0] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[1] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[2] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[3] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[4] ;\n wire [5:0]\\cmd_pipe_plus.mc_data_offset_reg[5] ;\n wire cnt_cmd_done_r;\n wire [2:0]ctl_lane_cnt;\n wire ctl_lane_cnt_0;\n wire [3:0]ctl_lane_cnt__0;\n wire \\ctl_lane_cnt_reg_n_0_[3] ;\n wire ctl_lane_sel;\n wire [5:0]dec_cnt;\n wire \\dec_cnt[0]_i_2_n_0 ;\n wire \\dec_cnt[0]_i_4_n_0 ;\n wire \\dec_cnt[0]_i_5_n_0 ;\n wire \\dec_cnt[0]_i_6_n_0 ;\n wire \\dec_cnt[0]_i_7_n_0 ;\n wire \\dec_cnt[1]_i_2_n_0 ;\n wire \\dec_cnt[1]_i_3_n_0 ;\n wire \\dec_cnt[1]_i_4_n_0 ;\n wire \\dec_cnt[2]_i_2_n_0 ;\n wire \\dec_cnt[2]_i_3_n_0 ;\n wire \\dec_cnt[2]_i_4_n_0 ;\n wire \\dec_cnt[3]_i_2_n_0 ;\n wire \\dec_cnt[3]_i_3_n_0 ;\n wire \\dec_cnt[3]_i_4_n_0 ;\n wire \\dec_cnt[4]_i_2_n_0 ;\n wire \\dec_cnt[4]_i_3_n_0 ;\n wire \\dec_cnt[4]_i_5_n_0 ;\n wire \\dec_cnt[4]_i_6_n_0 ;\n wire \\dec_cnt[4]_i_7_n_0 ;\n wire \\dec_cnt[5]_i_10_n_0 ;\n wire \\dec_cnt[5]_i_1_n_0 ;\n wire \\dec_cnt[5]_i_3_n_0 ;\n wire \\dec_cnt[5]_i_4_n_0 ;\n wire \\dec_cnt[5]_i_6_n_0 ;\n wire \\dec_cnt[5]_i_7_n_0 ;\n wire \\dec_cnt[5]_i_8_n_0 ;\n wire \\dec_cnt[5]_i_9_n_0 ;\n wire \\dec_cnt_reg[0]_0 ;\n wire \\dec_cnt_reg[0]_i_3_n_0 ;\n wire \\dec_cnt_reg[0]_i_3_n_1 ;\n wire \\dec_cnt_reg[0]_i_3_n_2 ;\n wire \\dec_cnt_reg[0]_i_3_n_3 ;\n wire \\dec_cnt_reg[0]_i_3_n_4 ;\n wire \\dec_cnt_reg[0]_i_3_n_5 ;\n wire \\dec_cnt_reg[0]_i_3_n_6 ;\n wire \\dec_cnt_reg[4]_i_4_n_3 ;\n wire \\dec_cnt_reg[4]_i_4_n_6 ;\n wire \\dec_cnt_reg[4]_i_4_n_7 ;\n wire \\dec_cnt_reg_n_0_[0] ;\n wire \\dec_cnt_reg_n_0_[1] ;\n wire \\dec_cnt_reg_n_0_[2] ;\n wire \\dec_cnt_reg_n_0_[3] ;\n wire \\dec_cnt_reg_n_0_[4] ;\n wire \\dec_cnt_reg_n_0_[5] ;\n wire detect_pi_found_dqs;\n wire detect_rd_cnt0;\n wire [3:0]detect_rd_cnt0__0;\n wire \\detect_rd_cnt[1]_i_1_n_0 ;\n wire \\detect_rd_cnt[3]_i_1_n_0 ;\n wire [3:0]detect_rd_cnt_reg__0;\n wire dqs_found_done_r0;\n wire dqs_found_done_r_i_3_n_0;\n wire dqs_found_prech_req;\n wire dqs_found_prech_req_i_5_n_0;\n wire dqs_found_prech_req_reg_0;\n wire dqs_found_prech_req_reg_1;\n wire dqs_found_start_r;\n wire dqs_po_dec_done;\n wire dqs_po_en_stg2_f;\n wire dqs_po_stg2_f_incdec;\n wire final_data_offset;\n wire final_data_offset_mc;\n wire final_dec_done_reg_0;\n wire final_dec_done_reg_1;\n wire fine_adj_state_r110_out;\n wire fine_adj_state_r134_out;\n wire fine_adj_state_r141_out;\n wire fine_adj_state_r144_out;\n wire fine_adj_state_r167_out;\n wire fine_adj_state_r16_out;\n wire fine_adj_state_r17_out;\n wire fine_adjust_done_r_reg_0;\n wire [2:0]fine_adjust_lane_cnt;\n wire fine_adjust_reg_0;\n wire first_fail_detect;\n wire first_fail_detect_i_1_n_0;\n wire first_fail_detect_i_2_n_0;\n wire first_fail_detect_reg_n_0;\n wire \\first_fail_taps[0]_i_1_n_0 ;\n wire \\first_fail_taps[1]_i_1_n_0 ;\n wire \\first_fail_taps[2]_i_1_n_0 ;\n wire \\first_fail_taps[3]_i_1_n_0 ;\n wire \\first_fail_taps[4]_i_1_n_0 ;\n wire \\first_fail_taps[5]_i_2_n_0 ;\n wire \\first_fail_taps[5]_i_4_n_0 ;\n wire \\first_fail_taps[5]_i_5_n_0 ;\n wire \\first_fail_taps[5]_i_6_n_0 ;\n wire \\first_fail_taps[5]_i_7_n_0 ;\n wire \\first_fail_taps_reg_n_0_[0] ;\n wire \\first_fail_taps_reg_n_0_[1] ;\n wire \\first_fail_taps_reg_n_0_[2] ;\n wire \\first_fail_taps_reg_n_0_[3] ;\n wire \\first_fail_taps_reg_n_0_[4] ;\n wire \\first_fail_taps_reg_n_0_[5] ;\n wire \\gen_byte_sel_div1.byte_sel_cnt[2]_i_9_n_0 ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[1] ;\n wire \\gen_byte_sel_div1.calib_in_common_i_2_n_0 ;\n wire \\gen_byte_sel_div1.calib_in_common_i_5_n_0 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_3 ;\n wire \\gen_byte_sel_div1.ctl_lane_sel[2]_i_2_n_0 ;\n wire \\gen_byte_sel_div1.ctl_lane_sel_reg[0] ;\n wire \\gen_byte_sel_div1.ctl_lane_sel_reg[0]_0 ;\n wire \\gen_byte_sel_div1.ctl_lane_sel_reg[1] ;\n wire \\gen_byte_sel_div1.ctl_lane_sel_reg[1]_0 ;\n wire \\gen_byte_sel_div1.ctl_lane_sel_reg[2] ;\n wire \\gen_byte_sel_div1.ctl_lane_sel_reg[2]_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ;\n wire ififo_rst_reg;\n wire ififo_rst_reg_0;\n wire ififo_rst_reg_1;\n wire ififo_rst_reg_2;\n wire [3:0]in0;\n wire inc_cnt;\n wire \\inc_cnt[4]_i_1_n_0 ;\n wire \\inc_cnt_reg_n_0_[0] ;\n wire \\inc_cnt_reg_n_0_[1] ;\n wire \\inc_cnt_reg_n_0_[2] ;\n wire \\inc_cnt_reg_n_0_[3] ;\n wire \\inc_cnt_reg_n_0_[4] ;\n wire \\inc_cnt_reg_n_0_[5] ;\n wire init_calib_complete_reg;\n wire init_dec_cnt;\n wire [5:0]init_dec_cnt0;\n wire \\init_dec_cnt[1]_i_1_n_0 ;\n wire [5:0]init_dec_cnt_reg__0;\n wire init_dec_done_reg_0;\n wire init_dec_done_reg_1;\n wire init_dec_done_reg_2;\n wire init_dqsfound_done_r1_reg_n_0;\n wire init_dqsfound_done_r2;\n wire init_dqsfound_done_r4_reg_srl2_n_0;\n wire init_dqsfound_done_r5;\n wire init_dqsfound_done_r_reg_0;\n wire \\init_state_r[1]_i_29_n_0 ;\n wire \\init_state_r[1]_i_30_n_0 ;\n wire \\init_state_r_reg[1] ;\n wire \\init_state_r_reg[1]_0 ;\n wire \\init_state_r_reg[1]_1 ;\n wire \\init_state_r_reg[2] ;\n wire mpr_rdlvl_done_r_reg;\n wire n_0_0;\n wire n_0_1;\n wire n_0_2;\n wire n_0_3;\n wire \\num_refresh_reg[1] ;\n wire oclkdelay_calib_done_r_reg;\n wire oclkdelay_calib_done_r_reg_0;\n wire oclkdelay_center_calib_done_r_reg;\n wire [5:0]p_0_in;\n wire p_0_in19_in;\n wire [5:0]p_0_in__0;\n wire [4:0]p_0_in__1;\n wire [5:0]p_1_in;\n wire p_1_in27_in;\n wire p_1_in50_in;\n wire p_22_out;\n wire pi_calib_done;\n wire [0:0]pi_dqs_found_all_bank;\n wire \\pi_dqs_found_all_bank[0]_i_1_n_0 ;\n wire [0:0]\\pi_dqs_found_all_bank_r_reg[1]_0 ;\n wire \\pi_dqs_found_all_bank_r_reg[1]_1 ;\n wire [0:0]pi_dqs_found_any_bank;\n wire \\pi_dqs_found_any_bank_r_reg_n_0_[0] ;\n wire pi_dqs_found_done_r1;\n wire pi_dqs_found_done_r1_reg;\n (* async_reg = \"true\" *) wire [7:0]pi_dqs_found_lanes_r1;\n (* async_reg = \"true\" *) wire [7:0]pi_dqs_found_lanes_r2;\n (* async_reg = \"true\" *) wire [7:0]pi_dqs_found_lanes_r3;\n wire \\pi_dqs_found_lanes_r3_reg[3]_0 ;\n wire pi_dqs_found_rank_done;\n wire pi_dqs_found_start_reg;\n wire pi_dqs_found_start_reg_0;\n wire pi_f_inc_reg;\n wire pi_fine_dly_dec_done;\n wire \\pi_rst_stg1_cal[0]_i_1_n_0 ;\n wire \\pi_rst_stg1_cal[1]_i_1_n_0 ;\n wire pi_rst_stg1_cal_r1_reg0;\n wire pi_rst_stg1_cal_r1_reg017_out;\n wire \\pi_rst_stg1_cal_r1_reg_n_0_[0] ;\n wire \\pi_rst_stg1_cal_r[0]_i_1_n_0 ;\n wire \\pi_rst_stg1_cal_r[0]_i_2_n_0 ;\n wire \\pi_rst_stg1_cal_r[0]_i_3_n_0 ;\n wire \\pi_rst_stg1_cal_r[1]_i_1_n_0 ;\n wire \\pi_rst_stg1_cal_r[1]_i_2_n_0 ;\n wire \\pi_rst_stg1_cal_r_reg[0]_0 ;\n wire \\pi_rst_stg1_cal_r_reg[0]_1 ;\n wire \\pi_rst_stg1_cal_reg_n_0_[1] ;\n wire \\po_counter_read_val_reg[8] ;\n wire \\po_counter_read_val_reg[8]_0 ;\n wire \\po_counter_read_val_reg[8]_1 ;\n wire \\po_counter_read_val_reg[8]_10 ;\n wire \\po_counter_read_val_reg[8]_11 ;\n wire \\po_counter_read_val_reg[8]_12 ;\n wire \\po_counter_read_val_reg[8]_2 ;\n wire \\po_counter_read_val_reg[8]_3 ;\n wire \\po_counter_read_val_reg[8]_4 ;\n wire \\po_counter_read_val_reg[8]_5 ;\n wire \\po_counter_read_val_reg[8]_6 ;\n wire \\po_counter_read_val_reg[8]_7 ;\n wire \\po_counter_read_val_reg[8]_8 ;\n wire \\po_counter_read_val_reg[8]_9 ;\n wire po_en_stg23;\n wire po_en_stg2_f;\n wire [0:0]po_enstg2_f;\n wire po_stg23_incdec;\n wire [0:0]po_stg2_fincdec;\n wire prbs_last_byte_done_r;\n wire prbs_rdlvl_done_reg_rep;\n wire prech_done;\n wire rank_done_r1;\n wire [1:0]rank_done_r_reg_0;\n wire \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0 ;\n wire \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1_n_0 ;\n wire \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1_n_0 ;\n wire \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1_n_0 ;\n wire \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1_n_0 ;\n wire \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2_n_0 ;\n wire [1:0]\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 ;\n wire \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ;\n wire \\rank_final_loop[0].final_do_index[0][0]_i_1_n_0 ;\n wire \\rank_final_loop[0].final_do_index[0][1]_i_1_n_0 ;\n wire \\rank_final_loop[0].final_do_index[0][2]_i_1_n_0 ;\n wire \\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ;\n wire \\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ;\n wire \\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ;\n wire \\rank_final_loop[0].final_do_max[0][0]_i_1_n_0 ;\n wire \\rank_final_loop[0].final_do_max[0][1]_i_1_n_0 ;\n wire \\rank_final_loop[0].final_do_max[0][2]_i_1_n_0 ;\n wire \\rank_final_loop[0].final_do_max[0][2]_i_2_n_0 ;\n wire \\rank_final_loop[0].final_do_max[0][3]_i_1_n_0 ;\n wire \\rank_final_loop[0].final_do_max[0][3]_i_2_n_0 ;\n wire \\rank_final_loop[0].final_do_max[0][4]_i_1_n_0 ;\n wire \\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ;\n wire \\rank_final_loop[0].final_do_max[0][5]_i_2_n_0 ;\n wire \\rank_final_loop[0].final_do_max[0][5]_i_3_n_0 ;\n wire \\rank_final_loop[0].final_do_max[0][5]_i_4_n_0 ;\n wire \\rank_final_loop[0].final_do_max[0][5]_i_5_n_0 ;\n wire \\rank_final_loop[0].final_do_max[0][5]_i_6_n_0 ;\n wire \\rank_final_loop[0].final_do_max[0][5]_i_7_n_0 ;\n wire \\rank_final_loop[0].final_do_max[0][5]_i_8_n_0 ;\n wire \\rank_final_loop[0].final_do_max[0][5]_i_9_n_0 ;\n wire [1:0]\\rank_final_loop[0].final_do_max_reg[0][3]_0 ;\n wire [1:0]\\rank_final_loop[0].final_do_max_reg[0][3]_1 ;\n wire [5:0]\\rank_final_loop[0].final_do_max_reg[0]__0 ;\n wire rd_byte_data_offset;\n wire \\rd_byte_data_offset[0][11]_i_1_n_0 ;\n wire \\rd_byte_data_offset[0][11]_i_2_n_0 ;\n wire \\rd_byte_data_offset[0][11]_i_4_n_0 ;\n wire \\rd_byte_data_offset[0][5]_i_1_n_0 ;\n wire \\rd_byte_data_offset[0][5]_i_3_n_0 ;\n wire \\rd_byte_data_offset[0][5]_i_4_n_0 ;\n wire \\rd_byte_data_offset[0][7]_i_1_n_0 ;\n wire [1:0]\\rd_byte_data_offset_reg[0][9]_0 ;\n wire \\rd_byte_data_offset_reg[0]_3 ;\n wire \\rd_byte_data_offset_reg_n_0_[0][0] ;\n wire \\rd_byte_data_offset_reg_n_0_[0][1] ;\n wire \\rd_byte_data_offset_reg_n_0_[0][4] ;\n wire \\rd_byte_data_offset_reg_n_0_[0][5] ;\n wire rd_data_offset_cal_done;\n wire [5:0]rd_data_offset_ranks_0;\n wire [5:0]rd_data_offset_ranks_1;\n wire rdlvl_stg1_done_int_reg;\n wire \\rnk_cnt_r[0]_i_1_n_0 ;\n wire \\rnk_cnt_r[1]_i_1_n_0 ;\n wire \\rnk_cnt_r_reg_n_0_[0] ;\n wire \\rnk_cnt_r_reg_n_0_[1] ;\n wire rst_dqs_find;\n wire rst_dqs_find_i_5_n_0;\n wire rst_dqs_find_i_6_n_0;\n wire rst_dqs_find_r1;\n wire rst_dqs_find_r1_reg_0;\n wire rst_dqs_find_r2;\n wire rst_dqs_find_reg_0;\n wire rst_dqs_find_reg_1;\n wire [0:0]rst_stg1_cal;\n wire rstdiv0_sync_r1_reg_rep__12;\n wire rstdiv0_sync_r1_reg_rep__13;\n wire [0:0]rstdiv0_sync_r1_reg_rep__19;\n wire rstdiv0_sync_r1_reg_rep__2;\n wire rstdiv0_sync_r1_reg_rep__24;\n wire rstdiv0_sync_r1_reg_rep__25;\n wire sent_col;\n wire stable_pass_cnt;\n wire \\stable_pass_cnt[3]_i_1_n_0 ;\n wire \\stable_pass_cnt[5]_i_2_n_0 ;\n wire \\stable_pass_cnt[5]_i_3_n_0 ;\n wire [5:1]stable_pass_cnt_reg__0;\n wire \\stable_pass_cnt_reg_n_0_[0] ;\n wire tempmon_sel_pi_incdec;\n wire wrcal_done_reg;\n wire wrlvl_byte_redo;\n wire wrlvl_done_r1;\n wire wrlvl_final_mux;\n wire [0:0]\\NLW_dec_cnt_reg[0]_i_3_O_UNCONNECTED ;\n wire [3:1]\\NLW_dec_cnt_reg[4]_i_4_CO_UNCONNECTED ;\n wire [3:2]\\NLW_dec_cnt_reg[4]_i_4_O_UNCONNECTED ;\n\n assign out[3:0] = pi_dqs_found_lanes_r3[3:0];\n LUT6 #(\n .INIT(64'hF3B0FFFFF3B00000)) \n \\FSM_sequential_fine_adj_state_r[0]_i_1 \n (.I0(\\FSM_sequential_fine_adj_state_r_reg[0]_1 ),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .I3(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .I4(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]),\n .I5(\\FSM_sequential_fine_adj_state_r_reg[0]_i_3_n_0 ),\n .O(\\FSM_sequential_fine_adj_state_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair271\" *) \n LUT4 #(\n .INIT(16'h0008)) \n \\FSM_sequential_fine_adj_state_r[0]_i_2 \n (.I0(fine_adjust_lane_cnt[1]),\n .I1(fine_adjust_lane_cnt[0]),\n .I2(\\ctl_lane_cnt_reg_n_0_[3] ),\n .I3(fine_adjust_lane_cnt[2]),\n .O(\\FSM_sequential_fine_adj_state_r_reg[0]_1 ));\n LUT5 #(\n .INIT(32'hA8AAFFFF)) \n \\FSM_sequential_fine_adj_state_r[0]_i_4 \n (.I0(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .I1(\\dec_cnt_reg[0]_0 ),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[2]_0 ),\n .I3(\\FSM_sequential_fine_adj_state_r_reg[0]_1 ),\n .I4(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .O(\\FSM_sequential_fine_adj_state_r[0]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'hCCCC7477)) \n \\FSM_sequential_fine_adj_state_r[0]_i_5 \n (.I0(fine_adj_state_r167_out),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[2]_0 ),\n .I3(final_dec_done_reg_0),\n .I4(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .O(\\FSM_sequential_fine_adj_state_r[0]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFAFF0AFF030F030)) \n \\FSM_sequential_fine_adj_state_r[1]_i_2 \n (.I0(fine_adj_state_r167_out),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[2]_0 ),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I3(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .I4(\\FSM_sequential_fine_adj_state_r[1]_i_5_n_0 ),\n .I5(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .O(\\FSM_sequential_fine_adj_state_r[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FFEA00EA)) \n \\FSM_sequential_fine_adj_state_r[1]_i_3 \n (.I0(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .I1(pi_dqs_found_all_bank),\n .I2(\\pi_dqs_found_all_bank_r_reg[1]_0 ),\n .I3(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .I4(\\FSM_sequential_fine_adj_state_r[3]_i_6_n_0 ),\n .I5(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .O(\\FSM_sequential_fine_adj_state_r[1]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair269\" *) \n LUT5 #(\n .INIT(32'h00000040)) \n \\FSM_sequential_fine_adj_state_r[1]_i_4 \n (.I0(detect_rd_cnt_reg__0[1]),\n .I1(detect_rd_cnt_reg__0[0]),\n .I2(detect_pi_found_dqs),\n .I3(detect_rd_cnt_reg__0[2]),\n .I4(detect_rd_cnt_reg__0[3]),\n .O(fine_adj_state_r167_out));\n LUT6 #(\n .INIT(64'h0000000000001000)) \n \\FSM_sequential_fine_adj_state_r[1]_i_5 \n (.I0(fine_adjust_lane_cnt[2]),\n .I1(\\ctl_lane_cnt_reg_n_0_[3] ),\n .I2(fine_adjust_lane_cnt[0]),\n .I3(fine_adjust_lane_cnt[1]),\n .I4(\\dec_cnt_reg[0]_0 ),\n .I5(\\FSM_sequential_fine_adj_state_r_reg[2]_0 ),\n .O(\\FSM_sequential_fine_adj_state_r[1]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h0033CCBB33FFFC00)) \n \\FSM_sequential_fine_adj_state_r[2]_i_1 \n (.I0(\\FSM_sequential_fine_adj_state_r[2]_i_2_n_0 ),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[2]_0 ),\n .I3(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I4(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .I5(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .O(\\FSM_sequential_fine_adj_state_r[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hC8FF40FF88FF0000)) \n \\FSM_sequential_fine_adj_state_r[2]_i_2 \n (.I0(\\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ),\n .I1(\\FSM_sequential_fine_adj_state_r[2]_i_4_n_0 ),\n .I2(fine_adj_state_r134_out),\n .I3(fine_adj_state_r144_out),\n .I4(fine_adj_state_r110_out),\n .I5(fine_adj_state_r17_out),\n .O(\\FSM_sequential_fine_adj_state_r[2]_i_2_n_0 ));\n LUT3 #(\n .INIT(8'h8F)) \n \\FSM_sequential_fine_adj_state_r[2]_i_3 \n (.I0(\\first_fail_taps[5]_i_5_n_0 ),\n .I1(\\first_fail_taps[5]_i_7_n_0 ),\n .I2(first_fail_detect_reg_n_0),\n .O(\\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ));\n LUT3 #(\n .INIT(8'h54)) \n \\FSM_sequential_fine_adj_state_r[2]_i_4 \n (.I0(fine_adj_state_r141_out),\n .I1(first_fail_detect_i_2_n_0),\n .I2(first_fail_detect_reg_n_0),\n .O(\\FSM_sequential_fine_adj_state_r[2]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h0000BF00)) \n \\FSM_sequential_fine_adj_state_r[2]_i_5 \n (.I0(\\first_fail_taps[5]_i_6_n_0 ),\n .I1(\\inc_cnt_reg_n_0_[0] ),\n .I2(\\inc_cnt_reg_n_0_[4] ),\n .I3(\\first_fail_taps[5]_i_5_n_0 ),\n .I4(\\first_fail_taps[5]_i_7_n_0 ),\n .O(fine_adj_state_r134_out));\n LUT6 #(\n .INIT(64'h0000000000101000)) \n \\FSM_sequential_fine_adj_state_r[2]_i_6 \n (.I0(\\inc_cnt_reg_n_0_[0] ),\n .I1(\\inc_cnt_reg_n_0_[1] ),\n .I2(\\inc_cnt_reg_n_0_[3] ),\n .I3(\\inc_cnt_reg_n_0_[2] ),\n .I4(\\inc_cnt_reg_n_0_[4] ),\n .I5(\\inc_cnt_reg_n_0_[5] ),\n .O(fine_adj_state_r110_out));\n LUT6 #(\n .INIT(64'h0000008000000028)) \n \\FSM_sequential_fine_adj_state_r[2]_i_7 \n (.I0(\\inc_cnt_reg_n_0_[5] ),\n .I1(\\inc_cnt_reg_n_0_[4] ),\n .I2(\\inc_cnt_reg_n_0_[2] ),\n .I3(\\inc_cnt_reg_n_0_[0] ),\n .I4(\\inc_cnt_reg_n_0_[1] ),\n .I5(\\inc_cnt_reg_n_0_[3] ),\n .O(fine_adj_state_r17_out));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\FSM_sequential_fine_adj_state_r[3]_i_1 \n (.I0(\\FSM_sequential_fine_adj_state_r[3]_i_3_n_0 ),\n .I1(detect_pi_found_dqs),\n .I2(\\FSM_sequential_fine_adj_state_r[3]_i_4_n_0 ),\n .I3(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]),\n .I4(\\FSM_sequential_fine_adj_state_r[3]_i_5_n_0 ),\n .O(\\FSM_sequential_fine_adj_state_r[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h33BBFF88CC003000)) \n \\FSM_sequential_fine_adj_state_r[3]_i_2 \n (.I0(\\FSM_sequential_fine_adj_state_r[3]_i_6_n_0 ),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[2]_0 ),\n .I3(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I4(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .I5(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .O(\\FSM_sequential_fine_adj_state_r[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hBFBFBFBFFFFCFCFC)) \n \\FSM_sequential_fine_adj_state_r[3]_i_3 \n (.I0(prech_done),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .I3(pi_dqs_found_all_bank),\n .I4(\\pi_dqs_found_all_bank_r_reg[1]_0 ),\n .I5(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .O(\\FSM_sequential_fine_adj_state_r[3]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hBFBFBFBFCFCCCCCC)) \n \\FSM_sequential_fine_adj_state_r[3]_i_4 \n (.I0(prech_done),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .I3(\\pi_dqs_found_all_bank_r_reg[1]_0 ),\n .I4(pi_dqs_found_all_bank),\n .I5(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .O(\\FSM_sequential_fine_adj_state_r[3]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFF4FFFFFFF40)) \n \\FSM_sequential_fine_adj_state_r[3]_i_5 \n (.I0(pi_dqs_found_any_bank),\n .I1(rst_dqs_find_r2),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I3(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .I4(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .I5(init_dqsfound_done_r5),\n .O(\\FSM_sequential_fine_adj_state_r[3]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'h0000FD0D)) \n \\FSM_sequential_fine_adj_state_r[3]_i_6 \n (.I0(first_fail_detect_i_2_n_0),\n .I1(fine_adj_state_r16_out),\n .I2(fine_adj_state_r144_out),\n .I3(\\FSM_sequential_fine_adj_state_r[3]_i_8_n_0 ),\n .I4(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .O(\\FSM_sequential_fine_adj_state_r[3]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\FSM_sequential_fine_adj_state_r[3]_i_7 \n (.I0(init_dec_cnt_reg__0[5]),\n .I1(init_dec_cnt_reg__0[3]),\n .I2(init_dec_cnt_reg__0[0]),\n .I3(init_dec_cnt_reg__0[1]),\n .I4(init_dec_cnt_reg__0[2]),\n .I5(init_dec_cnt_reg__0[4]),\n .O(\\FSM_sequential_fine_adj_state_r_reg[2]_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFB8FFFFFFBB)) \n \\FSM_sequential_fine_adj_state_r[3]_i_8 \n (.I0(fine_adj_state_r110_out),\n .I1(\\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ),\n .I2(fine_adj_state_r17_out),\n .I3(fine_adj_state_r141_out),\n .I4(\\FSM_sequential_fine_adj_state_r[3]_i_9_n_0 ),\n .I5(fine_adj_state_r134_out),\n .O(\\FSM_sequential_fine_adj_state_r[3]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h1)) \n \\FSM_sequential_fine_adj_state_r[3]_i_9 \n (.I0(first_fail_detect_reg_n_0),\n .I1(first_fail_detect_i_2_n_0),\n .O(\\FSM_sequential_fine_adj_state_r[3]_i_9_n_0 ));\n (* KEEP = \"yes\" *) \n FDRE \\FSM_sequential_fine_adj_state_r_reg[0] \n (.C(CLK),\n .CE(\\FSM_sequential_fine_adj_state_r[3]_i_1_n_0 ),\n .D(\\FSM_sequential_fine_adj_state_r[0]_i_1_n_0 ),\n .Q(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n MUXF7 \\FSM_sequential_fine_adj_state_r_reg[0]_i_3 \n (.I0(\\FSM_sequential_fine_adj_state_r[0]_i_4_n_0 ),\n .I1(\\FSM_sequential_fine_adj_state_r[0]_i_5_n_0 ),\n .O(\\FSM_sequential_fine_adj_state_r_reg[0]_i_3_n_0 ),\n .S(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]));\n (* KEEP = \"yes\" *) \n FDRE \\FSM_sequential_fine_adj_state_r_reg[1] \n (.C(CLK),\n .CE(\\FSM_sequential_fine_adj_state_r[3]_i_1_n_0 ),\n .D(\\FSM_sequential_fine_adj_state_r_reg[1]_i_1_n_0 ),\n .Q(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n MUXF7 \\FSM_sequential_fine_adj_state_r_reg[1]_i_1 \n (.I0(\\FSM_sequential_fine_adj_state_r[1]_i_2_n_0 ),\n .I1(\\FSM_sequential_fine_adj_state_r[1]_i_3_n_0 ),\n .O(\\FSM_sequential_fine_adj_state_r_reg[1]_i_1_n_0 ),\n .S(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]));\n (* KEEP = \"yes\" *) \n FDRE \\FSM_sequential_fine_adj_state_r_reg[2] \n (.C(CLK),\n .CE(\\FSM_sequential_fine_adj_state_r[3]_i_1_n_0 ),\n .D(\\FSM_sequential_fine_adj_state_r[2]_i_1_n_0 ),\n .Q(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n (* KEEP = \"yes\" *) \n FDRE \\FSM_sequential_fine_adj_state_r_reg[3] \n (.C(CLK),\n .CE(\\FSM_sequential_fine_adj_state_r[3]_i_1_n_0 ),\n .D(\\FSM_sequential_fine_adj_state_r[3]_i_2_n_0 ),\n .Q(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n (* SOFT_HLUTNM = \"soft_lutpair296\" *) \n LUT4 #(\n .INIT(16'hCDC8)) \n \\calib_data_offset_0[0]_i_1 \n (.I0(pi_dqs_found_done_r1),\n .I1(rd_data_offset_ranks_0[0]),\n .I2(init_dqsfound_done_r2),\n .I3(\\rd_byte_data_offset_reg_n_0_[0][0] ),\n .O(\\calib_data_offset_0_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair295\" *) \n LUT4 #(\n .INIT(16'hCDC8)) \n \\calib_data_offset_0[1]_i_1 \n (.I0(pi_dqs_found_done_r1),\n .I1(rd_data_offset_ranks_0[1]),\n .I2(init_dqsfound_done_r2),\n .I3(\\rd_byte_data_offset_reg_n_0_[0][1] ),\n .O(\\calib_data_offset_0_reg[1] ));\n LUT4 #(\n .INIT(16'hCDC8)) \n \\calib_data_offset_0[4]_i_1 \n (.I0(pi_dqs_found_done_r1),\n .I1(rd_data_offset_ranks_0[4]),\n .I2(init_dqsfound_done_r2),\n .I3(\\rd_byte_data_offset_reg_n_0_[0][4] ),\n .O(\\calib_data_offset_0_reg[4] ));\n LUT4 #(\n .INIT(16'hCDC8)) \n \\calib_data_offset_0[5]_i_2 \n (.I0(pi_dqs_found_done_r1),\n .I1(rd_data_offset_ranks_0[5]),\n .I2(init_dqsfound_done_r2),\n .I3(\\rd_byte_data_offset_reg_n_0_[0][5] ),\n .O(\\calib_data_offset_0_reg[5] ));\n (* SOFT_HLUTNM = \"soft_lutpair298\" *) \n LUT4 #(\n .INIT(16'hCDC8)) \n \\calib_data_offset_1[0]_i_1 \n (.I0(pi_dqs_found_done_r1),\n .I1(rd_data_offset_ranks_1[0]),\n .I2(init_dqsfound_done_r2),\n .I3(p_0_in[0]),\n .O(\\calib_data_offset_1_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair294\" *) \n LUT4 #(\n .INIT(16'hCDC8)) \n \\calib_data_offset_1[1]_i_1 \n (.I0(pi_dqs_found_done_r1),\n .I1(rd_data_offset_ranks_1[1]),\n .I2(init_dqsfound_done_r2),\n .I3(p_0_in[1]),\n .O(\\calib_data_offset_1_reg[1] ));\n LUT4 #(\n .INIT(16'hCDC8)) \n \\calib_data_offset_1[4]_i_1 \n (.I0(pi_dqs_found_done_r1),\n .I1(rd_data_offset_ranks_1[4]),\n .I2(init_dqsfound_done_r2),\n .I3(p_0_in[4]),\n .O(\\calib_data_offset_1_reg[4] ));\n LUT4 #(\n .INIT(16'hCDC8)) \n \\calib_data_offset_1[5]_i_1 \n (.I0(pi_dqs_found_done_r1),\n .I1(rd_data_offset_ranks_1[5]),\n .I2(init_dqsfound_done_r2),\n .I3(p_0_in[5]),\n .O(\\calib_data_offset_1_reg[5] ));\n LUT6 #(\n .INIT(64'h4040404F00000000)) \n \\calib_sel[0]_i_1 \n (.I0(\\gen_byte_sel_div1.ctl_lane_sel_reg[2]_0 ),\n .I1(\\gen_byte_sel_div1.ctl_lane_sel_reg[0]_0 ),\n .I2(ctl_lane_sel),\n .I3(byte_sel_cnt),\n .I4(\\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ),\n .I5(init_calib_complete_reg),\n .O(D[0]));\n LUT6 #(\n .INIT(64'h4040404F00000000)) \n \\calib_sel[1]_i_1 \n (.I0(\\gen_byte_sel_div1.ctl_lane_sel_reg[2]_0 ),\n .I1(\\gen_byte_sel_div1.ctl_lane_sel_reg[1]_0 ),\n .I2(ctl_lane_sel),\n .I3(byte_sel_cnt),\n .I4(\\gen_byte_sel_div1.byte_sel_cnt_reg[1] ),\n .I5(init_calib_complete_reg),\n .O(D[1]));\n (* SOFT_HLUTNM = \"soft_lutpair283\" *) \n LUT5 #(\n .INIT(32'h08008888)) \n \\calib_sel[3]_i_2 \n (.I0(dqs_po_dec_done),\n .I1(pi_fine_dly_dec_done),\n .I2(fine_adjust_done_r_reg_0),\n .I3(rd_data_offset_cal_done),\n .I4(ck_addr_cmd_delay_done),\n .O(ctl_lane_sel));\n (* SOFT_HLUTNM = \"soft_lutpair290\" *) \n LUT4 #(\n .INIT(16'h10FF)) \n \\calib_zero_inputs[0]_i_1 \n (.I0(rst_stg1_cal),\n .I1(\\pi_rst_stg1_cal_reg_n_0_[1] ),\n .I2(ctl_lane_sel),\n .I3(init_calib_complete_reg),\n .O(\\calib_zero_inputs_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair283\" *) \n LUT3 #(\n .INIT(8'hA2)) \n \\calib_zero_inputs[1]_i_2 \n (.I0(ck_addr_cmd_delay_done),\n .I1(rd_data_offset_cal_done),\n .I2(fine_adjust_done_r_reg_0),\n .O(\\calib_zero_inputs_reg[1] ));\n FDRE ck_po_stg2_f_en_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_fine_adj_state_r_reg[1]_3 ),\n .Q(ck_po_stg2_f_en),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE ck_po_stg2_f_indec_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_fine_adj_state_r_reg[1]_2 ),\n .Q(ck_po_stg2_f_indec),\n .R(rstdiv0_sync_r1_reg_rep__12));\n LUT1 #(\n .INIT(2'h1)) \n \\cmd_pipe_plus.mc_data_offset[0]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_reg[5] [0]),\n .O(\\cmd_pipe_plus.mc_data_offset_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair284\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\cmd_pipe_plus.mc_data_offset[1]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_reg[5] [0]),\n .I1(\\cmd_pipe_plus.mc_data_offset_reg[5] [1]),\n .O(\\cmd_pipe_plus.mc_data_offset_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair287\" *) \n LUT4 #(\n .INIT(16'h2A80)) \n \\cmd_pipe_plus.mc_data_offset[2]_i_1 \n (.I0(sent_col),\n .I1(\\cmd_pipe_plus.mc_data_offset_reg[5] [0]),\n .I2(\\cmd_pipe_plus.mc_data_offset_reg[5] [1]),\n .I3(\\cmd_pipe_plus.mc_data_offset_reg[5] [2]),\n .O(\\cmd_pipe_plus.mc_data_offset_reg[2] ));\n (* SOFT_HLUTNM = \"soft_lutpair287\" *) \n LUT5 #(\n .INIT(32'h2AAA8000)) \n \\cmd_pipe_plus.mc_data_offset[3]_i_1 \n (.I0(sent_col),\n .I1(\\cmd_pipe_plus.mc_data_offset_reg[5] [1]),\n .I2(\\cmd_pipe_plus.mc_data_offset_reg[5] [0]),\n .I3(\\cmd_pipe_plus.mc_data_offset_reg[5] [2]),\n .I4(\\cmd_pipe_plus.mc_data_offset_reg[5] [3]),\n .O(\\cmd_pipe_plus.mc_data_offset_reg[3] ));\n (* SOFT_HLUTNM = \"soft_lutpair284\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\cmd_pipe_plus.mc_data_offset[4]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_reg[5] [4]),\n .I1(\\cmd_pipe_plus.mc_data_offset_reg[5] [3]),\n .I2(\\cmd_pipe_plus.mc_data_offset_reg[5] [1]),\n .I3(\\cmd_pipe_plus.mc_data_offset_reg[5] [0]),\n .I4(\\cmd_pipe_plus.mc_data_offset_reg[5] [2]),\n .O(\\cmd_pipe_plus.mc_data_offset_reg[4] ));\n LUT1 #(\n .INIT(2'h1)) \n \\cmd_pipe_plus.mc_data_offset_1[0]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [0]),\n .O(\\cmd_pipe_plus.mc_data_offset_1_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair280\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\cmd_pipe_plus.mc_data_offset_1[1]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [0]),\n .I1(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [1]),\n .O(\\cmd_pipe_plus.mc_data_offset_1_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair282\" *) \n LUT4 #(\n .INIT(16'h2A80)) \n \\cmd_pipe_plus.mc_data_offset_1[2]_i_1 \n (.I0(sent_col),\n .I1(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [0]),\n .I2(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [1]),\n .I3(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [2]),\n .O(\\cmd_pipe_plus.mc_data_offset_1_reg[2] ));\n (* SOFT_HLUTNM = \"soft_lutpair282\" *) \n LUT5 #(\n .INIT(32'h2AAA8000)) \n \\cmd_pipe_plus.mc_data_offset_1[3]_i_1 \n (.I0(sent_col),\n .I1(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [1]),\n .I2(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [0]),\n .I3(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [2]),\n .I4(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [3]),\n .O(\\cmd_pipe_plus.mc_data_offset_1_reg[3] ));\n (* SOFT_HLUTNM = \"soft_lutpair280\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\cmd_pipe_plus.mc_data_offset_1[4]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [4]),\n .I1(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [3]),\n .I2(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [1]),\n .I3(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [0]),\n .I4(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [2]),\n .O(\\cmd_pipe_plus.mc_data_offset_1_reg[4] ));\n (* SOFT_HLUTNM = \"soft_lutpair303\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\ctl_lane_cnt[0]_i_1__0 \n (.I0(fine_adjust_lane_cnt[0]),\n .O(ctl_lane_cnt__0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair303\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\ctl_lane_cnt[1]_i_1__0 \n (.I0(fine_adjust_lane_cnt[0]),\n .I1(fine_adjust_lane_cnt[1]),\n .O(ctl_lane_cnt__0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair293\" *) \n LUT4 #(\n .INIT(16'h4AAA)) \n \\ctl_lane_cnt[2]_i_1__0 \n (.I0(fine_adjust_lane_cnt[2]),\n .I1(\\ctl_lane_cnt_reg_n_0_[3] ),\n .I2(fine_adjust_lane_cnt[0]),\n .I3(fine_adjust_lane_cnt[1]),\n .O(ctl_lane_cnt__0[2]));\n LUT4 #(\n .INIT(16'h2040)) \n \\ctl_lane_cnt[3]_i_1__0 \n (.I0(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .I3(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .O(ctl_lane_cnt_0));\n (* SOFT_HLUTNM = \"soft_lutpair293\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\ctl_lane_cnt[3]_i_2__0 \n (.I0(\\ctl_lane_cnt_reg_n_0_[3] ),\n .I1(fine_adjust_lane_cnt[0]),\n .I2(fine_adjust_lane_cnt[1]),\n .I3(fine_adjust_lane_cnt[2]),\n .O(ctl_lane_cnt__0[3]));\n FDRE \\ctl_lane_cnt_reg[0] \n (.C(CLK),\n .CE(ctl_lane_cnt_0),\n .D(ctl_lane_cnt__0[0]),\n .Q(fine_adjust_lane_cnt[0]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE \\ctl_lane_cnt_reg[1] \n (.C(CLK),\n .CE(ctl_lane_cnt_0),\n .D(ctl_lane_cnt__0[1]),\n .Q(fine_adjust_lane_cnt[1]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE \\ctl_lane_cnt_reg[2] \n (.C(CLK),\n .CE(ctl_lane_cnt_0),\n .D(ctl_lane_cnt__0[2]),\n .Q(fine_adjust_lane_cnt[2]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE \\ctl_lane_cnt_reg[3] \n (.C(CLK),\n .CE(ctl_lane_cnt_0),\n .D(ctl_lane_cnt__0[3]),\n .Q(\\ctl_lane_cnt_reg_n_0_[3] ),\n .R(rstdiv0_sync_r1_reg_rep__2));\n LUT6 #(\n .INIT(64'h7444744474777444)) \n \\dec_cnt[0]_i_1 \n (.I0(\\dec_cnt_reg_n_0_[0] ),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I2(\\dec_cnt[0]_i_2_n_0 ),\n .I3(fine_adj_state_r144_out),\n .I4(\\dec_cnt_reg[0]_i_3_n_6 ),\n .I5(\\dec_cnt[5]_i_9_n_0 ),\n .O(dec_cnt[0]));\n LUT6 #(\n .INIT(64'h0000888BFFFF888B)) \n \\dec_cnt[0]_i_2 \n (.I0(\\dec_cnt_reg[0]_i_3_n_6 ),\n .I1(first_fail_detect_i_2_n_0),\n .I2(\\first_fail_taps_reg_n_0_[1] ),\n .I3(\\first_fail_taps[5]_i_5_n_0 ),\n .I4(fine_adj_state_r141_out),\n .I5(\\inc_cnt_reg_n_0_[1] ),\n .O(\\dec_cnt[0]_i_2_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\dec_cnt[0]_i_4 \n (.I0(\\inc_cnt_reg_n_0_[3] ),\n .I1(\\first_fail_taps_reg_n_0_[3] ),\n .O(\\dec_cnt[0]_i_4_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\dec_cnt[0]_i_5 \n (.I0(\\inc_cnt_reg_n_0_[2] ),\n .I1(\\first_fail_taps_reg_n_0_[2] ),\n .O(\\dec_cnt[0]_i_5_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\dec_cnt[0]_i_6 \n (.I0(\\inc_cnt_reg_n_0_[1] ),\n .I1(\\first_fail_taps_reg_n_0_[1] ),\n .O(\\dec_cnt[0]_i_6_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\dec_cnt[0]_i_7 \n (.I0(\\inc_cnt_reg_n_0_[0] ),\n .I1(\\first_fail_taps_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_7_n_0 ));\n LUT4 #(\n .INIT(16'h9F90)) \n \\dec_cnt[1]_i_1 \n (.I0(\\dec_cnt_reg_n_0_[0] ),\n .I1(\\dec_cnt_reg_n_0_[1] ),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I3(\\dec_cnt[1]_i_2_n_0 ),\n .O(dec_cnt[1]));\n LUT6 #(\n .INIT(64'h08880888FBBB0888)) \n \\dec_cnt[1]_i_2 \n (.I0(\\dec_cnt[1]_i_3_n_0 ),\n .I1(detect_pi_found_dqs),\n .I2(\\pi_dqs_found_all_bank_r_reg[1]_0 ),\n .I3(pi_dqs_found_all_bank),\n .I4(\\dec_cnt_reg[0]_i_3_n_5 ),\n .I5(\\dec_cnt[5]_i_9_n_0 ),\n .O(\\dec_cnt[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h6F606F6F6F606060)) \n \\dec_cnt[1]_i_3 \n (.I0(\\inc_cnt_reg_n_0_[1] ),\n .I1(\\inc_cnt_reg_n_0_[2] ),\n .I2(fine_adj_state_r141_out),\n .I3(\\dec_cnt_reg[0]_i_3_n_5 ),\n .I4(first_fail_detect_i_2_n_0),\n .I5(\\dec_cnt[1]_i_4_n_0 ),\n .O(\\dec_cnt[1]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h5555555540000000)) \n \\dec_cnt[1]_i_4 \n (.I0(\\first_fail_taps_reg_n_0_[2] ),\n .I1(stable_pass_cnt_reg__0[4]),\n .I2(stable_pass_cnt_reg__0[3]),\n .I3(stable_pass_cnt_reg__0[2]),\n .I4(stable_pass_cnt_reg__0[1]),\n .I5(stable_pass_cnt_reg__0[5]),\n .O(\\dec_cnt[1]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'hE1FFE100)) \n \\dec_cnt[2]_i_1 \n (.I0(\\dec_cnt_reg_n_0_[0] ),\n .I1(\\dec_cnt_reg_n_0_[1] ),\n .I2(\\dec_cnt_reg_n_0_[2] ),\n .I3(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I4(\\dec_cnt[2]_i_2_n_0 ),\n .O(dec_cnt[2]));\n LUT6 #(\n .INIT(64'h08880888FBBB0888)) \n \\dec_cnt[2]_i_2 \n (.I0(\\dec_cnt[2]_i_3_n_0 ),\n .I1(detect_pi_found_dqs),\n .I2(\\pi_dqs_found_all_bank_r_reg[1]_0 ),\n .I3(pi_dqs_found_all_bank),\n .I4(\\dec_cnt_reg[0]_i_3_n_4 ),\n .I5(\\dec_cnt[5]_i_9_n_0 ),\n .O(\\dec_cnt[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hB888B888B888B8BB)) \n \\dec_cnt[2]_i_3 \n (.I0(\\dec_cnt[2]_i_4_n_0 ),\n .I1(fine_adj_state_r141_out),\n .I2(\\dec_cnt_reg[0]_i_3_n_4 ),\n .I3(first_fail_detect_i_2_n_0),\n .I4(\\first_fail_taps_reg_n_0_[3] ),\n .I5(\\first_fail_taps[5]_i_5_n_0 ),\n .O(\\dec_cnt[2]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair300\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\dec_cnt[2]_i_4 \n (.I0(\\inc_cnt_reg_n_0_[3] ),\n .I1(\\inc_cnt_reg_n_0_[1] ),\n .I2(\\inc_cnt_reg_n_0_[2] ),\n .O(\\dec_cnt[2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFE01FFFFFE010000)) \n \\dec_cnt[3]_i_1 \n (.I0(\\dec_cnt_reg_n_0_[2] ),\n .I1(\\dec_cnt_reg_n_0_[1] ),\n .I2(\\dec_cnt_reg_n_0_[0] ),\n .I3(\\dec_cnt_reg_n_0_[3] ),\n .I4(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I5(\\dec_cnt[3]_i_2_n_0 ),\n .O(dec_cnt[3]));\n LUT6 #(\n .INIT(64'h08880888FBBB0888)) \n \\dec_cnt[3]_i_2 \n (.I0(\\dec_cnt[3]_i_3_n_0 ),\n .I1(detect_pi_found_dqs),\n .I2(\\pi_dqs_found_all_bank_r_reg[1]_0 ),\n .I3(pi_dqs_found_all_bank),\n .I4(\\dec_cnt_reg[4]_i_4_n_7 ),\n .I5(\\dec_cnt[5]_i_9_n_0 ),\n .O(\\dec_cnt[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hB888B888B888B8BB)) \n \\dec_cnt[3]_i_3 \n (.I0(\\dec_cnt[3]_i_4_n_0 ),\n .I1(fine_adj_state_r141_out),\n .I2(\\dec_cnt_reg[4]_i_4_n_7 ),\n .I3(first_fail_detect_i_2_n_0),\n .I4(\\first_fail_taps_reg_n_0_[4] ),\n .I5(\\first_fail_taps[5]_i_5_n_0 ),\n .O(\\dec_cnt[3]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair278\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\dec_cnt[3]_i_4 \n (.I0(\\inc_cnt_reg_n_0_[4] ),\n .I1(\\inc_cnt_reg_n_0_[3] ),\n .I2(\\inc_cnt_reg_n_0_[1] ),\n .I3(\\inc_cnt_reg_n_0_[2] ),\n .O(\\dec_cnt[3]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hB888B888B8BBB888)) \n \\dec_cnt[4]_i_1 \n (.I0(\\dec_cnt[4]_i_2_n_0 ),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I2(\\dec_cnt[4]_i_3_n_0 ),\n .I3(fine_adj_state_r144_out),\n .I4(\\dec_cnt_reg[4]_i_4_n_6 ),\n .I5(\\dec_cnt[5]_i_9_n_0 ),\n .O(dec_cnt[4]));\n (* SOFT_HLUTNM = \"soft_lutpair275\" *) \n LUT5 #(\n .INIT(32'hFFFE0001)) \n \\dec_cnt[4]_i_2 \n (.I0(\\dec_cnt_reg_n_0_[3] ),\n .I1(\\dec_cnt_reg_n_0_[0] ),\n .I2(\\dec_cnt_reg_n_0_[1] ),\n .I3(\\dec_cnt_reg_n_0_[2] ),\n .I4(\\dec_cnt_reg_n_0_[4] ),\n .O(\\dec_cnt[4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hB888B888B888B8BB)) \n \\dec_cnt[4]_i_3 \n (.I0(\\dec_cnt[4]_i_5_n_0 ),\n .I1(fine_adj_state_r141_out),\n .I2(\\dec_cnt_reg[4]_i_4_n_6 ),\n .I3(first_fail_detect_i_2_n_0),\n .I4(\\first_fail_taps_reg_n_0_[5] ),\n .I5(\\first_fail_taps[5]_i_5_n_0 ),\n .O(\\dec_cnt[4]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair278\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\dec_cnt[4]_i_5 \n (.I0(\\inc_cnt_reg_n_0_[5] ),\n .I1(\\inc_cnt_reg_n_0_[4] ),\n .I2(\\inc_cnt_reg_n_0_[2] ),\n .I3(\\inc_cnt_reg_n_0_[1] ),\n .I4(\\inc_cnt_reg_n_0_[3] ),\n .O(\\dec_cnt[4]_i_5_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\dec_cnt[4]_i_6 \n (.I0(\\inc_cnt_reg_n_0_[5] ),\n .I1(\\first_fail_taps_reg_n_0_[5] ),\n .O(\\dec_cnt[4]_i_6_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\dec_cnt[4]_i_7 \n (.I0(\\inc_cnt_reg_n_0_[4] ),\n .I1(\\first_fail_taps_reg_n_0_[4] ),\n .O(\\dec_cnt[4]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h0808C80800000000)) \n \\dec_cnt[5]_i_1 \n (.I0(\\dec_cnt[5]_i_3_n_0 ),\n .I1(\\dec_cnt[5]_i_4_n_0 ),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I3(\\dec_cnt_reg[0]_0 ),\n .I4(\\dec_cnt[5]_i_6_n_0 ),\n .I5(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]),\n .O(\\dec_cnt[5]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h2220)) \n \\dec_cnt[5]_i_10 \n (.I0(\\first_fail_taps[5]_i_4_n_0 ),\n .I1(fine_adj_state_r141_out),\n .I2(first_fail_detect_reg_n_0),\n .I3(first_fail_detect_i_2_n_0),\n .O(\\dec_cnt[5]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'h9F909F9F9F909090)) \n \\dec_cnt[5]_i_2 \n (.I0(\\dec_cnt[5]_i_7_n_0 ),\n .I1(\\dec_cnt_reg_n_0_[5] ),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I3(\\dec_cnt[5]_i_8_n_0 ),\n .I4(fine_adj_state_r144_out),\n .I5(\\dec_cnt[5]_i_9_n_0 ),\n .O(dec_cnt[5]));\n LUT6 #(\n .INIT(64'h0555000035550000)) \n \\dec_cnt[5]_i_3 \n (.I0(\\dec_cnt[5]_i_10_n_0 ),\n .I1(fine_adj_state_r16_out),\n .I2(pi_dqs_found_all_bank),\n .I3(\\pi_dqs_found_all_bank_r_reg[1]_0 ),\n .I4(detect_pi_found_dqs),\n .I5(first_fail_detect_i_2_n_0),\n .O(\\dec_cnt[5]_i_3_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\dec_cnt[5]_i_4 \n (.I0(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .O(\\dec_cnt[5]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\dec_cnt[5]_i_5 \n (.I0(\\dec_cnt_reg_n_0_[5] ),\n .I1(\\dec_cnt_reg_n_0_[3] ),\n .I2(\\dec_cnt_reg_n_0_[0] ),\n .I3(\\dec_cnt_reg_n_0_[1] ),\n .I4(\\dec_cnt_reg_n_0_[2] ),\n .I5(\\dec_cnt_reg_n_0_[4] ),\n .O(\\dec_cnt_reg[0]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair271\" *) \n LUT5 #(\n .INIT(32'hFEFFFFFF)) \n \\dec_cnt[5]_i_6 \n (.I0(\\FSM_sequential_fine_adj_state_r_reg[2]_0 ),\n .I1(fine_adjust_lane_cnt[2]),\n .I2(\\ctl_lane_cnt_reg_n_0_[3] ),\n .I3(fine_adjust_lane_cnt[0]),\n .I4(fine_adjust_lane_cnt[1]),\n .O(\\dec_cnt[5]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair275\" *) \n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n \\dec_cnt[5]_i_7 \n (.I0(\\dec_cnt_reg_n_0_[4] ),\n .I1(\\dec_cnt_reg_n_0_[2] ),\n .I2(\\dec_cnt_reg_n_0_[1] ),\n .I3(\\dec_cnt_reg_n_0_[0] ),\n .I4(\\dec_cnt_reg_n_0_[3] ),\n .O(\\dec_cnt[5]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h0080000000D00000)) \n \\dec_cnt[5]_i_8 \n (.I0(\\first_fail_taps[5]_i_5_n_0 ),\n .I1(\\inc_cnt_reg_n_0_[0] ),\n .I2(\\inc_cnt_reg_n_0_[4] ),\n .I3(\\first_fail_taps[5]_i_6_n_0 ),\n .I4(\\inc_cnt_reg_n_0_[5] ),\n .I5(first_fail_detect_reg_n_0),\n .O(\\dec_cnt[5]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'hFFFE0000FFFFFFFF)) \n \\dec_cnt[5]_i_9 \n (.I0(\\first_fail_taps_reg_n_0_[2] ),\n .I1(\\first_fail_taps_reg_n_0_[1] ),\n .I2(\\first_fail_taps_reg_n_0_[4] ),\n .I3(\\first_fail_taps_reg_n_0_[3] ),\n .I4(\\first_fail_taps_reg_n_0_[5] ),\n .I5(first_fail_detect_reg_n_0),\n .O(\\dec_cnt[5]_i_9_n_0 ));\n FDRE \\dec_cnt_reg[0] \n (.C(CLK),\n .CE(\\dec_cnt[5]_i_1_n_0 ),\n .D(dec_cnt[0]),\n .Q(\\dec_cnt_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n CARRY4 \\dec_cnt_reg[0]_i_3 \n (.CI(1'b0),\n .CO({\\dec_cnt_reg[0]_i_3_n_0 ,\\dec_cnt_reg[0]_i_3_n_1 ,\\dec_cnt_reg[0]_i_3_n_2 ,\\dec_cnt_reg[0]_i_3_n_3 }),\n .CYINIT(1'b1),\n .DI({\\inc_cnt_reg_n_0_[3] ,\\inc_cnt_reg_n_0_[2] ,\\inc_cnt_reg_n_0_[1] ,\\inc_cnt_reg_n_0_[0] }),\n .O({\\dec_cnt_reg[0]_i_3_n_4 ,\\dec_cnt_reg[0]_i_3_n_5 ,\\dec_cnt_reg[0]_i_3_n_6 ,\\NLW_dec_cnt_reg[0]_i_3_O_UNCONNECTED [0]}),\n .S({\\dec_cnt[0]_i_4_n_0 ,\\dec_cnt[0]_i_5_n_0 ,\\dec_cnt[0]_i_6_n_0 ,\\dec_cnt[0]_i_7_n_0 }));\n FDRE \\dec_cnt_reg[1] \n (.C(CLK),\n .CE(\\dec_cnt[5]_i_1_n_0 ),\n .D(dec_cnt[1]),\n .Q(\\dec_cnt_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE \\dec_cnt_reg[2] \n (.C(CLK),\n .CE(\\dec_cnt[5]_i_1_n_0 ),\n .D(dec_cnt[2]),\n .Q(\\dec_cnt_reg_n_0_[2] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE \\dec_cnt_reg[3] \n (.C(CLK),\n .CE(\\dec_cnt[5]_i_1_n_0 ),\n .D(dec_cnt[3]),\n .Q(\\dec_cnt_reg_n_0_[3] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE \\dec_cnt_reg[4] \n (.C(CLK),\n .CE(\\dec_cnt[5]_i_1_n_0 ),\n .D(dec_cnt[4]),\n .Q(\\dec_cnt_reg_n_0_[4] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n CARRY4 \\dec_cnt_reg[4]_i_4 \n (.CI(\\dec_cnt_reg[0]_i_3_n_0 ),\n .CO({\\NLW_dec_cnt_reg[4]_i_4_CO_UNCONNECTED [3:1],\\dec_cnt_reg[4]_i_4_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,\\inc_cnt_reg_n_0_[4] }),\n .O({\\NLW_dec_cnt_reg[4]_i_4_O_UNCONNECTED [3:2],\\dec_cnt_reg[4]_i_4_n_6 ,\\dec_cnt_reg[4]_i_4_n_7 }),\n .S({1'b0,1'b0,\\dec_cnt[4]_i_6_n_0 ,\\dec_cnt[4]_i_7_n_0 }));\n FDRE \\dec_cnt_reg[5] \n (.C(CLK),\n .CE(\\dec_cnt[5]_i_1_n_0 ),\n .D(dec_cnt[5]),\n .Q(\\dec_cnt_reg_n_0_[5] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n LUT1 #(\n .INIT(2'h1)) \n \\detect_rd_cnt[0]_i_1 \n (.I0(detect_rd_cnt_reg__0[0]),\n .O(detect_rd_cnt0__0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair299\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\detect_rd_cnt[1]_i_1 \n (.I0(detect_rd_cnt_reg__0[0]),\n .I1(detect_rd_cnt_reg__0[1]),\n .O(\\detect_rd_cnt[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair299\" *) \n LUT3 #(\n .INIT(8'hA9)) \n \\detect_rd_cnt[2]_i_1 \n (.I0(detect_rd_cnt_reg__0[2]),\n .I1(detect_rd_cnt_reg__0[1]),\n .I2(detect_rd_cnt_reg__0[0]),\n .O(detect_rd_cnt0__0[2]));\n LUT5 #(\n .INIT(32'hAAAAAAAB)) \n \\detect_rd_cnt[3]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__24),\n .I1(detect_rd_cnt_reg__0[2]),\n .I2(detect_rd_cnt_reg__0[3]),\n .I3(detect_rd_cnt_reg__0[0]),\n .I4(detect_rd_cnt_reg__0[1]),\n .O(\\detect_rd_cnt[3]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAAAAAAA8)) \n \\detect_rd_cnt[3]_i_2 \n (.I0(detect_pi_found_dqs),\n .I1(detect_rd_cnt_reg__0[2]),\n .I2(detect_rd_cnt_reg__0[3]),\n .I3(detect_rd_cnt_reg__0[0]),\n .I4(detect_rd_cnt_reg__0[1]),\n .O(detect_rd_cnt0));\n (* SOFT_HLUTNM = \"soft_lutpair269\" *) \n LUT4 #(\n .INIT(16'hAAA9)) \n \\detect_rd_cnt[3]_i_3 \n (.I0(detect_rd_cnt_reg__0[3]),\n .I1(detect_rd_cnt_reg__0[2]),\n .I2(detect_rd_cnt_reg__0[0]),\n .I3(detect_rd_cnt_reg__0[1]),\n .O(detect_rd_cnt0__0[3]));\n FDSE \\detect_rd_cnt_reg[0] \n (.C(CLK),\n .CE(detect_rd_cnt0),\n .D(detect_rd_cnt0__0[0]),\n .Q(detect_rd_cnt_reg__0[0]),\n .S(\\detect_rd_cnt[3]_i_1_n_0 ));\n FDSE \\detect_rd_cnt_reg[1] \n (.C(CLK),\n .CE(detect_rd_cnt0),\n .D(\\detect_rd_cnt[1]_i_1_n_0 ),\n .Q(detect_rd_cnt_reg__0[1]),\n .S(\\detect_rd_cnt[3]_i_1_n_0 ));\n FDSE \\detect_rd_cnt_reg[2] \n (.C(CLK),\n .CE(detect_rd_cnt0),\n .D(detect_rd_cnt0__0[2]),\n .Q(detect_rd_cnt_reg__0[2]),\n .S(\\detect_rd_cnt[3]_i_1_n_0 ));\n FDRE \\detect_rd_cnt_reg[3] \n (.C(CLK),\n .CE(detect_rd_cnt0),\n .D(detect_rd_cnt0__0[3]),\n .Q(detect_rd_cnt_reg__0[3]),\n .R(\\detect_rd_cnt[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000800000000000)) \n dqs_found_done_r_i_1\n (.I0(\\rd_byte_data_offset_reg[0]_3 ),\n .I1(init_dqsfound_done_r1_reg_n_0),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]),\n .I3(dqs_found_done_r_i_3_n_0),\n .I4(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I5(p_1_in27_in),\n .O(dqs_found_done_r0));\n LUT2 #(\n .INIT(4'h1)) \n dqs_found_done_r_i_2\n (.I0(\\rnk_cnt_r_reg_n_0_[1] ),\n .I1(\\rnk_cnt_r_reg_n_0_[0] ),\n .O(\\rd_byte_data_offset_reg[0]_3 ));\n LUT2 #(\n .INIT(4'h1)) \n dqs_found_done_r_i_3\n (.I0(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .O(dqs_found_done_r_i_3_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair292\" *) \n LUT2 #(\n .INIT(4'h8)) \n dqs_found_done_r_i_4\n (.I0(pi_dqs_found_all_bank),\n .I1(\\pi_dqs_found_all_bank_r_reg[1]_0 ),\n .O(p_1_in27_in));\n FDRE dqs_found_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(dqs_found_done_r0),\n .Q(pi_dqs_found_done_r1_reg),\n .R(rstdiv0_sync_r1_reg_rep__12));\n LUT6 #(\n .INIT(64'h0201010000020200)) \n dqs_found_prech_req_i_2\n (.I0(\\inc_cnt_reg_n_0_[3] ),\n .I1(\\inc_cnt_reg_n_0_[1] ),\n .I2(\\inc_cnt_reg_n_0_[0] ),\n .I3(\\inc_cnt_reg_n_0_[2] ),\n .I4(\\inc_cnt_reg_n_0_[4] ),\n .I5(\\inc_cnt_reg_n_0_[5] ),\n .O(fine_adj_state_r16_out));\n LUT3 #(\n .INIT(8'hB8)) \n dqs_found_prech_req_i_3\n (.I0(fine_adj_state_r110_out),\n .I1(\\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ),\n .I2(fine_adj_state_r17_out),\n .O(dqs_found_prech_req_reg_0));\n LUT6 #(\n .INIT(64'hC008000800000000)) \n dqs_found_prech_req_i_4\n (.I0(dqs_found_prech_req_i_5_n_0),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .I3(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I4(prech_done),\n .I5(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]),\n .O(dqs_found_prech_req_reg_1));\n LUT6 #(\n .INIT(64'hF0C0F040F0800000)) \n dqs_found_prech_req_i_5\n (.I0(\\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ),\n .I1(\\dec_cnt[5]_i_10_n_0 ),\n .I2(detect_pi_found_dqs),\n .I3(p_1_in27_in),\n .I4(fine_adj_state_r110_out),\n .I5(fine_adj_state_r17_out),\n .O(dqs_found_prech_req_i_5_n_0));\n FDRE dqs_found_prech_req_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_fine_adj_state_r_reg[2]_1 ),\n .Q(dqs_found_prech_req),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE dqs_found_start_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_start_reg),\n .Q(dqs_found_start_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFBF)) \n final_dec_done_i_2\n (.I0(\\dec_cnt_reg[0]_0 ),\n .I1(fine_adjust_lane_cnt[1]),\n .I2(fine_adjust_lane_cnt[0]),\n .I3(\\ctl_lane_cnt_reg_n_0_[3] ),\n .I4(fine_adjust_lane_cnt[2]),\n .I5(\\FSM_sequential_fine_adj_state_r_reg[2]_0 ),\n .O(final_dec_done_reg_1));\n FDRE final_dec_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_fine_adj_state_r_reg[1]_1 ),\n .Q(final_dec_done_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE fine_adjust_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_fine_adj_state_r_reg[0]_3 ),\n .Q(fine_adjust_done_r_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE fine_adjust_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_fine_adj_state_r_reg[0]_2 ),\n .Q(\\pi_rst_stg1_cal_r_reg[0]_0 ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n LUT5 #(\n .INIT(32'hFFFFAEAF)) \n first_fail_detect_i_1\n (.I0(\\first_fail_taps[5]_i_4_n_0 ),\n .I1(\\first_fail_taps[5]_i_5_n_0 ),\n .I2(first_fail_detect_i_2_n_0),\n .I3(first_fail_detect_reg_n_0),\n .I4(fine_adj_state_r141_out),\n .O(first_fail_detect_i_1_n_0));\n LUT6 #(\n .INIT(64'h7FFFFFFFFFFFFFFF)) \n first_fail_detect_i_2\n (.I0(\\inc_cnt_reg_n_0_[5] ),\n .I1(\\inc_cnt_reg_n_0_[3] ),\n .I2(\\inc_cnt_reg_n_0_[1] ),\n .I3(\\inc_cnt_reg_n_0_[2] ),\n .I4(\\inc_cnt_reg_n_0_[4] ),\n .I5(\\inc_cnt_reg_n_0_[0] ),\n .O(first_fail_detect_i_2_n_0));\n LUT6 #(\n .INIT(64'h000000000000FF08)) \n first_fail_detect_i_3\n (.I0(\\inc_cnt_reg_n_0_[4] ),\n .I1(\\inc_cnt_reg_n_0_[0] ),\n .I2(\\first_fail_taps[5]_i_6_n_0 ),\n .I3(\\inc_cnt_reg_n_0_[5] ),\n .I4(\\first_fail_taps[5]_i_5_n_0 ),\n .I5(first_fail_detect_reg_n_0),\n .O(fine_adj_state_r141_out));\n FDRE first_fail_detect_reg\n (.C(CLK),\n .CE(first_fail_detect),\n .D(first_fail_detect_i_1_n_0),\n .Q(first_fail_detect_reg_n_0),\n .R(rstdiv0_sync_r1_reg_rep__2));\n LUT3 #(\n .INIT(8'hB8)) \n \\first_fail_taps[0]_i_1 \n (.I0(\\inc_cnt_reg_n_0_[0] ),\n .I1(\\first_fail_taps[5]_i_4_n_0 ),\n .I2(\\first_fail_taps[5]_i_5_n_0 ),\n .O(\\first_fail_taps[0]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hB8)) \n \\first_fail_taps[1]_i_1 \n (.I0(\\inc_cnt_reg_n_0_[1] ),\n .I1(\\first_fail_taps[5]_i_4_n_0 ),\n .I2(\\first_fail_taps[5]_i_5_n_0 ),\n .O(\\first_fail_taps[1]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hB8)) \n \\first_fail_taps[2]_i_1 \n (.I0(\\inc_cnt_reg_n_0_[2] ),\n .I1(\\first_fail_taps[5]_i_4_n_0 ),\n .I2(\\first_fail_taps[5]_i_5_n_0 ),\n .O(\\first_fail_taps[2]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hB8)) \n \\first_fail_taps[3]_i_1 \n (.I0(\\inc_cnt_reg_n_0_[3] ),\n .I1(\\first_fail_taps[5]_i_4_n_0 ),\n .I2(\\first_fail_taps[5]_i_5_n_0 ),\n .O(\\first_fail_taps[3]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hB8)) \n \\first_fail_taps[4]_i_1 \n (.I0(\\inc_cnt_reg_n_0_[4] ),\n .I1(\\first_fail_taps[5]_i_4_n_0 ),\n .I2(\\first_fail_taps[5]_i_5_n_0 ),\n .O(\\first_fail_taps[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0020000000000000)) \n \\first_fail_taps[5]_i_1 \n (.I0(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .I3(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I4(fine_adj_state_r144_out),\n .I5(first_fail_detect_i_1_n_0),\n .O(first_fail_detect));\n LUT3 #(\n .INIT(8'hB8)) \n \\first_fail_taps[5]_i_2 \n (.I0(\\inc_cnt_reg_n_0_[5] ),\n .I1(\\first_fail_taps[5]_i_4_n_0 ),\n .I2(\\first_fail_taps[5]_i_5_n_0 ),\n .O(\\first_fail_taps[5]_i_2_n_0 ));\n LUT3 #(\n .INIT(8'h2A)) \n \\first_fail_taps[5]_i_3 \n (.I0(detect_pi_found_dqs),\n .I1(\\pi_dqs_found_all_bank_r_reg[1]_0 ),\n .I2(pi_dqs_found_all_bank),\n .O(fine_adj_state_r144_out));\n LUT6 #(\n .INIT(64'hFFFFF7FF00FF00FF)) \n \\first_fail_taps[5]_i_4 \n (.I0(\\inc_cnt_reg_n_0_[4] ),\n .I1(\\inc_cnt_reg_n_0_[0] ),\n .I2(\\first_fail_taps[5]_i_6_n_0 ),\n .I3(first_fail_detect_reg_n_0),\n .I4(\\first_fail_taps[5]_i_7_n_0 ),\n .I5(\\first_fail_taps[5]_i_5_n_0 ),\n .O(\\first_fail_taps[5]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h15555555)) \n \\first_fail_taps[5]_i_5 \n (.I0(stable_pass_cnt_reg__0[5]),\n .I1(stable_pass_cnt_reg__0[1]),\n .I2(stable_pass_cnt_reg__0[2]),\n .I3(stable_pass_cnt_reg__0[3]),\n .I4(stable_pass_cnt_reg__0[4]),\n .O(\\first_fail_taps[5]_i_5_n_0 ));\n LUT3 #(\n .INIT(8'h7F)) \n \\first_fail_taps[5]_i_6 \n (.I0(\\inc_cnt_reg_n_0_[2] ),\n .I1(\\inc_cnt_reg_n_0_[1] ),\n .I2(\\inc_cnt_reg_n_0_[3] ),\n .O(\\first_fail_taps[5]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h00000001FFFFFFFF)) \n \\first_fail_taps[5]_i_7 \n (.I0(\\inc_cnt_reg_n_0_[3] ),\n .I1(\\inc_cnt_reg_n_0_[1] ),\n .I2(\\inc_cnt_reg_n_0_[0] ),\n .I3(\\inc_cnt_reg_n_0_[2] ),\n .I4(\\inc_cnt_reg_n_0_[4] ),\n .I5(\\inc_cnt_reg_n_0_[5] ),\n .O(\\first_fail_taps[5]_i_7_n_0 ));\n FDRE \\first_fail_taps_reg[0] \n (.C(CLK),\n .CE(first_fail_detect),\n .D(\\first_fail_taps[0]_i_1_n_0 ),\n .Q(\\first_fail_taps_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE \\first_fail_taps_reg[1] \n (.C(CLK),\n .CE(first_fail_detect),\n .D(\\first_fail_taps[1]_i_1_n_0 ),\n .Q(\\first_fail_taps_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE \\first_fail_taps_reg[2] \n (.C(CLK),\n .CE(first_fail_detect),\n .D(\\first_fail_taps[2]_i_1_n_0 ),\n .Q(\\first_fail_taps_reg_n_0_[2] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE \\first_fail_taps_reg[3] \n (.C(CLK),\n .CE(first_fail_detect),\n .D(\\first_fail_taps[3]_i_1_n_0 ),\n .Q(\\first_fail_taps_reg_n_0_[3] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE \\first_fail_taps_reg[4] \n (.C(CLK),\n .CE(first_fail_detect),\n .D(\\first_fail_taps[4]_i_1_n_0 ),\n .Q(\\first_fail_taps_reg_n_0_[4] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE \\first_fail_taps_reg[5] \n (.C(CLK),\n .CE(first_fail_detect),\n .D(\\first_fail_taps[5]_i_2_n_0 ),\n .Q(\\first_fail_taps_reg_n_0_[5] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n LUT6 #(\n .INIT(64'hFFFFFFFF88A8FFFF)) \n \\gen_byte_sel_div1.byte_sel_cnt[2]_i_4 \n (.I0(ck_addr_cmd_delay_done),\n .I1(\\gen_byte_sel_div1.byte_sel_cnt[2]_i_9_n_0 ),\n .I2(rd_data_offset_cal_done),\n .I3(fine_adjust_done_r_reg_0),\n .I4(cmd_delay_start0),\n .I5(rstdiv0_sync_r1_reg_rep__25),\n .O(\\gen_byte_sel_div1.byte_sel_cnt_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair291\" *) \n LUT2 #(\n .INIT(4'h7)) \n \\gen_byte_sel_div1.byte_sel_cnt[2]_i_9 \n (.I0(pi_dqs_found_done_r1_reg),\n .I1(pi_calib_done),\n .O(\\gen_byte_sel_div1.byte_sel_cnt[2]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAEAAAAAAA2A)) \n \\gen_byte_sel_div1.calib_in_common_i_1 \n (.I0(\\gen_byte_sel_div1.calib_in_common_i_2_n_0 ),\n .I1(pi_dqs_found_done_r1_reg),\n .I2(pi_calib_done),\n .I3(oclkdelay_calib_done_r_reg),\n .I4(pi_f_inc_reg),\n .I5(calib_in_common),\n .O(\\gen_byte_sel_div1.calib_in_common_reg ));\n LUT6 #(\n .INIT(64'hBFBFFFBFFFBFFFBF)) \n \\gen_byte_sel_div1.calib_in_common_i_2 \n (.I0(\\gen_byte_sel_div1.calib_in_common_i_5_n_0 ),\n .I1(pi_fine_dly_dec_done),\n .I2(dqs_po_dec_done),\n .I3(\\calib_zero_inputs_reg[1] ),\n .I4(pi_calib_done),\n .I5(pi_dqs_found_done_r1_reg),\n .O(\\gen_byte_sel_div1.calib_in_common_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h3533000005000000)) \n \\gen_byte_sel_div1.calib_in_common_i_5 \n (.I0(\\gen_byte_sel_div1.ctl_lane_sel[2]_i_2_n_0 ),\n .I1(oclkdelay_calib_done_r_reg),\n .I2(fine_adjust_done_r_reg_0),\n .I3(rd_data_offset_cal_done),\n .I4(ck_addr_cmd_delay_done),\n .I5(tempmon_sel_pi_incdec),\n .O(\\gen_byte_sel_div1.calib_in_common_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h8F80FFFF8F800000)) \n \\gen_byte_sel_div1.ctl_lane_sel[0]_i_1 \n (.I0(\\gen_byte_sel_div1.ctl_lane_sel[2]_i_2_n_0 ),\n .I1(fine_adjust_lane_cnt[0]),\n .I2(ck_addr_cmd_delay_done),\n .I3(ctl_lane_cnt[0]),\n .I4(ctl_lane_sel),\n .I5(\\gen_byte_sel_div1.ctl_lane_sel_reg[0]_0 ),\n .O(\\gen_byte_sel_div1.ctl_lane_sel_reg[0] ));\n LUT6 #(\n .INIT(64'h8F80FFFF8F800000)) \n \\gen_byte_sel_div1.ctl_lane_sel[1]_i_1 \n (.I0(\\gen_byte_sel_div1.ctl_lane_sel[2]_i_2_n_0 ),\n .I1(fine_adjust_lane_cnt[1]),\n .I2(ck_addr_cmd_delay_done),\n .I3(ctl_lane_cnt[1]),\n .I4(ctl_lane_sel),\n .I5(\\gen_byte_sel_div1.ctl_lane_sel_reg[1]_0 ),\n .O(\\gen_byte_sel_div1.ctl_lane_sel_reg[1] ));\n LUT6 #(\n .INIT(64'h8F80FFFF8F800000)) \n \\gen_byte_sel_div1.ctl_lane_sel[2]_i_1 \n (.I0(\\gen_byte_sel_div1.ctl_lane_sel[2]_i_2_n_0 ),\n .I1(fine_adjust_lane_cnt[2]),\n .I2(ck_addr_cmd_delay_done),\n .I3(ctl_lane_cnt[2]),\n .I4(ctl_lane_sel),\n .I5(\\gen_byte_sel_div1.ctl_lane_sel_reg[2]_0 ),\n .O(\\gen_byte_sel_div1.ctl_lane_sel_reg[2] ));\n (* SOFT_HLUTNM = \"soft_lutpair290\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\gen_byte_sel_div1.ctl_lane_sel[2]_i_2 \n (.I0(rst_stg1_cal),\n .I1(\\pi_rst_stg1_cal_reg_n_0_[1] ),\n .O(\\gen_byte_sel_div1.ctl_lane_sel[2]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair289\" *) \n LUT3 #(\n .INIT(8'h80)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_3 \n (.I0(pi_dqs_found_done_r1_reg),\n .I1(rdlvl_stg1_done_int_reg),\n .I2(prbs_rdlvl_done_reg_rep),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] ));\n LUT1 #(\n .INIT(2'h2)) \n i_0\n (.I0(1'b1),\n .O(n_0_0));\n LUT1 #(\n .INIT(2'h2)) \n i_1\n (.I0(1'b1),\n .O(n_0_1));\n LUT1 #(\n .INIT(2'h2)) \n i_2\n (.I0(1'b1),\n .O(n_0_2));\n LUT1 #(\n .INIT(2'h2)) \n i_3\n (.I0(1'b1),\n .O(n_0_3));\n (* SOFT_HLUTNM = \"soft_lutpair302\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\inc_cnt[0]_i_1 \n (.I0(\\inc_cnt_reg_n_0_[0] ),\n .O(p_0_in__0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair302\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\inc_cnt[1]_i_1 \n (.I0(\\inc_cnt_reg_n_0_[0] ),\n .I1(\\inc_cnt_reg_n_0_[1] ),\n .O(p_0_in__0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair300\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\inc_cnt[2]_i_1 \n (.I0(\\inc_cnt_reg_n_0_[2] ),\n .I1(\\inc_cnt_reg_n_0_[1] ),\n .I2(\\inc_cnt_reg_n_0_[0] ),\n .O(p_0_in__0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair286\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\inc_cnt[3]_i_1 \n (.I0(\\inc_cnt_reg_n_0_[3] ),\n .I1(\\inc_cnt_reg_n_0_[0] ),\n .I2(\\inc_cnt_reg_n_0_[1] ),\n .I3(\\inc_cnt_reg_n_0_[2] ),\n .O(p_0_in__0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair286\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\inc_cnt[4]_i_1 \n (.I0(\\inc_cnt_reg_n_0_[4] ),\n .I1(\\inc_cnt_reg_n_0_[0] ),\n .I2(\\inc_cnt_reg_n_0_[2] ),\n .I3(\\inc_cnt_reg_n_0_[1] ),\n .I4(\\inc_cnt_reg_n_0_[3] ),\n .O(\\inc_cnt[4]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h00200000)) \n \\inc_cnt[5]_i_1 \n (.I0(\\FSM_sequential_fine_adj_state_r_reg[0]_1 ),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .I3(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I4(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]),\n .O(inc_cnt));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n \\inc_cnt[5]_i_2 \n (.I0(\\inc_cnt_reg_n_0_[5] ),\n .I1(\\inc_cnt_reg_n_0_[3] ),\n .I2(\\inc_cnt_reg_n_0_[1] ),\n .I3(\\inc_cnt_reg_n_0_[2] ),\n .I4(\\inc_cnt_reg_n_0_[0] ),\n .I5(\\inc_cnt_reg_n_0_[4] ),\n .O(p_0_in__0[5]));\n FDRE \\inc_cnt_reg[0] \n (.C(CLK),\n .CE(inc_cnt),\n .D(p_0_in__0[0]),\n .Q(\\inc_cnt_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE \\inc_cnt_reg[1] \n (.C(CLK),\n .CE(inc_cnt),\n .D(p_0_in__0[1]),\n .Q(\\inc_cnt_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE \\inc_cnt_reg[2] \n (.C(CLK),\n .CE(inc_cnt),\n .D(p_0_in__0[2]),\n .Q(\\inc_cnt_reg_n_0_[2] ),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE \\inc_cnt_reg[3] \n (.C(CLK),\n .CE(inc_cnt),\n .D(p_0_in__0[3]),\n .Q(\\inc_cnt_reg_n_0_[3] ),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE \\inc_cnt_reg[4] \n (.C(CLK),\n .CE(inc_cnt),\n .D(\\inc_cnt[4]_i_1_n_0 ),\n .Q(\\inc_cnt_reg_n_0_[4] ),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE \\inc_cnt_reg[5] \n (.C(CLK),\n .CE(inc_cnt),\n .D(p_0_in__0[5]),\n .Q(\\inc_cnt_reg_n_0_[5] ),\n .R(rstdiv0_sync_r1_reg_rep__2));\n LUT1 #(\n .INIT(2'h1)) \n \\init_dec_cnt[0]_i_1 \n (.I0(init_dec_cnt_reg__0[0]),\n .O(init_dec_cnt0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair301\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\init_dec_cnt[1]_i_1 \n (.I0(init_dec_cnt_reg__0[0]),\n .I1(init_dec_cnt_reg__0[1]),\n .O(\\init_dec_cnt[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair301\" *) \n LUT3 #(\n .INIT(8'hE1)) \n \\init_dec_cnt[2]_i_1 \n (.I0(init_dec_cnt_reg__0[0]),\n .I1(init_dec_cnt_reg__0[1]),\n .I2(init_dec_cnt_reg__0[2]),\n .O(init_dec_cnt0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair281\" *) \n LUT4 #(\n .INIT(16'hFE01)) \n \\init_dec_cnt[3]_i_1 \n (.I0(init_dec_cnt_reg__0[2]),\n .I1(init_dec_cnt_reg__0[1]),\n .I2(init_dec_cnt_reg__0[0]),\n .I3(init_dec_cnt_reg__0[3]),\n .O(init_dec_cnt0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair281\" *) \n LUT5 #(\n .INIT(32'hFFFE0001)) \n \\init_dec_cnt[4]_i_1 \n (.I0(init_dec_cnt_reg__0[3]),\n .I1(init_dec_cnt_reg__0[0]),\n .I2(init_dec_cnt_reg__0[1]),\n .I3(init_dec_cnt_reg__0[2]),\n .I4(init_dec_cnt_reg__0[4]),\n .O(init_dec_cnt0[4]));\n LUT6 #(\n .INIT(64'h2000000000000000)) \n \\init_dec_cnt[5]_i_1 \n (.I0(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .I3(\\FSM_sequential_fine_adj_state_r_reg[0]_1 ),\n .I4(\\FSM_sequential_fine_adj_state_r_reg[2]_0 ),\n .I5(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]),\n .O(init_dec_cnt));\n LUT6 #(\n .INIT(64'hFFFFFFFE00000001)) \n \\init_dec_cnt[5]_i_2 \n (.I0(init_dec_cnt_reg__0[4]),\n .I1(init_dec_cnt_reg__0[2]),\n .I2(init_dec_cnt_reg__0[1]),\n .I3(init_dec_cnt_reg__0[0]),\n .I4(init_dec_cnt_reg__0[3]),\n .I5(init_dec_cnt_reg__0[5]),\n .O(init_dec_cnt0[5]));\n FDSE \\init_dec_cnt_reg[0] \n (.C(CLK),\n .CE(init_dec_cnt),\n .D(init_dec_cnt0[0]),\n .Q(init_dec_cnt_reg__0[0]),\n .S(rstdiv0_sync_r1_reg_rep__2));\n FDSE \\init_dec_cnt_reg[1] \n (.C(CLK),\n .CE(init_dec_cnt),\n .D(\\init_dec_cnt[1]_i_1_n_0 ),\n .Q(init_dec_cnt_reg__0[1]),\n .S(rstdiv0_sync_r1_reg_rep__2));\n FDSE \\init_dec_cnt_reg[2] \n (.C(CLK),\n .CE(init_dec_cnt),\n .D(init_dec_cnt0[2]),\n .Q(init_dec_cnt_reg__0[2]),\n .S(rstdiv0_sync_r1_reg_rep__2));\n FDSE \\init_dec_cnt_reg[3] \n (.C(CLK),\n .CE(init_dec_cnt),\n .D(init_dec_cnt0[3]),\n .Q(init_dec_cnt_reg__0[3]),\n .S(rstdiv0_sync_r1_reg_rep__2));\n FDSE \\init_dec_cnt_reg[4] \n (.C(CLK),\n .CE(init_dec_cnt),\n .D(init_dec_cnt0[4]),\n .Q(init_dec_cnt_reg__0[4]),\n .S(rstdiv0_sync_r1_reg_rep__2));\n FDRE \\init_dec_cnt_reg[5] \n (.C(CLK),\n .CE(init_dec_cnt),\n .D(init_dec_cnt0[5]),\n .Q(init_dec_cnt_reg__0[5]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n LUT3 #(\n .INIT(8'h08)) \n init_dec_done_i_2\n (.I0(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .O(init_dec_done_reg_1));\n FDRE init_dec_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(init_dec_done_reg_2),\n .Q(init_dec_done_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE init_dqsfound_done_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rd_data_offset_cal_done),\n .Q(init_dqsfound_done_r1_reg_n_0),\n .R(1'b0));\n FDRE init_dqsfound_done_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(init_dqsfound_done_r1_reg_n_0),\n .Q(init_dqsfound_done_r2),\n .R(1'b0));\n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_right.u_ddr_phy_dqs_found_cal/init_dqsfound_done_r4_reg_srl2 \" *) \n SRL16E init_dqsfound_done_r4_reg_srl2\n (.A0(1'b1),\n .A1(1'b0),\n .A2(1'b0),\n .A3(1'b0),\n .CE(1'b1),\n .CLK(CLK),\n .D(init_dqsfound_done_r2),\n .Q(init_dqsfound_done_r4_reg_srl2_n_0));\n FDRE init_dqsfound_done_r5_reg\n (.C(CLK),\n .CE(1'b1),\n .D(init_dqsfound_done_r4_reg_srl2_n_0),\n .Q(init_dqsfound_done_r5),\n .R(1'b0));\n FDRE init_dqsfound_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(init_dqsfound_done_r_reg_0),\n .Q(rd_data_offset_cal_done),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0003FFFF33A3FFFF)) \n \\init_state_r[1]_i_14 \n (.I0(\\init_state_r[1]_i_29_n_0 ),\n .I1(\\num_refresh_reg[1] ),\n .I2(oclkdelay_calib_done_r_reg_0),\n .I3(mpr_rdlvl_done_r_reg),\n .I4(cnt_cmd_done_r),\n .I5(\\init_state_r[1]_i_30_n_0 ),\n .O(\\init_state_r_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair291\" *) \n LUT4 #(\n .INIT(16'h00DF)) \n \\init_state_r[1]_i_29 \n (.I0(pi_dqs_found_done_r1_reg),\n .I1(prbs_rdlvl_done_reg_rep),\n .I2(prbs_last_byte_done_r),\n .I3(wrcal_done_reg),\n .O(\\init_state_r[1]_i_29_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair289\" *) \n LUT4 #(\n .INIT(16'h5DFD)) \n \\init_state_r[1]_i_30 \n (.I0(pi_dqs_found_done_r1_reg),\n .I1(wrcal_done_reg),\n .I2(rdlvl_stg1_done_int_reg),\n .I3(prbs_rdlvl_done_reg_rep),\n .O(\\init_state_r[1]_i_30_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair288\" *) \n LUT2 #(\n .INIT(4'h7)) \n \\init_state_r[1]_i_31 \n (.I0(pi_dqs_found_done_r1_reg),\n .I1(wrcal_done_reg),\n .O(\\init_state_r_reg[1]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair288\" *) \n LUT4 #(\n .INIT(16'hFFFB)) \n \\init_state_r[1]_i_44 \n (.I0(wrlvl_final_mux),\n .I1(pi_dqs_found_done_r1_reg),\n .I2(wrlvl_byte_redo),\n .I3(wrlvl_done_r1),\n .O(\\init_state_r_reg[1]_0 ));\n LUT6 #(\n .INIT(64'hF0FDFDFDFDFDFDFD)) \n \\init_state_r[2]_i_31 \n (.I0(pi_dqs_found_done_r1_reg),\n .I1(wrlvl_byte_redo),\n .I2(wrlvl_done_r1),\n .I3(oclkdelay_center_calib_done_r_reg),\n .I4(prbs_rdlvl_done_reg_rep),\n .I5(rdlvl_stg1_done_int_reg),\n .O(\\init_state_r_reg[2] ));\n (* SOFT_HLUTNM = \"soft_lutpair266\" *) \n LUT5 #(\n .INIT(32'h0000EA00)) \n \\phaser_in_gen.phaser_in_i_5 \n (.I0(calib_in_common),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(rst_stg1_cal),\n .I4(\\calib_zero_inputs_reg[1]_0 [0]),\n .O(ififo_rst_reg));\n (* SOFT_HLUTNM = \"soft_lutpair266\" *) \n LUT5 #(\n .INIT(32'h0000BA00)) \n \\phaser_in_gen.phaser_in_i_5__0 \n (.I0(calib_in_common),\n .I1(Q[0]),\n .I2(Q[1]),\n .I3(rst_stg1_cal),\n .I4(\\calib_zero_inputs_reg[1]_0 [0]),\n .O(ififo_rst_reg_0));\n (* SOFT_HLUTNM = \"soft_lutpair267\" *) \n LUT5 #(\n .INIT(32'h0000BA00)) \n \\phaser_in_gen.phaser_in_i_5__1 \n (.I0(calib_in_common),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(rst_stg1_cal),\n .I4(\\calib_zero_inputs_reg[1]_0 [0]),\n .O(ififo_rst_reg_1));\n (* SOFT_HLUTNM = \"soft_lutpair267\" *) \n LUT5 #(\n .INIT(32'h0000AB00)) \n \\phaser_in_gen.phaser_in_i_5__2 \n (.I0(calib_in_common),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(rst_stg1_cal),\n .I4(\\calib_zero_inputs_reg[1]_0 [0]),\n .O(ififo_rst_reg_2));\n LUT6 #(\n .INIT(64'h00000000AAAAAAA8)) \n phaser_out_i_2__1\n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .I1(ck_po_stg2_f_en),\n .I2(dqs_po_en_stg2_f),\n .I3(po_en_stg2_f),\n .I4(po_en_stg23),\n .I5(\\calib_zero_inputs_reg[1]_0 [0]),\n .O(\\po_counter_read_val_reg[8]_6 ));\n LUT6 #(\n .INIT(64'h00000000AAAAAAA8)) \n phaser_out_i_2__2\n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .I1(ck_po_stg2_f_en),\n .I2(dqs_po_en_stg2_f),\n .I3(po_en_stg2_f),\n .I4(po_en_stg23),\n .I5(\\calib_zero_inputs_reg[1]_0 [0]),\n .O(\\po_counter_read_val_reg[8]_8 ));\n LUT6 #(\n .INIT(64'h00000000AAAAAAA8)) \n phaser_out_i_2__3\n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_2 ),\n .I1(ck_po_stg2_f_en),\n .I2(dqs_po_en_stg2_f),\n .I3(po_en_stg2_f),\n .I4(po_en_stg23),\n .I5(\\calib_zero_inputs_reg[1]_0 [0]),\n .O(\\po_counter_read_val_reg[8]_10 ));\n LUT6 #(\n .INIT(64'h00000000AAAAAAA8)) \n phaser_out_i_2__4\n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_3 ),\n .I1(ck_po_stg2_f_en),\n .I2(dqs_po_en_stg2_f),\n .I3(po_en_stg2_f),\n .I4(po_en_stg23),\n .I5(\\calib_zero_inputs_reg[1]_0 [0]),\n .O(\\po_counter_read_val_reg[8]_12 ));\n (* SOFT_HLUTNM = \"soft_lutpair270\" *) \n LUT5 #(\n .INIT(32'h00000800)) \n phaser_out_i_3\n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(calib_in_common),\n .I3(po_enstg2_f),\n .I4(\\calib_zero_inputs_reg[1]_0 [1]),\n .O(D_po_fine_enable107_out));\n (* SOFT_HLUTNM = \"soft_lutpair270\" *) \n LUT5 #(\n .INIT(32'h00000100)) \n phaser_out_i_3__0\n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(calib_in_common),\n .I3(po_enstg2_f),\n .I4(\\calib_zero_inputs_reg[1]_0 [1]),\n .O(\\po_counter_read_val_reg[8] ));\n (* SOFT_HLUTNM = \"soft_lutpair272\" *) \n LUT5 #(\n .INIT(32'h00000400)) \n phaser_out_i_3__1\n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(calib_in_common),\n .I3(po_enstg2_f),\n .I4(\\calib_zero_inputs_reg[1]_0 [1]),\n .O(\\po_counter_read_val_reg[8]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair272\" *) \n LUT5 #(\n .INIT(32'h00000400)) \n phaser_out_i_3__2\n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(calib_in_common),\n .I3(po_enstg2_f),\n .I4(\\calib_zero_inputs_reg[1]_0 [1]),\n .O(\\po_counter_read_val_reg[8]_3 ));\n LUT5 #(\n .INIT(32'h0000AAA8)) \n phaser_out_i_3__3\n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .I1(ck_po_stg2_f_indec),\n .I2(dqs_po_stg2_f_incdec),\n .I3(po_stg23_incdec),\n .I4(\\calib_zero_inputs_reg[1]_0 [0]),\n .O(\\po_counter_read_val_reg[8]_5 ));\n LUT5 #(\n .INIT(32'h0000AAA8)) \n phaser_out_i_3__4\n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .I1(ck_po_stg2_f_indec),\n .I2(dqs_po_stg2_f_incdec),\n .I3(po_stg23_incdec),\n .I4(\\calib_zero_inputs_reg[1]_0 [0]),\n .O(\\po_counter_read_val_reg[8]_7 ));\n LUT5 #(\n .INIT(32'h0000AAA8)) \n phaser_out_i_3__5\n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_2 ),\n .I1(ck_po_stg2_f_indec),\n .I2(dqs_po_stg2_f_incdec),\n .I3(po_stg23_incdec),\n .I4(\\calib_zero_inputs_reg[1]_0 [0]),\n .O(\\po_counter_read_val_reg[8]_9 ));\n LUT5 #(\n .INIT(32'h0000AAA8)) \n phaser_out_i_3__6\n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_3 ),\n .I1(ck_po_stg2_f_indec),\n .I2(dqs_po_stg2_f_incdec),\n .I3(po_stg23_incdec),\n .I4(\\calib_zero_inputs_reg[1]_0 [0]),\n .O(\\po_counter_read_val_reg[8]_11 ));\n (* SOFT_HLUTNM = \"soft_lutpair265\" *) \n LUT5 #(\n .INIT(32'h00000800)) \n phaser_out_i_4\n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(calib_in_common),\n .I3(po_stg2_fincdec),\n .I4(\\calib_zero_inputs_reg[1]_0 [1]),\n .O(D_po_fine_inc113_out));\n (* SOFT_HLUTNM = \"soft_lutpair268\" *) \n LUT5 #(\n .INIT(32'h00000100)) \n phaser_out_i_4__0\n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(calib_in_common),\n .I3(po_stg2_fincdec),\n .I4(\\calib_zero_inputs_reg[1]_0 [1]),\n .O(\\po_counter_read_val_reg[8]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair268\" *) \n LUT5 #(\n .INIT(32'h00000400)) \n phaser_out_i_4__1\n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(calib_in_common),\n .I3(po_stg2_fincdec),\n .I4(\\calib_zero_inputs_reg[1]_0 [1]),\n .O(\\po_counter_read_val_reg[8]_2 ));\n (* SOFT_HLUTNM = \"soft_lutpair265\" *) \n LUT5 #(\n .INIT(32'h00000400)) \n phaser_out_i_4__2\n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(calib_in_common),\n .I3(po_stg2_fincdec),\n .I4(\\calib_zero_inputs_reg[1]_0 [1]),\n .O(\\po_counter_read_val_reg[8]_4 ));\n LUT6 #(\n .INIT(64'h8000FFFF80000000)) \n \\pi_dqs_found_all_bank[0]_i_1 \n (.I0(pi_dqs_found_lanes_r3[2]),\n .I1(pi_dqs_found_lanes_r3[3]),\n .I2(pi_dqs_found_lanes_r3[1]),\n .I3(pi_dqs_found_lanes_r3[0]),\n .I4(pi_dqs_found_start_reg),\n .I5(pi_dqs_found_all_bank),\n .O(\\pi_dqs_found_all_bank[0]_i_1_n_0 ));\n FDRE \\pi_dqs_found_all_bank_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_all_bank),\n .Q(rank_done_r_reg_0[0]),\n .R(1'b0));\n FDRE \\pi_dqs_found_all_bank_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\pi_dqs_found_all_bank_r_reg[1]_0 ),\n .Q(rank_done_r_reg_0[1]),\n .R(1'b0));\n FDRE \\pi_dqs_found_all_bank_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\pi_dqs_found_all_bank[0]_i_1_n_0 ),\n .Q(pi_dqs_found_all_bank),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE \\pi_dqs_found_all_bank_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_start_reg_0),\n .Q(\\pi_dqs_found_all_bank_r_reg[1]_0 ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE \\pi_dqs_found_any_bank_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_any_bank),\n .Q(\\pi_dqs_found_any_bank_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\pi_dqs_found_any_bank_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\pi_dqs_found_lanes_r3_reg[3]_0 ),\n .Q(pi_dqs_found_any_bank),\n .R(rstdiv0_sync_r1_reg_rep__12));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\pi_dqs_found_lanes_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(in0[0]),\n .Q(pi_dqs_found_lanes_r1[0]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\pi_dqs_found_lanes_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(in0[1]),\n .Q(pi_dqs_found_lanes_r1[1]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\pi_dqs_found_lanes_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(in0[2]),\n .Q(pi_dqs_found_lanes_r1[2]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\pi_dqs_found_lanes_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(in0[3]),\n .Q(pi_dqs_found_lanes_r1[3]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\pi_dqs_found_lanes_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(n_0_3),\n .Q(pi_dqs_found_lanes_r1[4]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\pi_dqs_found_lanes_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(n_0_2),\n .Q(pi_dqs_found_lanes_r1[5]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\pi_dqs_found_lanes_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(n_0_1),\n .Q(pi_dqs_found_lanes_r1[6]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\pi_dqs_found_lanes_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(n_0_0),\n .Q(pi_dqs_found_lanes_r1[7]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\pi_dqs_found_lanes_r2_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_lanes_r1[0]),\n .Q(pi_dqs_found_lanes_r2[0]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\pi_dqs_found_lanes_r2_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_lanes_r1[1]),\n .Q(pi_dqs_found_lanes_r2[1]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\pi_dqs_found_lanes_r2_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_lanes_r1[2]),\n .Q(pi_dqs_found_lanes_r2[2]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\pi_dqs_found_lanes_r2_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_lanes_r1[3]),\n .Q(pi_dqs_found_lanes_r2[3]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\pi_dqs_found_lanes_r2_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_lanes_r1[4]),\n .Q(pi_dqs_found_lanes_r2[4]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\pi_dqs_found_lanes_r2_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_lanes_r1[5]),\n .Q(pi_dqs_found_lanes_r2[5]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\pi_dqs_found_lanes_r2_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_lanes_r1[6]),\n .Q(pi_dqs_found_lanes_r2[6]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\pi_dqs_found_lanes_r2_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_lanes_r1[7]),\n .Q(pi_dqs_found_lanes_r2[7]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\pi_dqs_found_lanes_r3_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_lanes_r2[0]),\n .Q(pi_dqs_found_lanes_r3[0]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\pi_dqs_found_lanes_r3_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_lanes_r2[1]),\n .Q(pi_dqs_found_lanes_r3[1]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\pi_dqs_found_lanes_r3_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_lanes_r2[2]),\n .Q(pi_dqs_found_lanes_r3[2]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\pi_dqs_found_lanes_r3_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_lanes_r2[3]),\n .Q(pi_dqs_found_lanes_r3[3]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\pi_dqs_found_lanes_r3_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_lanes_r2[4]),\n .Q(pi_dqs_found_lanes_r3[4]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\pi_dqs_found_lanes_r3_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_lanes_r2[5]),\n .Q(pi_dqs_found_lanes_r3[5]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\pi_dqs_found_lanes_r3_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_lanes_r2[6]),\n .Q(pi_dqs_found_lanes_r3[6]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\pi_dqs_found_lanes_r3_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_lanes_r2[7]),\n .Q(pi_dqs_found_lanes_r3[7]),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair304\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\pi_rst_stg1_cal[0]_i_1 \n (.I0(\\pi_rst_stg1_cal_r_reg[0]_1 ),\n .I1(rst_dqs_find_r1_reg_0),\n .O(\\pi_rst_stg1_cal[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair304\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\pi_rst_stg1_cal[1]_i_1 \n (.I0(p_1_in50_in),\n .I1(rst_dqs_find_r1_reg_0),\n .O(\\pi_rst_stg1_cal[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h1111111010101010)) \n \\pi_rst_stg1_cal_r1[0]_i_1 \n (.I0(\\pi_rst_stg1_cal_r_reg[0]_0 ),\n .I1(rstdiv0_sync_r1_reg_rep__24),\n .I2(\\pi_rst_stg1_cal_r_reg[0]_1 ),\n .I3(\\pi_dqs_found_any_bank_r_reg_n_0_[0] ),\n .I4(pi_dqs_found_all_bank),\n .I5(\\pi_rst_stg1_cal_r1_reg_n_0_[0] ),\n .O(pi_rst_stg1_cal_r1_reg017_out));\n LUT5 #(\n .INIT(32'h11101010)) \n \\pi_rst_stg1_cal_r1[1]_i_1 \n (.I0(\\pi_rst_stg1_cal_r_reg[0]_0 ),\n .I1(rstdiv0_sync_r1_reg_rep__24),\n .I2(p_1_in50_in),\n .I3(p_0_in19_in),\n .I4(\\pi_dqs_found_all_bank_r_reg[1]_0 ),\n .O(pi_rst_stg1_cal_r1_reg0));\n FDRE \\pi_rst_stg1_cal_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_rst_stg1_cal_r1_reg017_out),\n .Q(\\pi_rst_stg1_cal_r1_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\pi_rst_stg1_cal_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_rst_stg1_cal_r1_reg0),\n .Q(p_0_in19_in),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000000000FE)) \n \\pi_rst_stg1_cal_r[0]_i_1 \n (.I0(\\pi_rst_stg1_cal_r_reg[0]_1 ),\n .I1(\\pi_rst_stg1_cal_r[0]_i_2_n_0 ),\n .I2(\\pi_rst_stg1_cal_r[0]_i_3_n_0 ),\n .I3(rstdiv0_sync_r1_reg_rep__24),\n .I4(\\pi_rst_stg1_cal_r_reg[0]_0 ),\n .I5(\\pi_rst_stg1_cal_r1_reg_n_0_[0] ),\n .O(\\pi_rst_stg1_cal_r[0]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h0007)) \n \\pi_rst_stg1_cal_r[0]_i_2 \n (.I0(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [1]),\n .I1(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [0]),\n .I2(\\rd_byte_data_offset_reg_n_0_[0][5] ),\n .I3(\\rd_byte_data_offset_reg_n_0_[0][4] ),\n .O(\\pi_rst_stg1_cal_r[0]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair292\" *) \n LUT4 #(\n .INIT(16'h4F44)) \n \\pi_rst_stg1_cal_r[0]_i_3 \n (.I0(dqs_found_start_r),\n .I1(pi_dqs_found_start_reg),\n .I2(pi_dqs_found_all_bank),\n .I3(\\pi_dqs_found_any_bank_r_reg_n_0_[0] ),\n .O(\\pi_rst_stg1_cal_r[0]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h00000000EFEE0000)) \n \\pi_rst_stg1_cal_r[1]_i_1 \n (.I0(p_1_in50_in),\n .I1(\\pi_rst_stg1_cal_r[1]_i_2_n_0 ),\n .I2(dqs_found_start_r),\n .I3(pi_dqs_found_start_reg),\n .I4(fine_adjust_reg_0),\n .I5(p_0_in19_in),\n .O(\\pi_rst_stg1_cal_r[1]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h0007)) \n \\pi_rst_stg1_cal_r[1]_i_2 \n (.I0(\\rd_byte_data_offset_reg[0][9]_0 [1]),\n .I1(\\rd_byte_data_offset_reg[0][9]_0 [0]),\n .I2(p_0_in[5]),\n .I3(p_0_in[4]),\n .O(\\pi_rst_stg1_cal_r[1]_i_2_n_0 ));\n FDRE \\pi_rst_stg1_cal_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\pi_rst_stg1_cal_r[0]_i_1_n_0 ),\n .Q(\\pi_rst_stg1_cal_r_reg[0]_1 ),\n .R(1'b0));\n FDRE \\pi_rst_stg1_cal_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\pi_rst_stg1_cal_r[1]_i_1_n_0 ),\n .Q(p_1_in50_in),\n .R(1'b0));\n FDRE \\pi_rst_stg1_cal_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\pi_rst_stg1_cal[0]_i_1_n_0 ),\n .Q(rst_stg1_cal),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE \\pi_rst_stg1_cal_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\pi_rst_stg1_cal[1]_i_1_n_0 ),\n .Q(\\pi_rst_stg1_cal_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE rank_done_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_rank_done),\n .Q(rank_done_r1),\n .R(1'b0));\n FDRE rank_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\pi_dqs_found_all_bank_r_reg[1]_1 ),\n .Q(pi_dqs_found_rank_done),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h2)) \n \\rank_final_loop[0].bank_final_loop[0].final_data_offset[0][5]_i_1 \n (.I0(rd_data_offset_cal_done),\n .I1(init_dqsfound_done_r1_reg_n_0),\n .O(p_22_out));\n (* SOFT_HLUTNM = \"soft_lutpair296\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1 \n (.I0(\\rd_byte_data_offset_reg_n_0_[0][0] ),\n .O(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair295\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1 \n (.I0(\\rd_byte_data_offset_reg_n_0_[0][1] ),\n .I1(\\rd_byte_data_offset_reg_n_0_[0][0] ),\n .O(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hA9)) \n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1 \n (.I0(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [0]),\n .I1(\\rd_byte_data_offset_reg_n_0_[0][0] ),\n .I2(\\rd_byte_data_offset_reg_n_0_[0][1] ),\n .O(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair276\" *) \n LUT4 #(\n .INIT(16'hAAA9)) \n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1 \n (.I0(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [1]),\n .I1(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [0]),\n .I2(\\rd_byte_data_offset_reg_n_0_[0][1] ),\n .I3(\\rd_byte_data_offset_reg_n_0_[0][0] ),\n .O(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair276\" *) \n LUT5 #(\n .INIT(32'hAAAAAAA9)) \n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1 \n (.I0(\\rd_byte_data_offset_reg_n_0_[0][4] ),\n .I1(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [1]),\n .I2(\\rd_byte_data_offset_reg_n_0_[0][0] ),\n .I3(\\rd_byte_data_offset_reg_n_0_[0][1] ),\n .I4(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [0]),\n .O(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h04)) \n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_1 \n (.I0(init_dqsfound_done_r1_reg_n_0),\n .I1(rd_data_offset_cal_done),\n .I2(rstdiv0_sync_r1_reg_rep__24),\n .O(final_data_offset_mc));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAAAAA9)) \n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2 \n (.I0(\\rd_byte_data_offset_reg_n_0_[0][5] ),\n .I1(\\rd_byte_data_offset_reg_n_0_[0][4] ),\n .I2(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [0]),\n .I3(\\rd_byte_data_offset_reg_n_0_[0][1] ),\n .I4(\\rd_byte_data_offset_reg_n_0_[0][0] ),\n .I5(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [1]),\n .O(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2_n_0 ));\n FDRE \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] \n (.C(CLK),\n .CE(final_data_offset_mc),\n .D(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0 ),\n .Q(\\cmd_pipe_plus.mc_data_offset_reg[5] [0]),\n .R(1'b0));\n FDRE \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][1] \n (.C(CLK),\n .CE(final_data_offset_mc),\n .D(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1_n_0 ),\n .Q(\\cmd_pipe_plus.mc_data_offset_reg[5] [1]),\n .R(1'b0));\n FDRE \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][2] \n (.C(CLK),\n .CE(final_data_offset_mc),\n .D(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1_n_0 ),\n .Q(\\cmd_pipe_plus.mc_data_offset_reg[5] [2]),\n .R(1'b0));\n FDRE \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][3] \n (.C(CLK),\n .CE(final_data_offset_mc),\n .D(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1_n_0 ),\n .Q(\\cmd_pipe_plus.mc_data_offset_reg[5] [3]),\n .R(1'b0));\n FDRE \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4] \n (.C(CLK),\n .CE(final_data_offset_mc),\n .D(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1_n_0 ),\n .Q(\\cmd_pipe_plus.mc_data_offset_reg[5] [4]),\n .R(1'b0));\n FDRE \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] \n (.C(CLK),\n .CE(final_data_offset_mc),\n .D(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2_n_0 ),\n .Q(\\cmd_pipe_plus.mc_data_offset_reg[5] [5]),\n .R(1'b0));\n FDRE \\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][0] \n (.C(CLK),\n .CE(p_22_out),\n .D(\\rd_byte_data_offset_reg_n_0_[0][0] ),\n .Q(rd_data_offset_ranks_0[0]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE \\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][1] \n (.C(CLK),\n .CE(p_22_out),\n .D(\\rd_byte_data_offset_reg_n_0_[0][1] ),\n .Q(rd_data_offset_ranks_0[1]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE \\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][2] \n (.C(CLK),\n .CE(p_22_out),\n .D(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [0]),\n .Q(\\rank_final_loop[0].final_do_max_reg[0][3]_0 [0]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE \\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3] \n (.C(CLK),\n .CE(p_22_out),\n .D(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [1]),\n .Q(\\rank_final_loop[0].final_do_max_reg[0][3]_0 [1]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE \\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][4] \n (.C(CLK),\n .CE(p_22_out),\n .D(\\rd_byte_data_offset_reg_n_0_[0][4] ),\n .Q(rd_data_offset_ranks_0[4]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE \\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][5] \n (.C(CLK),\n .CE(p_22_out),\n .D(\\rd_byte_data_offset_reg_n_0_[0][5] ),\n .Q(rd_data_offset_ranks_0[5]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n LUT3 #(\n .INIT(8'h8A)) \n \\rank_final_loop[0].bank_final_loop[1].final_data_offset[0][11]_i_1 \n (.I0(init_dqsfound_done_r5),\n .I1(init_dqsfound_done_r1_reg_n_0),\n .I2(rd_data_offset_cal_done),\n .O(final_data_offset));\n LUT4 #(\n .INIT(16'h00D0)) \n \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1 \n (.I0(rd_data_offset_cal_done),\n .I1(init_dqsfound_done_r1_reg_n_0),\n .I2(init_dqsfound_done_r5),\n .I3(rstdiv0_sync_r1_reg_rep__24),\n .O(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ));\n FDRE \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10] \n (.C(CLK),\n .CE(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ),\n .D(\\rank_final_loop[0].final_do_max_reg[0]__0 [4]),\n .Q(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [4]),\n .R(1'b0));\n FDRE \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] \n (.C(CLK),\n .CE(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ),\n .D(\\rank_final_loop[0].final_do_max_reg[0]__0 [5]),\n .Q(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [5]),\n .R(1'b0));\n FDRE \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] \n (.C(CLK),\n .CE(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ),\n .D(\\rank_final_loop[0].final_do_max_reg[0]__0 [0]),\n .Q(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [0]),\n .R(1'b0));\n FDRE \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][7] \n (.C(CLK),\n .CE(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ),\n .D(\\rank_final_loop[0].final_do_max_reg[0]__0 [1]),\n .Q(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [1]),\n .R(1'b0));\n FDRE \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][8] \n (.C(CLK),\n .CE(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ),\n .D(\\rank_final_loop[0].final_do_max_reg[0]__0 [2]),\n .Q(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [2]),\n .R(1'b0));\n FDRE \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][9] \n (.C(CLK),\n .CE(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ),\n .D(\\rank_final_loop[0].final_do_max_reg[0]__0 [3]),\n .Q(\\cmd_pipe_plus.mc_data_offset_1_reg[5] [3]),\n .R(1'b0));\n FDRE \\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][10] \n (.C(CLK),\n .CE(final_data_offset),\n .D(\\rank_final_loop[0].final_do_max_reg[0]__0 [4]),\n .Q(rd_data_offset_ranks_1[4]),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE \\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][11] \n (.C(CLK),\n .CE(final_data_offset),\n .D(\\rank_final_loop[0].final_do_max_reg[0]__0 [5]),\n .Q(rd_data_offset_ranks_1[5]),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE \\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][6] \n (.C(CLK),\n .CE(final_data_offset),\n .D(\\rank_final_loop[0].final_do_max_reg[0]__0 [0]),\n .Q(rd_data_offset_ranks_1[0]),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE \\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][7] \n (.C(CLK),\n .CE(final_data_offset),\n .D(\\rank_final_loop[0].final_do_max_reg[0]__0 [1]),\n .Q(rd_data_offset_ranks_1[1]),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE \\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][8] \n (.C(CLK),\n .CE(final_data_offset),\n .D(\\rank_final_loop[0].final_do_max_reg[0]__0 [2]),\n .Q(\\rank_final_loop[0].final_do_max_reg[0][3]_1 [0]),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE \\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] \n (.C(CLK),\n .CE(final_data_offset),\n .D(\\rank_final_loop[0].final_do_max_reg[0]__0 [3]),\n .Q(\\rank_final_loop[0].final_do_max_reg[0][3]_1 [1]),\n .R(rstdiv0_sync_r1_reg_rep__13));\n LUT1 #(\n .INIT(2'h1)) \n \\rank_final_loop[0].final_do_index[0][0]_i_1 \n (.I0(\\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),\n .O(\\rank_final_loop[0].final_do_index[0][0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair285\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\rank_final_loop[0].final_do_index[0][1]_i_1 \n (.I0(\\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),\n .I1(\\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ),\n .O(\\rank_final_loop[0].final_do_index[0][1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair264\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\rank_final_loop[0].final_do_index[0][2]_i_1 \n (.I0(\\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ),\n .I1(\\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ),\n .I2(\\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),\n .O(\\rank_final_loop[0].final_do_index[0][2]_i_1_n_0 ));\n FDRE \\rank_final_loop[0].final_do_index_reg[0][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rank_final_loop[0].final_do_index[0][0]_i_1_n_0 ),\n .Q(\\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE \\rank_final_loop[0].final_do_index_reg[0][1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rank_final_loop[0].final_do_index[0][1]_i_1_n_0 ),\n .Q(\\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE \\rank_final_loop[0].final_do_index_reg[0][2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rank_final_loop[0].final_do_index[0][2]_i_1_n_0 ),\n .Q(\\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n (* SOFT_HLUTNM = \"soft_lutpair274\" *) \n LUT5 #(\n .INIT(32'hEFEEEFFF)) \n \\rank_final_loop[0].final_do_max[0][0]_i_1 \n (.I0(\\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ),\n .I1(\\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ),\n .I2(rd_data_offset_ranks_1[0]),\n .I3(\\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),\n .I4(rd_data_offset_ranks_0[0]),\n .O(\\rank_final_loop[0].final_do_max[0][0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFAF5FCFCFAF5F3F3)) \n \\rank_final_loop[0].final_do_max[0][1]_i_1 \n (.I0(rd_data_offset_ranks_1[1]),\n .I1(rd_data_offset_ranks_0[1]),\n .I2(\\rank_final_loop[0].final_do_max[0][5]_i_5_n_0 ),\n .I3(rd_data_offset_ranks_1[0]),\n .I4(\\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),\n .I5(rd_data_offset_ranks_0[0]),\n .O(\\rank_final_loop[0].final_do_max[0][1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h555555555555A959)) \n \\rank_final_loop[0].final_do_max[0][2]_i_1 \n (.I0(\\rank_final_loop[0].final_do_max[0][2]_i_2_n_0 ),\n .I1(\\rank_final_loop[0].final_do_max_reg[0][3]_0 [0]),\n .I2(\\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),\n .I3(\\rank_final_loop[0].final_do_max_reg[0][3]_1 [0]),\n .I4(\\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ),\n .I5(\\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ),\n .O(\\rank_final_loop[0].final_do_max[0][2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FAFFFACC)) \n \\rank_final_loop[0].final_do_max[0][2]_i_2 \n (.I0(rd_data_offset_ranks_1[0]),\n .I1(rd_data_offset_ranks_0[0]),\n .I2(rd_data_offset_ranks_1[1]),\n .I3(\\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),\n .I4(rd_data_offset_ranks_0[1]),\n .I5(\\rank_final_loop[0].final_do_max[0][5]_i_5_n_0 ),\n .O(\\rank_final_loop[0].final_do_max[0][2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h555555555555A959)) \n \\rank_final_loop[0].final_do_max[0][3]_i_1 \n (.I0(\\rank_final_loop[0].final_do_max[0][3]_i_2_n_0 ),\n .I1(\\rank_final_loop[0].final_do_max_reg[0][3]_0 [1]),\n .I2(\\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),\n .I3(\\rank_final_loop[0].final_do_max_reg[0][3]_1 [1]),\n .I4(\\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ),\n .I5(\\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ),\n .O(\\rank_final_loop[0].final_do_max[0][3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF10111000)) \n \\rank_final_loop[0].final_do_max[0][3]_i_2 \n (.I0(\\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ),\n .I1(\\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ),\n .I2(\\rank_final_loop[0].final_do_max_reg[0][3]_1 [0]),\n .I3(\\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),\n .I4(\\rank_final_loop[0].final_do_max_reg[0][3]_0 [0]),\n .I5(\\rank_final_loop[0].final_do_max[0][2]_i_2_n_0 ),\n .O(\\rank_final_loop[0].final_do_max[0][3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hEFEEEFFF10111000)) \n \\rank_final_loop[0].final_do_max[0][4]_i_1 \n (.I0(\\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ),\n .I1(\\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ),\n .I2(rd_data_offset_ranks_1[4]),\n .I3(\\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),\n .I4(rd_data_offset_ranks_0[4]),\n .I5(\\rank_final_loop[0].final_do_max[0][5]_i_7_n_0 ),\n .O(\\rank_final_loop[0].final_do_max[0][4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FFFF4F44)) \n \\rank_final_loop[0].final_do_max[0][5]_i_1 \n (.I0(\\rank_final_loop[0].final_do_max_reg[0]__0 [5]),\n .I1(rd_data_offset_ranks_0[5]),\n .I2(\\rank_final_loop[0].final_do_max_reg[0]__0 [4]),\n .I3(rd_data_offset_ranks_0[4]),\n .I4(\\rank_final_loop[0].final_do_max[0][5]_i_3_n_0 ),\n .I5(\\rank_final_loop[0].final_do_max[0][5]_i_4_n_0 ),\n .O(\\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h4540BABF45404540)) \n \\rank_final_loop[0].final_do_max[0][5]_i_2 \n (.I0(\\rank_final_loop[0].final_do_max[0][5]_i_5_n_0 ),\n .I1(rd_data_offset_ranks_1[5]),\n .I2(\\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),\n .I3(rd_data_offset_ranks_0[5]),\n .I4(\\rank_final_loop[0].final_do_max[0][5]_i_6_n_0 ),\n .I5(\\rank_final_loop[0].final_do_max[0][5]_i_7_n_0 ),\n .O(\\rank_final_loop[0].final_do_max[0][5]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FFFF4F44)) \n \\rank_final_loop[0].final_do_max[0][5]_i_3 \n (.I0(\\rank_final_loop[0].final_do_max_reg[0]__0 [3]),\n .I1(\\rank_final_loop[0].final_do_max_reg[0][3]_0 [1]),\n .I2(\\rank_final_loop[0].final_do_max_reg[0]__0 [2]),\n .I3(\\rank_final_loop[0].final_do_max_reg[0][3]_0 [0]),\n .I4(\\rank_final_loop[0].final_do_max[0][5]_i_8_n_0 ),\n .I5(\\rank_final_loop[0].final_do_max[0][5]_i_9_n_0 ),\n .O(\\rank_final_loop[0].final_do_max[0][5]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair264\" *) \n LUT5 #(\n .INIT(32'hFFFFFFF4)) \n \\rank_final_loop[0].final_do_max[0][5]_i_4 \n (.I0(rd_data_offset_ranks_0[5]),\n .I1(\\rank_final_loop[0].final_do_max_reg[0]__0 [5]),\n .I2(\\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),\n .I3(\\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ),\n .I4(\\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ),\n .O(\\rank_final_loop[0].final_do_max[0][5]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair274\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\rank_final_loop[0].final_do_max[0][5]_i_5 \n (.I0(\\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ),\n .I1(\\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ),\n .O(\\rank_final_loop[0].final_do_max[0][5]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair285\" *) \n LUT5 #(\n .INIT(32'h000000E2)) \n \\rank_final_loop[0].final_do_max[0][5]_i_6 \n (.I0(rd_data_offset_ranks_0[4]),\n .I1(\\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),\n .I2(rd_data_offset_ranks_1[4]),\n .I3(\\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ),\n .I4(\\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ),\n .O(\\rank_final_loop[0].final_do_max[0][5]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h00000000EFEEEFFF)) \n \\rank_final_loop[0].final_do_max[0][5]_i_7 \n (.I0(\\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ),\n .I1(\\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ),\n .I2(\\rank_final_loop[0].final_do_max_reg[0][3]_1 [1]),\n .I3(\\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),\n .I4(\\rank_final_loop[0].final_do_max_reg[0][3]_0 [1]),\n .I5(\\rank_final_loop[0].final_do_max[0][3]_i_2_n_0 ),\n .O(\\rank_final_loop[0].final_do_max[0][5]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h40F4000040F440F4)) \n \\rank_final_loop[0].final_do_max[0][5]_i_8 \n (.I0(\\rank_final_loop[0].final_do_max_reg[0]__0 [0]),\n .I1(rd_data_offset_ranks_0[0]),\n .I2(rd_data_offset_ranks_0[1]),\n .I3(\\rank_final_loop[0].final_do_max_reg[0]__0 [1]),\n .I4(\\rank_final_loop[0].final_do_max_reg[0][3]_0 [0]),\n .I5(\\rank_final_loop[0].final_do_max_reg[0]__0 [2]),\n .O(\\rank_final_loop[0].final_do_max[0][5]_i_8_n_0 ));\n LUT4 #(\n .INIT(16'h4F44)) \n \\rank_final_loop[0].final_do_max[0][5]_i_9 \n (.I0(\\rank_final_loop[0].final_do_max_reg[0][3]_0 [1]),\n .I1(\\rank_final_loop[0].final_do_max_reg[0]__0 [3]),\n .I2(rd_data_offset_ranks_0[4]),\n .I3(\\rank_final_loop[0].final_do_max_reg[0]__0 [4]),\n .O(\\rank_final_loop[0].final_do_max[0][5]_i_9_n_0 ));\n FDRE \\rank_final_loop[0].final_do_max_reg[0][0] \n (.C(CLK),\n .CE(\\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ),\n .D(\\rank_final_loop[0].final_do_max[0][0]_i_1_n_0 ),\n .Q(\\rank_final_loop[0].final_do_max_reg[0]__0 [0]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE \\rank_final_loop[0].final_do_max_reg[0][1] \n (.C(CLK),\n .CE(\\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ),\n .D(\\rank_final_loop[0].final_do_max[0][1]_i_1_n_0 ),\n .Q(\\rank_final_loop[0].final_do_max_reg[0]__0 [1]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE \\rank_final_loop[0].final_do_max_reg[0][2] \n (.C(CLK),\n .CE(\\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ),\n .D(\\rank_final_loop[0].final_do_max[0][2]_i_1_n_0 ),\n .Q(\\rank_final_loop[0].final_do_max_reg[0]__0 [2]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE \\rank_final_loop[0].final_do_max_reg[0][3] \n (.C(CLK),\n .CE(\\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ),\n .D(\\rank_final_loop[0].final_do_max[0][3]_i_1_n_0 ),\n .Q(\\rank_final_loop[0].final_do_max_reg[0]__0 [3]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE \\rank_final_loop[0].final_do_max_reg[0][4] \n (.C(CLK),\n .CE(\\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ),\n .D(\\rank_final_loop[0].final_do_max[0][4]_i_1_n_0 ),\n .Q(\\rank_final_loop[0].final_do_max_reg[0]__0 [4]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE \\rank_final_loop[0].final_do_max_reg[0][5] \n (.C(CLK),\n .CE(\\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ),\n .D(\\rank_final_loop[0].final_do_max[0][5]_i_2_n_0 ),\n .Q(\\rank_final_loop[0].final_do_max_reg[0]__0 [5]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n (* SOFT_HLUTNM = \"soft_lutpair279\" *) \n LUT5 #(\n .INIT(32'hAAAAAAA9)) \n \\rd_byte_data_offset[0][10]_i_1 \n (.I0(p_0_in[4]),\n .I1(\\rd_byte_data_offset_reg[0][9]_0 [1]),\n .I2(p_0_in[1]),\n .I3(p_0_in[0]),\n .I4(\\rd_byte_data_offset_reg[0][9]_0 [0]),\n .O(p_1_in[4]));\n LUT4 #(\n .INIT(16'hAAAB)) \n \\rd_byte_data_offset[0][11]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__24),\n .I1(\\rd_byte_data_offset[0][11]_i_4_n_0 ),\n .I2(\\rnk_cnt_r_reg_n_0_[1] ),\n .I3(\\rnk_cnt_r_reg_n_0_[0] ),\n .O(\\rd_byte_data_offset[0][11]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000080000000000)) \n \\rd_byte_data_offset[0][11]_i_2 \n (.I0(\\rd_byte_data_offset[0][5]_i_4_n_0 ),\n .I1(\\rd_byte_data_offset_reg[0]_3 ),\n .I2(\\pi_rst_stg1_cal_r_reg[0]_0 ),\n .I3(dqs_found_start_r),\n .I4(\\pi_dqs_found_all_bank_r_reg[1]_0 ),\n .I5(\\rd_byte_data_offset[0][11]_i_4_n_0 ),\n .O(\\rd_byte_data_offset[0][11]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAAAAA9)) \n \\rd_byte_data_offset[0][11]_i_3 \n (.I0(p_0_in[5]),\n .I1(p_0_in[4]),\n .I2(\\rd_byte_data_offset_reg[0][9]_0 [0]),\n .I3(p_0_in[0]),\n .I4(p_0_in[1]),\n .I5(\\rd_byte_data_offset_reg[0][9]_0 [1]),\n .O(p_1_in[5]));\n LUT6 #(\n .INIT(64'hBBBBBBB0BBB0BBB0)) \n \\rd_byte_data_offset[0][11]_i_4 \n (.I0(rd_data_offset_cal_done),\n .I1(rank_done_r1),\n .I2(p_0_in[4]),\n .I3(p_0_in[5]),\n .I4(\\rd_byte_data_offset_reg[0][9]_0 [0]),\n .I5(\\rd_byte_data_offset_reg[0][9]_0 [1]),\n .O(\\rd_byte_data_offset[0][11]_i_4_n_0 ));\n LUT4 #(\n .INIT(16'hAAAB)) \n \\rd_byte_data_offset[0][5]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__24),\n .I1(\\rd_byte_data_offset[0][5]_i_3_n_0 ),\n .I2(\\rnk_cnt_r_reg_n_0_[1] ),\n .I3(\\rnk_cnt_r_reg_n_0_[0] ),\n .O(\\rd_byte_data_offset[0][5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000080000000000)) \n \\rd_byte_data_offset[0][5]_i_2 \n (.I0(\\rd_byte_data_offset[0][5]_i_4_n_0 ),\n .I1(\\rd_byte_data_offset_reg[0]_3 ),\n .I2(\\pi_rst_stg1_cal_r_reg[0]_0 ),\n .I3(dqs_found_start_r),\n .I4(pi_dqs_found_all_bank),\n .I5(\\rd_byte_data_offset[0][5]_i_3_n_0 ),\n .O(rd_byte_data_offset));\n LUT6 #(\n .INIT(64'hFEEE0000FEEEFEEE)) \n \\rd_byte_data_offset[0][5]_i_3 \n (.I0(\\rd_byte_data_offset_reg_n_0_[0][4] ),\n .I1(\\rd_byte_data_offset_reg_n_0_[0][5] ),\n .I2(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [0]),\n .I3(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [1]),\n .I4(rd_data_offset_cal_done),\n .I5(rank_done_r1),\n .O(\\rd_byte_data_offset[0][5]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000001000)) \n \\rd_byte_data_offset[0][5]_i_4 \n (.I0(detect_rd_cnt_reg__0[3]),\n .I1(detect_rd_cnt_reg__0[2]),\n .I2(detect_pi_found_dqs),\n .I3(detect_rd_cnt_reg__0[0]),\n .I4(detect_rd_cnt_reg__0[1]),\n .I5(rd_data_offset_cal_done),\n .O(\\rd_byte_data_offset[0][5]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair298\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\rd_byte_data_offset[0][6]_i_1 \n (.I0(p_0_in[0]),\n .O(p_1_in[0]));\n (* SOFT_HLUTNM = \"soft_lutpair294\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\rd_byte_data_offset[0][7]_i_1 \n (.I0(p_0_in[0]),\n .I1(p_0_in[1]),\n .O(\\rd_byte_data_offset[0][7]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hA9)) \n \\rd_byte_data_offset[0][8]_i_1 \n (.I0(\\rd_byte_data_offset_reg[0][9]_0 [0]),\n .I1(p_0_in[1]),\n .I2(p_0_in[0]),\n .O(p_1_in[2]));\n (* SOFT_HLUTNM = \"soft_lutpair279\" *) \n LUT4 #(\n .INIT(16'hAAA9)) \n \\rd_byte_data_offset[0][9]_i_1 \n (.I0(\\rd_byte_data_offset_reg[0][9]_0 [1]),\n .I1(\\rd_byte_data_offset_reg[0][9]_0 [0]),\n .I2(p_0_in[0]),\n .I3(p_0_in[1]),\n .O(p_1_in[3]));\n FDRE \\rd_byte_data_offset_reg[0][0] \n (.C(CLK),\n .CE(rd_byte_data_offset),\n .D(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0 ),\n .Q(\\rd_byte_data_offset_reg_n_0_[0][0] ),\n .R(\\rd_byte_data_offset[0][5]_i_1_n_0 ));\n FDSE \\rd_byte_data_offset_reg[0][10] \n (.C(CLK),\n .CE(\\rd_byte_data_offset[0][11]_i_2_n_0 ),\n .D(p_1_in[4]),\n .Q(p_0_in[4]),\n .S(\\rd_byte_data_offset[0][11]_i_1_n_0 ));\n FDRE \\rd_byte_data_offset_reg[0][11] \n (.C(CLK),\n .CE(\\rd_byte_data_offset[0][11]_i_2_n_0 ),\n .D(p_1_in[5]),\n .Q(p_0_in[5]),\n .R(\\rd_byte_data_offset[0][11]_i_1_n_0 ));\n FDSE \\rd_byte_data_offset_reg[0][1] \n (.C(CLK),\n .CE(rd_byte_data_offset),\n .D(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1_n_0 ),\n .Q(\\rd_byte_data_offset_reg_n_0_[0][1] ),\n .S(\\rd_byte_data_offset[0][5]_i_1_n_0 ));\n FDRE \\rd_byte_data_offset_reg[0][2] \n (.C(CLK),\n .CE(rd_byte_data_offset),\n .D(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1_n_0 ),\n .Q(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [0]),\n .R(\\rd_byte_data_offset[0][5]_i_1_n_0 ));\n FDSE \\rd_byte_data_offset_reg[0][3] \n (.C(CLK),\n .CE(rd_byte_data_offset),\n .D(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1_n_0 ),\n .Q(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 [1]),\n .S(\\rd_byte_data_offset[0][5]_i_1_n_0 ));\n FDSE \\rd_byte_data_offset_reg[0][4] \n (.C(CLK),\n .CE(rd_byte_data_offset),\n .D(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1_n_0 ),\n .Q(\\rd_byte_data_offset_reg_n_0_[0][4] ),\n .S(\\rd_byte_data_offset[0][5]_i_1_n_0 ));\n FDRE \\rd_byte_data_offset_reg[0][5] \n (.C(CLK),\n .CE(rd_byte_data_offset),\n .D(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2_n_0 ),\n .Q(\\rd_byte_data_offset_reg_n_0_[0][5] ),\n .R(\\rd_byte_data_offset[0][5]_i_1_n_0 ));\n FDRE \\rd_byte_data_offset_reg[0][6] \n (.C(CLK),\n .CE(\\rd_byte_data_offset[0][11]_i_2_n_0 ),\n .D(p_1_in[0]),\n .Q(p_0_in[0]),\n .R(\\rd_byte_data_offset[0][11]_i_1_n_0 ));\n FDSE \\rd_byte_data_offset_reg[0][7] \n (.C(CLK),\n .CE(\\rd_byte_data_offset[0][11]_i_2_n_0 ),\n .D(\\rd_byte_data_offset[0][7]_i_1_n_0 ),\n .Q(p_0_in[1]),\n .S(\\rd_byte_data_offset[0][11]_i_1_n_0 ));\n FDRE \\rd_byte_data_offset_reg[0][8] \n (.C(CLK),\n .CE(\\rd_byte_data_offset[0][11]_i_2_n_0 ),\n .D(p_1_in[2]),\n .Q(\\rd_byte_data_offset_reg[0][9]_0 [0]),\n .R(\\rd_byte_data_offset[0][11]_i_1_n_0 ));\n FDSE \\rd_byte_data_offset_reg[0][9] \n (.C(CLK),\n .CE(\\rd_byte_data_offset[0][11]_i_2_n_0 ),\n .D(p_1_in[3]),\n .Q(\\rd_byte_data_offset_reg[0][9]_0 [1]),\n .S(\\rd_byte_data_offset[0][11]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair297\" *) \n LUT3 #(\n .INIT(8'hD2)) \n \\rnk_cnt_r[0]_i_1 \n (.I0(pi_dqs_found_rank_done),\n .I1(rd_data_offset_cal_done),\n .I2(\\rnk_cnt_r_reg_n_0_[0] ),\n .O(\\rnk_cnt_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair297\" *) \n LUT4 #(\n .INIT(16'hF708)) \n \\rnk_cnt_r[1]_i_1 \n (.I0(\\rnk_cnt_r_reg_n_0_[0] ),\n .I1(pi_dqs_found_rank_done),\n .I2(rd_data_offset_cal_done),\n .I3(\\rnk_cnt_r_reg_n_0_[1] ),\n .O(\\rnk_cnt_r[1]_i_1_n_0 ));\n FDRE \\rnk_cnt_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rnk_cnt_r[0]_i_1_n_0 ),\n .Q(\\rnk_cnt_r_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE \\rnk_cnt_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rnk_cnt_r[1]_i_1_n_0 ),\n .Q(\\rnk_cnt_r_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n LUT5 #(\n .INIT(32'h8800FF30)) \n rst_dqs_find_i_2\n (.I0(prech_done),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]),\n .I2(init_dqsfound_done_r5),\n .I3(rst_dqs_find_i_5_n_0),\n .I4(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .O(rst_dqs_find));\n LUT6 #(\n .INIT(64'hBB00BB0030333000)) \n rst_dqs_find_i_3\n (.I0(prech_done),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I2(rst_dqs_find_i_6_n_0),\n .I3(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .I4(p_1_in27_in),\n .I5(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .O(rst_dqs_find_reg_1));\n LUT6 #(\n .INIT(64'h0000004F00000040)) \n rst_dqs_find_i_4\n (.I0(pi_dqs_found_any_bank),\n .I1(rst_dqs_find_r2),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I3(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .I4(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .I5(init_dqsfound_done_r5),\n .O(rst_dqs_find_reg_0));\n LUT5 #(\n .INIT(32'hFFFF8A80)) \n rst_dqs_find_i_5\n (.I0(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .I1(\\first_fail_taps[5]_i_4_n_0 ),\n .I2(fine_adj_state_r144_out),\n .I3(first_fail_detect_i_2_n_0),\n .I4(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .O(rst_dqs_find_i_5_n_0));\n LUT6 #(\n .INIT(64'h40F0F0F040000000)) \n rst_dqs_find_i_6\n (.I0(fine_adj_state_r16_out),\n .I1(first_fail_detect_i_2_n_0),\n .I2(detect_pi_found_dqs),\n .I3(\\pi_dqs_found_all_bank_r_reg[1]_0 ),\n .I4(pi_dqs_found_all_bank),\n .I5(\\dec_cnt[5]_i_10_n_0 ),\n .O(rst_dqs_find_i_6_n_0));\n FDRE rst_dqs_find_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rst_dqs_find_r1_reg_0),\n .Q(rst_dqs_find_r1),\n .R(1'b0));\n FDRE rst_dqs_find_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rst_dqs_find_r1),\n .Q(rst_dqs_find_r2),\n .R(1'b0));\n FDRE rst_dqs_find_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_fine_adj_state_r_reg[1]_0 ),\n .Q(rst_dqs_find_r1_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__12));\n (* SOFT_HLUTNM = \"soft_lutpair277\" *) \n LUT4 #(\n .INIT(16'h4055)) \n \\stable_pass_cnt[0]_i_1 \n (.I0(\\stable_pass_cnt_reg_n_0_[0] ),\n .I1(pi_dqs_found_all_bank),\n .I2(\\pi_dqs_found_all_bank_r_reg[1]_0 ),\n .I3(detect_pi_found_dqs),\n .O(p_0_in__1[0]));\n (* SOFT_HLUTNM = \"soft_lutpair277\" *) \n LUT5 #(\n .INIT(32'h60006666)) \n \\stable_pass_cnt[1]_i_1 \n (.I0(stable_pass_cnt_reg__0[1]),\n .I1(\\stable_pass_cnt_reg_n_0_[0] ),\n .I2(pi_dqs_found_all_bank),\n .I3(\\pi_dqs_found_all_bank_r_reg[1]_0 ),\n .I4(detect_pi_found_dqs),\n .O(p_0_in__1[1]));\n LUT6 #(\n .INIT(64'h7800000078787878)) \n \\stable_pass_cnt[2]_i_1 \n (.I0(\\stable_pass_cnt_reg_n_0_[0] ),\n .I1(stable_pass_cnt_reg__0[1]),\n .I2(stable_pass_cnt_reg__0[2]),\n .I3(pi_dqs_found_all_bank),\n .I4(\\pi_dqs_found_all_bank_r_reg[1]_0 ),\n .I5(detect_pi_found_dqs),\n .O(p_0_in__1[2]));\n (* SOFT_HLUTNM = \"soft_lutpair273\" *) \n LUT5 #(\n .INIT(32'h15554000)) \n \\stable_pass_cnt[3]_i_1 \n (.I0(fine_adj_state_r144_out),\n .I1(stable_pass_cnt_reg__0[2]),\n .I2(stable_pass_cnt_reg__0[1]),\n .I3(\\stable_pass_cnt_reg_n_0_[0] ),\n .I4(stable_pass_cnt_reg__0[3]),\n .O(\\stable_pass_cnt[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h000000007FFF8000)) \n \\stable_pass_cnt[4]_i_1 \n (.I0(\\stable_pass_cnt_reg_n_0_[0] ),\n .I1(stable_pass_cnt_reg__0[1]),\n .I2(stable_pass_cnt_reg__0[2]),\n .I3(stable_pass_cnt_reg__0[3]),\n .I4(stable_pass_cnt_reg__0[4]),\n .I5(fine_adj_state_r144_out),\n .O(p_0_in__1[4]));\n LUT5 #(\n .INIT(32'h00200000)) \n \\stable_pass_cnt[5]_i_1 \n (.I0(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [1]),\n .I1(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [2]),\n .I2(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [3]),\n .I3(\\FSM_sequential_fine_adj_state_r_reg[0]_0 [0]),\n .I4(detect_pi_found_dqs),\n .O(stable_pass_cnt));\n LUT5 #(\n .INIT(32'h15554000)) \n \\stable_pass_cnt[5]_i_2 \n (.I0(fine_adj_state_r144_out),\n .I1(stable_pass_cnt_reg__0[4]),\n .I2(stable_pass_cnt_reg__0[3]),\n .I3(\\stable_pass_cnt[5]_i_3_n_0 ),\n .I4(stable_pass_cnt_reg__0[5]),\n .O(\\stable_pass_cnt[5]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair273\" *) \n LUT3 #(\n .INIT(8'h80)) \n \\stable_pass_cnt[5]_i_3 \n (.I0(stable_pass_cnt_reg__0[2]),\n .I1(stable_pass_cnt_reg__0[1]),\n .I2(\\stable_pass_cnt_reg_n_0_[0] ),\n .O(\\stable_pass_cnt[5]_i_3_n_0 ));\n FDRE \\stable_pass_cnt_reg[0] \n (.C(CLK),\n .CE(stable_pass_cnt),\n .D(p_0_in__1[0]),\n .Q(\\stable_pass_cnt_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE \\stable_pass_cnt_reg[1] \n (.C(CLK),\n .CE(stable_pass_cnt),\n .D(p_0_in__1[1]),\n .Q(stable_pass_cnt_reg__0[1]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE \\stable_pass_cnt_reg[2] \n (.C(CLK),\n .CE(stable_pass_cnt),\n .D(p_0_in__1[2]),\n .Q(stable_pass_cnt_reg__0[2]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE \\stable_pass_cnt_reg[3] \n (.C(CLK),\n .CE(stable_pass_cnt),\n .D(\\stable_pass_cnt[3]_i_1_n_0 ),\n .Q(stable_pass_cnt_reg__0[3]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE \\stable_pass_cnt_reg[4] \n (.C(CLK),\n .CE(stable_pass_cnt),\n .D(p_0_in__1[4]),\n .Q(stable_pass_cnt_reg__0[4]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE \\stable_pass_cnt_reg[5] \n (.C(CLK),\n .CE(stable_pass_cnt),\n .D(\\stable_pass_cnt[5]_i_2_n_0 ),\n .Q(stable_pass_cnt_reg__0[5]),\n .R(rstdiv0_sync_r1_reg_rep__2));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_ddr_phy_init\n (prbs_rdlvl_done_r1,\n prech_done,\n rdlvl_start_pre,\n rdlvl_start_dly0_r,\n in0,\n out,\n cnt_cmd_done_r,\n wrlvl_done_r1,\n prbs_last_byte_done_r,\n prech_pending_r_reg_0,\n pi_calib_done,\n wrcal_resume_r,\n complex_ocal_reset_rd_addr,\n wl_sm_start,\n wrcal_rd_wait,\n wrcal_sanity_chk,\n detect_pi_found_dqs,\n mpr_end_if_reset,\n init_complete_r1_reg_0,\n calib_complete,\n cnt_pwron_reset_done_r,\n cnt_pwron_cke_done_r,\n pi_dqs_found_done_r1,\n complex_act_start,\n \\oclkdelay_ref_cnt_reg[13]_0 ,\n cnt_txpr_done_r,\n cnt_dllk_zqinit_done_r,\n cnt_init_mr_done_r,\n ddr2_refresh_flag_r,\n ddr2_pre_flag_r_reg_0,\n cnt_init_af_done_r,\n burst_addr_r_reg_0,\n prech_pending_r,\n rdlvl_stg1_start_r_reg,\n ocal_last_byte_done,\n \\rd_ptr_timing_reg[0] ,\n phy_dout,\n reset_if_reg,\n oclk_calib_resume_level_reg_0,\n Q,\n \\odd_cwl.phy_cas_n_reg[1]_0 ,\n \\cnt_init_mr_r_reg[1]_0 ,\n \\init_state_r_reg[1]_0 ,\n cnt_init_mr_r,\n complex_oclkdelay_calib_start_int_reg_0,\n \\reg_ctrl_cnt_r_reg[3]_0 ,\n \\one_rank.stg1_wr_done_reg_0 ,\n \\init_state_r_reg[2]_0 ,\n mem_init_done_r,\n \\victim_sel_rotate.sel_reg[31] ,\n new_cnt_dqs_r_reg,\n prbs_rdlvl_start_r_reg,\n first_wrcal_pat_r,\n D2,\n D0,\n D3,\n D5,\n D6,\n D1,\n \\rd_ptr_timing_reg[0]_0 ,\n D7,\n D8,\n \\rd_ptr_timing_reg[0]_1 ,\n \\my_empty_reg[7] ,\n \\my_empty_reg[7]_0 ,\n \\my_empty_reg[7]_1 ,\n D4,\n \\my_empty_reg[7]_2 ,\n \\my_empty_reg[7]_3 ,\n \\my_empty_reg[7]_4 ,\n \\my_empty_reg[7]_5 ,\n \\rd_ptr_timing_reg[0]_2 ,\n D9,\n \\my_empty_reg[7]_6 ,\n \\my_empty_reg[7]_7 ,\n \\my_empty_reg[7]_8 ,\n \\my_empty_reg[7]_9 ,\n \\my_empty_reg[7]_10 ,\n \\my_empty_reg[7]_11 ,\n \\my_empty_reg[7]_12 ,\n \\my_empty_reg[7]_13 ,\n \\my_empty_reg[7]_14 ,\n \\my_empty_reg[7]_15 ,\n \\my_empty_reg[7]_16 ,\n \\my_empty_reg[7]_17 ,\n \\my_empty_reg[7]_18 ,\n \\my_empty_reg[7]_19 ,\n \\my_empty_reg[7]_20 ,\n \\my_empty_reg[7]_21 ,\n \\my_empty_reg[7]_22 ,\n \\my_empty_reg[7]_23 ,\n \\my_empty_reg[7]_24 ,\n \\my_empty_reg[7]_25 ,\n \\my_empty_reg[7]_26 ,\n \\my_empty_reg[7]_27 ,\n \\my_empty_reg[7]_28 ,\n \\my_empty_reg[7]_29 ,\n \\my_empty_reg[7]_30 ,\n \\my_empty_reg[7]_31 ,\n \\my_empty_reg[7]_32 ,\n \\my_empty_reg[7]_33 ,\n \\my_empty_reg[7]_34 ,\n \\my_empty_reg[7]_35 ,\n \\my_empty_reg[7]_36 ,\n \\my_empty_reg[7]_37 ,\n lim_start_r_reg,\n cal1_state_r1535_out,\n mpr_rdlvl_start_r_reg,\n E,\n \\cnt_shift_r_reg[0] ,\n cnt_init_mr_r1,\n prech_pending_r_reg_1,\n rdlvl_start_pre_reg_0,\n read_calib_reg_0,\n temp_lmr_done,\n stg1_wr_done,\n \\back_to_back_reads_4_1.num_reads_reg[0]_0 ,\n \\back_to_back_reads_4_1.num_reads_reg[1]_0 ,\n \\init_state_r_reg[4]_0 ,\n burst_addr_r_reg_1,\n oclkdelay_int_ref_req_reg_0,\n \\init_state_r_reg[5]_0 ,\n ddr2_pre_flag_r_reg_1,\n ddr2_refresh_flag_r_reg_0,\n \\en_cnt_div4.enable_wrlvl_cnt_reg[3]_0 ,\n \\complex_row_cnt_ocal_reg[0]_0 ,\n ddr3_lm_done_r,\n \\row_cnt_victim_rotate.complex_row_cnt_reg[4]_0 ,\n cnt_pwron_reset_done_r_reg_0,\n \\cnt_pwron_r_reg[7]_0 ,\n cnt_pwron_cke_done_r_reg_0,\n \\cnt_txpr_r_reg[2]_0 ,\n mem_init_done_r_reg_0,\n mem_init_done_r_reg_1,\n \\init_state_r_reg[0]_0 ,\n rdlvl_stg1_start_int,\n \\init_state_r_reg[2]_1 ,\n cnt_txpr_done_r_reg_0,\n \\pi_dqs_found_all_bank_reg[1] ,\n dqs_found_start_r_reg,\n mux_wrdata_en,\n mux_cmd_wren,\n mux_reset_n,\n \\data_offset_1_i1_reg[5] ,\n \\rd_ptr_timing_reg[0]_3 ,\n \\my_full_reg[3] ,\n \\phy_ctl_wd_i1_reg[24] ,\n \\my_empty_reg[7]_38 ,\n \\my_empty_reg[7]_39 ,\n \\my_empty_reg[7]_40 ,\n \\my_empty_reg[7]_41 ,\n \\samples_cnt_r_reg[11] ,\n \\wrcal_dqs_cnt_r_reg[0] ,\n \\rd_addr_reg_rep[7] ,\n \\rd_addr_reg[0] ,\n cnt_init_af_r,\n wrlvl_final_if_rst,\n wr_level_start_r_reg,\n wrcal_start_reg_0,\n phy_write_calib,\n phy_read_calib,\n first_rdlvl_pat_r,\n prbs_rdlvl_done_reg_rep,\n CLK,\n rdlvl_stg1_done_int_reg,\n A_rst_primitives_reg,\n rstdiv0_sync_r1_reg_rep__12,\n wr_level_done_reg,\n prbs_last_byte_done,\n wrlvl_rank_done,\n prbs_rdlvl_done_pulse0,\n reset_rd_addr0,\n prech_req,\n wrcal_resume_w,\n rstdiv0_sync_r1_reg_rep__11,\n rdlvl_last_byte_done,\n dqs_found_done_r_reg,\n rstdiv0_sync_r1_reg_rep__10,\n cnt_pwron_cke_done_r_reg_1,\n cnt_txpr_done_r_reg_1,\n cnt_dllk_zqinit_done_r_reg_0,\n cnt_init_mr_done_r_reg_0,\n cnt_cmd_done_r_reg_0,\n ddr2_pre_flag_r_reg_2,\n cnt_init_af_done_r_reg_0,\n burst_addr_r_reg_2,\n prech_req_posedge_r_reg_0,\n \\init_state_r_reg[0]_1 ,\n \\rdlvl_start_dly0_r_reg[14]_0 ,\n \\init_state_r_reg[6]_0 ,\n \\cnt_pwron_r_reg[7]_1 ,\n \\init_state_r_reg[6]_1 ,\n oclkdelay_center_calib_done_r_reg,\n rdlvl_stg1_done_int_reg_0,\n oclkdelay_calib_done_r_reg,\n oclkdelay_calib_done_r_reg_0,\n \\dout_o_reg[11] ,\n \\dout_o_reg[11]_0 ,\n D,\n wrcal_done_reg,\n \\dout_o_reg[9] ,\n \\dout_o_reg[9]_0 ,\n \\dout_o_reg[11]_1 ,\n \\dout_o_reg[11]_2 ,\n \\dout_o_reg[13] ,\n \\dout_o_reg[13]_0 ,\n wrcal_done_reg_0,\n \\dout_o_reg[9]_1 ,\n \\dout_o_reg[9]_2 ,\n \\dout_o_reg[9]_3 ,\n \\dout_o_reg[9]_4 ,\n \\dout_o_reg[13]_1 ,\n \\dout_o_reg[13]_2 ,\n \\dout_o_reg[1] ,\n \\dout_o_reg[1]_0 ,\n \\dout_o_reg[13]_3 ,\n \\dout_o_reg[13]_4 ,\n oclkdelay_calib_done_r_reg_1,\n \\dout_o_reg[11]_3 ,\n \\dout_o_reg[11]_4 ,\n \\dout_o_reg[13]_5 ,\n \\dout_o_reg[13]_6 ,\n \\dout_o_reg[15] ,\n \\dout_o_reg[7] ,\n \\dout_o_reg[15]_0 ,\n \\dout_o_reg[15]_1 ,\n \\dout_o_reg[7]_0 ,\n \\dout_o_reg[15]_2 ,\n wrcal_done_reg_1,\n \\dout_o_reg[3] ,\n \\dout_o_reg[3]_0 ,\n \\dout_o_reg[7]_1 ,\n \\dout_o_reg[7]_2 ,\n \\dout_o_reg[8] ,\n \\dout_o_reg[8]_0 ,\n \\dout_o_reg[14] ,\n \\dout_o_reg[14]_0 ,\n \\dout_o_reg[6] ,\n \\dout_o_reg[14]_1 ,\n \\dout_o_reg[14]_2 ,\n first_rdlvl_pat_r_reg_0,\n wrcal_done_reg_2,\n \\dout_o_reg[2] ,\n \\dout_o_reg[2]_0 ,\n \\dout_o_reg[4] ,\n \\dout_o_reg[4]_0 ,\n \\dout_o_reg[8]_1 ,\n \\dout_o_reg[8]_2 ,\n \\dout_o_reg[10] ,\n \\dout_o_reg[10]_0 ,\n \\dout_o_reg[8]_3 ,\n \\dout_o_reg[8]_4 ,\n \\dout_o_reg[12] ,\n \\dout_o_reg[12]_0 ,\n wrcal_done_reg_3,\n wrcal_done_reg_4,\n wrcal_done_reg_5,\n wrcal_done_reg_6,\n wrcal_done_reg_7,\n wrcal_done_reg_8,\n init_calib_complete_reg_rep__13,\n init_calib_complete_reg_rep__12,\n rstdiv0_sync_r1_reg_rep__25,\n reset_if_r9,\n prbs_rdlvl_done_reg,\n reset_if,\n delay_done_r4_reg,\n dqs_found_done_r_reg_0,\n wrcal_done_reg_9,\n oclkdelay_center_calib_start_r_reg,\n oclk_calib_resume_r_reg,\n prbs_rdlvl_done_reg_rep_0,\n complex_oclk_calib_resume,\n pi_dqs_found_rank_done,\n wrcal_sanity_chk_done_reg,\n wrcal_done_reg_10,\n wrlvl_byte_redo,\n wrcal_prech_req,\n \\init_state_r_reg[1]_1 ,\n prbs_rdlvl_start_r,\n oclkdelay_calib_done_r_reg_2,\n mc_cas_n,\n init_calib_complete_reg_rep__6,\n \\rd_ptr_reg[3] ,\n \\my_empty_reg[1] ,\n mem_out,\n \\my_empty_reg[1]_0 ,\n mc_ras_n,\n mc_odt,\n \\rd_ptr_reg[3]_0 ,\n \\my_empty_reg[1]_1 ,\n mc_cke,\n mc_we_n,\n \\cmd_pipe_plus.mc_address_reg[42] ,\n \\rd_ptr_reg[3]_1 ,\n \\my_empty_reg[1]_2 ,\n init_calib_complete_reg_rep__5,\n \\cmd_pipe_plus.mc_bank_reg[8] ,\n \\write_buffer.wr_buf_out_data_reg[255] ,\n \\rd_ptr_reg[3]_2 ,\n \\my_empty_reg[1]_3 ,\n \\rd_ptr_reg[3]_3 ,\n \\my_empty_reg[1]_4 ,\n init_calib_complete_reg_rep__4,\n \\rd_ptr_reg[3]_4 ,\n \\my_empty_reg[1]_5 ,\n \\rd_ptr_reg[3]_5 ,\n \\my_empty_reg[1]_6 ,\n init_calib_complete_reg_rep__3,\n init_calib_complete_reg_rep__2,\n init_calib_complete_reg_rep__1,\n init_calib_complete_reg_rep__0,\n init_calib_complete_reg_rep,\n \\rd_byte_data_offset_reg[0][3] ,\n init_dqsfound_done_r2,\n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3] ,\n \\rd_byte_data_offset_reg[0][9] ,\n \\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] ,\n mpr_rdlvl_start_r,\n phy_rddata_en_1,\n mpr_rdlvl_done_r_reg,\n \\cnt_shift_r_reg[0]_0 ,\n rstdiv0_sync_r1_reg_rep__23,\n \\mcGo_r_reg[15] ,\n ck_addr_cmd_delay_done,\n prbs_rdlvl_done_reg_0,\n wrlvl_final_mux,\n mpr_rdlvl_done_r_reg_0,\n \\init_state_r_reg[2]_2 ,\n rstdiv0_sync_r1_reg_rep__24,\n rdlvl_pi_incdec,\n dqs_found_prech_req,\n prbs_rdlvl_prech_req_reg,\n complex_ocal_ref_req,\n rdlvl_prech_req,\n complex_pi_incdec_done,\n wrcal_done_reg_11,\n rdlvl_stg1_done_int_reg_1,\n phy_if_empty_r_reg,\n wrcal_sanity_chk_done_reg_0,\n rdlvl_stg1_done_int_reg_2,\n oclkdelay_calib_done_r_reg_3,\n lim2init_prech_req,\n ocd_prech_req,\n oclkdelay_calib_done_r_reg_4,\n cnt_cmd_done_r_reg_1,\n oclkdelay_center_calib_start_r_reg_0,\n oclk_calib_resume_r_reg_0,\n mpr_rdlvl_done_r_reg_1,\n dqs_found_done_r_reg_1,\n wrlvl_byte_redo_reg,\n mpr_rdlvl_done_r_reg_2,\n oclkdelay_center_calib_done_r_reg_0,\n complex_victim_inc_reg,\n complex_ocal_num_samples_done_r,\n reset_rd_addr,\n dqs_found_done_r_reg_2,\n prbs_last_byte_done_reg,\n \\rd_victim_sel_reg[1] ,\n \\rd_victim_sel_reg[0] ,\n \\rd_victim_sel_reg[2] ,\n cnt_init_af_done_r_reg_1,\n num_samples_done_r,\n complex_init_pi_dec_done,\n done_r_reg,\n rdlvl_stg1_rank_done,\n write_request_r_reg,\n complex_ocal_rd_victim_sel,\n prbs_rdlvl_done_reg_rep_1,\n prbs_rdlvl_done_reg_rep_2,\n wrlvl_final_mux_reg,\n oclkdelay_calib_done_r_reg_5,\n wrlvl_byte_redo_reg_0,\n mem_init_done_r_reg_2,\n rdlvl_stg1_done_int_reg_3,\n wrlvl_final_mux_reg_0,\n prbs_rdlvl_done_reg_rep_3,\n mpr_last_byte_done,\n rdlvl_stg1_done_int_reg_4,\n \\dout_o_reg[0] ,\n \\dout_o_reg[0]_0 ,\n \\pi_dqs_found_all_bank_reg[1]_0 ,\n mc_wrdata_en,\n init_calib_complete_reg_rep__14,\n \\cmd_pipe_plus.mc_data_offset_1_reg[0] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[1] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[2] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[3] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[4] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[5] ,\n mc_cmd,\n \\cmd_pipe_plus.mc_data_offset_reg[0] ,\n \\cmd_pipe_plus.mc_data_offset_reg[1] ,\n \\cmd_pipe_plus.mc_data_offset_reg[2] ,\n \\cmd_pipe_plus.mc_data_offset_reg[3] ,\n \\cmd_pipe_plus.mc_data_offset_reg[4] ,\n \\cmd_pipe_plus.mc_data_offset_reg[5] ,\n init_calib_complete_reg_rep__11,\n init_calib_complete_reg_rep__10,\n init_calib_complete_reg_rep__9,\n init_calib_complete_reg_rep__8,\n init_calib_complete_reg_rep__7,\n \\samples_cnt_r_reg[11]_0 ,\n wrcal_sanity_chk_r_reg,\n \\rd_addr_reg[3] ,\n rstdiv0_sync_r1_reg_rep__20,\n rstdiv0_sync_r1_reg_rep__24_0,\n done_dqs_tap_inc,\n p_81_in,\n rstdiv0_sync_r1_reg_rep__24_1,\n pi_dqs_found_done_r1_reg_0,\n pi_dqs_found_done_r1_reg_1,\n pi_dqs_found_done_r1_reg_2,\n pi_dqs_found_done_r1_reg_3,\n pi_dqs_found_done_r1_reg_4,\n pi_dqs_found_done_r1_reg_5,\n pi_dqs_found_done_r1_reg_6,\n pi_dqs_found_done_r1_reg_7,\n rstdiv0_sync_r1_reg_rep__19,\n rstdiv0_sync_r1_reg_rep__18);\n output prbs_rdlvl_done_r1;\n output prech_done;\n output rdlvl_start_pre;\n output [0:0]rdlvl_start_dly0_r;\n output in0;\n output out;\n output cnt_cmd_done_r;\n output wrlvl_done_r1;\n output prbs_last_byte_done_r;\n output prech_pending_r_reg_0;\n output pi_calib_done;\n output wrcal_resume_r;\n output complex_ocal_reset_rd_addr;\n output wl_sm_start;\n output wrcal_rd_wait;\n output wrcal_sanity_chk;\n output detect_pi_found_dqs;\n output mpr_end_if_reset;\n output init_complete_r1_reg_0;\n output calib_complete;\n output cnt_pwron_reset_done_r;\n output cnt_pwron_cke_done_r;\n output pi_dqs_found_done_r1;\n output complex_act_start;\n output \\oclkdelay_ref_cnt_reg[13]_0 ;\n output cnt_txpr_done_r;\n output cnt_dllk_zqinit_done_r;\n output cnt_init_mr_done_r;\n output ddr2_refresh_flag_r;\n output ddr2_pre_flag_r_reg_0;\n output cnt_init_af_done_r;\n output burst_addr_r_reg_0;\n output prech_pending_r;\n output rdlvl_stg1_start_r_reg;\n output ocal_last_byte_done;\n output [33:0]\\rd_ptr_timing_reg[0] ;\n output [31:0]phy_dout;\n output reset_if_reg;\n output oclk_calib_resume_level_reg_0;\n output [5:0]Q;\n output \\odd_cwl.phy_cas_n_reg[1]_0 ;\n output \\cnt_init_mr_r_reg[1]_0 ;\n output \\init_state_r_reg[1]_0 ;\n output [1:0]cnt_init_mr_r;\n output complex_oclkdelay_calib_start_int_reg_0;\n output \\reg_ctrl_cnt_r_reg[3]_0 ;\n output \\one_rank.stg1_wr_done_reg_0 ;\n output \\init_state_r_reg[2]_0 ;\n output mem_init_done_r;\n output [7:0]\\victim_sel_rotate.sel_reg[31] ;\n output new_cnt_dqs_r_reg;\n output prbs_rdlvl_start_r_reg;\n output first_wrcal_pat_r;\n output [0:0]D2;\n output [0:0]D0;\n output [0:0]D3;\n output [3:0]D5;\n output [3:0]D6;\n output [0:0]D1;\n output [7:0]\\rd_ptr_timing_reg[0]_0 ;\n output [3:0]D7;\n output [3:0]D8;\n output [7:0]\\rd_ptr_timing_reg[0]_1 ;\n output [3:0]\\my_empty_reg[7] ;\n output [3:0]\\my_empty_reg[7]_0 ;\n output [3:0]\\my_empty_reg[7]_1 ;\n output [3:0]D4;\n output [3:0]\\my_empty_reg[7]_2 ;\n output [3:0]\\my_empty_reg[7]_3 ;\n output [3:0]\\my_empty_reg[7]_4 ;\n output [3:0]\\my_empty_reg[7]_5 ;\n output [3:0]\\rd_ptr_timing_reg[0]_2 ;\n output [3:0]D9;\n output [7:0]\\my_empty_reg[7]_6 ;\n output [7:0]\\my_empty_reg[7]_7 ;\n output [7:0]\\my_empty_reg[7]_8 ;\n output [7:0]\\my_empty_reg[7]_9 ;\n output [7:0]\\my_empty_reg[7]_10 ;\n output [7:0]\\my_empty_reg[7]_11 ;\n output [7:0]\\my_empty_reg[7]_12 ;\n output [7:0]\\my_empty_reg[7]_13 ;\n output [7:0]\\my_empty_reg[7]_14 ;\n output [7:0]\\my_empty_reg[7]_15 ;\n output [7:0]\\my_empty_reg[7]_16 ;\n output [7:0]\\my_empty_reg[7]_17 ;\n output [7:0]\\my_empty_reg[7]_18 ;\n output [7:0]\\my_empty_reg[7]_19 ;\n output [7:0]\\my_empty_reg[7]_20 ;\n output [7:0]\\my_empty_reg[7]_21 ;\n output [7:0]\\my_empty_reg[7]_22 ;\n output [7:0]\\my_empty_reg[7]_23 ;\n output [7:0]\\my_empty_reg[7]_24 ;\n output [7:0]\\my_empty_reg[7]_25 ;\n output [7:0]\\my_empty_reg[7]_26 ;\n output [7:0]\\my_empty_reg[7]_27 ;\n output [7:0]\\my_empty_reg[7]_28 ;\n output [7:0]\\my_empty_reg[7]_29 ;\n output [7:0]\\my_empty_reg[7]_30 ;\n output [7:0]\\my_empty_reg[7]_31 ;\n output [7:0]\\my_empty_reg[7]_32 ;\n output [7:0]\\my_empty_reg[7]_33 ;\n output [7:0]\\my_empty_reg[7]_34 ;\n output [7:0]\\my_empty_reg[7]_35 ;\n output [7:0]\\my_empty_reg[7]_36 ;\n output [7:0]\\my_empty_reg[7]_37 ;\n output lim_start_r_reg;\n output cal1_state_r1535_out;\n output mpr_rdlvl_start_r_reg;\n output [0:0]E;\n output [0:0]\\cnt_shift_r_reg[0] ;\n output cnt_init_mr_r1;\n output prech_pending_r_reg_1;\n output rdlvl_start_pre_reg_0;\n output read_calib_reg_0;\n output temp_lmr_done;\n output stg1_wr_done;\n output \\back_to_back_reads_4_1.num_reads_reg[0]_0 ;\n output \\back_to_back_reads_4_1.num_reads_reg[1]_0 ;\n output \\init_state_r_reg[4]_0 ;\n output burst_addr_r_reg_1;\n output oclkdelay_int_ref_req_reg_0;\n output \\init_state_r_reg[5]_0 ;\n output ddr2_pre_flag_r_reg_1;\n output ddr2_refresh_flag_r_reg_0;\n output \\en_cnt_div4.enable_wrlvl_cnt_reg[3]_0 ;\n output \\complex_row_cnt_ocal_reg[0]_0 ;\n output ddr3_lm_done_r;\n output \\row_cnt_victim_rotate.complex_row_cnt_reg[4]_0 ;\n output cnt_pwron_reset_done_r_reg_0;\n output [3:0]\\cnt_pwron_r_reg[7]_0 ;\n output cnt_pwron_cke_done_r_reg_0;\n output [2:0]\\cnt_txpr_r_reg[2]_0 ;\n output [1:0]mem_init_done_r_reg_0;\n output mem_init_done_r_reg_1;\n output \\init_state_r_reg[0]_0 ;\n output rdlvl_stg1_start_int;\n output \\init_state_r_reg[2]_1 ;\n output cnt_txpr_done_r_reg_0;\n output \\pi_dqs_found_all_bank_reg[1] ;\n output dqs_found_start_r_reg;\n output mux_wrdata_en;\n output mux_cmd_wren;\n output mux_reset_n;\n output [5:0]\\data_offset_1_i1_reg[5] ;\n output [1:0]\\rd_ptr_timing_reg[0]_3 ;\n output [1:0]\\my_full_reg[3] ;\n output [10:0]\\phy_ctl_wd_i1_reg[24] ;\n output [63:0]\\my_empty_reg[7]_38 ;\n output [63:0]\\my_empty_reg[7]_39 ;\n output [63:0]\\my_empty_reg[7]_40 ;\n output [63:0]\\my_empty_reg[7]_41 ;\n output [0:0]\\samples_cnt_r_reg[11] ;\n output \\wrcal_dqs_cnt_r_reg[0] ;\n output \\rd_addr_reg_rep[7] ;\n output [0:0]\\rd_addr_reg[0] ;\n output [1:0]cnt_init_af_r;\n output wrlvl_final_if_rst;\n output wr_level_start_r_reg;\n output wrcal_start_reg_0;\n output phy_write_calib;\n output phy_read_calib;\n output first_rdlvl_pat_r;\n input prbs_rdlvl_done_reg_rep;\n input CLK;\n input rdlvl_stg1_done_int_reg;\n input A_rst_primitives_reg;\n input rstdiv0_sync_r1_reg_rep__12;\n input wr_level_done_reg;\n input prbs_last_byte_done;\n input wrlvl_rank_done;\n input prbs_rdlvl_done_pulse0;\n input reset_rd_addr0;\n input prech_req;\n input wrcal_resume_w;\n input [0:0]rstdiv0_sync_r1_reg_rep__11;\n input rdlvl_last_byte_done;\n input dqs_found_done_r_reg;\n input rstdiv0_sync_r1_reg_rep__10;\n input cnt_pwron_cke_done_r_reg_1;\n input cnt_txpr_done_r_reg_1;\n input cnt_dllk_zqinit_done_r_reg_0;\n input cnt_init_mr_done_r_reg_0;\n input cnt_cmd_done_r_reg_0;\n input ddr2_pre_flag_r_reg_2;\n input cnt_init_af_done_r_reg_0;\n input burst_addr_r_reg_2;\n input prech_req_posedge_r_reg_0;\n input \\init_state_r_reg[0]_1 ;\n input \\rdlvl_start_dly0_r_reg[14]_0 ;\n input \\init_state_r_reg[6]_0 ;\n input \\cnt_pwron_r_reg[7]_1 ;\n input \\init_state_r_reg[6]_1 ;\n input oclkdelay_center_calib_done_r_reg;\n input rdlvl_stg1_done_int_reg_0;\n input oclkdelay_calib_done_r_reg;\n input oclkdelay_calib_done_r_reg_0;\n input \\dout_o_reg[11] ;\n input \\dout_o_reg[11]_0 ;\n input [1:0]D;\n input wrcal_done_reg;\n input \\dout_o_reg[9] ;\n input \\dout_o_reg[9]_0 ;\n input \\dout_o_reg[11]_1 ;\n input \\dout_o_reg[11]_2 ;\n input \\dout_o_reg[13] ;\n input \\dout_o_reg[13]_0 ;\n input wrcal_done_reg_0;\n input \\dout_o_reg[9]_1 ;\n input \\dout_o_reg[9]_2 ;\n input \\dout_o_reg[9]_3 ;\n input \\dout_o_reg[9]_4 ;\n input \\dout_o_reg[13]_1 ;\n input \\dout_o_reg[13]_2 ;\n input \\dout_o_reg[1] ;\n input \\dout_o_reg[1]_0 ;\n input \\dout_o_reg[13]_3 ;\n input \\dout_o_reg[13]_4 ;\n input oclkdelay_calib_done_r_reg_1;\n input \\dout_o_reg[11]_3 ;\n input \\dout_o_reg[11]_4 ;\n input \\dout_o_reg[13]_5 ;\n input \\dout_o_reg[13]_6 ;\n input \\dout_o_reg[15] ;\n input \\dout_o_reg[7] ;\n input \\dout_o_reg[15]_0 ;\n input \\dout_o_reg[15]_1 ;\n input \\dout_o_reg[7]_0 ;\n input \\dout_o_reg[15]_2 ;\n input wrcal_done_reg_1;\n input \\dout_o_reg[3] ;\n input \\dout_o_reg[3]_0 ;\n input \\dout_o_reg[7]_1 ;\n input \\dout_o_reg[7]_2 ;\n input \\dout_o_reg[8] ;\n input \\dout_o_reg[8]_0 ;\n input \\dout_o_reg[14] ;\n input \\dout_o_reg[14]_0 ;\n input \\dout_o_reg[6] ;\n input \\dout_o_reg[14]_1 ;\n input \\dout_o_reg[14]_2 ;\n input first_rdlvl_pat_r_reg_0;\n input wrcal_done_reg_2;\n input \\dout_o_reg[2] ;\n input \\dout_o_reg[2]_0 ;\n input \\dout_o_reg[4] ;\n input \\dout_o_reg[4]_0 ;\n input \\dout_o_reg[8]_1 ;\n input \\dout_o_reg[8]_2 ;\n input \\dout_o_reg[10] ;\n input \\dout_o_reg[10]_0 ;\n input \\dout_o_reg[8]_3 ;\n input \\dout_o_reg[8]_4 ;\n input \\dout_o_reg[12] ;\n input \\dout_o_reg[12]_0 ;\n input wrcal_done_reg_3;\n input wrcal_done_reg_4;\n input wrcal_done_reg_5;\n input wrcal_done_reg_6;\n input wrcal_done_reg_7;\n input wrcal_done_reg_8;\n input init_calib_complete_reg_rep__13;\n input init_calib_complete_reg_rep__12;\n input rstdiv0_sync_r1_reg_rep__25;\n input reset_if_r9;\n input prbs_rdlvl_done_reg;\n input reset_if;\n input delay_done_r4_reg;\n input dqs_found_done_r_reg_0;\n input wrcal_done_reg_9;\n input oclkdelay_center_calib_start_r_reg;\n input oclk_calib_resume_r_reg;\n input prbs_rdlvl_done_reg_rep_0;\n input complex_oclk_calib_resume;\n input pi_dqs_found_rank_done;\n input wrcal_sanity_chk_done_reg;\n input wrcal_done_reg_10;\n input wrlvl_byte_redo;\n input wrcal_prech_req;\n input \\init_state_r_reg[1]_1 ;\n input prbs_rdlvl_start_r;\n input oclkdelay_calib_done_r_reg_2;\n input [0:0]mc_cas_n;\n input init_calib_complete_reg_rep__6;\n input [33:0]\\rd_ptr_reg[3] ;\n input \\my_empty_reg[1] ;\n input [1:0]mem_out;\n input \\my_empty_reg[1]_0 ;\n input [0:0]mc_ras_n;\n input [0:0]mc_odt;\n input [7:0]\\rd_ptr_reg[3]_0 ;\n input \\my_empty_reg[1]_1 ;\n input [0:0]mc_cke;\n input [0:0]mc_we_n;\n input [33:0]\\cmd_pipe_plus.mc_address_reg[42] ;\n input [31:0]\\rd_ptr_reg[3]_1 ;\n input \\my_empty_reg[1]_2 ;\n input init_calib_complete_reg_rep__5;\n input [8:0]\\cmd_pipe_plus.mc_bank_reg[8] ;\n input [255:0]\\write_buffer.wr_buf_out_data_reg[255] ;\n input [63:0]\\rd_ptr_reg[3]_2 ;\n input \\my_empty_reg[1]_3 ;\n input [63:0]\\rd_ptr_reg[3]_3 ;\n input \\my_empty_reg[1]_4 ;\n input init_calib_complete_reg_rep__4;\n input [63:0]\\rd_ptr_reg[3]_4 ;\n input \\my_empty_reg[1]_5 ;\n input [63:0]\\rd_ptr_reg[3]_5 ;\n input \\my_empty_reg[1]_6 ;\n input init_calib_complete_reg_rep__3;\n input init_calib_complete_reg_rep__2;\n input init_calib_complete_reg_rep__1;\n input init_calib_complete_reg_rep__0;\n input init_calib_complete_reg_rep;\n input [1:0]\\rd_byte_data_offset_reg[0][3] ;\n input init_dqsfound_done_r2;\n input [1:0]\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3] ;\n input [1:0]\\rd_byte_data_offset_reg[0][9] ;\n input [1:0]\\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] ;\n input mpr_rdlvl_start_r;\n input phy_rddata_en_1;\n input mpr_rdlvl_done_r_reg;\n input \\cnt_shift_r_reg[0]_0 ;\n input rstdiv0_sync_r1_reg_rep__23;\n input \\mcGo_r_reg[15] ;\n input ck_addr_cmd_delay_done;\n input prbs_rdlvl_done_reg_0;\n input wrlvl_final_mux;\n input mpr_rdlvl_done_r_reg_0;\n input \\init_state_r_reg[2]_2 ;\n input rstdiv0_sync_r1_reg_rep__24;\n input rdlvl_pi_incdec;\n input dqs_found_prech_req;\n input prbs_rdlvl_prech_req_reg;\n input complex_ocal_ref_req;\n input rdlvl_prech_req;\n input complex_pi_incdec_done;\n input wrcal_done_reg_11;\n input rdlvl_stg1_done_int_reg_1;\n input phy_if_empty_r_reg;\n input wrcal_sanity_chk_done_reg_0;\n input rdlvl_stg1_done_int_reg_2;\n input oclkdelay_calib_done_r_reg_3;\n input lim2init_prech_req;\n input ocd_prech_req;\n input oclkdelay_calib_done_r_reg_4;\n input cnt_cmd_done_r_reg_1;\n input oclkdelay_center_calib_start_r_reg_0;\n input oclk_calib_resume_r_reg_0;\n input mpr_rdlvl_done_r_reg_1;\n input dqs_found_done_r_reg_1;\n input wrlvl_byte_redo_reg;\n input mpr_rdlvl_done_r_reg_2;\n input oclkdelay_center_calib_done_r_reg_0;\n input complex_victim_inc_reg;\n input complex_ocal_num_samples_done_r;\n input reset_rd_addr;\n input dqs_found_done_r_reg_2;\n input prbs_last_byte_done_reg;\n input \\rd_victim_sel_reg[1] ;\n input \\rd_victim_sel_reg[0] ;\n input \\rd_victim_sel_reg[2] ;\n input cnt_init_af_done_r_reg_1;\n input num_samples_done_r;\n input complex_init_pi_dec_done;\n input done_r_reg;\n input rdlvl_stg1_rank_done;\n input write_request_r_reg;\n input [2:0]complex_ocal_rd_victim_sel;\n input prbs_rdlvl_done_reg_rep_1;\n input prbs_rdlvl_done_reg_rep_2;\n input wrlvl_final_mux_reg;\n input oclkdelay_calib_done_r_reg_5;\n input wrlvl_byte_redo_reg_0;\n input mem_init_done_r_reg_2;\n input rdlvl_stg1_done_int_reg_3;\n input wrlvl_final_mux_reg_0;\n input prbs_rdlvl_done_reg_rep_3;\n input mpr_last_byte_done;\n input rdlvl_stg1_done_int_reg_4;\n input \\dout_o_reg[0] ;\n input \\dout_o_reg[0]_0 ;\n input [0:0]\\pi_dqs_found_all_bank_reg[1]_0 ;\n input mc_wrdata_en;\n input init_calib_complete_reg_rep__14;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[0] ;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[1] ;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[2] ;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[3] ;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[4] ;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[5] ;\n input [1:0]mc_cmd;\n input \\cmd_pipe_plus.mc_data_offset_reg[0] ;\n input \\cmd_pipe_plus.mc_data_offset_reg[1] ;\n input \\cmd_pipe_plus.mc_data_offset_reg[2] ;\n input \\cmd_pipe_plus.mc_data_offset_reg[3] ;\n input \\cmd_pipe_plus.mc_data_offset_reg[4] ;\n input \\cmd_pipe_plus.mc_data_offset_reg[5] ;\n input init_calib_complete_reg_rep__11;\n input init_calib_complete_reg_rep__10;\n input init_calib_complete_reg_rep__9;\n input init_calib_complete_reg_rep__8;\n input init_calib_complete_reg_rep__7;\n input \\samples_cnt_r_reg[11]_0 ;\n input wrcal_sanity_chk_r_reg;\n input [0:0]\\rd_addr_reg[3] ;\n input rstdiv0_sync_r1_reg_rep__20;\n input rstdiv0_sync_r1_reg_rep__24_0;\n input done_dqs_tap_inc;\n input p_81_in;\n input rstdiv0_sync_r1_reg_rep__24_1;\n input pi_dqs_found_done_r1_reg_0;\n input pi_dqs_found_done_r1_reg_1;\n input pi_dqs_found_done_r1_reg_2;\n input pi_dqs_found_done_r1_reg_3;\n input pi_dqs_found_done_r1_reg_4;\n input pi_dqs_found_done_r1_reg_5;\n input pi_dqs_found_done_r1_reg_6;\n input pi_dqs_found_done_r1_reg_7;\n input [0:0]rstdiv0_sync_r1_reg_rep__19;\n input [0:0]rstdiv0_sync_r1_reg_rep__18;\n\n wire A_rst_primitives_reg;\n wire CLK;\n wire [1:0]D;\n wire [0:0]D0;\n wire [0:0]D1;\n wire [0:0]D2;\n wire [0:0]D3;\n wire [3:0]D4;\n wire [3:0]D5;\n wire [3:0]D6;\n wire [3:0]D7;\n wire [3:0]D8;\n wire [3:0]D9;\n wire \\DDR3_1rank.phy_int_cs_n[1]_i_1_n_0 ;\n wire \\DDR3_1rank.phy_int_cs_n[1]_i_3_n_0 ;\n wire \\DDR3_1rank.phy_int_cs_n[1]_i_4_n_0 ;\n wire \\DDR3_1rank.phy_int_cs_n[1]_i_5_n_0 ;\n wire \\DDR3_1rank.phy_int_cs_n[1]_i_6_n_0 ;\n wire \\DDR3_1rank.phy_int_cs_n[1]_i_7_n_0 ;\n wire \\DDR3_1rank.phy_int_cs_n[1]_i_8_n_0 ;\n wire [0:0]E;\n wire [5:0]Q;\n wire \\back_to_back_reads_4_1.num_reads[0]_i_1_n_0 ;\n wire \\back_to_back_reads_4_1.num_reads[1]_i_1_n_0 ;\n wire \\back_to_back_reads_4_1.num_reads[1]_i_2_n_0 ;\n wire \\back_to_back_reads_4_1.num_reads[2]_i_1_n_0 ;\n wire \\back_to_back_reads_4_1.num_reads_reg[0]_0 ;\n wire \\back_to_back_reads_4_1.num_reads_reg[1]_0 ;\n wire [1:0]bank_w;\n wire burst_addr_r_reg_0;\n wire burst_addr_r_reg_1;\n wire burst_addr_r_reg_2;\n wire cal1_state_r1535_out;\n wire [3:3]calib_cke;\n wire [2:0]calib_cmd;\n wire \\calib_cmd[0]_i_1_n_0 ;\n wire \\calib_cmd[1]_i_1_n_0 ;\n wire \\calib_cmd[2]_i_1_n_0 ;\n wire \\calib_cmd[2]_i_2_n_0 ;\n wire \\calib_cmd[2]_i_3_n_0 ;\n wire \\calib_cmd[2]_i_4_n_0 ;\n wire \\calib_cmd[2]_i_5_n_0 ;\n wire \\calib_cmd[2]_i_6_n_0 ;\n wire \\calib_cmd[2]_i_7_n_0 ;\n wire \\calib_cmd[2]_i_8_n_0 ;\n wire calib_complete;\n wire calib_ctl_wren;\n wire calib_ctl_wren0;\n wire [5:0]calib_data_offset_0;\n wire \\calib_data_offset_0[2]_i_1_n_0 ;\n wire \\calib_data_offset_0[3]_i_1_n_0 ;\n wire \\calib_data_offset_0[3]_i_2_n_0 ;\n wire \\calib_data_offset_0[5]_i_1_n_0 ;\n wire [5:0]calib_data_offset_1;\n wire \\calib_data_offset_1[2]_i_1_n_0 ;\n wire \\calib_data_offset_1[3]_i_1_n_0 ;\n wire [0:0]calib_odt;\n wire \\calib_odt[0]_i_1_n_0 ;\n wire \\calib_odt[0]_i_2_n_0 ;\n wire \\calib_odt[0]_i_3_n_0 ;\n wire \\calib_odt[0]_i_4_n_0 ;\n wire \\calib_seq[0]_i_1_n_0 ;\n wire \\calib_seq[1]_i_1_n_0 ;\n wire calib_wrdata_en;\n wire ck_addr_cmd_delay_done;\n wire clear;\n wire [33:0]\\cmd_pipe_plus.mc_address_reg[42] ;\n wire [8:0]\\cmd_pipe_plus.mc_bank_reg[8] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[0] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[1] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[2] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[3] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[4] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[5] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[0] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[1] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[2] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[3] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[4] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[5] ;\n wire cnt_cmd_done_m7_r;\n wire cnt_cmd_done_m7_r_i_1_n_0;\n wire cnt_cmd_done_m7_r_i_2_n_0;\n wire cnt_cmd_done_r;\n wire cnt_cmd_done_r_i_1_n_0;\n wire cnt_cmd_done_r_reg_0;\n wire cnt_cmd_done_r_reg_1;\n wire \\cnt_cmd_r[0]_i_1_n_0 ;\n wire \\cnt_cmd_r[1]_i_1_n_0 ;\n wire \\cnt_cmd_r[2]_i_1_n_0 ;\n wire \\cnt_cmd_r[3]_i_1_n_0 ;\n wire \\cnt_cmd_r[4]_i_1_n_0 ;\n wire \\cnt_cmd_r[5]_i_1_n_0 ;\n wire \\cnt_cmd_r[6]_i_1_n_0 ;\n wire \\cnt_cmd_r[6]_i_2_n_0 ;\n wire \\cnt_cmd_r[6]_i_3_n_0 ;\n wire \\cnt_cmd_r[6]_i_4_n_0 ;\n wire \\cnt_cmd_r[6]_i_5_n_0 ;\n wire \\cnt_cmd_r_reg_n_0_[0] ;\n wire \\cnt_cmd_r_reg_n_0_[1] ;\n wire \\cnt_cmd_r_reg_n_0_[2] ;\n wire \\cnt_cmd_r_reg_n_0_[3] ;\n wire \\cnt_cmd_r_reg_n_0_[4] ;\n wire \\cnt_cmd_r_reg_n_0_[5] ;\n wire \\cnt_cmd_r_reg_n_0_[6] ;\n wire cnt_dllk_zqinit_done_r;\n wire cnt_dllk_zqinit_done_r_reg_0;\n wire cnt_dllk_zqinit_r;\n wire [5:0]cnt_dllk_zqinit_r_reg__0;\n wire cnt_init_af_done_r;\n wire cnt_init_af_done_r_reg_0;\n wire cnt_init_af_done_r_reg_1;\n wire [1:0]cnt_init_af_r;\n wire \\cnt_init_af_r[0]_i_1_n_0 ;\n wire \\cnt_init_af_r[1]_i_1_n_0 ;\n wire cnt_init_mr_done_r;\n wire cnt_init_mr_done_r_reg_0;\n wire [1:0]cnt_init_mr_r;\n wire cnt_init_mr_r1;\n wire \\cnt_init_mr_r[0]_i_1_n_0 ;\n wire \\cnt_init_mr_r[1]_i_1_n_0 ;\n wire \\cnt_init_mr_r_reg[1]_0 ;\n wire [9:0]cnt_pwron_ce_r_reg__0;\n wire cnt_pwron_cke_done_r;\n wire cnt_pwron_cke_done_r_reg_0;\n wire cnt_pwron_cke_done_r_reg_1;\n wire \\cnt_pwron_r[6]_i_2_n_0 ;\n wire \\cnt_pwron_r[8]_i_2_n_0 ;\n wire [3:0]\\cnt_pwron_r_reg[7]_0 ;\n wire \\cnt_pwron_r_reg[7]_1 ;\n wire [8:2]cnt_pwron_r_reg__0;\n wire cnt_pwron_reset_done_r;\n wire cnt_pwron_reset_done_r_reg_0;\n wire [0:0]\\cnt_shift_r_reg[0] ;\n wire \\cnt_shift_r_reg[0]_0 ;\n wire cnt_txpr_done_r;\n wire cnt_txpr_done_r_reg_0;\n wire cnt_txpr_done_r_reg_1;\n wire \\cnt_txpr_r[7]_i_3_n_0 ;\n wire [2:0]\\cnt_txpr_r_reg[2]_0 ;\n wire [7:3]cnt_txpr_r_reg__0;\n wire complex_act_start;\n wire complex_act_start0;\n wire complex_address0;\n wire \\complex_address[9]_i_2_n_0 ;\n wire \\complex_address[9]_i_3_n_0 ;\n wire \\complex_address[9]_i_4_n_0 ;\n wire \\complex_address_reg_n_0_[0] ;\n wire \\complex_address_reg_n_0_[1] ;\n wire \\complex_address_reg_n_0_[2] ;\n wire \\complex_address_reg_n_0_[3] ;\n wire \\complex_address_reg_n_0_[4] ;\n wire \\complex_address_reg_n_0_[5] ;\n wire \\complex_address_reg_n_0_[6] ;\n wire \\complex_address_reg_n_0_[7] ;\n wire \\complex_address_reg_n_0_[8] ;\n wire \\complex_address_reg_n_0_[9] ;\n wire complex_byte_rd_done;\n wire complex_byte_rd_done_i_1_n_0;\n wire complex_byte_rd_done_i_2_n_0;\n wire complex_init_pi_dec_done;\n wire complex_mask_lim_done;\n wire complex_mask_lim_done_i_1_n_0;\n wire \\complex_num_reads[0]_i_1_n_0 ;\n wire \\complex_num_reads[1]_i_1_n_0 ;\n wire \\complex_num_reads[1]_i_2_n_0 ;\n wire \\complex_num_reads[2]_i_1_n_0 ;\n wire \\complex_num_reads[2]_i_2_n_0 ;\n wire \\complex_num_reads[2]_i_3_n_0 ;\n wire \\complex_num_reads[2]_i_4_n_0 ;\n wire \\complex_num_reads[2]_i_5_n_0 ;\n wire \\complex_num_reads[2]_i_6_n_0 ;\n wire \\complex_num_reads[3]_i_1_n_0 ;\n wire \\complex_num_reads[3]_i_2_n_0 ;\n wire \\complex_num_reads[3]_i_3_n_0 ;\n wire \\complex_num_reads[3]_i_4_n_0 ;\n wire \\complex_num_reads[3]_i_5_n_0 ;\n wire \\complex_num_reads[3]_i_6_n_0 ;\n wire \\complex_num_reads[3]_i_7_n_0 ;\n wire \\complex_num_reads[3]_i_8_n_0 ;\n wire \\complex_num_reads_dec[3]_i_2_n_0 ;\n wire \\complex_num_reads_dec[3]_i_4_n_0 ;\n wire \\complex_num_reads_dec[3]_i_5_n_0 ;\n wire [3:0]complex_num_reads_dec_reg__0;\n wire \\complex_num_reads_reg_n_0_[0] ;\n wire \\complex_num_reads_reg_n_0_[1] ;\n wire \\complex_num_reads_reg_n_0_[2] ;\n wire \\complex_num_reads_reg_n_0_[3] ;\n wire \\complex_num_writes[0]_i_1_n_0 ;\n wire \\complex_num_writes[0]_i_2_n_0 ;\n wire \\complex_num_writes[1]_i_1_n_0 ;\n wire \\complex_num_writes[1]_i_2_n_0 ;\n wire \\complex_num_writes[2]_i_1_n_0 ;\n wire \\complex_num_writes[2]_i_2_n_0 ;\n wire \\complex_num_writes[2]_i_3_n_0 ;\n wire \\complex_num_writes[2]_i_4_n_0 ;\n wire \\complex_num_writes[2]_i_5_n_0 ;\n wire \\complex_num_writes[2]_i_6_n_0 ;\n wire \\complex_num_writes[2]_i_7_n_0 ;\n wire \\complex_num_writes[2]_i_8_n_0 ;\n wire \\complex_num_writes[3]_i_1_n_0 ;\n wire \\complex_num_writes[3]_i_2_n_0 ;\n wire \\complex_num_writes[3]_i_3_n_0 ;\n wire \\complex_num_writes[3]_i_4_n_0 ;\n wire \\complex_num_writes[4]_i_10_n_0 ;\n wire \\complex_num_writes[4]_i_11_n_0 ;\n wire \\complex_num_writes[4]_i_12_n_0 ;\n wire \\complex_num_writes[4]_i_13_n_0 ;\n wire \\complex_num_writes[4]_i_14_n_0 ;\n wire \\complex_num_writes[4]_i_15_n_0 ;\n wire \\complex_num_writes[4]_i_1_n_0 ;\n wire \\complex_num_writes[4]_i_2_n_0 ;\n wire \\complex_num_writes[4]_i_3_n_0 ;\n wire \\complex_num_writes[4]_i_4_n_0 ;\n wire \\complex_num_writes[4]_i_5_n_0 ;\n wire \\complex_num_writes[4]_i_6_n_0 ;\n wire \\complex_num_writes[4]_i_7_n_0 ;\n wire \\complex_num_writes[4]_i_8_n_0 ;\n wire \\complex_num_writes[4]_i_9_n_0 ;\n wire \\complex_num_writes_dec[4]_i_2_n_0 ;\n wire \\complex_num_writes_dec[4]_i_4_n_0 ;\n wire \\complex_num_writes_dec[4]_i_5_n_0 ;\n wire \\complex_num_writes_dec[4]_i_6_n_0 ;\n wire [4:0]complex_num_writes_dec_reg__0;\n wire \\complex_num_writes_reg_n_0_[0] ;\n wire \\complex_num_writes_reg_n_0_[1] ;\n wire \\complex_num_writes_reg_n_0_[2] ;\n wire \\complex_num_writes_reg_n_0_[3] ;\n wire \\complex_num_writes_reg_n_0_[4] ;\n wire complex_ocal_num_samples_done_r;\n wire complex_ocal_odt_ext;\n wire complex_ocal_odt_ext_i_1_n_0;\n wire complex_ocal_odt_ext_i_2_n_0;\n wire complex_ocal_odt_ext_i_3_n_0;\n wire complex_ocal_odt_ext_i_4_n_0;\n wire [2:0]complex_ocal_rd_victim_sel;\n wire complex_ocal_ref_req;\n wire complex_ocal_reset_rd_addr;\n wire complex_ocal_reset_rd_addr0;\n wire complex_ocal_reset_rd_addr_i_2_n_0;\n wire complex_ocal_reset_rd_addr_i_3_n_0;\n wire complex_ocal_wr_start;\n wire complex_ocal_wr_start_i_1_n_0;\n wire complex_oclk_calib_resume;\n wire complex_oclkdelay_calib_done_r1;\n wire complex_oclkdelay_calib_start_int;\n wire complex_oclkdelay_calib_start_int_i_1_n_0;\n wire complex_oclkdelay_calib_start_int_i_2_n_0;\n wire complex_oclkdelay_calib_start_int_reg_0;\n wire complex_oclkdelay_calib_start_r1;\n wire complex_oclkdelay_calib_start_r2;\n wire complex_odt_ext;\n wire complex_odt_ext_i_1_n_0;\n wire complex_pi_incdec_done;\n wire complex_row0_rd_done;\n wire complex_row0_rd_done1;\n wire complex_row0_rd_done_i_1_n_0;\n wire complex_row0_rd_done_i_2_n_0;\n wire complex_row0_wr_done;\n wire complex_row0_wr_done0;\n wire [2:0]complex_row1_rd_cnt;\n wire \\complex_row1_rd_cnt[0]_i_1_n_0 ;\n wire \\complex_row1_rd_cnt[1]_i_1_n_0 ;\n wire \\complex_row1_rd_cnt[2]_i_1_n_0 ;\n wire complex_row1_rd_done;\n wire complex_row1_rd_done_i_1_n_0;\n wire complex_row1_rd_done_i_2_n_0;\n wire complex_row1_rd_done_r1;\n wire complex_row1_wr_done;\n wire complex_row_cnt;\n wire complex_row_cnt_ocal;\n wire complex_row_cnt_ocal0;\n wire \\complex_row_cnt_ocal[7]_i_5_n_0 ;\n wire \\complex_row_cnt_ocal[7]_i_6_n_0 ;\n wire \\complex_row_cnt_ocal[7]_i_7_n_0 ;\n wire \\complex_row_cnt_ocal[7]_i_8_n_0 ;\n wire \\complex_row_cnt_ocal[7]_i_9_n_0 ;\n wire \\complex_row_cnt_ocal_reg[0]_0 ;\n wire [7:0]complex_row_cnt_ocal_reg__0;\n wire complex_sample_cnt_inc;\n wire complex_sample_cnt_inc0;\n wire complex_sample_cnt_inc_i_2_n_0;\n wire complex_sample_cnt_inc_r1;\n wire complex_sample_cnt_inc_r2;\n wire complex_victim_inc_reg;\n wire \\complex_wait_cnt[3]_i_1_n_0 ;\n wire \\complex_wait_cnt[3]_i_3_n_0 ;\n wire [3:0]complex_wait_cnt_reg__0;\n wire complex_wr_done;\n wire [5:0]\\data_offset_1_i1_reg[5] ;\n wire ddr2_pre_flag_r_reg_0;\n wire ddr2_pre_flag_r_reg_1;\n wire ddr2_pre_flag_r_reg_2;\n wire ddr2_refresh_flag_r;\n wire ddr2_refresh_flag_r_reg_0;\n wire ddr3_lm_done_r;\n wire ddr3_lm_done_r_i_1_n_0;\n wire ddr3_lm_done_r_i_2_n_0;\n wire delay_done_r4_reg;\n wire detect_pi_found_dqs;\n wire detect_pi_found_dqs0;\n wire done_dqs_tap_inc;\n wire done_r_reg;\n wire \\dout_o_reg[0] ;\n wire \\dout_o_reg[0]_0 ;\n wire \\dout_o_reg[10] ;\n wire \\dout_o_reg[10]_0 ;\n wire \\dout_o_reg[11] ;\n wire \\dout_o_reg[11]_0 ;\n wire \\dout_o_reg[11]_1 ;\n wire \\dout_o_reg[11]_2 ;\n wire \\dout_o_reg[11]_3 ;\n wire \\dout_o_reg[11]_4 ;\n wire \\dout_o_reg[12] ;\n wire \\dout_o_reg[12]_0 ;\n wire \\dout_o_reg[13] ;\n wire \\dout_o_reg[13]_0 ;\n wire \\dout_o_reg[13]_1 ;\n wire \\dout_o_reg[13]_2 ;\n wire \\dout_o_reg[13]_3 ;\n wire \\dout_o_reg[13]_4 ;\n wire \\dout_o_reg[13]_5 ;\n wire \\dout_o_reg[13]_6 ;\n wire \\dout_o_reg[14] ;\n wire \\dout_o_reg[14]_0 ;\n wire \\dout_o_reg[14]_1 ;\n wire \\dout_o_reg[14]_2 ;\n wire \\dout_o_reg[15] ;\n wire \\dout_o_reg[15]_0 ;\n wire \\dout_o_reg[15]_1 ;\n wire \\dout_o_reg[15]_2 ;\n wire \\dout_o_reg[1] ;\n wire \\dout_o_reg[1]_0 ;\n wire \\dout_o_reg[2] ;\n wire \\dout_o_reg[2]_0 ;\n wire \\dout_o_reg[3] ;\n wire \\dout_o_reg[3]_0 ;\n wire \\dout_o_reg[4] ;\n wire \\dout_o_reg[4]_0 ;\n wire \\dout_o_reg[6] ;\n wire \\dout_o_reg[7] ;\n wire \\dout_o_reg[7]_0 ;\n wire \\dout_o_reg[7]_1 ;\n wire \\dout_o_reg[7]_2 ;\n wire \\dout_o_reg[8] ;\n wire \\dout_o_reg[8]_0 ;\n wire \\dout_o_reg[8]_1 ;\n wire \\dout_o_reg[8]_2 ;\n wire \\dout_o_reg[8]_3 ;\n wire \\dout_o_reg[8]_4 ;\n wire \\dout_o_reg[9] ;\n wire \\dout_o_reg[9]_0 ;\n wire \\dout_o_reg[9]_1 ;\n wire \\dout_o_reg[9]_2 ;\n wire \\dout_o_reg[9]_3 ;\n wire \\dout_o_reg[9]_4 ;\n wire [1:0]dqs_asrt_cnt;\n wire \\dqs_asrt_cnt[0]_i_1_n_0 ;\n wire \\dqs_asrt_cnt[1]_i_1_n_0 ;\n wire dqs_found_done_r_reg;\n wire dqs_found_done_r_reg_0;\n wire dqs_found_done_r_reg_1;\n wire dqs_found_done_r_reg_2;\n wire dqs_found_prech_req;\n wire dqs_found_start_r_reg;\n wire \\en_cnt_div4.enable_wrlvl_cnt[0]_i_1_n_0 ;\n wire \\en_cnt_div4.enable_wrlvl_cnt[1]_i_1_n_0 ;\n wire \\en_cnt_div4.enable_wrlvl_cnt[2]_i_1_n_0 ;\n wire \\en_cnt_div4.enable_wrlvl_cnt[3]_i_2_n_0 ;\n wire \\en_cnt_div4.enable_wrlvl_cnt[4]_i_1_n_0 ;\n wire \\en_cnt_div4.enable_wrlvl_cnt_reg[3]_0 ;\n wire \\en_cnt_div4.wrlvl_odt_i_1_n_0 ;\n wire \\en_cnt_div4.wrlvl_odt_i_2_n_0 ;\n wire [4:0]enable_wrlvl_cnt;\n wire enable_wrlvl_cnt0;\n wire first_rdlvl_pat_r;\n wire first_rdlvl_pat_r_i_1_n_0;\n wire first_rdlvl_pat_r_reg_0;\n wire first_wrcal_pat_r;\n wire first_wrcal_pat_r_i_1_n_0;\n wire first_wrcal_pat_r_i_2_n_0;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_1_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_5_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_6_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_7_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_1_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_1_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_4_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_1_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_7_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_10_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_1_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_9_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_1_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_4_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_5_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_7_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_8_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_9_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_1_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_5_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_6_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_7_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_8_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_11_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_13_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_1_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_9_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_11_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_12_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_1_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_13_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_15_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_16_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_17_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_18_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_1_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_1_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_1_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_4_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_5_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2_n_0 ;\n wire \\gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_1_n_0 ;\n wire [1:1]\\gen_rnk[0].mr1_r_reg[0]_196 ;\n wire init_calib_complete_reg_rep;\n wire init_calib_complete_reg_rep__0;\n wire init_calib_complete_reg_rep__1;\n wire init_calib_complete_reg_rep__10;\n wire init_calib_complete_reg_rep__11;\n wire init_calib_complete_reg_rep__12;\n wire init_calib_complete_reg_rep__13;\n wire init_calib_complete_reg_rep__14;\n wire init_calib_complete_reg_rep__2;\n wire init_calib_complete_reg_rep__3;\n wire init_calib_complete_reg_rep__4;\n wire init_calib_complete_reg_rep__5;\n wire init_calib_complete_reg_rep__6;\n wire init_calib_complete_reg_rep__7;\n wire init_calib_complete_reg_rep__8;\n wire init_calib_complete_reg_rep__9;\n wire init_complete_r1;\n wire init_complete_r1_reg_0;\n (* RTL_KEEP = \"true\" *) wire init_complete_r1_timing;\n wire init_complete_r2;\n (* RTL_KEEP = \"true\" *) wire init_complete_r_timing;\n wire init_dqsfound_done_r2;\n wire init_next_state1100_out;\n wire [6:0]init_state_r1;\n wire \\init_state_r[0]_i_10_n_0 ;\n wire \\init_state_r[0]_i_11_n_0 ;\n wire \\init_state_r[0]_i_13_n_0 ;\n wire \\init_state_r[0]_i_14_n_0 ;\n wire \\init_state_r[0]_i_15_n_0 ;\n wire \\init_state_r[0]_i_16_n_0 ;\n wire \\init_state_r[0]_i_17_n_0 ;\n wire \\init_state_r[0]_i_18_n_0 ;\n wire \\init_state_r[0]_i_19_n_0 ;\n wire \\init_state_r[0]_i_1_n_0 ;\n wire \\init_state_r[0]_i_20_n_0 ;\n wire \\init_state_r[0]_i_21_n_0 ;\n wire \\init_state_r[0]_i_22_n_0 ;\n wire \\init_state_r[0]_i_23_n_0 ;\n wire \\init_state_r[0]_i_24_n_0 ;\n wire \\init_state_r[0]_i_25_n_0 ;\n wire \\init_state_r[0]_i_26_n_0 ;\n wire \\init_state_r[0]_i_27_n_0 ;\n wire \\init_state_r[0]_i_28_n_0 ;\n wire \\init_state_r[0]_i_29_n_0 ;\n wire \\init_state_r[0]_i_2_n_0 ;\n wire \\init_state_r[0]_i_30_n_0 ;\n wire \\init_state_r[0]_i_31_n_0 ;\n wire \\init_state_r[0]_i_33_n_0 ;\n wire \\init_state_r[0]_i_34_n_0 ;\n wire \\init_state_r[0]_i_3_n_0 ;\n wire \\init_state_r[0]_i_40_n_0 ;\n wire \\init_state_r[0]_i_41_n_0 ;\n wire \\init_state_r[0]_i_42_n_0 ;\n wire \\init_state_r[0]_i_43_n_0 ;\n wire \\init_state_r[0]_i_45_n_0 ;\n wire \\init_state_r[0]_i_46_n_0 ;\n wire \\init_state_r[0]_i_51_n_0 ;\n wire \\init_state_r[0]_i_5_n_0 ;\n wire \\init_state_r[0]_i_6_n_0 ;\n wire \\init_state_r[0]_i_7_n_0 ;\n wire \\init_state_r[0]_i_8_n_0 ;\n wire \\init_state_r[0]_i_9_n_0 ;\n wire \\init_state_r[1]_i_10_n_0 ;\n wire \\init_state_r[1]_i_11_n_0 ;\n wire \\init_state_r[1]_i_12_n_0 ;\n wire \\init_state_r[1]_i_13_n_0 ;\n wire \\init_state_r[1]_i_15_n_0 ;\n wire \\init_state_r[1]_i_16_n_0 ;\n wire \\init_state_r[1]_i_17_n_0 ;\n wire \\init_state_r[1]_i_18_n_0 ;\n wire \\init_state_r[1]_i_19_n_0 ;\n wire \\init_state_r[1]_i_1_n_0 ;\n wire \\init_state_r[1]_i_20_n_0 ;\n wire \\init_state_r[1]_i_21_n_0 ;\n wire \\init_state_r[1]_i_22_n_0 ;\n wire \\init_state_r[1]_i_23_n_0 ;\n wire \\init_state_r[1]_i_24_n_0 ;\n wire \\init_state_r[1]_i_25_n_0 ;\n wire \\init_state_r[1]_i_26_n_0 ;\n wire \\init_state_r[1]_i_27_n_0 ;\n wire \\init_state_r[1]_i_28_n_0 ;\n wire \\init_state_r[1]_i_2_n_0 ;\n wire \\init_state_r[1]_i_33_n_0 ;\n wire \\init_state_r[1]_i_34_n_0 ;\n wire \\init_state_r[1]_i_35_n_0 ;\n wire \\init_state_r[1]_i_36_n_0 ;\n wire \\init_state_r[1]_i_37_n_0 ;\n wire \\init_state_r[1]_i_39_n_0 ;\n wire \\init_state_r[1]_i_3_n_0 ;\n wire \\init_state_r[1]_i_40_n_0 ;\n wire \\init_state_r[1]_i_41_n_0 ;\n wire \\init_state_r[1]_i_42_n_0 ;\n wire \\init_state_r[1]_i_43_n_0 ;\n wire \\init_state_r[1]_i_46_n_0 ;\n wire \\init_state_r[1]_i_47_n_0 ;\n wire \\init_state_r[1]_i_48_n_0 ;\n wire \\init_state_r[1]_i_5_n_0 ;\n wire \\init_state_r[1]_i_6_n_0 ;\n wire \\init_state_r[1]_i_7_n_0 ;\n wire \\init_state_r[1]_i_8_n_0 ;\n wire \\init_state_r[1]_i_9_n_0 ;\n wire \\init_state_r[2]_i_10_n_0 ;\n wire \\init_state_r[2]_i_11_n_0 ;\n wire \\init_state_r[2]_i_12_n_0 ;\n wire \\init_state_r[2]_i_14_n_0 ;\n wire \\init_state_r[2]_i_16_n_0 ;\n wire \\init_state_r[2]_i_17_n_0 ;\n wire \\init_state_r[2]_i_18_n_0 ;\n wire \\init_state_r[2]_i_1_n_0 ;\n wire \\init_state_r[2]_i_20_n_0 ;\n wire \\init_state_r[2]_i_21_n_0 ;\n wire \\init_state_r[2]_i_22_n_0 ;\n wire \\init_state_r[2]_i_24_n_0 ;\n wire \\init_state_r[2]_i_25_n_0 ;\n wire \\init_state_r[2]_i_26_n_0 ;\n wire \\init_state_r[2]_i_27_n_0 ;\n wire \\init_state_r[2]_i_2_n_0 ;\n wire \\init_state_r[2]_i_32_n_0 ;\n wire \\init_state_r[2]_i_33_n_0 ;\n wire \\init_state_r[2]_i_34_n_0 ;\n wire \\init_state_r[2]_i_35_n_0 ;\n wire \\init_state_r[2]_i_36_n_0 ;\n wire \\init_state_r[2]_i_37_n_0 ;\n wire \\init_state_r[2]_i_3_n_0 ;\n wire \\init_state_r[2]_i_4_n_0 ;\n wire \\init_state_r[2]_i_5_n_0 ;\n wire \\init_state_r[2]_i_6_n_0 ;\n wire \\init_state_r[2]_i_7_n_0 ;\n wire \\init_state_r[2]_i_8_n_0 ;\n wire \\init_state_r[2]_i_9_n_0 ;\n wire \\init_state_r[3]_i_10_n_0 ;\n wire \\init_state_r[3]_i_11_n_0 ;\n wire \\init_state_r[3]_i_13_n_0 ;\n wire \\init_state_r[3]_i_14_n_0 ;\n wire \\init_state_r[3]_i_15_n_0 ;\n wire \\init_state_r[3]_i_16_n_0 ;\n wire \\init_state_r[3]_i_17_n_0 ;\n wire \\init_state_r[3]_i_18_n_0 ;\n wire \\init_state_r[3]_i_19_n_0 ;\n wire \\init_state_r[3]_i_1_n_0 ;\n wire \\init_state_r[3]_i_20_n_0 ;\n wire \\init_state_r[3]_i_21_n_0 ;\n wire \\init_state_r[3]_i_22_n_0 ;\n wire \\init_state_r[3]_i_23_n_0 ;\n wire \\init_state_r[3]_i_24_n_0 ;\n wire \\init_state_r[3]_i_25_n_0 ;\n wire \\init_state_r[3]_i_2_n_0 ;\n wire \\init_state_r[3]_i_3_n_0 ;\n wire \\init_state_r[3]_i_4_n_0 ;\n wire \\init_state_r[3]_i_5_n_0 ;\n wire \\init_state_r[3]_i_6_n_0 ;\n wire \\init_state_r[3]_i_7_n_0 ;\n wire \\init_state_r[4]_i_10_n_0 ;\n wire \\init_state_r[4]_i_11_n_0 ;\n wire \\init_state_r[4]_i_12_n_0 ;\n wire \\init_state_r[4]_i_13_n_0 ;\n wire \\init_state_r[4]_i_15_n_0 ;\n wire \\init_state_r[4]_i_16_n_0 ;\n wire \\init_state_r[4]_i_17_n_0 ;\n wire \\init_state_r[4]_i_18_n_0 ;\n wire \\init_state_r[4]_i_19_n_0 ;\n wire \\init_state_r[4]_i_1_n_0 ;\n wire \\init_state_r[4]_i_20_n_0 ;\n wire \\init_state_r[4]_i_21_n_0 ;\n wire \\init_state_r[4]_i_22_n_0 ;\n wire \\init_state_r[4]_i_26_n_0 ;\n wire \\init_state_r[4]_i_27_n_0 ;\n wire \\init_state_r[4]_i_28_n_0 ;\n wire \\init_state_r[4]_i_29_n_0 ;\n wire \\init_state_r[4]_i_2_n_0 ;\n wire \\init_state_r[4]_i_30_n_0 ;\n wire \\init_state_r[4]_i_31_n_0 ;\n wire \\init_state_r[4]_i_32_n_0 ;\n wire \\init_state_r[4]_i_33_n_0 ;\n wire \\init_state_r[4]_i_37_n_0 ;\n wire \\init_state_r[4]_i_38_n_0 ;\n wire \\init_state_r[4]_i_39_n_0 ;\n wire \\init_state_r[4]_i_3_n_0 ;\n wire \\init_state_r[4]_i_40_n_0 ;\n wire \\init_state_r[4]_i_4_n_0 ;\n wire \\init_state_r[4]_i_5_n_0 ;\n wire \\init_state_r[4]_i_6_n_0 ;\n wire \\init_state_r[4]_i_7_n_0 ;\n wire \\init_state_r[4]_i_8_n_0 ;\n wire \\init_state_r[4]_i_9_n_0 ;\n wire \\init_state_r[5]_i_10_n_0 ;\n wire \\init_state_r[5]_i_11_n_0 ;\n wire \\init_state_r[5]_i_12_n_0 ;\n wire \\init_state_r[5]_i_13_n_0 ;\n wire \\init_state_r[5]_i_14_n_0 ;\n wire \\init_state_r[5]_i_15_n_0 ;\n wire \\init_state_r[5]_i_16_n_0 ;\n wire \\init_state_r[5]_i_17_n_0 ;\n wire \\init_state_r[5]_i_18_n_0 ;\n wire \\init_state_r[5]_i_19_n_0 ;\n wire \\init_state_r[5]_i_1_n_0 ;\n wire \\init_state_r[5]_i_20_n_0 ;\n wire \\init_state_r[5]_i_21_n_0 ;\n wire \\init_state_r[5]_i_22_n_0 ;\n wire \\init_state_r[5]_i_23_n_0 ;\n wire \\init_state_r[5]_i_24_n_0 ;\n wire \\init_state_r[5]_i_25_n_0 ;\n wire \\init_state_r[5]_i_26_n_0 ;\n wire \\init_state_r[5]_i_27_n_0 ;\n wire \\init_state_r[5]_i_29_n_0 ;\n wire \\init_state_r[5]_i_2_n_0 ;\n wire \\init_state_r[5]_i_31_n_0 ;\n wire \\init_state_r[5]_i_32_n_0 ;\n wire \\init_state_r[5]_i_33_n_0 ;\n wire \\init_state_r[5]_i_34_n_0 ;\n wire \\init_state_r[5]_i_35_n_0 ;\n wire \\init_state_r[5]_i_36_n_0 ;\n wire \\init_state_r[5]_i_38_n_0 ;\n wire \\init_state_r[5]_i_39_n_0 ;\n wire \\init_state_r[5]_i_3_n_0 ;\n wire \\init_state_r[5]_i_40_n_0 ;\n wire \\init_state_r[5]_i_41_n_0 ;\n wire \\init_state_r[5]_i_42_n_0 ;\n wire \\init_state_r[5]_i_43_n_0 ;\n wire \\init_state_r[5]_i_44_n_0 ;\n wire \\init_state_r[5]_i_45_n_0 ;\n wire \\init_state_r[5]_i_48_n_0 ;\n wire \\init_state_r[5]_i_49_n_0 ;\n wire \\init_state_r[5]_i_4_n_0 ;\n wire \\init_state_r[5]_i_50_n_0 ;\n wire \\init_state_r[5]_i_51_n_0 ;\n wire \\init_state_r[5]_i_52_n_0 ;\n wire \\init_state_r[5]_i_53_n_0 ;\n wire \\init_state_r[5]_i_54_n_0 ;\n wire \\init_state_r[5]_i_56_n_0 ;\n wire \\init_state_r[5]_i_57_n_0 ;\n wire \\init_state_r[5]_i_58_n_0 ;\n wire \\init_state_r[5]_i_5_n_0 ;\n wire \\init_state_r[5]_i_60_n_0 ;\n wire \\init_state_r[5]_i_61_n_0 ;\n wire \\init_state_r[5]_i_62_n_0 ;\n wire \\init_state_r[5]_i_6_n_0 ;\n wire \\init_state_r[5]_i_7_n_0 ;\n wire \\init_state_r[5]_i_8_n_0 ;\n wire \\init_state_r[5]_i_9_n_0 ;\n wire \\init_state_r[6]_i_10_n_0 ;\n wire \\init_state_r[6]_i_11_n_0 ;\n wire \\init_state_r[6]_i_12_n_0 ;\n wire \\init_state_r[6]_i_13_n_0 ;\n wire \\init_state_r[6]_i_14_n_0 ;\n wire \\init_state_r[6]_i_15_n_0 ;\n wire \\init_state_r[6]_i_16_n_0 ;\n wire \\init_state_r[6]_i_17_n_0 ;\n wire \\init_state_r[6]_i_18_n_0 ;\n wire \\init_state_r[6]_i_19_n_0 ;\n wire \\init_state_r[6]_i_1_n_0 ;\n wire \\init_state_r[6]_i_20_n_0 ;\n wire \\init_state_r[6]_i_21_n_0 ;\n wire \\init_state_r[6]_i_22_n_0 ;\n wire \\init_state_r[6]_i_2_n_0 ;\n wire \\init_state_r[6]_i_3_n_0 ;\n wire \\init_state_r[6]_i_4_n_0 ;\n wire \\init_state_r[6]_i_5_n_0 ;\n wire \\init_state_r[6]_i_7_n_0 ;\n wire \\init_state_r[6]_i_8_n_0 ;\n wire \\init_state_r[6]_i_9_n_0 ;\n wire \\init_state_r_reg[0]_0 ;\n wire \\init_state_r_reg[0]_1 ;\n wire \\init_state_r_reg[1]_0 ;\n wire \\init_state_r_reg[1]_1 ;\n wire \\init_state_r_reg[2]_0 ;\n wire \\init_state_r_reg[2]_1 ;\n wire \\init_state_r_reg[2]_2 ;\n wire \\init_state_r_reg[4]_0 ;\n wire \\init_state_r_reg[5]_0 ;\n wire \\init_state_r_reg[6]_0 ;\n wire \\init_state_r_reg[6]_1 ;\n wire \\init_state_r_reg_n_0_[3] ;\n wire lim2init_prech_req;\n wire lim_start_r_reg;\n wire mask_lim_done;\n wire mask_lim_done_i_1_n_0;\n wire \\mcGo_r_reg[15] ;\n wire [0:0]mc_cas_n;\n wire [0:0]mc_cke;\n wire [1:0]mc_cmd;\n wire [0:0]mc_odt;\n wire [0:0]mc_ras_n;\n wire [0:0]mc_we_n;\n wire mc_wrdata_en;\n wire mem_init_done_r;\n wire mem_init_done_r_i_1_n_0;\n wire [1:0]mem_init_done_r_reg_0;\n wire mem_init_done_r_reg_1;\n wire mem_init_done_r_reg_2;\n wire [1:0]mem_out;\n wire mpr_end_if_reset;\n wire mpr_end_if_reset0;\n wire mpr_last_byte_done;\n wire mpr_rdlvl_done_r_reg;\n wire mpr_rdlvl_done_r_reg_0;\n wire mpr_rdlvl_done_r_reg_1;\n wire mpr_rdlvl_done_r_reg_2;\n wire mpr_rdlvl_start_i_1_n_0;\n wire mpr_rdlvl_start_i_2_n_0;\n wire mpr_rdlvl_start_r;\n wire mpr_rdlvl_start_r_reg;\n wire mux_cmd_wren;\n wire mux_reset_n;\n wire mux_wrdata_en;\n wire \\my_empty_reg[1] ;\n wire \\my_empty_reg[1]_0 ;\n wire \\my_empty_reg[1]_1 ;\n wire \\my_empty_reg[1]_2 ;\n wire \\my_empty_reg[1]_3 ;\n wire \\my_empty_reg[1]_4 ;\n wire \\my_empty_reg[1]_5 ;\n wire \\my_empty_reg[1]_6 ;\n wire [3:0]\\my_empty_reg[7] ;\n wire [3:0]\\my_empty_reg[7]_0 ;\n wire [3:0]\\my_empty_reg[7]_1 ;\n wire [7:0]\\my_empty_reg[7]_10 ;\n wire [7:0]\\my_empty_reg[7]_11 ;\n wire [7:0]\\my_empty_reg[7]_12 ;\n wire [7:0]\\my_empty_reg[7]_13 ;\n wire [7:0]\\my_empty_reg[7]_14 ;\n wire [7:0]\\my_empty_reg[7]_15 ;\n wire [7:0]\\my_empty_reg[7]_16 ;\n wire [7:0]\\my_empty_reg[7]_17 ;\n wire [7:0]\\my_empty_reg[7]_18 ;\n wire [7:0]\\my_empty_reg[7]_19 ;\n wire [3:0]\\my_empty_reg[7]_2 ;\n wire [7:0]\\my_empty_reg[7]_20 ;\n wire [7:0]\\my_empty_reg[7]_21 ;\n wire [7:0]\\my_empty_reg[7]_22 ;\n wire [7:0]\\my_empty_reg[7]_23 ;\n wire [7:0]\\my_empty_reg[7]_24 ;\n wire [7:0]\\my_empty_reg[7]_25 ;\n wire [7:0]\\my_empty_reg[7]_26 ;\n wire [7:0]\\my_empty_reg[7]_27 ;\n wire [7:0]\\my_empty_reg[7]_28 ;\n wire [7:0]\\my_empty_reg[7]_29 ;\n wire [3:0]\\my_empty_reg[7]_3 ;\n wire [7:0]\\my_empty_reg[7]_30 ;\n wire [7:0]\\my_empty_reg[7]_31 ;\n wire [7:0]\\my_empty_reg[7]_32 ;\n wire [7:0]\\my_empty_reg[7]_33 ;\n wire [7:0]\\my_empty_reg[7]_34 ;\n wire [7:0]\\my_empty_reg[7]_35 ;\n wire [7:0]\\my_empty_reg[7]_36 ;\n wire [7:0]\\my_empty_reg[7]_37 ;\n wire [63:0]\\my_empty_reg[7]_38 ;\n wire [63:0]\\my_empty_reg[7]_39 ;\n wire [3:0]\\my_empty_reg[7]_4 ;\n wire [63:0]\\my_empty_reg[7]_40 ;\n wire [63:0]\\my_empty_reg[7]_41 ;\n wire [3:0]\\my_empty_reg[7]_5 ;\n wire [7:0]\\my_empty_reg[7]_6 ;\n wire [7:0]\\my_empty_reg[7]_7 ;\n wire [7:0]\\my_empty_reg[7]_8 ;\n wire [7:0]\\my_empty_reg[7]_9 ;\n wire [1:0]\\my_full_reg[3] ;\n wire new_cnt_dqs_r_reg;\n wire [2:0]num_reads;\n wire num_reads0;\n wire num_refresh0;\n wire \\num_refresh[3]_i_1_n_0 ;\n wire \\num_refresh[3]_i_4_n_0 ;\n wire \\num_refresh[3]_i_5_n_0 ;\n wire \\num_refresh[3]_i_6_n_0 ;\n wire [3:0]num_refresh_reg__0;\n wire num_samples_done_r;\n wire \\ocal_act_wait_cnt[3]_i_1_n_0 ;\n wire \\ocal_act_wait_cnt[3]_i_3_n_0 ;\n wire [3:0]ocal_act_wait_cnt_reg__0;\n wire ocal_last_byte_done;\n wire ocd_prech_req;\n wire oclk_calib_resume_level;\n wire oclk_calib_resume_level_i_1_n_0;\n wire oclk_calib_resume_level_reg_0;\n wire oclk_calib_resume_r_reg;\n wire oclk_calib_resume_r_reg_0;\n wire [3:2]oclk_wr_cnt0;\n wire \\oclk_wr_cnt[0]_i_1_n_0 ;\n wire \\oclk_wr_cnt[1]_i_1_n_0 ;\n wire \\oclk_wr_cnt[3]_i_1_n_0 ;\n wire \\oclk_wr_cnt[3]_i_4_n_0 ;\n wire [3:0]oclk_wr_cnt_reg__0;\n wire oclkdelay_calib_done_r_reg;\n wire oclkdelay_calib_done_r_reg_0;\n wire oclkdelay_calib_done_r_reg_1;\n wire oclkdelay_calib_done_r_reg_2;\n wire oclkdelay_calib_done_r_reg_3;\n wire oclkdelay_calib_done_r_reg_4;\n wire oclkdelay_calib_done_r_reg_5;\n wire oclkdelay_calib_start_int_i_1_n_0;\n wire oclkdelay_calib_start_pre;\n wire oclkdelay_center_calib_done_r_reg;\n wire oclkdelay_center_calib_done_r_reg_0;\n wire oclkdelay_center_calib_start_r_reg;\n wire oclkdelay_center_calib_start_r_reg_0;\n wire oclkdelay_int_ref_req0;\n wire oclkdelay_int_ref_req_i_1_n_0;\n wire oclkdelay_int_ref_req_i_2_n_0;\n wire oclkdelay_int_ref_req_i_3_n_0;\n wire oclkdelay_int_ref_req_i_5_n_0;\n wire oclkdelay_int_ref_req_reg_0;\n wire \\oclkdelay_ref_cnt[0]_i_1_n_0 ;\n wire \\oclkdelay_ref_cnt[0]_i_4_n_0 ;\n wire \\oclkdelay_ref_cnt[0]_i_5_n_0 ;\n wire \\oclkdelay_ref_cnt[0]_i_6_n_0 ;\n wire \\oclkdelay_ref_cnt[0]_i_7_n_0 ;\n wire \\oclkdelay_ref_cnt[12]_i_2_n_0 ;\n wire \\oclkdelay_ref_cnt[12]_i_3_n_0 ;\n wire \\oclkdelay_ref_cnt[4]_i_2_n_0 ;\n wire \\oclkdelay_ref_cnt[4]_i_3_n_0 ;\n wire \\oclkdelay_ref_cnt[4]_i_4_n_0 ;\n wire \\oclkdelay_ref_cnt[4]_i_5_n_0 ;\n wire \\oclkdelay_ref_cnt[8]_i_2_n_0 ;\n wire \\oclkdelay_ref_cnt[8]_i_3_n_0 ;\n wire \\oclkdelay_ref_cnt[8]_i_4_n_0 ;\n wire \\oclkdelay_ref_cnt[8]_i_5_n_0 ;\n wire [13:0]oclkdelay_ref_cnt_reg;\n wire \\oclkdelay_ref_cnt_reg[0]_i_2_n_0 ;\n wire \\oclkdelay_ref_cnt_reg[0]_i_2_n_1 ;\n wire \\oclkdelay_ref_cnt_reg[0]_i_2_n_2 ;\n wire \\oclkdelay_ref_cnt_reg[0]_i_2_n_3 ;\n wire \\oclkdelay_ref_cnt_reg[0]_i_2_n_4 ;\n wire \\oclkdelay_ref_cnt_reg[0]_i_2_n_5 ;\n wire \\oclkdelay_ref_cnt_reg[0]_i_2_n_6 ;\n wire \\oclkdelay_ref_cnt_reg[0]_i_2_n_7 ;\n wire \\oclkdelay_ref_cnt_reg[12]_i_1_n_3 ;\n wire \\oclkdelay_ref_cnt_reg[12]_i_1_n_6 ;\n wire \\oclkdelay_ref_cnt_reg[12]_i_1_n_7 ;\n wire \\oclkdelay_ref_cnt_reg[13]_0 ;\n wire \\oclkdelay_ref_cnt_reg[4]_i_1_n_0 ;\n wire \\oclkdelay_ref_cnt_reg[4]_i_1_n_1 ;\n wire \\oclkdelay_ref_cnt_reg[4]_i_1_n_2 ;\n wire \\oclkdelay_ref_cnt_reg[4]_i_1_n_3 ;\n wire \\oclkdelay_ref_cnt_reg[4]_i_1_n_4 ;\n wire \\oclkdelay_ref_cnt_reg[4]_i_1_n_5 ;\n wire \\oclkdelay_ref_cnt_reg[4]_i_1_n_6 ;\n wire \\oclkdelay_ref_cnt_reg[4]_i_1_n_7 ;\n wire \\oclkdelay_ref_cnt_reg[8]_i_1_n_0 ;\n wire \\oclkdelay_ref_cnt_reg[8]_i_1_n_1 ;\n wire \\oclkdelay_ref_cnt_reg[8]_i_1_n_2 ;\n wire \\oclkdelay_ref_cnt_reg[8]_i_1_n_3 ;\n wire \\oclkdelay_ref_cnt_reg[8]_i_1_n_4 ;\n wire \\oclkdelay_ref_cnt_reg[8]_i_1_n_5 ;\n wire \\oclkdelay_ref_cnt_reg[8]_i_1_n_6 ;\n wire \\oclkdelay_ref_cnt_reg[8]_i_1_n_7 ;\n wire [5:5]oclkdelay_start_dly_r;\n wire \\oclkdelay_start_dly_r_reg[4]_srl5_n_0 ;\n wire \\odd_cwl.phy_cas_n[1]_i_1_n_0 ;\n wire \\odd_cwl.phy_cas_n_reg[1]_0 ;\n wire \\odd_cwl.phy_ras_n[1]_i_1_n_0 ;\n wire \\odd_cwl.phy_ras_n[1]_i_2_n_0 ;\n wire \\odd_cwl.phy_we_n[1]_i_1_n_0 ;\n wire \\one_rank.stg1_wr_done_i_1_n_0 ;\n wire \\one_rank.stg1_wr_done_reg_0 ;\n wire \\one_rank_complex.complex_wr_done_i_1_n_0 ;\n wire \\one_rank_complex.complex_wr_done_i_2_n_0 ;\n wire \\one_rank_complex.complex_wr_done_i_3_n_0 ;\n wire \\one_rank_complex.complex_wr_done_i_4_n_0 ;\n wire \\one_rank_complex.complex_wr_done_i_5_n_0 ;\n wire p_0_in0_in;\n wire [9:0]p_0_in__0;\n wire [8:0]p_0_in__0__0;\n wire [7:0]p_0_in__1;\n wire [3:1]p_0_in__2;\n wire [7:0]p_0_in__3;\n wire [3:0]p_0_in__4;\n wire [7:0]p_0_in__5;\n wire [3:0]p_0_in__6;\n wire [4:0]p_0_in__7;\n wire [3:0]p_0_in__8;\n wire [3:0]p_0_in__9;\n wire p_81_in;\n wire [11:9]phy_bank;\n wire [1:1]phy_cas_n;\n wire [1:1]phy_cs_n;\n wire [10:0]\\phy_ctl_wd_i1_reg[24] ;\n wire [31:0]phy_dout;\n wire phy_if_empty_r_reg;\n wire [1:1]phy_ras_n;\n wire phy_rddata_en_1;\n wire phy_read_calib;\n wire phy_reset_n;\n wire [1:1]phy_we_n;\n wire [255:24]phy_wrdata;\n wire phy_wrdata_en;\n wire phy_write_calib;\n wire pi_calib_done;\n wire pi_calib_done_r;\n wire pi_calib_done_r_i_1_n_0;\n wire pi_calib_rank_done_r;\n wire \\pi_dqs_found_all_bank_reg[1] ;\n wire [0:0]\\pi_dqs_found_all_bank_reg[1]_0 ;\n wire pi_dqs_found_done_r1;\n wire pi_dqs_found_done_r1_reg_0;\n wire pi_dqs_found_done_r1_reg_1;\n wire pi_dqs_found_done_r1_reg_2;\n wire pi_dqs_found_done_r1_reg_3;\n wire pi_dqs_found_done_r1_reg_4;\n wire pi_dqs_found_done_r1_reg_5;\n wire pi_dqs_found_done_r1_reg_6;\n wire pi_dqs_found_done_r1_reg_7;\n wire pi_dqs_found_rank_done;\n wire pi_dqs_found_start_i_1_n_0;\n (* async_reg = \"true\" *) wire pi_phase_locked_all_r1;\n (* async_reg = \"true\" *) wire pi_phase_locked_all_r2;\n (* async_reg = \"true\" *) wire pi_phase_locked_all_r3;\n (* async_reg = \"true\" *) wire pi_phase_locked_all_r4;\n wire prbs_gen_clk_en;\n wire prbs_gen_clk_en040_out;\n wire prbs_gen_clk_en_i_1_n_0;\n wire prbs_gen_clk_en_i_2_n_0;\n wire prbs_gen_clk_en_i_3_n_0;\n wire prbs_gen_clk_en_i_5_n_0;\n wire prbs_gen_oclk_clk_en;\n wire prbs_gen_oclk_clk_en_i_1_n_0;\n wire prbs_gen_oclk_clk_en_i_2_n_0;\n wire prbs_gen_oclk_clk_en_i_3_n_0;\n wire prbs_gen_oclk_clk_en_i_4_n_0;\n wire prbs_gen_oclk_clk_en_i_5_n_0;\n wire prbs_gen_oclk_clk_en_i_6_n_0;\n wire prbs_gen_oclk_clk_en_i_7_n_0;\n wire prbs_gen_oclk_clk_en_i_8_n_0;\n wire prbs_gen_oclk_clk_en_i_9_n_0;\n wire prbs_last_byte_done;\n wire prbs_last_byte_done_r;\n wire prbs_last_byte_done_reg;\n wire prbs_rdlvl_done_pulse;\n wire prbs_rdlvl_done_pulse0;\n wire prbs_rdlvl_done_r1;\n wire prbs_rdlvl_done_r2;\n wire prbs_rdlvl_done_r3;\n wire prbs_rdlvl_done_reg;\n wire prbs_rdlvl_done_reg_0;\n wire prbs_rdlvl_done_reg_rep;\n wire prbs_rdlvl_done_reg_rep_0;\n wire prbs_rdlvl_done_reg_rep_1;\n wire prbs_rdlvl_done_reg_rep_2;\n wire prbs_rdlvl_done_reg_rep_3;\n wire prbs_rdlvl_prech_req_reg;\n wire prbs_rdlvl_start_i_1_n_0;\n wire prbs_rdlvl_start_i_2_n_0;\n wire prbs_rdlvl_start_i_3_n_0;\n wire prbs_rdlvl_start_r;\n wire prbs_rdlvl_start_r_reg;\n wire prech_done;\n wire \\prech_done_dly_r_reg[15]_srl16_n_0 ;\n wire prech_done_pre;\n wire prech_done_r2;\n wire prech_done_r3;\n wire prech_pending_r;\n wire prech_pending_r_i_3_n_0;\n wire prech_pending_r_i_4_n_0;\n wire prech_pending_r_i_5_n_0;\n wire prech_pending_r_i_6_n_0;\n wire prech_pending_r_i_7_n_0;\n wire prech_pending_r_i_8_n_0;\n wire prech_pending_r_i_9_n_0;\n wire prech_pending_r_reg_0;\n wire prech_pending_r_reg_1;\n wire prech_req;\n wire prech_req_posedge_r0;\n wire prech_req_posedge_r_i_2_n_0;\n wire prech_req_posedge_r_reg_0;\n wire prech_req_r;\n wire pwron_ce_r;\n wire pwron_ce_r_i_2_n_0;\n wire pwron_ce_r_i_3_n_0;\n wire [1:0]\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3] ;\n wire [1:0]\\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] ;\n wire [0:0]\\rd_addr_reg[0] ;\n wire [0:0]\\rd_addr_reg[3] ;\n wire \\rd_addr_reg_rep[7] ;\n wire [1:0]\\rd_byte_data_offset_reg[0][3] ;\n wire [1:0]\\rd_byte_data_offset_reg[0][9] ;\n wire [33:0]\\rd_ptr_reg[3] ;\n wire [7:0]\\rd_ptr_reg[3]_0 ;\n wire [31:0]\\rd_ptr_reg[3]_1 ;\n wire [63:0]\\rd_ptr_reg[3]_2 ;\n wire [63:0]\\rd_ptr_reg[3]_3 ;\n wire [63:0]\\rd_ptr_reg[3]_4 ;\n wire [63:0]\\rd_ptr_reg[3]_5 ;\n wire [33:0]\\rd_ptr_timing_reg[0] ;\n wire [7:0]\\rd_ptr_timing_reg[0]_0 ;\n wire [7:0]\\rd_ptr_timing_reg[0]_1 ;\n wire [3:0]\\rd_ptr_timing_reg[0]_2 ;\n wire [1:0]\\rd_ptr_timing_reg[0]_3 ;\n wire \\rd_victim_sel_reg[0] ;\n wire \\rd_victim_sel_reg[1] ;\n wire \\rd_victim_sel_reg[2] ;\n wire rdlvl_last_byte_done;\n wire rdlvl_last_byte_done_r;\n wire rdlvl_pi_incdec;\n wire rdlvl_prech_req;\n wire [0:0]rdlvl_start_dly0_r;\n wire \\rdlvl_start_dly0_r_reg[13]_srl14_n_0 ;\n wire \\rdlvl_start_dly0_r_reg[14]_0 ;\n wire rdlvl_start_pre;\n wire rdlvl_start_pre_reg_0;\n wire rdlvl_stg1_done_int_reg;\n wire rdlvl_stg1_done_int_reg_0;\n wire rdlvl_stg1_done_int_reg_1;\n wire rdlvl_stg1_done_int_reg_2;\n wire rdlvl_stg1_done_int_reg_3;\n wire rdlvl_stg1_done_int_reg_4;\n wire rdlvl_stg1_done_r1;\n wire rdlvl_stg1_rank_done;\n wire rdlvl_stg1_start_int;\n wire rdlvl_stg1_start_int_i_1_n_0;\n wire rdlvl_stg1_start_int_i_2_n_0;\n wire rdlvl_stg1_start_r_reg;\n wire read_calib_i_1_n_0;\n wire read_calib_i_2_n_0;\n wire read_calib_reg_0;\n wire reg_ctrl_cnt_r;\n wire \\reg_ctrl_cnt_r[0]_i_1_n_0 ;\n wire \\reg_ctrl_cnt_r_reg[3]_0 ;\n wire [3:0]reg_ctrl_cnt_r_reg__0;\n wire reset_if;\n wire reset_if_i_2_n_0;\n wire reset_if_r9;\n wire reset_if_reg;\n wire reset_rd_addr;\n wire reset_rd_addr0;\n wire reset_rd_addr_r1;\n wire \\row_cnt_victim_rotate.complex_row_cnt[0]_i_1_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt[1]_i_1_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt[2]_i_1_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt[3]_i_1_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt[4]_i_10_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt[4]_i_3_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt[4]_i_7_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt[5]_i_1_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt[6]_i_1_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt_reg[4]_0 ;\n wire \\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ;\n wire \\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ;\n wire \\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ;\n wire \\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ;\n wire \\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ;\n wire \\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ;\n wire \\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ;\n wire \\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ;\n wire rstdiv0_sync_r1_reg_rep__10;\n wire [0:0]rstdiv0_sync_r1_reg_rep__11;\n wire rstdiv0_sync_r1_reg_rep__12;\n wire [0:0]rstdiv0_sync_r1_reg_rep__18;\n wire [0:0]rstdiv0_sync_r1_reg_rep__19;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__23;\n wire rstdiv0_sync_r1_reg_rep__24;\n wire rstdiv0_sync_r1_reg_rep__24_0;\n wire rstdiv0_sync_r1_reg_rep__24_1;\n wire rstdiv0_sync_r1_reg_rep__25;\n wire [0:0]\\samples_cnt_r_reg[11] ;\n wire \\samples_cnt_r_reg[11]_0 ;\n wire stg1_wr_done;\n wire \\stg1_wr_rd_cnt[0]_i_1_n_0 ;\n wire \\stg1_wr_rd_cnt[1]_i_1_n_0 ;\n wire \\stg1_wr_rd_cnt[2]_i_1_n_0 ;\n wire \\stg1_wr_rd_cnt[3]_i_1_n_0 ;\n wire \\stg1_wr_rd_cnt[3]_i_2_n_0 ;\n wire \\stg1_wr_rd_cnt[4]_i_1_n_0 ;\n wire \\stg1_wr_rd_cnt[4]_i_3_n_0 ;\n wire \\stg1_wr_rd_cnt[4]_i_4_n_0 ;\n wire \\stg1_wr_rd_cnt[4]_i_5_n_0 ;\n wire \\stg1_wr_rd_cnt[4]_i_6_n_0 ;\n wire \\stg1_wr_rd_cnt[5]_i_1_n_0 ;\n wire \\stg1_wr_rd_cnt[5]_i_2_n_0 ;\n wire \\stg1_wr_rd_cnt[6]_i_1_n_0 ;\n wire \\stg1_wr_rd_cnt[6]_i_2_n_0 ;\n wire \\stg1_wr_rd_cnt[7]_i_1_n_0 ;\n wire \\stg1_wr_rd_cnt[8]_i_1_n_0 ;\n wire \\stg1_wr_rd_cnt[8]_i_2_n_0 ;\n wire \\stg1_wr_rd_cnt[8]_i_3_n_0 ;\n wire \\stg1_wr_rd_cnt[8]_i_4_n_0 ;\n wire \\stg1_wr_rd_cnt[8]_i_5_n_0 ;\n wire \\stg1_wr_rd_cnt[8]_i_6_n_0 ;\n wire \\stg1_wr_rd_cnt_reg_n_0_[0] ;\n wire \\stg1_wr_rd_cnt_reg_n_0_[1] ;\n wire \\stg1_wr_rd_cnt_reg_n_0_[2] ;\n wire \\stg1_wr_rd_cnt_reg_n_0_[3] ;\n wire \\stg1_wr_rd_cnt_reg_n_0_[4] ;\n wire \\stg1_wr_rd_cnt_reg_n_0_[5] ;\n wire \\stg1_wr_rd_cnt_reg_n_0_[6] ;\n wire \\stg1_wr_rd_cnt_reg_n_0_[7] ;\n wire \\stg1_wr_rd_cnt_reg_n_0_[8] ;\n wire temp_lmr_done;\n wire \\victim_sel[0]_i_1_n_0 ;\n wire \\victim_sel[0]_i_2_n_0 ;\n wire \\victim_sel[1]_i_1_n_0 ;\n wire \\victim_sel[1]_i_2_n_0 ;\n wire \\victim_sel[2]_i_1_n_0 ;\n wire \\victim_sel[2]_i_2_n_0 ;\n wire \\victim_sel[2]_i_3_n_0 ;\n wire \\victim_sel[2]_i_4_n_0 ;\n wire \\victim_sel[2]_i_5_n_0 ;\n wire \\victim_sel_reg_n_0_[0] ;\n wire \\victim_sel_reg_n_0_[1] ;\n wire \\victim_sel_reg_n_0_[2] ;\n wire [7:0]\\victim_sel_rotate.sel_reg[31] ;\n wire wl_sm_start;\n wire \\wr_done_victim_rotate.complex_row0_wr_done_i_1_n_0 ;\n wire \\wr_done_victim_rotate.complex_row1_wr_done_i_1_n_0 ;\n wire wr_level_done_reg;\n wire wr_level_dqs_asrt;\n wire wr_level_dqs_asrt_i_1_n_0;\n wire wr_level_dqs_asrt_r1;\n wire wr_level_start_r_reg;\n wire wr_lvl_start_i_1_n_0;\n wire wr_victim_inc;\n wire wr_victim_inc0;\n wire wr_victim_inc_i_2_n_0;\n wire wr_victim_inc_i_3_n_0;\n wire [2:0]wr_victim_sel;\n wire \\wr_victim_sel[0]_i_1_n_0 ;\n wire \\wr_victim_sel[1]_i_1_n_0 ;\n wire \\wr_victim_sel[2]_i_1_n_0 ;\n wire [2:0]wr_victim_sel_ocal;\n wire \\wr_victim_sel_ocal[0]_i_1_n_0 ;\n wire \\wr_victim_sel_ocal[1]_i_1_n_0 ;\n wire \\wr_victim_sel_ocal[2]_i_1_n_0 ;\n wire wrcal_done_reg;\n wire wrcal_done_reg_0;\n wire wrcal_done_reg_1;\n wire wrcal_done_reg_10;\n wire wrcal_done_reg_11;\n wire wrcal_done_reg_2;\n wire wrcal_done_reg_3;\n wire wrcal_done_reg_4;\n wire wrcal_done_reg_5;\n wire wrcal_done_reg_6;\n wire wrcal_done_reg_7;\n wire wrcal_done_reg_8;\n wire wrcal_done_reg_9;\n wire \\wrcal_dqs_cnt_r_reg[0] ;\n wire wrcal_final_chk;\n wire wrcal_final_chk_i_1_n_0;\n wire wrcal_final_chk_i_2_n_0;\n wire wrcal_prech_req;\n wire wrcal_rd_wait;\n wire wrcal_rd_wait_i_1_n_0;\n wire wrcal_reads;\n wire wrcal_reads05_out;\n wire \\wrcal_reads[0]_i_1_n_0 ;\n wire \\wrcal_reads[1]_i_1_n_0 ;\n wire \\wrcal_reads[2]_i_1_n_0 ;\n wire \\wrcal_reads[3]_i_1_n_0 ;\n wire \\wrcal_reads[4]_i_1_n_0 ;\n wire \\wrcal_reads[5]_i_1_n_0 ;\n wire \\wrcal_reads[5]_i_2_n_0 ;\n wire \\wrcal_reads[6]_i_1_n_0 ;\n wire \\wrcal_reads[7]_i_2_n_0 ;\n wire \\wrcal_reads[7]_i_3_n_0 ;\n wire \\wrcal_reads[7]_i_5_n_0 ;\n wire \\wrcal_reads[7]_i_6_n_0 ;\n wire \\wrcal_reads[7]_i_7_n_0 ;\n wire \\wrcal_reads_reg_n_0_[0] ;\n wire \\wrcal_reads_reg_n_0_[1] ;\n wire \\wrcal_reads_reg_n_0_[2] ;\n wire \\wrcal_reads_reg_n_0_[3] ;\n wire \\wrcal_reads_reg_n_0_[4] ;\n wire \\wrcal_reads_reg_n_0_[5] ;\n wire \\wrcal_reads_reg_n_0_[6] ;\n wire \\wrcal_reads_reg_n_0_[7] ;\n wire wrcal_resume_r;\n wire wrcal_resume_w;\n wire wrcal_sanity_chk;\n wire wrcal_sanity_chk_done_reg;\n wire wrcal_sanity_chk_done_reg_0;\n wire wrcal_sanity_chk_r_reg;\n wire [5:5]wrcal_start_dly_r;\n wire \\wrcal_start_dly_r_reg[4]_srl5_n_0 ;\n wire wrcal_start_i_1_n_0;\n wire wrcal_start_pre;\n wire wrcal_start_reg_0;\n wire [3:2]wrcal_wr_cnt0;\n wire \\wrcal_wr_cnt[0]_i_1_n_0 ;\n wire \\wrcal_wr_cnt[1]_i_1_n_0 ;\n wire \\wrcal_wr_cnt[3]_i_1_n_0 ;\n wire \\wrcal_wr_cnt[3]_i_2_n_0 ;\n wire \\wrcal_wr_cnt[3]_i_4_n_0 ;\n wire [3:0]wrcal_wr_cnt_reg__0;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata[250]_i_1_n_0 ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata[254]_i_2_n_0 ;\n wire [255:0]\\write_buffer.wr_buf_out_data_reg[255] ;\n wire write_calib_i_1_n_0;\n wire write_calib_i_2_n_0;\n wire write_request_r_reg;\n wire wrlvl_active;\n wire wrlvl_active_i_1_n_0;\n wire wrlvl_active_r1;\n wire wrlvl_byte_redo;\n wire wrlvl_byte_redo_reg;\n wire wrlvl_byte_redo_reg_0;\n wire wrlvl_done_r;\n wire wrlvl_done_r1;\n wire wrlvl_final_if_rst;\n wire wrlvl_final_if_rst_i_1_n_0;\n wire wrlvl_final_if_rst_i_2_n_0;\n wire wrlvl_final_mux;\n wire wrlvl_final_mux_reg;\n wire wrlvl_final_mux_reg_0;\n wire wrlvl_odt;\n wire wrlvl_odt_ctl;\n wire wrlvl_odt_ctl_i_1_n_0;\n wire wrlvl_odt_ctl_i_2_n_0;\n wire wrlvl_odt_ctl_i_3_n_0;\n wire wrlvl_rank_done;\n wire wrlvl_rank_done_r1;\n wire wrlvl_rank_done_r6_reg_srl5_n_0;\n wire wrlvl_rank_done_r7;\n wire [3:1]\\NLW_oclkdelay_ref_cnt_reg[12]_i_1_CO_UNCONNECTED ;\n wire [3:2]\\NLW_oclkdelay_ref_cnt_reg[12]_i_1_O_UNCONNECTED ;\n\n assign in0 = init_complete_r_timing;\n assign out = init_complete_r1_timing;\n LUT6 #(\n .INIT(64'h000000000000E0EE)) \n \\DDR3_1rank.phy_int_cs_n[1]_i_1 \n (.I0(\\odd_cwl.phy_cas_n_reg[1]_0 ),\n .I1(\\DDR3_1rank.phy_int_cs_n[1]_i_3_n_0 ),\n .I2(rdlvl_stg1_start_int_i_2_n_0),\n .I3(\\DDR3_1rank.phy_int_cs_n[1]_i_4_n_0 ),\n .I4(\\DDR3_1rank.phy_int_cs_n[1]_i_5_n_0 ),\n .I5(\\DDR3_1rank.phy_int_cs_n[1]_i_6_n_0 ),\n .O(\\DDR3_1rank.phy_int_cs_n[1]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\DDR3_1rank.phy_int_cs_n[1]_i_2 \n (.I0(\\calib_cmd[2]_i_2_n_0 ),\n .I1(\\calib_cmd[2]_i_3_n_0 ),\n .O(\\odd_cwl.phy_cas_n_reg[1]_0 ));\n LUT6 #(\n .INIT(64'h0000000000000010)) \n \\DDR3_1rank.phy_int_cs_n[1]_i_3 \n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(Q[5]),\n .I3(oclk_calib_resume_level_reg_0),\n .I4(Q[3]),\n .I5(Q[4]),\n .O(\\DDR3_1rank.phy_int_cs_n[1]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair597\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\DDR3_1rank.phy_int_cs_n[1]_i_4 \n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(Q[2]),\n .I2(Q[0]),\n .O(\\DDR3_1rank.phy_int_cs_n[1]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFAAAAABBA)) \n \\DDR3_1rank.phy_int_cs_n[1]_i_5 \n (.I0(write_calib_i_2_n_0),\n .I1(read_calib_i_2_n_0),\n .I2(Q[2]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(prbs_rdlvl_start_i_2_n_0),\n .I5(temp_lmr_done),\n .O(\\DDR3_1rank.phy_int_cs_n[1]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\DDR3_1rank.phy_int_cs_n[1]_i_6 \n (.I0(\\num_refresh[3]_i_4_n_0 ),\n .I1(\\DDR3_1rank.phy_int_cs_n[1]_i_7_n_0 ),\n .I2(\\victim_sel[2]_i_5_n_0 ),\n .I3(\\DDR3_1rank.phy_int_cs_n[1]_i_8_n_0 ),\n .I4(complex_row1_rd_done_i_2_n_0),\n .I5(\\cnt_init_mr_r_reg[1]_0 ),\n .O(\\DDR3_1rank.phy_int_cs_n[1]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000040000)) \n \\DDR3_1rank.phy_int_cs_n[1]_i_7 \n (.I0(prbs_rdlvl_start_i_2_n_0),\n .I1(Q[2]),\n .I2(\\init_state_r_reg_n_0_[3] ),\n .I3(Q[5]),\n .I4(Q[3]),\n .I5(Q[4]),\n .O(\\DDR3_1rank.phy_int_cs_n[1]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h0000000800000000)) \n \\DDR3_1rank.phy_int_cs_n[1]_i_8 \n (.I0(Q[2]),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .I2(Q[4]),\n .I3(prbs_rdlvl_start_i_2_n_0),\n .I4(Q[5]),\n .I5(Q[3]),\n .O(\\DDR3_1rank.phy_int_cs_n[1]_i_8_n_0 ));\n FDSE \\DDR3_1rank.phy_int_cs_n_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\DDR3_1rank.phy_int_cs_n[1]_i_1_n_0 ),\n .Q(phy_cs_n),\n .S(rstdiv0_sync_r1_reg_rep__12));\n LUT2 #(\n .INIT(4'h2)) \n \\FSM_sequential_cal1_state_r[5]_i_10 \n (.I0(mpr_rdlvl_start_r_reg),\n .I1(mpr_rdlvl_start_r),\n .O(cal1_state_r1535_out));\n LUT6 #(\n .INIT(64'h0000000066666706)) \n \\back_to_back_reads_4_1.num_reads[0]_i_1 \n (.I0(num_reads[0]),\n .I1(num_reads0),\n .I2(Q[1]),\n .I3(Q[0]),\n .I4(\\back_to_back_reads_4_1.num_reads_reg[0]_0 ),\n .I5(rstdiv0_sync_r1_reg_rep__25),\n .O(\\back_to_back_reads_4_1.num_reads[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair504\" *) \n LUT3 #(\n .INIT(8'hFE)) \n \\back_to_back_reads_4_1.num_reads[0]_i_2 \n (.I0(num_reads[0]),\n .I1(num_reads[2]),\n .I2(num_reads[1]),\n .O(num_reads0));\n (* SOFT_HLUTNM = \"soft_lutpair521\" *) \n LUT5 #(\n .INIT(32'hFFFFFEFF)) \n \\back_to_back_reads_4_1.num_reads[0]_i_3 \n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(Q[2]),\n .I2(Q[5]),\n .I3(Q[3]),\n .I4(Q[4]),\n .O(\\back_to_back_reads_4_1.num_reads_reg[0]_0 ));\n LUT6 #(\n .INIT(64'h00000000CC320000)) \n \\back_to_back_reads_4_1.num_reads[1]_i_1 \n (.I0(\\back_to_back_reads_4_1.num_reads[1]_i_2_n_0 ),\n .I1(num_reads[1]),\n .I2(num_reads[2]),\n .I3(num_reads[0]),\n .I4(\\back_to_back_reads_4_1.num_reads_reg[1]_0 ),\n .I5(rstdiv0_sync_r1_reg_rep__25),\n .O(\\back_to_back_reads_4_1.num_reads[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000020)) \n \\back_to_back_reads_4_1.num_reads[1]_i_2 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .I1(Q[4]),\n .I2(Q[3]),\n .I3(Q[5]),\n .I4(Q[2]),\n .I5(\\init_state_r_reg_n_0_[3] ),\n .O(\\back_to_back_reads_4_1.num_reads[1]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h00C80000)) \n \\back_to_back_reads_4_1.num_reads[2]_i_1 \n (.I0(num_reads[1]),\n .I1(num_reads[2]),\n .I2(num_reads[0]),\n .I3(rstdiv0_sync_r1_reg_rep__20),\n .I4(\\back_to_back_reads_4_1.num_reads_reg[1]_0 ),\n .O(\\back_to_back_reads_4_1.num_reads[2]_i_1_n_0 ));\n FDRE \\back_to_back_reads_4_1.num_reads_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\back_to_back_reads_4_1.num_reads[0]_i_1_n_0 ),\n .Q(num_reads[0]),\n .R(1'b0));\n FDRE \\back_to_back_reads_4_1.num_reads_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\back_to_back_reads_4_1.num_reads[1]_i_1_n_0 ),\n .Q(num_reads[1]),\n .R(1'b0));\n FDRE \\back_to_back_reads_4_1.num_reads_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\back_to_back_reads_4_1.num_reads[2]_i_1_n_0 ),\n .Q(num_reads[2]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0000010000009595)) \n burst_addr_r_i_2\n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(Q[1]),\n .I2(Q[2]),\n .I3(Q[0]),\n .I4(\\init_state_r[5]_i_26_n_0 ),\n .I5(Q[3]),\n .O(burst_addr_r_reg_1));\n FDRE burst_addr_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(burst_addr_r_reg_2),\n .Q(burst_addr_r_reg_0),\n .R(1'b0));\n FDRE \\calib_cke_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(cnt_pwron_cke_done_r),\n .Q(calib_cke),\n .R(rstdiv0_sync_r1_reg_rep__12));\n (* SOFT_HLUTNM = \"soft_lutpair575\" *) \n LUT3 #(\n .INIT(8'hFB)) \n \\calib_cmd[0]_i_1 \n (.I0(wr_level_dqs_asrt),\n .I1(\\calib_cmd[2]_i_2_n_0 ),\n .I2(\\calib_cmd[2]_i_3_n_0 ),\n .O(\\calib_cmd[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair575\" *) \n LUT3 #(\n .INIT(8'h40)) \n \\calib_cmd[1]_i_1 \n (.I0(wr_level_dqs_asrt),\n .I1(\\calib_cmd[2]_i_2_n_0 ),\n .I2(\\calib_cmd[2]_i_3_n_0 ),\n .O(\\calib_cmd[1]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h04)) \n \\calib_cmd[2]_i_1 \n (.I0(wr_level_dqs_asrt),\n .I1(\\calib_cmd[2]_i_2_n_0 ),\n .I2(\\calib_cmd[2]_i_3_n_0 ),\n .O(\\calib_cmd[2]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h01)) \n \\calib_cmd[2]_i_2 \n (.I0(\\wrcal_wr_cnt[3]_i_2_n_0 ),\n .I1(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .I2(\\calib_cmd[2]_i_4_n_0 ),\n .O(\\calib_cmd[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFEFEFEFEFFFFFEFF)) \n \\calib_cmd[2]_i_3 \n (.I0(\\calib_cmd[2]_i_5_n_0 ),\n .I1(\\calib_cmd[2]_i_6_n_0 ),\n .I2(\\back_to_back_reads_4_1.num_reads[1]_i_2_n_0 ),\n .I3(\\calib_cmd[2]_i_7_n_0 ),\n .I4(\\calib_cmd[2]_i_8_n_0 ),\n .I5(rdlvl_pi_incdec),\n .O(\\calib_cmd[2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h08080000000000FF)) \n \\calib_cmd[2]_i_4 \n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(Q[2]),\n .I2(read_calib_i_2_n_0),\n .I3(prbs_rdlvl_start_i_3_n_0),\n .I4(Q[0]),\n .I5(Q[1]),\n .O(\\calib_cmd[2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000040048)) \n \\calib_cmd[2]_i_5 \n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(Q[3]),\n .I3(\\init_state_r[5]_i_26_n_0 ),\n .I4(Q[2]),\n .I5(\\init_state_r_reg_n_0_[3] ),\n .O(\\calib_cmd[2]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000040200)) \n \\calib_cmd[2]_i_6 \n (.I0(Q[1]),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .I2(Q[0]),\n .I3(Q[2]),\n .I4(Q[3]),\n .I5(\\init_state_r[5]_i_26_n_0 ),\n .O(\\calib_cmd[2]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair507\" *) \n LUT5 #(\n .INIT(32'hFFFFFDFF)) \n \\calib_cmd[2]_i_7 \n (.I0(Q[0]),\n .I1(read_calib_i_2_n_0),\n .I2(Q[2]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[1]),\n .O(\\calib_cmd[2]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000100)) \n \\calib_cmd[2]_i_8 \n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(Q[4]),\n .I3(Q[3]),\n .I4(Q[5]),\n .I5(oclk_calib_resume_level_reg_0),\n .O(\\calib_cmd[2]_i_8_n_0 ));\n FDRE \\calib_cmd_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\calib_cmd[0]_i_1_n_0 ),\n .Q(calib_cmd[0]),\n .R(1'b0));\n FDRE \\calib_cmd_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\calib_cmd[1]_i_1_n_0 ),\n .Q(calib_cmd[1]),\n .R(1'b0));\n FDRE \\calib_cmd_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\calib_cmd[2]_i_1_n_0 ),\n .Q(calib_cmd[2]),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h8)) \n calib_ctl_wren_i_1\n (.I0(cnt_pwron_cke_done_r),\n .I1(\\mcGo_r_reg[15] ),\n .O(calib_ctl_wren0));\n FDRE calib_ctl_wren_reg\n (.C(CLK),\n .CE(1'b1),\n .D(calib_ctl_wren0),\n .Q(calib_ctl_wren),\n .R(rstdiv0_sync_r1_reg_rep__11));\n LUT6 #(\n .INIT(64'h8888000088800080)) \n \\calib_data_offset_0[2]_i_1 \n (.I0(pi_calib_done),\n .I1(\\calib_cmd[2]_i_3_n_0 ),\n .I2(\\rd_byte_data_offset_reg[0][3] [0]),\n .I3(init_dqsfound_done_r2),\n .I4(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3] [0]),\n .I5(pi_dqs_found_done_r1),\n .O(\\calib_data_offset_0[2]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'hB)) \n \\calib_data_offset_0[3]_i_1 \n (.I0(wr_level_dqs_asrt),\n .I1(\\calib_cmd[2]_i_2_n_0 ),\n .O(\\calib_data_offset_0[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8888000088800080)) \n \\calib_data_offset_0[3]_i_2 \n (.I0(pi_calib_done),\n .I1(\\calib_cmd[2]_i_3_n_0 ),\n .I2(\\rd_byte_data_offset_reg[0][3] [1]),\n .I3(init_dqsfound_done_r2),\n .I4(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3] [1]),\n .I5(pi_dqs_found_done_r1),\n .O(\\calib_data_offset_0[3]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'hBFFF)) \n \\calib_data_offset_0[5]_i_1 \n (.I0(wr_level_dqs_asrt),\n .I1(\\calib_cmd[2]_i_2_n_0 ),\n .I2(pi_calib_done),\n .I3(\\calib_cmd[2]_i_3_n_0 ),\n .O(\\calib_data_offset_0[5]_i_1_n_0 ));\n FDRE \\calib_data_offset_0_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_done_r1_reg_3),\n .Q(calib_data_offset_0[0]),\n .R(\\calib_data_offset_0[5]_i_1_n_0 ));\n FDRE \\calib_data_offset_0_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_done_r1_reg_2),\n .Q(calib_data_offset_0[1]),\n .R(\\calib_data_offset_0[5]_i_1_n_0 ));\n FDSE \\calib_data_offset_0_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\calib_data_offset_0[2]_i_1_n_0 ),\n .Q(calib_data_offset_0[2]),\n .S(\\calib_data_offset_0[3]_i_1_n_0 ));\n FDSE \\calib_data_offset_0_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\calib_data_offset_0[3]_i_2_n_0 ),\n .Q(calib_data_offset_0[3]),\n .S(\\calib_data_offset_0[3]_i_1_n_0 ));\n FDRE \\calib_data_offset_0_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_done_r1_reg_1),\n .Q(calib_data_offset_0[4]),\n .R(\\calib_data_offset_0[5]_i_1_n_0 ));\n FDRE \\calib_data_offset_0_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_done_r1_reg_0),\n .Q(calib_data_offset_0[5]),\n .R(\\calib_data_offset_0[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8888000088800080)) \n \\calib_data_offset_1[2]_i_1 \n (.I0(pi_calib_done),\n .I1(\\calib_cmd[2]_i_3_n_0 ),\n .I2(\\rd_byte_data_offset_reg[0][9] [0]),\n .I3(init_dqsfound_done_r2),\n .I4(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] [0]),\n .I5(pi_dqs_found_done_r1),\n .O(\\calib_data_offset_1[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8888000088800080)) \n \\calib_data_offset_1[3]_i_1 \n (.I0(pi_calib_done),\n .I1(\\calib_cmd[2]_i_3_n_0 ),\n .I2(\\rd_byte_data_offset_reg[0][9] [1]),\n .I3(init_dqsfound_done_r2),\n .I4(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] [1]),\n .I5(pi_dqs_found_done_r1),\n .O(\\calib_data_offset_1[3]_i_1_n_0 ));\n FDRE \\calib_data_offset_1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_done_r1_reg_7),\n .Q(calib_data_offset_1[0]),\n .R(\\calib_data_offset_0[5]_i_1_n_0 ));\n FDRE \\calib_data_offset_1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_done_r1_reg_6),\n .Q(calib_data_offset_1[1]),\n .R(\\calib_data_offset_0[5]_i_1_n_0 ));\n FDSE \\calib_data_offset_1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\calib_data_offset_1[2]_i_1_n_0 ),\n .Q(calib_data_offset_1[2]),\n .S(\\calib_data_offset_0[3]_i_1_n_0 ));\n FDSE \\calib_data_offset_1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\calib_data_offset_1[3]_i_1_n_0 ),\n .Q(calib_data_offset_1[3]),\n .S(\\calib_data_offset_0[3]_i_1_n_0 ));\n FDRE \\calib_data_offset_1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_done_r1_reg_5),\n .Q(calib_data_offset_1[4]),\n .R(\\calib_data_offset_0[5]_i_1_n_0 ));\n FDRE \\calib_data_offset_1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_done_r1_reg_4),\n .Q(calib_data_offset_1[5]),\n .R(\\calib_data_offset_0[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h0000AAA2)) \n \\calib_odt[0]_i_1 \n (.I0(\\gen_rnk[0].mr1_r_reg[0]_196 ),\n .I1(\\calib_cmd[2]_i_2_n_0 ),\n .I2(\\calib_odt[0]_i_2_n_0 ),\n .I3(\\calib_odt[0]_i_3_n_0 ),\n .I4(rstdiv0_sync_r1_reg_rep__24),\n .O(\\calib_odt[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hCFDCCFDFCCDCCCDF)) \n \\calib_odt[0]_i_2 \n (.I0(first_wrcal_pat_r_i_2_n_0),\n .I1(stg1_wr_done),\n .I2(Q[1]),\n .I3(Q[0]),\n .I4(complex_ocal_odt_ext_i_4_n_0),\n .I5(\\stg1_wr_rd_cnt[4]_i_5_n_0 ),\n .O(\\calib_odt[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF2000)) \n \\calib_odt[0]_i_3 \n (.I0(wrlvl_odt),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .I2(Q[2]),\n .I3(\\calib_odt[0]_i_4_n_0 ),\n .I4(complex_odt_ext),\n .I5(complex_ocal_odt_ext),\n .O(\\calib_odt[0]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair525\" *) \n LUT5 #(\n .INIT(32'h00100000)) \n \\calib_odt[0]_i_4 \n (.I0(Q[4]),\n .I1(Q[5]),\n .I2(Q[0]),\n .I3(Q[3]),\n .I4(Q[1]),\n .O(\\calib_odt[0]_i_4_n_0 ));\n FDRE \\calib_odt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\calib_odt[0]_i_1_n_0 ),\n .Q(calib_odt),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair559\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\calib_seq[0]_i_1 \n (.I0(cnt_pwron_cke_done_r),\n .I1(\\mcGo_r_reg[15] ),\n .I2(\\phy_ctl_wd_i1_reg[24] [9]),\n .O(\\calib_seq[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair559\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\calib_seq[1]_i_1 \n (.I0(\\phy_ctl_wd_i1_reg[24] [9]),\n .I1(cnt_pwron_cke_done_r),\n .I2(\\mcGo_r_reg[15] ),\n .I3(\\phy_ctl_wd_i1_reg[24] [10]),\n .O(\\calib_seq[1]_i_1_n_0 ));\n FDRE \\calib_seq_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\calib_seq[0]_i_1_n_0 ),\n .Q(\\phy_ctl_wd_i1_reg[24] [9]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE \\calib_seq_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\calib_seq[1]_i_1_n_0 ),\n .Q(\\phy_ctl_wd_i1_reg[24] [10]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n LUT1 #(\n .INIT(2'h1)) \n calib_wrdata_en_i_1\n (.I0(\\calib_cmd[2]_i_2_n_0 ),\n .O(phy_wrdata_en));\n FDRE calib_wrdata_en_reg\n (.C(CLK),\n .CE(1'b1),\n .D(phy_wrdata_en),\n .Q(calib_wrdata_en),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0000000000008000)) \n cnt_cmd_done_m7_r_i_1\n (.I0(\\cnt_cmd_r_reg_n_0_[6] ),\n .I1(\\cnt_cmd_r_reg_n_0_[5] ),\n .I2(\\cnt_cmd_r_reg_n_0_[4] ),\n .I3(\\cnt_cmd_r_reg_n_0_[3] ),\n .I4(cnt_cmd_done_m7_r_i_2_n_0),\n .I5(\\cnt_cmd_r_reg_n_0_[2] ),\n .O(cnt_cmd_done_m7_r_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair604\" *) \n LUT2 #(\n .INIT(4'hE)) \n cnt_cmd_done_m7_r_i_2\n (.I0(\\cnt_cmd_r_reg_n_0_[0] ),\n .I1(\\cnt_cmd_r_reg_n_0_[1] ),\n .O(cnt_cmd_done_m7_r_i_2_n_0));\n FDRE cnt_cmd_done_m7_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cnt_cmd_done_m7_r_i_1_n_0),\n .Q(cnt_cmd_done_m7_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair580\" *) \n LUT3 #(\n .INIT(8'h80)) \n cnt_cmd_done_r_i_1\n (.I0(\\cnt_cmd_r[6]_i_5_n_0 ),\n .I1(\\cnt_cmd_r_reg_n_0_[5] ),\n .I2(\\cnt_cmd_r_reg_n_0_[6] ),\n .O(cnt_cmd_done_r_i_1_n_0));\n FDRE cnt_cmd_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cnt_cmd_done_r_i_1_n_0),\n .Q(cnt_cmd_done_r),\n .R(1'b0));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_cmd_r[0]_i_1 \n (.I0(\\cnt_cmd_r_reg_n_0_[0] ),\n .O(\\cnt_cmd_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair604\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\cnt_cmd_r[1]_i_1 \n (.I0(\\cnt_cmd_r_reg_n_0_[1] ),\n .I1(\\cnt_cmd_r_reg_n_0_[0] ),\n .O(\\cnt_cmd_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair555\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\cnt_cmd_r[2]_i_1 \n (.I0(\\cnt_cmd_r_reg_n_0_[2] ),\n .I1(\\cnt_cmd_r_reg_n_0_[1] ),\n .I2(\\cnt_cmd_r_reg_n_0_[0] ),\n .O(\\cnt_cmd_r[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair555\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\cnt_cmd_r[3]_i_1 \n (.I0(\\cnt_cmd_r_reg_n_0_[3] ),\n .I1(\\cnt_cmd_r_reg_n_0_[2] ),\n .I2(\\cnt_cmd_r_reg_n_0_[0] ),\n .I3(\\cnt_cmd_r_reg_n_0_[1] ),\n .O(\\cnt_cmd_r[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair487\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\cnt_cmd_r[4]_i_1 \n (.I0(\\cnt_cmd_r_reg_n_0_[4] ),\n .I1(\\cnt_cmd_r_reg_n_0_[3] ),\n .I2(\\cnt_cmd_r_reg_n_0_[1] ),\n .I3(\\cnt_cmd_r_reg_n_0_[0] ),\n .I4(\\cnt_cmd_r_reg_n_0_[2] ),\n .O(\\cnt_cmd_r[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n \\cnt_cmd_r[5]_i_1 \n (.I0(\\cnt_cmd_r_reg_n_0_[5] ),\n .I1(\\cnt_cmd_r_reg_n_0_[4] ),\n .I2(\\cnt_cmd_r_reg_n_0_[3] ),\n .I3(\\cnt_cmd_r_reg_n_0_[1] ),\n .I4(\\cnt_cmd_r_reg_n_0_[0] ),\n .I5(\\cnt_cmd_r_reg_n_0_[2] ),\n .O(\\cnt_cmd_r[5]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hFE)) \n \\cnt_cmd_r[6]_i_1 \n (.I0(\\cnt_cmd_r[6]_i_3_n_0 ),\n .I1(\\cnt_cmd_r[6]_i_4_n_0 ),\n .I2(Q[5]),\n .O(\\cnt_cmd_r[6]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair580\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\cnt_cmd_r[6]_i_2 \n (.I0(\\cnt_cmd_r_reg_n_0_[6] ),\n .I1(\\cnt_cmd_r_reg_n_0_[5] ),\n .I2(\\cnt_cmd_r[6]_i_5_n_0 ),\n .O(\\cnt_cmd_r[6]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h5544151145411111)) \n \\cnt_cmd_r[6]_i_3 \n (.I0(Q[0]),\n .I1(Q[4]),\n .I2(\\init_state_r_reg_n_0_[3] ),\n .I3(Q[2]),\n .I4(Q[3]),\n .I5(Q[1]),\n .O(\\cnt_cmd_r[6]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hA8AAA8A2A820A8AA)) \n \\cnt_cmd_r[6]_i_4 \n (.I0(Q[0]),\n .I1(Q[3]),\n .I2(Q[4]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[1]),\n .I5(Q[2]),\n .O(\\cnt_cmd_r[6]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair487\" *) \n LUT5 #(\n .INIT(32'h80000000)) \n \\cnt_cmd_r[6]_i_5 \n (.I0(\\cnt_cmd_r_reg_n_0_[2] ),\n .I1(\\cnt_cmd_r_reg_n_0_[0] ),\n .I2(\\cnt_cmd_r_reg_n_0_[1] ),\n .I3(\\cnt_cmd_r_reg_n_0_[3] ),\n .I4(\\cnt_cmd_r_reg_n_0_[4] ),\n .O(\\cnt_cmd_r[6]_i_5_n_0 ));\n FDRE \\cnt_cmd_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cnt_cmd_r[0]_i_1_n_0 ),\n .Q(\\cnt_cmd_r_reg_n_0_[0] ),\n .R(\\cnt_cmd_r[6]_i_1_n_0 ));\n FDRE \\cnt_cmd_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cnt_cmd_r[1]_i_1_n_0 ),\n .Q(\\cnt_cmd_r_reg_n_0_[1] ),\n .R(\\cnt_cmd_r[6]_i_1_n_0 ));\n FDRE \\cnt_cmd_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cnt_cmd_r[2]_i_1_n_0 ),\n .Q(\\cnt_cmd_r_reg_n_0_[2] ),\n .R(\\cnt_cmd_r[6]_i_1_n_0 ));\n FDRE \\cnt_cmd_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cnt_cmd_r[3]_i_1_n_0 ),\n .Q(\\cnt_cmd_r_reg_n_0_[3] ),\n .R(\\cnt_cmd_r[6]_i_1_n_0 ));\n FDRE \\cnt_cmd_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cnt_cmd_r[4]_i_1_n_0 ),\n .Q(\\cnt_cmd_r_reg_n_0_[4] ),\n .R(\\cnt_cmd_r[6]_i_1_n_0 ));\n FDRE \\cnt_cmd_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cnt_cmd_r[5]_i_1_n_0 ),\n .Q(\\cnt_cmd_r_reg_n_0_[5] ),\n .R(\\cnt_cmd_r[6]_i_1_n_0 ));\n FDRE \\cnt_cmd_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cnt_cmd_r[6]_i_2_n_0 ),\n .Q(\\cnt_cmd_r_reg_n_0_[6] ),\n .R(\\cnt_cmd_r[6]_i_1_n_0 ));\n FDRE cnt_dllk_zqinit_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cnt_dllk_zqinit_done_r_reg_0),\n .Q(cnt_dllk_zqinit_done_r),\n .R(cnt_dllk_zqinit_r));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_dllk_zqinit_r[0]_i_1 \n (.I0(cnt_dllk_zqinit_r_reg__0[0]),\n .O(p_0_in__3[0]));\n (* SOFT_HLUTNM = \"soft_lutpair598\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\cnt_dllk_zqinit_r[1]_i_1 \n (.I0(cnt_dllk_zqinit_r_reg__0[1]),\n .I1(cnt_dllk_zqinit_r_reg__0[0]),\n .O(p_0_in__3[1]));\n (* SOFT_HLUTNM = \"soft_lutpair598\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\cnt_dllk_zqinit_r[2]_i_1 \n (.I0(cnt_dllk_zqinit_r_reg__0[2]),\n .I1(cnt_dllk_zqinit_r_reg__0[0]),\n .I2(cnt_dllk_zqinit_r_reg__0[1]),\n .O(p_0_in__3[2]));\n (* SOFT_HLUTNM = \"soft_lutpair520\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\cnt_dllk_zqinit_r[3]_i_1 \n (.I0(cnt_dllk_zqinit_r_reg__0[3]),\n .I1(cnt_dllk_zqinit_r_reg__0[1]),\n .I2(cnt_dllk_zqinit_r_reg__0[0]),\n .I3(cnt_dllk_zqinit_r_reg__0[2]),\n .O(p_0_in__3[3]));\n (* SOFT_HLUTNM = \"soft_lutpair520\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\cnt_dllk_zqinit_r[4]_i_1 \n (.I0(cnt_dllk_zqinit_r_reg__0[4]),\n .I1(cnt_dllk_zqinit_r_reg__0[2]),\n .I2(cnt_dllk_zqinit_r_reg__0[0]),\n .I3(cnt_dllk_zqinit_r_reg__0[1]),\n .I4(cnt_dllk_zqinit_r_reg__0[3]),\n .O(p_0_in__3[4]));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n \\cnt_dllk_zqinit_r[5]_i_1 \n (.I0(cnt_dllk_zqinit_r_reg__0[5]),\n .I1(cnt_dllk_zqinit_r_reg__0[3]),\n .I2(cnt_dllk_zqinit_r_reg__0[1]),\n .I3(cnt_dllk_zqinit_r_reg__0[0]),\n .I4(cnt_dllk_zqinit_r_reg__0[2]),\n .I5(cnt_dllk_zqinit_r_reg__0[4]),\n .O(p_0_in__3[5]));\n (* SOFT_HLUTNM = \"soft_lutpair595\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\cnt_dllk_zqinit_r[6]_i_1 \n (.I0(mem_init_done_r_reg_0[0]),\n .I1(mem_init_done_r_reg_1),\n .O(p_0_in__3[6]));\n LUT6 #(\n .INIT(64'h0000000000000010)) \n \\cnt_dllk_zqinit_r[7]_i_1 \n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(\\wrcal_reads[7]_i_5_n_0 ),\n .I3(Q[5]),\n .I4(Q[4]),\n .I5(Q[3]),\n .O(cnt_dllk_zqinit_r));\n (* SOFT_HLUTNM = \"soft_lutpair595\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\cnt_dllk_zqinit_r[7]_i_2 \n (.I0(mem_init_done_r_reg_0[1]),\n .I1(mem_init_done_r_reg_1),\n .I2(mem_init_done_r_reg_0[0]),\n .O(p_0_in__3[7]));\n FDRE \\cnt_dllk_zqinit_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__3[0]),\n .Q(cnt_dllk_zqinit_r_reg__0[0]),\n .R(cnt_dllk_zqinit_r));\n FDRE \\cnt_dllk_zqinit_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__3[1]),\n .Q(cnt_dllk_zqinit_r_reg__0[1]),\n .R(cnt_dllk_zqinit_r));\n FDRE \\cnt_dllk_zqinit_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__3[2]),\n .Q(cnt_dllk_zqinit_r_reg__0[2]),\n .R(cnt_dllk_zqinit_r));\n FDRE \\cnt_dllk_zqinit_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__3[3]),\n .Q(cnt_dllk_zqinit_r_reg__0[3]),\n .R(cnt_dllk_zqinit_r));\n FDRE \\cnt_dllk_zqinit_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__3[4]),\n .Q(cnt_dllk_zqinit_r_reg__0[4]),\n .R(cnt_dllk_zqinit_r));\n FDRE \\cnt_dllk_zqinit_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__3[5]),\n .Q(cnt_dllk_zqinit_r_reg__0[5]),\n .R(cnt_dllk_zqinit_r));\n FDRE \\cnt_dllk_zqinit_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__3[6]),\n .Q(mem_init_done_r_reg_0[0]),\n .R(cnt_dllk_zqinit_r));\n FDRE \\cnt_dllk_zqinit_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__3[7]),\n .Q(mem_init_done_r_reg_0[1]),\n .R(cnt_dllk_zqinit_r));\n FDRE cnt_init_af_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cnt_init_af_done_r_reg_0),\n .Q(cnt_init_af_done_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair500\" *) \n LUT4 #(\n .INIT(16'h009A)) \n \\cnt_init_af_r[0]_i_1 \n (.I0(cnt_init_af_r[0]),\n .I1(mem_init_done_r),\n .I2(\\cnt_init_mr_r_reg[1]_0 ),\n .I3(\\reg_ctrl_cnt_r_reg[3]_0 ),\n .O(\\cnt_init_af_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair500\" *) \n LUT5 #(\n .INIT(32'h00009AAA)) \n \\cnt_init_af_r[1]_i_1 \n (.I0(cnt_init_af_r[1]),\n .I1(mem_init_done_r),\n .I2(\\cnt_init_mr_r_reg[1]_0 ),\n .I3(cnt_init_af_r[0]),\n .I4(\\reg_ctrl_cnt_r_reg[3]_0 ),\n .O(\\cnt_init_af_r[1]_i_1_n_0 ));\n FDRE \\cnt_init_af_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cnt_init_af_r[0]_i_1_n_0 ),\n .Q(cnt_init_af_r[0]),\n .R(1'b0));\n FDRE \\cnt_init_af_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cnt_init_af_r[1]_i_1_n_0 ),\n .Q(cnt_init_af_r[1]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0000000004000000)) \n cnt_init_mr_done_r_i_2\n (.I0(Q[5]),\n .I1(Q[3]),\n .I2(Q[4]),\n .I3(\\init_state_r_reg[1]_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .I5(mem_init_done_r),\n .O(cnt_init_mr_r1));\n FDRE cnt_init_mr_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cnt_init_mr_done_r_reg_0),\n .Q(cnt_init_mr_done_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00006606)) \n \\cnt_init_mr_r[0]_i_1 \n (.I0(cnt_init_mr_r[0]),\n .I1(temp_lmr_done),\n .I2(\\cnt_init_mr_r_reg[1]_0 ),\n .I3(mem_init_done_r),\n .I4(\\reg_ctrl_cnt_r_reg[3]_0 ),\n .O(\\cnt_init_mr_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h000000006A6A006A)) \n \\cnt_init_mr_r[1]_i_1 \n (.I0(cnt_init_mr_r[1]),\n .I1(temp_lmr_done),\n .I2(cnt_init_mr_r[0]),\n .I3(\\cnt_init_mr_r_reg[1]_0 ),\n .I4(mem_init_done_r),\n .I5(\\reg_ctrl_cnt_r_reg[3]_0 ),\n .O(\\cnt_init_mr_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\cnt_init_mr_r[1]_i_2 \n (.I0(Q[1]),\n .I1(Q[4]),\n .I2(Q[5]),\n .I3(oclk_calib_resume_level_reg_0),\n .I4(Q[3]),\n .I5(Q[0]),\n .O(temp_lmr_done));\n LUT6 #(\n .INIT(64'h0000000000080000)) \n \\cnt_init_mr_r[1]_i_3 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .I2(Q[2]),\n .I3(Q[4]),\n .I4(Q[3]),\n .I5(Q[5]),\n .O(\\cnt_init_mr_r_reg[1]_0 ));\n FDRE \\cnt_init_mr_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cnt_init_mr_r[0]_i_1_n_0 ),\n .Q(cnt_init_mr_r[0]),\n .R(1'b0));\n FDRE \\cnt_init_mr_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cnt_init_mr_r[1]_i_1_n_0 ),\n .Q(cnt_init_mr_r[1]),\n .R(1'b0));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_pwron_ce_r[0]_i_1 \n (.I0(cnt_pwron_ce_r_reg__0[0]),\n .O(p_0_in__0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair602\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\cnt_pwron_ce_r[1]_i_1 \n (.I0(cnt_pwron_ce_r_reg__0[1]),\n .I1(cnt_pwron_ce_r_reg__0[0]),\n .O(p_0_in__0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair602\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\cnt_pwron_ce_r[2]_i_1 \n (.I0(cnt_pwron_ce_r_reg__0[2]),\n .I1(cnt_pwron_ce_r_reg__0[0]),\n .I2(cnt_pwron_ce_r_reg__0[1]),\n .O(p_0_in__0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair495\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\cnt_pwron_ce_r[3]_i_1 \n (.I0(cnt_pwron_ce_r_reg__0[3]),\n .I1(cnt_pwron_ce_r_reg__0[1]),\n .I2(cnt_pwron_ce_r_reg__0[0]),\n .I3(cnt_pwron_ce_r_reg__0[2]),\n .O(p_0_in__0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair495\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\cnt_pwron_ce_r[4]_i_1 \n (.I0(cnt_pwron_ce_r_reg__0[4]),\n .I1(cnt_pwron_ce_r_reg__0[2]),\n .I2(cnt_pwron_ce_r_reg__0[0]),\n .I3(cnt_pwron_ce_r_reg__0[1]),\n .I4(cnt_pwron_ce_r_reg__0[3]),\n .O(p_0_in__0[4]));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n \\cnt_pwron_ce_r[5]_i_1 \n (.I0(cnt_pwron_ce_r_reg__0[5]),\n .I1(cnt_pwron_ce_r_reg__0[3]),\n .I2(cnt_pwron_ce_r_reg__0[1]),\n .I3(cnt_pwron_ce_r_reg__0[0]),\n .I4(cnt_pwron_ce_r_reg__0[2]),\n .I5(cnt_pwron_ce_r_reg__0[4]),\n .O(p_0_in__0[5]));\n (* SOFT_HLUTNM = \"soft_lutpair601\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\cnt_pwron_ce_r[6]_i_1 \n (.I0(cnt_pwron_ce_r_reg__0[6]),\n .I1(pwron_ce_r_i_3_n_0),\n .O(p_0_in__0[6]));\n (* SOFT_HLUTNM = \"soft_lutpair601\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\cnt_pwron_ce_r[7]_i_1 \n (.I0(cnt_pwron_ce_r_reg__0[7]),\n .I1(pwron_ce_r_i_3_n_0),\n .I2(cnt_pwron_ce_r_reg__0[6]),\n .O(p_0_in__0[7]));\n (* SOFT_HLUTNM = \"soft_lutpair511\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\cnt_pwron_ce_r[8]_i_1 \n (.I0(cnt_pwron_ce_r_reg__0[8]),\n .I1(cnt_pwron_ce_r_reg__0[6]),\n .I2(pwron_ce_r_i_3_n_0),\n .I3(cnt_pwron_ce_r_reg__0[7]),\n .O(p_0_in__0[8]));\n (* SOFT_HLUTNM = \"soft_lutpair511\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\cnt_pwron_ce_r[9]_i_1 \n (.I0(cnt_pwron_ce_r_reg__0[9]),\n .I1(cnt_pwron_ce_r_reg__0[7]),\n .I2(pwron_ce_r_i_3_n_0),\n .I3(cnt_pwron_ce_r_reg__0[6]),\n .I4(cnt_pwron_ce_r_reg__0[8]),\n .O(p_0_in__0[9]));\n FDRE \\cnt_pwron_ce_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0[0]),\n .Q(cnt_pwron_ce_r_reg__0[0]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE \\cnt_pwron_ce_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0[1]),\n .Q(cnt_pwron_ce_r_reg__0[1]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE \\cnt_pwron_ce_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0[2]),\n .Q(cnt_pwron_ce_r_reg__0[2]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE \\cnt_pwron_ce_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0[3]),\n .Q(cnt_pwron_ce_r_reg__0[3]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE \\cnt_pwron_ce_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0[4]),\n .Q(cnt_pwron_ce_r_reg__0[4]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE \\cnt_pwron_ce_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0[5]),\n .Q(cnt_pwron_ce_r_reg__0[5]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE \\cnt_pwron_ce_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0[6]),\n .Q(cnt_pwron_ce_r_reg__0[6]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE \\cnt_pwron_ce_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0[7]),\n .Q(cnt_pwron_ce_r_reg__0[7]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE \\cnt_pwron_ce_r_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0[8]),\n .Q(cnt_pwron_ce_r_reg__0[8]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE \\cnt_pwron_ce_r_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0[9]),\n .Q(cnt_pwron_ce_r_reg__0[9]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n LUT6 #(\n .INIT(64'hFEFFFFFFFFFFFFFF)) \n cnt_pwron_cke_done_r_i_2\n (.I0(cnt_pwron_r_reg__0[8]),\n .I1(cnt_pwron_r_reg__0[6]),\n .I2(\\cnt_pwron_r_reg[7]_0 [2]),\n .I3(cnt_pwron_r_reg__0[4]),\n .I4(cnt_pwron_r_reg__0[3]),\n .I5(cnt_pwron_r_reg__0[2]),\n .O(cnt_pwron_cke_done_r_reg_0));\n FDRE cnt_pwron_cke_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cnt_pwron_cke_done_r_reg_1),\n .Q(cnt_pwron_cke_done_r),\n .R(1'b0));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_pwron_r[0]_i_1 \n (.I0(\\cnt_pwron_r_reg[7]_0 [0]),\n .O(p_0_in__0__0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair600\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\cnt_pwron_r[1]_i_1 \n (.I0(\\cnt_pwron_r_reg[7]_0 [1]),\n .I1(\\cnt_pwron_r_reg[7]_0 [0]),\n .O(p_0_in__0__0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair600\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\cnt_pwron_r[2]_i_1 \n (.I0(cnt_pwron_r_reg__0[2]),\n .I1(\\cnt_pwron_r_reg[7]_0 [0]),\n .I2(\\cnt_pwron_r_reg[7]_0 [1]),\n .O(p_0_in__0__0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair515\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\cnt_pwron_r[3]_i_1 \n (.I0(cnt_pwron_r_reg__0[3]),\n .I1(\\cnt_pwron_r_reg[7]_0 [1]),\n .I2(\\cnt_pwron_r_reg[7]_0 [0]),\n .I3(cnt_pwron_r_reg__0[2]),\n .O(p_0_in__0__0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair515\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\cnt_pwron_r[4]_i_1 \n (.I0(cnt_pwron_r_reg__0[4]),\n .I1(cnt_pwron_r_reg__0[3]),\n .I2(cnt_pwron_r_reg__0[2]),\n .I3(\\cnt_pwron_r_reg[7]_0 [1]),\n .I4(\\cnt_pwron_r_reg[7]_0 [0]),\n .O(p_0_in__0__0[4]));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n \\cnt_pwron_r[5]_i_1 \n (.I0(\\cnt_pwron_r_reg[7]_0 [2]),\n .I1(\\cnt_pwron_r_reg[7]_0 [0]),\n .I2(\\cnt_pwron_r_reg[7]_0 [1]),\n .I3(cnt_pwron_r_reg__0[2]),\n .I4(cnt_pwron_r_reg__0[3]),\n .I5(cnt_pwron_r_reg__0[4]),\n .O(p_0_in__0__0[5]));\n LUT6 #(\n .INIT(64'hA6AAAAAAAAAAAAAA)) \n \\cnt_pwron_r[6]_i_1 \n (.I0(cnt_pwron_r_reg__0[6]),\n .I1(cnt_pwron_r_reg__0[4]),\n .I2(\\cnt_pwron_r[6]_i_2_n_0 ),\n .I3(\\cnt_pwron_r_reg[7]_0 [1]),\n .I4(\\cnt_pwron_r_reg[7]_0 [0]),\n .I5(\\cnt_pwron_r_reg[7]_0 [2]),\n .O(p_0_in__0__0[6]));\n LUT2 #(\n .INIT(4'h7)) \n \\cnt_pwron_r[6]_i_2 \n (.I0(cnt_pwron_r_reg__0[3]),\n .I1(cnt_pwron_r_reg__0[2]),\n .O(\\cnt_pwron_r[6]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair535\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\cnt_pwron_r[7]_i_1 \n (.I0(\\cnt_pwron_r_reg[7]_0 [3]),\n .I1(\\cnt_pwron_r[8]_i_2_n_0 ),\n .I2(cnt_pwron_r_reg__0[6]),\n .O(p_0_in__0__0[7]));\n (* SOFT_HLUTNM = \"soft_lutpair535\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\cnt_pwron_r[8]_i_1 \n (.I0(cnt_pwron_r_reg__0[8]),\n .I1(cnt_pwron_r_reg__0[6]),\n .I2(\\cnt_pwron_r[8]_i_2_n_0 ),\n .I3(\\cnt_pwron_r_reg[7]_0 [3]),\n .O(p_0_in__0__0[8]));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\cnt_pwron_r[8]_i_2 \n (.I0(\\cnt_pwron_r_reg[7]_0 [2]),\n .I1(\\cnt_pwron_r_reg[7]_0 [0]),\n .I2(\\cnt_pwron_r_reg[7]_0 [1]),\n .I3(cnt_pwron_r_reg__0[2]),\n .I4(cnt_pwron_r_reg__0[3]),\n .I5(cnt_pwron_r_reg__0[4]),\n .O(\\cnt_pwron_r[8]_i_2_n_0 ));\n FDRE \\cnt_pwron_r_reg[0] \n (.C(CLK),\n .CE(pwron_ce_r),\n .D(p_0_in__0__0[0]),\n .Q(\\cnt_pwron_r_reg[7]_0 [0]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE \\cnt_pwron_r_reg[1] \n (.C(CLK),\n .CE(pwron_ce_r),\n .D(p_0_in__0__0[1]),\n .Q(\\cnt_pwron_r_reg[7]_0 [1]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE \\cnt_pwron_r_reg[2] \n (.C(CLK),\n .CE(pwron_ce_r),\n .D(p_0_in__0__0[2]),\n .Q(cnt_pwron_r_reg__0[2]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE \\cnt_pwron_r_reg[3] \n (.C(CLK),\n .CE(pwron_ce_r),\n .D(p_0_in__0__0[3]),\n .Q(cnt_pwron_r_reg__0[3]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE \\cnt_pwron_r_reg[4] \n (.C(CLK),\n .CE(pwron_ce_r),\n .D(p_0_in__0__0[4]),\n .Q(cnt_pwron_r_reg__0[4]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE \\cnt_pwron_r_reg[5] \n (.C(CLK),\n .CE(pwron_ce_r),\n .D(p_0_in__0__0[5]),\n .Q(\\cnt_pwron_r_reg[7]_0 [2]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE \\cnt_pwron_r_reg[6] \n (.C(CLK),\n .CE(pwron_ce_r),\n .D(p_0_in__0__0[6]),\n .Q(cnt_pwron_r_reg__0[6]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE \\cnt_pwron_r_reg[7] \n (.C(CLK),\n .CE(pwron_ce_r),\n .D(p_0_in__0__0[7]),\n .Q(\\cnt_pwron_r_reg[7]_0 [3]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE \\cnt_pwron_r_reg[8] \n (.C(CLK),\n .CE(pwron_ce_r),\n .D(p_0_in__0__0[8]),\n .Q(cnt_pwron_r_reg__0[8]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n LUT6 #(\n .INIT(64'hFFFEFFFFFFFFFFFF)) \n cnt_pwron_reset_done_r_i_2\n (.I0(cnt_pwron_r_reg__0[8]),\n .I1(cnt_pwron_r_reg__0[6]),\n .I2(\\cnt_pwron_r_reg[7]_0 [1]),\n .I3(cnt_pwron_r_reg__0[4]),\n .I4(cnt_pwron_r_reg__0[3]),\n .I5(cnt_pwron_r_reg__0[2]),\n .O(cnt_pwron_reset_done_r_reg_0));\n FDRE cnt_pwron_reset_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\cnt_pwron_r_reg[7]_1 ),\n .Q(cnt_pwron_reset_done_r),\n .R(1'b0));\n LUT3 #(\n .INIT(8'hBA)) \n \\cnt_shift_r[3]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__23),\n .I1(rdlvl_stg1_start_r_reg),\n .I2(mpr_rdlvl_done_r_reg),\n .O(\\cnt_shift_r_reg[0] ));\n LUT5 #(\n .INIT(32'h88C88888)) \n \\cnt_shift_r[3]_i_2 \n (.I0(rdlvl_stg1_start_r_reg),\n .I1(phy_rddata_en_1),\n .I2(mpr_rdlvl_start_r_reg),\n .I3(mpr_rdlvl_done_r_reg),\n .I4(\\cnt_shift_r_reg[0]_0 ),\n .O(E));\n LUT5 #(\n .INIT(32'hFFFFFFEF)) \n cnt_txpr_done_r_i_2\n (.I0(cnt_txpr_r_reg__0[7]),\n .I1(cnt_txpr_r_reg__0[4]),\n .I2(cnt_txpr_r_reg__0[6]),\n .I3(cnt_txpr_r_reg__0[3]),\n .I4(cnt_txpr_r_reg__0[5]),\n .O(cnt_txpr_done_r_reg_0));\n FDRE cnt_txpr_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cnt_txpr_done_r_reg_1),\n .Q(cnt_txpr_done_r),\n .R(clear));\n (* SOFT_HLUTNM = \"soft_lutpair609\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\cnt_txpr_r[0]_i_1 \n (.I0(\\cnt_txpr_r_reg[2]_0 [0]),\n .O(p_0_in__1[0]));\n (* SOFT_HLUTNM = \"soft_lutpair609\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\cnt_txpr_r[1]_i_1 \n (.I0(\\cnt_txpr_r_reg[2]_0 [1]),\n .I1(\\cnt_txpr_r_reg[2]_0 [0]),\n .O(p_0_in__1[1]));\n (* SOFT_HLUTNM = \"soft_lutpair599\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\cnt_txpr_r[2]_i_1 \n (.I0(\\cnt_txpr_r_reg[2]_0 [2]),\n .I1(\\cnt_txpr_r_reg[2]_0 [0]),\n .I2(\\cnt_txpr_r_reg[2]_0 [1]),\n .O(p_0_in__1[2]));\n (* SOFT_HLUTNM = \"soft_lutpair490\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\cnt_txpr_r[3]_i_1 \n (.I0(cnt_txpr_r_reg__0[3]),\n .I1(\\cnt_txpr_r_reg[2]_0 [1]),\n .I2(\\cnt_txpr_r_reg[2]_0 [0]),\n .I3(\\cnt_txpr_r_reg[2]_0 [2]),\n .O(p_0_in__1[3]));\n (* SOFT_HLUTNM = \"soft_lutpair490\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\cnt_txpr_r[4]_i_1 \n (.I0(cnt_txpr_r_reg__0[4]),\n .I1(\\cnt_txpr_r_reg[2]_0 [2]),\n .I2(\\cnt_txpr_r_reg[2]_0 [0]),\n .I3(\\cnt_txpr_r_reg[2]_0 [1]),\n .I4(cnt_txpr_r_reg__0[3]),\n .O(p_0_in__1[4]));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n \\cnt_txpr_r[5]_i_1 \n (.I0(cnt_txpr_r_reg__0[5]),\n .I1(cnt_txpr_r_reg__0[3]),\n .I2(\\cnt_txpr_r_reg[2]_0 [1]),\n .I3(\\cnt_txpr_r_reg[2]_0 [0]),\n .I4(\\cnt_txpr_r_reg[2]_0 [2]),\n .I5(cnt_txpr_r_reg__0[4]),\n .O(p_0_in__1[5]));\n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\cnt_txpr_r[6]_i_1 \n (.I0(cnt_txpr_r_reg__0[6]),\n .I1(cnt_txpr_r_reg__0[4]),\n .I2(\\cnt_txpr_r[7]_i_3_n_0 ),\n .I3(cnt_txpr_r_reg__0[3]),\n .I4(cnt_txpr_r_reg__0[5]),\n .O(p_0_in__1[6]));\n LUT1 #(\n .INIT(2'h1)) \n \\cnt_txpr_r[7]_i_1 \n (.I0(cnt_pwron_cke_done_r),\n .O(clear));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n \\cnt_txpr_r[7]_i_2 \n (.I0(cnt_txpr_r_reg__0[7]),\n .I1(cnt_txpr_r_reg__0[6]),\n .I2(cnt_txpr_r_reg__0[5]),\n .I3(cnt_txpr_r_reg__0[3]),\n .I4(\\cnt_txpr_r[7]_i_3_n_0 ),\n .I5(cnt_txpr_r_reg__0[4]),\n .O(p_0_in__1[7]));\n (* SOFT_HLUTNM = \"soft_lutpair599\" *) \n LUT3 #(\n .INIT(8'h80)) \n \\cnt_txpr_r[7]_i_3 \n (.I0(\\cnt_txpr_r_reg[2]_0 [2]),\n .I1(\\cnt_txpr_r_reg[2]_0 [0]),\n .I2(\\cnt_txpr_r_reg[2]_0 [1]),\n .O(\\cnt_txpr_r[7]_i_3_n_0 ));\n FDRE \\cnt_txpr_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__1[0]),\n .Q(\\cnt_txpr_r_reg[2]_0 [0]),\n .R(clear));\n FDRE \\cnt_txpr_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__1[1]),\n .Q(\\cnt_txpr_r_reg[2]_0 [1]),\n .R(clear));\n FDRE \\cnt_txpr_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__1[2]),\n .Q(\\cnt_txpr_r_reg[2]_0 [2]),\n .R(clear));\n FDRE \\cnt_txpr_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__1[3]),\n .Q(cnt_txpr_r_reg__0[3]),\n .R(clear));\n FDRE \\cnt_txpr_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__1[4]),\n .Q(cnt_txpr_r_reg__0[4]),\n .R(clear));\n FDRE \\cnt_txpr_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__1[5]),\n .Q(cnt_txpr_r_reg__0[5]),\n .R(clear));\n FDRE \\cnt_txpr_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__1[6]),\n .Q(cnt_txpr_r_reg__0[6]),\n .R(clear));\n FDRE \\cnt_txpr_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__1[7]),\n .Q(cnt_txpr_r_reg__0[7]),\n .R(clear));\n LUT6 #(\n .INIT(64'h0000404000034040)) \n complex_act_start_i_1\n (.I0(read_calib_reg_0),\n .I1(Q[4]),\n .I2(Q[3]),\n .I3(oclk_calib_resume_level_reg_0),\n .I4(Q[5]),\n .I5(prbs_rdlvl_start_i_2_n_0),\n .O(complex_act_start0));\n FDRE complex_act_start_reg\n (.C(CLK),\n .CE(1'b1),\n .D(complex_act_start0),\n .Q(complex_act_start),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hFFFEFD00)) \n \\complex_address[9]_i_1 \n (.I0(init_state_r1[2]),\n .I1(init_state_r1[6]),\n .I2(\\complex_address[9]_i_2_n_0 ),\n .I3(\\complex_address[9]_i_3_n_0 ),\n .I4(\\complex_address[9]_i_4_n_0 ),\n .O(complex_address0));\n (* SOFT_HLUTNM = \"soft_lutpair513\" *) \n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\complex_address[9]_i_2 \n (.I0(init_state_r1[3]),\n .I1(init_state_r1[4]),\n .I2(init_state_r1[5]),\n .I3(init_state_r1[0]),\n .I4(init_state_r1[1]),\n .O(\\complex_address[9]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h2000000000000000)) \n \\complex_address[9]_i_3 \n (.I0(Q[4]),\n .I1(Q[5]),\n .I2(Q[3]),\n .I3(Q[2]),\n .I4(\\init_state_r_reg_n_0_[3] ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .O(\\complex_address[9]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0000200000000000)) \n \\complex_address[9]_i_4 \n (.I0(Q[4]),\n .I1(Q[5]),\n .I2(Q[3]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[2]),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .O(\\complex_address[9]_i_4_n_0 ));\n FDRE \\complex_address_reg[0] \n (.C(CLK),\n .CE(complex_address0),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),\n .Q(\\complex_address_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE \\complex_address_reg[1] \n (.C(CLK),\n .CE(complex_address0),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),\n .Q(\\complex_address_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE \\complex_address_reg[2] \n (.C(CLK),\n .CE(complex_address0),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),\n .Q(\\complex_address_reg_n_0_[2] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE \\complex_address_reg[3] \n (.C(CLK),\n .CE(complex_address0),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .Q(\\complex_address_reg_n_0_[3] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE \\complex_address_reg[4] \n (.C(CLK),\n .CE(complex_address0),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .Q(\\complex_address_reg_n_0_[4] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE \\complex_address_reg[5] \n (.C(CLK),\n .CE(complex_address0),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),\n .Q(\\complex_address_reg_n_0_[5] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE \\complex_address_reg[6] \n (.C(CLK),\n .CE(complex_address0),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),\n .Q(\\complex_address_reg_n_0_[6] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE \\complex_address_reg[7] \n (.C(CLK),\n .CE(complex_address0),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),\n .Q(\\complex_address_reg_n_0_[7] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE \\complex_address_reg[8] \n (.C(CLK),\n .CE(complex_address0),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),\n .Q(\\complex_address_reg_n_0_[8] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE \\complex_address_reg[9] \n (.C(CLK),\n .CE(complex_address0),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),\n .Q(\\complex_address_reg_n_0_[9] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n LUT5 #(\n .INIT(32'h0000000E)) \n complex_byte_rd_done_i_1\n (.I0(complex_byte_rd_done),\n .I1(complex_byte_rd_done_i_2_n_0),\n .I2(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .I3(prbs_rdlvl_done_pulse),\n .I4(rstdiv0_sync_r1_reg_rep__25),\n .O(complex_byte_rd_done_i_1_n_0));\n LUT6 #(\n .INIT(64'h0000800000000000)) \n complex_byte_rd_done_i_2\n (.I0(complex_row1_rd_cnt[0]),\n .I1(complex_row1_rd_cnt[1]),\n .I2(complex_row1_rd_cnt[2]),\n .I3(complex_row1_rd_done),\n .I4(complex_row1_rd_done_r1),\n .I5(prbs_rdlvl_done_reg_rep),\n .O(complex_byte_rd_done_i_2_n_0));\n FDRE complex_byte_rd_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(complex_byte_rd_done_i_1_n_0),\n .Q(complex_byte_rd_done),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h000000AE)) \n complex_mask_lim_done_i_1\n (.I0(complex_mask_lim_done),\n .I1(complex_oclkdelay_calib_start_int),\n .I2(prbs_rdlvl_done_reg),\n .I3(prbs_rdlvl_done_r3),\n .I4(rstdiv0_sync_r1_reg_rep__25),\n .O(complex_mask_lim_done_i_1_n_0));\n FDRE complex_mask_lim_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(complex_mask_lim_done_i_1_n_0),\n .Q(complex_mask_lim_done),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hFFFF26EE)) \n \\complex_num_reads[0]_i_1 \n (.I0(\\complex_num_reads_reg_n_0_[0] ),\n .I1(\\complex_num_reads[3]_i_2_n_0 ),\n .I2(\\complex_num_writes[4]_i_5_n_0 ),\n .I3(\\complex_num_reads[2]_i_4_n_0 ),\n .I4(\\complex_num_reads[3]_i_4_n_0 ),\n .O(\\complex_num_reads[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h000000000222FE22)) \n \\complex_num_reads[1]_i_1 \n (.I0(\\complex_num_reads_reg_n_0_[1] ),\n .I1(\\complex_num_reads[2]_i_2_n_0 ),\n .I2(\\complex_num_writes[2]_i_4_n_0 ),\n .I3(\\complex_num_reads[2]_i_4_n_0 ),\n .I4(\\complex_num_reads[1]_i_2_n_0 ),\n .I5(\\complex_num_reads[2]_i_5_n_0 ),\n .O(\\complex_num_reads[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair553\" *) \n LUT4 #(\n .INIT(16'hA88A)) \n \\complex_num_reads[1]_i_2 \n (.I0(\\complex_num_reads[3]_i_8_n_0 ),\n .I1(\\complex_num_writes[4]_i_5_n_0 ),\n .I2(\\complex_num_reads_reg_n_0_[1] ),\n .I3(\\complex_num_reads_reg_n_0_[0] ),\n .O(\\complex_num_reads[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00000000002E2222)) \n \\complex_num_reads[2]_i_1 \n (.I0(\\complex_num_reads_reg_n_0_[2] ),\n .I1(\\complex_num_reads[2]_i_2_n_0 ),\n .I2(\\complex_num_reads[2]_i_3_n_0 ),\n .I3(\\complex_num_writes[2]_i_4_n_0 ),\n .I4(\\complex_num_reads[2]_i_4_n_0 ),\n .I5(\\complex_num_reads[2]_i_5_n_0 ),\n .O(\\complex_num_reads[2]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hEA)) \n \\complex_num_reads[2]_i_2 \n (.I0(\\complex_num_reads[3]_i_2_n_0 ),\n .I1(\\complex_num_reads[2]_i_4_n_0 ),\n .I2(\\complex_num_reads[2]_i_6_n_0 ),\n .O(\\complex_num_reads[2]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'h802A)) \n \\complex_num_reads[2]_i_3 \n (.I0(\\complex_num_writes[2]_i_6_n_0 ),\n .I1(\\complex_num_reads_reg_n_0_[1] ),\n .I2(\\complex_num_reads_reg_n_0_[0] ),\n .I3(\\complex_num_reads_reg_n_0_[2] ),\n .O(\\complex_num_reads[2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000008000)) \n \\complex_num_reads[2]_i_4 \n (.I0(\\complex_address[9]_i_4_n_0 ),\n .I1(complex_wait_cnt_reg__0[2]),\n .I2(complex_wait_cnt_reg__0[3]),\n .I3(complex_wait_cnt_reg__0[1]),\n .I4(complex_wait_cnt_reg__0[0]),\n .I5(complex_row0_rd_done),\n .O(\\complex_num_reads[2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFEAAAAAAAAAAAAA)) \n \\complex_num_reads[2]_i_5 \n (.I0(rstdiv0_sync_r1_reg_rep__24),\n .I1(\\complex_num_reads_reg_n_0_[2] ),\n .I2(\\complex_num_reads_reg_n_0_[1] ),\n .I3(\\complex_num_reads_reg_n_0_[3] ),\n .I4(\\complex_num_writes[4]_i_7_n_0 ),\n .I5(\\complex_num_reads[2]_i_4_n_0 ),\n .O(\\complex_num_reads[2]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000200)) \n \\complex_num_reads[2]_i_6 \n (.I0(\\complex_num_writes[2]_i_7_n_0 ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[4] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[5] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[3] ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[1] ),\n .I5(\\stg1_wr_rd_cnt_reg_n_0_[2] ),\n .O(\\complex_num_reads[2]_i_6_n_0 ));\n LUT4 #(\n .INIT(16'h00E2)) \n \\complex_num_reads[3]_i_1 \n (.I0(\\complex_num_reads_reg_n_0_[3] ),\n .I1(\\complex_num_reads[3]_i_2_n_0 ),\n .I2(\\complex_num_reads[3]_i_3_n_0 ),\n .I3(\\complex_num_reads[3]_i_4_n_0 ),\n .O(\\complex_num_reads[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFEFEFE0EFEFEFEFE)) \n \\complex_num_reads[3]_i_2 \n (.I0(\\complex_num_writes[3]_i_4_n_0 ),\n .I1(stg1_wr_done),\n .I2(\\complex_num_reads[2]_i_4_n_0 ),\n .I3(\\complex_num_writes[4]_i_7_n_0 ),\n .I4(\\complex_num_reads[3]_i_5_n_0 ),\n .I5(\\complex_num_reads[3]_i_6_n_0 ),\n .O(\\complex_num_reads[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h8AA8A8A8A8A8A8A8)) \n \\complex_num_reads[3]_i_3 \n (.I0(\\complex_num_reads[2]_i_4_n_0 ),\n .I1(\\complex_num_writes[4]_i_5_n_0 ),\n .I2(\\complex_num_reads_reg_n_0_[3] ),\n .I3(\\complex_num_reads_reg_n_0_[1] ),\n .I4(\\complex_num_reads_reg_n_0_[0] ),\n .I5(\\complex_num_reads_reg_n_0_[2] ),\n .O(\\complex_num_reads[3]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFEF0F0F0FEFFF0F0)) \n \\complex_num_reads[3]_i_4 \n (.I0(\\complex_num_reads_reg_n_0_[3] ),\n .I1(\\complex_num_reads[3]_i_7_n_0 ),\n .I2(rstdiv0_sync_r1_reg_rep__24),\n .I3(\\complex_num_writes[4]_i_7_n_0 ),\n .I4(\\complex_num_reads[2]_i_4_n_0 ),\n .I5(\\complex_num_reads[3]_i_8_n_0 ),\n .O(\\complex_num_reads[3]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair496\" *) \n LUT5 #(\n .INIT(32'hAAAABBBF)) \n \\complex_num_reads[3]_i_5 \n (.I0(\\complex_num_writes[4]_i_5_n_0 ),\n .I1(\\complex_num_reads_reg_n_0_[2] ),\n .I2(\\complex_num_reads_reg_n_0_[0] ),\n .I3(\\complex_num_reads_reg_n_0_[1] ),\n .I4(\\complex_num_reads_reg_n_0_[3] ),\n .O(\\complex_num_reads[3]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'hFEAAEAAA)) \n \\complex_num_reads[3]_i_6 \n (.I0(\\complex_num_writes[4]_i_14_n_0 ),\n .I1(\\complex_num_reads_reg_n_0_[1] ),\n .I2(\\complex_num_reads_reg_n_0_[2] ),\n .I3(\\complex_num_reads_reg_n_0_[3] ),\n .I4(\\complex_num_writes[4]_i_15_n_0 ),\n .O(\\complex_num_reads[3]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair496\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\complex_num_reads[3]_i_7 \n (.I0(\\complex_num_reads_reg_n_0_[2] ),\n .I1(\\complex_num_reads_reg_n_0_[1] ),\n .O(\\complex_num_reads[3]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFDEFFFFFFFFF)) \n \\complex_num_reads[3]_i_8 \n (.I0(\\stg1_wr_rd_cnt_reg_n_0_[4] ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[5] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[3] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[2] ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[1] ),\n .I5(\\complex_num_writes[2]_i_7_n_0 ),\n .O(\\complex_num_reads[3]_i_8_n_0 ));\n LUT3 #(\n .INIT(8'h74)) \n \\complex_num_reads_dec[0]_i_1 \n (.I0(complex_num_reads_dec_reg__0[0]),\n .I1(\\complex_num_reads_dec[3]_i_4_n_0 ),\n .I2(\\complex_num_reads_reg_n_0_[0] ),\n .O(p_0_in__8[0]));\n LUT4 #(\n .INIT(16'h9F90)) \n \\complex_num_reads_dec[1]_i_1 \n (.I0(complex_num_reads_dec_reg__0[1]),\n .I1(complex_num_reads_dec_reg__0[0]),\n .I2(\\complex_num_reads_dec[3]_i_4_n_0 ),\n .I3(\\complex_num_reads_reg_n_0_[1] ),\n .O(p_0_in__8[1]));\n LUT5 #(\n .INIT(32'hA9FFA900)) \n \\complex_num_reads_dec[2]_i_1 \n (.I0(complex_num_reads_dec_reg__0[2]),\n .I1(complex_num_reads_dec_reg__0[0]),\n .I2(complex_num_reads_dec_reg__0[1]),\n .I3(\\complex_num_reads_dec[3]_i_4_n_0 ),\n .I4(\\complex_num_reads_reg_n_0_[2] ),\n .O(p_0_in__8[2]));\n LUT6 #(\n .INIT(64'hDDDDDDDDDDDDDDD5)) \n \\complex_num_reads_dec[3]_i_2 \n (.I0(\\complex_num_reads_dec[3]_i_4_n_0 ),\n .I1(\\stg1_wr_rd_cnt[8]_i_4_n_0 ),\n .I2(complex_num_reads_dec_reg__0[0]),\n .I3(complex_num_reads_dec_reg__0[1]),\n .I4(complex_num_reads_dec_reg__0[2]),\n .I5(complex_num_reads_dec_reg__0[3]),\n .O(\\complex_num_reads_dec[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hAAA9FFFFAAA90000)) \n \\complex_num_reads_dec[3]_i_3 \n (.I0(complex_num_reads_dec_reg__0[3]),\n .I1(complex_num_reads_dec_reg__0[2]),\n .I2(complex_num_reads_dec_reg__0[1]),\n .I3(complex_num_reads_dec_reg__0[0]),\n .I4(\\complex_num_reads_dec[3]_i_4_n_0 ),\n .I5(\\complex_num_reads_reg_n_0_[3] ),\n .O(p_0_in__8[3]));\n LUT6 #(\n .INIT(64'h5545555555555555)) \n \\complex_num_reads_dec[3]_i_4 \n (.I0(\\complex_num_reads_dec[3]_i_5_n_0 ),\n .I1(complex_row0_rd_done),\n .I2(prbs_gen_oclk_clk_en_i_8_n_0),\n .I3(complex_oclkdelay_calib_start_int_i_2_n_0),\n .I4(\\init_state_r_reg[1]_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .O(\\complex_num_reads_dec[3]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF00400000)) \n \\complex_num_reads_dec[3]_i_5 \n (.I0(prbs_rdlvl_start_i_2_n_0),\n .I1(\\wrcal_reads[7]_i_5_n_0 ),\n .I2(Q[3]),\n .I3(Q[5]),\n .I4(Q[4]),\n .I5(stg1_wr_done),\n .O(\\complex_num_reads_dec[3]_i_5_n_0 ));\n FDSE \\complex_num_reads_dec_reg[0] \n (.C(CLK),\n .CE(\\complex_num_reads_dec[3]_i_2_n_0 ),\n .D(p_0_in__8[0]),\n .Q(complex_num_reads_dec_reg__0[0]),\n .S(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\complex_num_reads_dec_reg[1] \n (.C(CLK),\n .CE(\\complex_num_reads_dec[3]_i_2_n_0 ),\n .D(p_0_in__8[1]),\n .Q(complex_num_reads_dec_reg__0[1]),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\complex_num_reads_dec_reg[2] \n (.C(CLK),\n .CE(\\complex_num_reads_dec[3]_i_2_n_0 ),\n .D(p_0_in__8[2]),\n .Q(complex_num_reads_dec_reg__0[2]),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\complex_num_reads_dec_reg[3] \n (.C(CLK),\n .CE(\\complex_num_reads_dec[3]_i_2_n_0 ),\n .D(p_0_in__8[3]),\n .Q(complex_num_reads_dec_reg__0[3]),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\complex_num_reads_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\complex_num_reads[0]_i_1_n_0 ),\n .Q(\\complex_num_reads_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\complex_num_reads_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\complex_num_reads[1]_i_1_n_0 ),\n .Q(\\complex_num_reads_reg_n_0_[1] ),\n .R(1'b0));\n FDRE \\complex_num_reads_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\complex_num_reads[2]_i_1_n_0 ),\n .Q(\\complex_num_reads_reg_n_0_[2] ),\n .R(1'b0));\n FDRE \\complex_num_reads_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\complex_num_reads[3]_i_1_n_0 ),\n .Q(\\complex_num_reads_reg_n_0_[3] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFFFFFFF22622E6E)) \n \\complex_num_writes[0]_i_1 \n (.I0(\\complex_num_writes_reg_n_0_[0] ),\n .I1(\\complex_num_writes[3]_i_2_n_0 ),\n .I2(\\complex_num_writes[4]_i_4_n_0 ),\n .I3(\\complex_num_writes[4]_i_5_n_0 ),\n .I4(\\complex_num_writes[0]_i_2_n_0 ),\n .I5(\\complex_num_writes[4]_i_6_n_0 ),\n .O(\\complex_num_writes[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000200000000000)) \n \\complex_num_writes[0]_i_2 \n (.I0(complex_row0_wr_done),\n .I1(prbs_rdlvl_start_i_2_n_0),\n .I2(\\wrcal_reads[7]_i_5_n_0 ),\n .I3(Q[3]),\n .I4(Q[5]),\n .I5(Q[4]),\n .O(\\complex_num_writes[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FEEE0222)) \n \\complex_num_writes[1]_i_1 \n (.I0(\\complex_num_writes_reg_n_0_[1] ),\n .I1(\\complex_num_writes[2]_i_2_n_0 ),\n .I2(\\complex_num_writes[4]_i_4_n_0 ),\n .I3(\\complex_num_writes[2]_i_4_n_0 ),\n .I4(\\complex_num_writes[1]_i_2_n_0 ),\n .I5(\\complex_num_writes[2]_i_5_n_0 ),\n .O(\\complex_num_writes[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hBAAABABABABABAAA)) \n \\complex_num_writes[1]_i_2 \n (.I0(\\complex_num_writes[0]_i_2_n_0 ),\n .I1(\\complex_num_writes[4]_i_5_n_0 ),\n .I2(\\complex_num_writes[4]_i_4_n_0 ),\n .I3(\\complex_num_writes[4]_i_11_n_0 ),\n .I4(\\complex_num_writes_reg_n_0_[0] ),\n .I5(\\complex_num_writes_reg_n_0_[1] ),\n .O(\\complex_num_writes[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000E2E2E2)) \n \\complex_num_writes[2]_i_1 \n (.I0(\\complex_num_writes_reg_n_0_[2] ),\n .I1(\\complex_num_writes[2]_i_2_n_0 ),\n .I2(\\complex_num_writes[2]_i_3_n_0 ),\n .I3(\\complex_num_writes[4]_i_4_n_0 ),\n .I4(\\complex_num_writes[2]_i_4_n_0 ),\n .I5(\\complex_num_writes[2]_i_5_n_0 ),\n .O(\\complex_num_writes[2]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hBA)) \n \\complex_num_writes[2]_i_2 \n (.I0(\\complex_num_writes[4]_i_2_n_0 ),\n .I1(\\complex_num_writes[2]_i_6_n_0 ),\n .I2(\\complex_num_writes[4]_i_4_n_0 ),\n .O(\\complex_num_writes[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF7FD5FFFF0000)) \n \\complex_num_writes[2]_i_3 \n (.I0(\\complex_num_writes[2]_i_6_n_0 ),\n .I1(\\complex_num_writes_reg_n_0_[1] ),\n .I2(\\complex_num_writes_reg_n_0_[0] ),\n .I3(\\complex_num_writes_reg_n_0_[2] ),\n .I4(\\complex_num_writes[0]_i_2_n_0 ),\n .I5(\\complex_num_writes[4]_i_4_n_0 ),\n .O(\\complex_num_writes[2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0000002000000000)) \n \\complex_num_writes[2]_i_4 \n (.I0(\\complex_num_writes[2]_i_7_n_0 ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[1] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[2] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[3] ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[5] ),\n .I5(\\stg1_wr_rd_cnt_reg_n_0_[4] ),\n .O(\\complex_num_writes[2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFEEEAAAAAAAAAAAA)) \n \\complex_num_writes[2]_i_5 \n (.I0(complex_row0_rd_done1),\n .I1(\\complex_num_writes[2]_i_8_n_0 ),\n .I2(\\complex_num_writes_reg_n_0_[2] ),\n .I3(\\complex_num_writes_reg_n_0_[1] ),\n .I4(\\complex_num_writes[4]_i_7_n_0 ),\n .I5(\\complex_num_writes[4]_i_4_n_0 ),\n .O(\\complex_num_writes[2]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair553\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\complex_num_writes[2]_i_6 \n (.I0(\\complex_num_reads[2]_i_6_n_0 ),\n .I1(\\complex_num_writes[4]_i_5_n_0 ),\n .O(\\complex_num_writes[2]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair561\" *) \n LUT4 #(\n .INIT(16'h1000)) \n \\complex_num_writes[2]_i_7 \n (.I0(\\stg1_wr_rd_cnt_reg_n_0_[8] ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[7] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[0] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[6] ),\n .O(\\complex_num_writes[2]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\complex_num_writes[2]_i_8 \n (.I0(\\complex_num_writes_reg_n_0_[4] ),\n .I1(\\complex_num_writes_reg_n_0_[3] ),\n .O(\\complex_num_writes[2]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'h00000000EEE2E2E2)) \n \\complex_num_writes[3]_i_1 \n (.I0(\\complex_num_writes_reg_n_0_[3] ),\n .I1(\\complex_num_writes[3]_i_2_n_0 ),\n .I2(\\complex_num_writes[3]_i_3_n_0 ),\n .I3(complex_row0_wr_done),\n .I4(\\complex_num_writes[3]_i_4_n_0 ),\n .I5(\\complex_num_writes[4]_i_6_n_0 ),\n .O(\\complex_num_writes[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair573\" *) \n LUT3 #(\n .INIT(8'hF8)) \n \\complex_num_writes[3]_i_2 \n (.I0(\\complex_num_writes[4]_i_5_n_0 ),\n .I1(\\complex_num_writes[4]_i_4_n_0 ),\n .I2(\\complex_num_writes[4]_i_2_n_0 ),\n .O(\\complex_num_writes[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h8AA8A8A8A8A8A8A8)) \n \\complex_num_writes[3]_i_3 \n (.I0(\\complex_num_writes[4]_i_4_n_0 ),\n .I1(\\complex_num_writes[4]_i_5_n_0 ),\n .I2(\\complex_num_writes_reg_n_0_[3] ),\n .I3(\\complex_num_writes_reg_n_0_[1] ),\n .I4(\\complex_num_writes_reg_n_0_[0] ),\n .I5(\\complex_num_writes_reg_n_0_[2] ),\n .O(\\complex_num_writes[3]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000002000)) \n \\complex_num_writes[3]_i_4 \n (.I0(Q[4]),\n .I1(Q[5]),\n .I2(Q[3]),\n .I3(Q[2]),\n .I4(\\init_state_r_reg_n_0_[3] ),\n .I5(prbs_rdlvl_start_i_2_n_0),\n .O(\\complex_num_writes[3]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000E2E2E2)) \n \\complex_num_writes[4]_i_1 \n (.I0(\\complex_num_writes_reg_n_0_[4] ),\n .I1(\\complex_num_writes[4]_i_2_n_0 ),\n .I2(\\complex_num_writes[4]_i_3_n_0 ),\n .I3(\\complex_num_writes[4]_i_4_n_0 ),\n .I4(\\complex_num_writes[4]_i_5_n_0 ),\n .I5(\\complex_num_writes[4]_i_6_n_0 ),\n .O(\\complex_num_writes[4]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair578\" *) \n LUT3 #(\n .INIT(8'h80)) \n \\complex_num_writes[4]_i_10 \n (.I0(\\complex_num_writes_reg_n_0_[2] ),\n .I1(\\complex_num_writes_reg_n_0_[0] ),\n .I2(\\complex_num_writes_reg_n_0_[1] ),\n .O(\\complex_num_writes[4]_i_10_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair573\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\complex_num_writes[4]_i_11 \n (.I0(\\complex_num_reads[3]_i_8_n_0 ),\n .I1(\\complex_num_writes[4]_i_4_n_0 ),\n .I2(\\complex_num_writes[4]_i_7_n_0 ),\n .O(\\complex_num_writes[4]_i_11_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair606\" *) \n LUT2 #(\n .INIT(4'h7)) \n \\complex_num_writes[4]_i_12 \n (.I0(\\stg1_wr_rd_cnt_reg_n_0_[1] ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[2] ),\n .O(\\complex_num_writes[4]_i_12_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\complex_num_writes[4]_i_13 \n (.I0(\\stg1_wr_rd_cnt_reg_n_0_[8] ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[7] ),\n .O(\\complex_num_writes[4]_i_13_n_0 ));\n LUT6 #(\n .INIT(64'hEEEEEEECEEECEEEC)) \n \\complex_num_writes[4]_i_14 \n (.I0(\\stg1_wr_rd_cnt_reg_n_0_[6] ),\n .I1(\\complex_num_writes[4]_i_13_n_0 ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[4] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[5] ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[3] ),\n .I5(\\stg1_wr_rd_cnt[4]_i_3_n_0 ),\n .O(\\complex_num_writes[4]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'hFFFEFFFEFFFEFEFE)) \n \\complex_num_writes[4]_i_15 \n (.I0(\\stg1_wr_rd_cnt_reg_n_0_[8] ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[7] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[6] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[5] ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[4] ),\n .I5(\\stg1_wr_rd_cnt_reg_n_0_[3] ),\n .O(\\complex_num_writes[4]_i_15_n_0 ));\n LUT5 #(\n .INIT(32'hEEE2EEEE)) \n \\complex_num_writes[4]_i_2 \n (.I0(\\complex_num_writes[3]_i_4_n_0 ),\n .I1(\\complex_num_writes[4]_i_4_n_0 ),\n .I2(\\complex_num_writes[4]_i_7_n_0 ),\n .I3(\\complex_num_writes[4]_i_8_n_0 ),\n .I4(\\complex_num_writes[4]_i_9_n_0 ),\n .O(\\complex_num_writes[4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFF6A6A6AFF000000)) \n \\complex_num_writes[4]_i_3 \n (.I0(\\complex_num_writes_reg_n_0_[4] ),\n .I1(\\complex_num_writes_reg_n_0_[3] ),\n .I2(\\complex_num_writes[4]_i_10_n_0 ),\n .I3(complex_row0_wr_done),\n .I4(\\complex_num_writes[3]_i_4_n_0 ),\n .I5(\\complex_num_writes[4]_i_4_n_0 ),\n .O(\\complex_num_writes[4]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000008000)) \n \\complex_num_writes[4]_i_4 \n (.I0(\\complex_address[9]_i_3_n_0 ),\n .I1(complex_wait_cnt_reg__0[2]),\n .I2(complex_wait_cnt_reg__0[3]),\n .I3(complex_wait_cnt_reg__0[1]),\n .I4(complex_wait_cnt_reg__0[0]),\n .I5(complex_row0_wr_done),\n .O(\\complex_num_writes[4]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair489\" *) \n LUT5 #(\n .INIT(32'h40000000)) \n \\complex_num_writes[4]_i_5 \n (.I0(wr_victim_inc_i_3_n_0),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[0] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[5] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[1] ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[2] ),\n .O(\\complex_num_writes[4]_i_5_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\complex_num_writes[4]_i_6 \n (.I0(\\complex_num_writes[2]_i_5_n_0 ),\n .I1(\\complex_num_writes[4]_i_11_n_0 ),\n .O(\\complex_num_writes[4]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF008A00)) \n \\complex_num_writes[4]_i_7 \n (.I0(\\stg1_wr_rd_cnt_reg_n_0_[4] ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[3] ),\n .I2(\\complex_num_writes[4]_i_12_n_0 ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[6] ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[5] ),\n .I5(\\complex_num_writes[4]_i_13_n_0 ),\n .O(\\complex_num_writes[4]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h000000000000222A)) \n \\complex_num_writes[4]_i_8 \n (.I0(\\complex_num_writes[4]_i_14_n_0 ),\n .I1(\\complex_num_writes_reg_n_0_[2] ),\n .I2(\\complex_num_writes_reg_n_0_[0] ),\n .I3(\\complex_num_writes_reg_n_0_[1] ),\n .I4(\\complex_num_writes_reg_n_0_[4] ),\n .I5(\\complex_num_writes_reg_n_0_[3] ),\n .O(\\complex_num_writes[4]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFE080)) \n \\complex_num_writes[4]_i_9 \n (.I0(\\complex_num_writes_reg_n_0_[1] ),\n .I1(\\complex_num_writes_reg_n_0_[2] ),\n .I2(\\complex_num_writes_reg_n_0_[3] ),\n .I3(\\complex_num_writes[4]_i_15_n_0 ),\n .I4(\\complex_num_writes[4]_i_14_n_0 ),\n .I5(\\complex_num_writes_reg_n_0_[4] ),\n .O(\\complex_num_writes[4]_i_9_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair578\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\complex_num_writes_dec[0]_i_1 \n (.I0(complex_num_writes_dec_reg__0[0]),\n .I1(\\complex_num_writes_dec[4]_i_4_n_0 ),\n .I2(\\complex_num_writes_reg_n_0_[0] ),\n .O(p_0_in__7[0]));\n LUT4 #(\n .INIT(16'h9F90)) \n \\complex_num_writes_dec[1]_i_1 \n (.I0(complex_num_writes_dec_reg__0[0]),\n .I1(complex_num_writes_dec_reg__0[1]),\n .I2(\\complex_num_writes_dec[4]_i_4_n_0 ),\n .I3(\\complex_num_writes_reg_n_0_[1] ),\n .O(p_0_in__7[1]));\n (* SOFT_HLUTNM = \"soft_lutpair491\" *) \n LUT5 #(\n .INIT(32'hA9FFA900)) \n \\complex_num_writes_dec[2]_i_1 \n (.I0(complex_num_writes_dec_reg__0[2]),\n .I1(complex_num_writes_dec_reg__0[1]),\n .I2(complex_num_writes_dec_reg__0[0]),\n .I3(\\complex_num_writes_dec[4]_i_4_n_0 ),\n .I4(\\complex_num_writes_reg_n_0_[2] ),\n .O(p_0_in__7[2]));\n LUT6 #(\n .INIT(64'hAAA9FFFFAAA90000)) \n \\complex_num_writes_dec[3]_i_1 \n (.I0(complex_num_writes_dec_reg__0[3]),\n .I1(complex_num_writes_dec_reg__0[2]),\n .I2(complex_num_writes_dec_reg__0[0]),\n .I3(complex_num_writes_dec_reg__0[1]),\n .I4(\\complex_num_writes_dec[4]_i_4_n_0 ),\n .I5(\\complex_num_writes_reg_n_0_[3] ),\n .O(p_0_in__7[3]));\n LUT2 #(\n .INIT(4'hE)) \n \\complex_num_writes_dec[4]_i_1 \n (.I0(prbs_rdlvl_done_pulse),\n .I1(rstdiv0_sync_r1_reg_rep__24),\n .O(complex_row0_rd_done1));\n LUT5 #(\n .INIT(32'hDDDDDDD5)) \n \\complex_num_writes_dec[4]_i_2 \n (.I0(\\complex_num_writes_dec[4]_i_4_n_0 ),\n .I1(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .I2(complex_num_writes_dec_reg__0[1]),\n .I3(complex_num_writes_dec_reg__0[0]),\n .I4(\\complex_num_writes_dec[4]_i_5_n_0 ),\n .O(\\complex_num_writes_dec[4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hAA9AFFFFAA9A0000)) \n \\complex_num_writes_dec[4]_i_3 \n (.I0(complex_num_writes_dec_reg__0[4]),\n .I1(complex_num_writes_dec_reg__0[3]),\n .I2(\\complex_num_writes_dec[4]_i_6_n_0 ),\n .I3(complex_num_writes_dec_reg__0[2]),\n .I4(\\complex_num_writes_dec[4]_i_4_n_0 ),\n .I5(\\complex_num_writes_reg_n_0_[4] ),\n .O(p_0_in__7[4]));\n LUT5 #(\n .INIT(32'h10111111)) \n \\complex_num_writes_dec[4]_i_4 \n (.I0(stg1_wr_done),\n .I1(\\complex_num_writes[3]_i_4_n_0 ),\n .I2(complex_row0_rd_done),\n .I3(prbs_gen_oclk_clk_en_i_8_n_0),\n .I4(\\complex_address[9]_i_3_n_0 ),\n .O(\\complex_num_writes_dec[4]_i_4_n_0 ));\n LUT3 #(\n .INIT(8'hFE)) \n \\complex_num_writes_dec[4]_i_5 \n (.I0(complex_num_writes_dec_reg__0[3]),\n .I1(complex_num_writes_dec_reg__0[2]),\n .I2(complex_num_writes_dec_reg__0[4]),\n .O(\\complex_num_writes_dec[4]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair491\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\complex_num_writes_dec[4]_i_6 \n (.I0(complex_num_writes_dec_reg__0[0]),\n .I1(complex_num_writes_dec_reg__0[1]),\n .O(\\complex_num_writes_dec[4]_i_6_n_0 ));\n FDSE \\complex_num_writes_dec_reg[0] \n (.C(CLK),\n .CE(\\complex_num_writes_dec[4]_i_2_n_0 ),\n .D(p_0_in__7[0]),\n .Q(complex_num_writes_dec_reg__0[0]),\n .S(complex_row0_rd_done1));\n FDRE \\complex_num_writes_dec_reg[1] \n (.C(CLK),\n .CE(\\complex_num_writes_dec[4]_i_2_n_0 ),\n .D(p_0_in__7[1]),\n .Q(complex_num_writes_dec_reg__0[1]),\n .R(complex_row0_rd_done1));\n FDRE \\complex_num_writes_dec_reg[2] \n (.C(CLK),\n .CE(\\complex_num_writes_dec[4]_i_2_n_0 ),\n .D(p_0_in__7[2]),\n .Q(complex_num_writes_dec_reg__0[2]),\n .R(complex_row0_rd_done1));\n FDRE \\complex_num_writes_dec_reg[3] \n (.C(CLK),\n .CE(\\complex_num_writes_dec[4]_i_2_n_0 ),\n .D(p_0_in__7[3]),\n .Q(complex_num_writes_dec_reg__0[3]),\n .R(complex_row0_rd_done1));\n FDRE \\complex_num_writes_dec_reg[4] \n (.C(CLK),\n .CE(\\complex_num_writes_dec[4]_i_2_n_0 ),\n .D(p_0_in__7[4]),\n .Q(complex_num_writes_dec_reg__0[4]),\n .R(complex_row0_rd_done1));\n FDRE \\complex_num_writes_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\complex_num_writes[0]_i_1_n_0 ),\n .Q(\\complex_num_writes_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\complex_num_writes_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\complex_num_writes[1]_i_1_n_0 ),\n .Q(\\complex_num_writes_reg_n_0_[1] ),\n .R(1'b0));\n FDRE \\complex_num_writes_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\complex_num_writes[2]_i_1_n_0 ),\n .Q(\\complex_num_writes_reg_n_0_[2] ),\n .R(1'b0));\n FDRE \\complex_num_writes_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\complex_num_writes[3]_i_1_n_0 ),\n .Q(\\complex_num_writes_reg_n_0_[3] ),\n .R(1'b0));\n FDRE \\complex_num_writes_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\complex_num_writes[4]_i_1_n_0 ),\n .Q(\\complex_num_writes_reg_n_0_[4] ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h0000AABA)) \n complex_ocal_odt_ext_i_1\n (.I0(complex_ocal_odt_ext),\n .I1(complex_ocal_odt_ext_i_2_n_0),\n .I2(Q[5]),\n .I3(Q[1]),\n .I4(complex_ocal_odt_ext_i_3_n_0),\n .O(complex_ocal_odt_ext_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair541\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n complex_ocal_odt_ext_i_2\n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(Q[2]),\n .I2(Q[3]),\n .I3(Q[4]),\n .O(complex_ocal_odt_ext_i_2_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFF400040F0)) \n complex_ocal_odt_ext_i_3\n (.I0(\\back_to_back_reads_4_1.num_reads_reg[0]_0 ),\n .I1(cnt_cmd_done_m7_r),\n .I2(Q[1]),\n .I3(Q[0]),\n .I4(complex_ocal_odt_ext_i_4_n_0),\n .I5(rstdiv0_sync_r1_reg_rep__24),\n .O(complex_ocal_odt_ext_i_3_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair521\" *) \n LUT5 #(\n .INIT(32'hFFEFFFFF)) \n complex_ocal_odt_ext_i_4\n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(Q[2]),\n .I2(Q[3]),\n .I3(Q[5]),\n .I4(Q[4]),\n .O(complex_ocal_odt_ext_i_4_n_0));\n FDRE complex_ocal_odt_ext_reg\n (.C(CLK),\n .CE(1'b1),\n .D(complex_ocal_odt_ext_i_1_n_0),\n .Q(complex_ocal_odt_ext),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h44444F4444444444)) \n complex_ocal_reset_rd_addr_i_1\n (.I0(prbs_last_byte_done_r),\n .I1(prbs_last_byte_done),\n .I2(complex_ocal_reset_rd_addr_i_2_n_0),\n .I3(complex_wait_cnt_reg__0[3]),\n .I4(complex_wait_cnt_reg__0[2]),\n .I5(complex_ocal_reset_rd_addr_i_3_n_0),\n .O(complex_ocal_reset_rd_addr0));\n (* SOFT_HLUTNM = \"soft_lutpair605\" *) \n LUT2 #(\n .INIT(4'hB)) \n complex_ocal_reset_rd_addr_i_2\n (.I0(complex_wait_cnt_reg__0[1]),\n .I1(complex_wait_cnt_reg__0[0]),\n .O(complex_ocal_reset_rd_addr_i_2_n_0));\n LUT6 #(\n .INIT(64'h0000000000000020)) \n complex_ocal_reset_rd_addr_i_3\n (.I0(Q[4]),\n .I1(Q[5]),\n .I2(Q[3]),\n .I3(\\init_state_r[4]_i_5_n_0 ),\n .I4(Q[1]),\n .I5(Q[0]),\n .O(complex_ocal_reset_rd_addr_i_3_n_0));\n FDRE complex_ocal_reset_rd_addr_reg\n (.C(CLK),\n .CE(1'b1),\n .D(complex_ocal_reset_rd_addr0),\n .Q(complex_ocal_reset_rd_addr),\n .R(1'b0));\n LUT2 #(\n .INIT(4'hE)) \n complex_ocal_wr_start_i_1\n (.I0(complex_ocal_reset_rd_addr),\n .I1(complex_ocal_wr_start),\n .O(complex_ocal_wr_start_i_1_n_0));\n FDRE complex_ocal_wr_start_reg\n (.C(CLK),\n .CE(1'b1),\n .D(complex_ocal_wr_start_i_1_n_0),\n .Q(complex_ocal_wr_start),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE complex_oclkdelay_calib_done_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prbs_rdlvl_done_reg_rep),\n .Q(complex_oclkdelay_calib_done_r1),\n .R(rstdiv0_sync_r1_reg_rep__11));\n LUT6 #(\n .INIT(64'hFFFFFFFF00040000)) \n complex_oclkdelay_calib_start_int_i_1\n (.I0(complex_oclkdelay_calib_start_int_i_2_n_0),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .I2(Q[2]),\n .I3(complex_oclkdelay_calib_start_int_reg_0),\n .I4(prbs_last_byte_done_r),\n .I5(complex_oclkdelay_calib_start_int),\n .O(complex_oclkdelay_calib_start_int_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair572\" *) \n LUT3 #(\n .INIT(8'hDF)) \n complex_oclkdelay_calib_start_int_i_2\n (.I0(Q[4]),\n .I1(Q[5]),\n .I2(Q[3]),\n .O(complex_oclkdelay_calib_start_int_i_2_n_0));\n LUT2 #(\n .INIT(4'hB)) \n complex_oclkdelay_calib_start_int_i_3\n (.I0(Q[0]),\n .I1(Q[1]),\n .O(complex_oclkdelay_calib_start_int_reg_0));\n FDRE complex_oclkdelay_calib_start_int_reg\n (.C(CLK),\n .CE(1'b1),\n .D(complex_oclkdelay_calib_start_int_i_1_n_0),\n .Q(complex_oclkdelay_calib_start_int),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE complex_oclkdelay_calib_start_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(complex_oclkdelay_calib_start_int),\n .Q(complex_oclkdelay_calib_start_r1),\n .R(1'b0));\n FDRE complex_oclkdelay_calib_start_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(complex_oclkdelay_calib_start_r1),\n .Q(complex_oclkdelay_calib_start_r2),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h000000000000AAEA)) \n complex_odt_ext_i_1\n (.I0(complex_odt_ext),\n .I1(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .I2(rdlvl_stg1_done_r1),\n .I3(complex_sample_cnt_inc_i_2_n_0),\n .I4(complex_row1_rd_done_i_2_n_0),\n .I5(rstdiv0_sync_r1_reg_rep__24),\n .O(complex_odt_ext_i_1_n_0));\n FDRE complex_odt_ext_reg\n (.C(CLK),\n .CE(1'b1),\n .D(complex_odt_ext_i_1_n_0),\n .Q(complex_odt_ext),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair560\" *) \n LUT4 #(\n .INIT(16'h0002)) \n complex_row0_rd_done_i_1\n (.I0(complex_row0_rd_done_i_2_n_0),\n .I1(prbs_rdlvl_done_pulse),\n .I2(rstdiv0_sync_r1_reg_rep__25),\n .I3(complex_sample_cnt_inc),\n .O(complex_row0_rd_done_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFF0000E000)) \n complex_row0_rd_done_i_2\n (.I0(prbs_rdlvl_start_r_reg),\n .I1(complex_oclkdelay_calib_start_int),\n .I2(complex_row1_wr_done),\n .I3(complex_row0_wr_done),\n .I4(wr_victim_inc_i_2_n_0),\n .I5(complex_row0_rd_done),\n .O(complex_row0_rd_done_i_2_n_0));\n FDRE complex_row0_rd_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(complex_row0_rd_done_i_1_n_0),\n .Q(complex_row0_rd_done),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h0000009A)) \n \\complex_row1_rd_cnt[0]_i_1 \n (.I0(complex_row1_rd_cnt[0]),\n .I1(complex_row1_rd_done_r1),\n .I2(complex_row1_rd_done),\n .I3(rstdiv0_sync_r1_reg_rep__25),\n .I4(prbs_rdlvl_done_pulse),\n .O(\\complex_row1_rd_cnt[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000009AAA)) \n \\complex_row1_rd_cnt[1]_i_1 \n (.I0(complex_row1_rd_cnt[1]),\n .I1(complex_row1_rd_done_r1),\n .I2(complex_row1_rd_done),\n .I3(complex_row1_rd_cnt[0]),\n .I4(rstdiv0_sync_r1_reg_rep__25),\n .I5(prbs_rdlvl_done_pulse),\n .O(\\complex_row1_rd_cnt[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h000000009AAAAAAA)) \n \\complex_row1_rd_cnt[2]_i_1 \n (.I0(complex_row1_rd_cnt[2]),\n .I1(complex_row1_rd_done_r1),\n .I2(complex_row1_rd_done),\n .I3(complex_row1_rd_cnt[0]),\n .I4(complex_row1_rd_cnt[1]),\n .I5(complex_row0_rd_done1),\n .O(\\complex_row1_rd_cnt[2]_i_1_n_0 ));\n FDRE \\complex_row1_rd_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\complex_row1_rd_cnt[0]_i_1_n_0 ),\n .Q(complex_row1_rd_cnt[0]),\n .R(1'b0));\n FDRE \\complex_row1_rd_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\complex_row1_rd_cnt[1]_i_1_n_0 ),\n .Q(complex_row1_rd_cnt[1]),\n .R(1'b0));\n FDRE \\complex_row1_rd_cnt_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\complex_row1_rd_cnt[2]_i_1_n_0 ),\n .Q(complex_row1_rd_cnt[2]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000000000AE)) \n complex_row1_rd_done_i_1\n (.I0(complex_row1_rd_done),\n .I1(complex_row0_rd_done),\n .I2(wr_victim_inc_i_2_n_0),\n .I3(complex_row1_rd_done_i_2_n_0),\n .I4(prbs_rdlvl_done_pulse),\n .I5(rstdiv0_sync_r1_reg_rep__25),\n .O(complex_row1_rd_done_i_1_n_0));\n LUT6 #(\n .INIT(64'h0000000000100000)) \n complex_row1_rd_done_i_2\n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(Q[2]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[3]),\n .I5(Q[5]),\n .O(complex_row1_rd_done_i_2_n_0));\n FDRE complex_row1_rd_done_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(complex_row1_rd_done),\n .Q(complex_row1_rd_done_r1),\n .R(1'b0));\n FDRE complex_row1_rd_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(complex_row1_rd_done_i_1_n_0),\n .Q(complex_row1_rd_done),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair612\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\complex_row_cnt_ocal[0]_i_1 \n (.I0(complex_row_cnt_ocal_reg__0[0]),\n .O(p_0_in__5[0]));\n (* SOFT_HLUTNM = \"soft_lutpair612\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\complex_row_cnt_ocal[1]_i_1 \n (.I0(complex_row_cnt_ocal_reg__0[1]),\n .I1(complex_row_cnt_ocal_reg__0[0]),\n .O(p_0_in__5[1]));\n (* SOFT_HLUTNM = \"soft_lutpair563\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\complex_row_cnt_ocal[2]_i_1 \n (.I0(complex_row_cnt_ocal_reg__0[2]),\n .I1(complex_row_cnt_ocal_reg__0[0]),\n .I2(complex_row_cnt_ocal_reg__0[1]),\n .O(p_0_in__5[2]));\n (* SOFT_HLUTNM = \"soft_lutpair563\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\complex_row_cnt_ocal[3]_i_1 \n (.I0(complex_row_cnt_ocal_reg__0[3]),\n .I1(complex_row_cnt_ocal_reg__0[1]),\n .I2(complex_row_cnt_ocal_reg__0[0]),\n .I3(complex_row_cnt_ocal_reg__0[2]),\n .O(p_0_in__5[3]));\n (* SOFT_HLUTNM = \"soft_lutpair483\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\complex_row_cnt_ocal[4]_i_1 \n (.I0(complex_row_cnt_ocal_reg__0[4]),\n .I1(complex_row_cnt_ocal_reg__0[3]),\n .I2(complex_row_cnt_ocal_reg__0[2]),\n .I3(complex_row_cnt_ocal_reg__0[0]),\n .I4(complex_row_cnt_ocal_reg__0[1]),\n .O(p_0_in__5[4]));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n \\complex_row_cnt_ocal[5]_i_1 \n (.I0(complex_row_cnt_ocal_reg__0[5]),\n .I1(complex_row_cnt_ocal_reg__0[1]),\n .I2(complex_row_cnt_ocal_reg__0[0]),\n .I3(complex_row_cnt_ocal_reg__0[2]),\n .I4(complex_row_cnt_ocal_reg__0[3]),\n .I5(complex_row_cnt_ocal_reg__0[4]),\n .O(p_0_in__5[5]));\n (* SOFT_HLUTNM = \"soft_lutpair512\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\complex_row_cnt_ocal[6]_i_1 \n (.I0(complex_row_cnt_ocal_reg__0[6]),\n .I1(complex_row_cnt_ocal_reg__0[4]),\n .I2(\\complex_row_cnt_ocal[7]_i_8_n_0 ),\n .I3(complex_row_cnt_ocal_reg__0[5]),\n .O(p_0_in__5[6]));\n LUT5 #(\n .INIT(32'hFFFFFFFB)) \n \\complex_row_cnt_ocal[7]_i_1 \n (.I0(\\complex_row_cnt_ocal_reg[0]_0 ),\n .I1(rdlvl_stg1_done_r1),\n .I2(complex_byte_rd_done),\n .I3(rstdiv0_sync_r1_reg_rep__24),\n .I4(prbs_rdlvl_done_pulse),\n .O(complex_row_cnt_ocal0));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAA0800)) \n \\complex_row_cnt_ocal[7]_i_2 \n (.I0(\\complex_row_cnt_ocal[7]_i_5_n_0 ),\n .I1(\\complex_row_cnt_ocal[7]_i_6_n_0 ),\n .I2(\\complex_row_cnt_ocal[7]_i_7_n_0 ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[3] ),\n .I4(wr_victim_inc),\n .I5(complex_sample_cnt_inc_r2),\n .O(complex_row_cnt_ocal));\n (* SOFT_HLUTNM = \"soft_lutpair512\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\complex_row_cnt_ocal[7]_i_3 \n (.I0(complex_row_cnt_ocal_reg__0[7]),\n .I1(complex_row_cnt_ocal_reg__0[5]),\n .I2(\\complex_row_cnt_ocal[7]_i_8_n_0 ),\n .I3(complex_row_cnt_ocal_reg__0[4]),\n .I4(complex_row_cnt_ocal_reg__0[6]),\n .O(p_0_in__5[7]));\n LUT6 #(\n .INIT(64'h0000000000000008)) \n \\complex_row_cnt_ocal[7]_i_4 \n (.I0(\\complex_row_cnt_ocal[7]_i_8_n_0 ),\n .I1(wr_victim_inc),\n .I2(complex_row_cnt_ocal_reg__0[4]),\n .I3(complex_row_cnt_ocal_reg__0[7]),\n .I4(complex_row_cnt_ocal_reg__0[5]),\n .I5(complex_row_cnt_ocal_reg__0[6]),\n .O(\\complex_row_cnt_ocal_reg[0]_0 ));\n LUT6 #(\n .INIT(64'h0000000000000004)) \n \\complex_row_cnt_ocal[7]_i_5 \n (.I0(\\complex_row_cnt_ocal[7]_i_8_n_0 ),\n .I1(prbs_rdlvl_done_reg_rep),\n .I2(complex_row_cnt_ocal_reg__0[4]),\n .I3(complex_row_cnt_ocal_reg__0[7]),\n .I4(complex_row_cnt_ocal_reg__0[5]),\n .I5(complex_row_cnt_ocal_reg__0[6]),\n .O(\\complex_row_cnt_ocal[7]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000002000)) \n \\complex_row_cnt_ocal[7]_i_6 \n (.I0(Q[4]),\n .I1(Q[5]),\n .I2(Q[3]),\n .I3(\\wrcal_reads[7]_i_5_n_0 ),\n .I4(Q[1]),\n .I5(Q[0]),\n .O(\\complex_row_cnt_ocal[7]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFBFFFFFFFFFF)) \n \\complex_row_cnt_ocal[7]_i_7 \n (.I0(\\complex_row_cnt_ocal[7]_i_9_n_0 ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[4] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[5] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[2] ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[0] ),\n .I5(\\stg1_wr_rd_cnt_reg_n_0_[1] ),\n .O(\\complex_row_cnt_ocal[7]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair483\" *) \n LUT4 #(\n .INIT(16'h8000)) \n \\complex_row_cnt_ocal[7]_i_8 \n (.I0(complex_row_cnt_ocal_reg__0[1]),\n .I1(complex_row_cnt_ocal_reg__0[0]),\n .I2(complex_row_cnt_ocal_reg__0[2]),\n .I3(complex_row_cnt_ocal_reg__0[3]),\n .O(\\complex_row_cnt_ocal[7]_i_8_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair517\" *) \n LUT3 #(\n .INIT(8'hFE)) \n \\complex_row_cnt_ocal[7]_i_9 \n (.I0(\\stg1_wr_rd_cnt_reg_n_0_[6] ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[7] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[8] ),\n .O(\\complex_row_cnt_ocal[7]_i_9_n_0 ));\n FDRE \\complex_row_cnt_ocal_reg[0] \n (.C(CLK),\n .CE(complex_row_cnt_ocal),\n .D(p_0_in__5[0]),\n .Q(complex_row_cnt_ocal_reg__0[0]),\n .R(complex_row_cnt_ocal0));\n FDRE \\complex_row_cnt_ocal_reg[1] \n (.C(CLK),\n .CE(complex_row_cnt_ocal),\n .D(p_0_in__5[1]),\n .Q(complex_row_cnt_ocal_reg__0[1]),\n .R(complex_row_cnt_ocal0));\n FDRE \\complex_row_cnt_ocal_reg[2] \n (.C(CLK),\n .CE(complex_row_cnt_ocal),\n .D(p_0_in__5[2]),\n .Q(complex_row_cnt_ocal_reg__0[2]),\n .R(complex_row_cnt_ocal0));\n FDRE \\complex_row_cnt_ocal_reg[3] \n (.C(CLK),\n .CE(complex_row_cnt_ocal),\n .D(p_0_in__5[3]),\n .Q(complex_row_cnt_ocal_reg__0[3]),\n .R(complex_row_cnt_ocal0));\n FDRE \\complex_row_cnt_ocal_reg[4] \n (.C(CLK),\n .CE(complex_row_cnt_ocal),\n .D(p_0_in__5[4]),\n .Q(complex_row_cnt_ocal_reg__0[4]),\n .R(complex_row_cnt_ocal0));\n FDRE \\complex_row_cnt_ocal_reg[5] \n (.C(CLK),\n .CE(complex_row_cnt_ocal),\n .D(p_0_in__5[5]),\n .Q(complex_row_cnt_ocal_reg__0[5]),\n .R(complex_row_cnt_ocal0));\n FDRE \\complex_row_cnt_ocal_reg[6] \n (.C(CLK),\n .CE(complex_row_cnt_ocal),\n .D(p_0_in__5[6]),\n .Q(complex_row_cnt_ocal_reg__0[6]),\n .R(complex_row_cnt_ocal0));\n FDRE \\complex_row_cnt_ocal_reg[7] \n (.C(CLK),\n .CE(complex_row_cnt_ocal),\n .D(p_0_in__5[7]),\n .Q(complex_row_cnt_ocal_reg__0[7]),\n .R(complex_row_cnt_ocal0));\n LUT2 #(\n .INIT(4'h2)) \n complex_sample_cnt_inc_i_1\n (.I0(complex_row1_rd_done),\n .I1(complex_sample_cnt_inc_i_2_n_0),\n .O(complex_sample_cnt_inc0));\n (* SOFT_HLUTNM = \"soft_lutpair489\" *) \n LUT5 #(\n .INIT(32'hFFFFFFEF)) \n complex_sample_cnt_inc_i_2\n (.I0(wr_victim_inc_i_3_n_0),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[5] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[0] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[1] ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[2] ),\n .O(complex_sample_cnt_inc_i_2_n_0));\n FDRE complex_sample_cnt_inc_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(complex_sample_cnt_inc),\n .Q(complex_sample_cnt_inc_r1),\n .R(1'b0));\n FDRE complex_sample_cnt_inc_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(complex_sample_cnt_inc_r1),\n .Q(complex_sample_cnt_inc_r2),\n .R(1'b0));\n FDRE complex_sample_cnt_inc_reg\n (.C(CLK),\n .CE(1'b1),\n .D(complex_sample_cnt_inc0),\n .Q(complex_sample_cnt_inc),\n .R(rstdiv0_sync_r1_reg_rep__12));\n LUT1 #(\n .INIT(2'h1)) \n \\complex_wait_cnt[0]_i_1 \n (.I0(complex_wait_cnt_reg__0[0]),\n .O(p_0_in__6[0]));\n (* SOFT_HLUTNM = \"soft_lutpair605\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\complex_wait_cnt[1]_i_1 \n (.I0(complex_wait_cnt_reg__0[1]),\n .I1(complex_wait_cnt_reg__0[0]),\n .O(p_0_in__6[1]));\n (* SOFT_HLUTNM = \"soft_lutpair557\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\complex_wait_cnt[2]_i_1 \n (.I0(complex_wait_cnt_reg__0[1]),\n .I1(complex_wait_cnt_reg__0[0]),\n .I2(complex_wait_cnt_reg__0[2]),\n .O(p_0_in__6[2]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFBABEFBF)) \n \\complex_wait_cnt[3]_i_1 \n (.I0(complex_oclkdelay_calib_start_int_i_2_n_0),\n .I1(Q[2]),\n .I2(\\init_state_r_reg_n_0_[3] ),\n .I3(Q[1]),\n .I4(Q[0]),\n .I5(\\complex_wait_cnt[3]_i_3_n_0 ),\n .O(\\complex_wait_cnt[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair557\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\complex_wait_cnt[3]_i_2 \n (.I0(complex_wait_cnt_reg__0[3]),\n .I1(complex_wait_cnt_reg__0[1]),\n .I2(complex_wait_cnt_reg__0[0]),\n .I3(complex_wait_cnt_reg__0[2]),\n .O(p_0_in__6[3]));\n (* SOFT_HLUTNM = \"soft_lutpair505\" *) \n LUT5 #(\n .INIT(32'hEAAAAAAA)) \n \\complex_wait_cnt[3]_i_3 \n (.I0(rstdiv0_sync_r1_reg_rep__24),\n .I1(complex_wait_cnt_reg__0[3]),\n .I2(complex_wait_cnt_reg__0[2]),\n .I3(complex_wait_cnt_reg__0[1]),\n .I4(complex_wait_cnt_reg__0[0]),\n .O(\\complex_wait_cnt[3]_i_3_n_0 ));\n FDRE \\complex_wait_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__6[0]),\n .Q(complex_wait_cnt_reg__0[0]),\n .R(\\complex_wait_cnt[3]_i_1_n_0 ));\n FDRE \\complex_wait_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__6[1]),\n .Q(complex_wait_cnt_reg__0[1]),\n .R(\\complex_wait_cnt[3]_i_1_n_0 ));\n FDRE \\complex_wait_cnt_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__6[2]),\n .Q(complex_wait_cnt_reg__0[2]),\n .R(\\complex_wait_cnt[3]_i_1_n_0 ));\n FDRE \\complex_wait_cnt_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__6[3]),\n .Q(complex_wait_cnt_reg__0[3]),\n .R(\\complex_wait_cnt[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair588\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\data_offset_1_i1[0]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_1_reg[0] ),\n .I1(init_calib_complete_reg_rep__14),\n .I2(calib_data_offset_1[0]),\n .O(\\data_offset_1_i1_reg[5] [0]));\n (* SOFT_HLUTNM = \"soft_lutpair589\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\data_offset_1_i1[1]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_1_reg[1] ),\n .I1(init_calib_complete_reg_rep__14),\n .I2(calib_data_offset_1[1]),\n .O(\\data_offset_1_i1_reg[5] [1]));\n (* SOFT_HLUTNM = \"soft_lutpair590\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\data_offset_1_i1[2]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_1_reg[2] ),\n .I1(init_calib_complete_reg_rep__14),\n .I2(calib_data_offset_1[2]),\n .O(\\data_offset_1_i1_reg[5] [2]));\n (* SOFT_HLUTNM = \"soft_lutpair591\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\data_offset_1_i1[3]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_1_reg[3] ),\n .I1(init_calib_complete_reg_rep__14),\n .I2(calib_data_offset_1[3]),\n .O(\\data_offset_1_i1_reg[5] [3]));\n (* SOFT_HLUTNM = \"soft_lutpair590\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\data_offset_1_i1[4]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_1_reg[4] ),\n .I1(init_calib_complete_reg_rep__14),\n .I2(calib_data_offset_1[4]),\n .O(\\data_offset_1_i1_reg[5] [4]));\n (* SOFT_HLUTNM = \"soft_lutpair589\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\data_offset_1_i1[5]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_1_reg[5] ),\n .I1(init_calib_complete_reg_rep__14),\n .I2(calib_data_offset_1[5]),\n .O(\\data_offset_1_i1_reg[5] [5]));\n (* SOFT_HLUTNM = \"soft_lutpair539\" *) \n LUT4 #(\n .INIT(16'h8000)) \n ddr2_pre_flag_r_i_2\n (.I0(ddr2_refresh_flag_r_reg_0),\n .I1(cnt_cmd_done_r),\n .I2(ddr2_refresh_flag_r),\n .I3(cnt_init_mr_done_r),\n .O(ddr2_pre_flag_r_reg_1));\n FDRE ddr2_pre_flag_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(ddr2_pre_flag_r_reg_2),\n .Q(ddr2_pre_flag_r_reg_0),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0000010000000000)) \n ddr2_refresh_flag_r_i_2\n (.I0(oclk_calib_resume_level_reg_0),\n .I1(Q[5]),\n .I2(Q[4]),\n .I3(Q[0]),\n .I4(Q[3]),\n .I5(Q[1]),\n .O(ddr2_refresh_flag_r_reg_0));\n FDRE ddr2_refresh_flag_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cnt_cmd_done_r_reg_0),\n .Q(ddr2_refresh_flag_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFFFFFFF00000200)) \n ddr3_lm_done_r_i_1\n (.I0(wrcal_done_reg_10),\n .I1(oclk_calib_resume_level_reg_0),\n .I2(\\init_state_r[5]_i_2_n_0 ),\n .I3(Q[0]),\n .I4(ddr3_lm_done_r_i_2_n_0),\n .I5(ddr3_lm_done_r),\n .O(ddr3_lm_done_r_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair498\" *) \n LUT2 #(\n .INIT(4'hB)) \n ddr3_lm_done_r_i_2\n (.I0(Q[3]),\n .I1(Q[1]),\n .O(ddr3_lm_done_r_i_2_n_0));\n FDRE ddr3_lm_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(ddr3_lm_done_r_i_1_n_0),\n .Q(ddr3_lm_done_r),\n .R(rstdiv0_sync_r1_reg_rep__12));\n LUT6 #(\n .INIT(64'h0000000000000080)) \n detect_pi_found_dqs_i_1\n (.I0(\\cnt_cmd_r_reg_n_0_[5] ),\n .I1(\\cnt_cmd_r[6]_i_5_n_0 ),\n .I2(Q[1]),\n .I3(Q[0]),\n .I4(\\back_to_back_reads_4_1.num_reads_reg[0]_0 ),\n .I5(\\cnt_cmd_r_reg_n_0_[6] ),\n .O(detect_pi_found_dqs0));\n FDRE detect_pi_found_dqs_reg\n (.C(CLK),\n .CE(1'b1),\n .D(detect_pi_found_dqs0),\n .Q(detect_pi_found_dqs),\n .R(rstdiv0_sync_r1_reg_rep__11));\n LUT6 #(\n .INIT(64'h00000000DADA00DA)) \n \\dqs_asrt_cnt[0]_i_1 \n (.I0(dqs_asrt_cnt[0]),\n .I1(dqs_asrt_cnt[1]),\n .I2(wr_level_dqs_asrt),\n .I3(wrlvl_done_r),\n .I4(wrlvl_done_r1),\n .I5(rstdiv0_sync_r1_reg_rep__24),\n .O(\\dqs_asrt_cnt[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00000000ECEC00EC)) \n \\dqs_asrt_cnt[1]_i_1 \n (.I0(dqs_asrt_cnt[0]),\n .I1(dqs_asrt_cnt[1]),\n .I2(wr_level_dqs_asrt),\n .I3(wrlvl_done_r),\n .I4(wrlvl_done_r1),\n .I5(rstdiv0_sync_r1_reg_rep__25),\n .O(\\dqs_asrt_cnt[1]_i_1_n_0 ));\n FDRE \\dqs_asrt_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dqs_asrt_cnt[0]_i_1_n_0 ),\n .Q(dqs_asrt_cnt[0]),\n .R(1'b0));\n FDRE \\dqs_asrt_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dqs_asrt_cnt[1]_i_1_n_0 ),\n .Q(dqs_asrt_cnt[1]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h000000000F0F0F0E)) \n \\en_cnt_div4.enable_wrlvl_cnt[0]_i_1 \n (.I0(enable_wrlvl_cnt[3]),\n .I1(enable_wrlvl_cnt[4]),\n .I2(enable_wrlvl_cnt[0]),\n .I3(enable_wrlvl_cnt[1]),\n .I4(enable_wrlvl_cnt[2]),\n .I5(rstdiv0_sync_r1_reg_rep__24_0),\n .O(\\en_cnt_div4.enable_wrlvl_cnt[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00000000F00FF00E)) \n \\en_cnt_div4.enable_wrlvl_cnt[1]_i_1 \n (.I0(enable_wrlvl_cnt[3]),\n .I1(enable_wrlvl_cnt[4]),\n .I2(enable_wrlvl_cnt[0]),\n .I3(enable_wrlvl_cnt[1]),\n .I4(enable_wrlvl_cnt[2]),\n .I5(rstdiv0_sync_r1_reg_rep__24_0),\n .O(\\en_cnt_div4.enable_wrlvl_cnt[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFF0000E)) \n \\en_cnt_div4.enable_wrlvl_cnt[2]_i_1 \n (.I0(enable_wrlvl_cnt[3]),\n .I1(enable_wrlvl_cnt[4]),\n .I2(enable_wrlvl_cnt[0]),\n .I3(enable_wrlvl_cnt[1]),\n .I4(enable_wrlvl_cnt[2]),\n .I5(\\en_cnt_div4.enable_wrlvl_cnt_reg[3]_0 ),\n .O(\\en_cnt_div4.enable_wrlvl_cnt[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFAAAAAAA4)) \n \\en_cnt_div4.enable_wrlvl_cnt[3]_i_2 \n (.I0(enable_wrlvl_cnt[3]),\n .I1(enable_wrlvl_cnt[4]),\n .I2(enable_wrlvl_cnt[0]),\n .I3(enable_wrlvl_cnt[1]),\n .I4(enable_wrlvl_cnt[2]),\n .I5(\\en_cnt_div4.enable_wrlvl_cnt_reg[3]_0 ),\n .O(\\en_cnt_div4.enable_wrlvl_cnt[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h444444444444444F)) \n \\en_cnt_div4.enable_wrlvl_cnt[3]_i_3 \n (.I0(enable_wrlvl_cnt0),\n .I1(wrlvl_odt),\n .I2(read_calib_reg_0),\n .I3(Q[3]),\n .I4(Q[4]),\n .I5(Q[5]),\n .O(\\en_cnt_div4.enable_wrlvl_cnt_reg[3]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair519\" *) \n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n \\en_cnt_div4.enable_wrlvl_cnt[3]_i_4 \n (.I0(enable_wrlvl_cnt[2]),\n .I1(enable_wrlvl_cnt[1]),\n .I2(enable_wrlvl_cnt[0]),\n .I3(enable_wrlvl_cnt[4]),\n .I4(enable_wrlvl_cnt[3]),\n .O(enable_wrlvl_cnt0));\n LUT6 #(\n .INIT(64'h00000000CCCCCCC8)) \n \\en_cnt_div4.enable_wrlvl_cnt[4]_i_1 \n (.I0(enable_wrlvl_cnt[3]),\n .I1(enable_wrlvl_cnt[4]),\n .I2(enable_wrlvl_cnt[0]),\n .I3(enable_wrlvl_cnt[1]),\n .I4(enable_wrlvl_cnt[2]),\n .I5(rstdiv0_sync_r1_reg_rep__24_0),\n .O(\\en_cnt_div4.enable_wrlvl_cnt[4]_i_1_n_0 ));\n FDRE \\en_cnt_div4.enable_wrlvl_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\en_cnt_div4.enable_wrlvl_cnt[0]_i_1_n_0 ),\n .Q(enable_wrlvl_cnt[0]),\n .R(1'b0));\n FDRE \\en_cnt_div4.enable_wrlvl_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\en_cnt_div4.enable_wrlvl_cnt[1]_i_1_n_0 ),\n .Q(enable_wrlvl_cnt[1]),\n .R(1'b0));\n FDRE \\en_cnt_div4.enable_wrlvl_cnt_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\en_cnt_div4.enable_wrlvl_cnt[2]_i_1_n_0 ),\n .Q(enable_wrlvl_cnt[2]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE \\en_cnt_div4.enable_wrlvl_cnt_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\en_cnt_div4.enable_wrlvl_cnt[3]_i_2_n_0 ),\n .Q(enable_wrlvl_cnt[3]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE \\en_cnt_div4.enable_wrlvl_cnt_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\en_cnt_div4.enable_wrlvl_cnt[4]_i_1_n_0 ),\n .Q(enable_wrlvl_cnt[4]),\n .R(1'b0));\n LUT4 #(\n .INIT(16'h000E)) \n \\en_cnt_div4.wrlvl_odt_i_1 \n (.I0(wrlvl_odt),\n .I1(\\en_cnt_div4.wrlvl_odt_i_2_n_0 ),\n .I2(wrlvl_odt_ctl),\n .I3(rstdiv0_sync_r1_reg_rep__25),\n .O(\\en_cnt_div4.wrlvl_odt_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair519\" *) \n LUT5 #(\n .INIT(32'h00000010)) \n \\en_cnt_div4.wrlvl_odt_i_2 \n (.I0(enable_wrlvl_cnt[4]),\n .I1(enable_wrlvl_cnt[3]),\n .I2(enable_wrlvl_cnt[0]),\n .I3(enable_wrlvl_cnt[2]),\n .I4(enable_wrlvl_cnt[1]),\n .O(\\en_cnt_div4.wrlvl_odt_i_2_n_0 ));\n FDRE \\en_cnt_div4.wrlvl_odt_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\en_cnt_div4.wrlvl_odt_i_1_n_0 ),\n .Q(wrlvl_odt),\n .R(1'b0));\n LUT4 #(\n .INIT(16'hFFF4)) \n first_rdlvl_pat_r_i_1\n (.I0(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .I1(first_rdlvl_pat_r),\n .I2(rdlvl_stg1_rank_done),\n .I3(rstdiv0_sync_r1_reg_rep__24),\n .O(first_rdlvl_pat_r_i_1_n_0));\n FDRE first_rdlvl_pat_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(first_rdlvl_pat_r_i_1_n_0),\n .Q(first_rdlvl_pat_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFEFEFEFEFEFCFEFF)) \n first_wrcal_pat_r_i_1\n (.I0(first_wrcal_pat_r),\n .I1(rstdiv0_sync_r1_reg_rep__24),\n .I2(wrcal_resume_w),\n .I3(Q[1]),\n .I4(Q[0]),\n .I5(first_wrcal_pat_r_i_2_n_0),\n .O(first_wrcal_pat_r_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair494\" *) \n LUT5 #(\n .INIT(32'hFFFFFEFF)) \n first_wrcal_pat_r_i_2\n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(Q[2]),\n .I2(Q[5]),\n .I3(Q[4]),\n .I4(Q[3]),\n .O(first_wrcal_pat_r_i_2_n_0));\n FDRE first_wrcal_pat_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(first_wrcal_pat_r_i_1_n_0),\n .Q(first_wrcal_pat_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0404550404040404)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_1 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3_n_0 ),\n .I3(reg_ctrl_cnt_r),\n .I4(reg_ctrl_cnt_r_reg__0[3]),\n .I5(reg_ctrl_cnt_r_reg__0[0]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF4F44FFFF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ),\n .I3(\\complex_address_reg_n_0_[0] ),\n .I4(prbs_rdlvl_done_reg),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h5515FFFF55155515)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3 \n (.I0(Q[5]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_5_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_6_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h000000000000005D)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .I1(complex_row_cnt_ocal_reg__0[0]),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ),\n .I3(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_7_n_0 ),\n .I5(\\stg1_wr_rd_cnt[8]_i_4_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFF888)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_5 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0 ),\n .I2(\\complex_address_reg_n_0_[0] ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ),\n .I4(prbs_rdlvl_done_reg),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFD0D0D0FF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_6 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_6_n_0 ));\n LUT2 #(\n .INIT(4'h1)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_7 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair583\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_1 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_1_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0010009000000010)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2 \n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(\\wrcal_reads[7]_i_5_n_0 ),\n .I3(Q[5]),\n .I4(Q[4]),\n .I5(Q[3]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000554000000000)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_1 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ),\n .I1(cnt_init_mr_r[0]),\n .I2(cnt_init_mr_r[1]),\n .I3(dqs_found_done_r_reg_0),\n .I4(Q[5]),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_4_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFDFFFD7DFFEFF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2 \n (.I0(Q[0]),\n .I1(Q[3]),\n .I2(Q[4]),\n .I3(Q[1]),\n .I4(\\init_state_r_reg_n_0_[3] ),\n .I5(Q[2]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair522\" *) \n LUT5 #(\n .INIT(32'h00000010)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_4 \n (.I0(Q[2]),\n .I1(Q[4]),\n .I2(Q[1]),\n .I3(Q[3]),\n .I4(Q[0]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h0004010000000000)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1 \n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(Q[2]),\n .I2(Q[5]),\n .I3(Q[3]),\n .I4(Q[4]),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2 \n (.I0(Q[0]),\n .I1(Q[1]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFFF80)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_1 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFEAEAEAFFFFFFFF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2 \n (.I0(prbs_rdlvl_done_reg),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ),\n .I2(\\complex_address_reg_n_0_[1] ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF4F44FFFF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ),\n .I3(\\complex_address_reg_n_0_[1] ),\n .I4(prbs_rdlvl_done_reg),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair543\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4 \n (.I0(reg_ctrl_cnt_r),\n .I1(reg_ctrl_cnt_r_reg__0[1]),\n .I2(reg_ctrl_cnt_r_reg__0[3]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFD0D0D0FF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h000000000000005D)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .I1(complex_row_cnt_ocal_reg__0[1]),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_7_n_0 ),\n .I4(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .I5(\\stg1_wr_rd_cnt[8]_i_4_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6_n_0 ));\n LUT2 #(\n .INIT(4'h1)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_7 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h010101FF01010101)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_1 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2_n_0 ),\n .I1(Q[5]),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h1)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_10 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'h5FF55FF50F3F0F30)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2 \n (.I0(\\gen_rnk[0].mr1_r_reg[0]_196 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000022202220222)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7_n_0 ),\n .I1(prbs_rdlvl_done_reg),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ),\n .I3(\\complex_address_reg_n_0_[2] ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF4F44FFFF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ),\n .I3(\\complex_address_reg_n_0_[2] ),\n .I4(prbs_rdlvl_done_reg),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_9_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFF8080808080)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5 \n (.I0(dqs_found_done_r_reg),\n .I1(rdlvl_stg1_done_int_reg),\n .I2(prbs_rdlvl_done_reg_rep),\n .I3(cnt_init_mr_r[0]),\n .I4(\\gen_rnk[0].mr1_r_reg[0]_196 ),\n .I5(cnt_init_mr_r[1]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair586\" *) \n LUT3 #(\n .INIT(8'hEF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6 \n (.I0(reg_ctrl_cnt_r_reg__0[3]),\n .I1(reg_ctrl_cnt_r_reg__0[1]),\n .I2(reg_ctrl_cnt_r_reg__0[2]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFD0D0D0FF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'h000000000000005D)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_9 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .I1(complex_row_cnt_ocal_reg__0[2]),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ),\n .I3(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .I4(\\stg1_wr_rd_cnt[8]_i_4_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_10_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'h000000000000AAAB)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_1 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0 ),\n .I2(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_4_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_5_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h0047FFFF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ),\n .I2(\\complex_address_reg_n_0_[3] ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ),\n .I4(prbs_rdlvl_done_reg),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h00000000D000D0D0)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_4 \n (.I0(complex_row_cnt_ocal_reg__0[3]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_7_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_8_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h00000000AAA222A2)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_5 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_9_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ),\n .I4(\\complex_address_reg_n_0_[3] ),\n .I5(prbs_rdlvl_done_reg),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FFEFFFFF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6 \n (.I0(oclk_calib_resume_level_reg_0),\n .I1(Q[5]),\n .I2(Q[4]),\n .I3(Q[3]),\n .I4(Q[0]),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_7 \n (.I0(\\stg1_wr_rd_cnt[8]_i_4_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_8 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1_n_0 ),\n .I1(burst_addr_r_reg_0),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF4044)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_9 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_8_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ),\n .I3(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hABABABABABAAABAB)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_1 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_1_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3_n_0 ),\n .I4(prbs_rdlvl_done_reg),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FEEEFEFE)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_5_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ),\n .I4(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_6_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FBFB00F3)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_7_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_8_n_0 ),\n .I5(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0014551455140014)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ),\n .I1(\\complex_address_reg_n_0_[4] ),\n .I2(\\complex_address_reg_n_0_[3] ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4_n_0 ));\n LUT3 #(\n .INIT(8'h82)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_5 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hBEFFBEAAAAAAAAAA)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_6 \n (.I0(prbs_rdlvl_done_reg),\n .I1(\\complex_address_reg_n_0_[3] ),\n .I2(\\complex_address_reg_n_0_[4] ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_8_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_6_n_0 ));\n LUT3 #(\n .INIT(8'h02)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_7 \n (.I0(complex_row_cnt_ocal_reg__0[4]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ),\n .I2(\\stg1_wr_rd_cnt[8]_i_4_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair554\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_8 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_8_n_0 ));\n LUT5 #(\n .INIT(32'h00000100)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9 \n (.I0(init_state_r1[5]),\n .I1(init_state_r1[4]),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0 ),\n .I3(init_state_r1[3]),\n .I4(init_state_r1[0]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'h0004000400045555)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_1 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFEEEF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10 \n (.I0(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .I1(\\stg1_wr_rd_cnt[8]_i_4_n_0 ),\n .I2(read_calib_reg_0),\n .I3(read_calib_i_2_n_0),\n .I4(\\calib_cmd[2]_i_8_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair502\" *) \n LUT4 #(\n .INIT(16'h802A)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_11 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ));\n LUT6 #(\n .INIT(64'hBEFFBEAAAAAAAAAA)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_13 \n (.I0(prbs_rdlvl_done_reg),\n .I1(\\complex_address_reg_n_0_[5] ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_13_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF4500FFFF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2 \n (.I0(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8_n_0 ),\n .I4(prbs_rdlvl_done_reg),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_9_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FEEEFEFE)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_11_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ),\n .I4(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_13_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair546\" *) \n LUT4 #(\n .INIT(16'h00BF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ),\n .I3(Q[5]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4_n_0 ));\n LUT2 #(\n .INIT(4'hB)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5 \n (.I0(Q[5]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_4_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FFFFEAAA)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6 \n (.I0(cnt_init_mr_r[1]),\n .I1(prbs_rdlvl_done_reg),\n .I2(rdlvl_stg1_done_int_reg),\n .I3(dqs_found_done_r_reg),\n .I4(cnt_init_mr_r[0]),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6_n_0 ));\n LUT3 #(\n .INIT(8'h6A)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hFF020202FFFFFFFF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8 \n (.I0(complex_row_cnt_ocal_reg__0[5]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ),\n .I2(\\stg1_wr_rd_cnt[8]_i_4_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'h5555154000001540)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_9 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ),\n .I1(\\complex_address_reg_n_0_[4] ),\n .I2(\\complex_address_reg_n_0_[3] ),\n .I3(\\complex_address_reg_n_0_[5] ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_9_n_0 ));\n LUT5 #(\n .INIT(32'h888F8888)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_1 \n (.I0(\\gen_rnk[0].mr1_r_reg[0]_196 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair502\" *) \n LUT5 #(\n .INIT(32'h80002AAA)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF10FF10FF10FF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_11 \n (.I0(\\stg1_wr_rd_cnt[8]_i_4_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ),\n .I2(complex_row_cnt_ocal_reg__0[6]),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'h7447474747474747)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_12 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ),\n .I2(\\complex_address_reg_n_0_[6] ),\n .I3(\\complex_address_reg_n_0_[5] ),\n .I4(\\complex_address_reg_n_0_[4] ),\n .I5(\\complex_address_reg_n_0_[3] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_12_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair583\" *) \n LUT3 #(\n .INIT(8'h01)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),\n .I1(Q[5]),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00000000AA2A222A)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9_n_0 ),\n .I5(prbs_rdlvl_done_reg),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair585\" *) \n LUT3 #(\n .INIT(8'h4F)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4 \n (.I0(Q[5]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h10FF10FF10FFFFFF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5 \n (.I0(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_11_n_0 ),\n .I3(prbs_rdlvl_done_reg),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_12_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h5555FFFFFFEF5555)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ),\n .I1(dqs_found_done_r_reg_0),\n .I2(cnt_init_mr_r[1]),\n .I3(cnt_init_mr_r[0]),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFD0D0FFD0)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair523\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair528\" *) \n LUT4 #(\n .INIT(16'h9555)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9 \n (.I0(\\complex_address_reg_n_0_[6] ),\n .I1(\\complex_address_reg_n_0_[5] ),\n .I2(\\complex_address_reg_n_0_[4] ),\n .I3(\\complex_address_reg_n_0_[3] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hAA20AAAAAA20AA20)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_1 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ),\n .I1(Q[5]),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5_n_0 ),\n .I5(prbs_rdlvl_done_reg),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair528\" *) \n LUT5 #(\n .INIT(32'h95555555)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10 \n (.I0(\\complex_address_reg_n_0_[7] ),\n .I1(\\complex_address_reg_n_0_[6] ),\n .I2(\\complex_address_reg_n_0_[3] ),\n .I3(\\complex_address_reg_n_0_[4] ),\n .I4(\\complex_address_reg_n_0_[5] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFD0D0FFD0)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF00100000)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12 \n (.I0(oclk_calib_resume_level_reg_0),\n .I1(Q[5]),\n .I2(Q[4]),\n .I3(Q[3]),\n .I4(Q[0]),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ));\n LUT4 #(\n .INIT(16'hFBAA)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_13 \n (.I0(\\stg1_wr_rd_cnt[8]_i_4_n_0 ),\n .I1(complex_row_cnt_ocal_reg__0[7]),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_13_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14 \n (.I0(\\stg1_wr_rd_cnt[8]_i_4_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ));\n LUT4 #(\n .INIT(16'h5101)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_15 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_15_n_0 ));\n LUT6 #(\n .INIT(64'h5554555555555555)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_16 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18_n_0 ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[0] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[1] ),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[2] ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_18_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_16_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair513\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_17 \n (.I0(init_state_r1[0]),\n .I1(init_state_r1[3]),\n .I2(init_state_r1[4]),\n .I3(init_state_r1[5]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000001)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_18 \n (.I0(\\stg1_wr_rd_cnt_reg_n_0_[5] ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[6] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[7] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[8] ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[4] ),\n .I5(\\stg1_wr_rd_cnt_reg_n_0_[3] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_18_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair546\" *) \n LUT4 #(\n .INIT(16'h5540)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ),\n .I3(Q[5]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0020000000000070)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3 \n (.I0(Q[2]),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .I2(Q[1]),\n .I3(Q[3]),\n .I4(Q[0]),\n .I5(Q[4]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0040444055555555)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4 \n (.I0(prbs_rdlvl_done_reg),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h00000000BBBAFFBA)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5 \n (.I0(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_13_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_15_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF6EEF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6 \n (.I0(Q[0]),\n .I1(Q[3]),\n .I2(Q[1]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[4]),\n .I5(Q[2]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hFF54000000000000)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7 \n (.I0(complex_row0_rd_done),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ),\n .I2(\\one_rank.stg1_wr_done_reg_0 ),\n .I3(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_10_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_16_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair523\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair501\" *) \n LUT5 #(\n .INIT(32'hAAA8AAAA)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9 \n (.I0(\\stg1_wr_rd_cnt[8]_i_4_n_0 ),\n .I1(init_state_r1[1]),\n .I2(init_state_r1[2]),\n .I3(init_state_r1[6]),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_17_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF111F0000)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_1 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ),\n .I4(prbs_rdlvl_done_reg),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h800000007FFFFFFF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h9555555555555555)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3 \n (.I0(\\complex_address_reg_n_0_[8] ),\n .I1(\\complex_address_reg_n_0_[7] ),\n .I2(\\complex_address_reg_n_0_[5] ),\n .I3(\\complex_address_reg_n_0_[4] ),\n .I4(\\complex_address_reg_n_0_[3] ),\n .I5(\\complex_address_reg_n_0_[6] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAABAAA)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0 ),\n .I2(cnt_init_mr_r[0]),\n .I3(cnt_init_mr_r[1]),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_2_n_0 ),\n .I5(dqs_found_done_r_reg_0),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h0404040455045555)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5 \n (.I0(prbs_rdlvl_done_reg),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF1F110000)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_1 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0 ),\n .I4(prbs_rdlvl_done_reg),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair501\" *) \n LUT3 #(\n .INIT(8'hDF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10 \n (.I0(init_state_r1[2]),\n .I1(init_state_r1[6]),\n .I2(init_state_r1[1]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'hB)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0 ),\n .I1(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12 \n (.I0(\\complex_address_reg_n_0_[4] ),\n .I1(\\complex_address_reg_n_0_[3] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'hBBBBBBBBBBBBBBFB)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15 \n (.I0(first_wrcal_pat_r_i_2_n_0),\n .I1(Q[0]),\n .I2(wrcal_wr_cnt_reg__0[2]),\n .I3(wrcal_wr_cnt_reg__0[1]),\n .I4(wrcal_wr_cnt_reg__0[0]),\n .I5(wrcal_wr_cnt_reg__0[3]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF04000000)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16 \n (.I0(oclk_calib_resume_level_reg_0),\n .I1(Q[3]),\n .I2(Q[5]),\n .I3(Q[4]),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .I5(\\calib_cmd[2]_i_4_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAAEEEFAAAA)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18_n_0 ),\n .I1(complex_row0_rd_done),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_9_n_0 ),\n .I3(\\one_rank.stg1_wr_done_reg_0 ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[3] ),\n .I5(\\complex_row_cnt_ocal[7]_i_7_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'h2000000000000000)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19_n_0 ),\n .I1(\\complex_num_writes[4]_i_12_n_0 ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[3] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[4] ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[6] ),\n .I5(\\stg1_wr_rd_cnt_reg_n_0_[5] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair561\" *) \n LUT3 #(\n .INIT(8'h02)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19 \n (.I0(\\stg1_wr_rd_cnt_reg_n_0_[0] ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[7] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[8] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair558\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF00010000)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0 ),\n .I1(init_state_r1[5]),\n .I2(init_state_r1[4]),\n .I3(init_state_r1[0]),\n .I4(init_state_r1[3]),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5 \n (.I0(\\complex_address_reg_n_0_[9] ),\n .I1(\\complex_address_reg_n_0_[8] ),\n .I2(\\complex_address_reg_n_0_[6] ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0 ),\n .I4(\\complex_address_reg_n_0_[5] ),\n .I5(\\complex_address_reg_n_0_[7] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAAFFABABAB)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_1_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0 ),\n .I5(prbs_rdlvl_done_reg),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0 ));\n LUT4 #(\n .INIT(16'h00FD)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7 \n (.I0(init_state_r1[3]),\n .I1(wrlvl_odt_ctl_i_3_n_0),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_14_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h00000300AAAAAAAA)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0 ),\n .I1(oclk_wr_cnt_reg__0[3]),\n .I2(oclk_wr_cnt_reg__0[1]),\n .I3(oclk_wr_cnt_reg__0[2]),\n .I4(oclk_wr_cnt_reg__0[0]),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0 ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'h7FFFFFFFFFFFFFFF)) \n \\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I4(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ));\n FDRE \\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_1_n_0 ),\n .Q(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_1_n_0 ),\n .Q(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),\n .R(1'b0));\n FDRE \\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address[11]_i_1_n_0 ),\n .Q(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ),\n .R(1'b0));\n FDRE \\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1_n_0 ),\n .Q(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),\n .R(1'b0));\n FDRE \\gen_no_mirror.div_clk_loop[0].phy_address_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_1_n_0 ),\n .Q(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),\n .R(1'b0));\n FDRE \\gen_no_mirror.div_clk_loop[0].phy_address_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_1_n_0 ),\n .Q(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),\n .R(1'b0));\n FDRE \\gen_no_mirror.div_clk_loop[0].phy_address_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_1_n_0 ),\n .Q(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .R(1'b0));\n FDRE \\gen_no_mirror.div_clk_loop[0].phy_address_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_1_n_0 ),\n .Q(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .R(1'b0));\n FDRE \\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_1_n_0 ),\n .Q(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),\n .R(1'b0));\n FDRE \\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_1_n_0 ),\n .Q(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),\n .R(1'b0));\n FDRE \\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_1_n_0 ),\n .Q(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),\n .R(1'b0));\n FDRE \\gen_no_mirror.div_clk_loop[0].phy_address_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_1_n_0 ),\n .Q(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),\n .R(1'b0));\n FDRE \\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_1_n_0 ),\n .Q(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h888888888888888A)) \n \\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_1 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0 ),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_4_n_0 ),\n .I3(Q[4]),\n .I4(Q[3]),\n .I5(Q[0]),\n .O(bank_w[0]));\n LUT6 #(\n .INIT(64'h0D0F0F0F0F0F040F)) \n \\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2 \n (.I0(Q[3]),\n .I1(Q[4]),\n .I2(Q[5]),\n .I3(\\wrcal_reads[7]_i_5_n_0 ),\n .I4(Q[1]),\n .I5(Q[0]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h2000000028000000)) \n \\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_5_n_0 ),\n .I1(Q[2]),\n .I2(\\init_state_r_reg_n_0_[3] ),\n .I3(Q[1]),\n .I4(Q[0]),\n .I5(Q[3]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF00FFFF00F9FF)) \n \\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_4 \n (.I0(cnt_init_mr_r[0]),\n .I1(cnt_init_mr_r[1]),\n .I2(dqs_found_done_r_reg_0),\n .I3(Q[1]),\n .I4(\\init_state_r_reg_n_0_[3] ),\n .I5(Q[2]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h3030303034303030)) \n \\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_5 \n (.I0(reg_ctrl_cnt_r_reg__0[0]),\n .I1(Q[3]),\n .I2(Q[4]),\n .I3(reg_ctrl_cnt_r_reg__0[2]),\n .I4(reg_ctrl_cnt_r_reg__0[1]),\n .I5(reg_ctrl_cnt_r_reg__0[3]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair498\" *) \n LUT5 #(\n .INIT(32'h00010000)) \n \\gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_1 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),\n .I1(Q[5]),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2_n_0 ),\n .I3(Q[3]),\n .I4(Q[1]),\n .O(bank_w[1]));\n LUT6 #(\n .INIT(64'hAA55FFFFFFFFFF54)) \n \\gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2 \n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(dqs_found_done_r_reg_0),\n .I2(cnt_init_mr_r[1]),\n .I3(Q[2]),\n .I4(Q[4]),\n .I5(Q[0]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair543\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_1 \n (.I0(reg_ctrl_cnt_r_reg__0[3]),\n .I1(reg_ctrl_cnt_r_reg__0[1]),\n .I2(reg_ctrl_cnt_r),\n .I3(reg_ctrl_cnt_r_reg__0[2]),\n .O(\\gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_1_n_0 ));\n FDRE \\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(bank_w[0]),\n .Q(phy_bank[9]),\n .R(1'b0));\n FDRE \\gen_no_mirror.div_clk_loop[0].phy_bank_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(bank_w[1]),\n .Q(phy_bank[10]),\n .R(1'b0));\n FDRE \\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_1_n_0 ),\n .Q(phy_bank[11]),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair596\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\gen_reset_obuf.u_reset_obuf_i_1 \n (.I0(init_calib_complete_reg_rep__14),\n .I1(phy_reset_n),\n .O(mux_reset_n));\n FDRE \\gen_rnk[0].mr1_r_reg[0][1] \n (.C(CLK),\n .CE(1'b1),\n .D(1'b1),\n .Q(\\gen_rnk[0].mr1_r_reg[0]_196 ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE init_calib_complete_reg\n (.C(CLK),\n .CE(1'b1),\n .D(init_complete_r2),\n .Q(calib_complete),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE init_complete_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(init_complete_r1_reg_0),\n .Q(init_complete_r1),\n .R(rstdiv0_sync_r1_reg_rep__11));\n (* KEEP = \"yes\" *) \n FDRE init_complete_r1_timing_reg\n (.C(CLK),\n .CE(1'b1),\n .D(init_complete_r_timing),\n .Q(init_complete_r1_timing),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE init_complete_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(init_complete_r1),\n .Q(init_complete_r2),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE init_complete_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\init_state_r_reg[6]_0 ),\n .Q(init_complete_r1_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__12));\n (* KEEP = \"yes\" *) \n FDRE init_complete_r_timing_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\init_state_r_reg[6]_1 ),\n .Q(init_complete_r_timing),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE \\init_state_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(Q[0]),\n .Q(init_state_r1[0]),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE \\init_state_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(Q[1]),\n .Q(init_state_r1[1]),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE \\init_state_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(Q[2]),\n .Q(init_state_r1[2]),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE \\init_state_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\init_state_r_reg_n_0_[3] ),\n .Q(init_state_r1[3]),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE \\init_state_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(Q[3]),\n .Q(init_state_r1[4]),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE \\init_state_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(Q[4]),\n .Q(init_state_r1[5]),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE \\init_state_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(Q[5]),\n .Q(init_state_r1[6]),\n .R(rstdiv0_sync_r1_reg_rep__11));\n LUT6 #(\n .INIT(64'hAAAAAAAAEEEFFFFF)) \n \\init_state_r[0]_i_1 \n (.I0(\\init_state_r[0]_i_2_n_0 ),\n .I1(\\init_state_r[0]_i_3_n_0 ),\n .I2(oclk_calib_resume_level_reg_0),\n .I3(\\init_state_r[0]_i_5_n_0 ),\n .I4(\\init_state_r[0]_i_6_n_0 ),\n .I5(\\init_state_r[0]_i_7_n_0 ),\n .O(\\init_state_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFF000000FFFF1103)) \n \\init_state_r[0]_i_10 \n (.I0(\\init_state_r[0]_i_26_n_0 ),\n .I1(prech_pending_r_reg_0),\n .I2(\\init_state_r[0]_i_27_n_0 ),\n .I3(Q[0]),\n .I4(Q[1]),\n .I5(prbs_rdlvl_done_pulse0),\n .O(\\init_state_r[0]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'hEFEFEFEFFFEFEFEF)) \n \\init_state_r[0]_i_11 \n (.I0(\\init_state_r[0]_i_28_n_0 ),\n .I1(\\init_state_r[0]_i_29_n_0 ),\n .I2(Q[3]),\n .I3(\\init_state_r[0]_i_30_n_0 ),\n .I4(\\wrcal_reads[7]_i_5_n_0 ),\n .I5(\\init_state_r[0]_i_31_n_0 ),\n .O(\\init_state_r[0]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'hDDDFDDDDDDDDDDDD)) \n \\init_state_r[0]_i_13 \n (.I0(Q[3]),\n .I1(\\init_state_r_reg[5]_0 ),\n .I2(\\init_state_r[4]_i_5_n_0 ),\n .I3(Q[0]),\n .I4(cnt_cmd_done_r),\n .I5(\\init_state_r[0]_i_33_n_0 ),\n .O(\\init_state_r[0]_i_13_n_0 ));\n LUT5 #(\n .INIT(32'hAAAABBAB)) \n \\init_state_r[0]_i_14 \n (.I0(Q[1]),\n .I1(\\init_state_r[0]_i_34_n_0 ),\n .I2(rdlvl_stg1_done_int_reg),\n .I3(rdlvl_stg1_done_r1),\n .I4(rdlvl_stg1_rank_done),\n .O(\\init_state_r[0]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'h0000FF00FF00FE00)) \n \\init_state_r[0]_i_15 \n (.I0(prech_pending_r_reg_0),\n .I1(pi_dqs_found_rank_done),\n .I2(dqs_found_done_r_reg),\n .I3(Q[1]),\n .I4(cnt_cmd_done_r),\n .I5(Q[0]),\n .O(\\init_state_r[0]_i_15_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000F0FEFE)) \n \\init_state_r[0]_i_16 \n (.I0(prbs_rdlvl_done_reg_rep_2),\n .I1(wrlvl_final_mux_reg),\n .I2(cnt_init_af_done_r),\n .I3(mem_init_done_r),\n .I4(oclkdelay_calib_done_r_reg_5),\n .I5(wrlvl_byte_redo_reg_0),\n .O(\\init_state_r[0]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'h1505155515001550)) \n \\init_state_r[0]_i_17 \n (.I0(oclk_calib_resume_level_reg_0),\n .I1(cnt_cmd_done_r),\n .I2(Q[0]),\n .I3(Q[1]),\n .I4(cnt_txpr_done_r),\n .I5(delay_done_r4_reg),\n .O(\\init_state_r[0]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFDF005F00)) \n \\init_state_r[0]_i_18 \n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(cnt_cmd_done_r),\n .I3(\\init_state_r_reg[1]_0 ),\n .I4(wrlvl_done_r1),\n .I5(\\init_state_r[0]_i_40_n_0 ),\n .O(\\init_state_r[0]_i_18_n_0 ));\n LUT6 #(\n .INIT(64'hAEBBBFBBAABBBFBB)) \n \\init_state_r[0]_i_19 \n (.I0(\\init_state_r[0]_i_41_n_0 ),\n .I1(Q[1]),\n .I2(reset_rd_addr_r1),\n .I3(Q[0]),\n .I4(cnt_cmd_done_r),\n .I5(rdlvl_stg1_done_r1),\n .O(\\init_state_r[0]_i_19_n_0 ));\n LUT6 #(\n .INIT(64'hABABABABAAABAAAA)) \n \\init_state_r[0]_i_2 \n (.I0(\\init_state_r[0]_i_8_n_0 ),\n .I1(\\init_state_r[5]_i_26_n_0 ),\n .I2(\\init_state_r[0]_i_9_n_0 ),\n .I3(\\init_state_r[0]_i_10_n_0 ),\n .I4(\\init_state_r_reg[1]_0 ),\n .I5(\\init_state_r[0]_i_11_n_0 ),\n .O(\\init_state_r[0]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair486\" *) \n LUT5 #(\n .INIT(32'hFFFDDDDD)) \n \\init_state_r[0]_i_20 \n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(rdlvl_stg1_done_r1),\n .I3(complex_sample_cnt_inc_i_2_n_0),\n .I4(\\init_state_r[5]_i_32_n_0 ),\n .O(\\init_state_r[0]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFF133)) \n \\init_state_r[0]_i_21 \n (.I0(\\init_state_r[6]_i_21_n_0 ),\n .I1(write_request_r_reg),\n .I2(prech_pending_r_reg_0),\n .I3(Q[0]),\n .I4(Q[2]),\n .I5(Q[1]),\n .O(\\init_state_r[0]_i_21_n_0 ));\n LUT6 #(\n .INIT(64'hFFBFAFBFAAAAAAAA)) \n \\init_state_r[0]_i_22 \n (.I0(oclk_calib_resume_level_reg_0),\n .I1(cnt_cmd_done_r),\n .I2(Q[1]),\n .I3(Q[0]),\n .I4(burst_addr_r_reg_0),\n .I5(\\init_state_r[0]_i_42_n_0 ),\n .O(\\init_state_r[0]_i_22_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFEAEAEEEA)) \n \\init_state_r[0]_i_23 \n (.I0(\\init_state_r[0]_i_43_n_0 ),\n .I1(\\init_state_r_reg[1]_0 ),\n .I2(\\init_state_r_reg[1]_1 ),\n .I3(cnt_cmd_done_r),\n .I4(Q[0]),\n .I5(\\init_state_r[4]_i_28_n_0 ),\n .O(\\init_state_r[0]_i_23_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair577\" *) \n LUT3 #(\n .INIT(8'h10)) \n \\init_state_r[0]_i_24 \n (.I0(Q[1]),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .I2(Q[2]),\n .O(\\init_state_r[0]_i_24_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair540\" *) \n LUT4 #(\n .INIT(16'h0010)) \n \\init_state_r[0]_i_25 \n (.I0(\\wrcal_reads_reg_n_0_[4] ),\n .I1(\\wrcal_reads_reg_n_0_[6] ),\n .I2(\\wrcal_reads_reg_n_0_[0] ),\n .I3(\\init_state_r[0]_i_45_n_0 ),\n .O(\\init_state_r[0]_i_25_n_0 ));\n LUT6 #(\n .INIT(64'h0888888888888888)) \n \\init_state_r[0]_i_26 \n (.I0(complex_sample_cnt_inc_i_2_n_0),\n .I1(Q[0]),\n .I2(complex_wait_cnt_reg__0[0]),\n .I3(complex_wait_cnt_reg__0[1]),\n .I4(complex_wait_cnt_reg__0[2]),\n .I5(complex_wait_cnt_reg__0[3]),\n .O(\\init_state_r[0]_i_26_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000004)) \n \\init_state_r[0]_i_27 \n (.I0(complex_num_reads_dec_reg__0[1]),\n .I1(complex_num_reads_dec_reg__0[0]),\n .I2(prbs_rdlvl_done_reg_rep),\n .I3(complex_row0_rd_done),\n .I4(complex_num_reads_dec_reg__0[3]),\n .I5(complex_num_reads_dec_reg__0[2]),\n .O(\\init_state_r[0]_i_27_n_0 ));\n LUT6 #(\n .INIT(64'h0101010101014501)) \n \\init_state_r[0]_i_28 \n (.I0(\\init_state_r[4]_i_5_n_0 ),\n .I1(Q[1]),\n .I2(\\init_state_r[0]_i_46_n_0 ),\n .I3(prbs_rdlvl_done_reg_rep_0),\n .I4(Q[0]),\n .I5(complex_oclk_calib_resume),\n .O(\\init_state_r[0]_i_28_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000F0EFE0)) \n \\init_state_r[0]_i_29 \n (.I0(\\init_state_r[6]_i_16_n_0 ),\n .I1(oclkdelay_center_calib_start_r_reg_0),\n .I2(Q[1]),\n .I3(cnt_cmd_done_r),\n .I4(Q[0]),\n .I5(oclk_calib_resume_level_reg_0),\n .O(\\init_state_r[0]_i_29_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF000E0000)) \n \\init_state_r[0]_i_3 \n (.I0(\\init_state_r[2]_i_12_n_0 ),\n .I1(wrcal_sanity_chk_done_reg),\n .I2(Q[1]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[2]),\n .I5(\\init_state_r[0]_i_13_n_0 ),\n .O(\\init_state_r[0]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFDFDFDFDD)) \n \\init_state_r[0]_i_30 \n (.I0(prbs_gen_oclk_clk_en_i_8_n_0),\n .I1(\\init_state_r[3]_i_23_n_0 ),\n .I2(complex_oclkdelay_calib_start_r2),\n .I3(prbs_rdlvl_done_reg),\n .I4(prbs_last_byte_done_r),\n .I5(\\init_state_r[4]_i_39_n_0 ),\n .O(\\init_state_r[0]_i_30_n_0 ));\n LUT6 #(\n .INIT(64'h0004000400000004)) \n \\init_state_r[0]_i_31 \n (.I0(oclkdelay_center_calib_start_r_reg),\n .I1(prbs_gen_oclk_clk_en_i_8_n_0),\n .I2(prech_pending_r_reg_0),\n .I3(prbs_rdlvl_start_i_2_n_0),\n .I4(complex_row1_wr_done),\n .I5(\\one_rank.stg1_wr_done_reg_0 ),\n .O(\\init_state_r[0]_i_31_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair562\" *) \n LUT4 #(\n .INIT(16'hFFEF)) \n \\init_state_r[0]_i_33 \n (.I0(reg_ctrl_cnt_r_reg__0[1]),\n .I1(reg_ctrl_cnt_r_reg__0[0]),\n .I2(reg_ctrl_cnt_r_reg__0[3]),\n .I3(reg_ctrl_cnt_r_reg__0[2]),\n .O(\\init_state_r[0]_i_33_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair544\" *) \n LUT4 #(\n .INIT(16'hFFAE)) \n \\init_state_r[0]_i_34 \n (.I0(Q[0]),\n .I1(prbs_rdlvl_done_reg_rep),\n .I2(prbs_rdlvl_done_r1),\n .I3(prech_pending_r_reg_0),\n .O(\\init_state_r[0]_i_34_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\init_state_r[0]_i_4 \n (.I0(Q[2]),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .O(oclk_calib_resume_level_reg_0));\n LUT6 #(\n .INIT(64'hBAFFAAAABFFFAAAA)) \n \\init_state_r[0]_i_40 \n (.I0(Q[3]),\n .I1(wrlvl_rank_done_r7),\n .I2(Q[1]),\n .I3(Q[0]),\n .I4(\\wrcal_reads[7]_i_5_n_0 ),\n .I5(cnt_dllk_zqinit_done_r),\n .O(\\init_state_r[0]_i_40_n_0 ));\n LUT6 #(\n .INIT(64'h0000400044444444)) \n \\init_state_r[0]_i_41 \n (.I0(Q[1]),\n .I1(pi_calib_done),\n .I2(\\init_state_r[0]_i_51_n_0 ),\n .I3(wrcal_done_reg_10),\n .I4(rdlvl_stg1_done_int_reg_4),\n .I5(dqs_found_done_r_reg),\n .O(\\init_state_r[0]_i_41_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAABABB)) \n \\init_state_r[0]_i_42 \n (.I0(\\init_state_r[1]_i_20_n_0 ),\n .I1(Q[0]),\n .I2(wrcal_prech_req),\n .I3(cnt_cmd_done_r),\n .I4(wrcal_done_reg_10),\n .I5(prech_pending_r_reg_0),\n .O(\\init_state_r[0]_i_42_n_0 ));\n LUT6 #(\n .INIT(64'h000000000000F0EF)) \n \\init_state_r[0]_i_43 \n (.I0(\\init_state_r[2]_i_36_n_0 ),\n .I1(cnt_cmd_done_r_reg_1),\n .I2(Q[1]),\n .I3(Q[0]),\n .I4(\\init_state_r[4]_i_5_n_0 ),\n .I5(\\init_state_r[5]_i_57_n_0 ),\n .O(\\init_state_r[0]_i_43_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFEFF)) \n \\init_state_r[0]_i_45 \n (.I0(\\wrcal_reads_reg_n_0_[3] ),\n .I1(\\wrcal_reads_reg_n_0_[1] ),\n .I2(\\wrcal_reads_reg_n_0_[7] ),\n .I3(Q[0]),\n .I4(\\wrcal_reads_reg_n_0_[2] ),\n .I5(\\wrcal_reads_reg_n_0_[5] ),\n .O(\\init_state_r[0]_i_45_n_0 ));\n LUT6 #(\n .INIT(64'h4500FFFF4545FFFF)) \n \\init_state_r[0]_i_46 \n (.I0(prech_pending_r_reg_0),\n .I1(complex_oclkdelay_calib_done_r1),\n .I2(prbs_rdlvl_done_reg),\n .I3(prbs_gen_oclk_clk_en_i_8_n_0),\n .I4(Q[0]),\n .I5(complex_sample_cnt_inc_i_2_n_0),\n .O(\\init_state_r[0]_i_46_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FFFF1000)) \n \\init_state_r[0]_i_5 \n (.I0(num_reads[1]),\n .I1(num_reads[2]),\n .I2(num_reads[0]),\n .I3(Q[0]),\n .I4(\\init_state_r[0]_i_14_n_0 ),\n .I5(\\init_state_r[0]_i_15_n_0 ),\n .O(\\init_state_r[0]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h0155455501550055)) \n \\init_state_r[0]_i_50 \n (.I0(\\init_state_r_reg[2]_0 ),\n .I1(prbs_rdlvl_done_reg_rep),\n .I2(prbs_last_byte_done_r),\n .I3(dqs_found_done_r_reg),\n .I4(rdlvl_stg1_done_int_reg),\n .I5(wrcal_done_reg_10),\n .O(\\init_state_r_reg[0]_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFC44)) \n \\init_state_r[0]_i_51 \n (.I0(rdlvl_stg1_start_int),\n .I1(prbs_rdlvl_done_reg_rep),\n .I2(\\one_rank.stg1_wr_done_reg_0 ),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(rdlvl_last_byte_done),\n .I5(prbs_last_byte_done),\n .O(\\init_state_r[0]_i_51_n_0 ));\n LUT6 #(\n .INIT(64'hEFAFFFBFFFFFFFFF)) \n \\init_state_r[0]_i_6 \n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(cnt_cmd_done_r),\n .I3(\\init_state_r[0]_i_16_n_0 ),\n .I4(ddr2_pre_flag_r_reg_0),\n .I5(\\init_state_r_reg[1]_0 ),\n .O(\\init_state_r[0]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hABAAABABABAAABAA)) \n \\init_state_r[0]_i_7 \n (.I0(\\init_state_r[5]_i_2_n_0 ),\n .I1(\\init_state_r[0]_i_17_n_0 ),\n .I2(\\init_state_r[0]_i_18_n_0 ),\n .I3(\\init_state_r[4]_i_5_n_0 ),\n .I4(\\init_state_r[0]_i_19_n_0 ),\n .I5(\\init_state_r[0]_i_20_n_0 ),\n .O(\\init_state_r[0]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h88008A008A008A00)) \n \\init_state_r[0]_i_8 \n (.I0(\\init_state_r[0]_i_21_n_0 ),\n .I1(Q[0]),\n .I2(Q[2]),\n .I3(Q[5]),\n .I4(\\init_state_r[5]_i_36_n_0 ),\n .I5(Q[1]),\n .O(\\init_state_r[0]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'h2222222200202222)) \n \\init_state_r[0]_i_9 \n (.I0(\\init_state_r[0]_i_22_n_0 ),\n .I1(\\init_state_r[0]_i_23_n_0 ),\n .I2(wrcal_done_reg_9),\n .I3(Q[0]),\n .I4(\\init_state_r[0]_i_24_n_0 ),\n .I5(\\init_state_r[0]_i_25_n_0 ),\n .O(\\init_state_r[0]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAAEEFE)) \n \\init_state_r[1]_i_1 \n (.I0(\\init_state_r[1]_i_2_n_0 ),\n .I1(\\init_state_r[1]_i_3_n_0 ),\n .I2(\\init_state_r_reg[1]_0 ),\n .I3(\\init_state_r[1]_i_5_n_0 ),\n .I4(\\init_state_r[5]_i_2_n_0 ),\n .I5(\\init_state_r[1]_i_6_n_0 ),\n .O(\\init_state_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair504\" *) \n LUT5 #(\n .INIT(32'hFFFBAAAA)) \n \\init_state_r[1]_i_10 \n (.I0(\\init_state_r[0]_i_14_n_0 ),\n .I1(num_reads[0]),\n .I2(num_reads[2]),\n .I3(num_reads[1]),\n .I4(Q[0]),\n .O(\\init_state_r[1]_i_10_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair526\" *) \n LUT5 #(\n .INIT(32'h22222220)) \n \\init_state_r[1]_i_11 \n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(dqs_found_done_r_reg),\n .I3(pi_dqs_found_rank_done),\n .I4(prech_pending_r_reg_0),\n .O(\\init_state_r[1]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'hBBBBBBFFBBFFBBFB)) \n \\init_state_r[1]_i_12 \n (.I0(\\init_state_r[1]_i_25_n_0 ),\n .I1(Q[3]),\n .I2(cnt_cmd_done_r),\n .I3(\\init_state_r[4]_i_5_n_0 ),\n .I4(Q[0]),\n .I5(Q[1]),\n .O(\\init_state_r[1]_i_12_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF0B0B080B)) \n \\init_state_r[1]_i_13 \n (.I0(wrlvl_byte_redo_reg),\n .I1(mpr_rdlvl_done_r_reg_2),\n .I2(\\init_state_r[1]_i_26_n_0 ),\n .I3(oclkdelay_calib_done_r_reg_2),\n .I4(\\init_state_r[1]_i_27_n_0 ),\n .I5(\\init_state_r[1]_i_28_n_0 ),\n .O(\\init_state_r[1]_i_13_n_0 ));\n LUT6 #(\n .INIT(64'hFFE0FFE0FFE0FFFF)) \n \\init_state_r[1]_i_15 \n (.I0(dqs_found_done_r_reg_2),\n .I1(prbs_last_byte_done_reg),\n .I2(\\init_state_r[1]_i_33_n_0 ),\n .I3(\\init_state_r[1]_i_34_n_0 ),\n .I4(Q[0]),\n .I5(\\init_state_r[5]_i_32_n_0 ),\n .O(\\init_state_r[1]_i_15_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair566\" *) \n LUT4 #(\n .INIT(16'h0020)) \n \\init_state_r[1]_i_16 \n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(cnt_dllk_zqinit_done_r),\n .I3(mem_init_done_r),\n .O(\\init_state_r[1]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF7070FF70)) \n \\init_state_r[1]_i_17 \n (.I0(Q[0]),\n .I1(wrlvl_rank_done_r7),\n .I2(\\init_state_r[1]_i_35_n_0 ),\n .I3(\\init_state_r_reg[1]_0 ),\n .I4(\\init_state_r[1]_i_36_n_0 ),\n .I5(Q[3]),\n .O(\\init_state_r[1]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'hE0000F0FE000FFFF)) \n \\init_state_r[1]_i_18 \n (.I0(cnt_init_mr_done_r),\n .I1(dqs_found_done_r_reg_0),\n .I2(Q[0]),\n .I3(cnt_cmd_done_r),\n .I4(Q[1]),\n .I5(cnt_txpr_done_r),\n .O(\\init_state_r[1]_i_18_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair533\" *) \n LUT5 #(\n .INIT(32'hF2F2F2FF)) \n \\init_state_r[1]_i_19 \n (.I0(cnt_cmd_done_r),\n .I1(wrcal_prech_req),\n .I2(Q[0]),\n .I3(prech_pending_r_reg_0),\n .I4(wrcal_done_reg_10),\n .O(\\init_state_r[1]_i_19_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF0200)) \n \\init_state_r[1]_i_2 \n (.I0(Q[4]),\n .I1(Q[5]),\n .I2(\\init_state_r[1]_i_7_n_0 ),\n .I3(\\init_state_r[1]_i_8_n_0 ),\n .I4(\\init_state_r[1]_i_9_n_0 ),\n .I5(\\init_state_r[5]_i_19_n_0 ),\n .O(\\init_state_r[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAABAAAAAAAAAA)) \n \\init_state_r[1]_i_20 \n (.I0(Q[1]),\n .I1(wrcal_wr_cnt_reg__0[3]),\n .I2(wrcal_wr_cnt_reg__0[2]),\n .I3(wrcal_wr_cnt_reg__0[0]),\n .I4(wrcal_wr_cnt_reg__0[1]),\n .I5(Q[0]),\n .O(\\init_state_r[1]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'hFEFEFEFEFFFEFEFE)) \n \\init_state_r[1]_i_21 \n (.I0(\\init_state_r[1]_i_37_n_0 ),\n .I1(Q[3]),\n .I2(mpr_rdlvl_done_r_reg_0),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[2]),\n .I5(\\init_state_r[5]_i_57_n_0 ),\n .O(\\init_state_r[1]_i_21_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair529\" *) \n LUT5 #(\n .INIT(32'hEFEEAAAA)) \n \\init_state_r[1]_i_22 \n (.I0(Q[1]),\n .I1(prech_pending_r_reg_0),\n .I2(complex_oclkdelay_calib_done_r1),\n .I3(prbs_rdlvl_done_reg_rep),\n .I4(Q[0]),\n .O(\\init_state_r[1]_i_22_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFAABA)) \n \\init_state_r[1]_i_23 \n (.I0(\\init_state_r[1]_i_39_n_0 ),\n .I1(Q[0]),\n .I2(\\init_state_r_reg[1]_0 ),\n .I3(\\init_state_r[1]_i_40_n_0 ),\n .I4(\\init_state_r[1]_i_41_n_0 ),\n .I5(\\init_state_r[1]_i_42_n_0 ),\n .O(\\init_state_r[1]_i_23_n_0 ));\n LUT6 #(\n .INIT(64'hCCCCCC88CCCCCC08)) \n \\init_state_r[1]_i_24 \n (.I0(\\init_state_r[5]_i_13_n_0 ),\n .I1(\\init_state_r[1]_i_43_n_0 ),\n .I2(\\init_state_r[0]_i_27_n_0 ),\n .I3(prech_pending_r_reg_0),\n .I4(prbs_rdlvl_done_pulse0),\n .I5(Q[0]),\n .O(\\init_state_r[1]_i_24_n_0 ));\n LUT6 #(\n .INIT(64'h2820202028202820)) \n \\init_state_r[1]_i_25 \n (.I0(\\wrcal_reads[7]_i_5_n_0 ),\n .I1(Q[0]),\n .I2(Q[1]),\n .I3(cnt_cmd_done_r),\n .I4(wrcal_sanity_chk_done_reg_0),\n .I5(rdlvl_stg1_done_int_reg_2),\n .O(\\init_state_r[1]_i_25_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair493\" *) \n LUT5 #(\n .INIT(32'h0020FFFF)) \n \\init_state_r[1]_i_26 \n (.I0(prbs_last_byte_done_r),\n .I1(prbs_rdlvl_done_reg_rep),\n .I2(dqs_found_done_r_reg),\n .I3(\\init_state_r_reg[2]_0 ),\n .I4(mem_init_done_r),\n .O(\\init_state_r[1]_i_26_n_0 ));\n LUT6 #(\n .INIT(64'h8A8A8A88AAAAAAAA)) \n \\init_state_r[1]_i_27 \n (.I0(wrlvl_final_mux_reg_0),\n .I1(wrlvl_done_r1),\n .I2(prbs_rdlvl_done_reg_rep),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(prbs_last_byte_done_r),\n .I5(prbs_rdlvl_done_reg_rep_3),\n .O(\\init_state_r[1]_i_27_n_0 ));\n LUT6 #(\n .INIT(64'h000000F200000000)) \n \\init_state_r[1]_i_28 \n (.I0(wrcal_done_reg_10),\n .I1(\\init_state_r[1]_i_46_n_0 ),\n .I2(prbs_rdlvl_done_reg_rep_1),\n .I3(mem_init_done_r),\n .I4(cnt_init_af_done_r),\n .I5(mpr_rdlvl_done_r_reg_1),\n .O(\\init_state_r[1]_i_28_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF0000FF5D)) \n \\init_state_r[1]_i_3 \n (.I0(\\init_state_r[1]_i_10_n_0 ),\n .I1(Q[1]),\n .I2(cnt_cmd_done_r),\n .I3(\\init_state_r[1]_i_11_n_0 ),\n .I4(oclk_calib_resume_level_reg_0),\n .I5(\\init_state_r[1]_i_12_n_0 ),\n .O(\\init_state_r[1]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair581\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\init_state_r[1]_i_33 \n (.I0(pi_calib_done),\n .I1(Q[1]),\n .O(\\init_state_r[1]_i_33_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF10000FFF)) \n \\init_state_r[1]_i_34 \n (.I0(rdlvl_stg1_done_r1),\n .I1(reset_rd_addr_r1),\n .I2(Q[0]),\n .I3(cnt_cmd_done_r),\n .I4(Q[1]),\n .I5(\\init_state_r[4]_i_5_n_0 ),\n .O(\\init_state_r[1]_i_34_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair570\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\init_state_r[1]_i_35 \n (.I0(Q[1]),\n .I1(Q[2]),\n .I2(\\init_state_r_reg_n_0_[3] ),\n .O(\\init_state_r[1]_i_35_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair566\" *) \n LUT3 #(\n .INIT(8'h07)) \n \\init_state_r[1]_i_36 \n (.I0(Q[0]),\n .I1(cnt_cmd_done_r),\n .I2(Q[1]),\n .O(\\init_state_r[1]_i_36_n_0 ));\n LUT6 #(\n .INIT(64'h4444444044404440)) \n \\init_state_r[1]_i_37 \n (.I0(Q[0]),\n .I1(\\wrcal_reads[7]_i_5_n_0 ),\n .I2(\\init_state_r[5]_i_49_n_0 ),\n .I3(Q[1]),\n .I4(wrcal_final_chk),\n .I5(wrcal_resume_r),\n .O(\\init_state_r[1]_i_37_n_0 ));\n LUT6 #(\n .INIT(64'h1FFF0000FFFFFFFF)) \n \\init_state_r[1]_i_39 \n (.I0(\\one_rank.stg1_wr_done_reg_0 ),\n .I1(oclkdelay_center_calib_start_r_reg),\n .I2(prbs_gen_oclk_clk_en_i_8_n_0),\n .I3(\\init_state_r[2]_i_33_n_0 ),\n .I4(\\init_state_r[1]_i_35_n_0 ),\n .I5(Q[3]),\n .O(\\init_state_r[1]_i_39_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair541\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\init_state_r[1]_i_4 \n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(Q[2]),\n .O(\\init_state_r_reg[1]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair551\" *) \n LUT4 #(\n .INIT(16'hB0BB)) \n \\init_state_r[1]_i_40 \n (.I0(prbs_rdlvl_done_r1),\n .I1(prbs_rdlvl_done_reg_rep),\n .I2(prbs_gen_oclk_clk_en_i_8_n_0),\n .I3(Q[1]),\n .O(\\init_state_r[1]_i_40_n_0 ));\n LUT6 #(\n .INIT(64'h1515100015155444)) \n \\init_state_r[1]_i_41 \n (.I0(oclk_calib_resume_level_reg_0),\n .I1(Q[1]),\n .I2(cnt_cmd_done_r),\n .I3(oclkdelay_int_ref_req_reg_0),\n .I4(Q[0]),\n .I5(\\init_state_r[1]_i_47_n_0 ),\n .O(\\init_state_r[1]_i_41_n_0 ));\n LUT6 #(\n .INIT(64'h0000000088880080)) \n \\init_state_r[1]_i_42 \n (.I0(Q[0]),\n .I1(\\wrcal_reads[7]_i_5_n_0 ),\n .I2(prbs_gen_oclk_clk_en_i_8_n_0),\n .I3(\\init_state_r[1]_i_48_n_0 ),\n .I4(prbs_rdlvl_done_pulse0),\n .I5(Q[1]),\n .O(\\init_state_r[1]_i_42_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair570\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\init_state_r[1]_i_43 \n (.I0(Q[1]),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .I2(Q[2]),\n .O(\\init_state_r[1]_i_43_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\init_state_r[1]_i_46 \n (.I0(wrlvl_final_mux),\n .I1(wrlvl_done_r1),\n .O(\\init_state_r[1]_i_46_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000010000)) \n \\init_state_r[1]_i_47 \n (.I0(wrlvl_final_mux),\n .I1(oclkdelay_int_ref_req_reg_0),\n .I2(prech_pending_r_reg_0),\n .I3(oclkdelay_calib_done_r_reg_2),\n .I4(oclkdelay_center_calib_start_r_reg),\n .I5(\\init_state_r[6]_i_16_n_0 ),\n .O(\\init_state_r[1]_i_47_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair510\" *) \n LUT5 #(\n .INIT(32'h0000CC40)) \n \\init_state_r[1]_i_48 \n (.I0(complex_oclkdelay_calib_start_int),\n .I1(done_r_reg),\n .I2(prbs_last_byte_done_r),\n .I3(prbs_rdlvl_done_reg_rep),\n .I4(complex_oclkdelay_calib_start_r2),\n .O(\\init_state_r[1]_i_48_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF00002222F0FF)) \n \\init_state_r[1]_i_5 \n (.I0(\\init_state_r[1]_i_13_n_0 ),\n .I1(oclkdelay_calib_done_r_reg_4),\n .I2(ddr2_pre_flag_r_reg_0),\n .I3(cnt_cmd_done_r),\n .I4(Q[1]),\n .I5(Q[0]),\n .O(\\init_state_r[1]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h0000A2AA0000A0A8)) \n \\init_state_r[1]_i_6 \n (.I0(\\init_state_r[1]_i_15_n_0 ),\n .I1(Q[2]),\n .I2(\\init_state_r_reg_n_0_[3] ),\n .I3(\\init_state_r[1]_i_16_n_0 ),\n .I4(\\init_state_r[1]_i_17_n_0 ),\n .I5(\\init_state_r[1]_i_18_n_0 ),\n .O(\\init_state_r[1]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h00000000BABAFFBA)) \n \\init_state_r[1]_i_7 \n (.I0(oclk_calib_resume_level_reg_0),\n .I1(prbs_rdlvl_start_i_2_n_0),\n .I2(burst_addr_r_reg_0),\n .I3(\\init_state_r[1]_i_19_n_0 ),\n .I4(\\init_state_r[1]_i_20_n_0 ),\n .I5(\\init_state_r[1]_i_21_n_0 ),\n .O(\\init_state_r[1]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF00FD)) \n \\init_state_r[1]_i_8 \n (.I0(\\init_state_r[5]_i_42_n_0 ),\n .I1(\\init_state_r[1]_i_22_n_0 ),\n .I2(prbs_gen_oclk_clk_en_i_8_n_0),\n .I3(\\init_state_r[4]_i_5_n_0 ),\n .I4(\\init_state_r[1]_i_23_n_0 ),\n .I5(\\init_state_r[1]_i_24_n_0 ),\n .O(\\init_state_r[1]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'hFF80FFFF80808080)) \n \\init_state_r[1]_i_9 \n (.I0(Q[5]),\n .I1(Q[2]),\n .I2(Q[1]),\n .I3(prech_pending_r_reg_0),\n .I4(oclkdelay_calib_done_r_reg_2),\n .I5(\\init_state_r[6]_i_11_n_0 ),\n .O(\\init_state_r[1]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hAEAEAEAAAEAEAEAE)) \n \\init_state_r[2]_i_1 \n (.I0(\\init_state_r[2]_i_2_n_0 ),\n .I1(\\init_state_r[2]_i_3_n_0 ),\n .I2(\\init_state_r[5]_i_2_n_0 ),\n .I3(\\init_state_r[2]_i_4_n_0 ),\n .I4(\\init_state_r[2]_i_5_n_0 ),\n .I5(\\init_state_r[2]_i_6_n_0 ),\n .O(\\init_state_r[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAA0002)) \n \\init_state_r[2]_i_10 \n (.I0(\\init_state_r[2]_i_25_n_0 ),\n .I1(dqs_found_done_r_reg_0),\n .I2(cnt_init_mr_done_r),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[2]),\n .I5(\\init_state_r[2]_i_26_n_0 ),\n .O(\\init_state_r[2]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'hF2FF000000000000)) \n \\init_state_r[2]_i_11 \n (.I0(pi_calib_done),\n .I1(wrcal_done_reg_11),\n .I2(Q[1]),\n .I3(cnt_cmd_done_r),\n .I4(\\init_state_r[2]_i_27_n_0 ),\n .I5(\\init_state_r[0]_i_20_n_0 ),\n .O(\\init_state_r[2]_i_11_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair533\" *) \n LUT2 #(\n .INIT(4'h7)) \n \\init_state_r[2]_i_12 \n (.I0(Q[0]),\n .I1(cnt_cmd_done_r),\n .O(\\init_state_r[2]_i_12_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair497\" *) \n LUT5 #(\n .INIT(32'h45454500)) \n \\init_state_r[2]_i_14 \n (.I0(\\init_state_r_reg[2]_0 ),\n .I1(mem_init_done_r),\n .I2(cnt_init_af_done_r),\n .I3(prbs_rdlvl_done_reg_rep_1),\n .I4(\\init_state_r[4]_i_26_n_0 ),\n .O(\\init_state_r[2]_i_14_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair506\" *) \n LUT2 #(\n .INIT(4'h7)) \n \\init_state_r[2]_i_16 \n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(Q[1]),\n .O(\\init_state_r[2]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'hAAAABFFFAAAABBBB)) \n \\init_state_r[2]_i_17 \n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(cnt_cmd_done_r),\n .I4(Q[2]),\n .I5(\\init_state_r[5]_i_56_n_0 ),\n .O(\\init_state_r[2]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'h80AA808080AA80AA)) \n \\init_state_r[2]_i_18 \n (.I0(Q[2]),\n .I1(prbs_rdlvl_done_pulse0),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .I3(\\init_state_r[6]_i_22_n_0 ),\n .I4(\\init_state_r[2]_i_32_n_0 ),\n .I5(\\init_state_r[2]_i_33_n_0 ),\n .O(\\init_state_r[2]_i_18_n_0 ));\n LUT6 #(\n .INIT(64'hF200FFFFF200F200)) \n \\init_state_r[2]_i_2 \n (.I0(complex_pi_incdec_done),\n .I1(prbs_rdlvl_start_i_2_n_0),\n .I2(\\init_state_r[2]_i_7_n_0 ),\n .I3(Q[5]),\n .I4(\\init_state_r[2]_i_8_n_0 ),\n .I5(\\init_state_r[2]_i_9_n_0 ),\n .O(\\init_state_r[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h10111010FFFFFFFF)) \n \\init_state_r[2]_i_20 \n (.I0(\\init_state_r[2]_i_16_n_0 ),\n .I1(Q[2]),\n .I2(complex_oclkdelay_calib_start_int_reg_0),\n .I3(prbs_rdlvl_done_pulse0),\n .I4(prbs_gen_oclk_clk_en_i_8_n_0),\n .I5(Q[3]),\n .O(\\init_state_r[2]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'hF000F2F200000000)) \n \\init_state_r[2]_i_21 \n (.I0(pi_phase_locked_all_r3),\n .I1(pi_phase_locked_all_r4),\n .I2(Q[0]),\n .I3(\\init_state_r[2]_i_34_n_0 ),\n .I4(\\init_state_r_reg_n_0_[3] ),\n .I5(\\init_state_r[2]_i_35_n_0 ),\n .O(\\init_state_r[2]_i_21_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF010FFFFFFFFF)) \n \\init_state_r[2]_i_22 \n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(burst_addr_r_reg_0),\n .I2(Q[2]),\n .I3(Q[1]),\n .I4(Q[5]),\n .I5(Q[4]),\n .O(\\init_state_r[2]_i_22_n_0 ));\n LUT6 #(\n .INIT(64'hFFBFBBBBAAAAAAAA)) \n \\init_state_r[2]_i_24 \n (.I0(Q[0]),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .I2(\\init_state_r[2]_i_36_n_0 ),\n .I3(cnt_cmd_done_r_reg_1),\n .I4(Q[1]),\n .I5(Q[2]),\n .O(\\init_state_r[2]_i_24_n_0 ));\n LUT6 #(\n .INIT(64'hFF0F4F4F0F0F0F0F)) \n \\init_state_r[2]_i_25 \n (.I0(mem_init_done_r),\n .I1(cnt_dllk_zqinit_done_r),\n .I2(Q[2]),\n .I3(wrlvl_rank_done_r7),\n .I4(Q[1]),\n .I5(Q[0]),\n .O(\\init_state_r[2]_i_25_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair548\" *) \n LUT3 #(\n .INIT(8'h7F)) \n \\init_state_r[2]_i_26 \n (.I0(cnt_cmd_done_r),\n .I1(Q[0]),\n .I2(Q[1]),\n .O(\\init_state_r[2]_i_26_n_0 ));\n LUT6 #(\n .INIT(64'hEC00FFF0ECF0FFF0)) \n \\init_state_r[2]_i_27 \n (.I0(reset_rd_addr_r1),\n .I1(cnt_cmd_done_r),\n .I2(Q[1]),\n .I3(Q[0]),\n .I4(Q[2]),\n .I5(complex_sample_cnt_inc_i_2_n_0),\n .O(\\init_state_r[2]_i_27_n_0 ));\n LUT6 #(\n .INIT(64'hF0FFF1F1F3F3F3F3)) \n \\init_state_r[2]_i_3 \n (.I0(wrlvl_done_r1),\n .I1(\\init_state_r[2]_i_10_n_0 ),\n .I2(Q[3]),\n .I3(\\init_state_r[2]_i_11_n_0 ),\n .I4(Q[2]),\n .I5(\\init_state_r_reg_n_0_[3] ),\n .O(\\init_state_r[2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hAB00AB00AB00ABFF)) \n \\init_state_r[2]_i_30 \n (.I0(\\init_state_r[2]_i_37_n_0 ),\n .I1(wrlvl_done_r1),\n .I2(wrlvl_byte_redo),\n .I3(mem_init_done_r),\n .I4(wrcal_done_reg_10),\n .I5(cnt_init_af_done_r),\n .O(\\init_state_r_reg[2]_1 ));\n LUT6 #(\n .INIT(64'h8000800080000000)) \n \\init_state_r[2]_i_32 \n (.I0(complex_wait_cnt_reg__0[3]),\n .I1(complex_wait_cnt_reg__0[2]),\n .I2(complex_wait_cnt_reg__0[1]),\n .I3(complex_wait_cnt_reg__0[0]),\n .I4(oclkdelay_center_calib_start_r_reg),\n .I5(\\one_rank.stg1_wr_done_reg_0 ),\n .O(\\init_state_r[2]_i_32_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair526\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\init_state_r[2]_i_33 \n (.I0(Q[0]),\n .I1(prech_pending_r_reg_0),\n .O(\\init_state_r[2]_i_33_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair547\" *) \n LUT4 #(\n .INIT(16'h0010)) \n \\init_state_r[2]_i_34 \n (.I0(oclk_wr_cnt_reg__0[3]),\n .I1(oclk_wr_cnt_reg__0[1]),\n .I2(oclk_wr_cnt_reg__0[0]),\n .I3(oclk_wr_cnt_reg__0[2]),\n .O(\\init_state_r[2]_i_34_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair551\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\init_state_r[2]_i_35 \n (.I0(Q[2]),\n .I1(Q[1]),\n .O(\\init_state_r[2]_i_35_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair534\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\init_state_r[2]_i_36 \n (.I0(prech_pending_r_reg_0),\n .I1(oclkdelay_calib_done_r_reg_2),\n .O(\\init_state_r[2]_i_36_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair574\" *) \n LUT3 #(\n .INIT(8'hDF)) \n \\init_state_r[2]_i_37 \n (.I0(prbs_last_byte_done_r),\n .I1(prbs_rdlvl_done_reg_rep),\n .I2(dqs_found_done_r_reg),\n .O(\\init_state_r[2]_i_37_n_0 ));\n LUT6 #(\n .INIT(64'hEEFE000000000000)) \n \\init_state_r[2]_i_4 \n (.I0(wrcal_sanity_chk_done_reg_0),\n .I1(\\init_state_r[2]_i_12_n_0 ),\n .I2(ddr3_lm_done_r),\n .I3(rdlvl_stg1_done_int_reg_2),\n .I4(prbs_rdlvl_start_i_2_n_0),\n .I5(\\wrcal_reads[7]_i_5_n_0 ),\n .O(\\init_state_r[2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h5FF755555555D555)) \n \\init_state_r[2]_i_5 \n (.I0(Q[3]),\n .I1(cnt_cmd_done_r),\n .I2(Q[0]),\n .I3(Q[1]),\n .I4(Q[2]),\n .I5(\\init_state_r_reg_n_0_[3] ),\n .O(\\init_state_r[2]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF040F)) \n \\init_state_r[2]_i_6 \n (.I0(\\init_state_r[2]_i_14_n_0 ),\n .I1(cnt_init_af_done_r_reg_1),\n .I2(Q[0]),\n .I3(cnt_cmd_done_r),\n .I4(Q[2]),\n .I5(\\init_state_r[2]_i_16_n_0 ),\n .O(\\init_state_r[2]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hAAAEAAAAAAAAAAAA)) \n \\init_state_r[2]_i_7 \n (.I0(Q[2]),\n .I1(oclkdelay_calib_done_r_reg_2),\n .I2(prech_pending_r_reg_0),\n .I3(Q[1]),\n .I4(Q[0]),\n .I5(\\init_state_r[6]_i_21_n_0 ),\n .O(\\init_state_r[2]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h000E000E0000000E)) \n \\init_state_r[2]_i_8 \n (.I0(\\init_state_r[2]_i_17_n_0 ),\n .I1(\\init_state_r[2]_i_18_n_0 ),\n .I2(\\init_state_r_reg[2]_2 ),\n .I3(\\init_state_r[2]_i_20_n_0 ),\n .I4(\\init_state_r[5]_i_42_n_0 ),\n .I5(\\init_state_r[5]_i_41_n_0 ),\n .O(\\init_state_r[2]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'h11010000FFFFFFFF)) \n \\init_state_r[2]_i_9 \n (.I0(\\init_state_r[2]_i_21_n_0 ),\n .I1(\\init_state_r[2]_i_22_n_0 ),\n .I2(\\wrcal_reads[7]_i_6_n_0 ),\n .I3(wrcal_done_reg_9),\n .I4(\\init_state_r[2]_i_24_n_0 ),\n .I5(complex_oclkdelay_calib_start_int_i_2_n_0),\n .O(\\init_state_r[2]_i_9_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair484\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\init_state_r[3]_i_1 \n (.I0(\\init_state_r[3]_i_2_n_0 ),\n .O(\\init_state_r[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair565\" *) \n LUT4 #(\n .INIT(16'h0111)) \n \\init_state_r[3]_i_10 \n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(ddr2_pre_flag_r_reg_0),\n .I3(cnt_cmd_done_r),\n .O(\\init_state_r[3]_i_10_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair579\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\init_state_r[3]_i_11 \n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(cnt_cmd_done_r),\n .O(\\init_state_r[3]_i_11_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair532\" *) \n LUT5 #(\n .INIT(32'hF3FF23FF)) \n \\init_state_r[3]_i_13 \n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(cnt_cmd_done_r),\n .I2(Q[1]),\n .I3(Q[0]),\n .I4(reset_rd_addr_r1),\n .O(\\init_state_r[3]_i_13_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair494\" *) \n LUT5 #(\n .INIT(32'hFEFFFFFF)) \n \\init_state_r[3]_i_14 \n (.I0(Q[5]),\n .I1(Q[4]),\n .I2(Q[3]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[2]),\n .O(\\init_state_r[3]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF4440)) \n \\init_state_r[3]_i_15 \n (.I0(\\wrcal_reads[7]_i_5_n_0 ),\n .I1(Q[5]),\n .I2(\\init_state_r[3]_i_19_n_0 ),\n .I3(\\init_state_r[3]_i_20_n_0 ),\n .I4(\\init_state_r[3]_i_21_n_0 ),\n .I5(\\init_state_r[3]_i_22_n_0 ),\n .O(\\init_state_r[3]_i_15_n_0 ));\n LUT6 #(\n .INIT(64'h0202222202022202)) \n \\init_state_r[3]_i_16 \n (.I0(\\init_state_r[5]_i_41_n_0 ),\n .I1(\\init_state_r_reg[2]_2 ),\n .I2(\\init_state_r[5]_i_53_n_0 ),\n .I3(prbs_gen_oclk_clk_en_i_8_n_0),\n .I4(complex_oclkdelay_calib_start_int_reg_0),\n .I5(prbs_rdlvl_done_pulse0),\n .O(\\init_state_r[3]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'hFFDDFFFFF0DDFFFF)) \n \\init_state_r[3]_i_17 \n (.I0(\\init_state_r[3]_i_23_n_0 ),\n .I1(prbs_rdlvl_done_pulse0),\n .I2(prech_pending_r_reg_0),\n .I3(Q[1]),\n .I4(Q[0]),\n .I5(oclkdelay_center_calib_start_r_reg),\n .O(\\init_state_r[3]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'hCFFFAFCF00FF00CF)) \n \\init_state_r[3]_i_18 \n (.I0(oclkdelay_center_calib_start_r_reg_0),\n .I1(cnt_cmd_done_r),\n .I2(\\init_state_r_reg_n_0_[3] ),\n .I3(Q[1]),\n .I4(Q[0]),\n .I5(\\init_state_r[5]_i_56_n_0 ),\n .O(\\init_state_r[3]_i_18_n_0 ));\n LUT6 #(\n .INIT(64'h0044000000440400)) \n \\init_state_r[3]_i_19 \n (.I0(Q[1]),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .I2(prech_pending_r_reg_0),\n .I3(Q[0]),\n .I4(write_request_r_reg),\n .I5(\\init_state_r[6]_i_21_n_0 ),\n .O(\\init_state_r[3]_i_19_n_0 ));\n LUT6 #(\n .INIT(64'h00FE00FE00FE0000)) \n \\init_state_r[3]_i_2 \n (.I0(\\init_state_r[3]_i_3_n_0 ),\n .I1(\\init_state_r[3]_i_4_n_0 ),\n .I2(\\init_state_r[3]_i_5_n_0 ),\n .I3(\\init_state_r[3]_i_6_n_0 ),\n .I4(complex_oclkdelay_calib_start_int_i_2_n_0),\n .I5(\\init_state_r[3]_i_7_n_0 ),\n .O(\\init_state_r[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF08880800)) \n \\init_state_r[3]_i_20 \n (.I0(Q[1]),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .I2(complex_pi_incdec_done),\n .I3(Q[0]),\n .I4(\\init_state_r[5]_i_36_n_0 ),\n .I5(\\init_state_r[2]_i_7_n_0 ),\n .O(\\init_state_r[3]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'h0000000011014444)) \n \\init_state_r[3]_i_21 \n (.I0(rdlvl_stg1_start_int_i_2_n_0),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .I2(Q[1]),\n .I3(wrlvl_rank_done_r7),\n .I4(Q[2]),\n .I5(\\init_state_r[3]_i_24_n_0 ),\n .O(\\init_state_r[3]_i_21_n_0 ));\n LUT6 #(\n .INIT(64'h0000AFAF0000C000)) \n \\init_state_r[3]_i_22 \n (.I0(\\init_state_r[4]_i_27_n_0 ),\n .I1(Q[1]),\n .I2(Q[2]),\n .I3(Q[0]),\n .I4(read_calib_i_2_n_0),\n .I5(\\init_state_r_reg_n_0_[3] ),\n .O(\\init_state_r[3]_i_22_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair510\" *) \n LUT4 #(\n .INIT(16'h3B30)) \n \\init_state_r[3]_i_23 \n (.I0(complex_oclkdelay_calib_start_int),\n .I1(done_r_reg),\n .I2(prbs_rdlvl_done_reg_rep),\n .I3(prbs_last_byte_done_r),\n .O(\\init_state_r[3]_i_23_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF40434343)) \n \\init_state_r[3]_i_24 \n (.I0(\\init_state_r[2]_i_12_n_0 ),\n .I1(Q[1]),\n .I2(\\init_state_r_reg_n_0_[3] ),\n .I3(cnt_dllk_zqinit_done_r),\n .I4(mem_init_done_r),\n .I5(\\init_state_r[3]_i_25_n_0 ),\n .O(\\init_state_r[3]_i_24_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair524\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\init_state_r[3]_i_25 \n (.I0(Q[2]),\n .I1(Q[0]),\n .O(\\init_state_r[3]_i_25_n_0 ));\n LUT6 #(\n .INIT(64'h08AAAAAA08AA08AA)) \n \\init_state_r[3]_i_3 \n (.I0(\\init_state_r[4]_i_11_n_0 ),\n .I1(cnt_init_af_done_r),\n .I2(mem_init_done_r),\n .I3(mpr_rdlvl_done_r_reg_1),\n .I4(\\init_state_r[4]_i_26_n_0 ),\n .I5(dqs_found_done_r_reg_1),\n .O(\\init_state_r[3]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFDDDD00F0)) \n \\init_state_r[3]_i_4 \n (.I0(\\init_state_r[2]_i_16_n_0 ),\n .I1(\\init_state_r[4]_i_21_n_0 ),\n .I2(\\init_state_r[3]_i_10_n_0 ),\n .I3(\\init_state_r[3]_i_11_n_0 ),\n .I4(Q[2]),\n .I5(rdlvl_start_pre_reg_0),\n .O(\\init_state_r[3]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h0155555505555555)) \n \\init_state_r[3]_i_5 \n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(cnt_cmd_done_r),\n .I2(Q[1]),\n .I3(Q[0]),\n .I4(Q[2]),\n .I5(wrcal_sanity_chk_done_reg),\n .O(\\init_state_r[3]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF0000FF08)) \n \\init_state_r[3]_i_6 \n (.I0(wrcal_done_reg_11),\n .I1(pi_calib_done),\n .I2(Q[1]),\n .I3(\\init_state_r[3]_i_13_n_0 ),\n .I4(\\init_state_r[3]_i_14_n_0 ),\n .I5(\\init_state_r[3]_i_15_n_0 ),\n .O(\\init_state_r[3]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAA2AAAA0AA20)) \n \\init_state_r[3]_i_7 \n (.I0(\\init_state_r[3]_i_16_n_0 ),\n .I1(prbs_gen_oclk_clk_en_i_8_n_0),\n .I2(Q[2]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(\\init_state_r[3]_i_17_n_0 ),\n .I5(\\init_state_r[3]_i_18_n_0 ),\n .O(\\init_state_r[3]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF55550051)) \n \\init_state_r[4]_i_1 \n (.I0(\\init_state_r[4]_i_2_n_0 ),\n .I1(\\init_state_r[4]_i_3_n_0 ),\n .I2(\\init_state_r[4]_i_4_n_0 ),\n .I3(\\init_state_r[4]_i_5_n_0 ),\n .I4(\\init_state_r[4]_i_6_n_0 ),\n .I5(\\init_state_r[4]_i_7_n_0 ),\n .O(\\init_state_r[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAAAA88A888888888)) \n \\init_state_r[4]_i_10 \n (.I0(\\init_state_r[4]_i_22_n_0 ),\n .I1(mem_init_done_r_reg_2),\n .I2(\\init_state_r_reg[2]_0 ),\n .I3(rdlvl_stg1_done_int_reg_3),\n .I4(\\init_state_r[4]_i_26_n_0 ),\n .I5(wrlvl_byte_redo_reg),\n .O(\\init_state_r[4]_i_10_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair565\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\init_state_r[4]_i_11 \n (.I0(cnt_cmd_done_r),\n .I1(Q[1]),\n .I2(Q[0]),\n .O(\\init_state_r[4]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'h0001000DFFFFFFFF)) \n \\init_state_r[4]_i_12 \n (.I0(Q[3]),\n .I1(cnt_cmd_done_r),\n .I2(Q[1]),\n .I3(Q[0]),\n .I4(ddr2_pre_flag_r_reg_0),\n .I5(\\init_state_r_reg[1]_0 ),\n .O(\\init_state_r[4]_i_12_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair581\" *) \n LUT3 #(\n .INIT(8'h8A)) \n \\init_state_r[4]_i_13 \n (.I0(pi_calib_done),\n .I1(wrcal_done_reg_10),\n .I2(dqs_found_done_r_reg),\n .O(\\init_state_r[4]_i_13_n_0 ));\n LUT6 #(\n .INIT(64'hFF540000FF5C000C)) \n \\init_state_r[4]_i_14 \n (.I0(rdlvl_stg1_start_int),\n .I1(\\one_rank.stg1_wr_done_reg_0 ),\n .I2(rdlvl_last_byte_done),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(prbs_rdlvl_done_reg_rep),\n .I5(prbs_last_byte_done),\n .O(\\init_state_r_reg[4]_0 ));\n LUT6 #(\n .INIT(64'h0080000000000000)) \n \\init_state_r[4]_i_15 \n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(\\init_state_r_reg_n_0_[3] ),\n .I3(Q[2]),\n .I4(wrlvl_done_r1),\n .I5(cnt_cmd_done_r),\n .O(\\init_state_r[4]_i_15_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFF01FF01FF01)) \n \\init_state_r[4]_i_16 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .I1(\\init_state_r[4]_i_5_n_0 ),\n .I2(\\init_state_r[4]_i_27_n_0 ),\n .I3(\\init_state_r[4]_i_28_n_0 ),\n .I4(\\init_state_r[4]_i_29_n_0 ),\n .I5(\\init_state_r[5]_i_49_n_0 ),\n .O(\\init_state_r[4]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FF77F7F7)) \n \\init_state_r[4]_i_17 \n (.I0(Q[3]),\n .I1(Q[1]),\n .I2(cnt_cmd_done_r),\n .I3(burst_addr_r_reg_0),\n .I4(Q[0]),\n .I5(\\init_state_r[5]_i_51_n_0 ),\n .O(\\init_state_r[4]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFEAA)) \n \\init_state_r[4]_i_18 \n (.I0(\\init_state_r[4]_i_30_n_0 ),\n .I1(prech_pending_r_reg_0),\n .I2(\\init_state_r[5]_i_13_n_0 ),\n .I3(\\init_state_r_reg[1]_0 ),\n .I4(\\init_state_r[4]_i_31_n_0 ),\n .I5(\\init_state_r[4]_i_32_n_0 ),\n .O(\\init_state_r[4]_i_18_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFEA00)) \n \\init_state_r[4]_i_19 \n (.I0(Q[3]),\n .I1(complex_pi_incdec_done),\n .I2(Q[0]),\n .I3(\\init_state_r[5]_i_19_n_0 ),\n .I4(\\init_state_r[4]_i_33_n_0 ),\n .I5(\\init_state_r[6]_i_11_n_0 ),\n .O(\\init_state_r[4]_i_19_n_0 ));\n LUT6 #(\n .INIT(64'hABABABABAAABAAAA)) \n \\init_state_r[4]_i_2 \n (.I0(\\init_state_r[5]_i_2_n_0 ),\n .I1(\\init_state_r[4]_i_8_n_0 ),\n .I2(\\init_state_r[4]_i_9_n_0 ),\n .I3(\\init_state_r[4]_i_10_n_0 ),\n .I4(\\init_state_r[4]_i_11_n_0 ),\n .I5(\\init_state_r[4]_i_12_n_0 ),\n .O(\\init_state_r[4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h4000000000000000)) \n \\init_state_r[4]_i_20 \n (.I0(ddr3_lm_done_r),\n .I1(wrcal_done_reg_10),\n .I2(dqs_found_done_r_reg),\n .I3(wrlvl_done_r1),\n .I4(prbs_rdlvl_done_reg_rep),\n .I5(rdlvl_stg1_done_int_reg),\n .O(\\init_state_r[4]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000400)) \n \\init_state_r[4]_i_21 \n (.I0(Q[0]),\n .I1(cnt_cmd_done_r),\n .I2(reg_ctrl_cnt_r_reg__0[2]),\n .I3(reg_ctrl_cnt_r_reg__0[3]),\n .I4(reg_ctrl_cnt_r_reg__0[0]),\n .I5(reg_ctrl_cnt_r_reg__0[1]),\n .O(\\init_state_r[4]_i_21_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair497\" *) \n LUT2 #(\n .INIT(4'hB)) \n \\init_state_r[4]_i_22 \n (.I0(mem_init_done_r),\n .I1(cnt_init_af_done_r),\n .O(\\init_state_r[4]_i_22_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair485\" *) \n LUT4 #(\n .INIT(16'hFEFF)) \n \\init_state_r[4]_i_24 \n (.I0(num_refresh_reg__0[1]),\n .I1(num_refresh_reg__0[0]),\n .I2(num_refresh_reg__0[2]),\n .I3(num_refresh_reg__0[3]),\n .O(\\init_state_r_reg[2]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair493\" *) \n LUT4 #(\n .INIT(16'h0800)) \n \\init_state_r[4]_i_26 \n (.I0(mem_init_done_r),\n .I1(dqs_found_done_r_reg),\n .I2(prbs_rdlvl_done_reg_rep),\n .I3(prbs_last_byte_done_r),\n .O(\\init_state_r[4]_i_26_n_0 ));\n LUT6 #(\n .INIT(64'h00FF00AB00FF0000)) \n \\init_state_r[4]_i_27 \n (.I0(cnt_cmd_done_r_reg_1),\n .I1(prech_pending_r_reg_0),\n .I2(oclkdelay_calib_done_r_reg_2),\n .I3(\\init_state_r[5]_i_57_n_0 ),\n .I4(Q[0]),\n .I5(Q[1]),\n .O(\\init_state_r[4]_i_27_n_0 ));\n LUT4 #(\n .INIT(16'hABAA)) \n \\init_state_r[4]_i_28 \n (.I0(Q[3]),\n .I1(read_calib_reg_0),\n .I2(pi_phase_locked_all_r4),\n .I3(pi_phase_locked_all_r3),\n .O(\\init_state_r[4]_i_28_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair536\" *) \n LUT4 #(\n .INIT(16'h0004)) \n \\init_state_r[4]_i_29 \n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(Q[2]),\n .I2(Q[1]),\n .I3(Q[0]),\n .O(\\init_state_r[4]_i_29_n_0 ));\n LUT6 #(\n .INIT(64'h75FF75FF00FFFFFF)) \n \\init_state_r[4]_i_3 \n (.I0(\\init_state_r[4]_i_13_n_0 ),\n .I1(\\init_state_r_reg[4]_0 ),\n .I2(dqs_found_done_r_reg),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .I4(Q[3]),\n .I5(cnt_cmd_done_r),\n .O(\\init_state_r[4]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h4444454445454545)) \n \\init_state_r[4]_i_30 \n (.I0(\\init_state_r[4]_i_5_n_0 ),\n .I1(oclk_calib_resume_r_reg),\n .I2(Q[1]),\n .I3(Q[3]),\n .I4(prbs_gen_oclk_clk_en_i_8_n_0),\n .I5(\\init_state_r[4]_i_37_n_0 ),\n .O(\\init_state_r[4]_i_30_n_0 ));\n LUT6 #(\n .INIT(64'h45004545FFFFFFFF)) \n \\init_state_r[4]_i_31 \n (.I0(oclk_calib_resume_level_reg_0),\n .I1(\\init_state_r[5]_i_56_n_0 ),\n .I2(Q[1]),\n .I3(\\init_state_r[6]_i_17_n_0 ),\n .I4(oclkdelay_center_calib_start_r_reg),\n .I5(Q[3]),\n .O(\\init_state_r[4]_i_31_n_0 ));\n LUT6 #(\n .INIT(64'h2828282828282800)) \n \\init_state_r[4]_i_32 \n (.I0(\\init_state_r[4]_i_38_n_0 ),\n .I1(Q[2]),\n .I2(\\init_state_r_reg_n_0_[3] ),\n .I3(prbs_gen_oclk_clk_en_i_8_n_0),\n .I4(\\init_state_r[4]_i_39_n_0 ),\n .I5(Q[3]),\n .O(\\init_state_r[4]_i_32_n_0 ));\n LUT6 #(\n .INIT(64'hFF00060000000000)) \n \\init_state_r[4]_i_33 \n (.I0(Q[0]),\n .I1(write_request_r_reg),\n .I2(Q[1]),\n .I3(Q[3]),\n .I4(Q[2]),\n .I5(Q[5]),\n .O(\\init_state_r[4]_i_33_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair488\" *) \n LUT5 #(\n .INIT(32'h2022FFFF)) \n \\init_state_r[4]_i_37 \n (.I0(complex_sample_cnt_inc_i_2_n_0),\n .I1(prech_pending_r_reg_0),\n .I2(complex_oclkdelay_calib_done_r1),\n .I3(prbs_rdlvl_done_reg),\n .I4(Q[0]),\n .O(\\init_state_r[4]_i_37_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFD00)) \n \\init_state_r[4]_i_38 \n (.I0(\\init_state_r[5]_i_54_n_0 ),\n .I1(\\init_state_r[4]_i_40_n_0 ),\n .I2(prech_pending_r_reg_0),\n .I3(Q[0]),\n .I4(\\init_state_r[6]_i_22_n_0 ),\n .I5(\\init_state_r_reg[1]_0 ),\n .O(\\init_state_r[4]_i_38_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair548\" *) \n LUT4 #(\n .INIT(16'hF4FF)) \n \\init_state_r[4]_i_39 \n (.I0(prbs_rdlvl_done_r1),\n .I1(prbs_rdlvl_done_reg),\n .I2(Q[1]),\n .I3(Q[0]),\n .O(\\init_state_r[4]_i_39_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAFFFFAAAABBFA)) \n \\init_state_r[4]_i_4 \n (.I0(\\init_state_r[5]_i_12_n_0 ),\n .I1(rdlvl_stg1_done_r1),\n .I2(Q[3]),\n .I3(cnt_cmd_done_r),\n .I4(prbs_rdlvl_start_i_2_n_0),\n .I5(reset_rd_addr_r1),\n .O(\\init_state_r[4]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair508\" *) \n LUT5 #(\n .INIT(32'h2AAAAAAA)) \n \\init_state_r[4]_i_40 \n (.I0(Q[3]),\n .I1(complex_wait_cnt_reg__0[3]),\n .I2(complex_wait_cnt_reg__0[2]),\n .I3(complex_wait_cnt_reg__0[1]),\n .I4(complex_wait_cnt_reg__0[0]),\n .O(\\init_state_r[4]_i_40_n_0 ));\n LUT2 #(\n .INIT(4'h7)) \n \\init_state_r[4]_i_5 \n (.I0(Q[2]),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .O(\\init_state_r[4]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF0400)) \n \\init_state_r[4]_i_6 \n (.I0(oclk_calib_resume_level_reg_0),\n .I1(cnt_cmd_done_r),\n .I2(prbs_rdlvl_start_i_2_n_0),\n .I3(dqs_found_done_r_reg_0),\n .I4(\\init_state_r[4]_i_15_n_0 ),\n .I5(Q[3]),\n .O(\\init_state_r[4]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF44450000)) \n \\init_state_r[4]_i_7 \n (.I0(\\init_state_r[5]_i_26_n_0 ),\n .I1(\\init_state_r[4]_i_16_n_0 ),\n .I2(oclk_calib_resume_level_reg_0),\n .I3(\\init_state_r[4]_i_17_n_0 ),\n .I4(\\init_state_r[4]_i_18_n_0 ),\n .I5(\\init_state_r[4]_i_19_n_0 ),\n .O(\\init_state_r[4]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hA2AAA200AAAAAAAA)) \n \\init_state_r[4]_i_8 \n (.I0(\\wrcal_reads[7]_i_5_n_0 ),\n .I1(\\init_state_r[4]_i_20_n_0 ),\n .I2(wrcal_sanity_chk_done_reg_0),\n .I3(cnt_cmd_done_r),\n .I4(Q[3]),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .O(\\init_state_r[4]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'h57DF55555555FFFF)) \n \\init_state_r[4]_i_9 \n (.I0(Q[3]),\n .I1(Q[1]),\n .I2(\\init_state_r[4]_i_21_n_0 ),\n .I3(Q[0]),\n .I4(\\init_state_r_reg_n_0_[3] ),\n .I5(Q[2]),\n .O(\\init_state_r[4]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF1110)) \n \\init_state_r[5]_i_1 \n (.I0(\\init_state_r[5]_i_2_n_0 ),\n .I1(\\init_state_r[5]_i_3_n_0 ),\n .I2(\\init_state_r[5]_i_4_n_0 ),\n .I3(\\init_state_r[5]_i_5_n_0 ),\n .I4(\\init_state_r[5]_i_6_n_0 ),\n .I5(\\init_state_r[5]_i_7_n_0 ),\n .O(\\init_state_r[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF0000AA10)) \n \\init_state_r[5]_i_10 \n (.I0(Q[1]),\n .I1(cnt_cmd_done_r),\n .I2(Q[4]),\n .I3(Q[0]),\n .I4(\\init_state_r[4]_i_5_n_0 ),\n .I5(\\init_state_r[5]_i_31_n_0 ),\n .O(\\init_state_r[5]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'h00000000002A0000)) \n \\init_state_r[5]_i_11 \n (.I0(\\init_state_r[1]_i_10_n_0 ),\n .I1(cnt_cmd_done_r),\n .I2(Q[1]),\n .I3(oclk_calib_resume_level_reg_0),\n .I4(Q[4]),\n .I5(\\init_state_r[1]_i_11_n_0 ),\n .O(\\init_state_r[5]_i_11_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair486\" *) \n LUT5 #(\n .INIT(32'h02220202)) \n \\init_state_r[5]_i_12 \n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(\\init_state_r[5]_i_32_n_0 ),\n .I3(complex_sample_cnt_inc_i_2_n_0),\n .I4(rdlvl_stg1_done_r1),\n .O(\\init_state_r[5]_i_12_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair503\" *) \n LUT5 #(\n .INIT(32'h00000010)) \n \\init_state_r[5]_i_13 \n (.I0(wr_victim_inc_i_3_n_0),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[5] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[0] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[1] ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[2] ),\n .O(\\init_state_r[5]_i_13_n_0 ));\n LUT6 #(\n .INIT(64'h7500FFFF75007500)) \n \\init_state_r[5]_i_14 \n (.I0(pi_calib_done),\n .I1(wrcal_done_reg_10),\n .I2(dqs_found_done_r_reg),\n .I3(\\init_state_r[5]_i_33_n_0 ),\n .I4(prbs_rdlvl_start_i_2_n_0),\n .I5(reset_rd_addr_r1),\n .O(\\init_state_r[5]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'h00000000000FCDCD)) \n \\init_state_r[5]_i_15 \n (.I0(cnt_txpr_done_r),\n .I1(\\init_state_r[5]_i_34_n_0 ),\n .I2(\\init_state_r[5]_i_16_n_0 ),\n .I3(cnt_cmd_done_r),\n .I4(Q[1]),\n .I5(oclk_calib_resume_level_reg_0),\n .O(\\init_state_r[5]_i_15_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair527\" *) \n LUT2 #(\n .INIT(4'h7)) \n \\init_state_r[5]_i_16 \n (.I0(Q[4]),\n .I1(Q[0]),\n .O(\\init_state_r[5]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'h0000000040700000)) \n \\init_state_r[5]_i_17 \n (.I0(wrlvl_rank_done_r7),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(cnt_dllk_zqinit_done_r),\n .I4(\\init_state_r[5]_i_35_n_0 ),\n .I5(\\init_state_r_reg_n_0_[3] ),\n .O(\\init_state_r[5]_i_17_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\init_state_r[5]_i_18 \n (.I0(Q[0]),\n .I1(complex_pi_incdec_done),\n .O(\\init_state_r[5]_i_18_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair524\" *) \n LUT5 #(\n .INIT(32'h00E00000)) \n \\init_state_r[5]_i_19 \n (.I0(\\init_state_r[5]_i_36_n_0 ),\n .I1(Q[0]),\n .I2(Q[5]),\n .I3(Q[2]),\n .I4(Q[1]),\n .O(\\init_state_r[5]_i_19_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\init_state_r[5]_i_2 \n (.I0(Q[5]),\n .I1(Q[4]),\n .O(\\init_state_r[5]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hBFBF15B7FFFFFFFF)) \n \\init_state_r[5]_i_20 \n (.I0(Q[0]),\n .I1(Q[4]),\n .I2(write_request_r_reg),\n .I3(\\init_state_r[6]_i_21_n_0 ),\n .I4(prech_pending_r_reg_0),\n .I5(\\init_state_r[5]_i_38_n_0 ),\n .O(\\init_state_r[5]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'h444F44444F4F4F4F)) \n \\init_state_r[5]_i_21 \n (.I0(\\init_state_r[5]_i_39_n_0 ),\n .I1(\\init_state_r[5]_i_40_n_0 ),\n .I2(\\init_state_r[5]_i_41_n_0 ),\n .I3(prbs_gen_oclk_clk_en_i_8_n_0),\n .I4(Q[4]),\n .I5(\\init_state_r[5]_i_42_n_0 ),\n .O(\\init_state_r[5]_i_21_n_0 ));\n LUT6 #(\n .INIT(64'h0808080888888808)) \n \\init_state_r[5]_i_22 \n (.I0(\\init_state_r[5]_i_43_n_0 ),\n .I1(\\wrcal_reads[7]_i_5_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .I3(Q[4]),\n .I4(prbs_gen_oclk_clk_en_i_8_n_0),\n .I5(prbs_rdlvl_done_pulse0),\n .O(\\init_state_r[5]_i_22_n_0 ));\n LUT6 #(\n .INIT(64'h4F4F4F4FFF4F4F4F)) \n \\init_state_r[5]_i_23 \n (.I0(\\init_state_r[5]_i_44_n_0 ),\n .I1(\\init_state_r[5]_i_45_n_0 ),\n .I2(Q[3]),\n .I3(\\init_state_r_reg[5]_0 ),\n .I4(Q[4]),\n .I5(oclk_calib_resume_r_reg_0),\n .O(\\init_state_r[5]_i_23_n_0 ));\n LUT6 #(\n .INIT(64'h44455555FFFFFFFF)) \n \\init_state_r[5]_i_24 \n (.I0(\\init_state_r[5]_i_48_n_0 ),\n .I1(\\init_state_r[5]_i_49_n_0 ),\n .I2(Q[4]),\n .I3(wrcal_resume_r),\n .I4(\\wrcal_reads[7]_i_6_n_0 ),\n .I5(\\wrcal_reads[7]_i_5_n_0 ),\n .O(\\init_state_r[5]_i_24_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFEEEEEFEE)) \n \\init_state_r[5]_i_25 \n (.I0(\\init_state_r[5]_i_50_n_0 ),\n .I1(Q[3]),\n .I2(\\init_state_r[5]_i_51_n_0 ),\n .I3(Q[4]),\n .I4(oclk_calib_resume_level_reg_0),\n .I5(\\init_state_r[5]_i_52_n_0 ),\n .O(\\init_state_r[5]_i_25_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair550\" *) \n LUT2 #(\n .INIT(4'hB)) \n \\init_state_r[5]_i_26 \n (.I0(Q[5]),\n .I1(Q[4]),\n .O(\\init_state_r[5]_i_26_n_0 ));\n LUT6 #(\n .INIT(64'h00000000000000D0)) \n \\init_state_r[5]_i_27 \n (.I0(cnt_init_af_done_r),\n .I1(mem_init_done_r),\n .I2(num_refresh_reg__0[3]),\n .I3(num_refresh_reg__0[2]),\n .I4(num_refresh_reg__0[0]),\n .I5(num_refresh_reg__0[1]),\n .O(\\init_state_r[5]_i_27_n_0 ));\n LUT6 #(\n .INIT(64'h44FEFFFF44EEFFFF)) \n \\init_state_r[5]_i_29 \n (.I0(rdlvl_stg1_done_int_reg),\n .I1(wrcal_done_reg_10),\n .I2(prbs_last_byte_done_r),\n .I3(prbs_rdlvl_done_reg_rep),\n .I4(dqs_found_done_r_reg),\n .I5(mem_init_done_r),\n .O(\\init_state_r[5]_i_29_n_0 ));\n LUT6 #(\n .INIT(64'h000000000000D5DD)) \n \\init_state_r[5]_i_3 \n (.I0(\\init_state_r_reg[1]_0 ),\n .I1(\\init_state_r[5]_i_8_n_0 ),\n .I2(cnt_cmd_done_r),\n .I3(\\init_state_r[5]_i_9_n_0 ),\n .I4(\\init_state_r[5]_i_10_n_0 ),\n .I5(\\init_state_r[5]_i_11_n_0 ),\n .O(\\init_state_r[5]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h00010000FFFFFFFF)) \n \\init_state_r[5]_i_31 \n (.I0(cnt_cmd_done_r),\n .I1(\\init_state_r[5]_i_16_n_0 ),\n .I2(Q[1]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[2]),\n .I5(Q[3]),\n .O(\\init_state_r[5]_i_31_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFBFFFFFFFFFF)) \n \\init_state_r[5]_i_32 \n (.I0(\\complex_num_writes_dec[4]_i_5_n_0 ),\n .I1(rdlvl_stg1_done_r1),\n .I2(complex_row0_wr_done),\n .I3(prbs_rdlvl_done_reg_rep),\n .I4(complex_num_writes_dec_reg__0[1]),\n .I5(complex_num_writes_dec_reg__0[0]),\n .O(\\init_state_r[5]_i_32_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair532\" *) \n LUT3 #(\n .INIT(8'h20)) \n \\init_state_r[5]_i_33 \n (.I0(cnt_cmd_done_r),\n .I1(Q[1]),\n .I2(Q[0]),\n .O(\\init_state_r[5]_i_33_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair527\" *) \n LUT5 #(\n .INIT(32'h04444444)) \n \\init_state_r[5]_i_34 \n (.I0(Q[0]),\n .I1(Q[4]),\n .I2(\\mcGo_r_reg[15] ),\n .I3(cnt_pwron_cke_done_r),\n .I4(ck_addr_cmd_delay_done),\n .O(\\init_state_r[5]_i_34_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair522\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\init_state_r[5]_i_35 \n (.I0(Q[4]),\n .I1(Q[2]),\n .O(\\init_state_r[5]_i_35_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair538\" *) \n LUT4 #(\n .INIT(16'h7FFF)) \n \\init_state_r[5]_i_36 \n (.I0(ocal_act_wait_cnt_reg__0[2]),\n .I1(ocal_act_wait_cnt_reg__0[1]),\n .I2(ocal_act_wait_cnt_reg__0[0]),\n .I3(ocal_act_wait_cnt_reg__0[3]),\n .O(\\init_state_r[5]_i_36_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair577\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\init_state_r[5]_i_38 \n (.I0(Q[2]),\n .I1(Q[1]),\n .O(\\init_state_r[5]_i_38_n_0 ));\n LUT6 #(\n .INIT(64'h0000444FFFFFFFFF)) \n \\init_state_r[5]_i_39 \n (.I0(prbs_rdlvl_done_r1),\n .I1(prbs_rdlvl_done_reg),\n .I2(prbs_gen_oclk_clk_en_i_8_n_0),\n .I3(Q[4]),\n .I4(complex_oclkdelay_calib_start_int_reg_0),\n .I5(\\init_state_r[5]_i_53_n_0 ),\n .O(\\init_state_r[5]_i_39_n_0 ));\n LUT6 #(\n .INIT(64'h5555555544444544)) \n \\init_state_r[5]_i_4 \n (.I0(\\init_state_r[4]_i_5_n_0 ),\n .I1(\\init_state_r[5]_i_12_n_0 ),\n .I2(complex_oclkdelay_calib_start_int_reg_0),\n .I3(Q[4]),\n .I4(\\init_state_r[5]_i_13_n_0 ),\n .I5(\\init_state_r[5]_i_14_n_0 ),\n .O(\\init_state_r[5]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFE2)) \n \\init_state_r[5]_i_40 \n (.I0(\\init_state_r[0]_i_27_n_0 ),\n .I1(Q[0]),\n .I2(prbs_gen_oclk_clk_en_i_8_n_0),\n .I3(Q[4]),\n .I4(Q[1]),\n .I5(\\init_state_r[5]_i_13_n_0 ),\n .O(\\init_state_r[5]_i_40_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFEEEEAAEA)) \n \\init_state_r[5]_i_41 \n (.I0(\\init_state_r[4]_i_5_n_0 ),\n .I1(Q[0]),\n .I2(prbs_rdlvl_done_reg),\n .I3(complex_oclkdelay_calib_done_r1),\n .I4(prech_pending_r_reg_0),\n .I5(Q[1]),\n .O(\\init_state_r[5]_i_41_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair488\" *) \n LUT2 #(\n .INIT(4'hB)) \n \\init_state_r[5]_i_42 \n (.I0(complex_sample_cnt_inc_i_2_n_0),\n .I1(Q[0]),\n .O(\\init_state_r[5]_i_42_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAABFBBAAAA)) \n \\init_state_r[5]_i_43 \n (.I0(\\init_state_r[6]_i_22_n_0 ),\n .I1(\\init_state_r[5]_i_54_n_0 ),\n .I2(prbs_gen_oclk_clk_en_i_8_n_0),\n .I3(Q[4]),\n .I4(Q[0]),\n .I5(prech_pending_r_reg_0),\n .O(\\init_state_r[5]_i_43_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF03000101)) \n \\init_state_r[5]_i_44 \n (.I0(Q[4]),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(oclkdelay_int_ref_req_reg_0),\n .I4(cnt_cmd_done_r),\n .I5(oclk_calib_resume_level_reg_0),\n .O(\\init_state_r[5]_i_44_n_0 ));\n LUT6 #(\n .INIT(64'h3373F373FFFFFFFF)) \n \\init_state_r[5]_i_45 \n (.I0(oclkdelay_center_calib_start_r_reg_0),\n .I1(\\init_state_r[5]_i_56_n_0 ),\n .I2(Q[4]),\n .I3(Q[0]),\n .I4(cnt_cmd_done_r),\n .I5(Q[1]),\n .O(\\init_state_r[5]_i_45_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair536\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\init_state_r[5]_i_46 \n (.I0(Q[0]),\n .I1(Q[2]),\n .I2(Q[1]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .O(\\init_state_r_reg[5]_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFE8E8C8E8)) \n \\init_state_r[5]_i_48 \n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(Q[4]),\n .I3(pi_phase_locked_all_r3),\n .I4(pi_phase_locked_all_r4),\n .I5(\\init_state_r[0]_i_25_n_0 ),\n .O(\\init_state_r[5]_i_48_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair534\" *) \n LUT4 #(\n .INIT(16'h5554)) \n \\init_state_r[5]_i_49 \n (.I0(wrcal_resume_r),\n .I1(wrcal_done_reg_10),\n .I2(prech_pending_r_reg_0),\n .I3(wrlvl_byte_redo),\n .O(\\init_state_r[5]_i_49_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFEEEEEFEE)) \n \\init_state_r[5]_i_5 \n (.I0(\\init_state_r[5]_i_15_n_0 ),\n .I1(Q[3]),\n .I2(\\init_state_r[5]_i_16_n_0 ),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(cnt_cmd_done_r),\n .I5(\\init_state_r[5]_i_17_n_0 ),\n .O(\\init_state_r[5]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h00000000EEEEFEEE)) \n \\init_state_r[5]_i_50 \n (.I0(\\init_state_r[5]_i_57_n_0 ),\n .I1(\\init_state_r[5]_i_58_n_0 ),\n .I2(Q[1]),\n .I3(Q[4]),\n .I4(oclkdelay_calib_done_r_reg_3),\n .I5(\\init_state_r[5]_i_60_n_0 ),\n .O(\\init_state_r[5]_i_50_n_0 ));\n LUT6 #(\n .INIT(64'h0054000000540054)) \n \\init_state_r[5]_i_51 \n (.I0(Q[1]),\n .I1(wrcal_done_reg_10),\n .I2(prech_pending_r_reg_0),\n .I3(Q[0]),\n .I4(wrcal_prech_req),\n .I5(cnt_cmd_done_r),\n .O(\\init_state_r[5]_i_51_n_0 ));\n LUT6 #(\n .INIT(64'h00000000F2F200F2)) \n \\init_state_r[5]_i_52 \n (.I0(\\init_state_r[5]_i_61_n_0 ),\n .I1(wrcal_prech_req),\n .I2(\\init_state_r[1]_i_20_n_0 ),\n .I3(Q[1]),\n .I4(\\init_state_r[5]_i_62_n_0 ),\n .I5(oclk_calib_resume_level_reg_0),\n .O(\\init_state_r[5]_i_52_n_0 ));\n LUT6 #(\n .INIT(64'h4044404040444044)) \n \\init_state_r[5]_i_53 \n (.I0(Q[2]),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .I2(Q[1]),\n .I3(prech_pending_r_reg_0),\n .I4(prbs_rdlvl_done_r1),\n .I5(prbs_rdlvl_done_reg),\n .O(\\init_state_r[5]_i_53_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF00BFFFFFFFFF)) \n \\init_state_r[5]_i_54 \n (.I0(complex_row1_wr_done),\n .I1(complex_ocal_num_samples_done_r),\n .I2(complex_oclkdelay_calib_start_int),\n .I3(\\one_rank.stg1_wr_done_reg_0 ),\n .I4(oclkdelay_center_calib_start_r_reg),\n .I5(prbs_gen_oclk_clk_en_i_8_n_0),\n .O(\\init_state_r[5]_i_54_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair537\" *) \n LUT4 #(\n .INIT(16'hEEEF)) \n \\init_state_r[5]_i_56 \n (.I0(oclkdelay_int_ref_req_reg_0),\n .I1(Q[0]),\n .I2(complex_oclk_calib_resume),\n .I3(oclk_calib_resume_level),\n .O(\\init_state_r[5]_i_56_n_0 ));\n LUT6 #(\n .INIT(64'h0004000000000000)) \n \\init_state_r[5]_i_57 \n (.I0(oclk_wr_cnt_reg__0[2]),\n .I1(oclk_wr_cnt_reg__0[0]),\n .I2(oclk_wr_cnt_reg__0[1]),\n .I3(oclk_wr_cnt_reg__0[3]),\n .I4(Q[1]),\n .I5(Q[0]),\n .O(\\init_state_r[5]_i_57_n_0 ));\n LUT6 #(\n .INIT(64'h5D5D5D5D5D5D7D5D)) \n \\init_state_r[5]_i_58 \n (.I0(Q[2]),\n .I1(Q[0]),\n .I2(Q[1]),\n .I3(cnt_cmd_done_r),\n .I4(lim2init_prech_req),\n .I5(ocd_prech_req),\n .O(\\init_state_r[5]_i_58_n_0 ));\n LUT6 #(\n .INIT(64'hFFCF8F8FCCCC8888)) \n \\init_state_r[5]_i_6 \n (.I0(\\init_state_r[5]_i_18_n_0 ),\n .I1(\\init_state_r[5]_i_19_n_0 ),\n .I2(\\init_state_r[5]_i_20_n_0 ),\n .I3(Q[2]),\n .I4(Q[4]),\n .I5(Q[5]),\n .O(\\init_state_r[5]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h000000F1FFFFFFFF)) \n \\init_state_r[5]_i_60 \n (.I0(cnt_cmd_done_r),\n .I1(Q[0]),\n .I2(\\init_state_r_reg[1]_1 ),\n .I3(Q[4]),\n .I4(Q[2]),\n .I5(\\init_state_r_reg_n_0_[3] ),\n .O(\\init_state_r[5]_i_60_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair539\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\init_state_r[5]_i_61 \n (.I0(cnt_cmd_done_r),\n .I1(Q[0]),\n .O(\\init_state_r[5]_i_61_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair579\" *) \n LUT3 #(\n .INIT(8'hCA)) \n \\init_state_r[5]_i_62 \n (.I0(cnt_cmd_done_r),\n .I1(burst_addr_r_reg_0),\n .I2(Q[0]),\n .O(\\init_state_r[5]_i_62_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FEFE00FE)) \n \\init_state_r[5]_i_7 \n (.I0(\\init_state_r[5]_i_21_n_0 ),\n .I1(\\init_state_r[5]_i_22_n_0 ),\n .I2(\\init_state_r[5]_i_23_n_0 ),\n .I3(\\init_state_r[5]_i_24_n_0 ),\n .I4(\\init_state_r[5]_i_25_n_0 ),\n .I5(\\init_state_r[5]_i_26_n_0 ),\n .O(\\init_state_r[5]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF5FFFDFDFDFDF)) \n \\init_state_r[5]_i_8 \n (.I0(\\init_state_r[4]_i_11_n_0 ),\n .I1(oclkdelay_calib_done_r_reg_2),\n .I2(\\init_state_r[5]_i_27_n_0 ),\n .I3(wrlvl_byte_redo_reg),\n .I4(\\init_state_r[5]_i_29_n_0 ),\n .I5(mpr_rdlvl_done_r_reg_2),\n .O(\\init_state_r[5]_i_8_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair597\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\init_state_r[5]_i_9 \n (.I0(Q[4]),\n .I1(Q[0]),\n .O(\\init_state_r[5]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF00D00000)) \n \\init_state_r[6]_i_1 \n (.I0(\\init_state_r[6]_i_2_n_0 ),\n .I1(\\init_state_r[6]_i_3_n_0 ),\n .I2(Q[4]),\n .I3(Q[5]),\n .I4(Q[3]),\n .I5(\\init_state_r[6]_i_4_n_0 ),\n .O(\\init_state_r[6]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0100000000000000)) \n \\init_state_r[6]_i_10 \n (.I0(\\init_state_r[4]_i_5_n_0 ),\n .I1(Q[4]),\n .I2(ddr3_lm_done_r_i_2_n_0),\n .I3(\\init_state_r[6]_i_20_n_0 ),\n .I4(cnt_cmd_done_r),\n .I5(rdlvl_stg1_done_r1),\n .O(\\init_state_r[6]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'h0020002000200000)) \n \\init_state_r[6]_i_11 \n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(Q[5]),\n .I3(Q[2]),\n .I4(\\init_state_r[6]_i_21_n_0 ),\n .I5(prech_pending_r_reg_0),\n .O(\\init_state_r[6]_i_11_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair529\" *) \n LUT4 #(\n .INIT(16'hAA08)) \n \\init_state_r[6]_i_12 \n (.I0(Q[0]),\n .I1(prbs_rdlvl_done_reg_rep),\n .I2(complex_oclkdelay_calib_done_r1),\n .I3(prech_pending_r_reg_0),\n .O(\\init_state_r[6]_i_12_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair550\" *) \n LUT4 #(\n .INIT(16'hFF4F)) \n \\init_state_r[6]_i_13 \n (.I0(prbs_rdlvl_done_r1),\n .I1(prbs_rdlvl_done_reg),\n .I2(Q[5]),\n .I3(prbs_gen_oclk_clk_en_i_8_n_0),\n .O(\\init_state_r[6]_i_13_n_0 ));\n LUT4 #(\n .INIT(16'hFFAE)) \n \\init_state_r[6]_i_14 \n (.I0(\\init_state_r[5]_i_13_n_0 ),\n .I1(prbs_rdlvl_done_reg),\n .I2(prbs_rdlvl_done_r1),\n .I3(prech_pending_r_reg_0),\n .O(\\init_state_r[6]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'h8000FFFF80000000)) \n \\init_state_r[6]_i_15 \n (.I0(complex_wait_cnt_reg__0[0]),\n .I1(complex_wait_cnt_reg__0[1]),\n .I2(complex_wait_cnt_reg__0[2]),\n .I3(complex_wait_cnt_reg__0[3]),\n .I4(Q[0]),\n .I5(\\init_state_r[0]_i_27_n_0 ),\n .O(\\init_state_r[6]_i_15_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair537\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\init_state_r[6]_i_16 \n (.I0(oclk_calib_resume_level),\n .I1(complex_oclk_calib_resume),\n .O(\\init_state_r[6]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFD)) \n \\init_state_r[6]_i_17 \n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(wrlvl_final_mux),\n .I3(oclkdelay_int_ref_req_reg_0),\n .I4(prech_pending_r_reg_0),\n .I5(oclkdelay_calib_done_r_reg_2),\n .O(\\init_state_r[6]_i_17_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair509\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\init_state_r[6]_i_18 \n (.I0(Q[0]),\n .I1(Q[1]),\n .O(\\init_state_r[6]_i_18_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFABFB0000)) \n \\init_state_r[6]_i_19 \n (.I0(prech_pending_r_reg_0),\n .I1(Q[5]),\n .I2(prbs_gen_oclk_clk_en_i_8_n_0),\n .I3(oclkdelay_center_calib_start_r_reg),\n .I4(Q[0]),\n .I5(\\init_state_r[6]_i_22_n_0 ),\n .O(\\init_state_r[6]_i_19_n_0 ));\n LUT6 #(\n .INIT(64'hFBFBFBFAFBFBFBFB)) \n \\init_state_r[6]_i_2 \n (.I0(\\init_state_r[6]_i_5_n_0 ),\n .I1(complex_oclkdelay_calib_start_int_reg_0),\n .I2(\\init_state_r[4]_i_5_n_0 ),\n .I3(prbs_rdlvl_done_reg_rep_0),\n .I4(complex_oclk_calib_resume),\n .I5(Q[5]),\n .O(\\init_state_r[6]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair544\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\init_state_r[6]_i_20 \n (.I0(Q[0]),\n .I1(reset_rd_addr_r1),\n .O(\\init_state_r[6]_i_20_n_0 ));\n LUT4 #(\n .INIT(16'h0004)) \n \\init_state_r[6]_i_21 \n (.I0(mask_lim_done),\n .I1(done_r_reg),\n .I2(complex_mask_lim_done),\n .I3(oclkdelay_center_calib_start_r_reg),\n .O(\\init_state_r[6]_i_21_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair509\" *) \n LUT5 #(\n .INIT(32'h37773737)) \n \\init_state_r[6]_i_22 \n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(prbs_rdlvl_start_r_reg),\n .I3(num_samples_done_r),\n .I4(complex_init_pi_dec_done),\n .O(\\init_state_r[6]_i_22_n_0 ));\n LUT6 #(\n .INIT(64'h0503FFFF05F3FFFF)) \n \\init_state_r[6]_i_3 \n (.I0(\\init_state_r[6]_i_7_n_0 ),\n .I1(\\init_state_r[6]_i_8_n_0 ),\n .I2(Q[2]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[3]),\n .I5(\\init_state_r[6]_i_9_n_0 ),\n .O(\\init_state_r[6]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FAFACAFA)) \n \\init_state_r[6]_i_4 \n (.I0(\\init_state_r[6]_i_10_n_0 ),\n .I1(Q[2]),\n .I2(Q[5]),\n .I3(complex_pi_incdec_done),\n .I4(prbs_rdlvl_start_i_2_n_0),\n .I5(\\init_state_r[6]_i_11_n_0 ),\n .O(\\init_state_r[6]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h5555555545455545)) \n \\init_state_r[6]_i_5 \n (.I0(Q[1]),\n .I1(prbs_gen_oclk_clk_en_i_8_n_0),\n .I2(Q[5]),\n .I3(Q[0]),\n .I4(complex_sample_cnt_inc_i_2_n_0),\n .I5(\\init_state_r[6]_i_12_n_0 ),\n .O(\\init_state_r[6]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hEEEEFFFFEEEEF0FF)) \n \\init_state_r[6]_i_7 \n (.I0(\\init_state_r[6]_i_13_n_0 ),\n .I1(Q[0]),\n .I2(\\init_state_r[6]_i_14_n_0 ),\n .I3(Q[5]),\n .I4(Q[1]),\n .I5(\\init_state_r[6]_i_15_n_0 ),\n .O(\\init_state_r[6]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hFAFAFBFBFA00FBFB)) \n \\init_state_r[6]_i_8 \n (.I0(\\init_state_r[6]_i_16_n_0 ),\n .I1(oclkdelay_center_calib_start_r_reg),\n .I2(\\init_state_r[6]_i_17_n_0 ),\n .I3(\\init_state_r[6]_i_18_n_0 ),\n .I4(Q[5]),\n .I5(cnt_cmd_done_r),\n .O(\\init_state_r[6]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'hAAAA20AAAAAAAAAA)) \n \\init_state_r[6]_i_9 \n (.I0(\\init_state_r[6]_i_19_n_0 ),\n .I1(prbs_rdlvl_done_r1),\n .I2(prbs_rdlvl_done_reg),\n .I3(Q[5]),\n .I4(prbs_gen_oclk_clk_en_i_8_n_0),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .O(\\init_state_r[6]_i_9_n_0 ));\n FDRE \\init_state_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\init_state_r[0]_i_1_n_0 ),\n .Q(Q[0]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE \\init_state_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\init_state_r[1]_i_1_n_0 ),\n .Q(Q[1]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE \\init_state_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\init_state_r[2]_i_1_n_0 ),\n .Q(Q[2]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE \\init_state_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\init_state_r[3]_i_1_n_0 ),\n .Q(\\init_state_r_reg_n_0_[3] ),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE \\init_state_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\init_state_r[4]_i_1_n_0 ),\n .Q(Q[3]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE \\init_state_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\init_state_r[5]_i_1_n_0 ),\n .Q(Q[4]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE \\init_state_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\init_state_r[6]_i_1_n_0 ),\n .Q(Q[5]),\n .R(rstdiv0_sync_r1_reg_rep__12));\n (* SOFT_HLUTNM = \"soft_lutpair608\" *) \n LUT2 #(\n .INIT(4'h2)) \n lim_start_r_i_3\n (.I0(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .I1(oclkdelay_calib_done_r_reg_2),\n .O(lim_start_r_reg));\n LUT4 #(\n .INIT(16'h000E)) \n mask_lim_done_i_1\n (.I0(mask_lim_done),\n .I1(prech_pending_r),\n .I2(prech_done_r3),\n .I3(rstdiv0_sync_r1_reg_rep__25),\n .O(mask_lim_done_i_1_n_0));\n FDRE mask_lim_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mask_lim_done_i_1_n_0),\n .Q(mask_lim_done),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hFFFF4000)) \n mem_init_done_r_i_1\n (.I0(cnt_dllk_zqinit_done_r),\n .I1(mem_init_done_r_reg_0[1]),\n .I2(mem_init_done_r_reg_1),\n .I3(mem_init_done_r_reg_0[0]),\n .I4(mem_init_done_r),\n .O(mem_init_done_r_i_1_n_0));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n mem_init_done_r_i_2\n (.I0(cnt_dllk_zqinit_r_reg__0[5]),\n .I1(cnt_dllk_zqinit_r_reg__0[3]),\n .I2(cnt_dllk_zqinit_r_reg__0[1]),\n .I3(cnt_dllk_zqinit_r_reg__0[0]),\n .I4(cnt_dllk_zqinit_r_reg__0[2]),\n .I5(cnt_dllk_zqinit_r_reg__0[4]),\n .O(mem_init_done_r_reg_1));\n FDRE mem_init_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mem_init_done_r_i_1_n_0),\n .Q(mem_init_done_r),\n .R(rstdiv0_sync_r1_reg_rep__12));\n LUT3 #(\n .INIT(8'hB8)) \n mem_reg_0_15_0_5_i_1\n (.I0(mc_cas_n),\n .I1(init_calib_complete_reg_rep__14),\n .I2(phy_cs_n),\n .O(\\rd_ptr_timing_reg[0]_3 [0]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_0_5_i_2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [63]),\n .I1(phy_wrdata[63]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_41 [1]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_0_5_i_3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [31]),\n .I1(phy_wrdata[31]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_41 [0]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_0_5_i_4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [127]),\n .I1(phy_wrdata[127]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_41 [3]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_0_5_i_5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [95]),\n .I1(phy_wrdata[95]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_41 [2]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_0_5_i_6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [191]),\n .I1(phy_wrdata[191]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_41 [5]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_0_5_i_7\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [159]),\n .I1(phy_wrdata[159]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_41 [4]));\n LUT3 #(\n .INIT(8'hB8)) \n mem_reg_0_15_12_17_i_1\n (.I0(mc_cas_n),\n .I1(init_calib_complete_reg_rep__14),\n .I2(phy_cas_n),\n .O(\\rd_ptr_timing_reg[0] [0]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_1__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [16]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(phy_dout[5]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_1__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [167]),\n .I1(phy_wrdata[191]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_38 [5]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_1__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [175]),\n .I1(phy_wrdata[191]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_39 [5]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_1__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [183]),\n .I1(phy_wrdata[191]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_40 [5]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_1__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [190]),\n .I1(phy_wrdata[190]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_41 [13]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_2\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [6]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),\n .I2(init_calib_complete_reg_rep__14),\n .O(phy_dout[4]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_2__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [135]),\n .I1(phy_wrdata[159]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_38 [4]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_2__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [143]),\n .I1(phy_wrdata[159]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_39 [4]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_2__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [151]),\n .I1(phy_wrdata[159]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_40 [4]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_2__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [158]),\n .I1(phy_wrdata[158]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_41 [12]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [231]),\n .I1(phy_wrdata[255]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_38 [7]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_3__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [239]),\n .I1(phy_wrdata[255]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_39 [7]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_3__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [247]),\n .I1(phy_wrdata[255]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_40 [7]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_3__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [254]),\n .I1(phy_wrdata[254]),\n .I2(init_calib_complete_reg_rep__7),\n .O(\\my_empty_reg[7]_41 [15]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [199]),\n .I1(phy_wrdata[223]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_38 [6]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_4__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [207]),\n .I1(phy_wrdata[223]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_39 [6]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_4__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [215]),\n .I1(phy_wrdata[223]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_40 [6]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_4__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [222]),\n .I1(phy_wrdata[222]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_41 [14]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [38]),\n .I1(phy_wrdata[62]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_38 [9]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_5__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [46]),\n .I1(phy_wrdata[62]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_39 [9]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_5__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [54]),\n .I1(phy_wrdata[62]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_40 [9]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_5__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [61]),\n .I1(phy_wrdata[61]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_41 [17]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [6]),\n .I1(phy_wrdata[30]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_38 [8]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_6__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [14]),\n .I1(phy_wrdata[30]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_39 [8]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_6__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [22]),\n .I1(phy_wrdata[30]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_40 [8]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_12_17_i_6__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [29]),\n .I1(phy_wrdata[29]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_41 [16]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [102]),\n .I1(phy_wrdata[126]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_38 [11]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_1__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [110]),\n .I1(phy_wrdata[126]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_39 [11]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_1__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [118]),\n .I1(phy_wrdata[126]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_40 [11]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_1__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [125]),\n .I1(phy_wrdata[125]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_41 [19]));\n LUT2 #(\n .INIT(4'hE)) \n mem_reg_0_15_18_23_i_1__3\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),\n .I1(init_calib_complete_reg_rep__13),\n .O(phy_dout[7]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_2\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [27]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(phy_dout[6]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_2__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [70]),\n .I1(phy_wrdata[94]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_38 [10]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_2__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [78]),\n .I1(phy_wrdata[94]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_39 [10]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_2__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [86]),\n .I1(phy_wrdata[94]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_40 [10]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_2__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [93]),\n .I1(phy_wrdata[93]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_41 [18]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [166]),\n .I1(phy_wrdata[190]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_38 [13]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_3__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [174]),\n .I1(phy_wrdata[190]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_39 [13]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_3__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [182]),\n .I1(phy_wrdata[190]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_40 [13]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_3__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [189]),\n .I1(phy_wrdata[189]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_41 [21]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [134]),\n .I1(phy_wrdata[158]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_38 [12]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_4__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [142]),\n .I1(phy_wrdata[158]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_39 [12]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_4__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [150]),\n .I1(phy_wrdata[158]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_40 [12]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_4__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [157]),\n .I1(phy_wrdata[157]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_41 [20]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [230]),\n .I1(phy_wrdata[254]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_38 [15]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_5__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [238]),\n .I1(phy_wrdata[254]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_39 [15]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_5__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [246]),\n .I1(phy_wrdata[254]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_40 [15]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_5__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [253]),\n .I1(phy_wrdata[253]),\n .I2(init_calib_complete_reg_rep__7),\n .O(\\my_empty_reg[7]_41 [23]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [198]),\n .I1(phy_wrdata[222]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_38 [14]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_6__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [206]),\n .I1(phy_wrdata[222]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_39 [14]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_6__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [214]),\n .I1(phy_wrdata[222]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_40 [14]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_18_23_i_6__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [221]),\n .I1(phy_wrdata[221]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_41 [22]));\n LUT3 #(\n .INIT(8'hB8)) \n mem_reg_0_15_24_29_i_1\n (.I0(mc_ras_n),\n .I1(init_calib_complete_reg_rep__14),\n .I2(phy_ras_n),\n .O(\\rd_ptr_timing_reg[0] [1]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_1__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [17]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(phy_dout[9]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_1__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [37]),\n .I1(phy_wrdata[61]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_38 [17]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_1__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [45]),\n .I1(phy_wrdata[61]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_39 [17]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_1__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [53]),\n .I1(phy_wrdata[61]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_40 [17]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_1__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [60]),\n .I1(phy_wrdata[60]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_41 [25]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_2\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [7]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),\n .I2(init_calib_complete_reg_rep__14),\n .O(phy_dout[8]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_2__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [5]),\n .I1(phy_wrdata[29]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_38 [16]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_2__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [13]),\n .I1(phy_wrdata[29]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_39 [16]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_2__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [21]),\n .I1(phy_wrdata[29]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_40 [16]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_2__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [28]),\n .I1(phy_wrdata[28]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_41 [24]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [101]),\n .I1(phy_wrdata[125]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_38 [19]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_3__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [109]),\n .I1(phy_wrdata[125]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_39 [19]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_3__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [117]),\n .I1(phy_wrdata[125]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_40 [19]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_3__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [124]),\n .I1(phy_wrdata[124]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_41 [27]));\n LUT2 #(\n .INIT(4'hE)) \n mem_reg_0_15_24_29_i_3__3\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),\n .I1(init_calib_complete_reg_rep__13),\n .O(phy_dout[11]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_4\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [28]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(phy_dout[10]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_4__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [69]),\n .I1(phy_wrdata[93]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_38 [18]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_4__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [77]),\n .I1(phy_wrdata[93]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_39 [18]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_4__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [85]),\n .I1(phy_wrdata[93]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_40 [18]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_4__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [92]),\n .I1(phy_wrdata[92]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_41 [26]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [165]),\n .I1(phy_wrdata[189]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_38 [21]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_5__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [173]),\n .I1(phy_wrdata[189]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_39 [21]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_5__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [181]),\n .I1(phy_wrdata[189]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_40 [21]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_5__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [188]),\n .I1(phy_wrdata[188]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_41 [29]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [133]),\n .I1(phy_wrdata[157]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_38 [20]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_6__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [141]),\n .I1(phy_wrdata[157]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_39 [20]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_6__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [149]),\n .I1(phy_wrdata[157]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_40 [20]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_24_29_i_6__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [156]),\n .I1(phy_wrdata[156]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_41 [28]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_1\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [18]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(phy_dout[13]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_1__0\n (.I0(\\cmd_pipe_plus.mc_bank_reg[8] [3]),\n .I1(phy_bank[9]),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [3]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_1__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [229]),\n .I1(phy_wrdata[253]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_38 [23]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_1__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [237]),\n .I1(phy_wrdata[253]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_39 [23]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_1__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [245]),\n .I1(phy_wrdata[253]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_40 [23]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_1__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [252]),\n .I1(phy_wrdata[252]),\n .I2(init_calib_complete_reg_rep__7),\n .O(\\my_empty_reg[7]_41 [31]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_2\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [8]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),\n .I2(init_calib_complete_reg_rep__14),\n .O(phy_dout[12]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_2__0\n (.I0(\\cmd_pipe_plus.mc_bank_reg[8] [0]),\n .I1(phy_bank[9]),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [2]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_2__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [197]),\n .I1(phy_wrdata[221]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_38 [22]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_2__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [205]),\n .I1(phy_wrdata[221]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_39 [22]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_2__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [213]),\n .I1(phy_wrdata[221]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_40 [22]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_2__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [220]),\n .I1(phy_wrdata[220]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_41 [30]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [36]),\n .I1(phy_wrdata[60]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_38 [25]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_3__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [44]),\n .I1(phy_wrdata[60]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_39 [25]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_3__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [52]),\n .I1(phy_wrdata[60]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_40 [25]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_3__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [59]),\n .I1(phy_wrdata[59]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_41 [33]));\n LUT2 #(\n .INIT(4'hE)) \n mem_reg_0_15_30_35_i_3__3\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),\n .I1(init_calib_complete_reg_rep__13),\n .O(phy_dout[15]));\n LUT2 #(\n .INIT(4'hE)) \n mem_reg_0_15_30_35_i_3__4\n (.I0(phy_bank[9]),\n .I1(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [5]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_4\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [29]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(phy_dout[14]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_4__0\n (.I0(\\cmd_pipe_plus.mc_bank_reg[8] [6]),\n .I1(phy_bank[9]),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [4]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_4__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [4]),\n .I1(phy_wrdata[28]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_38 [24]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_4__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [12]),\n .I1(phy_wrdata[28]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_39 [24]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_4__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [20]),\n .I1(phy_wrdata[28]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_40 [24]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_4__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [27]),\n .I1(phy_wrdata[27]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_41 [32]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [100]),\n .I1(phy_wrdata[124]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_38 [27]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_5__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [108]),\n .I1(phy_wrdata[124]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_39 [27]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_5__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [116]),\n .I1(phy_wrdata[124]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_40 [27]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_5__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [123]),\n .I1(phy_wrdata[123]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_41 [35]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [68]),\n .I1(phy_wrdata[92]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_38 [26]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_6__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [76]),\n .I1(phy_wrdata[92]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_39 [26]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_6__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [84]),\n .I1(phy_wrdata[92]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_40 [26]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_30_35_i_6__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [91]),\n .I1(phy_wrdata[91]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_41 [34]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_1\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [14]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [7]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_1__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [19]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(phy_dout[17]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_1__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [164]),\n .I1(phy_wrdata[188]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_38 [29]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_1__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [172]),\n .I1(phy_wrdata[188]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_39 [29]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_1__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [180]),\n .I1(phy_wrdata[188]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_40 [29]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_1__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [187]),\n .I1(phy_wrdata[187]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_41 [37]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_2\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [4]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .I2(init_calib_complete_reg_rep__14),\n .O(\\rd_ptr_timing_reg[0] [6]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_2__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [9]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),\n .I2(init_calib_complete_reg_rep__14),\n .O(phy_dout[16]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_2__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [132]),\n .I1(phy_wrdata[156]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_38 [28]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_2__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [140]),\n .I1(phy_wrdata[156]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_39 [28]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_2__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [148]),\n .I1(phy_wrdata[156]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_40 [28]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_2__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [155]),\n .I1(phy_wrdata[155]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_41 [36]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [228]),\n .I1(phy_wrdata[252]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_38 [31]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_3__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [236]),\n .I1(phy_wrdata[252]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_39 [31]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_3__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [244]),\n .I1(phy_wrdata[252]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_40 [31]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_3__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [251]),\n .I1(phy_wrdata[251]),\n .I2(init_calib_complete_reg_rep__7),\n .O(\\my_empty_reg[7]_41 [39]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [196]),\n .I1(phy_wrdata[220]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_38 [30]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_4__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [204]),\n .I1(phy_wrdata[220]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_39 [30]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_4__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [212]),\n .I1(phy_wrdata[220]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_40 [30]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_4__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [219]),\n .I1(phy_wrdata[219]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_41 [38]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [35]),\n .I1(phy_wrdata[59]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_38 [33]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_5__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [43]),\n .I1(phy_wrdata[59]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_39 [33]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_5__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [51]),\n .I1(phy_wrdata[59]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_40 [33]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_5__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [58]),\n .I1(phy_wrdata[58]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_41 [41]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [3]),\n .I1(phy_wrdata[27]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_38 [32]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_6__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [11]),\n .I1(phy_wrdata[27]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_39 [32]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_6__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [19]),\n .I1(phy_wrdata[27]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_40 [32]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_36_41_i_6__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [26]),\n .I1(phy_wrdata[26]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_41 [40]));\n LUT3 #(\n .INIT(8'hB8)) \n mem_reg_0_15_42_47_i_1\n (.I0(mc_odt),\n .I1(init_calib_complete_reg_rep__14),\n .I2(calib_odt),\n .O(\\my_full_reg[3] [0]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_1__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [99]),\n .I1(phy_wrdata[123]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_38 [35]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_1__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [107]),\n .I1(phy_wrdata[123]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_39 [35]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_1__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [115]),\n .I1(phy_wrdata[123]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_40 [35]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_1__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [122]),\n .I1(phy_wrdata[122]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_41 [43]));\n LUT2 #(\n .INIT(4'hE)) \n mem_reg_0_15_42_47_i_1__4\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .I1(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [9]));\n LUT2 #(\n .INIT(4'hE)) \n mem_reg_0_15_42_47_i_1__5\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),\n .I1(init_calib_complete_reg_rep__13),\n .O(phy_dout[19]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_2\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [25]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [8]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_2__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [30]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(phy_dout[18]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_2__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [67]),\n .I1(phy_wrdata[91]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_38 [34]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_2__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [75]),\n .I1(phy_wrdata[91]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_39 [34]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_2__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [83]),\n .I1(phy_wrdata[91]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_40 [34]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_2__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [90]),\n .I1(phy_wrdata[90]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_41 [42]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_3\n (.I0(\\cmd_pipe_plus.mc_bank_reg[8] [5]),\n .I1(phy_bank[11]),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [11]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_3__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [163]),\n .I1(phy_wrdata[187]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_38 [37]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_3__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [171]),\n .I1(phy_wrdata[187]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_39 [37]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_3__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [179]),\n .I1(phy_wrdata[187]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_40 [37]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_3__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [186]),\n .I1(phy_wrdata[186]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_41 [45]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_4\n (.I0(\\cmd_pipe_plus.mc_bank_reg[8] [2]),\n .I1(phy_bank[11]),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [10]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_4__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [131]),\n .I1(phy_wrdata[155]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_38 [36]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_4__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [139]),\n .I1(phy_wrdata[155]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_39 [36]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_4__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [147]),\n .I1(phy_wrdata[155]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_40 [36]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_4__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [154]),\n .I1(phy_wrdata[154]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_41 [44]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [227]),\n .I1(phy_wrdata[251]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_38 [39]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_5__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [235]),\n .I1(phy_wrdata[251]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_39 [39]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_5__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [243]),\n .I1(phy_wrdata[251]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_40 [39]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_5__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [250]),\n .I1(phy_wrdata[250]),\n .I2(init_calib_complete_reg_rep__7),\n .O(\\my_empty_reg[7]_41 [47]));\n LUT2 #(\n .INIT(4'hE)) \n mem_reg_0_15_42_47_i_5__3\n (.I0(phy_bank[11]),\n .I1(init_calib_complete_reg_rep__12),\n .O(\\rd_ptr_timing_reg[0] [13]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_6\n (.I0(\\cmd_pipe_plus.mc_bank_reg[8] [8]),\n .I1(phy_bank[11]),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [12]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_6__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [195]),\n .I1(phy_wrdata[219]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_38 [38]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_6__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [203]),\n .I1(phy_wrdata[219]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_39 [38]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_6__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [211]),\n .I1(phy_wrdata[219]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_40 [38]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_42_47_i_6__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [218]),\n .I1(phy_wrdata[218]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_41 [46]));\n LUT3 #(\n .INIT(8'hB8)) \n mem_reg_0_15_48_53_i_1\n (.I0(mc_cke),\n .I1(init_calib_complete_reg_rep__14),\n .I2(calib_cke),\n .O(\\my_full_reg[3] [1]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_1__0\n (.I0(mc_cas_n),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [15]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_1__1\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [20]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(phy_dout[21]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_1__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [34]),\n .I1(phy_wrdata[58]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_38 [41]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_1__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [42]),\n .I1(phy_wrdata[58]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_39 [41]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_1__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [50]),\n .I1(phy_wrdata[58]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_40 [41]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_1__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [57]),\n .I1(phy_wrdata[57]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_41 [49]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_2\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [1]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),\n .I2(init_calib_complete_reg_rep__14),\n .O(\\rd_ptr_timing_reg[0] [14]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_2__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [10]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),\n .I2(init_calib_complete_reg_rep__14),\n .O(phy_dout[20]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_2__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [2]),\n .I1(phy_wrdata[26]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_38 [40]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_2__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [10]),\n .I1(phy_wrdata[26]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_39 [40]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_2__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [18]),\n .I1(phy_wrdata[26]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_40 [40]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_2__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [25]),\n .I1(phy_wrdata[25]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_41 [48]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [98]),\n .I1(phy_wrdata[122]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_38 [43]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_3__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [106]),\n .I1(phy_wrdata[122]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_39 [43]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_3__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [114]),\n .I1(phy_wrdata[122]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_40 [43]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_3__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [121]),\n .I1(phy_wrdata[121]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_41 [51]));\n LUT2 #(\n .INIT(4'hE)) \n mem_reg_0_15_48_53_i_3__3\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),\n .I1(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [17]));\n LUT2 #(\n .INIT(4'hE)) \n mem_reg_0_15_48_53_i_3__4\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),\n .I1(init_calib_complete_reg_rep__13),\n .O(phy_dout[23]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_4\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [22]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [16]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_4__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [31]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(phy_dout[22]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_4__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [66]),\n .I1(phy_wrdata[90]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_38 [42]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_4__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [74]),\n .I1(phy_wrdata[90]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_39 [42]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_4__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [82]),\n .I1(phy_wrdata[90]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_40 [42]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_4__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [89]),\n .I1(phy_wrdata[89]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_41 [50]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_5\n (.I0(mc_cas_n),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),\n .I2(init_calib_complete_reg_rep__14),\n .O(\\rd_ptr_timing_reg[0] [19]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_5__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [162]),\n .I1(phy_wrdata[186]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_38 [45]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_5__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [170]),\n .I1(phy_wrdata[186]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_39 [45]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_5__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [178]),\n .I1(phy_wrdata[186]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_40 [45]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_5__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [185]),\n .I1(phy_wrdata[185]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_41 [53]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_6\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [0]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),\n .I2(init_calib_complete_reg_rep__14),\n .O(\\rd_ptr_timing_reg[0] [18]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_6__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [130]),\n .I1(phy_wrdata[154]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_38 [44]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_6__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [138]),\n .I1(phy_wrdata[154]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_39 [44]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_6__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [146]),\n .I1(phy_wrdata[154]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_40 [44]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_48_53_i_6__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [153]),\n .I1(phy_wrdata[153]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_41 [52]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_1\n (.I0(mc_cas_n),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(phy_dout[25]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_1__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [226]),\n .I1(phy_wrdata[250]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_38 [47]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_1__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [234]),\n .I1(phy_wrdata[250]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_39 [47]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_1__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [242]),\n .I1(phy_wrdata[250]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_40 [47]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_1__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [249]),\n .I1(phy_wrdata[249]),\n .I2(init_calib_complete_reg_rep__7),\n .O(\\my_empty_reg[7]_41 [55]));\n LUT2 #(\n .INIT(4'hE)) \n mem_reg_0_15_54_59_i_1__4\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),\n .I1(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [21]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_2\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [11]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ),\n .I2(init_calib_complete_reg_rep__14),\n .O(phy_dout[24]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_2__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [21]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [20]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_2__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [194]),\n .I1(phy_wrdata[218]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_38 [46]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_2__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [202]),\n .I1(phy_wrdata[218]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_39 [46]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_2__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [210]),\n .I1(phy_wrdata[218]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_40 [46]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_2__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [217]),\n .I1(phy_wrdata[217]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_41 [54]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_3\n (.I0(mc_cas_n),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [23]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_3__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [33]),\n .I1(phy_wrdata[57]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_38 [49]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_3__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [41]),\n .I1(phy_wrdata[57]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_39 [49]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_3__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [49]),\n .I1(phy_wrdata[57]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_40 [49]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_3__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [56]),\n .I1(phy_wrdata[56]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_41 [57]));\n LUT2 #(\n .INIT(4'hE)) \n mem_reg_0_15_54_59_i_3__4\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ),\n .I1(init_calib_complete_reg_rep__13),\n .O(phy_dout[27]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_4\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [2]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),\n .I2(init_calib_complete_reg_rep__14),\n .O(\\rd_ptr_timing_reg[0] [22]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_4__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [32]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(phy_dout[26]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_4__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [1]),\n .I1(phy_wrdata[25]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_38 [48]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_4__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [9]),\n .I1(phy_wrdata[25]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_39 [48]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_4__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [17]),\n .I1(phy_wrdata[25]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_40 [48]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_4__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [24]),\n .I1(phy_wrdata[24]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_41 [56]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [97]),\n .I1(phy_wrdata[121]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_38 [51]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_5__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [105]),\n .I1(phy_wrdata[121]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_39 [51]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_5__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [113]),\n .I1(phy_wrdata[121]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_40 [51]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_5__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [120]),\n .I1(phy_wrdata[120]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_41 [59]));\n LUT2 #(\n .INIT(4'hE)) \n mem_reg_0_15_54_59_i_5__3\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),\n .I1(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [25]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_6\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [23]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [24]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_6__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [65]),\n .I1(phy_wrdata[89]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_38 [50]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_6__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [73]),\n .I1(phy_wrdata[89]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_39 [50]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_6__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [81]),\n .I1(phy_wrdata[89]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_40 [50]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_54_59_i_6__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [88]),\n .I1(phy_wrdata[88]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_41 [58]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_1\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [13]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [27]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_1__0\n (.I0(mc_ras_n),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(phy_dout[29]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_1__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [161]),\n .I1(phy_wrdata[185]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_38 [53]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_1__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [169]),\n .I1(phy_wrdata[185]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_39 [53]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_1__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [177]),\n .I1(phy_wrdata[185]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_40 [53]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_1__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [184]),\n .I1(phy_wrdata[184]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_41 [61]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_2\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [3]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I2(init_calib_complete_reg_rep__14),\n .O(\\rd_ptr_timing_reg[0] [26]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_2__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [12]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),\n .I2(init_calib_complete_reg_rep__14),\n .O(phy_dout[28]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_2__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [129]),\n .I1(phy_wrdata[153]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_38 [52]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_2__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [137]),\n .I1(phy_wrdata[153]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_39 [52]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_2__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [145]),\n .I1(phy_wrdata[153]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_40 [52]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_2__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [152]),\n .I1(phy_wrdata[152]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_41 [60]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [225]),\n .I1(phy_wrdata[249]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_38 [55]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_3__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [233]),\n .I1(phy_wrdata[249]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_39 [55]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_3__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [241]),\n .I1(phy_wrdata[249]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_40 [55]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_3__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [248]),\n .I1(phy_wrdata[248]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_41 [63]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [193]),\n .I1(phy_wrdata[217]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_38 [54]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_4__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [201]),\n .I1(phy_wrdata[217]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_39 [54]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_4__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [209]),\n .I1(phy_wrdata[217]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_40 [54]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_4__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [216]),\n .I1(phy_wrdata[216]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_41 [62]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [32]),\n .I1(phy_wrdata[56]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_38 [57]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_5__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [40]),\n .I1(phy_wrdata[56]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_39 [57]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_5__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [48]),\n .I1(phy_wrdata[56]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_40 [57]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [0]),\n .I1(phy_wrdata[24]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_38 [56]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_6__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [8]),\n .I1(phy_wrdata[24]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_39 [56]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_60_65_i_6__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [16]),\n .I1(phy_wrdata[24]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_40 [56]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [96]),\n .I1(phy_wrdata[120]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_38 [59]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_1__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [104]),\n .I1(phy_wrdata[120]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_39 [59]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_1__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [112]),\n .I1(phy_wrdata[120]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_40 [59]));\n LUT2 #(\n .INIT(4'hE)) \n mem_reg_0_15_66_71_i_1__2\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I1(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [29]));\n LUT2 #(\n .INIT(4'hE)) \n mem_reg_0_15_66_71_i_1__3\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),\n .I1(init_calib_complete_reg_rep__13),\n .O(phy_dout[31]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_2\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [24]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [28]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_2__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [33]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(phy_dout[30]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_2__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [64]),\n .I1(phy_wrdata[88]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_38 [58]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_2__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [72]),\n .I1(phy_wrdata[88]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_39 [58]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_2__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [80]),\n .I1(phy_wrdata[88]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_40 [58]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [160]),\n .I1(phy_wrdata[184]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_38 [61]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_3__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [168]),\n .I1(phy_wrdata[184]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_39 [61]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_3__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [176]),\n .I1(phy_wrdata[184]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_40 [61]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [128]),\n .I1(phy_wrdata[152]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_38 [60]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_4__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [136]),\n .I1(phy_wrdata[152]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_39 [60]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_4__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [144]),\n .I1(phy_wrdata[152]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_40 [60]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [224]),\n .I1(phy_wrdata[248]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_38 [63]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_5__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [232]),\n .I1(phy_wrdata[248]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_39 [63]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_5__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [240]),\n .I1(phy_wrdata[248]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_40 [63]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [192]),\n .I1(phy_wrdata[216]),\n .I2(init_calib_complete_reg_rep__9),\n .O(\\my_empty_reg[7]_38 [62]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_6__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [200]),\n .I1(phy_wrdata[216]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_39 [62]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_66_71_i_6__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [208]),\n .I1(phy_wrdata[216]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_40 [62]));\n LUT3 #(\n .INIT(8'hB8)) \n mem_reg_0_15_6_11_i_1\n (.I0(mc_we_n),\n .I1(init_calib_complete_reg_rep__14),\n .I2(phy_we_n),\n .O(\\rd_ptr_timing_reg[0]_3 [1]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_1__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [15]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(phy_dout[1]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_1__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [39]),\n .I1(phy_wrdata[63]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_38 [1]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_1__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [47]),\n .I1(phy_wrdata[63]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_39 [1]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_1__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [55]),\n .I1(phy_wrdata[63]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_40 [1]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_1__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [255]),\n .I1(phy_wrdata[255]),\n .I2(init_calib_complete_reg_rep__7),\n .O(\\my_empty_reg[7]_41 [7]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_2\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [5]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),\n .I2(init_calib_complete_reg_rep__14),\n .O(phy_dout[0]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_2__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [7]),\n .I1(phy_wrdata[31]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_38 [0]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_2__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [15]),\n .I1(phy_wrdata[31]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_39 [0]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_2__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [23]),\n .I1(phy_wrdata[31]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_40 [0]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_2__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [223]),\n .I1(phy_wrdata[223]),\n .I2(init_calib_complete_reg_rep__8),\n .O(\\my_empty_reg[7]_41 [6]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [62]),\n .I1(phy_wrdata[62]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_41 [9]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_3__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [103]),\n .I1(phy_wrdata[127]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_38 [3]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_3__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [111]),\n .I1(phy_wrdata[127]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_39 [3]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_3__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [119]),\n .I1(phy_wrdata[127]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_40 [3]));\n LUT2 #(\n .INIT(4'hE)) \n mem_reg_0_15_6_11_i_3__3\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),\n .I1(init_calib_complete_reg_rep__13),\n .O(phy_dout[3]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_4\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [26]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),\n .I2(init_calib_complete_reg_rep__13),\n .O(phy_dout[2]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_4__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [30]),\n .I1(phy_wrdata[30]),\n .I2(init_calib_complete_reg_rep__12),\n .O(\\my_empty_reg[7]_41 [8]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_4__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [71]),\n .I1(phy_wrdata[95]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_38 [2]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_4__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [79]),\n .I1(phy_wrdata[95]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_39 [2]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_4__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [87]),\n .I1(phy_wrdata[95]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_40 [2]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [126]),\n .I1(phy_wrdata[126]),\n .I2(init_calib_complete_reg_rep__10),\n .O(\\my_empty_reg[7]_41 [11]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_6_11_i_6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [94]),\n .I1(phy_wrdata[94]),\n .I2(init_calib_complete_reg_rep__11),\n .O(\\my_empty_reg[7]_41 [10]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_72_77_i_1__0\n (.I0(\\cmd_pipe_plus.mc_bank_reg[8] [4]),\n .I1(phy_bank[10]),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [31]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_72_77_i_2\n (.I0(\\cmd_pipe_plus.mc_bank_reg[8] [1]),\n .I1(phy_bank[10]),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [30]));\n LUT2 #(\n .INIT(4'hE)) \n mem_reg_0_15_72_77_i_3\n (.I0(phy_bank[10]),\n .I1(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [33]));\n LUT3 #(\n .INIT(8'hAC)) \n mem_reg_0_15_72_77_i_4\n (.I0(\\cmd_pipe_plus.mc_bank_reg[8] [7]),\n .I1(phy_bank[10]),\n .I2(init_calib_complete_reg_rep__13),\n .O(\\rd_ptr_timing_reg[0] [32]));\n (* SOFT_HLUTNM = \"soft_lutpair485\" *) \n LUT5 #(\n .INIT(32'hAAAAAAA8)) \n mpr_end_if_reset_i_1\n (.I0(mpr_last_byte_done),\n .I1(num_refresh_reg__0[2]),\n .I2(num_refresh_reg__0[0]),\n .I3(num_refresh_reg__0[1]),\n .I4(num_refresh_reg__0[3]),\n .O(mpr_end_if_reset0));\n FDRE mpr_end_if_reset_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mpr_end_if_reset0),\n .Q(mpr_end_if_reset),\n .R(rstdiv0_sync_r1_reg_rep__11));\n LUT6 #(\n .INIT(64'hFFFFFFFF00100000)) \n mpr_rdlvl_start_i_1\n (.I0(mpr_rdlvl_start_i_2_n_0),\n .I1(Q[2]),\n .I2(\\init_state_r_reg_n_0_[3] ),\n .I3(Q[1]),\n .I4(dqs_found_done_r_reg),\n .I5(mpr_rdlvl_start_r_reg),\n .O(mpr_rdlvl_start_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair525\" *) \n LUT4 #(\n .INIT(16'hFBFF)) \n mpr_rdlvl_start_i_2\n (.I0(Q[5]),\n .I1(Q[4]),\n .I2(Q[3]),\n .I3(Q[0]),\n .O(mpr_rdlvl_start_i_2_n_0));\n FDRE mpr_rdlvl_start_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mpr_rdlvl_start_i_1_n_0),\n .Q(mpr_rdlvl_start_r_reg),\n .R(rstdiv0_sync_r1_reg_rep__12));\n (* SOFT_HLUTNM = \"soft_lutpair611\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\num_refresh[0]_i_1 \n (.I0(num_refresh_reg__0[0]),\n .O(p_0_in__4[0]));\n (* SOFT_HLUTNM = \"soft_lutpair611\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\num_refresh[1]_i_1 \n (.I0(num_refresh_reg__0[1]),\n .I1(num_refresh_reg__0[0]),\n .O(p_0_in__4[1]));\n (* SOFT_HLUTNM = \"soft_lutpair556\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\num_refresh[2]_i_1 \n (.I0(num_refresh_reg__0[2]),\n .I1(num_refresh_reg__0[0]),\n .I2(num_refresh_reg__0[1]),\n .O(p_0_in__4[2]));\n LUT6 #(\n .INIT(64'hFEFEFEFEFEFFFEFE)) \n \\num_refresh[3]_i_1 \n (.I0(\\num_refresh[3]_i_4_n_0 ),\n .I1(rstdiv0_sync_r1_reg_rep__24),\n .I2(\\num_refresh[3]_i_5_n_0 ),\n .I3(prbs_rdlvl_start_i_2_n_0),\n .I4(\\wrcal_reads[7]_i_5_n_0 ),\n .I5(read_calib_i_2_n_0),\n .O(\\num_refresh[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h22A2AAA2AAAAAAAA)) \n \\num_refresh[3]_i_2 \n (.I0(\\cnt_init_mr_r_reg[1]_0 ),\n .I1(dqs_found_done_r_reg),\n .I2(wrcal_done_reg_10),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(prbs_rdlvl_done_reg),\n .I5(oclkdelay_calib_done_r_reg_2),\n .O(num_refresh0));\n (* SOFT_HLUTNM = \"soft_lutpair556\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\num_refresh[3]_i_3 \n (.I0(num_refresh_reg__0[3]),\n .I1(num_refresh_reg__0[1]),\n .I2(num_refresh_reg__0[0]),\n .I3(num_refresh_reg__0[2]),\n .O(p_0_in__4[3]));\n (* SOFT_HLUTNM = \"soft_lutpair506\" *) \n LUT5 #(\n .INIT(32'h404000FF)) \n \\num_refresh[3]_i_4 \n (.I0(complex_oclkdelay_calib_start_int_i_2_n_0),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .I2(Q[0]),\n .I3(\\num_refresh[3]_i_6_n_0 ),\n .I4(Q[1]),\n .O(\\num_refresh[3]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000002000)) \n \\num_refresh[3]_i_5 \n (.I0(Q[4]),\n .I1(Q[5]),\n .I2(Q[3]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[2]),\n .I5(complex_oclkdelay_calib_start_int_reg_0),\n .O(\\num_refresh[3]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFBFFFFFFFEFFFFFF)) \n \\num_refresh[3]_i_6 \n (.I0(Q[5]),\n .I1(Q[4]),\n .I2(Q[3]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[2]),\n .I5(Q[0]),\n .O(\\num_refresh[3]_i_6_n_0 ));\n FDRE \\num_refresh_reg[0] \n (.C(CLK),\n .CE(num_refresh0),\n .D(p_0_in__4[0]),\n .Q(num_refresh_reg__0[0]),\n .R(\\num_refresh[3]_i_1_n_0 ));\n FDRE \\num_refresh_reg[1] \n (.C(CLK),\n .CE(num_refresh0),\n .D(p_0_in__4[1]),\n .Q(num_refresh_reg__0[1]),\n .R(\\num_refresh[3]_i_1_n_0 ));\n FDRE \\num_refresh_reg[2] \n (.C(CLK),\n .CE(num_refresh0),\n .D(p_0_in__4[2]),\n .Q(num_refresh_reg__0[2]),\n .R(\\num_refresh[3]_i_1_n_0 ));\n FDRE \\num_refresh_reg[3] \n (.C(CLK),\n .CE(num_refresh0),\n .D(p_0_in__4[3]),\n .Q(num_refresh_reg__0[3]),\n .R(\\num_refresh[3]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\ocal_act_wait_cnt[0]_i_1 \n (.I0(ocal_act_wait_cnt_reg__0[0]),\n .O(p_0_in__9[0]));\n (* SOFT_HLUTNM = \"soft_lutpair603\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\ocal_act_wait_cnt[1]_i_1 \n (.I0(ocal_act_wait_cnt_reg__0[1]),\n .I1(ocal_act_wait_cnt_reg__0[0]),\n .O(p_0_in__9[1]));\n (* SOFT_HLUTNM = \"soft_lutpair603\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\ocal_act_wait_cnt[2]_i_1 \n (.I0(ocal_act_wait_cnt_reg__0[2]),\n .I1(ocal_act_wait_cnt_reg__0[1]),\n .I2(ocal_act_wait_cnt_reg__0[0]),\n .O(p_0_in__9[2]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFDFFFF)) \n \\ocal_act_wait_cnt[3]_i_1 \n (.I0(\\ocal_act_wait_cnt[3]_i_3_n_0 ),\n .I1(Q[4]),\n .I2(Q[3]),\n .I3(oclk_calib_resume_level_reg_0),\n .I4(Q[5]),\n .I5(rstdiv0_sync_r1_reg_rep__24),\n .O(\\ocal_act_wait_cnt[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair538\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\ocal_act_wait_cnt[3]_i_2 \n (.I0(ocal_act_wait_cnt_reg__0[3]),\n .I1(ocal_act_wait_cnt_reg__0[0]),\n .I2(ocal_act_wait_cnt_reg__0[1]),\n .I3(ocal_act_wait_cnt_reg__0[2]),\n .O(p_0_in__9[3]));\n LUT6 #(\n .INIT(64'h000000007FFF0000)) \n \\ocal_act_wait_cnt[3]_i_3 \n (.I0(ocal_act_wait_cnt_reg__0[3]),\n .I1(ocal_act_wait_cnt_reg__0[0]),\n .I2(ocal_act_wait_cnt_reg__0[1]),\n .I3(ocal_act_wait_cnt_reg__0[2]),\n .I4(Q[1]),\n .I5(Q[0]),\n .O(\\ocal_act_wait_cnt[3]_i_3_n_0 ));\n FDRE \\ocal_act_wait_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__9[0]),\n .Q(ocal_act_wait_cnt_reg__0[0]),\n .R(\\ocal_act_wait_cnt[3]_i_1_n_0 ));\n FDRE \\ocal_act_wait_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__9[1]),\n .Q(ocal_act_wait_cnt_reg__0[1]),\n .R(\\ocal_act_wait_cnt[3]_i_1_n_0 ));\n FDRE \\ocal_act_wait_cnt_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__9[2]),\n .Q(ocal_act_wait_cnt_reg__0[2]),\n .R(\\ocal_act_wait_cnt[3]_i_1_n_0 ));\n FDRE \\ocal_act_wait_cnt_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__9[3]),\n .Q(ocal_act_wait_cnt_reg__0[3]),\n .R(\\ocal_act_wait_cnt[3]_i_1_n_0 ));\n FDRE ocal_last_byte_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(oclkdelay_center_calib_done_r_reg),\n .Q(ocal_last_byte_done),\n .R(rstdiv0_sync_r1_reg_rep__11));\n LUT6 #(\n .INIT(64'h00000000EEEEEE0E)) \n oclk_calib_resume_level_i_1\n (.I0(oclk_calib_resume_level),\n .I1(complex_oclk_calib_resume),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .I3(complex_oclkdelay_calib_start_int_i_2_n_0),\n .I4(oclk_calib_resume_level_reg_0),\n .I5(rstdiv0_sync_r1_reg_rep__25),\n .O(oclk_calib_resume_level_i_1_n_0));\n FDRE oclk_calib_resume_level_reg\n (.C(CLK),\n .CE(1'b1),\n .D(oclk_calib_resume_level_i_1_n_0),\n .Q(oclk_calib_resume_level),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair607\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\oclk_wr_cnt[0]_i_1 \n (.I0(oclk_wr_cnt_reg__0[0]),\n .O(\\oclk_wr_cnt[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair607\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\oclk_wr_cnt[1]_i_1 \n (.I0(oclk_wr_cnt_reg__0[0]),\n .I1(oclk_wr_cnt_reg__0[1]),\n .O(\\oclk_wr_cnt[1]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hA9)) \n \\oclk_wr_cnt[2]_i_1 \n (.I0(oclk_wr_cnt_reg__0[2]),\n .I1(oclk_wr_cnt_reg__0[1]),\n .I2(oclk_wr_cnt_reg__0[0]),\n .O(oclk_wr_cnt0[2]));\n LUT6 #(\n .INIT(64'hFFFFFFFFAAAAAAAB)) \n \\oclk_wr_cnt[3]_i_1 \n (.I0(\\oclk_wr_cnt[3]_i_4_n_0 ),\n .I1(oclk_wr_cnt_reg__0[2]),\n .I2(oclk_wr_cnt_reg__0[0]),\n .I3(oclk_wr_cnt_reg__0[1]),\n .I4(oclk_wr_cnt_reg__0[3]),\n .I5(rstdiv0_sync_r1_reg_rep__24),\n .O(\\oclk_wr_cnt[3]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h00800000)) \n \\oclk_wr_cnt[3]_i_2 \n (.I0(Q[1]),\n .I1(Q[2]),\n .I2(Q[0]),\n .I3(read_calib_i_2_n_0),\n .I4(\\init_state_r_reg_n_0_[3] ),\n .O(p_0_in0_in));\n (* SOFT_HLUTNM = \"soft_lutpair547\" *) \n LUT4 #(\n .INIT(16'hAAA9)) \n \\oclk_wr_cnt[3]_i_3 \n (.I0(oclk_wr_cnt_reg__0[3]),\n .I1(oclk_wr_cnt_reg__0[2]),\n .I2(oclk_wr_cnt_reg__0[0]),\n .I3(oclk_wr_cnt_reg__0[1]),\n .O(oclk_wr_cnt0[3]));\n LUT6 #(\n .INIT(64'h0000000000100000)) \n \\oclk_wr_cnt[3]_i_4 \n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(Q[4]),\n .I3(Q[5]),\n .I4(Q[3]),\n .I5(oclk_calib_resume_level_reg_0),\n .O(\\oclk_wr_cnt[3]_i_4_n_0 ));\n FDRE \\oclk_wr_cnt_reg[0] \n (.C(CLK),\n .CE(p_0_in0_in),\n .D(\\oclk_wr_cnt[0]_i_1_n_0 ),\n .Q(oclk_wr_cnt_reg__0[0]),\n .R(\\oclk_wr_cnt[3]_i_1_n_0 ));\n FDRE \\oclk_wr_cnt_reg[1] \n (.C(CLK),\n .CE(p_0_in0_in),\n .D(\\oclk_wr_cnt[1]_i_1_n_0 ),\n .Q(oclk_wr_cnt_reg__0[1]),\n .R(\\oclk_wr_cnt[3]_i_1_n_0 ));\n FDSE \\oclk_wr_cnt_reg[2] \n (.C(CLK),\n .CE(p_0_in0_in),\n .D(oclk_wr_cnt0[2]),\n .Q(oclk_wr_cnt_reg__0[2]),\n .S(\\oclk_wr_cnt[3]_i_1_n_0 ));\n FDRE \\oclk_wr_cnt_reg[3] \n (.C(CLK),\n .CE(p_0_in0_in),\n .D(oclk_wr_cnt0[3]),\n .Q(oclk_wr_cnt_reg__0[3]),\n .R(\\oclk_wr_cnt[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair608\" *) \n LUT2 #(\n .INIT(4'hE)) \n oclkdelay_calib_start_int_i_1\n (.I0(oclkdelay_start_dly_r),\n .I1(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .O(oclkdelay_calib_start_int_i_1_n_0));\n FDRE oclkdelay_calib_start_int_reg\n (.C(CLK),\n .CE(1'b1),\n .D(oclkdelay_calib_start_int_i_1_n_0),\n .Q(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .R(rstdiv0_sync_r1_reg_rep__12));\n LUT5 #(\n .INIT(32'h0000AAEA)) \n oclkdelay_int_ref_req_i_1\n (.I0(oclkdelay_int_ref_req_reg_0),\n .I1(oclkdelay_int_ref_req_i_2_n_0),\n .I2(oclkdelay_ref_cnt_reg[0]),\n .I3(oclkdelay_int_ref_req_i_3_n_0),\n .I4(oclkdelay_int_ref_req0),\n .O(oclkdelay_int_ref_req_i_1_n_0));\n LUT6 #(\n .INIT(64'h0000000000000001)) \n oclkdelay_int_ref_req_i_2\n (.I0(oclkdelay_ref_cnt_reg[12]),\n .I1(oclkdelay_ref_cnt_reg[8]),\n .I2(oclkdelay_ref_cnt_reg[11]),\n .I3(oclkdelay_ref_cnt_reg[13]),\n .I4(oclkdelay_ref_cnt_reg[10]),\n .I5(oclkdelay_ref_cnt_reg[9]),\n .O(oclkdelay_int_ref_req_i_2_n_0));\n LUT4 #(\n .INIT(16'hFFFE)) \n oclkdelay_int_ref_req_i_3\n (.I0(oclkdelay_ref_cnt_reg[5]),\n .I1(oclkdelay_ref_cnt_reg[4]),\n .I2(oclkdelay_ref_cnt_reg[6]),\n .I3(oclkdelay_int_ref_req_i_5_n_0),\n .O(oclkdelay_int_ref_req_i_3_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFF4)) \n oclkdelay_int_ref_req_i_4\n (.I0(prbs_rdlvl_start_i_2_n_0),\n .I1(\\stg1_wr_rd_cnt[4]_i_5_n_0 ),\n .I2(ocal_last_byte_done),\n .I3(oclkdelay_center_calib_done_r_reg_0),\n .I4(rstdiv0_sync_r1_reg_rep__24),\n .I5(oclkdelay_calib_done_r_reg_2),\n .O(oclkdelay_int_ref_req0));\n LUT4 #(\n .INIT(16'hFFFE)) \n oclkdelay_int_ref_req_i_5\n (.I0(oclkdelay_ref_cnt_reg[1]),\n .I1(oclkdelay_ref_cnt_reg[3]),\n .I2(oclkdelay_ref_cnt_reg[7]),\n .I3(oclkdelay_ref_cnt_reg[2]),\n .O(oclkdelay_int_ref_req_i_5_n_0));\n FDRE oclkdelay_int_ref_req_reg\n (.C(CLK),\n .CE(1'b1),\n .D(oclkdelay_int_ref_req_i_1_n_0),\n .Q(oclkdelay_int_ref_req_reg_0),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hEEEEEFEEEEEEEEEE)) \n \\oclkdelay_ref_cnt[0]_i_1 \n (.I0(prbs_rdlvl_done_reg_0),\n .I1(\\cnt_init_mr_r_reg[1]_0 ),\n .I2(oclkdelay_int_ref_req_i_3_n_0),\n .I3(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .I4(oclkdelay_ref_cnt_reg[0]),\n .I5(oclkdelay_int_ref_req_i_2_n_0),\n .O(\\oclkdelay_ref_cnt[0]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\oclkdelay_ref_cnt[0]_i_4 \n (.I0(oclkdelay_ref_cnt_reg[3]),\n .O(\\oclkdelay_ref_cnt[0]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\oclkdelay_ref_cnt[0]_i_5 \n (.I0(oclkdelay_ref_cnt_reg[2]),\n .O(\\oclkdelay_ref_cnt[0]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\oclkdelay_ref_cnt[0]_i_6 \n (.I0(oclkdelay_ref_cnt_reg[1]),\n .O(\\oclkdelay_ref_cnt[0]_i_6_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\oclkdelay_ref_cnt[0]_i_7 \n (.I0(oclkdelay_ref_cnt_reg[0]),\n .O(\\oclkdelay_ref_cnt[0]_i_7_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\oclkdelay_ref_cnt[12]_i_2 \n (.I0(oclkdelay_ref_cnt_reg[13]),\n .O(\\oclkdelay_ref_cnt[12]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\oclkdelay_ref_cnt[12]_i_3 \n (.I0(oclkdelay_ref_cnt_reg[12]),\n .O(\\oclkdelay_ref_cnt[12]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\oclkdelay_ref_cnt[4]_i_2 \n (.I0(oclkdelay_ref_cnt_reg[7]),\n .O(\\oclkdelay_ref_cnt[4]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\oclkdelay_ref_cnt[4]_i_3 \n (.I0(oclkdelay_ref_cnt_reg[6]),\n .O(\\oclkdelay_ref_cnt[4]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\oclkdelay_ref_cnt[4]_i_4 \n (.I0(oclkdelay_ref_cnt_reg[5]),\n .O(\\oclkdelay_ref_cnt[4]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\oclkdelay_ref_cnt[4]_i_5 \n (.I0(oclkdelay_ref_cnt_reg[4]),\n .O(\\oclkdelay_ref_cnt[4]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\oclkdelay_ref_cnt[8]_i_2 \n (.I0(oclkdelay_ref_cnt_reg[11]),\n .O(\\oclkdelay_ref_cnt[8]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\oclkdelay_ref_cnt[8]_i_3 \n (.I0(oclkdelay_ref_cnt_reg[10]),\n .O(\\oclkdelay_ref_cnt[8]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\oclkdelay_ref_cnt[8]_i_4 \n (.I0(oclkdelay_ref_cnt_reg[9]),\n .O(\\oclkdelay_ref_cnt[8]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\oclkdelay_ref_cnt[8]_i_5 \n (.I0(oclkdelay_ref_cnt_reg[8]),\n .O(\\oclkdelay_ref_cnt[8]_i_5_n_0 ));\n FDRE \\oclkdelay_ref_cnt_reg[0] \n (.C(CLK),\n .CE(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .D(\\oclkdelay_ref_cnt_reg[0]_i_2_n_7 ),\n .Q(oclkdelay_ref_cnt_reg[0]),\n .R(\\oclkdelay_ref_cnt[0]_i_1_n_0 ));\n CARRY4 \\oclkdelay_ref_cnt_reg[0]_i_2 \n (.CI(1'b0),\n .CO({\\oclkdelay_ref_cnt_reg[0]_i_2_n_0 ,\\oclkdelay_ref_cnt_reg[0]_i_2_n_1 ,\\oclkdelay_ref_cnt_reg[0]_i_2_n_2 ,\\oclkdelay_ref_cnt_reg[0]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b1,1'b1,1'b1,1'b1}),\n .O({\\oclkdelay_ref_cnt_reg[0]_i_2_n_4 ,\\oclkdelay_ref_cnt_reg[0]_i_2_n_5 ,\\oclkdelay_ref_cnt_reg[0]_i_2_n_6 ,\\oclkdelay_ref_cnt_reg[0]_i_2_n_7 }),\n .S({\\oclkdelay_ref_cnt[0]_i_4_n_0 ,\\oclkdelay_ref_cnt[0]_i_5_n_0 ,\\oclkdelay_ref_cnt[0]_i_6_n_0 ,\\oclkdelay_ref_cnt[0]_i_7_n_0 }));\n FDSE \\oclkdelay_ref_cnt_reg[10] \n (.C(CLK),\n .CE(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .D(\\oclkdelay_ref_cnt_reg[8]_i_1_n_5 ),\n .Q(oclkdelay_ref_cnt_reg[10]),\n .S(\\oclkdelay_ref_cnt[0]_i_1_n_0 ));\n FDRE \\oclkdelay_ref_cnt_reg[11] \n (.C(CLK),\n .CE(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .D(\\oclkdelay_ref_cnt_reg[8]_i_1_n_4 ),\n .Q(oclkdelay_ref_cnt_reg[11]),\n .R(\\oclkdelay_ref_cnt[0]_i_1_n_0 ));\n FDSE \\oclkdelay_ref_cnt_reg[12] \n (.C(CLK),\n .CE(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .D(\\oclkdelay_ref_cnt_reg[12]_i_1_n_7 ),\n .Q(oclkdelay_ref_cnt_reg[12]),\n .S(\\oclkdelay_ref_cnt[0]_i_1_n_0 ));\n CARRY4 \\oclkdelay_ref_cnt_reg[12]_i_1 \n (.CI(\\oclkdelay_ref_cnt_reg[8]_i_1_n_0 ),\n .CO({\\NLW_oclkdelay_ref_cnt_reg[12]_i_1_CO_UNCONNECTED [3:1],\\oclkdelay_ref_cnt_reg[12]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b1}),\n .O({\\NLW_oclkdelay_ref_cnt_reg[12]_i_1_O_UNCONNECTED [3:2],\\oclkdelay_ref_cnt_reg[12]_i_1_n_6 ,\\oclkdelay_ref_cnt_reg[12]_i_1_n_7 }),\n .S({1'b0,1'b0,\\oclkdelay_ref_cnt[12]_i_2_n_0 ,\\oclkdelay_ref_cnt[12]_i_3_n_0 }));\n FDSE \\oclkdelay_ref_cnt_reg[13] \n (.C(CLK),\n .CE(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .D(\\oclkdelay_ref_cnt_reg[12]_i_1_n_6 ),\n .Q(oclkdelay_ref_cnt_reg[13]),\n .S(\\oclkdelay_ref_cnt[0]_i_1_n_0 ));\n FDSE \\oclkdelay_ref_cnt_reg[1] \n (.C(CLK),\n .CE(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .D(\\oclkdelay_ref_cnt_reg[0]_i_2_n_6 ),\n .Q(oclkdelay_ref_cnt_reg[1]),\n .S(\\oclkdelay_ref_cnt[0]_i_1_n_0 ));\n FDSE \\oclkdelay_ref_cnt_reg[2] \n (.C(CLK),\n .CE(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .D(\\oclkdelay_ref_cnt_reg[0]_i_2_n_5 ),\n .Q(oclkdelay_ref_cnt_reg[2]),\n .S(\\oclkdelay_ref_cnt[0]_i_1_n_0 ));\n FDSE \\oclkdelay_ref_cnt_reg[3] \n (.C(CLK),\n .CE(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .D(\\oclkdelay_ref_cnt_reg[0]_i_2_n_4 ),\n .Q(oclkdelay_ref_cnt_reg[3]),\n .S(\\oclkdelay_ref_cnt[0]_i_1_n_0 ));\n FDSE \\oclkdelay_ref_cnt_reg[4] \n (.C(CLK),\n .CE(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .D(\\oclkdelay_ref_cnt_reg[4]_i_1_n_7 ),\n .Q(oclkdelay_ref_cnt_reg[4]),\n .S(\\oclkdelay_ref_cnt[0]_i_1_n_0 ));\n CARRY4 \\oclkdelay_ref_cnt_reg[4]_i_1 \n (.CI(\\oclkdelay_ref_cnt_reg[0]_i_2_n_0 ),\n .CO({\\oclkdelay_ref_cnt_reg[4]_i_1_n_0 ,\\oclkdelay_ref_cnt_reg[4]_i_1_n_1 ,\\oclkdelay_ref_cnt_reg[4]_i_1_n_2 ,\\oclkdelay_ref_cnt_reg[4]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b1,1'b1,1'b1,1'b1}),\n .O({\\oclkdelay_ref_cnt_reg[4]_i_1_n_4 ,\\oclkdelay_ref_cnt_reg[4]_i_1_n_5 ,\\oclkdelay_ref_cnt_reg[4]_i_1_n_6 ,\\oclkdelay_ref_cnt_reg[4]_i_1_n_7 }),\n .S({\\oclkdelay_ref_cnt[4]_i_2_n_0 ,\\oclkdelay_ref_cnt[4]_i_3_n_0 ,\\oclkdelay_ref_cnt[4]_i_4_n_0 ,\\oclkdelay_ref_cnt[4]_i_5_n_0 }));\n FDSE \\oclkdelay_ref_cnt_reg[5] \n (.C(CLK),\n .CE(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .D(\\oclkdelay_ref_cnt_reg[4]_i_1_n_6 ),\n .Q(oclkdelay_ref_cnt_reg[5]),\n .S(\\oclkdelay_ref_cnt[0]_i_1_n_0 ));\n FDRE \\oclkdelay_ref_cnt_reg[6] \n (.C(CLK),\n .CE(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .D(\\oclkdelay_ref_cnt_reg[4]_i_1_n_5 ),\n .Q(oclkdelay_ref_cnt_reg[6]),\n .R(\\oclkdelay_ref_cnt[0]_i_1_n_0 ));\n FDSE \\oclkdelay_ref_cnt_reg[7] \n (.C(CLK),\n .CE(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .D(\\oclkdelay_ref_cnt_reg[4]_i_1_n_4 ),\n .Q(oclkdelay_ref_cnt_reg[7]),\n .S(\\oclkdelay_ref_cnt[0]_i_1_n_0 ));\n FDSE \\oclkdelay_ref_cnt_reg[8] \n (.C(CLK),\n .CE(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .D(\\oclkdelay_ref_cnt_reg[8]_i_1_n_7 ),\n .Q(oclkdelay_ref_cnt_reg[8]),\n .S(\\oclkdelay_ref_cnt[0]_i_1_n_0 ));\n CARRY4 \\oclkdelay_ref_cnt_reg[8]_i_1 \n (.CI(\\oclkdelay_ref_cnt_reg[4]_i_1_n_0 ),\n .CO({\\oclkdelay_ref_cnt_reg[8]_i_1_n_0 ,\\oclkdelay_ref_cnt_reg[8]_i_1_n_1 ,\\oclkdelay_ref_cnt_reg[8]_i_1_n_2 ,\\oclkdelay_ref_cnt_reg[8]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b1,1'b1,1'b1,1'b1}),\n .O({\\oclkdelay_ref_cnt_reg[8]_i_1_n_4 ,\\oclkdelay_ref_cnt_reg[8]_i_1_n_5 ,\\oclkdelay_ref_cnt_reg[8]_i_1_n_6 ,\\oclkdelay_ref_cnt_reg[8]_i_1_n_7 }),\n .S({\\oclkdelay_ref_cnt[8]_i_2_n_0 ,\\oclkdelay_ref_cnt[8]_i_3_n_0 ,\\oclkdelay_ref_cnt[8]_i_4_n_0 ,\\oclkdelay_ref_cnt[8]_i_5_n_0 }));\n FDRE \\oclkdelay_ref_cnt_reg[9] \n (.C(CLK),\n .CE(\\oclkdelay_ref_cnt_reg[13]_0 ),\n .D(\\oclkdelay_ref_cnt_reg[8]_i_1_n_6 ),\n .Q(oclkdelay_ref_cnt_reg[9]),\n .R(\\oclkdelay_ref_cnt[0]_i_1_n_0 ));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/oclkdelay_start_dly_r_reg \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/oclkdelay_start_dly_r_reg[4]_srl5 \" *) \n SRL16E \\oclkdelay_start_dly_r_reg[4]_srl5 \n (.A0(1'b0),\n .A1(1'b0),\n .A2(1'b1),\n .A3(1'b0),\n .CE(1'b1),\n .CLK(CLK),\n .D(oclkdelay_calib_start_pre),\n .Q(\\oclkdelay_start_dly_r_reg[4]_srl5_n_0 ));\n LUT6 #(\n .INIT(64'h0000000020000000)) \n \\oclkdelay_start_dly_r_reg[4]_srl5_i_1 \n (.I0(Q[4]),\n .I1(Q[5]),\n .I2(Q[3]),\n .I3(Q[2]),\n .I4(\\init_state_r_reg_n_0_[3] ),\n .I5(prbs_rdlvl_start_i_2_n_0),\n .O(oclkdelay_calib_start_pre));\n FDRE \\oclkdelay_start_dly_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\oclkdelay_start_dly_r_reg[4]_srl5_n_0 ),\n .Q(oclkdelay_start_dly_r),\n .R(1'b0));\n LUT3 #(\n .INIT(8'h02)) \n \\odd_cwl.phy_cas_n[1]_i_1 \n (.I0(\\odd_cwl.phy_cas_n_reg[1]_0 ),\n .I1(\\odd_cwl.phy_ras_n[1]_i_2_n_0 ),\n .I2(\\cnt_init_mr_r_reg[1]_0 ),\n .O(\\odd_cwl.phy_cas_n[1]_i_1_n_0 ));\n FDRE \\odd_cwl.phy_cas_n_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\odd_cwl.phy_cas_n[1]_i_1_n_0 ),\n .Q(phy_cas_n),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h1)) \n \\odd_cwl.phy_ras_n[1]_i_1 \n (.I0(\\DDR3_1rank.phy_int_cs_n[1]_i_6_n_0 ),\n .I1(\\odd_cwl.phy_ras_n[1]_i_2_n_0 ),\n .O(\\odd_cwl.phy_ras_n[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hEEEEEEEEEEEEEEEF)) \n \\odd_cwl.phy_ras_n[1]_i_2 \n (.I0(\\DDR3_1rank.phy_int_cs_n[1]_i_5_n_0 ),\n .I1(reg_ctrl_cnt_r),\n .I2(Q[5]),\n .I3(Q[4]),\n .I4(Q[3]),\n .I5(read_calib_reg_0),\n .O(\\odd_cwl.phy_ras_n[1]_i_2_n_0 ));\n FDRE \\odd_cwl.phy_ras_n_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\odd_cwl.phy_ras_n[1]_i_1_n_0 ),\n .Q(phy_ras_n),\n .R(1'b0));\n LUT3 #(\n .INIT(8'h04)) \n \\odd_cwl.phy_we_n[1]_i_1 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),\n .I1(\\calib_cmd[2]_i_2_n_0 ),\n .I2(\\odd_cwl.phy_ras_n[1]_i_2_n_0 ),\n .O(\\odd_cwl.phy_we_n[1]_i_1_n_0 ));\n FDRE \\odd_cwl.phy_we_n_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\odd_cwl.phy_we_n[1]_i_1_n_0 ),\n .Q(phy_we_n),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h000000000000000E)) \n \\one_rank.stg1_wr_done_i_1 \n (.I0(\\one_rank.stg1_wr_done_reg_0 ),\n .I1(stg1_wr_done),\n .I2(\\reg_ctrl_cnt_r_reg[3]_0 ),\n .I3(rdlvl_last_byte_done),\n .I4(prbs_rdlvl_done_pulse),\n .I5(complex_byte_rd_done),\n .O(\\one_rank.stg1_wr_done_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000020)) \n \\one_rank.stg1_wr_done_i_2 \n (.I0(Q[1]),\n .I1(Q[3]),\n .I2(Q[0]),\n .I3(Q[5]),\n .I4(Q[4]),\n .I5(\\init_state_r[4]_i_5_n_0 ),\n .O(stg1_wr_done));\n FDRE \\one_rank.stg1_wr_done_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\one_rank.stg1_wr_done_i_1_n_0 ),\n .Q(\\one_rank.stg1_wr_done_reg_0 ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000000E0E0E)) \n \\one_rank_complex.complex_wr_done_i_1 \n (.I0(complex_wr_done),\n .I1(\\one_rank_complex.complex_wr_done_i_2_n_0 ),\n .I2(\\one_rank_complex.complex_wr_done_i_3_n_0 ),\n .I3(prbs_rdlvl_done_reg),\n .I4(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .I5(\\one_rank_complex.complex_wr_done_i_4_n_0 ),\n .O(\\one_rank_complex.complex_wr_done_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000800000000000)) \n \\one_rank_complex.complex_wr_done_i_2 \n (.I0(\\one_rank_complex.complex_wr_done_i_5_n_0 ),\n .I1(complex_wait_cnt_reg__0[2]),\n .I2(complex_wait_cnt_reg__0[3]),\n .I3(complex_row1_wr_done),\n .I4(complex_wait_cnt_reg__0[1]),\n .I5(complex_wait_cnt_reg__0[0]),\n .O(\\one_rank_complex.complex_wr_done_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000080000)) \n \\one_rank_complex.complex_wr_done_i_3 \n (.I0(complex_byte_rd_done),\n .I1(Q[1]),\n .I2(\\init_state_r_reg_n_0_[3] ),\n .I3(Q[0]),\n .I4(Q[2]),\n .I5(complex_oclkdelay_calib_start_int_i_2_n_0),\n .O(\\one_rank_complex.complex_wr_done_i_3_n_0 ));\n LUT3 #(\n .INIT(8'hFE)) \n \\one_rank_complex.complex_wr_done_i_4 \n (.I0(\\reg_ctrl_cnt_r_reg[3]_0 ),\n .I1(rdlvl_last_byte_done),\n .I2(prbs_rdlvl_done_pulse),\n .O(\\one_rank_complex.complex_wr_done_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair516\" *) \n LUT5 #(\n .INIT(32'h00001800)) \n \\one_rank_complex.complex_wr_done_i_5 \n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(\\init_state_r_reg_n_0_[3] ),\n .I3(Q[2]),\n .I4(complex_oclkdelay_calib_start_int_i_2_n_0),\n .O(\\one_rank_complex.complex_wr_done_i_5_n_0 ));\n FDRE \\one_rank_complex.complex_wr_done_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\one_rank_complex.complex_wr_done_i_1_n_0 ),\n .Q(complex_wr_done),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_10__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [231]),\n .I1(phy_wrdata[255]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_2 [7]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_13 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_10__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [239]),\n .I1(phy_wrdata[255]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_3 [7]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_21 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_10__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [247]),\n .I1(phy_wrdata[255]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_4 [7]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_29 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_10__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [254]),\n .I1(phy_wrdata[254]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_5 [15]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_36 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_11__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [199]),\n .I1(phy_wrdata[223]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_2 [6]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_13 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_11__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [207]),\n .I1(phy_wrdata[223]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_3 [6]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_21 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_11__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [215]),\n .I1(phy_wrdata[223]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_4 [6]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_29 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_11__6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [222]),\n .I1(phy_wrdata[222]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_5 [14]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_36 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_12__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [167]),\n .I1(phy_wrdata[191]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_2 [5]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_13 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_12__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [175]),\n .I1(phy_wrdata[191]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_3 [5]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_21 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_12__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [183]),\n .I1(phy_wrdata[191]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_4 [5]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_29 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_12__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [190]),\n .I1(phy_wrdata[190]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_5 [13]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_36 [5]));\n LUT5 #(\n .INIT(32'hB8B8FF00)) \n out_fifo_i_13__2\n (.I0(mc_odt),\n .I1(init_calib_complete_reg_rep__6),\n .I2(calib_odt),\n .I3(\\rd_ptr_reg[3]_0 [3]),\n .I4(\\my_empty_reg[1]_1 ),\n .O(D5[3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_13__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [135]),\n .I1(phy_wrdata[159]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_2 [4]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_13 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_13__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [143]),\n .I1(phy_wrdata[159]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_3 [4]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_21 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_13__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [151]),\n .I1(phy_wrdata[159]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_4 [4]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_29 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_13__6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [158]),\n .I1(phy_wrdata[158]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_5 [12]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_36 [4]));\n LUT5 #(\n .INIT(32'hB8B8FF00)) \n out_fifo_i_14__1\n (.I0(mc_odt),\n .I1(init_calib_complete_reg_rep__6),\n .I2(calib_odt),\n .I3(\\rd_ptr_reg[3]_0 [2]),\n .I4(\\my_empty_reg[1]_1 ),\n .O(D5[2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_14__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [103]),\n .I1(phy_wrdata[127]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_2 [3]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_13 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_14__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [111]),\n .I1(phy_wrdata[127]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_3 [3]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_21 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_14__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [119]),\n .I1(phy_wrdata[127]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_4 [3]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_29 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_14__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [126]),\n .I1(phy_wrdata[126]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_5 [11]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_36 [3]));\n LUT4 #(\n .INIT(16'hEEF0)) \n out_fifo_i_14__6\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),\n .I1(init_calib_complete_reg_rep__0),\n .I2(\\rd_ptr_reg[3]_1 [3]),\n .I3(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7] [3]));\n LUT5 #(\n .INIT(32'hB8B8FF00)) \n out_fifo_i_15__0\n (.I0(mc_odt),\n .I1(init_calib_complete_reg_rep__6),\n .I2(calib_odt),\n .I3(\\rd_ptr_reg[3]_0 [1]),\n .I4(\\my_empty_reg[1]_1 ),\n .O(D5[1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_15__1\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [26]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_1 [2]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7] [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_15__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [71]),\n .I1(phy_wrdata[95]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_2 [2]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_13 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_15__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [79]),\n .I1(phy_wrdata[95]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_3 [2]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_21 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_15__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [87]),\n .I1(phy_wrdata[95]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_4 [2]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_29 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_15__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [94]),\n .I1(phy_wrdata[94]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_5 [10]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_36 [2]));\n LUT5 #(\n .INIT(32'hB8B8FF00)) \n out_fifo_i_16__0\n (.I0(mc_odt),\n .I1(init_calib_complete_reg_rep__6),\n .I2(calib_odt),\n .I3(\\rd_ptr_reg[3]_0 [0]),\n .I4(\\my_empty_reg[1]_1 ),\n .O(D5[0]));\n LUT5 #(\n .INIT(32'hB8B8FF00)) \n out_fifo_i_16__1\n (.I0(mc_we_n),\n .I1(init_calib_complete_reg_rep__6),\n .I2(phy_we_n),\n .I3(mem_out[1]),\n .I4(\\my_empty_reg[1]_0 ),\n .O(D1));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_16__2\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [15]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_1 [1]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7] [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_16__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [39]),\n .I1(phy_wrdata[63]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_2 [1]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_13 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_16__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [47]),\n .I1(phy_wrdata[63]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_3 [1]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_21 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_16__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [55]),\n .I1(phy_wrdata[63]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_4 [1]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_29 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_16__6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [62]),\n .I1(phy_wrdata[62]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_5 [9]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_36 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_17__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [5]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),\n .I2(init_calib_complete_reg_rep__6),\n .I3(\\rd_ptr_reg[3]_1 [0]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7] [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_17__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [7]),\n .I1(phy_wrdata[31]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_2 [0]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_13 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_17__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [15]),\n .I1(phy_wrdata[31]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_3 [0]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_21 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_17__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [23]),\n .I1(phy_wrdata[31]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_4 [0]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_29 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_17__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [30]),\n .I1(phy_wrdata[30]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_5 [8]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_36 [0]));\n LUT5 #(\n .INIT(32'hB8B8FF00)) \n out_fifo_i_18__2\n (.I0(mc_cas_n),\n .I1(init_calib_complete_reg_rep__6),\n .I2(phy_cas_n),\n .I3(\\rd_ptr_reg[3] [0]),\n .I4(\\my_empty_reg[1] ),\n .O(D2));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_18__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [230]),\n .I1(phy_wrdata[254]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_2 [15]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_12 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_18__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [238]),\n .I1(phy_wrdata[254]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_3 [15]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_20 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_18__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [246]),\n .I1(phy_wrdata[254]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_4 [15]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_28 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_18__6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [253]),\n .I1(phy_wrdata[253]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_5 [23]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_35 [7]));\n LUT5 #(\n .INIT(32'hB8B8FF00)) \n out_fifo_i_19__1\n (.I0(mc_cke),\n .I1(init_calib_complete_reg_rep__6),\n .I2(calib_cke),\n .I3(\\rd_ptr_reg[3]_0 [7]),\n .I4(\\my_empty_reg[1]_1 ),\n .O(D6[3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_19__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [198]),\n .I1(phy_wrdata[222]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_2 [14]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_12 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_19__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [206]),\n .I1(phy_wrdata[222]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_3 [14]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_20 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_19__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [214]),\n .I1(phy_wrdata[222]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_4 [14]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_28 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_19__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [221]),\n .I1(phy_wrdata[221]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_5 [22]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_35 [6]));\n LUT5 #(\n .INIT(32'hB8B8FF00)) \n out_fifo_i_20__1\n (.I0(mc_cke),\n .I1(init_calib_complete_reg_rep__6),\n .I2(calib_cke),\n .I3(\\rd_ptr_reg[3]_0 [6]),\n .I4(\\my_empty_reg[1]_1 ),\n .O(D6[2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_20__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [166]),\n .I1(phy_wrdata[190]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_2 [13]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_12 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_20__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [174]),\n .I1(phy_wrdata[190]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_3 [13]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_20 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_20__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [182]),\n .I1(phy_wrdata[190]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_4 [13]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_28 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_20__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [189]),\n .I1(phy_wrdata[189]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_5 [21]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_35 [5]));\n LUT5 #(\n .INIT(32'hB8B8FF00)) \n out_fifo_i_21__1\n (.I0(mc_cke),\n .I1(init_calib_complete_reg_rep__6),\n .I2(calib_cke),\n .I3(\\rd_ptr_reg[3]_0 [5]),\n .I4(\\my_empty_reg[1]_1 ),\n .O(D6[1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_21__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [134]),\n .I1(phy_wrdata[158]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_2 [12]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_12 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_21__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [142]),\n .I1(phy_wrdata[158]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_3 [12]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_20 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_21__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [150]),\n .I1(phy_wrdata[158]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_4 [12]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_28 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_21__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [157]),\n .I1(phy_wrdata[157]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_5 [20]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_35 [4]));\n LUT5 #(\n .INIT(32'hB8B8FF00)) \n out_fifo_i_22__0\n (.I0(mc_cke),\n .I1(init_calib_complete_reg_rep__6),\n .I2(calib_cke),\n .I3(\\rd_ptr_reg[3]_0 [4]),\n .I4(\\my_empty_reg[1]_1 ),\n .O(D6[0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_22__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [102]),\n .I1(phy_wrdata[126]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_2 [11]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_12 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_22__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [110]),\n .I1(phy_wrdata[126]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_3 [11]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_20 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_22__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [118]),\n .I1(phy_wrdata[126]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_4 [11]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_28 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_22__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [125]),\n .I1(phy_wrdata[125]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_5 [19]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_35 [3]));\n LUT4 #(\n .INIT(16'hEEF0)) \n out_fifo_i_22__5\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),\n .I1(init_calib_complete_reg_rep__0),\n .I2(\\rd_ptr_reg[3]_1 [7]),\n .I3(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_0 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_23__1\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [27]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_1 [6]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_0 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_23__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [70]),\n .I1(phy_wrdata[94]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_2 [10]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_12 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_23__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [78]),\n .I1(phy_wrdata[94]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_3 [10]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_20 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_23__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [86]),\n .I1(phy_wrdata[94]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_4 [10]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_28 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_23__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [93]),\n .I1(phy_wrdata[93]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_5 [18]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_35 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_24__1\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [16]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_1 [5]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_0 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_24__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [38]),\n .I1(phy_wrdata[62]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_2 [9]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_12 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_24__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [46]),\n .I1(phy_wrdata[62]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_3 [9]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_20 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_24__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [54]),\n .I1(phy_wrdata[62]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_4 [9]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_28 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_24__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [61]),\n .I1(phy_wrdata[61]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_5 [17]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_35 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_25__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [6]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),\n .I2(init_calib_complete_reg_rep__6),\n .I3(\\rd_ptr_reg[3]_1 [4]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_0 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_25__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [6]),\n .I1(phy_wrdata[30]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_2 [8]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_12 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_25__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [14]),\n .I1(phy_wrdata[30]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_3 [8]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_20 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_25__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [22]),\n .I1(phy_wrdata[30]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_4 [8]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_28 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_25__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [29]),\n .I1(phy_wrdata[29]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_5 [16]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_35 [0]));\n LUT5 #(\n .INIT(32'hB8B8FF00)) \n out_fifo_i_26__1\n (.I0(mc_ras_n),\n .I1(init_calib_complete_reg_rep__6),\n .I2(phy_ras_n),\n .I3(\\rd_ptr_reg[3] [1]),\n .I4(\\my_empty_reg[1] ),\n .O(D3));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_26__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [229]),\n .I1(phy_wrdata[253]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_2 [23]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_11 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_26__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [237]),\n .I1(phy_wrdata[253]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_3 [23]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_19 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_26__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [245]),\n .I1(phy_wrdata[253]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_4 [23]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_27 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_26__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [252]),\n .I1(phy_wrdata[252]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_5 [31]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_34 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_27__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [197]),\n .I1(phy_wrdata[221]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_2 [22]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_11 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_27__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [205]),\n .I1(phy_wrdata[221]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_3 [22]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_19 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_27__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [213]),\n .I1(phy_wrdata[221]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_4 [22]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_27 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_27__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [220]),\n .I1(phy_wrdata[220]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_5 [30]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_34 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_28__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [165]),\n .I1(phy_wrdata[189]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_2 [21]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_11 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_28__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [173]),\n .I1(phy_wrdata[189]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_3 [21]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_19 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_28__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [181]),\n .I1(phy_wrdata[189]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_4 [21]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_27 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_28__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [188]),\n .I1(phy_wrdata[188]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_5 [29]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_34 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_29__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [133]),\n .I1(phy_wrdata[157]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_2 [20]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_11 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_29__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [141]),\n .I1(phy_wrdata[157]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_3 [20]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_19 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_29__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [149]),\n .I1(phy_wrdata[157]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_4 [20]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_27 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_29__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [156]),\n .I1(phy_wrdata[156]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_5 [28]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_34 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_2__6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [255]),\n .I1(phy_wrdata[255]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_5 [7]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_37 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_30__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [101]),\n .I1(phy_wrdata[125]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_2 [19]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_11 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_30__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [109]),\n .I1(phy_wrdata[125]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_3 [19]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_19 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_30__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [117]),\n .I1(phy_wrdata[125]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_4 [19]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_27 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_30__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [124]),\n .I1(phy_wrdata[124]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_5 [27]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_34 [3]));\n LUT4 #(\n .INIT(16'hEEF0)) \n out_fifo_i_30__5\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),\n .I1(init_calib_complete_reg_rep__0),\n .I2(\\rd_ptr_reg[3]_1 [11]),\n .I3(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_1 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_31__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [28]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_1 [10]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_1 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_31__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [69]),\n .I1(phy_wrdata[93]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_2 [18]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_11 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_31__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [77]),\n .I1(phy_wrdata[93]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_3 [18]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_19 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_31__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [85]),\n .I1(phy_wrdata[93]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_4 [18]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_27 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_31__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [92]),\n .I1(phy_wrdata[92]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_5 [26]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_34 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_32\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [17]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_1 [9]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_1 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_32__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [37]),\n .I1(phy_wrdata[61]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_2 [17]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_11 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_32__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [45]),\n .I1(phy_wrdata[61]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_3 [17]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_19 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_32__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [53]),\n .I1(phy_wrdata[61]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_4 [17]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_27 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_32__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [60]),\n .I1(phy_wrdata[60]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_5 [25]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_34 [1]));\n LUT4 #(\n .INIT(16'hEEF0)) \n out_fifo_i_32__4\n (.I0(phy_bank[9]),\n .I1(init_calib_complete_reg_rep),\n .I2(\\rd_ptr_reg[3] [5]),\n .I3(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_2 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_33\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [7]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),\n .I2(init_calib_complete_reg_rep__6),\n .I3(\\rd_ptr_reg[3]_1 [8]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_1 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_33__0\n (.I0(\\cmd_pipe_plus.mc_bank_reg[8] [6]),\n .I1(phy_bank[9]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3] [4]),\n .I4(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_2 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_33__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [5]),\n .I1(phy_wrdata[29]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_2 [16]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_11 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_33__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [13]),\n .I1(phy_wrdata[29]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_3 [16]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_19 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_33__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [21]),\n .I1(phy_wrdata[29]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_4 [16]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_27 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_33__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [28]),\n .I1(phy_wrdata[28]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_5 [24]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_34 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_34__0\n (.I0(\\cmd_pipe_plus.mc_bank_reg[8] [3]),\n .I1(phy_bank[9]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3] [3]),\n .I4(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_2 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_34__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [228]),\n .I1(phy_wrdata[252]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_2 [31]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_10 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_34__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [236]),\n .I1(phy_wrdata[252]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_3 [31]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_18 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_34__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [244]),\n .I1(phy_wrdata[252]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_4 [31]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_26 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_34__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [251]),\n .I1(phy_wrdata[251]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_5 [39]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_33 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_35__0\n (.I0(\\cmd_pipe_plus.mc_bank_reg[8] [0]),\n .I1(phy_bank[9]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3] [2]),\n .I4(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_2 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_35__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [196]),\n .I1(phy_wrdata[220]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_2 [30]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_10 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_35__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [204]),\n .I1(phy_wrdata[220]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_3 [30]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_18 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_35__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [212]),\n .I1(phy_wrdata[220]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_4 [30]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_26 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_35__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [219]),\n .I1(phy_wrdata[219]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_5 [38]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_33 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_36__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [164]),\n .I1(phy_wrdata[188]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_2 [29]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_10 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_36__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [172]),\n .I1(phy_wrdata[188]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_3 [29]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_18 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_36__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [180]),\n .I1(phy_wrdata[188]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_4 [29]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_26 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_36__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [187]),\n .I1(phy_wrdata[187]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_5 [37]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_33 [5]));\n LUT4 #(\n .INIT(16'hEEF0)) \n out_fifo_i_36__4\n (.I0(phy_bank[11]),\n .I1(init_calib_complete_reg_rep),\n .I2(\\rd_ptr_reg[3] [13]),\n .I3(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_1 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_37__0\n (.I0(\\cmd_pipe_plus.mc_bank_reg[8] [8]),\n .I1(phy_bank[11]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3] [12]),\n .I4(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_1 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_37__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [132]),\n .I1(phy_wrdata[156]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_2 [28]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_10 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_37__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [140]),\n .I1(phy_wrdata[156]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_3 [28]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_18 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_37__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [148]),\n .I1(phy_wrdata[156]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_4 [28]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_26 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_37__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [155]),\n .I1(phy_wrdata[155]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_5 [36]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_33 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_38\n (.I0(\\cmd_pipe_plus.mc_bank_reg[8] [5]),\n .I1(phy_bank[11]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3] [11]),\n .I4(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_1 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_38__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [100]),\n .I1(phy_wrdata[124]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_2 [27]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_10 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_38__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [108]),\n .I1(phy_wrdata[124]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_3 [27]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_18 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_38__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [116]),\n .I1(phy_wrdata[124]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_4 [27]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_26 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_38__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [123]),\n .I1(phy_wrdata[123]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_5 [35]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_33 [3]));\n LUT4 #(\n .INIT(16'hEEF0)) \n out_fifo_i_38__4\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),\n .I1(init_calib_complete_reg_rep__0),\n .I2(\\rd_ptr_reg[3]_1 [15]),\n .I3(\\my_empty_reg[1]_2 ),\n .O(D4[3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_39\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [29]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_1 [14]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(D4[2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_39__0\n (.I0(\\cmd_pipe_plus.mc_bank_reg[8] [2]),\n .I1(phy_bank[11]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3] [10]),\n .I4(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_1 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_39__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [68]),\n .I1(phy_wrdata[92]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_2 [26]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_10 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_39__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [76]),\n .I1(phy_wrdata[92]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_3 [26]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_18 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_39__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [84]),\n .I1(phy_wrdata[92]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_4 [26]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_26 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_39__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [91]),\n .I1(phy_wrdata[91]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_5 [34]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_33 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_3__6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [223]),\n .I1(phy_wrdata[223]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_5 [6]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_37 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_40\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [18]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_1 [13]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(D4[1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_40__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [36]),\n .I1(phy_wrdata[60]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_2 [25]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_10 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_40__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [44]),\n .I1(phy_wrdata[60]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_3 [25]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_18 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_40__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [52]),\n .I1(phy_wrdata[60]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_4 [25]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_26 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_40__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [59]),\n .I1(phy_wrdata[59]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_5 [33]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_33 [1]));\n (* SOFT_HLUTNM = \"soft_lutpair554\" *) \n LUT4 #(\n .INIT(16'hEEF0)) \n out_fifo_i_40__4\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .I1(init_calib_complete_reg_rep__0),\n .I2(\\rd_ptr_reg[3] [9]),\n .I3(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_1 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_41\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [8]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),\n .I2(init_calib_complete_reg_rep__6),\n .I3(\\rd_ptr_reg[3]_1 [12]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(D4[0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_41__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [25]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3] [8]),\n .I4(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_1 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_41__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [4]),\n .I1(phy_wrdata[28]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_2 [24]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_10 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_41__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [12]),\n .I1(phy_wrdata[28]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_3 [24]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_18 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_41__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [20]),\n .I1(phy_wrdata[28]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_4 [24]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_26 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_41__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [27]),\n .I1(phy_wrdata[27]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_5 [32]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_33 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_42__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [14]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3] [7]),\n .I4(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_1 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_42__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [227]),\n .I1(phy_wrdata[251]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_2 [39]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_9 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_42__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [235]),\n .I1(phy_wrdata[251]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_3 [39]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_17 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_42__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [243]),\n .I1(phy_wrdata[251]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_4 [39]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_25 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_42__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [250]),\n .I1(phy_wrdata[250]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_5 [47]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_32 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_43__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [4]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),\n .I2(init_calib_complete_reg_rep__6),\n .I3(\\rd_ptr_reg[3] [6]),\n .I4(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_1 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_43__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [195]),\n .I1(phy_wrdata[219]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_2 [38]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_9 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_43__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [203]),\n .I1(phy_wrdata[219]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_3 [38]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_17 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_43__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [211]),\n .I1(phy_wrdata[219]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_4 [38]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_25 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_43__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [218]),\n .I1(phy_wrdata[218]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_5 [46]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_32 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_44__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [163]),\n .I1(phy_wrdata[187]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_2 [37]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_9 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_44__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [171]),\n .I1(phy_wrdata[187]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_3 [37]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_17 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_44__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [179]),\n .I1(phy_wrdata[187]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_4 [37]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_25 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_44__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [186]),\n .I1(phy_wrdata[186]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_5 [45]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_32 [5]));\n LUT4 #(\n .INIT(16'hEEF0)) \n out_fifo_i_44__4\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),\n .I1(init_calib_complete_reg_rep__0),\n .I2(\\rd_ptr_reg[3] [21]),\n .I3(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_0 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_45__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [21]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3] [20]),\n .I4(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_0 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_45__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [131]),\n .I1(phy_wrdata[155]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_2 [36]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_9 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_45__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [139]),\n .I1(phy_wrdata[155]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_3 [36]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_17 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_45__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [147]),\n .I1(phy_wrdata[155]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_4 [36]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_25 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_45__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [154]),\n .I1(phy_wrdata[154]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_5 [44]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_32 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_46\n (.I0(mc_cas_n),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),\n .I2(init_calib_complete_reg_rep__6),\n .I3(\\rd_ptr_reg[3] [19]),\n .I4(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_0 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_46__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [99]),\n .I1(phy_wrdata[123]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_2 [35]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_9 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_46__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [107]),\n .I1(phy_wrdata[123]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_3 [35]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_17 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_46__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [115]),\n .I1(phy_wrdata[123]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_4 [35]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_25 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_46__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [122]),\n .I1(phy_wrdata[122]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_5 [43]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_32 [3]));\n (* SOFT_HLUTNM = \"soft_lutpair558\" *) \n LUT4 #(\n .INIT(16'hEEF0)) \n out_fifo_i_46__4\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),\n .I1(init_calib_complete_reg_rep__0),\n .I2(\\rd_ptr_reg[3]_1 [19]),\n .I3(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_2 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_47\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [0]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),\n .I2(init_calib_complete_reg_rep__6),\n .I3(\\rd_ptr_reg[3] [18]),\n .I4(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_0 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_47__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [30]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_1 [18]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_2 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_47__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [67]),\n .I1(phy_wrdata[91]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_2 [34]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_9 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_47__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [75]),\n .I1(phy_wrdata[91]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_3 [34]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_17 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_47__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [83]),\n .I1(phy_wrdata[91]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_4 [34]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_25 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_47__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [90]),\n .I1(phy_wrdata[90]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_5 [42]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_32 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_48\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [19]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_1 [17]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_2 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_48__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [35]),\n .I1(phy_wrdata[59]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_2 [33]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_9 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_48__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [43]),\n .I1(phy_wrdata[59]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_3 [33]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_17 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_48__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [51]),\n .I1(phy_wrdata[59]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_4 [33]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_25 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_48__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [58]),\n .I1(phy_wrdata[58]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_5 [41]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_32 [1]));\n LUT4 #(\n .INIT(16'hEEF0)) \n out_fifo_i_48__4\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),\n .I1(init_calib_complete_reg_rep__0),\n .I2(\\rd_ptr_reg[3] [17]),\n .I3(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_0 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_49\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [9]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),\n .I2(init_calib_complete_reg_rep__6),\n .I3(\\rd_ptr_reg[3]_1 [16]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_2 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_49__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [22]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3] [16]),\n .I4(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_0 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_49__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [3]),\n .I1(phy_wrdata[27]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_2 [32]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_9 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_49__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [11]),\n .I1(phy_wrdata[27]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_3 [32]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_17 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_49__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [19]),\n .I1(phy_wrdata[27]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_4 [32]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_25 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_49__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [26]),\n .I1(phy_wrdata[26]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_5 [40]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_32 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_4__6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [191]),\n .I1(phy_wrdata[191]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_5 [5]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_37 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_50__0\n (.I0(mc_cas_n),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),\n .I2(init_calib_complete_reg_rep__6),\n .I3(\\rd_ptr_reg[3] [15]),\n .I4(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_0 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_50__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [226]),\n .I1(phy_wrdata[250]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_2 [47]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_8 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_50__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [234]),\n .I1(phy_wrdata[250]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_3 [47]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_16 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_50__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [242]),\n .I1(phy_wrdata[250]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_4 [47]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_24 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_50__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [249]),\n .I1(phy_wrdata[249]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_5 [55]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_31 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_51__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [1]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),\n .I2(init_calib_complete_reg_rep__6),\n .I3(\\rd_ptr_reg[3] [14]),\n .I4(\\my_empty_reg[1] ),\n .O(\\rd_ptr_timing_reg[0]_0 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_51__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [194]),\n .I1(phy_wrdata[218]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_2 [46]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_8 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_51__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [202]),\n .I1(phy_wrdata[218]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_3 [46]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_16 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_51__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [210]),\n .I1(phy_wrdata[218]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_4 [46]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_24 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_51__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [217]),\n .I1(phy_wrdata[217]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_5 [54]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_31 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_52__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [162]),\n .I1(phy_wrdata[186]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_2 [45]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_8 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_52__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [170]),\n .I1(phy_wrdata[186]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_3 [45]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_16 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_52__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [178]),\n .I1(phy_wrdata[186]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_4 [45]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_24 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_52__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [185]),\n .I1(phy_wrdata[185]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_5 [53]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_31 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_53__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [130]),\n .I1(phy_wrdata[154]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_2 [44]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_8 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_53__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [138]),\n .I1(phy_wrdata[154]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_3 [44]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_16 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_53__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [146]),\n .I1(phy_wrdata[154]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_4 [44]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_24 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_53__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [153]),\n .I1(phy_wrdata[153]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_5 [52]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_31 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_54__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [98]),\n .I1(phy_wrdata[122]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_2 [43]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_8 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_54__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [106]),\n .I1(phy_wrdata[122]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_3 [43]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_16 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_54__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [114]),\n .I1(phy_wrdata[122]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_4 [43]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_24 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_54__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [121]),\n .I1(phy_wrdata[121]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_5 [51]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_31 [3]));\n LUT4 #(\n .INIT(16'hEEF0)) \n out_fifo_i_54__4\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),\n .I1(init_calib_complete_reg_rep),\n .I2(\\rd_ptr_reg[3]_1 [23]),\n .I3(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_3 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_55__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [31]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_1 [22]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_3 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_55__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [66]),\n .I1(phy_wrdata[90]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_2 [42]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_8 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_55__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [74]),\n .I1(phy_wrdata[90]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_3 [42]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_16 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_55__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [82]),\n .I1(phy_wrdata[90]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_4 [42]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_24 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_55__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [89]),\n .I1(phy_wrdata[89]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_5 [50]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_31 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_56\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [20]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_1 [21]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_3 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_56__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [34]),\n .I1(phy_wrdata[58]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_2 [41]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_8 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_56__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [42]),\n .I1(phy_wrdata[58]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_3 [41]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_16 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_56__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [50]),\n .I1(phy_wrdata[58]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_4 [41]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_24 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_56__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [57]),\n .I1(phy_wrdata[57]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_5 [49]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_31 [1]));\n LUT4 #(\n .INIT(16'hEEF0)) \n out_fifo_i_56__4\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),\n .I1(init_calib_complete_reg_rep__0),\n .I2(\\rd_ptr_reg[3] [25]),\n .I3(\\my_empty_reg[1] ),\n .O(D7[3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_57\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [10]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),\n .I2(init_calib_complete_reg_rep__6),\n .I3(\\rd_ptr_reg[3]_1 [20]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_3 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_57__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [23]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3] [24]),\n .I4(\\my_empty_reg[1] ),\n .O(D7[2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_57__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [2]),\n .I1(phy_wrdata[26]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_2 [40]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_8 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_57__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [10]),\n .I1(phy_wrdata[26]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_3 [40]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_16 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_57__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [18]),\n .I1(phy_wrdata[26]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_4 [40]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_24 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_57__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [25]),\n .I1(phy_wrdata[25]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_5 [48]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_31 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_58__0\n (.I0(mc_cas_n),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),\n .I2(init_calib_complete_reg_rep__6),\n .I3(\\rd_ptr_reg[3] [23]),\n .I4(\\my_empty_reg[1] ),\n .O(D7[1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_58__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [225]),\n .I1(phy_wrdata[249]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_2 [55]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_7 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_58__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [233]),\n .I1(phy_wrdata[249]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_3 [55]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_15 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_58__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [241]),\n .I1(phy_wrdata[249]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_4 [55]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_23 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_58__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [248]),\n .I1(phy_wrdata[248]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_5 [63]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_30 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_59__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [2]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),\n .I2(init_calib_complete_reg_rep__6),\n .I3(\\rd_ptr_reg[3] [22]),\n .I4(\\my_empty_reg[1] ),\n .O(D7[0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_59__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [193]),\n .I1(phy_wrdata[217]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_2 [54]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_7 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_59__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [201]),\n .I1(phy_wrdata[217]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_3 [54]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_15 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_59__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [209]),\n .I1(phy_wrdata[217]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_4 [54]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_23 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_59__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [216]),\n .I1(phy_wrdata[216]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_5 [62]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_30 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_5__6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [159]),\n .I1(phy_wrdata[159]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_5 [4]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_37 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_60__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [161]),\n .I1(phy_wrdata[185]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_2 [53]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_7 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_60__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [169]),\n .I1(phy_wrdata[185]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_3 [53]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_15 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_60__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [177]),\n .I1(phy_wrdata[185]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_4 [53]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_23 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_60__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [184]),\n .I1(phy_wrdata[184]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_5 [61]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_30 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_61__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [129]),\n .I1(phy_wrdata[153]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_2 [52]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_7 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_61__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [137]),\n .I1(phy_wrdata[153]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_3 [52]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_15 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_61__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [145]),\n .I1(phy_wrdata[153]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_4 [52]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_23 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_61__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [152]),\n .I1(phy_wrdata[152]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_5 [60]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_30 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_62__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [97]),\n .I1(phy_wrdata[121]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_2 [51]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_7 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_62__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [105]),\n .I1(phy_wrdata[121]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_3 [51]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_15 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_62__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [113]),\n .I1(phy_wrdata[121]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_4 [51]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_23 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_62__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [120]),\n .I1(phy_wrdata[120]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_5 [59]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_30 [3]));\n LUT4 #(\n .INIT(16'hEEF0)) \n out_fifo_i_62__4\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ),\n .I1(init_calib_complete_reg_rep),\n .I2(\\rd_ptr_reg[3]_1 [27]),\n .I3(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_4 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_63__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [32]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_1 [26]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_4 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_63__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [65]),\n .I1(phy_wrdata[89]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_2 [50]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_7 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_63__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [73]),\n .I1(phy_wrdata[89]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_3 [50]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_15 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_63__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [81]),\n .I1(phy_wrdata[89]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_4 [50]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_23 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_63__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [88]),\n .I1(phy_wrdata[88]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_5 [58]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_30 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_64\n (.I0(mc_cas_n),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_1 [25]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_4 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_64__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [33]),\n .I1(phy_wrdata[57]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_2 [49]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_7 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_64__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [41]),\n .I1(phy_wrdata[57]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_3 [49]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_15 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_64__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [49]),\n .I1(phy_wrdata[57]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_4 [49]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_23 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_64__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [56]),\n .I1(phy_wrdata[56]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_5 [57]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_30 [1]));\n LUT4 #(\n .INIT(16'hEEF0)) \n out_fifo_i_64__4\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I1(init_calib_complete_reg_rep__0),\n .I2(\\rd_ptr_reg[3] [29]),\n .I3(\\my_empty_reg[1] ),\n .O(D8[3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_65\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [11]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[11] ),\n .I2(init_calib_complete_reg_rep__6),\n .I3(\\rd_ptr_reg[3]_1 [24]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_4 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_65__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [24]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3] [28]),\n .I4(\\my_empty_reg[1] ),\n .O(D8[2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_65__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [1]),\n .I1(phy_wrdata[25]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_2 [48]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_7 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_65__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [9]),\n .I1(phy_wrdata[25]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_3 [48]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_15 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_65__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [17]),\n .I1(phy_wrdata[25]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_4 [48]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_23 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_65__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [24]),\n .I1(phy_wrdata[24]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_5 [56]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_30 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_66__1\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [13]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3] [27]),\n .I4(\\my_empty_reg[1] ),\n .O(D8[1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_66__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [224]),\n .I1(phy_wrdata[248]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_2 [63]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_6 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_66__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [232]),\n .I1(phy_wrdata[248]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_3 [63]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_14 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_66__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [240]),\n .I1(phy_wrdata[248]),\n .I2(init_calib_complete_reg_rep__0),\n .I3(\\rd_ptr_reg[3]_4 [63]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_22 [7]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_67__1\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [3]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),\n .I2(init_calib_complete_reg_rep__6),\n .I3(\\rd_ptr_reg[3] [26]),\n .I4(\\my_empty_reg[1] ),\n .O(D8[0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_67__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [192]),\n .I1(phy_wrdata[216]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_2 [62]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_6 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_67__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [200]),\n .I1(phy_wrdata[216]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_3 [62]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_14 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_67__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [208]),\n .I1(phy_wrdata[216]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_4 [62]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_22 [6]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_68__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [160]),\n .I1(phy_wrdata[184]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_2 [61]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_6 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_68__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [168]),\n .I1(phy_wrdata[184]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_3 [61]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_14 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_68__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [176]),\n .I1(phy_wrdata[184]),\n .I2(init_calib_complete_reg_rep__1),\n .I3(\\rd_ptr_reg[3]_4 [61]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_22 [5]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_69__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [128]),\n .I1(phy_wrdata[152]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_2 [60]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_6 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_69__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [136]),\n .I1(phy_wrdata[152]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_3 [60]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_14 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_69__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [144]),\n .I1(phy_wrdata[152]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_4 [60]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_22 [4]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_6__6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [127]),\n .I1(phy_wrdata[127]),\n .I2(init_calib_complete_reg_rep__2),\n .I3(\\rd_ptr_reg[3]_5 [3]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_37 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_70__0\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [96]),\n .I1(phy_wrdata[120]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_2 [59]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_6 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_70__1\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [104]),\n .I1(phy_wrdata[120]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_3 [59]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_14 [3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_70__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [112]),\n .I1(phy_wrdata[120]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_4 [59]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_22 [3]));\n LUT4 #(\n .INIT(16'hEEF0)) \n out_fifo_i_70__3\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),\n .I1(init_calib_complete_reg_rep),\n .I2(\\rd_ptr_reg[3]_1 [31]),\n .I3(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_5 [3]));\n LUT4 #(\n .INIT(16'hEEF0)) \n out_fifo_i_70__4\n (.I0(phy_bank[10]),\n .I1(init_calib_complete_reg_rep),\n .I2(\\rd_ptr_reg[3] [33]),\n .I3(\\my_empty_reg[1] ),\n .O(D9[3]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_71__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [33]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_1 [30]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_5 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_71__1\n (.I0(\\cmd_pipe_plus.mc_bank_reg[8] [7]),\n .I1(phy_bank[10]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3] [32]),\n .I4(\\my_empty_reg[1] ),\n .O(D9[2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_71__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [64]),\n .I1(phy_wrdata[88]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_2 [58]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_6 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_71__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [72]),\n .I1(phy_wrdata[88]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_3 [58]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_14 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_71__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [80]),\n .I1(phy_wrdata[88]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_4 [58]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_22 [2]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_72__0\n (.I0(mc_ras_n),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_1 [29]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_5 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_72__1\n (.I0(\\cmd_pipe_plus.mc_bank_reg[8] [4]),\n .I1(phy_bank[10]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3] [31]),\n .I4(\\my_empty_reg[1] ),\n .O(D9[1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_72__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [32]),\n .I1(phy_wrdata[56]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_2 [57]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_6 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_72__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [40]),\n .I1(phy_wrdata[56]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_3 [57]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_14 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_72__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [48]),\n .I1(phy_wrdata[56]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_4 [57]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_22 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_73__0\n (.I0(\\cmd_pipe_plus.mc_address_reg[42] [12]),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),\n .I2(init_calib_complete_reg_rep__6),\n .I3(\\rd_ptr_reg[3]_1 [28]),\n .I4(\\my_empty_reg[1]_2 ),\n .O(\\my_empty_reg[7]_5 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_73__1\n (.I0(\\cmd_pipe_plus.mc_bank_reg[8] [1]),\n .I1(phy_bank[10]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3] [30]),\n .I4(\\my_empty_reg[1] ),\n .O(D9[0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_73__2\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [0]),\n .I1(phy_wrdata[24]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_2 [56]),\n .I4(\\my_empty_reg[1]_3 ),\n .O(\\my_empty_reg[7]_6 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_73__3\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [8]),\n .I1(phy_wrdata[24]),\n .I2(init_calib_complete_reg_rep__5),\n .I3(\\rd_ptr_reg[3]_3 [56]),\n .I4(\\my_empty_reg[1]_4 ),\n .O(\\my_empty_reg[7]_14 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_73__4\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [16]),\n .I1(phy_wrdata[24]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_4 [56]),\n .I4(\\my_empty_reg[1]_5 ),\n .O(\\my_empty_reg[7]_22 [0]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_7__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [95]),\n .I1(phy_wrdata[95]),\n .I2(init_calib_complete_reg_rep__3),\n .I3(\\rd_ptr_reg[3]_5 [2]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_37 [2]));\n LUT5 #(\n .INIT(32'hB8B8FF00)) \n out_fifo_i_8__5\n (.I0(mc_cas_n),\n .I1(init_calib_complete_reg_rep__6),\n .I2(phy_cs_n),\n .I3(mem_out[0]),\n .I4(\\my_empty_reg[1]_0 ),\n .O(D0));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_8__6\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [63]),\n .I1(phy_wrdata[63]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_5 [1]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_37 [1]));\n LUT5 #(\n .INIT(32'hACACFF00)) \n out_fifo_i_9__5\n (.I0(\\write_buffer.wr_buf_out_data_reg[255] [31]),\n .I1(phy_wrdata[31]),\n .I2(init_calib_complete_reg_rep__4),\n .I3(\\rd_ptr_reg[3]_5 [0]),\n .I4(\\my_empty_reg[1]_6 ),\n .O(\\my_empty_reg[7]_37 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair591\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\phy_ctl_wd_i1[0]_i_1 \n (.I0(mc_cmd[0]),\n .I1(calib_cmd[0]),\n .I2(init_calib_complete_reg_rep__14),\n .O(\\phy_ctl_wd_i1_reg[24] [0]));\n (* SOFT_HLUTNM = \"soft_lutpair592\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\phy_ctl_wd_i1[17]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_reg[0] ),\n .I1(calib_data_offset_0[0]),\n .I2(init_calib_complete_reg_rep__14),\n .O(\\phy_ctl_wd_i1_reg[24] [3]));\n (* SOFT_HLUTNM = \"soft_lutpair593\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\phy_ctl_wd_i1[18]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_reg[1] ),\n .I1(calib_data_offset_0[1]),\n .I2(init_calib_complete_reg_rep__14),\n .O(\\phy_ctl_wd_i1_reg[24] [4]));\n (* SOFT_HLUTNM = \"soft_lutpair594\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\phy_ctl_wd_i1[19]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_reg[2] ),\n .I1(calib_data_offset_0[2]),\n .I2(init_calib_complete_reg_rep__14),\n .O(\\phy_ctl_wd_i1_reg[24] [5]));\n (* SOFT_HLUTNM = \"soft_lutpair588\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\phy_ctl_wd_i1[1]_i_1 \n (.I0(mc_cmd[1]),\n .I1(calib_cmd[1]),\n .I2(init_calib_complete_reg_rep__14),\n .O(\\phy_ctl_wd_i1_reg[24] [1]));\n (* SOFT_HLUTNM = \"soft_lutpair593\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\phy_ctl_wd_i1[20]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_reg[3] ),\n .I1(calib_data_offset_0[3]),\n .I2(init_calib_complete_reg_rep__14),\n .O(\\phy_ctl_wd_i1_reg[24] [6]));\n (* SOFT_HLUTNM = \"soft_lutpair596\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\phy_ctl_wd_i1[21]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_reg[4] ),\n .I1(calib_data_offset_0[4]),\n .I2(init_calib_complete_reg_rep__14),\n .O(\\phy_ctl_wd_i1_reg[24] [7]));\n (* SOFT_HLUTNM = \"soft_lutpair594\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\phy_ctl_wd_i1[22]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_reg[5] ),\n .I1(calib_data_offset_0[5]),\n .I2(init_calib_complete_reg_rep__14),\n .O(\\phy_ctl_wd_i1_reg[24] [8]));\n (* SOFT_HLUTNM = \"soft_lutpair592\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\phy_ctl_wd_i1[2]_i_1 \n (.I0(mc_cas_n),\n .I1(calib_cmd[2]),\n .I2(init_calib_complete_reg_rep__14),\n .O(\\phy_ctl_wd_i1_reg[24] [2]));\n FDCE phy_reset_n_reg\n (.C(CLK),\n .CE(1'b1),\n .CLR(rstdiv0_sync_r1_reg_rep__11),\n .D(cnt_pwron_reset_done_r),\n .Q(phy_reset_n));\n FDRE pi_calib_done_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_calib_done_r),\n .Q(pi_calib_done),\n .R(1'b0));\n LUT2 #(\n .INIT(4'hE)) \n pi_calib_done_r_i_1\n (.I0(pi_calib_rank_done_r),\n .I1(pi_calib_done_r),\n .O(pi_calib_done_r_i_1_n_0));\n FDRE pi_calib_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_calib_done_r_i_1_n_0),\n .Q(pi_calib_done_r),\n .R(rstdiv0_sync_r1_reg_rep__11));\n LUT2 #(\n .INIT(4'h2)) \n pi_calib_rank_done_r_i_1\n (.I0(pi_phase_locked_all_r3),\n .I1(pi_phase_locked_all_r4),\n .O(init_next_state1100_out));\n FDRE pi_calib_rank_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(init_next_state1100_out),\n .Q(pi_calib_rank_done_r),\n .R(rstdiv0_sync_r1_reg_rep__12));\n LUT2 #(\n .INIT(4'hE)) \n \\pi_dqs_found_all_bank[1]_i_2 \n (.I0(dqs_found_start_r_reg),\n .I1(\\pi_dqs_found_all_bank_reg[1]_0 ),\n .O(\\pi_dqs_found_all_bank_reg[1] ));\n FDRE pi_dqs_found_done_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(dqs_found_done_r_reg),\n .Q(pi_dqs_found_done_r1),\n .R(rstdiv0_sync_r1_reg_rep__11));\n LUT5 #(\n .INIT(32'h000000AE)) \n pi_dqs_found_start_i_1\n (.I0(dqs_found_start_r_reg),\n .I1(\\back_to_back_reads_4_1.num_reads[1]_i_2_n_0 ),\n .I2(dqs_found_done_r_reg),\n .I3(wrlvl_byte_redo),\n .I4(rstdiv0_sync_r1_reg_rep__24),\n .O(pi_dqs_found_start_i_1_n_0));\n FDRE pi_dqs_found_start_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_dqs_found_start_i_1_n_0),\n .Q(dqs_found_start_r_reg),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE pi_phase_locked_all_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(A_rst_primitives_reg),\n .Q(pi_phase_locked_all_r1),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE pi_phase_locked_all_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_phase_locked_all_r1),\n .Q(pi_phase_locked_all_r2),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE pi_phase_locked_all_r3_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_phase_locked_all_r2),\n .Q(pi_phase_locked_all_r3),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE pi_phase_locked_all_r4_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_phase_locked_all_r3),\n .Q(pi_phase_locked_all_r4),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000FFFFEEFE)) \n prbs_gen_clk_en_i_1\n (.I0(prbs_gen_clk_en),\n .I1(prbs_gen_clk_en_i_2_n_0),\n .I2(prbs_rdlvl_start_r_reg),\n .I3(prbs_gen_clk_en_i_3_n_0),\n .I4(\\stg1_wr_rd_cnt[8]_i_4_n_0 ),\n .I5(prbs_gen_clk_en040_out),\n .O(prbs_gen_clk_en_i_1_n_0));\n LUT6 #(\n .INIT(64'h20AAAAAA20AA20AA)) \n prbs_gen_clk_en_i_2\n (.I0(rdlvl_stg1_done_r1),\n .I1(prbs_gen_clk_en_i_5_n_0),\n .I2(\\complex_num_writes[3]_i_4_n_0 ),\n .I3(phy_if_empty_r_reg),\n .I4(\\stg1_wr_rd_cnt[4]_i_6_n_0 ),\n .I5(cnt_cmd_done_r_i_1_n_0),\n .O(prbs_gen_clk_en_i_2_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFEF)) \n prbs_gen_clk_en_i_3\n (.I0(prbs_rdlvl_start_i_2_n_0),\n .I1(Q[4]),\n .I2(Q[3]),\n .I3(Q[5]),\n .I4(Q[2]),\n .I5(\\init_state_r_reg_n_0_[3] ),\n .O(prbs_gen_clk_en_i_3_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair552\" *) \n LUT4 #(\n .INIT(16'hEEEF)) \n prbs_gen_clk_en_i_4\n (.I0(prbs_rdlvl_done_reg),\n .I1(rstdiv0_sync_r1_reg_rep__24),\n .I2(wr_victim_inc_i_2_n_0),\n .I3(\\one_rank.stg1_wr_done_reg_0 ),\n .O(prbs_gen_clk_en040_out));\n (* SOFT_HLUTNM = \"soft_lutpair508\" *) \n LUT4 #(\n .INIT(16'hFF7F)) \n prbs_gen_clk_en_i_5\n (.I0(complex_wait_cnt_reg__0[2]),\n .I1(complex_wait_cnt_reg__0[3]),\n .I2(complex_wait_cnt_reg__0[1]),\n .I3(complex_wait_cnt_reg__0[0]),\n .O(prbs_gen_clk_en_i_5_n_0));\n FDRE prbs_gen_clk_en_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prbs_gen_clk_en_i_1_n_0),\n .Q(prbs_gen_clk_en),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n prbs_gen_oclk_clk_en_i_1\n (.I0(prbs_gen_oclk_clk_en_i_2_n_0),\n .I1(prbs_gen_oclk_clk_en_i_3_n_0),\n .I2(\\one_rank_complex.complex_wr_done_i_3_n_0 ),\n .I3(prbs_gen_oclk_clk_en_i_4_n_0),\n .I4(prbs_gen_oclk_clk_en_i_5_n_0),\n .I5(prbs_gen_clk_en040_out),\n .O(prbs_gen_oclk_clk_en_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFAE)) \n prbs_gen_oclk_clk_en_i_2\n (.I0(prbs_gen_oclk_clk_en_i_6_n_0),\n .I1(prbs_rdlvl_done_r1),\n .I2(phy_if_empty_r_reg),\n .I3(\\stg1_wr_rd_cnt[8]_i_4_n_0 ),\n .I4(prbs_gen_oclk_clk_en_i_7_n_0),\n .I5(prbs_gen_oclk_clk_en),\n .O(prbs_gen_oclk_clk_en_i_2_n_0));\n LUT6 #(\n .INIT(64'h0000000000002000)) \n prbs_gen_oclk_clk_en_i_3\n (.I0(Q[4]),\n .I1(Q[5]),\n .I2(Q[3]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[2]),\n .I5(prbs_rdlvl_start_i_2_n_0),\n .O(prbs_gen_oclk_clk_en_i_3_n_0));\n LUT6 #(\n .INIT(64'h0000000000000008)) \n prbs_gen_oclk_clk_en_i_4\n (.I0(prbs_gen_oclk_clk_en_i_8_n_0),\n .I1(\\complex_num_writes_reg_n_0_[0] ),\n .I2(\\complex_num_writes_reg_n_0_[1] ),\n .I3(\\complex_num_writes_reg_n_0_[2] ),\n .I4(\\complex_num_writes_reg_n_0_[4] ),\n .I5(\\complex_num_writes_reg_n_0_[3] ),\n .O(prbs_gen_oclk_clk_en_i_4_n_0));\n LUT6 #(\n .INIT(64'hAABAAAAAFFFFFFFF)) \n prbs_gen_oclk_clk_en_i_5\n (.I0(prbs_gen_oclk_clk_en_i_9_n_0),\n .I1(complex_num_writes_dec_reg__0[0]),\n .I2(complex_num_writes_dec_reg__0[1]),\n .I3(\\complex_num_writes_dec[4]_i_5_n_0 ),\n .I4(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .I5(complex_ocal_wr_start),\n .O(prbs_gen_oclk_clk_en_i_5_n_0));\n LUT6 #(\n .INIT(64'h0001101100010001)) \n prbs_gen_oclk_clk_en_i_6\n (.I0(complex_oclkdelay_calib_start_int_i_2_n_0),\n .I1(\\init_state_r[4]_i_5_n_0 ),\n .I2(Q[1]),\n .I3(prbs_gen_clk_en_i_5_n_0),\n .I4(Q[0]),\n .I5(complex_oclk_calib_resume),\n .O(prbs_gen_oclk_clk_en_i_6_n_0));\n LUT5 #(\n .INIT(32'h00000004)) \n prbs_gen_oclk_clk_en_i_7\n (.I0(prbs_gen_clk_en_i_5_n_0),\n .I1(\\complex_num_writes[3]_i_4_n_0 ),\n .I2(\\one_rank.stg1_wr_done_reg_0 ),\n .I3(complex_row1_wr_done),\n .I4(complex_ocal_num_samples_done_r),\n .O(prbs_gen_oclk_clk_en_i_7_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair505\" *) \n LUT4 #(\n .INIT(16'h8000)) \n prbs_gen_oclk_clk_en_i_8\n (.I0(complex_wait_cnt_reg__0[0]),\n .I1(complex_wait_cnt_reg__0[1]),\n .I2(complex_wait_cnt_reg__0[2]),\n .I3(complex_wait_cnt_reg__0[3]),\n .O(prbs_gen_oclk_clk_en_i_8_n_0));\n LUT6 #(\n .INIT(64'h0000D00000000000)) \n prbs_gen_oclk_clk_en_i_9\n (.I0(\\stg1_wr_rd_cnt[4]_i_5_n_0 ),\n .I1(complex_oclkdelay_calib_start_int_reg_0),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_17_n_0 ),\n .I3(init_state_r1[2]),\n .I4(init_state_r1[6]),\n .I5(init_state_r1[1]),\n .O(prbs_gen_oclk_clk_en_i_9_n_0));\n FDRE prbs_gen_oclk_clk_en_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prbs_gen_oclk_clk_en_i_1_n_0),\n .Q(prbs_gen_oclk_clk_en),\n .R(1'b0));\n FDRE prbs_last_byte_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prbs_last_byte_done),\n .Q(prbs_last_byte_done_r),\n .R(1'b0));\n FDRE prbs_rdlvl_done_pulse_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prbs_rdlvl_done_pulse0),\n .Q(prbs_rdlvl_done_pulse),\n .R(1'b0));\n FDRE prbs_rdlvl_done_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prbs_rdlvl_done_reg_rep),\n .Q(prbs_rdlvl_done_r1),\n .R(1'b0));\n FDRE prbs_rdlvl_done_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prbs_rdlvl_done_r1),\n .Q(prbs_rdlvl_done_r2),\n .R(1'b0));\n FDRE prbs_rdlvl_done_r3_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prbs_rdlvl_done_r2),\n .Q(prbs_rdlvl_done_r3),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFFFFFFF00000020)) \n prbs_rdlvl_start_i_1\n (.I0(rdlvl_stg1_done_int_reg),\n .I1(prbs_rdlvl_done_reg),\n .I2(dqs_found_done_r_reg),\n .I3(prbs_rdlvl_start_i_2_n_0),\n .I4(prbs_rdlvl_start_i_3_n_0),\n .I5(prbs_rdlvl_start_r_reg),\n .O(prbs_rdlvl_start_i_1_n_0));\n LUT2 #(\n .INIT(4'h7)) \n prbs_rdlvl_start_i_2\n (.I0(Q[0]),\n .I1(Q[1]),\n .O(prbs_rdlvl_start_i_2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair482\" *) \n LUT5 #(\n .INIT(32'hFFFEFFFF)) \n prbs_rdlvl_start_i_3\n (.I0(Q[4]),\n .I1(Q[3]),\n .I2(Q[2]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[5]),\n .O(prbs_rdlvl_start_i_3_n_0));\n FDRE prbs_rdlvl_start_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prbs_rdlvl_start_i_1_n_0),\n .Q(prbs_rdlvl_start_r_reg),\n .R(rstdiv0_sync_r1_reg_rep__12));\n LUT2 #(\n .INIT(4'h2)) \n \\prbs_state_r[4]_i_10 \n (.I0(prbs_rdlvl_start_r_reg),\n .I1(prbs_rdlvl_start_r),\n .O(new_cnt_dqs_r_reg));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done_dly_r_reg \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done_dly_r_reg[15]_srl16 \" *) \n SRL16E \\prech_done_dly_r_reg[15]_srl16 \n (.A0(1'b1),\n .A1(1'b1),\n .A2(1'b1),\n .A3(1'b1),\n .CE(1'b1),\n .CLK(CLK),\n .D(prech_done_pre),\n .Q(\\prech_done_dly_r_reg[15]_srl16_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\prech_done_dly_r_reg[15]_srl16_i_1 \n (.I0(prech_pending_r_reg_1),\n .I1(prech_pending_r_reg_0),\n .O(prech_done_pre));\n FDRE prech_done_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prech_done),\n .Q(prech_done_r2),\n .R(1'b0));\n FDRE prech_done_r3_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prech_done_r2),\n .Q(prech_done_r3),\n .R(1'b0));\n FDRE prech_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\prech_done_dly_r_reg[15]_srl16_n_0 ),\n .Q(prech_done),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hAAAAAA8A8A8A8A8A)) \n prech_pending_r_i_2\n (.I0(prech_pending_r),\n .I1(prech_pending_r_i_3_n_0),\n .I2(prech_pending_r_i_4_n_0),\n .I3(\\complex_row_cnt_ocal[7]_i_6_n_0 ),\n .I4(prech_pending_r_i_5_n_0),\n .I5(prbs_last_byte_done_r),\n .O(prech_pending_r_reg_1));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF5D0000)) \n prech_pending_r_i_3\n (.I0(prech_pending_r_i_6_n_0),\n .I1(\\wrcal_reads[7]_i_6_n_0 ),\n .I2(first_wrcal_pat_r_i_2_n_0),\n .I3(prech_pending_r_i_7_n_0),\n .I4(cnt_cmd_done_r),\n .I5(prech_pending_r_i_8_n_0),\n .O(prech_pending_r_i_3_n_0));\n LUT6 #(\n .INIT(64'h0000FDFFFDFFFDFF)) \n prech_pending_r_i_4\n (.I0(dqs_found_prech_req),\n .I1(\\init_state_r[4]_i_5_n_0 ),\n .I2(rdlvl_stg1_start_int_i_2_n_0),\n .I3(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .I4(\\num_refresh[3]_i_5_n_0 ),\n .I5(complex_oclkdelay_calib_start_r1),\n .O(prech_pending_r_i_4_n_0));\n LUT6 #(\n .INIT(64'h0000000000000008)) \n prech_pending_r_i_5\n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .I1(cnt_cmd_done_r),\n .I2(\\init_state_r[4]_i_5_n_0 ),\n .I3(Q[3]),\n .I4(Q[4]),\n .I5(Q[5]),\n .O(prech_pending_r_i_5_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFDFFFF)) \n prech_pending_r_i_6\n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(Q[2]),\n .I2(rdlvl_start_pre_reg_0),\n .I3(oclkdelay_calib_done_r_reg_2),\n .I4(wrlvl_final_mux),\n .I5(complex_oclkdelay_calib_start_int_reg_0),\n .O(prech_pending_r_i_6_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair492\" *) \n LUT5 #(\n .INIT(32'h00000080)) \n prech_pending_r_i_7\n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(Q[1]),\n .I2(Q[2]),\n .I3(Q[0]),\n .I4(read_calib_i_2_n_0),\n .O(prech_pending_r_i_7_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFEFFFEFFFE)) \n prech_pending_r_i_8\n (.I0(oclkdelay_calib_start_pre),\n .I1(prech_pending_r_i_9_n_0),\n .I2(stg1_wr_done),\n .I3(\\calib_cmd[2]_i_8_n_0 ),\n .I4(prech_pending_r_i_5_n_0),\n .I5(rdlvl_last_byte_done_r),\n .O(prech_pending_r_i_8_n_0));\n LUT6 #(\n .INIT(64'h0000000000040000)) \n prech_pending_r_i_9\n (.I0(prbs_rdlvl_start_i_2_n_0),\n .I1(Q[2]),\n .I2(\\init_state_r_reg_n_0_[3] ),\n .I3(Q[3]),\n .I4(Q[4]),\n .I5(Q[5]),\n .O(prech_pending_r_i_9_n_0));\n FDRE prech_pending_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prech_req_posedge_r_reg_0),\n .Q(prech_pending_r),\n .R(rstdiv0_sync_r1_reg_rep__12));\n LUT2 #(\n .INIT(4'h1)) \n prech_req_posedge_r_i_1\n (.I0(prech_req_r),\n .I1(prech_req_posedge_r_i_2_n_0),\n .O(prech_req_posedge_r0));\n LUT6 #(\n .INIT(64'h000000000000000B)) \n prech_req_posedge_r_i_2\n (.I0(\\back_to_back_reads_4_1.num_reads_reg[1]_0 ),\n .I1(dqs_found_prech_req),\n .I2(prbs_rdlvl_prech_req_reg),\n .I3(complex_ocal_ref_req),\n .I4(wrcal_prech_req),\n .I5(rdlvl_prech_req),\n .O(prech_req_posedge_r_i_2_n_0));\n FDRE prech_req_posedge_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prech_req_posedge_r0),\n .Q(prech_pending_r_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__12));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFEF)) \n prech_req_r_i_3\n (.I0(complex_oclkdelay_calib_start_int_reg_0),\n .I1(Q[4]),\n .I2(Q[3]),\n .I3(Q[5]),\n .I4(Q[2]),\n .I5(\\init_state_r_reg_n_0_[3] ),\n .O(\\back_to_back_reads_4_1.num_reads_reg[1]_0 ));\n FDRE prech_req_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prech_req),\n .Q(prech_req_r),\n .R(rstdiv0_sync_r1_reg_rep__12));\n LUT5 #(\n .INIT(32'h80000000)) \n pwron_ce_r_i_2\n (.I0(cnt_pwron_ce_r_reg__0[9]),\n .I1(cnt_pwron_ce_r_reg__0[7]),\n .I2(pwron_ce_r_i_3_n_0),\n .I3(cnt_pwron_ce_r_reg__0[6]),\n .I4(cnt_pwron_ce_r_reg__0[8]),\n .O(pwron_ce_r_i_2_n_0));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n pwron_ce_r_i_3\n (.I0(cnt_pwron_ce_r_reg__0[5]),\n .I1(cnt_pwron_ce_r_reg__0[3]),\n .I2(cnt_pwron_ce_r_reg__0[1]),\n .I3(cnt_pwron_ce_r_reg__0[0]),\n .I4(cnt_pwron_ce_r_reg__0[2]),\n .I5(cnt_pwron_ce_r_reg__0[4]),\n .O(pwron_ce_r_i_3_n_0));\n FDRE pwron_ce_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pwron_ce_r_i_2_n_0),\n .Q(pwron_ce_r),\n .R(rstdiv0_sync_r1_reg_rep__12));\n LUT6 #(\n .INIT(64'h0000BBB0FFF0FFF0)) \n \\rd_addr[7]_i_2 \n (.I0(prbs_rdlvl_done_reg_rep),\n .I1(prbs_rdlvl_start_r_reg),\n .I2(prbs_gen_clk_en),\n .I3(prbs_gen_oclk_clk_en),\n .I4(complex_wr_done),\n .I5(phy_if_empty_r_reg),\n .O(\\rd_addr_reg[0] ));\n LUT6 #(\n .INIT(64'h959595AAAAAAAAAA)) \n \\rd_addr[7]_i_7 \n (.I0(\\rd_addr_reg[3] ),\n .I1(phy_if_empty_r_reg),\n .I2(complex_wr_done),\n .I3(prbs_gen_oclk_clk_en),\n .I4(prbs_gen_clk_en),\n .I5(prbs_rdlvl_done_reg_rep),\n .O(\\rd_addr_reg_rep[7] ));\n FDRE rdlvl_last_byte_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rdlvl_last_byte_done),\n .Q(rdlvl_last_byte_done_r),\n .R(1'b0));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[13]_srl14 \" *) \n SRL16E \\rdlvl_start_dly0_r_reg[13]_srl14 \n (.A0(1'b1),\n .A1(1'b0),\n .A2(1'b1),\n .A3(1'b1),\n .CE(1'b1),\n .CLK(CLK),\n .D(rdlvl_start_pre),\n .Q(\\rdlvl_start_dly0_r_reg[13]_srl14_n_0 ));\n FDRE \\rdlvl_start_dly0_r_reg[14] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rdlvl_start_dly0_r_reg[13]_srl14_n_0 ),\n .Q(rdlvl_start_dly0_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair585\" *) \n LUT3 #(\n .INIT(8'hFB)) \n rdlvl_start_pre_i_2\n (.I0(Q[4]),\n .I1(Q[3]),\n .I2(Q[5]),\n .O(rdlvl_start_pre_reg_0));\n FDRE rdlvl_start_pre_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\init_state_r_reg[0]_1 ),\n .Q(rdlvl_start_pre),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE rdlvl_stg1_done_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rdlvl_stg1_done_int_reg),\n .Q(rdlvl_stg1_done_r1),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFFFFFFF00000080)) \n rdlvl_stg1_start_int_i_1\n (.I0(dqs_found_done_r_reg),\n .I1(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .I2(cnt_cmd_done_r),\n .I3(\\init_state_r[4]_i_5_n_0 ),\n .I4(rdlvl_stg1_start_int_i_2_n_0),\n .I5(rdlvl_stg1_start_int),\n .O(rdlvl_stg1_start_int_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair572\" *) \n LUT3 #(\n .INIT(8'hFE)) \n rdlvl_stg1_start_int_i_2\n (.I0(Q[3]),\n .I1(Q[4]),\n .I2(Q[5]),\n .O(rdlvl_stg1_start_int_i_2_n_0));\n FDRE rdlvl_stg1_start_int_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rdlvl_stg1_start_int_i_1_n_0),\n .Q(rdlvl_stg1_start_int),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE rdlvl_stg1_start_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\rdlvl_start_dly0_r_reg[14]_0 ),\n .Q(rdlvl_stg1_start_r_reg),\n .R(rstdiv0_sync_r1_reg_rep__12));\n LUT5 #(\n .INIT(32'h000000AB)) \n read_calib_i_1\n (.I0(phy_read_calib),\n .I1(read_calib_i_2_n_0),\n .I2(read_calib_reg_0),\n .I3(pi_calib_done),\n .I4(rstdiv0_sync_r1_reg_rep__24),\n .O(read_calib_i_1_n_0));\n LUT3 #(\n .INIT(8'hFB)) \n read_calib_i_2\n (.I0(Q[3]),\n .I1(Q[4]),\n .I2(Q[5]),\n .O(read_calib_i_2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair507\" *) \n LUT4 #(\n .INIT(16'hFDFF)) \n read_calib_i_3\n (.I0(Q[1]),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .I2(Q[0]),\n .I3(Q[2]),\n .O(read_calib_reg_0));\n FDRE read_calib_reg\n (.C(CLK),\n .CE(1'b1),\n .D(read_calib_i_1_n_0),\n .Q(phy_read_calib),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair610\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\reg_ctrl_cnt_r[0]_i_1 \n (.I0(reg_ctrl_cnt_r_reg__0[0]),\n .O(\\reg_ctrl_cnt_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair610\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\reg_ctrl_cnt_r[1]_i_1 \n (.I0(reg_ctrl_cnt_r_reg__0[0]),\n .I1(reg_ctrl_cnt_r_reg__0[1]),\n .O(p_0_in__2[1]));\n (* SOFT_HLUTNM = \"soft_lutpair586\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\reg_ctrl_cnt_r[2]_i_1 \n (.I0(reg_ctrl_cnt_r_reg__0[2]),\n .I1(reg_ctrl_cnt_r_reg__0[1]),\n .I2(reg_ctrl_cnt_r_reg__0[0]),\n .O(p_0_in__2[2]));\n LUT6 #(\n .INIT(64'h0000000000000001)) \n \\reg_ctrl_cnt_r[3]_i_1 \n (.I0(Q[1]),\n .I1(Q[4]),\n .I2(Q[5]),\n .I3(oclk_calib_resume_level_reg_0),\n .I4(Q[3]),\n .I5(Q[0]),\n .O(\\reg_ctrl_cnt_r_reg[3]_0 ));\n LUT6 #(\n .INIT(64'h0000000001000000)) \n \\reg_ctrl_cnt_r[3]_i_2 \n (.I0(prbs_rdlvl_start_i_2_n_0),\n .I1(Q[2]),\n .I2(Q[4]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[3]),\n .I5(Q[5]),\n .O(reg_ctrl_cnt_r));\n (* SOFT_HLUTNM = \"soft_lutpair562\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\reg_ctrl_cnt_r[3]_i_3 \n (.I0(reg_ctrl_cnt_r_reg__0[3]),\n .I1(reg_ctrl_cnt_r_reg__0[2]),\n .I2(reg_ctrl_cnt_r_reg__0[0]),\n .I3(reg_ctrl_cnt_r_reg__0[1]),\n .O(p_0_in__2[3]));\n FDRE \\reg_ctrl_cnt_r_reg[0] \n (.C(CLK),\n .CE(reg_ctrl_cnt_r),\n .D(\\reg_ctrl_cnt_r[0]_i_1_n_0 ),\n .Q(reg_ctrl_cnt_r_reg__0[0]),\n .R(\\reg_ctrl_cnt_r_reg[3]_0 ));\n FDRE \\reg_ctrl_cnt_r_reg[1] \n (.C(CLK),\n .CE(reg_ctrl_cnt_r),\n .D(p_0_in__2[1]),\n .Q(reg_ctrl_cnt_r_reg__0[1]),\n .R(\\reg_ctrl_cnt_r_reg[3]_0 ));\n FDRE \\reg_ctrl_cnt_r_reg[2] \n (.C(CLK),\n .CE(reg_ctrl_cnt_r),\n .D(p_0_in__2[2]),\n .Q(reg_ctrl_cnt_r_reg__0[2]),\n .R(\\reg_ctrl_cnt_r_reg[3]_0 ));\n FDRE \\reg_ctrl_cnt_r_reg[3] \n (.C(CLK),\n .CE(reg_ctrl_cnt_r),\n .D(p_0_in__2[3]),\n .Q(reg_ctrl_cnt_r_reg__0[3]),\n .R(\\reg_ctrl_cnt_r_reg[3]_0 ));\n LUT3 #(\n .INIT(8'h02)) \n reset_if_i_1\n (.I0(reset_if_i_2_n_0),\n .I1(rstdiv0_sync_r1_reg_rep__25),\n .I2(reset_if_r9),\n .O(reset_if_reg));\n LUT5 #(\n .INIT(32'hFFFF22F2)) \n reset_if_i_2\n (.I0(rdlvl_stg1_done_int_reg),\n .I1(rdlvl_stg1_done_r1),\n .I2(prbs_rdlvl_done_reg),\n .I3(prbs_rdlvl_done_r1),\n .I4(reset_if),\n .O(reset_if_i_2_n_0));\n FDRE reset_rd_addr_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(reset_rd_addr0),\n .Q(reset_rd_addr_r1),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair518\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\row_cnt_victim_rotate.complex_row_cnt[0]_i_1 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),\n .I1(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[0]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8BB8)) \n \\row_cnt_victim_rotate.complex_row_cnt[1]_i_1 \n (.I0(\\rd_victim_sel_reg[0] ),\n .I1(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ),\n .I2(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),\n .I3(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair518\" *) \n LUT5 #(\n .INIT(32'h8BB8B8B8)) \n \\row_cnt_victim_rotate.complex_row_cnt[2]_i_1 \n (.I0(\\rd_victim_sel_reg[1] ),\n .I1(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ),\n .I2(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),\n .I3(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),\n .I4(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8BB8B8B8B8B8B8B8)) \n \\row_cnt_victim_rotate.complex_row_cnt[3]_i_1 \n (.I0(\\rd_victim_sel_reg[2] ),\n .I1(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ),\n .I2(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ),\n .I3(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),\n .I4(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),\n .I5(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hEEEEFFEFAAAAAAAA)) \n \\row_cnt_victim_rotate.complex_row_cnt[4]_i_1 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0 ),\n .I1(reset_rd_addr_r1),\n .I2(complex_sample_cnt_inc_r2),\n .I3(complex_victim_inc_reg),\n .I4(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ),\n .I5(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0 ),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\row_cnt_victim_rotate.complex_row_cnt[4]_i_10 \n (.I0(\\stg1_wr_rd_cnt_reg_n_0_[3] ),\n .I1(\\complex_row_cnt_ocal[7]_i_7_n_0 ),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_10_n_0 ));\n LUT3 #(\n .INIT(8'h0E)) \n \\row_cnt_victim_rotate.complex_row_cnt[4]_i_2 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ),\n .I1(\\one_rank.stg1_wr_done_reg_0 ),\n .I2(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_7_n_0 ),\n .O(complex_row_cnt));\n LUT6 #(\n .INIT(64'h000000007FFF8000)) \n \\row_cnt_victim_rotate.complex_row_cnt[4]_i_3 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),\n .I1(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),\n .I2(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),\n .I3(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ),\n .I4(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),\n .I5(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'hFFFB)) \n \\row_cnt_victim_rotate.complex_row_cnt[4]_i_4 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt_reg[4]_0 ),\n .I1(rdlvl_stg1_done_r1),\n .I2(rstdiv0_sync_r1_reg_rep__24),\n .I3(prbs_rdlvl_done_reg),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h00000001)) \n \\row_cnt_victim_rotate.complex_row_cnt[4]_i_5 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),\n .I1(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ),\n .I2(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ),\n .I3(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ),\n .I4(\\row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 ),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair549\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\row_cnt_victim_rotate.complex_row_cnt[4]_i_6 \n (.I0(\\one_rank.stg1_wr_done_reg_0 ),\n .I1(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_7_n_0 ),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h000000000000000B)) \n \\row_cnt_victim_rotate.complex_row_cnt[4]_i_7 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_10_n_0 ),\n .I1(\\complex_row_cnt_ocal[7]_i_6_n_0 ),\n .I2(reset_rd_addr_r1),\n .I3(complex_victim_inc_reg),\n .I4(wr_victim_inc),\n .I5(complex_sample_cnt_inc_r2),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair549\" *) \n LUT4 #(\n .INIT(16'h4044)) \n \\row_cnt_victim_rotate.complex_row_cnt[4]_i_8 \n (.I0(complex_victim_inc_reg),\n .I1(complex_sample_cnt_inc_r2),\n .I2(\\one_rank.stg1_wr_done_reg_0 ),\n .I3(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'h0000000200000000)) \n \\row_cnt_victim_rotate.complex_row_cnt[4]_i_9 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 ),\n .I1(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ),\n .I2(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ),\n .I3(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ),\n .I4(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),\n .I5(wr_victim_inc),\n .O(\\row_cnt_victim_rotate.complex_row_cnt_reg[4]_0 ));\n LUT6 #(\n .INIT(64'h00000000262A2A2A)) \n \\row_cnt_victim_rotate.complex_row_cnt[5]_i_1 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ),\n .I1(complex_row_cnt),\n .I2(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ),\n .I3(\\row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 ),\n .I4(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),\n .I5(\\row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0 ),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[5]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8000)) \n \\row_cnt_victim_rotate.complex_row_cnt[5]_i_2 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),\n .I1(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),\n .I2(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),\n .I3(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h0000262A)) \n \\row_cnt_victim_rotate.complex_row_cnt[6]_i_1 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ),\n .I1(complex_row_cnt),\n .I2(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ),\n .I3(\\row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0 ),\n .I4(\\row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0 ),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[6]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00000000262A2A2A)) \n \\row_cnt_victim_rotate.complex_row_cnt[7]_i_1 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ),\n .I1(complex_row_cnt),\n .I2(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ),\n .I3(\\row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0 ),\n .I4(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ),\n .I5(\\row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0 ),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\row_cnt_victim_rotate.complex_row_cnt[7]_i_2 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ),\n .I1(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),\n .I2(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),\n .I3(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),\n .I4(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ),\n .I5(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFBBFBAAAAAAAA)) \n \\row_cnt_victim_rotate.complex_row_cnt[7]_i_3 \n (.I0(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0 ),\n .I1(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ),\n .I2(complex_sample_cnt_inc_r2),\n .I3(complex_victim_inc_reg),\n .I4(reset_rd_addr_r1),\n .I5(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0 ),\n .O(\\row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0 ));\n FDRE \\row_cnt_victim_rotate.complex_row_cnt_reg[0] \n (.C(CLK),\n .CE(complex_row_cnt),\n .D(\\row_cnt_victim_rotate.complex_row_cnt[0]_i_1_n_0 ),\n .Q(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),\n .R(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 ));\n FDRE \\row_cnt_victim_rotate.complex_row_cnt_reg[1] \n (.C(CLK),\n .CE(complex_row_cnt),\n .D(\\row_cnt_victim_rotate.complex_row_cnt[1]_i_1_n_0 ),\n .Q(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),\n .R(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 ));\n FDRE \\row_cnt_victim_rotate.complex_row_cnt_reg[2] \n (.C(CLK),\n .CE(complex_row_cnt),\n .D(\\row_cnt_victim_rotate.complex_row_cnt[2]_i_1_n_0 ),\n .Q(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),\n .R(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 ));\n FDRE \\row_cnt_victim_rotate.complex_row_cnt_reg[3] \n (.C(CLK),\n .CE(complex_row_cnt),\n .D(\\row_cnt_victim_rotate.complex_row_cnt[3]_i_1_n_0 ),\n .Q(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ),\n .R(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 ));\n FDRE \\row_cnt_victim_rotate.complex_row_cnt_reg[4] \n (.C(CLK),\n .CE(complex_row_cnt),\n .D(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_3_n_0 ),\n .Q(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),\n .R(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 ));\n FDRE \\row_cnt_victim_rotate.complex_row_cnt_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\row_cnt_victim_rotate.complex_row_cnt[5]_i_1_n_0 ),\n .Q(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ),\n .R(1'b0));\n FDRE \\row_cnt_victim_rotate.complex_row_cnt_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\row_cnt_victim_rotate.complex_row_cnt[6]_i_1_n_0 ),\n .Q(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ),\n .R(1'b0));\n FDRE \\row_cnt_victim_rotate.complex_row_cnt_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0 ),\n .Q(\\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair560\" *) \n LUT2 #(\n .INIT(4'hB)) \n \\samples_cnt_r[11]_i_1 \n (.I0(complex_sample_cnt_inc),\n .I1(\\samples_cnt_r_reg[11]_0 ),\n .O(\\samples_cnt_r_reg[11] ));\n LUT3 #(\n .INIT(8'hBA)) \n \\stg1_wr_rd_cnt[0]_i_1 \n (.I0(\\stg1_wr_rd_cnt[6]_i_2_n_0 ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[0] ),\n .I2(\\stg1_wr_rd_cnt[8]_i_3_n_0 ),\n .O(\\stg1_wr_rd_cnt[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0D00000D0D0D0D0D)) \n \\stg1_wr_rd_cnt[1]_i_1 \n (.I0(stg1_wr_done),\n .I1(rdlvl_stg1_done_int_reg),\n .I2(rstdiv0_sync_r1_reg_rep__24),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[1] ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[0] ),\n .I5(\\stg1_wr_rd_cnt[4]_i_4_n_0 ),\n .O(\\stg1_wr_rd_cnt[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair567\" *) \n LUT4 #(\n .INIT(16'hFD57)) \n \\stg1_wr_rd_cnt[2]_i_1 \n (.I0(\\stg1_wr_rd_cnt[8]_i_3_n_0 ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[1] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[0] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[2] ),\n .O(\\stg1_wr_rd_cnt[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00A8AAA8AAA800A8)) \n \\stg1_wr_rd_cnt[3]_i_1 \n (.I0(rdlvl_stg1_done_int_reg_1),\n .I1(\\stg1_wr_rd_cnt[3]_i_2_n_0 ),\n .I2(prbs_rdlvl_done_reg),\n .I3(\\stg1_wr_rd_cnt[4]_i_4_n_0 ),\n .I4(\\stg1_wr_rd_cnt[5]_i_2_n_0 ),\n .I5(\\stg1_wr_rd_cnt_reg_n_0_[3] ),\n .O(\\stg1_wr_rd_cnt[3]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFD0FF)) \n \\stg1_wr_rd_cnt[3]_i_2 \n (.I0(complex_row0_rd_done),\n .I1(complex_row1_rd_done),\n .I2(complex_row1_wr_done),\n .I3(complex_row0_wr_done),\n .I4(wr_victim_inc),\n .O(\\stg1_wr_rd_cnt[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h88888882AAAAAAAA)) \n \\stg1_wr_rd_cnt[4]_i_1 \n (.I0(rdlvl_stg1_done_int_reg_1),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[4] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[3] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[0] ),\n .I4(\\stg1_wr_rd_cnt[4]_i_3_n_0 ),\n .I5(\\stg1_wr_rd_cnt[4]_i_4_n_0 ),\n .O(\\stg1_wr_rd_cnt[4]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair606\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\stg1_wr_rd_cnt[4]_i_3 \n (.I0(\\stg1_wr_rd_cnt_reg_n_0_[1] ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[2] ),\n .O(\\stg1_wr_rd_cnt[4]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0222022200000222)) \n \\stg1_wr_rd_cnt[4]_i_4 \n (.I0(complex_sample_cnt_inc_i_2_n_0),\n .I1(rdlvl_last_byte_done),\n .I2(\\wrcal_reads[7]_i_6_n_0 ),\n .I3(\\stg1_wr_rd_cnt[4]_i_5_n_0 ),\n .I4(prbs_rdlvl_prech_req_reg),\n .I5(\\stg1_wr_rd_cnt[4]_i_6_n_0 ),\n .O(\\stg1_wr_rd_cnt[4]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair482\" *) \n LUT5 #(\n .INIT(32'h00800000)) \n \\stg1_wr_rd_cnt[4]_i_5 \n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(Q[2]),\n .I2(Q[3]),\n .I3(Q[5]),\n .I4(Q[4]),\n .O(\\stg1_wr_rd_cnt[4]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFF7FFFFFFFF)) \n \\stg1_wr_rd_cnt[4]_i_6 \n (.I0(Q[2]),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .I2(Q[3]),\n .I3(Q[4]),\n .I4(Q[5]),\n .I5(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .O(\\stg1_wr_rd_cnt[4]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hEEEBEEEEAAAAAAAA)) \n \\stg1_wr_rd_cnt[5]_i_1 \n (.I0(\\stg1_wr_rd_cnt[6]_i_2_n_0 ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[5] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[4] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[3] ),\n .I4(\\stg1_wr_rd_cnt[5]_i_2_n_0 ),\n .I5(\\stg1_wr_rd_cnt[8]_i_3_n_0 ),\n .O(\\stg1_wr_rd_cnt[5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair567\" *) \n LUT3 #(\n .INIT(8'h01)) \n \\stg1_wr_rd_cnt[5]_i_2 \n (.I0(\\stg1_wr_rd_cnt_reg_n_0_[0] ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[2] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[1] ),\n .O(\\stg1_wr_rd_cnt[5]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'hFF60)) \n \\stg1_wr_rd_cnt[6]_i_1 \n (.I0(\\stg1_wr_rd_cnt_reg_n_0_[6] ),\n .I1(\\stg1_wr_rd_cnt[8]_i_6_n_0 ),\n .I2(\\stg1_wr_rd_cnt[8]_i_3_n_0 ),\n .I3(\\stg1_wr_rd_cnt[6]_i_2_n_0 ),\n .O(\\stg1_wr_rd_cnt[6]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h00002022)) \n \\stg1_wr_rd_cnt[6]_i_2 \n (.I0(\\stg1_wr_rd_cnt[3]_i_2_n_0 ),\n .I1(rstdiv0_sync_r1_reg_rep__24),\n .I2(rdlvl_stg1_done_int_reg),\n .I3(stg1_wr_done),\n .I4(\\stg1_wr_rd_cnt[4]_i_4_n_0 ),\n .O(\\stg1_wr_rd_cnt[6]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair514\" *) \n LUT4 #(\n .INIT(16'hA208)) \n \\stg1_wr_rd_cnt[7]_i_1 \n (.I0(\\stg1_wr_rd_cnt[8]_i_3_n_0 ),\n .I1(\\stg1_wr_rd_cnt[8]_i_6_n_0 ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[6] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[7] ),\n .O(\\stg1_wr_rd_cnt[7]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hFFD5)) \n \\stg1_wr_rd_cnt[8]_i_1 \n (.I0(\\stg1_wr_rd_cnt[8]_i_3_n_0 ),\n .I1(\\stg1_wr_rd_cnt[8]_i_4_n_0 ),\n .I2(rdlvl_stg1_done_int_reg),\n .I3(\\stg1_wr_rd_cnt[8]_i_5_n_0 ),\n .O(\\stg1_wr_rd_cnt[8]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair514\" *) \n LUT5 #(\n .INIT(32'hA8AA0200)) \n \\stg1_wr_rd_cnt[8]_i_2 \n (.I0(\\stg1_wr_rd_cnt[8]_i_3_n_0 ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[7] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[6] ),\n .I3(\\stg1_wr_rd_cnt[8]_i_6_n_0 ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[8] ),\n .O(\\stg1_wr_rd_cnt[8]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'h00A2)) \n \\stg1_wr_rd_cnt[8]_i_3 \n (.I0(\\stg1_wr_rd_cnt[4]_i_4_n_0 ),\n .I1(stg1_wr_done),\n .I2(rdlvl_stg1_done_int_reg),\n .I3(rstdiv0_sync_r1_reg_rep__24),\n .O(\\stg1_wr_rd_cnt[8]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0000200000000000)) \n \\stg1_wr_rd_cnt[8]_i_4 \n (.I0(Q[4]),\n .I1(Q[5]),\n .I2(Q[3]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[2]),\n .I5(\\wrcal_reads[7]_i_6_n_0 ),\n .O(\\stg1_wr_rd_cnt[8]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000080)) \n \\stg1_wr_rd_cnt[8]_i_5 \n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(Q[1]),\n .I2(Q[2]),\n .I3(Q[0]),\n .I4(\\init_state_r[5]_i_2_n_0 ),\n .I5(Q[3]),\n .O(\\stg1_wr_rd_cnt[8]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000001)) \n \\stg1_wr_rd_cnt[8]_i_6 \n (.I0(\\stg1_wr_rd_cnt_reg_n_0_[3] ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[0] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[2] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[1] ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[4] ),\n .I5(\\stg1_wr_rd_cnt_reg_n_0_[5] ),\n .O(\\stg1_wr_rd_cnt[8]_i_6_n_0 ));\n FDRE \\stg1_wr_rd_cnt_reg[0] \n (.C(CLK),\n .CE(\\stg1_wr_rd_cnt[8]_i_1_n_0 ),\n .D(\\stg1_wr_rd_cnt[0]_i_1_n_0 ),\n .Q(\\stg1_wr_rd_cnt_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\stg1_wr_rd_cnt_reg[1] \n (.C(CLK),\n .CE(\\stg1_wr_rd_cnt[8]_i_1_n_0 ),\n .D(\\stg1_wr_rd_cnt[1]_i_1_n_0 ),\n .Q(\\stg1_wr_rd_cnt_reg_n_0_[1] ),\n .R(1'b0));\n FDRE \\stg1_wr_rd_cnt_reg[2] \n (.C(CLK),\n .CE(\\stg1_wr_rd_cnt[8]_i_1_n_0 ),\n .D(\\stg1_wr_rd_cnt[2]_i_1_n_0 ),\n .Q(\\stg1_wr_rd_cnt_reg_n_0_[2] ),\n .R(1'b0));\n FDRE \\stg1_wr_rd_cnt_reg[3] \n (.C(CLK),\n .CE(\\stg1_wr_rd_cnt[8]_i_1_n_0 ),\n .D(\\stg1_wr_rd_cnt[3]_i_1_n_0 ),\n .Q(\\stg1_wr_rd_cnt_reg_n_0_[3] ),\n .R(1'b0));\n FDRE \\stg1_wr_rd_cnt_reg[4] \n (.C(CLK),\n .CE(\\stg1_wr_rd_cnt[8]_i_1_n_0 ),\n .D(\\stg1_wr_rd_cnt[4]_i_1_n_0 ),\n .Q(\\stg1_wr_rd_cnt_reg_n_0_[4] ),\n .R(1'b0));\n FDRE \\stg1_wr_rd_cnt_reg[5] \n (.C(CLK),\n .CE(\\stg1_wr_rd_cnt[8]_i_1_n_0 ),\n .D(\\stg1_wr_rd_cnt[5]_i_1_n_0 ),\n .Q(\\stg1_wr_rd_cnt_reg_n_0_[5] ),\n .R(1'b0));\n FDRE \\stg1_wr_rd_cnt_reg[6] \n (.C(CLK),\n .CE(\\stg1_wr_rd_cnt[8]_i_1_n_0 ),\n .D(\\stg1_wr_rd_cnt[6]_i_1_n_0 ),\n .Q(\\stg1_wr_rd_cnt_reg_n_0_[6] ),\n .R(1'b0));\n FDRE \\stg1_wr_rd_cnt_reg[7] \n (.C(CLK),\n .CE(\\stg1_wr_rd_cnt[8]_i_1_n_0 ),\n .D(\\stg1_wr_rd_cnt[7]_i_1_n_0 ),\n .Q(\\stg1_wr_rd_cnt_reg_n_0_[7] ),\n .R(1'b0));\n FDRE \\stg1_wr_rd_cnt_reg[8] \n (.C(CLK),\n .CE(\\stg1_wr_rd_cnt[8]_i_1_n_0 ),\n .D(\\stg1_wr_rd_cnt[8]_i_2_n_0 ),\n .Q(\\stg1_wr_rd_cnt_reg_n_0_[8] ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair582\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\victim_sel[0]_i_1 \n (.I0(\\victim_sel[0]_i_2_n_0 ),\n .I1(\\victim_sel[2]_i_3_n_0 ),\n .I2(\\victim_sel_reg_n_0_[0] ),\n .O(\\victim_sel[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\victim_sel[0]_i_2 \n (.I0(complex_ocal_rd_victim_sel[0]),\n .I1(\\rd_victim_sel_reg[0] ),\n .I2(\\victim_sel[2]_i_4_n_0 ),\n .I3(wr_victim_sel_ocal[0]),\n .I4(prbs_rdlvl_done_reg_rep),\n .I5(wr_victim_sel[0]),\n .O(\\victim_sel[0]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair584\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\victim_sel[1]_i_1 \n (.I0(\\victim_sel[1]_i_2_n_0 ),\n .I1(\\victim_sel[2]_i_3_n_0 ),\n .I2(\\victim_sel_reg_n_0_[1] ),\n .O(\\victim_sel[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\victim_sel[1]_i_2 \n (.I0(complex_ocal_rd_victim_sel[1]),\n .I1(\\rd_victim_sel_reg[1] ),\n .I2(\\victim_sel[2]_i_4_n_0 ),\n .I3(wr_victim_sel_ocal[1]),\n .I4(prbs_rdlvl_done_reg_rep),\n .I5(wr_victim_sel[1]),\n .O(\\victim_sel[1]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair582\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\victim_sel[2]_i_1 \n (.I0(\\victim_sel[2]_i_2_n_0 ),\n .I1(\\victim_sel[2]_i_3_n_0 ),\n .I2(\\victim_sel_reg_n_0_[2] ),\n .O(\\victim_sel[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\victim_sel[2]_i_2 \n (.I0(complex_ocal_rd_victim_sel[2]),\n .I1(\\rd_victim_sel_reg[2] ),\n .I2(\\victim_sel[2]_i_4_n_0 ),\n .I3(wr_victim_sel_ocal[2]),\n .I4(prbs_rdlvl_done_reg_rep),\n .I5(wr_victim_sel[2]),\n .O(\\victim_sel[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFBABF)) \n \\victim_sel[2]_i_3 \n (.I0(\\victim_sel[2]_i_5_n_0 ),\n .I1(complex_wr_done),\n .I2(prbs_rdlvl_done_reg),\n .I3(\\one_rank.stg1_wr_done_reg_0 ),\n .I4(reset_rd_addr),\n .I5(complex_ocal_reset_rd_addr),\n .O(\\victim_sel[2]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair574\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\victim_sel[2]_i_4 \n (.I0(complex_wr_done),\n .I1(prbs_rdlvl_done_reg_rep),\n .I2(\\one_rank.stg1_wr_done_reg_0 ),\n .O(\\victim_sel[2]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair516\" *) \n LUT5 #(\n .INIT(32'h00040000)) \n \\victim_sel[2]_i_5 \n (.I0(complex_oclkdelay_calib_start_int_i_2_n_0),\n .I1(Q[2]),\n .I2(Q[0]),\n .I3(\\init_state_r_reg_n_0_[3] ),\n .I4(Q[1]),\n .O(\\victim_sel[2]_i_5_n_0 ));\n FDRE \\victim_sel_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\victim_sel[0]_i_1_n_0 ),\n .Q(\\victim_sel_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE \\victim_sel_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\victim_sel[1]_i_1_n_0 ),\n .Q(\\victim_sel_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__12));\n FDRE \\victim_sel_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\victim_sel[2]_i_1_n_0 ),\n .Q(\\victim_sel_reg_n_0_[2] ),\n .R(rstdiv0_sync_r1_reg_rep__12));\n (* SOFT_HLUTNM = \"soft_lutpair568\" *) \n LUT3 #(\n .INIT(8'h01)) \n \\victim_sel_rotate.sel[24]_i_1 \n (.I0(\\victim_sel_reg_n_0_[2] ),\n .I1(\\victim_sel_reg_n_0_[0] ),\n .I2(\\victim_sel_reg_n_0_[1] ),\n .O(\\victim_sel_rotate.sel_reg[31] [0]));\n (* SOFT_HLUTNM = \"soft_lutpair584\" *) \n LUT3 #(\n .INIT(8'h02)) \n \\victim_sel_rotate.sel[25]_i_1 \n (.I0(\\victim_sel_reg_n_0_[0] ),\n .I1(\\victim_sel_reg_n_0_[2] ),\n .I2(\\victim_sel_reg_n_0_[1] ),\n .O(\\victim_sel_rotate.sel_reg[31] [1]));\n (* SOFT_HLUTNM = \"soft_lutpair587\" *) \n LUT3 #(\n .INIT(8'h02)) \n \\victim_sel_rotate.sel[26]_i_1 \n (.I0(\\victim_sel_reg_n_0_[1] ),\n .I1(\\victim_sel_reg_n_0_[2] ),\n .I2(\\victim_sel_reg_n_0_[0] ),\n .O(\\victim_sel_rotate.sel_reg[31] [2]));\n LUT3 #(\n .INIT(8'h40)) \n \\victim_sel_rotate.sel[27]_i_1 \n (.I0(\\victim_sel_reg_n_0_[2] ),\n .I1(\\victim_sel_reg_n_0_[0] ),\n .I2(\\victim_sel_reg_n_0_[1] ),\n .O(\\victim_sel_rotate.sel_reg[31] [3]));\n (* SOFT_HLUTNM = \"soft_lutpair568\" *) \n LUT3 #(\n .INIT(8'h02)) \n \\victim_sel_rotate.sel[28]_i_1 \n (.I0(\\victim_sel_reg_n_0_[2] ),\n .I1(\\victim_sel_reg_n_0_[0] ),\n .I2(\\victim_sel_reg_n_0_[1] ),\n .O(\\victim_sel_rotate.sel_reg[31] [4]));\n (* SOFT_HLUTNM = \"soft_lutpair571\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\victim_sel_rotate.sel[29]_i_1 \n (.I0(\\victim_sel_reg_n_0_[0] ),\n .I1(\\victim_sel_reg_n_0_[2] ),\n .I2(\\victim_sel_reg_n_0_[1] ),\n .O(\\victim_sel_rotate.sel_reg[31] [5]));\n (* SOFT_HLUTNM = \"soft_lutpair587\" *) \n LUT3 #(\n .INIT(8'h40)) \n \\victim_sel_rotate.sel[30]_i_1 \n (.I0(\\victim_sel_reg_n_0_[0] ),\n .I1(\\victim_sel_reg_n_0_[2] ),\n .I2(\\victim_sel_reg_n_0_[1] ),\n .O(\\victim_sel_rotate.sel_reg[31] [6]));\n (* SOFT_HLUTNM = \"soft_lutpair571\" *) \n LUT3 #(\n .INIT(8'h80)) \n \\victim_sel_rotate.sel[31]_i_1 \n (.I0(\\victim_sel_reg_n_0_[1] ),\n .I1(\\victim_sel_reg_n_0_[0] ),\n .I2(\\victim_sel_reg_n_0_[2] ),\n .O(\\victim_sel_rotate.sel_reg[31] [7]));\n FDRE wl_sm_start_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wr_level_dqs_asrt_r1),\n .Q(wl_sm_start),\n .R(rstdiv0_sync_r1_reg_rep__11));\n (* SOFT_HLUTNM = \"soft_lutpair545\" *) \n LUT4 #(\n .INIT(16'h00AE)) \n \\wr_done_victim_rotate.complex_row0_wr_done_i_1 \n (.I0(complex_row0_wr_done),\n .I1(rdlvl_stg1_done_r1),\n .I2(wr_victim_inc_i_2_n_0),\n .I3(complex_row0_wr_done0),\n .O(\\wr_done_victim_rotate.complex_row0_wr_done_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFEEFEEEEEEEEE)) \n \\wr_done_victim_rotate.complex_row0_wr_done_i_2 \n (.I0(complex_row0_rd_done1),\n .I1(complex_byte_rd_done),\n .I2(\\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ),\n .I3(prbs_rdlvl_done_reg),\n .I4(\\complex_row_cnt_ocal[7]_i_5_n_0 ),\n .I5(wr_victim_inc),\n .O(complex_row0_wr_done0));\n FDRE \\wr_done_victim_rotate.complex_row0_wr_done_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_done_victim_rotate.complex_row0_wr_done_i_1_n_0 ),\n .Q(complex_row0_wr_done),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair545\" *) \n LUT4 #(\n .INIT(16'h00AE)) \n \\wr_done_victim_rotate.complex_row1_wr_done_i_1 \n (.I0(complex_row1_wr_done),\n .I1(complex_row0_wr_done),\n .I2(wr_victim_inc_i_2_n_0),\n .I3(complex_row0_wr_done0),\n .O(\\wr_done_victim_rotate.complex_row1_wr_done_i_1_n_0 ));\n FDRE \\wr_done_victim_rotate.complex_row1_wr_done_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_done_victim_rotate.complex_row1_wr_done_i_1_n_0 ),\n .Q(complex_row1_wr_done),\n .R(1'b0));\n LUT4 #(\n .INIT(16'h00E0)) \n wr_level_dqs_asrt_i_1\n (.I0(wr_level_dqs_asrt),\n .I1(wrlvl_active_r1),\n .I2(\\en_cnt_div4.wrlvl_odt_i_2_n_0 ),\n .I3(rstdiv0_sync_r1_reg_rep__25),\n .O(wr_level_dqs_asrt_i_1_n_0));\n FDRE wr_level_dqs_asrt_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wr_level_dqs_asrt),\n .Q(wr_level_dqs_asrt_r1),\n .R(1'b0));\n FDRE wr_level_dqs_asrt_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wr_level_dqs_asrt_i_1_n_0),\n .Q(wr_level_dqs_asrt),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h0000EA00)) \n wr_lvl_start_i_1\n (.I0(wr_level_start_r_reg),\n .I1(dqs_asrt_cnt[0]),\n .I2(dqs_asrt_cnt[1]),\n .I3(wrlvl_active),\n .I4(rstdiv0_sync_r1_reg_rep__24),\n .O(wr_lvl_start_i_1_n_0));\n FDRE wr_lvl_start_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wr_lvl_start_i_1_n_0),\n .Q(wr_level_start_r_reg),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair569\" *) \n LUT2 #(\n .INIT(4'hE)) \n wr_ptr0_i_1\n (.I0(init_calib_complete_reg_rep__14),\n .I1(calib_ctl_wren),\n .O(mux_cmd_wren));\n (* SOFT_HLUTNM = \"soft_lutpair569\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\wr_ptr[3]_i_3 \n (.I0(mc_wrdata_en),\n .I1(init_calib_complete_reg_rep__14),\n .I2(calib_wrdata_en),\n .O(mux_wrdata_en));\n (* SOFT_HLUTNM = \"soft_lutpair552\" *) \n LUT3 #(\n .INIT(8'h04)) \n wr_victim_inc_i_1\n (.I0(wr_victim_inc_i_2_n_0),\n .I1(complex_row0_wr_done),\n .I2(\\one_rank.stg1_wr_done_reg_0 ),\n .O(wr_victim_inc0));\n (* SOFT_HLUTNM = \"soft_lutpair503\" *) \n LUT5 #(\n .INIT(32'hFFFFFEFF)) \n wr_victim_inc_i_2\n (.I0(wr_victim_inc_i_3_n_0),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[5] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[0] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[1] ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[2] ),\n .O(wr_victim_inc_i_2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair517\" *) \n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n wr_victim_inc_i_3\n (.I0(\\stg1_wr_rd_cnt_reg_n_0_[3] ),\n .I1(\\stg1_wr_rd_cnt_reg_n_0_[4] ),\n .I2(\\stg1_wr_rd_cnt_reg_n_0_[8] ),\n .I3(\\stg1_wr_rd_cnt_reg_n_0_[7] ),\n .I4(\\stg1_wr_rd_cnt_reg_n_0_[6] ),\n .O(wr_victim_inc_i_3_n_0));\n FDRE wr_victim_inc_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wr_victim_inc0),\n .Q(wr_victim_inc),\n .R(rstdiv0_sync_r1_reg_rep__12));\n (* SOFT_HLUTNM = \"soft_lutpair530\" *) \n LUT4 #(\n .INIT(16'h006A)) \n \\wr_victim_sel[0]_i_1 \n (.I0(wr_victim_sel[0]),\n .I1(wr_victim_inc),\n .I2(rdlvl_stg1_done_r1),\n .I3(p_81_in),\n .O(\\wr_victim_sel[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair530\" *) \n LUT5 #(\n .INIT(32'h00006AAA)) \n \\wr_victim_sel[1]_i_1 \n (.I0(wr_victim_sel[1]),\n .I1(wr_victim_inc),\n .I2(rdlvl_stg1_done_r1),\n .I3(wr_victim_sel[0]),\n .I4(p_81_in),\n .O(\\wr_victim_sel[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h000000006AAAAAAA)) \n \\wr_victim_sel[2]_i_1 \n (.I0(wr_victim_sel[2]),\n .I1(wr_victim_inc),\n .I2(rdlvl_stg1_done_r1),\n .I3(wr_victim_sel[1]),\n .I4(wr_victim_sel[0]),\n .I5(p_81_in),\n .O(\\wr_victim_sel[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair531\" *) \n LUT4 #(\n .INIT(16'h006A)) \n \\wr_victim_sel_ocal[0]_i_1 \n (.I0(wr_victim_sel_ocal[0]),\n .I1(prbs_rdlvl_done_reg),\n .I2(wr_victim_inc),\n .I3(rstdiv0_sync_r1_reg_rep__24_1),\n .O(\\wr_victim_sel_ocal[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair531\" *) \n LUT5 #(\n .INIT(32'h00006AAA)) \n \\wr_victim_sel_ocal[1]_i_1 \n (.I0(wr_victim_sel_ocal[1]),\n .I1(prbs_rdlvl_done_reg),\n .I2(wr_victim_inc),\n .I3(wr_victim_sel_ocal[0]),\n .I4(rstdiv0_sync_r1_reg_rep__24_1),\n .O(\\wr_victim_sel_ocal[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h000000006AAAAAAA)) \n \\wr_victim_sel_ocal[2]_i_1 \n (.I0(wr_victim_sel_ocal[2]),\n .I1(prbs_rdlvl_done_reg),\n .I2(wr_victim_inc),\n .I3(wr_victim_sel_ocal[1]),\n .I4(wr_victim_sel_ocal[0]),\n .I5(rstdiv0_sync_r1_reg_rep__24_1),\n .O(\\wr_victim_sel_ocal[2]_i_1_n_0 ));\n FDRE \\wr_victim_sel_ocal_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_victim_sel_ocal[0]_i_1_n_0 ),\n .Q(wr_victim_sel_ocal[0]),\n .R(1'b0));\n FDRE \\wr_victim_sel_ocal_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_victim_sel_ocal[1]_i_1_n_0 ),\n .Q(wr_victim_sel_ocal[1]),\n .R(1'b0));\n FDRE \\wr_victim_sel_ocal_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_victim_sel_ocal[2]_i_1_n_0 ),\n .Q(wr_victim_sel_ocal[2]),\n .R(1'b0));\n FDRE \\wr_victim_sel_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_victim_sel[0]_i_1_n_0 ),\n .Q(wr_victim_sel[0]),\n .R(1'b0));\n FDRE \\wr_victim_sel_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_victim_sel[1]_i_1_n_0 ),\n .Q(wr_victim_sel[1]),\n .R(1'b0));\n FDRE \\wr_victim_sel_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_victim_sel[2]_i_1_n_0 ),\n .Q(wr_victim_sel[2]),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h2)) \n \\wrcal_dqs_cnt_r[2]_i_5 \n (.I0(wrcal_sanity_chk),\n .I1(wrcal_sanity_chk_r_reg),\n .O(\\wrcal_dqs_cnt_r_reg[0] ));\n LUT5 #(\n .INIT(32'hFFFF0080)) \n wrcal_final_chk_i_1\n (.I0(\\init_state_r[1]_i_1_n_0 ),\n .I1(\\init_state_r[0]_i_1_n_0 ),\n .I2(\\init_state_r[4]_i_1_n_0 ),\n .I3(wrcal_final_chk_i_2_n_0),\n .I4(wrcal_final_chk),\n .O(wrcal_final_chk_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair484\" *) \n LUT5 #(\n .INIT(32'hFFFFFFDF)) \n wrcal_final_chk_i_2\n (.I0(\\init_state_r[2]_i_1_n_0 ),\n .I1(\\init_state_r[5]_i_1_n_0 ),\n .I2(wrcal_done_reg_10),\n .I3(\\init_state_r[3]_i_2_n_0 ),\n .I4(\\init_state_r[6]_i_1_n_0 ),\n .O(wrcal_final_chk_i_2_n_0));\n FDRE wrcal_final_chk_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrcal_final_chk_i_1_n_0),\n .Q(wrcal_final_chk),\n .R(rstdiv0_sync_r1_reg_rep__11));\n LUT6 #(\n .INIT(64'h0000000000100000)) \n wrcal_rd_wait_i_1\n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(\\wrcal_reads[7]_i_5_n_0 ),\n .I3(Q[5]),\n .I4(Q[4]),\n .I5(Q[3]),\n .O(wrcal_rd_wait_i_1_n_0));\n FDRE wrcal_rd_wait_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrcal_rd_wait_i_1_n_0),\n .Q(wrcal_rd_wait),\n .R(rstdiv0_sync_r1_reg_rep__12));\n (* SOFT_HLUTNM = \"soft_lutpair540\" *) \n LUT2 #(\n .INIT(4'hB)) \n \\wrcal_reads[0]_i_1 \n (.I0(wrcal_reads),\n .I1(\\wrcal_reads_reg_n_0_[0] ),\n .O(\\wrcal_reads[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair576\" *) \n LUT3 #(\n .INIT(8'hF9)) \n \\wrcal_reads[1]_i_1 \n (.I0(\\wrcal_reads_reg_n_0_[0] ),\n .I1(\\wrcal_reads_reg_n_0_[1] ),\n .I2(wrcal_reads),\n .O(\\wrcal_reads[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair499\" *) \n LUT4 #(\n .INIT(16'hFFE1)) \n \\wrcal_reads[2]_i_1 \n (.I0(\\wrcal_reads_reg_n_0_[1] ),\n .I1(\\wrcal_reads_reg_n_0_[0] ),\n .I2(\\wrcal_reads_reg_n_0_[2] ),\n .I3(wrcal_reads),\n .O(\\wrcal_reads[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair499\" *) \n LUT5 #(\n .INIT(32'hFFFFFE01)) \n \\wrcal_reads[3]_i_1 \n (.I0(\\wrcal_reads_reg_n_0_[0] ),\n .I1(\\wrcal_reads_reg_n_0_[1] ),\n .I2(\\wrcal_reads_reg_n_0_[2] ),\n .I3(\\wrcal_reads_reg_n_0_[3] ),\n .I4(wrcal_reads),\n .O(\\wrcal_reads[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFE0001)) \n \\wrcal_reads[4]_i_1 \n (.I0(\\wrcal_reads_reg_n_0_[3] ),\n .I1(\\wrcal_reads_reg_n_0_[2] ),\n .I2(\\wrcal_reads_reg_n_0_[1] ),\n .I3(\\wrcal_reads_reg_n_0_[0] ),\n .I4(\\wrcal_reads_reg_n_0_[4] ),\n .I5(wrcal_reads),\n .O(\\wrcal_reads[4]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair576\" *) \n LUT3 #(\n .INIT(8'hF6)) \n \\wrcal_reads[5]_i_1 \n (.I0(\\wrcal_reads[5]_i_2_n_0 ),\n .I1(\\wrcal_reads_reg_n_0_[5] ),\n .I2(wrcal_reads),\n .O(\\wrcal_reads[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h00000001)) \n \\wrcal_reads[5]_i_2 \n (.I0(\\wrcal_reads_reg_n_0_[4] ),\n .I1(\\wrcal_reads_reg_n_0_[0] ),\n .I2(\\wrcal_reads_reg_n_0_[1] ),\n .I3(\\wrcal_reads_reg_n_0_[2] ),\n .I4(\\wrcal_reads_reg_n_0_[3] ),\n .O(\\wrcal_reads[5]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair542\" *) \n LUT3 #(\n .INIT(8'hF6)) \n \\wrcal_reads[6]_i_1 \n (.I0(\\wrcal_reads[7]_i_7_n_0 ),\n .I1(\\wrcal_reads_reg_n_0_[6] ),\n .I2(wrcal_reads),\n .O(\\wrcal_reads[6]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAABAAAAAAAAAAAAA)) \n \\wrcal_reads[7]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__24),\n .I1(Q[3]),\n .I2(Q[4]),\n .I3(Q[5]),\n .I4(\\wrcal_reads[7]_i_5_n_0 ),\n .I5(\\wrcal_reads[7]_i_6_n_0 ),\n .O(wrcal_reads05_out));\n LUT4 #(\n .INIT(16'hFFFD)) \n \\wrcal_reads[7]_i_2 \n (.I0(\\wrcal_reads[7]_i_7_n_0 ),\n .I1(\\wrcal_reads_reg_n_0_[6] ),\n .I2(\\wrcal_reads_reg_n_0_[7] ),\n .I3(wrcal_reads),\n .O(\\wrcal_reads[7]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair542\" *) \n LUT4 #(\n .INIT(16'hFFD2)) \n \\wrcal_reads[7]_i_3 \n (.I0(\\wrcal_reads[7]_i_7_n_0 ),\n .I1(\\wrcal_reads_reg_n_0_[6] ),\n .I2(\\wrcal_reads_reg_n_0_[7] ),\n .I3(wrcal_reads),\n .O(\\wrcal_reads[7]_i_3_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\wrcal_reads[7]_i_5 \n (.I0(Q[2]),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .O(\\wrcal_reads[7]_i_5_n_0 ));\n LUT2 #(\n .INIT(4'h1)) \n \\wrcal_reads[7]_i_6 \n (.I0(Q[0]),\n .I1(Q[1]),\n .O(\\wrcal_reads[7]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000001)) \n \\wrcal_reads[7]_i_7 \n (.I0(\\wrcal_reads_reg_n_0_[3] ),\n .I1(\\wrcal_reads_reg_n_0_[2] ),\n .I2(\\wrcal_reads_reg_n_0_[1] ),\n .I3(\\wrcal_reads_reg_n_0_[0] ),\n .I4(\\wrcal_reads_reg_n_0_[4] ),\n .I5(\\wrcal_reads_reg_n_0_[5] ),\n .O(\\wrcal_reads[7]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000004000)) \n \\wrcal_reads[7]_i_8 \n (.I0(read_calib_i_2_n_0),\n .I1(\\wrcal_reads[7]_i_5_n_0 ),\n .I2(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .I3(\\wrcal_reads[7]_i_7_n_0 ),\n .I4(\\wrcal_reads_reg_n_0_[6] ),\n .I5(\\wrcal_reads_reg_n_0_[7] ),\n .O(wrcal_reads));\n FDRE \\wrcal_reads_reg[0] \n (.C(CLK),\n .CE(\\wrcal_reads[7]_i_2_n_0 ),\n .D(\\wrcal_reads[0]_i_1_n_0 ),\n .Q(\\wrcal_reads_reg_n_0_[0] ),\n .R(wrcal_reads05_out));\n FDRE \\wrcal_reads_reg[1] \n (.C(CLK),\n .CE(\\wrcal_reads[7]_i_2_n_0 ),\n .D(\\wrcal_reads[1]_i_1_n_0 ),\n .Q(\\wrcal_reads_reg_n_0_[1] ),\n .R(wrcal_reads05_out));\n FDRE \\wrcal_reads_reg[2] \n (.C(CLK),\n .CE(\\wrcal_reads[7]_i_2_n_0 ),\n .D(\\wrcal_reads[2]_i_1_n_0 ),\n .Q(\\wrcal_reads_reg_n_0_[2] ),\n .R(wrcal_reads05_out));\n FDRE \\wrcal_reads_reg[3] \n (.C(CLK),\n .CE(\\wrcal_reads[7]_i_2_n_0 ),\n .D(\\wrcal_reads[3]_i_1_n_0 ),\n .Q(\\wrcal_reads_reg_n_0_[3] ),\n .R(wrcal_reads05_out));\n FDRE \\wrcal_reads_reg[4] \n (.C(CLK),\n .CE(\\wrcal_reads[7]_i_2_n_0 ),\n .D(\\wrcal_reads[4]_i_1_n_0 ),\n .Q(\\wrcal_reads_reg_n_0_[4] ),\n .R(wrcal_reads05_out));\n FDRE \\wrcal_reads_reg[5] \n (.C(CLK),\n .CE(\\wrcal_reads[7]_i_2_n_0 ),\n .D(\\wrcal_reads[5]_i_1_n_0 ),\n .Q(\\wrcal_reads_reg_n_0_[5] ),\n .R(wrcal_reads05_out));\n FDRE \\wrcal_reads_reg[6] \n (.C(CLK),\n .CE(\\wrcal_reads[7]_i_2_n_0 ),\n .D(\\wrcal_reads[6]_i_1_n_0 ),\n .Q(\\wrcal_reads_reg_n_0_[6] ),\n .R(wrcal_reads05_out));\n FDRE \\wrcal_reads_reg[7] \n (.C(CLK),\n .CE(\\wrcal_reads[7]_i_2_n_0 ),\n .D(\\wrcal_reads[7]_i_3_n_0 ),\n .Q(\\wrcal_reads_reg_n_0_[7] ),\n .R(wrcal_reads05_out));\n FDRE wrcal_resume_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrcal_resume_w),\n .Q(wrcal_resume_r),\n .R(1'b0));\n FDRE wrcal_sanity_chk_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrcal_final_chk),\n .Q(wrcal_sanity_chk),\n .R(1'b0));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_start_dly_r_reg \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_start_dly_r_reg[4]_srl5 \" *) \n SRL16E \\wrcal_start_dly_r_reg[4]_srl5 \n (.A0(1'b0),\n .A1(1'b0),\n .A2(1'b1),\n .A3(1'b0),\n .CE(1'b1),\n .CLK(CLK),\n .D(wrcal_start_pre),\n .Q(\\wrcal_start_dly_r_reg[4]_srl5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair492\" *) \n LUT5 #(\n .INIT(32'h01000400)) \n \\wrcal_start_dly_r_reg[4]_srl5_i_1 \n (.I0(\\init_state_r_reg_n_0_[3] ),\n .I1(Q[2]),\n .I2(read_calib_i_2_n_0),\n .I3(Q[0]),\n .I4(Q[1]),\n .O(wrcal_start_pre));\n FDRE \\wrcal_start_dly_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wrcal_start_dly_r_reg[4]_srl5_n_0 ),\n .Q(wrcal_start_dly_r),\n .R(1'b0));\n LUT4 #(\n .INIT(16'h000E)) \n wrcal_start_i_1\n (.I0(wrcal_start_reg_0),\n .I1(wrcal_start_dly_r),\n .I2(wrlvl_byte_redo),\n .I3(rstdiv0_sync_r1_reg_rep__24),\n .O(wrcal_start_i_1_n_0));\n FDRE wrcal_start_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrcal_start_i_1_n_0),\n .Q(wrcal_start_reg_0),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair613\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\wrcal_wr_cnt[0]_i_1 \n (.I0(wrcal_wr_cnt_reg__0[0]),\n .O(\\wrcal_wr_cnt[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair613\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\wrcal_wr_cnt[1]_i_1 \n (.I0(wrcal_wr_cnt_reg__0[0]),\n .I1(wrcal_wr_cnt_reg__0[1]),\n .O(\\wrcal_wr_cnt[1]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hA9)) \n \\wrcal_wr_cnt[2]_i_1 \n (.I0(wrcal_wr_cnt_reg__0[2]),\n .I1(wrcal_wr_cnt_reg__0[1]),\n .I2(wrcal_wr_cnt_reg__0[0]),\n .O(wrcal_wr_cnt0[2]));\n LUT6 #(\n .INIT(64'hFFFFFFFF111111F1)) \n \\wrcal_wr_cnt[3]_i_1 \n (.I0(first_wrcal_pat_r_i_2_n_0),\n .I1(complex_oclkdelay_calib_start_int_reg_0),\n .I2(\\wrcal_wr_cnt[3]_i_4_n_0 ),\n .I3(wrcal_wr_cnt_reg__0[3]),\n .I4(wrcal_wr_cnt_reg__0[2]),\n .I5(rstdiv0_sync_r1_reg_rep__24),\n .O(\\wrcal_wr_cnt[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000020)) \n \\wrcal_wr_cnt[3]_i_2 \n (.I0(\\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),\n .I1(Q[3]),\n .I2(Q[4]),\n .I3(Q[5]),\n .I4(Q[2]),\n .I5(\\init_state_r_reg_n_0_[3] ),\n .O(\\wrcal_wr_cnt[3]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair564\" *) \n LUT4 #(\n .INIT(16'hCCC9)) \n \\wrcal_wr_cnt[3]_i_3 \n (.I0(wrcal_wr_cnt_reg__0[2]),\n .I1(wrcal_wr_cnt_reg__0[3]),\n .I2(wrcal_wr_cnt_reg__0[0]),\n .I3(wrcal_wr_cnt_reg__0[1]),\n .O(wrcal_wr_cnt0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair564\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\wrcal_wr_cnt[3]_i_4 \n (.I0(wrcal_wr_cnt_reg__0[0]),\n .I1(wrcal_wr_cnt_reg__0[1]),\n .O(\\wrcal_wr_cnt[3]_i_4_n_0 ));\n FDRE \\wrcal_wr_cnt_reg[0] \n (.C(CLK),\n .CE(\\wrcal_wr_cnt[3]_i_2_n_0 ),\n .D(\\wrcal_wr_cnt[0]_i_1_n_0 ),\n .Q(wrcal_wr_cnt_reg__0[0]),\n .R(\\wrcal_wr_cnt[3]_i_1_n_0 ));\n FDRE \\wrcal_wr_cnt_reg[1] \n (.C(CLK),\n .CE(\\wrcal_wr_cnt[3]_i_2_n_0 ),\n .D(\\wrcal_wr_cnt[1]_i_1_n_0 ),\n .Q(wrcal_wr_cnt_reg__0[1]),\n .R(\\wrcal_wr_cnt[3]_i_1_n_0 ));\n FDSE \\wrcal_wr_cnt_reg[2] \n (.C(CLK),\n .CE(\\wrcal_wr_cnt[3]_i_2_n_0 ),\n .D(wrcal_wr_cnt0[2]),\n .Q(wrcal_wr_cnt_reg__0[2]),\n .S(\\wrcal_wr_cnt[3]_i_1_n_0 ));\n FDRE \\wrcal_wr_cnt_reg[3] \n (.C(CLK),\n .CE(\\wrcal_wr_cnt[3]_i_2_n_0 ),\n .D(wrcal_wr_cnt0[3]),\n .Q(wrcal_wr_cnt_reg__0[3]),\n .R(\\wrcal_wr_cnt[3]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h2F)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1 \n (.I0(first_wrcal_pat_r),\n .I1(wrcal_done_reg_10),\n .I2(oclkdelay_calib_done_r_reg_2),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFAFF3AFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[250]_i_1 \n (.I0(first_wrcal_pat_r),\n .I1(rdlvl_stg1_done_int_reg),\n .I2(wrcal_done_reg_10),\n .I3(oclkdelay_calib_done_r_reg_2),\n .I4(\\dout_o_reg[0]_0 ),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata[250]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFAFF3AFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[254]_i_2 \n (.I0(first_wrcal_pat_r),\n .I1(rdlvl_stg1_done_int_reg),\n .I2(wrcal_done_reg_10),\n .I3(oclkdelay_calib_done_r_reg_2),\n .I4(\\dout_o_reg[0] ),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata[254]_i_2_n_0 ));\n FDSE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[120] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[12]_0 ),\n .Q(phy_wrdata[120]),\n .S(\\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 ));\n FDSE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[121] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(wrcal_done_reg_8),\n .Q(phy_wrdata[121]),\n .S(wrcal_done_reg_0));\n FDSE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[122] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[4]_0 ),\n .Q(phy_wrdata[122]),\n .S(wrcal_done_reg_2));\n FDSE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[123] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(wrcal_done_reg_7),\n .Q(phy_wrdata[123]),\n .S(wrcal_done_reg_0));\n FDSE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[124] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[12] ),\n .Q(phy_wrdata[124]),\n .S(\\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 ));\n FDSE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[125] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(wrcal_done_reg_6),\n .Q(phy_wrdata[125]),\n .S(wrcal_done_reg_0));\n FDSE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[126] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[4] ),\n .Q(phy_wrdata[126]),\n .S(wrcal_done_reg_2));\n FDSE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[127] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(wrcal_done_reg_5),\n .Q(phy_wrdata[127]),\n .S(wrcal_done_reg_0));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[152] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[3]_0 ),\n .Q(phy_wrdata[152]),\n .R(wrcal_done_reg_1));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[153] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[11]_0 ),\n .Q(phy_wrdata[153]),\n .R(1'b0));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[154] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[11]_4 ),\n .Q(phy_wrdata[154]),\n .R(oclkdelay_calib_done_r_reg_1));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[155] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[11]_2 ),\n .Q(phy_wrdata[155]),\n .R(wrcal_done_reg));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[156] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[3] ),\n .Q(phy_wrdata[156]),\n .R(wrcal_done_reg_1));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[157] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[11] ),\n .Q(phy_wrdata[157]),\n .R(1'b0));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[158] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[11]_3 ),\n .Q(phy_wrdata[158]),\n .R(oclkdelay_calib_done_r_reg_1));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[159] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[11]_1 ),\n .Q(phy_wrdata[159]),\n .R(wrcal_done_reg));\n FDSE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[184] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(wrcal_done_reg_4),\n .Q(phy_wrdata[184]),\n .S(wrcal_done_reg_0));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[185] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(oclkdelay_calib_done_r_reg_0),\n .Q(phy_wrdata[185]),\n .R(1'b0));\n FDSE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[10]_0 ),\n .Q(phy_wrdata[186]),\n .S(wrcal_done_reg_1));\n FDSE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[2]_0 ),\n .Q(phy_wrdata[187]),\n .S(wrcal_done_reg_2));\n FDSE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[188] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(wrcal_done_reg_3),\n .Q(phy_wrdata[188]),\n .S(wrcal_done_reg_0));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[189] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(oclkdelay_calib_done_r_reg),\n .Q(phy_wrdata[189]),\n .R(1'b0));\n FDSE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[190] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[10] ),\n .Q(phy_wrdata[190]),\n .S(wrcal_done_reg_1));\n FDSE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[2] ),\n .Q(phy_wrdata[191]),\n .S(wrcal_done_reg_2));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[216] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[9]_4 ),\n .Q(phy_wrdata[216]),\n .R(wrcal_done_reg_0));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[217] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[9]_0 ),\n .Q(phy_wrdata[217]),\n .R(wrcal_done_reg));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[218] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[1]_0 ),\n .Q(phy_wrdata[218]),\n .R(\\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 ));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[219] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[9]_3 ),\n .Q(phy_wrdata[219]),\n .R(wrcal_done_reg_0));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[220] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[9]_2 ),\n .Q(phy_wrdata[220]),\n .R(wrcal_done_reg_0));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[9] ),\n .Q(phy_wrdata[221]),\n .R(wrcal_done_reg));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[222] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[1] ),\n .Q(phy_wrdata[222]),\n .R(\\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 ));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[223] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[9]_1 ),\n .Q(phy_wrdata[223]),\n .R(wrcal_done_reg_0));\n FDSE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[248] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[8]_0 ),\n .Q(phy_wrdata[248]),\n .S(oclkdelay_calib_done_r_reg_1));\n FDSE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[249] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[8]_4 ),\n .Q(phy_wrdata[249]),\n .S(\\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 ));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[24] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[15]_2 ),\n .Q(phy_wrdata[24]),\n .R(oclkdelay_calib_done_r_reg_1));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[250] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\wrdq_div1_4to1_wrcal_first.phy_wrdata[250]_i_1_n_0 ),\n .Q(phy_wrdata[250]),\n .R(1'b0));\n FDSE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[251] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[8]_2 ),\n .Q(phy_wrdata[251]),\n .S(wrcal_done_reg_1));\n FDSE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[252] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[8] ),\n .Q(phy_wrdata[252]),\n .S(oclkdelay_calib_done_r_reg_1));\n FDSE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[253] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[8]_3 ),\n .Q(phy_wrdata[253]),\n .S(\\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 ));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[254] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\wrdq_div1_4to1_wrcal_first.phy_wrdata[254]_i_2_n_0 ),\n .Q(phy_wrdata[254]),\n .R(1'b0));\n FDSE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[255] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[8]_1 ),\n .Q(phy_wrdata[255]),\n .S(wrcal_done_reg_1));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[25] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[7]_0 ),\n .Q(phy_wrdata[25]),\n .R(oclkdelay_calib_done_r_reg_1));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[26] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[7]_2 ),\n .Q(phy_wrdata[26]),\n .R(wrcal_done_reg_1));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[27] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[15]_1 ),\n .Q(phy_wrdata[27]),\n .R(oclkdelay_calib_done_r_reg_1));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[28] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[15]_0 ),\n .Q(phy_wrdata[28]),\n .R(oclkdelay_calib_done_r_reg_1));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[29] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[7] ),\n .Q(phy_wrdata[29]),\n .R(oclkdelay_calib_done_r_reg_1));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[30] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[7]_1 ),\n .Q(phy_wrdata[30]),\n .R(wrcal_done_reg_1));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[31] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[15] ),\n .Q(phy_wrdata[31]),\n .R(oclkdelay_calib_done_r_reg_1));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(D[0]),\n .Q(phy_wrdata[56]),\n .R(1'b0));\n FDSE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(first_rdlvl_pat_r_reg_0),\n .Q(phy_wrdata[57]),\n .S(oclkdelay_calib_done_r_reg_1));\n FDSE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[58] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[14]_2 ),\n .Q(phy_wrdata[58]),\n .S(oclkdelay_calib_done_r_reg_1));\n FDSE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[59] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[14]_1 ),\n .Q(phy_wrdata[59]),\n .S(oclkdelay_calib_done_r_reg_1));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[60] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(D[1]),\n .Q(phy_wrdata[60]),\n .R(1'b0));\n FDSE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[61] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[6] ),\n .Q(phy_wrdata[61]),\n .S(oclkdelay_calib_done_r_reg_1));\n FDSE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[62] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[14]_0 ),\n .Q(phy_wrdata[62]),\n .S(oclkdelay_calib_done_r_reg_1));\n FDSE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[63] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[14] ),\n .Q(phy_wrdata[63]),\n .S(oclkdelay_calib_done_r_reg_1));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[88] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[13]_0 ),\n .Q(phy_wrdata[88]),\n .R(wrcal_done_reg));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[89] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[13]_6 ),\n .Q(phy_wrdata[89]),\n .R(oclkdelay_calib_done_r_reg_1));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[90] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[13]_4 ),\n .Q(phy_wrdata[90]),\n .R(\\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 ));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[13]_2 ),\n .Q(phy_wrdata[91]),\n .R(wrcal_done_reg_0));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[92] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[13] ),\n .Q(phy_wrdata[92]),\n .R(wrcal_done_reg));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[93] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[13]_5 ),\n .Q(phy_wrdata[93]),\n .R(oclkdelay_calib_done_r_reg_1));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[94] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[13]_3 ),\n .Q(phy_wrdata[94]),\n .R(\\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_1_n_0 ));\n FDRE \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[95] \n (.C(CLK),\n .CE(rdlvl_stg1_done_int_reg_0),\n .D(\\dout_o_reg[13]_1 ),\n .Q(phy_wrdata[95]),\n .R(wrcal_done_reg_0));\n LUT6 #(\n .INIT(64'h000000000EEEEEEE)) \n write_calib_i_1\n (.I0(phy_write_calib),\n .I1(wrlvl_active_r1),\n .I2(done_dqs_tap_inc),\n .I3(write_calib_i_2_n_0),\n .I4(Q[1]),\n .I5(rstdiv0_sync_r1_reg_rep__24),\n .O(write_calib_i_1_n_0));\n LUT6 #(\n .INIT(64'h0000000000000004)) \n write_calib_i_2\n (.I0(Q[0]),\n .I1(\\init_state_r_reg_n_0_[3] ),\n .I2(Q[2]),\n .I3(Q[5]),\n .I4(Q[4]),\n .I5(Q[3]),\n .O(write_calib_i_2_n_0));\n FDRE write_calib_reg\n (.C(CLK),\n .CE(1'b1),\n .D(write_calib_i_1_n_0),\n .Q(phy_write_calib),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000000000EA)) \n wrlvl_active_i_1\n (.I0(wrlvl_active),\n .I1(\\en_cnt_div4.wrlvl_odt_i_2_n_0 ),\n .I2(wrlvl_odt),\n .I3(rstdiv0_sync_r1_reg_rep__25),\n .I4(done_dqs_tap_inc),\n .I5(wrlvl_rank_done),\n .O(wrlvl_active_i_1_n_0));\n FDRE wrlvl_active_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrlvl_active),\n .Q(wrlvl_active_r1),\n .R(1'b0));\n FDRE wrlvl_active_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrlvl_active_i_1_n_0),\n .Q(wrlvl_active),\n .R(1'b0));\n FDRE wrlvl_done_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrlvl_done_r),\n .Q(wrlvl_done_r1),\n .R(1'b0));\n FDRE wrlvl_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wr_level_done_reg),\n .Q(wrlvl_done_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000000000AE)) \n wrlvl_final_if_rst_i_1\n (.I0(wrlvl_final_if_rst),\n .I1(wrlvl_done_r),\n .I2(wrlvl_final_if_rst_i_2_n_0),\n .I3(rstdiv0_sync_r1_reg_rep__25),\n .I4(\\cnt_init_mr_r_reg[1]_0 ),\n .I5(\\wrcal_wr_cnt[3]_i_2_n_0 ),\n .O(wrlvl_final_if_rst_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFDFFFF)) \n wrlvl_final_if_rst_i_2\n (.I0(Q[1]),\n .I1(Q[3]),\n .I2(Q[4]),\n .I3(Q[5]),\n .I4(\\init_state_r_reg[1]_0 ),\n .I5(Q[0]),\n .O(wrlvl_final_if_rst_i_2_n_0));\n FDRE wrlvl_final_if_rst_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrlvl_final_if_rst_i_1_n_0),\n .Q(wrlvl_final_if_rst),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h000000AE)) \n wrlvl_odt_ctl_i_1\n (.I0(wrlvl_odt_ctl),\n .I1(wrlvl_rank_done),\n .I2(wrlvl_rank_done_r1),\n .I3(wrlvl_odt_ctl_i_2_n_0),\n .I4(rstdiv0_sync_r1_reg_rep__25),\n .O(wrlvl_odt_ctl_i_1_n_0));\n LUT6 #(\n .INIT(64'h0001000100010000)) \n wrlvl_odt_ctl_i_2\n (.I0(read_calib_reg_0),\n .I1(Q[3]),\n .I2(Q[4]),\n .I3(Q[5]),\n .I4(wrlvl_odt_ctl_i_3_n_0),\n .I5(init_state_r1[3]),\n .O(wrlvl_odt_ctl_i_2_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFDF)) \n wrlvl_odt_ctl_i_3\n (.I0(init_state_r1[1]),\n .I1(init_state_r1[6]),\n .I2(init_state_r1[2]),\n .I3(init_state_r1[5]),\n .I4(init_state_r1[4]),\n .I5(init_state_r1[0]),\n .O(wrlvl_odt_ctl_i_3_n_0));\n FDRE wrlvl_odt_ctl_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrlvl_odt_ctl_i_1_n_0),\n .Q(wrlvl_odt_ctl),\n .R(1'b0));\n FDRE wrlvl_rank_done_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrlvl_rank_done),\n .Q(wrlvl_rank_done_r1),\n .R(1'b0));\n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrlvl_rank_done_r6_reg_srl5 \" *) \n SRL16E wrlvl_rank_done_r6_reg_srl5\n (.A0(1'b0),\n .A1(1'b0),\n .A2(1'b1),\n .A3(1'b0),\n .CE(1'b1),\n .CLK(CLK),\n .D(wrlvl_rank_done_r1),\n .Q(wrlvl_rank_done_r6_reg_srl5_n_0));\n FDRE wrlvl_rank_done_r7_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrlvl_rank_done_r6_reg_srl5_n_0),\n .Q(wrlvl_rank_done_r7),\n .R(1'b0));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_ddr_phy_ocd_cntlr\n (prech_req_r_reg,\n rd_active_r1_reg,\n lim_start,\n wrlvl_final_mux_reg,\n reset_scan,\n complex_ocal_ref_req,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ,\n \\byte_r_reg[1]_0 ,\n \\byte_r_reg[0]_0 ,\n D,\n \\simp_stg3_final_r_reg[23] ,\n \\simp_stg3_final_r_reg[11] ,\n \\simp_stg3_final_r_reg[5] ,\n \\simp_stg3_final_r_reg[17] ,\n done_r_reg,\n \\rd_victim_sel_r_reg[0] ,\n \\stg3_init_val_reg[3] ,\n sr_valid_r108_out,\n \\init_state_r_reg[2] ,\n \\init_state_r_reg[5] ,\n ocal_last_byte_done_reg,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[1] ,\n \\cal2_state_r_reg[0] ,\n ocd_cntlr2stg2_dec_r,\n rstdiv0_sync_r1_reg_rep__9,\n CLK,\n phy_rddata_en,\n rstdiv0_sync_r1_reg_rep__10,\n rstdiv0_sync_r1_reg_rep__26,\n done_r_reg_0,\n oclkdelay_calib_start_int_reg,\n prech_req_r_reg_0,\n rstdiv0_sync_r1_reg_rep__26_0,\n po_rdy,\n \\po_counter_read_val_reg[2] ,\n \\simp_stg3_final_r_reg[17]_0 ,\n \\simp_stg3_final_r_reg[16] ,\n \\simp_stg3_final_r_reg[10] ,\n \\simp_stg3_final_r_reg[2] ,\n \\simp_stg3_final_r_reg[8] ,\n \\simp_stg3_final_r_reg[19] ,\n \\simp_stg3_final_r_reg[12] ,\n lim_start_r,\n rstdiv0_sync_r1_reg_rep__25,\n \\data_cnt_r_reg[7] ,\n rstdiv0_sync_r1_reg_rep__20,\n rdlvl_stg1_start_reg,\n \\cnt_shift_r_reg[0] ,\n \\init_state_r_reg[0] ,\n \\init_state_r_reg[2]_0 ,\n prbs_rdlvl_done_reg,\n oclk_calib_resume_r_reg,\n prech_req_posedge_r_reg,\n cnt_cmd_done_r,\n oclkdelay_center_calib_done_r_reg,\n ocal_last_byte_done,\n \\po_stg2_wrcal_cnt_reg[0] ,\n wr_level_done_reg,\n oclkdelay_calib_done_r_reg_0,\n pi_stg2_rdlvl_cnt,\n \\po_stg2_wrcal_cnt_reg[1] ,\n rd_active_r1,\n wrlvl_byte_done,\n rstdiv0_sync_r1_reg_rep__2,\n prech_done,\n oclkdelay_calib_start_int_reg_0);\n output prech_req_r_reg;\n output rd_active_r1_reg;\n output lim_start;\n output wrlvl_final_mux_reg;\n output reset_scan;\n output complex_ocal_ref_req;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ;\n output \\byte_r_reg[1]_0 ;\n output \\byte_r_reg[0]_0 ;\n output [4:0]D;\n output \\simp_stg3_final_r_reg[23] ;\n output \\simp_stg3_final_r_reg[11] ;\n output \\simp_stg3_final_r_reg[5] ;\n output \\simp_stg3_final_r_reg[17] ;\n output done_r_reg;\n output \\rd_victim_sel_r_reg[0] ;\n output \\stg3_init_val_reg[3] ;\n output sr_valid_r108_out;\n output \\init_state_r_reg[2] ;\n output \\init_state_r_reg[5] ;\n output ocal_last_byte_done_reg;\n output \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ;\n output \\gen_byte_sel_div1.byte_sel_cnt_reg[1] ;\n output \\cal2_state_r_reg[0] ;\n output ocd_cntlr2stg2_dec_r;\n input rstdiv0_sync_r1_reg_rep__9;\n input CLK;\n input phy_rddata_en;\n input rstdiv0_sync_r1_reg_rep__10;\n input rstdiv0_sync_r1_reg_rep__26;\n input done_r_reg_0;\n input oclkdelay_calib_start_int_reg;\n input prech_req_r_reg_0;\n input rstdiv0_sync_r1_reg_rep__26_0;\n input po_rdy;\n input \\po_counter_read_val_reg[2] ;\n input \\simp_stg3_final_r_reg[17]_0 ;\n input \\simp_stg3_final_r_reg[16] ;\n input \\simp_stg3_final_r_reg[10] ;\n input \\simp_stg3_final_r_reg[2] ;\n input \\simp_stg3_final_r_reg[8] ;\n input \\simp_stg3_final_r_reg[19] ;\n input \\simp_stg3_final_r_reg[12] ;\n input lim_start_r;\n input rstdiv0_sync_r1_reg_rep__25;\n input \\data_cnt_r_reg[7] ;\n input rstdiv0_sync_r1_reg_rep__20;\n input rdlvl_stg1_start_reg;\n input \\cnt_shift_r_reg[0] ;\n input \\init_state_r_reg[0] ;\n input [1:0]\\init_state_r_reg[2]_0 ;\n input prbs_rdlvl_done_reg;\n input oclk_calib_resume_r_reg;\n input prech_req_posedge_r_reg;\n input cnt_cmd_done_r;\n input oclkdelay_center_calib_done_r_reg;\n input ocal_last_byte_done;\n input \\po_stg2_wrcal_cnt_reg[0] ;\n input wr_level_done_reg;\n input oclkdelay_calib_done_r_reg_0;\n input [1:0]pi_stg2_rdlvl_cnt;\n input \\po_stg2_wrcal_cnt_reg[1] ;\n input rd_active_r1;\n input wrlvl_byte_done;\n input rstdiv0_sync_r1_reg_rep__2;\n input prech_done;\n input oclkdelay_calib_start_int_reg_0;\n\n wire CLK;\n wire [4:0]D;\n wire \\FSM_sequential_sm_r[0]_i_1_n_0 ;\n wire \\FSM_sequential_sm_r[1]_i_1_n_0 ;\n wire \\FSM_sequential_sm_r[2]_i_1_n_0 ;\n wire \\FSM_sequential_sm_r[2]_i_2_n_0 ;\n wire \\FSM_sequential_sm_r[2]_i_4_n_0 ;\n wire \\FSM_sequential_sm_r[2]_i_5_n_0 ;\n wire \\FSM_sequential_sm_r_reg[2]_i_3_n_0 ;\n wire \\byte_r[0]_i_1_n_0 ;\n wire \\byte_r[0]_i_2_n_0 ;\n wire \\byte_r[1]_i_1_n_0 ;\n wire \\byte_r[1]_i_2_n_0 ;\n wire \\byte_r_reg[0]_0 ;\n wire \\byte_r_reg[1]_0 ;\n wire \\cal2_state_r_reg[0] ;\n wire cnt_cmd_done_r;\n wire \\cnt_shift_r_reg[0] ;\n wire complex_ocal_ref_req;\n wire \\data_cnt_r_reg[7] ;\n wire done_r_reg;\n wire done_r_reg_0;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[1] ;\n wire \\init_state_r_reg[0] ;\n wire \\init_state_r_reg[2] ;\n wire [1:0]\\init_state_r_reg[2]_0 ;\n wire \\init_state_r_reg[5] ;\n wire lim_start;\n wire lim_start_r;\n wire lim_start_r_i_1_n_0;\n wire lim_start_r_i_2_n_0;\n wire ocal_last_byte_done;\n wire ocal_last_byte_done_reg;\n wire ocd_cntlr2stg2_dec_r;\n wire ocd_prech_req_ns;\n wire oclk_calib_resume_r_reg;\n wire oclkdelay_calib_done_r_i_1_n_0;\n wire oclkdelay_calib_done_r_i_3_n_0;\n wire oclkdelay_calib_done_r_reg_0;\n wire oclkdelay_calib_start_int_reg;\n wire oclkdelay_calib_start_int_reg_0;\n wire oclkdelay_center_calib_done_r_reg;\n wire phy_rddata_en;\n wire [1:0]pi_stg2_rdlvl_cnt;\n wire \\po_counter_read_val_reg[2] ;\n wire [3:0]po_rd_wait_ns;\n wire \\po_rd_wait_r[0]_i_2_n_0 ;\n wire \\po_rd_wait_r[1]_i_2_n_0 ;\n wire \\po_rd_wait_r[2]_i_2_n_0 ;\n wire \\po_rd_wait_r[2]_i_3_n_0 ;\n wire \\po_rd_wait_r[3]_i_1_n_0 ;\n wire \\po_rd_wait_r[3]_i_3_n_0 ;\n wire \\po_rd_wait_r[3]_i_4_n_0 ;\n wire \\po_rd_wait_r[3]_i_5_n_0 ;\n wire \\po_rd_wait_r[3]_i_6_n_0 ;\n wire [3:0]po_rd_wait_r_reg__0;\n wire po_rdy;\n wire \\po_stg2_wrcal_cnt_reg[0] ;\n wire \\po_stg2_wrcal_cnt_reg[1] ;\n wire prbs_rdlvl_done_reg;\n wire prech_done;\n wire prech_req_posedge_r_reg;\n wire prech_req_r_reg;\n wire prech_req_r_reg_0;\n wire rd_active_r1;\n wire rd_active_r1_reg;\n wire \\rd_victim_sel_r_reg[0] ;\n wire rdlvl_stg1_start_reg;\n wire reset_scan;\n wire reset_scan_r_i_1_n_0;\n wire rstdiv0_sync_r1_reg_rep__10;\n wire rstdiv0_sync_r1_reg_rep__2;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__25;\n wire rstdiv0_sync_r1_reg_rep__26;\n wire rstdiv0_sync_r1_reg_rep__26_0;\n wire rstdiv0_sync_r1_reg_rep__9;\n wire \\simp_stg3_final_r_reg[10] ;\n wire \\simp_stg3_final_r_reg[11] ;\n wire \\simp_stg3_final_r_reg[12] ;\n wire \\simp_stg3_final_r_reg[16] ;\n wire \\simp_stg3_final_r_reg[17] ;\n wire \\simp_stg3_final_r_reg[17]_0 ;\n wire \\simp_stg3_final_r_reg[19] ;\n wire \\simp_stg3_final_r_reg[23] ;\n wire \\simp_stg3_final_r_reg[2] ;\n wire \\simp_stg3_final_r_reg[5] ;\n wire \\simp_stg3_final_r_reg[8] ;\n (* RTL_KEEP = \"yes\" *) wire [2:0]sm_r;\n wire sr_valid_r108_out;\n wire \\stg3_init_val_reg[3] ;\n wire wr_level_done_reg;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ;\n wire wrlvl_byte_done;\n wire wrlvl_final_mux_reg;\n wire wrlvl_final_r0;\n\n LUT3 #(\n .INIT(8'h74)) \n \\FSM_sequential_sm_r[0]_i_1 \n (.I0(sm_r[0]),\n .I1(\\FSM_sequential_sm_r_reg[2]_i_3_n_0 ),\n .I2(sm_r[0]),\n .O(\\FSM_sequential_sm_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8FB0FFFF8FB00000)) \n \\FSM_sequential_sm_r[1]_i_1 \n (.I0(\\FSM_sequential_sm_r[2]_i_2_n_0 ),\n .I1(sm_r[2]),\n .I2(sm_r[1]),\n .I3(sm_r[0]),\n .I4(\\FSM_sequential_sm_r_reg[2]_i_3_n_0 ),\n .I5(sm_r[1]),\n .O(\\FSM_sequential_sm_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAFC0FFFFAFC00000)) \n \\FSM_sequential_sm_r[2]_i_1 \n (.I0(\\FSM_sequential_sm_r[2]_i_2_n_0 ),\n .I1(sm_r[0]),\n .I2(sm_r[1]),\n .I3(sm_r[2]),\n .I4(\\FSM_sequential_sm_r_reg[2]_i_3_n_0 ),\n .I5(sm_r[2]),\n .O(\\FSM_sequential_sm_r[2]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h08)) \n \\FSM_sequential_sm_r[2]_i_2 \n (.I0(\\byte_r_reg[0]_0 ),\n .I1(\\byte_r_reg[1]_0 ),\n .I2(sm_r[0]),\n .O(\\FSM_sequential_sm_r[2]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hBBBBCFCC)) \n \\FSM_sequential_sm_r[2]_i_4 \n (.I0(prech_done),\n .I1(sm_r[2]),\n .I2(wrlvl_final_mux_reg),\n .I3(oclkdelay_calib_start_int_reg_0),\n .I4(sm_r[0]),\n .O(\\FSM_sequential_sm_r[2]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB8CC)) \n \\FSM_sequential_sm_r[2]_i_5 \n (.I0(oclkdelay_calib_done_r_i_3_n_0),\n .I1(sm_r[2]),\n .I2(rstdiv0_sync_r1_reg_rep__26),\n .I3(sm_r[0]),\n .I4(done_r_reg_0),\n .O(\\FSM_sequential_sm_r[2]_i_5_n_0 ));\n (* KEEP = \"yes\" *) \n FDRE \\FSM_sequential_sm_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_sm_r[0]_i_1_n_0 ),\n .Q(sm_r[0]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n (* KEEP = \"yes\" *) \n FDRE \\FSM_sequential_sm_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_sm_r[1]_i_1_n_0 ),\n .Q(sm_r[1]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n (* KEEP = \"yes\" *) \n FDRE \\FSM_sequential_sm_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_sm_r[2]_i_1_n_0 ),\n .Q(sm_r[2]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n MUXF7 \\FSM_sequential_sm_r_reg[2]_i_3 \n (.I0(\\FSM_sequential_sm_r[2]_i_4_n_0 ),\n .I1(\\FSM_sequential_sm_r[2]_i_5_n_0 ),\n .O(\\FSM_sequential_sm_r_reg[2]_i_3_n_0 ),\n .S(sm_r[1]));\n LUT6 #(\n .INIT(64'hFFFF5EDE0000A020)) \n \\byte_r[0]_i_1 \n (.I0(sm_r[2]),\n .I1(sm_r[0]),\n .I2(sm_r[1]),\n .I3(\\byte_r[0]_i_2_n_0 ),\n .I4(rstdiv0_sync_r1_reg_rep__26_0),\n .I5(\\byte_r_reg[0]_0 ),\n .O(\\byte_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair353\" *) \n LUT5 #(\n .INIT(32'h00000444)) \n \\byte_r[0]_i_2 \n (.I0(\\po_rd_wait_r[3]_i_6_n_0 ),\n .I1(po_rdy),\n .I2(\\byte_r_reg[1]_0 ),\n .I3(\\byte_r_reg[0]_0 ),\n .I4(\\po_counter_read_val_reg[2] ),\n .O(\\byte_r[0]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'h4F80)) \n \\byte_r[1]_i_1 \n (.I0(\\byte_r_reg[0]_0 ),\n .I1(sm_r[1]),\n .I2(\\byte_r[1]_i_2_n_0 ),\n .I3(\\byte_r_reg[1]_0 ),\n .O(\\byte_r[1]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h0000A121)) \n \\byte_r[1]_i_2 \n (.I0(sm_r[2]),\n .I1(sm_r[0]),\n .I2(sm_r[1]),\n .I3(\\byte_r[0]_i_2_n_0 ),\n .I4(rstdiv0_sync_r1_reg_rep__26_0),\n .O(\\byte_r[1]_i_2_n_0 ));\n FDRE \\byte_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r[0]_i_1_n_0 ),\n .Q(\\byte_r_reg[0]_0 ),\n .R(1'b0));\n FDRE \\byte_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r[1]_i_1_n_0 ),\n .Q(\\byte_r_reg[1]_0 ),\n .R(1'b0));\n LUT3 #(\n .INIT(8'h40)) \n \\cal2_state_r[3]_i_10 \n (.I0(rd_active_r1_reg),\n .I1(rd_active_r1),\n .I2(wrlvl_byte_done),\n .O(\\cal2_state_r_reg[0] ));\n LUT2 #(\n .INIT(4'h2)) \n done_r_i_2\n (.I0(lim_start),\n .I1(lim_start_r),\n .O(done_r_reg));\n LUT6 #(\n .INIT(64'hFF00F4000000F400)) \n \\gen_byte_sel_div1.byte_sel_cnt[0]_i_2 \n (.I0(wrlvl_final_mux_reg),\n .I1(\\byte_r_reg[0]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[0] ),\n .I3(wr_level_done_reg),\n .I4(oclkdelay_calib_done_r_reg_0),\n .I5(pi_stg2_rdlvl_cnt[0]),\n .O(\\gen_byte_sel_div1.byte_sel_cnt_reg[0] ));\n LUT6 #(\n .INIT(64'hFF00F4000000F400)) \n \\gen_byte_sel_div1.byte_sel_cnt[1]_i_2 \n (.I0(wrlvl_final_mux_reg),\n .I1(\\byte_r_reg[1]_0 ),\n .I2(\\po_stg2_wrcal_cnt_reg[1] ),\n .I3(wr_level_done_reg),\n .I4(oclkdelay_calib_done_r_reg_0),\n .I5(pi_stg2_rdlvl_cnt[1]),\n .O(\\gen_byte_sel_div1.byte_sel_cnt_reg[1] ));\n LUT6 #(\n .INIT(64'hAAAAAAAA00000008)) \n \\init_state_r[2]_i_19 \n (.I0(\\init_state_r_reg[0] ),\n .I1(\\init_state_r_reg[2]_0 [1]),\n .I2(prech_req_r_reg),\n .I3(prech_req_r_reg_0),\n .I4(prbs_rdlvl_done_reg),\n .I5(oclk_calib_resume_r_reg),\n .O(\\init_state_r_reg[2] ));\n LUT6 #(\n .INIT(64'h00000000EEEEEE0E)) \n \\init_state_r[5]_i_59 \n (.I0(wrlvl_final_mux_reg),\n .I1(prech_req_posedge_r_reg),\n .I2(cnt_cmd_done_r),\n .I3(prech_req_r_reg_0),\n .I4(prech_req_r_reg),\n .I5(\\init_state_r_reg[2]_0 [0]),\n .O(\\init_state_r_reg[5] ));\n LUT6 #(\n .INIT(64'hFFFF777788880300)) \n lim_start_r_i_1\n (.I0(lim_start_r_i_2_n_0),\n .I1(sm_r[1]),\n .I2(sm_r[0]),\n .I3(oclkdelay_calib_start_int_reg),\n .I4(sm_r[2]),\n .I5(lim_start),\n .O(lim_start_r_i_1_n_0));\n LUT5 #(\n .INIT(32'h00007F70)) \n lim_start_r_i_2\n (.I0(\\byte_r_reg[0]_0 ),\n .I1(\\byte_r_reg[1]_0 ),\n .I2(sm_r[2]),\n .I3(done_r_reg_0),\n .I4(sm_r[0]),\n .O(lim_start_r_i_2_n_0));\n FDRE lim_start_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(lim_start_r_i_1_n_0),\n .Q(lim_start),\n .R(rstdiv0_sync_r1_reg_rep__10));\n (* SOFT_HLUTNM = \"soft_lutpair355\" *) \n LUT4 #(\n .INIT(16'hFF80)) \n ocal_last_byte_done_i_2\n (.I0(oclkdelay_center_calib_done_r_reg),\n .I1(\\byte_r_reg[0]_0 ),\n .I2(\\byte_r_reg[1]_0 ),\n .I3(ocal_last_byte_done),\n .O(ocal_last_byte_done_reg));\n LUT3 #(\n .INIT(8'h04)) \n ocd_prech_req_r_i_1\n (.I0(sm_r[0]),\n .I1(sm_r[2]),\n .I2(sm_r[1]),\n .O(ocd_prech_req_ns));\n FDRE ocd_prech_req_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(ocd_prech_req_ns),\n .Q(prech_req_r_reg),\n .R(rstdiv0_sync_r1_reg_rep__9));\n LUT6 #(\n .INIT(64'hBFFFFFFF80000000)) \n oclkdelay_calib_done_r_i_1\n (.I0(wrlvl_final_r0),\n .I1(sm_r[2]),\n .I2(oclkdelay_calib_done_r_i_3_n_0),\n .I3(sm_r[0]),\n .I4(sm_r[1]),\n .I5(wrlvl_final_mux_reg),\n .O(oclkdelay_calib_done_r_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair354\" *) \n LUT5 #(\n .INIT(32'h00000002)) \n oclkdelay_calib_done_r_i_2\n (.I0(po_rdy),\n .I1(po_rd_wait_r_reg__0[0]),\n .I2(po_rd_wait_r_reg__0[1]),\n .I3(po_rd_wait_r_reg__0[2]),\n .I4(po_rd_wait_r_reg__0[3]),\n .O(wrlvl_final_r0));\n (* SOFT_HLUTNM = \"soft_lutpair353\" *) \n LUT5 #(\n .INIT(32'h04000000)) \n oclkdelay_calib_done_r_i_3\n (.I0(\\po_rd_wait_r[3]_i_6_n_0 ),\n .I1(po_rdy),\n .I2(\\po_counter_read_val_reg[2] ),\n .I3(\\byte_r_reg[1]_0 ),\n .I4(\\byte_r_reg[0]_0 ),\n .O(oclkdelay_calib_done_r_i_3_n_0));\n FDRE oclkdelay_calib_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(oclkdelay_calib_done_r_i_1_n_0),\n .Q(wrlvl_final_mux_reg),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE phy_rddata_en_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(phy_rddata_en),\n .Q(rd_active_r1_reg),\n .R(1'b0));\n LUT4 #(\n .INIT(16'h40EF)) \n \\po_rd_wait_r[0]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__26_0),\n .I1(\\po_rd_wait_r[0]_i_2_n_0 ),\n .I2(sm_r[1]),\n .I3(po_rd_wait_r_reg__0[0]),\n .O(po_rd_wait_ns[0]));\n LUT6 #(\n .INIT(64'h000000004777FFFF)) \n \\po_rd_wait_r[0]_i_2 \n (.I0(\\byte_r[0]_i_2_n_0 ),\n .I1(sm_r[0]),\n .I2(\\byte_r_reg[0]_0 ),\n .I3(\\byte_r_reg[1]_0 ),\n .I4(sm_r[2]),\n .I5(po_rd_wait_r_reg__0[0]),\n .O(\\po_rd_wait_r[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hEFFF40004000EFFF)) \n \\po_rd_wait_r[1]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__26_0),\n .I1(\\po_rd_wait_r[1]_i_2_n_0 ),\n .I2(sm_r[2]),\n .I3(sm_r[1]),\n .I4(po_rd_wait_r_reg__0[0]),\n .I5(po_rd_wait_r_reg__0[1]),\n .O(po_rd_wait_ns[1]));\n LUT6 #(\n .INIT(64'h4777000000004777)) \n \\po_rd_wait_r[1]_i_2 \n (.I0(\\byte_r[0]_i_2_n_0 ),\n .I1(sm_r[0]),\n .I2(\\byte_r_reg[0]_0 ),\n .I3(\\byte_r_reg[1]_0 ),\n .I4(po_rd_wait_r_reg__0[0]),\n .I5(po_rd_wait_r_reg__0[1]),\n .O(\\po_rd_wait_r[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hEF40EF40EF4040EF)) \n \\po_rd_wait_r[2]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__26_0),\n .I1(\\po_rd_wait_r[2]_i_2_n_0 ),\n .I2(sm_r[1]),\n .I3(po_rd_wait_r_reg__0[2]),\n .I4(po_rd_wait_r_reg__0[0]),\n .I5(po_rd_wait_r_reg__0[1]),\n .O(po_rd_wait_ns[2]));\n LUT6 #(\n .INIT(64'h4777FFFF00000000)) \n \\po_rd_wait_r[2]_i_2 \n (.I0(\\byte_r[0]_i_2_n_0 ),\n .I1(sm_r[0]),\n .I2(\\byte_r_reg[0]_0 ),\n .I3(\\byte_r_reg[1]_0 ),\n .I4(sm_r[2]),\n .I5(\\po_rd_wait_r[2]_i_3_n_0 ),\n .O(\\po_rd_wait_r[2]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair356\" *) \n LUT3 #(\n .INIT(8'hA9)) \n \\po_rd_wait_r[2]_i_3 \n (.I0(po_rd_wait_r_reg__0[2]),\n .I1(po_rd_wait_r_reg__0[0]),\n .I2(po_rd_wait_r_reg__0[1]),\n .O(\\po_rd_wait_r[2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFEFFFFFFFE0000)) \n \\po_rd_wait_r[3]_i_1 \n (.I0(po_rd_wait_r_reg__0[3]),\n .I1(po_rd_wait_r_reg__0[2]),\n .I2(po_rd_wait_r_reg__0[1]),\n .I3(po_rd_wait_r_reg__0[0]),\n .I4(rstdiv0_sync_r1_reg_rep__26_0),\n .I5(\\po_rd_wait_r[3]_i_3_n_0 ),\n .O(\\po_rd_wait_r[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF01000000)) \n \\po_rd_wait_r[3]_i_2 \n (.I0(rstdiv0_sync_r1_reg_rep__26_0),\n .I1(sm_r[0]),\n .I2(\\po_rd_wait_r[3]_i_4_n_0 ),\n .I3(sm_r[2]),\n .I4(sm_r[1]),\n .I5(\\po_rd_wait_r[3]_i_5_n_0 ),\n .O(po_rd_wait_ns[3]));\n LUT6 #(\n .INIT(64'hFFFFFFFF8B000000)) \n \\po_rd_wait_r[3]_i_3 \n (.I0(\\byte_r[0]_i_2_n_0 ),\n .I1(sm_r[0]),\n .I2(\\po_rd_wait_r[3]_i_4_n_0 ),\n .I3(sm_r[2]),\n .I4(sm_r[1]),\n .I5(\\po_rd_wait_r[3]_i_6_n_0 ),\n .O(\\po_rd_wait_r[3]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair361\" *) \n LUT2 #(\n .INIT(4'h7)) \n \\po_rd_wait_r[3]_i_4 \n (.I0(\\byte_r_reg[1]_0 ),\n .I1(\\byte_r_reg[0]_0 ),\n .O(\\po_rd_wait_r[3]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair356\" *) \n LUT4 #(\n .INIT(16'hAAA9)) \n \\po_rd_wait_r[3]_i_5 \n (.I0(po_rd_wait_r_reg__0[3]),\n .I1(po_rd_wait_r_reg__0[2]),\n .I2(po_rd_wait_r_reg__0[1]),\n .I3(po_rd_wait_r_reg__0[0]),\n .O(\\po_rd_wait_r[3]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair354\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n \\po_rd_wait_r[3]_i_6 \n (.I0(po_rd_wait_r_reg__0[3]),\n .I1(po_rd_wait_r_reg__0[2]),\n .I2(po_rd_wait_r_reg__0[1]),\n .I3(po_rd_wait_r_reg__0[0]),\n .O(\\po_rd_wait_r[3]_i_6_n_0 ));\n FDRE \\po_rd_wait_r_reg[0] \n (.C(CLK),\n .CE(\\po_rd_wait_r[3]_i_1_n_0 ),\n .D(po_rd_wait_ns[0]),\n .Q(po_rd_wait_r_reg__0[0]),\n .R(1'b0));\n FDRE \\po_rd_wait_r_reg[1] \n (.C(CLK),\n .CE(\\po_rd_wait_r[3]_i_1_n_0 ),\n .D(po_rd_wait_ns[1]),\n .Q(po_rd_wait_r_reg__0[1]),\n .R(1'b0));\n FDRE \\po_rd_wait_r_reg[2] \n (.C(CLK),\n .CE(\\po_rd_wait_r[3]_i_1_n_0 ),\n .D(po_rd_wait_ns[2]),\n .Q(po_rd_wait_r_reg__0[2]),\n .R(1'b0));\n FDRE \\po_rd_wait_r_reg[3] \n (.C(CLK),\n .CE(\\po_rd_wait_r[3]_i_1_n_0 ),\n .D(po_rd_wait_ns[3]),\n .Q(po_rd_wait_r_reg__0[3]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0080000000000000)) \n po_rdy_r_i_8\n (.I0(sm_r[2]),\n .I1(\\po_counter_read_val_reg[2] ),\n .I2(po_rdy),\n .I3(\\po_rd_wait_r[3]_i_6_n_0 ),\n .I4(sm_r[0]),\n .I5(sm_r[1]),\n .O(ocd_cntlr2stg2_dec_r));\n LUT2 #(\n .INIT(4'hE)) \n prech_req_r_i_2__0\n (.I0(prech_req_r_reg),\n .I1(prech_req_r_reg_0),\n .O(complex_ocal_ref_req));\n (* SOFT_HLUTNM = \"soft_lutpair358\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\rd_victim_sel_r[2]_i_2 \n (.I0(rstdiv0_sync_r1_reg_rep__25),\n .I1(rd_active_r1_reg),\n .I2(\\data_cnt_r_reg[7] ),\n .O(\\rd_victim_sel_r_reg[0] ));\n LUT6 #(\n .INIT(64'hFAFFFFFF40400000)) \n reset_scan_r_i_1\n (.I0(sm_r[2]),\n .I1(rstdiv0_sync_r1_reg_rep__26),\n .I2(sm_r[0]),\n .I3(done_r_reg_0),\n .I4(sm_r[1]),\n .I5(reset_scan),\n .O(reset_scan_r_i_1_n_0));\n FDSE reset_scan_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(reset_scan_r_i_1_n_0),\n .Q(reset_scan),\n .S(rstdiv0_sync_r1_reg_rep__9));\n (* SOFT_HLUTNM = \"soft_lutpair360\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\simp_stg3_final_r[11]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__26),\n .I1(\\byte_r_reg[0]_0 ),\n .I2(\\byte_r_reg[1]_0 ),\n .O(\\simp_stg3_final_r_reg[11] ));\n (* SOFT_HLUTNM = \"soft_lutpair360\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\simp_stg3_final_r[17]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__26),\n .I1(\\byte_r_reg[1]_0 ),\n .I2(\\byte_r_reg[0]_0 ),\n .O(\\simp_stg3_final_r_reg[17] ));\n (* SOFT_HLUTNM = \"soft_lutpair355\" *) \n LUT3 #(\n .INIT(8'h80)) \n \\simp_stg3_final_r[23]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__26),\n .I1(\\byte_r_reg[0]_0 ),\n .I2(\\byte_r_reg[1]_0 ),\n .O(\\simp_stg3_final_r_reg[23] ));\n (* SOFT_HLUTNM = \"soft_lutpair361\" *) \n LUT3 #(\n .INIT(8'h02)) \n \\simp_stg3_final_r[5]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__26),\n .I1(\\byte_r_reg[0]_0 ),\n .I2(\\byte_r_reg[1]_0 ),\n .O(\\simp_stg3_final_r_reg[5] ));\n LUT4 #(\n .INIT(16'h0020)) \n sr_valid_r_i_1\n (.I0(rd_active_r1_reg),\n .I1(rstdiv0_sync_r1_reg_rep__20),\n .I2(rdlvl_stg1_start_reg),\n .I3(\\cnt_shift_r_reg[0] ),\n .O(sr_valid_r108_out));\n (* SOFT_HLUTNM = \"soft_lutpair359\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\stg3_init_val[0]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__26_0),\n .I1(wrlvl_final_mux_reg),\n .I2(\\simp_stg3_final_r_reg[12] ),\n .O(D[0]));\n (* SOFT_HLUTNM = \"soft_lutpair357\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\stg3_init_val[1]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__26_0),\n .I1(wrlvl_final_mux_reg),\n .I2(\\simp_stg3_final_r_reg[19] ),\n .O(D[1]));\n LUT6 #(\n .INIT(64'hFFFFFFFFDDDDDDFD)) \n \\stg3_init_val[2]_i_1 \n (.I0(wrlvl_final_mux_reg),\n .I1(rstdiv0_sync_r1_reg_rep__26_0),\n .I2(\\simp_stg3_final_r_reg[2] ),\n .I3(\\byte_r_reg[0]_0 ),\n .I4(\\byte_r_reg[1]_0 ),\n .I5(\\simp_stg3_final_r_reg[8] ),\n .O(D[2]));\n (* SOFT_HLUTNM = \"soft_lutpair358\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\stg3_init_val[3]_i_3 \n (.I0(wrlvl_final_mux_reg),\n .I1(rstdiv0_sync_r1_reg_rep__25),\n .O(\\stg3_init_val_reg[3] ));\n LUT6 #(\n .INIT(64'hFFFFFFFFDDDDFDDD)) \n \\stg3_init_val[4]_i_1 \n (.I0(wrlvl_final_mux_reg),\n .I1(rstdiv0_sync_r1_reg_rep__26_0),\n .I2(\\simp_stg3_final_r_reg[16] ),\n .I3(\\byte_r_reg[1]_0 ),\n .I4(\\byte_r_reg[0]_0 ),\n .I5(\\simp_stg3_final_r_reg[10] ),\n .O(D[3]));\n (* SOFT_HLUTNM = \"soft_lutpair357\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\stg3_init_val[5]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__26_0),\n .I1(wrlvl_final_mux_reg),\n .I2(\\simp_stg3_final_r_reg[17]_0 ),\n .O(D[4]));\n (* SOFT_HLUTNM = \"soft_lutpair359\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[158]_i_1 \n (.I0(wrlvl_final_mux_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_ddr_phy_ocd_data\n (E,\n \\zero_r_reg[9] ,\n \\zero_r_reg[9]_0 ,\n \\rd_victim_sel_r_reg[0] ,\n agg_samp_r,\n \\byte_r_reg[0] ,\n CLK);\n output [0:0]E;\n output \\zero_r_reg[9] ;\n output \\zero_r_reg[9]_0 ;\n input \\rd_victim_sel_r_reg[0] ;\n input [1:0]agg_samp_r;\n input [63:0]\\byte_r_reg[0] ;\n input CLK;\n\n wire CLK;\n wire [0:0]E;\n wire [1:0]agg_samp_r;\n wire [63:0]\\byte_r_reg[0] ;\n wire [63:0]data_bytes_r;\n wire \\rd_victim_sel_r_reg[0] ;\n wire \\zero_r[9]_i_10_n_0 ;\n wire \\zero_r[9]_i_11_n_0 ;\n wire \\zero_r[9]_i_12_n_0 ;\n wire \\zero_r[9]_i_13_n_0 ;\n wire \\zero_r[9]_i_14_n_0 ;\n wire \\zero_r[9]_i_15_n_0 ;\n wire \\zero_r[9]_i_16_n_0 ;\n wire \\zero_r[9]_i_17_n_0 ;\n wire \\zero_r[9]_i_18_n_0 ;\n wire \\zero_r[9]_i_19_n_0 ;\n wire \\zero_r[9]_i_20_n_0 ;\n wire \\zero_r[9]_i_21_n_0 ;\n wire \\zero_r[9]_i_22_n_0 ;\n wire \\zero_r[9]_i_23_n_0 ;\n wire \\zero_r[9]_i_24_n_0 ;\n wire \\zero_r[9]_i_25_n_0 ;\n wire \\zero_r[9]_i_26_n_0 ;\n wire \\zero_r[9]_i_27_n_0 ;\n wire \\zero_r[9]_i_28_n_0 ;\n wire \\zero_r[9]_i_29_n_0 ;\n wire \\zero_r[9]_i_30_n_0 ;\n wire \\zero_r[9]_i_31_n_0 ;\n wire \\zero_r[9]_i_32_n_0 ;\n wire \\zero_r[9]_i_33_n_0 ;\n wire \\zero_r[9]_i_34_n_0 ;\n wire \\zero_r[9]_i_35_n_0 ;\n wire \\zero_r[9]_i_36_n_0 ;\n wire \\zero_r[9]_i_37_n_0 ;\n wire \\zero_r[9]_i_38_n_0 ;\n wire \\zero_r[9]_i_39_n_0 ;\n wire \\zero_r[9]_i_40_n_0 ;\n wire \\zero_r[9]_i_9_n_0 ;\n wire \\zero_r_reg[9] ;\n wire \\zero_r_reg[9]_0 ;\n\n FDRE \\data_bytes_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [0]),\n .Q(data_bytes_r[0]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [10]),\n .Q(data_bytes_r[10]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [11]),\n .Q(data_bytes_r[11]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[12] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [12]),\n .Q(data_bytes_r[12]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[13] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [13]),\n .Q(data_bytes_r[13]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[14] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [14]),\n .Q(data_bytes_r[14]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[15] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [15]),\n .Q(data_bytes_r[15]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[16] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [16]),\n .Q(data_bytes_r[16]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[17] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [17]),\n .Q(data_bytes_r[17]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[18] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [18]),\n .Q(data_bytes_r[18]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[19] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [19]),\n .Q(data_bytes_r[19]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [1]),\n .Q(data_bytes_r[1]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[20] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [20]),\n .Q(data_bytes_r[20]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[21] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [21]),\n .Q(data_bytes_r[21]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[22] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [22]),\n .Q(data_bytes_r[22]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[23] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [23]),\n .Q(data_bytes_r[23]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[24] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [24]),\n .Q(data_bytes_r[24]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[25] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [25]),\n .Q(data_bytes_r[25]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[26] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [26]),\n .Q(data_bytes_r[26]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[27] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [27]),\n .Q(data_bytes_r[27]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[28] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [28]),\n .Q(data_bytes_r[28]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[29] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [29]),\n .Q(data_bytes_r[29]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [2]),\n .Q(data_bytes_r[2]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[30] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [30]),\n .Q(data_bytes_r[30]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[31] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [31]),\n .Q(data_bytes_r[31]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[32] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [32]),\n .Q(data_bytes_r[32]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[33] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [33]),\n .Q(data_bytes_r[33]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[34] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [34]),\n .Q(data_bytes_r[34]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[35] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [35]),\n .Q(data_bytes_r[35]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[36] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [36]),\n .Q(data_bytes_r[36]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[37] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [37]),\n .Q(data_bytes_r[37]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[38] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [38]),\n .Q(data_bytes_r[38]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[39] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [39]),\n .Q(data_bytes_r[39]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [3]),\n .Q(data_bytes_r[3]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[40] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [40]),\n .Q(data_bytes_r[40]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[41] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [41]),\n .Q(data_bytes_r[41]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[42] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [42]),\n .Q(data_bytes_r[42]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[43] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [43]),\n .Q(data_bytes_r[43]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[44] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [44]),\n .Q(data_bytes_r[44]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[45] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [45]),\n .Q(data_bytes_r[45]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[46] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [46]),\n .Q(data_bytes_r[46]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[47] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [47]),\n .Q(data_bytes_r[47]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[48] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [48]),\n .Q(data_bytes_r[48]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[49] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [49]),\n .Q(data_bytes_r[49]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [4]),\n .Q(data_bytes_r[4]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[50] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [50]),\n .Q(data_bytes_r[50]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[51] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [51]),\n .Q(data_bytes_r[51]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[52] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [52]),\n .Q(data_bytes_r[52]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[53] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [53]),\n .Q(data_bytes_r[53]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[54] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [54]),\n .Q(data_bytes_r[54]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[55] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [55]),\n .Q(data_bytes_r[55]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[56] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [56]),\n .Q(data_bytes_r[56]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[57] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [57]),\n .Q(data_bytes_r[57]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[58] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [58]),\n .Q(data_bytes_r[58]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[59] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [59]),\n .Q(data_bytes_r[59]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [5]),\n .Q(data_bytes_r[5]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[60] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [60]),\n .Q(data_bytes_r[60]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[61] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [61]),\n .Q(data_bytes_r[61]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[62] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [62]),\n .Q(data_bytes_r[62]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[63] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [63]),\n .Q(data_bytes_r[63]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [6]),\n .Q(data_bytes_r[6]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [7]),\n .Q(data_bytes_r[7]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [8]),\n .Q(data_bytes_r[8]),\n .R(1'b0));\n FDRE \\data_bytes_r_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(\\byte_r_reg[0] [9]),\n .Q(data_bytes_r[9]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0000010000000000)) \n \\zero_r[9]_i_10 \n (.I0(data_bytes_r[53]),\n .I1(data_bytes_r[52]),\n .I2(data_bytes_r[48]),\n .I3(data_bytes_r[58]),\n .I4(data_bytes_r[1]),\n .I5(data_bytes_r[59]),\n .O(\\zero_r[9]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFBFF)) \n \\zero_r[9]_i_11 \n (.I0(\\zero_r[9]_i_21_n_0 ),\n .I1(data_bytes_r[56]),\n .I2(data_bytes_r[38]),\n .I3(data_bytes_r[42]),\n .I4(data_bytes_r[35]),\n .I5(\\zero_r[9]_i_22_n_0 ),\n .O(\\zero_r[9]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFEFF)) \n \\zero_r[9]_i_12 \n (.I0(\\zero_r[9]_i_23_n_0 ),\n .I1(data_bytes_r[2]),\n .I2(data_bytes_r[3]),\n .I3(data_bytes_r[30]),\n .I4(data_bytes_r[39]),\n .I5(\\zero_r[9]_i_24_n_0 ),\n .O(\\zero_r[9]_i_12_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFFF7F)) \n \\zero_r[9]_i_13 \n (.I0(data_bytes_r[25]),\n .I1(data_bytes_r[9]),\n .I2(data_bytes_r[12]),\n .I3(\\zero_r[9]_i_25_n_0 ),\n .I4(\\zero_r[9]_i_26_n_0 ),\n .O(\\zero_r[9]_i_13_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFBFFFFFF)) \n \\zero_r[9]_i_14 \n (.I0(\\zero_r[9]_i_27_n_0 ),\n .I1(data_bytes_r[32]),\n .I2(data_bytes_r[29]),\n .I3(data_bytes_r[21]),\n .I4(data_bytes_r[19]),\n .I5(\\zero_r[9]_i_28_n_0 ),\n .O(\\zero_r[9]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'h0001000000000000)) \n \\zero_r[9]_i_15 \n (.I0(data_bytes_r[14]),\n .I1(data_bytes_r[30]),\n .I2(data_bytes_r[31]),\n .I3(data_bytes_r[46]),\n .I4(data_bytes_r[48]),\n .I5(data_bytes_r[54]),\n .O(\\zero_r[9]_i_15_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFBFF)) \n \\zero_r[9]_i_16 \n (.I0(\\zero_r[9]_i_29_n_0 ),\n .I1(data_bytes_r[49]),\n .I2(data_bytes_r[63]),\n .I3(data_bytes_r[22]),\n .I4(data_bytes_r[43]),\n .I5(\\zero_r[9]_i_30_n_0 ),\n .O(\\zero_r[9]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFBFFFFFF)) \n \\zero_r[9]_i_17 \n (.I0(\\zero_r[9]_i_31_n_0 ),\n .I1(data_bytes_r[53]),\n .I2(data_bytes_r[11]),\n .I3(data_bytes_r[7]),\n .I4(data_bytes_r[18]),\n .I5(\\zero_r[9]_i_32_n_0 ),\n .O(\\zero_r[9]_i_17_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFFFDF)) \n \\zero_r[9]_i_18 \n (.I0(data_bytes_r[36]),\n .I1(data_bytes_r[24]),\n .I2(data_bytes_r[4]),\n .I3(\\zero_r[9]_i_33_n_0 ),\n .I4(\\zero_r[9]_i_34_n_0 ),\n .O(\\zero_r[9]_i_18_n_0 ));\n LUT4 #(\n .INIT(16'hFFFD)) \n \\zero_r[9]_i_19 \n (.I0(data_bytes_r[43]),\n .I1(data_bytes_r[6]),\n .I2(data_bytes_r[54]),\n .I3(data_bytes_r[37]),\n .O(\\zero_r[9]_i_19_n_0 ));\n LUT3 #(\n .INIT(8'h08)) \n \\zero_r[9]_i_2 \n (.I0(\\zero_r_reg[9] ),\n .I1(\\rd_victim_sel_r_reg[0] ),\n .I2(\\zero_r_reg[9]_0 ),\n .O(E));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\zero_r[9]_i_20 \n (.I0(data_bytes_r[40]),\n .I1(data_bytes_r[29]),\n .I2(data_bytes_r[27]),\n .I3(data_bytes_r[60]),\n .I4(\\zero_r[9]_i_35_n_0 ),\n .O(\\zero_r[9]_i_20_n_0 ));\n LUT4 #(\n .INIT(16'hFFDF)) \n \\zero_r[9]_i_21 \n (.I0(data_bytes_r[44]),\n .I1(data_bytes_r[20]),\n .I2(agg_samp_r[0]),\n .I3(data_bytes_r[55]),\n .O(\\zero_r[9]_i_21_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFFFFB)) \n \\zero_r[9]_i_22 \n (.I0(data_bytes_r[19]),\n .I1(data_bytes_r[63]),\n .I2(data_bytes_r[5]),\n .I3(data_bytes_r[4]),\n .I4(\\zero_r[9]_i_36_n_0 ),\n .O(\\zero_r[9]_i_22_n_0 ));\n LUT4 #(\n .INIT(16'hFFF7)) \n \\zero_r[9]_i_23 \n (.I0(data_bytes_r[61]),\n .I1(data_bytes_r[31]),\n .I2(data_bytes_r[32]),\n .I3(data_bytes_r[23]),\n .O(\\zero_r[9]_i_23_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFBFFF)) \n \\zero_r[9]_i_24 \n (.I0(data_bytes_r[34]),\n .I1(data_bytes_r[41]),\n .I2(data_bytes_r[45]),\n .I3(data_bytes_r[14]),\n .I4(\\zero_r[9]_i_37_n_0 ),\n .O(\\zero_r[9]_i_24_n_0 ));\n LUT4 #(\n .INIT(16'hFFDF)) \n \\zero_r[9]_i_25 \n (.I0(data_bytes_r[57]),\n .I1(data_bytes_r[16]),\n .I2(data_bytes_r[26]),\n .I3(data_bytes_r[17]),\n .O(\\zero_r[9]_i_25_n_0 ));\n LUT4 #(\n .INIT(16'hEFFF)) \n \\zero_r[9]_i_26 \n (.I0(data_bytes_r[22]),\n .I1(data_bytes_r[51]),\n .I2(data_bytes_r[13]),\n .I3(data_bytes_r[28]),\n .O(\\zero_r[9]_i_26_n_0 ));\n LUT4 #(\n .INIT(16'hFFFD)) \n \\zero_r[9]_i_27 \n (.I0(data_bytes_r[6]),\n .I1(data_bytes_r[9]),\n .I2(data_bytes_r[12]),\n .I3(data_bytes_r[60]),\n .O(\\zero_r[9]_i_27_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFBFFF)) \n \\zero_r[9]_i_28 \n (.I0(data_bytes_r[47]),\n .I1(data_bytes_r[51]),\n .I2(data_bytes_r[55]),\n .I3(data_bytes_r[34]),\n .I4(\\zero_r[9]_i_38_n_0 ),\n .O(\\zero_r[9]_i_28_n_0 ));\n LUT4 #(\n .INIT(16'hFFFD)) \n \\zero_r[9]_i_29 \n (.I0(data_bytes_r[39]),\n .I1(data_bytes_r[13]),\n .I2(data_bytes_r[26]),\n .I3(data_bytes_r[57]),\n .O(\\zero_r[9]_i_29_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFF7FF)) \n \\zero_r[9]_i_30 \n (.I0(data_bytes_r[0]),\n .I1(data_bytes_r[5]),\n .I2(data_bytes_r[59]),\n .I3(agg_samp_r[1]),\n .I4(\\zero_r[9]_i_39_n_0 ),\n .O(\\zero_r[9]_i_30_n_0 ));\n LUT4 #(\n .INIT(16'hEFFF)) \n \\zero_r[9]_i_31 \n (.I0(data_bytes_r[25]),\n .I1(data_bytes_r[10]),\n .I2(data_bytes_r[20]),\n .I3(data_bytes_r[33]),\n .O(\\zero_r[9]_i_31_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFFEFF)) \n \\zero_r[9]_i_32 \n (.I0(data_bytes_r[27]),\n .I1(data_bytes_r[56]),\n .I2(data_bytes_r[8]),\n .I3(data_bytes_r[17]),\n .I4(\\zero_r[9]_i_40_n_0 ),\n .O(\\zero_r[9]_i_32_n_0 ));\n LUT4 #(\n .INIT(16'hFFF7)) \n \\zero_r[9]_i_33 \n (.I0(data_bytes_r[23]),\n .I1(data_bytes_r[50]),\n .I2(data_bytes_r[41]),\n .I3(data_bytes_r[44]),\n .O(\\zero_r[9]_i_33_n_0 ));\n LUT4 #(\n .INIT(16'hFF7F)) \n \\zero_r[9]_i_34 \n (.I0(data_bytes_r[16]),\n .I1(data_bytes_r[35]),\n .I2(data_bytes_r[38]),\n .I3(data_bytes_r[62]),\n .O(\\zero_r[9]_i_34_n_0 ));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\zero_r[9]_i_35 \n (.I0(data_bytes_r[49]),\n .I1(data_bytes_r[33]),\n .I2(data_bytes_r[18]),\n .I3(data_bytes_r[36]),\n .O(\\zero_r[9]_i_35_n_0 ));\n LUT4 #(\n .INIT(16'hFFDF)) \n \\zero_r[9]_i_36 \n (.I0(data_bytes_r[10]),\n .I1(data_bytes_r[7]),\n .I2(data_bytes_r[8]),\n .I3(data_bytes_r[21]),\n .O(\\zero_r[9]_i_36_n_0 ));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\zero_r[9]_i_37 \n (.I0(data_bytes_r[15]),\n .I1(data_bytes_r[47]),\n .I2(data_bytes_r[46]),\n .I3(data_bytes_r[11]),\n .O(\\zero_r[9]_i_37_n_0 ));\n LUT4 #(\n .INIT(16'hFFFD)) \n \\zero_r[9]_i_38 \n (.I0(data_bytes_r[52]),\n .I1(data_bytes_r[61]),\n .I2(data_bytes_r[15]),\n .I3(data_bytes_r[45]),\n .O(\\zero_r[9]_i_38_n_0 ));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\zero_r[9]_i_39 \n (.I0(data_bytes_r[42]),\n .I1(data_bytes_r[28]),\n .I2(data_bytes_r[40]),\n .I3(data_bytes_r[58]),\n .O(\\zero_r[9]_i_39_n_0 ));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\zero_r[9]_i_40 \n (.I0(data_bytes_r[2]),\n .I1(data_bytes_r[3]),\n .I2(data_bytes_r[1]),\n .I3(data_bytes_r[37]),\n .O(\\zero_r[9]_i_40_n_0 ));\n LUT5 #(\n .INIT(32'h00000004)) \n \\zero_r[9]_i_5 \n (.I0(\\zero_r[9]_i_9_n_0 ),\n .I1(\\zero_r[9]_i_10_n_0 ),\n .I2(\\zero_r[9]_i_11_n_0 ),\n .I3(\\zero_r[9]_i_12_n_0 ),\n .I4(\\zero_r[9]_i_13_n_0 ),\n .O(\\zero_r_reg[9] ));\n LUT5 #(\n .INIT(32'h00000004)) \n \\zero_r[9]_i_7 \n (.I0(\\zero_r[9]_i_14_n_0 ),\n .I1(\\zero_r[9]_i_15_n_0 ),\n .I2(\\zero_r[9]_i_16_n_0 ),\n .I3(\\zero_r[9]_i_17_n_0 ),\n .I4(\\zero_r[9]_i_18_n_0 ),\n .O(\\zero_r_reg[9]_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFBFF)) \n \\zero_r[9]_i_9 \n (.I0(\\zero_r[9]_i_19_n_0 ),\n .I1(data_bytes_r[24]),\n .I2(data_bytes_r[50]),\n .I3(data_bytes_r[62]),\n .I4(data_bytes_r[0]),\n .I5(\\zero_r[9]_i_20_n_0 ),\n .O(\\zero_r[9]_i_9_n_0 ));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_ddr_phy_ocd_edge\n (prev_samp_valid_r,\n o2f_r_reg_0,\n \\ninety_offsets_final_r_reg[0] ,\n f2o_r_reg_0,\n scan_right,\n prev_samp_r,\n \\ninety_offsets_final_r_reg[1] ,\n dec_po_ns,\n inc_po_ns,\n \\ninety_offsets_final_r_reg[0]_0 ,\n reset_scan,\n samp_done_r_reg,\n CLK,\n scanning_right_r_reg,\n scanning_right_r_reg_0,\n \\samp_result_r_reg[1] ,\n \\samp_result_r_reg[0] ,\n rd_active_r1_reg,\n rd_active_r1_reg_0,\n scanning_right,\n ocd_ktap_left_r_reg,\n Q,\n \\stg3_left_lim_reg[5] ,\n rd_active_r1,\n samp_done,\n \\stg3_right_lim_reg[5] ,\n E,\n D,\n reset_scan_r_reg);\n output prev_samp_valid_r;\n output o2f_r_reg_0;\n output \\ninety_offsets_final_r_reg[0] ;\n output f2o_r_reg_0;\n output scan_right;\n output [1:0]prev_samp_r;\n output \\ninety_offsets_final_r_reg[1] ;\n output dec_po_ns;\n output inc_po_ns;\n output \\ninety_offsets_final_r_reg[0]_0 ;\n input reset_scan;\n input samp_done_r_reg;\n input CLK;\n input scanning_right_r_reg;\n input scanning_right_r_reg_0;\n input \\samp_result_r_reg[1] ;\n input \\samp_result_r_reg[0] ;\n input rd_active_r1_reg;\n input rd_active_r1_reg_0;\n input scanning_right;\n input ocd_ktap_left_r_reg;\n input [5:0]Q;\n input [5:0]\\stg3_left_lim_reg[5] ;\n input rd_active_r1;\n input samp_done;\n input [5:0]\\stg3_right_lim_reg[5] ;\n input [0:0]E;\n input [5:0]D;\n input [0:0]reset_scan_r_reg;\n\n wire CLK;\n wire [5:0]D;\n wire [0:0]E;\n wire [5:0]Q;\n wire dec_po_ns;\n wire dec_po_r_i_10_n_0;\n wire dec_po_r_i_11_n_0;\n wire dec_po_r_i_12_n_0;\n wire dec_po_r_i_13_n_0;\n wire dec_po_r_i_14_n_0;\n wire dec_po_r_i_15_n_0;\n wire dec_po_r_i_16_n_0;\n wire dec_po_r_i_17_n_0;\n wire dec_po_r_i_18_n_0;\n wire dec_po_r_i_20_n_0;\n wire dec_po_r_i_21_n_0;\n wire dec_po_r_i_22_n_0;\n wire dec_po_r_i_23_n_0;\n wire dec_po_r_i_24_n_0;\n wire dec_po_r_i_26_n_0;\n wire dec_po_r_i_27_n_0;\n wire dec_po_r_i_28_n_0;\n wire dec_po_r_i_29_n_0;\n wire dec_po_r_i_2_n_0;\n wire dec_po_r_i_30_n_0;\n wire dec_po_r_i_31_n_0;\n wire dec_po_r_i_32_n_0;\n wire dec_po_r_i_3_n_0;\n wire dec_po_r_i_4_n_0;\n wire dec_po_r_i_5_n_0;\n wire dec_po_r_i_6_n_0;\n wire dec_po_r_i_7_n_0;\n wire dec_po_r_i_9_n_0;\n wire dec_po_r_reg_i_19_n_0;\n wire dec_po_r_reg_i_8_n_0;\n wire f2o_r_i_1_n_0;\n wire f2o_r_reg_0;\n wire \\fuzz2oneeighty_r[5]_i_1_n_0 ;\n wire \\fuzz2oneeighty_r[5]_i_2_n_0 ;\n wire \\fuzz2oneeighty_r_reg_n_0_[0] ;\n wire \\fuzz2oneeighty_r_reg_n_0_[1] ;\n wire \\fuzz2oneeighty_r_reg_n_0_[2] ;\n wire \\fuzz2oneeighty_r_reg_n_0_[3] ;\n wire \\fuzz2oneeighty_r_reg_n_0_[4] ;\n wire \\fuzz2oneeighty_r_reg_n_0_[5] ;\n wire \\fuzz2zero_r_reg_n_0_[0] ;\n wire \\fuzz2zero_r_reg_n_0_[1] ;\n wire \\fuzz2zero_r_reg_n_0_[2] ;\n wire \\fuzz2zero_r_reg_n_0_[3] ;\n wire \\fuzz2zero_r_reg_n_0_[4] ;\n wire \\fuzz2zero_r_reg_n_0_[5] ;\n wire inc_po_ns;\n wire inc_po_r_i_2_n_0;\n wire inc_po_r_i_3_n_0;\n wire inc_po_r_i_4_n_0;\n wire \\ninety_offsets_final_r_reg[0] ;\n wire \\ninety_offsets_final_r_reg[0]_0 ;\n wire \\ninety_offsets_final_r_reg[1] ;\n wire o2f_r_reg_0;\n wire ocd_ktap_left_r_reg;\n wire \\oneeighty2fuzz_r_reg_n_0_[0] ;\n wire \\oneeighty2fuzz_r_reg_n_0_[1] ;\n wire \\oneeighty2fuzz_r_reg_n_0_[2] ;\n wire \\oneeighty2fuzz_r_reg_n_0_[3] ;\n wire \\oneeighty2fuzz_r_reg_n_0_[4] ;\n wire \\oneeighty2fuzz_r_reg_n_0_[5] ;\n wire [1:0]prev_samp_r;\n wire prev_samp_valid_r;\n wire rd_active_r1;\n wire rd_active_r1_reg;\n wire rd_active_r1_reg_0;\n wire reset_scan;\n wire [0:0]reset_scan_r_reg;\n wire samp_done;\n wire samp_done_r_reg;\n wire \\samp_result_r_reg[0] ;\n wire \\samp_result_r_reg[1] ;\n wire scan_right;\n wire scan_right_r_i_1_n_0;\n wire scanning_right;\n wire scanning_right_r_reg;\n wire scanning_right_r_reg_0;\n wire [5:0]\\stg3_left_lim_reg[5] ;\n wire [5:0]\\stg3_right_lim_reg[5] ;\n wire \\u_ocd_po_cntlr/noise ;\n wire z2f_r_i_1_n_0;\n wire z2f_r_reg_n_0;\n wire zero2fuzz_ns;\n wire \\zero2fuzz_r_reg_n_0_[0] ;\n wire \\zero2fuzz_r_reg_n_0_[1] ;\n wire \\zero2fuzz_r_reg_n_0_[2] ;\n wire \\zero2fuzz_r_reg_n_0_[3] ;\n wire \\zero2fuzz_r_reg_n_0_[4] ;\n wire \\zero2fuzz_r_reg_n_0_[5] ;\n\n LUT6 #(\n .INIT(64'hFEE00000FFFFFEE0)) \n dec_po_r_i_1\n (.I0(dec_po_r_i_2_n_0),\n .I1(dec_po_r_i_3_n_0),\n .I2(dec_po_r_i_4_n_0),\n .I3(Q[4]),\n .I4(Q[5]),\n .I5(dec_po_r_i_5_n_0),\n .O(dec_po_ns));\n (* SOFT_HLUTNM = \"soft_lutpair364\" *) \n LUT3 #(\n .INIT(8'h8A)) \n dec_po_r_i_10\n (.I0(\\ninety_offsets_final_r_reg[0] ),\n .I1(z2f_r_reg_n_0),\n .I2(f2o_r_reg_0),\n .O(dec_po_r_i_10_n_0));\n LUT5 #(\n .INIT(32'hBF8CB380)) \n dec_po_r_i_11\n (.I0(\\zero2fuzz_r_reg_n_0_[3] ),\n .I1(f2o_r_reg_0),\n .I2(z2f_r_reg_n_0),\n .I3(\\stg3_left_lim_reg[5] [3]),\n .I4(\\fuzz2oneeighty_r_reg_n_0_[3] ),\n .O(dec_po_r_i_11_n_0));\n LUT5 #(\n .INIT(32'hBF8CB380)) \n dec_po_r_i_12\n (.I0(\\zero2fuzz_r_reg_n_0_[4] ),\n .I1(f2o_r_reg_0),\n .I2(z2f_r_reg_n_0),\n .I3(\\stg3_left_lim_reg[5] [4]),\n .I4(\\fuzz2oneeighty_r_reg_n_0_[4] ),\n .O(dec_po_r_i_12_n_0));\n LUT6 #(\n .INIT(64'h1010001015155515)) \n dec_po_r_i_13\n (.I0(ocd_ktap_left_r_reg),\n .I1(\\zero2fuzz_r_reg_n_0_[4] ),\n .I2(z2f_r_reg_n_0),\n .I3(f2o_r_reg_0),\n .I4(\\ninety_offsets_final_r_reg[0] ),\n .I5(dec_po_r_i_23_n_0),\n .O(dec_po_r_i_13_n_0));\n LUT6 #(\n .INIT(64'h0000FF00AE00AE00)) \n dec_po_r_i_14\n (.I0(dec_po_r_i_24_n_0),\n .I1(\\u_ocd_po_cntlr/noise ),\n .I2(\\zero2fuzz_r_reg_n_0_[5] ),\n .I3(ocd_ktap_left_r_reg),\n .I4(\\fuzz2zero_r_reg_n_0_[5] ),\n .I5(dec_po_r_i_10_n_0),\n .O(dec_po_r_i_14_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair365\" *) \n LUT3 #(\n .INIT(8'h4F)) \n dec_po_r_i_15\n (.I0(\\ninety_offsets_final_r_reg[0] ),\n .I1(f2o_r_reg_0),\n .I2(z2f_r_reg_n_0),\n .O(dec_po_r_i_15_n_0));\n LUT6 #(\n .INIT(64'hBF8CBF80B380BF80)) \n dec_po_r_i_16\n (.I0(\\fuzz2oneeighty_r_reg_n_0_[5] ),\n .I1(f2o_r_reg_0),\n .I2(z2f_r_reg_n_0),\n .I3(\\stg3_right_lim_reg[5] [5]),\n .I4(o2f_r_reg_0),\n .I5(\\oneeighty2fuzz_r_reg_n_0_[5] ),\n .O(dec_po_r_i_16_n_0));\n LUT6 #(\n .INIT(64'h0000000035355535)) \n dec_po_r_i_17\n (.I0(dec_po_r_i_26_n_0),\n .I1(\\zero2fuzz_r_reg_n_0_[1] ),\n .I2(z2f_r_reg_n_0),\n .I3(f2o_r_reg_0),\n .I4(\\ninety_offsets_final_r_reg[0] ),\n .I5(ocd_ktap_left_r_reg),\n .O(dec_po_r_i_17_n_0));\n LUT5 #(\n .INIT(32'hBF8CB380)) \n dec_po_r_i_18\n (.I0(\\zero2fuzz_r_reg_n_0_[1] ),\n .I1(f2o_r_reg_0),\n .I2(z2f_r_reg_n_0),\n .I3(\\stg3_left_lim_reg[5] [1]),\n .I4(\\fuzz2oneeighty_r_reg_n_0_[1] ),\n .O(dec_po_r_i_18_n_0));\n LUT6 #(\n .INIT(64'h008E00FF0000008E)) \n dec_po_r_i_2\n (.I0(Q[1]),\n .I1(dec_po_r_i_6_n_0),\n .I2(dec_po_r_i_7_n_0),\n .I3(inc_po_r_i_3_n_0),\n .I4(dec_po_r_reg_i_8_n_0),\n .I5(Q[2]),\n .O(dec_po_r_i_2_n_0));\n LUT5 #(\n .INIT(32'hEFAA20AA)) \n dec_po_r_i_20\n (.I0(dec_po_r_i_29_n_0),\n .I1(\\ninety_offsets_final_r_reg[0] ),\n .I2(f2o_r_reg_0),\n .I3(z2f_r_reg_n_0),\n .I4(\\zero2fuzz_r_reg_n_0_[2] ),\n .O(dec_po_r_i_20_n_0));\n LUT5 #(\n .INIT(32'hBFBB8088)) \n dec_po_r_i_21\n (.I0(\\fuzz2zero_r_reg_n_0_[2] ),\n .I1(\\ninety_offsets_final_r_reg[0] ),\n .I2(z2f_r_reg_n_0),\n .I3(f2o_r_reg_0),\n .I4(dec_po_r_i_30_n_0),\n .O(dec_po_r_i_21_n_0));\n LUT6 #(\n .INIT(64'hBF8CBF80B380BF80)) \n dec_po_r_i_22\n (.I0(\\fuzz2oneeighty_r_reg_n_0_[3] ),\n .I1(f2o_r_reg_0),\n .I2(z2f_r_reg_n_0),\n .I3(\\stg3_right_lim_reg[5] [3]),\n .I4(o2f_r_reg_0),\n .I5(\\oneeighty2fuzz_r_reg_n_0_[3] ),\n .O(dec_po_r_i_22_n_0));\n LUT6 #(\n .INIT(64'hBF8CBF80B380BF80)) \n dec_po_r_i_23\n (.I0(\\fuzz2oneeighty_r_reg_n_0_[4] ),\n .I1(f2o_r_reg_0),\n .I2(z2f_r_reg_n_0),\n .I3(\\stg3_right_lim_reg[5] [4]),\n .I4(o2f_r_reg_0),\n .I5(\\oneeighty2fuzz_r_reg_n_0_[4] ),\n .O(dec_po_r_i_23_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair364\" *) \n LUT4 #(\n .INIT(16'h0437)) \n dec_po_r_i_24\n (.I0(\\fuzz2oneeighty_r_reg_n_0_[5] ),\n .I1(f2o_r_reg_0),\n .I2(z2f_r_reg_n_0),\n .I3(\\stg3_left_lim_reg[5] [5]),\n .O(dec_po_r_i_24_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair362\" *) \n LUT2 #(\n .INIT(4'h8)) \n dec_po_r_i_25\n (.I0(f2o_r_reg_0),\n .I1(z2f_r_reg_n_0),\n .O(\\u_ocd_po_cntlr/noise ));\n LUT6 #(\n .INIT(64'hBF8CBF80B380BF80)) \n dec_po_r_i_26\n (.I0(\\fuzz2oneeighty_r_reg_n_0_[1] ),\n .I1(f2o_r_reg_0),\n .I2(z2f_r_reg_n_0),\n .I3(\\stg3_right_lim_reg[5] [1]),\n .I4(o2f_r_reg_0),\n .I5(\\oneeighty2fuzz_r_reg_n_0_[1] ),\n .O(dec_po_r_i_26_n_0));\n LUT5 #(\n .INIT(32'h8A00BAFF)) \n dec_po_r_i_27\n (.I0(\\zero2fuzz_r_reg_n_0_[0] ),\n .I1(\\ninety_offsets_final_r_reg[0] ),\n .I2(f2o_r_reg_0),\n .I3(z2f_r_reg_n_0),\n .I4(dec_po_r_i_31_n_0),\n .O(dec_po_r_i_27_n_0));\n LUT5 #(\n .INIT(32'hBFBB8088)) \n dec_po_r_i_28\n (.I0(\\fuzz2zero_r_reg_n_0_[0] ),\n .I1(\\ninety_offsets_final_r_reg[0] ),\n .I2(z2f_r_reg_n_0),\n .I3(f2o_r_reg_0),\n .I4(dec_po_r_i_32_n_0),\n .O(dec_po_r_i_28_n_0));\n LUT6 #(\n .INIT(64'hFFAAE2AA00AAE2AA)) \n dec_po_r_i_29\n (.I0(\\stg3_right_lim_reg[5] [2]),\n .I1(o2f_r_reg_0),\n .I2(\\oneeighty2fuzz_r_reg_n_0_[2] ),\n .I3(f2o_r_reg_0),\n .I4(z2f_r_reg_n_0),\n .I5(\\fuzz2oneeighty_r_reg_n_0_[2] ),\n .O(dec_po_r_i_29_n_0));\n LUT6 #(\n .INIT(64'hAEAABFAA00000000)) \n dec_po_r_i_3\n (.I0(dec_po_r_i_9_n_0),\n .I1(dec_po_r_i_10_n_0),\n .I2(\\fuzz2zero_r_reg_n_0_[3] ),\n .I3(ocd_ktap_left_r_reg),\n .I4(dec_po_r_i_11_n_0),\n .I5(Q[3]),\n .O(dec_po_r_i_3_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair362\" *) \n LUT5 #(\n .INIT(32'hBF8CB380)) \n dec_po_r_i_30\n (.I0(\\zero2fuzz_r_reg_n_0_[2] ),\n .I1(f2o_r_reg_0),\n .I2(z2f_r_reg_n_0),\n .I3(\\stg3_left_lim_reg[5] [2]),\n .I4(\\fuzz2oneeighty_r_reg_n_0_[2] ),\n .O(dec_po_r_i_30_n_0));\n LUT6 #(\n .INIT(64'h00FF55551D1D5555)) \n dec_po_r_i_31\n (.I0(\\stg3_right_lim_reg[5] [0]),\n .I1(o2f_r_reg_0),\n .I2(\\oneeighty2fuzz_r_reg_n_0_[0] ),\n .I3(\\fuzz2oneeighty_r_reg_n_0_[0] ),\n .I4(f2o_r_reg_0),\n .I5(z2f_r_reg_n_0),\n .O(dec_po_r_i_31_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair363\" *) \n LUT5 #(\n .INIT(32'hFACA0ACA)) \n dec_po_r_i_32\n (.I0(\\stg3_left_lim_reg[5] [0]),\n .I1(\\fuzz2oneeighty_r_reg_n_0_[0] ),\n .I2(f2o_r_reg_0),\n .I3(z2f_r_reg_n_0),\n .I4(\\zero2fuzz_r_reg_n_0_[0] ),\n .O(dec_po_r_i_32_n_0));\n LUT5 #(\n .INIT(32'hFFFF2070)) \n dec_po_r_i_4\n (.I0(dec_po_r_i_10_n_0),\n .I1(\\fuzz2zero_r_reg_n_0_[4] ),\n .I2(ocd_ktap_left_r_reg),\n .I3(dec_po_r_i_12_n_0),\n .I4(dec_po_r_i_13_n_0),\n .O(dec_po_r_i_4_n_0));\n LUT5 #(\n .INIT(32'h55544544)) \n dec_po_r_i_5\n (.I0(dec_po_r_i_14_n_0),\n .I1(ocd_ktap_left_r_reg),\n .I2(dec_po_r_i_15_n_0),\n .I3(\\zero2fuzz_r_reg_n_0_[5] ),\n .I4(dec_po_r_i_16_n_0),\n .O(dec_po_r_i_5_n_0));\n LUT5 #(\n .INIT(32'hABEFAAAA)) \n dec_po_r_i_6\n (.I0(dec_po_r_i_17_n_0),\n .I1(dec_po_r_i_10_n_0),\n .I2(dec_po_r_i_18_n_0),\n .I3(\\fuzz2zero_r_reg_n_0_[1] ),\n .I4(ocd_ktap_left_r_reg),\n .O(dec_po_r_i_6_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair366\" *) \n LUT2 #(\n .INIT(4'hB)) \n dec_po_r_i_7\n (.I0(dec_po_r_reg_i_19_n_0),\n .I1(Q[0]),\n .O(dec_po_r_i_7_n_0));\n LUT6 #(\n .INIT(64'h1010001015155515)) \n dec_po_r_i_9\n (.I0(ocd_ktap_left_r_reg),\n .I1(\\zero2fuzz_r_reg_n_0_[3] ),\n .I2(z2f_r_reg_n_0),\n .I3(f2o_r_reg_0),\n .I4(\\ninety_offsets_final_r_reg[0] ),\n .I5(dec_po_r_i_22_n_0),\n .O(dec_po_r_i_9_n_0));\n MUXF7 dec_po_r_reg_i_19\n (.I0(dec_po_r_i_27_n_0),\n .I1(dec_po_r_i_28_n_0),\n .O(dec_po_r_reg_i_19_n_0),\n .S(ocd_ktap_left_r_reg));\n MUXF7 dec_po_r_reg_i_8\n (.I0(dec_po_r_i_20_n_0),\n .I1(dec_po_r_i_21_n_0),\n .O(dec_po_r_reg_i_8_n_0),\n .S(ocd_ktap_left_r_reg));\n LUT6 #(\n .INIT(64'hFFFFFFFF00000020)) \n f2o_r_i_1\n (.I0(rd_active_r1_reg),\n .I1(rd_active_r1_reg_0),\n .I2(scanning_right),\n .I3(\\fuzz2oneeighty_r[5]_i_2_n_0 ),\n .I4(prev_samp_r[1]),\n .I5(f2o_r_reg_0),\n .O(f2o_r_i_1_n_0));\n FDRE f2o_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(f2o_r_i_1_n_0),\n .Q(f2o_r_reg_0),\n .R(reset_scan));\n FDRE f2z_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(scanning_right_r_reg_0),\n .Q(\\ninety_offsets_final_r_reg[0] ),\n .R(reset_scan));\n LUT6 #(\n .INIT(64'h0000000000100000)) \n \\fuzz2oneeighty_r[5]_i_1 \n (.I0(prev_samp_r[1]),\n .I1(\\fuzz2oneeighty_r[5]_i_2_n_0 ),\n .I2(scanning_right),\n .I3(rd_active_r1_reg_0),\n .I4(rd_active_r1_reg),\n .I5(reset_scan),\n .O(\\fuzz2oneeighty_r[5]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h7F)) \n \\fuzz2oneeighty_r[5]_i_2 \n (.I0(prev_samp_valid_r),\n .I1(rd_active_r1),\n .I2(samp_done),\n .O(\\fuzz2oneeighty_r[5]_i_2_n_0 ));\n FDRE \\fuzz2oneeighty_r_reg[0] \n (.C(CLK),\n .CE(\\fuzz2oneeighty_r[5]_i_1_n_0 ),\n .D(Q[0]),\n .Q(\\fuzz2oneeighty_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\fuzz2oneeighty_r_reg[1] \n (.C(CLK),\n .CE(\\fuzz2oneeighty_r[5]_i_1_n_0 ),\n .D(Q[1]),\n .Q(\\fuzz2oneeighty_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE \\fuzz2oneeighty_r_reg[2] \n (.C(CLK),\n .CE(\\fuzz2oneeighty_r[5]_i_1_n_0 ),\n .D(Q[2]),\n .Q(\\fuzz2oneeighty_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE \\fuzz2oneeighty_r_reg[3] \n (.C(CLK),\n .CE(\\fuzz2oneeighty_r[5]_i_1_n_0 ),\n .D(Q[3]),\n .Q(\\fuzz2oneeighty_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE \\fuzz2oneeighty_r_reg[4] \n (.C(CLK),\n .CE(\\fuzz2oneeighty_r[5]_i_1_n_0 ),\n .D(Q[4]),\n .Q(\\fuzz2oneeighty_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE \\fuzz2oneeighty_r_reg[5] \n (.C(CLK),\n .CE(\\fuzz2oneeighty_r[5]_i_1_n_0 ),\n .D(Q[5]),\n .Q(\\fuzz2oneeighty_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE \\fuzz2zero_r_reg[0] \n (.C(CLK),\n .CE(E),\n .D(Q[0]),\n .Q(\\fuzz2zero_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\fuzz2zero_r_reg[1] \n (.C(CLK),\n .CE(E),\n .D(Q[1]),\n .Q(\\fuzz2zero_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE \\fuzz2zero_r_reg[2] \n (.C(CLK),\n .CE(E),\n .D(Q[2]),\n .Q(\\fuzz2zero_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE \\fuzz2zero_r_reg[3] \n (.C(CLK),\n .CE(E),\n .D(Q[3]),\n .Q(\\fuzz2zero_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE \\fuzz2zero_r_reg[4] \n (.C(CLK),\n .CE(E),\n .D(Q[4]),\n .Q(\\fuzz2zero_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE \\fuzz2zero_r_reg[5] \n (.C(CLK),\n .CE(E),\n .D(Q[5]),\n .Q(\\fuzz2zero_r_reg_n_0_[5] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h70F770F770F710F1)) \n inc_po_r_i_1\n (.I0(dec_po_r_i_4_n_0),\n .I1(Q[4]),\n .I2(dec_po_r_i_5_n_0),\n .I3(Q[5]),\n .I4(inc_po_r_i_2_n_0),\n .I5(inc_po_r_i_3_n_0),\n .O(inc_po_ns));\n LUT6 #(\n .INIT(64'h0000000071FF0071)) \n inc_po_r_i_2\n (.I0(dec_po_r_i_6_n_0),\n .I1(Q[1]),\n .I2(inc_po_r_i_4_n_0),\n .I3(Q[2]),\n .I4(dec_po_r_reg_i_8_n_0),\n .I5(dec_po_r_i_3_n_0),\n .O(inc_po_r_i_2_n_0));\n LUT6 #(\n .INIT(64'h0000000051554055)) \n inc_po_r_i_3\n (.I0(dec_po_r_i_9_n_0),\n .I1(dec_po_r_i_10_n_0),\n .I2(\\fuzz2zero_r_reg_n_0_[3] ),\n .I3(ocd_ktap_left_r_reg),\n .I4(dec_po_r_i_11_n_0),\n .I5(Q[3]),\n .O(inc_po_r_i_3_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair366\" *) \n LUT2 #(\n .INIT(4'h2)) \n inc_po_r_i_4\n (.I0(dec_po_r_reg_i_19_n_0),\n .I1(Q[0]),\n .O(inc_po_r_i_4_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair365\" *) \n LUT3 #(\n .INIT(8'h20)) \n \\ninety_offsets_final_r[0]_i_1 \n (.I0(f2o_r_reg_0),\n .I1(\\ninety_offsets_final_r_reg[0] ),\n .I2(z2f_r_reg_n_0),\n .O(\\ninety_offsets_final_r_reg[0]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair363\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\ninety_offsets_final_r[1]_i_1 \n (.I0(f2o_r_reg_0),\n .I1(z2f_r_reg_n_0),\n .O(\\ninety_offsets_final_r_reg[1] ));\n FDRE o2f_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(scanning_right_r_reg),\n .Q(o2f_r_reg_0),\n .R(reset_scan));\n FDRE \\oneeighty2fuzz_r_reg[0] \n (.C(CLK),\n .CE(reset_scan_r_reg),\n .D(D[0]),\n .Q(\\oneeighty2fuzz_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\oneeighty2fuzz_r_reg[1] \n (.C(CLK),\n .CE(reset_scan_r_reg),\n .D(D[1]),\n .Q(\\oneeighty2fuzz_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE \\oneeighty2fuzz_r_reg[2] \n (.C(CLK),\n .CE(reset_scan_r_reg),\n .D(D[2]),\n .Q(\\oneeighty2fuzz_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE \\oneeighty2fuzz_r_reg[3] \n (.C(CLK),\n .CE(reset_scan_r_reg),\n .D(D[3]),\n .Q(\\oneeighty2fuzz_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE \\oneeighty2fuzz_r_reg[4] \n (.C(CLK),\n .CE(reset_scan_r_reg),\n .D(D[4]),\n .Q(\\oneeighty2fuzz_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE \\oneeighty2fuzz_r_reg[5] \n (.C(CLK),\n .CE(reset_scan_r_reg),\n .D(D[5]),\n .Q(\\oneeighty2fuzz_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE \\prev_samp_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\samp_result_r_reg[0] ),\n .Q(prev_samp_r[0]),\n .R(1'b0));\n FDRE \\prev_samp_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\samp_result_r_reg[1] ),\n .Q(prev_samp_r[1]),\n .R(1'b0));\n FDRE prev_samp_valid_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(samp_done_r_reg),\n .Q(prev_samp_valid_r),\n .R(reset_scan));\n LUT6 #(\n .INIT(64'h0000000000000010)) \n scan_right_r_i_1\n (.I0(rd_active_r1_reg_0),\n .I1(scanning_right),\n .I2(prev_samp_r[0]),\n .I3(prev_samp_r[1]),\n .I4(\\fuzz2oneeighty_r[5]_i_2_n_0 ),\n .I5(reset_scan),\n .O(scan_right_r_i_1_n_0));\n FDRE scan_right_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(scan_right_r_i_1_n_0),\n .Q(scan_right),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFFFFFFF00000400)) \n z2f_r_i_1\n (.I0(\\fuzz2oneeighty_r[5]_i_2_n_0 ),\n .I1(scanning_right),\n .I2(rd_active_r1_reg_0),\n .I3(prev_samp_r[0]),\n .I4(prev_samp_r[1]),\n .I5(z2f_r_reg_n_0),\n .O(z2f_r_i_1_n_0));\n FDRE z2f_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(z2f_r_i_1_n_0),\n .Q(z2f_r_reg_n_0),\n .R(reset_scan));\n LUT6 #(\n .INIT(64'h0000000000000400)) \n \\zero2fuzz_r[5]_i_1 \n (.I0(prev_samp_r[1]),\n .I1(prev_samp_r[0]),\n .I2(rd_active_r1_reg_0),\n .I3(scanning_right),\n .I4(\\fuzz2oneeighty_r[5]_i_2_n_0 ),\n .I5(reset_scan),\n .O(zero2fuzz_ns));\n FDRE \\zero2fuzz_r_reg[0] \n (.C(CLK),\n .CE(zero2fuzz_ns),\n .D(D[0]),\n .Q(\\zero2fuzz_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\zero2fuzz_r_reg[1] \n (.C(CLK),\n .CE(zero2fuzz_ns),\n .D(D[1]),\n .Q(\\zero2fuzz_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE \\zero2fuzz_r_reg[2] \n (.C(CLK),\n .CE(zero2fuzz_ns),\n .D(D[2]),\n .Q(\\zero2fuzz_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE \\zero2fuzz_r_reg[3] \n (.C(CLK),\n .CE(zero2fuzz_ns),\n .D(D[3]),\n .Q(\\zero2fuzz_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE \\zero2fuzz_r_reg[4] \n (.C(CLK),\n .CE(zero2fuzz_ns),\n .D(D[4]),\n .Q(\\zero2fuzz_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE \\zero2fuzz_r_reg[5] \n (.C(CLK),\n .CE(zero2fuzz_ns),\n .D(D[5]),\n .Q(\\zero2fuzz_r_reg_n_0_[5] ),\n .R(1'b0));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_ddr_phy_ocd_lim\n (lim_start_r,\n lim2poc_ktap_right,\n prech_req_r_reg_0,\n lim2stg2_inc,\n lim2stg3_dec,\n lim2stg3_inc,\n lim2stg2_dec,\n lim2poc_rdy,\n done_r_reg_0,\n po_stg23_sel_r_reg,\n stg3_dec2init_val_r_reg_0,\n stg3_inc2init_val_r_reg_0,\n \\stg2_tap_cnt_reg[0]_0 ,\n \\stg2_tap_cnt_reg[3]_0 ,\n \\stg3_tap_cnt_reg[2]_0 ,\n scanning_right_r_reg,\n scanning_right_r_reg_0,\n oclkdelay_center_calib_start_r_reg,\n oclkdelay_center_calib_start_r_reg_0,\n \\init_state_r_reg[6] ,\n \\init_state_r_reg[5] ,\n \\init_state_r_reg[4] ,\n rstdiv0_sync_r1_reg_rep__10,\n CLK,\n lim_start,\n done_r_reg_1,\n rstdiv0_sync_r1_reg_rep__9,\n rstdiv0_sync_r1_reg_rep__26,\n \\po_wait_r_reg[0] ,\n \\sm_r_reg[2] ,\n lim_start_r_reg_0,\n prech_done,\n \\wl_po_fine_cnt_reg[17] ,\n rstdiv0_sync_r1_reg_rep__20,\n \\byte_r_reg[0] ,\n Q,\n \\stg2_tap_cnt_reg[2]_0 ,\n \\wl_po_fine_cnt_reg[3] ,\n \\wl_po_fine_cnt_reg[14] ,\n \\wl_po_fine_cnt_reg[18] ,\n \\rise_lead_r_reg[5] ,\n rstdiv0_sync_r1_reg_rep__26_0,\n po_rdy,\n scan_right,\n scanning_right,\n \\stg3_r_reg[5] ,\n o2f_r_reg,\n \\mmcm_init_trail_reg[0]_0 ,\n \\mmcm_current_reg[0]_0 ,\n prbs_rdlvl_done_reg_rep,\n ocd_prech_req_r_reg,\n oclk_center_write_resume,\n cnt_cmd_done_r,\n rstdiv0_sync_r1_reg_rep__19,\n rstdiv0_sync_r1_reg_rep__11,\n D,\n oclkdelay_calib_done_r_reg);\n output lim_start_r;\n output lim2poc_ktap_right;\n output prech_req_r_reg_0;\n output lim2stg2_inc;\n output lim2stg3_dec;\n output lim2stg3_inc;\n output lim2stg2_dec;\n output lim2poc_rdy;\n output done_r_reg_0;\n output po_stg23_sel_r_reg;\n output stg3_dec2init_val_r_reg_0;\n output stg3_inc2init_val_r_reg_0;\n output \\stg2_tap_cnt_reg[0]_0 ;\n output [2:0]\\stg2_tap_cnt_reg[3]_0 ;\n output [2:0]\\stg3_tap_cnt_reg[2]_0 ;\n output scanning_right_r_reg;\n output [5:0]scanning_right_r_reg_0;\n output oclkdelay_center_calib_start_r_reg;\n output [5:0]oclkdelay_center_calib_start_r_reg_0;\n output \\init_state_r_reg[6] ;\n output \\init_state_r_reg[5] ;\n output \\init_state_r_reg[4] ;\n input rstdiv0_sync_r1_reg_rep__10;\n input CLK;\n input lim_start;\n input done_r_reg_1;\n input rstdiv0_sync_r1_reg_rep__9;\n input rstdiv0_sync_r1_reg_rep__26;\n input \\po_wait_r_reg[0] ;\n input \\sm_r_reg[2] ;\n input lim_start_r_reg_0;\n input prech_done;\n input \\wl_po_fine_cnt_reg[17] ;\n input rstdiv0_sync_r1_reg_rep__20;\n input \\byte_r_reg[0] ;\n input [5:0]Q;\n input \\stg2_tap_cnt_reg[2]_0 ;\n input \\wl_po_fine_cnt_reg[3] ;\n input [1:0]\\wl_po_fine_cnt_reg[14] ;\n input \\wl_po_fine_cnt_reg[18] ;\n input [5:0]\\rise_lead_r_reg[5] ;\n input rstdiv0_sync_r1_reg_rep__26_0;\n input po_rdy;\n input scan_right;\n input scanning_right;\n input [5:0]\\stg3_r_reg[5] ;\n input o2f_r_reg;\n input \\mmcm_init_trail_reg[0]_0 ;\n input \\mmcm_current_reg[0]_0 ;\n input prbs_rdlvl_done_reg_rep;\n input ocd_prech_req_r_reg;\n input oclk_center_write_resume;\n input cnt_cmd_done_r;\n input [0:0]rstdiv0_sync_r1_reg_rep__19;\n input [0:0]rstdiv0_sync_r1_reg_rep__11;\n input [2:0]D;\n input [5:0]oclkdelay_calib_done_r_reg;\n\n wire CLK;\n wire [2:0]D;\n wire [5:0]Q;\n wire \\byte_r_reg[0] ;\n wire cnt_cmd_done_r;\n wire detect_done_r;\n wire done_r_i_1__0_n_0;\n wire done_r_reg_0;\n wire done_r_reg_1;\n wire \\init_state_r_reg[4] ;\n wire \\init_state_r_reg[5] ;\n wire \\init_state_r_reg[6] ;\n wire ktap_right_r_i_1_n_0;\n wire ktap_right_r_i_2_n_0;\n wire lim2init_write_request;\n wire lim2poc_ktap_right;\n wire lim2poc_rdy;\n wire lim2stg2_dec;\n wire lim2stg2_inc;\n wire lim2stg3_dec;\n wire lim2stg3_inc;\n wire lim_nxt_state;\n wire lim_start;\n wire lim_start_r;\n wire lim_start_r_reg_0;\n wire [13:0]lim_state;\n wire \\lim_state[0]_i_1_n_0 ;\n wire \\lim_state[0]_i_2_n_0 ;\n wire \\lim_state[0]_i_3_n_0 ;\n wire \\lim_state[0]_i_4_n_0 ;\n wire \\lim_state[0]_i_5_n_0 ;\n wire \\lim_state[10]_i_1_n_0 ;\n wire \\lim_state[10]_i_2_n_0 ;\n wire \\lim_state[10]_i_3_n_0 ;\n wire \\lim_state[11]_i_1_n_0 ;\n wire \\lim_state[11]_i_2_n_0 ;\n wire \\lim_state[11]_i_3_n_0 ;\n wire \\lim_state[11]_i_4_n_0 ;\n wire \\lim_state[11]_i_5_n_0 ;\n wire \\lim_state[11]_i_6_n_0 ;\n wire \\lim_state[11]_i_7_n_0 ;\n wire \\lim_state[12]_i_1_n_0 ;\n wire \\lim_state[12]_i_2_n_0 ;\n wire \\lim_state[12]_i_3_n_0 ;\n wire \\lim_state[12]_i_4_n_0 ;\n wire \\lim_state[12]_i_5_n_0 ;\n wire \\lim_state[12]_i_7_n_0 ;\n wire \\lim_state[13]_i_10_n_0 ;\n wire \\lim_state[13]_i_11_n_0 ;\n wire \\lim_state[13]_i_12_n_0 ;\n wire \\lim_state[13]_i_13_n_0 ;\n wire \\lim_state[13]_i_14_n_0 ;\n wire \\lim_state[13]_i_2_n_0 ;\n wire \\lim_state[13]_i_3_n_0 ;\n wire \\lim_state[13]_i_4_n_0 ;\n wire \\lim_state[13]_i_5_n_0 ;\n wire \\lim_state[13]_i_6_n_0 ;\n wire \\lim_state[13]_i_7_n_0 ;\n wire \\lim_state[13]_i_8_n_0 ;\n wire \\lim_state[13]_i_9_n_0 ;\n wire \\lim_state[1]_i_1_n_0 ;\n wire \\lim_state[1]_i_2_n_0 ;\n wire \\lim_state[2]_i_1_n_0 ;\n wire \\lim_state[2]_i_2_n_0 ;\n wire \\lim_state[2]_i_3_n_0 ;\n wire \\lim_state[2]_i_4_n_0 ;\n wire \\lim_state[3]_i_1_n_0 ;\n wire \\lim_state[4]_i_1_n_0 ;\n wire \\lim_state[4]_i_2_n_0 ;\n wire \\lim_state[4]_i_3_n_0 ;\n wire \\lim_state[5]_i_1_n_0 ;\n wire \\lim_state[5]_i_2_n_0 ;\n wire \\lim_state[6]_i_10_n_0 ;\n wire \\lim_state[6]_i_11_n_0 ;\n wire \\lim_state[6]_i_12_n_0 ;\n wire \\lim_state[6]_i_13_n_0 ;\n wire \\lim_state[6]_i_14_n_0 ;\n wire \\lim_state[6]_i_15_n_0 ;\n wire \\lim_state[6]_i_16_n_0 ;\n wire \\lim_state[6]_i_17_n_0 ;\n wire \\lim_state[6]_i_18_n_0 ;\n wire \\lim_state[6]_i_19_n_0 ;\n wire \\lim_state[6]_i_1_n_0 ;\n wire \\lim_state[6]_i_20_n_0 ;\n wire \\lim_state[6]_i_21_n_0 ;\n wire \\lim_state[6]_i_22_n_0 ;\n wire \\lim_state[6]_i_2_n_0 ;\n wire \\lim_state[6]_i_3_n_0 ;\n wire \\lim_state[6]_i_4_n_0 ;\n wire \\lim_state[6]_i_5_n_0 ;\n wire \\lim_state[6]_i_6_n_0 ;\n wire \\lim_state[6]_i_7_n_0 ;\n wire \\lim_state[6]_i_8_n_0 ;\n wire \\lim_state[6]_i_9_n_0 ;\n wire \\lim_state[7]_i_1_n_0 ;\n wire \\lim_state[7]_i_2_n_0 ;\n wire \\lim_state[7]_i_3_n_0 ;\n wire \\lim_state[8]_i_1_n_0 ;\n wire \\lim_state[9]_i_1_n_0 ;\n wire \\lim_state[9]_i_2_n_0 ;\n wire \\lim_state[9]_i_3_n_0 ;\n wire \\mmcm_current[0]_i_1_n_0 ;\n wire \\mmcm_current[0]_i_2_n_0 ;\n wire \\mmcm_current[1]_i_1_n_0 ;\n wire \\mmcm_current[1]_i_2_n_0 ;\n wire \\mmcm_current[2]_i_1_n_0 ;\n wire \\mmcm_current[2]_i_2_n_0 ;\n wire \\mmcm_current[3]_i_1_n_0 ;\n wire \\mmcm_current[3]_i_2_n_0 ;\n wire \\mmcm_current[4]_i_1_n_0 ;\n wire \\mmcm_current[4]_i_2_n_0 ;\n wire \\mmcm_current[5]_i_1_n_0 ;\n wire \\mmcm_current[5]_i_2_n_0 ;\n wire \\mmcm_current_reg[0]_0 ;\n wire \\mmcm_current_reg_n_0_[0] ;\n wire \\mmcm_current_reg_n_0_[1] ;\n wire \\mmcm_current_reg_n_0_[2] ;\n wire \\mmcm_current_reg_n_0_[3] ;\n wire \\mmcm_current_reg_n_0_[4] ;\n wire \\mmcm_current_reg_n_0_[5] ;\n wire mmcm_init_lead;\n wire \\mmcm_init_lead[5]_i_2_n_0 ;\n wire \\mmcm_init_lead[5]_i_3_n_0 ;\n wire \\mmcm_init_lead[5]_i_4_n_0 ;\n wire \\mmcm_init_lead[5]_i_5_n_0 ;\n wire \\mmcm_init_lead[5]_i_6_n_0 ;\n wire \\mmcm_init_lead[5]_i_7_n_0 ;\n wire \\mmcm_init_lead[5]_i_8_n_0 ;\n wire \\mmcm_init_lead_reg_n_0_[0] ;\n wire \\mmcm_init_lead_reg_n_0_[1] ;\n wire \\mmcm_init_lead_reg_n_0_[2] ;\n wire \\mmcm_init_lead_reg_n_0_[3] ;\n wire \\mmcm_init_lead_reg_n_0_[4] ;\n wire \\mmcm_init_lead_reg_n_0_[5] ;\n wire mmcm_init_trail;\n wire \\mmcm_init_trail[5]_i_2_n_0 ;\n wire \\mmcm_init_trail[5]_i_3_n_0 ;\n wire \\mmcm_init_trail[5]_i_4_n_0 ;\n wire \\mmcm_init_trail_reg[0]_0 ;\n wire \\mmcm_init_trail_reg_n_0_[0] ;\n wire \\mmcm_init_trail_reg_n_0_[1] ;\n wire \\mmcm_init_trail_reg_n_0_[2] ;\n wire \\mmcm_init_trail_reg_n_0_[3] ;\n wire \\mmcm_init_trail_reg_n_0_[4] ;\n wire \\mmcm_init_trail_reg_n_0_[5] ;\n wire mod_sub0_return0__14_carry__0_i_1_n_0;\n wire mod_sub0_return0__14_carry__0_i_2_n_0;\n wire mod_sub0_return0__14_carry__0_n_1;\n wire mod_sub0_return0__14_carry__0_n_3;\n wire mod_sub0_return0__14_carry__0_n_6;\n wire mod_sub0_return0__14_carry__0_n_7;\n wire mod_sub0_return0__14_carry_i_1_n_0;\n wire mod_sub0_return0__14_carry_i_2_n_0;\n wire mod_sub0_return0__14_carry_i_3_n_0;\n wire mod_sub0_return0__14_carry_i_4_n_0;\n wire mod_sub0_return0__14_carry_n_0;\n wire mod_sub0_return0__14_carry_n_1;\n wire mod_sub0_return0__14_carry_n_2;\n wire mod_sub0_return0__14_carry_n_3;\n wire mod_sub0_return0__14_carry_n_4;\n wire mod_sub0_return0__14_carry_n_5;\n wire mod_sub0_return0__14_carry_n_6;\n wire mod_sub0_return0_carry__0_i_1_n_0;\n wire mod_sub0_return0_carry__0_i_2_n_0;\n wire mod_sub0_return0_carry__0_i_3_n_0;\n wire mod_sub0_return0_carry__0_i_4_n_0;\n wire mod_sub0_return0_carry__0_i_5_n_0;\n wire mod_sub0_return0_carry__0_n_2;\n wire mod_sub0_return0_carry__0_n_3;\n wire mod_sub0_return0_carry__0_n_5;\n wire mod_sub0_return0_carry__0_n_6;\n wire mod_sub0_return0_carry__0_n_7;\n wire mod_sub0_return0_carry_i_1_n_0;\n wire mod_sub0_return0_carry_i_2_n_0;\n wire mod_sub0_return0_carry_i_3_n_0;\n wire mod_sub0_return0_carry_i_4_n_0;\n wire mod_sub0_return0_carry_n_0;\n wire mod_sub0_return0_carry_n_1;\n wire mod_sub0_return0_carry_n_2;\n wire mod_sub0_return0_carry_n_3;\n wire mod_sub0_return0_carry_n_4;\n wire mod_sub0_return0_carry_n_5;\n wire mod_sub0_return0_carry_n_6;\n wire mod_sub0_return0_carry_n_7;\n wire mod_sub_return0__14_carry__0_i_1_n_0;\n wire mod_sub_return0__14_carry__0_i_2_n_0;\n wire mod_sub_return0__14_carry__0_n_1;\n wire mod_sub_return0__14_carry__0_n_3;\n wire mod_sub_return0__14_carry__0_n_6;\n wire mod_sub_return0__14_carry__0_n_7;\n wire mod_sub_return0__14_carry_i_1_n_0;\n wire mod_sub_return0__14_carry_i_2_n_0;\n wire mod_sub_return0__14_carry_i_3_n_0;\n wire mod_sub_return0__14_carry_i_4_n_0;\n wire mod_sub_return0__14_carry_n_0;\n wire mod_sub_return0__14_carry_n_1;\n wire mod_sub_return0__14_carry_n_2;\n wire mod_sub_return0__14_carry_n_3;\n wire mod_sub_return0__14_carry_n_4;\n wire mod_sub_return0__14_carry_n_5;\n wire mod_sub_return0__14_carry_n_6;\n wire mod_sub_return0_carry__0_i_1__0_n_0;\n wire mod_sub_return0_carry__0_i_2_n_0;\n wire mod_sub_return0_carry__0_i_3_n_0;\n wire mod_sub_return0_carry__0_i_4_n_0;\n wire mod_sub_return0_carry__0_i_5_n_0;\n wire mod_sub_return0_carry__0_n_2;\n wire mod_sub_return0_carry__0_n_3;\n wire mod_sub_return0_carry__0_n_5;\n wire mod_sub_return0_carry__0_n_6;\n wire mod_sub_return0_carry__0_n_7;\n wire mod_sub_return0_carry_i_1__0_n_0;\n wire mod_sub_return0_carry_i_2_n_0;\n wire mod_sub_return0_carry_i_3_n_0;\n wire mod_sub_return0_carry_i_4_n_0;\n wire mod_sub_return0_carry_n_0;\n wire mod_sub_return0_carry_n_1;\n wire mod_sub_return0_carry_n_2;\n wire mod_sub_return0_carry_n_3;\n wire mod_sub_return0_carry_n_4;\n wire mod_sub_return0_carry_n_5;\n wire mod_sub_return0_carry_n_6;\n wire mod_sub_return0_carry_n_7;\n wire o2f_r_reg;\n wire ocd_prech_req_r_reg;\n wire oclk_center_write_resume;\n wire [5:0]oclkdelay_calib_done_r_reg;\n wire oclkdelay_center_calib_start_r_i_3_n_0;\n wire oclkdelay_center_calib_start_r_i_4_n_0;\n wire oclkdelay_center_calib_start_r_reg;\n wire [5:0]oclkdelay_center_calib_start_r_reg_0;\n wire [3:0]p_0_in;\n wire [5:0]p_0_in__0;\n wire po_rdy;\n wire po_stg23_sel_r_reg;\n wire \\po_wait_r_reg[0] ;\n wire poc_ready_r_i_1_n_0;\n wire prbs_rdlvl_done_reg_rep;\n wire prech_done;\n wire prech_req_r_i_1__0_n_0;\n wire prech_req_r_i_2_n_0;\n wire prech_req_r_reg_0;\n wire [5:0]\\rise_lead_r_reg[5] ;\n wire rstdiv0_sync_r1_reg_rep__10;\n wire [0:0]rstdiv0_sync_r1_reg_rep__11;\n wire [0:0]rstdiv0_sync_r1_reg_rep__19;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__26;\n wire rstdiv0_sync_r1_reg_rep__26_0;\n wire rstdiv0_sync_r1_reg_rep__9;\n wire scan_right;\n wire scanning_right;\n wire scanning_right_r_i_4_n_0;\n wire scanning_right_r_i_5_n_0;\n wire scanning_right_r_reg;\n wire [5:0]scanning_right_r_reg_0;\n wire \\sm_r_reg[2] ;\n wire stg2_dec_req_r_i_1_n_0;\n wire stg2_inc_r;\n wire stg2_inc_r_i_1_n_0;\n wire stg2_inc_r_i_2_n_0;\n wire stg2_inc_r_i_3_n_0;\n wire stg2_inc_r_i_4_n_0;\n wire stg2_inc_req_r_i_1_n_0;\n wire stg2_inc_req_r_i_2_n_0;\n wire stg2_tap_cnt0;\n wire \\stg2_tap_cnt[1]_i_3_n_0 ;\n wire \\stg2_tap_cnt[1]_i_4_n_0 ;\n wire \\stg2_tap_cnt[2]_i_3_n_0 ;\n wire \\stg2_tap_cnt[2]_i_4_n_0 ;\n wire \\stg2_tap_cnt[2]_i_5_n_0 ;\n wire \\stg2_tap_cnt[2]_i_6_n_0 ;\n wire \\stg2_tap_cnt[3]_i_3_n_0 ;\n wire \\stg2_tap_cnt[4]_i_3_n_0 ;\n wire \\stg2_tap_cnt[5]_i_6_n_0 ;\n wire \\stg2_tap_cnt_reg[0]_0 ;\n wire \\stg2_tap_cnt_reg[2]_0 ;\n wire [2:0]\\stg2_tap_cnt_reg[3]_0 ;\n wire [5:3]stg2_tap_cnt_reg__0;\n wire stg3_dec2init_val_r;\n wire stg3_dec2init_val_r1;\n wire stg3_dec2init_val_r_i_10_n_0;\n wire stg3_dec2init_val_r_i_12_n_0;\n wire stg3_dec2init_val_r_i_13_n_0;\n wire stg3_dec2init_val_r_i_1_n_0;\n wire stg3_dec2init_val_r_i_2_n_0;\n wire stg3_dec2init_val_r_i_3_n_0;\n wire stg3_dec2init_val_r_i_4_n_0;\n wire stg3_dec2init_val_r_i_5_n_0;\n wire stg3_dec2init_val_r_i_6_n_0;\n wire stg3_dec2init_val_r_i_7_n_0;\n wire stg3_dec2init_val_r_i_8_n_0;\n wire stg3_dec2init_val_r_i_9_n_0;\n wire stg3_dec2init_val_r_reg_0;\n wire stg3_dec_r;\n wire stg3_dec_r_i_1_n_0;\n wire stg3_dec_r_i_2_n_0;\n wire stg3_dec_r_i_3_n_0;\n wire stg3_dec_r_i_4_n_0;\n wire stg3_dec_r_i_5_n_0;\n wire stg3_dec_req_r_i_1_n_0;\n wire stg3_dec_req_r_i_2_n_0;\n wire stg3_dec_req_r_i_3_n_0;\n wire [5:0]stg3_dec_val;\n wire [4:3]stg3_dec_val00_out;\n wire \\stg3_dec_val[5]_i_1_n_0 ;\n wire \\stg3_dec_val[5]_i_2_n_0 ;\n wire \\stg3_dec_val[5]_i_3_n_0 ;\n wire stg3_inc2init_val_r;\n wire stg3_inc2init_val_r1;\n wire stg3_inc2init_val_r_i_1_n_0;\n wire stg3_inc2init_val_r_i_2_n_0;\n wire stg3_inc2init_val_r_i_3_n_0;\n wire stg3_inc2init_val_r_reg_0;\n wire stg3_inc_req_r_i_1_n_0;\n wire [5:0]stg3_inc_val;\n wire \\stg3_inc_val[0]_i_1_n_0 ;\n wire \\stg3_inc_val[1]_i_1_n_0 ;\n wire \\stg3_inc_val[2]_i_1_n_0 ;\n wire \\stg3_inc_val[2]_i_2_n_0 ;\n wire \\stg3_inc_val[3]_i_1_n_0 ;\n wire \\stg3_inc_val[3]_i_2_n_0 ;\n wire \\stg3_inc_val[4]_i_1_n_0 ;\n wire \\stg3_inc_val[5]_i_1_n_0 ;\n wire \\stg3_inc_val[5]_i_2_n_0 ;\n wire \\stg3_inc_val[5]_i_3_n_0 ;\n wire stg3_init_dec_r;\n wire stg3_init_dec_r_i_1_n_0;\n wire stg3_init_dec_r_i_2_n_0;\n wire stg3_init_dec_r_i_3_n_0;\n wire stg3_init_dec_r_i_4_n_0;\n wire [5:3]stg3_init_val;\n wire stg3_left_lim0;\n wire \\stg3_left_lim[5]_i_1_n_0 ;\n wire [5:0]\\stg3_r_reg[5] ;\n wire stg3_right_lim0;\n wire \\stg3_right_lim[5]_i_1_n_0 ;\n wire stg3_tap_cnt0;\n wire \\stg3_tap_cnt[0]_i_1_n_0 ;\n wire \\stg3_tap_cnt[1]_i_1_n_0 ;\n wire \\stg3_tap_cnt[1]_i_2_n_0 ;\n wire \\stg3_tap_cnt[2]_i_1_n_0 ;\n wire \\stg3_tap_cnt[2]_i_2_n_0 ;\n wire \\stg3_tap_cnt[3]_i_1_n_0 ;\n wire \\stg3_tap_cnt[3]_i_2_n_0 ;\n wire \\stg3_tap_cnt[3]_i_3_n_0 ;\n wire \\stg3_tap_cnt[3]_i_4_n_0 ;\n wire \\stg3_tap_cnt[4]_i_1_n_0 ;\n wire \\stg3_tap_cnt[5]_i_2_n_0 ;\n wire \\stg3_tap_cnt[5]_i_4_n_0 ;\n wire \\stg3_tap_cnt[5]_i_5_n_0 ;\n wire \\stg3_tap_cnt[5]_i_6_n_0 ;\n wire [2:0]\\stg3_tap_cnt_reg[2]_0 ;\n wire \\stg3_tap_cnt_reg_n_0_[0] ;\n wire \\stg3_tap_cnt_reg_n_0_[1] ;\n wire \\stg3_tap_cnt_reg_n_0_[2] ;\n wire \\stg3_tap_cnt_reg_n_0_[3] ;\n wire \\stg3_tap_cnt_reg_n_0_[4] ;\n wire \\stg3_tap_cnt_reg_n_0_[5] ;\n wire wait_cnt_done;\n wire wait_cnt_done_i_1_n_0;\n wire wait_cnt_en_r;\n wire wait_cnt_en_r0;\n wire wait_cnt_en_r_i_2_n_0;\n wire wait_cnt_en_r_i_3_n_0;\n wire \\wait_cnt_r[3]_i_1_n_0 ;\n wire [3:0]wait_cnt_r_reg__0;\n wire [1:0]\\wl_po_fine_cnt_reg[14] ;\n wire \\wl_po_fine_cnt_reg[17] ;\n wire \\wl_po_fine_cnt_reg[18] ;\n wire \\wl_po_fine_cnt_reg[3] ;\n wire write_request_r_i_1_n_0;\n wire write_request_r_i_2_n_0;\n wire [0:0]NLW_mod_sub0_return0__14_carry_O_UNCONNECTED;\n wire [3:1]NLW_mod_sub0_return0__14_carry__0_CO_UNCONNECTED;\n wire [3:2]NLW_mod_sub0_return0__14_carry__0_O_UNCONNECTED;\n wire [3:2]NLW_mod_sub0_return0_carry__0_CO_UNCONNECTED;\n wire [3:3]NLW_mod_sub0_return0_carry__0_O_UNCONNECTED;\n wire [0:0]NLW_mod_sub_return0__14_carry_O_UNCONNECTED;\n wire [3:1]NLW_mod_sub_return0__14_carry__0_CO_UNCONNECTED;\n wire [3:2]NLW_mod_sub_return0__14_carry__0_O_UNCONNECTED;\n wire [3:2]NLW_mod_sub_return0_carry__0_CO_UNCONNECTED;\n wire [3:3]NLW_mod_sub_return0_carry__0_O_UNCONNECTED;\n\n FDRE detect_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(done_r_reg_1),\n .Q(detect_done_r),\n .R(rstdiv0_sync_r1_reg_rep__10));\n LUT6 #(\n .INIT(64'hFFFF7FFF00880000)) \n done_r_i_1__0\n (.I0(\\lim_state[0]_i_2_n_0 ),\n .I1(\\lim_state[4]_i_3_n_0 ),\n .I2(lim_start_r_reg_0),\n .I3(lim_state[0]),\n .I4(lim_state[13]),\n .I5(done_r_reg_0),\n .O(done_r_i_1__0_n_0));\n FDRE done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(done_r_i_1__0_n_0),\n .Q(done_r_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__9));\n (* SOFT_HLUTNM = \"soft_lutpair391\" *) \n LUT3 #(\n .INIT(8'h02)) \n \\init_state_r[4]_i_35 \n (.I0(cnt_cmd_done_r),\n .I1(prech_req_r_reg_0),\n .I2(ocd_prech_req_r_reg),\n .O(\\init_state_r_reg[4] ));\n LUT2 #(\n .INIT(4'hE)) \n \\init_state_r[5]_i_37 \n (.I0(lim2init_write_request),\n .I1(oclk_center_write_resume),\n .O(\\init_state_r_reg[5] ));\n (* SOFT_HLUTNM = \"soft_lutpair391\" *) \n LUT3 #(\n .INIT(8'hFE)) \n \\init_state_r[6]_i_6 \n (.I0(prbs_rdlvl_done_reg_rep),\n .I1(prech_req_r_reg_0),\n .I2(ocd_prech_req_r_reg),\n .O(\\init_state_r_reg[6] ));\n LUT6 #(\n .INIT(64'hFFEFFFFF01000000)) \n ktap_right_r_i_1\n (.I0(\\lim_state[13]_i_7_n_0 ),\n .I1(lim_state[0]),\n .I2(lim_state[13]),\n .I3(lim_state[1]),\n .I4(ktap_right_r_i_2_n_0),\n .I5(lim2poc_ktap_right),\n .O(ktap_right_r_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair383\" *) \n LUT4 #(\n .INIT(16'h0001)) \n ktap_right_r_i_2\n (.I0(lim_state[9]),\n .I1(lim_state[12]),\n .I2(lim_state[10]),\n .I3(lim_state[11]),\n .O(ktap_right_r_i_2_n_0));\n FDRE ktap_right_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(ktap_right_r_i_1_n_0),\n .Q(lim2poc_ktap_right),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE lim_start_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(lim_start),\n .Q(lim_start_r),\n .R(rstdiv0_sync_r1_reg_rep__10));\n LUT4 #(\n .INIT(16'hFFD0)) \n \\lim_state[0]_i_1 \n (.I0(\\lim_state[0]_i_2_n_0 ),\n .I1(\\lim_state[0]_i_3_n_0 ),\n .I2(wait_cnt_en_r_i_2_n_0),\n .I3(\\lim_state[0]_i_4_n_0 ),\n .O(\\lim_state[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair378\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\lim_state[0]_i_2 \n (.I0(lim_state[1]),\n .I1(lim_state[4]),\n .I2(lim_state[2]),\n .I3(lim_state[3]),\n .O(\\lim_state[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hAAA8A880AAAAAAAA)) \n \\lim_state[0]_i_3 \n (.I0(\\lim_state[0]_i_5_n_0 ),\n .I1(lim_state[8]),\n .I2(lim_state[7]),\n .I3(lim_state[6]),\n .I4(lim_state[5]),\n .I5(\\lim_state[1]_i_2_n_0 ),\n .O(\\lim_state[0]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFDFFFCFCC2)) \n \\lim_state[0]_i_4 \n (.I0(\\lim_state[4]_i_3_n_0 ),\n .I1(lim_state[3]),\n .I2(lim_state[2]),\n .I3(lim_state[4]),\n .I4(lim_state[1]),\n .I5(lim_state[0]),\n .O(\\lim_state[0]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFEFEEC)) \n \\lim_state[0]_i_5 \n (.I0(lim_state[9]),\n .I1(lim_state[13]),\n .I2(lim_state[12]),\n .I3(lim_state[10]),\n .I4(lim_state[11]),\n .I5(wait_cnt_en_r_i_3_n_0),\n .O(\\lim_state[0]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000020200)) \n \\lim_state[10]_i_1 \n (.I0(\\lim_state[10]_i_2_n_0 ),\n .I1(lim_state[0]),\n .I2(lim_state[9]),\n .I3(lim_state[7]),\n .I4(lim_state[8]),\n .I5(\\lim_state[10]_i_3_n_0 ),\n .O(\\lim_state[10]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair369\" *) \n LUT5 #(\n .INIT(32'h00010000)) \n \\lim_state[10]_i_2 \n (.I0(lim_state[12]),\n .I1(lim_state[13]),\n .I2(lim_state[11]),\n .I3(lim_state[10]),\n .I4(\\lim_state[0]_i_2_n_0 ),\n .O(\\lim_state[10]_i_2_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\lim_state[10]_i_3 \n (.I0(lim_state[6]),\n .I1(lim_state[5]),\n .O(\\lim_state[10]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h00000000E2000000)) \n \\lim_state[11]_i_1 \n (.I0(\\lim_state[11]_i_2_n_0 ),\n .I1(lim_state[1]),\n .I2(\\lim_state[11]_i_3_n_0 ),\n .I3(\\lim_state[11]_i_4_n_0 ),\n .I4(\\lim_state[11]_i_5_n_0 ),\n .I5(lim_state[13]),\n .O(\\lim_state[11]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000FFFFA8A00000)) \n \\lim_state[11]_i_2 \n (.I0(\\lim_state[6]_i_4_n_0 ),\n .I1(stg3_inc2init_val_r),\n .I2(stg3_dec2init_val_r),\n .I3(\\lim_state[11]_i_6_n_0 ),\n .I4(lim_state[9]),\n .I5(lim_state[10]),\n .O(\\lim_state[11]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair383\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\lim_state[11]_i_3 \n (.I0(lim_state[10]),\n .I1(lim_state[9]),\n .O(\\lim_state[11]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'h00000001)) \n \\lim_state[11]_i_4 \n (.I0(lim_state[0]),\n .I1(lim_state[3]),\n .I2(lim_state[2]),\n .I3(lim_state[4]),\n .I4(wait_cnt_en_r_i_3_n_0),\n .O(\\lim_state[11]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair380\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\lim_state[11]_i_5 \n (.I0(lim_state[11]),\n .I1(lim_state[12]),\n .O(\\lim_state[11]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h444F444F444F4444)) \n \\lim_state[11]_i_6 \n (.I0(stg3_inc_val[5]),\n .I1(\\stg3_tap_cnt_reg_n_0_[5] ),\n .I2(\\mmcm_init_lead[5]_i_3_n_0 ),\n .I3(\\lim_state[11]_i_7_n_0 ),\n .I4(\\mmcm_init_lead[5]_i_6_n_0 ),\n .I5(\\mmcm_init_lead[5]_i_4_n_0 ),\n .O(\\lim_state[11]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h00B0BBBB000000B0)) \n \\lim_state[11]_i_7 \n (.I0(stg3_inc_val[4]),\n .I1(\\stg3_tap_cnt_reg_n_0_[4] ),\n .I2(stg3_inc_val[2]),\n .I3(\\stg3_tap_cnt_reg_n_0_[2] ),\n .I4(\\stg3_tap_cnt_reg_n_0_[3] ),\n .I5(stg3_inc_val[3]),\n .O(\\lim_state[11]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair368\" *) \n LUT5 #(\n .INIT(32'h00005D55)) \n \\lim_state[12]_i_1 \n (.I0(\\lim_state[12]_i_2_n_0 ),\n .I1(\\lim_state[12]_i_3_n_0 ),\n .I2(stg3_dec2init_val_r),\n .I3(stg3_inc2init_val_r),\n .I4(\\lim_state[12]_i_4_n_0 ),\n .O(\\lim_state[12]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h555F5DDF5DDF5DDF)) \n \\lim_state[12]_i_2 \n (.I0(stg3_dec2init_val_r),\n .I1(\\lim_state[12]_i_5_n_0 ),\n .I2(stg2_tap_cnt_reg__0[5]),\n .I3(\\wl_po_fine_cnt_reg[17] ),\n .I4(stg2_tap_cnt_reg__0[4]),\n .I5(\\byte_r_reg[0] ),\n .O(\\lim_state[12]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000001)) \n \\lim_state[12]_i_3 \n (.I0(\\stg2_tap_cnt_reg[3]_0 [1]),\n .I1(\\stg2_tap_cnt_reg[3]_0 [0]),\n .I2(\\stg2_tap_cnt_reg[3]_0 [2]),\n .I3(stg2_tap_cnt_reg__0[3]),\n .I4(stg2_tap_cnt_reg__0[5]),\n .I5(stg2_tap_cnt_reg__0[4]),\n .O(\\lim_state[12]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFDFFFF)) \n \\lim_state[12]_i_4 \n (.I0(lim_state[11]),\n .I1(wait_cnt_en_r_i_3_n_0),\n .I2(lim_state[0]),\n .I3(lim_state[3]),\n .I4(\\lim_state[13]_i_11_n_0 ),\n .I5(stg2_inc_r_i_2_n_0),\n .O(\\lim_state[12]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h111111FF11F1F1FF)) \n \\lim_state[12]_i_5 \n (.I0(stg2_tap_cnt_reg__0[4]),\n .I1(\\byte_r_reg[0] ),\n .I2(\\stg2_tap_cnt_reg[2]_0 ),\n .I3(\\wl_po_fine_cnt_reg[3] ),\n .I4(stg2_tap_cnt_reg__0[3]),\n .I5(\\lim_state[12]_i_7_n_0 ),\n .O(\\lim_state[12]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair373\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\lim_state[12]_i_7 \n (.I0(\\stg2_tap_cnt_reg[3]_0 [2]),\n .I1(\\wl_po_fine_cnt_reg[14] [1]),\n .O(\\lim_state[12]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFEEEEEEEA)) \n \\lim_state[13]_i_1 \n (.I0(lim_state[13]),\n .I1(\\lim_state[13]_i_3_n_0 ),\n .I2(lim_state[4]),\n .I3(\\lim_state[13]_i_4_n_0 ),\n .I4(\\lim_state[13]_i_5_n_0 ),\n .I5(\\lim_state[13]_i_6_n_0 ),\n .O(lim_nxt_state));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFF4)) \n \\lim_state[13]_i_10 \n (.I0(lim_start_r),\n .I1(lim_start),\n .I2(lim_state[3]),\n .I3(lim_state[2]),\n .I4(lim_state[4]),\n .I5(lim_state[1]),\n .O(\\lim_state[13]_i_10_n_0 ));\n LUT3 #(\n .INIT(8'h01)) \n \\lim_state[13]_i_11 \n (.I0(lim_state[2]),\n .I1(lim_state[4]),\n .I2(lim_state[1]),\n .O(\\lim_state[13]_i_11_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair379\" *) \n LUT3 #(\n .INIT(8'h01)) \n \\lim_state[13]_i_12 \n (.I0(lim_state[9]),\n .I1(lim_state[10]),\n .I2(lim_state[12]),\n .O(\\lim_state[13]_i_12_n_0 ));\n LUT6 #(\n .INIT(64'h00000000EEEEEEFE)) \n \\lim_state[13]_i_13 \n (.I0(lim_state[10]),\n .I1(lim_state[8]),\n .I2(po_rdy),\n .I3(lim2stg3_dec),\n .I4(lim2stg3_inc),\n .I5(\\lim_state[13]_i_14_n_0 ),\n .O(\\lim_state[13]_i_13_n_0 ));\n LUT5 #(\n .INIT(32'h000000FB)) \n \\lim_state[13]_i_14 \n (.I0(lim2stg2_dec),\n .I1(po_rdy),\n .I2(lim2stg2_inc),\n .I3(lim_state[8]),\n .I4(lim_state[9]),\n .O(\\lim_state[13]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'h0001000000000000)) \n \\lim_state[13]_i_2 \n (.I0(\\lim_state[13]_i_7_n_0 ),\n .I1(\\lim_state[13]_i_8_n_0 ),\n .I2(lim_state[1]),\n .I3(lim_state[13]),\n .I4(lim_state[12]),\n .I5(stg3_dec2init_val_r),\n .O(\\lim_state[13]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hAAA8A888AAAAAAAA)) \n \\lim_state[13]_i_3 \n (.I0(\\lim_state[13]_i_9_n_0 ),\n .I1(wait_cnt_done),\n .I2(lim_state[4]),\n .I3(lim_state[1]),\n .I4(lim_state[2]),\n .I5(\\lim_state[4]_i_3_n_0 ),\n .O(\\lim_state[13]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair382\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n \\lim_state[13]_i_4 \n (.I0(lim_state[10]),\n .I1(lim_state[11]),\n .I2(lim_state[8]),\n .I3(lim_state[9]),\n .O(\\lim_state[13]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFEEE)) \n \\lim_state[13]_i_5 \n (.I0(\\lim_state[10]_i_3_n_0 ),\n .I1(lim_state[7]),\n .I2(lim_state[12]),\n .I3(prech_done),\n .I4(lim_state[2]),\n .I5(lim_state[1]),\n .O(\\lim_state[13]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hC8CFCCC0FFF0FFF0)) \n \\lim_state[13]_i_6 \n (.I0(done_r_reg_1),\n .I1(\\lim_state[13]_i_10_n_0 ),\n .I2(lim_state[0]),\n .I3(lim_state[3]),\n .I4(\\lim_state[13]_i_11_n_0 ),\n .I5(\\lim_state[13]_i_12_n_0 ),\n .O(\\lim_state[13]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\lim_state[13]_i_7 \n (.I0(lim_state[8]),\n .I1(lim_state[7]),\n .I2(\\lim_state[10]_i_3_n_0 ),\n .I3(lim_state[4]),\n .I4(lim_state[2]),\n .I5(lim_state[3]),\n .O(\\lim_state[13]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair382\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n \\lim_state[13]_i_8 \n (.I0(lim_state[10]),\n .I1(lim_state[11]),\n .I2(lim_state[0]),\n .I3(lim_state[9]),\n .O(\\lim_state[13]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFEFF)) \n \\lim_state[13]_i_9 \n (.I0(\\lim_state[13]_i_13_n_0 ),\n .I1(lim_state[12]),\n .I2(lim_state[11]),\n .I3(\\lim_state[13]_i_11_n_0 ),\n .I4(lim_state[7]),\n .I5(\\lim_state[10]_i_3_n_0 ),\n .O(\\lim_state[13]_i_9_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair384\" *) \n LUT4 #(\n .INIT(16'h0040)) \n \\lim_state[1]_i_1 \n (.I0(\\lim_state[13]_i_7_n_0 ),\n .I1(\\lim_state[1]_i_2_n_0 ),\n .I2(lim_state[0]),\n .I3(lim_state[1]),\n .O(\\lim_state[1]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h00000001)) \n \\lim_state[1]_i_2 \n (.I0(lim_state[11]),\n .I1(lim_state[10]),\n .I2(lim_state[12]),\n .I3(lim_state[9]),\n .I4(lim_state[13]),\n .O(\\lim_state[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\lim_state[2]_i_1 \n (.I0(\\lim_state[2]_i_2_n_0 ),\n .I1(\\lim_state[2]_i_3_n_0 ),\n .I2(lim_state[6]),\n .I3(lim_state[5]),\n .I4(lim_state[7]),\n .I5(\\lim_state[2]_i_4_n_0 ),\n .O(\\lim_state[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00F000F000F1FFFF)) \n \\lim_state[2]_i_2 \n (.I0(stg3_inc2init_val_r),\n .I1(stg3_init_dec_r),\n .I2(\\lim_state[6]_i_3_n_0 ),\n .I3(lim_state[12]),\n .I4(lim_state[9]),\n .I5(stg3_dec2init_val_r),\n .O(\\lim_state[2]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\lim_state[2]_i_3 \n (.I0(lim_state[0]),\n .I1(lim_state[3]),\n .I2(lim_state[1]),\n .I3(lim_state[2]),\n .O(\\lim_state[2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFEFFFEFFFEFFFFFF)) \n \\lim_state[2]_i_4 \n (.I0(lim_state[10]),\n .I1(lim_state[8]),\n .I2(lim_state[11]),\n .I3(\\lim_state[4]_i_2_n_0 ),\n .I4(lim_state[12]),\n .I5(lim_state[9]),\n .O(\\lim_state[2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h0000000010000000)) \n \\lim_state[3]_i_1 \n (.I0(lim_state[0]),\n .I1(lim_state[1]),\n .I2(\\lim_state[4]_i_2_n_0 ),\n .I3(\\lim_state[4]_i_3_n_0 ),\n .I4(lim_state[2]),\n .I5(lim_state[3]),\n .O(\\lim_state[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000010000000)) \n \\lim_state[4]_i_1 \n (.I0(lim_state[0]),\n .I1(lim_state[1]),\n .I2(\\lim_state[4]_i_2_n_0 ),\n .I3(\\lim_state[4]_i_3_n_0 ),\n .I4(lim_state[3]),\n .I5(lim_state[2]),\n .O(\\lim_state[4]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair372\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\lim_state[4]_i_2 \n (.I0(lim_state[4]),\n .I1(lim_state[13]),\n .O(\\lim_state[4]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h00000001)) \n \\lim_state[4]_i_3 \n (.I0(lim_state[11]),\n .I1(lim_state[10]),\n .I2(lim_state[12]),\n .I3(lim_state[9]),\n .I4(wait_cnt_en_r_i_3_n_0),\n .O(\\lim_state[4]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'h888A)) \n \\lim_state[5]_i_1 \n (.I0(\\lim_state[6]_i_2_n_0 ),\n .I1(\\lim_state[5]_i_2_n_0 ),\n .I2(lim_state[9]),\n .I3(\\lim_state[6]_i_5_n_0 ),\n .O(\\lim_state[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h00000010)) \n \\lim_state[5]_i_2 \n (.I0(lim_state[4]),\n .I1(stg3_init_dec_r),\n .I2(stg3_inc2init_val_r),\n .I3(stg3_dec2init_val_r),\n .I4(\\lim_state[11]_i_6_n_0 ),\n .O(\\lim_state[5]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0002AAAA00020002)) \n \\lim_state[6]_i_1 \n (.I0(\\lim_state[6]_i_2_n_0 ),\n .I1(\\lim_state[6]_i_3_n_0 ),\n .I2(lim_state[4]),\n .I3(\\lim_state[6]_i_4_n_0 ),\n .I4(lim_state[9]),\n .I5(\\lim_state[6]_i_5_n_0 ),\n .O(\\lim_state[6]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h1D1D1D1D1D1D1DFF)) \n \\lim_state[6]_i_10 \n (.I0(\\lim_state[6]_i_14_n_0 ),\n .I1(\\lim_state[6]_i_15_n_0 ),\n .I2(\\lim_state[6]_i_16_n_0 ),\n .I3(\\stg3_tap_cnt_reg_n_0_[4] ),\n .I4(\\stg3_tap_cnt_reg_n_0_[5] ),\n .I5(\\lim_state[6]_i_17_n_0 ),\n .O(\\lim_state[6]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'hD0FD0000FFFFD0FD)) \n \\lim_state[6]_i_11 \n (.I0(\\stg3_tap_cnt_reg_n_0_[0] ),\n .I1(stg3_dec_val[0]),\n .I2(stg3_dec_val[1]),\n .I3(\\stg3_tap_cnt_reg_n_0_[1] ),\n .I4(stg3_dec_val[2]),\n .I5(\\stg3_tap_cnt_reg_n_0_[2] ),\n .O(\\lim_state[6]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'h0D000D00DD0D0D00)) \n \\lim_state[6]_i_12 \n (.I0(\\stg3_tap_cnt_reg[2]_0 [2]),\n .I1(\\stg3_tap_cnt_reg_n_0_[2] ),\n .I2(\\stg3_tap_cnt_reg[2]_0 [1]),\n .I3(\\stg3_tap_cnt_reg_n_0_[1] ),\n .I4(\\stg3_tap_cnt_reg_n_0_[0] ),\n .I5(\\stg3_tap_cnt_reg[2]_0 [0]),\n .O(\\lim_state[6]_i_12_n_0 ));\n LUT4 #(\n .INIT(16'h4F44)) \n \\lim_state[6]_i_13 \n (.I0(\\stg3_tap_cnt_reg_n_0_[4] ),\n .I1(stg3_init_val[4]),\n .I2(\\stg3_tap_cnt_reg_n_0_[3] ),\n .I3(stg3_init_val[3]),\n .O(\\lim_state[6]_i_13_n_0 ));\n LUT4 #(\n .INIT(16'h0002)) \n \\lim_state[6]_i_14 \n (.I0(\\lim_state[6]_i_18_n_0 ),\n .I1(mod_sub_return0_carry__0_n_6),\n .I2(mod_sub_return0_carry__0_n_5),\n .I3(mod_sub_return0_carry__0_n_7),\n .O(\\lim_state[6]_i_14_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair376\" *) \n LUT5 #(\n .INIT(32'h4D44DDDD)) \n \\lim_state[6]_i_15 \n (.I0(\\mmcm_current_reg_n_0_[5] ),\n .I1(\\mmcm_init_trail_reg_n_0_[5] ),\n .I2(\\mmcm_current_reg_n_0_[4] ),\n .I3(\\mmcm_init_trail_reg_n_0_[4] ),\n .I4(\\lim_state[6]_i_19_n_0 ),\n .O(\\lim_state[6]_i_15_n_0 ));\n LUT4 #(\n .INIT(16'h0020)) \n \\lim_state[6]_i_16 \n (.I0(\\lim_state[6]_i_20_n_0 ),\n .I1(mod_sub_return0__14_carry__0_n_7),\n .I2(mod_sub_return0__14_carry__0_n_1),\n .I3(mod_sub_return0__14_carry__0_n_6),\n .O(\\lim_state[6]_i_16_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair377\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n \\lim_state[6]_i_17 \n (.I0(\\stg3_tap_cnt_reg_n_0_[1] ),\n .I1(\\stg3_tap_cnt_reg_n_0_[0] ),\n .I2(\\stg3_tap_cnt_reg_n_0_[2] ),\n .I3(\\stg3_tap_cnt_reg_n_0_[3] ),\n .O(\\lim_state[6]_i_17_n_0 ));\n LUT4 #(\n .INIT(16'h5557)) \n \\lim_state[6]_i_18 \n (.I0(mod_sub_return0_carry_n_4),\n .I1(mod_sub_return0_carry_n_6),\n .I2(mod_sub_return0_carry_n_5),\n .I3(mod_sub_return0_carry_n_7),\n .O(\\lim_state[6]_i_18_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFB000FFB0)) \n \\lim_state[6]_i_19 \n (.I0(\\mmcm_current_reg_n_0_[2] ),\n .I1(\\mmcm_init_trail_reg_n_0_[2] ),\n .I2(\\lim_state[6]_i_21_n_0 ),\n .I3(\\mmcm_current_reg_n_0_[3] ),\n .I4(\\mmcm_init_trail_reg_n_0_[3] ),\n .I5(\\lim_state[6]_i_22_n_0 ),\n .O(\\lim_state[6]_i_19_n_0 ));\n LUT5 #(\n .INIT(32'h11100000)) \n \\lim_state[6]_i_2 \n (.I0(wait_cnt_en_r_i_3_n_0),\n .I1(\\lim_state[2]_i_3_n_0 ),\n .I2(lim_state[4]),\n .I3(lim_state[9]),\n .I4(\\lim_state[6]_i_6_n_0 ),\n .O(\\lim_state[6]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'h5557)) \n \\lim_state[6]_i_20 \n (.I0(mod_sub_return0__14_carry_n_4),\n .I1(mod_sub_return0__14_carry_n_6),\n .I2(mod_sub_return0__14_carry_n_5),\n .I3(\\mmcm_init_trail_reg[0]_0 ),\n .O(\\lim_state[6]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'h40F440F4FFFF40F4)) \n \\lim_state[6]_i_21 \n (.I0(\\mmcm_init_trail_reg_n_0_[0] ),\n .I1(\\mmcm_current_reg_n_0_[0] ),\n .I2(\\mmcm_current_reg_n_0_[1] ),\n .I3(\\mmcm_init_trail_reg_n_0_[1] ),\n .I4(\\mmcm_current_reg_n_0_[2] ),\n .I5(\\mmcm_init_trail_reg_n_0_[2] ),\n .O(\\lim_state[6]_i_21_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair376\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\lim_state[6]_i_22 \n (.I0(\\mmcm_current_reg_n_0_[4] ),\n .I1(\\mmcm_init_trail_reg_n_0_[4] ),\n .O(\\lim_state[6]_i_22_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair393\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\lim_state[6]_i_24 \n (.I0(\\mmcm_init_trail_reg_n_0_[0] ),\n .I1(\\mmcm_current_reg_n_0_[0] ),\n .O(stg3_inc2init_val_r_reg_0));\n LUT4 #(\n .INIT(16'h8A08)) \n \\lim_state[6]_i_3 \n (.I0(stg3_init_dec_r),\n .I1(stg3_dec_val[5]),\n .I2(\\stg3_tap_cnt_reg_n_0_[5] ),\n .I3(\\lim_state[6]_i_7_n_0 ),\n .O(\\lim_state[6]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h1055105510555555)) \n \\lim_state[6]_i_4 \n (.I0(stg3_init_dec_r),\n .I1(\\stg3_tap_cnt_reg_n_0_[5] ),\n .I2(stg3_init_val[5]),\n .I3(stg3_dec2init_val_r),\n .I4(\\lim_state[6]_i_8_n_0 ),\n .I5(\\lim_state[6]_i_9_n_0 ),\n .O(\\lim_state[6]_i_4_n_0 ));\n LUT3 #(\n .INIT(8'hAE)) \n \\lim_state[6]_i_5 \n (.I0(stg3_dec2init_val_r_i_2_n_0),\n .I1(stg3_dec_r),\n .I2(\\lim_state[6]_i_10_n_0 ),\n .O(\\lim_state[6]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair369\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\lim_state[6]_i_6 \n (.I0(lim_state[10]),\n .I1(lim_state[11]),\n .I2(lim_state[13]),\n .I3(lim_state[12]),\n .O(\\lim_state[6]_i_6_n_0 ));\n LUT5 #(\n .INIT(32'hD4DD44D4)) \n \\lim_state[6]_i_7 \n (.I0(\\stg3_tap_cnt_reg_n_0_[4] ),\n .I1(stg3_dec_val[4]),\n .I2(\\lim_state[6]_i_11_n_0 ),\n .I3(\\stg3_tap_cnt_reg_n_0_[3] ),\n .I4(stg3_dec_val[3]),\n .O(\\lim_state[6]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FFFF4F44)) \n \\lim_state[6]_i_8 \n (.I0(stg3_init_val[3]),\n .I1(\\stg3_tap_cnt_reg_n_0_[3] ),\n .I2(\\stg3_tap_cnt_reg[2]_0 [2]),\n .I3(\\stg3_tap_cnt_reg_n_0_[2] ),\n .I4(\\lim_state[6]_i_12_n_0 ),\n .I5(\\lim_state[6]_i_13_n_0 ),\n .O(\\lim_state[6]_i_8_n_0 ));\n LUT4 #(\n .INIT(16'h4F44)) \n \\lim_state[6]_i_9 \n (.I0(stg3_init_val[4]),\n .I1(\\stg3_tap_cnt_reg_n_0_[4] ),\n .I2(stg3_init_val[5]),\n .I3(\\stg3_tap_cnt_reg_n_0_[5] ),\n .O(\\lim_state[6]_i_9_n_0 ));\n LUT5 #(\n .INIT(32'h0000888A)) \n \\lim_state[7]_i_1 \n (.I0(\\lim_state[12]_i_2_n_0 ),\n .I1(stg3_dec2init_val_r),\n .I2(\\lim_state[7]_i_2_n_0 ),\n .I3(stg3_inc2init_val_r),\n .I4(\\lim_state[12]_i_4_n_0 ),\n .O(\\lim_state[7]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h55555555D5555555)) \n \\lim_state[7]_i_2 \n (.I0(stg2_inc_r),\n .I1(stg2_tap_cnt_reg__0[5]),\n .I2(stg2_tap_cnt_reg__0[4]),\n .I3(\\stg2_tap_cnt_reg[3]_0 [1]),\n .I4(\\stg2_tap_cnt_reg[3]_0 [0]),\n .I5(\\lim_state[7]_i_3_n_0 ),\n .O(\\lim_state[7]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair367\" *) \n LUT2 #(\n .INIT(4'h7)) \n \\lim_state[7]_i_3 \n (.I0(\\stg2_tap_cnt_reg[3]_0 [2]),\n .I1(stg2_tap_cnt_reg__0[3]),\n .O(\\lim_state[7]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair368\" *) \n LUT4 #(\n .INIT(16'h0004)) \n \\lim_state[8]_i_1 \n (.I0(\\lim_state[12]_i_4_n_0 ),\n .I1(stg3_inc2init_val_r),\n .I2(stg3_dec2init_val_r),\n .I3(\\lim_state[12]_i_3_n_0 ),\n .O(\\lim_state[8]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h17001400)) \n \\lim_state[9]_i_1 \n (.I0(lim_state[11]),\n .I1(lim_state[5]),\n .I2(lim_state[6]),\n .I3(\\lim_state[9]_i_2_n_0 ),\n .I4(\\lim_state[9]_i_3_n_0 ),\n .O(\\lim_state[9]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h00000001)) \n \\lim_state[9]_i_2 \n (.I0(stg2_inc_r_i_2_n_0),\n .I1(lim_state[4]),\n .I2(lim_state[8]),\n .I3(lim_state[7]),\n .I4(\\lim_state[2]_i_3_n_0 ),\n .O(\\lim_state[9]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair386\" *) \n LUT4 #(\n .INIT(16'h0200)) \n \\lim_state[9]_i_3 \n (.I0(\\lim_state[7]_i_2_n_0 ),\n .I1(stg3_dec2init_val_r),\n .I2(stg3_inc2init_val_r),\n .I3(lim_state[11]),\n .O(\\lim_state[9]_i_3_n_0 ));\n FDSE \\lim_state_reg[0] \n (.C(CLK),\n .CE(lim_nxt_state),\n .D(\\lim_state[0]_i_1_n_0 ),\n .Q(lim_state[0]),\n .S(rstdiv0_sync_r1_reg_rep__10));\n FDRE \\lim_state_reg[10] \n (.C(CLK),\n .CE(lim_nxt_state),\n .D(\\lim_state[10]_i_1_n_0 ),\n .Q(lim_state[10]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE \\lim_state_reg[11] \n (.C(CLK),\n .CE(lim_nxt_state),\n .D(\\lim_state[11]_i_1_n_0 ),\n .Q(lim_state[11]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE \\lim_state_reg[12] \n (.C(CLK),\n .CE(lim_nxt_state),\n .D(\\lim_state[12]_i_1_n_0 ),\n .Q(lim_state[12]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE \\lim_state_reg[13] \n (.C(CLK),\n .CE(lim_nxt_state),\n .D(\\lim_state[13]_i_2_n_0 ),\n .Q(lim_state[13]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE \\lim_state_reg[1] \n (.C(CLK),\n .CE(lim_nxt_state),\n .D(\\lim_state[1]_i_1_n_0 ),\n .Q(lim_state[1]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE \\lim_state_reg[2] \n (.C(CLK),\n .CE(lim_nxt_state),\n .D(\\lim_state[2]_i_1_n_0 ),\n .Q(lim_state[2]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE \\lim_state_reg[3] \n (.C(CLK),\n .CE(lim_nxt_state),\n .D(\\lim_state[3]_i_1_n_0 ),\n .Q(lim_state[3]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE \\lim_state_reg[4] \n (.C(CLK),\n .CE(lim_nxt_state),\n .D(\\lim_state[4]_i_1_n_0 ),\n .Q(lim_state[4]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE \\lim_state_reg[5] \n (.C(CLK),\n .CE(lim_nxt_state),\n .D(\\lim_state[5]_i_1_n_0 ),\n .Q(lim_state[5]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE \\lim_state_reg[6] \n (.C(CLK),\n .CE(lim_nxt_state),\n .D(\\lim_state[6]_i_1_n_0 ),\n .Q(lim_state[6]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE \\lim_state_reg[7] \n (.C(CLK),\n .CE(lim_nxt_state),\n .D(\\lim_state[7]_i_1_n_0 ),\n .Q(lim_state[7]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE \\lim_state_reg[8] \n (.C(CLK),\n .CE(lim_nxt_state),\n .D(\\lim_state[8]_i_1_n_0 ),\n .Q(lim_state[8]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE \\lim_state_reg[9] \n (.C(CLK),\n .CE(lim_nxt_state),\n .D(\\lim_state[9]_i_1_n_0 ),\n .Q(lim_state[9]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\mmcm_current[0]_i_1 \n (.I0(\\mmcm_current[0]_i_2_n_0 ),\n .I1(stg3_dec_r),\n .I2(\\mmcm_init_lead_reg_n_0_[0] ),\n .I3(\\mmcm_init_lead[5]_i_2_n_0 ),\n .I4(Q[0]),\n .O(\\mmcm_current[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair387\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mmcm_current[0]_i_2 \n (.I0(\\mmcm_init_trail_reg_n_0_[0] ),\n .I1(\\mmcm_init_trail[5]_i_2_n_0 ),\n .I2(\\rise_lead_r_reg[5] [0]),\n .O(\\mmcm_current[0]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\mmcm_current[1]_i_1 \n (.I0(\\mmcm_current[1]_i_2_n_0 ),\n .I1(stg3_dec_r),\n .I2(\\mmcm_init_lead_reg_n_0_[1] ),\n .I3(\\mmcm_init_lead[5]_i_2_n_0 ),\n .I4(Q[1]),\n .O(\\mmcm_current[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair388\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mmcm_current[1]_i_2 \n (.I0(\\mmcm_init_trail_reg_n_0_[1] ),\n .I1(\\mmcm_init_trail[5]_i_2_n_0 ),\n .I2(\\rise_lead_r_reg[5] [1]),\n .O(\\mmcm_current[1]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\mmcm_current[2]_i_1 \n (.I0(\\mmcm_current[2]_i_2_n_0 ),\n .I1(stg3_dec_r),\n .I2(\\mmcm_init_lead_reg_n_0_[2] ),\n .I3(\\mmcm_init_lead[5]_i_2_n_0 ),\n .I4(Q[2]),\n .O(\\mmcm_current[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair389\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mmcm_current[2]_i_2 \n (.I0(\\mmcm_init_trail_reg_n_0_[2] ),\n .I1(\\mmcm_init_trail[5]_i_2_n_0 ),\n .I2(\\rise_lead_r_reg[5] [2]),\n .O(\\mmcm_current[2]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\mmcm_current[3]_i_1 \n (.I0(\\mmcm_current[3]_i_2_n_0 ),\n .I1(stg3_dec_r),\n .I2(\\mmcm_init_lead_reg_n_0_[3] ),\n .I3(\\mmcm_init_lead[5]_i_2_n_0 ),\n .I4(Q[3]),\n .O(\\mmcm_current[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair387\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mmcm_current[3]_i_2 \n (.I0(\\mmcm_init_trail_reg_n_0_[3] ),\n .I1(\\mmcm_init_trail[5]_i_2_n_0 ),\n .I2(\\rise_lead_r_reg[5] [3]),\n .O(\\mmcm_current[3]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\mmcm_current[4]_i_1 \n (.I0(\\mmcm_current[4]_i_2_n_0 ),\n .I1(stg3_dec_r),\n .I2(\\mmcm_init_lead_reg_n_0_[4] ),\n .I3(\\mmcm_init_lead[5]_i_2_n_0 ),\n .I4(Q[4]),\n .O(\\mmcm_current[4]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair388\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mmcm_current[4]_i_2 \n (.I0(\\mmcm_init_trail_reg_n_0_[4] ),\n .I1(\\mmcm_init_trail[5]_i_2_n_0 ),\n .I2(\\rise_lead_r_reg[5] [4]),\n .O(\\mmcm_current[4]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\mmcm_current[5]_i_1 \n (.I0(\\mmcm_current[5]_i_2_n_0 ),\n .I1(stg3_dec_r),\n .I2(\\mmcm_init_lead_reg_n_0_[5] ),\n .I3(\\mmcm_init_lead[5]_i_2_n_0 ),\n .I4(Q[5]),\n .O(\\mmcm_current[5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair389\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\mmcm_current[5]_i_2 \n (.I0(\\mmcm_init_trail_reg_n_0_[5] ),\n .I1(\\mmcm_init_trail[5]_i_2_n_0 ),\n .I2(\\rise_lead_r_reg[5] [5]),\n .O(\\mmcm_current[5]_i_2_n_0 ));\n FDRE \\mmcm_current_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mmcm_current[0]_i_1_n_0 ),\n .Q(\\mmcm_current_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE \\mmcm_current_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mmcm_current[1]_i_1_n_0 ),\n .Q(\\mmcm_current_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE \\mmcm_current_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mmcm_current[2]_i_1_n_0 ),\n .Q(\\mmcm_current_reg_n_0_[2] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE \\mmcm_current_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mmcm_current[3]_i_1_n_0 ),\n .Q(\\mmcm_current_reg_n_0_[3] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE \\mmcm_current_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mmcm_current[4]_i_1_n_0 ),\n .Q(\\mmcm_current_reg_n_0_[4] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE \\mmcm_current_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mmcm_current[5]_i_1_n_0 ),\n .Q(\\mmcm_current_reg_n_0_[5] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n LUT3 #(\n .INIT(8'h20)) \n \\mmcm_init_lead[5]_i_1 \n (.I0(\\mmcm_init_lead[5]_i_2_n_0 ),\n .I1(detect_done_r),\n .I2(done_r_reg_1),\n .O(mmcm_init_lead));\n LUT4 #(\n .INIT(16'h0004)) \n \\mmcm_init_lead[5]_i_2 \n (.I0(\\mmcm_init_lead[5]_i_3_n_0 ),\n .I1(\\mmcm_init_lead[5]_i_4_n_0 ),\n .I2(\\mmcm_init_lead[5]_i_5_n_0 ),\n .I3(\\mmcm_init_lead[5]_i_6_n_0 ),\n .O(\\mmcm_init_lead[5]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'h4F44)) \n \\mmcm_init_lead[5]_i_3 \n (.I0(\\stg3_tap_cnt_reg_n_0_[4] ),\n .I1(stg3_inc_val[4]),\n .I2(\\stg3_tap_cnt_reg_n_0_[5] ),\n .I3(stg3_inc_val[5]),\n .O(\\mmcm_init_lead[5]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'hD0DD)) \n \\mmcm_init_lead[5]_i_4 \n (.I0(stg3_inc_val[1]),\n .I1(\\stg3_tap_cnt_reg_n_0_[1] ),\n .I2(\\stg3_tap_cnt_reg_n_0_[0] ),\n .I3(stg3_inc_val[0]),\n .O(\\mmcm_init_lead[5]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h5D5DFF5D)) \n \\mmcm_init_lead[5]_i_5 \n (.I0(\\mmcm_init_lead[5]_i_7_n_0 ),\n .I1(\\stg3_tap_cnt_reg_n_0_[5] ),\n .I2(stg3_inc_val[5]),\n .I3(\\stg3_tap_cnt_reg_n_0_[0] ),\n .I4(stg3_inc_val[0]),\n .O(\\mmcm_init_lead[5]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'h22F2FFFF)) \n \\mmcm_init_lead[5]_i_6 \n (.I0(\\stg3_tap_cnt_reg_n_0_[1] ),\n .I1(stg3_inc_val[1]),\n .I2(\\stg3_tap_cnt_reg_n_0_[2] ),\n .I3(stg3_inc_val[2]),\n .I4(\\mmcm_init_lead[5]_i_8_n_0 ),\n .O(\\mmcm_init_lead[5]_i_6_n_0 ));\n LUT4 #(\n .INIT(16'hD0DD)) \n \\mmcm_init_lead[5]_i_7 \n (.I0(stg3_inc_val[3]),\n .I1(\\stg3_tap_cnt_reg_n_0_[3] ),\n .I2(\\stg3_tap_cnt_reg_n_0_[2] ),\n .I3(stg3_inc_val[2]),\n .O(\\mmcm_init_lead[5]_i_7_n_0 ));\n LUT4 #(\n .INIT(16'hD0DD)) \n \\mmcm_init_lead[5]_i_8 \n (.I0(\\stg3_tap_cnt_reg_n_0_[4] ),\n .I1(stg3_inc_val[4]),\n .I2(stg3_inc_val[3]),\n .I3(\\stg3_tap_cnt_reg_n_0_[3] ),\n .O(\\mmcm_init_lead[5]_i_8_n_0 ));\n FDRE \\mmcm_init_lead_reg[0] \n (.C(CLK),\n .CE(mmcm_init_lead),\n .D(\\rise_lead_r_reg[5] [0]),\n .Q(\\mmcm_init_lead_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE \\mmcm_init_lead_reg[1] \n (.C(CLK),\n .CE(mmcm_init_lead),\n .D(\\rise_lead_r_reg[5] [1]),\n .Q(\\mmcm_init_lead_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE \\mmcm_init_lead_reg[2] \n (.C(CLK),\n .CE(mmcm_init_lead),\n .D(\\rise_lead_r_reg[5] [2]),\n .Q(\\mmcm_init_lead_reg_n_0_[2] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE \\mmcm_init_lead_reg[3] \n (.C(CLK),\n .CE(mmcm_init_lead),\n .D(\\rise_lead_r_reg[5] [3]),\n .Q(\\mmcm_init_lead_reg_n_0_[3] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE \\mmcm_init_lead_reg[4] \n (.C(CLK),\n .CE(mmcm_init_lead),\n .D(\\rise_lead_r_reg[5] [4]),\n .Q(\\mmcm_init_lead_reg_n_0_[4] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE \\mmcm_init_lead_reg[5] \n (.C(CLK),\n .CE(mmcm_init_lead),\n .D(\\rise_lead_r_reg[5] [5]),\n .Q(\\mmcm_init_lead_reg_n_0_[5] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n LUT3 #(\n .INIT(8'h40)) \n \\mmcm_init_trail[5]_i_1 \n (.I0(detect_done_r),\n .I1(done_r_reg_1),\n .I2(\\mmcm_init_trail[5]_i_2_n_0 ),\n .O(mmcm_init_trail));\n LUT6 #(\n .INIT(64'h0000000009000009)) \n \\mmcm_init_trail[5]_i_2 \n (.I0(stg3_dec_val[5]),\n .I1(\\stg3_tap_cnt_reg_n_0_[5] ),\n .I2(\\mmcm_init_trail[5]_i_3_n_0 ),\n .I3(\\stg3_tap_cnt_reg_n_0_[3] ),\n .I4(stg3_dec_val[3]),\n .I5(\\mmcm_init_trail[5]_i_4_n_0 ),\n .O(\\mmcm_init_trail[5]_i_2_n_0 ));\n LUT2 #(\n .INIT(4'h6)) \n \\mmcm_init_trail[5]_i_3 \n (.I0(\\stg3_tap_cnt_reg_n_0_[4] ),\n .I1(stg3_dec_val[4]),\n .O(\\mmcm_init_trail[5]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\mmcm_init_trail[5]_i_4 \n (.I0(\\stg3_tap_cnt_reg_n_0_[1] ),\n .I1(stg3_dec_val[1]),\n .I2(\\stg3_tap_cnt_reg_n_0_[2] ),\n .I3(stg3_dec_val[2]),\n .I4(stg3_dec_val[0]),\n .I5(\\stg3_tap_cnt_reg_n_0_[0] ),\n .O(\\mmcm_init_trail[5]_i_4_n_0 ));\n FDRE \\mmcm_init_trail_reg[0] \n (.C(CLK),\n .CE(mmcm_init_trail),\n .D(Q[0]),\n .Q(\\mmcm_init_trail_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE \\mmcm_init_trail_reg[1] \n (.C(CLK),\n .CE(mmcm_init_trail),\n .D(Q[1]),\n .Q(\\mmcm_init_trail_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE \\mmcm_init_trail_reg[2] \n (.C(CLK),\n .CE(mmcm_init_trail),\n .D(Q[2]),\n .Q(\\mmcm_init_trail_reg_n_0_[2] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE \\mmcm_init_trail_reg[3] \n (.C(CLK),\n .CE(mmcm_init_trail),\n .D(Q[3]),\n .Q(\\mmcm_init_trail_reg_n_0_[3] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE \\mmcm_init_trail_reg[4] \n (.C(CLK),\n .CE(mmcm_init_trail),\n .D(Q[4]),\n .Q(\\mmcm_init_trail_reg_n_0_[4] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n FDRE \\mmcm_init_trail_reg[5] \n (.C(CLK),\n .CE(mmcm_init_trail),\n .D(Q[5]),\n .Q(\\mmcm_init_trail_reg_n_0_[5] ),\n .R(rstdiv0_sync_r1_reg_rep__11));\n CARRY4 mod_sub0_return0__14_carry\n (.CI(1'b0),\n .CO({mod_sub0_return0__14_carry_n_0,mod_sub0_return0__14_carry_n_1,mod_sub0_return0__14_carry_n_2,mod_sub0_return0__14_carry_n_3}),\n .CYINIT(1'b1),\n .DI({\\mmcm_current_reg_n_0_[3] ,\\mmcm_current_reg_n_0_[2] ,\\mmcm_current_reg_n_0_[1] ,\\mmcm_current_reg_n_0_[0] }),\n .O({mod_sub0_return0__14_carry_n_4,mod_sub0_return0__14_carry_n_5,mod_sub0_return0__14_carry_n_6,NLW_mod_sub0_return0__14_carry_O_UNCONNECTED[0]}),\n .S({mod_sub0_return0__14_carry_i_1_n_0,mod_sub0_return0__14_carry_i_2_n_0,mod_sub0_return0__14_carry_i_3_n_0,mod_sub0_return0__14_carry_i_4_n_0}));\n CARRY4 mod_sub0_return0__14_carry__0\n (.CI(mod_sub0_return0__14_carry_n_0),\n .CO({NLW_mod_sub0_return0__14_carry__0_CO_UNCONNECTED[3],mod_sub0_return0__14_carry__0_n_1,NLW_mod_sub0_return0__14_carry__0_CO_UNCONNECTED[1],mod_sub0_return0__14_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,\\mmcm_current_reg_n_0_[5] ,\\mmcm_current_reg_n_0_[4] }),\n .O({NLW_mod_sub0_return0__14_carry__0_O_UNCONNECTED[3:2],mod_sub0_return0__14_carry__0_n_6,mod_sub0_return0__14_carry__0_n_7}),\n .S({1'b0,1'b1,mod_sub0_return0__14_carry__0_i_1_n_0,mod_sub0_return0__14_carry__0_i_2_n_0}));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub0_return0__14_carry__0_i_1\n (.I0(\\mmcm_current_reg_n_0_[5] ),\n .I1(\\mmcm_init_lead_reg_n_0_[5] ),\n .O(mod_sub0_return0__14_carry__0_i_1_n_0));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub0_return0__14_carry__0_i_2\n (.I0(\\mmcm_current_reg_n_0_[4] ),\n .I1(\\mmcm_init_lead_reg_n_0_[4] ),\n .O(mod_sub0_return0__14_carry__0_i_2_n_0));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub0_return0__14_carry_i_1\n (.I0(\\mmcm_current_reg_n_0_[3] ),\n .I1(\\mmcm_init_lead_reg_n_0_[3] ),\n .O(mod_sub0_return0__14_carry_i_1_n_0));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub0_return0__14_carry_i_2\n (.I0(\\mmcm_current_reg_n_0_[2] ),\n .I1(\\mmcm_init_lead_reg_n_0_[2] ),\n .O(mod_sub0_return0__14_carry_i_2_n_0));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub0_return0__14_carry_i_3\n (.I0(\\mmcm_current_reg_n_0_[1] ),\n .I1(\\mmcm_init_lead_reg_n_0_[1] ),\n .O(mod_sub0_return0__14_carry_i_3_n_0));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub0_return0__14_carry_i_4\n (.I0(\\mmcm_current_reg_n_0_[0] ),\n .I1(\\mmcm_init_lead_reg_n_0_[0] ),\n .O(mod_sub0_return0__14_carry_i_4_n_0));\n CARRY4 mod_sub0_return0_carry\n (.CI(1'b0),\n .CO({mod_sub0_return0_carry_n_0,mod_sub0_return0_carry_n_1,mod_sub0_return0_carry_n_2,mod_sub0_return0_carry_n_3}),\n .CYINIT(1'b1),\n .DI({\\mmcm_init_lead_reg_n_0_[3] ,\\mmcm_current_reg_n_0_[2] ,\\mmcm_current_reg_n_0_[1] ,\\mmcm_current_reg_n_0_[0] }),\n .O({mod_sub0_return0_carry_n_4,mod_sub0_return0_carry_n_5,mod_sub0_return0_carry_n_6,mod_sub0_return0_carry_n_7}),\n .S({mod_sub0_return0_carry_i_1_n_0,mod_sub0_return0_carry_i_2_n_0,mod_sub0_return0_carry_i_3_n_0,mod_sub0_return0_carry_i_4_n_0}));\n CARRY4 mod_sub0_return0_carry__0\n (.CI(mod_sub0_return0_carry_n_0),\n .CO({NLW_mod_sub0_return0_carry__0_CO_UNCONNECTED[3:2],mod_sub0_return0_carry__0_n_2,mod_sub0_return0_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,mod_sub0_return0_carry__0_i_1_n_0,mod_sub0_return0_carry__0_i_2_n_0}),\n .O({NLW_mod_sub0_return0_carry__0_O_UNCONNECTED[3],mod_sub0_return0_carry__0_n_5,mod_sub0_return0_carry__0_n_6,mod_sub0_return0_carry__0_n_7}),\n .S({1'b0,mod_sub0_return0_carry__0_i_3_n_0,mod_sub0_return0_carry__0_i_4_n_0,mod_sub0_return0_carry__0_i_5_n_0}));\n LUT2 #(\n .INIT(4'hB)) \n mod_sub0_return0_carry__0_i_1\n (.I0(\\mmcm_current_reg_n_0_[4] ),\n .I1(\\mmcm_init_lead_reg_n_0_[4] ),\n .O(mod_sub0_return0_carry__0_i_1_n_0));\n LUT2 #(\n .INIT(4'h6)) \n mod_sub0_return0_carry__0_i_2\n (.I0(\\mmcm_init_lead_reg_n_0_[4] ),\n .I1(\\mmcm_current_reg_n_0_[4] ),\n .O(mod_sub0_return0_carry__0_i_2_n_0));\n LUT2 #(\n .INIT(4'h2)) \n mod_sub0_return0_carry__0_i_3\n (.I0(\\mmcm_init_lead_reg_n_0_[5] ),\n .I1(\\mmcm_current_reg_n_0_[5] ),\n .O(mod_sub0_return0_carry__0_i_3_n_0));\n LUT4 #(\n .INIT(16'hB44B)) \n mod_sub0_return0_carry__0_i_4\n (.I0(\\mmcm_current_reg_n_0_[4] ),\n .I1(\\mmcm_init_lead_reg_n_0_[4] ),\n .I2(\\mmcm_init_lead_reg_n_0_[5] ),\n .I3(\\mmcm_current_reg_n_0_[5] ),\n .O(mod_sub0_return0_carry__0_i_4_n_0));\n LUT3 #(\n .INIT(8'h69)) \n mod_sub0_return0_carry__0_i_5\n (.I0(\\mmcm_init_lead_reg_n_0_[4] ),\n .I1(\\mmcm_current_reg_n_0_[4] ),\n .I2(\\mmcm_init_lead_reg_n_0_[3] ),\n .O(mod_sub0_return0_carry__0_i_5_n_0));\n LUT2 #(\n .INIT(4'h6)) \n mod_sub0_return0_carry_i_1\n (.I0(\\mmcm_init_lead_reg_n_0_[3] ),\n .I1(\\mmcm_current_reg_n_0_[3] ),\n .O(mod_sub0_return0_carry_i_1_n_0));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub0_return0_carry_i_2\n (.I0(\\mmcm_current_reg_n_0_[2] ),\n .I1(\\mmcm_init_lead_reg_n_0_[2] ),\n .O(mod_sub0_return0_carry_i_2_n_0));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub0_return0_carry_i_3\n (.I0(\\mmcm_current_reg_n_0_[1] ),\n .I1(\\mmcm_init_lead_reg_n_0_[1] ),\n .O(mod_sub0_return0_carry_i_3_n_0));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub0_return0_carry_i_4\n (.I0(\\mmcm_current_reg_n_0_[0] ),\n .I1(\\mmcm_init_lead_reg_n_0_[0] ),\n .O(mod_sub0_return0_carry_i_4_n_0));\n CARRY4 mod_sub_return0__14_carry\n (.CI(1'b0),\n .CO({mod_sub_return0__14_carry_n_0,mod_sub_return0__14_carry_n_1,mod_sub_return0__14_carry_n_2,mod_sub_return0__14_carry_n_3}),\n .CYINIT(1'b1),\n .DI({\\mmcm_init_trail_reg_n_0_[3] ,\\mmcm_init_trail_reg_n_0_[2] ,\\mmcm_init_trail_reg_n_0_[1] ,\\mmcm_init_trail_reg_n_0_[0] }),\n .O({mod_sub_return0__14_carry_n_4,mod_sub_return0__14_carry_n_5,mod_sub_return0__14_carry_n_6,NLW_mod_sub_return0__14_carry_O_UNCONNECTED[0]}),\n .S({mod_sub_return0__14_carry_i_1_n_0,mod_sub_return0__14_carry_i_2_n_0,mod_sub_return0__14_carry_i_3_n_0,mod_sub_return0__14_carry_i_4_n_0}));\n CARRY4 mod_sub_return0__14_carry__0\n (.CI(mod_sub_return0__14_carry_n_0),\n .CO({NLW_mod_sub_return0__14_carry__0_CO_UNCONNECTED[3],mod_sub_return0__14_carry__0_n_1,NLW_mod_sub_return0__14_carry__0_CO_UNCONNECTED[1],mod_sub_return0__14_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,\\mmcm_init_trail_reg_n_0_[5] ,\\mmcm_init_trail_reg_n_0_[4] }),\n .O({NLW_mod_sub_return0__14_carry__0_O_UNCONNECTED[3:2],mod_sub_return0__14_carry__0_n_6,mod_sub_return0__14_carry__0_n_7}),\n .S({1'b0,1'b1,mod_sub_return0__14_carry__0_i_1_n_0,mod_sub_return0__14_carry__0_i_2_n_0}));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub_return0__14_carry__0_i_1\n (.I0(\\mmcm_init_trail_reg_n_0_[5] ),\n .I1(\\mmcm_current_reg_n_0_[5] ),\n .O(mod_sub_return0__14_carry__0_i_1_n_0));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub_return0__14_carry__0_i_2\n (.I0(\\mmcm_init_trail_reg_n_0_[4] ),\n .I1(\\mmcm_current_reg_n_0_[4] ),\n .O(mod_sub_return0__14_carry__0_i_2_n_0));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub_return0__14_carry_i_1\n (.I0(\\mmcm_init_trail_reg_n_0_[3] ),\n .I1(\\mmcm_current_reg_n_0_[3] ),\n .O(mod_sub_return0__14_carry_i_1_n_0));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub_return0__14_carry_i_2\n (.I0(\\mmcm_init_trail_reg_n_0_[2] ),\n .I1(\\mmcm_current_reg_n_0_[2] ),\n .O(mod_sub_return0__14_carry_i_2_n_0));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub_return0__14_carry_i_3\n (.I0(\\mmcm_init_trail_reg_n_0_[1] ),\n .I1(\\mmcm_current_reg_n_0_[1] ),\n .O(mod_sub_return0__14_carry_i_3_n_0));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub_return0__14_carry_i_4\n (.I0(\\mmcm_init_trail_reg_n_0_[0] ),\n .I1(\\mmcm_current_reg_n_0_[0] ),\n .O(mod_sub_return0__14_carry_i_4_n_0));\n CARRY4 mod_sub_return0_carry\n (.CI(1'b0),\n .CO({mod_sub_return0_carry_n_0,mod_sub_return0_carry_n_1,mod_sub_return0_carry_n_2,mod_sub_return0_carry_n_3}),\n .CYINIT(1'b1),\n .DI({\\mmcm_current_reg_n_0_[3] ,\\mmcm_init_trail_reg_n_0_[2] ,\\mmcm_init_trail_reg_n_0_[1] ,\\mmcm_init_trail_reg_n_0_[0] }),\n .O({mod_sub_return0_carry_n_4,mod_sub_return0_carry_n_5,mod_sub_return0_carry_n_6,mod_sub_return0_carry_n_7}),\n .S({mod_sub_return0_carry_i_1__0_n_0,mod_sub_return0_carry_i_2_n_0,mod_sub_return0_carry_i_3_n_0,mod_sub_return0_carry_i_4_n_0}));\n CARRY4 mod_sub_return0_carry__0\n (.CI(mod_sub_return0_carry_n_0),\n .CO({NLW_mod_sub_return0_carry__0_CO_UNCONNECTED[3:2],mod_sub_return0_carry__0_n_2,mod_sub_return0_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,mod_sub_return0_carry__0_i_1__0_n_0,mod_sub_return0_carry__0_i_2_n_0}),\n .O({NLW_mod_sub_return0_carry__0_O_UNCONNECTED[3],mod_sub_return0_carry__0_n_5,mod_sub_return0_carry__0_n_6,mod_sub_return0_carry__0_n_7}),\n .S({1'b0,mod_sub_return0_carry__0_i_3_n_0,mod_sub_return0_carry__0_i_4_n_0,mod_sub_return0_carry__0_i_5_n_0}));\n LUT2 #(\n .INIT(4'hB)) \n mod_sub_return0_carry__0_i_1__0\n (.I0(\\mmcm_init_trail_reg_n_0_[4] ),\n .I1(\\mmcm_current_reg_n_0_[4] ),\n .O(mod_sub_return0_carry__0_i_1__0_n_0));\n LUT2 #(\n .INIT(4'h6)) \n mod_sub_return0_carry__0_i_2\n (.I0(\\mmcm_current_reg_n_0_[4] ),\n .I1(\\mmcm_init_trail_reg_n_0_[4] ),\n .O(mod_sub_return0_carry__0_i_2_n_0));\n LUT2 #(\n .INIT(4'h2)) \n mod_sub_return0_carry__0_i_3\n (.I0(\\mmcm_current_reg_n_0_[5] ),\n .I1(\\mmcm_init_trail_reg_n_0_[5] ),\n .O(mod_sub_return0_carry__0_i_3_n_0));\n LUT4 #(\n .INIT(16'hB44B)) \n mod_sub_return0_carry__0_i_4\n (.I0(\\mmcm_init_trail_reg_n_0_[4] ),\n .I1(\\mmcm_current_reg_n_0_[4] ),\n .I2(\\mmcm_current_reg_n_0_[5] ),\n .I3(\\mmcm_init_trail_reg_n_0_[5] ),\n .O(mod_sub_return0_carry__0_i_4_n_0));\n LUT3 #(\n .INIT(8'h69)) \n mod_sub_return0_carry__0_i_5\n (.I0(\\mmcm_current_reg_n_0_[4] ),\n .I1(\\mmcm_init_trail_reg_n_0_[4] ),\n .I2(\\mmcm_current_reg_n_0_[3] ),\n .O(mod_sub_return0_carry__0_i_5_n_0));\n LUT2 #(\n .INIT(4'h6)) \n mod_sub_return0_carry_i_1__0\n (.I0(\\mmcm_current_reg_n_0_[3] ),\n .I1(\\mmcm_init_trail_reg_n_0_[3] ),\n .O(mod_sub_return0_carry_i_1__0_n_0));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub_return0_carry_i_2\n (.I0(\\mmcm_init_trail_reg_n_0_[2] ),\n .I1(\\mmcm_current_reg_n_0_[2] ),\n .O(mod_sub_return0_carry_i_2_n_0));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub_return0_carry_i_3\n (.I0(\\mmcm_init_trail_reg_n_0_[1] ),\n .I1(\\mmcm_current_reg_n_0_[1] ),\n .O(mod_sub_return0_carry_i_3_n_0));\n LUT2 #(\n .INIT(4'h9)) \n mod_sub_return0_carry_i_4\n (.I0(\\mmcm_init_trail_reg_n_0_[0] ),\n .I1(\\mmcm_current_reg_n_0_[0] ),\n .O(mod_sub_return0_carry_i_4_n_0));\n LUT4 #(\n .INIT(16'h8A88)) \n oclkdelay_center_calib_start_r_i_2\n (.I0(scanning_right),\n .I1(o2f_r_reg),\n .I2(oclkdelay_center_calib_start_r_i_3_n_0),\n .I3(oclkdelay_center_calib_start_r_i_4_n_0),\n .O(oclkdelay_center_calib_start_r_reg));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n oclkdelay_center_calib_start_r_i_3\n (.I0(oclkdelay_center_calib_start_r_reg_0[2]),\n .I1(\\stg3_r_reg[5] [2]),\n .I2(oclkdelay_center_calib_start_r_reg_0[1]),\n .I3(\\stg3_r_reg[5] [1]),\n .I4(\\stg3_r_reg[5] [0]),\n .I5(oclkdelay_center_calib_start_r_reg_0[0]),\n .O(oclkdelay_center_calib_start_r_i_3_n_0));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n oclkdelay_center_calib_start_r_i_4\n (.I0(oclkdelay_center_calib_start_r_reg_0[5]),\n .I1(\\stg3_r_reg[5] [5]),\n .I2(oclkdelay_center_calib_start_r_reg_0[4]),\n .I3(\\stg3_r_reg[5] [4]),\n .I4(oclkdelay_center_calib_start_r_reg_0[3]),\n .I5(\\stg3_r_reg[5] [3]),\n .O(oclkdelay_center_calib_start_r_i_4_n_0));\n LUT5 #(\n .INIT(32'h55555554)) \n po_stg23_sel_r_i_1\n (.I0(rstdiv0_sync_r1_reg_rep__26),\n .I1(\\po_wait_r_reg[0] ),\n .I2(\\sm_r_reg[2] ),\n .I3(lim2stg3_dec),\n .I4(lim2stg3_inc),\n .O(po_stg23_sel_r_reg));\n LUT6 #(\n .INIT(64'hBFFFBFFF20200000)) \n poc_ready_r_i_1\n (.I0(lim_state[2]),\n .I1(lim_state[3]),\n .I2(write_request_r_i_2_n_0),\n .I3(done_r_reg_1),\n .I4(wait_cnt_done),\n .I5(lim2poc_rdy),\n .O(poc_ready_r_i_1_n_0));\n FDRE poc_ready_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(poc_ready_r_i_1_n_0),\n .Q(lim2poc_rdy),\n .R(rstdiv0_sync_r1_reg_rep__10));\n LUT5 #(\n .INIT(32'hFFF70004)) \n prech_req_r_i_1__0\n (.I0(prech_done),\n .I1(prech_req_r_i_2_n_0),\n .I2(\\lim_state[13]_i_4_n_0 ),\n .I3(\\lim_state[2]_i_3_n_0 ),\n .I4(prech_req_r_reg_0),\n .O(prech_req_r_i_1__0_n_0));\n LUT6 #(\n .INIT(64'h0000000000010000)) \n prech_req_r_i_2\n (.I0(lim_state[6]),\n .I1(lim_state[5]),\n .I2(lim_state[7]),\n .I3(lim_state[4]),\n .I4(lim_state[12]),\n .I5(lim_state[13]),\n .O(prech_req_r_i_2_n_0));\n FDRE prech_req_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prech_req_r_i_1__0_n_0),\n .Q(prech_req_r_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__10));\n LUT4 #(\n .INIT(16'h000E)) \n scanning_right_r_i_2\n (.I0(scanning_right_r_i_4_n_0),\n .I1(scanning_right_r_i_5_n_0),\n .I2(scan_right),\n .I3(scanning_right),\n .O(scanning_right_r_reg));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n scanning_right_r_i_4\n (.I0(scanning_right_r_reg_0[0]),\n .I1(\\stg3_r_reg[5] [0]),\n .I2(\\stg3_r_reg[5] [1]),\n .I3(scanning_right_r_reg_0[1]),\n .I4(\\stg3_r_reg[5] [2]),\n .I5(scanning_right_r_reg_0[2]),\n .O(scanning_right_r_i_4_n_0));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n scanning_right_r_i_5\n (.I0(scanning_right_r_reg_0[3]),\n .I1(\\stg3_r_reg[5] [3]),\n .I2(\\stg3_r_reg[5] [4]),\n .I3(scanning_right_r_reg_0[4]),\n .I4(\\stg3_r_reg[5] [5]),\n .I5(scanning_right_r_reg_0[5]),\n .O(scanning_right_r_i_5_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFDF00000008)) \n stg2_dec_req_r_i_1\n (.I0(stg2_inc_req_r_i_2_n_0),\n .I1(lim_state[8]),\n .I2(lim_state[10]),\n .I3(lim_state[0]),\n .I4(lim_state[7]),\n .I5(lim2stg2_dec),\n .O(stg2_dec_req_r_i_1_n_0));\n FDRE stg2_dec_req_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(stg2_dec_req_r_i_1_n_0),\n .Q(lim2stg2_dec),\n .R(rstdiv0_sync_r1_reg_rep__10));\n LUT6 #(\n .INIT(64'hFFFFFFFD00003020)) \n stg2_inc_r_i_1\n (.I0(\\lim_state[9]_i_3_n_0 ),\n .I1(stg2_inc_r_i_2_n_0),\n .I2(stg2_inc_r_i_3_n_0),\n .I3(lim_state[0]),\n .I4(stg2_inc_r_i_4_n_0),\n .I5(stg2_inc_r),\n .O(stg2_inc_r_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair379\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n stg2_inc_r_i_2\n (.I0(lim_state[13]),\n .I1(lim_state[12]),\n .I2(lim_state[9]),\n .I3(lim_state[10]),\n .O(stg2_inc_r_i_2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair392\" *) \n LUT3 #(\n .INIT(8'h04)) \n stg2_inc_r_i_3\n (.I0(lim_start_r),\n .I1(lim_start),\n .I2(lim_state[11]),\n .O(stg2_inc_r_i_3_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair378\" *) \n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n stg2_inc_r_i_4\n (.I0(lim_state[1]),\n .I1(lim_state[3]),\n .I2(lim_state[2]),\n .I3(lim_state[4]),\n .I4(wait_cnt_en_r_i_3_n_0),\n .O(stg2_inc_r_i_4_n_0));\n FDRE stg2_inc_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(stg2_inc_r_i_1_n_0),\n .Q(stg2_inc_r),\n .R(rstdiv0_sync_r1_reg_rep__10));\n LUT6 #(\n .INIT(64'hFFFFFFF700000020)) \n stg2_inc_req_r_i_1\n (.I0(stg2_inc_req_r_i_2_n_0),\n .I1(lim_state[10]),\n .I2(lim_state[7]),\n .I3(lim_state[8]),\n .I4(lim_state[0]),\n .I5(lim2stg2_inc),\n .O(stg2_inc_req_r_i_1_n_0));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n stg2_inc_req_r_i_2\n (.I0(\\lim_state[0]_i_2_n_0 ),\n .I1(lim_state[12]),\n .I2(lim_state[11]),\n .I3(lim_state[13]),\n .I4(lim_state[9]),\n .I5(\\lim_state[10]_i_3_n_0 ),\n .O(stg2_inc_req_r_i_2_n_0));\n FDRE stg2_inc_req_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(stg2_inc_req_r_i_1_n_0),\n .Q(lim2stg2_inc),\n .R(rstdiv0_sync_r1_reg_rep__10));\n (* SOFT_HLUTNM = \"soft_lutpair390\" *) \n LUT3 #(\n .INIT(8'h47)) \n \\stg2_tap_cnt[0]_i_1 \n (.I0(\\wl_po_fine_cnt_reg[18] ),\n .I1(\\stg2_tap_cnt_reg[0]_0 ),\n .I2(\\stg2_tap_cnt_reg[3]_0 [0]),\n .O(p_0_in__0[0]));\n LUT5 #(\n .INIT(32'h8BB8B88B)) \n \\stg2_tap_cnt[1]_i_1 \n (.I0(\\wl_po_fine_cnt_reg[14] [0]),\n .I1(\\stg2_tap_cnt_reg[0]_0 ),\n .I2(\\stg2_tap_cnt[1]_i_3_n_0 ),\n .I3(\\stg2_tap_cnt_reg[3]_0 [1]),\n .I4(\\stg2_tap_cnt_reg[3]_0 [0]),\n .O(p_0_in__0[1]));\n LUT6 #(\n .INIT(64'h0000000000000100)) \n \\stg2_tap_cnt[1]_i_3 \n (.I0(\\stg2_tap_cnt[1]_i_4_n_0 ),\n .I1(lim_state[12]),\n .I2(\\lim_state[2]_i_3_n_0 ),\n .I3(lim_state[7]),\n .I4(lim_state[6]),\n .I5(lim_state[5]),\n .O(\\stg2_tap_cnt[1]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\stg2_tap_cnt[1]_i_4 \n (.I0(lim_state[9]),\n .I1(lim_state[8]),\n .I2(lim_state[11]),\n .I3(lim_state[10]),\n .I4(lim_state[13]),\n .I5(lim_state[4]),\n .O(\\stg2_tap_cnt[1]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair373\" *) \n LUT5 #(\n .INIT(32'h8B8B8BB8)) \n \\stg2_tap_cnt[2]_i_1 \n (.I0(\\wl_po_fine_cnt_reg[14] [1]),\n .I1(\\stg2_tap_cnt_reg[0]_0 ),\n .I2(\\stg2_tap_cnt_reg[3]_0 [2]),\n .I3(\\stg2_tap_cnt[2]_i_3_n_0 ),\n .I4(\\stg2_tap_cnt[2]_i_4_n_0 ),\n .O(p_0_in__0[2]));\n LUT6 #(\n .INIT(64'h0001000000000000)) \n \\stg2_tap_cnt[2]_i_3 \n (.I0(\\stg2_tap_cnt[2]_i_5_n_0 ),\n .I1(\\lim_state[13]_i_4_n_0 ),\n .I2(lim_state[12]),\n .I3(\\lim_state[2]_i_3_n_0 ),\n .I4(\\stg2_tap_cnt_reg[3]_0 [1]),\n .I5(\\stg2_tap_cnt_reg[3]_0 [0]),\n .O(\\stg2_tap_cnt[2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h1111111111101111)) \n \\stg2_tap_cnt[2]_i_4 \n (.I0(\\stg2_tap_cnt_reg[3]_0 [1]),\n .I1(\\stg2_tap_cnt_reg[3]_0 [0]),\n .I2(lim_state[5]),\n .I3(lim_state[6]),\n .I4(lim_state[7]),\n .I5(\\stg2_tap_cnt[2]_i_6_n_0 ),\n .O(\\stg2_tap_cnt[2]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFFEFF)) \n \\stg2_tap_cnt[2]_i_5 \n (.I0(lim_state[6]),\n .I1(lim_state[5]),\n .I2(lim_state[4]),\n .I3(lim_state[7]),\n .I4(lim_state[13]),\n .O(\\stg2_tap_cnt[2]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n \\stg2_tap_cnt[2]_i_6 \n (.I0(\\lim_state[2]_i_3_n_0 ),\n .I1(lim_state[12]),\n .I2(lim_state[4]),\n .I3(lim_state[13]),\n .I4(\\lim_state[13]_i_4_n_0 ),\n .O(\\stg2_tap_cnt[2]_i_6_n_0 ));\n LUT5 #(\n .INIT(32'h74474774)) \n \\stg2_tap_cnt[3]_i_1 \n (.I0(\\wl_po_fine_cnt_reg[3] ),\n .I1(\\stg2_tap_cnt[3]_i_3_n_0 ),\n .I2(\\stg2_tap_cnt[4]_i_3_n_0 ),\n .I3(stg2_tap_cnt_reg__0[3]),\n .I4(\\stg2_tap_cnt_reg[3]_0 [2]),\n .O(p_0_in__0[3]));\n LUT6 #(\n .INIT(64'h0000000000000110)) \n \\stg2_tap_cnt[3]_i_3 \n (.I0(wait_cnt_en_r_i_2_n_0),\n .I1(lim_state[3]),\n .I2(lim_state[1]),\n .I3(lim_state[0]),\n .I4(lim_state[4]),\n .I5(lim_state[2]),\n .O(\\stg2_tap_cnt[3]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h7447747474744774)) \n \\stg2_tap_cnt[4]_i_1 \n (.I0(\\byte_r_reg[0] ),\n .I1(\\stg2_tap_cnt_reg[0]_0 ),\n .I2(stg2_tap_cnt_reg__0[4]),\n .I3(\\stg2_tap_cnt[4]_i_3_n_0 ),\n .I4(stg2_tap_cnt_reg__0[3]),\n .I5(\\stg2_tap_cnt_reg[3]_0 [2]),\n .O(p_0_in__0[4]));\n LUT5 #(\n .INIT(32'h01FF0101)) \n \\stg2_tap_cnt[4]_i_3 \n (.I0(\\stg2_tap_cnt[1]_i_3_n_0 ),\n .I1(\\stg2_tap_cnt_reg[3]_0 [0]),\n .I2(\\stg2_tap_cnt_reg[3]_0 [1]),\n .I3(\\stg2_tap_cnt[2]_i_3_n_0 ),\n .I4(\\stg2_tap_cnt_reg[3]_0 [2]),\n .O(\\stg2_tap_cnt[4]_i_3_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\stg2_tap_cnt[5]_i_2 \n (.I0(\\stg2_tap_cnt_reg[0]_0 ),\n .I1(\\lim_state[10]_i_1_n_0 ),\n .O(stg2_tap_cnt0));\n (* SOFT_HLUTNM = \"soft_lutpair390\" *) \n LUT3 #(\n .INIT(8'h74)) \n \\stg2_tap_cnt[5]_i_3 \n (.I0(\\wl_po_fine_cnt_reg[17] ),\n .I1(\\stg2_tap_cnt_reg[0]_0 ),\n .I2(\\stg2_tap_cnt[5]_i_6_n_0 ),\n .O(p_0_in__0[5]));\n LUT4 #(\n .INIT(16'h0440)) \n \\stg2_tap_cnt[5]_i_4 \n (.I0(\\lim_state[13]_i_7_n_0 ),\n .I1(\\lim_state[1]_i_2_n_0 ),\n .I2(lim_state[0]),\n .I3(lim_state[1]),\n .O(\\stg2_tap_cnt_reg[0]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair367\" *) \n LUT5 #(\n .INIT(32'hAAA96AAA)) \n \\stg2_tap_cnt[5]_i_6 \n (.I0(stg2_tap_cnt_reg__0[5]),\n .I1(stg2_tap_cnt_reg__0[4]),\n .I2(\\stg2_tap_cnt_reg[3]_0 [2]),\n .I3(stg2_tap_cnt_reg__0[3]),\n .I4(\\stg2_tap_cnt[4]_i_3_n_0 ),\n .O(\\stg2_tap_cnt[5]_i_6_n_0 ));\n FDRE \\stg2_tap_cnt_reg[0] \n (.C(CLK),\n .CE(stg2_tap_cnt0),\n .D(p_0_in__0[0]),\n .Q(\\stg2_tap_cnt_reg[3]_0 [0]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE \\stg2_tap_cnt_reg[1] \n (.C(CLK),\n .CE(stg2_tap_cnt0),\n .D(p_0_in__0[1]),\n .Q(\\stg2_tap_cnt_reg[3]_0 [1]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE \\stg2_tap_cnt_reg[2] \n (.C(CLK),\n .CE(stg2_tap_cnt0),\n .D(p_0_in__0[2]),\n .Q(\\stg2_tap_cnt_reg[3]_0 [2]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE \\stg2_tap_cnt_reg[3] \n (.C(CLK),\n .CE(stg2_tap_cnt0),\n .D(p_0_in__0[3]),\n .Q(stg2_tap_cnt_reg__0[3]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE \\stg2_tap_cnt_reg[4] \n (.C(CLK),\n .CE(stg2_tap_cnt0),\n .D(p_0_in__0[4]),\n .Q(stg2_tap_cnt_reg__0[4]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE \\stg2_tap_cnt_reg[5] \n (.C(CLK),\n .CE(stg2_tap_cnt0),\n .D(p_0_in__0[5]),\n .Q(stg2_tap_cnt_reg__0[5]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE stg3_dec2init_val_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(stg3_dec2init_val_r),\n .Q(stg3_dec2init_val_r1),\n .R(rstdiv0_sync_r1_reg_rep__10));\n LUT6 #(\n .INIT(64'hFFFFAFAA00000D00)) \n stg3_dec2init_val_r_i_1\n (.I0(lim_state[4]),\n .I1(stg3_dec2init_val_r_i_2_n_0),\n .I2(lim_state[13]),\n .I3(wait_cnt_done),\n .I4(stg3_dec2init_val_r_i_3_n_0),\n .I5(stg3_dec2init_val_r),\n .O(stg3_dec2init_val_r_i_1_n_0));\n LUT4 #(\n .INIT(16'h5557)) \n stg3_dec2init_val_r_i_10\n (.I0(mod_sub0_return0_carry_n_4),\n .I1(mod_sub0_return0_carry_n_6),\n .I2(mod_sub0_return0_carry_n_5),\n .I3(mod_sub0_return0_carry_n_7),\n .O(stg3_dec2init_val_r_i_10_n_0));\n LUT6 #(\n .INIT(64'h40F440F4FFFF40F4)) \n stg3_dec2init_val_r_i_12\n (.I0(\\mmcm_current_reg_n_0_[0] ),\n .I1(\\mmcm_init_lead_reg_n_0_[0] ),\n .I2(\\mmcm_init_lead_reg_n_0_[1] ),\n .I3(\\mmcm_current_reg_n_0_[1] ),\n .I4(\\mmcm_init_lead_reg_n_0_[2] ),\n .I5(\\mmcm_current_reg_n_0_[2] ),\n .O(stg3_dec2init_val_r_i_12_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair375\" *) \n LUT2 #(\n .INIT(4'h2)) \n stg3_dec2init_val_r_i_13\n (.I0(\\mmcm_init_lead_reg_n_0_[4] ),\n .I1(\\mmcm_current_reg_n_0_[4] ),\n .O(stg3_dec2init_val_r_i_13_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair393\" *) \n LUT2 #(\n .INIT(4'h9)) \n stg3_dec2init_val_r_i_14\n (.I0(\\mmcm_current_reg_n_0_[0] ),\n .I1(\\mmcm_init_lead_reg_n_0_[0] ),\n .O(stg3_dec2init_val_r_reg_0));\n LUT6 #(\n .INIT(64'h4445554544555555)) \n stg3_dec2init_val_r_i_2\n (.I0(stg3_dec_r),\n .I1(stg3_dec2init_val_r_i_4_n_0),\n .I2(stg3_dec2init_val_r_i_5_n_0),\n .I3(stg3_dec2init_val_r_i_6_n_0),\n .I4(stg3_dec2init_val_r_i_7_n_0),\n .I5(stg3_dec2init_val_r_i_8_n_0),\n .O(stg3_dec2init_val_r_i_2_n_0));\n LUT4 #(\n .INIT(16'hDDDF)) \n stg3_dec2init_val_r_i_3\n (.I0(\\lim_state[4]_i_3_n_0 ),\n .I1(\\lim_state[2]_i_3_n_0 ),\n .I2(lim_state[4]),\n .I3(lim_state[13]),\n .O(stg3_dec2init_val_r_i_3_n_0));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n stg3_dec2init_val_r_i_4\n (.I0(\\stg3_tap_cnt_reg_n_0_[4] ),\n .I1(\\stg3_tap_cnt_reg_n_0_[5] ),\n .I2(\\stg3_tap_cnt_reg_n_0_[0] ),\n .I3(\\stg3_tap_cnt_reg_n_0_[1] ),\n .I4(\\stg3_tap_cnt_reg_n_0_[3] ),\n .I5(\\stg3_tap_cnt_reg_n_0_[2] ),\n .O(stg3_dec2init_val_r_i_4_n_0));\n LUT3 #(\n .INIT(8'h04)) \n stg3_dec2init_val_r_i_5\n (.I0(mod_sub0_return0__14_carry__0_n_6),\n .I1(mod_sub0_return0__14_carry__0_n_1),\n .I2(mod_sub0_return0__14_carry__0_n_7),\n .O(stg3_dec2init_val_r_i_5_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair375\" *) \n LUT5 #(\n .INIT(32'hB2BB2222)) \n stg3_dec2init_val_r_i_6\n (.I0(\\mmcm_init_lead_reg_n_0_[5] ),\n .I1(\\mmcm_current_reg_n_0_[5] ),\n .I2(\\mmcm_init_lead_reg_n_0_[4] ),\n .I3(\\mmcm_current_reg_n_0_[4] ),\n .I4(stg3_dec2init_val_r_i_9_n_0),\n .O(stg3_dec2init_val_r_i_6_n_0));\n LUT4 #(\n .INIT(16'h0002)) \n stg3_dec2init_val_r_i_7\n (.I0(stg3_dec2init_val_r_i_10_n_0),\n .I1(mod_sub0_return0_carry__0_n_7),\n .I2(mod_sub0_return0_carry__0_n_5),\n .I3(mod_sub0_return0_carry__0_n_6),\n .O(stg3_dec2init_val_r_i_7_n_0));\n LUT4 #(\n .INIT(16'h5557)) \n stg3_dec2init_val_r_i_8\n (.I0(mod_sub0_return0__14_carry_n_4),\n .I1(mod_sub0_return0__14_carry_n_6),\n .I2(mod_sub0_return0__14_carry_n_5),\n .I3(\\mmcm_current_reg[0]_0 ),\n .O(stg3_dec2init_val_r_i_8_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFFB000FFB0)) \n stg3_dec2init_val_r_i_9\n (.I0(\\mmcm_init_lead_reg_n_0_[2] ),\n .I1(\\mmcm_current_reg_n_0_[2] ),\n .I2(stg3_dec2init_val_r_i_12_n_0),\n .I3(\\mmcm_init_lead_reg_n_0_[3] ),\n .I4(\\mmcm_current_reg_n_0_[3] ),\n .I5(stg3_dec2init_val_r_i_13_n_0),\n .O(stg3_dec2init_val_r_i_9_n_0));\n FDRE stg3_dec2init_val_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(stg3_dec2init_val_r_i_1_n_0),\n .Q(stg3_dec2init_val_r),\n .R(rstdiv0_sync_r1_reg_rep__10));\n LUT6 #(\n .INIT(64'hFFFDFFFF30200000)) \n stg3_dec_r_i_1\n (.I0(stg3_dec_r_i_2_n_0),\n .I1(stg3_dec_r_i_3_n_0),\n .I2(stg3_dec_r_i_4_n_0),\n .I3(lim_state[0]),\n .I4(stg3_dec_r_i_5_n_0),\n .I5(stg3_dec_r),\n .O(stg3_dec_r_i_1_n_0));\n LUT4 #(\n .INIT(16'h8000)) \n stg3_dec_r_i_2\n (.I0(\\lim_state[6]_i_10_n_0 ),\n .I1(lim_state[4]),\n .I2(wait_cnt_done),\n .I3(stg3_dec_r),\n .O(stg3_dec_r_i_2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair384\" *) \n LUT2 #(\n .INIT(4'hE)) \n stg3_dec_r_i_3\n (.I0(lim_state[2]),\n .I1(lim_state[1]),\n .O(stg3_dec_r_i_3_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair392\" *) \n LUT3 #(\n .INIT(8'h04)) \n stg3_dec_r_i_4\n (.I0(lim_start_r),\n .I1(lim_start),\n .I2(lim_state[4]),\n .O(stg3_dec_r_i_4_n_0));\n LUT6 #(\n .INIT(64'h0000000000000004)) \n stg3_dec_r_i_5\n (.I0(lim_state[3]),\n .I1(\\lim_state[1]_i_2_n_0 ),\n .I2(lim_state[5]),\n .I3(lim_state[6]),\n .I4(lim_state[7]),\n .I5(lim_state[8]),\n .O(stg3_dec_r_i_5_n_0));\n FDRE stg3_dec_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(stg3_dec_r_i_1_n_0),\n .Q(stg3_dec_r),\n .R(rstdiv0_sync_r1_reg_rep__10));\n LUT6 #(\n .INIT(64'hFFFFFDFF00000020)) \n stg3_dec_req_r_i_1\n (.I0(stg3_dec_req_r_i_2_n_0),\n .I1(lim_state[7]),\n .I2(lim_state[6]),\n .I3(lim_state[9]),\n .I4(lim_state[5]),\n .I5(lim2stg3_dec),\n .O(stg3_dec_req_r_i_1_n_0));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n stg3_dec_req_r_i_2\n (.I0(\\lim_state[0]_i_2_n_0 ),\n .I1(stg3_dec_req_r_i_3_n_0),\n .I2(lim_state[13]),\n .I3(lim_state[12]),\n .I4(lim_state[0]),\n .I5(lim_state[8]),\n .O(stg3_dec_req_r_i_2_n_0));\n LUT2 #(\n .INIT(4'hE)) \n stg3_dec_req_r_i_3\n (.I0(lim_state[11]),\n .I1(lim_state[10]),\n .O(stg3_dec_req_r_i_3_n_0));\n FDRE stg3_dec_req_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(stg3_dec_req_r_i_1_n_0),\n .Q(lim2stg3_dec),\n .R(rstdiv0_sync_r1_reg_rep__10));\n (* SOFT_HLUTNM = \"soft_lutpair371\" *) \n LUT3 #(\n .INIT(8'h69)) \n \\stg3_dec_val[3]_i_1 \n (.I0(\\stg3_dec_val[5]_i_3_n_0 ),\n .I1(\\byte_r_reg[0] ),\n .I2(stg3_init_val[3]),\n .O(stg3_dec_val00_out[3]));\n (* SOFT_HLUTNM = \"soft_lutpair371\" *) \n LUT5 #(\n .INIT(32'h4DB2B24D)) \n \\stg3_dec_val[4]_i_1 \n (.I0(\\stg3_dec_val[5]_i_3_n_0 ),\n .I1(\\byte_r_reg[0] ),\n .I2(stg3_init_val[3]),\n .I3(\\wl_po_fine_cnt_reg[17] ),\n .I4(stg3_init_val[4]),\n .O(stg3_dec_val00_out[4]));\n LUT5 #(\n .INIT(32'hFF00FF71)) \n \\stg3_dec_val[5]_i_1 \n (.I0(\\stg3_inc_val[5]_i_2_n_0 ),\n .I1(stg3_init_val[4]),\n .I2(\\wl_po_fine_cnt_reg[17] ),\n .I3(rstdiv0_sync_r1_reg_rep__20),\n .I4(stg3_init_val[5]),\n .O(\\stg3_dec_val[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hB2FF00B24D00FF4D)) \n \\stg3_dec_val[5]_i_2 \n (.I0(\\stg3_dec_val[5]_i_3_n_0 ),\n .I1(\\byte_r_reg[0] ),\n .I2(stg3_init_val[3]),\n .I3(\\wl_po_fine_cnt_reg[17] ),\n .I4(stg3_init_val[4]),\n .I5(stg3_init_val[5]),\n .O(\\stg3_dec_val[5]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFEE0FFFF0000FEE0)) \n \\stg3_dec_val[5]_i_3 \n (.I0(\\stg3_tap_cnt_reg[2]_0 [0]),\n .I1(\\wl_po_fine_cnt_reg[14] [0]),\n .I2(\\stg3_tap_cnt_reg[2]_0 [1]),\n .I3(\\wl_po_fine_cnt_reg[14] [1]),\n .I4(\\wl_po_fine_cnt_reg[3] ),\n .I5(\\stg3_tap_cnt_reg[2]_0 [2]),\n .O(\\stg3_dec_val[5]_i_3_n_0 ));\n FDRE \\stg3_dec_val_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(D[0]),\n .Q(stg3_dec_val[0]),\n .R(\\stg3_dec_val[5]_i_1_n_0 ));\n FDRE \\stg3_dec_val_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(D[1]),\n .Q(stg3_dec_val[1]),\n .R(\\stg3_dec_val[5]_i_1_n_0 ));\n FDRE \\stg3_dec_val_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(D[2]),\n .Q(stg3_dec_val[2]),\n .R(\\stg3_dec_val[5]_i_1_n_0 ));\n FDRE \\stg3_dec_val_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(stg3_dec_val00_out[3]),\n .Q(stg3_dec_val[3]),\n .R(\\stg3_dec_val[5]_i_1_n_0 ));\n FDRE \\stg3_dec_val_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(stg3_dec_val00_out[4]),\n .Q(stg3_dec_val[4]),\n .R(\\stg3_dec_val[5]_i_1_n_0 ));\n FDRE \\stg3_dec_val_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\stg3_dec_val[5]_i_2_n_0 ),\n .Q(stg3_dec_val[5]),\n .R(\\stg3_dec_val[5]_i_1_n_0 ));\n FDRE stg3_inc2init_val_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(stg3_inc2init_val_r),\n .Q(stg3_inc2init_val_r1),\n .R(rstdiv0_sync_r1_reg_rep__9));\n LUT5 #(\n .INIT(32'hFF0B0008)) \n stg3_inc2init_val_r_i_1\n (.I0(stg3_dec_r),\n .I1(stg3_dec_r_i_2_n_0),\n .I2(lim_state[11]),\n .I3(stg3_inc2init_val_r_i_2_n_0),\n .I4(stg3_inc2init_val_r),\n .O(stg3_inc2init_val_r_i_1_n_0));\n LUT6 #(\n .INIT(64'hEEEEEEEEFFFFFFEF)) \n stg3_inc2init_val_r_i_2\n (.I0(wait_cnt_en_r_i_3_n_0),\n .I1(\\lim_state[2]_i_3_n_0 ),\n .I2(stg3_inc2init_val_r_i_3_n_0),\n .I3(stg2_inc_r_i_2_n_0),\n .I4(lim_state[4]),\n .I5(\\lim_state[1]_i_2_n_0 ),\n .O(stg3_inc2init_val_r_i_2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair386\" *) \n LUT3 #(\n .INIT(8'h20)) \n stg3_inc2init_val_r_i_3\n (.I0(\\lim_state[12]_i_3_n_0 ),\n .I1(stg3_dec2init_val_r),\n .I2(stg3_inc2init_val_r),\n .O(stg3_inc2init_val_r_i_3_n_0));\n FDRE stg3_inc2init_val_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(stg3_inc2init_val_r_i_1_n_0),\n .Q(stg3_inc2init_val_r),\n .R(rstdiv0_sync_r1_reg_rep__10));\n LUT6 #(\n .INIT(64'hFFFFFFF700000020)) \n stg3_inc_req_r_i_1\n (.I0(stg3_dec_req_r_i_2_n_0),\n .I1(lim_state[9]),\n .I2(lim_state[5]),\n .I3(lim_state[7]),\n .I4(lim_state[6]),\n .I5(lim2stg3_inc),\n .O(stg3_inc_req_r_i_1_n_0));\n FDRE stg3_inc_req_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(stg3_inc_req_r_i_1_n_0),\n .Q(lim2stg3_inc),\n .R(rstdiv0_sync_r1_reg_rep__10));\n LUT3 #(\n .INIT(8'hF6)) \n \\stg3_inc_val[0]_i_1 \n (.I0(\\wl_po_fine_cnt_reg[14] [0]),\n .I1(\\stg3_tap_cnt_reg[2]_0 [0]),\n .I2(\\stg3_inc_val[5]_i_3_n_0 ),\n .O(\\stg3_inc_val[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair370\" *) \n LUT5 #(\n .INIT(32'hFFFF9666)) \n \\stg3_inc_val[1]_i_1 \n (.I0(\\stg3_tap_cnt_reg[2]_0 [1]),\n .I1(\\wl_po_fine_cnt_reg[14] [1]),\n .I2(\\stg3_tap_cnt_reg[2]_0 [0]),\n .I3(\\wl_po_fine_cnt_reg[14] [0]),\n .I4(\\stg3_inc_val[5]_i_3_n_0 ),\n .O(\\stg3_inc_val[1]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hFF96)) \n \\stg3_inc_val[2]_i_1 \n (.I0(\\stg3_tap_cnt_reg[2]_0 [2]),\n .I1(\\wl_po_fine_cnt_reg[3] ),\n .I2(\\stg3_inc_val[2]_i_2_n_0 ),\n .I3(\\stg3_inc_val[5]_i_3_n_0 ),\n .O(\\stg3_inc_val[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair370\" *) \n LUT4 #(\n .INIT(16'h077F)) \n \\stg3_inc_val[2]_i_2 \n (.I0(\\stg3_tap_cnt_reg[2]_0 [0]),\n .I1(\\wl_po_fine_cnt_reg[14] [0]),\n .I2(\\wl_po_fine_cnt_reg[14] [1]),\n .I3(\\stg3_tap_cnt_reg[2]_0 [1]),\n .O(\\stg3_inc_val[2]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair381\" *) \n LUT4 #(\n .INIT(16'hFF96)) \n \\stg3_inc_val[3]_i_1 \n (.I0(stg3_init_val[3]),\n .I1(\\byte_r_reg[0] ),\n .I2(\\stg3_inc_val[3]_i_2_n_0 ),\n .I3(\\stg3_inc_val[5]_i_3_n_0 ),\n .O(\\stg3_inc_val[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h077FFFFF0000077F)) \n \\stg3_inc_val[3]_i_2 \n (.I0(\\stg3_tap_cnt_reg[2]_0 [0]),\n .I1(\\wl_po_fine_cnt_reg[14] [0]),\n .I2(\\wl_po_fine_cnt_reg[14] [1]),\n .I3(\\stg3_tap_cnt_reg[2]_0 [1]),\n .I4(\\stg3_tap_cnt_reg[2]_0 [2]),\n .I5(\\wl_po_fine_cnt_reg[3] ),\n .O(\\stg3_inc_val[3]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair374\" *) \n LUT4 #(\n .INIT(16'hFF69)) \n \\stg3_inc_val[4]_i_1 \n (.I0(stg3_init_val[4]),\n .I1(\\wl_po_fine_cnt_reg[17] ),\n .I2(\\stg3_inc_val[5]_i_2_n_0 ),\n .I3(\\stg3_inc_val[5]_i_3_n_0 ),\n .O(\\stg3_inc_val[4]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair374\" *) \n LUT5 #(\n .INIT(32'hFFFF718E)) \n \\stg3_inc_val[5]_i_1 \n (.I0(\\stg3_inc_val[5]_i_2_n_0 ),\n .I1(stg3_init_val[4]),\n .I2(\\wl_po_fine_cnt_reg[17] ),\n .I3(stg3_init_val[5]),\n .I4(\\stg3_inc_val[5]_i_3_n_0 ),\n .O(\\stg3_inc_val[5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair381\" *) \n LUT3 #(\n .INIT(8'h4D)) \n \\stg3_inc_val[5]_i_2 \n (.I0(\\stg3_inc_val[3]_i_2_n_0 ),\n .I1(stg3_init_val[3]),\n .I2(\\byte_r_reg[0] ),\n .O(\\stg3_inc_val[5]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hB2FF00B200000000)) \n \\stg3_inc_val[5]_i_3 \n (.I0(\\stg3_dec_val[5]_i_3_n_0 ),\n .I1(\\byte_r_reg[0] ),\n .I2(stg3_init_val[3]),\n .I3(\\wl_po_fine_cnt_reg[17] ),\n .I4(stg3_init_val[4]),\n .I5(stg3_init_val[5]),\n .O(\\stg3_inc_val[5]_i_3_n_0 ));\n FDRE \\stg3_inc_val_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\stg3_inc_val[0]_i_1_n_0 ),\n .Q(stg3_inc_val[0]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE \\stg3_inc_val_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\stg3_inc_val[1]_i_1_n_0 ),\n .Q(stg3_inc_val[1]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE \\stg3_inc_val_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\stg3_inc_val[2]_i_1_n_0 ),\n .Q(stg3_inc_val[2]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE \\stg3_inc_val_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\stg3_inc_val[3]_i_1_n_0 ),\n .Q(stg3_inc_val[3]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE \\stg3_inc_val_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\stg3_inc_val[4]_i_1_n_0 ),\n .Q(stg3_inc_val[4]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE \\stg3_inc_val_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\stg3_inc_val[5]_i_1_n_0 ),\n .Q(stg3_inc_val[5]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n LUT6 #(\n .INIT(64'hFFFFFFF70000FF00)) \n stg3_init_dec_r_i_1\n (.I0(\\lim_state[6]_i_3_n_0 ),\n .I1(stg3_init_dec_r_i_2_n_0),\n .I2(lim_state[0]),\n .I3(stg3_init_dec_r_i_3_n_0),\n .I4(stg3_init_dec_r_i_4_n_0),\n .I5(stg3_init_dec_r),\n .O(stg3_init_dec_r_i_1_n_0));\n LUT3 #(\n .INIT(8'h02)) \n stg3_init_dec_r_i_2\n (.I0(po_rdy),\n .I1(lim2stg3_dec),\n .I2(lim2stg3_inc),\n .O(stg3_init_dec_r_i_2_n_0));\n LUT3 #(\n .INIT(8'h04)) \n stg3_init_dec_r_i_3\n (.I0(lim_start_r),\n .I1(lim_start),\n .I2(lim_state[9]),\n .O(stg3_init_dec_r_i_3_n_0));\n LUT5 #(\n .INIT(32'hEFEFEFFF)) \n stg3_init_dec_r_i_4\n (.I0(\\lim_state[13]_i_7_n_0 ),\n .I1(lim_state[1]),\n .I2(\\lim_state[6]_i_6_n_0 ),\n .I3(lim_state[9]),\n .I4(lim_state[0]),\n .O(stg3_init_dec_r_i_4_n_0));\n FDRE stg3_init_dec_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(stg3_init_dec_r_i_1_n_0),\n .Q(stg3_init_dec_r),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE \\stg3_init_val_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(oclkdelay_calib_done_r_reg[0]),\n .Q(\\stg3_tap_cnt_reg[2]_0 [0]),\n .R(1'b0));\n FDRE \\stg3_init_val_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(oclkdelay_calib_done_r_reg[1]),\n .Q(\\stg3_tap_cnt_reg[2]_0 [1]),\n .R(1'b0));\n FDRE \\stg3_init_val_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(oclkdelay_calib_done_r_reg[2]),\n .Q(\\stg3_tap_cnt_reg[2]_0 [2]),\n .R(1'b0));\n FDRE \\stg3_init_val_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(oclkdelay_calib_done_r_reg[3]),\n .Q(stg3_init_val[3]),\n .R(1'b0));\n FDRE \\stg3_init_val_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(oclkdelay_calib_done_r_reg[4]),\n .Q(stg3_init_val[4]),\n .R(1'b0));\n FDRE \\stg3_init_val_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(oclkdelay_calib_done_r_reg[5]),\n .Q(stg3_init_val[5]),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hAAAAFBAA)) \n \\stg3_left_lim[5]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__26),\n .I1(stg3_inc2init_val_r),\n .I2(stg3_inc2init_val_r1),\n .I3(lim_start),\n .I4(lim_start_r),\n .O(\\stg3_left_lim[5]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\stg3_left_lim[5]_i_2 \n (.I0(stg3_inc2init_val_r),\n .I1(stg3_inc2init_val_r1),\n .O(stg3_left_lim0));\n FDRE \\stg3_left_lim_reg[0] \n (.C(CLK),\n .CE(stg3_left_lim0),\n .D(\\stg3_tap_cnt_reg_n_0_[0] ),\n .Q(scanning_right_r_reg_0[0]),\n .R(\\stg3_left_lim[5]_i_1_n_0 ));\n FDRE \\stg3_left_lim_reg[1] \n (.C(CLK),\n .CE(stg3_left_lim0),\n .D(\\stg3_tap_cnt_reg_n_0_[1] ),\n .Q(scanning_right_r_reg_0[1]),\n .R(\\stg3_left_lim[5]_i_1_n_0 ));\n FDRE \\stg3_left_lim_reg[2] \n (.C(CLK),\n .CE(stg3_left_lim0),\n .D(\\stg3_tap_cnt_reg_n_0_[2] ),\n .Q(scanning_right_r_reg_0[2]),\n .R(\\stg3_left_lim[5]_i_1_n_0 ));\n FDRE \\stg3_left_lim_reg[3] \n (.C(CLK),\n .CE(stg3_left_lim0),\n .D(\\stg3_tap_cnt_reg_n_0_[3] ),\n .Q(scanning_right_r_reg_0[3]),\n .R(\\stg3_left_lim[5]_i_1_n_0 ));\n FDRE \\stg3_left_lim_reg[4] \n (.C(CLK),\n .CE(stg3_left_lim0),\n .D(\\stg3_tap_cnt_reg_n_0_[4] ),\n .Q(scanning_right_r_reg_0[4]),\n .R(\\stg3_left_lim[5]_i_1_n_0 ));\n FDRE \\stg3_left_lim_reg[5] \n (.C(CLK),\n .CE(stg3_left_lim0),\n .D(\\stg3_tap_cnt_reg_n_0_[5] ),\n .Q(scanning_right_r_reg_0[5]),\n .R(\\stg3_left_lim[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAAAAFBAA)) \n \\stg3_right_lim[5]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__26),\n .I1(stg3_dec2init_val_r),\n .I2(stg3_dec2init_val_r1),\n .I3(lim_start),\n .I4(lim_start_r),\n .O(\\stg3_right_lim[5]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\stg3_right_lim[5]_i_2 \n (.I0(stg3_dec2init_val_r),\n .I1(stg3_dec2init_val_r1),\n .O(stg3_right_lim0));\n FDRE \\stg3_right_lim_reg[0] \n (.C(CLK),\n .CE(stg3_right_lim0),\n .D(\\stg3_tap_cnt_reg_n_0_[0] ),\n .Q(oclkdelay_center_calib_start_r_reg_0[0]),\n .R(\\stg3_right_lim[5]_i_1_n_0 ));\n FDRE \\stg3_right_lim_reg[1] \n (.C(CLK),\n .CE(stg3_right_lim0),\n .D(\\stg3_tap_cnt_reg_n_0_[1] ),\n .Q(oclkdelay_center_calib_start_r_reg_0[1]),\n .R(\\stg3_right_lim[5]_i_1_n_0 ));\n FDRE \\stg3_right_lim_reg[2] \n (.C(CLK),\n .CE(stg3_right_lim0),\n .D(\\stg3_tap_cnt_reg_n_0_[2] ),\n .Q(oclkdelay_center_calib_start_r_reg_0[2]),\n .R(\\stg3_right_lim[5]_i_1_n_0 ));\n FDRE \\stg3_right_lim_reg[3] \n (.C(CLK),\n .CE(stg3_right_lim0),\n .D(\\stg3_tap_cnt_reg_n_0_[3] ),\n .Q(oclkdelay_center_calib_start_r_reg_0[3]),\n .R(\\stg3_right_lim[5]_i_1_n_0 ));\n FDRE \\stg3_right_lim_reg[4] \n (.C(CLK),\n .CE(stg3_right_lim0),\n .D(\\stg3_tap_cnt_reg_n_0_[4] ),\n .Q(oclkdelay_center_calib_start_r_reg_0[4]),\n .R(\\stg3_right_lim[5]_i_1_n_0 ));\n FDRE \\stg3_right_lim_reg[5] \n (.C(CLK),\n .CE(stg3_right_lim0),\n .D(\\stg3_tap_cnt_reg_n_0_[5] ),\n .Q(oclkdelay_center_calib_start_r_reg_0[5]),\n .R(\\stg3_right_lim[5]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h3A)) \n \\stg3_tap_cnt[0]_i_1 \n (.I0(\\stg3_tap_cnt_reg[2]_0 [0]),\n .I1(\\stg3_tap_cnt_reg_n_0_[0] ),\n .I2(rstdiv0_sync_r1_reg_rep__26_0),\n .O(\\stg3_tap_cnt[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h96FF9600)) \n \\stg3_tap_cnt[1]_i_1 \n (.I0(\\stg3_tap_cnt[1]_i_2_n_0 ),\n .I1(\\stg3_tap_cnt_reg_n_0_[1] ),\n .I2(\\stg3_tap_cnt_reg_n_0_[0] ),\n .I3(rstdiv0_sync_r1_reg_rep__26_0),\n .I4(\\stg3_tap_cnt_reg[2]_0 [1]),\n .O(\\stg3_tap_cnt[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFEFFFFFFFF)) \n \\stg3_tap_cnt[1]_i_2 \n (.I0(\\stg2_tap_cnt[1]_i_4_n_0 ),\n .I1(lim_state[12]),\n .I2(\\lim_state[2]_i_3_n_0 ),\n .I3(lim_state[7]),\n .I4(lim_state[6]),\n .I5(lim_state[5]),\n .O(\\stg3_tap_cnt[1]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'h6F60)) \n \\stg3_tap_cnt[2]_i_1 \n (.I0(\\stg3_tap_cnt_reg_n_0_[2] ),\n .I1(\\stg3_tap_cnt[2]_i_2_n_0 ),\n .I2(rstdiv0_sync_r1_reg_rep__26_0),\n .I3(\\stg3_tap_cnt_reg[2]_0 [2]),\n .O(\\stg3_tap_cnt[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h001000000000FFEF)) \n \\stg3_tap_cnt[2]_i_2 \n (.I0(\\lim_state[2]_i_3_n_0 ),\n .I1(lim_state[12]),\n .I2(lim_state[5]),\n .I3(\\stg3_tap_cnt[3]_i_4_n_0 ),\n .I4(\\stg3_tap_cnt_reg_n_0_[0] ),\n .I5(\\stg3_tap_cnt_reg_n_0_[1] ),\n .O(\\stg3_tap_cnt[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hD32CFFFFD32C0000)) \n \\stg3_tap_cnt[3]_i_1 \n (.I0(\\stg3_tap_cnt[3]_i_2_n_0 ),\n .I1(\\stg3_tap_cnt[3]_i_3_n_0 ),\n .I2(\\stg3_tap_cnt_reg_n_0_[2] ),\n .I3(\\stg3_tap_cnt_reg_n_0_[3] ),\n .I4(rstdiv0_sync_r1_reg_rep__26_0),\n .I5(stg3_init_val[3]),\n .O(\\stg3_tap_cnt[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000800)) \n \\stg3_tap_cnt[3]_i_2 \n (.I0(\\stg3_tap_cnt_reg_n_0_[1] ),\n .I1(\\stg3_tap_cnt_reg_n_0_[0] ),\n .I2(\\stg3_tap_cnt[3]_i_4_n_0 ),\n .I3(lim_state[5]),\n .I4(lim_state[12]),\n .I5(\\lim_state[2]_i_3_n_0 ),\n .O(\\stg3_tap_cnt[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h1111111111101111)) \n \\stg3_tap_cnt[3]_i_3 \n (.I0(\\stg3_tap_cnt_reg_n_0_[1] ),\n .I1(\\stg3_tap_cnt_reg_n_0_[0] ),\n .I2(\\lim_state[2]_i_3_n_0 ),\n .I3(lim_state[12]),\n .I4(lim_state[5]),\n .I5(\\stg3_tap_cnt[3]_i_4_n_0 ),\n .O(\\stg3_tap_cnt[3]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n \\stg3_tap_cnt[3]_i_4 \n (.I0(\\lim_state[13]_i_4_n_0 ),\n .I1(lim_state[7]),\n .I2(lim_state[6]),\n .I3(lim_state[4]),\n .I4(lim_state[13]),\n .O(\\stg3_tap_cnt[3]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h56FF5600)) \n \\stg3_tap_cnt[4]_i_1 \n (.I0(\\stg3_tap_cnt_reg_n_0_[4] ),\n .I1(\\stg3_tap_cnt[5]_i_4_n_0 ),\n .I2(\\stg3_tap_cnt[5]_i_5_n_0 ),\n .I3(rstdiv0_sync_r1_reg_rep__26_0),\n .I4(stg3_init_val[4]),\n .O(\\stg3_tap_cnt[4]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h1400FFFF)) \n \\stg3_tap_cnt[5]_i_1 \n (.I0(lim_state[11]),\n .I1(lim_state[5]),\n .I2(lim_state[6]),\n .I3(\\lim_state[9]_i_2_n_0 ),\n .I4(rstdiv0_sync_r1_reg_rep__26_0),\n .O(stg3_tap_cnt0));\n LUT6 #(\n .INIT(64'hD32CFFFFD32C0000)) \n \\stg3_tap_cnt[5]_i_2 \n (.I0(\\stg3_tap_cnt[5]_i_4_n_0 ),\n .I1(\\stg3_tap_cnt[5]_i_5_n_0 ),\n .I2(\\stg3_tap_cnt_reg_n_0_[4] ),\n .I3(\\stg3_tap_cnt_reg_n_0_[5] ),\n .I4(rstdiv0_sync_r1_reg_rep__26_0),\n .I5(stg3_init_val[5]),\n .O(\\stg3_tap_cnt[5]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h00008000)) \n \\stg3_tap_cnt[5]_i_4 \n (.I0(\\stg3_tap_cnt_reg_n_0_[2] ),\n .I1(\\stg3_tap_cnt_reg_n_0_[3] ),\n .I2(\\stg3_tap_cnt_reg_n_0_[0] ),\n .I3(\\stg3_tap_cnt_reg_n_0_[1] ),\n .I4(\\stg3_tap_cnt[1]_i_2_n_0 ),\n .O(\\stg3_tap_cnt[5]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair377\" *) \n LUT5 #(\n .INIT(32'h00000001)) \n \\stg3_tap_cnt[5]_i_5 \n (.I0(\\stg3_tap_cnt_reg_n_0_[3] ),\n .I1(\\stg3_tap_cnt_reg_n_0_[2] ),\n .I2(\\stg3_tap_cnt_reg_n_0_[0] ),\n .I3(\\stg3_tap_cnt_reg_n_0_[1] ),\n .I4(\\stg3_tap_cnt[5]_i_6_n_0 ),\n .O(\\stg3_tap_cnt[5]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair380\" *) \n LUT4 #(\n .INIT(16'h0004)) \n \\stg3_tap_cnt[5]_i_6 \n (.I0(\\stg3_tap_cnt[3]_i_4_n_0 ),\n .I1(lim_state[5]),\n .I2(lim_state[12]),\n .I3(\\lim_state[2]_i_3_n_0 ),\n .O(\\stg3_tap_cnt[5]_i_6_n_0 ));\n FDRE \\stg3_tap_cnt_reg[0] \n (.C(CLK),\n .CE(stg3_tap_cnt0),\n .D(\\stg3_tap_cnt[0]_i_1_n_0 ),\n .Q(\\stg3_tap_cnt_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\stg3_tap_cnt_reg[1] \n (.C(CLK),\n .CE(stg3_tap_cnt0),\n .D(\\stg3_tap_cnt[1]_i_1_n_0 ),\n .Q(\\stg3_tap_cnt_reg_n_0_[1] ),\n .R(1'b0));\n FDRE \\stg3_tap_cnt_reg[2] \n (.C(CLK),\n .CE(stg3_tap_cnt0),\n .D(\\stg3_tap_cnt[2]_i_1_n_0 ),\n .Q(\\stg3_tap_cnt_reg_n_0_[2] ),\n .R(1'b0));\n FDRE \\stg3_tap_cnt_reg[3] \n (.C(CLK),\n .CE(stg3_tap_cnt0),\n .D(\\stg3_tap_cnt[3]_i_1_n_0 ),\n .Q(\\stg3_tap_cnt_reg_n_0_[3] ),\n .R(1'b0));\n FDRE \\stg3_tap_cnt_reg[4] \n (.C(CLK),\n .CE(stg3_tap_cnt0),\n .D(\\stg3_tap_cnt[4]_i_1_n_0 ),\n .Q(\\stg3_tap_cnt_reg_n_0_[4] ),\n .R(1'b0));\n FDRE \\stg3_tap_cnt_reg[5] \n (.C(CLK),\n .CE(stg3_tap_cnt0),\n .D(\\stg3_tap_cnt[5]_i_2_n_0 ),\n .Q(\\stg3_tap_cnt_reg_n_0_[5] ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00008000)) \n wait_cnt_done_i_1\n (.I0(wait_cnt_en_r),\n .I1(wait_cnt_r_reg__0[2]),\n .I2(wait_cnt_r_reg__0[3]),\n .I3(wait_cnt_r_reg__0[1]),\n .I4(wait_cnt_r_reg__0[0]),\n .O(wait_cnt_done_i_1_n_0));\n FDRE wait_cnt_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wait_cnt_done_i_1_n_0),\n .Q(wait_cnt_done),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0000000000010110)) \n wait_cnt_en_r_i_1\n (.I0(wait_cnt_en_r_i_2_n_0),\n .I1(lim_state[0]),\n .I2(lim_state[1]),\n .I3(lim_state[4]),\n .I4(lim_state[2]),\n .I5(lim_state[3]),\n .O(wait_cnt_en_r0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n wait_cnt_en_r_i_2\n (.I0(wait_cnt_en_r_i_3_n_0),\n .I1(lim_state[13]),\n .I2(lim_state[9]),\n .I3(lim_state[12]),\n .I4(lim_state[10]),\n .I5(lim_state[11]),\n .O(wait_cnt_en_r_i_2_n_0));\n LUT4 #(\n .INIT(16'hFFFE)) \n wait_cnt_en_r_i_3\n (.I0(lim_state[5]),\n .I1(lim_state[6]),\n .I2(lim_state[7]),\n .I3(lim_state[8]),\n .O(wait_cnt_en_r_i_3_n_0));\n FDRE wait_cnt_en_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wait_cnt_en_r0),\n .Q(wait_cnt_en_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair394\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\wait_cnt_r[0]_i_1 \n (.I0(wait_cnt_r_reg__0[0]),\n .O(p_0_in[0]));\n (* SOFT_HLUTNM = \"soft_lutpair394\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\wait_cnt_r[1]_i_1 \n (.I0(wait_cnt_r_reg__0[0]),\n .I1(wait_cnt_r_reg__0[1]),\n .O(p_0_in[1]));\n (* SOFT_HLUTNM = \"soft_lutpair385\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\wait_cnt_r[2]_i_1 \n (.I0(wait_cnt_r_reg__0[2]),\n .I1(wait_cnt_r_reg__0[1]),\n .I2(wait_cnt_r_reg__0[0]),\n .O(p_0_in[2]));\n LUT5 #(\n .INIT(32'h0080FFFF)) \n \\wait_cnt_r[3]_i_1 \n (.I0(wait_cnt_r_reg__0[2]),\n .I1(wait_cnt_r_reg__0[3]),\n .I2(wait_cnt_r_reg__0[1]),\n .I3(wait_cnt_r_reg__0[0]),\n .I4(wait_cnt_en_r),\n .O(\\wait_cnt_r[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair385\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\wait_cnt_r[3]_i_2 \n (.I0(wait_cnt_r_reg__0[3]),\n .I1(wait_cnt_r_reg__0[0]),\n .I2(wait_cnt_r_reg__0[1]),\n .I3(wait_cnt_r_reg__0[2]),\n .O(p_0_in[3]));\n FDRE \\wait_cnt_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in[0]),\n .Q(wait_cnt_r_reg__0[0]),\n .R(\\wait_cnt_r[3]_i_1_n_0 ));\n FDRE \\wait_cnt_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in[1]),\n .Q(wait_cnt_r_reg__0[1]),\n .R(\\wait_cnt_r[3]_i_1_n_0 ));\n FDRE \\wait_cnt_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in[2]),\n .Q(wait_cnt_r_reg__0[2]),\n .R(\\wait_cnt_r[3]_i_1_n_0 ));\n FDRE \\wait_cnt_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in[3]),\n .Q(wait_cnt_r_reg__0[3]),\n .R(\\wait_cnt_r[3]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFF7F0C00)) \n write_request_r_i_1\n (.I0(done_r_reg_1),\n .I1(write_request_r_i_2_n_0),\n .I2(lim_state[3]),\n .I3(lim_state[2]),\n .I4(lim2init_write_request),\n .O(write_request_r_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair372\" *) \n LUT5 #(\n .INIT(32'h00000002)) \n write_request_r_i_2\n (.I0(\\lim_state[4]_i_3_n_0 ),\n .I1(lim_state[4]),\n .I2(lim_state[13]),\n .I3(lim_state[1]),\n .I4(lim_state[0]),\n .O(write_request_r_i_2_n_0));\n FDRE write_request_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(write_request_r_i_1_n_0),\n .Q(lim2init_write_request),\n .R(rstdiv0_sync_r1_reg_rep__10));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_ddr_phy_ocd_mux\n (po_rdy,\n po_stg23_incdec,\n \\po_wait_r_reg[3]_0 ,\n D_po_sel_fine_oclk_delay125_out,\n \\po_counter_read_val_reg[8] ,\n \\po_counter_read_val_reg[8]_0 ,\n \\po_counter_read_val_reg[8]_1 ,\n \\po_counter_read_val_reg[8]_2 ,\n \\po_counter_read_val_reg[8]_3 ,\n \\po_counter_read_val_reg[8]_4 ,\n \\po_counter_read_val_reg[8]_5 ,\n po_stg23_sel_r_reg_0,\n CLK,\n stg3_inc_req_r_reg,\n stg3_dec_req_r_reg,\n Q,\n calib_in_common,\n \\calib_zero_inputs_reg[1] ,\n rstdiv0_sync_r1_reg_rep__25,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n ck_addr_cmd_delay_done,\n oclkdelay_calib_done_r_reg,\n mpr_rdlvl_done_r_reg,\n \\gen_byte_sel_div1.calib_in_common_reg_0 ,\n \\gen_byte_sel_div1.calib_in_common_reg_1 ,\n \\gen_byte_sel_div1.calib_in_common_reg_2 ,\n stg2_dec_req_r_reg,\n setup_po,\n rstdiv0_sync_r1_reg_rep__10);\n output po_rdy;\n output po_stg23_incdec;\n output \\po_wait_r_reg[3]_0 ;\n output D_po_sel_fine_oclk_delay125_out;\n output \\po_counter_read_val_reg[8] ;\n output \\po_counter_read_val_reg[8]_0 ;\n output \\po_counter_read_val_reg[8]_1 ;\n output \\po_counter_read_val_reg[8]_2 ;\n output \\po_counter_read_val_reg[8]_3 ;\n output \\po_counter_read_val_reg[8]_4 ;\n output \\po_counter_read_val_reg[8]_5 ;\n output po_stg23_sel_r_reg_0;\n input CLK;\n input stg3_inc_req_r_reg;\n input stg3_dec_req_r_reg;\n input [1:0]Q;\n input calib_in_common;\n input [1:0]\\calib_zero_inputs_reg[1] ;\n input rstdiv0_sync_r1_reg_rep__25;\n input \\gen_byte_sel_div1.calib_in_common_reg ;\n input ck_addr_cmd_delay_done;\n input oclkdelay_calib_done_r_reg;\n input mpr_rdlvl_done_r_reg;\n input \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n input \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n input \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n input stg2_dec_req_r_reg;\n input setup_po;\n input rstdiv0_sync_r1_reg_rep__10;\n\n wire CLK;\n wire D_po_sel_fine_oclk_delay125_out;\n wire [1:0]Q;\n wire calib_in_common;\n wire [1:0]\\calib_zero_inputs_reg[1] ;\n wire ck_addr_cmd_delay_done;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n wire mpr_rdlvl_done_r_reg;\n wire oclkdelay_calib_done_r_reg;\n wire \\po_counter_read_val_reg[8] ;\n wire \\po_counter_read_val_reg[8]_0 ;\n wire \\po_counter_read_val_reg[8]_1 ;\n wire \\po_counter_read_val_reg[8]_2 ;\n wire \\po_counter_read_val_reg[8]_3 ;\n wire \\po_counter_read_val_reg[8]_4 ;\n wire \\po_counter_read_val_reg[8]_5 ;\n wire po_en_stg23_r_i_1_n_0;\n wire po_rdy;\n wire po_rdy_ns;\n wire [0:0]po_sel_stg2stg3;\n wire [1:0]po_setup_r;\n wire po_setup_r0;\n wire \\po_setup_r[0]_i_1_n_0 ;\n wire \\po_setup_r[1]_i_1_n_0 ;\n wire po_stg23_incdec;\n wire po_stg23_sel;\n wire po_stg23_sel_r_reg_0;\n wire [3:0]po_wait_r;\n wire \\po_wait_r[0]_i_1_n_0 ;\n wire \\po_wait_r[1]_i_1_n_0 ;\n wire \\po_wait_r[2]_i_1_n_0 ;\n wire \\po_wait_r[3]_i_1_n_0 ;\n wire \\po_wait_r_reg[3]_0 ;\n wire rstdiv0_sync_r1_reg_rep__10;\n wire rstdiv0_sync_r1_reg_rep__25;\n wire setup_po;\n wire stg2_dec_req_r_reg;\n wire stg3_dec_req_r_reg;\n wire stg3_inc_req_r_reg;\n\n LUT6 #(\n .INIT(64'h0000000000800000)) \n phaser_out_i_4__3\n (.I0(\\gen_byte_sel_div1.calib_in_common_reg ),\n .I1(ck_addr_cmd_delay_done),\n .I2(po_stg23_sel),\n .I3(oclkdelay_calib_done_r_reg),\n .I4(mpr_rdlvl_done_r_reg),\n .I5(\\calib_zero_inputs_reg[1] [0]),\n .O(\\po_counter_read_val_reg[8]_2 ));\n LUT6 #(\n .INIT(64'h0000000000800000)) \n phaser_out_i_4__4\n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .I1(ck_addr_cmd_delay_done),\n .I2(po_stg23_sel),\n .I3(oclkdelay_calib_done_r_reg),\n .I4(mpr_rdlvl_done_r_reg),\n .I5(\\calib_zero_inputs_reg[1] [0]),\n .O(\\po_counter_read_val_reg[8]_3 ));\n LUT6 #(\n .INIT(64'h0000000000800000)) \n phaser_out_i_4__5\n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .I1(ck_addr_cmd_delay_done),\n .I2(po_stg23_sel),\n .I3(oclkdelay_calib_done_r_reg),\n .I4(mpr_rdlvl_done_r_reg),\n .I5(\\calib_zero_inputs_reg[1] [0]),\n .O(\\po_counter_read_val_reg[8]_4 ));\n LUT6 #(\n .INIT(64'h0000000000800000)) \n phaser_out_i_4__6\n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_2 ),\n .I1(ck_addr_cmd_delay_done),\n .I2(po_stg23_sel),\n .I3(oclkdelay_calib_done_r_reg),\n .I4(mpr_rdlvl_done_r_reg),\n .I5(\\calib_zero_inputs_reg[1] [0]),\n .O(\\po_counter_read_val_reg[8]_5 ));\n (* SOFT_HLUTNM = \"soft_lutpair395\" *) \n LUT5 #(\n .INIT(32'h00000800)) \n phaser_out_i_5\n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(calib_in_common),\n .I3(po_sel_stg2stg3),\n .I4(\\calib_zero_inputs_reg[1] [1]),\n .O(D_po_sel_fine_oclk_delay125_out));\n (* SOFT_HLUTNM = \"soft_lutpair395\" *) \n LUT5 #(\n .INIT(32'h00000100)) \n phaser_out_i_5__0\n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(calib_in_common),\n .I3(po_sel_stg2stg3),\n .I4(\\calib_zero_inputs_reg[1] [1]),\n .O(\\po_counter_read_val_reg[8] ));\n (* SOFT_HLUTNM = \"soft_lutpair396\" *) \n LUT5 #(\n .INIT(32'h00000400)) \n phaser_out_i_5__1\n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(calib_in_common),\n .I3(po_sel_stg2stg3),\n .I4(\\calib_zero_inputs_reg[1] [1]),\n .O(\\po_counter_read_val_reg[8]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair396\" *) \n LUT5 #(\n .INIT(32'h00000400)) \n phaser_out_i_5__2\n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(calib_in_common),\n .I3(po_sel_stg2stg3),\n .I4(\\calib_zero_inputs_reg[1] [1]),\n .O(\\po_counter_read_val_reg[8]_1 ));\n LUT4 #(\n .INIT(16'h0800)) \n phaser_out_i_6\n (.I0(ck_addr_cmd_delay_done),\n .I1(po_stg23_sel),\n .I2(oclkdelay_calib_done_r_reg),\n .I3(mpr_rdlvl_done_r_reg),\n .O(po_sel_stg2stg3));\n (* SOFT_HLUTNM = \"soft_lutpair397\" *) \n LUT3 #(\n .INIT(8'h04)) \n po_en_stg23_r_i_1\n (.I0(rstdiv0_sync_r1_reg_rep__25),\n .I1(po_setup_r[0]),\n .I2(po_setup_r[1]),\n .O(po_en_stg23_r_i_1_n_0));\n FDRE po_en_stg23_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(po_en_stg23_r_i_1_n_0),\n .Q(\\po_wait_r_reg[3]_0 ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0000000000000001)) \n po_rdy_r_i_1\n (.I0(setup_po),\n .I1(\\po_wait_r[3]_i_1_n_0 ),\n .I2(po_setup_r0),\n .I3(\\po_wait_r[0]_i_1_n_0 ),\n .I4(\\po_wait_r[1]_i_1_n_0 ),\n .I5(\\po_wait_r[2]_i_1_n_0 ),\n .O(po_rdy_ns));\n (* SOFT_HLUTNM = \"soft_lutpair397\" *) \n LUT2 #(\n .INIT(4'hE)) \n po_rdy_r_i_3\n (.I0(po_setup_r[0]),\n .I1(po_setup_r[1]),\n .O(po_setup_r0));\n FDRE po_rdy_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(po_rdy_ns),\n .Q(po_rdy),\n .R(1'b0));\n LUT3 #(\n .INIT(8'hF2)) \n \\po_setup_r[0]_i_1 \n (.I0(po_setup_r[1]),\n .I1(po_setup_r[0]),\n .I2(setup_po),\n .O(\\po_setup_r[0]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hF8)) \n \\po_setup_r[1]_i_1 \n (.I0(po_setup_r[1]),\n .I1(po_setup_r[0]),\n .I2(setup_po),\n .O(\\po_setup_r[1]_i_1_n_0 ));\n FDRE \\po_setup_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_setup_r[0]_i_1_n_0 ),\n .Q(po_setup_r[0]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE \\po_setup_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_setup_r[1]_i_1_n_0 ),\n .Q(po_setup_r[1]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE po_stg23_incdec_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(stg3_inc_req_r_reg),\n .Q(po_stg23_incdec),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h5555555100000000)) \n po_stg23_sel_r_i_2\n (.I0(stg2_dec_req_r_reg),\n .I1(po_wait_r[0]),\n .I2(po_wait_r[1]),\n .I3(po_wait_r[3]),\n .I4(po_wait_r[2]),\n .I5(po_stg23_sel),\n .O(po_stg23_sel_r_reg_0));\n FDRE po_stg23_sel_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(stg3_dec_req_r_reg),\n .Q(po_stg23_sel),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000000000FE)) \n \\po_wait_r[0]_i_1 \n (.I0(po_wait_r[1]),\n .I1(po_wait_r[2]),\n .I2(po_wait_r[3]),\n .I3(rstdiv0_sync_r1_reg_rep__25),\n .I4(po_wait_r[0]),\n .I5(\\po_wait_r_reg[3]_0 ),\n .O(\\po_wait_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h5445544554455444)) \n \\po_wait_r[1]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__25),\n .I1(\\po_wait_r_reg[3]_0 ),\n .I2(po_wait_r[0]),\n .I3(po_wait_r[1]),\n .I4(po_wait_r[2]),\n .I5(po_wait_r[3]),\n .O(\\po_wait_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h5554444555544444)) \n \\po_wait_r[2]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__25),\n .I1(\\po_wait_r_reg[3]_0 ),\n .I2(po_wait_r[0]),\n .I3(po_wait_r[1]),\n .I4(po_wait_r[2]),\n .I5(po_wait_r[3]),\n .O(\\po_wait_r[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h5555555444444444)) \n \\po_wait_r[3]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__25),\n .I1(\\po_wait_r_reg[3]_0 ),\n .I2(po_wait_r[2]),\n .I3(po_wait_r[0]),\n .I4(po_wait_r[1]),\n .I5(po_wait_r[3]),\n .O(\\po_wait_r[3]_i_1_n_0 ));\n FDRE \\po_wait_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_wait_r[0]_i_1_n_0 ),\n .Q(po_wait_r[0]),\n .R(1'b0));\n FDRE \\po_wait_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_wait_r[1]_i_1_n_0 ),\n .Q(po_wait_r[1]),\n .R(1'b0));\n FDRE \\po_wait_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_wait_r[2]_i_1_n_0 ),\n .Q(po_wait_r[2]),\n .R(1'b0));\n FDRE \\po_wait_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_wait_r[3]_i_1_n_0 ),\n .Q(po_wait_r[3]),\n .R(1'b0));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_ddr_phy_ocd_po_cntlr\n (O,\n ocal_last_byte_done_reg,\n oclk_center_write_resume,\n complex_ocal_num_samples_done_r,\n \\sm_r_reg[3]_0 ,\n oclkdelay_center_calib_start_r_reg_0,\n scanning_right,\n S,\n Q,\n po_stg23_incdec_r_reg,\n setup_po,\n \\stg2_r_reg[0]_0 ,\n \\two_r_reg[1]_0 ,\n E,\n o2f_r_reg,\n f2z_r_reg,\n \\stg2_target_r_reg[8]_0 ,\n po_stg23_incdec_r_reg_0,\n \\stg3_init_val_reg[5] ,\n \\stg3_init_val_reg[3] ,\n \\stg3_init_val_reg[4] ,\n \\stg3_init_val_reg[2] ,\n \\stg3_init_val_reg[1] ,\n \\stg3_init_val_reg[0] ,\n \\rise_trail_r_reg[5] ,\n \\run_ends_r_reg[1] ,\n \\sm_r_reg[0]_0 ,\n D,\n samp_done_ns8_out,\n ninety_offsets,\n use_noise_window,\n \\init_state_r_reg[0] ,\n poc_backup_r_reg_0,\n edge_aligned_r_reg,\n \\stg3_init_val_reg[4]_0 ,\n \\stg3_init_val_reg[2]_0 ,\n rstdiv0_sync_r1_reg_rep__10,\n CLK,\n dec_po_ns,\n inc_po_ns,\n rstdiv0_sync_r1_reg_rep__9,\n \\wl_po_fine_cnt_reg[14] ,\n \\stg3_r_reg[0]_0 ,\n f2o_r_reg,\n f2o_r_reg_0,\n rstdiv0_sync_r1_reg_rep__26,\n lim2stg3_inc,\n po_stg23_incdec,\n ocd_cntlr2stg2_dec_r,\n scanning_right_r_reg_0,\n scan_right_r_reg,\n samp_done,\n rd_active_r2,\n poc_backup_r_reg_1,\n done_r_reg,\n o2f_ns1_out,\n o2f_r_reg_0,\n f2z_ns5_out,\n f2z_r_reg_0,\n rstdiv0_sync_r1_reg_rep__20,\n lim2stg3_dec,\n lim2stg2_dec,\n \\byte_r_reg[0] ,\n \\wl_po_fine_cnt_reg[3] ,\n \\wl_po_fine_cnt_reg[17] ,\n \\wl_po_fine_cnt_reg[18] ,\n \\byte_r_reg[0]_0 ,\n \\byte_r_reg[1] ,\n oclkdelay_calib_done_r_reg,\n lim2poc_ktap_right,\n lim2poc_rdy,\n po_rdy,\n lim2stg2_inc,\n edge_aligned_r_reg_0,\n \\sm_r_reg[0]_1 ,\n reset_scan,\n rstdiv0_sync_r1_reg_rep__26_0,\n samp_done_r_reg,\n rstdiv0_sync_r1_reg_rep__25,\n wrlvl_final_mux,\n oclkdelay_int_ref_req_reg,\n prech_req_posedge_r_reg,\n oclkdelay_calib_done_r_reg_0,\n \\run_ends_r_reg[1]_0 ,\n \\run_ends_r_reg[0] ,\n \\po_counter_read_val_reg[5] ,\n \\byte_r_reg[0]_1 ,\n \\byte_r_reg[1]_0 ,\n \\byte_r_reg[0]_2 ,\n \\byte_r_reg[0]_3 ,\n \\wl_po_fine_cnt_reg[23] );\n output [3:0]O;\n output ocal_last_byte_done_reg;\n output oclk_center_write_resume;\n output complex_ocal_num_samples_done_r;\n output \\sm_r_reg[3]_0 ;\n output oclkdelay_center_calib_start_r_reg_0;\n output scanning_right;\n output [0:0]S;\n output [5:0]Q;\n output po_stg23_incdec_r_reg;\n output setup_po;\n output [0:0]\\stg2_r_reg[0]_0 ;\n output \\two_r_reg[1]_0 ;\n output [0:0]E;\n output o2f_r_reg;\n output f2z_r_reg;\n output [2:0]\\stg2_target_r_reg[8]_0 ;\n output po_stg23_incdec_r_reg_0;\n output \\stg3_init_val_reg[5] ;\n output [0:0]\\stg3_init_val_reg[3] ;\n output \\stg3_init_val_reg[4] ;\n output \\stg3_init_val_reg[2] ;\n output \\stg3_init_val_reg[1] ;\n output \\stg3_init_val_reg[0] ;\n output \\rise_trail_r_reg[5] ;\n output \\run_ends_r_reg[1] ;\n output \\sm_r_reg[0]_0 ;\n output [5:0]D;\n output samp_done_ns8_out;\n output [1:0]ninety_offsets;\n output use_noise_window;\n output \\init_state_r_reg[0] ;\n output poc_backup_r_reg_0;\n output edge_aligned_r_reg;\n output \\stg3_init_val_reg[4]_0 ;\n output \\stg3_init_val_reg[2]_0 ;\n input rstdiv0_sync_r1_reg_rep__10;\n input CLK;\n input dec_po_ns;\n input inc_po_ns;\n input rstdiv0_sync_r1_reg_rep__9;\n input [1:0]\\wl_po_fine_cnt_reg[14] ;\n input \\stg3_r_reg[0]_0 ;\n input f2o_r_reg;\n input f2o_r_reg_0;\n input rstdiv0_sync_r1_reg_rep__26;\n input lim2stg3_inc;\n input po_stg23_incdec;\n input ocd_cntlr2stg2_dec_r;\n input scanning_right_r_reg_0;\n input scan_right_r_reg;\n input samp_done;\n input rd_active_r2;\n input poc_backup_r_reg_1;\n input done_r_reg;\n input o2f_ns1_out;\n input o2f_r_reg_0;\n input f2z_ns5_out;\n input f2z_r_reg_0;\n input rstdiv0_sync_r1_reg_rep__20;\n input lim2stg3_dec;\n input lim2stg2_dec;\n input \\byte_r_reg[0] ;\n input \\wl_po_fine_cnt_reg[3] ;\n input \\wl_po_fine_cnt_reg[17] ;\n input \\wl_po_fine_cnt_reg[18] ;\n input \\byte_r_reg[0]_0 ;\n input \\byte_r_reg[1] ;\n input oclkdelay_calib_done_r_reg;\n input lim2poc_ktap_right;\n input lim2poc_rdy;\n input po_rdy;\n input lim2stg2_inc;\n input edge_aligned_r_reg_0;\n input \\sm_r_reg[0]_1 ;\n input reset_scan;\n input rstdiv0_sync_r1_reg_rep__26_0;\n input samp_done_r_reg;\n input rstdiv0_sync_r1_reg_rep__25;\n input wrlvl_final_mux;\n input oclkdelay_int_ref_req_reg;\n input prech_req_posedge_r_reg;\n input oclkdelay_calib_done_r_reg_0;\n input \\run_ends_r_reg[1]_0 ;\n input \\run_ends_r_reg[0] ;\n input [5:0]\\po_counter_read_val_reg[5] ;\n input \\byte_r_reg[0]_1 ;\n input \\byte_r_reg[1]_0 ;\n input \\byte_r_reg[0]_2 ;\n input \\byte_r_reg[0]_3 ;\n input [7:0]\\wl_po_fine_cnt_reg[23] ;\n\n wire [8:0]A;\n wire CLK;\n wire [5:0]D;\n wire [0:0]E;\n wire [3:0]O;\n wire [5:0]Q;\n wire [0:0]S;\n wire \\byte_r_reg[0] ;\n wire \\byte_r_reg[0]_0 ;\n wire \\byte_r_reg[0]_1 ;\n wire \\byte_r_reg[0]_2 ;\n wire \\byte_r_reg[0]_3 ;\n wire \\byte_r_reg[1] ;\n wire \\byte_r_reg[1]_0 ;\n wire cmplx_samples_done_r_i_2_n_0;\n wire cmplx_samples_done_r_i_3_n_0;\n wire complex_ocal_num_samples_done_r;\n wire dec_po_ns;\n wire dec_po_r;\n wire done_r_reg;\n wire edge_aligned_r_reg;\n wire edge_aligned_r_reg_0;\n wire f2o_r_reg;\n wire f2o_r_reg_0;\n wire f2z_ns5_out;\n wire f2z_r_reg;\n wire f2z_r_reg_0;\n wire inc_po_ns;\n wire inc_po_r;\n wire \\init_state_r_reg[0] ;\n wire lim2poc_ktap_right;\n wire lim2poc_rdy;\n wire lim2stg2_dec;\n wire lim2stg2_inc;\n wire lim2stg3_dec;\n wire lim2stg3_inc;\n wire [1:0]ninety_offsets;\n wire [1:0]ninety_offsets_final_r;\n wire ninety_offsets_ns;\n wire \\ninety_offsets_r[0]_i_1_n_0 ;\n wire \\ninety_offsets_r[1]_i_1_n_0 ;\n wire \\ninety_offsets_r[1]_i_3_n_0 ;\n wire \\ninety_offsets_r[1]_i_4_n_0 ;\n wire o2f_ns1_out;\n wire o2f_r_reg;\n wire o2f_r_reg_0;\n wire ocal_last_byte_done_reg;\n wire ocd2stg3_dec;\n wire ocd_cntlr2stg2_dec_r;\n wire ocd_edge_detect_rdy;\n wire ocd_edge_detect_rdy_r_i_1_n_0;\n wire ocd_ktap_left_r_i_2_n_0;\n wire ocd_ktap_left_r_i_3_n_0;\n wire ocd_ktap_left_r_i_4_n_0;\n wire ocd_ktap_right;\n wire ocd_ktap_right_r_i_1_n_0;\n wire oclk_calib_resume_r_i_5_n_0;\n wire oclk_center_write_resume;\n wire oclk_center_write_resume_r_i_2_n_0;\n wire oclk_center_write_resume_r_i_3_n_0;\n wire oclk_center_write_resume_r_i_4_n_0;\n wire oclk_center_write_resume_r_i_5_n_0;\n wire oclkdelay_calib_done_r_reg;\n wire oclkdelay_calib_done_r_reg_0;\n wire oclkdelay_center_calib_done_r_i_1_n_0;\n wire oclkdelay_center_calib_done_r_i_2_n_0;\n wire oclkdelay_center_calib_done_r_i_3_n_0;\n wire oclkdelay_center_calib_done_r_i_4_n_0;\n wire oclkdelay_center_calib_start_r_i_1_n_0;\n wire oclkdelay_center_calib_start_r_reg_0;\n wire oclkdelay_int_ref_req_reg;\n wire [8:1]out;\n wire [5:0]p_0_in;\n wire p_0_in0_carry__0_i_1_n_0;\n wire p_0_in0_carry__0_i_2_n_0;\n wire p_0_in0_carry__0_i_3_n_0;\n wire p_0_in0_carry__0_i_4_n_0;\n wire p_0_in0_carry__0_n_2;\n wire p_0_in0_carry__0_n_3;\n wire p_0_in0_carry__0_n_5;\n wire p_0_in0_carry__0_n_6;\n wire p_0_in0_carry__0_n_7;\n wire p_0_in0_carry_i_10_n_0;\n wire p_0_in0_carry_i_10_n_1;\n wire p_0_in0_carry_i_10_n_2;\n wire p_0_in0_carry_i_10_n_3;\n wire p_0_in0_carry_i_10_n_4;\n wire p_0_in0_carry_i_10_n_5;\n wire p_0_in0_carry_i_10_n_6;\n wire p_0_in0_carry_i_11_n_3;\n wire p_0_in0_carry_i_11_n_6;\n wire p_0_in0_carry_i_11_n_7;\n wire p_0_in0_carry_i_12_n_3;\n wire p_0_in0_carry_i_13_n_0;\n wire p_0_in0_carry_i_14_n_0;\n wire p_0_in0_carry_i_15_n_0;\n wire p_0_in0_carry_i_16_n_0;\n wire p_0_in0_carry_i_17_n_0;\n wire p_0_in0_carry_i_18_n_0;\n wire p_0_in0_carry_i_19_n_0;\n wire p_0_in0_carry_i_1_n_0;\n wire p_0_in0_carry_i_20_n_0;\n wire p_0_in0_carry_i_21_n_0;\n wire p_0_in0_carry_i_22_n_0;\n wire p_0_in0_carry_i_23_n_0;\n wire p_0_in0_carry_i_24_n_0;\n wire p_0_in0_carry_i_2_n_0;\n wire p_0_in0_carry_i_3_n_0;\n wire p_0_in0_carry_i_4_n_0;\n wire p_0_in0_carry_i_5_n_0;\n wire p_0_in0_carry_i_6_n_0;\n wire p_0_in0_carry_i_7_n_0;\n wire p_0_in0_carry_i_8_n_0;\n wire p_0_in0_carry_i_8_n_1;\n wire p_0_in0_carry_i_8_n_2;\n wire p_0_in0_carry_i_8_n_3;\n wire p_0_in0_carry_i_9_n_0;\n wire p_0_in0_carry_n_0;\n wire p_0_in0_carry_n_1;\n wire p_0_in0_carry_n_2;\n wire p_0_in0_carry_n_3;\n wire p_1_in;\n wire p_55_in;\n wire p_58_in;\n wire p_63_in;\n wire [5:0]po_counter_read_val_r;\n wire [5:0]\\po_counter_read_val_reg[5] ;\n wire po_done_ns;\n wire po_done_r;\n wire po_done_r_i_1_n_0;\n wire po_rdy;\n wire po_rdy_r_i_5_n_0;\n wire po_rdy_r_i_6_n_0;\n wire po_rdy_r_i_7_n_0;\n wire po_stg23_incdec;\n wire po_stg23_incdec_r_i_10_n_0;\n wire po_stg23_incdec_r_i_2_n_0;\n wire po_stg23_incdec_r_i_3_n_0;\n wire po_stg23_incdec_r_i_4_n_0;\n wire po_stg23_incdec_r_i_5_n_0;\n wire po_stg23_incdec_r_i_6_n_0;\n wire po_stg23_incdec_r_i_7_n_0;\n wire po_stg23_incdec_r_i_8_n_0;\n wire po_stg23_incdec_r_i_9_n_0;\n wire po_stg23_incdec_r_reg;\n wire po_stg23_incdec_r_reg_0;\n wire poc_backup_r;\n wire poc_backup_r_i_1__0_n_0;\n wire poc_backup_r_i_2__0_n_0;\n wire poc_backup_r_i_3_n_0;\n wire poc_backup_r_i_4_n_0;\n wire poc_backup_r_i_5_n_0;\n wire poc_backup_r_reg_0;\n wire poc_backup_r_reg_1;\n wire prech_req_posedge_r_reg;\n wire rd_active_r2;\n wire reset_scan;\n wire [9:5]resume_wait_ns0;\n wire [10:0]resume_wait_r;\n wire \\resume_wait_r[0]_i_1_n_0 ;\n wire \\resume_wait_r[10]_i_1_n_0 ;\n wire \\resume_wait_r[10]_i_2_n_0 ;\n wire \\resume_wait_r[10]_i_3_n_0 ;\n wire \\resume_wait_r[10]_i_4_n_0 ;\n wire \\resume_wait_r[1]_i_1_n_0 ;\n wire \\resume_wait_r[2]_i_1_n_0 ;\n wire \\resume_wait_r[2]_i_2_n_0 ;\n wire \\resume_wait_r[3]_i_1_n_0 ;\n wire \\resume_wait_r[4]_i_1_n_0 ;\n wire \\resume_wait_r[4]_i_2_n_0 ;\n wire \\resume_wait_r[7]_i_2_n_0 ;\n wire \\resume_wait_r[9]_i_1_n_0 ;\n wire \\resume_wait_r[9]_i_4_n_0 ;\n wire \\resume_wait_r[9]_i_5_n_0 ;\n wire \\resume_wait_r[9]_i_6_n_0 ;\n wire \\resume_wait_r[9]_i_7_n_0 ;\n wire \\resume_wait_r[9]_i_8_n_0 ;\n wire \\rise_trail_r_reg[5] ;\n wire rstdiv0_sync_r1_reg_rep__10;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__25;\n wire rstdiv0_sync_r1_reg_rep__26;\n wire rstdiv0_sync_r1_reg_rep__26_0;\n wire rstdiv0_sync_r1_reg_rep__9;\n wire \\run_ends_r_reg[0] ;\n wire \\run_ends_r_reg[1] ;\n wire \\run_ends_r_reg[1]_0 ;\n wire samp_done;\n wire samp_done_ns8_out;\n wire samp_done_r_reg;\n wire scan_right_r_reg;\n wire scanning_right;\n wire scanning_right_r_i_1_n_0;\n wire scanning_right_r_i_3_n_0;\n wire scanning_right_r_reg_0;\n wire setup_po;\n wire \\simp_stg3_final_r_reg_n_0_[0] ;\n wire \\simp_stg3_final_r_reg_n_0_[10] ;\n wire \\simp_stg3_final_r_reg_n_0_[11] ;\n wire \\simp_stg3_final_r_reg_n_0_[12] ;\n wire \\simp_stg3_final_r_reg_n_0_[13] ;\n wire \\simp_stg3_final_r_reg_n_0_[14] ;\n wire \\simp_stg3_final_r_reg_n_0_[15] ;\n wire \\simp_stg3_final_r_reg_n_0_[17] ;\n wire \\simp_stg3_final_r_reg_n_0_[18] ;\n wire \\simp_stg3_final_r_reg_n_0_[19] ;\n wire \\simp_stg3_final_r_reg_n_0_[1] ;\n wire \\simp_stg3_final_r_reg_n_0_[20] ;\n wire \\simp_stg3_final_r_reg_n_0_[21] ;\n wire \\simp_stg3_final_r_reg_n_0_[22] ;\n wire \\simp_stg3_final_r_reg_n_0_[23] ;\n wire \\simp_stg3_final_r_reg_n_0_[3] ;\n wire \\simp_stg3_final_r_reg_n_0_[4] ;\n wire \\simp_stg3_final_r_reg_n_0_[5] ;\n wire \\simp_stg3_final_r_reg_n_0_[6] ;\n wire \\simp_stg3_final_r_reg_n_0_[7] ;\n wire \\simp_stg3_final_r_reg_n_0_[8] ;\n wire \\simp_stg3_final_r_reg_n_0_[9] ;\n wire sm_ns;\n wire [3:0]sm_r;\n wire \\sm_r[0]_i_1_n_0 ;\n wire \\sm_r[0]_i_2__0_n_0 ;\n wire \\sm_r[0]_i_3_n_0 ;\n wire \\sm_r[1]_i_1_n_0 ;\n wire \\sm_r[1]_i_2_n_0 ;\n wire \\sm_r[2]_i_1_n_0 ;\n wire \\sm_r[2]_i_2_n_0 ;\n wire \\sm_r[3]_i_10_n_0 ;\n wire \\sm_r[3]_i_2_n_0 ;\n wire \\sm_r[3]_i_3_n_0 ;\n wire \\sm_r[3]_i_4_n_0 ;\n wire \\sm_r[3]_i_6_n_0 ;\n wire \\sm_r[3]_i_7_n_0 ;\n wire \\sm_r[3]_i_8_n_0 ;\n wire \\sm_r[3]_i_9_n_0 ;\n wire \\sm_r_reg[0]_0 ;\n wire \\sm_r_reg[0]_1 ;\n wire \\sm_r_reg[3]_0 ;\n wire [5:0]stg2_final_r;\n wire \\stg2_final_r[0]_i_1_n_0 ;\n wire \\stg2_final_r[1]_i_1_n_0 ;\n wire \\stg2_final_r[2]_i_1_n_0 ;\n wire \\stg2_final_r[3]_i_1_n_0 ;\n wire \\stg2_final_r[4]_i_1_n_0 ;\n wire \\stg2_final_r[5]_i_1_n_0 ;\n wire [8:0]stg2_ns;\n wire stg2_ns0_carry__0_i_1_n_0;\n wire stg2_ns0_carry__0_i_2_n_0;\n wire stg2_ns0_carry__0_i_3_n_0;\n wire stg2_ns0_carry__0_i_4_n_0;\n wire stg2_ns0_carry__0_n_1;\n wire stg2_ns0_carry__0_n_2;\n wire stg2_ns0_carry__0_n_3;\n wire stg2_ns0_carry_i_1_n_0;\n wire stg2_ns0_carry_i_2_n_0;\n wire stg2_ns0_carry_i_3_n_0;\n wire stg2_ns0_carry_i_4_n_0;\n wire stg2_ns0_carry_n_0;\n wire stg2_ns0_carry_n_1;\n wire stg2_ns0_carry_n_2;\n wire stg2_ns0_carry_n_3;\n wire \\stg2_r[8]_i_1_n_0 ;\n wire \\stg2_r[8]_i_3_n_0 ;\n wire [0:0]\\stg2_r_reg[0]_0 ;\n wire [1:1]stg2_target_ns;\n wire [2:0]\\stg2_target_r_reg[8]_0 ;\n wire \\stg2_target_r_reg_n_0_[0] ;\n wire \\stg2_target_r_reg_n_0_[1] ;\n wire \\stg2_target_r_reg_n_0_[2] ;\n wire \\stg2_target_r_reg_n_0_[3] ;\n wire \\stg2_target_r_reg_n_0_[4] ;\n wire \\stg2_target_r_reg_n_0_[5] ;\n wire \\stg2_target_r_reg_n_0_[6] ;\n wire \\stg2_target_r_reg_n_0_[7] ;\n wire \\stg3_init_val[3]_i_2_n_0 ;\n wire \\stg3_init_val_reg[0] ;\n wire \\stg3_init_val_reg[1] ;\n wire \\stg3_init_val_reg[2] ;\n wire \\stg3_init_val_reg[2]_0 ;\n wire [0:0]\\stg3_init_val_reg[3] ;\n wire \\stg3_init_val_reg[4] ;\n wire \\stg3_init_val_reg[4]_0 ;\n wire \\stg3_init_val_reg[5] ;\n wire [5:0]stg3_ns;\n wire \\stg3_r[5]_i_10_n_0 ;\n wire \\stg3_r[5]_i_11_n_0 ;\n wire \\stg3_r[5]_i_12_n_0 ;\n wire \\stg3_r[5]_i_1_n_0 ;\n wire \\stg3_r[5]_i_4_n_0 ;\n wire \\stg3_r[5]_i_5_n_0 ;\n wire \\stg3_r[5]_i_6_n_0 ;\n wire \\stg3_r[5]_i_7_n_0 ;\n wire \\stg3_r[5]_i_9_n_0 ;\n wire \\stg3_r_reg[0]_0 ;\n wire [1:0]two_r;\n wire \\two_r[0]_i_1_n_0 ;\n wire \\two_r[1]_i_1_n_0 ;\n wire \\two_r[1]_i_2_n_0 ;\n wire \\two_r_reg[1]_0 ;\n wire up_r;\n wire up_r_i_1_n_0;\n wire use_noise_window;\n wire [1:0]\\wl_po_fine_cnt_reg[14] ;\n wire \\wl_po_fine_cnt_reg[17] ;\n wire \\wl_po_fine_cnt_reg[18] ;\n wire [7:0]\\wl_po_fine_cnt_reg[23] ;\n wire \\wl_po_fine_cnt_reg[3] ;\n wire wrlvl_final_mux;\n wire [3:2]NLW_p_0_in0_carry__0_CO_UNCONNECTED;\n wire [3:3]NLW_p_0_in0_carry__0_O_UNCONNECTED;\n wire [3:1]NLW_p_0_in0_carry_i_11_CO_UNCONNECTED;\n wire [3:2]NLW_p_0_in0_carry_i_11_O_UNCONNECTED;\n wire [3:1]NLW_p_0_in0_carry_i_12_CO_UNCONNECTED;\n wire [3:2]NLW_p_0_in0_carry_i_12_O_UNCONNECTED;\n wire [0:0]NLW_p_0_in0_carry_i_8_O_UNCONNECTED;\n wire [3:3]NLW_stg2_ns0_carry__0_CO_UNCONNECTED;\n\n LUT3 #(\n .INIT(8'h04)) \n cmplx_samples_done_r_i_1\n (.I0(rstdiv0_sync_r1_reg_rep__26),\n .I1(complex_ocal_num_samples_done_r),\n .I2(cmplx_samples_done_r_i_2_n_0),\n .O(p_58_in));\n LUT5 #(\n .INIT(32'h0008AAAA)) \n cmplx_samples_done_r_i_2\n (.I0(oclk_calib_resume_r_i_5_n_0),\n .I1(cmplx_samples_done_r_i_3_n_0),\n .I2(inc_po_r),\n .I3(dec_po_r),\n .I4(sm_r[0]),\n .O(cmplx_samples_done_r_i_2_n_0));\n LUT3 #(\n .INIT(8'h08)) \n cmplx_samples_done_r_i_3\n (.I0(po_done_r),\n .I1(\\stg2_r_reg[0]_0 ),\n .I2(E),\n .O(cmplx_samples_done_r_i_3_n_0));\n FDRE cmplx_samples_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(p_58_in),\n .Q(complex_ocal_num_samples_done_r),\n .R(1'b0));\n FDRE dec_po_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(dec_po_ns),\n .Q(dec_po_r),\n .R(1'b0));\n LUT2 #(\n .INIT(4'hE)) \n done_r_i_2__0\n (.I0(ocd_edge_detect_rdy),\n .I1(lim2poc_rdy),\n .O(\\run_ends_r_reg[1] ));\n LUT2 #(\n .INIT(4'hE)) \n edge_aligned_r_i_4\n (.I0(\\sm_r_reg[3]_0 ),\n .I1(\\rise_trail_r_reg[5] ),\n .O(edge_aligned_r_reg));\n (* SOFT_HLUTNM = \"soft_lutpair421\" *) \n LUT3 #(\n .INIT(8'hB8)) \n f2z_r_i_1\n (.I0(scanning_right),\n .I1(f2z_ns5_out),\n .I2(f2z_r_reg_0),\n .O(f2z_r_reg));\n LUT2 #(\n .INIT(4'h2)) \n i___15_i_1__0\n (.I0(ninety_offsets[0]),\n .I1(ninety_offsets[1]),\n .O(use_noise_window));\n (* SOFT_HLUTNM = \"soft_lutpair416\" *) \n LUT2 #(\n .INIT(4'hE)) \n i___7_i_2\n (.I0(ocd_ktap_right),\n .I1(lim2poc_ktap_right),\n .O(\\rise_trail_r_reg[5] ));\n FDRE inc_po_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(inc_po_ns),\n .Q(inc_po_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n \\init_state_r[5]_i_55 \n (.I0(oclkdelay_center_calib_start_r_reg_0),\n .I1(wrlvl_final_mux),\n .I2(oclkdelay_int_ref_req_reg),\n .I3(prech_req_posedge_r_reg),\n .I4(oclkdelay_calib_done_r_reg_0),\n .O(\\init_state_r_reg[0] ));\n FDRE \\ninety_offsets_final_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(f2o_r_reg_0),\n .Q(ninety_offsets_final_r[0]),\n .R(1'b0));\n FDRE \\ninety_offsets_final_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(f2o_r_reg),\n .Q(ninety_offsets_final_r[1]),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hE0FFEF00)) \n \\ninety_offsets_r[0]_i_1 \n (.I0(ninety_offsets_final_r[1]),\n .I1(ninety_offsets_final_r[0]),\n .I2(sm_r[0]),\n .I3(ninety_offsets_ns),\n .I4(ninety_offsets[0]),\n .O(\\ninety_offsets_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair409\" *) \n LUT4 #(\n .INIT(16'h4F80)) \n \\ninety_offsets_r[1]_i_1 \n (.I0(ninety_offsets[0]),\n .I1(sm_r[2]),\n .I2(ninety_offsets_ns),\n .I3(ninety_offsets[1]),\n .O(\\ninety_offsets_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF00000040)) \n \\ninety_offsets_r[1]_i_2 \n (.I0(sm_r[2]),\n .I1(sm_r[0]),\n .I2(\\stg2_r_reg[0]_0 ),\n .I3(sm_r[3]),\n .I4(rstdiv0_sync_r1_reg_rep__26),\n .I5(\\ninety_offsets_r[1]_i_3_n_0 ),\n .O(ninety_offsets_ns));\n LUT6 #(\n .INIT(64'h0000000001000000)) \n \\ninety_offsets_r[1]_i_3 \n (.I0(sm_r[3]),\n .I1(rstdiv0_sync_r1_reg_rep__26),\n .I2(\\ninety_offsets_r[1]_i_4_n_0 ),\n .I3(oclk_center_write_resume_r_i_5_n_0),\n .I4(done_r_reg),\n .I5(E),\n .O(\\ninety_offsets_r[1]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair404\" *) \n LUT5 #(\n .INIT(32'hFFFFFFFB)) \n \\ninety_offsets_r[1]_i_4 \n (.I0(\\stg2_r_reg[0]_0 ),\n .I1(sm_r[2]),\n .I2(sm_r[0]),\n .I3(\\sm_r_reg[3]_0 ),\n .I4(ocd_ktap_right),\n .O(\\ninety_offsets_r[1]_i_4_n_0 ));\n FDRE \\ninety_offsets_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ninety_offsets_r[0]_i_1_n_0 ),\n .Q(ninety_offsets[0]),\n .R(1'b0));\n FDRE \\ninety_offsets_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\ninety_offsets_r[1]_i_1_n_0 ),\n .Q(ninety_offsets[1]),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair421\" *) \n LUT3 #(\n .INIT(8'hB8)) \n o2f_r_i_1\n (.I0(scanning_right),\n .I1(o2f_ns1_out),\n .I2(o2f_r_reg_0),\n .O(o2f_r_reg));\n (* SOFT_HLUTNM = \"soft_lutpair406\" *) \n LUT5 #(\n .INIT(32'hFDFF0100)) \n ocd_edge_detect_rdy_r_i_1\n (.I0(done_r_reg),\n .I1(E),\n .I2(sm_r[3]),\n .I3(\\sm_r[3]_i_6_n_0 ),\n .I4(ocd_edge_detect_rdy),\n .O(ocd_edge_detect_rdy_r_i_1_n_0));\n FDRE ocd_edge_detect_rdy_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(ocd_edge_detect_rdy_r_i_1_n_0),\n .Q(ocd_edge_detect_rdy),\n .R(rstdiv0_sync_r1_reg_rep__10));\n LUT6 #(\n .INIT(64'h00000000EEEEEEE0)) \n ocd_ktap_left_r_i_1\n (.I0(ocd_ktap_left_r_i_2_n_0),\n .I1(\\sm_r_reg[3]_0 ),\n .I2(sm_r[0]),\n .I3(\\stg2_r_reg[0]_0 ),\n .I4(ocd_ktap_left_r_i_3_n_0),\n .I5(rstdiv0_sync_r1_reg_rep__20),\n .O(p_55_in));\n LUT6 #(\n .INIT(64'h2000000000000000)) \n ocd_ktap_left_r_i_2\n (.I0(scanning_right_r_reg_0),\n .I1(\\stg2_r_reg[0]_0 ),\n .I2(rd_active_r2),\n .I3(samp_done),\n .I4(sm_r[0]),\n .I5(ocd_ktap_left_r_i_4_n_0),\n .O(ocd_ktap_left_r_i_2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair411\" *) \n LUT4 #(\n .INIT(16'hFFDF)) \n ocd_ktap_left_r_i_3\n (.I0(sm_r[2]),\n .I1(sm_r[3]),\n .I2(done_r_reg),\n .I3(E),\n .O(ocd_ktap_left_r_i_3_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair409\" *) \n LUT2 #(\n .INIT(4'h1)) \n ocd_ktap_left_r_i_4\n (.I0(sm_r[3]),\n .I1(sm_r[2]),\n .O(ocd_ktap_left_r_i_4_n_0));\n FDRE ocd_ktap_left_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(p_55_in),\n .Q(\\sm_r_reg[3]_0 ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFFF0200FDFF0000)) \n ocd_ktap_right_r_i_1\n (.I0(\\sm_r[3]_i_6_n_0 ),\n .I1(sm_r[3]),\n .I2(E),\n .I3(done_r_reg),\n .I4(ocd_ktap_right),\n .I5(\\sm_r_reg[3]_0 ),\n .O(ocd_ktap_right_r_i_1_n_0));\n FDRE ocd_ktap_right_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(ocd_ktap_right_r_i_1_n_0),\n .Q(ocd_ktap_right),\n .R(rstdiv0_sync_r1_reg_rep__9));\n LUT4 #(\n .INIT(16'h0002)) \n oclk_calib_resume_r_i_2\n (.I0(oclk_calib_resume_r_i_5_n_0),\n .I1(rstdiv0_sync_r1_reg_rep__26),\n .I2(\\sm_r_reg[0]_1 ),\n .I3(sm_r[0]),\n .O(samp_done_ns8_out));\n LUT6 #(\n .INIT(64'h00000000000000A3)) \n oclk_calib_resume_r_i_5\n (.I0(po_done_r),\n .I1(reset_scan),\n .I2(\\stg2_r_reg[0]_0 ),\n .I3(sm_r[3]),\n .I4(sm_r[2]),\n .I5(E),\n .O(oclk_calib_resume_r_i_5_n_0));\n LUT6 #(\n .INIT(64'hFFFF008000000000)) \n oclk_center_write_resume_r_i_1\n (.I0(oclk_center_write_resume_r_i_2_n_0),\n .I1(\\stg2_r_reg[0]_0 ),\n .I2(po_done_r),\n .I3(sm_r[3]),\n .I4(oclk_center_write_resume),\n .I5(oclk_center_write_resume_r_i_3_n_0),\n .O(p_63_in));\n LUT4 #(\n .INIT(16'hAAAB)) \n oclk_center_write_resume_r_i_2\n (.I0(sm_r[2]),\n .I1(dec_po_r),\n .I2(inc_po_r),\n .I3(E),\n .O(oclk_center_write_resume_r_i_2_n_0));\n LUT5 #(\n .INIT(32'h55554044)) \n oclk_center_write_resume_r_i_3\n (.I0(rstdiv0_sync_r1_reg_rep__26),\n .I1(oclk_center_write_resume),\n .I2(ocd_ktap_left_r_i_3_n_0),\n .I3(oclk_center_write_resume_r_i_4_n_0),\n .I4(sm_r[0]),\n .O(oclk_center_write_resume_r_i_3_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair407\" *) \n LUT4 #(\n .INIT(16'h00F1)) \n oclk_center_write_resume_r_i_4\n (.I0(ocd_ktap_right),\n .I1(oclk_center_write_resume_r_i_5_n_0),\n .I2(\\sm_r_reg[3]_0 ),\n .I3(\\stg2_r_reg[0]_0 ),\n .O(oclk_center_write_resume_r_i_4_n_0));\n LUT6 #(\n .INIT(64'h0880888888880880)) \n oclk_center_write_resume_r_i_5\n (.I0(edge_aligned_r_reg_0),\n .I1(ocd_edge_detect_rdy),\n .I2(ninety_offsets[0]),\n .I3(ninety_offsets_final_r[0]),\n .I4(ninety_offsets[1]),\n .I5(ninety_offsets_final_r[1]),\n .O(oclk_center_write_resume_r_i_5_n_0));\n FDRE oclk_center_write_resume_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(p_63_in),\n .Q(oclk_center_write_resume),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n oclkdelay_center_calib_done_r_i_1\n (.I0(oclkdelay_center_calib_done_r_i_2_n_0),\n .I1(resume_wait_r[3]),\n .I2(resume_wait_r[4]),\n .I3(resume_wait_r[5]),\n .I4(oclkdelay_center_calib_done_r_i_3_n_0),\n .I5(oclkdelay_center_calib_done_r_i_4_n_0),\n .O(oclkdelay_center_calib_done_r_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair405\" *) \n LUT5 #(\n .INIT(32'h00000004)) \n oclkdelay_center_calib_done_r_i_2\n (.I0(resume_wait_r[1]),\n .I1(resume_wait_r[0]),\n .I2(resume_wait_r[2]),\n .I3(poc_backup_r),\n .I4(resume_wait_r[10]),\n .O(oclkdelay_center_calib_done_r_i_2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair408\" *) \n LUT4 #(\n .INIT(16'hFFEF)) \n oclkdelay_center_calib_done_r_i_3\n (.I0(sm_r[2]),\n .I1(\\stg2_r_reg[0]_0 ),\n .I2(sm_r[3]),\n .I3(sm_r[0]),\n .O(oclkdelay_center_calib_done_r_i_3_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair401\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n oclkdelay_center_calib_done_r_i_4\n (.I0(resume_wait_r[8]),\n .I1(resume_wait_r[7]),\n .I2(resume_wait_r[9]),\n .I3(resume_wait_r[6]),\n .O(oclkdelay_center_calib_done_r_i_4_n_0));\n FDRE oclkdelay_center_calib_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(oclkdelay_center_calib_done_r_i_1_n_0),\n .Q(ocal_last_byte_done_reg),\n .R(rstdiv0_sync_r1_reg_rep__10));\n LUT6 #(\n .INIT(64'hEE44EFFFEE44E000)) \n oclkdelay_center_calib_start_r_i_1\n (.I0(sm_r[0]),\n .I1(poc_backup_r),\n .I2(\\sm_r[3]_i_3_n_0 ),\n .I3(scanning_right_r_reg_0),\n .I4(oclkdelay_center_calib_done_r_i_1_n_0),\n .I5(oclkdelay_center_calib_start_r_reg_0),\n .O(oclkdelay_center_calib_start_r_i_1_n_0));\n FDRE oclkdelay_center_calib_start_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(oclkdelay_center_calib_start_r_i_1_n_0),\n .Q(oclkdelay_center_calib_start_r_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__9));\n CARRY4 p_0_in0_carry\n (.CI(1'b0),\n .CO({p_0_in0_carry_n_0,p_0_in0_carry_n_1,p_0_in0_carry_n_2,p_0_in0_carry_n_3}),\n .CYINIT(1'b0),\n .DI({p_0_in0_carry_i_1_n_0,p_0_in0_carry_i_2_n_0,p_0_in0_carry_i_3_n_0,1'b0}),\n .O(O),\n .S({p_0_in0_carry_i_4_n_0,p_0_in0_carry_i_5_n_0,p_0_in0_carry_i_6_n_0,p_0_in0_carry_i_7_n_0}));\n CARRY4 p_0_in0_carry__0\n (.CI(p_0_in0_carry_n_0),\n .CO({NLW_p_0_in0_carry__0_CO_UNCONNECTED[3:2],p_0_in0_carry__0_n_2,p_0_in0_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,p_0_in0_carry__0_i_1_n_0,p_0_in0_carry__0_i_2_n_0}),\n .O({NLW_p_0_in0_carry__0_O_UNCONNECTED[3],p_0_in0_carry__0_n_5,p_0_in0_carry__0_n_6,p_0_in0_carry__0_n_7}),\n .S({1'b0,1'b1,p_0_in0_carry__0_i_3_n_0,p_0_in0_carry__0_i_4_n_0}));\n LUT2 #(\n .INIT(4'hB)) \n p_0_in0_carry__0_i_1\n (.I0(p_0_in0_carry_i_9_n_0),\n .I1(p_0_in[5]),\n .O(p_0_in0_carry__0_i_1_n_0));\n LUT4 #(\n .INIT(16'hF404)) \n p_0_in0_carry__0_i_2\n (.I0(p_0_in[3]),\n .I1(p_0_in[4]),\n .I2(p_0_in0_carry_i_9_n_0),\n .I3(p_0_in0_carry_i_11_n_7),\n .O(p_0_in0_carry__0_i_2_n_0));\n LUT4 #(\n .INIT(16'h553F)) \n p_0_in0_carry__0_i_3\n (.I0(p_0_in0_carry_i_11_n_6),\n .I1(p_0_in[4]),\n .I2(p_0_in[5]),\n .I3(p_0_in0_carry_i_9_n_0),\n .O(p_0_in0_carry__0_i_3_n_0));\n LUT6 #(\n .INIT(64'hAAC355C3AA0F550F)) \n p_0_in0_carry__0_i_4\n (.I0(p_0_in0_carry_i_11_n_7),\n .I1(p_0_in[3]),\n .I2(p_0_in[5]),\n .I3(p_0_in0_carry_i_9_n_0),\n .I4(p_0_in0_carry_i_11_n_6),\n .I5(p_0_in[4]),\n .O(p_0_in0_carry__0_i_4_n_0));\n LUT4 #(\n .INIT(16'hF404)) \n p_0_in0_carry_i_1\n (.I0(p_0_in[2]),\n .I1(p_0_in[3]),\n .I2(p_0_in0_carry_i_9_n_0),\n .I3(p_0_in0_carry_i_10_n_4),\n .O(p_0_in0_carry_i_1_n_0));\n CARRY4 p_0_in0_carry_i_10\n (.CI(1'b0),\n .CO({p_0_in0_carry_i_10_n_0,p_0_in0_carry_i_10_n_1,p_0_in0_carry_i_10_n_2,p_0_in0_carry_i_10_n_3}),\n .CYINIT(1'b1),\n .DI({1'b1,1'b1,1'b0,1'b0}),\n .O({p_0_in0_carry_i_10_n_4,p_0_in0_carry_i_10_n_5,p_0_in0_carry_i_10_n_6,p_0_in[0]}),\n .S({p_0_in0_carry_i_17_n_0,p_0_in0_carry_i_18_n_0,p_0_in0_carry_i_19_n_0,p_0_in0_carry_i_20_n_0}));\n CARRY4 p_0_in0_carry_i_11\n (.CI(p_0_in0_carry_i_10_n_0),\n .CO({NLW_p_0_in0_carry_i_11_CO_UNCONNECTED[3:1],p_0_in0_carry_i_11_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b1}),\n .O({NLW_p_0_in0_carry_i_11_O_UNCONNECTED[3:2],p_0_in0_carry_i_11_n_6,p_0_in0_carry_i_11_n_7}),\n .S({1'b0,1'b0,p_0_in0_carry_i_21_n_0,p_0_in0_carry_i_22_n_0}));\n CARRY4 p_0_in0_carry_i_12\n (.CI(p_0_in0_carry_i_8_n_0),\n .CO({NLW_p_0_in0_carry_i_12_CO_UNCONNECTED[3:1],p_0_in0_carry_i_12_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,Q[4]}),\n .O({NLW_p_0_in0_carry_i_12_O_UNCONNECTED[3:2],p_0_in[5:4]}),\n .S({1'b0,1'b0,p_0_in0_carry_i_23_n_0,p_0_in0_carry_i_24_n_0}));\n LUT1 #(\n .INIT(2'h2)) \n p_0_in0_carry_i_13\n (.I0(Q[3]),\n .O(p_0_in0_carry_i_13_n_0));\n LUT1 #(\n .INIT(2'h2)) \n p_0_in0_carry_i_14\n (.I0(Q[2]),\n .O(p_0_in0_carry_i_14_n_0));\n LUT1 #(\n .INIT(2'h1)) \n p_0_in0_carry_i_15\n (.I0(Q[1]),\n .O(p_0_in0_carry_i_15_n_0));\n LUT1 #(\n .INIT(2'h1)) \n p_0_in0_carry_i_16\n (.I0(Q[0]),\n .O(p_0_in0_carry_i_16_n_0));\n LUT1 #(\n .INIT(2'h2)) \n p_0_in0_carry_i_17\n (.I0(Q[3]),\n .O(p_0_in0_carry_i_17_n_0));\n LUT1 #(\n .INIT(2'h2)) \n p_0_in0_carry_i_18\n (.I0(Q[2]),\n .O(p_0_in0_carry_i_18_n_0));\n LUT1 #(\n .INIT(2'h1)) \n p_0_in0_carry_i_19\n (.I0(Q[1]),\n .O(p_0_in0_carry_i_19_n_0));\n LUT4 #(\n .INIT(16'hF404)) \n p_0_in0_carry_i_2\n (.I0(p_0_in[1]),\n .I1(p_0_in[2]),\n .I2(p_0_in0_carry_i_9_n_0),\n .I3(p_0_in0_carry_i_10_n_5),\n .O(p_0_in0_carry_i_2_n_0));\n LUT1 #(\n .INIT(2'h1)) \n p_0_in0_carry_i_20\n (.I0(Q[0]),\n .O(p_0_in0_carry_i_20_n_0));\n LUT1 #(\n .INIT(2'h1)) \n p_0_in0_carry_i_21\n (.I0(Q[5]),\n .O(p_0_in0_carry_i_21_n_0));\n LUT1 #(\n .INIT(2'h2)) \n p_0_in0_carry_i_22\n (.I0(Q[4]),\n .O(p_0_in0_carry_i_22_n_0));\n LUT1 #(\n .INIT(2'h1)) \n p_0_in0_carry_i_23\n (.I0(Q[5]),\n .O(p_0_in0_carry_i_23_n_0));\n LUT1 #(\n .INIT(2'h2)) \n p_0_in0_carry_i_24\n (.I0(Q[4]),\n .O(p_0_in0_carry_i_24_n_0));\n LUT3 #(\n .INIT(8'hEF)) \n p_0_in0_carry_i_3\n (.I0(p_0_in[1]),\n .I1(p_0_in0_carry_i_9_n_0),\n .I2(p_0_in[0]),\n .O(p_0_in0_carry_i_3_n_0));\n LUT6 #(\n .INIT(64'hA5CCA533A500A5FF)) \n p_0_in0_carry_i_4\n (.I0(p_0_in0_carry_i_10_n_4),\n .I1(p_0_in[2]),\n .I2(p_0_in0_carry_i_11_n_7),\n .I3(p_0_in0_carry_i_9_n_0),\n .I4(p_0_in[4]),\n .I5(p_0_in[3]),\n .O(p_0_in0_carry_i_4_n_0));\n LUT6 #(\n .INIT(64'hAA55C3C3AA550F0F)) \n p_0_in0_carry_i_5\n (.I0(p_0_in0_carry_i_10_n_5),\n .I1(p_0_in[1]),\n .I2(p_0_in[3]),\n .I3(p_0_in0_carry_i_10_n_4),\n .I4(p_0_in0_carry_i_9_n_0),\n .I5(p_0_in[2]),\n .O(p_0_in0_carry_i_5_n_0));\n LUT5 #(\n .INIT(32'hF033F066)) \n p_0_in0_carry_i_6\n (.I0(p_0_in[0]),\n .I1(p_0_in[2]),\n .I2(p_0_in0_carry_i_10_n_5),\n .I3(p_0_in0_carry_i_9_n_0),\n .I4(p_0_in[1]),\n .O(p_0_in0_carry_i_6_n_0));\n LUT4 #(\n .INIT(16'hF606)) \n p_0_in0_carry_i_7\n (.I0(p_0_in[0]),\n .I1(p_0_in[1]),\n .I2(p_0_in0_carry_i_9_n_0),\n .I3(p_0_in0_carry_i_10_n_6),\n .O(p_0_in0_carry_i_7_n_0));\n CARRY4 p_0_in0_carry_i_8\n (.CI(1'b0),\n .CO({p_0_in0_carry_i_8_n_0,p_0_in0_carry_i_8_n_1,p_0_in0_carry_i_8_n_2,p_0_in0_carry_i_8_n_3}),\n .CYINIT(1'b1),\n .DI(Q[3:0]),\n .O({p_0_in[3:1],NLW_p_0_in0_carry_i_8_O_UNCONNECTED[0]}),\n .S({p_0_in0_carry_i_13_n_0,p_0_in0_carry_i_14_n_0,p_0_in0_carry_i_15_n_0,p_0_in0_carry_i_16_n_0}));\n LUT6 #(\n .INIT(64'h0155555555555555)) \n p_0_in0_carry_i_9\n (.I0(Q[5]),\n .I1(Q[0]),\n .I2(Q[1]),\n .I3(Q[2]),\n .I4(Q[4]),\n .I5(Q[3]),\n .O(p_0_in0_carry_i_9_n_0));\n FDRE \\po_counter_read_val_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_counter_read_val_reg[5] [0]),\n .Q(po_counter_read_val_r[0]),\n .R(1'b0));\n FDRE \\po_counter_read_val_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_counter_read_val_reg[5] [1]),\n .Q(po_counter_read_val_r[1]),\n .R(1'b0));\n FDRE \\po_counter_read_val_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_counter_read_val_reg[5] [2]),\n .Q(po_counter_read_val_r[2]),\n .R(1'b0));\n FDRE \\po_counter_read_val_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_counter_read_val_reg[5] [3]),\n .Q(po_counter_read_val_r[3]),\n .R(1'b0));\n FDRE \\po_counter_read_val_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_counter_read_val_reg[5] [4]),\n .Q(po_counter_read_val_r[4]),\n .R(1'b0));\n FDRE \\po_counter_read_val_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_counter_read_val_reg[5] [5]),\n .Q(po_counter_read_val_r[5]),\n .R(1'b0));\n LUT3 #(\n .INIT(8'hDC)) \n po_done_r_i_1\n (.I0(\\two_r_reg[1]_0 ),\n .I1(po_done_ns),\n .I2(po_done_r),\n .O(po_done_r_i_1_n_0));\n LUT6 #(\n .INIT(64'hAAAAAAAABAFFAAAA)) \n po_done_r_i_2\n (.I0(rstdiv0_sync_r1_reg_rep__26),\n .I1(two_r[0]),\n .I2(two_r[1]),\n .I3(\\two_r[1]_i_2_n_0 ),\n .I4(po_rdy),\n .I5(po_done_r),\n .O(po_done_ns));\n FDRE po_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(po_done_r_i_1_n_0),\n .Q(po_done_r),\n .R(1'b0));\n LUT4 #(\n .INIT(16'hFFFE)) \n po_rdy_r_i_2\n (.I0(po_stg23_incdec_r_reg_0),\n .I1(lim2stg3_inc),\n .I2(lim2stg3_dec),\n .I3(\\two_r_reg[1]_0 ),\n .O(setup_po));\n LUT6 #(\n .INIT(64'hFFFFFFFFEEEFEEEE)) \n po_rdy_r_i_4\n (.I0(po_stg23_incdec_r_i_2_n_0),\n .I1(lim2stg2_dec),\n .I2(up_r),\n .I3(po_rdy_r_i_5_n_0),\n .I4(po_rdy_r_i_6_n_0),\n .I5(po_rdy_r_i_7_n_0),\n .O(po_stg23_incdec_r_reg_0));\n LUT6 #(\n .INIT(64'h0000000000000001)) \n po_rdy_r_i_5\n (.I0(A[2]),\n .I1(A[5]),\n .I2(A[4]),\n .I3(A[0]),\n .I4(A[3]),\n .I5(A[1]),\n .O(po_rdy_r_i_5_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair412\" *) \n LUT4 #(\n .INIT(16'h0002)) \n po_rdy_r_i_6\n (.I0(\\stg2_r[8]_i_3_n_0 ),\n .I1(A[7]),\n .I2(A[8]),\n .I3(A[6]),\n .O(po_rdy_r_i_6_n_0));\n LUT6 #(\n .INIT(64'h4545444544444444)) \n po_rdy_r_i_7\n (.I0(rstdiv0_sync_r1_reg_rep__26),\n .I1(ocd_cntlr2stg2_dec_r),\n .I2(\\sm_r[3]_i_9_n_0 ),\n .I3(stg2_final_r[5]),\n .I4(po_counter_read_val_r[5]),\n .I5(po_stg23_incdec_r_i_4_n_0),\n .O(po_rdy_r_i_7_n_0));\n LUT6 #(\n .INIT(64'h5455555554555455)) \n po_stg23_incdec_r_i_1\n (.I0(rstdiv0_sync_r1_reg_rep__26),\n .I1(po_stg23_incdec_r_i_2_n_0),\n .I2(lim2stg3_inc),\n .I3(\\stg3_r[5]_i_6_n_0 ),\n .I4(setup_po),\n .I5(po_stg23_incdec),\n .O(po_stg23_incdec_r_reg));\n LUT6 #(\n .INIT(64'h7FFFFFFFFFFFFFFF)) \n po_stg23_incdec_r_i_10\n (.I0(A[4]),\n .I1(A[2]),\n .I2(A[5]),\n .I3(A[1]),\n .I4(A[0]),\n .I5(A[3]),\n .O(po_stg23_incdec_r_i_10_n_0));\n LUT5 #(\n .INIT(32'hFFFFFF10)) \n po_stg23_incdec_r_i_2\n (.I0(rstdiv0_sync_r1_reg_rep__26),\n .I1(po_stg23_incdec_r_i_3_n_0),\n .I2(po_stg23_incdec_r_i_4_n_0),\n .I3(po_stg23_incdec_r_i_5_n_0),\n .I4(lim2stg2_inc),\n .O(po_stg23_incdec_r_i_2_n_0));\n LUT6 #(\n .INIT(64'hD5DD0000D5DDD5DD)) \n po_stg23_incdec_r_i_3\n (.I0(po_stg23_incdec_r_i_6_n_0),\n .I1(po_stg23_incdec_r_i_7_n_0),\n .I2(po_stg23_incdec_r_i_8_n_0),\n .I3(po_stg23_incdec_r_i_9_n_0),\n .I4(po_counter_read_val_r[5]),\n .I5(stg2_final_r[5]),\n .O(po_stg23_incdec_r_i_3_n_0));\n LUT4 #(\n .INIT(16'h0002)) \n po_stg23_incdec_r_i_4\n (.I0(po_rdy),\n .I1(E),\n .I2(oclkdelay_center_calib_done_r_i_3_n_0),\n .I3(poc_backup_r),\n .O(po_stg23_incdec_r_i_4_n_0));\n LUT6 #(\n .INIT(64'h0100000000000000)) \n po_stg23_incdec_r_i_5\n (.I0(A[6]),\n .I1(A[8]),\n .I2(A[7]),\n .I3(\\stg2_r[8]_i_3_n_0 ),\n .I4(po_stg23_incdec_r_i_10_n_0),\n .I5(up_r),\n .O(po_stg23_incdec_r_i_5_n_0));\n LUT4 #(\n .INIT(16'hD0DD)) \n po_stg23_incdec_r_i_6\n (.I0(po_counter_read_val_r[5]),\n .I1(stg2_final_r[5]),\n .I2(stg2_final_r[4]),\n .I3(po_counter_read_val_r[4]),\n .O(po_stg23_incdec_r_i_6_n_0));\n LUT4 #(\n .INIT(16'hD0DD)) \n po_stg23_incdec_r_i_7\n (.I0(stg2_final_r[3]),\n .I1(po_counter_read_val_r[3]),\n .I2(po_counter_read_val_r[4]),\n .I3(stg2_final_r[4]),\n .O(po_stg23_incdec_r_i_7_n_0));\n LUT6 #(\n .INIT(64'hB0BBBBBB0000B0BB)) \n po_stg23_incdec_r_i_8\n (.I0(po_counter_read_val_r[2]),\n .I1(stg2_final_r[2]),\n .I2(po_counter_read_val_r[0]),\n .I3(stg2_final_r[0]),\n .I4(stg2_final_r[1]),\n .I5(po_counter_read_val_r[1]),\n .O(po_stg23_incdec_r_i_8_n_0));\n LUT4 #(\n .INIT(16'hD0DD)) \n po_stg23_incdec_r_i_9\n (.I0(po_counter_read_val_r[2]),\n .I1(stg2_final_r[2]),\n .I2(stg2_final_r[3]),\n .I3(po_counter_read_val_r[3]),\n .O(po_stg23_incdec_r_i_9_n_0));\n LUT6 #(\n .INIT(64'hFFFFEAFF0000EA00)) \n poc_backup_r_i_1__0\n (.I0(poc_backup_r_i_2__0_n_0),\n .I1(poc_backup_r_reg_1),\n .I2(sm_r[2]),\n .I3(poc_backup_r_i_3_n_0),\n .I4(poc_backup_r_i_4_n_0),\n .I5(poc_backup_r),\n .O(poc_backup_r_i_1__0_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFF7F)) \n poc_backup_r_i_2\n (.I0(\\run_ends_r_reg[1]_0 ),\n .I1(\\run_ends_r_reg[0] ),\n .I2(\\run_ends_r_reg[1] ),\n .I3(\\sm_r_reg[3]_0 ),\n .I4(\\rise_trail_r_reg[5] ),\n .I5(rstdiv0_sync_r1_reg_rep__20),\n .O(poc_backup_r_reg_0));\n (* SOFT_HLUTNM = \"soft_lutpair406\" *) \n LUT2 #(\n .INIT(4'h8)) \n poc_backup_r_i_2__0\n (.I0(sm_r[3]),\n .I1(E),\n .O(poc_backup_r_i_2__0_n_0));\n LUT3 #(\n .INIT(8'h01)) \n poc_backup_r_i_3\n (.I0(sm_r[0]),\n .I1(\\stg2_r_reg[0]_0 ),\n .I2(rstdiv0_sync_r1_reg_rep__25),\n .O(poc_backup_r_i_3_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFF0F700F700)) \n poc_backup_r_i_4\n (.I0(poc_backup_r),\n .I1(po_rdy),\n .I2(E),\n .I3(sm_r[3]),\n .I4(poc_backup_r_i_5_n_0),\n .I5(sm_r[2]),\n .O(poc_backup_r_i_4_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair416\" *) \n LUT4 #(\n .INIT(16'hFFF7)) \n poc_backup_r_i_5\n (.I0(\\sm_r[3]_i_7_n_0 ),\n .I1(done_r_reg),\n .I2(ocd_ktap_right),\n .I3(\\sm_r_reg[3]_0 ),\n .O(poc_backup_r_i_5_n_0));\n FDRE poc_backup_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(poc_backup_r_i_1__0_n_0),\n .Q(poc_backup_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFFFFFFF0000FF46)) \n \\resume_wait_r[0]_i_1 \n (.I0(resume_wait_r[0]),\n .I1(E),\n .I2(rstdiv0_sync_r1_reg_rep__26),\n .I3(\\resume_wait_r[9]_i_5_n_0 ),\n .I4(\\resume_wait_r[10]_i_3_n_0 ),\n .I5(\\resume_wait_r[10]_i_4_n_0 ),\n .O(\\resume_wait_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair403\" *) \n LUT5 #(\n .INIT(32'h0000FF02)) \n \\resume_wait_r[10]_i_1 \n (.I0(resume_wait_r[10]),\n .I1(\\resume_wait_r[10]_i_2_n_0 ),\n .I2(\\resume_wait_r[9]_i_5_n_0 ),\n .I3(\\resume_wait_r[10]_i_3_n_0 ),\n .I4(\\resume_wait_r[10]_i_4_n_0 ),\n .O(\\resume_wait_r[10]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair401\" *) \n LUT5 #(\n .INIT(32'h00000001)) \n \\resume_wait_r[10]_i_2 \n (.I0(\\resume_wait_r[9]_i_6_n_0 ),\n .I1(resume_wait_r[6]),\n .I2(resume_wait_r[9]),\n .I3(resume_wait_r[7]),\n .I4(resume_wait_r[8]),\n .O(\\resume_wait_r[10]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000008000000000)) \n \\resume_wait_r[10]_i_3 \n (.I0(oclk_center_write_resume_r_i_2_n_0),\n .I1(\\stg2_r_reg[0]_0 ),\n .I2(po_done_r),\n .I3(sm_r[3]),\n .I4(oclk_center_write_resume),\n .I5(oclk_center_write_resume_r_i_3_n_0),\n .O(\\resume_wait_r[10]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0000000022222220)) \n \\resume_wait_r[10]_i_4 \n (.I0(ocd_ktap_left_r_i_2_n_0),\n .I1(\\sm_r_reg[3]_0 ),\n .I2(sm_r[0]),\n .I3(\\stg2_r_reg[0]_0 ),\n .I4(ocd_ktap_left_r_i_3_n_0),\n .I5(rstdiv0_sync_r1_reg_rep__20),\n .O(\\resume_wait_r[10]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h00000000EECEDDCE)) \n \\resume_wait_r[1]_i_1 \n (.I0(resume_wait_r[1]),\n .I1(\\resume_wait_r[9]_i_5_n_0 ),\n .I2(rstdiv0_sync_r1_reg_rep__26),\n .I3(E),\n .I4(resume_wait_r[0]),\n .I5(\\resume_wait_r[9]_i_4_n_0 ),\n .O(\\resume_wait_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00000000EECEDDCE)) \n \\resume_wait_r[2]_i_1 \n (.I0(resume_wait_r[2]),\n .I1(\\resume_wait_r[9]_i_5_n_0 ),\n .I2(rstdiv0_sync_r1_reg_rep__26),\n .I3(E),\n .I4(\\resume_wait_r[2]_i_2_n_0 ),\n .I5(\\resume_wait_r[9]_i_4_n_0 ),\n .O(\\resume_wait_r[2]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\resume_wait_r[2]_i_2 \n (.I0(resume_wait_r[0]),\n .I1(resume_wait_r[1]),\n .O(\\resume_wait_r[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00000000DDCEEECE)) \n \\resume_wait_r[3]_i_1 \n (.I0(resume_wait_r[3]),\n .I1(\\resume_wait_r[9]_i_5_n_0 ),\n .I2(rstdiv0_sync_r1_reg_rep__26),\n .I3(E),\n .I4(\\resume_wait_r[7]_i_2_n_0 ),\n .I5(\\resume_wait_r[9]_i_4_n_0 ),\n .O(\\resume_wait_r[3]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h00D0)) \n \\resume_wait_r[4]_i_1 \n (.I0(oclk_center_write_resume),\n .I1(oclk_center_write_resume_r_i_3_n_0),\n .I2(\\resume_wait_r[4]_i_2_n_0 ),\n .I3(\\resume_wait_r[9]_i_4_n_0 ),\n .O(\\resume_wait_r[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFD0DFFFFF2020)) \n \\resume_wait_r[4]_i_2 \n (.I0(\\resume_wait_r[7]_i_2_n_0 ),\n .I1(resume_wait_r[3]),\n .I2(E),\n .I3(rstdiv0_sync_r1_reg_rep__26),\n .I4(\\resume_wait_r[9]_i_8_n_0 ),\n .I5(resume_wait_r[4]),\n .O(\\resume_wait_r[4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAAAAA9)) \n \\resume_wait_r[5]_i_1 \n (.I0(resume_wait_r[5]),\n .I1(resume_wait_r[3]),\n .I2(resume_wait_r[4]),\n .I3(resume_wait_r[2]),\n .I4(resume_wait_r[1]),\n .I5(resume_wait_r[0]),\n .O(resume_wait_ns0[5]));\n (* SOFT_HLUTNM = \"soft_lutpair400\" *) \n LUT5 #(\n .INIT(32'hFEFF0100)) \n \\resume_wait_r[6]_i_1 \n (.I0(resume_wait_r[3]),\n .I1(resume_wait_r[4]),\n .I2(resume_wait_r[5]),\n .I3(\\resume_wait_r[7]_i_2_n_0 ),\n .I4(resume_wait_r[6]),\n .O(resume_wait_ns0[6]));\n LUT6 #(\n .INIT(64'hFFFFFFFB00000004)) \n \\resume_wait_r[7]_i_1 \n (.I0(resume_wait_r[6]),\n .I1(\\resume_wait_r[7]_i_2_n_0 ),\n .I2(resume_wait_r[5]),\n .I3(resume_wait_r[4]),\n .I4(resume_wait_r[3]),\n .I5(resume_wait_r[7]),\n .O(resume_wait_ns0[7]));\n (* SOFT_HLUTNM = \"soft_lutpair405\" *) \n LUT3 #(\n .INIT(8'h01)) \n \\resume_wait_r[7]_i_2 \n (.I0(resume_wait_r[2]),\n .I1(resume_wait_r[1]),\n .I2(resume_wait_r[0]),\n .O(\\resume_wait_r[7]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair415\" *) \n LUT3 #(\n .INIT(8'hE1)) \n \\resume_wait_r[8]_i_1 \n (.I0(resume_wait_r[7]),\n .I1(\\resume_wait_r[9]_i_7_n_0 ),\n .I2(resume_wait_r[8]),\n .O(resume_wait_ns0[8]));\n LUT4 #(\n .INIT(16'hEEFE)) \n \\resume_wait_r[9]_i_1 \n (.I0(\\resume_wait_r[9]_i_4_n_0 ),\n .I1(\\resume_wait_r[9]_i_5_n_0 ),\n .I2(rstdiv0_sync_r1_reg_rep__26),\n .I3(E),\n .O(\\resume_wait_r[9]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\resume_wait_r[9]_i_2 \n (.I0(resume_wait_r[10]),\n .I1(resume_wait_r[8]),\n .I2(resume_wait_r[7]),\n .I3(resume_wait_r[9]),\n .I4(resume_wait_r[6]),\n .I5(\\resume_wait_r[9]_i_6_n_0 ),\n .O(E));\n (* SOFT_HLUTNM = \"soft_lutpair415\" *) \n LUT4 #(\n .INIT(16'hAAA9)) \n \\resume_wait_r[9]_i_3 \n (.I0(resume_wait_r[9]),\n .I1(\\resume_wait_r[9]_i_7_n_0 ),\n .I2(resume_wait_r[7]),\n .I3(resume_wait_r[8]),\n .O(resume_wait_ns0[9]));\n (* SOFT_HLUTNM = \"soft_lutpair403\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\resume_wait_r[9]_i_4 \n (.I0(\\resume_wait_r[10]_i_4_n_0 ),\n .I1(\\resume_wait_r[10]_i_3_n_0 ),\n .O(\\resume_wait_r[9]_i_4_n_0 ));\n LUT3 #(\n .INIT(8'hF2)) \n \\resume_wait_r[9]_i_5 \n (.I0(oclk_center_write_resume),\n .I1(oclk_center_write_resume_r_i_3_n_0),\n .I2(\\resume_wait_r[9]_i_8_n_0 ),\n .O(\\resume_wait_r[9]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\resume_wait_r[9]_i_6 \n (.I0(resume_wait_r[3]),\n .I1(resume_wait_r[4]),\n .I2(resume_wait_r[5]),\n .I3(resume_wait_r[0]),\n .I4(resume_wait_r[1]),\n .I5(resume_wait_r[2]),\n .O(\\resume_wait_r[9]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair400\" *) \n LUT5 #(\n .INIT(32'hFFFFFFFB)) \n \\resume_wait_r[9]_i_7 \n (.I0(resume_wait_r[6]),\n .I1(\\resume_wait_r[7]_i_2_n_0 ),\n .I2(resume_wait_r[5]),\n .I3(resume_wait_r[4]),\n .I4(resume_wait_r[3]),\n .O(\\resume_wait_r[9]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\resume_wait_r[9]_i_8 \n (.I0(poc_backup_r),\n .I1(\\stg3_r[5]_i_6_n_0 ),\n .O(\\resume_wait_r[9]_i_8_n_0 ));\n FDRE \\resume_wait_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\resume_wait_r[0]_i_1_n_0 ),\n .Q(resume_wait_r[0]),\n .R(1'b0));\n FDRE \\resume_wait_r_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(\\resume_wait_r[10]_i_1_n_0 ),\n .Q(resume_wait_r[10]),\n .R(1'b0));\n FDRE \\resume_wait_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\resume_wait_r[1]_i_1_n_0 ),\n .Q(resume_wait_r[1]),\n .R(1'b0));\n FDRE \\resume_wait_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\resume_wait_r[2]_i_1_n_0 ),\n .Q(resume_wait_r[2]),\n .R(1'b0));\n FDRE \\resume_wait_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\resume_wait_r[3]_i_1_n_0 ),\n .Q(resume_wait_r[3]),\n .R(1'b0));\n FDRE \\resume_wait_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\resume_wait_r[4]_i_1_n_0 ),\n .Q(resume_wait_r[4]),\n .R(1'b0));\n FDRE \\resume_wait_r_reg[5] \n (.C(CLK),\n .CE(E),\n .D(resume_wait_ns0[5]),\n .Q(resume_wait_r[5]),\n .R(\\resume_wait_r[9]_i_1_n_0 ));\n FDRE \\resume_wait_r_reg[6] \n (.C(CLK),\n .CE(E),\n .D(resume_wait_ns0[6]),\n .Q(resume_wait_r[6]),\n .R(\\resume_wait_r[9]_i_1_n_0 ));\n FDRE \\resume_wait_r_reg[7] \n (.C(CLK),\n .CE(E),\n .D(resume_wait_ns0[7]),\n .Q(resume_wait_r[7]),\n .R(\\resume_wait_r[9]_i_1_n_0 ));\n FDRE \\resume_wait_r_reg[8] \n (.C(CLK),\n .CE(E),\n .D(resume_wait_ns0[8]),\n .Q(resume_wait_r[8]),\n .R(\\resume_wait_r[9]_i_1_n_0 ));\n FDRE \\resume_wait_r_reg[9] \n (.C(CLK),\n .CE(E),\n .D(resume_wait_ns0[9]),\n .Q(resume_wait_r[9]),\n .R(\\resume_wait_r[9]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF7F0000004000)) \n scanning_right_r_i_1\n (.I0(scan_right_r_reg),\n .I1(samp_done),\n .I2(rd_active_r2),\n .I3(sm_r[0]),\n .I4(scanning_right_r_i_3_n_0),\n .I5(scanning_right),\n .O(scanning_right_r_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair398\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n scanning_right_r_i_3\n (.I0(sm_r[2]),\n .I1(\\stg2_r_reg[0]_0 ),\n .I2(sm_r[3]),\n .I3(rstdiv0_sync_r1_reg_rep__26),\n .O(scanning_right_r_i_3_n_0));\n FDRE scanning_right_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(scanning_right_r_i_1_n_0),\n .Q(scanning_right),\n .R(1'b0));\n FDRE \\simp_stg3_final_r_reg[0] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_3 ),\n .D(Q[0]),\n .Q(\\simp_stg3_final_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\simp_stg3_final_r_reg[10] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_2 ),\n .D(Q[4]),\n .Q(\\simp_stg3_final_r_reg_n_0_[10] ),\n .R(1'b0));\n FDRE \\simp_stg3_final_r_reg[11] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_2 ),\n .D(Q[5]),\n .Q(\\simp_stg3_final_r_reg_n_0_[11] ),\n .R(1'b0));\n FDRE \\simp_stg3_final_r_reg[12] \n (.C(CLK),\n .CE(\\byte_r_reg[1]_0 ),\n .D(Q[0]),\n .Q(\\simp_stg3_final_r_reg_n_0_[12] ),\n .R(1'b0));\n FDRE \\simp_stg3_final_r_reg[13] \n (.C(CLK),\n .CE(\\byte_r_reg[1]_0 ),\n .D(Q[1]),\n .Q(\\simp_stg3_final_r_reg_n_0_[13] ),\n .R(1'b0));\n FDRE \\simp_stg3_final_r_reg[14] \n (.C(CLK),\n .CE(\\byte_r_reg[1]_0 ),\n .D(Q[2]),\n .Q(\\simp_stg3_final_r_reg_n_0_[14] ),\n .R(1'b0));\n FDRE \\simp_stg3_final_r_reg[15] \n (.C(CLK),\n .CE(\\byte_r_reg[1]_0 ),\n .D(Q[3]),\n .Q(\\simp_stg3_final_r_reg_n_0_[15] ),\n .R(1'b0));\n FDRE \\simp_stg3_final_r_reg[16] \n (.C(CLK),\n .CE(\\byte_r_reg[1]_0 ),\n .D(Q[4]),\n .Q(\\stg3_init_val_reg[4]_0 ),\n .R(1'b0));\n FDRE \\simp_stg3_final_r_reg[17] \n (.C(CLK),\n .CE(\\byte_r_reg[1]_0 ),\n .D(Q[5]),\n .Q(\\simp_stg3_final_r_reg_n_0_[17] ),\n .R(1'b0));\n FDRE \\simp_stg3_final_r_reg[18] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_1 ),\n .D(Q[0]),\n .Q(\\simp_stg3_final_r_reg_n_0_[18] ),\n .R(1'b0));\n FDRE \\simp_stg3_final_r_reg[19] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_1 ),\n .D(Q[1]),\n .Q(\\simp_stg3_final_r_reg_n_0_[19] ),\n .R(1'b0));\n FDRE \\simp_stg3_final_r_reg[1] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_3 ),\n .D(Q[1]),\n .Q(\\simp_stg3_final_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE \\simp_stg3_final_r_reg[20] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_1 ),\n .D(Q[2]),\n .Q(\\simp_stg3_final_r_reg_n_0_[20] ),\n .R(1'b0));\n FDRE \\simp_stg3_final_r_reg[21] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_1 ),\n .D(Q[3]),\n .Q(\\simp_stg3_final_r_reg_n_0_[21] ),\n .R(1'b0));\n FDRE \\simp_stg3_final_r_reg[22] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_1 ),\n .D(Q[4]),\n .Q(\\simp_stg3_final_r_reg_n_0_[22] ),\n .R(1'b0));\n FDRE \\simp_stg3_final_r_reg[23] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_1 ),\n .D(Q[5]),\n .Q(\\simp_stg3_final_r_reg_n_0_[23] ),\n .R(1'b0));\n FDRE \\simp_stg3_final_r_reg[2] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_3 ),\n .D(Q[2]),\n .Q(\\stg3_init_val_reg[2]_0 ),\n .R(1'b0));\n FDRE \\simp_stg3_final_r_reg[3] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_3 ),\n .D(Q[3]),\n .Q(\\simp_stg3_final_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE \\simp_stg3_final_r_reg[4] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_3 ),\n .D(Q[4]),\n .Q(\\simp_stg3_final_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE \\simp_stg3_final_r_reg[5] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_3 ),\n .D(Q[5]),\n .Q(\\simp_stg3_final_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE \\simp_stg3_final_r_reg[6] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_2 ),\n .D(Q[0]),\n .Q(\\simp_stg3_final_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE \\simp_stg3_final_r_reg[7] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_2 ),\n .D(Q[1]),\n .Q(\\simp_stg3_final_r_reg_n_0_[7] ),\n .R(1'b0));\n FDRE \\simp_stg3_final_r_reg[8] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_2 ),\n .D(Q[2]),\n .Q(\\simp_stg3_final_r_reg_n_0_[8] ),\n .R(1'b0));\n FDRE \\simp_stg3_final_r_reg[9] \n (.C(CLK),\n .CE(\\byte_r_reg[0]_2 ),\n .D(Q[3]),\n .Q(\\simp_stg3_final_r_reg_n_0_[9] ),\n .R(1'b0));\n LUT3 #(\n .INIT(8'hB8)) \n \\sm_r[0]_i_1 \n (.I0(E),\n .I1(sm_r[3]),\n .I2(\\sm_r[0]_i_2__0_n_0 ),\n .O(\\sm_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h000000AAFFF3FFFF)) \n \\sm_r[0]_i_2__0 \n (.I0(scanning_right_r_reg_0),\n .I1(\\sm_r[0]_i_3_n_0 ),\n .I2(\\sm_r_reg[3]_0 ),\n .I3(\\stg2_r_reg[0]_0 ),\n .I4(sm_r[2]),\n .I5(sm_r[0]),\n .O(\\sm_r[0]_i_2__0_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair407\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\sm_r[0]_i_3 \n (.I0(ocd_ktap_right),\n .I1(oclk_center_write_resume_r_i_5_n_0),\n .O(\\sm_r[0]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair411\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\sm_r[1]_i_1 \n (.I0(E),\n .I1(sm_r[3]),\n .I2(\\sm_r[1]_i_2_n_0 ),\n .O(\\sm_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000EEEF55550000)) \n \\sm_r[1]_i_2 \n (.I0(\\stg2_r_reg[0]_0 ),\n .I1(\\sm_r_reg[3]_0 ),\n .I2(ocd_ktap_right),\n .I3(edge_aligned_r_reg_0),\n .I4(sm_r[0]),\n .I5(sm_r[2]),\n .O(\\sm_r[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hBBBBB88888888888)) \n \\sm_r[2]_i_1 \n (.I0(E),\n .I1(sm_r[3]),\n .I2(\\stg2_r_reg[0]_0 ),\n .I3(sm_r[0]),\n .I4(sm_r[2]),\n .I5(\\sm_r[2]_i_2_n_0 ),\n .O(\\sm_r[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFF0DFFFF)) \n \\sm_r[2]_i_2 \n (.I0(\\sm_r[3]_i_7_n_0 ),\n .I1(ocd_ktap_right),\n .I2(\\sm_r_reg[3]_0 ),\n .I3(\\stg2_r_reg[0]_0 ),\n .I4(sm_r[2]),\n .I5(sm_r[0]),\n .O(\\sm_r[2]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'hFEFF)) \n \\sm_r[3]_i_1 \n (.I0(\\sm_r[3]_i_3_n_0 ),\n .I1(\\sm_r[3]_i_4_n_0 ),\n .I2(cmplx_samples_done_r_i_2_n_0),\n .I3(\\sm_r_reg[0]_0 ),\n .O(sm_ns));\n LUT6 #(\n .INIT(64'h00B0BBBB000000B0)) \n \\sm_r[3]_i_10 \n (.I0(po_counter_read_val_r[2]),\n .I1(stg2_final_r[2]),\n .I2(po_counter_read_val_r[0]),\n .I3(stg2_final_r[0]),\n .I4(stg2_final_r[1]),\n .I5(po_counter_read_val_r[1]),\n .O(\\sm_r[3]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'h888B888888888888)) \n \\sm_r[3]_i_2 \n (.I0(E),\n .I1(sm_r[3]),\n .I2(ocd_ktap_right),\n .I3(\\sm_r_reg[3]_0 ),\n .I4(\\sm_r[3]_i_6_n_0 ),\n .I5(\\sm_r[3]_i_7_n_0 ),\n .O(\\sm_r[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000010000000)) \n \\sm_r[3]_i_3 \n (.I0(sm_r[3]),\n .I1(sm_r[2]),\n .I2(sm_r[0]),\n .I3(samp_done),\n .I4(rd_active_r2),\n .I5(\\stg2_r_reg[0]_0 ),\n .O(\\sm_r[3]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h00000000F3F203F2)) \n \\sm_r[3]_i_4 \n (.I0(done_r_reg),\n .I1(E),\n .I2(sm_r[0]),\n .I3(\\stg2_r_reg[0]_0 ),\n .I4(po_done_r),\n .I5(\\sm_r[3]_i_8_n_0 ),\n .O(\\sm_r[3]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFF7FFFFFFFF)) \n \\sm_r[3]_i_5 \n (.I0(\\sm_r[3]_i_9_n_0 ),\n .I1(po_stg23_incdec_r_i_3_n_0),\n .I2(poc_backup_r),\n .I3(oclkdelay_center_calib_done_r_i_3_n_0),\n .I4(E),\n .I5(po_rdy),\n .O(\\sm_r_reg[0]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair404\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\sm_r[3]_i_6 \n (.I0(sm_r[0]),\n .I1(sm_r[2]),\n .I2(\\stg2_r_reg[0]_0 ),\n .O(\\sm_r[3]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hA22A22222222A22A)) \n \\sm_r[3]_i_7 \n (.I0(edge_aligned_r_reg_0),\n .I1(ocd_edge_detect_rdy),\n .I2(ninety_offsets[0]),\n .I3(ninety_offsets_final_r[0]),\n .I4(ninety_offsets[1]),\n .I5(ninety_offsets_final_r[1]),\n .O(\\sm_r[3]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair408\" *) \n LUT2 #(\n .INIT(4'hB)) \n \\sm_r[3]_i_8 \n (.I0(sm_r[3]),\n .I1(sm_r[2]),\n .O(\\sm_r[3]_i_8_n_0 ));\n LUT4 #(\n .INIT(16'h08AA)) \n \\sm_r[3]_i_9 \n (.I0(po_stg23_incdec_r_i_6_n_0),\n .I1(po_stg23_incdec_r_i_9_n_0),\n .I2(\\sm_r[3]_i_10_n_0 ),\n .I3(po_stg23_incdec_r_i_7_n_0),\n .O(\\sm_r[3]_i_9_n_0 ));\n FDRE \\sm_r_reg[0] \n (.C(CLK),\n .CE(sm_ns),\n .D(\\sm_r[0]_i_1_n_0 ),\n .Q(sm_r[0]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE \\sm_r_reg[1] \n (.C(CLK),\n .CE(sm_ns),\n .D(\\sm_r[1]_i_1_n_0 ),\n .Q(\\stg2_r_reg[0]_0 ),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE \\sm_r_reg[2] \n (.C(CLK),\n .CE(sm_ns),\n .D(\\sm_r[2]_i_1_n_0 ),\n .Q(sm_r[2]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n FDRE \\sm_r_reg[3] \n (.C(CLK),\n .CE(sm_ns),\n .D(\\sm_r[3]_i_2_n_0 ),\n .Q(sm_r[3]),\n .R(rstdiv0_sync_r1_reg_rep__10));\n (* SOFT_HLUTNM = \"soft_lutpair410\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n \\stg2_final_r[0]_i_1 \n (.I0(\\stg2_target_r_reg_n_0_[0] ),\n .I1(\\stg2_target_r_reg_n_0_[6] ),\n .I2(p_1_in),\n .I3(\\stg2_target_r_reg_n_0_[7] ),\n .O(\\stg2_final_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair413\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n \\stg2_final_r[1]_i_1 \n (.I0(\\stg2_target_r_reg_n_0_[1] ),\n .I1(\\stg2_target_r_reg_n_0_[6] ),\n .I2(p_1_in),\n .I3(\\stg2_target_r_reg_n_0_[7] ),\n .O(\\stg2_final_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair414\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n \\stg2_final_r[2]_i_1 \n (.I0(\\stg2_target_r_reg_n_0_[2] ),\n .I1(\\stg2_target_r_reg_n_0_[6] ),\n .I2(p_1_in),\n .I3(\\stg2_target_r_reg_n_0_[7] ),\n .O(\\stg2_final_r[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair413\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n \\stg2_final_r[3]_i_1 \n (.I0(\\stg2_target_r_reg_n_0_[3] ),\n .I1(\\stg2_target_r_reg_n_0_[6] ),\n .I2(p_1_in),\n .I3(\\stg2_target_r_reg_n_0_[7] ),\n .O(\\stg2_final_r[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair414\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n \\stg2_final_r[4]_i_1 \n (.I0(\\stg2_target_r_reg_n_0_[4] ),\n .I1(\\stg2_target_r_reg_n_0_[6] ),\n .I2(p_1_in),\n .I3(\\stg2_target_r_reg_n_0_[7] ),\n .O(\\stg2_final_r[4]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair410\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n \\stg2_final_r[5]_i_1 \n (.I0(\\stg2_target_r_reg_n_0_[5] ),\n .I1(\\stg2_target_r_reg_n_0_[6] ),\n .I2(p_1_in),\n .I3(\\stg2_target_r_reg_n_0_[7] ),\n .O(\\stg2_final_r[5]_i_1_n_0 ));\n FDRE \\stg2_final_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\stg2_final_r[0]_i_1_n_0 ),\n .Q(stg2_final_r[0]),\n .R(p_1_in));\n FDRE \\stg2_final_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\stg2_final_r[1]_i_1_n_0 ),\n .Q(stg2_final_r[1]),\n .R(p_1_in));\n FDRE \\stg2_final_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\stg2_final_r[2]_i_1_n_0 ),\n .Q(stg2_final_r[2]),\n .R(p_1_in));\n FDRE \\stg2_final_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\stg2_final_r[3]_i_1_n_0 ),\n .Q(stg2_final_r[3]),\n .R(p_1_in));\n FDRE \\stg2_final_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\stg2_final_r[4]_i_1_n_0 ),\n .Q(stg2_final_r[4]),\n .R(p_1_in));\n FDRE \\stg2_final_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\stg2_final_r[5]_i_1_n_0 ),\n .Q(stg2_final_r[5]),\n .R(p_1_in));\n (* METHODOLOGY_DRC_VIOS = \"{SYNTH-8 {cell *THIS*}}\" *) \n CARRY4 stg2_ns0_carry\n (.CI(1'b0),\n .CO({stg2_ns0_carry_n_0,stg2_ns0_carry_n_1,stg2_ns0_carry_n_2,stg2_ns0_carry_n_3}),\n .CYINIT(A[0]),\n .DI({A[3:1],up_r}),\n .O(out[4:1]),\n .S({stg2_ns0_carry_i_1_n_0,stg2_ns0_carry_i_2_n_0,stg2_ns0_carry_i_3_n_0,stg2_ns0_carry_i_4_n_0}));\n (* METHODOLOGY_DRC_VIOS = \"{SYNTH-8 {cell *THIS*}}\" *) \n CARRY4 stg2_ns0_carry__0\n (.CI(stg2_ns0_carry_n_0),\n .CO({NLW_stg2_ns0_carry__0_CO_UNCONNECTED[3],stg2_ns0_carry__0_n_1,stg2_ns0_carry__0_n_2,stg2_ns0_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,A[6:4]}),\n .O(out[8:5]),\n .S({stg2_ns0_carry__0_i_1_n_0,stg2_ns0_carry__0_i_2_n_0,stg2_ns0_carry__0_i_3_n_0,stg2_ns0_carry__0_i_4_n_0}));\n LUT2 #(\n .INIT(4'h9)) \n stg2_ns0_carry__0_i_1\n (.I0(A[7]),\n .I1(A[8]),\n .O(stg2_ns0_carry__0_i_1_n_0));\n LUT2 #(\n .INIT(4'h9)) \n stg2_ns0_carry__0_i_2\n (.I0(A[6]),\n .I1(A[7]),\n .O(stg2_ns0_carry__0_i_2_n_0));\n LUT2 #(\n .INIT(4'h9)) \n stg2_ns0_carry__0_i_3\n (.I0(A[5]),\n .I1(A[6]),\n .O(stg2_ns0_carry__0_i_3_n_0));\n LUT2 #(\n .INIT(4'h9)) \n stg2_ns0_carry__0_i_4\n (.I0(A[4]),\n .I1(A[5]),\n .O(stg2_ns0_carry__0_i_4_n_0));\n LUT2 #(\n .INIT(4'h9)) \n stg2_ns0_carry_i_1\n (.I0(A[3]),\n .I1(A[4]),\n .O(stg2_ns0_carry_i_1_n_0));\n LUT2 #(\n .INIT(4'h9)) \n stg2_ns0_carry_i_2\n (.I0(A[2]),\n .I1(A[3]),\n .O(stg2_ns0_carry_i_2_n_0));\n LUT2 #(\n .INIT(4'h9)) \n stg2_ns0_carry_i_3\n (.I0(A[1]),\n .I1(A[2]),\n .O(stg2_ns0_carry_i_3_n_0));\n LUT2 #(\n .INIT(4'h9)) \n stg2_ns0_carry_i_4\n (.I0(A[1]),\n .I1(up_r),\n .O(stg2_ns0_carry_i_4_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair419\" *) \n LUT3 #(\n .INIT(8'h35)) \n \\stg2_r[0]_i_1 \n (.I0(\\wl_po_fine_cnt_reg[18] ),\n .I1(A[0]),\n .I2(\\stg2_r[8]_i_3_n_0 ),\n .O(stg2_ns[0]));\n (* SOFT_HLUTNM = \"soft_lutpair420\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\stg2_r[1]_i_1 \n (.I0(out[1]),\n .I1(\\stg2_r[8]_i_3_n_0 ),\n .I2(\\wl_po_fine_cnt_reg[14] [0]),\n .O(stg2_ns[1]));\n (* SOFT_HLUTNM = \"soft_lutpair417\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\stg2_r[2]_i_1 \n (.I0(out[2]),\n .I1(\\stg2_r[8]_i_3_n_0 ),\n .I2(\\wl_po_fine_cnt_reg[14] [1]),\n .O(stg2_ns[2]));\n (* SOFT_HLUTNM = \"soft_lutpair419\" *) \n LUT3 #(\n .INIT(8'h8B)) \n \\stg2_r[3]_i_1 \n (.I0(out[3]),\n .I1(\\stg2_r[8]_i_3_n_0 ),\n .I2(\\wl_po_fine_cnt_reg[3] ),\n .O(stg2_ns[3]));\n (* SOFT_HLUTNM = \"soft_lutpair417\" *) \n LUT3 #(\n .INIT(8'h8B)) \n \\stg2_r[4]_i_1 \n (.I0(out[4]),\n .I1(\\stg2_r[8]_i_3_n_0 ),\n .I2(\\byte_r_reg[0] ),\n .O(stg2_ns[4]));\n (* SOFT_HLUTNM = \"soft_lutpair420\" *) \n LUT3 #(\n .INIT(8'h8B)) \n \\stg2_r[5]_i_1 \n (.I0(out[5]),\n .I1(\\stg2_r[8]_i_3_n_0 ),\n .I2(\\wl_po_fine_cnt_reg[17] ),\n .O(stg2_ns[5]));\n (* SOFT_HLUTNM = \"soft_lutpair412\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\stg2_r[6]_i_1 \n (.I0(out[6]),\n .I1(\\stg2_r[8]_i_3_n_0 ),\n .O(stg2_ns[6]));\n (* SOFT_HLUTNM = \"soft_lutpair422\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\stg2_r[7]_i_1 \n (.I0(out[7]),\n .I1(\\stg2_r[8]_i_3_n_0 ),\n .O(stg2_ns[7]));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAAAAAB)) \n \\stg2_r[8]_i_1 \n (.I0(\\stg2_r[8]_i_3_n_0 ),\n .I1(sm_r[0]),\n .I2(\\stg2_r_reg[0]_0 ),\n .I3(rstdiv0_sync_r1_reg_rep__26),\n .I4(sm_r[3]),\n .I5(sm_r[2]),\n .O(\\stg2_r[8]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair422\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\stg2_r[8]_i_2 \n (.I0(out[8]),\n .I1(\\stg2_r[8]_i_3_n_0 ),\n .O(stg2_ns[8]));\n LUT5 #(\n .INIT(32'h40400040)) \n \\stg2_r[8]_i_3 \n (.I0(po_done_r),\n .I1(po_rdy),\n .I2(\\two_r[1]_i_2_n_0 ),\n .I3(two_r[1]),\n .I4(two_r[0]),\n .O(\\stg2_r[8]_i_3_n_0 ));\n FDRE \\stg2_r_reg[0] \n (.C(CLK),\n .CE(\\stg2_r[8]_i_1_n_0 ),\n .D(stg2_ns[0]),\n .Q(A[0]),\n .R(1'b0));\n FDRE \\stg2_r_reg[1] \n (.C(CLK),\n .CE(\\stg2_r[8]_i_1_n_0 ),\n .D(stg2_ns[1]),\n .Q(A[1]),\n .R(1'b0));\n FDRE \\stg2_r_reg[2] \n (.C(CLK),\n .CE(\\stg2_r[8]_i_1_n_0 ),\n .D(stg2_ns[2]),\n .Q(A[2]),\n .R(1'b0));\n FDRE \\stg2_r_reg[3] \n (.C(CLK),\n .CE(\\stg2_r[8]_i_1_n_0 ),\n .D(stg2_ns[3]),\n .Q(A[3]),\n .R(1'b0));\n FDRE \\stg2_r_reg[4] \n (.C(CLK),\n .CE(\\stg2_r[8]_i_1_n_0 ),\n .D(stg2_ns[4]),\n .Q(A[4]),\n .R(1'b0));\n FDRE \\stg2_r_reg[5] \n (.C(CLK),\n .CE(\\stg2_r[8]_i_1_n_0 ),\n .D(stg2_ns[5]),\n .Q(A[5]),\n .R(1'b0));\n FDRE \\stg2_r_reg[6] \n (.C(CLK),\n .CE(\\stg2_r[8]_i_1_n_0 ),\n .D(stg2_ns[6]),\n .Q(A[6]),\n .R(1'b0));\n FDRE \\stg2_r_reg[7] \n (.C(CLK),\n .CE(\\stg2_r[8]_i_1_n_0 ),\n .D(stg2_ns[7]),\n .Q(A[7]),\n .R(1'b0));\n FDRE \\stg2_r_reg[8] \n (.C(CLK),\n .CE(\\stg2_r[8]_i_1_n_0 ),\n .D(stg2_ns[8]),\n .Q(A[8]),\n .R(1'b0));\n LUT4 #(\n .INIT(16'h56A6)) \n \\stg2_target_r[1]_i_1 \n (.I0(\\wl_po_fine_cnt_reg[14] [0]),\n .I1(p_0_in[0]),\n .I2(p_0_in0_carry_i_9_n_0),\n .I3(\\stg3_r_reg[0]_0 ),\n .O(stg2_target_ns));\n LUT4 #(\n .INIT(16'h56A6)) \n \\stg2_target_r[4]_i_7 \n (.I0(\\wl_po_fine_cnt_reg[14] [0]),\n .I1(p_0_in[0]),\n .I2(p_0_in0_carry_i_9_n_0),\n .I3(\\stg3_r_reg[0]_0 ),\n .O(S));\n LUT1 #(\n .INIT(2'h2)) \n \\stg2_target_r[8]_i_3 \n (.I0(p_0_in0_carry__0_n_5),\n .O(\\stg2_target_r_reg[8]_0 [2]));\n LUT1 #(\n .INIT(2'h2)) \n \\stg2_target_r[8]_i_4 \n (.I0(p_0_in0_carry__0_n_6),\n .O(\\stg2_target_r_reg[8]_0 [1]));\n LUT1 #(\n .INIT(2'h2)) \n \\stg2_target_r[8]_i_5 \n (.I0(p_0_in0_carry__0_n_7),\n .O(\\stg2_target_r_reg[8]_0 [0]));\n FDRE \\stg2_target_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_po_fine_cnt_reg[23] [0]),\n .Q(\\stg2_target_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\stg2_target_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(stg2_target_ns),\n .Q(\\stg2_target_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE \\stg2_target_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_po_fine_cnt_reg[23] [1]),\n .Q(\\stg2_target_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE \\stg2_target_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_po_fine_cnt_reg[23] [2]),\n .Q(\\stg2_target_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE \\stg2_target_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_po_fine_cnt_reg[23] [3]),\n .Q(\\stg2_target_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE \\stg2_target_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_po_fine_cnt_reg[23] [4]),\n .Q(\\stg2_target_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE \\stg2_target_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_po_fine_cnt_reg[23] [5]),\n .Q(\\stg2_target_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE \\stg2_target_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_po_fine_cnt_reg[23] [6]),\n .Q(\\stg2_target_r_reg_n_0_[7] ),\n .R(1'b0));\n FDRE \\stg2_target_r_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_po_fine_cnt_reg[23] [7]),\n .Q(p_1_in),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00550F33FF550F33)) \n \\stg3_init_val[0]_i_2 \n (.I0(\\simp_stg3_final_r_reg_n_0_[12] ),\n .I1(\\simp_stg3_final_r_reg_n_0_[0] ),\n .I2(\\simp_stg3_final_r_reg_n_0_[6] ),\n .I3(\\byte_r_reg[0]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\simp_stg3_final_r_reg_n_0_[18] ),\n .O(\\stg3_init_val_reg[0] ));\n LUT6 #(\n .INIT(64'h5500330F55FF330F)) \n \\stg3_init_val[1]_i_2 \n (.I0(\\simp_stg3_final_r_reg_n_0_[19] ),\n .I1(\\simp_stg3_final_r_reg_n_0_[7] ),\n .I2(\\simp_stg3_final_r_reg_n_0_[1] ),\n .I3(\\byte_r_reg[0]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\simp_stg3_final_r_reg_n_0_[13] ),\n .O(\\stg3_init_val_reg[1] ));\n LUT5 #(\n .INIT(32'hFAC00AC0)) \n \\stg3_init_val[2]_i_2 \n (.I0(\\simp_stg3_final_r_reg_n_0_[8] ),\n .I1(\\simp_stg3_final_r_reg_n_0_[14] ),\n .I2(\\byte_r_reg[1] ),\n .I3(\\byte_r_reg[0]_0 ),\n .I4(\\simp_stg3_final_r_reg_n_0_[20] ),\n .O(\\stg3_init_val_reg[2] ));\n LUT6 #(\n .INIT(64'h7747FFFF7444FFFF)) \n \\stg3_init_val[3]_i_1 \n (.I0(\\stg3_init_val[3]_i_2_n_0 ),\n .I1(\\byte_r_reg[0]_0 ),\n .I2(\\byte_r_reg[1] ),\n .I3(\\simp_stg3_final_r_reg_n_0_[15] ),\n .I4(oclkdelay_calib_done_r_reg),\n .I5(\\simp_stg3_final_r_reg_n_0_[3] ),\n .O(\\stg3_init_val_reg[3] ));\n LUT5 #(\n .INIT(32'h0407C4C7)) \n \\stg3_init_val[3]_i_2 \n (.I0(\\simp_stg3_final_r_reg_n_0_[9] ),\n .I1(\\byte_r_reg[0]_0 ),\n .I2(\\byte_r_reg[1] ),\n .I3(\\simp_stg3_final_r_reg_n_0_[5] ),\n .I4(\\simp_stg3_final_r_reg_n_0_[21] ),\n .O(\\stg3_init_val[3]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hF0AC00AC)) \n \\stg3_init_val[4]_i_2 \n (.I0(\\simp_stg3_final_r_reg_n_0_[10] ),\n .I1(\\simp_stg3_final_r_reg_n_0_[4] ),\n .I2(\\byte_r_reg[0]_0 ),\n .I3(\\byte_r_reg[1] ),\n .I4(\\simp_stg3_final_r_reg_n_0_[22] ),\n .O(\\stg3_init_val_reg[4] ));\n LUT6 #(\n .INIT(64'h0FDD00CC0FDDFFCC)) \n \\stg3_init_val[5]_i_2 \n (.I0(\\simp_stg3_final_r_reg_n_0_[17] ),\n .I1(\\stg3_init_val[3]_i_2_n_0 ),\n .I2(\\simp_stg3_final_r_reg_n_0_[23] ),\n .I3(\\byte_r_reg[0]_0 ),\n .I4(\\byte_r_reg[1] ),\n .I5(\\simp_stg3_final_r_reg_n_0_[11] ),\n .O(\\stg3_init_val_reg[5] ));\n LUT2 #(\n .INIT(4'h2)) \n \\stg3_r[0]_i_1 \n (.I0(\\two_r_reg[1]_0 ),\n .I1(Q[0]),\n .O(stg3_ns[0]));\n (* SOFT_HLUTNM = \"soft_lutpair402\" *) \n LUT4 #(\n .INIT(16'hD714)) \n \\stg3_r[1]_i_1 \n (.I0(\\stg3_r[5]_i_6_n_0 ),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(ocd2stg3_dec),\n .O(stg3_ns[1]));\n (* SOFT_HLUTNM = \"soft_lutpair402\" *) \n LUT5 #(\n .INIT(32'h8CC2BEEE)) \n \\stg3_r[2]_i_1 \n (.I0(\\stg3_r[5]_i_6_n_0 ),\n .I1(Q[2]),\n .I2(Q[0]),\n .I3(Q[1]),\n .I4(ocd2stg3_dec),\n .O(stg3_ns[2]));\n LUT6 #(\n .INIT(64'h8CCCCCC2BEEEEEEE)) \n \\stg3_r[3]_i_1 \n (.I0(\\stg3_r[5]_i_6_n_0 ),\n .I1(Q[3]),\n .I2(Q[2]),\n .I3(Q[1]),\n .I4(Q[0]),\n .I5(ocd2stg3_dec),\n .O(stg3_ns[3]));\n LUT6 #(\n .INIT(64'hFF6A0000FF6AFF6A)) \n \\stg3_r[4]_i_1 \n (.I0(Q[4]),\n .I1(Q[3]),\n .I2(\\stg3_r[5]_i_5_n_0 ),\n .I3(\\stg3_r[5]_i_6_n_0 ),\n .I4(D[4]),\n .I5(ocd2stg3_dec),\n .O(stg3_ns[4]));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAAAAAB)) \n \\stg3_r[5]_i_1 \n (.I0(\\two_r_reg[1]_0 ),\n .I1(sm_r[0]),\n .I2(\\stg2_r_reg[0]_0 ),\n .I3(rstdiv0_sync_r1_reg_rep__26),\n .I4(sm_r[3]),\n .I5(sm_r[2]),\n .O(\\stg3_r[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hEEEE0EEEEEEEEEEE)) \n \\stg3_r[5]_i_10 \n (.I0(scan_right_r_reg),\n .I1(samp_done_r_reg),\n .I2(po_done_r),\n .I3(\\stg2_r_reg[0]_0 ),\n .I4(E),\n .I5(inc_po_r),\n .O(\\stg3_r[5]_i_10_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFFFEF)) \n \\stg3_r[5]_i_11 \n (.I0(rstdiv0_sync_r1_reg_rep__26),\n .I1(sm_r[0]),\n .I2(sm_r[3]),\n .I3(\\stg2_r_reg[0]_0 ),\n .I4(sm_r[2]),\n .O(\\stg3_r[5]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'h0080AAAA00800080)) \n \\stg3_r[5]_i_12 \n (.I0(\\stg3_r[5]_i_9_n_0 ),\n .I1(cmplx_samples_done_r_i_3_n_0),\n .I2(dec_po_r),\n .I3(inc_po_r),\n .I4(samp_done_r_reg),\n .I5(scan_right_r_reg),\n .O(\\stg3_r[5]_i_12_n_0 ));\n LUT6 #(\n .INIT(64'h006AFFFF006A006A)) \n \\stg3_r[5]_i_2 \n (.I0(Q[5]),\n .I1(\\stg3_r[5]_i_4_n_0 ),\n .I2(\\stg3_r[5]_i_5_n_0 ),\n .I3(\\stg3_r[5]_i_6_n_0 ),\n .I4(\\stg3_r[5]_i_7_n_0 ),\n .I5(ocd2stg3_dec),\n .O(stg3_ns[5]));\n LUT2 #(\n .INIT(4'hB)) \n \\stg3_r[5]_i_3 \n (.I0(ocd2stg3_dec),\n .I1(\\stg3_r[5]_i_6_n_0 ),\n .O(\\two_r_reg[1]_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\stg3_r[5]_i_4 \n (.I0(Q[4]),\n .I1(Q[3]),\n .O(\\stg3_r[5]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair418\" *) \n LUT3 #(\n .INIT(8'h80)) \n \\stg3_r[5]_i_5 \n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(Q[2]),\n .O(\\stg3_r[5]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hDDDDDDDDD0DDDDDD)) \n \\stg3_r[5]_i_6 \n (.I0(\\stg3_r[5]_i_9_n_0 ),\n .I1(\\stg3_r[5]_i_10_n_0 ),\n .I2(\\stg3_r[5]_i_11_n_0 ),\n .I3(poc_backup_r),\n .I4(po_rdy),\n .I5(E),\n .O(\\stg3_r[5]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h5555555555555556)) \n \\stg3_r[5]_i_7 \n (.I0(Q[5]),\n .I1(Q[4]),\n .I2(Q[2]),\n .I3(Q[1]),\n .I4(Q[0]),\n .I5(Q[3]),\n .O(\\stg3_r[5]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAAAEAA)) \n \\stg3_r[5]_i_8 \n (.I0(\\stg3_r[5]_i_12_n_0 ),\n .I1(sm_r[2]),\n .I2(sm_r[3]),\n .I3(\\stg2_r_reg[0]_0 ),\n .I4(sm_r[0]),\n .I5(rstdiv0_sync_r1_reg_rep__26_0),\n .O(ocd2stg3_dec));\n LUT4 #(\n .INIT(16'h0100)) \n \\stg3_r[5]_i_9 \n (.I0(rstdiv0_sync_r1_reg_rep__26),\n .I1(sm_r[3]),\n .I2(sm_r[2]),\n .I3(sm_r[0]),\n .O(\\stg3_r[5]_i_9_n_0 ));\n FDRE \\stg3_r_reg[0] \n (.C(CLK),\n .CE(\\stg3_r[5]_i_1_n_0 ),\n .D(stg3_ns[0]),\n .Q(Q[0]),\n .R(1'b0));\n FDRE \\stg3_r_reg[1] \n (.C(CLK),\n .CE(\\stg3_r[5]_i_1_n_0 ),\n .D(stg3_ns[1]),\n .Q(Q[1]),\n .R(1'b0));\n FDRE \\stg3_r_reg[2] \n (.C(CLK),\n .CE(\\stg3_r[5]_i_1_n_0 ),\n .D(stg3_ns[2]),\n .Q(Q[2]),\n .R(1'b0));\n FDRE \\stg3_r_reg[3] \n (.C(CLK),\n .CE(\\stg3_r[5]_i_1_n_0 ),\n .D(stg3_ns[3]),\n .Q(Q[3]),\n .R(1'b0));\n FDRE \\stg3_r_reg[4] \n (.C(CLK),\n .CE(\\stg3_r[5]_i_1_n_0 ),\n .D(stg3_ns[4]),\n .Q(Q[4]),\n .R(1'b0));\n FDRE \\stg3_r_reg[5] \n (.C(CLK),\n .CE(\\stg3_r[5]_i_1_n_0 ),\n .D(stg3_ns[5]),\n .Q(Q[5]),\n .R(1'b0));\n LUT3 #(\n .INIT(8'h1C)) \n \\two_r[0]_i_1 \n (.I0(\\two_r_reg[1]_0 ),\n .I1(\\stg2_r[8]_i_3_n_0 ),\n .I2(two_r[0]),\n .O(\\two_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h505050501C505050)) \n \\two_r[1]_i_1 \n (.I0(\\two_r_reg[1]_0 ),\n .I1(two_r[0]),\n .I2(two_r[1]),\n .I3(\\two_r[1]_i_2_n_0 ),\n .I4(po_rdy),\n .I5(po_done_r),\n .O(\\two_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair398\" *) \n LUT5 #(\n .INIT(32'hFCFFFFEF)) \n \\two_r[1]_i_2 \n (.I0(sm_r[2]),\n .I1(rstdiv0_sync_r1_reg_rep__26),\n .I2(sm_r[3]),\n .I3(\\stg2_r_reg[0]_0 ),\n .I4(sm_r[0]),\n .O(\\two_r[1]_i_2_n_0 ));\n FDRE \\two_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\two_r[0]_i_1_n_0 ),\n .Q(two_r[0]),\n .R(1'b0));\n FDRE \\two_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\two_r[1]_i_1_n_0 ),\n .Q(two_r[1]),\n .R(1'b0));\n LUT3 #(\n .INIT(8'hF8)) \n up_r_i_1\n (.I0(\\stg3_r[5]_i_6_n_0 ),\n .I1(up_r),\n .I2(ocd2stg3_dec),\n .O(up_r_i_1_n_0));\n FDRE up_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(up_r_i_1_n_0),\n .Q(up_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair423\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\zero2fuzz_r[0]_i_1 \n (.I0(Q[0]),\n .O(D[0]));\n (* SOFT_HLUTNM = \"soft_lutpair423\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\zero2fuzz_r[1]_i_1 \n (.I0(Q[0]),\n .I1(Q[1]),\n .O(D[1]));\n (* SOFT_HLUTNM = \"soft_lutpair418\" *) \n LUT3 #(\n .INIT(8'hA9)) \n \\zero2fuzz_r[2]_i_1 \n (.I0(Q[2]),\n .I1(Q[0]),\n .I2(Q[1]),\n .O(D[2]));\n (* SOFT_HLUTNM = \"soft_lutpair399\" *) \n LUT4 #(\n .INIT(16'hAAA9)) \n \\zero2fuzz_r[3]_i_1 \n (.I0(Q[3]),\n .I1(Q[2]),\n .I2(Q[1]),\n .I3(Q[0]),\n .O(D[3]));\n (* SOFT_HLUTNM = \"soft_lutpair399\" *) \n LUT5 #(\n .INIT(32'hAAAAAAA9)) \n \\zero2fuzz_r[4]_i_1 \n (.I0(Q[4]),\n .I1(Q[3]),\n .I2(Q[0]),\n .I3(Q[1]),\n .I4(Q[2]),\n .O(D[4]));\n LUT6 #(\n .INIT(64'hFFFFFFFE00000001)) \n \\zero2fuzz_r[5]_i_2 \n (.I0(Q[3]),\n .I1(Q[0]),\n .I2(Q[1]),\n .I3(Q[2]),\n .I4(Q[4]),\n .I5(Q[5]),\n .O(D[5]));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_ddr_phy_ocd_samp\n (oclk_calib_resume_level_reg,\n \\samps_r_reg[9]_0 ,\n samp_done,\n oclk_calib_resume_r_reg_0,\n prev_samp_valid_r_reg,\n D,\n \\samps_r_reg[0]_0 ,\n agg_samp_r,\n \\stg3_r_reg[1] ,\n \\rd_victim_sel_r_reg[2]_0 ,\n \\rd_victim_sel_r_reg[1]_0 ,\n \\rd_victim_sel_r_reg[1]_1 ,\n \\oneeighty2fuzz_r_reg[5] ,\n o2f_ns1_out,\n E,\n f2z_ns5_out,\n \\init_state_r_reg[4] ,\n \\init_state_r_reg[5] ,\n \\prev_samp_r_reg[0] ,\n \\prev_samp_r_reg[1] ,\n rstdiv0_sync_r1_reg_rep__10,\n CLK,\n rstdiv0_sync_r1_reg_rep__9,\n samp_done_ns8_out,\n phy_rddata_en_r1_reg,\n rstdiv0_sync_r1_reg_rep__26,\n rstdiv0_sync_r1_reg_rep__25,\n \\sm_r_reg[0]_0 ,\n rd_active_r1,\n prev_samp_valid_r,\n rstdiv0_sync_r1_reg_rep__20,\n \\data_bytes_r_reg[32] ,\n \\data_bytes_r_reg[24] ,\n rd_active_r2,\n \\sm_r_reg[1] ,\n scanning_right_r_reg,\n phy_rddata_en_r1_reg_0,\n reset_scan,\n prev_samp_r,\n f2o_r_reg,\n scanning_right,\n \\init_state_r_reg[0] ,\n prbs_rdlvl_done_reg,\n prech_req_r_reg,\n ocd_prech_req_r_reg,\n \\init_state_r_reg[4]_0 ,\n prbs_rdlvl_done_reg_rep,\n \\rd_victim_sel_r_reg[0]_0 );\n output oclk_calib_resume_level_reg;\n output \\samps_r_reg[9]_0 ;\n output samp_done;\n output oclk_calib_resume_r_reg_0;\n output prev_samp_valid_r_reg;\n output [1:0]D;\n output \\samps_r_reg[0]_0 ;\n output [1:0]agg_samp_r;\n output \\stg3_r_reg[1] ;\n output \\rd_victim_sel_r_reg[2]_0 ;\n output \\rd_victim_sel_r_reg[1]_0 ;\n output \\rd_victim_sel_r_reg[1]_1 ;\n output [0:0]\\oneeighty2fuzz_r_reg[5] ;\n output o2f_ns1_out;\n output [0:0]E;\n output f2z_ns5_out;\n output \\init_state_r_reg[4] ;\n output \\init_state_r_reg[5] ;\n output \\prev_samp_r_reg[0] ;\n output \\prev_samp_r_reg[1] ;\n input rstdiv0_sync_r1_reg_rep__10;\n input CLK;\n input rstdiv0_sync_r1_reg_rep__9;\n input samp_done_ns8_out;\n input phy_rddata_en_r1_reg;\n input rstdiv0_sync_r1_reg_rep__26;\n input rstdiv0_sync_r1_reg_rep__25;\n input [0:0]\\sm_r_reg[0]_0 ;\n input rd_active_r1;\n input prev_samp_valid_r;\n input rstdiv0_sync_r1_reg_rep__20;\n input \\data_bytes_r_reg[32] ;\n input \\data_bytes_r_reg[24] ;\n input rd_active_r2;\n input [0:0]\\sm_r_reg[1] ;\n input scanning_right_r_reg;\n input phy_rddata_en_r1_reg_0;\n input reset_scan;\n input [1:0]prev_samp_r;\n input f2o_r_reg;\n input scanning_right;\n input \\init_state_r_reg[0] ;\n input prbs_rdlvl_done_reg;\n input prech_req_r_reg;\n input ocd_prech_req_r_reg;\n input [0:0]\\init_state_r_reg[4]_0 ;\n input prbs_rdlvl_done_reg_rep;\n input [0:0]\\rd_victim_sel_r_reg[0]_0 ;\n\n wire CLK;\n wire [1:0]D;\n wire [0:0]E;\n wire agg_samp_ns;\n wire [1:0]agg_samp_r;\n wire \\agg_samp_r[0]_i_1_n_0 ;\n wire \\agg_samp_r[1]_i_1_n_0 ;\n wire \\data_bytes_r_reg[24] ;\n wire \\data_bytes_r_reg[32] ;\n wire data_cnt_ns;\n wire [7:0]data_cnt_r;\n wire \\data_cnt_r[2]_i_1_n_0 ;\n wire \\data_cnt_r[3]_i_1_n_0 ;\n wire \\data_cnt_r[4]_i_1_n_0 ;\n wire \\data_cnt_r[6]_i_3_n_0 ;\n wire \\data_cnt_r[7]_i_1_n_0 ;\n wire \\data_cnt_r[7]_i_2_n_0 ;\n wire f2o_r_reg;\n wire f2z_ns5_out;\n wire \\fuzz2zero_r[5]_i_3_n_0 ;\n wire \\init_state_r_reg[0] ;\n wire \\init_state_r_reg[4] ;\n wire [0:0]\\init_state_r_reg[4]_0 ;\n wire \\init_state_r_reg[5] ;\n wire o2f_ns1_out;\n wire ocd_prech_req_r_reg;\n wire oclk_calib_resume_level_reg;\n wire oclk_calib_resume_r_i_1_n_0;\n wire oclk_calib_resume_r_i_6_n_0;\n wire oclk_calib_resume_r_reg_0;\n wire [0:0]\\oneeighty2fuzz_r_reg[5] ;\n wire oneeighty_ge_thresh;\n wire oneeighty_ge_thresh_carry__0_i_1_n_0;\n wire oneeighty_ge_thresh_carry_i_1_n_0;\n wire oneeighty_ge_thresh_carry_i_2_n_0;\n wire oneeighty_ge_thresh_carry_i_3_n_0;\n wire oneeighty_ge_thresh_carry_i_4_n_0;\n wire oneeighty_ge_thresh_carry_i_5_n_0;\n wire oneeighty_ge_thresh_carry_i_6_n_0;\n wire oneeighty_ge_thresh_carry_n_0;\n wire oneeighty_ge_thresh_carry_n_1;\n wire oneeighty_ge_thresh_carry_n_2;\n wire oneeighty_ge_thresh_carry_n_3;\n wire oneeighty_le_half_thresh;\n wire oneeighty_le_half_thresh_carry__0_i_1_n_0;\n wire oneeighty_le_half_thresh_carry_i_1_n_0;\n wire oneeighty_le_half_thresh_carry_i_2_n_0;\n wire oneeighty_le_half_thresh_carry_i_3_n_0;\n wire oneeighty_le_half_thresh_carry_i_4_n_0;\n wire oneeighty_le_half_thresh_carry_i_5_n_0;\n wire oneeighty_le_half_thresh_carry_i_6_n_0;\n wire oneeighty_le_half_thresh_carry_i_7_n_0;\n wire oneeighty_le_half_thresh_carry_n_0;\n wire oneeighty_le_half_thresh_carry_n_1;\n wire oneeighty_le_half_thresh_carry_n_2;\n wire oneeighty_le_half_thresh_carry_n_3;\n wire oneeighty_ns;\n wire \\oneeighty_r[0]_i_1_n_0 ;\n wire \\oneeighty_r[6]_i_2_n_0 ;\n wire \\oneeighty_r[9]_i_3_n_0 ;\n wire [9:0]oneeighty_r_reg__0;\n wire [6:0]p_0_in;\n wire p_0_in11_in;\n wire [9:1]p_0_in__1;\n wire [9:1]p_0_in__2;\n wire phy_rddata_en_r1_reg;\n wire phy_rddata_en_r1_reg_0;\n wire prbs_rdlvl_done_reg;\n wire prbs_rdlvl_done_reg_rep;\n wire prech_req_r_reg;\n wire [1:0]prev_samp_r;\n wire \\prev_samp_r_reg[0] ;\n wire \\prev_samp_r_reg[1] ;\n wire prev_samp_valid_r;\n wire prev_samp_valid_r_reg;\n wire rd_active_r1;\n wire rd_active_r2;\n wire \\rd_victim_sel_r[0]_i_1_n_0 ;\n wire \\rd_victim_sel_r[1]_i_1_n_0 ;\n wire \\rd_victim_sel_r[2]_i_1_n_0 ;\n wire [0:0]\\rd_victim_sel_r_reg[0]_0 ;\n wire \\rd_victim_sel_r_reg[1]_0 ;\n wire \\rd_victim_sel_r_reg[1]_1 ;\n wire \\rd_victim_sel_r_reg[2]_0 ;\n wire reset_scan;\n wire rstdiv0_sync_r1_reg_rep__10;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__25;\n wire rstdiv0_sync_r1_reg_rep__26;\n wire rstdiv0_sync_r1_reg_rep__9;\n wire samp_done;\n wire samp_done_ns8_out;\n wire samp_done_ns9_in;\n wire samp_done_r_i_1_n_0;\n wire \\samp_result_r_reg_n_0_[0] ;\n wire samps_ns;\n wire [9:0]samps_r;\n wire [8:0]samps_r0;\n wire \\samps_r[1]_i_1_n_0 ;\n wire \\samps_r[4]_i_1_n_0 ;\n wire \\samps_r[5]_i_1_n_0 ;\n wire \\samps_r[7]_i_1_n_0 ;\n wire \\samps_r[8]_i_3_n_0 ;\n wire \\samps_r[8]_i_4_n_0 ;\n wire \\samps_r[8]_i_5_n_0 ;\n wire \\samps_r[9]_i_1_n_0 ;\n wire \\samps_r[9]_i_2_n_0 ;\n wire \\samps_r[9]_i_3_n_0 ;\n wire \\samps_r_reg[0]_0 ;\n wire \\samps_r_reg[9]_0 ;\n wire scanning_right;\n wire scanning_right_r_reg;\n wire \\sm_r[0]_i_1__0_n_0 ;\n wire [0:0]\\sm_r_reg[0]_0 ;\n wire [0:0]\\sm_r_reg[1] ;\n wire \\stg3_r_reg[1] ;\n wire \\u_ocd_edge/samp_valid ;\n wire zero_ge_thresh;\n wire zero_ge_thresh_carry__0_i_1_n_0;\n wire zero_ge_thresh_carry_i_1_n_0;\n wire zero_ge_thresh_carry_i_2_n_0;\n wire zero_ge_thresh_carry_i_3_n_0;\n wire zero_ge_thresh_carry_i_4_n_0;\n wire zero_ge_thresh_carry_i_5_n_0;\n wire zero_ge_thresh_carry_i_6_n_0;\n wire zero_ge_thresh_carry_n_0;\n wire zero_ge_thresh_carry_n_1;\n wire zero_ge_thresh_carry_n_2;\n wire zero_ge_thresh_carry_n_3;\n wire zero_le_half_thresh;\n wire zero_le_half_thresh_carry__0_i_1_n_0;\n wire zero_le_half_thresh_carry_i_1_n_0;\n wire zero_le_half_thresh_carry_i_2_n_0;\n wire zero_le_half_thresh_carry_i_3_n_0;\n wire zero_le_half_thresh_carry_i_4_n_0;\n wire zero_le_half_thresh_carry_i_5_n_0;\n wire zero_le_half_thresh_carry_i_6_n_0;\n wire zero_le_half_thresh_carry_i_7_n_0;\n wire zero_le_half_thresh_carry_n_0;\n wire zero_le_half_thresh_carry_n_1;\n wire zero_le_half_thresh_carry_n_2;\n wire zero_le_half_thresh_carry_n_3;\n wire \\zero_r[0]_i_1_n_0 ;\n wire \\zero_r[6]_i_2_n_0 ;\n wire \\zero_r[9]_i_8_n_0 ;\n wire [9:0]zero_r_reg__0;\n wire [3:0]NLW_oneeighty_ge_thresh_carry_O_UNCONNECTED;\n wire [3:1]NLW_oneeighty_ge_thresh_carry__0_CO_UNCONNECTED;\n wire [3:0]NLW_oneeighty_ge_thresh_carry__0_O_UNCONNECTED;\n wire [3:0]NLW_oneeighty_le_half_thresh_carry_O_UNCONNECTED;\n wire [3:1]NLW_oneeighty_le_half_thresh_carry__0_CO_UNCONNECTED;\n wire [3:0]NLW_oneeighty_le_half_thresh_carry__0_O_UNCONNECTED;\n wire [3:0]NLW_zero_ge_thresh_carry_O_UNCONNECTED;\n wire [3:1]NLW_zero_ge_thresh_carry__0_CO_UNCONNECTED;\n wire [3:0]NLW_zero_ge_thresh_carry__0_O_UNCONNECTED;\n wire [3:0]NLW_zero_le_half_thresh_carry_O_UNCONNECTED;\n wire [3:1]NLW_zero_le_half_thresh_carry__0_CO_UNCONNECTED;\n wire [3:0]NLW_zero_le_half_thresh_carry__0_O_UNCONNECTED;\n\n LUT6 #(\n .INIT(64'hFFFFFFF1F1F1FFF1)) \n \\agg_samp_r[0]_i_1 \n (.I0(\\samps_r_reg[9]_0 ),\n .I1(rstdiv0_sync_r1_reg_rep__20),\n .I2(\\samps_r_reg[0]_0 ),\n .I3(agg_samp_r[0]),\n .I4(agg_samp_ns),\n .I5(\\data_bytes_r_reg[24] ),\n .O(\\agg_samp_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFF1F1F1FFF1)) \n \\agg_samp_r[1]_i_1 \n (.I0(\\samps_r_reg[9]_0 ),\n .I1(rstdiv0_sync_r1_reg_rep__20),\n .I2(\\samps_r_reg[0]_0 ),\n .I3(agg_samp_r[1]),\n .I4(agg_samp_ns),\n .I5(\\data_bytes_r_reg[32] ),\n .O(\\agg_samp_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h4444444444444440)) \n \\agg_samp_r[1]_i_2 \n (.I0(rstdiv0_sync_r1_reg_rep__25),\n .I1(phy_rddata_en_r1_reg),\n .I2(\\rd_victim_sel_r_reg[2]_0 ),\n .I3(\\rd_victim_sel_r_reg[1]_0 ),\n .I4(\\rd_victim_sel_r_reg[1]_1 ),\n .I5(oclk_calib_resume_r_reg_0),\n .O(agg_samp_ns));\n FDRE \\agg_samp_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\agg_samp_r[0]_i_1_n_0 ),\n .Q(agg_samp_r[0]),\n .R(1'b0));\n FDRE \\agg_samp_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\agg_samp_r[1]_i_1_n_0 ),\n .Q(agg_samp_r[1]),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair435\" *) \n LUT3 #(\n .INIT(8'h7F)) \n \\data_cnt_r[0]_i_1 \n (.I0(data_cnt_r[0]),\n .I1(\\samps_r_reg[9]_0 ),\n .I2(oclk_calib_resume_r_reg_0),\n .O(p_0_in[0]));\n (* SOFT_HLUTNM = \"soft_lutpair435\" *) \n LUT3 #(\n .INIT(8'h82)) \n \\data_cnt_r[1]_i_1 \n (.I0(\\samps_r_reg[9]_0 ),\n .I1(data_cnt_r[1]),\n .I2(data_cnt_r[0]),\n .O(p_0_in[1]));\n (* SOFT_HLUTNM = \"soft_lutpair431\" *) \n LUT3 #(\n .INIT(8'hA9)) \n \\data_cnt_r[2]_i_1 \n (.I0(data_cnt_r[2]),\n .I1(data_cnt_r[1]),\n .I2(data_cnt_r[0]),\n .O(\\data_cnt_r[2]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hAAA9)) \n \\data_cnt_r[3]_i_1 \n (.I0(data_cnt_r[3]),\n .I1(data_cnt_r[2]),\n .I2(data_cnt_r[1]),\n .I3(data_cnt_r[0]),\n .O(\\data_cnt_r[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair428\" *) \n LUT5 #(\n .INIT(32'hAAAAAAA9)) \n \\data_cnt_r[4]_i_1 \n (.I0(data_cnt_r[4]),\n .I1(data_cnt_r[3]),\n .I2(data_cnt_r[0]),\n .I3(data_cnt_r[1]),\n .I4(data_cnt_r[2]),\n .O(\\data_cnt_r[4]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair432\" *) \n LUT3 #(\n .INIT(8'h28)) \n \\data_cnt_r[5]_i_1 \n (.I0(\\samps_r_reg[9]_0 ),\n .I1(\\data_cnt_r[6]_i_3_n_0 ),\n .I2(data_cnt_r[5]),\n .O(p_0_in[5]));\n LUT3 #(\n .INIT(8'h31)) \n \\data_cnt_r[6]_i_1 \n (.I0(\\samps_r_reg[9]_0 ),\n .I1(rstdiv0_sync_r1_reg_rep__25),\n .I2(phy_rddata_en_r1_reg),\n .O(data_cnt_ns));\n (* SOFT_HLUTNM = \"soft_lutpair432\" *) \n LUT4 #(\n .INIT(16'h8A20)) \n \\data_cnt_r[6]_i_2 \n (.I0(\\samps_r_reg[9]_0 ),\n .I1(data_cnt_r[5]),\n .I2(\\data_cnt_r[6]_i_3_n_0 ),\n .I3(data_cnt_r[6]),\n .O(p_0_in[6]));\n (* SOFT_HLUTNM = \"soft_lutpair428\" *) \n LUT5 #(\n .INIT(32'h00000001)) \n \\data_cnt_r[6]_i_3 \n (.I0(data_cnt_r[3]),\n .I1(data_cnt_r[0]),\n .I2(data_cnt_r[1]),\n .I3(data_cnt_r[2]),\n .I4(data_cnt_r[4]),\n .O(\\data_cnt_r[6]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'h0323)) \n \\data_cnt_r[7]_i_1 \n (.I0(phy_rddata_en_r1_reg),\n .I1(rstdiv0_sync_r1_reg_rep__25),\n .I2(\\samps_r_reg[9]_0 ),\n .I3(oclk_calib_resume_r_reg_0),\n .O(\\data_cnt_r[7]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hAAA6)) \n \\data_cnt_r[7]_i_2 \n (.I0(data_cnt_r[7]),\n .I1(\\data_cnt_r[6]_i_3_n_0 ),\n .I2(data_cnt_r[5]),\n .I3(data_cnt_r[6]),\n .O(\\data_cnt_r[7]_i_2_n_0 ));\n FDRE \\data_cnt_r_reg[0] \n (.C(CLK),\n .CE(data_cnt_ns),\n .D(p_0_in[0]),\n .Q(data_cnt_r[0]),\n .R(1'b0));\n FDRE \\data_cnt_r_reg[1] \n (.C(CLK),\n .CE(data_cnt_ns),\n .D(p_0_in[1]),\n .Q(data_cnt_r[1]),\n .R(1'b0));\n FDRE \\data_cnt_r_reg[2] \n (.C(CLK),\n .CE(data_cnt_ns),\n .D(\\data_cnt_r[2]_i_1_n_0 ),\n .Q(data_cnt_r[2]),\n .R(\\data_cnt_r[7]_i_1_n_0 ));\n FDRE \\data_cnt_r_reg[3] \n (.C(CLK),\n .CE(data_cnt_ns),\n .D(\\data_cnt_r[3]_i_1_n_0 ),\n .Q(data_cnt_r[3]),\n .R(\\data_cnt_r[7]_i_1_n_0 ));\n FDRE \\data_cnt_r_reg[4] \n (.C(CLK),\n .CE(data_cnt_ns),\n .D(\\data_cnt_r[4]_i_1_n_0 ),\n .Q(data_cnt_r[4]),\n .R(\\data_cnt_r[7]_i_1_n_0 ));\n FDRE \\data_cnt_r_reg[5] \n (.C(CLK),\n .CE(data_cnt_ns),\n .D(p_0_in[5]),\n .Q(data_cnt_r[5]),\n .R(1'b0));\n FDRE \\data_cnt_r_reg[6] \n (.C(CLK),\n .CE(data_cnt_ns),\n .D(p_0_in[6]),\n .Q(data_cnt_r[6]),\n .R(1'b0));\n FDRE \\data_cnt_r_reg[7] \n (.C(CLK),\n .CE(data_cnt_ns),\n .D(\\data_cnt_r[7]_i_2_n_0 ),\n .Q(data_cnt_r[7]),\n .R(\\data_cnt_r[7]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\fuzz2zero_r[5]_i_1 \n (.I0(f2z_ns5_out),\n .I1(reset_scan),\n .O(E));\n LUT6 #(\n .INIT(64'h0080808000000000)) \n \\fuzz2zero_r[5]_i_2 \n (.I0(\\fuzz2zero_r[5]_i_3_n_0 ),\n .I1(\\u_ocd_edge/samp_valid ),\n .I2(prev_samp_valid_r),\n .I3(f2o_r_reg),\n .I4(prev_samp_r[1]),\n .I5(D[0]),\n .O(f2z_ns5_out));\n LUT3 #(\n .INIT(8'h04)) \n \\fuzz2zero_r[5]_i_3 \n (.I0(D[1]),\n .I1(scanning_right),\n .I2(prev_samp_r[0]),\n .O(\\fuzz2zero_r[5]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h1111111111111110)) \n \\init_state_r[4]_i_36 \n (.I0(\\init_state_r_reg[0] ),\n .I1(oclk_calib_resume_level_reg),\n .I2(prbs_rdlvl_done_reg),\n .I3(prech_req_r_reg),\n .I4(ocd_prech_req_r_reg),\n .I5(\\init_state_r_reg[4]_0 ),\n .O(\\init_state_r_reg[4] ));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\init_state_r[5]_i_47 \n (.I0(oclk_calib_resume_level_reg),\n .I1(ocd_prech_req_r_reg),\n .I2(prech_req_r_reg),\n .I3(prbs_rdlvl_done_reg_rep),\n .O(\\init_state_r_reg[5] ));\n LUT5 #(\n .INIT(32'hAAAABAAA)) \n oclk_calib_resume_r_i_1\n (.I0(samp_done_ns8_out),\n .I1(oclk_calib_resume_r_reg_0),\n .I2(phy_rddata_en_r1_reg),\n .I3(\\samps_r_reg[9]_0 ),\n .I4(samp_done_ns9_in),\n .O(oclk_calib_resume_r_i_1_n_0));\n LUT5 #(\n .INIT(32'hFFFFFEFF)) \n oclk_calib_resume_r_i_3\n (.I0(data_cnt_r[7]),\n .I1(data_cnt_r[4]),\n .I2(data_cnt_r[3]),\n .I3(data_cnt_r[0]),\n .I4(oclk_calib_resume_r_i_6_n_0),\n .O(oclk_calib_resume_r_reg_0));\n LUT6 #(\n .INIT(64'hAAAAAAABAAAAAAAA)) \n oclk_calib_resume_r_i_4\n (.I0(samp_done),\n .I1(oclk_calib_resume_r_reg_0),\n .I2(\\rd_victim_sel_r_reg[1]_1 ),\n .I3(\\rd_victim_sel_r_reg[1]_0 ),\n .I4(\\rd_victim_sel_r_reg[2]_0 ),\n .I5(\\samps_r[8]_i_3_n_0 ),\n .O(samp_done_ns9_in));\n (* SOFT_HLUTNM = \"soft_lutpair431\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n oclk_calib_resume_r_i_6\n (.I0(data_cnt_r[6]),\n .I1(data_cnt_r[5]),\n .I2(data_cnt_r[1]),\n .I3(data_cnt_r[2]),\n .O(oclk_calib_resume_r_i_6_n_0));\n FDRE oclk_calib_resume_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(oclk_calib_resume_r_i_1_n_0),\n .Q(oclk_calib_resume_level_reg),\n .R(rstdiv0_sync_r1_reg_rep__10));\n LUT2 #(\n .INIT(4'h2)) \n \\oneeighty2fuzz_r[5]_i_1 \n (.I0(o2f_ns1_out),\n .I1(reset_scan),\n .O(\\oneeighty2fuzz_r_reg[5] ));\n LUT6 #(\n .INIT(64'h8000800000008000)) \n \\oneeighty2fuzz_r[5]_i_2 \n (.I0(\\fuzz2zero_r[5]_i_3_n_0 ),\n .I1(\\u_ocd_edge/samp_valid ),\n .I2(prev_samp_valid_r),\n .I3(prev_samp_r[1]),\n .I4(D[0]),\n .I5(f2o_r_reg),\n .O(o2f_ns1_out));\n CARRY4 oneeighty_ge_thresh_carry\n (.CI(1'b0),\n .CO({oneeighty_ge_thresh_carry_n_0,oneeighty_ge_thresh_carry_n_1,oneeighty_ge_thresh_carry_n_2,oneeighty_ge_thresh_carry_n_3}),\n .CYINIT(1'b1),\n .DI({1'b0,oneeighty_ge_thresh_carry_i_1_n_0,oneeighty_r_reg__0[3],oneeighty_ge_thresh_carry_i_2_n_0}),\n .O(NLW_oneeighty_ge_thresh_carry_O_UNCONNECTED[3:0]),\n .S({oneeighty_ge_thresh_carry_i_3_n_0,oneeighty_ge_thresh_carry_i_4_n_0,oneeighty_ge_thresh_carry_i_5_n_0,oneeighty_ge_thresh_carry_i_6_n_0}));\n CARRY4 oneeighty_ge_thresh_carry__0\n (.CI(oneeighty_ge_thresh_carry_n_0),\n .CO({NLW_oneeighty_ge_thresh_carry__0_CO_UNCONNECTED[3:1],oneeighty_ge_thresh}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,oneeighty_r_reg__0[9]}),\n .O(NLW_oneeighty_ge_thresh_carry__0_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,1'b0,oneeighty_ge_thresh_carry__0_i_1_n_0}));\n LUT2 #(\n .INIT(4'h2)) \n oneeighty_ge_thresh_carry__0_i_1\n (.I0(oneeighty_r_reg__0[8]),\n .I1(oneeighty_r_reg__0[9]),\n .O(oneeighty_ge_thresh_carry__0_i_1_n_0));\n LUT2 #(\n .INIT(4'h8)) \n oneeighty_ge_thresh_carry_i_1\n (.I0(oneeighty_r_reg__0[4]),\n .I1(oneeighty_r_reg__0[5]),\n .O(oneeighty_ge_thresh_carry_i_1_n_0));\n LUT2 #(\n .INIT(4'h8)) \n oneeighty_ge_thresh_carry_i_2\n (.I0(oneeighty_r_reg__0[1]),\n .I1(oneeighty_r_reg__0[0]),\n .O(oneeighty_ge_thresh_carry_i_2_n_0));\n LUT2 #(\n .INIT(4'h8)) \n oneeighty_ge_thresh_carry_i_3\n (.I0(oneeighty_r_reg__0[7]),\n .I1(oneeighty_r_reg__0[6]),\n .O(oneeighty_ge_thresh_carry_i_3_n_0));\n LUT2 #(\n .INIT(4'h2)) \n oneeighty_ge_thresh_carry_i_4\n (.I0(oneeighty_r_reg__0[5]),\n .I1(oneeighty_r_reg__0[4]),\n .O(oneeighty_ge_thresh_carry_i_4_n_0));\n LUT2 #(\n .INIT(4'h2)) \n oneeighty_ge_thresh_carry_i_5\n (.I0(oneeighty_r_reg__0[2]),\n .I1(oneeighty_r_reg__0[3]),\n .O(oneeighty_ge_thresh_carry_i_5_n_0));\n LUT2 #(\n .INIT(4'h2)) \n oneeighty_ge_thresh_carry_i_6\n (.I0(oneeighty_r_reg__0[1]),\n .I1(oneeighty_r_reg__0[0]),\n .O(oneeighty_ge_thresh_carry_i_6_n_0));\n CARRY4 oneeighty_le_half_thresh_carry\n (.CI(1'b0),\n .CO({oneeighty_le_half_thresh_carry_n_0,oneeighty_le_half_thresh_carry_n_1,oneeighty_le_half_thresh_carry_n_2,oneeighty_le_half_thresh_carry_n_3}),\n .CYINIT(1'b1),\n .DI({oneeighty_le_half_thresh_carry_i_1_n_0,oneeighty_le_half_thresh_carry_i_2_n_0,1'b0,oneeighty_le_half_thresh_carry_i_3_n_0}),\n .O(NLW_oneeighty_le_half_thresh_carry_O_UNCONNECTED[3:0]),\n .S({oneeighty_le_half_thresh_carry_i_4_n_0,oneeighty_le_half_thresh_carry_i_5_n_0,oneeighty_le_half_thresh_carry_i_6_n_0,oneeighty_le_half_thresh_carry_i_7_n_0}));\n CARRY4 oneeighty_le_half_thresh_carry__0\n (.CI(oneeighty_le_half_thresh_carry_n_0),\n .CO({NLW_oneeighty_le_half_thresh_carry__0_CO_UNCONNECTED[3:1],oneeighty_le_half_thresh}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(NLW_oneeighty_le_half_thresh_carry__0_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,1'b0,oneeighty_le_half_thresh_carry__0_i_1_n_0}));\n LUT2 #(\n .INIT(4'h1)) \n oneeighty_le_half_thresh_carry__0_i_1\n (.I0(oneeighty_r_reg__0[8]),\n .I1(oneeighty_r_reg__0[9]),\n .O(oneeighty_le_half_thresh_carry__0_i_1_n_0));\n LUT2 #(\n .INIT(4'h7)) \n oneeighty_le_half_thresh_carry_i_1\n (.I0(oneeighty_r_reg__0[6]),\n .I1(oneeighty_r_reg__0[7]),\n .O(oneeighty_le_half_thresh_carry_i_1_n_0));\n LUT2 #(\n .INIT(4'h7)) \n oneeighty_le_half_thresh_carry_i_2\n (.I0(oneeighty_r_reg__0[5]),\n .I1(oneeighty_r_reg__0[4]),\n .O(oneeighty_le_half_thresh_carry_i_2_n_0));\n LUT2 #(\n .INIT(4'h7)) \n oneeighty_le_half_thresh_carry_i_3\n (.I0(oneeighty_r_reg__0[0]),\n .I1(oneeighty_r_reg__0[1]),\n .O(oneeighty_le_half_thresh_carry_i_3_n_0));\n LUT2 #(\n .INIT(4'h8)) \n oneeighty_le_half_thresh_carry_i_4\n (.I0(oneeighty_r_reg__0[7]),\n .I1(oneeighty_r_reg__0[6]),\n .O(oneeighty_le_half_thresh_carry_i_4_n_0));\n LUT2 #(\n .INIT(4'h8)) \n oneeighty_le_half_thresh_carry_i_5\n (.I0(oneeighty_r_reg__0[4]),\n .I1(oneeighty_r_reg__0[5]),\n .O(oneeighty_le_half_thresh_carry_i_5_n_0));\n LUT2 #(\n .INIT(4'h1)) \n oneeighty_le_half_thresh_carry_i_6\n (.I0(oneeighty_r_reg__0[2]),\n .I1(oneeighty_r_reg__0[3]),\n .O(oneeighty_le_half_thresh_carry_i_6_n_0));\n LUT2 #(\n .INIT(4'h8)) \n oneeighty_le_half_thresh_carry_i_7\n (.I0(oneeighty_r_reg__0[1]),\n .I1(oneeighty_r_reg__0[0]),\n .O(oneeighty_le_half_thresh_carry_i_7_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair440\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\oneeighty_r[0]_i_1 \n (.I0(oneeighty_r_reg__0[0]),\n .O(\\oneeighty_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair440\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\oneeighty_r[1]_i_1 \n (.I0(oneeighty_r_reg__0[1]),\n .I1(oneeighty_r_reg__0[0]),\n .O(p_0_in__2[1]));\n (* SOFT_HLUTNM = \"soft_lutpair437\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\oneeighty_r[2]_i_1 \n (.I0(oneeighty_r_reg__0[2]),\n .I1(oneeighty_r_reg__0[0]),\n .I2(oneeighty_r_reg__0[1]),\n .O(p_0_in__2[2]));\n (* SOFT_HLUTNM = \"soft_lutpair425\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\oneeighty_r[3]_i_1 \n (.I0(oneeighty_r_reg__0[3]),\n .I1(oneeighty_r_reg__0[1]),\n .I2(oneeighty_r_reg__0[0]),\n .I3(oneeighty_r_reg__0[2]),\n .O(p_0_in__2[3]));\n (* SOFT_HLUTNM = \"soft_lutpair425\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\oneeighty_r[4]_i_1 \n (.I0(oneeighty_r_reg__0[4]),\n .I1(oneeighty_r_reg__0[2]),\n .I2(oneeighty_r_reg__0[0]),\n .I3(oneeighty_r_reg__0[1]),\n .I4(oneeighty_r_reg__0[3]),\n .O(p_0_in__2[4]));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n \\oneeighty_r[5]_i_1 \n (.I0(oneeighty_r_reg__0[5]),\n .I1(oneeighty_r_reg__0[3]),\n .I2(oneeighty_r_reg__0[1]),\n .I3(oneeighty_r_reg__0[0]),\n .I4(oneeighty_r_reg__0[2]),\n .I5(oneeighty_r_reg__0[4]),\n .O(p_0_in__2[5]));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n \\oneeighty_r[6]_i_1 \n (.I0(oneeighty_r_reg__0[6]),\n .I1(oneeighty_r_reg__0[4]),\n .I2(oneeighty_r_reg__0[5]),\n .I3(oneeighty_r_reg__0[3]),\n .I4(\\oneeighty_r[6]_i_2_n_0 ),\n .I5(oneeighty_r_reg__0[2]),\n .O(p_0_in__2[6]));\n (* SOFT_HLUTNM = \"soft_lutpair437\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\oneeighty_r[6]_i_2 \n (.I0(oneeighty_r_reg__0[1]),\n .I1(oneeighty_r_reg__0[0]),\n .O(\\oneeighty_r[6]_i_2_n_0 ));\n LUT3 #(\n .INIT(8'h6A)) \n \\oneeighty_r[7]_i_1 \n (.I0(oneeighty_r_reg__0[7]),\n .I1(\\oneeighty_r[9]_i_3_n_0 ),\n .I2(oneeighty_r_reg__0[6]),\n .O(p_0_in__2[7]));\n (* SOFT_HLUTNM = \"soft_lutpair430\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\oneeighty_r[8]_i_1 \n (.I0(oneeighty_r_reg__0[8]),\n .I1(oneeighty_r_reg__0[7]),\n .I2(oneeighty_r_reg__0[6]),\n .I3(\\oneeighty_r[9]_i_3_n_0 ),\n .O(p_0_in__2[8]));\n LUT2 #(\n .INIT(4'h8)) \n \\oneeighty_r[9]_i_1 \n (.I0(\\samps_r_reg[0]_0 ),\n .I1(\\data_bytes_r_reg[32] ),\n .O(oneeighty_ns));\n (* SOFT_HLUTNM = \"soft_lutpair430\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\oneeighty_r[9]_i_2 \n (.I0(oneeighty_r_reg__0[9]),\n .I1(\\oneeighty_r[9]_i_3_n_0 ),\n .I2(oneeighty_r_reg__0[6]),\n .I3(oneeighty_r_reg__0[7]),\n .I4(oneeighty_r_reg__0[8]),\n .O(p_0_in__2[9]));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\oneeighty_r[9]_i_3 \n (.I0(oneeighty_r_reg__0[2]),\n .I1(oneeighty_r_reg__0[0]),\n .I2(oneeighty_r_reg__0[1]),\n .I3(oneeighty_r_reg__0[3]),\n .I4(oneeighty_r_reg__0[5]),\n .I5(oneeighty_r_reg__0[4]),\n .O(\\oneeighty_r[9]_i_3_n_0 ));\n FDRE \\oneeighty_r_reg[0] \n (.C(CLK),\n .CE(oneeighty_ns),\n .D(\\oneeighty_r[0]_i_1_n_0 ),\n .Q(oneeighty_r_reg__0[0]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE \\oneeighty_r_reg[1] \n (.C(CLK),\n .CE(oneeighty_ns),\n .D(p_0_in__2[1]),\n .Q(oneeighty_r_reg__0[1]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE \\oneeighty_r_reg[2] \n (.C(CLK),\n .CE(oneeighty_ns),\n .D(p_0_in__2[2]),\n .Q(oneeighty_r_reg__0[2]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE \\oneeighty_r_reg[3] \n (.C(CLK),\n .CE(oneeighty_ns),\n .D(p_0_in__2[3]),\n .Q(oneeighty_r_reg__0[3]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE \\oneeighty_r_reg[4] \n (.C(CLK),\n .CE(oneeighty_ns),\n .D(p_0_in__2[4]),\n .Q(oneeighty_r_reg__0[4]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE \\oneeighty_r_reg[5] \n (.C(CLK),\n .CE(oneeighty_ns),\n .D(p_0_in__2[5]),\n .Q(oneeighty_r_reg__0[5]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE \\oneeighty_r_reg[6] \n (.C(CLK),\n .CE(oneeighty_ns),\n .D(p_0_in__2[6]),\n .Q(oneeighty_r_reg__0[6]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE \\oneeighty_r_reg[7] \n (.C(CLK),\n .CE(oneeighty_ns),\n .D(p_0_in__2[7]),\n .Q(oneeighty_r_reg__0[7]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE \\oneeighty_r_reg[8] \n (.C(CLK),\n .CE(oneeighty_ns),\n .D(p_0_in__2[8]),\n .Q(oneeighty_r_reg__0[8]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE \\oneeighty_r_reg[9] \n (.C(CLK),\n .CE(oneeighty_ns),\n .D(p_0_in__2[9]),\n .Q(oneeighty_r_reg__0[9]),\n .R(\\sm_r_reg[0]_0 ));\n LUT6 #(\n .INIT(64'h003AFFFF003A0000)) \n \\prev_samp_r[0]_i_1 \n (.I0(zero_ge_thresh),\n .I1(zero_le_half_thresh),\n .I2(\\samp_result_r_reg_n_0_[0] ),\n .I3(rstdiv0_sync_r1_reg_rep__25),\n .I4(\\u_ocd_edge/samp_valid ),\n .I5(prev_samp_r[0]),\n .O(\\prev_samp_r_reg[0] ));\n LUT6 #(\n .INIT(64'h0454FFFF04540000)) \n \\prev_samp_r[1]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__25),\n .I1(oneeighty_ge_thresh),\n .I2(p_0_in11_in),\n .I3(oneeighty_le_half_thresh),\n .I4(\\u_ocd_edge/samp_valid ),\n .I5(prev_samp_r[1]),\n .O(\\prev_samp_r_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair434\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\prev_samp_r[1]_i_2 \n (.I0(samp_done),\n .I1(rd_active_r1),\n .O(\\u_ocd_edge/samp_valid ));\n (* SOFT_HLUTNM = \"soft_lutpair434\" *) \n LUT3 #(\n .INIT(8'hF8)) \n prev_samp_valid_r_i_1\n (.I0(samp_done),\n .I1(rd_active_r1),\n .I2(prev_samp_valid_r),\n .O(prev_samp_valid_r_reg));\n LUT6 #(\n .INIT(64'h6664666466640000)) \n \\rd_victim_sel_r[0]_i_1 \n (.I0(phy_rddata_en_r1_reg_0),\n .I1(\\rd_victim_sel_r_reg[1]_1 ),\n .I2(\\rd_victim_sel_r_reg[1]_0 ),\n .I3(\\rd_victim_sel_r_reg[2]_0 ),\n .I4(rstdiv0_sync_r1_reg_rep__25),\n .I5(\\samps_r_reg[9]_0 ),\n .O(\\rd_victim_sel_r[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h78787800)) \n \\rd_victim_sel_r[1]_i_1 \n (.I0(phy_rddata_en_r1_reg_0),\n .I1(\\rd_victim_sel_r_reg[1]_1 ),\n .I2(\\rd_victim_sel_r_reg[1]_0 ),\n .I3(rstdiv0_sync_r1_reg_rep__20),\n .I4(\\samps_r_reg[9]_0 ),\n .O(\\rd_victim_sel_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h7F807F807F800000)) \n \\rd_victim_sel_r[2]_i_1 \n (.I0(phy_rddata_en_r1_reg_0),\n .I1(\\rd_victim_sel_r_reg[1]_1 ),\n .I2(\\rd_victim_sel_r_reg[1]_0 ),\n .I3(\\rd_victim_sel_r_reg[2]_0 ),\n .I4(rstdiv0_sync_r1_reg_rep__25),\n .I5(\\samps_r_reg[9]_0 ),\n .O(\\rd_victim_sel_r[2]_i_1_n_0 ));\n FDRE \\rd_victim_sel_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_victim_sel_r[0]_i_1_n_0 ),\n .Q(\\rd_victim_sel_r_reg[1]_1 ),\n .R(1'b0));\n FDRE \\rd_victim_sel_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_victim_sel_r[1]_i_1_n_0 ),\n .Q(\\rd_victim_sel_r_reg[1]_0 ),\n .R(1'b0));\n FDRE \\rd_victim_sel_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_victim_sel_r[2]_i_1_n_0 ),\n .Q(\\rd_victim_sel_r_reg[2]_0 ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000AAEAAA2A)) \n samp_done_r_i_1\n (.I0(samp_done),\n .I1(\\samps_r_reg[9]_0 ),\n .I2(phy_rddata_en_r1_reg),\n .I3(rstdiv0_sync_r1_reg_rep__26),\n .I4(samp_done_ns9_in),\n .I5(samp_done_ns8_out),\n .O(samp_done_r_i_1_n_0));\n FDRE samp_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(samp_done_r_i_1_n_0),\n .Q(samp_done),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h000000003FFF8080)) \n \\samp_result_r[0]_i_1 \n (.I0(zero_ge_thresh),\n .I1(rd_active_r1),\n .I2(samp_done),\n .I3(zero_le_half_thresh),\n .I4(\\samp_result_r_reg_n_0_[0] ),\n .I5(rstdiv0_sync_r1_reg_rep__25),\n .O(D[0]));\n LUT6 #(\n .INIT(64'h1515400055554000)) \n \\samp_result_r[1]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__25),\n .I1(rd_active_r1),\n .I2(samp_done),\n .I3(oneeighty_ge_thresh),\n .I4(p_0_in11_in),\n .I5(oneeighty_le_half_thresh),\n .O(D[1]));\n FDRE \\samp_result_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(D[0]),\n .Q(\\samp_result_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\samp_result_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(D[1]),\n .Q(p_0_in11_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair438\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\samps_r[0]_i_1 \n (.I0(samps_r[0]),\n .O(samps_r0[0]));\n LUT4 #(\n .INIT(16'h9990)) \n \\samps_r[1]_i_1 \n (.I0(samps_r[1]),\n .I1(samps_r[0]),\n .I2(\\samps_r_reg[9]_0 ),\n .I3(rstdiv0_sync_r1_reg_rep__25),\n .O(\\samps_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair438\" *) \n LUT3 #(\n .INIT(8'hA9)) \n \\samps_r[2]_i_1 \n (.I0(samps_r[2]),\n .I1(samps_r[1]),\n .I2(samps_r[0]),\n .O(samps_r0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair427\" *) \n LUT4 #(\n .INIT(16'hAAA9)) \n \\samps_r[3]_i_1 \n (.I0(samps_r[3]),\n .I1(samps_r[2]),\n .I2(samps_r[0]),\n .I3(samps_r[1]),\n .O(samps_r0[3]));\n LUT6 #(\n .INIT(64'h00000000FFFE0001)) \n \\samps_r[4]_i_1 \n (.I0(samps_r[2]),\n .I1(samps_r[0]),\n .I2(samps_r[1]),\n .I3(samps_r[3]),\n .I4(samps_r[4]),\n .I5(\\sm_r_reg[0]_0 ),\n .O(\\samps_r[4]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h9990)) \n \\samps_r[5]_i_1 \n (.I0(\\samps_r[8]_i_4_n_0 ),\n .I1(samps_r[5]),\n .I2(\\samps_r_reg[9]_0 ),\n .I3(rstdiv0_sync_r1_reg_rep__25),\n .O(\\samps_r[5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair433\" *) \n LUT3 #(\n .INIT(8'hA9)) \n \\samps_r[6]_i_1 \n (.I0(samps_r[6]),\n .I1(\\samps_r[8]_i_4_n_0 ),\n .I2(samps_r[5]),\n .O(samps_r0[6]));\n (* SOFT_HLUTNM = \"soft_lutpair433\" *) \n LUT4 #(\n .INIT(16'hAAA9)) \n \\samps_r[7]_i_1 \n (.I0(samps_r[7]),\n .I1(samps_r[6]),\n .I2(samps_r[5]),\n .I3(\\samps_r[8]_i_4_n_0 ),\n .O(\\samps_r[7]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h1F11)) \n \\samps_r[8]_i_1 \n (.I0(\\samps_r_reg[9]_0 ),\n .I1(rstdiv0_sync_r1_reg_rep__25),\n .I2(\\samps_r[8]_i_3_n_0 ),\n .I3(\\samps_r_reg[0]_0 ),\n .O(samps_ns));\n (* SOFT_HLUTNM = \"soft_lutpair429\" *) \n LUT5 #(\n .INIT(32'hAAAAAAA9)) \n \\samps_r[8]_i_2 \n (.I0(samps_r[8]),\n .I1(\\samps_r[8]_i_4_n_0 ),\n .I2(samps_r[5]),\n .I3(samps_r[6]),\n .I4(samps_r[7]),\n .O(samps_r0[8]));\n LUT5 #(\n .INIT(32'h00000001)) \n \\samps_r[8]_i_3 \n (.I0(samps_r[2]),\n .I1(samps_r[9]),\n .I2(samps_r[6]),\n .I3(samps_r[5]),\n .I4(\\samps_r[8]_i_5_n_0 ),\n .O(\\samps_r[8]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair427\" *) \n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n \\samps_r[8]_i_4 \n (.I0(samps_r[4]),\n .I1(samps_r[3]),\n .I2(samps_r[2]),\n .I3(samps_r[0]),\n .I4(samps_r[1]),\n .O(\\samps_r[8]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFEFF)) \n \\samps_r[8]_i_5 \n (.I0(samps_r[4]),\n .I1(samps_r[3]),\n .I2(samps_r[8]),\n .I3(samps_r[0]),\n .I4(samps_r[1]),\n .I5(samps_r[7]),\n .O(\\samps_r[8]_i_5_n_0 ));\n LUT4 #(\n .INIT(16'h1F11)) \n \\samps_r[9]_i_1 \n (.I0(\\samps_r_reg[9]_0 ),\n .I1(rstdiv0_sync_r1_reg_rep__20),\n .I2(\\samps_r[8]_i_3_n_0 ),\n .I3(\\samps_r_reg[0]_0 ),\n .O(\\samps_r[9]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hD2D2D2FF)) \n \\samps_r[9]_i_2 \n (.I0(\\samps_r[9]_i_3_n_0 ),\n .I1(samps_r[8]),\n .I2(samps_r[9]),\n .I3(\\samps_r_reg[9]_0 ),\n .I4(rstdiv0_sync_r1_reg_rep__25),\n .O(\\samps_r[9]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair429\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\samps_r[9]_i_3 \n (.I0(samps_r[7]),\n .I1(samps_r[6]),\n .I2(samps_r[5]),\n .I3(\\samps_r[8]_i_4_n_0 ),\n .O(\\samps_r[9]_i_3_n_0 ));\n FDRE \\samps_r_reg[0] \n (.C(CLK),\n .CE(samps_ns),\n .D(samps_r0[0]),\n .Q(samps_r[0]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE \\samps_r_reg[1] \n (.C(CLK),\n .CE(\\samps_r[9]_i_1_n_0 ),\n .D(\\samps_r[1]_i_1_n_0 ),\n .Q(samps_r[1]),\n .R(1'b0));\n FDRE \\samps_r_reg[2] \n (.C(CLK),\n .CE(samps_ns),\n .D(samps_r0[2]),\n .Q(samps_r[2]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE \\samps_r_reg[3] \n (.C(CLK),\n .CE(samps_ns),\n .D(samps_r0[3]),\n .Q(samps_r[3]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE \\samps_r_reg[4] \n (.C(CLK),\n .CE(\\samps_r[9]_i_1_n_0 ),\n .D(\\samps_r[4]_i_1_n_0 ),\n .Q(samps_r[4]),\n .R(1'b0));\n FDRE \\samps_r_reg[5] \n (.C(CLK),\n .CE(\\samps_r[9]_i_1_n_0 ),\n .D(\\samps_r[5]_i_1_n_0 ),\n .Q(samps_r[5]),\n .R(1'b0));\n FDRE \\samps_r_reg[6] \n (.C(CLK),\n .CE(samps_ns),\n .D(samps_r0[6]),\n .Q(samps_r[6]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE \\samps_r_reg[7] \n (.C(CLK),\n .CE(samps_ns),\n .D(\\samps_r[7]_i_1_n_0 ),\n .Q(samps_r[7]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE \\samps_r_reg[8] \n (.C(CLK),\n .CE(samps_ns),\n .D(samps_r0[8]),\n .Q(samps_r[8]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE \\samps_r_reg[9] \n (.C(CLK),\n .CE(\\samps_r[9]_i_1_n_0 ),\n .D(\\samps_r[9]_i_2_n_0 ),\n .Q(samps_r[9]),\n .R(1'b0));\n LUT4 #(\n .INIT(16'hAEEE)) \n \\sm_r[0]_i_1__0 \n (.I0(samp_done_ns8_out),\n .I1(\\samps_r_reg[9]_0 ),\n .I2(phy_rddata_en_r1_reg),\n .I3(samp_done_ns9_in),\n .O(\\sm_r[0]_i_1__0_n_0 ));\n FDRE \\sm_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\sm_r[0]_i_1__0_n_0 ),\n .Q(\\samps_r_reg[9]_0 ),\n .R(rstdiv0_sync_r1_reg_rep__9));\n LUT4 #(\n .INIT(16'hFFF7)) \n \\stg3_r[5]_i_14 \n (.I0(samp_done),\n .I1(rd_active_r2),\n .I2(\\sm_r_reg[1] ),\n .I3(scanning_right_r_reg),\n .O(\\stg3_r_reg[1] ));\n CARRY4 zero_ge_thresh_carry\n (.CI(1'b0),\n .CO({zero_ge_thresh_carry_n_0,zero_ge_thresh_carry_n_1,zero_ge_thresh_carry_n_2,zero_ge_thresh_carry_n_3}),\n .CYINIT(1'b1),\n .DI({1'b0,zero_ge_thresh_carry_i_1_n_0,zero_r_reg__0[3],zero_ge_thresh_carry_i_2_n_0}),\n .O(NLW_zero_ge_thresh_carry_O_UNCONNECTED[3:0]),\n .S({zero_ge_thresh_carry_i_3_n_0,zero_ge_thresh_carry_i_4_n_0,zero_ge_thresh_carry_i_5_n_0,zero_ge_thresh_carry_i_6_n_0}));\n CARRY4 zero_ge_thresh_carry__0\n (.CI(zero_ge_thresh_carry_n_0),\n .CO({NLW_zero_ge_thresh_carry__0_CO_UNCONNECTED[3:1],zero_ge_thresh}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,zero_r_reg__0[9]}),\n .O(NLW_zero_ge_thresh_carry__0_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,1'b0,zero_ge_thresh_carry__0_i_1_n_0}));\n LUT2 #(\n .INIT(4'h2)) \n zero_ge_thresh_carry__0_i_1\n (.I0(zero_r_reg__0[8]),\n .I1(zero_r_reg__0[9]),\n .O(zero_ge_thresh_carry__0_i_1_n_0));\n LUT2 #(\n .INIT(4'h8)) \n zero_ge_thresh_carry_i_1\n (.I0(zero_r_reg__0[4]),\n .I1(zero_r_reg__0[5]),\n .O(zero_ge_thresh_carry_i_1_n_0));\n LUT2 #(\n .INIT(4'h8)) \n zero_ge_thresh_carry_i_2\n (.I0(zero_r_reg__0[1]),\n .I1(zero_r_reg__0[0]),\n .O(zero_ge_thresh_carry_i_2_n_0));\n LUT2 #(\n .INIT(4'h8)) \n zero_ge_thresh_carry_i_3\n (.I0(zero_r_reg__0[6]),\n .I1(zero_r_reg__0[7]),\n .O(zero_ge_thresh_carry_i_3_n_0));\n LUT2 #(\n .INIT(4'h2)) \n zero_ge_thresh_carry_i_4\n (.I0(zero_r_reg__0[5]),\n .I1(zero_r_reg__0[4]),\n .O(zero_ge_thresh_carry_i_4_n_0));\n LUT2 #(\n .INIT(4'h2)) \n zero_ge_thresh_carry_i_5\n (.I0(zero_r_reg__0[2]),\n .I1(zero_r_reg__0[3]),\n .O(zero_ge_thresh_carry_i_5_n_0));\n LUT2 #(\n .INIT(4'h2)) \n zero_ge_thresh_carry_i_6\n (.I0(zero_r_reg__0[1]),\n .I1(zero_r_reg__0[0]),\n .O(zero_ge_thresh_carry_i_6_n_0));\n CARRY4 zero_le_half_thresh_carry\n (.CI(1'b0),\n .CO({zero_le_half_thresh_carry_n_0,zero_le_half_thresh_carry_n_1,zero_le_half_thresh_carry_n_2,zero_le_half_thresh_carry_n_3}),\n .CYINIT(1'b1),\n .DI({zero_le_half_thresh_carry_i_1_n_0,zero_le_half_thresh_carry_i_2_n_0,1'b0,zero_le_half_thresh_carry_i_3_n_0}),\n .O(NLW_zero_le_half_thresh_carry_O_UNCONNECTED[3:0]),\n .S({zero_le_half_thresh_carry_i_4_n_0,zero_le_half_thresh_carry_i_5_n_0,zero_le_half_thresh_carry_i_6_n_0,zero_le_half_thresh_carry_i_7_n_0}));\n CARRY4 zero_le_half_thresh_carry__0\n (.CI(zero_le_half_thresh_carry_n_0),\n .CO({NLW_zero_le_half_thresh_carry__0_CO_UNCONNECTED[3:1],zero_le_half_thresh}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(NLW_zero_le_half_thresh_carry__0_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,1'b0,zero_le_half_thresh_carry__0_i_1_n_0}));\n LUT2 #(\n .INIT(4'h1)) \n zero_le_half_thresh_carry__0_i_1\n (.I0(zero_r_reg__0[8]),\n .I1(zero_r_reg__0[9]),\n .O(zero_le_half_thresh_carry__0_i_1_n_0));\n LUT2 #(\n .INIT(4'h7)) \n zero_le_half_thresh_carry_i_1\n (.I0(zero_r_reg__0[7]),\n .I1(zero_r_reg__0[6]),\n .O(zero_le_half_thresh_carry_i_1_n_0));\n LUT2 #(\n .INIT(4'h7)) \n zero_le_half_thresh_carry_i_2\n (.I0(zero_r_reg__0[5]),\n .I1(zero_r_reg__0[4]),\n .O(zero_le_half_thresh_carry_i_2_n_0));\n LUT2 #(\n .INIT(4'h7)) \n zero_le_half_thresh_carry_i_3\n (.I0(zero_r_reg__0[0]),\n .I1(zero_r_reg__0[1]),\n .O(zero_le_half_thresh_carry_i_3_n_0));\n LUT2 #(\n .INIT(4'h8)) \n zero_le_half_thresh_carry_i_4\n (.I0(zero_r_reg__0[6]),\n .I1(zero_r_reg__0[7]),\n .O(zero_le_half_thresh_carry_i_4_n_0));\n LUT2 #(\n .INIT(4'h8)) \n zero_le_half_thresh_carry_i_5\n (.I0(zero_r_reg__0[4]),\n .I1(zero_r_reg__0[5]),\n .O(zero_le_half_thresh_carry_i_5_n_0));\n LUT2 #(\n .INIT(4'h1)) \n zero_le_half_thresh_carry_i_6\n (.I0(zero_r_reg__0[2]),\n .I1(zero_r_reg__0[3]),\n .O(zero_le_half_thresh_carry_i_6_n_0));\n LUT2 #(\n .INIT(4'h8)) \n zero_le_half_thresh_carry_i_7\n (.I0(zero_r_reg__0[1]),\n .I1(zero_r_reg__0[0]),\n .O(zero_le_half_thresh_carry_i_7_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair439\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\zero_r[0]_i_1 \n (.I0(zero_r_reg__0[0]),\n .O(\\zero_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair439\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\zero_r[1]_i_1 \n (.I0(zero_r_reg__0[1]),\n .I1(zero_r_reg__0[0]),\n .O(p_0_in__1[1]));\n (* SOFT_HLUTNM = \"soft_lutpair436\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\zero_r[2]_i_1 \n (.I0(zero_r_reg__0[2]),\n .I1(zero_r_reg__0[0]),\n .I2(zero_r_reg__0[1]),\n .O(p_0_in__1[2]));\n (* SOFT_HLUTNM = \"soft_lutpair424\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\zero_r[3]_i_1 \n (.I0(zero_r_reg__0[3]),\n .I1(zero_r_reg__0[1]),\n .I2(zero_r_reg__0[0]),\n .I3(zero_r_reg__0[2]),\n .O(p_0_in__1[3]));\n (* SOFT_HLUTNM = \"soft_lutpair424\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\zero_r[4]_i_1 \n (.I0(zero_r_reg__0[4]),\n .I1(zero_r_reg__0[2]),\n .I2(zero_r_reg__0[0]),\n .I3(zero_r_reg__0[1]),\n .I4(zero_r_reg__0[3]),\n .O(p_0_in__1[4]));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n \\zero_r[5]_i_1 \n (.I0(zero_r_reg__0[5]),\n .I1(zero_r_reg__0[3]),\n .I2(zero_r_reg__0[1]),\n .I3(zero_r_reg__0[0]),\n .I4(zero_r_reg__0[2]),\n .I5(zero_r_reg__0[4]),\n .O(p_0_in__1[5]));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n \\zero_r[6]_i_1 \n (.I0(zero_r_reg__0[6]),\n .I1(zero_r_reg__0[4]),\n .I2(zero_r_reg__0[5]),\n .I3(zero_r_reg__0[3]),\n .I4(\\zero_r[6]_i_2_n_0 ),\n .I5(zero_r_reg__0[2]),\n .O(p_0_in__1[6]));\n (* SOFT_HLUTNM = \"soft_lutpair436\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\zero_r[6]_i_2 \n (.I0(zero_r_reg__0[1]),\n .I1(zero_r_reg__0[0]),\n .O(\\zero_r[6]_i_2_n_0 ));\n LUT3 #(\n .INIT(8'h6A)) \n \\zero_r[7]_i_1 \n (.I0(zero_r_reg__0[7]),\n .I1(\\zero_r[9]_i_8_n_0 ),\n .I2(zero_r_reg__0[6]),\n .O(p_0_in__1[7]));\n (* SOFT_HLUTNM = \"soft_lutpair426\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\zero_r[8]_i_1 \n (.I0(zero_r_reg__0[8]),\n .I1(zero_r_reg__0[6]),\n .I2(zero_r_reg__0[7]),\n .I3(\\zero_r[9]_i_8_n_0 ),\n .O(p_0_in__1[8]));\n (* SOFT_HLUTNM = \"soft_lutpair426\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\zero_r[9]_i_3 \n (.I0(zero_r_reg__0[9]),\n .I1(zero_r_reg__0[7]),\n .I2(\\zero_r[9]_i_8_n_0 ),\n .I3(zero_r_reg__0[6]),\n .I4(zero_r_reg__0[8]),\n .O(p_0_in__1[9]));\n LUT4 #(\n .INIT(16'h0002)) \n \\zero_r[9]_i_6 \n (.I0(phy_rddata_en_r1_reg_0),\n .I1(\\rd_victim_sel_r_reg[1]_1 ),\n .I2(\\rd_victim_sel_r_reg[1]_0 ),\n .I3(\\rd_victim_sel_r_reg[2]_0 ),\n .O(\\samps_r_reg[0]_0 ));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\zero_r[9]_i_8 \n (.I0(zero_r_reg__0[2]),\n .I1(zero_r_reg__0[0]),\n .I2(zero_r_reg__0[1]),\n .I3(zero_r_reg__0[3]),\n .I4(zero_r_reg__0[5]),\n .I5(zero_r_reg__0[4]),\n .O(\\zero_r[9]_i_8_n_0 ));\n FDRE \\zero_r_reg[0] \n (.C(CLK),\n .CE(\\rd_victim_sel_r_reg[0]_0 ),\n .D(\\zero_r[0]_i_1_n_0 ),\n .Q(zero_r_reg__0[0]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE \\zero_r_reg[1] \n (.C(CLK),\n .CE(\\rd_victim_sel_r_reg[0]_0 ),\n .D(p_0_in__1[1]),\n .Q(zero_r_reg__0[1]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE \\zero_r_reg[2] \n (.C(CLK),\n .CE(\\rd_victim_sel_r_reg[0]_0 ),\n .D(p_0_in__1[2]),\n .Q(zero_r_reg__0[2]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE \\zero_r_reg[3] \n (.C(CLK),\n .CE(\\rd_victim_sel_r_reg[0]_0 ),\n .D(p_0_in__1[3]),\n .Q(zero_r_reg__0[3]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE \\zero_r_reg[4] \n (.C(CLK),\n .CE(\\rd_victim_sel_r_reg[0]_0 ),\n .D(p_0_in__1[4]),\n .Q(zero_r_reg__0[4]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE \\zero_r_reg[5] \n (.C(CLK),\n .CE(\\rd_victim_sel_r_reg[0]_0 ),\n .D(p_0_in__1[5]),\n .Q(zero_r_reg__0[5]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE \\zero_r_reg[6] \n (.C(CLK),\n .CE(\\rd_victim_sel_r_reg[0]_0 ),\n .D(p_0_in__1[6]),\n .Q(zero_r_reg__0[6]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE \\zero_r_reg[7] \n (.C(CLK),\n .CE(\\rd_victim_sel_r_reg[0]_0 ),\n .D(p_0_in__1[7]),\n .Q(zero_r_reg__0[7]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE \\zero_r_reg[8] \n (.C(CLK),\n .CE(\\rd_victim_sel_r_reg[0]_0 ),\n .D(p_0_in__1[8]),\n .Q(zero_r_reg__0[8]),\n .R(\\sm_r_reg[0]_0 ));\n FDRE \\zero_r_reg[9] \n (.C(CLK),\n .CE(\\rd_victim_sel_r_reg[0]_0 ),\n .D(p_0_in__1[9]),\n .Q(zero_r_reg__0[9]),\n .R(\\sm_r_reg[0]_0 ));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_ddr_phy_oclkdelay_cal\n (O,\n ocal_last_byte_done_reg,\n complex_oclk_calib_resume,\n ocd_prech_req,\n complex_ocal_num_samples_done_r,\n po_stg23_incdec,\n po_en_stg23,\n phy_rddata_en_1,\n wrlvl_final_mux_reg,\n lim2init_prech_req,\n done_r_reg,\n \\samps_r_reg[9] ,\n oclkdelay_center_calib_start_r_reg,\n D_po_sel_fine_oclk_delay125_out,\n \\po_counter_read_val_reg[8] ,\n \\po_counter_read_val_reg[8]_0 ,\n \\po_counter_read_val_reg[8]_1 ,\n \\resume_wait_r_reg[5] ,\n \\po_counter_read_val_reg[8]_2 ,\n \\po_counter_read_val_reg[8]_3 ,\n \\po_counter_read_val_reg[8]_4 ,\n \\po_counter_read_val_reg[8]_5 ,\n complex_ocal_ref_req,\n stg3_dec2init_val_r_reg,\n stg3_inc2init_val_r_reg,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ,\n \\stg2_target_r_reg[8] ,\n \\stg3_tap_cnt_reg[2] ,\n \\byte_r_reg[1] ,\n \\byte_r_reg[0] ,\n \\stg2_tap_cnt_reg[3] ,\n \\stg2_tap_cnt_reg[0] ,\n \\sm_r_reg[0] ,\n complex_ocal_rd_victim_sel,\n \\zero2fuzz_r_reg[0] ,\n sr_valid_r108_out,\n \\init_state_r_reg[4] ,\n \\init_state_r_reg[2] ,\n \\init_state_r_reg[0] ,\n \\init_state_r_reg[5] ,\n \\init_state_r_reg[5]_0 ,\n \\init_state_r_reg[6] ,\n \\init_state_r_reg[5]_1 ,\n \\init_state_r_reg[4]_0 ,\n ocal_last_byte_done_reg_0,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[1] ,\n \\cal2_state_r_reg[0] ,\n S,\n \\qcntr_r_reg[0] ,\n CLK,\n rstdiv0_sync_r1_reg_rep__20,\n poc_sample_pd,\n rstdiv0_sync_r1_reg_rep__10,\n rstdiv0_sync_r1_reg_rep__9,\n phy_rddata_en,\n Q,\n calib_in_common,\n \\calib_zero_inputs_reg[1] ,\n rstdiv0_sync_r1_reg_rep__26,\n rstdiv0_sync_r1_reg_rep__26_0,\n oclkdelay_calib_start_int_reg,\n prech_done,\n rd_active_r2,\n rstdiv0_sync_r1_reg_rep__25,\n \\sm_r_reg[0]_0 ,\n rd_active_r1,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n ck_addr_cmd_delay_done,\n mpr_rdlvl_done_r_reg,\n \\gen_byte_sel_div1.calib_in_common_reg_0 ,\n \\gen_byte_sel_div1.calib_in_common_reg_1 ,\n \\gen_byte_sel_div1.calib_in_common_reg_2 ,\n \\wl_po_fine_cnt_reg[17] ,\n \\byte_r_reg[0]_0 ,\n D,\n \\po_counter_read_val_reg[2] ,\n \\stg2_tap_cnt_reg[2] ,\n \\wl_po_fine_cnt_reg[3] ,\n \\wl_po_fine_cnt_reg[14] ,\n \\wl_po_fine_cnt_reg[18] ,\n rstdiv0_sync_r1_reg_rep__26_1,\n rstdiv0_sync_r1_reg_rep__26_2,\n \\mmcm_init_trail_reg[0] ,\n \\mmcm_current_reg[0] ,\n rdlvl_stg1_start_reg,\n \\cnt_shift_r_reg[0] ,\n \\init_state_r_reg[0]_0 ,\n prbs_rdlvl_done_reg,\n \\init_state_r_reg[4]_1 ,\n \\init_state_r_reg[0]_1 ,\n wrlvl_final_mux,\n oclkdelay_int_ref_req_reg,\n prech_req_posedge_r_reg,\n cnt_cmd_done_r,\n prbs_rdlvl_done_reg_rep,\n ocal_last_byte_done,\n \\po_stg2_wrcal_cnt_reg[0] ,\n wr_level_done_reg,\n oclkdelay_calib_done_r_reg,\n pi_stg2_rdlvl_cnt,\n \\po_stg2_wrcal_cnt_reg[1] ,\n wrlvl_byte_done,\n \\wl_po_fine_cnt_reg[23] ,\n \\stg3_r_reg[0] ,\n psdone,\n rstdiv0_sync_r1_reg_rep,\n rstdiv0_sync_r1_reg_rep__0,\n rstdiv0_sync_r1_reg_rep__19,\n rstdiv0_sync_r1_reg_rep__11,\n \\po_counter_read_val_reg[5] ,\n \\byte_r_reg[0]_1 ,\n rstdiv0_sync_r1_reg_rep__2,\n oclkdelay_calib_start_int_reg_0,\n pd_out);\n output [3:0]O;\n output ocal_last_byte_done_reg;\n output complex_oclk_calib_resume;\n output ocd_prech_req;\n output complex_ocal_num_samples_done_r;\n output po_stg23_incdec;\n output po_en_stg23;\n output phy_rddata_en_1;\n output wrlvl_final_mux_reg;\n output lim2init_prech_req;\n output done_r_reg;\n output \\samps_r_reg[9] ;\n output oclkdelay_center_calib_start_r_reg;\n output D_po_sel_fine_oclk_delay125_out;\n output \\po_counter_read_val_reg[8] ;\n output \\po_counter_read_val_reg[8]_0 ;\n output \\po_counter_read_val_reg[8]_1 ;\n output \\resume_wait_r_reg[5] ;\n output \\po_counter_read_val_reg[8]_2 ;\n output \\po_counter_read_val_reg[8]_3 ;\n output \\po_counter_read_val_reg[8]_4 ;\n output \\po_counter_read_val_reg[8]_5 ;\n output complex_ocal_ref_req;\n output stg3_dec2init_val_r_reg;\n output stg3_inc2init_val_r_reg;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ;\n output [2:0]\\stg2_target_r_reg[8] ;\n output [2:0]\\stg3_tap_cnt_reg[2] ;\n output \\byte_r_reg[1] ;\n output \\byte_r_reg[0] ;\n output [2:0]\\stg2_tap_cnt_reg[3] ;\n output \\stg2_tap_cnt_reg[0] ;\n output \\sm_r_reg[0] ;\n output [2:0]complex_ocal_rd_victim_sel;\n output [0:0]\\zero2fuzz_r_reg[0] ;\n output sr_valid_r108_out;\n output \\init_state_r_reg[4] ;\n output \\init_state_r_reg[2] ;\n output \\init_state_r_reg[0] ;\n output \\init_state_r_reg[5] ;\n output \\init_state_r_reg[5]_0 ;\n output \\init_state_r_reg[6] ;\n output \\init_state_r_reg[5]_1 ;\n output \\init_state_r_reg[4]_0 ;\n output ocal_last_byte_done_reg_0;\n output \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ;\n output \\gen_byte_sel_div1.byte_sel_cnt_reg[1] ;\n output \\cal2_state_r_reg[0] ;\n output [0:0]S;\n output [0:0]\\qcntr_r_reg[0] ;\n input CLK;\n input rstdiv0_sync_r1_reg_rep__20;\n input poc_sample_pd;\n input rstdiv0_sync_r1_reg_rep__10;\n input rstdiv0_sync_r1_reg_rep__9;\n input phy_rddata_en;\n input [1:0]Q;\n input calib_in_common;\n input [1:0]\\calib_zero_inputs_reg[1] ;\n input rstdiv0_sync_r1_reg_rep__26;\n input rstdiv0_sync_r1_reg_rep__26_0;\n input oclkdelay_calib_start_int_reg;\n input prech_done;\n input rd_active_r2;\n input rstdiv0_sync_r1_reg_rep__25;\n input [0:0]\\sm_r_reg[0]_0 ;\n input rd_active_r1;\n input \\gen_byte_sel_div1.calib_in_common_reg ;\n input ck_addr_cmd_delay_done;\n input mpr_rdlvl_done_r_reg;\n input \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n input \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n input \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n input \\wl_po_fine_cnt_reg[17] ;\n input \\byte_r_reg[0]_0 ;\n input [2:0]D;\n input \\po_counter_read_val_reg[2] ;\n input \\stg2_tap_cnt_reg[2] ;\n input \\wl_po_fine_cnt_reg[3] ;\n input [1:0]\\wl_po_fine_cnt_reg[14] ;\n input \\wl_po_fine_cnt_reg[18] ;\n input rstdiv0_sync_r1_reg_rep__26_1;\n input rstdiv0_sync_r1_reg_rep__26_2;\n input \\mmcm_init_trail_reg[0] ;\n input \\mmcm_current_reg[0] ;\n input rdlvl_stg1_start_reg;\n input \\cnt_shift_r_reg[0] ;\n input \\init_state_r_reg[0]_0 ;\n input prbs_rdlvl_done_reg;\n input [2:0]\\init_state_r_reg[4]_1 ;\n input \\init_state_r_reg[0]_1 ;\n input wrlvl_final_mux;\n input oclkdelay_int_ref_req_reg;\n input prech_req_posedge_r_reg;\n input cnt_cmd_done_r;\n input prbs_rdlvl_done_reg_rep;\n input ocal_last_byte_done;\n input \\po_stg2_wrcal_cnt_reg[0] ;\n input wr_level_done_reg;\n input oclkdelay_calib_done_r_reg;\n input [1:0]pi_stg2_rdlvl_cnt;\n input \\po_stg2_wrcal_cnt_reg[1] ;\n input wrlvl_byte_done;\n input [7:0]\\wl_po_fine_cnt_reg[23] ;\n input \\stg3_r_reg[0] ;\n input psdone;\n input rstdiv0_sync_r1_reg_rep;\n input rstdiv0_sync_r1_reg_rep__0;\n input [0:0]rstdiv0_sync_r1_reg_rep__19;\n input [0:0]rstdiv0_sync_r1_reg_rep__11;\n input [5:0]\\po_counter_read_val_reg[5] ;\n input [63:0]\\byte_r_reg[0]_1 ;\n input rstdiv0_sync_r1_reg_rep__2;\n input oclkdelay_calib_start_int_reg_0;\n input pd_out;\n\n wire CLK;\n wire [2:0]D;\n wire D_po_sel_fine_oclk_delay125_out;\n wire [3:0]O;\n wire [1:0]Q;\n wire [0:0]S;\n wire [1:0]agg_samp_r;\n wire \\byte_r_reg[0] ;\n wire \\byte_r_reg[0]_0 ;\n wire [63:0]\\byte_r_reg[0]_1 ;\n wire \\byte_r_reg[1] ;\n wire \\cal2_state_r_reg[0] ;\n wire calib_in_common;\n wire [1:0]\\calib_zero_inputs_reg[1] ;\n wire ck_addr_cmd_delay_done;\n wire cnt_cmd_done_r;\n wire \\cnt_shift_r_reg[0] ;\n wire complex_ocal_num_samples_done_r;\n wire [2:0]complex_ocal_rd_victim_sel;\n wire complex_ocal_ref_req;\n wire complex_oclk_calib_resume;\n wire dec_po_ns;\n wire done_r_reg;\n wire f2z_ns5_out;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[1] ;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n wire inc_po_ns;\n wire \\init_state_r_reg[0] ;\n wire \\init_state_r_reg[0]_0 ;\n wire \\init_state_r_reg[0]_1 ;\n wire \\init_state_r_reg[2] ;\n wire \\init_state_r_reg[4] ;\n wire \\init_state_r_reg[4]_0 ;\n wire [2:0]\\init_state_r_reg[4]_1 ;\n wire \\init_state_r_reg[5] ;\n wire \\init_state_r_reg[5]_0 ;\n wire \\init_state_r_reg[5]_1 ;\n wire \\init_state_r_reg[6] ;\n wire lim2init_prech_req;\n wire lim2poc_ktap_right;\n wire lim2poc_rdy;\n wire lim2stg2_dec;\n wire lim2stg2_inc;\n wire lim2stg3_dec;\n wire lim2stg3_inc;\n wire lim_start;\n wire lim_start_r;\n wire \\mmcm_current_reg[0] ;\n wire \\mmcm_init_trail_reg[0] ;\n wire mpr_rdlvl_done_r_reg;\n wire [1:0]ninety_offsets;\n wire o2f_ns1_out;\n wire ocal_last_byte_done;\n wire ocal_last_byte_done_reg;\n wire ocal_last_byte_done_reg_0;\n wire ocd_cntlr2stg2_dec_r;\n wire ocd_prech_req;\n wire oclk_center_write_resume;\n wire oclkdelay_calib_done_r_reg;\n wire oclkdelay_calib_start_int_reg;\n wire oclkdelay_calib_start_int_reg_0;\n wire oclkdelay_center_calib_start_r_reg;\n wire oclkdelay_int_ref_req_reg;\n wire pd_out;\n wire phy_rddata_en;\n wire phy_rddata_en_1;\n wire [1:0]pi_stg2_rdlvl_cnt;\n wire \\po_counter_read_val_reg[2] ;\n wire [5:0]\\po_counter_read_val_reg[5] ;\n wire \\po_counter_read_val_reg[8] ;\n wire \\po_counter_read_val_reg[8]_0 ;\n wire \\po_counter_read_val_reg[8]_1 ;\n wire \\po_counter_read_val_reg[8]_2 ;\n wire \\po_counter_read_val_reg[8]_3 ;\n wire \\po_counter_read_val_reg[8]_4 ;\n wire \\po_counter_read_val_reg[8]_5 ;\n wire po_en_stg23;\n wire po_rdy;\n wire po_stg23_incdec;\n wire \\po_stg2_wrcal_cnt_reg[0] ;\n wire \\po_stg2_wrcal_cnt_reg[1] ;\n wire poc_sample_pd;\n wire prbs_rdlvl_done_reg;\n wire prbs_rdlvl_done_reg_rep;\n wire prech_done;\n wire prech_req_posedge_r_reg;\n wire [1:0]prev_samp_r;\n wire prev_samp_valid_r;\n wire psdone;\n wire [0:0]\\qcntr_r_reg[0] ;\n wire rd_active_r1;\n wire rd_active_r2;\n wire rdlvl_stg1_start_reg;\n wire reset_scan;\n wire \\resume_wait_r_reg[5] ;\n wire [5:0]rise_lead_right;\n wire [5:0]rise_trail_right;\n wire rstdiv0_sync_r1_reg_rep;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__10;\n wire [0:0]rstdiv0_sync_r1_reg_rep__11;\n wire [0:0]rstdiv0_sync_r1_reg_rep__19;\n wire rstdiv0_sync_r1_reg_rep__2;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__25;\n wire rstdiv0_sync_r1_reg_rep__26;\n wire rstdiv0_sync_r1_reg_rep__26_0;\n wire rstdiv0_sync_r1_reg_rep__26_1;\n wire rstdiv0_sync_r1_reg_rep__26_2;\n wire rstdiv0_sync_r1_reg_rep__9;\n wire samp_done;\n wire samp_done_ns8_out;\n wire \\samps_r_reg[9] ;\n wire scan_right;\n wire scanning_right;\n wire setup_po;\n wire [1:1]sm_r;\n wire \\sm_r_reg[0] ;\n wire [0:0]\\sm_r_reg[0]_0 ;\n wire sr_valid_r108_out;\n wire \\stg2_tap_cnt_reg[0] ;\n wire \\stg2_tap_cnt_reg[2] ;\n wire [2:0]\\stg2_tap_cnt_reg[3] ;\n wire [2:0]\\stg2_target_r_reg[8] ;\n wire stg3_dec2init_val_r_reg;\n wire stg3_inc2init_val_r_reg;\n wire \\stg3_r_reg[0] ;\n wire [2:0]\\stg3_tap_cnt_reg[2] ;\n wire u_ocd_cntlr_n_10;\n wire u_ocd_cntlr_n_11;\n wire u_ocd_cntlr_n_12;\n wire u_ocd_cntlr_n_13;\n wire u_ocd_cntlr_n_14;\n wire u_ocd_cntlr_n_15;\n wire u_ocd_cntlr_n_16;\n wire u_ocd_cntlr_n_17;\n wire u_ocd_cntlr_n_18;\n wire u_ocd_cntlr_n_19;\n wire u_ocd_cntlr_n_20;\n wire u_ocd_cntlr_n_9;\n wire u_ocd_data_n_0;\n wire u_ocd_data_n_1;\n wire u_ocd_data_n_2;\n wire u_ocd_edge_n_1;\n wire u_ocd_edge_n_10;\n wire u_ocd_edge_n_2;\n wire u_ocd_edge_n_3;\n wire u_ocd_edge_n_7;\n wire u_ocd_lim_n_19;\n wire u_ocd_lim_n_20;\n wire u_ocd_lim_n_21;\n wire u_ocd_lim_n_22;\n wire u_ocd_lim_n_23;\n wire u_ocd_lim_n_24;\n wire u_ocd_lim_n_25;\n wire u_ocd_lim_n_26;\n wire u_ocd_lim_n_27;\n wire u_ocd_lim_n_28;\n wire u_ocd_lim_n_29;\n wire u_ocd_lim_n_30;\n wire u_ocd_lim_n_31;\n wire u_ocd_lim_n_32;\n wire u_ocd_lim_n_9;\n wire u_ocd_mux_n_11;\n wire u_ocd_po_cntlr_n_11;\n wire u_ocd_po_cntlr_n_12;\n wire u_ocd_po_cntlr_n_13;\n wire u_ocd_po_cntlr_n_14;\n wire u_ocd_po_cntlr_n_15;\n wire u_ocd_po_cntlr_n_16;\n wire u_ocd_po_cntlr_n_17;\n wire u_ocd_po_cntlr_n_20;\n wire u_ocd_po_cntlr_n_22;\n wire u_ocd_po_cntlr_n_23;\n wire u_ocd_po_cntlr_n_27;\n wire u_ocd_po_cntlr_n_28;\n wire u_ocd_po_cntlr_n_29;\n wire u_ocd_po_cntlr_n_30;\n wire u_ocd_po_cntlr_n_31;\n wire u_ocd_po_cntlr_n_32;\n wire u_ocd_po_cntlr_n_33;\n wire u_ocd_po_cntlr_n_34;\n wire u_ocd_po_cntlr_n_35;\n wire u_ocd_po_cntlr_n_48;\n wire u_ocd_po_cntlr_n_49;\n wire u_ocd_po_cntlr_n_50;\n wire u_ocd_po_cntlr_n_51;\n wire u_ocd_po_cntlr_n_7;\n wire u_ocd_samp_n_10;\n wire u_ocd_samp_n_14;\n wire u_ocd_samp_n_16;\n wire u_ocd_samp_n_20;\n wire u_ocd_samp_n_21;\n wire u_ocd_samp_n_3;\n wire u_ocd_samp_n_4;\n wire u_ocd_samp_n_5;\n wire u_ocd_samp_n_6;\n wire u_ocd_samp_n_7;\n wire u_poc_n_0;\n wire u_poc_n_1;\n wire u_poc_n_16;\n wire u_poc_n_17;\n wire u_poc_n_2;\n wire use_noise_window;\n wire [1:0]\\wl_po_fine_cnt_reg[14] ;\n wire \\wl_po_fine_cnt_reg[17] ;\n wire \\wl_po_fine_cnt_reg[18] ;\n wire [7:0]\\wl_po_fine_cnt_reg[23] ;\n wire \\wl_po_fine_cnt_reg[3] ;\n wire wr_level_done_reg;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ;\n wire wrlvl_byte_done;\n wire wrlvl_final_mux;\n wire wrlvl_final_mux_reg;\n wire [5:1]zero2fuzz_r0;\n wire [0:0]\\zero2fuzz_r_reg[0] ;\n\n ddr3_if_mig_7series_v4_0_ddr_phy_ocd_cntlr u_ocd_cntlr\n (.CLK(CLK),\n .D({u_ocd_cntlr_n_9,u_ocd_cntlr_n_10,u_ocd_cntlr_n_11,u_ocd_cntlr_n_12,u_ocd_cntlr_n_13}),\n .\\byte_r_reg[0]_0 (\\byte_r_reg[0] ),\n .\\byte_r_reg[1]_0 (\\byte_r_reg[1] ),\n .\\cal2_state_r_reg[0] (\\cal2_state_r_reg[0] ),\n .cnt_cmd_done_r(cnt_cmd_done_r),\n .\\cnt_shift_r_reg[0] (\\cnt_shift_r_reg[0] ),\n .complex_ocal_ref_req(complex_ocal_ref_req),\n .\\data_cnt_r_reg[7] (u_ocd_samp_n_3),\n .done_r_reg(u_ocd_cntlr_n_18),\n .done_r_reg_0(done_r_reg),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[0] (\\gen_byte_sel_div1.byte_sel_cnt_reg[0] ),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[1] (\\gen_byte_sel_div1.byte_sel_cnt_reg[1] ),\n .\\init_state_r_reg[0] (\\init_state_r_reg[0]_1 ),\n .\\init_state_r_reg[2] (\\init_state_r_reg[2] ),\n .\\init_state_r_reg[2]_0 (\\init_state_r_reg[4]_1 [1:0]),\n .\\init_state_r_reg[5] (\\init_state_r_reg[5] ),\n .lim_start(lim_start),\n .lim_start_r(lim_start_r),\n .ocal_last_byte_done(ocal_last_byte_done),\n .ocal_last_byte_done_reg(ocal_last_byte_done_reg_0),\n .ocd_cntlr2stg2_dec_r(ocd_cntlr2stg2_dec_r),\n .oclk_calib_resume_r_reg(complex_oclk_calib_resume),\n .oclkdelay_calib_done_r_reg_0(oclkdelay_calib_done_r_reg),\n .oclkdelay_calib_start_int_reg(oclkdelay_calib_start_int_reg),\n .oclkdelay_calib_start_int_reg_0(oclkdelay_calib_start_int_reg_0),\n .oclkdelay_center_calib_done_r_reg(ocal_last_byte_done_reg),\n .phy_rddata_en(phy_rddata_en),\n .pi_stg2_rdlvl_cnt(pi_stg2_rdlvl_cnt),\n .\\po_counter_read_val_reg[2] (\\po_counter_read_val_reg[2] ),\n .po_rdy(po_rdy),\n .\\po_stg2_wrcal_cnt_reg[0] (\\po_stg2_wrcal_cnt_reg[0] ),\n .\\po_stg2_wrcal_cnt_reg[1] (\\po_stg2_wrcal_cnt_reg[1] ),\n .prbs_rdlvl_done_reg(prbs_rdlvl_done_reg),\n .prech_done(prech_done),\n .prech_req_posedge_r_reg(prech_req_posedge_r_reg),\n .prech_req_r_reg(ocd_prech_req),\n .prech_req_r_reg_0(lim2init_prech_req),\n .rd_active_r1(rd_active_r1),\n .rd_active_r1_reg(phy_rddata_en_1),\n .\\rd_victim_sel_r_reg[0] (u_ocd_cntlr_n_19),\n .rdlvl_stg1_start_reg(rdlvl_stg1_start_reg),\n .reset_scan(reset_scan),\n .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10),\n .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25),\n .rstdiv0_sync_r1_reg_rep__26(rstdiv0_sync_r1_reg_rep__26_0),\n .rstdiv0_sync_r1_reg_rep__26_0(rstdiv0_sync_r1_reg_rep__26),\n .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9),\n .\\simp_stg3_final_r_reg[10] (u_ocd_po_cntlr_n_30),\n .\\simp_stg3_final_r_reg[11] (u_ocd_cntlr_n_15),\n .\\simp_stg3_final_r_reg[12] (u_ocd_po_cntlr_n_33),\n .\\simp_stg3_final_r_reg[16] (u_ocd_po_cntlr_n_50),\n .\\simp_stg3_final_r_reg[17] (u_ocd_cntlr_n_17),\n .\\simp_stg3_final_r_reg[17]_0 (u_ocd_po_cntlr_n_28),\n .\\simp_stg3_final_r_reg[19] (u_ocd_po_cntlr_n_32),\n .\\simp_stg3_final_r_reg[23] (u_ocd_cntlr_n_14),\n .\\simp_stg3_final_r_reg[2] (u_ocd_po_cntlr_n_51),\n .\\simp_stg3_final_r_reg[5] (u_ocd_cntlr_n_16),\n .\\simp_stg3_final_r_reg[8] (u_ocd_po_cntlr_n_31),\n .sr_valid_r108_out(sr_valid_r108_out),\n .\\stg3_init_val_reg[3] (u_ocd_cntlr_n_20),\n .wr_level_done_reg(wr_level_done_reg),\n .\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] (\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ),\n .wrlvl_byte_done(wrlvl_byte_done),\n .wrlvl_final_mux_reg(wrlvl_final_mux_reg));\n ddr3_if_mig_7series_v4_0_ddr_phy_ocd_data u_ocd_data\n (.CLK(CLK),\n .E(u_ocd_data_n_0),\n .agg_samp_r(agg_samp_r),\n .\\byte_r_reg[0] (\\byte_r_reg[0]_1 ),\n .\\rd_victim_sel_r_reg[0] (u_ocd_samp_n_7),\n .\\zero_r_reg[9] (u_ocd_data_n_1),\n .\\zero_r_reg[9]_0 (u_ocd_data_n_2));\n ddr3_if_mig_7series_v4_0_ddr_phy_ocd_edge u_ocd_edge\n (.CLK(CLK),\n .D({zero2fuzz_r0,\\zero2fuzz_r_reg[0] }),\n .E(u_ocd_samp_n_16),\n .Q({u_ocd_po_cntlr_n_11,u_ocd_po_cntlr_n_12,u_ocd_po_cntlr_n_13,u_ocd_po_cntlr_n_14,u_ocd_po_cntlr_n_15,u_ocd_po_cntlr_n_16}),\n .dec_po_ns(dec_po_ns),\n .f2o_r_reg_0(u_ocd_edge_n_3),\n .inc_po_ns(inc_po_ns),\n .\\ninety_offsets_final_r_reg[0] (u_ocd_edge_n_2),\n .\\ninety_offsets_final_r_reg[0]_0 (u_ocd_edge_n_10),\n .\\ninety_offsets_final_r_reg[1] (u_ocd_edge_n_7),\n .o2f_r_reg_0(u_ocd_edge_n_1),\n .ocd_ktap_left_r_reg(u_ocd_po_cntlr_n_7),\n .prev_samp_r(prev_samp_r),\n .prev_samp_valid_r(prev_samp_valid_r),\n .rd_active_r1(rd_active_r1),\n .rd_active_r1_reg(u_ocd_samp_n_5),\n .rd_active_r1_reg_0(u_ocd_samp_n_6),\n .reset_scan(reset_scan),\n .reset_scan_r_reg(u_ocd_samp_n_14),\n .samp_done(samp_done),\n .samp_done_r_reg(u_ocd_samp_n_4),\n .\\samp_result_r_reg[0] (u_ocd_samp_n_20),\n .\\samp_result_r_reg[1] (u_ocd_samp_n_21),\n .scan_right(scan_right),\n .scanning_right(scanning_right),\n .scanning_right_r_reg(u_ocd_po_cntlr_n_22),\n .scanning_right_r_reg_0(u_ocd_po_cntlr_n_23),\n .\\stg3_left_lim_reg[5] ({u_ocd_lim_n_20,u_ocd_lim_n_21,u_ocd_lim_n_22,u_ocd_lim_n_23,u_ocd_lim_n_24,u_ocd_lim_n_25}),\n .\\stg3_right_lim_reg[5] ({u_ocd_lim_n_27,u_ocd_lim_n_28,u_ocd_lim_n_29,u_ocd_lim_n_30,u_ocd_lim_n_31,u_ocd_lim_n_32}));\n ddr3_if_mig_7series_v4_0_ddr_phy_ocd_lim u_ocd_lim\n (.CLK(CLK),\n .D(D),\n .Q(rise_trail_right),\n .\\byte_r_reg[0] (\\byte_r_reg[0]_0 ),\n .cnt_cmd_done_r(cnt_cmd_done_r),\n .done_r_reg_0(done_r_reg),\n .done_r_reg_1(u_poc_n_0),\n .\\init_state_r_reg[4] (\\init_state_r_reg[4]_0 ),\n .\\init_state_r_reg[5] (\\init_state_r_reg[5]_1 ),\n .\\init_state_r_reg[6] (\\init_state_r_reg[6] ),\n .lim2poc_ktap_right(lim2poc_ktap_right),\n .lim2poc_rdy(lim2poc_rdy),\n .lim2stg2_dec(lim2stg2_dec),\n .lim2stg2_inc(lim2stg2_inc),\n .lim2stg3_dec(lim2stg3_dec),\n .lim2stg3_inc(lim2stg3_inc),\n .lim_start(lim_start),\n .lim_start_r(lim_start_r),\n .lim_start_r_reg_0(u_ocd_cntlr_n_18),\n .\\mmcm_current_reg[0]_0 (\\mmcm_current_reg[0] ),\n .\\mmcm_init_trail_reg[0]_0 (\\mmcm_init_trail_reg[0] ),\n .o2f_r_reg(u_ocd_edge_n_1),\n .ocd_prech_req_r_reg(ocd_prech_req),\n .oclk_center_write_resume(oclk_center_write_resume),\n .oclkdelay_calib_done_r_reg({u_ocd_cntlr_n_9,u_ocd_cntlr_n_10,u_ocd_po_cntlr_n_29,u_ocd_cntlr_n_11,u_ocd_cntlr_n_12,u_ocd_cntlr_n_13}),\n .oclkdelay_center_calib_start_r_reg(u_ocd_lim_n_26),\n .oclkdelay_center_calib_start_r_reg_0({u_ocd_lim_n_27,u_ocd_lim_n_28,u_ocd_lim_n_29,u_ocd_lim_n_30,u_ocd_lim_n_31,u_ocd_lim_n_32}),\n .po_rdy(po_rdy),\n .po_stg23_sel_r_reg(u_ocd_lim_n_9),\n .\\po_wait_r_reg[0] (u_ocd_mux_n_11),\n .prbs_rdlvl_done_reg_rep(prbs_rdlvl_done_reg_rep),\n .prech_done(prech_done),\n .prech_req_r_reg_0(lim2init_prech_req),\n .\\rise_lead_r_reg[5] (rise_lead_right),\n .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10),\n .rstdiv0_sync_r1_reg_rep__11(rstdiv0_sync_r1_reg_rep__11),\n .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__26(rstdiv0_sync_r1_reg_rep__26),\n .rstdiv0_sync_r1_reg_rep__26_0(rstdiv0_sync_r1_reg_rep__26_1),\n .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9),\n .scan_right(scan_right),\n .scanning_right(scanning_right),\n .scanning_right_r_reg(u_ocd_lim_n_19),\n .scanning_right_r_reg_0({u_ocd_lim_n_20,u_ocd_lim_n_21,u_ocd_lim_n_22,u_ocd_lim_n_23,u_ocd_lim_n_24,u_ocd_lim_n_25}),\n .\\sm_r_reg[2] (u_ocd_po_cntlr_n_20),\n .\\stg2_tap_cnt_reg[0]_0 (\\stg2_tap_cnt_reg[0] ),\n .\\stg2_tap_cnt_reg[2]_0 (\\stg2_tap_cnt_reg[2] ),\n .\\stg2_tap_cnt_reg[3]_0 (\\stg2_tap_cnt_reg[3] ),\n .stg3_dec2init_val_r_reg_0(stg3_dec2init_val_r_reg),\n .stg3_inc2init_val_r_reg_0(stg3_inc2init_val_r_reg),\n .\\stg3_r_reg[5] ({u_ocd_po_cntlr_n_11,u_ocd_po_cntlr_n_12,u_ocd_po_cntlr_n_13,u_ocd_po_cntlr_n_14,u_ocd_po_cntlr_n_15,u_ocd_po_cntlr_n_16}),\n .\\stg3_tap_cnt_reg[2]_0 (\\stg3_tap_cnt_reg[2] ),\n .\\wl_po_fine_cnt_reg[14] (\\wl_po_fine_cnt_reg[14] ),\n .\\wl_po_fine_cnt_reg[17] (\\wl_po_fine_cnt_reg[17] ),\n .\\wl_po_fine_cnt_reg[18] (\\wl_po_fine_cnt_reg[18] ),\n .\\wl_po_fine_cnt_reg[3] (\\wl_po_fine_cnt_reg[3] ));\n ddr3_if_mig_7series_v4_0_ddr_phy_ocd_mux u_ocd_mux\n (.CLK(CLK),\n .D_po_sel_fine_oclk_delay125_out(D_po_sel_fine_oclk_delay125_out),\n .Q(Q),\n .calib_in_common(calib_in_common),\n .\\calib_zero_inputs_reg[1] (\\calib_zero_inputs_reg[1] ),\n .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done),\n .\\gen_byte_sel_div1.calib_in_common_reg (\\gen_byte_sel_div1.calib_in_common_reg ),\n .\\gen_byte_sel_div1.calib_in_common_reg_0 (\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_1 (\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .\\gen_byte_sel_div1.calib_in_common_reg_2 (\\gen_byte_sel_div1.calib_in_common_reg_2 ),\n .mpr_rdlvl_done_r_reg(mpr_rdlvl_done_r_reg),\n .oclkdelay_calib_done_r_reg(wrlvl_final_mux_reg),\n .\\po_counter_read_val_reg[8] (\\po_counter_read_val_reg[8] ),\n .\\po_counter_read_val_reg[8]_0 (\\po_counter_read_val_reg[8]_0 ),\n .\\po_counter_read_val_reg[8]_1 (\\po_counter_read_val_reg[8]_1 ),\n .\\po_counter_read_val_reg[8]_2 (\\po_counter_read_val_reg[8]_2 ),\n .\\po_counter_read_val_reg[8]_3 (\\po_counter_read_val_reg[8]_3 ),\n .\\po_counter_read_val_reg[8]_4 (\\po_counter_read_val_reg[8]_4 ),\n .\\po_counter_read_val_reg[8]_5 (\\po_counter_read_val_reg[8]_5 ),\n .po_rdy(po_rdy),\n .po_stg23_incdec(po_stg23_incdec),\n .po_stg23_sel_r_reg_0(u_ocd_mux_n_11),\n .\\po_wait_r_reg[3]_0 (po_en_stg23),\n .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10),\n .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25),\n .setup_po(setup_po),\n .stg2_dec_req_r_reg(u_ocd_po_cntlr_n_27),\n .stg3_dec_req_r_reg(u_ocd_lim_n_9),\n .stg3_inc_req_r_reg(u_ocd_po_cntlr_n_17));\n ddr3_if_mig_7series_v4_0_ddr_phy_ocd_po_cntlr u_ocd_po_cntlr\n (.CLK(CLK),\n .D({zero2fuzz_r0,\\zero2fuzz_r_reg[0] }),\n .E(\\resume_wait_r_reg[5] ),\n .O(O),\n .Q({u_ocd_po_cntlr_n_11,u_ocd_po_cntlr_n_12,u_ocd_po_cntlr_n_13,u_ocd_po_cntlr_n_14,u_ocd_po_cntlr_n_15,u_ocd_po_cntlr_n_16}),\n .S(S),\n .\\byte_r_reg[0] (\\byte_r_reg[0]_0 ),\n .\\byte_r_reg[0]_0 (\\byte_r_reg[0] ),\n .\\byte_r_reg[0]_1 (u_ocd_cntlr_n_14),\n .\\byte_r_reg[0]_2 (u_ocd_cntlr_n_15),\n .\\byte_r_reg[0]_3 (u_ocd_cntlr_n_16),\n .\\byte_r_reg[1] (\\byte_r_reg[1] ),\n .\\byte_r_reg[1]_0 (u_ocd_cntlr_n_17),\n .complex_ocal_num_samples_done_r(complex_ocal_num_samples_done_r),\n .dec_po_ns(dec_po_ns),\n .done_r_reg(u_poc_n_0),\n .edge_aligned_r_reg(u_ocd_po_cntlr_n_49),\n .edge_aligned_r_reg_0(u_poc_n_1),\n .f2o_r_reg(u_ocd_edge_n_7),\n .f2o_r_reg_0(u_ocd_edge_n_10),\n .f2z_ns5_out(f2z_ns5_out),\n .f2z_r_reg(u_ocd_po_cntlr_n_23),\n .f2z_r_reg_0(u_ocd_edge_n_2),\n .inc_po_ns(inc_po_ns),\n .\\init_state_r_reg[0] (\\init_state_r_reg[0] ),\n .lim2poc_ktap_right(lim2poc_ktap_right),\n .lim2poc_rdy(lim2poc_rdy),\n .lim2stg2_dec(lim2stg2_dec),\n .lim2stg2_inc(lim2stg2_inc),\n .lim2stg3_dec(lim2stg3_dec),\n .lim2stg3_inc(lim2stg3_inc),\n .ninety_offsets(ninety_offsets),\n .o2f_ns1_out(o2f_ns1_out),\n .o2f_r_reg(u_ocd_po_cntlr_n_22),\n .o2f_r_reg_0(u_ocd_edge_n_1),\n .ocal_last_byte_done_reg(ocal_last_byte_done_reg),\n .ocd_cntlr2stg2_dec_r(ocd_cntlr2stg2_dec_r),\n .oclk_center_write_resume(oclk_center_write_resume),\n .oclkdelay_calib_done_r_reg(u_ocd_cntlr_n_20),\n .oclkdelay_calib_done_r_reg_0(wrlvl_final_mux_reg),\n .oclkdelay_center_calib_start_r_reg_0(oclkdelay_center_calib_start_r_reg),\n .oclkdelay_int_ref_req_reg(oclkdelay_int_ref_req_reg),\n .\\po_counter_read_val_reg[5] (\\po_counter_read_val_reg[5] ),\n .po_rdy(po_rdy),\n .po_stg23_incdec(po_stg23_incdec),\n .po_stg23_incdec_r_reg(u_ocd_po_cntlr_n_17),\n .po_stg23_incdec_r_reg_0(u_ocd_po_cntlr_n_27),\n .poc_backup_r_reg_0(u_ocd_po_cntlr_n_48),\n .poc_backup_r_reg_1(u_poc_n_2),\n .prech_req_posedge_r_reg(prech_req_posedge_r_reg),\n .rd_active_r2(rd_active_r2),\n .reset_scan(reset_scan),\n .\\rise_trail_r_reg[5] (u_ocd_po_cntlr_n_34),\n .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25),\n .rstdiv0_sync_r1_reg_rep__26(rstdiv0_sync_r1_reg_rep__26),\n .rstdiv0_sync_r1_reg_rep__26_0(rstdiv0_sync_r1_reg_rep__26_2),\n .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9),\n .\\run_ends_r_reg[0] (u_poc_n_16),\n .\\run_ends_r_reg[1] (u_ocd_po_cntlr_n_35),\n .\\run_ends_r_reg[1]_0 (u_poc_n_17),\n .samp_done(samp_done),\n .samp_done_ns8_out(samp_done_ns8_out),\n .samp_done_r_reg(u_ocd_samp_n_10),\n .scan_right_r_reg(u_ocd_lim_n_19),\n .scanning_right(scanning_right),\n .scanning_right_r_reg_0(u_ocd_lim_n_26),\n .setup_po(setup_po),\n .\\sm_r_reg[0]_0 (\\sm_r_reg[0] ),\n .\\sm_r_reg[0]_1 (\\samps_r_reg[9] ),\n .\\sm_r_reg[3]_0 (u_ocd_po_cntlr_n_7),\n .\\stg2_r_reg[0]_0 (sm_r),\n .\\stg2_target_r_reg[8]_0 (\\stg2_target_r_reg[8] ),\n .\\stg3_init_val_reg[0] (u_ocd_po_cntlr_n_33),\n .\\stg3_init_val_reg[1] (u_ocd_po_cntlr_n_32),\n .\\stg3_init_val_reg[2] (u_ocd_po_cntlr_n_31),\n .\\stg3_init_val_reg[2]_0 (u_ocd_po_cntlr_n_51),\n .\\stg3_init_val_reg[3] (u_ocd_po_cntlr_n_29),\n .\\stg3_init_val_reg[4] (u_ocd_po_cntlr_n_30),\n .\\stg3_init_val_reg[4]_0 (u_ocd_po_cntlr_n_50),\n .\\stg3_init_val_reg[5] (u_ocd_po_cntlr_n_28),\n .\\stg3_r_reg[0]_0 (\\stg3_r_reg[0] ),\n .\\two_r_reg[1]_0 (u_ocd_po_cntlr_n_20),\n .use_noise_window(use_noise_window),\n .\\wl_po_fine_cnt_reg[14] (\\wl_po_fine_cnt_reg[14] ),\n .\\wl_po_fine_cnt_reg[17] (\\wl_po_fine_cnt_reg[17] ),\n .\\wl_po_fine_cnt_reg[18] (\\wl_po_fine_cnt_reg[18] ),\n .\\wl_po_fine_cnt_reg[23] (\\wl_po_fine_cnt_reg[23] ),\n .\\wl_po_fine_cnt_reg[3] (\\wl_po_fine_cnt_reg[3] ),\n .wrlvl_final_mux(wrlvl_final_mux));\n ddr3_if_mig_7series_v4_0_ddr_phy_ocd_samp u_ocd_samp\n (.CLK(CLK),\n .D({u_ocd_samp_n_5,u_ocd_samp_n_6}),\n .E(u_ocd_samp_n_16),\n .agg_samp_r(agg_samp_r),\n .\\data_bytes_r_reg[24] (u_ocd_data_n_1),\n .\\data_bytes_r_reg[32] (u_ocd_data_n_2),\n .f2o_r_reg(u_ocd_edge_n_3),\n .f2z_ns5_out(f2z_ns5_out),\n .\\init_state_r_reg[0] (\\init_state_r_reg[0]_0 ),\n .\\init_state_r_reg[4] (\\init_state_r_reg[4] ),\n .\\init_state_r_reg[4]_0 (\\init_state_r_reg[4]_1 [2]),\n .\\init_state_r_reg[5] (\\init_state_r_reg[5]_0 ),\n .o2f_ns1_out(o2f_ns1_out),\n .ocd_prech_req_r_reg(ocd_prech_req),\n .oclk_calib_resume_level_reg(complex_oclk_calib_resume),\n .oclk_calib_resume_r_reg_0(u_ocd_samp_n_3),\n .\\oneeighty2fuzz_r_reg[5] (u_ocd_samp_n_14),\n .phy_rddata_en_r1_reg(phy_rddata_en_1),\n .phy_rddata_en_r1_reg_0(u_ocd_cntlr_n_19),\n .prbs_rdlvl_done_reg(prbs_rdlvl_done_reg),\n .prbs_rdlvl_done_reg_rep(prbs_rdlvl_done_reg_rep),\n .prech_req_r_reg(lim2init_prech_req),\n .prev_samp_r(prev_samp_r),\n .\\prev_samp_r_reg[0] (u_ocd_samp_n_20),\n .\\prev_samp_r_reg[1] (u_ocd_samp_n_21),\n .prev_samp_valid_r(prev_samp_valid_r),\n .prev_samp_valid_r_reg(u_ocd_samp_n_4),\n .rd_active_r1(rd_active_r1),\n .rd_active_r2(rd_active_r2),\n .\\rd_victim_sel_r_reg[0]_0 (u_ocd_data_n_0),\n .\\rd_victim_sel_r_reg[1]_0 (complex_ocal_rd_victim_sel[1]),\n .\\rd_victim_sel_r_reg[1]_1 (complex_ocal_rd_victim_sel[0]),\n .\\rd_victim_sel_r_reg[2]_0 (complex_ocal_rd_victim_sel[2]),\n .reset_scan(reset_scan),\n .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25),\n .rstdiv0_sync_r1_reg_rep__26(rstdiv0_sync_r1_reg_rep__26),\n .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9),\n .samp_done(samp_done),\n .samp_done_ns8_out(samp_done_ns8_out),\n .\\samps_r_reg[0]_0 (u_ocd_samp_n_7),\n .\\samps_r_reg[9]_0 (\\samps_r_reg[9] ),\n .scanning_right(scanning_right),\n .scanning_right_r_reg(u_ocd_lim_n_26),\n .\\sm_r_reg[0]_0 (\\sm_r_reg[0]_0 ),\n .\\sm_r_reg[1] (sm_r),\n .\\stg3_r_reg[1] (u_ocd_samp_n_10));\n ddr3_if_mig_7series_v4_0_poc_top u_poc\n (.CLK(CLK),\n .Q(rise_trail_right),\n .detect_done_r_reg(u_poc_n_0),\n .\\mmcm_init_lead_reg[5] (rise_lead_right),\n .ninety_offsets(ninety_offsets),\n .ocd_edge_detect_rdy_r_reg(u_ocd_po_cntlr_n_35),\n .ocd_ktap_left_r_reg(u_ocd_po_cntlr_n_7),\n .ocd_ktap_left_r_reg_0(u_ocd_po_cntlr_n_49),\n .ocd_ktap_right_r_reg(u_ocd_po_cntlr_n_34),\n .pd_out(pd_out),\n .poc_backup_r_reg(u_poc_n_2),\n .poc_sample_pd(poc_sample_pd),\n .\\prev_r_reg[0] (u_poc_n_16),\n .\\prev_r_reg[0]_0 (u_poc_n_17),\n .psdone(psdone),\n .\\qcntr_r_reg[0] (\\qcntr_r_reg[0] ),\n .rstdiv0_sync_r1_reg_rep(rstdiv0_sync_r1_reg_rep),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .\\run_ends_r_reg[1] (u_ocd_po_cntlr_n_48),\n .\\sm_r_reg[1] (u_poc_n_1),\n .use_noise_window(use_noise_window));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_ddr_phy_prbs_rdlvl\n (prbs_rdlvl_start_r,\n \\row_cnt_victim_rotate.complex_row_cnt_reg[4] ,\n prech_req_r_reg,\n prbs_prech_req_r,\n pi_en_stg2_f_timing_reg_0,\n prbs_pi_stg2_f_en,\n prbs_pi_stg2_f_incdec,\n A,\n \\A[0]_0 ,\n \\A[1]_0 ,\n no_err_win_detected_latch_reg_0,\n cnt_wait_state,\n \\rdlvl_cpt_tap_cnt_reg[5]_0 ,\n prbs_found_1st_edge_r_reg_0,\n \\genblk8[0].left_loss_pb_reg[0]_0 ,\n \\genblk8[1].left_loss_pb_reg[6]_0 ,\n \\genblk8[2].left_loss_pb_reg[12]_0 ,\n \\genblk8[3].left_loss_pb_reg[18]_0 ,\n \\genblk8[4].left_loss_pb_reg[24]_0 ,\n \\genblk8[5].left_loss_pb_reg[30]_0 ,\n \\genblk8[6].left_loss_pb_reg[36]_0 ,\n \\genblk8[7].left_loss_pb_reg[42]_0 ,\n \\genblk8[0].right_edge_pb_reg[0]_0 ,\n \\genblk8[1].right_edge_pb_reg[6]_0 ,\n \\genblk8[2].right_edge_pb_reg[12]_0 ,\n \\genblk8[3].right_edge_pb_reg[18]_0 ,\n \\genblk8[4].right_edge_pb_reg[24]_0 ,\n \\genblk8[5].right_edge_pb_reg[30]_0 ,\n \\genblk8[6].right_edge_pb_reg[36]_0 ,\n \\genblk8[7].right_edge_pb_reg[42]_0 ,\n fine_delay_sel_r_reg,\n right_edge_found_reg_0,\n prbs_tap_inc_r,\n \\match_flag_or_reg[0]_0 ,\n \\largest_left_edge_reg[0]_0 ,\n D,\n prbs_rdlvl_done_reg_0,\n \\stg1_wr_rd_cnt_reg[3] ,\n prbs_last_byte_done,\n reset_rd_addr,\n complex_init_pi_dec_done,\n complex_pi_incdec_done,\n \\prbs_dqs_cnt_r_reg[2]_0 ,\n complex_oclkdelay_calib_done_r1_reg,\n p_154_out,\n p_95_out,\n \\genblk8[7].right_edge_pb_reg[42]_1 ,\n p_98_out,\n p_103_out,\n p_106_out,\n \\genblk8[5].right_edge_pb_reg[30]_1 ,\n \\genblk8[5].right_gain_pb_reg[30]_0 ,\n p_119_out,\n p_122_out,\n p_127_out,\n p_130_out,\n \\genblk8[2].right_edge_pb_reg[12]_1 ,\n \\genblk8[2].right_edge_pb_reg[12]_2 ,\n p_143_out,\n p_146_out,\n \\genblk8[0].right_edge_pb_reg[0]_1 ,\n \\genblk8[0].left_loss_pb_reg[0]_1 ,\n Q,\n num_samples_done_r,\n prbs_state_r178_out,\n bit_cnt,\n \\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ,\n right_edge_found_reg_1,\n \\prbs_dec_tap_cnt_reg[1]_0 ,\n reset_rd_addr0,\n \\genblk8[7].left_edge_updated_reg[7]_0 ,\n \\rd_victim_sel_reg[2]_0 ,\n \\oclkdelay_ref_cnt_reg[0] ,\n prbs_rdlvl_done_pulse0,\n \\init_state_r_reg[0] ,\n \\init_state_r_reg[1] ,\n \\init_state_r_reg[0]_0 ,\n \\init_state_r_reg[1]_0 ,\n \\fine_delay_mod_reg[5] ,\n \\fine_delay_mod_reg[20] ,\n \\rdlvl_cpt_tap_cnt_reg[5]_1 ,\n right_gain_pb,\n right_edge_found,\n no_err_win_detected_reg_0,\n prbs_found_1st_edge_r_reg_1,\n prbs_tap_en_r_reg_0,\n prbs_tap_en_r,\n fine_delay_sel_reg_0,\n no_err_win_detected_latch_reg_1,\n fine_delay_sel_reg_1,\n complex_pi_incdec_done_reg_0,\n num_samples_done_ind_reg_0,\n complex_pi_incdec_done_reg_1,\n fine_dly_error_reg_0,\n compare_err_latch_reg_0,\n \\prbs_dqs_cnt_r_reg[1]_0 ,\n prbs_rdlvl_done_reg_1,\n prbs_last_byte_done_reg_0,\n new_cnt_dqs_r_reg_0,\n new_cnt_dqs_r,\n \\rd_victim_sel_reg[2]_1 ,\n \\rd_victim_sel_reg[2]_2 ,\n \\rd_victim_sel_reg[2]_3 ,\n \\fine_delay_mod_reg[26] ,\n \\genblk9[1].fine_delay_incdec_pb_reg[1]_0 ,\n \\genblk9[2].fine_delay_incdec_pb_reg[2]_0 ,\n \\genblk9[3].fine_delay_incdec_pb_reg[3]_0 ,\n \\genblk9[5].fine_delay_incdec_pb_reg[5]_0 ,\n \\genblk9[6].fine_delay_incdec_pb_reg[6]_0 ,\n \\genblk9[7].fine_delay_incdec_pb_reg[7]_0 ,\n CLK,\n prbs_rdlvl_start_reg,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,\n rstdiv0_sync_r1_reg_rep__7,\n \\dout_o_reg[7] ,\n \\dout_o_reg[7]_0 ,\n \\dout_o_reg[7]_1 ,\n \\dout_o_reg[7]_2 ,\n \\dout_o_reg[7]_3 ,\n \\dout_o_reg[7]_4 ,\n \\dout_o_reg[7]_5 ,\n \\dout_o_reg[7]_6 ,\n \\A[1]_1 ,\n \\A[1]_2 ,\n \\A[1]_3 ,\n \\A[1]_4 ,\n \\A[1]_5 ,\n \\A[1]_6 ,\n \\A[1]_7 ,\n \\A[1]_8 ,\n \\dout_o_reg[6] ,\n \\dout_o_reg[6]_0 ,\n \\dout_o_reg[6]_1 ,\n \\dout_o_reg[6]_2 ,\n \\dout_o_reg[6]_3 ,\n \\dout_o_reg[6]_4 ,\n \\dout_o_reg[6]_5 ,\n \\dout_o_reg[6]_6 ,\n \\A[1]_9 ,\n \\A[1]_10 ,\n \\A[1]_11 ,\n \\A[1]_12 ,\n \\A[1]_13 ,\n \\A[1]_14 ,\n \\A[1]_15 ,\n \\A[1]_16 ,\n \\dout_o_reg[5] ,\n \\dout_o_reg[5]_0 ,\n \\dout_o_reg[5]_1 ,\n \\dout_o_reg[5]_2 ,\n \\dout_o_reg[5]_3 ,\n \\dout_o_reg[5]_4 ,\n \\dout_o_reg[5]_5 ,\n \\dout_o_reg[5]_6 ,\n \\A[1]_17 ,\n \\A[1]_18 ,\n \\A[1]_19 ,\n \\A[1]_20 ,\n \\A[1]_21 ,\n \\A[1]_22 ,\n \\A[1]_23 ,\n \\A[1]_24 ,\n \\dout_o_reg[4] ,\n \\dout_o_reg[4]_0 ,\n \\dout_o_reg[4]_1 ,\n \\dout_o_reg[4]_2 ,\n \\dout_o_reg[4]_3 ,\n \\dout_o_reg[4]_4 ,\n \\dout_o_reg[4]_5 ,\n \\dout_o_reg[4]_6 ,\n \\A[1]_25 ,\n \\A[1]_26 ,\n \\A[1]_27 ,\n \\A[1]_28 ,\n \\A[1]_29 ,\n \\A[1]_30 ,\n \\A[1]_31 ,\n \\A[1]_32 ,\n \\dout_o_reg[3] ,\n \\dout_o_reg[3]_0 ,\n \\dout_o_reg[3]_1 ,\n \\dout_o_reg[3]_2 ,\n \\dout_o_reg[3]_3 ,\n \\dout_o_reg[3]_4 ,\n \\dout_o_reg[3]_5 ,\n \\dout_o_reg[3]_6 ,\n \\A[1]_33 ,\n \\A[1]_34 ,\n \\A[1]_35 ,\n \\A[1]_36 ,\n \\A[1]_37 ,\n \\A[1]_38 ,\n \\A[1]_39 ,\n \\A[1]_40 ,\n \\dout_o_reg[2] ,\n \\dout_o_reg[2]_0 ,\n \\dout_o_reg[2]_1 ,\n \\dout_o_reg[2]_2 ,\n \\dout_o_reg[2]_3 ,\n \\dout_o_reg[2]_4 ,\n \\dout_o_reg[2]_5 ,\n \\dout_o_reg[2]_6 ,\n \\A[1]_41 ,\n \\A[1]_42 ,\n \\A[1]_43 ,\n \\A[1]_44 ,\n \\A[1]_45 ,\n \\A[1]_46 ,\n \\A[1]_47 ,\n \\A[1]_48 ,\n \\dout_o_reg[1] ,\n \\dout_o_reg[1]_0 ,\n \\dout_o_reg[1]_1 ,\n \\dout_o_reg[1]_2 ,\n \\dout_o_reg[1]_3 ,\n \\dout_o_reg[1]_4 ,\n \\dout_o_reg[1]_5 ,\n \\dout_o_reg[1]_6 ,\n \\A[1]_49 ,\n \\A[1]_50 ,\n \\A[1]_51 ,\n \\A[1]_52 ,\n \\A[1]_53 ,\n \\A[1]_54 ,\n \\A[1]_55 ,\n \\A[1]_56 ,\n \\dout_o_reg[0] ,\n \\dout_o_reg[0]_0 ,\n \\dout_o_reg[0]_1 ,\n \\dout_o_reg[0]_2 ,\n \\dout_o_reg[0]_3 ,\n \\dout_o_reg[0]_4 ,\n \\dout_o_reg[0]_5 ,\n \\dout_o_reg[0]_6 ,\n \\A[1]_57 ,\n \\A[1]_58 ,\n \\A[1]_59 ,\n \\A[1]_60 ,\n \\A[1]_61 ,\n \\A[1]_62 ,\n \\A[1]_63 ,\n \\A[1]_64 ,\n rstdiv0_sync_r1_reg_rep__8,\n rstdiv0_sync_r1_reg_rep__2,\n \\prbs_state_r_reg[4]_0 ,\n \\prbs_state_r_reg[3]_0 ,\n \\genblk8[0].left_edge_found_pb_reg[0]_0 ,\n \\genblk8[1].left_edge_found_pb_reg[1]_0 ,\n \\genblk8[2].left_edge_found_pb_reg[2]_0 ,\n \\genblk8[3].left_edge_found_pb_reg[3]_0 ,\n \\genblk8[4].left_edge_found_pb_reg[4]_0 ,\n \\genblk8[5].left_edge_found_pb_reg[5]_0 ,\n \\genblk8[6].left_edge_found_pb_reg[6]_0 ,\n \\genblk8[7].left_edge_found_pb_reg[7]_0 ,\n \\genblk8[0].right_edge_found_pb_reg[0]_0 ,\n \\genblk8[1].right_edge_found_pb_reg[1]_0 ,\n \\genblk8[2].right_edge_found_pb_reg[2]_0 ,\n \\genblk8[3].right_edge_found_pb_reg[3]_0 ,\n \\genblk8[4].right_edge_found_pb_reg[4]_0 ,\n \\genblk8[5].right_edge_found_pb_reg[5]_0 ,\n \\genblk8[6].right_edge_found_pb_reg[6]_0 ,\n \\genblk8[7].right_edge_found_pb_reg[7]_0 ,\n \\prbs_state_r_reg[0]_0 ,\n no_err_win_detected_reg_1,\n new_cnt_dqs_r_reg_1,\n \\prbs_state_r_reg[0]_1 ,\n \\prbs_state_r_reg[0]_2 ,\n \\prbs_state_r_reg[4]_1 ,\n \\prbs_state_r_reg[3]_1 ,\n \\genblk8[0].left_edge_updated_reg[0]_0 ,\n \\genblk8[1].left_edge_updated_reg[1]_0 ,\n \\genblk8[2].left_edge_updated_reg[2]_0 ,\n \\genblk8[3].left_edge_updated_reg[3]_0 ,\n \\genblk8[4].left_edge_updated_reg[4]_0 ,\n \\genblk8[5].left_edge_updated_reg[5]_0 ,\n \\genblk8[6].left_edge_updated_reg[6]_0 ,\n \\genblk8[7].left_edge_updated_reg[7]_1 ,\n \\dec_cnt_reg[0]_0 ,\n fine_dly_error_reg_1,\n \\prbs_state_r_reg[0]_3 ,\n prech_done_reg,\n prbs_tap_inc_r_reg_0,\n rstdiv0_sync_r1_reg_rep__9,\n \\prbs_state_r_reg[4]_2 ,\n \\prbs_state_r_reg[4]_3 ,\n \\prbs_state_r_reg[0]_4 ,\n \\prbs_dqs_cnt_r_reg[0]_0 ,\n \\prbs_dqs_cnt_r_reg[0]_1 ,\n \\prbs_dqs_cnt_r_reg[0]_2 ,\n rstdiv0_sync_r1_reg_rep,\n complex_ocal_reset_rd_addr,\n \\calib_sel_reg[3] ,\n \\pi_counter_read_val_reg[5] ,\n rstdiv0_sync_r1_reg_rep__24,\n oclkdelay_center_calib_done_r_reg,\n ocal_last_byte_done,\n prbs_rdlvl_done_r1,\n rdlvl_stg1_done_int_reg,\n wrcal_done_reg,\n dqs_found_done_r_reg,\n \\num_refresh_reg[1] ,\n wrlvl_final_mux,\n rdlvl_stg1_start_int,\n rdlvl_last_byte_done,\n \\one_rank.stg1_wr_done_reg ,\n \\A[2]__2 ,\n \\calib_sel_reg[3]_0 ,\n \\calib_sel_reg[3]_1 ,\n \\calib_sel_reg[3]_2 ,\n rstdiv0_sync_r1_reg_rep__23,\n complex_act_start,\n prech_done,\n prbs_rdlvl_start_reg_0,\n E,\n \\stage_cnt_reg[1]_0 );\n output prbs_rdlvl_start_r;\n output \\row_cnt_victim_rotate.complex_row_cnt_reg[4] ;\n output prech_req_r_reg;\n output prbs_prech_req_r;\n output pi_en_stg2_f_timing_reg_0;\n output prbs_pi_stg2_f_en;\n output prbs_pi_stg2_f_incdec;\n output [1:0]A;\n output \\A[0]_0 ;\n output \\A[1]_0 ;\n output no_err_win_detected_latch_reg_0;\n output cnt_wait_state;\n output \\rdlvl_cpt_tap_cnt_reg[5]_0 ;\n output prbs_found_1st_edge_r_reg_0;\n output \\genblk8[0].left_loss_pb_reg[0]_0 ;\n output \\genblk8[1].left_loss_pb_reg[6]_0 ;\n output \\genblk8[2].left_loss_pb_reg[12]_0 ;\n output \\genblk8[3].left_loss_pb_reg[18]_0 ;\n output \\genblk8[4].left_loss_pb_reg[24]_0 ;\n output \\genblk8[5].left_loss_pb_reg[30]_0 ;\n output \\genblk8[6].left_loss_pb_reg[36]_0 ;\n output \\genblk8[7].left_loss_pb_reg[42]_0 ;\n output \\genblk8[0].right_edge_pb_reg[0]_0 ;\n output \\genblk8[1].right_edge_pb_reg[6]_0 ;\n output \\genblk8[2].right_edge_pb_reg[12]_0 ;\n output \\genblk8[3].right_edge_pb_reg[18]_0 ;\n output \\genblk8[4].right_edge_pb_reg[24]_0 ;\n output \\genblk8[5].right_edge_pb_reg[30]_0 ;\n output \\genblk8[6].right_edge_pb_reg[36]_0 ;\n output \\genblk8[7].right_edge_pb_reg[42]_0 ;\n output fine_delay_sel_r_reg;\n output right_edge_found_reg_0;\n output prbs_tap_inc_r;\n output \\match_flag_or_reg[0]_0 ;\n output \\largest_left_edge_reg[0]_0 ;\n output [7:0]D;\n output prbs_rdlvl_done_reg_0;\n output \\stg1_wr_rd_cnt_reg[3] ;\n output prbs_last_byte_done;\n output reset_rd_addr;\n output complex_init_pi_dec_done;\n output complex_pi_incdec_done;\n output \\prbs_dqs_cnt_r_reg[2]_0 ;\n output complex_oclkdelay_calib_done_r1_reg;\n output p_154_out;\n output p_95_out;\n output \\genblk8[7].right_edge_pb_reg[42]_1 ;\n output p_98_out;\n output p_103_out;\n output p_106_out;\n output \\genblk8[5].right_edge_pb_reg[30]_1 ;\n output \\genblk8[5].right_gain_pb_reg[30]_0 ;\n output p_119_out;\n output p_122_out;\n output p_127_out;\n output p_130_out;\n output \\genblk8[2].right_edge_pb_reg[12]_1 ;\n output \\genblk8[2].right_edge_pb_reg[12]_2 ;\n output p_143_out;\n output p_146_out;\n output \\genblk8[0].right_edge_pb_reg[0]_1 ;\n output \\genblk8[0].left_loss_pb_reg[0]_1 ;\n output [4:0]Q;\n output num_samples_done_r;\n output prbs_state_r178_out;\n output bit_cnt;\n output \\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ;\n output right_edge_found_reg_1;\n output [1:0]\\prbs_dec_tap_cnt_reg[1]_0 ;\n output reset_rd_addr0;\n output \\genblk8[7].left_edge_updated_reg[7]_0 ;\n output \\rd_victim_sel_reg[2]_0 ;\n output \\oclkdelay_ref_cnt_reg[0] ;\n output prbs_rdlvl_done_pulse0;\n output \\init_state_r_reg[0] ;\n output \\init_state_r_reg[1] ;\n output \\init_state_r_reg[0]_0 ;\n output \\init_state_r_reg[1]_0 ;\n output \\fine_delay_mod_reg[5] ;\n output \\fine_delay_mod_reg[20] ;\n output [2:0]\\rdlvl_cpt_tap_cnt_reg[5]_1 ;\n output right_gain_pb;\n output right_edge_found;\n output no_err_win_detected_reg_0;\n output prbs_found_1st_edge_r_reg_1;\n output prbs_tap_en_r_reg_0;\n output prbs_tap_en_r;\n output fine_delay_sel_reg_0;\n output no_err_win_detected_latch_reg_1;\n output fine_delay_sel_reg_1;\n output complex_pi_incdec_done_reg_0;\n output num_samples_done_ind_reg_0;\n output complex_pi_incdec_done_reg_1;\n output fine_dly_error_reg_0;\n output compare_err_latch_reg_0;\n output \\prbs_dqs_cnt_r_reg[1]_0 ;\n output prbs_rdlvl_done_reg_1;\n output prbs_last_byte_done_reg_0;\n output new_cnt_dqs_r_reg_0;\n output new_cnt_dqs_r;\n output \\rd_victim_sel_reg[2]_1 ;\n output \\rd_victim_sel_reg[2]_2 ;\n output \\rd_victim_sel_reg[2]_3 ;\n output \\fine_delay_mod_reg[26] ;\n output \\genblk9[1].fine_delay_incdec_pb_reg[1]_0 ;\n output \\genblk9[2].fine_delay_incdec_pb_reg[2]_0 ;\n output \\genblk9[3].fine_delay_incdec_pb_reg[3]_0 ;\n output \\genblk9[5].fine_delay_incdec_pb_reg[5]_0 ;\n output \\genblk9[6].fine_delay_incdec_pb_reg[6]_0 ;\n output \\genblk9[7].fine_delay_incdec_pb_reg[7]_0 ;\n input CLK;\n input prbs_rdlvl_start_reg;\n input \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n input rstdiv0_sync_r1_reg_rep__7;\n input \\dout_o_reg[7] ;\n input \\dout_o_reg[7]_0 ;\n input \\dout_o_reg[7]_1 ;\n input \\dout_o_reg[7]_2 ;\n input \\dout_o_reg[7]_3 ;\n input \\dout_o_reg[7]_4 ;\n input \\dout_o_reg[7]_5 ;\n input \\dout_o_reg[7]_6 ;\n input \\A[1]_1 ;\n input \\A[1]_2 ;\n input \\A[1]_3 ;\n input \\A[1]_4 ;\n input \\A[1]_5 ;\n input \\A[1]_6 ;\n input \\A[1]_7 ;\n input \\A[1]_8 ;\n input \\dout_o_reg[6] ;\n input \\dout_o_reg[6]_0 ;\n input \\dout_o_reg[6]_1 ;\n input \\dout_o_reg[6]_2 ;\n input \\dout_o_reg[6]_3 ;\n input \\dout_o_reg[6]_4 ;\n input \\dout_o_reg[6]_5 ;\n input \\dout_o_reg[6]_6 ;\n input \\A[1]_9 ;\n input \\A[1]_10 ;\n input \\A[1]_11 ;\n input \\A[1]_12 ;\n input \\A[1]_13 ;\n input \\A[1]_14 ;\n input \\A[1]_15 ;\n input \\A[1]_16 ;\n input \\dout_o_reg[5] ;\n input \\dout_o_reg[5]_0 ;\n input \\dout_o_reg[5]_1 ;\n input \\dout_o_reg[5]_2 ;\n input \\dout_o_reg[5]_3 ;\n input \\dout_o_reg[5]_4 ;\n input \\dout_o_reg[5]_5 ;\n input \\dout_o_reg[5]_6 ;\n input \\A[1]_17 ;\n input \\A[1]_18 ;\n input \\A[1]_19 ;\n input \\A[1]_20 ;\n input \\A[1]_21 ;\n input \\A[1]_22 ;\n input \\A[1]_23 ;\n input \\A[1]_24 ;\n input \\dout_o_reg[4] ;\n input \\dout_o_reg[4]_0 ;\n input \\dout_o_reg[4]_1 ;\n input \\dout_o_reg[4]_2 ;\n input \\dout_o_reg[4]_3 ;\n input \\dout_o_reg[4]_4 ;\n input \\dout_o_reg[4]_5 ;\n input \\dout_o_reg[4]_6 ;\n input \\A[1]_25 ;\n input \\A[1]_26 ;\n input \\A[1]_27 ;\n input \\A[1]_28 ;\n input \\A[1]_29 ;\n input \\A[1]_30 ;\n input \\A[1]_31 ;\n input \\A[1]_32 ;\n input \\dout_o_reg[3] ;\n input \\dout_o_reg[3]_0 ;\n input \\dout_o_reg[3]_1 ;\n input \\dout_o_reg[3]_2 ;\n input \\dout_o_reg[3]_3 ;\n input \\dout_o_reg[3]_4 ;\n input \\dout_o_reg[3]_5 ;\n input \\dout_o_reg[3]_6 ;\n input \\A[1]_33 ;\n input \\A[1]_34 ;\n input \\A[1]_35 ;\n input \\A[1]_36 ;\n input \\A[1]_37 ;\n input \\A[1]_38 ;\n input \\A[1]_39 ;\n input \\A[1]_40 ;\n input \\dout_o_reg[2] ;\n input \\dout_o_reg[2]_0 ;\n input \\dout_o_reg[2]_1 ;\n input \\dout_o_reg[2]_2 ;\n input \\dout_o_reg[2]_3 ;\n input \\dout_o_reg[2]_4 ;\n input \\dout_o_reg[2]_5 ;\n input \\dout_o_reg[2]_6 ;\n input \\A[1]_41 ;\n input \\A[1]_42 ;\n input \\A[1]_43 ;\n input \\A[1]_44 ;\n input \\A[1]_45 ;\n input \\A[1]_46 ;\n input \\A[1]_47 ;\n input \\A[1]_48 ;\n input \\dout_o_reg[1] ;\n input \\dout_o_reg[1]_0 ;\n input \\dout_o_reg[1]_1 ;\n input \\dout_o_reg[1]_2 ;\n input \\dout_o_reg[1]_3 ;\n input \\dout_o_reg[1]_4 ;\n input \\dout_o_reg[1]_5 ;\n input \\dout_o_reg[1]_6 ;\n input \\A[1]_49 ;\n input \\A[1]_50 ;\n input \\A[1]_51 ;\n input \\A[1]_52 ;\n input \\A[1]_53 ;\n input \\A[1]_54 ;\n input \\A[1]_55 ;\n input \\A[1]_56 ;\n input \\dout_o_reg[0] ;\n input \\dout_o_reg[0]_0 ;\n input \\dout_o_reg[0]_1 ;\n input \\dout_o_reg[0]_2 ;\n input \\dout_o_reg[0]_3 ;\n input \\dout_o_reg[0]_4 ;\n input \\dout_o_reg[0]_5 ;\n input \\dout_o_reg[0]_6 ;\n input \\A[1]_57 ;\n input \\A[1]_58 ;\n input \\A[1]_59 ;\n input \\A[1]_60 ;\n input \\A[1]_61 ;\n input \\A[1]_62 ;\n input \\A[1]_63 ;\n input \\A[1]_64 ;\n input rstdiv0_sync_r1_reg_rep__8;\n input rstdiv0_sync_r1_reg_rep__2;\n input \\prbs_state_r_reg[4]_0 ;\n input \\prbs_state_r_reg[3]_0 ;\n input \\genblk8[0].left_edge_found_pb_reg[0]_0 ;\n input \\genblk8[1].left_edge_found_pb_reg[1]_0 ;\n input \\genblk8[2].left_edge_found_pb_reg[2]_0 ;\n input \\genblk8[3].left_edge_found_pb_reg[3]_0 ;\n input \\genblk8[4].left_edge_found_pb_reg[4]_0 ;\n input \\genblk8[5].left_edge_found_pb_reg[5]_0 ;\n input \\genblk8[6].left_edge_found_pb_reg[6]_0 ;\n input \\genblk8[7].left_edge_found_pb_reg[7]_0 ;\n input \\genblk8[0].right_edge_found_pb_reg[0]_0 ;\n input \\genblk8[1].right_edge_found_pb_reg[1]_0 ;\n input \\genblk8[2].right_edge_found_pb_reg[2]_0 ;\n input \\genblk8[3].right_edge_found_pb_reg[3]_0 ;\n input \\genblk8[4].right_edge_found_pb_reg[4]_0 ;\n input \\genblk8[5].right_edge_found_pb_reg[5]_0 ;\n input \\genblk8[6].right_edge_found_pb_reg[6]_0 ;\n input \\genblk8[7].right_edge_found_pb_reg[7]_0 ;\n input \\prbs_state_r_reg[0]_0 ;\n input no_err_win_detected_reg_1;\n input new_cnt_dqs_r_reg_1;\n input \\prbs_state_r_reg[0]_1 ;\n input \\prbs_state_r_reg[0]_2 ;\n input \\prbs_state_r_reg[4]_1 ;\n input \\prbs_state_r_reg[3]_1 ;\n input \\genblk8[0].left_edge_updated_reg[0]_0 ;\n input \\genblk8[1].left_edge_updated_reg[1]_0 ;\n input \\genblk8[2].left_edge_updated_reg[2]_0 ;\n input \\genblk8[3].left_edge_updated_reg[3]_0 ;\n input \\genblk8[4].left_edge_updated_reg[4]_0 ;\n input \\genblk8[5].left_edge_updated_reg[5]_0 ;\n input \\genblk8[6].left_edge_updated_reg[6]_0 ;\n input \\genblk8[7].left_edge_updated_reg[7]_1 ;\n input \\dec_cnt_reg[0]_0 ;\n input fine_dly_error_reg_1;\n input \\prbs_state_r_reg[0]_3 ;\n input prech_done_reg;\n input prbs_tap_inc_r_reg_0;\n input rstdiv0_sync_r1_reg_rep__9;\n input \\prbs_state_r_reg[4]_2 ;\n input \\prbs_state_r_reg[4]_3 ;\n input \\prbs_state_r_reg[0]_4 ;\n input \\prbs_dqs_cnt_r_reg[0]_0 ;\n input \\prbs_dqs_cnt_r_reg[0]_1 ;\n input \\prbs_dqs_cnt_r_reg[0]_2 ;\n input rstdiv0_sync_r1_reg_rep;\n input complex_ocal_reset_rd_addr;\n input [0:0]\\calib_sel_reg[3] ;\n input [3:0]\\pi_counter_read_val_reg[5] ;\n input rstdiv0_sync_r1_reg_rep__24;\n input oclkdelay_center_calib_done_r_reg;\n input ocal_last_byte_done;\n input prbs_rdlvl_done_r1;\n input rdlvl_stg1_done_int_reg;\n input wrcal_done_reg;\n input dqs_found_done_r_reg;\n input \\num_refresh_reg[1] ;\n input wrlvl_final_mux;\n input rdlvl_stg1_start_int;\n input rdlvl_last_byte_done;\n input \\one_rank.stg1_wr_done_reg ;\n input \\A[2]__2 ;\n input \\calib_sel_reg[3]_0 ;\n input \\calib_sel_reg[3]_1 ;\n input \\calib_sel_reg[3]_2 ;\n input rstdiv0_sync_r1_reg_rep__23;\n input complex_act_start;\n input prech_done;\n input prbs_rdlvl_start_reg_0;\n input [0:0]E;\n input \\stage_cnt_reg[1]_0 ;\n\n wire [1:0]A;\n wire \\A[0]_0 ;\n wire \\A[1]_0 ;\n wire \\A[1]_1 ;\n wire \\A[1]_10 ;\n wire \\A[1]_11 ;\n wire \\A[1]_12 ;\n wire \\A[1]_13 ;\n wire \\A[1]_14 ;\n wire \\A[1]_15 ;\n wire \\A[1]_16 ;\n wire \\A[1]_17 ;\n wire \\A[1]_18 ;\n wire \\A[1]_19 ;\n wire \\A[1]_2 ;\n wire \\A[1]_20 ;\n wire \\A[1]_21 ;\n wire \\A[1]_22 ;\n wire \\A[1]_23 ;\n wire \\A[1]_24 ;\n wire \\A[1]_25 ;\n wire \\A[1]_26 ;\n wire \\A[1]_27 ;\n wire \\A[1]_28 ;\n wire \\A[1]_29 ;\n wire \\A[1]_3 ;\n wire \\A[1]_30 ;\n wire \\A[1]_31 ;\n wire \\A[1]_32 ;\n wire \\A[1]_33 ;\n wire \\A[1]_34 ;\n wire \\A[1]_35 ;\n wire \\A[1]_36 ;\n wire \\A[1]_37 ;\n wire \\A[1]_38 ;\n wire \\A[1]_39 ;\n wire \\A[1]_4 ;\n wire \\A[1]_40 ;\n wire \\A[1]_41 ;\n wire \\A[1]_42 ;\n wire \\A[1]_43 ;\n wire \\A[1]_44 ;\n wire \\A[1]_45 ;\n wire \\A[1]_46 ;\n wire \\A[1]_47 ;\n wire \\A[1]_48 ;\n wire \\A[1]_49 ;\n wire \\A[1]_5 ;\n wire \\A[1]_50 ;\n wire \\A[1]_51 ;\n wire \\A[1]_52 ;\n wire \\A[1]_53 ;\n wire \\A[1]_54 ;\n wire \\A[1]_55 ;\n wire \\A[1]_56 ;\n wire \\A[1]_57 ;\n wire \\A[1]_58 ;\n wire \\A[1]_59 ;\n wire \\A[1]_6 ;\n wire \\A[1]_60 ;\n wire \\A[1]_61 ;\n wire \\A[1]_62 ;\n wire \\A[1]_63 ;\n wire \\A[1]_64 ;\n wire \\A[1]_7 ;\n wire \\A[1]_8 ;\n wire \\A[1]_9 ;\n wire \\A[2]__2 ;\n wire CLK;\n wire [7:0]D;\n wire [0:0]E;\n wire [4:0]Q;\n wire bit_cnt;\n wire bit_cnt0;\n wire \\bit_cnt[7]_i_3_n_0 ;\n wire \\bit_cnt[7]_i_4_n_0 ;\n wire [7:0]bit_cnt_reg__0;\n wire [0:0]\\calib_sel_reg[3] ;\n wire \\calib_sel_reg[3]_0 ;\n wire \\calib_sel_reg[3]_1 ;\n wire \\calib_sel_reg[3]_2 ;\n wire \\cmp_err_4to1.compare_err_f0_i_2_n_0 ;\n wire \\cmp_err_4to1.compare_err_f0_i_3_n_0 ;\n wire \\cmp_err_4to1.compare_err_f0_reg_n_0 ;\n wire \\cmp_err_4to1.compare_err_f1_i_2_n_0 ;\n wire \\cmp_err_4to1.compare_err_f1_i_3_n_0 ;\n wire \\cmp_err_4to1.compare_err_f1_reg_n_0 ;\n wire \\cmp_err_4to1.compare_err_f2_i_2_n_0 ;\n wire \\cmp_err_4to1.compare_err_f2_i_3_n_0 ;\n wire \\cmp_err_4to1.compare_err_f2_reg_n_0 ;\n wire \\cmp_err_4to1.compare_err_f3_i_2_n_0 ;\n wire \\cmp_err_4to1.compare_err_f3_i_3_n_0 ;\n wire \\cmp_err_4to1.compare_err_f3_reg_n_0 ;\n wire \\cmp_err_4to1.compare_err_i_4_n_0 ;\n wire \\cmp_err_4to1.compare_err_r0_i_2_n_0 ;\n wire \\cmp_err_4to1.compare_err_r0_i_3_n_0 ;\n wire \\cmp_err_4to1.compare_err_r0_reg_n_0 ;\n wire \\cmp_err_4to1.compare_err_r1_i_2_n_0 ;\n wire \\cmp_err_4to1.compare_err_r1_i_3_n_0 ;\n wire \\cmp_err_4to1.compare_err_r1_reg_n_0 ;\n wire \\cmp_err_4to1.compare_err_r2_i_2_n_0 ;\n wire \\cmp_err_4to1.compare_err_r2_i_3_n_0 ;\n wire \\cmp_err_4to1.compare_err_r2_reg_n_0 ;\n wire \\cmp_err_4to1.compare_err_r3_i_2_n_0 ;\n wire \\cmp_err_4to1.compare_err_r3_i_3_n_0 ;\n wire \\cmp_err_4to1.compare_err_r3_reg_n_0 ;\n wire \\cmp_err_4to1.compare_err_reg_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_5_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_6_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_7_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_2_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_3_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_4_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_2_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_3_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_4_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_2_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_3_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_4_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_2_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_3_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_4_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_2_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_3_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_4_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_2_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_3_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_4_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_2_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_3_n_0 ;\n wire \\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_4_n_0 ;\n wire cnt_wait_state;\n wire cnt_wait_state_i_1_n_0;\n wire compare_err0;\n wire compare_err086_out__0;\n wire compare_err2;\n wire compare_err_f00;\n wire compare_err_f10;\n wire compare_err_f20;\n wire compare_err_f30;\n wire compare_err_latch_i_1_n_0;\n wire compare_err_latch_i_2_n_0;\n wire compare_err_latch_reg_0;\n wire compare_err_latch_reg_n_0;\n wire [7:0]compare_err_pb;\n wire compare_err_pb_and2;\n wire compare_err_pb_and_i_1_n_0;\n wire compare_err_pb_and_i_2_n_0;\n wire compare_err_pb_and_i_3_n_0;\n wire compare_err_pb_and_reg_n_0;\n wire compare_err_pb_or_i_1_n_0;\n wire compare_err_pb_or_i_2_n_0;\n wire compare_err_pb_or_i_3_n_0;\n wire compare_err_r00;\n wire compare_err_r10;\n wire compare_err_r20;\n wire compare_err_r30;\n wire complex_act_start;\n wire complex_init_pi_dec_done;\n wire complex_ocal_reset_rd_addr;\n wire complex_oclkdelay_calib_done_r1_reg;\n wire complex_pi_incdec_done;\n wire complex_pi_incdec_done_i_3_n_0;\n wire complex_pi_incdec_done_i_4_n_0;\n wire complex_pi_incdec_done_i_5_n_0;\n wire complex_pi_incdec_done_i_6_n_0;\n wire complex_pi_incdec_done_reg_0;\n wire complex_pi_incdec_done_reg_1;\n wire complex_victim_inc__0;\n wire [11:1]data0;\n wire \\dec_cnt[0]_i_11_n_0 ;\n wire \\dec_cnt[0]_i_13_n_0 ;\n wire \\dec_cnt[0]_i_14_n_0 ;\n wire \\dec_cnt[0]_i_15_n_0 ;\n wire \\dec_cnt[0]_i_16_n_0 ;\n wire \\dec_cnt[0]_i_17_n_0 ;\n wire \\dec_cnt[0]_i_1_n_0 ;\n wire \\dec_cnt[0]_i_20_n_0 ;\n wire \\dec_cnt[0]_i_21_n_0 ;\n wire \\dec_cnt[0]_i_22_n_0 ;\n wire \\dec_cnt[0]_i_23_n_0 ;\n wire \\dec_cnt[0]_i_24_n_0 ;\n wire \\dec_cnt[0]_i_25_n_0 ;\n wire \\dec_cnt[0]_i_26_n_0 ;\n wire \\dec_cnt[0]_i_29_n_0 ;\n wire \\dec_cnt[0]_i_32_n_0 ;\n wire \\dec_cnt[0]_i_33_n_0 ;\n wire \\dec_cnt[0]_i_34_n_0 ;\n wire \\dec_cnt[0]_i_35_n_0 ;\n wire \\dec_cnt[0]_i_36_n_0 ;\n wire \\dec_cnt[0]_i_37_n_0 ;\n wire \\dec_cnt[0]_i_38_n_0 ;\n wire \\dec_cnt[0]_i_39_n_0 ;\n wire \\dec_cnt[0]_i_3_n_0 ;\n wire \\dec_cnt[0]_i_40_n_0 ;\n wire \\dec_cnt[0]_i_41_n_0 ;\n wire \\dec_cnt[0]_i_42_n_0 ;\n wire \\dec_cnt[0]_i_43_n_0 ;\n wire \\dec_cnt[0]_i_44_n_0 ;\n wire \\dec_cnt[0]_i_45_n_0 ;\n wire \\dec_cnt[0]_i_46_n_0 ;\n wire \\dec_cnt[0]_i_47_n_0 ;\n wire \\dec_cnt[0]_i_4_n_0 ;\n wire \\dec_cnt[0]_i_5_n_0 ;\n wire \\dec_cnt[0]_i_6_n_0 ;\n wire \\dec_cnt[0]_i_8_n_0 ;\n wire \\dec_cnt[0]_i_9_n_0 ;\n wire \\dec_cnt[1]_i_13_n_0 ;\n wire \\dec_cnt[1]_i_15_n_0 ;\n wire \\dec_cnt[1]_i_16_n_0 ;\n wire \\dec_cnt[1]_i_19_n_0 ;\n wire \\dec_cnt[1]_i_1_n_0 ;\n wire \\dec_cnt[1]_i_20_n_0 ;\n wire \\dec_cnt[1]_i_21_n_0 ;\n wire \\dec_cnt[1]_i_22_n_0 ;\n wire \\dec_cnt[1]_i_25_n_0 ;\n wire \\dec_cnt[1]_i_26_n_0 ;\n wire \\dec_cnt[1]_i_27_n_0 ;\n wire \\dec_cnt[1]_i_28_n_0 ;\n wire \\dec_cnt[1]_i_29_n_0 ;\n wire \\dec_cnt[1]_i_2_n_0 ;\n wire \\dec_cnt[1]_i_30_n_0 ;\n wire \\dec_cnt[1]_i_31_n_0 ;\n wire \\dec_cnt[1]_i_32_n_0 ;\n wire \\dec_cnt[1]_i_33_n_0 ;\n wire \\dec_cnt[1]_i_34_n_0 ;\n wire \\dec_cnt[1]_i_35_n_0 ;\n wire \\dec_cnt[1]_i_36_n_0 ;\n wire \\dec_cnt[1]_i_37_n_0 ;\n wire \\dec_cnt[1]_i_38_n_0 ;\n wire \\dec_cnt[1]_i_3_n_0 ;\n wire \\dec_cnt[1]_i_4_n_0 ;\n wire \\dec_cnt[1]_i_5_n_0 ;\n wire \\dec_cnt[1]_i_6_n_0 ;\n wire \\dec_cnt[1]_i_8_n_0 ;\n wire \\dec_cnt[1]_i_9_n_0 ;\n wire \\dec_cnt[2]_i_10_n_0 ;\n wire \\dec_cnt[2]_i_11_n_0 ;\n wire \\dec_cnt[2]_i_12_n_0 ;\n wire \\dec_cnt[2]_i_13_n_0 ;\n wire \\dec_cnt[2]_i_14_n_0 ;\n wire \\dec_cnt[2]_i_15_n_0 ;\n wire \\dec_cnt[2]_i_17_n_0 ;\n wire \\dec_cnt[2]_i_18_n_0 ;\n wire \\dec_cnt[2]_i_19_n_0 ;\n wire \\dec_cnt[2]_i_20_n_0 ;\n wire \\dec_cnt[2]_i_21_n_0 ;\n wire \\dec_cnt[2]_i_22_n_0 ;\n wire \\dec_cnt[2]_i_23_n_0 ;\n wire \\dec_cnt[2]_i_24_n_0 ;\n wire \\dec_cnt[2]_i_25_n_0 ;\n wire \\dec_cnt[2]_i_26_n_0 ;\n wire \\dec_cnt[2]_i_27_n_0 ;\n wire \\dec_cnt[2]_i_28_n_0 ;\n wire \\dec_cnt[2]_i_29_n_0 ;\n wire \\dec_cnt[2]_i_2_n_0 ;\n wire \\dec_cnt[2]_i_30_n_0 ;\n wire \\dec_cnt[2]_i_31_n_0 ;\n wire \\dec_cnt[2]_i_32_n_0 ;\n wire \\dec_cnt[2]_i_33_n_0 ;\n wire \\dec_cnt[2]_i_34_n_0 ;\n wire \\dec_cnt[2]_i_3_n_0 ;\n wire \\dec_cnt[2]_i_5_n_0 ;\n wire \\dec_cnt[2]_i_6_n_0 ;\n wire \\dec_cnt[2]_i_7_n_0 ;\n wire \\dec_cnt[3]_i_10_n_0 ;\n wire \\dec_cnt[3]_i_11_n_0 ;\n wire \\dec_cnt[3]_i_12_n_0 ;\n wire \\dec_cnt[3]_i_13_n_0 ;\n wire \\dec_cnt[3]_i_14_n_0 ;\n wire \\dec_cnt[3]_i_15_n_0 ;\n wire \\dec_cnt[3]_i_16_n_0 ;\n wire \\dec_cnt[3]_i_17_n_0 ;\n wire \\dec_cnt[3]_i_18_n_0 ;\n wire \\dec_cnt[3]_i_19_n_0 ;\n wire \\dec_cnt[3]_i_1_n_0 ;\n wire \\dec_cnt[3]_i_20_n_0 ;\n wire \\dec_cnt[3]_i_21_n_0 ;\n wire \\dec_cnt[3]_i_22_n_0 ;\n wire \\dec_cnt[3]_i_23_n_0 ;\n wire \\dec_cnt[3]_i_24_n_0 ;\n wire \\dec_cnt[3]_i_25_n_0 ;\n wire \\dec_cnt[3]_i_26_n_0 ;\n wire \\dec_cnt[3]_i_27_n_0 ;\n wire \\dec_cnt[3]_i_2_n_0 ;\n wire \\dec_cnt[3]_i_3_n_0 ;\n wire \\dec_cnt[3]_i_4_n_0 ;\n wire \\dec_cnt[3]_i_5_n_0 ;\n wire \\dec_cnt[3]_i_6_n_0 ;\n wire \\dec_cnt[3]_i_7_n_0 ;\n wire \\dec_cnt[3]_i_8_n_0 ;\n wire \\dec_cnt[3]_i_9_n_0 ;\n wire \\dec_cnt[4]_i_10_n_0 ;\n wire \\dec_cnt[4]_i_11_n_0 ;\n wire \\dec_cnt[4]_i_12_n_0 ;\n wire \\dec_cnt[4]_i_13_n_0 ;\n wire \\dec_cnt[4]_i_14_n_0 ;\n wire \\dec_cnt[4]_i_15_n_0 ;\n wire \\dec_cnt[4]_i_16_n_0 ;\n wire \\dec_cnt[4]_i_17_n_0 ;\n wire \\dec_cnt[4]_i_1_n_0 ;\n wire \\dec_cnt[4]_i_3_n_0 ;\n wire \\dec_cnt[4]_i_4_n_0 ;\n wire \\dec_cnt[4]_i_5_n_0 ;\n wire \\dec_cnt[4]_i_6_n_0 ;\n wire \\dec_cnt[4]_i_7_n_0 ;\n wire \\dec_cnt[4]_i_8_n_0 ;\n wire \\dec_cnt[4]_i_9_n_0 ;\n wire \\dec_cnt[5]_i_1_n_0 ;\n wire \\dec_cnt[5]_i_2_n_0 ;\n wire \\dec_cnt[5]_i_3_n_0 ;\n wire \\dec_cnt[5]_i_4_n_0 ;\n wire \\dec_cnt[5]_i_5_n_0 ;\n wire \\dec_cnt[5]_i_6_n_0 ;\n wire \\dec_cnt[5]_i_7_n_0 ;\n wire [4:1]dec_cnt_reg;\n wire \\dec_cnt_reg[0]_0 ;\n wire \\dec_cnt_reg[0]_i_10_n_0 ;\n wire \\dec_cnt_reg[0]_i_12_n_0 ;\n wire \\dec_cnt_reg[0]_i_18_n_0 ;\n wire \\dec_cnt_reg[0]_i_19_n_0 ;\n wire \\dec_cnt_reg[0]_i_27_n_0 ;\n wire \\dec_cnt_reg[0]_i_28_n_0 ;\n wire \\dec_cnt_reg[0]_i_2_n_0 ;\n wire \\dec_cnt_reg[0]_i_30_n_0 ;\n wire \\dec_cnt_reg[0]_i_31_n_0 ;\n wire \\dec_cnt_reg[0]_i_7_n_0 ;\n wire \\dec_cnt_reg[1]_i_10_n_0 ;\n wire \\dec_cnt_reg[1]_i_11_n_0 ;\n wire \\dec_cnt_reg[1]_i_12_n_0 ;\n wire \\dec_cnt_reg[1]_i_14_n_0 ;\n wire \\dec_cnt_reg[1]_i_17_n_0 ;\n wire \\dec_cnt_reg[1]_i_18_n_0 ;\n wire \\dec_cnt_reg[1]_i_23_n_0 ;\n wire \\dec_cnt_reg[1]_i_24_n_0 ;\n wire \\dec_cnt_reg[1]_i_7_n_0 ;\n wire \\dec_cnt_reg[2]_i_16_n_0 ;\n wire \\dec_cnt_reg[2]_i_1_n_0 ;\n wire \\dec_cnt_reg[2]_i_4_n_0 ;\n wire \\dec_cnt_reg[2]_i_8_n_0 ;\n wire \\dec_cnt_reg[2]_i_9_n_0 ;\n wire \\dec_cnt_reg[4]_i_2_n_0 ;\n wire \\dout_o_reg[0] ;\n wire \\dout_o_reg[0]_0 ;\n wire \\dout_o_reg[0]_1 ;\n wire \\dout_o_reg[0]_2 ;\n wire \\dout_o_reg[0]_3 ;\n wire \\dout_o_reg[0]_4 ;\n wire \\dout_o_reg[0]_5 ;\n wire \\dout_o_reg[0]_6 ;\n wire \\dout_o_reg[1] ;\n wire \\dout_o_reg[1]_0 ;\n wire \\dout_o_reg[1]_1 ;\n wire \\dout_o_reg[1]_2 ;\n wire \\dout_o_reg[1]_3 ;\n wire \\dout_o_reg[1]_4 ;\n wire \\dout_o_reg[1]_5 ;\n wire \\dout_o_reg[1]_6 ;\n wire \\dout_o_reg[2] ;\n wire \\dout_o_reg[2]_0 ;\n wire \\dout_o_reg[2]_1 ;\n wire \\dout_o_reg[2]_2 ;\n wire \\dout_o_reg[2]_3 ;\n wire \\dout_o_reg[2]_4 ;\n wire \\dout_o_reg[2]_5 ;\n wire \\dout_o_reg[2]_6 ;\n wire \\dout_o_reg[3] ;\n wire \\dout_o_reg[3]_0 ;\n wire \\dout_o_reg[3]_1 ;\n wire \\dout_o_reg[3]_2 ;\n wire \\dout_o_reg[3]_3 ;\n wire \\dout_o_reg[3]_4 ;\n wire \\dout_o_reg[3]_5 ;\n wire \\dout_o_reg[3]_6 ;\n wire \\dout_o_reg[4] ;\n wire \\dout_o_reg[4]_0 ;\n wire \\dout_o_reg[4]_1 ;\n wire \\dout_o_reg[4]_2 ;\n wire \\dout_o_reg[4]_3 ;\n wire \\dout_o_reg[4]_4 ;\n wire \\dout_o_reg[4]_5 ;\n wire \\dout_o_reg[4]_6 ;\n wire \\dout_o_reg[5] ;\n wire \\dout_o_reg[5]_0 ;\n wire \\dout_o_reg[5]_1 ;\n wire \\dout_o_reg[5]_2 ;\n wire \\dout_o_reg[5]_3 ;\n wire \\dout_o_reg[5]_4 ;\n wire \\dout_o_reg[5]_5 ;\n wire \\dout_o_reg[5]_6 ;\n wire \\dout_o_reg[6] ;\n wire \\dout_o_reg[6]_0 ;\n wire \\dout_o_reg[6]_1 ;\n wire \\dout_o_reg[6]_2 ;\n wire \\dout_o_reg[6]_3 ;\n wire \\dout_o_reg[6]_4 ;\n wire \\dout_o_reg[6]_5 ;\n wire \\dout_o_reg[6]_6 ;\n wire \\dout_o_reg[7] ;\n wire \\dout_o_reg[7]_0 ;\n wire \\dout_o_reg[7]_1 ;\n wire \\dout_o_reg[7]_2 ;\n wire \\dout_o_reg[7]_3 ;\n wire \\dout_o_reg[7]_4 ;\n wire \\dout_o_reg[7]_5 ;\n wire \\dout_o_reg[7]_6 ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n wire dqs_found_done_r_reg;\n wire err_chk_invalid;\n wire err_chk_invalid_i_1_n_0;\n wire \\fine_delay_mod_reg[20] ;\n wire \\fine_delay_mod_reg[26] ;\n wire \\fine_delay_mod_reg[5] ;\n wire fine_delay_sel_i_4_n_0;\n wire fine_delay_sel_r_reg;\n wire fine_delay_sel_reg_0;\n wire fine_delay_sel_reg_1;\n wire fine_dly_error_reg_0;\n wire fine_dly_error_reg_1;\n wire fine_inc_stage_i_1_n_0;\n wire fine_inc_stage_reg_n_0;\n wire fine_pi_dec_cnt;\n wire \\fine_pi_dec_cnt[0]_i_1_n_0 ;\n wire \\fine_pi_dec_cnt[0]_i_2_n_0 ;\n wire \\fine_pi_dec_cnt[1]_i_1_n_0 ;\n wire \\fine_pi_dec_cnt[1]_i_2_n_0 ;\n wire \\fine_pi_dec_cnt[2]_i_1_n_0 ;\n wire \\fine_pi_dec_cnt[2]_i_2_n_0 ;\n wire \\fine_pi_dec_cnt[3]_i_10_n_0 ;\n wire \\fine_pi_dec_cnt[3]_i_1_n_0 ;\n wire \\fine_pi_dec_cnt[3]_i_2_n_0 ;\n wire \\fine_pi_dec_cnt[3]_i_4_n_0 ;\n wire \\fine_pi_dec_cnt[3]_i_5_n_0 ;\n wire \\fine_pi_dec_cnt[3]_i_6_n_0 ;\n wire \\fine_pi_dec_cnt[3]_i_7_n_0 ;\n wire \\fine_pi_dec_cnt[3]_i_8_n_0 ;\n wire \\fine_pi_dec_cnt[3]_i_9_n_0 ;\n wire \\fine_pi_dec_cnt[4]_i_2_n_0 ;\n wire \\fine_pi_dec_cnt[4]_i_3_n_0 ;\n wire \\fine_pi_dec_cnt[5]_i_10_n_0 ;\n wire \\fine_pi_dec_cnt[5]_i_11_n_0 ;\n wire \\fine_pi_dec_cnt[5]_i_3_n_0 ;\n wire \\fine_pi_dec_cnt[5]_i_4_n_0 ;\n wire \\fine_pi_dec_cnt[5]_i_5_n_0 ;\n wire \\fine_pi_dec_cnt[5]_i_6_n_0 ;\n wire \\fine_pi_dec_cnt[5]_i_7_n_0 ;\n wire \\fine_pi_dec_cnt[5]_i_9_n_0 ;\n wire \\fine_pi_dec_cnt_reg[3]_i_3_n_0 ;\n wire \\fine_pi_dec_cnt_reg[3]_i_3_n_1 ;\n wire \\fine_pi_dec_cnt_reg[3]_i_3_n_2 ;\n wire \\fine_pi_dec_cnt_reg[3]_i_3_n_3 ;\n wire \\fine_pi_dec_cnt_reg[3]_i_3_n_4 ;\n wire \\fine_pi_dec_cnt_reg[3]_i_3_n_5 ;\n wire \\fine_pi_dec_cnt_reg[3]_i_3_n_6 ;\n wire \\fine_pi_dec_cnt_reg[3]_i_3_n_7 ;\n wire \\fine_pi_dec_cnt_reg[4]_i_1_n_0 ;\n wire \\fine_pi_dec_cnt_reg[5]_i_2_n_0 ;\n wire \\fine_pi_dec_cnt_reg[5]_i_8_n_3 ;\n wire \\fine_pi_dec_cnt_reg[5]_i_8_n_6 ;\n wire \\fine_pi_dec_cnt_reg[5]_i_8_n_7 ;\n wire \\fine_pi_dec_cnt_reg_n_0_[0] ;\n wire \\fine_pi_dec_cnt_reg_n_0_[1] ;\n wire \\fine_pi_dec_cnt_reg_n_0_[2] ;\n wire \\fine_pi_dec_cnt_reg_n_0_[3] ;\n wire \\fine_pi_dec_cnt_reg_n_0_[4] ;\n wire \\fine_pi_dec_cnt_reg_n_0_[5] ;\n wire \\gen_mux_div4.gen_rd_4[0].mux_rd_fall0_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[0].mux_rd_fall1_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[0].mux_rd_fall2_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[0].mux_rd_fall3_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[0].mux_rd_rise0_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[0].mux_rd_rise1_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[0].mux_rd_rise2_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[0].mux_rd_rise3_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r3_reg ;\n wire \\gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r2_reg ;\n wire \\gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r3_reg ;\n wire \\gen_mux_rd[0].compare_data_fall0_r1_reg ;\n wire \\gen_mux_rd[0].compare_data_fall1_r1_reg ;\n wire \\gen_mux_rd[0].compare_data_fall2_r1_reg ;\n wire \\gen_mux_rd[0].compare_data_fall3_r1_reg ;\n wire \\gen_mux_rd[0].compare_data_rise0_r1_reg ;\n wire \\gen_mux_rd[0].compare_data_rise1_r1_reg ;\n wire \\gen_mux_rd[0].compare_data_rise2_r1_reg ;\n wire \\gen_mux_rd[0].compare_data_rise3_r1_reg ;\n wire \\gen_mux_rd[1].compare_data_fall0_r1_reg ;\n wire \\gen_mux_rd[1].compare_data_fall1_r1_reg ;\n wire \\gen_mux_rd[1].compare_data_fall2_r1_reg ;\n wire \\gen_mux_rd[1].compare_data_fall3_r1_reg ;\n wire \\gen_mux_rd[1].compare_data_rise0_r1_reg ;\n wire \\gen_mux_rd[1].compare_data_rise1_r1_reg ;\n wire \\gen_mux_rd[1].compare_data_rise2_r1_reg ;\n wire \\gen_mux_rd[1].compare_data_rise3_r1_reg ;\n wire \\gen_mux_rd[1].mux_rd_fall0_r1_reg ;\n wire \\gen_mux_rd[1].mux_rd_fall1_r1_reg ;\n wire \\gen_mux_rd[1].mux_rd_fall2_r1_reg ;\n wire \\gen_mux_rd[1].mux_rd_fall3_r1_reg ;\n wire \\gen_mux_rd[1].mux_rd_rise0_r1_reg ;\n wire \\gen_mux_rd[1].mux_rd_rise1_r1_reg ;\n wire \\gen_mux_rd[1].mux_rd_rise2_r1_reg ;\n wire \\gen_mux_rd[1].mux_rd_rise3_r1_reg ;\n wire \\gen_mux_rd[2].compare_data_fall0_r1_reg ;\n wire \\gen_mux_rd[2].compare_data_fall1_r1_reg ;\n wire \\gen_mux_rd[2].compare_data_fall2_r1_reg ;\n wire \\gen_mux_rd[2].compare_data_fall3_r1_reg ;\n wire \\gen_mux_rd[2].compare_data_rise0_r1_reg ;\n wire \\gen_mux_rd[2].compare_data_rise1_r1_reg ;\n wire \\gen_mux_rd[2].compare_data_rise2_r1_reg ;\n wire \\gen_mux_rd[2].compare_data_rise3_r1_reg ;\n wire \\gen_mux_rd[2].mux_rd_fall0_r1_reg ;\n wire \\gen_mux_rd[2].mux_rd_fall1_r1_reg ;\n wire \\gen_mux_rd[2].mux_rd_fall2_r1_reg ;\n wire \\gen_mux_rd[2].mux_rd_fall3_r1_reg ;\n wire \\gen_mux_rd[2].mux_rd_rise0_r1_reg ;\n wire \\gen_mux_rd[2].mux_rd_rise1_r1_reg ;\n wire \\gen_mux_rd[2].mux_rd_rise2_r1_reg ;\n wire \\gen_mux_rd[2].mux_rd_rise3_r1_reg ;\n wire \\gen_mux_rd[3].compare_data_fall0_r1_reg ;\n wire \\gen_mux_rd[3].compare_data_fall1_r1_reg ;\n wire \\gen_mux_rd[3].compare_data_fall2_r1_reg ;\n wire \\gen_mux_rd[3].compare_data_fall3_r1_reg ;\n wire \\gen_mux_rd[3].compare_data_rise0_r1_reg ;\n wire \\gen_mux_rd[3].compare_data_rise1_r1_reg ;\n wire \\gen_mux_rd[3].compare_data_rise2_r1_reg ;\n wire \\gen_mux_rd[3].compare_data_rise3_r1_reg ;\n wire \\gen_mux_rd[3].mux_rd_fall0_r1_reg ;\n wire \\gen_mux_rd[3].mux_rd_fall1_r1_reg ;\n wire \\gen_mux_rd[3].mux_rd_fall2_r1_reg ;\n wire \\gen_mux_rd[3].mux_rd_fall3_r1_reg ;\n wire \\gen_mux_rd[3].mux_rd_rise0_r1_reg ;\n wire \\gen_mux_rd[3].mux_rd_rise1_r1_reg ;\n wire \\gen_mux_rd[3].mux_rd_rise2_r1_reg ;\n wire \\gen_mux_rd[3].mux_rd_rise3_r1_reg ;\n wire \\gen_mux_rd[4].compare_data_fall0_r1_reg ;\n wire \\gen_mux_rd[4].compare_data_fall1_r1_reg ;\n wire \\gen_mux_rd[4].compare_data_fall2_r1_reg ;\n wire \\gen_mux_rd[4].compare_data_fall3_r1_reg ;\n wire \\gen_mux_rd[4].compare_data_rise0_r1_reg ;\n wire \\gen_mux_rd[4].compare_data_rise1_r1_reg ;\n wire \\gen_mux_rd[4].compare_data_rise2_r1_reg ;\n wire \\gen_mux_rd[4].compare_data_rise3_r1_reg ;\n wire \\gen_mux_rd[4].mux_rd_fall0_r1_reg ;\n wire \\gen_mux_rd[4].mux_rd_fall1_r1_reg ;\n wire \\gen_mux_rd[4].mux_rd_fall2_r1_reg ;\n wire \\gen_mux_rd[4].mux_rd_fall3_r1_reg ;\n wire \\gen_mux_rd[4].mux_rd_rise0_r1_reg ;\n wire \\gen_mux_rd[4].mux_rd_rise1_r1_reg ;\n wire \\gen_mux_rd[4].mux_rd_rise2_r1_reg ;\n wire \\gen_mux_rd[4].mux_rd_rise3_r1_reg ;\n wire \\gen_mux_rd[5].compare_data_fall0_r1_reg ;\n wire \\gen_mux_rd[5].compare_data_fall1_r1_reg ;\n wire \\gen_mux_rd[5].compare_data_fall2_r1_reg ;\n wire \\gen_mux_rd[5].compare_data_fall3_r1_reg ;\n wire \\gen_mux_rd[5].compare_data_rise0_r1_reg ;\n wire \\gen_mux_rd[5].compare_data_rise1_r1_reg ;\n wire \\gen_mux_rd[5].compare_data_rise2_r1_reg ;\n wire \\gen_mux_rd[5].compare_data_rise3_r1_reg ;\n wire \\gen_mux_rd[5].mux_rd_fall0_r1_reg ;\n wire \\gen_mux_rd[5].mux_rd_fall1_r1_reg ;\n wire \\gen_mux_rd[5].mux_rd_fall2_r1_reg ;\n wire \\gen_mux_rd[5].mux_rd_fall3_r1_reg ;\n wire \\gen_mux_rd[5].mux_rd_rise0_r1_reg ;\n wire \\gen_mux_rd[5].mux_rd_rise1_r1_reg ;\n wire \\gen_mux_rd[5].mux_rd_rise2_r1_reg ;\n wire \\gen_mux_rd[5].mux_rd_rise3_r1_reg ;\n wire \\gen_mux_rd[6].compare_data_fall0_r1_reg ;\n wire \\gen_mux_rd[6].compare_data_fall1_r1_reg ;\n wire \\gen_mux_rd[6].compare_data_fall2_r1_reg ;\n wire \\gen_mux_rd[6].compare_data_fall3_r1_reg ;\n wire \\gen_mux_rd[6].compare_data_rise0_r1_reg ;\n wire \\gen_mux_rd[6].compare_data_rise1_r1_reg ;\n wire \\gen_mux_rd[6].compare_data_rise2_r1_reg ;\n wire \\gen_mux_rd[6].compare_data_rise3_r1_reg ;\n wire \\gen_mux_rd[6].mux_rd_fall0_r1_reg ;\n wire \\gen_mux_rd[6].mux_rd_fall1_r1_reg ;\n wire \\gen_mux_rd[6].mux_rd_fall2_r1_reg ;\n wire \\gen_mux_rd[6].mux_rd_fall3_r1_reg ;\n wire \\gen_mux_rd[6].mux_rd_rise0_r1_reg ;\n wire \\gen_mux_rd[6].mux_rd_rise1_r1_reg ;\n wire \\gen_mux_rd[6].mux_rd_rise2_r1_reg ;\n wire \\gen_mux_rd[6].mux_rd_rise3_r1_reg ;\n wire \\gen_mux_rd[7].compare_data_fall0_r1_reg ;\n wire \\gen_mux_rd[7].compare_data_fall1_r1_reg ;\n wire \\gen_mux_rd[7].compare_data_fall2_r1_reg ;\n wire \\gen_mux_rd[7].compare_data_fall3_r1_reg ;\n wire \\gen_mux_rd[7].compare_data_rise0_r1_reg ;\n wire \\gen_mux_rd[7].compare_data_rise1_r1_reg ;\n wire \\gen_mux_rd[7].compare_data_rise2_r1_reg ;\n wire \\gen_mux_rd[7].compare_data_rise3_r1_reg ;\n wire \\gen_mux_rd[7].mux_rd_fall0_r1_reg ;\n wire \\gen_mux_rd[7].mux_rd_fall1_r1_reg ;\n wire \\gen_mux_rd[7].mux_rd_fall2_r1_reg ;\n wire \\gen_mux_rd[7].mux_rd_fall3_r1_reg ;\n wire \\gen_mux_rd[7].mux_rd_rise0_r1_reg ;\n wire \\gen_mux_rd[7].mux_rd_rise1_r1_reg ;\n wire \\gen_mux_rd[7].mux_rd_rise2_r1_reg ;\n wire \\gen_mux_rd[7].mux_rd_rise3_r1_reg ;\n wire \\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 ;\n wire \\genblk7[0].compare_err_pb_latch_r[0]_i_2_n_0 ;\n wire \\genblk7[0].compare_err_pb_latch_r_reg_n_0_[0] ;\n wire \\genblk7[1].compare_err_pb_latch_r[1]_i_1_n_0 ;\n wire \\genblk7[1].compare_err_pb_latch_r_reg_n_0_[1] ;\n wire \\genblk7[2].compare_err_pb_latch_r[2]_i_1_n_0 ;\n wire \\genblk7[2].compare_err_pb_latch_r_reg_n_0_[2] ;\n wire \\genblk7[3].compare_err_pb_latch_r[3]_i_1_n_0 ;\n wire \\genblk7[3].compare_err_pb_latch_r_reg_n_0_[3] ;\n wire \\genblk7[4].compare_err_pb_latch_r[4]_i_1_n_0 ;\n wire \\genblk7[4].compare_err_pb_latch_r_reg_n_0_[4] ;\n wire \\genblk7[5].compare_err_pb_latch_r[5]_i_1_n_0 ;\n wire \\genblk7[5].compare_err_pb_latch_r_reg_n_0_[5] ;\n wire \\genblk7[6].compare_err_pb_latch_r[6]_i_1_n_0 ;\n wire \\genblk7[6].compare_err_pb_latch_r_reg_n_0_[6] ;\n wire \\genblk7[7].compare_err_pb_latch_r[7]_i_1_n_0 ;\n wire \\genblk7[7].compare_err_pb_latch_r_reg_n_0_[7] ;\n wire \\genblk8[0].left_edge_found_pb_reg[0]_0 ;\n wire \\genblk8[0].left_edge_pb[0]_i_1_n_0 ;\n wire \\genblk8[0].left_edge_pb[1]_i_1_n_0 ;\n wire \\genblk8[0].left_edge_pb[2]_i_1_n_0 ;\n wire \\genblk8[0].left_edge_pb[3]_i_1_n_0 ;\n wire \\genblk8[0].left_edge_pb[4]_i_1_n_0 ;\n wire \\genblk8[0].left_edge_pb[5]_i_1_n_0 ;\n wire \\genblk8[0].left_edge_pb[5]_i_3_n_0 ;\n wire \\genblk8[0].left_edge_pb[5]_i_5_n_0 ;\n wire \\genblk8[0].left_edge_pb_reg_n_0_[0] ;\n wire \\genblk8[0].left_edge_pb_reg_n_0_[1] ;\n wire \\genblk8[0].left_edge_pb_reg_n_0_[2] ;\n wire \\genblk8[0].left_edge_pb_reg_n_0_[3] ;\n wire \\genblk8[0].left_edge_pb_reg_n_0_[4] ;\n wire \\genblk8[0].left_edge_pb_reg_n_0_[5] ;\n wire \\genblk8[0].left_edge_updated_reg[0]_0 ;\n wire \\genblk8[0].left_loss_pb[0]_i_1_n_0 ;\n wire \\genblk8[0].left_loss_pb[1]_i_1_n_0 ;\n wire \\genblk8[0].left_loss_pb[2]_i_1_n_0 ;\n wire \\genblk8[0].left_loss_pb[3]_i_1_n_0 ;\n wire \\genblk8[0].left_loss_pb[3]_i_3_n_0 ;\n wire \\genblk8[0].left_loss_pb[3]_i_4_n_0 ;\n wire \\genblk8[0].left_loss_pb[3]_i_5_n_0 ;\n wire \\genblk8[0].left_loss_pb[3]_i_6_n_0 ;\n wire \\genblk8[0].left_loss_pb[3]_i_7_n_0 ;\n wire \\genblk8[0].left_loss_pb[3]_i_8_n_0 ;\n wire \\genblk8[0].left_loss_pb[4]_i_1_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_10_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_11_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_12_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_13_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_15_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_16_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_17_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_18_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_1_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_20_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_21_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_22_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_23_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_24_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_25_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_26_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_27_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_28_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_29_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_2_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_30_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_31_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_7_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_8_n_0 ;\n wire \\genblk8[0].left_loss_pb[5]_i_9_n_0 ;\n wire \\genblk8[0].left_loss_pb_reg[0]_0 ;\n wire \\genblk8[0].left_loss_pb_reg[0]_1 ;\n wire \\genblk8[0].left_loss_pb_reg[3]_i_2_n_0 ;\n wire \\genblk8[0].left_loss_pb_reg[3]_i_2_n_1 ;\n wire \\genblk8[0].left_loss_pb_reg[3]_i_2_n_2 ;\n wire \\genblk8[0].left_loss_pb_reg[3]_i_2_n_3 ;\n wire \\genblk8[0].left_loss_pb_reg[3]_i_2_n_4 ;\n wire \\genblk8[0].left_loss_pb_reg[3]_i_2_n_5 ;\n wire \\genblk8[0].left_loss_pb_reg[3]_i_2_n_6 ;\n wire \\genblk8[0].left_loss_pb_reg[3]_i_2_n_7 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_14_n_0 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_14_n_1 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_14_n_2 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_14_n_3 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_19_n_0 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_19_n_1 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_19_n_2 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_19_n_3 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_4_n_0 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_4_n_1 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_4_n_2 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_4_n_3 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_5_n_3 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_5_n_6 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_5_n_7 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_6_n_0 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_6_n_1 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_6_n_2 ;\n wire \\genblk8[0].left_loss_pb_reg[5]_i_6_n_3 ;\n wire [5:2]\\genblk8[0].left_loss_pb_reg__0 ;\n wire \\genblk8[0].left_loss_pb_reg_n_0_[0] ;\n wire \\genblk8[0].left_loss_pb_reg_n_0_[1] ;\n wire \\genblk8[0].match_flag_pb[7]_i_1_n_0 ;\n wire \\genblk8[0].right_edge_found_pb_reg[0]_0 ;\n wire \\genblk8[0].right_edge_pb[1]_i_1_n_0 ;\n wire \\genblk8[0].right_edge_pb[2]_i_1_n_0 ;\n wire \\genblk8[0].right_edge_pb[3]_i_1_n_0 ;\n wire \\genblk8[0].right_edge_pb[4]_i_1_n_0 ;\n wire \\genblk8[0].right_edge_pb[5]_i_1_n_0 ;\n wire \\genblk8[0].right_edge_pb[5]_i_2_n_0 ;\n wire \\genblk8[0].right_edge_pb[5]_i_3_n_0 ;\n wire \\genblk8[0].right_edge_pb_reg[0]_0 ;\n wire \\genblk8[0].right_edge_pb_reg[0]_1 ;\n wire \\genblk8[0].right_edge_pb_reg_n_0_[0] ;\n wire \\genblk8[0].right_edge_pb_reg_n_0_[1] ;\n wire \\genblk8[0].right_edge_pb_reg_n_0_[2] ;\n wire \\genblk8[0].right_edge_pb_reg_n_0_[3] ;\n wire \\genblk8[0].right_edge_pb_reg_n_0_[4] ;\n wire \\genblk8[0].right_edge_pb_reg_n_0_[5] ;\n wire \\genblk8[0].right_gain_pb[0]_i_1_n_0 ;\n wire \\genblk8[0].right_gain_pb[1]_i_1_n_0 ;\n wire \\genblk8[0].right_gain_pb[2]_i_1_n_0 ;\n wire \\genblk8[0].right_gain_pb[3]_i_10_n_0 ;\n wire \\genblk8[0].right_gain_pb[3]_i_11_n_0 ;\n wire \\genblk8[0].right_gain_pb[3]_i_1_n_0 ;\n wire \\genblk8[0].right_gain_pb[3]_i_4_n_0 ;\n wire \\genblk8[0].right_gain_pb[3]_i_5_n_0 ;\n wire \\genblk8[0].right_gain_pb[3]_i_6_n_0 ;\n wire \\genblk8[0].right_gain_pb[3]_i_7_n_0 ;\n wire \\genblk8[0].right_gain_pb[3]_i_8_n_0 ;\n wire \\genblk8[0].right_gain_pb[3]_i_9_n_0 ;\n wire \\genblk8[0].right_gain_pb[4]_i_1_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_11_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_12_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_13_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_14_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_15_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_16_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_17_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_18_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_19_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_1_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_20_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_23_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_24_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_25_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_26_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_27_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_28_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_2_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_30_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_31_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_32_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_33_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_35_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_36_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_37_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_38_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_3_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_40_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_41_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_42_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_43_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_44_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_45_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_46_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_47_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_48_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_49_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_50_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_52_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_53_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_54_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_55_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_56_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_57_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_58_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_59_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_60_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_61_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_62_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_8_n_0 ;\n wire \\genblk8[0].right_gain_pb[5]_i_9_n_0 ;\n wire \\genblk8[0].right_gain_pb_reg[3]_i_2_n_0 ;\n wire \\genblk8[0].right_gain_pb_reg[3]_i_2_n_1 ;\n wire \\genblk8[0].right_gain_pb_reg[3]_i_2_n_2 ;\n wire \\genblk8[0].right_gain_pb_reg[3]_i_2_n_3 ;\n wire \\genblk8[0].right_gain_pb_reg[3]_i_2_n_4 ;\n wire \\genblk8[0].right_gain_pb_reg[3]_i_2_n_5 ;\n wire \\genblk8[0].right_gain_pb_reg[3]_i_2_n_6 ;\n wire \\genblk8[0].right_gain_pb_reg[3]_i_2_n_7 ;\n wire \\genblk8[0].right_gain_pb_reg[3]_i_3_n_0 ;\n wire \\genblk8[0].right_gain_pb_reg[3]_i_3_n_1 ;\n wire \\genblk8[0].right_gain_pb_reg[3]_i_3_n_2 ;\n wire \\genblk8[0].right_gain_pb_reg[3]_i_3_n_3 ;\n wire \\genblk8[0].right_gain_pb_reg[3]_i_3_n_4 ;\n wire \\genblk8[0].right_gain_pb_reg[3]_i_3_n_5 ;\n wire \\genblk8[0].right_gain_pb_reg[3]_i_3_n_6 ;\n wire \\genblk8[0].right_gain_pb_reg[3]_i_3_n_7 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_10_n_0 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_10_n_1 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_10_n_2 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_10_n_3 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_21_n_0 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_21_n_1 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_21_n_2 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_21_n_3 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_22_n_0 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_22_n_1 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_22_n_2 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_22_n_3 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_29_n_0 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_29_n_1 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_29_n_2 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_29_n_3 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_34_n_0 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_34_n_1 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_34_n_2 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_34_n_3 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_39_n_0 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_39_n_1 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_39_n_2 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_39_n_3 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_4_n_0 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_51_n_0 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_51_n_1 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_51_n_2 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_51_n_3 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_5_n_1 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_5_n_2 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_5_n_3 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_6_n_3 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_6_n_6 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_6_n_7 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_7_n_3 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_7_n_6 ;\n wire \\genblk8[0].right_gain_pb_reg[5]_i_7_n_7 ;\n wire [5:2]\\genblk8[0].right_gain_pb_reg__0 ;\n wire \\genblk8[0].right_gain_pb_reg_n_0_[0] ;\n wire \\genblk8[0].right_gain_pb_reg_n_0_[1] ;\n wire \\genblk8[1].left_edge_found_pb_reg[1]_0 ;\n wire \\genblk8[1].left_edge_pb[11]_i_1_n_0 ;\n wire \\genblk8[1].left_edge_pb[11]_i_3_n_0 ;\n wire \\genblk8[1].left_edge_pb_reg_n_0_[10] ;\n wire \\genblk8[1].left_edge_pb_reg_n_0_[11] ;\n wire \\genblk8[1].left_edge_pb_reg_n_0_[6] ;\n wire \\genblk8[1].left_edge_pb_reg_n_0_[7] ;\n wire \\genblk8[1].left_edge_pb_reg_n_0_[8] ;\n wire \\genblk8[1].left_edge_pb_reg_n_0_[9] ;\n wire \\genblk8[1].left_edge_updated_reg[1]_0 ;\n wire \\genblk8[1].left_loss_pb[11]_i_1_n_0 ;\n wire \\genblk8[1].left_loss_pb_reg[6]_0 ;\n wire [5:2]\\genblk8[1].left_loss_pb_reg__0 ;\n wire \\genblk8[1].left_loss_pb_reg_n_0_[6] ;\n wire \\genblk8[1].left_loss_pb_reg_n_0_[7] ;\n wire \\genblk8[1].right_edge_found_pb_reg[1]_0 ;\n wire \\genblk8[1].right_edge_pb[11]_i_1_n_0 ;\n wire \\genblk8[1].right_edge_pb[11]_i_2_n_0 ;\n wire \\genblk8[1].right_edge_pb_reg[6]_0 ;\n wire \\genblk8[1].right_edge_pb_reg_n_0_[10] ;\n wire \\genblk8[1].right_edge_pb_reg_n_0_[11] ;\n wire \\genblk8[1].right_edge_pb_reg_n_0_[6] ;\n wire \\genblk8[1].right_edge_pb_reg_n_0_[7] ;\n wire \\genblk8[1].right_edge_pb_reg_n_0_[8] ;\n wire \\genblk8[1].right_edge_pb_reg_n_0_[9] ;\n wire \\genblk8[1].right_gain_pb[10]_i_1_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_10_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_11_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_12_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_13_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_14_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_16_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_17_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_19_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_1_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_20_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_21_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_22_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_24_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_25_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_26_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_27_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_29_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_2_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_30_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_31_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_32_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_33_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_34_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_35_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_36_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_37_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_38_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_39_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_3_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_7_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_8_n_0 ;\n wire \\genblk8[1].right_gain_pb[11]_i_9_n_0 ;\n wire \\genblk8[1].right_gain_pb[6]_i_1_n_0 ;\n wire \\genblk8[1].right_gain_pb[7]_i_1_n_0 ;\n wire \\genblk8[1].right_gain_pb[8]_i_1_n_0 ;\n wire \\genblk8[1].right_gain_pb[9]_i_10_n_0 ;\n wire \\genblk8[1].right_gain_pb[9]_i_11_n_0 ;\n wire \\genblk8[1].right_gain_pb[9]_i_1_n_0 ;\n wire \\genblk8[1].right_gain_pb[9]_i_4_n_0 ;\n wire \\genblk8[1].right_gain_pb[9]_i_5_n_0 ;\n wire \\genblk8[1].right_gain_pb[9]_i_6_n_0 ;\n wire \\genblk8[1].right_gain_pb[9]_i_7_n_0 ;\n wire \\genblk8[1].right_gain_pb[9]_i_8_n_0 ;\n wire \\genblk8[1].right_gain_pb[9]_i_9_n_0 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_15_n_0 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_15_n_1 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_15_n_2 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_15_n_3 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_18_n_0 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_18_n_1 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_18_n_2 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_18_n_3 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_23_n_0 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_23_n_1 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_23_n_2 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_23_n_3 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_28_n_0 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_28_n_1 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_28_n_2 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_28_n_3 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_4_n_0 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_5_n_3 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_5_n_6 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_5_n_7 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_6_n_3 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_6_n_6 ;\n wire \\genblk8[1].right_gain_pb_reg[11]_i_6_n_7 ;\n wire \\genblk8[1].right_gain_pb_reg[9]_i_2_n_0 ;\n wire \\genblk8[1].right_gain_pb_reg[9]_i_2_n_1 ;\n wire \\genblk8[1].right_gain_pb_reg[9]_i_2_n_2 ;\n wire \\genblk8[1].right_gain_pb_reg[9]_i_2_n_3 ;\n wire \\genblk8[1].right_gain_pb_reg[9]_i_2_n_4 ;\n wire \\genblk8[1].right_gain_pb_reg[9]_i_2_n_5 ;\n wire \\genblk8[1].right_gain_pb_reg[9]_i_2_n_6 ;\n wire \\genblk8[1].right_gain_pb_reg[9]_i_2_n_7 ;\n wire \\genblk8[1].right_gain_pb_reg[9]_i_3_n_0 ;\n wire \\genblk8[1].right_gain_pb_reg[9]_i_3_n_1 ;\n wire \\genblk8[1].right_gain_pb_reg[9]_i_3_n_2 ;\n wire \\genblk8[1].right_gain_pb_reg[9]_i_3_n_3 ;\n wire \\genblk8[1].right_gain_pb_reg[9]_i_3_n_4 ;\n wire \\genblk8[1].right_gain_pb_reg[9]_i_3_n_5 ;\n wire \\genblk8[1].right_gain_pb_reg[9]_i_3_n_6 ;\n wire \\genblk8[1].right_gain_pb_reg[9]_i_3_n_7 ;\n wire [5:2]\\genblk8[1].right_gain_pb_reg__0 ;\n wire \\genblk8[1].right_gain_pb_reg_n_0_[6] ;\n wire \\genblk8[1].right_gain_pb_reg_n_0_[7] ;\n wire \\genblk8[2].left_edge_found_pb_reg[2]_0 ;\n wire \\genblk8[2].left_edge_pb[17]_i_1_n_0 ;\n wire \\genblk8[2].left_edge_pb[17]_i_3_n_0 ;\n wire \\genblk8[2].left_edge_pb_reg_n_0_[12] ;\n wire \\genblk8[2].left_edge_pb_reg_n_0_[13] ;\n wire \\genblk8[2].left_edge_pb_reg_n_0_[14] ;\n wire \\genblk8[2].left_edge_pb_reg_n_0_[15] ;\n wire \\genblk8[2].left_edge_pb_reg_n_0_[16] ;\n wire \\genblk8[2].left_edge_pb_reg_n_0_[17] ;\n wire \\genblk8[2].left_edge_updated_reg[2]_0 ;\n wire \\genblk8[2].left_loss_pb[17]_i_1_n_0 ;\n wire \\genblk8[2].left_loss_pb_reg[12]_0 ;\n wire [5:2]\\genblk8[2].left_loss_pb_reg__0 ;\n wire \\genblk8[2].left_loss_pb_reg_n_0_[12] ;\n wire \\genblk8[2].left_loss_pb_reg_n_0_[13] ;\n wire \\genblk8[2].right_edge_found_pb_reg[2]_0 ;\n wire \\genblk8[2].right_edge_pb[17]_i_1_n_0 ;\n wire \\genblk8[2].right_edge_pb[17]_i_2_n_0 ;\n wire \\genblk8[2].right_edge_pb_reg[12]_0 ;\n wire \\genblk8[2].right_edge_pb_reg[12]_1 ;\n wire \\genblk8[2].right_edge_pb_reg[12]_2 ;\n wire \\genblk8[2].right_edge_pb_reg_n_0_[12] ;\n wire \\genblk8[2].right_edge_pb_reg_n_0_[13] ;\n wire \\genblk8[2].right_edge_pb_reg_n_0_[14] ;\n wire \\genblk8[2].right_edge_pb_reg_n_0_[15] ;\n wire \\genblk8[2].right_edge_pb_reg_n_0_[16] ;\n wire \\genblk8[2].right_edge_pb_reg_n_0_[17] ;\n wire \\genblk8[2].right_gain_pb[12]_i_1_n_0 ;\n wire \\genblk8[2].right_gain_pb[13]_i_1_n_0 ;\n wire \\genblk8[2].right_gain_pb[14]_i_1_n_0 ;\n wire \\genblk8[2].right_gain_pb[15]_i_10_n_0 ;\n wire \\genblk8[2].right_gain_pb[15]_i_11_n_0 ;\n wire \\genblk8[2].right_gain_pb[15]_i_1_n_0 ;\n wire \\genblk8[2].right_gain_pb[15]_i_4_n_0 ;\n wire \\genblk8[2].right_gain_pb[15]_i_5_n_0 ;\n wire \\genblk8[2].right_gain_pb[15]_i_6_n_0 ;\n wire \\genblk8[2].right_gain_pb[15]_i_7_n_0 ;\n wire \\genblk8[2].right_gain_pb[15]_i_8_n_0 ;\n wire \\genblk8[2].right_gain_pb[15]_i_9_n_0 ;\n wire \\genblk8[2].right_gain_pb[16]_i_1_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_10_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_11_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_12_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_13_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_14_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_16_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_17_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_19_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_1_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_20_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_21_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_22_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_24_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_25_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_26_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_27_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_29_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_2_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_30_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_31_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_32_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_33_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_34_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_35_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_36_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_37_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_38_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_39_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_3_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_7_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_8_n_0 ;\n wire \\genblk8[2].right_gain_pb[17]_i_9_n_0 ;\n wire \\genblk8[2].right_gain_pb_reg[15]_i_2_n_0 ;\n wire \\genblk8[2].right_gain_pb_reg[15]_i_2_n_1 ;\n wire \\genblk8[2].right_gain_pb_reg[15]_i_2_n_2 ;\n wire \\genblk8[2].right_gain_pb_reg[15]_i_2_n_3 ;\n wire \\genblk8[2].right_gain_pb_reg[15]_i_2_n_4 ;\n wire \\genblk8[2].right_gain_pb_reg[15]_i_2_n_5 ;\n wire \\genblk8[2].right_gain_pb_reg[15]_i_2_n_6 ;\n wire \\genblk8[2].right_gain_pb_reg[15]_i_2_n_7 ;\n wire \\genblk8[2].right_gain_pb_reg[15]_i_3_n_0 ;\n wire \\genblk8[2].right_gain_pb_reg[15]_i_3_n_1 ;\n wire \\genblk8[2].right_gain_pb_reg[15]_i_3_n_2 ;\n wire \\genblk8[2].right_gain_pb_reg[15]_i_3_n_3 ;\n wire \\genblk8[2].right_gain_pb_reg[15]_i_3_n_4 ;\n wire \\genblk8[2].right_gain_pb_reg[15]_i_3_n_5 ;\n wire \\genblk8[2].right_gain_pb_reg[15]_i_3_n_6 ;\n wire \\genblk8[2].right_gain_pb_reg[15]_i_3_n_7 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_15_n_0 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_15_n_1 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_15_n_2 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_15_n_3 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_18_n_0 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_18_n_1 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_18_n_2 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_18_n_3 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_23_n_0 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_23_n_1 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_23_n_2 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_23_n_3 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_28_n_0 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_28_n_1 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_28_n_2 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_28_n_3 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_4_n_0 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_5_n_3 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_5_n_6 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_5_n_7 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_6_n_3 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_6_n_6 ;\n wire \\genblk8[2].right_gain_pb_reg[17]_i_6_n_7 ;\n wire [5:2]\\genblk8[2].right_gain_pb_reg__0 ;\n wire \\genblk8[2].right_gain_pb_reg_n_0_[12] ;\n wire \\genblk8[2].right_gain_pb_reg_n_0_[13] ;\n wire \\genblk8[3].left_edge_found_pb_reg[3]_0 ;\n wire \\genblk8[3].left_edge_pb[23]_i_1_n_0 ;\n wire \\genblk8[3].left_edge_pb[23]_i_3_n_0 ;\n wire \\genblk8[3].left_edge_pb_reg_n_0_[18] ;\n wire \\genblk8[3].left_edge_pb_reg_n_0_[19] ;\n wire \\genblk8[3].left_edge_pb_reg_n_0_[20] ;\n wire \\genblk8[3].left_edge_pb_reg_n_0_[21] ;\n wire \\genblk8[3].left_edge_pb_reg_n_0_[22] ;\n wire \\genblk8[3].left_edge_pb_reg_n_0_[23] ;\n wire \\genblk8[3].left_edge_updated_reg[3]_0 ;\n wire \\genblk8[3].left_loss_pb[23]_i_1_n_0 ;\n wire \\genblk8[3].left_loss_pb_reg[18]_0 ;\n wire [5:2]\\genblk8[3].left_loss_pb_reg__0 ;\n wire \\genblk8[3].left_loss_pb_reg_n_0_[18] ;\n wire \\genblk8[3].left_loss_pb_reg_n_0_[19] ;\n wire \\genblk8[3].right_edge_found_pb_reg[3]_0 ;\n wire \\genblk8[3].right_edge_pb[23]_i_1_n_0 ;\n wire \\genblk8[3].right_edge_pb[23]_i_2_n_0 ;\n wire \\genblk8[3].right_edge_pb_reg[18]_0 ;\n wire \\genblk8[3].right_edge_pb_reg_n_0_[18] ;\n wire \\genblk8[3].right_edge_pb_reg_n_0_[19] ;\n wire \\genblk8[3].right_edge_pb_reg_n_0_[20] ;\n wire \\genblk8[3].right_edge_pb_reg_n_0_[21] ;\n wire \\genblk8[3].right_edge_pb_reg_n_0_[22] ;\n wire \\genblk8[3].right_edge_pb_reg_n_0_[23] ;\n wire \\genblk8[3].right_gain_pb[18]_i_1_n_0 ;\n wire \\genblk8[3].right_gain_pb[19]_i_1_n_0 ;\n wire \\genblk8[3].right_gain_pb[20]_i_1_n_0 ;\n wire \\genblk8[3].right_gain_pb[21]_i_10_n_0 ;\n wire \\genblk8[3].right_gain_pb[21]_i_11_n_0 ;\n wire \\genblk8[3].right_gain_pb[21]_i_1_n_0 ;\n wire \\genblk8[3].right_gain_pb[21]_i_4_n_0 ;\n wire \\genblk8[3].right_gain_pb[21]_i_5_n_0 ;\n wire \\genblk8[3].right_gain_pb[21]_i_6_n_0 ;\n wire \\genblk8[3].right_gain_pb[21]_i_7_n_0 ;\n wire \\genblk8[3].right_gain_pb[21]_i_8_n_0 ;\n wire \\genblk8[3].right_gain_pb[21]_i_9_n_0 ;\n wire \\genblk8[3].right_gain_pb[22]_i_1_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_10_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_11_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_12_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_13_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_14_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_16_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_17_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_19_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_1_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_20_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_21_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_22_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_24_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_25_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_26_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_27_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_29_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_2_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_30_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_31_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_32_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_33_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_34_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_35_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_36_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_37_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_38_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_39_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_3_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_7_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_8_n_0 ;\n wire \\genblk8[3].right_gain_pb[23]_i_9_n_0 ;\n wire \\genblk8[3].right_gain_pb_reg[21]_i_2_n_0 ;\n wire \\genblk8[3].right_gain_pb_reg[21]_i_2_n_1 ;\n wire \\genblk8[3].right_gain_pb_reg[21]_i_2_n_2 ;\n wire \\genblk8[3].right_gain_pb_reg[21]_i_2_n_3 ;\n wire \\genblk8[3].right_gain_pb_reg[21]_i_2_n_4 ;\n wire \\genblk8[3].right_gain_pb_reg[21]_i_2_n_5 ;\n wire \\genblk8[3].right_gain_pb_reg[21]_i_2_n_6 ;\n wire \\genblk8[3].right_gain_pb_reg[21]_i_2_n_7 ;\n wire \\genblk8[3].right_gain_pb_reg[21]_i_3_n_0 ;\n wire \\genblk8[3].right_gain_pb_reg[21]_i_3_n_1 ;\n wire \\genblk8[3].right_gain_pb_reg[21]_i_3_n_2 ;\n wire \\genblk8[3].right_gain_pb_reg[21]_i_3_n_3 ;\n wire \\genblk8[3].right_gain_pb_reg[21]_i_3_n_4 ;\n wire \\genblk8[3].right_gain_pb_reg[21]_i_3_n_5 ;\n wire \\genblk8[3].right_gain_pb_reg[21]_i_3_n_6 ;\n wire \\genblk8[3].right_gain_pb_reg[21]_i_3_n_7 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_15_n_0 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_15_n_1 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_15_n_2 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_15_n_3 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_18_n_0 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_18_n_1 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_18_n_2 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_18_n_3 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_23_n_0 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_23_n_1 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_23_n_2 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_23_n_3 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_28_n_0 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_28_n_1 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_28_n_2 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_28_n_3 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_4_n_0 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_5_n_3 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_5_n_6 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_5_n_7 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_6_n_3 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_6_n_6 ;\n wire \\genblk8[3].right_gain_pb_reg[23]_i_6_n_7 ;\n wire [5:2]\\genblk8[3].right_gain_pb_reg__0 ;\n wire \\genblk8[3].right_gain_pb_reg_n_0_[18] ;\n wire \\genblk8[3].right_gain_pb_reg_n_0_[19] ;\n wire \\genblk8[4].left_edge_found_pb_reg[4]_0 ;\n wire \\genblk8[4].left_edge_pb[29]_i_1_n_0 ;\n wire \\genblk8[4].left_edge_pb[29]_i_3_n_0 ;\n wire \\genblk8[4].left_edge_pb_reg_n_0_[24] ;\n wire \\genblk8[4].left_edge_pb_reg_n_0_[25] ;\n wire \\genblk8[4].left_edge_pb_reg_n_0_[26] ;\n wire \\genblk8[4].left_edge_pb_reg_n_0_[27] ;\n wire \\genblk8[4].left_edge_pb_reg_n_0_[28] ;\n wire \\genblk8[4].left_edge_pb_reg_n_0_[29] ;\n wire \\genblk8[4].left_edge_updated_reg[4]_0 ;\n wire \\genblk8[4].left_loss_pb[29]_i_1_n_0 ;\n wire \\genblk8[4].left_loss_pb_reg[24]_0 ;\n wire [5:2]\\genblk8[4].left_loss_pb_reg__0 ;\n wire \\genblk8[4].left_loss_pb_reg_n_0_[24] ;\n wire \\genblk8[4].left_loss_pb_reg_n_0_[25] ;\n wire \\genblk8[4].right_edge_found_pb_reg[4]_0 ;\n wire \\genblk8[4].right_edge_pb[29]_i_1_n_0 ;\n wire \\genblk8[4].right_edge_pb[29]_i_2_n_0 ;\n wire \\genblk8[4].right_edge_pb_reg[24]_0 ;\n wire \\genblk8[4].right_edge_pb_reg_n_0_[24] ;\n wire \\genblk8[4].right_edge_pb_reg_n_0_[25] ;\n wire \\genblk8[4].right_edge_pb_reg_n_0_[26] ;\n wire \\genblk8[4].right_edge_pb_reg_n_0_[27] ;\n wire \\genblk8[4].right_edge_pb_reg_n_0_[28] ;\n wire \\genblk8[4].right_edge_pb_reg_n_0_[29] ;\n wire \\genblk8[4].right_gain_pb[24]_i_1_n_0 ;\n wire \\genblk8[4].right_gain_pb[25]_i_1_n_0 ;\n wire \\genblk8[4].right_gain_pb[26]_i_1_n_0 ;\n wire \\genblk8[4].right_gain_pb[27]_i_10_n_0 ;\n wire \\genblk8[4].right_gain_pb[27]_i_11_n_0 ;\n wire \\genblk8[4].right_gain_pb[27]_i_1_n_0 ;\n wire \\genblk8[4].right_gain_pb[27]_i_4_n_0 ;\n wire \\genblk8[4].right_gain_pb[27]_i_5_n_0 ;\n wire \\genblk8[4].right_gain_pb[27]_i_6_n_0 ;\n wire \\genblk8[4].right_gain_pb[27]_i_7_n_0 ;\n wire \\genblk8[4].right_gain_pb[27]_i_8_n_0 ;\n wire \\genblk8[4].right_gain_pb[27]_i_9_n_0 ;\n wire \\genblk8[4].right_gain_pb[28]_i_1_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_10_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_11_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_12_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_13_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_14_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_16_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_17_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_19_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_1_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_20_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_21_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_22_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_24_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_25_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_26_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_27_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_29_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_2_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_30_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_31_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_32_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_33_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_34_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_35_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_36_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_37_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_38_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_39_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_3_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_7_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_8_n_0 ;\n wire \\genblk8[4].right_gain_pb[29]_i_9_n_0 ;\n wire \\genblk8[4].right_gain_pb_reg[27]_i_2_n_0 ;\n wire \\genblk8[4].right_gain_pb_reg[27]_i_2_n_1 ;\n wire \\genblk8[4].right_gain_pb_reg[27]_i_2_n_2 ;\n wire \\genblk8[4].right_gain_pb_reg[27]_i_2_n_3 ;\n wire \\genblk8[4].right_gain_pb_reg[27]_i_2_n_4 ;\n wire \\genblk8[4].right_gain_pb_reg[27]_i_2_n_5 ;\n wire \\genblk8[4].right_gain_pb_reg[27]_i_2_n_6 ;\n wire \\genblk8[4].right_gain_pb_reg[27]_i_2_n_7 ;\n wire \\genblk8[4].right_gain_pb_reg[27]_i_3_n_0 ;\n wire \\genblk8[4].right_gain_pb_reg[27]_i_3_n_1 ;\n wire \\genblk8[4].right_gain_pb_reg[27]_i_3_n_2 ;\n wire \\genblk8[4].right_gain_pb_reg[27]_i_3_n_3 ;\n wire \\genblk8[4].right_gain_pb_reg[27]_i_3_n_4 ;\n wire \\genblk8[4].right_gain_pb_reg[27]_i_3_n_5 ;\n wire \\genblk8[4].right_gain_pb_reg[27]_i_3_n_6 ;\n wire \\genblk8[4].right_gain_pb_reg[27]_i_3_n_7 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_15_n_0 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_15_n_1 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_15_n_2 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_15_n_3 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_18_n_0 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_18_n_1 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_18_n_2 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_18_n_3 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_23_n_0 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_23_n_1 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_23_n_2 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_23_n_3 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_28_n_0 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_28_n_1 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_28_n_2 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_28_n_3 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_4_n_0 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_5_n_3 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_5_n_6 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_5_n_7 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_6_n_3 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_6_n_6 ;\n wire \\genblk8[4].right_gain_pb_reg[29]_i_6_n_7 ;\n wire [5:2]\\genblk8[4].right_gain_pb_reg__0 ;\n wire \\genblk8[4].right_gain_pb_reg_n_0_[24] ;\n wire \\genblk8[4].right_gain_pb_reg_n_0_[25] ;\n wire \\genblk8[5].left_edge_found_pb_reg[5]_0 ;\n wire \\genblk8[5].left_edge_pb[35]_i_1_n_0 ;\n wire \\genblk8[5].left_edge_pb[35]_i_3_n_0 ;\n wire \\genblk8[5].left_edge_pb_reg_n_0_[30] ;\n wire \\genblk8[5].left_edge_pb_reg_n_0_[31] ;\n wire \\genblk8[5].left_edge_pb_reg_n_0_[32] ;\n wire \\genblk8[5].left_edge_pb_reg_n_0_[33] ;\n wire \\genblk8[5].left_edge_pb_reg_n_0_[34] ;\n wire \\genblk8[5].left_edge_pb_reg_n_0_[35] ;\n wire \\genblk8[5].left_edge_updated_reg[5]_0 ;\n wire \\genblk8[5].left_loss_pb[35]_i_1_n_0 ;\n wire \\genblk8[5].left_loss_pb_reg[30]_0 ;\n wire [5:2]\\genblk8[5].left_loss_pb_reg__0 ;\n wire \\genblk8[5].left_loss_pb_reg_n_0_[30] ;\n wire \\genblk8[5].left_loss_pb_reg_n_0_[31] ;\n wire \\genblk8[5].right_edge_found_pb_reg[5]_0 ;\n wire \\genblk8[5].right_edge_pb[35]_i_1_n_0 ;\n wire \\genblk8[5].right_edge_pb[35]_i_2_n_0 ;\n wire \\genblk8[5].right_edge_pb_reg[30]_0 ;\n wire \\genblk8[5].right_edge_pb_reg[30]_1 ;\n wire \\genblk8[5].right_edge_pb_reg_n_0_[30] ;\n wire \\genblk8[5].right_edge_pb_reg_n_0_[31] ;\n wire \\genblk8[5].right_edge_pb_reg_n_0_[32] ;\n wire \\genblk8[5].right_edge_pb_reg_n_0_[33] ;\n wire \\genblk8[5].right_edge_pb_reg_n_0_[34] ;\n wire \\genblk8[5].right_edge_pb_reg_n_0_[35] ;\n wire \\genblk8[5].right_gain_pb[30]_i_1_n_0 ;\n wire \\genblk8[5].right_gain_pb[31]_i_1_n_0 ;\n wire \\genblk8[5].right_gain_pb[32]_i_1_n_0 ;\n wire \\genblk8[5].right_gain_pb[33]_i_10_n_0 ;\n wire \\genblk8[5].right_gain_pb[33]_i_11_n_0 ;\n wire \\genblk8[5].right_gain_pb[33]_i_1_n_0 ;\n wire \\genblk8[5].right_gain_pb[33]_i_4_n_0 ;\n wire \\genblk8[5].right_gain_pb[33]_i_5_n_0 ;\n wire \\genblk8[5].right_gain_pb[33]_i_6_n_0 ;\n wire \\genblk8[5].right_gain_pb[33]_i_7_n_0 ;\n wire \\genblk8[5].right_gain_pb[33]_i_8_n_0 ;\n wire \\genblk8[5].right_gain_pb[33]_i_9_n_0 ;\n wire \\genblk8[5].right_gain_pb[34]_i_1_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_10_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_11_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_12_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_13_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_14_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_16_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_17_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_19_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_1_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_20_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_21_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_22_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_24_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_25_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_26_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_27_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_29_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_2_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_30_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_31_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_32_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_33_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_34_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_35_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_36_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_37_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_38_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_39_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_3_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_7_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_8_n_0 ;\n wire \\genblk8[5].right_gain_pb[35]_i_9_n_0 ;\n wire \\genblk8[5].right_gain_pb_reg[30]_0 ;\n wire \\genblk8[5].right_gain_pb_reg[33]_i_2_n_0 ;\n wire \\genblk8[5].right_gain_pb_reg[33]_i_2_n_1 ;\n wire \\genblk8[5].right_gain_pb_reg[33]_i_2_n_2 ;\n wire \\genblk8[5].right_gain_pb_reg[33]_i_2_n_3 ;\n wire \\genblk8[5].right_gain_pb_reg[33]_i_2_n_4 ;\n wire \\genblk8[5].right_gain_pb_reg[33]_i_2_n_5 ;\n wire \\genblk8[5].right_gain_pb_reg[33]_i_2_n_6 ;\n wire \\genblk8[5].right_gain_pb_reg[33]_i_2_n_7 ;\n wire \\genblk8[5].right_gain_pb_reg[33]_i_3_n_0 ;\n wire \\genblk8[5].right_gain_pb_reg[33]_i_3_n_1 ;\n wire \\genblk8[5].right_gain_pb_reg[33]_i_3_n_2 ;\n wire \\genblk8[5].right_gain_pb_reg[33]_i_3_n_3 ;\n wire \\genblk8[5].right_gain_pb_reg[33]_i_3_n_4 ;\n wire \\genblk8[5].right_gain_pb_reg[33]_i_3_n_5 ;\n wire \\genblk8[5].right_gain_pb_reg[33]_i_3_n_6 ;\n wire \\genblk8[5].right_gain_pb_reg[33]_i_3_n_7 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_15_n_0 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_15_n_1 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_15_n_2 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_15_n_3 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_18_n_0 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_18_n_1 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_18_n_2 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_18_n_3 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_23_n_0 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_23_n_1 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_23_n_2 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_23_n_3 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_28_n_0 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_28_n_1 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_28_n_2 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_28_n_3 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_4_n_0 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_5_n_3 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_5_n_6 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_5_n_7 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_6_n_3 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_6_n_6 ;\n wire \\genblk8[5].right_gain_pb_reg[35]_i_6_n_7 ;\n wire [5:2]\\genblk8[5].right_gain_pb_reg__0 ;\n wire \\genblk8[5].right_gain_pb_reg_n_0_[30] ;\n wire \\genblk8[5].right_gain_pb_reg_n_0_[31] ;\n wire \\genblk8[6].left_edge_found_pb_reg[6]_0 ;\n wire \\genblk8[6].left_edge_pb[41]_i_1_n_0 ;\n wire \\genblk8[6].left_edge_pb[41]_i_3_n_0 ;\n wire \\genblk8[6].left_edge_pb_reg_n_0_[36] ;\n wire \\genblk8[6].left_edge_pb_reg_n_0_[37] ;\n wire \\genblk8[6].left_edge_pb_reg_n_0_[38] ;\n wire \\genblk8[6].left_edge_pb_reg_n_0_[39] ;\n wire \\genblk8[6].left_edge_pb_reg_n_0_[40] ;\n wire \\genblk8[6].left_edge_pb_reg_n_0_[41] ;\n wire \\genblk8[6].left_edge_updated_reg[6]_0 ;\n wire \\genblk8[6].left_loss_pb[41]_i_1_n_0 ;\n wire \\genblk8[6].left_loss_pb_reg[36]_0 ;\n wire [5:2]\\genblk8[6].left_loss_pb_reg__0 ;\n wire \\genblk8[6].left_loss_pb_reg_n_0_[36] ;\n wire \\genblk8[6].left_loss_pb_reg_n_0_[37] ;\n wire \\genblk8[6].right_edge_found_pb_reg[6]_0 ;\n wire \\genblk8[6].right_edge_pb[41]_i_1_n_0 ;\n wire \\genblk8[6].right_edge_pb[41]_i_2_n_0 ;\n wire \\genblk8[6].right_edge_pb_reg[36]_0 ;\n wire \\genblk8[6].right_edge_pb_reg_n_0_[36] ;\n wire \\genblk8[6].right_edge_pb_reg_n_0_[37] ;\n wire \\genblk8[6].right_edge_pb_reg_n_0_[38] ;\n wire \\genblk8[6].right_edge_pb_reg_n_0_[39] ;\n wire \\genblk8[6].right_edge_pb_reg_n_0_[40] ;\n wire \\genblk8[6].right_edge_pb_reg_n_0_[41] ;\n wire \\genblk8[6].right_gain_pb[36]_i_1_n_0 ;\n wire \\genblk8[6].right_gain_pb[37]_i_1_n_0 ;\n wire \\genblk8[6].right_gain_pb[38]_i_1_n_0 ;\n wire \\genblk8[6].right_gain_pb[39]_i_10_n_0 ;\n wire \\genblk8[6].right_gain_pb[39]_i_11_n_0 ;\n wire \\genblk8[6].right_gain_pb[39]_i_1_n_0 ;\n wire \\genblk8[6].right_gain_pb[39]_i_4_n_0 ;\n wire \\genblk8[6].right_gain_pb[39]_i_5_n_0 ;\n wire \\genblk8[6].right_gain_pb[39]_i_6_n_0 ;\n wire \\genblk8[6].right_gain_pb[39]_i_7_n_0 ;\n wire \\genblk8[6].right_gain_pb[39]_i_8_n_0 ;\n wire \\genblk8[6].right_gain_pb[39]_i_9_n_0 ;\n wire \\genblk8[6].right_gain_pb[40]_i_1_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_10_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_11_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_12_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_13_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_14_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_16_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_17_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_19_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_1_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_20_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_21_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_22_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_24_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_25_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_26_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_27_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_29_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_2_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_30_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_31_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_32_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_33_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_34_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_35_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_36_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_37_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_38_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_39_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_3_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_7_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_8_n_0 ;\n wire \\genblk8[6].right_gain_pb[41]_i_9_n_0 ;\n wire \\genblk8[6].right_gain_pb_reg[39]_i_2_n_0 ;\n wire \\genblk8[6].right_gain_pb_reg[39]_i_2_n_1 ;\n wire \\genblk8[6].right_gain_pb_reg[39]_i_2_n_2 ;\n wire \\genblk8[6].right_gain_pb_reg[39]_i_2_n_3 ;\n wire \\genblk8[6].right_gain_pb_reg[39]_i_2_n_4 ;\n wire \\genblk8[6].right_gain_pb_reg[39]_i_2_n_5 ;\n wire \\genblk8[6].right_gain_pb_reg[39]_i_2_n_6 ;\n wire \\genblk8[6].right_gain_pb_reg[39]_i_2_n_7 ;\n wire \\genblk8[6].right_gain_pb_reg[39]_i_3_n_0 ;\n wire \\genblk8[6].right_gain_pb_reg[39]_i_3_n_1 ;\n wire \\genblk8[6].right_gain_pb_reg[39]_i_3_n_2 ;\n wire \\genblk8[6].right_gain_pb_reg[39]_i_3_n_3 ;\n wire \\genblk8[6].right_gain_pb_reg[39]_i_3_n_4 ;\n wire \\genblk8[6].right_gain_pb_reg[39]_i_3_n_5 ;\n wire \\genblk8[6].right_gain_pb_reg[39]_i_3_n_6 ;\n wire \\genblk8[6].right_gain_pb_reg[39]_i_3_n_7 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_15_n_0 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_15_n_1 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_15_n_2 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_15_n_3 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_18_n_0 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_18_n_1 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_18_n_2 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_18_n_3 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_23_n_0 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_23_n_1 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_23_n_2 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_23_n_3 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_28_n_0 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_28_n_1 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_28_n_2 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_28_n_3 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_4_n_0 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_5_n_3 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_5_n_6 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_5_n_7 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_6_n_3 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_6_n_6 ;\n wire \\genblk8[6].right_gain_pb_reg[41]_i_6_n_7 ;\n wire [5:2]\\genblk8[6].right_gain_pb_reg__0 ;\n wire \\genblk8[6].right_gain_pb_reg_n_0_[36] ;\n wire \\genblk8[6].right_gain_pb_reg_n_0_[37] ;\n wire \\genblk8[7].left_edge_found_pb_reg[7]_0 ;\n wire \\genblk8[7].left_edge_pb[47]_i_1_n_0 ;\n wire \\genblk8[7].left_edge_pb[47]_i_3_n_0 ;\n wire \\genblk8[7].left_edge_pb_reg_n_0_[42] ;\n wire \\genblk8[7].left_edge_pb_reg_n_0_[43] ;\n wire \\genblk8[7].left_edge_pb_reg_n_0_[44] ;\n wire \\genblk8[7].left_edge_pb_reg_n_0_[45] ;\n wire \\genblk8[7].left_edge_pb_reg_n_0_[46] ;\n wire \\genblk8[7].left_edge_pb_reg_n_0_[47] ;\n wire \\genblk8[7].left_edge_updated_reg[7]_0 ;\n wire \\genblk8[7].left_edge_updated_reg[7]_1 ;\n wire \\genblk8[7].left_loss_pb[47]_i_1_n_0 ;\n wire \\genblk8[7].left_loss_pb_reg[42]_0 ;\n wire [5:2]\\genblk8[7].left_loss_pb_reg__0 ;\n wire \\genblk8[7].left_loss_pb_reg_n_0_[42] ;\n wire \\genblk8[7].left_loss_pb_reg_n_0_[43] ;\n wire \\genblk8[7].right_edge_found_pb_reg[7]_0 ;\n wire \\genblk8[7].right_edge_pb[47]_i_1_n_0 ;\n wire \\genblk8[7].right_edge_pb[47]_i_2_n_0 ;\n wire \\genblk8[7].right_edge_pb_reg[42]_0 ;\n wire \\genblk8[7].right_edge_pb_reg[42]_1 ;\n wire \\genblk8[7].right_edge_pb_reg_n_0_[42] ;\n wire \\genblk8[7].right_edge_pb_reg_n_0_[43] ;\n wire \\genblk8[7].right_edge_pb_reg_n_0_[44] ;\n wire \\genblk8[7].right_edge_pb_reg_n_0_[45] ;\n wire \\genblk8[7].right_edge_pb_reg_n_0_[46] ;\n wire \\genblk8[7].right_edge_pb_reg_n_0_[47] ;\n wire \\genblk8[7].right_gain_pb[42]_i_1_n_0 ;\n wire \\genblk8[7].right_gain_pb[43]_i_1_n_0 ;\n wire \\genblk8[7].right_gain_pb[44]_i_1_n_0 ;\n wire \\genblk8[7].right_gain_pb[45]_i_10_n_0 ;\n wire \\genblk8[7].right_gain_pb[45]_i_11_n_0 ;\n wire \\genblk8[7].right_gain_pb[45]_i_1_n_0 ;\n wire \\genblk8[7].right_gain_pb[45]_i_4_n_0 ;\n wire \\genblk8[7].right_gain_pb[45]_i_5_n_0 ;\n wire \\genblk8[7].right_gain_pb[45]_i_6_n_0 ;\n wire \\genblk8[7].right_gain_pb[45]_i_7_n_0 ;\n wire \\genblk8[7].right_gain_pb[45]_i_8_n_0 ;\n wire \\genblk8[7].right_gain_pb[45]_i_9_n_0 ;\n wire \\genblk8[7].right_gain_pb[46]_i_1_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_10_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_11_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_12_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_13_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_14_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_16_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_17_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_19_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_1_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_20_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_21_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_22_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_24_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_25_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_26_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_27_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_29_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_2_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_30_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_31_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_32_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_33_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_34_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_35_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_36_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_37_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_38_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_39_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_3_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_7_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_8_n_0 ;\n wire \\genblk8[7].right_gain_pb[47]_i_9_n_0 ;\n wire \\genblk8[7].right_gain_pb_reg[45]_i_2_n_0 ;\n wire \\genblk8[7].right_gain_pb_reg[45]_i_2_n_1 ;\n wire \\genblk8[7].right_gain_pb_reg[45]_i_2_n_2 ;\n wire \\genblk8[7].right_gain_pb_reg[45]_i_2_n_3 ;\n wire \\genblk8[7].right_gain_pb_reg[45]_i_2_n_4 ;\n wire \\genblk8[7].right_gain_pb_reg[45]_i_2_n_5 ;\n wire \\genblk8[7].right_gain_pb_reg[45]_i_2_n_6 ;\n wire \\genblk8[7].right_gain_pb_reg[45]_i_2_n_7 ;\n wire \\genblk8[7].right_gain_pb_reg[45]_i_3_n_0 ;\n wire \\genblk8[7].right_gain_pb_reg[45]_i_3_n_1 ;\n wire \\genblk8[7].right_gain_pb_reg[45]_i_3_n_2 ;\n wire \\genblk8[7].right_gain_pb_reg[45]_i_3_n_3 ;\n wire \\genblk8[7].right_gain_pb_reg[45]_i_3_n_4 ;\n wire \\genblk8[7].right_gain_pb_reg[45]_i_3_n_5 ;\n wire \\genblk8[7].right_gain_pb_reg[45]_i_3_n_6 ;\n wire \\genblk8[7].right_gain_pb_reg[45]_i_3_n_7 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_15_n_0 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_15_n_1 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_15_n_2 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_15_n_3 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_18_n_0 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_18_n_1 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_18_n_2 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_18_n_3 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_23_n_0 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_23_n_1 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_23_n_2 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_23_n_3 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_28_n_0 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_28_n_1 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_28_n_2 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_28_n_3 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_4_n_0 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_5_n_3 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_5_n_6 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_5_n_7 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_6_n_3 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_6_n_6 ;\n wire \\genblk8[7].right_gain_pb_reg[47]_i_6_n_7 ;\n wire [5:2]\\genblk8[7].right_gain_pb_reg__0 ;\n wire \\genblk8[7].right_gain_pb_reg_n_0_[42] ;\n wire \\genblk8[7].right_gain_pb_reg_n_0_[43] ;\n wire \\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ;\n wire \\genblk9[0].fine_delay_incdec_pb[0]_i_11_n_0 ;\n wire \\genblk9[0].fine_delay_incdec_pb[0]_i_1_n_0 ;\n wire \\genblk9[0].fine_delay_incdec_pb[0]_i_2_n_0 ;\n wire \\genblk9[0].fine_delay_incdec_pb[0]_i_4_n_0 ;\n wire \\genblk9[0].fine_delay_incdec_pb[0]_i_5_n_0 ;\n wire \\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ;\n wire \\genblk9[0].fine_delay_incdec_pb[0]_i_9_n_0 ;\n wire \\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ;\n wire \\genblk9[1].fine_delay_incdec_pb[1]_i_1_n_0 ;\n wire \\genblk9[1].fine_delay_incdec_pb[1]_i_2_n_0 ;\n wire \\genblk9[1].fine_delay_incdec_pb[1]_i_3_n_0 ;\n wire \\genblk9[1].fine_delay_incdec_pb[1]_i_4_n_0 ;\n wire \\genblk9[1].fine_delay_incdec_pb[1]_i_5_n_0 ;\n wire \\genblk9[1].fine_delay_incdec_pb_reg[1]_0 ;\n wire \\genblk9[2].fine_delay_incdec_pb[2]_i_1_n_0 ;\n wire \\genblk9[2].fine_delay_incdec_pb[2]_i_2_n_0 ;\n wire \\genblk9[2].fine_delay_incdec_pb[2]_i_3_n_0 ;\n wire \\genblk9[2].fine_delay_incdec_pb[2]_i_4_n_0 ;\n wire \\genblk9[2].fine_delay_incdec_pb[2]_i_5_n_0 ;\n wire \\genblk9[2].fine_delay_incdec_pb_reg[2]_0 ;\n wire \\genblk9[3].fine_delay_incdec_pb[3]_i_1_n_0 ;\n wire \\genblk9[3].fine_delay_incdec_pb[3]_i_2_n_0 ;\n wire \\genblk9[3].fine_delay_incdec_pb[3]_i_3_n_0 ;\n wire \\genblk9[3].fine_delay_incdec_pb[3]_i_4_n_0 ;\n wire \\genblk9[3].fine_delay_incdec_pb[3]_i_5_n_0 ;\n wire \\genblk9[3].fine_delay_incdec_pb_reg[3]_0 ;\n wire \\genblk9[4].fine_delay_incdec_pb[4]_i_1_n_0 ;\n wire \\genblk9[4].fine_delay_incdec_pb[4]_i_2_n_0 ;\n wire \\genblk9[4].fine_delay_incdec_pb[4]_i_3_n_0 ;\n wire \\genblk9[4].fine_delay_incdec_pb[4]_i_4_n_0 ;\n wire \\genblk9[4].fine_delay_incdec_pb[4]_i_5_n_0 ;\n wire \\genblk9[5].fine_delay_incdec_pb[5]_i_1_n_0 ;\n wire \\genblk9[5].fine_delay_incdec_pb[5]_i_2_n_0 ;\n wire \\genblk9[5].fine_delay_incdec_pb[5]_i_3_n_0 ;\n wire \\genblk9[5].fine_delay_incdec_pb[5]_i_4_n_0 ;\n wire \\genblk9[5].fine_delay_incdec_pb[5]_i_5_n_0 ;\n wire \\genblk9[5].fine_delay_incdec_pb_reg[5]_0 ;\n wire \\genblk9[6].fine_delay_incdec_pb[6]_i_1_n_0 ;\n wire \\genblk9[6].fine_delay_incdec_pb[6]_i_2_n_0 ;\n wire \\genblk9[6].fine_delay_incdec_pb[6]_i_3_n_0 ;\n wire \\genblk9[6].fine_delay_incdec_pb[6]_i_4_n_0 ;\n wire \\genblk9[6].fine_delay_incdec_pb[6]_i_5_n_0 ;\n wire \\genblk9[6].fine_delay_incdec_pb_reg[6]_0 ;\n wire \\genblk9[7].fine_delay_incdec_pb[7]_i_1_n_0 ;\n wire \\genblk9[7].fine_delay_incdec_pb[7]_i_2_n_0 ;\n wire \\genblk9[7].fine_delay_incdec_pb[7]_i_3_n_0 ;\n wire \\genblk9[7].fine_delay_incdec_pb[7]_i_4_n_0 ;\n wire \\genblk9[7].fine_delay_incdec_pb[7]_i_5_n_0 ;\n wire \\genblk9[7].fine_delay_incdec_pb_reg[7]_0 ;\n wire \\init_state_r_reg[0] ;\n wire \\init_state_r_reg[0]_0 ;\n wire \\init_state_r_reg[1] ;\n wire \\init_state_r_reg[1]_0 ;\n wire \\largest_left_edge[0]_i_1_n_0 ;\n wire \\largest_left_edge[1]_i_1_n_0 ;\n wire \\largest_left_edge[2]_i_1_n_0 ;\n wire \\largest_left_edge[3]_i_1_n_0 ;\n wire \\largest_left_edge[4]_i_1_n_0 ;\n wire \\largest_left_edge[5]_i_1_n_0 ;\n wire \\largest_left_edge[5]_i_2_n_0 ;\n wire \\largest_left_edge[5]_i_4_n_0 ;\n wire \\largest_left_edge[5]_i_5_n_0 ;\n wire \\largest_left_edge[5]_i_6_n_0 ;\n wire \\largest_left_edge_reg[0]_0 ;\n wire \\largest_left_edge_reg_n_0_[0] ;\n wire \\largest_left_edge_reg_n_0_[1] ;\n wire \\largest_left_edge_reg_n_0_[2] ;\n wire \\largest_left_edge_reg_n_0_[3] ;\n wire \\largest_left_edge_reg_n_0_[4] ;\n wire \\largest_left_edge_reg_n_0_[5] ;\n wire left_edge_pb;\n wire [5:0]left_edge_ref;\n wire \\left_edge_ref[0]_i_1_n_0 ;\n wire \\left_edge_ref[0]_i_2_n_0 ;\n wire \\left_edge_ref[0]_i_3_n_0 ;\n wire \\left_edge_ref[1]_i_1_n_0 ;\n wire \\left_edge_ref[1]_i_2_n_0 ;\n wire \\left_edge_ref[1]_i_3_n_0 ;\n wire \\left_edge_ref[2]_i_1_n_0 ;\n wire \\left_edge_ref[2]_i_2_n_0 ;\n wire \\left_edge_ref[2]_i_3_n_0 ;\n wire \\left_edge_ref[3]_i_1_n_0 ;\n wire \\left_edge_ref[3]_i_2_n_0 ;\n wire \\left_edge_ref[3]_i_3_n_0 ;\n wire \\left_edge_ref[4]_i_11_n_0 ;\n wire \\left_edge_ref[4]_i_12_n_0 ;\n wire \\left_edge_ref[4]_i_1_n_0 ;\n wire \\left_edge_ref[4]_i_2_n_0 ;\n wire \\left_edge_ref[4]_i_4_n_0 ;\n wire \\left_edge_ref[4]_i_5_n_0 ;\n wire \\left_edge_ref[4]_i_6_n_0 ;\n wire \\left_edge_ref[4]_i_7_n_0 ;\n wire \\left_edge_ref[4]_i_8_n_0 ;\n wire \\left_edge_ref[4]_i_9_n_0 ;\n wire \\left_edge_ref[5]_i_10_n_0 ;\n wire \\left_edge_ref[5]_i_11_n_0 ;\n wire \\left_edge_ref[5]_i_12_n_0 ;\n wire \\left_edge_ref[5]_i_13_n_0 ;\n wire \\left_edge_ref[5]_i_14_n_0 ;\n wire \\left_edge_ref[5]_i_15_n_0 ;\n wire \\left_edge_ref[5]_i_17_n_0 ;\n wire \\left_edge_ref[5]_i_18_n_0 ;\n wire \\left_edge_ref[5]_i_19_n_0 ;\n wire \\left_edge_ref[5]_i_1_n_0 ;\n wire \\left_edge_ref[5]_i_2_n_0 ;\n wire \\left_edge_ref[5]_i_5_n_0 ;\n wire \\left_edge_ref[5]_i_7_n_0 ;\n wire \\left_edge_ref[5]_i_8_n_0 ;\n wire \\left_edge_ref[5]_i_9_n_0 ;\n wire \\left_edge_ref_reg[4]_i_10_n_0 ;\n wire \\left_edge_ref_reg[4]_i_3_n_0 ;\n wire \\left_edge_ref_reg[5]_i_16_n_0 ;\n wire \\left_edge_ref_reg[5]_i_3_n_0 ;\n wire \\left_edge_ref_reg[5]_i_3_n_1 ;\n wire \\left_edge_ref_reg[5]_i_3_n_2 ;\n wire \\left_edge_ref_reg[5]_i_3_n_3 ;\n wire \\left_edge_ref_reg[5]_i_3_n_4 ;\n wire \\left_edge_ref_reg[5]_i_3_n_5 ;\n wire \\left_edge_ref_reg[5]_i_3_n_6 ;\n wire \\left_edge_ref_reg[5]_i_3_n_7 ;\n wire \\left_edge_ref_reg[5]_i_4_n_0 ;\n wire \\left_edge_ref_reg[5]_i_6_n_7 ;\n wire match_flag_and;\n wire \\match_flag_and[0]_i_1_n_0 ;\n wire \\match_flag_and[1]_i_1_n_0 ;\n wire \\match_flag_and[2]_i_1_n_0 ;\n wire \\match_flag_and[3]_i_1_n_0 ;\n wire \\match_flag_and[4]_i_1_n_0 ;\n wire \\match_flag_and[5]_i_1_n_0 ;\n wire \\match_flag_and[6]_i_1_n_0 ;\n wire \\match_flag_and[7]_i_2_n_0 ;\n wire \\match_flag_and[7]_i_3_n_0 ;\n wire \\match_flag_and_reg_n_0_[0] ;\n wire \\match_flag_and_reg_n_0_[1] ;\n wire \\match_flag_and_reg_n_0_[2] ;\n wire \\match_flag_and_reg_n_0_[3] ;\n wire \\match_flag_and_reg_n_0_[4] ;\n wire \\match_flag_and_reg_n_0_[5] ;\n wire \\match_flag_and_reg_n_0_[6] ;\n wire \\match_flag_and_reg_n_0_[7] ;\n wire \\match_flag_or[0]_i_1_n_0 ;\n wire \\match_flag_or[1]_i_1_n_0 ;\n wire \\match_flag_or[2]_i_1_n_0 ;\n wire \\match_flag_or[3]_i_1_n_0 ;\n wire \\match_flag_or[4]_i_1_n_0 ;\n wire \\match_flag_or[5]_i_1_n_0 ;\n wire \\match_flag_or[6]_i_1_n_0 ;\n wire \\match_flag_or_reg[0]_0 ;\n wire [63:0]match_flag_pb;\n wire mux_rd_fall0_r1;\n wire mux_rd_fall0_r2;\n wire mux_rd_fall1_r1;\n wire mux_rd_fall1_r2;\n wire mux_rd_fall2_r1;\n wire mux_rd_fall2_r2;\n wire mux_rd_fall3_r1;\n wire mux_rd_fall3_r2;\n wire mux_rd_rise0_r1;\n wire mux_rd_rise0_r2;\n wire mux_rd_rise1_r1;\n wire mux_rd_rise1_r2;\n wire mux_rd_rise2_r1;\n wire mux_rd_rise2_r2;\n wire mux_rd_rise3_r1;\n wire mux_rd_rise3_r2;\n wire mux_rd_valid_r;\n wire new_cnt_dqs_r;\n wire new_cnt_dqs_r_reg_0;\n wire new_cnt_dqs_r_reg_1;\n wire no_err_win_detected_i_1_n_0;\n wire no_err_win_detected_i_2_n_0;\n wire no_err_win_detected_i_3_n_0;\n wire no_err_win_detected_latch_reg_0;\n wire no_err_win_detected_latch_reg_1;\n wire no_err_win_detected_reg_0;\n wire no_err_win_detected_reg_1;\n wire \\num_refresh_reg[1] ;\n wire num_samples_done_ind_reg_0;\n wire num_samples_done_r;\n wire ocal_last_byte_done;\n wire oclkdelay_center_calib_done_r_reg;\n wire \\oclkdelay_ref_cnt_reg[0] ;\n wire \\one_rank.stg1_wr_done_reg ;\n wire [3:0]p_0_in;\n wire [7:0]p_0_in__0;\n wire p_103_out;\n wire p_106_out;\n wire p_10_out;\n wire p_119_out;\n wire p_122_out;\n wire p_127_out;\n wire p_130_out;\n wire p_143_out;\n wire p_146_out;\n wire p_154_out;\n wire p_19_out;\n wire p_1_in159_in;\n wire p_28_out;\n wire p_37_out;\n wire [0:0]p_3_in;\n wire p_46_out;\n wire p_55_out;\n wire p_64_out;\n wire p_66_out;\n wire p_75_out;\n wire p_95_out;\n wire p_98_out;\n wire [3:0]\\pi_counter_read_val_reg[5] ;\n wire pi_en_stg2_f_timing;\n wire pi_en_stg2_f_timing_reg_0;\n wire pi_stg2_f_incdec_timing;\n wire [5:0]prbs_dec_tap_cnt;\n wire \\prbs_dec_tap_cnt[0]_i_1_n_0 ;\n wire \\prbs_dec_tap_cnt[1]_i_1_n_0 ;\n wire \\prbs_dec_tap_cnt[2]_i_1_n_0 ;\n wire \\prbs_dec_tap_cnt[2]_i_2_n_0 ;\n wire \\prbs_dec_tap_cnt[2]_i_3_n_0 ;\n wire \\prbs_dec_tap_cnt[2]_i_4_n_0 ;\n wire \\prbs_dec_tap_cnt[3]_i_1_n_0 ;\n wire \\prbs_dec_tap_cnt[3]_i_2_n_0 ;\n wire \\prbs_dec_tap_cnt[4]_i_2_n_0 ;\n wire \\prbs_dec_tap_cnt[4]_i_3_n_0 ;\n wire \\prbs_dec_tap_cnt[5]_i_1_n_0 ;\n wire \\prbs_dec_tap_cnt[5]_i_4_n_0 ;\n wire \\prbs_dec_tap_cnt[5]_i_5_n_0 ;\n wire [1:0]\\prbs_dec_tap_cnt_reg[1]_0 ;\n wire \\prbs_dec_tap_cnt_reg[4]_i_1_n_0 ;\n wire \\prbs_dec_tap_cnt_reg[5]_i_2_n_0 ;\n wire \\prbs_dqs_cnt_r_reg[0]_0 ;\n wire \\prbs_dqs_cnt_r_reg[0]_1 ;\n wire \\prbs_dqs_cnt_r_reg[0]_2 ;\n wire \\prbs_dqs_cnt_r_reg[1]_0 ;\n wire \\prbs_dqs_cnt_r_reg[2]_0 ;\n wire \\prbs_dqs_tap_cnt_r[0]_i_1_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[0]_rep__0_i_1_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[0]_rep_i_1_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[1]_i_1_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[1]_rep__0_i_1_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[1]_rep_i_1_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[2]_i_1_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[3]_i_1_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[3]_i_2_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[3]_i_3_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[3]_rep__0_i_1_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[3]_rep_i_1_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[4]_i_1_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[4]_i_2_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[5]_i_2_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[5]_i_3_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[5]_i_4_n_0 ;\n wire \\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ;\n wire \\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ;\n wire \\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ;\n wire \\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ;\n wire \\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ;\n wire \\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ;\n wire \\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ;\n wire \\prbs_dqs_tap_cnt_r_reg_n_0_[0] ;\n wire \\prbs_dqs_tap_cnt_r_reg_n_0_[1] ;\n wire \\prbs_dqs_tap_cnt_r_reg_n_0_[2] ;\n wire \\prbs_dqs_tap_cnt_r_reg_n_0_[3] ;\n wire \\prbs_dqs_tap_cnt_r_reg_n_0_[4] ;\n wire \\prbs_dqs_tap_cnt_r_reg_n_0_[5] ;\n wire prbs_dqs_tap_limit_r;\n wire prbs_found_1st_edge_r_i_5_n_0;\n wire prbs_found_1st_edge_r_reg_0;\n wire prbs_found_1st_edge_r_reg_1;\n wire \\prbs_inc_tap_cnt[0]_i_1_n_0 ;\n wire \\prbs_inc_tap_cnt[1]_i_1_n_0 ;\n wire \\prbs_inc_tap_cnt[1]_i_2_n_0 ;\n wire \\prbs_inc_tap_cnt[2]_i_1_n_0 ;\n wire \\prbs_inc_tap_cnt[2]_i_2_n_0 ;\n wire \\prbs_inc_tap_cnt[2]_i_3_n_0 ;\n wire \\prbs_inc_tap_cnt[3]_i_1_n_0 ;\n wire \\prbs_inc_tap_cnt[3]_i_2_n_0 ;\n wire \\prbs_inc_tap_cnt[3]_i_3_n_0 ;\n wire \\prbs_inc_tap_cnt[3]_i_4_n_0 ;\n wire \\prbs_inc_tap_cnt[4]_i_1_n_0 ;\n wire \\prbs_inc_tap_cnt[4]_i_2_n_0 ;\n wire \\prbs_inc_tap_cnt[5]_i_1_n_0 ;\n wire \\prbs_inc_tap_cnt[5]_i_2_n_0 ;\n wire \\prbs_inc_tap_cnt[5]_i_3_n_0 ;\n wire \\prbs_inc_tap_cnt[5]_i_4_n_0 ;\n wire \\prbs_inc_tap_cnt[5]_i_5_n_0 ;\n wire \\prbs_inc_tap_cnt[5]_i_6_n_0 ;\n wire \\prbs_inc_tap_cnt[5]_i_7_n_0 ;\n wire \\prbs_inc_tap_cnt[5]_i_8_n_0 ;\n wire \\prbs_inc_tap_cnt[5]_i_9_n_0 ;\n wire \\prbs_inc_tap_cnt_reg_n_0_[0] ;\n wire \\prbs_inc_tap_cnt_reg_n_0_[1] ;\n wire \\prbs_inc_tap_cnt_reg_n_0_[2] ;\n wire \\prbs_inc_tap_cnt_reg_n_0_[3] ;\n wire \\prbs_inc_tap_cnt_reg_n_0_[4] ;\n wire \\prbs_inc_tap_cnt_reg_n_0_[5] ;\n wire prbs_last_byte_done;\n wire prbs_last_byte_done_reg_0;\n wire prbs_pi_stg2_f_en;\n wire prbs_pi_stg2_f_incdec;\n wire prbs_prech_req_r;\n wire prbs_rdlvl_done_pulse0;\n wire prbs_rdlvl_done_r1;\n wire prbs_rdlvl_done_reg_0;\n wire prbs_rdlvl_done_reg_1;\n wire prbs_rdlvl_start_r;\n wire prbs_rdlvl_start_reg;\n wire prbs_rdlvl_start_reg_0;\n wire prbs_state_r1;\n wire prbs_state_r178_out;\n wire \\prbs_state_r[0]_i_1_n_0 ;\n wire \\prbs_state_r[0]_i_2_n_0 ;\n wire \\prbs_state_r[0]_i_3_n_0 ;\n wire \\prbs_state_r[0]_i_4_n_0 ;\n wire \\prbs_state_r[0]_i_5_n_0 ;\n wire \\prbs_state_r[1]_i_1_n_0 ;\n wire \\prbs_state_r[1]_i_2_n_0 ;\n wire \\prbs_state_r[1]_i_3_n_0 ;\n wire \\prbs_state_r[1]_i_4_n_0 ;\n wire \\prbs_state_r[1]_i_5_n_0 ;\n wire \\prbs_state_r[1]_i_6_n_0 ;\n wire \\prbs_state_r[2]_i_10_n_0 ;\n wire \\prbs_state_r[2]_i_11_n_0 ;\n wire \\prbs_state_r[2]_i_2_n_0 ;\n wire \\prbs_state_r[2]_i_3_n_0 ;\n wire \\prbs_state_r[2]_i_4_n_0 ;\n wire \\prbs_state_r[2]_i_6_n_0 ;\n wire \\prbs_state_r[2]_i_7_n_0 ;\n wire \\prbs_state_r[2]_i_8_n_0 ;\n wire \\prbs_state_r[2]_i_9_n_0 ;\n wire \\prbs_state_r[3]_i_1_n_0 ;\n wire \\prbs_state_r[3]_i_2_n_0 ;\n wire \\prbs_state_r[3]_i_3_n_0 ;\n wire \\prbs_state_r[3]_i_4_n_0 ;\n wire \\prbs_state_r[4]_i_11_n_0 ;\n wire \\prbs_state_r[4]_i_2_n_0 ;\n wire \\prbs_state_r[4]_i_3_n_0 ;\n wire \\prbs_state_r[4]_i_4_n_0 ;\n wire \\prbs_state_r[4]_i_5_n_0 ;\n wire \\prbs_state_r[4]_i_6_n_0 ;\n wire \\prbs_state_r[4]_i_7_n_0 ;\n wire \\prbs_state_r[4]_i_8_n_0 ;\n wire \\prbs_state_r[4]_i_9_n_0 ;\n wire \\prbs_state_r_reg[0]_0 ;\n wire \\prbs_state_r_reg[0]_1 ;\n wire \\prbs_state_r_reg[0]_2 ;\n wire \\prbs_state_r_reg[0]_3 ;\n wire \\prbs_state_r_reg[0]_4 ;\n wire \\prbs_state_r_reg[2]_i_1_n_0 ;\n wire \\prbs_state_r_reg[3]_0 ;\n wire \\prbs_state_r_reg[3]_1 ;\n wire \\prbs_state_r_reg[4]_0 ;\n wire \\prbs_state_r_reg[4]_1 ;\n wire \\prbs_state_r_reg[4]_2 ;\n wire \\prbs_state_r_reg[4]_3 ;\n wire prbs_tap_en_r;\n wire prbs_tap_en_r_reg_0;\n wire prbs_tap_inc_r;\n wire prbs_tap_inc_r_i_3_n_0;\n wire prbs_tap_inc_r_reg_0;\n wire prech_done;\n wire prech_done_reg;\n wire prech_req_r_reg;\n wire rd_valid_r1;\n wire rd_valid_r2_reg_n_0;\n wire \\rd_victim_sel[0]_i_1_n_0 ;\n wire \\rd_victim_sel[1]_i_1_n_0 ;\n wire \\rd_victim_sel[2]_i_1_n_0 ;\n wire \\rd_victim_sel_reg[2]_0 ;\n wire \\rd_victim_sel_reg[2]_1 ;\n wire \\rd_victim_sel_reg[2]_2 ;\n wire \\rd_victim_sel_reg[2]_3 ;\n wire [5:0]rdlvl_cpt_tap_cnt;\n wire \\rdlvl_cpt_tap_cnt_reg[5]_0 ;\n wire [2:0]\\rdlvl_cpt_tap_cnt_reg[5]_1 ;\n wire rdlvl_last_byte_done;\n wire rdlvl_stg1_done_int_reg;\n wire rdlvl_stg1_start_int;\n wire [7:3]ref_bit;\n wire \\ref_bit[7]_i_3_n_0 ;\n wire \\ref_bit[7]_i_4_n_0 ;\n wire \\ref_bit[7]_i_5_n_0 ;\n wire \\ref_bit[7]_i_6_n_0 ;\n wire ref_bit_per_bit;\n wire ref_bit_per_bit0;\n wire \\ref_bit_per_bit[7]_i_2_n_0 ;\n wire \\ref_bit_per_bit[7]_i_3_n_0 ;\n wire \\ref_bit_per_bit_reg_n_0_[0] ;\n wire \\ref_bit_per_bit_reg_n_0_[1] ;\n wire \\ref_bit_per_bit_reg_n_0_[2] ;\n wire \\ref_bit_per_bit_reg_n_0_[3] ;\n wire \\ref_bit_per_bit_reg_n_0_[4] ;\n wire \\ref_bit_per_bit_reg_n_0_[5] ;\n wire \\ref_bit_per_bit_reg_n_0_[6] ;\n wire \\ref_bit_per_bit_reg_n_0_[7] ;\n wire \\ref_bit_reg_n_0_[0] ;\n wire \\ref_bit_reg_n_0_[1] ;\n wire \\ref_bit_reg_n_0_[2] ;\n wire ref_right_edge;\n wire ref_right_edge125_in;\n wire \\ref_right_edge[0]_i_1_n_0 ;\n wire \\ref_right_edge[0]_i_3_n_0 ;\n wire \\ref_right_edge[0]_i_4_n_0 ;\n wire \\ref_right_edge[1]_i_1_n_0 ;\n wire \\ref_right_edge[1]_i_3_n_0 ;\n wire \\ref_right_edge[1]_i_4_n_0 ;\n wire \\ref_right_edge[1]_i_5_n_0 ;\n wire \\ref_right_edge[1]_i_6_n_0 ;\n wire \\ref_right_edge[2]_i_1_n_0 ;\n wire \\ref_right_edge[2]_i_2_n_0 ;\n wire \\ref_right_edge[2]_i_3_n_0 ;\n wire \\ref_right_edge[3]_i_1_n_0 ;\n wire \\ref_right_edge[3]_i_2_n_0 ;\n wire \\ref_right_edge[3]_i_3_n_0 ;\n wire \\ref_right_edge[4]_i_10_n_0 ;\n wire \\ref_right_edge[4]_i_11_n_0 ;\n wire \\ref_right_edge[4]_i_1_n_0 ;\n wire \\ref_right_edge[4]_i_2_n_0 ;\n wire \\ref_right_edge[4]_i_4_n_0 ;\n wire \\ref_right_edge[4]_i_5_n_0 ;\n wire \\ref_right_edge[4]_i_6_n_0 ;\n wire \\ref_right_edge[4]_i_7_n_0 ;\n wire \\ref_right_edge[4]_i_8_n_0 ;\n wire \\ref_right_edge[4]_i_9_n_0 ;\n wire \\ref_right_edge[5]_i_10_n_0 ;\n wire \\ref_right_edge[5]_i_11_n_0 ;\n wire \\ref_right_edge[5]_i_12_n_0 ;\n wire \\ref_right_edge[5]_i_13_n_0 ;\n wire \\ref_right_edge[5]_i_14_n_0 ;\n wire \\ref_right_edge[5]_i_15_n_0 ;\n wire \\ref_right_edge[5]_i_16_n_0 ;\n wire \\ref_right_edge[5]_i_1_n_0 ;\n wire \\ref_right_edge[5]_i_2_n_0 ;\n wire \\ref_right_edge[5]_i_5_n_0 ;\n wire \\ref_right_edge[5]_i_7_n_0 ;\n wire \\ref_right_edge[5]_i_8_n_0 ;\n wire \\ref_right_edge[5]_i_9_n_0 ;\n wire \\ref_right_edge_reg[0]_i_2_n_0 ;\n wire \\ref_right_edge_reg[1]_i_2_n_0 ;\n wire \\ref_right_edge_reg[4]_i_3_n_0 ;\n wire \\ref_right_edge_reg[5]_i_3_n_0 ;\n wire \\ref_right_edge_reg[5]_i_3_n_1 ;\n wire \\ref_right_edge_reg[5]_i_3_n_2 ;\n wire \\ref_right_edge_reg[5]_i_3_n_3 ;\n wire \\ref_right_edge_reg[5]_i_3_n_4 ;\n wire \\ref_right_edge_reg[5]_i_3_n_5 ;\n wire \\ref_right_edge_reg[5]_i_3_n_6 ;\n wire \\ref_right_edge_reg[5]_i_3_n_7 ;\n wire \\ref_right_edge_reg[5]_i_4_n_0 ;\n wire \\ref_right_edge_reg[5]_i_6_n_7 ;\n wire \\ref_right_edge_reg_n_0_[0] ;\n wire \\ref_right_edge_reg_n_0_[1] ;\n wire \\ref_right_edge_reg_n_0_[2] ;\n wire \\ref_right_edge_reg_n_0_[3] ;\n wire \\ref_right_edge_reg_n_0_[4] ;\n wire \\ref_right_edge_reg_n_0_[5] ;\n wire reset_rd_addr;\n wire reset_rd_addr0;\n wire right_edge_found;\n wire right_edge_found_i_4_n_0;\n wire right_edge_found_i_5_n_0;\n wire right_edge_found_reg_0;\n wire right_edge_found_reg_1;\n wire [5:0]right_edge_ref;\n wire \\right_edge_ref[0]_i_1_n_0 ;\n wire \\right_edge_ref[0]_i_2_n_0 ;\n wire \\right_edge_ref[0]_i_3_n_0 ;\n wire \\right_edge_ref[1]_i_1_n_0 ;\n wire \\right_edge_ref[1]_i_2_n_0 ;\n wire \\right_edge_ref[1]_i_3_n_0 ;\n wire \\right_edge_ref[2]_i_1_n_0 ;\n wire \\right_edge_ref[2]_i_2_n_0 ;\n wire \\right_edge_ref[2]_i_3_n_0 ;\n wire \\right_edge_ref[3]_i_1_n_0 ;\n wire \\right_edge_ref[3]_i_2_n_0 ;\n wire \\right_edge_ref[3]_i_3_n_0 ;\n wire \\right_edge_ref[4]_i_11_n_0 ;\n wire \\right_edge_ref[4]_i_12_n_0 ;\n wire \\right_edge_ref[4]_i_1_n_0 ;\n wire \\right_edge_ref[4]_i_2_n_0 ;\n wire \\right_edge_ref[4]_i_4_n_0 ;\n wire \\right_edge_ref[4]_i_5_n_0 ;\n wire \\right_edge_ref[4]_i_6_n_0 ;\n wire \\right_edge_ref[4]_i_7_n_0 ;\n wire \\right_edge_ref[4]_i_8_n_0 ;\n wire \\right_edge_ref[4]_i_9_n_0 ;\n wire \\right_edge_ref[5]_i_11_n_0 ;\n wire \\right_edge_ref[5]_i_12_n_0 ;\n wire \\right_edge_ref[5]_i_1_n_0 ;\n wire \\right_edge_ref[5]_i_2_n_0 ;\n wire \\right_edge_ref[5]_i_4_n_0 ;\n wire \\right_edge_ref[5]_i_5_n_0 ;\n wire \\right_edge_ref[5]_i_6_n_0 ;\n wire \\right_edge_ref[5]_i_7_n_0 ;\n wire \\right_edge_ref[5]_i_8_n_0 ;\n wire \\right_edge_ref[5]_i_9_n_0 ;\n wire \\right_edge_ref_reg[4]_i_10_n_0 ;\n wire \\right_edge_ref_reg[4]_i_3_n_0 ;\n wire \\right_edge_ref_reg[5]_i_10_n_0 ;\n wire \\right_edge_ref_reg[5]_i_3_n_0 ;\n wire right_gain_pb;\n wire \\row_cnt_victim_rotate.complex_row_cnt_reg[4] ;\n wire rstdiv0_sync_r1_reg_rep;\n wire rstdiv0_sync_r1_reg_rep__2;\n wire rstdiv0_sync_r1_reg_rep__23;\n wire rstdiv0_sync_r1_reg_rep__24;\n wire rstdiv0_sync_r1_reg_rep__7;\n wire rstdiv0_sync_r1_reg_rep__8;\n wire rstdiv0_sync_r1_reg_rep__9;\n wire \\samples_cnt_r[0]_i_1_n_0 ;\n wire \\samples_cnt_r[0]_i_2_n_0 ;\n wire \\samples_cnt_r[0]_i_3_n_0 ;\n wire \\samples_cnt_r[10]_i_1_n_0 ;\n wire \\samples_cnt_r[11]_i_2_n_0 ;\n wire \\samples_cnt_r[11]_i_5_n_0 ;\n wire \\samples_cnt_r[11]_i_6_n_0 ;\n wire \\samples_cnt_r[11]_i_7_n_0 ;\n wire \\samples_cnt_r[1]_i_1_n_0 ;\n wire \\samples_cnt_r[2]_i_1_n_0 ;\n wire \\samples_cnt_r[3]_i_1_n_0 ;\n wire \\samples_cnt_r[4]_i_1_n_0 ;\n wire \\samples_cnt_r[4]_i_3_n_0 ;\n wire \\samples_cnt_r[4]_i_4_n_0 ;\n wire \\samples_cnt_r[4]_i_5_n_0 ;\n wire \\samples_cnt_r[4]_i_6_n_0 ;\n wire \\samples_cnt_r[5]_i_1_n_0 ;\n wire \\samples_cnt_r[6]_i_1_n_0 ;\n wire \\samples_cnt_r[7]_i_1_n_0 ;\n wire \\samples_cnt_r[8]_i_1_n_0 ;\n wire \\samples_cnt_r[8]_i_3_n_0 ;\n wire \\samples_cnt_r[8]_i_4_n_0 ;\n wire \\samples_cnt_r[8]_i_5_n_0 ;\n wire \\samples_cnt_r[8]_i_6_n_0 ;\n wire \\samples_cnt_r[9]_i_1_n_0 ;\n wire \\samples_cnt_r_reg[11]_i_4_n_2 ;\n wire \\samples_cnt_r_reg[11]_i_4_n_3 ;\n wire \\samples_cnt_r_reg[4]_i_2_n_0 ;\n wire \\samples_cnt_r_reg[4]_i_2_n_1 ;\n wire \\samples_cnt_r_reg[4]_i_2_n_2 ;\n wire \\samples_cnt_r_reg[4]_i_2_n_3 ;\n wire \\samples_cnt_r_reg[8]_i_2_n_0 ;\n wire \\samples_cnt_r_reg[8]_i_2_n_1 ;\n wire \\samples_cnt_r_reg[8]_i_2_n_2 ;\n wire \\samples_cnt_r_reg[8]_i_2_n_3 ;\n wire \\samples_cnt_r_reg_n_0_[0] ;\n wire \\samples_cnt_r_reg_n_0_[10] ;\n wire \\samples_cnt_r_reg_n_0_[11] ;\n wire \\samples_cnt_r_reg_n_0_[1] ;\n wire \\samples_cnt_r_reg_n_0_[2] ;\n wire \\samples_cnt_r_reg_n_0_[3] ;\n wire \\samples_cnt_r_reg_n_0_[4] ;\n wire \\samples_cnt_r_reg_n_0_[5] ;\n wire \\samples_cnt_r_reg_n_0_[6] ;\n wire \\samples_cnt_r_reg_n_0_[7] ;\n wire \\samples_cnt_r_reg_n_0_[8] ;\n wire \\samples_cnt_r_reg_n_0_[9] ;\n wire [7:0]sel0;\n wire smallest_right_edge;\n wire \\smallest_right_edge[0]_i_1_n_0 ;\n wire \\smallest_right_edge[1]_i_1_n_0 ;\n wire \\smallest_right_edge[2]_i_1_n_0 ;\n wire \\smallest_right_edge[3]_i_1_n_0 ;\n wire \\smallest_right_edge[4]_i_1_n_0 ;\n wire \\smallest_right_edge[5]_i_2_n_0 ;\n wire \\smallest_right_edge[5]_i_3_n_0 ;\n wire \\smallest_right_edge[5]_i_4_n_0 ;\n wire \\smallest_right_edge_reg_n_0_[0] ;\n wire \\smallest_right_edge_reg_n_0_[1] ;\n wire \\smallest_right_edge_reg_n_0_[2] ;\n wire \\smallest_right_edge_reg_n_0_[3] ;\n wire \\smallest_right_edge_reg_n_0_[4] ;\n wire \\smallest_right_edge_reg_n_0_[5] ;\n wire \\stage_cnt[0]_i_1_n_0 ;\n wire \\stage_cnt[1]_i_1_n_0 ;\n wire \\stage_cnt[1]_i_2_n_0 ;\n wire \\stage_cnt_reg[1]_0 ;\n wire \\stage_cnt_reg_n_0_[0] ;\n wire \\stg1_wr_rd_cnt_reg[3] ;\n wire \\victim_not_fixed.num_samples_done_r_i_1_n_0 ;\n wire \\victim_not_fixed.num_samples_done_r_i_2_n_0 ;\n wire wait_state_cnt_en_r;\n wire wait_state_cnt_en_r0;\n wire \\wait_state_cnt_r[2]_i_1_n_0 ;\n wire \\wait_state_cnt_r[3]_i_1_n_0 ;\n wire [3:0]wait_state_cnt_r_reg__0;\n wire wrcal_done_reg;\n wire wrlvl_final_mux;\n wire [3:1]\\NLW_fine_pi_dec_cnt_reg[5]_i_8_CO_UNCONNECTED ;\n wire [3:2]\\NLW_fine_pi_dec_cnt_reg[5]_i_8_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[0].left_loss_pb_reg[5]_i_14_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[0].left_loss_pb_reg[5]_i_19_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[0].left_loss_pb_reg[5]_i_4_O_UNCONNECTED ;\n wire [3:1]\\NLW_genblk8[0].left_loss_pb_reg[5]_i_5_CO_UNCONNECTED ;\n wire [3:2]\\NLW_genblk8[0].left_loss_pb_reg[5]_i_5_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[0].left_loss_pb_reg[5]_i_6_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[0].right_gain_pb_reg[5]_i_10_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[0].right_gain_pb_reg[5]_i_21_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[0].right_gain_pb_reg[5]_i_22_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[0].right_gain_pb_reg[5]_i_29_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[0].right_gain_pb_reg[5]_i_34_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[0].right_gain_pb_reg[5]_i_39_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[0].right_gain_pb_reg[5]_i_5_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[0].right_gain_pb_reg[5]_i_51_O_UNCONNECTED ;\n wire [3:1]\\NLW_genblk8[0].right_gain_pb_reg[5]_i_6_CO_UNCONNECTED ;\n wire [3:2]\\NLW_genblk8[0].right_gain_pb_reg[5]_i_6_O_UNCONNECTED ;\n wire [3:1]\\NLW_genblk8[0].right_gain_pb_reg[5]_i_7_CO_UNCONNECTED ;\n wire [3:2]\\NLW_genblk8[0].right_gain_pb_reg[5]_i_7_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[1].right_gain_pb_reg[11]_i_15_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[1].right_gain_pb_reg[11]_i_18_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[1].right_gain_pb_reg[11]_i_23_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[1].right_gain_pb_reg[11]_i_28_O_UNCONNECTED ;\n wire [3:1]\\NLW_genblk8[1].right_gain_pb_reg[11]_i_5_CO_UNCONNECTED ;\n wire [3:2]\\NLW_genblk8[1].right_gain_pb_reg[11]_i_5_O_UNCONNECTED ;\n wire [3:1]\\NLW_genblk8[1].right_gain_pb_reg[11]_i_6_CO_UNCONNECTED ;\n wire [3:2]\\NLW_genblk8[1].right_gain_pb_reg[11]_i_6_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[2].right_gain_pb_reg[17]_i_15_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[2].right_gain_pb_reg[17]_i_18_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[2].right_gain_pb_reg[17]_i_23_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[2].right_gain_pb_reg[17]_i_28_O_UNCONNECTED ;\n wire [3:1]\\NLW_genblk8[2].right_gain_pb_reg[17]_i_5_CO_UNCONNECTED ;\n wire [3:2]\\NLW_genblk8[2].right_gain_pb_reg[17]_i_5_O_UNCONNECTED ;\n wire [3:1]\\NLW_genblk8[2].right_gain_pb_reg[17]_i_6_CO_UNCONNECTED ;\n wire [3:2]\\NLW_genblk8[2].right_gain_pb_reg[17]_i_6_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[3].right_gain_pb_reg[23]_i_15_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[3].right_gain_pb_reg[23]_i_18_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[3].right_gain_pb_reg[23]_i_23_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[3].right_gain_pb_reg[23]_i_28_O_UNCONNECTED ;\n wire [3:1]\\NLW_genblk8[3].right_gain_pb_reg[23]_i_5_CO_UNCONNECTED ;\n wire [3:2]\\NLW_genblk8[3].right_gain_pb_reg[23]_i_5_O_UNCONNECTED ;\n wire [3:1]\\NLW_genblk8[3].right_gain_pb_reg[23]_i_6_CO_UNCONNECTED ;\n wire [3:2]\\NLW_genblk8[3].right_gain_pb_reg[23]_i_6_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[4].right_gain_pb_reg[29]_i_15_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[4].right_gain_pb_reg[29]_i_18_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[4].right_gain_pb_reg[29]_i_23_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[4].right_gain_pb_reg[29]_i_28_O_UNCONNECTED ;\n wire [3:1]\\NLW_genblk8[4].right_gain_pb_reg[29]_i_5_CO_UNCONNECTED ;\n wire [3:2]\\NLW_genblk8[4].right_gain_pb_reg[29]_i_5_O_UNCONNECTED ;\n wire [3:1]\\NLW_genblk8[4].right_gain_pb_reg[29]_i_6_CO_UNCONNECTED ;\n wire [3:2]\\NLW_genblk8[4].right_gain_pb_reg[29]_i_6_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[5].right_gain_pb_reg[35]_i_15_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[5].right_gain_pb_reg[35]_i_18_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[5].right_gain_pb_reg[35]_i_23_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[5].right_gain_pb_reg[35]_i_28_O_UNCONNECTED ;\n wire [3:1]\\NLW_genblk8[5].right_gain_pb_reg[35]_i_5_CO_UNCONNECTED ;\n wire [3:2]\\NLW_genblk8[5].right_gain_pb_reg[35]_i_5_O_UNCONNECTED ;\n wire [3:1]\\NLW_genblk8[5].right_gain_pb_reg[35]_i_6_CO_UNCONNECTED ;\n wire [3:2]\\NLW_genblk8[5].right_gain_pb_reg[35]_i_6_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[6].right_gain_pb_reg[41]_i_15_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[6].right_gain_pb_reg[41]_i_18_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[6].right_gain_pb_reg[41]_i_23_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[6].right_gain_pb_reg[41]_i_28_O_UNCONNECTED ;\n wire [3:1]\\NLW_genblk8[6].right_gain_pb_reg[41]_i_5_CO_UNCONNECTED ;\n wire [3:2]\\NLW_genblk8[6].right_gain_pb_reg[41]_i_5_O_UNCONNECTED ;\n wire [3:1]\\NLW_genblk8[6].right_gain_pb_reg[41]_i_6_CO_UNCONNECTED ;\n wire [3:2]\\NLW_genblk8[6].right_gain_pb_reg[41]_i_6_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[7].right_gain_pb_reg[47]_i_15_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[7].right_gain_pb_reg[47]_i_18_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[7].right_gain_pb_reg[47]_i_23_O_UNCONNECTED ;\n wire [3:0]\\NLW_genblk8[7].right_gain_pb_reg[47]_i_28_O_UNCONNECTED ;\n wire [3:1]\\NLW_genblk8[7].right_gain_pb_reg[47]_i_5_CO_UNCONNECTED ;\n wire [3:2]\\NLW_genblk8[7].right_gain_pb_reg[47]_i_5_O_UNCONNECTED ;\n wire [3:1]\\NLW_genblk8[7].right_gain_pb_reg[47]_i_6_CO_UNCONNECTED ;\n wire [3:2]\\NLW_genblk8[7].right_gain_pb_reg[47]_i_6_O_UNCONNECTED ;\n wire [3:0]\\NLW_left_edge_ref_reg[5]_i_6_CO_UNCONNECTED ;\n wire [3:1]\\NLW_left_edge_ref_reg[5]_i_6_O_UNCONNECTED ;\n wire [3:0]\\NLW_ref_right_edge_reg[5]_i_6_CO_UNCONNECTED ;\n wire [3:1]\\NLW_ref_right_edge_reg[5]_i_6_O_UNCONNECTED ;\n wire [3:2]\\NLW_samples_cnt_r_reg[11]_i_4_CO_UNCONNECTED ;\n wire [3:3]\\NLW_samples_cnt_r_reg[11]_i_4_O_UNCONNECTED ;\n\n FDRE \\A[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[0]_0 ),\n .Q(A[0]),\n .R(1'b0));\n FDRE \\A[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_0 ),\n .Q(A[1]),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair88\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\bit_cnt[0]_i_1 \n (.I0(bit_cnt_reg__0[0]),\n .O(p_0_in__0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair88\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\bit_cnt[1]_i_1 \n (.I0(bit_cnt_reg__0[0]),\n .I1(bit_cnt_reg__0[1]),\n .O(p_0_in__0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair66\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\bit_cnt[2]_i_1 \n (.I0(bit_cnt_reg__0[0]),\n .I1(bit_cnt_reg__0[1]),\n .I2(bit_cnt_reg__0[2]),\n .O(p_0_in__0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair66\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\bit_cnt[3]_i_1 \n (.I0(bit_cnt_reg__0[1]),\n .I1(bit_cnt_reg__0[0]),\n .I2(bit_cnt_reg__0[2]),\n .I3(bit_cnt_reg__0[3]),\n .O(p_0_in__0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair42\" *) \n LUT5 #(\n .INIT(32'h7FFF8000)) \n \\bit_cnt[4]_i_1 \n (.I0(bit_cnt_reg__0[2]),\n .I1(bit_cnt_reg__0[0]),\n .I2(bit_cnt_reg__0[1]),\n .I3(bit_cnt_reg__0[3]),\n .I4(bit_cnt_reg__0[4]),\n .O(p_0_in__0[4]));\n LUT6 #(\n .INIT(64'h7FFFFFFF80000000)) \n \\bit_cnt[5]_i_1 \n (.I0(bit_cnt_reg__0[3]),\n .I1(bit_cnt_reg__0[1]),\n .I2(bit_cnt_reg__0[0]),\n .I3(bit_cnt_reg__0[2]),\n .I4(bit_cnt_reg__0[4]),\n .I5(bit_cnt_reg__0[5]),\n .O(p_0_in__0[5]));\n LUT2 #(\n .INIT(4'h6)) \n \\bit_cnt[6]_i_1 \n (.I0(\\bit_cnt[7]_i_4_n_0 ),\n .I1(bit_cnt_reg__0[6]),\n .O(p_0_in__0[6]));\n LUT6 #(\n .INIT(64'h0000000000000100)) \n \\bit_cnt[7]_i_1 \n (.I0(bit_cnt_reg__0[6]),\n .I1(bit_cnt_reg__0[7]),\n .I2(\\ref_bit_per_bit[7]_i_2_n_0 ),\n .I3(\\bit_cnt[7]_i_3_n_0 ),\n .I4(bit_cnt_reg__0[5]),\n .I5(bit_cnt_reg__0[4]),\n .O(bit_cnt0));\n (* SOFT_HLUTNM = \"soft_lutpair55\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\bit_cnt[7]_i_2 \n (.I0(\\bit_cnt[7]_i_4_n_0 ),\n .I1(bit_cnt_reg__0[6]),\n .I2(bit_cnt_reg__0[7]),\n .O(p_0_in__0[7]));\n LUT6 #(\n .INIT(64'h0000000000000800)) \n \\bit_cnt[7]_i_3 \n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(Q[2]),\n .I3(Q[4]),\n .I4(Q[3]),\n .I5(bit_cnt_reg__0[3]),\n .O(\\bit_cnt[7]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\bit_cnt[7]_i_4 \n (.I0(bit_cnt_reg__0[5]),\n .I1(bit_cnt_reg__0[3]),\n .I2(bit_cnt_reg__0[1]),\n .I3(bit_cnt_reg__0[0]),\n .I4(bit_cnt_reg__0[2]),\n .I5(bit_cnt_reg__0[4]),\n .O(\\bit_cnt[7]_i_4_n_0 ));\n FDRE \\bit_cnt_reg[0] \n (.C(CLK),\n .CE(bit_cnt0),\n .D(p_0_in__0[0]),\n .Q(bit_cnt_reg__0[0]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\bit_cnt_reg[1] \n (.C(CLK),\n .CE(bit_cnt0),\n .D(p_0_in__0[1]),\n .Q(bit_cnt_reg__0[1]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\bit_cnt_reg[2] \n (.C(CLK),\n .CE(bit_cnt0),\n .D(p_0_in__0[2]),\n .Q(bit_cnt_reg__0[2]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\bit_cnt_reg[3] \n (.C(CLK),\n .CE(bit_cnt0),\n .D(p_0_in__0[3]),\n .Q(bit_cnt_reg__0[3]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\bit_cnt_reg[4] \n (.C(CLK),\n .CE(bit_cnt0),\n .D(p_0_in__0[4]),\n .Q(bit_cnt_reg__0[4]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\bit_cnt_reg[5] \n (.C(CLK),\n .CE(bit_cnt0),\n .D(p_0_in__0[5]),\n .Q(bit_cnt_reg__0[5]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\bit_cnt_reg[6] \n (.C(CLK),\n .CE(bit_cnt0),\n .D(p_0_in__0[6]),\n .Q(bit_cnt_reg__0[6]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\bit_cnt_reg[7] \n (.C(CLK),\n .CE(bit_cnt0),\n .D(p_0_in__0[7]),\n .Q(bit_cnt_reg__0[7]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_f0_i_1 \n (.I0(\\gen_mux_rd[7].compare_data_fall0_r1_reg ),\n .I1(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r3_reg ),\n .I2(\\gen_mux_rd[6].compare_data_fall0_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r3_reg ),\n .I4(\\cmp_err_4to1.compare_err_f0_i_2_n_0 ),\n .I5(\\cmp_err_4to1.compare_err_f0_i_3_n_0 ),\n .O(compare_err_f00));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_f0_i_2 \n (.I0(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r3_reg ),\n .I1(\\gen_mux_rd[3].compare_data_fall0_r1_reg ),\n .I2(\\gen_mux_rd[5].compare_data_fall0_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r3_reg ),\n .I4(\\gen_mux_rd[4].compare_data_fall0_r1_reg ),\n .I5(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r3_reg ),\n .O(\\cmp_err_4to1.compare_err_f0_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_f0_i_3 \n (.I0(\\gen_mux_div4.gen_rd_4[0].mux_rd_fall0_r3_reg ),\n .I1(\\gen_mux_rd[0].compare_data_fall0_r1_reg ),\n .I2(\\gen_mux_rd[2].compare_data_fall0_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r3_reg ),\n .I4(\\gen_mux_rd[1].compare_data_fall0_r1_reg ),\n .I5(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r3_reg ),\n .O(\\cmp_err_4to1.compare_err_f0_i_3_n_0 ));\n FDRE \\cmp_err_4to1.compare_err_f0_reg \n (.C(CLK),\n .CE(rd_valid_r2_reg_n_0),\n .D(compare_err_f00),\n .Q(\\cmp_err_4to1.compare_err_f0_reg_n_0 ),\n .R(compare_err0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_f1_i_1 \n (.I0(\\gen_mux_rd[7].compare_data_fall1_r1_reg ),\n .I1(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r3_reg ),\n .I2(\\gen_mux_rd[6].compare_data_fall1_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r3_reg ),\n .I4(\\cmp_err_4to1.compare_err_f1_i_2_n_0 ),\n .I5(\\cmp_err_4to1.compare_err_f1_i_3_n_0 ),\n .O(compare_err_f10));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_f1_i_2 \n (.I0(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r3_reg ),\n .I1(\\gen_mux_rd[3].compare_data_fall1_r1_reg ),\n .I2(\\gen_mux_rd[5].compare_data_fall1_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r3_reg ),\n .I4(\\gen_mux_rd[4].compare_data_fall1_r1_reg ),\n .I5(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r3_reg ),\n .O(\\cmp_err_4to1.compare_err_f1_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_f1_i_3 \n (.I0(\\gen_mux_div4.gen_rd_4[0].mux_rd_fall1_r3_reg ),\n .I1(\\gen_mux_rd[0].compare_data_fall1_r1_reg ),\n .I2(\\gen_mux_rd[2].compare_data_fall1_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r3_reg ),\n .I4(\\gen_mux_rd[1].compare_data_fall1_r1_reg ),\n .I5(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r3_reg ),\n .O(\\cmp_err_4to1.compare_err_f1_i_3_n_0 ));\n FDRE \\cmp_err_4to1.compare_err_f1_reg \n (.C(CLK),\n .CE(rd_valid_r2_reg_n_0),\n .D(compare_err_f10),\n .Q(\\cmp_err_4to1.compare_err_f1_reg_n_0 ),\n .R(compare_err0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_f2_i_1 \n (.I0(\\gen_mux_rd[7].compare_data_fall2_r1_reg ),\n .I1(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r3_reg ),\n .I2(\\gen_mux_rd[6].compare_data_fall2_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r3_reg ),\n .I4(\\cmp_err_4to1.compare_err_f2_i_2_n_0 ),\n .I5(\\cmp_err_4to1.compare_err_f2_i_3_n_0 ),\n .O(compare_err_f20));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_f2_i_2 \n (.I0(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r3_reg ),\n .I1(\\gen_mux_rd[3].compare_data_fall2_r1_reg ),\n .I2(\\gen_mux_rd[5].compare_data_fall2_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r3_reg ),\n .I4(\\gen_mux_rd[4].compare_data_fall2_r1_reg ),\n .I5(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r3_reg ),\n .O(\\cmp_err_4to1.compare_err_f2_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_f2_i_3 \n (.I0(\\gen_mux_div4.gen_rd_4[0].mux_rd_fall2_r3_reg ),\n .I1(\\gen_mux_rd[0].compare_data_fall2_r1_reg ),\n .I2(\\gen_mux_rd[2].compare_data_fall2_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r3_reg ),\n .I4(\\gen_mux_rd[1].compare_data_fall2_r1_reg ),\n .I5(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r3_reg ),\n .O(\\cmp_err_4to1.compare_err_f2_i_3_n_0 ));\n FDRE \\cmp_err_4to1.compare_err_f2_reg \n (.C(CLK),\n .CE(rd_valid_r2_reg_n_0),\n .D(compare_err_f20),\n .Q(\\cmp_err_4to1.compare_err_f2_reg_n_0 ),\n .R(compare_err0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_f3_i_1 \n (.I0(\\gen_mux_rd[7].compare_data_fall3_r1_reg ),\n .I1(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r3_reg ),\n .I2(\\gen_mux_rd[6].compare_data_fall3_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r3_reg ),\n .I4(\\cmp_err_4to1.compare_err_f3_i_2_n_0 ),\n .I5(\\cmp_err_4to1.compare_err_f3_i_3_n_0 ),\n .O(compare_err_f30));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_f3_i_2 \n (.I0(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r3_reg ),\n .I1(\\gen_mux_rd[3].compare_data_fall3_r1_reg ),\n .I2(\\gen_mux_rd[5].compare_data_fall3_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r3_reg ),\n .I4(\\gen_mux_rd[4].compare_data_fall3_r1_reg ),\n .I5(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r3_reg ),\n .O(\\cmp_err_4to1.compare_err_f3_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_f3_i_3 \n (.I0(\\gen_mux_div4.gen_rd_4[0].mux_rd_fall3_r3_reg ),\n .I1(\\gen_mux_rd[0].compare_data_fall3_r1_reg ),\n .I2(\\gen_mux_rd[2].compare_data_fall3_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r3_reg ),\n .I4(\\gen_mux_rd[1].compare_data_fall3_r1_reg ),\n .I5(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r3_reg ),\n .O(\\cmp_err_4to1.compare_err_f3_i_3_n_0 ));\n FDRE \\cmp_err_4to1.compare_err_f3_reg \n (.C(CLK),\n .CE(rd_valid_r2_reg_n_0),\n .D(compare_err_f30),\n .Q(\\cmp_err_4to1.compare_err_f3_reg_n_0 ),\n .R(compare_err0));\n LUT6 #(\n .INIT(64'hAAAAAAAEAAAAAEAA)) \n \\cmp_err_4to1.compare_err_i_1 \n (.I0(compare_err2),\n .I1(Q[0]),\n .I2(Q[4]),\n .I3(Q[1]),\n .I4(Q[3]),\n .I5(Q[2]),\n .O(compare_err0));\n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n \\cmp_err_4to1.compare_err_i_2 \n (.I0(\\cmp_err_4to1.compare_err_r0_reg_n_0 ),\n .I1(\\cmp_err_4to1.compare_err_f2_reg_n_0 ),\n .I2(\\cmp_err_4to1.compare_err_r2_reg_n_0 ),\n .I3(\\cmp_err_4to1.compare_err_r3_reg_n_0 ),\n .I4(\\cmp_err_4to1.compare_err_i_4_n_0 ),\n .O(compare_err086_out__0));\n LUT2 #(\n .INIT(4'hE)) \n \\cmp_err_4to1.compare_err_i_3 \n (.I0(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .I1(rstdiv0_sync_r1_reg_rep__23),\n .O(compare_err2));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\cmp_err_4to1.compare_err_i_4 \n (.I0(\\cmp_err_4to1.compare_err_r1_reg_n_0 ),\n .I1(\\cmp_err_4to1.compare_err_f1_reg_n_0 ),\n .I2(\\cmp_err_4to1.compare_err_f3_reg_n_0 ),\n .I3(\\cmp_err_4to1.compare_err_f0_reg_n_0 ),\n .O(\\cmp_err_4to1.compare_err_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_r0_i_1 \n (.I0(\\gen_mux_rd[7].compare_data_rise0_r1_reg ),\n .I1(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r3_reg ),\n .I2(\\gen_mux_rd[6].compare_data_rise0_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r3_reg ),\n .I4(\\cmp_err_4to1.compare_err_r0_i_2_n_0 ),\n .I5(\\cmp_err_4to1.compare_err_r0_i_3_n_0 ),\n .O(compare_err_r00));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_r0_i_2 \n (.I0(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r3_reg ),\n .I1(\\gen_mux_rd[3].compare_data_rise0_r1_reg ),\n .I2(\\gen_mux_rd[5].compare_data_rise0_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r3_reg ),\n .I4(\\gen_mux_rd[4].compare_data_rise0_r1_reg ),\n .I5(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r3_reg ),\n .O(\\cmp_err_4to1.compare_err_r0_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_r0_i_3 \n (.I0(\\gen_mux_div4.gen_rd_4[0].mux_rd_rise0_r3_reg ),\n .I1(\\gen_mux_rd[0].compare_data_rise0_r1_reg ),\n .I2(\\gen_mux_rd[2].compare_data_rise0_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r3_reg ),\n .I4(\\gen_mux_rd[1].compare_data_rise0_r1_reg ),\n .I5(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r3_reg ),\n .O(\\cmp_err_4to1.compare_err_r0_i_3_n_0 ));\n FDRE \\cmp_err_4to1.compare_err_r0_reg \n (.C(CLK),\n .CE(rd_valid_r2_reg_n_0),\n .D(compare_err_r00),\n .Q(\\cmp_err_4to1.compare_err_r0_reg_n_0 ),\n .R(compare_err0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_r1_i_1 \n (.I0(\\gen_mux_rd[7].compare_data_rise1_r1_reg ),\n .I1(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r3_reg ),\n .I2(\\gen_mux_rd[6].compare_data_rise1_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r3_reg ),\n .I4(\\cmp_err_4to1.compare_err_r1_i_2_n_0 ),\n .I5(\\cmp_err_4to1.compare_err_r1_i_3_n_0 ),\n .O(compare_err_r10));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_r1_i_2 \n (.I0(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r3_reg ),\n .I1(\\gen_mux_rd[3].compare_data_rise1_r1_reg ),\n .I2(\\gen_mux_rd[5].compare_data_rise1_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r3_reg ),\n .I4(\\gen_mux_rd[4].compare_data_rise1_r1_reg ),\n .I5(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r3_reg ),\n .O(\\cmp_err_4to1.compare_err_r1_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_r1_i_3 \n (.I0(\\gen_mux_div4.gen_rd_4[0].mux_rd_rise1_r3_reg ),\n .I1(\\gen_mux_rd[0].compare_data_rise1_r1_reg ),\n .I2(\\gen_mux_rd[2].compare_data_rise1_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r3_reg ),\n .I4(\\gen_mux_rd[1].compare_data_rise1_r1_reg ),\n .I5(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r3_reg ),\n .O(\\cmp_err_4to1.compare_err_r1_i_3_n_0 ));\n FDRE \\cmp_err_4to1.compare_err_r1_reg \n (.C(CLK),\n .CE(rd_valid_r2_reg_n_0),\n .D(compare_err_r10),\n .Q(\\cmp_err_4to1.compare_err_r1_reg_n_0 ),\n .R(compare_err0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_r2_i_1 \n (.I0(\\gen_mux_rd[7].compare_data_rise2_r1_reg ),\n .I1(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r3_reg ),\n .I2(\\gen_mux_rd[6].compare_data_rise2_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r3_reg ),\n .I4(\\cmp_err_4to1.compare_err_r2_i_2_n_0 ),\n .I5(\\cmp_err_4to1.compare_err_r2_i_3_n_0 ),\n .O(compare_err_r20));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_r2_i_2 \n (.I0(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r3_reg ),\n .I1(\\gen_mux_rd[3].compare_data_rise2_r1_reg ),\n .I2(\\gen_mux_rd[5].compare_data_rise2_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r3_reg ),\n .I4(\\gen_mux_rd[4].compare_data_rise2_r1_reg ),\n .I5(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r3_reg ),\n .O(\\cmp_err_4to1.compare_err_r2_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_r2_i_3 \n (.I0(\\gen_mux_div4.gen_rd_4[0].mux_rd_rise2_r3_reg ),\n .I1(\\gen_mux_rd[0].compare_data_rise2_r1_reg ),\n .I2(\\gen_mux_rd[2].compare_data_rise2_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r3_reg ),\n .I4(\\gen_mux_rd[1].compare_data_rise2_r1_reg ),\n .I5(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r3_reg ),\n .O(\\cmp_err_4to1.compare_err_r2_i_3_n_0 ));\n FDRE \\cmp_err_4to1.compare_err_r2_reg \n (.C(CLK),\n .CE(rd_valid_r2_reg_n_0),\n .D(compare_err_r20),\n .Q(\\cmp_err_4to1.compare_err_r2_reg_n_0 ),\n .R(compare_err0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_r3_i_1 \n (.I0(\\gen_mux_rd[7].compare_data_rise3_r1_reg ),\n .I1(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r3_reg ),\n .I2(\\gen_mux_rd[6].compare_data_rise3_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r3_reg ),\n .I4(\\cmp_err_4to1.compare_err_r3_i_2_n_0 ),\n .I5(\\cmp_err_4to1.compare_err_r3_i_3_n_0 ),\n .O(compare_err_r30));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_r3_i_2 \n (.I0(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r3_reg ),\n .I1(\\gen_mux_rd[3].compare_data_rise3_r1_reg ),\n .I2(\\gen_mux_rd[5].compare_data_rise3_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r3_reg ),\n .I4(\\gen_mux_rd[4].compare_data_rise3_r1_reg ),\n .I5(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r3_reg ),\n .O(\\cmp_err_4to1.compare_err_r3_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\cmp_err_4to1.compare_err_r3_i_3 \n (.I0(\\gen_mux_div4.gen_rd_4[0].mux_rd_rise3_r3_reg ),\n .I1(\\gen_mux_rd[0].compare_data_rise3_r1_reg ),\n .I2(\\gen_mux_rd[2].compare_data_rise3_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r3_reg ),\n .I4(\\gen_mux_rd[1].compare_data_rise3_r1_reg ),\n .I5(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r3_reg ),\n .O(\\cmp_err_4to1.compare_err_r3_i_3_n_0 ));\n FDRE \\cmp_err_4to1.compare_err_r3_reg \n (.C(CLK),\n .CE(rd_valid_r2_reg_n_0),\n .D(compare_err_r30),\n .Q(\\cmp_err_4to1.compare_err_r3_reg_n_0 ),\n .R(compare_err0));\n FDRE \\cmp_err_4to1.compare_err_reg \n (.C(CLK),\n .CE(rd_valid_r2_reg_n_0),\n .D(compare_err086_out__0),\n .Q(\\cmp_err_4to1.compare_err_reg_n_0 ),\n .R(compare_err0));\n LUT5 #(\n .INIT(32'hFFFFFFEA)) \n \\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_1 \n (.I0(\\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0 ),\n .I1(compare_err_pb_and2),\n .I2(err_chk_invalid),\n .I3(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .I4(rstdiv0_sync_r1_reg_rep__23),\n .O(p_66_out));\n LUT6 #(\n .INIT(64'hFFFFFFFFBEFFFFBE)) \n \\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_2 \n (.I0(\\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_5_n_0 ),\n .I1(\\gen_mux_div4.gen_rd_4[0].mux_rd_fall2_r3_reg ),\n .I2(\\gen_mux_rd[0].compare_data_fall2_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[0].mux_rd_rise3_r3_reg ),\n .I4(\\gen_mux_rd[0].compare_data_rise3_r1_reg ),\n .I5(\\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_6_n_0 ),\n .O(p_75_out));\n (* SOFT_HLUTNM = \"soft_lutpair52\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3 \n (.I0(Q[4]),\n .I1(Q[3]),\n .I2(Q[2]),\n .I3(Q[0]),\n .O(\\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair41\" *) \n LUT5 #(\n .INIT(32'h04000010)) \n \\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_4 \n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(Q[4]),\n .I3(Q[3]),\n .I4(Q[2]),\n .O(compare_err_pb_and2));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_5 \n (.I0(\\gen_mux_div4.gen_rd_4[0].mux_rd_fall0_r3_reg ),\n .I1(\\gen_mux_rd[0].compare_data_fall0_r1_reg ),\n .I2(\\gen_mux_div4.gen_rd_4[0].mux_rd_rise1_r3_reg ),\n .I3(\\gen_mux_rd[0].compare_data_rise1_r1_reg ),\n .O(\\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF6FF6)) \n \\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_6 \n (.I0(\\gen_mux_rd[0].compare_data_rise2_r1_reg ),\n .I1(\\gen_mux_div4.gen_rd_4[0].mux_rd_rise2_r3_reg ),\n .I2(\\gen_mux_rd[0].compare_data_fall1_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[0].mux_rd_fall1_r3_reg ),\n .I4(\\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_7_n_0 ),\n .O(\\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_6_n_0 ));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_7 \n (.I0(\\gen_mux_div4.gen_rd_4[0].mux_rd_fall3_r3_reg ),\n .I1(\\gen_mux_rd[0].compare_data_fall3_r1_reg ),\n .I2(\\gen_mux_div4.gen_rd_4[0].mux_rd_rise0_r3_reg ),\n .I3(\\gen_mux_rd[0].compare_data_rise0_r1_reg ),\n .O(\\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_7_n_0 ));\n FDRE \\cmp_err_pb_4to1.(null)[0].compare_err_pb_reg[0] \n (.C(CLK),\n .CE(rd_valid_r2_reg_n_0),\n .D(p_75_out),\n .Q(compare_err_pb[0]),\n .R(p_66_out));\n LUT6 #(\n .INIT(64'hFFFFFFFFBEFFFFBE)) \n \\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_1 \n (.I0(\\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_2_n_0 ),\n .I1(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r3_reg ),\n .I2(\\gen_mux_rd[1].compare_data_rise1_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r3_reg ),\n .I4(\\gen_mux_rd[1].compare_data_fall0_r1_reg ),\n .I5(\\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_3_n_0 ),\n .O(p_64_out));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_2 \n (.I0(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r3_reg ),\n .I1(\\gen_mux_rd[1].compare_data_fall1_r1_reg ),\n .I2(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r3_reg ),\n .I3(\\gen_mux_rd[1].compare_data_rise2_r1_reg ),\n .O(\\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF6FF6)) \n \\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_3 \n (.I0(\\gen_mux_rd[1].compare_data_rise3_r1_reg ),\n .I1(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r3_reg ),\n .I2(\\gen_mux_rd[1].compare_data_fall2_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r3_reg ),\n .I4(\\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_4_n_0 ),\n .O(\\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_4 \n (.I0(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r3_reg ),\n .I1(\\gen_mux_rd[1].compare_data_fall3_r1_reg ),\n .I2(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r3_reg ),\n .I3(\\gen_mux_rd[1].compare_data_rise0_r1_reg ),\n .O(\\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_4_n_0 ));\n FDRE \\cmp_err_pb_4to1.(null)[1].compare_err_pb_reg[1] \n (.C(CLK),\n .CE(rd_valid_r2_reg_n_0),\n .D(p_64_out),\n .Q(compare_err_pb[1]),\n .R(p_66_out));\n LUT6 #(\n .INIT(64'hFFFFFFFFBEFFFFBE)) \n \\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_1 \n (.I0(\\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_2_n_0 ),\n .I1(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r3_reg ),\n .I2(\\gen_mux_rd[2].compare_data_rise1_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r3_reg ),\n .I4(\\gen_mux_rd[2].compare_data_fall0_r1_reg ),\n .I5(\\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_3_n_0 ),\n .O(p_55_out));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_2 \n (.I0(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r3_reg ),\n .I1(\\gen_mux_rd[2].compare_data_fall1_r1_reg ),\n .I2(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r3_reg ),\n .I3(\\gen_mux_rd[2].compare_data_rise2_r1_reg ),\n .O(\\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF6FF6)) \n \\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_3 \n (.I0(\\gen_mux_rd[2].compare_data_fall3_r1_reg ),\n .I1(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r3_reg ),\n .I2(\\gen_mux_rd[2].compare_data_fall2_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r3_reg ),\n .I4(\\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_4_n_0 ),\n .O(\\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_4 \n (.I0(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r3_reg ),\n .I1(\\gen_mux_rd[2].compare_data_rise0_r1_reg ),\n .I2(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r3_reg ),\n .I3(\\gen_mux_rd[2].compare_data_rise3_r1_reg ),\n .O(\\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_4_n_0 ));\n FDRE \\cmp_err_pb_4to1.(null)[2].compare_err_pb_reg[2] \n (.C(CLK),\n .CE(rd_valid_r2_reg_n_0),\n .D(p_55_out),\n .Q(compare_err_pb[2]),\n .R(p_66_out));\n LUT6 #(\n .INIT(64'hFFFFFFFFBEFFFFBE)) \n \\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_1 \n (.I0(\\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_2_n_0 ),\n .I1(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r3_reg ),\n .I2(\\gen_mux_rd[3].compare_data_rise1_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r3_reg ),\n .I4(\\gen_mux_rd[3].compare_data_fall0_r1_reg ),\n .I5(\\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_3_n_0 ),\n .O(p_46_out));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_2 \n (.I0(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r3_reg ),\n .I1(\\gen_mux_rd[3].compare_data_fall1_r1_reg ),\n .I2(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r3_reg ),\n .I3(\\gen_mux_rd[3].compare_data_rise2_r1_reg ),\n .O(\\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF6FF6)) \n \\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_3 \n (.I0(\\gen_mux_rd[3].compare_data_rise3_r1_reg ),\n .I1(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r3_reg ),\n .I2(\\gen_mux_rd[3].compare_data_fall2_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r3_reg ),\n .I4(\\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_4_n_0 ),\n .O(\\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_4 \n (.I0(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r3_reg ),\n .I1(\\gen_mux_rd[3].compare_data_fall3_r1_reg ),\n .I2(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r3_reg ),\n .I3(\\gen_mux_rd[3].compare_data_rise0_r1_reg ),\n .O(\\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_4_n_0 ));\n FDRE \\cmp_err_pb_4to1.(null)[3].compare_err_pb_reg[3] \n (.C(CLK),\n .CE(rd_valid_r2_reg_n_0),\n .D(p_46_out),\n .Q(compare_err_pb[3]),\n .R(p_66_out));\n LUT6 #(\n .INIT(64'hFFFFFFFFBEFFFFBE)) \n \\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_1 \n (.I0(\\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_2_n_0 ),\n .I1(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r3_reg ),\n .I2(\\gen_mux_rd[4].compare_data_rise1_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r3_reg ),\n .I4(\\gen_mux_rd[4].compare_data_fall0_r1_reg ),\n .I5(\\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_3_n_0 ),\n .O(p_37_out));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_2 \n (.I0(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r3_reg ),\n .I1(\\gen_mux_rd[4].compare_data_fall1_r1_reg ),\n .I2(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r3_reg ),\n .I3(\\gen_mux_rd[4].compare_data_rise2_r1_reg ),\n .O(\\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF6FF6)) \n \\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_3 \n (.I0(\\gen_mux_rd[4].compare_data_rise3_r1_reg ),\n .I1(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r3_reg ),\n .I2(\\gen_mux_rd[4].compare_data_fall2_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r3_reg ),\n .I4(\\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_4_n_0 ),\n .O(\\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_4 \n (.I0(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r3_reg ),\n .I1(\\gen_mux_rd[4].compare_data_fall3_r1_reg ),\n .I2(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r3_reg ),\n .I3(\\gen_mux_rd[4].compare_data_rise0_r1_reg ),\n .O(\\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_4_n_0 ));\n FDRE \\cmp_err_pb_4to1.(null)[4].compare_err_pb_reg[4] \n (.C(CLK),\n .CE(rd_valid_r2_reg_n_0),\n .D(p_37_out),\n .Q(compare_err_pb[4]),\n .R(p_66_out));\n LUT6 #(\n .INIT(64'hFFFFFFFFBEFFFFBE)) \n \\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_1 \n (.I0(\\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_2_n_0 ),\n .I1(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r3_reg ),\n .I2(\\gen_mux_rd[5].compare_data_rise1_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r3_reg ),\n .I4(\\gen_mux_rd[5].compare_data_fall0_r1_reg ),\n .I5(\\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_3_n_0 ),\n .O(p_28_out));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_2 \n (.I0(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r3_reg ),\n .I1(\\gen_mux_rd[5].compare_data_fall1_r1_reg ),\n .I2(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r3_reg ),\n .I3(\\gen_mux_rd[5].compare_data_rise2_r1_reg ),\n .O(\\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF6FF6)) \n \\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_3 \n (.I0(\\gen_mux_rd[5].compare_data_fall3_r1_reg ),\n .I1(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r3_reg ),\n .I2(\\gen_mux_rd[5].compare_data_rise3_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r3_reg ),\n .I4(\\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_4_n_0 ),\n .O(\\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_4 \n (.I0(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r3_reg ),\n .I1(\\gen_mux_rd[5].compare_data_rise0_r1_reg ),\n .I2(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r3_reg ),\n .I3(\\gen_mux_rd[5].compare_data_fall2_r1_reg ),\n .O(\\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_4_n_0 ));\n FDRE \\cmp_err_pb_4to1.(null)[5].compare_err_pb_reg[5] \n (.C(CLK),\n .CE(rd_valid_r2_reg_n_0),\n .D(p_28_out),\n .Q(compare_err_pb[5]),\n .R(p_66_out));\n LUT6 #(\n .INIT(64'hFFFFFFFFBEFFFFBE)) \n \\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_1 \n (.I0(\\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_2_n_0 ),\n .I1(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r3_reg ),\n .I2(\\gen_mux_rd[6].compare_data_fall2_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r3_reg ),\n .I4(\\gen_mux_rd[6].compare_data_fall1_r1_reg ),\n .I5(\\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_3_n_0 ),\n .O(p_19_out));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_2 \n (.I0(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r3_reg ),\n .I1(\\gen_mux_rd[6].compare_data_rise3_r1_reg ),\n .I2(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r3_reg ),\n .I3(\\gen_mux_rd[6].compare_data_fall3_r1_reg ),\n .O(\\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF6FF6)) \n \\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_3 \n (.I0(\\gen_mux_rd[6].compare_data_fall0_r1_reg ),\n .I1(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r3_reg ),\n .I2(\\gen_mux_rd[6].compare_data_rise1_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r3_reg ),\n .I4(\\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_4_n_0 ),\n .O(\\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_4 \n (.I0(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r3_reg ),\n .I1(\\gen_mux_rd[6].compare_data_rise2_r1_reg ),\n .I2(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r3_reg ),\n .I3(\\gen_mux_rd[6].compare_data_rise0_r1_reg ),\n .O(\\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_4_n_0 ));\n FDRE \\cmp_err_pb_4to1.(null)[6].compare_err_pb_reg[6] \n (.C(CLK),\n .CE(rd_valid_r2_reg_n_0),\n .D(p_19_out),\n .Q(compare_err_pb[6]),\n .R(p_66_out));\n LUT6 #(\n .INIT(64'hFFFFFFFFBEFFFFBE)) \n \\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_1 \n (.I0(\\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_2_n_0 ),\n .I1(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r3_reg ),\n .I2(\\gen_mux_rd[7].compare_data_rise1_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r3_reg ),\n .I4(\\gen_mux_rd[7].compare_data_fall1_r1_reg ),\n .I5(\\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_3_n_0 ),\n .O(p_10_out));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_2 \n (.I0(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r3_reg ),\n .I1(\\gen_mux_rd[7].compare_data_rise3_r1_reg ),\n .I2(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r3_reg ),\n .I3(\\gen_mux_rd[7].compare_data_fall0_r1_reg ),\n .O(\\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF6FF6)) \n \\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_3 \n (.I0(\\gen_mux_rd[7].compare_data_fall2_r1_reg ),\n .I1(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r3_reg ),\n .I2(\\gen_mux_rd[7].compare_data_rise2_r1_reg ),\n .I3(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r3_reg ),\n .I4(\\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_4_n_0 ),\n .O(\\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_4 \n (.I0(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r3_reg ),\n .I1(\\gen_mux_rd[7].compare_data_fall3_r1_reg ),\n .I2(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r3_reg ),\n .I3(\\gen_mux_rd[7].compare_data_rise0_r1_reg ),\n .O(\\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_4_n_0 ));\n FDRE \\cmp_err_pb_4to1.(null)[7].compare_err_pb_reg[7] \n (.C(CLK),\n .CE(rd_valid_r2_reg_n_0),\n .D(p_10_out),\n .Q(compare_err_pb[7]),\n .R(p_66_out));\n (* SOFT_HLUTNM = \"soft_lutpair35\" *) \n LUT5 #(\n .INIT(32'h80000000)) \n cnt_wait_state_i_1\n (.I0(wait_state_cnt_en_r),\n .I1(wait_state_cnt_r_reg__0[3]),\n .I2(wait_state_cnt_r_reg__0[2]),\n .I3(wait_state_cnt_r_reg__0[0]),\n .I4(wait_state_cnt_r_reg__0[1]),\n .O(cnt_wait_state_i_1_n_0));\n FDRE cnt_wait_state_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cnt_wait_state_i_1_n_0),\n .Q(cnt_wait_state),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hAAAAABAAAAAAAAAA)) \n compare_err_latch_i_1\n (.I0(compare_err_latch_i_2_n_0),\n .I1(compare_err_latch_reg_0),\n .I2(Q[2]),\n .I3(\\cmp_err_4to1.compare_err_reg_n_0 ),\n .I4(Q[0]),\n .I5(Q[1]),\n .O(compare_err_latch_i_1_n_0));\n LUT6 #(\n .INIT(64'h0000000200000000)) \n compare_err_latch_i_2\n (.I0(compare_err_latch_reg_n_0),\n .I1(Q[2]),\n .I2(Q[3]),\n .I3(Q[0]),\n .I4(Q[4]),\n .I5(Q[1]),\n .O(compare_err_latch_i_2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair19\" *) \n LUT2 #(\n .INIT(4'hE)) \n compare_err_latch_i_3\n (.I0(Q[3]),\n .I1(Q[4]),\n .O(compare_err_latch_reg_0));\n FDRE compare_err_latch_reg\n (.C(CLK),\n .CE(1'b1),\n .D(compare_err_latch_i_1_n_0),\n .Q(compare_err_latch_reg_n_0),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00002022)) \n compare_err_pb_and_i_1\n (.I0(compare_err_pb_and_i_2_n_0),\n .I1(rstdiv0_sync_r1_reg_rep__23),\n .I2(cnt_wait_state),\n .I3(compare_err_pb_and2),\n .I4(\\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0 ),\n .O(compare_err_pb_and_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFF40000000)) \n compare_err_pb_and_i_2\n (.I0(compare_err_pb_and_i_3_n_0),\n .I1(compare_err_pb[5]),\n .I2(compare_err_pb[4]),\n .I3(compare_err_pb[6]),\n .I4(compare_err_pb[7]),\n .I5(compare_err_pb_and_reg_n_0),\n .O(compare_err_pb_and_i_2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair60\" *) \n LUT4 #(\n .INIT(16'h7FFF)) \n compare_err_pb_and_i_3\n (.I0(compare_err_pb[1]),\n .I1(compare_err_pb[0]),\n .I2(compare_err_pb[3]),\n .I3(compare_err_pb[2]),\n .O(compare_err_pb_and_i_3_n_0));\n FDRE compare_err_pb_and_reg\n (.C(CLK),\n .CE(1'b1),\n .D(compare_err_pb_and_i_1_n_0),\n .Q(compare_err_pb_and_reg_n_0),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00002022)) \n compare_err_pb_or_i_1\n (.I0(compare_err_pb_or_i_2_n_0),\n .I1(rstdiv0_sync_r1_reg_rep__23),\n .I2(cnt_wait_state),\n .I3(compare_err_pb_and2),\n .I4(\\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0 ),\n .O(compare_err_pb_or_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFD)) \n compare_err_pb_or_i_2\n (.I0(compare_err_pb_or_i_3_n_0),\n .I1(compare_err_pb[3]),\n .I2(compare_err_pb[2]),\n .I3(compare_err_pb[1]),\n .I4(compare_err_pb[0]),\n .I5(sel0[0]),\n .O(compare_err_pb_or_i_2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair61\" *) \n LUT4 #(\n .INIT(16'h0001)) \n compare_err_pb_or_i_3\n (.I0(compare_err_pb[6]),\n .I1(compare_err_pb[7]),\n .I2(compare_err_pb[5]),\n .I3(compare_err_pb[4]),\n .O(compare_err_pb_or_i_3_n_0));\n FDRE compare_err_pb_or_reg\n (.C(CLK),\n .CE(1'b1),\n .D(compare_err_pb_or_i_1_n_0),\n .Q(sel0[0]),\n .R(1'b0));\n FDRE complex_init_pi_dec_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\prbs_state_r_reg[4]_3 ),\n .Q(complex_init_pi_dec_done),\n .R(rstdiv0_sync_r1_reg_rep__2));\n LUT6 #(\n .INIT(64'h88B88888B8B8B8B8)) \n complex_pi_incdec_done_i_2\n (.I0(complex_pi_incdec_done_i_3_n_0),\n .I1(complex_pi_incdec_done_i_4_n_0),\n .I2(complex_pi_incdec_done_i_5_n_0),\n .I3(\\prbs_state_r[1]_i_5_n_0 ),\n .I4(cnt_wait_state),\n .I5(complex_pi_incdec_done_i_6_n_0),\n .O(complex_pi_incdec_done_reg_0));\n LUT6 #(\n .INIT(64'hC0F07373C0F04040)) \n complex_pi_incdec_done_i_3\n (.I0(prbs_tap_en_r_reg_0),\n .I1(complex_pi_incdec_done_i_5_n_0),\n .I2(cnt_wait_state),\n .I3(p_3_in),\n .I4(complex_pi_incdec_done_i_6_n_0),\n .I5(\\prbs_state_r[3]_i_4_n_0 ),\n .O(complex_pi_incdec_done_i_3_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair51\" *) \n LUT5 #(\n .INIT(32'h04000118)) \n complex_pi_incdec_done_i_4\n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(Q[4]),\n .I3(Q[2]),\n .I4(Q[3]),\n .O(complex_pi_incdec_done_i_4_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair47\" *) \n LUT5 #(\n .INIT(32'h04040834)) \n complex_pi_incdec_done_i_5\n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(Q[4]),\n .I3(Q[3]),\n .I4(Q[2]),\n .O(complex_pi_incdec_done_i_5_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair47\" *) \n LUT5 #(\n .INIT(32'hEFDCFFF7)) \n complex_pi_incdec_done_i_6\n (.I0(Q[0]),\n .I1(Q[4]),\n .I2(Q[3]),\n .I3(Q[2]),\n .I4(Q[1]),\n .O(complex_pi_incdec_done_i_6_n_0));\n FDRE complex_pi_incdec_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\prbs_state_r_reg[0]_4 ),\n .Q(complex_pi_incdec_done),\n .R(rstdiv0_sync_r1_reg_rep__2));\n LUT1 #(\n .INIT(2'h1)) \n complex_victim_inc_i_2\n (.I0(\\rd_victim_sel_reg[2]_0 ),\n .O(complex_victim_inc__0));\n FDRE complex_victim_inc_reg\n (.C(CLK),\n .CE(1'b1),\n .D(complex_victim_inc__0),\n .Q(\\row_cnt_victim_rotate.complex_row_cnt_reg[4] ),\n .R(rstdiv0_sync_r1_reg_rep__7));\n LUT5 #(\n .INIT(32'hB8FFB8CC)) \n \\dec_cnt[0]_i_1 \n (.I0(\\dec_cnt_reg[0]_i_2_n_0 ),\n .I1(\\largest_left_edge_reg_n_0_[5] ),\n .I2(\\dec_cnt[0]_i_3_n_0 ),\n .I3(\\smallest_right_edge_reg_n_0_[5] ),\n .I4(\\dec_cnt[0]_i_4_n_0 ),\n .O(\\dec_cnt[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAFAFCFC0)) \n \\dec_cnt[0]_i_11 \n (.I0(\\dec_cnt[5]_i_6_n_0 ),\n .I1(\\dec_cnt[0]_i_29_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[3] ),\n .I3(\\dec_cnt[0]_i_14_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[3] ),\n .O(\\dec_cnt[0]_i_11_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFDE8E)) \n \\dec_cnt[0]_i_13 \n (.I0(\\largest_left_edge_reg_n_0_[3] ),\n .I1(\\dec_cnt[0]_i_14_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[3] ),\n .I3(\\dec_cnt[0]_i_32_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[4] ),\n .O(\\dec_cnt[0]_i_13_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFDFFDFFFF)) \n \\dec_cnt[0]_i_14 \n (.I0(\\smallest_right_edge_reg_n_0_[2] ),\n .I1(\\largest_left_edge_reg_n_0_[1] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\smallest_right_edge_reg_n_0_[1] ),\n .I5(\\largest_left_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[0]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'h7E733BEEE73EBEC3)) \n \\dec_cnt[0]_i_15 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_15_n_0 ));\n LUT6 #(\n .INIT(64'h3E432BAEE6323AC3)) \n \\dec_cnt[0]_i_16 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\dec_cnt[0]_i_17 \n (.I0(\\dec_cnt[0]_i_33_n_0 ),\n .I1(\\dec_cnt[0]_i_34_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[3] ),\n .I3(\\dec_cnt[0]_i_26_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[3] ),\n .I5(\\dec_cnt[0]_i_35_n_0 ),\n .O(\\dec_cnt[0]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'h9996966669699999)) \n \\dec_cnt[0]_i_20 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\smallest_right_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'hC29C39C323CE9C22)) \n \\dec_cnt[0]_i_21 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_21_n_0 ));\n LUT6 #(\n .INIT(64'h25B649A565A55A64)) \n \\dec_cnt[0]_i_22 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_22_n_0 ));\n LUT6 #(\n .INIT(64'h7DFEF57E08818110)) \n \\dec_cnt[0]_i_23 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_23_n_0 ));\n LUT6 #(\n .INIT(64'h9796766669899991)) \n \\dec_cnt[0]_i_24 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\smallest_right_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_24_n_0 ));\n LUT6 #(\n .INIT(64'h629C394323C69C32)) \n \\dec_cnt[0]_i_25 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_25_n_0 ));\n LUT6 #(\n .INIT(64'h6B7F6AF74AB756A6)) \n \\dec_cnt[0]_i_26 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[1] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[0]_i_26_n_0 ));\n LUT6 #(\n .INIT(64'h3E732BEEE736BEC3)) \n \\dec_cnt[0]_i_29 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_29_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\dec_cnt[0]_i_3 \n (.I0(\\dec_cnt_reg[0]_i_7_n_0 ),\n .I1(\\dec_cnt[0]_i_8_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[4] ),\n .I3(\\dec_cnt[0]_i_9_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[4] ),\n .I5(\\dec_cnt_reg[0]_i_10_n_0 ),\n .O(\\dec_cnt[0]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h3E532BEEE7323AC3)) \n \\dec_cnt[0]_i_32 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_32_n_0 ));\n LUT6 #(\n .INIT(64'h9B96966669699999)) \n \\dec_cnt[0]_i_33 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\smallest_right_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_33_n_0 ));\n LUT6 #(\n .INIT(64'hC29C39C323CE9C32)) \n \\dec_cnt[0]_i_34 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_34_n_0 ));\n LUT6 #(\n .INIT(64'h7DBEF57E08C18110)) \n \\dec_cnt[0]_i_35 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_35_n_0 ));\n LUT6 #(\n .INIT(64'hF00FE51A1ECFF00F)) \n \\dec_cnt[0]_i_36 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_36_n_0 ));\n LUT6 #(\n .INIT(64'h3A755DAAA6558A15)) \n \\dec_cnt[0]_i_37 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\largest_left_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[0]_i_37_n_0 ));\n LUT6 #(\n .INIT(64'h1CC32B8CC63238C1)) \n \\dec_cnt[0]_i_38 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_38_n_0 ));\n LUT6 #(\n .INIT(64'hFF0F00E000F0FF3F)) \n \\dec_cnt[0]_i_39 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\largest_left_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\smallest_right_edge_reg_n_0_[1] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[0]_i_39_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\dec_cnt[0]_i_4 \n (.I0(\\dec_cnt[0]_i_11_n_0 ),\n .I1(\\largest_left_edge_reg_n_0_[4] ),\n .I2(\\dec_cnt_reg[0]_i_12_n_0 ),\n .I3(\\smallest_right_edge_reg_n_0_[4] ),\n .I4(\\dec_cnt[0]_i_13_n_0 ),\n .O(\\dec_cnt[0]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hF00F87E0708FF00F)) \n \\dec_cnt[0]_i_40 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_40_n_0 ));\n LUT6 #(\n .INIT(64'h271D55AA8A55A285)) \n \\dec_cnt[0]_i_41 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\largest_left_edge_reg_n_0_[0] ),\n .I2(\\smallest_right_edge_reg_n_0_[2] ),\n .I3(\\smallest_right_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[0]_i_41_n_0 ));\n LUT6 #(\n .INIT(64'h1C532BCCC736BCC1)) \n \\dec_cnt[0]_i_42 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_42_n_0 ));\n LUT6 #(\n .INIT(64'hF00F0FF0F00BF00F)) \n \\dec_cnt[0]_i_43 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_43_n_0 ));\n LUT6 #(\n .INIT(64'h1DBED57E48C10110)) \n \\dec_cnt[0]_i_44 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_44_n_0 ));\n LUT6 #(\n .INIT(64'h6A7F6AB75AB756AE)) \n \\dec_cnt[0]_i_45 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[1] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[0]_i_45_n_0 ));\n LUT6 #(\n .INIT(64'h633C33CCDC63C63A)) \n \\dec_cnt[0]_i_46 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_46_n_0 ));\n LUT6 #(\n .INIT(64'h9796666669999995)) \n \\dec_cnt[0]_i_47 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\smallest_right_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[0]_i_47_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFDE8E)) \n \\dec_cnt[0]_i_5 \n (.I0(\\largest_left_edge_reg_n_0_[3] ),\n .I1(\\dec_cnt[0]_i_14_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[3] ),\n .I3(\\dec_cnt[0]_i_15_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[4] ),\n .O(\\dec_cnt[0]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hF3B8FFFFF3B80000)) \n \\dec_cnt[0]_i_6 \n (.I0(\\dec_cnt[0]_i_16_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[0]_i_14_n_0 ),\n .I3(\\largest_left_edge_reg_n_0_[3] ),\n .I4(\\largest_left_edge_reg_n_0_[4] ),\n .I5(\\dec_cnt[0]_i_17_n_0 ),\n .O(\\dec_cnt[0]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\dec_cnt[0]_i_8 \n (.I0(\\dec_cnt[0]_i_20_n_0 ),\n .I1(\\dec_cnt[0]_i_21_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[3] ),\n .I3(\\dec_cnt[0]_i_22_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[3] ),\n .I5(\\dec_cnt[0]_i_23_n_0 ),\n .O(\\dec_cnt[0]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\dec_cnt[0]_i_9 \n (.I0(\\dec_cnt[0]_i_24_n_0 ),\n .I1(\\dec_cnt[0]_i_25_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[3] ),\n .I3(\\dec_cnt[0]_i_26_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[3] ),\n .I5(\\dec_cnt[0]_i_23_n_0 ),\n .O(\\dec_cnt[0]_i_9_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\dec_cnt[1]_i_1 \n (.I0(\\dec_cnt[1]_i_2_n_0 ),\n .I1(\\largest_left_edge_reg_n_0_[5] ),\n .I2(\\dec_cnt[1]_i_3_n_0 ),\n .I3(\\smallest_right_edge_reg_n_0_[5] ),\n .I4(\\dec_cnt[1]_i_4_n_0 ),\n .O(\\dec_cnt[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hA61AAFB6BE5BA69A)) \n \\dec_cnt[1]_i_13 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[1]_i_13_n_0 ));\n LUT6 #(\n .INIT(64'hE73BE633C673CE62)) \n \\dec_cnt[1]_i_15 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[1] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[1]_i_15_n_0 ));\n LUT6 #(\n .INIT(64'h0A7F8AFE3F017F11)) \n \\dec_cnt[1]_i_16 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[1]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'hE731E633C673CE62)) \n \\dec_cnt[1]_i_19 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[1] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[1]_i_19_n_0 ));\n LUT5 #(\n .INIT(32'hDE8EFFFF)) \n \\dec_cnt[1]_i_2 \n (.I0(\\largest_left_edge_reg_n_0_[4] ),\n .I1(\\dec_cnt[1]_i_5_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[4] ),\n .I3(\\dec_cnt[1]_i_6_n_0 ),\n .I4(\\smallest_right_edge_reg_n_0_[5] ),\n .O(\\dec_cnt[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0A7F8AFE7F017F11)) \n \\dec_cnt[1]_i_20 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[1]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'h8F8E0E1EE787878F)) \n \\dec_cnt[1]_i_21 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\smallest_right_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[1]_i_21_n_0 ));\n LUT6 #(\n .INIT(64'hE759A651AE758A64)) \n \\dec_cnt[1]_i_22 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[1] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[1]_i_22_n_0 ));\n LUT6 #(\n .INIT(64'hE579A561A6E596A4)) \n \\dec_cnt[1]_i_25 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[1]_i_25_n_0 ));\n LUT6 #(\n .INIT(64'h8F8E1E1EE787878F)) \n \\dec_cnt[1]_i_26 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\smallest_right_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[1]_i_26_n_0 ));\n LUT6 #(\n .INIT(64'h6A7FAA7E3F017F11)) \n \\dec_cnt[1]_i_27 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[1]_i_27_n_0 ));\n LUT6 #(\n .INIT(64'hDAD2DAF22F4F4F4A)) \n \\dec_cnt[1]_i_28 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[0] ),\n .I2(\\smallest_right_edge_reg_n_0_[2] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[1]_i_28_n_0 ));\n LUT6 #(\n .INIT(64'h6759A659A6758A64)) \n \\dec_cnt[1]_i_29 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[1] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[1]_i_29_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\dec_cnt[1]_i_3 \n (.I0(\\dec_cnt_reg[1]_i_7_n_0 ),\n .I1(\\dec_cnt[1]_i_8_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[4] ),\n .I3(\\dec_cnt[1]_i_9_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[4] ),\n .I5(\\dec_cnt_reg[1]_i_10_n_0 ),\n .O(\\dec_cnt[1]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h878E8E1EE7E78787)) \n \\dec_cnt[1]_i_30 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\smallest_right_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[1]_i_30_n_0 ));\n LUT6 #(\n .INIT(64'h6663866696869696)) \n \\dec_cnt[1]_i_31 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[1]_i_31_n_0 ));\n LUT6 #(\n .INIT(64'h89C991C9EC6CCC6C)) \n \\dec_cnt[1]_i_32 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\largest_left_edge_reg_n_0_[1] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[1]_i_32_n_0 ));\n LUT6 #(\n .INIT(64'h869AA5969E5BA69A)) \n \\dec_cnt[1]_i_33 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[1]_i_33_n_0 ));\n LUT6 #(\n .INIT(64'h6966696966866666)) \n \\dec_cnt[1]_i_34 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\largest_left_edge_reg_n_0_[1] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[1]_i_34_n_0 ));\n LUT6 #(\n .INIT(64'h6616666696991696)) \n \\dec_cnt[1]_i_35 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[1]_i_35_n_0 ));\n LUT6 #(\n .INIT(64'hCF00F38C8C33F700)) \n \\dec_cnt[1]_i_36 \n (.I0(\\largest_left_edge_reg_n_0_[0] ),\n .I1(\\largest_left_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[2] ),\n .I4(\\smallest_right_edge_reg_n_0_[1] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[1]_i_36_n_0 ));\n LUT6 #(\n .INIT(64'h861AA5969E5BA69A)) \n \\dec_cnt[1]_i_37 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[1]_i_37_n_0 ));\n LUT6 #(\n .INIT(64'h6669666696669296)) \n \\dec_cnt[1]_i_38 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[1]_i_38_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF00FFB8FFB800)) \n \\dec_cnt[1]_i_4 \n (.I0(\\dec_cnt_reg[1]_i_11_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt_reg[1]_i_12_n_0 ),\n .I3(\\smallest_right_edge_reg_n_0_[4] ),\n .I4(\\dec_cnt[1]_i_5_n_0 ),\n .I5(\\largest_left_edge_reg_n_0_[4] ),\n .O(\\dec_cnt[1]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair56\" *) \n LUT4 #(\n .INIT(16'hF3B8)) \n \\dec_cnt[1]_i_5 \n (.I0(\\dec_cnt[1]_i_13_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[5]_i_6_n_0 ),\n .I3(\\largest_left_edge_reg_n_0_[3] ),\n .O(\\dec_cnt[1]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\dec_cnt[1]_i_6 \n (.I0(\\dec_cnt_reg[1]_i_14_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[1]_i_15_n_0 ),\n .I3(\\largest_left_edge_reg_n_0_[3] ),\n .I4(\\dec_cnt[1]_i_16_n_0 ),\n .O(\\dec_cnt[1]_i_6_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\dec_cnt[1]_i_8 \n (.I0(\\dec_cnt_reg[1]_i_14_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[1]_i_19_n_0 ),\n .I3(\\largest_left_edge_reg_n_0_[3] ),\n .I4(\\dec_cnt[1]_i_20_n_0 ),\n .O(\\dec_cnt[1]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\dec_cnt[1]_i_9 \n (.I0(\\dec_cnt[1]_i_21_n_0 ),\n .I1(\\dec_cnt[1]_i_22_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[3] ),\n .I3(\\dec_cnt[1]_i_15_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[3] ),\n .I5(\\dec_cnt[1]_i_20_n_0 ),\n .O(\\dec_cnt[1]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'h42C444C433232323)) \n \\dec_cnt[2]_i_10 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[2]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'hDC9CC4DC9DBDDC9D)) \n \\dec_cnt[2]_i_11 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[2]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFEFEEEEF7)) \n \\dec_cnt[2]_i_12 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[1] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[2]_i_12_n_0 ));\n LUT6 #(\n .INIT(64'h26A22524AAAAA4A4)) \n \\dec_cnt[2]_i_13 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\largest_left_edge_reg_n_0_[1] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[2]_i_13_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair71\" *) \n LUT3 #(\n .INIT(8'hDF)) \n \\dec_cnt[2]_i_14 \n (.I0(\\smallest_right_edge_reg_n_0_[0] ),\n .I1(\\largest_left_edge_reg_n_0_[1] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[2]_i_14_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair58\" *) \n LUT4 #(\n .INIT(16'h00AE)) \n \\dec_cnt[2]_i_15 \n (.I0(\\largest_left_edge_reg_n_0_[1] ),\n .I1(\\largest_left_edge_reg_n_0_[0] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[2]_i_15_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFBDABEB)) \n \\dec_cnt[2]_i_17 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\largest_left_edge_reg_n_0_[0] ),\n .I2(\\largest_left_edge_reg_n_0_[1] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\smallest_right_edge_reg_n_0_[1] ),\n .I5(\\smallest_right_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[2]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'h26A225A4AAAAA4A4)) \n \\dec_cnt[2]_i_18 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\largest_left_edge_reg_n_0_[1] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[2]_i_18_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\dec_cnt[2]_i_19 \n (.I0(\\dec_cnt[2]_i_25_n_0 ),\n .I1(\\dec_cnt[2]_i_26_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[3] ),\n .I3(\\dec_cnt[2]_i_27_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[3] ),\n .I5(\\dec_cnt[2]_i_28_n_0 ),\n .O(\\dec_cnt[2]_i_19_n_0 ));\n LUT6 #(\n .INIT(64'hBBBB88BBB8BBB888)) \n \\dec_cnt[2]_i_2 \n (.I0(\\dec_cnt_reg[2]_i_4_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[5] ),\n .I2(\\dec_cnt[2]_i_5_n_0 ),\n .I3(\\smallest_right_edge_reg_n_0_[4] ),\n .I4(\\dec_cnt[2]_i_6_n_0 ),\n .I5(\\largest_left_edge_reg_n_0_[4] ),\n .O(\\dec_cnt[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\dec_cnt[2]_i_20 \n (.I0(\\dec_cnt[2]_i_10_n_0 ),\n .I1(\\dec_cnt[2]_i_29_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[3] ),\n .I3(\\dec_cnt[2]_i_17_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[3] ),\n .I5(\\dec_cnt[2]_i_30_n_0 ),\n .O(\\dec_cnt[2]_i_20_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\dec_cnt[2]_i_21 \n (.I0(\\dec_cnt_reg[2]_i_16_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[2]_i_31_n_0 ),\n .I3(\\largest_left_edge_reg_n_0_[3] ),\n .I4(\\dec_cnt[2]_i_30_n_0 ),\n .O(\\dec_cnt[2]_i_21_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\dec_cnt[2]_i_22 \n (.I0(\\dec_cnt[2]_i_32_n_0 ),\n .I1(\\dec_cnt[2]_i_33_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[3] ),\n .I3(\\dec_cnt[2]_i_27_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[3] ),\n .I5(\\dec_cnt[2]_i_34_n_0 ),\n .O(\\dec_cnt[2]_i_22_n_0 ));\n LUT6 #(\n .INIT(64'hDCC49DC49DCCB9DD)) \n \\dec_cnt[2]_i_23 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[1] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[2]_i_23_n_0 ));\n LUT6 #(\n .INIT(64'h424442C433232323)) \n \\dec_cnt[2]_i_24 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[2]_i_24_n_0 ));\n LUT6 #(\n .INIT(64'h242422242226B222)) \n \\dec_cnt[2]_i_25 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\largest_left_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[2]_i_25_n_0 ));\n LUT6 #(\n .INIT(64'hB39BB39BD9CDD9D9)) \n \\dec_cnt[2]_i_26 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\largest_left_edge_reg_n_0_[1] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[2]_i_26_n_0 ));\n LUT6 #(\n .INIT(64'hCF8FFFCFF7FFF3FF)) \n \\dec_cnt[2]_i_27 \n (.I0(\\largest_left_edge_reg_n_0_[0] ),\n .I1(\\largest_left_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[2]_i_27_n_0 ));\n LUT6 #(\n .INIT(64'h115100108808AA8A)) \n \\dec_cnt[2]_i_28 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\largest_left_edge_reg_n_0_[1] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\smallest_right_edge_reg_n_0_[1] ),\n .I5(\\smallest_right_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[2]_i_28_n_0 ));\n LUT6 #(\n .INIT(64'hDCC49DCC9DCCB9DD)) \n \\dec_cnt[2]_i_29 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[1] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[2]_i_29_n_0 ));\n LUT5 #(\n .INIT(32'hDE8EFFFF)) \n \\dec_cnt[2]_i_3 \n (.I0(\\largest_left_edge_reg_n_0_[4] ),\n .I1(\\dec_cnt[2]_i_6_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[4] ),\n .I3(\\dec_cnt[2]_i_7_n_0 ),\n .I4(\\smallest_right_edge_reg_n_0_[5] ),\n .O(\\dec_cnt[2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h22A225A4AAAAA4A4)) \n \\dec_cnt[2]_i_30 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\largest_left_edge_reg_n_0_[1] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[2]_i_30_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF77011501)) \n \\dec_cnt[2]_i_31 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\largest_left_edge_reg_n_0_[1] ),\n .I2(\\largest_left_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[2]_i_31_n_0 ));\n LUT6 #(\n .INIT(64'h00204404AAAA22A2)) \n \\dec_cnt[2]_i_32 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[1] ),\n .I2(\\largest_left_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\smallest_right_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[2]_i_32_n_0 ));\n LUT6 #(\n .INIT(64'hBB9BB39BD9CDD9D9)) \n \\dec_cnt[2]_i_33 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\largest_left_edge_reg_n_0_[1] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[2]_i_33_n_0 ));\n LUT6 #(\n .INIT(64'h2444242422223222)) \n \\dec_cnt[2]_i_34 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\largest_left_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[2]_i_34_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\dec_cnt[2]_i_5 \n (.I0(\\dec_cnt[2]_i_10_n_0 ),\n .I1(\\dec_cnt[2]_i_11_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[3] ),\n .I3(\\dec_cnt[2]_i_12_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[3] ),\n .I5(\\dec_cnt[2]_i_13_n_0 ),\n .O(\\dec_cnt[2]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hEFEAFFFFFFFFFFFF)) \n \\dec_cnt[2]_i_6 \n (.I0(\\largest_left_edge_reg_n_0_[3] ),\n .I1(\\dec_cnt[2]_i_14_n_0 ),\n .I2(\\largest_left_edge_reg_n_0_[2] ),\n .I3(\\dec_cnt[2]_i_15_n_0 ),\n .I4(\\smallest_right_edge_reg_n_0_[2] ),\n .I5(\\smallest_right_edge_reg_n_0_[3] ),\n .O(\\dec_cnt[2]_i_6_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\dec_cnt[2]_i_7 \n (.I0(\\dec_cnt_reg[2]_i_16_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[2]_i_17_n_0 ),\n .I3(\\largest_left_edge_reg_n_0_[3] ),\n .I4(\\dec_cnt[2]_i_18_n_0 ),\n .O(\\dec_cnt[2]_i_7_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB8CC)) \n \\dec_cnt[3]_i_1 \n (.I0(\\dec_cnt[3]_i_2_n_0 ),\n .I1(\\largest_left_edge_reg_n_0_[5] ),\n .I2(\\dec_cnt[3]_i_3_n_0 ),\n .I3(\\smallest_right_edge_reg_n_0_[5] ),\n .I4(\\dec_cnt[3]_i_4_n_0 ),\n .O(\\dec_cnt[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair32\" *) \n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\dec_cnt[3]_i_10 \n (.I0(\\dec_cnt[3]_i_12_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[5]_i_5_n_0 ),\n .I3(\\largest_left_edge_reg_n_0_[3] ),\n .I4(\\dec_cnt[3]_i_16_n_0 ),\n .O(\\dec_cnt[3]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\dec_cnt[3]_i_11 \n (.I0(\\dec_cnt[5]_i_5_n_0 ),\n .I1(\\dec_cnt[3]_i_21_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[3] ),\n .I3(\\dec_cnt[3]_i_19_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[3] ),\n .I5(\\dec_cnt[3]_i_22_n_0 ),\n .O(\\dec_cnt[3]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'hBBBBBBBBBB8BBBBB)) \n \\dec_cnt[3]_i_12 \n (.I0(\\dec_cnt[3]_i_23_n_0 ),\n .I1(\\largest_left_edge_reg_n_0_[3] ),\n .I2(\\smallest_right_edge_reg_n_0_[2] ),\n .I3(\\dec_cnt[4]_i_11_n_0 ),\n .I4(\\smallest_right_edge_reg_n_0_[1] ),\n .I5(\\largest_left_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[3]_i_12_n_0 ));\n LUT6 #(\n .INIT(64'hBBB888B8BBBBBBBB)) \n \\dec_cnt[3]_i_13 \n (.I0(\\dec_cnt[5]_i_5_n_0 ),\n .I1(\\largest_left_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[3]_i_24_n_0 ),\n .I3(\\smallest_right_edge_reg_n_0_[2] ),\n .I4(\\dec_cnt[3]_i_25_n_0 ),\n .I5(\\largest_left_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[3]_i_13_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair46\" *) \n LUT5 #(\n .INIT(32'hFFFFBFAA)) \n \\dec_cnt[3]_i_14 \n (.I0(\\smallest_right_edge_reg_n_0_[1] ),\n .I1(\\largest_left_edge_reg_n_0_[0] ),\n .I2(\\largest_left_edge_reg_n_0_[1] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\smallest_right_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[3]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFF775FFFF)) \n \\dec_cnt[3]_i_15 \n (.I0(\\smallest_right_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[0] ),\n .I2(\\largest_left_edge_reg_n_0_[0] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[1] ),\n .I5(\\largest_left_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[3]_i_15_n_0 ));\n LUT6 #(\n .INIT(64'hF1115111FFFFFFFF)) \n \\dec_cnt[3]_i_16 \n (.I0(\\largest_left_edge_reg_n_0_[1] ),\n .I1(\\largest_left_edge_reg_n_0_[0] ),\n .I2(\\smallest_right_edge_reg_n_0_[2] ),\n .I3(\\smallest_right_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\largest_left_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[3]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'h6C6C66642626B226)) \n \\dec_cnt[3]_i_17 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\largest_left_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[3]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'hB8883333B8880000)) \n \\dec_cnt[3]_i_18 \n (.I0(\\dec_cnt[3]_i_26_n_0 ),\n .I1(\\largest_left_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[4]_i_15_n_0 ),\n .I3(\\smallest_right_edge_reg_n_0_[2] ),\n .I4(\\largest_left_edge_reg_n_0_[2] ),\n .I5(\\dec_cnt[3]_i_27_n_0 ),\n .O(\\dec_cnt[3]_i_18_n_0 ));\n LUT6 #(\n .INIT(64'hCF8FFFCFFFFFFFFF)) \n \\dec_cnt[3]_i_19 \n (.I0(\\largest_left_edge_reg_n_0_[0] ),\n .I1(\\largest_left_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[3]_i_19_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF00FFB8FFB800)) \n \\dec_cnt[3]_i_2 \n (.I0(\\dec_cnt[3]_i_5_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[3]_i_6_n_0 ),\n .I3(\\smallest_right_edge_reg_n_0_[4] ),\n .I4(\\dec_cnt[3]_i_7_n_0 ),\n .I5(\\largest_left_edge_reg_n_0_[4] ),\n .O(\\dec_cnt[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00000000AB2A2222)) \n \\dec_cnt[3]_i_20 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[1] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\smallest_right_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[3]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'h4444DD4500000000)) \n \\dec_cnt[3]_i_21 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[1] ),\n .I2(\\largest_left_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\smallest_right_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[3]_i_21_n_0 ));\n LUT6 #(\n .INIT(64'h5515110100000000)) \n \\dec_cnt[3]_i_22 \n (.I0(\\smallest_right_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[1] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\largest_left_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[3]_i_22_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFCDDD4CCC)) \n \\dec_cnt[3]_i_23 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[1] ),\n .I2(\\largest_left_edge_reg_n_0_[0] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[0] ),\n .I5(\\smallest_right_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[3]_i_23_n_0 ));\n LUT2 #(\n .INIT(4'h1)) \n \\dec_cnt[3]_i_24 \n (.I0(\\largest_left_edge_reg_n_0_[0] ),\n .I1(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[3]_i_24_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair57\" *) \n LUT4 #(\n .INIT(16'h8CCF)) \n \\dec_cnt[3]_i_25 \n (.I0(\\smallest_right_edge_reg_n_0_[0] ),\n .I1(\\smallest_right_edge_reg_n_0_[1] ),\n .I2(\\largest_left_edge_reg_n_0_[0] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[3]_i_25_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair34\" *) \n LUT5 #(\n .INIT(32'h445455D5)) \n \\dec_cnt[3]_i_26 \n (.I0(\\smallest_right_edge_reg_n_0_[2] ),\n .I1(\\largest_left_edge_reg_n_0_[1] ),\n .I2(\\largest_left_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[3]_i_26_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair46\" *) \n LUT5 #(\n .INIT(32'hAAFB0000)) \n \\dec_cnt[3]_i_27 \n (.I0(\\smallest_right_edge_reg_n_0_[1] ),\n .I1(\\largest_left_edge_reg_n_0_[0] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .I4(\\smallest_right_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[3]_i_27_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\dec_cnt[3]_i_3 \n (.I0(\\dec_cnt[3]_i_8_n_0 ),\n .I1(\\dec_cnt[3]_i_9_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[4] ),\n .I3(\\dec_cnt[3]_i_10_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[4] ),\n .I5(\\dec_cnt[3]_i_11_n_0 ),\n .O(\\dec_cnt[3]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF00FFB8FFB800)) \n \\dec_cnt[3]_i_4 \n (.I0(\\dec_cnt[3]_i_12_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[3]_i_13_n_0 ),\n .I3(\\smallest_right_edge_reg_n_0_[4] ),\n .I4(\\dec_cnt[3]_i_7_n_0 ),\n .I5(\\largest_left_edge_reg_n_0_[4] ),\n .O(\\dec_cnt[3]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hEFE0FFFFEFE00000)) \n \\dec_cnt[3]_i_5 \n (.I0(\\dec_cnt[4]_i_16_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\largest_left_edge_reg_n_0_[2] ),\n .I3(\\dec_cnt[3]_i_14_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[3] ),\n .I5(\\dec_cnt[3]_i_15_n_0 ),\n .O(\\dec_cnt[3]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair32\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\dec_cnt[3]_i_6 \n (.I0(\\dec_cnt[5]_i_5_n_0 ),\n .I1(\\largest_left_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[3]_i_16_n_0 ),\n .O(\\dec_cnt[3]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair56\" *) \n LUT4 #(\n .INIT(16'hF3B8)) \n \\dec_cnt[3]_i_7 \n (.I0(\\dec_cnt[3]_i_17_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[5]_i_6_n_0 ),\n .I3(\\largest_left_edge_reg_n_0_[3] ),\n .O(\\dec_cnt[3]_i_7_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\dec_cnt[3]_i_8 \n (.I0(\\dec_cnt[3]_i_18_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[3]_i_19_n_0 ),\n .I3(\\largest_left_edge_reg_n_0_[3] ),\n .I4(\\dec_cnt[3]_i_20_n_0 ),\n .O(\\dec_cnt[3]_i_8_n_0 ));\n LUT4 #(\n .INIT(16'h88B8)) \n \\dec_cnt[3]_i_9 \n (.I0(\\dec_cnt[3]_i_5_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[3]_i_16_n_0 ),\n .I3(\\largest_left_edge_reg_n_0_[3] ),\n .O(\\dec_cnt[3]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hEFEAFFFF4540AAAA)) \n \\dec_cnt[4]_i_1 \n (.I0(\\largest_left_edge_reg_n_0_[5] ),\n .I1(\\dec_cnt_reg[4]_i_2_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[4] ),\n .I3(\\dec_cnt[4]_i_3_n_0 ),\n .I4(\\smallest_right_edge_reg_n_0_[5] ),\n .I5(\\dec_cnt[4]_i_4_n_0 ),\n .O(\\dec_cnt[4]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair53\" *) \n LUT4 #(\n .INIT(16'hF3B8)) \n \\dec_cnt[4]_i_10 \n (.I0(\\dec_cnt[5]_i_5_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[5]_i_6_n_0 ),\n .I3(\\largest_left_edge_reg_n_0_[3] ),\n .O(\\dec_cnt[4]_i_10_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair72\" *) \n LUT3 #(\n .INIT(8'h8E)) \n \\dec_cnt[4]_i_11 \n (.I0(\\largest_left_edge_reg_n_0_[1] ),\n .I1(\\largest_left_edge_reg_n_0_[0] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[4]_i_11_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair34\" *) \n LUT5 #(\n .INIT(32'hBABBA2AA)) \n \\dec_cnt[4]_i_12 \n (.I0(\\smallest_right_edge_reg_n_0_[2] ),\n .I1(\\largest_left_edge_reg_n_0_[1] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[4]_i_12_n_0 ));\n LUT6 #(\n .INIT(64'h3000703000000000)) \n \\dec_cnt[4]_i_13 \n (.I0(\\largest_left_edge_reg_n_0_[0] ),\n .I1(\\largest_left_edge_reg_n_0_[2] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\smallest_right_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[4]_i_13_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF5D45DDDD)) \n \\dec_cnt[4]_i_14 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[1] ),\n .I2(\\largest_left_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\smallest_right_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[4]_i_14_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair57\" *) \n LUT4 #(\n .INIT(16'h0400)) \n \\dec_cnt[4]_i_15 \n (.I0(\\largest_left_edge_reg_n_0_[1] ),\n .I1(\\smallest_right_edge_reg_n_0_[0] ),\n .I2(\\largest_left_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[4]_i_15_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair71\" *) \n LUT3 #(\n .INIT(8'hD0)) \n \\dec_cnt[4]_i_16 \n (.I0(\\largest_left_edge_reg_n_0_[1] ),\n .I1(\\smallest_right_edge_reg_n_0_[0] ),\n .I2(\\smallest_right_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[4]_i_16_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair58\" *) \n LUT4 #(\n .INIT(16'h20BA)) \n \\dec_cnt[4]_i_17 \n (.I0(\\smallest_right_edge_reg_n_0_[1] ),\n .I1(\\largest_left_edge_reg_n_0_[0] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\largest_left_edge_reg_n_0_[1] ),\n .O(\\dec_cnt[4]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'hB8BBBBBBB8BB8888)) \n \\dec_cnt[4]_i_3 \n (.I0(\\dec_cnt[4]_i_7_n_0 ),\n .I1(\\largest_left_edge_reg_n_0_[4] ),\n .I2(\\dec_cnt[4]_i_8_n_0 ),\n .I3(\\largest_left_edge_reg_n_0_[3] ),\n .I4(\\smallest_right_edge_reg_n_0_[3] ),\n .I5(\\dec_cnt[4]_i_9_n_0 ),\n .O(\\dec_cnt[4]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'hF3B8)) \n \\dec_cnt[4]_i_4 \n (.I0(\\dec_cnt[4]_i_7_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[4] ),\n .I2(\\dec_cnt[4]_i_10_n_0 ),\n .I3(\\largest_left_edge_reg_n_0_[4] ),\n .O(\\dec_cnt[4]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFBFFFFFFFFFF)) \n \\dec_cnt[4]_i_5 \n (.I0(\\largest_left_edge_reg_n_0_[3] ),\n .I1(\\smallest_right_edge_reg_n_0_[2] ),\n .I2(\\dec_cnt[4]_i_11_n_0 ),\n .I3(\\smallest_right_edge_reg_n_0_[1] ),\n .I4(\\largest_left_edge_reg_n_0_[2] ),\n .I5(\\smallest_right_edge_reg_n_0_[3] ),\n .O(\\dec_cnt[4]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hDFD0FFFFDFD0F0F0)) \n \\dec_cnt[4]_i_6 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\dec_cnt[4]_i_12_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[3] ),\n .I3(\\dec_cnt[4]_i_13_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[3] ),\n .I5(\\dec_cnt[4]_i_14_n_0 ),\n .O(\\dec_cnt[4]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair53\" *) \n LUT4 #(\n .INIT(16'hB888)) \n \\dec_cnt[4]_i_7 \n (.I0(\\dec_cnt[5]_i_4_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[5]_i_5_n_0 ),\n .I3(\\largest_left_edge_reg_n_0_[3] ),\n .O(\\dec_cnt[4]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hFFDFFFFF5545DD5D)) \n \\dec_cnt[4]_i_8 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[1] ),\n .I2(\\largest_left_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\smallest_right_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[4]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'hAF0FAF00CF0FCF0F)) \n \\dec_cnt[4]_i_9 \n (.I0(\\dec_cnt[4]_i_15_n_0 ),\n .I1(\\dec_cnt[4]_i_16_n_0 ),\n .I2(\\largest_left_edge_reg_n_0_[3] ),\n .I3(\\smallest_right_edge_reg_n_0_[2] ),\n .I4(\\dec_cnt[4]_i_17_n_0 ),\n .I5(\\largest_left_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[4]_i_9_n_0 ));\n LUT4 #(\n .INIT(16'hEF4A)) \n \\dec_cnt[5]_i_1 \n (.I0(\\largest_left_edge_reg_n_0_[5] ),\n .I1(\\dec_cnt[5]_i_2_n_0 ),\n .I2(\\smallest_right_edge_reg_n_0_[5] ),\n .I3(\\dec_cnt[5]_i_3_n_0 ),\n .O(\\dec_cnt[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0300000080808080)) \n \\dec_cnt[5]_i_2 \n (.I0(\\dec_cnt[5]_i_4_n_0 ),\n .I1(\\smallest_right_edge_reg_n_0_[4] ),\n .I2(\\smallest_right_edge_reg_n_0_[3] ),\n .I3(\\dec_cnt[5]_i_5_n_0 ),\n .I4(\\largest_left_edge_reg_n_0_[3] ),\n .I5(\\largest_left_edge_reg_n_0_[4] ),\n .O(\\dec_cnt[5]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hF7FDD5FD51DC4054)) \n \\dec_cnt[5]_i_3 \n (.I0(\\smallest_right_edge_reg_n_0_[4] ),\n .I1(\\largest_left_edge_reg_n_0_[3] ),\n .I2(\\dec_cnt[5]_i_6_n_0 ),\n .I3(\\smallest_right_edge_reg_n_0_[3] ),\n .I4(\\dec_cnt[5]_i_5_n_0 ),\n .I5(\\largest_left_edge_reg_n_0_[4] ),\n .O(\\dec_cnt[5]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'h00004000)) \n \\dec_cnt[5]_i_4 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[1] ),\n .I2(\\dec_cnt[5]_i_7_n_0 ),\n .I3(\\smallest_right_edge_reg_n_0_[2] ),\n .I4(\\largest_left_edge_reg_n_0_[3] ),\n .O(\\dec_cnt[5]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h02000000ABAA2A22)) \n \\dec_cnt[5]_i_5 \n (.I0(\\largest_left_edge_reg_n_0_[2] ),\n .I1(\\smallest_right_edge_reg_n_0_[1] ),\n .I2(\\smallest_right_edge_reg_n_0_[0] ),\n .I3(\\largest_left_edge_reg_n_0_[0] ),\n .I4(\\largest_left_edge_reg_n_0_[1] ),\n .I5(\\smallest_right_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[5]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFDDFDFFFF)) \n \\dec_cnt[5]_i_6 \n (.I0(\\smallest_right_edge_reg_n_0_[2] ),\n .I1(\\largest_left_edge_reg_n_0_[1] ),\n .I2(\\largest_left_edge_reg_n_0_[0] ),\n .I3(\\smallest_right_edge_reg_n_0_[0] ),\n .I4(\\smallest_right_edge_reg_n_0_[1] ),\n .I5(\\largest_left_edge_reg_n_0_[2] ),\n .O(\\dec_cnt[5]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair72\" *) \n LUT3 #(\n .INIT(8'h4D)) \n \\dec_cnt[5]_i_7 \n (.I0(\\largest_left_edge_reg_n_0_[1] ),\n .I1(\\smallest_right_edge_reg_n_0_[0] ),\n .I2(\\largest_left_edge_reg_n_0_[0] ),\n .O(\\dec_cnt[5]_i_7_n_0 ));\n FDRE \\dec_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dec_cnt[0]_i_1_n_0 ),\n .Q(\\prbs_dec_tap_cnt_reg[1]_0 [0]),\n .R(1'b0));\n MUXF8 \\dec_cnt_reg[0]_i_10 \n (.I0(\\dec_cnt_reg[0]_i_27_n_0 ),\n .I1(\\dec_cnt_reg[0]_i_28_n_0 ),\n .O(\\dec_cnt_reg[0]_i_10_n_0 ),\n .S(\\smallest_right_edge_reg_n_0_[3] ));\n MUXF8 \\dec_cnt_reg[0]_i_12 \n (.I0(\\dec_cnt_reg[0]_i_30_n_0 ),\n .I1(\\dec_cnt_reg[0]_i_31_n_0 ),\n .O(\\dec_cnt_reg[0]_i_12_n_0 ),\n .S(\\smallest_right_edge_reg_n_0_[3] ));\n MUXF7 \\dec_cnt_reg[0]_i_18 \n (.I0(\\dec_cnt[0]_i_36_n_0 ),\n .I1(\\dec_cnt[0]_i_37_n_0 ),\n .O(\\dec_cnt_reg[0]_i_18_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[3] ));\n MUXF7 \\dec_cnt_reg[0]_i_19 \n (.I0(\\dec_cnt[0]_i_38_n_0 ),\n .I1(\\dec_cnt[0]_i_39_n_0 ),\n .O(\\dec_cnt_reg[0]_i_19_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[3] ));\n MUXF7 \\dec_cnt_reg[0]_i_2 \n (.I0(\\dec_cnt[0]_i_5_n_0 ),\n .I1(\\dec_cnt[0]_i_6_n_0 ),\n .O(\\dec_cnt_reg[0]_i_2_n_0 ),\n .S(\\smallest_right_edge_reg_n_0_[4] ));\n MUXF7 \\dec_cnt_reg[0]_i_27 \n (.I0(\\dec_cnt[0]_i_40_n_0 ),\n .I1(\\dec_cnt[0]_i_41_n_0 ),\n .O(\\dec_cnt_reg[0]_i_27_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[3] ));\n MUXF7 \\dec_cnt_reg[0]_i_28 \n (.I0(\\dec_cnt[0]_i_42_n_0 ),\n .I1(\\dec_cnt[0]_i_43_n_0 ),\n .O(\\dec_cnt_reg[0]_i_28_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[3] ));\n MUXF7 \\dec_cnt_reg[0]_i_30 \n (.I0(\\dec_cnt[0]_i_44_n_0 ),\n .I1(\\dec_cnt[0]_i_45_n_0 ),\n .O(\\dec_cnt_reg[0]_i_30_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[3] ));\n MUXF7 \\dec_cnt_reg[0]_i_31 \n (.I0(\\dec_cnt[0]_i_46_n_0 ),\n .I1(\\dec_cnt[0]_i_47_n_0 ),\n .O(\\dec_cnt_reg[0]_i_31_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[3] ));\n MUXF8 \\dec_cnt_reg[0]_i_7 \n (.I0(\\dec_cnt_reg[0]_i_18_n_0 ),\n .I1(\\dec_cnt_reg[0]_i_19_n_0 ),\n .O(\\dec_cnt_reg[0]_i_7_n_0 ),\n .S(\\smallest_right_edge_reg_n_0_[3] ));\n FDRE \\dec_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dec_cnt[1]_i_1_n_0 ),\n .Q(dec_cnt_reg[1]),\n .R(1'b0));\n MUXF8 \\dec_cnt_reg[1]_i_10 \n (.I0(\\dec_cnt_reg[1]_i_23_n_0 ),\n .I1(\\dec_cnt_reg[1]_i_24_n_0 ),\n .O(\\dec_cnt_reg[1]_i_10_n_0 ),\n .S(\\smallest_right_edge_reg_n_0_[3] ));\n MUXF7 \\dec_cnt_reg[1]_i_11 \n (.I0(\\dec_cnt[1]_i_25_n_0 ),\n .I1(\\dec_cnt[1]_i_26_n_0 ),\n .O(\\dec_cnt_reg[1]_i_11_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[3] ));\n MUXF7 \\dec_cnt_reg[1]_i_12 \n (.I0(\\dec_cnt[1]_i_27_n_0 ),\n .I1(\\dec_cnt[1]_i_28_n_0 ),\n .O(\\dec_cnt_reg[1]_i_12_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[3] ));\n MUXF7 \\dec_cnt_reg[1]_i_14 \n (.I0(\\dec_cnt[1]_i_29_n_0 ),\n .I1(\\dec_cnt[1]_i_30_n_0 ),\n .O(\\dec_cnt_reg[1]_i_14_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[3] ));\n MUXF7 \\dec_cnt_reg[1]_i_17 \n (.I0(\\dec_cnt[1]_i_31_n_0 ),\n .I1(\\dec_cnt[1]_i_32_n_0 ),\n .O(\\dec_cnt_reg[1]_i_17_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[3] ));\n MUXF7 \\dec_cnt_reg[1]_i_18 \n (.I0(\\dec_cnt[1]_i_33_n_0 ),\n .I1(\\dec_cnt[1]_i_34_n_0 ),\n .O(\\dec_cnt_reg[1]_i_18_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[3] ));\n MUXF7 \\dec_cnt_reg[1]_i_23 \n (.I0(\\dec_cnt[1]_i_35_n_0 ),\n .I1(\\dec_cnt[1]_i_36_n_0 ),\n .O(\\dec_cnt_reg[1]_i_23_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[3] ));\n MUXF7 \\dec_cnt_reg[1]_i_24 \n (.I0(\\dec_cnt[1]_i_37_n_0 ),\n .I1(\\dec_cnt[1]_i_38_n_0 ),\n .O(\\dec_cnt_reg[1]_i_24_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[3] ));\n MUXF8 \\dec_cnt_reg[1]_i_7 \n (.I0(\\dec_cnt_reg[1]_i_17_n_0 ),\n .I1(\\dec_cnt_reg[1]_i_18_n_0 ),\n .O(\\dec_cnt_reg[1]_i_7_n_0 ),\n .S(\\smallest_right_edge_reg_n_0_[3] ));\n FDRE \\dec_cnt_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dec_cnt_reg[2]_i_1_n_0 ),\n .Q(dec_cnt_reg[2]),\n .R(1'b0));\n MUXF7 \\dec_cnt_reg[2]_i_1 \n (.I0(\\dec_cnt[2]_i_2_n_0 ),\n .I1(\\dec_cnt[2]_i_3_n_0 ),\n .O(\\dec_cnt_reg[2]_i_1_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[5] ));\n MUXF7 \\dec_cnt_reg[2]_i_16 \n (.I0(\\dec_cnt[2]_i_23_n_0 ),\n .I1(\\dec_cnt[2]_i_24_n_0 ),\n .O(\\dec_cnt_reg[2]_i_16_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[3] ));\n MUXF8 \\dec_cnt_reg[2]_i_4 \n (.I0(\\dec_cnt_reg[2]_i_8_n_0 ),\n .I1(\\dec_cnt_reg[2]_i_9_n_0 ),\n .O(\\dec_cnt_reg[2]_i_4_n_0 ),\n .S(\\smallest_right_edge_reg_n_0_[4] ));\n MUXF7 \\dec_cnt_reg[2]_i_8 \n (.I0(\\dec_cnt[2]_i_19_n_0 ),\n .I1(\\dec_cnt[2]_i_20_n_0 ),\n .O(\\dec_cnt_reg[2]_i_8_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[4] ));\n MUXF7 \\dec_cnt_reg[2]_i_9 \n (.I0(\\dec_cnt[2]_i_21_n_0 ),\n .I1(\\dec_cnt[2]_i_22_n_0 ),\n .O(\\dec_cnt_reg[2]_i_9_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[4] ));\n FDRE \\dec_cnt_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dec_cnt[3]_i_1_n_0 ),\n .Q(dec_cnt_reg[3]),\n .R(1'b0));\n FDRE \\dec_cnt_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dec_cnt[4]_i_1_n_0 ),\n .Q(dec_cnt_reg[4]),\n .R(1'b0));\n MUXF7 \\dec_cnt_reg[4]_i_2 \n (.I0(\\dec_cnt[4]_i_5_n_0 ),\n .I1(\\dec_cnt[4]_i_6_n_0 ),\n .O(\\dec_cnt_reg[4]_i_2_n_0 ),\n .S(\\largest_left_edge_reg_n_0_[4] ));\n FDRE \\dec_cnt_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dec_cnt[5]_i_1_n_0 ),\n .Q(\\prbs_dec_tap_cnt_reg[1]_0 [1]),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair35\" *) \n LUT3 #(\n .INIT(8'h7F)) \n err_chk_invalid_i_1\n (.I0(wait_state_cnt_r_reg__0[3]),\n .I1(wait_state_cnt_r_reg__0[1]),\n .I2(wait_state_cnt_r_reg__0[2]),\n .O(err_chk_invalid_i_1_n_0));\n FDRE err_chk_invalid_reg\n (.C(CLK),\n .CE(1'b1),\n .D(err_chk_invalid_i_1_n_0),\n .Q(err_chk_invalid),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h2)) \n \\fine_delay_mod[11]_i_8 \n (.I0(\\fine_delay_mod_reg[20] ),\n .I1(\\A[2]__2 ),\n .O(\\fine_delay_mod_reg[5] ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFD)) \n fine_delay_sel_i_2\n (.I0(Q[4]),\n .I1(fine_delay_sel_i_4_n_0),\n .I2(bit_cnt_reg__0[7]),\n .I3(bit_cnt_reg__0[6]),\n .I4(bit_cnt_reg__0[4]),\n .I5(bit_cnt_reg__0[5]),\n .O(fine_delay_sel_reg_0));\n (* SOFT_HLUTNM = \"soft_lutpair43\" *) \n LUT3 #(\n .INIT(8'hBD)) \n fine_delay_sel_i_3\n (.I0(Q[1]),\n .I1(Q[2]),\n .I2(Q[3]),\n .O(fine_delay_sel_reg_1));\n (* SOFT_HLUTNM = \"soft_lutpair42\" *) \n LUT4 #(\n .INIT(16'hFFEF)) \n fine_delay_sel_i_4\n (.I0(bit_cnt_reg__0[2]),\n .I1(bit_cnt_reg__0[0]),\n .I2(bit_cnt_reg__0[3]),\n .I3(bit_cnt_reg__0[1]),\n .O(fine_delay_sel_i_4_n_0));\n FDRE fine_delay_sel_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\prbs_state_r_reg[0]_0 ),\n .Q(fine_delay_sel_r_reg),\n .R(rstdiv0_sync_r1_reg_rep__7));\n LUT6 #(\n .INIT(64'h0100000022002200)) \n fine_dly_error_i_2\n (.I0(Q[2]),\n .I1(Q[3]),\n .I2(\\stage_cnt_reg_n_0_[0] ),\n .I3(\\prbs_dec_tap_cnt[2]_i_3_n_0 ),\n .I4(\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ),\n .I5(Q[4]),\n .O(fine_dly_error_reg_0));\n FDRE fine_dly_error_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\dec_cnt_reg[0]_0 ),\n .Q(prbs_rdlvl_done_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__2));\n (* SOFT_HLUTNM = \"soft_lutpair83\" *) \n LUT2 #(\n .INIT(4'h7)) \n fine_inc_stage_i_1\n (.I0(\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ),\n .I1(\\stage_cnt_reg_n_0_[0] ),\n .O(fine_inc_stage_i_1_n_0));\n FDSE fine_inc_stage_reg\n (.C(CLK),\n .CE(1'b1),\n .D(fine_inc_stage_i_1_n_0),\n .Q(fine_inc_stage_reg_n_0),\n .S(rstdiv0_sync_r1_reg_rep__8));\n LUT5 #(\n .INIT(32'h74777444)) \n \\fine_pi_dec_cnt[0]_i_1 \n (.I0(\\fine_pi_dec_cnt_reg_n_0_[0] ),\n .I1(Q[2]),\n .I2(\\fine_pi_dec_cnt[0]_i_2_n_0 ),\n .I3(Q[1]),\n .I4(\\rdlvl_cpt_tap_cnt_reg[5]_1 [0]),\n .O(\\fine_pi_dec_cnt[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8A8ABA8ABA8ABA8A)) \n \\fine_pi_dec_cnt[0]_i_2 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I1(\\stage_cnt_reg_n_0_[0] ),\n .I2(\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ),\n .I3(\\fine_pi_dec_cnt_reg[3]_i_3_n_7 ),\n .I4(\\prbs_dec_tap_cnt_reg[1]_0 [1]),\n .I5(\\prbs_dec_tap_cnt_reg[1]_0 [0]),\n .O(\\fine_pi_dec_cnt[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h9F909F9F9F909090)) \n \\fine_pi_dec_cnt[1]_i_1 \n (.I0(\\fine_pi_dec_cnt_reg_n_0_[0] ),\n .I1(\\fine_pi_dec_cnt_reg_n_0_[1] ),\n .I2(Q[2]),\n .I3(\\fine_pi_dec_cnt[1]_i_2_n_0 ),\n .I4(Q[1]),\n .I5(\\calib_sel_reg[3]_0 ),\n .O(\\fine_pi_dec_cnt[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8A8ABA8ABA8ABA8A)) \n \\fine_pi_dec_cnt[1]_i_2 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I1(\\stage_cnt_reg_n_0_[0] ),\n .I2(\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ),\n .I3(\\fine_pi_dec_cnt_reg[3]_i_3_n_6 ),\n .I4(\\prbs_dec_tap_cnt_reg[1]_0 [1]),\n .I5(\\prbs_dec_tap_cnt_reg[1]_0 [0]),\n .O(\\fine_pi_dec_cnt[1]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hE1FFE100)) \n \\fine_pi_dec_cnt[2]_i_1 \n (.I0(\\fine_pi_dec_cnt_reg_n_0_[1] ),\n .I1(\\fine_pi_dec_cnt_reg_n_0_[0] ),\n .I2(\\fine_pi_dec_cnt_reg_n_0_[2] ),\n .I3(Q[2]),\n .I4(\\fine_pi_dec_cnt[2]_i_2_n_0 ),\n .O(\\fine_pi_dec_cnt[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h88B8FFFF88B80000)) \n \\fine_pi_dec_cnt[2]_i_2 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I1(\\fine_pi_dec_cnt[5]_i_7_n_0 ),\n .I2(\\fine_pi_dec_cnt_reg[3]_i_3_n_5 ),\n .I3(\\prbs_dec_tap_cnt[2]_i_3_n_0 ),\n .I4(Q[1]),\n .I5(\\calib_sel_reg[3]_1 ),\n .O(\\fine_pi_dec_cnt[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFE01FFFFFE010000)) \n \\fine_pi_dec_cnt[3]_i_1 \n (.I0(\\fine_pi_dec_cnt_reg_n_0_[0] ),\n .I1(\\fine_pi_dec_cnt_reg_n_0_[1] ),\n .I2(\\fine_pi_dec_cnt_reg_n_0_[2] ),\n .I3(\\fine_pi_dec_cnt_reg_n_0_[3] ),\n .I4(Q[2]),\n .I5(\\fine_pi_dec_cnt[3]_i_2_n_0 ),\n .O(\\fine_pi_dec_cnt[3]_i_1_n_0 ));\n (* HLUTNM = \"lutpair3\" *) \n LUT3 #(\n .INIT(8'h96)) \n \\fine_pi_dec_cnt[3]_i_10 \n (.I0(\\prbs_dec_tap_cnt_reg[1]_0 [0]),\n .I1(\\smallest_right_edge_reg_n_0_[0] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .O(\\fine_pi_dec_cnt[3]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'h88B8FFFF88B80000)) \n \\fine_pi_dec_cnt[3]_i_2 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I1(\\fine_pi_dec_cnt[5]_i_7_n_0 ),\n .I2(\\fine_pi_dec_cnt_reg[3]_i_3_n_4 ),\n .I3(\\prbs_dec_tap_cnt[2]_i_3_n_0 ),\n .I4(Q[1]),\n .I5(\\rdlvl_cpt_tap_cnt_reg[5]_1 [1]),\n .O(\\fine_pi_dec_cnt[3]_i_2_n_0 ));\n (* HLUTNM = \"lutpair1\" *) \n LUT3 #(\n .INIT(8'hD4)) \n \\fine_pi_dec_cnt[3]_i_4 \n (.I0(\\smallest_right_edge_reg_n_0_[2] ),\n .I1(dec_cnt_reg[2]),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .O(\\fine_pi_dec_cnt[3]_i_4_n_0 ));\n (* HLUTNM = \"lutpair0\" *) \n LUT3 #(\n .INIT(8'hD4)) \n \\fine_pi_dec_cnt[3]_i_5 \n (.I0(\\smallest_right_edge_reg_n_0_[1] ),\n .I1(dec_cnt_reg[1]),\n .I2(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\fine_pi_dec_cnt[3]_i_5_n_0 ));\n (* HLUTNM = \"lutpair3\" *) \n LUT2 #(\n .INIT(4'hB)) \n \\fine_pi_dec_cnt[3]_i_6 \n (.I0(\\prbs_dec_tap_cnt_reg[1]_0 [0]),\n .I1(\\smallest_right_edge_reg_n_0_[0] ),\n .O(\\fine_pi_dec_cnt[3]_i_6_n_0 ));\n (* HLUTNM = \"lutpair2\" *) \n LUT4 #(\n .INIT(16'h9669)) \n \\fine_pi_dec_cnt[3]_i_7 \n (.I0(\\smallest_right_edge_reg_n_0_[3] ),\n .I1(dec_cnt_reg[3]),\n .I2(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I3(\\fine_pi_dec_cnt[3]_i_4_n_0 ),\n .O(\\fine_pi_dec_cnt[3]_i_7_n_0 ));\n (* HLUTNM = \"lutpair1\" *) \n LUT4 #(\n .INIT(16'h9669)) \n \\fine_pi_dec_cnt[3]_i_8 \n (.I0(\\smallest_right_edge_reg_n_0_[2] ),\n .I1(dec_cnt_reg[2]),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\fine_pi_dec_cnt[3]_i_5_n_0 ),\n .O(\\fine_pi_dec_cnt[3]_i_8_n_0 ));\n (* HLUTNM = \"lutpair0\" *) \n LUT4 #(\n .INIT(16'h9669)) \n \\fine_pi_dec_cnt[3]_i_9 \n (.I0(\\smallest_right_edge_reg_n_0_[1] ),\n .I1(dec_cnt_reg[1]),\n .I2(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I3(\\fine_pi_dec_cnt[3]_i_6_n_0 ),\n .O(\\fine_pi_dec_cnt[3]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'h88B8FFFF88B80000)) \n \\fine_pi_dec_cnt[4]_i_2 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\fine_pi_dec_cnt[5]_i_7_n_0 ),\n .I2(\\fine_pi_dec_cnt_reg[5]_i_8_n_7 ),\n .I3(\\prbs_dec_tap_cnt[2]_i_3_n_0 ),\n .I4(Q[1]),\n .I5(\\calib_sel_reg[3]_2 ),\n .O(\\fine_pi_dec_cnt[4]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFE0001)) \n \\fine_pi_dec_cnt[4]_i_3 \n (.I0(\\fine_pi_dec_cnt_reg_n_0_[3] ),\n .I1(\\fine_pi_dec_cnt_reg_n_0_[2] ),\n .I2(\\fine_pi_dec_cnt_reg_n_0_[1] ),\n .I3(\\fine_pi_dec_cnt_reg_n_0_[0] ),\n .I4(\\fine_pi_dec_cnt_reg_n_0_[4] ),\n .O(\\fine_pi_dec_cnt[4]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h8E71718E718E8E71)) \n \\fine_pi_dec_cnt[5]_i_10 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(dec_cnt_reg[4]),\n .I2(\\smallest_right_edge_reg_n_0_[4] ),\n .I3(\\prbs_dec_tap_cnt_reg[1]_0 [1]),\n .I4(\\smallest_right_edge_reg_n_0_[5] ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\fine_pi_dec_cnt[5]_i_10_n_0 ));\n LUT4 #(\n .INIT(16'h9669)) \n \\fine_pi_dec_cnt[5]_i_11 \n (.I0(\\fine_pi_dec_cnt[5]_i_9_n_0 ),\n .I1(dec_cnt_reg[4]),\n .I2(\\smallest_right_edge_reg_n_0_[4] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .O(\\fine_pi_dec_cnt[5]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000004)) \n \\fine_pi_dec_cnt[5]_i_3 \n (.I0(prbs_rdlvl_start_r),\n .I1(prbs_rdlvl_start_reg),\n .I2(Q[3]),\n .I3(Q[2]),\n .I4(Q[4]),\n .I5(Q[1]),\n .O(\\fine_pi_dec_cnt[5]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h1010180800001808)) \n \\fine_pi_dec_cnt[5]_i_4 \n (.I0(Q[1]),\n .I1(Q[4]),\n .I2(Q[3]),\n .I3(cnt_wait_state),\n .I4(Q[2]),\n .I5(prbs_tap_en_r_reg_0),\n .O(\\fine_pi_dec_cnt[5]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hBBB8FFFFBBB80000)) \n \\fine_pi_dec_cnt[5]_i_5 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .I1(\\fine_pi_dec_cnt[5]_i_7_n_0 ),\n .I2(\\prbs_dec_tap_cnt[2]_i_3_n_0 ),\n .I3(\\fine_pi_dec_cnt_reg[5]_i_8_n_6 ),\n .I4(Q[1]),\n .I5(\\rdlvl_cpt_tap_cnt_reg[5]_1 [2]),\n .O(\\fine_pi_dec_cnt[5]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFE00000001)) \n \\fine_pi_dec_cnt[5]_i_6 \n (.I0(\\fine_pi_dec_cnt_reg_n_0_[4] ),\n .I1(\\fine_pi_dec_cnt_reg_n_0_[0] ),\n .I2(\\fine_pi_dec_cnt_reg_n_0_[1] ),\n .I3(\\fine_pi_dec_cnt_reg_n_0_[2] ),\n .I4(\\fine_pi_dec_cnt_reg_n_0_[3] ),\n .I5(\\fine_pi_dec_cnt_reg_n_0_[5] ),\n .O(\\fine_pi_dec_cnt[5]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair83\" *) \n LUT2 #(\n .INIT(4'hB)) \n \\fine_pi_dec_cnt[5]_i_7 \n (.I0(\\stage_cnt_reg_n_0_[0] ),\n .I1(\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ),\n .O(\\fine_pi_dec_cnt[5]_i_7_n_0 ));\n (* HLUTNM = \"lutpair2\" *) \n LUT3 #(\n .INIT(8'hD4)) \n \\fine_pi_dec_cnt[5]_i_9 \n (.I0(\\smallest_right_edge_reg_n_0_[3] ),\n .I1(dec_cnt_reg[3]),\n .I2(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\fine_pi_dec_cnt[5]_i_9_n_0 ));\n FDRE \\fine_pi_dec_cnt_reg[0] \n (.C(CLK),\n .CE(fine_pi_dec_cnt),\n .D(\\fine_pi_dec_cnt[0]_i_1_n_0 ),\n .Q(\\fine_pi_dec_cnt_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE \\fine_pi_dec_cnt_reg[1] \n (.C(CLK),\n .CE(fine_pi_dec_cnt),\n .D(\\fine_pi_dec_cnt[1]_i_1_n_0 ),\n .Q(\\fine_pi_dec_cnt_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE \\fine_pi_dec_cnt_reg[2] \n (.C(CLK),\n .CE(fine_pi_dec_cnt),\n .D(\\fine_pi_dec_cnt[2]_i_1_n_0 ),\n .Q(\\fine_pi_dec_cnt_reg_n_0_[2] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE \\fine_pi_dec_cnt_reg[3] \n (.C(CLK),\n .CE(fine_pi_dec_cnt),\n .D(\\fine_pi_dec_cnt[3]_i_1_n_0 ),\n .Q(\\fine_pi_dec_cnt_reg_n_0_[3] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n CARRY4 \\fine_pi_dec_cnt_reg[3]_i_3 \n (.CI(1'b0),\n .CO({\\fine_pi_dec_cnt_reg[3]_i_3_n_0 ,\\fine_pi_dec_cnt_reg[3]_i_3_n_1 ,\\fine_pi_dec_cnt_reg[3]_i_3_n_2 ,\\fine_pi_dec_cnt_reg[3]_i_3_n_3 }),\n .CYINIT(1'b0),\n .DI({\\fine_pi_dec_cnt[3]_i_4_n_0 ,\\fine_pi_dec_cnt[3]_i_5_n_0 ,\\fine_pi_dec_cnt[3]_i_6_n_0 ,\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }),\n .O({\\fine_pi_dec_cnt_reg[3]_i_3_n_4 ,\\fine_pi_dec_cnt_reg[3]_i_3_n_5 ,\\fine_pi_dec_cnt_reg[3]_i_3_n_6 ,\\fine_pi_dec_cnt_reg[3]_i_3_n_7 }),\n .S({\\fine_pi_dec_cnt[3]_i_7_n_0 ,\\fine_pi_dec_cnt[3]_i_8_n_0 ,\\fine_pi_dec_cnt[3]_i_9_n_0 ,\\fine_pi_dec_cnt[3]_i_10_n_0 }));\n FDRE \\fine_pi_dec_cnt_reg[4] \n (.C(CLK),\n .CE(fine_pi_dec_cnt),\n .D(\\fine_pi_dec_cnt_reg[4]_i_1_n_0 ),\n .Q(\\fine_pi_dec_cnt_reg_n_0_[4] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n MUXF7 \\fine_pi_dec_cnt_reg[4]_i_1 \n (.I0(\\fine_pi_dec_cnt[4]_i_2_n_0 ),\n .I1(\\fine_pi_dec_cnt[4]_i_3_n_0 ),\n .O(\\fine_pi_dec_cnt_reg[4]_i_1_n_0 ),\n .S(Q[2]));\n FDRE \\fine_pi_dec_cnt_reg[5] \n (.C(CLK),\n .CE(fine_pi_dec_cnt),\n .D(\\fine_pi_dec_cnt_reg[5]_i_2_n_0 ),\n .Q(\\fine_pi_dec_cnt_reg_n_0_[5] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n MUXF7 \\fine_pi_dec_cnt_reg[5]_i_1 \n (.I0(\\fine_pi_dec_cnt[5]_i_3_n_0 ),\n .I1(\\fine_pi_dec_cnt[5]_i_4_n_0 ),\n .O(fine_pi_dec_cnt),\n .S(Q[0]));\n MUXF7 \\fine_pi_dec_cnt_reg[5]_i_2 \n (.I0(\\fine_pi_dec_cnt[5]_i_5_n_0 ),\n .I1(\\fine_pi_dec_cnt[5]_i_6_n_0 ),\n .O(\\fine_pi_dec_cnt_reg[5]_i_2_n_0 ),\n .S(Q[2]));\n CARRY4 \\fine_pi_dec_cnt_reg[5]_i_8 \n (.CI(\\fine_pi_dec_cnt_reg[3]_i_3_n_0 ),\n .CO({\\NLW_fine_pi_dec_cnt_reg[5]_i_8_CO_UNCONNECTED [3:1],\\fine_pi_dec_cnt_reg[5]_i_8_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,\\fine_pi_dec_cnt[5]_i_9_n_0 }),\n .O({\\NLW_fine_pi_dec_cnt_reg[5]_i_8_O_UNCONNECTED [3:2],\\fine_pi_dec_cnt_reg[5]_i_8_n_6 ,\\fine_pi_dec_cnt_reg[5]_i_8_n_7 }),\n .S({1'b0,1'b0,\\fine_pi_dec_cnt[5]_i_10_n_0 ,\\fine_pi_dec_cnt[5]_i_11_n_0 }));\n FDRE \\gen_mux_div4.gen_rd_4[0].mux_rd_fall0_r2_reg[0] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(mux_rd_fall0_r1),\n .Q(mux_rd_fall0_r2),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[0].mux_rd_fall0_r3_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(mux_rd_fall0_r2),\n .Q(\\gen_mux_div4.gen_rd_4[0].mux_rd_fall0_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[0].mux_rd_fall1_r2_reg[0] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(mux_rd_fall1_r1),\n .Q(mux_rd_fall1_r2),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[0].mux_rd_fall1_r3_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(mux_rd_fall1_r2),\n .Q(\\gen_mux_div4.gen_rd_4[0].mux_rd_fall1_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[0].mux_rd_fall2_r2_reg[0] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(mux_rd_fall2_r1),\n .Q(mux_rd_fall2_r2),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[0].mux_rd_fall2_r3_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(mux_rd_fall2_r2),\n .Q(\\gen_mux_div4.gen_rd_4[0].mux_rd_fall2_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[0].mux_rd_fall3_r2_reg[0] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(mux_rd_fall3_r1),\n .Q(mux_rd_fall3_r2),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[0].mux_rd_fall3_r3_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(mux_rd_fall3_r2),\n .Q(\\gen_mux_div4.gen_rd_4[0].mux_rd_fall3_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[0].mux_rd_rise0_r2_reg[0] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(mux_rd_rise0_r1),\n .Q(mux_rd_rise0_r2),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[0].mux_rd_rise0_r3_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(mux_rd_rise0_r2),\n .Q(\\gen_mux_div4.gen_rd_4[0].mux_rd_rise0_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[0].mux_rd_rise1_r2_reg[0] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(mux_rd_rise1_r1),\n .Q(mux_rd_rise1_r2),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[0].mux_rd_rise1_r3_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(mux_rd_rise1_r2),\n .Q(\\gen_mux_div4.gen_rd_4[0].mux_rd_rise1_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[0].mux_rd_rise2_r2_reg[0] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(mux_rd_rise2_r1),\n .Q(mux_rd_rise2_r2),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[0].mux_rd_rise2_r3_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(mux_rd_rise2_r2),\n .Q(\\gen_mux_div4.gen_rd_4[0].mux_rd_rise2_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[0].mux_rd_rise3_r2_reg[0] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(mux_rd_rise3_r1),\n .Q(mux_rd_rise3_r2),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[0].mux_rd_rise3_r3_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(mux_rd_rise3_r2),\n .Q(\\gen_mux_div4.gen_rd_4[0].mux_rd_rise3_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r2_reg[1] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[1].mux_rd_fall0_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r3_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r2_reg[1] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[1].mux_rd_fall1_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r3_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r2_reg[1] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[1].mux_rd_fall2_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r3_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r2_reg[1] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[1].mux_rd_fall3_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r3_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r2_reg[1] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[1].mux_rd_rise0_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r3_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r2_reg[1] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[1].mux_rd_rise1_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r3_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r2_reg[1] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[1].mux_rd_rise2_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r3_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r2_reg[1] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[1].mux_rd_rise3_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r3_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r2_reg[2] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[2].mux_rd_fall0_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r3_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r2_reg[2] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[2].mux_rd_fall1_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r3_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r2_reg[2] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[2].mux_rd_fall2_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r3_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r2_reg[2] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[2].mux_rd_fall3_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r3_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r2_reg[2] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[2].mux_rd_rise0_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r3_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r2_reg[2] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[2].mux_rd_rise1_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r3_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r2_reg[2] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[2].mux_rd_rise2_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r3_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r2_reg[2] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[2].mux_rd_rise3_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r3_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r2_reg[3] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[3].mux_rd_fall0_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r3_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r2_reg[3] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[3].mux_rd_fall1_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r3_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r2_reg[3] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[3].mux_rd_fall2_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r3_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r2_reg[3] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[3].mux_rd_fall3_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r3_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r2_reg[3] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[3].mux_rd_rise0_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r3_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r2_reg[3] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[3].mux_rd_rise1_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r3_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r2_reg[3] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[3].mux_rd_rise2_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r3_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r2_reg[3] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[3].mux_rd_rise3_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r3_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r2_reg[4] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[4].mux_rd_fall0_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r3_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r2_reg[4] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[4].mux_rd_fall1_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r3_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r2_reg[4] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[4].mux_rd_fall2_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r3_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r2_reg[4] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[4].mux_rd_fall3_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r3_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r2_reg[4] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[4].mux_rd_rise0_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r3_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r2_reg[4] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[4].mux_rd_rise1_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r3_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r2_reg[4] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[4].mux_rd_rise2_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r3_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r2_reg[4] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[4].mux_rd_rise3_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r3_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r2_reg[5] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[5].mux_rd_fall0_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r3_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r2_reg[5] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[5].mux_rd_fall1_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r3_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r2_reg[5] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[5].mux_rd_fall2_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r3_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r2_reg[5] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[5].mux_rd_fall3_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r3_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r2_reg[5] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[5].mux_rd_rise0_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r3_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r2_reg[5] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[5].mux_rd_rise1_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r3_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r2_reg[5] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[5].mux_rd_rise2_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r3_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r2_reg[5] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[5].mux_rd_rise3_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r3_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r2_reg[6] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[6].mux_rd_fall0_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r3_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r2_reg[6] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[6].mux_rd_fall1_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r3_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r2_reg[6] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[6].mux_rd_fall2_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r3_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r2_reg[6] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[6].mux_rd_fall3_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r3_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r2_reg[6] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[6].mux_rd_rise0_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r3_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r2_reg[6] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[6].mux_rd_rise1_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r3_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r2_reg[6] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[6].mux_rd_rise2_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r3_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r2_reg[6] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[6].mux_rd_rise3_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r3_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r2_reg[7] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[7].mux_rd_fall0_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r3_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r2_reg[7] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[7].mux_rd_fall1_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r3_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r2_reg[7] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[7].mux_rd_fall2_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r3_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r2_reg[7] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[7].mux_rd_fall3_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r3_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r2_reg[7] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[7].mux_rd_rise0_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r3_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r2_reg[7] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[7].mux_rd_rise1_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r3_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r2_reg[7] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[7].mux_rd_rise2_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r3_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r2_reg[7] \n (.C(CLK),\n .CE(mux_rd_valid_r),\n .D(\\gen_mux_rd[7].mux_rd_rise3_r1_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r2_reg ),\n .R(1'b0));\n FDRE \\gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r3_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r2_reg ),\n .Q(\\gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r3_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[0].compare_data_fall0_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[6] ),\n .Q(\\gen_mux_rd[0].compare_data_fall0_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[0].compare_data_fall1_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[4] ),\n .Q(\\gen_mux_rd[0].compare_data_fall1_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[0].compare_data_fall2_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[2] ),\n .Q(\\gen_mux_rd[0].compare_data_fall2_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[0].compare_data_fall3_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[0] ),\n .Q(\\gen_mux_rd[0].compare_data_fall3_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[0].compare_data_rise0_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[7] ),\n .Q(\\gen_mux_rd[0].compare_data_rise0_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[0].compare_data_rise1_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[5] ),\n .Q(\\gen_mux_rd[0].compare_data_rise1_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[0].compare_data_rise2_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[3] ),\n .Q(\\gen_mux_rd[0].compare_data_rise2_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[0].compare_data_rise3_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[1] ),\n .Q(\\gen_mux_rd[0].compare_data_rise3_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_9 ),\n .Q(mux_rd_fall0_r1),\n .R(1'b0));\n FDRE \\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_25 ),\n .Q(mux_rd_fall1_r1),\n .R(1'b0));\n FDRE \\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_41 ),\n .Q(mux_rd_fall2_r1),\n .R(1'b0));\n FDRE \\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_57 ),\n .Q(mux_rd_fall3_r1),\n .R(1'b0));\n FDRE \\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_1 ),\n .Q(mux_rd_rise0_r1),\n .R(1'b0));\n FDRE \\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_17 ),\n .Q(mux_rd_rise1_r1),\n .R(1'b0));\n FDRE \\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_33 ),\n .Q(mux_rd_rise2_r1),\n .R(1'b0));\n FDRE \\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_49 ),\n .Q(mux_rd_rise3_r1),\n .R(1'b0));\n FDRE \\gen_mux_rd[1].compare_data_fall0_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[6]_0 ),\n .Q(\\gen_mux_rd[1].compare_data_fall0_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[1].compare_data_fall1_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[4]_0 ),\n .Q(\\gen_mux_rd[1].compare_data_fall1_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[1].compare_data_fall2_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[2]_0 ),\n .Q(\\gen_mux_rd[1].compare_data_fall2_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[1].compare_data_fall3_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[0]_0 ),\n .Q(\\gen_mux_rd[1].compare_data_fall3_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[1].compare_data_rise0_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[7]_0 ),\n .Q(\\gen_mux_rd[1].compare_data_rise0_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[1].compare_data_rise1_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[5]_0 ),\n .Q(\\gen_mux_rd[1].compare_data_rise1_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[1].compare_data_rise2_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[3]_0 ),\n .Q(\\gen_mux_rd[1].compare_data_rise2_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[1].compare_data_rise3_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[1]_0 ),\n .Q(\\gen_mux_rd[1].compare_data_rise3_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_10 ),\n .Q(\\gen_mux_rd[1].mux_rd_fall0_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_26 ),\n .Q(\\gen_mux_rd[1].mux_rd_fall1_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_42 ),\n .Q(\\gen_mux_rd[1].mux_rd_fall2_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_58 ),\n .Q(\\gen_mux_rd[1].mux_rd_fall3_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_2 ),\n .Q(\\gen_mux_rd[1].mux_rd_rise0_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_18 ),\n .Q(\\gen_mux_rd[1].mux_rd_rise1_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_34 ),\n .Q(\\gen_mux_rd[1].mux_rd_rise2_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_50 ),\n .Q(\\gen_mux_rd[1].mux_rd_rise3_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[2].compare_data_fall0_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[6]_1 ),\n .Q(\\gen_mux_rd[2].compare_data_fall0_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[2].compare_data_fall1_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[4]_1 ),\n .Q(\\gen_mux_rd[2].compare_data_fall1_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[2].compare_data_fall2_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[2]_1 ),\n .Q(\\gen_mux_rd[2].compare_data_fall2_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[2].compare_data_fall3_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[0]_1 ),\n .Q(\\gen_mux_rd[2].compare_data_fall3_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[2].compare_data_rise0_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[7]_1 ),\n .Q(\\gen_mux_rd[2].compare_data_rise0_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[2].compare_data_rise1_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[5]_1 ),\n .Q(\\gen_mux_rd[2].compare_data_rise1_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[2].compare_data_rise2_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[3]_1 ),\n .Q(\\gen_mux_rd[2].compare_data_rise2_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[2].compare_data_rise3_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[1]_1 ),\n .Q(\\gen_mux_rd[2].compare_data_rise3_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_11 ),\n .Q(\\gen_mux_rd[2].mux_rd_fall0_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_27 ),\n .Q(\\gen_mux_rd[2].mux_rd_fall1_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_43 ),\n .Q(\\gen_mux_rd[2].mux_rd_fall2_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_59 ),\n .Q(\\gen_mux_rd[2].mux_rd_fall3_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_3 ),\n .Q(\\gen_mux_rd[2].mux_rd_rise0_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_19 ),\n .Q(\\gen_mux_rd[2].mux_rd_rise1_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_35 ),\n .Q(\\gen_mux_rd[2].mux_rd_rise2_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_51 ),\n .Q(\\gen_mux_rd[2].mux_rd_rise3_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[3].compare_data_fall0_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[6]_2 ),\n .Q(\\gen_mux_rd[3].compare_data_fall0_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[3].compare_data_fall1_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[4]_2 ),\n .Q(\\gen_mux_rd[3].compare_data_fall1_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[3].compare_data_fall2_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[2]_2 ),\n .Q(\\gen_mux_rd[3].compare_data_fall2_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[3].compare_data_fall3_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[0]_2 ),\n .Q(\\gen_mux_rd[3].compare_data_fall3_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[3].compare_data_rise0_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[7]_2 ),\n .Q(\\gen_mux_rd[3].compare_data_rise0_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[3].compare_data_rise1_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[5]_2 ),\n .Q(\\gen_mux_rd[3].compare_data_rise1_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[3].compare_data_rise2_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[3]_2 ),\n .Q(\\gen_mux_rd[3].compare_data_rise2_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[3].compare_data_rise3_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[1]_2 ),\n .Q(\\gen_mux_rd[3].compare_data_rise3_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_12 ),\n .Q(\\gen_mux_rd[3].mux_rd_fall0_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_28 ),\n .Q(\\gen_mux_rd[3].mux_rd_fall1_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_44 ),\n .Q(\\gen_mux_rd[3].mux_rd_fall2_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_60 ),\n .Q(\\gen_mux_rd[3].mux_rd_fall3_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_4 ),\n .Q(\\gen_mux_rd[3].mux_rd_rise0_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_20 ),\n .Q(\\gen_mux_rd[3].mux_rd_rise1_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_36 ),\n .Q(\\gen_mux_rd[3].mux_rd_rise2_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_52 ),\n .Q(\\gen_mux_rd[3].mux_rd_rise3_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[4].compare_data_fall0_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[6]_3 ),\n .Q(\\gen_mux_rd[4].compare_data_fall0_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[4].compare_data_fall1_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[4]_3 ),\n .Q(\\gen_mux_rd[4].compare_data_fall1_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[4].compare_data_fall2_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[2]_3 ),\n .Q(\\gen_mux_rd[4].compare_data_fall2_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[4].compare_data_fall3_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[0]_3 ),\n .Q(\\gen_mux_rd[4].compare_data_fall3_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[4].compare_data_rise0_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[7]_3 ),\n .Q(\\gen_mux_rd[4].compare_data_rise0_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[4].compare_data_rise1_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[5]_3 ),\n .Q(\\gen_mux_rd[4].compare_data_rise1_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[4].compare_data_rise2_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[3]_3 ),\n .Q(\\gen_mux_rd[4].compare_data_rise2_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[4].compare_data_rise3_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[1]_3 ),\n .Q(\\gen_mux_rd[4].compare_data_rise3_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_13 ),\n .Q(\\gen_mux_rd[4].mux_rd_fall0_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_29 ),\n .Q(\\gen_mux_rd[4].mux_rd_fall1_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_45 ),\n .Q(\\gen_mux_rd[4].mux_rd_fall2_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_61 ),\n .Q(\\gen_mux_rd[4].mux_rd_fall3_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_5 ),\n .Q(\\gen_mux_rd[4].mux_rd_rise0_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_21 ),\n .Q(\\gen_mux_rd[4].mux_rd_rise1_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_37 ),\n .Q(\\gen_mux_rd[4].mux_rd_rise2_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_53 ),\n .Q(\\gen_mux_rd[4].mux_rd_rise3_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[5].compare_data_fall0_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[6]_4 ),\n .Q(\\gen_mux_rd[5].compare_data_fall0_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[5].compare_data_fall1_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[4]_4 ),\n .Q(\\gen_mux_rd[5].compare_data_fall1_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[5].compare_data_fall2_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[2]_4 ),\n .Q(\\gen_mux_rd[5].compare_data_fall2_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[5].compare_data_fall3_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[0]_4 ),\n .Q(\\gen_mux_rd[5].compare_data_fall3_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[5].compare_data_rise0_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[7]_4 ),\n .Q(\\gen_mux_rd[5].compare_data_rise0_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[5].compare_data_rise1_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[5]_4 ),\n .Q(\\gen_mux_rd[5].compare_data_rise1_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[5].compare_data_rise2_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[3]_4 ),\n .Q(\\gen_mux_rd[5].compare_data_rise2_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[5].compare_data_rise3_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[1]_4 ),\n .Q(\\gen_mux_rd[5].compare_data_rise3_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_14 ),\n .Q(\\gen_mux_rd[5].mux_rd_fall0_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_30 ),\n .Q(\\gen_mux_rd[5].mux_rd_fall1_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_46 ),\n .Q(\\gen_mux_rd[5].mux_rd_fall2_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_62 ),\n .Q(\\gen_mux_rd[5].mux_rd_fall3_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_6 ),\n .Q(\\gen_mux_rd[5].mux_rd_rise0_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_22 ),\n .Q(\\gen_mux_rd[5].mux_rd_rise1_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_38 ),\n .Q(\\gen_mux_rd[5].mux_rd_rise2_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_54 ),\n .Q(\\gen_mux_rd[5].mux_rd_rise3_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[6].compare_data_fall0_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[6]_5 ),\n .Q(\\gen_mux_rd[6].compare_data_fall0_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[6].compare_data_fall1_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[4]_5 ),\n .Q(\\gen_mux_rd[6].compare_data_fall1_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[6].compare_data_fall2_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[2]_5 ),\n .Q(\\gen_mux_rd[6].compare_data_fall2_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[6].compare_data_fall3_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[0]_5 ),\n .Q(\\gen_mux_rd[6].compare_data_fall3_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[6].compare_data_rise0_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[7]_5 ),\n .Q(\\gen_mux_rd[6].compare_data_rise0_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[6].compare_data_rise1_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[5]_5 ),\n .Q(\\gen_mux_rd[6].compare_data_rise1_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[6].compare_data_rise2_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[3]_5 ),\n .Q(\\gen_mux_rd[6].compare_data_rise2_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[6].compare_data_rise3_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[1]_5 ),\n .Q(\\gen_mux_rd[6].compare_data_rise3_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_15 ),\n .Q(\\gen_mux_rd[6].mux_rd_fall0_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_31 ),\n .Q(\\gen_mux_rd[6].mux_rd_fall1_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_47 ),\n .Q(\\gen_mux_rd[6].mux_rd_fall2_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_63 ),\n .Q(\\gen_mux_rd[6].mux_rd_fall3_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_7 ),\n .Q(\\gen_mux_rd[6].mux_rd_rise0_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_23 ),\n .Q(\\gen_mux_rd[6].mux_rd_rise1_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_39 ),\n .Q(\\gen_mux_rd[6].mux_rd_rise2_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_55 ),\n .Q(\\gen_mux_rd[6].mux_rd_rise3_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[7].compare_data_fall0_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[6]_6 ),\n .Q(\\gen_mux_rd[7].compare_data_fall0_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[7].compare_data_fall1_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[4]_6 ),\n .Q(\\gen_mux_rd[7].compare_data_fall1_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[7].compare_data_fall2_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[2]_6 ),\n .Q(\\gen_mux_rd[7].compare_data_fall2_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[7].compare_data_fall3_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[0]_6 ),\n .Q(\\gen_mux_rd[7].compare_data_fall3_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[7].compare_data_rise0_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[7]_6 ),\n .Q(\\gen_mux_rd[7].compare_data_rise0_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[7].compare_data_rise1_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[5]_6 ),\n .Q(\\gen_mux_rd[7].compare_data_rise1_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[7].compare_data_rise2_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[3]_6 ),\n .Q(\\gen_mux_rd[7].compare_data_rise2_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[7].compare_data_rise3_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o_reg[1]_6 ),\n .Q(\\gen_mux_rd[7].compare_data_rise3_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_16 ),\n .Q(\\gen_mux_rd[7].mux_rd_fall0_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_32 ),\n .Q(\\gen_mux_rd[7].mux_rd_fall1_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_48 ),\n .Q(\\gen_mux_rd[7].mux_rd_fall2_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_64 ),\n .Q(\\gen_mux_rd[7].mux_rd_fall3_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_8 ),\n .Q(\\gen_mux_rd[7].mux_rd_rise0_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_24 ),\n .Q(\\gen_mux_rd[7].mux_rd_rise1_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_40 ),\n .Q(\\gen_mux_rd[7].mux_rd_rise2_r1_reg ),\n .R(1'b0));\n FDRE \\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\A[1]_56 ),\n .Q(\\gen_mux_rd[7].mux_rd_rise3_r1_reg ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000001D000C000)) \n \\genblk7[0].compare_err_pb_latch_r[0]_i_1 \n (.I0(cnt_wait_state),\n .I1(Q[0]),\n .I2(Q[2]),\n .I3(Q[3]),\n .I4(Q[1]),\n .I5(Q[4]),\n .O(\\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\genblk7[0].compare_err_pb_latch_r[0]_i_2 \n (.I0(compare_err_pb[0]),\n .I1(\\genblk7[0].compare_err_pb_latch_r_reg_n_0_[0] ),\n .O(\\genblk7[0].compare_err_pb_latch_r[0]_i_2_n_0 ));\n FDRE \\genblk7[0].compare_err_pb_latch_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk7[0].compare_err_pb_latch_r[0]_i_2_n_0 ),\n .Q(\\genblk7[0].compare_err_pb_latch_r_reg_n_0_[0] ),\n .R(\\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair60\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\genblk7[1].compare_err_pb_latch_r[1]_i_1 \n (.I0(compare_err_pb[1]),\n .I1(\\genblk7[1].compare_err_pb_latch_r_reg_n_0_[1] ),\n .O(\\genblk7[1].compare_err_pb_latch_r[1]_i_1_n_0 ));\n FDRE \\genblk7[1].compare_err_pb_latch_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk7[1].compare_err_pb_latch_r[1]_i_1_n_0 ),\n .Q(\\genblk7[1].compare_err_pb_latch_r_reg_n_0_[1] ),\n .R(\\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\genblk7[2].compare_err_pb_latch_r[2]_i_1 \n (.I0(compare_err_pb[2]),\n .I1(\\genblk7[2].compare_err_pb_latch_r_reg_n_0_[2] ),\n .O(\\genblk7[2].compare_err_pb_latch_r[2]_i_1_n_0 ));\n FDRE \\genblk7[2].compare_err_pb_latch_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk7[2].compare_err_pb_latch_r[2]_i_1_n_0 ),\n .Q(\\genblk7[2].compare_err_pb_latch_r_reg_n_0_[2] ),\n .R(\\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\genblk7[3].compare_err_pb_latch_r[3]_i_1 \n (.I0(compare_err_pb[3]),\n .I1(\\genblk7[3].compare_err_pb_latch_r_reg_n_0_[3] ),\n .O(\\genblk7[3].compare_err_pb_latch_r[3]_i_1_n_0 ));\n FDRE \\genblk7[3].compare_err_pb_latch_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk7[3].compare_err_pb_latch_r[3]_i_1_n_0 ),\n .Q(\\genblk7[3].compare_err_pb_latch_r_reg_n_0_[3] ),\n .R(\\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\genblk7[4].compare_err_pb_latch_r[4]_i_1 \n (.I0(compare_err_pb[4]),\n .I1(\\genblk7[4].compare_err_pb_latch_r_reg_n_0_[4] ),\n .O(\\genblk7[4].compare_err_pb_latch_r[4]_i_1_n_0 ));\n FDRE \\genblk7[4].compare_err_pb_latch_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk7[4].compare_err_pb_latch_r[4]_i_1_n_0 ),\n .Q(\\genblk7[4].compare_err_pb_latch_r_reg_n_0_[4] ),\n .R(\\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\genblk7[5].compare_err_pb_latch_r[5]_i_1 \n (.I0(compare_err_pb[5]),\n .I1(\\genblk7[5].compare_err_pb_latch_r_reg_n_0_[5] ),\n .O(\\genblk7[5].compare_err_pb_latch_r[5]_i_1_n_0 ));\n FDRE \\genblk7[5].compare_err_pb_latch_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk7[5].compare_err_pb_latch_r[5]_i_1_n_0 ),\n .Q(\\genblk7[5].compare_err_pb_latch_r_reg_n_0_[5] ),\n .R(\\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair61\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\genblk7[6].compare_err_pb_latch_r[6]_i_1 \n (.I0(compare_err_pb[6]),\n .I1(\\genblk7[6].compare_err_pb_latch_r_reg_n_0_[6] ),\n .O(\\genblk7[6].compare_err_pb_latch_r[6]_i_1_n_0 ));\n FDRE \\genblk7[6].compare_err_pb_latch_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk7[6].compare_err_pb_latch_r[6]_i_1_n_0 ),\n .Q(\\genblk7[6].compare_err_pb_latch_r_reg_n_0_[6] ),\n .R(\\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\genblk7[7].compare_err_pb_latch_r[7]_i_1 \n (.I0(compare_err_pb[7]),\n .I1(\\genblk7[7].compare_err_pb_latch_r_reg_n_0_[7] ),\n .O(\\genblk7[7].compare_err_pb_latch_r[7]_i_1_n_0 ));\n FDRE \\genblk7[7].compare_err_pb_latch_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk7[7].compare_err_pb_latch_r[7]_i_1_n_0 ),\n .Q(\\genblk7[7].compare_err_pb_latch_r_reg_n_0_[7] ),\n .R(\\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 ));\n FDRE \\genblk8[0].left_edge_found_pb_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[0].left_edge_found_pb_reg[0]_0 ),\n .Q(\\genblk8[0].left_loss_pb_reg[0]_0 ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair44\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\genblk8[0].left_edge_pb[0]_i_1 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .O(\\genblk8[0].left_edge_pb[0]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h6)) \n \\genblk8[0].left_edge_pb[1]_i_1 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .O(\\genblk8[0].left_edge_pb[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair20\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\genblk8[0].left_edge_pb[2]_i_1 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I1(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .O(\\genblk8[0].left_edge_pb[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair65\" *) \n LUT4 #(\n .INIT(16'h9555)) \n \\genblk8[0].left_edge_pb[3]_i_1 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .O(\\genblk8[0].left_edge_pb[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair44\" *) \n LUT5 #(\n .INIT(32'hAAAA9555)) \n \\genblk8[0].left_edge_pb[4]_i_1 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),\n .O(\\genblk8[0].left_edge_pb[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF00000004)) \n \\genblk8[0].left_edge_pb[5]_i_1 \n (.I0(Q[2]),\n .I1(Q[0]),\n .I2(Q[4]),\n .I3(Q[1]),\n .I4(Q[3]),\n .I5(rstdiv0_sync_r1_reg_rep__23),\n .O(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\genblk8[0].left_edge_pb[5]_i_2 \n (.I0(p_154_out),\n .I1(\\genblk8[0].left_loss_pb_reg[0]_1 ),\n .O(left_edge_pb));\n LUT6 #(\n .INIT(64'hAAAAAAAAA9999999)) \n \\genblk8[0].left_edge_pb[5]_i_3 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .O(\\genblk8[0].left_edge_pb[5]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\genblk8[0].left_edge_pb[5]_i_4 \n (.I0(match_flag_pb[7]),\n .I1(\\genblk8[0].left_edge_pb[5]_i_5_n_0 ),\n .I2(\\genblk7[0].compare_err_pb_latch_r_reg_n_0_[0] ),\n .I3(match_flag_pb[6]),\n .I4(match_flag_pb[4]),\n .I5(match_flag_pb[5]),\n .O(\\genblk8[0].left_loss_pb_reg[0]_1 ));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\genblk8[0].left_edge_pb[5]_i_5 \n (.I0(match_flag_pb[2]),\n .I1(match_flag_pb[3]),\n .I2(match_flag_pb[0]),\n .I3(match_flag_pb[1]),\n .O(\\genblk8[0].left_edge_pb[5]_i_5_n_0 ));\n FDRE \\genblk8[0].left_edge_pb_reg[0] \n (.C(CLK),\n .CE(left_edge_pb),\n .D(\\genblk8[0].left_edge_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[0].left_edge_pb_reg_n_0_[0] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[0].left_edge_pb_reg[1] \n (.C(CLK),\n .CE(left_edge_pb),\n .D(\\genblk8[0].left_edge_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[0].left_edge_pb_reg_n_0_[1] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[0].left_edge_pb_reg[2] \n (.C(CLK),\n .CE(left_edge_pb),\n .D(\\genblk8[0].left_edge_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[0].left_edge_pb_reg_n_0_[2] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[0].left_edge_pb_reg[3] \n (.C(CLK),\n .CE(left_edge_pb),\n .D(\\genblk8[0].left_edge_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[0].left_edge_pb_reg_n_0_[3] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[0].left_edge_pb_reg[4] \n (.C(CLK),\n .CE(left_edge_pb),\n .D(\\genblk8[0].left_edge_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[0].left_edge_pb_reg_n_0_[4] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[0].left_edge_pb_reg[5] \n (.C(CLK),\n .CE(left_edge_pb),\n .D(\\genblk8[0].left_edge_pb[5]_i_3_n_0 ),\n .Q(\\genblk8[0].left_edge_pb_reg_n_0_[5] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair51\" *) \n LUT4 #(\n .INIT(16'h0080)) \n \\genblk8[0].left_edge_updated[0]_i_2 \n (.I0(Q[0]),\n .I1(Q[2]),\n .I2(Q[3]),\n .I3(Q[4]),\n .O(\\genblk8[7].left_edge_updated_reg[7]_0 ));\n FDRE \\genblk8[0].left_edge_updated_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[0].left_edge_updated_reg[0]_0 ),\n .Q(D[0]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair80\" *) \n LUT3 #(\n .INIT(8'h40)) \n \\genblk8[0].left_loss_pb[0]_i_1 \n (.I0(\\genblk8[0].left_loss_pb_reg[5]_i_4_n_0 ),\n .I1(p_154_out),\n .I2(\\genblk8[0].left_loss_pb_reg[3]_i_2_n_7 ),\n .O(\\genblk8[0].left_loss_pb[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair81\" *) \n LUT3 #(\n .INIT(8'h40)) \n \\genblk8[0].left_loss_pb[1]_i_1 \n (.I0(\\genblk8[0].left_loss_pb_reg[5]_i_4_n_0 ),\n .I1(p_154_out),\n .I2(\\genblk8[0].left_loss_pb_reg[3]_i_2_n_6 ),\n .O(\\genblk8[0].left_loss_pb[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair81\" *) \n LUT3 #(\n .INIT(8'h40)) \n \\genblk8[0].left_loss_pb[2]_i_1 \n (.I0(\\genblk8[0].left_loss_pb_reg[5]_i_4_n_0 ),\n .I1(p_154_out),\n .I2(\\genblk8[0].left_loss_pb_reg[3]_i_2_n_5 ),\n .O(\\genblk8[0].left_loss_pb[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair80\" *) \n LUT3 #(\n .INIT(8'h40)) \n \\genblk8[0].left_loss_pb[3]_i_1 \n (.I0(\\genblk8[0].left_loss_pb_reg[5]_i_4_n_0 ),\n .I1(p_154_out),\n .I2(\\genblk8[0].left_loss_pb_reg[3]_i_2_n_4 ),\n .O(\\genblk8[0].left_loss_pb[3]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h6)) \n \\genblk8[0].left_loss_pb[3]_i_3 \n (.I0(left_edge_ref[3]),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),\n .O(\\genblk8[0].left_loss_pb[3]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\genblk8[0].left_loss_pb[3]_i_4 \n (.I0(left_edge_ref[1]),\n .O(\\genblk8[0].left_loss_pb[3]_i_4_n_0 ));\n LUT4 #(\n .INIT(16'h6966)) \n \\genblk8[0].left_loss_pb[3]_i_5 \n (.I0(left_edge_ref[3]),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),\n .I2(left_edge_ref[2]),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .O(\\genblk8[0].left_loss_pb[3]_i_5_n_0 ));\n LUT3 #(\n .INIT(8'h96)) \n \\genblk8[0].left_loss_pb[3]_i_6 \n (.I0(left_edge_ref[1]),\n .I1(left_edge_ref[2]),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .O(\\genblk8[0].left_loss_pb[3]_i_6_n_0 ));\n LUT2 #(\n .INIT(4'h6)) \n \\genblk8[0].left_loss_pb[3]_i_7 \n (.I0(left_edge_ref[1]),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .O(\\genblk8[0].left_loss_pb[3]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[0].left_loss_pb[3]_i_8 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I1(left_edge_ref[0]),\n .O(\\genblk8[0].left_loss_pb[3]_i_8_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair78\" *) \n LUT3 #(\n .INIT(8'h40)) \n \\genblk8[0].left_loss_pb[4]_i_1 \n (.I0(\\genblk8[0].left_loss_pb_reg[5]_i_4_n_0 ),\n .I1(p_154_out),\n .I2(\\genblk8[0].left_loss_pb_reg[5]_i_5_n_7 ),\n .O(\\genblk8[0].left_loss_pb[4]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAEFEAEAE)) \n \\genblk8[0].left_loss_pb[5]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(right_gain_pb),\n .I2(p_154_out),\n .I3(\\genblk8[0].left_loss_pb_reg[0]_0 ),\n .I4(\\genblk8[0].left_loss_pb_reg[0]_1 ),\n .O(\\genblk8[0].left_loss_pb[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFEAAA)) \n \\genblk8[0].left_loss_pb[5]_i_10 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'hB)) \n \\genblk8[0].left_loss_pb[5]_i_11 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),\n .I1(left_edge_ref[3]),\n .O(\\genblk8[0].left_loss_pb[5]_i_11_n_0 ));\n LUT4 #(\n .INIT(16'hD22D)) \n \\genblk8[0].left_loss_pb[5]_i_12 \n (.I0(left_edge_ref[4]),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I2(left_edge_ref[5]),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_12_n_0 ));\n LUT4 #(\n .INIT(16'hD22D)) \n \\genblk8[0].left_loss_pb[5]_i_13 \n (.I0(left_edge_ref[3]),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),\n .I2(left_edge_ref[4]),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_13_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFEAAA)) \n \\genblk8[0].left_loss_pb[5]_i_15 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_15_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFEAAA)) \n \\genblk8[0].left_loss_pb[5]_i_16 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFEAAA)) \n \\genblk8[0].left_loss_pb[5]_i_17 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFEAAA)) \n \\genblk8[0].left_loss_pb[5]_i_18 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_18_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair78\" *) \n LUT3 #(\n .INIT(8'h40)) \n \\genblk8[0].left_loss_pb[5]_i_2 \n (.I0(\\genblk8[0].left_loss_pb_reg[5]_i_4_n_0 ),\n .I1(p_154_out),\n .I2(\\genblk8[0].left_loss_pb_reg[5]_i_5_n_6 ),\n .O(\\genblk8[0].left_loss_pb[5]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFEAAA)) \n \\genblk8[0].left_loss_pb[5]_i_20 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFEAAA)) \n \\genblk8[0].left_loss_pb[5]_i_21 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_21_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFEAAA)) \n \\genblk8[0].left_loss_pb[5]_i_22 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_22_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFEAAA)) \n \\genblk8[0].left_loss_pb[5]_i_23 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_23_n_0 ));\n LUT6 #(\n .INIT(64'h0808088CCECECEE0)) \n \\genblk8[0].left_loss_pb[5]_i_24 \n (.I0(left_edge_ref[4]),\n .I1(left_edge_ref[5]),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I3(\\genblk8[0].left_loss_pb[5]_i_31_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_24_n_0 ));\n LUT6 #(\n .INIT(64'h8CCCCEEEE0000888)) \n \\genblk8[0].left_loss_pb[5]_i_25 \n (.I0(left_edge_ref[2]),\n .I1(left_edge_ref[3]),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[0].left_loss_pb[5]_i_25_n_0 ));\n LUT4 #(\n .INIT(16'hCB80)) \n \\genblk8[0].left_loss_pb[5]_i_26 \n (.I0(left_edge_ref[0]),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I3(left_edge_ref[1]),\n .O(\\genblk8[0].left_loss_pb[5]_i_26_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFEAAA)) \n \\genblk8[0].left_loss_pb[5]_i_27 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_27_n_0 ));\n LUT6 #(\n .INIT(64'h8484844221212118)) \n \\genblk8[0].left_loss_pb[5]_i_28 \n (.I0(left_edge_ref[4]),\n .I1(left_edge_ref[5]),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I3(\\genblk8[0].left_loss_pb[5]_i_31_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_28_n_0 ));\n LUT6 #(\n .INIT(64'h4222211118888444)) \n \\genblk8[0].left_loss_pb[5]_i_29 \n (.I0(left_edge_ref[2]),\n .I1(left_edge_ref[3]),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[0].left_loss_pb[5]_i_29_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair18\" *) \n LUT5 #(\n .INIT(32'h00400000)) \n \\genblk8[0].left_loss_pb[5]_i_3 \n (.I0(Q[4]),\n .I1(Q[2]),\n .I2(Q[0]),\n .I3(Q[1]),\n .I4(Q[3]),\n .O(right_gain_pb));\n LUT4 #(\n .INIT(16'h1842)) \n \\genblk8[0].left_loss_pb[5]_i_30 \n (.I0(left_edge_ref[0]),\n .I1(left_edge_ref[1]),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_30_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair65\" *) \n LUT3 #(\n .INIT(8'h80)) \n \\genblk8[0].left_loss_pb[5]_i_31 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_31_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFEAAA)) \n \\genblk8[0].left_loss_pb[5]_i_7 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFEAAA)) \n \\genblk8[0].left_loss_pb[5]_i_8 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFEAAA)) \n \\genblk8[0].left_loss_pb[5]_i_9 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].left_loss_pb[5]_i_9_n_0 ));\n FDRE \\genblk8[0].left_loss_pb_reg[0] \n (.C(CLK),\n .CE(\\genblk8[0].left_loss_pb[5]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[0].left_loss_pb_reg_n_0_[0] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[0].left_loss_pb_reg[1] \n (.C(CLK),\n .CE(\\genblk8[0].left_loss_pb[5]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[0].left_loss_pb_reg_n_0_[1] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[0].left_loss_pb_reg[2] \n (.C(CLK),\n .CE(\\genblk8[0].left_loss_pb[5]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[0].left_loss_pb_reg__0 [2]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[0].left_loss_pb_reg[3] \n (.C(CLK),\n .CE(\\genblk8[0].left_loss_pb[5]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[0].left_loss_pb_reg__0 [3]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n CARRY4 \\genblk8[0].left_loss_pb_reg[3]_i_2 \n (.CI(1'b0),\n .CO({\\genblk8[0].left_loss_pb_reg[3]_i_2_n_0 ,\\genblk8[0].left_loss_pb_reg[3]_i_2_n_1 ,\\genblk8[0].left_loss_pb_reg[3]_i_2_n_2 ,\\genblk8[0].left_loss_pb_reg[3]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({\\genblk8[0].left_loss_pb[3]_i_3_n_0 ,\\genblk8[0].left_loss_pb[3]_i_4_n_0 ,left_edge_ref[1],\\prbs_dqs_tap_cnt_r_reg_n_0_[0] }),\n .O({\\genblk8[0].left_loss_pb_reg[3]_i_2_n_4 ,\\genblk8[0].left_loss_pb_reg[3]_i_2_n_5 ,\\genblk8[0].left_loss_pb_reg[3]_i_2_n_6 ,\\genblk8[0].left_loss_pb_reg[3]_i_2_n_7 }),\n .S({\\genblk8[0].left_loss_pb[3]_i_5_n_0 ,\\genblk8[0].left_loss_pb[3]_i_6_n_0 ,\\genblk8[0].left_loss_pb[3]_i_7_n_0 ,\\genblk8[0].left_loss_pb[3]_i_8_n_0 }));\n FDRE \\genblk8[0].left_loss_pb_reg[4] \n (.C(CLK),\n .CE(\\genblk8[0].left_loss_pb[5]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[0].left_loss_pb_reg__0 [4]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[0].left_loss_pb_reg[5] \n (.C(CLK),\n .CE(\\genblk8[0].left_loss_pb[5]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[5]_i_2_n_0 ),\n .Q(\\genblk8[0].left_loss_pb_reg__0 [5]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n CARRY4 \\genblk8[0].left_loss_pb_reg[5]_i_14 \n (.CI(\\genblk8[0].left_loss_pb_reg[5]_i_19_n_0 ),\n .CO({\\genblk8[0].left_loss_pb_reg[5]_i_14_n_0 ,\\genblk8[0].left_loss_pb_reg[5]_i_14_n_1 ,\\genblk8[0].left_loss_pb_reg[5]_i_14_n_2 ,\\genblk8[0].left_loss_pb_reg[5]_i_14_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[0].left_loss_pb_reg[5]_i_14_O_UNCONNECTED [3:0]),\n .S({\\genblk8[0].left_loss_pb[5]_i_20_n_0 ,\\genblk8[0].left_loss_pb[5]_i_21_n_0 ,\\genblk8[0].left_loss_pb[5]_i_22_n_0 ,\\genblk8[0].left_loss_pb[5]_i_23_n_0 }));\n CARRY4 \\genblk8[0].left_loss_pb_reg[5]_i_19 \n (.CI(1'b0),\n .CO({\\genblk8[0].left_loss_pb_reg[5]_i_19_n_0 ,\\genblk8[0].left_loss_pb_reg[5]_i_19_n_1 ,\\genblk8[0].left_loss_pb_reg[5]_i_19_n_2 ,\\genblk8[0].left_loss_pb_reg[5]_i_19_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,\\genblk8[0].left_loss_pb[5]_i_24_n_0 ,\\genblk8[0].left_loss_pb[5]_i_25_n_0 ,\\genblk8[0].left_loss_pb[5]_i_26_n_0 }),\n .O(\\NLW_genblk8[0].left_loss_pb_reg[5]_i_19_O_UNCONNECTED [3:0]),\n .S({\\genblk8[0].left_loss_pb[5]_i_27_n_0 ,\\genblk8[0].left_loss_pb[5]_i_28_n_0 ,\\genblk8[0].left_loss_pb[5]_i_29_n_0 ,\\genblk8[0].left_loss_pb[5]_i_30_n_0 }));\n CARRY4 \\genblk8[0].left_loss_pb_reg[5]_i_4 \n (.CI(\\genblk8[0].left_loss_pb_reg[5]_i_6_n_0 ),\n .CO({\\genblk8[0].left_loss_pb_reg[5]_i_4_n_0 ,\\genblk8[0].left_loss_pb_reg[5]_i_4_n_1 ,\\genblk8[0].left_loss_pb_reg[5]_i_4_n_2 ,\\genblk8[0].left_loss_pb_reg[5]_i_4_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[0].left_loss_pb_reg[5]_i_4_O_UNCONNECTED [3:0]),\n .S({\\genblk8[0].left_loss_pb[5]_i_7_n_0 ,\\genblk8[0].left_loss_pb[5]_i_8_n_0 ,\\genblk8[0].left_loss_pb[5]_i_9_n_0 ,\\genblk8[0].left_loss_pb[5]_i_10_n_0 }));\n CARRY4 \\genblk8[0].left_loss_pb_reg[5]_i_5 \n (.CI(\\genblk8[0].left_loss_pb_reg[3]_i_2_n_0 ),\n .CO({\\NLW_genblk8[0].left_loss_pb_reg[5]_i_5_CO_UNCONNECTED [3:1],\\genblk8[0].left_loss_pb_reg[5]_i_5_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,\\genblk8[0].left_loss_pb[5]_i_11_n_0 }),\n .O({\\NLW_genblk8[0].left_loss_pb_reg[5]_i_5_O_UNCONNECTED [3:2],\\genblk8[0].left_loss_pb_reg[5]_i_5_n_6 ,\\genblk8[0].left_loss_pb_reg[5]_i_5_n_7 }),\n .S({1'b0,1'b0,\\genblk8[0].left_loss_pb[5]_i_12_n_0 ,\\genblk8[0].left_loss_pb[5]_i_13_n_0 }));\n CARRY4 \\genblk8[0].left_loss_pb_reg[5]_i_6 \n (.CI(\\genblk8[0].left_loss_pb_reg[5]_i_14_n_0 ),\n .CO({\\genblk8[0].left_loss_pb_reg[5]_i_6_n_0 ,\\genblk8[0].left_loss_pb_reg[5]_i_6_n_1 ,\\genblk8[0].left_loss_pb_reg[5]_i_6_n_2 ,\\genblk8[0].left_loss_pb_reg[5]_i_6_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[0].left_loss_pb_reg[5]_i_6_O_UNCONNECTED [3:0]),\n .S({\\genblk8[0].left_loss_pb[5]_i_15_n_0 ,\\genblk8[0].left_loss_pb[5]_i_16_n_0 ,\\genblk8[0].left_loss_pb[5]_i_17_n_0 ,\\genblk8[0].left_loss_pb[5]_i_18_n_0 }));\n LUT3 #(\n .INIT(8'hBA)) \n \\genblk8[0].match_flag_pb[7]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(p_154_out),\n .I2(right_gain_pb),\n .O(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0002000000000000)) \n \\genblk8[0].match_flag_pb[7]_i_2 \n (.I0(num_samples_done_r),\n .I1(Q[3]),\n .I2(Q[2]),\n .I3(Q[1]),\n .I4(Q[4]),\n .I5(Q[0]),\n .O(p_154_out));\n FDSE \\genblk8[0].match_flag_pb_reg[0] \n (.C(CLK),\n .CE(p_154_out),\n .D(\\genblk7[0].compare_err_pb_latch_r_reg_n_0_[0] ),\n .Q(match_flag_pb[0]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[0].match_flag_pb_reg[1] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[0]),\n .Q(match_flag_pb[1]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[0].match_flag_pb_reg[2] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[1]),\n .Q(match_flag_pb[2]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[0].match_flag_pb_reg[3] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[2]),\n .Q(match_flag_pb[3]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[0].match_flag_pb_reg[4] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[3]),\n .Q(match_flag_pb[4]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[0].match_flag_pb_reg[5] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[4]),\n .Q(match_flag_pb[5]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[0].match_flag_pb_reg[6] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[5]),\n .Q(match_flag_pb[6]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[0].match_flag_pb_reg[7] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[6]),\n .Q(match_flag_pb[7]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDRE \\genblk8[0].right_edge_found_pb_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[0].right_edge_found_pb_reg[0]_0 ),\n .Q(\\genblk8[0].right_edge_pb_reg[0]_0 ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair77\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[0].right_edge_pb[1]_i_1 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I1(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .O(\\genblk8[0].right_edge_pb[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair77\" *) \n LUT3 #(\n .INIT(8'hA9)) \n \\genblk8[0].right_edge_pb[2]_i_1 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .O(\\genblk8[0].right_edge_pb[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair63\" *) \n LUT4 #(\n .INIT(16'hAAA9)) \n \\genblk8[0].right_edge_pb[3]_i_1 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I1(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .O(\\genblk8[0].right_edge_pb[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair45\" *) \n LUT5 #(\n .INIT(32'hAAAAAAA9)) \n \\genblk8[0].right_edge_pb[4]_i_1 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .O(\\genblk8[0].right_edge_pb[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAABAAAAAAAAA)) \n \\genblk8[0].right_edge_pb[5]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(\\genblk8[0].left_loss_pb_reg[0]_1 ),\n .I2(p_154_out),\n .I3(\\genblk8[0].right_edge_pb_reg[0]_1 ),\n .I4(\\genblk8[0].right_edge_pb_reg[0]_0 ),\n .I5(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .O(\\genblk8[0].right_edge_pb[5]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h08)) \n \\genblk8[0].right_edge_pb[5]_i_2 \n (.I0(p_154_out),\n .I1(\\genblk8[0].right_edge_pb_reg[0]_1 ),\n .I2(\\genblk8[0].left_loss_pb_reg[0]_1 ),\n .O(\\genblk8[0].right_edge_pb[5]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAAAAA9)) \n \\genblk8[0].right_edge_pb[5]_i_3 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .O(\\genblk8[0].right_edge_pb[5]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\genblk8[0].right_edge_pb[5]_i_4 \n (.I0(\\genblk7[0].compare_err_pb_latch_r_reg_n_0_[0] ),\n .I1(\\genblk8[0].left_edge_pb[5]_i_5_n_0 ),\n .I2(match_flag_pb[7]),\n .I3(match_flag_pb[6]),\n .I4(match_flag_pb[4]),\n .I5(match_flag_pb[5]),\n .O(\\genblk8[0].right_edge_pb_reg[0]_1 ));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\genblk8[0].right_edge_pb[5]_i_5 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .O(\\genblk8[7].right_edge_pb_reg[42]_1 ));\n FDSE \\genblk8[0].right_edge_pb_reg[0] \n (.C(CLK),\n .CE(\\genblk8[0].right_edge_pb[5]_i_2_n_0 ),\n .D(\\genblk8[0].left_edge_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[0].right_edge_pb_reg_n_0_[0] ),\n .S(\\genblk8[0].right_edge_pb[5]_i_1_n_0 ));\n FDSE \\genblk8[0].right_edge_pb_reg[1] \n (.C(CLK),\n .CE(\\genblk8[0].right_edge_pb[5]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[0].right_edge_pb_reg_n_0_[1] ),\n .S(\\genblk8[0].right_edge_pb[5]_i_1_n_0 ));\n FDSE \\genblk8[0].right_edge_pb_reg[2] \n (.C(CLK),\n .CE(\\genblk8[0].right_edge_pb[5]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[0].right_edge_pb_reg_n_0_[2] ),\n .S(\\genblk8[0].right_edge_pb[5]_i_1_n_0 ));\n FDSE \\genblk8[0].right_edge_pb_reg[3] \n (.C(CLK),\n .CE(\\genblk8[0].right_edge_pb[5]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[0].right_edge_pb_reg_n_0_[3] ),\n .S(\\genblk8[0].right_edge_pb[5]_i_1_n_0 ));\n FDSE \\genblk8[0].right_edge_pb_reg[4] \n (.C(CLK),\n .CE(\\genblk8[0].right_edge_pb[5]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[0].right_edge_pb_reg_n_0_[4] ),\n .S(\\genblk8[0].right_edge_pb[5]_i_1_n_0 ));\n FDSE \\genblk8[0].right_edge_pb_reg[5] \n (.C(CLK),\n .CE(\\genblk8[0].right_edge_pb[5]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[5]_i_3_n_0 ),\n .Q(\\genblk8[0].right_edge_pb_reg_n_0_[5] ),\n .S(\\genblk8[0].right_edge_pb[5]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[0].right_gain_pb[0]_i_1 \n (.I0(\\genblk8[0].right_edge_pb_reg[0]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[0].right_gain_pb_reg[3]_i_2_n_7 ),\n .I3(\\genblk8[0].right_gain_pb_reg[3]_i_3_n_7 ),\n .O(\\genblk8[0].right_gain_pb[0]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[0].right_gain_pb[1]_i_1 \n (.I0(\\genblk8[0].right_edge_pb_reg[0]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[0].right_gain_pb_reg[3]_i_2_n_6 ),\n .I3(\\genblk8[0].right_gain_pb_reg[3]_i_3_n_6 ),\n .O(\\genblk8[0].right_gain_pb[1]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[0].right_gain_pb[2]_i_1 \n (.I0(\\genblk8[0].right_edge_pb_reg[0]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[0].right_gain_pb_reg[3]_i_2_n_5 ),\n .I3(\\genblk8[0].right_gain_pb_reg[3]_i_3_n_5 ),\n .O(\\genblk8[0].right_gain_pb[2]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[0].right_gain_pb[3]_i_1 \n (.I0(\\genblk8[0].right_edge_pb_reg[0]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[0].right_gain_pb_reg[3]_i_2_n_4 ),\n .I3(\\genblk8[0].right_gain_pb_reg[3]_i_3_n_4 ),\n .O(\\genblk8[0].right_gain_pb[3]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[0].right_gain_pb[3]_i_10 \n (.I0(right_edge_ref[1]),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[1] ),\n .O(\\genblk8[0].right_gain_pb[3]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[0].right_gain_pb[3]_i_11 \n (.I0(right_edge_ref[0]),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[0] ),\n .O(\\genblk8[0].right_gain_pb[3]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[0].right_gain_pb[3]_i_4 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[3] ),\n .O(\\genblk8[0].right_gain_pb[3]_i_4_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[0].right_gain_pb[3]_i_5 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[2] ),\n .O(\\genblk8[0].right_gain_pb[3]_i_5_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[0].right_gain_pb[3]_i_6 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[1] ),\n .O(\\genblk8[0].right_gain_pb[3]_i_6_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[0].right_gain_pb[3]_i_7 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[0] ),\n .O(\\genblk8[0].right_gain_pb[3]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[0].right_gain_pb[3]_i_8 \n (.I0(right_edge_ref[3]),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[3] ),\n .O(\\genblk8[0].right_gain_pb[3]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[0].right_gain_pb[3]_i_9 \n (.I0(right_edge_ref[2]),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[2] ),\n .O(\\genblk8[0].right_gain_pb[3]_i_9_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[0].right_gain_pb[4]_i_1 \n (.I0(\\genblk8[0].right_edge_pb_reg[0]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[0].right_gain_pb_reg[5]_i_6_n_7 ),\n .I3(\\genblk8[0].right_gain_pb_reg[5]_i_7_n_7 ),\n .O(\\genblk8[0].right_gain_pb[4]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAEFEAEAE)) \n \\genblk8[0].right_gain_pb[5]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(right_gain_pb),\n .I2(p_154_out),\n .I3(\\genblk8[0].left_loss_pb_reg[0]_1 ),\n .I4(\\genblk8[0].right_gain_pb_reg[5]_i_4_n_0 ),\n .O(\\genblk8[0].right_gain_pb[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_11 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_12 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_12_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_13 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_13_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_14 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_14_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[0].right_gain_pb[5]_i_15 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_15_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[0].right_gain_pb[5]_i_16 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[4] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_16_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[0].right_gain_pb[5]_i_17 \n (.I0(right_edge_ref[5]),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_17_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[0].right_gain_pb[5]_i_18 \n (.I0(right_edge_ref[4]),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[4] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_18_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk8[0].right_gain_pb[5]_i_19 \n (.I0(\\genblk8[0].right_gain_pb[5]_i_27_n_0 ),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[3] ),\n .I2(right_edge_ref[3]),\n .I3(\\genblk8[0].right_edge_pb_reg_n_0_[4] ),\n .I4(right_edge_ref[4]),\n .O(\\genblk8[0].right_gain_pb[5]_i_19_n_0 ));\n LUT5 #(\n .INIT(32'h000000A8)) \n \\genblk8[0].right_gain_pb[5]_i_2 \n (.I0(p_154_out),\n .I1(\\genblk8[0].right_edge_pb_reg[0]_1 ),\n .I2(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .I3(\\genblk8[0].right_edge_pb_reg[0]_0 ),\n .I4(\\genblk8[0].left_loss_pb_reg[0]_1 ),\n .O(\\genblk8[0].right_gain_pb[5]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk8[0].right_gain_pb[5]_i_20 \n (.I0(\\genblk8[0].right_gain_pb[5]_i_28_n_0 ),\n .I1(right_edge_ref[3]),\n .I2(\\genblk8[0].right_edge_pb_reg_n_0_[3] ),\n .I3(right_edge_ref[4]),\n .I4(\\genblk8[0].right_edge_pb_reg_n_0_[4] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_23 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_23_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_24 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_24_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_25 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_25_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_26 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_26_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk8[0].right_gain_pb[5]_i_27 \n (.I0(right_edge_ref[0]),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[0] ),\n .I2(\\genblk8[0].right_edge_pb_reg_n_0_[1] ),\n .I3(right_edge_ref[1]),\n .I4(\\genblk8[0].right_edge_pb_reg_n_0_[2] ),\n .I5(right_edge_ref[2]),\n .O(\\genblk8[0].right_gain_pb[5]_i_27_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk8[0].right_gain_pb[5]_i_28 \n (.I0(\\genblk8[0].right_edge_pb_reg_n_0_[0] ),\n .I1(right_edge_ref[0]),\n .I2(right_edge_ref[1]),\n .I3(\\genblk8[0].right_edge_pb_reg_n_0_[1] ),\n .I4(right_edge_ref[2]),\n .I5(\\genblk8[0].right_edge_pb_reg_n_0_[2] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_28_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[0].right_gain_pb[5]_i_3 \n (.I0(\\genblk8[0].right_edge_pb_reg[0]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[0].right_gain_pb_reg[5]_i_6_n_6 ),\n .I3(\\genblk8[0].right_gain_pb_reg[5]_i_7_n_6 ),\n .O(\\genblk8[0].right_gain_pb[5]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_30 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_30_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_31 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_31_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_32 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_32_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_33 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_33_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_35 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_35_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_36 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_36_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_37 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_37_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_38 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_38_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_40 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_40_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_41 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_41_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_42 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_42_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_43 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_43_n_0 ));\n LUT4 #(\n .INIT(16'hF880)) \n \\genblk8[0].right_gain_pb[5]_i_44 \n (.I0(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I1(right_edge_ref[4]),\n .I2(right_edge_ref[5]),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[0].right_gain_pb[5]_i_44_n_0 ));\n LUT6 #(\n .INIT(64'h0808088CCECECEE0)) \n \\genblk8[0].right_gain_pb[5]_i_45 \n (.I0(right_edge_ref[2]),\n .I1(right_edge_ref[3]),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .O(\\genblk8[0].right_gain_pb[5]_i_45_n_0 ));\n LUT4 #(\n .INIT(16'h8CE0)) \n \\genblk8[0].right_gain_pb[5]_i_46 \n (.I0(right_edge_ref[0]),\n .I1(right_edge_ref[1]),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .O(\\genblk8[0].right_gain_pb[5]_i_46_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_47 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_47_n_0 ));\n LUT4 #(\n .INIT(16'h0660)) \n \\genblk8[0].right_gain_pb[5]_i_48 \n (.I0(right_edge_ref[4]),\n .I1(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I2(right_edge_ref[5]),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[0].right_gain_pb[5]_i_48_n_0 ));\n LUT6 #(\n .INIT(64'h8484844221212118)) \n \\genblk8[0].right_gain_pb[5]_i_49 \n (.I0(right_edge_ref[2]),\n .I1(right_edge_ref[3]),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .O(\\genblk8[0].right_gain_pb[5]_i_49_n_0 ));\n LUT4 #(\n .INIT(16'h4218)) \n \\genblk8[0].right_gain_pb[5]_i_50 \n (.I0(right_edge_ref[0]),\n .I1(right_edge_ref[1]),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .O(\\genblk8[0].right_gain_pb[5]_i_50_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_52 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_52_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_53 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_53_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_54 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_54_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_55 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_55_n_0 ));\n LUT4 #(\n .INIT(16'hF880)) \n \\genblk8[0].right_gain_pb[5]_i_56 \n (.I0(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[4] ),\n .I2(\\genblk8[0].right_edge_pb_reg_n_0_[5] ),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[0].right_gain_pb[5]_i_56_n_0 ));\n LUT6 #(\n .INIT(64'h0808088CCECECEE0)) \n \\genblk8[0].right_gain_pb[5]_i_57 \n (.I0(\\genblk8[0].right_edge_pb_reg_n_0_[2] ),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[3] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[0].right_gain_pb[5]_i_57_n_0 ));\n LUT4 #(\n .INIT(16'h8CE0)) \n \\genblk8[0].right_gain_pb[5]_i_58 \n (.I0(\\genblk8[0].right_edge_pb_reg_n_0_[0] ),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[1] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\genblk8[0].right_gain_pb[5]_i_58_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[0].right_gain_pb[5]_i_59 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[0].right_gain_pb[5]_i_59_n_0 ));\n LUT4 #(\n .INIT(16'h0660)) \n \\genblk8[0].right_gain_pb[5]_i_60 \n (.I0(\\genblk8[0].right_edge_pb_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I2(\\genblk8[0].right_edge_pb_reg_n_0_[5] ),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[0].right_gain_pb[5]_i_60_n_0 ));\n LUT6 #(\n .INIT(64'h8484844221212118)) \n \\genblk8[0].right_gain_pb[5]_i_61 \n (.I0(\\genblk8[0].right_edge_pb_reg_n_0_[2] ),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[3] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[0].right_gain_pb[5]_i_61_n_0 ));\n LUT4 #(\n .INIT(16'h4218)) \n \\genblk8[0].right_gain_pb[5]_i_62 \n (.I0(\\genblk8[0].right_edge_pb_reg_n_0_[0] ),\n .I1(\\genblk8[0].right_edge_pb_reg_n_0_[1] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\genblk8[0].right_gain_pb[5]_i_62_n_0 ));\n LUT5 #(\n .INIT(32'h04004404)) \n \\genblk8[0].right_gain_pb[5]_i_8 \n (.I0(\\genblk8[0].right_edge_pb_reg[0]_0 ),\n .I1(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .I2(right_edge_ref[5]),\n .I3(\\genblk8[0].right_edge_pb_reg_n_0_[5] ),\n .I4(\\genblk8[0].right_gain_pb[5]_i_19_n_0 ),\n .O(\\genblk8[0].right_gain_pb[5]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FFB200B2)) \n \\genblk8[0].right_gain_pb[5]_i_9 \n (.I0(\\genblk8[0].right_edge_pb_reg_n_0_[5] ),\n .I1(right_edge_ref[5]),\n .I2(\\genblk8[0].right_gain_pb[5]_i_20_n_0 ),\n .I3(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I4(\\genblk8[0].right_gain_pb_reg[5]_i_21_n_0 ),\n .I5(\\genblk8[0].right_edge_pb_reg[0]_0 ),\n .O(\\genblk8[0].right_gain_pb[5]_i_9_n_0 ));\n FDRE \\genblk8[0].right_gain_pb_reg[0] \n (.C(CLK),\n .CE(\\genblk8[0].right_gain_pb[5]_i_2_n_0 ),\n .D(\\genblk8[0].right_gain_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[0].right_gain_pb_reg_n_0_[0] ),\n .R(\\genblk8[0].right_gain_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[0].right_gain_pb_reg[1] \n (.C(CLK),\n .CE(\\genblk8[0].right_gain_pb[5]_i_2_n_0 ),\n .D(\\genblk8[0].right_gain_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[0].right_gain_pb_reg_n_0_[1] ),\n .R(\\genblk8[0].right_gain_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[0].right_gain_pb_reg[2] \n (.C(CLK),\n .CE(\\genblk8[0].right_gain_pb[5]_i_2_n_0 ),\n .D(\\genblk8[0].right_gain_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[0].right_gain_pb_reg__0 [2]),\n .R(\\genblk8[0].right_gain_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[0].right_gain_pb_reg[3] \n (.C(CLK),\n .CE(\\genblk8[0].right_gain_pb[5]_i_2_n_0 ),\n .D(\\genblk8[0].right_gain_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[0].right_gain_pb_reg__0 [3]),\n .R(\\genblk8[0].right_gain_pb[5]_i_1_n_0 ));\n CARRY4 \\genblk8[0].right_gain_pb_reg[3]_i_2 \n (.CI(1'b0),\n .CO({\\genblk8[0].right_gain_pb_reg[3]_i_2_n_0 ,\\genblk8[0].right_gain_pb_reg[3]_i_2_n_1 ,\\genblk8[0].right_gain_pb_reg[3]_i_2_n_2 ,\\genblk8[0].right_gain_pb_reg[3]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ,\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ,\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ,\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }),\n .O({\\genblk8[0].right_gain_pb_reg[3]_i_2_n_4 ,\\genblk8[0].right_gain_pb_reg[3]_i_2_n_5 ,\\genblk8[0].right_gain_pb_reg[3]_i_2_n_6 ,\\genblk8[0].right_gain_pb_reg[3]_i_2_n_7 }),\n .S({\\genblk8[0].right_gain_pb[3]_i_4_n_0 ,\\genblk8[0].right_gain_pb[3]_i_5_n_0 ,\\genblk8[0].right_gain_pb[3]_i_6_n_0 ,\\genblk8[0].right_gain_pb[3]_i_7_n_0 }));\n CARRY4 \\genblk8[0].right_gain_pb_reg[3]_i_3 \n (.CI(1'b0),\n .CO({\\genblk8[0].right_gain_pb_reg[3]_i_3_n_0 ,\\genblk8[0].right_gain_pb_reg[3]_i_3_n_1 ,\\genblk8[0].right_gain_pb_reg[3]_i_3_n_2 ,\\genblk8[0].right_gain_pb_reg[3]_i_3_n_3 }),\n .CYINIT(1'b1),\n .DI(right_edge_ref[3:0]),\n .O({\\genblk8[0].right_gain_pb_reg[3]_i_3_n_4 ,\\genblk8[0].right_gain_pb_reg[3]_i_3_n_5 ,\\genblk8[0].right_gain_pb_reg[3]_i_3_n_6 ,\\genblk8[0].right_gain_pb_reg[3]_i_3_n_7 }),\n .S({\\genblk8[0].right_gain_pb[3]_i_8_n_0 ,\\genblk8[0].right_gain_pb[3]_i_9_n_0 ,\\genblk8[0].right_gain_pb[3]_i_10_n_0 ,\\genblk8[0].right_gain_pb[3]_i_11_n_0 }));\n FDRE \\genblk8[0].right_gain_pb_reg[4] \n (.C(CLK),\n .CE(\\genblk8[0].right_gain_pb[5]_i_2_n_0 ),\n .D(\\genblk8[0].right_gain_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[0].right_gain_pb_reg__0 [4]),\n .R(\\genblk8[0].right_gain_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[0].right_gain_pb_reg[5] \n (.C(CLK),\n .CE(\\genblk8[0].right_gain_pb[5]_i_2_n_0 ),\n .D(\\genblk8[0].right_gain_pb[5]_i_3_n_0 ),\n .Q(\\genblk8[0].right_gain_pb_reg__0 [5]),\n .R(\\genblk8[0].right_gain_pb[5]_i_1_n_0 ));\n CARRY4 \\genblk8[0].right_gain_pb_reg[5]_i_10 \n (.CI(\\genblk8[0].right_gain_pb_reg[5]_i_22_n_0 ),\n .CO({\\genblk8[0].right_gain_pb_reg[5]_i_10_n_0 ,\\genblk8[0].right_gain_pb_reg[5]_i_10_n_1 ,\\genblk8[0].right_gain_pb_reg[5]_i_10_n_2 ,\\genblk8[0].right_gain_pb_reg[5]_i_10_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[0].right_gain_pb_reg[5]_i_10_O_UNCONNECTED [3:0]),\n .S({\\genblk8[0].right_gain_pb[5]_i_23_n_0 ,\\genblk8[0].right_gain_pb[5]_i_24_n_0 ,\\genblk8[0].right_gain_pb[5]_i_25_n_0 ,\\genblk8[0].right_gain_pb[5]_i_26_n_0 }));\n CARRY4 \\genblk8[0].right_gain_pb_reg[5]_i_21 \n (.CI(\\genblk8[0].right_gain_pb_reg[5]_i_29_n_0 ),\n .CO({\\genblk8[0].right_gain_pb_reg[5]_i_21_n_0 ,\\genblk8[0].right_gain_pb_reg[5]_i_21_n_1 ,\\genblk8[0].right_gain_pb_reg[5]_i_21_n_2 ,\\genblk8[0].right_gain_pb_reg[5]_i_21_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[0].right_gain_pb_reg[5]_i_21_O_UNCONNECTED [3:0]),\n .S({\\genblk8[0].right_gain_pb[5]_i_30_n_0 ,\\genblk8[0].right_gain_pb[5]_i_31_n_0 ,\\genblk8[0].right_gain_pb[5]_i_32_n_0 ,\\genblk8[0].right_gain_pb[5]_i_33_n_0 }));\n CARRY4 \\genblk8[0].right_gain_pb_reg[5]_i_22 \n (.CI(\\genblk8[0].right_gain_pb_reg[5]_i_34_n_0 ),\n .CO({\\genblk8[0].right_gain_pb_reg[5]_i_22_n_0 ,\\genblk8[0].right_gain_pb_reg[5]_i_22_n_1 ,\\genblk8[0].right_gain_pb_reg[5]_i_22_n_2 ,\\genblk8[0].right_gain_pb_reg[5]_i_22_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[0].right_gain_pb_reg[5]_i_22_O_UNCONNECTED [3:0]),\n .S({\\genblk8[0].right_gain_pb[5]_i_35_n_0 ,\\genblk8[0].right_gain_pb[5]_i_36_n_0 ,\\genblk8[0].right_gain_pb[5]_i_37_n_0 ,\\genblk8[0].right_gain_pb[5]_i_38_n_0 }));\n CARRY4 \\genblk8[0].right_gain_pb_reg[5]_i_29 \n (.CI(\\genblk8[0].right_gain_pb_reg[5]_i_39_n_0 ),\n .CO({\\genblk8[0].right_gain_pb_reg[5]_i_29_n_0 ,\\genblk8[0].right_gain_pb_reg[5]_i_29_n_1 ,\\genblk8[0].right_gain_pb_reg[5]_i_29_n_2 ,\\genblk8[0].right_gain_pb_reg[5]_i_29_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[0].right_gain_pb_reg[5]_i_29_O_UNCONNECTED [3:0]),\n .S({\\genblk8[0].right_gain_pb[5]_i_40_n_0 ,\\genblk8[0].right_gain_pb[5]_i_41_n_0 ,\\genblk8[0].right_gain_pb[5]_i_42_n_0 ,\\genblk8[0].right_gain_pb[5]_i_43_n_0 }));\n CARRY4 \\genblk8[0].right_gain_pb_reg[5]_i_34 \n (.CI(1'b0),\n .CO({\\genblk8[0].right_gain_pb_reg[5]_i_34_n_0 ,\\genblk8[0].right_gain_pb_reg[5]_i_34_n_1 ,\\genblk8[0].right_gain_pb_reg[5]_i_34_n_2 ,\\genblk8[0].right_gain_pb_reg[5]_i_34_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,\\genblk8[0].right_gain_pb[5]_i_44_n_0 ,\\genblk8[0].right_gain_pb[5]_i_45_n_0 ,\\genblk8[0].right_gain_pb[5]_i_46_n_0 }),\n .O(\\NLW_genblk8[0].right_gain_pb_reg[5]_i_34_O_UNCONNECTED [3:0]),\n .S({\\genblk8[0].right_gain_pb[5]_i_47_n_0 ,\\genblk8[0].right_gain_pb[5]_i_48_n_0 ,\\genblk8[0].right_gain_pb[5]_i_49_n_0 ,\\genblk8[0].right_gain_pb[5]_i_50_n_0 }));\n CARRY4 \\genblk8[0].right_gain_pb_reg[5]_i_39 \n (.CI(\\genblk8[0].right_gain_pb_reg[5]_i_51_n_0 ),\n .CO({\\genblk8[0].right_gain_pb_reg[5]_i_39_n_0 ,\\genblk8[0].right_gain_pb_reg[5]_i_39_n_1 ,\\genblk8[0].right_gain_pb_reg[5]_i_39_n_2 ,\\genblk8[0].right_gain_pb_reg[5]_i_39_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[0].right_gain_pb_reg[5]_i_39_O_UNCONNECTED [3:0]),\n .S({\\genblk8[0].right_gain_pb[5]_i_52_n_0 ,\\genblk8[0].right_gain_pb[5]_i_53_n_0 ,\\genblk8[0].right_gain_pb[5]_i_54_n_0 ,\\genblk8[0].right_gain_pb[5]_i_55_n_0 }));\n MUXF7 \\genblk8[0].right_gain_pb_reg[5]_i_4 \n (.I0(\\genblk8[0].right_gain_pb[5]_i_8_n_0 ),\n .I1(\\genblk8[0].right_gain_pb[5]_i_9_n_0 ),\n .O(\\genblk8[0].right_gain_pb_reg[5]_i_4_n_0 ),\n .S(\\genblk8[0].right_edge_pb_reg[0]_1 ));\n CARRY4 \\genblk8[0].right_gain_pb_reg[5]_i_5 \n (.CI(\\genblk8[0].right_gain_pb_reg[5]_i_10_n_0 ),\n .CO({\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ,\\genblk8[0].right_gain_pb_reg[5]_i_5_n_1 ,\\genblk8[0].right_gain_pb_reg[5]_i_5_n_2 ,\\genblk8[0].right_gain_pb_reg[5]_i_5_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[0].right_gain_pb_reg[5]_i_5_O_UNCONNECTED [3:0]),\n .S({\\genblk8[0].right_gain_pb[5]_i_11_n_0 ,\\genblk8[0].right_gain_pb[5]_i_12_n_0 ,\\genblk8[0].right_gain_pb[5]_i_13_n_0 ,\\genblk8[0].right_gain_pb[5]_i_14_n_0 }));\n CARRY4 \\genblk8[0].right_gain_pb_reg[5]_i_51 \n (.CI(1'b0),\n .CO({\\genblk8[0].right_gain_pb_reg[5]_i_51_n_0 ,\\genblk8[0].right_gain_pb_reg[5]_i_51_n_1 ,\\genblk8[0].right_gain_pb_reg[5]_i_51_n_2 ,\\genblk8[0].right_gain_pb_reg[5]_i_51_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,\\genblk8[0].right_gain_pb[5]_i_56_n_0 ,\\genblk8[0].right_gain_pb[5]_i_57_n_0 ,\\genblk8[0].right_gain_pb[5]_i_58_n_0 }),\n .O(\\NLW_genblk8[0].right_gain_pb_reg[5]_i_51_O_UNCONNECTED [3:0]),\n .S({\\genblk8[0].right_gain_pb[5]_i_59_n_0 ,\\genblk8[0].right_gain_pb[5]_i_60_n_0 ,\\genblk8[0].right_gain_pb[5]_i_61_n_0 ,\\genblk8[0].right_gain_pb[5]_i_62_n_0 }));\n CARRY4 \\genblk8[0].right_gain_pb_reg[5]_i_6 \n (.CI(\\genblk8[0].right_gain_pb_reg[3]_i_2_n_0 ),\n .CO({\\NLW_genblk8[0].right_gain_pb_reg[5]_i_6_CO_UNCONNECTED [3:1],\\genblk8[0].right_gain_pb_reg[5]_i_6_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,\\prbs_dqs_tap_cnt_r_reg_n_0_[4] }),\n .O({\\NLW_genblk8[0].right_gain_pb_reg[5]_i_6_O_UNCONNECTED [3:2],\\genblk8[0].right_gain_pb_reg[5]_i_6_n_6 ,\\genblk8[0].right_gain_pb_reg[5]_i_6_n_7 }),\n .S({1'b0,1'b0,\\genblk8[0].right_gain_pb[5]_i_15_n_0 ,\\genblk8[0].right_gain_pb[5]_i_16_n_0 }));\n CARRY4 \\genblk8[0].right_gain_pb_reg[5]_i_7 \n (.CI(\\genblk8[0].right_gain_pb_reg[3]_i_3_n_0 ),\n .CO({\\NLW_genblk8[0].right_gain_pb_reg[5]_i_7_CO_UNCONNECTED [3:1],\\genblk8[0].right_gain_pb_reg[5]_i_7_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,right_edge_ref[4]}),\n .O({\\NLW_genblk8[0].right_gain_pb_reg[5]_i_7_O_UNCONNECTED [3:2],\\genblk8[0].right_gain_pb_reg[5]_i_7_n_6 ,\\genblk8[0].right_gain_pb_reg[5]_i_7_n_7 }),\n .S({1'b0,1'b0,\\genblk8[0].right_gain_pb[5]_i_17_n_0 ,\\genblk8[0].right_gain_pb[5]_i_18_n_0 }));\n FDRE \\genblk8[1].left_edge_found_pb_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[1].left_edge_found_pb_reg[1]_0 ),\n .Q(\\genblk8[1].left_loss_pb_reg[6]_0 ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\genblk8[1].left_edge_pb[11]_i_1 \n (.I0(p_154_out),\n .I1(p_146_out),\n .O(\\genblk8[1].left_edge_pb[11]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\genblk8[1].left_edge_pb[11]_i_2 \n (.I0(match_flag_pb[15]),\n .I1(\\genblk8[1].left_edge_pb[11]_i_3_n_0 ),\n .I2(\\genblk7[1].compare_err_pb_latch_r_reg_n_0_[1] ),\n .I3(match_flag_pb[14]),\n .I4(match_flag_pb[12]),\n .I5(match_flag_pb[13]),\n .O(p_146_out));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\genblk8[1].left_edge_pb[11]_i_3 \n (.I0(match_flag_pb[10]),\n .I1(match_flag_pb[11]),\n .I2(match_flag_pb[8]),\n .I3(match_flag_pb[9]),\n .O(\\genblk8[1].left_edge_pb[11]_i_3_n_0 ));\n FDRE \\genblk8[1].left_edge_pb_reg[10] \n (.C(CLK),\n .CE(\\genblk8[1].left_edge_pb[11]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[1].left_edge_pb_reg_n_0_[10] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[1].left_edge_pb_reg[11] \n (.C(CLK),\n .CE(\\genblk8[1].left_edge_pb[11]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[5]_i_3_n_0 ),\n .Q(\\genblk8[1].left_edge_pb_reg_n_0_[11] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[1].left_edge_pb_reg[6] \n (.C(CLK),\n .CE(\\genblk8[1].left_edge_pb[11]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[1].left_edge_pb_reg_n_0_[6] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[1].left_edge_pb_reg[7] \n (.C(CLK),\n .CE(\\genblk8[1].left_edge_pb[11]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[1].left_edge_pb_reg_n_0_[7] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[1].left_edge_pb_reg[8] \n (.C(CLK),\n .CE(\\genblk8[1].left_edge_pb[11]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[1].left_edge_pb_reg_n_0_[8] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[1].left_edge_pb_reg[9] \n (.C(CLK),\n .CE(\\genblk8[1].left_edge_pb[11]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[1].left_edge_pb_reg_n_0_[9] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[1].left_edge_updated_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[1].left_edge_updated_reg[1]_0 ),\n .Q(D[1]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAEFEAEAE)) \n \\genblk8[1].left_loss_pb[11]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(right_gain_pb),\n .I2(p_154_out),\n .I3(\\genblk8[1].left_loss_pb_reg[6]_0 ),\n .I4(p_146_out),\n .O(\\genblk8[1].left_loss_pb[11]_i_1_n_0 ));\n FDRE \\genblk8[1].left_loss_pb_reg[10] \n (.C(CLK),\n .CE(\\genblk8[1].left_loss_pb[11]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[1].left_loss_pb_reg__0 [4]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[1].left_loss_pb_reg[11] \n (.C(CLK),\n .CE(\\genblk8[1].left_loss_pb[11]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[5]_i_2_n_0 ),\n .Q(\\genblk8[1].left_loss_pb_reg__0 [5]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[1].left_loss_pb_reg[6] \n (.C(CLK),\n .CE(\\genblk8[1].left_loss_pb[11]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[1].left_loss_pb_reg_n_0_[6] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[1].left_loss_pb_reg[7] \n (.C(CLK),\n .CE(\\genblk8[1].left_loss_pb[11]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[1].left_loss_pb_reg_n_0_[7] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[1].left_loss_pb_reg[8] \n (.C(CLK),\n .CE(\\genblk8[1].left_loss_pb[11]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[1].left_loss_pb_reg__0 [2]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[1].left_loss_pb_reg[9] \n (.C(CLK),\n .CE(\\genblk8[1].left_loss_pb[11]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[1].left_loss_pb_reg__0 [3]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDSE \\genblk8[1].match_flag_pb_reg[10] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[9]),\n .Q(match_flag_pb[10]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[1].match_flag_pb_reg[11] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[10]),\n .Q(match_flag_pb[11]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[1].match_flag_pb_reg[12] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[11]),\n .Q(match_flag_pb[12]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[1].match_flag_pb_reg[13] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[12]),\n .Q(match_flag_pb[13]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[1].match_flag_pb_reg[14] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[13]),\n .Q(match_flag_pb[14]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[1].match_flag_pb_reg[15] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[14]),\n .Q(match_flag_pb[15]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[1].match_flag_pb_reg[8] \n (.C(CLK),\n .CE(p_154_out),\n .D(\\genblk7[1].compare_err_pb_latch_r_reg_n_0_[1] ),\n .Q(match_flag_pb[8]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[1].match_flag_pb_reg[9] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[8]),\n .Q(match_flag_pb[9]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDRE \\genblk8[1].right_edge_found_pb_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[1].right_edge_found_pb_reg[1]_0 ),\n .Q(\\genblk8[1].right_edge_pb_reg[6]_0 ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAABAAAAAAAAA)) \n \\genblk8[1].right_edge_pb[11]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(p_146_out),\n .I2(p_154_out),\n .I3(p_143_out),\n .I4(\\genblk8[1].right_edge_pb_reg[6]_0 ),\n .I5(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .O(\\genblk8[1].right_edge_pb[11]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h08)) \n \\genblk8[1].right_edge_pb[11]_i_2 \n (.I0(p_154_out),\n .I1(p_143_out),\n .I2(p_146_out),\n .O(\\genblk8[1].right_edge_pb[11]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\genblk8[1].right_edge_pb[11]_i_3 \n (.I0(\\genblk7[1].compare_err_pb_latch_r_reg_n_0_[1] ),\n .I1(\\genblk8[1].left_edge_pb[11]_i_3_n_0 ),\n .I2(match_flag_pb[15]),\n .I3(match_flag_pb[14]),\n .I4(match_flag_pb[12]),\n .I5(match_flag_pb[13]),\n .O(p_143_out));\n FDSE \\genblk8[1].right_edge_pb_reg[10] \n (.C(CLK),\n .CE(\\genblk8[1].right_edge_pb[11]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[1].right_edge_pb_reg_n_0_[10] ),\n .S(\\genblk8[1].right_edge_pb[11]_i_1_n_0 ));\n FDSE \\genblk8[1].right_edge_pb_reg[11] \n (.C(CLK),\n .CE(\\genblk8[1].right_edge_pb[11]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[5]_i_3_n_0 ),\n .Q(\\genblk8[1].right_edge_pb_reg_n_0_[11] ),\n .S(\\genblk8[1].right_edge_pb[11]_i_1_n_0 ));\n FDSE \\genblk8[1].right_edge_pb_reg[6] \n (.C(CLK),\n .CE(\\genblk8[1].right_edge_pb[11]_i_2_n_0 ),\n .D(\\genblk8[0].left_edge_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[1].right_edge_pb_reg_n_0_[6] ),\n .S(\\genblk8[1].right_edge_pb[11]_i_1_n_0 ));\n FDSE \\genblk8[1].right_edge_pb_reg[7] \n (.C(CLK),\n .CE(\\genblk8[1].right_edge_pb[11]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[1].right_edge_pb_reg_n_0_[7] ),\n .S(\\genblk8[1].right_edge_pb[11]_i_1_n_0 ));\n FDSE \\genblk8[1].right_edge_pb_reg[8] \n (.C(CLK),\n .CE(\\genblk8[1].right_edge_pb[11]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[1].right_edge_pb_reg_n_0_[8] ),\n .S(\\genblk8[1].right_edge_pb[11]_i_1_n_0 ));\n FDSE \\genblk8[1].right_edge_pb_reg[9] \n (.C(CLK),\n .CE(\\genblk8[1].right_edge_pb[11]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[1].right_edge_pb_reg_n_0_[9] ),\n .S(\\genblk8[1].right_edge_pb[11]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[1].right_gain_pb[10]_i_1 \n (.I0(p_143_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[1].right_gain_pb_reg[11]_i_5_n_7 ),\n .I3(\\genblk8[1].right_gain_pb_reg[11]_i_6_n_7 ),\n .O(\\genblk8[1].right_gain_pb[10]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAEFEAEAE)) \n \\genblk8[1].right_gain_pb[11]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(right_gain_pb),\n .I2(p_154_out),\n .I3(p_146_out),\n .I4(\\genblk8[1].right_gain_pb_reg[11]_i_4_n_0 ),\n .O(\\genblk8[1].right_gain_pb[11]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[1].right_gain_pb[11]_i_10 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[10] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[1].right_gain_pb[11]_i_11 \n (.I0(right_edge_ref[5]),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[11] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[1].right_gain_pb[11]_i_12 \n (.I0(right_edge_ref[4]),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[10] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_12_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk8[1].right_gain_pb[11]_i_13 \n (.I0(\\genblk8[1].right_gain_pb[11]_i_16_n_0 ),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[9] ),\n .I2(right_edge_ref[3]),\n .I3(\\genblk8[1].right_edge_pb_reg_n_0_[10] ),\n .I4(right_edge_ref[4]),\n .O(\\genblk8[1].right_gain_pb[11]_i_13_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk8[1].right_gain_pb[11]_i_14 \n (.I0(\\genblk8[1].right_gain_pb[11]_i_17_n_0 ),\n .I1(right_edge_ref[3]),\n .I2(\\genblk8[1].right_edge_pb_reg_n_0_[9] ),\n .I3(right_edge_ref[4]),\n .I4(\\genblk8[1].right_edge_pb_reg_n_0_[10] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk8[1].right_gain_pb[11]_i_16 \n (.I0(right_edge_ref[0]),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[6] ),\n .I2(\\genblk8[1].right_edge_pb_reg_n_0_[7] ),\n .I3(right_edge_ref[1]),\n .I4(\\genblk8[1].right_edge_pb_reg_n_0_[8] ),\n .I5(right_edge_ref[2]),\n .O(\\genblk8[1].right_gain_pb[11]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk8[1].right_gain_pb[11]_i_17 \n (.I0(\\genblk8[1].right_edge_pb_reg_n_0_[6] ),\n .I1(right_edge_ref[0]),\n .I2(right_edge_ref[1]),\n .I3(\\genblk8[1].right_edge_pb_reg_n_0_[7] ),\n .I4(right_edge_ref[2]),\n .I5(\\genblk8[1].right_edge_pb_reg_n_0_[8] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[1].right_gain_pb[11]_i_19 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_19_n_0 ));\n LUT5 #(\n .INIT(32'h000000A8)) \n \\genblk8[1].right_gain_pb[11]_i_2 \n (.I0(p_154_out),\n .I1(p_143_out),\n .I2(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .I3(\\genblk8[1].right_edge_pb_reg[6]_0 ),\n .I4(p_146_out),\n .O(\\genblk8[1].right_gain_pb[11]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[1].right_gain_pb[11]_i_20 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[1].right_gain_pb[11]_i_21 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_21_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[1].right_gain_pb[11]_i_22 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_22_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[1].right_gain_pb[11]_i_24 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_24_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[1].right_gain_pb[11]_i_25 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_25_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[1].right_gain_pb[11]_i_26 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_26_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[1].right_gain_pb[11]_i_27 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_27_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[1].right_gain_pb[11]_i_29 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_29_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[1].right_gain_pb[11]_i_3 \n (.I0(p_143_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[1].right_gain_pb_reg[11]_i_5_n_6 ),\n .I3(\\genblk8[1].right_gain_pb_reg[11]_i_6_n_6 ),\n .O(\\genblk8[1].right_gain_pb[11]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[1].right_gain_pb[11]_i_30 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_30_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[1].right_gain_pb[11]_i_31 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_31_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[1].right_gain_pb[11]_i_32 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_32_n_0 ));\n LUT4 #(\n .INIT(16'hF880)) \n \\genblk8[1].right_gain_pb[11]_i_33 \n (.I0(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[10] ),\n .I2(\\genblk8[1].right_edge_pb_reg_n_0_[11] ),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[1].right_gain_pb[11]_i_33_n_0 ));\n LUT6 #(\n .INIT(64'h0808088CCECECEE0)) \n \\genblk8[1].right_gain_pb[11]_i_34 \n (.I0(\\genblk8[1].right_edge_pb_reg_n_0_[8] ),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[9] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[1].right_gain_pb[11]_i_34_n_0 ));\n LUT4 #(\n .INIT(16'h8CE0)) \n \\genblk8[1].right_gain_pb[11]_i_35 \n (.I0(\\genblk8[1].right_edge_pb_reg_n_0_[6] ),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[7] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\genblk8[1].right_gain_pb[11]_i_35_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[1].right_gain_pb[11]_i_36 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_36_n_0 ));\n LUT4 #(\n .INIT(16'h0660)) \n \\genblk8[1].right_gain_pb[11]_i_37 \n (.I0(\\genblk8[1].right_edge_pb_reg_n_0_[10] ),\n .I1(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I2(\\genblk8[1].right_edge_pb_reg_n_0_[11] ),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[1].right_gain_pb[11]_i_37_n_0 ));\n LUT6 #(\n .INIT(64'h8484844221212118)) \n \\genblk8[1].right_gain_pb[11]_i_38 \n (.I0(\\genblk8[1].right_edge_pb_reg_n_0_[8] ),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[9] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[1].right_gain_pb[11]_i_38_n_0 ));\n LUT4 #(\n .INIT(16'h4218)) \n \\genblk8[1].right_gain_pb[11]_i_39 \n (.I0(\\genblk8[1].right_edge_pb_reg_n_0_[6] ),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[7] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\genblk8[1].right_gain_pb[11]_i_39_n_0 ));\n LUT5 #(\n .INIT(32'h04004404)) \n \\genblk8[1].right_gain_pb[11]_i_7 \n (.I0(\\genblk8[1].right_edge_pb_reg[6]_0 ),\n .I1(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .I2(right_edge_ref[5]),\n .I3(\\genblk8[1].right_edge_pb_reg_n_0_[11] ),\n .I4(\\genblk8[1].right_gain_pb[11]_i_13_n_0 ),\n .O(\\genblk8[1].right_gain_pb[11]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FFB200B2)) \n \\genblk8[1].right_gain_pb[11]_i_8 \n (.I0(\\genblk8[1].right_edge_pb_reg_n_0_[11] ),\n .I1(right_edge_ref[5]),\n .I2(\\genblk8[1].right_gain_pb[11]_i_14_n_0 ),\n .I3(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I4(\\genblk8[1].right_gain_pb_reg[11]_i_15_n_0 ),\n .I5(\\genblk8[1].right_edge_pb_reg[6]_0 ),\n .O(\\genblk8[1].right_gain_pb[11]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[1].right_gain_pb[11]_i_9 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[11] ),\n .O(\\genblk8[1].right_gain_pb[11]_i_9_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[1].right_gain_pb[6]_i_1 \n (.I0(p_143_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[1].right_gain_pb_reg[9]_i_2_n_7 ),\n .I3(\\genblk8[1].right_gain_pb_reg[9]_i_3_n_7 ),\n .O(\\genblk8[1].right_gain_pb[6]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[1].right_gain_pb[7]_i_1 \n (.I0(p_143_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[1].right_gain_pb_reg[9]_i_2_n_6 ),\n .I3(\\genblk8[1].right_gain_pb_reg[9]_i_3_n_6 ),\n .O(\\genblk8[1].right_gain_pb[7]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[1].right_gain_pb[8]_i_1 \n (.I0(p_143_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[1].right_gain_pb_reg[9]_i_2_n_5 ),\n .I3(\\genblk8[1].right_gain_pb_reg[9]_i_3_n_5 ),\n .O(\\genblk8[1].right_gain_pb[8]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[1].right_gain_pb[9]_i_1 \n (.I0(p_143_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[1].right_gain_pb_reg[9]_i_2_n_4 ),\n .I3(\\genblk8[1].right_gain_pb_reg[9]_i_3_n_4 ),\n .O(\\genblk8[1].right_gain_pb[9]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[1].right_gain_pb[9]_i_10 \n (.I0(right_edge_ref[1]),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[7] ),\n .O(\\genblk8[1].right_gain_pb[9]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[1].right_gain_pb[9]_i_11 \n (.I0(right_edge_ref[0]),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[6] ),\n .O(\\genblk8[1].right_gain_pb[9]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[1].right_gain_pb[9]_i_4 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[9] ),\n .O(\\genblk8[1].right_gain_pb[9]_i_4_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[1].right_gain_pb[9]_i_5 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[8] ),\n .O(\\genblk8[1].right_gain_pb[9]_i_5_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[1].right_gain_pb[9]_i_6 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[7] ),\n .O(\\genblk8[1].right_gain_pb[9]_i_6_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[1].right_gain_pb[9]_i_7 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[6] ),\n .O(\\genblk8[1].right_gain_pb[9]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[1].right_gain_pb[9]_i_8 \n (.I0(right_edge_ref[3]),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[9] ),\n .O(\\genblk8[1].right_gain_pb[9]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[1].right_gain_pb[9]_i_9 \n (.I0(right_edge_ref[2]),\n .I1(\\genblk8[1].right_edge_pb_reg_n_0_[8] ),\n .O(\\genblk8[1].right_gain_pb[9]_i_9_n_0 ));\n FDRE \\genblk8[1].right_gain_pb_reg[10] \n (.C(CLK),\n .CE(\\genblk8[1].right_gain_pb[11]_i_2_n_0 ),\n .D(\\genblk8[1].right_gain_pb[10]_i_1_n_0 ),\n .Q(\\genblk8[1].right_gain_pb_reg__0 [4]),\n .R(\\genblk8[1].right_gain_pb[11]_i_1_n_0 ));\n FDRE \\genblk8[1].right_gain_pb_reg[11] \n (.C(CLK),\n .CE(\\genblk8[1].right_gain_pb[11]_i_2_n_0 ),\n .D(\\genblk8[1].right_gain_pb[11]_i_3_n_0 ),\n .Q(\\genblk8[1].right_gain_pb_reg__0 [5]),\n .R(\\genblk8[1].right_gain_pb[11]_i_1_n_0 ));\n CARRY4 \\genblk8[1].right_gain_pb_reg[11]_i_15 \n (.CI(\\genblk8[1].right_gain_pb_reg[11]_i_18_n_0 ),\n .CO({\\genblk8[1].right_gain_pb_reg[11]_i_15_n_0 ,\\genblk8[1].right_gain_pb_reg[11]_i_15_n_1 ,\\genblk8[1].right_gain_pb_reg[11]_i_15_n_2 ,\\genblk8[1].right_gain_pb_reg[11]_i_15_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[1].right_gain_pb_reg[11]_i_15_O_UNCONNECTED [3:0]),\n .S({\\genblk8[1].right_gain_pb[11]_i_19_n_0 ,\\genblk8[1].right_gain_pb[11]_i_20_n_0 ,\\genblk8[1].right_gain_pb[11]_i_21_n_0 ,\\genblk8[1].right_gain_pb[11]_i_22_n_0 }));\n CARRY4 \\genblk8[1].right_gain_pb_reg[11]_i_18 \n (.CI(\\genblk8[1].right_gain_pb_reg[11]_i_23_n_0 ),\n .CO({\\genblk8[1].right_gain_pb_reg[11]_i_18_n_0 ,\\genblk8[1].right_gain_pb_reg[11]_i_18_n_1 ,\\genblk8[1].right_gain_pb_reg[11]_i_18_n_2 ,\\genblk8[1].right_gain_pb_reg[11]_i_18_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[1].right_gain_pb_reg[11]_i_18_O_UNCONNECTED [3:0]),\n .S({\\genblk8[1].right_gain_pb[11]_i_24_n_0 ,\\genblk8[1].right_gain_pb[11]_i_25_n_0 ,\\genblk8[1].right_gain_pb[11]_i_26_n_0 ,\\genblk8[1].right_gain_pb[11]_i_27_n_0 }));\n CARRY4 \\genblk8[1].right_gain_pb_reg[11]_i_23 \n (.CI(\\genblk8[1].right_gain_pb_reg[11]_i_28_n_0 ),\n .CO({\\genblk8[1].right_gain_pb_reg[11]_i_23_n_0 ,\\genblk8[1].right_gain_pb_reg[11]_i_23_n_1 ,\\genblk8[1].right_gain_pb_reg[11]_i_23_n_2 ,\\genblk8[1].right_gain_pb_reg[11]_i_23_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[1].right_gain_pb_reg[11]_i_23_O_UNCONNECTED [3:0]),\n .S({\\genblk8[1].right_gain_pb[11]_i_29_n_0 ,\\genblk8[1].right_gain_pb[11]_i_30_n_0 ,\\genblk8[1].right_gain_pb[11]_i_31_n_0 ,\\genblk8[1].right_gain_pb[11]_i_32_n_0 }));\n CARRY4 \\genblk8[1].right_gain_pb_reg[11]_i_28 \n (.CI(1'b0),\n .CO({\\genblk8[1].right_gain_pb_reg[11]_i_28_n_0 ,\\genblk8[1].right_gain_pb_reg[11]_i_28_n_1 ,\\genblk8[1].right_gain_pb_reg[11]_i_28_n_2 ,\\genblk8[1].right_gain_pb_reg[11]_i_28_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,\\genblk8[1].right_gain_pb[11]_i_33_n_0 ,\\genblk8[1].right_gain_pb[11]_i_34_n_0 ,\\genblk8[1].right_gain_pb[11]_i_35_n_0 }),\n .O(\\NLW_genblk8[1].right_gain_pb_reg[11]_i_28_O_UNCONNECTED [3:0]),\n .S({\\genblk8[1].right_gain_pb[11]_i_36_n_0 ,\\genblk8[1].right_gain_pb[11]_i_37_n_0 ,\\genblk8[1].right_gain_pb[11]_i_38_n_0 ,\\genblk8[1].right_gain_pb[11]_i_39_n_0 }));\n MUXF7 \\genblk8[1].right_gain_pb_reg[11]_i_4 \n (.I0(\\genblk8[1].right_gain_pb[11]_i_7_n_0 ),\n .I1(\\genblk8[1].right_gain_pb[11]_i_8_n_0 ),\n .O(\\genblk8[1].right_gain_pb_reg[11]_i_4_n_0 ),\n .S(p_143_out));\n CARRY4 \\genblk8[1].right_gain_pb_reg[11]_i_5 \n (.CI(\\genblk8[1].right_gain_pb_reg[9]_i_2_n_0 ),\n .CO({\\NLW_genblk8[1].right_gain_pb_reg[11]_i_5_CO_UNCONNECTED [3:1],\\genblk8[1].right_gain_pb_reg[11]_i_5_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,\\prbs_dqs_tap_cnt_r_reg_n_0_[4] }),\n .O({\\NLW_genblk8[1].right_gain_pb_reg[11]_i_5_O_UNCONNECTED [3:2],\\genblk8[1].right_gain_pb_reg[11]_i_5_n_6 ,\\genblk8[1].right_gain_pb_reg[11]_i_5_n_7 }),\n .S({1'b0,1'b0,\\genblk8[1].right_gain_pb[11]_i_9_n_0 ,\\genblk8[1].right_gain_pb[11]_i_10_n_0 }));\n CARRY4 \\genblk8[1].right_gain_pb_reg[11]_i_6 \n (.CI(\\genblk8[1].right_gain_pb_reg[9]_i_3_n_0 ),\n .CO({\\NLW_genblk8[1].right_gain_pb_reg[11]_i_6_CO_UNCONNECTED [3:1],\\genblk8[1].right_gain_pb_reg[11]_i_6_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,right_edge_ref[4]}),\n .O({\\NLW_genblk8[1].right_gain_pb_reg[11]_i_6_O_UNCONNECTED [3:2],\\genblk8[1].right_gain_pb_reg[11]_i_6_n_6 ,\\genblk8[1].right_gain_pb_reg[11]_i_6_n_7 }),\n .S({1'b0,1'b0,\\genblk8[1].right_gain_pb[11]_i_11_n_0 ,\\genblk8[1].right_gain_pb[11]_i_12_n_0 }));\n FDRE \\genblk8[1].right_gain_pb_reg[6] \n (.C(CLK),\n .CE(\\genblk8[1].right_gain_pb[11]_i_2_n_0 ),\n .D(\\genblk8[1].right_gain_pb[6]_i_1_n_0 ),\n .Q(\\genblk8[1].right_gain_pb_reg_n_0_[6] ),\n .R(\\genblk8[1].right_gain_pb[11]_i_1_n_0 ));\n FDRE \\genblk8[1].right_gain_pb_reg[7] \n (.C(CLK),\n .CE(\\genblk8[1].right_gain_pb[11]_i_2_n_0 ),\n .D(\\genblk8[1].right_gain_pb[7]_i_1_n_0 ),\n .Q(\\genblk8[1].right_gain_pb_reg_n_0_[7] ),\n .R(\\genblk8[1].right_gain_pb[11]_i_1_n_0 ));\n FDRE \\genblk8[1].right_gain_pb_reg[8] \n (.C(CLK),\n .CE(\\genblk8[1].right_gain_pb[11]_i_2_n_0 ),\n .D(\\genblk8[1].right_gain_pb[8]_i_1_n_0 ),\n .Q(\\genblk8[1].right_gain_pb_reg__0 [2]),\n .R(\\genblk8[1].right_gain_pb[11]_i_1_n_0 ));\n FDRE \\genblk8[1].right_gain_pb_reg[9] \n (.C(CLK),\n .CE(\\genblk8[1].right_gain_pb[11]_i_2_n_0 ),\n .D(\\genblk8[1].right_gain_pb[9]_i_1_n_0 ),\n .Q(\\genblk8[1].right_gain_pb_reg__0 [3]),\n .R(\\genblk8[1].right_gain_pb[11]_i_1_n_0 ));\n CARRY4 \\genblk8[1].right_gain_pb_reg[9]_i_2 \n (.CI(1'b0),\n .CO({\\genblk8[1].right_gain_pb_reg[9]_i_2_n_0 ,\\genblk8[1].right_gain_pb_reg[9]_i_2_n_1 ,\\genblk8[1].right_gain_pb_reg[9]_i_2_n_2 ,\\genblk8[1].right_gain_pb_reg[9]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ,\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ,\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ,\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }),\n .O({\\genblk8[1].right_gain_pb_reg[9]_i_2_n_4 ,\\genblk8[1].right_gain_pb_reg[9]_i_2_n_5 ,\\genblk8[1].right_gain_pb_reg[9]_i_2_n_6 ,\\genblk8[1].right_gain_pb_reg[9]_i_2_n_7 }),\n .S({\\genblk8[1].right_gain_pb[9]_i_4_n_0 ,\\genblk8[1].right_gain_pb[9]_i_5_n_0 ,\\genblk8[1].right_gain_pb[9]_i_6_n_0 ,\\genblk8[1].right_gain_pb[9]_i_7_n_0 }));\n CARRY4 \\genblk8[1].right_gain_pb_reg[9]_i_3 \n (.CI(1'b0),\n .CO({\\genblk8[1].right_gain_pb_reg[9]_i_3_n_0 ,\\genblk8[1].right_gain_pb_reg[9]_i_3_n_1 ,\\genblk8[1].right_gain_pb_reg[9]_i_3_n_2 ,\\genblk8[1].right_gain_pb_reg[9]_i_3_n_3 }),\n .CYINIT(1'b1),\n .DI(right_edge_ref[3:0]),\n .O({\\genblk8[1].right_gain_pb_reg[9]_i_3_n_4 ,\\genblk8[1].right_gain_pb_reg[9]_i_3_n_5 ,\\genblk8[1].right_gain_pb_reg[9]_i_3_n_6 ,\\genblk8[1].right_gain_pb_reg[9]_i_3_n_7 }),\n .S({\\genblk8[1].right_gain_pb[9]_i_8_n_0 ,\\genblk8[1].right_gain_pb[9]_i_9_n_0 ,\\genblk8[1].right_gain_pb[9]_i_10_n_0 ,\\genblk8[1].right_gain_pb[9]_i_11_n_0 }));\n FDRE \\genblk8[2].left_edge_found_pb_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[2].left_edge_found_pb_reg[2]_0 ),\n .Q(\\genblk8[2].left_loss_pb_reg[12]_0 ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\genblk8[2].left_edge_pb[17]_i_1 \n (.I0(p_154_out),\n .I1(\\genblk8[2].right_edge_pb_reg[12]_2 ),\n .O(\\genblk8[2].left_edge_pb[17]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\genblk8[2].left_edge_pb[17]_i_2 \n (.I0(match_flag_pb[23]),\n .I1(\\genblk8[2].left_edge_pb[17]_i_3_n_0 ),\n .I2(\\genblk7[2].compare_err_pb_latch_r_reg_n_0_[2] ),\n .I3(match_flag_pb[22]),\n .I4(match_flag_pb[20]),\n .I5(match_flag_pb[21]),\n .O(\\genblk8[2].right_edge_pb_reg[12]_2 ));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\genblk8[2].left_edge_pb[17]_i_3 \n (.I0(match_flag_pb[18]),\n .I1(match_flag_pb[19]),\n .I2(match_flag_pb[16]),\n .I3(match_flag_pb[17]),\n .O(\\genblk8[2].left_edge_pb[17]_i_3_n_0 ));\n FDRE \\genblk8[2].left_edge_pb_reg[12] \n (.C(CLK),\n .CE(\\genblk8[2].left_edge_pb[17]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[2].left_edge_pb_reg_n_0_[12] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[2].left_edge_pb_reg[13] \n (.C(CLK),\n .CE(\\genblk8[2].left_edge_pb[17]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[2].left_edge_pb_reg_n_0_[13] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[2].left_edge_pb_reg[14] \n (.C(CLK),\n .CE(\\genblk8[2].left_edge_pb[17]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[2].left_edge_pb_reg_n_0_[14] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[2].left_edge_pb_reg[15] \n (.C(CLK),\n .CE(\\genblk8[2].left_edge_pb[17]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[2].left_edge_pb_reg_n_0_[15] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[2].left_edge_pb_reg[16] \n (.C(CLK),\n .CE(\\genblk8[2].left_edge_pb[17]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[2].left_edge_pb_reg_n_0_[16] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[2].left_edge_pb_reg[17] \n (.C(CLK),\n .CE(\\genblk8[2].left_edge_pb[17]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[5]_i_3_n_0 ),\n .Q(\\genblk8[2].left_edge_pb_reg_n_0_[17] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[2].left_edge_updated_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[2].left_edge_updated_reg[2]_0 ),\n .Q(D[2]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAEFEAEAE)) \n \\genblk8[2].left_loss_pb[17]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(right_gain_pb),\n .I2(p_154_out),\n .I3(\\genblk8[2].left_loss_pb_reg[12]_0 ),\n .I4(\\genblk8[2].right_edge_pb_reg[12]_2 ),\n .O(\\genblk8[2].left_loss_pb[17]_i_1_n_0 ));\n FDRE \\genblk8[2].left_loss_pb_reg[12] \n (.C(CLK),\n .CE(\\genblk8[2].left_loss_pb[17]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[2].left_loss_pb_reg_n_0_[12] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[2].left_loss_pb_reg[13] \n (.C(CLK),\n .CE(\\genblk8[2].left_loss_pb[17]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[2].left_loss_pb_reg_n_0_[13] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[2].left_loss_pb_reg[14] \n (.C(CLK),\n .CE(\\genblk8[2].left_loss_pb[17]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[2].left_loss_pb_reg__0 [2]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[2].left_loss_pb_reg[15] \n (.C(CLK),\n .CE(\\genblk8[2].left_loss_pb[17]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[2].left_loss_pb_reg__0 [3]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[2].left_loss_pb_reg[16] \n (.C(CLK),\n .CE(\\genblk8[2].left_loss_pb[17]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[2].left_loss_pb_reg__0 [4]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[2].left_loss_pb_reg[17] \n (.C(CLK),\n .CE(\\genblk8[2].left_loss_pb[17]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[5]_i_2_n_0 ),\n .Q(\\genblk8[2].left_loss_pb_reg__0 [5]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDSE \\genblk8[2].match_flag_pb_reg[16] \n (.C(CLK),\n .CE(p_154_out),\n .D(\\genblk7[2].compare_err_pb_latch_r_reg_n_0_[2] ),\n .Q(match_flag_pb[16]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[2].match_flag_pb_reg[17] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[16]),\n .Q(match_flag_pb[17]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[2].match_flag_pb_reg[18] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[17]),\n .Q(match_flag_pb[18]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[2].match_flag_pb_reg[19] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[18]),\n .Q(match_flag_pb[19]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[2].match_flag_pb_reg[20] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[19]),\n .Q(match_flag_pb[20]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[2].match_flag_pb_reg[21] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[20]),\n .Q(match_flag_pb[21]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[2].match_flag_pb_reg[22] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[21]),\n .Q(match_flag_pb[22]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[2].match_flag_pb_reg[23] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[22]),\n .Q(match_flag_pb[23]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDRE \\genblk8[2].right_edge_found_pb_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[2].right_edge_found_pb_reg[2]_0 ),\n .Q(\\genblk8[2].right_edge_pb_reg[12]_0 ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAABAAAAAAAAA)) \n \\genblk8[2].right_edge_pb[17]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(\\genblk8[2].right_edge_pb_reg[12]_2 ),\n .I2(p_154_out),\n .I3(\\genblk8[2].right_edge_pb_reg[12]_1 ),\n .I4(\\genblk8[2].right_edge_pb_reg[12]_0 ),\n .I5(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .O(\\genblk8[2].right_edge_pb[17]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h08)) \n \\genblk8[2].right_edge_pb[17]_i_2 \n (.I0(p_154_out),\n .I1(\\genblk8[2].right_edge_pb_reg[12]_1 ),\n .I2(\\genblk8[2].right_edge_pb_reg[12]_2 ),\n .O(\\genblk8[2].right_edge_pb[17]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\genblk8[2].right_edge_pb[17]_i_3 \n (.I0(\\genblk7[2].compare_err_pb_latch_r_reg_n_0_[2] ),\n .I1(\\genblk8[2].left_edge_pb[17]_i_3_n_0 ),\n .I2(match_flag_pb[23]),\n .I3(match_flag_pb[22]),\n .I4(match_flag_pb[20]),\n .I5(match_flag_pb[21]),\n .O(\\genblk8[2].right_edge_pb_reg[12]_1 ));\n FDSE \\genblk8[2].right_edge_pb_reg[12] \n (.C(CLK),\n .CE(\\genblk8[2].right_edge_pb[17]_i_2_n_0 ),\n .D(\\genblk8[0].left_edge_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[2].right_edge_pb_reg_n_0_[12] ),\n .S(\\genblk8[2].right_edge_pb[17]_i_1_n_0 ));\n FDSE \\genblk8[2].right_edge_pb_reg[13] \n (.C(CLK),\n .CE(\\genblk8[2].right_edge_pb[17]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[2].right_edge_pb_reg_n_0_[13] ),\n .S(\\genblk8[2].right_edge_pb[17]_i_1_n_0 ));\n FDSE \\genblk8[2].right_edge_pb_reg[14] \n (.C(CLK),\n .CE(\\genblk8[2].right_edge_pb[17]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[2].right_edge_pb_reg_n_0_[14] ),\n .S(\\genblk8[2].right_edge_pb[17]_i_1_n_0 ));\n FDSE \\genblk8[2].right_edge_pb_reg[15] \n (.C(CLK),\n .CE(\\genblk8[2].right_edge_pb[17]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[2].right_edge_pb_reg_n_0_[15] ),\n .S(\\genblk8[2].right_edge_pb[17]_i_1_n_0 ));\n FDSE \\genblk8[2].right_edge_pb_reg[16] \n (.C(CLK),\n .CE(\\genblk8[2].right_edge_pb[17]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[2].right_edge_pb_reg_n_0_[16] ),\n .S(\\genblk8[2].right_edge_pb[17]_i_1_n_0 ));\n FDSE \\genblk8[2].right_edge_pb_reg[17] \n (.C(CLK),\n .CE(\\genblk8[2].right_edge_pb[17]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[5]_i_3_n_0 ),\n .Q(\\genblk8[2].right_edge_pb_reg_n_0_[17] ),\n .S(\\genblk8[2].right_edge_pb[17]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[2].right_gain_pb[12]_i_1 \n (.I0(\\genblk8[2].right_edge_pb_reg[12]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[2].right_gain_pb_reg[15]_i_2_n_7 ),\n .I3(\\genblk8[2].right_gain_pb_reg[15]_i_3_n_7 ),\n .O(\\genblk8[2].right_gain_pb[12]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[2].right_gain_pb[13]_i_1 \n (.I0(\\genblk8[2].right_edge_pb_reg[12]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[2].right_gain_pb_reg[15]_i_2_n_6 ),\n .I3(\\genblk8[2].right_gain_pb_reg[15]_i_3_n_6 ),\n .O(\\genblk8[2].right_gain_pb[13]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[2].right_gain_pb[14]_i_1 \n (.I0(\\genblk8[2].right_edge_pb_reg[12]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[2].right_gain_pb_reg[15]_i_2_n_5 ),\n .I3(\\genblk8[2].right_gain_pb_reg[15]_i_3_n_5 ),\n .O(\\genblk8[2].right_gain_pb[14]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[2].right_gain_pb[15]_i_1 \n (.I0(\\genblk8[2].right_edge_pb_reg[12]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[2].right_gain_pb_reg[15]_i_2_n_4 ),\n .I3(\\genblk8[2].right_gain_pb_reg[15]_i_3_n_4 ),\n .O(\\genblk8[2].right_gain_pb[15]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[2].right_gain_pb[15]_i_10 \n (.I0(right_edge_ref[1]),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[13] ),\n .O(\\genblk8[2].right_gain_pb[15]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[2].right_gain_pb[15]_i_11 \n (.I0(right_edge_ref[0]),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[12] ),\n .O(\\genblk8[2].right_gain_pb[15]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[2].right_gain_pb[15]_i_4 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[15] ),\n .O(\\genblk8[2].right_gain_pb[15]_i_4_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[2].right_gain_pb[15]_i_5 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[14] ),\n .O(\\genblk8[2].right_gain_pb[15]_i_5_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[2].right_gain_pb[15]_i_6 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[13] ),\n .O(\\genblk8[2].right_gain_pb[15]_i_6_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[2].right_gain_pb[15]_i_7 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[12] ),\n .O(\\genblk8[2].right_gain_pb[15]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[2].right_gain_pb[15]_i_8 \n (.I0(right_edge_ref[3]),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[15] ),\n .O(\\genblk8[2].right_gain_pb[15]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[2].right_gain_pb[15]_i_9 \n (.I0(right_edge_ref[2]),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[14] ),\n .O(\\genblk8[2].right_gain_pb[15]_i_9_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[2].right_gain_pb[16]_i_1 \n (.I0(\\genblk8[2].right_edge_pb_reg[12]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[2].right_gain_pb_reg[17]_i_5_n_7 ),\n .I3(\\genblk8[2].right_gain_pb_reg[17]_i_6_n_7 ),\n .O(\\genblk8[2].right_gain_pb[16]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAEFEAEAE)) \n \\genblk8[2].right_gain_pb[17]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(right_gain_pb),\n .I2(p_154_out),\n .I3(\\genblk8[2].right_edge_pb_reg[12]_2 ),\n .I4(\\genblk8[2].right_gain_pb_reg[17]_i_4_n_0 ),\n .O(\\genblk8[2].right_gain_pb[17]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[2].right_gain_pb[17]_i_10 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[16] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[2].right_gain_pb[17]_i_11 \n (.I0(right_edge_ref[5]),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[17] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[2].right_gain_pb[17]_i_12 \n (.I0(right_edge_ref[4]),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[16] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_12_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk8[2].right_gain_pb[17]_i_13 \n (.I0(\\genblk8[2].right_gain_pb[17]_i_16_n_0 ),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[15] ),\n .I2(right_edge_ref[3]),\n .I3(\\genblk8[2].right_edge_pb_reg_n_0_[16] ),\n .I4(right_edge_ref[4]),\n .O(\\genblk8[2].right_gain_pb[17]_i_13_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk8[2].right_gain_pb[17]_i_14 \n (.I0(\\genblk8[2].right_gain_pb[17]_i_17_n_0 ),\n .I1(right_edge_ref[3]),\n .I2(\\genblk8[2].right_edge_pb_reg_n_0_[15] ),\n .I3(right_edge_ref[4]),\n .I4(\\genblk8[2].right_edge_pb_reg_n_0_[16] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk8[2].right_gain_pb[17]_i_16 \n (.I0(right_edge_ref[0]),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[12] ),\n .I2(\\genblk8[2].right_edge_pb_reg_n_0_[13] ),\n .I3(right_edge_ref[1]),\n .I4(\\genblk8[2].right_edge_pb_reg_n_0_[14] ),\n .I5(right_edge_ref[2]),\n .O(\\genblk8[2].right_gain_pb[17]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk8[2].right_gain_pb[17]_i_17 \n (.I0(\\genblk8[2].right_edge_pb_reg_n_0_[12] ),\n .I1(right_edge_ref[0]),\n .I2(right_edge_ref[1]),\n .I3(\\genblk8[2].right_edge_pb_reg_n_0_[13] ),\n .I4(right_edge_ref[2]),\n .I5(\\genblk8[2].right_edge_pb_reg_n_0_[14] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[2].right_gain_pb[17]_i_19 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_19_n_0 ));\n LUT5 #(\n .INIT(32'h000000A8)) \n \\genblk8[2].right_gain_pb[17]_i_2 \n (.I0(p_154_out),\n .I1(\\genblk8[2].right_edge_pb_reg[12]_1 ),\n .I2(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .I3(\\genblk8[2].right_edge_pb_reg[12]_0 ),\n .I4(\\genblk8[2].right_edge_pb_reg[12]_2 ),\n .O(\\genblk8[2].right_gain_pb[17]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[2].right_gain_pb[17]_i_20 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[2].right_gain_pb[17]_i_21 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_21_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[2].right_gain_pb[17]_i_22 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_22_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[2].right_gain_pb[17]_i_24 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_24_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[2].right_gain_pb[17]_i_25 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_25_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[2].right_gain_pb[17]_i_26 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_26_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[2].right_gain_pb[17]_i_27 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_27_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[2].right_gain_pb[17]_i_29 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_29_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[2].right_gain_pb[17]_i_3 \n (.I0(\\genblk8[2].right_edge_pb_reg[12]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[2].right_gain_pb_reg[17]_i_5_n_6 ),\n .I3(\\genblk8[2].right_gain_pb_reg[17]_i_6_n_6 ),\n .O(\\genblk8[2].right_gain_pb[17]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[2].right_gain_pb[17]_i_30 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_30_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[2].right_gain_pb[17]_i_31 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_31_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[2].right_gain_pb[17]_i_32 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_32_n_0 ));\n LUT4 #(\n .INIT(16'hF880)) \n \\genblk8[2].right_gain_pb[17]_i_33 \n (.I0(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[16] ),\n .I2(\\genblk8[2].right_edge_pb_reg_n_0_[17] ),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[2].right_gain_pb[17]_i_33_n_0 ));\n LUT6 #(\n .INIT(64'h0808088CCECECEE0)) \n \\genblk8[2].right_gain_pb[17]_i_34 \n (.I0(\\genblk8[2].right_edge_pb_reg_n_0_[14] ),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[15] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[2].right_gain_pb[17]_i_34_n_0 ));\n LUT4 #(\n .INIT(16'h8CE0)) \n \\genblk8[2].right_gain_pb[17]_i_35 \n (.I0(\\genblk8[2].right_edge_pb_reg_n_0_[12] ),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[13] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\genblk8[2].right_gain_pb[17]_i_35_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[2].right_gain_pb[17]_i_36 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_36_n_0 ));\n LUT4 #(\n .INIT(16'h0660)) \n \\genblk8[2].right_gain_pb[17]_i_37 \n (.I0(\\genblk8[2].right_edge_pb_reg_n_0_[16] ),\n .I1(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I2(\\genblk8[2].right_edge_pb_reg_n_0_[17] ),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[2].right_gain_pb[17]_i_37_n_0 ));\n LUT6 #(\n .INIT(64'h8484844221212118)) \n \\genblk8[2].right_gain_pb[17]_i_38 \n (.I0(\\genblk8[2].right_edge_pb_reg_n_0_[14] ),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[15] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[2].right_gain_pb[17]_i_38_n_0 ));\n LUT4 #(\n .INIT(16'h4218)) \n \\genblk8[2].right_gain_pb[17]_i_39 \n (.I0(\\genblk8[2].right_edge_pb_reg_n_0_[12] ),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[13] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\genblk8[2].right_gain_pb[17]_i_39_n_0 ));\n LUT5 #(\n .INIT(32'h04004404)) \n \\genblk8[2].right_gain_pb[17]_i_7 \n (.I0(\\genblk8[2].right_edge_pb_reg[12]_0 ),\n .I1(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .I2(right_edge_ref[5]),\n .I3(\\genblk8[2].right_edge_pb_reg_n_0_[17] ),\n .I4(\\genblk8[2].right_gain_pb[17]_i_13_n_0 ),\n .O(\\genblk8[2].right_gain_pb[17]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FFB200B2)) \n \\genblk8[2].right_gain_pb[17]_i_8 \n (.I0(\\genblk8[2].right_edge_pb_reg_n_0_[17] ),\n .I1(right_edge_ref[5]),\n .I2(\\genblk8[2].right_gain_pb[17]_i_14_n_0 ),\n .I3(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I4(\\genblk8[2].right_gain_pb_reg[17]_i_15_n_0 ),\n .I5(\\genblk8[2].right_edge_pb_reg[12]_0 ),\n .O(\\genblk8[2].right_gain_pb[17]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[2].right_gain_pb[17]_i_9 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .I1(\\genblk8[2].right_edge_pb_reg_n_0_[17] ),\n .O(\\genblk8[2].right_gain_pb[17]_i_9_n_0 ));\n FDRE \\genblk8[2].right_gain_pb_reg[12] \n (.C(CLK),\n .CE(\\genblk8[2].right_gain_pb[17]_i_2_n_0 ),\n .D(\\genblk8[2].right_gain_pb[12]_i_1_n_0 ),\n .Q(\\genblk8[2].right_gain_pb_reg_n_0_[12] ),\n .R(\\genblk8[2].right_gain_pb[17]_i_1_n_0 ));\n FDRE \\genblk8[2].right_gain_pb_reg[13] \n (.C(CLK),\n .CE(\\genblk8[2].right_gain_pb[17]_i_2_n_0 ),\n .D(\\genblk8[2].right_gain_pb[13]_i_1_n_0 ),\n .Q(\\genblk8[2].right_gain_pb_reg_n_0_[13] ),\n .R(\\genblk8[2].right_gain_pb[17]_i_1_n_0 ));\n FDRE \\genblk8[2].right_gain_pb_reg[14] \n (.C(CLK),\n .CE(\\genblk8[2].right_gain_pb[17]_i_2_n_0 ),\n .D(\\genblk8[2].right_gain_pb[14]_i_1_n_0 ),\n .Q(\\genblk8[2].right_gain_pb_reg__0 [2]),\n .R(\\genblk8[2].right_gain_pb[17]_i_1_n_0 ));\n FDRE \\genblk8[2].right_gain_pb_reg[15] \n (.C(CLK),\n .CE(\\genblk8[2].right_gain_pb[17]_i_2_n_0 ),\n .D(\\genblk8[2].right_gain_pb[15]_i_1_n_0 ),\n .Q(\\genblk8[2].right_gain_pb_reg__0 [3]),\n .R(\\genblk8[2].right_gain_pb[17]_i_1_n_0 ));\n CARRY4 \\genblk8[2].right_gain_pb_reg[15]_i_2 \n (.CI(1'b0),\n .CO({\\genblk8[2].right_gain_pb_reg[15]_i_2_n_0 ,\\genblk8[2].right_gain_pb_reg[15]_i_2_n_1 ,\\genblk8[2].right_gain_pb_reg[15]_i_2_n_2 ,\\genblk8[2].right_gain_pb_reg[15]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ,\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ,\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ,\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }),\n .O({\\genblk8[2].right_gain_pb_reg[15]_i_2_n_4 ,\\genblk8[2].right_gain_pb_reg[15]_i_2_n_5 ,\\genblk8[2].right_gain_pb_reg[15]_i_2_n_6 ,\\genblk8[2].right_gain_pb_reg[15]_i_2_n_7 }),\n .S({\\genblk8[2].right_gain_pb[15]_i_4_n_0 ,\\genblk8[2].right_gain_pb[15]_i_5_n_0 ,\\genblk8[2].right_gain_pb[15]_i_6_n_0 ,\\genblk8[2].right_gain_pb[15]_i_7_n_0 }));\n CARRY4 \\genblk8[2].right_gain_pb_reg[15]_i_3 \n (.CI(1'b0),\n .CO({\\genblk8[2].right_gain_pb_reg[15]_i_3_n_0 ,\\genblk8[2].right_gain_pb_reg[15]_i_3_n_1 ,\\genblk8[2].right_gain_pb_reg[15]_i_3_n_2 ,\\genblk8[2].right_gain_pb_reg[15]_i_3_n_3 }),\n .CYINIT(1'b1),\n .DI(right_edge_ref[3:0]),\n .O({\\genblk8[2].right_gain_pb_reg[15]_i_3_n_4 ,\\genblk8[2].right_gain_pb_reg[15]_i_3_n_5 ,\\genblk8[2].right_gain_pb_reg[15]_i_3_n_6 ,\\genblk8[2].right_gain_pb_reg[15]_i_3_n_7 }),\n .S({\\genblk8[2].right_gain_pb[15]_i_8_n_0 ,\\genblk8[2].right_gain_pb[15]_i_9_n_0 ,\\genblk8[2].right_gain_pb[15]_i_10_n_0 ,\\genblk8[2].right_gain_pb[15]_i_11_n_0 }));\n FDRE \\genblk8[2].right_gain_pb_reg[16] \n (.C(CLK),\n .CE(\\genblk8[2].right_gain_pb[17]_i_2_n_0 ),\n .D(\\genblk8[2].right_gain_pb[16]_i_1_n_0 ),\n .Q(\\genblk8[2].right_gain_pb_reg__0 [4]),\n .R(\\genblk8[2].right_gain_pb[17]_i_1_n_0 ));\n FDRE \\genblk8[2].right_gain_pb_reg[17] \n (.C(CLK),\n .CE(\\genblk8[2].right_gain_pb[17]_i_2_n_0 ),\n .D(\\genblk8[2].right_gain_pb[17]_i_3_n_0 ),\n .Q(\\genblk8[2].right_gain_pb_reg__0 [5]),\n .R(\\genblk8[2].right_gain_pb[17]_i_1_n_0 ));\n CARRY4 \\genblk8[2].right_gain_pb_reg[17]_i_15 \n (.CI(\\genblk8[2].right_gain_pb_reg[17]_i_18_n_0 ),\n .CO({\\genblk8[2].right_gain_pb_reg[17]_i_15_n_0 ,\\genblk8[2].right_gain_pb_reg[17]_i_15_n_1 ,\\genblk8[2].right_gain_pb_reg[17]_i_15_n_2 ,\\genblk8[2].right_gain_pb_reg[17]_i_15_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[2].right_gain_pb_reg[17]_i_15_O_UNCONNECTED [3:0]),\n .S({\\genblk8[2].right_gain_pb[17]_i_19_n_0 ,\\genblk8[2].right_gain_pb[17]_i_20_n_0 ,\\genblk8[2].right_gain_pb[17]_i_21_n_0 ,\\genblk8[2].right_gain_pb[17]_i_22_n_0 }));\n CARRY4 \\genblk8[2].right_gain_pb_reg[17]_i_18 \n (.CI(\\genblk8[2].right_gain_pb_reg[17]_i_23_n_0 ),\n .CO({\\genblk8[2].right_gain_pb_reg[17]_i_18_n_0 ,\\genblk8[2].right_gain_pb_reg[17]_i_18_n_1 ,\\genblk8[2].right_gain_pb_reg[17]_i_18_n_2 ,\\genblk8[2].right_gain_pb_reg[17]_i_18_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[2].right_gain_pb_reg[17]_i_18_O_UNCONNECTED [3:0]),\n .S({\\genblk8[2].right_gain_pb[17]_i_24_n_0 ,\\genblk8[2].right_gain_pb[17]_i_25_n_0 ,\\genblk8[2].right_gain_pb[17]_i_26_n_0 ,\\genblk8[2].right_gain_pb[17]_i_27_n_0 }));\n CARRY4 \\genblk8[2].right_gain_pb_reg[17]_i_23 \n (.CI(\\genblk8[2].right_gain_pb_reg[17]_i_28_n_0 ),\n .CO({\\genblk8[2].right_gain_pb_reg[17]_i_23_n_0 ,\\genblk8[2].right_gain_pb_reg[17]_i_23_n_1 ,\\genblk8[2].right_gain_pb_reg[17]_i_23_n_2 ,\\genblk8[2].right_gain_pb_reg[17]_i_23_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[2].right_gain_pb_reg[17]_i_23_O_UNCONNECTED [3:0]),\n .S({\\genblk8[2].right_gain_pb[17]_i_29_n_0 ,\\genblk8[2].right_gain_pb[17]_i_30_n_0 ,\\genblk8[2].right_gain_pb[17]_i_31_n_0 ,\\genblk8[2].right_gain_pb[17]_i_32_n_0 }));\n CARRY4 \\genblk8[2].right_gain_pb_reg[17]_i_28 \n (.CI(1'b0),\n .CO({\\genblk8[2].right_gain_pb_reg[17]_i_28_n_0 ,\\genblk8[2].right_gain_pb_reg[17]_i_28_n_1 ,\\genblk8[2].right_gain_pb_reg[17]_i_28_n_2 ,\\genblk8[2].right_gain_pb_reg[17]_i_28_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,\\genblk8[2].right_gain_pb[17]_i_33_n_0 ,\\genblk8[2].right_gain_pb[17]_i_34_n_0 ,\\genblk8[2].right_gain_pb[17]_i_35_n_0 }),\n .O(\\NLW_genblk8[2].right_gain_pb_reg[17]_i_28_O_UNCONNECTED [3:0]),\n .S({\\genblk8[2].right_gain_pb[17]_i_36_n_0 ,\\genblk8[2].right_gain_pb[17]_i_37_n_0 ,\\genblk8[2].right_gain_pb[17]_i_38_n_0 ,\\genblk8[2].right_gain_pb[17]_i_39_n_0 }));\n MUXF7 \\genblk8[2].right_gain_pb_reg[17]_i_4 \n (.I0(\\genblk8[2].right_gain_pb[17]_i_7_n_0 ),\n .I1(\\genblk8[2].right_gain_pb[17]_i_8_n_0 ),\n .O(\\genblk8[2].right_gain_pb_reg[17]_i_4_n_0 ),\n .S(\\genblk8[2].right_edge_pb_reg[12]_1 ));\n CARRY4 \\genblk8[2].right_gain_pb_reg[17]_i_5 \n (.CI(\\genblk8[2].right_gain_pb_reg[15]_i_2_n_0 ),\n .CO({\\NLW_genblk8[2].right_gain_pb_reg[17]_i_5_CO_UNCONNECTED [3:1],\\genblk8[2].right_gain_pb_reg[17]_i_5_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,\\prbs_dqs_tap_cnt_r_reg_n_0_[4] }),\n .O({\\NLW_genblk8[2].right_gain_pb_reg[17]_i_5_O_UNCONNECTED [3:2],\\genblk8[2].right_gain_pb_reg[17]_i_5_n_6 ,\\genblk8[2].right_gain_pb_reg[17]_i_5_n_7 }),\n .S({1'b0,1'b0,\\genblk8[2].right_gain_pb[17]_i_9_n_0 ,\\genblk8[2].right_gain_pb[17]_i_10_n_0 }));\n CARRY4 \\genblk8[2].right_gain_pb_reg[17]_i_6 \n (.CI(\\genblk8[2].right_gain_pb_reg[15]_i_3_n_0 ),\n .CO({\\NLW_genblk8[2].right_gain_pb_reg[17]_i_6_CO_UNCONNECTED [3:1],\\genblk8[2].right_gain_pb_reg[17]_i_6_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,right_edge_ref[4]}),\n .O({\\NLW_genblk8[2].right_gain_pb_reg[17]_i_6_O_UNCONNECTED [3:2],\\genblk8[2].right_gain_pb_reg[17]_i_6_n_6 ,\\genblk8[2].right_gain_pb_reg[17]_i_6_n_7 }),\n .S({1'b0,1'b0,\\genblk8[2].right_gain_pb[17]_i_11_n_0 ,\\genblk8[2].right_gain_pb[17]_i_12_n_0 }));\n FDRE \\genblk8[3].left_edge_found_pb_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[3].left_edge_found_pb_reg[3]_0 ),\n .Q(\\genblk8[3].left_loss_pb_reg[18]_0 ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\genblk8[3].left_edge_pb[23]_i_1 \n (.I0(p_154_out),\n .I1(p_130_out),\n .O(\\genblk8[3].left_edge_pb[23]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\genblk8[3].left_edge_pb[23]_i_2 \n (.I0(match_flag_pb[31]),\n .I1(\\genblk8[3].left_edge_pb[23]_i_3_n_0 ),\n .I2(\\genblk7[3].compare_err_pb_latch_r_reg_n_0_[3] ),\n .I3(match_flag_pb[30]),\n .I4(match_flag_pb[28]),\n .I5(match_flag_pb[29]),\n .O(p_130_out));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\genblk8[3].left_edge_pb[23]_i_3 \n (.I0(match_flag_pb[26]),\n .I1(match_flag_pb[27]),\n .I2(match_flag_pb[24]),\n .I3(match_flag_pb[25]),\n .O(\\genblk8[3].left_edge_pb[23]_i_3_n_0 ));\n FDRE \\genblk8[3].left_edge_pb_reg[18] \n (.C(CLK),\n .CE(\\genblk8[3].left_edge_pb[23]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[3].left_edge_pb_reg_n_0_[18] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[3].left_edge_pb_reg[19] \n (.C(CLK),\n .CE(\\genblk8[3].left_edge_pb[23]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[3].left_edge_pb_reg_n_0_[19] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[3].left_edge_pb_reg[20] \n (.C(CLK),\n .CE(\\genblk8[3].left_edge_pb[23]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[3].left_edge_pb_reg_n_0_[20] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[3].left_edge_pb_reg[21] \n (.C(CLK),\n .CE(\\genblk8[3].left_edge_pb[23]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[3].left_edge_pb_reg_n_0_[21] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[3].left_edge_pb_reg[22] \n (.C(CLK),\n .CE(\\genblk8[3].left_edge_pb[23]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[3].left_edge_pb_reg_n_0_[22] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[3].left_edge_pb_reg[23] \n (.C(CLK),\n .CE(\\genblk8[3].left_edge_pb[23]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[5]_i_3_n_0 ),\n .Q(\\genblk8[3].left_edge_pb_reg_n_0_[23] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[3].left_edge_updated_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[3].left_edge_updated_reg[3]_0 ),\n .Q(D[3]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAEFEAEAE)) \n \\genblk8[3].left_loss_pb[23]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(right_gain_pb),\n .I2(p_154_out),\n .I3(\\genblk8[3].left_loss_pb_reg[18]_0 ),\n .I4(p_130_out),\n .O(\\genblk8[3].left_loss_pb[23]_i_1_n_0 ));\n FDRE \\genblk8[3].left_loss_pb_reg[18] \n (.C(CLK),\n .CE(\\genblk8[3].left_loss_pb[23]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[3].left_loss_pb_reg_n_0_[18] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[3].left_loss_pb_reg[19] \n (.C(CLK),\n .CE(\\genblk8[3].left_loss_pb[23]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[3].left_loss_pb_reg_n_0_[19] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[3].left_loss_pb_reg[20] \n (.C(CLK),\n .CE(\\genblk8[3].left_loss_pb[23]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[3].left_loss_pb_reg__0 [2]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[3].left_loss_pb_reg[21] \n (.C(CLK),\n .CE(\\genblk8[3].left_loss_pb[23]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[3].left_loss_pb_reg__0 [3]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[3].left_loss_pb_reg[22] \n (.C(CLK),\n .CE(\\genblk8[3].left_loss_pb[23]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[3].left_loss_pb_reg__0 [4]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[3].left_loss_pb_reg[23] \n (.C(CLK),\n .CE(\\genblk8[3].left_loss_pb[23]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[5]_i_2_n_0 ),\n .Q(\\genblk8[3].left_loss_pb_reg__0 [5]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDSE \\genblk8[3].match_flag_pb_reg[24] \n (.C(CLK),\n .CE(p_154_out),\n .D(\\genblk7[3].compare_err_pb_latch_r_reg_n_0_[3] ),\n .Q(match_flag_pb[24]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[3].match_flag_pb_reg[25] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[24]),\n .Q(match_flag_pb[25]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[3].match_flag_pb_reg[26] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[25]),\n .Q(match_flag_pb[26]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[3].match_flag_pb_reg[27] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[26]),\n .Q(match_flag_pb[27]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[3].match_flag_pb_reg[28] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[27]),\n .Q(match_flag_pb[28]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[3].match_flag_pb_reg[29] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[28]),\n .Q(match_flag_pb[29]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[3].match_flag_pb_reg[30] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[29]),\n .Q(match_flag_pb[30]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[3].match_flag_pb_reg[31] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[30]),\n .Q(match_flag_pb[31]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDRE \\genblk8[3].right_edge_found_pb_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[3].right_edge_found_pb_reg[3]_0 ),\n .Q(\\genblk8[3].right_edge_pb_reg[18]_0 ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAABAAAAAAAAA)) \n \\genblk8[3].right_edge_pb[23]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(p_130_out),\n .I2(p_154_out),\n .I3(p_127_out),\n .I4(\\genblk8[3].right_edge_pb_reg[18]_0 ),\n .I5(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .O(\\genblk8[3].right_edge_pb[23]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h08)) \n \\genblk8[3].right_edge_pb[23]_i_2 \n (.I0(p_154_out),\n .I1(p_127_out),\n .I2(p_130_out),\n .O(\\genblk8[3].right_edge_pb[23]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\genblk8[3].right_edge_pb[23]_i_3 \n (.I0(\\genblk7[3].compare_err_pb_latch_r_reg_n_0_[3] ),\n .I1(\\genblk8[3].left_edge_pb[23]_i_3_n_0 ),\n .I2(match_flag_pb[31]),\n .I3(match_flag_pb[30]),\n .I4(match_flag_pb[28]),\n .I5(match_flag_pb[29]),\n .O(p_127_out));\n FDSE \\genblk8[3].right_edge_pb_reg[18] \n (.C(CLK),\n .CE(\\genblk8[3].right_edge_pb[23]_i_2_n_0 ),\n .D(\\genblk8[0].left_edge_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[3].right_edge_pb_reg_n_0_[18] ),\n .S(\\genblk8[3].right_edge_pb[23]_i_1_n_0 ));\n FDSE \\genblk8[3].right_edge_pb_reg[19] \n (.C(CLK),\n .CE(\\genblk8[3].right_edge_pb[23]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[3].right_edge_pb_reg_n_0_[19] ),\n .S(\\genblk8[3].right_edge_pb[23]_i_1_n_0 ));\n FDSE \\genblk8[3].right_edge_pb_reg[20] \n (.C(CLK),\n .CE(\\genblk8[3].right_edge_pb[23]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[3].right_edge_pb_reg_n_0_[20] ),\n .S(\\genblk8[3].right_edge_pb[23]_i_1_n_0 ));\n FDSE \\genblk8[3].right_edge_pb_reg[21] \n (.C(CLK),\n .CE(\\genblk8[3].right_edge_pb[23]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[3].right_edge_pb_reg_n_0_[21] ),\n .S(\\genblk8[3].right_edge_pb[23]_i_1_n_0 ));\n FDSE \\genblk8[3].right_edge_pb_reg[22] \n (.C(CLK),\n .CE(\\genblk8[3].right_edge_pb[23]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[3].right_edge_pb_reg_n_0_[22] ),\n .S(\\genblk8[3].right_edge_pb[23]_i_1_n_0 ));\n FDSE \\genblk8[3].right_edge_pb_reg[23] \n (.C(CLK),\n .CE(\\genblk8[3].right_edge_pb[23]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[5]_i_3_n_0 ),\n .Q(\\genblk8[3].right_edge_pb_reg_n_0_[23] ),\n .S(\\genblk8[3].right_edge_pb[23]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[3].right_gain_pb[18]_i_1 \n (.I0(p_127_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[3].right_gain_pb_reg[21]_i_2_n_7 ),\n .I3(\\genblk8[3].right_gain_pb_reg[21]_i_3_n_7 ),\n .O(\\genblk8[3].right_gain_pb[18]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[3].right_gain_pb[19]_i_1 \n (.I0(p_127_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[3].right_gain_pb_reg[21]_i_2_n_6 ),\n .I3(\\genblk8[3].right_gain_pb_reg[21]_i_3_n_6 ),\n .O(\\genblk8[3].right_gain_pb[19]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[3].right_gain_pb[20]_i_1 \n (.I0(p_127_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[3].right_gain_pb_reg[21]_i_2_n_5 ),\n .I3(\\genblk8[3].right_gain_pb_reg[21]_i_3_n_5 ),\n .O(\\genblk8[3].right_gain_pb[20]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[3].right_gain_pb[21]_i_1 \n (.I0(p_127_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[3].right_gain_pb_reg[21]_i_2_n_4 ),\n .I3(\\genblk8[3].right_gain_pb_reg[21]_i_3_n_4 ),\n .O(\\genblk8[3].right_gain_pb[21]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[3].right_gain_pb[21]_i_10 \n (.I0(right_edge_ref[1]),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[19] ),\n .O(\\genblk8[3].right_gain_pb[21]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[3].right_gain_pb[21]_i_11 \n (.I0(right_edge_ref[0]),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[18] ),\n .O(\\genblk8[3].right_gain_pb[21]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[3].right_gain_pb[21]_i_4 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[21] ),\n .O(\\genblk8[3].right_gain_pb[21]_i_4_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[3].right_gain_pb[21]_i_5 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[20] ),\n .O(\\genblk8[3].right_gain_pb[21]_i_5_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[3].right_gain_pb[21]_i_6 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[19] ),\n .O(\\genblk8[3].right_gain_pb[21]_i_6_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[3].right_gain_pb[21]_i_7 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[18] ),\n .O(\\genblk8[3].right_gain_pb[21]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[3].right_gain_pb[21]_i_8 \n (.I0(right_edge_ref[3]),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[21] ),\n .O(\\genblk8[3].right_gain_pb[21]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[3].right_gain_pb[21]_i_9 \n (.I0(right_edge_ref[2]),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[20] ),\n .O(\\genblk8[3].right_gain_pb[21]_i_9_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[3].right_gain_pb[22]_i_1 \n (.I0(p_127_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[3].right_gain_pb_reg[23]_i_5_n_7 ),\n .I3(\\genblk8[3].right_gain_pb_reg[23]_i_6_n_7 ),\n .O(\\genblk8[3].right_gain_pb[22]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAEFEAEAE)) \n \\genblk8[3].right_gain_pb[23]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(right_gain_pb),\n .I2(p_154_out),\n .I3(p_130_out),\n .I4(\\genblk8[3].right_gain_pb_reg[23]_i_4_n_0 ),\n .O(\\genblk8[3].right_gain_pb[23]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[3].right_gain_pb[23]_i_10 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[22] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[3].right_gain_pb[23]_i_11 \n (.I0(right_edge_ref[5]),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[23] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[3].right_gain_pb[23]_i_12 \n (.I0(right_edge_ref[4]),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[22] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_12_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk8[3].right_gain_pb[23]_i_13 \n (.I0(\\genblk8[3].right_gain_pb[23]_i_16_n_0 ),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[21] ),\n .I2(right_edge_ref[3]),\n .I3(\\genblk8[3].right_edge_pb_reg_n_0_[22] ),\n .I4(right_edge_ref[4]),\n .O(\\genblk8[3].right_gain_pb[23]_i_13_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk8[3].right_gain_pb[23]_i_14 \n (.I0(\\genblk8[3].right_gain_pb[23]_i_17_n_0 ),\n .I1(right_edge_ref[3]),\n .I2(\\genblk8[3].right_edge_pb_reg_n_0_[21] ),\n .I3(right_edge_ref[4]),\n .I4(\\genblk8[3].right_edge_pb_reg_n_0_[22] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk8[3].right_gain_pb[23]_i_16 \n (.I0(right_edge_ref[0]),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[18] ),\n .I2(\\genblk8[3].right_edge_pb_reg_n_0_[19] ),\n .I3(right_edge_ref[1]),\n .I4(\\genblk8[3].right_edge_pb_reg_n_0_[20] ),\n .I5(right_edge_ref[2]),\n .O(\\genblk8[3].right_gain_pb[23]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk8[3].right_gain_pb[23]_i_17 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[18] ),\n .I1(right_edge_ref[0]),\n .I2(right_edge_ref[1]),\n .I3(\\genblk8[3].right_edge_pb_reg_n_0_[19] ),\n .I4(right_edge_ref[2]),\n .I5(\\genblk8[3].right_edge_pb_reg_n_0_[20] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[3].right_gain_pb[23]_i_19 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_19_n_0 ));\n LUT5 #(\n .INIT(32'h000000A8)) \n \\genblk8[3].right_gain_pb[23]_i_2 \n (.I0(p_154_out),\n .I1(p_127_out),\n .I2(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .I3(\\genblk8[3].right_edge_pb_reg[18]_0 ),\n .I4(p_130_out),\n .O(\\genblk8[3].right_gain_pb[23]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[3].right_gain_pb[23]_i_20 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[3].right_gain_pb[23]_i_21 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_21_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[3].right_gain_pb[23]_i_22 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_22_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[3].right_gain_pb[23]_i_24 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_24_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[3].right_gain_pb[23]_i_25 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_25_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[3].right_gain_pb[23]_i_26 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_26_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[3].right_gain_pb[23]_i_27 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_27_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[3].right_gain_pb[23]_i_29 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_29_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[3].right_gain_pb[23]_i_3 \n (.I0(p_127_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[3].right_gain_pb_reg[23]_i_5_n_6 ),\n .I3(\\genblk8[3].right_gain_pb_reg[23]_i_6_n_6 ),\n .O(\\genblk8[3].right_gain_pb[23]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[3].right_gain_pb[23]_i_30 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_30_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[3].right_gain_pb[23]_i_31 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_31_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[3].right_gain_pb[23]_i_32 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_32_n_0 ));\n LUT4 #(\n .INIT(16'hF880)) \n \\genblk8[3].right_gain_pb[23]_i_33 \n (.I0(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[22] ),\n .I2(\\genblk8[3].right_edge_pb_reg_n_0_[23] ),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[3].right_gain_pb[23]_i_33_n_0 ));\n LUT6 #(\n .INIT(64'h0808088CCECECEE0)) \n \\genblk8[3].right_gain_pb[23]_i_34 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[20] ),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[21] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[3].right_gain_pb[23]_i_34_n_0 ));\n LUT4 #(\n .INIT(16'h8CE0)) \n \\genblk8[3].right_gain_pb[23]_i_35 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[18] ),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[19] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\genblk8[3].right_gain_pb[23]_i_35_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[3].right_gain_pb[23]_i_36 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_36_n_0 ));\n LUT4 #(\n .INIT(16'h0660)) \n \\genblk8[3].right_gain_pb[23]_i_37 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[22] ),\n .I1(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I2(\\genblk8[3].right_edge_pb_reg_n_0_[23] ),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[3].right_gain_pb[23]_i_37_n_0 ));\n LUT6 #(\n .INIT(64'h8484844221212118)) \n \\genblk8[3].right_gain_pb[23]_i_38 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[20] ),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[21] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[3].right_gain_pb[23]_i_38_n_0 ));\n LUT4 #(\n .INIT(16'h4218)) \n \\genblk8[3].right_gain_pb[23]_i_39 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[18] ),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[19] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\genblk8[3].right_gain_pb[23]_i_39_n_0 ));\n LUT5 #(\n .INIT(32'h04004404)) \n \\genblk8[3].right_gain_pb[23]_i_7 \n (.I0(\\genblk8[3].right_edge_pb_reg[18]_0 ),\n .I1(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .I2(right_edge_ref[5]),\n .I3(\\genblk8[3].right_edge_pb_reg_n_0_[23] ),\n .I4(\\genblk8[3].right_gain_pb[23]_i_13_n_0 ),\n .O(\\genblk8[3].right_gain_pb[23]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FFB200B2)) \n \\genblk8[3].right_gain_pb[23]_i_8 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[23] ),\n .I1(right_edge_ref[5]),\n .I2(\\genblk8[3].right_gain_pb[23]_i_14_n_0 ),\n .I3(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I4(\\genblk8[3].right_gain_pb_reg[23]_i_15_n_0 ),\n .I5(\\genblk8[3].right_edge_pb_reg[18]_0 ),\n .O(\\genblk8[3].right_gain_pb[23]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[3].right_gain_pb[23]_i_9 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .I1(\\genblk8[3].right_edge_pb_reg_n_0_[23] ),\n .O(\\genblk8[3].right_gain_pb[23]_i_9_n_0 ));\n FDRE \\genblk8[3].right_gain_pb_reg[18] \n (.C(CLK),\n .CE(\\genblk8[3].right_gain_pb[23]_i_2_n_0 ),\n .D(\\genblk8[3].right_gain_pb[18]_i_1_n_0 ),\n .Q(\\genblk8[3].right_gain_pb_reg_n_0_[18] ),\n .R(\\genblk8[3].right_gain_pb[23]_i_1_n_0 ));\n FDRE \\genblk8[3].right_gain_pb_reg[19] \n (.C(CLK),\n .CE(\\genblk8[3].right_gain_pb[23]_i_2_n_0 ),\n .D(\\genblk8[3].right_gain_pb[19]_i_1_n_0 ),\n .Q(\\genblk8[3].right_gain_pb_reg_n_0_[19] ),\n .R(\\genblk8[3].right_gain_pb[23]_i_1_n_0 ));\n FDRE \\genblk8[3].right_gain_pb_reg[20] \n (.C(CLK),\n .CE(\\genblk8[3].right_gain_pb[23]_i_2_n_0 ),\n .D(\\genblk8[3].right_gain_pb[20]_i_1_n_0 ),\n .Q(\\genblk8[3].right_gain_pb_reg__0 [2]),\n .R(\\genblk8[3].right_gain_pb[23]_i_1_n_0 ));\n FDRE \\genblk8[3].right_gain_pb_reg[21] \n (.C(CLK),\n .CE(\\genblk8[3].right_gain_pb[23]_i_2_n_0 ),\n .D(\\genblk8[3].right_gain_pb[21]_i_1_n_0 ),\n .Q(\\genblk8[3].right_gain_pb_reg__0 [3]),\n .R(\\genblk8[3].right_gain_pb[23]_i_1_n_0 ));\n CARRY4 \\genblk8[3].right_gain_pb_reg[21]_i_2 \n (.CI(1'b0),\n .CO({\\genblk8[3].right_gain_pb_reg[21]_i_2_n_0 ,\\genblk8[3].right_gain_pb_reg[21]_i_2_n_1 ,\\genblk8[3].right_gain_pb_reg[21]_i_2_n_2 ,\\genblk8[3].right_gain_pb_reg[21]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ,\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ,\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ,\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }),\n .O({\\genblk8[3].right_gain_pb_reg[21]_i_2_n_4 ,\\genblk8[3].right_gain_pb_reg[21]_i_2_n_5 ,\\genblk8[3].right_gain_pb_reg[21]_i_2_n_6 ,\\genblk8[3].right_gain_pb_reg[21]_i_2_n_7 }),\n .S({\\genblk8[3].right_gain_pb[21]_i_4_n_0 ,\\genblk8[3].right_gain_pb[21]_i_5_n_0 ,\\genblk8[3].right_gain_pb[21]_i_6_n_0 ,\\genblk8[3].right_gain_pb[21]_i_7_n_0 }));\n CARRY4 \\genblk8[3].right_gain_pb_reg[21]_i_3 \n (.CI(1'b0),\n .CO({\\genblk8[3].right_gain_pb_reg[21]_i_3_n_0 ,\\genblk8[3].right_gain_pb_reg[21]_i_3_n_1 ,\\genblk8[3].right_gain_pb_reg[21]_i_3_n_2 ,\\genblk8[3].right_gain_pb_reg[21]_i_3_n_3 }),\n .CYINIT(1'b1),\n .DI(right_edge_ref[3:0]),\n .O({\\genblk8[3].right_gain_pb_reg[21]_i_3_n_4 ,\\genblk8[3].right_gain_pb_reg[21]_i_3_n_5 ,\\genblk8[3].right_gain_pb_reg[21]_i_3_n_6 ,\\genblk8[3].right_gain_pb_reg[21]_i_3_n_7 }),\n .S({\\genblk8[3].right_gain_pb[21]_i_8_n_0 ,\\genblk8[3].right_gain_pb[21]_i_9_n_0 ,\\genblk8[3].right_gain_pb[21]_i_10_n_0 ,\\genblk8[3].right_gain_pb[21]_i_11_n_0 }));\n FDRE \\genblk8[3].right_gain_pb_reg[22] \n (.C(CLK),\n .CE(\\genblk8[3].right_gain_pb[23]_i_2_n_0 ),\n .D(\\genblk8[3].right_gain_pb[22]_i_1_n_0 ),\n .Q(\\genblk8[3].right_gain_pb_reg__0 [4]),\n .R(\\genblk8[3].right_gain_pb[23]_i_1_n_0 ));\n FDRE \\genblk8[3].right_gain_pb_reg[23] \n (.C(CLK),\n .CE(\\genblk8[3].right_gain_pb[23]_i_2_n_0 ),\n .D(\\genblk8[3].right_gain_pb[23]_i_3_n_0 ),\n .Q(\\genblk8[3].right_gain_pb_reg__0 [5]),\n .R(\\genblk8[3].right_gain_pb[23]_i_1_n_0 ));\n CARRY4 \\genblk8[3].right_gain_pb_reg[23]_i_15 \n (.CI(\\genblk8[3].right_gain_pb_reg[23]_i_18_n_0 ),\n .CO({\\genblk8[3].right_gain_pb_reg[23]_i_15_n_0 ,\\genblk8[3].right_gain_pb_reg[23]_i_15_n_1 ,\\genblk8[3].right_gain_pb_reg[23]_i_15_n_2 ,\\genblk8[3].right_gain_pb_reg[23]_i_15_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[3].right_gain_pb_reg[23]_i_15_O_UNCONNECTED [3:0]),\n .S({\\genblk8[3].right_gain_pb[23]_i_19_n_0 ,\\genblk8[3].right_gain_pb[23]_i_20_n_0 ,\\genblk8[3].right_gain_pb[23]_i_21_n_0 ,\\genblk8[3].right_gain_pb[23]_i_22_n_0 }));\n CARRY4 \\genblk8[3].right_gain_pb_reg[23]_i_18 \n (.CI(\\genblk8[3].right_gain_pb_reg[23]_i_23_n_0 ),\n .CO({\\genblk8[3].right_gain_pb_reg[23]_i_18_n_0 ,\\genblk8[3].right_gain_pb_reg[23]_i_18_n_1 ,\\genblk8[3].right_gain_pb_reg[23]_i_18_n_2 ,\\genblk8[3].right_gain_pb_reg[23]_i_18_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[3].right_gain_pb_reg[23]_i_18_O_UNCONNECTED [3:0]),\n .S({\\genblk8[3].right_gain_pb[23]_i_24_n_0 ,\\genblk8[3].right_gain_pb[23]_i_25_n_0 ,\\genblk8[3].right_gain_pb[23]_i_26_n_0 ,\\genblk8[3].right_gain_pb[23]_i_27_n_0 }));\n CARRY4 \\genblk8[3].right_gain_pb_reg[23]_i_23 \n (.CI(\\genblk8[3].right_gain_pb_reg[23]_i_28_n_0 ),\n .CO({\\genblk8[3].right_gain_pb_reg[23]_i_23_n_0 ,\\genblk8[3].right_gain_pb_reg[23]_i_23_n_1 ,\\genblk8[3].right_gain_pb_reg[23]_i_23_n_2 ,\\genblk8[3].right_gain_pb_reg[23]_i_23_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[3].right_gain_pb_reg[23]_i_23_O_UNCONNECTED [3:0]),\n .S({\\genblk8[3].right_gain_pb[23]_i_29_n_0 ,\\genblk8[3].right_gain_pb[23]_i_30_n_0 ,\\genblk8[3].right_gain_pb[23]_i_31_n_0 ,\\genblk8[3].right_gain_pb[23]_i_32_n_0 }));\n CARRY4 \\genblk8[3].right_gain_pb_reg[23]_i_28 \n (.CI(1'b0),\n .CO({\\genblk8[3].right_gain_pb_reg[23]_i_28_n_0 ,\\genblk8[3].right_gain_pb_reg[23]_i_28_n_1 ,\\genblk8[3].right_gain_pb_reg[23]_i_28_n_2 ,\\genblk8[3].right_gain_pb_reg[23]_i_28_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,\\genblk8[3].right_gain_pb[23]_i_33_n_0 ,\\genblk8[3].right_gain_pb[23]_i_34_n_0 ,\\genblk8[3].right_gain_pb[23]_i_35_n_0 }),\n .O(\\NLW_genblk8[3].right_gain_pb_reg[23]_i_28_O_UNCONNECTED [3:0]),\n .S({\\genblk8[3].right_gain_pb[23]_i_36_n_0 ,\\genblk8[3].right_gain_pb[23]_i_37_n_0 ,\\genblk8[3].right_gain_pb[23]_i_38_n_0 ,\\genblk8[3].right_gain_pb[23]_i_39_n_0 }));\n MUXF7 \\genblk8[3].right_gain_pb_reg[23]_i_4 \n (.I0(\\genblk8[3].right_gain_pb[23]_i_7_n_0 ),\n .I1(\\genblk8[3].right_gain_pb[23]_i_8_n_0 ),\n .O(\\genblk8[3].right_gain_pb_reg[23]_i_4_n_0 ),\n .S(p_127_out));\n CARRY4 \\genblk8[3].right_gain_pb_reg[23]_i_5 \n (.CI(\\genblk8[3].right_gain_pb_reg[21]_i_2_n_0 ),\n .CO({\\NLW_genblk8[3].right_gain_pb_reg[23]_i_5_CO_UNCONNECTED [3:1],\\genblk8[3].right_gain_pb_reg[23]_i_5_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,\\prbs_dqs_tap_cnt_r_reg_n_0_[4] }),\n .O({\\NLW_genblk8[3].right_gain_pb_reg[23]_i_5_O_UNCONNECTED [3:2],\\genblk8[3].right_gain_pb_reg[23]_i_5_n_6 ,\\genblk8[3].right_gain_pb_reg[23]_i_5_n_7 }),\n .S({1'b0,1'b0,\\genblk8[3].right_gain_pb[23]_i_9_n_0 ,\\genblk8[3].right_gain_pb[23]_i_10_n_0 }));\n CARRY4 \\genblk8[3].right_gain_pb_reg[23]_i_6 \n (.CI(\\genblk8[3].right_gain_pb_reg[21]_i_3_n_0 ),\n .CO({\\NLW_genblk8[3].right_gain_pb_reg[23]_i_6_CO_UNCONNECTED [3:1],\\genblk8[3].right_gain_pb_reg[23]_i_6_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,right_edge_ref[4]}),\n .O({\\NLW_genblk8[3].right_gain_pb_reg[23]_i_6_O_UNCONNECTED [3:2],\\genblk8[3].right_gain_pb_reg[23]_i_6_n_6 ,\\genblk8[3].right_gain_pb_reg[23]_i_6_n_7 }),\n .S({1'b0,1'b0,\\genblk8[3].right_gain_pb[23]_i_11_n_0 ,\\genblk8[3].right_gain_pb[23]_i_12_n_0 }));\n FDRE \\genblk8[4].left_edge_found_pb_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[4].left_edge_found_pb_reg[4]_0 ),\n .Q(\\genblk8[4].left_loss_pb_reg[24]_0 ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\genblk8[4].left_edge_pb[29]_i_1 \n (.I0(p_154_out),\n .I1(p_122_out),\n .O(\\genblk8[4].left_edge_pb[29]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\genblk8[4].left_edge_pb[29]_i_2 \n (.I0(match_flag_pb[39]),\n .I1(\\genblk8[4].left_edge_pb[29]_i_3_n_0 ),\n .I2(\\genblk7[4].compare_err_pb_latch_r_reg_n_0_[4] ),\n .I3(match_flag_pb[38]),\n .I4(match_flag_pb[36]),\n .I5(match_flag_pb[37]),\n .O(p_122_out));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\genblk8[4].left_edge_pb[29]_i_3 \n (.I0(match_flag_pb[34]),\n .I1(match_flag_pb[35]),\n .I2(match_flag_pb[32]),\n .I3(match_flag_pb[33]),\n .O(\\genblk8[4].left_edge_pb[29]_i_3_n_0 ));\n FDRE \\genblk8[4].left_edge_pb_reg[24] \n (.C(CLK),\n .CE(\\genblk8[4].left_edge_pb[29]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[4].left_edge_pb_reg_n_0_[24] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[4].left_edge_pb_reg[25] \n (.C(CLK),\n .CE(\\genblk8[4].left_edge_pb[29]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[4].left_edge_pb_reg_n_0_[25] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[4].left_edge_pb_reg[26] \n (.C(CLK),\n .CE(\\genblk8[4].left_edge_pb[29]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[4].left_edge_pb_reg_n_0_[26] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[4].left_edge_pb_reg[27] \n (.C(CLK),\n .CE(\\genblk8[4].left_edge_pb[29]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[4].left_edge_pb_reg_n_0_[27] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[4].left_edge_pb_reg[28] \n (.C(CLK),\n .CE(\\genblk8[4].left_edge_pb[29]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[4].left_edge_pb_reg_n_0_[28] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[4].left_edge_pb_reg[29] \n (.C(CLK),\n .CE(\\genblk8[4].left_edge_pb[29]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[5]_i_3_n_0 ),\n .Q(\\genblk8[4].left_edge_pb_reg_n_0_[29] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[4].left_edge_updated_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[4].left_edge_updated_reg[4]_0 ),\n .Q(D[4]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAEFEAEAE)) \n \\genblk8[4].left_loss_pb[29]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(right_gain_pb),\n .I2(p_154_out),\n .I3(\\genblk8[4].left_loss_pb_reg[24]_0 ),\n .I4(p_122_out),\n .O(\\genblk8[4].left_loss_pb[29]_i_1_n_0 ));\n FDRE \\genblk8[4].left_loss_pb_reg[24] \n (.C(CLK),\n .CE(\\genblk8[4].left_loss_pb[29]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[4].left_loss_pb_reg_n_0_[24] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[4].left_loss_pb_reg[25] \n (.C(CLK),\n .CE(\\genblk8[4].left_loss_pb[29]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[4].left_loss_pb_reg_n_0_[25] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[4].left_loss_pb_reg[26] \n (.C(CLK),\n .CE(\\genblk8[4].left_loss_pb[29]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[4].left_loss_pb_reg__0 [2]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[4].left_loss_pb_reg[27] \n (.C(CLK),\n .CE(\\genblk8[4].left_loss_pb[29]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[4].left_loss_pb_reg__0 [3]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[4].left_loss_pb_reg[28] \n (.C(CLK),\n .CE(\\genblk8[4].left_loss_pb[29]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[4].left_loss_pb_reg__0 [4]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[4].left_loss_pb_reg[29] \n (.C(CLK),\n .CE(\\genblk8[4].left_loss_pb[29]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[5]_i_2_n_0 ),\n .Q(\\genblk8[4].left_loss_pb_reg__0 [5]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDSE \\genblk8[4].match_flag_pb_reg[32] \n (.C(CLK),\n .CE(p_154_out),\n .D(\\genblk7[4].compare_err_pb_latch_r_reg_n_0_[4] ),\n .Q(match_flag_pb[32]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[4].match_flag_pb_reg[33] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[32]),\n .Q(match_flag_pb[33]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[4].match_flag_pb_reg[34] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[33]),\n .Q(match_flag_pb[34]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[4].match_flag_pb_reg[35] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[34]),\n .Q(match_flag_pb[35]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[4].match_flag_pb_reg[36] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[35]),\n .Q(match_flag_pb[36]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[4].match_flag_pb_reg[37] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[36]),\n .Q(match_flag_pb[37]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[4].match_flag_pb_reg[38] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[37]),\n .Q(match_flag_pb[38]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[4].match_flag_pb_reg[39] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[38]),\n .Q(match_flag_pb[39]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDRE \\genblk8[4].right_edge_found_pb_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[4].right_edge_found_pb_reg[4]_0 ),\n .Q(\\genblk8[4].right_edge_pb_reg[24]_0 ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAABAAAAAAAAA)) \n \\genblk8[4].right_edge_pb[29]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(p_122_out),\n .I2(p_154_out),\n .I3(p_119_out),\n .I4(\\genblk8[4].right_edge_pb_reg[24]_0 ),\n .I5(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .O(\\genblk8[4].right_edge_pb[29]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h08)) \n \\genblk8[4].right_edge_pb[29]_i_2 \n (.I0(p_154_out),\n .I1(p_119_out),\n .I2(p_122_out),\n .O(\\genblk8[4].right_edge_pb[29]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\genblk8[4].right_edge_pb[29]_i_3 \n (.I0(\\genblk7[4].compare_err_pb_latch_r_reg_n_0_[4] ),\n .I1(\\genblk8[4].left_edge_pb[29]_i_3_n_0 ),\n .I2(match_flag_pb[39]),\n .I3(match_flag_pb[38]),\n .I4(match_flag_pb[36]),\n .I5(match_flag_pb[37]),\n .O(p_119_out));\n FDSE \\genblk8[4].right_edge_pb_reg[24] \n (.C(CLK),\n .CE(\\genblk8[4].right_edge_pb[29]_i_2_n_0 ),\n .D(\\genblk8[0].left_edge_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[4].right_edge_pb_reg_n_0_[24] ),\n .S(\\genblk8[4].right_edge_pb[29]_i_1_n_0 ));\n FDSE \\genblk8[4].right_edge_pb_reg[25] \n (.C(CLK),\n .CE(\\genblk8[4].right_edge_pb[29]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[4].right_edge_pb_reg_n_0_[25] ),\n .S(\\genblk8[4].right_edge_pb[29]_i_1_n_0 ));\n FDSE \\genblk8[4].right_edge_pb_reg[26] \n (.C(CLK),\n .CE(\\genblk8[4].right_edge_pb[29]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[4].right_edge_pb_reg_n_0_[26] ),\n .S(\\genblk8[4].right_edge_pb[29]_i_1_n_0 ));\n FDSE \\genblk8[4].right_edge_pb_reg[27] \n (.C(CLK),\n .CE(\\genblk8[4].right_edge_pb[29]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[4].right_edge_pb_reg_n_0_[27] ),\n .S(\\genblk8[4].right_edge_pb[29]_i_1_n_0 ));\n FDSE \\genblk8[4].right_edge_pb_reg[28] \n (.C(CLK),\n .CE(\\genblk8[4].right_edge_pb[29]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[4].right_edge_pb_reg_n_0_[28] ),\n .S(\\genblk8[4].right_edge_pb[29]_i_1_n_0 ));\n FDSE \\genblk8[4].right_edge_pb_reg[29] \n (.C(CLK),\n .CE(\\genblk8[4].right_edge_pb[29]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[5]_i_3_n_0 ),\n .Q(\\genblk8[4].right_edge_pb_reg_n_0_[29] ),\n .S(\\genblk8[4].right_edge_pb[29]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[4].right_gain_pb[24]_i_1 \n (.I0(p_119_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[4].right_gain_pb_reg[27]_i_2_n_7 ),\n .I3(\\genblk8[4].right_gain_pb_reg[27]_i_3_n_7 ),\n .O(\\genblk8[4].right_gain_pb[24]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[4].right_gain_pb[25]_i_1 \n (.I0(p_119_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[4].right_gain_pb_reg[27]_i_2_n_6 ),\n .I3(\\genblk8[4].right_gain_pb_reg[27]_i_3_n_6 ),\n .O(\\genblk8[4].right_gain_pb[25]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[4].right_gain_pb[26]_i_1 \n (.I0(p_119_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[4].right_gain_pb_reg[27]_i_2_n_5 ),\n .I3(\\genblk8[4].right_gain_pb_reg[27]_i_3_n_5 ),\n .O(\\genblk8[4].right_gain_pb[26]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[4].right_gain_pb[27]_i_1 \n (.I0(p_119_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[4].right_gain_pb_reg[27]_i_2_n_4 ),\n .I3(\\genblk8[4].right_gain_pb_reg[27]_i_3_n_4 ),\n .O(\\genblk8[4].right_gain_pb[27]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[4].right_gain_pb[27]_i_10 \n (.I0(right_edge_ref[1]),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[25] ),\n .O(\\genblk8[4].right_gain_pb[27]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[4].right_gain_pb[27]_i_11 \n (.I0(right_edge_ref[0]),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[24] ),\n .O(\\genblk8[4].right_gain_pb[27]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[4].right_gain_pb[27]_i_4 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[27] ),\n .O(\\genblk8[4].right_gain_pb[27]_i_4_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[4].right_gain_pb[27]_i_5 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[26] ),\n .O(\\genblk8[4].right_gain_pb[27]_i_5_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[4].right_gain_pb[27]_i_6 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[25] ),\n .O(\\genblk8[4].right_gain_pb[27]_i_6_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[4].right_gain_pb[27]_i_7 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[24] ),\n .O(\\genblk8[4].right_gain_pb[27]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[4].right_gain_pb[27]_i_8 \n (.I0(right_edge_ref[3]),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[27] ),\n .O(\\genblk8[4].right_gain_pb[27]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[4].right_gain_pb[27]_i_9 \n (.I0(right_edge_ref[2]),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[26] ),\n .O(\\genblk8[4].right_gain_pb[27]_i_9_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[4].right_gain_pb[28]_i_1 \n (.I0(p_119_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[4].right_gain_pb_reg[29]_i_5_n_7 ),\n .I3(\\genblk8[4].right_gain_pb_reg[29]_i_6_n_7 ),\n .O(\\genblk8[4].right_gain_pb[28]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAEFEAEAE)) \n \\genblk8[4].right_gain_pb[29]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(right_gain_pb),\n .I2(p_154_out),\n .I3(p_122_out),\n .I4(\\genblk8[4].right_gain_pb_reg[29]_i_4_n_0 ),\n .O(\\genblk8[4].right_gain_pb[29]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[4].right_gain_pb[29]_i_10 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[28] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[4].right_gain_pb[29]_i_11 \n (.I0(right_edge_ref[5]),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[29] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[4].right_gain_pb[29]_i_12 \n (.I0(right_edge_ref[4]),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[28] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_12_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk8[4].right_gain_pb[29]_i_13 \n (.I0(\\genblk8[4].right_gain_pb[29]_i_16_n_0 ),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[27] ),\n .I2(right_edge_ref[3]),\n .I3(\\genblk8[4].right_edge_pb_reg_n_0_[28] ),\n .I4(right_edge_ref[4]),\n .O(\\genblk8[4].right_gain_pb[29]_i_13_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk8[4].right_gain_pb[29]_i_14 \n (.I0(\\genblk8[4].right_gain_pb[29]_i_17_n_0 ),\n .I1(right_edge_ref[3]),\n .I2(\\genblk8[4].right_edge_pb_reg_n_0_[27] ),\n .I3(right_edge_ref[4]),\n .I4(\\genblk8[4].right_edge_pb_reg_n_0_[28] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk8[4].right_gain_pb[29]_i_16 \n (.I0(right_edge_ref[0]),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[24] ),\n .I2(\\genblk8[4].right_edge_pb_reg_n_0_[25] ),\n .I3(right_edge_ref[1]),\n .I4(\\genblk8[4].right_edge_pb_reg_n_0_[26] ),\n .I5(right_edge_ref[2]),\n .O(\\genblk8[4].right_gain_pb[29]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk8[4].right_gain_pb[29]_i_17 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[24] ),\n .I1(right_edge_ref[0]),\n .I2(right_edge_ref[1]),\n .I3(\\genblk8[4].right_edge_pb_reg_n_0_[25] ),\n .I4(right_edge_ref[2]),\n .I5(\\genblk8[4].right_edge_pb_reg_n_0_[26] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[4].right_gain_pb[29]_i_19 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_19_n_0 ));\n LUT5 #(\n .INIT(32'h000000A8)) \n \\genblk8[4].right_gain_pb[29]_i_2 \n (.I0(p_154_out),\n .I1(p_119_out),\n .I2(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .I3(\\genblk8[4].right_edge_pb_reg[24]_0 ),\n .I4(p_122_out),\n .O(\\genblk8[4].right_gain_pb[29]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[4].right_gain_pb[29]_i_20 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[4].right_gain_pb[29]_i_21 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_21_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[4].right_gain_pb[29]_i_22 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_22_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[4].right_gain_pb[29]_i_24 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_24_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[4].right_gain_pb[29]_i_25 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_25_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[4].right_gain_pb[29]_i_26 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_26_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[4].right_gain_pb[29]_i_27 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_27_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[4].right_gain_pb[29]_i_29 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_29_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[4].right_gain_pb[29]_i_3 \n (.I0(p_119_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[4].right_gain_pb_reg[29]_i_5_n_6 ),\n .I3(\\genblk8[4].right_gain_pb_reg[29]_i_6_n_6 ),\n .O(\\genblk8[4].right_gain_pb[29]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[4].right_gain_pb[29]_i_30 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_30_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[4].right_gain_pb[29]_i_31 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_31_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[4].right_gain_pb[29]_i_32 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_32_n_0 ));\n LUT4 #(\n .INIT(16'hF880)) \n \\genblk8[4].right_gain_pb[29]_i_33 \n (.I0(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[28] ),\n .I2(\\genblk8[4].right_edge_pb_reg_n_0_[29] ),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[4].right_gain_pb[29]_i_33_n_0 ));\n LUT6 #(\n .INIT(64'h0808088CCECECEE0)) \n \\genblk8[4].right_gain_pb[29]_i_34 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[26] ),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[27] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[4].right_gain_pb[29]_i_34_n_0 ));\n LUT4 #(\n .INIT(16'h8CE0)) \n \\genblk8[4].right_gain_pb[29]_i_35 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[24] ),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[25] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\genblk8[4].right_gain_pb[29]_i_35_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[4].right_gain_pb[29]_i_36 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_36_n_0 ));\n LUT4 #(\n .INIT(16'h0660)) \n \\genblk8[4].right_gain_pb[29]_i_37 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[28] ),\n .I1(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I2(\\genblk8[4].right_edge_pb_reg_n_0_[29] ),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[4].right_gain_pb[29]_i_37_n_0 ));\n LUT6 #(\n .INIT(64'h8484844221212118)) \n \\genblk8[4].right_gain_pb[29]_i_38 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[26] ),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[27] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[4].right_gain_pb[29]_i_38_n_0 ));\n LUT4 #(\n .INIT(16'h4218)) \n \\genblk8[4].right_gain_pb[29]_i_39 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[24] ),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[25] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\genblk8[4].right_gain_pb[29]_i_39_n_0 ));\n LUT5 #(\n .INIT(32'h04004404)) \n \\genblk8[4].right_gain_pb[29]_i_7 \n (.I0(\\genblk8[4].right_edge_pb_reg[24]_0 ),\n .I1(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .I2(right_edge_ref[5]),\n .I3(\\genblk8[4].right_edge_pb_reg_n_0_[29] ),\n .I4(\\genblk8[4].right_gain_pb[29]_i_13_n_0 ),\n .O(\\genblk8[4].right_gain_pb[29]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FFB200B2)) \n \\genblk8[4].right_gain_pb[29]_i_8 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[29] ),\n .I1(right_edge_ref[5]),\n .I2(\\genblk8[4].right_gain_pb[29]_i_14_n_0 ),\n .I3(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I4(\\genblk8[4].right_gain_pb_reg[29]_i_15_n_0 ),\n .I5(\\genblk8[4].right_edge_pb_reg[24]_0 ),\n .O(\\genblk8[4].right_gain_pb[29]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[4].right_gain_pb[29]_i_9 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .I1(\\genblk8[4].right_edge_pb_reg_n_0_[29] ),\n .O(\\genblk8[4].right_gain_pb[29]_i_9_n_0 ));\n FDRE \\genblk8[4].right_gain_pb_reg[24] \n (.C(CLK),\n .CE(\\genblk8[4].right_gain_pb[29]_i_2_n_0 ),\n .D(\\genblk8[4].right_gain_pb[24]_i_1_n_0 ),\n .Q(\\genblk8[4].right_gain_pb_reg_n_0_[24] ),\n .R(\\genblk8[4].right_gain_pb[29]_i_1_n_0 ));\n FDRE \\genblk8[4].right_gain_pb_reg[25] \n (.C(CLK),\n .CE(\\genblk8[4].right_gain_pb[29]_i_2_n_0 ),\n .D(\\genblk8[4].right_gain_pb[25]_i_1_n_0 ),\n .Q(\\genblk8[4].right_gain_pb_reg_n_0_[25] ),\n .R(\\genblk8[4].right_gain_pb[29]_i_1_n_0 ));\n FDRE \\genblk8[4].right_gain_pb_reg[26] \n (.C(CLK),\n .CE(\\genblk8[4].right_gain_pb[29]_i_2_n_0 ),\n .D(\\genblk8[4].right_gain_pb[26]_i_1_n_0 ),\n .Q(\\genblk8[4].right_gain_pb_reg__0 [2]),\n .R(\\genblk8[4].right_gain_pb[29]_i_1_n_0 ));\n FDRE \\genblk8[4].right_gain_pb_reg[27] \n (.C(CLK),\n .CE(\\genblk8[4].right_gain_pb[29]_i_2_n_0 ),\n .D(\\genblk8[4].right_gain_pb[27]_i_1_n_0 ),\n .Q(\\genblk8[4].right_gain_pb_reg__0 [3]),\n .R(\\genblk8[4].right_gain_pb[29]_i_1_n_0 ));\n CARRY4 \\genblk8[4].right_gain_pb_reg[27]_i_2 \n (.CI(1'b0),\n .CO({\\genblk8[4].right_gain_pb_reg[27]_i_2_n_0 ,\\genblk8[4].right_gain_pb_reg[27]_i_2_n_1 ,\\genblk8[4].right_gain_pb_reg[27]_i_2_n_2 ,\\genblk8[4].right_gain_pb_reg[27]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ,\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ,\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ,\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }),\n .O({\\genblk8[4].right_gain_pb_reg[27]_i_2_n_4 ,\\genblk8[4].right_gain_pb_reg[27]_i_2_n_5 ,\\genblk8[4].right_gain_pb_reg[27]_i_2_n_6 ,\\genblk8[4].right_gain_pb_reg[27]_i_2_n_7 }),\n .S({\\genblk8[4].right_gain_pb[27]_i_4_n_0 ,\\genblk8[4].right_gain_pb[27]_i_5_n_0 ,\\genblk8[4].right_gain_pb[27]_i_6_n_0 ,\\genblk8[4].right_gain_pb[27]_i_7_n_0 }));\n CARRY4 \\genblk8[4].right_gain_pb_reg[27]_i_3 \n (.CI(1'b0),\n .CO({\\genblk8[4].right_gain_pb_reg[27]_i_3_n_0 ,\\genblk8[4].right_gain_pb_reg[27]_i_3_n_1 ,\\genblk8[4].right_gain_pb_reg[27]_i_3_n_2 ,\\genblk8[4].right_gain_pb_reg[27]_i_3_n_3 }),\n .CYINIT(1'b1),\n .DI(right_edge_ref[3:0]),\n .O({\\genblk8[4].right_gain_pb_reg[27]_i_3_n_4 ,\\genblk8[4].right_gain_pb_reg[27]_i_3_n_5 ,\\genblk8[4].right_gain_pb_reg[27]_i_3_n_6 ,\\genblk8[4].right_gain_pb_reg[27]_i_3_n_7 }),\n .S({\\genblk8[4].right_gain_pb[27]_i_8_n_0 ,\\genblk8[4].right_gain_pb[27]_i_9_n_0 ,\\genblk8[4].right_gain_pb[27]_i_10_n_0 ,\\genblk8[4].right_gain_pb[27]_i_11_n_0 }));\n FDRE \\genblk8[4].right_gain_pb_reg[28] \n (.C(CLK),\n .CE(\\genblk8[4].right_gain_pb[29]_i_2_n_0 ),\n .D(\\genblk8[4].right_gain_pb[28]_i_1_n_0 ),\n .Q(\\genblk8[4].right_gain_pb_reg__0 [4]),\n .R(\\genblk8[4].right_gain_pb[29]_i_1_n_0 ));\n FDRE \\genblk8[4].right_gain_pb_reg[29] \n (.C(CLK),\n .CE(\\genblk8[4].right_gain_pb[29]_i_2_n_0 ),\n .D(\\genblk8[4].right_gain_pb[29]_i_3_n_0 ),\n .Q(\\genblk8[4].right_gain_pb_reg__0 [5]),\n .R(\\genblk8[4].right_gain_pb[29]_i_1_n_0 ));\n CARRY4 \\genblk8[4].right_gain_pb_reg[29]_i_15 \n (.CI(\\genblk8[4].right_gain_pb_reg[29]_i_18_n_0 ),\n .CO({\\genblk8[4].right_gain_pb_reg[29]_i_15_n_0 ,\\genblk8[4].right_gain_pb_reg[29]_i_15_n_1 ,\\genblk8[4].right_gain_pb_reg[29]_i_15_n_2 ,\\genblk8[4].right_gain_pb_reg[29]_i_15_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[4].right_gain_pb_reg[29]_i_15_O_UNCONNECTED [3:0]),\n .S({\\genblk8[4].right_gain_pb[29]_i_19_n_0 ,\\genblk8[4].right_gain_pb[29]_i_20_n_0 ,\\genblk8[4].right_gain_pb[29]_i_21_n_0 ,\\genblk8[4].right_gain_pb[29]_i_22_n_0 }));\n CARRY4 \\genblk8[4].right_gain_pb_reg[29]_i_18 \n (.CI(\\genblk8[4].right_gain_pb_reg[29]_i_23_n_0 ),\n .CO({\\genblk8[4].right_gain_pb_reg[29]_i_18_n_0 ,\\genblk8[4].right_gain_pb_reg[29]_i_18_n_1 ,\\genblk8[4].right_gain_pb_reg[29]_i_18_n_2 ,\\genblk8[4].right_gain_pb_reg[29]_i_18_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[4].right_gain_pb_reg[29]_i_18_O_UNCONNECTED [3:0]),\n .S({\\genblk8[4].right_gain_pb[29]_i_24_n_0 ,\\genblk8[4].right_gain_pb[29]_i_25_n_0 ,\\genblk8[4].right_gain_pb[29]_i_26_n_0 ,\\genblk8[4].right_gain_pb[29]_i_27_n_0 }));\n CARRY4 \\genblk8[4].right_gain_pb_reg[29]_i_23 \n (.CI(\\genblk8[4].right_gain_pb_reg[29]_i_28_n_0 ),\n .CO({\\genblk8[4].right_gain_pb_reg[29]_i_23_n_0 ,\\genblk8[4].right_gain_pb_reg[29]_i_23_n_1 ,\\genblk8[4].right_gain_pb_reg[29]_i_23_n_2 ,\\genblk8[4].right_gain_pb_reg[29]_i_23_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[4].right_gain_pb_reg[29]_i_23_O_UNCONNECTED [3:0]),\n .S({\\genblk8[4].right_gain_pb[29]_i_29_n_0 ,\\genblk8[4].right_gain_pb[29]_i_30_n_0 ,\\genblk8[4].right_gain_pb[29]_i_31_n_0 ,\\genblk8[4].right_gain_pb[29]_i_32_n_0 }));\n CARRY4 \\genblk8[4].right_gain_pb_reg[29]_i_28 \n (.CI(1'b0),\n .CO({\\genblk8[4].right_gain_pb_reg[29]_i_28_n_0 ,\\genblk8[4].right_gain_pb_reg[29]_i_28_n_1 ,\\genblk8[4].right_gain_pb_reg[29]_i_28_n_2 ,\\genblk8[4].right_gain_pb_reg[29]_i_28_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,\\genblk8[4].right_gain_pb[29]_i_33_n_0 ,\\genblk8[4].right_gain_pb[29]_i_34_n_0 ,\\genblk8[4].right_gain_pb[29]_i_35_n_0 }),\n .O(\\NLW_genblk8[4].right_gain_pb_reg[29]_i_28_O_UNCONNECTED [3:0]),\n .S({\\genblk8[4].right_gain_pb[29]_i_36_n_0 ,\\genblk8[4].right_gain_pb[29]_i_37_n_0 ,\\genblk8[4].right_gain_pb[29]_i_38_n_0 ,\\genblk8[4].right_gain_pb[29]_i_39_n_0 }));\n MUXF7 \\genblk8[4].right_gain_pb_reg[29]_i_4 \n (.I0(\\genblk8[4].right_gain_pb[29]_i_7_n_0 ),\n .I1(\\genblk8[4].right_gain_pb[29]_i_8_n_0 ),\n .O(\\genblk8[4].right_gain_pb_reg[29]_i_4_n_0 ),\n .S(p_119_out));\n CARRY4 \\genblk8[4].right_gain_pb_reg[29]_i_5 \n (.CI(\\genblk8[4].right_gain_pb_reg[27]_i_2_n_0 ),\n .CO({\\NLW_genblk8[4].right_gain_pb_reg[29]_i_5_CO_UNCONNECTED [3:1],\\genblk8[4].right_gain_pb_reg[29]_i_5_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,\\prbs_dqs_tap_cnt_r_reg_n_0_[4] }),\n .O({\\NLW_genblk8[4].right_gain_pb_reg[29]_i_5_O_UNCONNECTED [3:2],\\genblk8[4].right_gain_pb_reg[29]_i_5_n_6 ,\\genblk8[4].right_gain_pb_reg[29]_i_5_n_7 }),\n .S({1'b0,1'b0,\\genblk8[4].right_gain_pb[29]_i_9_n_0 ,\\genblk8[4].right_gain_pb[29]_i_10_n_0 }));\n CARRY4 \\genblk8[4].right_gain_pb_reg[29]_i_6 \n (.CI(\\genblk8[4].right_gain_pb_reg[27]_i_3_n_0 ),\n .CO({\\NLW_genblk8[4].right_gain_pb_reg[29]_i_6_CO_UNCONNECTED [3:1],\\genblk8[4].right_gain_pb_reg[29]_i_6_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,right_edge_ref[4]}),\n .O({\\NLW_genblk8[4].right_gain_pb_reg[29]_i_6_O_UNCONNECTED [3:2],\\genblk8[4].right_gain_pb_reg[29]_i_6_n_6 ,\\genblk8[4].right_gain_pb_reg[29]_i_6_n_7 }),\n .S({1'b0,1'b0,\\genblk8[4].right_gain_pb[29]_i_11_n_0 ,\\genblk8[4].right_gain_pb[29]_i_12_n_0 }));\n FDRE \\genblk8[5].left_edge_found_pb_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[5].left_edge_found_pb_reg[5]_0 ),\n .Q(\\genblk8[5].left_loss_pb_reg[30]_0 ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\genblk8[5].left_edge_pb[35]_i_1 \n (.I0(p_154_out),\n .I1(\\genblk8[5].right_gain_pb_reg[30]_0 ),\n .O(\\genblk8[5].left_edge_pb[35]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\genblk8[5].left_edge_pb[35]_i_2 \n (.I0(match_flag_pb[47]),\n .I1(\\genblk8[5].left_edge_pb[35]_i_3_n_0 ),\n .I2(\\genblk7[5].compare_err_pb_latch_r_reg_n_0_[5] ),\n .I3(match_flag_pb[46]),\n .I4(match_flag_pb[44]),\n .I5(match_flag_pb[45]),\n .O(\\genblk8[5].right_gain_pb_reg[30]_0 ));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\genblk8[5].left_edge_pb[35]_i_3 \n (.I0(match_flag_pb[42]),\n .I1(match_flag_pb[43]),\n .I2(match_flag_pb[40]),\n .I3(match_flag_pb[41]),\n .O(\\genblk8[5].left_edge_pb[35]_i_3_n_0 ));\n FDRE \\genblk8[5].left_edge_pb_reg[30] \n (.C(CLK),\n .CE(\\genblk8[5].left_edge_pb[35]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[5].left_edge_pb_reg_n_0_[30] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[5].left_edge_pb_reg[31] \n (.C(CLK),\n .CE(\\genblk8[5].left_edge_pb[35]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[5].left_edge_pb_reg_n_0_[31] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[5].left_edge_pb_reg[32] \n (.C(CLK),\n .CE(\\genblk8[5].left_edge_pb[35]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[5].left_edge_pb_reg_n_0_[32] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[5].left_edge_pb_reg[33] \n (.C(CLK),\n .CE(\\genblk8[5].left_edge_pb[35]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[5].left_edge_pb_reg_n_0_[33] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[5].left_edge_pb_reg[34] \n (.C(CLK),\n .CE(\\genblk8[5].left_edge_pb[35]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[5].left_edge_pb_reg_n_0_[34] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[5].left_edge_pb_reg[35] \n (.C(CLK),\n .CE(\\genblk8[5].left_edge_pb[35]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[5]_i_3_n_0 ),\n .Q(\\genblk8[5].left_edge_pb_reg_n_0_[35] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[5].left_edge_updated_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[5].left_edge_updated_reg[5]_0 ),\n .Q(D[5]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAEFEAEAE)) \n \\genblk8[5].left_loss_pb[35]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(right_gain_pb),\n .I2(p_154_out),\n .I3(\\genblk8[5].left_loss_pb_reg[30]_0 ),\n .I4(\\genblk8[5].right_gain_pb_reg[30]_0 ),\n .O(\\genblk8[5].left_loss_pb[35]_i_1_n_0 ));\n FDRE \\genblk8[5].left_loss_pb_reg[30] \n (.C(CLK),\n .CE(\\genblk8[5].left_loss_pb[35]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[5].left_loss_pb_reg_n_0_[30] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[5].left_loss_pb_reg[31] \n (.C(CLK),\n .CE(\\genblk8[5].left_loss_pb[35]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[5].left_loss_pb_reg_n_0_[31] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[5].left_loss_pb_reg[32] \n (.C(CLK),\n .CE(\\genblk8[5].left_loss_pb[35]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[5].left_loss_pb_reg__0 [2]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[5].left_loss_pb_reg[33] \n (.C(CLK),\n .CE(\\genblk8[5].left_loss_pb[35]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[5].left_loss_pb_reg__0 [3]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[5].left_loss_pb_reg[34] \n (.C(CLK),\n .CE(\\genblk8[5].left_loss_pb[35]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[5].left_loss_pb_reg__0 [4]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[5].left_loss_pb_reg[35] \n (.C(CLK),\n .CE(\\genblk8[5].left_loss_pb[35]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[5]_i_2_n_0 ),\n .Q(\\genblk8[5].left_loss_pb_reg__0 [5]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDSE \\genblk8[5].match_flag_pb_reg[40] \n (.C(CLK),\n .CE(p_154_out),\n .D(\\genblk7[5].compare_err_pb_latch_r_reg_n_0_[5] ),\n .Q(match_flag_pb[40]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[5].match_flag_pb_reg[41] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[40]),\n .Q(match_flag_pb[41]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[5].match_flag_pb_reg[42] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[41]),\n .Q(match_flag_pb[42]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[5].match_flag_pb_reg[43] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[42]),\n .Q(match_flag_pb[43]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[5].match_flag_pb_reg[44] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[43]),\n .Q(match_flag_pb[44]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[5].match_flag_pb_reg[45] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[44]),\n .Q(match_flag_pb[45]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[5].match_flag_pb_reg[46] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[45]),\n .Q(match_flag_pb[46]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[5].match_flag_pb_reg[47] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[46]),\n .Q(match_flag_pb[47]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDRE \\genblk8[5].right_edge_found_pb_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[5].right_edge_found_pb_reg[5]_0 ),\n .Q(\\genblk8[5].right_edge_pb_reg[30]_0 ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAABAAAAAAAAA)) \n \\genblk8[5].right_edge_pb[35]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(\\genblk8[5].right_gain_pb_reg[30]_0 ),\n .I2(p_154_out),\n .I3(\\genblk8[5].right_edge_pb_reg[30]_1 ),\n .I4(\\genblk8[5].right_edge_pb_reg[30]_0 ),\n .I5(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .O(\\genblk8[5].right_edge_pb[35]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h08)) \n \\genblk8[5].right_edge_pb[35]_i_2 \n (.I0(p_154_out),\n .I1(\\genblk8[5].right_edge_pb_reg[30]_1 ),\n .I2(\\genblk8[5].right_gain_pb_reg[30]_0 ),\n .O(\\genblk8[5].right_edge_pb[35]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\genblk8[5].right_edge_pb[35]_i_3 \n (.I0(\\genblk7[5].compare_err_pb_latch_r_reg_n_0_[5] ),\n .I1(\\genblk8[5].left_edge_pb[35]_i_3_n_0 ),\n .I2(match_flag_pb[47]),\n .I3(match_flag_pb[46]),\n .I4(match_flag_pb[44]),\n .I5(match_flag_pb[45]),\n .O(\\genblk8[5].right_edge_pb_reg[30]_1 ));\n FDSE \\genblk8[5].right_edge_pb_reg[30] \n (.C(CLK),\n .CE(\\genblk8[5].right_edge_pb[35]_i_2_n_0 ),\n .D(\\genblk8[0].left_edge_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[5].right_edge_pb_reg_n_0_[30] ),\n .S(\\genblk8[5].right_edge_pb[35]_i_1_n_0 ));\n FDSE \\genblk8[5].right_edge_pb_reg[31] \n (.C(CLK),\n .CE(\\genblk8[5].right_edge_pb[35]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[5].right_edge_pb_reg_n_0_[31] ),\n .S(\\genblk8[5].right_edge_pb[35]_i_1_n_0 ));\n FDSE \\genblk8[5].right_edge_pb_reg[32] \n (.C(CLK),\n .CE(\\genblk8[5].right_edge_pb[35]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[5].right_edge_pb_reg_n_0_[32] ),\n .S(\\genblk8[5].right_edge_pb[35]_i_1_n_0 ));\n FDSE \\genblk8[5].right_edge_pb_reg[33] \n (.C(CLK),\n .CE(\\genblk8[5].right_edge_pb[35]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[5].right_edge_pb_reg_n_0_[33] ),\n .S(\\genblk8[5].right_edge_pb[35]_i_1_n_0 ));\n FDSE \\genblk8[5].right_edge_pb_reg[34] \n (.C(CLK),\n .CE(\\genblk8[5].right_edge_pb[35]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[5].right_edge_pb_reg_n_0_[34] ),\n .S(\\genblk8[5].right_edge_pb[35]_i_1_n_0 ));\n FDSE \\genblk8[5].right_edge_pb_reg[35] \n (.C(CLK),\n .CE(\\genblk8[5].right_edge_pb[35]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[5]_i_3_n_0 ),\n .Q(\\genblk8[5].right_edge_pb_reg_n_0_[35] ),\n .S(\\genblk8[5].right_edge_pb[35]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[5].right_gain_pb[30]_i_1 \n (.I0(\\genblk8[5].right_edge_pb_reg[30]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[5].right_gain_pb_reg[33]_i_2_n_7 ),\n .I3(\\genblk8[5].right_gain_pb_reg[33]_i_3_n_7 ),\n .O(\\genblk8[5].right_gain_pb[30]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[5].right_gain_pb[31]_i_1 \n (.I0(\\genblk8[5].right_edge_pb_reg[30]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[5].right_gain_pb_reg[33]_i_2_n_6 ),\n .I3(\\genblk8[5].right_gain_pb_reg[33]_i_3_n_6 ),\n .O(\\genblk8[5].right_gain_pb[31]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[5].right_gain_pb[32]_i_1 \n (.I0(\\genblk8[5].right_edge_pb_reg[30]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[5].right_gain_pb_reg[33]_i_2_n_5 ),\n .I3(\\genblk8[5].right_gain_pb_reg[33]_i_3_n_5 ),\n .O(\\genblk8[5].right_gain_pb[32]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[5].right_gain_pb[33]_i_1 \n (.I0(\\genblk8[5].right_edge_pb_reg[30]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[5].right_gain_pb_reg[33]_i_2_n_4 ),\n .I3(\\genblk8[5].right_gain_pb_reg[33]_i_3_n_4 ),\n .O(\\genblk8[5].right_gain_pb[33]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[5].right_gain_pb[33]_i_10 \n (.I0(right_edge_ref[1]),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[31] ),\n .O(\\genblk8[5].right_gain_pb[33]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[5].right_gain_pb[33]_i_11 \n (.I0(right_edge_ref[0]),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[30] ),\n .O(\\genblk8[5].right_gain_pb[33]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[5].right_gain_pb[33]_i_4 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[33] ),\n .O(\\genblk8[5].right_gain_pb[33]_i_4_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[5].right_gain_pb[33]_i_5 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[32] ),\n .O(\\genblk8[5].right_gain_pb[33]_i_5_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[5].right_gain_pb[33]_i_6 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[31] ),\n .O(\\genblk8[5].right_gain_pb[33]_i_6_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[5].right_gain_pb[33]_i_7 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[30] ),\n .O(\\genblk8[5].right_gain_pb[33]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[5].right_gain_pb[33]_i_8 \n (.I0(right_edge_ref[3]),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[33] ),\n .O(\\genblk8[5].right_gain_pb[33]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[5].right_gain_pb[33]_i_9 \n (.I0(right_edge_ref[2]),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[32] ),\n .O(\\genblk8[5].right_gain_pb[33]_i_9_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[5].right_gain_pb[34]_i_1 \n (.I0(\\genblk8[5].right_edge_pb_reg[30]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[5].right_gain_pb_reg[35]_i_5_n_7 ),\n .I3(\\genblk8[5].right_gain_pb_reg[35]_i_6_n_7 ),\n .O(\\genblk8[5].right_gain_pb[34]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAEFEAEAE)) \n \\genblk8[5].right_gain_pb[35]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(right_gain_pb),\n .I2(p_154_out),\n .I3(\\genblk8[5].right_gain_pb_reg[30]_0 ),\n .I4(\\genblk8[5].right_gain_pb_reg[35]_i_4_n_0 ),\n .O(\\genblk8[5].right_gain_pb[35]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[5].right_gain_pb[35]_i_10 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[34] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[5].right_gain_pb[35]_i_11 \n (.I0(right_edge_ref[5]),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[35] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[5].right_gain_pb[35]_i_12 \n (.I0(right_edge_ref[4]),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[34] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_12_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk8[5].right_gain_pb[35]_i_13 \n (.I0(\\genblk8[5].right_gain_pb[35]_i_16_n_0 ),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[33] ),\n .I2(right_edge_ref[3]),\n .I3(\\genblk8[5].right_edge_pb_reg_n_0_[34] ),\n .I4(right_edge_ref[4]),\n .O(\\genblk8[5].right_gain_pb[35]_i_13_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk8[5].right_gain_pb[35]_i_14 \n (.I0(\\genblk8[5].right_gain_pb[35]_i_17_n_0 ),\n .I1(right_edge_ref[3]),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[33] ),\n .I3(right_edge_ref[4]),\n .I4(\\genblk8[5].right_edge_pb_reg_n_0_[34] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk8[5].right_gain_pb[35]_i_16 \n (.I0(right_edge_ref[0]),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[30] ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[31] ),\n .I3(right_edge_ref[1]),\n .I4(\\genblk8[5].right_edge_pb_reg_n_0_[32] ),\n .I5(right_edge_ref[2]),\n .O(\\genblk8[5].right_gain_pb[35]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk8[5].right_gain_pb[35]_i_17 \n (.I0(\\genblk8[5].right_edge_pb_reg_n_0_[30] ),\n .I1(right_edge_ref[0]),\n .I2(right_edge_ref[1]),\n .I3(\\genblk8[5].right_edge_pb_reg_n_0_[31] ),\n .I4(right_edge_ref[2]),\n .I5(\\genblk8[5].right_edge_pb_reg_n_0_[32] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[5].right_gain_pb[35]_i_19 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_19_n_0 ));\n LUT5 #(\n .INIT(32'h000000A8)) \n \\genblk8[5].right_gain_pb[35]_i_2 \n (.I0(p_154_out),\n .I1(\\genblk8[5].right_edge_pb_reg[30]_1 ),\n .I2(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .I3(\\genblk8[5].right_edge_pb_reg[30]_0 ),\n .I4(\\genblk8[5].right_gain_pb_reg[30]_0 ),\n .O(\\genblk8[5].right_gain_pb[35]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[5].right_gain_pb[35]_i_20 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[5].right_gain_pb[35]_i_21 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_21_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[5].right_gain_pb[35]_i_22 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_22_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[5].right_gain_pb[35]_i_24 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_24_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[5].right_gain_pb[35]_i_25 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_25_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[5].right_gain_pb[35]_i_26 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_26_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[5].right_gain_pb[35]_i_27 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_27_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[5].right_gain_pb[35]_i_29 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_29_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[5].right_gain_pb[35]_i_3 \n (.I0(\\genblk8[5].right_edge_pb_reg[30]_1 ),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[5].right_gain_pb_reg[35]_i_5_n_6 ),\n .I3(\\genblk8[5].right_gain_pb_reg[35]_i_6_n_6 ),\n .O(\\genblk8[5].right_gain_pb[35]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[5].right_gain_pb[35]_i_30 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_30_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[5].right_gain_pb[35]_i_31 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_31_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[5].right_gain_pb[35]_i_32 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_32_n_0 ));\n LUT4 #(\n .INIT(16'hF880)) \n \\genblk8[5].right_gain_pb[35]_i_33 \n (.I0(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[34] ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[35] ),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[5].right_gain_pb[35]_i_33_n_0 ));\n LUT6 #(\n .INIT(64'h0808088CCECECEE0)) \n \\genblk8[5].right_gain_pb[35]_i_34 \n (.I0(\\genblk8[5].right_edge_pb_reg_n_0_[32] ),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[33] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[5].right_gain_pb[35]_i_34_n_0 ));\n LUT4 #(\n .INIT(16'h8CE0)) \n \\genblk8[5].right_gain_pb[35]_i_35 \n (.I0(\\genblk8[5].right_edge_pb_reg_n_0_[30] ),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[31] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\genblk8[5].right_gain_pb[35]_i_35_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[5].right_gain_pb[35]_i_36 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_36_n_0 ));\n LUT4 #(\n .INIT(16'h0660)) \n \\genblk8[5].right_gain_pb[35]_i_37 \n (.I0(\\genblk8[5].right_edge_pb_reg_n_0_[34] ),\n .I1(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[35] ),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[5].right_gain_pb[35]_i_37_n_0 ));\n LUT6 #(\n .INIT(64'h8484844221212118)) \n \\genblk8[5].right_gain_pb[35]_i_38 \n (.I0(\\genblk8[5].right_edge_pb_reg_n_0_[32] ),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[33] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[5].right_gain_pb[35]_i_38_n_0 ));\n LUT4 #(\n .INIT(16'h4218)) \n \\genblk8[5].right_gain_pb[35]_i_39 \n (.I0(\\genblk8[5].right_edge_pb_reg_n_0_[30] ),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[31] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\genblk8[5].right_gain_pb[35]_i_39_n_0 ));\n LUT5 #(\n .INIT(32'h04004404)) \n \\genblk8[5].right_gain_pb[35]_i_7 \n (.I0(\\genblk8[5].right_edge_pb_reg[30]_0 ),\n .I1(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .I2(right_edge_ref[5]),\n .I3(\\genblk8[5].right_edge_pb_reg_n_0_[35] ),\n .I4(\\genblk8[5].right_gain_pb[35]_i_13_n_0 ),\n .O(\\genblk8[5].right_gain_pb[35]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FFB200B2)) \n \\genblk8[5].right_gain_pb[35]_i_8 \n (.I0(\\genblk8[5].right_edge_pb_reg_n_0_[35] ),\n .I1(right_edge_ref[5]),\n .I2(\\genblk8[5].right_gain_pb[35]_i_14_n_0 ),\n .I3(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I4(\\genblk8[5].right_gain_pb_reg[35]_i_15_n_0 ),\n .I5(\\genblk8[5].right_edge_pb_reg[30]_0 ),\n .O(\\genblk8[5].right_gain_pb[35]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[5].right_gain_pb[35]_i_9 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .I1(\\genblk8[5].right_edge_pb_reg_n_0_[35] ),\n .O(\\genblk8[5].right_gain_pb[35]_i_9_n_0 ));\n FDRE \\genblk8[5].right_gain_pb_reg[30] \n (.C(CLK),\n .CE(\\genblk8[5].right_gain_pb[35]_i_2_n_0 ),\n .D(\\genblk8[5].right_gain_pb[30]_i_1_n_0 ),\n .Q(\\genblk8[5].right_gain_pb_reg_n_0_[30] ),\n .R(\\genblk8[5].right_gain_pb[35]_i_1_n_0 ));\n FDRE \\genblk8[5].right_gain_pb_reg[31] \n (.C(CLK),\n .CE(\\genblk8[5].right_gain_pb[35]_i_2_n_0 ),\n .D(\\genblk8[5].right_gain_pb[31]_i_1_n_0 ),\n .Q(\\genblk8[5].right_gain_pb_reg_n_0_[31] ),\n .R(\\genblk8[5].right_gain_pb[35]_i_1_n_0 ));\n FDRE \\genblk8[5].right_gain_pb_reg[32] \n (.C(CLK),\n .CE(\\genblk8[5].right_gain_pb[35]_i_2_n_0 ),\n .D(\\genblk8[5].right_gain_pb[32]_i_1_n_0 ),\n .Q(\\genblk8[5].right_gain_pb_reg__0 [2]),\n .R(\\genblk8[5].right_gain_pb[35]_i_1_n_0 ));\n FDRE \\genblk8[5].right_gain_pb_reg[33] \n (.C(CLK),\n .CE(\\genblk8[5].right_gain_pb[35]_i_2_n_0 ),\n .D(\\genblk8[5].right_gain_pb[33]_i_1_n_0 ),\n .Q(\\genblk8[5].right_gain_pb_reg__0 [3]),\n .R(\\genblk8[5].right_gain_pb[35]_i_1_n_0 ));\n CARRY4 \\genblk8[5].right_gain_pb_reg[33]_i_2 \n (.CI(1'b0),\n .CO({\\genblk8[5].right_gain_pb_reg[33]_i_2_n_0 ,\\genblk8[5].right_gain_pb_reg[33]_i_2_n_1 ,\\genblk8[5].right_gain_pb_reg[33]_i_2_n_2 ,\\genblk8[5].right_gain_pb_reg[33]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ,\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ,\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ,\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }),\n .O({\\genblk8[5].right_gain_pb_reg[33]_i_2_n_4 ,\\genblk8[5].right_gain_pb_reg[33]_i_2_n_5 ,\\genblk8[5].right_gain_pb_reg[33]_i_2_n_6 ,\\genblk8[5].right_gain_pb_reg[33]_i_2_n_7 }),\n .S({\\genblk8[5].right_gain_pb[33]_i_4_n_0 ,\\genblk8[5].right_gain_pb[33]_i_5_n_0 ,\\genblk8[5].right_gain_pb[33]_i_6_n_0 ,\\genblk8[5].right_gain_pb[33]_i_7_n_0 }));\n CARRY4 \\genblk8[5].right_gain_pb_reg[33]_i_3 \n (.CI(1'b0),\n .CO({\\genblk8[5].right_gain_pb_reg[33]_i_3_n_0 ,\\genblk8[5].right_gain_pb_reg[33]_i_3_n_1 ,\\genblk8[5].right_gain_pb_reg[33]_i_3_n_2 ,\\genblk8[5].right_gain_pb_reg[33]_i_3_n_3 }),\n .CYINIT(1'b1),\n .DI(right_edge_ref[3:0]),\n .O({\\genblk8[5].right_gain_pb_reg[33]_i_3_n_4 ,\\genblk8[5].right_gain_pb_reg[33]_i_3_n_5 ,\\genblk8[5].right_gain_pb_reg[33]_i_3_n_6 ,\\genblk8[5].right_gain_pb_reg[33]_i_3_n_7 }),\n .S({\\genblk8[5].right_gain_pb[33]_i_8_n_0 ,\\genblk8[5].right_gain_pb[33]_i_9_n_0 ,\\genblk8[5].right_gain_pb[33]_i_10_n_0 ,\\genblk8[5].right_gain_pb[33]_i_11_n_0 }));\n FDRE \\genblk8[5].right_gain_pb_reg[34] \n (.C(CLK),\n .CE(\\genblk8[5].right_gain_pb[35]_i_2_n_0 ),\n .D(\\genblk8[5].right_gain_pb[34]_i_1_n_0 ),\n .Q(\\genblk8[5].right_gain_pb_reg__0 [4]),\n .R(\\genblk8[5].right_gain_pb[35]_i_1_n_0 ));\n FDRE \\genblk8[5].right_gain_pb_reg[35] \n (.C(CLK),\n .CE(\\genblk8[5].right_gain_pb[35]_i_2_n_0 ),\n .D(\\genblk8[5].right_gain_pb[35]_i_3_n_0 ),\n .Q(\\genblk8[5].right_gain_pb_reg__0 [5]),\n .R(\\genblk8[5].right_gain_pb[35]_i_1_n_0 ));\n CARRY4 \\genblk8[5].right_gain_pb_reg[35]_i_15 \n (.CI(\\genblk8[5].right_gain_pb_reg[35]_i_18_n_0 ),\n .CO({\\genblk8[5].right_gain_pb_reg[35]_i_15_n_0 ,\\genblk8[5].right_gain_pb_reg[35]_i_15_n_1 ,\\genblk8[5].right_gain_pb_reg[35]_i_15_n_2 ,\\genblk8[5].right_gain_pb_reg[35]_i_15_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[5].right_gain_pb_reg[35]_i_15_O_UNCONNECTED [3:0]),\n .S({\\genblk8[5].right_gain_pb[35]_i_19_n_0 ,\\genblk8[5].right_gain_pb[35]_i_20_n_0 ,\\genblk8[5].right_gain_pb[35]_i_21_n_0 ,\\genblk8[5].right_gain_pb[35]_i_22_n_0 }));\n CARRY4 \\genblk8[5].right_gain_pb_reg[35]_i_18 \n (.CI(\\genblk8[5].right_gain_pb_reg[35]_i_23_n_0 ),\n .CO({\\genblk8[5].right_gain_pb_reg[35]_i_18_n_0 ,\\genblk8[5].right_gain_pb_reg[35]_i_18_n_1 ,\\genblk8[5].right_gain_pb_reg[35]_i_18_n_2 ,\\genblk8[5].right_gain_pb_reg[35]_i_18_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[5].right_gain_pb_reg[35]_i_18_O_UNCONNECTED [3:0]),\n .S({\\genblk8[5].right_gain_pb[35]_i_24_n_0 ,\\genblk8[5].right_gain_pb[35]_i_25_n_0 ,\\genblk8[5].right_gain_pb[35]_i_26_n_0 ,\\genblk8[5].right_gain_pb[35]_i_27_n_0 }));\n CARRY4 \\genblk8[5].right_gain_pb_reg[35]_i_23 \n (.CI(\\genblk8[5].right_gain_pb_reg[35]_i_28_n_0 ),\n .CO({\\genblk8[5].right_gain_pb_reg[35]_i_23_n_0 ,\\genblk8[5].right_gain_pb_reg[35]_i_23_n_1 ,\\genblk8[5].right_gain_pb_reg[35]_i_23_n_2 ,\\genblk8[5].right_gain_pb_reg[35]_i_23_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[5].right_gain_pb_reg[35]_i_23_O_UNCONNECTED [3:0]),\n .S({\\genblk8[5].right_gain_pb[35]_i_29_n_0 ,\\genblk8[5].right_gain_pb[35]_i_30_n_0 ,\\genblk8[5].right_gain_pb[35]_i_31_n_0 ,\\genblk8[5].right_gain_pb[35]_i_32_n_0 }));\n CARRY4 \\genblk8[5].right_gain_pb_reg[35]_i_28 \n (.CI(1'b0),\n .CO({\\genblk8[5].right_gain_pb_reg[35]_i_28_n_0 ,\\genblk8[5].right_gain_pb_reg[35]_i_28_n_1 ,\\genblk8[5].right_gain_pb_reg[35]_i_28_n_2 ,\\genblk8[5].right_gain_pb_reg[35]_i_28_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,\\genblk8[5].right_gain_pb[35]_i_33_n_0 ,\\genblk8[5].right_gain_pb[35]_i_34_n_0 ,\\genblk8[5].right_gain_pb[35]_i_35_n_0 }),\n .O(\\NLW_genblk8[5].right_gain_pb_reg[35]_i_28_O_UNCONNECTED [3:0]),\n .S({\\genblk8[5].right_gain_pb[35]_i_36_n_0 ,\\genblk8[5].right_gain_pb[35]_i_37_n_0 ,\\genblk8[5].right_gain_pb[35]_i_38_n_0 ,\\genblk8[5].right_gain_pb[35]_i_39_n_0 }));\n MUXF7 \\genblk8[5].right_gain_pb_reg[35]_i_4 \n (.I0(\\genblk8[5].right_gain_pb[35]_i_7_n_0 ),\n .I1(\\genblk8[5].right_gain_pb[35]_i_8_n_0 ),\n .O(\\genblk8[5].right_gain_pb_reg[35]_i_4_n_0 ),\n .S(\\genblk8[5].right_edge_pb_reg[30]_1 ));\n CARRY4 \\genblk8[5].right_gain_pb_reg[35]_i_5 \n (.CI(\\genblk8[5].right_gain_pb_reg[33]_i_2_n_0 ),\n .CO({\\NLW_genblk8[5].right_gain_pb_reg[35]_i_5_CO_UNCONNECTED [3:1],\\genblk8[5].right_gain_pb_reg[35]_i_5_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,\\prbs_dqs_tap_cnt_r_reg_n_0_[4] }),\n .O({\\NLW_genblk8[5].right_gain_pb_reg[35]_i_5_O_UNCONNECTED [3:2],\\genblk8[5].right_gain_pb_reg[35]_i_5_n_6 ,\\genblk8[5].right_gain_pb_reg[35]_i_5_n_7 }),\n .S({1'b0,1'b0,\\genblk8[5].right_gain_pb[35]_i_9_n_0 ,\\genblk8[5].right_gain_pb[35]_i_10_n_0 }));\n CARRY4 \\genblk8[5].right_gain_pb_reg[35]_i_6 \n (.CI(\\genblk8[5].right_gain_pb_reg[33]_i_3_n_0 ),\n .CO({\\NLW_genblk8[5].right_gain_pb_reg[35]_i_6_CO_UNCONNECTED [3:1],\\genblk8[5].right_gain_pb_reg[35]_i_6_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,right_edge_ref[4]}),\n .O({\\NLW_genblk8[5].right_gain_pb_reg[35]_i_6_O_UNCONNECTED [3:2],\\genblk8[5].right_gain_pb_reg[35]_i_6_n_6 ,\\genblk8[5].right_gain_pb_reg[35]_i_6_n_7 }),\n .S({1'b0,1'b0,\\genblk8[5].right_gain_pb[35]_i_11_n_0 ,\\genblk8[5].right_gain_pb[35]_i_12_n_0 }));\n FDRE \\genblk8[6].left_edge_found_pb_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[6].left_edge_found_pb_reg[6]_0 ),\n .Q(\\genblk8[6].left_loss_pb_reg[36]_0 ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\genblk8[6].left_edge_pb[41]_i_1 \n (.I0(p_154_out),\n .I1(p_106_out),\n .O(\\genblk8[6].left_edge_pb[41]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\genblk8[6].left_edge_pb[41]_i_2 \n (.I0(match_flag_pb[55]),\n .I1(\\genblk8[6].left_edge_pb[41]_i_3_n_0 ),\n .I2(\\genblk7[6].compare_err_pb_latch_r_reg_n_0_[6] ),\n .I3(match_flag_pb[54]),\n .I4(match_flag_pb[52]),\n .I5(match_flag_pb[53]),\n .O(p_106_out));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\genblk8[6].left_edge_pb[41]_i_3 \n (.I0(match_flag_pb[50]),\n .I1(match_flag_pb[51]),\n .I2(match_flag_pb[48]),\n .I3(match_flag_pb[49]),\n .O(\\genblk8[6].left_edge_pb[41]_i_3_n_0 ));\n FDRE \\genblk8[6].left_edge_pb_reg[36] \n (.C(CLK),\n .CE(\\genblk8[6].left_edge_pb[41]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[6].left_edge_pb_reg_n_0_[36] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[6].left_edge_pb_reg[37] \n (.C(CLK),\n .CE(\\genblk8[6].left_edge_pb[41]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[6].left_edge_pb_reg_n_0_[37] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[6].left_edge_pb_reg[38] \n (.C(CLK),\n .CE(\\genblk8[6].left_edge_pb[41]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[6].left_edge_pb_reg_n_0_[38] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[6].left_edge_pb_reg[39] \n (.C(CLK),\n .CE(\\genblk8[6].left_edge_pb[41]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[6].left_edge_pb_reg_n_0_[39] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[6].left_edge_pb_reg[40] \n (.C(CLK),\n .CE(\\genblk8[6].left_edge_pb[41]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[6].left_edge_pb_reg_n_0_[40] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[6].left_edge_pb_reg[41] \n (.C(CLK),\n .CE(\\genblk8[6].left_edge_pb[41]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[5]_i_3_n_0 ),\n .Q(\\genblk8[6].left_edge_pb_reg_n_0_[41] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[6].left_edge_updated_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[6].left_edge_updated_reg[6]_0 ),\n .Q(D[6]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAEFEAEAE)) \n \\genblk8[6].left_loss_pb[41]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(right_gain_pb),\n .I2(p_154_out),\n .I3(\\genblk8[6].left_loss_pb_reg[36]_0 ),\n .I4(p_106_out),\n .O(\\genblk8[6].left_loss_pb[41]_i_1_n_0 ));\n FDRE \\genblk8[6].left_loss_pb_reg[36] \n (.C(CLK),\n .CE(\\genblk8[6].left_loss_pb[41]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[6].left_loss_pb_reg_n_0_[36] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[6].left_loss_pb_reg[37] \n (.C(CLK),\n .CE(\\genblk8[6].left_loss_pb[41]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[6].left_loss_pb_reg_n_0_[37] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[6].left_loss_pb_reg[38] \n (.C(CLK),\n .CE(\\genblk8[6].left_loss_pb[41]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[6].left_loss_pb_reg__0 [2]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[6].left_loss_pb_reg[39] \n (.C(CLK),\n .CE(\\genblk8[6].left_loss_pb[41]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[6].left_loss_pb_reg__0 [3]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[6].left_loss_pb_reg[40] \n (.C(CLK),\n .CE(\\genblk8[6].left_loss_pb[41]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[6].left_loss_pb_reg__0 [4]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[6].left_loss_pb_reg[41] \n (.C(CLK),\n .CE(\\genblk8[6].left_loss_pb[41]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[5]_i_2_n_0 ),\n .Q(\\genblk8[6].left_loss_pb_reg__0 [5]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDSE \\genblk8[6].match_flag_pb_reg[48] \n (.C(CLK),\n .CE(p_154_out),\n .D(\\genblk7[6].compare_err_pb_latch_r_reg_n_0_[6] ),\n .Q(match_flag_pb[48]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[6].match_flag_pb_reg[49] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[48]),\n .Q(match_flag_pb[49]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[6].match_flag_pb_reg[50] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[49]),\n .Q(match_flag_pb[50]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[6].match_flag_pb_reg[51] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[50]),\n .Q(match_flag_pb[51]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[6].match_flag_pb_reg[52] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[51]),\n .Q(match_flag_pb[52]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[6].match_flag_pb_reg[53] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[52]),\n .Q(match_flag_pb[53]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[6].match_flag_pb_reg[54] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[53]),\n .Q(match_flag_pb[54]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[6].match_flag_pb_reg[55] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[54]),\n .Q(match_flag_pb[55]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDRE \\genblk8[6].right_edge_found_pb_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[6].right_edge_found_pb_reg[6]_0 ),\n .Q(\\genblk8[6].right_edge_pb_reg[36]_0 ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAABAAAAAAAAA)) \n \\genblk8[6].right_edge_pb[41]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(p_106_out),\n .I2(p_154_out),\n .I3(p_103_out),\n .I4(\\genblk8[6].right_edge_pb_reg[36]_0 ),\n .I5(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .O(\\genblk8[6].right_edge_pb[41]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h08)) \n \\genblk8[6].right_edge_pb[41]_i_2 \n (.I0(p_154_out),\n .I1(p_103_out),\n .I2(p_106_out),\n .O(\\genblk8[6].right_edge_pb[41]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\genblk8[6].right_edge_pb[41]_i_3 \n (.I0(\\genblk7[6].compare_err_pb_latch_r_reg_n_0_[6] ),\n .I1(\\genblk8[6].left_edge_pb[41]_i_3_n_0 ),\n .I2(match_flag_pb[55]),\n .I3(match_flag_pb[54]),\n .I4(match_flag_pb[52]),\n .I5(match_flag_pb[53]),\n .O(p_103_out));\n FDSE \\genblk8[6].right_edge_pb_reg[36] \n (.C(CLK),\n .CE(\\genblk8[6].right_edge_pb[41]_i_2_n_0 ),\n .D(\\genblk8[0].left_edge_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[6].right_edge_pb_reg_n_0_[36] ),\n .S(\\genblk8[6].right_edge_pb[41]_i_1_n_0 ));\n FDSE \\genblk8[6].right_edge_pb_reg[37] \n (.C(CLK),\n .CE(\\genblk8[6].right_edge_pb[41]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[6].right_edge_pb_reg_n_0_[37] ),\n .S(\\genblk8[6].right_edge_pb[41]_i_1_n_0 ));\n FDSE \\genblk8[6].right_edge_pb_reg[38] \n (.C(CLK),\n .CE(\\genblk8[6].right_edge_pb[41]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[6].right_edge_pb_reg_n_0_[38] ),\n .S(\\genblk8[6].right_edge_pb[41]_i_1_n_0 ));\n FDSE \\genblk8[6].right_edge_pb_reg[39] \n (.C(CLK),\n .CE(\\genblk8[6].right_edge_pb[41]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[6].right_edge_pb_reg_n_0_[39] ),\n .S(\\genblk8[6].right_edge_pb[41]_i_1_n_0 ));\n FDSE \\genblk8[6].right_edge_pb_reg[40] \n (.C(CLK),\n .CE(\\genblk8[6].right_edge_pb[41]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[6].right_edge_pb_reg_n_0_[40] ),\n .S(\\genblk8[6].right_edge_pb[41]_i_1_n_0 ));\n FDSE \\genblk8[6].right_edge_pb_reg[41] \n (.C(CLK),\n .CE(\\genblk8[6].right_edge_pb[41]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[5]_i_3_n_0 ),\n .Q(\\genblk8[6].right_edge_pb_reg_n_0_[41] ),\n .S(\\genblk8[6].right_edge_pb[41]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[6].right_gain_pb[36]_i_1 \n (.I0(p_103_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[6].right_gain_pb_reg[39]_i_2_n_7 ),\n .I3(\\genblk8[6].right_gain_pb_reg[39]_i_3_n_7 ),\n .O(\\genblk8[6].right_gain_pb[36]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[6].right_gain_pb[37]_i_1 \n (.I0(p_103_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[6].right_gain_pb_reg[39]_i_2_n_6 ),\n .I3(\\genblk8[6].right_gain_pb_reg[39]_i_3_n_6 ),\n .O(\\genblk8[6].right_gain_pb[37]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[6].right_gain_pb[38]_i_1 \n (.I0(p_103_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[6].right_gain_pb_reg[39]_i_2_n_5 ),\n .I3(\\genblk8[6].right_gain_pb_reg[39]_i_3_n_5 ),\n .O(\\genblk8[6].right_gain_pb[38]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[6].right_gain_pb[39]_i_1 \n (.I0(p_103_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[6].right_gain_pb_reg[39]_i_2_n_4 ),\n .I3(\\genblk8[6].right_gain_pb_reg[39]_i_3_n_4 ),\n .O(\\genblk8[6].right_gain_pb[39]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[6].right_gain_pb[39]_i_10 \n (.I0(right_edge_ref[1]),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[37] ),\n .O(\\genblk8[6].right_gain_pb[39]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[6].right_gain_pb[39]_i_11 \n (.I0(right_edge_ref[0]),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[36] ),\n .O(\\genblk8[6].right_gain_pb[39]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[6].right_gain_pb[39]_i_4 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[39] ),\n .O(\\genblk8[6].right_gain_pb[39]_i_4_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[6].right_gain_pb[39]_i_5 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[38] ),\n .O(\\genblk8[6].right_gain_pb[39]_i_5_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[6].right_gain_pb[39]_i_6 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[37] ),\n .O(\\genblk8[6].right_gain_pb[39]_i_6_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[6].right_gain_pb[39]_i_7 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[36] ),\n .O(\\genblk8[6].right_gain_pb[39]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[6].right_gain_pb[39]_i_8 \n (.I0(right_edge_ref[3]),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[39] ),\n .O(\\genblk8[6].right_gain_pb[39]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[6].right_gain_pb[39]_i_9 \n (.I0(right_edge_ref[2]),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[38] ),\n .O(\\genblk8[6].right_gain_pb[39]_i_9_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[6].right_gain_pb[40]_i_1 \n (.I0(p_103_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[6].right_gain_pb_reg[41]_i_5_n_7 ),\n .I3(\\genblk8[6].right_gain_pb_reg[41]_i_6_n_7 ),\n .O(\\genblk8[6].right_gain_pb[40]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAEFEAEAE)) \n \\genblk8[6].right_gain_pb[41]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(right_gain_pb),\n .I2(p_154_out),\n .I3(p_106_out),\n .I4(\\genblk8[6].right_gain_pb_reg[41]_i_4_n_0 ),\n .O(\\genblk8[6].right_gain_pb[41]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[6].right_gain_pb[41]_i_10 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[40] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[6].right_gain_pb[41]_i_11 \n (.I0(right_edge_ref[5]),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[41] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[6].right_gain_pb[41]_i_12 \n (.I0(right_edge_ref[4]),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[40] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_12_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk8[6].right_gain_pb[41]_i_13 \n (.I0(\\genblk8[6].right_gain_pb[41]_i_16_n_0 ),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[39] ),\n .I2(right_edge_ref[3]),\n .I3(\\genblk8[6].right_edge_pb_reg_n_0_[40] ),\n .I4(right_edge_ref[4]),\n .O(\\genblk8[6].right_gain_pb[41]_i_13_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk8[6].right_gain_pb[41]_i_14 \n (.I0(\\genblk8[6].right_gain_pb[41]_i_17_n_0 ),\n .I1(right_edge_ref[3]),\n .I2(\\genblk8[6].right_edge_pb_reg_n_0_[39] ),\n .I3(right_edge_ref[4]),\n .I4(\\genblk8[6].right_edge_pb_reg_n_0_[40] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk8[6].right_gain_pb[41]_i_16 \n (.I0(right_edge_ref[0]),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[36] ),\n .I2(\\genblk8[6].right_edge_pb_reg_n_0_[37] ),\n .I3(right_edge_ref[1]),\n .I4(\\genblk8[6].right_edge_pb_reg_n_0_[38] ),\n .I5(right_edge_ref[2]),\n .O(\\genblk8[6].right_gain_pb[41]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk8[6].right_gain_pb[41]_i_17 \n (.I0(\\genblk8[6].right_edge_pb_reg_n_0_[36] ),\n .I1(right_edge_ref[0]),\n .I2(right_edge_ref[1]),\n .I3(\\genblk8[6].right_edge_pb_reg_n_0_[37] ),\n .I4(right_edge_ref[2]),\n .I5(\\genblk8[6].right_edge_pb_reg_n_0_[38] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[6].right_gain_pb[41]_i_19 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_19_n_0 ));\n LUT5 #(\n .INIT(32'h000000A8)) \n \\genblk8[6].right_gain_pb[41]_i_2 \n (.I0(p_154_out),\n .I1(p_103_out),\n .I2(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .I3(\\genblk8[6].right_edge_pb_reg[36]_0 ),\n .I4(p_106_out),\n .O(\\genblk8[6].right_gain_pb[41]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[6].right_gain_pb[41]_i_20 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[6].right_gain_pb[41]_i_21 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_21_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[6].right_gain_pb[41]_i_22 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_22_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[6].right_gain_pb[41]_i_24 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_24_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[6].right_gain_pb[41]_i_25 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_25_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[6].right_gain_pb[41]_i_26 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_26_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[6].right_gain_pb[41]_i_27 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_27_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[6].right_gain_pb[41]_i_29 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_29_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[6].right_gain_pb[41]_i_3 \n (.I0(p_103_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[6].right_gain_pb_reg[41]_i_5_n_6 ),\n .I3(\\genblk8[6].right_gain_pb_reg[41]_i_6_n_6 ),\n .O(\\genblk8[6].right_gain_pb[41]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[6].right_gain_pb[41]_i_30 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_30_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[6].right_gain_pb[41]_i_31 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_31_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[6].right_gain_pb[41]_i_32 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_32_n_0 ));\n LUT4 #(\n .INIT(16'hF880)) \n \\genblk8[6].right_gain_pb[41]_i_33 \n (.I0(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[40] ),\n .I2(\\genblk8[6].right_edge_pb_reg_n_0_[41] ),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[6].right_gain_pb[41]_i_33_n_0 ));\n LUT6 #(\n .INIT(64'h0808088CCECECEE0)) \n \\genblk8[6].right_gain_pb[41]_i_34 \n (.I0(\\genblk8[6].right_edge_pb_reg_n_0_[38] ),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[39] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[6].right_gain_pb[41]_i_34_n_0 ));\n LUT4 #(\n .INIT(16'h8CE0)) \n \\genblk8[6].right_gain_pb[41]_i_35 \n (.I0(\\genblk8[6].right_edge_pb_reg_n_0_[36] ),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[37] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\genblk8[6].right_gain_pb[41]_i_35_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[6].right_gain_pb[41]_i_36 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_36_n_0 ));\n LUT4 #(\n .INIT(16'h0660)) \n \\genblk8[6].right_gain_pb[41]_i_37 \n (.I0(\\genblk8[6].right_edge_pb_reg_n_0_[40] ),\n .I1(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I2(\\genblk8[6].right_edge_pb_reg_n_0_[41] ),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[6].right_gain_pb[41]_i_37_n_0 ));\n LUT6 #(\n .INIT(64'h8484844221212118)) \n \\genblk8[6].right_gain_pb[41]_i_38 \n (.I0(\\genblk8[6].right_edge_pb_reg_n_0_[38] ),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[39] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[6].right_gain_pb[41]_i_38_n_0 ));\n LUT4 #(\n .INIT(16'h4218)) \n \\genblk8[6].right_gain_pb[41]_i_39 \n (.I0(\\genblk8[6].right_edge_pb_reg_n_0_[36] ),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[37] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\genblk8[6].right_gain_pb[41]_i_39_n_0 ));\n LUT5 #(\n .INIT(32'h04004404)) \n \\genblk8[6].right_gain_pb[41]_i_7 \n (.I0(\\genblk8[6].right_edge_pb_reg[36]_0 ),\n .I1(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .I2(right_edge_ref[5]),\n .I3(\\genblk8[6].right_edge_pb_reg_n_0_[41] ),\n .I4(\\genblk8[6].right_gain_pb[41]_i_13_n_0 ),\n .O(\\genblk8[6].right_gain_pb[41]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FFB200B2)) \n \\genblk8[6].right_gain_pb[41]_i_8 \n (.I0(\\genblk8[6].right_edge_pb_reg_n_0_[41] ),\n .I1(right_edge_ref[5]),\n .I2(\\genblk8[6].right_gain_pb[41]_i_14_n_0 ),\n .I3(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I4(\\genblk8[6].right_gain_pb_reg[41]_i_15_n_0 ),\n .I5(\\genblk8[6].right_edge_pb_reg[36]_0 ),\n .O(\\genblk8[6].right_gain_pb[41]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[6].right_gain_pb[41]_i_9 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .I1(\\genblk8[6].right_edge_pb_reg_n_0_[41] ),\n .O(\\genblk8[6].right_gain_pb[41]_i_9_n_0 ));\n FDRE \\genblk8[6].right_gain_pb_reg[36] \n (.C(CLK),\n .CE(\\genblk8[6].right_gain_pb[41]_i_2_n_0 ),\n .D(\\genblk8[6].right_gain_pb[36]_i_1_n_0 ),\n .Q(\\genblk8[6].right_gain_pb_reg_n_0_[36] ),\n .R(\\genblk8[6].right_gain_pb[41]_i_1_n_0 ));\n FDRE \\genblk8[6].right_gain_pb_reg[37] \n (.C(CLK),\n .CE(\\genblk8[6].right_gain_pb[41]_i_2_n_0 ),\n .D(\\genblk8[6].right_gain_pb[37]_i_1_n_0 ),\n .Q(\\genblk8[6].right_gain_pb_reg_n_0_[37] ),\n .R(\\genblk8[6].right_gain_pb[41]_i_1_n_0 ));\n FDRE \\genblk8[6].right_gain_pb_reg[38] \n (.C(CLK),\n .CE(\\genblk8[6].right_gain_pb[41]_i_2_n_0 ),\n .D(\\genblk8[6].right_gain_pb[38]_i_1_n_0 ),\n .Q(\\genblk8[6].right_gain_pb_reg__0 [2]),\n .R(\\genblk8[6].right_gain_pb[41]_i_1_n_0 ));\n FDRE \\genblk8[6].right_gain_pb_reg[39] \n (.C(CLK),\n .CE(\\genblk8[6].right_gain_pb[41]_i_2_n_0 ),\n .D(\\genblk8[6].right_gain_pb[39]_i_1_n_0 ),\n .Q(\\genblk8[6].right_gain_pb_reg__0 [3]),\n .R(\\genblk8[6].right_gain_pb[41]_i_1_n_0 ));\n CARRY4 \\genblk8[6].right_gain_pb_reg[39]_i_2 \n (.CI(1'b0),\n .CO({\\genblk8[6].right_gain_pb_reg[39]_i_2_n_0 ,\\genblk8[6].right_gain_pb_reg[39]_i_2_n_1 ,\\genblk8[6].right_gain_pb_reg[39]_i_2_n_2 ,\\genblk8[6].right_gain_pb_reg[39]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ,\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ,\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ,\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }),\n .O({\\genblk8[6].right_gain_pb_reg[39]_i_2_n_4 ,\\genblk8[6].right_gain_pb_reg[39]_i_2_n_5 ,\\genblk8[6].right_gain_pb_reg[39]_i_2_n_6 ,\\genblk8[6].right_gain_pb_reg[39]_i_2_n_7 }),\n .S({\\genblk8[6].right_gain_pb[39]_i_4_n_0 ,\\genblk8[6].right_gain_pb[39]_i_5_n_0 ,\\genblk8[6].right_gain_pb[39]_i_6_n_0 ,\\genblk8[6].right_gain_pb[39]_i_7_n_0 }));\n CARRY4 \\genblk8[6].right_gain_pb_reg[39]_i_3 \n (.CI(1'b0),\n .CO({\\genblk8[6].right_gain_pb_reg[39]_i_3_n_0 ,\\genblk8[6].right_gain_pb_reg[39]_i_3_n_1 ,\\genblk8[6].right_gain_pb_reg[39]_i_3_n_2 ,\\genblk8[6].right_gain_pb_reg[39]_i_3_n_3 }),\n .CYINIT(1'b1),\n .DI(right_edge_ref[3:0]),\n .O({\\genblk8[6].right_gain_pb_reg[39]_i_3_n_4 ,\\genblk8[6].right_gain_pb_reg[39]_i_3_n_5 ,\\genblk8[6].right_gain_pb_reg[39]_i_3_n_6 ,\\genblk8[6].right_gain_pb_reg[39]_i_3_n_7 }),\n .S({\\genblk8[6].right_gain_pb[39]_i_8_n_0 ,\\genblk8[6].right_gain_pb[39]_i_9_n_0 ,\\genblk8[6].right_gain_pb[39]_i_10_n_0 ,\\genblk8[6].right_gain_pb[39]_i_11_n_0 }));\n FDRE \\genblk8[6].right_gain_pb_reg[40] \n (.C(CLK),\n .CE(\\genblk8[6].right_gain_pb[41]_i_2_n_0 ),\n .D(\\genblk8[6].right_gain_pb[40]_i_1_n_0 ),\n .Q(\\genblk8[6].right_gain_pb_reg__0 [4]),\n .R(\\genblk8[6].right_gain_pb[41]_i_1_n_0 ));\n FDRE \\genblk8[6].right_gain_pb_reg[41] \n (.C(CLK),\n .CE(\\genblk8[6].right_gain_pb[41]_i_2_n_0 ),\n .D(\\genblk8[6].right_gain_pb[41]_i_3_n_0 ),\n .Q(\\genblk8[6].right_gain_pb_reg__0 [5]),\n .R(\\genblk8[6].right_gain_pb[41]_i_1_n_0 ));\n CARRY4 \\genblk8[6].right_gain_pb_reg[41]_i_15 \n (.CI(\\genblk8[6].right_gain_pb_reg[41]_i_18_n_0 ),\n .CO({\\genblk8[6].right_gain_pb_reg[41]_i_15_n_0 ,\\genblk8[6].right_gain_pb_reg[41]_i_15_n_1 ,\\genblk8[6].right_gain_pb_reg[41]_i_15_n_2 ,\\genblk8[6].right_gain_pb_reg[41]_i_15_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[6].right_gain_pb_reg[41]_i_15_O_UNCONNECTED [3:0]),\n .S({\\genblk8[6].right_gain_pb[41]_i_19_n_0 ,\\genblk8[6].right_gain_pb[41]_i_20_n_0 ,\\genblk8[6].right_gain_pb[41]_i_21_n_0 ,\\genblk8[6].right_gain_pb[41]_i_22_n_0 }));\n CARRY4 \\genblk8[6].right_gain_pb_reg[41]_i_18 \n (.CI(\\genblk8[6].right_gain_pb_reg[41]_i_23_n_0 ),\n .CO({\\genblk8[6].right_gain_pb_reg[41]_i_18_n_0 ,\\genblk8[6].right_gain_pb_reg[41]_i_18_n_1 ,\\genblk8[6].right_gain_pb_reg[41]_i_18_n_2 ,\\genblk8[6].right_gain_pb_reg[41]_i_18_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[6].right_gain_pb_reg[41]_i_18_O_UNCONNECTED [3:0]),\n .S({\\genblk8[6].right_gain_pb[41]_i_24_n_0 ,\\genblk8[6].right_gain_pb[41]_i_25_n_0 ,\\genblk8[6].right_gain_pb[41]_i_26_n_0 ,\\genblk8[6].right_gain_pb[41]_i_27_n_0 }));\n CARRY4 \\genblk8[6].right_gain_pb_reg[41]_i_23 \n (.CI(\\genblk8[6].right_gain_pb_reg[41]_i_28_n_0 ),\n .CO({\\genblk8[6].right_gain_pb_reg[41]_i_23_n_0 ,\\genblk8[6].right_gain_pb_reg[41]_i_23_n_1 ,\\genblk8[6].right_gain_pb_reg[41]_i_23_n_2 ,\\genblk8[6].right_gain_pb_reg[41]_i_23_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[6].right_gain_pb_reg[41]_i_23_O_UNCONNECTED [3:0]),\n .S({\\genblk8[6].right_gain_pb[41]_i_29_n_0 ,\\genblk8[6].right_gain_pb[41]_i_30_n_0 ,\\genblk8[6].right_gain_pb[41]_i_31_n_0 ,\\genblk8[6].right_gain_pb[41]_i_32_n_0 }));\n CARRY4 \\genblk8[6].right_gain_pb_reg[41]_i_28 \n (.CI(1'b0),\n .CO({\\genblk8[6].right_gain_pb_reg[41]_i_28_n_0 ,\\genblk8[6].right_gain_pb_reg[41]_i_28_n_1 ,\\genblk8[6].right_gain_pb_reg[41]_i_28_n_2 ,\\genblk8[6].right_gain_pb_reg[41]_i_28_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,\\genblk8[6].right_gain_pb[41]_i_33_n_0 ,\\genblk8[6].right_gain_pb[41]_i_34_n_0 ,\\genblk8[6].right_gain_pb[41]_i_35_n_0 }),\n .O(\\NLW_genblk8[6].right_gain_pb_reg[41]_i_28_O_UNCONNECTED [3:0]),\n .S({\\genblk8[6].right_gain_pb[41]_i_36_n_0 ,\\genblk8[6].right_gain_pb[41]_i_37_n_0 ,\\genblk8[6].right_gain_pb[41]_i_38_n_0 ,\\genblk8[6].right_gain_pb[41]_i_39_n_0 }));\n MUXF7 \\genblk8[6].right_gain_pb_reg[41]_i_4 \n (.I0(\\genblk8[6].right_gain_pb[41]_i_7_n_0 ),\n .I1(\\genblk8[6].right_gain_pb[41]_i_8_n_0 ),\n .O(\\genblk8[6].right_gain_pb_reg[41]_i_4_n_0 ),\n .S(p_103_out));\n CARRY4 \\genblk8[6].right_gain_pb_reg[41]_i_5 \n (.CI(\\genblk8[6].right_gain_pb_reg[39]_i_2_n_0 ),\n .CO({\\NLW_genblk8[6].right_gain_pb_reg[41]_i_5_CO_UNCONNECTED [3:1],\\genblk8[6].right_gain_pb_reg[41]_i_5_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,\\prbs_dqs_tap_cnt_r_reg_n_0_[4] }),\n .O({\\NLW_genblk8[6].right_gain_pb_reg[41]_i_5_O_UNCONNECTED [3:2],\\genblk8[6].right_gain_pb_reg[41]_i_5_n_6 ,\\genblk8[6].right_gain_pb_reg[41]_i_5_n_7 }),\n .S({1'b0,1'b0,\\genblk8[6].right_gain_pb[41]_i_9_n_0 ,\\genblk8[6].right_gain_pb[41]_i_10_n_0 }));\n CARRY4 \\genblk8[6].right_gain_pb_reg[41]_i_6 \n (.CI(\\genblk8[6].right_gain_pb_reg[39]_i_3_n_0 ),\n .CO({\\NLW_genblk8[6].right_gain_pb_reg[41]_i_6_CO_UNCONNECTED [3:1],\\genblk8[6].right_gain_pb_reg[41]_i_6_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,right_edge_ref[4]}),\n .O({\\NLW_genblk8[6].right_gain_pb_reg[41]_i_6_O_UNCONNECTED [3:2],\\genblk8[6].right_gain_pb_reg[41]_i_6_n_6 ,\\genblk8[6].right_gain_pb_reg[41]_i_6_n_7 }),\n .S({1'b0,1'b0,\\genblk8[6].right_gain_pb[41]_i_11_n_0 ,\\genblk8[6].right_gain_pb[41]_i_12_n_0 }));\n FDRE \\genblk8[7].left_edge_found_pb_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[7].left_edge_found_pb_reg[7]_0 ),\n .Q(\\genblk8[7].left_loss_pb_reg[42]_0 ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\genblk8[7].left_edge_pb[47]_i_1 \n (.I0(p_154_out),\n .I1(p_98_out),\n .O(\\genblk8[7].left_edge_pb[47]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\genblk8[7].left_edge_pb[47]_i_2 \n (.I0(match_flag_pb[63]),\n .I1(\\genblk8[7].left_edge_pb[47]_i_3_n_0 ),\n .I2(\\genblk7[7].compare_err_pb_latch_r_reg_n_0_[7] ),\n .I3(match_flag_pb[62]),\n .I4(match_flag_pb[60]),\n .I5(match_flag_pb[61]),\n .O(p_98_out));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\genblk8[7].left_edge_pb[47]_i_3 \n (.I0(match_flag_pb[58]),\n .I1(match_flag_pb[59]),\n .I2(match_flag_pb[56]),\n .I3(match_flag_pb[57]),\n .O(\\genblk8[7].left_edge_pb[47]_i_3_n_0 ));\n FDRE \\genblk8[7].left_edge_pb_reg[42] \n (.C(CLK),\n .CE(\\genblk8[7].left_edge_pb[47]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[7].left_edge_pb_reg_n_0_[42] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[7].left_edge_pb_reg[43] \n (.C(CLK),\n .CE(\\genblk8[7].left_edge_pb[47]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[7].left_edge_pb_reg_n_0_[43] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[7].left_edge_pb_reg[44] \n (.C(CLK),\n .CE(\\genblk8[7].left_edge_pb[47]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[7].left_edge_pb_reg_n_0_[44] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[7].left_edge_pb_reg[45] \n (.C(CLK),\n .CE(\\genblk8[7].left_edge_pb[47]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[7].left_edge_pb_reg_n_0_[45] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[7].left_edge_pb_reg[46] \n (.C(CLK),\n .CE(\\genblk8[7].left_edge_pb[47]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[7].left_edge_pb_reg_n_0_[46] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[7].left_edge_pb_reg[47] \n (.C(CLK),\n .CE(\\genblk8[7].left_edge_pb[47]_i_1_n_0 ),\n .D(\\genblk8[0].left_edge_pb[5]_i_3_n_0 ),\n .Q(\\genblk8[7].left_edge_pb_reg_n_0_[47] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[7].left_edge_updated_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[7].left_edge_updated_reg[7]_1 ),\n .Q(D[7]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAEFEAEAE)) \n \\genblk8[7].left_loss_pb[47]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(right_gain_pb),\n .I2(p_154_out),\n .I3(\\genblk8[7].left_loss_pb_reg[42]_0 ),\n .I4(p_98_out),\n .O(\\genblk8[7].left_loss_pb[47]_i_1_n_0 ));\n FDRE \\genblk8[7].left_loss_pb_reg[42] \n (.C(CLK),\n .CE(\\genblk8[7].left_loss_pb[47]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[7].left_loss_pb_reg_n_0_[42] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[7].left_loss_pb_reg[43] \n (.C(CLK),\n .CE(\\genblk8[7].left_loss_pb[47]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[7].left_loss_pb_reg_n_0_[43] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[7].left_loss_pb_reg[44] \n (.C(CLK),\n .CE(\\genblk8[7].left_loss_pb[47]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[7].left_loss_pb_reg__0 [2]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[7].left_loss_pb_reg[45] \n (.C(CLK),\n .CE(\\genblk8[7].left_loss_pb[47]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[7].left_loss_pb_reg__0 [3]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[7].left_loss_pb_reg[46] \n (.C(CLK),\n .CE(\\genblk8[7].left_loss_pb[47]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[7].left_loss_pb_reg__0 [4]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\genblk8[7].left_loss_pb_reg[47] \n (.C(CLK),\n .CE(\\genblk8[7].left_loss_pb[47]_i_1_n_0 ),\n .D(\\genblk8[0].left_loss_pb[5]_i_2_n_0 ),\n .Q(\\genblk8[7].left_loss_pb_reg__0 [5]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDSE \\genblk8[7].match_flag_pb_reg[56] \n (.C(CLK),\n .CE(p_154_out),\n .D(\\genblk7[7].compare_err_pb_latch_r_reg_n_0_[7] ),\n .Q(match_flag_pb[56]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[7].match_flag_pb_reg[57] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[56]),\n .Q(match_flag_pb[57]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[7].match_flag_pb_reg[58] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[57]),\n .Q(match_flag_pb[58]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[7].match_flag_pb_reg[59] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[58]),\n .Q(match_flag_pb[59]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[7].match_flag_pb_reg[60] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[59]),\n .Q(match_flag_pb[60]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[7].match_flag_pb_reg[61] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[60]),\n .Q(match_flag_pb[61]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[7].match_flag_pb_reg[62] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[61]),\n .Q(match_flag_pb[62]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDSE \\genblk8[7].match_flag_pb_reg[63] \n (.C(CLK),\n .CE(p_154_out),\n .D(match_flag_pb[62]),\n .Q(match_flag_pb[63]),\n .S(\\genblk8[0].match_flag_pb[7]_i_1_n_0 ));\n FDRE \\genblk8[7].right_edge_found_pb_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk8[7].right_edge_found_pb_reg[7]_0 ),\n .Q(\\genblk8[7].right_edge_pb_reg[42]_0 ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAABAAAAAAAAA)) \n \\genblk8[7].right_edge_pb[47]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(p_98_out),\n .I2(p_154_out),\n .I3(p_95_out),\n .I4(\\genblk8[7].right_edge_pb_reg[42]_0 ),\n .I5(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .O(\\genblk8[7].right_edge_pb[47]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h08)) \n \\genblk8[7].right_edge_pb[47]_i_2 \n (.I0(p_154_out),\n .I1(p_95_out),\n .I2(p_98_out),\n .O(\\genblk8[7].right_edge_pb[47]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\genblk8[7].right_edge_pb[47]_i_3 \n (.I0(\\genblk7[7].compare_err_pb_latch_r_reg_n_0_[7] ),\n .I1(\\genblk8[7].left_edge_pb[47]_i_3_n_0 ),\n .I2(match_flag_pb[63]),\n .I3(match_flag_pb[62]),\n .I4(match_flag_pb[60]),\n .I5(match_flag_pb[61]),\n .O(p_95_out));\n FDSE \\genblk8[7].right_edge_pb_reg[42] \n (.C(CLK),\n .CE(\\genblk8[7].right_edge_pb[47]_i_2_n_0 ),\n .D(\\genblk8[0].left_edge_pb[0]_i_1_n_0 ),\n .Q(\\genblk8[7].right_edge_pb_reg_n_0_[42] ),\n .S(\\genblk8[7].right_edge_pb[47]_i_1_n_0 ));\n FDSE \\genblk8[7].right_edge_pb_reg[43] \n (.C(CLK),\n .CE(\\genblk8[7].right_edge_pb[47]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[1]_i_1_n_0 ),\n .Q(\\genblk8[7].right_edge_pb_reg_n_0_[43] ),\n .S(\\genblk8[7].right_edge_pb[47]_i_1_n_0 ));\n FDSE \\genblk8[7].right_edge_pb_reg[44] \n (.C(CLK),\n .CE(\\genblk8[7].right_edge_pb[47]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[2]_i_1_n_0 ),\n .Q(\\genblk8[7].right_edge_pb_reg_n_0_[44] ),\n .S(\\genblk8[7].right_edge_pb[47]_i_1_n_0 ));\n FDSE \\genblk8[7].right_edge_pb_reg[45] \n (.C(CLK),\n .CE(\\genblk8[7].right_edge_pb[47]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[3]_i_1_n_0 ),\n .Q(\\genblk8[7].right_edge_pb_reg_n_0_[45] ),\n .S(\\genblk8[7].right_edge_pb[47]_i_1_n_0 ));\n FDSE \\genblk8[7].right_edge_pb_reg[46] \n (.C(CLK),\n .CE(\\genblk8[7].right_edge_pb[47]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[4]_i_1_n_0 ),\n .Q(\\genblk8[7].right_edge_pb_reg_n_0_[46] ),\n .S(\\genblk8[7].right_edge_pb[47]_i_1_n_0 ));\n FDSE \\genblk8[7].right_edge_pb_reg[47] \n (.C(CLK),\n .CE(\\genblk8[7].right_edge_pb[47]_i_2_n_0 ),\n .D(\\genblk8[0].right_edge_pb[5]_i_3_n_0 ),\n .Q(\\genblk8[7].right_edge_pb_reg_n_0_[47] ),\n .S(\\genblk8[7].right_edge_pb[47]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[7].right_gain_pb[42]_i_1 \n (.I0(p_95_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[7].right_gain_pb_reg[45]_i_2_n_7 ),\n .I3(\\genblk8[7].right_gain_pb_reg[45]_i_3_n_7 ),\n .O(\\genblk8[7].right_gain_pb[42]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[7].right_gain_pb[43]_i_1 \n (.I0(p_95_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[7].right_gain_pb_reg[45]_i_2_n_6 ),\n .I3(\\genblk8[7].right_gain_pb_reg[45]_i_3_n_6 ),\n .O(\\genblk8[7].right_gain_pb[43]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[7].right_gain_pb[44]_i_1 \n (.I0(p_95_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[7].right_gain_pb_reg[45]_i_2_n_5 ),\n .I3(\\genblk8[7].right_gain_pb_reg[45]_i_3_n_5 ),\n .O(\\genblk8[7].right_gain_pb[44]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[7].right_gain_pb[45]_i_1 \n (.I0(p_95_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[7].right_gain_pb_reg[45]_i_2_n_4 ),\n .I3(\\genblk8[7].right_gain_pb_reg[45]_i_3_n_4 ),\n .O(\\genblk8[7].right_gain_pb[45]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[7].right_gain_pb[45]_i_10 \n (.I0(right_edge_ref[1]),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[43] ),\n .O(\\genblk8[7].right_gain_pb[45]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[7].right_gain_pb[45]_i_11 \n (.I0(right_edge_ref[0]),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[42] ),\n .O(\\genblk8[7].right_gain_pb[45]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[7].right_gain_pb[45]_i_4 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[45] ),\n .O(\\genblk8[7].right_gain_pb[45]_i_4_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[7].right_gain_pb[45]_i_5 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[44] ),\n .O(\\genblk8[7].right_gain_pb[45]_i_5_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[7].right_gain_pb[45]_i_6 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[43] ),\n .O(\\genblk8[7].right_gain_pb[45]_i_6_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[7].right_gain_pb[45]_i_7 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[42] ),\n .O(\\genblk8[7].right_gain_pb[45]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[7].right_gain_pb[45]_i_8 \n (.I0(right_edge_ref[3]),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[45] ),\n .O(\\genblk8[7].right_gain_pb[45]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[7].right_gain_pb[45]_i_9 \n (.I0(right_edge_ref[2]),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[44] ),\n .O(\\genblk8[7].right_gain_pb[45]_i_9_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[7].right_gain_pb[46]_i_1 \n (.I0(p_95_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[7].right_gain_pb_reg[47]_i_5_n_7 ),\n .I3(\\genblk8[7].right_gain_pb_reg[47]_i_6_n_7 ),\n .O(\\genblk8[7].right_gain_pb[46]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hAEFEAEAE)) \n \\genblk8[7].right_gain_pb[47]_i_1 \n (.I0(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .I1(right_gain_pb),\n .I2(p_154_out),\n .I3(p_98_out),\n .I4(\\genblk8[7].right_gain_pb_reg[47]_i_4_n_0 ),\n .O(\\genblk8[7].right_gain_pb[47]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[7].right_gain_pb[47]_i_10 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[46] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[7].right_gain_pb[47]_i_11 \n (.I0(right_edge_ref[5]),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[47] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[7].right_gain_pb[47]_i_12 \n (.I0(right_edge_ref[4]),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[46] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_12_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk8[7].right_gain_pb[47]_i_13 \n (.I0(\\genblk8[7].right_gain_pb[47]_i_16_n_0 ),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[45] ),\n .I2(right_edge_ref[3]),\n .I3(\\genblk8[7].right_edge_pb_reg_n_0_[46] ),\n .I4(right_edge_ref[4]),\n .O(\\genblk8[7].right_gain_pb[47]_i_13_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk8[7].right_gain_pb[47]_i_14 \n (.I0(\\genblk8[7].right_gain_pb[47]_i_17_n_0 ),\n .I1(right_edge_ref[3]),\n .I2(\\genblk8[7].right_edge_pb_reg_n_0_[45] ),\n .I3(right_edge_ref[4]),\n .I4(\\genblk8[7].right_edge_pb_reg_n_0_[46] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk8[7].right_gain_pb[47]_i_16 \n (.I0(right_edge_ref[0]),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[42] ),\n .I2(\\genblk8[7].right_edge_pb_reg_n_0_[43] ),\n .I3(right_edge_ref[1]),\n .I4(\\genblk8[7].right_edge_pb_reg_n_0_[44] ),\n .I5(right_edge_ref[2]),\n .O(\\genblk8[7].right_gain_pb[47]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk8[7].right_gain_pb[47]_i_17 \n (.I0(\\genblk8[7].right_edge_pb_reg_n_0_[42] ),\n .I1(right_edge_ref[0]),\n .I2(right_edge_ref[1]),\n .I3(\\genblk8[7].right_edge_pb_reg_n_0_[43] ),\n .I4(right_edge_ref[2]),\n .I5(\\genblk8[7].right_edge_pb_reg_n_0_[44] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_17_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[7].right_gain_pb[47]_i_19 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_19_n_0 ));\n LUT5 #(\n .INIT(32'h000000A8)) \n \\genblk8[7].right_gain_pb[47]_i_2 \n (.I0(p_154_out),\n .I1(p_95_out),\n .I2(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .I3(\\genblk8[7].right_edge_pb_reg[42]_0 ),\n .I4(p_98_out),\n .O(\\genblk8[7].right_gain_pb[47]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[7].right_gain_pb[47]_i_20 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_20_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[7].right_gain_pb[47]_i_21 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_21_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[7].right_gain_pb[47]_i_22 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_22_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[7].right_gain_pb[47]_i_24 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_24_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[7].right_gain_pb[47]_i_25 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_25_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[7].right_gain_pb[47]_i_26 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_26_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[7].right_gain_pb[47]_i_27 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_27_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[7].right_gain_pb[47]_i_29 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_29_n_0 ));\n LUT4 #(\n .INIT(16'hF780)) \n \\genblk8[7].right_gain_pb[47]_i_3 \n (.I0(p_95_out),\n .I1(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I2(\\genblk8[7].right_gain_pb_reg[47]_i_5_n_6 ),\n .I3(\\genblk8[7].right_gain_pb_reg[47]_i_6_n_6 ),\n .O(\\genblk8[7].right_gain_pb[47]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[7].right_gain_pb[47]_i_30 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_30_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[7].right_gain_pb[47]_i_31 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_31_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[7].right_gain_pb[47]_i_32 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_32_n_0 ));\n LUT4 #(\n .INIT(16'hF880)) \n \\genblk8[7].right_gain_pb[47]_i_33 \n (.I0(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[46] ),\n .I2(\\genblk8[7].right_edge_pb_reg_n_0_[47] ),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[7].right_gain_pb[47]_i_33_n_0 ));\n LUT6 #(\n .INIT(64'h0808088CCECECEE0)) \n \\genblk8[7].right_gain_pb[47]_i_34 \n (.I0(\\genblk8[7].right_edge_pb_reg_n_0_[44] ),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[45] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[7].right_gain_pb[47]_i_34_n_0 ));\n LUT4 #(\n .INIT(16'h8CE0)) \n \\genblk8[7].right_gain_pb[47]_i_35 \n (.I0(\\genblk8[7].right_edge_pb_reg_n_0_[42] ),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[43] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\genblk8[7].right_gain_pb[47]_i_35_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\genblk8[7].right_gain_pb[47]_i_36 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_36_n_0 ));\n LUT4 #(\n .INIT(16'h0660)) \n \\genblk8[7].right_gain_pb[47]_i_37 \n (.I0(\\genblk8[7].right_edge_pb_reg_n_0_[46] ),\n .I1(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .I2(\\genblk8[7].right_edge_pb_reg_n_0_[47] ),\n .I3(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\genblk8[7].right_gain_pb[47]_i_37_n_0 ));\n LUT6 #(\n .INIT(64'h8484844221212118)) \n \\genblk8[7].right_gain_pb[47]_i_38 \n (.I0(\\genblk8[7].right_edge_pb_reg_n_0_[44] ),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[45] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\genblk8[7].right_gain_pb[47]_i_38_n_0 ));\n LUT4 #(\n .INIT(16'h4218)) \n \\genblk8[7].right_gain_pb[47]_i_39 \n (.I0(\\genblk8[7].right_edge_pb_reg_n_0_[42] ),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[43] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\genblk8[7].right_gain_pb[47]_i_39_n_0 ));\n LUT5 #(\n .INIT(32'h04004404)) \n \\genblk8[7].right_gain_pb[47]_i_7 \n (.I0(\\genblk8[7].right_edge_pb_reg[42]_0 ),\n .I1(\\genblk8[7].right_edge_pb_reg[42]_1 ),\n .I2(right_edge_ref[5]),\n .I3(\\genblk8[7].right_edge_pb_reg_n_0_[47] ),\n .I4(\\genblk8[7].right_gain_pb[47]_i_13_n_0 ),\n .O(\\genblk8[7].right_gain_pb[47]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FFB200B2)) \n \\genblk8[7].right_gain_pb[47]_i_8 \n (.I0(\\genblk8[7].right_edge_pb_reg_n_0_[47] ),\n .I1(right_edge_ref[5]),\n .I2(\\genblk8[7].right_gain_pb[47]_i_14_n_0 ),\n .I3(\\genblk8[0].right_gain_pb_reg[5]_i_5_n_0 ),\n .I4(\\genblk8[7].right_gain_pb_reg[47]_i_15_n_0 ),\n .I5(\\genblk8[7].right_edge_pb_reg[42]_0 ),\n .O(\\genblk8[7].right_gain_pb[47]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\genblk8[7].right_gain_pb[47]_i_9 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .I1(\\genblk8[7].right_edge_pb_reg_n_0_[47] ),\n .O(\\genblk8[7].right_gain_pb[47]_i_9_n_0 ));\n FDRE \\genblk8[7].right_gain_pb_reg[42] \n (.C(CLK),\n .CE(\\genblk8[7].right_gain_pb[47]_i_2_n_0 ),\n .D(\\genblk8[7].right_gain_pb[42]_i_1_n_0 ),\n .Q(\\genblk8[7].right_gain_pb_reg_n_0_[42] ),\n .R(\\genblk8[7].right_gain_pb[47]_i_1_n_0 ));\n FDRE \\genblk8[7].right_gain_pb_reg[43] \n (.C(CLK),\n .CE(\\genblk8[7].right_gain_pb[47]_i_2_n_0 ),\n .D(\\genblk8[7].right_gain_pb[43]_i_1_n_0 ),\n .Q(\\genblk8[7].right_gain_pb_reg_n_0_[43] ),\n .R(\\genblk8[7].right_gain_pb[47]_i_1_n_0 ));\n FDRE \\genblk8[7].right_gain_pb_reg[44] \n (.C(CLK),\n .CE(\\genblk8[7].right_gain_pb[47]_i_2_n_0 ),\n .D(\\genblk8[7].right_gain_pb[44]_i_1_n_0 ),\n .Q(\\genblk8[7].right_gain_pb_reg__0 [2]),\n .R(\\genblk8[7].right_gain_pb[47]_i_1_n_0 ));\n FDRE \\genblk8[7].right_gain_pb_reg[45] \n (.C(CLK),\n .CE(\\genblk8[7].right_gain_pb[47]_i_2_n_0 ),\n .D(\\genblk8[7].right_gain_pb[45]_i_1_n_0 ),\n .Q(\\genblk8[7].right_gain_pb_reg__0 [3]),\n .R(\\genblk8[7].right_gain_pb[47]_i_1_n_0 ));\n CARRY4 \\genblk8[7].right_gain_pb_reg[45]_i_2 \n (.CI(1'b0),\n .CO({\\genblk8[7].right_gain_pb_reg[45]_i_2_n_0 ,\\genblk8[7].right_gain_pb_reg[45]_i_2_n_1 ,\\genblk8[7].right_gain_pb_reg[45]_i_2_n_2 ,\\genblk8[7].right_gain_pb_reg[45]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ,\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ,\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ,\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 }),\n .O({\\genblk8[7].right_gain_pb_reg[45]_i_2_n_4 ,\\genblk8[7].right_gain_pb_reg[45]_i_2_n_5 ,\\genblk8[7].right_gain_pb_reg[45]_i_2_n_6 ,\\genblk8[7].right_gain_pb_reg[45]_i_2_n_7 }),\n .S({\\genblk8[7].right_gain_pb[45]_i_4_n_0 ,\\genblk8[7].right_gain_pb[45]_i_5_n_0 ,\\genblk8[7].right_gain_pb[45]_i_6_n_0 ,\\genblk8[7].right_gain_pb[45]_i_7_n_0 }));\n CARRY4 \\genblk8[7].right_gain_pb_reg[45]_i_3 \n (.CI(1'b0),\n .CO({\\genblk8[7].right_gain_pb_reg[45]_i_3_n_0 ,\\genblk8[7].right_gain_pb_reg[45]_i_3_n_1 ,\\genblk8[7].right_gain_pb_reg[45]_i_3_n_2 ,\\genblk8[7].right_gain_pb_reg[45]_i_3_n_3 }),\n .CYINIT(1'b1),\n .DI(right_edge_ref[3:0]),\n .O({\\genblk8[7].right_gain_pb_reg[45]_i_3_n_4 ,\\genblk8[7].right_gain_pb_reg[45]_i_3_n_5 ,\\genblk8[7].right_gain_pb_reg[45]_i_3_n_6 ,\\genblk8[7].right_gain_pb_reg[45]_i_3_n_7 }),\n .S({\\genblk8[7].right_gain_pb[45]_i_8_n_0 ,\\genblk8[7].right_gain_pb[45]_i_9_n_0 ,\\genblk8[7].right_gain_pb[45]_i_10_n_0 ,\\genblk8[7].right_gain_pb[45]_i_11_n_0 }));\n FDRE \\genblk8[7].right_gain_pb_reg[46] \n (.C(CLK),\n .CE(\\genblk8[7].right_gain_pb[47]_i_2_n_0 ),\n .D(\\genblk8[7].right_gain_pb[46]_i_1_n_0 ),\n .Q(\\genblk8[7].right_gain_pb_reg__0 [4]),\n .R(\\genblk8[7].right_gain_pb[47]_i_1_n_0 ));\n FDRE \\genblk8[7].right_gain_pb_reg[47] \n (.C(CLK),\n .CE(\\genblk8[7].right_gain_pb[47]_i_2_n_0 ),\n .D(\\genblk8[7].right_gain_pb[47]_i_3_n_0 ),\n .Q(\\genblk8[7].right_gain_pb_reg__0 [5]),\n .R(\\genblk8[7].right_gain_pb[47]_i_1_n_0 ));\n CARRY4 \\genblk8[7].right_gain_pb_reg[47]_i_15 \n (.CI(\\genblk8[7].right_gain_pb_reg[47]_i_18_n_0 ),\n .CO({\\genblk8[7].right_gain_pb_reg[47]_i_15_n_0 ,\\genblk8[7].right_gain_pb_reg[47]_i_15_n_1 ,\\genblk8[7].right_gain_pb_reg[47]_i_15_n_2 ,\\genblk8[7].right_gain_pb_reg[47]_i_15_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[7].right_gain_pb_reg[47]_i_15_O_UNCONNECTED [3:0]),\n .S({\\genblk8[7].right_gain_pb[47]_i_19_n_0 ,\\genblk8[7].right_gain_pb[47]_i_20_n_0 ,\\genblk8[7].right_gain_pb[47]_i_21_n_0 ,\\genblk8[7].right_gain_pb[47]_i_22_n_0 }));\n CARRY4 \\genblk8[7].right_gain_pb_reg[47]_i_18 \n (.CI(\\genblk8[7].right_gain_pb_reg[47]_i_23_n_0 ),\n .CO({\\genblk8[7].right_gain_pb_reg[47]_i_18_n_0 ,\\genblk8[7].right_gain_pb_reg[47]_i_18_n_1 ,\\genblk8[7].right_gain_pb_reg[47]_i_18_n_2 ,\\genblk8[7].right_gain_pb_reg[47]_i_18_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[7].right_gain_pb_reg[47]_i_18_O_UNCONNECTED [3:0]),\n .S({\\genblk8[7].right_gain_pb[47]_i_24_n_0 ,\\genblk8[7].right_gain_pb[47]_i_25_n_0 ,\\genblk8[7].right_gain_pb[47]_i_26_n_0 ,\\genblk8[7].right_gain_pb[47]_i_27_n_0 }));\n CARRY4 \\genblk8[7].right_gain_pb_reg[47]_i_23 \n (.CI(\\genblk8[7].right_gain_pb_reg[47]_i_28_n_0 ),\n .CO({\\genblk8[7].right_gain_pb_reg[47]_i_23_n_0 ,\\genblk8[7].right_gain_pb_reg[47]_i_23_n_1 ,\\genblk8[7].right_gain_pb_reg[47]_i_23_n_2 ,\\genblk8[7].right_gain_pb_reg[47]_i_23_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(\\NLW_genblk8[7].right_gain_pb_reg[47]_i_23_O_UNCONNECTED [3:0]),\n .S({\\genblk8[7].right_gain_pb[47]_i_29_n_0 ,\\genblk8[7].right_gain_pb[47]_i_30_n_0 ,\\genblk8[7].right_gain_pb[47]_i_31_n_0 ,\\genblk8[7].right_gain_pb[47]_i_32_n_0 }));\n CARRY4 \\genblk8[7].right_gain_pb_reg[47]_i_28 \n (.CI(1'b0),\n .CO({\\genblk8[7].right_gain_pb_reg[47]_i_28_n_0 ,\\genblk8[7].right_gain_pb_reg[47]_i_28_n_1 ,\\genblk8[7].right_gain_pb_reg[47]_i_28_n_2 ,\\genblk8[7].right_gain_pb_reg[47]_i_28_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,\\genblk8[7].right_gain_pb[47]_i_33_n_0 ,\\genblk8[7].right_gain_pb[47]_i_34_n_0 ,\\genblk8[7].right_gain_pb[47]_i_35_n_0 }),\n .O(\\NLW_genblk8[7].right_gain_pb_reg[47]_i_28_O_UNCONNECTED [3:0]),\n .S({\\genblk8[7].right_gain_pb[47]_i_36_n_0 ,\\genblk8[7].right_gain_pb[47]_i_37_n_0 ,\\genblk8[7].right_gain_pb[47]_i_38_n_0 ,\\genblk8[7].right_gain_pb[47]_i_39_n_0 }));\n MUXF7 \\genblk8[7].right_gain_pb_reg[47]_i_4 \n (.I0(\\genblk8[7].right_gain_pb[47]_i_7_n_0 ),\n .I1(\\genblk8[7].right_gain_pb[47]_i_8_n_0 ),\n .O(\\genblk8[7].right_gain_pb_reg[47]_i_4_n_0 ),\n .S(p_95_out));\n CARRY4 \\genblk8[7].right_gain_pb_reg[47]_i_5 \n (.CI(\\genblk8[7].right_gain_pb_reg[45]_i_2_n_0 ),\n .CO({\\NLW_genblk8[7].right_gain_pb_reg[47]_i_5_CO_UNCONNECTED [3:1],\\genblk8[7].right_gain_pb_reg[47]_i_5_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,\\prbs_dqs_tap_cnt_r_reg_n_0_[4] }),\n .O({\\NLW_genblk8[7].right_gain_pb_reg[47]_i_5_O_UNCONNECTED [3:2],\\genblk8[7].right_gain_pb_reg[47]_i_5_n_6 ,\\genblk8[7].right_gain_pb_reg[47]_i_5_n_7 }),\n .S({1'b0,1'b0,\\genblk8[7].right_gain_pb[47]_i_9_n_0 ,\\genblk8[7].right_gain_pb[47]_i_10_n_0 }));\n CARRY4 \\genblk8[7].right_gain_pb_reg[47]_i_6 \n (.CI(\\genblk8[7].right_gain_pb_reg[45]_i_3_n_0 ),\n .CO({\\NLW_genblk8[7].right_gain_pb_reg[47]_i_6_CO_UNCONNECTED [3:1],\\genblk8[7].right_gain_pb_reg[47]_i_6_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,right_edge_ref[4]}),\n .O({\\NLW_genblk8[7].right_gain_pb_reg[47]_i_6_O_UNCONNECTED [3:2],\\genblk8[7].right_gain_pb_reg[47]_i_6_n_6 ,\\genblk8[7].right_gain_pb_reg[47]_i_6_n_7 }),\n .S({1'b0,1'b0,\\genblk8[7].right_gain_pb[47]_i_11_n_0 ,\\genblk8[7].right_gain_pb[47]_i_12_n_0 }));\n LUT6 #(\n .INIT(64'h00000000AAAAAAA2)) \n \\genblk9[0].fine_delay_incdec_pb[0]_i_1 \n (.I0(\\genblk9[0].fine_delay_incdec_pb[0]_i_2_n_0 ),\n .I1(bit_cnt),\n .I2(\\genblk9[0].fine_delay_incdec_pb[0]_i_4_n_0 ),\n .I3(\\stage_cnt_reg_n_0_[0] ),\n .I4(\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ),\n .I5(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .O(\\genblk9[0].fine_delay_incdec_pb[0]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\genblk9[0].fine_delay_incdec_pb[0]_i_10 \n (.I0(ref_bit[6]),\n .I1(ref_bit[7]),\n .I2(ref_bit[4]),\n .I3(ref_bit[5]),\n .O(\\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk9[0].fine_delay_incdec_pb[0]_i_11 \n (.I0(\\genblk8[0].right_gain_pb_reg_n_0_[0] ),\n .I1(\\genblk8[0].left_loss_pb_reg_n_0_[0] ),\n .I2(\\genblk8[0].left_loss_pb_reg_n_0_[1] ),\n .I3(\\genblk8[0].right_gain_pb_reg_n_0_[1] ),\n .I4(\\genblk8[0].left_loss_pb_reg__0 [2]),\n .I5(\\genblk8[0].right_gain_pb_reg__0 [2]),\n .O(\\genblk9[0].fine_delay_incdec_pb[0]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'hFFB2FFFFFFB20000)) \n \\genblk9[0].fine_delay_incdec_pb[0]_i_2 \n (.I0(\\genblk8[0].right_gain_pb_reg__0 [5]),\n .I1(\\genblk8[0].left_loss_pb_reg__0 [5]),\n .I2(\\genblk9[0].fine_delay_incdec_pb[0]_i_5_n_0 ),\n .I3(\\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ),\n .I4(\\stage_cnt_reg[1]_0 ),\n .I5(\\fine_delay_mod_reg[26] ),\n .O(\\genblk9[0].fine_delay_incdec_pb[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000200)) \n \\genblk9[0].fine_delay_incdec_pb[0]_i_3 \n (.I0(bit_cnt_reg__0[3]),\n .I1(bit_cnt_reg__0[0]),\n .I2(bit_cnt_reg__0[4]),\n .I3(p_1_in159_in),\n .I4(bit_cnt_reg__0[2]),\n .I5(\\genblk9[0].fine_delay_incdec_pb[0]_i_9_n_0 ),\n .O(bit_cnt));\n (* SOFT_HLUTNM = \"soft_lutpair37\" *) \n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n \\genblk9[0].fine_delay_incdec_pb[0]_i_4 \n (.I0(\\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ),\n .I1(\\ref_bit_reg_n_0_[1] ),\n .I2(\\ref_bit_reg_n_0_[0] ),\n .I3(ref_bit[3]),\n .I4(\\ref_bit_reg_n_0_[2] ),\n .O(\\genblk9[0].fine_delay_incdec_pb[0]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk9[0].fine_delay_incdec_pb[0]_i_5 \n (.I0(\\genblk9[0].fine_delay_incdec_pb[0]_i_11_n_0 ),\n .I1(\\genblk8[0].left_loss_pb_reg__0 [3]),\n .I2(\\genblk8[0].right_gain_pb_reg__0 [3]),\n .I3(\\genblk8[0].left_loss_pb_reg__0 [4]),\n .I4(\\genblk8[0].right_gain_pb_reg__0 [4]),\n .O(\\genblk9[0].fine_delay_incdec_pb[0]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair75\" *) \n LUT3 #(\n .INIT(8'h02)) \n \\genblk9[0].fine_delay_incdec_pb[0]_i_6 \n (.I0(bit_cnt),\n .I1(\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ),\n .I2(\\stage_cnt_reg_n_0_[0] ),\n .O(\\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair18\" *) \n LUT5 #(\n .INIT(32'h04000000)) \n \\genblk9[0].fine_delay_incdec_pb[0]_i_8 \n (.I0(Q[3]),\n .I1(Q[4]),\n .I2(Q[2]),\n .I3(Q[0]),\n .I4(Q[1]),\n .O(p_1_in159_in));\n (* SOFT_HLUTNM = \"soft_lutpair55\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n \\genblk9[0].fine_delay_incdec_pb[0]_i_9 \n (.I0(bit_cnt_reg__0[1]),\n .I1(bit_cnt_reg__0[7]),\n .I2(bit_cnt_reg__0[5]),\n .I3(bit_cnt_reg__0[6]),\n .O(\\genblk9[0].fine_delay_incdec_pb[0]_i_9_n_0 ));\n FDRE \\genblk9[0].fine_delay_incdec_pb_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk9[0].fine_delay_incdec_pb[0]_i_1_n_0 ),\n .Q(\\fine_delay_mod_reg[26] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000AAA8AAAA)) \n \\genblk9[1].fine_delay_incdec_pb[1]_i_1 \n (.I0(\\genblk9[1].fine_delay_incdec_pb[1]_i_2_n_0 ),\n .I1(\\genblk9[1].fine_delay_incdec_pb[1]_i_3_n_0 ),\n .I2(\\stage_cnt_reg_n_0_[0] ),\n .I3(\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ),\n .I4(bit_cnt),\n .I5(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .O(\\genblk9[1].fine_delay_incdec_pb[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFB2FFFFFFB20000)) \n \\genblk9[1].fine_delay_incdec_pb[1]_i_2 \n (.I0(\\genblk8[1].right_gain_pb_reg__0 [5]),\n .I1(\\genblk8[1].left_loss_pb_reg__0 [5]),\n .I2(\\genblk9[1].fine_delay_incdec_pb[1]_i_4_n_0 ),\n .I3(\\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ),\n .I4(\\stage_cnt_reg[1]_0 ),\n .I5(\\genblk9[1].fine_delay_incdec_pb_reg[1]_0 ),\n .O(\\genblk9[1].fine_delay_incdec_pb[1]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair38\" *) \n LUT5 #(\n .INIT(32'hFFFFFFEF)) \n \\genblk9[1].fine_delay_incdec_pb[1]_i_3 \n (.I0(\\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ),\n .I1(\\ref_bit_reg_n_0_[1] ),\n .I2(\\ref_bit_reg_n_0_[0] ),\n .I3(ref_bit[3]),\n .I4(\\ref_bit_reg_n_0_[2] ),\n .O(\\genblk9[1].fine_delay_incdec_pb[1]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk9[1].fine_delay_incdec_pb[1]_i_4 \n (.I0(\\genblk9[1].fine_delay_incdec_pb[1]_i_5_n_0 ),\n .I1(\\genblk8[1].left_loss_pb_reg__0 [3]),\n .I2(\\genblk8[1].right_gain_pb_reg__0 [3]),\n .I3(\\genblk8[1].left_loss_pb_reg__0 [4]),\n .I4(\\genblk8[1].right_gain_pb_reg__0 [4]),\n .O(\\genblk9[1].fine_delay_incdec_pb[1]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk9[1].fine_delay_incdec_pb[1]_i_5 \n (.I0(\\genblk8[1].right_gain_pb_reg_n_0_[6] ),\n .I1(\\genblk8[1].left_loss_pb_reg_n_0_[6] ),\n .I2(\\genblk8[1].left_loss_pb_reg_n_0_[7] ),\n .I3(\\genblk8[1].right_gain_pb_reg_n_0_[7] ),\n .I4(\\genblk8[1].left_loss_pb_reg__0 [2]),\n .I5(\\genblk8[1].right_gain_pb_reg__0 [2]),\n .O(\\genblk9[1].fine_delay_incdec_pb[1]_i_5_n_0 ));\n FDRE \\genblk9[1].fine_delay_incdec_pb_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk9[1].fine_delay_incdec_pb[1]_i_1_n_0 ),\n .Q(\\genblk9[1].fine_delay_incdec_pb_reg[1]_0 ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000AAA8AAAA)) \n \\genblk9[2].fine_delay_incdec_pb[2]_i_1 \n (.I0(\\genblk9[2].fine_delay_incdec_pb[2]_i_2_n_0 ),\n .I1(\\genblk9[2].fine_delay_incdec_pb[2]_i_3_n_0 ),\n .I2(\\stage_cnt_reg_n_0_[0] ),\n .I3(\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ),\n .I4(bit_cnt),\n .I5(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .O(\\genblk9[2].fine_delay_incdec_pb[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFB2FFFFFFB20000)) \n \\genblk9[2].fine_delay_incdec_pb[2]_i_2 \n (.I0(\\genblk8[2].right_gain_pb_reg__0 [5]),\n .I1(\\genblk8[2].left_loss_pb_reg__0 [5]),\n .I2(\\genblk9[2].fine_delay_incdec_pb[2]_i_4_n_0 ),\n .I3(\\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ),\n .I4(\\stage_cnt_reg[1]_0 ),\n .I5(\\genblk9[2].fine_delay_incdec_pb_reg[2]_0 ),\n .O(\\genblk9[2].fine_delay_incdec_pb[2]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair37\" *) \n LUT5 #(\n .INIT(32'hFFFFFFEF)) \n \\genblk9[2].fine_delay_incdec_pb[2]_i_3 \n (.I0(\\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ),\n .I1(\\ref_bit_reg_n_0_[0] ),\n .I2(\\ref_bit_reg_n_0_[1] ),\n .I3(ref_bit[3]),\n .I4(\\ref_bit_reg_n_0_[2] ),\n .O(\\genblk9[2].fine_delay_incdec_pb[2]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk9[2].fine_delay_incdec_pb[2]_i_4 \n (.I0(\\genblk9[2].fine_delay_incdec_pb[2]_i_5_n_0 ),\n .I1(\\genblk8[2].left_loss_pb_reg__0 [3]),\n .I2(\\genblk8[2].right_gain_pb_reg__0 [3]),\n .I3(\\genblk8[2].left_loss_pb_reg__0 [4]),\n .I4(\\genblk8[2].right_gain_pb_reg__0 [4]),\n .O(\\genblk9[2].fine_delay_incdec_pb[2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk9[2].fine_delay_incdec_pb[2]_i_5 \n (.I0(\\genblk8[2].right_gain_pb_reg_n_0_[12] ),\n .I1(\\genblk8[2].left_loss_pb_reg_n_0_[12] ),\n .I2(\\genblk8[2].left_loss_pb_reg_n_0_[13] ),\n .I3(\\genblk8[2].right_gain_pb_reg_n_0_[13] ),\n .I4(\\genblk8[2].left_loss_pb_reg__0 [2]),\n .I5(\\genblk8[2].right_gain_pb_reg__0 [2]),\n .O(\\genblk9[2].fine_delay_incdec_pb[2]_i_5_n_0 ));\n FDRE \\genblk9[2].fine_delay_incdec_pb_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk9[2].fine_delay_incdec_pb[2]_i_1_n_0 ),\n .Q(\\genblk9[2].fine_delay_incdec_pb_reg[2]_0 ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000AAA8AAAA)) \n \\genblk9[3].fine_delay_incdec_pb[3]_i_1 \n (.I0(\\genblk9[3].fine_delay_incdec_pb[3]_i_2_n_0 ),\n .I1(\\genblk9[3].fine_delay_incdec_pb[3]_i_3_n_0 ),\n .I2(\\stage_cnt_reg_n_0_[0] ),\n .I3(\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ),\n .I4(bit_cnt),\n .I5(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .O(\\genblk9[3].fine_delay_incdec_pb[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFB2FFFFFFB20000)) \n \\genblk9[3].fine_delay_incdec_pb[3]_i_2 \n (.I0(\\genblk8[3].right_gain_pb_reg__0 [5]),\n .I1(\\genblk8[3].left_loss_pb_reg__0 [5]),\n .I2(\\genblk9[3].fine_delay_incdec_pb[3]_i_4_n_0 ),\n .I3(\\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ),\n .I4(\\stage_cnt_reg[1]_0 ),\n .I5(\\genblk9[3].fine_delay_incdec_pb_reg[3]_0 ),\n .O(\\genblk9[3].fine_delay_incdec_pb[3]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair38\" *) \n LUT5 #(\n .INIT(32'hFFFFFFBF)) \n \\genblk9[3].fine_delay_incdec_pb[3]_i_3 \n (.I0(\\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ),\n .I1(\\ref_bit_reg_n_0_[1] ),\n .I2(\\ref_bit_reg_n_0_[0] ),\n .I3(ref_bit[3]),\n .I4(\\ref_bit_reg_n_0_[2] ),\n .O(\\genblk9[3].fine_delay_incdec_pb[3]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk9[3].fine_delay_incdec_pb[3]_i_4 \n (.I0(\\genblk9[3].fine_delay_incdec_pb[3]_i_5_n_0 ),\n .I1(\\genblk8[3].left_loss_pb_reg__0 [3]),\n .I2(\\genblk8[3].right_gain_pb_reg__0 [3]),\n .I3(\\genblk8[3].left_loss_pb_reg__0 [4]),\n .I4(\\genblk8[3].right_gain_pb_reg__0 [4]),\n .O(\\genblk9[3].fine_delay_incdec_pb[3]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk9[3].fine_delay_incdec_pb[3]_i_5 \n (.I0(\\genblk8[3].right_gain_pb_reg_n_0_[18] ),\n .I1(\\genblk8[3].left_loss_pb_reg_n_0_[18] ),\n .I2(\\genblk8[3].left_loss_pb_reg_n_0_[19] ),\n .I3(\\genblk8[3].right_gain_pb_reg_n_0_[19] ),\n .I4(\\genblk8[3].left_loss_pb_reg__0 [2]),\n .I5(\\genblk8[3].right_gain_pb_reg__0 [2]),\n .O(\\genblk9[3].fine_delay_incdec_pb[3]_i_5_n_0 ));\n FDRE \\genblk9[3].fine_delay_incdec_pb_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk9[3].fine_delay_incdec_pb[3]_i_1_n_0 ),\n .Q(\\genblk9[3].fine_delay_incdec_pb_reg[3]_0 ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000AAA8AAAA)) \n \\genblk9[4].fine_delay_incdec_pb[4]_i_1 \n (.I0(\\genblk9[4].fine_delay_incdec_pb[4]_i_2_n_0 ),\n .I1(\\genblk9[4].fine_delay_incdec_pb[4]_i_3_n_0 ),\n .I2(\\stage_cnt_reg_n_0_[0] ),\n .I3(\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ),\n .I4(bit_cnt),\n .I5(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .O(\\genblk9[4].fine_delay_incdec_pb[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFB2FFFFFFB20000)) \n \\genblk9[4].fine_delay_incdec_pb[4]_i_2 \n (.I0(\\genblk8[4].right_gain_pb_reg__0 [5]),\n .I1(\\genblk8[4].left_loss_pb_reg__0 [5]),\n .I2(\\genblk9[4].fine_delay_incdec_pb[4]_i_4_n_0 ),\n .I3(\\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ),\n .I4(\\stage_cnt_reg[1]_0 ),\n .I5(\\fine_delay_mod_reg[20] ),\n .O(\\genblk9[4].fine_delay_incdec_pb[4]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair36\" *) \n LUT5 #(\n .INIT(32'hFFFFFFEF)) \n \\genblk9[4].fine_delay_incdec_pb[4]_i_3 \n (.I0(\\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ),\n .I1(\\ref_bit_reg_n_0_[1] ),\n .I2(\\ref_bit_reg_n_0_[2] ),\n .I3(ref_bit[3]),\n .I4(\\ref_bit_reg_n_0_[0] ),\n .O(\\genblk9[4].fine_delay_incdec_pb[4]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk9[4].fine_delay_incdec_pb[4]_i_4 \n (.I0(\\genblk9[4].fine_delay_incdec_pb[4]_i_5_n_0 ),\n .I1(\\genblk8[4].left_loss_pb_reg__0 [3]),\n .I2(\\genblk8[4].right_gain_pb_reg__0 [3]),\n .I3(\\genblk8[4].left_loss_pb_reg__0 [4]),\n .I4(\\genblk8[4].right_gain_pb_reg__0 [4]),\n .O(\\genblk9[4].fine_delay_incdec_pb[4]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk9[4].fine_delay_incdec_pb[4]_i_5 \n (.I0(\\genblk8[4].right_gain_pb_reg_n_0_[24] ),\n .I1(\\genblk8[4].left_loss_pb_reg_n_0_[24] ),\n .I2(\\genblk8[4].left_loss_pb_reg_n_0_[25] ),\n .I3(\\genblk8[4].right_gain_pb_reg_n_0_[25] ),\n .I4(\\genblk8[4].left_loss_pb_reg__0 [2]),\n .I5(\\genblk8[4].right_gain_pb_reg__0 [2]),\n .O(\\genblk9[4].fine_delay_incdec_pb[4]_i_5_n_0 ));\n FDRE \\genblk9[4].fine_delay_incdec_pb_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk9[4].fine_delay_incdec_pb[4]_i_1_n_0 ),\n .Q(\\fine_delay_mod_reg[20] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000AAA8AAAA)) \n \\genblk9[5].fine_delay_incdec_pb[5]_i_1 \n (.I0(\\genblk9[5].fine_delay_incdec_pb[5]_i_2_n_0 ),\n .I1(\\genblk9[5].fine_delay_incdec_pb[5]_i_3_n_0 ),\n .I2(\\stage_cnt_reg_n_0_[0] ),\n .I3(\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ),\n .I4(bit_cnt),\n .I5(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .O(\\genblk9[5].fine_delay_incdec_pb[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFB2FFFFFFB20000)) \n \\genblk9[5].fine_delay_incdec_pb[5]_i_2 \n (.I0(\\genblk8[5].right_gain_pb_reg__0 [5]),\n .I1(\\genblk8[5].left_loss_pb_reg__0 [5]),\n .I2(\\genblk9[5].fine_delay_incdec_pb[5]_i_4_n_0 ),\n .I3(\\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ),\n .I4(\\stage_cnt_reg[1]_0 ),\n .I5(\\genblk9[5].fine_delay_incdec_pb_reg[5]_0 ),\n .O(\\genblk9[5].fine_delay_incdec_pb[5]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair39\" *) \n LUT5 #(\n .INIT(32'hFFFFFFBF)) \n \\genblk9[5].fine_delay_incdec_pb[5]_i_3 \n (.I0(\\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ),\n .I1(\\ref_bit_reg_n_0_[2] ),\n .I2(\\ref_bit_reg_n_0_[0] ),\n .I3(ref_bit[3]),\n .I4(\\ref_bit_reg_n_0_[1] ),\n .O(\\genblk9[5].fine_delay_incdec_pb[5]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk9[5].fine_delay_incdec_pb[5]_i_4 \n (.I0(\\genblk9[5].fine_delay_incdec_pb[5]_i_5_n_0 ),\n .I1(\\genblk8[5].left_loss_pb_reg__0 [3]),\n .I2(\\genblk8[5].right_gain_pb_reg__0 [3]),\n .I3(\\genblk8[5].left_loss_pb_reg__0 [4]),\n .I4(\\genblk8[5].right_gain_pb_reg__0 [4]),\n .O(\\genblk9[5].fine_delay_incdec_pb[5]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk9[5].fine_delay_incdec_pb[5]_i_5 \n (.I0(\\genblk8[5].right_gain_pb_reg_n_0_[30] ),\n .I1(\\genblk8[5].left_loss_pb_reg_n_0_[30] ),\n .I2(\\genblk8[5].left_loss_pb_reg_n_0_[31] ),\n .I3(\\genblk8[5].right_gain_pb_reg_n_0_[31] ),\n .I4(\\genblk8[5].left_loss_pb_reg__0 [2]),\n .I5(\\genblk8[5].right_gain_pb_reg__0 [2]),\n .O(\\genblk9[5].fine_delay_incdec_pb[5]_i_5_n_0 ));\n FDRE \\genblk9[5].fine_delay_incdec_pb_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk9[5].fine_delay_incdec_pb[5]_i_1_n_0 ),\n .Q(\\genblk9[5].fine_delay_incdec_pb_reg[5]_0 ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000AAAAAAA2)) \n \\genblk9[6].fine_delay_incdec_pb[6]_i_1 \n (.I0(\\genblk9[6].fine_delay_incdec_pb[6]_i_2_n_0 ),\n .I1(bit_cnt),\n .I2(\\genblk9[6].fine_delay_incdec_pb[6]_i_3_n_0 ),\n .I3(\\stage_cnt_reg_n_0_[0] ),\n .I4(\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ),\n .I5(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .O(\\genblk9[6].fine_delay_incdec_pb[6]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFB2FFFFFFB20000)) \n \\genblk9[6].fine_delay_incdec_pb[6]_i_2 \n (.I0(\\genblk8[6].right_gain_pb_reg__0 [5]),\n .I1(\\genblk8[6].left_loss_pb_reg__0 [5]),\n .I2(\\genblk9[6].fine_delay_incdec_pb[6]_i_4_n_0 ),\n .I3(\\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ),\n .I4(\\stage_cnt_reg[1]_0 ),\n .I5(\\genblk9[6].fine_delay_incdec_pb_reg[6]_0 ),\n .O(\\genblk9[6].fine_delay_incdec_pb[6]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair36\" *) \n LUT5 #(\n .INIT(32'hFFFFFFBF)) \n \\genblk9[6].fine_delay_incdec_pb[6]_i_3 \n (.I0(\\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ),\n .I1(\\ref_bit_reg_n_0_[2] ),\n .I2(\\ref_bit_reg_n_0_[1] ),\n .I3(ref_bit[3]),\n .I4(\\ref_bit_reg_n_0_[0] ),\n .O(\\genblk9[6].fine_delay_incdec_pb[6]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk9[6].fine_delay_incdec_pb[6]_i_4 \n (.I0(\\genblk9[6].fine_delay_incdec_pb[6]_i_5_n_0 ),\n .I1(\\genblk8[6].left_loss_pb_reg__0 [3]),\n .I2(\\genblk8[6].right_gain_pb_reg__0 [3]),\n .I3(\\genblk8[6].left_loss_pb_reg__0 [4]),\n .I4(\\genblk8[6].right_gain_pb_reg__0 [4]),\n .O(\\genblk9[6].fine_delay_incdec_pb[6]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk9[6].fine_delay_incdec_pb[6]_i_5 \n (.I0(\\genblk8[6].right_gain_pb_reg_n_0_[36] ),\n .I1(\\genblk8[6].left_loss_pb_reg_n_0_[36] ),\n .I2(\\genblk8[6].left_loss_pb_reg_n_0_[37] ),\n .I3(\\genblk8[6].right_gain_pb_reg_n_0_[37] ),\n .I4(\\genblk8[6].left_loss_pb_reg__0 [2]),\n .I5(\\genblk8[6].right_gain_pb_reg__0 [2]),\n .O(\\genblk9[6].fine_delay_incdec_pb[6]_i_5_n_0 ));\n FDRE \\genblk9[6].fine_delay_incdec_pb_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk9[6].fine_delay_incdec_pb[6]_i_1_n_0 ),\n .Q(\\genblk9[6].fine_delay_incdec_pb_reg[6]_0 ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000AAA8AAAA)) \n \\genblk9[7].fine_delay_incdec_pb[7]_i_1 \n (.I0(\\genblk9[7].fine_delay_incdec_pb[7]_i_2_n_0 ),\n .I1(\\genblk9[7].fine_delay_incdec_pb[7]_i_3_n_0 ),\n .I2(\\stage_cnt_reg_n_0_[0] ),\n .I3(\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ),\n .I4(bit_cnt),\n .I5(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ),\n .O(\\genblk9[7].fine_delay_incdec_pb[7]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFB2FFFFFFB20000)) \n \\genblk9[7].fine_delay_incdec_pb[7]_i_2 \n (.I0(\\genblk8[7].right_gain_pb_reg__0 [5]),\n .I1(\\genblk8[7].left_loss_pb_reg__0 [5]),\n .I2(\\genblk9[7].fine_delay_incdec_pb[7]_i_4_n_0 ),\n .I3(\\genblk9[0].fine_delay_incdec_pb[0]_i_6_n_0 ),\n .I4(\\stage_cnt_reg[1]_0 ),\n .I5(\\genblk9[7].fine_delay_incdec_pb_reg[7]_0 ),\n .O(\\genblk9[7].fine_delay_incdec_pb[7]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair39\" *) \n LUT5 #(\n .INIT(32'hFFBFFFFF)) \n \\genblk9[7].fine_delay_incdec_pb[7]_i_3 \n (.I0(\\genblk9[0].fine_delay_incdec_pb[0]_i_10_n_0 ),\n .I1(\\ref_bit_reg_n_0_[1] ),\n .I2(\\ref_bit_reg_n_0_[0] ),\n .I3(ref_bit[3]),\n .I4(\\ref_bit_reg_n_0_[2] ),\n .O(\\genblk9[7].fine_delay_incdec_pb[7]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\genblk9[7].fine_delay_incdec_pb[7]_i_4 \n (.I0(\\genblk9[7].fine_delay_incdec_pb[7]_i_5_n_0 ),\n .I1(\\genblk8[7].left_loss_pb_reg__0 [3]),\n .I2(\\genblk8[7].right_gain_pb_reg__0 [3]),\n .I3(\\genblk8[7].left_loss_pb_reg__0 [4]),\n .I4(\\genblk8[7].right_gain_pb_reg__0 [4]),\n .O(\\genblk9[7].fine_delay_incdec_pb[7]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h2F02FFFF00002F02)) \n \\genblk9[7].fine_delay_incdec_pb[7]_i_5 \n (.I0(\\genblk8[7].right_gain_pb_reg_n_0_[42] ),\n .I1(\\genblk8[7].left_loss_pb_reg_n_0_[42] ),\n .I2(\\genblk8[7].left_loss_pb_reg_n_0_[43] ),\n .I3(\\genblk8[7].right_gain_pb_reg_n_0_[43] ),\n .I4(\\genblk8[7].left_loss_pb_reg__0 [2]),\n .I5(\\genblk8[7].right_gain_pb_reg__0 [2]),\n .O(\\genblk9[7].fine_delay_incdec_pb[7]_i_5_n_0 ));\n FDRE \\genblk9[7].fine_delay_incdec_pb_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\genblk9[7].fine_delay_incdec_pb[7]_i_1_n_0 ),\n .Q(\\genblk9[7].fine_delay_incdec_pb_reg[7]_0 ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair22\" *) \n LUT2 #(\n .INIT(4'h7)) \n \\init_state_r[0]_i_32 \n (.I0(complex_oclkdelay_calib_done_r1_reg),\n .I1(rdlvl_stg1_done_int_reg),\n .O(\\init_state_r_reg[0]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair22\" *) \n LUT5 #(\n .INIT(32'h000074FF)) \n \\init_state_r[0]_i_35 \n (.I0(complex_oclkdelay_calib_done_r1_reg),\n .I1(rdlvl_stg1_done_int_reg),\n .I2(wrcal_done_reg),\n .I3(dqs_found_done_r_reg),\n .I4(\\num_refresh_reg[1] ),\n .O(\\init_state_r_reg[0] ));\n LUT6 #(\n .INIT(64'h3F332F233F332020)) \n \\init_state_r[1]_i_32 \n (.I0(prbs_last_byte_done),\n .I1(complex_oclkdelay_calib_done_r1_reg),\n .I2(rdlvl_stg1_done_int_reg),\n .I3(rdlvl_stg1_start_int),\n .I4(rdlvl_last_byte_done),\n .I5(\\one_rank.stg1_wr_done_reg ),\n .O(\\init_state_r_reg[1]_0 ));\n LUT6 #(\n .INIT(64'hF0FF808080808080)) \n \\init_state_r[1]_i_45 \n (.I0(complex_oclkdelay_calib_done_r1_reg),\n .I1(oclkdelay_center_calib_done_r_reg),\n .I2(rdlvl_stg1_done_int_reg),\n .I3(wrcal_done_reg),\n .I4(dqs_found_done_r_reg),\n .I5(wrlvl_final_mux),\n .O(\\init_state_r_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair76\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\largest_left_edge[0]_i_1 \n (.I0(Q[2]),\n .I1(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .O(\\largest_left_edge[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair76\" *) \n LUT3 #(\n .INIT(8'h28)) \n \\largest_left_edge[1]_i_1 \n (.I0(Q[2]),\n .I1(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .O(\\largest_left_edge[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair31\" *) \n LUT4 #(\n .INIT(16'h2888)) \n \\largest_left_edge[2]_i_1 \n (.I0(Q[2]),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .O(\\largest_left_edge[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair31\" *) \n LUT5 #(\n .INIT(32'h82222222)) \n \\largest_left_edge[3]_i_1 \n (.I0(Q[2]),\n .I1(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\largest_left_edge[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8888888882222222)) \n \\largest_left_edge[4]_i_1 \n (.I0(Q[2]),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\largest_left_edge[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00002F0000000000)) \n \\largest_left_edge[5]_i_1 \n (.I0(ref_bit_per_bit0),\n .I1(\\largest_left_edge_reg[0]_0 ),\n .I2(Q[2]),\n .I3(Q[3]),\n .I4(Q[4]),\n .I5(\\largest_left_edge[5]_i_4_n_0 ),\n .O(\\largest_left_edge[5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair73\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\largest_left_edge[5]_i_2 \n (.I0(Q[2]),\n .I1(\\largest_left_edge[5]_i_5_n_0 ),\n .O(\\largest_left_edge[5]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFEFFFF)) \n \\largest_left_edge[5]_i_3 \n (.I0(D[0]),\n .I1(D[1]),\n .I2(D[2]),\n .I3(D[3]),\n .I4(\\largest_left_edge[5]_i_6_n_0 ),\n .O(ref_bit_per_bit0));\n (* SOFT_HLUTNM = \"soft_lutpair26\" *) \n LUT3 #(\n .INIT(8'h81)) \n \\largest_left_edge[5]_i_4 \n (.I0(Q[0]),\n .I1(Q[2]),\n .I2(Q[1]),\n .O(\\largest_left_edge[5]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h00001555FFFFEAAA)) \n \\largest_left_edge[5]_i_5 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\largest_left_edge[5]_i_5_n_0 ));\n LUT4 #(\n .INIT(16'h0001)) \n \\largest_left_edge[5]_i_6 \n (.I0(D[6]),\n .I1(D[7]),\n .I2(D[5]),\n .I3(D[4]),\n .O(\\largest_left_edge[5]_i_6_n_0 ));\n FDRE \\largest_left_edge_reg[0] \n (.C(CLK),\n .CE(\\largest_left_edge[5]_i_1_n_0 ),\n .D(\\largest_left_edge[0]_i_1_n_0 ),\n .Q(\\largest_left_edge_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE \\largest_left_edge_reg[1] \n (.C(CLK),\n .CE(\\largest_left_edge[5]_i_1_n_0 ),\n .D(\\largest_left_edge[1]_i_1_n_0 ),\n .Q(\\largest_left_edge_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE \\largest_left_edge_reg[2] \n (.C(CLK),\n .CE(\\largest_left_edge[5]_i_1_n_0 ),\n .D(\\largest_left_edge[2]_i_1_n_0 ),\n .Q(\\largest_left_edge_reg_n_0_[2] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE \\largest_left_edge_reg[3] \n (.C(CLK),\n .CE(\\largest_left_edge[5]_i_1_n_0 ),\n .D(\\largest_left_edge[3]_i_1_n_0 ),\n .Q(\\largest_left_edge_reg_n_0_[3] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE \\largest_left_edge_reg[4] \n (.C(CLK),\n .CE(\\largest_left_edge[5]_i_1_n_0 ),\n .D(\\largest_left_edge[4]_i_1_n_0 ),\n .Q(\\largest_left_edge_reg_n_0_[4] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE \\largest_left_edge_reg[5] \n (.C(CLK),\n .CE(\\largest_left_edge[5]_i_1_n_0 ),\n .D(\\largest_left_edge[5]_i_2_n_0 ),\n .Q(\\largest_left_edge_reg_n_0_[5] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n LUT3 #(\n .INIT(8'hB8)) \n \\left_edge_ref[0]_i_1 \n (.I0(\\left_edge_ref[2]_i_2_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_7 ),\n .I2(\\left_edge_ref[0]_i_2_n_0 ),\n .O(\\left_edge_ref[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\left_edge_ref[0]_i_2 \n (.I0(\\left_edge_ref_reg[4]_i_10_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_6 ),\n .I2(\\left_edge_ref[4]_i_9_n_0 ),\n .I3(\\left_edge_ref_reg[5]_i_3_n_5 ),\n .I4(\\left_edge_ref[0]_i_3_n_0 ),\n .O(\\left_edge_ref[0]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair17\" *) \n LUT5 #(\n .INIT(32'h30BB3088)) \n \\left_edge_ref[0]_i_3 \n (.I0(\\genblk8[2].left_edge_pb_reg_n_0_[16] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].left_edge_pb_reg_n_0_[32] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].left_edge_pb_reg_n_0_[0] ),\n .O(\\left_edge_ref[0]_i_3_n_0 ));\n LUT3 #(\n .INIT(8'hB8)) \n \\left_edge_ref[1]_i_1 \n (.I0(\\left_edge_ref[3]_i_2_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_7 ),\n .I2(\\left_edge_ref[1]_i_2_n_0 ),\n .O(\\left_edge_ref[1]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\left_edge_ref[1]_i_2 \n (.I0(\\left_edge_ref_reg[5]_i_16_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_6 ),\n .I2(\\left_edge_ref[5]_i_15_n_0 ),\n .I3(\\left_edge_ref_reg[5]_i_3_n_5 ),\n .I4(\\left_edge_ref[1]_i_3_n_0 ),\n .O(\\left_edge_ref[1]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair27\" *) \n LUT5 #(\n .INIT(32'h30BB3088)) \n \\left_edge_ref[1]_i_3 \n (.I0(\\genblk8[2].left_edge_pb_reg_n_0_[17] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].left_edge_pb_reg_n_0_[33] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].left_edge_pb_reg_n_0_[1] ),\n .O(\\left_edge_ref[1]_i_3_n_0 ));\n LUT3 #(\n .INIT(8'hB8)) \n \\left_edge_ref[2]_i_1 \n (.I0(\\left_edge_ref[4]_i_4_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_7 ),\n .I2(\\left_edge_ref[2]_i_2_n_0 ),\n .O(\\left_edge_ref[2]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\left_edge_ref[2]_i_2 \n (.I0(\\left_edge_ref_reg[4]_i_3_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_6 ),\n .I2(\\left_edge_ref[4]_i_5_n_0 ),\n .I3(\\left_edge_ref_reg[5]_i_3_n_5 ),\n .I4(\\left_edge_ref[2]_i_3_n_0 ),\n .O(\\left_edge_ref[2]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\left_edge_ref[2]_i_3 \n (.I0(\\genblk8[3].left_edge_pb_reg_n_0_[18] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].left_edge_pb_reg_n_0_[34] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].left_edge_pb_reg_n_0_[2] ),\n .O(\\left_edge_ref[2]_i_3_n_0 ));\n LUT3 #(\n .INIT(8'hB8)) \n \\left_edge_ref[3]_i_1 \n (.I0(\\left_edge_ref[5]_i_5_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_7 ),\n .I2(\\left_edge_ref[3]_i_2_n_0 ),\n .O(\\left_edge_ref[3]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\left_edge_ref[3]_i_2 \n (.I0(\\left_edge_ref_reg[5]_i_4_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_6 ),\n .I2(\\left_edge_ref[5]_i_7_n_0 ),\n .I3(\\left_edge_ref_reg[5]_i_3_n_5 ),\n .I4(\\left_edge_ref[3]_i_3_n_0 ),\n .O(\\left_edge_ref[3]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\left_edge_ref[3]_i_3 \n (.I0(\\genblk8[3].left_edge_pb_reg_n_0_[19] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].left_edge_pb_reg_n_0_[35] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].left_edge_pb_reg_n_0_[3] ),\n .O(\\left_edge_ref[3]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\left_edge_ref[4]_i_1 \n (.I0(\\left_edge_ref[4]_i_2_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_6 ),\n .I2(\\left_edge_ref_reg[4]_i_3_n_0 ),\n .I3(\\left_edge_ref_reg[5]_i_3_n_7 ),\n .I4(\\left_edge_ref[4]_i_4_n_0 ),\n .O(\\left_edge_ref[4]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\left_edge_ref[4]_i_11 \n (.I0(\\genblk8[3].left_edge_pb_reg_n_0_[20] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].left_edge_pb_reg_n_0_[36] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].left_edge_pb_reg_n_0_[4] ),\n .O(\\left_edge_ref[4]_i_11_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\left_edge_ref[4]_i_12 \n (.I0(\\genblk8[4].left_edge_pb_reg_n_0_[28] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].left_edge_pb_reg_n_0_[44] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[2].left_edge_pb_reg_n_0_[12] ),\n .O(\\left_edge_ref[4]_i_12_n_0 ));\n LUT6 #(\n .INIT(64'h00E2FFFF00E20000)) \n \\left_edge_ref[4]_i_2 \n (.I0(\\genblk8[3].left_edge_pb_reg_n_0_[18] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].left_edge_pb_reg_n_0_[34] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\left_edge_ref_reg[5]_i_3_n_5 ),\n .I5(\\left_edge_ref[4]_i_5_n_0 ),\n .O(\\left_edge_ref[4]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\left_edge_ref[4]_i_4 \n (.I0(\\left_edge_ref[4]_i_8_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_5 ),\n .I2(\\left_edge_ref[4]_i_9_n_0 ),\n .I3(\\left_edge_ref_reg[5]_i_3_n_6 ),\n .I4(\\left_edge_ref_reg[4]_i_10_n_0 ),\n .O(\\left_edge_ref[4]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\left_edge_ref[4]_i_5 \n (.I0(\\genblk8[4].left_edge_pb_reg_n_0_[26] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].left_edge_pb_reg_n_0_[42] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].left_edge_pb_reg_n_0_[10] ),\n .O(\\left_edge_ref[4]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\left_edge_ref[4]_i_6 \n (.I0(\\genblk8[3].left_edge_pb_reg_n_0_[22] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].left_edge_pb_reg_n_0_[38] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].left_edge_pb_reg_n_0_[6] ),\n .O(\\left_edge_ref[4]_i_6_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\left_edge_ref[4]_i_7 \n (.I0(\\genblk8[5].left_edge_pb_reg_n_0_[30] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].left_edge_pb_reg_n_0_[46] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[2].left_edge_pb_reg_n_0_[14] ),\n .O(\\left_edge_ref[4]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair17\" *) \n LUT4 #(\n .INIT(16'h00E2)) \n \\left_edge_ref[4]_i_8 \n (.I0(\\genblk8[2].left_edge_pb_reg_n_0_[16] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].left_edge_pb_reg_n_0_[32] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .O(\\left_edge_ref[4]_i_8_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\left_edge_ref[4]_i_9 \n (.I0(\\genblk8[4].left_edge_pb_reg_n_0_[24] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].left_edge_pb_reg_n_0_[40] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].left_edge_pb_reg_n_0_[8] ),\n .O(\\left_edge_ref[4]_i_9_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\left_edge_ref[5]_i_1 \n (.I0(\\left_edge_ref[5]_i_2_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_6 ),\n .I2(\\left_edge_ref_reg[5]_i_4_n_0 ),\n .I3(\\left_edge_ref_reg[5]_i_3_n_7 ),\n .I4(\\left_edge_ref[5]_i_5_n_0 ),\n .O(\\left_edge_ref[5]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\left_edge_ref[5]_i_10 \n (.I0(\\ref_bit_reg_n_0_[1] ),\n .O(\\left_edge_ref[5]_i_10_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\left_edge_ref[5]_i_11 \n (.I0(\\ref_bit_reg_n_0_[0] ),\n .O(\\left_edge_ref[5]_i_11_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\left_edge_ref[5]_i_12 \n (.I0(\\genblk8[3].left_edge_pb_reg_n_0_[23] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].left_edge_pb_reg_n_0_[39] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].left_edge_pb_reg_n_0_[7] ),\n .O(\\left_edge_ref[5]_i_12_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\left_edge_ref[5]_i_13 \n (.I0(\\genblk8[5].left_edge_pb_reg_n_0_[31] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].left_edge_pb_reg_n_0_[47] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[2].left_edge_pb_reg_n_0_[15] ),\n .O(\\left_edge_ref[5]_i_13_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair27\" *) \n LUT4 #(\n .INIT(16'h00E2)) \n \\left_edge_ref[5]_i_14 \n (.I0(\\genblk8[2].left_edge_pb_reg_n_0_[17] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].left_edge_pb_reg_n_0_[33] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .O(\\left_edge_ref[5]_i_14_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\left_edge_ref[5]_i_15 \n (.I0(\\genblk8[4].left_edge_pb_reg_n_0_[25] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].left_edge_pb_reg_n_0_[41] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].left_edge_pb_reg_n_0_[9] ),\n .O(\\left_edge_ref[5]_i_15_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\left_edge_ref[5]_i_17 \n (.I0(\\ref_bit_reg_n_0_[2] ),\n .I1(ref_bit[4]),\n .O(\\left_edge_ref[5]_i_17_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\left_edge_ref[5]_i_18 \n (.I0(\\genblk8[3].left_edge_pb_reg_n_0_[21] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].left_edge_pb_reg_n_0_[37] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].left_edge_pb_reg_n_0_[5] ),\n .O(\\left_edge_ref[5]_i_18_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\left_edge_ref[5]_i_19 \n (.I0(\\genblk8[4].left_edge_pb_reg_n_0_[29] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].left_edge_pb_reg_n_0_[45] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[2].left_edge_pb_reg_n_0_[13] ),\n .O(\\left_edge_ref[5]_i_19_n_0 ));\n LUT6 #(\n .INIT(64'h00E2FFFF00E20000)) \n \\left_edge_ref[5]_i_2 \n (.I0(\\genblk8[3].left_edge_pb_reg_n_0_[19] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].left_edge_pb_reg_n_0_[35] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\left_edge_ref_reg[5]_i_3_n_5 ),\n .I5(\\left_edge_ref[5]_i_7_n_0 ),\n .O(\\left_edge_ref[5]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\left_edge_ref[5]_i_5 \n (.I0(\\left_edge_ref[5]_i_14_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_5 ),\n .I2(\\left_edge_ref[5]_i_15_n_0 ),\n .I3(\\left_edge_ref_reg[5]_i_3_n_6 ),\n .I4(\\left_edge_ref_reg[5]_i_16_n_0 ),\n .O(\\left_edge_ref[5]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\left_edge_ref[5]_i_7 \n (.I0(\\genblk8[4].left_edge_pb_reg_n_0_[27] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].left_edge_pb_reg_n_0_[43] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].left_edge_pb_reg_n_0_[11] ),\n .O(\\left_edge_ref[5]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\left_edge_ref[5]_i_8 \n (.I0(\\ref_bit_reg_n_0_[1] ),\n .I1(ref_bit[3]),\n .O(\\left_edge_ref[5]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\left_edge_ref[5]_i_9 \n (.I0(\\ref_bit_reg_n_0_[0] ),\n .I1(\\ref_bit_reg_n_0_[2] ),\n .O(\\left_edge_ref[5]_i_9_n_0 ));\n FDRE \\left_edge_ref_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\left_edge_ref[0]_i_1_n_0 ),\n .Q(left_edge_ref[0]),\n .R(1'b0));\n FDRE \\left_edge_ref_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\left_edge_ref[1]_i_1_n_0 ),\n .Q(left_edge_ref[1]),\n .R(1'b0));\n FDRE \\left_edge_ref_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\left_edge_ref[2]_i_1_n_0 ),\n .Q(left_edge_ref[2]),\n .R(1'b0));\n FDRE \\left_edge_ref_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\left_edge_ref[3]_i_1_n_0 ),\n .Q(left_edge_ref[3]),\n .R(1'b0));\n FDRE \\left_edge_ref_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\left_edge_ref[4]_i_1_n_0 ),\n .Q(left_edge_ref[4]),\n .R(1'b0));\n MUXF7 \\left_edge_ref_reg[4]_i_10 \n (.I0(\\left_edge_ref[4]_i_11_n_0 ),\n .I1(\\left_edge_ref[4]_i_12_n_0 ),\n .O(\\left_edge_ref_reg[4]_i_10_n_0 ),\n .S(\\left_edge_ref_reg[5]_i_3_n_5 ));\n MUXF7 \\left_edge_ref_reg[4]_i_3 \n (.I0(\\left_edge_ref[4]_i_6_n_0 ),\n .I1(\\left_edge_ref[4]_i_7_n_0 ),\n .O(\\left_edge_ref_reg[4]_i_3_n_0 ),\n .S(\\left_edge_ref_reg[5]_i_3_n_5 ));\n FDRE \\left_edge_ref_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\left_edge_ref[5]_i_1_n_0 ),\n .Q(left_edge_ref[5]),\n .R(1'b0));\n MUXF7 \\left_edge_ref_reg[5]_i_16 \n (.I0(\\left_edge_ref[5]_i_18_n_0 ),\n .I1(\\left_edge_ref[5]_i_19_n_0 ),\n .O(\\left_edge_ref_reg[5]_i_16_n_0 ),\n .S(\\left_edge_ref_reg[5]_i_3_n_5 ));\n CARRY4 \\left_edge_ref_reg[5]_i_3 \n (.CI(1'b0),\n .CO({\\left_edge_ref_reg[5]_i_3_n_0 ,\\left_edge_ref_reg[5]_i_3_n_1 ,\\left_edge_ref_reg[5]_i_3_n_2 ,\\left_edge_ref_reg[5]_i_3_n_3 }),\n .CYINIT(1'b0),\n .DI({\\ref_bit_reg_n_0_[1] ,\\ref_bit_reg_n_0_[0] ,1'b0,1'b1}),\n .O({\\left_edge_ref_reg[5]_i_3_n_4 ,\\left_edge_ref_reg[5]_i_3_n_5 ,\\left_edge_ref_reg[5]_i_3_n_6 ,\\left_edge_ref_reg[5]_i_3_n_7 }),\n .S({\\left_edge_ref[5]_i_8_n_0 ,\\left_edge_ref[5]_i_9_n_0 ,\\left_edge_ref[5]_i_10_n_0 ,\\left_edge_ref[5]_i_11_n_0 }));\n MUXF7 \\left_edge_ref_reg[5]_i_4 \n (.I0(\\left_edge_ref[5]_i_12_n_0 ),\n .I1(\\left_edge_ref[5]_i_13_n_0 ),\n .O(\\left_edge_ref_reg[5]_i_4_n_0 ),\n .S(\\left_edge_ref_reg[5]_i_3_n_5 ));\n CARRY4 \\left_edge_ref_reg[5]_i_6 \n (.CI(\\left_edge_ref_reg[5]_i_3_n_0 ),\n .CO(\\NLW_left_edge_ref_reg[5]_i_6_CO_UNCONNECTED [3:0]),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\NLW_left_edge_ref_reg[5]_i_6_O_UNCONNECTED [3:1],\\left_edge_ref_reg[5]_i_6_n_7 }),\n .S({1'b0,1'b0,1'b0,\\left_edge_ref[5]_i_17_n_0 }));\n LUT5 #(\n .INIT(32'hEEE2FFFF)) \n \\match_flag_and[0]_i_1 \n (.I0(compare_err_pb_and_reg_n_0),\n .I1(Q[1]),\n .I2(num_samples_done_r),\n .I3(\\match_flag_or_reg[0]_0 ),\n .I4(Q[4]),\n .O(\\match_flag_and[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hEEE2FFFF)) \n \\match_flag_and[1]_i_1 \n (.I0(\\match_flag_and_reg_n_0_[0] ),\n .I1(Q[1]),\n .I2(num_samples_done_r),\n .I3(\\match_flag_or_reg[0]_0 ),\n .I4(Q[4]),\n .O(\\match_flag_and[1]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hEEE2FFFF)) \n \\match_flag_and[2]_i_1 \n (.I0(\\match_flag_and_reg_n_0_[1] ),\n .I1(Q[1]),\n .I2(num_samples_done_r),\n .I3(\\match_flag_or_reg[0]_0 ),\n .I4(Q[4]),\n .O(\\match_flag_and[2]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hEEE2FFFF)) \n \\match_flag_and[3]_i_1 \n (.I0(\\match_flag_and_reg_n_0_[2] ),\n .I1(Q[1]),\n .I2(num_samples_done_r),\n .I3(\\match_flag_or_reg[0]_0 ),\n .I4(Q[4]),\n .O(\\match_flag_and[3]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hEEE2FFFF)) \n \\match_flag_and[4]_i_1 \n (.I0(\\match_flag_and_reg_n_0_[3] ),\n .I1(Q[1]),\n .I2(num_samples_done_r),\n .I3(\\match_flag_or_reg[0]_0 ),\n .I4(Q[4]),\n .O(\\match_flag_and[4]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hEEE2FFFF)) \n \\match_flag_and[5]_i_1 \n (.I0(\\match_flag_and_reg_n_0_[4] ),\n .I1(Q[1]),\n .I2(num_samples_done_r),\n .I3(\\match_flag_or_reg[0]_0 ),\n .I4(Q[4]),\n .O(\\match_flag_and[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hEEE2FFFF)) \n \\match_flag_and[6]_i_1 \n (.I0(\\match_flag_and_reg_n_0_[5] ),\n .I1(Q[1]),\n .I2(num_samples_done_r),\n .I3(\\match_flag_or_reg[0]_0 ),\n .I4(Q[4]),\n .O(\\match_flag_and[6]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00A2FFFF00A20000)) \n \\match_flag_and[7]_i_1 \n (.I0(\\match_flag_and[7]_i_3_n_0 ),\n .I1(Q[4]),\n .I2(num_samples_done_r),\n .I3(Q[2]),\n .I4(Q[0]),\n .I5(no_err_win_detected_reg_0),\n .O(match_flag_and));\n LUT5 #(\n .INIT(32'hEEE2FFFF)) \n \\match_flag_and[7]_i_2 \n (.I0(\\match_flag_and_reg_n_0_[6] ),\n .I1(Q[1]),\n .I2(num_samples_done_r),\n .I3(\\match_flag_or_reg[0]_0 ),\n .I4(Q[4]),\n .O(\\match_flag_and[7]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair28\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\match_flag_and[7]_i_3 \n (.I0(Q[1]),\n .I1(Q[3]),\n .O(\\match_flag_and[7]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0000444000000000)) \n \\match_flag_and[7]_i_4 \n (.I0(Q[3]),\n .I1(Q[1]),\n .I2(num_samples_done_r),\n .I3(\\match_flag_or_reg[0]_0 ),\n .I4(Q[2]),\n .I5(Q[4]),\n .O(no_err_win_detected_reg_0));\n FDSE \\match_flag_and_reg[0] \n (.C(CLK),\n .CE(match_flag_and),\n .D(\\match_flag_and[0]_i_1_n_0 ),\n .Q(\\match_flag_and_reg_n_0_[0] ),\n .S(rstdiv0_sync_r1_reg_rep__9));\n FDSE \\match_flag_and_reg[1] \n (.C(CLK),\n .CE(match_flag_and),\n .D(\\match_flag_and[1]_i_1_n_0 ),\n .Q(\\match_flag_and_reg_n_0_[1] ),\n .S(rstdiv0_sync_r1_reg_rep__9));\n FDSE \\match_flag_and_reg[2] \n (.C(CLK),\n .CE(match_flag_and),\n .D(\\match_flag_and[2]_i_1_n_0 ),\n .Q(\\match_flag_and_reg_n_0_[2] ),\n .S(rstdiv0_sync_r1_reg_rep__9));\n FDSE \\match_flag_and_reg[3] \n (.C(CLK),\n .CE(match_flag_and),\n .D(\\match_flag_and[3]_i_1_n_0 ),\n .Q(\\match_flag_and_reg_n_0_[3] ),\n .S(rstdiv0_sync_r1_reg_rep__9));\n FDSE \\match_flag_and_reg[4] \n (.C(CLK),\n .CE(match_flag_and),\n .D(\\match_flag_and[4]_i_1_n_0 ),\n .Q(\\match_flag_and_reg_n_0_[4] ),\n .S(rstdiv0_sync_r1_reg_rep__9));\n FDSE \\match_flag_and_reg[5] \n (.C(CLK),\n .CE(match_flag_and),\n .D(\\match_flag_and[5]_i_1_n_0 ),\n .Q(\\match_flag_and_reg_n_0_[5] ),\n .S(rstdiv0_sync_r1_reg_rep__9));\n FDSE \\match_flag_and_reg[6] \n (.C(CLK),\n .CE(match_flag_and),\n .D(\\match_flag_and[6]_i_1_n_0 ),\n .Q(\\match_flag_and_reg_n_0_[6] ),\n .S(rstdiv0_sync_r1_reg_rep__9));\n FDSE \\match_flag_and_reg[7] \n (.C(CLK),\n .CE(match_flag_and),\n .D(\\match_flag_and[7]_i_2_n_0 ),\n .Q(\\match_flag_and_reg_n_0_[7] ),\n .S(rstdiv0_sync_r1_reg_rep__9));\n LUT5 #(\n .INIT(32'hEEE2FFFF)) \n \\match_flag_or[0]_i_1 \n (.I0(sel0[0]),\n .I1(Q[1]),\n .I2(num_samples_done_r),\n .I3(\\match_flag_or_reg[0]_0 ),\n .I4(Q[4]),\n .O(\\match_flag_or[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hEEE2FFFF)) \n \\match_flag_or[1]_i_1 \n (.I0(sel0[1]),\n .I1(Q[1]),\n .I2(num_samples_done_r),\n .I3(\\match_flag_or_reg[0]_0 ),\n .I4(Q[4]),\n .O(\\match_flag_or[1]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hEEE2FFFF)) \n \\match_flag_or[2]_i_1 \n (.I0(sel0[2]),\n .I1(Q[1]),\n .I2(num_samples_done_r),\n .I3(\\match_flag_or_reg[0]_0 ),\n .I4(Q[4]),\n .O(\\match_flag_or[2]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hEEE2FFFF)) \n \\match_flag_or[3]_i_1 \n (.I0(sel0[3]),\n .I1(Q[1]),\n .I2(num_samples_done_r),\n .I3(\\match_flag_or_reg[0]_0 ),\n .I4(Q[4]),\n .O(\\match_flag_or[3]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hEEE2FFFF)) \n \\match_flag_or[4]_i_1 \n (.I0(sel0[4]),\n .I1(Q[1]),\n .I2(num_samples_done_r),\n .I3(\\match_flag_or_reg[0]_0 ),\n .I4(Q[4]),\n .O(\\match_flag_or[4]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hEEE2FFFF)) \n \\match_flag_or[5]_i_1 \n (.I0(sel0[5]),\n .I1(Q[1]),\n .I2(num_samples_done_r),\n .I3(\\match_flag_or_reg[0]_0 ),\n .I4(Q[4]),\n .O(\\match_flag_or[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hEEE2FFFF)) \n \\match_flag_or[6]_i_1 \n (.I0(sel0[6]),\n .I1(Q[1]),\n .I2(num_samples_done_r),\n .I3(\\match_flag_or_reg[0]_0 ),\n .I4(Q[4]),\n .O(\\match_flag_or[6]_i_1_n_0 ));\n FDSE \\match_flag_or_reg[0] \n (.C(CLK),\n .CE(match_flag_and),\n .D(\\match_flag_or[0]_i_1_n_0 ),\n .Q(sel0[1]),\n .S(rstdiv0_sync_r1_reg_rep__9));\n FDSE \\match_flag_or_reg[1] \n (.C(CLK),\n .CE(match_flag_and),\n .D(\\match_flag_or[1]_i_1_n_0 ),\n .Q(sel0[2]),\n .S(rstdiv0_sync_r1_reg_rep__9));\n FDSE \\match_flag_or_reg[2] \n (.C(CLK),\n .CE(match_flag_and),\n .D(\\match_flag_or[2]_i_1_n_0 ),\n .Q(sel0[3]),\n .S(rstdiv0_sync_r1_reg_rep__9));\n FDSE \\match_flag_or_reg[3] \n (.C(CLK),\n .CE(match_flag_and),\n .D(\\match_flag_or[3]_i_1_n_0 ),\n .Q(sel0[4]),\n .S(rstdiv0_sync_r1_reg_rep__9));\n FDSE \\match_flag_or_reg[4] \n (.C(CLK),\n .CE(match_flag_and),\n .D(\\match_flag_or[4]_i_1_n_0 ),\n .Q(sel0[5]),\n .S(rstdiv0_sync_r1_reg_rep__9));\n FDSE \\match_flag_or_reg[5] \n (.C(CLK),\n .CE(match_flag_and),\n .D(\\match_flag_or[5]_i_1_n_0 ),\n .Q(sel0[6]),\n .S(rstdiv0_sync_r1_reg_rep__9));\n FDSE \\match_flag_or_reg[6] \n (.C(CLK),\n .CE(match_flag_and),\n .D(\\match_flag_or[6]_i_1_n_0 ),\n .Q(sel0[7]),\n .S(rstdiv0_sync_r1_reg_rep__9));\n FDRE mux_rd_valid_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .Q(mux_rd_valid_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h88888B88)) \n new_cnt_dqs_r_i_2\n (.I0(prech_done),\n .I1(Q[3]),\n .I2(prbs_rdlvl_start_r),\n .I3(prbs_rdlvl_start_reg),\n .I4(Q[0]),\n .O(new_cnt_dqs_r));\n LUT6 #(\n .INIT(64'h0030BBBB00308888)) \n new_cnt_dqs_r_i_3\n (.I0(cnt_wait_state),\n .I1(Q[0]),\n .I2(prech_done),\n .I3(prbs_last_byte_done_reg_0),\n .I4(Q[3]),\n .I5(prbs_rdlvl_start_reg_0),\n .O(new_cnt_dqs_r_reg_0));\n FDRE new_cnt_dqs_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\prbs_state_r_reg[4]_0 ),\n .Q(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .R(rstdiv0_sync_r1_reg_rep__7));\n (* SOFT_HLUTNM = \"soft_lutpair68\" *) \n LUT4 #(\n .INIT(16'h0100)) \n no_err_win_detected_i_1\n (.I0(Q[1]),\n .I1(no_err_win_detected_i_2_n_0),\n .I2(no_err_win_detected_i_3_n_0),\n .I3(Q[4]),\n .O(no_err_win_detected_i_1_n_0));\n LUT4 #(\n .INIT(16'hFFFE)) \n no_err_win_detected_i_2\n (.I0(sel0[7]),\n .I1(sel0[6]),\n .I2(sel0[4]),\n .I3(sel0[5]),\n .O(no_err_win_detected_i_2_n_0));\n LUT4 #(\n .INIT(16'hFFFE)) \n no_err_win_detected_i_3\n (.I0(sel0[2]),\n .I1(sel0[3]),\n .I2(sel0[0]),\n .I3(sel0[1]),\n .O(no_err_win_detected_i_3_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair49\" *) \n LUT5 #(\n .INIT(32'h20000003)) \n no_err_win_detected_latch_i_2\n (.I0(no_err_win_detected_latch_reg_0),\n .I1(Q[4]),\n .I2(Q[2]),\n .I3(Q[3]),\n .I4(Q[1]),\n .O(no_err_win_detected_latch_reg_1));\n FDRE no_err_win_detected_latch_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\prbs_state_r_reg[3]_1 ),\n .Q(\\largest_left_edge_reg[0]_0 ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE no_err_win_detected_reg\n (.C(CLK),\n .CE(match_flag_and),\n .D(no_err_win_detected_i_1_n_0),\n .Q(no_err_win_detected_latch_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__2));\n (* SOFT_HLUTNM = \"soft_lutpair52\" *) \n LUT2 #(\n .INIT(4'hE)) \n num_samples_done_ind_i_2\n (.I0(Q[2]),\n .I1(Q[3]),\n .O(num_samples_done_ind_reg_0));\n FDRE num_samples_done_ind_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\prbs_state_r_reg[4]_1 ),\n .Q(\\match_flag_or_reg[0]_0 ),\n .R(rstdiv0_sync_r1_reg_rep__2));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\oclkdelay_ref_cnt[0]_i_3 \n (.I0(\\stg1_wr_rd_cnt_reg[3] ),\n .I1(rstdiv0_sync_r1_reg_rep__24),\n .I2(oclkdelay_center_calib_done_r_reg),\n .I3(ocal_last_byte_done),\n .O(\\oclkdelay_ref_cnt_reg[0] ));\n FDRE pi_en_stg2_f_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_en_stg2_f_timing),\n .Q(prbs_pi_stg2_f_en),\n .R(1'b0));\n FDRE pi_en_stg2_f_timing_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_en_stg2_f_timing_reg_0),\n .Q(pi_en_stg2_f_timing),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE pi_stg2_f_incdec_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_stg2_f_incdec_timing),\n .Q(prbs_pi_stg2_f_incdec),\n .R(1'b0));\n FDRE pi_stg2_f_incdec_timing_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prbs_tap_inc_r_reg_0),\n .Q(pi_stg2_f_incdec_timing),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair74\" *) \n LUT3 #(\n .INIT(8'h47)) \n \\prbs_dec_tap_cnt[0]_i_1 \n (.I0(\\prbs_dec_tap_cnt_reg[1]_0 [0]),\n .I1(Q[2]),\n .I2(prbs_dec_tap_cnt[0]),\n .O(\\prbs_dec_tap_cnt[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h1AFF1A001A001AFF)) \n \\prbs_dec_tap_cnt[1]_i_1 \n (.I0(dec_cnt_reg[1]),\n .I1(\\prbs_dec_tap_cnt_reg[1]_0 [1]),\n .I2(\\prbs_dec_tap_cnt_reg[1]_0 [0]),\n .I3(Q[2]),\n .I4(prbs_dec_tap_cnt[0]),\n .I5(prbs_dec_tap_cnt[1]),\n .O(\\prbs_dec_tap_cnt[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h060006FF06FF0600)) \n \\prbs_dec_tap_cnt[2]_i_1 \n (.I0(dec_cnt_reg[2]),\n .I1(\\prbs_dec_tap_cnt[2]_i_2_n_0 ),\n .I2(\\prbs_dec_tap_cnt[2]_i_3_n_0 ),\n .I3(Q[2]),\n .I4(\\prbs_dec_tap_cnt[2]_i_4_n_0 ),\n .I5(prbs_dec_tap_cnt[2]),\n .O(\\prbs_dec_tap_cnt[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair74\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\prbs_dec_tap_cnt[2]_i_2 \n (.I0(dec_cnt_reg[1]),\n .I1(\\prbs_dec_tap_cnt_reg[1]_0 [0]),\n .O(\\prbs_dec_tap_cnt[2]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair50\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\prbs_dec_tap_cnt[2]_i_3 \n (.I0(\\prbs_dec_tap_cnt_reg[1]_0 [0]),\n .I1(\\prbs_dec_tap_cnt_reg[1]_0 [1]),\n .O(\\prbs_dec_tap_cnt[2]_i_3_n_0 ));\n LUT2 #(\n .INIT(4'h1)) \n \\prbs_dec_tap_cnt[2]_i_4 \n (.I0(prbs_dec_tap_cnt[0]),\n .I1(prbs_dec_tap_cnt[1]),\n .O(\\prbs_dec_tap_cnt[2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hBBBBBBB88888888B)) \n \\prbs_dec_tap_cnt[3]_i_1 \n (.I0(\\prbs_dec_tap_cnt[3]_i_2_n_0 ),\n .I1(Q[2]),\n .I2(prbs_dec_tap_cnt[0]),\n .I3(prbs_dec_tap_cnt[1]),\n .I4(prbs_dec_tap_cnt[2]),\n .I5(prbs_dec_tap_cnt[3]),\n .O(\\prbs_dec_tap_cnt[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair50\" *) \n LUT5 #(\n .INIT(32'h006AAAAA)) \n \\prbs_dec_tap_cnt[3]_i_2 \n (.I0(dec_cnt_reg[3]),\n .I1(dec_cnt_reg[2]),\n .I2(dec_cnt_reg[1]),\n .I3(\\prbs_dec_tap_cnt_reg[1]_0 [1]),\n .I4(\\prbs_dec_tap_cnt_reg[1]_0 [0]),\n .O(\\prbs_dec_tap_cnt[3]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFE0001)) \n \\prbs_dec_tap_cnt[4]_i_2 \n (.I0(prbs_dec_tap_cnt[3]),\n .I1(prbs_dec_tap_cnt[2]),\n .I2(prbs_dec_tap_cnt[1]),\n .I3(prbs_dec_tap_cnt[0]),\n .I4(prbs_dec_tap_cnt[4]),\n .O(\\prbs_dec_tap_cnt[4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00006AAAAAAAAAAA)) \n \\prbs_dec_tap_cnt[4]_i_3 \n (.I0(dec_cnt_reg[4]),\n .I1(dec_cnt_reg[3]),\n .I2(dec_cnt_reg[1]),\n .I3(dec_cnt_reg[2]),\n .I4(\\prbs_dec_tap_cnt_reg[1]_0 [1]),\n .I5(\\prbs_dec_tap_cnt_reg[1]_0 [0]),\n .O(\\prbs_dec_tap_cnt[4]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h1010100000000000)) \n \\prbs_dec_tap_cnt[5]_i_1 \n (.I0(Q[4]),\n .I1(Q[3]),\n .I2(Q[1]),\n .I3(p_3_in),\n .I4(Q[2]),\n .I5(Q[0]),\n .O(\\prbs_dec_tap_cnt[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\prbs_dec_tap_cnt[5]_i_3 \n (.I0(prbs_dec_tap_cnt[2]),\n .I1(prbs_dec_tap_cnt[0]),\n .I2(prbs_dec_tap_cnt[1]),\n .I3(prbs_dec_tap_cnt[4]),\n .I4(prbs_dec_tap_cnt[3]),\n .I5(prbs_dec_tap_cnt[5]),\n .O(p_3_in));\n LUT6 #(\n .INIT(64'hFFFFFFFE00000001)) \n \\prbs_dec_tap_cnt[5]_i_4 \n (.I0(prbs_dec_tap_cnt[4]),\n .I1(prbs_dec_tap_cnt[0]),\n .I2(prbs_dec_tap_cnt[1]),\n .I3(prbs_dec_tap_cnt[2]),\n .I4(prbs_dec_tap_cnt[3]),\n .I5(prbs_dec_tap_cnt[5]),\n .O(\\prbs_dec_tap_cnt[5]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hEAAAAAAAAAAAAAAA)) \n \\prbs_dec_tap_cnt[5]_i_5 \n (.I0(\\prbs_dec_tap_cnt_reg[1]_0 [1]),\n .I1(dec_cnt_reg[4]),\n .I2(dec_cnt_reg[2]),\n .I3(\\prbs_dec_tap_cnt_reg[1]_0 [0]),\n .I4(dec_cnt_reg[1]),\n .I5(dec_cnt_reg[3]),\n .O(\\prbs_dec_tap_cnt[5]_i_5_n_0 ));\n FDRE \\prbs_dec_tap_cnt_reg[0] \n (.C(CLK),\n .CE(\\prbs_dec_tap_cnt[5]_i_1_n_0 ),\n .D(\\prbs_dec_tap_cnt[0]_i_1_n_0 ),\n .Q(prbs_dec_tap_cnt[0]),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE \\prbs_dec_tap_cnt_reg[1] \n (.C(CLK),\n .CE(\\prbs_dec_tap_cnt[5]_i_1_n_0 ),\n .D(\\prbs_dec_tap_cnt[1]_i_1_n_0 ),\n .Q(prbs_dec_tap_cnt[1]),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE \\prbs_dec_tap_cnt_reg[2] \n (.C(CLK),\n .CE(\\prbs_dec_tap_cnt[5]_i_1_n_0 ),\n .D(\\prbs_dec_tap_cnt[2]_i_1_n_0 ),\n .Q(prbs_dec_tap_cnt[2]),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE \\prbs_dec_tap_cnt_reg[3] \n (.C(CLK),\n .CE(\\prbs_dec_tap_cnt[5]_i_1_n_0 ),\n .D(\\prbs_dec_tap_cnt[3]_i_1_n_0 ),\n .Q(prbs_dec_tap_cnt[3]),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE \\prbs_dec_tap_cnt_reg[4] \n (.C(CLK),\n .CE(\\prbs_dec_tap_cnt[5]_i_1_n_0 ),\n .D(\\prbs_dec_tap_cnt_reg[4]_i_1_n_0 ),\n .Q(prbs_dec_tap_cnt[4]),\n .R(rstdiv0_sync_r1_reg_rep__9));\n MUXF7 \\prbs_dec_tap_cnt_reg[4]_i_1 \n (.I0(\\prbs_dec_tap_cnt[4]_i_2_n_0 ),\n .I1(\\prbs_dec_tap_cnt[4]_i_3_n_0 ),\n .O(\\prbs_dec_tap_cnt_reg[4]_i_1_n_0 ),\n .S(Q[2]));\n FDRE \\prbs_dec_tap_cnt_reg[5] \n (.C(CLK),\n .CE(\\prbs_dec_tap_cnt[5]_i_1_n_0 ),\n .D(\\prbs_dec_tap_cnt_reg[5]_i_2_n_0 ),\n .Q(prbs_dec_tap_cnt[5]),\n .R(rstdiv0_sync_r1_reg_rep__9));\n MUXF7 \\prbs_dec_tap_cnt_reg[5]_i_2 \n (.I0(\\prbs_dec_tap_cnt[5]_i_4_n_0 ),\n .I1(\\prbs_dec_tap_cnt[5]_i_5_n_0 ),\n .O(\\prbs_dec_tap_cnt_reg[5]_i_2_n_0 ),\n .S(Q[2]));\n LUT6 #(\n .INIT(64'h0000000000000800)) \n \\prbs_dqs_cnt_r[1]_i_2 \n (.I0(prbs_rdlvl_done_reg_1),\n .I1(Q[3]),\n .I2(prbs_last_byte_done_reg_0),\n .I3(prech_done),\n .I4(Q[1]),\n .I5(Q[2]),\n .O(\\prbs_dqs_cnt_r_reg[1]_0 ));\n FDRE \\prbs_dqs_cnt_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\prbs_dqs_cnt_r_reg[0]_1 ),\n .Q(\\A[0]_0 ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE \\prbs_dqs_cnt_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\prbs_dqs_cnt_r_reg[0]_0 ),\n .Q(\\A[1]_0 ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE \\prbs_dqs_cnt_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\prbs_dqs_cnt_r_reg[0]_2 ),\n .Q(\\prbs_dqs_cnt_r_reg[2]_0 ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n (* SOFT_HLUTNM = \"soft_lutpair69\" *) \n LUT4 #(\n .INIT(16'h404F)) \n \\prbs_dqs_tap_cnt_r[0]_i_1 \n (.I0(\\calib_sel_reg[3] ),\n .I1(\\pi_counter_read_val_reg[5] [0]),\n .I2(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .O(\\prbs_dqs_tap_cnt_r[0]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h404F)) \n \\prbs_dqs_tap_cnt_r[0]_rep__0_i_1 \n (.I0(\\calib_sel_reg[3] ),\n .I1(\\pi_counter_read_val_reg[5] [0]),\n .I2(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .O(\\prbs_dqs_tap_cnt_r[0]_rep__0_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h404F)) \n \\prbs_dqs_tap_cnt_r[0]_rep_i_1 \n (.I0(\\calib_sel_reg[3] ),\n .I1(\\pi_counter_read_val_reg[5] [0]),\n .I2(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .O(\\prbs_dqs_tap_cnt_r[0]_rep_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0F0066660F009999)) \n \\prbs_dqs_tap_cnt_r[1]_i_1 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I2(\\calib_sel_reg[3] ),\n .I3(\\pi_counter_read_val_reg[5] [1]),\n .I4(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .I5(prbs_tap_inc_r),\n .O(\\prbs_dqs_tap_cnt_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0F0066660F009999)) \n \\prbs_dqs_tap_cnt_r[1]_rep__0_i_1 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I2(\\calib_sel_reg[3] ),\n .I3(\\pi_counter_read_val_reg[5] [1]),\n .I4(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .I5(prbs_tap_inc_r),\n .O(\\prbs_dqs_tap_cnt_r[1]_rep__0_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0F0066660F009999)) \n \\prbs_dqs_tap_cnt_r[1]_rep_i_1 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .I2(\\calib_sel_reg[3] ),\n .I3(\\pi_counter_read_val_reg[5] [1]),\n .I4(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .I5(prbs_tap_inc_r),\n .O(\\prbs_dqs_tap_cnt_r[1]_rep_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8BB8BB88BB88B88B)) \n \\prbs_dqs_tap_cnt_r[2]_i_1 \n (.I0(\\calib_sel_reg[3]_1 ),\n .I1(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .I2(prbs_tap_inc_r),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .O(\\prbs_dqs_tap_cnt_r[2]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hB888B8BB)) \n \\prbs_dqs_tap_cnt_r[3]_i_1 \n (.I0(\\rdlvl_cpt_tap_cnt_reg[5]_1 [1]),\n .I1(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .I2(\\prbs_dqs_tap_cnt_r[3]_i_2_n_0 ),\n .I3(prbs_tap_inc_r),\n .I4(\\prbs_dqs_tap_cnt_r[3]_i_3_n_0 ),\n .O(\\prbs_dqs_tap_cnt_r[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair45\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\prbs_dqs_tap_cnt_r[3]_i_2 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I1(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .O(\\prbs_dqs_tap_cnt_r[3]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair63\" *) \n LUT4 #(\n .INIT(16'h01FE)) \n \\prbs_dqs_tap_cnt_r[3]_i_3 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .O(\\prbs_dqs_tap_cnt_r[3]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hB888B8BB)) \n \\prbs_dqs_tap_cnt_r[3]_rep__0_i_1 \n (.I0(\\rdlvl_cpt_tap_cnt_reg[5]_1 [1]),\n .I1(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .I2(\\prbs_dqs_tap_cnt_r[3]_i_2_n_0 ),\n .I3(prbs_tap_inc_r),\n .I4(\\prbs_dqs_tap_cnt_r[3]_i_3_n_0 ),\n .O(\\prbs_dqs_tap_cnt_r[3]_rep__0_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hB888B8BB)) \n \\prbs_dqs_tap_cnt_r[3]_rep_i_1 \n (.I0(\\rdlvl_cpt_tap_cnt_reg[5]_1 [1]),\n .I1(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .I2(\\prbs_dqs_tap_cnt_r[3]_i_2_n_0 ),\n .I3(prbs_tap_inc_r),\n .I4(\\prbs_dqs_tap_cnt_r[3]_i_3_n_0 ),\n .O(\\prbs_dqs_tap_cnt_r[3]_rep_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8BB888888BB8BBBB)) \n \\prbs_dqs_tap_cnt_r[4]_i_1 \n (.I0(\\calib_sel_reg[3]_2 ),\n .I1(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .I2(\\prbs_dqs_tap_cnt_r[4]_i_2_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I4(prbs_tap_inc_r),\n .I5(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ),\n .O(\\prbs_dqs_tap_cnt_r[4]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8000)) \n \\prbs_dqs_tap_cnt_r[4]_i_2 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I1(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .O(\\prbs_dqs_tap_cnt_r[4]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h0001FFFE)) \n \\prbs_dqs_tap_cnt_r[4]_i_3 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I1(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .O(\\prbs_dqs_tap_cnt_r[4]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'hFEAA)) \n \\prbs_dqs_tap_cnt_r[5]_i_1 \n (.I0(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .I1(prbs_tap_inc_r),\n .I2(\\prbs_dqs_tap_cnt_r[5]_i_3_n_0 ),\n .I3(pi_en_stg2_f_timing_reg_0),\n .O(\\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hB888B8BB)) \n \\prbs_dqs_tap_cnt_r[5]_i_2 \n (.I0(\\rdlvl_cpt_tap_cnt_reg[5]_1 [2]),\n .I1(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .I2(\\prbs_dqs_tap_cnt_r[5]_i_4_n_0 ),\n .I3(prbs_tap_inc_r),\n .I4(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\prbs_dqs_tap_cnt_r[5]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\prbs_dqs_tap_cnt_r[5]_i_3 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\prbs_dqs_tap_cnt_r[5]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h7FFFFFFF80000000)) \n \\prbs_dqs_tap_cnt_r[5]_i_4 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I1(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\prbs_dqs_tap_cnt_r[5]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h00000001FFFFFFFE)) \n \\prbs_dqs_tap_cnt_r[5]_i_5 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ));\n (* ORIG_CELL_NAME = \"prbs_dqs_tap_cnt_r_reg[0]\" *) \n FDRE \\prbs_dqs_tap_cnt_r_reg[0] \n (.C(CLK),\n .CE(\\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ),\n .D(\\prbs_dqs_tap_cnt_r[0]_i_1_n_0 ),\n .Q(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n (* ORIG_CELL_NAME = \"prbs_dqs_tap_cnt_r_reg[0]\" *) \n FDRE \\prbs_dqs_tap_cnt_r_reg[0]_rep \n (.C(CLK),\n .CE(\\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ),\n .D(\\prbs_dqs_tap_cnt_r[0]_rep_i_1_n_0 ),\n .Q(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .R(rstdiv0_sync_r1_reg_rep));\n (* ORIG_CELL_NAME = \"prbs_dqs_tap_cnt_r_reg[0]\" *) \n FDRE \\prbs_dqs_tap_cnt_r_reg[0]_rep__0 \n (.C(CLK),\n .CE(\\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ),\n .D(\\prbs_dqs_tap_cnt_r[0]_rep__0_i_1_n_0 ),\n .Q(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .R(rstdiv0_sync_r1_reg_rep));\n (* ORIG_CELL_NAME = \"prbs_dqs_tap_cnt_r_reg[1]\" *) \n FDRE \\prbs_dqs_tap_cnt_r_reg[1] \n (.C(CLK),\n .CE(\\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ),\n .D(\\prbs_dqs_tap_cnt_r[1]_i_1_n_0 ),\n .Q(\\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n (* ORIG_CELL_NAME = \"prbs_dqs_tap_cnt_r_reg[1]\" *) \n FDRE \\prbs_dqs_tap_cnt_r_reg[1]_rep \n (.C(CLK),\n .CE(\\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ),\n .D(\\prbs_dqs_tap_cnt_r[1]_rep_i_1_n_0 ),\n .Q(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .R(rstdiv0_sync_r1_reg_rep));\n (* ORIG_CELL_NAME = \"prbs_dqs_tap_cnt_r_reg[1]\" *) \n FDRE \\prbs_dqs_tap_cnt_r_reg[1]_rep__0 \n (.C(CLK),\n .CE(\\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ),\n .D(\\prbs_dqs_tap_cnt_r[1]_rep__0_i_1_n_0 ),\n .Q(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE \\prbs_dqs_tap_cnt_r_reg[2] \n (.C(CLK),\n .CE(\\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ),\n .D(\\prbs_dqs_tap_cnt_r[2]_i_1_n_0 ),\n .Q(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n (* ORIG_CELL_NAME = \"prbs_dqs_tap_cnt_r_reg[3]\" *) \n FDRE \\prbs_dqs_tap_cnt_r_reg[3] \n (.C(CLK),\n .CE(\\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ),\n .D(\\prbs_dqs_tap_cnt_r[3]_i_1_n_0 ),\n .Q(\\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n (* ORIG_CELL_NAME = \"prbs_dqs_tap_cnt_r_reg[3]\" *) \n FDRE \\prbs_dqs_tap_cnt_r_reg[3]_rep \n (.C(CLK),\n .CE(\\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ),\n .D(\\prbs_dqs_tap_cnt_r[3]_rep_i_1_n_0 ),\n .Q(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .R(rstdiv0_sync_r1_reg_rep));\n (* ORIG_CELL_NAME = \"prbs_dqs_tap_cnt_r_reg[3]\" *) \n FDRE \\prbs_dqs_tap_cnt_r_reg[3]_rep__0 \n (.C(CLK),\n .CE(\\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ),\n .D(\\prbs_dqs_tap_cnt_r[3]_rep__0_i_1_n_0 ),\n .Q(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE \\prbs_dqs_tap_cnt_r_reg[4] \n (.C(CLK),\n .CE(\\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ),\n .D(\\prbs_dqs_tap_cnt_r[4]_i_1_n_0 ),\n .Q(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE \\prbs_dqs_tap_cnt_r_reg[5] \n (.C(CLK),\n .CE(\\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ),\n .D(\\prbs_dqs_tap_cnt_r[5]_i_2_n_0 ),\n .Q(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE prbs_dqs_tap_limit_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(new_cnt_dqs_r_reg_1),\n .Q(prbs_dqs_tap_limit_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAAAAAB)) \n prbs_found_1st_edge_r_i_2\n (.I0(compare_err_latch_reg_n_0),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[3]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .I5(prbs_found_1st_edge_r_i_5_n_0),\n .O(prbs_state_r178_out));\n (* SOFT_HLUTNM = \"soft_lutpair30\" *) \n LUT2 #(\n .INIT(4'h1)) \n prbs_found_1st_edge_r_i_3\n (.I0(Q[2]),\n .I1(Q[4]),\n .O(complex_pi_incdec_done_reg_1));\n (* SOFT_HLUTNM = \"soft_lutpair28\" *) \n LUT5 #(\n .INIT(32'h00FF2000)) \n prbs_found_1st_edge_r_i_4\n (.I0(prbs_state_r178_out),\n .I1(prbs_dqs_tap_limit_r),\n .I2(num_samples_done_r),\n .I3(Q[1]),\n .I4(Q[3]),\n .O(prbs_found_1st_edge_r_reg_1));\n (* SOFT_HLUTNM = \"soft_lutpair70\" *) \n LUT2 #(\n .INIT(4'hE)) \n prbs_found_1st_edge_r_i_5\n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .O(prbs_found_1st_edge_r_i_5_n_0));\n FDRE prbs_found_1st_edge_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\prbs_state_r_reg[3]_0 ),\n .Q(prbs_found_1st_edge_r_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__7));\n LUT4 #(\n .INIT(16'h06F6)) \n \\prbs_inc_tap_cnt[0]_i_1 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I1(rdlvl_cpt_tap_cnt[0]),\n .I2(Q[2]),\n .I3(\\prbs_inc_tap_cnt_reg_n_0_[0] ),\n .O(\\prbs_inc_tap_cnt[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAA3055CFAACF5530)) \n \\prbs_inc_tap_cnt[1]_i_1 \n (.I0(\\prbs_inc_tap_cnt_reg_n_0_[0] ),\n .I1(rdlvl_cpt_tap_cnt[0]),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(Q[2]),\n .I4(\\prbs_inc_tap_cnt[1]_i_2_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .O(\\prbs_inc_tap_cnt[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair73\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\prbs_inc_tap_cnt[1]_i_2 \n (.I0(\\prbs_inc_tap_cnt_reg_n_0_[1] ),\n .I1(Q[2]),\n .I2(rdlvl_cpt_tap_cnt[1]),\n .O(\\prbs_inc_tap_cnt[1]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair48\" *) \n LUT5 #(\n .INIT(32'h99699966)) \n \\prbs_inc_tap_cnt[2]_i_1 \n (.I0(\\prbs_inc_tap_cnt[2]_i_2_n_0 ),\n .I1(\\prbs_inc_tap_cnt[2]_i_3_n_0 ),\n .I2(rdlvl_cpt_tap_cnt[1]),\n .I3(Q[2]),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .O(\\prbs_inc_tap_cnt[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFCFAAFFFFFFAACF)) \n \\prbs_inc_tap_cnt[2]_i_2 \n (.I0(\\prbs_inc_tap_cnt_reg_n_0_[0] ),\n .I1(rdlvl_cpt_tap_cnt[0]),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep__0_n_0 ),\n .I3(Q[2]),\n .I4(\\prbs_inc_tap_cnt[1]_i_2_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .O(\\prbs_inc_tap_cnt[2]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair59\" *) \n LUT4 #(\n .INIT(16'hF909)) \n \\prbs_inc_tap_cnt[2]_i_3 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I1(rdlvl_cpt_tap_cnt[2]),\n .I2(Q[2]),\n .I3(\\prbs_inc_tap_cnt_reg_n_0_[2] ),\n .O(\\prbs_inc_tap_cnt[2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h6666669699996696)) \n \\prbs_inc_tap_cnt[3]_i_1 \n (.I0(\\prbs_inc_tap_cnt[3]_i_2_n_0 ),\n .I1(\\prbs_inc_tap_cnt[3]_i_3_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(rdlvl_cpt_tap_cnt[2]),\n .I4(Q[2]),\n .I5(\\prbs_inc_tap_cnt_reg_n_0_[2] ),\n .O(\\prbs_inc_tap_cnt[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF477447740000)) \n \\prbs_inc_tap_cnt[3]_i_2 \n (.I0(\\prbs_inc_tap_cnt_reg_n_0_[2] ),\n .I1(Q[2]),\n .I2(rdlvl_cpt_tap_cnt[2]),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I4(\\prbs_inc_tap_cnt[3]_i_4_n_0 ),\n .I5(\\prbs_inc_tap_cnt[2]_i_2_n_0 ),\n .O(\\prbs_inc_tap_cnt[3]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair62\" *) \n LUT4 #(\n .INIT(16'hF909)) \n \\prbs_inc_tap_cnt[3]_i_3 \n (.I0(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I1(rdlvl_cpt_tap_cnt[3]),\n .I2(Q[2]),\n .I3(\\prbs_inc_tap_cnt_reg_n_0_[3] ),\n .O(\\prbs_inc_tap_cnt[3]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair48\" *) \n LUT3 #(\n .INIT(8'h23)) \n \\prbs_inc_tap_cnt[3]_i_4 \n (.I0(rdlvl_cpt_tap_cnt[1]),\n .I1(Q[2]),\n .I2(\\prbs_dqs_tap_cnt_r_reg[1]_rep_n_0 ),\n .O(\\prbs_inc_tap_cnt[3]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h6666669699996696)) \n \\prbs_inc_tap_cnt[4]_i_1 \n (.I0(\\prbs_inc_tap_cnt[5]_i_5_n_0 ),\n .I1(\\prbs_inc_tap_cnt[4]_i_2_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I3(rdlvl_cpt_tap_cnt[3]),\n .I4(Q[2]),\n .I5(\\prbs_inc_tap_cnt_reg_n_0_[3] ),\n .O(\\prbs_inc_tap_cnt[4]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair64\" *) \n LUT4 #(\n .INIT(16'hF909)) \n \\prbs_inc_tap_cnt[4]_i_2 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I1(rdlvl_cpt_tap_cnt[4]),\n .I2(Q[2]),\n .I3(\\prbs_inc_tap_cnt_reg_n_0_[4] ),\n .O(\\prbs_inc_tap_cnt[4]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h00004540)) \n \\prbs_inc_tap_cnt[5]_i_1 \n (.I0(Q[3]),\n .I1(\\prbs_inc_tap_cnt[5]_i_3_n_0 ),\n .I2(Q[2]),\n .I3(\\prbs_inc_tap_cnt[5]_i_4_n_0 ),\n .I4(Q[4]),\n .O(\\prbs_inc_tap_cnt[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h7878781EE1E1E178)) \n \\prbs_inc_tap_cnt[5]_i_2 \n (.I0(\\prbs_inc_tap_cnt[5]_i_5_n_0 ),\n .I1(\\prbs_inc_tap_cnt[5]_i_6_n_0 ),\n .I2(\\prbs_inc_tap_cnt[5]_i_7_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I4(Q[2]),\n .I5(\\prbs_inc_tap_cnt[5]_i_8_n_0 ),\n .O(\\prbs_inc_tap_cnt[5]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair21\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\prbs_inc_tap_cnt[5]_i_3 \n (.I0(\\prbs_state_r[1]_i_5_n_0 ),\n .I1(Q[0]),\n .I2(Q[1]),\n .O(\\prbs_inc_tap_cnt[5]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000200000)) \n \\prbs_inc_tap_cnt[5]_i_4 \n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(prbs_state_r178_out),\n .I3(prbs_found_1st_edge_r_reg_0),\n .I4(num_samples_done_r),\n .I5(prbs_dqs_tap_limit_r),\n .O(\\prbs_inc_tap_cnt[5]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF477447740000)) \n \\prbs_inc_tap_cnt[5]_i_5 \n (.I0(\\prbs_inc_tap_cnt_reg_n_0_[3] ),\n .I1(Q[2]),\n .I2(rdlvl_cpt_tap_cnt[3]),\n .I3(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I4(\\prbs_inc_tap_cnt[5]_i_9_n_0 ),\n .I5(\\prbs_inc_tap_cnt[3]_i_2_n_0 ),\n .O(\\prbs_inc_tap_cnt[5]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair62\" *) \n LUT4 #(\n .INIT(16'hFD0D)) \n \\prbs_inc_tap_cnt[5]_i_6 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),\n .I1(rdlvl_cpt_tap_cnt[3]),\n .I2(Q[2]),\n .I3(\\prbs_inc_tap_cnt_reg_n_0_[3] ),\n .O(\\prbs_inc_tap_cnt[5]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair70\" *) \n LUT4 #(\n .INIT(16'hF909)) \n \\prbs_inc_tap_cnt[5]_i_7 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .I1(rdlvl_cpt_tap_cnt[5]),\n .I2(Q[2]),\n .I3(\\prbs_inc_tap_cnt_reg_n_0_[5] ),\n .O(\\prbs_inc_tap_cnt[5]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair64\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\prbs_inc_tap_cnt[5]_i_8 \n (.I0(\\prbs_inc_tap_cnt_reg_n_0_[4] ),\n .I1(Q[2]),\n .I2(rdlvl_cpt_tap_cnt[4]),\n .O(\\prbs_inc_tap_cnt[5]_i_8_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair59\" *) \n LUT4 #(\n .INIT(16'hFD0D)) \n \\prbs_inc_tap_cnt[5]_i_9 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I1(rdlvl_cpt_tap_cnt[2]),\n .I2(Q[2]),\n .I3(\\prbs_inc_tap_cnt_reg_n_0_[2] ),\n .O(\\prbs_inc_tap_cnt[5]_i_9_n_0 ));\n FDRE \\prbs_inc_tap_cnt_reg[0] \n (.C(CLK),\n .CE(\\prbs_inc_tap_cnt[5]_i_1_n_0 ),\n .D(\\prbs_inc_tap_cnt[0]_i_1_n_0 ),\n .Q(\\prbs_inc_tap_cnt_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE \\prbs_inc_tap_cnt_reg[1] \n (.C(CLK),\n .CE(\\prbs_inc_tap_cnt[5]_i_1_n_0 ),\n .D(\\prbs_inc_tap_cnt[1]_i_1_n_0 ),\n .Q(\\prbs_inc_tap_cnt_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE \\prbs_inc_tap_cnt_reg[2] \n (.C(CLK),\n .CE(\\prbs_inc_tap_cnt[5]_i_1_n_0 ),\n .D(\\prbs_inc_tap_cnt[2]_i_1_n_0 ),\n .Q(\\prbs_inc_tap_cnt_reg_n_0_[2] ),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE \\prbs_inc_tap_cnt_reg[3] \n (.C(CLK),\n .CE(\\prbs_inc_tap_cnt[5]_i_1_n_0 ),\n .D(\\prbs_inc_tap_cnt[3]_i_1_n_0 ),\n .Q(\\prbs_inc_tap_cnt_reg_n_0_[3] ),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE \\prbs_inc_tap_cnt_reg[4] \n (.C(CLK),\n .CE(\\prbs_inc_tap_cnt[5]_i_1_n_0 ),\n .D(\\prbs_inc_tap_cnt[4]_i_1_n_0 ),\n .Q(\\prbs_inc_tap_cnt_reg_n_0_[4] ),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE \\prbs_inc_tap_cnt_reg[5] \n (.C(CLK),\n .CE(\\prbs_inc_tap_cnt[5]_i_1_n_0 ),\n .D(\\prbs_inc_tap_cnt[5]_i_2_n_0 ),\n .Q(\\prbs_inc_tap_cnt_reg_n_0_[5] ),\n .R(rstdiv0_sync_r1_reg_rep__7));\n LUT3 #(\n .INIT(8'hEA)) \n prbs_last_byte_done_i_2\n (.I0(\\prbs_dqs_cnt_r_reg[2]_0 ),\n .I1(\\A[0]_0 ),\n .I2(\\A[1]_0 ),\n .O(prbs_last_byte_done_reg_0));\n FDRE prbs_last_byte_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\prbs_state_r_reg[0]_3 ),\n .Q(prbs_last_byte_done),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE prbs_prech_req_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prech_done_reg),\n .Q(prbs_prech_req_r),\n .R(rstdiv0_sync_r1_reg_rep__8));\n (* SOFT_HLUTNM = \"soft_lutpair68\" *) \n LUT2 #(\n .INIT(4'h1)) \n prbs_rdlvl_done_i_2\n (.I0(Q[4]),\n .I1(Q[0]),\n .O(prbs_rdlvl_done_reg_1));\n LUT2 #(\n .INIT(4'h2)) \n prbs_rdlvl_done_pulse_i_1\n (.I0(complex_oclkdelay_calib_done_r1_reg),\n .I1(prbs_rdlvl_done_r1),\n .O(prbs_rdlvl_done_pulse0));\n (* MAX_FANOUT = \"100\" *) \n (* ORIG_CELL_NAME = \"prbs_rdlvl_done_reg\" *) \n FDRE prbs_rdlvl_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(fine_dly_error_reg_1),\n .Q(\\stg1_wr_rd_cnt_reg[3] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* MAX_FANOUT = \"100\" *) \n (* ORIG_CELL_NAME = \"prbs_rdlvl_done_reg\" *) \n FDRE prbs_rdlvl_done_reg_rep\n (.C(CLK),\n .CE(1'b1),\n .D(fine_dly_error_reg_1),\n .Q(complex_oclkdelay_calib_done_r1_reg),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE prbs_rdlvl_prech_req_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prbs_prech_req_r),\n .Q(prech_req_r_reg),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE prbs_rdlvl_start_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(prbs_rdlvl_start_reg),\n .Q(prbs_rdlvl_start_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFF0DFDFFFF0D0D0)) \n \\prbs_state_r[0]_i_1 \n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(Q[4]),\n .I3(\\prbs_state_r[0]_i_2_n_0 ),\n .I4(\\prbs_state_r[0]_i_3_n_0 ),\n .I5(\\prbs_state_r[0]_i_4_n_0 ),\n .O(\\prbs_state_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h1C1C1C1C1C1D1D1D)) \n \\prbs_state_r[0]_i_2 \n (.I0(Q[1]),\n .I1(Q[2]),\n .I2(Q[0]),\n .I3(\\A[1]_0 ),\n .I4(\\A[0]_0 ),\n .I5(\\prbs_dqs_cnt_r_reg[2]_0 ),\n .O(\\prbs_state_r[0]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair29\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\prbs_state_r[0]_i_3 \n (.I0(Q[2]),\n .I1(Q[4]),\n .I2(Q[3]),\n .O(\\prbs_state_r[0]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hCCB8FFFFCCB80000)) \n \\prbs_state_r[0]_i_4 \n (.I0(\\prbs_state_r[1]_i_5_n_0 ),\n .I1(Q[1]),\n .I2(p_3_in),\n .I3(Q[0]),\n .I4(Q[2]),\n .I5(\\prbs_state_r[0]_i_5_n_0 ),\n .O(\\prbs_state_r[0]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair25\" *) \n LUT5 #(\n .INIT(32'h5445FFFF)) \n \\prbs_state_r[0]_i_5 \n (.I0(Q[0]),\n .I1(prbs_dqs_tap_limit_r),\n .I2(prbs_state_r178_out),\n .I3(prbs_found_1st_edge_r_reg_0),\n .I4(Q[1]),\n .O(\\prbs_state_r[0]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair19\" *) \n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\prbs_state_r[1]_i_1 \n (.I0(\\prbs_state_r[1]_i_2_n_0 ),\n .I1(Q[4]),\n .I2(\\prbs_state_r[1]_i_3_n_0 ),\n .I3(Q[3]),\n .I4(\\prbs_state_r[1]_i_4_n_0 ),\n .O(\\prbs_state_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0047FFB80000FFB8)) \n \\prbs_state_r[1]_i_2 \n (.I0(Q[2]),\n .I1(Q[4]),\n .I2(Q[3]),\n .I3(Q[1]),\n .I4(Q[0]),\n .I5(prbs_state_r1),\n .O(\\prbs_state_r[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0F000F001F0F1F00)) \n \\prbs_state_r[1]_i_3 \n (.I0(prbs_tap_en_r_reg_0),\n .I1(fine_inc_stage_reg_n_0),\n .I2(Q[1]),\n .I3(Q[2]),\n .I4(prbs_last_byte_done_reg_0),\n .I5(Q[0]),\n .O(\\prbs_state_r[1]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair21\" *) \n LUT5 #(\n .INIT(32'h0C0C4C7C)) \n \\prbs_state_r[1]_i_4 \n (.I0(\\prbs_state_r[1]_i_5_n_0 ),\n .I1(Q[2]),\n .I2(Q[1]),\n .I3(\\prbs_state_r[1]_i_6_n_0 ),\n .I4(Q[0]),\n .O(\\prbs_state_r[1]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\prbs_state_r[1]_i_5 \n (.I0(\\prbs_inc_tap_cnt_reg_n_0_[2] ),\n .I1(\\prbs_inc_tap_cnt_reg_n_0_[0] ),\n .I2(\\prbs_inc_tap_cnt_reg_n_0_[1] ),\n .I3(\\prbs_inc_tap_cnt_reg_n_0_[4] ),\n .I4(\\prbs_inc_tap_cnt_reg_n_0_[3] ),\n .I5(\\prbs_inc_tap_cnt_reg_n_0_[5] ),\n .O(\\prbs_state_r[1]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair25\" *) \n LUT3 #(\n .INIT(8'h15)) \n \\prbs_state_r[1]_i_6 \n (.I0(prbs_dqs_tap_limit_r),\n .I1(prbs_state_r178_out),\n .I2(prbs_found_1st_edge_r_reg_0),\n .O(\\prbs_state_r[1]_i_6_n_0 ));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\prbs_state_r[2]_i_10 \n (.I0(\\genblk8[1].right_edge_pb_reg[6]_0 ),\n .I1(\\genblk8[0].right_edge_pb_reg[0]_0 ),\n .I2(\\genblk8[3].right_edge_pb_reg[18]_0 ),\n .I3(\\genblk8[2].right_edge_pb_reg[12]_0 ),\n .O(\\prbs_state_r[2]_i_10_n_0 ));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\prbs_state_r[2]_i_11 \n (.I0(\\match_flag_and_reg_n_0_[2] ),\n .I1(\\match_flag_and_reg_n_0_[3] ),\n .I2(\\match_flag_and_reg_n_0_[0] ),\n .I3(\\match_flag_and_reg_n_0_[1] ),\n .O(\\prbs_state_r[2]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'h4F00FFFF4F000000)) \n \\prbs_state_r[2]_i_2 \n (.I0(Q[0]),\n .I1(prbs_tap_en_r_reg_0),\n .I2(Q[1]),\n .I3(Q[2]),\n .I4(\\prbs_state_r[0]_i_3_n_0 ),\n .I5(\\prbs_state_r[2]_i_4_n_0 ),\n .O(\\prbs_state_r[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFE2E2E2FFE2E2)) \n \\prbs_state_r[2]_i_3 \n (.I0(Q[3]),\n .I1(Q[4]),\n .I2(Q[2]),\n .I3(prbs_state_r1),\n .I4(Q[0]),\n .I5(Q[1]),\n .O(\\prbs_state_r[2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFCFCFFFFBB880000)) \n \\prbs_state_r[2]_i_4 \n (.I0(\\prbs_state_r[1]_i_5_n_0 ),\n .I1(Q[2]),\n .I2(\\prbs_state_r[2]_i_6_n_0 ),\n .I3(\\prbs_state_r[1]_i_6_n_0 ),\n .I4(Q[1]),\n .I5(Q[0]),\n .O(\\prbs_state_r[2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hEAEAEAEAEAEAEAAA)) \n \\prbs_state_r[2]_i_5 \n (.I0(\\prbs_state_r[2]_i_7_n_0 ),\n .I1(\\prbs_state_r[2]_i_8_n_0 ),\n .I2(\\prbs_state_r[2]_i_9_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .I5(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .O(prbs_state_r1));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFD)) \n \\prbs_state_r[2]_i_6 \n (.I0(prbs_dec_tap_cnt[0]),\n .I1(prbs_dec_tap_cnt[4]),\n .I2(prbs_dec_tap_cnt[1]),\n .I3(prbs_dec_tap_cnt[5]),\n .I4(prbs_dec_tap_cnt[3]),\n .I5(prbs_dec_tap_cnt[2]),\n .O(\\prbs_state_r[2]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hBAAAAAAAAAAAAAAA)) \n \\prbs_state_r[2]_i_7 \n (.I0(prbs_dqs_tap_limit_r),\n .I1(\\prbs_state_r[2]_i_10_n_0 ),\n .I2(\\genblk8[5].right_edge_pb_reg[30]_0 ),\n .I3(\\genblk8[4].right_edge_pb_reg[24]_0 ),\n .I4(\\genblk8[6].right_edge_pb_reg[36]_0 ),\n .I5(\\genblk8[7].right_edge_pb_reg[42]_0 ),\n .O(\\prbs_state_r[2]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair20\" *) \n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n \\prbs_state_r[2]_i_8 \n (.I0(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I1(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\prbs_state_r[2]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\prbs_state_r[2]_i_9 \n (.I0(compare_err_pb_and_reg_n_0),\n .I1(\\prbs_state_r[2]_i_11_n_0 ),\n .I2(\\match_flag_and_reg_n_0_[6] ),\n .I3(\\match_flag_and_reg_n_0_[7] ),\n .I4(\\match_flag_and_reg_n_0_[4] ),\n .I5(\\match_flag_and_reg_n_0_[5] ),\n .O(\\prbs_state_r[2]_i_9_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair30\" *) \n LUT5 #(\n .INIT(32'hE4A5E4A0)) \n \\prbs_state_r[3]_i_1 \n (.I0(Q[4]),\n .I1(\\prbs_state_r[3]_i_2_n_0 ),\n .I2(Q[2]),\n .I3(Q[3]),\n .I4(\\prbs_state_r[3]_i_3_n_0 ),\n .O(\\prbs_state_r[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair40\" *) \n LUT5 #(\n .INIT(32'h0FF0B0FF)) \n \\prbs_state_r[3]_i_2 \n (.I0(prbs_tap_en_r_reg_0),\n .I1(fine_inc_stage_reg_n_0),\n .I2(Q[1]),\n .I3(Q[2]),\n .I4(Q[0]),\n .O(\\prbs_state_r[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAFFFFFFC00000)) \n \\prbs_state_r[3]_i_3 \n (.I0(\\prbs_state_r[3]_i_4_n_0 ),\n .I1(prbs_found_1st_edge_r_reg_0),\n .I2(prbs_state_r178_out),\n .I3(prbs_dqs_tap_limit_r),\n .I4(Q[1]),\n .I5(Q[0]),\n .O(\\prbs_state_r[3]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000100)) \n \\prbs_state_r[3]_i_4 \n (.I0(prbs_dec_tap_cnt[5]),\n .I1(prbs_dec_tap_cnt[4]),\n .I2(prbs_dec_tap_cnt[1]),\n .I3(prbs_dec_tap_cnt[0]),\n .I4(prbs_dec_tap_cnt[3]),\n .I5(prbs_dec_tap_cnt[2]),\n .O(\\prbs_state_r[3]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h00000001)) \n \\prbs_state_r[4]_i_11 \n (.I0(bit_cnt_reg__0[5]),\n .I1(bit_cnt_reg__0[4]),\n .I2(bit_cnt_reg__0[6]),\n .I3(bit_cnt_reg__0[7]),\n .I4(fine_delay_sel_i_4_n_0),\n .O(\\prbs_state_r[4]_i_11_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\prbs_state_r[4]_i_2 \n (.I0(\\prbs_state_r[4]_i_4_n_0 ),\n .I1(Q[4]),\n .I2(\\prbs_state_r[4]_i_5_n_0 ),\n .I3(Q[3]),\n .I4(\\prbs_state_r[4]_i_6_n_0 ),\n .O(\\prbs_state_r[4]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair29\" *) \n LUT5 #(\n .INIT(32'h4E5F4E0A)) \n \\prbs_state_r[4]_i_3 \n (.I0(Q[4]),\n .I1(\\prbs_state_r[4]_i_7_n_0 ),\n .I2(Q[2]),\n .I3(Q[3]),\n .I4(\\prbs_state_r[4]_i_8_n_0 ),\n .O(\\prbs_state_r[4]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0A3A3A3A0A0A0A0A)) \n \\prbs_state_r[4]_i_4 \n (.I0(\\prbs_state_r[4]_i_9_n_0 ),\n .I1(Q[1]),\n .I2(Q[2]),\n .I3(prbs_rdlvl_done_reg_0),\n .I4(Q[0]),\n .I5(complex_act_start),\n .O(\\prbs_state_r[4]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair26\" *) \n LUT5 #(\n .INIT(32'hFFF2FC32)) \n \\prbs_state_r[4]_i_5 \n (.I0(prech_done),\n .I1(Q[1]),\n .I2(Q[2]),\n .I3(Q[0]),\n .I4(cnt_wait_state),\n .O(\\prbs_state_r[4]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFFAEF45FFFAEA40)) \n \\prbs_state_r[4]_i_6 \n (.I0(Q[2]),\n .I1(num_samples_done_r),\n .I2(Q[1]),\n .I3(cnt_wait_state),\n .I4(Q[0]),\n .I5(prbs_rdlvl_start_reg_0),\n .O(\\prbs_state_r[4]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair40\" *) \n LUT5 #(\n .INIT(32'hAA080000)) \n \\prbs_state_r[4]_i_7 \n (.I0(Q[1]),\n .I1(fine_inc_stage_reg_n_0),\n .I2(prbs_tap_en_r_reg_0),\n .I3(Q[0]),\n .I4(Q[2]),\n .O(\\prbs_state_r[4]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h8080808480848084)) \n \\prbs_state_r[4]_i_8 \n (.I0(Q[2]),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(prbs_dqs_tap_limit_r),\n .I4(prbs_state_r178_out),\n .I5(prbs_found_1st_edge_r_reg_0),\n .O(\\prbs_state_r[4]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0FFCFAFA0F0C0)) \n \\prbs_state_r[4]_i_9 \n (.I0(\\prbs_state_r[4]_i_11_n_0 ),\n .I1(\\match_flag_or_reg[0]_0 ),\n .I2(Q[1]),\n .I3(num_samples_done_r),\n .I4(Q[0]),\n .I5(cnt_wait_state),\n .O(\\prbs_state_r[4]_i_9_n_0 ));\n FDRE \\prbs_state_r_reg[0] \n (.C(CLK),\n .CE(\\prbs_state_r[4]_i_2_n_0 ),\n .D(\\prbs_state_r[0]_i_1_n_0 ),\n .Q(Q[0]),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE \\prbs_state_r_reg[1] \n (.C(CLK),\n .CE(\\prbs_state_r[4]_i_2_n_0 ),\n .D(\\prbs_state_r[1]_i_1_n_0 ),\n .Q(Q[1]),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE \\prbs_state_r_reg[2] \n (.C(CLK),\n .CE(\\prbs_state_r[4]_i_2_n_0 ),\n .D(\\prbs_state_r_reg[2]_i_1_n_0 ),\n .Q(Q[2]),\n .R(rstdiv0_sync_r1_reg_rep__8));\n MUXF7 \\prbs_state_r_reg[2]_i_1 \n (.I0(\\prbs_state_r[2]_i_2_n_0 ),\n .I1(\\prbs_state_r[2]_i_3_n_0 ),\n .O(\\prbs_state_r_reg[2]_i_1_n_0 ),\n .S(Q[4]));\n FDRE \\prbs_state_r_reg[3] \n (.C(CLK),\n .CE(\\prbs_state_r[4]_i_2_n_0 ),\n .D(\\prbs_state_r[3]_i_1_n_0 ),\n .Q(Q[3]),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE \\prbs_state_r_reg[4] \n (.C(CLK),\n .CE(\\prbs_state_r[4]_i_2_n_0 ),\n .D(\\prbs_state_r[4]_i_3_n_0 ),\n .Q(Q[4]),\n .R(rstdiv0_sync_r1_reg_rep__8));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n prbs_tap_en_r_i_2\n (.I0(\\fine_pi_dec_cnt_reg_n_0_[2] ),\n .I1(\\fine_pi_dec_cnt_reg_n_0_[0] ),\n .I2(\\fine_pi_dec_cnt_reg_n_0_[1] ),\n .I3(\\fine_pi_dec_cnt_reg_n_0_[4] ),\n .I4(\\fine_pi_dec_cnt_reg_n_0_[3] ),\n .I5(\\fine_pi_dec_cnt_reg_n_0_[5] ),\n .O(prbs_tap_en_r_reg_0));\n FDRE prbs_tap_en_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\prbs_state_r_reg[0]_2 ),\n .Q(pi_en_stg2_f_timing_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__8));\n LUT6 #(\n .INIT(64'h888888B8888B8B88)) \n prbs_tap_inc_r_i_2\n (.I0(prbs_tap_inc_r_i_3_n_0),\n .I1(Q[2]),\n .I2(Q[0]),\n .I3(Q[4]),\n .I4(Q[3]),\n .I5(Q[1]),\n .O(prbs_tap_en_r));\n LUT6 #(\n .INIT(64'h1454051504440515)) \n prbs_tap_inc_r_i_3\n (.I0(Q[4]),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(prbs_dqs_tap_limit_r),\n .I4(Q[3]),\n .I5(prbs_tap_en_r_reg_0),\n .O(prbs_tap_inc_r_i_3_n_0));\n FDRE prbs_tap_inc_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\prbs_state_r_reg[0]_1 ),\n .Q(prbs_tap_inc_r),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE rd_valid_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mux_rd_valid_r),\n .Q(rd_valid_r1),\n .R(1'b0));\n FDRE rd_valid_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rd_valid_r1),\n .Q(rd_valid_r2_reg_n_0),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h000000000000E5A5)) \n \\rd_victim_sel[0]_i_1 \n (.I0(\\rd_victim_sel_reg[2]_0 ),\n .I1(\\rd_victim_sel_reg[2]_1 ),\n .I2(\\rd_victim_sel_reg[2]_2 ),\n .I3(\\rd_victim_sel_reg[2]_3 ),\n .I4(num_samples_done_r),\n .I5(rstdiv0_sync_r1_reg_rep__23),\n .O(\\rd_victim_sel[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h000000000000DC9C)) \n \\rd_victim_sel[1]_i_1 \n (.I0(\\rd_victim_sel_reg[2]_0 ),\n .I1(\\rd_victim_sel_reg[2]_1 ),\n .I2(\\rd_victim_sel_reg[2]_2 ),\n .I3(\\rd_victim_sel_reg[2]_3 ),\n .I4(num_samples_done_r),\n .I5(rstdiv0_sync_r1_reg_rep__23),\n .O(\\rd_victim_sel[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h000000000000FF40)) \n \\rd_victim_sel[2]_i_1 \n (.I0(\\rd_victim_sel_reg[2]_0 ),\n .I1(\\rd_victim_sel_reg[2]_1 ),\n .I2(\\rd_victim_sel_reg[2]_2 ),\n .I3(\\rd_victim_sel_reg[2]_3 ),\n .I4(num_samples_done_r),\n .I5(rstdiv0_sync_r1_reg_rep__24),\n .O(\\rd_victim_sel[2]_i_1_n_0 ));\n FDRE \\rd_victim_sel_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_victim_sel[0]_i_1_n_0 ),\n .Q(\\rd_victim_sel_reg[2]_2 ),\n .R(1'b0));\n FDRE \\rd_victim_sel_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_victim_sel[1]_i_1_n_0 ),\n .Q(\\rd_victim_sel_reg[2]_1 ),\n .R(1'b0));\n FDRE \\rd_victim_sel_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_victim_sel[2]_i_1_n_0 ),\n .Q(\\rd_victim_sel_reg[2]_3 ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair69\" *) \n LUT2 #(\n .INIT(4'h4)) \n \\rdlvl_cpt_tap_cnt[0]_i_1 \n (.I0(\\calib_sel_reg[3] ),\n .I1(\\pi_counter_read_val_reg[5] [0]),\n .O(\\rdlvl_cpt_tap_cnt_reg[5]_1 [0]));\n LUT2 #(\n .INIT(4'h4)) \n \\rdlvl_cpt_tap_cnt[3]_i_1 \n (.I0(\\calib_sel_reg[3] ),\n .I1(\\pi_counter_read_val_reg[5] [2]),\n .O(\\rdlvl_cpt_tap_cnt_reg[5]_1 [1]));\n LUT2 #(\n .INIT(4'h4)) \n \\rdlvl_cpt_tap_cnt[5]_i_1 \n (.I0(\\calib_sel_reg[3] ),\n .I1(\\pi_counter_read_val_reg[5] [3]),\n .O(\\rdlvl_cpt_tap_cnt_reg[5]_1 [2]));\n FDRE \\rdlvl_cpt_tap_cnt_reg[0] \n (.C(CLK),\n .CE(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .D(\\rdlvl_cpt_tap_cnt_reg[5]_1 [0]),\n .Q(rdlvl_cpt_tap_cnt[0]),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE \\rdlvl_cpt_tap_cnt_reg[1] \n (.C(CLK),\n .CE(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .D(\\calib_sel_reg[3]_0 ),\n .Q(rdlvl_cpt_tap_cnt[1]),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE \\rdlvl_cpt_tap_cnt_reg[2] \n (.C(CLK),\n .CE(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .D(\\calib_sel_reg[3]_1 ),\n .Q(rdlvl_cpt_tap_cnt[2]),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE \\rdlvl_cpt_tap_cnt_reg[3] \n (.C(CLK),\n .CE(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .D(\\rdlvl_cpt_tap_cnt_reg[5]_1 [1]),\n .Q(rdlvl_cpt_tap_cnt[3]),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE \\rdlvl_cpt_tap_cnt_reg[4] \n (.C(CLK),\n .CE(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .D(\\calib_sel_reg[3]_2 ),\n .Q(rdlvl_cpt_tap_cnt[4]),\n .R(rstdiv0_sync_r1_reg_rep__9));\n FDRE \\rdlvl_cpt_tap_cnt_reg[5] \n (.C(CLK),\n .CE(\\rdlvl_cpt_tap_cnt_reg[5]_0 ),\n .D(\\rdlvl_cpt_tap_cnt_reg[5]_1 [2]),\n .Q(rdlvl_cpt_tap_cnt[5]),\n .R(rstdiv0_sync_r1_reg_rep__9));\n LUT5 #(\n .INIT(32'h80880080)) \n \\ref_bit[7]_i_1 \n (.I0(bit_cnt0),\n .I1(ref_right_edge125_in),\n .I2(\\ref_bit[7]_i_3_n_0 ),\n .I3(\\ref_right_edge[5]_i_1_n_0 ),\n .I4(\\ref_right_edge_reg_n_0_[5] ),\n .O(ref_right_edge));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\ref_bit[7]_i_3 \n (.I0(\\ref_bit[7]_i_6_n_0 ),\n .I1(\\ref_right_edge[3]_i_1_n_0 ),\n .I2(\\ref_right_edge_reg_n_0_[3] ),\n .I3(\\ref_right_edge[4]_i_1_n_0 ),\n .I4(\\ref_right_edge_reg_n_0_[4] ),\n .O(\\ref_bit[7]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\ref_bit[7]_i_4 \n (.I0(\\ref_bit_per_bit_reg_n_0_[3] ),\n .I1(\\ref_bit_per_bit_reg_n_0_[2] ),\n .I2(bit_cnt_reg__0[1]),\n .I3(\\ref_bit_per_bit_reg_n_0_[1] ),\n .I4(bit_cnt_reg__0[0]),\n .I5(\\ref_bit_per_bit_reg_n_0_[0] ),\n .O(\\ref_bit[7]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\ref_bit[7]_i_5 \n (.I0(\\ref_bit_per_bit_reg_n_0_[7] ),\n .I1(\\ref_bit_per_bit_reg_n_0_[6] ),\n .I2(bit_cnt_reg__0[1]),\n .I3(\\ref_bit_per_bit_reg_n_0_[5] ),\n .I4(bit_cnt_reg__0[0]),\n .I5(\\ref_bit_per_bit_reg_n_0_[4] ),\n .O(\\ref_bit[7]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hDF0DFFFF0000DF0D)) \n \\ref_bit[7]_i_6 \n (.I0(\\ref_right_edge[0]_i_1_n_0 ),\n .I1(\\ref_right_edge_reg_n_0_[0] ),\n .I2(\\ref_right_edge[1]_i_1_n_0 ),\n .I3(\\ref_right_edge_reg_n_0_[1] ),\n .I4(\\ref_right_edge[2]_i_1_n_0 ),\n .I5(\\ref_right_edge_reg_n_0_[2] ),\n .O(\\ref_bit[7]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000200000)) \n \\ref_bit_per_bit[7]_i_1 \n (.I0(ref_bit_per_bit0),\n .I1(\\ref_bit_per_bit[7]_i_2_n_0 ),\n .I2(Q[0]),\n .I3(\\ref_bit_per_bit[7]_i_3_n_0 ),\n .I4(Q[1]),\n .I5(Q[4]),\n .O(ref_bit_per_bit));\n (* SOFT_HLUTNM = \"soft_lutpair75\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\ref_bit_per_bit[7]_i_2 \n (.I0(\\stage_cnt_reg_n_0_[0] ),\n .I1(\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ),\n .O(\\ref_bit_per_bit[7]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair49\" *) \n LUT2 #(\n .INIT(4'h7)) \n \\ref_bit_per_bit[7]_i_3 \n (.I0(Q[2]),\n .I1(Q[3]),\n .O(\\ref_bit_per_bit[7]_i_3_n_0 ));\n FDRE \\ref_bit_per_bit_reg[0] \n (.C(CLK),\n .CE(ref_bit_per_bit),\n .D(D[0]),\n .Q(\\ref_bit_per_bit_reg_n_0_[0] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\ref_bit_per_bit_reg[1] \n (.C(CLK),\n .CE(ref_bit_per_bit),\n .D(D[1]),\n .Q(\\ref_bit_per_bit_reg_n_0_[1] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\ref_bit_per_bit_reg[2] \n (.C(CLK),\n .CE(ref_bit_per_bit),\n .D(D[2]),\n .Q(\\ref_bit_per_bit_reg_n_0_[2] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\ref_bit_per_bit_reg[3] \n (.C(CLK),\n .CE(ref_bit_per_bit),\n .D(D[3]),\n .Q(\\ref_bit_per_bit_reg_n_0_[3] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\ref_bit_per_bit_reg[4] \n (.C(CLK),\n .CE(ref_bit_per_bit),\n .D(D[4]),\n .Q(\\ref_bit_per_bit_reg_n_0_[4] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\ref_bit_per_bit_reg[5] \n (.C(CLK),\n .CE(ref_bit_per_bit),\n .D(D[5]),\n .Q(\\ref_bit_per_bit_reg_n_0_[5] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\ref_bit_per_bit_reg[6] \n (.C(CLK),\n .CE(ref_bit_per_bit),\n .D(D[6]),\n .Q(\\ref_bit_per_bit_reg_n_0_[6] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\ref_bit_per_bit_reg[7] \n (.C(CLK),\n .CE(ref_bit_per_bit),\n .D(D[7]),\n .Q(\\ref_bit_per_bit_reg_n_0_[7] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\ref_bit_reg[0] \n (.C(CLK),\n .CE(ref_right_edge),\n .D(bit_cnt_reg__0[0]),\n .Q(\\ref_bit_reg_n_0_[0] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\ref_bit_reg[1] \n (.C(CLK),\n .CE(ref_right_edge),\n .D(bit_cnt_reg__0[1]),\n .Q(\\ref_bit_reg_n_0_[1] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\ref_bit_reg[2] \n (.C(CLK),\n .CE(ref_right_edge),\n .D(bit_cnt_reg__0[2]),\n .Q(\\ref_bit_reg_n_0_[2] ),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\ref_bit_reg[3] \n (.C(CLK),\n .CE(ref_right_edge),\n .D(bit_cnt_reg__0[3]),\n .Q(ref_bit[3]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\ref_bit_reg[4] \n (.C(CLK),\n .CE(ref_right_edge),\n .D(bit_cnt_reg__0[4]),\n .Q(ref_bit[4]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\ref_bit_reg[5] \n (.C(CLK),\n .CE(ref_right_edge),\n .D(bit_cnt_reg__0[5]),\n .Q(ref_bit[5]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\ref_bit_reg[6] \n (.C(CLK),\n .CE(ref_right_edge),\n .D(bit_cnt_reg__0[6]),\n .Q(ref_bit[6]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDRE \\ref_bit_reg[7] \n (.C(CLK),\n .CE(ref_right_edge),\n .D(bit_cnt_reg__0[7]),\n .Q(ref_bit[7]),\n .R(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n MUXF7 \\ref_bit_reg[7]_i_2 \n (.I0(\\ref_bit[7]_i_4_n_0 ),\n .I1(\\ref_bit[7]_i_5_n_0 ),\n .O(ref_right_edge125_in),\n .S(bit_cnt_reg__0[2]));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\ref_right_edge[0]_i_1 \n (.I0(\\ref_right_edge[2]_i_2_n_0 ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_7 ),\n .I2(\\ref_right_edge_reg[0]_i_2_n_0 ),\n .I3(\\ref_right_edge_reg[5]_i_3_n_6 ),\n .I4(\\ref_right_edge[0]_i_3_n_0 ),\n .O(\\ref_right_edge[0]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hB8)) \n \\ref_right_edge[0]_i_3 \n (.I0(\\ref_right_edge[4]_i_9_n_0 ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_5 ),\n .I2(\\ref_right_edge[0]_i_4_n_0 ),\n .O(\\ref_right_edge[0]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\ref_right_edge[0]_i_4 \n (.I0(\\genblk8[2].right_edge_pb_reg_n_0_[16] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[32] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].right_edge_pb_reg_n_0_[0] ),\n .O(\\ref_right_edge[0]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\ref_right_edge[1]_i_1 \n (.I0(\\ref_right_edge[3]_i_2_n_0 ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_7 ),\n .I2(\\ref_right_edge_reg[1]_i_2_n_0 ),\n .I3(\\ref_right_edge_reg[5]_i_3_n_6 ),\n .I4(\\ref_right_edge[1]_i_3_n_0 ),\n .O(\\ref_right_edge[1]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hB8)) \n \\ref_right_edge[1]_i_3 \n (.I0(\\ref_right_edge[5]_i_15_n_0 ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_5 ),\n .I2(\\ref_right_edge[1]_i_6_n_0 ),\n .O(\\ref_right_edge[1]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\ref_right_edge[1]_i_4 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[21] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].right_edge_pb_reg_n_0_[37] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].right_edge_pb_reg_n_0_[5] ),\n .O(\\ref_right_edge[1]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\ref_right_edge[1]_i_5 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[29] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].right_edge_pb_reg_n_0_[45] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[2].right_edge_pb_reg_n_0_[13] ),\n .O(\\ref_right_edge[1]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\ref_right_edge[1]_i_6 \n (.I0(\\genblk8[2].right_edge_pb_reg_n_0_[17] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[33] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].right_edge_pb_reg_n_0_[1] ),\n .O(\\ref_right_edge[1]_i_6_n_0 ));\n LUT3 #(\n .INIT(8'hB8)) \n \\ref_right_edge[2]_i_1 \n (.I0(\\ref_right_edge[4]_i_4_n_0 ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_7 ),\n .I2(\\ref_right_edge[2]_i_2_n_0 ),\n .O(\\ref_right_edge[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\ref_right_edge[2]_i_2 \n (.I0(\\ref_right_edge[4]_i_7_n_0 ),\n .I1(\\ref_right_edge[4]_i_6_n_0 ),\n .I2(\\ref_right_edge_reg[5]_i_3_n_6 ),\n .I3(\\ref_right_edge[4]_i_5_n_0 ),\n .I4(\\ref_right_edge_reg[5]_i_3_n_5 ),\n .I5(\\ref_right_edge[2]_i_3_n_0 ),\n .O(\\ref_right_edge[2]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\ref_right_edge[2]_i_3 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[18] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[34] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].right_edge_pb_reg_n_0_[2] ),\n .O(\\ref_right_edge[2]_i_3_n_0 ));\n LUT3 #(\n .INIT(8'hB8)) \n \\ref_right_edge[3]_i_1 \n (.I0(\\ref_right_edge[5]_i_5_n_0 ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_7 ),\n .I2(\\ref_right_edge[3]_i_2_n_0 ),\n .O(\\ref_right_edge[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\ref_right_edge[3]_i_2 \n (.I0(\\ref_right_edge[5]_i_13_n_0 ),\n .I1(\\ref_right_edge[5]_i_12_n_0 ),\n .I2(\\ref_right_edge_reg[5]_i_3_n_6 ),\n .I3(\\ref_right_edge[5]_i_7_n_0 ),\n .I4(\\ref_right_edge_reg[5]_i_3_n_5 ),\n .I5(\\ref_right_edge[3]_i_3_n_0 ),\n .O(\\ref_right_edge[3]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\ref_right_edge[3]_i_3 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[19] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[35] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].right_edge_pb_reg_n_0_[3] ),\n .O(\\ref_right_edge[3]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\ref_right_edge[4]_i_1 \n (.I0(\\ref_right_edge[4]_i_2_n_0 ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_6 ),\n .I2(\\ref_right_edge_reg[4]_i_3_n_0 ),\n .I3(\\ref_right_edge_reg[5]_i_3_n_7 ),\n .I4(\\ref_right_edge[4]_i_4_n_0 ),\n .O(\\ref_right_edge[4]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\ref_right_edge[4]_i_10 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[28] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].right_edge_pb_reg_n_0_[44] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[2].right_edge_pb_reg_n_0_[12] ),\n .O(\\ref_right_edge[4]_i_10_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\ref_right_edge[4]_i_11 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[20] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].right_edge_pb_reg_n_0_[36] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].right_edge_pb_reg_n_0_[4] ),\n .O(\\ref_right_edge[4]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'h00E2FFFF00E20000)) \n \\ref_right_edge[4]_i_2 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[18] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[34] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\ref_right_edge_reg[5]_i_3_n_5 ),\n .I5(\\ref_right_edge[4]_i_5_n_0 ),\n .O(\\ref_right_edge[4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\ref_right_edge[4]_i_4 \n (.I0(\\ref_right_edge[4]_i_8_n_0 ),\n .I1(\\ref_right_edge[4]_i_9_n_0 ),\n .I2(\\ref_right_edge_reg[5]_i_3_n_6 ),\n .I3(\\ref_right_edge[4]_i_10_n_0 ),\n .I4(\\ref_right_edge_reg[5]_i_3_n_5 ),\n .I5(\\ref_right_edge[4]_i_11_n_0 ),\n .O(\\ref_right_edge[4]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\ref_right_edge[4]_i_5 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[26] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].right_edge_pb_reg_n_0_[42] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].right_edge_pb_reg_n_0_[10] ),\n .O(\\ref_right_edge[4]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\ref_right_edge[4]_i_6 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[22] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].right_edge_pb_reg_n_0_[38] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].right_edge_pb_reg_n_0_[6] ),\n .O(\\ref_right_edge[4]_i_6_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\ref_right_edge[4]_i_7 \n (.I0(\\genblk8[5].right_edge_pb_reg_n_0_[30] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].right_edge_pb_reg_n_0_[46] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[2].right_edge_pb_reg_n_0_[14] ),\n .O(\\ref_right_edge[4]_i_7_n_0 ));\n LUT4 #(\n .INIT(16'h00E2)) \n \\ref_right_edge[4]_i_8 \n (.I0(\\genblk8[2].right_edge_pb_reg_n_0_[16] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[32] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .O(\\ref_right_edge[4]_i_8_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\ref_right_edge[4]_i_9 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[24] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].right_edge_pb_reg_n_0_[40] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].right_edge_pb_reg_n_0_[8] ),\n .O(\\ref_right_edge[4]_i_9_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\ref_right_edge[5]_i_1 \n (.I0(\\ref_right_edge[5]_i_2_n_0 ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_6 ),\n .I2(\\ref_right_edge_reg[5]_i_4_n_0 ),\n .I3(\\ref_right_edge_reg[5]_i_3_n_7 ),\n .I4(\\ref_right_edge[5]_i_5_n_0 ),\n .O(\\ref_right_edge[5]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\ref_right_edge[5]_i_10 \n (.I0(bit_cnt_reg__0[1]),\n .O(\\ref_right_edge[5]_i_10_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\ref_right_edge[5]_i_11 \n (.I0(bit_cnt_reg__0[0]),\n .O(\\ref_right_edge[5]_i_11_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\ref_right_edge[5]_i_12 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[23] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].right_edge_pb_reg_n_0_[39] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].right_edge_pb_reg_n_0_[7] ),\n .O(\\ref_right_edge[5]_i_12_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\ref_right_edge[5]_i_13 \n (.I0(\\genblk8[5].right_edge_pb_reg_n_0_[31] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].right_edge_pb_reg_n_0_[47] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[2].right_edge_pb_reg_n_0_[15] ),\n .O(\\ref_right_edge[5]_i_13_n_0 ));\n LUT4 #(\n .INIT(16'h00E2)) \n \\ref_right_edge[5]_i_14 \n (.I0(\\genblk8[2].right_edge_pb_reg_n_0_[17] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[33] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .O(\\ref_right_edge[5]_i_14_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\ref_right_edge[5]_i_15 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[25] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].right_edge_pb_reg_n_0_[41] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].right_edge_pb_reg_n_0_[9] ),\n .O(\\ref_right_edge[5]_i_15_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\ref_right_edge[5]_i_16 \n (.I0(bit_cnt_reg__0[2]),\n .I1(bit_cnt_reg__0[4]),\n .O(\\ref_right_edge[5]_i_16_n_0 ));\n LUT6 #(\n .INIT(64'h00E2FFFF00E20000)) \n \\ref_right_edge[5]_i_2 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[19] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[35] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\ref_right_edge_reg[5]_i_3_n_5 ),\n .I5(\\ref_right_edge[5]_i_7_n_0 ),\n .O(\\ref_right_edge[5]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\ref_right_edge[5]_i_5 \n (.I0(\\ref_right_edge[5]_i_14_n_0 ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_5 ),\n .I2(\\ref_right_edge[5]_i_15_n_0 ),\n .I3(\\ref_right_edge_reg[5]_i_3_n_6 ),\n .I4(\\ref_right_edge_reg[1]_i_2_n_0 ),\n .O(\\ref_right_edge[5]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\ref_right_edge[5]_i_7 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[27] ),\n .I1(\\ref_right_edge_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].right_edge_pb_reg_n_0_[43] ),\n .I3(\\ref_right_edge_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].right_edge_pb_reg_n_0_[11] ),\n .O(\\ref_right_edge[5]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\ref_right_edge[5]_i_8 \n (.I0(bit_cnt_reg__0[1]),\n .I1(bit_cnt_reg__0[3]),\n .O(\\ref_right_edge[5]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\ref_right_edge[5]_i_9 \n (.I0(bit_cnt_reg__0[0]),\n .I1(bit_cnt_reg__0[2]),\n .O(\\ref_right_edge[5]_i_9_n_0 ));\n FDSE \\ref_right_edge_reg[0] \n (.C(CLK),\n .CE(ref_right_edge),\n .D(\\ref_right_edge[0]_i_1_n_0 ),\n .Q(\\ref_right_edge_reg_n_0_[0] ),\n .S(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n MUXF7 \\ref_right_edge_reg[0]_i_2 \n (.I0(\\ref_right_edge[4]_i_11_n_0 ),\n .I1(\\ref_right_edge[4]_i_10_n_0 ),\n .O(\\ref_right_edge_reg[0]_i_2_n_0 ),\n .S(\\ref_right_edge_reg[5]_i_3_n_5 ));\n FDSE \\ref_right_edge_reg[1] \n (.C(CLK),\n .CE(ref_right_edge),\n .D(\\ref_right_edge[1]_i_1_n_0 ),\n .Q(\\ref_right_edge_reg_n_0_[1] ),\n .S(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n MUXF7 \\ref_right_edge_reg[1]_i_2 \n (.I0(\\ref_right_edge[1]_i_4_n_0 ),\n .I1(\\ref_right_edge[1]_i_5_n_0 ),\n .O(\\ref_right_edge_reg[1]_i_2_n_0 ),\n .S(\\ref_right_edge_reg[5]_i_3_n_5 ));\n FDSE \\ref_right_edge_reg[2] \n (.C(CLK),\n .CE(ref_right_edge),\n .D(\\ref_right_edge[2]_i_1_n_0 ),\n .Q(\\ref_right_edge_reg_n_0_[2] ),\n .S(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDSE \\ref_right_edge_reg[3] \n (.C(CLK),\n .CE(ref_right_edge),\n .D(\\ref_right_edge[3]_i_1_n_0 ),\n .Q(\\ref_right_edge_reg_n_0_[3] ),\n .S(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n FDSE \\ref_right_edge_reg[4] \n (.C(CLK),\n .CE(ref_right_edge),\n .D(\\ref_right_edge[4]_i_1_n_0 ),\n .Q(\\ref_right_edge_reg_n_0_[4] ),\n .S(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n MUXF7 \\ref_right_edge_reg[4]_i_3 \n (.I0(\\ref_right_edge[4]_i_6_n_0 ),\n .I1(\\ref_right_edge[4]_i_7_n_0 ),\n .O(\\ref_right_edge_reg[4]_i_3_n_0 ),\n .S(\\ref_right_edge_reg[5]_i_3_n_5 ));\n FDSE \\ref_right_edge_reg[5] \n (.C(CLK),\n .CE(ref_right_edge),\n .D(\\ref_right_edge[5]_i_1_n_0 ),\n .Q(\\ref_right_edge_reg_n_0_[5] ),\n .S(\\genblk8[0].left_edge_pb[5]_i_1_n_0 ));\n CARRY4 \\ref_right_edge_reg[5]_i_3 \n (.CI(1'b0),\n .CO({\\ref_right_edge_reg[5]_i_3_n_0 ,\\ref_right_edge_reg[5]_i_3_n_1 ,\\ref_right_edge_reg[5]_i_3_n_2 ,\\ref_right_edge_reg[5]_i_3_n_3 }),\n .CYINIT(1'b0),\n .DI({bit_cnt_reg__0[1:0],1'b0,1'b1}),\n .O({\\ref_right_edge_reg[5]_i_3_n_4 ,\\ref_right_edge_reg[5]_i_3_n_5 ,\\ref_right_edge_reg[5]_i_3_n_6 ,\\ref_right_edge_reg[5]_i_3_n_7 }),\n .S({\\ref_right_edge[5]_i_8_n_0 ,\\ref_right_edge[5]_i_9_n_0 ,\\ref_right_edge[5]_i_10_n_0 ,\\ref_right_edge[5]_i_11_n_0 }));\n MUXF7 \\ref_right_edge_reg[5]_i_4 \n (.I0(\\ref_right_edge[5]_i_12_n_0 ),\n .I1(\\ref_right_edge[5]_i_13_n_0 ),\n .O(\\ref_right_edge_reg[5]_i_4_n_0 ),\n .S(\\ref_right_edge_reg[5]_i_3_n_5 ));\n CARRY4 \\ref_right_edge_reg[5]_i_6 \n (.CI(\\ref_right_edge_reg[5]_i_3_n_0 ),\n .CO(\\NLW_ref_right_edge_reg[5]_i_6_CO_UNCONNECTED [3:0]),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\NLW_ref_right_edge_reg[5]_i_6_O_UNCONNECTED [3:1],\\ref_right_edge_reg[5]_i_6_n_7 }),\n .S({1'b0,1'b0,1'b0,\\ref_right_edge[5]_i_16_n_0 }));\n LUT2 #(\n .INIT(4'hE)) \n reset_rd_addr_r1_i_1\n (.I0(reset_rd_addr),\n .I1(complex_ocal_reset_rd_addr),\n .O(reset_rd_addr0));\n FDRE reset_rd_addr_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\prbs_state_r_reg[4]_2 ),\n .Q(reset_rd_addr),\n .R(rstdiv0_sync_r1_reg_rep__9));\n LUT6 #(\n .INIT(64'h00000000FFFFFFFD)) \n right_edge_found_i_2\n (.I0(right_edge_found_i_4_n_0),\n .I1(\\genblk8[3].right_edge_pb_reg[18]_0 ),\n .I2(\\genblk8[2].right_edge_pb_reg[12]_0 ),\n .I3(\\genblk8[1].right_edge_pb_reg[6]_0 ),\n .I4(\\genblk8[0].right_edge_pb_reg[0]_0 ),\n .I5(right_edge_found_reg_0),\n .O(right_edge_found_reg_1));\n (* SOFT_HLUTNM = \"soft_lutpair43\" *) \n LUT5 #(\n .INIT(32'h80000008)) \n right_edge_found_i_3\n (.I0(Q[1]),\n .I1(right_edge_found_i_5_n_0),\n .I2(Q[0]),\n .I3(Q[3]),\n .I4(Q[2]),\n .O(right_edge_found));\n LUT4 #(\n .INIT(16'h0001)) \n right_edge_found_i_4\n (.I0(\\genblk8[6].right_edge_pb_reg[36]_0 ),\n .I1(\\genblk8[7].right_edge_pb_reg[42]_0 ),\n .I2(\\genblk8[5].right_edge_pb_reg[30]_0 ),\n .I3(\\genblk8[4].right_edge_pb_reg[24]_0 ),\n .O(right_edge_found_i_4_n_0));\n LUT6 #(\n .INIT(64'h0FE00FE00FE000E0)) \n right_edge_found_i_5\n (.I0(right_edge_found_reg_1),\n .I1(no_err_win_detected_latch_reg_0),\n .I2(Q[3]),\n .I3(Q[4]),\n .I4(num_samples_done_r),\n .I5(\\match_flag_or_reg[0]_0 ),\n .O(right_edge_found_i_5_n_0));\n FDRE right_edge_found_reg\n (.C(CLK),\n .CE(1'b1),\n .D(no_err_win_detected_reg_1),\n .Q(right_edge_found_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__7));\n LUT3 #(\n .INIT(8'hB8)) \n \\right_edge_ref[0]_i_1 \n (.I0(\\right_edge_ref[2]_i_2_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_7 ),\n .I2(\\right_edge_ref[0]_i_2_n_0 ),\n .O(\\right_edge_ref[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\right_edge_ref[0]_i_2 \n (.I0(\\right_edge_ref_reg[4]_i_10_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_6 ),\n .I2(\\right_edge_ref[4]_i_9_n_0 ),\n .I3(\\left_edge_ref_reg[5]_i_3_n_5 ),\n .I4(\\right_edge_ref[0]_i_3_n_0 ),\n .O(\\right_edge_ref[0]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair24\" *) \n LUT5 #(\n .INIT(32'h30BB3088)) \n \\right_edge_ref[0]_i_3 \n (.I0(\\genblk8[2].right_edge_pb_reg_n_0_[16] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[32] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].right_edge_pb_reg_n_0_[0] ),\n .O(\\right_edge_ref[0]_i_3_n_0 ));\n LUT3 #(\n .INIT(8'hB8)) \n \\right_edge_ref[1]_i_1 \n (.I0(\\right_edge_ref[3]_i_2_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_7 ),\n .I2(\\right_edge_ref[1]_i_2_n_0 ),\n .O(\\right_edge_ref[1]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\right_edge_ref[1]_i_2 \n (.I0(\\right_edge_ref_reg[5]_i_10_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_6 ),\n .I2(\\right_edge_ref[5]_i_9_n_0 ),\n .I3(\\left_edge_ref_reg[5]_i_3_n_5 ),\n .I4(\\right_edge_ref[1]_i_3_n_0 ),\n .O(\\right_edge_ref[1]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair23\" *) \n LUT5 #(\n .INIT(32'h30BB3088)) \n \\right_edge_ref[1]_i_3 \n (.I0(\\genblk8[2].right_edge_pb_reg_n_0_[17] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[33] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].right_edge_pb_reg_n_0_[1] ),\n .O(\\right_edge_ref[1]_i_3_n_0 ));\n LUT3 #(\n .INIT(8'hB8)) \n \\right_edge_ref[2]_i_1 \n (.I0(\\right_edge_ref[4]_i_4_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_7 ),\n .I2(\\right_edge_ref[2]_i_2_n_0 ),\n .O(\\right_edge_ref[2]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\right_edge_ref[2]_i_2 \n (.I0(\\right_edge_ref_reg[4]_i_3_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_6 ),\n .I2(\\right_edge_ref[4]_i_5_n_0 ),\n .I3(\\left_edge_ref_reg[5]_i_3_n_5 ),\n .I4(\\right_edge_ref[2]_i_3_n_0 ),\n .O(\\right_edge_ref[2]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\right_edge_ref[2]_i_3 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[18] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[34] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].right_edge_pb_reg_n_0_[2] ),\n .O(\\right_edge_ref[2]_i_3_n_0 ));\n LUT3 #(\n .INIT(8'hB8)) \n \\right_edge_ref[3]_i_1 \n (.I0(\\right_edge_ref[5]_i_4_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_7 ),\n .I2(\\right_edge_ref[3]_i_2_n_0 ),\n .O(\\right_edge_ref[3]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\right_edge_ref[3]_i_2 \n (.I0(\\right_edge_ref_reg[5]_i_3_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_6 ),\n .I2(\\right_edge_ref[5]_i_5_n_0 ),\n .I3(\\left_edge_ref_reg[5]_i_3_n_5 ),\n .I4(\\right_edge_ref[3]_i_3_n_0 ),\n .O(\\right_edge_ref[3]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\right_edge_ref[3]_i_3 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[19] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[35] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].right_edge_pb_reg_n_0_[3] ),\n .O(\\right_edge_ref[3]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\right_edge_ref[4]_i_1 \n (.I0(\\right_edge_ref[4]_i_2_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_6 ),\n .I2(\\right_edge_ref_reg[4]_i_3_n_0 ),\n .I3(\\left_edge_ref_reg[5]_i_3_n_7 ),\n .I4(\\right_edge_ref[4]_i_4_n_0 ),\n .O(\\right_edge_ref[4]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\right_edge_ref[4]_i_11 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[20] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].right_edge_pb_reg_n_0_[36] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].right_edge_pb_reg_n_0_[4] ),\n .O(\\right_edge_ref[4]_i_11_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\right_edge_ref[4]_i_12 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[28] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].right_edge_pb_reg_n_0_[44] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[2].right_edge_pb_reg_n_0_[12] ),\n .O(\\right_edge_ref[4]_i_12_n_0 ));\n LUT6 #(\n .INIT(64'h00E2FFFF00E20000)) \n \\right_edge_ref[4]_i_2 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[18] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[34] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\left_edge_ref_reg[5]_i_3_n_5 ),\n .I5(\\right_edge_ref[4]_i_5_n_0 ),\n .O(\\right_edge_ref[4]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\right_edge_ref[4]_i_4 \n (.I0(\\right_edge_ref[4]_i_8_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_5 ),\n .I2(\\right_edge_ref[4]_i_9_n_0 ),\n .I3(\\left_edge_ref_reg[5]_i_3_n_6 ),\n .I4(\\right_edge_ref_reg[4]_i_10_n_0 ),\n .O(\\right_edge_ref[4]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\right_edge_ref[4]_i_5 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[26] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].right_edge_pb_reg_n_0_[42] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].right_edge_pb_reg_n_0_[10] ),\n .O(\\right_edge_ref[4]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\right_edge_ref[4]_i_6 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[22] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].right_edge_pb_reg_n_0_[38] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].right_edge_pb_reg_n_0_[6] ),\n .O(\\right_edge_ref[4]_i_6_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\right_edge_ref[4]_i_7 \n (.I0(\\genblk8[5].right_edge_pb_reg_n_0_[30] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].right_edge_pb_reg_n_0_[46] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[2].right_edge_pb_reg_n_0_[14] ),\n .O(\\right_edge_ref[4]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair24\" *) \n LUT4 #(\n .INIT(16'h00E2)) \n \\right_edge_ref[4]_i_8 \n (.I0(\\genblk8[2].right_edge_pb_reg_n_0_[16] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[32] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .O(\\right_edge_ref[4]_i_8_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\right_edge_ref[4]_i_9 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[24] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].right_edge_pb_reg_n_0_[40] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].right_edge_pb_reg_n_0_[8] ),\n .O(\\right_edge_ref[4]_i_9_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\right_edge_ref[5]_i_1 \n (.I0(\\right_edge_ref[5]_i_2_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_6 ),\n .I2(\\right_edge_ref_reg[5]_i_3_n_0 ),\n .I3(\\left_edge_ref_reg[5]_i_3_n_7 ),\n .I4(\\right_edge_ref[5]_i_4_n_0 ),\n .O(\\right_edge_ref[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\right_edge_ref[5]_i_11 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[21] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].right_edge_pb_reg_n_0_[37] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[0].right_edge_pb_reg_n_0_[5] ),\n .O(\\right_edge_ref[5]_i_11_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\right_edge_ref[5]_i_12 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[29] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].right_edge_pb_reg_n_0_[45] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[2].right_edge_pb_reg_n_0_[13] ),\n .O(\\right_edge_ref[5]_i_12_n_0 ));\n LUT6 #(\n .INIT(64'h00E2FFFF00E20000)) \n \\right_edge_ref[5]_i_2 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[19] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[35] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\left_edge_ref_reg[5]_i_3_n_5 ),\n .I5(\\right_edge_ref[5]_i_5_n_0 ),\n .O(\\right_edge_ref[5]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\right_edge_ref[5]_i_4 \n (.I0(\\right_edge_ref[5]_i_8_n_0 ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_5 ),\n .I2(\\right_edge_ref[5]_i_9_n_0 ),\n .I3(\\left_edge_ref_reg[5]_i_3_n_6 ),\n .I4(\\right_edge_ref_reg[5]_i_10_n_0 ),\n .O(\\right_edge_ref[5]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\right_edge_ref[5]_i_5 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[27] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].right_edge_pb_reg_n_0_[43] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].right_edge_pb_reg_n_0_[11] ),\n .O(\\right_edge_ref[5]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\right_edge_ref[5]_i_6 \n (.I0(\\genblk8[3].right_edge_pb_reg_n_0_[23] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].right_edge_pb_reg_n_0_[39] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].right_edge_pb_reg_n_0_[7] ),\n .O(\\right_edge_ref[5]_i_6_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\right_edge_ref[5]_i_7 \n (.I0(\\genblk8[5].right_edge_pb_reg_n_0_[31] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[7].right_edge_pb_reg_n_0_[47] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[2].right_edge_pb_reg_n_0_[15] ),\n .O(\\right_edge_ref[5]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair23\" *) \n LUT4 #(\n .INIT(16'h00E2)) \n \\right_edge_ref[5]_i_8 \n (.I0(\\genblk8[2].right_edge_pb_reg_n_0_[17] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[5].right_edge_pb_reg_n_0_[33] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .O(\\right_edge_ref[5]_i_8_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\right_edge_ref[5]_i_9 \n (.I0(\\genblk8[4].right_edge_pb_reg_n_0_[25] ),\n .I1(\\left_edge_ref_reg[5]_i_3_n_4 ),\n .I2(\\genblk8[6].right_edge_pb_reg_n_0_[41] ),\n .I3(\\left_edge_ref_reg[5]_i_6_n_7 ),\n .I4(\\genblk8[1].right_edge_pb_reg_n_0_[9] ),\n .O(\\right_edge_ref[5]_i_9_n_0 ));\n FDRE \\right_edge_ref_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\right_edge_ref[0]_i_1_n_0 ),\n .Q(right_edge_ref[0]),\n .R(1'b0));\n FDRE \\right_edge_ref_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\right_edge_ref[1]_i_1_n_0 ),\n .Q(right_edge_ref[1]),\n .R(1'b0));\n FDRE \\right_edge_ref_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\right_edge_ref[2]_i_1_n_0 ),\n .Q(right_edge_ref[2]),\n .R(1'b0));\n FDRE \\right_edge_ref_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\right_edge_ref[3]_i_1_n_0 ),\n .Q(right_edge_ref[3]),\n .R(1'b0));\n FDRE \\right_edge_ref_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\right_edge_ref[4]_i_1_n_0 ),\n .Q(right_edge_ref[4]),\n .R(1'b0));\n MUXF7 \\right_edge_ref_reg[4]_i_10 \n (.I0(\\right_edge_ref[4]_i_11_n_0 ),\n .I1(\\right_edge_ref[4]_i_12_n_0 ),\n .O(\\right_edge_ref_reg[4]_i_10_n_0 ),\n .S(\\left_edge_ref_reg[5]_i_3_n_5 ));\n MUXF7 \\right_edge_ref_reg[4]_i_3 \n (.I0(\\right_edge_ref[4]_i_6_n_0 ),\n .I1(\\right_edge_ref[4]_i_7_n_0 ),\n .O(\\right_edge_ref_reg[4]_i_3_n_0 ),\n .S(\\left_edge_ref_reg[5]_i_3_n_5 ));\n FDRE \\right_edge_ref_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\right_edge_ref[5]_i_1_n_0 ),\n .Q(right_edge_ref[5]),\n .R(1'b0));\n MUXF7 \\right_edge_ref_reg[5]_i_10 \n (.I0(\\right_edge_ref[5]_i_11_n_0 ),\n .I1(\\right_edge_ref[5]_i_12_n_0 ),\n .O(\\right_edge_ref_reg[5]_i_10_n_0 ),\n .S(\\left_edge_ref_reg[5]_i_3_n_5 ));\n MUXF7 \\right_edge_ref_reg[5]_i_3 \n (.I0(\\right_edge_ref[5]_i_6_n_0 ),\n .I1(\\right_edge_ref[5]_i_7_n_0 ),\n .O(\\right_edge_ref_reg[5]_i_3_n_0 ),\n .S(\\left_edge_ref_reg[5]_i_3_n_5 ));\n LUT6 #(\n .INIT(64'h00000000FFFFFFFE)) \n \\samples_cnt_r[0]_i_1 \n (.I0(\\samples_cnt_r_reg_n_0_[11] ),\n .I1(\\samples_cnt_r_reg_n_0_[10] ),\n .I2(\\samples_cnt_r_reg_n_0_[1] ),\n .I3(\\samples_cnt_r[0]_i_2_n_0 ),\n .I4(\\samples_cnt_r[0]_i_3_n_0 ),\n .I5(\\samples_cnt_r_reg_n_0_[0] ),\n .O(\\samples_cnt_r[0]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\samples_cnt_r[0]_i_2 \n (.I0(\\samples_cnt_r_reg_n_0_[7] ),\n .I1(\\samples_cnt_r_reg_n_0_[6] ),\n .I2(\\samples_cnt_r_reg_n_0_[9] ),\n .I3(\\samples_cnt_r_reg_n_0_[8] ),\n .O(\\samples_cnt_r[0]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'hFFF7)) \n \\samples_cnt_r[0]_i_3 \n (.I0(\\samples_cnt_r_reg_n_0_[3] ),\n .I1(\\samples_cnt_r_reg_n_0_[2] ),\n .I2(\\samples_cnt_r_reg_n_0_[5] ),\n .I3(\\samples_cnt_r_reg_n_0_[4] ),\n .O(\\samples_cnt_r[0]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair82\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\samples_cnt_r[10]_i_1 \n (.I0(\\rd_victim_sel_reg[2]_0 ),\n .I1(data0[10]),\n .O(\\samples_cnt_r[10]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair85\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\samples_cnt_r[11]_i_2 \n (.I0(\\rd_victim_sel_reg[2]_0 ),\n .I1(data0[11]),\n .O(\\samples_cnt_r[11]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\samples_cnt_r[11]_i_3 \n (.I0(\\samples_cnt_r_reg_n_0_[11] ),\n .I1(\\samples_cnt_r_reg_n_0_[10] ),\n .I2(\\samples_cnt_r_reg_n_0_[1] ),\n .I3(\\samples_cnt_r[0]_i_2_n_0 ),\n .I4(\\samples_cnt_r[0]_i_3_n_0 ),\n .I5(\\samples_cnt_r_reg_n_0_[0] ),\n .O(\\rd_victim_sel_reg[2]_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samples_cnt_r[11]_i_5 \n (.I0(\\samples_cnt_r_reg_n_0_[11] ),\n .O(\\samples_cnt_r[11]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samples_cnt_r[11]_i_6 \n (.I0(\\samples_cnt_r_reg_n_0_[10] ),\n .O(\\samples_cnt_r[11]_i_6_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samples_cnt_r[11]_i_7 \n (.I0(\\samples_cnt_r_reg_n_0_[9] ),\n .O(\\samples_cnt_r[11]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair85\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\samples_cnt_r[1]_i_1 \n (.I0(\\rd_victim_sel_reg[2]_0 ),\n .I1(data0[1]),\n .O(\\samples_cnt_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair89\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\samples_cnt_r[2]_i_1 \n (.I0(\\rd_victim_sel_reg[2]_0 ),\n .I1(data0[2]),\n .O(\\samples_cnt_r[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair87\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\samples_cnt_r[3]_i_1 \n (.I0(\\rd_victim_sel_reg[2]_0 ),\n .I1(data0[3]),\n .O(\\samples_cnt_r[3]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\samples_cnt_r[4]_i_1 \n (.I0(\\rd_victim_sel_reg[2]_0 ),\n .I1(data0[4]),\n .O(\\samples_cnt_r[4]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samples_cnt_r[4]_i_3 \n (.I0(\\samples_cnt_r_reg_n_0_[4] ),\n .O(\\samples_cnt_r[4]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samples_cnt_r[4]_i_4 \n (.I0(\\samples_cnt_r_reg_n_0_[3] ),\n .O(\\samples_cnt_r[4]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samples_cnt_r[4]_i_5 \n (.I0(\\samples_cnt_r_reg_n_0_[2] ),\n .O(\\samples_cnt_r[4]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samples_cnt_r[4]_i_6 \n (.I0(\\samples_cnt_r_reg_n_0_[1] ),\n .O(\\samples_cnt_r[4]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair89\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\samples_cnt_r[5]_i_1 \n (.I0(\\rd_victim_sel_reg[2]_0 ),\n .I1(data0[5]),\n .O(\\samples_cnt_r[5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair84\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\samples_cnt_r[6]_i_1 \n (.I0(\\rd_victim_sel_reg[2]_0 ),\n .I1(data0[6]),\n .O(\\samples_cnt_r[6]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair87\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\samples_cnt_r[7]_i_1 \n (.I0(\\rd_victim_sel_reg[2]_0 ),\n .I1(data0[7]),\n .O(\\samples_cnt_r[7]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair84\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\samples_cnt_r[8]_i_1 \n (.I0(\\rd_victim_sel_reg[2]_0 ),\n .I1(data0[8]),\n .O(\\samples_cnt_r[8]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samples_cnt_r[8]_i_3 \n (.I0(\\samples_cnt_r_reg_n_0_[8] ),\n .O(\\samples_cnt_r[8]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samples_cnt_r[8]_i_4 \n (.I0(\\samples_cnt_r_reg_n_0_[7] ),\n .O(\\samples_cnt_r[8]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samples_cnt_r[8]_i_5 \n (.I0(\\samples_cnt_r_reg_n_0_[6] ),\n .O(\\samples_cnt_r[8]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samples_cnt_r[8]_i_6 \n (.I0(\\samples_cnt_r_reg_n_0_[5] ),\n .O(\\samples_cnt_r[8]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair82\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\samples_cnt_r[9]_i_1 \n (.I0(\\rd_victim_sel_reg[2]_0 ),\n .I1(data0[9]),\n .O(\\samples_cnt_r[9]_i_1_n_0 ));\n FDRE \\samples_cnt_r_reg[0] \n (.C(CLK),\n .CE(E),\n .D(\\samples_cnt_r[0]_i_1_n_0 ),\n .Q(\\samples_cnt_r_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE \\samples_cnt_r_reg[10] \n (.C(CLK),\n .CE(E),\n .D(\\samples_cnt_r[10]_i_1_n_0 ),\n .Q(\\samples_cnt_r_reg_n_0_[10] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE \\samples_cnt_r_reg[11] \n (.C(CLK),\n .CE(E),\n .D(\\samples_cnt_r[11]_i_2_n_0 ),\n .Q(\\samples_cnt_r_reg_n_0_[11] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n CARRY4 \\samples_cnt_r_reg[11]_i_4 \n (.CI(\\samples_cnt_r_reg[8]_i_2_n_0 ),\n .CO({\\NLW_samples_cnt_r_reg[11]_i_4_CO_UNCONNECTED [3:2],\\samples_cnt_r_reg[11]_i_4_n_2 ,\\samples_cnt_r_reg[11]_i_4_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\NLW_samples_cnt_r_reg[11]_i_4_O_UNCONNECTED [3],data0[11:9]}),\n .S({1'b0,\\samples_cnt_r[11]_i_5_n_0 ,\\samples_cnt_r[11]_i_6_n_0 ,\\samples_cnt_r[11]_i_7_n_0 }));\n FDRE \\samples_cnt_r_reg[1] \n (.C(CLK),\n .CE(E),\n .D(\\samples_cnt_r[1]_i_1_n_0 ),\n .Q(\\samples_cnt_r_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE \\samples_cnt_r_reg[2] \n (.C(CLK),\n .CE(E),\n .D(\\samples_cnt_r[2]_i_1_n_0 ),\n .Q(\\samples_cnt_r_reg_n_0_[2] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE \\samples_cnt_r_reg[3] \n (.C(CLK),\n .CE(E),\n .D(\\samples_cnt_r[3]_i_1_n_0 ),\n .Q(\\samples_cnt_r_reg_n_0_[3] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE \\samples_cnt_r_reg[4] \n (.C(CLK),\n .CE(E),\n .D(\\samples_cnt_r[4]_i_1_n_0 ),\n .Q(\\samples_cnt_r_reg_n_0_[4] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n CARRY4 \\samples_cnt_r_reg[4]_i_2 \n (.CI(1'b0),\n .CO({\\samples_cnt_r_reg[4]_i_2_n_0 ,\\samples_cnt_r_reg[4]_i_2_n_1 ,\\samples_cnt_r_reg[4]_i_2_n_2 ,\\samples_cnt_r_reg[4]_i_2_n_3 }),\n .CYINIT(\\samples_cnt_r_reg_n_0_[0] ),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(data0[4:1]),\n .S({\\samples_cnt_r[4]_i_3_n_0 ,\\samples_cnt_r[4]_i_4_n_0 ,\\samples_cnt_r[4]_i_5_n_0 ,\\samples_cnt_r[4]_i_6_n_0 }));\n FDRE \\samples_cnt_r_reg[5] \n (.C(CLK),\n .CE(E),\n .D(\\samples_cnt_r[5]_i_1_n_0 ),\n .Q(\\samples_cnt_r_reg_n_0_[5] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE \\samples_cnt_r_reg[6] \n (.C(CLK),\n .CE(E),\n .D(\\samples_cnt_r[6]_i_1_n_0 ),\n .Q(\\samples_cnt_r_reg_n_0_[6] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE \\samples_cnt_r_reg[7] \n (.C(CLK),\n .CE(E),\n .D(\\samples_cnt_r[7]_i_1_n_0 ),\n .Q(\\samples_cnt_r_reg_n_0_[7] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n FDRE \\samples_cnt_r_reg[8] \n (.C(CLK),\n .CE(E),\n .D(\\samples_cnt_r[8]_i_1_n_0 ),\n .Q(\\samples_cnt_r_reg_n_0_[8] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n CARRY4 \\samples_cnt_r_reg[8]_i_2 \n (.CI(\\samples_cnt_r_reg[4]_i_2_n_0 ),\n .CO({\\samples_cnt_r_reg[8]_i_2_n_0 ,\\samples_cnt_r_reg[8]_i_2_n_1 ,\\samples_cnt_r_reg[8]_i_2_n_2 ,\\samples_cnt_r_reg[8]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(data0[8:5]),\n .S({\\samples_cnt_r[8]_i_3_n_0 ,\\samples_cnt_r[8]_i_4_n_0 ,\\samples_cnt_r[8]_i_5_n_0 ,\\samples_cnt_r[8]_i_6_n_0 }));\n FDRE \\samples_cnt_r_reg[9] \n (.C(CLK),\n .CE(E),\n .D(\\samples_cnt_r[9]_i_1_n_0 ),\n .Q(\\samples_cnt_r_reg_n_0_[9] ),\n .R(rstdiv0_sync_r1_reg_rep__8));\n (* SOFT_HLUTNM = \"soft_lutpair79\" *) \n LUT2 #(\n .INIT(4'h7)) \n \\smallest_right_edge[0]_i_1 \n (.I0(Q[0]),\n .I1(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .O(\\smallest_right_edge[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair79\" *) \n LUT3 #(\n .INIT(8'hD7)) \n \\smallest_right_edge[1]_i_1 \n (.I0(Q[0]),\n .I1(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .O(\\smallest_right_edge[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair33\" *) \n LUT4 #(\n .INIT(16'hDDD7)) \n \\smallest_right_edge[2]_i_1 \n (.I0(Q[0]),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .O(\\smallest_right_edge[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair33\" *) \n LUT5 #(\n .INIT(32'hDDDDDDD7)) \n \\smallest_right_edge[3]_i_1 \n (.I0(Q[0]),\n .I1(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .I2(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .O(\\smallest_right_edge[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hDDDDDDDDDDDDDDD7)) \n \\smallest_right_edge[4]_i_1 \n (.I0(Q[0]),\n .I1(\\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),\n .I2(\\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),\n .I3(\\prbs_dqs_tap_cnt_r_reg[0]_rep_n_0 ),\n .I4(\\prbs_dqs_tap_cnt_r_reg[1]_rep__0_n_0 ),\n .I5(\\prbs_dqs_tap_cnt_r_reg[3]_rep__0_n_0 ),\n .O(\\smallest_right_edge[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8000800000080308)) \n \\smallest_right_edge[5]_i_1 \n (.I0(\\smallest_right_edge[5]_i_3_n_0 ),\n .I1(Q[0]),\n .I2(Q[2]),\n .I3(Q[3]),\n .I4(Q[4]),\n .I5(Q[1]),\n .O(smallest_right_edge));\n LUT2 #(\n .INIT(4'h7)) \n \\smallest_right_edge[5]_i_2 \n (.I0(Q[0]),\n .I1(\\prbs_dqs_tap_cnt_r[5]_i_5_n_0 ),\n .O(\\smallest_right_edge[5]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0F40004000400040)) \n \\smallest_right_edge[5]_i_3 \n (.I0(no_err_win_detected_latch_reg_0),\n .I1(right_edge_found_reg_1),\n .I2(Q[3]),\n .I3(Q[4]),\n .I4(\\smallest_right_edge[5]_i_4_n_0 ),\n .I5(prbs_state_r1),\n .O(\\smallest_right_edge[5]_i_3_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\smallest_right_edge[5]_i_4 \n (.I0(num_samples_done_r),\n .I1(right_edge_found_reg_0),\n .O(\\smallest_right_edge[5]_i_4_n_0 ));\n FDSE \\smallest_right_edge_reg[0] \n (.C(CLK),\n .CE(smallest_right_edge),\n .D(\\smallest_right_edge[0]_i_1_n_0 ),\n .Q(\\smallest_right_edge_reg_n_0_[0] ),\n .S(rstdiv0_sync_r1_reg_rep__8));\n FDSE \\smallest_right_edge_reg[1] \n (.C(CLK),\n .CE(smallest_right_edge),\n .D(\\smallest_right_edge[1]_i_1_n_0 ),\n .Q(\\smallest_right_edge_reg_n_0_[1] ),\n .S(rstdiv0_sync_r1_reg_rep__8));\n FDSE \\smallest_right_edge_reg[2] \n (.C(CLK),\n .CE(smallest_right_edge),\n .D(\\smallest_right_edge[2]_i_1_n_0 ),\n .Q(\\smallest_right_edge_reg_n_0_[2] ),\n .S(rstdiv0_sync_r1_reg_rep__8));\n FDSE \\smallest_right_edge_reg[3] \n (.C(CLK),\n .CE(smallest_right_edge),\n .D(\\smallest_right_edge[3]_i_1_n_0 ),\n .Q(\\smallest_right_edge_reg_n_0_[3] ),\n .S(rstdiv0_sync_r1_reg_rep__8));\n FDSE \\smallest_right_edge_reg[4] \n (.C(CLK),\n .CE(smallest_right_edge),\n .D(\\smallest_right_edge[4]_i_1_n_0 ),\n .Q(\\smallest_right_edge_reg_n_0_[4] ),\n .S(rstdiv0_sync_r1_reg_rep__8));\n FDSE \\smallest_right_edge_reg[5] \n (.C(CLK),\n .CE(smallest_right_edge),\n .D(\\smallest_right_edge[5]_i_2_n_0 ),\n .Q(\\smallest_right_edge_reg_n_0_[5] ),\n .S(rstdiv0_sync_r1_reg_rep__8));\n (* SOFT_HLUTNM = \"soft_lutpair54\" *) \n LUT3 #(\n .INIT(8'h38)) \n \\stage_cnt[0]_i_1 \n (.I0(Q[4]),\n .I1(\\stage_cnt[1]_i_2_n_0 ),\n .I2(\\stage_cnt_reg_n_0_[0] ),\n .O(\\stage_cnt[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair54\" *) \n LUT4 #(\n .INIT(16'h2F80)) \n \\stage_cnt[1]_i_1 \n (.I0(Q[4]),\n .I1(\\stage_cnt_reg_n_0_[0] ),\n .I2(\\stage_cnt[1]_i_2_n_0 ),\n .I3(\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ),\n .O(\\stage_cnt[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000202020002)) \n \\stage_cnt[1]_i_2 \n (.I0(Q[0]),\n .I1(Q[2]),\n .I2(Q[3]),\n .I3(Q[4]),\n .I4(Q[1]),\n .I5(fine_delay_sel_reg_0),\n .O(\\stage_cnt[1]_i_2_n_0 ));\n FDRE \\stage_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\stage_cnt[0]_i_1_n_0 ),\n .Q(\\stage_cnt_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE \\stage_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\stage_cnt[1]_i_1_n_0 ),\n .Q(\\genblk9[0].fine_delay_incdec_pb_reg[0]_0 ),\n .R(rstdiv0_sync_r1_reg_rep__7));\n LUT6 #(\n .INIT(64'h00000000AAAAEAAA)) \n \\victim_not_fixed.num_samples_done_r_i_1 \n (.I0(num_samples_done_r),\n .I1(\\rd_victim_sel_reg[2]_3 ),\n .I2(\\rd_victim_sel_reg[2]_2 ),\n .I3(\\rd_victim_sel_reg[2]_1 ),\n .I4(\\rd_victim_sel_reg[2]_0 ),\n .I5(\\victim_not_fixed.num_samples_done_r_i_2_n_0 ),\n .O(\\victim_not_fixed.num_samples_done_r_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAEBEEAAAAAAAA)) \n \\victim_not_fixed.num_samples_done_r_i_2 \n (.I0(rstdiv0_sync_r1_reg_rep__23),\n .I1(Q[2]),\n .I2(Q[3]),\n .I3(Q[1]),\n .I4(Q[4]),\n .I5(Q[0]),\n .O(\\victim_not_fixed.num_samples_done_r_i_2_n_0 ));\n FDRE \\victim_not_fixed.num_samples_done_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\victim_not_fixed.num_samples_done_r_i_1_n_0 ),\n .Q(num_samples_done_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair41\" *) \n LUT5 #(\n .INIT(32'h00050A12)) \n wait_state_cnt_en_r_i_1\n (.I0(Q[2]),\n .I1(Q[3]),\n .I2(Q[4]),\n .I3(Q[1]),\n .I4(Q[0]),\n .O(wait_state_cnt_en_r0));\n FDRE wait_state_cnt_en_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wait_state_cnt_en_r0),\n .Q(wait_state_cnt_en_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair86\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\wait_state_cnt_r[0]_i_1 \n (.I0(wait_state_cnt_r_reg__0[0]),\n .O(p_0_in[0]));\n (* SOFT_HLUTNM = \"soft_lutpair86\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\wait_state_cnt_r[1]_i_1 \n (.I0(wait_state_cnt_r_reg__0[0]),\n .I1(wait_state_cnt_r_reg__0[1]),\n .O(p_0_in[1]));\n (* SOFT_HLUTNM = \"soft_lutpair67\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\wait_state_cnt_r[2]_i_1 \n (.I0(wait_state_cnt_r_reg__0[1]),\n .I1(wait_state_cnt_r_reg__0[0]),\n .I2(wait_state_cnt_r_reg__0[2]),\n .O(\\wait_state_cnt_r[2]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hD5555555)) \n \\wait_state_cnt_r[3]_i_1 \n (.I0(wait_state_cnt_en_r),\n .I1(wait_state_cnt_r_reg__0[3]),\n .I2(wait_state_cnt_r_reg__0[2]),\n .I3(wait_state_cnt_r_reg__0[0]),\n .I4(wait_state_cnt_r_reg__0[1]),\n .O(\\wait_state_cnt_r[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair67\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\wait_state_cnt_r[3]_i_2 \n (.I0(wait_state_cnt_r_reg__0[0]),\n .I1(wait_state_cnt_r_reg__0[1]),\n .I2(wait_state_cnt_r_reg__0[2]),\n .I3(wait_state_cnt_r_reg__0[3]),\n .O(p_0_in[3]));\n FDRE \\wait_state_cnt_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in[0]),\n .Q(wait_state_cnt_r_reg__0[0]),\n .R(\\wait_state_cnt_r[3]_i_1_n_0 ));\n FDRE \\wait_state_cnt_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in[1]),\n .Q(wait_state_cnt_r_reg__0[1]),\n .R(\\wait_state_cnt_r[3]_i_1_n_0 ));\n FDRE \\wait_state_cnt_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wait_state_cnt_r[2]_i_1_n_0 ),\n .Q(wait_state_cnt_r_reg__0[2]),\n .R(\\wait_state_cnt_r[3]_i_1_n_0 ));\n FDRE \\wait_state_cnt_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in[3]),\n .Q(wait_state_cnt_r_reg__0[3]),\n .R(\\wait_state_cnt_r[3]_i_1_n_0 ));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_ddr_phy_rdlvl\n (mpr_rdlvl_done_r1_reg_0,\n store_sr_r_reg_0,\n sr_valid_r1_reg_0,\n found_stable_eye_last_r_reg_0,\n found_first_edge_r_reg_0,\n mpr_rdlvl_start_r,\n mpr_valid_r1_reg_0,\n detect_edge_done_r,\n samp_edge_cnt0_en_r,\n \\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_0 ,\n p_0_in102_in,\n p_0_in99_in,\n p_0_in96_in,\n p_0_in93_in,\n p_0_in90_in,\n p_0_in87_in,\n p_0_in84_in,\n idelay_ce_int,\n idelay_inc_int,\n dqs_po_dec_done_r2,\n rdlvl_prech_req,\n pi_fine_dly_dec_done,\n pb_detect_edge_done_r,\n \\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0]_0 ,\n \\gen_track_left_edge[0].pb_found_stable_eye_r_reg ,\n \\gen_track_left_edge[1].pb_found_stable_eye_r_reg ,\n \\gen_track_left_edge[2].pb_found_stable_eye_r_reg ,\n \\gen_track_left_edge[3].pb_found_stable_eye_r_reg ,\n \\gen_track_left_edge[4].pb_found_stable_eye_r_reg ,\n \\gen_track_left_edge[5].pb_found_stable_eye_r_reg ,\n \\gen_track_left_edge[6].pb_found_stable_eye_r_reg ,\n \\gen_track_left_edge[7].pb_found_stable_eye_r_reg ,\n \\gen_track_left_edge[0].pb_found_edge_r_reg[0]_0 ,\n found_edge_r_reg_0,\n found_edge_r_reg_1,\n found_edge_r_reg_2,\n \\gen_track_left_edge[4].pb_found_edge_r_reg[4]_0 ,\n found_edge_r_reg_3,\n \\gen_track_left_edge[6].pb_found_edge_r_reg[6]_0 ,\n \\gen_track_left_edge[7].pb_found_edge_r_reg[7]_0 ,\n \\right_edge_taps_r_reg[0]_0 ,\n cal1_wait_r,\n found_stable_eye_last_r,\n mpr_rd_rise0_prev_r_reg_0,\n mpr_dec_cpt_r_reg_0,\n idel_adj_inc_reg_0,\n pi_en_stg2_f_timing_reg_0,\n mpr_last_byte_done,\n mpr_rnk_done,\n rdlvl_stg1_done_r1_reg,\n rdlvl_stg1_rank_done,\n rdlvl_last_byte_done,\n rdlvl_pi_incdec,\n \\cnt_idel_dec_cpt_r_reg[0]_0 ,\n \\pi_dqs_found_lanes_r1_reg[3] ,\n \\pi_dqs_found_lanes_r1_reg[3]_0 ,\n \\pi_dqs_found_lanes_r1_reg[3]_1 ,\n \\pi_dqs_found_lanes_r1_reg[2] ,\n \\pi_dqs_found_lanes_r1_reg[2]_0 ,\n \\pi_dqs_found_lanes_r1_reg[2]_1 ,\n \\pi_dqs_found_lanes_r1_reg[1] ,\n \\pi_dqs_found_lanes_r1_reg[1]_0 ,\n \\pi_dqs_found_lanes_r1_reg[1]_1 ,\n COUNTERLOADVAL,\n \\pi_dqs_found_lanes_r1_reg[0] ,\n \\pi_dqs_found_lanes_r1_reg[0]_0 ,\n \\pi_dqs_found_lanes_r1_reg[0]_1 ,\n \\stg1_wr_rd_cnt_reg[3] ,\n \\init_state_r_reg[0] ,\n \\init_state_r_reg[0]_0 ,\n \\init_state_r_reg[0]_1 ,\n out,\n idel_adj_inc_reg_1,\n \\wait_cnt_r_reg[0]_0 ,\n \\right_edge_taps_r_reg[0]_1 ,\n store_sr_req_r_reg_0,\n \\rdlvl_cpt_tap_cnt_reg[4] ,\n \\rdlvl_cpt_tap_cnt_reg[1] ,\n \\rdlvl_cpt_tap_cnt_reg[2] ,\n \\pi_rdval_cnt_reg[1]_0 ,\n \\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ,\n \\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ,\n \\pi_stg2_reg_l_timing_reg[0]_0 ,\n \\regl_dqs_cnt_r_reg[2]_0 ,\n \\regl_dqs_cnt_reg[0]_0 ,\n mpr_rd_rise0_prev_r_reg_1,\n \\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 ,\n cal1_cnt_cpt_r1,\n mpr_valid_r_reg_0,\n \\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 ,\n \\gen_track_left_edge[0].pb_found_edge_r_reg[0]_1 ,\n p_0_in16_in,\n \\gen_track_left_edge[1].pb_found_edge_r_reg[1]_0 ,\n p_0_in13_in,\n \\gen_track_left_edge[2].pb_found_edge_r_reg[2]_0 ,\n p_0_in10_in,\n \\gen_track_left_edge[3].pb_found_edge_r_reg[3]_0 ,\n p_0_in7_in,\n \\gen_track_left_edge[4].pb_found_edge_r_reg[4]_1 ,\n p_0_in4_in,\n \\gen_track_left_edge[5].pb_found_edge_r_reg[5]_0 ,\n p_0_in1_in,\n \\gen_track_left_edge[6].pb_found_edge_r_reg[6]_1 ,\n p_0_in,\n \\gen_track_left_edge[7].pb_found_edge_r_reg[7]_1 ,\n pb_found_stable_eye_r76_out,\n \\gen_track_left_edge[0].pb_found_stable_eye_r_reg[0]_0 ,\n pb_found_stable_eye_r72_out,\n \\gen_track_left_edge[1].pb_found_stable_eye_r_reg[1]_0 ,\n pb_found_stable_eye_r68_out,\n \\gen_track_left_edge[2].pb_found_stable_eye_r_reg[2]_0 ,\n pb_found_stable_eye_r64_out,\n \\gen_track_left_edge[3].pb_found_stable_eye_r_reg[3]_0 ,\n pb_found_stable_eye_r60_out,\n \\gen_track_left_edge[4].pb_found_stable_eye_r_reg[4]_0 ,\n pb_found_stable_eye_r56_out,\n \\gen_track_left_edge[5].pb_found_stable_eye_r_reg[5]_0 ,\n pb_found_stable_eye_r52_out,\n \\gen_track_left_edge[6].pb_found_stable_eye_r_reg[6]_0 ,\n \\gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_0 ,\n \\gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_1 ,\n \\right_edge_taps_r_reg[0]_2 ,\n idel_adj_inc_reg_2,\n pi_cnt_dec_reg_0,\n \\init_state_r_reg[1] ,\n prech_req,\n \\init_state_r_reg[2] ,\n \\init_state_r_reg[2]_0 ,\n \\init_state_r_reg[2]_1 ,\n \\init_state_r_reg[5] ,\n \\init_state_r_reg[0]_2 ,\n \\init_state_r_reg[3] ,\n \\init_state_r_reg[0]_3 ,\n \\init_state_r_reg[4] ,\n \\init_state_r_reg[0]_4 ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[254] ,\n \\init_state_r_reg[2]_2 ,\n D,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[2] ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 ,\n cmd_delay_start0,\n \\second_edge_taps_r_reg[5]_0 ,\n \\pi_dqs_found_lanes_r1_reg[1]_2 ,\n \\pi_dqs_found_lanes_r1_reg[2]_2 ,\n \\pi_dqs_found_lanes_r1_reg[3]_2 ,\n rdlvl_pi_incdec_reg_0,\n pi_stg2_rdlvl_cnt,\n mpr_last_byte_done_reg_0,\n mpr_rank_done_r_reg_0,\n rdlvl_pi_incdec_reg_1,\n \\idel_dec_cnt_reg[0]_0 ,\n rdlvl_stg1_done_int,\n rdlvl_rank_done_r_reg_0,\n mpr_rank_done_r_reg_1,\n mpr_dec_cpt_r_reg_1,\n CLK,\n rstdiv0_sync_r1_reg_rep__14,\n sr_valid_r108_out,\n \\rd_mux_sel_r_reg[1]_0 ,\n \\rd_mux_sel_r_reg[1]_1 ,\n \\rd_mux_sel_r_reg[1]_2 ,\n \\rd_mux_sel_r_reg[1]_3 ,\n \\rd_mux_sel_r_reg[1]_4 ,\n \\rd_mux_sel_r_reg[1]_5 ,\n \\rd_mux_sel_r_reg[1]_6 ,\n \\rd_mux_sel_r_reg[1]_7 ,\n \\rd_mux_sel_r_reg[1]_8 ,\n \\rd_mux_sel_r_reg[1]_9 ,\n \\rd_mux_sel_r_reg[1]_10 ,\n \\rd_mux_sel_r_reg[1]_11 ,\n \\rd_mux_sel_r_reg[1]_12 ,\n \\rd_mux_sel_r_reg[1]_13 ,\n \\rd_mux_sel_r_reg[1]_14 ,\n \\rd_mux_sel_r_reg[1]_15 ,\n \\rd_mux_sel_r_reg[1]_16 ,\n \\rd_mux_sel_r_reg[1]_17 ,\n \\rd_mux_sel_r_reg[1]_18 ,\n \\rd_mux_sel_r_reg[1]_19 ,\n \\rd_mux_sel_r_reg[1]_20 ,\n \\rd_mux_sel_r_reg[1]_21 ,\n \\rd_mux_sel_r_reg[1]_22 ,\n \\rd_mux_sel_r_reg[1]_23 ,\n \\rd_mux_sel_r_reg[1]_24 ,\n \\rd_mux_sel_r_reg[1]_25 ,\n \\rd_mux_sel_r_reg[1]_26 ,\n \\rd_mux_sel_r_reg[1]_27 ,\n \\rd_mux_sel_r_reg[1]_28 ,\n \\rd_mux_sel_r_reg[1]_29 ,\n \\rd_mux_sel_r_reg[1]_30 ,\n \\rd_mux_sel_r_reg[1]_31 ,\n \\rd_mux_sel_r_reg[1]_32 ,\n \\rd_mux_sel_r_reg[1]_33 ,\n \\rd_mux_sel_r_reg[1]_34 ,\n \\rd_mux_sel_r_reg[1]_35 ,\n \\rd_mux_sel_r_reg[1]_36 ,\n \\rd_mux_sel_r_reg[1]_37 ,\n \\rd_mux_sel_r_reg[1]_38 ,\n \\rd_mux_sel_r_reg[1]_39 ,\n \\rd_mux_sel_r_reg[1]_40 ,\n \\rd_mux_sel_r_reg[1]_41 ,\n \\rd_mux_sel_r_reg[1]_42 ,\n \\rd_mux_sel_r_reg[1]_43 ,\n \\rd_mux_sel_r_reg[1]_44 ,\n \\rd_mux_sel_r_reg[1]_45 ,\n \\rd_mux_sel_r_reg[1]_46 ,\n \\rd_mux_sel_r_reg[1]_47 ,\n \\rd_mux_sel_r_reg[1]_48 ,\n \\rd_mux_sel_r_reg[1]_49 ,\n \\rd_mux_sel_r_reg[1]_50 ,\n \\rd_mux_sel_r_reg[1]_51 ,\n \\rd_mux_sel_r_reg[1]_52 ,\n \\rd_mux_sel_r_reg[1]_53 ,\n \\rd_mux_sel_r_reg[1]_54 ,\n \\rd_mux_sel_r_reg[1]_55 ,\n \\rd_mux_sel_r_reg[1]_56 ,\n \\rd_mux_sel_r_reg[1]_57 ,\n \\rd_mux_sel_r_reg[1]_58 ,\n \\rd_mux_sel_r_reg[1]_59 ,\n \\rd_mux_sel_r_reg[1]_60 ,\n \\rd_mux_sel_r_reg[1]_61 ,\n \\rd_mux_sel_r_reg[1]_62 ,\n \\rd_mux_sel_r_reg[1]_63 ,\n mpr_rdlvl_start_reg,\n rdlvl_stg1_start_reg,\n phy_rddata_en_1,\n dqs_po_dec_done,\n rstdiv0_sync_r1_reg_rep__13,\n samp_cnt_done_r_reg_0,\n samp_cnt_done_r_reg_1,\n samp_cnt_done_r_reg_2,\n samp_cnt_done_r_reg_3,\n samp_cnt_done_r_reg_4,\n samp_cnt_done_r_reg_5,\n samp_cnt_done_r_reg_6,\n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg[0]_0 ,\n mpr_rdlvl_done_r_reg_0,\n store_sr_req_r_reg_1,\n \\gen_track_left_edge[0].pb_detect_edge_done_r_reg[0]_0 ,\n \\gen_track_left_edge[1].pb_detect_edge_done_r_reg[1]_0 ,\n \\gen_track_left_edge[2].pb_detect_edge_done_r_reg[2]_0 ,\n \\gen_track_left_edge[3].pb_detect_edge_done_r_reg[3]_0 ,\n \\gen_track_left_edge[4].pb_detect_edge_done_r_reg[4]_0 ,\n \\gen_track_left_edge[5].pb_detect_edge_done_r_reg[5]_0 ,\n \\gen_track_left_edge[6].pb_detect_edge_done_r_reg[6]_0 ,\n \\gen_track_left_edge[7].pb_detect_edge_done_r_reg[7]_0 ,\n \\gen_track_left_edge[0].pb_found_edge_r_reg[0]_2 ,\n \\gen_track_left_edge[1].pb_found_edge_r_reg[1]_1 ,\n \\gen_track_left_edge[2].pb_found_edge_r_reg[2]_1 ,\n \\gen_track_left_edge[3].pb_found_edge_r_reg[3]_1 ,\n \\gen_track_left_edge[4].pb_found_edge_r_reg[4]_2 ,\n \\gen_track_left_edge[5].pb_found_edge_r_reg[5]_1 ,\n \\gen_track_left_edge[6].pb_found_edge_r_reg[6]_2 ,\n \\gen_track_left_edge[7].pb_found_edge_r_reg[7]_2 ,\n found_edge_r_reg_4,\n found_stable_eye_r_reg_0,\n \\FSM_sequential_cal1_state_r_reg[4]_0 ,\n \\FSM_sequential_cal1_state_r_reg[3]_0 ,\n \\FSM_sequential_cal1_state_r_reg[2]_0 ,\n \\wait_cnt_r_reg[0]_1 ,\n \\FSM_sequential_cal1_state_r_reg[4]_1 ,\n \\FSM_sequential_cal1_state_r_reg[4]_2 ,\n mpr_rdlvl_done_r_reg_1,\n \\FSM_sequential_cal1_state_r_reg[4]_3 ,\n \\FSM_sequential_cal1_state_r_reg[4]_4 ,\n \\regl_dqs_cnt_reg[2]_0 ,\n \\FSM_sequential_cal1_state_r_reg[1]_0 ,\n SR,\n found_stable_eye_last_r_reg_1,\n \\gen_byte_sel_div1.calib_in_common_reg_0 ,\n prbs_pi_stg2_f_incdec,\n tempmon_pi_f_inc_r,\n Q,\n prbs_pi_stg2_f_en,\n tempmon_pi_f_en_r,\n calib_in_common,\n \\calib_sel_reg[3] ,\n \\gen_byte_sel_div1.calib_in_common_reg_1 ,\n \\gen_byte_sel_div1.calib_in_common_reg_2 ,\n \\gen_byte_sel_div1.calib_in_common_reg_3 ,\n rstdiv0_sync_r1_reg_rep__24,\n stg1_wr_done,\n wrcal_done_reg,\n dqs_found_done_r_reg,\n \\init_state_r_reg[1]_0 ,\n oclkdelay_calib_done_r_reg,\n \\one_rank.stg1_wr_done_reg ,\n cal1_state_r1535_out,\n rstdiv0_sync_r1_reg_rep__23,\n \\calib_sel_reg[3]_0 ,\n \\po_stg2_wrcal_cnt_reg[0] ,\n \\po_stg2_wrcal_cnt_reg[1] ,\n cal1_dq_idel_ce_reg_0,\n prech_done,\n \\pi_counter_read_val_reg[5] ,\n rstdiv0_sync_r1_reg_rep__20,\n \\init_state_r_reg[3]_0 ,\n wrcal_prech_req,\n complex_ocal_ref_req,\n prbs_rdlvl_prech_req_reg,\n dqs_found_prech_req,\n \\init_state_r_reg[5]_0 ,\n wrlvl_done_r1_reg,\n wrlvl_done_r1_reg_0,\n cnt_init_af_done_r,\n dqs_found_done_r_reg_0,\n prbs_rdlvl_done_reg_rep,\n wrlvl_byte_redo,\n wrlvl_final_mux,\n mem_init_done_r,\n prbs_rdlvl_done_reg_rep_0,\n \\num_refresh_reg[1] ,\n prbs_last_byte_done_r,\n wrlvl_final_mux_reg,\n prbs_rdlvl_done_reg_rep_1,\n oclkdelay_center_calib_done_r_reg,\n wrlvl_done_r1,\n wrlvl_byte_redo_reg,\n \\dout_o_reg[6] ,\n first_wrcal_pat_r,\n \\dout_o_reg[6]_0 ,\n prbs_rdlvl_done_reg,\n wr_level_done_reg,\n \\prbs_dqs_cnt_r_reg[2] ,\n \\po_stg2_wrcal_cnt_reg[2] ,\n rdlvl_stg1_start_reg_0,\n E,\n samp_edge_cnt0_en_r_reg_0,\n pi_cnt_dec_reg_1,\n rstdiv0_sync_r1_reg_rep__2);\n output mpr_rdlvl_done_r1_reg_0;\n output store_sr_r_reg_0;\n output sr_valid_r1_reg_0;\n output found_stable_eye_last_r_reg_0;\n output found_first_edge_r_reg_0;\n output mpr_rdlvl_start_r;\n output mpr_valid_r1_reg_0;\n output detect_edge_done_r;\n output samp_edge_cnt0_en_r;\n output \\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_0 ;\n output p_0_in102_in;\n output p_0_in99_in;\n output p_0_in96_in;\n output p_0_in93_in;\n output p_0_in90_in;\n output p_0_in87_in;\n output p_0_in84_in;\n output idelay_ce_int;\n output idelay_inc_int;\n output dqs_po_dec_done_r2;\n output rdlvl_prech_req;\n output pi_fine_dly_dec_done;\n output [7:0]pb_detect_edge_done_r;\n output \\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0]_0 ;\n output \\gen_track_left_edge[0].pb_found_stable_eye_r_reg ;\n output \\gen_track_left_edge[1].pb_found_stable_eye_r_reg ;\n output \\gen_track_left_edge[2].pb_found_stable_eye_r_reg ;\n output \\gen_track_left_edge[3].pb_found_stable_eye_r_reg ;\n output \\gen_track_left_edge[4].pb_found_stable_eye_r_reg ;\n output \\gen_track_left_edge[5].pb_found_stable_eye_r_reg ;\n output \\gen_track_left_edge[6].pb_found_stable_eye_r_reg ;\n output \\gen_track_left_edge[7].pb_found_stable_eye_r_reg ;\n output \\gen_track_left_edge[0].pb_found_edge_r_reg[0]_0 ;\n output found_edge_r_reg_0;\n output found_edge_r_reg_1;\n output found_edge_r_reg_2;\n output \\gen_track_left_edge[4].pb_found_edge_r_reg[4]_0 ;\n output found_edge_r_reg_3;\n output \\gen_track_left_edge[6].pb_found_edge_r_reg[6]_0 ;\n output \\gen_track_left_edge[7].pb_found_edge_r_reg[7]_0 ;\n output \\right_edge_taps_r_reg[0]_0 ;\n output cal1_wait_r;\n output found_stable_eye_last_r;\n output mpr_rd_rise0_prev_r_reg_0;\n output mpr_dec_cpt_r_reg_0;\n output idel_adj_inc_reg_0;\n output pi_en_stg2_f_timing_reg_0;\n output mpr_last_byte_done;\n output mpr_rnk_done;\n output rdlvl_stg1_done_r1_reg;\n output rdlvl_stg1_rank_done;\n output rdlvl_last_byte_done;\n output rdlvl_pi_incdec;\n output \\cnt_idel_dec_cpt_r_reg[0]_0 ;\n output \\pi_dqs_found_lanes_r1_reg[3] ;\n output \\pi_dqs_found_lanes_r1_reg[3]_0 ;\n output \\pi_dqs_found_lanes_r1_reg[3]_1 ;\n output \\pi_dqs_found_lanes_r1_reg[2] ;\n output \\pi_dqs_found_lanes_r1_reg[2]_0 ;\n output \\pi_dqs_found_lanes_r1_reg[2]_1 ;\n output \\pi_dqs_found_lanes_r1_reg[1] ;\n output \\pi_dqs_found_lanes_r1_reg[1]_0 ;\n output \\pi_dqs_found_lanes_r1_reg[1]_1 ;\n output [5:0]COUNTERLOADVAL;\n output \\pi_dqs_found_lanes_r1_reg[0] ;\n output \\pi_dqs_found_lanes_r1_reg[0]_0 ;\n output \\pi_dqs_found_lanes_r1_reg[0]_1 ;\n output \\stg1_wr_rd_cnt_reg[3] ;\n output \\init_state_r_reg[0] ;\n output \\init_state_r_reg[0]_0 ;\n output \\init_state_r_reg[0]_1 ;\n output [4:0]out;\n output idel_adj_inc_reg_1;\n output [1:0]\\wait_cnt_r_reg[0]_0 ;\n output \\right_edge_taps_r_reg[0]_1 ;\n output store_sr_req_r_reg_0;\n output \\rdlvl_cpt_tap_cnt_reg[4] ;\n output \\rdlvl_cpt_tap_cnt_reg[1] ;\n output \\rdlvl_cpt_tap_cnt_reg[2] ;\n output \\pi_rdval_cnt_reg[1]_0 ;\n output \\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ;\n output \\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ;\n output \\pi_stg2_reg_l_timing_reg[0]_0 ;\n output [0:0]\\regl_dqs_cnt_r_reg[2]_0 ;\n output \\regl_dqs_cnt_reg[0]_0 ;\n output mpr_rd_rise0_prev_r_reg_1;\n output [1:0]\\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 ;\n output cal1_cnt_cpt_r1;\n output mpr_valid_r_reg_0;\n output \\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 ;\n output \\gen_track_left_edge[0].pb_found_edge_r_reg[0]_1 ;\n output p_0_in16_in;\n output \\gen_track_left_edge[1].pb_found_edge_r_reg[1]_0 ;\n output p_0_in13_in;\n output \\gen_track_left_edge[2].pb_found_edge_r_reg[2]_0 ;\n output p_0_in10_in;\n output \\gen_track_left_edge[3].pb_found_edge_r_reg[3]_0 ;\n output p_0_in7_in;\n output \\gen_track_left_edge[4].pb_found_edge_r_reg[4]_1 ;\n output p_0_in4_in;\n output \\gen_track_left_edge[5].pb_found_edge_r_reg[5]_0 ;\n output p_0_in1_in;\n output \\gen_track_left_edge[6].pb_found_edge_r_reg[6]_1 ;\n output p_0_in;\n output \\gen_track_left_edge[7].pb_found_edge_r_reg[7]_1 ;\n output pb_found_stable_eye_r76_out;\n output \\gen_track_left_edge[0].pb_found_stable_eye_r_reg[0]_0 ;\n output pb_found_stable_eye_r72_out;\n output \\gen_track_left_edge[1].pb_found_stable_eye_r_reg[1]_0 ;\n output pb_found_stable_eye_r68_out;\n output \\gen_track_left_edge[2].pb_found_stable_eye_r_reg[2]_0 ;\n output pb_found_stable_eye_r64_out;\n output \\gen_track_left_edge[3].pb_found_stable_eye_r_reg[3]_0 ;\n output pb_found_stable_eye_r60_out;\n output \\gen_track_left_edge[4].pb_found_stable_eye_r_reg[4]_0 ;\n output pb_found_stable_eye_r56_out;\n output \\gen_track_left_edge[5].pb_found_stable_eye_r_reg[5]_0 ;\n output pb_found_stable_eye_r52_out;\n output \\gen_track_left_edge[6].pb_found_stable_eye_r_reg[6]_0 ;\n output \\gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_0 ;\n output \\gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_1 ;\n output \\right_edge_taps_r_reg[0]_2 ;\n output idel_adj_inc_reg_2;\n output pi_cnt_dec_reg_0;\n output \\init_state_r_reg[1] ;\n output prech_req;\n output \\init_state_r_reg[2] ;\n output \\init_state_r_reg[2]_0 ;\n output \\init_state_r_reg[2]_1 ;\n output \\init_state_r_reg[5] ;\n output \\init_state_r_reg[0]_2 ;\n output \\init_state_r_reg[3] ;\n output \\init_state_r_reg[0]_3 ;\n output \\init_state_r_reg[4] ;\n output \\init_state_r_reg[0]_4 ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[254] ;\n output \\init_state_r_reg[2]_2 ;\n output [1:0]D;\n output \\gen_byte_sel_div1.calib_in_common_reg ;\n output \\gen_byte_sel_div1.byte_sel_cnt_reg[2] ;\n output \\gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 ;\n output cmd_delay_start0;\n output \\second_edge_taps_r_reg[5]_0 ;\n output [5:0]\\pi_dqs_found_lanes_r1_reg[1]_2 ;\n output [5:0]\\pi_dqs_found_lanes_r1_reg[2]_2 ;\n output [5:0]\\pi_dqs_found_lanes_r1_reg[3]_2 ;\n output rdlvl_pi_incdec_reg_0;\n output [1:0]pi_stg2_rdlvl_cnt;\n output mpr_last_byte_done_reg_0;\n output mpr_rank_done_r_reg_0;\n output rdlvl_pi_incdec_reg_1;\n output \\idel_dec_cnt_reg[0]_0 ;\n output rdlvl_stg1_done_int;\n output rdlvl_rank_done_r_reg_0;\n output mpr_rank_done_r_reg_1;\n output mpr_dec_cpt_r_reg_1;\n input CLK;\n input [1:0]rstdiv0_sync_r1_reg_rep__14;\n input sr_valid_r108_out;\n input \\rd_mux_sel_r_reg[1]_0 ;\n input \\rd_mux_sel_r_reg[1]_1 ;\n input \\rd_mux_sel_r_reg[1]_2 ;\n input \\rd_mux_sel_r_reg[1]_3 ;\n input \\rd_mux_sel_r_reg[1]_4 ;\n input \\rd_mux_sel_r_reg[1]_5 ;\n input \\rd_mux_sel_r_reg[1]_6 ;\n input \\rd_mux_sel_r_reg[1]_7 ;\n input \\rd_mux_sel_r_reg[1]_8 ;\n input \\rd_mux_sel_r_reg[1]_9 ;\n input \\rd_mux_sel_r_reg[1]_10 ;\n input \\rd_mux_sel_r_reg[1]_11 ;\n input \\rd_mux_sel_r_reg[1]_12 ;\n input \\rd_mux_sel_r_reg[1]_13 ;\n input \\rd_mux_sel_r_reg[1]_14 ;\n input \\rd_mux_sel_r_reg[1]_15 ;\n input \\rd_mux_sel_r_reg[1]_16 ;\n input \\rd_mux_sel_r_reg[1]_17 ;\n input \\rd_mux_sel_r_reg[1]_18 ;\n input \\rd_mux_sel_r_reg[1]_19 ;\n input \\rd_mux_sel_r_reg[1]_20 ;\n input \\rd_mux_sel_r_reg[1]_21 ;\n input \\rd_mux_sel_r_reg[1]_22 ;\n input \\rd_mux_sel_r_reg[1]_23 ;\n input \\rd_mux_sel_r_reg[1]_24 ;\n input \\rd_mux_sel_r_reg[1]_25 ;\n input \\rd_mux_sel_r_reg[1]_26 ;\n input \\rd_mux_sel_r_reg[1]_27 ;\n input \\rd_mux_sel_r_reg[1]_28 ;\n input \\rd_mux_sel_r_reg[1]_29 ;\n input \\rd_mux_sel_r_reg[1]_30 ;\n input \\rd_mux_sel_r_reg[1]_31 ;\n input \\rd_mux_sel_r_reg[1]_32 ;\n input \\rd_mux_sel_r_reg[1]_33 ;\n input \\rd_mux_sel_r_reg[1]_34 ;\n input \\rd_mux_sel_r_reg[1]_35 ;\n input \\rd_mux_sel_r_reg[1]_36 ;\n input \\rd_mux_sel_r_reg[1]_37 ;\n input \\rd_mux_sel_r_reg[1]_38 ;\n input \\rd_mux_sel_r_reg[1]_39 ;\n input \\rd_mux_sel_r_reg[1]_40 ;\n input \\rd_mux_sel_r_reg[1]_41 ;\n input \\rd_mux_sel_r_reg[1]_42 ;\n input \\rd_mux_sel_r_reg[1]_43 ;\n input \\rd_mux_sel_r_reg[1]_44 ;\n input \\rd_mux_sel_r_reg[1]_45 ;\n input \\rd_mux_sel_r_reg[1]_46 ;\n input \\rd_mux_sel_r_reg[1]_47 ;\n input \\rd_mux_sel_r_reg[1]_48 ;\n input \\rd_mux_sel_r_reg[1]_49 ;\n input \\rd_mux_sel_r_reg[1]_50 ;\n input \\rd_mux_sel_r_reg[1]_51 ;\n input \\rd_mux_sel_r_reg[1]_52 ;\n input \\rd_mux_sel_r_reg[1]_53 ;\n input \\rd_mux_sel_r_reg[1]_54 ;\n input \\rd_mux_sel_r_reg[1]_55 ;\n input \\rd_mux_sel_r_reg[1]_56 ;\n input \\rd_mux_sel_r_reg[1]_57 ;\n input \\rd_mux_sel_r_reg[1]_58 ;\n input \\rd_mux_sel_r_reg[1]_59 ;\n input \\rd_mux_sel_r_reg[1]_60 ;\n input \\rd_mux_sel_r_reg[1]_61 ;\n input \\rd_mux_sel_r_reg[1]_62 ;\n input \\rd_mux_sel_r_reg[1]_63 ;\n input mpr_rdlvl_start_reg;\n input rdlvl_stg1_start_reg;\n input phy_rddata_en_1;\n input dqs_po_dec_done;\n input rstdiv0_sync_r1_reg_rep__13;\n input samp_cnt_done_r_reg_0;\n input samp_cnt_done_r_reg_1;\n input samp_cnt_done_r_reg_2;\n input samp_cnt_done_r_reg_3;\n input samp_cnt_done_r_reg_4;\n input samp_cnt_done_r_reg_5;\n input samp_cnt_done_r_reg_6;\n input \\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg[0]_0 ;\n input mpr_rdlvl_done_r_reg_0;\n input store_sr_req_r_reg_1;\n input \\gen_track_left_edge[0].pb_detect_edge_done_r_reg[0]_0 ;\n input \\gen_track_left_edge[1].pb_detect_edge_done_r_reg[1]_0 ;\n input \\gen_track_left_edge[2].pb_detect_edge_done_r_reg[2]_0 ;\n input \\gen_track_left_edge[3].pb_detect_edge_done_r_reg[3]_0 ;\n input \\gen_track_left_edge[4].pb_detect_edge_done_r_reg[4]_0 ;\n input \\gen_track_left_edge[5].pb_detect_edge_done_r_reg[5]_0 ;\n input \\gen_track_left_edge[6].pb_detect_edge_done_r_reg[6]_0 ;\n input \\gen_track_left_edge[7].pb_detect_edge_done_r_reg[7]_0 ;\n input \\gen_track_left_edge[0].pb_found_edge_r_reg[0]_2 ;\n input \\gen_track_left_edge[1].pb_found_edge_r_reg[1]_1 ;\n input \\gen_track_left_edge[2].pb_found_edge_r_reg[2]_1 ;\n input \\gen_track_left_edge[3].pb_found_edge_r_reg[3]_1 ;\n input \\gen_track_left_edge[4].pb_found_edge_r_reg[4]_2 ;\n input \\gen_track_left_edge[5].pb_found_edge_r_reg[5]_1 ;\n input \\gen_track_left_edge[6].pb_found_edge_r_reg[6]_2 ;\n input \\gen_track_left_edge[7].pb_found_edge_r_reg[7]_2 ;\n input found_edge_r_reg_4;\n input found_stable_eye_r_reg_0;\n input \\FSM_sequential_cal1_state_r_reg[4]_0 ;\n input \\FSM_sequential_cal1_state_r_reg[3]_0 ;\n input \\FSM_sequential_cal1_state_r_reg[2]_0 ;\n input \\wait_cnt_r_reg[0]_1 ;\n input \\FSM_sequential_cal1_state_r_reg[4]_1 ;\n input \\FSM_sequential_cal1_state_r_reg[4]_2 ;\n input mpr_rdlvl_done_r_reg_1;\n input \\FSM_sequential_cal1_state_r_reg[4]_3 ;\n input \\FSM_sequential_cal1_state_r_reg[4]_4 ;\n input \\regl_dqs_cnt_reg[2]_0 ;\n input \\FSM_sequential_cal1_state_r_reg[1]_0 ;\n input [0:0]SR;\n input found_stable_eye_last_r_reg_1;\n input \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n input prbs_pi_stg2_f_incdec;\n input tempmon_pi_f_inc_r;\n input [0:0]Q;\n input prbs_pi_stg2_f_en;\n input tempmon_pi_f_en_r;\n input calib_in_common;\n input [2:0]\\calib_sel_reg[3] ;\n input \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n input \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n input \\gen_byte_sel_div1.calib_in_common_reg_3 ;\n input rstdiv0_sync_r1_reg_rep__24;\n input stg1_wr_done;\n input wrcal_done_reg;\n input dqs_found_done_r_reg;\n input [1:0]\\init_state_r_reg[1]_0 ;\n input oclkdelay_calib_done_r_reg;\n input \\one_rank.stg1_wr_done_reg ;\n input cal1_state_r1535_out;\n input rstdiv0_sync_r1_reg_rep__23;\n input [2:0]\\calib_sel_reg[3]_0 ;\n input \\po_stg2_wrcal_cnt_reg[0] ;\n input [0:0]\\po_stg2_wrcal_cnt_reg[1] ;\n input cal1_dq_idel_ce_reg_0;\n input prech_done;\n input [4:0]\\pi_counter_read_val_reg[5] ;\n input rstdiv0_sync_r1_reg_rep__20;\n input \\init_state_r_reg[3]_0 ;\n input wrcal_prech_req;\n input complex_ocal_ref_req;\n input prbs_rdlvl_prech_req_reg;\n input dqs_found_prech_req;\n input \\init_state_r_reg[5]_0 ;\n input wrlvl_done_r1_reg;\n input wrlvl_done_r1_reg_0;\n input cnt_init_af_done_r;\n input dqs_found_done_r_reg_0;\n input prbs_rdlvl_done_reg_rep;\n input wrlvl_byte_redo;\n input wrlvl_final_mux;\n input mem_init_done_r;\n input prbs_rdlvl_done_reg_rep_0;\n input \\num_refresh_reg[1] ;\n input prbs_last_byte_done_r;\n input wrlvl_final_mux_reg;\n input prbs_rdlvl_done_reg_rep_1;\n input oclkdelay_center_calib_done_r_reg;\n input wrlvl_done_r1;\n input wrlvl_byte_redo_reg;\n input \\dout_o_reg[6] ;\n input first_wrcal_pat_r;\n input \\dout_o_reg[6]_0 ;\n input prbs_rdlvl_done_reg;\n input wr_level_done_reg;\n input \\prbs_dqs_cnt_r_reg[2] ;\n input \\po_stg2_wrcal_cnt_reg[2] ;\n input [0:0]rdlvl_stg1_start_reg_0;\n input [0:0]E;\n input samp_edge_cnt0_en_r_reg_0;\n input [0:0]pi_cnt_dec_reg_1;\n input rstdiv0_sync_r1_reg_rep__2;\n\n wire CLK;\n wire [5:0]COUNTERLOADVAL;\n wire [1:0]D;\n wire [0:0]E;\n wire \\FSM_sequential_cal1_state_r[0]_i_11_n_0 ;\n wire \\FSM_sequential_cal1_state_r[0]_i_12_n_0 ;\n wire \\FSM_sequential_cal1_state_r[0]_i_14_n_0 ;\n wire \\FSM_sequential_cal1_state_r[0]_i_1_n_0 ;\n wire \\FSM_sequential_cal1_state_r[0]_i_2_n_0 ;\n wire \\FSM_sequential_cal1_state_r[0]_i_3_n_0 ;\n wire \\FSM_sequential_cal1_state_r[0]_i_4_n_0 ;\n wire \\FSM_sequential_cal1_state_r[0]_i_5_n_0 ;\n wire \\FSM_sequential_cal1_state_r[0]_i_6_n_0 ;\n wire \\FSM_sequential_cal1_state_r[0]_i_7_n_0 ;\n wire \\FSM_sequential_cal1_state_r[0]_i_8_n_0 ;\n wire \\FSM_sequential_cal1_state_r[0]_i_9_n_0 ;\n wire \\FSM_sequential_cal1_state_r[1]_i_10_n_0 ;\n wire \\FSM_sequential_cal1_state_r[1]_i_11_n_0 ;\n wire \\FSM_sequential_cal1_state_r[1]_i_12_n_0 ;\n wire \\FSM_sequential_cal1_state_r[1]_i_13_n_0 ;\n wire \\FSM_sequential_cal1_state_r[1]_i_1_n_0 ;\n wire \\FSM_sequential_cal1_state_r[1]_i_2_n_0 ;\n wire \\FSM_sequential_cal1_state_r[1]_i_3_n_0 ;\n wire \\FSM_sequential_cal1_state_r[1]_i_4_n_0 ;\n wire \\FSM_sequential_cal1_state_r[1]_i_6_n_0 ;\n wire \\FSM_sequential_cal1_state_r[1]_i_7_n_0 ;\n wire \\FSM_sequential_cal1_state_r[1]_i_8_n_0 ;\n wire \\FSM_sequential_cal1_state_r[1]_i_9_n_0 ;\n wire \\FSM_sequential_cal1_state_r[2]_i_1_n_0 ;\n wire \\FSM_sequential_cal1_state_r[2]_i_3_n_0 ;\n wire \\FSM_sequential_cal1_state_r[2]_i_4_n_0 ;\n wire \\FSM_sequential_cal1_state_r[2]_i_5_n_0 ;\n wire \\FSM_sequential_cal1_state_r[3]_i_1_n_0 ;\n wire \\FSM_sequential_cal1_state_r[3]_i_2_n_0 ;\n wire \\FSM_sequential_cal1_state_r[3]_i_3_n_0 ;\n wire \\FSM_sequential_cal1_state_r[4]_i_1_n_0 ;\n wire \\FSM_sequential_cal1_state_r[4]_i_2_n_0 ;\n wire \\FSM_sequential_cal1_state_r[4]_i_3_n_0 ;\n wire \\FSM_sequential_cal1_state_r[4]_i_4_n_0 ;\n wire \\FSM_sequential_cal1_state_r[4]_i_5_n_0 ;\n wire \\FSM_sequential_cal1_state_r[4]_i_6_n_0 ;\n wire \\FSM_sequential_cal1_state_r[4]_i_7_n_0 ;\n wire \\FSM_sequential_cal1_state_r[5]_i_11_n_0 ;\n wire \\FSM_sequential_cal1_state_r[5]_i_1_n_0 ;\n wire \\FSM_sequential_cal1_state_r[5]_i_2_n_0 ;\n wire \\FSM_sequential_cal1_state_r[5]_i_3_n_0 ;\n wire \\FSM_sequential_cal1_state_r[5]_i_4_n_0 ;\n wire \\FSM_sequential_cal1_state_r[5]_i_5_n_0 ;\n wire \\FSM_sequential_cal1_state_r[5]_i_6_n_0 ;\n wire \\FSM_sequential_cal1_state_r[5]_i_7_n_0 ;\n wire \\FSM_sequential_cal1_state_r[5]_i_8_n_0 ;\n wire \\FSM_sequential_cal1_state_r[5]_i_9_n_0 ;\n wire \\FSM_sequential_cal1_state_r_reg[1]_0 ;\n wire \\FSM_sequential_cal1_state_r_reg[1]_i_5_n_0 ;\n wire \\FSM_sequential_cal1_state_r_reg[2]_0 ;\n wire \\FSM_sequential_cal1_state_r_reg[2]_i_2_n_0 ;\n wire \\FSM_sequential_cal1_state_r_reg[3]_0 ;\n wire \\FSM_sequential_cal1_state_r_reg[4]_0 ;\n wire \\FSM_sequential_cal1_state_r_reg[4]_1 ;\n wire \\FSM_sequential_cal1_state_r_reg[4]_2 ;\n wire \\FSM_sequential_cal1_state_r_reg[4]_3 ;\n wire \\FSM_sequential_cal1_state_r_reg[4]_4 ;\n wire [0:0]Q;\n wire [0:0]SR;\n wire cal1_cnt_cpt_r1;\n wire \\cal1_cnt_cpt_r[0]_i_1_n_0 ;\n wire \\cal1_cnt_cpt_r[1]_i_2_n_0 ;\n wire \\cal1_cnt_cpt_r[1]_i_3_n_0 ;\n wire \\cal1_cnt_cpt_r[1]_i_4_n_0 ;\n wire \\cal1_cnt_cpt_r[1]_i_5_n_0 ;\n wire \\cal1_cnt_cpt_r_reg_n_0_[0] ;\n wire \\cal1_cnt_cpt_r_reg_n_0_[1] ;\n wire cal1_dlyce_cpt_r;\n wire cal1_dlyce_cpt_r_i_2_n_0;\n wire cal1_dlyce_cpt_r_reg_n_0;\n wire cal1_dlyinc_cpt_r;\n wire cal1_dlyinc_cpt_r_i_2_n_0;\n wire cal1_dlyinc_cpt_r_reg_n_0;\n wire cal1_dq_idel_ce;\n wire cal1_dq_idel_ce_reg_0;\n wire cal1_dq_idel_inc;\n wire cal1_prech_req_r;\n wire cal1_prech_req_r_reg_n_0;\n (* RTL_KEEP = \"yes\" *) wire [5:5]cal1_state_r;\n wire cal1_state_r1;\n wire cal1_state_r1533_out;\n wire cal1_state_r1535_out;\n wire \\cal1_state_r1[0]_i_1_n_0 ;\n wire \\cal1_state_r1[1]_i_1_n_0 ;\n wire \\cal1_state_r1[2]_i_1_n_0 ;\n wire \\cal1_state_r1[3]_i_1_n_0 ;\n wire \\cal1_state_r1[4]_i_1_n_0 ;\n wire \\cal1_state_r1[5]_i_1_n_0 ;\n wire \\cal1_state_r1_reg_n_0_[0] ;\n wire \\cal1_state_r1_reg_n_0_[1] ;\n wire \\cal1_state_r1_reg_n_0_[2] ;\n wire \\cal1_state_r1_reg_n_0_[3] ;\n wire \\cal1_state_r1_reg_n_0_[4] ;\n wire \\cal1_state_r1_reg_n_0_[5] ;\n wire cal1_state_r2;\n wire cal1_wait_cnt_en_r;\n wire cal1_wait_cnt_en_r0;\n wire \\cal1_wait_cnt_r[4]_i_1_n_0 ;\n wire [4:0]cal1_wait_cnt_r_reg__0;\n wire cal1_wait_r;\n wire cal1_wait_r_i_1_n_0;\n wire calib_in_common;\n wire [2:0]\\calib_sel_reg[3] ;\n wire [2:0]\\calib_sel_reg[3]_0 ;\n wire cmd_delay_start0;\n wire [5:0]cnt_idel_dec_cpt_r;\n wire [5:1]cnt_idel_dec_cpt_r2;\n wire \\cnt_idel_dec_cpt_r[0]_i_2_n_0 ;\n wire \\cnt_idel_dec_cpt_r[0]_i_3_n_0 ;\n wire \\cnt_idel_dec_cpt_r[1]_i_10_n_0 ;\n wire \\cnt_idel_dec_cpt_r[1]_i_11_n_0 ;\n wire \\cnt_idel_dec_cpt_r[1]_i_12_n_0 ;\n wire \\cnt_idel_dec_cpt_r[1]_i_13_n_0 ;\n wire \\cnt_idel_dec_cpt_r[1]_i_14_n_0 ;\n wire \\cnt_idel_dec_cpt_r[1]_i_3_n_0 ;\n wire \\cnt_idel_dec_cpt_r[1]_i_4_n_0 ;\n wire \\cnt_idel_dec_cpt_r[1]_i_5_n_0 ;\n wire \\cnt_idel_dec_cpt_r[1]_i_6_n_0 ;\n wire \\cnt_idel_dec_cpt_r[1]_i_7_n_0 ;\n wire \\cnt_idel_dec_cpt_r[1]_i_8_n_0 ;\n wire \\cnt_idel_dec_cpt_r[2]_i_2_n_0 ;\n wire \\cnt_idel_dec_cpt_r[2]_i_3_n_0 ;\n wire \\cnt_idel_dec_cpt_r[2]_i_4_n_0 ;\n wire \\cnt_idel_dec_cpt_r[2]_i_5_n_0 ;\n wire \\cnt_idel_dec_cpt_r[3]_i_2_n_0 ;\n wire \\cnt_idel_dec_cpt_r[3]_i_3_n_0 ;\n wire \\cnt_idel_dec_cpt_r[3]_i_4_n_0 ;\n wire \\cnt_idel_dec_cpt_r[3]_i_5_n_0 ;\n wire \\cnt_idel_dec_cpt_r[4]_i_3_n_0 ;\n wire \\cnt_idel_dec_cpt_r[4]_i_4_n_0 ;\n wire \\cnt_idel_dec_cpt_r[4]_i_5_n_0 ;\n wire \\cnt_idel_dec_cpt_r[4]_i_7_n_0 ;\n wire \\cnt_idel_dec_cpt_r[4]_i_8_n_0 ;\n wire \\cnt_idel_dec_cpt_r[4]_i_9_n_0 ;\n wire \\cnt_idel_dec_cpt_r[5]_i_10_n_0 ;\n wire \\cnt_idel_dec_cpt_r[5]_i_11_n_0 ;\n wire \\cnt_idel_dec_cpt_r[5]_i_12_n_0 ;\n wire \\cnt_idel_dec_cpt_r[5]_i_13_n_0 ;\n wire \\cnt_idel_dec_cpt_r[5]_i_1_n_0 ;\n wire \\cnt_idel_dec_cpt_r[5]_i_3_n_0 ;\n wire \\cnt_idel_dec_cpt_r[5]_i_5_n_0 ;\n wire \\cnt_idel_dec_cpt_r[5]_i_6_n_0 ;\n wire \\cnt_idel_dec_cpt_r[5]_i_7_n_0 ;\n wire \\cnt_idel_dec_cpt_r[5]_i_8_n_0 ;\n wire \\cnt_idel_dec_cpt_r_reg[0]_0 ;\n wire \\cnt_idel_dec_cpt_r_reg[1]_i_2_n_0 ;\n wire \\cnt_idel_dec_cpt_r_reg[1]_i_2_n_1 ;\n wire \\cnt_idel_dec_cpt_r_reg[1]_i_2_n_2 ;\n wire \\cnt_idel_dec_cpt_r_reg[1]_i_2_n_3 ;\n wire \\cnt_idel_dec_cpt_r_reg[1]_i_9_n_0 ;\n wire \\cnt_idel_dec_cpt_r_reg[1]_i_9_n_1 ;\n wire \\cnt_idel_dec_cpt_r_reg[1]_i_9_n_2 ;\n wire \\cnt_idel_dec_cpt_r_reg[1]_i_9_n_3 ;\n wire \\cnt_idel_dec_cpt_r_reg[1]_i_9_n_4 ;\n wire \\cnt_idel_dec_cpt_r_reg[1]_i_9_n_5 ;\n wire \\cnt_idel_dec_cpt_r_reg[1]_i_9_n_6 ;\n wire \\cnt_idel_dec_cpt_r_reg[4]_i_2_n_0 ;\n wire \\cnt_idel_dec_cpt_r_reg[4]_i_6_n_3 ;\n wire \\cnt_idel_dec_cpt_r_reg[4]_i_6_n_6 ;\n wire \\cnt_idel_dec_cpt_r_reg[4]_i_6_n_7 ;\n wire \\cnt_idel_dec_cpt_r_reg[5]_i_9_n_1 ;\n wire \\cnt_idel_dec_cpt_r_reg[5]_i_9_n_3 ;\n wire \\cnt_idel_dec_cpt_r_reg_n_0_[0] ;\n wire \\cnt_idel_dec_cpt_r_reg_n_0_[1] ;\n wire \\cnt_idel_dec_cpt_r_reg_n_0_[2] ;\n wire \\cnt_idel_dec_cpt_r_reg_n_0_[3] ;\n wire \\cnt_idel_dec_cpt_r_reg_n_0_[4] ;\n wire \\cnt_idel_dec_cpt_r_reg_n_0_[5] ;\n wire cnt_init_af_done_r;\n wire [3:0]cnt_shift_r_reg__0;\n wire complex_ocal_ref_req;\n wire detect_edge_done_r;\n wire detect_edge_done_r_i_1_n_0;\n wire detect_edge_done_r_i_2_n_0;\n wire [3:0]done_cnt;\n wire done_cnt1;\n wire \\done_cnt[0]_i_1_n_0 ;\n wire \\done_cnt[1]_i_1_n_0 ;\n wire \\done_cnt[2]_i_1_n_0 ;\n wire \\done_cnt[3]_i_1_n_0 ;\n wire \\done_cnt[3]_i_3_n_0 ;\n wire \\done_cnt[3]_i_4_n_0 ;\n wire \\dout_o_reg[6] ;\n wire \\dout_o_reg[6]_0 ;\n wire dqs_found_done_r_reg;\n wire dqs_found_done_r_reg_0;\n wire dqs_found_prech_req;\n wire dqs_po_dec_done;\n wire dqs_po_dec_done_r1;\n wire dqs_po_dec_done_r2;\n wire fine_dly_dec_done_r1;\n wire fine_dly_dec_done_r1_i_1_n_0;\n wire fine_dly_dec_done_r1_i_2_n_0;\n wire fine_dly_dec_done_r1_i_3_n_0;\n wire fine_dly_dec_done_r2;\n wire \\first_edge_taps_r[5]_i_1_n_0 ;\n wire \\first_edge_taps_r[5]_i_2_n_0 ;\n wire \\first_edge_taps_r_reg_n_0_[0] ;\n wire \\first_edge_taps_r_reg_n_0_[1] ;\n wire \\first_edge_taps_r_reg_n_0_[2] ;\n wire \\first_edge_taps_r_reg_n_0_[3] ;\n wire \\first_edge_taps_r_reg_n_0_[4] ;\n wire \\first_edge_taps_r_reg_n_0_[5] ;\n wire first_wrcal_pat_r;\n wire found_edge_r_i_1_n_0;\n wire found_edge_r_i_2_n_0;\n wire found_edge_r_reg_0;\n wire found_edge_r_reg_1;\n wire found_edge_r_reg_2;\n wire found_edge_r_reg_3;\n wire found_edge_r_reg_4;\n wire found_first_edge_r_reg_0;\n wire found_stable_eye_last_r;\n wire found_stable_eye_last_r_reg_0;\n wire found_stable_eye_last_r_reg_1;\n wire found_stable_eye_r_i_1_n_0;\n wire found_stable_eye_r_i_2_n_0;\n wire found_stable_eye_r_reg_0;\n wire \\gen_byte_sel_div1.byte_sel_cnt[2]_i_5_n_0 ;\n wire \\gen_byte_sel_div1.byte_sel_cnt[2]_i_8_n_0 ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[2] ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_0 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_1 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_2 ;\n wire \\gen_byte_sel_div1.calib_in_common_reg_3 ;\n wire \\gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ;\n wire \\gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ;\n wire \\gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ;\n wire \\gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ;\n wire \\gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ;\n wire \\gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ;\n wire \\gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ;\n wire \\gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ;\n wire \\gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ;\n wire \\gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ;\n wire \\gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ;\n wire \\gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3] ;\n wire \\gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ;\n wire \\gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4] ;\n wire \\gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ;\n wire \\gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ;\n wire \\gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ;\n wire \\gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ;\n wire \\gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ;\n wire \\gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ;\n wire \\gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ;\n wire \\gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ;\n wire \\gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ;\n wire \\gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7] ;\n wire \\gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0]_140 ;\n wire \\gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0]_132 ;\n wire \\gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0]_164 ;\n wire \\gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0]_172 ;\n wire \\gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0]_180 ;\n wire \\gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0]_148 ;\n wire \\gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0]_156 ;\n wire \\gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0]_188 ;\n wire \\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0]_68 ;\n wire \\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0]_108 ;\n wire \\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0]_124 ;\n wire \\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0]_100 ;\n wire \\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0]_92 ;\n wire \\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0]_76 ;\n wire \\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0]_84 ;\n wire \\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0]_116 ;\n wire \\gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1]_141 ;\n wire \\gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1]_133 ;\n wire \\gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1]_165 ;\n wire \\gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1]_173 ;\n wire \\gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1]_181 ;\n wire \\gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1]_149 ;\n wire \\gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1]_157 ;\n wire \\gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1]_189 ;\n wire \\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1]_69 ;\n wire \\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1]_109 ;\n wire \\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1]_125 ;\n wire \\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1]_101 ;\n wire \\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1]_93 ;\n wire \\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1]_77 ;\n wire \\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1]_85 ;\n wire \\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1]_117 ;\n wire \\gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2]_142 ;\n wire \\gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2]_134 ;\n wire \\gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2]_166 ;\n wire \\gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2]_174 ;\n wire \\gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2]_182 ;\n wire \\gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2]_150 ;\n wire \\gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2]_158 ;\n wire \\gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2]_190 ;\n wire \\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2]_70 ;\n wire \\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2]_110 ;\n wire \\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2]_126 ;\n wire \\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2]_102 ;\n wire \\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2]_94 ;\n wire \\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2]_78 ;\n wire \\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2]_86 ;\n wire \\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2]_118 ;\n wire \\gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3]_143 ;\n wire \\gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3]_135 ;\n wire \\gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3]_167 ;\n wire \\gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3]_175 ;\n wire \\gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3]_183 ;\n wire \\gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3]_151 ;\n wire \\gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3]_159 ;\n wire \\gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3]_191 ;\n wire \\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3]_71 ;\n wire \\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3]_111 ;\n wire \\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3]_127 ;\n wire \\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3]_103 ;\n wire \\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3]_95 ;\n wire \\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3]_79 ;\n wire \\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3]_87 ;\n wire \\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3]_119 ;\n wire \\gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4]_144 ;\n wire \\gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4]_136 ;\n wire \\gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4]_168 ;\n wire \\gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4]_176 ;\n wire \\gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4]_184 ;\n wire \\gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4]_152 ;\n wire \\gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4]_160 ;\n wire \\gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4]_192 ;\n wire \\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4]_72 ;\n wire \\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4]_112 ;\n wire \\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4]_128 ;\n wire \\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4]_104 ;\n wire \\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4]_96 ;\n wire \\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4]_80 ;\n wire \\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4]_88 ;\n wire \\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4]_120 ;\n wire \\gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5]_145 ;\n wire \\gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5]_137 ;\n wire \\gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5]_169 ;\n wire \\gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5]_177 ;\n wire \\gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5]_185 ;\n wire \\gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5]_153 ;\n wire \\gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5]_161 ;\n wire \\gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5]_193 ;\n wire \\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5]_73 ;\n wire \\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5]_113 ;\n wire \\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5]_129 ;\n wire \\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5]_105 ;\n wire \\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5]_97 ;\n wire \\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5]_81 ;\n wire \\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5]_89 ;\n wire \\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5]_121 ;\n wire \\gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6]_146 ;\n wire \\gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6]_138 ;\n wire \\gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6]_170 ;\n wire \\gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6]_178 ;\n wire \\gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6]_186 ;\n wire \\gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6]_154 ;\n wire \\gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6]_162 ;\n wire \\gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6]_194 ;\n wire \\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6]_74 ;\n wire \\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6]_114 ;\n wire \\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6]_130 ;\n wire \\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6]_106 ;\n wire \\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6]_98 ;\n wire \\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6]_82 ;\n wire \\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6]_90 ;\n wire \\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6]_122 ;\n wire \\gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7]_147 ;\n wire \\gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7]_139 ;\n wire \\gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7]_171 ;\n wire \\gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7]_179 ;\n wire \\gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7]_187 ;\n wire \\gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7]_155 ;\n wire \\gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7]_163 ;\n wire \\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0]_0 ;\n wire \\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7]_195 ;\n wire \\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7]_75 ;\n wire \\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7]_115 ;\n wire \\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7]_131 ;\n wire \\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7]_107 ;\n wire \\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7]_99 ;\n wire \\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7]_83 ;\n wire \\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7]_91 ;\n wire \\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7]_123 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.idel_pat0_data_match_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ;\n wire \\gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.idel_pat1_data_match_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ;\n wire \\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat0_data_match_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ;\n wire \\gen_pat_match_div4.pat0_match_fall0_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat0_match_fall0_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat0_match_fall1_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat0_match_fall1_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat0_match_fall2_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat0_match_fall3_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat0_match_rise0_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat0_match_rise1_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat0_match_rise2_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat0_match_rise2_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat0_match_rise3_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat1_data_match_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ;\n wire \\gen_pat_match_div4.pat1_match_fall0_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat1_match_fall1_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat1_match_fall2_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat1_match_fall2_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat1_match_fall3_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat1_match_fall3_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat1_match_rise0_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat1_match_rise1_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat1_match_rise2_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat1_match_rise3_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_52 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_36 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_20 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_12 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_4 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_44 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_28 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_60 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_53 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_37 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_21 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_13 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_5 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_45 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_29 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_61 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_54 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_38 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_22 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_14 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_6 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_46 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_30 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_62 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_55 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_39 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_23 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_15 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_7 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_47 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_31 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_63 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_56 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_40 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_24 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_16 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_8 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_48 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_32 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_64 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_57 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_41 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_25 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_17 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_9 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_49 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_33 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_65 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_58 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_42 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_26 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_18 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_10 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_50 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_34 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_66 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_59 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_43 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_27 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_19 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_11 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_51 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_35 ;\n wire \\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_67 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0] ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0] ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0] ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0] ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0] ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0] ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0] ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0] ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0] ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg[0]_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0] ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0] ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0] ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0] ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0] ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0] ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0] ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0] ;\n wire \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7] ;\n wire \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r_reg_n_0_[7] ;\n wire \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg_n_0_[7] ;\n wire \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg_n_0_[7] ;\n wire \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r_reg_n_0_[7] ;\n wire \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1_n_0 ;\n wire \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1_n_0 ;\n wire \\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ;\n wire \\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0 ;\n wire \\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0 ;\n wire [4:0]\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 ;\n wire \\gen_track_left_edge[0].pb_detect_edge_done_r_reg[0]_0 ;\n wire \\gen_track_left_edge[0].pb_found_edge_r_reg[0]_0 ;\n wire \\gen_track_left_edge[0].pb_found_edge_r_reg[0]_1 ;\n wire \\gen_track_left_edge[0].pb_found_edge_r_reg[0]_2 ;\n wire \\gen_track_left_edge[0].pb_found_stable_eye_r_reg ;\n wire \\gen_track_left_edge[0].pb_found_stable_eye_r_reg[0]_0 ;\n wire \\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1_n_0 ;\n wire \\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_0 ;\n wire \\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 ;\n wire \\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ;\n wire \\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ;\n wire \\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0 ;\n wire \\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0 ;\n wire [4:0]\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 ;\n wire \\gen_track_left_edge[1].pb_detect_edge_done_r_reg[1]_0 ;\n wire \\gen_track_left_edge[1].pb_found_edge_r_reg[1]_0 ;\n wire \\gen_track_left_edge[1].pb_found_edge_r_reg[1]_1 ;\n wire \\gen_track_left_edge[1].pb_found_stable_eye_r_reg ;\n wire \\gen_track_left_edge[1].pb_found_stable_eye_r_reg[1]_0 ;\n wire \\gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1_n_0 ;\n wire \\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ;\n wire \\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ;\n wire \\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0 ;\n wire \\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0 ;\n wire [4:0]\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 ;\n wire \\gen_track_left_edge[2].pb_detect_edge_done_r_reg[2]_0 ;\n wire \\gen_track_left_edge[2].pb_found_edge_r_reg[2]_0 ;\n wire \\gen_track_left_edge[2].pb_found_edge_r_reg[2]_1 ;\n wire \\gen_track_left_edge[2].pb_found_stable_eye_r_reg ;\n wire \\gen_track_left_edge[2].pb_found_stable_eye_r_reg[2]_0 ;\n wire \\gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1_n_0 ;\n wire \\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ;\n wire \\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ;\n wire \\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0 ;\n wire \\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0 ;\n wire [4:0]\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 ;\n wire \\gen_track_left_edge[3].pb_detect_edge_done_r_reg[3]_0 ;\n wire \\gen_track_left_edge[3].pb_found_edge_r_reg[3]_0 ;\n wire \\gen_track_left_edge[3].pb_found_edge_r_reg[3]_1 ;\n wire \\gen_track_left_edge[3].pb_found_stable_eye_r_reg ;\n wire \\gen_track_left_edge[3].pb_found_stable_eye_r_reg[3]_0 ;\n wire \\gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1_n_0 ;\n wire \\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ;\n wire \\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ;\n wire \\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0 ;\n wire \\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0 ;\n wire [4:0]\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 ;\n wire \\gen_track_left_edge[4].pb_detect_edge_done_r_reg[4]_0 ;\n wire \\gen_track_left_edge[4].pb_found_edge_r_reg[4]_0 ;\n wire \\gen_track_left_edge[4].pb_found_edge_r_reg[4]_1 ;\n wire \\gen_track_left_edge[4].pb_found_edge_r_reg[4]_2 ;\n wire \\gen_track_left_edge[4].pb_found_stable_eye_r_reg ;\n wire \\gen_track_left_edge[4].pb_found_stable_eye_r_reg[4]_0 ;\n wire \\gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1_n_0 ;\n wire \\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ;\n wire \\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ;\n wire \\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0 ;\n wire \\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0 ;\n wire [4:0]\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 ;\n wire \\gen_track_left_edge[5].pb_detect_edge_done_r_reg[5]_0 ;\n wire \\gen_track_left_edge[5].pb_found_edge_r_reg[5]_0 ;\n wire \\gen_track_left_edge[5].pb_found_edge_r_reg[5]_1 ;\n wire \\gen_track_left_edge[5].pb_found_stable_eye_r_reg ;\n wire \\gen_track_left_edge[5].pb_found_stable_eye_r_reg[5]_0 ;\n wire \\gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1_n_0 ;\n wire \\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ;\n wire \\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ;\n wire \\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0 ;\n wire \\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0 ;\n wire [4:0]\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 ;\n wire \\gen_track_left_edge[6].pb_detect_edge_done_r_reg[6]_0 ;\n wire \\gen_track_left_edge[6].pb_found_edge_r_reg[6]_0 ;\n wire \\gen_track_left_edge[6].pb_found_edge_r_reg[6]_1 ;\n wire \\gen_track_left_edge[6].pb_found_edge_r_reg[6]_2 ;\n wire \\gen_track_left_edge[6].pb_found_stable_eye_r_reg ;\n wire \\gen_track_left_edge[6].pb_found_stable_eye_r_reg[6]_0 ;\n wire \\gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1_n_0 ;\n wire \\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ;\n wire \\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ;\n wire \\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0 ;\n wire \\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0 ;\n wire [4:0]\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 ;\n wire \\gen_track_left_edge[7].pb_detect_edge_done_r_reg[7]_0 ;\n wire \\gen_track_left_edge[7].pb_found_edge_r_reg[7]_0 ;\n wire \\gen_track_left_edge[7].pb_found_edge_r_reg[7]_1 ;\n wire \\gen_track_left_edge[7].pb_found_edge_r_reg[7]_2 ;\n wire \\gen_track_left_edge[7].pb_found_stable_eye_r_reg ;\n wire \\gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_0 ;\n wire \\gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_1 ;\n wire \\gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1_n_0 ;\n wire \\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ;\n wire \\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ;\n wire idel_adj_inc_reg_0;\n wire idel_adj_inc_reg_1;\n wire idel_adj_inc_reg_2;\n wire [0:0]idel_dec_cnt;\n wire \\idel_dec_cnt[0]_i_2_n_0 ;\n wire \\idel_dec_cnt[1]_i_1_n_0 ;\n wire \\idel_dec_cnt[2]_i_1_n_0 ;\n wire \\idel_dec_cnt[3]_i_1_n_0 ;\n wire \\idel_dec_cnt[3]_i_2_n_0 ;\n wire \\idel_dec_cnt[4]_i_1_n_0 ;\n wire \\idel_dec_cnt[4]_i_2_n_0 ;\n wire \\idel_dec_cnt[4]_i_4_n_0 ;\n wire \\idel_dec_cnt[4]_i_5_n_0 ;\n wire \\idel_dec_cnt[4]_i_7_n_0 ;\n wire \\idel_dec_cnt[4]_i_8_n_0 ;\n wire \\idel_dec_cnt[4]_i_9_n_0 ;\n wire [4:0]idel_dec_cnt__0;\n wire \\idel_dec_cnt_reg[0]_0 ;\n wire idel_mpr_pat_detect_r;\n wire idel_pat0_data_match_r0__0;\n wire idel_pat0_match_fall0_and_r;\n wire idel_pat0_match_fall1_and_r;\n wire idel_pat0_match_fall2_and_r;\n wire idel_pat0_match_fall3_and_r;\n wire idel_pat0_match_rise0_and_r;\n wire idel_pat0_match_rise1_and_r;\n wire idel_pat0_match_rise2_and_r;\n wire idel_pat0_match_rise3_and_r;\n wire idel_pat1_data_match_r0__0;\n wire idel_pat1_match_fall0_and_r;\n wire idel_pat1_match_fall1_and_r;\n wire idel_pat1_match_fall2_and_r;\n wire idel_pat1_match_fall3_and_r;\n wire idel_pat1_match_rise0_and_r;\n wire idel_pat1_match_rise1_and_r;\n wire idel_pat1_match_rise2_and_r;\n wire idel_pat1_match_rise3_and_r;\n wire idelay_ce_int;\n wire idelay_inc_int;\n wire [4:0]idelay_tap_cnt_r;\n wire \\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ;\n wire \\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ;\n wire \\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ;\n wire \\idelay_tap_cnt_r[0][0][3]_i_1_n_0 ;\n wire \\idelay_tap_cnt_r[0][0][3]_i_2_n_0 ;\n wire \\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ;\n wire \\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ;\n wire \\idelay_tap_cnt_r[0][0][4]_i_4_n_0 ;\n wire \\idelay_tap_cnt_r[0][0][4]_i_5_n_0 ;\n wire \\idelay_tap_cnt_r[0][1][4]_i_1_n_0 ;\n wire \\idelay_tap_cnt_r[0][2][4]_i_1_n_0 ;\n wire \\idelay_tap_cnt_r[0][3][4]_i_1_n_0 ;\n wire \\idelay_tap_cnt_r[0][3][4]_i_2_n_0 ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][0][0] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][0][1] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][0][2] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][0][3] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][0][4] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][1][0] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][1][1] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][1][2] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][1][3] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][1][4] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][2][0] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][2][1] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][2][2] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][2][3] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][2][4] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][3][0] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][3][1] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][3][2] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][3][3] ;\n wire \\idelay_tap_cnt_r_reg_n_0_[0][3][4] ;\n wire [4:0]idelay_tap_cnt_slice_r;\n wire idelay_tap_limit_r_i_1_n_0;\n wire idelay_tap_limit_r_i_2_n_0;\n wire idelay_tap_limit_r_reg_n_0;\n wire inhibit_edge_detect_r;\n wire inhibit_edge_detect_r0;\n wire \\init_state_r[0]_i_48_n_0 ;\n wire \\init_state_r[0]_i_49_n_0 ;\n wire \\init_state_r[0]_i_53_n_0 ;\n wire \\init_state_r[0]_i_54_n_0 ;\n wire \\init_state_r_reg[0] ;\n wire \\init_state_r_reg[0]_0 ;\n wire \\init_state_r_reg[0]_1 ;\n wire \\init_state_r_reg[0]_2 ;\n wire \\init_state_r_reg[0]_3 ;\n wire \\init_state_r_reg[0]_4 ;\n wire \\init_state_r_reg[1] ;\n wire [1:0]\\init_state_r_reg[1]_0 ;\n wire \\init_state_r_reg[2] ;\n wire \\init_state_r_reg[2]_0 ;\n wire \\init_state_r_reg[2]_1 ;\n wire \\init_state_r_reg[2]_2 ;\n wire \\init_state_r_reg[3] ;\n wire \\init_state_r_reg[3]_0 ;\n wire \\init_state_r_reg[4] ;\n wire \\init_state_r_reg[5] ;\n wire \\init_state_r_reg[5]_0 ;\n wire mem_init_done_r;\n wire \\mpr_4to1.idel_mpr_pat_detect_r_i_1_n_0 ;\n wire \\mpr_4to1.idel_mpr_pat_detect_r_i_2_n_0 ;\n wire \\mpr_4to1.idel_mpr_pat_detect_r_i_3_n_0 ;\n wire \\mpr_4to1.inhibit_edge_detect_r_i_1_n_0 ;\n wire \\mpr_4to1.inhibit_edge_detect_r_i_2_n_0 ;\n wire \\mpr_4to1.inhibit_edge_detect_r_i_3_n_0 ;\n wire \\mpr_4to1.inhibit_edge_detect_r_i_4_n_0 ;\n wire \\mpr_4to1.inhibit_edge_detect_r_i_6_n_0 ;\n wire \\mpr_4to1.inhibit_edge_detect_r_i_7_n_0 ;\n wire \\mpr_4to1.stable_idel_cnt[0]_i_1_n_0 ;\n wire \\mpr_4to1.stable_idel_cnt[1]_i_1_n_0 ;\n wire \\mpr_4to1.stable_idel_cnt[2]_i_1_n_0 ;\n wire \\mpr_4to1.stable_idel_cnt[2]_i_4_n_0 ;\n wire \\mpr_4to1.stable_idel_cnt[2]_i_5_n_0 ;\n wire \\mpr_4to1.stable_idel_cnt[2]_i_6_n_0 ;\n wire \\mpr_4to1.stable_idel_cnt[2]_i_7_n_0 ;\n wire \\mpr_4to1.stable_idel_cnt[2]_i_8_n_0 ;\n wire \\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ;\n wire \\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ;\n wire \\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ;\n wire mpr_dec_cpt_r_reg_0;\n wire mpr_dec_cpt_r_reg_1;\n wire mpr_last_byte_done;\n wire mpr_last_byte_done_reg_0;\n wire mpr_rank_done_r_reg_0;\n wire mpr_rank_done_r_reg_1;\n wire mpr_rd_fall0_prev_r;\n wire mpr_rd_fall1_prev_r;\n wire mpr_rd_fall2_prev_r;\n wire mpr_rd_fall3_prev_r;\n wire mpr_rd_rise0_prev_r;\n wire mpr_rd_rise0_prev_r0;\n wire mpr_rd_rise0_prev_r_reg_0;\n wire mpr_rd_rise0_prev_r_reg_1;\n wire mpr_rd_rise1_prev_r;\n wire mpr_rd_rise2_prev_r;\n wire mpr_rd_rise3_prev_r;\n wire mpr_rdlvl_done_r1;\n wire mpr_rdlvl_done_r1_reg_0;\n wire mpr_rdlvl_done_r2;\n wire mpr_rdlvl_done_r_reg_0;\n wire mpr_rdlvl_done_r_reg_1;\n wire mpr_rdlvl_start_r;\n wire mpr_rdlvl_start_reg;\n wire mpr_rnk_done;\n wire mpr_valid_r;\n wire mpr_valid_r1;\n wire mpr_valid_r1_reg_0;\n wire mpr_valid_r2;\n wire mpr_valid_r_reg_0;\n wire new_cnt_cpt_r;\n wire new_cnt_cpt_r82_out;\n wire new_cnt_cpt_r_i_2_n_0;\n wire new_cnt_cpt_r_reg_n_0;\n wire \\num_refresh_reg[1] ;\n wire oclkdelay_calib_done_r_reg;\n wire oclkdelay_center_calib_done_r_reg;\n wire \\one_rank.stg1_wr_done_reg ;\n (* RTL_KEEP = \"yes\" *) wire [4:0]out;\n wire p_0_in;\n wire p_0_in102_in;\n wire p_0_in10_in;\n wire p_0_in134_in;\n wire p_0_in13_in;\n wire p_0_in155_in;\n wire p_0_in16_in;\n wire p_0_in180_in;\n wire p_0_in1_in;\n wire p_0_in205_in;\n wire p_0_in230_in;\n wire p_0_in255_in;\n wire p_0_in280_in;\n wire p_0_in305_in;\n wire p_0_in330_in;\n wire p_0_in355_in;\n wire p_0_in380_in;\n wire p_0_in405_in;\n wire p_0_in430_in;\n wire p_0_in455_in;\n wire p_0_in4_in;\n wire p_0_in539_in;\n wire p_0_in7_in;\n wire p_0_in84_in;\n wire p_0_in87_in;\n wire p_0_in90_in;\n wire p_0_in93_in;\n wire p_0_in96_in;\n wire p_0_in99_in;\n wire [5:2]p_0_in__0;\n wire [4:0]p_0_in__0__0;\n wire [3:0]p_0_in__1;\n wire [4:0]p_0_in__2;\n wire [4:0]p_0_in__3;\n wire [4:0]p_0_in__4;\n wire [4:0]p_0_in__5;\n wire [4:0]p_0_in__6;\n wire [4:0]p_0_in__7;\n wire [4:0]p_0_in__8;\n wire [4:0]p_0_in__9;\n wire p_137_out__0;\n wire p_163_out__0;\n wire p_188_out__0;\n wire p_1_in11_in;\n wire p_1_in14_in;\n wire p_1_in162_in;\n wire p_1_in17_in;\n wire p_1_in187_in;\n wire p_1_in212_in;\n wire p_1_in237_in;\n wire p_1_in262_in;\n wire p_1_in26_in;\n wire p_1_in287_in;\n wire p_1_in2_in;\n wire p_1_in312_in;\n wire p_1_in337_in;\n wire p_1_in362_in;\n wire p_1_in387_in;\n wire p_1_in412_in;\n wire p_1_in437_in;\n wire p_1_in462_in;\n wire p_1_in5_in;\n wire p_1_in8_in;\n wire p_213_out__0;\n wire p_238_out__0;\n wire p_263_out__0;\n wire p_288_out__0;\n wire p_2_in156_in;\n wire p_2_in181_in;\n wire p_2_in206_in;\n wire p_2_in231_in;\n wire p_2_in256_in;\n wire p_2_in281_in;\n wire p_2_in306_in;\n wire p_2_in331_in;\n wire p_2_in356_in;\n wire p_2_in381_in;\n wire p_2_in406_in;\n wire p_2_in431_in;\n wire p_2_in456_in;\n wire p_313_out__0;\n wire p_338_out__0;\n wire p_363_out__0;\n wire p_388_out__0;\n wire p_3_in135_in;\n wire p_3_in157_in;\n wire p_3_in182_in;\n wire p_3_in207_in;\n wire p_3_in232_in;\n wire p_3_in257_in;\n wire p_3_in282_in;\n wire p_3_in307_in;\n wire p_3_in332_in;\n wire p_3_in357_in;\n wire p_3_in382_in;\n wire p_3_in407_in;\n wire p_3_in432_in;\n wire p_3_in457_in;\n wire p_413_out__0;\n wire p_438_out__0;\n wire p_463_out__0;\n wire p_488_out__0;\n wire p_4_in158_in;\n wire p_4_in183_in;\n wire p_4_in208_in;\n wire p_4_in233_in;\n wire p_4_in258_in;\n wire p_4_in283_in;\n wire p_4_in308_in;\n wire p_4_in333_in;\n wire p_4_in358_in;\n wire p_4_in383_in;\n wire p_4_in408_in;\n wire p_4_in433_in;\n wire p_4_in458_in;\n wire p_513_out__0;\n wire p_5_in136_in;\n wire p_5_in159_in;\n wire p_5_in184_in;\n wire p_5_in209_in;\n wire p_5_in234_in;\n wire p_5_in259_in;\n wire p_5_in284_in;\n wire p_5_in309_in;\n wire p_5_in334_in;\n wire p_5_in359_in;\n wire p_5_in384_in;\n wire p_5_in409_in;\n wire p_5_in434_in;\n wire p_5_in459_in;\n wire p_6_in160_in;\n wire p_6_in185_in;\n wire p_6_in210_in;\n wire p_6_in235_in;\n wire p_6_in260_in;\n wire p_6_in285_in;\n wire p_6_in310_in;\n wire p_6_in335_in;\n wire p_6_in360_in;\n wire p_6_in385_in;\n wire p_6_in410_in;\n wire p_6_in435_in;\n wire p_6_in460_in;\n wire p_7_in;\n wire p_7_in161_in;\n wire p_7_in186_in;\n wire p_7_in211_in;\n wire p_7_in236_in;\n wire p_7_in261_in;\n wire p_7_in286_in;\n wire p_7_in311_in;\n wire p_7_in336_in;\n wire p_7_in361_in;\n wire p_7_in386_in;\n wire p_7_in411_in;\n wire p_7_in436_in;\n wire p_7_in461_in;\n wire pat0_data_match_r0__0;\n wire pat0_match_fall0_and_r;\n wire pat0_match_fall1_and_r;\n wire pat0_match_fall2_and_r;\n wire pat0_match_fall3_and_r;\n wire pat0_match_rise0_and_r;\n wire pat0_match_rise1_and_r;\n wire pat0_match_rise2_and_r;\n wire pat0_match_rise3_and_r;\n wire pat1_data_match_r0__0;\n wire pat1_match_fall0_and_r;\n wire pat1_match_fall1_and_r;\n wire pat1_match_fall2_and_r;\n wire pat1_match_fall3_and_r;\n wire pat1_match_rise0_and_r;\n wire pat1_match_rise1_and_r;\n wire pat1_match_rise2_and_r;\n wire pat1_match_rise3_and_r;\n wire pb_cnt_eye_size_r;\n wire pb_detect_edge;\n wire [7:0]pb_detect_edge_done_r;\n wire pb_detect_edge_setup;\n wire pb_found_stable_eye_r52_out;\n wire pb_found_stable_eye_r56_out;\n wire pb_found_stable_eye_r60_out;\n wire pb_found_stable_eye_r64_out;\n wire pb_found_stable_eye_r68_out;\n wire pb_found_stable_eye_r72_out;\n wire pb_found_stable_eye_r76_out;\n wire phy_rddata_en_1;\n wire pi_cnt_dec_reg_0;\n wire [0:0]pi_cnt_dec_reg_1;\n wire pi_counter_load_en;\n wire [5:0]pi_counter_load_val;\n wire [4:0]\\pi_counter_read_val_reg[5] ;\n wire \\pi_dqs_found_lanes_r1_reg[0] ;\n wire \\pi_dqs_found_lanes_r1_reg[0]_0 ;\n wire \\pi_dqs_found_lanes_r1_reg[0]_1 ;\n wire \\pi_dqs_found_lanes_r1_reg[1] ;\n wire \\pi_dqs_found_lanes_r1_reg[1]_0 ;\n wire \\pi_dqs_found_lanes_r1_reg[1]_1 ;\n wire [5:0]\\pi_dqs_found_lanes_r1_reg[1]_2 ;\n wire \\pi_dqs_found_lanes_r1_reg[2] ;\n wire \\pi_dqs_found_lanes_r1_reg[2]_0 ;\n wire \\pi_dqs_found_lanes_r1_reg[2]_1 ;\n wire [5:0]\\pi_dqs_found_lanes_r1_reg[2]_2 ;\n wire \\pi_dqs_found_lanes_r1_reg[3] ;\n wire \\pi_dqs_found_lanes_r1_reg[3]_0 ;\n wire \\pi_dqs_found_lanes_r1_reg[3]_1 ;\n wire [5:0]\\pi_dqs_found_lanes_r1_reg[3]_2 ;\n wire pi_en_stg2_f_timing;\n wire pi_en_stg2_f_timing_i_1_n_0;\n wire pi_en_stg2_f_timing_reg_0;\n wire pi_fine_dly_dec_done;\n wire [5:0]pi_rdval_cnt;\n wire \\pi_rdval_cnt[0]_i_1_n_0 ;\n wire \\pi_rdval_cnt[1]_i_1_n_0 ;\n wire \\pi_rdval_cnt[2]_i_1_n_0 ;\n wire \\pi_rdval_cnt[3]_i_1_n_0 ;\n wire \\pi_rdval_cnt[3]_i_2_n_0 ;\n wire \\pi_rdval_cnt[4]_i_1_n_0 ;\n wire \\pi_rdval_cnt[4]_i_2_n_0 ;\n wire \\pi_rdval_cnt[5]_i_1_n_0 ;\n wire \\pi_rdval_cnt[5]_i_2_n_0 ;\n wire \\pi_rdval_cnt[5]_i_4_n_0 ;\n wire \\pi_rdval_cnt[5]_i_5_n_0 ;\n wire \\pi_rdval_cnt_reg[1]_0 ;\n wire pi_stg2_f_incdec_timing;\n wire pi_stg2_f_incdec_timing0;\n wire pi_stg2_load_timing;\n wire [1:0]pi_stg2_rdlvl_cnt;\n wire [5:0]pi_stg2_reg_l_timing;\n wire \\pi_stg2_reg_l_timing[0]_i_1_n_0 ;\n wire \\pi_stg2_reg_l_timing[1]_i_1_n_0 ;\n wire \\pi_stg2_reg_l_timing[2]_i_1_n_0 ;\n wire \\pi_stg2_reg_l_timing[3]_i_1_n_0 ;\n wire \\pi_stg2_reg_l_timing[4]_i_1_n_0 ;\n wire \\pi_stg2_reg_l_timing[5]_i_1_n_0 ;\n wire \\pi_stg2_reg_l_timing[5]_i_2_n_0 ;\n wire \\pi_stg2_reg_l_timing_reg[0]_0 ;\n wire \\po_stg2_wrcal_cnt_reg[0] ;\n wire [0:0]\\po_stg2_wrcal_cnt_reg[1] ;\n wire \\po_stg2_wrcal_cnt_reg[2] ;\n wire \\prbs_dqs_cnt_r_reg[2] ;\n wire prbs_last_byte_done_r;\n wire prbs_pi_stg2_f_en;\n wire prbs_pi_stg2_f_incdec;\n wire prbs_rdlvl_done_reg;\n wire prbs_rdlvl_done_reg_rep;\n wire prbs_rdlvl_done_reg_rep_0;\n wire prbs_rdlvl_done_reg_rep_1;\n wire prbs_rdlvl_prech_req_reg;\n wire prech_done;\n wire prech_req;\n wire \\rd_mux_sel_r_reg[1]_0 ;\n wire \\rd_mux_sel_r_reg[1]_1 ;\n wire \\rd_mux_sel_r_reg[1]_10 ;\n wire \\rd_mux_sel_r_reg[1]_11 ;\n wire \\rd_mux_sel_r_reg[1]_12 ;\n wire \\rd_mux_sel_r_reg[1]_13 ;\n wire \\rd_mux_sel_r_reg[1]_14 ;\n wire \\rd_mux_sel_r_reg[1]_15 ;\n wire \\rd_mux_sel_r_reg[1]_16 ;\n wire \\rd_mux_sel_r_reg[1]_17 ;\n wire \\rd_mux_sel_r_reg[1]_18 ;\n wire \\rd_mux_sel_r_reg[1]_19 ;\n wire \\rd_mux_sel_r_reg[1]_2 ;\n wire \\rd_mux_sel_r_reg[1]_20 ;\n wire \\rd_mux_sel_r_reg[1]_21 ;\n wire \\rd_mux_sel_r_reg[1]_22 ;\n wire \\rd_mux_sel_r_reg[1]_23 ;\n wire \\rd_mux_sel_r_reg[1]_24 ;\n wire \\rd_mux_sel_r_reg[1]_25 ;\n wire \\rd_mux_sel_r_reg[1]_26 ;\n wire \\rd_mux_sel_r_reg[1]_27 ;\n wire \\rd_mux_sel_r_reg[1]_28 ;\n wire \\rd_mux_sel_r_reg[1]_29 ;\n wire \\rd_mux_sel_r_reg[1]_3 ;\n wire \\rd_mux_sel_r_reg[1]_30 ;\n wire \\rd_mux_sel_r_reg[1]_31 ;\n wire \\rd_mux_sel_r_reg[1]_32 ;\n wire \\rd_mux_sel_r_reg[1]_33 ;\n wire \\rd_mux_sel_r_reg[1]_34 ;\n wire \\rd_mux_sel_r_reg[1]_35 ;\n wire \\rd_mux_sel_r_reg[1]_36 ;\n wire \\rd_mux_sel_r_reg[1]_37 ;\n wire \\rd_mux_sel_r_reg[1]_38 ;\n wire \\rd_mux_sel_r_reg[1]_39 ;\n wire \\rd_mux_sel_r_reg[1]_4 ;\n wire \\rd_mux_sel_r_reg[1]_40 ;\n wire \\rd_mux_sel_r_reg[1]_41 ;\n wire \\rd_mux_sel_r_reg[1]_42 ;\n wire \\rd_mux_sel_r_reg[1]_43 ;\n wire \\rd_mux_sel_r_reg[1]_44 ;\n wire \\rd_mux_sel_r_reg[1]_45 ;\n wire \\rd_mux_sel_r_reg[1]_46 ;\n wire \\rd_mux_sel_r_reg[1]_47 ;\n wire \\rd_mux_sel_r_reg[1]_48 ;\n wire \\rd_mux_sel_r_reg[1]_49 ;\n wire \\rd_mux_sel_r_reg[1]_5 ;\n wire \\rd_mux_sel_r_reg[1]_50 ;\n wire \\rd_mux_sel_r_reg[1]_51 ;\n wire \\rd_mux_sel_r_reg[1]_52 ;\n wire \\rd_mux_sel_r_reg[1]_53 ;\n wire \\rd_mux_sel_r_reg[1]_54 ;\n wire \\rd_mux_sel_r_reg[1]_55 ;\n wire \\rd_mux_sel_r_reg[1]_56 ;\n wire \\rd_mux_sel_r_reg[1]_57 ;\n wire \\rd_mux_sel_r_reg[1]_58 ;\n wire \\rd_mux_sel_r_reg[1]_59 ;\n wire \\rd_mux_sel_r_reg[1]_6 ;\n wire \\rd_mux_sel_r_reg[1]_60 ;\n wire \\rd_mux_sel_r_reg[1]_61 ;\n wire \\rd_mux_sel_r_reg[1]_62 ;\n wire \\rd_mux_sel_r_reg[1]_63 ;\n wire \\rd_mux_sel_r_reg[1]_7 ;\n wire \\rd_mux_sel_r_reg[1]_8 ;\n wire \\rd_mux_sel_r_reg[1]_9 ;\n wire \\rdlvl_cpt_tap_cnt_reg[1] ;\n wire \\rdlvl_cpt_tap_cnt_reg[2] ;\n wire \\rdlvl_cpt_tap_cnt_reg[4] ;\n wire rdlvl_dqs_tap_cnt_r;\n wire \\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ;\n wire \\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ;\n wire \\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ;\n wire \\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ;\n wire [1:0]\\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][0] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][1] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][2] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][3] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][4] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][5] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][0] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][1] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][2] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][3] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][4] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][5] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][0] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][1] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][2] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][3] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][4] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][5] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][0] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][1] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][2] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][3] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][4] ;\n wire \\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][5] ;\n wire rdlvl_last_byte_done;\n wire rdlvl_pi_incdec;\n wire rdlvl_pi_incdec_i_4_n_0;\n wire rdlvl_pi_incdec_i_5_n_0;\n wire rdlvl_pi_incdec_i_6_n_0;\n wire rdlvl_pi_incdec_reg_0;\n wire rdlvl_pi_incdec_reg_1;\n wire rdlvl_pi_stg2_f_en;\n wire rdlvl_pi_stg2_f_incdec;\n wire rdlvl_prech_req;\n wire rdlvl_rank_done_r_reg_0;\n wire rdlvl_stg1_done_int;\n wire rdlvl_stg1_done_r1_reg;\n wire rdlvl_stg1_rank_done;\n wire rdlvl_stg1_start_r;\n wire rdlvl_stg1_start_reg;\n wire [0:0]rdlvl_stg1_start_reg_0;\n wire [1:0]regl_dqs_cnt;\n wire \\regl_dqs_cnt[0]_i_1_n_0 ;\n wire \\regl_dqs_cnt[1]_i_1_n_0 ;\n wire \\regl_dqs_cnt[1]_i_2_n_0 ;\n wire \\regl_dqs_cnt[2]_i_1_n_0 ;\n wire [2:0]regl_dqs_cnt_r;\n wire [0:0]\\regl_dqs_cnt_r_reg[2]_0 ;\n wire \\regl_dqs_cnt_reg[0]_0 ;\n wire \\regl_dqs_cnt_reg[2]_0 ;\n wire [1:0]regl_rank_cnt;\n wire \\regl_rank_cnt[0]_i_1_n_0 ;\n wire \\regl_rank_cnt[1]_i_1_n_0 ;\n wire \\right_edge_taps_r[0]_i_1_n_0 ;\n wire \\right_edge_taps_r[1]_i_1_n_0 ;\n wire \\right_edge_taps_r[2]_i_1_n_0 ;\n wire \\right_edge_taps_r[3]_i_1_n_0 ;\n wire \\right_edge_taps_r[4]_i_1_n_0 ;\n wire \\right_edge_taps_r[5]_i_1_n_0 ;\n wire \\right_edge_taps_r[5]_i_2_n_0 ;\n wire [5:0]right_edge_taps_r__0;\n wire \\right_edge_taps_r_reg[0]_0 ;\n wire \\right_edge_taps_r_reg[0]_1 ;\n wire \\right_edge_taps_r_reg[0]_2 ;\n wire \\rnk_cnt_r[0]_i_1__0_n_0 ;\n wire \\rnk_cnt_r[1]_i_1__0_n_0 ;\n wire \\rnk_cnt_r[1]_i_2_n_0 ;\n wire \\rnk_cnt_r[1]_i_3_n_0 ;\n wire \\rnk_cnt_r_reg_n_0_[0] ;\n wire \\rnk_cnt_r_reg_n_0_[1] ;\n wire rstdiv0_sync_r1_reg_rep__13;\n wire [1:0]rstdiv0_sync_r1_reg_rep__14;\n wire rstdiv0_sync_r1_reg_rep__2;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__23;\n wire rstdiv0_sync_r1_reg_rep__24;\n wire samp_cnt_done_r_i_1_n_0;\n wire samp_cnt_done_r_i_2_n_0;\n wire samp_cnt_done_r_i_3_n_0;\n wire samp_cnt_done_r_i_4_n_0;\n wire samp_cnt_done_r_reg_0;\n wire samp_cnt_done_r_reg_1;\n wire samp_cnt_done_r_reg_2;\n wire samp_cnt_done_r_reg_3;\n wire samp_cnt_done_r_reg_4;\n wire samp_cnt_done_r_reg_5;\n wire samp_cnt_done_r_reg_6;\n wire samp_edge_cnt0_en_r;\n wire samp_edge_cnt0_en_r_reg_0;\n wire samp_edge_cnt0_r0;\n wire \\samp_edge_cnt0_r[0]_i_4_n_0 ;\n wire \\samp_edge_cnt0_r[0]_i_5_n_0 ;\n wire \\samp_edge_cnt0_r[0]_i_6_n_0 ;\n wire \\samp_edge_cnt0_r[0]_i_7_n_0 ;\n wire \\samp_edge_cnt0_r[4]_i_2_n_0 ;\n wire \\samp_edge_cnt0_r[4]_i_3_n_0 ;\n wire \\samp_edge_cnt0_r[4]_i_4_n_0 ;\n wire \\samp_edge_cnt0_r[4]_i_5_n_0 ;\n wire \\samp_edge_cnt0_r[8]_i_2_n_0 ;\n wire \\samp_edge_cnt0_r[8]_i_3_n_0 ;\n wire \\samp_edge_cnt0_r[8]_i_4_n_0 ;\n wire \\samp_edge_cnt0_r[8]_i_5_n_0 ;\n wire [11:0]samp_edge_cnt0_r_reg;\n wire \\samp_edge_cnt0_r_reg[0]_i_3_n_0 ;\n wire \\samp_edge_cnt0_r_reg[0]_i_3_n_1 ;\n wire \\samp_edge_cnt0_r_reg[0]_i_3_n_2 ;\n wire \\samp_edge_cnt0_r_reg[0]_i_3_n_3 ;\n wire \\samp_edge_cnt0_r_reg[0]_i_3_n_4 ;\n wire \\samp_edge_cnt0_r_reg[0]_i_3_n_5 ;\n wire \\samp_edge_cnt0_r_reg[0]_i_3_n_6 ;\n wire \\samp_edge_cnt0_r_reg[0]_i_3_n_7 ;\n wire \\samp_edge_cnt0_r_reg[4]_i_1_n_0 ;\n wire \\samp_edge_cnt0_r_reg[4]_i_1_n_1 ;\n wire \\samp_edge_cnt0_r_reg[4]_i_1_n_2 ;\n wire \\samp_edge_cnt0_r_reg[4]_i_1_n_3 ;\n wire \\samp_edge_cnt0_r_reg[4]_i_1_n_4 ;\n wire \\samp_edge_cnt0_r_reg[4]_i_1_n_5 ;\n wire \\samp_edge_cnt0_r_reg[4]_i_1_n_6 ;\n wire \\samp_edge_cnt0_r_reg[4]_i_1_n_7 ;\n wire \\samp_edge_cnt0_r_reg[8]_i_1_n_1 ;\n wire \\samp_edge_cnt0_r_reg[8]_i_1_n_2 ;\n wire \\samp_edge_cnt0_r_reg[8]_i_1_n_3 ;\n wire \\samp_edge_cnt0_r_reg[8]_i_1_n_4 ;\n wire \\samp_edge_cnt0_r_reg[8]_i_1_n_5 ;\n wire \\samp_edge_cnt0_r_reg[8]_i_1_n_6 ;\n wire \\samp_edge_cnt0_r_reg[8]_i_1_n_7 ;\n wire samp_edge_cnt1_en_r;\n wire samp_edge_cnt1_en_r0;\n wire samp_edge_cnt1_en_r_i_2_n_0;\n wire samp_edge_cnt1_en_r_i_3_n_0;\n wire \\samp_edge_cnt1_r[0]_i_2_n_0 ;\n wire \\samp_edge_cnt1_r[0]_i_3_n_0 ;\n wire \\samp_edge_cnt1_r[0]_i_4_n_0 ;\n wire \\samp_edge_cnt1_r[0]_i_5_n_0 ;\n wire \\samp_edge_cnt1_r[4]_i_2_n_0 ;\n wire \\samp_edge_cnt1_r[4]_i_3_n_0 ;\n wire \\samp_edge_cnt1_r[4]_i_4_n_0 ;\n wire \\samp_edge_cnt1_r[4]_i_5_n_0 ;\n wire \\samp_edge_cnt1_r[8]_i_2_n_0 ;\n wire \\samp_edge_cnt1_r[8]_i_3_n_0 ;\n wire \\samp_edge_cnt1_r[8]_i_4_n_0 ;\n wire \\samp_edge_cnt1_r[8]_i_5_n_0 ;\n wire [11:0]samp_edge_cnt1_r_reg;\n wire \\samp_edge_cnt1_r_reg[0]_i_1_n_0 ;\n wire \\samp_edge_cnt1_r_reg[0]_i_1_n_1 ;\n wire \\samp_edge_cnt1_r_reg[0]_i_1_n_2 ;\n wire \\samp_edge_cnt1_r_reg[0]_i_1_n_3 ;\n wire \\samp_edge_cnt1_r_reg[0]_i_1_n_4 ;\n wire \\samp_edge_cnt1_r_reg[0]_i_1_n_5 ;\n wire \\samp_edge_cnt1_r_reg[0]_i_1_n_6 ;\n wire \\samp_edge_cnt1_r_reg[0]_i_1_n_7 ;\n wire \\samp_edge_cnt1_r_reg[4]_i_1_n_0 ;\n wire \\samp_edge_cnt1_r_reg[4]_i_1_n_1 ;\n wire \\samp_edge_cnt1_r_reg[4]_i_1_n_2 ;\n wire \\samp_edge_cnt1_r_reg[4]_i_1_n_3 ;\n wire \\samp_edge_cnt1_r_reg[4]_i_1_n_4 ;\n wire \\samp_edge_cnt1_r_reg[4]_i_1_n_5 ;\n wire \\samp_edge_cnt1_r_reg[4]_i_1_n_6 ;\n wire \\samp_edge_cnt1_r_reg[4]_i_1_n_7 ;\n wire \\samp_edge_cnt1_r_reg[8]_i_1_n_1 ;\n wire \\samp_edge_cnt1_r_reg[8]_i_1_n_2 ;\n wire \\samp_edge_cnt1_r_reg[8]_i_1_n_3 ;\n wire \\samp_edge_cnt1_r_reg[8]_i_1_n_4 ;\n wire \\samp_edge_cnt1_r_reg[8]_i_1_n_5 ;\n wire \\samp_edge_cnt1_r_reg[8]_i_1_n_6 ;\n wire \\samp_edge_cnt1_r_reg[8]_i_1_n_7 ;\n wire \\second_edge_taps_r[0]_i_1_n_0 ;\n wire \\second_edge_taps_r[1]_i_1_n_0 ;\n wire \\second_edge_taps_r[2]_i_1_n_0 ;\n wire \\second_edge_taps_r[3]_i_1_n_0 ;\n wire \\second_edge_taps_r[4]_i_1_n_0 ;\n wire \\second_edge_taps_r[5]_i_1_n_0 ;\n wire \\second_edge_taps_r[5]_i_3_n_0 ;\n wire \\second_edge_taps_r_reg[5]_0 ;\n wire \\second_edge_taps_r_reg_n_0_[0] ;\n wire \\second_edge_taps_r_reg_n_0_[1] ;\n wire \\second_edge_taps_r_reg_n_0_[2] ;\n wire \\second_edge_taps_r_reg_n_0_[3] ;\n wire \\second_edge_taps_r_reg_n_0_[4] ;\n wire \\second_edge_taps_r_reg_n_0_[5] ;\n wire sr_valid_r1;\n wire sr_valid_r108_out;\n wire sr_valid_r1_reg_0;\n wire sr_valid_r2;\n wire stable_idel_cnt;\n wire stable_idel_cnt0;\n wire stable_idel_cnt22_in;\n wire stg1_wr_done;\n wire \\stg1_wr_rd_cnt_reg[3] ;\n wire store_sr_r0;\n wire store_sr_r1;\n wire store_sr_r_reg_0;\n wire store_sr_req_pulsed_r;\n wire store_sr_req_pulsed_r_reg_n_0;\n wire store_sr_req_r;\n wire store_sr_req_r_i_2_n_0;\n wire store_sr_req_r_reg_0;\n wire store_sr_req_r_reg_1;\n wire tap_cnt_cpt_r;\n wire tap_cnt_cpt_r0;\n wire \\tap_cnt_cpt_r[1]_i_1_n_0 ;\n wire \\tap_cnt_cpt_r[5]_i_4_n_0 ;\n wire \\tap_cnt_cpt_r_reg_n_0_[0] ;\n wire \\tap_cnt_cpt_r_reg_n_0_[1] ;\n wire \\tap_cnt_cpt_r_reg_n_0_[2] ;\n wire \\tap_cnt_cpt_r_reg_n_0_[3] ;\n wire \\tap_cnt_cpt_r_reg_n_0_[4] ;\n wire \\tap_cnt_cpt_r_reg_n_0_[5] ;\n wire tap_limit_cpt_r;\n wire tap_limit_cpt_r_i_1_n_0;\n wire tap_limit_cpt_r_i_2_n_0;\n wire tap_limit_cpt_r_i_3_n_0;\n wire tempmon_pi_f_en_r;\n wire tempmon_pi_f_inc_r;\n wire wait_cnt_r0;\n wire [3:0]wait_cnt_r0__0;\n wire \\wait_cnt_r[1]_i_1__1_n_0 ;\n wire [1:0]\\wait_cnt_r_reg[0]_0 ;\n wire \\wait_cnt_r_reg[0]_1 ;\n wire [3:2]wait_cnt_r_reg__0;\n wire wr_level_done_reg;\n wire wrcal_done_reg;\n wire wrcal_prech_req;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[254] ;\n wire wrlvl_byte_redo;\n wire wrlvl_byte_redo_reg;\n wire wrlvl_done_r1;\n wire wrlvl_done_r1_reg;\n wire wrlvl_done_r1_reg_0;\n wire wrlvl_final_mux;\n wire wrlvl_final_mux_reg;\n wire [0:0]\\NLW_cnt_idel_dec_cpt_r_reg[1]_i_2_O_UNCONNECTED ;\n wire [0:0]\\NLW_cnt_idel_dec_cpt_r_reg[1]_i_9_O_UNCONNECTED ;\n wire [3:1]\\NLW_cnt_idel_dec_cpt_r_reg[4]_i_6_CO_UNCONNECTED ;\n wire [3:2]\\NLW_cnt_idel_dec_cpt_r_reg[4]_i_6_O_UNCONNECTED ;\n wire [3:1]\\NLW_cnt_idel_dec_cpt_r_reg[5]_i_9_CO_UNCONNECTED ;\n wire [3:2]\\NLW_cnt_idel_dec_cpt_r_reg[5]_i_9_O_UNCONNECTED ;\n wire [3:3]\\NLW_samp_edge_cnt0_r_reg[8]_i_1_CO_UNCONNECTED ;\n wire [3:3]\\NLW_samp_edge_cnt1_r_reg[8]_i_1_CO_UNCONNECTED ;\n\n LUT6 #(\n .INIT(64'hFFFFFEAEAAAAFEAE)) \n \\FSM_sequential_cal1_state_r[0]_i_1 \n (.I0(\\FSM_sequential_cal1_state_r[0]_i_2_n_0 ),\n .I1(\\FSM_sequential_cal1_state_r[0]_i_3_n_0 ),\n .I2(out[0]),\n .I3(\\FSM_sequential_cal1_state_r[0]_i_4_n_0 ),\n .I4(out[1]),\n .I5(\\FSM_sequential_cal1_state_r[0]_i_5_n_0 ),\n .O(\\FSM_sequential_cal1_state_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000002000000)) \n \\FSM_sequential_cal1_state_r[0]_i_10 \n (.I0(\\done_cnt[3]_i_3_n_0 ),\n .I1(regl_rank_cnt[1]),\n .I2(regl_rank_cnt[0]),\n .I3(regl_dqs_cnt[0]),\n .I4(regl_dqs_cnt[1]),\n .I5(\\regl_dqs_cnt_r_reg[2]_0 ),\n .O(cal1_state_r1));\n LUT5 #(\n .INIT(32'hBFFFFF00)) \n \\FSM_sequential_cal1_state_r[0]_i_11 \n (.I0(mpr_rdlvl_done_r1_reg_0),\n .I1(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I2(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .I3(out[0]),\n .I4(out[2]),\n .O(\\FSM_sequential_cal1_state_r[0]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'h0000150000000000)) \n \\FSM_sequential_cal1_state_r[0]_i_12 \n (.I0(\\FSM_sequential_cal1_state_r[0]_i_14_n_0 ),\n .I1(mpr_dec_cpt_r_reg_0),\n .I2(stable_idel_cnt22_in),\n .I3(\\cnt_idel_dec_cpt_r_reg_n_0_[0] ),\n .I4(\\cnt_idel_dec_cpt_r_reg_n_0_[1] ),\n .I5(out[2]),\n .O(\\FSM_sequential_cal1_state_r[0]_i_12_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair227\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\FSM_sequential_cal1_state_r[0]_i_13 \n (.I0(\\right_edge_taps_r_reg[0]_0 ),\n .I1(found_stable_eye_last_r),\n .O(cal1_state_r1533_out));\n (* SOFT_HLUTNM = \"soft_lutpair205\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n \\FSM_sequential_cal1_state_r[0]_i_14 \n (.I0(\\cnt_idel_dec_cpt_r_reg_n_0_[5] ),\n .I1(\\cnt_idel_dec_cpt_r_reg_n_0_[4] ),\n .I2(\\cnt_idel_dec_cpt_r_reg_n_0_[2] ),\n .I3(\\cnt_idel_dec_cpt_r_reg_n_0_[3] ),\n .O(\\FSM_sequential_cal1_state_r[0]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'hBBBB88B888B8BBB8)) \n \\FSM_sequential_cal1_state_r[0]_i_2 \n (.I0(\\FSM_sequential_cal1_state_r[0]_i_6_n_0 ),\n .I1(\\idel_dec_cnt_reg[0]_0 ),\n .I2(\\FSM_sequential_cal1_state_r[0]_i_7_n_0 ),\n .I3(out[4]),\n .I4(out[2]),\n .I5(out[0]),\n .O(\\FSM_sequential_cal1_state_r[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h8988898889998988)) \n \\FSM_sequential_cal1_state_r[0]_i_3 \n (.I0(out[2]),\n .I1(out[4]),\n .I2(mpr_rdlvl_done_r1_reg_0),\n .I3(cal1_state_r),\n .I4(mpr_rdlvl_start_reg),\n .I5(mpr_rdlvl_start_r),\n .O(\\FSM_sequential_cal1_state_r[0]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h1110101011111111)) \n \\FSM_sequential_cal1_state_r[0]_i_4 \n (.I0(out[2]),\n .I1(cal1_state_r),\n .I2(out[3]),\n .I3(idelay_tap_limit_r_reg_n_0),\n .I4(\\FSM_sequential_cal1_state_r[0]_i_8_n_0 ),\n .I5(out[4]),\n .O(\\FSM_sequential_cal1_state_r[0]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hEEAFEEAAEEAFEEAF)) \n \\FSM_sequential_cal1_state_r[0]_i_5 \n (.I0(\\FSM_sequential_cal1_state_r[0]_i_9_n_0 ),\n .I1(cal1_state_r1),\n .I2(\\FSM_sequential_cal1_state_r[0]_i_11_n_0 ),\n .I3(cal1_state_r),\n .I4(out[3]),\n .I5(store_sr_req_r_reg_0),\n .O(\\FSM_sequential_cal1_state_r[0]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'h11040004)) \n \\FSM_sequential_cal1_state_r[0]_i_6 \n (.I0(out[2]),\n .I1(out[3]),\n .I2(\\FSM_sequential_cal1_state_r[1]_i_7_n_0 ),\n .I3(out[0]),\n .I4(mpr_rdlvl_done_r1_reg_0),\n .O(\\FSM_sequential_cal1_state_r[0]_i_6_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFA800)) \n \\FSM_sequential_cal1_state_r[0]_i_7 \n (.I0(mpr_rd_rise0_prev_r_reg_0),\n .I1(idelay_tap_limit_r_reg_n_0),\n .I2(idel_mpr_pat_detect_r),\n .I3(out[0]),\n .I4(\\FSM_sequential_cal1_state_r[0]_i_12_n_0 ),\n .O(\\FSM_sequential_cal1_state_r[0]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h1)) \n \\FSM_sequential_cal1_state_r[0]_i_8 \n (.I0(\\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ),\n .I1(\\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ),\n .O(\\FSM_sequential_cal1_state_r[0]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'h2220202000000000)) \n \\FSM_sequential_cal1_state_r[0]_i_9 \n (.I0(out[0]),\n .I1(out[3]),\n .I2(tap_limit_cpt_r),\n .I3(found_first_edge_r_reg_0),\n .I4(cal1_state_r1533_out),\n .I5(out[4]),\n .O(\\FSM_sequential_cal1_state_r[0]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF2EEE2222)) \n \\FSM_sequential_cal1_state_r[1]_i_1 \n (.I0(\\FSM_sequential_cal1_state_r[1]_i_2_n_0 ),\n .I1(out[0]),\n .I2(out[4]),\n .I3(\\FSM_sequential_cal1_state_r[1]_i_3_n_0 ),\n .I4(\\FSM_sequential_cal1_state_r[1]_i_4_n_0 ),\n .I5(\\FSM_sequential_cal1_state_r_reg[1]_i_5_n_0 ),\n .O(\\FSM_sequential_cal1_state_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair203\" *) \n LUT4 #(\n .INIT(16'hFEFF)) \n \\FSM_sequential_cal1_state_r[1]_i_10 \n (.I0(\\cnt_idel_dec_cpt_r_reg_n_0_[1] ),\n .I1(\\cnt_idel_dec_cpt_r_reg_n_0_[2] ),\n .I2(\\cnt_idel_dec_cpt_r_reg_n_0_[4] ),\n .I3(mpr_dec_cpt_r_reg_0),\n .O(\\FSM_sequential_cal1_state_r[1]_i_10_n_0 ));\n LUT4 #(\n .INIT(16'h4474)) \n \\FSM_sequential_cal1_state_r[1]_i_11 \n (.I0(mpr_rdlvl_done_r1_reg_0),\n .I1(cal1_state_r),\n .I2(mpr_rdlvl_start_reg),\n .I3(mpr_rdlvl_start_r),\n .O(\\FSM_sequential_cal1_state_r[1]_i_11_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair227\" *) \n LUT3 #(\n .INIT(8'h7F)) \n \\FSM_sequential_cal1_state_r[1]_i_12 \n (.I0(found_stable_eye_last_r),\n .I1(\\right_edge_taps_r_reg[0]_0 ),\n .I2(found_first_edge_r_reg_0),\n .O(\\FSM_sequential_cal1_state_r[1]_i_12_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\FSM_sequential_cal1_state_r[1]_i_13 \n (.I0(out[3]),\n .I1(out[2]),\n .O(\\FSM_sequential_cal1_state_r[1]_i_13_n_0 ));\n LUT6 #(\n .INIT(64'h0C0C0C0C88888088)) \n \\FSM_sequential_cal1_state_r[1]_i_2 \n (.I0(out[4]),\n .I1(\\FSM_sequential_cal1_state_r[1]_i_6_n_0 ),\n .I2(out[1]),\n .I3(mpr_dec_cpt_r_reg_0),\n .I4(\\FSM_sequential_cal1_state_r[1]_i_7_n_0 ),\n .I5(out[2]),\n .O(\\FSM_sequential_cal1_state_r[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hEF00FF00EFFFFF00)) \n \\FSM_sequential_cal1_state_r[1]_i_3 \n (.I0(\\rnk_cnt_r_reg_n_0_[0] ),\n .I1(\\rnk_cnt_r_reg_n_0_[1] ),\n .I2(cal1_cnt_cpt_r1),\n .I3(out[3]),\n .I4(mpr_rdlvl_done_r1_reg_0),\n .I5(idel_adj_inc_reg_0),\n .O(\\FSM_sequential_cal1_state_r[1]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h5500000055510055)) \n \\FSM_sequential_cal1_state_r[1]_i_4 \n (.I0(cal1_state_r),\n .I1(mpr_rd_rise0_prev_r_reg_0),\n .I2(idel_mpr_pat_detect_r),\n .I3(out[2]),\n .I4(out[1]),\n .I5(out[4]),\n .O(\\FSM_sequential_cal1_state_r[1]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFD)) \n \\FSM_sequential_cal1_state_r[1]_i_6 \n (.I0(\\cnt_idel_dec_cpt_r_reg_n_0_[0] ),\n .I1(out[4]),\n .I2(stable_idel_cnt22_in),\n .I3(\\cnt_idel_dec_cpt_r_reg_n_0_[5] ),\n .I4(\\cnt_idel_dec_cpt_r_reg_n_0_[3] ),\n .I5(\\FSM_sequential_cal1_state_r[1]_i_10_n_0 ),\n .O(\\FSM_sequential_cal1_state_r[1]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\FSM_sequential_cal1_state_r[1]_i_7 \n (.I0(\\pi_rdval_cnt_reg[1]_0 ),\n .I1(idel_dec_cnt__0[2]),\n .I2(idel_dec_cnt__0[1]),\n .I3(idel_dec_cnt__0[0]),\n .I4(idel_dec_cnt__0[3]),\n .I5(idel_dec_cnt__0[4]),\n .O(\\FSM_sequential_cal1_state_r[1]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h0101010151515101)) \n \\FSM_sequential_cal1_state_r[1]_i_8 \n (.I0(out[2]),\n .I1(\\FSM_sequential_cal1_state_r[1]_i_11_n_0 ),\n .I2(out[4]),\n .I3(\\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ),\n .I4(\\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ),\n .I5(out[3]),\n .O(\\FSM_sequential_cal1_state_r[1]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'h000000004040FF40)) \n \\FSM_sequential_cal1_state_r[1]_i_9 \n (.I0(tap_limit_cpt_r),\n .I1(\\FSM_sequential_cal1_state_r[1]_i_12_n_0 ),\n .I2(out[4]),\n .I3(cal1_state_r),\n .I4(cal1_state_r1),\n .I5(\\FSM_sequential_cal1_state_r[1]_i_13_n_0 ),\n .O(\\FSM_sequential_cal1_state_r[1]_i_9_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF3404)) \n \\FSM_sequential_cal1_state_r[2]_i_1 \n (.I0(out[4]),\n .I1(out[2]),\n .I2(out[0]),\n .I3(out[3]),\n .I4(\\FSM_sequential_cal1_state_r_reg[2]_i_2_n_0 ),\n .O(\\FSM_sequential_cal1_state_r[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8888AAA8AAAAAAAA)) \n \\FSM_sequential_cal1_state_r[2]_i_3 \n (.I0(out[4]),\n .I1(out[0]),\n .I2(\\FSM_sequential_cal1_state_r[1]_i_7_n_0 ),\n .I3(mpr_dec_cpt_r_reg_0),\n .I4(out[2]),\n .I5(out[3]),\n .O(\\FSM_sequential_cal1_state_r[2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h00AB00AB03AB00AB)) \n \\FSM_sequential_cal1_state_r[2]_i_4 \n (.I0(\\FSM_sequential_cal1_state_r[2]_i_5_n_0 ),\n .I1(out[4]),\n .I2(cal1_state_r),\n .I3(out[0]),\n .I4(mpr_rd_rise0_prev_r_reg_0),\n .I5(idel_mpr_pat_detect_r),\n .O(\\FSM_sequential_cal1_state_r[2]_i_4_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\FSM_sequential_cal1_state_r[2]_i_5 \n (.I0(out[2]),\n .I1(out[3]),\n .O(\\FSM_sequential_cal1_state_r[2]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h303030003008CC08)) \n \\FSM_sequential_cal1_state_r[3]_i_1 \n (.I0(\\FSM_sequential_cal1_state_r[3]_i_2_n_0 ),\n .I1(out[2]),\n .I2(out[4]),\n .I3(out[1]),\n .I4(out[3]),\n .I5(out[0]),\n .O(\\FSM_sequential_cal1_state_r[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFDF)) \n \\FSM_sequential_cal1_state_r[3]_i_2 \n (.I0(mpr_dec_cpt_r_reg_0),\n .I1(\\cnt_idel_dec_cpt_r_reg_n_0_[4] ),\n .I2(\\cnt_idel_dec_cpt_r_reg_n_0_[0] ),\n .I3(\\cnt_idel_dec_cpt_r_reg_n_0_[3] ),\n .I4(\\cnt_idel_dec_cpt_r_reg_n_0_[5] ),\n .I5(\\FSM_sequential_cal1_state_r[3]_i_3_n_0 ),\n .O(\\FSM_sequential_cal1_state_r[3]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair203\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\FSM_sequential_cal1_state_r[3]_i_3 \n (.I0(\\cnt_idel_dec_cpt_r_reg_n_0_[2] ),\n .I1(\\cnt_idel_dec_cpt_r_reg_n_0_[1] ),\n .O(\\FSM_sequential_cal1_state_r[3]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'h0C0C0C8C)) \n \\FSM_sequential_cal1_state_r[4]_i_1 \n (.I0(out[2]),\n .I1(\\FSM_sequential_cal1_state_r[4]_i_2_n_0 ),\n .I2(\\FSM_sequential_cal1_state_r[4]_i_3_n_0 ),\n .I3(\\FSM_sequential_cal1_state_r[4]_i_4_n_0 ),\n .I4(out[0]),\n .O(\\FSM_sequential_cal1_state_r[4]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hEFFFFFFF)) \n \\FSM_sequential_cal1_state_r[4]_i_2 \n (.I0(idel_adj_inc_reg_0),\n .I1(mpr_rdlvl_done_r1_reg_0),\n .I2(out[0]),\n .I3(out[2]),\n .I4(out[1]),\n .O(\\FSM_sequential_cal1_state_r[4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h000000000000AFEF)) \n \\FSM_sequential_cal1_state_r[4]_i_3 \n (.I0(out[3]),\n .I1(mpr_dec_cpt_r_reg_0),\n .I2(out[2]),\n .I3(out[0]),\n .I4(\\FSM_sequential_cal1_state_r[4]_i_5_n_0 ),\n .I5(\\FSM_sequential_cal1_state_r[4]_i_6_n_0 ),\n .O(\\FSM_sequential_cal1_state_r[4]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hA0A0A0A0A0A0A0A1)) \n \\FSM_sequential_cal1_state_r[4]_i_4 \n (.I0(out[1]),\n .I1(\\FSM_sequential_cal1_state_r[4]_i_7_n_0 ),\n .I2(out[3]),\n .I3(stable_idel_cnt22_in),\n .I4(\\cnt_idel_dec_cpt_r_reg_n_0_[2] ),\n .I5(\\cnt_idel_dec_cpt_r_reg_n_0_[1] ),\n .O(\\FSM_sequential_cal1_state_r[4]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h1000101010101010)) \n \\FSM_sequential_cal1_state_r[4]_i_5 \n (.I0(out[0]),\n .I1(out[1]),\n .I2(out[4]),\n .I3(\\FSM_sequential_cal1_state_r[1]_i_7_n_0 ),\n .I4(out[3]),\n .I5(mpr_dec_cpt_r_reg_0),\n .O(\\FSM_sequential_cal1_state_r[4]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'h55404440)) \n \\FSM_sequential_cal1_state_r[4]_i_6 \n (.I0(out[2]),\n .I1(out[1]),\n .I2(out[3]),\n .I3(out[0]),\n .I4(out[4]),\n .O(\\FSM_sequential_cal1_state_r[4]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair205\" *) \n LUT4 #(\n .INIT(16'hFFFD)) \n \\FSM_sequential_cal1_state_r[4]_i_7 \n (.I0(\\cnt_idel_dec_cpt_r_reg_n_0_[0] ),\n .I1(\\cnt_idel_dec_cpt_r_reg_n_0_[5] ),\n .I2(\\cnt_idel_dec_cpt_r_reg_n_0_[3] ),\n .I3(\\cnt_idel_dec_cpt_r_reg_n_0_[4] ),\n .O(\\FSM_sequential_cal1_state_r[4]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair110\" *) \n LUT5 #(\n .INIT(32'hFFFEFFFF)) \n \\FSM_sequential_cal1_state_r[4]_i_8 \n (.I0(idelay_tap_cnt_r[4]),\n .I1(idelay_tap_cnt_r[3]),\n .I2(idelay_tap_cnt_r[2]),\n .I3(idelay_tap_cnt_r[1]),\n .I4(\\idel_dec_cnt[0]_i_2_n_0 ),\n .O(stable_idel_cnt22_in));\n LUT6 #(\n .INIT(64'h101F101F101F1010)) \n \\FSM_sequential_cal1_state_r[5]_i_1 \n (.I0(cal1_state_r),\n .I1(\\FSM_sequential_cal1_state_r[5]_i_3_n_0 ),\n .I2(out[4]),\n .I3(out[3]),\n .I4(\\FSM_sequential_cal1_state_r[5]_i_4_n_0 ),\n .I5(\\FSM_sequential_cal1_state_r[5]_i_5_n_0 ),\n .O(\\FSM_sequential_cal1_state_r[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0FF00FF050005FC0)) \n \\FSM_sequential_cal1_state_r[5]_i_11 \n (.I0(mpr_rdlvl_done_r1_reg_0),\n .I1(mpr_valid_r1_reg_0),\n .I2(out[0]),\n .I3(cal1_state_r),\n .I4(cal1_wait_r),\n .I5(out[1]),\n .O(\\FSM_sequential_cal1_state_r[5]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'h00005400FC00FC00)) \n \\FSM_sequential_cal1_state_r[5]_i_2 \n (.I0(\\rnk_cnt_r_reg_n_0_[0] ),\n .I1(out[3]),\n .I2(cal1_state_r),\n .I3(\\FSM_sequential_cal1_state_r[5]_i_6_n_0 ),\n .I4(\\rnk_cnt_r_reg_n_0_[1] ),\n .I5(\\FSM_sequential_cal1_state_r[5]_i_7_n_0 ),\n .O(\\FSM_sequential_cal1_state_r[5]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000B0B1FBF5B0B1)) \n \\FSM_sequential_cal1_state_r[5]_i_3 \n (.I0(out[3]),\n .I1(out[2]),\n .I2(cal1_wait_r),\n .I3(out[1]),\n .I4(out[0]),\n .I5(\\FSM_sequential_cal1_state_r[5]_i_8_n_0 ),\n .O(\\FSM_sequential_cal1_state_r[5]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0007FFFF00070000)) \n \\FSM_sequential_cal1_state_r[5]_i_4 \n (.I0(cal1_wait_r),\n .I1(out[0]),\n .I2(cal1_state_r),\n .I3(out[1]),\n .I4(out[2]),\n .I5(\\FSM_sequential_cal1_state_r[5]_i_9_n_0 ),\n .O(\\FSM_sequential_cal1_state_r[5]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h0000000010111010)) \n \\FSM_sequential_cal1_state_r[5]_i_5 \n (.I0(out[0]),\n .I1(cal1_state_r),\n .I2(cal1_state_r1535_out),\n .I3(rdlvl_stg1_start_r),\n .I4(rdlvl_stg1_start_reg),\n .I5(out[1]),\n .O(\\FSM_sequential_cal1_state_r[5]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'hC0FE00CC)) \n \\FSM_sequential_cal1_state_r[5]_i_6 \n (.I0(mpr_rdlvl_done_r1_reg_0),\n .I1(out[1]),\n .I2(out[2]),\n .I3(out[4]),\n .I4(out[0]),\n .O(\\FSM_sequential_cal1_state_r[5]_i_6_n_0 ));\n LUT5 #(\n .INIT(32'h80000000)) \n \\FSM_sequential_cal1_state_r[5]_i_7 \n (.I0(mpr_rdlvl_done_r1_reg_0),\n .I1(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I2(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .I3(out[1]),\n .I4(out[0]),\n .O(\\FSM_sequential_cal1_state_r[5]_i_7_n_0 ));\n LUT5 #(\n .INIT(32'hC000EEEE)) \n \\FSM_sequential_cal1_state_r[5]_i_8 \n (.I0(detect_edge_done_r),\n .I1(out[3]),\n .I2(out[1]),\n .I3(prech_done),\n .I4(out[2]),\n .O(\\FSM_sequential_cal1_state_r[5]_i_8_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF00D0)) \n \\FSM_sequential_cal1_state_r[5]_i_9 \n (.I0(cal1_wait_r),\n .I1(store_sr_req_r_reg_0),\n .I2(out[1]),\n .I3(cal1_state_r),\n .I4(\\FSM_sequential_cal1_state_r[5]_i_11_n_0 ),\n .O(\\FSM_sequential_cal1_state_r[5]_i_9_n_0 ));\n (* KEEP = \"yes\" *) \n FDRE \\FSM_sequential_cal1_state_r_reg[0] \n (.C(CLK),\n .CE(\\FSM_sequential_cal1_state_r[5]_i_1_n_0 ),\n .D(\\FSM_sequential_cal1_state_r[0]_i_1_n_0 ),\n .Q(out[0]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n (* KEEP = \"yes\" *) \n FDRE \\FSM_sequential_cal1_state_r_reg[1] \n (.C(CLK),\n .CE(\\FSM_sequential_cal1_state_r[5]_i_1_n_0 ),\n .D(\\FSM_sequential_cal1_state_r[1]_i_1_n_0 ),\n .Q(out[1]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n MUXF7 \\FSM_sequential_cal1_state_r_reg[1]_i_5 \n (.I0(\\FSM_sequential_cal1_state_r[1]_i_8_n_0 ),\n .I1(\\FSM_sequential_cal1_state_r[1]_i_9_n_0 ),\n .O(\\FSM_sequential_cal1_state_r_reg[1]_i_5_n_0 ),\n .S(out[1]));\n (* KEEP = \"yes\" *) \n FDRE \\FSM_sequential_cal1_state_r_reg[2] \n (.C(CLK),\n .CE(\\FSM_sequential_cal1_state_r[5]_i_1_n_0 ),\n .D(\\FSM_sequential_cal1_state_r[2]_i_1_n_0 ),\n .Q(out[2]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n MUXF7 \\FSM_sequential_cal1_state_r_reg[2]_i_2 \n (.I0(\\FSM_sequential_cal1_state_r[2]_i_3_n_0 ),\n .I1(\\FSM_sequential_cal1_state_r[2]_i_4_n_0 ),\n .O(\\FSM_sequential_cal1_state_r_reg[2]_i_2_n_0 ),\n .S(out[1]));\n (* KEEP = \"yes\" *) \n FDRE \\FSM_sequential_cal1_state_r_reg[3] \n (.C(CLK),\n .CE(\\FSM_sequential_cal1_state_r[5]_i_1_n_0 ),\n .D(\\FSM_sequential_cal1_state_r[3]_i_1_n_0 ),\n .Q(out[3]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n (* KEEP = \"yes\" *) \n FDRE \\FSM_sequential_cal1_state_r_reg[4] \n (.C(CLK),\n .CE(\\FSM_sequential_cal1_state_r[5]_i_1_n_0 ),\n .D(\\FSM_sequential_cal1_state_r[4]_i_1_n_0 ),\n .Q(out[4]),\n .R(rstdiv0_sync_r1_reg_rep__2));\n (* KEEP = \"yes\" *) \n FDRE \\FSM_sequential_cal1_state_r_reg[5] \n (.C(CLK),\n .CE(\\FSM_sequential_cal1_state_r[5]_i_1_n_0 ),\n .D(\\FSM_sequential_cal1_state_r[5]_i_2_n_0 ),\n .Q(cal1_state_r),\n .R(rstdiv0_sync_r1_reg_rep__2));\n LUT3 #(\n .INIT(8'h34)) \n \\cal1_cnt_cpt_r[0]_i_1 \n (.I0(cal1_state_r),\n .I1(\\cal1_cnt_cpt_r[1]_i_3_n_0 ),\n .I2(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .O(\\cal1_cnt_cpt_r[0]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h1F20)) \n \\cal1_cnt_cpt_r[1]_i_2 \n (.I0(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .I1(cal1_state_r),\n .I2(\\cal1_cnt_cpt_r[1]_i_3_n_0 ),\n .I3(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .O(\\cal1_cnt_cpt_r[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00800A0000000000)) \n \\cal1_cnt_cpt_r[1]_i_3 \n (.I0(out[1]),\n .I1(\\cal1_cnt_cpt_r[1]_i_4_n_0 ),\n .I2(out[3]),\n .I3(cal1_state_r),\n .I4(out[4]),\n .I5(\\cal1_cnt_cpt_r[1]_i_5_n_0 ),\n .O(\\cal1_cnt_cpt_r[1]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAA2AAAAAAAAA)) \n \\cal1_cnt_cpt_r[1]_i_4 \n (.I0(prech_done),\n .I1(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .I2(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I3(\\rnk_cnt_r_reg_n_0_[0] ),\n .I4(\\rnk_cnt_r_reg_n_0_[1] ),\n .I5(mpr_rdlvl_done_r1_reg_0),\n .O(\\cal1_cnt_cpt_r[1]_i_4_n_0 ));\n LUT3 #(\n .INIT(8'h81)) \n \\cal1_cnt_cpt_r[1]_i_5 \n (.I0(out[0]),\n .I1(out[2]),\n .I2(out[3]),\n .O(\\cal1_cnt_cpt_r[1]_i_5_n_0 ));\n FDRE \\cal1_cnt_cpt_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cal1_cnt_cpt_r[0]_i_1_n_0 ),\n .Q(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE \\cal1_cnt_cpt_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cal1_cnt_cpt_r[1]_i_2_n_0 ),\n .Q(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n LUT6 #(\n .INIT(64'h0010000000003000)) \n cal1_dlyce_cpt_r_i_1\n (.I0(tap_limit_cpt_r),\n .I1(cal1_state_r),\n .I2(cal1_dlyce_cpt_r_i_2_n_0),\n .I3(out[2]),\n .I4(out[4]),\n .I5(out[3]),\n .O(cal1_dlyce_cpt_r));\n LUT3 #(\n .INIT(8'h24)) \n cal1_dlyce_cpt_r_i_2\n (.I0(out[0]),\n .I1(out[2]),\n .I2(out[1]),\n .O(cal1_dlyce_cpt_r_i_2_n_0));\n FDRE cal1_dlyce_cpt_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cal1_dlyce_cpt_r),\n .Q(cal1_dlyce_cpt_r_reg_n_0),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n LUT6 #(\n .INIT(64'h0000000001000000)) \n cal1_dlyinc_cpt_r_i_1\n (.I0(out[2]),\n .I1(tap_limit_cpt_r),\n .I2(cal1_state_r),\n .I3(out[1]),\n .I4(out[0]),\n .I5(cal1_dlyinc_cpt_r_i_2_n_0),\n .O(cal1_dlyinc_cpt_r));\n LUT2 #(\n .INIT(4'h7)) \n cal1_dlyinc_cpt_r_i_2\n (.I0(out[3]),\n .I1(out[4]),\n .O(cal1_dlyinc_cpt_r_i_2_n_0));\n FDRE cal1_dlyinc_cpt_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cal1_dlyinc_cpt_r),\n .Q(cal1_dlyinc_cpt_r_reg_n_0),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n LUT5 #(\n .INIT(32'h00000020)) \n cal1_dq_idel_ce_i_1\n (.I0(out[2]),\n .I1(out[3]),\n .I2(out[4]),\n .I3(out[0]),\n .I4(cal1_state_r),\n .O(cal1_dq_idel_ce));\n FDRE cal1_dq_idel_ce_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cal1_dq_idel_ce),\n .Q(idelay_ce_int),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n LUT6 #(\n .INIT(64'h0000000000001000)) \n cal1_dq_idel_inc_i_1\n (.I0(cal1_state_r),\n .I1(out[1]),\n .I2(out[4]),\n .I3(out[2]),\n .I4(out[3]),\n .I5(out[0]),\n .O(cal1_dq_idel_inc));\n FDRE cal1_dq_idel_inc_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cal1_dq_idel_inc),\n .Q(idelay_inc_int),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n LUT6 #(\n .INIT(64'h2000000000000000)) \n cal1_prech_req_r_i_1\n (.I0(out[4]),\n .I1(cal1_state_r),\n .I2(out[2]),\n .I3(out[3]),\n .I4(out[1]),\n .I5(out[0]),\n .O(cal1_prech_req_r));\n FDRE cal1_prech_req_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cal1_prech_req_r),\n .Q(cal1_prech_req_r_reg_n_0),\n .R(rstdiv0_sync_r1_reg_rep__13));\n LUT6 #(\n .INIT(64'h00404000501F500C)) \n \\cal1_state_r1[0]_i_1 \n (.I0(cal1_state_r),\n .I1(out[1]),\n .I2(out[4]),\n .I3(out[3]),\n .I4(out[0]),\n .I5(out[2]),\n .O(\\cal1_state_r1[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h090A010E00045440)) \n \\cal1_state_r1[1]_i_1 \n (.I0(out[3]),\n .I1(out[0]),\n .I2(cal1_state_r),\n .I3(out[1]),\n .I4(out[2]),\n .I5(out[4]),\n .O(\\cal1_state_r1[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000CA0F1102C)) \n \\cal1_state_r1[2]_i_1 \n (.I0(out[1]),\n .I1(out[0]),\n .I2(out[4]),\n .I3(out[3]),\n .I4(out[2]),\n .I5(cal1_state_r),\n .O(\\cal1_state_r1[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0101C54901008482)) \n \\cal1_state_r1[3]_i_1 \n (.I0(out[2]),\n .I1(out[4]),\n .I2(out[3]),\n .I3(out[1]),\n .I4(cal1_state_r),\n .I5(out[0]),\n .O(\\cal1_state_r1[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0100004500000440)) \n \\cal1_state_r1[4]_i_1 \n (.I0(out[3]),\n .I1(out[1]),\n .I2(cal1_state_r),\n .I3(out[4]),\n .I4(out[2]),\n .I5(out[0]),\n .O(\\cal1_state_r1[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h1000000800004002)) \n \\cal1_state_r1[5]_i_1 \n (.I0(cal1_state_r),\n .I1(out[1]),\n .I2(out[4]),\n .I3(out[3]),\n .I4(out[2]),\n .I5(out[0]),\n .O(\\cal1_state_r1[5]_i_1_n_0 ));\n FDRE \\cal1_state_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cal1_state_r1[0]_i_1_n_0 ),\n .Q(\\cal1_state_r1_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\cal1_state_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cal1_state_r1[1]_i_1_n_0 ),\n .Q(\\cal1_state_r1_reg_n_0_[1] ),\n .R(1'b0));\n FDRE \\cal1_state_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cal1_state_r1[2]_i_1_n_0 ),\n .Q(\\cal1_state_r1_reg_n_0_[2] ),\n .R(1'b0));\n FDRE \\cal1_state_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cal1_state_r1[3]_i_1_n_0 ),\n .Q(\\cal1_state_r1_reg_n_0_[3] ),\n .R(1'b0));\n FDRE \\cal1_state_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cal1_state_r1[4]_i_1_n_0 ),\n .Q(\\cal1_state_r1_reg_n_0_[4] ),\n .R(1'b0));\n FDRE \\cal1_state_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cal1_state_r1[5]_i_1_n_0 ),\n .Q(\\cal1_state_r1_reg_n_0_[5] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h06090C0600090F12)) \n cal1_wait_cnt_en_r_i_1\n (.I0(out[1]),\n .I1(out[3]),\n .I2(cal1_state_r),\n .I3(out[4]),\n .I4(out[0]),\n .I5(out[2]),\n .O(cal1_wait_cnt_en_r0));\n FDRE cal1_wait_cnt_en_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cal1_wait_cnt_en_r0),\n .Q(cal1_wait_cnt_en_r),\n .R(1'b0));\n LUT1 #(\n .INIT(2'h1)) \n \\cal1_wait_cnt_r[0]_i_1 \n (.I0(cal1_wait_cnt_r_reg__0[0]),\n .O(p_0_in__0__0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair238\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\cal1_wait_cnt_r[1]_i_1 \n (.I0(cal1_wait_cnt_r_reg__0[1]),\n .I1(cal1_wait_cnt_r_reg__0[0]),\n .O(p_0_in__0__0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair238\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\cal1_wait_cnt_r[2]_i_1 \n (.I0(cal1_wait_cnt_r_reg__0[2]),\n .I1(cal1_wait_cnt_r_reg__0[0]),\n .I2(cal1_wait_cnt_r_reg__0[1]),\n .O(p_0_in__0__0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair193\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\cal1_wait_cnt_r[3]_i_1 \n (.I0(cal1_wait_cnt_r_reg__0[3]),\n .I1(cal1_wait_cnt_r_reg__0[1]),\n .I2(cal1_wait_cnt_r_reg__0[0]),\n .I3(cal1_wait_cnt_r_reg__0[2]),\n .O(p_0_in__0__0[3]));\n LUT6 #(\n .INIT(64'h40000000FFFFFFFF)) \n \\cal1_wait_cnt_r[4]_i_1 \n (.I0(cal1_wait_cnt_r_reg__0[4]),\n .I1(cal1_wait_cnt_r_reg__0[3]),\n .I2(cal1_wait_cnt_r_reg__0[1]),\n .I3(cal1_wait_cnt_r_reg__0[0]),\n .I4(cal1_wait_cnt_r_reg__0[2]),\n .I5(cal1_wait_cnt_en_r),\n .O(\\cal1_wait_cnt_r[4]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair193\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\cal1_wait_cnt_r[4]_i_2 \n (.I0(cal1_wait_cnt_r_reg__0[4]),\n .I1(cal1_wait_cnt_r_reg__0[2]),\n .I2(cal1_wait_cnt_r_reg__0[0]),\n .I3(cal1_wait_cnt_r_reg__0[1]),\n .I4(cal1_wait_cnt_r_reg__0[3]),\n .O(p_0_in__0__0[4]));\n FDRE \\cal1_wait_cnt_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0__0[0]),\n .Q(cal1_wait_cnt_r_reg__0[0]),\n .R(\\cal1_wait_cnt_r[4]_i_1_n_0 ));\n FDRE \\cal1_wait_cnt_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0__0[1]),\n .Q(cal1_wait_cnt_r_reg__0[1]),\n .R(\\cal1_wait_cnt_r[4]_i_1_n_0 ));\n FDRE \\cal1_wait_cnt_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0__0[2]),\n .Q(cal1_wait_cnt_r_reg__0[2]),\n .R(\\cal1_wait_cnt_r[4]_i_1_n_0 ));\n FDRE \\cal1_wait_cnt_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0__0[3]),\n .Q(cal1_wait_cnt_r_reg__0[3]),\n .R(\\cal1_wait_cnt_r[4]_i_1_n_0 ));\n FDRE \\cal1_wait_cnt_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0__0[4]),\n .Q(cal1_wait_cnt_r_reg__0[4]),\n .R(\\cal1_wait_cnt_r[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hBFFFFFFFFFFFFFFF)) \n cal1_wait_r_i_1\n (.I0(cal1_wait_cnt_r_reg__0[4]),\n .I1(cal1_wait_cnt_r_reg__0[3]),\n .I2(cal1_wait_cnt_r_reg__0[1]),\n .I3(cal1_wait_cnt_r_reg__0[0]),\n .I4(cal1_wait_cnt_r_reg__0[2]),\n .I5(cal1_wait_cnt_en_r),\n .O(cal1_wait_r_i_1_n_0));\n FDRE cal1_wait_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cal1_wait_r_i_1_n_0),\n .Q(cal1_wait_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h74FF7400)) \n \\cnt_idel_dec_cpt_r[0]_i_1 \n (.I0(cnt_idel_dec_cpt_r2[1]),\n .I1(\\cnt_idel_dec_cpt_r_reg[0]_0 ),\n .I2(\\cnt_idel_dec_cpt_r[0]_i_2_n_0 ),\n .I3(out[0]),\n .I4(\\cnt_idel_dec_cpt_r[0]_i_3_n_0 ),\n .O(cnt_idel_dec_cpt_r[0]));\n LUT6 #(\n .INIT(64'hB800B8FFB8FFB800)) \n \\cnt_idel_dec_cpt_r[0]_i_2 \n (.I0(\\cnt_idel_dec_cpt_r_reg[1]_i_9_n_6 ),\n .I1(\\right_edge_taps_r_reg[0]_0 ),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .I3(\\cnt_idel_dec_cpt_r[5]_i_8_n_0 ),\n .I4(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .I5(right_edge_taps_r__0[1]),\n .O(\\cnt_idel_dec_cpt_r[0]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'h404F)) \n \\cnt_idel_dec_cpt_r[0]_i_3 \n (.I0(\\calib_sel_reg[3] [2]),\n .I1(\\pi_counter_read_val_reg[5] [0]),\n .I2(out[1]),\n .I3(\\cnt_idel_dec_cpt_r_reg_n_0_[0] ),\n .O(\\cnt_idel_dec_cpt_r[0]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h6F60FFFF6F600000)) \n \\cnt_idel_dec_cpt_r[1]_i_1 \n (.I0(cnt_idel_dec_cpt_r2[2]),\n .I1(cnt_idel_dec_cpt_r2[1]),\n .I2(\\cnt_idel_dec_cpt_r_reg[0]_0 ),\n .I3(\\cnt_idel_dec_cpt_r[1]_i_3_n_0 ),\n .I4(out[0]),\n .I5(\\cnt_idel_dec_cpt_r[1]_i_4_n_0 ),\n .O(cnt_idel_dec_cpt_r[1]));\n (* SOFT_HLUTNM = \"soft_lutpair208\" *) \n LUT4 #(\n .INIT(16'h4BB4)) \n \\cnt_idel_dec_cpt_r[1]_i_10 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .I1(right_edge_taps_r__0[1]),\n .I2(right_edge_taps_r__0[2]),\n .I3(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .O(\\cnt_idel_dec_cpt_r[1]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\cnt_idel_dec_cpt_r[1]_i_11 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .I1(\\first_edge_taps_r_reg_n_0_[3] ),\n .O(\\cnt_idel_dec_cpt_r[1]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\cnt_idel_dec_cpt_r[1]_i_12 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .I1(\\first_edge_taps_r_reg_n_0_[2] ),\n .O(\\cnt_idel_dec_cpt_r[1]_i_12_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\cnt_idel_dec_cpt_r[1]_i_13 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .I1(\\first_edge_taps_r_reg_n_0_[1] ),\n .O(\\cnt_idel_dec_cpt_r[1]_i_13_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\cnt_idel_dec_cpt_r[1]_i_14 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .I1(\\first_edge_taps_r_reg_n_0_[0] ),\n .O(\\cnt_idel_dec_cpt_r[1]_i_14_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\cnt_idel_dec_cpt_r[1]_i_3 \n (.I0(\\cnt_idel_dec_cpt_r_reg[1]_i_9_n_5 ),\n .I1(\\right_edge_taps_r_reg[0]_0 ),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .I3(\\cnt_idel_dec_cpt_r[5]_i_8_n_0 ),\n .I4(\\cnt_idel_dec_cpt_r[1]_i_10_n_0 ),\n .O(\\cnt_idel_dec_cpt_r[1]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'h4F40404F)) \n \\cnt_idel_dec_cpt_r[1]_i_4 \n (.I0(\\calib_sel_reg[3] [2]),\n .I1(\\pi_counter_read_val_reg[5] [1]),\n .I2(out[1]),\n .I3(\\cnt_idel_dec_cpt_r_reg_n_0_[0] ),\n .I4(\\cnt_idel_dec_cpt_r_reg_n_0_[1] ),\n .O(\\cnt_idel_dec_cpt_r[1]_i_4_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\cnt_idel_dec_cpt_r[1]_i_5 \n (.I0(\\second_edge_taps_r_reg_n_0_[3] ),\n .I1(\\first_edge_taps_r_reg_n_0_[3] ),\n .O(\\cnt_idel_dec_cpt_r[1]_i_5_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\cnt_idel_dec_cpt_r[1]_i_6 \n (.I0(\\second_edge_taps_r_reg_n_0_[2] ),\n .I1(\\first_edge_taps_r_reg_n_0_[2] ),\n .O(\\cnt_idel_dec_cpt_r[1]_i_6_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\cnt_idel_dec_cpt_r[1]_i_7 \n (.I0(\\second_edge_taps_r_reg_n_0_[1] ),\n .I1(\\first_edge_taps_r_reg_n_0_[1] ),\n .O(\\cnt_idel_dec_cpt_r[1]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\cnt_idel_dec_cpt_r[1]_i_8 \n (.I0(\\second_edge_taps_r_reg_n_0_[0] ),\n .I1(\\first_edge_taps_r_reg_n_0_[0] ),\n .O(\\cnt_idel_dec_cpt_r[1]_i_8_n_0 ));\n LUT5 #(\n .INIT(32'hB8B8B88B)) \n \\cnt_idel_dec_cpt_r[2]_i_2 \n (.I0(\\rdlvl_cpt_tap_cnt_reg[2] ),\n .I1(out[1]),\n .I2(\\cnt_idel_dec_cpt_r_reg_n_0_[2] ),\n .I3(\\cnt_idel_dec_cpt_r_reg_n_0_[1] ),\n .I4(\\cnt_idel_dec_cpt_r_reg_n_0_[0] ),\n .O(\\cnt_idel_dec_cpt_r[2]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h6AFF6A00)) \n \\cnt_idel_dec_cpt_r[2]_i_3 \n (.I0(cnt_idel_dec_cpt_r2[3]),\n .I1(cnt_idel_dec_cpt_r2[1]),\n .I2(cnt_idel_dec_cpt_r2[2]),\n .I3(\\cnt_idel_dec_cpt_r_reg[0]_0 ),\n .I4(\\cnt_idel_dec_cpt_r[2]_i_4_n_0 ),\n .O(\\cnt_idel_dec_cpt_r[2]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\cnt_idel_dec_cpt_r[2]_i_4 \n (.I0(\\cnt_idel_dec_cpt_r_reg[1]_i_9_n_4 ),\n .I1(\\right_edge_taps_r_reg[0]_0 ),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .I3(\\cnt_idel_dec_cpt_r[5]_i_8_n_0 ),\n .I4(\\cnt_idel_dec_cpt_r[2]_i_5_n_0 ),\n .O(\\cnt_idel_dec_cpt_r[2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h40F4BF0BBF0B40F4)) \n \\cnt_idel_dec_cpt_r[2]_i_5 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .I1(right_edge_taps_r__0[1]),\n .I2(right_edge_taps_r__0[2]),\n .I3(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .I4(right_edge_taps_r__0[3]),\n .I5(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .O(\\cnt_idel_dec_cpt_r[2]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hB8B8B8B8B8B8B88B)) \n \\cnt_idel_dec_cpt_r[3]_i_2 \n (.I0(\\calib_sel_reg[3]_0 [1]),\n .I1(out[1]),\n .I2(\\cnt_idel_dec_cpt_r_reg_n_0_[3] ),\n .I3(\\cnt_idel_dec_cpt_r_reg_n_0_[2] ),\n .I4(\\cnt_idel_dec_cpt_r_reg_n_0_[0] ),\n .I5(\\cnt_idel_dec_cpt_r_reg_n_0_[1] ),\n .O(\\cnt_idel_dec_cpt_r[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h6AAAFFFF6AAA0000)) \n \\cnt_idel_dec_cpt_r[3]_i_3 \n (.I0(cnt_idel_dec_cpt_r2[4]),\n .I1(cnt_idel_dec_cpt_r2[2]),\n .I2(cnt_idel_dec_cpt_r2[1]),\n .I3(cnt_idel_dec_cpt_r2[3]),\n .I4(\\cnt_idel_dec_cpt_r_reg[0]_0 ),\n .I5(\\cnt_idel_dec_cpt_r[3]_i_4_n_0 ),\n .O(\\cnt_idel_dec_cpt_r[3]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\cnt_idel_dec_cpt_r[3]_i_4 \n (.I0(\\cnt_idel_dec_cpt_r_reg[4]_i_6_n_7 ),\n .I1(\\right_edge_taps_r_reg[0]_0 ),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[4] ),\n .I3(\\cnt_idel_dec_cpt_r[5]_i_8_n_0 ),\n .I4(\\cnt_idel_dec_cpt_r[3]_i_5_n_0 ),\n .O(\\cnt_idel_dec_cpt_r[3]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair108\" *) \n LUT3 #(\n .INIT(8'h96)) \n \\cnt_idel_dec_cpt_r[3]_i_5 \n (.I0(\\cnt_idel_dec_cpt_r[5]_i_11_n_0 ),\n .I1(right_edge_taps_r__0[4]),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .O(\\cnt_idel_dec_cpt_r[3]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hB888B8BBB8BBB888)) \n \\cnt_idel_dec_cpt_r[4]_i_1 \n (.I0(\\cnt_idel_dec_cpt_r_reg[4]_i_2_n_0 ),\n .I1(out[0]),\n .I2(\\rdlvl_cpt_tap_cnt_reg[4] ),\n .I3(out[1]),\n .I4(\\cnt_idel_dec_cpt_r_reg_n_0_[4] ),\n .I5(\\cnt_idel_dec_cpt_r[4]_i_3_n_0 ),\n .O(cnt_idel_dec_cpt_r[4]));\n (* SOFT_HLUTNM = \"soft_lutpair206\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\cnt_idel_dec_cpt_r[4]_i_3 \n (.I0(\\cnt_idel_dec_cpt_r_reg_n_0_[2] ),\n .I1(\\cnt_idel_dec_cpt_r_reg_n_0_[0] ),\n .I2(\\cnt_idel_dec_cpt_r_reg_n_0_[1] ),\n .I3(\\cnt_idel_dec_cpt_r_reg_n_0_[3] ),\n .O(\\cnt_idel_dec_cpt_r[4]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\cnt_idel_dec_cpt_r[4]_i_4 \n (.I0(\\cnt_idel_dec_cpt_r_reg[4]_i_6_n_6 ),\n .I1(\\right_edge_taps_r_reg[0]_0 ),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[5] ),\n .I3(\\cnt_idel_dec_cpt_r[5]_i_8_n_0 ),\n .I4(\\cnt_idel_dec_cpt_r[4]_i_7_n_0 ),\n .O(\\cnt_idel_dec_cpt_r[4]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\cnt_idel_dec_cpt_r[4]_i_5 \n (.I0(cnt_idel_dec_cpt_r2[5]),\n .I1(cnt_idel_dec_cpt_r2[3]),\n .I2(cnt_idel_dec_cpt_r2[1]),\n .I3(cnt_idel_dec_cpt_r2[2]),\n .I4(cnt_idel_dec_cpt_r2[4]),\n .O(\\cnt_idel_dec_cpt_r[4]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair108\" *) \n LUT5 #(\n .INIT(32'hB24D4DB2)) \n \\cnt_idel_dec_cpt_r[4]_i_7 \n (.I0(\\cnt_idel_dec_cpt_r[5]_i_11_n_0 ),\n .I1(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .I2(right_edge_taps_r__0[4]),\n .I3(right_edge_taps_r__0[5]),\n .I4(\\tap_cnt_cpt_r_reg_n_0_[4] ),\n .O(\\cnt_idel_dec_cpt_r[4]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\cnt_idel_dec_cpt_r[4]_i_8 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[5] ),\n .I1(\\first_edge_taps_r_reg_n_0_[5] ),\n .O(\\cnt_idel_dec_cpt_r[4]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\cnt_idel_dec_cpt_r[4]_i_9 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[4] ),\n .I1(\\first_edge_taps_r_reg_n_0_[4] ),\n .O(\\cnt_idel_dec_cpt_r[4]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'h0000008800222000)) \n \\cnt_idel_dec_cpt_r[5]_i_1 \n (.I0(\\cnt_idel_dec_cpt_r[5]_i_3_n_0 ),\n .I1(out[3]),\n .I2(store_sr_req_r_reg_0),\n .I3(out[1]),\n .I4(out[2]),\n .I5(out[0]),\n .O(\\cnt_idel_dec_cpt_r[5]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8000)) \n \\cnt_idel_dec_cpt_r[5]_i_10 \n (.I0(cnt_idel_dec_cpt_r2[4]),\n .I1(cnt_idel_dec_cpt_r2[2]),\n .I2(cnt_idel_dec_cpt_r2[1]),\n .I3(cnt_idel_dec_cpt_r2[3]),\n .O(\\cnt_idel_dec_cpt_r[5]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'h2B222222BBBB2B22)) \n \\cnt_idel_dec_cpt_r[5]_i_11 \n (.I0(right_edge_taps_r__0[3]),\n .I1(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .I3(right_edge_taps_r__0[1]),\n .I4(right_edge_taps_r__0[2]),\n .I5(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .O(\\cnt_idel_dec_cpt_r[5]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\cnt_idel_dec_cpt_r[5]_i_12 \n (.I0(\\second_edge_taps_r_reg_n_0_[5] ),\n .I1(\\first_edge_taps_r_reg_n_0_[5] ),\n .O(\\cnt_idel_dec_cpt_r[5]_i_12_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\cnt_idel_dec_cpt_r[5]_i_13 \n (.I0(\\second_edge_taps_r_reg_n_0_[4] ),\n .I1(\\first_edge_taps_r_reg_n_0_[4] ),\n .O(\\cnt_idel_dec_cpt_r[5]_i_13_n_0 ));\n LUT3 #(\n .INIT(8'h41)) \n \\cnt_idel_dec_cpt_r[5]_i_3 \n (.I0(cal1_state_r),\n .I1(out[4]),\n .I2(out[3]),\n .O(\\cnt_idel_dec_cpt_r[5]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\cnt_idel_dec_cpt_r[5]_i_4 \n (.I0(\\rdlvl_cpt_tap_cnt_reg[4] ),\n .I1(\\rdlvl_cpt_tap_cnt_reg[1] ),\n .I2(\\rdlvl_cpt_tap_cnt_reg[2] ),\n .I3(\\calib_sel_reg[3]_0 [1]),\n .I4(\\calib_sel_reg[3]_0 [0]),\n .I5(\\calib_sel_reg[3]_0 [2]),\n .O(store_sr_req_r_reg_0));\n LUT5 #(\n .INIT(32'hB88BB8B8)) \n \\cnt_idel_dec_cpt_r[5]_i_5 \n (.I0(\\calib_sel_reg[3]_0 [2]),\n .I1(out[1]),\n .I2(\\cnt_idel_dec_cpt_r_reg_n_0_[5] ),\n .I3(\\cnt_idel_dec_cpt_r_reg_n_0_[4] ),\n .I4(\\cnt_idel_dec_cpt_r[4]_i_3_n_0 ),\n .O(\\cnt_idel_dec_cpt_r[5]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hF00F0F0F11111111)) \n \\cnt_idel_dec_cpt_r[5]_i_6 \n (.I0(\\cnt_idel_dec_cpt_r[5]_i_7_n_0 ),\n .I1(\\cnt_idel_dec_cpt_r[5]_i_8_n_0 ),\n .I2(\\cnt_idel_dec_cpt_r_reg[5]_i_9_n_1 ),\n .I3(\\cnt_idel_dec_cpt_r[5]_i_10_n_0 ),\n .I4(cnt_idel_dec_cpt_r2[5]),\n .I5(\\cnt_idel_dec_cpt_r_reg[0]_0 ),\n .O(\\cnt_idel_dec_cpt_r[5]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h9A59AAAA55559A59)) \n \\cnt_idel_dec_cpt_r[5]_i_7 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[5] ),\n .I1(right_edge_taps_r__0[4]),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .I3(\\cnt_idel_dec_cpt_r[5]_i_11_n_0 ),\n .I4(\\tap_cnt_cpt_r_reg_n_0_[4] ),\n .I5(right_edge_taps_r__0[5]),\n .O(\\cnt_idel_dec_cpt_r[5]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000001)) \n \\cnt_idel_dec_cpt_r[5]_i_8 \n (.I0(right_edge_taps_r__0[2]),\n .I1(right_edge_taps_r__0[3]),\n .I2(right_edge_taps_r__0[1]),\n .I3(right_edge_taps_r__0[0]),\n .I4(right_edge_taps_r__0[5]),\n .I5(right_edge_taps_r__0[4]),\n .O(\\cnt_idel_dec_cpt_r[5]_i_8_n_0 ));\n FDRE \\cnt_idel_dec_cpt_r_reg[0] \n (.C(CLK),\n .CE(\\cnt_idel_dec_cpt_r[5]_i_1_n_0 ),\n .D(cnt_idel_dec_cpt_r[0]),\n .Q(\\cnt_idel_dec_cpt_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\cnt_idel_dec_cpt_r_reg[1] \n (.C(CLK),\n .CE(\\cnt_idel_dec_cpt_r[5]_i_1_n_0 ),\n .D(cnt_idel_dec_cpt_r[1]),\n .Q(\\cnt_idel_dec_cpt_r_reg_n_0_[1] ),\n .R(1'b0));\n CARRY4 \\cnt_idel_dec_cpt_r_reg[1]_i_2 \n (.CI(1'b0),\n .CO({\\cnt_idel_dec_cpt_r_reg[1]_i_2_n_0 ,\\cnt_idel_dec_cpt_r_reg[1]_i_2_n_1 ,\\cnt_idel_dec_cpt_r_reg[1]_i_2_n_2 ,\\cnt_idel_dec_cpt_r_reg[1]_i_2_n_3 }),\n .CYINIT(1'b1),\n .DI({\\second_edge_taps_r_reg_n_0_[3] ,\\second_edge_taps_r_reg_n_0_[2] ,\\second_edge_taps_r_reg_n_0_[1] ,\\second_edge_taps_r_reg_n_0_[0] }),\n .O({cnt_idel_dec_cpt_r2[3:1],\\NLW_cnt_idel_dec_cpt_r_reg[1]_i_2_O_UNCONNECTED [0]}),\n .S({\\cnt_idel_dec_cpt_r[1]_i_5_n_0 ,\\cnt_idel_dec_cpt_r[1]_i_6_n_0 ,\\cnt_idel_dec_cpt_r[1]_i_7_n_0 ,\\cnt_idel_dec_cpt_r[1]_i_8_n_0 }));\n CARRY4 \\cnt_idel_dec_cpt_r_reg[1]_i_9 \n (.CI(1'b0),\n .CO({\\cnt_idel_dec_cpt_r_reg[1]_i_9_n_0 ,\\cnt_idel_dec_cpt_r_reg[1]_i_9_n_1 ,\\cnt_idel_dec_cpt_r_reg[1]_i_9_n_2 ,\\cnt_idel_dec_cpt_r_reg[1]_i_9_n_3 }),\n .CYINIT(1'b1),\n .DI({\\tap_cnt_cpt_r_reg_n_0_[3] ,\\tap_cnt_cpt_r_reg_n_0_[2] ,\\tap_cnt_cpt_r_reg_n_0_[1] ,\\tap_cnt_cpt_r_reg_n_0_[0] }),\n .O({\\cnt_idel_dec_cpt_r_reg[1]_i_9_n_4 ,\\cnt_idel_dec_cpt_r_reg[1]_i_9_n_5 ,\\cnt_idel_dec_cpt_r_reg[1]_i_9_n_6 ,\\NLW_cnt_idel_dec_cpt_r_reg[1]_i_9_O_UNCONNECTED [0]}),\n .S({\\cnt_idel_dec_cpt_r[1]_i_11_n_0 ,\\cnt_idel_dec_cpt_r[1]_i_12_n_0 ,\\cnt_idel_dec_cpt_r[1]_i_13_n_0 ,\\cnt_idel_dec_cpt_r[1]_i_14_n_0 }));\n FDRE \\cnt_idel_dec_cpt_r_reg[2] \n (.C(CLK),\n .CE(\\cnt_idel_dec_cpt_r[5]_i_1_n_0 ),\n .D(cnt_idel_dec_cpt_r[2]),\n .Q(\\cnt_idel_dec_cpt_r_reg_n_0_[2] ),\n .R(1'b0));\n MUXF7 \\cnt_idel_dec_cpt_r_reg[2]_i_1 \n (.I0(\\cnt_idel_dec_cpt_r[2]_i_2_n_0 ),\n .I1(\\cnt_idel_dec_cpt_r[2]_i_3_n_0 ),\n .O(cnt_idel_dec_cpt_r[2]),\n .S(out[0]));\n FDRE \\cnt_idel_dec_cpt_r_reg[3] \n (.C(CLK),\n .CE(\\cnt_idel_dec_cpt_r[5]_i_1_n_0 ),\n .D(cnt_idel_dec_cpt_r[3]),\n .Q(\\cnt_idel_dec_cpt_r_reg_n_0_[3] ),\n .R(1'b0));\n MUXF7 \\cnt_idel_dec_cpt_r_reg[3]_i_1 \n (.I0(\\cnt_idel_dec_cpt_r[3]_i_2_n_0 ),\n .I1(\\cnt_idel_dec_cpt_r[3]_i_3_n_0 ),\n .O(cnt_idel_dec_cpt_r[3]),\n .S(out[0]));\n FDRE \\cnt_idel_dec_cpt_r_reg[4] \n (.C(CLK),\n .CE(\\cnt_idel_dec_cpt_r[5]_i_1_n_0 ),\n .D(cnt_idel_dec_cpt_r[4]),\n .Q(\\cnt_idel_dec_cpt_r_reg_n_0_[4] ),\n .R(1'b0));\n MUXF7 \\cnt_idel_dec_cpt_r_reg[4]_i_2 \n (.I0(\\cnt_idel_dec_cpt_r[4]_i_4_n_0 ),\n .I1(\\cnt_idel_dec_cpt_r[4]_i_5_n_0 ),\n .O(\\cnt_idel_dec_cpt_r_reg[4]_i_2_n_0 ),\n .S(\\cnt_idel_dec_cpt_r_reg[0]_0 ));\n CARRY4 \\cnt_idel_dec_cpt_r_reg[4]_i_6 \n (.CI(\\cnt_idel_dec_cpt_r_reg[1]_i_9_n_0 ),\n .CO({\\NLW_cnt_idel_dec_cpt_r_reg[4]_i_6_CO_UNCONNECTED [3:1],\\cnt_idel_dec_cpt_r_reg[4]_i_6_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,\\tap_cnt_cpt_r_reg_n_0_[4] }),\n .O({\\NLW_cnt_idel_dec_cpt_r_reg[4]_i_6_O_UNCONNECTED [3:2],\\cnt_idel_dec_cpt_r_reg[4]_i_6_n_6 ,\\cnt_idel_dec_cpt_r_reg[4]_i_6_n_7 }),\n .S({1'b0,1'b0,\\cnt_idel_dec_cpt_r[4]_i_8_n_0 ,\\cnt_idel_dec_cpt_r[4]_i_9_n_0 }));\n FDRE \\cnt_idel_dec_cpt_r_reg[5] \n (.C(CLK),\n .CE(\\cnt_idel_dec_cpt_r[5]_i_1_n_0 ),\n .D(cnt_idel_dec_cpt_r[5]),\n .Q(\\cnt_idel_dec_cpt_r_reg_n_0_[5] ),\n .R(1'b0));\n MUXF7 \\cnt_idel_dec_cpt_r_reg[5]_i_2 \n (.I0(\\cnt_idel_dec_cpt_r[5]_i_5_n_0 ),\n .I1(\\cnt_idel_dec_cpt_r[5]_i_6_n_0 ),\n .O(cnt_idel_dec_cpt_r[5]),\n .S(out[0]));\n CARRY4 \\cnt_idel_dec_cpt_r_reg[5]_i_9 \n (.CI(\\cnt_idel_dec_cpt_r_reg[1]_i_2_n_0 ),\n .CO({\\NLW_cnt_idel_dec_cpt_r_reg[5]_i_9_CO_UNCONNECTED [3],\\cnt_idel_dec_cpt_r_reg[5]_i_9_n_1 ,\\NLW_cnt_idel_dec_cpt_r_reg[5]_i_9_CO_UNCONNECTED [1],\\cnt_idel_dec_cpt_r_reg[5]_i_9_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,\\second_edge_taps_r_reg_n_0_[5] ,\\second_edge_taps_r_reg_n_0_[4] }),\n .O({\\NLW_cnt_idel_dec_cpt_r_reg[5]_i_9_O_UNCONNECTED [3:2],cnt_idel_dec_cpt_r2[5:4]}),\n .S({1'b0,1'b1,\\cnt_idel_dec_cpt_r[5]_i_12_n_0 ,\\cnt_idel_dec_cpt_r[5]_i_13_n_0 }));\n LUT6 #(\n .INIT(64'h00000000FFFFFFF7)) \n \\cnt_shift_r[0]_i_1 \n (.I0(rdlvl_stg1_start_reg),\n .I1(phy_rddata_en_1),\n .I2(cnt_shift_r_reg__0[1]),\n .I3(cnt_shift_r_reg__0[3]),\n .I4(cnt_shift_r_reg__0[2]),\n .I5(cnt_shift_r_reg__0[0]),\n .O(p_0_in__1[0]));\n (* SOFT_HLUTNM = \"soft_lutpair237\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\cnt_shift_r[1]_i_1 \n (.I0(cnt_shift_r_reg__0[1]),\n .I1(cnt_shift_r_reg__0[0]),\n .O(p_0_in__1[1]));\n (* SOFT_HLUTNM = \"soft_lutpair237\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\cnt_shift_r[2]_i_1 \n (.I0(cnt_shift_r_reg__0[2]),\n .I1(cnt_shift_r_reg__0[0]),\n .I2(cnt_shift_r_reg__0[1]),\n .O(p_0_in__1[2]));\n (* SOFT_HLUTNM = \"soft_lutpair199\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\cnt_shift_r[3]_i_3 \n (.I0(cnt_shift_r_reg__0[3]),\n .I1(cnt_shift_r_reg__0[1]),\n .I2(cnt_shift_r_reg__0[0]),\n .I3(cnt_shift_r_reg__0[2]),\n .O(p_0_in__1[3]));\n FDSE \\cnt_shift_r_reg[0] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__1[0]),\n .Q(cnt_shift_r_reg__0[0]),\n .S(rdlvl_stg1_start_reg_0));\n FDRE \\cnt_shift_r_reg[1] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__1[1]),\n .Q(cnt_shift_r_reg__0[1]),\n .R(rdlvl_stg1_start_reg_0));\n FDRE \\cnt_shift_r_reg[2] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__1[2]),\n .Q(cnt_shift_r_reg__0[2]),\n .R(rdlvl_stg1_start_reg_0));\n FDRE \\cnt_shift_r_reg[3] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__1[3]),\n .Q(cnt_shift_r_reg__0[3]),\n .R(rdlvl_stg1_start_reg_0));\n LUT2 #(\n .INIT(4'h8)) \n \\ctl_lane_cnt[1]_i_2 \n (.I0(pi_fine_dly_dec_done),\n .I1(dqs_po_dec_done),\n .O(cmd_delay_start0));\n LUT5 #(\n .INIT(32'h00008000)) \n detect_edge_done_r_i_1\n (.I0(pb_detect_edge_done_r[6]),\n .I1(pb_detect_edge_done_r[7]),\n .I2(pb_detect_edge_done_r[4]),\n .I3(pb_detect_edge_done_r[5]),\n .I4(detect_edge_done_r_i_2_n_0),\n .O(detect_edge_done_r_i_1_n_0));\n LUT4 #(\n .INIT(16'h7FFF)) \n detect_edge_done_r_i_2\n (.I0(pb_detect_edge_done_r[1]),\n .I1(pb_detect_edge_done_r[0]),\n .I2(pb_detect_edge_done_r[3]),\n .I3(pb_detect_edge_done_r[2]),\n .O(detect_edge_done_r_i_2_n_0));\n FDRE detect_edge_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(detect_edge_done_r_i_1_n_0),\n .Q(detect_edge_done_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0000000000005554)) \n \\done_cnt[0]_i_1 \n (.I0(done_cnt[0]),\n .I1(done_cnt[1]),\n .I2(done_cnt[3]),\n .I3(done_cnt[2]),\n .I4(done_cnt1),\n .I5(rstdiv0_sync_r1_reg_rep__23),\n .O(\\done_cnt[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair194\" *) \n LUT5 #(\n .INIT(32'hFFAAAAFE)) \n \\done_cnt[1]_i_1 \n (.I0(done_cnt1),\n .I1(done_cnt[2]),\n .I2(done_cnt[3]),\n .I3(done_cnt[1]),\n .I4(done_cnt[0]),\n .O(\\done_cnt[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h000000000000EE10)) \n \\done_cnt[2]_i_1 \n (.I0(done_cnt[0]),\n .I1(done_cnt[1]),\n .I2(done_cnt[3]),\n .I3(done_cnt[2]),\n .I4(done_cnt1),\n .I5(rstdiv0_sync_r1_reg_rep__23),\n .O(\\done_cnt[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair194\" *) \n LUT5 #(\n .INIT(32'hFAFAFAEA)) \n \\done_cnt[3]_i_1 \n (.I0(done_cnt1),\n .I1(done_cnt[2]),\n .I2(done_cnt[3]),\n .I3(done_cnt[1]),\n .I4(done_cnt[0]),\n .O(\\done_cnt[3]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8F88)) \n \\done_cnt[3]_i_2 \n (.I0(\\done_cnt[3]_i_3_n_0 ),\n .I1(\\done_cnt[3]_i_4_n_0 ),\n .I2(\\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ),\n .I3(p_0_in539_in),\n .O(done_cnt1));\n (* SOFT_HLUTNM = \"soft_lutpair92\" *) \n LUT4 #(\n .INIT(16'h0004)) \n \\done_cnt[3]_i_3 \n (.I0(done_cnt[1]),\n .I1(done_cnt[0]),\n .I2(done_cnt[3]),\n .I3(done_cnt[2]),\n .O(\\done_cnt[3]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFF7)) \n \\done_cnt[3]_i_4 \n (.I0(cal1_state_r),\n .I1(out[0]),\n .I2(out[1]),\n .I3(out[3]),\n .I4(out[4]),\n .I5(out[2]),\n .O(\\done_cnt[3]_i_4_n_0 ));\n FDRE \\done_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\done_cnt[0]_i_1_n_0 ),\n .Q(done_cnt[0]),\n .R(1'b0));\n FDRE \\done_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\done_cnt[1]_i_1_n_0 ),\n .Q(done_cnt[1]),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE \\done_cnt_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\done_cnt[2]_i_1_n_0 ),\n .Q(done_cnt[2]),\n .R(1'b0));\n FDRE \\done_cnt_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\done_cnt[3]_i_1_n_0 ),\n .Q(done_cnt[3]),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE dqs_po_dec_done_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(dqs_po_dec_done),\n .Q(dqs_po_dec_done_r1),\n .R(1'b0));\n FDRE dqs_po_dec_done_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(dqs_po_dec_done_r1),\n .Q(dqs_po_dec_done_r2),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hFFFF22F2)) \n fine_dly_dec_done_r1_i_1\n (.I0(fine_dly_dec_done_r1_i_2_n_0),\n .I1(fine_dly_dec_done_r1_i_3_n_0),\n .I2(dqs_po_dec_done_r2),\n .I3(\\pi_rdval_cnt_reg[1]_0 ),\n .I4(fine_dly_dec_done_r1),\n .O(fine_dly_dec_done_r1_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair202\" *) \n LUT4 #(\n .INIT(16'h0010)) \n fine_dly_dec_done_r1_i_2\n (.I0(pi_rdval_cnt[1]),\n .I1(pi_rdval_cnt[2]),\n .I2(pi_rdval_cnt[0]),\n .I3(pi_rdval_cnt[4]),\n .O(fine_dly_dec_done_r1_i_2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair235\" *) \n LUT3 #(\n .INIT(8'hFB)) \n fine_dly_dec_done_r1_i_3\n (.I0(pi_rdval_cnt[5]),\n .I1(pi_en_stg2_f_timing_reg_0),\n .I2(pi_rdval_cnt[3]),\n .O(fine_dly_dec_done_r1_i_3_n_0));\n FDRE fine_dly_dec_done_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(fine_dly_dec_done_r1_i_1_n_0),\n .Q(fine_dly_dec_done_r1),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE fine_dly_dec_done_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(fine_dly_dec_done_r1),\n .Q(fine_dly_dec_done_r2),\n .R(1'b0));\n LUT3 #(\n .INIT(8'h80)) \n \\first_edge_taps_r[5]_i_1 \n (.I0(\\right_edge_taps_r_reg[0]_1 ),\n .I1(out[3]),\n .I2(out[2]),\n .O(\\first_edge_taps_r[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8888888800202020)) \n \\first_edge_taps_r[5]_i_2 \n (.I0(\\right_edge_taps_r_reg[0]_1 ),\n .I1(out[3]),\n .I2(\\right_edge_taps_r_reg[0]_2 ),\n .I3(found_stable_eye_last_r),\n .I4(\\right_edge_taps_r_reg[0]_0 ),\n .I5(out[2]),\n .O(\\first_edge_taps_r[5]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'h2000)) \n \\first_edge_taps_r[5]_i_3 \n (.I0(out[4]),\n .I1(cal1_state_r),\n .I2(out[0]),\n .I3(out[1]),\n .O(\\right_edge_taps_r_reg[0]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair223\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\first_edge_taps_r[5]_i_4 \n (.I0(detect_edge_done_r),\n .I1(found_first_edge_r_reg_0),\n .I2(tap_limit_cpt_r),\n .O(\\right_edge_taps_r_reg[0]_2 ));\n FDRE \\first_edge_taps_r_reg[0] \n (.C(CLK),\n .CE(\\first_edge_taps_r[5]_i_2_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .Q(\\first_edge_taps_r_reg_n_0_[0] ),\n .R(\\first_edge_taps_r[5]_i_1_n_0 ));\n FDRE \\first_edge_taps_r_reg[1] \n (.C(CLK),\n .CE(\\first_edge_taps_r[5]_i_2_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .Q(\\first_edge_taps_r_reg_n_0_[1] ),\n .R(\\first_edge_taps_r[5]_i_1_n_0 ));\n FDRE \\first_edge_taps_r_reg[2] \n (.C(CLK),\n .CE(\\first_edge_taps_r[5]_i_2_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .Q(\\first_edge_taps_r_reg_n_0_[2] ),\n .R(\\first_edge_taps_r[5]_i_1_n_0 ));\n FDRE \\first_edge_taps_r_reg[3] \n (.C(CLK),\n .CE(\\first_edge_taps_r[5]_i_2_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .Q(\\first_edge_taps_r_reg_n_0_[3] ),\n .R(\\first_edge_taps_r[5]_i_1_n_0 ));\n FDRE \\first_edge_taps_r_reg[4] \n (.C(CLK),\n .CE(\\first_edge_taps_r[5]_i_2_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[4] ),\n .Q(\\first_edge_taps_r_reg_n_0_[4] ),\n .R(\\first_edge_taps_r[5]_i_1_n_0 ));\n FDRE \\first_edge_taps_r_reg[5] \n (.C(CLK),\n .CE(\\first_edge_taps_r[5]_i_2_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[5] ),\n .Q(\\first_edge_taps_r_reg_n_0_[5] ),\n .R(\\first_edge_taps_r[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n found_edge_r_i_1\n (.I0(found_edge_r_reg_1),\n .I1(found_edge_r_reg_2),\n .I2(found_edge_r_reg_0),\n .I3(found_edge_r_reg_3),\n .I4(found_edge_r_i_2_n_0),\n .O(found_edge_r_i_1_n_0));\n LUT4 #(\n .INIT(16'hFFFE)) \n found_edge_r_i_2\n (.I0(\\gen_track_left_edge[7].pb_found_edge_r_reg[7]_0 ),\n .I1(\\gen_track_left_edge[4].pb_found_edge_r_reg[4]_0 ),\n .I2(\\gen_track_left_edge[6].pb_found_edge_r_reg[6]_0 ),\n .I3(\\gen_track_left_edge[0].pb_found_edge_r_reg[0]_0 ),\n .O(found_edge_r_i_2_n_0));\n FDRE found_edge_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(found_edge_r_i_1_n_0),\n .Q(found_first_edge_r_reg_0),\n .R(1'b0));\n FDRE found_first_edge_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(found_edge_r_reg_4),\n .Q(\\right_edge_taps_r_reg[0]_0 ),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE found_second_edge_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(found_stable_eye_last_r_reg_1),\n .Q(\\cnt_idel_dec_cpt_r_reg[0]_0 ),\n .R(SR));\n FDRE found_stable_eye_last_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(found_stable_eye_r_reg_0),\n .Q(found_stable_eye_last_r),\n .R(pb_detect_edge_setup));\n LUT5 #(\n .INIT(32'h00008000)) \n found_stable_eye_r_i_1\n (.I0(\\gen_track_left_edge[7].pb_found_stable_eye_r_reg ),\n .I1(\\gen_track_left_edge[6].pb_found_stable_eye_r_reg ),\n .I2(\\gen_track_left_edge[4].pb_found_stable_eye_r_reg ),\n .I3(\\gen_track_left_edge[5].pb_found_stable_eye_r_reg ),\n .I4(found_stable_eye_r_i_2_n_0),\n .O(found_stable_eye_r_i_1_n_0));\n LUT4 #(\n .INIT(16'h7FFF)) \n found_stable_eye_r_i_2\n (.I0(\\gen_track_left_edge[1].pb_found_stable_eye_r_reg ),\n .I1(\\gen_track_left_edge[0].pb_found_stable_eye_r_reg ),\n .I2(\\gen_track_left_edge[3].pb_found_stable_eye_r_reg ),\n .I3(\\gen_track_left_edge[2].pb_found_stable_eye_r_reg ),\n .O(found_stable_eye_r_i_2_n_0));\n FDRE found_stable_eye_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(found_stable_eye_r_i_1_n_0),\n .Q(found_stable_eye_last_r_reg_0),\n .R(1'b0));\n LUT3 #(\n .INIT(8'hB8)) \n \\gen_byte_sel_div1.byte_sel_cnt[0]_i_4 \n (.I0(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .I1(\\gen_byte_sel_div1.byte_sel_cnt[2]_i_8_n_0 ),\n .I2(regl_dqs_cnt_r[0]),\n .O(pi_stg2_rdlvl_cnt[0]));\n (* SOFT_HLUTNM = \"soft_lutpair231\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_byte_sel_div1.byte_sel_cnt[1]_i_4 \n (.I0(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I1(\\gen_byte_sel_div1.byte_sel_cnt[2]_i_8_n_0 ),\n .I2(regl_dqs_cnt_r[1]),\n .O(pi_stg2_rdlvl_cnt[1]));\n LUT6 #(\n .INIT(64'hF0F4F0F4FFF4F0F4)) \n \\gen_byte_sel_div1.byte_sel_cnt[2]_i_3 \n (.I0(\\gen_byte_sel_div1.byte_sel_cnt[2]_i_5_n_0 ),\n .I1(\\prbs_dqs_cnt_r_reg[2] ),\n .I2(\\po_stg2_wrcal_cnt_reg[2] ),\n .I3(\\gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 ),\n .I4(regl_dqs_cnt_r[2]),\n .I5(\\gen_byte_sel_div1.byte_sel_cnt[2]_i_8_n_0 ),\n .O(\\gen_byte_sel_div1.byte_sel_cnt_reg[2] ));\n (* SOFT_HLUTNM = \"soft_lutpair198\" *) \n LUT4 #(\n .INIT(16'hDFFF)) \n \\gen_byte_sel_div1.byte_sel_cnt[2]_i_5 \n (.I0(rdlvl_stg1_done_r1_reg),\n .I1(prbs_rdlvl_done_reg),\n .I2(wrcal_done_reg),\n .I3(oclkdelay_calib_done_r_reg),\n .O(\\gen_byte_sel_div1.byte_sel_cnt[2]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair207\" *) \n LUT4 #(\n .INIT(16'h08FF)) \n \\gen_byte_sel_div1.byte_sel_cnt[2]_i_7 \n (.I0(oclkdelay_calib_done_r_reg),\n .I1(wrcal_done_reg),\n .I2(rdlvl_stg1_done_r1_reg),\n .I3(mpr_rdlvl_done_r1_reg_0),\n .O(\\gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFF7)) \n \\gen_byte_sel_div1.byte_sel_cnt[2]_i_8 \n (.I0(cal1_state_r),\n .I1(out[1]),\n .I2(out[3]),\n .I3(out[0]),\n .I4(out[4]),\n .I5(out[2]),\n .O(\\gen_byte_sel_div1.byte_sel_cnt[2]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'h7FFFFFFFFFFFFFFF)) \n \\gen_byte_sel_div1.calib_in_common_i_3 \n (.I0(oclkdelay_calib_done_r_reg),\n .I1(wrcal_done_reg),\n .I2(prbs_rdlvl_done_reg),\n .I3(rdlvl_stg1_done_r1_reg),\n .I4(wr_level_done_reg),\n .I5(mpr_rdlvl_done_r1_reg_0),\n .O(\\gen_byte_sel_div1.calib_in_common_reg ));\n FDRE \\gen_mux_rd[0].mux_rd_fall0_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_8 ),\n .Q(\\gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[0].mux_rd_fall1_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_24 ),\n .Q(\\gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[0].mux_rd_fall2_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_40 ),\n .Q(\\gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[0].mux_rd_fall3_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_56 ),\n .Q(\\gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[0].mux_rd_rise0_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_0 ),\n .Q(\\gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[0].mux_rd_rise1_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_16 ),\n .Q(\\gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[0].mux_rd_rise2_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_32 ),\n .Q(\\gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[0].mux_rd_rise3_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_48 ),\n .Q(\\gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[1].mux_rd_fall0_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_9 ),\n .Q(\\gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[1].mux_rd_fall1_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_25 ),\n .Q(\\gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[1].mux_rd_fall2_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_41 ),\n .Q(\\gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[1].mux_rd_fall3_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_57 ),\n .Q(\\gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[1].mux_rd_rise0_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_1 ),\n .Q(\\gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[1].mux_rd_rise1_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_17 ),\n .Q(\\gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[1].mux_rd_rise2_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_33 ),\n .Q(\\gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[1].mux_rd_rise3_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_49 ),\n .Q(\\gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[2].mux_rd_fall0_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_10 ),\n .Q(\\gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[2].mux_rd_fall1_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_26 ),\n .Q(\\gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[2].mux_rd_fall2_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_42 ),\n .Q(\\gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[2].mux_rd_fall3_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_58 ),\n .Q(\\gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[2].mux_rd_rise0_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_2 ),\n .Q(\\gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[2].mux_rd_rise1_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_18 ),\n .Q(\\gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[2].mux_rd_rise2_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_34 ),\n .Q(\\gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[2].mux_rd_rise3_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_50 ),\n .Q(\\gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[3].mux_rd_fall0_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_11 ),\n .Q(\\gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[3].mux_rd_fall1_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_27 ),\n .Q(\\gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[3].mux_rd_fall2_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_43 ),\n .Q(\\gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[3].mux_rd_fall3_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_59 ),\n .Q(\\gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[3].mux_rd_rise0_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_3 ),\n .Q(\\gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[3].mux_rd_rise1_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_19 ),\n .Q(\\gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[3].mux_rd_rise2_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_35 ),\n .Q(\\gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[3].mux_rd_rise3_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_51 ),\n .Q(\\gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[4].mux_rd_fall0_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_12 ),\n .Q(\\gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[4].mux_rd_fall1_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_28 ),\n .Q(\\gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[4].mux_rd_fall2_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_44 ),\n .Q(\\gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[4].mux_rd_fall3_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_60 ),\n .Q(\\gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[4].mux_rd_rise0_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_4 ),\n .Q(\\gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[4].mux_rd_rise1_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_20 ),\n .Q(\\gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[4].mux_rd_rise2_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_36 ),\n .Q(\\gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[4].mux_rd_rise3_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_52 ),\n .Q(\\gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[5].mux_rd_fall0_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_13 ),\n .Q(\\gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[5].mux_rd_fall1_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_29 ),\n .Q(\\gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[5].mux_rd_fall2_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_45 ),\n .Q(\\gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[5].mux_rd_fall3_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_61 ),\n .Q(\\gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[5].mux_rd_rise0_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_5 ),\n .Q(\\gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[5].mux_rd_rise1_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_21 ),\n .Q(\\gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[5].mux_rd_rise2_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_37 ),\n .Q(\\gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[5].mux_rd_rise3_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_53 ),\n .Q(\\gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[6].mux_rd_fall0_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_14 ),\n .Q(\\gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[6].mux_rd_fall1_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_30 ),\n .Q(\\gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[6].mux_rd_fall2_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_46 ),\n .Q(\\gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[6].mux_rd_fall3_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_62 ),\n .Q(\\gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[6].mux_rd_rise0_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_6 ),\n .Q(\\gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[6].mux_rd_rise1_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_22 ),\n .Q(\\gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[6].mux_rd_rise2_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_38 ),\n .Q(\\gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[6].mux_rd_rise3_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_54 ),\n .Q(\\gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[7].mux_rd_fall0_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_15 ),\n .Q(\\gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[7].mux_rd_fall1_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_31 ),\n .Q(\\gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[7].mux_rd_fall2_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_47 ),\n .Q(\\gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[7].mux_rd_fall3_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_63 ),\n .Q(\\gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[7].mux_rd_rise0_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_7 ),\n .Q(\\gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[7].mux_rd_rise1_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_23 ),\n .Q(\\gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[7].mux_rd_rise2_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_39 ),\n .Q(\\gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ),\n .R(1'b0));\n FDRE \\gen_mux_rd[7].mux_rd_rise3_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rd_mux_sel_r_reg[1]_55 ),\n .Q(\\gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7] ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_52 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0]_140 ),\n .R(1'b0));\n LUT3 #(\n .INIT(8'hA8)) \n \\gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r[0][0]_i_1 \n (.I0(\\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0]_0 ),\n .I1(sr_valid_r1_reg_0),\n .I2(mpr_valid_r1_reg_0),\n .O(store_sr_r0));\n FDRE \\gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_36 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0]_132 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_20 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0]_164 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_12 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0]_172 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_4 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0]_180 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_44 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0]_148 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_28 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0]_156 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_60 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0]_188 ),\n .R(1'b0));\n LUT2 #(\n .INIT(4'hE)) \n \\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r[0][0]_i_1 \n (.I0(sr_valid_r1_reg_0),\n .I1(mpr_valid_r1_reg_0),\n .O(store_sr_r1));\n FDRE \\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_52 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0]_68 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_36 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0]_108 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_20 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0]_124 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_12 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0]_100 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_4 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0]_92 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_44 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0]_76 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_28 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0]_84 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_60 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0]_116 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_53 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1]_141 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_37 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1]_133 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_21 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1]_165 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_13 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1]_173 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_5 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1]_181 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_45 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1]_149 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_29 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1]_157 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_61 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1]_189 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_53 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1]_69 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_37 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1]_109 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_21 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1]_125 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_13 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1]_101 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_5 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1]_93 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_45 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1]_77 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_29 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1]_85 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_61 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1]_117 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_54 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2]_142 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_38 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2]_134 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_22 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2]_166 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_14 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2]_174 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_6 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2]_182 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_46 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2]_150 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_30 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2]_158 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_62 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2]_190 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_54 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2]_70 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_38 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2]_110 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_22 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2]_126 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_14 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2]_102 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_6 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2]_94 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_46 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2]_78 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_30 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2]_86 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_62 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2]_118 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_55 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3]_143 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_39 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3]_135 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_23 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3]_167 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_15 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3]_175 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_7 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3]_183 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_47 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3]_151 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_31 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3]_159 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_63 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3]_191 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_55 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3]_71 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_39 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3]_111 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_23 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3]_127 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_15 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3]_103 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_7 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3]_95 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_47 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3]_79 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_31 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3]_87 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_63 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3]_119 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_56 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4]_144 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_40 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4]_136 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_24 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4]_168 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_16 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4]_176 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_8 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4]_184 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_48 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4]_152 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_32 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4]_160 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_64 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4]_192 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_56 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4]_72 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_40 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4]_112 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_24 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4]_128 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_16 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4]_104 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_8 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4]_96 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_48 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4]_80 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_32 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4]_88 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_64 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4]_120 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_57 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5]_145 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_41 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5]_137 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_25 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5]_169 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_17 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5]_177 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_9 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5]_185 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_49 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5]_153 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_33 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5]_161 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_65 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5]_193 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_57 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5]_73 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_41 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5]_113 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_25 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5]_129 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_17 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5]_105 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_9 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5]_97 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_49 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5]_81 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_33 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5]_89 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_65 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5]_121 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_58 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6]_146 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_42 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6]_138 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_26 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6]_170 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_18 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6]_178 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_10 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6]_186 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_50 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6]_154 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_34 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6]_162 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_66 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6]_194 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_58 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6]_74 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_42 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6]_114 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_26 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6]_130 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_18 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6]_106 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_10 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6]_98 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_50 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6]_82 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_34 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6]_90 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_66 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6]_122 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_59 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7]_147 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_43 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7]_139 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_27 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7]_171 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_19 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7]_179 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_11 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7]_187 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_51 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7]_155 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_35 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7]_163 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0] \n (.C(CLK),\n .CE(store_sr_r0),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_67 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7]_195 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_59 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7]_75 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_43 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7]_115 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_27 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7]_131 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_19 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7]_107 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_11 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7]_99 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_51 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7]_83 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_35 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7]_91 ),\n .R(1'b0));\n FDRE \\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7][0] \n (.C(CLK),\n .CE(store_sr_r1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_67 ),\n .Q(\\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7]_123 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_52 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair151\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_36 ),\n .O(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair167\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_20 ),\n .O(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall3_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_12 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall3_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise0_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_4 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise0_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair119\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_44 ),\n .O(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_28 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair159\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_60 ),\n .O(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall1_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_36 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall1_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair143\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_12 ),\n .O(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair135\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_4 ),\n .O(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise1_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_44 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise1_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair127\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_28 ),\n .O(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise3_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_60 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair112\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_52 ),\n .O(\\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_20 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall0_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_53 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall0_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair152\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_37 ),\n .O(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_21 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_13 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair136\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_5 ),\n .O(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise1_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_45 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise1_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair128\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_29 ),\n .O(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair160\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_61 ),\n .O(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair113\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_53 ),\n .O(\\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_37 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair168\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_21 ),\n .O(\\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_rise2_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_29 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_rise2_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair144\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_13 ),\n .O(\\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise0_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_5 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise0_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair120\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_45 ),\n .O(\\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise3_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_61 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise3_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall0_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_54 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_38 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair169\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_22 ),\n .O(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair145\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_14 ),\n .O(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair137\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_6 ),\n .O(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise1_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_46 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise1_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair129\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_30 ),\n .O(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise3_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_62 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair114\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_54 ),\n .O(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall2_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_22 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise0_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_6 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise0_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair121\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_46 ),\n .O(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_30 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair161\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_62 ),\n .O(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair153\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_38 ),\n .O(\\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_14 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair115\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_55 ),\n .O(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall1_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_39 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall1_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair170\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_23 ),\n .O(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_15 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair138\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_7 ),\n .O(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise1_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_47 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise1_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_31 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair162\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_63 ),\n .O(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall0_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_55 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall0_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair154\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_39 ),\n .O(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_23 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair146\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_15 ),\n .O(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair175\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_47 ),\n .O(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise3_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_63 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair130\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_31 ),\n .O(\\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_7 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_56 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair155\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_40 ),\n .O(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair171\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_24 ),\n .O(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall3_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_16 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall3_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise0_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_8 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise0_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair123\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_48 ),\n .O(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_32 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair163\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_64 ),\n .O(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall1_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_40 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall1_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair147\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_16 ),\n .O(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair139\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_8 ),\n .O(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise1_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_48 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise1_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair131\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_32 ),\n .O(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise3_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_64 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair116\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_56 ),\n .O(\\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_24 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_57 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair156\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_41 ),\n .O(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_25 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_17 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair140\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_9 ),\n .O(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise1_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_49 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise1_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair132\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_33 ),\n .O(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair164\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_65 ),\n .O(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair117\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_57 ),\n .O(\\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_41 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair172\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_25 ),\n .O(\\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_rise2_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_33 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_rise2_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair148\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_17 ),\n .O(\\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise0_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_9 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise0_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair124\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_49 ),\n .O(\\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise3_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_65 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise3_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall0_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_58 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_42 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair173\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_26 ),\n .O(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair149\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_18 ),\n .O(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair141\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_10 ),\n .O(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise1_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_50 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise1_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair133\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_34 ),\n .O(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise3_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_66 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair122\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_58 ),\n .O(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall2_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_26 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise0_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_10 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise0_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair125\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_50 ),\n .O(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_34 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair165\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_66 ),\n .O(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair157\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_42 ),\n .O(\\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_18 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair118\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_59 ),\n .O(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_43 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair174\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_27 ),\n .O(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_19 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair142\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_11 ),\n .O(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise1_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_51 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise1_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_35 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair166\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_67 ),\n .O(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall0_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_59 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall0_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair158\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_43 ),\n .O(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_27 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair150\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_19 ),\n .O(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair126\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_51 ),\n .O(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise3_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_67 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise3_r_reg ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair134\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1 \n (.I0(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_35 ),\n .O(\\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_11 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_pat_match_div4.idel_pat0_data_match_r_i_1 \n (.I0(idel_pat0_match_rise2_and_r),\n .I1(idel_pat0_match_fall2_and_r),\n .I2(idel_pat0_match_fall3_and_r),\n .I3(idel_pat0_match_rise0_and_r),\n .I4(\\gen_pat_match_div4.idel_pat0_data_match_r_i_2_n_0 ),\n .O(idel_pat0_data_match_r0__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_pat_match_div4.idel_pat0_data_match_r_i_2 \n (.I0(idel_pat0_match_fall0_and_r),\n .I1(idel_pat0_match_fall1_and_r),\n .I2(idel_pat0_match_rise3_and_r),\n .I3(idel_pat0_match_rise1_and_r),\n .O(\\gen_pat_match_div4.idel_pat0_data_match_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.idel_pat0_data_match_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(idel_pat0_data_match_r0__0),\n .Q(\\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg ),\n .I2(\\gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0 ),\n .I3(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall0_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg ),\n .I5(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall0_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.idel_pat0_match_fall0_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1_n_0 ),\n .Q(idel_pat0_match_fall0_and_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg ),\n .I2(\\gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0 ),\n .I3(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r_reg ),\n .I5(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.idel_pat0_match_fall1_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1_n_0 ),\n .Q(idel_pat0_match_fall1_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1 \n (.I0(\\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair186\" *) \n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.idel_pat0_match_fall2_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1_n_0 ),\n .Q(idel_pat0_match_fall2_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall3_r_reg ),\n .I4(\\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2_n_0 ),\n .O(\\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall3_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.idel_pat0_match_fall3_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1_n_0 ),\n .Q(idel_pat0_match_fall3_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1 \n (.I0(\\gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.idel_pat0_match_rise0_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1_n_0 ),\n .Q(idel_pat0_match_rise0_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1 \n (.I0(\\gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise1_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise1_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.idel_pat0_match_rise1_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1_n_0 ),\n .Q(idel_pat0_match_rise1_and_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair220\" *) \n LUT3 #(\n .INIT(8'h80)) \n \\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r_reg ),\n .I1(\\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2_n_0 ),\n .I2(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg ),\n .I5(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.idel_pat0_match_rise2_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1_n_0 ),\n .Q(idel_pat0_match_rise2_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1 \n (.I0(\\gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.idel_pat0_match_rise3_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1_n_0 ),\n .Q(idel_pat0_match_rise3_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_pat_match_div4.idel_pat1_data_match_r_i_1 \n (.I0(idel_pat1_match_rise2_and_r),\n .I1(idel_pat1_match_fall2_and_r),\n .I2(idel_pat1_match_fall3_and_r),\n .I3(idel_pat1_match_rise0_and_r),\n .I4(\\gen_pat_match_div4.idel_pat1_data_match_r_i_2_n_0 ),\n .O(idel_pat1_data_match_r0__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_pat_match_div4.idel_pat1_data_match_r_i_2 \n (.I0(idel_pat1_match_rise1_and_r),\n .I1(idel_pat1_match_fall1_and_r),\n .I2(idel_pat1_match_rise3_and_r),\n .I3(idel_pat1_match_fall0_and_r),\n .O(\\gen_pat_match_div4.idel_pat1_data_match_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.idel_pat1_data_match_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(idel_pat1_data_match_r0__0),\n .Q(\\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair224\" *) \n LUT3 #(\n .INIT(8'h80)) \n \\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg ),\n .I1(\\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2_n_0 ),\n .I2(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall0_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg__0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall0_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg__0 ),\n .I4(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg ),\n .I5(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.idel_pat1_match_fall0_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1_n_0 ),\n .Q(idel_pat1_match_fall0_and_r),\n .R(1'b0));\n LUT3 #(\n .INIT(8'h80)) \n \\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg ),\n .I1(\\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2_n_0 ),\n .I2(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg__0 ),\n .O(\\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall1_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall1_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg__0 ),\n .I4(\\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg ),\n .I5(\\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.idel_pat1_match_fall1_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1_n_0 ),\n .Q(idel_pat1_match_fall1_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1 \n (.I0(\\gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.idel_pat1_match_fall2_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1_n_0 ),\n .Q(idel_pat1_match_fall2_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1 \n (.I0(\\gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.idel_pat1_match_fall3_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1_n_0 ),\n .Q(idel_pat1_match_fall3_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1 \n (.I0(\\gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg__0 ),\n .I2(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg__0 ),\n .I3(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.idel_pat1_match_rise0_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1_n_0 ),\n .Q(idel_pat1_match_rise0_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1 \n (.I0(\\gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r_reg__0 ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r_reg__0 ),\n .I3(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.idel_pat1_match_rise1_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1_n_0 ),\n .Q(idel_pat1_match_rise1_and_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg ),\n .I2(\\gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0 ),\n .I3(\\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_rise2_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_rise2_r_reg ),\n .I5(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.idel_pat1_match_rise2_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1_n_0 ),\n .Q(idel_pat1_match_rise2_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1 \n (.I0(\\gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg ),\n .O(\\gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.idel_pat1_match_rise3_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1_n_0 ),\n .Q(idel_pat1_match_rise3_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_pat_match_div4.pat0_data_match_r_i_1 \n (.I0(pat0_match_fall2_and_r),\n .I1(pat0_match_rise2_and_r),\n .I2(pat0_match_fall3_and_r),\n .I3(pat0_match_rise0_and_r),\n .I4(\\gen_pat_match_div4.pat0_data_match_r_i_2_n_0 ),\n .O(pat0_data_match_r0__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_pat_match_div4.pat0_data_match_r_i_2 \n (.I0(pat0_match_rise1_and_r),\n .I1(pat0_match_fall1_and_r),\n .I2(pat0_match_rise3_and_r),\n .I3(pat0_match_fall0_and_r),\n .O(\\gen_pat_match_div4.pat0_data_match_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.pat0_data_match_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(pat0_data_match_r0__0),\n .Q(\\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair224\" *) \n LUT3 #(\n .INIT(8'h80)) \n \\gen_pat_match_div4.pat0_match_fall0_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall0_r_reg ),\n .I1(\\gen_pat_match_div4.pat0_match_fall0_and_r_i_2_n_0 ),\n .I2(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall0_r_reg ),\n .O(\\gen_pat_match_div4.pat0_match_fall0_and_r_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\gen_pat_match_div4.pat0_match_fall0_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r_reg__0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall0_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r_reg__0 ),\n .I3(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall0_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall0_r_reg ),\n .I5(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg ),\n .O(\\gen_pat_match_div4.pat0_match_fall0_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.pat0_match_fall0_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat0_match_fall0_and_r_i_1_n_0 ),\n .Q(pat0_match_fall0_and_r),\n .R(1'b0));\n LUT3 #(\n .INIT(8'h80)) \n \\gen_pat_match_div4.pat0_match_fall1_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r_reg__0 ),\n .I1(\\gen_pat_match_div4.pat0_match_fall1_and_r_i_2_n_0 ),\n .I2(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg ),\n .O(\\gen_pat_match_div4.pat0_match_fall1_and_r_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\gen_pat_match_div4.pat0_match_fall1_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall1_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall1_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r_reg__0 ),\n .I4(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall1_r_reg ),\n .I5(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r_reg ),\n .O(\\gen_pat_match_div4.pat0_match_fall1_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.pat0_match_fall1_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat0_match_fall1_and_r_i_1_n_0 ),\n .Q(pat0_match_fall1_and_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair186\" *) \n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.pat0_match_fall2_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r_reg ),\n .I4(\\gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0 ),\n .O(\\gen_pat_match_div4.pat0_match_fall2_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.pat0_match_fall2_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall2_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r_reg ),\n .O(\\gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.pat0_match_fall2_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat0_match_fall2_and_r_i_1_n_0 ),\n .Q(pat0_match_fall2_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.pat0_match_fall3_and_r_i_1 \n (.I0(\\gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall3_r_reg ),\n .O(\\gen_pat_match_div4.pat0_match_fall3_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.pat0_match_fall3_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r_reg ),\n .O(\\gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.pat0_match_fall3_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat0_match_fall3_and_r_i_1_n_0 ),\n .Q(pat0_match_fall3_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.pat0_match_rise0_and_r_i_1 \n (.I0(\\gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise0_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise0_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise0_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise0_r_reg ),\n .O(\\gen_pat_match_div4.pat0_match_rise0_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.pat0_match_rise0_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise0_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise0_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r_reg ),\n .O(\\gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.pat0_match_rise0_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat0_match_rise0_and_r_i_1_n_0 ),\n .Q(pat0_match_rise0_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.pat0_match_rise1_and_r_i_1 \n (.I0(\\gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r_reg__0 ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r_reg__0 ),\n .I3(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r_reg ),\n .O(\\gen_pat_match_div4.pat0_match_rise1_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.pat0_match_rise1_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise1_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise1_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise1_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise1_r_reg ),\n .O(\\gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.pat0_match_rise1_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat0_match_rise1_and_r_i_1_n_0 ),\n .Q(pat0_match_rise1_and_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair220\" *) \n LUT3 #(\n .INIT(8'h80)) \n \\gen_pat_match_div4.pat0_match_rise2_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r_reg__0 ),\n .I1(\\gen_pat_match_div4.pat0_match_rise2_and_r_i_2_n_0 ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r_reg ),\n .O(\\gen_pat_match_div4.pat0_match_rise2_and_r_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\gen_pat_match_div4.pat0_match_rise2_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_rise2_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r_reg__0 ),\n .I5(\\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_rise2_r_reg ),\n .O(\\gen_pat_match_div4.pat0_match_rise2_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.pat0_match_rise2_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat0_match_rise2_and_r_i_1_n_0 ),\n .Q(pat0_match_rise2_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.pat0_match_rise3_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise3_r_reg ),\n .I4(\\gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0 ),\n .O(\\gen_pat_match_div4.pat0_match_rise3_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.pat0_match_rise3_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise3_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise3_r_reg ),\n .O(\\gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.pat0_match_rise3_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat0_match_rise3_and_r_i_1_n_0 ),\n .Q(pat0_match_rise3_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_pat_match_div4.pat1_data_match_r_i_1 \n (.I0(pat1_match_rise2_and_r),\n .I1(pat1_match_fall1_and_r),\n .I2(pat1_match_fall3_and_r),\n .I3(pat1_match_rise0_and_r),\n .I4(\\gen_pat_match_div4.pat1_data_match_r_i_2_n_0 ),\n .O(pat1_data_match_r0__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_pat_match_div4.pat1_data_match_r_i_2 \n (.I0(pat1_match_fall0_and_r),\n .I1(pat1_match_rise1_and_r),\n .I2(pat1_match_rise3_and_r),\n .I3(pat1_match_fall2_and_r),\n .O(\\gen_pat_match_div4.pat1_data_match_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.pat1_data_match_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(pat1_data_match_r0__0),\n .Q(\\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\gen_pat_match_div4.pat1_match_fall0_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg ),\n .I2(\\gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0 ),\n .I3(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg ),\n .I5(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg ),\n .O(\\gen_pat_match_div4.pat1_match_fall0_and_r_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h80)) \n \\gen_pat_match_div4.pat1_match_fall0_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall0_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg ),\n .O(\\gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.pat1_match_fall0_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat1_match_fall0_and_r_i_1_n_0 ),\n .Q(pat1_match_fall0_and_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\gen_pat_match_div4.pat1_match_fall1_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg ),\n .I2(\\gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0 ),\n .I3(\\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg ),\n .I5(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg ),\n .O(\\gen_pat_match_div4.pat1_match_fall1_and_r_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h80)) \n \\gen_pat_match_div4.pat1_match_fall1_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall1_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg ),\n .O(\\gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.pat1_match_fall1_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat1_match_fall1_and_r_i_1_n_0 ),\n .Q(pat1_match_fall1_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_pat_match_div4.pat1_match_fall2_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg ),\n .I4(\\gen_pat_match_div4.pat1_match_fall2_and_r_i_2_n_0 ),\n .O(\\gen_pat_match_div4.pat1_match_fall2_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_pat_match_div4.pat1_match_fall2_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg ),\n .O(\\gen_pat_match_div4.pat1_match_fall2_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.pat1_match_fall2_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat1_match_fall2_and_r_i_1_n_0 ),\n .Q(pat1_match_fall2_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_pat_match_div4.pat1_match_fall3_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r_reg ),\n .I4(\\gen_pat_match_div4.pat1_match_fall3_and_r_i_2_n_0 ),\n .O(\\gen_pat_match_div4.pat1_match_fall3_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_pat_match_div4.pat1_match_fall3_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg ),\n .O(\\gen_pat_match_div4.pat1_match_fall3_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.pat1_match_fall3_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat1_match_fall3_and_r_i_1_n_0 ),\n .Q(pat1_match_fall3_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.pat1_match_rise0_and_r_i_1 \n (.I0(\\gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg ),\n .O(\\gen_pat_match_div4.pat1_match_rise0_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.pat1_match_rise0_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise0_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise0_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg ),\n .O(\\gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.pat1_match_rise0_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat1_match_rise0_and_r_i_1_n_0 ),\n .Q(pat1_match_rise0_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.pat1_match_rise1_and_r_i_1 \n (.I0(\\gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise1_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise1_r_reg ),\n .O(\\gen_pat_match_div4.pat1_match_rise1_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.pat1_match_rise1_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise1_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise1_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise1_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise1_r_reg ),\n .O(\\gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.pat1_match_rise1_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat1_match_rise1_and_r_i_1_n_0 ),\n .Q(pat1_match_rise1_and_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\gen_pat_match_div4.pat1_match_rise2_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg ),\n .I2(\\gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0 ),\n .I3(\\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg ),\n .I5(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg ),\n .O(\\gen_pat_match_div4.pat1_match_rise2_and_r_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h80)) \n \\gen_pat_match_div4.pat1_match_rise2_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r_reg ),\n .O(\\gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.pat1_match_rise2_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat1_match_rise2_and_r_i_1_n_0 ),\n .Q(pat1_match_rise2_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.pat1_match_rise3_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise3_r_reg ),\n .I4(\\gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0 ),\n .O(\\gen_pat_match_div4.pat1_match_rise3_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.pat1_match_rise3_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r_reg ),\n .O(\\gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.pat1_match_rise3_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat1_match_rise3_and_r_i_1_n_0 ),\n .Q(pat1_match_rise3_and_r),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_52 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_36 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_20 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_12 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_4 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_44 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_28 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_60 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_53 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_37 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_21 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_13 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_5 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_45 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_29 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_61 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_54 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_38 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_22 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_14 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_6 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_46 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_30 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_62 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_55 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_39 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_23 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_15 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_7 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_47 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_31 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_63 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_56 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_40 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_24 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_16 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_8 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_48 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_32 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_64 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_57 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_41 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_25 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_17 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_9 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_49 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_33 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_65 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_58 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_42 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_26 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_18 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_10 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_50 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_34 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_66 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_59 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_43 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_27 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_19 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_11 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_51 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_35 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7][0] \n (.C(CLK),\n .CE(phy_rddata_en_1),\n .D(\\gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7] ),\n .Q(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_67 ),\n .R(1'b0));\n FDRE \\gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0] ),\n .R(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0] ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0] ),\n .I2(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0] ),\n .I3(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0] ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2_n_0 ),\n .O(p_488_out__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0] ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0] ),\n .I2(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0] ),\n .I3(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0] ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2_n_0 ));\n FDRE #(\n .INIT(1'b1)) \n \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv \n (.C(CLK),\n .CE(1'b1),\n .D(p_488_out__0),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv_n_0 ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0] ),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_52 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0]_140 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0] ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0] ),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_36 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0]_132 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0] ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0] ),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_20 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0]_164 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0] ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0] ),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_12 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0]_172 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0] ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0] ),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_4 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0]_180 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0] ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0] ),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_44 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0]_148 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0] ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0] ),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_28 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0]_156 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0] ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0] ),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_60 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0]_188 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0] ),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h1)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1 \n (.I0(mpr_valid_r2),\n .I1(sr_valid_r2),\n .O(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv_n_0 ),\n .Q(\\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_0 ),\n .R(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0] ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0] ),\n .I2(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0] ),\n .I3(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0] ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2_n_0 ),\n .O(p_513_out__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0] ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0] ),\n .I2(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0] ),\n .I3(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0] ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2_n_0 ));\n FDRE #(\n .INIT(1'b1)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv \n (.C(CLK),\n .CE(1'b1),\n .D(p_513_out__0),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv_n_0 ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair112\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0] ),\n .I2(\\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0]_68 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_52 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hFB)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2 \n (.I0(mpr_valid_r1),\n .I1(mpr_rdlvl_start_reg),\n .I2(mpr_rdlvl_done_r1_reg_0),\n .O(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ));\n LUT3 #(\n .INIT(8'hFE)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3 \n (.I0(mpr_valid_r1),\n .I1(\\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),\n .I2(\\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0] ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair151\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0] ),\n .I2(\\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0]_108 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_36 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0] ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair167\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0] ),\n .I2(\\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0]_124 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_20 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0] ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair143\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0] ),\n .I2(\\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0]_100 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_12 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0] ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair135\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0] ),\n .I2(\\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0]_92 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_4 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0] ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair119\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0] ),\n .I2(\\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0]_76 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_44 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0] ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair127\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0] ),\n .I2(\\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0]_84 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_28 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0] ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair159\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0] ),\n .I2(\\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0]_116 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_60 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\gen_sr_match_div4.gen_sr_match[1].old_sr_diff_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv_n_0 ),\n .Q(p_1_in17_in),\n .R(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_1 \n (.I0(p_2_in431_in),\n .I1(p_4_in433_in),\n .I2(p_0_in430_in),\n .I3(p_3_in432_in),\n .I4(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2_n_0 ),\n .O(p_438_out__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2 \n (.I0(p_7_in436_in),\n .I1(p_5_in434_in),\n .I2(p_6_in435_in),\n .I3(p_1_in437_in),\n .O(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2_n_0 ));\n FDRE #(\n .INIT(1'b1)) \n \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv \n (.C(CLK),\n .CE(1'b1),\n .D(p_438_out__0),\n .Q(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv_n_0 ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_0_in430_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_53 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1]_141 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1_n_0 ),\n .Q(p_0_in430_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_3_in432_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_37 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1]_133 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1_n_0 ),\n .Q(p_3_in432_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_5_in434_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_21 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1]_165 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1_n_0 ),\n .Q(p_5_in434_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_7_in436_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_13 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1]_173 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1_n_0 ),\n .Q(p_7_in436_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_1_in437_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_5 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1]_181 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1_n_0 ),\n .Q(p_1_in437_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_2_in431_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_45 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1]_149 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1_n_0 ),\n .Q(p_2_in431_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_4_in433_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_29 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1]_157 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1_n_0 ),\n .Q(p_4_in433_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_6_in435_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_61 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1]_189 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1_n_0 ),\n .Q(p_6_in435_in),\n .R(1'b0));\n FDRE \\gen_sr_match_div4.gen_sr_match[1].prev_sr_diff_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv_n_0 ),\n .Q(p_0_in102_in),\n .R(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_1 \n (.I0(p_2_in456_in),\n .I1(p_4_in458_in),\n .I2(p_0_in455_in),\n .I3(p_3_in457_in),\n .I4(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2_n_0 ),\n .O(p_463_out__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2 \n (.I0(p_7_in461_in),\n .I1(p_6_in460_in),\n .I2(p_5_in459_in),\n .I3(p_1_in462_in),\n .O(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2_n_0 ));\n FDRE #(\n .INIT(1'b1)) \n \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv \n (.C(CLK),\n .CE(1'b1),\n .D(p_463_out__0),\n .Q(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv_n_0 ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair113\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_0_in455_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1]_69 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_53 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1_n_0 ),\n .Q(p_0_in455_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair152\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_3_in457_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1]_109 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_37 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1_n_0 ),\n .Q(p_3_in457_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair168\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_5_in459_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1]_125 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_21 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1_n_0 ),\n .Q(p_5_in459_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair144\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_7_in461_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1]_101 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_13 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1_n_0 ),\n .Q(p_7_in461_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair136\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_1_in462_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1]_93 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_5 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1_n_0 ),\n .Q(p_1_in462_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair120\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_2_in456_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1]_77 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_45 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1_n_0 ),\n .Q(p_2_in456_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair128\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_4_in458_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1]_85 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_29 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1_n_0 ),\n .Q(p_4_in458_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair160\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_6_in460_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1]_117 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_61 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1_n_0 ),\n .Q(p_6_in460_in),\n .R(1'b0));\n FDRE \\gen_sr_match_div4.gen_sr_match[2].old_sr_diff_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv_n_0 ),\n .Q(p_1_in14_in),\n .R(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_1 \n (.I0(p_3_in382_in),\n .I1(p_4_in383_in),\n .I2(p_2_in381_in),\n .I3(p_0_in380_in),\n .I4(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2_n_0 ),\n .O(p_388_out__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2 \n (.I0(p_7_in386_in),\n .I1(p_5_in384_in),\n .I2(p_6_in385_in),\n .I3(p_1_in387_in),\n .O(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2_n_0 ));\n FDRE #(\n .INIT(1'b1)) \n \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv \n (.C(CLK),\n .CE(1'b1),\n .D(p_388_out__0),\n .Q(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv_n_0 ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_0_in380_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_54 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2]_142 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1_n_0 ),\n .Q(p_0_in380_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_3_in382_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_38 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2]_134 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1_n_0 ),\n .Q(p_3_in382_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_5_in384_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_22 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2]_166 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1_n_0 ),\n .Q(p_5_in384_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_7_in386_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_14 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2]_174 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1_n_0 ),\n .Q(p_7_in386_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_1_in387_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_6 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2]_182 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1_n_0 ),\n .Q(p_1_in387_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_2_in381_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_46 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2]_150 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1_n_0 ),\n .Q(p_2_in381_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_4_in383_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_30 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2]_158 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1_n_0 ),\n .Q(p_4_in383_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_6_in385_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_62 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2]_190 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1_n_0 ),\n .Q(p_6_in385_in),\n .R(1'b0));\n FDRE \\gen_sr_match_div4.gen_sr_match[2].prev_sr_diff_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv_n_0 ),\n .Q(p_0_in99_in),\n .R(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_1 \n (.I0(p_2_in406_in),\n .I1(p_4_in408_in),\n .I2(p_0_in405_in),\n .I3(p_3_in407_in),\n .I4(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2_n_0 ),\n .O(p_413_out__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2 \n (.I0(p_7_in411_in),\n .I1(p_5_in409_in),\n .I2(p_6_in410_in),\n .I3(p_1_in412_in),\n .O(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2_n_0 ));\n FDRE #(\n .INIT(1'b1)) \n \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv \n (.C(CLK),\n .CE(1'b1),\n .D(p_413_out__0),\n .Q(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv_n_0 ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair114\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_0_in405_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2]_70 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_54 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1_n_0 ),\n .Q(p_0_in405_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair153\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_3_in407_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2]_110 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_38 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1_n_0 ),\n .Q(p_3_in407_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair169\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_5_in409_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2]_126 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_22 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1_n_0 ),\n .Q(p_5_in409_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair145\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_7_in411_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2]_102 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_14 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1_n_0 ),\n .Q(p_7_in411_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair137\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_1_in412_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2]_94 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_6 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1_n_0 ),\n .Q(p_1_in412_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair121\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_2_in406_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2]_78 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_46 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1_n_0 ),\n .Q(p_2_in406_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair129\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_4_in408_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2]_86 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_30 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1_n_0 ),\n .Q(p_4_in408_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair161\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_6_in410_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2]_118 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_62 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1_n_0 ),\n .Q(p_6_in410_in),\n .R(1'b0));\n FDRE \\gen_sr_match_div4.gen_sr_match[3].old_sr_diff_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv_n_0 ),\n .Q(p_1_in11_in),\n .R(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_1 \n (.I0(p_3_in332_in),\n .I1(p_4_in333_in),\n .I2(p_2_in331_in),\n .I3(p_0_in330_in),\n .I4(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2_n_0 ),\n .O(p_338_out__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2 \n (.I0(p_6_in335_in),\n .I1(p_5_in334_in),\n .I2(p_7_in336_in),\n .I3(p_1_in337_in),\n .O(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2_n_0 ));\n FDRE #(\n .INIT(1'b1)) \n \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv \n (.C(CLK),\n .CE(1'b1),\n .D(p_338_out__0),\n .Q(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv_n_0 ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_0_in330_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_55 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3]_143 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1_n_0 ),\n .Q(p_0_in330_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_3_in332_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_39 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3]_135 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1_n_0 ),\n .Q(p_3_in332_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_5_in334_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_23 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3]_167 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1_n_0 ),\n .Q(p_5_in334_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_7_in336_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_15 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3]_175 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1_n_0 ),\n .Q(p_7_in336_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_1_in337_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_7 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3]_183 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1_n_0 ),\n .Q(p_1_in337_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair175\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_2_in331_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_47 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3]_151 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1_n_0 ),\n .Q(p_2_in331_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_4_in333_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_31 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3]_159 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1_n_0 ),\n .Q(p_4_in333_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_6_in335_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_63 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3]_191 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1_n_0 ),\n .Q(p_6_in335_in),\n .R(1'b0));\n FDRE \\gen_sr_match_div4.gen_sr_match[3].prev_sr_diff_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv_n_0 ),\n .Q(p_0_in96_in),\n .R(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_1 \n (.I0(p_4_in358_in),\n .I1(p_5_in359_in),\n .I2(p_3_in357_in),\n .I3(p_0_in355_in),\n .I4(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2_n_0 ),\n .O(p_363_out__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2 \n (.I0(p_7_in361_in),\n .I1(p_6_in360_in),\n .I2(p_2_in356_in),\n .I3(p_1_in362_in),\n .O(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2_n_0 ));\n FDRE #(\n .INIT(1'b1)) \n \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv \n (.C(CLK),\n .CE(1'b1),\n .D(p_363_out__0),\n .Q(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv_n_0 ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair115\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_0_in355_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3]_71 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_55 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1_n_0 ),\n .Q(p_0_in355_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair154\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_3_in357_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3]_111 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_39 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1_n_0 ),\n .Q(p_3_in357_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair170\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_5_in359_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3]_127 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_23 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1_n_0 ),\n .Q(p_5_in359_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair146\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_7_in361_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3]_103 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_15 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1_n_0 ),\n .Q(p_7_in361_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair138\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_1_in362_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3]_95 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_7 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1_n_0 ),\n .Q(p_1_in362_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_2_in356_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3]_79 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_47 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1_n_0 ),\n .Q(p_2_in356_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair130\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_4_in358_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3]_87 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_31 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1_n_0 ),\n .Q(p_4_in358_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair162\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_6_in360_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3]_119 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_63 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1_n_0 ),\n .Q(p_6_in360_in),\n .R(1'b0));\n FDRE \\gen_sr_match_div4.gen_sr_match[4].old_sr_diff_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv_n_0 ),\n .Q(p_1_in8_in),\n .R(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_1 \n (.I0(p_4_in283_in),\n .I1(p_5_in284_in),\n .I2(p_3_in282_in),\n .I3(p_2_in281_in),\n .I4(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2_n_0 ),\n .O(p_288_out__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2 \n (.I0(p_7_in286_in),\n .I1(p_6_in285_in),\n .I2(p_0_in280_in),\n .I3(p_1_in287_in),\n .O(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2_n_0 ));\n FDRE #(\n .INIT(1'b1)) \n \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv \n (.C(CLK),\n .CE(1'b1),\n .D(p_288_out__0),\n .Q(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv_n_0 ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_0_in280_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_56 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4]_144 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1_n_0 ),\n .Q(p_0_in280_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_3_in282_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_40 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4]_136 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1_n_0 ),\n .Q(p_3_in282_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_5_in284_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_24 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4]_168 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1_n_0 ),\n .Q(p_5_in284_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_7_in286_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_16 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4]_176 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1_n_0 ),\n .Q(p_7_in286_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_1_in287_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_8 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4]_184 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1_n_0 ),\n .Q(p_1_in287_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_2_in281_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_48 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4]_152 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1_n_0 ),\n .Q(p_2_in281_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_4_in283_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_32 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4]_160 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1_n_0 ),\n .Q(p_4_in283_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_6_in285_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_64 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4]_192 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1_n_0 ),\n .Q(p_6_in285_in),\n .R(1'b0));\n FDRE \\gen_sr_match_div4.gen_sr_match[4].prev_sr_diff_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv_n_0 ),\n .Q(p_0_in93_in),\n .R(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_1 \n (.I0(p_4_in308_in),\n .I1(p_5_in309_in),\n .I2(p_3_in307_in),\n .I3(p_2_in306_in),\n .I4(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2_n_0 ),\n .O(p_313_out__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2 \n (.I0(p_7_in311_in),\n .I1(p_6_in310_in),\n .I2(p_0_in305_in),\n .I3(p_1_in312_in),\n .O(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2_n_0 ));\n FDRE #(\n .INIT(1'b1)) \n \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv \n (.C(CLK),\n .CE(1'b1),\n .D(p_313_out__0),\n .Q(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv_n_0 ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair116\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_0_in305_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4]_72 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_56 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1_n_0 ),\n .Q(p_0_in305_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair155\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_3_in307_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4]_112 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_40 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1_n_0 ),\n .Q(p_3_in307_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair171\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_5_in309_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4]_128 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_24 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1_n_0 ),\n .Q(p_5_in309_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair147\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_7_in311_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4]_104 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_16 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1_n_0 ),\n .Q(p_7_in311_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair139\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_1_in312_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4]_96 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_8 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1_n_0 ),\n .Q(p_1_in312_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair123\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_2_in306_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4]_80 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_48 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1_n_0 ),\n .Q(p_2_in306_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair131\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_4_in308_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4]_88 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_32 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1_n_0 ),\n .Q(p_4_in308_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair163\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_6_in310_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4]_120 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_64 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1_n_0 ),\n .Q(p_6_in310_in),\n .R(1'b0));\n FDRE \\gen_sr_match_div4.gen_sr_match[5].old_sr_diff_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv_n_0 ),\n .Q(p_1_in5_in),\n .R(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_1 \n (.I0(p_4_in233_in),\n .I1(p_5_in234_in),\n .I2(p_3_in232_in),\n .I3(p_2_in231_in),\n .I4(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2_n_0 ),\n .O(p_238_out__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2 \n (.I0(p_7_in236_in),\n .I1(p_6_in235_in),\n .I2(p_0_in230_in),\n .I3(p_1_in237_in),\n .O(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2_n_0 ));\n FDRE #(\n .INIT(1'b1)) \n \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv \n (.C(CLK),\n .CE(1'b1),\n .D(p_238_out__0),\n .Q(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv_n_0 ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_0_in230_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_57 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5]_145 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1_n_0 ),\n .Q(p_0_in230_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_3_in232_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_41 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5]_137 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1_n_0 ),\n .Q(p_3_in232_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_5_in234_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_25 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5]_169 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1_n_0 ),\n .Q(p_5_in234_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_7_in236_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_17 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5]_177 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1_n_0 ),\n .Q(p_7_in236_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_1_in237_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_9 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5]_185 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1_n_0 ),\n .Q(p_1_in237_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_2_in231_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_49 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5]_153 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1_n_0 ),\n .Q(p_2_in231_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_4_in233_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_33 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5]_161 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1_n_0 ),\n .Q(p_4_in233_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_6_in235_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_65 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5]_193 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1_n_0 ),\n .Q(p_6_in235_in),\n .R(1'b0));\n FDRE \\gen_sr_match_div4.gen_sr_match[5].prev_sr_diff_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv_n_0 ),\n .Q(p_0_in90_in),\n .R(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_1 \n (.I0(p_4_in258_in),\n .I1(p_5_in259_in),\n .I2(p_3_in257_in),\n .I3(p_2_in256_in),\n .I4(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2_n_0 ),\n .O(p_263_out__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2 \n (.I0(p_7_in261_in),\n .I1(p_6_in260_in),\n .I2(p_0_in255_in),\n .I3(p_1_in262_in),\n .O(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2_n_0 ));\n FDRE #(\n .INIT(1'b1)) \n \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv \n (.C(CLK),\n .CE(1'b1),\n .D(p_263_out__0),\n .Q(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv_n_0 ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair117\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_0_in255_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5]_73 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_57 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1_n_0 ),\n .Q(p_0_in255_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair156\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_3_in257_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5]_113 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_41 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1_n_0 ),\n .Q(p_3_in257_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair172\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_5_in259_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5]_129 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_25 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1_n_0 ),\n .Q(p_5_in259_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair148\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_7_in261_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5]_105 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_17 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1_n_0 ),\n .Q(p_7_in261_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair140\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_1_in262_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5]_97 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_9 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1_n_0 ),\n .Q(p_1_in262_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair124\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_2_in256_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5]_81 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_49 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1_n_0 ),\n .Q(p_2_in256_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair132\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_4_in258_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5]_89 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_33 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1_n_0 ),\n .Q(p_4_in258_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair164\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_6_in260_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5]_121 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_65 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1_n_0 ),\n .Q(p_6_in260_in),\n .R(1'b0));\n FDRE \\gen_sr_match_div4.gen_sr_match[6].old_sr_diff_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv_n_0 ),\n .Q(p_1_in2_in),\n .R(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_1 \n (.I0(p_4_in183_in),\n .I1(p_5_in184_in),\n .I2(p_3_in182_in),\n .I3(p_2_in181_in),\n .I4(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2_n_0 ),\n .O(p_188_out__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2 \n (.I0(p_7_in186_in),\n .I1(p_6_in185_in),\n .I2(p_0_in180_in),\n .I3(p_1_in187_in),\n .O(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2_n_0 ));\n FDRE #(\n .INIT(1'b1)) \n \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv \n (.C(CLK),\n .CE(1'b1),\n .D(p_188_out__0),\n .Q(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv_n_0 ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_0_in180_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_58 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6]_146 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1_n_0 ),\n .Q(p_0_in180_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_3_in182_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_42 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6]_138 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1_n_0 ),\n .Q(p_3_in182_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_5_in184_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_26 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6]_170 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1_n_0 ),\n .Q(p_5_in184_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_7_in186_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_18 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6]_178 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1_n_0 ),\n .Q(p_7_in186_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_1_in187_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_10 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6]_186 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1_n_0 ),\n .Q(p_1_in187_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_2_in181_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_50 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6]_154 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1_n_0 ),\n .Q(p_2_in181_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_4_in183_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_34 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6]_162 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1_n_0 ),\n .Q(p_4_in183_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_6_in185_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_66 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6]_194 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1_n_0 ),\n .Q(p_6_in185_in),\n .R(1'b0));\n FDRE \\gen_sr_match_div4.gen_sr_match[6].prev_sr_diff_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv_n_0 ),\n .Q(p_0_in87_in),\n .R(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_1 \n (.I0(p_4_in208_in),\n .I1(p_5_in209_in),\n .I2(p_3_in207_in),\n .I3(p_2_in206_in),\n .I4(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2_n_0 ),\n .O(p_213_out__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2 \n (.I0(p_7_in211_in),\n .I1(p_6_in210_in),\n .I2(p_0_in205_in),\n .I3(p_1_in212_in),\n .O(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2_n_0 ));\n FDRE #(\n .INIT(1'b1)) \n \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv \n (.C(CLK),\n .CE(1'b1),\n .D(p_213_out__0),\n .Q(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv_n_0 ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair122\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_0_in205_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6]_74 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_58 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1_n_0 ),\n .Q(p_0_in205_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair157\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_3_in207_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6]_114 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_42 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1_n_0 ),\n .Q(p_3_in207_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair173\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_5_in209_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6]_130 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_26 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1_n_0 ),\n .Q(p_5_in209_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair149\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_7_in211_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6]_106 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_18 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1_n_0 ),\n .Q(p_7_in211_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair141\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_1_in212_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6]_98 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_10 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1_n_0 ),\n .Q(p_1_in212_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair125\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_2_in206_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6]_82 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_50 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1_n_0 ),\n .Q(p_2_in206_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair133\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_4_in208_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6]_90 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_34 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1_n_0 ),\n .Q(p_4_in208_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair165\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_6_in210_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6]_122 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_66 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1_n_0 ),\n .Q(p_6_in210_in),\n .R(1'b0));\n FDRE \\gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7] ),\n .R(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg_n_0_[7] ),\n .I1(p_5_in136_in),\n .I2(p_3_in135_in),\n .I3(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg_n_0_[7] ),\n .I4(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2_n_0 ),\n .O(p_137_out__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2 \n (.I0(p_7_in),\n .I1(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r_reg_n_0_[7] ),\n .I2(p_0_in134_in),\n .I3(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r_reg_n_0_[7] ),\n .O(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2_n_0 ));\n FDRE #(\n .INIT(1'b1)) \n \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv \n (.C(CLK),\n .CE(1'b1),\n .D(p_137_out__0),\n .Q(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv_n_0 ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_0_in134_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_59 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7]_147 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1_n_0 ),\n .Q(p_0_in134_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_3_in135_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_43 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7]_139 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1_n_0 ),\n .Q(p_3_in135_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_5_in136_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_27 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7]_171 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1_n_0 ),\n .Q(p_5_in136_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_7_in),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_19 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7]_179 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1_n_0 ),\n .Q(p_7_in),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r_reg_n_0_[7] ),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_11 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7]_187 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r_reg_n_0_[7] ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg_n_0_[7] ),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_51 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7]_155 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg_n_0_[7] ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg_n_0_[7] ),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_35 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7]_163 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg_n_0_[7] ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r_reg_n_0_[7] ),\n .I2(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_67 ),\n .I3(\\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7]_195 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1_n_0 ),\n .Q(\\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r_reg_n_0_[7] ),\n .R(1'b0));\n FDRE \\gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv_n_0 ),\n .Q(p_0_in84_in),\n .R(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF7FFF)) \n \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_1 \n (.I0(p_4_in158_in),\n .I1(p_5_in159_in),\n .I2(p_3_in157_in),\n .I3(p_2_in156_in),\n .I4(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2_n_0 ),\n .O(p_163_out__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2 \n (.I0(p_7_in161_in),\n .I1(p_6_in160_in),\n .I2(p_0_in155_in),\n .I3(p_1_in162_in),\n .O(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2_n_0 ));\n FDRE #(\n .INIT(1'b1)) \n \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv \n (.C(CLK),\n .CE(1'b1),\n .D(p_163_out__0),\n .Q(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv_n_0 ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair118\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_0_in155_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7]_75 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_59 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1_n_0 ),\n .Q(p_0_in155_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair158\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_3_in157_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7]_115 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_43 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1_n_0 ),\n .Q(p_3_in157_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair174\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_5_in159_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7]_131 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_27 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1_n_0 ),\n .Q(p_5_in159_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair150\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_7_in161_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7]_107 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_19 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1_n_0 ),\n .Q(p_7_in161_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair142\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_1_in162_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7]_99 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_11 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1_n_0 ),\n .Q(p_1_in162_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair126\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_2_in156_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7]_83 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_51 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1_n_0 ),\n .Q(p_2_in156_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair134\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_4_in158_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7]_91 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_35 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1_n_0 ),\n .Q(p_4_in158_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair166\" *) \n LUT5 #(\n .INIT(32'hF44F4444)) \n \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_2_n_0 ),\n .I1(p_6_in160_in),\n .I2(\\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7]_123 ),\n .I3(\\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_67 ),\n .I4(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_3_n_0 ),\n .O(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1_n_0 ));\n FDRE \\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1_n_0 ),\n .Q(p_6_in160_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair245\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_track_left_edge[0].pb_cnt_eye_size_r[0][0]_i_1 \n (.I0(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]),\n .O(p_0_in__2[0]));\n (* SOFT_HLUTNM = \"soft_lutpair245\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gen_track_left_edge[0].pb_cnt_eye_size_r[0][1]_i_1 \n (.I0(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]),\n .I1(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]),\n .O(p_0_in__2[1]));\n (* SOFT_HLUTNM = \"soft_lutpair216\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\gen_track_left_edge[0].pb_cnt_eye_size_r[0][2]_i_1 \n (.I0(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [2]),\n .I1(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]),\n .I2(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]),\n .O(p_0_in__2[2]));\n (* SOFT_HLUTNM = \"soft_lutpair216\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\gen_track_left_edge[0].pb_cnt_eye_size_r[0][3]_i_1 \n (.I0(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [3]),\n .I1(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]),\n .I2(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]),\n .I3(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [2]),\n .O(p_0_in__2[3]));\n LUT4 #(\n .INIT(16'hAAAB)) \n \\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1 \n (.I0(pb_detect_edge_setup),\n .I1(\\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0 ),\n .I2(pb_detect_edge_done_r[0]),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .O(\\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8AAAAAAAAAAAAAAA)) \n \\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_2 \n (.I0(\\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0 ),\n .I1(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [4]),\n .I2(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [3]),\n .I3(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]),\n .I4(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]),\n .I5(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [2]),\n .O(pb_cnt_eye_size_r));\n (* SOFT_HLUTNM = \"soft_lutpair188\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_3 \n (.I0(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [4]),\n .I1(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [2]),\n .I2(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]),\n .I3(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]),\n .I4(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [3]),\n .O(p_0_in__2[4]));\n (* SOFT_HLUTNM = \"soft_lutpair178\" *) \n LUT5 #(\n .INIT(32'h00000F11)) \n \\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4 \n (.I0(\\gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0] ),\n .I1(\\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_0 ),\n .I2(\\gen_track_left_edge[0].pb_found_edge_r_reg[0]_0 ),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I4(\\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 ),\n .O(\\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair233\" *) \n LUT3 #(\n .INIT(8'h02)) \n \\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5 \n (.I0(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .I2(pb_detect_edge_done_r[0]),\n .O(\\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0 ));\n FDRE \\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][0] \n (.C(CLK),\n .CE(pb_cnt_eye_size_r),\n .D(p_0_in__2[0]),\n .Q(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]),\n .R(\\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][1] \n (.C(CLK),\n .CE(pb_cnt_eye_size_r),\n .D(p_0_in__2[1]),\n .Q(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]),\n .R(\\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][2] \n (.C(CLK),\n .CE(pb_cnt_eye_size_r),\n .D(p_0_in__2[2]),\n .Q(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [2]),\n .R(\\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][3] \n (.C(CLK),\n .CE(pb_cnt_eye_size_r),\n .D(p_0_in__2[3]),\n .Q(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [3]),\n .R(\\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][4] \n (.C(CLK),\n .CE(pb_cnt_eye_size_r),\n .D(p_0_in__2[4]),\n .Q(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [4]),\n .R(\\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[0].pb_detect_edge_done_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg[0]_0 ),\n .Q(pb_detect_edge_done_r[0]),\n .R(pb_detect_edge_setup));\n FDRE \\gen_track_left_edge[0].pb_found_edge_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[0].pb_found_edge_r_reg[0]_2 ),\n .Q(\\gen_track_left_edge[0].pb_found_edge_r_reg[0]_0 ),\n .R(pb_detect_edge_setup));\n (* SOFT_HLUTNM = \"soft_lutpair178\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_2 \n (.I0(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I1(\\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_0 ),\n .I2(\\gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0] ),\n .I3(\\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 ),\n .O(\\gen_track_left_edge[0].pb_found_edge_r_reg[0]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair188\" *) \n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3 \n (.I0(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [2]),\n .I1(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [0]),\n .I2(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [1]),\n .I3(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [3]),\n .I4(\\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]__0 [4]),\n .O(\\gen_track_left_edge[0].pb_found_stable_eye_r_reg[0]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair226\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_4 \n (.I0(\\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 ),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I2(\\gen_track_left_edge[0].pb_found_edge_r_reg[0]_0 ),\n .O(pb_found_stable_eye_r76_out));\n FDRE \\gen_track_left_edge[0].pb_found_stable_eye_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[0].pb_detect_edge_done_r_reg[0]_0 ),\n .Q(\\gen_track_left_edge[0].pb_found_stable_eye_r_reg ),\n .R(pb_detect_edge_setup));\n LUT6 #(\n .INIT(64'h00000000AAAAAA0E)) \n \\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1 \n (.I0(\\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 ),\n .I1(\\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_0 ),\n .I2(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .I4(pb_detect_edge_done_r[0]),\n .I5(pb_detect_edge_setup),\n .O(\\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFEFBFFFFFEF7F)) \n \\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_2 \n (.I0(out[3]),\n .I1(out[2]),\n .I2(out[0]),\n .I3(out[4]),\n .I4(cal1_state_r),\n .I5(out[1]),\n .O(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ));\n FDRE \\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1_n_0 ),\n .Q(\\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]_1 ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair244\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_track_left_edge[1].pb_cnt_eye_size_r[1][0]_i_1 \n (.I0(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]),\n .O(p_0_in__3[0]));\n (* SOFT_HLUTNM = \"soft_lutpair244\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gen_track_left_edge[1].pb_cnt_eye_size_r[1][1]_i_1 \n (.I0(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]),\n .I1(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]),\n .O(p_0_in__3[1]));\n (* SOFT_HLUTNM = \"soft_lutpair213\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\gen_track_left_edge[1].pb_cnt_eye_size_r[1][2]_i_1 \n (.I0(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [2]),\n .I1(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]),\n .I2(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]),\n .O(p_0_in__3[2]));\n (* SOFT_HLUTNM = \"soft_lutpair213\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\gen_track_left_edge[1].pb_cnt_eye_size_r[1][3]_i_1 \n (.I0(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [3]),\n .I1(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]),\n .I2(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]),\n .I3(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [2]),\n .O(p_0_in__3[3]));\n LUT4 #(\n .INIT(16'hAAAB)) \n \\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1 \n (.I0(pb_detect_edge_setup),\n .I1(\\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0 ),\n .I2(pb_detect_edge_done_r[1]),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .O(\\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8AAAAAAAAAAAAAAA)) \n \\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2 \n (.I0(\\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0 ),\n .I1(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [4]),\n .I2(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [3]),\n .I3(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]),\n .I4(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]),\n .I5(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [2]),\n .O(\\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair177\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_3 \n (.I0(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [4]),\n .I1(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [2]),\n .I2(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]),\n .I3(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]),\n .I4(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [3]),\n .O(p_0_in__3[4]));\n (* SOFT_HLUTNM = \"soft_lutpair179\" *) \n LUT5 #(\n .INIT(32'h00000F11)) \n \\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4 \n (.I0(p_1_in17_in),\n .I1(p_0_in102_in),\n .I2(found_edge_r_reg_0),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I4(p_0_in16_in),\n .O(\\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair233\" *) \n LUT3 #(\n .INIT(8'h02)) \n \\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5 \n (.I0(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .I2(pb_detect_edge_done_r[1]),\n .O(\\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0 ));\n FDRE \\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][0] \n (.C(CLK),\n .CE(\\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ),\n .D(p_0_in__3[0]),\n .Q(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]),\n .R(\\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][1] \n (.C(CLK),\n .CE(\\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ),\n .D(p_0_in__3[1]),\n .Q(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]),\n .R(\\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][2] \n (.C(CLK),\n .CE(\\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ),\n .D(p_0_in__3[2]),\n .Q(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [2]),\n .R(\\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][3] \n (.C(CLK),\n .CE(\\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ),\n .D(p_0_in__3[3]),\n .Q(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [3]),\n .R(\\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][4] \n (.C(CLK),\n .CE(\\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ),\n .D(p_0_in__3[4]),\n .Q(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [4]),\n .R(\\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[1].pb_detect_edge_done_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(samp_cnt_done_r_reg_6),\n .Q(pb_detect_edge_done_r[1]),\n .R(pb_detect_edge_setup));\n FDRE \\gen_track_left_edge[1].pb_found_edge_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[1].pb_found_edge_r_reg[1]_1 ),\n .Q(found_edge_r_reg_0),\n .R(pb_detect_edge_setup));\n (* SOFT_HLUTNM = \"soft_lutpair179\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_2 \n (.I0(p_0_in102_in),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I2(p_1_in17_in),\n .I3(p_0_in16_in),\n .O(\\gen_track_left_edge[1].pb_found_edge_r_reg[1]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair177\" *) \n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_3 \n (.I0(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [2]),\n .I1(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [0]),\n .I2(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [1]),\n .I3(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [3]),\n .I4(\\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]__0 [4]),\n .O(\\gen_track_left_edge[1].pb_found_stable_eye_r_reg[1]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair234\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_4 \n (.I0(p_0_in16_in),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I2(found_edge_r_reg_0),\n .O(pb_found_stable_eye_r72_out));\n FDRE \\gen_track_left_edge[1].pb_found_stable_eye_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[1].pb_detect_edge_done_r_reg[1]_0 ),\n .Q(\\gen_track_left_edge[1].pb_found_stable_eye_r_reg ),\n .R(pb_detect_edge_setup));\n LUT6 #(\n .INIT(64'h00000000AAAAAA0E)) \n \\gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1 \n (.I0(p_0_in16_in),\n .I1(p_0_in102_in),\n .I2(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .I4(pb_detect_edge_done_r[1]),\n .I5(pb_detect_edge_setup),\n .O(\\gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[1].pb_last_tap_jitter_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1_n_0 ),\n .Q(p_0_in16_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair243\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_track_left_edge[2].pb_cnt_eye_size_r[2][0]_i_1 \n (.I0(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]),\n .O(p_0_in__4[0]));\n (* SOFT_HLUTNM = \"soft_lutpair243\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gen_track_left_edge[2].pb_cnt_eye_size_r[2][1]_i_1 \n (.I0(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]),\n .I1(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]),\n .O(p_0_in__4[1]));\n (* SOFT_HLUTNM = \"soft_lutpair210\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\gen_track_left_edge[2].pb_cnt_eye_size_r[2][2]_i_1 \n (.I0(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [2]),\n .I1(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]),\n .I2(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]),\n .O(p_0_in__4[2]));\n (* SOFT_HLUTNM = \"soft_lutpair210\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\gen_track_left_edge[2].pb_cnt_eye_size_r[2][3]_i_1 \n (.I0(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [3]),\n .I1(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]),\n .I2(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]),\n .I3(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [2]),\n .O(p_0_in__4[3]));\n LUT4 #(\n .INIT(16'hAAAB)) \n \\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1 \n (.I0(pb_detect_edge_setup),\n .I1(\\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0 ),\n .I2(pb_detect_edge_done_r[2]),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .O(\\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8AAAAAAAAAAAAAAA)) \n \\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2 \n (.I0(\\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0 ),\n .I1(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [4]),\n .I2(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [3]),\n .I3(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]),\n .I4(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]),\n .I5(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [2]),\n .O(\\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair191\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_3 \n (.I0(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [4]),\n .I1(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [2]),\n .I2(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]),\n .I3(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]),\n .I4(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [3]),\n .O(p_0_in__4[4]));\n (* SOFT_HLUTNM = \"soft_lutpair180\" *) \n LUT5 #(\n .INIT(32'h00000F11)) \n \\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4 \n (.I0(p_1_in14_in),\n .I1(p_0_in99_in),\n .I2(found_edge_r_reg_1),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I4(p_0_in13_in),\n .O(\\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair232\" *) \n LUT3 #(\n .INIT(8'h02)) \n \\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5 \n (.I0(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .I2(pb_detect_edge_done_r[2]),\n .O(\\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0 ));\n FDRE \\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][0] \n (.C(CLK),\n .CE(\\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ),\n .D(p_0_in__4[0]),\n .Q(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]),\n .R(\\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][1] \n (.C(CLK),\n .CE(\\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ),\n .D(p_0_in__4[1]),\n .Q(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]),\n .R(\\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][2] \n (.C(CLK),\n .CE(\\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ),\n .D(p_0_in__4[2]),\n .Q(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [2]),\n .R(\\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][3] \n (.C(CLK),\n .CE(\\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ),\n .D(p_0_in__4[3]),\n .Q(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [3]),\n .R(\\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][4] \n (.C(CLK),\n .CE(\\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ),\n .D(p_0_in__4[4]),\n .Q(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [4]),\n .R(\\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[2].pb_detect_edge_done_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(samp_cnt_done_r_reg_5),\n .Q(pb_detect_edge_done_r[2]),\n .R(pb_detect_edge_setup));\n FDRE \\gen_track_left_edge[2].pb_found_edge_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[2].pb_found_edge_r_reg[2]_1 ),\n .Q(found_edge_r_reg_1),\n .R(pb_detect_edge_setup));\n (* SOFT_HLUTNM = \"soft_lutpair180\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_2 \n (.I0(p_0_in99_in),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I2(p_1_in14_in),\n .I3(p_0_in13_in),\n .O(\\gen_track_left_edge[2].pb_found_edge_r_reg[2]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair191\" *) \n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_3 \n (.I0(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [2]),\n .I1(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [0]),\n .I2(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [1]),\n .I3(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [3]),\n .I4(\\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]__0 [4]),\n .O(\\gen_track_left_edge[2].pb_found_stable_eye_r_reg[2]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair234\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_4 \n (.I0(p_0_in13_in),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I2(found_edge_r_reg_1),\n .O(pb_found_stable_eye_r68_out));\n FDRE \\gen_track_left_edge[2].pb_found_stable_eye_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[2].pb_detect_edge_done_r_reg[2]_0 ),\n .Q(\\gen_track_left_edge[2].pb_found_stable_eye_r_reg ),\n .R(pb_detect_edge_setup));\n LUT6 #(\n .INIT(64'h00000000AAAAAA0E)) \n \\gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1 \n (.I0(p_0_in13_in),\n .I1(p_0_in99_in),\n .I2(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .I4(pb_detect_edge_done_r[2]),\n .I5(pb_detect_edge_setup),\n .O(\\gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[2].pb_last_tap_jitter_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1_n_0 ),\n .Q(p_0_in13_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair242\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_track_left_edge[3].pb_cnt_eye_size_r[3][0]_i_1 \n (.I0(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]),\n .O(p_0_in__5[0]));\n (* SOFT_HLUTNM = \"soft_lutpair242\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gen_track_left_edge[3].pb_cnt_eye_size_r[3][1]_i_1 \n (.I0(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]),\n .I1(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]),\n .O(p_0_in__5[1]));\n (* SOFT_HLUTNM = \"soft_lutpair212\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\gen_track_left_edge[3].pb_cnt_eye_size_r[3][2]_i_1 \n (.I0(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [2]),\n .I1(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]),\n .I2(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]),\n .O(p_0_in__5[2]));\n (* SOFT_HLUTNM = \"soft_lutpair212\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\gen_track_left_edge[3].pb_cnt_eye_size_r[3][3]_i_1 \n (.I0(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [3]),\n .I1(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]),\n .I2(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]),\n .I3(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [2]),\n .O(p_0_in__5[3]));\n LUT4 #(\n .INIT(16'hAAAB)) \n \\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1 \n (.I0(pb_detect_edge_setup),\n .I1(\\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0 ),\n .I2(pb_detect_edge_done_r[3]),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .O(\\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8AAAAAAAAAAAAAAA)) \n \\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2 \n (.I0(\\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0 ),\n .I1(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [4]),\n .I2(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [3]),\n .I3(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]),\n .I4(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]),\n .I5(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [2]),\n .O(\\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair196\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_3 \n (.I0(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [4]),\n .I1(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [2]),\n .I2(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]),\n .I3(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]),\n .I4(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [3]),\n .O(p_0_in__5[4]));\n (* SOFT_HLUTNM = \"soft_lutpair181\" *) \n LUT5 #(\n .INIT(32'h00000F11)) \n \\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4 \n (.I0(p_1_in11_in),\n .I1(p_0_in96_in),\n .I2(found_edge_r_reg_2),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I4(p_0_in10_in),\n .O(\\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair229\" *) \n LUT3 #(\n .INIT(8'h02)) \n \\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5 \n (.I0(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .I2(pb_detect_edge_done_r[3]),\n .O(\\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0 ));\n FDRE \\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][0] \n (.C(CLK),\n .CE(\\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ),\n .D(p_0_in__5[0]),\n .Q(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]),\n .R(\\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][1] \n (.C(CLK),\n .CE(\\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ),\n .D(p_0_in__5[1]),\n .Q(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]),\n .R(\\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][2] \n (.C(CLK),\n .CE(\\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ),\n .D(p_0_in__5[2]),\n .Q(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [2]),\n .R(\\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][3] \n (.C(CLK),\n .CE(\\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ),\n .D(p_0_in__5[3]),\n .Q(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [3]),\n .R(\\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][4] \n (.C(CLK),\n .CE(\\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ),\n .D(p_0_in__5[4]),\n .Q(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [4]),\n .R(\\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[3].pb_detect_edge_done_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(samp_cnt_done_r_reg_4),\n .Q(pb_detect_edge_done_r[3]),\n .R(pb_detect_edge_setup));\n FDRE \\gen_track_left_edge[3].pb_found_edge_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[3].pb_found_edge_r_reg[3]_1 ),\n .Q(found_edge_r_reg_2),\n .R(pb_detect_edge_setup));\n (* SOFT_HLUTNM = \"soft_lutpair181\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_2 \n (.I0(p_0_in96_in),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I2(p_1_in11_in),\n .I3(p_0_in10_in),\n .O(\\gen_track_left_edge[3].pb_found_edge_r_reg[3]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair196\" *) \n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_3 \n (.I0(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [2]),\n .I1(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [0]),\n .I2(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [1]),\n .I3(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [3]),\n .I4(\\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]__0 [4]),\n .O(\\gen_track_left_edge[3].pb_found_stable_eye_r_reg[3]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair232\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_4 \n (.I0(p_0_in10_in),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I2(found_edge_r_reg_2),\n .O(pb_found_stable_eye_r64_out));\n FDRE \\gen_track_left_edge[3].pb_found_stable_eye_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[3].pb_detect_edge_done_r_reg[3]_0 ),\n .Q(\\gen_track_left_edge[3].pb_found_stable_eye_r_reg ),\n .R(pb_detect_edge_setup));\n LUT6 #(\n .INIT(64'h00000000AAAAAA0E)) \n \\gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1 \n (.I0(p_0_in10_in),\n .I1(p_0_in96_in),\n .I2(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .I4(pb_detect_edge_done_r[3]),\n .I5(pb_detect_edge_setup),\n .O(\\gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[3].pb_last_tap_jitter_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1_n_0 ),\n .Q(p_0_in10_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair241\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_track_left_edge[4].pb_cnt_eye_size_r[4][0]_i_1 \n (.I0(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]),\n .O(p_0_in__6[0]));\n (* SOFT_HLUTNM = \"soft_lutpair241\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gen_track_left_edge[4].pb_cnt_eye_size_r[4][1]_i_1 \n (.I0(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]),\n .I1(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]),\n .O(p_0_in__6[1]));\n (* SOFT_HLUTNM = \"soft_lutpair217\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\gen_track_left_edge[4].pb_cnt_eye_size_r[4][2]_i_1 \n (.I0(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [2]),\n .I1(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]),\n .I2(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]),\n .O(p_0_in__6[2]));\n (* SOFT_HLUTNM = \"soft_lutpair217\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\gen_track_left_edge[4].pb_cnt_eye_size_r[4][3]_i_1 \n (.I0(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [3]),\n .I1(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]),\n .I2(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]),\n .I3(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [2]),\n .O(p_0_in__6[3]));\n LUT4 #(\n .INIT(16'hAAAB)) \n \\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1 \n (.I0(pb_detect_edge_setup),\n .I1(\\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0 ),\n .I2(pb_detect_edge_done_r[4]),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .O(\\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8AAAAAAAAAAAAAAA)) \n \\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2 \n (.I0(\\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0 ),\n .I1(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [4]),\n .I2(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [3]),\n .I3(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]),\n .I4(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]),\n .I5(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [2]),\n .O(\\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair197\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_3 \n (.I0(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [4]),\n .I1(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [2]),\n .I2(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]),\n .I3(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]),\n .I4(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [3]),\n .O(p_0_in__6[4]));\n (* SOFT_HLUTNM = \"soft_lutpair182\" *) \n LUT5 #(\n .INIT(32'h00000F11)) \n \\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4 \n (.I0(p_1_in8_in),\n .I1(p_0_in93_in),\n .I2(\\gen_track_left_edge[4].pb_found_edge_r_reg[4]_0 ),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I4(p_0_in7_in),\n .O(\\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair226\" *) \n LUT3 #(\n .INIT(8'h02)) \n \\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5 \n (.I0(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .I2(pb_detect_edge_done_r[4]),\n .O(\\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0 ));\n FDRE \\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][0] \n (.C(CLK),\n .CE(\\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ),\n .D(p_0_in__6[0]),\n .Q(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]),\n .R(\\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][1] \n (.C(CLK),\n .CE(\\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ),\n .D(p_0_in__6[1]),\n .Q(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]),\n .R(\\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][2] \n (.C(CLK),\n .CE(\\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ),\n .D(p_0_in__6[2]),\n .Q(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [2]),\n .R(\\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][3] \n (.C(CLK),\n .CE(\\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ),\n .D(p_0_in__6[3]),\n .Q(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [3]),\n .R(\\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][4] \n (.C(CLK),\n .CE(\\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ),\n .D(p_0_in__6[4]),\n .Q(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [4]),\n .R(\\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[4].pb_detect_edge_done_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(samp_cnt_done_r_reg_3),\n .Q(pb_detect_edge_done_r[4]),\n .R(pb_detect_edge_setup));\n FDRE \\gen_track_left_edge[4].pb_found_edge_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[4].pb_found_edge_r_reg[4]_2 ),\n .Q(\\gen_track_left_edge[4].pb_found_edge_r_reg[4]_0 ),\n .R(pb_detect_edge_setup));\n (* SOFT_HLUTNM = \"soft_lutpair182\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_2 \n (.I0(p_0_in93_in),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I2(p_1_in8_in),\n .I3(p_0_in7_in),\n .O(\\gen_track_left_edge[4].pb_found_edge_r_reg[4]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair197\" *) \n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_3 \n (.I0(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [2]),\n .I1(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [0]),\n .I2(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [1]),\n .I3(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [3]),\n .I4(\\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]__0 [4]),\n .O(\\gen_track_left_edge[4].pb_found_stable_eye_r_reg[4]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair229\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_4 \n (.I0(p_0_in7_in),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I2(\\gen_track_left_edge[4].pb_found_edge_r_reg[4]_0 ),\n .O(pb_found_stable_eye_r60_out));\n FDRE \\gen_track_left_edge[4].pb_found_stable_eye_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[4].pb_detect_edge_done_r_reg[4]_0 ),\n .Q(\\gen_track_left_edge[4].pb_found_stable_eye_r_reg ),\n .R(pb_detect_edge_setup));\n LUT6 #(\n .INIT(64'h00000000AAAAAA0E)) \n \\gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1 \n (.I0(p_0_in7_in),\n .I1(p_0_in93_in),\n .I2(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .I4(pb_detect_edge_done_r[4]),\n .I5(pb_detect_edge_setup),\n .O(\\gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[4].pb_last_tap_jitter_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1_n_0 ),\n .Q(p_0_in7_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair240\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_track_left_edge[5].pb_cnt_eye_size_r[5][0]_i_1 \n (.I0(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]),\n .O(p_0_in__7[0]));\n (* SOFT_HLUTNM = \"soft_lutpair240\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gen_track_left_edge[5].pb_cnt_eye_size_r[5][1]_i_1 \n (.I0(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]),\n .I1(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]),\n .O(p_0_in__7[1]));\n (* SOFT_HLUTNM = \"soft_lutpair215\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\gen_track_left_edge[5].pb_cnt_eye_size_r[5][2]_i_1 \n (.I0(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [2]),\n .I1(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]),\n .I2(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]),\n .O(p_0_in__7[2]));\n (* SOFT_HLUTNM = \"soft_lutpair215\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\gen_track_left_edge[5].pb_cnt_eye_size_r[5][3]_i_1 \n (.I0(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [3]),\n .I1(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]),\n .I2(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]),\n .I3(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [2]),\n .O(p_0_in__7[3]));\n LUT4 #(\n .INIT(16'hAAAB)) \n \\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1 \n (.I0(pb_detect_edge_setup),\n .I1(\\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0 ),\n .I2(pb_detect_edge_done_r[5]),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .O(\\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8AAAAAAAAAAAAAAA)) \n \\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2 \n (.I0(\\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0 ),\n .I1(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [4]),\n .I2(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [3]),\n .I3(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]),\n .I4(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]),\n .I5(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [2]),\n .O(\\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair192\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_3 \n (.I0(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [4]),\n .I1(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [2]),\n .I2(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]),\n .I3(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]),\n .I4(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [3]),\n .O(p_0_in__7[4]));\n (* SOFT_HLUTNM = \"soft_lutpair183\" *) \n LUT5 #(\n .INIT(32'h00000F11)) \n \\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4 \n (.I0(p_1_in5_in),\n .I1(p_0_in90_in),\n .I2(found_edge_r_reg_3),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I4(p_0_in4_in),\n .O(\\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair222\" *) \n LUT3 #(\n .INIT(8'h02)) \n \\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5 \n (.I0(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .I2(pb_detect_edge_done_r[5]),\n .O(\\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0 ));\n FDRE \\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][0] \n (.C(CLK),\n .CE(\\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ),\n .D(p_0_in__7[0]),\n .Q(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]),\n .R(\\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][1] \n (.C(CLK),\n .CE(\\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ),\n .D(p_0_in__7[1]),\n .Q(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]),\n .R(\\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][2] \n (.C(CLK),\n .CE(\\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ),\n .D(p_0_in__7[2]),\n .Q(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [2]),\n .R(\\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][3] \n (.C(CLK),\n .CE(\\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ),\n .D(p_0_in__7[3]),\n .Q(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [3]),\n .R(\\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][4] \n (.C(CLK),\n .CE(\\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ),\n .D(p_0_in__7[4]),\n .Q(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [4]),\n .R(\\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[5].pb_detect_edge_done_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(samp_cnt_done_r_reg_2),\n .Q(pb_detect_edge_done_r[5]),\n .R(pb_detect_edge_setup));\n FDRE \\gen_track_left_edge[5].pb_found_edge_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[5].pb_found_edge_r_reg[5]_1 ),\n .Q(found_edge_r_reg_3),\n .R(pb_detect_edge_setup));\n (* SOFT_HLUTNM = \"soft_lutpair183\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_2 \n (.I0(p_0_in90_in),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I2(p_1_in5_in),\n .I3(p_0_in4_in),\n .O(\\gen_track_left_edge[5].pb_found_edge_r_reg[5]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair192\" *) \n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_3 \n (.I0(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [2]),\n .I1(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [0]),\n .I2(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [1]),\n .I3(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [3]),\n .I4(\\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]__0 [4]),\n .O(\\gen_track_left_edge[5].pb_found_stable_eye_r_reg[5]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair219\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_4 \n (.I0(p_0_in4_in),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I2(found_edge_r_reg_3),\n .O(pb_found_stable_eye_r56_out));\n FDRE \\gen_track_left_edge[5].pb_found_stable_eye_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[5].pb_detect_edge_done_r_reg[5]_0 ),\n .Q(\\gen_track_left_edge[5].pb_found_stable_eye_r_reg ),\n .R(pb_detect_edge_setup));\n LUT6 #(\n .INIT(64'h00000000AAAAAA0E)) \n \\gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1 \n (.I0(p_0_in4_in),\n .I1(p_0_in90_in),\n .I2(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .I4(pb_detect_edge_done_r[5]),\n .I5(pb_detect_edge_setup),\n .O(\\gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[5].pb_last_tap_jitter_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1_n_0 ),\n .Q(p_0_in4_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair247\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_track_left_edge[6].pb_cnt_eye_size_r[6][0]_i_1 \n (.I0(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]),\n .O(p_0_in__8[0]));\n (* SOFT_HLUTNM = \"soft_lutpair247\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gen_track_left_edge[6].pb_cnt_eye_size_r[6][1]_i_1 \n (.I0(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]),\n .I1(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]),\n .O(p_0_in__8[1]));\n (* SOFT_HLUTNM = \"soft_lutpair200\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\gen_track_left_edge[6].pb_cnt_eye_size_r[6][2]_i_1 \n (.I0(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [2]),\n .I1(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]),\n .I2(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]),\n .O(p_0_in__8[2]));\n (* SOFT_HLUTNM = \"soft_lutpair200\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\gen_track_left_edge[6].pb_cnt_eye_size_r[6][3]_i_1 \n (.I0(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [3]),\n .I1(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]),\n .I2(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]),\n .I3(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [2]),\n .O(p_0_in__8[3]));\n LUT4 #(\n .INIT(16'hAAAB)) \n \\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1 \n (.I0(pb_detect_edge_setup),\n .I1(\\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0 ),\n .I2(pb_detect_edge_done_r[6]),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .O(\\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8AAAAAAAAAAAAAAA)) \n \\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2 \n (.I0(\\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0 ),\n .I1(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [4]),\n .I2(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [3]),\n .I3(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]),\n .I4(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]),\n .I5(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [2]),\n .O(\\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair176\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_3 \n (.I0(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [4]),\n .I1(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [2]),\n .I2(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]),\n .I3(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]),\n .I4(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [3]),\n .O(p_0_in__8[4]));\n (* SOFT_HLUTNM = \"soft_lutpair184\" *) \n LUT5 #(\n .INIT(32'h00000F11)) \n \\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4 \n (.I0(p_1_in2_in),\n .I1(p_0_in87_in),\n .I2(\\gen_track_left_edge[6].pb_found_edge_r_reg[6]_0 ),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I4(p_0_in1_in),\n .O(\\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair219\" *) \n LUT3 #(\n .INIT(8'h02)) \n \\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5 \n (.I0(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .I2(pb_detect_edge_done_r[6]),\n .O(\\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0 ));\n FDRE \\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][0] \n (.C(CLK),\n .CE(\\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ),\n .D(p_0_in__8[0]),\n .Q(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]),\n .R(\\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][1] \n (.C(CLK),\n .CE(\\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ),\n .D(p_0_in__8[1]),\n .Q(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]),\n .R(\\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][2] \n (.C(CLK),\n .CE(\\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ),\n .D(p_0_in__8[2]),\n .Q(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [2]),\n .R(\\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][3] \n (.C(CLK),\n .CE(\\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ),\n .D(p_0_in__8[3]),\n .Q(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [3]),\n .R(\\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][4] \n (.C(CLK),\n .CE(\\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ),\n .D(p_0_in__8[4]),\n .Q(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [4]),\n .R(\\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[6].pb_detect_edge_done_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(samp_cnt_done_r_reg_1),\n .Q(pb_detect_edge_done_r[6]),\n .R(pb_detect_edge_setup));\n FDRE \\gen_track_left_edge[6].pb_found_edge_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[6].pb_found_edge_r_reg[6]_2 ),\n .Q(\\gen_track_left_edge[6].pb_found_edge_r_reg[6]_0 ),\n .R(pb_detect_edge_setup));\n (* SOFT_HLUTNM = \"soft_lutpair184\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_2 \n (.I0(p_0_in87_in),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I2(p_1_in2_in),\n .I3(p_0_in1_in),\n .O(\\gen_track_left_edge[6].pb_found_edge_r_reg[6]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair176\" *) \n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_3 \n (.I0(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [2]),\n .I1(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [0]),\n .I2(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [1]),\n .I3(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [3]),\n .I4(\\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]__0 [4]),\n .O(\\gen_track_left_edge[6].pb_found_stable_eye_r_reg[6]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair222\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_4 \n (.I0(p_0_in1_in),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I2(\\gen_track_left_edge[6].pb_found_edge_r_reg[6]_0 ),\n .O(pb_found_stable_eye_r52_out));\n FDRE \\gen_track_left_edge[6].pb_found_stable_eye_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[6].pb_detect_edge_done_r_reg[6]_0 ),\n .Q(\\gen_track_left_edge[6].pb_found_stable_eye_r_reg ),\n .R(pb_detect_edge_setup));\n LUT6 #(\n .INIT(64'h00000000AAAAAA0E)) \n \\gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1 \n (.I0(p_0_in1_in),\n .I1(p_0_in87_in),\n .I2(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .I4(pb_detect_edge_done_r[6]),\n .I5(pb_detect_edge_setup),\n .O(\\gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[6].pb_last_tap_jitter_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1_n_0 ),\n .Q(p_0_in1_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair246\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\gen_track_left_edge[7].pb_cnt_eye_size_r[7][0]_i_1 \n (.I0(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]),\n .O(p_0_in__9[0]));\n (* SOFT_HLUTNM = \"soft_lutpair246\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\gen_track_left_edge[7].pb_cnt_eye_size_r[7][1]_i_1 \n (.I0(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]),\n .I1(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]),\n .O(p_0_in__9[1]));\n (* SOFT_HLUTNM = \"soft_lutpair204\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\gen_track_left_edge[7].pb_cnt_eye_size_r[7][2]_i_1 \n (.I0(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [2]),\n .I1(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]),\n .I2(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]),\n .O(p_0_in__9[2]));\n (* SOFT_HLUTNM = \"soft_lutpair204\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\gen_track_left_edge[7].pb_cnt_eye_size_r[7][3]_i_1 \n (.I0(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [3]),\n .I1(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]),\n .I2(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]),\n .I3(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [2]),\n .O(p_0_in__9[3]));\n LUT4 #(\n .INIT(16'hAAAB)) \n \\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1 \n (.I0(pb_detect_edge_setup),\n .I1(\\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0 ),\n .I2(pb_detect_edge_done_r[7]),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .O(\\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8AAAAAAAAAAAAAAA)) \n \\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2 \n (.I0(\\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0 ),\n .I1(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [4]),\n .I2(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [3]),\n .I3(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]),\n .I4(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]),\n .I5(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [2]),\n .O(\\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair195\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_3 \n (.I0(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [4]),\n .I1(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [2]),\n .I2(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]),\n .I3(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]),\n .I4(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [3]),\n .O(p_0_in__9[4]));\n (* SOFT_HLUTNM = \"soft_lutpair185\" *) \n LUT5 #(\n .INIT(32'h00000F11)) \n \\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4 \n (.I0(\\gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7] ),\n .I1(p_0_in84_in),\n .I2(\\gen_track_left_edge[7].pb_found_edge_r_reg[7]_0 ),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I4(p_0_in),\n .O(\\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair218\" *) \n LUT3 #(\n .INIT(8'h02)) \n \\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5 \n (.I0(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .I2(pb_detect_edge_done_r[7]),\n .O(\\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0 ));\n FDRE \\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][0] \n (.C(CLK),\n .CE(\\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ),\n .D(p_0_in__9[0]),\n .Q(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]),\n .R(\\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][1] \n (.C(CLK),\n .CE(\\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ),\n .D(p_0_in__9[1]),\n .Q(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]),\n .R(\\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][2] \n (.C(CLK),\n .CE(\\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ),\n .D(p_0_in__9[2]),\n .Q(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [2]),\n .R(\\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][3] \n (.C(CLK),\n .CE(\\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ),\n .D(p_0_in__9[3]),\n .Q(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [3]),\n .R(\\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][4] \n (.C(CLK),\n .CE(\\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ),\n .D(p_0_in__9[4]),\n .Q(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [4]),\n .R(\\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000400040008)) \n \\gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_1 \n (.I0(out[3]),\n .I1(out[2]),\n .I2(cal1_state_r),\n .I3(out[4]),\n .I4(out[0]),\n .I5(out[1]),\n .O(pb_detect_edge_setup));\n FDRE \\gen_track_left_edge[7].pb_detect_edge_done_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(samp_cnt_done_r_reg_0),\n .Q(pb_detect_edge_done_r[7]),\n .R(pb_detect_edge_setup));\n FDRE \\gen_track_left_edge[7].pb_found_edge_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[7].pb_found_edge_r_reg[7]_2 ),\n .Q(\\gen_track_left_edge[7].pb_found_edge_r_reg[7]_0 ),\n .R(pb_detect_edge_setup));\n (* SOFT_HLUTNM = \"soft_lutpair185\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_2 \n (.I0(p_0_in84_in),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I2(\\gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7] ),\n .I3(p_0_in),\n .O(\\gen_track_left_edge[7].pb_found_edge_r_reg[7]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair195\" *) \n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_3 \n (.I0(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [2]),\n .I1(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [0]),\n .I2(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [1]),\n .I3(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [3]),\n .I4(\\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]__0 [4]),\n .O(\\gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair218\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_4 \n (.I0(p_0_in),\n .I1(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I2(\\gen_track_left_edge[7].pb_found_edge_r_reg[7]_0 ),\n .O(\\gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]_0 ));\n FDRE \\gen_track_left_edge[7].pb_found_stable_eye_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[7].pb_detect_edge_done_r_reg[7]_0 ),\n .Q(\\gen_track_left_edge[7].pb_found_stable_eye_r_reg ),\n .R(pb_detect_edge_setup));\n LUT6 #(\n .INIT(64'h00000000AAAAAA0E)) \n \\gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1 \n (.I0(p_0_in),\n .I1(p_0_in84_in),\n .I2(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I3(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_1 ),\n .I4(pb_detect_edge_done_r[7]),\n .I5(pb_detect_edge_setup),\n .O(\\gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1_n_0 ));\n FDRE \\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1_n_0 ),\n .Q(p_0_in),\n .R(1'b0));\n LUT4 #(\n .INIT(16'h0008)) \n idel_adj_inc_i_2\n (.I0(out[4]),\n .I1(out[0]),\n .I2(cal1_state_r),\n .I3(out[3]),\n .O(idel_adj_inc_reg_1));\n (* SOFT_HLUTNM = \"soft_lutpair223\" *) \n LUT3 #(\n .INIT(8'hA8)) \n idel_adj_inc_i_3\n (.I0(detect_edge_done_r),\n .I1(\\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ),\n .I2(\\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ),\n .O(idel_adj_inc_reg_2));\n FDRE idel_adj_inc_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_cal1_state_r_reg[2]_0 ),\n .Q(idel_adj_inc_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n LUT4 #(\n .INIT(16'h4373)) \n \\idel_dec_cnt[0]_i_1 \n (.I0(idel_dec_cnt__0[0]),\n .I1(out[1]),\n .I2(out[2]),\n .I3(\\idel_dec_cnt[0]_i_2_n_0 ),\n .O(idel_dec_cnt));\n LUT6 #(\n .INIT(64'h505F3030505F3F3F)) \n \\idel_dec_cnt[0]_i_2 \n (.I0(\\idelay_tap_cnt_r_reg_n_0_[0][3][0] ),\n .I1(\\idelay_tap_cnt_r_reg_n_0_[0][1][0] ),\n .I2(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .I3(\\idelay_tap_cnt_r_reg_n_0_[0][2][0] ),\n .I4(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I5(\\idelay_tap_cnt_r_reg_n_0_[0][0][0] ),\n .O(\\idel_dec_cnt[0]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h0000E22E)) \n \\idel_dec_cnt[1]_i_1 \n (.I0(idelay_tap_cnt_r[1]),\n .I1(out[4]),\n .I2(idel_dec_cnt__0[0]),\n .I3(idel_dec_cnt__0[1]),\n .I4(out[0]),\n .O(\\idel_dec_cnt[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00000000EEE2222E)) \n \\idel_dec_cnt[2]_i_1 \n (.I0(idelay_tap_cnt_r[2]),\n .I1(out[4]),\n .I2(idel_dec_cnt__0[1]),\n .I3(idel_dec_cnt__0[0]),\n .I4(idel_dec_cnt__0[2]),\n .I5(out[0]),\n .O(\\idel_dec_cnt[2]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h00002EE2)) \n \\idel_dec_cnt[3]_i_1 \n (.I0(idelay_tap_cnt_r[3]),\n .I1(out[4]),\n .I2(\\idel_dec_cnt[3]_i_2_n_0 ),\n .I3(idel_dec_cnt__0[3]),\n .I4(out[0]),\n .O(\\idel_dec_cnt[3]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h01)) \n \\idel_dec_cnt[3]_i_2 \n (.I0(idel_dec_cnt__0[0]),\n .I1(idel_dec_cnt__0[1]),\n .I2(idel_dec_cnt__0[2]),\n .O(\\idel_dec_cnt[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h1000001000404000)) \n \\idel_dec_cnt[4]_i_1 \n (.I0(\\idel_dec_cnt_reg[0]_0 ),\n .I1(out[0]),\n .I2(\\idel_dec_cnt[4]_i_4_n_0 ),\n .I3(out[1]),\n .I4(out[4]),\n .I5(out[2]),\n .O(\\idel_dec_cnt[4]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h00002EE2)) \n \\idel_dec_cnt[4]_i_2 \n (.I0(idelay_tap_cnt_r[4]),\n .I1(out[4]),\n .I2(\\idel_dec_cnt[4]_i_5_n_0 ),\n .I3(idel_dec_cnt__0[4]),\n .I4(out[0]),\n .O(\\idel_dec_cnt[4]_i_2_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\idel_dec_cnt[4]_i_3 \n (.I0(out[3]),\n .I1(cal1_state_r),\n .O(\\idel_dec_cnt_reg[0]_0 ));\n LUT6 #(\n .INIT(64'hB888FFFFB8880000)) \n \\idel_dec_cnt[4]_i_4 \n (.I0(cal1_state_r2),\n .I1(out[4]),\n .I2(mpr_rd_rise0_prev_r_reg_0),\n .I3(idel_mpr_pat_detect_r),\n .I4(out[1]),\n .I5(\\idel_dec_cnt[4]_i_7_n_0 ),\n .O(\\idel_dec_cnt[4]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair93\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\idel_dec_cnt[4]_i_5 \n (.I0(idel_dec_cnt__0[2]),\n .I1(idel_dec_cnt__0[1]),\n .I2(idel_dec_cnt__0[0]),\n .I3(idel_dec_cnt__0[3]),\n .O(\\idel_dec_cnt[4]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair93\" *) \n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n \\idel_dec_cnt[4]_i_6 \n (.I0(idel_dec_cnt__0[4]),\n .I1(idel_dec_cnt__0[3]),\n .I2(idel_dec_cnt__0[0]),\n .I3(idel_dec_cnt__0[1]),\n .I4(idel_dec_cnt__0[2]),\n .O(cal1_state_r2));\n LUT6 #(\n .INIT(64'hA800A800A8FFA800)) \n \\idel_dec_cnt[4]_i_7 \n (.I0(detect_edge_done_r),\n .I1(\\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ),\n .I2(\\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ),\n .I3(out[4]),\n .I4(stable_idel_cnt22_in),\n .I5(\\idel_dec_cnt[4]_i_8_n_0 ),\n .O(\\idel_dec_cnt[4]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFB)) \n \\idel_dec_cnt[4]_i_8 \n (.I0(\\cnt_idel_dec_cpt_r_reg_n_0_[5] ),\n .I1(mpr_dec_cpt_r_reg_0),\n .I2(\\cnt_idel_dec_cpt_r_reg_n_0_[2] ),\n .I3(\\cnt_idel_dec_cpt_r_reg_n_0_[3] ),\n .I4(\\cnt_idel_dec_cpt_r_reg_n_0_[4] ),\n .I5(\\idel_dec_cnt[4]_i_9_n_0 ),\n .O(\\idel_dec_cnt[4]_i_8_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair206\" *) \n LUT2 #(\n .INIT(4'hB)) \n \\idel_dec_cnt[4]_i_9 \n (.I0(\\cnt_idel_dec_cpt_r_reg_n_0_[1] ),\n .I1(\\cnt_idel_dec_cpt_r_reg_n_0_[0] ),\n .O(\\idel_dec_cnt[4]_i_9_n_0 ));\n FDRE \\idel_dec_cnt_reg[0] \n (.C(CLK),\n .CE(\\idel_dec_cnt[4]_i_1_n_0 ),\n .D(idel_dec_cnt),\n .Q(idel_dec_cnt__0[0]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE \\idel_dec_cnt_reg[1] \n (.C(CLK),\n .CE(\\idel_dec_cnt[4]_i_1_n_0 ),\n .D(\\idel_dec_cnt[1]_i_1_n_0 ),\n .Q(idel_dec_cnt__0[1]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE \\idel_dec_cnt_reg[2] \n (.C(CLK),\n .CE(\\idel_dec_cnt[4]_i_1_n_0 ),\n .D(\\idel_dec_cnt[2]_i_1_n_0 ),\n .Q(idel_dec_cnt__0[2]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE \\idel_dec_cnt_reg[3] \n (.C(CLK),\n .CE(\\idel_dec_cnt[4]_i_1_n_0 ),\n .D(\\idel_dec_cnt[3]_i_1_n_0 ),\n .Q(idel_dec_cnt__0[3]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE \\idel_dec_cnt_reg[4] \n (.C(CLK),\n .CE(\\idel_dec_cnt[4]_i_1_n_0 ),\n .D(\\idel_dec_cnt[4]_i_2_n_0 ),\n .Q(idel_dec_cnt__0[4]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE idel_pat_detect_valid_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_cal1_state_r_reg[4]_0 ),\n .Q(mpr_rd_rise0_prev_r_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n (* SOFT_HLUTNM = \"soft_lutpair107\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\idelay_tap_cnt_r[0][0][0]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__23),\n .I1(idelay_ce_int),\n .I2(idelay_tap_cnt_slice_r[0]),\n .O(\\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair107\" *) \n LUT5 #(\n .INIT(32'h04404004)) \n \\idelay_tap_cnt_r[0][0][1]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__23),\n .I1(idelay_ce_int),\n .I2(idelay_tap_cnt_slice_r[0]),\n .I3(idelay_tap_cnt_slice_r[1]),\n .I4(idelay_inc_int),\n .O(\\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0444400044400004)) \n \\idelay_tap_cnt_r[0][0][2]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__23),\n .I1(idelay_ce_int),\n .I2(idelay_inc_int),\n .I3(idelay_tap_cnt_slice_r[0]),\n .I4(idelay_tap_cnt_slice_r[2]),\n .I5(idelay_tap_cnt_slice_r[1]),\n .O(\\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h28A0A0A0A0A0A082)) \n \\idelay_tap_cnt_r[0][0][3]_i_1 \n (.I0(\\idelay_tap_cnt_r[0][0][3]_i_2_n_0 ),\n .I1(idelay_tap_cnt_slice_r[2]),\n .I2(idelay_tap_cnt_slice_r[3]),\n .I3(idelay_tap_cnt_slice_r[0]),\n .I4(idelay_inc_int),\n .I5(idelay_tap_cnt_slice_r[1]),\n .O(\\idelay_tap_cnt_r[0][0][3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair201\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\idelay_tap_cnt_r[0][0][3]_i_2 \n (.I0(idelay_ce_int),\n .I1(rstdiv0_sync_r1_reg_rep__23),\n .O(\\idelay_tap_cnt_r[0][0][3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF111111F1)) \n \\idelay_tap_cnt_r[0][0][4]_i_1 \n (.I0(\\po_stg2_wrcal_cnt_reg[0] ),\n .I1(\\po_stg2_wrcal_cnt_reg[1] ),\n .I2(\\idelay_tap_cnt_r[0][0][4]_i_4_n_0 ),\n .I3(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .I4(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I5(rstdiv0_sync_r1_reg_rep__23),\n .O(\\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair228\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\idelay_tap_cnt_r[0][0][4]_i_2 \n (.I0(rstdiv0_sync_r1_reg_rep__23),\n .I1(idelay_ce_int),\n .I2(\\idelay_tap_cnt_r[0][0][4]_i_5_n_0 ),\n .O(\\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair221\" *) \n LUT3 #(\n .INIT(8'h10)) \n \\idelay_tap_cnt_r[0][0][4]_i_4 \n (.I0(\\rnk_cnt_r_reg_n_0_[0] ),\n .I1(\\rnk_cnt_r_reg_n_0_[1] ),\n .I2(idelay_ce_int),\n .O(\\idelay_tap_cnt_r[0][0][4]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h9555555555555556)) \n \\idelay_tap_cnt_r[0][0][4]_i_5 \n (.I0(idelay_tap_cnt_slice_r[4]),\n .I1(idelay_tap_cnt_slice_r[0]),\n .I2(idelay_inc_int),\n .I3(idelay_tap_cnt_slice_r[1]),\n .I4(idelay_tap_cnt_slice_r[3]),\n .I5(idelay_tap_cnt_slice_r[2]),\n .O(\\idelay_tap_cnt_r[0][0][4]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF1111F111)) \n \\idelay_tap_cnt_r[0][1][4]_i_1 \n (.I0(cal1_dq_idel_ce_reg_0),\n .I1(\\po_stg2_wrcal_cnt_reg[1] ),\n .I2(\\idelay_tap_cnt_r[0][0][4]_i_4_n_0 ),\n .I3(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .I4(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I5(rstdiv0_sync_r1_reg_rep__23),\n .O(\\idelay_tap_cnt_r[0][1][4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF4F444444)) \n \\idelay_tap_cnt_r[0][2][4]_i_1 \n (.I0(\\po_stg2_wrcal_cnt_reg[0] ),\n .I1(\\po_stg2_wrcal_cnt_reg[1] ),\n .I2(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .I3(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I4(\\idelay_tap_cnt_r[0][0][4]_i_4_n_0 ),\n .I5(rstdiv0_sync_r1_reg_rep__23),\n .O(\\idelay_tap_cnt_r[0][2][4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFF4444444)) \n \\idelay_tap_cnt_r[0][3][4]_i_1 \n (.I0(cal1_dq_idel_ce_reg_0),\n .I1(\\po_stg2_wrcal_cnt_reg[1] ),\n .I2(idelay_ce_int),\n .I3(\\idelay_tap_cnt_r[0][3][4]_i_2_n_0 ),\n .I4(cal1_cnt_cpt_r1),\n .I5(rstdiv0_sync_r1_reg_rep__23),\n .O(\\idelay_tap_cnt_r[0][3][4]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair221\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\idelay_tap_cnt_r[0][3][4]_i_2 \n (.I0(\\rnk_cnt_r_reg_n_0_[1] ),\n .I1(\\rnk_cnt_r_reg_n_0_[0] ),\n .O(\\idelay_tap_cnt_r[0][3][4]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair231\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\idelay_tap_cnt_r[0][3][4]_i_3 \n (.I0(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I1(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .O(cal1_cnt_cpt_r1));\n FDRE \\idelay_tap_cnt_r_reg[0][0][0] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][0][0] ),\n .R(1'b0));\n FDRE \\idelay_tap_cnt_r_reg[0][0][1] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][0][1] ),\n .R(1'b0));\n FDRE \\idelay_tap_cnt_r_reg[0][0][2] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][0][2] ),\n .R(1'b0));\n FDRE \\idelay_tap_cnt_r_reg[0][0][3] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][3]_i_1_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][0][3] ),\n .R(1'b0));\n FDRE \\idelay_tap_cnt_r_reg[0][0][4] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][0][4] ),\n .R(1'b0));\n FDRE \\idelay_tap_cnt_r_reg[0][1][0] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][1][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][1][0] ),\n .R(1'b0));\n FDRE \\idelay_tap_cnt_r_reg[0][1][1] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][1][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][1][1] ),\n .R(1'b0));\n FDRE \\idelay_tap_cnt_r_reg[0][1][2] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][1][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][1][2] ),\n .R(1'b0));\n FDRE \\idelay_tap_cnt_r_reg[0][1][3] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][1][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][3]_i_1_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][1][3] ),\n .R(1'b0));\n FDRE \\idelay_tap_cnt_r_reg[0][1][4] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][1][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][1][4] ),\n .R(1'b0));\n FDRE \\idelay_tap_cnt_r_reg[0][2][0] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][2][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][2][0] ),\n .R(1'b0));\n FDRE \\idelay_tap_cnt_r_reg[0][2][1] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][2][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][2][1] ),\n .R(1'b0));\n FDRE \\idelay_tap_cnt_r_reg[0][2][2] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][2][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][2][2] ),\n .R(1'b0));\n FDRE \\idelay_tap_cnt_r_reg[0][2][3] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][2][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][3]_i_1_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][2][3] ),\n .R(1'b0));\n FDRE \\idelay_tap_cnt_r_reg[0][2][4] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][2][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][2][4] ),\n .R(1'b0));\n FDRE \\idelay_tap_cnt_r_reg[0][3][0] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][3][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][3][0] ),\n .R(1'b0));\n FDRE \\idelay_tap_cnt_r_reg[0][3][1] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][3][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][3][1] ),\n .R(1'b0));\n FDRE \\idelay_tap_cnt_r_reg[0][3][2] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][3][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][3][2] ),\n .R(1'b0));\n FDRE \\idelay_tap_cnt_r_reg[0][3][3] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][3][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][3]_i_1_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][3][3] ),\n .R(1'b0));\n FDRE \\idelay_tap_cnt_r_reg[0][3][4] \n (.C(CLK),\n .CE(\\idelay_tap_cnt_r[0][3][4]_i_1_n_0 ),\n .D(\\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ),\n .Q(\\idelay_tap_cnt_r_reg_n_0_[0][3][4] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFE2CCE233E200E2)) \n \\idelay_tap_cnt_slice_r[0]_i_1 \n (.I0(\\idelay_tap_cnt_r_reg_n_0_[0][0][0] ),\n .I1(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I2(\\idelay_tap_cnt_r_reg_n_0_[0][2][0] ),\n .I3(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .I4(\\idelay_tap_cnt_r_reg_n_0_[0][1][0] ),\n .I5(\\idelay_tap_cnt_r_reg_n_0_[0][3][0] ),\n .O(idelay_tap_cnt_r[0]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\idelay_tap_cnt_slice_r[1]_i_1 \n (.I0(\\idelay_tap_cnt_r_reg_n_0_[0][3][1] ),\n .I1(\\idelay_tap_cnt_r_reg_n_0_[0][1][1] ),\n .I2(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .I3(\\idelay_tap_cnt_r_reg_n_0_[0][2][1] ),\n .I4(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I5(\\idelay_tap_cnt_r_reg_n_0_[0][0][1] ),\n .O(idelay_tap_cnt_r[1]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\idelay_tap_cnt_slice_r[2]_i_1 \n (.I0(\\idelay_tap_cnt_r_reg_n_0_[0][3][2] ),\n .I1(\\idelay_tap_cnt_r_reg_n_0_[0][1][2] ),\n .I2(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .I3(\\idelay_tap_cnt_r_reg_n_0_[0][2][2] ),\n .I4(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I5(\\idelay_tap_cnt_r_reg_n_0_[0][0][2] ),\n .O(idelay_tap_cnt_r[2]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\idelay_tap_cnt_slice_r[3]_i_1 \n (.I0(\\idelay_tap_cnt_r_reg_n_0_[0][3][3] ),\n .I1(\\idelay_tap_cnt_r_reg_n_0_[0][1][3] ),\n .I2(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .I3(\\idelay_tap_cnt_r_reg_n_0_[0][2][3] ),\n .I4(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I5(\\idelay_tap_cnt_r_reg_n_0_[0][0][3] ),\n .O(idelay_tap_cnt_r[3]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\idelay_tap_cnt_slice_r[4]_i_1 \n (.I0(\\idelay_tap_cnt_r_reg_n_0_[0][3][4] ),\n .I1(\\idelay_tap_cnt_r_reg_n_0_[0][1][4] ),\n .I2(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .I3(\\idelay_tap_cnt_r_reg_n_0_[0][2][4] ),\n .I4(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I5(\\idelay_tap_cnt_r_reg_n_0_[0][0][4] ),\n .O(idelay_tap_cnt_r[4]));\n FDRE \\idelay_tap_cnt_slice_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(idelay_tap_cnt_r[0]),\n .Q(idelay_tap_cnt_slice_r[0]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE \\idelay_tap_cnt_slice_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(idelay_tap_cnt_r[1]),\n .Q(idelay_tap_cnt_slice_r[1]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE \\idelay_tap_cnt_slice_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(idelay_tap_cnt_r[2]),\n .Q(idelay_tap_cnt_slice_r[2]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE \\idelay_tap_cnt_slice_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(idelay_tap_cnt_r[3]),\n .Q(idelay_tap_cnt_slice_r[3]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE \\idelay_tap_cnt_slice_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(idelay_tap_cnt_r[4]),\n .Q(idelay_tap_cnt_slice_r[4]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n LUT3 #(\n .INIT(8'h02)) \n idelay_tap_limit_r_i_1\n (.I0(idelay_tap_limit_r_i_2_n_0),\n .I1(new_cnt_cpt_r_reg_n_0),\n .I2(rstdiv0_sync_r1_reg_rep__23),\n .O(idelay_tap_limit_r_i_1_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFF40000000)) \n idelay_tap_limit_r_i_2\n (.I0(\\idel_dec_cnt[0]_i_2_n_0 ),\n .I1(idelay_tap_cnt_r[3]),\n .I2(idelay_tap_cnt_r[4]),\n .I3(idelay_tap_cnt_r[2]),\n .I4(idelay_tap_cnt_r[1]),\n .I5(idelay_tap_limit_r_reg_n_0),\n .O(idelay_tap_limit_r_i_2_n_0));\n FDRE idelay_tap_limit_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(idelay_tap_limit_r_i_1_n_0),\n .Q(idelay_tap_limit_r_reg_n_0),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair207\" *) \n LUT3 #(\n .INIT(8'h54)) \n \\init_state_r[0]_i_37 \n (.I0(oclkdelay_calib_done_r_reg),\n .I1(mpr_last_byte_done),\n .I2(mpr_rdlvl_done_r1_reg_0),\n .O(\\init_state_r_reg[0]_0 ));\n LUT6 #(\n .INIT(64'h00000000AAFE0000)) \n \\init_state_r[0]_i_38 \n (.I0(\\init_state_r[0]_i_48_n_0 ),\n .I1(wrlvl_byte_redo),\n .I2(wrlvl_final_mux),\n .I3(\\init_state_r[0]_i_49_n_0 ),\n .I4(mem_init_done_r),\n .I5(prbs_rdlvl_done_reg_rep_0),\n .O(\\init_state_r_reg[0]_2 ));\n LUT5 #(\n .INIT(32'h00010000)) \n \\init_state_r[0]_i_44 \n (.I0(\\init_state_r_reg[1]_0 [1]),\n .I1(mpr_rdlvl_done_r1_reg_0),\n .I2(mpr_rnk_done),\n .I3(rdlvl_prech_req),\n .I4(\\init_state_r_reg[1]_0 [0]),\n .O(\\init_state_r_reg[0] ));\n LUT6 #(\n .INIT(64'h55FF55FF51FF51F1)) \n \\init_state_r[0]_i_47 \n (.I0(\\init_state_r[0]_i_53_n_0 ),\n .I1(oclkdelay_calib_done_r_reg),\n .I2(\\init_state_r[0]_i_54_n_0 ),\n .I3(prbs_rdlvl_done_reg_rep),\n .I4(rdlvl_stg1_done_r1_reg),\n .I5(\\init_state_r_reg[5] ),\n .O(\\init_state_r_reg[0]_3 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF001F0000)) \n \\init_state_r[0]_i_48 \n (.I0(mpr_rdlvl_done_r1_reg_0),\n .I1(mpr_last_byte_done),\n .I2(oclkdelay_calib_done_r_reg),\n .I3(\\init_state_r[0]_i_53_n_0 ),\n .I4(wrlvl_final_mux_reg),\n .I5(prbs_rdlvl_done_reg_rep_1),\n .O(\\init_state_r[0]_i_48_n_0 ));\n LUT6 #(\n .INIT(64'hFF00FF000000FF54)) \n \\init_state_r[0]_i_49 \n (.I0(prbs_last_byte_done_r),\n .I1(mpr_last_byte_done),\n .I2(mpr_rdlvl_done_r1_reg_0),\n .I3(prbs_rdlvl_done_reg_rep),\n .I4(wrcal_done_reg),\n .I5(rdlvl_stg1_done_r1_reg),\n .O(\\init_state_r[0]_i_49_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair225\" *) \n LUT3 #(\n .INIT(8'h01)) \n \\init_state_r[0]_i_52 \n (.I0(rdlvl_stg1_done_r1_reg),\n .I1(rdlvl_last_byte_done),\n .I2(\\one_rank.stg1_wr_done_reg ),\n .O(\\init_state_r_reg[0]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair214\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\init_state_r[0]_i_53 \n (.I0(rdlvl_stg1_done_r1_reg),\n .I1(oclkdelay_center_calib_done_r_reg),\n .I2(wrlvl_done_r1),\n .O(\\init_state_r[0]_i_53_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair94\" *) \n LUT3 #(\n .INIT(8'h4F)) \n \\init_state_r[0]_i_54 \n (.I0(rdlvl_stg1_done_r1_reg),\n .I1(wrcal_done_reg),\n .I2(dqs_found_done_r_reg),\n .O(\\init_state_r[0]_i_54_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair214\" *) \n LUT4 #(\n .INIT(16'h0080)) \n \\init_state_r[0]_i_57 \n (.I0(rdlvl_stg1_done_r1_reg),\n .I1(prbs_rdlvl_done_reg_rep),\n .I2(oclkdelay_center_calib_done_r_reg),\n .I3(wrlvl_done_r1),\n .O(\\init_state_r_reg[0]_4 ));\n LUT6 #(\n .INIT(64'h00FFFE0000000000)) \n \\init_state_r[1]_i_38 \n (.I0(mpr_rdlvl_done_r1_reg_0),\n .I1(mpr_rnk_done),\n .I2(rdlvl_prech_req),\n .I3(\\init_state_r_reg[1]_0 [0]),\n .I4(\\init_state_r_reg[1]_0 [1]),\n .I5(\\init_state_r_reg[3]_0 ),\n .O(\\init_state_r_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair94\" *) \n LUT5 #(\n .INIT(32'h7FFFFFFF)) \n \\init_state_r[2]_i_13 \n (.I0(rdlvl_stg1_done_r1_reg),\n .I1(prbs_rdlvl_done_reg_rep),\n .I2(wrlvl_done_r1),\n .I3(dqs_found_done_r_reg),\n .I4(wrcal_done_reg),\n .O(\\init_state_r_reg[2]_2 ));\n LUT6 #(\n .INIT(64'hD0FFD0FFD0FFD0D0)) \n \\init_state_r[2]_i_15 \n (.I0(wrlvl_done_r1_reg),\n .I1(\\init_state_r_reg[2]_0 ),\n .I2(\\init_state_r_reg[2]_1 ),\n .I3(wrlvl_done_r1_reg_0),\n .I4(cnt_init_af_done_r),\n .I5(dqs_found_done_r_reg_0),\n .O(\\init_state_r_reg[2] ));\n LUT6 #(\n .INIT(64'hFFFFFFFF74FFFFFF)) \n \\init_state_r[2]_i_28 \n (.I0(prbs_rdlvl_done_reg_rep),\n .I1(rdlvl_stg1_done_r1_reg),\n .I2(wrcal_done_reg),\n .I3(dqs_found_done_r_reg),\n .I4(oclkdelay_calib_done_r_reg),\n .I5(\\init_state_r_reg[5] ),\n .O(\\init_state_r_reg[2]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair211\" *) \n LUT4 #(\n .INIT(16'hAAFE)) \n \\init_state_r[3]_i_8 \n (.I0(wrlvl_byte_redo_reg),\n .I1(mpr_rdlvl_done_r1_reg_0),\n .I2(mpr_last_byte_done),\n .I3(oclkdelay_calib_done_r_reg),\n .O(\\init_state_r_reg[2]_1 ));\n LUT6 #(\n .INIT(64'h4040004000000040)) \n \\init_state_r[3]_i_9 \n (.I0(\\num_refresh_reg[1] ),\n .I1(\\init_state_r_reg[5] ),\n .I2(dqs_found_done_r_reg),\n .I3(wrcal_done_reg),\n .I4(rdlvl_stg1_done_r1_reg),\n .I5(prbs_rdlvl_done_reg_rep),\n .O(\\init_state_r_reg[3] ));\n LUT6 #(\n .INIT(64'hB010B010B0100000)) \n \\init_state_r[4]_i_25 \n (.I0(rdlvl_stg1_done_r1_reg),\n .I1(wrcal_done_reg),\n .I2(dqs_found_done_r_reg),\n .I3(prbs_rdlvl_done_reg_rep),\n .I4(mpr_last_byte_done),\n .I5(mpr_rdlvl_done_r1_reg_0),\n .O(\\init_state_r_reg[4] ));\n (* SOFT_HLUTNM = \"soft_lutpair211\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\init_state_r[5]_i_30 \n (.I0(mpr_rdlvl_done_r1_reg_0),\n .I1(mpr_last_byte_done),\n .O(\\init_state_r_reg[5] ));\n LUT5 #(\n .INIT(32'h00000002)) \n \\mpr_4to1.idel_mpr_pat_detect_r_i_1 \n (.I0(\\mpr_4to1.idel_mpr_pat_detect_r_i_2_n_0 ),\n .I1(\\mpr_4to1.idel_mpr_pat_detect_r_i_3_n_0 ),\n .I2(inhibit_edge_detect_r),\n .I3(p_1_in26_in),\n .I4(inhibit_edge_detect_r0),\n .O(\\mpr_4to1.idel_mpr_pat_detect_r_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF00100000)) \n \\mpr_4to1.idel_mpr_pat_detect_r_i_2 \n (.I0(\\mpr_4to1.inhibit_edge_detect_r_i_2_n_0 ),\n .I1(\\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ),\n .I2(\\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ),\n .I3(\\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ),\n .I4(\\mpr_4to1.stable_idel_cnt[2]_i_4_n_0 ),\n .I5(idel_mpr_pat_detect_r),\n .O(\\mpr_4to1.idel_mpr_pat_detect_r_i_2_n_0 ));\n LUT4 #(\n .INIT(16'h0008)) \n \\mpr_4to1.idel_mpr_pat_detect_r_i_3 \n (.I0(\\mpr_4to1.inhibit_edge_detect_r_i_3_n_0 ),\n .I1(mpr_rd_rise0_prev_r_reg_0),\n .I2(\\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ),\n .I3(\\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ),\n .O(\\mpr_4to1.idel_mpr_pat_detect_r_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000100)) \n \\mpr_4to1.idel_mpr_pat_detect_r_i_4 \n (.I0(out[3]),\n .I1(cal1_state_r),\n .I2(out[4]),\n .I3(out[0]),\n .I4(out[2]),\n .I5(out[1]),\n .O(p_1_in26_in));\n FDRE \\mpr_4to1.idel_mpr_pat_detect_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\mpr_4to1.idel_mpr_pat_detect_r_i_1_n_0 ),\n .Q(idel_mpr_pat_detect_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hFFFFFB00)) \n \\mpr_4to1.inhibit_edge_detect_r_i_1 \n (.I0(\\mpr_4to1.inhibit_edge_detect_r_i_2_n_0 ),\n .I1(\\mpr_4to1.inhibit_edge_detect_r_i_3_n_0 ),\n .I2(\\mpr_4to1.inhibit_edge_detect_r_i_4_n_0 ),\n .I3(inhibit_edge_detect_r),\n .I4(inhibit_edge_detect_r0),\n .O(\\mpr_4to1.inhibit_edge_detect_r_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFFEFF)) \n \\mpr_4to1.inhibit_edge_detect_r_i_2 \n (.I0(mpr_rd_rise2_prev_r),\n .I1(mpr_rd_rise1_prev_r),\n .I2(mpr_rd_rise3_prev_r),\n .I3(mpr_rd_fall1_prev_r),\n .I4(\\mpr_4to1.inhibit_edge_detect_r_i_6_n_0 ),\n .O(\\mpr_4to1.inhibit_edge_detect_r_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000020000)) \n \\mpr_4to1.inhibit_edge_detect_r_i_3 \n (.I0(out[1]),\n .I1(out[3]),\n .I2(cal1_state_r),\n .I3(out[4]),\n .I4(out[0]),\n .I5(out[2]),\n .O(\\mpr_4to1.inhibit_edge_detect_r_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair110\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\mpr_4to1.inhibit_edge_detect_r_i_4 \n (.I0(idelay_tap_cnt_r[1]),\n .I1(idelay_tap_cnt_r[2]),\n .I2(idelay_tap_cnt_r[3]),\n .I3(idelay_tap_cnt_r[4]),\n .O(\\mpr_4to1.inhibit_edge_detect_r_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAAABAAAAAA)) \n \\mpr_4to1.inhibit_edge_detect_r_i_5 \n (.I0(rstdiv0_sync_r1_reg_rep__23),\n .I1(\\mpr_4to1.inhibit_edge_detect_r_i_7_n_0 ),\n .I2(mpr_rd_fall2_prev_r),\n .I3(mpr_rd_rise2_prev_r),\n .I4(mpr_rd_rise1_prev_r),\n .I5(mpr_rd_fall0_prev_r),\n .O(inhibit_edge_detect_r0));\n LUT4 #(\n .INIT(16'hFF7F)) \n \\mpr_4to1.inhibit_edge_detect_r_i_6 \n (.I0(mpr_rd_fall2_prev_r),\n .I1(mpr_rd_fall0_prev_r),\n .I2(mpr_rd_fall3_prev_r),\n .I3(mpr_rd_rise0_prev_r),\n .O(\\mpr_4to1.inhibit_edge_detect_r_i_6_n_0 ));\n LUT4 #(\n .INIT(16'hFFDF)) \n \\mpr_4to1.inhibit_edge_detect_r_i_7 \n (.I0(mpr_rd_rise0_prev_r),\n .I1(mpr_rd_fall1_prev_r),\n .I2(mpr_rd_rise3_prev_r),\n .I3(mpr_rd_fall3_prev_r),\n .O(\\mpr_4to1.inhibit_edge_detect_r_i_7_n_0 ));\n FDRE \\mpr_4to1.inhibit_edge_detect_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\mpr_4to1.inhibit_edge_detect_r_i_1_n_0 ),\n .Q(inhibit_edge_detect_r),\n .R(1'b0));\n LUT3 #(\n .INIT(8'h06)) \n \\mpr_4to1.stable_idel_cnt[0]_i_1 \n (.I0(\\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ),\n .I1(stable_idel_cnt),\n .I2(stable_idel_cnt0),\n .O(\\mpr_4to1.stable_idel_cnt[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair109\" *) \n LUT4 #(\n .INIT(16'h006A)) \n \\mpr_4to1.stable_idel_cnt[1]_i_1 \n (.I0(\\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ),\n .I1(stable_idel_cnt),\n .I2(\\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ),\n .I3(stable_idel_cnt0),\n .O(\\mpr_4to1.stable_idel_cnt[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair109\" *) \n LUT5 #(\n .INIT(32'h00006AAA)) \n \\mpr_4to1.stable_idel_cnt[2]_i_1 \n (.I0(\\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ),\n .I1(stable_idel_cnt),\n .I2(\\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ),\n .I3(\\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ),\n .I4(stable_idel_cnt0),\n .O(\\mpr_4to1.stable_idel_cnt[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000080)) \n \\mpr_4to1.stable_idel_cnt[2]_i_2 \n (.I0(stable_idel_cnt22_in),\n .I1(\\mpr_4to1.inhibit_edge_detect_r_i_3_n_0 ),\n .I2(mpr_rd_rise0_prev_r_reg_0),\n .I3(\\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ),\n .I4(\\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ),\n .I5(\\mpr_4to1.stable_idel_cnt[2]_i_4_n_0 ),\n .O(stable_idel_cnt));\n (* SOFT_HLUTNM = \"soft_lutpair228\" *) \n LUT3 #(\n .INIT(8'hFE)) \n \\mpr_4to1.stable_idel_cnt[2]_i_3 \n (.I0(\\mpr_4to1.stable_idel_cnt[2]_i_4_n_0 ),\n .I1(\\mpr_4to1.stable_idel_cnt[2]_i_5_n_0 ),\n .I2(rstdiv0_sync_r1_reg_rep__23),\n .O(stable_idel_cnt0));\n LUT6 #(\n .INIT(64'hFFFFFFFFBEFFFFBE)) \n \\mpr_4to1.stable_idel_cnt[2]_i_4 \n (.I0(\\mpr_4to1.stable_idel_cnt[2]_i_6_n_0 ),\n .I1(\\gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ),\n .I2(mpr_rd_fall0_prev_r),\n .I3(\\gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ),\n .I4(mpr_rd_rise2_prev_r),\n .I5(\\mpr_4to1.stable_idel_cnt[2]_i_7_n_0 ),\n .O(\\mpr_4to1.stable_idel_cnt[2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000004)) \n \\mpr_4to1.stable_idel_cnt[2]_i_5 \n (.I0(out[3]),\n .I1(cal1_state_r),\n .I2(out[2]),\n .I3(out[0]),\n .I4(out[4]),\n .I5(out[1]),\n .O(\\mpr_4to1.stable_idel_cnt[2]_i_5_n_0 ));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\mpr_4to1.stable_idel_cnt[2]_i_6 \n (.I0(\\gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ),\n .I1(mpr_rd_fall2_prev_r),\n .I2(\\gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ),\n .I3(mpr_rd_rise1_prev_r),\n .O(\\mpr_4to1.stable_idel_cnt[2]_i_6_n_0 ));\n LUT5 #(\n .INIT(32'hFFFF6FF6)) \n \\mpr_4to1.stable_idel_cnt[2]_i_7 \n (.I0(mpr_rd_rise0_prev_r),\n .I1(\\gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ),\n .I2(mpr_rd_fall3_prev_r),\n .I3(\\gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ),\n .I4(\\mpr_4to1.stable_idel_cnt[2]_i_8_n_0 ),\n .O(\\mpr_4to1.stable_idel_cnt[2]_i_7_n_0 ));\n LUT4 #(\n .INIT(16'h6FF6)) \n \\mpr_4to1.stable_idel_cnt[2]_i_8 \n (.I0(\\gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ),\n .I1(mpr_rd_fall1_prev_r),\n .I2(\\gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ),\n .I3(mpr_rd_rise3_prev_r),\n .O(\\mpr_4to1.stable_idel_cnt[2]_i_8_n_0 ));\n FDRE \\mpr_4to1.stable_idel_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mpr_4to1.stable_idel_cnt[0]_i_1_n_0 ),\n .Q(\\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\mpr_4to1.stable_idel_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mpr_4to1.stable_idel_cnt[1]_i_1_n_0 ),\n .Q(\\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ),\n .R(1'b0));\n FDRE \\mpr_4to1.stable_idel_cnt_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\mpr_4to1.stable_idel_cnt[2]_i_1_n_0 ),\n .Q(\\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ),\n .R(1'b0));\n LUT3 #(\n .INIT(8'h24)) \n mpr_dec_cpt_r_i_2\n (.I0(out[0]),\n .I1(out[1]),\n .I2(out[2]),\n .O(mpr_dec_cpt_r_reg_1));\n FDRE mpr_dec_cpt_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_cal1_state_r_reg[3]_0 ),\n .Q(mpr_dec_cpt_r_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n LUT6 #(\n .INIT(64'h0300000000002323)) \n mpr_last_byte_done_i_2\n (.I0(cal1_state_r1),\n .I1(mpr_rank_done_r_reg_0),\n .I2(cal1_state_r),\n .I3(cal1_cnt_cpt_r1),\n .I4(out[3]),\n .I5(out[4]),\n .O(mpr_last_byte_done_reg_0));\n FDRE mpr_last_byte_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_cal1_state_r_reg[4]_1 ),\n .Q(mpr_last_byte_done),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n LUT6 #(\n .INIT(64'hFBFFFFFFFFFFFFFF)) \n mpr_rank_done_r_i_2\n (.I0(cal1_state_r),\n .I1(out[4]),\n .I2(mpr_rdlvl_done_r1_reg_0),\n .I3(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I4(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .I5(prech_done),\n .O(mpr_rank_done_r_reg_1));\n LUT5 #(\n .INIT(32'h7E7EFFFE)) \n mpr_rank_done_r_i_3\n (.I0(out[0]),\n .I1(out[2]),\n .I2(out[3]),\n .I3(cal1_state_r),\n .I4(out[1]),\n .O(mpr_rank_done_r_reg_0));\n FDRE mpr_rank_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_cal1_state_r_reg[4]_2 ),\n .Q(mpr_rnk_done),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE mpr_rd_fall0_prev_r_reg\n (.C(CLK),\n .CE(mpr_rd_rise0_prev_r0),\n .D(\\gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ),\n .Q(mpr_rd_fall0_prev_r),\n .R(1'b0));\n FDRE mpr_rd_fall1_prev_r_reg\n (.C(CLK),\n .CE(mpr_rd_rise0_prev_r0),\n .D(\\gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ),\n .Q(mpr_rd_fall1_prev_r),\n .R(1'b0));\n FDRE mpr_rd_fall2_prev_r_reg\n (.C(CLK),\n .CE(mpr_rd_rise0_prev_r0),\n .D(\\gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ),\n .Q(mpr_rd_fall2_prev_r),\n .R(1'b0));\n FDRE mpr_rd_fall3_prev_r_reg\n (.C(CLK),\n .CE(mpr_rd_rise0_prev_r0),\n .D(\\gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ),\n .Q(mpr_rd_fall3_prev_r),\n .R(1'b0));\n FDRE mpr_rd_rise0_prev_r_reg\n (.C(CLK),\n .CE(mpr_rd_rise0_prev_r0),\n .D(\\gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ),\n .Q(mpr_rd_rise0_prev_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0000300000001000)) \n mpr_rd_rise1_prev_r_i_1\n (.I0(out[1]),\n .I1(out[3]),\n .I2(mpr_rd_rise0_prev_r_reg_1),\n .I3(out[0]),\n .I4(out[2]),\n .I5(mpr_rd_rise0_prev_r_reg_0),\n .O(mpr_rd_rise0_prev_r0));\n LUT2 #(\n .INIT(4'h1)) \n mpr_rd_rise1_prev_r_i_2\n (.I0(cal1_state_r),\n .I1(out[4]),\n .O(mpr_rd_rise0_prev_r_reg_1));\n FDRE mpr_rd_rise1_prev_r_reg\n (.C(CLK),\n .CE(mpr_rd_rise0_prev_r0),\n .D(\\gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ),\n .Q(mpr_rd_rise1_prev_r),\n .R(1'b0));\n FDRE mpr_rd_rise2_prev_r_reg\n (.C(CLK),\n .CE(mpr_rd_rise0_prev_r0),\n .D(\\gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ),\n .Q(mpr_rd_rise2_prev_r),\n .R(1'b0));\n FDRE mpr_rd_rise3_prev_r_reg\n (.C(CLK),\n .CE(mpr_rd_rise0_prev_r0),\n .D(\\gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ),\n .Q(mpr_rd_rise3_prev_r),\n .R(1'b0));\n FDRE mpr_rdlvl_done_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mpr_rdlvl_done_r1_reg_0),\n .Q(mpr_rdlvl_done_r1),\n .R(1'b0));\n FDRE mpr_rdlvl_done_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mpr_rdlvl_done_r1),\n .Q(mpr_rdlvl_done_r2),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0000000000001000)) \n mpr_rdlvl_done_r_i_2\n (.I0(out[1]),\n .I1(out[4]),\n .I2(cal1_state_r),\n .I3(out[0]),\n .I4(out[3]),\n .I5(out[2]),\n .O(rdlvl_stg1_done_int));\n FDRE mpr_rdlvl_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mpr_rdlvl_done_r_reg_0),\n .Q(mpr_rdlvl_done_r1_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE mpr_rdlvl_start_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mpr_rdlvl_start_reg),\n .Q(mpr_rdlvl_start_r),\n .R(1'b0));\n FDRE mpr_valid_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mpr_valid_r1_reg_0),\n .Q(mpr_valid_r1),\n .R(1'b0));\n FDRE mpr_valid_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mpr_valid_r1),\n .Q(mpr_valid_r2),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00000008)) \n mpr_valid_r_i_1\n (.I0(mpr_rdlvl_start_reg),\n .I1(phy_rddata_en_1),\n .I2(rstdiv0_sync_r1_reg_rep__20),\n .I3(mpr_rdlvl_done_r1_reg_0),\n .I4(mpr_valid_r_reg_0),\n .O(mpr_valid_r));\n FDRE mpr_valid_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mpr_valid_r),\n .Q(mpr_valid_r1_reg_0),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h4000000000000001)) \n new_cnt_cpt_r_i_1\n (.I0(new_cnt_cpt_r_i_2_n_0),\n .I1(out[2]),\n .I2(out[3]),\n .I3(out[4]),\n .I4(out[0]),\n .I5(out[1]),\n .O(new_cnt_cpt_r));\n LUT6 #(\n .INIT(64'hAAAAFFEFFFFFFFEF)) \n new_cnt_cpt_r_i_2\n (.I0(cal1_state_r),\n .I1(cal1_state_r1535_out),\n .I2(rdlvl_stg1_start_reg),\n .I3(rdlvl_stg1_start_r),\n .I4(out[4]),\n .I5(new_cnt_cpt_r82_out),\n .O(new_cnt_cpt_r_i_2_n_0));\n LUT6 #(\n .INIT(64'h8880AAAAAAAAAAAA)) \n new_cnt_cpt_r_i_3\n (.I0(prech_done),\n .I1(mpr_rdlvl_done_r1_reg_0),\n .I2(\\rnk_cnt_r_reg_n_0_[0] ),\n .I3(\\rnk_cnt_r_reg_n_0_[1] ),\n .I4(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I5(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .O(new_cnt_cpt_r82_out));\n FDRE new_cnt_cpt_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(new_cnt_cpt_r),\n .Q(new_cnt_cpt_r_reg_n_0),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n (* SOFT_HLUTNM = \"soft_lutpair90\" *) \n LUT5 #(\n .INIT(32'h0000EA00)) \n \\phaser_in_gen.phaser_in_i_1 \n (.I0(calib_in_common),\n .I1(\\calib_sel_reg[3] [1]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(pi_counter_load_en),\n .I4(Q),\n .O(\\pi_dqs_found_lanes_r1_reg[3]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair99\" *) \n LUT5 #(\n .INIT(32'h44440040)) \n \\phaser_in_gen.phaser_in_i_10 \n (.I0(Q),\n .I1(pi_counter_load_val[1]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[1]_2 [1]));\n (* SOFT_HLUTNM = \"soft_lutpair105\" *) \n LUT5 #(\n .INIT(32'h44440040)) \n \\phaser_in_gen.phaser_in_i_10__0 \n (.I0(Q),\n .I1(pi_counter_load_val[1]),\n .I2(\\calib_sel_reg[3] [1]),\n .I3(\\calib_sel_reg[3] [0]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[2]_2 [1]));\n (* SOFT_HLUTNM = \"soft_lutpair105\" *) \n LUT5 #(\n .INIT(32'h44444000)) \n \\phaser_in_gen.phaser_in_i_10__1 \n (.I0(Q),\n .I1(pi_counter_load_val[1]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[3]_2 [1]));\n (* SOFT_HLUTNM = \"soft_lutpair99\" *) \n LUT5 #(\n .INIT(32'h44440004)) \n \\phaser_in_gen.phaser_in_i_10__2 \n (.I0(Q),\n .I1(pi_counter_load_val[1]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(COUNTERLOADVAL[1]));\n (* SOFT_HLUTNM = \"soft_lutpair100\" *) \n LUT5 #(\n .INIT(32'h44440040)) \n \\phaser_in_gen.phaser_in_i_11 \n (.I0(Q),\n .I1(pi_counter_load_val[0]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[1]_2 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair106\" *) \n LUT5 #(\n .INIT(32'h44440040)) \n \\phaser_in_gen.phaser_in_i_11__0 \n (.I0(Q),\n .I1(pi_counter_load_val[0]),\n .I2(\\calib_sel_reg[3] [1]),\n .I3(\\calib_sel_reg[3] [0]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[2]_2 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair106\" *) \n LUT5 #(\n .INIT(32'h44444000)) \n \\phaser_in_gen.phaser_in_i_11__1 \n (.I0(Q),\n .I1(pi_counter_load_val[0]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[3]_2 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair100\" *) \n LUT5 #(\n .INIT(32'h44440004)) \n \\phaser_in_gen.phaser_in_i_11__2 \n (.I0(Q),\n .I1(pi_counter_load_val[0]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(COUNTERLOADVAL[0]));\n (* SOFT_HLUTNM = \"soft_lutpair111\" *) \n LUT5 #(\n .INIT(32'h0000BA00)) \n \\phaser_in_gen.phaser_in_i_1__0 \n (.I0(calib_in_common),\n .I1(\\calib_sel_reg[3] [0]),\n .I2(\\calib_sel_reg[3] [1]),\n .I3(pi_counter_load_en),\n .I4(Q),\n .O(\\pi_dqs_found_lanes_r1_reg[2]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair90\" *) \n LUT5 #(\n .INIT(32'h0000BA00)) \n \\phaser_in_gen.phaser_in_i_1__1 \n (.I0(calib_in_common),\n .I1(\\calib_sel_reg[3] [1]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(pi_counter_load_en),\n .I4(Q),\n .O(\\pi_dqs_found_lanes_r1_reg[1]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair111\" *) \n LUT5 #(\n .INIT(32'h0000AB00)) \n \\phaser_in_gen.phaser_in_i_1__2 \n (.I0(calib_in_common),\n .I1(\\calib_sel_reg[3] [1]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(pi_counter_load_en),\n .I4(Q),\n .O(\\pi_dqs_found_lanes_r1_reg[0]_1 ));\n LUT5 #(\n .INIT(32'h0000AAA8)) \n \\phaser_in_gen.phaser_in_i_3 \n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .I1(rdlvl_pi_stg2_f_en),\n .I2(prbs_pi_stg2_f_en),\n .I3(tempmon_pi_f_en_r),\n .I4(Q),\n .O(\\pi_dqs_found_lanes_r1_reg[3]_0 ));\n LUT5 #(\n .INIT(32'h0000AAA8)) \n \\phaser_in_gen.phaser_in_i_3__0 \n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .I1(rdlvl_pi_stg2_f_en),\n .I2(prbs_pi_stg2_f_en),\n .I3(tempmon_pi_f_en_r),\n .I4(Q),\n .O(\\pi_dqs_found_lanes_r1_reg[2]_0 ));\n LUT5 #(\n .INIT(32'h0000AAA8)) \n \\phaser_in_gen.phaser_in_i_3__1 \n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_2 ),\n .I1(rdlvl_pi_stg2_f_en),\n .I2(prbs_pi_stg2_f_en),\n .I3(tempmon_pi_f_en_r),\n .I4(Q),\n .O(\\pi_dqs_found_lanes_r1_reg[1]_0 ));\n LUT5 #(\n .INIT(32'h0000AAA8)) \n \\phaser_in_gen.phaser_in_i_3__2 \n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_3 ),\n .I1(rdlvl_pi_stg2_f_en),\n .I2(prbs_pi_stg2_f_en),\n .I3(tempmon_pi_f_en_r),\n .I4(Q),\n .O(\\pi_dqs_found_lanes_r1_reg[0]_0 ));\n LUT5 #(\n .INIT(32'h0000AAA8)) \n \\phaser_in_gen.phaser_in_i_4 \n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_0 ),\n .I1(rdlvl_pi_stg2_f_incdec),\n .I2(prbs_pi_stg2_f_incdec),\n .I3(tempmon_pi_f_inc_r),\n .I4(Q),\n .O(\\pi_dqs_found_lanes_r1_reg[3] ));\n LUT5 #(\n .INIT(32'h0000AAA8)) \n \\phaser_in_gen.phaser_in_i_4__0 \n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_1 ),\n .I1(rdlvl_pi_stg2_f_incdec),\n .I2(prbs_pi_stg2_f_incdec),\n .I3(tempmon_pi_f_inc_r),\n .I4(Q),\n .O(\\pi_dqs_found_lanes_r1_reg[2] ));\n LUT5 #(\n .INIT(32'h0000AAA8)) \n \\phaser_in_gen.phaser_in_i_4__1 \n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_2 ),\n .I1(rdlvl_pi_stg2_f_incdec),\n .I2(prbs_pi_stg2_f_incdec),\n .I3(tempmon_pi_f_inc_r),\n .I4(Q),\n .O(\\pi_dqs_found_lanes_r1_reg[1] ));\n LUT5 #(\n .INIT(32'h0000AAA8)) \n \\phaser_in_gen.phaser_in_i_4__2 \n (.I0(\\gen_byte_sel_div1.calib_in_common_reg_3 ),\n .I1(rdlvl_pi_stg2_f_incdec),\n .I2(prbs_pi_stg2_f_incdec),\n .I3(tempmon_pi_f_inc_r),\n .I4(Q),\n .O(\\pi_dqs_found_lanes_r1_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair95\" *) \n LUT5 #(\n .INIT(32'h44440040)) \n \\phaser_in_gen.phaser_in_i_6 \n (.I0(Q),\n .I1(pi_counter_load_val[5]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[1]_2 [5]));\n (* SOFT_HLUTNM = \"soft_lutpair101\" *) \n LUT5 #(\n .INIT(32'h44440040)) \n \\phaser_in_gen.phaser_in_i_6__0 \n (.I0(Q),\n .I1(pi_counter_load_val[5]),\n .I2(\\calib_sel_reg[3] [1]),\n .I3(\\calib_sel_reg[3] [0]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[2]_2 [5]));\n (* SOFT_HLUTNM = \"soft_lutpair101\" *) \n LUT5 #(\n .INIT(32'h44444000)) \n \\phaser_in_gen.phaser_in_i_6__1 \n (.I0(Q),\n .I1(pi_counter_load_val[5]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[3]_2 [5]));\n (* SOFT_HLUTNM = \"soft_lutpair95\" *) \n LUT5 #(\n .INIT(32'h44440004)) \n \\phaser_in_gen.phaser_in_i_6__2 \n (.I0(Q),\n .I1(pi_counter_load_val[5]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(COUNTERLOADVAL[5]));\n (* SOFT_HLUTNM = \"soft_lutpair96\" *) \n LUT5 #(\n .INIT(32'h44440040)) \n \\phaser_in_gen.phaser_in_i_7 \n (.I0(Q),\n .I1(pi_counter_load_val[4]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[1]_2 [4]));\n (* SOFT_HLUTNM = \"soft_lutpair102\" *) \n LUT5 #(\n .INIT(32'h44440040)) \n \\phaser_in_gen.phaser_in_i_7__0 \n (.I0(Q),\n .I1(pi_counter_load_val[4]),\n .I2(\\calib_sel_reg[3] [1]),\n .I3(\\calib_sel_reg[3] [0]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[2]_2 [4]));\n (* SOFT_HLUTNM = \"soft_lutpair102\" *) \n LUT5 #(\n .INIT(32'h44444000)) \n \\phaser_in_gen.phaser_in_i_7__1 \n (.I0(Q),\n .I1(pi_counter_load_val[4]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[3]_2 [4]));\n (* SOFT_HLUTNM = \"soft_lutpair96\" *) \n LUT5 #(\n .INIT(32'h44440004)) \n \\phaser_in_gen.phaser_in_i_7__2 \n (.I0(Q),\n .I1(pi_counter_load_val[4]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(COUNTERLOADVAL[4]));\n (* SOFT_HLUTNM = \"soft_lutpair97\" *) \n LUT5 #(\n .INIT(32'h44440040)) \n \\phaser_in_gen.phaser_in_i_8 \n (.I0(Q),\n .I1(pi_counter_load_val[3]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[1]_2 [3]));\n (* SOFT_HLUTNM = \"soft_lutpair103\" *) \n LUT5 #(\n .INIT(32'h44440040)) \n \\phaser_in_gen.phaser_in_i_8__0 \n (.I0(Q),\n .I1(pi_counter_load_val[3]),\n .I2(\\calib_sel_reg[3] [1]),\n .I3(\\calib_sel_reg[3] [0]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[2]_2 [3]));\n (* SOFT_HLUTNM = \"soft_lutpair103\" *) \n LUT5 #(\n .INIT(32'h44444000)) \n \\phaser_in_gen.phaser_in_i_8__1 \n (.I0(Q),\n .I1(pi_counter_load_val[3]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[3]_2 [3]));\n (* SOFT_HLUTNM = \"soft_lutpair97\" *) \n LUT5 #(\n .INIT(32'h44440004)) \n \\phaser_in_gen.phaser_in_i_8__2 \n (.I0(Q),\n .I1(pi_counter_load_val[3]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(COUNTERLOADVAL[3]));\n (* SOFT_HLUTNM = \"soft_lutpair98\" *) \n LUT5 #(\n .INIT(32'h44440040)) \n \\phaser_in_gen.phaser_in_i_9 \n (.I0(Q),\n .I1(pi_counter_load_val[2]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[1]_2 [2]));\n (* SOFT_HLUTNM = \"soft_lutpair104\" *) \n LUT5 #(\n .INIT(32'h44440040)) \n \\phaser_in_gen.phaser_in_i_9__0 \n (.I0(Q),\n .I1(pi_counter_load_val[2]),\n .I2(\\calib_sel_reg[3] [1]),\n .I3(\\calib_sel_reg[3] [0]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[2]_2 [2]));\n (* SOFT_HLUTNM = \"soft_lutpair104\" *) \n LUT5 #(\n .INIT(32'h44444000)) \n \\phaser_in_gen.phaser_in_i_9__1 \n (.I0(Q),\n .I1(pi_counter_load_val[2]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(\\pi_dqs_found_lanes_r1_reg[3]_2 [2]));\n (* SOFT_HLUTNM = \"soft_lutpair98\" *) \n LUT5 #(\n .INIT(32'h44440004)) \n \\phaser_in_gen.phaser_in_i_9__2 \n (.I0(Q),\n .I1(pi_counter_load_val[2]),\n .I2(\\calib_sel_reg[3] [0]),\n .I3(\\calib_sel_reg[3] [1]),\n .I4(calib_in_common),\n .O(COUNTERLOADVAL[2]));\n (* SOFT_HLUTNM = \"soft_lutpair209\" *) \n LUT2 #(\n .INIT(4'hE)) \n pi_cnt_dec_i_2\n (.I0(wait_cnt_r_reg__0[2]),\n .I1(wait_cnt_r_reg__0[3]),\n .O(pi_cnt_dec_reg_0));\n FDRE pi_cnt_dec_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\wait_cnt_r_reg[0]_1 ),\n .Q(pi_en_stg2_f_timing_reg_0),\n .R(1'b0));\n FDRE pi_en_stg2_f_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_en_stg2_f_timing),\n .Q(rdlvl_pi_stg2_f_en),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair235\" *) \n LUT2 #(\n .INIT(4'hE)) \n pi_en_stg2_f_timing_i_1\n (.I0(cal1_dlyce_cpt_r_reg_n_0),\n .I1(pi_en_stg2_f_timing_reg_0),\n .O(pi_en_stg2_f_timing_i_1_n_0));\n FDRE pi_en_stg2_f_timing_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_en_stg2_f_timing_i_1_n_0),\n .Q(pi_en_stg2_f_timing),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE pi_fine_dly_dec_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(fine_dly_dec_done_r2),\n .Q(pi_fine_dly_dec_done),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h40404F40)) \n \\pi_rdval_cnt[0]_i_1 \n (.I0(\\calib_sel_reg[3] [2]),\n .I1(\\pi_counter_read_val_reg[5] [0]),\n .I2(\\pi_rdval_cnt[5]_i_4_n_0 ),\n .I3(\\pi_rdval_cnt_reg[1]_0 ),\n .I4(pi_rdval_cnt[0]),\n .O(\\pi_rdval_cnt[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFB0808FBFB08FB08)) \n \\pi_rdval_cnt[1]_i_1 \n (.I0(\\rdlvl_cpt_tap_cnt_reg[1] ),\n .I1(dqs_po_dec_done_r1),\n .I2(dqs_po_dec_done_r2),\n .I3(pi_rdval_cnt[1]),\n .I4(pi_rdval_cnt[0]),\n .I5(\\pi_rdval_cnt_reg[1]_0 ),\n .O(\\pi_rdval_cnt[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hB8B8B888888888B8)) \n \\pi_rdval_cnt[2]_i_1 \n (.I0(\\rdlvl_cpt_tap_cnt_reg[2] ),\n .I1(\\pi_rdval_cnt[5]_i_4_n_0 ),\n .I2(\\pi_rdval_cnt_reg[1]_0 ),\n .I3(pi_rdval_cnt[1]),\n .I4(pi_rdval_cnt[0]),\n .I5(pi_rdval_cnt[2]),\n .O(\\pi_rdval_cnt[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0808FB08FB080808)) \n \\pi_rdval_cnt[3]_i_1 \n (.I0(\\calib_sel_reg[3]_0 [1]),\n .I1(dqs_po_dec_done_r1),\n .I2(dqs_po_dec_done_r2),\n .I3(\\pi_rdval_cnt_reg[1]_0 ),\n .I4(\\pi_rdval_cnt[3]_i_2_n_0 ),\n .I5(pi_rdval_cnt[3]),\n .O(\\pi_rdval_cnt[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair202\" *) \n LUT3 #(\n .INIT(8'h01)) \n \\pi_rdval_cnt[3]_i_2 \n (.I0(pi_rdval_cnt[0]),\n .I1(pi_rdval_cnt[1]),\n .I2(pi_rdval_cnt[2]),\n .O(\\pi_rdval_cnt[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0808FBFBFB080808)) \n \\pi_rdval_cnt[4]_i_1 \n (.I0(\\rdlvl_cpt_tap_cnt_reg[4] ),\n .I1(dqs_po_dec_done_r1),\n .I2(dqs_po_dec_done_r2),\n .I3(pi_rdval_cnt[5]),\n .I4(\\pi_rdval_cnt[4]_i_2_n_0 ),\n .I5(pi_rdval_cnt[4]),\n .O(\\pi_rdval_cnt[4]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair187\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\pi_rdval_cnt[4]_i_2 \n (.I0(pi_rdval_cnt[2]),\n .I1(pi_rdval_cnt[1]),\n .I2(pi_rdval_cnt[0]),\n .I3(pi_rdval_cnt[3]),\n .O(\\pi_rdval_cnt[4]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'hBBFB)) \n \\pi_rdval_cnt[5]_i_1 \n (.I0(pi_en_stg2_f_timing_reg_0),\n .I1(\\pi_rdval_cnt_reg[1]_0 ),\n .I2(dqs_po_dec_done_r1),\n .I3(dqs_po_dec_done_r2),\n .O(\\pi_rdval_cnt[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h40404F40)) \n \\pi_rdval_cnt[5]_i_2 \n (.I0(\\calib_sel_reg[3] [2]),\n .I1(\\pi_counter_read_val_reg[5] [4]),\n .I2(\\pi_rdval_cnt[5]_i_4_n_0 ),\n .I3(pi_rdval_cnt[5]),\n .I4(\\pi_rdval_cnt[5]_i_5_n_0 ),\n .O(\\pi_rdval_cnt[5]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\pi_rdval_cnt[5]_i_3 \n (.I0(pi_rdval_cnt[5]),\n .I1(pi_rdval_cnt[4]),\n .I2(pi_rdval_cnt[2]),\n .I3(pi_rdval_cnt[1]),\n .I4(pi_rdval_cnt[0]),\n .I5(pi_rdval_cnt[3]),\n .O(\\pi_rdval_cnt_reg[1]_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\pi_rdval_cnt[5]_i_4 \n (.I0(dqs_po_dec_done_r1),\n .I1(dqs_po_dec_done_r2),\n .O(\\pi_rdval_cnt[5]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair187\" *) \n LUT5 #(\n .INIT(32'h00000001)) \n \\pi_rdval_cnt[5]_i_5 \n (.I0(pi_rdval_cnt[3]),\n .I1(pi_rdval_cnt[0]),\n .I2(pi_rdval_cnt[1]),\n .I3(pi_rdval_cnt[2]),\n .I4(pi_rdval_cnt[4]),\n .O(\\pi_rdval_cnt[5]_i_5_n_0 ));\n FDRE \\pi_rdval_cnt_reg[0] \n (.C(CLK),\n .CE(\\pi_rdval_cnt[5]_i_1_n_0 ),\n .D(\\pi_rdval_cnt[0]_i_1_n_0 ),\n .Q(pi_rdval_cnt[0]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE \\pi_rdval_cnt_reg[1] \n (.C(CLK),\n .CE(\\pi_rdval_cnt[5]_i_1_n_0 ),\n .D(\\pi_rdval_cnt[1]_i_1_n_0 ),\n .Q(pi_rdval_cnt[1]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE \\pi_rdval_cnt_reg[2] \n (.C(CLK),\n .CE(\\pi_rdval_cnt[5]_i_1_n_0 ),\n .D(\\pi_rdval_cnt[2]_i_1_n_0 ),\n .Q(pi_rdval_cnt[2]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE \\pi_rdval_cnt_reg[3] \n (.C(CLK),\n .CE(\\pi_rdval_cnt[5]_i_1_n_0 ),\n .D(\\pi_rdval_cnt[3]_i_1_n_0 ),\n .Q(pi_rdval_cnt[3]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE \\pi_rdval_cnt_reg[4] \n (.C(CLK),\n .CE(\\pi_rdval_cnt[5]_i_1_n_0 ),\n .D(\\pi_rdval_cnt[4]_i_1_n_0 ),\n .Q(pi_rdval_cnt[4]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE \\pi_rdval_cnt_reg[5] \n (.C(CLK),\n .CE(\\pi_rdval_cnt[5]_i_1_n_0 ),\n .D(\\pi_rdval_cnt[5]_i_2_n_0 ),\n .Q(pi_rdval_cnt[5]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE pi_stg2_f_incdec_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_stg2_f_incdec_timing),\n .Q(rdlvl_pi_stg2_f_incdec),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair201\" *) \n LUT4 #(\n .INIT(16'h0008)) \n pi_stg2_f_incdec_timing_i_1__0\n (.I0(cal1_dlyce_cpt_r_reg_n_0),\n .I1(cal1_dlyinc_cpt_r_reg_n_0),\n .I2(pi_en_stg2_f_timing_reg_0),\n .I3(rstdiv0_sync_r1_reg_rep__23),\n .O(pi_stg2_f_incdec_timing0));\n FDRE pi_stg2_f_incdec_timing_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_stg2_f_incdec_timing0),\n .Q(pi_stg2_f_incdec_timing),\n .R(1'b0));\n FDRE pi_stg2_load_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_stg2_load_timing),\n .Q(pi_counter_load_en),\n .R(1'b0));\n FDRE pi_stg2_load_timing_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\regl_dqs_cnt_reg[2]_0 ),\n .Q(pi_stg2_load_timing),\n .R(1'b0));\n FDRE \\pi_stg2_reg_l_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_stg2_reg_l_timing[0]),\n .Q(pi_counter_load_val[0]),\n .R(1'b0));\n FDRE \\pi_stg2_reg_l_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_stg2_reg_l_timing[1]),\n .Q(pi_counter_load_val[1]),\n .R(1'b0));\n FDRE \\pi_stg2_reg_l_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_stg2_reg_l_timing[2]),\n .Q(pi_counter_load_val[2]),\n .R(1'b0));\n FDRE \\pi_stg2_reg_l_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_stg2_reg_l_timing[3]),\n .Q(pi_counter_load_val[3]),\n .R(1'b0));\n FDRE \\pi_stg2_reg_l_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_stg2_reg_l_timing[4]),\n .Q(pi_counter_load_val[4]),\n .R(1'b0));\n FDRE \\pi_stg2_reg_l_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(pi_stg2_reg_l_timing[5]),\n .Q(pi_counter_load_val[5]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\pi_stg2_reg_l_timing[0]_i_1 \n (.I0(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][0] ),\n .I1(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][0] ),\n .I2(regl_dqs_cnt[0]),\n .I3(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][0] ),\n .I4(regl_dqs_cnt[1]),\n .I5(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][0] ),\n .O(\\pi_stg2_reg_l_timing[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\pi_stg2_reg_l_timing[1]_i_1 \n (.I0(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][1] ),\n .I1(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][1] ),\n .I2(regl_dqs_cnt[0]),\n .I3(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][1] ),\n .I4(regl_dqs_cnt[1]),\n .I5(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][1] ),\n .O(\\pi_stg2_reg_l_timing[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\pi_stg2_reg_l_timing[2]_i_1 \n (.I0(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][2] ),\n .I1(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][2] ),\n .I2(regl_dqs_cnt[0]),\n .I3(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][2] ),\n .I4(regl_dqs_cnt[1]),\n .I5(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][2] ),\n .O(\\pi_stg2_reg_l_timing[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\pi_stg2_reg_l_timing[3]_i_1 \n (.I0(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][3] ),\n .I1(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][3] ),\n .I2(regl_dqs_cnt[0]),\n .I3(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][3] ),\n .I4(regl_dqs_cnt[1]),\n .I5(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][3] ),\n .O(\\pi_stg2_reg_l_timing[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\pi_stg2_reg_l_timing[4]_i_1 \n (.I0(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][4] ),\n .I1(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][4] ),\n .I2(regl_dqs_cnt[0]),\n .I3(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][4] ),\n .I4(regl_dqs_cnt[1]),\n .I5(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][4] ),\n .O(\\pi_stg2_reg_l_timing[4]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hEF)) \n \\pi_stg2_reg_l_timing[5]_i_1 \n (.I0(\\pi_stg2_reg_l_timing_reg[0]_0 ),\n .I1(\\regl_dqs_cnt_r_reg[2]_0 ),\n .I2(\\regl_dqs_cnt_reg[0]_0 ),\n .O(\\pi_stg2_reg_l_timing[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\pi_stg2_reg_l_timing[5]_i_2 \n (.I0(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][5] ),\n .I1(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][5] ),\n .I2(regl_dqs_cnt[0]),\n .I3(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][5] ),\n .I4(regl_dqs_cnt[1]),\n .I5(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][5] ),\n .O(\\pi_stg2_reg_l_timing[5]_i_2_n_0 ));\n FDRE \\pi_stg2_reg_l_timing_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\pi_stg2_reg_l_timing[0]_i_1_n_0 ),\n .Q(pi_stg2_reg_l_timing[0]),\n .R(\\pi_stg2_reg_l_timing[5]_i_1_n_0 ));\n FDRE \\pi_stg2_reg_l_timing_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\pi_stg2_reg_l_timing[1]_i_1_n_0 ),\n .Q(pi_stg2_reg_l_timing[1]),\n .R(\\pi_stg2_reg_l_timing[5]_i_1_n_0 ));\n FDRE \\pi_stg2_reg_l_timing_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\pi_stg2_reg_l_timing[2]_i_1_n_0 ),\n .Q(pi_stg2_reg_l_timing[2]),\n .R(\\pi_stg2_reg_l_timing[5]_i_1_n_0 ));\n FDRE \\pi_stg2_reg_l_timing_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\pi_stg2_reg_l_timing[3]_i_1_n_0 ),\n .Q(pi_stg2_reg_l_timing[3]),\n .R(\\pi_stg2_reg_l_timing[5]_i_1_n_0 ));\n FDRE \\pi_stg2_reg_l_timing_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\pi_stg2_reg_l_timing[4]_i_1_n_0 ),\n .Q(pi_stg2_reg_l_timing[4]),\n .R(\\pi_stg2_reg_l_timing[5]_i_1_n_0 ));\n FDRE \\pi_stg2_reg_l_timing_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\pi_stg2_reg_l_timing[5]_i_2_n_0 ),\n .Q(pi_stg2_reg_l_timing[5]),\n .R(\\pi_stg2_reg_l_timing[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFEFFFEFFFFFFFE)) \n prech_req_r_i_1\n (.I0(rdlvl_prech_req),\n .I1(wrcal_prech_req),\n .I2(complex_ocal_ref_req),\n .I3(prbs_rdlvl_prech_req_reg),\n .I4(dqs_found_prech_req),\n .I5(\\init_state_r_reg[5]_0 ),\n .O(prech_req));\n FDRE \\rd_mux_sel_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [0]),\n .R(1'b0));\n FDRE \\rd_mux_sel_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [1]),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair239\" *) \n LUT2 #(\n .INIT(4'h4)) \n \\rdlvl_cpt_tap_cnt[1]_i_1 \n (.I0(\\calib_sel_reg[3] [2]),\n .I1(\\pi_counter_read_val_reg[5] [1]),\n .O(\\rdlvl_cpt_tap_cnt_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair239\" *) \n LUT2 #(\n .INIT(4'h4)) \n \\rdlvl_cpt_tap_cnt[2]_i_1 \n (.I0(\\calib_sel_reg[3] [2]),\n .I1(\\pi_counter_read_val_reg[5] [2]),\n .O(\\rdlvl_cpt_tap_cnt_reg[2] ));\n LUT2 #(\n .INIT(4'h4)) \n \\rdlvl_cpt_tap_cnt[4]_i_1 \n (.I0(\\calib_sel_reg[3] [2]),\n .I1(\\pi_counter_read_val_reg[5] [3]),\n .O(\\rdlvl_cpt_tap_cnt_reg[4] ));\n LUT5 #(\n .INIT(32'h00000001)) \n \\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1 \n (.I0(\\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ),\n .I1(\\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [0]),\n .I2(\\rnk_cnt_r_reg_n_0_[1] ),\n .I3(\\rnk_cnt_r_reg_n_0_[0] ),\n .I4(\\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [1]),\n .O(\\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFEFFFFFFFFFFFFF)) \n \\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2 \n (.I0(\\cal1_state_r1_reg_n_0_[5] ),\n .I1(\\cal1_state_r1_reg_n_0_[4] ),\n .I2(\\cal1_state_r1_reg_n_0_[2] ),\n .I3(\\cal1_state_r1_reg_n_0_[0] ),\n .I4(\\cal1_state_r1_reg_n_0_[3] ),\n .I5(\\cal1_state_r1_reg_n_0_[1] ),\n .O(\\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h00000004)) \n \\rdlvl_dqs_tap_cnt_r[0][1][5]_i_1 \n (.I0(\\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ),\n .I1(\\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [0]),\n .I2(\\rnk_cnt_r_reg_n_0_[1] ),\n .I3(\\rnk_cnt_r_reg_n_0_[0] ),\n .I4(\\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [1]),\n .O(rdlvl_dqs_tap_cnt_r));\n LUT5 #(\n .INIT(32'h00000002)) \n \\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1 \n (.I0(\\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [1]),\n .I1(\\rnk_cnt_r_reg_n_0_[1] ),\n .I2(\\rnk_cnt_r_reg_n_0_[0] ),\n .I3(\\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ),\n .I4(\\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [0]),\n .O(\\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h00020000)) \n \\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1 \n (.I0(\\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [1]),\n .I1(\\rnk_cnt_r_reg_n_0_[1] ),\n .I2(\\rnk_cnt_r_reg_n_0_[0] ),\n .I3(\\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ),\n .I4(\\rdlvl_dqs_tap_cnt_r_reg[0][3][0]_0 [0]),\n .O(\\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ));\n FDRE \\rdlvl_dqs_tap_cnt_r_reg[0][0][0] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][0] ),\n .R(rstdiv0_sync_r1_reg_rep__14[0]));\n FDRE \\rdlvl_dqs_tap_cnt_r_reg[0][0][1] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][1] ),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE \\rdlvl_dqs_tap_cnt_r_reg[0][0][2] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][2] ),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE \\rdlvl_dqs_tap_cnt_r_reg[0][0][3] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][3] ),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE \\rdlvl_dqs_tap_cnt_r_reg[0][0][4] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[4] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][4] ),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE \\rdlvl_dqs_tap_cnt_r_reg[0][0][5] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[5] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][5] ),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE \\rdlvl_dqs_tap_cnt_r_reg[0][1][0] \n (.C(CLK),\n .CE(rdlvl_dqs_tap_cnt_r),\n .D(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][0] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE \\rdlvl_dqs_tap_cnt_r_reg[0][1][1] \n (.C(CLK),\n .CE(rdlvl_dqs_tap_cnt_r),\n .D(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][1] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE \\rdlvl_dqs_tap_cnt_r_reg[0][1][2] \n (.C(CLK),\n .CE(rdlvl_dqs_tap_cnt_r),\n .D(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][2] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE \\rdlvl_dqs_tap_cnt_r_reg[0][1][3] \n (.C(CLK),\n .CE(rdlvl_dqs_tap_cnt_r),\n .D(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][3] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE \\rdlvl_dqs_tap_cnt_r_reg[0][1][4] \n (.C(CLK),\n .CE(rdlvl_dqs_tap_cnt_r),\n .D(\\tap_cnt_cpt_r_reg_n_0_[4] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][4] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE \\rdlvl_dqs_tap_cnt_r_reg[0][1][5] \n (.C(CLK),\n .CE(rdlvl_dqs_tap_cnt_r),\n .D(\\tap_cnt_cpt_r_reg_n_0_[5] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][5] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE \\rdlvl_dqs_tap_cnt_r_reg[0][2][0] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][0] ),\n .R(rstdiv0_sync_r1_reg_rep__14[0]));\n FDRE \\rdlvl_dqs_tap_cnt_r_reg[0][2][1] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][1] ),\n .R(rstdiv0_sync_r1_reg_rep__14[0]));\n FDRE \\rdlvl_dqs_tap_cnt_r_reg[0][2][2] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][2] ),\n .R(rstdiv0_sync_r1_reg_rep__14[0]));\n FDRE \\rdlvl_dqs_tap_cnt_r_reg[0][2][3] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][3] ),\n .R(rstdiv0_sync_r1_reg_rep__14[0]));\n FDRE \\rdlvl_dqs_tap_cnt_r_reg[0][2][4] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[4] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][4] ),\n .R(rstdiv0_sync_r1_reg_rep__14[0]));\n FDRE \\rdlvl_dqs_tap_cnt_r_reg[0][2][5] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[5] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][5] ),\n .R(rstdiv0_sync_r1_reg_rep__14[0]));\n FDRE \\rdlvl_dqs_tap_cnt_r_reg[0][3][0] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][0] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE \\rdlvl_dqs_tap_cnt_r_reg[0][3][1] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][1] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE \\rdlvl_dqs_tap_cnt_r_reg[0][3][2] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][2] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE \\rdlvl_dqs_tap_cnt_r_reg[0][3][3] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][3] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE \\rdlvl_dqs_tap_cnt_r_reg[0][3][4] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[4] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][4] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE \\rdlvl_dqs_tap_cnt_r_reg[0][3][5] \n (.C(CLK),\n .CE(\\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ),\n .D(\\tap_cnt_cpt_r_reg_n_0_[5] ),\n .Q(\\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][5] ),\n .R(rstdiv0_sync_r1_reg_rep__13));\n FDRE rdlvl_last_byte_done_int_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_cal1_state_r_reg[4]_4 ),\n .Q(rdlvl_last_byte_done),\n .R(rstdiv0_sync_r1_reg_rep__13));\n LUT6 #(\n .INIT(64'hFFFFFFFFCC88FEAA)) \n rdlvl_pi_incdec_i_2\n (.I0(out[3]),\n .I1(cal1_wait_r),\n .I2(store_sr_req_r_reg_0),\n .I3(out[1]),\n .I4(out[2]),\n .I5(rdlvl_pi_incdec_i_4_n_0),\n .O(rdlvl_pi_incdec_reg_0));\n LUT6 #(\n .INIT(64'h000000000000FD0D)) \n rdlvl_pi_incdec_i_4\n (.I0(mpr_rdlvl_start_reg),\n .I1(mpr_rdlvl_start_r),\n .I2(cal1_state_r),\n .I3(cal1_wait_r),\n .I4(out[1]),\n .I5(out[4]),\n .O(rdlvl_pi_incdec_i_4_n_0));\n LUT6 #(\n .INIT(64'h0000000105A5AA05)) \n rdlvl_pi_incdec_i_5\n (.I0(out[4]),\n .I1(cal1_wait_r),\n .I2(out[3]),\n .I3(out[0]),\n .I4(out[1]),\n .I5(cal1_state_r),\n .O(rdlvl_pi_incdec_i_5_n_0));\n LUT6 #(\n .INIT(64'h0000000000001000)) \n rdlvl_pi_incdec_i_6\n (.I0(out[1]),\n .I1(cal1_state_r),\n .I2(out[3]),\n .I3(out[4]),\n .I4(out[0]),\n .I5(cal1_wait_r),\n .O(rdlvl_pi_incdec_i_6_n_0));\n FDRE rdlvl_pi_incdec_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_cal1_state_r_reg[1]_0 ),\n .Q(rdlvl_pi_incdec),\n .R(rstdiv0_sync_r1_reg_rep__14[0]));\n MUXF7 rdlvl_pi_incdec_reg_i_3\n (.I0(rdlvl_pi_incdec_i_5_n_0),\n .I1(rdlvl_pi_incdec_i_6_n_0),\n .O(rdlvl_pi_incdec_reg_1),\n .S(out[2]));\n FDRE rdlvl_prech_req_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cal1_prech_req_r_reg_n_0),\n .Q(rdlvl_prech_req),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n LUT6 #(\n .INIT(64'hBFFFFFFFFFFFFFFF)) \n rdlvl_rank_done_r_i_2\n (.I0(cal1_state_r),\n .I1(out[4]),\n .I2(mpr_rdlvl_done_r1_reg_0),\n .I3(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I4(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .I5(prech_done),\n .O(rdlvl_rank_done_r_reg_0));\n FDRE rdlvl_rank_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_cal1_state_r_reg[4]_3 ),\n .Q(rdlvl_stg1_rank_done),\n .R(rstdiv0_sync_r1_reg_rep__13));\n (* syn_maxfan = \"30\" *) \n FDRE rdlvl_stg1_done_int_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mpr_rdlvl_done_r_reg_1),\n .Q(rdlvl_stg1_done_r1_reg),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE rdlvl_stg1_start_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rdlvl_stg1_start_reg),\n .Q(rdlvl_stg1_start_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0004FFFFFFFF0000)) \n \\regl_dqs_cnt[0]_i_1 \n (.I0(\\regl_dqs_cnt_r_reg[2]_0 ),\n .I1(regl_dqs_cnt[1]),\n .I2(regl_rank_cnt[0]),\n .I3(regl_rank_cnt[1]),\n .I4(\\regl_dqs_cnt_reg[0]_0 ),\n .I5(regl_dqs_cnt[0]),\n .O(\\regl_dqs_cnt[0]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hBA)) \n \\regl_dqs_cnt[1]_i_1 \n (.I0(\\pi_stg2_reg_l_timing_reg[0]_0 ),\n .I1(mpr_rdlvl_done_r2),\n .I2(mpr_rdlvl_done_r1),\n .O(\\regl_dqs_cnt[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h3337FFFFCCCC0000)) \n \\regl_dqs_cnt[1]_i_2 \n (.I0(\\regl_dqs_cnt_r_reg[2]_0 ),\n .I1(regl_dqs_cnt[0]),\n .I2(regl_rank_cnt[0]),\n .I3(regl_rank_cnt[1]),\n .I4(\\regl_dqs_cnt_reg[0]_0 ),\n .I5(regl_dqs_cnt[1]),\n .O(\\regl_dqs_cnt[1]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hAAAAAAAB)) \n \\regl_dqs_cnt[1]_i_3 \n (.I0(rstdiv0_sync_r1_reg_rep__23),\n .I1(done_cnt[2]),\n .I2(done_cnt[3]),\n .I3(done_cnt[1]),\n .I4(done_cnt[0]),\n .O(\\pi_stg2_reg_l_timing_reg[0]_0 ));\n LUT5 #(\n .INIT(32'h04444444)) \n \\regl_dqs_cnt[2]_i_1 \n (.I0(\\regl_dqs_cnt[1]_i_1_n_0 ),\n .I1(\\regl_dqs_cnt_r_reg[2]_0 ),\n .I2(regl_dqs_cnt[1]),\n .I3(regl_dqs_cnt[0]),\n .I4(\\regl_dqs_cnt_reg[0]_0 ),\n .O(\\regl_dqs_cnt[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair92\" *) \n LUT5 #(\n .INIT(32'h00000200)) \n \\regl_dqs_cnt[2]_i_2 \n (.I0(p_0_in539_in),\n .I1(done_cnt[2]),\n .I2(done_cnt[3]),\n .I3(done_cnt[0]),\n .I4(done_cnt[1]),\n .O(\\regl_dqs_cnt_reg[0]_0 ));\n LUT6 #(\n .INIT(64'h0000000000020000)) \n \\regl_dqs_cnt[2]_i_3 \n (.I0(out[1]),\n .I1(out[0]),\n .I2(out[4]),\n .I3(out[3]),\n .I4(cal1_state_r),\n .I5(out[2]),\n .O(p_0_in539_in));\n FDRE \\regl_dqs_cnt_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(regl_dqs_cnt[0]),\n .Q(regl_dqs_cnt_r[0]),\n .R(1'b0));\n FDRE \\regl_dqs_cnt_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(regl_dqs_cnt[1]),\n .Q(regl_dqs_cnt_r[1]),\n .R(1'b0));\n FDRE \\regl_dqs_cnt_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\regl_dqs_cnt_r_reg[2]_0 ),\n .Q(regl_dqs_cnt_r[2]),\n .R(1'b0));\n FDRE \\regl_dqs_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\regl_dqs_cnt[0]_i_1_n_0 ),\n .Q(regl_dqs_cnt[0]),\n .R(\\regl_dqs_cnt[1]_i_1_n_0 ));\n FDRE \\regl_dqs_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\regl_dqs_cnt[1]_i_2_n_0 ),\n .Q(regl_dqs_cnt[1]),\n .R(\\regl_dqs_cnt[1]_i_1_n_0 ));\n FDRE \\regl_dqs_cnt_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\regl_dqs_cnt[2]_i_1_n_0 ),\n .Q(\\regl_dqs_cnt_r_reg[2]_0 ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hCFFFFFFF20000000)) \n \\regl_rank_cnt[0]_i_1 \n (.I0(regl_rank_cnt[1]),\n .I1(\\regl_dqs_cnt_r_reg[2]_0 ),\n .I2(regl_dqs_cnt[1]),\n .I3(regl_dqs_cnt[0]),\n .I4(\\regl_dqs_cnt_reg[0]_0 ),\n .I5(regl_rank_cnt[0]),\n .O(\\regl_rank_cnt[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hDFFFFFFF20000000)) \n \\regl_rank_cnt[1]_i_1 \n (.I0(regl_rank_cnt[0]),\n .I1(\\regl_dqs_cnt_r_reg[2]_0 ),\n .I2(regl_dqs_cnt[1]),\n .I3(regl_dqs_cnt[0]),\n .I4(\\regl_dqs_cnt_reg[0]_0 ),\n .I5(regl_rank_cnt[1]),\n .O(\\regl_rank_cnt[1]_i_1_n_0 ));\n FDRE \\regl_rank_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\regl_rank_cnt[0]_i_1_n_0 ),\n .Q(regl_rank_cnt[0]),\n .R(\\regl_dqs_cnt[1]_i_1_n_0 ));\n FDRE \\regl_rank_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\regl_rank_cnt[1]_i_1_n_0 ),\n .Q(regl_rank_cnt[1]),\n .R(\\regl_dqs_cnt[1]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\right_edge_taps_r[0]_i_1 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .I1(out[3]),\n .O(\\right_edge_taps_r[0]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\right_edge_taps_r[1]_i_1 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .I1(out[3]),\n .O(\\right_edge_taps_r[1]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\right_edge_taps_r[2]_i_1 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .I1(out[3]),\n .O(\\right_edge_taps_r[2]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\right_edge_taps_r[3]_i_1 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .I1(out[3]),\n .O(\\right_edge_taps_r[3]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\right_edge_taps_r[4]_i_1 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[4] ),\n .I1(out[3]),\n .O(\\right_edge_taps_r[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8888888800002000)) \n \\right_edge_taps_r[5]_i_1 \n (.I0(\\right_edge_taps_r_reg[0]_1 ),\n .I1(out[3]),\n .I2(\\right_edge_taps_r_reg[0]_2 ),\n .I3(found_stable_eye_last_r),\n .I4(\\right_edge_taps_r_reg[0]_0 ),\n .I5(out[2]),\n .O(\\right_edge_taps_r[5]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\right_edge_taps_r[5]_i_2 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[5] ),\n .I1(out[3]),\n .O(\\right_edge_taps_r[5]_i_2_n_0 ));\n FDRE \\right_edge_taps_r_reg[0] \n (.C(CLK),\n .CE(\\right_edge_taps_r[5]_i_1_n_0 ),\n .D(\\right_edge_taps_r[0]_i_1_n_0 ),\n .Q(right_edge_taps_r__0[0]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE \\right_edge_taps_r_reg[1] \n (.C(CLK),\n .CE(\\right_edge_taps_r[5]_i_1_n_0 ),\n .D(\\right_edge_taps_r[1]_i_1_n_0 ),\n .Q(right_edge_taps_r__0[1]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE \\right_edge_taps_r_reg[2] \n (.C(CLK),\n .CE(\\right_edge_taps_r[5]_i_1_n_0 ),\n .D(\\right_edge_taps_r[2]_i_1_n_0 ),\n .Q(right_edge_taps_r__0[2]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE \\right_edge_taps_r_reg[3] \n (.C(CLK),\n .CE(\\right_edge_taps_r[5]_i_1_n_0 ),\n .D(\\right_edge_taps_r[3]_i_1_n_0 ),\n .Q(right_edge_taps_r__0[3]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE \\right_edge_taps_r_reg[4] \n (.C(CLK),\n .CE(\\right_edge_taps_r[5]_i_1_n_0 ),\n .D(\\right_edge_taps_r[4]_i_1_n_0 ),\n .Q(right_edge_taps_r__0[4]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE \\right_edge_taps_r_reg[5] \n (.C(CLK),\n .CE(\\right_edge_taps_r[5]_i_1_n_0 ),\n .D(\\right_edge_taps_r[5]_i_2_n_0 ),\n .Q(right_edge_taps_r__0[5]),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n LUT3 #(\n .INIT(8'h34)) \n \\rnk_cnt_r[0]_i_1__0 \n (.I0(cal1_state_r),\n .I1(\\rnk_cnt_r[1]_i_2_n_0 ),\n .I2(\\rnk_cnt_r_reg_n_0_[0] ),\n .O(\\rnk_cnt_r[0]_i_1__0_n_0 ));\n LUT4 #(\n .INIT(16'h1F20)) \n \\rnk_cnt_r[1]_i_1__0 \n (.I0(\\rnk_cnt_r_reg_n_0_[0] ),\n .I1(cal1_state_r),\n .I2(\\rnk_cnt_r[1]_i_2_n_0 ),\n .I3(\\rnk_cnt_r_reg_n_0_[1] ),\n .O(\\rnk_cnt_r[1]_i_1__0_n_0 ));\n LUT6 #(\n .INIT(64'h00800A0000000000)) \n \\rnk_cnt_r[1]_i_2 \n (.I0(out[1]),\n .I1(\\rnk_cnt_r[1]_i_3_n_0 ),\n .I2(out[3]),\n .I3(cal1_state_r),\n .I4(out[4]),\n .I5(\\cal1_cnt_cpt_r[1]_i_5_n_0 ),\n .O(\\rnk_cnt_r[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hE000000000000000)) \n \\rnk_cnt_r[1]_i_3 \n (.I0(\\rnk_cnt_r_reg_n_0_[1] ),\n .I1(\\rnk_cnt_r_reg_n_0_[0] ),\n .I2(mpr_rdlvl_done_r1_reg_0),\n .I3(\\cal1_cnt_cpt_r_reg_n_0_[1] ),\n .I4(\\cal1_cnt_cpt_r_reg_n_0_[0] ),\n .I5(prech_done),\n .O(\\rnk_cnt_r[1]_i_3_n_0 ));\n FDRE \\rnk_cnt_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rnk_cnt_r[0]_i_1__0_n_0 ),\n .Q(\\rnk_cnt_r_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n FDRE \\rnk_cnt_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rnk_cnt_r[1]_i_1__0_n_0 ),\n .Q(\\rnk_cnt_r_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n LUT6 #(\n .INIT(64'h00000000AAAE0000)) \n samp_cnt_done_r_i_1\n (.I0(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .I1(samp_cnt_done_r_i_2_n_0),\n .I2(samp_cnt_done_r_i_3_n_0),\n .I3(samp_cnt_done_r_i_4_n_0),\n .I4(samp_edge_cnt0_en_r),\n .I5(rstdiv0_sync_r1_reg_rep__23),\n .O(samp_cnt_done_r_i_1_n_0));\n LUT4 #(\n .INIT(16'h0010)) \n samp_cnt_done_r_i_2\n (.I0(samp_edge_cnt1_r_reg[11]),\n .I1(samp_edge_cnt1_r_reg[7]),\n .I2(samp_edge_cnt1_r_reg[0]),\n .I3(samp_edge_cnt1_r_reg[6]),\n .O(samp_cnt_done_r_i_2_n_0));\n LUT4 #(\n .INIT(16'hFFFE)) \n samp_cnt_done_r_i_3\n (.I0(samp_edge_cnt1_r_reg[8]),\n .I1(samp_edge_cnt1_r_reg[3]),\n .I2(samp_edge_cnt1_r_reg[1]),\n .I3(samp_edge_cnt1_r_reg[10]),\n .O(samp_cnt_done_r_i_3_n_0));\n LUT4 #(\n .INIT(16'hFFFE)) \n samp_cnt_done_r_i_4\n (.I0(samp_edge_cnt1_r_reg[4]),\n .I1(samp_edge_cnt1_r_reg[9]),\n .I2(samp_edge_cnt1_r_reg[2]),\n .I3(samp_edge_cnt1_r_reg[5]),\n .O(samp_cnt_done_r_i_4_n_0));\n FDRE samp_cnt_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(samp_cnt_done_r_i_1_n_0),\n .Q(\\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]_0 ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0100000002003000)) \n samp_edge_cnt0_en_r_i_1\n (.I0(out[1]),\n .I1(cal1_state_r),\n .I2(out[4]),\n .I3(out[0]),\n .I4(out[2]),\n .I5(out[3]),\n .O(pb_detect_edge));\n FDRE samp_edge_cnt0_en_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pb_detect_edge),\n .Q(samp_edge_cnt0_en_r),\n .R(1'b0));\n LUT2 #(\n .INIT(4'hE)) \n \\samp_edge_cnt0_r[0]_i_2 \n (.I0(sr_valid_r2),\n .I1(mpr_valid_r2),\n .O(samp_edge_cnt0_r0));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt0_r[0]_i_4 \n (.I0(samp_edge_cnt0_r_reg[3]),\n .O(\\samp_edge_cnt0_r[0]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt0_r[0]_i_5 \n (.I0(samp_edge_cnt0_r_reg[2]),\n .O(\\samp_edge_cnt0_r[0]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt0_r[0]_i_6 \n (.I0(samp_edge_cnt0_r_reg[1]),\n .O(\\samp_edge_cnt0_r[0]_i_6_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\samp_edge_cnt0_r[0]_i_7 \n (.I0(samp_edge_cnt0_r_reg[0]),\n .O(\\samp_edge_cnt0_r[0]_i_7_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt0_r[4]_i_2 \n (.I0(samp_edge_cnt0_r_reg[7]),\n .O(\\samp_edge_cnt0_r[4]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt0_r[4]_i_3 \n (.I0(samp_edge_cnt0_r_reg[6]),\n .O(\\samp_edge_cnt0_r[4]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt0_r[4]_i_4 \n (.I0(samp_edge_cnt0_r_reg[5]),\n .O(\\samp_edge_cnt0_r[4]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt0_r[4]_i_5 \n (.I0(samp_edge_cnt0_r_reg[4]),\n .O(\\samp_edge_cnt0_r[4]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt0_r[8]_i_2 \n (.I0(samp_edge_cnt0_r_reg[11]),\n .O(\\samp_edge_cnt0_r[8]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt0_r[8]_i_3 \n (.I0(samp_edge_cnt0_r_reg[10]),\n .O(\\samp_edge_cnt0_r[8]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt0_r[8]_i_4 \n (.I0(samp_edge_cnt0_r_reg[9]),\n .O(\\samp_edge_cnt0_r[8]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt0_r[8]_i_5 \n (.I0(samp_edge_cnt0_r_reg[8]),\n .O(\\samp_edge_cnt0_r[8]_i_5_n_0 ));\n FDRE \\samp_edge_cnt0_r_reg[0] \n (.C(CLK),\n .CE(samp_edge_cnt0_r0),\n .D(\\samp_edge_cnt0_r_reg[0]_i_3_n_7 ),\n .Q(samp_edge_cnt0_r_reg[0]),\n .R(samp_edge_cnt0_en_r_reg_0));\n CARRY4 \\samp_edge_cnt0_r_reg[0]_i_3 \n (.CI(1'b0),\n .CO({\\samp_edge_cnt0_r_reg[0]_i_3_n_0 ,\\samp_edge_cnt0_r_reg[0]_i_3_n_1 ,\\samp_edge_cnt0_r_reg[0]_i_3_n_2 ,\\samp_edge_cnt0_r_reg[0]_i_3_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b1}),\n .O({\\samp_edge_cnt0_r_reg[0]_i_3_n_4 ,\\samp_edge_cnt0_r_reg[0]_i_3_n_5 ,\\samp_edge_cnt0_r_reg[0]_i_3_n_6 ,\\samp_edge_cnt0_r_reg[0]_i_3_n_7 }),\n .S({\\samp_edge_cnt0_r[0]_i_4_n_0 ,\\samp_edge_cnt0_r[0]_i_5_n_0 ,\\samp_edge_cnt0_r[0]_i_6_n_0 ,\\samp_edge_cnt0_r[0]_i_7_n_0 }));\n FDRE \\samp_edge_cnt0_r_reg[10] \n (.C(CLK),\n .CE(samp_edge_cnt0_r0),\n .D(\\samp_edge_cnt0_r_reg[8]_i_1_n_5 ),\n .Q(samp_edge_cnt0_r_reg[10]),\n .R(samp_edge_cnt0_en_r_reg_0));\n FDRE \\samp_edge_cnt0_r_reg[11] \n (.C(CLK),\n .CE(samp_edge_cnt0_r0),\n .D(\\samp_edge_cnt0_r_reg[8]_i_1_n_4 ),\n .Q(samp_edge_cnt0_r_reg[11]),\n .R(samp_edge_cnt0_en_r_reg_0));\n FDRE \\samp_edge_cnt0_r_reg[1] \n (.C(CLK),\n .CE(samp_edge_cnt0_r0),\n .D(\\samp_edge_cnt0_r_reg[0]_i_3_n_6 ),\n .Q(samp_edge_cnt0_r_reg[1]),\n .R(samp_edge_cnt0_en_r_reg_0));\n FDRE \\samp_edge_cnt0_r_reg[2] \n (.C(CLK),\n .CE(samp_edge_cnt0_r0),\n .D(\\samp_edge_cnt0_r_reg[0]_i_3_n_5 ),\n .Q(samp_edge_cnt0_r_reg[2]),\n .R(samp_edge_cnt0_en_r_reg_0));\n FDRE \\samp_edge_cnt0_r_reg[3] \n (.C(CLK),\n .CE(samp_edge_cnt0_r0),\n .D(\\samp_edge_cnt0_r_reg[0]_i_3_n_4 ),\n .Q(samp_edge_cnt0_r_reg[3]),\n .R(samp_edge_cnt0_en_r_reg_0));\n FDRE \\samp_edge_cnt0_r_reg[4] \n (.C(CLK),\n .CE(samp_edge_cnt0_r0),\n .D(\\samp_edge_cnt0_r_reg[4]_i_1_n_7 ),\n .Q(samp_edge_cnt0_r_reg[4]),\n .R(samp_edge_cnt0_en_r_reg_0));\n CARRY4 \\samp_edge_cnt0_r_reg[4]_i_1 \n (.CI(\\samp_edge_cnt0_r_reg[0]_i_3_n_0 ),\n .CO({\\samp_edge_cnt0_r_reg[4]_i_1_n_0 ,\\samp_edge_cnt0_r_reg[4]_i_1_n_1 ,\\samp_edge_cnt0_r_reg[4]_i_1_n_2 ,\\samp_edge_cnt0_r_reg[4]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\samp_edge_cnt0_r_reg[4]_i_1_n_4 ,\\samp_edge_cnt0_r_reg[4]_i_1_n_5 ,\\samp_edge_cnt0_r_reg[4]_i_1_n_6 ,\\samp_edge_cnt0_r_reg[4]_i_1_n_7 }),\n .S({\\samp_edge_cnt0_r[4]_i_2_n_0 ,\\samp_edge_cnt0_r[4]_i_3_n_0 ,\\samp_edge_cnt0_r[4]_i_4_n_0 ,\\samp_edge_cnt0_r[4]_i_5_n_0 }));\n FDRE \\samp_edge_cnt0_r_reg[5] \n (.C(CLK),\n .CE(samp_edge_cnt0_r0),\n .D(\\samp_edge_cnt0_r_reg[4]_i_1_n_6 ),\n .Q(samp_edge_cnt0_r_reg[5]),\n .R(samp_edge_cnt0_en_r_reg_0));\n FDRE \\samp_edge_cnt0_r_reg[6] \n (.C(CLK),\n .CE(samp_edge_cnt0_r0),\n .D(\\samp_edge_cnt0_r_reg[4]_i_1_n_5 ),\n .Q(samp_edge_cnt0_r_reg[6]),\n .R(samp_edge_cnt0_en_r_reg_0));\n FDRE \\samp_edge_cnt0_r_reg[7] \n (.C(CLK),\n .CE(samp_edge_cnt0_r0),\n .D(\\samp_edge_cnt0_r_reg[4]_i_1_n_4 ),\n .Q(samp_edge_cnt0_r_reg[7]),\n .R(samp_edge_cnt0_en_r_reg_0));\n FDRE \\samp_edge_cnt0_r_reg[8] \n (.C(CLK),\n .CE(samp_edge_cnt0_r0),\n .D(\\samp_edge_cnt0_r_reg[8]_i_1_n_7 ),\n .Q(samp_edge_cnt0_r_reg[8]),\n .R(samp_edge_cnt0_en_r_reg_0));\n CARRY4 \\samp_edge_cnt0_r_reg[8]_i_1 \n (.CI(\\samp_edge_cnt0_r_reg[4]_i_1_n_0 ),\n .CO({\\NLW_samp_edge_cnt0_r_reg[8]_i_1_CO_UNCONNECTED [3],\\samp_edge_cnt0_r_reg[8]_i_1_n_1 ,\\samp_edge_cnt0_r_reg[8]_i_1_n_2 ,\\samp_edge_cnt0_r_reg[8]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\samp_edge_cnt0_r_reg[8]_i_1_n_4 ,\\samp_edge_cnt0_r_reg[8]_i_1_n_5 ,\\samp_edge_cnt0_r_reg[8]_i_1_n_6 ,\\samp_edge_cnt0_r_reg[8]_i_1_n_7 }),\n .S({\\samp_edge_cnt0_r[8]_i_2_n_0 ,\\samp_edge_cnt0_r[8]_i_3_n_0 ,\\samp_edge_cnt0_r[8]_i_4_n_0 ,\\samp_edge_cnt0_r[8]_i_5_n_0 }));\n FDRE \\samp_edge_cnt0_r_reg[9] \n (.C(CLK),\n .CE(samp_edge_cnt0_r0),\n .D(\\samp_edge_cnt0_r_reg[8]_i_1_n_6 ),\n .Q(samp_edge_cnt0_r_reg[9]),\n .R(samp_edge_cnt0_en_r_reg_0));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n samp_edge_cnt1_en_r_i_1\n (.I0(samp_edge_cnt1_en_r_i_2_n_0),\n .I1(samp_edge_cnt1_en_r_i_3_n_0),\n .I2(samp_edge_cnt0_r_reg[8]),\n .I3(samp_edge_cnt0_r_reg[7]),\n .I4(samp_edge_cnt0_r_reg[6]),\n .I5(samp_edge_cnt0_r_reg[2]),\n .O(samp_edge_cnt1_en_r0));\n LUT6 #(\n .INIT(64'h0000000000000E00)) \n samp_edge_cnt1_en_r_i_2\n (.I0(sr_valid_r2),\n .I1(mpr_valid_r2),\n .I2(samp_edge_cnt0_r_reg[3]),\n .I3(samp_edge_cnt0_r_reg[0]),\n .I4(samp_edge_cnt0_r_reg[5]),\n .I5(samp_edge_cnt0_r_reg[1]),\n .O(samp_edge_cnt1_en_r_i_2_n_0));\n LUT4 #(\n .INIT(16'hFFFE)) \n samp_edge_cnt1_en_r_i_3\n (.I0(samp_edge_cnt0_r_reg[11]),\n .I1(samp_edge_cnt0_r_reg[4]),\n .I2(samp_edge_cnt0_r_reg[10]),\n .I3(samp_edge_cnt0_r_reg[9]),\n .O(samp_edge_cnt1_en_r_i_3_n_0));\n FDRE samp_edge_cnt1_en_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(samp_edge_cnt1_en_r0),\n .Q(samp_edge_cnt1_en_r),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt1_r[0]_i_2 \n (.I0(samp_edge_cnt1_r_reg[3]),\n .O(\\samp_edge_cnt1_r[0]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt1_r[0]_i_3 \n (.I0(samp_edge_cnt1_r_reg[2]),\n .O(\\samp_edge_cnt1_r[0]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt1_r[0]_i_4 \n (.I0(samp_edge_cnt1_r_reg[1]),\n .O(\\samp_edge_cnt1_r[0]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\samp_edge_cnt1_r[0]_i_5 \n (.I0(samp_edge_cnt1_r_reg[0]),\n .O(\\samp_edge_cnt1_r[0]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt1_r[4]_i_2 \n (.I0(samp_edge_cnt1_r_reg[7]),\n .O(\\samp_edge_cnt1_r[4]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt1_r[4]_i_3 \n (.I0(samp_edge_cnt1_r_reg[6]),\n .O(\\samp_edge_cnt1_r[4]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt1_r[4]_i_4 \n (.I0(samp_edge_cnt1_r_reg[5]),\n .O(\\samp_edge_cnt1_r[4]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt1_r[4]_i_5 \n (.I0(samp_edge_cnt1_r_reg[4]),\n .O(\\samp_edge_cnt1_r[4]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt1_r[8]_i_2 \n (.I0(samp_edge_cnt1_r_reg[11]),\n .O(\\samp_edge_cnt1_r[8]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt1_r[8]_i_3 \n (.I0(samp_edge_cnt1_r_reg[10]),\n .O(\\samp_edge_cnt1_r[8]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt1_r[8]_i_4 \n (.I0(samp_edge_cnt1_r_reg[9]),\n .O(\\samp_edge_cnt1_r[8]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_edge_cnt1_r[8]_i_5 \n (.I0(samp_edge_cnt1_r_reg[8]),\n .O(\\samp_edge_cnt1_r[8]_i_5_n_0 ));\n FDRE \\samp_edge_cnt1_r_reg[0] \n (.C(CLK),\n .CE(samp_edge_cnt1_en_r),\n .D(\\samp_edge_cnt1_r_reg[0]_i_1_n_7 ),\n .Q(samp_edge_cnt1_r_reg[0]),\n .R(samp_edge_cnt0_en_r_reg_0));\n CARRY4 \\samp_edge_cnt1_r_reg[0]_i_1 \n (.CI(1'b0),\n .CO({\\samp_edge_cnt1_r_reg[0]_i_1_n_0 ,\\samp_edge_cnt1_r_reg[0]_i_1_n_1 ,\\samp_edge_cnt1_r_reg[0]_i_1_n_2 ,\\samp_edge_cnt1_r_reg[0]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b1}),\n .O({\\samp_edge_cnt1_r_reg[0]_i_1_n_4 ,\\samp_edge_cnt1_r_reg[0]_i_1_n_5 ,\\samp_edge_cnt1_r_reg[0]_i_1_n_6 ,\\samp_edge_cnt1_r_reg[0]_i_1_n_7 }),\n .S({\\samp_edge_cnt1_r[0]_i_2_n_0 ,\\samp_edge_cnt1_r[0]_i_3_n_0 ,\\samp_edge_cnt1_r[0]_i_4_n_0 ,\\samp_edge_cnt1_r[0]_i_5_n_0 }));\n FDRE \\samp_edge_cnt1_r_reg[10] \n (.C(CLK),\n .CE(samp_edge_cnt1_en_r),\n .D(\\samp_edge_cnt1_r_reg[8]_i_1_n_5 ),\n .Q(samp_edge_cnt1_r_reg[10]),\n .R(samp_edge_cnt0_en_r_reg_0));\n FDRE \\samp_edge_cnt1_r_reg[11] \n (.C(CLK),\n .CE(samp_edge_cnt1_en_r),\n .D(\\samp_edge_cnt1_r_reg[8]_i_1_n_4 ),\n .Q(samp_edge_cnt1_r_reg[11]),\n .R(samp_edge_cnt0_en_r_reg_0));\n FDRE \\samp_edge_cnt1_r_reg[1] \n (.C(CLK),\n .CE(samp_edge_cnt1_en_r),\n .D(\\samp_edge_cnt1_r_reg[0]_i_1_n_6 ),\n .Q(samp_edge_cnt1_r_reg[1]),\n .R(samp_edge_cnt0_en_r_reg_0));\n FDRE \\samp_edge_cnt1_r_reg[2] \n (.C(CLK),\n .CE(samp_edge_cnt1_en_r),\n .D(\\samp_edge_cnt1_r_reg[0]_i_1_n_5 ),\n .Q(samp_edge_cnt1_r_reg[2]),\n .R(samp_edge_cnt0_en_r_reg_0));\n FDRE \\samp_edge_cnt1_r_reg[3] \n (.C(CLK),\n .CE(samp_edge_cnt1_en_r),\n .D(\\samp_edge_cnt1_r_reg[0]_i_1_n_4 ),\n .Q(samp_edge_cnt1_r_reg[3]),\n .R(samp_edge_cnt0_en_r_reg_0));\n FDRE \\samp_edge_cnt1_r_reg[4] \n (.C(CLK),\n .CE(samp_edge_cnt1_en_r),\n .D(\\samp_edge_cnt1_r_reg[4]_i_1_n_7 ),\n .Q(samp_edge_cnt1_r_reg[4]),\n .R(samp_edge_cnt0_en_r_reg_0));\n CARRY4 \\samp_edge_cnt1_r_reg[4]_i_1 \n (.CI(\\samp_edge_cnt1_r_reg[0]_i_1_n_0 ),\n .CO({\\samp_edge_cnt1_r_reg[4]_i_1_n_0 ,\\samp_edge_cnt1_r_reg[4]_i_1_n_1 ,\\samp_edge_cnt1_r_reg[4]_i_1_n_2 ,\\samp_edge_cnt1_r_reg[4]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\samp_edge_cnt1_r_reg[4]_i_1_n_4 ,\\samp_edge_cnt1_r_reg[4]_i_1_n_5 ,\\samp_edge_cnt1_r_reg[4]_i_1_n_6 ,\\samp_edge_cnt1_r_reg[4]_i_1_n_7 }),\n .S({\\samp_edge_cnt1_r[4]_i_2_n_0 ,\\samp_edge_cnt1_r[4]_i_3_n_0 ,\\samp_edge_cnt1_r[4]_i_4_n_0 ,\\samp_edge_cnt1_r[4]_i_5_n_0 }));\n FDRE \\samp_edge_cnt1_r_reg[5] \n (.C(CLK),\n .CE(samp_edge_cnt1_en_r),\n .D(\\samp_edge_cnt1_r_reg[4]_i_1_n_6 ),\n .Q(samp_edge_cnt1_r_reg[5]),\n .R(samp_edge_cnt0_en_r_reg_0));\n FDRE \\samp_edge_cnt1_r_reg[6] \n (.C(CLK),\n .CE(samp_edge_cnt1_en_r),\n .D(\\samp_edge_cnt1_r_reg[4]_i_1_n_5 ),\n .Q(samp_edge_cnt1_r_reg[6]),\n .R(samp_edge_cnt0_en_r_reg_0));\n FDRE \\samp_edge_cnt1_r_reg[7] \n (.C(CLK),\n .CE(samp_edge_cnt1_en_r),\n .D(\\samp_edge_cnt1_r_reg[4]_i_1_n_4 ),\n .Q(samp_edge_cnt1_r_reg[7]),\n .R(samp_edge_cnt0_en_r_reg_0));\n FDRE \\samp_edge_cnt1_r_reg[8] \n (.C(CLK),\n .CE(samp_edge_cnt1_en_r),\n .D(\\samp_edge_cnt1_r_reg[8]_i_1_n_7 ),\n .Q(samp_edge_cnt1_r_reg[8]),\n .R(samp_edge_cnt0_en_r_reg_0));\n CARRY4 \\samp_edge_cnt1_r_reg[8]_i_1 \n (.CI(\\samp_edge_cnt1_r_reg[4]_i_1_n_0 ),\n .CO({\\NLW_samp_edge_cnt1_r_reg[8]_i_1_CO_UNCONNECTED [3],\\samp_edge_cnt1_r_reg[8]_i_1_n_1 ,\\samp_edge_cnt1_r_reg[8]_i_1_n_2 ,\\samp_edge_cnt1_r_reg[8]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\samp_edge_cnt1_r_reg[8]_i_1_n_4 ,\\samp_edge_cnt1_r_reg[8]_i_1_n_5 ,\\samp_edge_cnt1_r_reg[8]_i_1_n_6 ,\\samp_edge_cnt1_r_reg[8]_i_1_n_7 }),\n .S({\\samp_edge_cnt1_r[8]_i_2_n_0 ,\\samp_edge_cnt1_r[8]_i_3_n_0 ,\\samp_edge_cnt1_r[8]_i_4_n_0 ,\\samp_edge_cnt1_r[8]_i_5_n_0 }));\n FDRE \\samp_edge_cnt1_r_reg[9] \n (.C(CLK),\n .CE(samp_edge_cnt1_en_r),\n .D(\\samp_edge_cnt1_r_reg[8]_i_1_n_6 ),\n .Q(samp_edge_cnt1_r_reg[9]),\n .R(samp_edge_cnt0_en_r_reg_0));\n LUT1 #(\n .INIT(2'h1)) \n \\second_edge_taps_r[0]_i_1 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .O(\\second_edge_taps_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair230\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\second_edge_taps_r[1]_i_1 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .I1(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .O(\\second_edge_taps_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair230\" *) \n LUT3 #(\n .INIT(8'hA9)) \n \\second_edge_taps_r[2]_i_1 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .I1(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .O(\\second_edge_taps_r[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair189\" *) \n LUT4 #(\n .INIT(16'hAAA9)) \n \\second_edge_taps_r[3]_i_1 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .I1(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .I3(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .O(\\second_edge_taps_r[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair189\" *) \n LUT5 #(\n .INIT(32'hAAAAAAA9)) \n \\second_edge_taps_r[4]_i_1 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[4] ),\n .I1(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .I3(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .I4(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .O(\\second_edge_taps_r[4]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\second_edge_taps_r[5]_i_1 \n (.I0(out[3]),\n .I1(\\second_edge_taps_r_reg[5]_0 ),\n .O(\\second_edge_taps_r[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8888888820000000)) \n \\second_edge_taps_r[5]_i_2 \n (.I0(\\right_edge_taps_r_reg[0]_1 ),\n .I1(out[3]),\n .I2(\\right_edge_taps_r_reg[0]_2 ),\n .I3(found_stable_eye_last_r),\n .I4(\\right_edge_taps_r_reg[0]_0 ),\n .I5(out[2]),\n .O(\\second_edge_taps_r_reg[5]_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAAAAA9)) \n \\second_edge_taps_r[5]_i_3 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[5] ),\n .I1(\\tap_cnt_cpt_r_reg_n_0_[4] ),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .I3(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .I4(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .I5(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .O(\\second_edge_taps_r[5]_i_3_n_0 ));\n FDRE \\second_edge_taps_r_reg[0] \n (.C(CLK),\n .CE(\\second_edge_taps_r_reg[5]_0 ),\n .D(\\second_edge_taps_r[0]_i_1_n_0 ),\n .Q(\\second_edge_taps_r_reg_n_0_[0] ),\n .R(\\second_edge_taps_r[5]_i_1_n_0 ));\n FDRE \\second_edge_taps_r_reg[1] \n (.C(CLK),\n .CE(\\second_edge_taps_r_reg[5]_0 ),\n .D(\\second_edge_taps_r[1]_i_1_n_0 ),\n .Q(\\second_edge_taps_r_reg_n_0_[1] ),\n .R(\\second_edge_taps_r[5]_i_1_n_0 ));\n FDRE \\second_edge_taps_r_reg[2] \n (.C(CLK),\n .CE(\\second_edge_taps_r_reg[5]_0 ),\n .D(\\second_edge_taps_r[2]_i_1_n_0 ),\n .Q(\\second_edge_taps_r_reg_n_0_[2] ),\n .R(\\second_edge_taps_r[5]_i_1_n_0 ));\n FDRE \\second_edge_taps_r_reg[3] \n (.C(CLK),\n .CE(\\second_edge_taps_r_reg[5]_0 ),\n .D(\\second_edge_taps_r[3]_i_1_n_0 ),\n .Q(\\second_edge_taps_r_reg_n_0_[3] ),\n .R(\\second_edge_taps_r[5]_i_1_n_0 ));\n FDRE \\second_edge_taps_r_reg[4] \n (.C(CLK),\n .CE(\\second_edge_taps_r_reg[5]_0 ),\n .D(\\second_edge_taps_r[4]_i_1_n_0 ),\n .Q(\\second_edge_taps_r_reg_n_0_[4] ),\n .R(\\second_edge_taps_r[5]_i_1_n_0 ));\n FDRE \\second_edge_taps_r_reg[5] \n (.C(CLK),\n .CE(\\second_edge_taps_r_reg[5]_0 ),\n .D(\\second_edge_taps_r[5]_i_3_n_0 ),\n .Q(\\second_edge_taps_r_reg_n_0_[5] ),\n .R(\\second_edge_taps_r[5]_i_1_n_0 ));\n FDRE sr_valid_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(sr_valid_r1_reg_0),\n .Q(sr_valid_r1),\n .R(1'b0));\n FDRE sr_valid_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(sr_valid_r1),\n .Q(sr_valid_r2),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair199\" *) \n LUT4 #(\n .INIT(16'hFFFE)) \n sr_valid_r_i_2\n (.I0(cnt_shift_r_reg__0[0]),\n .I1(cnt_shift_r_reg__0[1]),\n .I2(cnt_shift_r_reg__0[3]),\n .I3(cnt_shift_r_reg__0[2]),\n .O(mpr_valid_r_reg_0));\n FDRE sr_valid_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(sr_valid_r108_out),\n .Q(sr_valid_r1_reg_0),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair225\" *) \n LUT3 #(\n .INIT(8'h45)) \n \\stg1_wr_rd_cnt[4]_i_2 \n (.I0(rstdiv0_sync_r1_reg_rep__24),\n .I1(rdlvl_stg1_done_r1_reg),\n .I2(stg1_wr_done),\n .O(\\stg1_wr_rd_cnt_reg[3] ));\n FDRE store_sr_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(store_sr_req_r_reg_1),\n .Q(\\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0]_0 ),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n LUT6 #(\n .INIT(64'h0000100000000000)) \n store_sr_req_pulsed_r_i_1\n (.I0(cal1_state_r),\n .I1(out[2]),\n .I2(out[1]),\n .I3(out[0]),\n .I4(out[3]),\n .I5(out[4]),\n .O(store_sr_req_pulsed_r));\n FDRE store_sr_req_pulsed_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(store_sr_req_pulsed_r),\n .Q(store_sr_req_pulsed_r_reg_n_0),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n LUT6 #(\n .INIT(64'h0000000288880002)) \n store_sr_req_r_i_1\n (.I0(store_sr_req_r_i_2_n_0),\n .I1(out[4]),\n .I2(cal1_wait_r),\n .I3(store_sr_req_r_reg_0),\n .I4(out[0]),\n .I5(store_sr_req_pulsed_r_reg_n_0),\n .O(store_sr_req_r));\n LUT4 #(\n .INIT(16'h0010)) \n store_sr_req_r_i_2\n (.I0(cal1_state_r),\n .I1(out[3]),\n .I2(out[1]),\n .I3(out[2]),\n .O(store_sr_req_r_i_2_n_0));\n FDRE store_sr_req_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(store_sr_req_r),\n .Q(store_sr_r_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__14[1]));\n (* SOFT_HLUTNM = \"soft_lutpair208\" *) \n LUT3 #(\n .INIT(8'h69)) \n \\tap_cnt_cpt_r[1]_i_1 \n (.I0(cal1_dlyinc_cpt_r_reg_n_0),\n .I1(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .O(\\tap_cnt_cpt_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair190\" *) \n LUT4 #(\n .INIT(16'h6CC9)) \n \\tap_cnt_cpt_r[2]_i_1 \n (.I0(cal1_dlyinc_cpt_r_reg_n_0),\n .I1(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .I3(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .O(p_0_in__0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair190\" *) \n LUT5 #(\n .INIT(32'h6CCCCCC9)) \n \\tap_cnt_cpt_r[3]_i_1 \n (.I0(cal1_dlyinc_cpt_r_reg_n_0),\n .I1(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .I3(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .I4(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .O(p_0_in__0[3]));\n LUT6 #(\n .INIT(64'h6CCCCCCCCCCCCCC9)) \n \\tap_cnt_cpt_r[4]_i_1 \n (.I0(cal1_dlyinc_cpt_r_reg_n_0),\n .I1(\\tap_cnt_cpt_r_reg_n_0_[4] ),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .I3(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .I4(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .I5(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .O(p_0_in__0[4]));\n LUT4 #(\n .INIT(16'hFFF4)) \n \\tap_cnt_cpt_r[5]_i_1 \n (.I0(mpr_rdlvl_done_r2),\n .I1(mpr_rdlvl_done_r1),\n .I2(new_cnt_cpt_r_reg_n_0),\n .I3(rstdiv0_sync_r1_reg_rep__23),\n .O(tap_cnt_cpt_r0));\n LUT4 #(\n .INIT(16'hAA8A)) \n \\tap_cnt_cpt_r[5]_i_2 \n (.I0(cal1_dlyce_cpt_r_reg_n_0),\n .I1(\\tap_cnt_cpt_r_reg_n_0_[5] ),\n .I2(\\tap_cnt_cpt_r[5]_i_4_n_0 ),\n .I3(cal1_dlyinc_cpt_r_reg_n_0),\n .O(tap_cnt_cpt_r));\n LUT4 #(\n .INIT(16'h6F60)) \n \\tap_cnt_cpt_r[5]_i_3 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[5] ),\n .I1(tap_limit_cpt_r_i_2_n_0),\n .I2(cal1_dlyinc_cpt_r_reg_n_0),\n .I3(\\second_edge_taps_r[5]_i_3_n_0 ),\n .O(p_0_in__0[5]));\n (* SOFT_HLUTNM = \"soft_lutpair91\" *) \n LUT5 #(\n .INIT(32'h00000001)) \n \\tap_cnt_cpt_r[5]_i_4 \n (.I0(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .I1(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .I3(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .I4(\\tap_cnt_cpt_r_reg_n_0_[4] ),\n .O(\\tap_cnt_cpt_r[5]_i_4_n_0 ));\n FDRE \\tap_cnt_cpt_r_reg[0] \n (.C(CLK),\n .CE(tap_cnt_cpt_r),\n .D(\\second_edge_taps_r[0]_i_1_n_0 ),\n .Q(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .R(tap_cnt_cpt_r0));\n FDRE \\tap_cnt_cpt_r_reg[1] \n (.C(CLK),\n .CE(tap_cnt_cpt_r),\n .D(\\tap_cnt_cpt_r[1]_i_1_n_0 ),\n .Q(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .R(tap_cnt_cpt_r0));\n FDRE \\tap_cnt_cpt_r_reg[2] \n (.C(CLK),\n .CE(tap_cnt_cpt_r),\n .D(p_0_in__0[2]),\n .Q(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .R(tap_cnt_cpt_r0));\n FDRE \\tap_cnt_cpt_r_reg[3] \n (.C(CLK),\n .CE(tap_cnt_cpt_r),\n .D(p_0_in__0[3]),\n .Q(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .R(tap_cnt_cpt_r0));\n FDRE \\tap_cnt_cpt_r_reg[4] \n (.C(CLK),\n .CE(tap_cnt_cpt_r),\n .D(p_0_in__0[4]),\n .Q(\\tap_cnt_cpt_r_reg_n_0_[4] ),\n .R(tap_cnt_cpt_r0));\n FDRE \\tap_cnt_cpt_r_reg[5] \n (.C(CLK),\n .CE(tap_cnt_cpt_r),\n .D(p_0_in__0[5]),\n .Q(\\tap_cnt_cpt_r_reg_n_0_[5] ),\n .R(tap_cnt_cpt_r0));\n LUT5 #(\n .INIT(32'h000000EA)) \n tap_limit_cpt_r_i_1\n (.I0(tap_limit_cpt_r),\n .I1(tap_limit_cpt_r_i_2_n_0),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[5] ),\n .I3(tap_limit_cpt_r_i_3_n_0),\n .I4(tap_cnt_cpt_r0),\n .O(tap_limit_cpt_r_i_1_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair91\" *) \n LUT5 #(\n .INIT(32'h80000000)) \n tap_limit_cpt_r_i_2\n (.I0(\\tap_cnt_cpt_r_reg_n_0_[3] ),\n .I1(\\tap_cnt_cpt_r_reg_n_0_[1] ),\n .I2(\\tap_cnt_cpt_r_reg_n_0_[0] ),\n .I3(\\tap_cnt_cpt_r_reg_n_0_[2] ),\n .I4(\\tap_cnt_cpt_r_reg_n_0_[4] ),\n .O(tap_limit_cpt_r_i_2_n_0));\n LUT6 #(\n .INIT(64'h0000000000000010)) \n tap_limit_cpt_r_i_3\n (.I0(\\cal1_state_r1_reg_n_0_[5] ),\n .I1(\\cal1_state_r1_reg_n_0_[4] ),\n .I2(\\cal1_state_r1_reg_n_0_[2] ),\n .I3(\\cal1_state_r1_reg_n_0_[0] ),\n .I4(\\cal1_state_r1_reg_n_0_[3] ),\n .I5(\\cal1_state_r1_reg_n_0_[1] ),\n .O(tap_limit_cpt_r_i_3_n_0));\n FDRE tap_limit_cpt_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(tap_limit_cpt_r_i_1_n_0),\n .Q(tap_limit_cpt_r),\n .R(1'b0));\n LUT1 #(\n .INIT(2'h1)) \n \\wait_cnt_r[0]_i_1__1 \n (.I0(\\wait_cnt_r_reg[0]_0 [0]),\n .O(wait_cnt_r0__0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair236\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\wait_cnt_r[1]_i_1__1 \n (.I0(\\wait_cnt_r_reg[0]_0 [1]),\n .I1(\\wait_cnt_r_reg[0]_0 [0]),\n .O(\\wait_cnt_r[1]_i_1__1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair236\" *) \n LUT3 #(\n .INIT(8'hA9)) \n \\wait_cnt_r[2]_i_1__0 \n (.I0(wait_cnt_r_reg__0[2]),\n .I1(\\wait_cnt_r_reg[0]_0 [0]),\n .I2(\\wait_cnt_r_reg[0]_0 [1]),\n .O(wait_cnt_r0__0[2]));\n LUT5 #(\n .INIT(32'hAAAAAAA8)) \n \\wait_cnt_r[3]_i_2__1 \n (.I0(dqs_po_dec_done_r2),\n .I1(wait_cnt_r_reg__0[2]),\n .I2(wait_cnt_r_reg__0[3]),\n .I3(\\wait_cnt_r_reg[0]_0 [1]),\n .I4(\\wait_cnt_r_reg[0]_0 [0]),\n .O(wait_cnt_r0));\n (* SOFT_HLUTNM = \"soft_lutpair209\" *) \n LUT4 #(\n .INIT(16'hAAA9)) \n \\wait_cnt_r[3]_i_3 \n (.I0(wait_cnt_r_reg__0[3]),\n .I1(wait_cnt_r_reg__0[2]),\n .I2(\\wait_cnt_r_reg[0]_0 [1]),\n .I3(\\wait_cnt_r_reg[0]_0 [0]),\n .O(wait_cnt_r0__0[3]));\n FDRE \\wait_cnt_r_reg[0] \n (.C(CLK),\n .CE(wait_cnt_r0),\n .D(wait_cnt_r0__0[0]),\n .Q(\\wait_cnt_r_reg[0]_0 [0]),\n .R(pi_cnt_dec_reg_1));\n FDRE \\wait_cnt_r_reg[1] \n (.C(CLK),\n .CE(wait_cnt_r0),\n .D(\\wait_cnt_r[1]_i_1__1_n_0 ),\n .Q(\\wait_cnt_r_reg[0]_0 [1]),\n .R(pi_cnt_dec_reg_1));\n FDRE \\wait_cnt_r_reg[2] \n (.C(CLK),\n .CE(wait_cnt_r0),\n .D(wait_cnt_r0__0[2]),\n .Q(wait_cnt_r_reg__0[2]),\n .R(pi_cnt_dec_reg_1));\n FDSE \\wait_cnt_r_reg[3] \n (.C(CLK),\n .CE(wait_cnt_r0),\n .D(wait_cnt_r0__0[3]),\n .Q(wait_cnt_r_reg__0[3]),\n .S(pi_cnt_dec_reg_1));\n (* SOFT_HLUTNM = \"soft_lutpair198\" *) \n LUT4 #(\n .INIT(16'h7FFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[254]_i_1 \n (.I0(rdlvl_stg1_done_r1_reg),\n .I1(prbs_rdlvl_done_reg_rep),\n .I2(oclkdelay_calib_done_r_reg),\n .I3(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[254] ));\n LUT5 #(\n .INIT(32'hDFDF0FFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[56]_i_1 \n (.I0(rdlvl_stg1_done_r1_reg),\n .I1(\\dout_o_reg[6]_0 ),\n .I2(oclkdelay_calib_done_r_reg),\n .I3(first_wrcal_pat_r),\n .I4(wrcal_done_reg),\n .O(D[0]));\n LUT5 #(\n .INIT(32'hDFDF0FFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[60]_i_1 \n (.I0(rdlvl_stg1_done_r1_reg),\n .I1(\\dout_o_reg[6] ),\n .I2(oclkdelay_calib_done_r_reg),\n .I3(first_wrcal_pat_r),\n .I4(wrcal_done_reg),\n .O(D[1]));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_ddr_phy_tempmon\n (tempmon_pi_f_inc,\n tempmon_sel_pi_incdec,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ,\n D,\n \\calib_zero_inputs_reg[1] ,\n \\calib_zero_inputs_reg[1]_0 ,\n \\gen_byte_sel_div1.calib_in_common_reg ,\n CLK,\n SS,\n tempmon_sample_en,\n rstdiv0_sync_r1_reg_rep__2,\n rstdiv0_sync_r1_reg_rep__7,\n oclkdelay_calib_done_r_reg,\n ck_addr_cmd_delay_done,\n ctl_lane_sel,\n rstdiv0_sync_r1_reg_rep__25,\n calib_complete,\n cmd_delay_start0,\n delay_done_r4_reg,\n calib_in_common,\n fine_adjust_done_r_reg,\n rd_data_offset_cal_done,\n rstdiv0_sync_r1_reg_rep__5,\n \\device_temp_r_reg[11] ,\n rstdiv0_sync_r1_reg_rep__4,\n rstdiv0_sync_r1_reg_rep__6);\n output tempmon_pi_f_inc;\n output tempmon_sel_pi_incdec;\n output \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ;\n output [0:0]D;\n output [0:0]\\calib_zero_inputs_reg[1] ;\n output \\calib_zero_inputs_reg[1]_0 ;\n output \\gen_byte_sel_div1.calib_in_common_reg ;\n input CLK;\n input [0:0]SS;\n input tempmon_sample_en;\n input rstdiv0_sync_r1_reg_rep__2;\n input rstdiv0_sync_r1_reg_rep__7;\n input oclkdelay_calib_done_r_reg;\n input ck_addr_cmd_delay_done;\n input ctl_lane_sel;\n input rstdiv0_sync_r1_reg_rep__25;\n input calib_complete;\n input cmd_delay_start0;\n input delay_done_r4_reg;\n input calib_in_common;\n input fine_adjust_done_r_reg;\n input rd_data_offset_cal_done;\n input [0:0]rstdiv0_sync_r1_reg_rep__5;\n input [11:0]\\device_temp_r_reg[11] ;\n input rstdiv0_sync_r1_reg_rep__4;\n input rstdiv0_sync_r1_reg_rep__6;\n\n wire CLK;\n wire [0:0]D;\n wire [0:0]SS;\n wire calib_complete;\n wire calib_in_common;\n wire [0:0]\\calib_zero_inputs_reg[1] ;\n wire \\calib_zero_inputs_reg[1]_0 ;\n wire ck_addr_cmd_delay_done;\n wire cmd_delay_start0;\n wire ctl_lane_sel;\n wire delay_done_r4_reg;\n wire [11:0]device_temp_101;\n wire [11:0]device_temp_init;\n wire \\device_temp_init[11]_i_2_n_0 ;\n wire \\device_temp_init[11]_i_3_n_0 ;\n wire [11:0]\\device_temp_r_reg[11] ;\n wire fine_adjust_done_r_reg;\n wire [11:0]four_dec_min_limit;\n wire \\four_dec_min_limit[11]_i_2_n_0 ;\n wire \\four_dec_min_limit[11]_i_3_n_0 ;\n wire \\four_dec_min_limit[5]_i_2_n_0 ;\n wire \\four_dec_min_limit[5]_i_3_n_0 ;\n wire \\four_dec_min_limit[5]_i_4_n_0 ;\n wire \\four_dec_min_limit[5]_i_5_n_0 ;\n wire \\four_dec_min_limit[9]_i_2_n_0 ;\n wire \\four_dec_min_limit[9]_i_3_n_0 ;\n wire \\four_dec_min_limit[9]_i_4_n_0 ;\n wire \\four_dec_min_limit[9]_i_5_n_0 ;\n wire [11:2]four_dec_min_limit_nxt;\n wire \\four_dec_min_limit_reg[11]_i_1_n_3 ;\n wire \\four_dec_min_limit_reg[5]_i_1_n_0 ;\n wire \\four_dec_min_limit_reg[5]_i_1_n_1 ;\n wire \\four_dec_min_limit_reg[5]_i_1_n_2 ;\n wire \\four_dec_min_limit_reg[5]_i_1_n_3 ;\n wire \\four_dec_min_limit_reg[9]_i_1_n_0 ;\n wire \\four_dec_min_limit_reg[9]_i_1_n_1 ;\n wire \\four_dec_min_limit_reg[9]_i_1_n_2 ;\n wire \\four_dec_min_limit_reg[9]_i_1_n_3 ;\n wire [11:1]four_inc_max_limit;\n wire \\four_inc_max_limit[11]_i_2_n_0 ;\n wire \\four_inc_max_limit[11]_i_3_n_0 ;\n wire \\four_inc_max_limit[11]_i_4_n_0 ;\n wire \\four_inc_max_limit[1]_i_2_n_0 ;\n wire \\four_inc_max_limit[4]_i_2_n_0 ;\n wire \\four_inc_max_limit[4]_i_3_n_0 ;\n wire \\four_inc_max_limit[4]_i_4_n_0 ;\n wire \\four_inc_max_limit[4]_i_5_n_0 ;\n wire \\four_inc_max_limit[8]_i_2_n_0 ;\n wire \\four_inc_max_limit[8]_i_3_n_0 ;\n wire \\four_inc_max_limit[8]_i_4_n_0 ;\n wire \\four_inc_max_limit[8]_i_5_n_0 ;\n wire [11:1]four_inc_max_limit_nxt;\n wire \\four_inc_max_limit_reg[11]_i_1_n_2 ;\n wire \\four_inc_max_limit_reg[11]_i_1_n_3 ;\n wire \\four_inc_max_limit_reg[4]_i_1_n_0 ;\n wire \\four_inc_max_limit_reg[4]_i_1_n_1 ;\n wire \\four_inc_max_limit_reg[4]_i_1_n_2 ;\n wire \\four_inc_max_limit_reg[4]_i_1_n_3 ;\n wire \\four_inc_max_limit_reg[8]_i_1_n_0 ;\n wire \\four_inc_max_limit_reg[8]_i_1_n_1 ;\n wire \\four_inc_max_limit_reg[8]_i_1_n_2 ;\n wire \\four_inc_max_limit_reg[8]_i_1_n_3 ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ;\n wire \\gen_byte_sel_div1.calib_in_common_reg ;\n wire [11:1]neutral_max_limit;\n wire \\neutral_max_limit[11]_i_2_n_0 ;\n wire \\neutral_max_limit[11]_i_3_n_0 ;\n wire \\neutral_max_limit[11]_i_4_n_0 ;\n wire \\neutral_max_limit[4]_i_2_n_0 ;\n wire \\neutral_max_limit[4]_i_3_n_0 ;\n wire \\neutral_max_limit[4]_i_4_n_0 ;\n wire \\neutral_max_limit[4]_i_5_n_0 ;\n wire \\neutral_max_limit[8]_i_2_n_0 ;\n wire \\neutral_max_limit[8]_i_3_n_0 ;\n wire \\neutral_max_limit[8]_i_4_n_0 ;\n wire \\neutral_max_limit[8]_i_5_n_0 ;\n wire [11:1]neutral_max_limit_nxt;\n wire \\neutral_max_limit_reg[11]_i_1_n_2 ;\n wire \\neutral_max_limit_reg[11]_i_1_n_3 ;\n wire \\neutral_max_limit_reg[4]_i_1_n_0 ;\n wire \\neutral_max_limit_reg[4]_i_1_n_1 ;\n wire \\neutral_max_limit_reg[4]_i_1_n_2 ;\n wire \\neutral_max_limit_reg[4]_i_1_n_3 ;\n wire \\neutral_max_limit_reg[8]_i_1_n_0 ;\n wire \\neutral_max_limit_reg[8]_i_1_n_1 ;\n wire \\neutral_max_limit_reg[8]_i_1_n_2 ;\n wire \\neutral_max_limit_reg[8]_i_1_n_3 ;\n wire [11:1]neutral_min_limit;\n wire \\neutral_min_limit[11]_i_2_n_0 ;\n wire \\neutral_min_limit[11]_i_3_n_0 ;\n wire \\neutral_min_limit[5]_i_2_n_0 ;\n wire \\neutral_min_limit[5]_i_3_n_0 ;\n wire \\neutral_min_limit[5]_i_4_n_0 ;\n wire \\neutral_min_limit[5]_i_5_n_0 ;\n wire \\neutral_min_limit[9]_i_2_n_0 ;\n wire \\neutral_min_limit[9]_i_3_n_0 ;\n wire \\neutral_min_limit[9]_i_4_n_0 ;\n wire \\neutral_min_limit[9]_i_5_n_0 ;\n wire [11:2]neutral_min_limit_nxt;\n wire \\neutral_min_limit_reg[11]_i_1_n_3 ;\n wire \\neutral_min_limit_reg[5]_i_1_n_0 ;\n wire \\neutral_min_limit_reg[5]_i_1_n_1 ;\n wire \\neutral_min_limit_reg[5]_i_1_n_2 ;\n wire \\neutral_min_limit_reg[5]_i_1_n_3 ;\n wire \\neutral_min_limit_reg[9]_i_1_n_0 ;\n wire \\neutral_min_limit_reg[9]_i_1_n_1 ;\n wire \\neutral_min_limit_reg[9]_i_1_n_2 ;\n wire \\neutral_min_limit_reg[9]_i_1_n_3 ;\n wire oclkdelay_calib_done_r_reg;\n wire [11:1]one_dec_max_limit;\n wire \\one_dec_max_limit[11]_i_2_n_0 ;\n wire \\one_dec_max_limit[11]_i_3_n_0 ;\n wire \\one_dec_max_limit[11]_i_4_n_0 ;\n wire \\one_dec_max_limit[4]_i_2_n_0 ;\n wire \\one_dec_max_limit[4]_i_3_n_0 ;\n wire \\one_dec_max_limit[4]_i_4_n_0 ;\n wire \\one_dec_max_limit[4]_i_5_n_0 ;\n wire \\one_dec_max_limit[8]_i_2_n_0 ;\n wire \\one_dec_max_limit[8]_i_3_n_0 ;\n wire \\one_dec_max_limit[8]_i_4_n_0 ;\n wire \\one_dec_max_limit[8]_i_5_n_0 ;\n wire [11:1]one_dec_max_limit_nxt;\n wire \\one_dec_max_limit_reg[11]_i_1_n_2 ;\n wire \\one_dec_max_limit_reg[11]_i_1_n_3 ;\n wire \\one_dec_max_limit_reg[4]_i_1_n_0 ;\n wire \\one_dec_max_limit_reg[4]_i_1_n_1 ;\n wire \\one_dec_max_limit_reg[4]_i_1_n_2 ;\n wire \\one_dec_max_limit_reg[4]_i_1_n_3 ;\n wire \\one_dec_max_limit_reg[8]_i_1_n_0 ;\n wire \\one_dec_max_limit_reg[8]_i_1_n_1 ;\n wire \\one_dec_max_limit_reg[8]_i_1_n_2 ;\n wire \\one_dec_max_limit_reg[8]_i_1_n_3 ;\n wire [11:1]one_dec_min_limit;\n wire \\one_dec_min_limit[11]_i_2_n_0 ;\n wire \\one_dec_min_limit[11]_i_3_n_0 ;\n wire \\one_dec_min_limit[5]_i_2_n_0 ;\n wire \\one_dec_min_limit[5]_i_3_n_0 ;\n wire \\one_dec_min_limit[5]_i_4_n_0 ;\n wire \\one_dec_min_limit[5]_i_5_n_0 ;\n wire \\one_dec_min_limit[9]_i_2_n_0 ;\n wire \\one_dec_min_limit[9]_i_3_n_0 ;\n wire \\one_dec_min_limit[9]_i_4_n_0 ;\n wire \\one_dec_min_limit[9]_i_5_n_0 ;\n wire [11:2]one_dec_min_limit_nxt;\n wire \\one_dec_min_limit_reg[11]_i_1_n_3 ;\n wire \\one_dec_min_limit_reg[5]_i_1_n_0 ;\n wire \\one_dec_min_limit_reg[5]_i_1_n_1 ;\n wire \\one_dec_min_limit_reg[5]_i_1_n_2 ;\n wire \\one_dec_min_limit_reg[5]_i_1_n_3 ;\n wire \\one_dec_min_limit_reg[9]_i_1_n_0 ;\n wire \\one_dec_min_limit_reg[9]_i_1_n_1 ;\n wire \\one_dec_min_limit_reg[9]_i_1_n_2 ;\n wire \\one_dec_min_limit_reg[9]_i_1_n_3 ;\n wire [11:1]one_inc_max_limit;\n wire \\one_inc_max_limit[11]_i_2_n_0 ;\n wire \\one_inc_max_limit[11]_i_3_n_0 ;\n wire \\one_inc_max_limit[11]_i_4_n_0 ;\n wire \\one_inc_max_limit[4]_i_2_n_0 ;\n wire \\one_inc_max_limit[4]_i_3_n_0 ;\n wire \\one_inc_max_limit[4]_i_4_n_0 ;\n wire \\one_inc_max_limit[4]_i_5_n_0 ;\n wire \\one_inc_max_limit[8]_i_2_n_0 ;\n wire \\one_inc_max_limit[8]_i_3_n_0 ;\n wire \\one_inc_max_limit[8]_i_4_n_0 ;\n wire \\one_inc_max_limit[8]_i_5_n_0 ;\n wire [11:1]one_inc_max_limit_nxt;\n wire \\one_inc_max_limit_reg[11]_i_1_n_2 ;\n wire \\one_inc_max_limit_reg[11]_i_1_n_3 ;\n wire \\one_inc_max_limit_reg[4]_i_1_n_0 ;\n wire \\one_inc_max_limit_reg[4]_i_1_n_1 ;\n wire \\one_inc_max_limit_reg[4]_i_1_n_2 ;\n wire \\one_inc_max_limit_reg[4]_i_1_n_3 ;\n wire \\one_inc_max_limit_reg[8]_i_1_n_0 ;\n wire \\one_inc_max_limit_reg[8]_i_1_n_1 ;\n wire \\one_inc_max_limit_reg[8]_i_1_n_2 ;\n wire \\one_inc_max_limit_reg[8]_i_1_n_3 ;\n wire [11:1]one_inc_min_limit;\n wire \\one_inc_min_limit[11]_i_2_n_0 ;\n wire \\one_inc_min_limit[11]_i_3_n_0 ;\n wire \\one_inc_min_limit[5]_i_2_n_0 ;\n wire \\one_inc_min_limit[5]_i_3_n_0 ;\n wire \\one_inc_min_limit[5]_i_4_n_0 ;\n wire \\one_inc_min_limit[5]_i_5_n_0 ;\n wire \\one_inc_min_limit[9]_i_2_n_0 ;\n wire \\one_inc_min_limit[9]_i_3_n_0 ;\n wire \\one_inc_min_limit[9]_i_4_n_0 ;\n wire \\one_inc_min_limit[9]_i_5_n_0 ;\n wire [11:2]one_inc_min_limit_nxt;\n wire \\one_inc_min_limit_reg[11]_i_1_n_3 ;\n wire \\one_inc_min_limit_reg[5]_i_1_n_0 ;\n wire \\one_inc_min_limit_reg[5]_i_1_n_1 ;\n wire \\one_inc_min_limit_reg[5]_i_1_n_2 ;\n wire \\one_inc_min_limit_reg[5]_i_1_n_3 ;\n wire \\one_inc_min_limit_reg[9]_i_1_n_0 ;\n wire \\one_inc_min_limit_reg[9]_i_1_n_1 ;\n wire \\one_inc_min_limit_reg[9]_i_1_n_2 ;\n wire \\one_inc_min_limit_reg[9]_i_1_n_3 ;\n wire p_0_in;\n wire pi_f_dec_i_2_n_0;\n wire pi_f_dec_nxt;\n wire pi_f_inc_i_10_n_0;\n wire pi_f_inc_i_2_n_0;\n wire pi_f_inc_i_3_n_0;\n wire pi_f_inc_i_5_n_0;\n wire pi_f_inc_i_6_n_0;\n wire pi_f_inc_i_7_n_0;\n wire pi_f_inc_i_8_n_0;\n wire pi_f_inc_i_9_n_0;\n wire pi_f_inc_nxt;\n wire rd_data_offset_cal_done;\n wire rstdiv0_sync_r1_reg_rep__2;\n wire rstdiv0_sync_r1_reg_rep__25;\n wire rstdiv0_sync_r1_reg_rep__4;\n wire [0:0]rstdiv0_sync_r1_reg_rep__5;\n wire rstdiv0_sync_r1_reg_rep__6;\n wire rstdiv0_sync_r1_reg_rep__7;\n wire temp_cmp_four_dec_min_101;\n wire temp_cmp_four_dec_min_102;\n wire temp_cmp_four_dec_min_102_i_10_n_0;\n wire temp_cmp_four_dec_min_102_i_11_n_0;\n wire temp_cmp_four_dec_min_102_i_12_n_0;\n wire temp_cmp_four_dec_min_102_i_13_n_0;\n wire temp_cmp_four_dec_min_102_i_14_n_0;\n wire temp_cmp_four_dec_min_102_i_3_n_0;\n wire temp_cmp_four_dec_min_102_i_4_n_0;\n wire temp_cmp_four_dec_min_102_i_5_n_0;\n wire temp_cmp_four_dec_min_102_i_6_n_0;\n wire temp_cmp_four_dec_min_102_i_7_n_0;\n wire temp_cmp_four_dec_min_102_i_8_n_0;\n wire temp_cmp_four_dec_min_102_i_9_n_0;\n wire temp_cmp_four_dec_min_102_reg_i_1_n_3;\n wire temp_cmp_four_dec_min_102_reg_i_2_n_0;\n wire temp_cmp_four_dec_min_102_reg_i_2_n_1;\n wire temp_cmp_four_dec_min_102_reg_i_2_n_2;\n wire temp_cmp_four_dec_min_102_reg_i_2_n_3;\n wire temp_cmp_four_inc_max_101;\n wire temp_cmp_four_inc_max_102;\n wire temp_cmp_four_inc_max_102_i_10_n_0;\n wire temp_cmp_four_inc_max_102_i_11_n_0;\n wire temp_cmp_four_inc_max_102_i_12_n_0;\n wire temp_cmp_four_inc_max_102_i_13_n_0;\n wire temp_cmp_four_inc_max_102_i_14_n_0;\n wire temp_cmp_four_inc_max_102_i_3_n_0;\n wire temp_cmp_four_inc_max_102_i_4_n_0;\n wire temp_cmp_four_inc_max_102_i_5_n_0;\n wire temp_cmp_four_inc_max_102_i_6_n_0;\n wire temp_cmp_four_inc_max_102_i_7_n_0;\n wire temp_cmp_four_inc_max_102_i_8_n_0;\n wire temp_cmp_four_inc_max_102_i_9_n_0;\n wire temp_cmp_four_inc_max_102_reg_i_1_n_3;\n wire temp_cmp_four_inc_max_102_reg_i_2_n_0;\n wire temp_cmp_four_inc_max_102_reg_i_2_n_1;\n wire temp_cmp_four_inc_max_102_reg_i_2_n_2;\n wire temp_cmp_four_inc_max_102_reg_i_2_n_3;\n wire temp_cmp_neutral_max_101;\n wire temp_cmp_neutral_max_102;\n wire temp_cmp_neutral_max_102_i_10_n_0;\n wire temp_cmp_neutral_max_102_i_11_n_0;\n wire temp_cmp_neutral_max_102_i_12_n_0;\n wire temp_cmp_neutral_max_102_i_13_n_0;\n wire temp_cmp_neutral_max_102_i_14_n_0;\n wire temp_cmp_neutral_max_102_i_3_n_0;\n wire temp_cmp_neutral_max_102_i_4_n_0;\n wire temp_cmp_neutral_max_102_i_5_n_0;\n wire temp_cmp_neutral_max_102_i_6_n_0;\n wire temp_cmp_neutral_max_102_i_7_n_0;\n wire temp_cmp_neutral_max_102_i_8_n_0;\n wire temp_cmp_neutral_max_102_i_9_n_0;\n wire temp_cmp_neutral_max_102_reg_i_1_n_3;\n wire temp_cmp_neutral_max_102_reg_i_2_n_0;\n wire temp_cmp_neutral_max_102_reg_i_2_n_1;\n wire temp_cmp_neutral_max_102_reg_i_2_n_2;\n wire temp_cmp_neutral_max_102_reg_i_2_n_3;\n wire temp_cmp_neutral_min_101;\n wire temp_cmp_neutral_min_102;\n wire temp_cmp_neutral_min_102_i_10_n_0;\n wire temp_cmp_neutral_min_102_i_11_n_0;\n wire temp_cmp_neutral_min_102_i_12_n_0;\n wire temp_cmp_neutral_min_102_i_13_n_0;\n wire temp_cmp_neutral_min_102_i_14_n_0;\n wire temp_cmp_neutral_min_102_i_3_n_0;\n wire temp_cmp_neutral_min_102_i_4_n_0;\n wire temp_cmp_neutral_min_102_i_5_n_0;\n wire temp_cmp_neutral_min_102_i_6_n_0;\n wire temp_cmp_neutral_min_102_i_7_n_0;\n wire temp_cmp_neutral_min_102_i_8_n_0;\n wire temp_cmp_neutral_min_102_i_9_n_0;\n wire temp_cmp_neutral_min_102_reg_i_1_n_3;\n wire temp_cmp_neutral_min_102_reg_i_2_n_0;\n wire temp_cmp_neutral_min_102_reg_i_2_n_1;\n wire temp_cmp_neutral_min_102_reg_i_2_n_2;\n wire temp_cmp_neutral_min_102_reg_i_2_n_3;\n wire temp_cmp_one_dec_max_101;\n wire temp_cmp_one_dec_max_102;\n wire temp_cmp_one_dec_max_102_i_10_n_0;\n wire temp_cmp_one_dec_max_102_i_11_n_0;\n wire temp_cmp_one_dec_max_102_i_12_n_0;\n wire temp_cmp_one_dec_max_102_i_13_n_0;\n wire temp_cmp_one_dec_max_102_i_14_n_0;\n wire temp_cmp_one_dec_max_102_i_3_n_0;\n wire temp_cmp_one_dec_max_102_i_4_n_0;\n wire temp_cmp_one_dec_max_102_i_5_n_0;\n wire temp_cmp_one_dec_max_102_i_6_n_0;\n wire temp_cmp_one_dec_max_102_i_7_n_0;\n wire temp_cmp_one_dec_max_102_i_8_n_0;\n wire temp_cmp_one_dec_max_102_i_9_n_0;\n wire temp_cmp_one_dec_max_102_reg_i_1_n_3;\n wire temp_cmp_one_dec_max_102_reg_i_2_n_0;\n wire temp_cmp_one_dec_max_102_reg_i_2_n_1;\n wire temp_cmp_one_dec_max_102_reg_i_2_n_2;\n wire temp_cmp_one_dec_max_102_reg_i_2_n_3;\n wire temp_cmp_one_dec_min_101;\n wire temp_cmp_one_dec_min_102;\n wire temp_cmp_one_dec_min_102_i_10_n_0;\n wire temp_cmp_one_dec_min_102_i_11_n_0;\n wire temp_cmp_one_dec_min_102_i_12_n_0;\n wire temp_cmp_one_dec_min_102_i_13_n_0;\n wire temp_cmp_one_dec_min_102_i_14_n_0;\n wire temp_cmp_one_dec_min_102_i_3_n_0;\n wire temp_cmp_one_dec_min_102_i_4_n_0;\n wire temp_cmp_one_dec_min_102_i_5_n_0;\n wire temp_cmp_one_dec_min_102_i_6_n_0;\n wire temp_cmp_one_dec_min_102_i_7_n_0;\n wire temp_cmp_one_dec_min_102_i_8_n_0;\n wire temp_cmp_one_dec_min_102_i_9_n_0;\n wire temp_cmp_one_dec_min_102_reg_i_1_n_3;\n wire temp_cmp_one_dec_min_102_reg_i_2_n_0;\n wire temp_cmp_one_dec_min_102_reg_i_2_n_1;\n wire temp_cmp_one_dec_min_102_reg_i_2_n_2;\n wire temp_cmp_one_dec_min_102_reg_i_2_n_3;\n wire temp_cmp_one_inc_max_101;\n wire temp_cmp_one_inc_max_102;\n wire temp_cmp_one_inc_max_102_i_10_n_0;\n wire temp_cmp_one_inc_max_102_i_11_n_0;\n wire temp_cmp_one_inc_max_102_i_12_n_0;\n wire temp_cmp_one_inc_max_102_i_13_n_0;\n wire temp_cmp_one_inc_max_102_i_14_n_0;\n wire temp_cmp_one_inc_max_102_i_3_n_0;\n wire temp_cmp_one_inc_max_102_i_4_n_0;\n wire temp_cmp_one_inc_max_102_i_5_n_0;\n wire temp_cmp_one_inc_max_102_i_6_n_0;\n wire temp_cmp_one_inc_max_102_i_7_n_0;\n wire temp_cmp_one_inc_max_102_i_8_n_0;\n wire temp_cmp_one_inc_max_102_i_9_n_0;\n wire temp_cmp_one_inc_max_102_reg_i_1_n_3;\n wire temp_cmp_one_inc_max_102_reg_i_2_n_0;\n wire temp_cmp_one_inc_max_102_reg_i_2_n_1;\n wire temp_cmp_one_inc_max_102_reg_i_2_n_2;\n wire temp_cmp_one_inc_max_102_reg_i_2_n_3;\n wire temp_cmp_one_inc_min_101;\n wire temp_cmp_one_inc_min_102;\n wire temp_cmp_one_inc_min_102_i_10_n_0;\n wire temp_cmp_one_inc_min_102_i_11_n_0;\n wire temp_cmp_one_inc_min_102_i_12_n_0;\n wire temp_cmp_one_inc_min_102_i_13_n_0;\n wire temp_cmp_one_inc_min_102_i_14_n_0;\n wire temp_cmp_one_inc_min_102_i_3_n_0;\n wire temp_cmp_one_inc_min_102_i_4_n_0;\n wire temp_cmp_one_inc_min_102_i_5_n_0;\n wire temp_cmp_one_inc_min_102_i_6_n_0;\n wire temp_cmp_one_inc_min_102_i_7_n_0;\n wire temp_cmp_one_inc_min_102_i_8_n_0;\n wire temp_cmp_one_inc_min_102_i_9_n_0;\n wire temp_cmp_one_inc_min_102_reg_i_1_n_3;\n wire temp_cmp_one_inc_min_102_reg_i_2_n_0;\n wire temp_cmp_one_inc_min_102_reg_i_2_n_1;\n wire temp_cmp_one_inc_min_102_reg_i_2_n_2;\n wire temp_cmp_one_inc_min_102_reg_i_2_n_3;\n wire temp_cmp_three_dec_max_101;\n wire temp_cmp_three_dec_max_102;\n wire temp_cmp_three_dec_max_102_i_10_n_0;\n wire temp_cmp_three_dec_max_102_i_11_n_0;\n wire temp_cmp_three_dec_max_102_i_12_n_0;\n wire temp_cmp_three_dec_max_102_i_13_n_0;\n wire temp_cmp_three_dec_max_102_i_14_n_0;\n wire temp_cmp_three_dec_max_102_i_3_n_0;\n wire temp_cmp_three_dec_max_102_i_4_n_0;\n wire temp_cmp_three_dec_max_102_i_5_n_0;\n wire temp_cmp_three_dec_max_102_i_6_n_0;\n wire temp_cmp_three_dec_max_102_i_7_n_0;\n wire temp_cmp_three_dec_max_102_i_8_n_0;\n wire temp_cmp_three_dec_max_102_i_9_n_0;\n wire temp_cmp_three_dec_max_102_reg_i_1_n_3;\n wire temp_cmp_three_dec_max_102_reg_i_2_n_0;\n wire temp_cmp_three_dec_max_102_reg_i_2_n_1;\n wire temp_cmp_three_dec_max_102_reg_i_2_n_2;\n wire temp_cmp_three_dec_max_102_reg_i_2_n_3;\n wire temp_cmp_three_dec_min_101;\n wire temp_cmp_three_dec_min_102;\n wire temp_cmp_three_dec_min_102_i_10_n_0;\n wire temp_cmp_three_dec_min_102_i_11_n_0;\n wire temp_cmp_three_dec_min_102_i_12_n_0;\n wire temp_cmp_three_dec_min_102_i_13_n_0;\n wire temp_cmp_three_dec_min_102_i_14_n_0;\n wire temp_cmp_three_dec_min_102_i_3_n_0;\n wire temp_cmp_three_dec_min_102_i_4_n_0;\n wire temp_cmp_three_dec_min_102_i_5_n_0;\n wire temp_cmp_three_dec_min_102_i_6_n_0;\n wire temp_cmp_three_dec_min_102_i_7_n_0;\n wire temp_cmp_three_dec_min_102_i_8_n_0;\n wire temp_cmp_three_dec_min_102_i_9_n_0;\n wire temp_cmp_three_dec_min_102_reg_i_1_n_3;\n wire temp_cmp_three_dec_min_102_reg_i_2_n_0;\n wire temp_cmp_three_dec_min_102_reg_i_2_n_1;\n wire temp_cmp_three_dec_min_102_reg_i_2_n_2;\n wire temp_cmp_three_dec_min_102_reg_i_2_n_3;\n wire temp_cmp_three_inc_max_101;\n wire temp_cmp_three_inc_max_102;\n wire temp_cmp_three_inc_max_102_i_10_n_0;\n wire temp_cmp_three_inc_max_102_i_11_n_0;\n wire temp_cmp_three_inc_max_102_i_12_n_0;\n wire temp_cmp_three_inc_max_102_i_13_n_0;\n wire temp_cmp_three_inc_max_102_i_14_n_0;\n wire temp_cmp_three_inc_max_102_i_3_n_0;\n wire temp_cmp_three_inc_max_102_i_4_n_0;\n wire temp_cmp_three_inc_max_102_i_5_n_0;\n wire temp_cmp_three_inc_max_102_i_6_n_0;\n wire temp_cmp_three_inc_max_102_i_7_n_0;\n wire temp_cmp_three_inc_max_102_i_8_n_0;\n wire temp_cmp_three_inc_max_102_i_9_n_0;\n wire temp_cmp_three_inc_max_102_reg_i_1_n_3;\n wire temp_cmp_three_inc_max_102_reg_i_2_n_0;\n wire temp_cmp_three_inc_max_102_reg_i_2_n_1;\n wire temp_cmp_three_inc_max_102_reg_i_2_n_2;\n wire temp_cmp_three_inc_max_102_reg_i_2_n_3;\n wire temp_cmp_three_inc_min_101;\n wire temp_cmp_three_inc_min_102;\n wire temp_cmp_three_inc_min_102_i_10_n_0;\n wire temp_cmp_three_inc_min_102_i_11_n_0;\n wire temp_cmp_three_inc_min_102_i_12_n_0;\n wire temp_cmp_three_inc_min_102_i_13_n_0;\n wire temp_cmp_three_inc_min_102_i_14_n_0;\n wire temp_cmp_three_inc_min_102_i_3_n_0;\n wire temp_cmp_three_inc_min_102_i_4_n_0;\n wire temp_cmp_three_inc_min_102_i_5_n_0;\n wire temp_cmp_three_inc_min_102_i_6_n_0;\n wire temp_cmp_three_inc_min_102_i_7_n_0;\n wire temp_cmp_three_inc_min_102_i_8_n_0;\n wire temp_cmp_three_inc_min_102_i_9_n_0;\n wire temp_cmp_three_inc_min_102_reg_i_1_n_3;\n wire temp_cmp_three_inc_min_102_reg_i_2_n_0;\n wire temp_cmp_three_inc_min_102_reg_i_2_n_1;\n wire temp_cmp_three_inc_min_102_reg_i_2_n_2;\n wire temp_cmp_three_inc_min_102_reg_i_2_n_3;\n wire temp_cmp_two_dec_max_101;\n wire temp_cmp_two_dec_max_102;\n wire temp_cmp_two_dec_max_102_i_10_n_0;\n wire temp_cmp_two_dec_max_102_i_11_n_0;\n wire temp_cmp_two_dec_max_102_i_12_n_0;\n wire temp_cmp_two_dec_max_102_i_13_n_0;\n wire temp_cmp_two_dec_max_102_i_14_n_0;\n wire temp_cmp_two_dec_max_102_i_3_n_0;\n wire temp_cmp_two_dec_max_102_i_4_n_0;\n wire temp_cmp_two_dec_max_102_i_5_n_0;\n wire temp_cmp_two_dec_max_102_i_6_n_0;\n wire temp_cmp_two_dec_max_102_i_7_n_0;\n wire temp_cmp_two_dec_max_102_i_8_n_0;\n wire temp_cmp_two_dec_max_102_i_9_n_0;\n wire temp_cmp_two_dec_max_102_reg_i_1_n_3;\n wire temp_cmp_two_dec_max_102_reg_i_2_n_0;\n wire temp_cmp_two_dec_max_102_reg_i_2_n_1;\n wire temp_cmp_two_dec_max_102_reg_i_2_n_2;\n wire temp_cmp_two_dec_max_102_reg_i_2_n_3;\n wire temp_cmp_two_dec_min_101;\n wire temp_cmp_two_dec_min_102;\n wire temp_cmp_two_dec_min_102_i_10_n_0;\n wire temp_cmp_two_dec_min_102_i_11_n_0;\n wire temp_cmp_two_dec_min_102_i_12_n_0;\n wire temp_cmp_two_dec_min_102_i_13_n_0;\n wire temp_cmp_two_dec_min_102_i_14_n_0;\n wire temp_cmp_two_dec_min_102_i_3_n_0;\n wire temp_cmp_two_dec_min_102_i_4_n_0;\n wire temp_cmp_two_dec_min_102_i_5_n_0;\n wire temp_cmp_two_dec_min_102_i_6_n_0;\n wire temp_cmp_two_dec_min_102_i_7_n_0;\n wire temp_cmp_two_dec_min_102_i_8_n_0;\n wire temp_cmp_two_dec_min_102_i_9_n_0;\n wire temp_cmp_two_dec_min_102_reg_i_1_n_3;\n wire temp_cmp_two_dec_min_102_reg_i_2_n_0;\n wire temp_cmp_two_dec_min_102_reg_i_2_n_1;\n wire temp_cmp_two_dec_min_102_reg_i_2_n_2;\n wire temp_cmp_two_dec_min_102_reg_i_2_n_3;\n wire temp_cmp_two_inc_max_101;\n wire temp_cmp_two_inc_max_102;\n wire temp_cmp_two_inc_max_102_i_10_n_0;\n wire temp_cmp_two_inc_max_102_i_11_n_0;\n wire temp_cmp_two_inc_max_102_i_12_n_0;\n wire temp_cmp_two_inc_max_102_i_13_n_0;\n wire temp_cmp_two_inc_max_102_i_14_n_0;\n wire temp_cmp_two_inc_max_102_i_3_n_0;\n wire temp_cmp_two_inc_max_102_i_4_n_0;\n wire temp_cmp_two_inc_max_102_i_5_n_0;\n wire temp_cmp_two_inc_max_102_i_6_n_0;\n wire temp_cmp_two_inc_max_102_i_7_n_0;\n wire temp_cmp_two_inc_max_102_i_8_n_0;\n wire temp_cmp_two_inc_max_102_i_9_n_0;\n wire temp_cmp_two_inc_max_102_reg_i_1_n_3;\n wire temp_cmp_two_inc_max_102_reg_i_2_n_0;\n wire temp_cmp_two_inc_max_102_reg_i_2_n_1;\n wire temp_cmp_two_inc_max_102_reg_i_2_n_2;\n wire temp_cmp_two_inc_max_102_reg_i_2_n_3;\n wire temp_cmp_two_inc_min_101;\n wire temp_cmp_two_inc_min_102;\n wire temp_cmp_two_inc_min_102_i_10_n_0;\n wire temp_cmp_two_inc_min_102_i_11_n_0;\n wire temp_cmp_two_inc_min_102_i_12_n_0;\n wire temp_cmp_two_inc_min_102_i_13_n_0;\n wire temp_cmp_two_inc_min_102_i_14_n_0;\n wire temp_cmp_two_inc_min_102_i_3_n_0;\n wire temp_cmp_two_inc_min_102_i_4_n_0;\n wire temp_cmp_two_inc_min_102_i_5_n_0;\n wire temp_cmp_two_inc_min_102_i_6_n_0;\n wire temp_cmp_two_inc_min_102_i_7_n_0;\n wire temp_cmp_two_inc_min_102_i_8_n_0;\n wire temp_cmp_two_inc_min_102_i_9_n_0;\n wire temp_cmp_two_inc_min_102_reg_i_1_n_3;\n wire temp_cmp_two_inc_min_102_reg_i_2_n_0;\n wire temp_cmp_two_inc_min_102_reg_i_2_n_1;\n wire temp_cmp_two_inc_min_102_reg_i_2_n_2;\n wire temp_cmp_two_inc_min_102_reg_i_2_n_3;\n wire temp_gte_three_dec_max;\n wire tempmon_init_complete;\n wire tempmon_pi_f_dec;\n wire tempmon_pi_f_inc;\n wire tempmon_sample_en;\n wire tempmon_sample_en_101;\n wire tempmon_sample_en_102;\n wire tempmon_sel_pi_incdec;\n wire [10:0]tempmon_state;\n wire \\tempmon_state[0]_i_2_n_0 ;\n wire \\tempmon_state[10]_i_10_n_0 ;\n wire \\tempmon_state[10]_i_11_n_0 ;\n wire \\tempmon_state[10]_i_12_n_0 ;\n wire \\tempmon_state[10]_i_13_n_0 ;\n wire \\tempmon_state[10]_i_14_n_0 ;\n wire \\tempmon_state[10]_i_15_n_0 ;\n wire \\tempmon_state[10]_i_16_n_0 ;\n wire \\tempmon_state[10]_i_2_n_0 ;\n wire \\tempmon_state[10]_i_3_n_0 ;\n wire \\tempmon_state[10]_i_4_n_0 ;\n wire \\tempmon_state[10]_i_5_n_0 ;\n wire \\tempmon_state[10]_i_6_n_0 ;\n wire \\tempmon_state[10]_i_7_n_0 ;\n wire \\tempmon_state[10]_i_8_n_0 ;\n wire \\tempmon_state[10]_i_9_n_0 ;\n wire \\tempmon_state[1]_i_1_n_0 ;\n wire \\tempmon_state[2]_i_1_n_0 ;\n wire \\tempmon_state[3]_i_1_n_0 ;\n wire \\tempmon_state[4]_i_1_n_0 ;\n wire \\tempmon_state[5]_i_1_n_0 ;\n wire \\tempmon_state[6]_i_1_n_0 ;\n wire \\tempmon_state[6]_i_2_n_0 ;\n wire \\tempmon_state[7]_i_1_n_0 ;\n wire \\tempmon_state[8]_i_1_n_0 ;\n wire \\tempmon_state[9]_i_1_n_0 ;\n wire tempmon_state_init;\n wire tempmon_state_nxt;\n wire [11:0]three_dec_max_limit;\n wire \\three_dec_max_limit[0]_i_1_n_0 ;\n wire \\three_dec_max_limit[10]_i_1_n_0 ;\n wire \\three_dec_max_limit[11]_i_1_n_0 ;\n wire \\three_dec_max_limit[11]_i_3_n_0 ;\n wire \\three_dec_max_limit[11]_i_4_n_0 ;\n wire \\three_dec_max_limit[11]_i_5_n_0 ;\n wire \\three_dec_max_limit[1]_i_1_n_0 ;\n wire \\three_dec_max_limit[2]_i_1_n_0 ;\n wire \\three_dec_max_limit[3]_i_1_n_0 ;\n wire \\three_dec_max_limit[4]_i_1_n_0 ;\n wire \\three_dec_max_limit[4]_i_3_n_0 ;\n wire \\three_dec_max_limit[4]_i_4_n_0 ;\n wire \\three_dec_max_limit[4]_i_5_n_0 ;\n wire \\three_dec_max_limit[4]_i_6_n_0 ;\n wire \\three_dec_max_limit[5]_i_1_n_0 ;\n wire \\three_dec_max_limit[6]_i_1_n_0 ;\n wire \\three_dec_max_limit[7]_i_1_n_0 ;\n wire \\three_dec_max_limit[8]_i_1_n_0 ;\n wire \\three_dec_max_limit[8]_i_3_n_0 ;\n wire \\three_dec_max_limit[8]_i_4_n_0 ;\n wire \\three_dec_max_limit[8]_i_5_n_0 ;\n wire \\three_dec_max_limit[8]_i_6_n_0 ;\n wire \\three_dec_max_limit[9]_i_1_n_0 ;\n wire \\three_dec_max_limit_reg[11]_i_2_n_2 ;\n wire \\three_dec_max_limit_reg[11]_i_2_n_3 ;\n wire \\three_dec_max_limit_reg[11]_i_2_n_5 ;\n wire \\three_dec_max_limit_reg[11]_i_2_n_6 ;\n wire \\three_dec_max_limit_reg[11]_i_2_n_7 ;\n wire \\three_dec_max_limit_reg[1]_i_2_n_0 ;\n wire \\three_dec_max_limit_reg[4]_i_2_n_0 ;\n wire \\three_dec_max_limit_reg[4]_i_2_n_1 ;\n wire \\three_dec_max_limit_reg[4]_i_2_n_2 ;\n wire \\three_dec_max_limit_reg[4]_i_2_n_3 ;\n wire \\three_dec_max_limit_reg[4]_i_2_n_4 ;\n wire \\three_dec_max_limit_reg[4]_i_2_n_5 ;\n wire \\three_dec_max_limit_reg[4]_i_2_n_6 ;\n wire \\three_dec_max_limit_reg[8]_i_2_n_0 ;\n wire \\three_dec_max_limit_reg[8]_i_2_n_1 ;\n wire \\three_dec_max_limit_reg[8]_i_2_n_2 ;\n wire \\three_dec_max_limit_reg[8]_i_2_n_3 ;\n wire \\three_dec_max_limit_reg[8]_i_2_n_4 ;\n wire \\three_dec_max_limit_reg[8]_i_2_n_5 ;\n wire \\three_dec_max_limit_reg[8]_i_2_n_6 ;\n wire \\three_dec_max_limit_reg[8]_i_2_n_7 ;\n wire [11:0]three_dec_min_limit;\n wire \\three_dec_min_limit[11]_i_2_n_0 ;\n wire \\three_dec_min_limit[11]_i_3_n_0 ;\n wire \\three_dec_min_limit[5]_i_2_n_0 ;\n wire \\three_dec_min_limit[5]_i_3_n_0 ;\n wire \\three_dec_min_limit[5]_i_4_n_0 ;\n wire \\three_dec_min_limit[5]_i_5_n_0 ;\n wire \\three_dec_min_limit[9]_i_2_n_0 ;\n wire \\three_dec_min_limit[9]_i_3_n_0 ;\n wire \\three_dec_min_limit[9]_i_4_n_0 ;\n wire \\three_dec_min_limit[9]_i_5_n_0 ;\n wire [11:2]three_dec_min_limit_nxt;\n wire \\three_dec_min_limit_reg[11]_i_1_n_3 ;\n wire \\three_dec_min_limit_reg[5]_i_1_n_0 ;\n wire \\three_dec_min_limit_reg[5]_i_1_n_1 ;\n wire \\three_dec_min_limit_reg[5]_i_1_n_2 ;\n wire \\three_dec_min_limit_reg[5]_i_1_n_3 ;\n wire \\three_dec_min_limit_reg[9]_i_1_n_0 ;\n wire \\three_dec_min_limit_reg[9]_i_1_n_1 ;\n wire \\three_dec_min_limit_reg[9]_i_1_n_2 ;\n wire \\three_dec_min_limit_reg[9]_i_1_n_3 ;\n wire [11:1]three_inc_max_limit;\n wire \\three_inc_max_limit[11]_i_2_n_0 ;\n wire \\three_inc_max_limit[11]_i_3_n_0 ;\n wire \\three_inc_max_limit[11]_i_4_n_0 ;\n wire \\three_inc_max_limit[4]_i_2_n_0 ;\n wire \\three_inc_max_limit[4]_i_3_n_0 ;\n wire \\three_inc_max_limit[4]_i_4_n_0 ;\n wire \\three_inc_max_limit[4]_i_5_n_0 ;\n wire \\three_inc_max_limit[8]_i_2_n_0 ;\n wire \\three_inc_max_limit[8]_i_3_n_0 ;\n wire \\three_inc_max_limit[8]_i_4_n_0 ;\n wire \\three_inc_max_limit[8]_i_5_n_0 ;\n wire [11:1]three_inc_max_limit_nxt;\n wire \\three_inc_max_limit_reg[11]_i_1_n_2 ;\n wire \\three_inc_max_limit_reg[11]_i_1_n_3 ;\n wire \\three_inc_max_limit_reg[4]_i_1_n_0 ;\n wire \\three_inc_max_limit_reg[4]_i_1_n_1 ;\n wire \\three_inc_max_limit_reg[4]_i_1_n_2 ;\n wire \\three_inc_max_limit_reg[4]_i_1_n_3 ;\n wire \\three_inc_max_limit_reg[8]_i_1_n_0 ;\n wire \\three_inc_max_limit_reg[8]_i_1_n_1 ;\n wire \\three_inc_max_limit_reg[8]_i_1_n_2 ;\n wire \\three_inc_max_limit_reg[8]_i_1_n_3 ;\n wire [11:1]three_inc_min_limit;\n wire \\three_inc_min_limit[11]_i_2_n_0 ;\n wire \\three_inc_min_limit[11]_i_3_n_0 ;\n wire \\three_inc_min_limit[5]_i_2_n_0 ;\n wire \\three_inc_min_limit[5]_i_3_n_0 ;\n wire \\three_inc_min_limit[5]_i_4_n_0 ;\n wire \\three_inc_min_limit[5]_i_5_n_0 ;\n wire \\three_inc_min_limit[9]_i_2_n_0 ;\n wire \\three_inc_min_limit[9]_i_3_n_0 ;\n wire \\three_inc_min_limit[9]_i_4_n_0 ;\n wire \\three_inc_min_limit[9]_i_5_n_0 ;\n wire [11:2]three_inc_min_limit_nxt;\n wire \\three_inc_min_limit_reg[11]_i_1_n_3 ;\n wire \\three_inc_min_limit_reg[5]_i_1_n_0 ;\n wire \\three_inc_min_limit_reg[5]_i_1_n_1 ;\n wire \\three_inc_min_limit_reg[5]_i_1_n_2 ;\n wire \\three_inc_min_limit_reg[5]_i_1_n_3 ;\n wire \\three_inc_min_limit_reg[9]_i_1_n_0 ;\n wire \\three_inc_min_limit_reg[9]_i_1_n_1 ;\n wire \\three_inc_min_limit_reg[9]_i_1_n_2 ;\n wire \\three_inc_min_limit_reg[9]_i_1_n_3 ;\n wire [11:0]two_dec_max_limit;\n wire \\two_dec_max_limit[0]_i_1_n_0 ;\n wire \\two_dec_max_limit[11]_i_2_n_0 ;\n wire \\two_dec_max_limit[11]_i_3_n_0 ;\n wire \\two_dec_max_limit[11]_i_4_n_0 ;\n wire \\two_dec_max_limit[4]_i_2_n_0 ;\n wire \\two_dec_max_limit[4]_i_3_n_0 ;\n wire \\two_dec_max_limit[4]_i_4_n_0 ;\n wire \\two_dec_max_limit[4]_i_5_n_0 ;\n wire \\two_dec_max_limit[8]_i_2_n_0 ;\n wire \\two_dec_max_limit[8]_i_3_n_0 ;\n wire \\two_dec_max_limit[8]_i_4_n_0 ;\n wire \\two_dec_max_limit[8]_i_5_n_0 ;\n wire [11:1]two_dec_max_limit_nxt;\n wire \\two_dec_max_limit_reg[11]_i_1_n_2 ;\n wire \\two_dec_max_limit_reg[11]_i_1_n_3 ;\n wire \\two_dec_max_limit_reg[4]_i_1_n_0 ;\n wire \\two_dec_max_limit_reg[4]_i_1_n_1 ;\n wire \\two_dec_max_limit_reg[4]_i_1_n_2 ;\n wire \\two_dec_max_limit_reg[4]_i_1_n_3 ;\n wire \\two_dec_max_limit_reg[8]_i_1_n_0 ;\n wire \\two_dec_max_limit_reg[8]_i_1_n_1 ;\n wire \\two_dec_max_limit_reg[8]_i_1_n_2 ;\n wire \\two_dec_max_limit_reg[8]_i_1_n_3 ;\n wire [11:1]two_dec_min_limit;\n wire \\two_dec_min_limit[11]_i_2_n_0 ;\n wire \\two_dec_min_limit[11]_i_3_n_0 ;\n wire \\two_dec_min_limit[5]_i_2_n_0 ;\n wire \\two_dec_min_limit[5]_i_3_n_0 ;\n wire \\two_dec_min_limit[5]_i_4_n_0 ;\n wire \\two_dec_min_limit[5]_i_5_n_0 ;\n wire \\two_dec_min_limit[9]_i_2_n_0 ;\n wire \\two_dec_min_limit[9]_i_3_n_0 ;\n wire \\two_dec_min_limit[9]_i_4_n_0 ;\n wire \\two_dec_min_limit[9]_i_5_n_0 ;\n wire [11:2]two_dec_min_limit_nxt;\n wire \\two_dec_min_limit_reg[11]_i_1_n_3 ;\n wire \\two_dec_min_limit_reg[5]_i_1_n_0 ;\n wire \\two_dec_min_limit_reg[5]_i_1_n_1 ;\n wire \\two_dec_min_limit_reg[5]_i_1_n_2 ;\n wire \\two_dec_min_limit_reg[5]_i_1_n_3 ;\n wire \\two_dec_min_limit_reg[9]_i_1_n_0 ;\n wire \\two_dec_min_limit_reg[9]_i_1_n_1 ;\n wire \\two_dec_min_limit_reg[9]_i_1_n_2 ;\n wire \\two_dec_min_limit_reg[9]_i_1_n_3 ;\n wire [11:1]two_inc_max_limit;\n wire \\two_inc_max_limit[11]_i_2_n_0 ;\n wire \\two_inc_max_limit[11]_i_3_n_0 ;\n wire \\two_inc_max_limit[11]_i_4_n_0 ;\n wire \\two_inc_max_limit[4]_i_2_n_0 ;\n wire \\two_inc_max_limit[4]_i_3_n_0 ;\n wire \\two_inc_max_limit[4]_i_4_n_0 ;\n wire \\two_inc_max_limit[4]_i_5_n_0 ;\n wire \\two_inc_max_limit[8]_i_2_n_0 ;\n wire \\two_inc_max_limit[8]_i_3_n_0 ;\n wire \\two_inc_max_limit[8]_i_4_n_0 ;\n wire \\two_inc_max_limit[8]_i_5_n_0 ;\n wire [11:1]two_inc_max_limit_nxt;\n wire \\two_inc_max_limit_reg[11]_i_1_n_2 ;\n wire \\two_inc_max_limit_reg[11]_i_1_n_3 ;\n wire \\two_inc_max_limit_reg[4]_i_1_n_0 ;\n wire \\two_inc_max_limit_reg[4]_i_1_n_1 ;\n wire \\two_inc_max_limit_reg[4]_i_1_n_2 ;\n wire \\two_inc_max_limit_reg[4]_i_1_n_3 ;\n wire \\two_inc_max_limit_reg[8]_i_1_n_0 ;\n wire \\two_inc_max_limit_reg[8]_i_1_n_1 ;\n wire \\two_inc_max_limit_reg[8]_i_1_n_2 ;\n wire \\two_inc_max_limit_reg[8]_i_1_n_3 ;\n wire [11:1]two_inc_min_limit;\n wire \\two_inc_min_limit[11]_i_2_n_0 ;\n wire \\two_inc_min_limit[11]_i_3_n_0 ;\n wire \\two_inc_min_limit[5]_i_2_n_0 ;\n wire \\two_inc_min_limit[5]_i_3_n_0 ;\n wire \\two_inc_min_limit[5]_i_4_n_0 ;\n wire \\two_inc_min_limit[5]_i_5_n_0 ;\n wire \\two_inc_min_limit[9]_i_2_n_0 ;\n wire \\two_inc_min_limit[9]_i_3_n_0 ;\n wire \\two_inc_min_limit[9]_i_4_n_0 ;\n wire \\two_inc_min_limit[9]_i_5_n_0 ;\n wire [11:2]two_inc_min_limit_nxt;\n wire \\two_inc_min_limit_reg[11]_i_1_n_3 ;\n wire \\two_inc_min_limit_reg[5]_i_1_n_0 ;\n wire \\two_inc_min_limit_reg[5]_i_1_n_1 ;\n wire \\two_inc_min_limit_reg[5]_i_1_n_2 ;\n wire \\two_inc_min_limit_reg[5]_i_1_n_3 ;\n wire \\two_inc_min_limit_reg[9]_i_1_n_0 ;\n wire \\two_inc_min_limit_reg[9]_i_1_n_1 ;\n wire \\two_inc_min_limit_reg[9]_i_1_n_2 ;\n wire \\two_inc_min_limit_reg[9]_i_1_n_3 ;\n wire update_temp_101__0;\n wire update_temp_102;\n wire [3:1]\\NLW_four_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED ;\n wire [3:2]\\NLW_four_dec_min_limit_reg[11]_i_1_O_UNCONNECTED ;\n wire [3:2]\\NLW_four_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED ;\n wire [3:3]\\NLW_four_inc_max_limit_reg[11]_i_1_O_UNCONNECTED ;\n wire [3:0]\\NLW_four_inc_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED ;\n wire [3:0]\\NLW_four_inc_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED ;\n wire [3:1]\\NLW_four_inc_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED ;\n wire [3:1]\\NLW_four_inc_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED ;\n wire [3:2]\\NLW_neutral_max_limit_reg[11]_i_1_CO_UNCONNECTED ;\n wire [3:3]\\NLW_neutral_max_limit_reg[11]_i_1_O_UNCONNECTED ;\n wire [3:0]\\NLW_neutral_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED ;\n wire [3:0]\\NLW_neutral_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED ;\n wire [3:1]\\NLW_neutral_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED ;\n wire [3:1]\\NLW_neutral_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED ;\n wire [0:0]\\NLW_neutral_max_limit_reg[4]_i_1_O_UNCONNECTED ;\n wire [3:1]\\NLW_neutral_min_limit_reg[11]_i_1_CO_UNCONNECTED ;\n wire [3:2]\\NLW_neutral_min_limit_reg[11]_i_1_O_UNCONNECTED ;\n wire [3:2]\\NLW_one_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED ;\n wire [3:3]\\NLW_one_dec_max_limit_reg[11]_i_1_O_UNCONNECTED ;\n wire [3:0]\\NLW_one_dec_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED ;\n wire [3:0]\\NLW_one_dec_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED ;\n wire [3:1]\\NLW_one_dec_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED ;\n wire [3:1]\\NLW_one_dec_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED ;\n wire [0:0]\\NLW_one_dec_max_limit_reg[4]_i_1_O_UNCONNECTED ;\n wire [3:1]\\NLW_one_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED ;\n wire [3:2]\\NLW_one_dec_min_limit_reg[11]_i_1_O_UNCONNECTED ;\n wire [3:2]\\NLW_one_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED ;\n wire [3:3]\\NLW_one_inc_max_limit_reg[11]_i_1_O_UNCONNECTED ;\n wire [3:0]\\NLW_one_inc_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED ;\n wire [3:0]\\NLW_one_inc_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED ;\n wire [3:1]\\NLW_one_inc_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED ;\n wire [3:1]\\NLW_one_inc_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED ;\n wire [0:0]\\NLW_one_inc_max_limit_reg[4]_i_1_O_UNCONNECTED ;\n wire [3:1]\\NLW_one_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED ;\n wire [3:2]\\NLW_one_inc_min_limit_reg[11]_i_1_O_UNCONNECTED ;\n wire [3:2]NLW_temp_cmp_four_dec_min_102_reg_i_1_CO_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_four_dec_min_102_reg_i_1_O_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_four_dec_min_102_reg_i_2_O_UNCONNECTED;\n wire [3:2]NLW_temp_cmp_four_inc_max_102_reg_i_1_CO_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_four_inc_max_102_reg_i_1_O_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_four_inc_max_102_reg_i_2_O_UNCONNECTED;\n wire [3:2]NLW_temp_cmp_neutral_max_102_reg_i_1_CO_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_neutral_max_102_reg_i_1_O_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_neutral_max_102_reg_i_2_O_UNCONNECTED;\n wire [3:2]NLW_temp_cmp_neutral_min_102_reg_i_1_CO_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_neutral_min_102_reg_i_1_O_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_neutral_min_102_reg_i_2_O_UNCONNECTED;\n wire [3:2]NLW_temp_cmp_one_dec_max_102_reg_i_1_CO_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_one_dec_max_102_reg_i_1_O_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_one_dec_max_102_reg_i_2_O_UNCONNECTED;\n wire [3:2]NLW_temp_cmp_one_dec_min_102_reg_i_1_CO_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_one_dec_min_102_reg_i_1_O_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_one_dec_min_102_reg_i_2_O_UNCONNECTED;\n wire [3:2]NLW_temp_cmp_one_inc_max_102_reg_i_1_CO_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_one_inc_max_102_reg_i_1_O_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_one_inc_max_102_reg_i_2_O_UNCONNECTED;\n wire [3:2]NLW_temp_cmp_one_inc_min_102_reg_i_1_CO_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_one_inc_min_102_reg_i_1_O_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_one_inc_min_102_reg_i_2_O_UNCONNECTED;\n wire [3:2]NLW_temp_cmp_three_dec_max_102_reg_i_1_CO_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_three_dec_max_102_reg_i_1_O_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_three_dec_max_102_reg_i_2_O_UNCONNECTED;\n wire [3:2]NLW_temp_cmp_three_dec_min_102_reg_i_1_CO_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_three_dec_min_102_reg_i_1_O_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_three_dec_min_102_reg_i_2_O_UNCONNECTED;\n wire [3:2]NLW_temp_cmp_three_inc_max_102_reg_i_1_CO_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_three_inc_max_102_reg_i_1_O_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_three_inc_max_102_reg_i_2_O_UNCONNECTED;\n wire [3:2]NLW_temp_cmp_three_inc_min_102_reg_i_1_CO_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_three_inc_min_102_reg_i_1_O_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_three_inc_min_102_reg_i_2_O_UNCONNECTED;\n wire [3:2]NLW_temp_cmp_two_dec_max_102_reg_i_1_CO_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_two_dec_max_102_reg_i_1_O_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_two_dec_max_102_reg_i_2_O_UNCONNECTED;\n wire [3:2]NLW_temp_cmp_two_dec_min_102_reg_i_1_CO_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_two_dec_min_102_reg_i_1_O_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_two_dec_min_102_reg_i_2_O_UNCONNECTED;\n wire [3:2]NLW_temp_cmp_two_inc_max_102_reg_i_1_CO_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_two_inc_max_102_reg_i_1_O_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_two_inc_max_102_reg_i_2_O_UNCONNECTED;\n wire [3:2]NLW_temp_cmp_two_inc_min_102_reg_i_1_CO_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_two_inc_min_102_reg_i_1_O_UNCONNECTED;\n wire [3:0]NLW_temp_cmp_two_inc_min_102_reg_i_2_O_UNCONNECTED;\n wire [2:2]\\NLW_three_dec_max_limit_reg[11]_i_2_CO_UNCONNECTED ;\n wire [3:3]\\NLW_three_dec_max_limit_reg[11]_i_2_O_UNCONNECTED ;\n wire [3:0]\\NLW_three_dec_max_limit_reg[1]_i_2_CARRY4_CO_UNCONNECTED ;\n wire [3:0]\\NLW_three_dec_max_limit_reg[1]_i_2_CARRY4_DI_UNCONNECTED ;\n wire [3:1]\\NLW_three_dec_max_limit_reg[1]_i_2_CARRY4_O_UNCONNECTED ;\n wire [3:1]\\NLW_three_dec_max_limit_reg[1]_i_2_CARRY4_S_UNCONNECTED ;\n wire [0:0]\\NLW_three_dec_max_limit_reg[4]_i_2_O_UNCONNECTED ;\n wire [3:1]\\NLW_three_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED ;\n wire [3:2]\\NLW_three_dec_min_limit_reg[11]_i_1_O_UNCONNECTED ;\n wire [3:2]\\NLW_three_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED ;\n wire [3:3]\\NLW_three_inc_max_limit_reg[11]_i_1_O_UNCONNECTED ;\n wire [3:1]\\NLW_three_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED ;\n wire [3:2]\\NLW_three_inc_min_limit_reg[11]_i_1_O_UNCONNECTED ;\n wire [3:2]\\NLW_two_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED ;\n wire [3:3]\\NLW_two_dec_max_limit_reg[11]_i_1_O_UNCONNECTED ;\n wire [3:0]\\NLW_two_dec_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED ;\n wire [3:0]\\NLW_two_dec_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED ;\n wire [3:1]\\NLW_two_dec_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED ;\n wire [3:1]\\NLW_two_dec_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED ;\n wire [0:0]\\NLW_two_dec_max_limit_reg[4]_i_1_O_UNCONNECTED ;\n wire [3:1]\\NLW_two_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED ;\n wire [3:2]\\NLW_two_dec_min_limit_reg[11]_i_1_O_UNCONNECTED ;\n wire [3:2]\\NLW_two_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED ;\n wire [3:3]\\NLW_two_inc_max_limit_reg[11]_i_1_O_UNCONNECTED ;\n wire [0:0]\\NLW_two_inc_max_limit_reg[4]_i_1_O_UNCONNECTED ;\n wire [3:1]\\NLW_two_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED ;\n wire [3:2]\\NLW_two_inc_min_limit_reg[11]_i_1_O_UNCONNECTED ;\n\n (* SOFT_HLUTNM = \"soft_lutpair248\" *) \n LUT4 #(\n .INIT(16'h3331)) \n \\calib_sel[1]_i_2 \n (.I0(calib_complete),\n .I1(rstdiv0_sync_r1_reg_rep__25),\n .I2(tempmon_pi_f_inc),\n .I3(tempmon_pi_f_dec),\n .O(\\calib_zero_inputs_reg[1]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair248\" *) \n LUT5 #(\n .INIT(32'h00A800AA)) \n \\calib_sel[3]_i_1 \n (.I0(ctl_lane_sel),\n .I1(tempmon_pi_f_dec),\n .I2(tempmon_pi_f_inc),\n .I3(rstdiv0_sync_r1_reg_rep__25),\n .I4(calib_complete),\n .O(D));\n LUT6 #(\n .INIT(64'h00000200FFFFFFFF)) \n \\calib_zero_inputs[1]_i_1 \n (.I0(cmd_delay_start0),\n .I1(tempmon_pi_f_inc),\n .I2(tempmon_pi_f_dec),\n .I3(delay_done_r4_reg),\n .I4(calib_in_common),\n .I5(\\calib_zero_inputs_reg[1]_0 ),\n .O(\\calib_zero_inputs_reg[1] ));\n FDRE \\device_temp_101_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\device_temp_r_reg[11] [0]),\n .Q(device_temp_101[0]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\device_temp_101_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(\\device_temp_r_reg[11] [10]),\n .Q(device_temp_101[10]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\device_temp_101_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(\\device_temp_r_reg[11] [11]),\n .Q(device_temp_101[11]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\device_temp_101_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\device_temp_r_reg[11] [1]),\n .Q(device_temp_101[1]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\device_temp_101_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\device_temp_r_reg[11] [2]),\n .Q(device_temp_101[2]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\device_temp_101_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\device_temp_r_reg[11] [3]),\n .Q(device_temp_101[3]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\device_temp_101_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\device_temp_r_reg[11] [4]),\n .Q(device_temp_101[4]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\device_temp_101_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\device_temp_r_reg[11] [5]),\n .Q(device_temp_101[5]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\device_temp_101_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\device_temp_r_reg[11] [6]),\n .Q(device_temp_101[6]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\device_temp_101_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\device_temp_r_reg[11] [7]),\n .Q(device_temp_101[7]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\device_temp_101_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(\\device_temp_r_reg[11] [8]),\n .Q(device_temp_101[8]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\device_temp_101_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(\\device_temp_r_reg[11] [9]),\n .Q(device_temp_101[9]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n LUT5 #(\n .INIT(32'h00000800)) \n \\device_temp_init[11]_i_1 \n (.I0(\\device_temp_init[11]_i_2_n_0 ),\n .I1(\\device_temp_init[11]_i_3_n_0 ),\n .I2(tempmon_state[0]),\n .I3(tempmon_state[1]),\n .I4(tempmon_state[2]),\n .O(tempmon_state_init));\n (* SOFT_HLUTNM = \"soft_lutpair254\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\device_temp_init[11]_i_2 \n (.I0(tempmon_state[6]),\n .I1(tempmon_state[5]),\n .I2(tempmon_state[4]),\n .I3(tempmon_state[3]),\n .O(\\device_temp_init[11]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'h0001)) \n \\device_temp_init[11]_i_3 \n (.I0(tempmon_state[10]),\n .I1(tempmon_state[9]),\n .I2(tempmon_state[8]),\n .I3(tempmon_state[7]),\n .O(\\device_temp_init[11]_i_3_n_0 ));\n FDRE \\device_temp_init_reg[0] \n (.C(CLK),\n .CE(tempmon_state_init),\n .D(device_temp_101[0]),\n .Q(device_temp_init[0]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE \\device_temp_init_reg[10] \n (.C(CLK),\n .CE(tempmon_state_init),\n .D(device_temp_101[10]),\n .Q(device_temp_init[10]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE \\device_temp_init_reg[11] \n (.C(CLK),\n .CE(tempmon_state_init),\n .D(device_temp_101[11]),\n .Q(device_temp_init[11]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE \\device_temp_init_reg[1] \n (.C(CLK),\n .CE(tempmon_state_init),\n .D(device_temp_101[1]),\n .Q(device_temp_init[1]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE \\device_temp_init_reg[2] \n (.C(CLK),\n .CE(tempmon_state_init),\n .D(device_temp_101[2]),\n .Q(device_temp_init[2]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE \\device_temp_init_reg[3] \n (.C(CLK),\n .CE(tempmon_state_init),\n .D(device_temp_101[3]),\n .Q(device_temp_init[3]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE \\device_temp_init_reg[4] \n (.C(CLK),\n .CE(tempmon_state_init),\n .D(device_temp_101[4]),\n .Q(device_temp_init[4]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE \\device_temp_init_reg[5] \n (.C(CLK),\n .CE(tempmon_state_init),\n .D(device_temp_101[5]),\n .Q(device_temp_init[5]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE \\device_temp_init_reg[6] \n (.C(CLK),\n .CE(tempmon_state_init),\n .D(device_temp_101[6]),\n .Q(device_temp_init[6]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE \\device_temp_init_reg[7] \n (.C(CLK),\n .CE(tempmon_state_init),\n .D(device_temp_101[7]),\n .Q(device_temp_init[7]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE \\device_temp_init_reg[8] \n (.C(CLK),\n .CE(tempmon_state_init),\n .D(device_temp_101[8]),\n .Q(device_temp_init[8]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE \\device_temp_init_reg[9] \n (.C(CLK),\n .CE(tempmon_state_init),\n .D(device_temp_101[9]),\n .Q(device_temp_init[9]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n LUT1 #(\n .INIT(2'h1)) \n \\four_dec_min_limit[11]_i_2 \n (.I0(three_dec_max_limit[11]),\n .O(\\four_dec_min_limit[11]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\four_dec_min_limit[11]_i_3 \n (.I0(three_dec_max_limit[10]),\n .O(\\four_dec_min_limit[11]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\four_dec_min_limit[5]_i_2 \n (.I0(three_dec_max_limit[5]),\n .O(\\four_dec_min_limit[5]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\four_dec_min_limit[5]_i_3 \n (.I0(three_dec_max_limit[4]),\n .O(\\four_dec_min_limit[5]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\four_dec_min_limit[5]_i_4 \n (.I0(three_dec_max_limit[3]),\n .O(\\four_dec_min_limit[5]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\four_dec_min_limit[5]_i_5 \n (.I0(three_dec_max_limit[2]),\n .O(\\four_dec_min_limit[5]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\four_dec_min_limit[9]_i_2 \n (.I0(three_dec_max_limit[9]),\n .O(\\four_dec_min_limit[9]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\four_dec_min_limit[9]_i_3 \n (.I0(three_dec_max_limit[8]),\n .O(\\four_dec_min_limit[9]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\four_dec_min_limit[9]_i_4 \n (.I0(three_dec_max_limit[7]),\n .O(\\four_dec_min_limit[9]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\four_dec_min_limit[9]_i_5 \n (.I0(three_dec_max_limit[6]),\n .O(\\four_dec_min_limit[9]_i_5_n_0 ));\n FDRE \\four_dec_min_limit_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(three_dec_max_limit[0]),\n .Q(four_dec_min_limit[0]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE \\four_dec_min_limit_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(four_dec_min_limit_nxt[10]),\n .Q(four_dec_min_limit[10]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE \\four_dec_min_limit_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(four_dec_min_limit_nxt[11]),\n .Q(four_dec_min_limit[11]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n CARRY4 \\four_dec_min_limit_reg[11]_i_1 \n (.CI(\\four_dec_min_limit_reg[9]_i_1_n_0 ),\n .CO({\\NLW_four_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\\four_dec_min_limit_reg[11]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,three_dec_max_limit[10]}),\n .O({\\NLW_four_dec_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],four_dec_min_limit_nxt[11:10]}),\n .S({1'b0,1'b0,\\four_dec_min_limit[11]_i_2_n_0 ,\\four_dec_min_limit[11]_i_3_n_0 }));\n FDRE \\four_dec_min_limit_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(three_dec_max_limit[1]),\n .Q(four_dec_min_limit[1]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE \\four_dec_min_limit_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(four_dec_min_limit_nxt[2]),\n .Q(four_dec_min_limit[2]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE \\four_dec_min_limit_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(four_dec_min_limit_nxt[3]),\n .Q(four_dec_min_limit[3]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE \\four_dec_min_limit_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(four_dec_min_limit_nxt[4]),\n .Q(four_dec_min_limit[4]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE \\four_dec_min_limit_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(four_dec_min_limit_nxt[5]),\n .Q(four_dec_min_limit[5]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n CARRY4 \\four_dec_min_limit_reg[5]_i_1 \n (.CI(1'b0),\n .CO({\\four_dec_min_limit_reg[5]_i_1_n_0 ,\\four_dec_min_limit_reg[5]_i_1_n_1 ,\\four_dec_min_limit_reg[5]_i_1_n_2 ,\\four_dec_min_limit_reg[5]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({three_dec_max_limit[5:3],1'b0}),\n .O(four_dec_min_limit_nxt[5:2]),\n .S({\\four_dec_min_limit[5]_i_2_n_0 ,\\four_dec_min_limit[5]_i_3_n_0 ,\\four_dec_min_limit[5]_i_4_n_0 ,\\four_dec_min_limit[5]_i_5_n_0 }));\n FDRE \\four_dec_min_limit_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(four_dec_min_limit_nxt[6]),\n .Q(four_dec_min_limit[6]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE \\four_dec_min_limit_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(four_dec_min_limit_nxt[7]),\n .Q(four_dec_min_limit[7]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE \\four_dec_min_limit_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(four_dec_min_limit_nxt[8]),\n .Q(four_dec_min_limit[8]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE \\four_dec_min_limit_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(four_dec_min_limit_nxt[9]),\n .Q(four_dec_min_limit[9]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n CARRY4 \\four_dec_min_limit_reg[9]_i_1 \n (.CI(\\four_dec_min_limit_reg[5]_i_1_n_0 ),\n .CO({\\four_dec_min_limit_reg[9]_i_1_n_0 ,\\four_dec_min_limit_reg[9]_i_1_n_1 ,\\four_dec_min_limit_reg[9]_i_1_n_2 ,\\four_dec_min_limit_reg[9]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI(three_dec_max_limit[9:6]),\n .O(four_dec_min_limit_nxt[9:6]),\n .S({\\four_dec_min_limit[9]_i_2_n_0 ,\\four_dec_min_limit[9]_i_3_n_0 ,\\four_dec_min_limit[9]_i_4_n_0 ,\\four_dec_min_limit[9]_i_5_n_0 }));\n LUT1 #(\n .INIT(2'h1)) \n \\four_inc_max_limit[11]_i_2 \n (.I0(device_temp_init[11]),\n .O(\\four_inc_max_limit[11]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\four_inc_max_limit[11]_i_3 \n (.I0(device_temp_init[10]),\n .O(\\four_inc_max_limit[11]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\four_inc_max_limit[11]_i_4 \n (.I0(device_temp_init[9]),\n .O(\\four_inc_max_limit[11]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\four_inc_max_limit[1]_i_2 \n (.I0(device_temp_init[1]),\n .O(\\four_inc_max_limit[1]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\four_inc_max_limit[4]_i_2 \n (.I0(device_temp_init[4]),\n .O(\\four_inc_max_limit[4]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\four_inc_max_limit[4]_i_3 \n (.I0(device_temp_init[3]),\n .O(\\four_inc_max_limit[4]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\four_inc_max_limit[4]_i_4 \n (.I0(device_temp_init[2]),\n .O(\\four_inc_max_limit[4]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\four_inc_max_limit[4]_i_5 \n (.I0(device_temp_init[1]),\n .O(\\four_inc_max_limit[4]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\four_inc_max_limit[8]_i_2 \n (.I0(device_temp_init[8]),\n .O(\\four_inc_max_limit[8]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\four_inc_max_limit[8]_i_3 \n (.I0(device_temp_init[7]),\n .O(\\four_inc_max_limit[8]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\four_inc_max_limit[8]_i_4 \n (.I0(device_temp_init[6]),\n .O(\\four_inc_max_limit[8]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\four_inc_max_limit[8]_i_5 \n (.I0(device_temp_init[5]),\n .O(\\four_inc_max_limit[8]_i_5_n_0 ));\n FDRE \\four_inc_max_limit_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(four_inc_max_limit_nxt[10]),\n .Q(four_inc_max_limit[10]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\four_inc_max_limit_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(four_inc_max_limit_nxt[11]),\n .Q(four_inc_max_limit[11]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n CARRY4 \\four_inc_max_limit_reg[11]_i_1 \n (.CI(\\four_inc_max_limit_reg[8]_i_1_n_0 ),\n .CO({\\NLW_four_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\\four_inc_max_limit_reg[11]_i_1_n_2 ,\\four_inc_max_limit_reg[11]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,device_temp_init[10],1'b0}),\n .O({\\NLW_four_inc_max_limit_reg[11]_i_1_O_UNCONNECTED [3],four_inc_max_limit_nxt[11:9]}),\n .S({1'b0,\\four_inc_max_limit[11]_i_2_n_0 ,\\four_inc_max_limit[11]_i_3_n_0 ,\\four_inc_max_limit[11]_i_4_n_0 }));\n FDRE \\four_inc_max_limit_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(four_inc_max_limit_nxt[1]),\n .Q(four_inc_max_limit[1]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n (* XILINX_LEGACY_PRIM = \"(MUXCY,XORCY)\" *) \n CARRY4 \\four_inc_max_limit_reg[1]_i_1_CARRY4 \n (.CI(1'b0),\n .CO(\\NLW_four_inc_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED [3:0]),\n .CYINIT(device_temp_init[0]),\n .DI(\\NLW_four_inc_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED [3:0]),\n .O({\\NLW_four_inc_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED [3:1],four_inc_max_limit_nxt[1]}),\n .S({\\NLW_four_inc_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED [3:1],\\four_inc_max_limit[1]_i_2_n_0 }));\n FDRE \\four_inc_max_limit_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(four_inc_max_limit_nxt[2]),\n .Q(four_inc_max_limit[2]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\four_inc_max_limit_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(four_inc_max_limit_nxt[3]),\n .Q(four_inc_max_limit[3]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\four_inc_max_limit_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(four_inc_max_limit_nxt[4]),\n .Q(four_inc_max_limit[4]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n CARRY4 \\four_inc_max_limit_reg[4]_i_1 \n (.CI(1'b0),\n .CO({\\four_inc_max_limit_reg[4]_i_1_n_0 ,\\four_inc_max_limit_reg[4]_i_1_n_1 ,\\four_inc_max_limit_reg[4]_i_1_n_2 ,\\four_inc_max_limit_reg[4]_i_1_n_3 }),\n .CYINIT(device_temp_init[0]),\n .DI(device_temp_init[4:1]),\n .O({four_inc_max_limit_nxt[4:2],two_inc_max_limit_nxt[1]}),\n .S({\\four_inc_max_limit[4]_i_2_n_0 ,\\four_inc_max_limit[4]_i_3_n_0 ,\\four_inc_max_limit[4]_i_4_n_0 ,\\four_inc_max_limit[4]_i_5_n_0 }));\n FDRE \\four_inc_max_limit_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(four_inc_max_limit_nxt[5]),\n .Q(four_inc_max_limit[5]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\four_inc_max_limit_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(four_inc_max_limit_nxt[6]),\n .Q(four_inc_max_limit[6]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\four_inc_max_limit_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(four_inc_max_limit_nxt[7]),\n .Q(four_inc_max_limit[7]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\four_inc_max_limit_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(four_inc_max_limit_nxt[8]),\n .Q(four_inc_max_limit[8]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n CARRY4 \\four_inc_max_limit_reg[8]_i_1 \n (.CI(\\four_inc_max_limit_reg[4]_i_1_n_0 ),\n .CO({\\four_inc_max_limit_reg[8]_i_1_n_0 ,\\four_inc_max_limit_reg[8]_i_1_n_1 ,\\four_inc_max_limit_reg[8]_i_1_n_2 ,\\four_inc_max_limit_reg[8]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,device_temp_init[7],1'b0,device_temp_init[5]}),\n .O(four_inc_max_limit_nxt[8:5]),\n .S({\\four_inc_max_limit[8]_i_2_n_0 ,\\four_inc_max_limit[8]_i_3_n_0 ,\\four_inc_max_limit[8]_i_4_n_0 ,\\four_inc_max_limit[8]_i_5_n_0 }));\n FDRE \\four_inc_max_limit_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(four_inc_max_limit_nxt[9]),\n .Q(four_inc_max_limit[9]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n (* SOFT_HLUTNM = \"soft_lutpair255\" *) \n LUT4 #(\n .INIT(16'hFE00)) \n \\gen_byte_sel_div1.byte_sel_cnt[2]_i_2 \n (.I0(tempmon_pi_f_inc),\n .I1(tempmon_pi_f_dec),\n .I2(oclkdelay_calib_done_r_reg),\n .I3(ck_addr_cmd_delay_done),\n .O(\\gen_byte_sel_div1.byte_sel_cnt_reg[0] ));\n LUT6 #(\n .INIT(64'hFDFFFDFDFFFFFFFF)) \n \\gen_byte_sel_div1.calib_in_common_i_4 \n (.I0(cmd_delay_start0),\n .I1(tempmon_pi_f_inc),\n .I2(tempmon_pi_f_dec),\n .I3(fine_adjust_done_r_reg),\n .I4(rd_data_offset_cal_done),\n .I5(ck_addr_cmd_delay_done),\n .O(\\gen_byte_sel_div1.calib_in_common_reg ));\n LUT1 #(\n .INIT(2'h2)) \n \\neutral_max_limit[11]_i_2 \n (.I0(device_temp_init[11]),\n .O(\\neutral_max_limit[11]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\neutral_max_limit[11]_i_3 \n (.I0(device_temp_init[10]),\n .O(\\neutral_max_limit[11]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\neutral_max_limit[11]_i_4 \n (.I0(device_temp_init[9]),\n .O(\\neutral_max_limit[11]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\neutral_max_limit[4]_i_2 \n (.I0(device_temp_init[4]),\n .O(\\neutral_max_limit[4]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\neutral_max_limit[4]_i_3 \n (.I0(device_temp_init[3]),\n .O(\\neutral_max_limit[4]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\neutral_max_limit[4]_i_4 \n (.I0(device_temp_init[2]),\n .O(\\neutral_max_limit[4]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\neutral_max_limit[4]_i_5 \n (.I0(device_temp_init[1]),\n .O(\\neutral_max_limit[4]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\neutral_max_limit[8]_i_2 \n (.I0(device_temp_init[8]),\n .O(\\neutral_max_limit[8]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\neutral_max_limit[8]_i_3 \n (.I0(device_temp_init[7]),\n .O(\\neutral_max_limit[8]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\neutral_max_limit[8]_i_4 \n (.I0(device_temp_init[6]),\n .O(\\neutral_max_limit[8]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\neutral_max_limit[8]_i_5 \n (.I0(device_temp_init[5]),\n .O(\\neutral_max_limit[8]_i_5_n_0 ));\n FDRE \\neutral_max_limit_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_max_limit_nxt[10]),\n .Q(neutral_max_limit[10]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE \\neutral_max_limit_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_max_limit_nxt[11]),\n .Q(neutral_max_limit[11]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n CARRY4 \\neutral_max_limit_reg[11]_i_1 \n (.CI(\\neutral_max_limit_reg[8]_i_1_n_0 ),\n .CO({\\NLW_neutral_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\\neutral_max_limit_reg[11]_i_1_n_2 ,\\neutral_max_limit_reg[11]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\NLW_neutral_max_limit_reg[11]_i_1_O_UNCONNECTED [3],neutral_max_limit_nxt[11:9]}),\n .S({1'b0,\\neutral_max_limit[11]_i_2_n_0 ,\\neutral_max_limit[11]_i_3_n_0 ,\\neutral_max_limit[11]_i_4_n_0 }));\n FDRE \\neutral_max_limit_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_max_limit_nxt[1]),\n .Q(neutral_max_limit[1]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n (* XILINX_LEGACY_PRIM = \"(MUXCY,XORCY)\" *) \n CARRY4 \\neutral_max_limit_reg[1]_i_1_CARRY4 \n (.CI(1'b0),\n .CO(\\NLW_neutral_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED [3:0]),\n .CYINIT(device_temp_init[0]),\n .DI(\\NLW_neutral_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED [3:0]),\n .O({\\NLW_neutral_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED [3:1],neutral_max_limit_nxt[1]}),\n .S({\\NLW_neutral_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED [3:1],\\four_inc_max_limit[1]_i_2_n_0 }));\n FDRE \\neutral_max_limit_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_max_limit_nxt[2]),\n .Q(neutral_max_limit[2]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE \\neutral_max_limit_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_max_limit_nxt[3]),\n .Q(neutral_max_limit[3]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE \\neutral_max_limit_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_max_limit_nxt[4]),\n .Q(neutral_max_limit[4]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n CARRY4 \\neutral_max_limit_reg[4]_i_1 \n (.CI(1'b0),\n .CO({\\neutral_max_limit_reg[4]_i_1_n_0 ,\\neutral_max_limit_reg[4]_i_1_n_1 ,\\neutral_max_limit_reg[4]_i_1_n_2 ,\\neutral_max_limit_reg[4]_i_1_n_3 }),\n .CYINIT(device_temp_init[0]),\n .DI({device_temp_init[4],1'b0,device_temp_init[2:1]}),\n .O({neutral_max_limit_nxt[4:2],\\NLW_neutral_max_limit_reg[4]_i_1_O_UNCONNECTED [0]}),\n .S({\\neutral_max_limit[4]_i_2_n_0 ,\\neutral_max_limit[4]_i_3_n_0 ,\\neutral_max_limit[4]_i_4_n_0 ,\\neutral_max_limit[4]_i_5_n_0 }));\n FDRE \\neutral_max_limit_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_max_limit_nxt[5]),\n .Q(neutral_max_limit[5]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE \\neutral_max_limit_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_max_limit_nxt[6]),\n .Q(neutral_max_limit[6]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE \\neutral_max_limit_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_max_limit_nxt[7]),\n .Q(neutral_max_limit[7]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE \\neutral_max_limit_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_max_limit_nxt[8]),\n .Q(neutral_max_limit[8]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n CARRY4 \\neutral_max_limit_reg[8]_i_1 \n (.CI(\\neutral_max_limit_reg[4]_i_1_n_0 ),\n .CO({\\neutral_max_limit_reg[8]_i_1_n_0 ,\\neutral_max_limit_reg[8]_i_1_n_1 ,\\neutral_max_limit_reg[8]_i_1_n_2 ,\\neutral_max_limit_reg[8]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,device_temp_init[6:5]}),\n .O(neutral_max_limit_nxt[8:5]),\n .S({\\neutral_max_limit[8]_i_2_n_0 ,\\neutral_max_limit[8]_i_3_n_0 ,\\neutral_max_limit[8]_i_4_n_0 ,\\neutral_max_limit[8]_i_5_n_0 }));\n FDRE \\neutral_max_limit_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_max_limit_nxt[9]),\n .Q(neutral_max_limit[9]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n LUT1 #(\n .INIT(2'h1)) \n \\neutral_min_limit[11]_i_2 \n (.I0(one_inc_max_limit[11]),\n .O(\\neutral_min_limit[11]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\neutral_min_limit[11]_i_3 \n (.I0(one_inc_max_limit[10]),\n .O(\\neutral_min_limit[11]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\neutral_min_limit[5]_i_2 \n (.I0(one_inc_max_limit[5]),\n .O(\\neutral_min_limit[5]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\neutral_min_limit[5]_i_3 \n (.I0(one_inc_max_limit[4]),\n .O(\\neutral_min_limit[5]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\neutral_min_limit[5]_i_4 \n (.I0(one_inc_max_limit[3]),\n .O(\\neutral_min_limit[5]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\neutral_min_limit[5]_i_5 \n (.I0(one_inc_max_limit[2]),\n .O(\\neutral_min_limit[5]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\neutral_min_limit[9]_i_2 \n (.I0(one_inc_max_limit[9]),\n .O(\\neutral_min_limit[9]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\neutral_min_limit[9]_i_3 \n (.I0(one_inc_max_limit[8]),\n .O(\\neutral_min_limit[9]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\neutral_min_limit[9]_i_4 \n (.I0(one_inc_max_limit[7]),\n .O(\\neutral_min_limit[9]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\neutral_min_limit[9]_i_5 \n (.I0(one_inc_max_limit[6]),\n .O(\\neutral_min_limit[9]_i_5_n_0 ));\n FDRE \\neutral_min_limit_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_min_limit_nxt[10]),\n .Q(neutral_min_limit[10]),\n .R(SS));\n FDRE \\neutral_min_limit_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_min_limit_nxt[11]),\n .Q(neutral_min_limit[11]),\n .R(SS));\n CARRY4 \\neutral_min_limit_reg[11]_i_1 \n (.CI(\\neutral_min_limit_reg[9]_i_1_n_0 ),\n .CO({\\NLW_neutral_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\\neutral_min_limit_reg[11]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,one_inc_max_limit[10]}),\n .O({\\NLW_neutral_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],neutral_min_limit_nxt[11:10]}),\n .S({1'b0,1'b0,\\neutral_min_limit[11]_i_2_n_0 ,\\neutral_min_limit[11]_i_3_n_0 }));\n FDRE \\neutral_min_limit_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_max_limit[1]),\n .Q(neutral_min_limit[1]),\n .R(SS));\n FDRE \\neutral_min_limit_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_min_limit_nxt[2]),\n .Q(neutral_min_limit[2]),\n .R(SS));\n FDRE \\neutral_min_limit_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_min_limit_nxt[3]),\n .Q(neutral_min_limit[3]),\n .R(SS));\n FDRE \\neutral_min_limit_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_min_limit_nxt[4]),\n .Q(neutral_min_limit[4]),\n .R(SS));\n FDRE \\neutral_min_limit_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_min_limit_nxt[5]),\n .Q(neutral_min_limit[5]),\n .R(SS));\n CARRY4 \\neutral_min_limit_reg[5]_i_1 \n (.CI(1'b0),\n .CO({\\neutral_min_limit_reg[5]_i_1_n_0 ,\\neutral_min_limit_reg[5]_i_1_n_1 ,\\neutral_min_limit_reg[5]_i_1_n_2 ,\\neutral_min_limit_reg[5]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({one_inc_max_limit[5:3],1'b0}),\n .O(neutral_min_limit_nxt[5:2]),\n .S({\\neutral_min_limit[5]_i_2_n_0 ,\\neutral_min_limit[5]_i_3_n_0 ,\\neutral_min_limit[5]_i_4_n_0 ,\\neutral_min_limit[5]_i_5_n_0 }));\n FDRE \\neutral_min_limit_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_min_limit_nxt[6]),\n .Q(neutral_min_limit[6]),\n .R(SS));\n FDRE \\neutral_min_limit_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_min_limit_nxt[7]),\n .Q(neutral_min_limit[7]),\n .R(SS));\n FDRE \\neutral_min_limit_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_min_limit_nxt[8]),\n .Q(neutral_min_limit[8]),\n .R(SS));\n FDRE \\neutral_min_limit_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_min_limit_nxt[9]),\n .Q(neutral_min_limit[9]),\n .R(SS));\n CARRY4 \\neutral_min_limit_reg[9]_i_1 \n (.CI(\\neutral_min_limit_reg[5]_i_1_n_0 ),\n .CO({\\neutral_min_limit_reg[9]_i_1_n_0 ,\\neutral_min_limit_reg[9]_i_1_n_1 ,\\neutral_min_limit_reg[9]_i_1_n_2 ,\\neutral_min_limit_reg[9]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI(one_inc_max_limit[9:6]),\n .O(neutral_min_limit_nxt[9:6]),\n .S({\\neutral_min_limit[9]_i_2_n_0 ,\\neutral_min_limit[9]_i_3_n_0 ,\\neutral_min_limit[9]_i_4_n_0 ,\\neutral_min_limit[9]_i_5_n_0 }));\n LUT1 #(\n .INIT(2'h2)) \n \\one_dec_max_limit[11]_i_2 \n (.I0(device_temp_init[11]),\n .O(\\one_dec_max_limit[11]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\one_dec_max_limit[11]_i_3 \n (.I0(device_temp_init[10]),\n .O(\\one_dec_max_limit[11]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\one_dec_max_limit[11]_i_4 \n (.I0(device_temp_init[9]),\n .O(\\one_dec_max_limit[11]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\one_dec_max_limit[4]_i_2 \n (.I0(device_temp_init[4]),\n .O(\\one_dec_max_limit[4]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\one_dec_max_limit[4]_i_3 \n (.I0(device_temp_init[3]),\n .O(\\one_dec_max_limit[4]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_dec_max_limit[4]_i_4 \n (.I0(device_temp_init[2]),\n .O(\\one_dec_max_limit[4]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\one_dec_max_limit[4]_i_5 \n (.I0(device_temp_init[1]),\n .O(\\one_dec_max_limit[4]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_dec_max_limit[8]_i_2 \n (.I0(device_temp_init[8]),\n .O(\\one_dec_max_limit[8]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\one_dec_max_limit[8]_i_3 \n (.I0(device_temp_init[7]),\n .O(\\one_dec_max_limit[8]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_dec_max_limit[8]_i_4 \n (.I0(device_temp_init[6]),\n .O(\\one_dec_max_limit[8]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_dec_max_limit[8]_i_5 \n (.I0(device_temp_init[5]),\n .O(\\one_dec_max_limit[8]_i_5_n_0 ));\n FDRE \\one_dec_max_limit_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_max_limit_nxt[10]),\n .Q(one_dec_max_limit[10]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE \\one_dec_max_limit_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_max_limit_nxt[11]),\n .Q(one_dec_max_limit[11]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n CARRY4 \\one_dec_max_limit_reg[11]_i_1 \n (.CI(\\one_dec_max_limit_reg[8]_i_1_n_0 ),\n .CO({\\NLW_one_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\\one_dec_max_limit_reg[11]_i_1_n_2 ,\\one_dec_max_limit_reg[11]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\NLW_one_dec_max_limit_reg[11]_i_1_O_UNCONNECTED [3],one_dec_max_limit_nxt[11:9]}),\n .S({1'b0,\\one_dec_max_limit[11]_i_2_n_0 ,\\one_dec_max_limit[11]_i_3_n_0 ,\\one_dec_max_limit[11]_i_4_n_0 }));\n FDRE \\one_dec_max_limit_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_max_limit_nxt[1]),\n .Q(one_dec_max_limit[1]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n (* XILINX_LEGACY_PRIM = \"(MUXCY,XORCY)\" *) \n CARRY4 \\one_dec_max_limit_reg[1]_i_1_CARRY4 \n (.CI(1'b0),\n .CO(\\NLW_one_dec_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED [3:0]),\n .CYINIT(device_temp_init[0]),\n .DI(\\NLW_one_dec_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED [3:0]),\n .O({\\NLW_one_dec_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED [3:1],one_dec_max_limit_nxt[1]}),\n .S({\\NLW_one_dec_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED [3:1],device_temp_init[1]}));\n FDRE \\one_dec_max_limit_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_max_limit_nxt[2]),\n .Q(one_dec_max_limit[2]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE \\one_dec_max_limit_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_max_limit_nxt[3]),\n .Q(one_dec_max_limit[3]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE \\one_dec_max_limit_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_max_limit_nxt[4]),\n .Q(one_dec_max_limit[4]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n CARRY4 \\one_dec_max_limit_reg[4]_i_1 \n (.CI(1'b0),\n .CO({\\one_dec_max_limit_reg[4]_i_1_n_0 ,\\one_dec_max_limit_reg[4]_i_1_n_1 ,\\one_dec_max_limit_reg[4]_i_1_n_2 ,\\one_dec_max_limit_reg[4]_i_1_n_3 }),\n .CYINIT(device_temp_init[0]),\n .DI({1'b0,1'b0,device_temp_init[2],1'b0}),\n .O({one_dec_max_limit_nxt[4:2],\\NLW_one_dec_max_limit_reg[4]_i_1_O_UNCONNECTED [0]}),\n .S({\\one_dec_max_limit[4]_i_2_n_0 ,\\one_dec_max_limit[4]_i_3_n_0 ,\\one_dec_max_limit[4]_i_4_n_0 ,\\one_dec_max_limit[4]_i_5_n_0 }));\n FDRE \\one_dec_max_limit_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_max_limit_nxt[5]),\n .Q(one_dec_max_limit[5]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE \\one_dec_max_limit_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_max_limit_nxt[6]),\n .Q(one_dec_max_limit[6]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE \\one_dec_max_limit_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_max_limit_nxt[7]),\n .Q(one_dec_max_limit[7]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE \\one_dec_max_limit_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_max_limit_nxt[8]),\n .Q(one_dec_max_limit[8]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n CARRY4 \\one_dec_max_limit_reg[8]_i_1 \n (.CI(\\one_dec_max_limit_reg[4]_i_1_n_0 ),\n .CO({\\one_dec_max_limit_reg[8]_i_1_n_0 ,\\one_dec_max_limit_reg[8]_i_1_n_1 ,\\one_dec_max_limit_reg[8]_i_1_n_2 ,\\one_dec_max_limit_reg[8]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({device_temp_init[8],1'b0,device_temp_init[6:5]}),\n .O(one_dec_max_limit_nxt[8:5]),\n .S({\\one_dec_max_limit[8]_i_2_n_0 ,\\one_dec_max_limit[8]_i_3_n_0 ,\\one_dec_max_limit[8]_i_4_n_0 ,\\one_dec_max_limit[8]_i_5_n_0 }));\n FDRE \\one_dec_max_limit_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_max_limit_nxt[9]),\n .Q(one_dec_max_limit[9]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n LUT1 #(\n .INIT(2'h1)) \n \\one_dec_min_limit[11]_i_2 \n (.I0(neutral_max_limit[11]),\n .O(\\one_dec_min_limit[11]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_dec_min_limit[11]_i_3 \n (.I0(neutral_max_limit[10]),\n .O(\\one_dec_min_limit[11]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_dec_min_limit[5]_i_2 \n (.I0(neutral_max_limit[5]),\n .O(\\one_dec_min_limit[5]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_dec_min_limit[5]_i_3 \n (.I0(neutral_max_limit[4]),\n .O(\\one_dec_min_limit[5]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_dec_min_limit[5]_i_4 \n (.I0(neutral_max_limit[3]),\n .O(\\one_dec_min_limit[5]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\one_dec_min_limit[5]_i_5 \n (.I0(neutral_max_limit[2]),\n .O(\\one_dec_min_limit[5]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_dec_min_limit[9]_i_2 \n (.I0(neutral_max_limit[9]),\n .O(\\one_dec_min_limit[9]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_dec_min_limit[9]_i_3 \n (.I0(neutral_max_limit[8]),\n .O(\\one_dec_min_limit[9]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_dec_min_limit[9]_i_4 \n (.I0(neutral_max_limit[7]),\n .O(\\one_dec_min_limit[9]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_dec_min_limit[9]_i_5 \n (.I0(neutral_max_limit[6]),\n .O(\\one_dec_min_limit[9]_i_5_n_0 ));\n FDRE \\one_dec_min_limit_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_min_limit_nxt[10]),\n .Q(one_dec_min_limit[10]),\n .R(SS));\n FDRE \\one_dec_min_limit_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_min_limit_nxt[11]),\n .Q(one_dec_min_limit[11]),\n .R(SS));\n CARRY4 \\one_dec_min_limit_reg[11]_i_1 \n (.CI(\\one_dec_min_limit_reg[9]_i_1_n_0 ),\n .CO({\\NLW_one_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\\one_dec_min_limit_reg[11]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,neutral_max_limit[10]}),\n .O({\\NLW_one_dec_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],one_dec_min_limit_nxt[11:10]}),\n .S({1'b0,1'b0,\\one_dec_min_limit[11]_i_2_n_0 ,\\one_dec_min_limit[11]_i_3_n_0 }));\n FDRE \\one_dec_min_limit_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(neutral_max_limit[1]),\n .Q(one_dec_min_limit[1]),\n .R(SS));\n FDRE \\one_dec_min_limit_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_min_limit_nxt[2]),\n .Q(one_dec_min_limit[2]),\n .R(SS));\n FDRE \\one_dec_min_limit_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_min_limit_nxt[3]),\n .Q(one_dec_min_limit[3]),\n .R(SS));\n FDRE \\one_dec_min_limit_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_min_limit_nxt[4]),\n .Q(one_dec_min_limit[4]),\n .R(SS));\n FDRE \\one_dec_min_limit_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_min_limit_nxt[5]),\n .Q(one_dec_min_limit[5]),\n .R(SS));\n CARRY4 \\one_dec_min_limit_reg[5]_i_1 \n (.CI(1'b0),\n .CO({\\one_dec_min_limit_reg[5]_i_1_n_0 ,\\one_dec_min_limit_reg[5]_i_1_n_1 ,\\one_dec_min_limit_reg[5]_i_1_n_2 ,\\one_dec_min_limit_reg[5]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({neutral_max_limit[5:3],1'b0}),\n .O(one_dec_min_limit_nxt[5:2]),\n .S({\\one_dec_min_limit[5]_i_2_n_0 ,\\one_dec_min_limit[5]_i_3_n_0 ,\\one_dec_min_limit[5]_i_4_n_0 ,\\one_dec_min_limit[5]_i_5_n_0 }));\n FDRE \\one_dec_min_limit_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_min_limit_nxt[6]),\n .Q(one_dec_min_limit[6]),\n .R(SS));\n FDRE \\one_dec_min_limit_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_min_limit_nxt[7]),\n .Q(one_dec_min_limit[7]),\n .R(SS));\n FDRE \\one_dec_min_limit_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_min_limit_nxt[8]),\n .Q(one_dec_min_limit[8]),\n .R(SS));\n FDRE \\one_dec_min_limit_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_min_limit_nxt[9]),\n .Q(one_dec_min_limit[9]),\n .R(SS));\n CARRY4 \\one_dec_min_limit_reg[9]_i_1 \n (.CI(\\one_dec_min_limit_reg[5]_i_1_n_0 ),\n .CO({\\one_dec_min_limit_reg[9]_i_1_n_0 ,\\one_dec_min_limit_reg[9]_i_1_n_1 ,\\one_dec_min_limit_reg[9]_i_1_n_2 ,\\one_dec_min_limit_reg[9]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI(neutral_max_limit[9:6]),\n .O(one_dec_min_limit_nxt[9:6]),\n .S({\\one_dec_min_limit[9]_i_2_n_0 ,\\one_dec_min_limit[9]_i_3_n_0 ,\\one_dec_min_limit[9]_i_4_n_0 ,\\one_dec_min_limit[9]_i_5_n_0 }));\n LUT1 #(\n .INIT(2'h1)) \n \\one_inc_max_limit[11]_i_2 \n (.I0(device_temp_init[11]),\n .O(\\one_inc_max_limit[11]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_inc_max_limit[11]_i_3 \n (.I0(device_temp_init[10]),\n .O(\\one_inc_max_limit[11]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_inc_max_limit[11]_i_4 \n (.I0(device_temp_init[9]),\n .O(\\one_inc_max_limit[11]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\one_inc_max_limit[4]_i_2 \n (.I0(device_temp_init[4]),\n .O(\\one_inc_max_limit[4]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_inc_max_limit[4]_i_3 \n (.I0(device_temp_init[3]),\n .O(\\one_inc_max_limit[4]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\one_inc_max_limit[4]_i_4 \n (.I0(device_temp_init[2]),\n .O(\\one_inc_max_limit[4]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\one_inc_max_limit[4]_i_5 \n (.I0(device_temp_init[1]),\n .O(\\one_inc_max_limit[4]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_inc_max_limit[8]_i_2 \n (.I0(device_temp_init[8]),\n .O(\\one_inc_max_limit[8]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_inc_max_limit[8]_i_3 \n (.I0(device_temp_init[7]),\n .O(\\one_inc_max_limit[8]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\one_inc_max_limit[8]_i_4 \n (.I0(device_temp_init[6]),\n .O(\\one_inc_max_limit[8]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\one_inc_max_limit[8]_i_5 \n (.I0(device_temp_init[5]),\n .O(\\one_inc_max_limit[8]_i_5_n_0 ));\n FDRE \\one_inc_max_limit_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_max_limit_nxt[10]),\n .Q(one_inc_max_limit[10]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE \\one_inc_max_limit_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_max_limit_nxt[11]),\n .Q(one_inc_max_limit[11]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n CARRY4 \\one_inc_max_limit_reg[11]_i_1 \n (.CI(\\one_inc_max_limit_reg[8]_i_1_n_0 ),\n .CO({\\NLW_one_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\\one_inc_max_limit_reg[11]_i_1_n_2 ,\\one_inc_max_limit_reg[11]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,device_temp_init[10:9]}),\n .O({\\NLW_one_inc_max_limit_reg[11]_i_1_O_UNCONNECTED [3],one_inc_max_limit_nxt[11:9]}),\n .S({1'b0,\\one_inc_max_limit[11]_i_2_n_0 ,\\one_inc_max_limit[11]_i_3_n_0 ,\\one_inc_max_limit[11]_i_4_n_0 }));\n FDRE \\one_inc_max_limit_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_max_limit_nxt[1]),\n .Q(one_inc_max_limit[1]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n (* XILINX_LEGACY_PRIM = \"(MUXCY,XORCY)\" *) \n CARRY4 \\one_inc_max_limit_reg[1]_i_1_CARRY4 \n (.CI(1'b0),\n .CO(\\NLW_one_inc_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED [3:0]),\n .CYINIT(device_temp_init[0]),\n .DI(\\NLW_one_inc_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED [3:0]),\n .O({\\NLW_one_inc_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED [3:1],one_inc_max_limit_nxt[1]}),\n .S({\\NLW_one_inc_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED [3:1],device_temp_init[1]}));\n FDRE \\one_inc_max_limit_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_max_limit_nxt[2]),\n .Q(one_inc_max_limit[2]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE \\one_inc_max_limit_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_max_limit_nxt[3]),\n .Q(one_inc_max_limit[3]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE \\one_inc_max_limit_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_max_limit_nxt[4]),\n .Q(one_inc_max_limit[4]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n CARRY4 \\one_inc_max_limit_reg[4]_i_1 \n (.CI(1'b0),\n .CO({\\one_inc_max_limit_reg[4]_i_1_n_0 ,\\one_inc_max_limit_reg[4]_i_1_n_1 ,\\one_inc_max_limit_reg[4]_i_1_n_2 ,\\one_inc_max_limit_reg[4]_i_1_n_3 }),\n .CYINIT(device_temp_init[0]),\n .DI({1'b0,device_temp_init[3],1'b0,1'b0}),\n .O({one_inc_max_limit_nxt[4:2],\\NLW_one_inc_max_limit_reg[4]_i_1_O_UNCONNECTED [0]}),\n .S({\\one_inc_max_limit[4]_i_2_n_0 ,\\one_inc_max_limit[4]_i_3_n_0 ,\\one_inc_max_limit[4]_i_4_n_0 ,\\one_inc_max_limit[4]_i_5_n_0 }));\n FDRE \\one_inc_max_limit_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_max_limit_nxt[5]),\n .Q(one_inc_max_limit[5]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE \\one_inc_max_limit_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_max_limit_nxt[6]),\n .Q(one_inc_max_limit[6]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE \\one_inc_max_limit_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_max_limit_nxt[7]),\n .Q(one_inc_max_limit[7]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE \\one_inc_max_limit_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_max_limit_nxt[8]),\n .Q(one_inc_max_limit[8]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n CARRY4 \\one_inc_max_limit_reg[8]_i_1 \n (.CI(\\one_inc_max_limit_reg[4]_i_1_n_0 ),\n .CO({\\one_inc_max_limit_reg[8]_i_1_n_0 ,\\one_inc_max_limit_reg[8]_i_1_n_1 ,\\one_inc_max_limit_reg[8]_i_1_n_2 ,\\one_inc_max_limit_reg[8]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({device_temp_init[8:7],1'b0,1'b0}),\n .O(one_inc_max_limit_nxt[8:5]),\n .S({\\one_inc_max_limit[8]_i_2_n_0 ,\\one_inc_max_limit[8]_i_3_n_0 ,\\one_inc_max_limit[8]_i_4_n_0 ,\\one_inc_max_limit[8]_i_5_n_0 }));\n FDRE \\one_inc_max_limit_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_max_limit_nxt[9]),\n .Q(one_inc_max_limit[9]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n LUT1 #(\n .INIT(2'h1)) \n \\one_inc_min_limit[11]_i_2 \n (.I0(two_inc_max_limit[11]),\n .O(\\one_inc_min_limit[11]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_inc_min_limit[11]_i_3 \n (.I0(two_inc_max_limit[10]),\n .O(\\one_inc_min_limit[11]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_inc_min_limit[5]_i_2 \n (.I0(two_inc_max_limit[5]),\n .O(\\one_inc_min_limit[5]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_inc_min_limit[5]_i_3 \n (.I0(two_inc_max_limit[4]),\n .O(\\one_inc_min_limit[5]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_inc_min_limit[5]_i_4 \n (.I0(two_inc_max_limit[3]),\n .O(\\one_inc_min_limit[5]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\one_inc_min_limit[5]_i_5 \n (.I0(two_inc_max_limit[2]),\n .O(\\one_inc_min_limit[5]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_inc_min_limit[9]_i_2 \n (.I0(two_inc_max_limit[9]),\n .O(\\one_inc_min_limit[9]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_inc_min_limit[9]_i_3 \n (.I0(two_inc_max_limit[8]),\n .O(\\one_inc_min_limit[9]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_inc_min_limit[9]_i_4 \n (.I0(two_inc_max_limit[7]),\n .O(\\one_inc_min_limit[9]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\one_inc_min_limit[9]_i_5 \n (.I0(two_inc_max_limit[6]),\n .O(\\one_inc_min_limit[9]_i_5_n_0 ));\n FDRE \\one_inc_min_limit_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_min_limit_nxt[10]),\n .Q(one_inc_min_limit[10]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE \\one_inc_min_limit_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_min_limit_nxt[11]),\n .Q(one_inc_min_limit[11]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n CARRY4 \\one_inc_min_limit_reg[11]_i_1 \n (.CI(\\one_inc_min_limit_reg[9]_i_1_n_0 ),\n .CO({\\NLW_one_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\\one_inc_min_limit_reg[11]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,two_inc_max_limit[10]}),\n .O({\\NLW_one_inc_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],one_inc_min_limit_nxt[11:10]}),\n .S({1'b0,1'b0,\\one_inc_min_limit[11]_i_2_n_0 ,\\one_inc_min_limit[11]_i_3_n_0 }));\n FDRE \\one_inc_min_limit_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_max_limit[1]),\n .Q(one_inc_min_limit[1]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE \\one_inc_min_limit_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_min_limit_nxt[2]),\n .Q(one_inc_min_limit[2]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE \\one_inc_min_limit_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_min_limit_nxt[3]),\n .Q(one_inc_min_limit[3]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE \\one_inc_min_limit_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_min_limit_nxt[4]),\n .Q(one_inc_min_limit[4]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE \\one_inc_min_limit_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_min_limit_nxt[5]),\n .Q(one_inc_min_limit[5]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n CARRY4 \\one_inc_min_limit_reg[5]_i_1 \n (.CI(1'b0),\n .CO({\\one_inc_min_limit_reg[5]_i_1_n_0 ,\\one_inc_min_limit_reg[5]_i_1_n_1 ,\\one_inc_min_limit_reg[5]_i_1_n_2 ,\\one_inc_min_limit_reg[5]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({two_inc_max_limit[5:3],1'b0}),\n .O(one_inc_min_limit_nxt[5:2]),\n .S({\\one_inc_min_limit[5]_i_2_n_0 ,\\one_inc_min_limit[5]_i_3_n_0 ,\\one_inc_min_limit[5]_i_4_n_0 ,\\one_inc_min_limit[5]_i_5_n_0 }));\n FDRE \\one_inc_min_limit_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_min_limit_nxt[6]),\n .Q(one_inc_min_limit[6]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE \\one_inc_min_limit_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_min_limit_nxt[7]),\n .Q(one_inc_min_limit[7]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE \\one_inc_min_limit_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_min_limit_nxt[8]),\n .Q(one_inc_min_limit[8]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE \\one_inc_min_limit_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(one_inc_min_limit_nxt[9]),\n .Q(one_inc_min_limit[9]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n CARRY4 \\one_inc_min_limit_reg[9]_i_1 \n (.CI(\\one_inc_min_limit_reg[5]_i_1_n_0 ),\n .CO({\\one_inc_min_limit_reg[9]_i_1_n_0 ,\\one_inc_min_limit_reg[9]_i_1_n_1 ,\\one_inc_min_limit_reg[9]_i_1_n_2 ,\\one_inc_min_limit_reg[9]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI(two_inc_max_limit[9:6]),\n .O(one_inc_min_limit_nxt[9:6]),\n .S({\\one_inc_min_limit[9]_i_2_n_0 ,\\one_inc_min_limit[9]_i_3_n_0 ,\\one_inc_min_limit[9]_i_4_n_0 ,\\one_inc_min_limit[9]_i_5_n_0 }));\n LUT4 #(\n .INIT(16'hF080)) \n pi_f_dec_i_1\n (.I0(update_temp_102),\n .I1(pi_f_dec_i_2_n_0),\n .I2(\\tempmon_state[10]_i_7_n_0 ),\n .I3(\\tempmon_state[10]_i_3_n_0 ),\n .O(pi_f_dec_nxt));\n LUT6 #(\n .INIT(64'hFFFFF888F888F888)) \n pi_f_dec_i_2\n (.I0(temp_cmp_three_inc_max_102),\n .I1(tempmon_state[3]),\n .I2(tempmon_state[5]),\n .I3(temp_cmp_one_inc_max_102),\n .I4(tempmon_state[4]),\n .I5(temp_cmp_two_inc_max_102),\n .O(pi_f_dec_i_2_n_0));\n FDRE pi_f_dec_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_f_dec_nxt),\n .Q(tempmon_pi_f_dec),\n .R(SS));\n LUT6 #(\n .INIT(64'hEFEEEEEEEEEEEEEE)) \n pi_f_inc_i_1\n (.I0(pi_f_inc_i_2_n_0),\n .I1(pi_f_inc_i_3_n_0),\n .I2(temp_gte_three_dec_max),\n .I3(tempmon_state[9]),\n .I4(temp_cmp_three_dec_min_102),\n .I5(pi_f_inc_i_5_n_0),\n .O(pi_f_inc_nxt));\n LUT4 #(\n .INIT(16'h0800)) \n pi_f_inc_i_10\n (.I0(tempmon_state[5]),\n .I1(update_temp_102),\n .I2(temp_cmp_one_inc_max_102),\n .I3(temp_cmp_one_inc_min_102),\n .O(pi_f_inc_i_10_n_0));\n LUT6 #(\n .INIT(64'hFAEAEAEAEAEAEAEA)) \n pi_f_inc_i_2\n (.I0(pi_f_inc_i_6_n_0),\n .I1(pi_f_inc_i_7_n_0),\n .I2(\\tempmon_state[10]_i_7_n_0 ),\n .I3(tempmon_state[10]),\n .I4(temp_cmp_four_dec_min_102),\n .I5(update_temp_102),\n .O(pi_f_inc_i_2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair253\" *) \n LUT5 #(\n .INIT(32'h40000000)) \n pi_f_inc_i_3\n (.I0(temp_cmp_two_dec_max_102),\n .I1(tempmon_state[8]),\n .I2(temp_cmp_two_dec_min_102),\n .I3(update_temp_102),\n .I4(\\tempmon_state[10]_i_7_n_0 ),\n .O(pi_f_inc_i_3_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair252\" *) \n LUT2 #(\n .INIT(4'h8)) \n pi_f_inc_i_4\n (.I0(update_temp_102),\n .I1(temp_cmp_three_dec_max_102),\n .O(temp_gte_three_dec_max));\n (* SOFT_HLUTNM = \"soft_lutpair249\" *) \n LUT2 #(\n .INIT(4'h8)) \n pi_f_inc_i_5\n (.I0(\\tempmon_state[10]_i_7_n_0 ),\n .I1(update_temp_102),\n .O(pi_f_inc_i_5_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFF00008000)) \n pi_f_inc_i_6\n (.I0(\\tempmon_state[10]_i_7_n_0 ),\n .I1(update_temp_102),\n .I2(temp_cmp_one_dec_min_102),\n .I3(tempmon_state[7]),\n .I4(temp_cmp_one_dec_max_102),\n .I5(pi_f_inc_i_8_n_0),\n .O(pi_f_inc_i_6_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFFAAEAAAAA)) \n pi_f_inc_i_7\n (.I0(pi_f_inc_i_9_n_0),\n .I1(tempmon_state[4]),\n .I2(update_temp_102),\n .I3(temp_cmp_two_inc_max_102),\n .I4(temp_cmp_two_inc_min_102),\n .I5(pi_f_inc_i_10_n_0),\n .O(pi_f_inc_i_7_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair250\" *) \n LUT5 #(\n .INIT(32'h40000000)) \n pi_f_inc_i_8\n (.I0(temp_cmp_neutral_max_102),\n .I1(tempmon_state[6]),\n .I2(temp_cmp_neutral_min_102),\n .I3(update_temp_102),\n .I4(\\tempmon_state[10]_i_7_n_0 ),\n .O(pi_f_inc_i_8_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair256\" *) \n LUT4 #(\n .INIT(16'h0800)) \n pi_f_inc_i_9\n (.I0(tempmon_state[3]),\n .I1(update_temp_102),\n .I2(temp_cmp_three_inc_max_102),\n .I3(temp_cmp_three_inc_min_102),\n .O(pi_f_inc_i_9_n_0));\n FDRE pi_f_inc_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pi_f_inc_nxt),\n .Q(tempmon_pi_f_inc),\n .R(rstdiv0_sync_r1_reg_rep__2));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_four_dec_min_102_i_10\n (.I0(four_dec_min_limit[0]),\n .I1(device_temp_101[0]),\n .I2(device_temp_101[1]),\n .I3(four_dec_min_limit[1]),\n .O(temp_cmp_four_dec_min_102_i_10_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_four_dec_min_102_i_11\n (.I0(four_dec_min_limit[6]),\n .I1(device_temp_101[6]),\n .I2(four_dec_min_limit[7]),\n .I3(device_temp_101[7]),\n .O(temp_cmp_four_dec_min_102_i_11_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_four_dec_min_102_i_12\n (.I0(four_dec_min_limit[4]),\n .I1(device_temp_101[4]),\n .I2(four_dec_min_limit[5]),\n .I3(device_temp_101[5]),\n .O(temp_cmp_four_dec_min_102_i_12_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_four_dec_min_102_i_13\n (.I0(four_dec_min_limit[2]),\n .I1(device_temp_101[2]),\n .I2(four_dec_min_limit[3]),\n .I3(device_temp_101[3]),\n .O(temp_cmp_four_dec_min_102_i_13_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_four_dec_min_102_i_14\n (.I0(four_dec_min_limit[0]),\n .I1(device_temp_101[0]),\n .I2(four_dec_min_limit[1]),\n .I3(device_temp_101[1]),\n .O(temp_cmp_four_dec_min_102_i_14_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_four_dec_min_102_i_3\n (.I0(four_dec_min_limit[10]),\n .I1(device_temp_101[10]),\n .I2(device_temp_101[11]),\n .I3(four_dec_min_limit[11]),\n .O(temp_cmp_four_dec_min_102_i_3_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_four_dec_min_102_i_4\n (.I0(four_dec_min_limit[8]),\n .I1(device_temp_101[8]),\n .I2(device_temp_101[9]),\n .I3(four_dec_min_limit[9]),\n .O(temp_cmp_four_dec_min_102_i_4_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_four_dec_min_102_i_5\n (.I0(four_dec_min_limit[10]),\n .I1(device_temp_101[10]),\n .I2(four_dec_min_limit[11]),\n .I3(device_temp_101[11]),\n .O(temp_cmp_four_dec_min_102_i_5_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_four_dec_min_102_i_6\n (.I0(four_dec_min_limit[8]),\n .I1(device_temp_101[8]),\n .I2(four_dec_min_limit[9]),\n .I3(device_temp_101[9]),\n .O(temp_cmp_four_dec_min_102_i_6_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_four_dec_min_102_i_7\n (.I0(four_dec_min_limit[6]),\n .I1(device_temp_101[6]),\n .I2(device_temp_101[7]),\n .I3(four_dec_min_limit[7]),\n .O(temp_cmp_four_dec_min_102_i_7_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_four_dec_min_102_i_8\n (.I0(four_dec_min_limit[4]),\n .I1(device_temp_101[4]),\n .I2(device_temp_101[5]),\n .I3(four_dec_min_limit[5]),\n .O(temp_cmp_four_dec_min_102_i_8_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_four_dec_min_102_i_9\n (.I0(four_dec_min_limit[2]),\n .I1(device_temp_101[2]),\n .I2(device_temp_101[3]),\n .I3(four_dec_min_limit[3]),\n .O(temp_cmp_four_dec_min_102_i_9_n_0));\n FDRE temp_cmp_four_dec_min_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(temp_cmp_four_dec_min_101),\n .Q(temp_cmp_four_dec_min_102),\n .R(1'b0));\n CARRY4 temp_cmp_four_dec_min_102_reg_i_1\n (.CI(temp_cmp_four_dec_min_102_reg_i_2_n_0),\n .CO({NLW_temp_cmp_four_dec_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_four_dec_min_101,temp_cmp_four_dec_min_102_reg_i_1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,temp_cmp_four_dec_min_102_i_3_n_0,temp_cmp_four_dec_min_102_i_4_n_0}),\n .O(NLW_temp_cmp_four_dec_min_102_reg_i_1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,temp_cmp_four_dec_min_102_i_5_n_0,temp_cmp_four_dec_min_102_i_6_n_0}));\n CARRY4 temp_cmp_four_dec_min_102_reg_i_2\n (.CI(1'b0),\n .CO({temp_cmp_four_dec_min_102_reg_i_2_n_0,temp_cmp_four_dec_min_102_reg_i_2_n_1,temp_cmp_four_dec_min_102_reg_i_2_n_2,temp_cmp_four_dec_min_102_reg_i_2_n_3}),\n .CYINIT(1'b0),\n .DI({temp_cmp_four_dec_min_102_i_7_n_0,temp_cmp_four_dec_min_102_i_8_n_0,temp_cmp_four_dec_min_102_i_9_n_0,temp_cmp_four_dec_min_102_i_10_n_0}),\n .O(NLW_temp_cmp_four_dec_min_102_reg_i_2_O_UNCONNECTED[3:0]),\n .S({temp_cmp_four_dec_min_102_i_11_n_0,temp_cmp_four_dec_min_102_i_12_n_0,temp_cmp_four_dec_min_102_i_13_n_0,temp_cmp_four_dec_min_102_i_14_n_0}));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_four_inc_max_102_i_10\n (.I0(device_temp_101[0]),\n .I1(two_dec_max_limit[0]),\n .I2(four_inc_max_limit[1]),\n .I3(device_temp_101[1]),\n .O(temp_cmp_four_inc_max_102_i_10_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_four_inc_max_102_i_11\n (.I0(device_temp_101[6]),\n .I1(four_inc_max_limit[6]),\n .I2(device_temp_101[7]),\n .I3(four_inc_max_limit[7]),\n .O(temp_cmp_four_inc_max_102_i_11_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_four_inc_max_102_i_12\n (.I0(device_temp_101[4]),\n .I1(four_inc_max_limit[4]),\n .I2(device_temp_101[5]),\n .I3(four_inc_max_limit[5]),\n .O(temp_cmp_four_inc_max_102_i_12_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_four_inc_max_102_i_13\n (.I0(device_temp_101[2]),\n .I1(four_inc_max_limit[2]),\n .I2(device_temp_101[3]),\n .I3(four_inc_max_limit[3]),\n .O(temp_cmp_four_inc_max_102_i_13_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_four_inc_max_102_i_14\n (.I0(device_temp_101[0]),\n .I1(two_dec_max_limit[0]),\n .I2(device_temp_101[1]),\n .I3(four_inc_max_limit[1]),\n .O(temp_cmp_four_inc_max_102_i_14_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_four_inc_max_102_i_3\n (.I0(device_temp_101[10]),\n .I1(four_inc_max_limit[10]),\n .I2(four_inc_max_limit[11]),\n .I3(device_temp_101[11]),\n .O(temp_cmp_four_inc_max_102_i_3_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_four_inc_max_102_i_4\n (.I0(device_temp_101[8]),\n .I1(four_inc_max_limit[8]),\n .I2(four_inc_max_limit[9]),\n .I3(device_temp_101[9]),\n .O(temp_cmp_four_inc_max_102_i_4_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_four_inc_max_102_i_5\n (.I0(device_temp_101[10]),\n .I1(four_inc_max_limit[10]),\n .I2(device_temp_101[11]),\n .I3(four_inc_max_limit[11]),\n .O(temp_cmp_four_inc_max_102_i_5_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_four_inc_max_102_i_6\n (.I0(device_temp_101[8]),\n .I1(four_inc_max_limit[8]),\n .I2(device_temp_101[9]),\n .I3(four_inc_max_limit[9]),\n .O(temp_cmp_four_inc_max_102_i_6_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_four_inc_max_102_i_7\n (.I0(device_temp_101[6]),\n .I1(four_inc_max_limit[6]),\n .I2(four_inc_max_limit[7]),\n .I3(device_temp_101[7]),\n .O(temp_cmp_four_inc_max_102_i_7_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_four_inc_max_102_i_8\n (.I0(device_temp_101[4]),\n .I1(four_inc_max_limit[4]),\n .I2(four_inc_max_limit[5]),\n .I3(device_temp_101[5]),\n .O(temp_cmp_four_inc_max_102_i_8_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_four_inc_max_102_i_9\n (.I0(device_temp_101[2]),\n .I1(four_inc_max_limit[2]),\n .I2(four_inc_max_limit[3]),\n .I3(device_temp_101[3]),\n .O(temp_cmp_four_inc_max_102_i_9_n_0));\n FDRE temp_cmp_four_inc_max_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(temp_cmp_four_inc_max_101),\n .Q(temp_cmp_four_inc_max_102),\n .R(1'b0));\n CARRY4 temp_cmp_four_inc_max_102_reg_i_1\n (.CI(temp_cmp_four_inc_max_102_reg_i_2_n_0),\n .CO({NLW_temp_cmp_four_inc_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_four_inc_max_101,temp_cmp_four_inc_max_102_reg_i_1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,temp_cmp_four_inc_max_102_i_3_n_0,temp_cmp_four_inc_max_102_i_4_n_0}),\n .O(NLW_temp_cmp_four_inc_max_102_reg_i_1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,temp_cmp_four_inc_max_102_i_5_n_0,temp_cmp_four_inc_max_102_i_6_n_0}));\n CARRY4 temp_cmp_four_inc_max_102_reg_i_2\n (.CI(1'b0),\n .CO({temp_cmp_four_inc_max_102_reg_i_2_n_0,temp_cmp_four_inc_max_102_reg_i_2_n_1,temp_cmp_four_inc_max_102_reg_i_2_n_2,temp_cmp_four_inc_max_102_reg_i_2_n_3}),\n .CYINIT(1'b1),\n .DI({temp_cmp_four_inc_max_102_i_7_n_0,temp_cmp_four_inc_max_102_i_8_n_0,temp_cmp_four_inc_max_102_i_9_n_0,temp_cmp_four_inc_max_102_i_10_n_0}),\n .O(NLW_temp_cmp_four_inc_max_102_reg_i_2_O_UNCONNECTED[3:0]),\n .S({temp_cmp_four_inc_max_102_i_11_n_0,temp_cmp_four_inc_max_102_i_12_n_0,temp_cmp_four_inc_max_102_i_13_n_0,temp_cmp_four_inc_max_102_i_14_n_0}));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_neutral_max_102_i_10\n (.I0(device_temp_101[0]),\n .I1(two_dec_max_limit[0]),\n .I2(neutral_max_limit[1]),\n .I3(device_temp_101[1]),\n .O(temp_cmp_neutral_max_102_i_10_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_neutral_max_102_i_11\n (.I0(device_temp_101[6]),\n .I1(neutral_max_limit[6]),\n .I2(device_temp_101[7]),\n .I3(neutral_max_limit[7]),\n .O(temp_cmp_neutral_max_102_i_11_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_neutral_max_102_i_12\n (.I0(device_temp_101[4]),\n .I1(neutral_max_limit[4]),\n .I2(device_temp_101[5]),\n .I3(neutral_max_limit[5]),\n .O(temp_cmp_neutral_max_102_i_12_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_neutral_max_102_i_13\n (.I0(device_temp_101[2]),\n .I1(neutral_max_limit[2]),\n .I2(device_temp_101[3]),\n .I3(neutral_max_limit[3]),\n .O(temp_cmp_neutral_max_102_i_13_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_neutral_max_102_i_14\n (.I0(device_temp_101[0]),\n .I1(two_dec_max_limit[0]),\n .I2(device_temp_101[1]),\n .I3(neutral_max_limit[1]),\n .O(temp_cmp_neutral_max_102_i_14_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_neutral_max_102_i_3\n (.I0(device_temp_101[10]),\n .I1(neutral_max_limit[10]),\n .I2(neutral_max_limit[11]),\n .I3(device_temp_101[11]),\n .O(temp_cmp_neutral_max_102_i_3_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_neutral_max_102_i_4\n (.I0(device_temp_101[8]),\n .I1(neutral_max_limit[8]),\n .I2(neutral_max_limit[9]),\n .I3(device_temp_101[9]),\n .O(temp_cmp_neutral_max_102_i_4_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_neutral_max_102_i_5\n (.I0(device_temp_101[10]),\n .I1(neutral_max_limit[10]),\n .I2(device_temp_101[11]),\n .I3(neutral_max_limit[11]),\n .O(temp_cmp_neutral_max_102_i_5_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_neutral_max_102_i_6\n (.I0(device_temp_101[8]),\n .I1(neutral_max_limit[8]),\n .I2(device_temp_101[9]),\n .I3(neutral_max_limit[9]),\n .O(temp_cmp_neutral_max_102_i_6_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_neutral_max_102_i_7\n (.I0(device_temp_101[6]),\n .I1(neutral_max_limit[6]),\n .I2(neutral_max_limit[7]),\n .I3(device_temp_101[7]),\n .O(temp_cmp_neutral_max_102_i_7_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_neutral_max_102_i_8\n (.I0(device_temp_101[4]),\n .I1(neutral_max_limit[4]),\n .I2(neutral_max_limit[5]),\n .I3(device_temp_101[5]),\n .O(temp_cmp_neutral_max_102_i_8_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_neutral_max_102_i_9\n (.I0(device_temp_101[2]),\n .I1(neutral_max_limit[2]),\n .I2(neutral_max_limit[3]),\n .I3(device_temp_101[3]),\n .O(temp_cmp_neutral_max_102_i_9_n_0));\n FDRE temp_cmp_neutral_max_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(temp_cmp_neutral_max_101),\n .Q(temp_cmp_neutral_max_102),\n .R(1'b0));\n CARRY4 temp_cmp_neutral_max_102_reg_i_1\n (.CI(temp_cmp_neutral_max_102_reg_i_2_n_0),\n .CO({NLW_temp_cmp_neutral_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_neutral_max_101,temp_cmp_neutral_max_102_reg_i_1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,temp_cmp_neutral_max_102_i_3_n_0,temp_cmp_neutral_max_102_i_4_n_0}),\n .O(NLW_temp_cmp_neutral_max_102_reg_i_1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,temp_cmp_neutral_max_102_i_5_n_0,temp_cmp_neutral_max_102_i_6_n_0}));\n CARRY4 temp_cmp_neutral_max_102_reg_i_2\n (.CI(1'b0),\n .CO({temp_cmp_neutral_max_102_reg_i_2_n_0,temp_cmp_neutral_max_102_reg_i_2_n_1,temp_cmp_neutral_max_102_reg_i_2_n_2,temp_cmp_neutral_max_102_reg_i_2_n_3}),\n .CYINIT(1'b1),\n .DI({temp_cmp_neutral_max_102_i_7_n_0,temp_cmp_neutral_max_102_i_8_n_0,temp_cmp_neutral_max_102_i_9_n_0,temp_cmp_neutral_max_102_i_10_n_0}),\n .O(NLW_temp_cmp_neutral_max_102_reg_i_2_O_UNCONNECTED[3:0]),\n .S({temp_cmp_neutral_max_102_i_11_n_0,temp_cmp_neutral_max_102_i_12_n_0,temp_cmp_neutral_max_102_i_13_n_0,temp_cmp_neutral_max_102_i_14_n_0}));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_neutral_min_102_i_10\n (.I0(three_dec_min_limit[0]),\n .I1(device_temp_101[0]),\n .I2(device_temp_101[1]),\n .I3(neutral_min_limit[1]),\n .O(temp_cmp_neutral_min_102_i_10_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_neutral_min_102_i_11\n (.I0(neutral_min_limit[6]),\n .I1(device_temp_101[6]),\n .I2(neutral_min_limit[7]),\n .I3(device_temp_101[7]),\n .O(temp_cmp_neutral_min_102_i_11_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_neutral_min_102_i_12\n (.I0(neutral_min_limit[4]),\n .I1(device_temp_101[4]),\n .I2(neutral_min_limit[5]),\n .I3(device_temp_101[5]),\n .O(temp_cmp_neutral_min_102_i_12_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_neutral_min_102_i_13\n (.I0(neutral_min_limit[2]),\n .I1(device_temp_101[2]),\n .I2(neutral_min_limit[3]),\n .I3(device_temp_101[3]),\n .O(temp_cmp_neutral_min_102_i_13_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_neutral_min_102_i_14\n (.I0(three_dec_min_limit[0]),\n .I1(device_temp_101[0]),\n .I2(neutral_min_limit[1]),\n .I3(device_temp_101[1]),\n .O(temp_cmp_neutral_min_102_i_14_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_neutral_min_102_i_3\n (.I0(neutral_min_limit[10]),\n .I1(device_temp_101[10]),\n .I2(device_temp_101[11]),\n .I3(neutral_min_limit[11]),\n .O(temp_cmp_neutral_min_102_i_3_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_neutral_min_102_i_4\n (.I0(neutral_min_limit[8]),\n .I1(device_temp_101[8]),\n .I2(device_temp_101[9]),\n .I3(neutral_min_limit[9]),\n .O(temp_cmp_neutral_min_102_i_4_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_neutral_min_102_i_5\n (.I0(neutral_min_limit[10]),\n .I1(device_temp_101[10]),\n .I2(neutral_min_limit[11]),\n .I3(device_temp_101[11]),\n .O(temp_cmp_neutral_min_102_i_5_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_neutral_min_102_i_6\n (.I0(neutral_min_limit[8]),\n .I1(device_temp_101[8]),\n .I2(neutral_min_limit[9]),\n .I3(device_temp_101[9]),\n .O(temp_cmp_neutral_min_102_i_6_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_neutral_min_102_i_7\n (.I0(neutral_min_limit[6]),\n .I1(device_temp_101[6]),\n .I2(device_temp_101[7]),\n .I3(neutral_min_limit[7]),\n .O(temp_cmp_neutral_min_102_i_7_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_neutral_min_102_i_8\n (.I0(neutral_min_limit[4]),\n .I1(device_temp_101[4]),\n .I2(device_temp_101[5]),\n .I3(neutral_min_limit[5]),\n .O(temp_cmp_neutral_min_102_i_8_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_neutral_min_102_i_9\n (.I0(neutral_min_limit[2]),\n .I1(device_temp_101[2]),\n .I2(device_temp_101[3]),\n .I3(neutral_min_limit[3]),\n .O(temp_cmp_neutral_min_102_i_9_n_0));\n FDRE temp_cmp_neutral_min_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(temp_cmp_neutral_min_101),\n .Q(temp_cmp_neutral_min_102),\n .R(1'b0));\n CARRY4 temp_cmp_neutral_min_102_reg_i_1\n (.CI(temp_cmp_neutral_min_102_reg_i_2_n_0),\n .CO({NLW_temp_cmp_neutral_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_neutral_min_101,temp_cmp_neutral_min_102_reg_i_1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,temp_cmp_neutral_min_102_i_3_n_0,temp_cmp_neutral_min_102_i_4_n_0}),\n .O(NLW_temp_cmp_neutral_min_102_reg_i_1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,temp_cmp_neutral_min_102_i_5_n_0,temp_cmp_neutral_min_102_i_6_n_0}));\n CARRY4 temp_cmp_neutral_min_102_reg_i_2\n (.CI(1'b0),\n .CO({temp_cmp_neutral_min_102_reg_i_2_n_0,temp_cmp_neutral_min_102_reg_i_2_n_1,temp_cmp_neutral_min_102_reg_i_2_n_2,temp_cmp_neutral_min_102_reg_i_2_n_3}),\n .CYINIT(1'b0),\n .DI({temp_cmp_neutral_min_102_i_7_n_0,temp_cmp_neutral_min_102_i_8_n_0,temp_cmp_neutral_min_102_i_9_n_0,temp_cmp_neutral_min_102_i_10_n_0}),\n .O(NLW_temp_cmp_neutral_min_102_reg_i_2_O_UNCONNECTED[3:0]),\n .S({temp_cmp_neutral_min_102_i_11_n_0,temp_cmp_neutral_min_102_i_12_n_0,temp_cmp_neutral_min_102_i_13_n_0,temp_cmp_neutral_min_102_i_14_n_0}));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_dec_max_102_i_10\n (.I0(device_temp_101[0]),\n .I1(two_dec_max_limit[0]),\n .I2(one_dec_max_limit[1]),\n .I3(device_temp_101[1]),\n .O(temp_cmp_one_dec_max_102_i_10_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_dec_max_102_i_11\n (.I0(device_temp_101[6]),\n .I1(one_dec_max_limit[6]),\n .I2(device_temp_101[7]),\n .I3(one_dec_max_limit[7]),\n .O(temp_cmp_one_dec_max_102_i_11_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_dec_max_102_i_12\n (.I0(device_temp_101[4]),\n .I1(one_dec_max_limit[4]),\n .I2(device_temp_101[5]),\n .I3(one_dec_max_limit[5]),\n .O(temp_cmp_one_dec_max_102_i_12_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_dec_max_102_i_13\n (.I0(device_temp_101[2]),\n .I1(one_dec_max_limit[2]),\n .I2(device_temp_101[3]),\n .I3(one_dec_max_limit[3]),\n .O(temp_cmp_one_dec_max_102_i_13_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_dec_max_102_i_14\n (.I0(device_temp_101[0]),\n .I1(two_dec_max_limit[0]),\n .I2(device_temp_101[1]),\n .I3(one_dec_max_limit[1]),\n .O(temp_cmp_one_dec_max_102_i_14_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_dec_max_102_i_3\n (.I0(device_temp_101[10]),\n .I1(one_dec_max_limit[10]),\n .I2(one_dec_max_limit[11]),\n .I3(device_temp_101[11]),\n .O(temp_cmp_one_dec_max_102_i_3_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_dec_max_102_i_4\n (.I0(device_temp_101[8]),\n .I1(one_dec_max_limit[8]),\n .I2(one_dec_max_limit[9]),\n .I3(device_temp_101[9]),\n .O(temp_cmp_one_dec_max_102_i_4_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_dec_max_102_i_5\n (.I0(device_temp_101[10]),\n .I1(one_dec_max_limit[10]),\n .I2(device_temp_101[11]),\n .I3(one_dec_max_limit[11]),\n .O(temp_cmp_one_dec_max_102_i_5_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_dec_max_102_i_6\n (.I0(device_temp_101[8]),\n .I1(one_dec_max_limit[8]),\n .I2(device_temp_101[9]),\n .I3(one_dec_max_limit[9]),\n .O(temp_cmp_one_dec_max_102_i_6_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_dec_max_102_i_7\n (.I0(device_temp_101[6]),\n .I1(one_dec_max_limit[6]),\n .I2(one_dec_max_limit[7]),\n .I3(device_temp_101[7]),\n .O(temp_cmp_one_dec_max_102_i_7_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_dec_max_102_i_8\n (.I0(device_temp_101[4]),\n .I1(one_dec_max_limit[4]),\n .I2(one_dec_max_limit[5]),\n .I3(device_temp_101[5]),\n .O(temp_cmp_one_dec_max_102_i_8_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_dec_max_102_i_9\n (.I0(device_temp_101[2]),\n .I1(one_dec_max_limit[2]),\n .I2(one_dec_max_limit[3]),\n .I3(device_temp_101[3]),\n .O(temp_cmp_one_dec_max_102_i_9_n_0));\n FDRE temp_cmp_one_dec_max_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(temp_cmp_one_dec_max_101),\n .Q(temp_cmp_one_dec_max_102),\n .R(1'b0));\n CARRY4 temp_cmp_one_dec_max_102_reg_i_1\n (.CI(temp_cmp_one_dec_max_102_reg_i_2_n_0),\n .CO({NLW_temp_cmp_one_dec_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_one_dec_max_101,temp_cmp_one_dec_max_102_reg_i_1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,temp_cmp_one_dec_max_102_i_3_n_0,temp_cmp_one_dec_max_102_i_4_n_0}),\n .O(NLW_temp_cmp_one_dec_max_102_reg_i_1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,temp_cmp_one_dec_max_102_i_5_n_0,temp_cmp_one_dec_max_102_i_6_n_0}));\n CARRY4 temp_cmp_one_dec_max_102_reg_i_2\n (.CI(1'b0),\n .CO({temp_cmp_one_dec_max_102_reg_i_2_n_0,temp_cmp_one_dec_max_102_reg_i_2_n_1,temp_cmp_one_dec_max_102_reg_i_2_n_2,temp_cmp_one_dec_max_102_reg_i_2_n_3}),\n .CYINIT(1'b1),\n .DI({temp_cmp_one_dec_max_102_i_7_n_0,temp_cmp_one_dec_max_102_i_8_n_0,temp_cmp_one_dec_max_102_i_9_n_0,temp_cmp_one_dec_max_102_i_10_n_0}),\n .O(NLW_temp_cmp_one_dec_max_102_reg_i_2_O_UNCONNECTED[3:0]),\n .S({temp_cmp_one_dec_max_102_i_11_n_0,temp_cmp_one_dec_max_102_i_12_n_0,temp_cmp_one_dec_max_102_i_13_n_0,temp_cmp_one_dec_max_102_i_14_n_0}));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_dec_min_102_i_10\n (.I0(three_dec_min_limit[0]),\n .I1(device_temp_101[0]),\n .I2(device_temp_101[1]),\n .I3(one_dec_min_limit[1]),\n .O(temp_cmp_one_dec_min_102_i_10_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_dec_min_102_i_11\n (.I0(one_dec_min_limit[6]),\n .I1(device_temp_101[6]),\n .I2(one_dec_min_limit[7]),\n .I3(device_temp_101[7]),\n .O(temp_cmp_one_dec_min_102_i_11_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_dec_min_102_i_12\n (.I0(one_dec_min_limit[4]),\n .I1(device_temp_101[4]),\n .I2(one_dec_min_limit[5]),\n .I3(device_temp_101[5]),\n .O(temp_cmp_one_dec_min_102_i_12_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_dec_min_102_i_13\n (.I0(one_dec_min_limit[2]),\n .I1(device_temp_101[2]),\n .I2(one_dec_min_limit[3]),\n .I3(device_temp_101[3]),\n .O(temp_cmp_one_dec_min_102_i_13_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_dec_min_102_i_14\n (.I0(three_dec_min_limit[0]),\n .I1(device_temp_101[0]),\n .I2(one_dec_min_limit[1]),\n .I3(device_temp_101[1]),\n .O(temp_cmp_one_dec_min_102_i_14_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_dec_min_102_i_3\n (.I0(one_dec_min_limit[10]),\n .I1(device_temp_101[10]),\n .I2(device_temp_101[11]),\n .I3(one_dec_min_limit[11]),\n .O(temp_cmp_one_dec_min_102_i_3_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_dec_min_102_i_4\n (.I0(one_dec_min_limit[8]),\n .I1(device_temp_101[8]),\n .I2(device_temp_101[9]),\n .I3(one_dec_min_limit[9]),\n .O(temp_cmp_one_dec_min_102_i_4_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_dec_min_102_i_5\n (.I0(one_dec_min_limit[10]),\n .I1(device_temp_101[10]),\n .I2(one_dec_min_limit[11]),\n .I3(device_temp_101[11]),\n .O(temp_cmp_one_dec_min_102_i_5_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_dec_min_102_i_6\n (.I0(one_dec_min_limit[8]),\n .I1(device_temp_101[8]),\n .I2(one_dec_min_limit[9]),\n .I3(device_temp_101[9]),\n .O(temp_cmp_one_dec_min_102_i_6_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_dec_min_102_i_7\n (.I0(one_dec_min_limit[6]),\n .I1(device_temp_101[6]),\n .I2(device_temp_101[7]),\n .I3(one_dec_min_limit[7]),\n .O(temp_cmp_one_dec_min_102_i_7_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_dec_min_102_i_8\n (.I0(one_dec_min_limit[4]),\n .I1(device_temp_101[4]),\n .I2(device_temp_101[5]),\n .I3(one_dec_min_limit[5]),\n .O(temp_cmp_one_dec_min_102_i_8_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_dec_min_102_i_9\n (.I0(one_dec_min_limit[2]),\n .I1(device_temp_101[2]),\n .I2(device_temp_101[3]),\n .I3(one_dec_min_limit[3]),\n .O(temp_cmp_one_dec_min_102_i_9_n_0));\n FDRE temp_cmp_one_dec_min_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(temp_cmp_one_dec_min_101),\n .Q(temp_cmp_one_dec_min_102),\n .R(1'b0));\n CARRY4 temp_cmp_one_dec_min_102_reg_i_1\n (.CI(temp_cmp_one_dec_min_102_reg_i_2_n_0),\n .CO({NLW_temp_cmp_one_dec_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_one_dec_min_101,temp_cmp_one_dec_min_102_reg_i_1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,temp_cmp_one_dec_min_102_i_3_n_0,temp_cmp_one_dec_min_102_i_4_n_0}),\n .O(NLW_temp_cmp_one_dec_min_102_reg_i_1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,temp_cmp_one_dec_min_102_i_5_n_0,temp_cmp_one_dec_min_102_i_6_n_0}));\n CARRY4 temp_cmp_one_dec_min_102_reg_i_2\n (.CI(1'b0),\n .CO({temp_cmp_one_dec_min_102_reg_i_2_n_0,temp_cmp_one_dec_min_102_reg_i_2_n_1,temp_cmp_one_dec_min_102_reg_i_2_n_2,temp_cmp_one_dec_min_102_reg_i_2_n_3}),\n .CYINIT(1'b0),\n .DI({temp_cmp_one_dec_min_102_i_7_n_0,temp_cmp_one_dec_min_102_i_8_n_0,temp_cmp_one_dec_min_102_i_9_n_0,temp_cmp_one_dec_min_102_i_10_n_0}),\n .O(NLW_temp_cmp_one_dec_min_102_reg_i_2_O_UNCONNECTED[3:0]),\n .S({temp_cmp_one_dec_min_102_i_11_n_0,temp_cmp_one_dec_min_102_i_12_n_0,temp_cmp_one_dec_min_102_i_13_n_0,temp_cmp_one_dec_min_102_i_14_n_0}));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_inc_max_102_i_10\n (.I0(device_temp_101[0]),\n .I1(two_dec_max_limit[0]),\n .I2(one_inc_max_limit[1]),\n .I3(device_temp_101[1]),\n .O(temp_cmp_one_inc_max_102_i_10_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_inc_max_102_i_11\n (.I0(device_temp_101[6]),\n .I1(one_inc_max_limit[6]),\n .I2(device_temp_101[7]),\n .I3(one_inc_max_limit[7]),\n .O(temp_cmp_one_inc_max_102_i_11_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_inc_max_102_i_12\n (.I0(device_temp_101[4]),\n .I1(one_inc_max_limit[4]),\n .I2(device_temp_101[5]),\n .I3(one_inc_max_limit[5]),\n .O(temp_cmp_one_inc_max_102_i_12_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_inc_max_102_i_13\n (.I0(device_temp_101[2]),\n .I1(one_inc_max_limit[2]),\n .I2(device_temp_101[3]),\n .I3(one_inc_max_limit[3]),\n .O(temp_cmp_one_inc_max_102_i_13_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_inc_max_102_i_14\n (.I0(device_temp_101[0]),\n .I1(two_dec_max_limit[0]),\n .I2(device_temp_101[1]),\n .I3(one_inc_max_limit[1]),\n .O(temp_cmp_one_inc_max_102_i_14_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_inc_max_102_i_3\n (.I0(device_temp_101[10]),\n .I1(one_inc_max_limit[10]),\n .I2(one_inc_max_limit[11]),\n .I3(device_temp_101[11]),\n .O(temp_cmp_one_inc_max_102_i_3_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_inc_max_102_i_4\n (.I0(device_temp_101[8]),\n .I1(one_inc_max_limit[8]),\n .I2(one_inc_max_limit[9]),\n .I3(device_temp_101[9]),\n .O(temp_cmp_one_inc_max_102_i_4_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_inc_max_102_i_5\n (.I0(device_temp_101[10]),\n .I1(one_inc_max_limit[10]),\n .I2(device_temp_101[11]),\n .I3(one_inc_max_limit[11]),\n .O(temp_cmp_one_inc_max_102_i_5_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_inc_max_102_i_6\n (.I0(device_temp_101[8]),\n .I1(one_inc_max_limit[8]),\n .I2(device_temp_101[9]),\n .I3(one_inc_max_limit[9]),\n .O(temp_cmp_one_inc_max_102_i_6_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_inc_max_102_i_7\n (.I0(device_temp_101[6]),\n .I1(one_inc_max_limit[6]),\n .I2(one_inc_max_limit[7]),\n .I3(device_temp_101[7]),\n .O(temp_cmp_one_inc_max_102_i_7_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_inc_max_102_i_8\n (.I0(device_temp_101[4]),\n .I1(one_inc_max_limit[4]),\n .I2(one_inc_max_limit[5]),\n .I3(device_temp_101[5]),\n .O(temp_cmp_one_inc_max_102_i_8_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_inc_max_102_i_9\n (.I0(device_temp_101[2]),\n .I1(one_inc_max_limit[2]),\n .I2(one_inc_max_limit[3]),\n .I3(device_temp_101[3]),\n .O(temp_cmp_one_inc_max_102_i_9_n_0));\n FDRE temp_cmp_one_inc_max_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(temp_cmp_one_inc_max_101),\n .Q(temp_cmp_one_inc_max_102),\n .R(1'b0));\n CARRY4 temp_cmp_one_inc_max_102_reg_i_1\n (.CI(temp_cmp_one_inc_max_102_reg_i_2_n_0),\n .CO({NLW_temp_cmp_one_inc_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_one_inc_max_101,temp_cmp_one_inc_max_102_reg_i_1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,temp_cmp_one_inc_max_102_i_3_n_0,temp_cmp_one_inc_max_102_i_4_n_0}),\n .O(NLW_temp_cmp_one_inc_max_102_reg_i_1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,temp_cmp_one_inc_max_102_i_5_n_0,temp_cmp_one_inc_max_102_i_6_n_0}));\n CARRY4 temp_cmp_one_inc_max_102_reg_i_2\n (.CI(1'b0),\n .CO({temp_cmp_one_inc_max_102_reg_i_2_n_0,temp_cmp_one_inc_max_102_reg_i_2_n_1,temp_cmp_one_inc_max_102_reg_i_2_n_2,temp_cmp_one_inc_max_102_reg_i_2_n_3}),\n .CYINIT(1'b1),\n .DI({temp_cmp_one_inc_max_102_i_7_n_0,temp_cmp_one_inc_max_102_i_8_n_0,temp_cmp_one_inc_max_102_i_9_n_0,temp_cmp_one_inc_max_102_i_10_n_0}),\n .O(NLW_temp_cmp_one_inc_max_102_reg_i_2_O_UNCONNECTED[3:0]),\n .S({temp_cmp_one_inc_max_102_i_11_n_0,temp_cmp_one_inc_max_102_i_12_n_0,temp_cmp_one_inc_max_102_i_13_n_0,temp_cmp_one_inc_max_102_i_14_n_0}));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_inc_min_102_i_10\n (.I0(three_dec_min_limit[0]),\n .I1(device_temp_101[0]),\n .I2(device_temp_101[1]),\n .I3(one_inc_min_limit[1]),\n .O(temp_cmp_one_inc_min_102_i_10_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_inc_min_102_i_11\n (.I0(one_inc_min_limit[6]),\n .I1(device_temp_101[6]),\n .I2(one_inc_min_limit[7]),\n .I3(device_temp_101[7]),\n .O(temp_cmp_one_inc_min_102_i_11_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_inc_min_102_i_12\n (.I0(one_inc_min_limit[4]),\n .I1(device_temp_101[4]),\n .I2(one_inc_min_limit[5]),\n .I3(device_temp_101[5]),\n .O(temp_cmp_one_inc_min_102_i_12_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_inc_min_102_i_13\n (.I0(one_inc_min_limit[2]),\n .I1(device_temp_101[2]),\n .I2(one_inc_min_limit[3]),\n .I3(device_temp_101[3]),\n .O(temp_cmp_one_inc_min_102_i_13_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_inc_min_102_i_14\n (.I0(three_dec_min_limit[0]),\n .I1(device_temp_101[0]),\n .I2(one_inc_min_limit[1]),\n .I3(device_temp_101[1]),\n .O(temp_cmp_one_inc_min_102_i_14_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_inc_min_102_i_3\n (.I0(one_inc_min_limit[10]),\n .I1(device_temp_101[10]),\n .I2(device_temp_101[11]),\n .I3(one_inc_min_limit[11]),\n .O(temp_cmp_one_inc_min_102_i_3_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_inc_min_102_i_4\n (.I0(one_inc_min_limit[8]),\n .I1(device_temp_101[8]),\n .I2(device_temp_101[9]),\n .I3(one_inc_min_limit[9]),\n .O(temp_cmp_one_inc_min_102_i_4_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_inc_min_102_i_5\n (.I0(one_inc_min_limit[10]),\n .I1(device_temp_101[10]),\n .I2(one_inc_min_limit[11]),\n .I3(device_temp_101[11]),\n .O(temp_cmp_one_inc_min_102_i_5_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_one_inc_min_102_i_6\n (.I0(one_inc_min_limit[8]),\n .I1(device_temp_101[8]),\n .I2(one_inc_min_limit[9]),\n .I3(device_temp_101[9]),\n .O(temp_cmp_one_inc_min_102_i_6_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_inc_min_102_i_7\n (.I0(one_inc_min_limit[6]),\n .I1(device_temp_101[6]),\n .I2(device_temp_101[7]),\n .I3(one_inc_min_limit[7]),\n .O(temp_cmp_one_inc_min_102_i_7_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_inc_min_102_i_8\n (.I0(one_inc_min_limit[4]),\n .I1(device_temp_101[4]),\n .I2(device_temp_101[5]),\n .I3(one_inc_min_limit[5]),\n .O(temp_cmp_one_inc_min_102_i_8_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_one_inc_min_102_i_9\n (.I0(one_inc_min_limit[2]),\n .I1(device_temp_101[2]),\n .I2(device_temp_101[3]),\n .I3(one_inc_min_limit[3]),\n .O(temp_cmp_one_inc_min_102_i_9_n_0));\n FDRE temp_cmp_one_inc_min_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(temp_cmp_one_inc_min_101),\n .Q(temp_cmp_one_inc_min_102),\n .R(1'b0));\n CARRY4 temp_cmp_one_inc_min_102_reg_i_1\n (.CI(temp_cmp_one_inc_min_102_reg_i_2_n_0),\n .CO({NLW_temp_cmp_one_inc_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_one_inc_min_101,temp_cmp_one_inc_min_102_reg_i_1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,temp_cmp_one_inc_min_102_i_3_n_0,temp_cmp_one_inc_min_102_i_4_n_0}),\n .O(NLW_temp_cmp_one_inc_min_102_reg_i_1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,temp_cmp_one_inc_min_102_i_5_n_0,temp_cmp_one_inc_min_102_i_6_n_0}));\n CARRY4 temp_cmp_one_inc_min_102_reg_i_2\n (.CI(1'b0),\n .CO({temp_cmp_one_inc_min_102_reg_i_2_n_0,temp_cmp_one_inc_min_102_reg_i_2_n_1,temp_cmp_one_inc_min_102_reg_i_2_n_2,temp_cmp_one_inc_min_102_reg_i_2_n_3}),\n .CYINIT(1'b0),\n .DI({temp_cmp_one_inc_min_102_i_7_n_0,temp_cmp_one_inc_min_102_i_8_n_0,temp_cmp_one_inc_min_102_i_9_n_0,temp_cmp_one_inc_min_102_i_10_n_0}),\n .O(NLW_temp_cmp_one_inc_min_102_reg_i_2_O_UNCONNECTED[3:0]),\n .S({temp_cmp_one_inc_min_102_i_11_n_0,temp_cmp_one_inc_min_102_i_12_n_0,temp_cmp_one_inc_min_102_i_13_n_0,temp_cmp_one_inc_min_102_i_14_n_0}));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_dec_max_102_i_10\n (.I0(device_temp_101[0]),\n .I1(three_dec_max_limit[0]),\n .I2(three_dec_max_limit[1]),\n .I3(device_temp_101[1]),\n .O(temp_cmp_three_dec_max_102_i_10_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_dec_max_102_i_11\n (.I0(device_temp_101[6]),\n .I1(three_dec_max_limit[6]),\n .I2(device_temp_101[7]),\n .I3(three_dec_max_limit[7]),\n .O(temp_cmp_three_dec_max_102_i_11_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_dec_max_102_i_12\n (.I0(device_temp_101[4]),\n .I1(three_dec_max_limit[4]),\n .I2(device_temp_101[5]),\n .I3(three_dec_max_limit[5]),\n .O(temp_cmp_three_dec_max_102_i_12_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_dec_max_102_i_13\n (.I0(device_temp_101[2]),\n .I1(three_dec_max_limit[2]),\n .I2(device_temp_101[3]),\n .I3(three_dec_max_limit[3]),\n .O(temp_cmp_three_dec_max_102_i_13_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_dec_max_102_i_14\n (.I0(device_temp_101[0]),\n .I1(three_dec_max_limit[0]),\n .I2(device_temp_101[1]),\n .I3(three_dec_max_limit[1]),\n .O(temp_cmp_three_dec_max_102_i_14_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_dec_max_102_i_3\n (.I0(device_temp_101[10]),\n .I1(three_dec_max_limit[10]),\n .I2(three_dec_max_limit[11]),\n .I3(device_temp_101[11]),\n .O(temp_cmp_three_dec_max_102_i_3_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_dec_max_102_i_4\n (.I0(device_temp_101[8]),\n .I1(three_dec_max_limit[8]),\n .I2(three_dec_max_limit[9]),\n .I3(device_temp_101[9]),\n .O(temp_cmp_three_dec_max_102_i_4_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_dec_max_102_i_5\n (.I0(device_temp_101[10]),\n .I1(three_dec_max_limit[10]),\n .I2(device_temp_101[11]),\n .I3(three_dec_max_limit[11]),\n .O(temp_cmp_three_dec_max_102_i_5_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_dec_max_102_i_6\n (.I0(device_temp_101[8]),\n .I1(three_dec_max_limit[8]),\n .I2(device_temp_101[9]),\n .I3(three_dec_max_limit[9]),\n .O(temp_cmp_three_dec_max_102_i_6_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_dec_max_102_i_7\n (.I0(device_temp_101[6]),\n .I1(three_dec_max_limit[6]),\n .I2(three_dec_max_limit[7]),\n .I3(device_temp_101[7]),\n .O(temp_cmp_three_dec_max_102_i_7_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_dec_max_102_i_8\n (.I0(device_temp_101[4]),\n .I1(three_dec_max_limit[4]),\n .I2(three_dec_max_limit[5]),\n .I3(device_temp_101[5]),\n .O(temp_cmp_three_dec_max_102_i_8_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_dec_max_102_i_9\n (.I0(device_temp_101[2]),\n .I1(three_dec_max_limit[2]),\n .I2(three_dec_max_limit[3]),\n .I3(device_temp_101[3]),\n .O(temp_cmp_three_dec_max_102_i_9_n_0));\n FDRE temp_cmp_three_dec_max_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(temp_cmp_three_dec_max_101),\n .Q(temp_cmp_three_dec_max_102),\n .R(1'b0));\n CARRY4 temp_cmp_three_dec_max_102_reg_i_1\n (.CI(temp_cmp_three_dec_max_102_reg_i_2_n_0),\n .CO({NLW_temp_cmp_three_dec_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_three_dec_max_101,temp_cmp_three_dec_max_102_reg_i_1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,temp_cmp_three_dec_max_102_i_3_n_0,temp_cmp_three_dec_max_102_i_4_n_0}),\n .O(NLW_temp_cmp_three_dec_max_102_reg_i_1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,temp_cmp_three_dec_max_102_i_5_n_0,temp_cmp_three_dec_max_102_i_6_n_0}));\n CARRY4 temp_cmp_three_dec_max_102_reg_i_2\n (.CI(1'b0),\n .CO({temp_cmp_three_dec_max_102_reg_i_2_n_0,temp_cmp_three_dec_max_102_reg_i_2_n_1,temp_cmp_three_dec_max_102_reg_i_2_n_2,temp_cmp_three_dec_max_102_reg_i_2_n_3}),\n .CYINIT(1'b1),\n .DI({temp_cmp_three_dec_max_102_i_7_n_0,temp_cmp_three_dec_max_102_i_8_n_0,temp_cmp_three_dec_max_102_i_9_n_0,temp_cmp_three_dec_max_102_i_10_n_0}),\n .O(NLW_temp_cmp_three_dec_max_102_reg_i_2_O_UNCONNECTED[3:0]),\n .S({temp_cmp_three_dec_max_102_i_11_n_0,temp_cmp_three_dec_max_102_i_12_n_0,temp_cmp_three_dec_max_102_i_13_n_0,temp_cmp_three_dec_max_102_i_14_n_0}));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_dec_min_102_i_10\n (.I0(three_dec_min_limit[0]),\n .I1(device_temp_101[0]),\n .I2(device_temp_101[1]),\n .I3(three_dec_min_limit[1]),\n .O(temp_cmp_three_dec_min_102_i_10_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_dec_min_102_i_11\n (.I0(three_dec_min_limit[6]),\n .I1(device_temp_101[6]),\n .I2(three_dec_min_limit[7]),\n .I3(device_temp_101[7]),\n .O(temp_cmp_three_dec_min_102_i_11_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_dec_min_102_i_12\n (.I0(three_dec_min_limit[4]),\n .I1(device_temp_101[4]),\n .I2(three_dec_min_limit[5]),\n .I3(device_temp_101[5]),\n .O(temp_cmp_three_dec_min_102_i_12_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_dec_min_102_i_13\n (.I0(three_dec_min_limit[2]),\n .I1(device_temp_101[2]),\n .I2(three_dec_min_limit[3]),\n .I3(device_temp_101[3]),\n .O(temp_cmp_three_dec_min_102_i_13_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_dec_min_102_i_14\n (.I0(three_dec_min_limit[0]),\n .I1(device_temp_101[0]),\n .I2(three_dec_min_limit[1]),\n .I3(device_temp_101[1]),\n .O(temp_cmp_three_dec_min_102_i_14_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_dec_min_102_i_3\n (.I0(three_dec_min_limit[10]),\n .I1(device_temp_101[10]),\n .I2(device_temp_101[11]),\n .I3(three_dec_min_limit[11]),\n .O(temp_cmp_three_dec_min_102_i_3_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_dec_min_102_i_4\n (.I0(three_dec_min_limit[8]),\n .I1(device_temp_101[8]),\n .I2(device_temp_101[9]),\n .I3(three_dec_min_limit[9]),\n .O(temp_cmp_three_dec_min_102_i_4_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_dec_min_102_i_5\n (.I0(three_dec_min_limit[10]),\n .I1(device_temp_101[10]),\n .I2(three_dec_min_limit[11]),\n .I3(device_temp_101[11]),\n .O(temp_cmp_three_dec_min_102_i_5_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_dec_min_102_i_6\n (.I0(three_dec_min_limit[8]),\n .I1(device_temp_101[8]),\n .I2(three_dec_min_limit[9]),\n .I3(device_temp_101[9]),\n .O(temp_cmp_three_dec_min_102_i_6_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_dec_min_102_i_7\n (.I0(three_dec_min_limit[6]),\n .I1(device_temp_101[6]),\n .I2(device_temp_101[7]),\n .I3(three_dec_min_limit[7]),\n .O(temp_cmp_three_dec_min_102_i_7_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_dec_min_102_i_8\n (.I0(three_dec_min_limit[4]),\n .I1(device_temp_101[4]),\n .I2(device_temp_101[5]),\n .I3(three_dec_min_limit[5]),\n .O(temp_cmp_three_dec_min_102_i_8_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_dec_min_102_i_9\n (.I0(three_dec_min_limit[2]),\n .I1(device_temp_101[2]),\n .I2(device_temp_101[3]),\n .I3(three_dec_min_limit[3]),\n .O(temp_cmp_three_dec_min_102_i_9_n_0));\n FDRE temp_cmp_three_dec_min_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(temp_cmp_three_dec_min_101),\n .Q(temp_cmp_three_dec_min_102),\n .R(1'b0));\n CARRY4 temp_cmp_three_dec_min_102_reg_i_1\n (.CI(temp_cmp_three_dec_min_102_reg_i_2_n_0),\n .CO({NLW_temp_cmp_three_dec_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_three_dec_min_101,temp_cmp_three_dec_min_102_reg_i_1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,temp_cmp_three_dec_min_102_i_3_n_0,temp_cmp_three_dec_min_102_i_4_n_0}),\n .O(NLW_temp_cmp_three_dec_min_102_reg_i_1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,temp_cmp_three_dec_min_102_i_5_n_0,temp_cmp_three_dec_min_102_i_6_n_0}));\n CARRY4 temp_cmp_three_dec_min_102_reg_i_2\n (.CI(1'b0),\n .CO({temp_cmp_three_dec_min_102_reg_i_2_n_0,temp_cmp_three_dec_min_102_reg_i_2_n_1,temp_cmp_three_dec_min_102_reg_i_2_n_2,temp_cmp_three_dec_min_102_reg_i_2_n_3}),\n .CYINIT(1'b0),\n .DI({temp_cmp_three_dec_min_102_i_7_n_0,temp_cmp_three_dec_min_102_i_8_n_0,temp_cmp_three_dec_min_102_i_9_n_0,temp_cmp_three_dec_min_102_i_10_n_0}),\n .O(NLW_temp_cmp_three_dec_min_102_reg_i_2_O_UNCONNECTED[3:0]),\n .S({temp_cmp_three_dec_min_102_i_11_n_0,temp_cmp_three_dec_min_102_i_12_n_0,temp_cmp_three_dec_min_102_i_13_n_0,temp_cmp_three_dec_min_102_i_14_n_0}));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_inc_max_102_i_10\n (.I0(device_temp_101[0]),\n .I1(two_dec_max_limit[0]),\n .I2(three_inc_max_limit[1]),\n .I3(device_temp_101[1]),\n .O(temp_cmp_three_inc_max_102_i_10_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_inc_max_102_i_11\n (.I0(device_temp_101[6]),\n .I1(three_inc_max_limit[6]),\n .I2(device_temp_101[7]),\n .I3(three_inc_max_limit[7]),\n .O(temp_cmp_three_inc_max_102_i_11_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_inc_max_102_i_12\n (.I0(device_temp_101[4]),\n .I1(three_inc_max_limit[4]),\n .I2(device_temp_101[5]),\n .I3(three_inc_max_limit[5]),\n .O(temp_cmp_three_inc_max_102_i_12_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_inc_max_102_i_13\n (.I0(device_temp_101[2]),\n .I1(three_inc_max_limit[2]),\n .I2(device_temp_101[3]),\n .I3(three_inc_max_limit[3]),\n .O(temp_cmp_three_inc_max_102_i_13_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_inc_max_102_i_14\n (.I0(device_temp_101[0]),\n .I1(two_dec_max_limit[0]),\n .I2(device_temp_101[1]),\n .I3(three_inc_max_limit[1]),\n .O(temp_cmp_three_inc_max_102_i_14_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_inc_max_102_i_3\n (.I0(device_temp_101[10]),\n .I1(three_inc_max_limit[10]),\n .I2(three_inc_max_limit[11]),\n .I3(device_temp_101[11]),\n .O(temp_cmp_three_inc_max_102_i_3_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_inc_max_102_i_4\n (.I0(device_temp_101[8]),\n .I1(three_inc_max_limit[8]),\n .I2(three_inc_max_limit[9]),\n .I3(device_temp_101[9]),\n .O(temp_cmp_three_inc_max_102_i_4_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_inc_max_102_i_5\n (.I0(device_temp_101[10]),\n .I1(three_inc_max_limit[10]),\n .I2(device_temp_101[11]),\n .I3(three_inc_max_limit[11]),\n .O(temp_cmp_three_inc_max_102_i_5_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_inc_max_102_i_6\n (.I0(device_temp_101[8]),\n .I1(three_inc_max_limit[8]),\n .I2(device_temp_101[9]),\n .I3(three_inc_max_limit[9]),\n .O(temp_cmp_three_inc_max_102_i_6_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_inc_max_102_i_7\n (.I0(device_temp_101[6]),\n .I1(three_inc_max_limit[6]),\n .I2(three_inc_max_limit[7]),\n .I3(device_temp_101[7]),\n .O(temp_cmp_three_inc_max_102_i_7_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_inc_max_102_i_8\n (.I0(device_temp_101[4]),\n .I1(three_inc_max_limit[4]),\n .I2(three_inc_max_limit[5]),\n .I3(device_temp_101[5]),\n .O(temp_cmp_three_inc_max_102_i_8_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_inc_max_102_i_9\n (.I0(device_temp_101[2]),\n .I1(three_inc_max_limit[2]),\n .I2(three_inc_max_limit[3]),\n .I3(device_temp_101[3]),\n .O(temp_cmp_three_inc_max_102_i_9_n_0));\n FDRE temp_cmp_three_inc_max_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(temp_cmp_three_inc_max_101),\n .Q(temp_cmp_three_inc_max_102),\n .R(1'b0));\n CARRY4 temp_cmp_three_inc_max_102_reg_i_1\n (.CI(temp_cmp_three_inc_max_102_reg_i_2_n_0),\n .CO({NLW_temp_cmp_three_inc_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_three_inc_max_101,temp_cmp_three_inc_max_102_reg_i_1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,temp_cmp_three_inc_max_102_i_3_n_0,temp_cmp_three_inc_max_102_i_4_n_0}),\n .O(NLW_temp_cmp_three_inc_max_102_reg_i_1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,temp_cmp_three_inc_max_102_i_5_n_0,temp_cmp_three_inc_max_102_i_6_n_0}));\n CARRY4 temp_cmp_three_inc_max_102_reg_i_2\n (.CI(1'b0),\n .CO({temp_cmp_three_inc_max_102_reg_i_2_n_0,temp_cmp_three_inc_max_102_reg_i_2_n_1,temp_cmp_three_inc_max_102_reg_i_2_n_2,temp_cmp_three_inc_max_102_reg_i_2_n_3}),\n .CYINIT(1'b1),\n .DI({temp_cmp_three_inc_max_102_i_7_n_0,temp_cmp_three_inc_max_102_i_8_n_0,temp_cmp_three_inc_max_102_i_9_n_0,temp_cmp_three_inc_max_102_i_10_n_0}),\n .O(NLW_temp_cmp_three_inc_max_102_reg_i_2_O_UNCONNECTED[3:0]),\n .S({temp_cmp_three_inc_max_102_i_11_n_0,temp_cmp_three_inc_max_102_i_12_n_0,temp_cmp_three_inc_max_102_i_13_n_0,temp_cmp_three_inc_max_102_i_14_n_0}));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_inc_min_102_i_10\n (.I0(three_dec_min_limit[0]),\n .I1(device_temp_101[0]),\n .I2(device_temp_101[1]),\n .I3(three_inc_min_limit[1]),\n .O(temp_cmp_three_inc_min_102_i_10_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_inc_min_102_i_11\n (.I0(three_inc_min_limit[6]),\n .I1(device_temp_101[6]),\n .I2(three_inc_min_limit[7]),\n .I3(device_temp_101[7]),\n .O(temp_cmp_three_inc_min_102_i_11_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_inc_min_102_i_12\n (.I0(three_inc_min_limit[4]),\n .I1(device_temp_101[4]),\n .I2(three_inc_min_limit[5]),\n .I3(device_temp_101[5]),\n .O(temp_cmp_three_inc_min_102_i_12_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_inc_min_102_i_13\n (.I0(three_inc_min_limit[2]),\n .I1(device_temp_101[2]),\n .I2(three_inc_min_limit[3]),\n .I3(device_temp_101[3]),\n .O(temp_cmp_three_inc_min_102_i_13_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_inc_min_102_i_14\n (.I0(three_dec_min_limit[0]),\n .I1(device_temp_101[0]),\n .I2(three_inc_min_limit[1]),\n .I3(device_temp_101[1]),\n .O(temp_cmp_three_inc_min_102_i_14_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_inc_min_102_i_3\n (.I0(three_inc_min_limit[10]),\n .I1(device_temp_101[10]),\n .I2(device_temp_101[11]),\n .I3(three_inc_min_limit[11]),\n .O(temp_cmp_three_inc_min_102_i_3_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_inc_min_102_i_4\n (.I0(three_inc_min_limit[8]),\n .I1(device_temp_101[8]),\n .I2(device_temp_101[9]),\n .I3(three_inc_min_limit[9]),\n .O(temp_cmp_three_inc_min_102_i_4_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_inc_min_102_i_5\n (.I0(three_inc_min_limit[10]),\n .I1(device_temp_101[10]),\n .I2(three_inc_min_limit[11]),\n .I3(device_temp_101[11]),\n .O(temp_cmp_three_inc_min_102_i_5_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_three_inc_min_102_i_6\n (.I0(three_inc_min_limit[8]),\n .I1(device_temp_101[8]),\n .I2(three_inc_min_limit[9]),\n .I3(device_temp_101[9]),\n .O(temp_cmp_three_inc_min_102_i_6_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_inc_min_102_i_7\n (.I0(three_inc_min_limit[6]),\n .I1(device_temp_101[6]),\n .I2(device_temp_101[7]),\n .I3(three_inc_min_limit[7]),\n .O(temp_cmp_three_inc_min_102_i_7_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_inc_min_102_i_8\n (.I0(three_inc_min_limit[4]),\n .I1(device_temp_101[4]),\n .I2(device_temp_101[5]),\n .I3(three_inc_min_limit[5]),\n .O(temp_cmp_three_inc_min_102_i_8_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_three_inc_min_102_i_9\n (.I0(three_inc_min_limit[2]),\n .I1(device_temp_101[2]),\n .I2(device_temp_101[3]),\n .I3(three_inc_min_limit[3]),\n .O(temp_cmp_three_inc_min_102_i_9_n_0));\n FDRE temp_cmp_three_inc_min_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(temp_cmp_three_inc_min_101),\n .Q(temp_cmp_three_inc_min_102),\n .R(1'b0));\n CARRY4 temp_cmp_three_inc_min_102_reg_i_1\n (.CI(temp_cmp_three_inc_min_102_reg_i_2_n_0),\n .CO({NLW_temp_cmp_three_inc_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_three_inc_min_101,temp_cmp_three_inc_min_102_reg_i_1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,temp_cmp_three_inc_min_102_i_3_n_0,temp_cmp_three_inc_min_102_i_4_n_0}),\n .O(NLW_temp_cmp_three_inc_min_102_reg_i_1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,temp_cmp_three_inc_min_102_i_5_n_0,temp_cmp_three_inc_min_102_i_6_n_0}));\n CARRY4 temp_cmp_three_inc_min_102_reg_i_2\n (.CI(1'b0),\n .CO({temp_cmp_three_inc_min_102_reg_i_2_n_0,temp_cmp_three_inc_min_102_reg_i_2_n_1,temp_cmp_three_inc_min_102_reg_i_2_n_2,temp_cmp_three_inc_min_102_reg_i_2_n_3}),\n .CYINIT(1'b0),\n .DI({temp_cmp_three_inc_min_102_i_7_n_0,temp_cmp_three_inc_min_102_i_8_n_0,temp_cmp_three_inc_min_102_i_9_n_0,temp_cmp_three_inc_min_102_i_10_n_0}),\n .O(NLW_temp_cmp_three_inc_min_102_reg_i_2_O_UNCONNECTED[3:0]),\n .S({temp_cmp_three_inc_min_102_i_11_n_0,temp_cmp_three_inc_min_102_i_12_n_0,temp_cmp_three_inc_min_102_i_13_n_0,temp_cmp_three_inc_min_102_i_14_n_0}));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_dec_max_102_i_10\n (.I0(device_temp_101[0]),\n .I1(two_dec_max_limit[0]),\n .I2(two_dec_max_limit[1]),\n .I3(device_temp_101[1]),\n .O(temp_cmp_two_dec_max_102_i_10_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_dec_max_102_i_11\n (.I0(device_temp_101[6]),\n .I1(two_dec_max_limit[6]),\n .I2(device_temp_101[7]),\n .I3(two_dec_max_limit[7]),\n .O(temp_cmp_two_dec_max_102_i_11_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_dec_max_102_i_12\n (.I0(device_temp_101[4]),\n .I1(two_dec_max_limit[4]),\n .I2(device_temp_101[5]),\n .I3(two_dec_max_limit[5]),\n .O(temp_cmp_two_dec_max_102_i_12_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_dec_max_102_i_13\n (.I0(device_temp_101[2]),\n .I1(two_dec_max_limit[2]),\n .I2(device_temp_101[3]),\n .I3(two_dec_max_limit[3]),\n .O(temp_cmp_two_dec_max_102_i_13_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_dec_max_102_i_14\n (.I0(device_temp_101[0]),\n .I1(two_dec_max_limit[0]),\n .I2(device_temp_101[1]),\n .I3(two_dec_max_limit[1]),\n .O(temp_cmp_two_dec_max_102_i_14_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_dec_max_102_i_3\n (.I0(device_temp_101[10]),\n .I1(two_dec_max_limit[10]),\n .I2(two_dec_max_limit[11]),\n .I3(device_temp_101[11]),\n .O(temp_cmp_two_dec_max_102_i_3_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_dec_max_102_i_4\n (.I0(device_temp_101[8]),\n .I1(two_dec_max_limit[8]),\n .I2(two_dec_max_limit[9]),\n .I3(device_temp_101[9]),\n .O(temp_cmp_two_dec_max_102_i_4_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_dec_max_102_i_5\n (.I0(device_temp_101[10]),\n .I1(two_dec_max_limit[10]),\n .I2(device_temp_101[11]),\n .I3(two_dec_max_limit[11]),\n .O(temp_cmp_two_dec_max_102_i_5_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_dec_max_102_i_6\n (.I0(device_temp_101[8]),\n .I1(two_dec_max_limit[8]),\n .I2(device_temp_101[9]),\n .I3(two_dec_max_limit[9]),\n .O(temp_cmp_two_dec_max_102_i_6_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_dec_max_102_i_7\n (.I0(device_temp_101[6]),\n .I1(two_dec_max_limit[6]),\n .I2(two_dec_max_limit[7]),\n .I3(device_temp_101[7]),\n .O(temp_cmp_two_dec_max_102_i_7_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_dec_max_102_i_8\n (.I0(device_temp_101[4]),\n .I1(two_dec_max_limit[4]),\n .I2(two_dec_max_limit[5]),\n .I3(device_temp_101[5]),\n .O(temp_cmp_two_dec_max_102_i_8_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_dec_max_102_i_9\n (.I0(device_temp_101[2]),\n .I1(two_dec_max_limit[2]),\n .I2(two_dec_max_limit[3]),\n .I3(device_temp_101[3]),\n .O(temp_cmp_two_dec_max_102_i_9_n_0));\n FDRE temp_cmp_two_dec_max_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(temp_cmp_two_dec_max_101),\n .Q(temp_cmp_two_dec_max_102),\n .R(1'b0));\n CARRY4 temp_cmp_two_dec_max_102_reg_i_1\n (.CI(temp_cmp_two_dec_max_102_reg_i_2_n_0),\n .CO({NLW_temp_cmp_two_dec_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_two_dec_max_101,temp_cmp_two_dec_max_102_reg_i_1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,temp_cmp_two_dec_max_102_i_3_n_0,temp_cmp_two_dec_max_102_i_4_n_0}),\n .O(NLW_temp_cmp_two_dec_max_102_reg_i_1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,temp_cmp_two_dec_max_102_i_5_n_0,temp_cmp_two_dec_max_102_i_6_n_0}));\n CARRY4 temp_cmp_two_dec_max_102_reg_i_2\n (.CI(1'b0),\n .CO({temp_cmp_two_dec_max_102_reg_i_2_n_0,temp_cmp_two_dec_max_102_reg_i_2_n_1,temp_cmp_two_dec_max_102_reg_i_2_n_2,temp_cmp_two_dec_max_102_reg_i_2_n_3}),\n .CYINIT(1'b1),\n .DI({temp_cmp_two_dec_max_102_i_7_n_0,temp_cmp_two_dec_max_102_i_8_n_0,temp_cmp_two_dec_max_102_i_9_n_0,temp_cmp_two_dec_max_102_i_10_n_0}),\n .O(NLW_temp_cmp_two_dec_max_102_reg_i_2_O_UNCONNECTED[3:0]),\n .S({temp_cmp_two_dec_max_102_i_11_n_0,temp_cmp_two_dec_max_102_i_12_n_0,temp_cmp_two_dec_max_102_i_13_n_0,temp_cmp_two_dec_max_102_i_14_n_0}));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_dec_min_102_i_10\n (.I0(three_dec_min_limit[0]),\n .I1(device_temp_101[0]),\n .I2(device_temp_101[1]),\n .I3(two_dec_min_limit[1]),\n .O(temp_cmp_two_dec_min_102_i_10_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_dec_min_102_i_11\n (.I0(two_dec_min_limit[6]),\n .I1(device_temp_101[6]),\n .I2(two_dec_min_limit[7]),\n .I3(device_temp_101[7]),\n .O(temp_cmp_two_dec_min_102_i_11_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_dec_min_102_i_12\n (.I0(two_dec_min_limit[4]),\n .I1(device_temp_101[4]),\n .I2(two_dec_min_limit[5]),\n .I3(device_temp_101[5]),\n .O(temp_cmp_two_dec_min_102_i_12_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_dec_min_102_i_13\n (.I0(two_dec_min_limit[2]),\n .I1(device_temp_101[2]),\n .I2(two_dec_min_limit[3]),\n .I3(device_temp_101[3]),\n .O(temp_cmp_two_dec_min_102_i_13_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_dec_min_102_i_14\n (.I0(three_dec_min_limit[0]),\n .I1(device_temp_101[0]),\n .I2(two_dec_min_limit[1]),\n .I3(device_temp_101[1]),\n .O(temp_cmp_two_dec_min_102_i_14_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_dec_min_102_i_3\n (.I0(two_dec_min_limit[10]),\n .I1(device_temp_101[10]),\n .I2(device_temp_101[11]),\n .I3(two_dec_min_limit[11]),\n .O(temp_cmp_two_dec_min_102_i_3_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_dec_min_102_i_4\n (.I0(two_dec_min_limit[8]),\n .I1(device_temp_101[8]),\n .I2(device_temp_101[9]),\n .I3(two_dec_min_limit[9]),\n .O(temp_cmp_two_dec_min_102_i_4_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_dec_min_102_i_5\n (.I0(two_dec_min_limit[10]),\n .I1(device_temp_101[10]),\n .I2(two_dec_min_limit[11]),\n .I3(device_temp_101[11]),\n .O(temp_cmp_two_dec_min_102_i_5_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_dec_min_102_i_6\n (.I0(two_dec_min_limit[8]),\n .I1(device_temp_101[8]),\n .I2(two_dec_min_limit[9]),\n .I3(device_temp_101[9]),\n .O(temp_cmp_two_dec_min_102_i_6_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_dec_min_102_i_7\n (.I0(two_dec_min_limit[6]),\n .I1(device_temp_101[6]),\n .I2(device_temp_101[7]),\n .I3(two_dec_min_limit[7]),\n .O(temp_cmp_two_dec_min_102_i_7_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_dec_min_102_i_8\n (.I0(two_dec_min_limit[4]),\n .I1(device_temp_101[4]),\n .I2(device_temp_101[5]),\n .I3(two_dec_min_limit[5]),\n .O(temp_cmp_two_dec_min_102_i_8_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_dec_min_102_i_9\n (.I0(two_dec_min_limit[2]),\n .I1(device_temp_101[2]),\n .I2(device_temp_101[3]),\n .I3(two_dec_min_limit[3]),\n .O(temp_cmp_two_dec_min_102_i_9_n_0));\n FDRE temp_cmp_two_dec_min_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(temp_cmp_two_dec_min_101),\n .Q(temp_cmp_two_dec_min_102),\n .R(1'b0));\n CARRY4 temp_cmp_two_dec_min_102_reg_i_1\n (.CI(temp_cmp_two_dec_min_102_reg_i_2_n_0),\n .CO({NLW_temp_cmp_two_dec_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_two_dec_min_101,temp_cmp_two_dec_min_102_reg_i_1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,temp_cmp_two_dec_min_102_i_3_n_0,temp_cmp_two_dec_min_102_i_4_n_0}),\n .O(NLW_temp_cmp_two_dec_min_102_reg_i_1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,temp_cmp_two_dec_min_102_i_5_n_0,temp_cmp_two_dec_min_102_i_6_n_0}));\n CARRY4 temp_cmp_two_dec_min_102_reg_i_2\n (.CI(1'b0),\n .CO({temp_cmp_two_dec_min_102_reg_i_2_n_0,temp_cmp_two_dec_min_102_reg_i_2_n_1,temp_cmp_two_dec_min_102_reg_i_2_n_2,temp_cmp_two_dec_min_102_reg_i_2_n_3}),\n .CYINIT(1'b0),\n .DI({temp_cmp_two_dec_min_102_i_7_n_0,temp_cmp_two_dec_min_102_i_8_n_0,temp_cmp_two_dec_min_102_i_9_n_0,temp_cmp_two_dec_min_102_i_10_n_0}),\n .O(NLW_temp_cmp_two_dec_min_102_reg_i_2_O_UNCONNECTED[3:0]),\n .S({temp_cmp_two_dec_min_102_i_11_n_0,temp_cmp_two_dec_min_102_i_12_n_0,temp_cmp_two_dec_min_102_i_13_n_0,temp_cmp_two_dec_min_102_i_14_n_0}));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_inc_max_102_i_10\n (.I0(device_temp_101[0]),\n .I1(two_dec_max_limit[0]),\n .I2(two_inc_max_limit[1]),\n .I3(device_temp_101[1]),\n .O(temp_cmp_two_inc_max_102_i_10_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_inc_max_102_i_11\n (.I0(device_temp_101[6]),\n .I1(two_inc_max_limit[6]),\n .I2(device_temp_101[7]),\n .I3(two_inc_max_limit[7]),\n .O(temp_cmp_two_inc_max_102_i_11_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_inc_max_102_i_12\n (.I0(device_temp_101[4]),\n .I1(two_inc_max_limit[4]),\n .I2(device_temp_101[5]),\n .I3(two_inc_max_limit[5]),\n .O(temp_cmp_two_inc_max_102_i_12_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_inc_max_102_i_13\n (.I0(device_temp_101[2]),\n .I1(two_inc_max_limit[2]),\n .I2(device_temp_101[3]),\n .I3(two_inc_max_limit[3]),\n .O(temp_cmp_two_inc_max_102_i_13_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_inc_max_102_i_14\n (.I0(device_temp_101[0]),\n .I1(two_dec_max_limit[0]),\n .I2(device_temp_101[1]),\n .I3(two_inc_max_limit[1]),\n .O(temp_cmp_two_inc_max_102_i_14_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_inc_max_102_i_3\n (.I0(device_temp_101[10]),\n .I1(two_inc_max_limit[10]),\n .I2(two_inc_max_limit[11]),\n .I3(device_temp_101[11]),\n .O(temp_cmp_two_inc_max_102_i_3_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_inc_max_102_i_4\n (.I0(device_temp_101[8]),\n .I1(two_inc_max_limit[8]),\n .I2(two_inc_max_limit[9]),\n .I3(device_temp_101[9]),\n .O(temp_cmp_two_inc_max_102_i_4_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_inc_max_102_i_5\n (.I0(device_temp_101[10]),\n .I1(two_inc_max_limit[10]),\n .I2(device_temp_101[11]),\n .I3(two_inc_max_limit[11]),\n .O(temp_cmp_two_inc_max_102_i_5_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_inc_max_102_i_6\n (.I0(device_temp_101[8]),\n .I1(two_inc_max_limit[8]),\n .I2(device_temp_101[9]),\n .I3(two_inc_max_limit[9]),\n .O(temp_cmp_two_inc_max_102_i_6_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_inc_max_102_i_7\n (.I0(device_temp_101[6]),\n .I1(two_inc_max_limit[6]),\n .I2(two_inc_max_limit[7]),\n .I3(device_temp_101[7]),\n .O(temp_cmp_two_inc_max_102_i_7_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_inc_max_102_i_8\n (.I0(device_temp_101[4]),\n .I1(two_inc_max_limit[4]),\n .I2(two_inc_max_limit[5]),\n .I3(device_temp_101[5]),\n .O(temp_cmp_two_inc_max_102_i_8_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_inc_max_102_i_9\n (.I0(device_temp_101[2]),\n .I1(two_inc_max_limit[2]),\n .I2(two_inc_max_limit[3]),\n .I3(device_temp_101[3]),\n .O(temp_cmp_two_inc_max_102_i_9_n_0));\n FDRE temp_cmp_two_inc_max_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(temp_cmp_two_inc_max_101),\n .Q(temp_cmp_two_inc_max_102),\n .R(1'b0));\n CARRY4 temp_cmp_two_inc_max_102_reg_i_1\n (.CI(temp_cmp_two_inc_max_102_reg_i_2_n_0),\n .CO({NLW_temp_cmp_two_inc_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_two_inc_max_101,temp_cmp_two_inc_max_102_reg_i_1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,temp_cmp_two_inc_max_102_i_3_n_0,temp_cmp_two_inc_max_102_i_4_n_0}),\n .O(NLW_temp_cmp_two_inc_max_102_reg_i_1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,temp_cmp_two_inc_max_102_i_5_n_0,temp_cmp_two_inc_max_102_i_6_n_0}));\n CARRY4 temp_cmp_two_inc_max_102_reg_i_2\n (.CI(1'b0),\n .CO({temp_cmp_two_inc_max_102_reg_i_2_n_0,temp_cmp_two_inc_max_102_reg_i_2_n_1,temp_cmp_two_inc_max_102_reg_i_2_n_2,temp_cmp_two_inc_max_102_reg_i_2_n_3}),\n .CYINIT(1'b1),\n .DI({temp_cmp_two_inc_max_102_i_7_n_0,temp_cmp_two_inc_max_102_i_8_n_0,temp_cmp_two_inc_max_102_i_9_n_0,temp_cmp_two_inc_max_102_i_10_n_0}),\n .O(NLW_temp_cmp_two_inc_max_102_reg_i_2_O_UNCONNECTED[3:0]),\n .S({temp_cmp_two_inc_max_102_i_11_n_0,temp_cmp_two_inc_max_102_i_12_n_0,temp_cmp_two_inc_max_102_i_13_n_0,temp_cmp_two_inc_max_102_i_14_n_0}));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_inc_min_102_i_10\n (.I0(three_dec_min_limit[0]),\n .I1(device_temp_101[0]),\n .I2(device_temp_101[1]),\n .I3(two_inc_min_limit[1]),\n .O(temp_cmp_two_inc_min_102_i_10_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_inc_min_102_i_11\n (.I0(two_inc_min_limit[6]),\n .I1(device_temp_101[6]),\n .I2(two_inc_min_limit[7]),\n .I3(device_temp_101[7]),\n .O(temp_cmp_two_inc_min_102_i_11_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_inc_min_102_i_12\n (.I0(two_inc_min_limit[4]),\n .I1(device_temp_101[4]),\n .I2(two_inc_min_limit[5]),\n .I3(device_temp_101[5]),\n .O(temp_cmp_two_inc_min_102_i_12_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_inc_min_102_i_13\n (.I0(two_inc_min_limit[2]),\n .I1(device_temp_101[2]),\n .I2(two_inc_min_limit[3]),\n .I3(device_temp_101[3]),\n .O(temp_cmp_two_inc_min_102_i_13_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_inc_min_102_i_14\n (.I0(three_dec_min_limit[0]),\n .I1(device_temp_101[0]),\n .I2(two_inc_min_limit[1]),\n .I3(device_temp_101[1]),\n .O(temp_cmp_two_inc_min_102_i_14_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_inc_min_102_i_3\n (.I0(two_inc_min_limit[10]),\n .I1(device_temp_101[10]),\n .I2(device_temp_101[11]),\n .I3(two_inc_min_limit[11]),\n .O(temp_cmp_two_inc_min_102_i_3_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_inc_min_102_i_4\n (.I0(two_inc_min_limit[8]),\n .I1(device_temp_101[8]),\n .I2(device_temp_101[9]),\n .I3(two_inc_min_limit[9]),\n .O(temp_cmp_two_inc_min_102_i_4_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_inc_min_102_i_5\n (.I0(two_inc_min_limit[10]),\n .I1(device_temp_101[10]),\n .I2(two_inc_min_limit[11]),\n .I3(device_temp_101[11]),\n .O(temp_cmp_two_inc_min_102_i_5_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n temp_cmp_two_inc_min_102_i_6\n (.I0(two_inc_min_limit[8]),\n .I1(device_temp_101[8]),\n .I2(two_inc_min_limit[9]),\n .I3(device_temp_101[9]),\n .O(temp_cmp_two_inc_min_102_i_6_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_inc_min_102_i_7\n (.I0(two_inc_min_limit[6]),\n .I1(device_temp_101[6]),\n .I2(device_temp_101[7]),\n .I3(two_inc_min_limit[7]),\n .O(temp_cmp_two_inc_min_102_i_7_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_inc_min_102_i_8\n (.I0(two_inc_min_limit[4]),\n .I1(device_temp_101[4]),\n .I2(device_temp_101[5]),\n .I3(two_inc_min_limit[5]),\n .O(temp_cmp_two_inc_min_102_i_8_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n temp_cmp_two_inc_min_102_i_9\n (.I0(two_inc_min_limit[2]),\n .I1(device_temp_101[2]),\n .I2(device_temp_101[3]),\n .I3(two_inc_min_limit[3]),\n .O(temp_cmp_two_inc_min_102_i_9_n_0));\n FDRE temp_cmp_two_inc_min_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(temp_cmp_two_inc_min_101),\n .Q(temp_cmp_two_inc_min_102),\n .R(1'b0));\n CARRY4 temp_cmp_two_inc_min_102_reg_i_1\n (.CI(temp_cmp_two_inc_min_102_reg_i_2_n_0),\n .CO({NLW_temp_cmp_two_inc_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_two_inc_min_101,temp_cmp_two_inc_min_102_reg_i_1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,temp_cmp_two_inc_min_102_i_3_n_0,temp_cmp_two_inc_min_102_i_4_n_0}),\n .O(NLW_temp_cmp_two_inc_min_102_reg_i_1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,temp_cmp_two_inc_min_102_i_5_n_0,temp_cmp_two_inc_min_102_i_6_n_0}));\n CARRY4 temp_cmp_two_inc_min_102_reg_i_2\n (.CI(1'b0),\n .CO({temp_cmp_two_inc_min_102_reg_i_2_n_0,temp_cmp_two_inc_min_102_reg_i_2_n_1,temp_cmp_two_inc_min_102_reg_i_2_n_2,temp_cmp_two_inc_min_102_reg_i_2_n_3}),\n .CYINIT(1'b0),\n .DI({temp_cmp_two_inc_min_102_i_7_n_0,temp_cmp_two_inc_min_102_i_8_n_0,temp_cmp_two_inc_min_102_i_9_n_0,temp_cmp_two_inc_min_102_i_10_n_0}),\n .O(NLW_temp_cmp_two_inc_min_102_reg_i_2_O_UNCONNECTED[3:0]),\n .S({temp_cmp_two_inc_min_102_i_11_n_0,temp_cmp_two_inc_min_102_i_12_n_0,temp_cmp_two_inc_min_102_i_13_n_0,temp_cmp_two_inc_min_102_i_14_n_0}));\n FDRE tempmon_init_complete_reg\n (.C(CLK),\n .CE(tempmon_state_init),\n .D(tempmon_state_init),\n .Q(tempmon_init_complete),\n .R(SS));\n (* SOFT_HLUTNM = \"soft_lutpair255\" *) \n LUT2 #(\n .INIT(4'hE)) \n tempmon_pi_f_en_r_i_1\n (.I0(tempmon_pi_f_inc),\n .I1(tempmon_pi_f_dec),\n .O(tempmon_sel_pi_incdec));\n FDRE tempmon_sample_en_101_reg\n (.C(CLK),\n .CE(1'b1),\n .D(tempmon_sample_en),\n .Q(tempmon_sample_en_101),\n .R(SS));\n FDRE tempmon_sample_en_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(tempmon_sample_en_101),\n .Q(tempmon_sample_en_102),\n .R(SS));\n (* SOFT_HLUTNM = \"soft_lutpair253\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\tempmon_state[0]_i_2 \n (.I0(\\tempmon_state[10]_i_7_n_0 ),\n .O(\\tempmon_state[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFEAFFFFFFFF)) \n \\tempmon_state[10]_i_1 \n (.I0(\\tempmon_state[10]_i_3_n_0 ),\n .I1(\\tempmon_state[10]_i_4_n_0 ),\n .I2(update_temp_102),\n .I3(\\tempmon_state[10]_i_5_n_0 ),\n .I4(\\tempmon_state[10]_i_6_n_0 ),\n .I5(\\tempmon_state[10]_i_7_n_0 ),\n .O(tempmon_state_nxt));\n LUT3 #(\n .INIT(8'h80)) \n \\tempmon_state[10]_i_10 \n (.I0(update_temp_102),\n .I1(temp_cmp_four_dec_min_102),\n .I2(tempmon_state[10]),\n .O(\\tempmon_state[10]_i_10_n_0 ));\n LUT5 #(\n .INIT(32'hF0808080)) \n \\tempmon_state[10]_i_11 \n (.I0(tempmon_state[5]),\n .I1(temp_cmp_one_inc_min_102),\n .I2(update_temp_102),\n .I3(tempmon_state[4]),\n .I4(temp_cmp_two_inc_min_102),\n .O(\\tempmon_state[10]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'hFFEAEAEAEAEAEAEA)) \n \\tempmon_state[10]_i_12 \n (.I0(tempmon_state[1]),\n .I1(calib_complete),\n .I2(tempmon_state[0]),\n .I3(update_temp_102),\n .I4(tempmon_state[9]),\n .I5(temp_cmp_three_dec_min_102),\n .O(\\tempmon_state[10]_i_12_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair251\" *) \n LUT5 #(\n .INIT(32'h00010116)) \n \\tempmon_state[10]_i_13 \n (.I0(tempmon_state[0]),\n .I1(tempmon_state[1]),\n .I2(tempmon_state[2]),\n .I3(tempmon_state[3]),\n .I4(tempmon_state[4]),\n .O(\\tempmon_state[10]_i_13_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair251\" *) \n LUT5 #(\n .INIT(32'hFFFEFEE8)) \n \\tempmon_state[10]_i_14 \n (.I0(tempmon_state[0]),\n .I1(tempmon_state[1]),\n .I2(tempmon_state[2]),\n .I3(tempmon_state[3]),\n .I4(tempmon_state[4]),\n .O(\\tempmon_state[10]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'h0000000100010116)) \n \\tempmon_state[10]_i_15 \n (.I0(tempmon_state[5]),\n .I1(tempmon_state[6]),\n .I2(tempmon_state[7]),\n .I3(tempmon_state[8]),\n .I4(tempmon_state[9]),\n .I5(tempmon_state[10]),\n .O(\\tempmon_state[10]_i_15_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFEFFFEFEE8)) \n \\tempmon_state[10]_i_16 \n (.I0(tempmon_state[5]),\n .I1(tempmon_state[6]),\n .I2(tempmon_state[7]),\n .I3(tempmon_state[8]),\n .I4(tempmon_state[9]),\n .I5(tempmon_state[10]),\n .O(\\tempmon_state[10]_i_16_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair257\" *) \n LUT4 #(\n .INIT(16'h8000)) \n \\tempmon_state[10]_i_2 \n (.I0(tempmon_state[9]),\n .I1(\\tempmon_state[10]_i_7_n_0 ),\n .I2(temp_cmp_three_dec_max_102),\n .I3(update_temp_102),\n .O(\\tempmon_state[10]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFFF80)) \n \\tempmon_state[10]_i_3 \n (.I0(temp_cmp_four_inc_max_102),\n .I1(update_temp_102),\n .I2(tempmon_state[2]),\n .I3(\\tempmon_state[10]_i_8_n_0 ),\n .I4(\\tempmon_state[10]_i_9_n_0 ),\n .O(\\tempmon_state[10]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair250\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\tempmon_state[10]_i_4 \n (.I0(tempmon_state[6]),\n .I1(temp_cmp_neutral_min_102),\n .O(\\tempmon_state[10]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFAAEAAA)) \n \\tempmon_state[10]_i_5 \n (.I0(\\tempmon_state[10]_i_10_n_0 ),\n .I1(tempmon_state[3]),\n .I2(temp_cmp_three_inc_min_102),\n .I3(update_temp_102),\n .I4(pi_f_dec_i_2_n_0),\n .I5(\\tempmon_state[10]_i_11_n_0 ),\n .O(\\tempmon_state[10]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFFAAEAAAEAAAEAAA)) \n \\tempmon_state[10]_i_6 \n (.I0(\\tempmon_state[10]_i_12_n_0 ),\n .I1(temp_cmp_one_dec_min_102),\n .I2(tempmon_state[7]),\n .I3(update_temp_102),\n .I4(temp_cmp_two_dec_min_102),\n .I5(tempmon_state[8]),\n .O(\\tempmon_state[10]_i_6_n_0 ));\n LUT4 #(\n .INIT(16'h0012)) \n \\tempmon_state[10]_i_7 \n (.I0(\\tempmon_state[10]_i_13_n_0 ),\n .I1(\\tempmon_state[10]_i_14_n_0 ),\n .I2(\\tempmon_state[10]_i_15_n_0 ),\n .I3(\\tempmon_state[10]_i_16_n_0 ),\n .O(\\tempmon_state[10]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair252\" *) \n LUT5 #(\n .INIT(32'hF0808080)) \n \\tempmon_state[10]_i_8 \n (.I0(temp_cmp_two_dec_max_102),\n .I1(tempmon_state[8]),\n .I2(update_temp_102),\n .I3(temp_cmp_three_dec_max_102),\n .I4(tempmon_state[9]),\n .O(\\tempmon_state[10]_i_8_n_0 ));\n LUT5 #(\n .INIT(32'hF0808080)) \n \\tempmon_state[10]_i_9 \n (.I0(temp_cmp_neutral_max_102),\n .I1(tempmon_state[6]),\n .I2(update_temp_102),\n .I3(temp_cmp_one_dec_max_102),\n .I4(tempmon_state[7]),\n .O(\\tempmon_state[10]_i_9_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair257\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\tempmon_state[1]_i_1 \n (.I0(\\tempmon_state[10]_i_7_n_0 ),\n .I1(tempmon_state[0]),\n .O(\\tempmon_state[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair256\" *) \n LUT4 #(\n .INIT(16'h0888)) \n \\tempmon_state[2]_i_1 \n (.I0(tempmon_state[3]),\n .I1(\\tempmon_state[10]_i_7_n_0 ),\n .I2(update_temp_102),\n .I3(temp_cmp_three_inc_max_102),\n .O(\\tempmon_state[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair249\" *) \n LUT5 #(\n .INIT(32'hFF007000)) \n \\tempmon_state[3]_i_1 \n (.I0(temp_cmp_two_inc_max_102),\n .I1(update_temp_102),\n .I2(tempmon_state[4]),\n .I3(\\tempmon_state[10]_i_7_n_0 ),\n .I4(tempmon_state[2]),\n .O(\\tempmon_state[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8FFF000088000000)) \n \\tempmon_state[4]_i_1 \n (.I0(tempmon_state[3]),\n .I1(temp_cmp_three_inc_max_102),\n .I2(temp_cmp_one_inc_max_102),\n .I3(update_temp_102),\n .I4(\\tempmon_state[10]_i_7_n_0 ),\n .I5(tempmon_state[5]),\n .O(\\tempmon_state[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h8FFF000080800000)) \n \\tempmon_state[5]_i_1 \n (.I0(tempmon_state[4]),\n .I1(temp_cmp_two_inc_max_102),\n .I2(update_temp_102),\n .I3(temp_cmp_neutral_max_102),\n .I4(\\tempmon_state[10]_i_7_n_0 ),\n .I5(tempmon_state[6]),\n .O(\\tempmon_state[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFF00EE00AE00EE00)) \n \\tempmon_state[6]_i_1 \n (.I0(tempmon_state[1]),\n .I1(tempmon_state[7]),\n .I2(temp_cmp_one_dec_max_102),\n .I3(\\tempmon_state[10]_i_7_n_0 ),\n .I4(update_temp_102),\n .I5(\\tempmon_state[6]_i_2_n_0 ),\n .O(\\tempmon_state[6]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair254\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\tempmon_state[6]_i_2 \n (.I0(tempmon_state[5]),\n .I1(temp_cmp_one_inc_max_102),\n .O(\\tempmon_state[6]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFC4C00004C4C0000)) \n \\tempmon_state[7]_i_1 \n (.I0(temp_cmp_two_dec_max_102),\n .I1(tempmon_state[8]),\n .I2(update_temp_102),\n .I3(temp_cmp_neutral_max_102),\n .I4(\\tempmon_state[10]_i_7_n_0 ),\n .I5(tempmon_state[6]),\n .O(\\tempmon_state[7]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFC4C00004C4C0000)) \n \\tempmon_state[8]_i_1 \n (.I0(temp_cmp_three_dec_max_102),\n .I1(tempmon_state[9]),\n .I2(update_temp_102),\n .I3(temp_cmp_one_dec_max_102),\n .I4(\\tempmon_state[10]_i_7_n_0 ),\n .I5(tempmon_state[7]),\n .O(\\tempmon_state[8]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFF800000)) \n \\tempmon_state[9]_i_1 \n (.I0(update_temp_102),\n .I1(temp_cmp_two_dec_max_102),\n .I2(tempmon_state[8]),\n .I3(tempmon_state[10]),\n .I4(\\tempmon_state[10]_i_7_n_0 ),\n .O(\\tempmon_state[9]_i_1_n_0 ));\n FDSE \\tempmon_state_reg[0] \n (.C(CLK),\n .CE(tempmon_state_nxt),\n .D(\\tempmon_state[0]_i_2_n_0 ),\n .Q(tempmon_state[0]),\n .S(SS));\n FDRE \\tempmon_state_reg[10] \n (.C(CLK),\n .CE(tempmon_state_nxt),\n .D(\\tempmon_state[10]_i_2_n_0 ),\n .Q(tempmon_state[10]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\tempmon_state_reg[1] \n (.C(CLK),\n .CE(tempmon_state_nxt),\n .D(\\tempmon_state[1]_i_1_n_0 ),\n .Q(tempmon_state[1]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\tempmon_state_reg[2] \n (.C(CLK),\n .CE(tempmon_state_nxt),\n .D(\\tempmon_state[2]_i_1_n_0 ),\n .Q(tempmon_state[2]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\tempmon_state_reg[3] \n (.C(CLK),\n .CE(tempmon_state_nxt),\n .D(\\tempmon_state[3]_i_1_n_0 ),\n .Q(tempmon_state[3]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\tempmon_state_reg[4] \n (.C(CLK),\n .CE(tempmon_state_nxt),\n .D(\\tempmon_state[4]_i_1_n_0 ),\n .Q(tempmon_state[4]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\tempmon_state_reg[5] \n (.C(CLK),\n .CE(tempmon_state_nxt),\n .D(\\tempmon_state[5]_i_1_n_0 ),\n .Q(tempmon_state[5]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\tempmon_state_reg[6] \n (.C(CLK),\n .CE(tempmon_state_nxt),\n .D(\\tempmon_state[6]_i_1_n_0 ),\n .Q(tempmon_state[6]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\tempmon_state_reg[7] \n (.C(CLK),\n .CE(tempmon_state_nxt),\n .D(\\tempmon_state[7]_i_1_n_0 ),\n .Q(tempmon_state[7]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\tempmon_state_reg[8] \n (.C(CLK),\n .CE(tempmon_state_nxt),\n .D(\\tempmon_state[8]_i_1_n_0 ),\n .Q(tempmon_state[8]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\tempmon_state_reg[9] \n (.C(CLK),\n .CE(tempmon_state_nxt),\n .D(\\tempmon_state[9]_i_1_n_0 ),\n .Q(tempmon_state[9]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n (* SOFT_HLUTNM = \"soft_lutpair258\" *) \n LUT2 #(\n .INIT(4'hB)) \n \\three_dec_max_limit[0]_i_1 \n (.I0(p_0_in),\n .I1(device_temp_init[0]),\n .O(\\three_dec_max_limit[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair258\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\three_dec_max_limit[10]_i_1 \n (.I0(\\three_dec_max_limit_reg[11]_i_2_n_6 ),\n .I1(p_0_in),\n .O(\\three_dec_max_limit[10]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair260\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\three_dec_max_limit[11]_i_1 \n (.I0(\\three_dec_max_limit_reg[11]_i_2_n_5 ),\n .I1(p_0_in),\n .O(\\three_dec_max_limit[11]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\three_dec_max_limit[11]_i_3 \n (.I0(device_temp_init[11]),\n .O(\\three_dec_max_limit[11]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\three_dec_max_limit[11]_i_4 \n (.I0(device_temp_init[10]),\n .O(\\three_dec_max_limit[11]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_dec_max_limit[11]_i_5 \n (.I0(device_temp_init[9]),\n .O(\\three_dec_max_limit[11]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair263\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\three_dec_max_limit[1]_i_1 \n (.I0(\\three_dec_max_limit_reg[1]_i_2_n_0 ),\n .I1(p_0_in),\n .O(\\three_dec_max_limit[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair263\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\three_dec_max_limit[2]_i_1 \n (.I0(\\three_dec_max_limit_reg[4]_i_2_n_6 ),\n .I1(p_0_in),\n .O(\\three_dec_max_limit[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair259\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\three_dec_max_limit[3]_i_1 \n (.I0(\\three_dec_max_limit_reg[4]_i_2_n_5 ),\n .I1(p_0_in),\n .O(\\three_dec_max_limit[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair262\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\three_dec_max_limit[4]_i_1 \n (.I0(\\three_dec_max_limit_reg[4]_i_2_n_4 ),\n .I1(p_0_in),\n .O(\\three_dec_max_limit[4]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\three_dec_max_limit[4]_i_3 \n (.I0(device_temp_init[4]),\n .O(\\three_dec_max_limit[4]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\three_dec_max_limit[4]_i_4 \n (.I0(device_temp_init[3]),\n .O(\\three_dec_max_limit[4]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\three_dec_max_limit[4]_i_5 \n (.I0(device_temp_init[2]),\n .O(\\three_dec_max_limit[4]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\three_dec_max_limit[4]_i_6 \n (.I0(device_temp_init[1]),\n .O(\\three_dec_max_limit[4]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair262\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\three_dec_max_limit[5]_i_1 \n (.I0(\\three_dec_max_limit_reg[8]_i_2_n_7 ),\n .I1(p_0_in),\n .O(\\three_dec_max_limit[5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair259\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\three_dec_max_limit[6]_i_1 \n (.I0(\\three_dec_max_limit_reg[8]_i_2_n_6 ),\n .I1(p_0_in),\n .O(\\three_dec_max_limit[6]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair261\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\three_dec_max_limit[7]_i_1 \n (.I0(\\three_dec_max_limit_reg[8]_i_2_n_5 ),\n .I1(p_0_in),\n .O(\\three_dec_max_limit[7]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair260\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\three_dec_max_limit[8]_i_1 \n (.I0(\\three_dec_max_limit_reg[8]_i_2_n_4 ),\n .I1(p_0_in),\n .O(\\three_dec_max_limit[8]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_dec_max_limit[8]_i_3 \n (.I0(device_temp_init[8]),\n .O(\\three_dec_max_limit[8]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\three_dec_max_limit[8]_i_4 \n (.I0(device_temp_init[7]),\n .O(\\three_dec_max_limit[8]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_dec_max_limit[8]_i_5 \n (.I0(device_temp_init[6]),\n .O(\\three_dec_max_limit[8]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\three_dec_max_limit[8]_i_6 \n (.I0(device_temp_init[5]),\n .O(\\three_dec_max_limit[8]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair261\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\three_dec_max_limit[9]_i_1 \n (.I0(\\three_dec_max_limit_reg[11]_i_2_n_7 ),\n .I1(p_0_in),\n .O(\\three_dec_max_limit[9]_i_1_n_0 ));\n FDRE \\three_dec_max_limit_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\three_dec_max_limit[0]_i_1_n_0 ),\n .Q(three_dec_max_limit[0]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE \\three_dec_max_limit_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(\\three_dec_max_limit[10]_i_1_n_0 ),\n .Q(three_dec_max_limit[10]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE \\three_dec_max_limit_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(\\three_dec_max_limit[11]_i_1_n_0 ),\n .Q(three_dec_max_limit[11]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n CARRY4 \\three_dec_max_limit_reg[11]_i_2 \n (.CI(\\three_dec_max_limit_reg[8]_i_2_n_0 ),\n .CO({p_0_in,\\NLW_three_dec_max_limit_reg[11]_i_2_CO_UNCONNECTED [2],\\three_dec_max_limit_reg[11]_i_2_n_2 ,\\three_dec_max_limit_reg[11]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,device_temp_init[9]}),\n .O({\\NLW_three_dec_max_limit_reg[11]_i_2_O_UNCONNECTED [3],\\three_dec_max_limit_reg[11]_i_2_n_5 ,\\three_dec_max_limit_reg[11]_i_2_n_6 ,\\three_dec_max_limit_reg[11]_i_2_n_7 }),\n .S({1'b1,\\three_dec_max_limit[11]_i_3_n_0 ,\\three_dec_max_limit[11]_i_4_n_0 ,\\three_dec_max_limit[11]_i_5_n_0 }));\n FDRE \\three_dec_max_limit_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\three_dec_max_limit[1]_i_1_n_0 ),\n .Q(three_dec_max_limit[1]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n (* XILINX_LEGACY_PRIM = \"(MUXCY,XORCY)\" *) \n CARRY4 \\three_dec_max_limit_reg[1]_i_2_CARRY4 \n (.CI(1'b0),\n .CO(\\NLW_three_dec_max_limit_reg[1]_i_2_CARRY4_CO_UNCONNECTED [3:0]),\n .CYINIT(device_temp_init[0]),\n .DI(\\NLW_three_dec_max_limit_reg[1]_i_2_CARRY4_DI_UNCONNECTED [3:0]),\n .O({\\NLW_three_dec_max_limit_reg[1]_i_2_CARRY4_O_UNCONNECTED [3:1],\\three_dec_max_limit_reg[1]_i_2_n_0 }),\n .S({\\NLW_three_dec_max_limit_reg[1]_i_2_CARRY4_S_UNCONNECTED [3:1],device_temp_init[1]}));\n FDRE \\three_dec_max_limit_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\three_dec_max_limit[2]_i_1_n_0 ),\n .Q(three_dec_max_limit[2]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE \\three_dec_max_limit_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\three_dec_max_limit[3]_i_1_n_0 ),\n .Q(three_dec_max_limit[3]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE \\three_dec_max_limit_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\three_dec_max_limit[4]_i_1_n_0 ),\n .Q(three_dec_max_limit[4]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n CARRY4 \\three_dec_max_limit_reg[4]_i_2 \n (.CI(1'b0),\n .CO({\\three_dec_max_limit_reg[4]_i_2_n_0 ,\\three_dec_max_limit_reg[4]_i_2_n_1 ,\\three_dec_max_limit_reg[4]_i_2_n_2 ,\\three_dec_max_limit_reg[4]_i_2_n_3 }),\n .CYINIT(device_temp_init[0]),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\three_dec_max_limit_reg[4]_i_2_n_4 ,\\three_dec_max_limit_reg[4]_i_2_n_5 ,\\three_dec_max_limit_reg[4]_i_2_n_6 ,\\NLW_three_dec_max_limit_reg[4]_i_2_O_UNCONNECTED [0]}),\n .S({\\three_dec_max_limit[4]_i_3_n_0 ,\\three_dec_max_limit[4]_i_4_n_0 ,\\three_dec_max_limit[4]_i_5_n_0 ,\\three_dec_max_limit[4]_i_6_n_0 }));\n FDRE \\three_dec_max_limit_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\three_dec_max_limit[5]_i_1_n_0 ),\n .Q(three_dec_max_limit[5]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE \\three_dec_max_limit_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\three_dec_max_limit[6]_i_1_n_0 ),\n .Q(three_dec_max_limit[6]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE \\three_dec_max_limit_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\three_dec_max_limit[7]_i_1_n_0 ),\n .Q(three_dec_max_limit[7]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE \\three_dec_max_limit_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(\\three_dec_max_limit[8]_i_1_n_0 ),\n .Q(three_dec_max_limit[8]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n CARRY4 \\three_dec_max_limit_reg[8]_i_2 \n (.CI(\\three_dec_max_limit_reg[4]_i_2_n_0 ),\n .CO({\\three_dec_max_limit_reg[8]_i_2_n_0 ,\\three_dec_max_limit_reg[8]_i_2_n_1 ,\\three_dec_max_limit_reg[8]_i_2_n_2 ,\\three_dec_max_limit_reg[8]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({device_temp_init[8],1'b0,device_temp_init[6],1'b0}),\n .O({\\three_dec_max_limit_reg[8]_i_2_n_4 ,\\three_dec_max_limit_reg[8]_i_2_n_5 ,\\three_dec_max_limit_reg[8]_i_2_n_6 ,\\three_dec_max_limit_reg[8]_i_2_n_7 }),\n .S({\\three_dec_max_limit[8]_i_3_n_0 ,\\three_dec_max_limit[8]_i_4_n_0 ,\\three_dec_max_limit[8]_i_5_n_0 ,\\three_dec_max_limit[8]_i_6_n_0 }));\n FDRE \\three_dec_max_limit_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(\\three_dec_max_limit[9]_i_1_n_0 ),\n .Q(three_dec_max_limit[9]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n LUT1 #(\n .INIT(2'h1)) \n \\three_dec_min_limit[11]_i_2 \n (.I0(two_dec_max_limit[11]),\n .O(\\three_dec_min_limit[11]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_dec_min_limit[11]_i_3 \n (.I0(two_dec_max_limit[10]),\n .O(\\three_dec_min_limit[11]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_dec_min_limit[5]_i_2 \n (.I0(two_dec_max_limit[5]),\n .O(\\three_dec_min_limit[5]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_dec_min_limit[5]_i_3 \n (.I0(two_dec_max_limit[4]),\n .O(\\three_dec_min_limit[5]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_dec_min_limit[5]_i_4 \n (.I0(two_dec_max_limit[3]),\n .O(\\three_dec_min_limit[5]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\three_dec_min_limit[5]_i_5 \n (.I0(two_dec_max_limit[2]),\n .O(\\three_dec_min_limit[5]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_dec_min_limit[9]_i_2 \n (.I0(two_dec_max_limit[9]),\n .O(\\three_dec_min_limit[9]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_dec_min_limit[9]_i_3 \n (.I0(two_dec_max_limit[8]),\n .O(\\three_dec_min_limit[9]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_dec_min_limit[9]_i_4 \n (.I0(two_dec_max_limit[7]),\n .O(\\three_dec_min_limit[9]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_dec_min_limit[9]_i_5 \n (.I0(two_dec_max_limit[6]),\n .O(\\three_dec_min_limit[9]_i_5_n_0 ));\n FDRE \\three_dec_min_limit_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_max_limit[0]),\n .Q(three_dec_min_limit[0]),\n .R(SS));\n FDRE \\three_dec_min_limit_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(three_dec_min_limit_nxt[10]),\n .Q(three_dec_min_limit[10]),\n .R(SS));\n FDRE \\three_dec_min_limit_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(three_dec_min_limit_nxt[11]),\n .Q(three_dec_min_limit[11]),\n .R(SS));\n CARRY4 \\three_dec_min_limit_reg[11]_i_1 \n (.CI(\\three_dec_min_limit_reg[9]_i_1_n_0 ),\n .CO({\\NLW_three_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\\three_dec_min_limit_reg[11]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,two_dec_max_limit[10]}),\n .O({\\NLW_three_dec_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],three_dec_min_limit_nxt[11:10]}),\n .S({1'b0,1'b0,\\three_dec_min_limit[11]_i_2_n_0 ,\\three_dec_min_limit[11]_i_3_n_0 }));\n FDRE \\three_dec_min_limit_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_max_limit[1]),\n .Q(three_dec_min_limit[1]),\n .R(SS));\n FDRE \\three_dec_min_limit_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(three_dec_min_limit_nxt[2]),\n .Q(three_dec_min_limit[2]),\n .R(SS));\n FDRE \\three_dec_min_limit_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(three_dec_min_limit_nxt[3]),\n .Q(three_dec_min_limit[3]),\n .R(SS));\n FDRE \\three_dec_min_limit_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(three_dec_min_limit_nxt[4]),\n .Q(three_dec_min_limit[4]),\n .R(SS));\n FDRE \\three_dec_min_limit_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(three_dec_min_limit_nxt[5]),\n .Q(three_dec_min_limit[5]),\n .R(SS));\n CARRY4 \\three_dec_min_limit_reg[5]_i_1 \n (.CI(1'b0),\n .CO({\\three_dec_min_limit_reg[5]_i_1_n_0 ,\\three_dec_min_limit_reg[5]_i_1_n_1 ,\\three_dec_min_limit_reg[5]_i_1_n_2 ,\\three_dec_min_limit_reg[5]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({two_dec_max_limit[5:3],1'b0}),\n .O(three_dec_min_limit_nxt[5:2]),\n .S({\\three_dec_min_limit[5]_i_2_n_0 ,\\three_dec_min_limit[5]_i_3_n_0 ,\\three_dec_min_limit[5]_i_4_n_0 ,\\three_dec_min_limit[5]_i_5_n_0 }));\n FDRE \\three_dec_min_limit_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(three_dec_min_limit_nxt[6]),\n .Q(three_dec_min_limit[6]),\n .R(SS));\n FDRE \\three_dec_min_limit_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(three_dec_min_limit_nxt[7]),\n .Q(three_dec_min_limit[7]),\n .R(SS));\n FDRE \\three_dec_min_limit_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(three_dec_min_limit_nxt[8]),\n .Q(three_dec_min_limit[8]),\n .R(SS));\n FDRE \\three_dec_min_limit_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(three_dec_min_limit_nxt[9]),\n .Q(three_dec_min_limit[9]),\n .R(SS));\n CARRY4 \\three_dec_min_limit_reg[9]_i_1 \n (.CI(\\three_dec_min_limit_reg[5]_i_1_n_0 ),\n .CO({\\three_dec_min_limit_reg[9]_i_1_n_0 ,\\three_dec_min_limit_reg[9]_i_1_n_1 ,\\three_dec_min_limit_reg[9]_i_1_n_2 ,\\three_dec_min_limit_reg[9]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI(two_dec_max_limit[9:6]),\n .O(three_dec_min_limit_nxt[9:6]),\n .S({\\three_dec_min_limit[9]_i_2_n_0 ,\\three_dec_min_limit[9]_i_3_n_0 ,\\three_dec_min_limit[9]_i_4_n_0 ,\\three_dec_min_limit[9]_i_5_n_0 }));\n LUT1 #(\n .INIT(2'h1)) \n \\three_inc_max_limit[11]_i_2 \n (.I0(device_temp_init[11]),\n .O(\\three_inc_max_limit[11]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_inc_max_limit[11]_i_3 \n (.I0(device_temp_init[10]),\n .O(\\three_inc_max_limit[11]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\three_inc_max_limit[11]_i_4 \n (.I0(device_temp_init[9]),\n .O(\\three_inc_max_limit[11]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\three_inc_max_limit[4]_i_2 \n (.I0(device_temp_init[4]),\n .O(\\three_inc_max_limit[4]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_inc_max_limit[4]_i_3 \n (.I0(device_temp_init[3]),\n .O(\\three_inc_max_limit[4]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_inc_max_limit[4]_i_4 \n (.I0(device_temp_init[2]),\n .O(\\three_inc_max_limit[4]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\three_inc_max_limit[4]_i_5 \n (.I0(device_temp_init[1]),\n .O(\\three_inc_max_limit[4]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_inc_max_limit[8]_i_2 \n (.I0(device_temp_init[8]),\n .O(\\three_inc_max_limit[8]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_inc_max_limit[8]_i_3 \n (.I0(device_temp_init[7]),\n .O(\\three_inc_max_limit[8]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\three_inc_max_limit[8]_i_4 \n (.I0(device_temp_init[6]),\n .O(\\three_inc_max_limit[8]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_inc_max_limit[8]_i_5 \n (.I0(device_temp_init[5]),\n .O(\\three_inc_max_limit[8]_i_5_n_0 ));\n FDRE \\three_inc_max_limit_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_max_limit_nxt[10]),\n .Q(three_inc_max_limit[10]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE \\three_inc_max_limit_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_max_limit_nxt[11]),\n .Q(three_inc_max_limit[11]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n CARRY4 \\three_inc_max_limit_reg[11]_i_1 \n (.CI(\\three_inc_max_limit_reg[8]_i_1_n_0 ),\n .CO({\\NLW_three_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\\three_inc_max_limit_reg[11]_i_1_n_2 ,\\three_inc_max_limit_reg[11]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,device_temp_init[10],1'b0}),\n .O({\\NLW_three_inc_max_limit_reg[11]_i_1_O_UNCONNECTED [3],three_inc_max_limit_nxt[11:9]}),\n .S({1'b0,\\three_inc_max_limit[11]_i_2_n_0 ,\\three_inc_max_limit[11]_i_3_n_0 ,\\three_inc_max_limit[11]_i_4_n_0 }));\n FDRE \\three_inc_max_limit_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_max_limit_nxt[1]),\n .Q(three_inc_max_limit[1]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE \\three_inc_max_limit_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_max_limit_nxt[2]),\n .Q(three_inc_max_limit[2]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE \\three_inc_max_limit_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_max_limit_nxt[3]),\n .Q(three_inc_max_limit[3]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE \\three_inc_max_limit_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_max_limit_nxt[4]),\n .Q(three_inc_max_limit[4]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n CARRY4 \\three_inc_max_limit_reg[4]_i_1 \n (.CI(1'b0),\n .CO({\\three_inc_max_limit_reg[4]_i_1_n_0 ,\\three_inc_max_limit_reg[4]_i_1_n_1 ,\\three_inc_max_limit_reg[4]_i_1_n_2 ,\\three_inc_max_limit_reg[4]_i_1_n_3 }),\n .CYINIT(device_temp_init[0]),\n .DI({1'b0,device_temp_init[3:2],1'b0}),\n .O(three_inc_max_limit_nxt[4:1]),\n .S({\\three_inc_max_limit[4]_i_2_n_0 ,\\three_inc_max_limit[4]_i_3_n_0 ,\\three_inc_max_limit[4]_i_4_n_0 ,\\three_inc_max_limit[4]_i_5_n_0 }));\n FDRE \\three_inc_max_limit_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_max_limit_nxt[5]),\n .Q(three_inc_max_limit[5]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE \\three_inc_max_limit_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_max_limit_nxt[6]),\n .Q(three_inc_max_limit[6]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE \\three_inc_max_limit_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_max_limit_nxt[7]),\n .Q(three_inc_max_limit[7]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE \\three_inc_max_limit_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_max_limit_nxt[8]),\n .Q(three_inc_max_limit[8]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n CARRY4 \\three_inc_max_limit_reg[8]_i_1 \n (.CI(\\three_inc_max_limit_reg[4]_i_1_n_0 ),\n .CO({\\three_inc_max_limit_reg[8]_i_1_n_0 ,\\three_inc_max_limit_reg[8]_i_1_n_1 ,\\three_inc_max_limit_reg[8]_i_1_n_2 ,\\three_inc_max_limit_reg[8]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({device_temp_init[8:7],1'b0,device_temp_init[5]}),\n .O(three_inc_max_limit_nxt[8:5]),\n .S({\\three_inc_max_limit[8]_i_2_n_0 ,\\three_inc_max_limit[8]_i_3_n_0 ,\\three_inc_max_limit[8]_i_4_n_0 ,\\three_inc_max_limit[8]_i_5_n_0 }));\n FDRE \\three_inc_max_limit_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_max_limit_nxt[9]),\n .Q(three_inc_max_limit[9]),\n .R(rstdiv0_sync_r1_reg_rep__6));\n LUT1 #(\n .INIT(2'h1)) \n \\three_inc_min_limit[11]_i_2 \n (.I0(four_inc_max_limit[11]),\n .O(\\three_inc_min_limit[11]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_inc_min_limit[11]_i_3 \n (.I0(four_inc_max_limit[10]),\n .O(\\three_inc_min_limit[11]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_inc_min_limit[5]_i_2 \n (.I0(four_inc_max_limit[5]),\n .O(\\three_inc_min_limit[5]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_inc_min_limit[5]_i_3 \n (.I0(four_inc_max_limit[4]),\n .O(\\three_inc_min_limit[5]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_inc_min_limit[5]_i_4 \n (.I0(four_inc_max_limit[3]),\n .O(\\three_inc_min_limit[5]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\three_inc_min_limit[5]_i_5 \n (.I0(four_inc_max_limit[2]),\n .O(\\three_inc_min_limit[5]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_inc_min_limit[9]_i_2 \n (.I0(four_inc_max_limit[9]),\n .O(\\three_inc_min_limit[9]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_inc_min_limit[9]_i_3 \n (.I0(four_inc_max_limit[8]),\n .O(\\three_inc_min_limit[9]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_inc_min_limit[9]_i_4 \n (.I0(four_inc_max_limit[7]),\n .O(\\three_inc_min_limit[9]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\three_inc_min_limit[9]_i_5 \n (.I0(four_inc_max_limit[6]),\n .O(\\three_inc_min_limit[9]_i_5_n_0 ));\n FDRE \\three_inc_min_limit_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_min_limit_nxt[10]),\n .Q(three_inc_min_limit[10]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\three_inc_min_limit_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_min_limit_nxt[11]),\n .Q(three_inc_min_limit[11]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n CARRY4 \\three_inc_min_limit_reg[11]_i_1 \n (.CI(\\three_inc_min_limit_reg[9]_i_1_n_0 ),\n .CO({\\NLW_three_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\\three_inc_min_limit_reg[11]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,four_inc_max_limit[10]}),\n .O({\\NLW_three_inc_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],three_inc_min_limit_nxt[11:10]}),\n .S({1'b0,1'b0,\\three_inc_min_limit[11]_i_2_n_0 ,\\three_inc_min_limit[11]_i_3_n_0 }));\n FDRE \\three_inc_min_limit_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(four_inc_max_limit[1]),\n .Q(three_inc_min_limit[1]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\three_inc_min_limit_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_min_limit_nxt[2]),\n .Q(three_inc_min_limit[2]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\three_inc_min_limit_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_min_limit_nxt[3]),\n .Q(three_inc_min_limit[3]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\three_inc_min_limit_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_min_limit_nxt[4]),\n .Q(three_inc_min_limit[4]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\three_inc_min_limit_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_min_limit_nxt[5]),\n .Q(three_inc_min_limit[5]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n CARRY4 \\three_inc_min_limit_reg[5]_i_1 \n (.CI(1'b0),\n .CO({\\three_inc_min_limit_reg[5]_i_1_n_0 ,\\three_inc_min_limit_reg[5]_i_1_n_1 ,\\three_inc_min_limit_reg[5]_i_1_n_2 ,\\three_inc_min_limit_reg[5]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({four_inc_max_limit[5:3],1'b0}),\n .O(three_inc_min_limit_nxt[5:2]),\n .S({\\three_inc_min_limit[5]_i_2_n_0 ,\\three_inc_min_limit[5]_i_3_n_0 ,\\three_inc_min_limit[5]_i_4_n_0 ,\\three_inc_min_limit[5]_i_5_n_0 }));\n FDRE \\three_inc_min_limit_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_min_limit_nxt[6]),\n .Q(three_inc_min_limit[6]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\three_inc_min_limit_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_min_limit_nxt[7]),\n .Q(three_inc_min_limit[7]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\three_inc_min_limit_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_min_limit_nxt[8]),\n .Q(three_inc_min_limit[8]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\three_inc_min_limit_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_min_limit_nxt[9]),\n .Q(three_inc_min_limit[9]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n CARRY4 \\three_inc_min_limit_reg[9]_i_1 \n (.CI(\\three_inc_min_limit_reg[5]_i_1_n_0 ),\n .CO({\\three_inc_min_limit_reg[9]_i_1_n_0 ,\\three_inc_min_limit_reg[9]_i_1_n_1 ,\\three_inc_min_limit_reg[9]_i_1_n_2 ,\\three_inc_min_limit_reg[9]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI(four_inc_max_limit[9:6]),\n .O(three_inc_min_limit_nxt[9:6]),\n .S({\\three_inc_min_limit[9]_i_2_n_0 ,\\three_inc_min_limit[9]_i_3_n_0 ,\\three_inc_min_limit[9]_i_4_n_0 ,\\three_inc_min_limit[9]_i_5_n_0 }));\n LUT1 #(\n .INIT(2'h1)) \n \\two_dec_max_limit[0]_i_1 \n (.I0(device_temp_init[0]),\n .O(\\two_dec_max_limit[0]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\two_dec_max_limit[11]_i_2 \n (.I0(device_temp_init[11]),\n .O(\\two_dec_max_limit[11]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\two_dec_max_limit[11]_i_3 \n (.I0(device_temp_init[10]),\n .O(\\two_dec_max_limit[11]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_dec_max_limit[11]_i_4 \n (.I0(device_temp_init[9]),\n .O(\\two_dec_max_limit[11]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_dec_max_limit[4]_i_2 \n (.I0(device_temp_init[4]),\n .O(\\two_dec_max_limit[4]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\two_dec_max_limit[4]_i_3 \n (.I0(device_temp_init[3]),\n .O(\\two_dec_max_limit[4]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\two_dec_max_limit[4]_i_4 \n (.I0(device_temp_init[2]),\n .O(\\two_dec_max_limit[4]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_dec_max_limit[4]_i_5 \n (.I0(device_temp_init[1]),\n .O(\\two_dec_max_limit[4]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\two_dec_max_limit[8]_i_2 \n (.I0(device_temp_init[8]),\n .O(\\two_dec_max_limit[8]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\two_dec_max_limit[8]_i_3 \n (.I0(device_temp_init[7]),\n .O(\\two_dec_max_limit[8]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_dec_max_limit[8]_i_4 \n (.I0(device_temp_init[6]),\n .O(\\two_dec_max_limit[8]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\two_dec_max_limit[8]_i_5 \n (.I0(device_temp_init[5]),\n .O(\\two_dec_max_limit[8]_i_5_n_0 ));\n FDRE \\two_dec_max_limit_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\two_dec_max_limit[0]_i_1_n_0 ),\n .Q(two_dec_max_limit[0]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE \\two_dec_max_limit_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_max_limit_nxt[10]),\n .Q(two_dec_max_limit[10]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE \\two_dec_max_limit_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_max_limit_nxt[11]),\n .Q(two_dec_max_limit[11]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n CARRY4 \\two_dec_max_limit_reg[11]_i_1 \n (.CI(\\two_dec_max_limit_reg[8]_i_1_n_0 ),\n .CO({\\NLW_two_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\\two_dec_max_limit_reg[11]_i_1_n_2 ,\\two_dec_max_limit_reg[11]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,device_temp_init[9]}),\n .O({\\NLW_two_dec_max_limit_reg[11]_i_1_O_UNCONNECTED [3],two_dec_max_limit_nxt[11:9]}),\n .S({1'b0,\\two_dec_max_limit[11]_i_2_n_0 ,\\two_dec_max_limit[11]_i_3_n_0 ,\\two_dec_max_limit[11]_i_4_n_0 }));\n FDRE \\two_dec_max_limit_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_max_limit_nxt[1]),\n .Q(two_dec_max_limit[1]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n (* XILINX_LEGACY_PRIM = \"(MUXCY,XORCY)\" *) \n CARRY4 \\two_dec_max_limit_reg[1]_i_1_CARRY4 \n (.CI(1'b0),\n .CO(\\NLW_two_dec_max_limit_reg[1]_i_1_CARRY4_CO_UNCONNECTED [3:0]),\n .CYINIT(device_temp_init[0]),\n .DI(\\NLW_two_dec_max_limit_reg[1]_i_1_CARRY4_DI_UNCONNECTED [3:0]),\n .O({\\NLW_two_dec_max_limit_reg[1]_i_1_CARRY4_O_UNCONNECTED [3:1],two_dec_max_limit_nxt[1]}),\n .S({\\NLW_two_dec_max_limit_reg[1]_i_1_CARRY4_S_UNCONNECTED [3:1],\\four_inc_max_limit[1]_i_2_n_0 }));\n FDRE \\two_dec_max_limit_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_max_limit_nxt[2]),\n .Q(two_dec_max_limit[2]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE \\two_dec_max_limit_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_max_limit_nxt[3]),\n .Q(two_dec_max_limit[3]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE \\two_dec_max_limit_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_max_limit_nxt[4]),\n .Q(two_dec_max_limit[4]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n CARRY4 \\two_dec_max_limit_reg[4]_i_1 \n (.CI(1'b0),\n .CO({\\two_dec_max_limit_reg[4]_i_1_n_0 ,\\two_dec_max_limit_reg[4]_i_1_n_1 ,\\two_dec_max_limit_reg[4]_i_1_n_2 ,\\two_dec_max_limit_reg[4]_i_1_n_3 }),\n .CYINIT(device_temp_init[0]),\n .DI({device_temp_init[4],1'b0,1'b0,device_temp_init[1]}),\n .O({two_dec_max_limit_nxt[4:2],\\NLW_two_dec_max_limit_reg[4]_i_1_O_UNCONNECTED [0]}),\n .S({\\two_dec_max_limit[4]_i_2_n_0 ,\\two_dec_max_limit[4]_i_3_n_0 ,\\two_dec_max_limit[4]_i_4_n_0 ,\\two_dec_max_limit[4]_i_5_n_0 }));\n FDRE \\two_dec_max_limit_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_max_limit_nxt[5]),\n .Q(two_dec_max_limit[5]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE \\two_dec_max_limit_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_max_limit_nxt[6]),\n .Q(two_dec_max_limit[6]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE \\two_dec_max_limit_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_max_limit_nxt[7]),\n .Q(two_dec_max_limit[7]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n FDRE \\two_dec_max_limit_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_max_limit_nxt[8]),\n .Q(two_dec_max_limit[8]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n CARRY4 \\two_dec_max_limit_reg[8]_i_1 \n (.CI(\\two_dec_max_limit_reg[4]_i_1_n_0 ),\n .CO({\\two_dec_max_limit_reg[8]_i_1_n_0 ,\\two_dec_max_limit_reg[8]_i_1_n_1 ,\\two_dec_max_limit_reg[8]_i_1_n_2 ,\\two_dec_max_limit_reg[8]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,device_temp_init[6],1'b0}),\n .O(two_dec_max_limit_nxt[8:5]),\n .S({\\two_dec_max_limit[8]_i_2_n_0 ,\\two_dec_max_limit[8]_i_3_n_0 ,\\two_dec_max_limit[8]_i_4_n_0 ,\\two_dec_max_limit[8]_i_5_n_0 }));\n FDRE \\two_dec_max_limit_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_max_limit_nxt[9]),\n .Q(two_dec_max_limit[9]),\n .R(rstdiv0_sync_r1_reg_rep__7));\n LUT1 #(\n .INIT(2'h1)) \n \\two_dec_min_limit[11]_i_2 \n (.I0(one_dec_max_limit[11]),\n .O(\\two_dec_min_limit[11]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_dec_min_limit[11]_i_3 \n (.I0(one_dec_max_limit[10]),\n .O(\\two_dec_min_limit[11]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_dec_min_limit[5]_i_2 \n (.I0(one_dec_max_limit[5]),\n .O(\\two_dec_min_limit[5]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_dec_min_limit[5]_i_3 \n (.I0(one_dec_max_limit[4]),\n .O(\\two_dec_min_limit[5]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_dec_min_limit[5]_i_4 \n (.I0(one_dec_max_limit[3]),\n .O(\\two_dec_min_limit[5]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\two_dec_min_limit[5]_i_5 \n (.I0(one_dec_max_limit[2]),\n .O(\\two_dec_min_limit[5]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_dec_min_limit[9]_i_2 \n (.I0(one_dec_max_limit[9]),\n .O(\\two_dec_min_limit[9]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_dec_min_limit[9]_i_3 \n (.I0(one_dec_max_limit[8]),\n .O(\\two_dec_min_limit[9]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_dec_min_limit[9]_i_4 \n (.I0(one_dec_max_limit[7]),\n .O(\\two_dec_min_limit[9]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_dec_min_limit[9]_i_5 \n (.I0(one_dec_max_limit[6]),\n .O(\\two_dec_min_limit[9]_i_5_n_0 ));\n FDRE \\two_dec_min_limit_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_min_limit_nxt[10]),\n .Q(two_dec_min_limit[10]),\n .R(SS));\n FDRE \\two_dec_min_limit_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_min_limit_nxt[11]),\n .Q(two_dec_min_limit[11]),\n .R(SS));\n CARRY4 \\two_dec_min_limit_reg[11]_i_1 \n (.CI(\\two_dec_min_limit_reg[9]_i_1_n_0 ),\n .CO({\\NLW_two_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\\two_dec_min_limit_reg[11]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,one_dec_max_limit[10]}),\n .O({\\NLW_two_dec_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],two_dec_min_limit_nxt[11:10]}),\n .S({1'b0,1'b0,\\two_dec_min_limit[11]_i_2_n_0 ,\\two_dec_min_limit[11]_i_3_n_0 }));\n FDRE \\two_dec_min_limit_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(one_dec_max_limit[1]),\n .Q(two_dec_min_limit[1]),\n .R(SS));\n FDRE \\two_dec_min_limit_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_min_limit_nxt[2]),\n .Q(two_dec_min_limit[2]),\n .R(SS));\n FDRE \\two_dec_min_limit_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_min_limit_nxt[3]),\n .Q(two_dec_min_limit[3]),\n .R(SS));\n FDRE \\two_dec_min_limit_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_min_limit_nxt[4]),\n .Q(two_dec_min_limit[4]),\n .R(SS));\n FDRE \\two_dec_min_limit_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_min_limit_nxt[5]),\n .Q(two_dec_min_limit[5]),\n .R(SS));\n CARRY4 \\two_dec_min_limit_reg[5]_i_1 \n (.CI(1'b0),\n .CO({\\two_dec_min_limit_reg[5]_i_1_n_0 ,\\two_dec_min_limit_reg[5]_i_1_n_1 ,\\two_dec_min_limit_reg[5]_i_1_n_2 ,\\two_dec_min_limit_reg[5]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({one_dec_max_limit[5:3],1'b0}),\n .O(two_dec_min_limit_nxt[5:2]),\n .S({\\two_dec_min_limit[5]_i_2_n_0 ,\\two_dec_min_limit[5]_i_3_n_0 ,\\two_dec_min_limit[5]_i_4_n_0 ,\\two_dec_min_limit[5]_i_5_n_0 }));\n FDRE \\two_dec_min_limit_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_min_limit_nxt[6]),\n .Q(two_dec_min_limit[6]),\n .R(SS));\n FDRE \\two_dec_min_limit_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_min_limit_nxt[7]),\n .Q(two_dec_min_limit[7]),\n .R(SS));\n FDRE \\two_dec_min_limit_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_min_limit_nxt[8]),\n .Q(two_dec_min_limit[8]),\n .R(SS));\n FDRE \\two_dec_min_limit_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(two_dec_min_limit_nxt[9]),\n .Q(two_dec_min_limit[9]),\n .R(SS));\n CARRY4 \\two_dec_min_limit_reg[9]_i_1 \n (.CI(\\two_dec_min_limit_reg[5]_i_1_n_0 ),\n .CO({\\two_dec_min_limit_reg[9]_i_1_n_0 ,\\two_dec_min_limit_reg[9]_i_1_n_1 ,\\two_dec_min_limit_reg[9]_i_1_n_2 ,\\two_dec_min_limit_reg[9]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI(one_dec_max_limit[9:6]),\n .O(two_dec_min_limit_nxt[9:6]),\n .S({\\two_dec_min_limit[9]_i_2_n_0 ,\\two_dec_min_limit[9]_i_3_n_0 ,\\two_dec_min_limit[9]_i_4_n_0 ,\\two_dec_min_limit[9]_i_5_n_0 }));\n LUT1 #(\n .INIT(2'h1)) \n \\two_inc_max_limit[11]_i_2 \n (.I0(device_temp_init[11]),\n .O(\\two_inc_max_limit[11]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_inc_max_limit[11]_i_3 \n (.I0(device_temp_init[10]),\n .O(\\two_inc_max_limit[11]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_inc_max_limit[11]_i_4 \n (.I0(device_temp_init[9]),\n .O(\\two_inc_max_limit[11]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_inc_max_limit[4]_i_2 \n (.I0(device_temp_init[4]),\n .O(\\two_inc_max_limit[4]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_inc_max_limit[4]_i_3 \n (.I0(device_temp_init[3]),\n .O(\\two_inc_max_limit[4]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\two_inc_max_limit[4]_i_4 \n (.I0(device_temp_init[2]),\n .O(\\two_inc_max_limit[4]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_inc_max_limit[4]_i_5 \n (.I0(device_temp_init[1]),\n .O(\\two_inc_max_limit[4]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\two_inc_max_limit[8]_i_2 \n (.I0(device_temp_init[8]),\n .O(\\two_inc_max_limit[8]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_inc_max_limit[8]_i_3 \n (.I0(device_temp_init[7]),\n .O(\\two_inc_max_limit[8]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\two_inc_max_limit[8]_i_4 \n (.I0(device_temp_init[6]),\n .O(\\two_inc_max_limit[8]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\two_inc_max_limit[8]_i_5 \n (.I0(device_temp_init[5]),\n .O(\\two_inc_max_limit[8]_i_5_n_0 ));\n FDRE \\two_inc_max_limit_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_max_limit_nxt[10]),\n .Q(two_inc_max_limit[10]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE \\two_inc_max_limit_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_max_limit_nxt[11]),\n .Q(two_inc_max_limit[11]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n CARRY4 \\two_inc_max_limit_reg[11]_i_1 \n (.CI(\\two_inc_max_limit_reg[8]_i_1_n_0 ),\n .CO({\\NLW_two_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\\two_inc_max_limit_reg[11]_i_1_n_2 ,\\two_inc_max_limit_reg[11]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,device_temp_init[10:9]}),\n .O({\\NLW_two_inc_max_limit_reg[11]_i_1_O_UNCONNECTED [3],two_inc_max_limit_nxt[11:9]}),\n .S({1'b0,\\two_inc_max_limit[11]_i_2_n_0 ,\\two_inc_max_limit[11]_i_3_n_0 ,\\two_inc_max_limit[11]_i_4_n_0 }));\n FDRE \\two_inc_max_limit_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_max_limit_nxt[1]),\n .Q(two_inc_max_limit[1]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE \\two_inc_max_limit_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_max_limit_nxt[2]),\n .Q(two_inc_max_limit[2]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE \\two_inc_max_limit_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_max_limit_nxt[3]),\n .Q(two_inc_max_limit[3]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE \\two_inc_max_limit_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_max_limit_nxt[4]),\n .Q(two_inc_max_limit[4]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n CARRY4 \\two_inc_max_limit_reg[4]_i_1 \n (.CI(1'b0),\n .CO({\\two_inc_max_limit_reg[4]_i_1_n_0 ,\\two_inc_max_limit_reg[4]_i_1_n_1 ,\\two_inc_max_limit_reg[4]_i_1_n_2 ,\\two_inc_max_limit_reg[4]_i_1_n_3 }),\n .CYINIT(device_temp_init[0]),\n .DI({device_temp_init[4:3],1'b0,device_temp_init[1]}),\n .O({two_inc_max_limit_nxt[4:2],\\NLW_two_inc_max_limit_reg[4]_i_1_O_UNCONNECTED [0]}),\n .S({\\two_inc_max_limit[4]_i_2_n_0 ,\\two_inc_max_limit[4]_i_3_n_0 ,\\two_inc_max_limit[4]_i_4_n_0 ,\\two_inc_max_limit[4]_i_5_n_0 }));\n FDRE \\two_inc_max_limit_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_max_limit_nxt[5]),\n .Q(two_inc_max_limit[5]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE \\two_inc_max_limit_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_max_limit_nxt[6]),\n .Q(two_inc_max_limit[6]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE \\two_inc_max_limit_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_max_limit_nxt[7]),\n .Q(two_inc_max_limit[7]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE \\two_inc_max_limit_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_max_limit_nxt[8]),\n .Q(two_inc_max_limit[8]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n CARRY4 \\two_inc_max_limit_reg[8]_i_1 \n (.CI(\\two_inc_max_limit_reg[4]_i_1_n_0 ),\n .CO({\\two_inc_max_limit_reg[8]_i_1_n_0 ,\\two_inc_max_limit_reg[8]_i_1_n_1 ,\\two_inc_max_limit_reg[8]_i_1_n_2 ,\\two_inc_max_limit_reg[8]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,device_temp_init[7],1'b0,1'b0}),\n .O(two_inc_max_limit_nxt[8:5]),\n .S({\\two_inc_max_limit[8]_i_2_n_0 ,\\two_inc_max_limit[8]_i_3_n_0 ,\\two_inc_max_limit[8]_i_4_n_0 ,\\two_inc_max_limit[8]_i_5_n_0 }));\n FDRE \\two_inc_max_limit_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_max_limit_nxt[9]),\n .Q(two_inc_max_limit[9]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n LUT1 #(\n .INIT(2'h1)) \n \\two_inc_min_limit[11]_i_2 \n (.I0(three_inc_max_limit[11]),\n .O(\\two_inc_min_limit[11]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_inc_min_limit[11]_i_3 \n (.I0(three_inc_max_limit[10]),\n .O(\\two_inc_min_limit[11]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_inc_min_limit[5]_i_2 \n (.I0(three_inc_max_limit[5]),\n .O(\\two_inc_min_limit[5]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_inc_min_limit[5]_i_3 \n (.I0(three_inc_max_limit[4]),\n .O(\\two_inc_min_limit[5]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_inc_min_limit[5]_i_4 \n (.I0(three_inc_max_limit[3]),\n .O(\\two_inc_min_limit[5]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\two_inc_min_limit[5]_i_5 \n (.I0(three_inc_max_limit[2]),\n .O(\\two_inc_min_limit[5]_i_5_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_inc_min_limit[9]_i_2 \n (.I0(three_inc_max_limit[9]),\n .O(\\two_inc_min_limit[9]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_inc_min_limit[9]_i_3 \n (.I0(three_inc_max_limit[8]),\n .O(\\two_inc_min_limit[9]_i_3_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_inc_min_limit[9]_i_4 \n (.I0(three_inc_max_limit[7]),\n .O(\\two_inc_min_limit[9]_i_4_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\two_inc_min_limit[9]_i_5 \n (.I0(three_inc_max_limit[6]),\n .O(\\two_inc_min_limit[9]_i_5_n_0 ));\n FDRE \\two_inc_min_limit_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_min_limit_nxt[10]),\n .Q(two_inc_min_limit[10]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE \\two_inc_min_limit_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_min_limit_nxt[11]),\n .Q(two_inc_min_limit[11]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n CARRY4 \\two_inc_min_limit_reg[11]_i_1 \n (.CI(\\two_inc_min_limit_reg[9]_i_1_n_0 ),\n .CO({\\NLW_two_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\\two_inc_min_limit_reg[11]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,three_inc_max_limit[10]}),\n .O({\\NLW_two_inc_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],two_inc_min_limit_nxt[11:10]}),\n .S({1'b0,1'b0,\\two_inc_min_limit[11]_i_2_n_0 ,\\two_inc_min_limit[11]_i_3_n_0 }));\n FDRE \\two_inc_min_limit_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(three_inc_max_limit[1]),\n .Q(two_inc_min_limit[1]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE \\two_inc_min_limit_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_min_limit_nxt[2]),\n .Q(two_inc_min_limit[2]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE \\two_inc_min_limit_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_min_limit_nxt[3]),\n .Q(two_inc_min_limit[3]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE \\two_inc_min_limit_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_min_limit_nxt[4]),\n .Q(two_inc_min_limit[4]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE \\two_inc_min_limit_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_min_limit_nxt[5]),\n .Q(two_inc_min_limit[5]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n CARRY4 \\two_inc_min_limit_reg[5]_i_1 \n (.CI(1'b0),\n .CO({\\two_inc_min_limit_reg[5]_i_1_n_0 ,\\two_inc_min_limit_reg[5]_i_1_n_1 ,\\two_inc_min_limit_reg[5]_i_1_n_2 ,\\two_inc_min_limit_reg[5]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({three_inc_max_limit[5:3],1'b0}),\n .O(two_inc_min_limit_nxt[5:2]),\n .S({\\two_inc_min_limit[5]_i_2_n_0 ,\\two_inc_min_limit[5]_i_3_n_0 ,\\two_inc_min_limit[5]_i_4_n_0 ,\\two_inc_min_limit[5]_i_5_n_0 }));\n FDRE \\two_inc_min_limit_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_min_limit_nxt[6]),\n .Q(two_inc_min_limit[6]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE \\two_inc_min_limit_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_min_limit_nxt[7]),\n .Q(two_inc_min_limit[7]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE \\two_inc_min_limit_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_min_limit_nxt[8]),\n .Q(two_inc_min_limit[8]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE \\two_inc_min_limit_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(two_inc_min_limit_nxt[9]),\n .Q(two_inc_min_limit[9]),\n .R(rstdiv0_sync_r1_reg_rep__4));\n CARRY4 \\two_inc_min_limit_reg[9]_i_1 \n (.CI(\\two_inc_min_limit_reg[5]_i_1_n_0 ),\n .CO({\\two_inc_min_limit_reg[9]_i_1_n_0 ,\\two_inc_min_limit_reg[9]_i_1_n_1 ,\\two_inc_min_limit_reg[9]_i_1_n_2 ,\\two_inc_min_limit_reg[9]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI(three_inc_max_limit[9:6]),\n .O(two_inc_min_limit_nxt[9:6]),\n .S({\\two_inc_min_limit[9]_i_2_n_0 ,\\two_inc_min_limit[9]_i_3_n_0 ,\\two_inc_min_limit[9]_i_4_n_0 ,\\two_inc_min_limit[9]_i_5_n_0 }));\n LUT3 #(\n .INIT(8'h40)) \n update_temp_101\n (.I0(tempmon_sample_en_102),\n .I1(tempmon_init_complete),\n .I2(tempmon_sample_en_101),\n .O(update_temp_101__0));\n FDRE update_temp_102_reg\n (.C(CLK),\n .CE(1'b1),\n .D(update_temp_101__0),\n .Q(update_temp_102),\n .R(1'b0));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_ddr_phy_top\n (ddr3_reset_n,\n ddr3_cas_n,\n ddr3_ras_n,\n ddr3_we_n,\n ddr3_addr,\n ddr3_ba,\n ddr3_cs_n,\n ddr3_odt,\n ddr3_cke,\n ddr3_dm,\n \\rd_ptr_timing_reg[2] ,\n \\rd_ptr_timing_reg[2]_0 ,\n \\rd_ptr_timing_reg[2]_1 ,\n \\rd_ptr_timing_reg[2]_2 ,\n \\rd_ptr_timing_reg[2]_3 ,\n \\rd_ptr_timing_reg[2]_4 ,\n \\rd_ptr_timing_reg[2]_5 ,\n \\rd_ptr_timing_reg[2]_6 ,\n \\rd_ptr_timing_reg[2]_7 ,\n \\rd_ptr_timing_reg[2]_8 ,\n \\rd_ptr_timing_reg[2]_9 ,\n \\rd_ptr_timing_reg[2]_10 ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,\n phy_dout,\n \\samps_r_reg[9] ,\n app_zq_r_reg,\n \\my_empty_reg[7] ,\n init_calib_complete_r_reg,\n \\calib_seq_reg[0] ,\n \\pi_rst_stg1_cal_r_reg[0] ,\n samp_edge_cnt0_en_r,\n pi_en_stg2_f_timing_reg,\n dqs_po_en_stg2_f_reg,\n \\rd_ptr_timing_reg[0] ,\n \\resume_wait_r_reg[5] ,\n phy_mc_ctl_full,\n stg3_dec2init_val_r_reg,\n stg3_inc2init_val_r_reg,\n rd_buf_we,\n \\not_strict_mode.status_ram.rd_buf_we_r1_reg ,\n rst_sync_r1_reg,\n \\stg2_tap_cnt_reg[0] ,\n \\sm_r_reg[0] ,\n D,\n \\not_strict_mode.app_rd_data_reg[255] ,\n \\not_strict_mode.app_rd_data_reg[239] ,\n \\not_strict_mode.app_rd_data_reg[247] ,\n \\not_strict_mode.app_rd_data_reg[231] ,\n \\not_strict_mode.app_rd_data_reg[254] ,\n \\not_strict_mode.app_rd_data_reg[238] ,\n \\not_strict_mode.app_rd_data_reg[246] ,\n \\not_strict_mode.app_rd_data_reg[230] ,\n \\not_strict_mode.app_rd_data_reg[253] ,\n \\not_strict_mode.app_rd_data_reg[237] ,\n \\not_strict_mode.app_rd_data_reg[245] ,\n \\not_strict_mode.app_rd_data_reg[229] ,\n \\not_strict_mode.app_rd_data_reg[252] ,\n \\not_strict_mode.app_rd_data_reg[236] ,\n \\not_strict_mode.app_rd_data_reg[244] ,\n \\not_strict_mode.app_rd_data_reg[228] ,\n \\not_strict_mode.app_rd_data_reg[251] ,\n \\not_strict_mode.app_rd_data_reg[235] ,\n \\not_strict_mode.app_rd_data_reg[243] ,\n \\not_strict_mode.app_rd_data_reg[227] ,\n \\not_strict_mode.app_rd_data_reg[250] ,\n \\not_strict_mode.app_rd_data_reg[234] ,\n \\not_strict_mode.app_rd_data_reg[242] ,\n \\not_strict_mode.app_rd_data_reg[226] ,\n \\not_strict_mode.app_rd_data_reg[249] ,\n \\not_strict_mode.app_rd_data_reg[233] ,\n \\not_strict_mode.app_rd_data_reg[241] ,\n \\not_strict_mode.app_rd_data_reg[225] ,\n \\not_strict_mode.app_rd_data_reg[248] ,\n \\not_strict_mode.app_rd_data_reg[232] ,\n \\not_strict_mode.app_rd_data_reg[240] ,\n \\not_strict_mode.app_rd_data_reg[224] ,\n \\not_strict_mode.app_rd_data_reg[223] ,\n \\not_strict_mode.app_rd_data_reg[207] ,\n \\not_strict_mode.app_rd_data_reg[215] ,\n \\not_strict_mode.app_rd_data_reg[199] ,\n \\not_strict_mode.app_rd_data_reg[222] ,\n \\not_strict_mode.app_rd_data_reg[206] ,\n \\not_strict_mode.app_rd_data_reg[214] ,\n \\not_strict_mode.app_rd_data_reg[198] ,\n \\not_strict_mode.app_rd_data_reg[221] ,\n \\not_strict_mode.app_rd_data_reg[205] ,\n \\not_strict_mode.app_rd_data_reg[213] ,\n \\not_strict_mode.app_rd_data_reg[197] ,\n \\not_strict_mode.app_rd_data_reg[220] ,\n \\not_strict_mode.app_rd_data_reg[204] ,\n \\not_strict_mode.app_rd_data_reg[212] ,\n \\not_strict_mode.app_rd_data_reg[196] ,\n \\not_strict_mode.app_rd_data_reg[219] ,\n \\not_strict_mode.app_rd_data_reg[203] ,\n \\not_strict_mode.app_rd_data_reg[211] ,\n \\not_strict_mode.app_rd_data_reg[195] ,\n \\not_strict_mode.app_rd_data_reg[218] ,\n \\not_strict_mode.app_rd_data_reg[202] ,\n \\not_strict_mode.app_rd_data_reg[210] ,\n \\not_strict_mode.app_rd_data_reg[194] ,\n \\not_strict_mode.app_rd_data_reg[217] ,\n \\not_strict_mode.app_rd_data_reg[201] ,\n \\not_strict_mode.app_rd_data_reg[209] ,\n \\not_strict_mode.app_rd_data_reg[193] ,\n \\not_strict_mode.app_rd_data_reg[216] ,\n \\not_strict_mode.app_rd_data_reg[200] ,\n \\not_strict_mode.app_rd_data_reg[208] ,\n \\not_strict_mode.app_rd_data_reg[192] ,\n \\not_strict_mode.app_rd_data_reg[191] ,\n \\not_strict_mode.app_rd_data_reg[175] ,\n \\not_strict_mode.app_rd_data_reg[183] ,\n \\not_strict_mode.app_rd_data_reg[167] ,\n \\not_strict_mode.app_rd_data_reg[190] ,\n \\not_strict_mode.app_rd_data_reg[174] ,\n \\not_strict_mode.app_rd_data_reg[182] ,\n \\not_strict_mode.app_rd_data_reg[166] ,\n \\not_strict_mode.app_rd_data_reg[189] ,\n \\not_strict_mode.app_rd_data_reg[173] ,\n \\not_strict_mode.app_rd_data_reg[181] ,\n \\not_strict_mode.app_rd_data_reg[165] ,\n \\not_strict_mode.app_rd_data_reg[188] ,\n \\not_strict_mode.app_rd_data_reg[172] ,\n \\not_strict_mode.app_rd_data_reg[180] ,\n \\not_strict_mode.app_rd_data_reg[164] ,\n \\not_strict_mode.app_rd_data_reg[187] ,\n \\not_strict_mode.app_rd_data_reg[171] ,\n \\not_strict_mode.app_rd_data_reg[179] ,\n \\not_strict_mode.app_rd_data_reg[163] ,\n \\not_strict_mode.app_rd_data_reg[186] ,\n \\not_strict_mode.app_rd_data_reg[170] ,\n \\not_strict_mode.app_rd_data_reg[178] ,\n \\not_strict_mode.app_rd_data_reg[162] ,\n \\not_strict_mode.app_rd_data_reg[185] ,\n \\not_strict_mode.app_rd_data_reg[169] ,\n \\not_strict_mode.app_rd_data_reg[177] ,\n \\not_strict_mode.app_rd_data_reg[161] ,\n \\not_strict_mode.app_rd_data_reg[184] ,\n \\not_strict_mode.app_rd_data_reg[168] ,\n \\not_strict_mode.app_rd_data_reg[176] ,\n \\not_strict_mode.app_rd_data_reg[160] ,\n \\not_strict_mode.app_rd_data_reg[159] ,\n \\not_strict_mode.app_rd_data_reg[143] ,\n \\not_strict_mode.app_rd_data_reg[151] ,\n \\not_strict_mode.app_rd_data_reg[135] ,\n \\not_strict_mode.app_rd_data_reg[158] ,\n \\not_strict_mode.app_rd_data_reg[142] ,\n \\not_strict_mode.app_rd_data_reg[150] ,\n \\not_strict_mode.app_rd_data_reg[134] ,\n \\not_strict_mode.app_rd_data_reg[157] ,\n \\not_strict_mode.app_rd_data_reg[141] ,\n \\not_strict_mode.app_rd_data_reg[149] ,\n \\not_strict_mode.app_rd_data_reg[133] ,\n \\not_strict_mode.app_rd_data_reg[156] ,\n \\not_strict_mode.app_rd_data_reg[140] ,\n \\not_strict_mode.app_rd_data_reg[148] ,\n \\not_strict_mode.app_rd_data_reg[132] ,\n \\not_strict_mode.app_rd_data_reg[155] ,\n \\not_strict_mode.app_rd_data_reg[139] ,\n \\not_strict_mode.app_rd_data_reg[147] ,\n \\not_strict_mode.app_rd_data_reg[131] ,\n \\not_strict_mode.app_rd_data_reg[154] ,\n \\not_strict_mode.app_rd_data_reg[138] ,\n \\not_strict_mode.app_rd_data_reg[146] ,\n \\not_strict_mode.app_rd_data_reg[130] ,\n \\not_strict_mode.app_rd_data_reg[153] ,\n \\not_strict_mode.app_rd_data_reg[137] ,\n \\not_strict_mode.app_rd_data_reg[145] ,\n \\not_strict_mode.app_rd_data_reg[129] ,\n \\not_strict_mode.app_rd_data_reg[152] ,\n \\not_strict_mode.app_rd_data_reg[136] ,\n \\not_strict_mode.app_rd_data_reg[144] ,\n \\not_strict_mode.app_rd_data_reg[128] ,\n \\not_strict_mode.app_rd_data_reg[127] ,\n \\not_strict_mode.app_rd_data_reg[111] ,\n \\not_strict_mode.app_rd_data_reg[119] ,\n \\not_strict_mode.app_rd_data_reg[103] ,\n \\not_strict_mode.app_rd_data_reg[126] ,\n \\not_strict_mode.app_rd_data_reg[110] ,\n \\not_strict_mode.app_rd_data_reg[118] ,\n \\not_strict_mode.app_rd_data_reg[102] ,\n \\not_strict_mode.app_rd_data_reg[125] ,\n \\not_strict_mode.app_rd_data_reg[109] ,\n \\not_strict_mode.app_rd_data_reg[117] ,\n \\not_strict_mode.app_rd_data_reg[101] ,\n \\not_strict_mode.app_rd_data_reg[124] ,\n \\not_strict_mode.app_rd_data_reg[108] ,\n \\not_strict_mode.app_rd_data_reg[116] ,\n \\not_strict_mode.app_rd_data_reg[100] ,\n \\not_strict_mode.app_rd_data_reg[123] ,\n \\not_strict_mode.app_rd_data_reg[107] ,\n \\not_strict_mode.app_rd_data_reg[115] ,\n \\not_strict_mode.app_rd_data_reg[99] ,\n \\not_strict_mode.app_rd_data_reg[122] ,\n \\not_strict_mode.app_rd_data_reg[106] ,\n \\not_strict_mode.app_rd_data_reg[114] ,\n \\not_strict_mode.app_rd_data_reg[98] ,\n \\not_strict_mode.app_rd_data_reg[121] ,\n \\not_strict_mode.app_rd_data_reg[105] ,\n \\not_strict_mode.app_rd_data_reg[113] ,\n \\not_strict_mode.app_rd_data_reg[97] ,\n \\not_strict_mode.app_rd_data_reg[120] ,\n \\not_strict_mode.app_rd_data_reg[104] ,\n \\not_strict_mode.app_rd_data_reg[112] ,\n \\not_strict_mode.app_rd_data_reg[96] ,\n \\not_strict_mode.app_rd_data_reg[95] ,\n \\not_strict_mode.app_rd_data_reg[79] ,\n \\not_strict_mode.app_rd_data_reg[87] ,\n \\not_strict_mode.app_rd_data_reg[71] ,\n \\not_strict_mode.app_rd_data_reg[94] ,\n \\not_strict_mode.app_rd_data_reg[78] ,\n \\not_strict_mode.app_rd_data_reg[86] ,\n \\not_strict_mode.app_rd_data_reg[70] ,\n \\not_strict_mode.app_rd_data_reg[93] ,\n \\not_strict_mode.app_rd_data_reg[77] ,\n \\not_strict_mode.app_rd_data_reg[85] ,\n \\not_strict_mode.app_rd_data_reg[69] ,\n \\not_strict_mode.app_rd_data_reg[92] ,\n \\not_strict_mode.app_rd_data_reg[76] ,\n \\not_strict_mode.app_rd_data_reg[84] ,\n \\not_strict_mode.app_rd_data_reg[68] ,\n \\not_strict_mode.app_rd_data_reg[91] ,\n \\not_strict_mode.app_rd_data_reg[75] ,\n \\not_strict_mode.app_rd_data_reg[83] ,\n \\not_strict_mode.app_rd_data_reg[67] ,\n \\not_strict_mode.app_rd_data_reg[90] ,\n \\not_strict_mode.app_rd_data_reg[74] ,\n \\not_strict_mode.app_rd_data_reg[82] ,\n \\not_strict_mode.app_rd_data_reg[66] ,\n \\not_strict_mode.app_rd_data_reg[89] ,\n \\not_strict_mode.app_rd_data_reg[73] ,\n \\not_strict_mode.app_rd_data_reg[81] ,\n \\not_strict_mode.app_rd_data_reg[65] ,\n \\not_strict_mode.app_rd_data_reg[88] ,\n \\not_strict_mode.app_rd_data_reg[72] ,\n \\not_strict_mode.app_rd_data_reg[80] ,\n \\not_strict_mode.app_rd_data_reg[64] ,\n \\not_strict_mode.app_rd_data_reg[63] ,\n \\not_strict_mode.app_rd_data_reg[47] ,\n \\not_strict_mode.app_rd_data_reg[55] ,\n \\not_strict_mode.app_rd_data_reg[39] ,\n \\not_strict_mode.app_rd_data_reg[62] ,\n \\not_strict_mode.app_rd_data_reg[46] ,\n \\not_strict_mode.app_rd_data_reg[54] ,\n \\not_strict_mode.app_rd_data_reg[38] ,\n \\not_strict_mode.app_rd_data_reg[61] ,\n \\not_strict_mode.app_rd_data_reg[45] ,\n \\not_strict_mode.app_rd_data_reg[53] ,\n \\not_strict_mode.app_rd_data_reg[37] ,\n \\not_strict_mode.app_rd_data_reg[60] ,\n \\not_strict_mode.app_rd_data_reg[44] ,\n \\not_strict_mode.app_rd_data_reg[52] ,\n \\not_strict_mode.app_rd_data_reg[36] ,\n \\not_strict_mode.app_rd_data_reg[59] ,\n \\not_strict_mode.app_rd_data_reg[43] ,\n \\not_strict_mode.app_rd_data_reg[51] ,\n \\not_strict_mode.app_rd_data_reg[35] ,\n \\not_strict_mode.app_rd_data_reg[58] ,\n \\not_strict_mode.app_rd_data_reg[42] ,\n \\not_strict_mode.app_rd_data_reg[50] ,\n \\not_strict_mode.app_rd_data_reg[34] ,\n \\not_strict_mode.app_rd_data_reg[57] ,\n \\not_strict_mode.app_rd_data_reg[41] ,\n \\not_strict_mode.app_rd_data_reg[49] ,\n \\not_strict_mode.app_rd_data_reg[33] ,\n \\not_strict_mode.app_rd_data_reg[56] ,\n \\not_strict_mode.app_rd_data_reg[40] ,\n \\not_strict_mode.app_rd_data_reg[48] ,\n \\not_strict_mode.app_rd_data_reg[32] ,\n \\not_strict_mode.app_rd_data_reg[31] ,\n \\not_strict_mode.app_rd_data_reg[15] ,\n \\not_strict_mode.app_rd_data_reg[23] ,\n \\not_strict_mode.app_rd_data_reg[7] ,\n \\not_strict_mode.app_rd_data_reg[30] ,\n \\not_strict_mode.app_rd_data_reg[14] ,\n \\not_strict_mode.app_rd_data_reg[22] ,\n \\not_strict_mode.app_rd_data_reg[6] ,\n \\not_strict_mode.app_rd_data_reg[29] ,\n \\not_strict_mode.app_rd_data_reg[13] ,\n \\not_strict_mode.app_rd_data_reg[21] ,\n \\not_strict_mode.app_rd_data_reg[5] ,\n \\not_strict_mode.app_rd_data_reg[28] ,\n \\not_strict_mode.app_rd_data_reg[12] ,\n \\not_strict_mode.app_rd_data_reg[20] ,\n \\not_strict_mode.app_rd_data_reg[4] ,\n \\not_strict_mode.app_rd_data_reg[27] ,\n \\not_strict_mode.app_rd_data_reg[11] ,\n \\not_strict_mode.app_rd_data_reg[19] ,\n \\not_strict_mode.app_rd_data_reg[3] ,\n \\not_strict_mode.app_rd_data_reg[26] ,\n \\not_strict_mode.app_rd_data_reg[10] ,\n \\not_strict_mode.app_rd_data_reg[18] ,\n \\not_strict_mode.app_rd_data_reg[2] ,\n \\not_strict_mode.app_rd_data_reg[25] ,\n \\not_strict_mode.app_rd_data_reg[9] ,\n \\not_strict_mode.app_rd_data_reg[17] ,\n \\not_strict_mode.app_rd_data_reg[1] ,\n \\not_strict_mode.app_rd_data_reg[24] ,\n \\not_strict_mode.app_rd_data_reg[8] ,\n \\not_strict_mode.app_rd_data_reg[16] ,\n \\not_strict_mode.app_rd_data_reg[0] ,\n maint_prescaler_r1,\n \\cmd_pipe_plus.mc_data_offset_reg[3] ,\n \\cmd_pipe_plus.mc_data_offset_reg[5] ,\n \\cmd_pipe_plus.mc_data_offset_reg[4] ,\n \\cmd_pipe_plus.mc_data_offset_reg[2] ,\n \\cmd_pipe_plus.mc_data_offset_reg[1] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[3] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[5] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[4] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[2] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[1] ,\n \\read_fifo.tail_r_reg[0] ,\n \\cmd_pipe_plus.mc_data_offset_reg[0] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[0] ,\n \\en_cnt_div4.enable_wrlvl_cnt_reg[3] ,\n \\complex_row_cnt_ocal_reg[0] ,\n \\row_cnt_victim_rotate.complex_row_cnt_reg[4] ,\n \\not_strict_mode.app_rd_data_reg[255]_0 ,\n ofs_rdy_r_reg,\n ofs_rdy_r_reg_0,\n \\wr_ptr_timing_reg[2] ,\n \\wr_ptr_timing_reg[2]_0 ,\n \\wr_ptr_timing_reg[2]_1 ,\n \\rd_ptr_timing_reg[0]_0 ,\n wr_en,\n wr_en_5,\n wr_en_6,\n of_ctl_full_v,\n ddr_ck_out,\n \\qcntr_r_reg[0] ,\n ddr3_dq,\n ddr3_dqs_p,\n ddr3_dqs_n,\n idle,\n mmcm_ps_clk,\n rst_sync_r1,\n CLK,\n rstdiv0_sync_r1_reg_rep__20,\n poc_sample_pd,\n freq_refclk,\n mem_refclk,\n sync_pulse,\n pll_locked,\n in0,\n CLKB0,\n CLKB0_7,\n CLKB0_8,\n CLKB0_9,\n RST0,\n rstdiv0_sync_r1_reg_rep__9,\n rstdiv0_sync_r1_reg_rep__10,\n rstdiv0_sync_r1_reg_rep__12,\n rstdiv0_sync_r1_reg_rep__2,\n rstdiv0_sync_r1_reg_rep__24,\n rstdiv0_sync_r1_reg_rep__13,\n rstdiv0_sync_r1_reg_rep__14,\n rstdiv0_sync_r1_reg_rep__23,\n SR,\n rstdiv0_sync_r1_reg_rep__11,\n cnt_pwron_reset_done_r0,\n rstdiv0_sync_r1_reg_rep__18,\n rstdiv0_sync_r1_reg_rep__16,\n SS,\n tempmon_sample_en,\n rstdiv0_sync_r1_reg_rep__7,\n \\cmd_pipe_plus.mc_address_reg[43] ,\n Q,\n mem_out,\n \\rd_ptr_reg[3] ,\n rstdiv0_sync_r1_reg_rep__26,\n rstdiv0_sync_r1_reg_rep__26_0,\n rstdiv0_sync_r1_reg_rep__25,\n \\sm_r_reg[0]_0 ,\n \\rd_ptr_reg[3]_0 ,\n \\read_fifo.fifo_out_data_r_reg[6] ,\n ram_init_done_r,\n mc_cas_n,\n mc_ras_n,\n mc_odt,\n mc_cke,\n mc_we_n,\n \\cmd_pipe_plus.mc_address_reg[44] ,\n \\cmd_pipe_plus.mc_bank_reg[8] ,\n mc_cs_n,\n sys_rst,\n \\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ,\n mmcm_locked,\n rstdiv0_sync_r1_reg_rep__26_1,\n rstdiv0_sync_r1_reg_rep__26_2,\n \\mmcm_init_trail_reg[0] ,\n \\mmcm_current_reg[0] ,\n sent_col,\n tail_r,\n \\read_fifo.fifo_out_data_r_reg[6]_0 ,\n DOC,\n DOB,\n DOA,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ,\n psdone,\n rstdiv0_sync_r1_reg_rep__0,\n rstdiv0_sync_r1_reg_rep__19,\n fine_adjust_reg,\n samp_edge_cnt0_en_r_reg,\n pi_cnt_dec_reg,\n rstdiv0_sync_r1_reg_rep__24_0,\n p_81_in,\n rstdiv0_sync_r1_reg_rep__24_1,\n rstdiv0_sync_r1_reg_rep__17,\n po_cnt_dec_reg,\n rstdiv0_sync_r1_reg_rep__5,\n \\device_temp_r_reg[11] ,\n rstdiv0_sync_r1_reg_rep__4,\n rstdiv0_sync_r1_reg_rep__6,\n mc_wrdata_en,\n \\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[2]_0 ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[3]_0 ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ,\n mc_cmd,\n \\cmd_pipe_plus.mc_data_offset_reg[0]_0 ,\n \\cmd_pipe_plus.mc_data_offset_reg[1]_0 ,\n \\cmd_pipe_plus.mc_data_offset_reg[2]_0 ,\n \\cmd_pipe_plus.mc_data_offset_reg[3]_0 ,\n \\cmd_pipe_plus.mc_data_offset_reg[4]_0 ,\n \\cmd_pipe_plus.mc_data_offset_reg[5]_0 ,\n \\stg3_r_reg[0] ,\n rstdiv0_sync_r1_reg_rep__8);\n output ddr3_reset_n;\n output ddr3_cas_n;\n output ddr3_ras_n;\n output ddr3_we_n;\n output [14:0]ddr3_addr;\n output [2:0]ddr3_ba;\n output [0:0]ddr3_cs_n;\n output [0:0]ddr3_odt;\n output [0:0]ddr3_cke;\n output [3:0]ddr3_dm;\n output \\rd_ptr_timing_reg[2] ;\n output \\rd_ptr_timing_reg[2]_0 ;\n output \\rd_ptr_timing_reg[2]_1 ;\n output \\rd_ptr_timing_reg[2]_2 ;\n output \\rd_ptr_timing_reg[2]_3 ;\n output \\rd_ptr_timing_reg[2]_4 ;\n output \\rd_ptr_timing_reg[2]_5 ;\n output \\rd_ptr_timing_reg[2]_6 ;\n output \\rd_ptr_timing_reg[2]_7 ;\n output \\rd_ptr_timing_reg[2]_8 ;\n output \\rd_ptr_timing_reg[2]_9 ;\n output \\rd_ptr_timing_reg[2]_10 ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;\n output [3:0]phy_dout;\n output \\samps_r_reg[9] ;\n output app_zq_r_reg;\n output \\my_empty_reg[7] ;\n output init_calib_complete_r_reg;\n output \\calib_seq_reg[0] ;\n output \\pi_rst_stg1_cal_r_reg[0] ;\n output samp_edge_cnt0_en_r;\n output pi_en_stg2_f_timing_reg;\n output dqs_po_en_stg2_f_reg;\n output [33:0]\\rd_ptr_timing_reg[0] ;\n output \\resume_wait_r_reg[5] ;\n output phy_mc_ctl_full;\n output stg3_dec2init_val_r_reg;\n output stg3_inc2init_val_r_reg;\n output rd_buf_we;\n output \\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n output rst_sync_r1_reg;\n output \\stg2_tap_cnt_reg[0] ;\n output \\sm_r_reg[0] ;\n output [0:0]D;\n output \\not_strict_mode.app_rd_data_reg[255] ;\n output \\not_strict_mode.app_rd_data_reg[239] ;\n output \\not_strict_mode.app_rd_data_reg[247] ;\n output \\not_strict_mode.app_rd_data_reg[231] ;\n output \\not_strict_mode.app_rd_data_reg[254] ;\n output \\not_strict_mode.app_rd_data_reg[238] ;\n output \\not_strict_mode.app_rd_data_reg[246] ;\n output \\not_strict_mode.app_rd_data_reg[230] ;\n output \\not_strict_mode.app_rd_data_reg[253] ;\n output \\not_strict_mode.app_rd_data_reg[237] ;\n output \\not_strict_mode.app_rd_data_reg[245] ;\n output \\not_strict_mode.app_rd_data_reg[229] ;\n output \\not_strict_mode.app_rd_data_reg[252] ;\n output \\not_strict_mode.app_rd_data_reg[236] ;\n output \\not_strict_mode.app_rd_data_reg[244] ;\n output \\not_strict_mode.app_rd_data_reg[228] ;\n output \\not_strict_mode.app_rd_data_reg[251] ;\n output \\not_strict_mode.app_rd_data_reg[235] ;\n output \\not_strict_mode.app_rd_data_reg[243] ;\n output \\not_strict_mode.app_rd_data_reg[227] ;\n output \\not_strict_mode.app_rd_data_reg[250] ;\n output \\not_strict_mode.app_rd_data_reg[234] ;\n output \\not_strict_mode.app_rd_data_reg[242] ;\n output \\not_strict_mode.app_rd_data_reg[226] ;\n output \\not_strict_mode.app_rd_data_reg[249] ;\n output \\not_strict_mode.app_rd_data_reg[233] ;\n output \\not_strict_mode.app_rd_data_reg[241] ;\n output \\not_strict_mode.app_rd_data_reg[225] ;\n output \\not_strict_mode.app_rd_data_reg[248] ;\n output \\not_strict_mode.app_rd_data_reg[232] ;\n output \\not_strict_mode.app_rd_data_reg[240] ;\n output \\not_strict_mode.app_rd_data_reg[224] ;\n output \\not_strict_mode.app_rd_data_reg[223] ;\n output \\not_strict_mode.app_rd_data_reg[207] ;\n output \\not_strict_mode.app_rd_data_reg[215] ;\n output \\not_strict_mode.app_rd_data_reg[199] ;\n output \\not_strict_mode.app_rd_data_reg[222] ;\n output \\not_strict_mode.app_rd_data_reg[206] ;\n output \\not_strict_mode.app_rd_data_reg[214] ;\n output \\not_strict_mode.app_rd_data_reg[198] ;\n output \\not_strict_mode.app_rd_data_reg[221] ;\n output \\not_strict_mode.app_rd_data_reg[205] ;\n output \\not_strict_mode.app_rd_data_reg[213] ;\n output \\not_strict_mode.app_rd_data_reg[197] ;\n output \\not_strict_mode.app_rd_data_reg[220] ;\n output \\not_strict_mode.app_rd_data_reg[204] ;\n output \\not_strict_mode.app_rd_data_reg[212] ;\n output \\not_strict_mode.app_rd_data_reg[196] ;\n output \\not_strict_mode.app_rd_data_reg[219] ;\n output \\not_strict_mode.app_rd_data_reg[203] ;\n output \\not_strict_mode.app_rd_data_reg[211] ;\n output \\not_strict_mode.app_rd_data_reg[195] ;\n output \\not_strict_mode.app_rd_data_reg[218] ;\n output \\not_strict_mode.app_rd_data_reg[202] ;\n output \\not_strict_mode.app_rd_data_reg[210] ;\n output \\not_strict_mode.app_rd_data_reg[194] ;\n output \\not_strict_mode.app_rd_data_reg[217] ;\n output \\not_strict_mode.app_rd_data_reg[201] ;\n output \\not_strict_mode.app_rd_data_reg[209] ;\n output \\not_strict_mode.app_rd_data_reg[193] ;\n output \\not_strict_mode.app_rd_data_reg[216] ;\n output \\not_strict_mode.app_rd_data_reg[200] ;\n output \\not_strict_mode.app_rd_data_reg[208] ;\n output \\not_strict_mode.app_rd_data_reg[192] ;\n output \\not_strict_mode.app_rd_data_reg[191] ;\n output \\not_strict_mode.app_rd_data_reg[175] ;\n output \\not_strict_mode.app_rd_data_reg[183] ;\n output \\not_strict_mode.app_rd_data_reg[167] ;\n output \\not_strict_mode.app_rd_data_reg[190] ;\n output \\not_strict_mode.app_rd_data_reg[174] ;\n output \\not_strict_mode.app_rd_data_reg[182] ;\n output \\not_strict_mode.app_rd_data_reg[166] ;\n output \\not_strict_mode.app_rd_data_reg[189] ;\n output \\not_strict_mode.app_rd_data_reg[173] ;\n output \\not_strict_mode.app_rd_data_reg[181] ;\n output \\not_strict_mode.app_rd_data_reg[165] ;\n output \\not_strict_mode.app_rd_data_reg[188] ;\n output \\not_strict_mode.app_rd_data_reg[172] ;\n output \\not_strict_mode.app_rd_data_reg[180] ;\n output \\not_strict_mode.app_rd_data_reg[164] ;\n output \\not_strict_mode.app_rd_data_reg[187] ;\n output \\not_strict_mode.app_rd_data_reg[171] ;\n output \\not_strict_mode.app_rd_data_reg[179] ;\n output \\not_strict_mode.app_rd_data_reg[163] ;\n output \\not_strict_mode.app_rd_data_reg[186] ;\n output \\not_strict_mode.app_rd_data_reg[170] ;\n output \\not_strict_mode.app_rd_data_reg[178] ;\n output \\not_strict_mode.app_rd_data_reg[162] ;\n output \\not_strict_mode.app_rd_data_reg[185] ;\n output \\not_strict_mode.app_rd_data_reg[169] ;\n output \\not_strict_mode.app_rd_data_reg[177] ;\n output \\not_strict_mode.app_rd_data_reg[161] ;\n output \\not_strict_mode.app_rd_data_reg[184] ;\n output \\not_strict_mode.app_rd_data_reg[168] ;\n output \\not_strict_mode.app_rd_data_reg[176] ;\n output \\not_strict_mode.app_rd_data_reg[160] ;\n output \\not_strict_mode.app_rd_data_reg[159] ;\n output \\not_strict_mode.app_rd_data_reg[143] ;\n output \\not_strict_mode.app_rd_data_reg[151] ;\n output \\not_strict_mode.app_rd_data_reg[135] ;\n output \\not_strict_mode.app_rd_data_reg[158] ;\n output \\not_strict_mode.app_rd_data_reg[142] ;\n output \\not_strict_mode.app_rd_data_reg[150] ;\n output \\not_strict_mode.app_rd_data_reg[134] ;\n output \\not_strict_mode.app_rd_data_reg[157] ;\n output \\not_strict_mode.app_rd_data_reg[141] ;\n output \\not_strict_mode.app_rd_data_reg[149] ;\n output \\not_strict_mode.app_rd_data_reg[133] ;\n output \\not_strict_mode.app_rd_data_reg[156] ;\n output \\not_strict_mode.app_rd_data_reg[140] ;\n output \\not_strict_mode.app_rd_data_reg[148] ;\n output \\not_strict_mode.app_rd_data_reg[132] ;\n output \\not_strict_mode.app_rd_data_reg[155] ;\n output \\not_strict_mode.app_rd_data_reg[139] ;\n output \\not_strict_mode.app_rd_data_reg[147] ;\n output \\not_strict_mode.app_rd_data_reg[131] ;\n output \\not_strict_mode.app_rd_data_reg[154] ;\n output \\not_strict_mode.app_rd_data_reg[138] ;\n output \\not_strict_mode.app_rd_data_reg[146] ;\n output \\not_strict_mode.app_rd_data_reg[130] ;\n output \\not_strict_mode.app_rd_data_reg[153] ;\n output \\not_strict_mode.app_rd_data_reg[137] ;\n output \\not_strict_mode.app_rd_data_reg[145] ;\n output \\not_strict_mode.app_rd_data_reg[129] ;\n output \\not_strict_mode.app_rd_data_reg[152] ;\n output \\not_strict_mode.app_rd_data_reg[136] ;\n output \\not_strict_mode.app_rd_data_reg[144] ;\n output \\not_strict_mode.app_rd_data_reg[128] ;\n output \\not_strict_mode.app_rd_data_reg[127] ;\n output \\not_strict_mode.app_rd_data_reg[111] ;\n output \\not_strict_mode.app_rd_data_reg[119] ;\n output \\not_strict_mode.app_rd_data_reg[103] ;\n output \\not_strict_mode.app_rd_data_reg[126] ;\n output \\not_strict_mode.app_rd_data_reg[110] ;\n output \\not_strict_mode.app_rd_data_reg[118] ;\n output \\not_strict_mode.app_rd_data_reg[102] ;\n output \\not_strict_mode.app_rd_data_reg[125] ;\n output \\not_strict_mode.app_rd_data_reg[109] ;\n output \\not_strict_mode.app_rd_data_reg[117] ;\n output \\not_strict_mode.app_rd_data_reg[101] ;\n output \\not_strict_mode.app_rd_data_reg[124] ;\n output \\not_strict_mode.app_rd_data_reg[108] ;\n output \\not_strict_mode.app_rd_data_reg[116] ;\n output \\not_strict_mode.app_rd_data_reg[100] ;\n output \\not_strict_mode.app_rd_data_reg[123] ;\n output \\not_strict_mode.app_rd_data_reg[107] ;\n output \\not_strict_mode.app_rd_data_reg[115] ;\n output \\not_strict_mode.app_rd_data_reg[99] ;\n output \\not_strict_mode.app_rd_data_reg[122] ;\n output \\not_strict_mode.app_rd_data_reg[106] ;\n output \\not_strict_mode.app_rd_data_reg[114] ;\n output \\not_strict_mode.app_rd_data_reg[98] ;\n output \\not_strict_mode.app_rd_data_reg[121] ;\n output \\not_strict_mode.app_rd_data_reg[105] ;\n output \\not_strict_mode.app_rd_data_reg[113] ;\n output \\not_strict_mode.app_rd_data_reg[97] ;\n output \\not_strict_mode.app_rd_data_reg[120] ;\n output \\not_strict_mode.app_rd_data_reg[104] ;\n output \\not_strict_mode.app_rd_data_reg[112] ;\n output \\not_strict_mode.app_rd_data_reg[96] ;\n output \\not_strict_mode.app_rd_data_reg[95] ;\n output \\not_strict_mode.app_rd_data_reg[79] ;\n output \\not_strict_mode.app_rd_data_reg[87] ;\n output \\not_strict_mode.app_rd_data_reg[71] ;\n output \\not_strict_mode.app_rd_data_reg[94] ;\n output \\not_strict_mode.app_rd_data_reg[78] ;\n output \\not_strict_mode.app_rd_data_reg[86] ;\n output \\not_strict_mode.app_rd_data_reg[70] ;\n output \\not_strict_mode.app_rd_data_reg[93] ;\n output \\not_strict_mode.app_rd_data_reg[77] ;\n output \\not_strict_mode.app_rd_data_reg[85] ;\n output \\not_strict_mode.app_rd_data_reg[69] ;\n output \\not_strict_mode.app_rd_data_reg[92] ;\n output \\not_strict_mode.app_rd_data_reg[76] ;\n output \\not_strict_mode.app_rd_data_reg[84] ;\n output \\not_strict_mode.app_rd_data_reg[68] ;\n output \\not_strict_mode.app_rd_data_reg[91] ;\n output \\not_strict_mode.app_rd_data_reg[75] ;\n output \\not_strict_mode.app_rd_data_reg[83] ;\n output \\not_strict_mode.app_rd_data_reg[67] ;\n output \\not_strict_mode.app_rd_data_reg[90] ;\n output \\not_strict_mode.app_rd_data_reg[74] ;\n output \\not_strict_mode.app_rd_data_reg[82] ;\n output \\not_strict_mode.app_rd_data_reg[66] ;\n output \\not_strict_mode.app_rd_data_reg[89] ;\n output \\not_strict_mode.app_rd_data_reg[73] ;\n output \\not_strict_mode.app_rd_data_reg[81] ;\n output \\not_strict_mode.app_rd_data_reg[65] ;\n output \\not_strict_mode.app_rd_data_reg[88] ;\n output \\not_strict_mode.app_rd_data_reg[72] ;\n output \\not_strict_mode.app_rd_data_reg[80] ;\n output \\not_strict_mode.app_rd_data_reg[64] ;\n output \\not_strict_mode.app_rd_data_reg[63] ;\n output \\not_strict_mode.app_rd_data_reg[47] ;\n output \\not_strict_mode.app_rd_data_reg[55] ;\n output \\not_strict_mode.app_rd_data_reg[39] ;\n output \\not_strict_mode.app_rd_data_reg[62] ;\n output \\not_strict_mode.app_rd_data_reg[46] ;\n output \\not_strict_mode.app_rd_data_reg[54] ;\n output \\not_strict_mode.app_rd_data_reg[38] ;\n output \\not_strict_mode.app_rd_data_reg[61] ;\n output \\not_strict_mode.app_rd_data_reg[45] ;\n output \\not_strict_mode.app_rd_data_reg[53] ;\n output \\not_strict_mode.app_rd_data_reg[37] ;\n output \\not_strict_mode.app_rd_data_reg[60] ;\n output \\not_strict_mode.app_rd_data_reg[44] ;\n output \\not_strict_mode.app_rd_data_reg[52] ;\n output \\not_strict_mode.app_rd_data_reg[36] ;\n output \\not_strict_mode.app_rd_data_reg[59] ;\n output \\not_strict_mode.app_rd_data_reg[43] ;\n output \\not_strict_mode.app_rd_data_reg[51] ;\n output \\not_strict_mode.app_rd_data_reg[35] ;\n output \\not_strict_mode.app_rd_data_reg[58] ;\n output \\not_strict_mode.app_rd_data_reg[42] ;\n output \\not_strict_mode.app_rd_data_reg[50] ;\n output \\not_strict_mode.app_rd_data_reg[34] ;\n output \\not_strict_mode.app_rd_data_reg[57] ;\n output \\not_strict_mode.app_rd_data_reg[41] ;\n output \\not_strict_mode.app_rd_data_reg[49] ;\n output \\not_strict_mode.app_rd_data_reg[33] ;\n output \\not_strict_mode.app_rd_data_reg[56] ;\n output \\not_strict_mode.app_rd_data_reg[40] ;\n output \\not_strict_mode.app_rd_data_reg[48] ;\n output \\not_strict_mode.app_rd_data_reg[32] ;\n output \\not_strict_mode.app_rd_data_reg[31] ;\n output \\not_strict_mode.app_rd_data_reg[15] ;\n output \\not_strict_mode.app_rd_data_reg[23] ;\n output \\not_strict_mode.app_rd_data_reg[7] ;\n output \\not_strict_mode.app_rd_data_reg[30] ;\n output \\not_strict_mode.app_rd_data_reg[14] ;\n output \\not_strict_mode.app_rd_data_reg[22] ;\n output \\not_strict_mode.app_rd_data_reg[6] ;\n output \\not_strict_mode.app_rd_data_reg[29] ;\n output \\not_strict_mode.app_rd_data_reg[13] ;\n output \\not_strict_mode.app_rd_data_reg[21] ;\n output \\not_strict_mode.app_rd_data_reg[5] ;\n output \\not_strict_mode.app_rd_data_reg[28] ;\n output \\not_strict_mode.app_rd_data_reg[12] ;\n output \\not_strict_mode.app_rd_data_reg[20] ;\n output \\not_strict_mode.app_rd_data_reg[4] ;\n output \\not_strict_mode.app_rd_data_reg[27] ;\n output \\not_strict_mode.app_rd_data_reg[11] ;\n output \\not_strict_mode.app_rd_data_reg[19] ;\n output \\not_strict_mode.app_rd_data_reg[3] ;\n output \\not_strict_mode.app_rd_data_reg[26] ;\n output \\not_strict_mode.app_rd_data_reg[10] ;\n output \\not_strict_mode.app_rd_data_reg[18] ;\n output \\not_strict_mode.app_rd_data_reg[2] ;\n output \\not_strict_mode.app_rd_data_reg[25] ;\n output \\not_strict_mode.app_rd_data_reg[9] ;\n output \\not_strict_mode.app_rd_data_reg[17] ;\n output \\not_strict_mode.app_rd_data_reg[1] ;\n output \\not_strict_mode.app_rd_data_reg[24] ;\n output \\not_strict_mode.app_rd_data_reg[8] ;\n output \\not_strict_mode.app_rd_data_reg[16] ;\n output \\not_strict_mode.app_rd_data_reg[0] ;\n output maint_prescaler_r1;\n output \\cmd_pipe_plus.mc_data_offset_reg[3] ;\n output [5:0]\\cmd_pipe_plus.mc_data_offset_reg[5] ;\n output \\cmd_pipe_plus.mc_data_offset_reg[4] ;\n output \\cmd_pipe_plus.mc_data_offset_reg[2] ;\n output \\cmd_pipe_plus.mc_data_offset_reg[1] ;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[3] ;\n output [5:0]\\cmd_pipe_plus.mc_data_offset_1_reg[5] ;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[4] ;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[2] ;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[1] ;\n output \\read_fifo.tail_r_reg[0] ;\n output \\cmd_pipe_plus.mc_data_offset_reg[0] ;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[0] ;\n output \\en_cnt_div4.enable_wrlvl_cnt_reg[3] ;\n output \\complex_row_cnt_ocal_reg[0] ;\n output \\row_cnt_victim_rotate.complex_row_cnt_reg[4] ;\n output [255:0]\\not_strict_mode.app_rd_data_reg[255]_0 ;\n output ofs_rdy_r_reg;\n output ofs_rdy_r_reg_0;\n output [3:0]\\wr_ptr_timing_reg[2] ;\n output [3:0]\\wr_ptr_timing_reg[2]_0 ;\n output [3:0]\\wr_ptr_timing_reg[2]_1 ;\n output [1:0]\\rd_ptr_timing_reg[0]_0 ;\n output wr_en;\n output wr_en_5;\n output wr_en_6;\n output [0:0]of_ctl_full_v;\n output [1:0]ddr_ck_out;\n output [0:0]\\qcntr_r_reg[0] ;\n inout [31:0]ddr3_dq;\n inout [3:0]ddr3_dqs_p;\n inout [3:0]ddr3_dqs_n;\n input idle;\n input mmcm_ps_clk;\n input rst_sync_r1;\n input CLK;\n input rstdiv0_sync_r1_reg_rep__20;\n input poc_sample_pd;\n input freq_refclk;\n input mem_refclk;\n input sync_pulse;\n input pll_locked;\n input in0;\n input CLKB0;\n input CLKB0_7;\n input CLKB0_8;\n input CLKB0_9;\n input RST0;\n input rstdiv0_sync_r1_reg_rep__9;\n input rstdiv0_sync_r1_reg_rep__10;\n input rstdiv0_sync_r1_reg_rep__12;\n input rstdiv0_sync_r1_reg_rep__2;\n input rstdiv0_sync_r1_reg_rep__24;\n input rstdiv0_sync_r1_reg_rep__13;\n input [1:0]rstdiv0_sync_r1_reg_rep__14;\n input rstdiv0_sync_r1_reg_rep__23;\n input [0:0]SR;\n input [0:0]rstdiv0_sync_r1_reg_rep__11;\n input cnt_pwron_reset_done_r0;\n input [0:0]rstdiv0_sync_r1_reg_rep__18;\n input [0:0]rstdiv0_sync_r1_reg_rep__16;\n input [0:0]SS;\n input tempmon_sample_en;\n input rstdiv0_sync_r1_reg_rep__7;\n input [1:0]\\cmd_pipe_plus.mc_address_reg[43] ;\n input [287:0]Q;\n input [17:0]mem_out;\n input [71:0]\\rd_ptr_reg[3] ;\n input rstdiv0_sync_r1_reg_rep__26;\n input rstdiv0_sync_r1_reg_rep__26_0;\n input rstdiv0_sync_r1_reg_rep__25;\n input [0:0]\\sm_r_reg[0]_0 ;\n input [29:0]\\rd_ptr_reg[3]_0 ;\n input [0:0]\\read_fifo.fifo_out_data_r_reg[6] ;\n input ram_init_done_r;\n input [2:0]mc_cas_n;\n input [2:0]mc_ras_n;\n input [0:0]mc_odt;\n input [0:0]mc_cke;\n input [2:0]mc_we_n;\n input [37:0]\\cmd_pipe_plus.mc_address_reg[44] ;\n input [8:0]\\cmd_pipe_plus.mc_bank_reg[8] ;\n input [0:0]mc_cs_n;\n input sys_rst;\n input [0:0]\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ;\n input mmcm_locked;\n input rstdiv0_sync_r1_reg_rep__26_1;\n input rstdiv0_sync_r1_reg_rep__26_2;\n input \\mmcm_init_trail_reg[0] ;\n input \\mmcm_current_reg[0] ;\n input sent_col;\n input [0:0]tail_r;\n input \\read_fifo.fifo_out_data_r_reg[6]_0 ;\n input [1:0]DOC;\n input [1:0]DOB;\n input [1:0]DOA;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ;\n input psdone;\n input rstdiv0_sync_r1_reg_rep__0;\n input [0:0]rstdiv0_sync_r1_reg_rep__19;\n input fine_adjust_reg;\n input samp_edge_cnt0_en_r_reg;\n input [0:0]pi_cnt_dec_reg;\n input rstdiv0_sync_r1_reg_rep__24_0;\n input p_81_in;\n input rstdiv0_sync_r1_reg_rep__24_1;\n input [0:0]rstdiv0_sync_r1_reg_rep__17;\n input [0:0]po_cnt_dec_reg;\n input [0:0]rstdiv0_sync_r1_reg_rep__5;\n input [11:0]\\device_temp_r_reg[11] ;\n input rstdiv0_sync_r1_reg_rep__4;\n input rstdiv0_sync_r1_reg_rep__6;\n input mc_wrdata_en;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[2]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[3]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ;\n input [1:0]mc_cmd;\n input \\cmd_pipe_plus.mc_data_offset_reg[0]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_reg[1]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_reg[2]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_reg[3]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_reg[4]_0 ;\n input \\cmd_pipe_plus.mc_data_offset_reg[5]_0 ;\n input \\stg3_r_reg[0] ;\n input rstdiv0_sync_r1_reg_rep__8;\n\n wire CLK;\n wire CLKB0;\n wire CLKB0_7;\n wire CLKB0_8;\n wire CLKB0_9;\n wire [0:0]D;\n wire [1:0]DOA;\n wire [1:0]DOB;\n wire [1:0]DOC;\n wire [287:0]Q;\n wire RST0;\n wire [0:0]SR;\n wire [0:0]SS;\n wire app_zq_r_reg;\n wire [1:0]byte_sel_cnt;\n wire [1:0]calib_sel;\n wire [3:3]calib_sel__0;\n wire [1:0]calib_seq;\n wire \\calib_seq_reg[0] ;\n wire [1:0]\\cmd_pipe_plus.mc_address_reg[43] ;\n wire [37:0]\\cmd_pipe_plus.mc_address_reg[44] ;\n wire [8:0]\\cmd_pipe_plus.mc_bank_reg[8] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[0] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[1] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[2] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[2]_0 ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[3] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[3]_0 ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[4] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ;\n wire [5:0]\\cmd_pipe_plus.mc_data_offset_1_reg[5] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[0] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[0]_0 ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[1] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[1]_0 ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[2] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[2]_0 ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[3] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[3]_0 ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[4] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[4]_0 ;\n wire [5:0]\\cmd_pipe_plus.mc_data_offset_reg[5] ;\n wire \\cmd_pipe_plus.mc_data_offset_reg[5]_0 ;\n wire cnt_pwron_reset_done_r0;\n wire \\complex_row_cnt_ocal_reg[0] ;\n wire [14:0]ddr3_addr;\n wire [2:0]ddr3_ba;\n wire ddr3_cas_n;\n wire [0:0]ddr3_cke;\n wire [0:0]ddr3_cs_n;\n wire [3:0]ddr3_dm;\n wire [31:0]ddr3_dq;\n wire [3:0]ddr3_dqs_n;\n wire [3:0]ddr3_dqs_p;\n wire [0:0]ddr3_odt;\n wire ddr3_ras_n;\n wire ddr3_reset_n;\n wire ddr3_we_n;\n wire [1:0]ddr_ck_out;\n wire [1:0]\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl/A ;\n wire [11:0]\\device_temp_r_reg[11] ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;\n wire dqs_po_en_stg2_f_reg;\n wire \\en_cnt_div4.enable_wrlvl_cnt_reg[3] ;\n wire fine_adjust_reg;\n wire [26:2]fine_delay_mod;\n wire fine_delay_sel_r;\n wire freq_refclk;\n wire idelay_inc;\n wire idle;\n wire in0;\n wire init_calib_complete_r_reg;\n wire maint_prescaler_r1;\n wire [2:0]mc_cas_n;\n wire [0:0]mc_cke;\n wire [1:0]mc_cmd;\n wire [0:0]mc_cs_n;\n wire [0:0]mc_odt;\n wire [2:0]mc_ras_n;\n wire [2:0]mc_we_n;\n wire mc_wrdata_en;\n wire [17:0]mem_out;\n wire mem_refclk;\n wire \\mmcm_current_reg[0] ;\n wire \\mmcm_init_trail_reg[0] ;\n wire mmcm_locked;\n wire mmcm_ps_clk;\n wire [57:5]mux_address;\n wire mux_cmd_wren;\n wire [5:0]mux_data_offset_1;\n wire mux_reset_n;\n wire [255:0]mux_wrdata;\n wire mux_wrdata_en;\n wire [31:0]mux_wrdata_mask;\n wire \\my_empty_reg[7] ;\n wire \\not_strict_mode.app_rd_data_reg[0] ;\n wire \\not_strict_mode.app_rd_data_reg[100] ;\n wire \\not_strict_mode.app_rd_data_reg[101] ;\n wire \\not_strict_mode.app_rd_data_reg[102] ;\n wire \\not_strict_mode.app_rd_data_reg[103] ;\n wire \\not_strict_mode.app_rd_data_reg[104] ;\n wire \\not_strict_mode.app_rd_data_reg[105] ;\n wire \\not_strict_mode.app_rd_data_reg[106] ;\n wire \\not_strict_mode.app_rd_data_reg[107] ;\n wire \\not_strict_mode.app_rd_data_reg[108] ;\n wire \\not_strict_mode.app_rd_data_reg[109] ;\n wire \\not_strict_mode.app_rd_data_reg[10] ;\n wire \\not_strict_mode.app_rd_data_reg[110] ;\n wire \\not_strict_mode.app_rd_data_reg[111] ;\n wire \\not_strict_mode.app_rd_data_reg[112] ;\n wire \\not_strict_mode.app_rd_data_reg[113] ;\n wire \\not_strict_mode.app_rd_data_reg[114] ;\n wire \\not_strict_mode.app_rd_data_reg[115] ;\n wire \\not_strict_mode.app_rd_data_reg[116] ;\n wire \\not_strict_mode.app_rd_data_reg[117] ;\n wire \\not_strict_mode.app_rd_data_reg[118] ;\n wire \\not_strict_mode.app_rd_data_reg[119] ;\n wire \\not_strict_mode.app_rd_data_reg[11] ;\n wire \\not_strict_mode.app_rd_data_reg[120] ;\n wire \\not_strict_mode.app_rd_data_reg[121] ;\n wire \\not_strict_mode.app_rd_data_reg[122] ;\n wire \\not_strict_mode.app_rd_data_reg[123] ;\n wire \\not_strict_mode.app_rd_data_reg[124] ;\n wire \\not_strict_mode.app_rd_data_reg[125] ;\n wire \\not_strict_mode.app_rd_data_reg[126] ;\n wire \\not_strict_mode.app_rd_data_reg[127] ;\n wire \\not_strict_mode.app_rd_data_reg[128] ;\n wire \\not_strict_mode.app_rd_data_reg[129] ;\n wire \\not_strict_mode.app_rd_data_reg[12] ;\n wire \\not_strict_mode.app_rd_data_reg[130] ;\n wire \\not_strict_mode.app_rd_data_reg[131] ;\n wire \\not_strict_mode.app_rd_data_reg[132] ;\n wire \\not_strict_mode.app_rd_data_reg[133] ;\n wire \\not_strict_mode.app_rd_data_reg[134] ;\n wire \\not_strict_mode.app_rd_data_reg[135] ;\n wire \\not_strict_mode.app_rd_data_reg[136] ;\n wire \\not_strict_mode.app_rd_data_reg[137] ;\n wire \\not_strict_mode.app_rd_data_reg[138] ;\n wire \\not_strict_mode.app_rd_data_reg[139] ;\n wire \\not_strict_mode.app_rd_data_reg[13] ;\n wire \\not_strict_mode.app_rd_data_reg[140] ;\n wire \\not_strict_mode.app_rd_data_reg[141] ;\n wire \\not_strict_mode.app_rd_data_reg[142] ;\n wire \\not_strict_mode.app_rd_data_reg[143] ;\n wire \\not_strict_mode.app_rd_data_reg[144] ;\n wire \\not_strict_mode.app_rd_data_reg[145] ;\n wire \\not_strict_mode.app_rd_data_reg[146] ;\n wire \\not_strict_mode.app_rd_data_reg[147] ;\n wire \\not_strict_mode.app_rd_data_reg[148] ;\n wire \\not_strict_mode.app_rd_data_reg[149] ;\n wire \\not_strict_mode.app_rd_data_reg[14] ;\n wire \\not_strict_mode.app_rd_data_reg[150] ;\n wire \\not_strict_mode.app_rd_data_reg[151] ;\n wire \\not_strict_mode.app_rd_data_reg[152] ;\n wire \\not_strict_mode.app_rd_data_reg[153] ;\n wire \\not_strict_mode.app_rd_data_reg[154] ;\n wire \\not_strict_mode.app_rd_data_reg[155] ;\n wire \\not_strict_mode.app_rd_data_reg[156] ;\n wire \\not_strict_mode.app_rd_data_reg[157] ;\n wire \\not_strict_mode.app_rd_data_reg[158] ;\n wire \\not_strict_mode.app_rd_data_reg[159] ;\n wire \\not_strict_mode.app_rd_data_reg[15] ;\n wire \\not_strict_mode.app_rd_data_reg[160] ;\n wire \\not_strict_mode.app_rd_data_reg[161] ;\n wire \\not_strict_mode.app_rd_data_reg[162] ;\n wire \\not_strict_mode.app_rd_data_reg[163] ;\n wire \\not_strict_mode.app_rd_data_reg[164] ;\n wire \\not_strict_mode.app_rd_data_reg[165] ;\n wire \\not_strict_mode.app_rd_data_reg[166] ;\n wire \\not_strict_mode.app_rd_data_reg[167] ;\n wire \\not_strict_mode.app_rd_data_reg[168] ;\n wire \\not_strict_mode.app_rd_data_reg[169] ;\n wire \\not_strict_mode.app_rd_data_reg[16] ;\n wire \\not_strict_mode.app_rd_data_reg[170] ;\n wire \\not_strict_mode.app_rd_data_reg[171] ;\n wire \\not_strict_mode.app_rd_data_reg[172] ;\n wire \\not_strict_mode.app_rd_data_reg[173] ;\n wire \\not_strict_mode.app_rd_data_reg[174] ;\n wire \\not_strict_mode.app_rd_data_reg[175] ;\n wire \\not_strict_mode.app_rd_data_reg[176] ;\n wire \\not_strict_mode.app_rd_data_reg[177] ;\n wire \\not_strict_mode.app_rd_data_reg[178] ;\n wire \\not_strict_mode.app_rd_data_reg[179] ;\n wire \\not_strict_mode.app_rd_data_reg[17] ;\n wire \\not_strict_mode.app_rd_data_reg[180] ;\n wire \\not_strict_mode.app_rd_data_reg[181] ;\n wire \\not_strict_mode.app_rd_data_reg[182] ;\n wire \\not_strict_mode.app_rd_data_reg[183] ;\n wire \\not_strict_mode.app_rd_data_reg[184] ;\n wire \\not_strict_mode.app_rd_data_reg[185] ;\n wire \\not_strict_mode.app_rd_data_reg[186] ;\n wire \\not_strict_mode.app_rd_data_reg[187] ;\n wire \\not_strict_mode.app_rd_data_reg[188] ;\n wire \\not_strict_mode.app_rd_data_reg[189] ;\n wire \\not_strict_mode.app_rd_data_reg[18] ;\n wire \\not_strict_mode.app_rd_data_reg[190] ;\n wire \\not_strict_mode.app_rd_data_reg[191] ;\n wire \\not_strict_mode.app_rd_data_reg[192] ;\n wire \\not_strict_mode.app_rd_data_reg[193] ;\n wire \\not_strict_mode.app_rd_data_reg[194] ;\n wire \\not_strict_mode.app_rd_data_reg[195] ;\n wire \\not_strict_mode.app_rd_data_reg[196] ;\n wire \\not_strict_mode.app_rd_data_reg[197] ;\n wire \\not_strict_mode.app_rd_data_reg[198] ;\n wire \\not_strict_mode.app_rd_data_reg[199] ;\n wire \\not_strict_mode.app_rd_data_reg[19] ;\n wire \\not_strict_mode.app_rd_data_reg[1] ;\n wire \\not_strict_mode.app_rd_data_reg[200] ;\n wire \\not_strict_mode.app_rd_data_reg[201] ;\n wire \\not_strict_mode.app_rd_data_reg[202] ;\n wire \\not_strict_mode.app_rd_data_reg[203] ;\n wire \\not_strict_mode.app_rd_data_reg[204] ;\n wire \\not_strict_mode.app_rd_data_reg[205] ;\n wire \\not_strict_mode.app_rd_data_reg[206] ;\n wire \\not_strict_mode.app_rd_data_reg[207] ;\n wire \\not_strict_mode.app_rd_data_reg[208] ;\n wire \\not_strict_mode.app_rd_data_reg[209] ;\n wire \\not_strict_mode.app_rd_data_reg[20] ;\n wire \\not_strict_mode.app_rd_data_reg[210] ;\n wire \\not_strict_mode.app_rd_data_reg[211] ;\n wire \\not_strict_mode.app_rd_data_reg[212] ;\n wire \\not_strict_mode.app_rd_data_reg[213] ;\n wire \\not_strict_mode.app_rd_data_reg[214] ;\n wire \\not_strict_mode.app_rd_data_reg[215] ;\n wire \\not_strict_mode.app_rd_data_reg[216] ;\n wire \\not_strict_mode.app_rd_data_reg[217] ;\n wire \\not_strict_mode.app_rd_data_reg[218] ;\n wire \\not_strict_mode.app_rd_data_reg[219] ;\n wire \\not_strict_mode.app_rd_data_reg[21] ;\n wire \\not_strict_mode.app_rd_data_reg[220] ;\n wire \\not_strict_mode.app_rd_data_reg[221] ;\n wire \\not_strict_mode.app_rd_data_reg[222] ;\n wire \\not_strict_mode.app_rd_data_reg[223] ;\n wire \\not_strict_mode.app_rd_data_reg[224] ;\n wire \\not_strict_mode.app_rd_data_reg[225] ;\n wire \\not_strict_mode.app_rd_data_reg[226] ;\n wire \\not_strict_mode.app_rd_data_reg[227] ;\n wire \\not_strict_mode.app_rd_data_reg[228] ;\n wire \\not_strict_mode.app_rd_data_reg[229] ;\n wire \\not_strict_mode.app_rd_data_reg[22] ;\n wire \\not_strict_mode.app_rd_data_reg[230] ;\n wire \\not_strict_mode.app_rd_data_reg[231] ;\n wire \\not_strict_mode.app_rd_data_reg[232] ;\n wire \\not_strict_mode.app_rd_data_reg[233] ;\n wire \\not_strict_mode.app_rd_data_reg[234] ;\n wire \\not_strict_mode.app_rd_data_reg[235] ;\n wire \\not_strict_mode.app_rd_data_reg[236] ;\n wire \\not_strict_mode.app_rd_data_reg[237] ;\n wire \\not_strict_mode.app_rd_data_reg[238] ;\n wire \\not_strict_mode.app_rd_data_reg[239] ;\n wire \\not_strict_mode.app_rd_data_reg[23] ;\n wire \\not_strict_mode.app_rd_data_reg[240] ;\n wire \\not_strict_mode.app_rd_data_reg[241] ;\n wire \\not_strict_mode.app_rd_data_reg[242] ;\n wire \\not_strict_mode.app_rd_data_reg[243] ;\n wire \\not_strict_mode.app_rd_data_reg[244] ;\n wire \\not_strict_mode.app_rd_data_reg[245] ;\n wire \\not_strict_mode.app_rd_data_reg[246] ;\n wire \\not_strict_mode.app_rd_data_reg[247] ;\n wire \\not_strict_mode.app_rd_data_reg[248] ;\n wire \\not_strict_mode.app_rd_data_reg[249] ;\n wire \\not_strict_mode.app_rd_data_reg[24] ;\n wire \\not_strict_mode.app_rd_data_reg[250] ;\n wire \\not_strict_mode.app_rd_data_reg[251] ;\n wire \\not_strict_mode.app_rd_data_reg[252] ;\n wire \\not_strict_mode.app_rd_data_reg[253] ;\n wire \\not_strict_mode.app_rd_data_reg[254] ;\n wire \\not_strict_mode.app_rd_data_reg[255] ;\n wire [255:0]\\not_strict_mode.app_rd_data_reg[255]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[25] ;\n wire \\not_strict_mode.app_rd_data_reg[26] ;\n wire \\not_strict_mode.app_rd_data_reg[27] ;\n wire \\not_strict_mode.app_rd_data_reg[28] ;\n wire \\not_strict_mode.app_rd_data_reg[29] ;\n wire \\not_strict_mode.app_rd_data_reg[2] ;\n wire \\not_strict_mode.app_rd_data_reg[30] ;\n wire \\not_strict_mode.app_rd_data_reg[31] ;\n wire \\not_strict_mode.app_rd_data_reg[32] ;\n wire \\not_strict_mode.app_rd_data_reg[33] ;\n wire \\not_strict_mode.app_rd_data_reg[34] ;\n wire \\not_strict_mode.app_rd_data_reg[35] ;\n wire \\not_strict_mode.app_rd_data_reg[36] ;\n wire \\not_strict_mode.app_rd_data_reg[37] ;\n wire \\not_strict_mode.app_rd_data_reg[38] ;\n wire \\not_strict_mode.app_rd_data_reg[39] ;\n wire \\not_strict_mode.app_rd_data_reg[3] ;\n wire \\not_strict_mode.app_rd_data_reg[40] ;\n wire \\not_strict_mode.app_rd_data_reg[41] ;\n wire \\not_strict_mode.app_rd_data_reg[42] ;\n wire \\not_strict_mode.app_rd_data_reg[43] ;\n wire \\not_strict_mode.app_rd_data_reg[44] ;\n wire \\not_strict_mode.app_rd_data_reg[45] ;\n wire \\not_strict_mode.app_rd_data_reg[46] ;\n wire \\not_strict_mode.app_rd_data_reg[47] ;\n wire \\not_strict_mode.app_rd_data_reg[48] ;\n wire \\not_strict_mode.app_rd_data_reg[49] ;\n wire \\not_strict_mode.app_rd_data_reg[4] ;\n wire \\not_strict_mode.app_rd_data_reg[50] ;\n wire \\not_strict_mode.app_rd_data_reg[51] ;\n wire \\not_strict_mode.app_rd_data_reg[52] ;\n wire \\not_strict_mode.app_rd_data_reg[53] ;\n wire \\not_strict_mode.app_rd_data_reg[54] ;\n wire \\not_strict_mode.app_rd_data_reg[55] ;\n wire \\not_strict_mode.app_rd_data_reg[56] ;\n wire \\not_strict_mode.app_rd_data_reg[57] ;\n wire \\not_strict_mode.app_rd_data_reg[58] ;\n wire \\not_strict_mode.app_rd_data_reg[59] ;\n wire \\not_strict_mode.app_rd_data_reg[5] ;\n wire \\not_strict_mode.app_rd_data_reg[60] ;\n wire \\not_strict_mode.app_rd_data_reg[61] ;\n wire \\not_strict_mode.app_rd_data_reg[62] ;\n wire \\not_strict_mode.app_rd_data_reg[63] ;\n wire \\not_strict_mode.app_rd_data_reg[64] ;\n wire \\not_strict_mode.app_rd_data_reg[65] ;\n wire \\not_strict_mode.app_rd_data_reg[66] ;\n wire \\not_strict_mode.app_rd_data_reg[67] ;\n wire \\not_strict_mode.app_rd_data_reg[68] ;\n wire \\not_strict_mode.app_rd_data_reg[69] ;\n wire \\not_strict_mode.app_rd_data_reg[6] ;\n wire \\not_strict_mode.app_rd_data_reg[70] ;\n wire \\not_strict_mode.app_rd_data_reg[71] ;\n wire \\not_strict_mode.app_rd_data_reg[72] ;\n wire \\not_strict_mode.app_rd_data_reg[73] ;\n wire \\not_strict_mode.app_rd_data_reg[74] ;\n wire \\not_strict_mode.app_rd_data_reg[75] ;\n wire \\not_strict_mode.app_rd_data_reg[76] ;\n wire \\not_strict_mode.app_rd_data_reg[77] ;\n wire \\not_strict_mode.app_rd_data_reg[78] ;\n wire \\not_strict_mode.app_rd_data_reg[79] ;\n wire \\not_strict_mode.app_rd_data_reg[7] ;\n wire \\not_strict_mode.app_rd_data_reg[80] ;\n wire \\not_strict_mode.app_rd_data_reg[81] ;\n wire \\not_strict_mode.app_rd_data_reg[82] ;\n wire \\not_strict_mode.app_rd_data_reg[83] ;\n wire \\not_strict_mode.app_rd_data_reg[84] ;\n wire \\not_strict_mode.app_rd_data_reg[85] ;\n wire \\not_strict_mode.app_rd_data_reg[86] ;\n wire \\not_strict_mode.app_rd_data_reg[87] ;\n wire \\not_strict_mode.app_rd_data_reg[88] ;\n wire \\not_strict_mode.app_rd_data_reg[89] ;\n wire \\not_strict_mode.app_rd_data_reg[8] ;\n wire \\not_strict_mode.app_rd_data_reg[90] ;\n wire \\not_strict_mode.app_rd_data_reg[91] ;\n wire \\not_strict_mode.app_rd_data_reg[92] ;\n wire \\not_strict_mode.app_rd_data_reg[93] ;\n wire \\not_strict_mode.app_rd_data_reg[94] ;\n wire \\not_strict_mode.app_rd_data_reg[95] ;\n wire \\not_strict_mode.app_rd_data_reg[96] ;\n wire \\not_strict_mode.app_rd_data_reg[97] ;\n wire \\not_strict_mode.app_rd_data_reg[98] ;\n wire \\not_strict_mode.app_rd_data_reg[99] ;\n wire \\not_strict_mode.app_rd_data_reg[9] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ;\n wire \\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n wire [55:0]\\oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_data/data_bytes_ns ;\n wire [7:0]\\oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_data/data_bytes_r0 ;\n wire [0:0]of_ctl_full_v;\n wire ofs_rdy_r_reg;\n wire ofs_rdy_r_reg_0;\n wire [22:0]p_1_out;\n wire p_81_in;\n wire pd_out;\n wire [3:0]phy_dout;\n wire phy_if_reset;\n wire phy_mc_ctl_full;\n wire phy_rddata_en;\n wire phy_read_calib;\n wire phy_write_calib;\n wire [0:0]pi_cnt_dec_reg;\n wire pi_en_stg2_f_timing_reg;\n wire \\pi_rst_stg1_cal_r_reg[0] ;\n wire pll_locked;\n wire [0:0]po_cnt_dec_reg;\n wire [1:0]po_stg2_wrcal_cnt;\n wire poc_sample_pd;\n wire psdone;\n wire [0:0]\\qcntr_r_reg[0] ;\n wire ram_init_done_r;\n wire rd_buf_we;\n wire [71:0]\\rd_ptr_reg[3] ;\n wire [29:0]\\rd_ptr_reg[3]_0 ;\n wire [33:0]\\rd_ptr_timing_reg[0] ;\n wire [1:0]\\rd_ptr_timing_reg[0]_0 ;\n wire \\rd_ptr_timing_reg[2] ;\n wire \\rd_ptr_timing_reg[2]_0 ;\n wire \\rd_ptr_timing_reg[2]_1 ;\n wire \\rd_ptr_timing_reg[2]_10 ;\n wire \\rd_ptr_timing_reg[2]_2 ;\n wire \\rd_ptr_timing_reg[2]_3 ;\n wire \\rd_ptr_timing_reg[2]_4 ;\n wire \\rd_ptr_timing_reg[2]_5 ;\n wire \\rd_ptr_timing_reg[2]_6 ;\n wire \\rd_ptr_timing_reg[2]_7 ;\n wire \\rd_ptr_timing_reg[2]_8 ;\n wire \\rd_ptr_timing_reg[2]_9 ;\n wire [0:0]\\read_fifo.fifo_out_data_r_reg[6] ;\n wire \\read_fifo.fifo_out_data_r_reg[6]_0 ;\n wire \\read_fifo.tail_r_reg[0] ;\n wire \\resume_wait_r_reg[5] ;\n wire \\row_cnt_victim_rotate.complex_row_cnt_reg[4] ;\n wire [0:0]\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ;\n wire rst_sync_r1;\n wire rst_sync_r1_reg;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__10;\n wire [0:0]rstdiv0_sync_r1_reg_rep__11;\n wire rstdiv0_sync_r1_reg_rep__12;\n wire rstdiv0_sync_r1_reg_rep__13;\n wire [1:0]rstdiv0_sync_r1_reg_rep__14;\n wire [0:0]rstdiv0_sync_r1_reg_rep__16;\n wire [0:0]rstdiv0_sync_r1_reg_rep__17;\n wire [0:0]rstdiv0_sync_r1_reg_rep__18;\n wire [0:0]rstdiv0_sync_r1_reg_rep__19;\n wire rstdiv0_sync_r1_reg_rep__2;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__23;\n wire rstdiv0_sync_r1_reg_rep__24;\n wire rstdiv0_sync_r1_reg_rep__24_0;\n wire rstdiv0_sync_r1_reg_rep__24_1;\n wire rstdiv0_sync_r1_reg_rep__25;\n wire rstdiv0_sync_r1_reg_rep__26;\n wire rstdiv0_sync_r1_reg_rep__26_0;\n wire rstdiv0_sync_r1_reg_rep__26_1;\n wire rstdiv0_sync_r1_reg_rep__26_2;\n wire rstdiv0_sync_r1_reg_rep__4;\n wire [0:0]rstdiv0_sync_r1_reg_rep__5;\n wire rstdiv0_sync_r1_reg_rep__6;\n wire rstdiv0_sync_r1_reg_rep__7;\n wire rstdiv0_sync_r1_reg_rep__8;\n wire rstdiv0_sync_r1_reg_rep__9;\n wire samp_edge_cnt0_en_r;\n wire samp_edge_cnt0_en_r_reg;\n wire \\samps_r_reg[9] ;\n wire sent_col;\n wire \\sm_r_reg[0] ;\n wire [0:0]\\sm_r_reg[0]_0 ;\n wire \\stg2_tap_cnt_reg[0] ;\n wire stg3_dec2init_val_r_reg;\n wire stg3_inc2init_val_r_reg;\n wire \\stg3_r_reg[0] ;\n wire sync_pulse;\n wire sys_rst;\n wire [0:0]tail_r;\n wire tempmon_sample_en;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire u_ddr_calib_top_n_37;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire u_ddr_calib_top_n_38;\n wire u_ddr_calib_top_n_385;\n wire u_ddr_calib_top_n_386;\n wire u_ddr_calib_top_n_387;\n wire u_ddr_calib_top_n_388;\n wire u_ddr_calib_top_n_389;\n wire u_ddr_calib_top_n_390;\n wire u_ddr_calib_top_n_391;\n wire u_ddr_calib_top_n_392;\n wire u_ddr_calib_top_n_393;\n wire u_ddr_calib_top_n_394;\n wire u_ddr_calib_top_n_395;\n wire u_ddr_calib_top_n_396;\n wire u_ddr_calib_top_n_397;\n wire u_ddr_calib_top_n_399;\n wire u_ddr_calib_top_n_400;\n wire u_ddr_calib_top_n_401;\n wire u_ddr_calib_top_n_402;\n wire u_ddr_calib_top_n_403;\n wire u_ddr_calib_top_n_404;\n wire u_ddr_calib_top_n_405;\n wire u_ddr_calib_top_n_406;\n wire u_ddr_calib_top_n_407;\n wire u_ddr_calib_top_n_408;\n wire u_ddr_calib_top_n_409;\n wire u_ddr_calib_top_n_410;\n wire u_ddr_calib_top_n_411;\n wire u_ddr_calib_top_n_412;\n wire u_ddr_calib_top_n_413;\n wire u_ddr_calib_top_n_414;\n wire u_ddr_calib_top_n_415;\n wire u_ddr_calib_top_n_416;\n wire u_ddr_calib_top_n_417;\n wire u_ddr_calib_top_n_418;\n wire u_ddr_calib_top_n_419;\n wire u_ddr_calib_top_n_420;\n wire u_ddr_calib_top_n_421;\n wire u_ddr_calib_top_n_422;\n wire u_ddr_calib_top_n_423;\n wire u_ddr_calib_top_n_424;\n wire u_ddr_calib_top_n_425;\n wire u_ddr_calib_top_n_426;\n wire u_ddr_calib_top_n_427;\n wire u_ddr_calib_top_n_428;\n wire u_ddr_calib_top_n_429;\n wire u_ddr_calib_top_n_430;\n wire u_ddr_calib_top_n_431;\n wire u_ddr_calib_top_n_432;\n wire u_ddr_calib_top_n_433;\n wire u_ddr_calib_top_n_434;\n wire u_ddr_calib_top_n_435;\n wire u_ddr_calib_top_n_436;\n wire u_ddr_calib_top_n_437;\n wire u_ddr_calib_top_n_438;\n wire u_ddr_calib_top_n_439;\n wire u_ddr_calib_top_n_441;\n wire u_ddr_calib_top_n_442;\n wire u_ddr_calib_top_n_443;\n wire u_ddr_calib_top_n_444;\n wire u_ddr_calib_top_n_445;\n wire u_ddr_calib_top_n_446;\n wire u_ddr_calib_top_n_447;\n wire u_ddr_calib_top_n_448;\n wire u_ddr_calib_top_n_449;\n wire u_ddr_calib_top_n_45;\n wire u_ddr_calib_top_n_450;\n wire u_ddr_calib_top_n_451;\n wire u_ddr_calib_top_n_452;\n wire u_ddr_calib_top_n_453;\n wire u_ddr_calib_top_n_454;\n wire u_ddr_calib_top_n_455;\n wire u_ddr_calib_top_n_456;\n wire u_ddr_calib_top_n_457;\n wire u_ddr_calib_top_n_458;\n wire u_ddr_calib_top_n_461;\n wire u_ddr_calib_top_n_464;\n wire u_ddr_calib_top_n_47;\n wire u_ddr_calib_top_n_50;\n wire u_ddr_calib_top_n_809;\n wire u_ddr_calib_top_n_810;\n wire u_ddr_calib_top_n_837;\n wire u_ddr_calib_top_n_838;\n wire u_ddr_calib_top_n_844;\n wire u_ddr_calib_top_n_845;\n wire u_ddr_calib_top_n_859;\n wire u_ddr_calib_top_n_860;\n wire u_ddr_calib_top_n_861;\n wire u_ddr_calib_top_n_862;\n wire u_ddr_calib_top_n_863;\n wire u_ddr_calib_top_n_864;\n wire u_ddr_calib_top_n_865;\n wire u_ddr_calib_top_n_879;\n wire u_ddr_calib_top_n_880;\n wire u_ddr_calib_top_n_881;\n wire u_ddr_calib_top_n_882;\n wire u_ddr_calib_top_n_883;\n wire u_ddr_calib_top_n_884;\n wire u_ddr_calib_top_n_885;\n wire u_ddr_calib_top_n_886;\n wire [2:2]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_fine_delay ;\n wire [26:5]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay ;\n wire [5:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_pi_counter_load_val ;\n wire [26:5]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay ;\n wire [5:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_counter_load_val ;\n wire [26:5]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay ;\n wire [5:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_counter_load_val ;\n wire \\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0 ;\n wire \\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst ;\n wire [4:4]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ;\n wire [0:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7 ;\n wire [0:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r ;\n wire \\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/LD0 ;\n wire \\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/idelay_ld_rst ;\n wire [4:4]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ;\n wire [8:8]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8 ;\n wire [8:8]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r ;\n wire \\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0 ;\n wire \\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst ;\n wire [4:4]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ;\n wire [8:8]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ;\n wire [8:8]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r ;\n wire \\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/LD0 ;\n wire \\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/idelay_ld_rst ;\n wire [4:4]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ;\n wire [8:8]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ;\n wire [8:8]\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r ;\n wire \\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_coarse_enable110_out ;\n wire \\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_counter_read_en122_out ;\n wire \\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_enable107_out ;\n wire \\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_inc113_out ;\n wire \\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_sel_fine_oclk_delay125_out ;\n wire [2:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0 ;\n wire [2:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ;\n wire [3:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ;\n wire [7:4]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ;\n wire [7:4]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ;\n wire [2:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ;\n wire [2:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ;\n wire [3:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ;\n wire [7:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ;\n wire [3:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ;\n wire [3:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ;\n wire [3:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9 ;\n wire [67:8]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out ;\n wire [3:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 ;\n wire [3:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ;\n wire [3:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ;\n wire [3:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ;\n wire [3:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ;\n wire [3:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ;\n wire [3:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ;\n wire [3:0]\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ;\n wire [5:0]\\u_ddr_mc_phy/pi_counter_read_val_w[0]_1 ;\n wire [8:0]\\u_ddr_mc_phy/po_counter_read_val_w[0]_0 ;\n wire [8:0]\\u_ddr_mc_phy/po_counter_read_val_w[1]_2 ;\n wire u_ddr_mc_phy_wrapper_n_1000;\n wire u_ddr_mc_phy_wrapper_n_1001;\n wire u_ddr_mc_phy_wrapper_n_1002;\n wire u_ddr_mc_phy_wrapper_n_1003;\n wire u_ddr_mc_phy_wrapper_n_1004;\n wire u_ddr_mc_phy_wrapper_n_1005;\n wire u_ddr_mc_phy_wrapper_n_1006;\n wire u_ddr_mc_phy_wrapper_n_1007;\n wire u_ddr_mc_phy_wrapper_n_1008;\n wire u_ddr_mc_phy_wrapper_n_1009;\n wire u_ddr_mc_phy_wrapper_n_1010;\n wire u_ddr_mc_phy_wrapper_n_1011;\n wire u_ddr_mc_phy_wrapper_n_1012;\n wire u_ddr_mc_phy_wrapper_n_1013;\n wire u_ddr_mc_phy_wrapper_n_1014;\n wire u_ddr_mc_phy_wrapper_n_1015;\n wire u_ddr_mc_phy_wrapper_n_1016;\n wire u_ddr_mc_phy_wrapper_n_1017;\n wire u_ddr_mc_phy_wrapper_n_1018;\n wire u_ddr_mc_phy_wrapper_n_1019;\n wire u_ddr_mc_phy_wrapper_n_102;\n wire u_ddr_mc_phy_wrapper_n_1020;\n wire u_ddr_mc_phy_wrapper_n_1021;\n wire u_ddr_mc_phy_wrapper_n_1022;\n wire u_ddr_mc_phy_wrapper_n_1023;\n wire u_ddr_mc_phy_wrapper_n_1024;\n wire u_ddr_mc_phy_wrapper_n_1025;\n wire u_ddr_mc_phy_wrapper_n_1026;\n wire u_ddr_mc_phy_wrapper_n_1027;\n wire u_ddr_mc_phy_wrapper_n_1028;\n wire u_ddr_mc_phy_wrapper_n_1029;\n wire u_ddr_mc_phy_wrapper_n_1030;\n wire u_ddr_mc_phy_wrapper_n_1033;\n wire u_ddr_mc_phy_wrapper_n_1034;\n wire u_ddr_mc_phy_wrapper_n_1035;\n wire u_ddr_mc_phy_wrapper_n_1036;\n wire u_ddr_mc_phy_wrapper_n_1037;\n wire u_ddr_mc_phy_wrapper_n_1038;\n wire u_ddr_mc_phy_wrapper_n_1039;\n wire u_ddr_mc_phy_wrapper_n_104;\n wire u_ddr_mc_phy_wrapper_n_1040;\n wire u_ddr_mc_phy_wrapper_n_1041;\n wire u_ddr_mc_phy_wrapper_n_1042;\n wire u_ddr_mc_phy_wrapper_n_1043;\n wire u_ddr_mc_phy_wrapper_n_1044;\n wire u_ddr_mc_phy_wrapper_n_1045;\n wire u_ddr_mc_phy_wrapper_n_1046;\n wire u_ddr_mc_phy_wrapper_n_1047;\n wire u_ddr_mc_phy_wrapper_n_1048;\n wire u_ddr_mc_phy_wrapper_n_1049;\n wire u_ddr_mc_phy_wrapper_n_1050;\n wire u_ddr_mc_phy_wrapper_n_1051;\n wire u_ddr_mc_phy_wrapper_n_1052;\n wire u_ddr_mc_phy_wrapper_n_1053;\n wire u_ddr_mc_phy_wrapper_n_1054;\n wire u_ddr_mc_phy_wrapper_n_1055;\n wire u_ddr_mc_phy_wrapper_n_1056;\n wire u_ddr_mc_phy_wrapper_n_1057;\n wire u_ddr_mc_phy_wrapper_n_1058;\n wire u_ddr_mc_phy_wrapper_n_1059;\n wire u_ddr_mc_phy_wrapper_n_106;\n wire u_ddr_mc_phy_wrapper_n_1060;\n wire u_ddr_mc_phy_wrapper_n_1061;\n wire u_ddr_mc_phy_wrapper_n_1062;\n wire u_ddr_mc_phy_wrapper_n_1063;\n wire u_ddr_mc_phy_wrapper_n_1064;\n wire u_ddr_mc_phy_wrapper_n_1065;\n wire u_ddr_mc_phy_wrapper_n_1066;\n wire u_ddr_mc_phy_wrapper_n_1067;\n wire u_ddr_mc_phy_wrapper_n_1068;\n wire u_ddr_mc_phy_wrapper_n_1069;\n wire u_ddr_mc_phy_wrapper_n_107;\n wire u_ddr_mc_phy_wrapper_n_1070;\n wire u_ddr_mc_phy_wrapper_n_1071;\n wire u_ddr_mc_phy_wrapper_n_1072;\n wire u_ddr_mc_phy_wrapper_n_1073;\n wire u_ddr_mc_phy_wrapper_n_1074;\n wire u_ddr_mc_phy_wrapper_n_1075;\n wire u_ddr_mc_phy_wrapper_n_1076;\n wire u_ddr_mc_phy_wrapper_n_1077;\n wire u_ddr_mc_phy_wrapper_n_1078;\n wire u_ddr_mc_phy_wrapper_n_1079;\n wire u_ddr_mc_phy_wrapper_n_108;\n wire u_ddr_mc_phy_wrapper_n_1080;\n wire u_ddr_mc_phy_wrapper_n_1081;\n wire u_ddr_mc_phy_wrapper_n_1082;\n wire u_ddr_mc_phy_wrapper_n_1083;\n wire u_ddr_mc_phy_wrapper_n_1084;\n wire u_ddr_mc_phy_wrapper_n_1085;\n wire u_ddr_mc_phy_wrapper_n_1086;\n wire u_ddr_mc_phy_wrapper_n_1087;\n wire u_ddr_mc_phy_wrapper_n_1088;\n wire u_ddr_mc_phy_wrapper_n_1089;\n wire u_ddr_mc_phy_wrapper_n_109;\n wire u_ddr_mc_phy_wrapper_n_1090;\n wire u_ddr_mc_phy_wrapper_n_1091;\n wire u_ddr_mc_phy_wrapper_n_1092;\n wire u_ddr_mc_phy_wrapper_n_1093;\n wire u_ddr_mc_phy_wrapper_n_1094;\n wire u_ddr_mc_phy_wrapper_n_1095;\n wire u_ddr_mc_phy_wrapper_n_1096;\n wire u_ddr_mc_phy_wrapper_n_110;\n wire u_ddr_mc_phy_wrapper_n_111;\n wire u_ddr_mc_phy_wrapper_n_112;\n wire u_ddr_mc_phy_wrapper_n_1127;\n wire u_ddr_mc_phy_wrapper_n_1129;\n wire u_ddr_mc_phy_wrapper_n_1130;\n wire u_ddr_mc_phy_wrapper_n_1131;\n wire u_ddr_mc_phy_wrapper_n_1132;\n wire u_ddr_mc_phy_wrapper_n_1133;\n wire u_ddr_mc_phy_wrapper_n_1134;\n wire u_ddr_mc_phy_wrapper_n_1135;\n wire u_ddr_mc_phy_wrapper_n_1136;\n wire u_ddr_mc_phy_wrapper_n_1137;\n wire u_ddr_mc_phy_wrapper_n_1138;\n wire u_ddr_mc_phy_wrapper_n_1139;\n wire u_ddr_mc_phy_wrapper_n_1140;\n wire u_ddr_mc_phy_wrapper_n_1141;\n wire u_ddr_mc_phy_wrapper_n_1142;\n wire u_ddr_mc_phy_wrapper_n_1143;\n wire u_ddr_mc_phy_wrapper_n_1144;\n wire u_ddr_mc_phy_wrapper_n_1145;\n wire u_ddr_mc_phy_wrapper_n_1146;\n wire u_ddr_mc_phy_wrapper_n_1147;\n wire u_ddr_mc_phy_wrapper_n_1148;\n wire u_ddr_mc_phy_wrapper_n_1149;\n wire u_ddr_mc_phy_wrapper_n_1150;\n wire u_ddr_mc_phy_wrapper_n_1151;\n wire u_ddr_mc_phy_wrapper_n_1152;\n wire u_ddr_mc_phy_wrapper_n_1153;\n wire u_ddr_mc_phy_wrapper_n_1154;\n wire u_ddr_mc_phy_wrapper_n_1155;\n wire u_ddr_mc_phy_wrapper_n_1156;\n wire u_ddr_mc_phy_wrapper_n_1157;\n wire u_ddr_mc_phy_wrapper_n_1158;\n wire u_ddr_mc_phy_wrapper_n_1159;\n wire u_ddr_mc_phy_wrapper_n_1160;\n wire u_ddr_mc_phy_wrapper_n_1161;\n wire u_ddr_mc_phy_wrapper_n_1162;\n wire u_ddr_mc_phy_wrapper_n_1163;\n wire u_ddr_mc_phy_wrapper_n_1164;\n wire u_ddr_mc_phy_wrapper_n_1165;\n wire u_ddr_mc_phy_wrapper_n_1166;\n wire u_ddr_mc_phy_wrapper_n_1167;\n wire u_ddr_mc_phy_wrapper_n_1168;\n wire u_ddr_mc_phy_wrapper_n_1169;\n wire u_ddr_mc_phy_wrapper_n_1170;\n wire u_ddr_mc_phy_wrapper_n_1171;\n wire u_ddr_mc_phy_wrapper_n_1172;\n wire u_ddr_mc_phy_wrapper_n_1173;\n wire u_ddr_mc_phy_wrapper_n_1174;\n wire u_ddr_mc_phy_wrapper_n_1175;\n wire u_ddr_mc_phy_wrapper_n_1176;\n wire u_ddr_mc_phy_wrapper_n_1177;\n wire u_ddr_mc_phy_wrapper_n_1178;\n wire u_ddr_mc_phy_wrapper_n_1179;\n wire u_ddr_mc_phy_wrapper_n_1180;\n wire u_ddr_mc_phy_wrapper_n_1181;\n wire u_ddr_mc_phy_wrapper_n_1182;\n wire u_ddr_mc_phy_wrapper_n_1183;\n wire u_ddr_mc_phy_wrapper_n_1184;\n wire u_ddr_mc_phy_wrapper_n_1185;\n wire u_ddr_mc_phy_wrapper_n_1186;\n wire u_ddr_mc_phy_wrapper_n_1187;\n wire u_ddr_mc_phy_wrapper_n_1188;\n wire u_ddr_mc_phy_wrapper_n_1189;\n wire u_ddr_mc_phy_wrapper_n_1190;\n wire u_ddr_mc_phy_wrapper_n_1191;\n wire u_ddr_mc_phy_wrapper_n_30;\n wire u_ddr_mc_phy_wrapper_n_43;\n wire u_ddr_mc_phy_wrapper_n_434;\n wire u_ddr_mc_phy_wrapper_n_435;\n wire u_ddr_mc_phy_wrapper_n_436;\n wire u_ddr_mc_phy_wrapper_n_437;\n wire u_ddr_mc_phy_wrapper_n_438;\n wire u_ddr_mc_phy_wrapper_n_439;\n wire u_ddr_mc_phy_wrapper_n_44;\n wire u_ddr_mc_phy_wrapper_n_440;\n wire u_ddr_mc_phy_wrapper_n_441;\n wire u_ddr_mc_phy_wrapper_n_442;\n wire u_ddr_mc_phy_wrapper_n_443;\n wire u_ddr_mc_phy_wrapper_n_444;\n wire u_ddr_mc_phy_wrapper_n_445;\n wire u_ddr_mc_phy_wrapper_n_446;\n wire u_ddr_mc_phy_wrapper_n_447;\n wire u_ddr_mc_phy_wrapper_n_448;\n wire u_ddr_mc_phy_wrapper_n_449;\n wire u_ddr_mc_phy_wrapper_n_45;\n wire u_ddr_mc_phy_wrapper_n_450;\n wire u_ddr_mc_phy_wrapper_n_451;\n wire u_ddr_mc_phy_wrapper_n_452;\n wire u_ddr_mc_phy_wrapper_n_453;\n wire u_ddr_mc_phy_wrapper_n_454;\n wire u_ddr_mc_phy_wrapper_n_455;\n wire u_ddr_mc_phy_wrapper_n_456;\n wire u_ddr_mc_phy_wrapper_n_457;\n wire u_ddr_mc_phy_wrapper_n_458;\n wire u_ddr_mc_phy_wrapper_n_459;\n wire u_ddr_mc_phy_wrapper_n_46;\n wire u_ddr_mc_phy_wrapper_n_460;\n wire u_ddr_mc_phy_wrapper_n_461;\n wire u_ddr_mc_phy_wrapper_n_462;\n wire u_ddr_mc_phy_wrapper_n_463;\n wire u_ddr_mc_phy_wrapper_n_464;\n wire u_ddr_mc_phy_wrapper_n_465;\n wire u_ddr_mc_phy_wrapper_n_466;\n wire u_ddr_mc_phy_wrapper_n_467;\n wire u_ddr_mc_phy_wrapper_n_468;\n wire u_ddr_mc_phy_wrapper_n_469;\n wire u_ddr_mc_phy_wrapper_n_470;\n wire u_ddr_mc_phy_wrapper_n_471;\n wire u_ddr_mc_phy_wrapper_n_472;\n wire u_ddr_mc_phy_wrapper_n_473;\n wire u_ddr_mc_phy_wrapper_n_474;\n wire u_ddr_mc_phy_wrapper_n_475;\n wire u_ddr_mc_phy_wrapper_n_476;\n wire u_ddr_mc_phy_wrapper_n_477;\n wire u_ddr_mc_phy_wrapper_n_478;\n wire u_ddr_mc_phy_wrapper_n_479;\n wire u_ddr_mc_phy_wrapper_n_480;\n wire u_ddr_mc_phy_wrapper_n_481;\n wire u_ddr_mc_phy_wrapper_n_482;\n wire u_ddr_mc_phy_wrapper_n_483;\n wire u_ddr_mc_phy_wrapper_n_484;\n wire u_ddr_mc_phy_wrapper_n_485;\n wire u_ddr_mc_phy_wrapper_n_486;\n wire u_ddr_mc_phy_wrapper_n_487;\n wire u_ddr_mc_phy_wrapper_n_488;\n wire u_ddr_mc_phy_wrapper_n_489;\n wire u_ddr_mc_phy_wrapper_n_490;\n wire u_ddr_mc_phy_wrapper_n_491;\n wire u_ddr_mc_phy_wrapper_n_492;\n wire u_ddr_mc_phy_wrapper_n_493;\n wire u_ddr_mc_phy_wrapper_n_494;\n wire u_ddr_mc_phy_wrapper_n_495;\n wire u_ddr_mc_phy_wrapper_n_496;\n wire u_ddr_mc_phy_wrapper_n_497;\n wire u_ddr_mc_phy_wrapper_n_60;\n wire u_ddr_mc_phy_wrapper_n_61;\n wire u_ddr_mc_phy_wrapper_n_63;\n wire u_ddr_mc_phy_wrapper_n_64;\n wire u_ddr_mc_phy_wrapper_n_65;\n wire u_ddr_mc_phy_wrapper_n_66;\n wire u_ddr_mc_phy_wrapper_n_67;\n wire u_ddr_mc_phy_wrapper_n_756;\n wire u_ddr_mc_phy_wrapper_n_757;\n wire u_ddr_mc_phy_wrapper_n_758;\n wire u_ddr_mc_phy_wrapper_n_759;\n wire u_ddr_mc_phy_wrapper_n_760;\n wire u_ddr_mc_phy_wrapper_n_761;\n wire u_ddr_mc_phy_wrapper_n_762;\n wire u_ddr_mc_phy_wrapper_n_763;\n wire u_ddr_mc_phy_wrapper_n_764;\n wire u_ddr_mc_phy_wrapper_n_765;\n wire u_ddr_mc_phy_wrapper_n_766;\n wire u_ddr_mc_phy_wrapper_n_767;\n wire u_ddr_mc_phy_wrapper_n_768;\n wire u_ddr_mc_phy_wrapper_n_769;\n wire u_ddr_mc_phy_wrapper_n_770;\n wire u_ddr_mc_phy_wrapper_n_771;\n wire u_ddr_mc_phy_wrapper_n_772;\n wire u_ddr_mc_phy_wrapper_n_773;\n wire u_ddr_mc_phy_wrapper_n_774;\n wire u_ddr_mc_phy_wrapper_n_775;\n wire u_ddr_mc_phy_wrapper_n_776;\n wire u_ddr_mc_phy_wrapper_n_777;\n wire u_ddr_mc_phy_wrapper_n_778;\n wire u_ddr_mc_phy_wrapper_n_779;\n wire u_ddr_mc_phy_wrapper_n_780;\n wire u_ddr_mc_phy_wrapper_n_781;\n wire u_ddr_mc_phy_wrapper_n_782;\n wire u_ddr_mc_phy_wrapper_n_783;\n wire u_ddr_mc_phy_wrapper_n_784;\n wire u_ddr_mc_phy_wrapper_n_785;\n wire u_ddr_mc_phy_wrapper_n_786;\n wire u_ddr_mc_phy_wrapper_n_787;\n wire u_ddr_mc_phy_wrapper_n_788;\n wire u_ddr_mc_phy_wrapper_n_789;\n wire u_ddr_mc_phy_wrapper_n_790;\n wire u_ddr_mc_phy_wrapper_n_791;\n wire u_ddr_mc_phy_wrapper_n_792;\n wire u_ddr_mc_phy_wrapper_n_793;\n wire u_ddr_mc_phy_wrapper_n_794;\n wire u_ddr_mc_phy_wrapper_n_795;\n wire u_ddr_mc_phy_wrapper_n_796;\n wire u_ddr_mc_phy_wrapper_n_797;\n wire u_ddr_mc_phy_wrapper_n_798;\n wire u_ddr_mc_phy_wrapper_n_799;\n wire u_ddr_mc_phy_wrapper_n_800;\n wire u_ddr_mc_phy_wrapper_n_801;\n wire u_ddr_mc_phy_wrapper_n_802;\n wire u_ddr_mc_phy_wrapper_n_803;\n wire u_ddr_mc_phy_wrapper_n_804;\n wire u_ddr_mc_phy_wrapper_n_805;\n wire u_ddr_mc_phy_wrapper_n_806;\n wire u_ddr_mc_phy_wrapper_n_807;\n wire u_ddr_mc_phy_wrapper_n_808;\n wire u_ddr_mc_phy_wrapper_n_809;\n wire u_ddr_mc_phy_wrapper_n_810;\n wire u_ddr_mc_phy_wrapper_n_811;\n wire u_ddr_mc_phy_wrapper_n_812;\n wire u_ddr_mc_phy_wrapper_n_813;\n wire u_ddr_mc_phy_wrapper_n_814;\n wire u_ddr_mc_phy_wrapper_n_815;\n wire u_ddr_mc_phy_wrapper_n_816;\n wire u_ddr_mc_phy_wrapper_n_817;\n wire u_ddr_mc_phy_wrapper_n_818;\n wire u_ddr_mc_phy_wrapper_n_819;\n wire u_ddr_mc_phy_wrapper_n_820;\n wire u_ddr_mc_phy_wrapper_n_835;\n wire u_ddr_mc_phy_wrapper_n_836;\n wire u_ddr_mc_phy_wrapper_n_837;\n wire u_ddr_mc_phy_wrapper_n_838;\n wire u_ddr_mc_phy_wrapper_n_839;\n wire u_ddr_mc_phy_wrapper_n_840;\n wire u_ddr_mc_phy_wrapper_n_841;\n wire u_ddr_mc_phy_wrapper_n_842;\n wire u_ddr_mc_phy_wrapper_n_843;\n wire u_ddr_mc_phy_wrapper_n_844;\n wire u_ddr_mc_phy_wrapper_n_845;\n wire u_ddr_mc_phy_wrapper_n_846;\n wire u_ddr_mc_phy_wrapper_n_847;\n wire u_ddr_mc_phy_wrapper_n_848;\n wire u_ddr_mc_phy_wrapper_n_849;\n wire u_ddr_mc_phy_wrapper_n_850;\n wire u_ddr_mc_phy_wrapper_n_851;\n wire u_ddr_mc_phy_wrapper_n_852;\n wire u_ddr_mc_phy_wrapper_n_853;\n wire u_ddr_mc_phy_wrapper_n_854;\n wire u_ddr_mc_phy_wrapper_n_855;\n wire u_ddr_mc_phy_wrapper_n_856;\n wire u_ddr_mc_phy_wrapper_n_857;\n wire u_ddr_mc_phy_wrapper_n_858;\n wire u_ddr_mc_phy_wrapper_n_859;\n wire u_ddr_mc_phy_wrapper_n_860;\n wire u_ddr_mc_phy_wrapper_n_861;\n wire u_ddr_mc_phy_wrapper_n_862;\n wire u_ddr_mc_phy_wrapper_n_863;\n wire u_ddr_mc_phy_wrapper_n_864;\n wire u_ddr_mc_phy_wrapper_n_865;\n wire u_ddr_mc_phy_wrapper_n_866;\n wire u_ddr_mc_phy_wrapper_n_867;\n wire u_ddr_mc_phy_wrapper_n_868;\n wire u_ddr_mc_phy_wrapper_n_869;\n wire u_ddr_mc_phy_wrapper_n_870;\n wire u_ddr_mc_phy_wrapper_n_871;\n wire u_ddr_mc_phy_wrapper_n_872;\n wire u_ddr_mc_phy_wrapper_n_873;\n wire u_ddr_mc_phy_wrapper_n_874;\n wire u_ddr_mc_phy_wrapper_n_875;\n wire u_ddr_mc_phy_wrapper_n_876;\n wire u_ddr_mc_phy_wrapper_n_877;\n wire u_ddr_mc_phy_wrapper_n_878;\n wire u_ddr_mc_phy_wrapper_n_879;\n wire u_ddr_mc_phy_wrapper_n_880;\n wire u_ddr_mc_phy_wrapper_n_881;\n wire u_ddr_mc_phy_wrapper_n_882;\n wire u_ddr_mc_phy_wrapper_n_883;\n wire u_ddr_mc_phy_wrapper_n_884;\n wire u_ddr_mc_phy_wrapper_n_885;\n wire u_ddr_mc_phy_wrapper_n_886;\n wire u_ddr_mc_phy_wrapper_n_887;\n wire u_ddr_mc_phy_wrapper_n_888;\n wire u_ddr_mc_phy_wrapper_n_889;\n wire u_ddr_mc_phy_wrapper_n_890;\n wire u_ddr_mc_phy_wrapper_n_891;\n wire u_ddr_mc_phy_wrapper_n_892;\n wire u_ddr_mc_phy_wrapper_n_893;\n wire u_ddr_mc_phy_wrapper_n_894;\n wire u_ddr_mc_phy_wrapper_n_895;\n wire u_ddr_mc_phy_wrapper_n_896;\n wire u_ddr_mc_phy_wrapper_n_897;\n wire u_ddr_mc_phy_wrapper_n_898;\n wire u_ddr_mc_phy_wrapper_n_901;\n wire u_ddr_mc_phy_wrapper_n_902;\n wire u_ddr_mc_phy_wrapper_n_903;\n wire u_ddr_mc_phy_wrapper_n_904;\n wire u_ddr_mc_phy_wrapper_n_905;\n wire u_ddr_mc_phy_wrapper_n_906;\n wire u_ddr_mc_phy_wrapper_n_907;\n wire u_ddr_mc_phy_wrapper_n_908;\n wire u_ddr_mc_phy_wrapper_n_909;\n wire u_ddr_mc_phy_wrapper_n_910;\n wire u_ddr_mc_phy_wrapper_n_911;\n wire u_ddr_mc_phy_wrapper_n_912;\n wire u_ddr_mc_phy_wrapper_n_913;\n wire u_ddr_mc_phy_wrapper_n_914;\n wire u_ddr_mc_phy_wrapper_n_915;\n wire u_ddr_mc_phy_wrapper_n_916;\n wire u_ddr_mc_phy_wrapper_n_917;\n wire u_ddr_mc_phy_wrapper_n_918;\n wire u_ddr_mc_phy_wrapper_n_919;\n wire u_ddr_mc_phy_wrapper_n_920;\n wire u_ddr_mc_phy_wrapper_n_921;\n wire u_ddr_mc_phy_wrapper_n_922;\n wire u_ddr_mc_phy_wrapper_n_923;\n wire u_ddr_mc_phy_wrapper_n_924;\n wire u_ddr_mc_phy_wrapper_n_925;\n wire u_ddr_mc_phy_wrapper_n_926;\n wire u_ddr_mc_phy_wrapper_n_927;\n wire u_ddr_mc_phy_wrapper_n_928;\n wire u_ddr_mc_phy_wrapper_n_929;\n wire u_ddr_mc_phy_wrapper_n_930;\n wire u_ddr_mc_phy_wrapper_n_931;\n wire u_ddr_mc_phy_wrapper_n_932;\n wire u_ddr_mc_phy_wrapper_n_933;\n wire u_ddr_mc_phy_wrapper_n_934;\n wire u_ddr_mc_phy_wrapper_n_935;\n wire u_ddr_mc_phy_wrapper_n_936;\n wire u_ddr_mc_phy_wrapper_n_937;\n wire u_ddr_mc_phy_wrapper_n_938;\n wire u_ddr_mc_phy_wrapper_n_939;\n wire u_ddr_mc_phy_wrapper_n_940;\n wire u_ddr_mc_phy_wrapper_n_941;\n wire u_ddr_mc_phy_wrapper_n_942;\n wire u_ddr_mc_phy_wrapper_n_943;\n wire u_ddr_mc_phy_wrapper_n_944;\n wire u_ddr_mc_phy_wrapper_n_945;\n wire u_ddr_mc_phy_wrapper_n_946;\n wire u_ddr_mc_phy_wrapper_n_947;\n wire u_ddr_mc_phy_wrapper_n_948;\n wire u_ddr_mc_phy_wrapper_n_949;\n wire u_ddr_mc_phy_wrapper_n_950;\n wire u_ddr_mc_phy_wrapper_n_951;\n wire u_ddr_mc_phy_wrapper_n_952;\n wire u_ddr_mc_phy_wrapper_n_953;\n wire u_ddr_mc_phy_wrapper_n_954;\n wire u_ddr_mc_phy_wrapper_n_955;\n wire u_ddr_mc_phy_wrapper_n_956;\n wire u_ddr_mc_phy_wrapper_n_957;\n wire u_ddr_mc_phy_wrapper_n_958;\n wire u_ddr_mc_phy_wrapper_n_959;\n wire u_ddr_mc_phy_wrapper_n_960;\n wire u_ddr_mc_phy_wrapper_n_961;\n wire u_ddr_mc_phy_wrapper_n_962;\n wire u_ddr_mc_phy_wrapper_n_963;\n wire u_ddr_mc_phy_wrapper_n_964;\n wire u_ddr_mc_phy_wrapper_n_967;\n wire u_ddr_mc_phy_wrapper_n_968;\n wire u_ddr_mc_phy_wrapper_n_969;\n wire u_ddr_mc_phy_wrapper_n_970;\n wire u_ddr_mc_phy_wrapper_n_971;\n wire u_ddr_mc_phy_wrapper_n_972;\n wire u_ddr_mc_phy_wrapper_n_973;\n wire u_ddr_mc_phy_wrapper_n_974;\n wire u_ddr_mc_phy_wrapper_n_975;\n wire u_ddr_mc_phy_wrapper_n_976;\n wire u_ddr_mc_phy_wrapper_n_977;\n wire u_ddr_mc_phy_wrapper_n_978;\n wire u_ddr_mc_phy_wrapper_n_979;\n wire u_ddr_mc_phy_wrapper_n_980;\n wire u_ddr_mc_phy_wrapper_n_981;\n wire u_ddr_mc_phy_wrapper_n_982;\n wire u_ddr_mc_phy_wrapper_n_983;\n wire u_ddr_mc_phy_wrapper_n_984;\n wire u_ddr_mc_phy_wrapper_n_985;\n wire u_ddr_mc_phy_wrapper_n_986;\n wire u_ddr_mc_phy_wrapper_n_987;\n wire u_ddr_mc_phy_wrapper_n_988;\n wire u_ddr_mc_phy_wrapper_n_989;\n wire u_ddr_mc_phy_wrapper_n_990;\n wire u_ddr_mc_phy_wrapper_n_991;\n wire u_ddr_mc_phy_wrapper_n_992;\n wire u_ddr_mc_phy_wrapper_n_993;\n wire u_ddr_mc_phy_wrapper_n_994;\n wire u_ddr_mc_phy_wrapper_n_995;\n wire u_ddr_mc_phy_wrapper_n_996;\n wire u_ddr_mc_phy_wrapper_n_997;\n wire u_ddr_mc_phy_wrapper_n_998;\n wire u_ddr_mc_phy_wrapper_n_999;\n wire \\u_ddr_phy_wrcal/p_0_out ;\n wire wr_en;\n wire wr_en_5;\n wire wr_en_6;\n wire [3:0]\\wr_ptr_timing_reg[2] ;\n wire [3:0]\\wr_ptr_timing_reg[2]_0 ;\n wire [3:0]\\wr_ptr_timing_reg[2]_1 ;\n\n ddr3_if_mig_7series_v4_0_ddr_calib_top u_ddr_calib_top\n (.A(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl/A ),\n .\\A[0]__0 (u_ddr_calib_top_n_881),\n .\\A[0]__4 (u_ddr_calib_top_n_880),\n .\\A[1]_0 (u_ddr_mc_phy_wrapper_n_813),\n .\\A[1]_1 (u_ddr_mc_phy_wrapper_n_805),\n .\\A[1]_10 (u_ddr_mc_phy_wrapper_n_798),\n .\\A[1]_11 (u_ddr_mc_phy_wrapper_n_790),\n .\\A[1]_12 (u_ddr_mc_phy_wrapper_n_782),\n .\\A[1]_13 (u_ddr_mc_phy_wrapper_n_774),\n .\\A[1]_14 (u_ddr_mc_phy_wrapper_n_766),\n .\\A[1]_15 (u_ddr_mc_phy_wrapper_n_758),\n .\\A[1]_16 (u_ddr_mc_phy_wrapper_n_815),\n .\\A[1]_17 (u_ddr_mc_phy_wrapper_n_807),\n .\\A[1]_18 (u_ddr_mc_phy_wrapper_n_799),\n .\\A[1]_19 (u_ddr_mc_phy_wrapper_n_791),\n .\\A[1]_2 (u_ddr_mc_phy_wrapper_n_797),\n .\\A[1]_20 (u_ddr_mc_phy_wrapper_n_783),\n .\\A[1]_21 (u_ddr_mc_phy_wrapper_n_775),\n .\\A[1]_22 (u_ddr_mc_phy_wrapper_n_767),\n .\\A[1]_23 (u_ddr_mc_phy_wrapper_n_759),\n .\\A[1]_24 (u_ddr_mc_phy_wrapper_n_816),\n .\\A[1]_25 (u_ddr_mc_phy_wrapper_n_808),\n .\\A[1]_26 (u_ddr_mc_phy_wrapper_n_800),\n .\\A[1]_27 (u_ddr_mc_phy_wrapper_n_792),\n .\\A[1]_28 (u_ddr_mc_phy_wrapper_n_784),\n .\\A[1]_29 (u_ddr_mc_phy_wrapper_n_776),\n .\\A[1]_3 (u_ddr_mc_phy_wrapper_n_789),\n .\\A[1]_30 (u_ddr_mc_phy_wrapper_n_768),\n .\\A[1]_31 (u_ddr_mc_phy_wrapper_n_760),\n .\\A[1]_32 (u_ddr_mc_phy_wrapper_n_817),\n .\\A[1]_33 (u_ddr_mc_phy_wrapper_n_809),\n .\\A[1]_34 (u_ddr_mc_phy_wrapper_n_801),\n .\\A[1]_35 (u_ddr_mc_phy_wrapper_n_793),\n .\\A[1]_36 (u_ddr_mc_phy_wrapper_n_785),\n .\\A[1]_37 (u_ddr_mc_phy_wrapper_n_777),\n .\\A[1]_38 (u_ddr_mc_phy_wrapper_n_769),\n .\\A[1]_39 (u_ddr_mc_phy_wrapper_n_761),\n .\\A[1]_4 (u_ddr_mc_phy_wrapper_n_781),\n .\\A[1]_40 (u_ddr_mc_phy_wrapper_n_818),\n .\\A[1]_41 (u_ddr_mc_phy_wrapper_n_810),\n .\\A[1]_42 (u_ddr_mc_phy_wrapper_n_802),\n .\\A[1]_43 (u_ddr_mc_phy_wrapper_n_794),\n .\\A[1]_44 (u_ddr_mc_phy_wrapper_n_786),\n .\\A[1]_45 (u_ddr_mc_phy_wrapper_n_778),\n .\\A[1]_46 (u_ddr_mc_phy_wrapper_n_770),\n .\\A[1]_47 (u_ddr_mc_phy_wrapper_n_762),\n .\\A[1]_48 (u_ddr_mc_phy_wrapper_n_819),\n .\\A[1]_49 (u_ddr_mc_phy_wrapper_n_811),\n .\\A[1]_5 (u_ddr_mc_phy_wrapper_n_773),\n .\\A[1]_50 (u_ddr_mc_phy_wrapper_n_803),\n .\\A[1]_51 (u_ddr_mc_phy_wrapper_n_795),\n .\\A[1]_52 (u_ddr_mc_phy_wrapper_n_787),\n .\\A[1]_53 (u_ddr_mc_phy_wrapper_n_779),\n .\\A[1]_54 (u_ddr_mc_phy_wrapper_n_771),\n .\\A[1]_55 (u_ddr_mc_phy_wrapper_n_763),\n .\\A[1]_56 (u_ddr_mc_phy_wrapper_n_820),\n .\\A[1]_57 (u_ddr_mc_phy_wrapper_n_812),\n .\\A[1]_58 (u_ddr_mc_phy_wrapper_n_804),\n .\\A[1]_59 (u_ddr_mc_phy_wrapper_n_796),\n .\\A[1]_6 (u_ddr_mc_phy_wrapper_n_765),\n .\\A[1]_60 (u_ddr_mc_phy_wrapper_n_788),\n .\\A[1]_61 (u_ddr_mc_phy_wrapper_n_780),\n .\\A[1]_62 (u_ddr_mc_phy_wrapper_n_772),\n .\\A[1]_63 (u_ddr_mc_phy_wrapper_n_764),\n .\\A[1]_7 (u_ddr_mc_phy_wrapper_n_757),\n .\\A[1]_8 (u_ddr_mc_phy_wrapper_n_814),\n .\\A[1]_9 (u_ddr_mc_phy_wrapper_n_806),\n .\\A[1]__0 (u_ddr_calib_top_n_883),\n .\\A[1]__3 (u_ddr_calib_top_n_885),\n .\\A[1]__4 (u_ddr_calib_top_n_464),\n .\\A[1]__4_0 (u_ddr_calib_top_n_884),\n .\\A[2]__1 (u_ddr_calib_top_n_886),\n .\\A[2]__2 (u_ddr_calib_top_n_882),\n .\\A[2]__2_0 (u_ddr_mc_phy_wrapper_n_30),\n .A_1__s_port_(u_ddr_calib_top_n_461),\n .A_rst_primitives_reg(u_ddr_mc_phy_wrapper_n_756),\n .CLK(CLK),\n .COUNTERLOADVAL({u_ddr_calib_top_n_441,u_ddr_calib_top_n_442,u_ddr_calib_top_n_443,u_ddr_calib_top_n_444,u_ddr_calib_top_n_445,u_ddr_calib_top_n_446}),\n .D({u_ddr_calib_top_n_433,u_ddr_calib_top_n_434,u_ddr_calib_top_n_435,u_ddr_calib_top_n_436,u_ddr_calib_top_n_437,u_ddr_calib_top_n_438,u_ddr_calib_top_n_439,\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_fine_delay }),\n .D0(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0 ),\n .D1(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ),\n .D2(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ),\n .D3(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ),\n .D4(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ),\n .D5(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ),\n .D6(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ),\n .D7(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ),\n .D8(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ),\n .D9(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9 ),\n .D_po_coarse_enable110_out(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_coarse_enable110_out ),\n .D_po_counter_read_en122_out(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_counter_read_en122_out ),\n .D_po_fine_enable107_out(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_enable107_out ),\n .D_po_fine_inc113_out(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_inc113_out ),\n .D_po_sel_fine_oclk_delay125_out(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_sel_fine_oclk_delay125_out ),\n .E(\\resume_wait_r_reg[5] ),\n .LD0(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0 ),\n .LD0_0(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/LD0 ),\n .LD0_1(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0 ),\n .LD0_2(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/LD0 ),\n .Q(Q),\n .SR(SR),\n .SS(SS),\n .app_zq_r_reg(app_zq_r_reg),\n .\\byte_r_reg[0] (u_ddr_calib_top_n_809),\n .\\byte_r_reg[0]_0 ({\\oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_data/data_bytes_r0 ,\\oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_data/data_bytes_ns }),\n .\\byte_r_reg[1] (u_ddr_calib_top_n_810),\n .\\byte_sel_data_map_reg[1] (u_ddr_calib_top_n_879),\n .\\cmd_pipe_plus.mc_address_reg[44] ({\\cmd_pipe_plus.mc_address_reg[44] [37],\\cmd_pipe_plus.mc_address_reg[44] [35:14],\\cmd_pipe_plus.mc_address_reg[44] [12:0]}),\n .\\cmd_pipe_plus.mc_bank_reg[8] (\\cmd_pipe_plus.mc_bank_reg[8] ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[0] (\\cmd_pipe_plus.mc_data_offset_1_reg[0] ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 (\\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[1] (\\cmd_pipe_plus.mc_data_offset_1_reg[1] ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[1]_0 (\\cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[2] (\\cmd_pipe_plus.mc_data_offset_1_reg[2] ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[2]_0 (\\cmd_pipe_plus.mc_data_offset_1_reg[2]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[3] (\\cmd_pipe_plus.mc_data_offset_1_reg[3] ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[3]_0 (\\cmd_pipe_plus.mc_data_offset_1_reg[3]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[4] (\\cmd_pipe_plus.mc_data_offset_1_reg[4] ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[4]_0 (\\cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[5] (\\cmd_pipe_plus.mc_data_offset_1_reg[5] ),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[5]_0 (\\cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_reg[0] (\\cmd_pipe_plus.mc_data_offset_reg[0] ),\n .\\cmd_pipe_plus.mc_data_offset_reg[0]_0 (\\cmd_pipe_plus.mc_data_offset_reg[0]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_reg[1] (\\cmd_pipe_plus.mc_data_offset_reg[1] ),\n .\\cmd_pipe_plus.mc_data_offset_reg[1]_0 (\\cmd_pipe_plus.mc_data_offset_reg[1]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_reg[2] (\\cmd_pipe_plus.mc_data_offset_reg[2] ),\n .\\cmd_pipe_plus.mc_data_offset_reg[2]_0 (\\cmd_pipe_plus.mc_data_offset_reg[2]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_reg[3] (\\cmd_pipe_plus.mc_data_offset_reg[3] ),\n .\\cmd_pipe_plus.mc_data_offset_reg[3]_0 (\\cmd_pipe_plus.mc_data_offset_reg[3]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_reg[4] (\\cmd_pipe_plus.mc_data_offset_reg[4] ),\n .\\cmd_pipe_plus.mc_data_offset_reg[4]_0 (\\cmd_pipe_plus.mc_data_offset_reg[4]_0 ),\n .\\cmd_pipe_plus.mc_data_offset_reg[5] (\\cmd_pipe_plus.mc_data_offset_reg[5] ),\n .\\cmd_pipe_plus.mc_data_offset_reg[5]_0 (\\cmd_pipe_plus.mc_data_offset_reg[5]_0 ),\n .cnt_pwron_reset_done_r0(cnt_pwron_reset_done_r0),\n .\\complex_row_cnt_ocal_reg[0] (\\complex_row_cnt_ocal_reg[0] ),\n .\\data_offset_1_i1_reg[5] (mux_data_offset_1),\n .\\device_temp_r_reg[11] (\\device_temp_r_reg[11] ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (u_ddr_calib_top_n_405),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (u_ddr_calib_top_n_415),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (u_ddr_calib_top_n_425),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (u_ddr_calib_top_n_449),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 (u_ddr_mc_phy_wrapper_n_1127),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_4 (u_ddr_mc_phy_wrapper_n_104),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\\not_strict_mode.app_rd_data_reg[6] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\\not_strict_mode.app_rd_data_reg[14] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 (\\not_strict_mode.app_rd_data_reg[22] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 (\\not_strict_mode.app_rd_data_reg[29] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\\not_strict_mode.app_rd_data_reg[5] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\\not_strict_mode.app_rd_data_reg[13] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 (\\not_strict_mode.app_rd_data_reg[21] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 (\\not_strict_mode.app_rd_data_reg[28] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\\not_strict_mode.app_rd_data_reg[4] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\\not_strict_mode.app_rd_data_reg[12] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 (\\not_strict_mode.app_rd_data_reg[20] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 (\\not_strict_mode.app_rd_data_reg[27] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\\not_strict_mode.app_rd_data_reg[3] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\\not_strict_mode.app_rd_data_reg[11] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 (\\not_strict_mode.app_rd_data_reg[19] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 (\\not_strict_mode.app_rd_data_reg[26] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\\not_strict_mode.app_rd_data_reg[2] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\\not_strict_mode.app_rd_data_reg[10] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 (\\not_strict_mode.app_rd_data_reg[18] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 (\\not_strict_mode.app_rd_data_reg[25] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\\not_strict_mode.app_rd_data_reg[1] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\\not_strict_mode.app_rd_data_reg[9] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 (\\not_strict_mode.app_rd_data_reg[17] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 (\\not_strict_mode.app_rd_data_reg[24] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (\\not_strict_mode.app_rd_data_reg[0] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (\\not_strict_mode.app_rd_data_reg[8] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 (\\not_strict_mode.app_rd_data_reg[16] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 (\\not_strict_mode.app_rd_data_reg[30] ),\n .dqs_po_en_stg2_f_reg(dqs_po_en_stg2_f_reg),\n .\\en_cnt_div4.enable_wrlvl_cnt_reg[3] (\\en_cnt_div4.enable_wrlvl_cnt_reg[3] ),\n .fine_adjust_reg(fine_adjust_reg),\n .fine_delay_mod({fine_delay_mod[26],fine_delay_mod[23],fine_delay_mod[20],fine_delay_mod[17],fine_delay_mod[14],fine_delay_mod[11],fine_delay_mod[8],fine_delay_mod[5],fine_delay_mod[2]}),\n .\\fine_delay_mod_reg[20] (u_ddr_calib_top_n_845),\n .\\fine_delay_mod_reg[26] (u_ddr_calib_top_n_859),\n .\\fine_delay_mod_reg[5] (u_ddr_calib_top_n_844),\n .\\fine_delay_r_reg[26] ({\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [26],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [23],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [20],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [17],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [14],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [11],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [8],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [5]}),\n .\\fine_delay_r_reg[26]_0 ({\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [26],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [23],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [20],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [17],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [14],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [11],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [8],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [5]}),\n .\\fine_delay_r_reg[26]_1 ({\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [26],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [23],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [20],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [17],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [14],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [11],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [8],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [5]}),\n .\\fine_delay_r_reg[2] (u_ddr_calib_top_n_448),\n .\\fine_delay_r_reg[5] (u_ddr_calib_top_n_404),\n .\\fine_delay_r_reg[5]_0 (u_ddr_calib_top_n_414),\n .\\fine_delay_r_reg[5]_1 (u_ddr_calib_top_n_424),\n .fine_delay_sel_r(fine_delay_sel_r),\n .fine_delay_sel_r_reg(u_ddr_calib_top_n_50),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 (byte_sel_cnt),\n .\\genblk9[1].fine_delay_incdec_pb_reg[1] (u_ddr_calib_top_n_860),\n .\\genblk9[2].fine_delay_incdec_pb_reg[2] (u_ddr_calib_top_n_861),\n .\\genblk9[3].fine_delay_incdec_pb_reg[3] (u_ddr_calib_top_n_862),\n .\\genblk9[5].fine_delay_incdec_pb_reg[5] (u_ddr_calib_top_n_863),\n .\\genblk9[6].fine_delay_incdec_pb_reg[6] (u_ddr_calib_top_n_864),\n .\\genblk9[7].fine_delay_incdec_pb_reg[7] (u_ddr_calib_top_n_865),\n .idelay_inc(idelay_inc),\n .idelay_ld_rst(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst ),\n .idelay_ld_rst_3(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/idelay_ld_rst ),\n .idelay_ld_rst_4(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst ),\n .idelay_ld_rst_5(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/idelay_ld_rst ),\n .\\idelay_tap_cnt_r_reg[0][3][0] (po_stg2_wrcal_cnt),\n .ififo_rst_reg(u_ddr_calib_top_n_409),\n .ififo_rst_reg_0(u_ddr_calib_top_n_419),\n .ififo_rst_reg_1(u_ddr_calib_top_n_429),\n .ififo_rst_reg_2(u_ddr_calib_top_n_453),\n .in0({u_ddr_mc_phy_wrapper_n_43,u_ddr_mc_phy_wrapper_n_44,u_ddr_mc_phy_wrapper_n_45,u_ddr_mc_phy_wrapper_n_46}),\n .init_calib_complete_r_reg(init_calib_complete_r_reg),\n .maint_prescaler_r1(maint_prescaler_r1),\n .\\mcGo_r_reg[15] (\\calib_seq_reg[0] ),\n .mc_cas_n(mc_cas_n),\n .mc_cke(mc_cke),\n .mc_cmd(mc_cmd),\n .mc_cs_n(mc_cs_n),\n .mc_odt(mc_odt),\n .mc_ras_n(mc_ras_n),\n .mc_we_n(mc_we_n),\n .mc_wrdata_en(mc_wrdata_en),\n .mem_out({mem_out[10:8],mem_out[2:0]}),\n .\\mmcm_current_reg[0] (\\mmcm_current_reg[0] ),\n .\\mmcm_init_trail_reg[0] (\\mmcm_init_trail_reg[0] ),\n .mux_cmd_wren(mux_cmd_wren),\n .mux_reset_n(mux_reset_n),\n .mux_wrdata_en(mux_wrdata_en),\n .my_empty(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ),\n .my_empty_6(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ),\n .my_empty_7(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ),\n .my_empty_8(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ),\n .\\my_empty_reg[1] (u_ddr_mc_phy_wrapper_n_61),\n .\\my_empty_reg[1]_0 (u_ddr_mc_phy_wrapper_n_60),\n .\\my_empty_reg[1]_1 (u_ddr_mc_phy_wrapper_n_63),\n .\\my_empty_reg[1]_2 (u_ddr_mc_phy_wrapper_n_102),\n .\\my_empty_reg[1]_3 (u_ddr_mc_phy_wrapper_n_67),\n .\\my_empty_reg[1]_4 (u_ddr_mc_phy_wrapper_n_66),\n .\\my_empty_reg[1]_5 (u_ddr_mc_phy_wrapper_n_65),\n .\\my_empty_reg[1]_6 (u_ddr_mc_phy_wrapper_n_64),\n .\\my_empty_reg[7] (u_ddr_calib_top_n_37),\n .\\my_empty_reg[7]_0 (\\my_empty_reg[7] ),\n .\\my_empty_reg[7]_1 ({mux_wrdata_mask[28],mux_wrdata_mask[24],mux_wrdata_mask[20],mux_wrdata_mask[16],mux_wrdata_mask[12],mux_wrdata_mask[8],mux_wrdata_mask[4],mux_wrdata_mask[0],mux_wrdata[224],mux_wrdata[192],mux_wrdata[160],mux_wrdata[128],mux_wrdata[96],mux_wrdata[64],mux_wrdata[32],mux_wrdata[0],mux_wrdata[225],mux_wrdata[193],mux_wrdata[161],mux_wrdata[129],mux_wrdata[97],mux_wrdata[65],mux_wrdata[33],mux_wrdata[1],mux_wrdata[226],mux_wrdata[194],mux_wrdata[162],mux_wrdata[130],mux_wrdata[98],mux_wrdata[66],mux_wrdata[34],mux_wrdata[2],mux_wrdata[227],mux_wrdata[195],mux_wrdata[163],mux_wrdata[131],mux_wrdata[99],mux_wrdata[67],mux_wrdata[35],mux_wrdata[3],mux_wrdata[228],mux_wrdata[196],mux_wrdata[164],mux_wrdata[132],mux_wrdata[100],mux_wrdata[68],mux_wrdata[36],mux_wrdata[4],mux_wrdata[229],mux_wrdata[197],mux_wrdata[165],mux_wrdata[133],mux_wrdata[101],mux_wrdata[69],mux_wrdata[37],mux_wrdata[5],mux_wrdata[230],mux_wrdata[198],mux_wrdata[166],mux_wrdata[134],mux_wrdata[102],mux_wrdata[70],mux_wrdata[38],mux_wrdata[6],mux_wrdata[231],mux_wrdata[199],mux_wrdata[167],mux_wrdata[135],mux_wrdata[103],mux_wrdata[71],mux_wrdata[39],mux_wrdata[7]}),\n .\\my_empty_reg[7]_10 (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ),\n .\\my_empty_reg[7]_11 (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ),\n .\\my_empty_reg[7]_12 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ),\n .\\my_empty_reg[7]_13 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ),\n .\\my_empty_reg[7]_14 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ),\n .\\my_empty_reg[7]_15 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ),\n .\\my_empty_reg[7]_16 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ),\n .\\my_empty_reg[7]_17 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ),\n .\\my_empty_reg[7]_18 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ),\n .\\my_empty_reg[7]_19 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 ),\n .\\my_empty_reg[7]_2 ({mux_wrdata_mask[29],mux_wrdata_mask[25],mux_wrdata_mask[21],mux_wrdata_mask[17],mux_wrdata_mask[13],mux_wrdata_mask[9],mux_wrdata_mask[5],mux_wrdata_mask[1],mux_wrdata[232],mux_wrdata[200],mux_wrdata[168],mux_wrdata[136],mux_wrdata[104],mux_wrdata[72],mux_wrdata[40],mux_wrdata[8],mux_wrdata[233],mux_wrdata[201],mux_wrdata[169],mux_wrdata[137],mux_wrdata[105],mux_wrdata[73],mux_wrdata[41],mux_wrdata[9],mux_wrdata[234],mux_wrdata[202],mux_wrdata[170],mux_wrdata[138],mux_wrdata[106],mux_wrdata[74],mux_wrdata[42],mux_wrdata[10],mux_wrdata[235],mux_wrdata[203],mux_wrdata[171],mux_wrdata[139],mux_wrdata[107],mux_wrdata[75],mux_wrdata[43],mux_wrdata[11],mux_wrdata[236],mux_wrdata[204],mux_wrdata[172],mux_wrdata[140],mux_wrdata[108],mux_wrdata[76],mux_wrdata[44],mux_wrdata[12],mux_wrdata[237],mux_wrdata[205],mux_wrdata[173],mux_wrdata[141],mux_wrdata[109],mux_wrdata[77],mux_wrdata[45],mux_wrdata[13],mux_wrdata[238],mux_wrdata[206],mux_wrdata[174],mux_wrdata[142],mux_wrdata[110],mux_wrdata[78],mux_wrdata[46],mux_wrdata[14],mux_wrdata[239],mux_wrdata[207],mux_wrdata[175],mux_wrdata[143],mux_wrdata[111],mux_wrdata[79],mux_wrdata[47],mux_wrdata[15]}),\n .\\my_empty_reg[7]_20 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ),\n .\\my_empty_reg[7]_21 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ),\n .\\my_empty_reg[7]_22 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ),\n .\\my_empty_reg[7]_23 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ),\n .\\my_empty_reg[7]_24 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ),\n .\\my_empty_reg[7]_25 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ),\n .\\my_empty_reg[7]_26 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ),\n .\\my_empty_reg[7]_27 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1 ),\n .\\my_empty_reg[7]_28 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8 ),\n .\\my_empty_reg[7]_29 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7 ),\n .\\my_empty_reg[7]_3 ({mux_wrdata_mask[30],mux_wrdata_mask[26],mux_wrdata_mask[22],mux_wrdata_mask[18],mux_wrdata_mask[14],mux_wrdata_mask[10],mux_wrdata_mask[6],mux_wrdata_mask[2],mux_wrdata[240],mux_wrdata[208],mux_wrdata[176],mux_wrdata[144],mux_wrdata[112],mux_wrdata[80],mux_wrdata[48],mux_wrdata[16],mux_wrdata[241],mux_wrdata[209],mux_wrdata[177],mux_wrdata[145],mux_wrdata[113],mux_wrdata[81],mux_wrdata[49],mux_wrdata[17],mux_wrdata[242],mux_wrdata[210],mux_wrdata[178],mux_wrdata[146],mux_wrdata[114],mux_wrdata[82],mux_wrdata[50],mux_wrdata[18],mux_wrdata[243],mux_wrdata[211],mux_wrdata[179],mux_wrdata[147],mux_wrdata[115],mux_wrdata[83],mux_wrdata[51],mux_wrdata[19],mux_wrdata[244],mux_wrdata[212],mux_wrdata[180],mux_wrdata[148],mux_wrdata[116],mux_wrdata[84],mux_wrdata[52],mux_wrdata[20],mux_wrdata[245],mux_wrdata[213],mux_wrdata[181],mux_wrdata[149],mux_wrdata[117],mux_wrdata[85],mux_wrdata[53],mux_wrdata[21],mux_wrdata[246],mux_wrdata[214],mux_wrdata[182],mux_wrdata[150],mux_wrdata[118],mux_wrdata[86],mux_wrdata[54],mux_wrdata[22],mux_wrdata[247],mux_wrdata[215],mux_wrdata[183],mux_wrdata[151],mux_wrdata[119],mux_wrdata[87],mux_wrdata[55],mux_wrdata[23]}),\n .\\my_empty_reg[7]_30 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ),\n .\\my_empty_reg[7]_31 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ),\n .\\my_empty_reg[7]_32 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ),\n .\\my_empty_reg[7]_33 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3 ),\n .\\my_empty_reg[7]_34 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2 ),\n .\\my_empty_reg[7]_35 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1 ),\n .\\my_empty_reg[7]_36 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7 ),\n .\\my_empty_reg[7]_37 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6 ),\n .\\my_empty_reg[7]_38 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5 ),\n .\\my_empty_reg[7]_39 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4 ),\n .\\my_empty_reg[7]_4 ({mux_wrdata_mask[31],mux_wrdata_mask[27],mux_wrdata_mask[23],mux_wrdata_mask[19],mux_wrdata_mask[15],mux_wrdata_mask[11],mux_wrdata_mask[7],mux_wrdata_mask[3],mux_wrdata[248],mux_wrdata[216],mux_wrdata[184],mux_wrdata[152],mux_wrdata[120],mux_wrdata[88],mux_wrdata[56],mux_wrdata[24],mux_wrdata[249],mux_wrdata[217],mux_wrdata[185],mux_wrdata[153],mux_wrdata[121],mux_wrdata[89],mux_wrdata[57],mux_wrdata[25],mux_wrdata[250],mux_wrdata[218],mux_wrdata[186],mux_wrdata[154],mux_wrdata[122],mux_wrdata[90],mux_wrdata[58],mux_wrdata[26],mux_wrdata[251],mux_wrdata[219],mux_wrdata[187],mux_wrdata[155],mux_wrdata[123],mux_wrdata[91],mux_wrdata[59],mux_wrdata[27],mux_wrdata[252],mux_wrdata[220],mux_wrdata[188],mux_wrdata[156],mux_wrdata[124],mux_wrdata[92],mux_wrdata[60],mux_wrdata[28],mux_wrdata[253],mux_wrdata[221],mux_wrdata[189],mux_wrdata[157],mux_wrdata[125],mux_wrdata[93],mux_wrdata[61],mux_wrdata[29],mux_wrdata[254],mux_wrdata[222],mux_wrdata[190],mux_wrdata[158],mux_wrdata[126],mux_wrdata[94],mux_wrdata[62],mux_wrdata[30],mux_wrdata[255],mux_wrdata[223],mux_wrdata[191],mux_wrdata[159],mux_wrdata[127],mux_wrdata[95],mux_wrdata[63],mux_wrdata[31]}),\n .\\my_empty_reg[7]_40 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3 ),\n .\\my_empty_reg[7]_41 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2 ),\n .\\my_empty_reg[7]_42 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ),\n .\\my_empty_reg[7]_43 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0 ),\n .\\my_empty_reg[7]_5 (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 ),\n .\\my_empty_reg[7]_6 (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ),\n .\\my_empty_reg[7]_7 (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ),\n .\\my_empty_reg[7]_8 (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ),\n .\\my_empty_reg[7]_9 (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ),\n .\\my_full_reg[3] (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ),\n .\\my_full_reg[3]_0 (phy_dout[3:2]),\n .out(u_ddr_calib_top_n_45),\n .p_0_out(\\u_ddr_phy_wrcal/p_0_out ),\n .p_81_in(p_81_in),\n .pd_out(pd_out),\n .\\phy_ctl_wd_i1_reg[24] ({calib_seq,p_1_out[22:17],p_1_out[2:0]}),\n .phy_dout({phy_dout[1:0],mux_address[57],mux_address[42],mux_address[27],mux_address[12],mux_address[56],mux_address[41],mux_address[26],mux_address[11],mux_address[55],mux_address[40],mux_address[25],mux_address[10],mux_address[54],mux_address[39],mux_address[24],mux_address[9],mux_address[53],mux_address[38],mux_address[23],mux_address[8],mux_address[52],mux_address[37],mux_address[22],mux_address[7],mux_address[51],mux_address[36],mux_address[21],mux_address[6],mux_address[50],mux_address[35],mux_address[20],mux_address[5]}),\n .phy_if_reset(phy_if_reset),\n .phy_rddata_en(phy_rddata_en),\n .phy_read_calib(phy_read_calib),\n .phy_write_calib(phy_write_calib),\n .pi_cnt_dec_reg(pi_cnt_dec_reg),\n .\\pi_counter_read_val_reg[5] (\\u_ddr_mc_phy/pi_counter_read_val_w[0]_1 ),\n .\\pi_dqs_found_lanes_r1_reg[0] (u_ddr_calib_top_n_447),\n .\\pi_dqs_found_lanes_r1_reg[0]_0 (u_ddr_calib_top_n_454),\n .\\pi_dqs_found_lanes_r1_reg[0]_1 (u_ddr_calib_top_n_455),\n .\\pi_dqs_found_lanes_r1_reg[0]_2 (u_ddr_calib_top_n_456),\n .\\pi_dqs_found_lanes_r1_reg[1] (u_ddr_calib_top_n_423),\n .\\pi_dqs_found_lanes_r1_reg[1]_0 (u_ddr_calib_top_n_430),\n .\\pi_dqs_found_lanes_r1_reg[1]_1 (u_ddr_calib_top_n_431),\n .\\pi_dqs_found_lanes_r1_reg[1]_2 (u_ddr_calib_top_n_432),\n .\\pi_dqs_found_lanes_r1_reg[1]_3 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_pi_counter_load_val ),\n .\\pi_dqs_found_lanes_r1_reg[2] (u_ddr_calib_top_n_413),\n .\\pi_dqs_found_lanes_r1_reg[2]_0 (u_ddr_calib_top_n_420),\n .\\pi_dqs_found_lanes_r1_reg[2]_1 (u_ddr_calib_top_n_421),\n .\\pi_dqs_found_lanes_r1_reg[2]_2 (u_ddr_calib_top_n_422),\n .\\pi_dqs_found_lanes_r1_reg[2]_3 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_counter_load_val ),\n .\\pi_dqs_found_lanes_r1_reg[3] (u_ddr_calib_top_n_403),\n .\\pi_dqs_found_lanes_r1_reg[3]_0 (u_ddr_calib_top_n_410),\n .\\pi_dqs_found_lanes_r1_reg[3]_1 (u_ddr_calib_top_n_411),\n .\\pi_dqs_found_lanes_r1_reg[3]_2 (u_ddr_calib_top_n_412),\n .\\pi_dqs_found_lanes_r1_reg[3]_3 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_counter_load_val ),\n .pi_en_stg2_f_timing_reg(pi_en_stg2_f_timing_reg),\n .\\pi_rst_stg1_cal_r_reg[0] (\\pi_rst_stg1_cal_r_reg[0] ),\n .po_cnt_dec_reg(po_cnt_dec_reg),\n .\\po_counter_read_val_reg[2] (u_ddr_mc_phy_wrapper_n_106),\n .\\po_counter_read_val_reg[5] ({u_ddr_mc_phy_wrapper_n_107,u_ddr_mc_phy_wrapper_n_108,u_ddr_mc_phy_wrapper_n_109,u_ddr_mc_phy_wrapper_n_110,u_ddr_mc_phy_wrapper_n_111,u_ddr_mc_phy_wrapper_n_112}),\n .\\po_counter_read_val_reg[8] (u_ddr_calib_top_n_385),\n .\\po_counter_read_val_reg[8]_0 (u_ddr_calib_top_n_386),\n .\\po_counter_read_val_reg[8]_1 (u_ddr_calib_top_n_387),\n .\\po_counter_read_val_reg[8]_10 (u_ddr_calib_top_n_396),\n .\\po_counter_read_val_reg[8]_11 (u_ddr_calib_top_n_397),\n .\\po_counter_read_val_reg[8]_12 (u_ddr_calib_top_n_399),\n .\\po_counter_read_val_reg[8]_13 (u_ddr_calib_top_n_400),\n .\\po_counter_read_val_reg[8]_14 (u_ddr_calib_top_n_401),\n .\\po_counter_read_val_reg[8]_15 (u_ddr_calib_top_n_402),\n .\\po_counter_read_val_reg[8]_16 (u_ddr_calib_top_n_406),\n .\\po_counter_read_val_reg[8]_17 (u_ddr_calib_top_n_407),\n .\\po_counter_read_val_reg[8]_18 (u_ddr_calib_top_n_408),\n .\\po_counter_read_val_reg[8]_19 (u_ddr_calib_top_n_416),\n .\\po_counter_read_val_reg[8]_2 (u_ddr_calib_top_n_388),\n .\\po_counter_read_val_reg[8]_20 (u_ddr_calib_top_n_417),\n .\\po_counter_read_val_reg[8]_21 (u_ddr_calib_top_n_418),\n .\\po_counter_read_val_reg[8]_22 (u_ddr_calib_top_n_426),\n .\\po_counter_read_val_reg[8]_23 (u_ddr_calib_top_n_427),\n .\\po_counter_read_val_reg[8]_24 (u_ddr_calib_top_n_428),\n .\\po_counter_read_val_reg[8]_25 (u_ddr_calib_top_n_450),\n .\\po_counter_read_val_reg[8]_26 (u_ddr_calib_top_n_451),\n .\\po_counter_read_val_reg[8]_27 (u_ddr_calib_top_n_452),\n .\\po_counter_read_val_reg[8]_28 (u_ddr_calib_top_n_457),\n .\\po_counter_read_val_reg[8]_29 (u_ddr_calib_top_n_458),\n .\\po_counter_read_val_reg[8]_3 (u_ddr_calib_top_n_389),\n .\\po_counter_read_val_reg[8]_30 ({\\u_ddr_mc_phy/po_counter_read_val_w[1]_2 [8:6],\\u_ddr_mc_phy/po_counter_read_val_w[1]_2 [3],\\u_ddr_mc_phy/po_counter_read_val_w[1]_2 [0]}),\n .\\po_counter_read_val_reg[8]_31 ({\\u_ddr_mc_phy/po_counter_read_val_w[0]_0 [8:6],\\u_ddr_mc_phy/po_counter_read_val_w[0]_0 [3],\\u_ddr_mc_phy/po_counter_read_val_w[0]_0 [0]}),\n .\\po_counter_read_val_reg[8]_4 (u_ddr_calib_top_n_390),\n .\\po_counter_read_val_reg[8]_5 (u_ddr_calib_top_n_391),\n .\\po_counter_read_val_reg[8]_6 (u_ddr_calib_top_n_392),\n .\\po_counter_read_val_reg[8]_7 (u_ddr_calib_top_n_393),\n .\\po_counter_read_val_reg[8]_8 (u_ddr_calib_top_n_394),\n .\\po_counter_read_val_reg[8]_9 (u_ddr_calib_top_n_395),\n .\\po_rdval_cnt_reg[8] ({calib_sel__0,calib_sel}),\n .\\po_stg2_wrcal_cnt_reg[1] (u_ddr_mc_phy_wrapper_n_1152),\n .\\po_stg2_wrcal_cnt_reg[1]_0 (u_ddr_mc_phy_wrapper_n_1156),\n .\\po_stg2_wrcal_cnt_reg[1]_1 (u_ddr_mc_phy_wrapper_n_1171),\n .\\po_stg2_wrcal_cnt_reg[1]_10 (u_ddr_mc_phy_wrapper_n_1136),\n .\\po_stg2_wrcal_cnt_reg[1]_11 (u_ddr_mc_phy_wrapper_n_1137),\n .\\po_stg2_wrcal_cnt_reg[1]_12 (u_ddr_mc_phy_wrapper_n_1138),\n .\\po_stg2_wrcal_cnt_reg[1]_13 (u_ddr_mc_phy_wrapper_n_1139),\n .\\po_stg2_wrcal_cnt_reg[1]_14 (u_ddr_mc_phy_wrapper_n_1140),\n .\\po_stg2_wrcal_cnt_reg[1]_15 (u_ddr_mc_phy_wrapper_n_1141),\n .\\po_stg2_wrcal_cnt_reg[1]_16 (u_ddr_mc_phy_wrapper_n_1142),\n .\\po_stg2_wrcal_cnt_reg[1]_17 (u_ddr_mc_phy_wrapper_n_1143),\n .\\po_stg2_wrcal_cnt_reg[1]_18 (u_ddr_mc_phy_wrapper_n_1144),\n .\\po_stg2_wrcal_cnt_reg[1]_19 (u_ddr_mc_phy_wrapper_n_1145),\n .\\po_stg2_wrcal_cnt_reg[1]_2 (u_ddr_mc_phy_wrapper_n_1175),\n .\\po_stg2_wrcal_cnt_reg[1]_20 (u_ddr_mc_phy_wrapper_n_1146),\n .\\po_stg2_wrcal_cnt_reg[1]_21 (u_ddr_mc_phy_wrapper_n_1147),\n .\\po_stg2_wrcal_cnt_reg[1]_22 (u_ddr_mc_phy_wrapper_n_1148),\n .\\po_stg2_wrcal_cnt_reg[1]_23 (u_ddr_mc_phy_wrapper_n_1149),\n .\\po_stg2_wrcal_cnt_reg[1]_24 (u_ddr_mc_phy_wrapper_n_1150),\n .\\po_stg2_wrcal_cnt_reg[1]_25 (u_ddr_mc_phy_wrapper_n_1151),\n .\\po_stg2_wrcal_cnt_reg[1]_26 (u_ddr_mc_phy_wrapper_n_1153),\n .\\po_stg2_wrcal_cnt_reg[1]_27 (u_ddr_mc_phy_wrapper_n_1154),\n .\\po_stg2_wrcal_cnt_reg[1]_28 (u_ddr_mc_phy_wrapper_n_1155),\n .\\po_stg2_wrcal_cnt_reg[1]_29 (u_ddr_mc_phy_wrapper_n_1157),\n .\\po_stg2_wrcal_cnt_reg[1]_3 (u_ddr_mc_phy_wrapper_n_1129),\n .\\po_stg2_wrcal_cnt_reg[1]_30 (u_ddr_mc_phy_wrapper_n_1158),\n .\\po_stg2_wrcal_cnt_reg[1]_31 (u_ddr_mc_phy_wrapper_n_1159),\n .\\po_stg2_wrcal_cnt_reg[1]_32 (u_ddr_mc_phy_wrapper_n_1160),\n .\\po_stg2_wrcal_cnt_reg[1]_33 (u_ddr_mc_phy_wrapper_n_1161),\n .\\po_stg2_wrcal_cnt_reg[1]_34 (u_ddr_mc_phy_wrapper_n_1162),\n .\\po_stg2_wrcal_cnt_reg[1]_35 (u_ddr_mc_phy_wrapper_n_1163),\n .\\po_stg2_wrcal_cnt_reg[1]_36 (u_ddr_mc_phy_wrapper_n_1164),\n .\\po_stg2_wrcal_cnt_reg[1]_37 (u_ddr_mc_phy_wrapper_n_1165),\n .\\po_stg2_wrcal_cnt_reg[1]_38 (u_ddr_mc_phy_wrapper_n_1166),\n .\\po_stg2_wrcal_cnt_reg[1]_39 (u_ddr_mc_phy_wrapper_n_1167),\n .\\po_stg2_wrcal_cnt_reg[1]_4 (u_ddr_mc_phy_wrapper_n_1130),\n .\\po_stg2_wrcal_cnt_reg[1]_40 (u_ddr_mc_phy_wrapper_n_1168),\n .\\po_stg2_wrcal_cnt_reg[1]_41 (u_ddr_mc_phy_wrapper_n_1169),\n .\\po_stg2_wrcal_cnt_reg[1]_42 (u_ddr_mc_phy_wrapper_n_1170),\n .\\po_stg2_wrcal_cnt_reg[1]_43 (u_ddr_mc_phy_wrapper_n_1172),\n .\\po_stg2_wrcal_cnt_reg[1]_44 (u_ddr_mc_phy_wrapper_n_1173),\n .\\po_stg2_wrcal_cnt_reg[1]_45 (u_ddr_mc_phy_wrapper_n_1174),\n .\\po_stg2_wrcal_cnt_reg[1]_46 (u_ddr_mc_phy_wrapper_n_1176),\n .\\po_stg2_wrcal_cnt_reg[1]_47 (u_ddr_mc_phy_wrapper_n_1177),\n .\\po_stg2_wrcal_cnt_reg[1]_48 (u_ddr_mc_phy_wrapper_n_1178),\n .\\po_stg2_wrcal_cnt_reg[1]_49 (u_ddr_mc_phy_wrapper_n_1179),\n .\\po_stg2_wrcal_cnt_reg[1]_5 (u_ddr_mc_phy_wrapper_n_1131),\n .\\po_stg2_wrcal_cnt_reg[1]_50 (u_ddr_mc_phy_wrapper_n_1180),\n .\\po_stg2_wrcal_cnt_reg[1]_51 (u_ddr_mc_phy_wrapper_n_1181),\n .\\po_stg2_wrcal_cnt_reg[1]_52 (u_ddr_mc_phy_wrapper_n_1182),\n .\\po_stg2_wrcal_cnt_reg[1]_53 (u_ddr_mc_phy_wrapper_n_1183),\n .\\po_stg2_wrcal_cnt_reg[1]_54 (u_ddr_mc_phy_wrapper_n_1184),\n .\\po_stg2_wrcal_cnt_reg[1]_55 (u_ddr_mc_phy_wrapper_n_1185),\n .\\po_stg2_wrcal_cnt_reg[1]_56 (u_ddr_mc_phy_wrapper_n_1186),\n .\\po_stg2_wrcal_cnt_reg[1]_57 (u_ddr_mc_phy_wrapper_n_1187),\n .\\po_stg2_wrcal_cnt_reg[1]_58 (u_ddr_mc_phy_wrapper_n_1188),\n .\\po_stg2_wrcal_cnt_reg[1]_59 (u_ddr_mc_phy_wrapper_n_1189),\n .\\po_stg2_wrcal_cnt_reg[1]_6 (u_ddr_mc_phy_wrapper_n_1132),\n .\\po_stg2_wrcal_cnt_reg[1]_60 (u_ddr_mc_phy_wrapper_n_1190),\n .\\po_stg2_wrcal_cnt_reg[1]_61 (u_ddr_mc_phy_wrapper_n_1191),\n .\\po_stg2_wrcal_cnt_reg[1]_7 (u_ddr_mc_phy_wrapper_n_1133),\n .\\po_stg2_wrcal_cnt_reg[1]_8 (u_ddr_mc_phy_wrapper_n_1134),\n .\\po_stg2_wrcal_cnt_reg[1]_9 (u_ddr_mc_phy_wrapper_n_1135),\n .poc_sample_pd(poc_sample_pd),\n .prbs_rdlvl_start_r_reg(u_ddr_calib_top_n_47),\n .psdone(psdone),\n .\\qcntr_r_reg[0] (\\qcntr_r_reg[0] ),\n .\\rd_mux_sel_r_reg[1] (u_ddr_mc_phy_wrapper_n_490),\n .\\rd_mux_sel_r_reg[1]_0 (u_ddr_mc_phy_wrapper_n_482),\n .\\rd_mux_sel_r_reg[1]_1 (u_ddr_mc_phy_wrapper_n_474),\n .\\rd_mux_sel_r_reg[1]_10 (u_ddr_mc_phy_wrapper_n_467),\n .\\rd_mux_sel_r_reg[1]_11 (u_ddr_mc_phy_wrapper_n_459),\n .\\rd_mux_sel_r_reg[1]_12 (u_ddr_mc_phy_wrapper_n_451),\n .\\rd_mux_sel_r_reg[1]_13 (u_ddr_mc_phy_wrapper_n_443),\n .\\rd_mux_sel_r_reg[1]_14 (u_ddr_mc_phy_wrapper_n_435),\n .\\rd_mux_sel_r_reg[1]_15 (u_ddr_mc_phy_wrapper_n_492),\n .\\rd_mux_sel_r_reg[1]_16 (u_ddr_mc_phy_wrapper_n_484),\n .\\rd_mux_sel_r_reg[1]_17 (u_ddr_mc_phy_wrapper_n_476),\n .\\rd_mux_sel_r_reg[1]_18 (u_ddr_mc_phy_wrapper_n_468),\n .\\rd_mux_sel_r_reg[1]_19 (u_ddr_mc_phy_wrapper_n_460),\n .\\rd_mux_sel_r_reg[1]_2 (u_ddr_mc_phy_wrapper_n_466),\n .\\rd_mux_sel_r_reg[1]_20 (u_ddr_mc_phy_wrapper_n_452),\n .\\rd_mux_sel_r_reg[1]_21 (u_ddr_mc_phy_wrapper_n_444),\n .\\rd_mux_sel_r_reg[1]_22 (u_ddr_mc_phy_wrapper_n_436),\n .\\rd_mux_sel_r_reg[1]_23 (u_ddr_mc_phy_wrapper_n_493),\n .\\rd_mux_sel_r_reg[1]_24 (u_ddr_mc_phy_wrapper_n_485),\n .\\rd_mux_sel_r_reg[1]_25 (u_ddr_mc_phy_wrapper_n_477),\n .\\rd_mux_sel_r_reg[1]_26 (u_ddr_mc_phy_wrapper_n_469),\n .\\rd_mux_sel_r_reg[1]_27 (u_ddr_mc_phy_wrapper_n_461),\n .\\rd_mux_sel_r_reg[1]_28 (u_ddr_mc_phy_wrapper_n_453),\n .\\rd_mux_sel_r_reg[1]_29 (u_ddr_mc_phy_wrapper_n_445),\n .\\rd_mux_sel_r_reg[1]_3 (u_ddr_mc_phy_wrapper_n_458),\n .\\rd_mux_sel_r_reg[1]_30 (u_ddr_mc_phy_wrapper_n_437),\n .\\rd_mux_sel_r_reg[1]_31 (u_ddr_mc_phy_wrapper_n_494),\n .\\rd_mux_sel_r_reg[1]_32 (u_ddr_mc_phy_wrapper_n_486),\n .\\rd_mux_sel_r_reg[1]_33 (u_ddr_mc_phy_wrapper_n_478),\n .\\rd_mux_sel_r_reg[1]_34 (u_ddr_mc_phy_wrapper_n_470),\n .\\rd_mux_sel_r_reg[1]_35 (u_ddr_mc_phy_wrapper_n_462),\n .\\rd_mux_sel_r_reg[1]_36 (u_ddr_mc_phy_wrapper_n_454),\n .\\rd_mux_sel_r_reg[1]_37 (u_ddr_mc_phy_wrapper_n_446),\n .\\rd_mux_sel_r_reg[1]_38 (u_ddr_mc_phy_wrapper_n_438),\n .\\rd_mux_sel_r_reg[1]_39 (u_ddr_mc_phy_wrapper_n_495),\n .\\rd_mux_sel_r_reg[1]_4 (u_ddr_mc_phy_wrapper_n_450),\n .\\rd_mux_sel_r_reg[1]_40 (u_ddr_mc_phy_wrapper_n_487),\n .\\rd_mux_sel_r_reg[1]_41 (u_ddr_mc_phy_wrapper_n_479),\n .\\rd_mux_sel_r_reg[1]_42 (u_ddr_mc_phy_wrapper_n_471),\n .\\rd_mux_sel_r_reg[1]_43 (u_ddr_mc_phy_wrapper_n_463),\n .\\rd_mux_sel_r_reg[1]_44 (u_ddr_mc_phy_wrapper_n_455),\n .\\rd_mux_sel_r_reg[1]_45 (u_ddr_mc_phy_wrapper_n_447),\n .\\rd_mux_sel_r_reg[1]_46 (u_ddr_mc_phy_wrapper_n_439),\n .\\rd_mux_sel_r_reg[1]_47 (u_ddr_mc_phy_wrapper_n_496),\n .\\rd_mux_sel_r_reg[1]_48 (u_ddr_mc_phy_wrapper_n_488),\n .\\rd_mux_sel_r_reg[1]_49 (u_ddr_mc_phy_wrapper_n_480),\n .\\rd_mux_sel_r_reg[1]_5 (u_ddr_mc_phy_wrapper_n_442),\n .\\rd_mux_sel_r_reg[1]_50 (u_ddr_mc_phy_wrapper_n_472),\n .\\rd_mux_sel_r_reg[1]_51 (u_ddr_mc_phy_wrapper_n_464),\n .\\rd_mux_sel_r_reg[1]_52 (u_ddr_mc_phy_wrapper_n_456),\n .\\rd_mux_sel_r_reg[1]_53 (u_ddr_mc_phy_wrapper_n_448),\n .\\rd_mux_sel_r_reg[1]_54 (u_ddr_mc_phy_wrapper_n_440),\n .\\rd_mux_sel_r_reg[1]_55 (u_ddr_mc_phy_wrapper_n_497),\n .\\rd_mux_sel_r_reg[1]_56 (u_ddr_mc_phy_wrapper_n_489),\n .\\rd_mux_sel_r_reg[1]_57 (u_ddr_mc_phy_wrapper_n_481),\n .\\rd_mux_sel_r_reg[1]_58 (u_ddr_mc_phy_wrapper_n_473),\n .\\rd_mux_sel_r_reg[1]_59 (u_ddr_mc_phy_wrapper_n_465),\n .\\rd_mux_sel_r_reg[1]_6 (u_ddr_mc_phy_wrapper_n_434),\n .\\rd_mux_sel_r_reg[1]_60 (u_ddr_mc_phy_wrapper_n_457),\n .\\rd_mux_sel_r_reg[1]_61 (u_ddr_mc_phy_wrapper_n_449),\n .\\rd_mux_sel_r_reg[1]_62 (u_ddr_mc_phy_wrapper_n_441),\n .\\rd_mux_sel_r_reg[1]_7 (u_ddr_mc_phy_wrapper_n_491),\n .\\rd_mux_sel_r_reg[1]_8 (u_ddr_mc_phy_wrapper_n_483),\n .\\rd_mux_sel_r_reg[1]_9 (u_ddr_mc_phy_wrapper_n_475),\n .\\rd_ptr_reg[3] ({\\rd_ptr_reg[3] [69:66],\\rd_ptr_reg[3] [61:58],\\rd_ptr_reg[3] [53:34],\\rd_ptr_reg[3] [29:26],\\rd_ptr_reg[3] [20:18],\\rd_ptr_reg[3] [12:10]}),\n .\\rd_ptr_reg[3]_0 ({\\rd_ptr_reg[3]_0 [25:22],\\rd_ptr_reg[3]_0 [17:14],\\rd_ptr_reg[3]_0 [11:8]}),\n .\\rd_ptr_reg[3]_1 ({\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [67:64],\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [59:56],\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [51:48],\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [43:40],\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [35:32],\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [27:24],\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [19:16],\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [11:8]}),\n .\\rd_ptr_reg[3]_2 ({u_ddr_mc_phy_wrapper_n_1033,u_ddr_mc_phy_wrapper_n_1034,u_ddr_mc_phy_wrapper_n_1035,u_ddr_mc_phy_wrapper_n_1036,u_ddr_mc_phy_wrapper_n_1037,u_ddr_mc_phy_wrapper_n_1038,u_ddr_mc_phy_wrapper_n_1039,u_ddr_mc_phy_wrapper_n_1040,u_ddr_mc_phy_wrapper_n_1041,u_ddr_mc_phy_wrapper_n_1042,u_ddr_mc_phy_wrapper_n_1043,u_ddr_mc_phy_wrapper_n_1044,u_ddr_mc_phy_wrapper_n_1045,u_ddr_mc_phy_wrapper_n_1046,u_ddr_mc_phy_wrapper_n_1047,u_ddr_mc_phy_wrapper_n_1048,u_ddr_mc_phy_wrapper_n_1049,u_ddr_mc_phy_wrapper_n_1050,u_ddr_mc_phy_wrapper_n_1051,u_ddr_mc_phy_wrapper_n_1052,u_ddr_mc_phy_wrapper_n_1053,u_ddr_mc_phy_wrapper_n_1054,u_ddr_mc_phy_wrapper_n_1055,u_ddr_mc_phy_wrapper_n_1056,u_ddr_mc_phy_wrapper_n_1057,u_ddr_mc_phy_wrapper_n_1058,u_ddr_mc_phy_wrapper_n_1059,u_ddr_mc_phy_wrapper_n_1060,u_ddr_mc_phy_wrapper_n_1061,u_ddr_mc_phy_wrapper_n_1062,u_ddr_mc_phy_wrapper_n_1063,u_ddr_mc_phy_wrapper_n_1064,u_ddr_mc_phy_wrapper_n_1065,u_ddr_mc_phy_wrapper_n_1066,u_ddr_mc_phy_wrapper_n_1067,u_ddr_mc_phy_wrapper_n_1068,u_ddr_mc_phy_wrapper_n_1069,u_ddr_mc_phy_wrapper_n_1070,u_ddr_mc_phy_wrapper_n_1071,u_ddr_mc_phy_wrapper_n_1072,u_ddr_mc_phy_wrapper_n_1073,u_ddr_mc_phy_wrapper_n_1074,u_ddr_mc_phy_wrapper_n_1075,u_ddr_mc_phy_wrapper_n_1076,u_ddr_mc_phy_wrapper_n_1077,u_ddr_mc_phy_wrapper_n_1078,u_ddr_mc_phy_wrapper_n_1079,u_ddr_mc_phy_wrapper_n_1080,u_ddr_mc_phy_wrapper_n_1081,u_ddr_mc_phy_wrapper_n_1082,u_ddr_mc_phy_wrapper_n_1083,u_ddr_mc_phy_wrapper_n_1084,u_ddr_mc_phy_wrapper_n_1085,u_ddr_mc_phy_wrapper_n_1086,u_ddr_mc_phy_wrapper_n_1087,u_ddr_mc_phy_wrapper_n_1088,u_ddr_mc_phy_wrapper_n_1089,u_ddr_mc_phy_wrapper_n_1090,u_ddr_mc_phy_wrapper_n_1091,u_ddr_mc_phy_wrapper_n_1092,u_ddr_mc_phy_wrapper_n_1093,u_ddr_mc_phy_wrapper_n_1094,u_ddr_mc_phy_wrapper_n_1095,u_ddr_mc_phy_wrapper_n_1096}),\n .\\rd_ptr_reg[3]_3 ({u_ddr_mc_phy_wrapper_n_967,u_ddr_mc_phy_wrapper_n_968,u_ddr_mc_phy_wrapper_n_969,u_ddr_mc_phy_wrapper_n_970,u_ddr_mc_phy_wrapper_n_971,u_ddr_mc_phy_wrapper_n_972,u_ddr_mc_phy_wrapper_n_973,u_ddr_mc_phy_wrapper_n_974,u_ddr_mc_phy_wrapper_n_975,u_ddr_mc_phy_wrapper_n_976,u_ddr_mc_phy_wrapper_n_977,u_ddr_mc_phy_wrapper_n_978,u_ddr_mc_phy_wrapper_n_979,u_ddr_mc_phy_wrapper_n_980,u_ddr_mc_phy_wrapper_n_981,u_ddr_mc_phy_wrapper_n_982,u_ddr_mc_phy_wrapper_n_983,u_ddr_mc_phy_wrapper_n_984,u_ddr_mc_phy_wrapper_n_985,u_ddr_mc_phy_wrapper_n_986,u_ddr_mc_phy_wrapper_n_987,u_ddr_mc_phy_wrapper_n_988,u_ddr_mc_phy_wrapper_n_989,u_ddr_mc_phy_wrapper_n_990,u_ddr_mc_phy_wrapper_n_991,u_ddr_mc_phy_wrapper_n_992,u_ddr_mc_phy_wrapper_n_993,u_ddr_mc_phy_wrapper_n_994,u_ddr_mc_phy_wrapper_n_995,u_ddr_mc_phy_wrapper_n_996,u_ddr_mc_phy_wrapper_n_997,u_ddr_mc_phy_wrapper_n_998,u_ddr_mc_phy_wrapper_n_999,u_ddr_mc_phy_wrapper_n_1000,u_ddr_mc_phy_wrapper_n_1001,u_ddr_mc_phy_wrapper_n_1002,u_ddr_mc_phy_wrapper_n_1003,u_ddr_mc_phy_wrapper_n_1004,u_ddr_mc_phy_wrapper_n_1005,u_ddr_mc_phy_wrapper_n_1006,u_ddr_mc_phy_wrapper_n_1007,u_ddr_mc_phy_wrapper_n_1008,u_ddr_mc_phy_wrapper_n_1009,u_ddr_mc_phy_wrapper_n_1010,u_ddr_mc_phy_wrapper_n_1011,u_ddr_mc_phy_wrapper_n_1012,u_ddr_mc_phy_wrapper_n_1013,u_ddr_mc_phy_wrapper_n_1014,u_ddr_mc_phy_wrapper_n_1015,u_ddr_mc_phy_wrapper_n_1016,u_ddr_mc_phy_wrapper_n_1017,u_ddr_mc_phy_wrapper_n_1018,u_ddr_mc_phy_wrapper_n_1019,u_ddr_mc_phy_wrapper_n_1020,u_ddr_mc_phy_wrapper_n_1021,u_ddr_mc_phy_wrapper_n_1022,u_ddr_mc_phy_wrapper_n_1023,u_ddr_mc_phy_wrapper_n_1024,u_ddr_mc_phy_wrapper_n_1025,u_ddr_mc_phy_wrapper_n_1026,u_ddr_mc_phy_wrapper_n_1027,u_ddr_mc_phy_wrapper_n_1028,u_ddr_mc_phy_wrapper_n_1029,u_ddr_mc_phy_wrapper_n_1030}),\n .\\rd_ptr_reg[3]_4 ({u_ddr_mc_phy_wrapper_n_901,u_ddr_mc_phy_wrapper_n_902,u_ddr_mc_phy_wrapper_n_903,u_ddr_mc_phy_wrapper_n_904,u_ddr_mc_phy_wrapper_n_905,u_ddr_mc_phy_wrapper_n_906,u_ddr_mc_phy_wrapper_n_907,u_ddr_mc_phy_wrapper_n_908,u_ddr_mc_phy_wrapper_n_909,u_ddr_mc_phy_wrapper_n_910,u_ddr_mc_phy_wrapper_n_911,u_ddr_mc_phy_wrapper_n_912,u_ddr_mc_phy_wrapper_n_913,u_ddr_mc_phy_wrapper_n_914,u_ddr_mc_phy_wrapper_n_915,u_ddr_mc_phy_wrapper_n_916,u_ddr_mc_phy_wrapper_n_917,u_ddr_mc_phy_wrapper_n_918,u_ddr_mc_phy_wrapper_n_919,u_ddr_mc_phy_wrapper_n_920,u_ddr_mc_phy_wrapper_n_921,u_ddr_mc_phy_wrapper_n_922,u_ddr_mc_phy_wrapper_n_923,u_ddr_mc_phy_wrapper_n_924,u_ddr_mc_phy_wrapper_n_925,u_ddr_mc_phy_wrapper_n_926,u_ddr_mc_phy_wrapper_n_927,u_ddr_mc_phy_wrapper_n_928,u_ddr_mc_phy_wrapper_n_929,u_ddr_mc_phy_wrapper_n_930,u_ddr_mc_phy_wrapper_n_931,u_ddr_mc_phy_wrapper_n_932,u_ddr_mc_phy_wrapper_n_933,u_ddr_mc_phy_wrapper_n_934,u_ddr_mc_phy_wrapper_n_935,u_ddr_mc_phy_wrapper_n_936,u_ddr_mc_phy_wrapper_n_937,u_ddr_mc_phy_wrapper_n_938,u_ddr_mc_phy_wrapper_n_939,u_ddr_mc_phy_wrapper_n_940,u_ddr_mc_phy_wrapper_n_941,u_ddr_mc_phy_wrapper_n_942,u_ddr_mc_phy_wrapper_n_943,u_ddr_mc_phy_wrapper_n_944,u_ddr_mc_phy_wrapper_n_945,u_ddr_mc_phy_wrapper_n_946,u_ddr_mc_phy_wrapper_n_947,u_ddr_mc_phy_wrapper_n_948,u_ddr_mc_phy_wrapper_n_949,u_ddr_mc_phy_wrapper_n_950,u_ddr_mc_phy_wrapper_n_951,u_ddr_mc_phy_wrapper_n_952,u_ddr_mc_phy_wrapper_n_953,u_ddr_mc_phy_wrapper_n_954,u_ddr_mc_phy_wrapper_n_955,u_ddr_mc_phy_wrapper_n_956,u_ddr_mc_phy_wrapper_n_957,u_ddr_mc_phy_wrapper_n_958,u_ddr_mc_phy_wrapper_n_959,u_ddr_mc_phy_wrapper_n_960,u_ddr_mc_phy_wrapper_n_961,u_ddr_mc_phy_wrapper_n_962,u_ddr_mc_phy_wrapper_n_963,u_ddr_mc_phy_wrapper_n_964}),\n .\\rd_ptr_reg[3]_5 ({u_ddr_mc_phy_wrapper_n_835,u_ddr_mc_phy_wrapper_n_836,u_ddr_mc_phy_wrapper_n_837,u_ddr_mc_phy_wrapper_n_838,u_ddr_mc_phy_wrapper_n_839,u_ddr_mc_phy_wrapper_n_840,u_ddr_mc_phy_wrapper_n_841,u_ddr_mc_phy_wrapper_n_842,u_ddr_mc_phy_wrapper_n_843,u_ddr_mc_phy_wrapper_n_844,u_ddr_mc_phy_wrapper_n_845,u_ddr_mc_phy_wrapper_n_846,u_ddr_mc_phy_wrapper_n_847,u_ddr_mc_phy_wrapper_n_848,u_ddr_mc_phy_wrapper_n_849,u_ddr_mc_phy_wrapper_n_850,u_ddr_mc_phy_wrapper_n_851,u_ddr_mc_phy_wrapper_n_852,u_ddr_mc_phy_wrapper_n_853,u_ddr_mc_phy_wrapper_n_854,u_ddr_mc_phy_wrapper_n_855,u_ddr_mc_phy_wrapper_n_856,u_ddr_mc_phy_wrapper_n_857,u_ddr_mc_phy_wrapper_n_858,u_ddr_mc_phy_wrapper_n_859,u_ddr_mc_phy_wrapper_n_860,u_ddr_mc_phy_wrapper_n_861,u_ddr_mc_phy_wrapper_n_862,u_ddr_mc_phy_wrapper_n_863,u_ddr_mc_phy_wrapper_n_864,u_ddr_mc_phy_wrapper_n_865,u_ddr_mc_phy_wrapper_n_866,u_ddr_mc_phy_wrapper_n_867,u_ddr_mc_phy_wrapper_n_868,u_ddr_mc_phy_wrapper_n_869,u_ddr_mc_phy_wrapper_n_870,u_ddr_mc_phy_wrapper_n_871,u_ddr_mc_phy_wrapper_n_872,u_ddr_mc_phy_wrapper_n_873,u_ddr_mc_phy_wrapper_n_874,u_ddr_mc_phy_wrapper_n_875,u_ddr_mc_phy_wrapper_n_876,u_ddr_mc_phy_wrapper_n_877,u_ddr_mc_phy_wrapper_n_878,u_ddr_mc_phy_wrapper_n_879,u_ddr_mc_phy_wrapper_n_880,u_ddr_mc_phy_wrapper_n_881,u_ddr_mc_phy_wrapper_n_882,u_ddr_mc_phy_wrapper_n_883,u_ddr_mc_phy_wrapper_n_884,u_ddr_mc_phy_wrapper_n_885,u_ddr_mc_phy_wrapper_n_886,u_ddr_mc_phy_wrapper_n_887,u_ddr_mc_phy_wrapper_n_888,u_ddr_mc_phy_wrapper_n_889,u_ddr_mc_phy_wrapper_n_890,u_ddr_mc_phy_wrapper_n_891,u_ddr_mc_phy_wrapper_n_892,u_ddr_mc_phy_wrapper_n_893,u_ddr_mc_phy_wrapper_n_894,u_ddr_mc_phy_wrapper_n_895,u_ddr_mc_phy_wrapper_n_896,u_ddr_mc_phy_wrapper_n_897,u_ddr_mc_phy_wrapper_n_898}),\n .\\rd_ptr_timing_reg[0] (u_ddr_calib_top_n_38),\n .\\rd_ptr_timing_reg[0]_0 (\\rd_ptr_timing_reg[0] ),\n .\\rd_ptr_timing_reg[0]_1 (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ),\n .\\rd_ptr_timing_reg[0]_2 (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ),\n .\\rd_ptr_timing_reg[0]_3 (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ),\n .\\rd_ptr_timing_reg[0]_4 (\\rd_ptr_timing_reg[0]_0 ),\n .\\rdlvl_dqs_tap_cnt_r_reg[0][3][0] ({u_ddr_calib_top_n_837,u_ddr_calib_top_n_838}),\n .\\row_cnt_victim_rotate.complex_row_cnt_reg[4] (\\row_cnt_victim_rotate.complex_row_cnt_reg[4] ),\n .rstdiv0_sync_r1_reg_rep(in0),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10),\n .rstdiv0_sync_r1_reg_rep__11(rstdiv0_sync_r1_reg_rep__11),\n .rstdiv0_sync_r1_reg_rep__12(rstdiv0_sync_r1_reg_rep__12),\n .rstdiv0_sync_r1_reg_rep__13(rstdiv0_sync_r1_reg_rep__13),\n .rstdiv0_sync_r1_reg_rep__14(rstdiv0_sync_r1_reg_rep__14),\n .rstdiv0_sync_r1_reg_rep__16(rstdiv0_sync_r1_reg_rep__16),\n .rstdiv0_sync_r1_reg_rep__17(rstdiv0_sync_r1_reg_rep__17),\n .rstdiv0_sync_r1_reg_rep__18(rstdiv0_sync_r1_reg_rep__18),\n .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),\n .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23),\n .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),\n .rstdiv0_sync_r1_reg_rep__24_0(rstdiv0_sync_r1_reg_rep__24_0),\n .rstdiv0_sync_r1_reg_rep__24_1(rstdiv0_sync_r1_reg_rep__24_1),\n .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25),\n .rstdiv0_sync_r1_reg_rep__26(rstdiv0_sync_r1_reg_rep__26),\n .rstdiv0_sync_r1_reg_rep__26_0(rstdiv0_sync_r1_reg_rep__26_0),\n .rstdiv0_sync_r1_reg_rep__26_1(rstdiv0_sync_r1_reg_rep__26_1),\n .rstdiv0_sync_r1_reg_rep__26_2(rstdiv0_sync_r1_reg_rep__26_2),\n .rstdiv0_sync_r1_reg_rep__4(rstdiv0_sync_r1_reg_rep__4),\n .rstdiv0_sync_r1_reg_rep__5(rstdiv0_sync_r1_reg_rep__5),\n .rstdiv0_sync_r1_reg_rep__6(rstdiv0_sync_r1_reg_rep__6),\n .rstdiv0_sync_r1_reg_rep__7(rstdiv0_sync_r1_reg_rep__7),\n .rstdiv0_sync_r1_reg_rep__8(rstdiv0_sync_r1_reg_rep__8),\n .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9),\n .samp_edge_cnt0_en_r(samp_edge_cnt0_en_r),\n .samp_edge_cnt0_en_r_reg(samp_edge_cnt0_en_r_reg),\n .\\samps_r_reg[9] (\\samps_r_reg[9] ),\n .sent_col(sent_col),\n .\\sm_r_reg[0] (\\sm_r_reg[0] ),\n .\\sm_r_reg[0]_0 (\\sm_r_reg[0]_0 ),\n .\\stg2_tap_cnt_reg[0] (\\stg2_tap_cnt_reg[0] ),\n .stg3_dec2init_val_r_reg(stg3_dec2init_val_r_reg),\n .stg3_inc2init_val_r_reg(stg3_inc2init_val_r_reg),\n .\\stg3_r_reg[0] (\\stg3_r_reg[0] ),\n .tempmon_sample_en(tempmon_sample_en),\n .\\zero2fuzz_r_reg[0] (D));\n ddr3_if_mig_7series_v4_0_ddr_mc_phy_wrapper u_ddr_mc_phy_wrapper\n (.A(\\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl/A ),\n .CLK(CLK),\n .CLKB0(CLKB0),\n .CLKB0_7(CLKB0_7),\n .CLKB0_8(CLKB0_8),\n .CLKB0_9(CLKB0_9),\n .COUNTERLOADVAL({u_ddr_calib_top_n_441,u_ddr_calib_top_n_442,u_ddr_calib_top_n_443,u_ddr_calib_top_n_444,u_ddr_calib_top_n_445,u_ddr_calib_top_n_446}),\n .D({calib_seq,p_1_out[22:17],p_1_out[2:0]}),\n .D0(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0 ),\n .D1(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ),\n .D2(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ),\n .D3(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ),\n .D4(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ),\n .D5(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ),\n .D6(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ),\n .D7(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ),\n .D8(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ),\n .D9(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9 ),\n .DOA(DOA),\n .DOB(DOB),\n .DOC(DOC),\n .D_po_coarse_enable110_out(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_coarse_enable110_out ),\n .D_po_counter_read_en122_out(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_counter_read_en122_out ),\n .D_po_fine_enable107_out(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_enable107_out ),\n .D_po_fine_inc113_out(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_fine_inc113_out ),\n .D_po_sel_fine_oclk_delay125_out(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/D_po_sel_fine_oclk_delay125_out ),\n .E(u_ddr_calib_top_n_448),\n .LD0(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0 ),\n .LD0_3(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/LD0 ),\n .LD0_4(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0 ),\n .LD0_5(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/LD0 ),\n .Q(Q[287:256]),\n .RST0(RST0),\n .SR(SR),\n .\\byte_r_reg[0] (u_ddr_mc_phy_wrapper_n_106),\n .\\byte_r_reg[0]_0 (u_ddr_calib_top_n_809),\n .\\byte_r_reg[1] (u_ddr_calib_top_n_810),\n .\\calib_sel_reg[0] (u_ddr_calib_top_n_390),\n .\\calib_sel_reg[0]_0 (u_ddr_calib_top_n_395),\n .\\calib_sel_reg[0]_1 (u_ddr_calib_top_n_396),\n .\\calib_sel_reg[0]_2 (u_ddr_calib_top_n_397),\n .\\calib_sel_reg[0]_3 (u_ddr_calib_top_n_447),\n .\\calib_sel_reg[0]_4 (u_ddr_calib_top_n_423),\n .\\calib_sel_reg[0]_5 (u_ddr_calib_top_n_403),\n .\\calib_sel_reg[0]_6 ({\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [26],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [23],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [20],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [17],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [14],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [11],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [8],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_fine_delay [5]}),\n .\\calib_sel_reg[0]_7 ({\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [26],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [23],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [20],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [17],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [14],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [11],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [8],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_fine_delay [5]}),\n .\\calib_sel_reg[1] (u_ddr_calib_top_n_386),\n .\\calib_sel_reg[1]_0 (u_ddr_calib_top_n_387),\n .\\calib_sel_reg[1]_1 (u_ddr_calib_top_n_388),\n .\\calib_sel_reg[1]_2 (u_ddr_calib_top_n_389),\n .\\calib_sel_reg[1]_3 (u_ddr_calib_top_n_391),\n .\\calib_sel_reg[1]_4 (u_ddr_calib_top_n_392),\n .\\calib_sel_reg[1]_5 (u_ddr_calib_top_n_393),\n .\\calib_sel_reg[1]_6 (u_ddr_calib_top_n_394),\n .\\calib_sel_reg[1]_7 (u_ddr_calib_top_n_413),\n .\\calib_sel_reg[1]_8 ({\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [26],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [23],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [20],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [17],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [14],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [11],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [8],\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_fine_delay [5]}),\n .\\calib_sel_reg[3] ({calib_sel__0,calib_sel}),\n .\\calib_seq_reg[0] (\\calib_seq_reg[0] ),\n .\\calib_zero_inputs_reg[0] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_pi_counter_load_val ),\n .\\calib_zero_inputs_reg[0]_0 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_counter_load_val ),\n .\\calib_zero_inputs_reg[0]_1 (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_counter_load_val ),\n .ck_po_stg2_f_en_reg(u_ddr_calib_top_n_451),\n .ck_po_stg2_f_en_reg_0(u_ddr_calib_top_n_427),\n .ck_po_stg2_f_en_reg_1(u_ddr_calib_top_n_417),\n .ck_po_stg2_f_en_reg_2(u_ddr_calib_top_n_407),\n .ck_po_stg2_f_indec_reg(u_ddr_calib_top_n_450),\n .ck_po_stg2_f_indec_reg_0(u_ddr_calib_top_n_426),\n .ck_po_stg2_f_indec_reg_1(u_ddr_calib_top_n_416),\n .ck_po_stg2_f_indec_reg_2(u_ddr_calib_top_n_406),\n .\\cmd_pipe_plus.mc_address_reg[43] ({\\cmd_pipe_plus.mc_address_reg[44] [36],\\cmd_pipe_plus.mc_address_reg[44] [13]}),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[5] (mux_data_offset_1),\n .\\data_bytes_r_reg[63] ({\\oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_data/data_bytes_r0 ,\\oclk_calib.u_ddr_phy_oclkdelay_cal/u_ocd_data/data_bytes_ns }),\n .ddr3_addr(ddr3_addr),\n .ddr3_ba(ddr3_ba),\n .ddr3_cas_n(ddr3_cas_n),\n .ddr3_cke(ddr3_cke),\n .ddr3_cs_n(ddr3_cs_n),\n .ddr3_dm(ddr3_dm),\n .ddr3_dq(ddr3_dq),\n .ddr3_dqs_n(ddr3_dqs_n),\n .ddr3_dqs_p(ddr3_dqs_p),\n .ddr3_odt(ddr3_odt),\n .ddr3_ras_n(ddr3_ras_n),\n .ddr3_reset_n(ddr3_reset_n),\n .ddr3_we_n(ddr3_we_n),\n .ddr_ck_out(ddr_ck_out),\n .delay_done_r4_reg(u_ddr_calib_top_n_400),\n .delay_done_r4_reg_0(u_ddr_calib_top_n_401),\n .delay_done_r4_reg_1(u_ddr_calib_top_n_399),\n .delay_done_r4_reg_2(u_ddr_calib_top_n_402),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ),\n .fine_delay_mod({fine_delay_mod[26],fine_delay_mod[23],fine_delay_mod[20],fine_delay_mod[17],fine_delay_mod[14],fine_delay_mod[11],fine_delay_mod[8],fine_delay_mod[5],fine_delay_mod[2]}),\n .\\fine_delay_mod_reg[23]_0 ({u_ddr_calib_top_n_433,u_ddr_calib_top_n_434,u_ddr_calib_top_n_435,u_ddr_calib_top_n_436,u_ddr_calib_top_n_437,u_ddr_calib_top_n_438,u_ddr_calib_top_n_439,\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_fine_delay }),\n .\\fine_delay_mod_reg[26]_0 (u_ddr_mc_phy_wrapper_n_30),\n .fine_delay_sel_r(fine_delay_sel_r),\n .fine_delay_sel_reg(u_ddr_calib_top_n_50),\n .freq_refclk(freq_refclk),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[0] (u_ddr_calib_top_n_882),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 (u_ddr_calib_top_n_881),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[0]_1 (u_ddr_calib_top_n_880),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[0]_2 (u_ddr_calib_top_n_883),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[0]_3 (u_ddr_calib_top_n_885),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[0]_4 (u_ddr_calib_top_n_884),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[1] (byte_sel_cnt),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[2] (u_ddr_calib_top_n_464),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[2]_0 (u_ddr_calib_top_n_461),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[2]_1 (u_ddr_calib_top_n_886),\n .\\gen_byte_sel_div1.byte_sel_cnt_reg[2]_2 (u_ddr_calib_top_n_879),\n .\\gen_byte_sel_div1.calib_in_common_reg (u_ddr_calib_top_n_457),\n .\\gen_byte_sel_div1.calib_in_common_reg_0 (u_ddr_calib_top_n_385),\n .\\gen_byte_sel_div1.calib_in_common_reg_1 (u_ddr_calib_top_n_458),\n .\\gen_byte_sel_div1.calib_in_common_reg_10 (u_ddr_calib_top_n_422),\n .\\gen_byte_sel_div1.calib_in_common_reg_11 (u_ddr_calib_top_n_419),\n .\\gen_byte_sel_div1.calib_in_common_reg_12 (u_ddr_calib_top_n_418),\n .\\gen_byte_sel_div1.calib_in_common_reg_13 (u_ddr_calib_top_n_415),\n .\\gen_byte_sel_div1.calib_in_common_reg_14 (u_ddr_calib_top_n_412),\n .\\gen_byte_sel_div1.calib_in_common_reg_15 (u_ddr_calib_top_n_409),\n .\\gen_byte_sel_div1.calib_in_common_reg_16 (u_ddr_calib_top_n_408),\n .\\gen_byte_sel_div1.calib_in_common_reg_17 (u_ddr_calib_top_n_405),\n .\\gen_byte_sel_div1.calib_in_common_reg_18 (u_ddr_calib_top_n_424),\n .\\gen_byte_sel_div1.calib_in_common_reg_19 (u_ddr_calib_top_n_414),\n .\\gen_byte_sel_div1.calib_in_common_reg_2 (u_ddr_calib_top_n_456),\n .\\gen_byte_sel_div1.calib_in_common_reg_20 (u_ddr_calib_top_n_404),\n .\\gen_byte_sel_div1.calib_in_common_reg_3 (u_ddr_calib_top_n_453),\n .\\gen_byte_sel_div1.calib_in_common_reg_4 (u_ddr_calib_top_n_452),\n .\\gen_byte_sel_div1.calib_in_common_reg_5 (u_ddr_calib_top_n_449),\n .\\gen_byte_sel_div1.calib_in_common_reg_6 (u_ddr_calib_top_n_432),\n .\\gen_byte_sel_div1.calib_in_common_reg_7 (u_ddr_calib_top_n_429),\n .\\gen_byte_sel_div1.calib_in_common_reg_8 (u_ddr_calib_top_n_428),\n .\\gen_byte_sel_div1.calib_in_common_reg_9 (u_ddr_calib_top_n_425),\n .\\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] (u_ddr_mc_phy_wrapper_n_814),\n .\\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (u_ddr_mc_phy_wrapper_n_491),\n .\\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] (u_ddr_mc_phy_wrapper_n_816),\n .\\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (u_ddr_mc_phy_wrapper_n_493),\n .\\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] (u_ddr_mc_phy_wrapper_n_818),\n .\\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (u_ddr_mc_phy_wrapper_n_495),\n .\\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] (u_ddr_mc_phy_wrapper_n_820),\n .\\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (u_ddr_mc_phy_wrapper_n_497),\n .\\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] (u_ddr_mc_phy_wrapper_n_813),\n .\\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (u_ddr_mc_phy_wrapper_n_490),\n .\\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] (u_ddr_mc_phy_wrapper_n_815),\n .\\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (u_ddr_mc_phy_wrapper_n_492),\n .\\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] (u_ddr_mc_phy_wrapper_n_817),\n .\\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (u_ddr_mc_phy_wrapper_n_494),\n .\\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] (u_ddr_mc_phy_wrapper_n_819),\n .\\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (u_ddr_mc_phy_wrapper_n_496),\n .\\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] (u_ddr_mc_phy_wrapper_n_806),\n .\\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (u_ddr_mc_phy_wrapper_n_483),\n .\\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] (u_ddr_mc_phy_wrapper_n_808),\n .\\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (u_ddr_mc_phy_wrapper_n_485),\n .\\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] (u_ddr_mc_phy_wrapper_n_810),\n .\\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (u_ddr_mc_phy_wrapper_n_487),\n .\\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] (u_ddr_mc_phy_wrapper_n_812),\n .\\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (u_ddr_mc_phy_wrapper_n_489),\n .\\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] (u_ddr_mc_phy_wrapper_n_805),\n .\\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (u_ddr_mc_phy_wrapper_n_482),\n .\\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] (u_ddr_mc_phy_wrapper_n_807),\n .\\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (u_ddr_mc_phy_wrapper_n_484),\n .\\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] (u_ddr_mc_phy_wrapper_n_809),\n .\\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (u_ddr_mc_phy_wrapper_n_486),\n .\\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] (u_ddr_mc_phy_wrapper_n_811),\n .\\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (u_ddr_mc_phy_wrapper_n_488),\n .\\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] (u_ddr_mc_phy_wrapper_n_798),\n .\\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (u_ddr_mc_phy_wrapper_n_475),\n .\\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] (u_ddr_mc_phy_wrapper_n_800),\n .\\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (u_ddr_mc_phy_wrapper_n_477),\n .\\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] (u_ddr_mc_phy_wrapper_n_802),\n .\\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (u_ddr_mc_phy_wrapper_n_479),\n .\\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] (u_ddr_mc_phy_wrapper_n_804),\n .\\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (u_ddr_mc_phy_wrapper_n_481),\n .\\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] (u_ddr_mc_phy_wrapper_n_797),\n .\\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (u_ddr_mc_phy_wrapper_n_474),\n .\\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] (u_ddr_mc_phy_wrapper_n_799),\n .\\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (u_ddr_mc_phy_wrapper_n_476),\n .\\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] (u_ddr_mc_phy_wrapper_n_801),\n .\\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (u_ddr_mc_phy_wrapper_n_478),\n .\\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] (u_ddr_mc_phy_wrapper_n_803),\n .\\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (u_ddr_mc_phy_wrapper_n_480),\n .\\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] (u_ddr_mc_phy_wrapper_n_790),\n .\\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (u_ddr_mc_phy_wrapper_n_467),\n .\\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] (u_ddr_mc_phy_wrapper_n_792),\n .\\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (u_ddr_mc_phy_wrapper_n_469),\n .\\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] (u_ddr_mc_phy_wrapper_n_794),\n .\\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (u_ddr_mc_phy_wrapper_n_471),\n .\\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] (u_ddr_mc_phy_wrapper_n_796),\n .\\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (u_ddr_mc_phy_wrapper_n_473),\n .\\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] (u_ddr_mc_phy_wrapper_n_789),\n .\\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (u_ddr_mc_phy_wrapper_n_466),\n .\\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] (u_ddr_mc_phy_wrapper_n_791),\n .\\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (u_ddr_mc_phy_wrapper_n_468),\n .\\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] (u_ddr_mc_phy_wrapper_n_793),\n .\\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (u_ddr_mc_phy_wrapper_n_470),\n .\\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] (u_ddr_mc_phy_wrapper_n_795),\n .\\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (u_ddr_mc_phy_wrapper_n_472),\n .\\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] (u_ddr_mc_phy_wrapper_n_782),\n .\\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (u_ddr_mc_phy_wrapper_n_459),\n .\\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] (u_ddr_mc_phy_wrapper_n_784),\n .\\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (u_ddr_mc_phy_wrapper_n_461),\n .\\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] (u_ddr_mc_phy_wrapper_n_786),\n .\\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (u_ddr_mc_phy_wrapper_n_463),\n .\\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] (u_ddr_mc_phy_wrapper_n_788),\n .\\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (u_ddr_mc_phy_wrapper_n_465),\n .\\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] (u_ddr_mc_phy_wrapper_n_781),\n .\\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (u_ddr_mc_phy_wrapper_n_458),\n .\\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] (u_ddr_mc_phy_wrapper_n_783),\n .\\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (u_ddr_mc_phy_wrapper_n_460),\n .\\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] (u_ddr_mc_phy_wrapper_n_785),\n .\\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (u_ddr_mc_phy_wrapper_n_462),\n .\\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] (u_ddr_mc_phy_wrapper_n_787),\n .\\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (u_ddr_mc_phy_wrapper_n_464),\n .\\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] (u_ddr_mc_phy_wrapper_n_774),\n .\\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (u_ddr_mc_phy_wrapper_n_451),\n .\\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] (u_ddr_mc_phy_wrapper_n_776),\n .\\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (u_ddr_mc_phy_wrapper_n_453),\n .\\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] (u_ddr_mc_phy_wrapper_n_778),\n .\\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (u_ddr_mc_phy_wrapper_n_455),\n .\\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] (u_ddr_mc_phy_wrapper_n_780),\n .\\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (u_ddr_mc_phy_wrapper_n_457),\n .\\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] (u_ddr_mc_phy_wrapper_n_773),\n .\\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (u_ddr_mc_phy_wrapper_n_450),\n .\\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] (u_ddr_mc_phy_wrapper_n_775),\n .\\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (u_ddr_mc_phy_wrapper_n_452),\n .\\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] (u_ddr_mc_phy_wrapper_n_777),\n .\\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (u_ddr_mc_phy_wrapper_n_454),\n .\\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] (u_ddr_mc_phy_wrapper_n_779),\n .\\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (u_ddr_mc_phy_wrapper_n_456),\n .\\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] (u_ddr_mc_phy_wrapper_n_766),\n .\\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (u_ddr_mc_phy_wrapper_n_443),\n .\\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] (u_ddr_mc_phy_wrapper_n_768),\n .\\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (u_ddr_mc_phy_wrapper_n_445),\n .\\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] (u_ddr_mc_phy_wrapper_n_770),\n .\\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (u_ddr_mc_phy_wrapper_n_447),\n .\\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] (u_ddr_mc_phy_wrapper_n_772),\n .\\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (u_ddr_mc_phy_wrapper_n_449),\n .\\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] (u_ddr_mc_phy_wrapper_n_765),\n .\\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (u_ddr_mc_phy_wrapper_n_442),\n .\\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] (u_ddr_mc_phy_wrapper_n_767),\n .\\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (u_ddr_mc_phy_wrapper_n_444),\n .\\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] (u_ddr_mc_phy_wrapper_n_769),\n .\\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (u_ddr_mc_phy_wrapper_n_446),\n .\\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] (u_ddr_mc_phy_wrapper_n_771),\n .\\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (u_ddr_mc_phy_wrapper_n_448),\n .\\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] (u_ddr_mc_phy_wrapper_n_758),\n .\\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (u_ddr_mc_phy_wrapper_n_435),\n .\\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] (u_ddr_mc_phy_wrapper_n_760),\n .\\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (u_ddr_mc_phy_wrapper_n_437),\n .\\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] (u_ddr_mc_phy_wrapper_n_762),\n .\\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (u_ddr_mc_phy_wrapper_n_439),\n .\\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] (u_ddr_mc_phy_wrapper_n_764),\n .\\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (u_ddr_mc_phy_wrapper_n_441),\n .\\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] (u_ddr_mc_phy_wrapper_n_757),\n .\\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (u_ddr_mc_phy_wrapper_n_434),\n .\\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] (u_ddr_mc_phy_wrapper_n_759),\n .\\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (u_ddr_mc_phy_wrapper_n_436),\n .\\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] (u_ddr_mc_phy_wrapper_n_761),\n .\\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (u_ddr_mc_phy_wrapper_n_438),\n .\\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] (u_ddr_mc_phy_wrapper_n_763),\n .\\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (u_ddr_mc_phy_wrapper_n_440),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (u_ddr_mc_phy_wrapper_n_1144),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (u_ddr_mc_phy_wrapper_n_1184),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (u_ddr_mc_phy_wrapper_n_1160),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (u_ddr_mc_phy_wrapper_n_1136),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (u_ddr_mc_phy_wrapper_n_1176),\n .\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (u_ddr_mc_phy_wrapper_n_1168),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (u_ddr_mc_phy_wrapper_n_1145),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (u_ddr_mc_phy_wrapper_n_1185),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (u_ddr_mc_phy_wrapper_n_1161),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (u_ddr_mc_phy_wrapper_n_1137),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (u_ddr_mc_phy_wrapper_n_1177),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (u_ddr_mc_phy_wrapper_n_1129),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (u_ddr_mc_phy_wrapper_n_1153),\n .\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (u_ddr_mc_phy_wrapper_n_1169),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (u_ddr_mc_phy_wrapper_n_1146),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (u_ddr_mc_phy_wrapper_n_1186),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (u_ddr_mc_phy_wrapper_n_1162),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (u_ddr_mc_phy_wrapper_n_1138),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (u_ddr_mc_phy_wrapper_n_1178),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (u_ddr_mc_phy_wrapper_n_1130),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (u_ddr_mc_phy_wrapper_n_1154),\n .\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (u_ddr_mc_phy_wrapper_n_1170),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (u_ddr_mc_phy_wrapper_n_1147),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (u_ddr_mc_phy_wrapper_n_1187),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (u_ddr_mc_phy_wrapper_n_1163),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (u_ddr_mc_phy_wrapper_n_1139),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (u_ddr_mc_phy_wrapper_n_1179),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (u_ddr_mc_phy_wrapper_n_1131),\n .\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (u_ddr_mc_phy_wrapper_n_1155),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (u_ddr_mc_phy_wrapper_n_1148),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (u_ddr_mc_phy_wrapper_n_1188),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (u_ddr_mc_phy_wrapper_n_1164),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (u_ddr_mc_phy_wrapper_n_1140),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (u_ddr_mc_phy_wrapper_n_1180),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (u_ddr_mc_phy_wrapper_n_1132),\n .\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (u_ddr_mc_phy_wrapper_n_1172),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (u_ddr_mc_phy_wrapper_n_1149),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (u_ddr_mc_phy_wrapper_n_1189),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (u_ddr_mc_phy_wrapper_n_1165),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (u_ddr_mc_phy_wrapper_n_1141),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (u_ddr_mc_phy_wrapper_n_1181),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (u_ddr_mc_phy_wrapper_n_1133),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (u_ddr_mc_phy_wrapper_n_1157),\n .\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (u_ddr_mc_phy_wrapper_n_1173),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (u_ddr_mc_phy_wrapper_n_1150),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (u_ddr_mc_phy_wrapper_n_1190),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (u_ddr_mc_phy_wrapper_n_1166),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (u_ddr_mc_phy_wrapper_n_1142),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (u_ddr_mc_phy_wrapper_n_1182),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (u_ddr_mc_phy_wrapper_n_1134),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (u_ddr_mc_phy_wrapper_n_1158),\n .\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (u_ddr_mc_phy_wrapper_n_1174),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (u_ddr_mc_phy_wrapper_n_1151),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (u_ddr_mc_phy_wrapper_n_1191),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (u_ddr_mc_phy_wrapper_n_1167),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (u_ddr_mc_phy_wrapper_n_1143),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (u_ddr_mc_phy_wrapper_n_1183),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (u_ddr_mc_phy_wrapper_n_1135),\n .\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (u_ddr_mc_phy_wrapper_n_1159),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[0] (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[11] (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ),\n .\\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ),\n .\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ),\n .\\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] (\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ),\n .\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] (u_ddr_mc_phy_wrapper_n_1152),\n .\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] (u_ddr_mc_phy_wrapper_n_1171),\n .\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] (u_ddr_mc_phy_wrapper_n_1156),\n .\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] (u_ddr_mc_phy_wrapper_n_1175),\n .\\genblk9[0].fine_delay_incdec_pb_reg[0] (u_ddr_calib_top_n_859),\n .\\genblk9[1].fine_delay_incdec_pb_reg[1] (u_ddr_calib_top_n_860),\n .\\genblk9[2].fine_delay_incdec_pb_reg[2] (u_ddr_calib_top_n_861),\n .\\genblk9[3].fine_delay_incdec_pb_reg[3] (u_ddr_calib_top_n_862),\n .\\genblk9[4].fine_delay_incdec_pb_reg[4] (u_ddr_calib_top_n_844),\n .\\genblk9[4].fine_delay_incdec_pb_reg[4]_0 (u_ddr_calib_top_n_845),\n .\\genblk9[5].fine_delay_incdec_pb_reg[5] (u_ddr_calib_top_n_863),\n .\\genblk9[6].fine_delay_incdec_pb_reg[6] (u_ddr_calib_top_n_864),\n .\\genblk9[7].fine_delay_incdec_pb_reg[7] (u_ddr_calib_top_n_865),\n .idelay_inc(idelay_inc),\n .idelay_ld_rst(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst ),\n .idelay_ld_rst_0(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/idelay_ld_rst ),\n .idelay_ld_rst_1(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst ),\n .idelay_ld_rst_2(\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/idelay_ld_rst ),\n .idle(idle),\n .in0(in0),\n .init_calib_complete_reg_rep(u_ddr_calib_top_n_37),\n .init_calib_complete_reg_rep__5(u_ddr_calib_top_n_38),\n .init_calib_complete_reg_rep__6(\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ),\n .init_calib_complete_reg_rep__6_0(app_zq_r_reg),\n .mc_cas_n(mc_cas_n[1]),\n .mem_out({mem_out[17:11],mem_out[7:3]}),\n .mem_refclk(mem_refclk),\n .mmcm_locked(mmcm_locked),\n .mmcm_ps_clk(mmcm_ps_clk),\n .mux_cmd_wren(mux_cmd_wren),\n .mux_rd_valid_r_reg(u_ddr_mc_phy_wrapper_n_104),\n .mux_reset_n(mux_reset_n),\n .mux_wrdata(mux_wrdata),\n .mux_wrdata_en(mux_wrdata_en),\n .mux_wrdata_mask(mux_wrdata_mask),\n .\\my_empty_reg[1] (u_ddr_mc_phy_wrapper_n_60),\n .\\my_empty_reg[1]_0 (u_ddr_mc_phy_wrapper_n_61),\n .\\my_empty_reg[1]_1 (u_ddr_mc_phy_wrapper_n_63),\n .\\my_empty_reg[1]_2 (u_ddr_mc_phy_wrapper_n_64),\n .\\my_empty_reg[1]_3 (u_ddr_mc_phy_wrapper_n_65),\n .\\my_empty_reg[1]_4 (u_ddr_mc_phy_wrapper_n_66),\n .\\my_empty_reg[1]_5 (u_ddr_mc_phy_wrapper_n_67),\n .\\my_empty_reg[1]_6 (u_ddr_mc_phy_wrapper_n_102),\n .\\my_empty_reg[7] ({\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [67:64],\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [59:56],\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [51:48],\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [43:40],\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [35:32],\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [27:24],\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [19:16],\\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [11:8]}),\n .\\my_empty_reg[7]_0 ({u_ddr_mc_phy_wrapper_n_835,u_ddr_mc_phy_wrapper_n_836,u_ddr_mc_phy_wrapper_n_837,u_ddr_mc_phy_wrapper_n_838,u_ddr_mc_phy_wrapper_n_839,u_ddr_mc_phy_wrapper_n_840,u_ddr_mc_phy_wrapper_n_841,u_ddr_mc_phy_wrapper_n_842,u_ddr_mc_phy_wrapper_n_843,u_ddr_mc_phy_wrapper_n_844,u_ddr_mc_phy_wrapper_n_845,u_ddr_mc_phy_wrapper_n_846,u_ddr_mc_phy_wrapper_n_847,u_ddr_mc_phy_wrapper_n_848,u_ddr_mc_phy_wrapper_n_849,u_ddr_mc_phy_wrapper_n_850,u_ddr_mc_phy_wrapper_n_851,u_ddr_mc_phy_wrapper_n_852,u_ddr_mc_phy_wrapper_n_853,u_ddr_mc_phy_wrapper_n_854,u_ddr_mc_phy_wrapper_n_855,u_ddr_mc_phy_wrapper_n_856,u_ddr_mc_phy_wrapper_n_857,u_ddr_mc_phy_wrapper_n_858,u_ddr_mc_phy_wrapper_n_859,u_ddr_mc_phy_wrapper_n_860,u_ddr_mc_phy_wrapper_n_861,u_ddr_mc_phy_wrapper_n_862,u_ddr_mc_phy_wrapper_n_863,u_ddr_mc_phy_wrapper_n_864,u_ddr_mc_phy_wrapper_n_865,u_ddr_mc_phy_wrapper_n_866,u_ddr_mc_phy_wrapper_n_867,u_ddr_mc_phy_wrapper_n_868,u_ddr_mc_phy_wrapper_n_869,u_ddr_mc_phy_wrapper_n_870,u_ddr_mc_phy_wrapper_n_871,u_ddr_mc_phy_wrapper_n_872,u_ddr_mc_phy_wrapper_n_873,u_ddr_mc_phy_wrapper_n_874,u_ddr_mc_phy_wrapper_n_875,u_ddr_mc_phy_wrapper_n_876,u_ddr_mc_phy_wrapper_n_877,u_ddr_mc_phy_wrapper_n_878,u_ddr_mc_phy_wrapper_n_879,u_ddr_mc_phy_wrapper_n_880,u_ddr_mc_phy_wrapper_n_881,u_ddr_mc_phy_wrapper_n_882,u_ddr_mc_phy_wrapper_n_883,u_ddr_mc_phy_wrapper_n_884,u_ddr_mc_phy_wrapper_n_885,u_ddr_mc_phy_wrapper_n_886,u_ddr_mc_phy_wrapper_n_887,u_ddr_mc_phy_wrapper_n_888,u_ddr_mc_phy_wrapper_n_889,u_ddr_mc_phy_wrapper_n_890,u_ddr_mc_phy_wrapper_n_891,u_ddr_mc_phy_wrapper_n_892,u_ddr_mc_phy_wrapper_n_893,u_ddr_mc_phy_wrapper_n_894,u_ddr_mc_phy_wrapper_n_895,u_ddr_mc_phy_wrapper_n_896,u_ddr_mc_phy_wrapper_n_897,u_ddr_mc_phy_wrapper_n_898}),\n .\\my_empty_reg[7]_1 ({u_ddr_mc_phy_wrapper_n_901,u_ddr_mc_phy_wrapper_n_902,u_ddr_mc_phy_wrapper_n_903,u_ddr_mc_phy_wrapper_n_904,u_ddr_mc_phy_wrapper_n_905,u_ddr_mc_phy_wrapper_n_906,u_ddr_mc_phy_wrapper_n_907,u_ddr_mc_phy_wrapper_n_908,u_ddr_mc_phy_wrapper_n_909,u_ddr_mc_phy_wrapper_n_910,u_ddr_mc_phy_wrapper_n_911,u_ddr_mc_phy_wrapper_n_912,u_ddr_mc_phy_wrapper_n_913,u_ddr_mc_phy_wrapper_n_914,u_ddr_mc_phy_wrapper_n_915,u_ddr_mc_phy_wrapper_n_916,u_ddr_mc_phy_wrapper_n_917,u_ddr_mc_phy_wrapper_n_918,u_ddr_mc_phy_wrapper_n_919,u_ddr_mc_phy_wrapper_n_920,u_ddr_mc_phy_wrapper_n_921,u_ddr_mc_phy_wrapper_n_922,u_ddr_mc_phy_wrapper_n_923,u_ddr_mc_phy_wrapper_n_924,u_ddr_mc_phy_wrapper_n_925,u_ddr_mc_phy_wrapper_n_926,u_ddr_mc_phy_wrapper_n_927,u_ddr_mc_phy_wrapper_n_928,u_ddr_mc_phy_wrapper_n_929,u_ddr_mc_phy_wrapper_n_930,u_ddr_mc_phy_wrapper_n_931,u_ddr_mc_phy_wrapper_n_932,u_ddr_mc_phy_wrapper_n_933,u_ddr_mc_phy_wrapper_n_934,u_ddr_mc_phy_wrapper_n_935,u_ddr_mc_phy_wrapper_n_936,u_ddr_mc_phy_wrapper_n_937,u_ddr_mc_phy_wrapper_n_938,u_ddr_mc_phy_wrapper_n_939,u_ddr_mc_phy_wrapper_n_940,u_ddr_mc_phy_wrapper_n_941,u_ddr_mc_phy_wrapper_n_942,u_ddr_mc_phy_wrapper_n_943,u_ddr_mc_phy_wrapper_n_944,u_ddr_mc_phy_wrapper_n_945,u_ddr_mc_phy_wrapper_n_946,u_ddr_mc_phy_wrapper_n_947,u_ddr_mc_phy_wrapper_n_948,u_ddr_mc_phy_wrapper_n_949,u_ddr_mc_phy_wrapper_n_950,u_ddr_mc_phy_wrapper_n_951,u_ddr_mc_phy_wrapper_n_952,u_ddr_mc_phy_wrapper_n_953,u_ddr_mc_phy_wrapper_n_954,u_ddr_mc_phy_wrapper_n_955,u_ddr_mc_phy_wrapper_n_956,u_ddr_mc_phy_wrapper_n_957,u_ddr_mc_phy_wrapper_n_958,u_ddr_mc_phy_wrapper_n_959,u_ddr_mc_phy_wrapper_n_960,u_ddr_mc_phy_wrapper_n_961,u_ddr_mc_phy_wrapper_n_962,u_ddr_mc_phy_wrapper_n_963,u_ddr_mc_phy_wrapper_n_964}),\n .\\my_empty_reg[7]_2 ({u_ddr_mc_phy_wrapper_n_967,u_ddr_mc_phy_wrapper_n_968,u_ddr_mc_phy_wrapper_n_969,u_ddr_mc_phy_wrapper_n_970,u_ddr_mc_phy_wrapper_n_971,u_ddr_mc_phy_wrapper_n_972,u_ddr_mc_phy_wrapper_n_973,u_ddr_mc_phy_wrapper_n_974,u_ddr_mc_phy_wrapper_n_975,u_ddr_mc_phy_wrapper_n_976,u_ddr_mc_phy_wrapper_n_977,u_ddr_mc_phy_wrapper_n_978,u_ddr_mc_phy_wrapper_n_979,u_ddr_mc_phy_wrapper_n_980,u_ddr_mc_phy_wrapper_n_981,u_ddr_mc_phy_wrapper_n_982,u_ddr_mc_phy_wrapper_n_983,u_ddr_mc_phy_wrapper_n_984,u_ddr_mc_phy_wrapper_n_985,u_ddr_mc_phy_wrapper_n_986,u_ddr_mc_phy_wrapper_n_987,u_ddr_mc_phy_wrapper_n_988,u_ddr_mc_phy_wrapper_n_989,u_ddr_mc_phy_wrapper_n_990,u_ddr_mc_phy_wrapper_n_991,u_ddr_mc_phy_wrapper_n_992,u_ddr_mc_phy_wrapper_n_993,u_ddr_mc_phy_wrapper_n_994,u_ddr_mc_phy_wrapper_n_995,u_ddr_mc_phy_wrapper_n_996,u_ddr_mc_phy_wrapper_n_997,u_ddr_mc_phy_wrapper_n_998,u_ddr_mc_phy_wrapper_n_999,u_ddr_mc_phy_wrapper_n_1000,u_ddr_mc_phy_wrapper_n_1001,u_ddr_mc_phy_wrapper_n_1002,u_ddr_mc_phy_wrapper_n_1003,u_ddr_mc_phy_wrapper_n_1004,u_ddr_mc_phy_wrapper_n_1005,u_ddr_mc_phy_wrapper_n_1006,u_ddr_mc_phy_wrapper_n_1007,u_ddr_mc_phy_wrapper_n_1008,u_ddr_mc_phy_wrapper_n_1009,u_ddr_mc_phy_wrapper_n_1010,u_ddr_mc_phy_wrapper_n_1011,u_ddr_mc_phy_wrapper_n_1012,u_ddr_mc_phy_wrapper_n_1013,u_ddr_mc_phy_wrapper_n_1014,u_ddr_mc_phy_wrapper_n_1015,u_ddr_mc_phy_wrapper_n_1016,u_ddr_mc_phy_wrapper_n_1017,u_ddr_mc_phy_wrapper_n_1018,u_ddr_mc_phy_wrapper_n_1019,u_ddr_mc_phy_wrapper_n_1020,u_ddr_mc_phy_wrapper_n_1021,u_ddr_mc_phy_wrapper_n_1022,u_ddr_mc_phy_wrapper_n_1023,u_ddr_mc_phy_wrapper_n_1024,u_ddr_mc_phy_wrapper_n_1025,u_ddr_mc_phy_wrapper_n_1026,u_ddr_mc_phy_wrapper_n_1027,u_ddr_mc_phy_wrapper_n_1028,u_ddr_mc_phy_wrapper_n_1029,u_ddr_mc_phy_wrapper_n_1030}),\n .\\my_empty_reg[7]_3 ({u_ddr_mc_phy_wrapper_n_1033,u_ddr_mc_phy_wrapper_n_1034,u_ddr_mc_phy_wrapper_n_1035,u_ddr_mc_phy_wrapper_n_1036,u_ddr_mc_phy_wrapper_n_1037,u_ddr_mc_phy_wrapper_n_1038,u_ddr_mc_phy_wrapper_n_1039,u_ddr_mc_phy_wrapper_n_1040,u_ddr_mc_phy_wrapper_n_1041,u_ddr_mc_phy_wrapper_n_1042,u_ddr_mc_phy_wrapper_n_1043,u_ddr_mc_phy_wrapper_n_1044,u_ddr_mc_phy_wrapper_n_1045,u_ddr_mc_phy_wrapper_n_1046,u_ddr_mc_phy_wrapper_n_1047,u_ddr_mc_phy_wrapper_n_1048,u_ddr_mc_phy_wrapper_n_1049,u_ddr_mc_phy_wrapper_n_1050,u_ddr_mc_phy_wrapper_n_1051,u_ddr_mc_phy_wrapper_n_1052,u_ddr_mc_phy_wrapper_n_1053,u_ddr_mc_phy_wrapper_n_1054,u_ddr_mc_phy_wrapper_n_1055,u_ddr_mc_phy_wrapper_n_1056,u_ddr_mc_phy_wrapper_n_1057,u_ddr_mc_phy_wrapper_n_1058,u_ddr_mc_phy_wrapper_n_1059,u_ddr_mc_phy_wrapper_n_1060,u_ddr_mc_phy_wrapper_n_1061,u_ddr_mc_phy_wrapper_n_1062,u_ddr_mc_phy_wrapper_n_1063,u_ddr_mc_phy_wrapper_n_1064,u_ddr_mc_phy_wrapper_n_1065,u_ddr_mc_phy_wrapper_n_1066,u_ddr_mc_phy_wrapper_n_1067,u_ddr_mc_phy_wrapper_n_1068,u_ddr_mc_phy_wrapper_n_1069,u_ddr_mc_phy_wrapper_n_1070,u_ddr_mc_phy_wrapper_n_1071,u_ddr_mc_phy_wrapper_n_1072,u_ddr_mc_phy_wrapper_n_1073,u_ddr_mc_phy_wrapper_n_1074,u_ddr_mc_phy_wrapper_n_1075,u_ddr_mc_phy_wrapper_n_1076,u_ddr_mc_phy_wrapper_n_1077,u_ddr_mc_phy_wrapper_n_1078,u_ddr_mc_phy_wrapper_n_1079,u_ddr_mc_phy_wrapper_n_1080,u_ddr_mc_phy_wrapper_n_1081,u_ddr_mc_phy_wrapper_n_1082,u_ddr_mc_phy_wrapper_n_1083,u_ddr_mc_phy_wrapper_n_1084,u_ddr_mc_phy_wrapper_n_1085,u_ddr_mc_phy_wrapper_n_1086,u_ddr_mc_phy_wrapper_n_1087,u_ddr_mc_phy_wrapper_n_1088,u_ddr_mc_phy_wrapper_n_1089,u_ddr_mc_phy_wrapper_n_1090,u_ddr_mc_phy_wrapper_n_1091,u_ddr_mc_phy_wrapper_n_1092,u_ddr_mc_phy_wrapper_n_1093,u_ddr_mc_phy_wrapper_n_1094,u_ddr_mc_phy_wrapper_n_1095,u_ddr_mc_phy_wrapper_n_1096}),\n .\\not_strict_mode.app_rd_data_reg[0] (\\not_strict_mode.app_rd_data_reg[0] ),\n .\\not_strict_mode.app_rd_data_reg[100] (\\not_strict_mode.app_rd_data_reg[100] ),\n .\\not_strict_mode.app_rd_data_reg[101] (\\not_strict_mode.app_rd_data_reg[101] ),\n .\\not_strict_mode.app_rd_data_reg[102] (\\not_strict_mode.app_rd_data_reg[102] ),\n .\\not_strict_mode.app_rd_data_reg[103] (\\not_strict_mode.app_rd_data_reg[103] ),\n .\\not_strict_mode.app_rd_data_reg[104] (\\not_strict_mode.app_rd_data_reg[104] ),\n .\\not_strict_mode.app_rd_data_reg[105] (\\not_strict_mode.app_rd_data_reg[105] ),\n .\\not_strict_mode.app_rd_data_reg[106] (\\not_strict_mode.app_rd_data_reg[106] ),\n .\\not_strict_mode.app_rd_data_reg[107] (\\not_strict_mode.app_rd_data_reg[107] ),\n .\\not_strict_mode.app_rd_data_reg[108] (\\not_strict_mode.app_rd_data_reg[108] ),\n .\\not_strict_mode.app_rd_data_reg[109] (\\not_strict_mode.app_rd_data_reg[109] ),\n .\\not_strict_mode.app_rd_data_reg[10] (\\not_strict_mode.app_rd_data_reg[10] ),\n .\\not_strict_mode.app_rd_data_reg[110] (\\not_strict_mode.app_rd_data_reg[110] ),\n .\\not_strict_mode.app_rd_data_reg[111] (\\not_strict_mode.app_rd_data_reg[111] ),\n .\\not_strict_mode.app_rd_data_reg[112] (\\not_strict_mode.app_rd_data_reg[112] ),\n .\\not_strict_mode.app_rd_data_reg[113] (\\not_strict_mode.app_rd_data_reg[113] ),\n .\\not_strict_mode.app_rd_data_reg[114] (\\not_strict_mode.app_rd_data_reg[114] ),\n .\\not_strict_mode.app_rd_data_reg[115] (\\not_strict_mode.app_rd_data_reg[115] ),\n .\\not_strict_mode.app_rd_data_reg[116] (\\not_strict_mode.app_rd_data_reg[116] ),\n .\\not_strict_mode.app_rd_data_reg[117] (\\not_strict_mode.app_rd_data_reg[117] ),\n .\\not_strict_mode.app_rd_data_reg[118] (\\not_strict_mode.app_rd_data_reg[118] ),\n .\\not_strict_mode.app_rd_data_reg[119] (\\not_strict_mode.app_rd_data_reg[119] ),\n .\\not_strict_mode.app_rd_data_reg[11] (\\not_strict_mode.app_rd_data_reg[11] ),\n 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.\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ),\n .\\not_strict_mode.status_ram.rd_buf_we_r1_reg (\\not_strict_mode.status_ram.rd_buf_we_r1_reg ),\n .of_ctl_full_v(of_ctl_full_v),\n .ofs_rdy_r_reg(ofs_rdy_r_reg),\n .ofs_rdy_r_reg_0(ofs_rdy_r_reg_0),\n .out(u_ddr_calib_top_n_45),\n .p_0_out(\\u_ddr_phy_wrcal/p_0_out ),\n .pd_out(pd_out),\n .phy_dout({phy_dout[1],\\cmd_pipe_plus.mc_address_reg[43] [1],phy_dout[0],\\cmd_pipe_plus.mc_address_reg[43] [0],mux_address[57],mux_address[42],mux_address[27],mux_address[12],mux_address[56],mux_address[41],mux_address[26],mux_address[11],mux_address[55],mux_address[40],mux_address[25],mux_address[10],mux_address[54],mux_address[39],mux_address[24],mux_address[9],mux_address[53],mux_address[38],mux_address[23],mux_address[8],mux_address[52],mux_address[37],mux_address[22],mux_address[7],mux_address[51],mux_address[36],mux_address[21],mux_address[6],mux_address[50],mux_address[35],mux_address[20],mux_address[5]}),\n .phy_if_empty_r_reg(u_ddr_mc_phy_wrapper_n_1127),\n .phy_if_reset(phy_if_reset),\n .phy_mc_ctl_full(phy_mc_ctl_full),\n .phy_rddata_en(phy_rddata_en),\n .phy_read_calib(phy_read_calib),\n .phy_write_calib(phy_write_calib),\n .\\pi_dqs_found_lanes_r1_reg[3] ({u_ddr_mc_phy_wrapper_n_43,u_ddr_mc_phy_wrapper_n_44,u_ddr_mc_phy_wrapper_n_45,u_ddr_mc_phy_wrapper_n_46}),\n .pi_en_stg2_f_reg(u_ddr_calib_top_n_455),\n .pi_en_stg2_f_reg_0(u_ddr_calib_top_n_431),\n .pi_en_stg2_f_reg_1(u_ddr_calib_top_n_421),\n .pi_en_stg2_f_reg_2(u_ddr_calib_top_n_411),\n .pi_phase_locked_all_r1_reg(u_ddr_mc_phy_wrapper_n_756),\n .\\pi_rdval_cnt_reg[5] (\\u_ddr_mc_phy/pi_counter_read_val_w[0]_1 ),\n .pi_stg2_f_incdec_reg(u_ddr_calib_top_n_454),\n .pi_stg2_f_incdec_reg_0(u_ddr_calib_top_n_430),\n .pi_stg2_f_incdec_reg_1(u_ddr_calib_top_n_420),\n .pi_stg2_f_incdec_reg_2(u_ddr_calib_top_n_410),\n .pll_locked(pll_locked),\n .\\po_counter_read_val_r_reg[5] ({u_ddr_mc_phy_wrapper_n_107,u_ddr_mc_phy_wrapper_n_108,u_ddr_mc_phy_wrapper_n_109,u_ddr_mc_phy_wrapper_n_110,u_ddr_mc_phy_wrapper_n_111,u_ddr_mc_phy_wrapper_n_112}),\n .\\po_rdval_cnt_reg[8] ({\\u_ddr_mc_phy/po_counter_read_val_w[0]_0 [8:6],\\u_ddr_mc_phy/po_counter_read_val_w[0]_0 [3],\\u_ddr_mc_phy/po_counter_read_val_w[0]_0 [0]}),\n .\\po_rdval_cnt_reg[8]_0 ({\\u_ddr_mc_phy/po_counter_read_val_w[1]_2 [8:6],\\u_ddr_mc_phy/po_counter_read_val_w[1]_2 [3],\\u_ddr_mc_phy/po_counter_read_val_w[1]_2 [0]}),\n .\\po_stg2_wrcal_cnt_reg[1] (po_stg2_wrcal_cnt),\n .prbs_rdlvl_start_reg(u_ddr_calib_top_n_47),\n .ram_init_done_r(ram_init_done_r),\n .rd_buf_we(rd_buf_we),\n .\\rd_mux_sel_r_reg[1] ({u_ddr_calib_top_n_837,u_ddr_calib_top_n_838}),\n .\\rd_ptr_reg[3] ({\\rd_ptr_reg[3] [71:70],\\rd_ptr_reg[3] [65:62],\\rd_ptr_reg[3] [57:54],\\rd_ptr_reg[3] [33:30],\\rd_ptr_reg[3] [25:21],\\rd_ptr_reg[3] [17:13],\\rd_ptr_reg[3] [9:0]}),\n .\\rd_ptr_reg[3]_0 ({\\rd_ptr_reg[3]_0 [29:26],\\rd_ptr_reg[3]_0 [21:18],\\rd_ptr_reg[3]_0 [13:12],\\rd_ptr_reg[3]_0 [7:0]}),\n .\\rd_ptr_timing_reg[2] (\\rd_ptr_timing_reg[2] ),\n .\\rd_ptr_timing_reg[2]_0 (\\rd_ptr_timing_reg[2]_0 ),\n .\\rd_ptr_timing_reg[2]_1 (\\rd_ptr_timing_reg[2]_1 ),\n .\\rd_ptr_timing_reg[2]_10 (\\rd_ptr_timing_reg[2]_10 ),\n .\\rd_ptr_timing_reg[2]_2 (\\rd_ptr_timing_reg[2]_2 ),\n .\\rd_ptr_timing_reg[2]_3 (\\rd_ptr_timing_reg[2]_3 ),\n .\\rd_ptr_timing_reg[2]_4 (\\rd_ptr_timing_reg[2]_4 ),\n .\\rd_ptr_timing_reg[2]_5 (\\rd_ptr_timing_reg[2]_5 ),\n .\\rd_ptr_timing_reg[2]_6 (\\rd_ptr_timing_reg[2]_6 ),\n .\\rd_ptr_timing_reg[2]_7 (\\rd_ptr_timing_reg[2]_7 ),\n .\\rd_ptr_timing_reg[2]_8 (\\rd_ptr_timing_reg[2]_8 ),\n .\\rd_ptr_timing_reg[2]_9 (\\rd_ptr_timing_reg[2]_9 ),\n .\\read_fifo.fifo_out_data_r_reg[6] (\\read_fifo.fifo_out_data_r_reg[6] ),\n .\\read_fifo.fifo_out_data_r_reg[6]_0 (\\read_fifo.fifo_out_data_r_reg[6]_0 ),\n .\\read_fifo.tail_r_reg[0] (\\read_fifo.tail_r_reg[0] ),\n .\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] (\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .rst_sync_r1(rst_sync_r1),\n .rst_sync_r1_reg(rst_sync_r1_reg),\n .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2),\n .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9),\n .sync_pulse(sync_pulse),\n .sys_rst(sys_rst),\n .tail_r(tail_r),\n .wr_en(wr_en),\n .wr_en_5(wr_en_5),\n .wr_en_6(wr_en_6),\n .\\wr_ptr_timing_reg[2] (\\wr_ptr_timing_reg[2] ),\n .\\wr_ptr_timing_reg[2]_0 (\\wr_ptr_timing_reg[2]_0 ),\n .\\wr_ptr_timing_reg[2]_1 (\\wr_ptr_timing_reg[2]_1 ),\n .\\write_buffer.wr_buf_out_data_reg[224] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ),\n .\\write_buffer.wr_buf_out_data_reg[225] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ),\n .\\write_buffer.wr_buf_out_data_reg[226] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ),\n .\\write_buffer.wr_buf_out_data_reg[227] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ),\n .\\write_buffer.wr_buf_out_data_reg[228] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ),\n .\\write_buffer.wr_buf_out_data_reg[229] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ),\n .\\write_buffer.wr_buf_out_data_reg[230] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ),\n .\\write_buffer.wr_buf_out_data_reg[231] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 ),\n .\\write_buffer.wr_buf_out_data_reg[232] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ),\n .\\write_buffer.wr_buf_out_data_reg[233] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ),\n .\\write_buffer.wr_buf_out_data_reg[234] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ),\n .\\write_buffer.wr_buf_out_data_reg[235] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ),\n .\\write_buffer.wr_buf_out_data_reg[236] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ),\n .\\write_buffer.wr_buf_out_data_reg[237] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ),\n .\\write_buffer.wr_buf_out_data_reg[238] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ),\n .\\write_buffer.wr_buf_out_data_reg[239] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1 ),\n .\\write_buffer.wr_buf_out_data_reg[240] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8 ),\n .\\write_buffer.wr_buf_out_data_reg[241] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7 ),\n .\\write_buffer.wr_buf_out_data_reg[242] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ),\n .\\write_buffer.wr_buf_out_data_reg[243] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ),\n .\\write_buffer.wr_buf_out_data_reg[244] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ),\n .\\write_buffer.wr_buf_out_data_reg[245] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3 ),\n .\\write_buffer.wr_buf_out_data_reg[246] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2 ),\n .\\write_buffer.wr_buf_out_data_reg[247] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1 ),\n .\\write_buffer.wr_buf_out_data_reg[248] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7 ),\n .\\write_buffer.wr_buf_out_data_reg[249] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6 ),\n .\\write_buffer.wr_buf_out_data_reg[250] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5 ),\n .\\write_buffer.wr_buf_out_data_reg[251] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4 ),\n .\\write_buffer.wr_buf_out_data_reg[252] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3 ),\n .\\write_buffer.wr_buf_out_data_reg[253] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2 ),\n .\\write_buffer.wr_buf_out_data_reg[254] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ),\n .\\write_buffer.wr_buf_out_data_reg[255] (\\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0 ));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_ddr_phy_wrcal\n (rd_active_r1,\n rd_active_r2,\n wrcal_pat_resume_r,\n wrcal_resume_w,\n idelay_ld_reg_0,\n wrcal_done_reg_0,\n \\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 ,\n \\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 ,\n \\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 ,\n \\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 ,\n \\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 ,\n \\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 ,\n \\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 ,\n \\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 ,\n \\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 ,\n \\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 ,\n \\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 ,\n \\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_208 ,\n \\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 ,\n \\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 ,\n \\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 ,\n \\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_212 ,\n \\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 ,\n \\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 ,\n \\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 ,\n \\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 ,\n \\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 ,\n \\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 ,\n \\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 ,\n \\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 ,\n \\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 ,\n \\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 ,\n \\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 ,\n \\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 ,\n \\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 ,\n \\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 ,\n \\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 ,\n \\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 ,\n \\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 ,\n \\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 ,\n \\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 ,\n \\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 ,\n \\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 ,\n \\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 ,\n \\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 ,\n \\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 ,\n \\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 ,\n \\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 ,\n \\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 ,\n \\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 ,\n \\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 ,\n \\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 ,\n \\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 ,\n \\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 ,\n \\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 ,\n \\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 ,\n \\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 ,\n \\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 ,\n \\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 ,\n \\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 ,\n \\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 ,\n \\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 ,\n \\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 ,\n \\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 ,\n \\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 ,\n \\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 ,\n early2_data_reg_0,\n early1_data_reg_0,\n wrcal_prech_req,\n wrcal_pat_resume_r_reg_0,\n cal2_done_r,\n wrcal_sanity_chk_done_reg_0,\n wrlvl_byte_redo,\n early1_data_reg_1,\n early2_data_reg_1,\n idelay_ld,\n phy_if_reset_w,\n LD0,\n LD0_0,\n LD0_1,\n LD0_2,\n \\init_state_r_reg[3] ,\n wrcal_done_reg_1,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] ,\n \\idelay_tap_cnt_r_reg[0][2][0] ,\n \\idelay_tap_cnt_r_reg[0][2][0]_0 ,\n \\idelay_tap_cnt_r_reg[0][1][0] ,\n \\init_state_r_reg[0] ,\n \\init_state_r_reg[2] ,\n \\init_state_r_reg[4] ,\n \\init_state_r_reg[0]_0 ,\n \\init_state_r_reg[0]_1 ,\n \\init_state_r_reg[5] ,\n \\init_state_r_reg[0]_2 ,\n \\corse_cnt_reg[1][2] ,\n \\corse_cnt_reg[2][2] ,\n done_dqs_dec239_out,\n \\corse_cnt_reg[0][2] ,\n \\wrlvl_redo_corse_inc_reg[2] ,\n \\FSM_sequential_wl_state_r_reg[0] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[1] ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[2] ,\n \\not_empty_wait_cnt_reg[0]_0 ,\n wrcal_pat_resume_r_reg_1,\n idelay_ld_done_reg_0,\n cal2_if_reset_reg_0,\n cal2_if_reset_reg_1,\n idelay_ld_reg_1,\n cal2_done_r_reg_0,\n wrlvl_byte_redo_reg_0,\n early1_data_reg_2,\n cal2_if_reset_reg_2,\n phy_rddata_en_1,\n CLK,\n \\po_stg2_wrcal_cnt_reg[1]_0 ,\n \\po_stg2_wrcal_cnt_reg[1]_1 ,\n \\po_stg2_wrcal_cnt_reg[1]_2 ,\n \\po_stg2_wrcal_cnt_reg[1]_3 ,\n wrcal_sanity_chk,\n p_0_out,\n \\po_stg2_wrcal_cnt_reg[1]_4 ,\n \\po_stg2_wrcal_cnt_reg[1]_5 ,\n \\po_stg2_wrcal_cnt_reg[1]_6 ,\n \\po_stg2_wrcal_cnt_reg[1]_7 ,\n \\po_stg2_wrcal_cnt_reg[1]_8 ,\n \\po_stg2_wrcal_cnt_reg[1]_9 ,\n \\po_stg2_wrcal_cnt_reg[1]_10 ,\n \\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1][0]_0 ,\n \\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2][0]_0 ,\n \\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5][0]_0 ,\n \\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6][0]_0 ,\n \\po_stg2_wrcal_cnt_reg[1]_11 ,\n \\po_stg2_wrcal_cnt_reg[1]_12 ,\n \\po_stg2_wrcal_cnt_reg[1]_13 ,\n \\po_stg2_wrcal_cnt_reg[1]_14 ,\n \\po_stg2_wrcal_cnt_reg[1]_15 ,\n \\po_stg2_wrcal_cnt_reg[1]_16 ,\n \\po_stg2_wrcal_cnt_reg[1]_17 ,\n \\po_stg2_wrcal_cnt_reg[1]_18 ,\n \\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0][0]_0 ,\n \\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1][0]_0 ,\n \\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3][0]_0 ,\n \\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4][0]_0 ,\n \\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5][0]_0 ,\n \\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7][0]_0 ,\n \\po_stg2_wrcal_cnt_reg[1]_19 ,\n \\po_stg2_wrcal_cnt_reg[1]_20 ,\n \\po_stg2_wrcal_cnt_reg[1]_21 ,\n \\po_stg2_wrcal_cnt_reg[1]_22 ,\n \\po_stg2_wrcal_cnt_reg[1]_23 ,\n \\po_stg2_wrcal_cnt_reg[1]_24 ,\n \\po_stg2_wrcal_cnt_reg[1]_25 ,\n \\po_stg2_wrcal_cnt_reg[1]_26 ,\n \\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0][0]_0 ,\n \\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2][0]_0 ,\n \\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4][0]_0 ,\n \\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6][0]_0 ,\n \\po_stg2_wrcal_cnt_reg[1]_27 ,\n \\po_stg2_wrcal_cnt_reg[1]_28 ,\n \\po_stg2_wrcal_cnt_reg[1]_29 ,\n \\po_stg2_wrcal_cnt_reg[1]_30 ,\n \\po_stg2_wrcal_cnt_reg[1]_31 ,\n \\po_stg2_wrcal_cnt_reg[1]_32 ,\n \\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2][0]_0 ,\n \\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6][0]_0 ,\n \\po_stg2_wrcal_cnt_reg[1]_33 ,\n \\po_stg2_wrcal_cnt_reg[1]_34 ,\n \\po_stg2_wrcal_cnt_reg[1]_35 ,\n \\po_stg2_wrcal_cnt_reg[1]_36 ,\n \\po_stg2_wrcal_cnt_reg[1]_37 ,\n \\po_stg2_wrcal_cnt_reg[1]_38 ,\n \\po_stg2_wrcal_cnt_reg[1]_39 ,\n \\po_stg2_wrcal_cnt_reg[1]_40 ,\n \\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2][0]_0 ,\n \\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3][0]_0 ,\n \\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6][0]_0 ,\n \\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7][0]_0 ,\n \\po_stg2_wrcal_cnt_reg[1]_41 ,\n \\po_stg2_wrcal_cnt_reg[1]_42 ,\n \\po_stg2_wrcal_cnt_reg[1]_43 ,\n \\po_stg2_wrcal_cnt_reg[1]_44 ,\n \\po_stg2_wrcal_cnt_reg[1]_45 ,\n \\po_stg2_wrcal_cnt_reg[1]_46 ,\n \\po_stg2_wrcal_cnt_reg[1]_47 ,\n \\po_stg2_wrcal_cnt_reg[1]_48 ,\n \\po_stg2_wrcal_cnt_reg[1]_49 ,\n \\po_stg2_wrcal_cnt_reg[1]_50 ,\n \\po_stg2_wrcal_cnt_reg[1]_51 ,\n \\po_stg2_wrcal_cnt_reg[1]_52 ,\n \\po_stg2_wrcal_cnt_reg[1]_53 ,\n \\po_stg2_wrcal_cnt_reg[1]_54 ,\n \\po_stg2_wrcal_cnt_reg[1]_55 ,\n \\po_stg2_wrcal_cnt_reg[1]_56 ,\n \\po_stg2_wrcal_cnt_reg[1]_57 ,\n \\po_stg2_wrcal_cnt_reg[1]_58 ,\n \\po_stg2_wrcal_cnt_reg[1]_59 ,\n \\po_stg2_wrcal_cnt_reg[1]_60 ,\n \\po_stg2_wrcal_cnt_reg[1]_61 ,\n \\po_stg2_wrcal_cnt_reg[1]_62 ,\n \\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0][0]_0 ,\n \\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3][0]_0 ,\n \\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4][0]_0 ,\n \\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7][0]_0 ,\n \\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1][0]_0 ,\n \\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5][0]_0 ,\n \\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2][0]_0 ,\n \\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6][0]_0 ,\n \\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0][0]_0 ,\n \\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4][0]_0 ,\n \\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1][0]_0 ,\n \\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3][0]_0 ,\n \\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5][0]_0 ,\n \\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7][0]_0 ,\n rstdiv0_sync_r1_reg_rep__4,\n rstdiv0_sync_r1_reg_rep__6,\n wrlvl_byte_done,\n rstdiv0_sync_r1_reg_rep__5,\n \\cal2_state_r_reg[0]_0 ,\n \\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1][0]_0 ,\n \\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5][0]_0 ,\n \\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0][0]_0 ,\n \\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4][0]_0 ,\n \\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1][0]_0 ,\n \\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3][0]_0 ,\n \\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5][0]_0 ,\n \\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7][0]_0 ,\n \\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3][0]_0 ,\n \\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7][0]_0 ,\n \\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2][0]_0 ,\n \\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6][0]_0 ,\n \\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2][0]_0 ,\n \\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6][0]_0 ,\n \\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0][0]_0 ,\n \\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2][0]_0 ,\n \\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4][0]_0 ,\n \\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6][0]_0 ,\n \\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1][0]_0 ,\n \\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5][0]_0 ,\n \\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3][0]_0 ,\n \\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7][0]_0 ,\n \\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1][0]_0 ,\n \\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5][0]_0 ,\n \\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0][0]_0 ,\n \\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4][0]_0 ,\n wrcal_sanity_chk_r_reg_0,\n \\cal2_state_r_reg[3]_0 ,\n \\gen_pat_match_div4.early2_data_match_r_reg_0 ,\n \\gen_pat_match_div4.early1_data_match_r_reg_0 ,\n \\gen_pat_match_div4.early1_data_match_r_reg_1 ,\n \\gen_pat_match_div4.pat_data_match_valid_r_reg_0 ,\n rstdiv0_sync_r1_reg_rep__2,\n \\cal2_state_r_reg[2]_0 ,\n \\cal2_state_r_reg[0]_1 ,\n Q,\n \\calib_sel_reg[1] ,\n calib_in_common,\n idelay_ld_rst,\n idelay_ld_rst_3,\n idelay_ld_rst_4,\n idelay_ld_rst_5,\n dqs_found_done_r_reg,\n rdlvl_stg1_start_int_reg,\n rdlvl_stg1_done_int_reg,\n oclkdelay_calib_done_r_reg,\n first_wrcal_pat_r,\n idelay_ce_int,\n oclkdelay_calib_done_r_reg_0,\n wrlvl_final_mux,\n mem_init_done_r,\n dqs_found_done_r_reg_0,\n mpr_rdlvl_done_r_reg,\n mpr_last_byte_done,\n prbs_rdlvl_done_reg_rep,\n prech_req_posedge_r_reg,\n wrcal_resume_r,\n wrlvl_done_r1,\n rdlvl_stg1_done_int_reg_0,\n oclkdelay_center_calib_done_r_reg,\n prbs_rdlvl_done_reg_rep_0,\n ddr3_lm_done_r,\n wrlvl_byte_redo_r,\n \\final_coarse_tap_reg[3][2] ,\n wl_sm_start,\n prbs_rdlvl_done_reg,\n \\prbs_dqs_cnt_r_reg[0] ,\n \\prbs_dqs_cnt_r_reg[1] ,\n rstdiv0_sync_r1_reg_rep__23,\n wrcal_rd_wait,\n wrcal_start_reg,\n prech_done,\n wrcal_sanity_chk_reg,\n phy_rddata_en_r1_reg);\n output rd_active_r1;\n output rd_active_r2;\n output wrcal_pat_resume_r;\n output wrcal_resume_w;\n output idelay_ld_reg_0;\n output wrcal_done_reg_0;\n output \\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 ;\n output \\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 ;\n output \\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 ;\n output \\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 ;\n output \\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 ;\n output \\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 ;\n output \\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 ;\n output \\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 ;\n output \\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 ;\n output \\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 ;\n output \\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 ;\n output \\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_208 ;\n output \\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 ;\n output \\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 ;\n output \\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 ;\n output \\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_212 ;\n output \\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 ;\n output \\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 ;\n output \\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 ;\n output \\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 ;\n output \\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 ;\n output \\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 ;\n output \\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 ;\n output \\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 ;\n output \\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 ;\n output \\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 ;\n output \\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 ;\n output \\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 ;\n output \\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 ;\n output \\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 ;\n output \\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 ;\n output \\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 ;\n output \\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 ;\n output \\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 ;\n output \\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 ;\n output \\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 ;\n output \\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 ;\n output \\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 ;\n output \\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 ;\n output \\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 ;\n output \\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 ;\n output \\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 ;\n output \\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 ;\n output \\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 ;\n output \\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 ;\n output \\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 ;\n output \\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 ;\n output \\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 ;\n output \\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 ;\n output \\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 ;\n output \\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 ;\n output \\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 ;\n output \\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 ;\n output \\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 ;\n output \\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 ;\n output \\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 ;\n output \\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 ;\n output \\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 ;\n output \\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 ;\n output \\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 ;\n output early2_data_reg_0;\n output early1_data_reg_0;\n output wrcal_prech_req;\n output wrcal_pat_resume_r_reg_0;\n output cal2_done_r;\n output wrcal_sanity_chk_done_reg_0;\n output wrlvl_byte_redo;\n output early1_data_reg_1;\n output early2_data_reg_1;\n output idelay_ld;\n output phy_if_reset_w;\n output LD0;\n output LD0_0;\n output LD0_1;\n output LD0_2;\n output \\init_state_r_reg[3] ;\n output wrcal_done_reg_1;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] ;\n output \\idelay_tap_cnt_r_reg[0][2][0] ;\n output [2:0]\\idelay_tap_cnt_r_reg[0][2][0]_0 ;\n output \\idelay_tap_cnt_r_reg[0][1][0] ;\n output \\init_state_r_reg[0] ;\n output \\init_state_r_reg[2] ;\n output \\init_state_r_reg[4] ;\n output \\init_state_r_reg[0]_0 ;\n output \\init_state_r_reg[0]_1 ;\n output \\init_state_r_reg[5] ;\n output \\init_state_r_reg[0]_2 ;\n output \\corse_cnt_reg[1][2] ;\n output \\corse_cnt_reg[2][2] ;\n output done_dqs_dec239_out;\n output \\corse_cnt_reg[0][2] ;\n output \\wrlvl_redo_corse_inc_reg[2] ;\n output \\FSM_sequential_wl_state_r_reg[0] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] ;\n output \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ;\n output \\gen_byte_sel_div1.byte_sel_cnt_reg[1] ;\n output \\gen_byte_sel_div1.byte_sel_cnt_reg[2] ;\n output [3:0]\\not_empty_wait_cnt_reg[0]_0 ;\n output wrcal_pat_resume_r_reg_1;\n output idelay_ld_done_reg_0;\n output cal2_if_reset_reg_0;\n output cal2_if_reset_reg_1;\n output idelay_ld_reg_1;\n output cal2_done_r_reg_0;\n output wrlvl_byte_redo_reg_0;\n output early1_data_reg_2;\n output cal2_if_reset_reg_2;\n input phy_rddata_en_1;\n input CLK;\n input \\po_stg2_wrcal_cnt_reg[1]_0 ;\n input \\po_stg2_wrcal_cnt_reg[1]_1 ;\n input \\po_stg2_wrcal_cnt_reg[1]_2 ;\n input \\po_stg2_wrcal_cnt_reg[1]_3 ;\n input wrcal_sanity_chk;\n input p_0_out;\n input \\po_stg2_wrcal_cnt_reg[1]_4 ;\n input \\po_stg2_wrcal_cnt_reg[1]_5 ;\n input \\po_stg2_wrcal_cnt_reg[1]_6 ;\n input \\po_stg2_wrcal_cnt_reg[1]_7 ;\n input \\po_stg2_wrcal_cnt_reg[1]_8 ;\n input \\po_stg2_wrcal_cnt_reg[1]_9 ;\n input \\po_stg2_wrcal_cnt_reg[1]_10 ;\n input \\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1][0]_0 ;\n input \\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2][0]_0 ;\n input \\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5][0]_0 ;\n input \\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6][0]_0 ;\n input \\po_stg2_wrcal_cnt_reg[1]_11 ;\n input \\po_stg2_wrcal_cnt_reg[1]_12 ;\n input \\po_stg2_wrcal_cnt_reg[1]_13 ;\n input \\po_stg2_wrcal_cnt_reg[1]_14 ;\n input \\po_stg2_wrcal_cnt_reg[1]_15 ;\n input \\po_stg2_wrcal_cnt_reg[1]_16 ;\n input \\po_stg2_wrcal_cnt_reg[1]_17 ;\n input \\po_stg2_wrcal_cnt_reg[1]_18 ;\n input \\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0][0]_0 ;\n input \\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1][0]_0 ;\n input \\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3][0]_0 ;\n input \\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4][0]_0 ;\n input \\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5][0]_0 ;\n input \\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7][0]_0 ;\n input \\po_stg2_wrcal_cnt_reg[1]_19 ;\n input \\po_stg2_wrcal_cnt_reg[1]_20 ;\n input \\po_stg2_wrcal_cnt_reg[1]_21 ;\n input \\po_stg2_wrcal_cnt_reg[1]_22 ;\n input \\po_stg2_wrcal_cnt_reg[1]_23 ;\n input \\po_stg2_wrcal_cnt_reg[1]_24 ;\n input \\po_stg2_wrcal_cnt_reg[1]_25 ;\n input \\po_stg2_wrcal_cnt_reg[1]_26 ;\n input \\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0][0]_0 ;\n input \\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2][0]_0 ;\n input \\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4][0]_0 ;\n input \\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6][0]_0 ;\n input \\po_stg2_wrcal_cnt_reg[1]_27 ;\n input \\po_stg2_wrcal_cnt_reg[1]_28 ;\n input \\po_stg2_wrcal_cnt_reg[1]_29 ;\n input \\po_stg2_wrcal_cnt_reg[1]_30 ;\n input \\po_stg2_wrcal_cnt_reg[1]_31 ;\n input \\po_stg2_wrcal_cnt_reg[1]_32 ;\n input \\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2][0]_0 ;\n input \\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6][0]_0 ;\n input \\po_stg2_wrcal_cnt_reg[1]_33 ;\n input \\po_stg2_wrcal_cnt_reg[1]_34 ;\n input \\po_stg2_wrcal_cnt_reg[1]_35 ;\n input \\po_stg2_wrcal_cnt_reg[1]_36 ;\n input \\po_stg2_wrcal_cnt_reg[1]_37 ;\n input \\po_stg2_wrcal_cnt_reg[1]_38 ;\n input \\po_stg2_wrcal_cnt_reg[1]_39 ;\n input \\po_stg2_wrcal_cnt_reg[1]_40 ;\n input \\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2][0]_0 ;\n input \\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3][0]_0 ;\n input \\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6][0]_0 ;\n input \\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7][0]_0 ;\n input \\po_stg2_wrcal_cnt_reg[1]_41 ;\n input \\po_stg2_wrcal_cnt_reg[1]_42 ;\n input \\po_stg2_wrcal_cnt_reg[1]_43 ;\n input \\po_stg2_wrcal_cnt_reg[1]_44 ;\n input \\po_stg2_wrcal_cnt_reg[1]_45 ;\n input \\po_stg2_wrcal_cnt_reg[1]_46 ;\n input \\po_stg2_wrcal_cnt_reg[1]_47 ;\n input \\po_stg2_wrcal_cnt_reg[1]_48 ;\n input \\po_stg2_wrcal_cnt_reg[1]_49 ;\n input \\po_stg2_wrcal_cnt_reg[1]_50 ;\n input \\po_stg2_wrcal_cnt_reg[1]_51 ;\n input \\po_stg2_wrcal_cnt_reg[1]_52 ;\n input \\po_stg2_wrcal_cnt_reg[1]_53 ;\n input \\po_stg2_wrcal_cnt_reg[1]_54 ;\n input \\po_stg2_wrcal_cnt_reg[1]_55 ;\n input \\po_stg2_wrcal_cnt_reg[1]_56 ;\n input \\po_stg2_wrcal_cnt_reg[1]_57 ;\n input \\po_stg2_wrcal_cnt_reg[1]_58 ;\n input \\po_stg2_wrcal_cnt_reg[1]_59 ;\n input \\po_stg2_wrcal_cnt_reg[1]_60 ;\n input \\po_stg2_wrcal_cnt_reg[1]_61 ;\n input \\po_stg2_wrcal_cnt_reg[1]_62 ;\n input \\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0][0]_0 ;\n input \\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3][0]_0 ;\n input \\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4][0]_0 ;\n input \\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7][0]_0 ;\n input \\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1][0]_0 ;\n input \\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5][0]_0 ;\n input \\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2][0]_0 ;\n input \\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6][0]_0 ;\n input \\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0][0]_0 ;\n input \\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4][0]_0 ;\n input \\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1][0]_0 ;\n input \\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3][0]_0 ;\n input \\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5][0]_0 ;\n input \\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7][0]_0 ;\n input rstdiv0_sync_r1_reg_rep__4;\n input rstdiv0_sync_r1_reg_rep__6;\n input wrlvl_byte_done;\n input [0:0]rstdiv0_sync_r1_reg_rep__5;\n input \\cal2_state_r_reg[0]_0 ;\n input \\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1][0]_0 ;\n input \\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5][0]_0 ;\n input \\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0][0]_0 ;\n input \\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4][0]_0 ;\n input \\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1][0]_0 ;\n input \\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3][0]_0 ;\n input \\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5][0]_0 ;\n input \\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7][0]_0 ;\n input \\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3][0]_0 ;\n input \\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7][0]_0 ;\n input \\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2][0]_0 ;\n input \\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6][0]_0 ;\n input \\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2][0]_0 ;\n input \\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6][0]_0 ;\n input \\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0][0]_0 ;\n input \\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2][0]_0 ;\n input \\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4][0]_0 ;\n input \\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6][0]_0 ;\n input \\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1][0]_0 ;\n input \\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5][0]_0 ;\n input \\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3][0]_0 ;\n input \\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7][0]_0 ;\n input \\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1][0]_0 ;\n input \\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5][0]_0 ;\n input \\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0][0]_0 ;\n input \\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4][0]_0 ;\n input wrcal_sanity_chk_r_reg_0;\n input \\cal2_state_r_reg[3]_0 ;\n input \\gen_pat_match_div4.early2_data_match_r_reg_0 ;\n input \\gen_pat_match_div4.early1_data_match_r_reg_0 ;\n input \\gen_pat_match_div4.early1_data_match_r_reg_1 ;\n input \\gen_pat_match_div4.pat_data_match_valid_r_reg_0 ;\n input rstdiv0_sync_r1_reg_rep__2;\n input \\cal2_state_r_reg[2]_0 ;\n input \\cal2_state_r_reg[0]_1 ;\n input [0:0]Q;\n input [1:0]\\calib_sel_reg[1] ;\n input calib_in_common;\n input idelay_ld_rst;\n input idelay_ld_rst_3;\n input idelay_ld_rst_4;\n input idelay_ld_rst_5;\n input dqs_found_done_r_reg;\n input rdlvl_stg1_start_int_reg;\n input rdlvl_stg1_done_int_reg;\n input oclkdelay_calib_done_r_reg;\n input first_wrcal_pat_r;\n input idelay_ce_int;\n input oclkdelay_calib_done_r_reg_0;\n input wrlvl_final_mux;\n input mem_init_done_r;\n input dqs_found_done_r_reg_0;\n input mpr_rdlvl_done_r_reg;\n input mpr_last_byte_done;\n input prbs_rdlvl_done_reg_rep;\n input prech_req_posedge_r_reg;\n input wrcal_resume_r;\n input wrlvl_done_r1;\n input rdlvl_stg1_done_int_reg_0;\n input oclkdelay_center_calib_done_r_reg;\n input prbs_rdlvl_done_reg_rep_0;\n input ddr3_lm_done_r;\n input wrlvl_byte_redo_r;\n input [1:0]\\final_coarse_tap_reg[3][2] ;\n input wl_sm_start;\n input prbs_rdlvl_done_reg;\n input \\prbs_dqs_cnt_r_reg[0] ;\n input \\prbs_dqs_cnt_r_reg[1] ;\n input rstdiv0_sync_r1_reg_rep__23;\n input wrcal_rd_wait;\n input wrcal_start_reg;\n input prech_done;\n input wrcal_sanity_chk_reg;\n input phy_rddata_en_r1_reg;\n\n wire CLK;\n wire \\FSM_sequential_wl_state_r_reg[0] ;\n wire LD0;\n wire LD0_0;\n wire LD0_1;\n wire LD0_2;\n wire [0:0]Q;\n wire cal2_done_r;\n wire cal2_done_r_reg_0;\n wire cal2_if_reset_i_5_n_0;\n wire cal2_if_reset_reg_0;\n wire cal2_if_reset_reg_1;\n wire cal2_if_reset_reg_2;\n wire cal2_prech_req_r;\n wire cal2_prech_req_r_i_2_n_0;\n wire cal2_prech_req_r_i_3_n_0;\n wire cal2_state_r;\n wire \\cal2_state_r[0]_i_1_n_0 ;\n wire \\cal2_state_r[0]_i_2_n_0 ;\n wire \\cal2_state_r[0]_i_3_n_0 ;\n wire \\cal2_state_r[0]_i_4_n_0 ;\n wire \\cal2_state_r[0]_i_5_n_0 ;\n wire \\cal2_state_r[1]_i_1_n_0 ;\n wire \\cal2_state_r[1]_i_2_n_0 ;\n wire \\cal2_state_r[1]_i_3_n_0 ;\n wire \\cal2_state_r[2]_i_1_n_0 ;\n wire \\cal2_state_r[2]_i_2_n_0 ;\n wire \\cal2_state_r[2]_i_3_n_0 ;\n wire \\cal2_state_r[3]_i_11_n_0 ;\n wire \\cal2_state_r[3]_i_3_n_0 ;\n wire \\cal2_state_r[3]_i_4_n_0 ;\n wire \\cal2_state_r[3]_i_5_n_0 ;\n wire \\cal2_state_r[3]_i_6_n_0 ;\n wire \\cal2_state_r[3]_i_7_n_0 ;\n wire \\cal2_state_r[3]_i_8_n_0 ;\n wire \\cal2_state_r[3]_i_9_n_0 ;\n wire \\cal2_state_r_reg[0]_0 ;\n wire \\cal2_state_r_reg[0]_1 ;\n wire \\cal2_state_r_reg[2]_0 ;\n wire \\cal2_state_r_reg[3]_0 ;\n wire calib_in_common;\n wire [1:0]\\calib_sel_reg[1] ;\n wire \\corse_cnt_reg[0][2] ;\n wire \\corse_cnt_reg[1][2] ;\n wire \\corse_cnt_reg[2][2] ;\n wire ddr3_lm_done_r;\n wire done_dqs_dec239_out;\n wire dqs_found_done_r_reg;\n wire dqs_found_done_r_reg_0;\n wire early1_data_i_3_n_0;\n wire early1_data_match_r0__0;\n wire early1_data_reg_0;\n wire early1_data_reg_1;\n wire early1_data_reg_2;\n wire early1_match_fall0_and_r;\n wire early1_match_fall1_and_r;\n wire early1_match_fall2_and_r;\n wire early1_match_fall3_and_r;\n wire early1_match_rise0_and_r;\n wire early1_match_rise1_and_r;\n wire early1_match_rise2_and_r;\n wire early1_match_rise3_and_r;\n wire early2_data_match_r0__0;\n wire early2_data_reg_0;\n wire early2_data_reg_1;\n wire early2_match_fall0_and_r;\n wire early2_match_fall1_and_r;\n wire early2_match_fall2_and_r;\n wire early2_match_fall3_and_r;\n wire early2_match_rise0_and_r;\n wire early2_match_rise1_and_r;\n wire early2_match_rise2_and_r;\n wire early2_match_rise3_and_r;\n wire [1:0]\\final_coarse_tap_reg[3][2] ;\n wire first_wrcal_pat_r;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[1] ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ;\n wire \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ;\n wire \\gen_pat_match_div4.early1_data_match_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.early1_data_match_r_reg_0 ;\n wire \\gen_pat_match_div4.early1_data_match_r_reg_1 ;\n wire \\gen_pat_match_div4.early1_match_fall0_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.early1_match_fall1_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.early1_match_fall1_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.early1_match_fall2_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.early1_match_fall3_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.early1_match_fall3_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.early1_match_rise0_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.early1_match_rise1_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.early1_match_rise1_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.early1_match_rise2_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.early1_match_rise3_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.early2_data_match_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.early2_data_match_r_reg_0 ;\n wire \\gen_pat_match_div4.early2_match_fall0_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.early2_match_fall0_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.early2_match_fall1_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.early2_match_fall2_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.early2_match_fall2_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.early2_match_fall3_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.early2_match_rise0_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.early2_match_rise0_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.early2_match_rise1_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.early2_match_rise2_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.early2_match_rise2_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.early2_match_rise3_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.early2_match_rise3_and_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].early1_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].early1_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].early2_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].early1_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].early1_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].early2_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].early2_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].early1_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].early2_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].pat_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].pat_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].pat_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].early1_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].early2_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].early1_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].early1_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].early2_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].early1_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].early1_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].early2_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].early2_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].early1_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].early2_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].pat_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].pat_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].pat_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].early1_match_rise2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].early2_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise0_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise1_r_reg ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg__0 ;\n wire \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg ;\n wire \\gen_pat_match_div4.pat_data_match_r_i_2_n_0 ;\n wire \\gen_pat_match_div4.pat_data_match_r_reg_n_0 ;\n wire \\gen_pat_match_div4.pat_data_match_valid_r_reg_0 ;\n wire \\gen_pat_match_div4.pat_match_fall0_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat_match_fall1_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat_match_fall2_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat_match_fall3_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat_match_rise0_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat_match_rise1_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat_match_rise2_and_r_i_1_n_0 ;\n wire \\gen_pat_match_div4.pat_match_rise3_and_r_i_1_n_0 ;\n wire \\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0][0]_0 ;\n wire \\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 ;\n wire \\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0][0]_0 ;\n wire \\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 ;\n wire \\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0][0]_0 ;\n wire \\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 ;\n wire \\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0][0]_0 ;\n wire \\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 ;\n wire \\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0][0]_0 ;\n wire \\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 ;\n wire \\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0][0]_0 ;\n wire \\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 ;\n wire \\gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2_n_0 ;\n wire \\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0][0]_0 ;\n wire \\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 ;\n wire \\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1][0]_0 ;\n wire \\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 ;\n wire \\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1][0]_0 ;\n wire \\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 ;\n wire \\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1][0]_0 ;\n wire \\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 ;\n wire \\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1][0]_0 ;\n wire \\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 ;\n wire \\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1][0]_0 ;\n wire \\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 ;\n wire \\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1][0]_0 ;\n wire \\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 ;\n wire \\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1][0]_0 ;\n wire \\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 ;\n wire \\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1][0]_0 ;\n wire \\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 ;\n wire \\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2][0]_0 ;\n wire \\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 ;\n wire \\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2][0]_0 ;\n wire \\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 ;\n wire \\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2][0]_0 ;\n wire \\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 ;\n wire \\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2][0]_0 ;\n wire \\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 ;\n wire \\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2][0]_0 ;\n wire \\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 ;\n wire \\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2][0]_0 ;\n wire \\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 ;\n wire \\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2][0]_0 ;\n wire \\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 ;\n wire \\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2][0]_0 ;\n wire \\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 ;\n wire \\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3][0]_0 ;\n wire \\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 ;\n wire \\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3][0]_0 ;\n wire \\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 ;\n wire \\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3][0]_0 ;\n wire \\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 ;\n wire \\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3][0]_0 ;\n wire \\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_208 ;\n wire \\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3][0]_0 ;\n wire \\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 ;\n wire \\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3][0]_0 ;\n wire \\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 ;\n wire \\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3][0]_0 ;\n wire \\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 ;\n wire \\gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2_n_0 ;\n wire \\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4][0]_0 ;\n wire \\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 ;\n wire \\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4][0]_0 ;\n wire \\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 ;\n wire \\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4][0]_0 ;\n wire \\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 ;\n wire \\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4][0]_0 ;\n wire \\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 ;\n wire \\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4][0]_0 ;\n wire \\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 ;\n wire \\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4][0]_0 ;\n wire \\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 ;\n wire \\gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2_n_0 ;\n wire \\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4][0]_0 ;\n wire \\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 ;\n wire \\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5][0]_0 ;\n wire \\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 ;\n wire \\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5][0]_0 ;\n wire \\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 ;\n wire \\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5][0]_0 ;\n wire \\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 ;\n wire \\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5][0]_0 ;\n wire \\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 ;\n wire \\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5][0]_0 ;\n wire \\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 ;\n wire \\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5][0]_0 ;\n wire \\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 ;\n wire \\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5][0]_0 ;\n wire \\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 ;\n wire \\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5][0]_0 ;\n wire \\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 ;\n wire \\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6][0]_0 ;\n wire \\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 ;\n wire \\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6][0]_0 ;\n wire \\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 ;\n wire \\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6][0]_0 ;\n wire \\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 ;\n wire \\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6][0]_0 ;\n wire \\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 ;\n wire \\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6][0]_0 ;\n wire \\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 ;\n wire \\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6][0]_0 ;\n wire \\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 ;\n wire \\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6][0]_0 ;\n wire \\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 ;\n wire \\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6][0]_0 ;\n wire \\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 ;\n wire \\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7][0]_0 ;\n wire \\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 ;\n wire \\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7][0]_0 ;\n wire \\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 ;\n wire \\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7][0]_0 ;\n wire \\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 ;\n wire \\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7][0]_0 ;\n wire \\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_212 ;\n wire \\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7][0]_0 ;\n wire \\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 ;\n wire \\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7][0]_0 ;\n wire \\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 ;\n wire \\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7][0]_0 ;\n wire \\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 ;\n wire \\gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2_n_0 ;\n wire idelay_ce_int;\n wire idelay_ld;\n wire idelay_ld_done_reg_0;\n wire idelay_ld_reg_0;\n wire idelay_ld_reg_1;\n wire idelay_ld_rst;\n wire idelay_ld_rst_3;\n wire idelay_ld_rst_4;\n wire idelay_ld_rst_5;\n wire \\idelay_tap_cnt_r_reg[0][1][0] ;\n wire \\idelay_tap_cnt_r_reg[0][2][0] ;\n wire [2:0]\\idelay_tap_cnt_r_reg[0][2][0]_0 ;\n wire \\init_state_r[0]_i_56_n_0 ;\n wire \\init_state_r[4]_i_34_n_0 ;\n wire \\init_state_r_reg[0] ;\n wire \\init_state_r_reg[0]_0 ;\n wire \\init_state_r_reg[0]_1 ;\n wire \\init_state_r_reg[0]_2 ;\n wire \\init_state_r_reg[2] ;\n wire \\init_state_r_reg[3] ;\n wire \\init_state_r_reg[4] ;\n wire \\init_state_r_reg[5] ;\n wire mem_init_done_r;\n wire mpr_last_byte_done;\n wire mpr_rdlvl_done_r_reg;\n wire \\not_empty_wait_cnt[4]_i_1_n_0 ;\n wire [3:0]\\not_empty_wait_cnt_reg[0]_0 ;\n wire \\not_empty_wait_cnt_reg_n_0_[0] ;\n wire \\not_empty_wait_cnt_reg_n_0_[1] ;\n wire \\not_empty_wait_cnt_reg_n_0_[2] ;\n wire \\not_empty_wait_cnt_reg_n_0_[3] ;\n wire \\not_empty_wait_cnt_reg_n_0_[4] ;\n wire oclkdelay_calib_done_r_reg;\n wire oclkdelay_calib_done_r_reg_0;\n wire oclkdelay_center_calib_done_r_reg;\n wire [4:0]p_0_in;\n wire [3:0]p_0_in__0;\n wire p_0_out;\n wire pat_data_match_r0__0;\n wire pat_match_fall0_and_r;\n wire pat_match_fall1_and_r;\n wire pat_match_fall2_and_r;\n wire pat_match_fall3_and_r;\n wire pat_match_rise0_and_r;\n wire pat_match_rise1_and_r;\n wire pat_match_rise2_and_r;\n wire pat_match_rise3_and_r;\n wire phy_if_reset_w;\n wire phy_rddata_en_1;\n wire phy_rddata_en_r1_reg;\n wire \\po_stg2_wrcal_cnt_reg[1]_0 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_1 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_10 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_11 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_12 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_13 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_14 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_15 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_16 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_17 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_18 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_19 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_2 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_20 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_21 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_22 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_23 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_24 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_25 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_26 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_27 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_28 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_29 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_3 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_30 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_31 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_32 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_33 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_34 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_35 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_36 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_37 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_38 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_39 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_4 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_40 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_41 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_42 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_43 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_44 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_45 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_46 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_47 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_48 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_49 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_5 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_50 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_51 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_52 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_53 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_54 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_55 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_56 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_57 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_58 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_59 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_6 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_60 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_61 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_62 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_7 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_8 ;\n wire \\po_stg2_wrcal_cnt_reg[1]_9 ;\n wire \\prbs_dqs_cnt_r_reg[0] ;\n wire \\prbs_dqs_cnt_r_reg[1] ;\n wire prbs_rdlvl_done_reg;\n wire prbs_rdlvl_done_reg_rep;\n wire prbs_rdlvl_done_reg_rep_0;\n wire prech_done;\n wire prech_req_posedge_r_reg;\n wire rd_active_r1;\n wire rd_active_r2;\n wire rd_active_r3;\n wire rdlvl_stg1_done_int_reg;\n wire rdlvl_stg1_done_int_reg_0;\n wire rdlvl_stg1_start_int_reg;\n wire rstdiv0_sync_r1_reg_rep__2;\n wire rstdiv0_sync_r1_reg_rep__23;\n wire rstdiv0_sync_r1_reg_rep__4;\n wire [0:0]rstdiv0_sync_r1_reg_rep__5;\n wire rstdiv0_sync_r1_reg_rep__6;\n wire \\tap_inc_wait_cnt[3]_i_1_n_0 ;\n wire [3:0]tap_inc_wait_cnt_reg__0;\n wire wl_sm_start;\n wire wrcal_done_i_1_n_0;\n wire wrcal_done_reg_0;\n wire wrcal_done_reg_1;\n wire [2:2]wrcal_dqs_cnt_r;\n wire \\wrcal_dqs_cnt_r[0]_i_1_n_0 ;\n wire \\wrcal_dqs_cnt_r[1]_i_1_n_0 ;\n wire \\wrcal_dqs_cnt_r[2]_i_2_n_0 ;\n wire \\wrcal_dqs_cnt_r[2]_i_3_n_0 ;\n wire \\wrcal_dqs_cnt_r[2]_i_4_n_0 ;\n wire \\wrcal_dqs_cnt_r_reg_n_0_[0] ;\n wire \\wrcal_dqs_cnt_r_reg_n_0_[1] ;\n wire wrcal_pat_resume_r;\n wire wrcal_pat_resume_r2_reg_srl2_n_0;\n wire wrcal_pat_resume_r_i_3_n_0;\n wire wrcal_pat_resume_r_reg_0;\n wire wrcal_pat_resume_r_reg_1;\n wire wrcal_prech_req;\n wire wrcal_rd_wait;\n wire wrcal_resume_r;\n wire wrcal_resume_w;\n wire wrcal_sanity_chk;\n wire wrcal_sanity_chk_done_reg_0;\n wire wrcal_sanity_chk_r_reg_0;\n wire wrcal_sanity_chk_reg;\n wire wrcal_start_reg;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] ;\n wire wrlvl_byte_done;\n wire wrlvl_byte_done_r;\n wire wrlvl_byte_redo;\n wire wrlvl_byte_redo_i_3_n_0;\n wire wrlvl_byte_redo_r;\n wire wrlvl_byte_redo_reg_0;\n wire wrlvl_done_r1;\n wire wrlvl_final_mux;\n wire \\wrlvl_redo_corse_inc_reg[2] ;\n\n (* SOFT_HLUTNM = \"soft_lutpair635\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\FSM_sequential_wl_state_r[4]_i_13 \n (.I0(wrlvl_byte_redo),\n .I1(wl_sm_start),\n .O(\\FSM_sequential_wl_state_r_reg[0] ));\n LUT4 #(\n .INIT(16'hDD45)) \n \\FSM_sequential_wl_state_r[4]_i_6 \n (.I0(early1_data_reg_1),\n .I1(\\final_coarse_tap_reg[3][2] [0]),\n .I2(early2_data_reg_1),\n .I3(\\final_coarse_tap_reg[3][2] [1]),\n .O(\\wrlvl_redo_corse_inc_reg[2] ));\n LUT4 #(\n .INIT(16'h0040)) \n cal2_done_r_i_2\n (.I0(\\not_empty_wait_cnt_reg[0]_0 [3]),\n .I1(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I2(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I3(\\not_empty_wait_cnt_reg[0]_0 [0]),\n .O(cal2_done_r_reg_0));\n FDRE cal2_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrcal_sanity_chk_r_reg_0),\n .Q(cal2_done_r),\n .R(rstdiv0_sync_r1_reg_rep__5));\n LUT6 #(\n .INIT(64'h004F0040F000F000)) \n cal2_if_reset_i_2\n (.I0(phy_rddata_en_1),\n .I1(rd_active_r1),\n .I2(\\not_empty_wait_cnt_reg[0]_0 [0]),\n .I3(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I4(wrcal_done_reg_0),\n .I5(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .O(cal2_if_reset_reg_2));\n LUT6 #(\n .INIT(64'h00FF000008FF08FF)) \n cal2_if_reset_i_3\n (.I0(wrlvl_byte_done),\n .I1(rd_active_r1),\n .I2(phy_rddata_en_1),\n .I3(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I4(idelay_ld_done_reg_0),\n .I5(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .O(cal2_if_reset_reg_1));\n LUT6 #(\n .INIT(64'hFF80FFFFFF800000)) \n cal2_if_reset_i_4\n (.I0(prech_done),\n .I1(cal2_prech_req_r_i_3_n_0),\n .I2(wrcal_done_reg_0),\n .I3(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I4(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I5(cal2_if_reset_i_5_n_0),\n .O(cal2_if_reset_reg_0));\n LUT6 #(\n .INIT(64'h8000FFFF80000000)) \n cal2_if_reset_i_5\n (.I0(tap_inc_wait_cnt_reg__0[2]),\n .I1(tap_inc_wait_cnt_reg__0[0]),\n .I2(tap_inc_wait_cnt_reg__0[1]),\n .I3(tap_inc_wait_cnt_reg__0[3]),\n .I4(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I5(wrcal_start_reg),\n .O(cal2_if_reset_i_5_n_0));\n FDRE cal2_if_reset_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\cal2_state_r_reg[0]_1 ),\n .Q(phy_if_reset_w),\n .R(rstdiv0_sync_r1_reg_rep__4));\n LUT6 #(\n .INIT(64'h0000000010110000)) \n cal2_prech_req_r_i_2\n (.I0(\\not_empty_wait_cnt_reg[0]_0 [3]),\n .I1(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I2(cal2_prech_req_r_i_3_n_0),\n .I3(wrcal_done_reg_0),\n .I4(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I5(\\not_empty_wait_cnt_reg[0]_0 [0]),\n .O(cal2_prech_req_r_i_2_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair634\" *) \n LUT3 #(\n .INIT(8'h08)) \n cal2_prech_req_r_i_3\n (.I0(\\wrcal_dqs_cnt_r_reg_n_0_[1] ),\n .I1(\\wrcal_dqs_cnt_r_reg_n_0_[0] ),\n .I2(wrcal_dqs_cnt_r),\n .O(cal2_prech_req_r_i_3_n_0));\n FDRE cal2_prech_req_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cal2_prech_req_r_i_2_n_0),\n .Q(cal2_prech_req_r),\n .R(rstdiv0_sync_r1_reg_rep__4));\n LUT6 #(\n .INIT(64'h00000000E2FFE200)) \n \\cal2_state_r[0]_i_1 \n (.I0(\\cal2_state_r[0]_i_2_n_0 ),\n .I1(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I2(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I3(\\not_empty_wait_cnt_reg[0]_0 [0]),\n .I4(\\cal2_state_r[0]_i_3_n_0 ),\n .I5(\\not_empty_wait_cnt_reg[0]_0 [3]),\n .O(\\cal2_state_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hBBB8BBBB88888888)) \n \\cal2_state_r[0]_i_2 \n (.I0(tap_inc_wait_cnt_reg__0[0]),\n .I1(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I2(early2_data_reg_0),\n .I3(early1_data_reg_0),\n .I4(wrcal_pat_resume_r_reg_0),\n .I5(\\cal2_state_r[0]_i_4_n_0 ),\n .O(\\cal2_state_r[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h000F0000DFDFDFDF)) \n \\cal2_state_r[0]_i_3 \n (.I0(prech_done),\n .I1(\\cal2_state_r[0]_i_5_n_0 ),\n .I2(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I3(wrcal_done_reg_0),\n .I4(wrcal_pat_resume_r_reg_0),\n .I5(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .O(\\cal2_state_r[0]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair618\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\cal2_state_r[0]_i_4 \n (.I0(\\gen_pat_match_div4.pat_data_match_r_reg_n_0 ),\n .I1(idelay_ld_reg_0),\n .I2(wrcal_done_reg_0),\n .O(\\cal2_state_r[0]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair617\" *) \n LUT3 #(\n .INIT(8'hF7)) \n \\cal2_state_r[0]_i_5 \n (.I0(\\wrcal_dqs_cnt_r_reg_n_0_[1] ),\n .I1(\\wrcal_dqs_cnt_r_reg_n_0_[0] ),\n .I2(wrcal_dqs_cnt_r),\n .O(\\cal2_state_r[0]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h00E2FFFF00E20000)) \n \\cal2_state_r[1]_i_1 \n (.I0(\\cal2_state_r[1]_i_2_n_0 ),\n .I1(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I2(tap_inc_wait_cnt_reg__0[1]),\n .I3(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I4(\\not_empty_wait_cnt_reg[0]_0 [0]),\n .I5(\\cal2_state_r[1]_i_3_n_0 ),\n .O(\\cal2_state_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair618\" *) \n LUT5 #(\n .INIT(32'hFF003200)) \n \\cal2_state_r[1]_i_2 \n (.I0(early2_data_reg_0),\n .I1(wrcal_done_reg_0),\n .I2(early1_data_reg_0),\n .I3(idelay_ld_reg_0),\n .I4(\\gen_pat_match_div4.pat_data_match_r_reg_n_0 ),\n .O(\\cal2_state_r[1]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair619\" *) \n LUT5 #(\n .INIT(32'h0F0050D0)) \n \\cal2_state_r[1]_i_3 \n (.I0(prech_done),\n .I1(cal2_prech_req_r_i_3_n_0),\n .I2(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I3(wrcal_done_reg_0),\n .I4(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .O(\\cal2_state_r[1]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h4F4AFFFF4F4A0000)) \n \\cal2_state_r[2]_i_1 \n (.I0(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I1(tap_inc_wait_cnt_reg__0[2]),\n .I2(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I3(\\cal2_state_r[2]_i_2_n_0 ),\n .I4(\\not_empty_wait_cnt_reg[0]_0 [0]),\n .I5(\\cal2_state_r[2]_i_3_n_0 ),\n .O(\\cal2_state_r[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000010)) \n \\cal2_state_r[2]_i_2 \n (.I0(early2_data_reg_0),\n .I1(wrcal_done_reg_0),\n .I2(idelay_ld_reg_0),\n .I3(\\gen_pat_match_div4.pat_data_match_r_reg_n_0 ),\n .I4(early1_data_reg_0),\n .I5(wrcal_pat_resume_r_reg_0),\n .O(\\cal2_state_r[2]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair619\" *) \n LUT5 #(\n .INIT(32'h0F00D0D0)) \n \\cal2_state_r[2]_i_3 \n (.I0(prech_done),\n .I1(cal2_prech_req_r_i_3_n_0),\n .I2(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I3(wrcal_done_reg_0),\n .I4(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .O(\\cal2_state_r[2]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair615\" *) \n LUT4 #(\n .INIT(16'h8000)) \n \\cal2_state_r[3]_i_11 \n (.I0(\\not_empty_wait_cnt_reg_n_0_[2] ),\n .I1(\\not_empty_wait_cnt_reg_n_0_[1] ),\n .I2(\\not_empty_wait_cnt_reg_n_0_[0] ),\n .I3(\\not_empty_wait_cnt_reg_n_0_[3] ),\n .O(\\cal2_state_r[3]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'h00E2FFFF00E20000)) \n \\cal2_state_r[3]_i_3 \n (.I0(\\cal2_state_r[3]_i_6_n_0 ),\n .I1(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I2(tap_inc_wait_cnt_reg__0[3]),\n .I3(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I4(\\not_empty_wait_cnt_reg[0]_0 [0]),\n .I5(\\not_empty_wait_cnt_reg[0]_0 [3]),\n .O(\\cal2_state_r[3]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h45404F4F45404A4A)) \n \\cal2_state_r[3]_i_4 \n (.I0(\\not_empty_wait_cnt_reg[0]_0 [3]),\n .I1(\\cal2_state_r[3]_i_7_n_0 ),\n .I2(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I3(\\cal2_state_r[3]_i_8_n_0 ),\n .I4(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I5(wrcal_start_reg),\n .O(\\cal2_state_r[3]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h00000000EEE222E2)) \n \\cal2_state_r[3]_i_5 \n (.I0(\\cal2_state_r[3]_i_9_n_0 ),\n .I1(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I2(phy_rddata_en_r1_reg),\n .I3(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I4(\\cal2_state_r[3]_i_8_n_0 ),\n .I5(\\not_empty_wait_cnt_reg[0]_0 [3]),\n .O(\\cal2_state_r[3]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h00FF0010FFFFFFFF)) \n \\cal2_state_r[3]_i_6 \n (.I0(early2_data_reg_0),\n .I1(early1_data_reg_0),\n .I2(wrcal_pat_resume_r_reg_0),\n .I3(\\gen_pat_match_div4.pat_data_match_r_reg_n_0 ),\n .I4(wrcal_done_reg_0),\n .I5(idelay_ld_reg_0),\n .O(\\cal2_state_r[3]_i_6_n_0 ));\n LUT5 #(\n .INIT(32'h3B3B3808)) \n \\cal2_state_r[3]_i_7 \n (.I0(wrcal_sanity_chk),\n .I1(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I2(wrcal_done_reg_0),\n .I3(\\cal2_state_r[0]_i_5_n_0 ),\n .I4(prech_done),\n .O(\\cal2_state_r[3]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair630\" *) \n LUT4 #(\n .INIT(16'h8000)) \n \\cal2_state_r[3]_i_8 \n (.I0(tap_inc_wait_cnt_reg__0[2]),\n .I1(tap_inc_wait_cnt_reg__0[0]),\n .I2(tap_inc_wait_cnt_reg__0[1]),\n .I3(tap_inc_wait_cnt_reg__0[3]),\n .O(\\cal2_state_r[3]_i_8_n_0 ));\n LUT5 #(\n .INIT(32'hBBBBB888)) \n \\cal2_state_r[3]_i_9 \n (.I0(idelay_ld_done_reg_0),\n .I1(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I2(\\cal2_state_r[3]_i_11_n_0 ),\n .I3(\\not_empty_wait_cnt_reg_n_0_[4] ),\n .I4(idelay_ld_reg_0),\n .O(\\cal2_state_r[3]_i_9_n_0 ));\n FDRE \\cal2_state_r_reg[0] \n (.C(CLK),\n .CE(cal2_state_r),\n .D(\\cal2_state_r[0]_i_1_n_0 ),\n .Q(\\not_empty_wait_cnt_reg[0]_0 [0]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\cal2_state_r_reg[1] \n (.C(CLK),\n .CE(cal2_state_r),\n .D(\\cal2_state_r[1]_i_1_n_0 ),\n .Q(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\cal2_state_r_reg[2] \n (.C(CLK),\n .CE(cal2_state_r),\n .D(\\cal2_state_r[2]_i_1_n_0 ),\n .Q(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n FDRE \\cal2_state_r_reg[3] \n (.C(CLK),\n .CE(cal2_state_r),\n .D(\\cal2_state_r[3]_i_3_n_0 ),\n .Q(\\not_empty_wait_cnt_reg[0]_0 [3]),\n .R(rstdiv0_sync_r1_reg_rep__5));\n MUXF7 \\cal2_state_r_reg[3]_i_2 \n (.I0(\\cal2_state_r[3]_i_4_n_0 ),\n .I1(\\cal2_state_r[3]_i_5_n_0 ),\n .O(cal2_state_r),\n .S(\\not_empty_wait_cnt_reg[0]_0 [0]));\n LUT2 #(\n .INIT(4'h1)) \n \\corse_cnt[0][2]_i_11 \n (.I0(\\idelay_tap_cnt_r_reg[0][2][0]_0 [0]),\n .I1(\\idelay_tap_cnt_r_reg[0][2][0]_0 [2]),\n .O(\\corse_cnt_reg[0][2] ));\n (* SOFT_HLUTNM = \"soft_lutpair625\" *) \n LUT4 #(\n .INIT(16'hFBFF)) \n \\corse_cnt[1][2]_i_5 \n (.I0(\\idelay_tap_cnt_r_reg[0][2][0]_0 [2]),\n .I1(wrlvl_byte_redo),\n .I2(wrlvl_byte_redo_r),\n .I3(\\idelay_tap_cnt_r_reg[0][2][0]_0 [0]),\n .O(\\corse_cnt_reg[1][2] ));\n (* SOFT_HLUTNM = \"soft_lutpair635\" *) \n LUT3 #(\n .INIT(8'hDF)) \n \\corse_cnt[2][2]_i_5 \n (.I0(\\idelay_tap_cnt_r_reg[0][2][0]_0 [1]),\n .I1(wrlvl_byte_redo_r),\n .I2(wrlvl_byte_redo),\n .O(\\corse_cnt_reg[2][2] ));\n LUT5 #(\n .INIT(32'h45400000)) \n early1_data_i_2\n (.I0(\\not_empty_wait_cnt_reg[0]_0 [3]),\n .I1(early1_data_i_3_n_0),\n .I2(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I3(wrlvl_byte_redo_i_3_n_0),\n .I4(\\not_empty_wait_cnt_reg[0]_0 [0]),\n .O(early1_data_reg_2));\n LUT4 #(\n .INIT(16'h0008)) \n early1_data_i_3\n (.I0(wrlvl_byte_done),\n .I1(rd_active_r1),\n .I2(phy_rddata_en_1),\n .I3(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .O(early1_data_i_3_n_0));\n FDRE early1_data_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early1_data_match_r_reg_0 ),\n .Q(early1_data_reg_1),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE early2_data_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early1_data_match_r_reg_1 ),\n .Q(early2_data_reg_1),\n .R(rstdiv0_sync_r1_reg_rep__6));\n LUT6 #(\n .INIT(64'h0CAA000000AA0000)) \n \\gen_byte_sel_div1.byte_sel_cnt[0]_i_3 \n (.I0(\\idelay_tap_cnt_r_reg[0][2][0]_0 [0]),\n .I1(rdlvl_stg1_done_int_reg),\n .I2(prbs_rdlvl_done_reg),\n .I3(wrcal_done_reg_1),\n .I4(oclkdelay_calib_done_r_reg),\n .I5(\\prbs_dqs_cnt_r_reg[0] ),\n .O(\\gen_byte_sel_div1.byte_sel_cnt_reg[0] ));\n LUT6 #(\n .INIT(64'h0CAA000000AA0000)) \n \\gen_byte_sel_div1.byte_sel_cnt[1]_i_3 \n (.I0(\\idelay_tap_cnt_r_reg[0][2][0]_0 [1]),\n .I1(rdlvl_stg1_done_int_reg),\n .I2(prbs_rdlvl_done_reg),\n .I3(wrcal_done_reg_1),\n .I4(oclkdelay_calib_done_r_reg),\n .I5(\\prbs_dqs_cnt_r_reg[1] ),\n .O(\\gen_byte_sel_div1.byte_sel_cnt_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair632\" *) \n LUT4 #(\n .INIT(16'h0800)) \n \\gen_byte_sel_div1.byte_sel_cnt[2]_i_6 \n (.I0(\\idelay_tap_cnt_r_reg[0][2][0]_0 [2]),\n .I1(mpr_rdlvl_done_r_reg),\n .I2(wrcal_done_reg_1),\n .I3(oclkdelay_calib_done_r_reg),\n .O(\\gen_byte_sel_div1.byte_sel_cnt_reg[2] ));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_19 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_55 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_33 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_11 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_47 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_out),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_41 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_20 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_56 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_34 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_12 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_48 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_4 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_27 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_42 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_21 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_57 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_35 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_13 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_49 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_5 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_28 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_43 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_22 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_58 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_36 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_14 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_50 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_6 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_29 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_23 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_59 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_37 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_15 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_51 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_7 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_44 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_24 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_60 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_38 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_16 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_52 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_8 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_30 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_45 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_25 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_61 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_39 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_17 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_53 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_9 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_31 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_46 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_26 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_62 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_40 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_18 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_54 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_10 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ),\n .R(1'b0));\n FDRE \\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\po_stg2_wrcal_cnt_reg[1]_32 ),\n .Q(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_pat_match_div4.early1_data_match_r_i_1 \n (.I0(early1_match_rise2_and_r),\n .I1(early1_match_rise3_and_r),\n .I2(early1_match_fall1_and_r),\n .I3(early1_match_rise1_and_r),\n .I4(\\gen_pat_match_div4.early1_data_match_r_i_2_n_0 ),\n .O(early1_data_match_r0__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_pat_match_div4.early1_data_match_r_i_2 \n (.I0(early1_match_rise0_and_r),\n .I1(early1_match_fall3_and_r),\n .I2(early1_match_fall0_and_r),\n .I3(early1_match_fall2_and_r),\n .O(\\gen_pat_match_div4.early1_data_match_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.early1_data_match_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(early1_data_match_r0__0),\n .Q(early1_data_reg_0),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_pat_match_div4.early1_match_fall0_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[0].early1_match_fall0_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[6].early1_match_fall0_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[2].early1_match_fall0_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[4].early1_match_fall0_r_reg ),\n .I4(\\gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0 ),\n .O(\\gen_pat_match_div4.early1_match_fall0_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_pat_match_div4.early1_match_fall0_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r_reg ),\n .O(\\gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.early1_match_fall0_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early1_match_fall0_and_r_i_1_n_0 ),\n .Q(early1_match_fall0_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.early1_match_fall1_and_r_i_1 \n (.I0(\\gen_pat_match_div4.early1_match_fall1_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg__0 ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg__0 ),\n .I3(\\gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg ),\n .O(\\gen_pat_match_div4.early1_match_fall1_and_r_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair616\" *) \n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.early1_match_fall1_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].early1_match_fall1_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].early1_match_fall1_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r_reg ),\n .O(\\gen_pat_match_div4.early1_match_fall1_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.early1_match_fall1_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early1_match_fall1_and_r_i_1_n_0 ),\n .Q(early1_match_fall1_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.early1_match_fall2_and_r_i_1 \n (.I0(\\gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r_reg ),\n .O(\\gen_pat_match_div4.early1_match_fall2_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.early1_match_fall2_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg ),\n .O(\\gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.early1_match_fall2_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early1_match_fall2_and_r_i_1_n_0 ),\n .Q(early1_match_fall2_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.early1_match_fall3_and_r_i_1 \n (.I0(\\gen_pat_match_div4.early1_match_fall3_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg__0 ),\n .I3(\\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg__0 ),\n .I4(\\gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg ),\n .O(\\gen_pat_match_div4.early1_match_fall3_and_r_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair622\" *) \n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.early1_match_fall3_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg ),\n .O(\\gen_pat_match_div4.early1_match_fall3_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.early1_match_fall3_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early1_match_fall3_and_r_i_1_n_0 ),\n .Q(early1_match_fall3_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_pat_match_div4.early1_match_rise0_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r_reg__0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r_reg__0 ),\n .I2(\\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r_reg__0 ),\n .I3(\\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r_reg__0 ),\n .I4(\\gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0 ),\n .O(\\gen_pat_match_div4.early1_match_rise0_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_pat_match_div4.early1_match_rise0_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise0_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].pat_match_rise0_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].pat_match_rise0_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise0_r_reg ),\n .O(\\gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.early1_match_rise0_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early1_match_rise0_and_r_i_1_n_0 ),\n .Q(early1_match_rise0_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.early1_match_rise1_and_r_i_1 \n (.I0(\\gen_pat_match_div4.early1_match_rise1_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg__0 ),\n .I4(\\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg__0 ),\n .O(\\gen_pat_match_div4.early1_match_rise1_and_r_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair624\" *) \n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.early1_match_rise1_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[4].early1_match_rise1_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[0].early1_match_rise1_r_reg ),\n .O(\\gen_pat_match_div4.early1_match_rise1_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.early1_match_rise1_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early1_match_rise1_and_r_i_1_n_0 ),\n .Q(early1_match_rise1_and_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair620\" *) \n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.early1_match_rise2_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[3].early1_match_rise2_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[7].early1_match_rise2_r_reg ),\n .I4(\\gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0 ),\n .O(\\gen_pat_match_div4.early1_match_rise2_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.early1_match_rise2_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg ),\n .O(\\gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.early1_match_rise2_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early1_match_rise2_and_r_i_1_n_0 ),\n .Q(early1_match_rise2_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.early1_match_rise3_and_r_i_1 \n (.I0(\\gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].early1_match_rise3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].early1_match_rise3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg ),\n .O(\\gen_pat_match_div4.early1_match_rise3_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.early1_match_rise3_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg ),\n .O(\\gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.early1_match_rise3_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early1_match_rise3_and_r_i_1_n_0 ),\n .Q(early1_match_rise3_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_pat_match_div4.early2_data_match_r_i_1 \n (.I0(early2_match_fall0_and_r),\n .I1(early2_match_rise2_and_r),\n .I2(early2_match_fall3_and_r),\n .I3(early2_match_rise1_and_r),\n .I4(\\gen_pat_match_div4.early2_data_match_r_i_2_n_0 ),\n .O(early2_data_match_r0__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_pat_match_div4.early2_data_match_r_i_2 \n (.I0(early2_match_rise3_and_r),\n .I1(early2_match_fall2_and_r),\n .I2(early2_match_fall1_and_r),\n .I3(early2_match_rise0_and_r),\n .O(\\gen_pat_match_div4.early2_data_match_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.early2_data_match_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(early2_data_match_r0__0),\n .Q(early2_data_reg_0),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.early2_match_fall0_and_r_i_1 \n (.I0(\\gen_pat_match_div4.early2_match_fall0_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].early2_match_fall0_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[7].early2_match_fall0_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[3].early2_match_fall0_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[5].early2_match_fall0_r_reg ),\n .O(\\gen_pat_match_div4.early2_match_fall0_and_r_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair621\" *) \n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.early2_match_fall0_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r_reg ),\n .O(\\gen_pat_match_div4.early2_match_fall0_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.early2_match_fall0_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early2_match_fall0_and_r_i_1_n_0 ),\n .Q(early2_match_fall0_and_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair616\" *) \n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.early2_match_fall1_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[5].early1_match_fall1_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[1].early1_match_fall1_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r_reg ),\n .I4(\\gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0 ),\n .O(\\gen_pat_match_div4.early2_match_fall1_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.early2_match_fall1_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].pat_match_fall1_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[2].pat_match_fall1_r_reg ),\n .O(\\gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.early2_match_fall1_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early2_match_fall1_and_r_i_1_n_0 ),\n .Q(early2_match_fall1_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_pat_match_div4.early2_match_fall2_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r_reg__0 ),\n .I2(\\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[4].early2_match_fall2_r_reg ),\n .I4(\\gen_pat_match_div4.early2_match_fall2_and_r_i_2_n_0 ),\n .O(\\gen_pat_match_div4.early2_match_fall2_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_pat_match_div4.early2_match_fall2_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r_reg__0 ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[0].early2_match_fall2_r_reg ),\n .O(\\gen_pat_match_div4.early2_match_fall2_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.early2_match_fall2_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early2_match_fall2_and_r_i_1_n_0 ),\n .Q(early2_match_fall2_and_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair622\" *) \n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.early2_match_fall3_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r_reg ),\n .I4(\\gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0 ),\n .O(\\gen_pat_match_div4.early2_match_fall3_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.early2_match_fall3_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[2].pat_match_fall3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[6].pat_match_fall3_r_reg ),\n .O(\\gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.early2_match_fall3_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early2_match_fall3_and_r_i_1_n_0 ),\n .Q(early2_match_fall3_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.early2_match_rise0_and_r_i_1 \n (.I0(\\gen_pat_match_div4.early2_match_rise0_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r_reg__0 ),\n .I2(\\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r_reg__0 ),\n .I3(\\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r_reg__0 ),\n .I4(\\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r_reg__0 ),\n .O(\\gen_pat_match_div4.early2_match_rise0_and_r_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair614\" *) \n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.early2_match_rise0_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise0_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[2].pat_match_rise0_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].pat_match_rise0_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise0_r_reg ),\n .O(\\gen_pat_match_div4.early2_match_rise0_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.early2_match_rise0_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early2_match_rise0_and_r_i_1_n_0 ),\n .Q(early2_match_rise0_and_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair624\" *) \n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.early2_match_rise1_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[0].early1_match_rise1_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[4].early1_match_rise1_r_reg ),\n .I4(\\gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0 ),\n .O(\\gen_pat_match_div4.early2_match_rise1_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.early2_match_rise1_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise1_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise1_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r_reg ),\n .O(\\gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.early2_match_rise1_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early2_match_rise1_and_r_i_1_n_0 ),\n .Q(early2_match_rise1_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.early2_match_rise2_and_r_i_1 \n (.I0(\\gen_pat_match_div4.early2_match_rise2_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[1].early2_match_rise2_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[5].early2_match_rise2_r_reg ),\n .O(\\gen_pat_match_div4.early2_match_rise2_and_r_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair620\" *) \n LUT4 #(\n .INIT(16'h8000)) \n \\gen_pat_match_div4.early2_match_rise2_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[7].early1_match_rise2_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[3].early1_match_rise2_r_reg ),\n .O(\\gen_pat_match_div4.early2_match_rise2_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.early2_match_rise2_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early2_match_rise2_and_r_i_1_n_0 ),\n .Q(early2_match_rise2_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_pat_match_div4.early2_match_rise3_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[2].early2_match_rise3_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].early1_match_rise3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r_reg__0 ),\n .I4(\\gen_pat_match_div4.early2_match_rise3_and_r_i_2_n_0 ),\n .O(\\gen_pat_match_div4.early2_match_rise3_and_r_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_pat_match_div4.early2_match_rise3_and_r_i_2 \n (.I0(\\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r_reg__0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].early1_match_rise3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[6].early2_match_rise3_r_reg ),\n .O(\\gen_pat_match_div4.early2_match_rise3_and_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.early2_match_rise3_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early2_match_rise3_and_r_i_1_n_0 ),\n .Q(early2_match_rise3_and_r),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[0].early1_match_fall0_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].early1_match_fall0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[0].early1_match_rise1_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].early1_match_rise1_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[0].early2_match_fall2_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].early2_match_fall2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise0_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[1].early1_match_fall1_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].early1_match_fall1_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[1].early1_match_rise3_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].early1_match_rise3_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[1].early2_match_fall0_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].early2_match_fall0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[1].early2_match_rise2_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].early2_match_rise2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[1].pat_match_rise0_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].pat_match_rise0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[2].early1_match_fall0_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].early1_match_fall0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[2].early2_match_rise3_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].early2_match_rise3_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[2].pat_match_fall1_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].pat_match_fall1_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[2].pat_match_fall3_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].pat_match_fall3_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[2].pat_match_rise0_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].pat_match_rise0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[3].early1_match_rise2_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].early1_match_rise2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[3].early2_match_fall0_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].early2_match_fall0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise0_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise1_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise1_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[4].early1_match_fall0_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].early1_match_fall0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[4].early1_match_rise1_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].early1_match_rise1_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[4].early2_match_fall2_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].early2_match_fall2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise0_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[5].early1_match_fall1_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].early1_match_fall1_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[5].early1_match_rise3_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].early1_match_rise3_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[5].early2_match_fall0_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].early2_match_fall0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[5].early2_match_rise2_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].early2_match_rise2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[5].pat_match_rise0_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].pat_match_rise0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[6].early1_match_fall0_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].early1_match_fall0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[6].early2_match_rise3_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].early2_match_rise3_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[6].pat_match_fall1_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].pat_match_fall1_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[6].pat_match_fall3_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].pat_match_fall3_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[6].pat_match_rise0_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].pat_match_rise0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[7].early1_match_rise2_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].early1_match_rise2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[7].early2_match_fall0_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].early2_match_fall0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise0_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise0_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise1_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise1_r_reg ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7][0]_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg__0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2_n_0 ),\n .Q(\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg ),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_pat_match_div4.pat_data_match_r_i_1 \n (.I0(pat_match_rise0_and_r),\n .I1(pat_match_rise3_and_r),\n .I2(pat_match_fall2_and_r),\n .I3(pat_match_fall3_and_r),\n .I4(\\gen_pat_match_div4.pat_data_match_r_i_2_n_0 ),\n .O(pat_data_match_r0__0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\gen_pat_match_div4.pat_data_match_r_i_2 \n (.I0(pat_match_fall0_and_r),\n .I1(pat_match_rise2_and_r),\n .I2(pat_match_rise1_and_r),\n .I3(pat_match_fall1_and_r),\n .O(\\gen_pat_match_div4.pat_data_match_r_i_2_n_0 ));\n FDRE \\gen_pat_match_div4.pat_data_match_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(pat_data_match_r0__0),\n .Q(\\gen_pat_match_div4.pat_data_match_r_reg_n_0 ),\n .R(1'b0));\n FDRE \\gen_pat_match_div4.pat_data_match_valid_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(rd_active_r3),\n .Q(idelay_ld_reg_0),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair621\" *) \n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_pat_match_div4.pat_match_fall0_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r_reg ),\n .I4(\\gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0 ),\n .O(\\gen_pat_match_div4.pat_match_fall0_and_r_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.pat_match_fall0_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat_match_fall0_and_r_i_1_n_0 ),\n .Q(pat_match_fall0_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.pat_match_fall1_and_r_i_1 \n (.I0(\\gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg__0 ),\n .I3(\\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg__0 ),\n .I4(\\gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg ),\n .O(\\gen_pat_match_div4.pat_match_fall1_and_r_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.pat_match_fall1_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat_match_fall1_and_r_i_1_n_0 ),\n .Q(pat_match_fall1_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.pat_match_fall2_and_r_i_1 \n (.I0(\\gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r_reg ),\n .O(\\gen_pat_match_div4.pat_match_fall2_and_r_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.pat_match_fall2_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat_match_fall2_and_r_i_1_n_0 ),\n .Q(pat_match_fall2_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.pat_match_fall3_and_r_i_1 \n (.I0(\\gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg ),\n .O(\\gen_pat_match_div4.pat_match_fall3_and_r_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.pat_match_fall3_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat_match_fall3_and_r_i_1_n_0 ),\n .Q(pat_match_fall3_and_r),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair614\" *) \n LUT5 #(\n .INIT(32'h00008000)) \n \\gen_pat_match_div4.pat_match_rise0_and_r_i_1 \n (.I0(\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise0_r_reg ),\n .I1(\\gen_pat_match_div4.gen_pat_match[6].pat_match_rise0_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[2].pat_match_rise0_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise0_r_reg ),\n .I4(\\gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0 ),\n .O(\\gen_pat_match_div4.pat_match_rise0_and_r_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.pat_match_rise0_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat_match_rise0_and_r_i_1_n_0 ),\n .Q(pat_match_rise0_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.pat_match_rise1_and_r_i_1 \n (.I0(\\gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg__0 ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg__0 ),\n .O(\\gen_pat_match_div4.pat_match_rise1_and_r_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.pat_match_rise1_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat_match_rise1_and_r_i_1_n_0 ),\n .Q(pat_match_rise1_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.pat_match_rise2_and_r_i_1 \n (.I0(\\gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg ),\n .I2(\\gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg ),\n .I3(\\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg__0 ),\n .I4(\\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg__0 ),\n .O(\\gen_pat_match_div4.pat_match_rise2_and_r_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.pat_match_rise2_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat_match_rise2_and_r_i_1_n_0 ),\n .Q(pat_match_rise2_and_r),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h80000000)) \n \\gen_pat_match_div4.pat_match_rise3_and_r_i_1 \n (.I0(\\gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0 ),\n .I1(\\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg__0 ),\n .I2(\\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg__0 ),\n .I3(\\gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg ),\n .I4(\\gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg ),\n .O(\\gen_pat_match_div4.pat_match_rise3_and_r_i_1_n_0 ));\n FDRE \\gen_pat_match_div4.pat_match_rise3_and_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat_match_rise3_and_r_i_1_n_0 ),\n .Q(pat_match_rise3_and_r),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ),\n .Q(\\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_213 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ),\n .Q(\\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_249 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ),\n .Q(\\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_227 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ),\n .Q(\\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_205 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ),\n .Q(\\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_241 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ),\n .Q(\\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_197 ),\n .R(1'b0));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2 \" *) \n SRL16E \\gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2 \n (.A0(1'b1),\n .A1(1'b0),\n .A2(1'b0),\n .A3(1'b0),\n .CE(1'b1),\n .CLK(CLK),\n .D(\\po_stg2_wrcal_cnt_reg[1]_0 ),\n .Q(\\gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2_n_0 ));\n FDRE \\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ),\n .Q(\\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_235 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ),\n .Q(\\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_214 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ),\n .Q(\\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_250 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ),\n .Q(\\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_228 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ),\n .Q(\\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_206 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ),\n .Q(\\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_242 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ),\n .Q(\\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_198 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ),\n .Q(\\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_221 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ),\n .Q(\\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_236 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ),\n .Q(\\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_215 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ),\n .Q(\\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_251 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ),\n .Q(\\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_229 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ),\n .Q(\\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_207 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ),\n .Q(\\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_243 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ),\n .Q(\\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_199 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ),\n .Q(\\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_222 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ),\n .Q(\\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_237 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ),\n .Q(\\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_216 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ),\n .Q(\\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_252 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ),\n .Q(\\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_230 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ),\n .Q(\\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_208 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ),\n .Q(\\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_244 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ),\n .Q(\\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_200 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ),\n .Q(\\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_223 ),\n .R(1'b0));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2 \" *) \n SRL16E \\gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2 \n (.A0(1'b1),\n .A1(1'b0),\n .A2(1'b0),\n .A3(1'b0),\n .CE(1'b1),\n .CLK(CLK),\n .D(\\po_stg2_wrcal_cnt_reg[1]_2 ),\n .Q(\\gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2_n_0 ));\n FDRE \\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ),\n .Q(\\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_217 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ),\n .Q(\\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_253 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ),\n .Q(\\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_231 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ),\n .Q(\\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_209 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ),\n .Q(\\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_245 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ),\n .Q(\\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_201 ),\n .R(1'b0));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2 \" *) \n SRL16E \\gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2 \n (.A0(1'b1),\n .A1(1'b0),\n .A2(1'b0),\n .A3(1'b0),\n .CE(1'b1),\n .CLK(CLK),\n .D(\\po_stg2_wrcal_cnt_reg[1]_1 ),\n .Q(\\gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2_n_0 ));\n FDRE \\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ),\n .Q(\\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_238 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ),\n .Q(\\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_218 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ),\n .Q(\\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_254 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ),\n .Q(\\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_232 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ),\n .Q(\\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_210 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ),\n .Q(\\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_246 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ),\n .Q(\\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_202 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ),\n .Q(\\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_224 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ),\n .Q(\\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_239 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ),\n .Q(\\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_219 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ),\n .Q(\\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_255 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ),\n .Q(\\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_233 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ),\n .Q(\\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_211 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ),\n .Q(\\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_247 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ),\n .Q(\\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_203 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ),\n .Q(\\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_225 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ),\n .Q(\\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_240 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ),\n .Q(\\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_220 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ),\n .Q(\\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_256 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ),\n .Q(\\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_234 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ),\n .Q(\\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_212 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ),\n .Q(\\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_248 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ),\n .Q(\\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_204 ),\n .R(1'b0));\n FDRE \\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ),\n .Q(\\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_226 ),\n .R(1'b0));\n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7] \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2 \" *) \n SRL16E \\gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2 \n (.A0(1'b1),\n .A1(1'b0),\n .A2(1'b0),\n .A3(1'b0),\n .CE(1'b1),\n .CLK(CLK),\n .D(\\po_stg2_wrcal_cnt_reg[1]_3 ),\n .Q(\\gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair628\" *) \n LUT4 #(\n .INIT(16'h0002)) \n idelay_ld_done_i_2\n (.I0(tap_inc_wait_cnt_reg__0[2]),\n .I1(tap_inc_wait_cnt_reg__0[0]),\n .I2(tap_inc_wait_cnt_reg__0[1]),\n .I3(tap_inc_wait_cnt_reg__0[3]),\n .O(idelay_ld_done_reg_0));\n FDRE idelay_ld_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\cal2_state_r_reg[0]_0 ),\n .Q(wrcal_pat_resume_r_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__5));\n LUT6 #(\n .INIT(64'h0000540400000000)) \n idelay_ld_i_2\n (.I0(\\not_empty_wait_cnt_reg[0]_0 [3]),\n .I1(\\cal2_state_r[2]_i_2_n_0 ),\n .I2(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I3(idelay_ld_done_reg_0),\n .I4(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I5(\\not_empty_wait_cnt_reg[0]_0 [0]),\n .O(idelay_ld_reg_1));\n FDRE idelay_ld_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.pat_data_match_valid_r_reg_0 ),\n .Q(idelay_ld),\n .R(rstdiv0_sync_r1_reg_rep__4));\n (* SOFT_HLUTNM = \"soft_lutpair627\" *) \n LUT4 #(\n .INIT(16'hFFEF)) \n \\idelay_tap_cnt_r[0][0][4]_i_3 \n (.I0(\\idelay_tap_cnt_r_reg[0][2][0]_0 [0]),\n .I1(idelay_ce_int),\n .I2(idelay_ld),\n .I3(\\idelay_tap_cnt_r_reg[0][2][0]_0 [2]),\n .O(\\idelay_tap_cnt_r_reg[0][2][0] ));\n (* SOFT_HLUTNM = \"soft_lutpair627\" *) \n LUT4 #(\n .INIT(16'hFBFF)) \n \\idelay_tap_cnt_r[0][1][4]_i_2 \n (.I0(idelay_ce_int),\n .I1(idelay_ld),\n .I2(\\idelay_tap_cnt_r_reg[0][2][0]_0 [2]),\n .I3(\\idelay_tap_cnt_r_reg[0][2][0]_0 [0]),\n .O(\\idelay_tap_cnt_r_reg[0][1][0] ));\n LUT6 #(\n .INIT(64'h5555555545555555)) \n \\init_state_r[0]_i_12 \n (.I0(wrcal_sanity_chk_done_reg_0),\n .I1(prbs_rdlvl_done_reg_rep_0),\n .I2(wrlvl_done_r1),\n .I3(dqs_found_done_r_reg),\n .I4(wrcal_done_reg_1),\n .I5(ddr3_lm_done_r),\n .O(\\init_state_r_reg[0]_2 ));\n LUT6 #(\n .INIT(64'h5700575757575757)) \n \\init_state_r[0]_i_36 \n (.I0(oclkdelay_calib_done_r_reg_0),\n .I1(wrlvl_final_mux),\n .I2(wrlvl_byte_redo),\n .I3(mem_init_done_r),\n .I4(\\init_state_r_reg[2] ),\n .I5(dqs_found_done_r_reg_0),\n .O(\\init_state_r_reg[0] ));\n LUT6 #(\n .INIT(64'h00D000D000D0FFFF)) \n \\init_state_r[0]_i_55 \n (.I0(prbs_rdlvl_done_reg_rep),\n .I1(\\init_state_r[0]_i_56_n_0 ),\n .I2(wrlvl_done_r1),\n .I3(wrlvl_byte_redo),\n .I4(rdlvl_stg1_done_int_reg_0),\n .I5(dqs_found_done_r_reg),\n .O(\\init_state_r_reg[0]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair626\" *) \n LUT2 #(\n .INIT(4'h7)) \n \\init_state_r[0]_i_56 \n (.I0(wrcal_done_reg_1),\n .I1(rdlvl_stg1_done_int_reg),\n .O(\\init_state_r[0]_i_56_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair629\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\init_state_r[2]_i_23 \n (.I0(wrcal_done_reg_1),\n .I1(prech_req_posedge_r_reg),\n .I2(wrlvl_byte_redo),\n .I3(wrcal_resume_r),\n .O(\\init_state_r_reg[0]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair626\" *) \n LUT4 #(\n .INIT(16'hB0BB)) \n \\init_state_r[2]_i_29 \n (.I0(wrlvl_done_r1),\n .I1(wrlvl_final_mux),\n .I2(wrcal_done_reg_1),\n .I3(wrlvl_byte_redo),\n .O(\\init_state_r_reg[2] ));\n LUT3 #(\n .INIT(8'h08)) \n \\init_state_r[3]_i_12 \n (.I0(wrcal_done_reg_1),\n .I1(dqs_found_done_r_reg),\n .I2(rdlvl_stg1_start_int_reg),\n .O(\\init_state_r_reg[3] ));\n LUT6 #(\n .INIT(64'h2FAF2FAF2FAF0000)) \n \\init_state_r[4]_i_23 \n (.I0(\\init_state_r[4]_i_34_n_0 ),\n .I1(mem_init_done_r),\n .I2(oclkdelay_calib_done_r_reg),\n .I3(wrcal_done_reg_1),\n .I4(mpr_rdlvl_done_r_reg),\n .I5(mpr_last_byte_done),\n .O(\\init_state_r_reg[4] ));\n LUT6 #(\n .INIT(64'hB010000000000000)) \n \\init_state_r[4]_i_34 \n (.I0(rdlvl_stg1_done_int_reg),\n .I1(wrcal_done_reg_1),\n .I2(dqs_found_done_r_reg),\n .I3(prbs_rdlvl_done_reg_rep),\n .I4(\\init_state_r_reg[2] ),\n .I5(dqs_found_done_r_reg_0),\n .O(\\init_state_r[4]_i_34_n_0 ));\n LUT6 #(\n .INIT(64'hFFFBFFFBFF00FFFB)) \n \\init_state_r[5]_i_28 \n (.I0(wrlvl_byte_redo),\n .I1(dqs_found_done_r_reg),\n .I2(wrlvl_final_mux),\n .I3(wrlvl_done_r1),\n .I4(oclkdelay_center_calib_done_r_reg),\n .I5(prbs_rdlvl_done_reg_rep_0),\n .O(\\init_state_r_reg[5] ));\n LUT6 #(\n .INIT(64'hFFFFFFFF44440004)) \n \\input_[0].iserdes_dq_.idelay_finedelay_dq.idelaye2_i_2 \n (.I0(Q),\n .I1(idelay_ld),\n .I2(\\calib_sel_reg[1] [0]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(calib_in_common),\n .I5(idelay_ld_rst),\n .O(LD0));\n LUT6 #(\n .INIT(64'hFFFFFFFF44440040)) \n \\input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_i_2 \n (.I0(Q),\n .I1(idelay_ld),\n .I2(\\calib_sel_reg[1] [0]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(calib_in_common),\n .I5(idelay_ld_rst_3),\n .O(LD0_0));\n LUT6 #(\n .INIT(64'hFFFFFFFF44440040)) \n \\input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_i_2__0 \n (.I0(Q),\n .I1(idelay_ld),\n .I2(\\calib_sel_reg[1] [1]),\n .I3(\\calib_sel_reg[1] [0]),\n .I4(calib_in_common),\n .I5(idelay_ld_rst_4),\n .O(LD0_1));\n LUT6 #(\n .INIT(64'hFFFFFFFF44444000)) \n \\input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2_i_2__1 \n (.I0(Q),\n .I1(idelay_ld),\n .I2(\\calib_sel_reg[1] [0]),\n .I3(\\calib_sel_reg[1] [1]),\n .I4(calib_in_common),\n .I5(idelay_ld_rst_5),\n .O(LD0_2));\n (* SOFT_HLUTNM = \"soft_lutpair636\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\not_empty_wait_cnt[0]_i_1 \n (.I0(\\not_empty_wait_cnt_reg_n_0_[0] ),\n .O(p_0_in[0]));\n (* SOFT_HLUTNM = \"soft_lutpair636\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\not_empty_wait_cnt[1]_i_1 \n (.I0(\\not_empty_wait_cnt_reg_n_0_[0] ),\n .I1(\\not_empty_wait_cnt_reg_n_0_[1] ),\n .O(p_0_in[1]));\n (* SOFT_HLUTNM = \"soft_lutpair631\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\not_empty_wait_cnt[2]_i_1 \n (.I0(\\not_empty_wait_cnt_reg_n_0_[2] ),\n .I1(\\not_empty_wait_cnt_reg_n_0_[1] ),\n .I2(\\not_empty_wait_cnt_reg_n_0_[0] ),\n .O(p_0_in[2]));\n (* SOFT_HLUTNM = \"soft_lutpair631\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\not_empty_wait_cnt[3]_i_1 \n (.I0(\\not_empty_wait_cnt_reg_n_0_[3] ),\n .I1(\\not_empty_wait_cnt_reg_n_0_[0] ),\n .I2(\\not_empty_wait_cnt_reg_n_0_[1] ),\n .I3(\\not_empty_wait_cnt_reg_n_0_[2] ),\n .O(p_0_in[3]));\n LUT6 #(\n .INIT(64'hFFFEFFFFFFFFFFFF)) \n \\not_empty_wait_cnt[4]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__23),\n .I1(\\not_empty_wait_cnt_reg[0]_0 [3]),\n .I2(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I3(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I4(\\not_empty_wait_cnt_reg[0]_0 [0]),\n .I5(wrcal_rd_wait),\n .O(\\not_empty_wait_cnt[4]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair615\" *) \n LUT5 #(\n .INIT(32'h6AAAAAAA)) \n \\not_empty_wait_cnt[4]_i_2 \n (.I0(\\not_empty_wait_cnt_reg_n_0_[4] ),\n .I1(\\not_empty_wait_cnt_reg_n_0_[2] ),\n .I2(\\not_empty_wait_cnt_reg_n_0_[1] ),\n .I3(\\not_empty_wait_cnt_reg_n_0_[0] ),\n .I4(\\not_empty_wait_cnt_reg_n_0_[3] ),\n .O(p_0_in[4]));\n FDRE \\not_empty_wait_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in[0]),\n .Q(\\not_empty_wait_cnt_reg_n_0_[0] ),\n .R(\\not_empty_wait_cnt[4]_i_1_n_0 ));\n FDRE \\not_empty_wait_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in[1]),\n .Q(\\not_empty_wait_cnt_reg_n_0_[1] ),\n .R(\\not_empty_wait_cnt[4]_i_1_n_0 ));\n FDRE \\not_empty_wait_cnt_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in[2]),\n .Q(\\not_empty_wait_cnt_reg_n_0_[2] ),\n .R(\\not_empty_wait_cnt[4]_i_1_n_0 ));\n FDRE \\not_empty_wait_cnt_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in[3]),\n .Q(\\not_empty_wait_cnt_reg_n_0_[3] ),\n .R(\\not_empty_wait_cnt[4]_i_1_n_0 ));\n FDRE \\not_empty_wait_cnt_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in[4]),\n .Q(\\not_empty_wait_cnt_reg_n_0_[4] ),\n .R(\\not_empty_wait_cnt[4]_i_1_n_0 ));\n FDRE \\po_stg2_wrcal_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wrcal_dqs_cnt_r_reg_n_0_[0] ),\n .Q(\\idelay_tap_cnt_r_reg[0][2][0]_0 [0]),\n .R(1'b0));\n FDRE \\po_stg2_wrcal_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wrcal_dqs_cnt_r_reg_n_0_[1] ),\n .Q(\\idelay_tap_cnt_r_reg[0][2][0]_0 [1]),\n .R(1'b0));\n FDRE \\po_stg2_wrcal_cnt_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(wrcal_dqs_cnt_r),\n .Q(\\idelay_tap_cnt_r_reg[0][2][0]_0 [2]),\n .R(1'b0));\n FDRE rd_active_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(phy_rddata_en_1),\n .Q(rd_active_r1),\n .R(1'b0));\n FDRE rd_active_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rd_active_r1),\n .Q(rd_active_r2),\n .R(1'b0));\n FDRE rd_active_r3_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rd_active_r2),\n .Q(rd_active_r3),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair637\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\tap_inc_wait_cnt[0]_i_1 \n (.I0(tap_inc_wait_cnt_reg__0[0]),\n .O(p_0_in__0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair637\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\tap_inc_wait_cnt[1]_i_1 \n (.I0(tap_inc_wait_cnt_reg__0[1]),\n .I1(tap_inc_wait_cnt_reg__0[0]),\n .O(p_0_in__0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair630\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\tap_inc_wait_cnt[2]_i_1 \n (.I0(tap_inc_wait_cnt_reg__0[2]),\n .I1(tap_inc_wait_cnt_reg__0[0]),\n .I2(tap_inc_wait_cnt_reg__0[1]),\n .O(p_0_in__0[2]));\n LUT5 #(\n .INIT(32'hFFFFAFEF)) \n \\tap_inc_wait_cnt[3]_i_1 \n (.I0(\\not_empty_wait_cnt_reg[0]_0 [3]),\n .I1(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I2(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I3(\\not_empty_wait_cnt_reg[0]_0 [0]),\n .I4(rstdiv0_sync_r1_reg_rep__23),\n .O(\\tap_inc_wait_cnt[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair628\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\tap_inc_wait_cnt[3]_i_2 \n (.I0(tap_inc_wait_cnt_reg__0[3]),\n .I1(tap_inc_wait_cnt_reg__0[1]),\n .I2(tap_inc_wait_cnt_reg__0[0]),\n .I3(tap_inc_wait_cnt_reg__0[2]),\n .O(p_0_in__0[3]));\n FDRE \\tap_inc_wait_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0[0]),\n .Q(tap_inc_wait_cnt_reg__0[0]),\n .R(\\tap_inc_wait_cnt[3]_i_1_n_0 ));\n FDRE \\tap_inc_wait_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0[1]),\n .Q(tap_inc_wait_cnt_reg__0[1]),\n .R(\\tap_inc_wait_cnt[3]_i_1_n_0 ));\n FDRE \\tap_inc_wait_cnt_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0[2]),\n .Q(tap_inc_wait_cnt_reg__0[2]),\n .R(\\tap_inc_wait_cnt[3]_i_1_n_0 ));\n FDRE \\tap_inc_wait_cnt_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0[3]),\n .Q(tap_inc_wait_cnt_reg__0[3]),\n .R(\\tap_inc_wait_cnt[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair625\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\wl_tap_count_r[5]_i_3 \n (.I0(wrlvl_byte_redo),\n .I1(wrlvl_byte_redo_r),\n .O(done_dqs_dec239_out));\n LUT5 #(\n .INIT(32'h0E0E000E)) \n wrcal_done_i_1\n (.I0(wrcal_done_reg_1),\n .I1(cal2_done_r),\n .I2(rstdiv0_sync_r1_reg_rep__23),\n .I3(wrcal_sanity_chk),\n .I4(wrcal_done_reg_0),\n .O(wrcal_done_i_1_n_0));\n FDRE wrcal_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrcal_done_i_1_n_0),\n .Q(wrcal_done_reg_1),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair634\" *) \n LUT3 #(\n .INIT(8'h34)) \n \\wrcal_dqs_cnt_r[0]_i_1 \n (.I0(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I1(\\wrcal_dqs_cnt_r[2]_i_3_n_0 ),\n .I2(\\wrcal_dqs_cnt_r_reg_n_0_[0] ),\n .O(\\wrcal_dqs_cnt_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair623\" *) \n LUT4 #(\n .INIT(16'h1F20)) \n \\wrcal_dqs_cnt_r[1]_i_1 \n (.I0(\\wrcal_dqs_cnt_r_reg_n_0_[0] ),\n .I1(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I2(\\wrcal_dqs_cnt_r[2]_i_3_n_0 ),\n .I3(\\wrcal_dqs_cnt_r_reg_n_0_[1] ),\n .O(\\wrcal_dqs_cnt_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair623\" *) \n LUT5 #(\n .INIT(32'h07FF0800)) \n \\wrcal_dqs_cnt_r[2]_i_2 \n (.I0(\\wrcal_dqs_cnt_r_reg_n_0_[1] ),\n .I1(\\wrcal_dqs_cnt_r_reg_n_0_[0] ),\n .I2(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I3(\\wrcal_dqs_cnt_r[2]_i_3_n_0 ),\n .I4(wrcal_dqs_cnt_r),\n .O(\\wrcal_dqs_cnt_r[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000054040000)) \n \\wrcal_dqs_cnt_r[2]_i_3 \n (.I0(\\not_empty_wait_cnt_reg[0]_0 [3]),\n .I1(\\wrcal_dqs_cnt_r[2]_i_4_n_0 ),\n .I2(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I3(wrcal_sanity_chk_reg),\n .I4(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I5(\\not_empty_wait_cnt_reg[0]_0 [0]),\n .O(\\wrcal_dqs_cnt_r[2]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair617\" *) \n LUT5 #(\n .INIT(32'hCFFF8AAA)) \n \\wrcal_dqs_cnt_r[2]_i_4 \n (.I0(prech_done),\n .I1(wrcal_dqs_cnt_r),\n .I2(\\wrcal_dqs_cnt_r_reg_n_0_[0] ),\n .I3(\\wrcal_dqs_cnt_r_reg_n_0_[1] ),\n .I4(wrcal_done_reg_0),\n .O(\\wrcal_dqs_cnt_r[2]_i_4_n_0 ));\n (* syn_maxfan = \"10\" *) \n FDRE \\wrcal_dqs_cnt_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wrcal_dqs_cnt_r[0]_i_1_n_0 ),\n .Q(\\wrcal_dqs_cnt_r_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__6));\n (* syn_maxfan = \"10\" *) \n FDRE \\wrcal_dqs_cnt_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wrcal_dqs_cnt_r[1]_i_1_n_0 ),\n .Q(\\wrcal_dqs_cnt_r_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__6));\n (* syn_maxfan = \"10\" *) \n FDRE \\wrcal_dqs_cnt_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wrcal_dqs_cnt_r[2]_i_2_n_0 ),\n .Q(wrcal_dqs_cnt_r),\n .R(rstdiv0_sync_r1_reg_rep__6));\n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/wrcal_pat_resume_r2_reg_srl2 \" *) \n SRL16E wrcal_pat_resume_r2_reg_srl2\n (.A0(1'b1),\n .A1(1'b0),\n .A2(1'b0),\n .A3(1'b0),\n .CE(1'b1),\n .CLK(CLK),\n .D(wrcal_pat_resume_r),\n .Q(wrcal_pat_resume_r2_reg_srl2_n_0));\n LUT6 #(\n .INIT(64'h08000800033C003C)) \n wrcal_pat_resume_r_i_2\n (.I0(\\cal2_state_r[3]_i_8_n_0 ),\n .I1(\\not_empty_wait_cnt_reg[0]_0 [0]),\n .I2(\\not_empty_wait_cnt_reg[0]_0 [3]),\n .I3(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I4(wrcal_pat_resume_r_i_3_n_0),\n .I5(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .O(wrcal_pat_resume_r_reg_1));\n LUT6 #(\n .INIT(64'h0000800000000000)) \n wrcal_pat_resume_r_i_3\n (.I0(wrcal_pat_resume_r_reg_0),\n .I1(tap_inc_wait_cnt_reg__0[2]),\n .I2(tap_inc_wait_cnt_reg__0[0]),\n .I3(tap_inc_wait_cnt_reg__0[1]),\n .I4(wrcal_done_reg_0),\n .I5(tap_inc_wait_cnt_reg__0[3]),\n .O(wrcal_pat_resume_r_i_3_n_0));\n FDRE wrcal_pat_resume_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\cal2_state_r_reg[2]_0 ),\n .Q(wrcal_pat_resume_r),\n .R(rstdiv0_sync_r1_reg_rep__2));\n FDRE wrcal_pat_resume_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrcal_pat_resume_r2_reg_srl2_n_0),\n .Q(wrcal_resume_w),\n .R(1'b0));\n FDRE wrcal_prech_req_reg\n (.C(CLK),\n .CE(1'b1),\n .D(cal2_prech_req_r),\n .Q(wrcal_prech_req),\n .R(rstdiv0_sync_r1_reg_rep__6));\n FDRE wrcal_sanity_chk_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\cal2_state_r_reg[3]_0 ),\n .Q(wrcal_sanity_chk_done_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__4));\n FDRE wrcal_sanity_chk_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrcal_sanity_chk),\n .Q(wrcal_done_reg_0),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair633\" *) \n LUT3 #(\n .INIT(8'h1F)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[156]_i_1 \n (.I0(wrcal_done_reg_1),\n .I1(first_wrcal_pat_r),\n .I2(oclkdelay_calib_done_r_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] ));\n (* SOFT_HLUTNM = \"soft_lutpair633\" *) \n LUT3 #(\n .INIT(8'h7F)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[191]_i_1 \n (.I0(wrcal_done_reg_1),\n .I1(oclkdelay_calib_done_r_reg),\n .I2(rdlvl_stg1_done_int_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] ));\n (* SOFT_HLUTNM = \"soft_lutpair629\" *) \n LUT2 #(\n .INIT(4'h7)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[221]_i_1 \n (.I0(wrcal_done_reg_1),\n .I1(oclkdelay_calib_done_r_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] ));\n (* SOFT_HLUTNM = \"soft_lutpair632\" *) \n LUT3 #(\n .INIT(8'h2F)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[223]_i_1 \n (.I0(wrcal_done_reg_1),\n .I1(rdlvl_stg1_done_int_reg),\n .I2(oclkdelay_calib_done_r_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] ));\n FDRE wrlvl_byte_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrlvl_byte_done),\n .Q(wrlvl_byte_done_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0000000022222E22)) \n wrlvl_byte_redo_i_2\n (.I0(wrlvl_byte_redo_i_3_n_0),\n .I1(\\not_empty_wait_cnt_reg[0]_0 [1]),\n .I2(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .I3(wrlvl_byte_done),\n .I4(wrlvl_byte_done_r),\n .I5(\\not_empty_wait_cnt_reg[0]_0 [3]),\n .O(wrlvl_byte_redo_reg_0));\n LUT6 #(\n .INIT(64'h0000000000300020)) \n wrlvl_byte_redo_i_3\n (.I0(early1_data_reg_0),\n .I1(\\gen_pat_match_div4.pat_data_match_r_reg_n_0 ),\n .I2(idelay_ld_reg_0),\n .I3(wrcal_done_reg_0),\n .I4(early2_data_reg_0),\n .I5(\\not_empty_wait_cnt_reg[0]_0 [2]),\n .O(wrlvl_byte_redo_i_3_n_0));\n FDRE wrlvl_byte_redo_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\gen_pat_match_div4.early2_data_match_r_reg_0 ),\n .Q(wrlvl_byte_redo),\n .R(rstdiv0_sync_r1_reg_rep__6));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_ddr_phy_wrlvl\n (wr_level_done_r1_reg_0,\n wrlvl_byte_redo_r,\n wrlvl_final_r,\n dqs_po_dec_done,\n dqs_po_stg2_f_incdec,\n dqs_po_en_stg2_f,\n dqs_wl_po_stg2_c_incdec,\n \\rd_data_edge_detect_r_reg[0]_0 ,\n \\FSM_sequential_wl_state_r_reg[0]_0 ,\n p_0_in,\n \\rd_data_edge_detect_r_reg[0]_1 ,\n dqs_po_en_stg2_f_reg_0,\n wrlvl_done_r_reg,\n wrlvl_rank_done,\n D,\n \\stg2_target_r_reg[4] ,\n \\stg2_r_reg[4] ,\n \\stg3_dec_val_reg[2] ,\n \\stg2_r_reg[5] ,\n out,\n stable_cnt227_in,\n \\stg3_dec_val_reg[2]_0 ,\n \\lim_state_reg[12] ,\n \\stg2_r_reg[0] ,\n \\po_rdval_cnt_reg[0]_0 ,\n flag_ck_negedge09_out,\n \\stable_cnt_reg[3]_0 ,\n \\rank_cnt_r_reg[0]_0 ,\n \\rank_cnt_r_reg[0]_1 ,\n stable_cnt1,\n \\wrlvl_redo_corse_inc_reg[2]_0 ,\n po_cnt_dec_reg_0,\n flag_ck_negedge_reg_0,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[1] ,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[2] ,\n p_1_in,\n wrlvl_byte_done,\n done_dqs_tap_inc,\n wr_level_done_r_reg_0,\n wrlvl_rank_done_r_reg_0,\n dq_cnt_inc_reg_0,\n inhibit_edge_detect_r,\n inhibit_edge_detect_r_reg_0,\n \\mcGo_r_reg[15] ,\n CLK,\n wrlvl_byte_redo,\n wrlvl_final_mux,\n wr_lvl_start_reg,\n rstdiv0_sync_r1_reg_rep__18,\n rstdiv0_sync_r1_reg_rep__15,\n flag_ck_negedge_reg_1,\n rstdiv0_sync_r1_reg_rep__16,\n \\FSM_sequential_wl_state_r_reg[2]_0 ,\n \\FSM_sequential_wl_state_r_reg[0]_1 ,\n \\FSM_sequential_wl_state_r_reg[1]_0 ,\n inhibit_edge_detect_r_reg_1,\n \\wait_cnt_reg[0]_0 ,\n \\single_rank.done_dqs_dec_reg_0 ,\n \\FSM_sequential_wl_state_r_reg[2]_1 ,\n S,\n \\stg3_r_reg[5] ,\n O,\n wl_sm_start,\n \\byte_r_reg[0] ,\n \\byte_r_reg[1] ,\n Q,\n \\stg2_tap_cnt_reg[2] ,\n \\po_counter_read_val_reg[8] ,\n \\po_counter_read_val_reg[8]_0 ,\n \\calib_sel_reg[3] ,\n \\po_counter_read_val_reg[5] ,\n rstdiv0_sync_r1_reg_rep__23,\n oclkdelay_calib_done_r_reg,\n \\po_stg2_wrcal_cnt_reg[2] ,\n early1_data_reg,\n early1_data_reg_0,\n rstdiv0_sync_r1_reg_rep__20,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ,\n pi_f_inc_reg,\n oclkdelay_calib_done_r_reg_0,\n delay_done_r4_reg,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 ,\n oclkdelay_calib_done_r_reg_1,\n byte_sel_cnt,\n \\prbs_dqs_cnt_r_reg[2] ,\n rstdiv0_sync_r1_reg_rep__25,\n pi_fine_dly_dec_done,\n rstdiv0_sync_r1_reg_rep__17,\n rstdiv0_sync_r1_reg_rep,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ,\n my_empty,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ,\n my_empty_6,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ,\n my_empty_7,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ,\n my_empty_8,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ,\n po_cnt_dec_reg_1,\n rstdiv0_sync_r1_reg_rep__19,\n done_dqs_dec239_out,\n \\po_stg2_wrcal_cnt_reg[0] ,\n \\po_stg2_wrcal_cnt_reg[2]_0 ,\n \\po_stg2_wrcal_cnt_reg[1] ,\n wrlvl_byte_redo_reg);\n output wr_level_done_r1_reg_0;\n output wrlvl_byte_redo_r;\n output wrlvl_final_r;\n output dqs_po_dec_done;\n output dqs_po_stg2_f_incdec;\n output dqs_po_en_stg2_f;\n output dqs_wl_po_stg2_c_incdec;\n output \\rd_data_edge_detect_r_reg[0]_0 ;\n output \\FSM_sequential_wl_state_r_reg[0]_0 ;\n output p_0_in;\n output \\rd_data_edge_detect_r_reg[0]_1 ;\n output dqs_po_en_stg2_f_reg_0;\n output wrlvl_done_r_reg;\n output wrlvl_rank_done;\n output [7:0]D;\n output [1:0]\\stg2_target_r_reg[4] ;\n output \\stg2_r_reg[4] ;\n output \\stg3_dec_val_reg[2] ;\n output \\stg2_r_reg[5] ;\n output [4:0]out;\n output stable_cnt227_in;\n output [2:0]\\stg3_dec_val_reg[2]_0 ;\n output \\lim_state_reg[12] ;\n output \\stg2_r_reg[0] ;\n output \\po_rdval_cnt_reg[0]_0 ;\n output flag_ck_negedge09_out;\n output [0:0]\\stable_cnt_reg[3]_0 ;\n output \\rank_cnt_r_reg[0]_0 ;\n output \\rank_cnt_r_reg[0]_1 ;\n output stable_cnt1;\n output [1:0]\\wrlvl_redo_corse_inc_reg[2]_0 ;\n output po_cnt_dec_reg_0;\n output flag_ck_negedge_reg_0;\n output \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ;\n output \\gen_byte_sel_div1.byte_sel_cnt_reg[1] ;\n output \\gen_byte_sel_div1.byte_sel_cnt_reg[2] ;\n output p_1_in;\n output wrlvl_byte_done;\n output done_dqs_tap_inc;\n output wr_level_done_r_reg_0;\n output wrlvl_rank_done_r_reg_0;\n output dq_cnt_inc_reg_0;\n output inhibit_edge_detect_r;\n output inhibit_edge_detect_r_reg_0;\n input \\mcGo_r_reg[15] ;\n input CLK;\n input wrlvl_byte_redo;\n input wrlvl_final_mux;\n input wr_lvl_start_reg;\n input [0:0]rstdiv0_sync_r1_reg_rep__18;\n input [0:0]rstdiv0_sync_r1_reg_rep__15;\n input flag_ck_negedge_reg_1;\n input [0:0]rstdiv0_sync_r1_reg_rep__16;\n input \\FSM_sequential_wl_state_r_reg[2]_0 ;\n input \\FSM_sequential_wl_state_r_reg[0]_1 ;\n input \\FSM_sequential_wl_state_r_reg[1]_0 ;\n input inhibit_edge_detect_r_reg_1;\n input \\wait_cnt_reg[0]_0 ;\n input \\single_rank.done_dqs_dec_reg_0 ;\n input \\FSM_sequential_wl_state_r_reg[2]_1 ;\n input [0:0]S;\n input [2:0]\\stg3_r_reg[5] ;\n input [3:0]O;\n input wl_sm_start;\n input \\byte_r_reg[0] ;\n input \\byte_r_reg[1] ;\n input [2:0]Q;\n input [2:0]\\stg2_tap_cnt_reg[2] ;\n input [4:0]\\po_counter_read_val_reg[8] ;\n input [4:0]\\po_counter_read_val_reg[8]_0 ;\n input [0:0]\\calib_sel_reg[3] ;\n input [3:0]\\po_counter_read_val_reg[5] ;\n input rstdiv0_sync_r1_reg_rep__23;\n input oclkdelay_calib_done_r_reg;\n input [2:0]\\po_stg2_wrcal_cnt_reg[2] ;\n input early1_data_reg;\n input early1_data_reg_0;\n input rstdiv0_sync_r1_reg_rep__20;\n input \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ;\n input pi_f_inc_reg;\n input oclkdelay_calib_done_r_reg_0;\n input delay_done_r4_reg;\n input \\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 ;\n input oclkdelay_calib_done_r_reg_1;\n input [0:0]byte_sel_cnt;\n input \\prbs_dqs_cnt_r_reg[2] ;\n input rstdiv0_sync_r1_reg_rep__25;\n input pi_fine_dly_dec_done;\n input [0:0]rstdiv0_sync_r1_reg_rep__17;\n input rstdiv0_sync_r1_reg_rep;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;\n input [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;\n input [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ;\n input [0:0]my_empty;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;\n input [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;\n input [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ;\n input [0:0]my_empty_6;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;\n input [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;\n input [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ;\n input [0:0]my_empty_7;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ;\n input [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ;\n input [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ;\n input [0:0]my_empty_8;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ;\n input \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;\n input [0:0]po_cnt_dec_reg_1;\n input [0:0]rstdiv0_sync_r1_reg_rep__19;\n input done_dqs_dec239_out;\n input \\po_stg2_wrcal_cnt_reg[0] ;\n input \\po_stg2_wrcal_cnt_reg[2]_0 ;\n input \\po_stg2_wrcal_cnt_reg[1] ;\n input wrlvl_byte_redo_reg;\n\n wire CLK;\n wire [7:0]D;\n wire \\FSM_sequential_wl_state_r[0]_i_10_n_0 ;\n wire \\FSM_sequential_wl_state_r[0]_i_11_n_0 ;\n wire \\FSM_sequential_wl_state_r[0]_i_13_n_0 ;\n wire \\FSM_sequential_wl_state_r[0]_i_14_n_0 ;\n wire \\FSM_sequential_wl_state_r[0]_i_15_n_0 ;\n wire \\FSM_sequential_wl_state_r[0]_i_16_n_0 ;\n wire \\FSM_sequential_wl_state_r[0]_i_1_n_0 ;\n wire \\FSM_sequential_wl_state_r[0]_i_2_n_0 ;\n wire \\FSM_sequential_wl_state_r[0]_i_3_n_0 ;\n wire \\FSM_sequential_wl_state_r[0]_i_4_n_0 ;\n wire \\FSM_sequential_wl_state_r[0]_i_5_n_0 ;\n wire \\FSM_sequential_wl_state_r[0]_i_6_n_0 ;\n wire \\FSM_sequential_wl_state_r[0]_i_7_n_0 ;\n wire \\FSM_sequential_wl_state_r[0]_i_8_n_0 ;\n wire \\FSM_sequential_wl_state_r[0]_i_9_n_0 ;\n wire \\FSM_sequential_wl_state_r[1]_i_10_n_0 ;\n wire \\FSM_sequential_wl_state_r[1]_i_11_n_0 ;\n wire \\FSM_sequential_wl_state_r[1]_i_1_n_0 ;\n wire \\FSM_sequential_wl_state_r[1]_i_2_n_0 ;\n wire \\FSM_sequential_wl_state_r[1]_i_3_n_0 ;\n wire \\FSM_sequential_wl_state_r[1]_i_4_n_0 ;\n wire \\FSM_sequential_wl_state_r[1]_i_5_n_0 ;\n wire \\FSM_sequential_wl_state_r[1]_i_6_n_0 ;\n wire \\FSM_sequential_wl_state_r[1]_i_7_n_0 ;\n wire \\FSM_sequential_wl_state_r[1]_i_8_n_0 ;\n wire \\FSM_sequential_wl_state_r[1]_i_9_n_0 ;\n wire \\FSM_sequential_wl_state_r[2]_i_10_n_0 ;\n wire \\FSM_sequential_wl_state_r[2]_i_11_n_0 ;\n wire \\FSM_sequential_wl_state_r[2]_i_12_n_0 ;\n wire \\FSM_sequential_wl_state_r[2]_i_13_n_0 ;\n wire \\FSM_sequential_wl_state_r[2]_i_14_n_0 ;\n wire \\FSM_sequential_wl_state_r[2]_i_15_n_0 ;\n wire \\FSM_sequential_wl_state_r[2]_i_1_n_0 ;\n wire \\FSM_sequential_wl_state_r[2]_i_2_n_0 ;\n wire \\FSM_sequential_wl_state_r[2]_i_3_n_0 ;\n wire \\FSM_sequential_wl_state_r[2]_i_5_n_0 ;\n wire \\FSM_sequential_wl_state_r[2]_i_6_n_0 ;\n wire \\FSM_sequential_wl_state_r[2]_i_7_n_0 ;\n wire \\FSM_sequential_wl_state_r[2]_i_8_n_0 ;\n wire \\FSM_sequential_wl_state_r[2]_i_9_n_0 ;\n wire \\FSM_sequential_wl_state_r[3]_i_10_n_0 ;\n wire \\FSM_sequential_wl_state_r[3]_i_1_n_0 ;\n wire \\FSM_sequential_wl_state_r[3]_i_2_n_0 ;\n wire \\FSM_sequential_wl_state_r[3]_i_3_n_0 ;\n wire \\FSM_sequential_wl_state_r[3]_i_4_n_0 ;\n wire \\FSM_sequential_wl_state_r[3]_i_5_n_0 ;\n wire \\FSM_sequential_wl_state_r[3]_i_6_n_0 ;\n wire \\FSM_sequential_wl_state_r[3]_i_7_n_0 ;\n wire \\FSM_sequential_wl_state_r[3]_i_8_n_0 ;\n wire \\FSM_sequential_wl_state_r[3]_i_9_n_0 ;\n wire \\FSM_sequential_wl_state_r[4]_i_10_n_0 ;\n wire \\FSM_sequential_wl_state_r[4]_i_11_n_0 ;\n wire \\FSM_sequential_wl_state_r[4]_i_12_n_0 ;\n wire \\FSM_sequential_wl_state_r[4]_i_1_n_0 ;\n wire \\FSM_sequential_wl_state_r[4]_i_2_n_0 ;\n wire \\FSM_sequential_wl_state_r[4]_i_3_n_0 ;\n wire \\FSM_sequential_wl_state_r[4]_i_5_n_0 ;\n wire \\FSM_sequential_wl_state_r[4]_i_7_n_0 ;\n wire \\FSM_sequential_wl_state_r[4]_i_8_n_0 ;\n wire \\FSM_sequential_wl_state_r[4]_i_9_n_0 ;\n wire \\FSM_sequential_wl_state_r_reg[0]_0 ;\n wire \\FSM_sequential_wl_state_r_reg[0]_1 ;\n wire \\FSM_sequential_wl_state_r_reg[0]_i_12_n_0 ;\n wire \\FSM_sequential_wl_state_r_reg[1]_0 ;\n wire \\FSM_sequential_wl_state_r_reg[2]_0 ;\n wire \\FSM_sequential_wl_state_r_reg[2]_1 ;\n wire \\FSM_sequential_wl_state_r_reg[2]_i_4_n_0 ;\n wire \\FSM_sequential_wl_state_r_reg[4]_i_4_n_0 ;\n wire [3:0]O;\n wire [2:0]Q;\n wire [0:0]S;\n wire \\byte_r_reg[0] ;\n wire \\byte_r_reg[1] ;\n wire [0:0]byte_sel_cnt;\n wire [0:0]\\calib_sel_reg[3] ;\n wire [2:0]corse_cnt;\n wire \\corse_cnt[0][0]_i_1_n_0 ;\n wire \\corse_cnt[0][0]_i_3_n_0 ;\n wire \\corse_cnt[0][0]_i_4_n_0 ;\n wire \\corse_cnt[0][1]_i_1_n_0 ;\n wire \\corse_cnt[0][1]_i_3_n_0 ;\n wire \\corse_cnt[0][1]_i_4_n_0 ;\n wire \\corse_cnt[0][1]_i_5_n_0 ;\n wire \\corse_cnt[0][2]_i_10_n_0 ;\n wire \\corse_cnt[0][2]_i_1_n_0 ;\n wire \\corse_cnt[0][2]_i_3_n_0 ;\n wire \\corse_cnt[0][2]_i_4_n_0 ;\n wire \\corse_cnt[0][2]_i_5_n_0 ;\n wire \\corse_cnt[0][2]_i_6_n_0 ;\n wire \\corse_cnt[0][2]_i_7_n_0 ;\n wire \\corse_cnt[0][2]_i_8_n_0 ;\n wire \\corse_cnt[0][2]_i_9_n_0 ;\n wire \\corse_cnt[1][0]_i_1_n_0 ;\n wire \\corse_cnt[1][1]_i_1_n_0 ;\n wire \\corse_cnt[1][2]_i_1_n_0 ;\n wire \\corse_cnt[1][2]_i_2_n_0 ;\n wire \\corse_cnt[1][2]_i_3_n_0 ;\n wire \\corse_cnt[1][2]_i_4_n_0 ;\n wire \\corse_cnt[2][0]_i_1_n_0 ;\n wire \\corse_cnt[2][1]_i_1_n_0 ;\n wire \\corse_cnt[2][2]_i_1_n_0 ;\n wire \\corse_cnt[2][2]_i_2_n_0 ;\n wire \\corse_cnt[2][2]_i_3_n_0 ;\n wire \\corse_cnt[2][2]_i_4_n_0 ;\n wire \\corse_cnt[3][0]_i_1_n_0 ;\n wire \\corse_cnt[3][1]_i_1_n_0 ;\n wire \\corse_cnt[3][2]_i_1_n_0 ;\n wire \\corse_cnt[3][2]_i_2_n_0 ;\n wire \\corse_cnt[3][2]_i_3_n_0 ;\n wire \\corse_cnt[3][2]_i_4_n_0 ;\n wire \\corse_cnt_reg_n_0_[0][0] ;\n wire \\corse_cnt_reg_n_0_[0][1] ;\n wire \\corse_cnt_reg_n_0_[0][2] ;\n wire \\corse_cnt_reg_n_0_[1][0] ;\n wire \\corse_cnt_reg_n_0_[1][1] ;\n wire \\corse_cnt_reg_n_0_[1][2] ;\n wire \\corse_cnt_reg_n_0_[2][0] ;\n wire \\corse_cnt_reg_n_0_[2][1] ;\n wire \\corse_cnt_reg_n_0_[2][2] ;\n wire \\corse_cnt_reg_n_0_[3][0] ;\n wire \\corse_cnt_reg_n_0_[3][1] ;\n wire \\corse_cnt_reg_n_0_[3][2] ;\n wire \\corse_dec[0][0]_i_1_n_0 ;\n wire \\corse_dec[0][1]_i_1_n_0 ;\n wire \\corse_dec[0][2]_i_1_n_0 ;\n wire \\corse_dec[0][2]_i_2_n_0 ;\n wire \\corse_dec[1][0]_i_1_n_0 ;\n wire \\corse_dec[1][1]_i_1_n_0 ;\n wire \\corse_dec[1][2]_i_1_n_0 ;\n wire \\corse_dec[1][2]_i_2_n_0 ;\n wire \\corse_dec[2][0]_i_1_n_0 ;\n wire \\corse_dec[2][1]_i_1_n_0 ;\n wire \\corse_dec[2][2]_i_1_n_0 ;\n wire \\corse_dec[2][2]_i_2_n_0 ;\n wire \\corse_dec[3][0]_i_1_n_0 ;\n wire \\corse_dec[3][1]_i_1_n_0 ;\n wire \\corse_dec[3][2]_i_1_n_0 ;\n wire \\corse_dec[3][2]_i_2_n_0 ;\n wire \\corse_dec[3][2]_i_3_n_0 ;\n wire \\corse_dec[3][2]_i_4_n_0 ;\n wire \\corse_dec[3][2]_i_5_n_0 ;\n wire \\corse_dec_reg_n_0_[0][0] ;\n wire \\corse_dec_reg_n_0_[0][1] ;\n wire \\corse_dec_reg_n_0_[0][2] ;\n wire \\corse_dec_reg_n_0_[1][0] ;\n wire \\corse_dec_reg_n_0_[1][1] ;\n wire \\corse_dec_reg_n_0_[1][2] ;\n wire \\corse_dec_reg_n_0_[2][0] ;\n wire \\corse_dec_reg_n_0_[2][1] ;\n wire \\corse_dec_reg_n_0_[2][2] ;\n wire \\corse_dec_reg_n_0_[3][0] ;\n wire \\corse_dec_reg_n_0_[3][1] ;\n wire \\corse_dec_reg_n_0_[3][2] ;\n wire \\corse_inc[0][0]_i_1_n_0 ;\n wire \\corse_inc[0][1]_i_1_n_0 ;\n wire \\corse_inc[0][2]_i_1_n_0 ;\n wire \\corse_inc[0][2]_i_2_n_0 ;\n wire \\corse_inc[0][2]_i_3_n_0 ;\n wire \\corse_inc[1][0]_i_1_n_0 ;\n wire \\corse_inc[1][1]_i_1_n_0 ;\n wire \\corse_inc[1][2]_i_1_n_0 ;\n wire \\corse_inc[1][2]_i_2_n_0 ;\n wire \\corse_inc[1][2]_i_3_n_0 ;\n wire \\corse_inc[2][0]_i_1_n_0 ;\n wire \\corse_inc[2][1]_i_1_n_0 ;\n wire \\corse_inc[2][2]_i_1_n_0 ;\n wire \\corse_inc[2][2]_i_2_n_0 ;\n wire \\corse_inc[2][2]_i_3_n_0 ;\n wire \\corse_inc[3][0]_i_1_n_0 ;\n wire \\corse_inc[3][0]_i_2_n_0 ;\n wire \\corse_inc[3][1]_i_1_n_0 ;\n wire \\corse_inc[3][1]_i_2_n_0 ;\n wire \\corse_inc[3][2]_i_1_n_0 ;\n wire \\corse_inc[3][2]_i_2_n_0 ;\n wire \\corse_inc[3][2]_i_3_n_0 ;\n wire \\corse_inc[3][2]_i_4_n_0 ;\n wire \\corse_inc[3][2]_i_5_n_0 ;\n wire \\corse_inc[3][2]_i_6_n_0 ;\n wire \\corse_inc[3][2]_i_7_n_0 ;\n wire \\corse_inc_reg_n_0_[0][0] ;\n wire \\corse_inc_reg_n_0_[0][1] ;\n wire \\corse_inc_reg_n_0_[0][2] ;\n wire \\corse_inc_reg_n_0_[1][0] ;\n wire \\corse_inc_reg_n_0_[1][1] ;\n wire \\corse_inc_reg_n_0_[1][2] ;\n wire \\corse_inc_reg_n_0_[2][0] ;\n wire \\corse_inc_reg_n_0_[2][1] ;\n wire \\corse_inc_reg_n_0_[2][2] ;\n wire \\corse_inc_reg_n_0_[3][0] ;\n wire \\corse_inc_reg_n_0_[3][1] ;\n wire \\corse_inc_reg_n_0_[3][2] ;\n wire delay_done_r4_reg;\n wire done_dqs_dec;\n wire done_dqs_dec239_out;\n wire done_dqs_tap_inc;\n wire dq_cnt_inc_reg_0;\n wire [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ;\n wire [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;\n wire [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ;\n wire [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ;\n wire [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ;\n wire [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;\n wire [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;\n wire [0:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ;\n wire [2:0]dqs_count_r;\n wire dqs_count_r140_out;\n wire \\dqs_count_r[0]_i_1_n_0 ;\n wire \\dqs_count_r[0]_i_4_n_0 ;\n wire \\dqs_count_r[0]_i_5_n_0 ;\n wire \\dqs_count_r[0]_i_6_n_0 ;\n wire \\dqs_count_r[0]_i_7_n_0 ;\n wire \\dqs_count_r[0]_i_8_n_0 ;\n wire \\dqs_count_r[1]_i_1_n_0 ;\n wire \\dqs_count_r[1]_i_4_n_0 ;\n wire \\dqs_count_r[1]_i_5_n_0 ;\n wire \\dqs_count_r[1]_i_6_n_0 ;\n wire \\dqs_count_r[1]_i_7_n_0 ;\n wire \\dqs_count_r[1]_i_8_n_0 ;\n wire \\dqs_count_r[2]_i_10_n_0 ;\n wire \\dqs_count_r[2]_i_11_n_0 ;\n wire \\dqs_count_r[2]_i_2_n_0 ;\n wire \\dqs_count_r[2]_i_5_n_0 ;\n wire \\dqs_count_r[2]_i_6_n_0 ;\n wire \\dqs_count_r[2]_i_7_n_0 ;\n wire \\dqs_count_r[2]_i_8_n_0 ;\n wire \\dqs_count_r[2]_i_9_n_0 ;\n wire \\dqs_count_r_reg[0]_i_2_n_0 ;\n wire \\dqs_count_r_reg[0]_i_3_n_0 ;\n wire \\dqs_count_r_reg[0]_rep_n_0 ;\n wire \\dqs_count_r_reg[1]_i_2_n_0 ;\n wire \\dqs_count_r_reg[1]_i_3_n_0 ;\n wire \\dqs_count_r_reg[1]_rep_n_0 ;\n wire \\dqs_count_r_reg[2]_i_3_n_0 ;\n wire \\dqs_count_r_reg[2]_i_4_n_0 ;\n wire dqs_po_dec_done;\n wire dqs_po_en_stg2_f;\n wire dqs_po_en_stg2_f_i_1_n_0;\n wire dqs_po_en_stg2_f_reg_0;\n wire dqs_po_stg2_f_incdec;\n wire dqs_po_stg2_f_incdec0;\n wire dqs_po_stg2_f_incdec_i_2_n_0;\n wire dqs_po_stg2_f_incdec_i_3_n_0;\n wire dqs_wl_po_stg2_c_incdec;\n wire dqs_wl_po_stg2_c_incdec_i_1_n_0;\n wire early1_data_reg;\n wire early1_data_reg_0;\n wire [0:0]final_coarse_tap;\n wire \\final_coarse_tap_reg_n_0_[0][0] ;\n wire \\final_coarse_tap_reg_n_0_[0][1] ;\n wire \\final_coarse_tap_reg_n_0_[0][2] ;\n wire \\final_coarse_tap_reg_n_0_[1][0] ;\n wire \\final_coarse_tap_reg_n_0_[1][1] ;\n wire \\final_coarse_tap_reg_n_0_[1][2] ;\n wire \\final_coarse_tap_reg_n_0_[2][0] ;\n wire \\final_coarse_tap_reg_n_0_[2][1] ;\n wire \\final_coarse_tap_reg_n_0_[2][2] ;\n wire \\final_coarse_tap_reg_n_0_[3][0] ;\n wire \\final_coarse_tap_reg_n_0_[3][1] ;\n wire \\final_coarse_tap_reg_n_0_[3][2] ;\n wire [5:0]fine_dec_cnt;\n wire \\fine_dec_cnt[1]_i_2_n_0 ;\n wire \\fine_dec_cnt[2]_i_2_n_0 ;\n wire \\fine_dec_cnt[3]_i_2_n_0 ;\n wire \\fine_dec_cnt[4]_i_2_n_0 ;\n wire \\fine_dec_cnt[5]_i_3_n_0 ;\n wire \\fine_dec_cnt[5]_i_4_n_0 ;\n wire \\fine_dec_cnt[5]_i_5_n_0 ;\n wire \\fine_dec_cnt[5]_i_6_n_0 ;\n wire \\fine_dec_cnt[5]_i_7_n_0 ;\n wire \\fine_dec_cnt[5]_i_8_n_0 ;\n wire [5:0]fine_dec_cnt__0;\n wire \\fine_dec_cnt_reg[5]_i_1_n_0 ;\n wire [5:0]fine_inc;\n wire \\fine_inc[0][5]_i_1_n_0 ;\n wire \\fine_inc[0][5]_i_3_n_0 ;\n wire \\fine_inc[1][0]_i_1_n_0 ;\n wire \\fine_inc[1][1]_i_1_n_0 ;\n wire \\fine_inc[1][2]_i_1_n_0 ;\n wire \\fine_inc[1][3]_i_1_n_0 ;\n wire \\fine_inc[1][4]_i_1_n_0 ;\n wire \\fine_inc[1][5]_i_1_n_0 ;\n wire \\fine_inc[1][5]_i_2_n_0 ;\n wire \\fine_inc[1][5]_i_3_n_0 ;\n wire \\fine_inc[2][0]_i_1_n_0 ;\n wire \\fine_inc[2][1]_i_1_n_0 ;\n wire \\fine_inc[2][2]_i_1_n_0 ;\n wire \\fine_inc[2][3]_i_1_n_0 ;\n wire \\fine_inc[2][4]_i_1_n_0 ;\n wire \\fine_inc[2][5]_i_1_n_0 ;\n wire \\fine_inc[2][5]_i_2_n_0 ;\n wire \\fine_inc[2][5]_i_3_n_0 ;\n wire \\fine_inc[3][0]_i_1_n_0 ;\n wire \\fine_inc[3][1]_i_1_n_0 ;\n wire \\fine_inc[3][2]_i_1_n_0 ;\n wire \\fine_inc[3][2]_i_2_n_0 ;\n wire \\fine_inc[3][2]_i_3_n_0 ;\n wire \\fine_inc[3][2]_i_4_n_0 ;\n wire \\fine_inc[3][3]_i_1_n_0 ;\n wire \\fine_inc[3][4]_i_1_n_0 ;\n wire \\fine_inc[3][4]_i_2_n_0 ;\n wire \\fine_inc[3][4]_i_3_n_0 ;\n wire \\fine_inc[3][4]_i_4_n_0 ;\n wire \\fine_inc[3][5]_i_1_n_0 ;\n wire \\fine_inc[3][5]_i_2_n_0 ;\n wire \\fine_inc[3][5]_i_3_n_0 ;\n wire \\fine_inc[3][5]_i_5_n_0 ;\n wire \\fine_inc[3][5]_i_6_n_0 ;\n wire \\fine_inc[3][5]_i_7_n_0 ;\n wire \\fine_inc[3][5]_i_8_n_0 ;\n wire \\fine_inc_reg_n_0_[0][0] ;\n wire \\fine_inc_reg_n_0_[0][1] ;\n wire \\fine_inc_reg_n_0_[0][2] ;\n wire \\fine_inc_reg_n_0_[0][3] ;\n wire \\fine_inc_reg_n_0_[0][4] ;\n wire \\fine_inc_reg_n_0_[0][5] ;\n wire \\fine_inc_reg_n_0_[1][0] ;\n wire \\fine_inc_reg_n_0_[1][1] ;\n wire \\fine_inc_reg_n_0_[1][2] ;\n wire \\fine_inc_reg_n_0_[1][3] ;\n wire \\fine_inc_reg_n_0_[1][4] ;\n wire \\fine_inc_reg_n_0_[1][5] ;\n wire \\fine_inc_reg_n_0_[2][0] ;\n wire \\fine_inc_reg_n_0_[2][1] ;\n wire \\fine_inc_reg_n_0_[2][2] ;\n wire \\fine_inc_reg_n_0_[2][3] ;\n wire \\fine_inc_reg_n_0_[2][4] ;\n wire \\fine_inc_reg_n_0_[2][5] ;\n wire \\fine_inc_reg_n_0_[3][0] ;\n wire \\fine_inc_reg_n_0_[3][1] ;\n wire \\fine_inc_reg_n_0_[3][2] ;\n wire \\fine_inc_reg_n_0_[3][3] ;\n wire \\fine_inc_reg_n_0_[3][4] ;\n wire \\fine_inc_reg_n_0_[3][5] ;\n wire flag_ck_negedge09_out;\n wire flag_ck_negedge_i_10_n_0;\n wire flag_ck_negedge_i_6_n_0;\n wire flag_ck_negedge_i_7_n_0;\n wire flag_ck_negedge_i_8_n_0;\n wire flag_ck_negedge_reg_0;\n wire flag_ck_negedge_reg_1;\n wire flag_init;\n wire flag_init_i_1_n_0;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[0] ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[1] ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 ;\n wire \\gen_byte_sel_div1.byte_sel_cnt_reg[2] ;\n wire \\gen_final_tap[0].final_val_reg_n_0_[0][0] ;\n wire \\gen_final_tap[0].final_val_reg_n_0_[0][1] ;\n wire \\gen_final_tap[0].final_val_reg_n_0_[0][2] ;\n wire \\gen_final_tap[0].final_val_reg_n_0_[0][3] ;\n wire \\gen_final_tap[0].final_val_reg_n_0_[0][4] ;\n wire \\gen_final_tap[0].final_val_reg_n_0_[0][5] ;\n wire \\gen_final_tap[1].final_val_reg_n_0_[1][0] ;\n wire \\gen_final_tap[1].final_val_reg_n_0_[1][1] ;\n wire \\gen_final_tap[1].final_val_reg_n_0_[1][2] ;\n wire \\gen_final_tap[1].final_val_reg_n_0_[1][3] ;\n wire \\gen_final_tap[1].final_val_reg_n_0_[1][4] ;\n wire \\gen_final_tap[1].final_val_reg_n_0_[1][5] ;\n wire \\gen_final_tap[2].final_val_reg_n_0_[2][0] ;\n wire \\gen_final_tap[2].final_val_reg_n_0_[2][1] ;\n wire \\gen_final_tap[2].final_val_reg_n_0_[2][2] ;\n wire \\gen_final_tap[2].final_val_reg_n_0_[2][3] ;\n wire \\gen_final_tap[2].final_val_reg_n_0_[2][4] ;\n wire \\gen_final_tap[2].final_val_reg_n_0_[2][5] ;\n wire \\gen_final_tap[3].final_val_reg_n_0_[3][0] ;\n wire \\gen_final_tap[3].final_val_reg_n_0_[3][1] ;\n wire \\gen_final_tap[3].final_val_reg_n_0_[3][2] ;\n wire \\gen_final_tap[3].final_val_reg_n_0_[3][3] ;\n wire \\gen_final_tap[3].final_val_reg_n_0_[3][4] ;\n wire \\gen_final_tap[3].final_val_reg_n_0_[3][5] ;\n wire \\gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ;\n wire \\gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ;\n wire \\gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2] ;\n wire \\gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3] ;\n wire \\incdec_wait_cnt[3]_i_1_n_0 ;\n wire [3:0]incdec_wait_cnt_reg__0;\n wire inhibit_edge_detect_r;\n wire inhibit_edge_detect_r_i_4_n_0;\n wire inhibit_edge_detect_r_reg_0;\n wire inhibit_edge_detect_r_reg_1;\n wire [5:0]largest;\n wire \\lim_state_reg[12] ;\n wire \\mcGo_r_reg[15] ;\n wire [0:0]my_empty;\n wire [0:0]my_empty_6;\n wire [0:0]my_empty_7;\n wire [0:0]my_empty_8;\n wire [5:3]\\oclk_calib.u_ddr_phy_oclkdelay_cal/wl_po_fine_cnt_sel_0__0 ;\n wire oclkdelay_calib_done_r_reg;\n wire oclkdelay_calib_done_r_reg_0;\n wire oclkdelay_calib_done_r_reg_1;\n (* RTL_KEEP = \"yes\" *) wire [4:0]out;\n wire p_0_in;\n wire p_0_in32_in;\n wire [3:0]p_0_in__0;\n wire [3:0]p_0_in__0__0;\n wire \\p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_1_n_0 ;\n wire \\p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_2_n_0 ;\n wire \\p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_1_n_0 ;\n wire \\p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_2_n_0 ;\n wire \\p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_1_n_0 ;\n wire \\p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_2_n_0 ;\n wire \\p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_1_n_0 ;\n wire \\p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_2_n_0 ;\n wire p_1_in;\n wire p_1_in1_in;\n wire p_1_in28_in;\n wire p_1_in_0;\n wire p_21_out;\n wire phy_ctl_ready_r4_reg_srl4_n_0;\n wire phy_ctl_ready_r5;\n wire phy_ctl_ready_r6_reg_n_0;\n wire pi_f_inc_reg;\n wire pi_fine_dly_dec_done;\n wire po_cnt_dec_reg_0;\n wire [0:0]po_cnt_dec_reg_1;\n wire [3:0]\\po_counter_read_val_reg[5] ;\n wire [4:0]\\po_counter_read_val_reg[8] ;\n wire [4:0]\\po_counter_read_val_reg[8]_0 ;\n wire po_dec_done;\n wire po_dec_done_i_1_n_0;\n wire po_dec_done_i_2_n_0;\n wire po_dec_done_i_3_n_0;\n wire [8:0]po_rdval_cnt;\n wire \\po_rdval_cnt[0]_i_1_n_0 ;\n wire \\po_rdval_cnt[1]_i_1_n_0 ;\n wire \\po_rdval_cnt[2]_i_1_n_0 ;\n wire \\po_rdval_cnt[3]_i_1_n_0 ;\n wire \\po_rdval_cnt[4]_i_1_n_0 ;\n wire \\po_rdval_cnt[4]_i_2_n_0 ;\n wire \\po_rdval_cnt[5]_i_1_n_0 ;\n wire \\po_rdval_cnt[5]_i_2_n_0 ;\n wire \\po_rdval_cnt[6]_i_1_n_0 ;\n wire \\po_rdval_cnt[6]_i_2_n_0 ;\n wire \\po_rdval_cnt[7]_i_1_n_0 ;\n wire \\po_rdval_cnt[7]_i_2_n_0 ;\n wire \\po_rdval_cnt[8]_i_1_n_0 ;\n wire \\po_rdval_cnt[8]_i_2_n_0 ;\n wire \\po_rdval_cnt[8]_i_4_n_0 ;\n wire \\po_rdval_cnt[8]_i_5_n_0 ;\n wire \\po_rdval_cnt[8]_i_6_n_0 ;\n wire \\po_rdval_cnt[8]_i_7_n_0 ;\n wire \\po_rdval_cnt_reg[0]_0 ;\n wire \\po_stg2_wrcal_cnt_reg[0] ;\n wire \\po_stg2_wrcal_cnt_reg[1] ;\n wire [2:0]\\po_stg2_wrcal_cnt_reg[2] ;\n wire \\po_stg2_wrcal_cnt_reg[2]_0 ;\n wire \\prbs_dqs_cnt_r_reg[2] ;\n wire rank_cnt_r;\n wire \\rank_cnt_r[0]_i_1_n_0 ;\n wire \\rank_cnt_r[1]_i_1_n_0 ;\n wire \\rank_cnt_r_reg[0]_0 ;\n wire \\rank_cnt_r_reg[0]_1 ;\n wire rd_data_edge_detect_r0;\n wire \\rd_data_edge_detect_r[0]_i_1_n_0 ;\n wire \\rd_data_edge_detect_r[1]_i_1_n_0 ;\n wire \\rd_data_edge_detect_r[2]_i_1_n_0 ;\n wire \\rd_data_edge_detect_r[3]_i_2_n_0 ;\n wire \\rd_data_edge_detect_r[3]_i_3_n_0 ;\n wire \\rd_data_edge_detect_r[3]_i_4_n_0 ;\n wire \\rd_data_edge_detect_r[3]_i_5_n_0 ;\n wire \\rd_data_edge_detect_r[3]_i_6_n_0 ;\n wire \\rd_data_edge_detect_r_reg[0]_0 ;\n wire \\rd_data_edge_detect_r_reg[0]_1 ;\n wire \\rd_data_edge_detect_r_reg_n_0_[0] ;\n wire \\rd_data_edge_detect_r_reg_n_0_[1] ;\n wire \\rd_data_edge_detect_r_reg_n_0_[2] ;\n wire \\rd_data_edge_detect_r_reg_n_0_[3] ;\n wire rd_data_previous_r0;\n wire \\rd_data_previous_r[3]_i_2_n_0 ;\n wire \\rd_data_previous_r[3]_i_3_n_0 ;\n wire \\rd_data_previous_r[3]_i_4_n_0 ;\n wire \\rd_data_previous_r_reg_n_0_[0] ;\n wire \\rd_data_previous_r_reg_n_0_[1] ;\n wire \\rd_data_previous_r_reg_n_0_[2] ;\n wire \\rd_data_previous_r_reg_n_0_[3] ;\n wire rstdiv0_sync_r1_reg_rep;\n wire [0:0]rstdiv0_sync_r1_reg_rep__15;\n wire [0:0]rstdiv0_sync_r1_reg_rep__16;\n wire [0:0]rstdiv0_sync_r1_reg_rep__17;\n wire [0:0]rstdiv0_sync_r1_reg_rep__18;\n wire [0:0]rstdiv0_sync_r1_reg_rep__19;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__23;\n wire rstdiv0_sync_r1_reg_rep__25;\n wire \\single_rank.done_dqs_dec_i_1_n_0 ;\n wire \\single_rank.done_dqs_dec_reg_0 ;\n wire \\smallest[0][0]_i_2_n_0 ;\n wire \\smallest[0][1]_i_2_n_0 ;\n wire \\smallest[0][2]_i_2_n_0 ;\n wire \\smallest[0][3]_i_2_n_0 ;\n wire \\smallest[0][4]_i_2_n_0 ;\n wire \\smallest[0][5]_i_2_n_0 ;\n wire \\smallest[0][5]_i_4_n_0 ;\n wire \\smallest[0][5]_i_5_n_0 ;\n wire \\smallest[1][0]_i_1_n_0 ;\n wire \\smallest[1][1]_i_1_n_0 ;\n wire \\smallest[1][2]_i_1_n_0 ;\n wire \\smallest[1][3]_i_1_n_0 ;\n wire \\smallest[1][4]_i_1_n_0 ;\n wire \\smallest[1][5]_i_1_n_0 ;\n wire \\smallest[1][5]_i_2_n_0 ;\n wire \\smallest[2][0]_i_1_n_0 ;\n wire \\smallest[2][1]_i_1_n_0 ;\n wire \\smallest[2][2]_i_1_n_0 ;\n wire \\smallest[2][3]_i_1_n_0 ;\n wire \\smallest[2][4]_i_1_n_0 ;\n wire \\smallest[2][5]_i_1_n_0 ;\n wire \\smallest[2][5]_i_2_n_0 ;\n wire \\smallest[3][0]_i_1_n_0 ;\n wire \\smallest[3][1]_i_1_n_0 ;\n wire \\smallest[3][2]_i_1_n_0 ;\n wire \\smallest[3][3]_i_1_n_0 ;\n wire \\smallest[3][4]_i_1_n_0 ;\n wire \\smallest[3][5]_i_1_n_0 ;\n wire \\smallest[3][5]_i_2_n_0 ;\n wire [5:0]\\smallest_reg[0]__0 ;\n wire [5:0]\\smallest_reg[1]__0 ;\n wire [5:0]\\smallest_reg[2]__0 ;\n wire [5:0]\\smallest_reg[3]__0 ;\n wire stable_cnt;\n wire stable_cnt0;\n wire stable_cnt1;\n wire stable_cnt227_in;\n wire \\stable_cnt[3]_i_4_n_0 ;\n wire \\stable_cnt[3]_i_6_n_0 ;\n wire \\stable_cnt[3]_i_7_n_0 ;\n wire [0:0]\\stable_cnt_reg[3]_0 ;\n wire \\stable_cnt_reg_n_0_[1] ;\n wire \\stable_cnt_reg_n_0_[2] ;\n wire \\stable_cnt_reg_n_0_[3] ;\n wire \\stg2_r_reg[0] ;\n wire \\stg2_r_reg[4] ;\n wire \\stg2_r_reg[5] ;\n wire \\stg2_tap_cnt[3]_i_4_n_0 ;\n wire [2:0]\\stg2_tap_cnt_reg[2] ;\n wire \\stg2_target_r[4]_i_4_n_0 ;\n wire \\stg2_target_r[4]_i_5_n_0 ;\n wire \\stg2_target_r[8]_i_6_n_0 ;\n wire [1:0]\\stg2_target_r_reg[4] ;\n wire \\stg2_target_r_reg[4]_i_1_n_0 ;\n wire \\stg2_target_r_reg[4]_i_1_n_1 ;\n wire \\stg2_target_r_reg[4]_i_1_n_2 ;\n wire \\stg2_target_r_reg[4]_i_1_n_3 ;\n wire \\stg2_target_r_reg[8]_i_1_n_1 ;\n wire \\stg2_target_r_reg[8]_i_1_n_2 ;\n wire \\stg2_target_r_reg[8]_i_1_n_3 ;\n wire \\stg3_dec_val_reg[2] ;\n wire [2:0]\\stg3_dec_val_reg[2]_0 ;\n wire [2:0]\\stg3_r_reg[5] ;\n wire \\u_ocd_po_cntlr/stg2_target_r[4]_i_6_n_0 ;\n wire wait_cnt0;\n wire [3:0]wait_cnt0__0;\n wire \\wait_cnt[1]_i_1_n_0 ;\n wire \\wait_cnt_reg[0]_0 ;\n wire [3:0]wait_cnt_reg__0;\n wire wl_corse_cnt;\n wire \\wl_corse_cnt[0][0][0]_i_1_n_0 ;\n wire \\wl_corse_cnt[0][0][1]_i_1_n_0 ;\n wire \\wl_corse_cnt[0][0][2]_i_2_n_0 ;\n wire \\wl_corse_cnt[0][0][2]_i_3_n_0 ;\n wire \\wl_corse_cnt[0][0][2]_i_4_n_0 ;\n wire \\wl_corse_cnt[0][1][2]_i_1_n_0 ;\n wire \\wl_corse_cnt[0][2][2]_i_1_n_0 ;\n wire \\wl_corse_cnt[0][3][2]_i_1_n_0 ;\n wire [2:0]\\wl_corse_cnt_reg[0][0]__0 ;\n wire [2:0]\\wl_corse_cnt_reg[0][1]__0 ;\n wire [2:0]\\wl_corse_cnt_reg[0][2]__0 ;\n wire [2:0]\\wl_corse_cnt_reg[0][3]__0 ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][0][0] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][0][1] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][0][2] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][0][3] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][0][4] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][0][5] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][1][0] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][1][1] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][1][2] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][1][3] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][1][4] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][1][5] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][2][0] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][2][1] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][2][2] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][2][3] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][2][4] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][2][5] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][3][0] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][3][1] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][3][2] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][3][3] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][3][4] ;\n wire \\wl_dqs_tap_count_r_reg_n_0_[0][3][5] ;\n wire [23:0]wl_po_fine_cnt;\n wire wl_sm_start;\n wire wl_state_r1;\n wire \\wl_state_r1[0]_i_1_n_0 ;\n wire \\wl_state_r1[1]_i_1_n_0 ;\n wire \\wl_state_r1[2]_i_1_n_0 ;\n wire \\wl_state_r1[3]_i_1_n_0 ;\n wire \\wl_state_r1[4]_i_1_n_0 ;\n wire \\wl_state_r1_reg_n_0_[0] ;\n wire \\wl_state_r1_reg_n_0_[1] ;\n wire \\wl_state_r1_reg_n_0_[2] ;\n wire \\wl_state_r1_reg_n_0_[3] ;\n wire \\wl_state_r1_reg_n_0_[4] ;\n wire [5:0]wl_tap_count_r;\n wire \\wl_tap_count_r[0]_i_2_n_0 ;\n wire \\wl_tap_count_r[0]_i_3_n_0 ;\n wire \\wl_tap_count_r[1]_i_2_n_0 ;\n wire \\wl_tap_count_r[1]_i_3_n_0 ;\n wire \\wl_tap_count_r[1]_i_4_n_0 ;\n wire \\wl_tap_count_r[2]_i_2_n_0 ;\n wire \\wl_tap_count_r[2]_i_3_n_0 ;\n wire \\wl_tap_count_r[2]_i_4_n_0 ;\n wire \\wl_tap_count_r[3]_i_2_n_0 ;\n wire \\wl_tap_count_r[3]_i_3_n_0 ;\n wire \\wl_tap_count_r[3]_i_4_n_0 ;\n wire \\wl_tap_count_r[4]_i_2_n_0 ;\n wire \\wl_tap_count_r[4]_i_3_n_0 ;\n wire \\wl_tap_count_r[4]_i_4_n_0 ;\n wire \\wl_tap_count_r[5]_i_1_n_0 ;\n wire \\wl_tap_count_r[5]_i_4_n_0 ;\n wire \\wl_tap_count_r[5]_i_5_n_0 ;\n wire \\wl_tap_count_r[5]_i_6_n_0 ;\n wire \\wl_tap_count_r_reg_n_0_[0] ;\n wire \\wl_tap_count_r_reg_n_0_[1] ;\n wire \\wl_tap_count_r_reg_n_0_[2] ;\n wire \\wl_tap_count_r_reg_n_0_[3] ;\n wire \\wl_tap_count_r_reg_n_0_[4] ;\n wire \\wl_tap_count_r_reg_n_0_[5] ;\n wire wr_level_done0;\n wire wr_level_done_r1;\n wire wr_level_done_r1_reg_0;\n wire wr_level_done_r2;\n wire wr_level_done_r3;\n wire wr_level_done_r4;\n wire wr_level_done_r5;\n wire wr_level_done_r_reg_0;\n wire wr_level_start_r;\n wire wr_lvl_start_reg;\n wire wrlvl_byte_done;\n wire wrlvl_byte_done_i_1_n_0;\n wire wrlvl_byte_redo;\n wire wrlvl_byte_redo_r;\n wire wrlvl_byte_redo_reg;\n wire wrlvl_done_r_reg;\n wire wrlvl_final_mux;\n wire wrlvl_final_r;\n wire wrlvl_rank_done;\n wire wrlvl_rank_done_r_reg_0;\n wire \\wrlvl_redo_corse_inc[0]_i_1_n_0 ;\n wire \\wrlvl_redo_corse_inc[1]_i_1_n_0 ;\n wire \\wrlvl_redo_corse_inc[2]_i_1_n_0 ;\n wire \\wrlvl_redo_corse_inc[2]_i_2_n_0 ;\n wire \\wrlvl_redo_corse_inc[2]_i_3_n_0 ;\n wire \\wrlvl_redo_corse_inc[2]_i_4_n_0 ;\n wire \\wrlvl_redo_corse_inc[2]_i_7_n_0 ;\n wire [2:0]wrlvl_redo_corse_inc__0;\n wire [1:0]\\wrlvl_redo_corse_inc_reg[2]_0 ;\n wire [0:0]\\NLW_stg2_target_r_reg[4]_i_1_O_UNCONNECTED ;\n wire [3:3]\\NLW_stg2_target_r_reg[8]_i_1_CO_UNCONNECTED ;\n\n LUT6 #(\n .INIT(64'hFFFFFFBF00000000)) \n \\FSM_sequential_wl_state_r[0]_i_1 \n (.I0(\\FSM_sequential_wl_state_r[0]_i_2_n_0 ),\n .I1(out[4]),\n .I2(\\FSM_sequential_wl_state_r_reg[0]_0 ),\n .I3(out[1]),\n .I4(\\FSM_sequential_wl_state_r[0]_i_3_n_0 ),\n .I5(\\FSM_sequential_wl_state_r[0]_i_4_n_0 ),\n .O(\\FSM_sequential_wl_state_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hEEAEEEAEEEAEEFAF)) \n \\FSM_sequential_wl_state_r[0]_i_10 \n (.I0(out[4]),\n .I1(out[3]),\n .I2(out[0]),\n .I3(\\FSM_sequential_wl_state_r[3]_i_10_n_0 ),\n .I4(stable_cnt227_in),\n .I5(stable_cnt1),\n .O(\\FSM_sequential_wl_state_r[0]_i_10_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\FSM_sequential_wl_state_r[0]_i_11 \n (.I0(out[3]),\n .I1(out[0]),\n .O(\\FSM_sequential_wl_state_r[0]_i_11_n_0 ));\n LUT2 #(\n .INIT(4'h8)) \n \\FSM_sequential_wl_state_r[0]_i_13 \n (.I0(p_0_in),\n .I1(out[3]),\n .O(\\FSM_sequential_wl_state_r[0]_i_13_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair347\" *) \n LUT3 #(\n .INIT(8'hF4)) \n \\FSM_sequential_wl_state_r[0]_i_14 \n (.I0(wr_level_done_r5),\n .I1(wl_sm_start),\n .I2(wrlvl_byte_redo),\n .O(\\FSM_sequential_wl_state_r[0]_i_14_n_0 ));\n LUT5 #(\n .INIT(32'hFC7FFC7C)) \n \\FSM_sequential_wl_state_r[0]_i_15 \n (.I0(\\FSM_sequential_wl_state_r[3]_i_10_n_0 ),\n .I1(out[1]),\n .I2(out[3]),\n .I3(out[4]),\n .I4(wl_state_r1),\n .O(\\FSM_sequential_wl_state_r[0]_i_15_n_0 ));\n LUT6 #(\n .INIT(64'h3434343430333030)) \n \\FSM_sequential_wl_state_r[0]_i_16 \n (.I0(wr_level_done_r5),\n .I1(out[1]),\n .I2(out[4]),\n .I3(\\rd_data_edge_detect_r[3]_i_4_n_0 ),\n .I4(wrlvl_byte_redo),\n .I5(out[3]),\n .O(\\FSM_sequential_wl_state_r[0]_i_16_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair347\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\FSM_sequential_wl_state_r[0]_i_17 \n (.I0(wr_level_start_r),\n .I1(wl_sm_start),\n .I2(wr_level_done_r1_reg_0),\n .O(wl_state_r1));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\FSM_sequential_wl_state_r[0]_i_2 \n (.I0(\\rd_data_edge_detect_r[3]_i_5_n_0 ),\n .I1(out[0]),\n .I2(\\FSM_sequential_wl_state_r[0]_i_5_n_0 ),\n .I3(out[2]),\n .O(\\FSM_sequential_wl_state_r[0]_i_2_n_0 ));\n LUT3 #(\n .INIT(8'h7F)) \n \\FSM_sequential_wl_state_r[0]_i_3 \n (.I0(\\wl_corse_cnt[0][0][2]_i_2_n_0 ),\n .I1(\\wl_corse_cnt[0][0][0]_i_1_n_0 ),\n .I2(\\wl_corse_cnt[0][0][1]_i_1_n_0 ),\n .O(\\FSM_sequential_wl_state_r[0]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFAEAAAAAA)) \n \\FSM_sequential_wl_state_r[0]_i_4 \n (.I0(\\FSM_sequential_wl_state_r[0]_i_6_n_0 ),\n .I1(out[2]),\n .I2(out[0]),\n .I3(\\FSM_sequential_wl_state_r[3]_i_7_n_0 ),\n .I4(out[3]),\n .I5(\\FSM_sequential_wl_state_r[0]_i_7_n_0 ),\n .O(\\FSM_sequential_wl_state_r[0]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair313\" *) \n LUT3 #(\n .INIT(8'h7F)) \n \\FSM_sequential_wl_state_r[0]_i_5 \n (.I0(\\wl_tap_count_r_reg_n_0_[5] ),\n .I1(\\wl_tap_count_r_reg_n_0_[4] ),\n .I2(\\wl_tap_count_r_reg_n_0_[3] ),\n .O(\\FSM_sequential_wl_state_r[0]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hEA00000000000000)) \n \\FSM_sequential_wl_state_r[0]_i_6 \n (.I0(out[2]),\n .I1(out[3]),\n .I2(p_0_in),\n .I3(out[4]),\n .I4(\\FSM_sequential_wl_state_r[0]_i_8_n_0 ),\n .I5(\\FSM_sequential_wl_state_r[0]_i_9_n_0 ),\n .O(\\FSM_sequential_wl_state_r[0]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hB888FFFFB8880000)) \n \\FSM_sequential_wl_state_r[0]_i_7 \n (.I0(\\FSM_sequential_wl_state_r[0]_i_10_n_0 ),\n .I1(out[1]),\n .I2(\\FSM_sequential_wl_state_r[3]_i_9_n_0 ),\n .I3(\\FSM_sequential_wl_state_r[0]_i_11_n_0 ),\n .I4(out[2]),\n .I5(\\FSM_sequential_wl_state_r_reg[0]_i_12_n_0 ),\n .O(\\FSM_sequential_wl_state_r[0]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFF7FFFFFFFF)) \n \\FSM_sequential_wl_state_r[0]_i_8 \n (.I0(out[0]),\n .I1(dqs_count_r[0]),\n .I2(dqs_count_r[2]),\n .I3(\\FSM_sequential_wl_state_r[0]_i_13_n_0 ),\n .I4(\\FSM_sequential_wl_state_r[2]_i_10_n_0 ),\n .I5(dqs_count_r[1]),\n .O(\\FSM_sequential_wl_state_r[0]_i_8_n_0 ));\n LUT5 #(\n .INIT(32'hFF5D5D5D)) \n \\FSM_sequential_wl_state_r[0]_i_9 \n (.I0(out[0]),\n .I1(\\FSM_sequential_wl_state_r[3]_i_9_n_0 ),\n .I2(\\FSM_sequential_wl_state_r[0]_i_14_n_0 ),\n .I3(p_0_in),\n .I4(out[3]),\n .O(\\FSM_sequential_wl_state_r[0]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hA888A88888A88888)) \n \\FSM_sequential_wl_state_r[1]_i_1 \n (.I0(\\FSM_sequential_wl_state_r[1]_i_2_n_0 ),\n .I1(\\FSM_sequential_wl_state_r[1]_i_3_n_0 ),\n .I2(\\FSM_sequential_wl_state_r[1]_i_4_n_0 ),\n .I3(out[1]),\n .I4(out[4]),\n .I5(out[2]),\n .O(\\FSM_sequential_wl_state_r[1]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFA200)) \n \\FSM_sequential_wl_state_r[1]_i_10 \n (.I0(out[2]),\n .I1(out[4]),\n .I2(\\FSM_sequential_wl_state_r[2]_i_10_n_0 ),\n .I3(\\FSM_sequential_wl_state_r[3]_i_9_n_0 ),\n .I4(\\FSM_sequential_wl_state_r[1]_i_11_n_0 ),\n .O(\\FSM_sequential_wl_state_r[1]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'h00BB00BBFF0BFFBB)) \n \\FSM_sequential_wl_state_r[1]_i_11 \n (.I0(\\FSM_sequential_wl_state_r[0]_i_14_n_0 ),\n .I1(out[4]),\n .I2(\\rd_data_edge_detect_r[3]_i_4_n_0 ),\n .I3(out[3]),\n .I4(wrlvl_byte_redo),\n .I5(out[2]),\n .O(\\FSM_sequential_wl_state_r[1]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFDFFF)) \n \\FSM_sequential_wl_state_r[1]_i_2 \n (.I0(out[3]),\n .I1(\\FSM_sequential_wl_state_r[0]_i_3_n_0 ),\n .I2(\\FSM_sequential_wl_state_r_reg[0]_0 ),\n .I3(\\FSM_sequential_wl_state_r[1]_i_5_n_0 ),\n .I4(out[0]),\n .I5(out[1]),\n .O(\\FSM_sequential_wl_state_r[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h8F8F8F8F8F808080)) \n \\FSM_sequential_wl_state_r[1]_i_3 \n (.I0(\\FSM_sequential_wl_state_r[1]_i_6_n_0 ),\n .I1(\\FSM_sequential_wl_state_r[1]_i_7_n_0 ),\n .I2(out[0]),\n .I3(\\FSM_sequential_wl_state_r[1]_i_8_n_0 ),\n .I4(out[1]),\n .I5(\\FSM_sequential_wl_state_r[1]_i_9_n_0 ),\n .O(\\FSM_sequential_wl_state_r[1]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'h3FAAFF00)) \n \\FSM_sequential_wl_state_r[1]_i_4 \n (.I0(\\FSM_sequential_wl_state_r[3]_i_10_n_0 ),\n .I1(\\FSM_sequential_wl_state_r_reg[0]_0 ),\n .I2(\\rd_data_edge_detect_r[3]_i_5_n_0 ),\n .I3(out[4]),\n .I4(out[3]),\n .O(\\FSM_sequential_wl_state_r[1]_i_4_n_0 ));\n LUT4 #(\n .INIT(16'h4000)) \n \\FSM_sequential_wl_state_r[1]_i_5 \n (.I0(out[2]),\n .I1(\\wl_tap_count_r_reg_n_0_[3] ),\n .I2(\\wl_tap_count_r_reg_n_0_[4] ),\n .I3(\\wl_tap_count_r_reg_n_0_[5] ),\n .O(\\FSM_sequential_wl_state_r[1]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h7F7F7F7F7F7F7FFF)) \n \\FSM_sequential_wl_state_r[1]_i_6 \n (.I0(out[4]),\n .I1(wrlvl_byte_redo),\n .I2(out[2]),\n .I3(wrlvl_redo_corse_inc__0[1]),\n .I4(wrlvl_redo_corse_inc__0[0]),\n .I5(wrlvl_redo_corse_inc__0[2]),\n .O(\\FSM_sequential_wl_state_r[1]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h0007FFFF00070000)) \n \\FSM_sequential_wl_state_r[1]_i_7 \n (.I0(out[3]),\n .I1(wr_level_done_r5),\n .I2(out[4]),\n .I3(out[2]),\n .I4(out[1]),\n .I5(\\FSM_sequential_wl_state_r[1]_i_10_n_0 ),\n .O(\\FSM_sequential_wl_state_r[1]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hAAA8FFFFAAA8AAA8)) \n \\FSM_sequential_wl_state_r[1]_i_8 \n (.I0(out[4]),\n .I1(\\corse_dec[3][2]_i_2_n_0 ),\n .I2(\\corse_dec[3][2]_i_3_n_0 ),\n .I3(\\corse_dec[3][2]_i_4_n_0 ),\n .I4(\\FSM_sequential_wl_state_r[3]_i_10_n_0 ),\n .I5(out[3]),\n .O(\\FSM_sequential_wl_state_r[1]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'hAAA2A0A0AAA20000)) \n \\FSM_sequential_wl_state_r[1]_i_9 \n (.I0(out[2]),\n .I1(stable_cnt227_in),\n .I2(out[3]),\n .I3(stable_cnt1),\n .I4(out[1]),\n .I5(\\FSM_sequential_wl_state_r[2]_i_10_n_0 ),\n .O(\\FSM_sequential_wl_state_r[1]_i_9_n_0 ));\n LUT5 #(\n .INIT(32'hAAA8A8A8)) \n \\FSM_sequential_wl_state_r[2]_i_1 \n (.I0(\\FSM_sequential_wl_state_r[2]_i_2_n_0 ),\n .I1(\\FSM_sequential_wl_state_r[2]_i_3_n_0 ),\n .I2(\\FSM_sequential_wl_state_r_reg[2]_i_4_n_0 ),\n .I3(\\FSM_sequential_wl_state_r[2]_i_5_n_0 ),\n .I4(out[2]),\n .O(\\FSM_sequential_wl_state_r[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\FSM_sequential_wl_state_r[2]_i_10 \n (.I0(\\fine_inc[3][2]_i_3_n_0 ),\n .I1(\\fine_inc[3][2]_i_2_n_0 ),\n .I2(\\fine_inc[3][2]_i_4_n_0 ),\n .I3(\\fine_inc[3][5]_i_8_n_0 ),\n .I4(\\fine_inc[3][4]_i_3_n_0 ),\n .I5(\\fine_inc[3][4]_i_4_n_0 ),\n .O(\\FSM_sequential_wl_state_r[2]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'h1000100010001010)) \n \\FSM_sequential_wl_state_r[2]_i_11 \n (.I0(out[3]),\n .I1(out[0]),\n .I2(out[2]),\n .I3(out[4]),\n .I4(stable_cnt227_in),\n .I5(stable_cnt1),\n .O(\\FSM_sequential_wl_state_r[2]_i_11_n_0 ));\n LUT5 #(\n .INIT(32'h00200000)) \n \\FSM_sequential_wl_state_r[2]_i_12 \n (.I0(\\rd_data_edge_detect_r[3]_i_4_n_0 ),\n .I1(out[1]),\n .I2(out[0]),\n .I3(out[4]),\n .I4(wrlvl_byte_redo),\n .O(\\FSM_sequential_wl_state_r[2]_i_12_n_0 ));\n LUT5 #(\n .INIT(32'h10101F10)) \n \\FSM_sequential_wl_state_r[2]_i_13 \n (.I0(\\FSM_sequential_wl_state_r_reg[0]_0 ),\n .I1(out[0]),\n .I2(out[4]),\n .I3(out[1]),\n .I4(\\FSM_sequential_wl_state_r[3]_i_10_n_0 ),\n .O(\\FSM_sequential_wl_state_r[2]_i_13_n_0 ));\n LUT6 #(\n .INIT(64'h0B3B0B0B3B3B3B3B)) \n \\FSM_sequential_wl_state_r[2]_i_14 \n (.I0(out[0]),\n .I1(out[3]),\n .I2(\\FSM_sequential_wl_state_r[3]_i_9_n_0 ),\n .I3(wr_level_done_r5),\n .I4(wl_sm_start),\n .I5(out[4]),\n .O(\\FSM_sequential_wl_state_r[2]_i_14_n_0 ));\n LUT6 #(\n .INIT(64'h011F077F077F077F)) \n \\FSM_sequential_wl_state_r[2]_i_15 \n (.I0(\\wl_corse_cnt[0][0][1]_i_1_n_0 ),\n .I1(wrlvl_redo_corse_inc__0[1]),\n .I2(\\wl_corse_cnt[0][0][2]_i_2_n_0 ),\n .I3(wrlvl_redo_corse_inc__0[2]),\n .I4(wrlvl_redo_corse_inc__0[0]),\n .I5(\\wl_corse_cnt[0][0][0]_i_1_n_0 ),\n .O(\\FSM_sequential_wl_state_r[2]_i_15_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF7FFF00000000)) \n \\FSM_sequential_wl_state_r[2]_i_2 \n (.I0(\\FSM_sequential_wl_state_r[2]_i_6_n_0 ),\n .I1(out[4]),\n .I2(out[0]),\n .I3(wrlvl_byte_redo),\n .I4(out[1]),\n .I5(\\FSM_sequential_wl_state_r[2]_i_7_n_0 ),\n .O(\\FSM_sequential_wl_state_r[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFAAAAAAAE)) \n \\FSM_sequential_wl_state_r[2]_i_3 \n (.I0(\\FSM_sequential_wl_state_r[2]_i_8_n_0 ),\n .I1(out[2]),\n .I2(\\FSM_sequential_wl_state_r[2]_i_9_n_0 ),\n .I3(out[1]),\n .I4(\\FSM_sequential_wl_state_r[2]_i_10_n_0 ),\n .I5(\\FSM_sequential_wl_state_r[2]_i_11_n_0 ),\n .O(\\FSM_sequential_wl_state_r[2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hBFAFBFAFB0AFB0A0)) \n \\FSM_sequential_wl_state_r[2]_i_5 \n (.I0(out[4]),\n .I1(out[0]),\n .I2(out[1]),\n .I3(out[3]),\n .I4(wrlvl_byte_redo),\n .I5(\\FSM_sequential_wl_state_r[2]_i_14_n_0 ),\n .O(\\FSM_sequential_wl_state_r[2]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair336\" *) \n LUT3 #(\n .INIT(8'h01)) \n \\FSM_sequential_wl_state_r[2]_i_6 \n (.I0(wrlvl_redo_corse_inc__0[1]),\n .I1(wrlvl_redo_corse_inc__0[0]),\n .I2(wrlvl_redo_corse_inc__0[2]),\n .O(\\FSM_sequential_wl_state_r[2]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFDFFDFFFFFFFF)) \n \\FSM_sequential_wl_state_r[2]_i_7 \n (.I0(out[0]),\n .I1(\\FSM_sequential_wl_state_r[2]_i_15_n_0 ),\n .I2(out[2]),\n .I3(out[1]),\n .I4(out[4]),\n .I5(wrlvl_byte_redo),\n .O(\\FSM_sequential_wl_state_r[2]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h0500000035330000)) \n \\FSM_sequential_wl_state_r[2]_i_8 \n (.I0(\\FSM_sequential_wl_state_r[3]_i_10_n_0 ),\n .I1(out[4]),\n .I2(out[0]),\n .I3(out[3]),\n .I4(out[1]),\n .I5(out[2]),\n .O(\\FSM_sequential_wl_state_r[2]_i_8_n_0 ));\n LUT5 #(\n .INIT(32'h8888F888)) \n \\FSM_sequential_wl_state_r[2]_i_9 \n (.I0(out[0]),\n .I1(out[3]),\n .I2(dqs_count_r[1]),\n .I3(dqs_count_r[0]),\n .I4(dqs_count_r[2]),\n .O(\\FSM_sequential_wl_state_r[2]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFEFEAEFEAEFEA)) \n \\FSM_sequential_wl_state_r[3]_i_1 \n (.I0(\\FSM_sequential_wl_state_r[3]_i_2_n_0 ),\n .I1(\\FSM_sequential_wl_state_r[3]_i_3_n_0 ),\n .I2(out[0]),\n .I3(\\FSM_sequential_wl_state_r[3]_i_4_n_0 ),\n .I4(out[3]),\n .I5(\\FSM_sequential_wl_state_r[3]_i_5_n_0 ),\n .O(\\FSM_sequential_wl_state_r[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\FSM_sequential_wl_state_r[3]_i_10 \n (.I0(fine_dec_cnt__0[5]),\n .I1(fine_dec_cnt__0[3]),\n .I2(fine_dec_cnt__0[1]),\n .I3(fine_dec_cnt__0[0]),\n .I4(fine_dec_cnt__0[2]),\n .I5(fine_dec_cnt__0[4]),\n .O(\\FSM_sequential_wl_state_r[3]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'h0100010005AA0500)) \n \\FSM_sequential_wl_state_r[3]_i_2 \n (.I0(out[1]),\n .I1(\\FSM_sequential_wl_state_r[3]_i_6_n_0 ),\n .I2(out[2]),\n .I3(out[3]),\n .I4(out[0]),\n .I5(out[4]),\n .O(\\FSM_sequential_wl_state_r[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h6200000062626262)) \n \\FSM_sequential_wl_state_r[3]_i_3 \n (.I0(out[4]),\n .I1(out[1]),\n .I2(wr_level_done_r5),\n .I3(\\FSM_sequential_wl_state_r[3]_i_7_n_0 ),\n .I4(\\FSM_sequential_wl_state_r[3]_i_8_n_0 ),\n .I5(out[2]),\n .O(\\FSM_sequential_wl_state_r[3]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'h00400000)) \n \\FSM_sequential_wl_state_r[3]_i_4 \n (.I0(stable_cnt1),\n .I1(out[1]),\n .I2(out[2]),\n .I3(out[4]),\n .I4(stable_cnt227_in),\n .O(\\FSM_sequential_wl_state_r[3]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h33BB338830883088)) \n \\FSM_sequential_wl_state_r[3]_i_5 \n (.I0(\\FSM_sequential_wl_state_r[3]_i_9_n_0 ),\n .I1(out[0]),\n .I2(\\FSM_sequential_wl_state_r[3]_i_10_n_0 ),\n .I3(out[1]),\n .I4(\\FSM_sequential_wl_state_r[3]_i_7_n_0 ),\n .I5(out[2]),\n .O(\\FSM_sequential_wl_state_r[3]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair313\" *) \n LUT5 #(\n .INIT(32'h5555D555)) \n \\FSM_sequential_wl_state_r[3]_i_6 \n (.I0(\\FSM_sequential_wl_state_r_reg[0]_0 ),\n .I1(\\wl_tap_count_r_reg_n_0_[5] ),\n .I2(\\wl_tap_count_r_reg_n_0_[4] ),\n .I3(\\wl_tap_count_r_reg_n_0_[3] ),\n .I4(\\rd_data_edge_detect_r[3]_i_5_n_0 ),\n .O(\\FSM_sequential_wl_state_r[3]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair318\" *) \n LUT4 #(\n .INIT(16'hFFF7)) \n \\FSM_sequential_wl_state_r[3]_i_7 \n (.I0(dqs_count_r[0]),\n .I1(dqs_count_r[1]),\n .I2(\\FSM_sequential_wl_state_r[2]_i_10_n_0 ),\n .I3(dqs_count_r[2]),\n .O(\\FSM_sequential_wl_state_r[3]_i_7_n_0 ));\n LUT5 #(\n .INIT(32'h00005100)) \n \\FSM_sequential_wl_state_r[3]_i_8 \n (.I0(wrlvl_byte_redo),\n .I1(wl_sm_start),\n .I2(wr_level_done_r5),\n .I3(\\FSM_sequential_wl_state_r[3]_i_9_n_0 ),\n .I4(out[1]),\n .O(\\FSM_sequential_wl_state_r[3]_i_8_n_0 ));\n LUT3 #(\n .INIT(8'h01)) \n \\FSM_sequential_wl_state_r[3]_i_9 \n (.I0(\\corse_inc[3][0]_i_2_n_0 ),\n .I1(\\corse_inc[3][2]_i_4_n_0 ),\n .I2(\\corse_inc[3][2]_i_5_n_0 ),\n .O(\\FSM_sequential_wl_state_r[3]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFF03031D1C)) \n \\FSM_sequential_wl_state_r[4]_i_1 \n (.I0(out[0]),\n .I1(out[4]),\n .I2(out[2]),\n .I3(\\FSM_sequential_wl_state_r[4]_i_3_n_0 ),\n .I4(out[1]),\n .I5(\\FSM_sequential_wl_state_r_reg[4]_i_4_n_0 ),\n .O(\\FSM_sequential_wl_state_r[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hE0FFFF00E000FF00)) \n \\FSM_sequential_wl_state_r[4]_i_10 \n (.I0(wr_level_done_r5),\n .I1(wrlvl_byte_redo_reg),\n .I2(out[4]),\n .I3(out[0]),\n .I4(out[2]),\n .I5(\\FSM_sequential_wl_state_r[4]_i_12_n_0 ),\n .O(\\FSM_sequential_wl_state_r[4]_i_10_n_0 ));\n LUT4 #(\n .INIT(16'hF8FA)) \n \\FSM_sequential_wl_state_r[4]_i_11 \n (.I0(wr_level_done_r5),\n .I1(\\FSM_sequential_wl_state_r[2]_i_10_n_0 ),\n .I2(out[1]),\n .I3(\\FSM_sequential_wl_state_r[3]_i_9_n_0 ),\n .O(\\FSM_sequential_wl_state_r[4]_i_11_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair321\" *) \n LUT4 #(\n .INIT(16'h0010)) \n \\FSM_sequential_wl_state_r[4]_i_12 \n (.I0(incdec_wait_cnt_reg__0[1]),\n .I1(incdec_wait_cnt_reg__0[0]),\n .I2(incdec_wait_cnt_reg__0[3]),\n .I3(incdec_wait_cnt_reg__0[2]),\n .O(\\FSM_sequential_wl_state_r[4]_i_12_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF080403070804)) \n \\FSM_sequential_wl_state_r[4]_i_2 \n (.I0(out[0]),\n .I1(out[2]),\n .I2(out[3]),\n .I3(out[1]),\n .I4(out[4]),\n .I5(\\FSM_sequential_wl_state_r[4]_i_5_n_0 ),\n .O(\\FSM_sequential_wl_state_r[4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h08FF080808080808)) \n \\FSM_sequential_wl_state_r[4]_i_3 \n (.I0(early1_data_reg),\n .I1(wrlvl_byte_redo),\n .I2(wrlvl_byte_redo_r),\n .I3(wr_level_done_r1_reg_0),\n .I4(wl_sm_start),\n .I5(wr_level_start_r),\n .O(\\FSM_sequential_wl_state_r[4]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h000000000F0FBBB0)) \n \\FSM_sequential_wl_state_r[4]_i_5 \n (.I0(\\rd_data_edge_detect_r[3]_i_5_n_0 ),\n .I1(out[3]),\n .I2(out[1]),\n .I3(\\FSM_sequential_wl_state_r_reg[0]_0 ),\n .I4(out[0]),\n .I5(\\FSM_sequential_wl_state_r[4]_i_9_n_0 ),\n .O(\\FSM_sequential_wl_state_r[4]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hF0F0FFFCF0F02020)) \n \\FSM_sequential_wl_state_r[4]_i_7 \n (.I0(out[2]),\n .I1(out[4]),\n .I2(wl_sm_start),\n .I3(wrlvl_byte_redo),\n .I4(out[1]),\n .I5(\\FSM_sequential_wl_state_r[4]_i_10_n_0 ),\n .O(\\FSM_sequential_wl_state_r[4]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h22222020FFF000FF)) \n \\FSM_sequential_wl_state_r[4]_i_8 \n (.I0(\\FSM_sequential_wl_state_r[4]_i_11_n_0 ),\n .I1(out[4]),\n .I2(\\FSM_sequential_wl_state_r[4]_i_12_n_0 ),\n .I3(out[1]),\n .I4(out[0]),\n .I5(out[2]),\n .O(\\FSM_sequential_wl_state_r[4]_i_8_n_0 ));\n LUT5 #(\n .INIT(32'h00005545)) \n \\FSM_sequential_wl_state_r[4]_i_9 \n (.I0(out[3]),\n .I1(wr_level_done_r5),\n .I2(wl_sm_start),\n .I3(wrlvl_byte_redo),\n .I4(out[1]),\n .O(\\FSM_sequential_wl_state_r[4]_i_9_n_0 ));\n (* KEEP = \"yes\" *) \n FDRE \\FSM_sequential_wl_state_r_reg[0] \n (.C(CLK),\n .CE(\\FSM_sequential_wl_state_r[4]_i_1_n_0 ),\n .D(\\FSM_sequential_wl_state_r[0]_i_1_n_0 ),\n .Q(out[0]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n MUXF7 \\FSM_sequential_wl_state_r_reg[0]_i_12 \n (.I0(\\FSM_sequential_wl_state_r[0]_i_15_n_0 ),\n .I1(\\FSM_sequential_wl_state_r[0]_i_16_n_0 ),\n .O(\\FSM_sequential_wl_state_r_reg[0]_i_12_n_0 ),\n .S(out[0]));\n (* KEEP = \"yes\" *) \n FDRE \\FSM_sequential_wl_state_r_reg[1] \n (.C(CLK),\n .CE(\\FSM_sequential_wl_state_r[4]_i_1_n_0 ),\n .D(\\FSM_sequential_wl_state_r[1]_i_1_n_0 ),\n .Q(out[1]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n (* KEEP = \"yes\" *) \n FDRE \\FSM_sequential_wl_state_r_reg[2] \n (.C(CLK),\n .CE(\\FSM_sequential_wl_state_r[4]_i_1_n_0 ),\n .D(\\FSM_sequential_wl_state_r[2]_i_1_n_0 ),\n .Q(out[2]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n MUXF7 \\FSM_sequential_wl_state_r_reg[2]_i_4 \n (.I0(\\FSM_sequential_wl_state_r[2]_i_12_n_0 ),\n .I1(\\FSM_sequential_wl_state_r[2]_i_13_n_0 ),\n .O(\\FSM_sequential_wl_state_r_reg[2]_i_4_n_0 ),\n .S(out[3]));\n (* KEEP = \"yes\" *) \n FDRE \\FSM_sequential_wl_state_r_reg[3] \n (.C(CLK),\n .CE(\\FSM_sequential_wl_state_r[4]_i_1_n_0 ),\n .D(\\FSM_sequential_wl_state_r[3]_i_1_n_0 ),\n .Q(out[3]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n (* KEEP = \"yes\" *) \n FDRE \\FSM_sequential_wl_state_r_reg[4] \n (.C(CLK),\n .CE(\\FSM_sequential_wl_state_r[4]_i_1_n_0 ),\n .D(\\FSM_sequential_wl_state_r[4]_i_2_n_0 ),\n .Q(out[4]),\n .R(rstdiv0_sync_r1_reg_rep__19));\n MUXF7 \\FSM_sequential_wl_state_r_reg[4]_i_4 \n (.I0(\\FSM_sequential_wl_state_r[4]_i_7_n_0 ),\n .I1(\\FSM_sequential_wl_state_r[4]_i_8_n_0 ),\n .O(\\FSM_sequential_wl_state_r_reg[4]_i_4_n_0 ),\n .S(out[3]));\n (* SOFT_HLUTNM = \"soft_lutpair348\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\corse_cnt[0][0]_i_1 \n (.I0(corse_cnt[0]),\n .I1(\\corse_cnt[0][2]_i_3_n_0 ),\n .I2(\\corse_cnt_reg_n_0_[0][0] ),\n .O(\\corse_cnt[0][0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00F000F088F8FFF8)) \n \\corse_cnt[0][0]_i_2 \n (.I0(\\corse_cnt[0][0]_i_3_n_0 ),\n .I1(out[0]),\n .I2(\\corse_cnt[0][0]_i_4_n_0 ),\n .I3(out[2]),\n .I4(\\wl_corse_cnt[0][0][0]_i_1_n_0 ),\n .I5(out[3]),\n .O(corse_cnt[0]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\corse_cnt[0][0]_i_3 \n (.I0(\\final_coarse_tap_reg_n_0_[3][0] ),\n .I1(\\final_coarse_tap_reg_n_0_[1][0] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\final_coarse_tap_reg_n_0_[2][0] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\final_coarse_tap_reg_n_0_[0][0] ),\n .O(\\corse_cnt[0][0]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'h8830)) \n \\corse_cnt[0][0]_i_4 \n (.I0(p_0_in),\n .I1(out[0]),\n .I2(final_coarse_tap),\n .I3(out[1]),\n .O(\\corse_cnt[0][0]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\corse_cnt[0][0]_i_5 \n (.I0(\\final_coarse_tap_reg_n_0_[3][0] ),\n .I1(\\final_coarse_tap_reg_n_0_[1][0] ),\n .I2(\\po_stg2_wrcal_cnt_reg[2] [0]),\n .I3(\\final_coarse_tap_reg_n_0_[2][0] ),\n .I4(\\po_stg2_wrcal_cnt_reg[2] [1]),\n .I5(\\final_coarse_tap_reg_n_0_[0][0] ),\n .O(final_coarse_tap));\n (* SOFT_HLUTNM = \"soft_lutpair337\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\corse_cnt[0][1]_i_1 \n (.I0(corse_cnt[1]),\n .I1(\\corse_cnt[0][2]_i_3_n_0 ),\n .I2(\\corse_cnt_reg_n_0_[0][1] ),\n .O(\\corse_cnt[0][1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFF080808FF08)) \n \\corse_cnt[0][1]_i_2 \n (.I0(\\corse_cnt[0][1]_i_3_n_0 ),\n .I1(out[0]),\n .I2(out[3]),\n .I3(\\corse_cnt[0][1]_i_4_n_0 ),\n .I4(out[2]),\n .I5(\\corse_cnt[0][1]_i_5_n_0 ),\n .O(corse_cnt[1]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\corse_cnt[0][1]_i_3 \n (.I0(\\final_coarse_tap_reg_n_0_[3][1] ),\n .I1(\\final_coarse_tap_reg_n_0_[1][1] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\final_coarse_tap_reg_n_0_[2][1] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\final_coarse_tap_reg_n_0_[0][1] ),\n .O(\\corse_cnt[0][1]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'h8830)) \n \\corse_cnt[0][1]_i_4 \n (.I0(p_0_in),\n .I1(out[0]),\n .I2(\\wrlvl_redo_corse_inc_reg[2]_0 [0]),\n .I3(out[1]),\n .O(\\corse_cnt[0][1]_i_4_n_0 ));\n LUT3 #(\n .INIT(8'h06)) \n \\corse_cnt[0][1]_i_5 \n (.I0(\\wl_corse_cnt[0][0][0]_i_1_n_0 ),\n .I1(\\wl_corse_cnt[0][0][1]_i_1_n_0 ),\n .I2(out[3]),\n .O(\\corse_cnt[0][1]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair338\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\corse_cnt[0][2]_i_1 \n (.I0(corse_cnt[2]),\n .I1(\\corse_cnt[0][2]_i_3_n_0 ),\n .I2(\\corse_cnt_reg_n_0_[0][2] ),\n .O(\\corse_cnt[0][2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAA00010000)) \n \\corse_cnt[0][2]_i_10 \n (.I0(out[1]),\n .I1(dqs_count_r[2]),\n .I2(dqs_count_r[1]),\n .I3(dqs_count_r[0]),\n .I4(wrlvl_final_mux),\n .I5(out[3]),\n .O(\\corse_cnt[0][2]_i_10_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFF080808FF08)) \n \\corse_cnt[0][2]_i_2 \n (.I0(\\corse_cnt[0][2]_i_4_n_0 ),\n .I1(out[0]),\n .I2(out[3]),\n .I3(\\corse_cnt[0][2]_i_5_n_0 ),\n .I4(out[2]),\n .I5(\\corse_cnt[0][2]_i_6_n_0 ),\n .O(corse_cnt[2]));\n LUT6 #(\n .INIT(64'h0040004055400040)) \n \\corse_cnt[0][2]_i_3 \n (.I0(\\corse_cnt[0][2]_i_7_n_0 ),\n .I1(\\corse_cnt[0][2]_i_8_n_0 ),\n .I2(\\corse_cnt[0][2]_i_9_n_0 ),\n .I3(out[0]),\n .I4(\\corse_cnt[0][2]_i_10_n_0 ),\n .I5(out[2]),\n .O(\\corse_cnt[0][2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\corse_cnt[0][2]_i_4 \n (.I0(\\final_coarse_tap_reg_n_0_[3][2] ),\n .I1(\\final_coarse_tap_reg_n_0_[1][2] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\final_coarse_tap_reg_n_0_[2][2] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\final_coarse_tap_reg_n_0_[0][2] ),\n .O(\\corse_cnt[0][2]_i_4_n_0 ));\n LUT4 #(\n .INIT(16'h8830)) \n \\corse_cnt[0][2]_i_5 \n (.I0(p_0_in),\n .I1(out[0]),\n .I2(\\wrlvl_redo_corse_inc_reg[2]_0 [1]),\n .I3(out[1]),\n .O(\\corse_cnt[0][2]_i_5_n_0 ));\n LUT4 #(\n .INIT(16'h0078)) \n \\corse_cnt[0][2]_i_6 \n (.I0(\\wl_corse_cnt[0][0][1]_i_1_n_0 ),\n .I1(\\wl_corse_cnt[0][0][0]_i_1_n_0 ),\n .I2(\\wl_corse_cnt[0][0][2]_i_2_n_0 ),\n .I3(out[3]),\n .O(\\corse_cnt[0][2]_i_6_n_0 ));\n LUT3 #(\n .INIT(8'hBC)) \n \\corse_cnt[0][2]_i_7 \n (.I0(p_0_in),\n .I1(out[3]),\n .I2(out[4]),\n .O(\\corse_cnt[0][2]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'h202020202F202020)) \n \\corse_cnt[0][2]_i_8 \n (.I0(\\fine_inc[0][5]_i_3_n_0 ),\n .I1(\\dqs_count_r[0]_i_8_n_0 ),\n .I2(out[2]),\n .I3(\\po_stg2_wrcal_cnt_reg[0] ),\n .I4(done_dqs_dec239_out),\n .I5(\\po_stg2_wrcal_cnt_reg[2] [1]),\n .O(\\corse_cnt[0][2]_i_8_n_0 ));\n LUT2 #(\n .INIT(4'h1)) \n \\corse_cnt[0][2]_i_9 \n (.I0(out[3]),\n .I1(out[1]),\n .O(\\corse_cnt[0][2]_i_9_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair335\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\corse_cnt[1][0]_i_1 \n (.I0(corse_cnt[0]),\n .I1(\\corse_cnt[1][2]_i_2_n_0 ),\n .I2(\\corse_cnt_reg_n_0_[1][0] ),\n .O(\\corse_cnt[1][0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair339\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\corse_cnt[1][1]_i_1 \n (.I0(corse_cnt[1]),\n .I1(\\corse_cnt[1][2]_i_2_n_0 ),\n .I2(\\corse_cnt_reg_n_0_[1][1] ),\n .O(\\corse_cnt[1][1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair340\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\corse_cnt[1][2]_i_1 \n (.I0(corse_cnt[2]),\n .I1(\\corse_cnt[1][2]_i_2_n_0 ),\n .I2(\\corse_cnt_reg_n_0_[1][2] ),\n .O(\\corse_cnt[1][2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0040004055400040)) \n \\corse_cnt[1][2]_i_2 \n (.I0(\\corse_cnt[0][2]_i_7_n_0 ),\n .I1(\\corse_cnt[1][2]_i_3_n_0 ),\n .I2(\\corse_cnt[0][2]_i_9_n_0 ),\n .I3(out[0]),\n .I4(\\corse_cnt[1][2]_i_4_n_0 ),\n .I5(out[2]),\n .O(\\corse_cnt[1][2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h8A008A008A008AFF)) \n \\corse_cnt[1][2]_i_3 \n (.I0(\\fine_inc[1][5]_i_3_n_0 ),\n .I1(wrlvl_byte_redo),\n .I2(wr_level_done_r5),\n .I3(out[2]),\n .I4(\\po_stg2_wrcal_cnt_reg[2] [1]),\n .I5(\\po_stg2_wrcal_cnt_reg[2]_0 ),\n .O(\\corse_cnt[1][2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAA00100000)) \n \\corse_cnt[1][2]_i_4 \n (.I0(out[1]),\n .I1(dqs_count_r[2]),\n .I2(dqs_count_r[0]),\n .I3(dqs_count_r[1]),\n .I4(wrlvl_final_mux),\n .I5(out[3]),\n .O(\\corse_cnt[1][2]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair348\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\corse_cnt[2][0]_i_1 \n (.I0(corse_cnt[0]),\n .I1(\\corse_cnt[2][2]_i_2_n_0 ),\n .I2(\\corse_cnt_reg_n_0_[2][0] ),\n .O(\\corse_cnt[2][0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair339\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\corse_cnt[2][1]_i_1 \n (.I0(corse_cnt[1]),\n .I1(\\corse_cnt[2][2]_i_2_n_0 ),\n .I2(\\corse_cnt_reg_n_0_[2][1] ),\n .O(\\corse_cnt[2][1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair338\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\corse_cnt[2][2]_i_1 \n (.I0(corse_cnt[2]),\n .I1(\\corse_cnt[2][2]_i_2_n_0 ),\n .I2(\\corse_cnt_reg_n_0_[2][2] ),\n .O(\\corse_cnt[2][2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0040004055400040)) \n \\corse_cnt[2][2]_i_2 \n (.I0(\\corse_cnt[0][2]_i_7_n_0 ),\n .I1(\\corse_cnt[2][2]_i_3_n_0 ),\n .I2(\\corse_cnt[0][2]_i_9_n_0 ),\n .I3(out[0]),\n .I4(\\corse_cnt[2][2]_i_4_n_0 ),\n .I5(out[2]),\n .O(\\corse_cnt[2][2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h202020202020202F)) \n \\corse_cnt[2][2]_i_3 \n (.I0(\\fine_inc[2][5]_i_3_n_0 ),\n .I1(\\dqs_count_r[0]_i_8_n_0 ),\n .I2(out[2]),\n .I3(\\po_stg2_wrcal_cnt_reg[2] [2]),\n .I4(\\po_stg2_wrcal_cnt_reg[2] [0]),\n .I5(\\po_stg2_wrcal_cnt_reg[1] ),\n .O(\\corse_cnt[2][2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAA00100000)) \n \\corse_cnt[2][2]_i_4 \n (.I0(out[1]),\n .I1(dqs_count_r[2]),\n .I2(dqs_count_r[1]),\n .I3(dqs_count_r[0]),\n .I4(wrlvl_final_mux),\n .I5(out[3]),\n .O(\\corse_cnt[2][2]_i_4_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair335\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\corse_cnt[3][0]_i_1 \n (.I0(corse_cnt[0]),\n .I1(\\corse_cnt[3][2]_i_2_n_0 ),\n .I2(\\corse_cnt_reg_n_0_[3][0] ),\n .O(\\corse_cnt[3][0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair337\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\corse_cnt[3][1]_i_1 \n (.I0(corse_cnt[1]),\n .I1(\\corse_cnt[3][2]_i_2_n_0 ),\n .I2(\\corse_cnt_reg_n_0_[3][1] ),\n .O(\\corse_cnt[3][1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair340\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\corse_cnt[3][2]_i_1 \n (.I0(corse_cnt[2]),\n .I1(\\corse_cnt[3][2]_i_2_n_0 ),\n .I2(\\corse_cnt_reg_n_0_[3][2] ),\n .O(\\corse_cnt[3][2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000455550004)) \n \\corse_cnt[3][2]_i_2 \n (.I0(\\corse_cnt[0][2]_i_7_n_0 ),\n .I1(\\corse_cnt[3][2]_i_3_n_0 ),\n .I2(out[3]),\n .I3(out[1]),\n .I4(out[0]),\n .I5(\\corse_cnt[3][2]_i_4_n_0 ),\n .O(\\corse_cnt[3][2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h8A008A008AFF8A00)) \n \\corse_cnt[3][2]_i_3 \n (.I0(\\fine_inc[3][5]_i_5_n_0 ),\n .I1(wrlvl_byte_redo),\n .I2(wr_level_done_r5),\n .I3(out[2]),\n .I4(\\po_stg2_wrcal_cnt_reg[2] [1]),\n .I5(\\po_stg2_wrcal_cnt_reg[2]_0 ),\n .O(\\corse_cnt[3][2]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'hBBBBEFFF)) \n \\corse_cnt[3][2]_i_4 \n (.I0(out[2]),\n .I1(out[3]),\n .I2(wrlvl_final_mux),\n .I3(\\fine_inc[3][5]_i_5_n_0 ),\n .I4(out[1]),\n .O(\\corse_cnt[3][2]_i_4_n_0 ));\n FDRE \\corse_cnt_reg[0][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_cnt[0][0]_i_1_n_0 ),\n .Q(\\corse_cnt_reg_n_0_[0][0] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\corse_cnt_reg[0][1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_cnt[0][1]_i_1_n_0 ),\n .Q(\\corse_cnt_reg_n_0_[0][1] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\corse_cnt_reg[0][2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_cnt[0][2]_i_1_n_0 ),\n .Q(\\corse_cnt_reg_n_0_[0][2] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\corse_cnt_reg[1][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_cnt[1][0]_i_1_n_0 ),\n .Q(\\corse_cnt_reg_n_0_[1][0] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\corse_cnt_reg[1][1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_cnt[1][1]_i_1_n_0 ),\n .Q(\\corse_cnt_reg_n_0_[1][1] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\corse_cnt_reg[1][2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_cnt[1][2]_i_1_n_0 ),\n .Q(\\corse_cnt_reg_n_0_[1][2] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\corse_cnt_reg[2][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_cnt[2][0]_i_1_n_0 ),\n .Q(\\corse_cnt_reg_n_0_[2][0] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\corse_cnt_reg[2][1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_cnt[2][1]_i_1_n_0 ),\n .Q(\\corse_cnt_reg_n_0_[2][1] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\corse_cnt_reg[2][2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_cnt[2][2]_i_1_n_0 ),\n .Q(\\corse_cnt_reg_n_0_[2][2] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\corse_cnt_reg[3][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_cnt[3][0]_i_1_n_0 ),\n .Q(\\corse_cnt_reg_n_0_[3][0] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\corse_cnt_reg[3][1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_cnt[3][1]_i_1_n_0 ),\n .Q(\\corse_cnt_reg_n_0_[3][1] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\corse_cnt_reg[3][2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_cnt[3][2]_i_1_n_0 ),\n .Q(\\corse_cnt_reg_n_0_[3][2] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n LUT6 #(\n .INIT(64'h000EFFFF000E0000)) \n \\corse_dec[0][0]_i_1 \n (.I0(\\corse_dec[3][2]_i_3_n_0 ),\n .I1(\\corse_dec[3][2]_i_4_n_0 ),\n .I2(\\corse_dec[3][2]_i_2_n_0 ),\n .I3(out[3]),\n .I4(\\corse_dec[0][2]_i_2_n_0 ),\n .I5(\\corse_dec_reg_n_0_[0][0] ),\n .O(\\corse_dec[0][0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00C2FFFF00C20000)) \n \\corse_dec[0][1]_i_1 \n (.I0(\\corse_dec[3][2]_i_3_n_0 ),\n .I1(\\corse_dec[3][2]_i_4_n_0 ),\n .I2(\\corse_dec[3][2]_i_2_n_0 ),\n .I3(out[3]),\n .I4(\\corse_dec[0][2]_i_2_n_0 ),\n .I5(\\corse_dec_reg_n_0_[0][1] ),\n .O(\\corse_dec[0][1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00C8FFFF00C80000)) \n \\corse_dec[0][2]_i_1 \n (.I0(\\corse_dec[3][2]_i_2_n_0 ),\n .I1(\\corse_dec[3][2]_i_3_n_0 ),\n .I2(\\corse_dec[3][2]_i_4_n_0 ),\n .I3(out[3]),\n .I4(\\corse_dec[0][2]_i_2_n_0 ),\n .I5(\\corse_dec_reg_n_0_[0][2] ),\n .O(\\corse_dec[0][2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0001000000000000)) \n \\corse_dec[0][2]_i_2 \n (.I0(out[0]),\n .I1(out[1]),\n .I2(out[2]),\n .I3(out[3]),\n .I4(out[4]),\n .I5(\\fine_inc[0][5]_i_3_n_0 ),\n .O(\\corse_dec[0][2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h000EFFFF000E0000)) \n \\corse_dec[1][0]_i_1 \n (.I0(\\corse_dec[3][2]_i_3_n_0 ),\n .I1(\\corse_dec[3][2]_i_4_n_0 ),\n .I2(\\corse_dec[3][2]_i_2_n_0 ),\n .I3(out[3]),\n .I4(\\corse_dec[1][2]_i_2_n_0 ),\n .I5(\\corse_dec_reg_n_0_[1][0] ),\n .O(\\corse_dec[1][0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00C2FFFF00C20000)) \n \\corse_dec[1][1]_i_1 \n (.I0(\\corse_dec[3][2]_i_3_n_0 ),\n .I1(\\corse_dec[3][2]_i_4_n_0 ),\n .I2(\\corse_dec[3][2]_i_2_n_0 ),\n .I3(out[3]),\n .I4(\\corse_dec[1][2]_i_2_n_0 ),\n .I5(\\corse_dec_reg_n_0_[1][1] ),\n .O(\\corse_dec[1][1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00C8FFFF00C80000)) \n \\corse_dec[1][2]_i_1 \n (.I0(\\corse_dec[3][2]_i_2_n_0 ),\n .I1(\\corse_dec[3][2]_i_3_n_0 ),\n .I2(\\corse_dec[3][2]_i_4_n_0 ),\n .I3(out[3]),\n .I4(\\corse_dec[1][2]_i_2_n_0 ),\n .I5(\\corse_dec_reg_n_0_[1][2] ),\n .O(\\corse_dec[1][2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0001000000000000)) \n \\corse_dec[1][2]_i_2 \n (.I0(out[0]),\n .I1(out[1]),\n .I2(out[2]),\n .I3(out[3]),\n .I4(out[4]),\n .I5(\\fine_inc[1][5]_i_3_n_0 ),\n .O(\\corse_dec[1][2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h000EFFFF000E0000)) \n \\corse_dec[2][0]_i_1 \n (.I0(\\corse_dec[3][2]_i_3_n_0 ),\n .I1(\\corse_dec[3][2]_i_4_n_0 ),\n .I2(\\corse_dec[3][2]_i_2_n_0 ),\n .I3(out[3]),\n .I4(\\corse_dec[2][2]_i_2_n_0 ),\n .I5(\\corse_dec_reg_n_0_[2][0] ),\n .O(\\corse_dec[2][0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00C2FFFF00C20000)) \n \\corse_dec[2][1]_i_1 \n (.I0(\\corse_dec[3][2]_i_3_n_0 ),\n .I1(\\corse_dec[3][2]_i_4_n_0 ),\n .I2(\\corse_dec[3][2]_i_2_n_0 ),\n .I3(out[3]),\n .I4(\\corse_dec[2][2]_i_2_n_0 ),\n .I5(\\corse_dec_reg_n_0_[2][1] ),\n .O(\\corse_dec[2][1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00C8FFFF00C80000)) \n \\corse_dec[2][2]_i_1 \n (.I0(\\corse_dec[3][2]_i_2_n_0 ),\n .I1(\\corse_dec[3][2]_i_3_n_0 ),\n .I2(\\corse_dec[3][2]_i_4_n_0 ),\n .I3(out[3]),\n .I4(\\corse_dec[2][2]_i_2_n_0 ),\n .I5(\\corse_dec_reg_n_0_[2][2] ),\n .O(\\corse_dec[2][2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0001000000000000)) \n \\corse_dec[2][2]_i_2 \n (.I0(out[0]),\n .I1(out[1]),\n .I2(out[2]),\n .I3(out[3]),\n .I4(out[4]),\n .I5(\\fine_inc[2][5]_i_3_n_0 ),\n .O(\\corse_dec[2][2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h000EFFFF000E0000)) \n \\corse_dec[3][0]_i_1 \n (.I0(\\corse_dec[3][2]_i_3_n_0 ),\n .I1(\\corse_dec[3][2]_i_4_n_0 ),\n .I2(\\corse_dec[3][2]_i_2_n_0 ),\n .I3(out[3]),\n .I4(\\corse_dec[3][2]_i_5_n_0 ),\n .I5(\\corse_dec_reg_n_0_[3][0] ),\n .O(\\corse_dec[3][0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00C2FFFF00C20000)) \n \\corse_dec[3][1]_i_1 \n (.I0(\\corse_dec[3][2]_i_3_n_0 ),\n .I1(\\corse_dec[3][2]_i_4_n_0 ),\n .I2(\\corse_dec[3][2]_i_2_n_0 ),\n .I3(out[3]),\n .I4(\\corse_dec[3][2]_i_5_n_0 ),\n .I5(\\corse_dec_reg_n_0_[3][1] ),\n .O(\\corse_dec[3][1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00C8FFFF00C80000)) \n \\corse_dec[3][2]_i_1 \n (.I0(\\corse_dec[3][2]_i_2_n_0 ),\n .I1(\\corse_dec[3][2]_i_3_n_0 ),\n .I2(\\corse_dec[3][2]_i_4_n_0 ),\n .I3(out[3]),\n .I4(\\corse_dec[3][2]_i_5_n_0 ),\n .I5(\\corse_dec_reg_n_0_[3][2] ),\n .O(\\corse_dec[3][2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\corse_dec[3][2]_i_2 \n (.I0(\\corse_dec_reg_n_0_[3][0] ),\n .I1(\\corse_dec_reg_n_0_[1][0] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\corse_dec_reg_n_0_[2][0] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\corse_dec_reg_n_0_[0][0] ),\n .O(\\corse_dec[3][2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\corse_dec[3][2]_i_3 \n (.I0(\\corse_dec_reg_n_0_[3][2] ),\n .I1(\\corse_dec_reg_n_0_[1][2] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\corse_dec_reg_n_0_[2][2] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\corse_dec_reg_n_0_[0][2] ),\n .O(\\corse_dec[3][2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\corse_dec[3][2]_i_4 \n (.I0(\\corse_dec_reg_n_0_[3][1] ),\n .I1(\\corse_dec_reg_n_0_[1][1] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\corse_dec_reg_n_0_[2][1] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\corse_dec_reg_n_0_[0][1] ),\n .O(\\corse_dec[3][2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h0001000000000000)) \n \\corse_dec[3][2]_i_5 \n (.I0(out[0]),\n .I1(out[1]),\n .I2(out[2]),\n .I3(out[3]),\n .I4(out[4]),\n .I5(\\fine_inc[3][5]_i_5_n_0 ),\n .O(\\corse_dec[3][2]_i_5_n_0 ));\n FDRE \\corse_dec_reg[0][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_dec[0][0]_i_1_n_0 ),\n .Q(\\corse_dec_reg_n_0_[0][0] ),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\corse_dec_reg[0][1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_dec[0][1]_i_1_n_0 ),\n .Q(\\corse_dec_reg_n_0_[0][1] ),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\corse_dec_reg[0][2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_dec[0][2]_i_1_n_0 ),\n .Q(\\corse_dec_reg_n_0_[0][2] ),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\corse_dec_reg[1][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_dec[1][0]_i_1_n_0 ),\n .Q(\\corse_dec_reg_n_0_[1][0] ),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\corse_dec_reg[1][1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_dec[1][1]_i_1_n_0 ),\n .Q(\\corse_dec_reg_n_0_[1][1] ),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\corse_dec_reg[1][2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_dec[1][2]_i_1_n_0 ),\n .Q(\\corse_dec_reg_n_0_[1][2] ),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\corse_dec_reg[2][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_dec[2][0]_i_1_n_0 ),\n .Q(\\corse_dec_reg_n_0_[2][0] ),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\corse_dec_reg[2][1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_dec[2][1]_i_1_n_0 ),\n .Q(\\corse_dec_reg_n_0_[2][1] ),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\corse_dec_reg[2][2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_dec[2][2]_i_1_n_0 ),\n .Q(\\corse_dec_reg_n_0_[2][2] ),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\corse_dec_reg[3][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_dec[3][0]_i_1_n_0 ),\n .Q(\\corse_dec_reg_n_0_[3][0] ),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\corse_dec_reg[3][1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_dec[3][1]_i_1_n_0 ),\n .Q(\\corse_dec_reg_n_0_[3][1] ),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\corse_dec_reg[3][2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_dec[3][2]_i_1_n_0 ),\n .Q(\\corse_dec_reg_n_0_[3][2] ),\n .R(rstdiv0_sync_r1_reg_rep__15));\n LUT6 #(\n .INIT(64'h5011FFFF50110000)) \n \\corse_inc[0][0]_i_1 \n (.I0(out[4]),\n .I1(\\corse_inc[3][0]_i_2_n_0 ),\n .I2(\\final_coarse_tap_reg_n_0_[0][0] ),\n .I3(out[0]),\n .I4(\\corse_inc[0][2]_i_2_n_0 ),\n .I5(\\corse_inc_reg_n_0_[0][0] ),\n .O(\\corse_inc[0][0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h2F20FFFF2F200000)) \n \\corse_inc[0][1]_i_1 \n (.I0(\\final_coarse_tap_reg_n_0_[0][1] ),\n .I1(out[4]),\n .I2(out[0]),\n .I3(\\corse_inc[3][1]_i_2_n_0 ),\n .I4(\\corse_inc[0][2]_i_2_n_0 ),\n .I5(\\corse_inc_reg_n_0_[0][1] ),\n .O(\\corse_inc[0][1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h2F20FFFF2F200000)) \n \\corse_inc[0][2]_i_1 \n (.I0(\\final_coarse_tap_reg_n_0_[0][2] ),\n .I1(out[4]),\n .I2(out[0]),\n .I3(\\corse_inc[3][2]_i_2_n_0 ),\n .I4(\\corse_inc[0][2]_i_2_n_0 ),\n .I5(\\corse_inc_reg_n_0_[0][2] ),\n .O(\\corse_inc[0][2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0020002088200020)) \n \\corse_inc[0][2]_i_2 \n (.I0(\\corse_inc[3][2]_i_6_n_0 ),\n .I1(out[3]),\n .I2(\\corse_inc[0][2]_i_3_n_0 ),\n .I3(out[0]),\n .I4(wr_level_done_r4),\n .I5(wr_level_done_r5),\n .O(\\corse_inc[0][2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000002)) \n \\corse_inc[0][2]_i_3 \n (.I0(wr_level_done_r5),\n .I1(wrlvl_byte_redo),\n .I2(dqs_count_r[2]),\n .I3(dqs_count_r[1]),\n .I4(dqs_count_r[0]),\n .I5(\\FSM_sequential_wl_state_r[3]_i_9_n_0 ),\n .O(\\corse_inc[0][2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h5011FFFF50110000)) \n \\corse_inc[1][0]_i_1 \n (.I0(out[4]),\n .I1(\\corse_inc[3][0]_i_2_n_0 ),\n .I2(\\final_coarse_tap_reg_n_0_[1][0] ),\n .I3(out[0]),\n .I4(\\corse_inc[1][2]_i_2_n_0 ),\n .I5(\\corse_inc_reg_n_0_[1][0] ),\n .O(\\corse_inc[1][0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h2F20FFFF2F200000)) \n \\corse_inc[1][1]_i_1 \n (.I0(\\final_coarse_tap_reg_n_0_[1][1] ),\n .I1(out[4]),\n .I2(out[0]),\n .I3(\\corse_inc[3][1]_i_2_n_0 ),\n .I4(\\corse_inc[1][2]_i_2_n_0 ),\n .I5(\\corse_inc_reg_n_0_[1][1] ),\n .O(\\corse_inc[1][1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h2F20FFFF2F200000)) \n \\corse_inc[1][2]_i_1 \n (.I0(\\final_coarse_tap_reg_n_0_[1][2] ),\n .I1(out[4]),\n .I2(out[0]),\n .I3(\\corse_inc[3][2]_i_2_n_0 ),\n .I4(\\corse_inc[1][2]_i_2_n_0 ),\n .I5(\\corse_inc_reg_n_0_[1][2] ),\n .O(\\corse_inc[1][2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0020002088200020)) \n \\corse_inc[1][2]_i_2 \n (.I0(\\corse_inc[3][2]_i_6_n_0 ),\n .I1(out[3]),\n .I2(\\corse_inc[1][2]_i_3_n_0 ),\n .I3(out[0]),\n .I4(wr_level_done_r4),\n .I5(wr_level_done_r5),\n .O(\\corse_inc[1][2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000200)) \n \\corse_inc[1][2]_i_3 \n (.I0(wr_level_done_r5),\n .I1(wrlvl_byte_redo),\n .I2(dqs_count_r[2]),\n .I3(dqs_count_r[0]),\n .I4(dqs_count_r[1]),\n .I5(\\FSM_sequential_wl_state_r[3]_i_9_n_0 ),\n .O(\\corse_inc[1][2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h5011FFFF50110000)) \n \\corse_inc[2][0]_i_1 \n (.I0(out[4]),\n .I1(\\corse_inc[3][0]_i_2_n_0 ),\n .I2(\\final_coarse_tap_reg_n_0_[2][0] ),\n .I3(out[0]),\n .I4(\\corse_inc[2][2]_i_2_n_0 ),\n .I5(\\corse_inc_reg_n_0_[2][0] ),\n .O(\\corse_inc[2][0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h2F20FFFF2F200000)) \n \\corse_inc[2][1]_i_1 \n (.I0(\\final_coarse_tap_reg_n_0_[2][1] ),\n .I1(out[4]),\n .I2(out[0]),\n .I3(\\corse_inc[3][1]_i_2_n_0 ),\n .I4(\\corse_inc[2][2]_i_2_n_0 ),\n .I5(\\corse_inc_reg_n_0_[2][1] ),\n .O(\\corse_inc[2][1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h2F20FFFF2F200000)) \n \\corse_inc[2][2]_i_1 \n (.I0(\\final_coarse_tap_reg_n_0_[2][2] ),\n .I1(out[4]),\n .I2(out[0]),\n .I3(\\corse_inc[3][2]_i_2_n_0 ),\n .I4(\\corse_inc[2][2]_i_2_n_0 ),\n .I5(\\corse_inc_reg_n_0_[2][2] ),\n .O(\\corse_inc[2][2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0020002088200020)) \n \\corse_inc[2][2]_i_2 \n (.I0(\\corse_inc[3][2]_i_6_n_0 ),\n .I1(out[3]),\n .I2(\\corse_inc[2][2]_i_3_n_0 ),\n .I3(out[0]),\n .I4(wr_level_done_r4),\n .I5(wr_level_done_r5),\n .O(\\corse_inc[2][2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000200)) \n \\corse_inc[2][2]_i_3 \n (.I0(wr_level_done_r5),\n .I1(wrlvl_byte_redo),\n .I2(dqs_count_r[2]),\n .I3(dqs_count_r[1]),\n .I4(dqs_count_r[0]),\n .I5(\\FSM_sequential_wl_state_r[3]_i_9_n_0 ),\n .O(\\corse_inc[2][2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h5011FFFF50110000)) \n \\corse_inc[3][0]_i_1 \n (.I0(out[4]),\n .I1(\\corse_inc[3][0]_i_2_n_0 ),\n .I2(\\final_coarse_tap_reg_n_0_[3][0] ),\n .I3(out[0]),\n .I4(\\corse_inc[3][2]_i_3_n_0 ),\n .I5(\\corse_inc_reg_n_0_[3][0] ),\n .O(\\corse_inc[3][0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hF0FFF000AACCAACC)) \n \\corse_inc[3][0]_i_2 \n (.I0(\\corse_inc_reg_n_0_[2][0] ),\n .I1(\\corse_inc_reg_n_0_[0][0] ),\n .I2(\\corse_inc_reg_n_0_[3][0] ),\n .I3(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I4(\\corse_inc_reg_n_0_[1][0] ),\n .I5(\\dqs_count_r_reg[0]_rep_n_0 ),\n .O(\\corse_inc[3][0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h2F20FFFF2F200000)) \n \\corse_inc[3][1]_i_1 \n (.I0(\\final_coarse_tap_reg_n_0_[3][1] ),\n .I1(out[4]),\n .I2(out[0]),\n .I3(\\corse_inc[3][1]_i_2_n_0 ),\n .I4(\\corse_inc[3][2]_i_3_n_0 ),\n .I5(\\corse_inc_reg_n_0_[3][1] ),\n .O(\\corse_inc[3][1]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h09)) \n \\corse_inc[3][1]_i_2 \n (.I0(\\corse_inc[3][0]_i_2_n_0 ),\n .I1(\\corse_inc[3][2]_i_4_n_0 ),\n .I2(out[4]),\n .O(\\corse_inc[3][1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h2F20FFFF2F200000)) \n \\corse_inc[3][2]_i_1 \n (.I0(\\final_coarse_tap_reg_n_0_[3][2] ),\n .I1(out[4]),\n .I2(out[0]),\n .I3(\\corse_inc[3][2]_i_2_n_0 ),\n .I4(\\corse_inc[3][2]_i_3_n_0 ),\n .I5(\\corse_inc_reg_n_0_[3][2] ),\n .O(\\corse_inc[3][2]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h00E1)) \n \\corse_inc[3][2]_i_2 \n (.I0(\\corse_inc[3][2]_i_4_n_0 ),\n .I1(\\corse_inc[3][0]_i_2_n_0 ),\n .I2(\\corse_inc[3][2]_i_5_n_0 ),\n .I3(out[4]),\n .O(\\corse_inc[3][2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0020002088200020)) \n \\corse_inc[3][2]_i_3 \n (.I0(\\corse_inc[3][2]_i_6_n_0 ),\n .I1(out[3]),\n .I2(\\corse_inc[3][2]_i_7_n_0 ),\n .I3(out[0]),\n .I4(wr_level_done_r4),\n .I5(wr_level_done_r5),\n .O(\\corse_inc[3][2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\corse_inc[3][2]_i_4 \n (.I0(\\corse_inc_reg_n_0_[3][1] ),\n .I1(\\corse_inc_reg_n_0_[1][1] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\corse_inc_reg_n_0_[2][1] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\corse_inc_reg_n_0_[0][1] ),\n .O(\\corse_inc[3][2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\corse_inc[3][2]_i_5 \n (.I0(\\corse_inc_reg_n_0_[3][2] ),\n .I1(\\corse_inc_reg_n_0_[1][2] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\corse_inc_reg_n_0_[2][2] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\corse_inc_reg_n_0_[0][2] ),\n .O(\\corse_inc[3][2]_i_5_n_0 ));\n LUT3 #(\n .INIT(8'h02)) \n \\corse_inc[3][2]_i_6 \n (.I0(out[2]),\n .I1(out[4]),\n .I2(out[1]),\n .O(\\corse_inc[3][2]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h0000000002000000)) \n \\corse_inc[3][2]_i_7 \n (.I0(wr_level_done_r5),\n .I1(wrlvl_byte_redo),\n .I2(dqs_count_r[2]),\n .I3(dqs_count_r[1]),\n .I4(dqs_count_r[0]),\n .I5(\\FSM_sequential_wl_state_r[3]_i_9_n_0 ),\n .O(\\corse_inc[3][2]_i_7_n_0 ));\n FDRE \\corse_inc_reg[0][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_inc[0][0]_i_1_n_0 ),\n .Q(\\corse_inc_reg_n_0_[0][0] ),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\corse_inc_reg[0][1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_inc[0][1]_i_1_n_0 ),\n .Q(\\corse_inc_reg_n_0_[0][1] ),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\corse_inc_reg[0][2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_inc[0][2]_i_1_n_0 ),\n .Q(\\corse_inc_reg_n_0_[0][2] ),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\corse_inc_reg[1][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_inc[1][0]_i_1_n_0 ),\n .Q(\\corse_inc_reg_n_0_[1][0] ),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\corse_inc_reg[1][1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_inc[1][1]_i_1_n_0 ),\n .Q(\\corse_inc_reg_n_0_[1][1] ),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\corse_inc_reg[1][2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_inc[1][2]_i_1_n_0 ),\n .Q(\\corse_inc_reg_n_0_[1][2] ),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\corse_inc_reg[2][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_inc[2][0]_i_1_n_0 ),\n .Q(\\corse_inc_reg_n_0_[2][0] ),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\corse_inc_reg[2][1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_inc[2][1]_i_1_n_0 ),\n .Q(\\corse_inc_reg_n_0_[2][1] ),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\corse_inc_reg[2][2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_inc[2][2]_i_1_n_0 ),\n .Q(\\corse_inc_reg_n_0_[2][2] ),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\corse_inc_reg[3][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_inc[3][0]_i_1_n_0 ),\n .Q(\\corse_inc_reg_n_0_[3][0] ),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\corse_inc_reg[3][1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_inc[3][1]_i_1_n_0 ),\n .Q(\\corse_inc_reg_n_0_[3][1] ),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\corse_inc_reg[3][2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\corse_inc[3][2]_i_1_n_0 ),\n .Q(\\corse_inc_reg_n_0_[3][2] ),\n .R(rstdiv0_sync_r1_reg_rep__15));\n LUT3 #(\n .INIT(8'hBF)) \n \\ctl_lane_cnt[2]_i_2 \n (.I0(rstdiv0_sync_r1_reg_rep__25),\n .I1(dqs_po_dec_done),\n .I2(pi_fine_dly_dec_done),\n .O(p_1_in));\n LUT5 #(\n .INIT(32'h77770777)) \n dq_cnt_inc_i_2\n (.I0(wrlvl_byte_redo),\n .I1(out[3]),\n .I2(dqs_count_r[0]),\n .I3(dqs_count_r[1]),\n .I4(dqs_count_r[2]),\n .O(dq_cnt_inc_reg_0));\n FDSE dq_cnt_inc_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_wl_state_r_reg[1]_0 ),\n .Q(p_0_in),\n .S(rstdiv0_sync_r1_reg_rep__15));\n LUT6 #(\n .INIT(64'hF444FFFFF4440000)) \n \\dqs_count_r[0]_i_1 \n (.I0(out[4]),\n .I1(\\dqs_count_r_reg[0]_i_2_n_0 ),\n .I2(\\dqs_count_r_reg[0]_i_3_n_0 ),\n .I3(out[0]),\n .I4(\\dqs_count_r[2]_i_5_n_0 ),\n .I5(\\dqs_count_r_reg[0]_rep_n_0 ),\n .O(\\dqs_count_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hCACC0A00CACCCACC)) \n \\dqs_count_r[0]_i_4 \n (.I0(\\po_stg2_wrcal_cnt_reg[2] [0]),\n .I1(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I2(wrlvl_byte_redo_r),\n .I3(wrlvl_byte_redo),\n .I4(wrlvl_final_r),\n .I5(wrlvl_final_mux),\n .O(\\dqs_count_r[0]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hBFBFBFB0000F000F)) \n \\dqs_count_r[0]_i_5 \n (.I0(wr_level_done_r5),\n .I1(wr_level_done_r4),\n .I2(out[0]),\n .I3(\\FSM_sequential_wl_state_r[2]_i_10_n_0 ),\n .I4(\\fine_inc[3][5]_i_5_n_0 ),\n .I5(dqs_count_r[0]),\n .O(\\dqs_count_r[0]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFBFFF80000FF03FF)) \n \\dqs_count_r[0]_i_6 \n (.I0(p_0_in),\n .I1(out[1]),\n .I2(wrlvl_byte_redo),\n .I3(out[3]),\n .I4(\\fine_inc[3][5]_i_5_n_0 ),\n .I5(dqs_count_r[0]),\n .O(\\dqs_count_r[0]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h00000000ADAAAAAA)) \n \\dqs_count_r[0]_i_7 \n (.I0(dqs_count_r[0]),\n .I1(\\fine_inc[3][5]_i_5_n_0 ),\n .I2(\\FSM_sequential_wl_state_r[2]_i_10_n_0 ),\n .I3(\\FSM_sequential_wl_state_r[3]_i_9_n_0 ),\n .I4(\\dqs_count_r[0]_i_8_n_0 ),\n .I5(out[3]),\n .O(\\dqs_count_r[0]_i_7_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair322\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\dqs_count_r[0]_i_8 \n (.I0(wr_level_done_r5),\n .I1(wrlvl_byte_redo),\n .O(\\dqs_count_r[0]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'hF444FFFFF4440000)) \n \\dqs_count_r[1]_i_1 \n (.I0(out[4]),\n .I1(\\dqs_count_r_reg[1]_i_2_n_0 ),\n .I2(\\dqs_count_r_reg[1]_i_3_n_0 ),\n .I3(out[0]),\n .I4(\\dqs_count_r[2]_i_5_n_0 ),\n .I5(\\dqs_count_r_reg[1]_rep_n_0 ),\n .O(\\dqs_count_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hCACC0A00CACCCACC)) \n \\dqs_count_r[1]_i_4 \n (.I0(\\po_stg2_wrcal_cnt_reg[2] [1]),\n .I1(dqs_count_r[1]),\n .I2(wrlvl_byte_redo_r),\n .I3(wrlvl_byte_redo),\n .I4(wrlvl_final_r),\n .I5(wrlvl_final_mux),\n .O(\\dqs_count_r[1]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h7477030377770000)) \n \\dqs_count_r[1]_i_5 \n (.I0(dqs_count_r140_out),\n .I1(out[0]),\n .I2(\\FSM_sequential_wl_state_r[2]_i_10_n_0 ),\n .I3(dqs_count_r[2]),\n .I4(dqs_count_r[1]),\n .I5(dqs_count_r[0]),\n .O(\\dqs_count_r[1]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'h8BBBBB88)) \n \\dqs_count_r[1]_i_6 \n (.I0(\\dqs_count_r[1]_i_8_n_0 ),\n .I1(out[3]),\n .I2(dqs_count_r[2]),\n .I3(dqs_count_r[1]),\n .I4(dqs_count_r[0]),\n .O(\\dqs_count_r[1]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h00000000CCCCCC6E)) \n \\dqs_count_r[1]_i_7 \n (.I0(dqs_count_r[0]),\n .I1(dqs_count_r[1]),\n .I2(dqs_count_r[2]),\n .I3(\\FSM_sequential_wl_state_r[2]_i_10_n_0 ),\n .I4(\\dqs_count_r[2]_i_11_n_0 ),\n .I5(out[3]),\n .O(\\dqs_count_r[1]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hF8FB0300FBFB0300)) \n \\dqs_count_r[1]_i_8 \n (.I0(p_0_in),\n .I1(out[1]),\n .I2(wrlvl_byte_redo),\n .I3(dqs_count_r[0]),\n .I4(dqs_count_r[1]),\n .I5(dqs_count_r[2]),\n .O(\\dqs_count_r[1]_i_8_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair342\" *) \n LUT2 #(\n .INIT(4'h7)) \n \\dqs_count_r[2]_i_10 \n (.I0(dqs_count_r[0]),\n .I1(dqs_count_r[1]),\n .O(\\dqs_count_r[2]_i_10_n_0 ));\n LUT3 #(\n .INIT(8'hBF)) \n \\dqs_count_r[2]_i_11 \n (.I0(wrlvl_byte_redo),\n .I1(wr_level_done_r5),\n .I2(\\FSM_sequential_wl_state_r[3]_i_9_n_0 ),\n .O(\\dqs_count_r[2]_i_11_n_0 ));\n LUT6 #(\n .INIT(64'hF444FFFFF4440000)) \n \\dqs_count_r[2]_i_2 \n (.I0(out[4]),\n .I1(\\dqs_count_r_reg[2]_i_3_n_0 ),\n .I2(\\dqs_count_r_reg[2]_i_4_n_0 ),\n .I3(out[0]),\n .I4(\\dqs_count_r[2]_i_5_n_0 ),\n .I5(dqs_count_r[2]),\n .O(\\dqs_count_r[2]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'h00805889)) \n \\dqs_count_r[2]_i_5 \n (.I0(out[4]),\n .I1(out[0]),\n .I2(out[3]),\n .I3(out[2]),\n .I4(out[1]),\n .O(\\dqs_count_r[2]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hFB080808FB08FB08)) \n \\dqs_count_r[2]_i_6 \n (.I0(\\po_stg2_wrcal_cnt_reg[2] [2]),\n .I1(wrlvl_byte_redo),\n .I2(wrlvl_byte_redo_r),\n .I3(dqs_count_r[2]),\n .I4(wrlvl_final_r),\n .I5(wrlvl_final_mux),\n .O(\\dqs_count_r[2]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h7040707070707070)) \n \\dqs_count_r[2]_i_7 \n (.I0(dqs_count_r140_out),\n .I1(out[0]),\n .I2(dqs_count_r[2]),\n .I3(\\FSM_sequential_wl_state_r[2]_i_10_n_0 ),\n .I4(dqs_count_r[0]),\n .I5(dqs_count_r[1]),\n .O(\\dqs_count_r[2]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hFBFFF80000000000)) \n \\dqs_count_r[2]_i_8 \n (.I0(p_0_in),\n .I1(out[1]),\n .I2(wrlvl_byte_redo),\n .I3(out[3]),\n .I4(\\dqs_count_r[2]_i_10_n_0 ),\n .I5(dqs_count_r[2]),\n .O(\\dqs_count_r[2]_i_8_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FFBF0000)) \n \\dqs_count_r[2]_i_9 \n (.I0(\\FSM_sequential_wl_state_r[2]_i_10_n_0 ),\n .I1(dqs_count_r[0]),\n .I2(dqs_count_r[1]),\n .I3(\\dqs_count_r[2]_i_11_n_0 ),\n .I4(dqs_count_r[2]),\n .I5(out[3]),\n .O(\\dqs_count_r[2]_i_9_n_0 ));\n (* MAX_FANOUT = \"50\" *) \n (* ORIG_CELL_NAME = \"dqs_count_r_reg[0]\" *) \n FDRE \\dqs_count_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dqs_count_r[0]_i_1_n_0 ),\n .Q(dqs_count_r[0]),\n .R(rstdiv0_sync_r1_reg_rep__17));\n MUXF7 \\dqs_count_r_reg[0]_i_2 \n (.I0(\\dqs_count_r[0]_i_4_n_0 ),\n .I1(\\dqs_count_r[0]_i_5_n_0 ),\n .O(\\dqs_count_r_reg[0]_i_2_n_0 ),\n .S(out[3]));\n MUXF7 \\dqs_count_r_reg[0]_i_3 \n (.I0(\\dqs_count_r[0]_i_6_n_0 ),\n .I1(\\dqs_count_r[0]_i_7_n_0 ),\n .O(\\dqs_count_r_reg[0]_i_3_n_0 ),\n .S(out[2]));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* MAX_FANOUT = \"50\" *) \n (* ORIG_CELL_NAME = \"dqs_count_r_reg[0]\" *) \n FDRE \\dqs_count_r_reg[0]_rep \n (.C(CLK),\n .CE(1'b1),\n .D(\\dqs_count_r[0]_i_1_n_0 ),\n .Q(\\dqs_count_r_reg[0]_rep_n_0 ),\n .R(rstdiv0_sync_r1_reg_rep));\n (* MAX_FANOUT = \"50\" *) \n (* ORIG_CELL_NAME = \"dqs_count_r_reg[1]\" *) \n FDRE \\dqs_count_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dqs_count_r[1]_i_1_n_0 ),\n .Q(dqs_count_r[1]),\n .R(rstdiv0_sync_r1_reg_rep__17));\n MUXF7 \\dqs_count_r_reg[1]_i_2 \n (.I0(\\dqs_count_r[1]_i_4_n_0 ),\n .I1(\\dqs_count_r[1]_i_5_n_0 ),\n .O(\\dqs_count_r_reg[1]_i_2_n_0 ),\n .S(out[3]));\n MUXF7 \\dqs_count_r_reg[1]_i_3 \n (.I0(\\dqs_count_r[1]_i_6_n_0 ),\n .I1(\\dqs_count_r[1]_i_7_n_0 ),\n .O(\\dqs_count_r_reg[1]_i_3_n_0 ),\n .S(out[2]));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n (* MAX_FANOUT = \"50\" *) \n (* ORIG_CELL_NAME = \"dqs_count_r_reg[1]\" *) \n FDRE \\dqs_count_r_reg[1]_rep \n (.C(CLK),\n .CE(1'b1),\n .D(\\dqs_count_r[1]_i_1_n_0 ),\n .Q(\\dqs_count_r_reg[1]_rep_n_0 ),\n .R(rstdiv0_sync_r1_reg_rep));\n (* MAX_FANOUT = \"50\" *) \n FDRE \\dqs_count_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dqs_count_r[2]_i_2_n_0 ),\n .Q(dqs_count_r[2]),\n .R(rstdiv0_sync_r1_reg_rep__17));\n MUXF7 \\dqs_count_r_reg[2]_i_3 \n (.I0(\\dqs_count_r[2]_i_6_n_0 ),\n .I1(\\dqs_count_r[2]_i_7_n_0 ),\n .O(\\dqs_count_r_reg[2]_i_3_n_0 ),\n .S(out[3]));\n MUXF7 \\dqs_count_r_reg[2]_i_4 \n (.I0(\\dqs_count_r[2]_i_8_n_0 ),\n .I1(\\dqs_count_r[2]_i_9_n_0 ),\n .O(\\dqs_count_r_reg[2]_i_4_n_0 ),\n .S(out[2]));\n (* syn_maxfan = \"2\" *) \n FDRE dqs_po_dec_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(po_dec_done),\n .Q(dqs_po_dec_done),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hAAAABBABAAAAAABA)) \n dqs_po_en_stg2_f_i_1\n (.I0(dqs_po_en_stg2_f_reg_0),\n .I1(out[2]),\n .I2(out[3]),\n .I3(out[0]),\n .I4(out[4]),\n .I5(out[1]),\n .O(dqs_po_en_stg2_f_i_1_n_0));\n FDRE dqs_po_en_stg2_f_reg\n (.C(CLK),\n .CE(1'b1),\n .D(dqs_po_en_stg2_f_i_1_n_0),\n .Q(dqs_po_en_stg2_f),\n .R(rstdiv0_sync_r1_reg_rep__18));\n LUT3 #(\n .INIT(8'h02)) \n dqs_po_stg2_f_incdec_i_1\n (.I0(dqs_po_stg2_f_incdec_i_2_n_0),\n .I1(dqs_po_stg2_f_incdec_i_3_n_0),\n .I2(rstdiv0_sync_r1_reg_rep__23),\n .O(dqs_po_stg2_f_incdec0));\n LUT6 #(\n .INIT(64'h00000000FFFFFEDF)) \n dqs_po_stg2_f_incdec_i_2\n (.I0(out[1]),\n .I1(out[4]),\n .I2(out[0]),\n .I3(out[3]),\n .I4(out[2]),\n .I5(dqs_po_en_stg2_f_reg_0),\n .O(dqs_po_stg2_f_incdec_i_2_n_0));\n LUT5 #(\n .INIT(32'hFBFEFFFF)) \n dqs_po_stg2_f_incdec_i_3\n (.I0(out[2]),\n .I1(out[0]),\n .I2(out[4]),\n .I3(out[3]),\n .I4(out[1]),\n .O(dqs_po_stg2_f_incdec_i_3_n_0));\n FDRE dqs_po_stg2_f_incdec_reg\n (.C(CLK),\n .CE(1'b1),\n .D(dqs_po_stg2_f_incdec0),\n .Q(dqs_po_stg2_f_incdec),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h00000002)) \n dqs_wl_po_stg2_c_incdec_i_1\n (.I0(out[2]),\n .I1(out[0]),\n .I2(out[1]),\n .I3(out[3]),\n .I4(out[4]),\n .O(dqs_wl_po_stg2_c_incdec_i_1_n_0));\n FDRE dqs_wl_po_stg2_c_incdec_reg\n (.C(CLK),\n .CE(1'b1),\n .D(dqs_wl_po_stg2_c_incdec_i_1_n_0),\n .Q(dqs_wl_po_stg2_c_incdec),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\final_coarse_tap_reg[0][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_corse_cnt_reg[0][0]__0 [0]),\n .Q(\\final_coarse_tap_reg_n_0_[0][0] ),\n .R(1'b0));\n FDRE \\final_coarse_tap_reg[0][1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_corse_cnt_reg[0][0]__0 [1]),\n .Q(\\final_coarse_tap_reg_n_0_[0][1] ),\n .R(1'b0));\n FDRE \\final_coarse_tap_reg[0][2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_corse_cnt_reg[0][0]__0 [2]),\n .Q(\\final_coarse_tap_reg_n_0_[0][2] ),\n .R(1'b0));\n FDRE \\final_coarse_tap_reg[1][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_corse_cnt_reg[0][1]__0 [0]),\n .Q(\\final_coarse_tap_reg_n_0_[1][0] ),\n .R(1'b0));\n FDRE \\final_coarse_tap_reg[1][1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_corse_cnt_reg[0][1]__0 [1]),\n .Q(\\final_coarse_tap_reg_n_0_[1][1] ),\n .R(1'b0));\n FDRE \\final_coarse_tap_reg[1][2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_corse_cnt_reg[0][1]__0 [2]),\n .Q(\\final_coarse_tap_reg_n_0_[1][2] ),\n .R(1'b0));\n FDRE \\final_coarse_tap_reg[2][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_corse_cnt_reg[0][2]__0 [0]),\n .Q(\\final_coarse_tap_reg_n_0_[2][0] ),\n .R(1'b0));\n FDRE \\final_coarse_tap_reg[2][1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_corse_cnt_reg[0][2]__0 [1]),\n .Q(\\final_coarse_tap_reg_n_0_[2][1] ),\n .R(1'b0));\n FDRE \\final_coarse_tap_reg[2][2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_corse_cnt_reg[0][2]__0 [2]),\n .Q(\\final_coarse_tap_reg_n_0_[2][2] ),\n .R(1'b0));\n FDRE \\final_coarse_tap_reg[3][0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_corse_cnt_reg[0][3]__0 [0]),\n .Q(\\final_coarse_tap_reg_n_0_[3][0] ),\n .R(1'b0));\n FDRE \\final_coarse_tap_reg[3][1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_corse_cnt_reg[0][3]__0 [1]),\n .Q(\\final_coarse_tap_reg_n_0_[3][1] ),\n .R(1'b0));\n FDRE \\final_coarse_tap_reg[3][2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_corse_cnt_reg[0][3]__0 [2]),\n .Q(\\final_coarse_tap_reg_n_0_[3][2] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h303F000035370504)) \n \\fine_dec_cnt[0]_i_1 \n (.I0(fine_dec_cnt__0[0]),\n .I1(out[3]),\n .I2(out[2]),\n .I3(out[1]),\n .I4(\\wl_tap_count_r_reg_n_0_[0] ),\n .I5(out[4]),\n .O(fine_dec_cnt[0]));\n LUT6 #(\n .INIT(64'hBABFAAAABABBAAAA)) \n \\fine_dec_cnt[1]_i_1 \n (.I0(\\fine_dec_cnt[1]_i_2_n_0 ),\n .I1(out[3]),\n .I2(out[2]),\n .I3(out[1]),\n .I4(\\wl_tap_count_r_reg_n_0_[1] ),\n .I5(out[4]),\n .O(fine_dec_cnt[1]));\n LUT6 #(\n .INIT(64'h1001100110010000)) \n \\fine_dec_cnt[1]_i_2 \n (.I0(out[4]),\n .I1(out[2]),\n .I2(fine_dec_cnt__0[1]),\n .I3(fine_dec_cnt__0[0]),\n .I4(out[1]),\n .I5(out[3]),\n .O(\\fine_dec_cnt[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h303F000035370505)) \n \\fine_dec_cnt[2]_i_1 \n (.I0(\\fine_dec_cnt[2]_i_2_n_0 ),\n .I1(out[3]),\n .I2(out[2]),\n .I3(out[1]),\n .I4(\\wl_tap_count_r_reg_n_0_[2] ),\n .I5(out[4]),\n .O(fine_dec_cnt[2]));\n LUT5 #(\n .INIT(32'h1F1F1FF1)) \n \\fine_dec_cnt[2]_i_2 \n (.I0(out[3]),\n .I1(out[1]),\n .I2(fine_dec_cnt__0[2]),\n .I3(fine_dec_cnt__0[0]),\n .I4(fine_dec_cnt__0[1]),\n .O(\\fine_dec_cnt[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h303F000035370505)) \n \\fine_dec_cnt[3]_i_1 \n (.I0(\\fine_dec_cnt[3]_i_2_n_0 ),\n .I1(out[3]),\n .I2(out[2]),\n .I3(out[1]),\n .I4(\\wl_tap_count_r_reg_n_0_[3] ),\n .I5(out[4]),\n .O(fine_dec_cnt[3]));\n LUT6 #(\n .INIT(64'h1F1F1F1F1F1F1FF1)) \n \\fine_dec_cnt[3]_i_2 \n (.I0(out[3]),\n .I1(out[1]),\n .I2(fine_dec_cnt__0[3]),\n .I3(fine_dec_cnt__0[1]),\n .I4(fine_dec_cnt__0[0]),\n .I5(fine_dec_cnt__0[2]),\n .O(\\fine_dec_cnt[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h303F00003A3B0A08)) \n \\fine_dec_cnt[4]_i_1 \n (.I0(\\fine_dec_cnt[4]_i_2_n_0 ),\n .I1(out[3]),\n .I2(out[2]),\n .I3(out[1]),\n .I4(\\wl_tap_count_r_reg_n_0_[4] ),\n .I5(out[4]),\n .O(fine_dec_cnt[4]));\n LUT5 #(\n .INIT(32'hFFFE0001)) \n \\fine_dec_cnt[4]_i_2 \n (.I0(fine_dec_cnt__0[3]),\n .I1(fine_dec_cnt__0[1]),\n .I2(fine_dec_cnt__0[0]),\n .I3(fine_dec_cnt__0[2]),\n .I4(fine_dec_cnt__0[4]),\n .O(\\fine_dec_cnt[4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h303F00003A3B0A08)) \n \\fine_dec_cnt[5]_i_2 \n (.I0(\\fine_dec_cnt[5]_i_5_n_0 ),\n .I1(out[3]),\n .I2(out[2]),\n .I3(out[1]),\n .I4(\\wl_tap_count_r_reg_n_0_[5] ),\n .I5(out[4]),\n .O(fine_dec_cnt[5]));\n LUT5 #(\n .INIT(32'h11800080)) \n \\fine_dec_cnt[5]_i_3 \n (.I0(out[2]),\n .I1(out[1]),\n .I2(\\fine_dec_cnt[5]_i_6_n_0 ),\n .I3(out[3]),\n .I4(\\fine_dec_cnt[5]_i_7_n_0 ),\n .O(\\fine_dec_cnt[5]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h4444040000000400)) \n \\fine_dec_cnt[5]_i_4 \n (.I0(out[3]),\n .I1(\\fine_dec_cnt[5]_i_8_n_0 ),\n .I2(\\rd_data_edge_detect_r[3]_i_4_n_0 ),\n .I3(wrlvl_byte_redo),\n .I4(out[1]),\n .I5(\\FSM_sequential_wl_state_r[3]_i_10_n_0 ),\n .O(\\fine_dec_cnt[5]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAAAAA9)) \n \\fine_dec_cnt[5]_i_5 \n (.I0(fine_dec_cnt__0[5]),\n .I1(fine_dec_cnt__0[3]),\n .I2(fine_dec_cnt__0[1]),\n .I3(fine_dec_cnt__0[0]),\n .I4(fine_dec_cnt__0[2]),\n .I5(fine_dec_cnt__0[4]),\n .O(\\fine_dec_cnt[5]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h0000000080000000)) \n \\fine_dec_cnt[5]_i_6 \n (.I0(\\stable_cnt_reg_n_0_[1] ),\n .I1(\\stable_cnt_reg_n_0_[2] ),\n .I2(\\stable_cnt_reg_n_0_[3] ),\n .I3(wl_sm_start),\n .I4(stable_cnt227_in),\n .I5(out[4]),\n .O(\\fine_dec_cnt[5]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h0020FFFF00200000)) \n \\fine_dec_cnt[5]_i_7 \n (.I0(\\FSM_sequential_wl_state_r[0]_i_3_n_0 ),\n .I1(\\FSM_sequential_wl_state_r[0]_i_5_n_0 ),\n .I2(\\FSM_sequential_wl_state_r_reg[0]_0 ),\n .I3(\\rd_data_edge_detect_r[3]_i_5_n_0 ),\n .I4(out[4]),\n .I5(\\FSM_sequential_wl_state_r[3]_i_10_n_0 ),\n .O(\\fine_dec_cnt[5]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h1)) \n \\fine_dec_cnt[5]_i_8 \n (.I0(out[2]),\n .I1(out[4]),\n .O(\\fine_dec_cnt[5]_i_8_n_0 ));\n FDRE \\fine_dec_cnt_reg[0] \n (.C(CLK),\n .CE(\\fine_dec_cnt_reg[5]_i_1_n_0 ),\n .D(fine_dec_cnt[0]),\n .Q(fine_dec_cnt__0[0]),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\fine_dec_cnt_reg[1] \n (.C(CLK),\n .CE(\\fine_dec_cnt_reg[5]_i_1_n_0 ),\n .D(fine_dec_cnt[1]),\n .Q(fine_dec_cnt__0[1]),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\fine_dec_cnt_reg[2] \n (.C(CLK),\n .CE(\\fine_dec_cnt_reg[5]_i_1_n_0 ),\n .D(fine_dec_cnt[2]),\n .Q(fine_dec_cnt__0[2]),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\fine_dec_cnt_reg[3] \n (.C(CLK),\n .CE(\\fine_dec_cnt_reg[5]_i_1_n_0 ),\n .D(fine_dec_cnt[3]),\n .Q(fine_dec_cnt__0[3]),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\fine_dec_cnt_reg[4] \n (.C(CLK),\n .CE(\\fine_dec_cnt_reg[5]_i_1_n_0 ),\n .D(fine_dec_cnt[4]),\n .Q(fine_dec_cnt__0[4]),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\fine_dec_cnt_reg[5] \n (.C(CLK),\n .CE(\\fine_dec_cnt_reg[5]_i_1_n_0 ),\n .D(fine_dec_cnt[5]),\n .Q(fine_dec_cnt__0[5]),\n .R(rstdiv0_sync_r1_reg_rep__18));\n MUXF7 \\fine_dec_cnt_reg[5]_i_1 \n (.I0(\\fine_dec_cnt[5]_i_3_n_0 ),\n .I1(\\fine_dec_cnt[5]_i_4_n_0 ),\n .O(\\fine_dec_cnt_reg[5]_i_1_n_0 ),\n .S(out[0]));\n LUT4 #(\n .INIT(16'h0074)) \n \\fine_inc[0][0]_i_1 \n (.I0(\\fine_inc[3][2]_i_3_n_0 ),\n .I1(out[1]),\n .I2(\\gen_final_tap[0].final_val_reg_n_0_[0][0] ),\n .I3(out[4]),\n .O(fine_inc[0]));\n LUT5 #(\n .INIT(32'h090F0900)) \n \\fine_inc[0][1]_i_1 \n (.I0(\\fine_inc[3][2]_i_3_n_0 ),\n .I1(\\fine_inc[3][2]_i_2_n_0 ),\n .I2(out[4]),\n .I3(out[1]),\n .I4(\\gen_final_tap[0].final_val_reg_n_0_[0][1] ),\n .O(fine_inc[1]));\n LUT6 #(\n .INIT(64'h00E100FF00E10000)) \n \\fine_inc[0][2]_i_1 \n (.I0(\\fine_inc[3][2]_i_2_n_0 ),\n .I1(\\fine_inc[3][2]_i_3_n_0 ),\n .I2(\\fine_inc[3][2]_i_4_n_0 ),\n .I3(out[4]),\n .I4(out[1]),\n .I5(\\gen_final_tap[0].final_val_reg_n_0_[0][2] ),\n .O(fine_inc[2]));\n LUT5 #(\n .INIT(32'h060F0600)) \n \\fine_inc[0][3]_i_1 \n (.I0(\\fine_inc[3][4]_i_3_n_0 ),\n .I1(\\fine_inc[3][4]_i_2_n_0 ),\n .I2(out[4]),\n .I3(out[1]),\n .I4(\\gen_final_tap[0].final_val_reg_n_0_[0][3] ),\n .O(fine_inc[3]));\n LUT6 #(\n .INIT(64'h00D200FF00D20000)) \n \\fine_inc[0][4]_i_1 \n (.I0(\\fine_inc[3][4]_i_2_n_0 ),\n .I1(\\fine_inc[3][4]_i_3_n_0 ),\n .I2(\\fine_inc[3][4]_i_4_n_0 ),\n .I3(out[4]),\n .I4(out[1]),\n .I5(\\gen_final_tap[0].final_val_reg_n_0_[0][4] ),\n .O(fine_inc[4]));\n LUT6 #(\n .INIT(64'h008000800A800080)) \n \\fine_inc[0][5]_i_1 \n (.I0(\\fine_inc[3][5]_i_3_n_0 ),\n .I1(dqs_count_r140_out),\n .I2(out[2]),\n .I3(out[1]),\n .I4(\\fine_inc[0][5]_i_3_n_0 ),\n .I5(\\fine_inc[3][5]_i_6_n_0 ),\n .O(\\fine_inc[0][5]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h88B8)) \n \\fine_inc[0][5]_i_2 \n (.I0(\\fine_inc[3][5]_i_7_n_0 ),\n .I1(out[1]),\n .I2(\\gen_final_tap[0].final_val_reg_n_0_[0][5] ),\n .I3(out[4]),\n .O(fine_inc[5]));\n (* SOFT_HLUTNM = \"soft_lutpair341\" *) \n LUT3 #(\n .INIT(8'h01)) \n \\fine_inc[0][5]_i_3 \n (.I0(dqs_count_r[2]),\n .I1(dqs_count_r[1]),\n .I2(dqs_count_r[0]),\n .O(\\fine_inc[0][5]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'h0074)) \n \\fine_inc[1][0]_i_1 \n (.I0(\\fine_inc[3][2]_i_3_n_0 ),\n .I1(out[1]),\n .I2(\\gen_final_tap[1].final_val_reg_n_0_[1][0] ),\n .I3(out[4]),\n .O(\\fine_inc[1][0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h090F0900)) \n \\fine_inc[1][1]_i_1 \n (.I0(\\fine_inc[3][2]_i_3_n_0 ),\n .I1(\\fine_inc[3][2]_i_2_n_0 ),\n .I2(out[4]),\n .I3(out[1]),\n .I4(\\gen_final_tap[1].final_val_reg_n_0_[1][1] ),\n .O(\\fine_inc[1][1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00E100FF00E10000)) \n \\fine_inc[1][2]_i_1 \n (.I0(\\fine_inc[3][2]_i_2_n_0 ),\n .I1(\\fine_inc[3][2]_i_3_n_0 ),\n .I2(\\fine_inc[3][2]_i_4_n_0 ),\n .I3(out[4]),\n .I4(out[1]),\n .I5(\\gen_final_tap[1].final_val_reg_n_0_[1][2] ),\n .O(\\fine_inc[1][2]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h060F0600)) \n \\fine_inc[1][3]_i_1 \n (.I0(\\fine_inc[3][4]_i_3_n_0 ),\n .I1(\\fine_inc[3][4]_i_2_n_0 ),\n .I2(out[4]),\n .I3(out[1]),\n .I4(\\gen_final_tap[1].final_val_reg_n_0_[1][3] ),\n .O(\\fine_inc[1][3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00D200FF00D20000)) \n \\fine_inc[1][4]_i_1 \n (.I0(\\fine_inc[3][4]_i_2_n_0 ),\n .I1(\\fine_inc[3][4]_i_3_n_0 ),\n .I2(\\fine_inc[3][4]_i_4_n_0 ),\n .I3(out[4]),\n .I4(out[1]),\n .I5(\\gen_final_tap[1].final_val_reg_n_0_[1][4] ),\n .O(\\fine_inc[1][4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h008000800A800080)) \n \\fine_inc[1][5]_i_1 \n (.I0(\\fine_inc[3][5]_i_3_n_0 ),\n .I1(dqs_count_r140_out),\n .I2(out[2]),\n .I3(out[1]),\n .I4(\\fine_inc[1][5]_i_3_n_0 ),\n .I5(\\fine_inc[3][5]_i_6_n_0 ),\n .O(\\fine_inc[1][5]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h88B8)) \n \\fine_inc[1][5]_i_2 \n (.I0(\\fine_inc[3][5]_i_7_n_0 ),\n .I1(out[1]),\n .I2(\\gen_final_tap[1].final_val_reg_n_0_[1][5] ),\n .I3(out[4]),\n .O(\\fine_inc[1][5]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair341\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\fine_inc[1][5]_i_3 \n (.I0(dqs_count_r[2]),\n .I1(dqs_count_r[0]),\n .I2(dqs_count_r[1]),\n .O(\\fine_inc[1][5]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'h0074)) \n \\fine_inc[2][0]_i_1 \n (.I0(\\fine_inc[3][2]_i_3_n_0 ),\n .I1(out[1]),\n .I2(\\gen_final_tap[2].final_val_reg_n_0_[2][0] ),\n .I3(out[4]),\n .O(\\fine_inc[2][0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h090F0900)) \n \\fine_inc[2][1]_i_1 \n (.I0(\\fine_inc[3][2]_i_3_n_0 ),\n .I1(\\fine_inc[3][2]_i_2_n_0 ),\n .I2(out[4]),\n .I3(out[1]),\n .I4(\\gen_final_tap[2].final_val_reg_n_0_[2][1] ),\n .O(\\fine_inc[2][1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00E100FF00E10000)) \n \\fine_inc[2][2]_i_1 \n (.I0(\\fine_inc[3][2]_i_2_n_0 ),\n .I1(\\fine_inc[3][2]_i_3_n_0 ),\n .I2(\\fine_inc[3][2]_i_4_n_0 ),\n .I3(out[4]),\n .I4(out[1]),\n .I5(\\gen_final_tap[2].final_val_reg_n_0_[2][2] ),\n .O(\\fine_inc[2][2]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h060F0600)) \n \\fine_inc[2][3]_i_1 \n (.I0(\\fine_inc[3][4]_i_3_n_0 ),\n .I1(\\fine_inc[3][4]_i_2_n_0 ),\n .I2(out[4]),\n .I3(out[1]),\n .I4(\\gen_final_tap[2].final_val_reg_n_0_[2][3] ),\n .O(\\fine_inc[2][3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00D200FF00D20000)) \n \\fine_inc[2][4]_i_1 \n (.I0(\\fine_inc[3][4]_i_2_n_0 ),\n .I1(\\fine_inc[3][4]_i_3_n_0 ),\n .I2(\\fine_inc[3][4]_i_4_n_0 ),\n .I3(out[4]),\n .I4(out[1]),\n .I5(\\gen_final_tap[2].final_val_reg_n_0_[2][4] ),\n .O(\\fine_inc[2][4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h008000800A800080)) \n \\fine_inc[2][5]_i_1 \n (.I0(\\fine_inc[3][5]_i_3_n_0 ),\n .I1(dqs_count_r140_out),\n .I2(out[2]),\n .I3(out[1]),\n .I4(\\fine_inc[2][5]_i_3_n_0 ),\n .I5(\\fine_inc[3][5]_i_6_n_0 ),\n .O(\\fine_inc[2][5]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h88B8)) \n \\fine_inc[2][5]_i_2 \n (.I0(\\fine_inc[3][5]_i_7_n_0 ),\n .I1(out[1]),\n .I2(\\gen_final_tap[2].final_val_reg_n_0_[2][5] ),\n .I3(out[4]),\n .O(\\fine_inc[2][5]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair342\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\fine_inc[2][5]_i_3 \n (.I0(dqs_count_r[2]),\n .I1(dqs_count_r[1]),\n .I2(dqs_count_r[0]),\n .O(\\fine_inc[2][5]_i_3_n_0 ));\n LUT4 #(\n .INIT(16'h0074)) \n \\fine_inc[3][0]_i_1 \n (.I0(\\fine_inc[3][2]_i_3_n_0 ),\n .I1(out[1]),\n .I2(\\gen_final_tap[3].final_val_reg_n_0_[3][0] ),\n .I3(out[4]),\n .O(\\fine_inc[3][0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h090F0900)) \n \\fine_inc[3][1]_i_1 \n (.I0(\\fine_inc[3][2]_i_3_n_0 ),\n .I1(\\fine_inc[3][2]_i_2_n_0 ),\n .I2(out[4]),\n .I3(out[1]),\n .I4(\\gen_final_tap[3].final_val_reg_n_0_[3][1] ),\n .O(\\fine_inc[3][1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00E100FF00E10000)) \n \\fine_inc[3][2]_i_1 \n (.I0(\\fine_inc[3][2]_i_2_n_0 ),\n .I1(\\fine_inc[3][2]_i_3_n_0 ),\n .I2(\\fine_inc[3][2]_i_4_n_0 ),\n .I3(out[4]),\n .I4(out[1]),\n .I5(\\gen_final_tap[3].final_val_reg_n_0_[3][2] ),\n .O(\\fine_inc[3][2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\fine_inc[3][2]_i_2 \n (.I0(\\fine_inc_reg_n_0_[3][1] ),\n .I1(\\fine_inc_reg_n_0_[1][1] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\fine_inc_reg_n_0_[2][1] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\fine_inc_reg_n_0_[0][1] ),\n .O(\\fine_inc[3][2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\fine_inc[3][2]_i_3 \n (.I0(\\fine_inc_reg_n_0_[3][0] ),\n .I1(\\fine_inc_reg_n_0_[1][0] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\fine_inc_reg_n_0_[2][0] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\fine_inc_reg_n_0_[0][0] ),\n .O(\\fine_inc[3][2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\fine_inc[3][2]_i_4 \n (.I0(\\fine_inc_reg_n_0_[3][2] ),\n .I1(\\fine_inc_reg_n_0_[1][2] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\fine_inc_reg_n_0_[2][2] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\fine_inc_reg_n_0_[0][2] ),\n .O(\\fine_inc[3][2]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h060F0600)) \n \\fine_inc[3][3]_i_1 \n (.I0(\\fine_inc[3][4]_i_3_n_0 ),\n .I1(\\fine_inc[3][4]_i_2_n_0 ),\n .I2(out[4]),\n .I3(out[1]),\n .I4(\\gen_final_tap[3].final_val_reg_n_0_[3][3] ),\n .O(\\fine_inc[3][3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00D200FF00D20000)) \n \\fine_inc[3][4]_i_1 \n (.I0(\\fine_inc[3][4]_i_2_n_0 ),\n .I1(\\fine_inc[3][4]_i_3_n_0 ),\n .I2(\\fine_inc[3][4]_i_4_n_0 ),\n .I3(out[4]),\n .I4(out[1]),\n .I5(\\gen_final_tap[3].final_val_reg_n_0_[3][4] ),\n .O(\\fine_inc[3][4]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'h01)) \n \\fine_inc[3][4]_i_2 \n (.I0(\\fine_inc[3][2]_i_3_n_0 ),\n .I1(\\fine_inc[3][2]_i_2_n_0 ),\n .I2(\\fine_inc[3][2]_i_4_n_0 ),\n .O(\\fine_inc[3][4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\fine_inc[3][4]_i_3 \n (.I0(\\fine_inc_reg_n_0_[3][3] ),\n .I1(\\fine_inc_reg_n_0_[1][3] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\fine_inc_reg_n_0_[2][3] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\fine_inc_reg_n_0_[0][3] ),\n .O(\\fine_inc[3][4]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\fine_inc[3][4]_i_4 \n (.I0(\\fine_inc_reg_n_0_[3][4] ),\n .I1(\\fine_inc_reg_n_0_[1][4] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\fine_inc_reg_n_0_[2][4] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\fine_inc_reg_n_0_[0][4] ),\n .O(\\fine_inc[3][4]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h008000800A800080)) \n \\fine_inc[3][5]_i_1 \n (.I0(\\fine_inc[3][5]_i_3_n_0 ),\n .I1(dqs_count_r140_out),\n .I2(out[2]),\n .I3(out[1]),\n .I4(\\fine_inc[3][5]_i_5_n_0 ),\n .I5(\\fine_inc[3][5]_i_6_n_0 ),\n .O(\\fine_inc[3][5]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h88B8)) \n \\fine_inc[3][5]_i_2 \n (.I0(\\fine_inc[3][5]_i_7_n_0 ),\n .I1(out[1]),\n .I2(\\gen_final_tap[3].final_val_reg_n_0_[3][5] ),\n .I3(out[4]),\n .O(\\fine_inc[3][5]_i_2_n_0 ));\n LUT3 #(\n .INIT(8'h08)) \n \\fine_inc[3][5]_i_3 \n (.I0(out[0]),\n .I1(out[3]),\n .I2(out[4]),\n .O(\\fine_inc[3][5]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair345\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\fine_inc[3][5]_i_4 \n (.I0(wr_level_done_r4),\n .I1(wr_level_done_r5),\n .O(dqs_count_r140_out));\n (* SOFT_HLUTNM = \"soft_lutpair318\" *) \n LUT3 #(\n .INIT(8'h40)) \n \\fine_inc[3][5]_i_5 \n (.I0(dqs_count_r[2]),\n .I1(dqs_count_r[1]),\n .I2(dqs_count_r[0]),\n .O(\\fine_inc[3][5]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'h0100FFFF)) \n \\fine_inc[3][5]_i_6 \n (.I0(\\fine_inc[3][5]_i_8_n_0 ),\n .I1(\\fine_inc[3][4]_i_3_n_0 ),\n .I2(\\fine_inc[3][4]_i_4_n_0 ),\n .I3(\\fine_inc[3][4]_i_2_n_0 ),\n .I4(wr_level_done_r5),\n .O(\\fine_inc[3][5]_i_6_n_0 ));\n LUT5 #(\n .INIT(32'h0000FD02)) \n \\fine_inc[3][5]_i_7 \n (.I0(\\fine_inc[3][4]_i_2_n_0 ),\n .I1(\\fine_inc[3][4]_i_3_n_0 ),\n .I2(\\fine_inc[3][4]_i_4_n_0 ),\n .I3(\\fine_inc[3][5]_i_8_n_0 ),\n .I4(out[4]),\n .O(\\fine_inc[3][5]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\fine_inc[3][5]_i_8 \n (.I0(\\fine_inc_reg_n_0_[3][5] ),\n .I1(\\fine_inc_reg_n_0_[1][5] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\fine_inc_reg_n_0_[2][5] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\fine_inc_reg_n_0_[0][5] ),\n .O(\\fine_inc[3][5]_i_8_n_0 ));\n FDRE \\fine_inc_reg[0][0] \n (.C(CLK),\n .CE(\\fine_inc[0][5]_i_1_n_0 ),\n .D(fine_inc[0]),\n .Q(\\fine_inc_reg_n_0_[0][0] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\fine_inc_reg[0][1] \n (.C(CLK),\n .CE(\\fine_inc[0][5]_i_1_n_0 ),\n .D(fine_inc[1]),\n .Q(\\fine_inc_reg_n_0_[0][1] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\fine_inc_reg[0][2] \n (.C(CLK),\n .CE(\\fine_inc[0][5]_i_1_n_0 ),\n .D(fine_inc[2]),\n .Q(\\fine_inc_reg_n_0_[0][2] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\fine_inc_reg[0][3] \n (.C(CLK),\n .CE(\\fine_inc[0][5]_i_1_n_0 ),\n .D(fine_inc[3]),\n .Q(\\fine_inc_reg_n_0_[0][3] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\fine_inc_reg[0][4] \n (.C(CLK),\n .CE(\\fine_inc[0][5]_i_1_n_0 ),\n .D(fine_inc[4]),\n .Q(\\fine_inc_reg_n_0_[0][4] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\fine_inc_reg[0][5] \n (.C(CLK),\n .CE(\\fine_inc[0][5]_i_1_n_0 ),\n .D(fine_inc[5]),\n .Q(\\fine_inc_reg_n_0_[0][5] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\fine_inc_reg[1][0] \n (.C(CLK),\n .CE(\\fine_inc[1][5]_i_1_n_0 ),\n .D(\\fine_inc[1][0]_i_1_n_0 ),\n .Q(\\fine_inc_reg_n_0_[1][0] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\fine_inc_reg[1][1] \n (.C(CLK),\n .CE(\\fine_inc[1][5]_i_1_n_0 ),\n .D(\\fine_inc[1][1]_i_1_n_0 ),\n .Q(\\fine_inc_reg_n_0_[1][1] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\fine_inc_reg[1][2] \n (.C(CLK),\n .CE(\\fine_inc[1][5]_i_1_n_0 ),\n .D(\\fine_inc[1][2]_i_1_n_0 ),\n .Q(\\fine_inc_reg_n_0_[1][2] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\fine_inc_reg[1][3] \n (.C(CLK),\n .CE(\\fine_inc[1][5]_i_1_n_0 ),\n .D(\\fine_inc[1][3]_i_1_n_0 ),\n .Q(\\fine_inc_reg_n_0_[1][3] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\fine_inc_reg[1][4] \n (.C(CLK),\n .CE(\\fine_inc[1][5]_i_1_n_0 ),\n .D(\\fine_inc[1][4]_i_1_n_0 ),\n .Q(\\fine_inc_reg_n_0_[1][4] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\fine_inc_reg[1][5] \n (.C(CLK),\n .CE(\\fine_inc[1][5]_i_1_n_0 ),\n .D(\\fine_inc[1][5]_i_2_n_0 ),\n .Q(\\fine_inc_reg_n_0_[1][5] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\fine_inc_reg[2][0] \n (.C(CLK),\n .CE(\\fine_inc[2][5]_i_1_n_0 ),\n .D(\\fine_inc[2][0]_i_1_n_0 ),\n .Q(\\fine_inc_reg_n_0_[2][0] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\fine_inc_reg[2][1] \n (.C(CLK),\n .CE(\\fine_inc[2][5]_i_1_n_0 ),\n .D(\\fine_inc[2][1]_i_1_n_0 ),\n .Q(\\fine_inc_reg_n_0_[2][1] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\fine_inc_reg[2][2] \n (.C(CLK),\n .CE(\\fine_inc[2][5]_i_1_n_0 ),\n .D(\\fine_inc[2][2]_i_1_n_0 ),\n .Q(\\fine_inc_reg_n_0_[2][2] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\fine_inc_reg[2][3] \n (.C(CLK),\n .CE(\\fine_inc[2][5]_i_1_n_0 ),\n .D(\\fine_inc[2][3]_i_1_n_0 ),\n .Q(\\fine_inc_reg_n_0_[2][3] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\fine_inc_reg[2][4] \n (.C(CLK),\n .CE(\\fine_inc[2][5]_i_1_n_0 ),\n .D(\\fine_inc[2][4]_i_1_n_0 ),\n .Q(\\fine_inc_reg_n_0_[2][4] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\fine_inc_reg[2][5] \n (.C(CLK),\n .CE(\\fine_inc[2][5]_i_1_n_0 ),\n .D(\\fine_inc[2][5]_i_2_n_0 ),\n .Q(\\fine_inc_reg_n_0_[2][5] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\fine_inc_reg[3][0] \n (.C(CLK),\n .CE(\\fine_inc[3][5]_i_1_n_0 ),\n .D(\\fine_inc[3][0]_i_1_n_0 ),\n .Q(\\fine_inc_reg_n_0_[3][0] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\fine_inc_reg[3][1] \n (.C(CLK),\n .CE(\\fine_inc[3][5]_i_1_n_0 ),\n .D(\\fine_inc[3][1]_i_1_n_0 ),\n .Q(\\fine_inc_reg_n_0_[3][1] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\fine_inc_reg[3][2] \n (.C(CLK),\n .CE(\\fine_inc[3][5]_i_1_n_0 ),\n .D(\\fine_inc[3][2]_i_1_n_0 ),\n .Q(\\fine_inc_reg_n_0_[3][2] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\fine_inc_reg[3][3] \n (.C(CLK),\n .CE(\\fine_inc[3][5]_i_1_n_0 ),\n .D(\\fine_inc[3][3]_i_1_n_0 ),\n .Q(\\fine_inc_reg_n_0_[3][3] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\fine_inc_reg[3][4] \n (.C(CLK),\n .CE(\\fine_inc[3][5]_i_1_n_0 ),\n .D(\\fine_inc[3][4]_i_1_n_0 ),\n .Q(\\fine_inc_reg_n_0_[3][4] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\fine_inc_reg[3][5] \n (.C(CLK),\n .CE(\\fine_inc[3][5]_i_1_n_0 ),\n .D(\\fine_inc[3][5]_i_2_n_0 ),\n .Q(\\fine_inc_reg_n_0_[3][5] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n LUT5 #(\n .INIT(32'h00820000)) \n flag_ck_negedge_i_10\n (.I0(out[1]),\n .I1(out[2]),\n .I2(out[3]),\n .I3(out[4]),\n .I4(out[0]),\n .O(flag_ck_negedge_i_10_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair314\" *) \n LUT3 #(\n .INIT(8'h7F)) \n flag_ck_negedge_i_2\n (.I0(\\stable_cnt_reg_n_0_[3] ),\n .I1(\\stable_cnt_reg_n_0_[2] ),\n .I2(\\stable_cnt_reg_n_0_[1] ),\n .O(stable_cnt1));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n flag_ck_negedge_i_3\n (.I0(\\rd_data_previous_r_reg_n_0_[3] ),\n .I1(\\rd_data_previous_r_reg_n_0_[2] ),\n .I2(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I3(\\rd_data_previous_r_reg_n_0_[1] ),\n .I4(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I5(\\rd_data_previous_r_reg_n_0_[0] ),\n .O(stable_cnt227_in));\n LUT6 #(\n .INIT(64'h0040FFFF00400040)) \n flag_ck_negedge_i_4\n (.I0(out[1]),\n .I1(out[2]),\n .I2(flag_ck_negedge_i_6_n_0),\n .I3(out[3]),\n .I4(flag_ck_negedge_i_7_n_0),\n .I5(stable_cnt227_in),\n .O(flag_ck_negedge09_out));\n LUT4 #(\n .INIT(16'hFFFE)) \n flag_ck_negedge_i_5\n (.I0(\\stable_cnt[3]_i_6_n_0 ),\n .I1(wr_level_done_r1_reg_0),\n .I2(flag_ck_negedge_i_8_n_0),\n .I3(rstdiv0_sync_r1_reg_rep__20),\n .O(flag_ck_negedge_reg_0));\n LUT2 #(\n .INIT(4'h1)) \n flag_ck_negedge_i_6\n (.I0(out[4]),\n .I1(out[0]),\n .O(flag_ck_negedge_i_6_n_0));\n LUT6 #(\n .INIT(64'h0000000000000001)) \n flag_ck_negedge_i_7\n (.I0(\\stable_cnt_reg_n_0_[2] ),\n .I1(\\stable_cnt_reg_n_0_[3] ),\n .I2(p_1_in_0),\n .I3(flag_ck_negedge_i_10_n_0),\n .I4(\\stable_cnt_reg[3]_0 ),\n .I5(\\stable_cnt_reg_n_0_[1] ),\n .O(flag_ck_negedge_i_7_n_0));\n LUT4 #(\n .INIT(16'h4000)) \n flag_ck_negedge_i_8\n (.I0(out[2]),\n .I1(out[3]),\n .I2(out[0]),\n .I3(out[4]),\n .O(flag_ck_negedge_i_8_n_0));\n LUT5 #(\n .INIT(32'h10000000)) \n flag_ck_negedge_i_9\n (.I0(out[4]),\n .I1(out[0]),\n .I2(out[3]),\n .I3(out[2]),\n .I4(out[1]),\n .O(p_1_in_0));\n FDRE flag_ck_negedge_reg\n (.C(CLK),\n .CE(1'b1),\n .D(flag_ck_negedge_reg_1),\n .Q(\\rd_data_edge_detect_r_reg[0]_0 ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hAAAAAAAAAA8AAAAA)) \n flag_init_i_1\n (.I0(flag_init),\n .I1(\\wl_state_r1_reg_n_0_[0] ),\n .I2(p_1_in28_in),\n .I3(\\wl_state_r1_reg_n_0_[4] ),\n .I4(\\wl_state_r1_reg_n_0_[2] ),\n .I5(\\wl_state_r1_reg_n_0_[3] ),\n .O(flag_init_i_1_n_0));\n LUT5 #(\n .INIT(32'h04000000)) \n flag_init_i_2\n (.I0(out[3]),\n .I1(out[0]),\n .I2(out[4]),\n .I3(out[2]),\n .I4(out[1]),\n .O(p_1_in28_in));\n FDSE flag_init_reg\n (.C(CLK),\n .CE(1'b1),\n .D(flag_init_i_1_n_0),\n .Q(flag_init),\n .S(rstdiv0_sync_r1_reg_rep__18));\n LUT6 #(\n .INIT(64'h00000000EEEE22E2)) \n \\gen_byte_sel_div1.byte_sel_cnt[0]_i_1 \n (.I0(\\gen_byte_sel_div1.byte_sel_cnt_reg[0]_0 ),\n .I1(pi_f_inc_reg),\n .I2(dqs_count_r[0]),\n .I3(wrlvl_done_r_reg),\n .I4(oclkdelay_calib_done_r_reg_0),\n .I5(delay_done_r4_reg),\n .O(\\gen_byte_sel_div1.byte_sel_cnt_reg[0] ));\n LUT6 #(\n .INIT(64'h00000000EEEE22E2)) \n \\gen_byte_sel_div1.byte_sel_cnt[1]_i_1 \n (.I0(\\gen_byte_sel_div1.byte_sel_cnt_reg[1]_0 ),\n .I1(pi_f_inc_reg),\n .I2(dqs_count_r[1]),\n .I3(wrlvl_done_r_reg),\n .I4(oclkdelay_calib_done_r_reg_1),\n .I5(delay_done_r4_reg),\n .O(\\gen_byte_sel_div1.byte_sel_cnt_reg[1] ));\n LUT6 #(\n .INIT(64'h00000000EEE222E2)) \n \\gen_byte_sel_div1.byte_sel_cnt[2]_i_1 \n (.I0(byte_sel_cnt),\n .I1(pi_f_inc_reg),\n .I2(dqs_count_r[2]),\n .I3(wrlvl_done_r_reg),\n .I4(\\prbs_dqs_cnt_r_reg[2] ),\n .I5(delay_done_r4_reg),\n .O(\\gen_byte_sel_div1.byte_sel_cnt_reg[2] ));\n LUT2 #(\n .INIT(4'h2)) \n \\gen_final_tap[0].final_val[0][5]_i_1 \n (.I0(wr_level_done_r2),\n .I1(wr_level_done_r3),\n .O(p_21_out));\n FDRE \\gen_final_tap[0].final_val_reg[0][0] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[0]__0 [0]),\n .Q(\\gen_final_tap[0].final_val_reg_n_0_[0][0] ),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\gen_final_tap[0].final_val_reg[0][1] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[0]__0 [1]),\n .Q(\\gen_final_tap[0].final_val_reg_n_0_[0][1] ),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\gen_final_tap[0].final_val_reg[0][2] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[0]__0 [2]),\n .Q(\\gen_final_tap[0].final_val_reg_n_0_[0][2] ),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\gen_final_tap[0].final_val_reg[0][3] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[0]__0 [3]),\n .Q(\\gen_final_tap[0].final_val_reg_n_0_[0][3] ),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\gen_final_tap[0].final_val_reg[0][4] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[0]__0 [4]),\n .Q(\\gen_final_tap[0].final_val_reg_n_0_[0][4] ),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\gen_final_tap[0].final_val_reg[0][5] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[0]__0 [5]),\n .Q(\\gen_final_tap[0].final_val_reg_n_0_[0][5] ),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\gen_final_tap[1].final_val_reg[1][0] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[1]__0 [0]),\n .Q(\\gen_final_tap[1].final_val_reg_n_0_[1][0] ),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\gen_final_tap[1].final_val_reg[1][1] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[1]__0 [1]),\n .Q(\\gen_final_tap[1].final_val_reg_n_0_[1][1] ),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\gen_final_tap[1].final_val_reg[1][2] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[1]__0 [2]),\n .Q(\\gen_final_tap[1].final_val_reg_n_0_[1][2] ),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\gen_final_tap[1].final_val_reg[1][3] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[1]__0 [3]),\n .Q(\\gen_final_tap[1].final_val_reg_n_0_[1][3] ),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\gen_final_tap[1].final_val_reg[1][4] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[1]__0 [4]),\n .Q(\\gen_final_tap[1].final_val_reg_n_0_[1][4] ),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\gen_final_tap[1].final_val_reg[1][5] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[1]__0 [5]),\n .Q(\\gen_final_tap[1].final_val_reg_n_0_[1][5] ),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\gen_final_tap[2].final_val_reg[2][0] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[2]__0 [0]),\n .Q(\\gen_final_tap[2].final_val_reg_n_0_[2][0] ),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\gen_final_tap[2].final_val_reg[2][1] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[2]__0 [1]),\n .Q(\\gen_final_tap[2].final_val_reg_n_0_[2][1] ),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\gen_final_tap[2].final_val_reg[2][2] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[2]__0 [2]),\n .Q(\\gen_final_tap[2].final_val_reg_n_0_[2][2] ),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\gen_final_tap[2].final_val_reg[2][3] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[2]__0 [3]),\n .Q(\\gen_final_tap[2].final_val_reg_n_0_[2][3] ),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\gen_final_tap[2].final_val_reg[2][4] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[2]__0 [4]),\n .Q(\\gen_final_tap[2].final_val_reg_n_0_[2][4] ),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\gen_final_tap[2].final_val_reg[2][5] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[2]__0 [5]),\n .Q(\\gen_final_tap[2].final_val_reg_n_0_[2][5] ),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\gen_final_tap[3].final_val_reg[3][0] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[3]__0 [0]),\n .Q(\\gen_final_tap[3].final_val_reg_n_0_[3][0] ),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\gen_final_tap[3].final_val_reg[3][1] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[3]__0 [1]),\n .Q(\\gen_final_tap[3].final_val_reg_n_0_[3][1] ),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\gen_final_tap[3].final_val_reg[3][2] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[3]__0 [2]),\n .Q(\\gen_final_tap[3].final_val_reg_n_0_[3][2] ),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\gen_final_tap[3].final_val_reg[3][3] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[3]__0 [3]),\n .Q(\\gen_final_tap[3].final_val_reg_n_0_[3][3] ),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\gen_final_tap[3].final_val_reg[3][4] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[3]__0 [4]),\n .Q(\\gen_final_tap[3].final_val_reg_n_0_[3][4] ),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\gen_final_tap[3].final_val_reg[3][5] \n (.C(CLK),\n .CE(p_21_out),\n .D(\\smallest_reg[3]__0 [5]),\n .Q(\\gen_final_tap[3].final_val_reg_n_0_[3][5] ),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\gen_rd[0].rd_data_rise_wl_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_1_n_0 ),\n .Q(\\gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\gen_rd[1].rd_data_rise_wl_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_1_n_0 ),\n .Q(\\gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE \\gen_rd[2].rd_data_rise_wl_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_1_n_0 ),\n .Q(\\gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE \\gen_rd[3].rd_data_rise_wl_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_1_n_0 ),\n .Q(\\gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3] ),\n .R(1'b0));\n LUT1 #(\n .INIT(2'h1)) \n \\incdec_wait_cnt[0]_i_1 \n (.I0(incdec_wait_cnt_reg__0[0]),\n .O(p_0_in__0__0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair350\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\incdec_wait_cnt[1]_i_1 \n (.I0(incdec_wait_cnt_reg__0[0]),\n .I1(incdec_wait_cnt_reg__0[1]),\n .O(p_0_in__0__0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair350\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\incdec_wait_cnt[2]_i_1 \n (.I0(incdec_wait_cnt_reg__0[2]),\n .I1(incdec_wait_cnt_reg__0[1]),\n .I2(incdec_wait_cnt_reg__0[0]),\n .O(p_0_in__0__0[2]));\n LUT6 #(\n .INIT(64'hFFFBFFEFFEFFFFFF)) \n \\incdec_wait_cnt[3]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__23),\n .I1(out[1]),\n .I2(out[0]),\n .I3(out[4]),\n .I4(out[2]),\n .I5(out[3]),\n .O(\\incdec_wait_cnt[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair321\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\incdec_wait_cnt[3]_i_2 \n (.I0(incdec_wait_cnt_reg__0[3]),\n .I1(incdec_wait_cnt_reg__0[0]),\n .I2(incdec_wait_cnt_reg__0[1]),\n .I3(incdec_wait_cnt_reg__0[2]),\n .O(p_0_in__0__0[3]));\n FDRE \\incdec_wait_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0__0[0]),\n .Q(incdec_wait_cnt_reg__0[0]),\n .R(\\incdec_wait_cnt[3]_i_1_n_0 ));\n FDRE \\incdec_wait_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0__0[1]),\n .Q(incdec_wait_cnt_reg__0[1]),\n .R(\\incdec_wait_cnt[3]_i_1_n_0 ));\n FDRE \\incdec_wait_cnt_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0__0[2]),\n .Q(incdec_wait_cnt_reg__0[2]),\n .R(\\incdec_wait_cnt[3]_i_1_n_0 ));\n FDRE \\incdec_wait_cnt_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(p_0_in__0__0[3]),\n .Q(incdec_wait_cnt_reg__0[3]),\n .R(\\incdec_wait_cnt[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h2F203F3F2F203333)) \n inhibit_edge_detect_r_i_2\n (.I0(wrlvl_byte_redo),\n .I1(out[3]),\n .I2(out[4]),\n .I3(stable_cnt227_in),\n .I4(out[2]),\n .I5(\\FSM_sequential_wl_state_r[3]_i_10_n_0 ),\n .O(inhibit_edge_detect_r));\n LUT6 #(\n .INIT(64'h0000008303080003)) \n inhibit_edge_detect_r_i_3\n (.I0(inhibit_edge_detect_r_i_4_n_0),\n .I1(out[2]),\n .I2(out[4]),\n .I3(out[3]),\n .I4(out[1]),\n .I5(out[0]),\n .O(inhibit_edge_detect_r_reg_0));\n LUT6 #(\n .INIT(64'h8080808080808F80)) \n inhibit_edge_detect_r_i_4\n (.I0(wrlvl_byte_redo),\n .I1(\\FSM_sequential_wl_state_r[2]_i_6_n_0 ),\n .I2(out[4]),\n .I3(wl_sm_start),\n .I4(stable_cnt1),\n .I5(stable_cnt227_in),\n .O(inhibit_edge_detect_r_i_4_n_0));\n FDSE inhibit_edge_detect_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(inhibit_edge_detect_r_reg_1),\n .Q(\\rd_data_edge_detect_r_reg[0]_1 ),\n .S(rstdiv0_sync_r1_reg_rep__15));\n LUT6 #(\n .INIT(64'h222222F2F2F2F2FF)) \n \\lim_state[12]_i_6 \n (.I0(\\stg2_target_r_reg[4] [1]),\n .I1(\\stg2_tap_cnt_reg[2] [2]),\n .I2(\\stg2_target_r_reg[4] [0]),\n .I3(\\stg2_r_reg[0] ),\n .I4(\\stg2_tap_cnt_reg[2] [0]),\n .I5(\\stg2_tap_cnt_reg[2] [1]),\n .O(\\lim_state_reg[12] ));\n LUT5 #(\n .INIT(32'hFFFEFFFF)) \n \\p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_1 \n (.I0(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),\n .I2(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),\n .I4(\\p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_2_n_0 ),\n .O(\\p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000001105)) \n \\p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_2 \n (.I0(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),\n .I2(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ),\n .I3(my_empty),\n .I4(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),\n .O(\\p_0_out_inferred__0/gen_rd[0].rd_data_rise_wl_r[0]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFEFFFF)) \n \\p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_1 \n (.I0(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),\n .I2(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),\n .I4(\\p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_2_n_0 ),\n .O(\\p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000001105)) \n \\p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_2 \n (.I0(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),\n .I2(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ),\n .I3(my_empty_6),\n .I4(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),\n .O(\\p_0_out_inferred__1/gen_rd[1].rd_data_rise_wl_r[1]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFEFFFF)) \n \\p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_1 \n (.I0(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ),\n .I2(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ),\n .I4(\\p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_2_n_0 ),\n .O(\\p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000001105)) \n \\p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_2 \n (.I0(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ),\n .I2(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_1 ),\n .I3(my_empty_7),\n .I4(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),\n .O(\\p_0_out_inferred__2/gen_rd[2].rd_data_rise_wl_r[2]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFEFFFF)) \n \\p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_1 \n (.I0(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ),\n .I2(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ),\n .I3(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ),\n .I4(\\p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_2_n_0 ),\n .O(\\p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000001105)) \n \\p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_2 \n (.I0(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_2 ),\n .I1(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ),\n .I2(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ),\n .I3(my_empty_8),\n .I4(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ),\n .I5(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ),\n .O(\\p_0_out_inferred__3/gen_rd[3].rd_data_rise_wl_r[3]_i_2_n_0 ));\n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/phy_ctl_ready_r4_reg_srl4 \" *) \n SRL16E phy_ctl_ready_r4_reg_srl4\n (.A0(1'b1),\n .A1(1'b1),\n .A2(1'b0),\n .A3(1'b0),\n .CE(1'b1),\n .CLK(CLK),\n .D(\\mcGo_r_reg[15] ),\n .Q(phy_ctl_ready_r4_reg_srl4_n_0));\n FDRE phy_ctl_ready_r5_reg\n (.C(CLK),\n .CE(1'b1),\n .D(phy_ctl_ready_r4_reg_srl4_n_0),\n .Q(phy_ctl_ready_r5),\n .R(1'b0));\n FDRE phy_ctl_ready_r6_reg\n (.C(CLK),\n .CE(1'b1),\n .D(phy_ctl_ready_r5),\n .Q(phy_ctl_ready_r6_reg_n_0),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair316\" *) \n LUT5 #(\n .INIT(32'hFFFFFDFF)) \n po_cnt_dec_i_2\n (.I0(wait_cnt_reg__0[0]),\n .I1(wait_cnt_reg__0[1]),\n .I2(wait_cnt_reg__0[3]),\n .I3(phy_ctl_ready_r6_reg_n_0),\n .I4(wait_cnt_reg__0[2]),\n .O(po_cnt_dec_reg_0));\n FDRE po_cnt_dec_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\wait_cnt_reg[0]_0 ),\n .Q(dqs_po_en_stg2_f_reg_0),\n .R(1'b0));\n LUT3 #(\n .INIT(8'hF4)) \n po_dec_done_i_1\n (.I0(po_dec_done_i_2_n_0),\n .I1(po_dec_done_i_3_n_0),\n .I2(po_dec_done),\n .O(po_dec_done_i_1_n_0));\n LUT5 #(\n .INIT(32'hEEEFFFEF)) \n po_dec_done_i_2\n (.I0(po_rdval_cnt[2]),\n .I1(po_rdval_cnt[1]),\n .I2(phy_ctl_ready_r6_reg_n_0),\n .I3(po_rdval_cnt[0]),\n .I4(dqs_po_en_stg2_f_reg_0),\n .O(po_dec_done_i_2_n_0));\n LUT6 #(\n .INIT(64'h0000000000000001)) \n po_dec_done_i_3\n (.I0(po_rdval_cnt[7]),\n .I1(po_rdval_cnt[3]),\n .I2(po_rdval_cnt[4]),\n .I3(po_rdval_cnt[5]),\n .I4(po_rdval_cnt[6]),\n .I5(po_rdval_cnt[8]),\n .O(po_dec_done_i_3_n_0));\n FDRE po_dec_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(po_dec_done_i_1_n_0),\n .Q(po_dec_done),\n .R(rstdiv0_sync_r1_reg_rep__18));\n LUT6 #(\n .INIT(64'hAC00AC00ACFFAC00)) \n \\po_rdval_cnt[0]_i_1 \n (.I0(\\po_counter_read_val_reg[8] [0]),\n .I1(\\po_counter_read_val_reg[8]_0 [0]),\n .I2(\\calib_sel_reg[3] ),\n .I3(\\po_rdval_cnt[8]_i_4_n_0 ),\n .I4(\\po_rdval_cnt_reg[0]_0 ),\n .I5(po_rdval_cnt[0]),\n .O(\\po_rdval_cnt[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFB0808080808FB08)) \n \\po_rdval_cnt[1]_i_1 \n (.I0(\\po_counter_read_val_reg[5] [0]),\n .I1(phy_ctl_ready_r5),\n .I2(phy_ctl_ready_r6_reg_n_0),\n .I3(\\po_rdval_cnt_reg[0]_0 ),\n .I4(po_rdval_cnt[0]),\n .I5(po_rdval_cnt[1]),\n .O(\\po_rdval_cnt[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hB8B8B888888888B8)) \n \\po_rdval_cnt[2]_i_1 \n (.I0(\\po_counter_read_val_reg[5] [1]),\n .I1(\\po_rdval_cnt[8]_i_4_n_0 ),\n .I2(\\po_rdval_cnt_reg[0]_0 ),\n .I3(po_rdval_cnt[1]),\n .I4(po_rdval_cnt[0]),\n .I5(po_rdval_cnt[2]),\n .O(\\po_rdval_cnt[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAC00ACFFACFFAC00)) \n \\po_rdval_cnt[3]_i_1 \n (.I0(\\po_counter_read_val_reg[8] [1]),\n .I1(\\po_counter_read_val_reg[8]_0 [1]),\n .I2(\\calib_sel_reg[3] ),\n .I3(\\po_rdval_cnt[8]_i_4_n_0 ),\n .I4(po_rdval_cnt[3]),\n .I5(\\po_rdval_cnt[4]_i_2_n_0 ),\n .O(\\po_rdval_cnt[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFB0808FBFB08FB08)) \n \\po_rdval_cnt[4]_i_1 \n (.I0(\\po_counter_read_val_reg[5] [2]),\n .I1(phy_ctl_ready_r5),\n .I2(phy_ctl_ready_r6_reg_n_0),\n .I3(po_rdval_cnt[4]),\n .I4(po_rdval_cnt[3]),\n .I5(\\po_rdval_cnt[4]_i_2_n_0 ),\n .O(\\po_rdval_cnt[4]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h0001)) \n \\po_rdval_cnt[4]_i_2 \n (.I0(po_rdval_cnt[1]),\n .I1(po_rdval_cnt[0]),\n .I2(po_rdval_cnt[2]),\n .I3(po_dec_done_i_3_n_0),\n .O(\\po_rdval_cnt[4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFB0808080808FB08)) \n \\po_rdval_cnt[5]_i_1 \n (.I0(\\po_counter_read_val_reg[5] [3]),\n .I1(phy_ctl_ready_r5),\n .I2(phy_ctl_ready_r6_reg_n_0),\n .I3(\\po_rdval_cnt_reg[0]_0 ),\n .I4(\\po_rdval_cnt[5]_i_2_n_0 ),\n .I5(po_rdval_cnt[5]),\n .O(\\po_rdval_cnt[5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair315\" *) \n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n \\po_rdval_cnt[5]_i_2 \n (.I0(po_rdval_cnt[3]),\n .I1(po_rdval_cnt[4]),\n .I2(po_rdval_cnt[1]),\n .I3(po_rdval_cnt[0]),\n .I4(po_rdval_cnt[2]),\n .O(\\po_rdval_cnt[5]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFACFF0000AC00)) \n \\po_rdval_cnt[6]_i_1 \n (.I0(\\po_counter_read_val_reg[8] [2]),\n .I1(\\po_counter_read_val_reg[8]_0 [2]),\n .I2(\\calib_sel_reg[3] ),\n .I3(phy_ctl_ready_r5),\n .I4(phy_ctl_ready_r6_reg_n_0),\n .I5(\\po_rdval_cnt[6]_i_2_n_0 ),\n .O(\\po_rdval_cnt[6]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAA8A00000020)) \n \\po_rdval_cnt[6]_i_2 \n (.I0(\\po_rdval_cnt_reg[0]_0 ),\n .I1(po_rdval_cnt[5]),\n .I2(\\po_rdval_cnt[8]_i_7_n_0 ),\n .I3(po_rdval_cnt[4]),\n .I4(po_rdval_cnt[3]),\n .I5(po_rdval_cnt[6]),\n .O(\\po_rdval_cnt[6]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFACFF0000AC00)) \n \\po_rdval_cnt[7]_i_1 \n (.I0(\\po_counter_read_val_reg[8] [3]),\n .I1(\\po_counter_read_val_reg[8]_0 [3]),\n .I2(\\calib_sel_reg[3] ),\n .I3(phy_ctl_ready_r5),\n .I4(phy_ctl_ready_r6_reg_n_0),\n .I5(\\po_rdval_cnt[7]_i_2_n_0 ),\n .O(\\po_rdval_cnt[7]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFC00000002)) \n \\po_rdval_cnt[7]_i_2 \n (.I0(po_rdval_cnt[8]),\n .I1(po_rdval_cnt[1]),\n .I2(po_rdval_cnt[0]),\n .I3(po_rdval_cnt[2]),\n .I4(\\po_rdval_cnt[8]_i_6_n_0 ),\n .I5(po_rdval_cnt[7]),\n .O(\\po_rdval_cnt[7]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'hAEFF)) \n \\po_rdval_cnt[8]_i_1 \n (.I0(dqs_po_en_stg2_f_reg_0),\n .I1(phy_ctl_ready_r5),\n .I2(phy_ctl_ready_r6_reg_n_0),\n .I3(\\po_rdval_cnt_reg[0]_0 ),\n .O(\\po_rdval_cnt[8]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hACFFAC00AC00AC00)) \n \\po_rdval_cnt[8]_i_2 \n (.I0(\\po_counter_read_val_reg[8] [4]),\n .I1(\\po_counter_read_val_reg[8]_0 [4]),\n .I2(\\calib_sel_reg[3] ),\n .I3(\\po_rdval_cnt[8]_i_4_n_0 ),\n .I4(po_rdval_cnt[8]),\n .I5(\\po_rdval_cnt[8]_i_5_n_0 ),\n .O(\\po_rdval_cnt[8]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\po_rdval_cnt[8]_i_3 \n (.I0(po_rdval_cnt[8]),\n .I1(po_rdval_cnt[1]),\n .I2(po_rdval_cnt[0]),\n .I3(po_rdval_cnt[2]),\n .I4(\\po_rdval_cnt[8]_i_6_n_0 ),\n .I5(po_rdval_cnt[7]),\n .O(\\po_rdval_cnt_reg[0]_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\po_rdval_cnt[8]_i_4 \n (.I0(phy_ctl_ready_r5),\n .I1(phy_ctl_ready_r6_reg_n_0),\n .O(\\po_rdval_cnt[8]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFEFFFFFFFF)) \n \\po_rdval_cnt[8]_i_5 \n (.I0(po_rdval_cnt[7]),\n .I1(po_rdval_cnt[3]),\n .I2(po_rdval_cnt[4]),\n .I3(po_rdval_cnt[5]),\n .I4(po_rdval_cnt[6]),\n .I5(\\po_rdval_cnt[8]_i_7_n_0 ),\n .O(\\po_rdval_cnt[8]_i_5_n_0 ));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\po_rdval_cnt[8]_i_6 \n (.I0(po_rdval_cnt[3]),\n .I1(po_rdval_cnt[4]),\n .I2(po_rdval_cnt[5]),\n .I3(po_rdval_cnt[6]),\n .O(\\po_rdval_cnt[8]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair315\" *) \n LUT3 #(\n .INIT(8'h01)) \n \\po_rdval_cnt[8]_i_7 \n (.I0(po_rdval_cnt[2]),\n .I1(po_rdval_cnt[0]),\n .I2(po_rdval_cnt[1]),\n .O(\\po_rdval_cnt[8]_i_7_n_0 ));\n FDRE \\po_rdval_cnt_reg[0] \n (.C(CLK),\n .CE(\\po_rdval_cnt[8]_i_1_n_0 ),\n .D(\\po_rdval_cnt[0]_i_1_n_0 ),\n .Q(po_rdval_cnt[0]),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\po_rdval_cnt_reg[1] \n (.C(CLK),\n .CE(\\po_rdval_cnt[8]_i_1_n_0 ),\n .D(\\po_rdval_cnt[1]_i_1_n_0 ),\n .Q(po_rdval_cnt[1]),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\po_rdval_cnt_reg[2] \n (.C(CLK),\n .CE(\\po_rdval_cnt[8]_i_1_n_0 ),\n .D(\\po_rdval_cnt[2]_i_1_n_0 ),\n .Q(po_rdval_cnt[2]),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\po_rdval_cnt_reg[3] \n (.C(CLK),\n .CE(\\po_rdval_cnt[8]_i_1_n_0 ),\n .D(\\po_rdval_cnt[3]_i_1_n_0 ),\n .Q(po_rdval_cnt[3]),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\po_rdval_cnt_reg[4] \n (.C(CLK),\n .CE(\\po_rdval_cnt[8]_i_1_n_0 ),\n .D(\\po_rdval_cnt[4]_i_1_n_0 ),\n .Q(po_rdval_cnt[4]),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\po_rdval_cnt_reg[5] \n (.C(CLK),\n .CE(\\po_rdval_cnt[8]_i_1_n_0 ),\n .D(\\po_rdval_cnt[5]_i_1_n_0 ),\n .Q(po_rdval_cnt[5]),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\po_rdval_cnt_reg[6] \n (.C(CLK),\n .CE(\\po_rdval_cnt[8]_i_1_n_0 ),\n .D(\\po_rdval_cnt[6]_i_1_n_0 ),\n .Q(po_rdval_cnt[6]),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\po_rdval_cnt_reg[7] \n (.C(CLK),\n .CE(\\po_rdval_cnt[8]_i_1_n_0 ),\n .D(\\po_rdval_cnt[7]_i_1_n_0 ),\n .Q(po_rdval_cnt[7]),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\po_rdval_cnt_reg[8] \n (.C(CLK),\n .CE(\\po_rdval_cnt[8]_i_1_n_0 ),\n .D(\\po_rdval_cnt[8]_i_2_n_0 ),\n .Q(po_rdval_cnt[8]),\n .R(rstdiv0_sync_r1_reg_rep__15));\n (* SOFT_HLUTNM = \"soft_lutpair349\" *) \n LUT3 #(\n .INIT(8'h38)) \n \\rank_cnt_r[0]_i_1 \n (.I0(\\rank_cnt_r_reg[0]_0 ),\n .I1(rank_cnt_r),\n .I2(\\rank_cnt_r_reg[0]_1 ),\n .O(\\rank_cnt_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair349\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\rank_cnt_r[1]_i_1 \n (.I0(\\rank_cnt_r_reg[0]_1 ),\n .I1(rank_cnt_r),\n .I2(\\rank_cnt_r_reg[0]_0 ),\n .O(\\rank_cnt_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000200000000000)) \n \\rank_cnt_r[1]_i_2 \n (.I0(out[4]),\n .I1(out[2]),\n .I2(out[1]),\n .I3(out[0]),\n .I4(p_0_in),\n .I5(out[3]),\n .O(rank_cnt_r));\n FDRE \\rank_cnt_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rank_cnt_r[0]_i_1_n_0 ),\n .Q(\\rank_cnt_r_reg[0]_1 ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\rank_cnt_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rank_cnt_r[1]_i_1_n_0 ),\n .Q(\\rank_cnt_r_reg[0]_0 ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n (* SOFT_HLUTNM = \"soft_lutpair344\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\rd_data_edge_detect_r[0]_i_1 \n (.I0(\\rd_data_edge_detect_r[3]_i_6_n_0 ),\n .I1(\\gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ),\n .I2(\\rd_data_previous_r_reg_n_0_[0] ),\n .O(\\rd_data_edge_detect_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair344\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\rd_data_edge_detect_r[1]_i_1 \n (.I0(\\rd_data_edge_detect_r[3]_i_6_n_0 ),\n .I1(\\gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ),\n .I2(\\rd_data_previous_r_reg_n_0_[1] ),\n .O(\\rd_data_edge_detect_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair346\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\rd_data_edge_detect_r[2]_i_1 \n (.I0(\\rd_data_edge_detect_r[3]_i_6_n_0 ),\n .I1(\\gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2] ),\n .I2(\\rd_data_previous_r_reg_n_0_[2] ),\n .O(\\rd_data_edge_detect_r[2]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n \\rd_data_edge_detect_r[3]_i_1 \n (.I0(\\rd_data_edge_detect_r[3]_i_4_n_0 ),\n .I1(\\rd_data_edge_detect_r_reg[0]_1 ),\n .I2(flag_init),\n .I3(rstdiv0_sync_r1_reg_rep__23),\n .I4(\\rd_data_edge_detect_r_reg[0]_0 ),\n .O(rd_data_edge_detect_r0));\n LUT6 #(\n .INIT(64'h49484044FFFFFFFF)) \n \\rd_data_edge_detect_r[3]_i_2 \n (.I0(out[3]),\n .I1(out[2]),\n .I2(out[4]),\n .I3(out[0]),\n .I4(out[1]),\n .I5(\\rd_data_edge_detect_r[3]_i_5_n_0 ),\n .O(\\rd_data_edge_detect_r[3]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair346\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\rd_data_edge_detect_r[3]_i_3 \n (.I0(\\rd_data_edge_detect_r[3]_i_6_n_0 ),\n .I1(\\gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3] ),\n .I2(\\rd_data_previous_r_reg_n_0_[3] ),\n .O(\\rd_data_edge_detect_r[3]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000001)) \n \\rd_data_edge_detect_r[3]_i_4 \n (.I0(\\wl_tap_count_r_reg_n_0_[0] ),\n .I1(\\wl_tap_count_r_reg_n_0_[1] ),\n .I2(\\wl_tap_count_r_reg_n_0_[2] ),\n .I3(\\wl_tap_count_r_reg_n_0_[3] ),\n .I4(\\wl_tap_count_r_reg_n_0_[5] ),\n .I5(\\wl_tap_count_r_reg_n_0_[4] ),\n .O(\\rd_data_edge_detect_r[3]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\rd_data_edge_detect_r[3]_i_5 \n (.I0(\\rd_data_edge_detect_r_reg_n_0_[3] ),\n .I1(\\rd_data_edge_detect_r_reg_n_0_[2] ),\n .I2(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I3(\\rd_data_edge_detect_r_reg_n_0_[1] ),\n .I4(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I5(\\rd_data_edge_detect_r_reg_n_0_[0] ),\n .O(\\rd_data_edge_detect_r[3]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair314\" *) \n LUT5 #(\n .INIT(32'h000080FF)) \n \\rd_data_edge_detect_r[3]_i_6 \n (.I0(\\stable_cnt_reg_n_0_[3] ),\n .I1(\\stable_cnt_reg_n_0_[2] ),\n .I2(\\stable_cnt_reg_n_0_[1] ),\n .I3(stable_cnt227_in),\n .I4(\\rd_data_edge_detect_r[3]_i_5_n_0 ),\n .O(\\rd_data_edge_detect_r[3]_i_6_n_0 ));\n FDRE \\rd_data_edge_detect_r_reg[0] \n (.C(CLK),\n .CE(\\rd_data_edge_detect_r[3]_i_2_n_0 ),\n .D(\\rd_data_edge_detect_r[0]_i_1_n_0 ),\n .Q(\\rd_data_edge_detect_r_reg_n_0_[0] ),\n .R(rd_data_edge_detect_r0));\n FDRE \\rd_data_edge_detect_r_reg[1] \n (.C(CLK),\n .CE(\\rd_data_edge_detect_r[3]_i_2_n_0 ),\n .D(\\rd_data_edge_detect_r[1]_i_1_n_0 ),\n .Q(\\rd_data_edge_detect_r_reg_n_0_[1] ),\n .R(rd_data_edge_detect_r0));\n FDRE \\rd_data_edge_detect_r_reg[2] \n (.C(CLK),\n .CE(\\rd_data_edge_detect_r[3]_i_2_n_0 ),\n .D(\\rd_data_edge_detect_r[2]_i_1_n_0 ),\n .Q(\\rd_data_edge_detect_r_reg_n_0_[2] ),\n .R(rd_data_edge_detect_r0));\n FDRE \\rd_data_edge_detect_r_reg[3] \n (.C(CLK),\n .CE(\\rd_data_edge_detect_r[3]_i_2_n_0 ),\n .D(\\rd_data_edge_detect_r[3]_i_3_n_0 ),\n .Q(\\rd_data_edge_detect_r_reg_n_0_[3] ),\n .R(rd_data_edge_detect_r0));\n LUT6 #(\n .INIT(64'hAAEEAAAAFFABAAFA)) \n \\rd_data_previous_r[3]_i_1 \n (.I0(\\rd_data_previous_r[3]_i_2_n_0 ),\n .I1(out[1]),\n .I2(out[0]),\n .I3(out[4]),\n .I4(out[2]),\n .I5(out[3]),\n .O(rd_data_previous_r0));\n LUT6 #(\n .INIT(64'hFFFFFFFF00000020)) \n \\rd_data_previous_r[3]_i_2 \n (.I0(\\FSM_sequential_wl_state_r_reg[0]_0 ),\n .I1(\\rd_data_previous_r[3]_i_3_n_0 ),\n .I2(out[3]),\n .I3(out[2]),\n .I4(out[1]),\n .I5(\\rd_data_previous_r[3]_i_4_n_0 ),\n .O(\\rd_data_previous_r[3]_i_2_n_0 ));\n LUT2 #(\n .INIT(4'hB)) \n \\rd_data_previous_r[3]_i_3 \n (.I0(out[0]),\n .I1(out[4]),\n .O(\\rd_data_previous_r[3]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000400)) \n \\rd_data_previous_r[3]_i_4 \n (.I0(\\wl_state_r1_reg_n_0_[0] ),\n .I1(p_0_in32_in),\n .I2(\\wl_state_r1_reg_n_0_[4] ),\n .I3(\\wl_state_r1_reg_n_0_[2] ),\n .I4(\\wl_state_r1_reg_n_0_[3] ),\n .I5(\\wl_state_r1_reg_n_0_[1] ),\n .O(\\rd_data_previous_r[3]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h00000100)) \n \\rd_data_previous_r[3]_i_5 \n (.I0(out[3]),\n .I1(out[4]),\n .I2(out[0]),\n .I3(out[1]),\n .I4(out[2]),\n .O(p_0_in32_in));\n FDRE \\rd_data_previous_r_reg[0] \n (.C(CLK),\n .CE(rd_data_previous_r0),\n .D(\\gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ),\n .Q(\\rd_data_previous_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\rd_data_previous_r_reg[1] \n (.C(CLK),\n .CE(rd_data_previous_r0),\n .D(\\gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ),\n .Q(\\rd_data_previous_r_reg_n_0_[1] ),\n .R(1'b0));\n FDRE \\rd_data_previous_r_reg[2] \n (.C(CLK),\n .CE(rd_data_previous_r0),\n .D(\\gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2] ),\n .Q(\\rd_data_previous_r_reg_n_0_[2] ),\n .R(1'b0));\n FDRE \\rd_data_previous_r_reg[3] \n (.C(CLK),\n .CE(rd_data_previous_r0),\n .D(\\gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3] ),\n .Q(\\rd_data_previous_r_reg_n_0_[3] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h000000000000FBF8)) \n \\single_rank.done_dqs_dec_i_1 \n (.I0(done_dqs_tap_inc),\n .I1(oclkdelay_calib_done_r_reg),\n .I2(done_dqs_dec),\n .I3(wr_level_done_r1_reg_0),\n .I4(wr_level_done0),\n .I5(rstdiv0_sync_r1_reg_rep__23),\n .O(\\single_rank.done_dqs_dec_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair345\" *) \n LUT3 #(\n .INIT(8'h08)) \n \\single_rank.done_dqs_dec_i_2 \n (.I0(oclkdelay_calib_done_r_reg),\n .I1(wr_level_done_r3),\n .I2(wr_level_done_r4),\n .O(done_dqs_dec));\n (* SOFT_HLUTNM = \"soft_lutpair322\" *) \n LUT4 #(\n .INIT(16'h4F44)) \n \\single_rank.done_dqs_dec_i_3 \n (.I0(wrlvl_byte_redo_r),\n .I1(wrlvl_byte_redo),\n .I2(wrlvl_final_r),\n .I3(wrlvl_final_mux),\n .O(wr_level_done0));\n FDRE \\single_rank.done_dqs_dec_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\single_rank.done_dqs_dec_i_1_n_0 ),\n .Q(done_dqs_tap_inc),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair332\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[0][0]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][0][0] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][0]_i_2_n_0 ),\n .O(largest[0]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\smallest[0][0]_i_2 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][3][0] ),\n .I1(\\wl_dqs_tap_count_r_reg_n_0_[0][1][0] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\wl_dqs_tap_count_r_reg_n_0_[0][2][0] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\wl_dqs_tap_count_r_reg_n_0_[0][0][0] ),\n .O(\\smallest[0][0]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair333\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[0][1]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][0][1] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][1]_i_2_n_0 ),\n .O(largest[1]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\smallest[0][1]_i_2 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][3][1] ),\n .I1(\\wl_dqs_tap_count_r_reg_n_0_[0][1][1] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\wl_dqs_tap_count_r_reg_n_0_[0][2][1] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\wl_dqs_tap_count_r_reg_n_0_[0][0][1] ),\n .O(\\smallest[0][1]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair332\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[0][2]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][0][2] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][2]_i_2_n_0 ),\n .O(largest[2]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\smallest[0][2]_i_2 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][3][2] ),\n .I1(\\wl_dqs_tap_count_r_reg_n_0_[0][1][2] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\wl_dqs_tap_count_r_reg_n_0_[0][2][2] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\wl_dqs_tap_count_r_reg_n_0_[0][0][2] ),\n .O(\\smallest[0][2]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair334\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[0][3]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][0][3] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][3]_i_2_n_0 ),\n .O(largest[3]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\smallest[0][3]_i_2 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][3][3] ),\n .I1(\\wl_dqs_tap_count_r_reg_n_0_[0][1][3] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\wl_dqs_tap_count_r_reg_n_0_[0][2][3] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\wl_dqs_tap_count_r_reg_n_0_[0][0][3] ),\n .O(\\smallest[0][3]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair333\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[0][4]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][0][4] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][4]_i_2_n_0 ),\n .O(largest[4]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\smallest[0][4]_i_2 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][3][4] ),\n .I1(\\wl_dqs_tap_count_r_reg_n_0_[0][1][4] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\wl_dqs_tap_count_r_reg_n_0_[0][2][4] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\wl_dqs_tap_count_r_reg_n_0_[0][0][4] ),\n .O(\\smallest[0][4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0010FFFF00100000)) \n \\smallest[0][5]_i_2 \n (.I0(wr_level_done_r2),\n .I1(oclkdelay_calib_done_r_reg),\n .I2(wr_level_done_r1),\n .I3(wrlvl_byte_redo),\n .I4(\\smallest[0][5]_i_4_n_0 ),\n .I5(\\fine_inc[0][5]_i_3_n_0 ),\n .O(\\smallest[0][5]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair334\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[0][5]_i_3 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][0][5] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][5]_i_5_n_0 ),\n .O(largest[5]));\n LUT5 #(\n .INIT(32'hFDFFF7FF)) \n \\smallest[0][5]_i_4 \n (.I0(out[4]),\n .I1(out[0]),\n .I2(out[2]),\n .I3(out[3]),\n .I4(out[1]),\n .O(\\smallest[0][5]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\smallest[0][5]_i_5 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][3][5] ),\n .I1(\\wl_dqs_tap_count_r_reg_n_0_[0][1][5] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\wl_dqs_tap_count_r_reg_n_0_[0][2][5] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\wl_dqs_tap_count_r_reg_n_0_[0][0][5] ),\n .O(\\smallest[0][5]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair327\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[1][0]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][1][0] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][0]_i_2_n_0 ),\n .O(\\smallest[1][0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair327\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[1][1]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][1][1] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][1]_i_2_n_0 ),\n .O(\\smallest[1][1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair330\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[1][2]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][1][2] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][2]_i_2_n_0 ),\n .O(\\smallest[1][2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair330\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[1][3]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][1][3] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][3]_i_2_n_0 ),\n .O(\\smallest[1][3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair331\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[1][4]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][1][4] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][4]_i_2_n_0 ),\n .O(\\smallest[1][4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0010FFFF00100000)) \n \\smallest[1][5]_i_1 \n (.I0(wr_level_done_r2),\n .I1(oclkdelay_calib_done_r_reg),\n .I2(wr_level_done_r1),\n .I3(wrlvl_byte_redo),\n .I4(\\smallest[0][5]_i_4_n_0 ),\n .I5(\\fine_inc[1][5]_i_3_n_0 ),\n .O(\\smallest[1][5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair331\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[1][5]_i_2 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][1][5] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][5]_i_5_n_0 ),\n .O(\\smallest[1][5]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair324\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[2][0]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][2][0] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][0]_i_2_n_0 ),\n .O(\\smallest[2][0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair324\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[2][1]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][2][1] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][1]_i_2_n_0 ),\n .O(\\smallest[2][1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair325\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[2][2]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][2][2] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][2]_i_2_n_0 ),\n .O(\\smallest[2][2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair325\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[2][3]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][2][3] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][3]_i_2_n_0 ),\n .O(\\smallest[2][3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair329\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[2][4]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][2][4] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][4]_i_2_n_0 ),\n .O(\\smallest[2][4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0010FFFF00100000)) \n \\smallest[2][5]_i_1 \n (.I0(wr_level_done_r2),\n .I1(oclkdelay_calib_done_r_reg),\n .I2(wr_level_done_r1),\n .I3(wrlvl_byte_redo),\n .I4(\\smallest[0][5]_i_4_n_0 ),\n .I5(\\fine_inc[2][5]_i_3_n_0 ),\n .O(\\smallest[2][5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair329\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[2][5]_i_2 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][2][5] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][5]_i_5_n_0 ),\n .O(\\smallest[2][5]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair323\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[3][0]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][3][0] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][0]_i_2_n_0 ),\n .O(\\smallest[3][0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair326\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[3][1]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][3][1] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][1]_i_2_n_0 ),\n .O(\\smallest[3][1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair328\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[3][2]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][3][2] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][2]_i_2_n_0 ),\n .O(\\smallest[3][2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair328\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[3][3]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][3][3] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][3]_i_2_n_0 ),\n .O(\\smallest[3][3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair326\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[3][4]_i_1 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][3][4] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][4]_i_2_n_0 ),\n .O(\\smallest[3][4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0010FFFF00100000)) \n \\smallest[3][5]_i_1 \n (.I0(wr_level_done_r2),\n .I1(oclkdelay_calib_done_r_reg),\n .I2(wr_level_done_r1),\n .I3(wrlvl_byte_redo),\n .I4(\\smallest[0][5]_i_4_n_0 ),\n .I5(\\fine_inc[3][5]_i_5_n_0 ),\n .O(\\smallest[3][5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair323\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\smallest[3][5]_i_2 \n (.I0(\\wl_dqs_tap_count_r_reg_n_0_[0][3][5] ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(\\smallest[0][5]_i_5_n_0 ),\n .O(\\smallest[3][5]_i_2_n_0 ));\n FDRE \\smallest_reg[0][0] \n (.C(CLK),\n .CE(\\smallest[0][5]_i_2_n_0 ),\n .D(largest[0]),\n .Q(\\smallest_reg[0]__0 [0]),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\smallest_reg[0][1] \n (.C(CLK),\n .CE(\\smallest[0][5]_i_2_n_0 ),\n .D(largest[1]),\n .Q(\\smallest_reg[0]__0 [1]),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\smallest_reg[0][2] \n (.C(CLK),\n .CE(\\smallest[0][5]_i_2_n_0 ),\n .D(largest[2]),\n .Q(\\smallest_reg[0]__0 [2]),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\smallest_reg[0][3] \n (.C(CLK),\n .CE(\\smallest[0][5]_i_2_n_0 ),\n .D(largest[3]),\n .Q(\\smallest_reg[0]__0 [3]),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\smallest_reg[0][4] \n (.C(CLK),\n .CE(\\smallest[0][5]_i_2_n_0 ),\n .D(largest[4]),\n .Q(\\smallest_reg[0]__0 [4]),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\smallest_reg[0][5] \n (.C(CLK),\n .CE(\\smallest[0][5]_i_2_n_0 ),\n .D(largest[5]),\n .Q(\\smallest_reg[0]__0 [5]),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\smallest_reg[1][0] \n (.C(CLK),\n .CE(\\smallest[1][5]_i_1_n_0 ),\n .D(\\smallest[1][0]_i_1_n_0 ),\n .Q(\\smallest_reg[1]__0 [0]),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\smallest_reg[1][1] \n (.C(CLK),\n .CE(\\smallest[1][5]_i_1_n_0 ),\n .D(\\smallest[1][1]_i_1_n_0 ),\n .Q(\\smallest_reg[1]__0 [1]),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\smallest_reg[1][2] \n (.C(CLK),\n .CE(\\smallest[1][5]_i_1_n_0 ),\n .D(\\smallest[1][2]_i_1_n_0 ),\n .Q(\\smallest_reg[1]__0 [2]),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\smallest_reg[1][3] \n (.C(CLK),\n .CE(\\smallest[1][5]_i_1_n_0 ),\n .D(\\smallest[1][3]_i_1_n_0 ),\n .Q(\\smallest_reg[1]__0 [3]),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\smallest_reg[1][4] \n (.C(CLK),\n .CE(\\smallest[1][5]_i_1_n_0 ),\n .D(\\smallest[1][4]_i_1_n_0 ),\n .Q(\\smallest_reg[1]__0 [4]),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\smallest_reg[1][5] \n (.C(CLK),\n .CE(\\smallest[1][5]_i_1_n_0 ),\n .D(\\smallest[1][5]_i_2_n_0 ),\n .Q(\\smallest_reg[1]__0 [5]),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\smallest_reg[2][0] \n (.C(CLK),\n .CE(\\smallest[2][5]_i_1_n_0 ),\n .D(\\smallest[2][0]_i_1_n_0 ),\n .Q(\\smallest_reg[2]__0 [0]),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\smallest_reg[2][1] \n (.C(CLK),\n .CE(\\smallest[2][5]_i_1_n_0 ),\n .D(\\smallest[2][1]_i_1_n_0 ),\n .Q(\\smallest_reg[2]__0 [1]),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\smallest_reg[2][2] \n (.C(CLK),\n .CE(\\smallest[2][5]_i_1_n_0 ),\n .D(\\smallest[2][2]_i_1_n_0 ),\n .Q(\\smallest_reg[2]__0 [2]),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\smallest_reg[2][3] \n (.C(CLK),\n .CE(\\smallest[2][5]_i_1_n_0 ),\n .D(\\smallest[2][3]_i_1_n_0 ),\n .Q(\\smallest_reg[2]__0 [3]),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\smallest_reg[2][4] \n (.C(CLK),\n .CE(\\smallest[2][5]_i_1_n_0 ),\n .D(\\smallest[2][4]_i_1_n_0 ),\n .Q(\\smallest_reg[2]__0 [4]),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\smallest_reg[2][5] \n (.C(CLK),\n .CE(\\smallest[2][5]_i_1_n_0 ),\n .D(\\smallest[2][5]_i_2_n_0 ),\n .Q(\\smallest_reg[2]__0 [5]),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\smallest_reg[3][0] \n (.C(CLK),\n .CE(\\smallest[3][5]_i_1_n_0 ),\n .D(\\smallest[3][0]_i_1_n_0 ),\n .Q(\\smallest_reg[3]__0 [0]),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\smallest_reg[3][1] \n (.C(CLK),\n .CE(\\smallest[3][5]_i_1_n_0 ),\n .D(\\smallest[3][1]_i_1_n_0 ),\n .Q(\\smallest_reg[3]__0 [1]),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\smallest_reg[3][2] \n (.C(CLK),\n .CE(\\smallest[3][5]_i_1_n_0 ),\n .D(\\smallest[3][2]_i_1_n_0 ),\n .Q(\\smallest_reg[3]__0 [2]),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\smallest_reg[3][3] \n (.C(CLK),\n .CE(\\smallest[3][5]_i_1_n_0 ),\n .D(\\smallest[3][3]_i_1_n_0 ),\n .Q(\\smallest_reg[3]__0 [3]),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\smallest_reg[3][4] \n (.C(CLK),\n .CE(\\smallest[3][5]_i_1_n_0 ),\n .D(\\smallest[3][4]_i_1_n_0 ),\n .Q(\\smallest_reg[3]__0 [4]),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\smallest_reg[3][5] \n (.C(CLK),\n .CE(\\smallest[3][5]_i_1_n_0 ),\n .D(\\smallest[3][5]_i_2_n_0 ),\n .Q(\\smallest_reg[3]__0 [5]),\n .R(rstdiv0_sync_r1_reg_rep__16));\n (* SOFT_HLUTNM = \"soft_lutpair352\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\stable_cnt[0]_i_1 \n (.I0(\\stable_cnt_reg[3]_0 ),\n .O(p_0_in__0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair352\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\stable_cnt[1]_i_1 \n (.I0(\\stable_cnt_reg[3]_0 ),\n .I1(\\stable_cnt_reg_n_0_[1] ),\n .O(p_0_in__0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair320\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\stable_cnt[2]_i_1 \n (.I0(\\stable_cnt_reg_n_0_[2] ),\n .I1(\\stable_cnt_reg_n_0_[1] ),\n .I2(\\stable_cnt_reg[3]_0 ),\n .O(p_0_in__0[2]));\n LUT5 #(\n .INIT(32'hFFFFFFFB)) \n \\stable_cnt[3]_i_1 \n (.I0(\\stable_cnt[3]_i_4_n_0 ),\n .I1(\\smallest[0][5]_i_4_n_0 ),\n .I2(p_1_in1_in),\n .I3(rstdiv0_sync_r1_reg_rep__23),\n .I4(\\stable_cnt[3]_i_6_n_0 ),\n .O(stable_cnt0));\n LUT6 #(\n .INIT(64'h0000000015550000)) \n \\stable_cnt[3]_i_2 \n (.I0(\\rd_data_edge_detect_r[3]_i_4_n_0 ),\n .I1(\\stable_cnt_reg_n_0_[1] ),\n .I2(\\stable_cnt_reg_n_0_[2] ),\n .I3(\\stable_cnt_reg_n_0_[3] ),\n .I4(\\rd_data_previous_r[3]_i_2_n_0 ),\n .I5(\\stable_cnt[3]_i_4_n_0 ),\n .O(stable_cnt));\n (* SOFT_HLUTNM = \"soft_lutpair320\" *) \n LUT4 #(\n .INIT(16'h6AAA)) \n \\stable_cnt[3]_i_3 \n (.I0(\\stable_cnt_reg_n_0_[3] ),\n .I1(\\stable_cnt_reg[3]_0 ),\n .I2(\\stable_cnt_reg_n_0_[1] ),\n .I3(\\stable_cnt_reg_n_0_[2] ),\n .O(p_0_in__0[3]));\n LUT2 #(\n .INIT(4'h6)) \n \\stable_cnt[3]_i_4 \n (.I0(stable_cnt227_in),\n .I1(\\stable_cnt[3]_i_7_n_0 ),\n .O(\\stable_cnt[3]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h00000020)) \n \\stable_cnt[3]_i_5 \n (.I0(out[1]),\n .I1(out[4]),\n .I2(out[0]),\n .I3(out[3]),\n .I4(out[2]),\n .O(p_1_in1_in));\n LUT5 #(\n .INIT(32'h00000020)) \n \\stable_cnt[3]_i_6 \n (.I0(\\wl_state_r1_reg_n_0_[0] ),\n .I1(\\wl_state_r1_reg_n_0_[4] ),\n .I2(\\wl_state_r1_reg_n_0_[2] ),\n .I3(\\wl_state_r1_reg_n_0_[3] ),\n .I4(\\wl_state_r1_reg_n_0_[1] ),\n .O(\\stable_cnt[3]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\stable_cnt[3]_i_7 \n (.I0(\\gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3] ),\n .I1(\\gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2] ),\n .I2(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I3(\\gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ),\n .I4(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I5(\\gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ),\n .O(\\stable_cnt[3]_i_7_n_0 ));\n FDRE \\stable_cnt_reg[0] \n (.C(CLK),\n .CE(stable_cnt),\n .D(p_0_in__0[0]),\n .Q(\\stable_cnt_reg[3]_0 ),\n .R(stable_cnt0));\n FDRE \\stable_cnt_reg[1] \n (.C(CLK),\n .CE(stable_cnt),\n .D(p_0_in__0[1]),\n .Q(\\stable_cnt_reg_n_0_[1] ),\n .R(stable_cnt0));\n FDRE \\stable_cnt_reg[2] \n (.C(CLK),\n .CE(stable_cnt),\n .D(p_0_in__0[2]),\n .Q(\\stable_cnt_reg_n_0_[2] ),\n .R(stable_cnt0));\n FDRE \\stable_cnt_reg[3] \n (.C(CLK),\n .CE(stable_cnt),\n .D(p_0_in__0[3]),\n .Q(\\stable_cnt_reg_n_0_[3] ),\n .R(stable_cnt0));\n LUT6 #(\n .INIT(64'h55330F0055330FFF)) \n \\stg2_tap_cnt[0]_i_2 \n (.I0(wl_po_fine_cnt[18]),\n .I1(wl_po_fine_cnt[12]),\n .I2(wl_po_fine_cnt[6]),\n .I3(\\byte_r_reg[0] ),\n .I4(\\byte_r_reg[1] ),\n .I5(wl_po_fine_cnt[0]),\n .O(\\stg2_r_reg[0] ));\n LUT6 #(\n .INIT(64'h55FFDDF05500DDF0)) \n \\stg2_tap_cnt[1]_i_2 \n (.I0(\\stg2_tap_cnt[3]_i_4_n_0 ),\n .I1(wl_po_fine_cnt[7]),\n .I2(wl_po_fine_cnt[1]),\n .I3(\\byte_r_reg[0] ),\n .I4(\\byte_r_reg[1] ),\n .I5(wl_po_fine_cnt[13]),\n .O(\\stg2_target_r_reg[4] [0]));\n LUT6 #(\n .INIT(64'hFFAAF0CC00AAF0CC)) \n \\stg2_tap_cnt[2]_i_2 \n (.I0(wl_po_fine_cnt[14]),\n .I1(wl_po_fine_cnt[2]),\n .I2(wl_po_fine_cnt[8]),\n .I3(\\byte_r_reg[0] ),\n .I4(\\byte_r_reg[1] ),\n .I5(wl_po_fine_cnt[20]),\n .O(\\stg2_target_r_reg[4] [1]));\n LUT6 #(\n .INIT(64'h00AA0F22FFAA0F22)) \n \\stg2_tap_cnt[3]_i_2 \n (.I0(\\stg2_tap_cnt[3]_i_4_n_0 ),\n .I1(wl_po_fine_cnt[3]),\n .I2(wl_po_fine_cnt[9]),\n .I3(\\byte_r_reg[0] ),\n .I4(\\byte_r_reg[1] ),\n .I5(wl_po_fine_cnt[21]),\n .O(\\stg3_dec_val_reg[2] ));\n LUT4 #(\n .INIT(16'h4F7F)) \n \\stg2_tap_cnt[3]_i_4 \n (.I0(wl_po_fine_cnt[19]),\n .I1(\\byte_r_reg[0] ),\n .I2(\\byte_r_reg[1] ),\n .I3(wl_po_fine_cnt[15]),\n .O(\\stg2_tap_cnt[3]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h0511AF1105BBAFBB)) \n \\stg2_tap_cnt[4]_i_2 \n (.I0(\\byte_r_reg[0] ),\n .I1(wl_po_fine_cnt[4]),\n .I2(wl_po_fine_cnt[16]),\n .I3(\\byte_r_reg[1] ),\n .I4(wl_po_fine_cnt[22]),\n .I5(wl_po_fine_cnt[10]),\n .O(\\stg2_r_reg[4] ));\n LUT6 #(\n .INIT(64'h00550F33FF550F33)) \n \\stg2_tap_cnt[5]_i_5 \n (.I0(wl_po_fine_cnt[17]),\n .I1(wl_po_fine_cnt[5]),\n .I2(wl_po_fine_cnt[11]),\n .I3(\\byte_r_reg[0] ),\n .I4(\\byte_r_reg[1] ),\n .I5(wl_po_fine_cnt[23]),\n .O(\\stg2_r_reg[5] ));\n LUT6 #(\n .INIT(64'hFECEF2C23E0E3202)) \n \\stg2_target_r[0]_i_1 \n (.I0(wl_po_fine_cnt[0]),\n .I1(\\byte_r_reg[1] ),\n .I2(\\byte_r_reg[0] ),\n .I3(wl_po_fine_cnt[6]),\n .I4(wl_po_fine_cnt[12]),\n .I5(wl_po_fine_cnt[18]),\n .O(D[0]));\n LUT1 #(\n .INIT(2'h1)) \n \\stg2_target_r[4]_i_2 \n (.I0(\\stg2_r_reg[4] ),\n .O(\\oclk_calib.u_ddr_phy_oclkdelay_cal/wl_po_fine_cnt_sel_0__0 [4]));\n LUT1 #(\n .INIT(2'h1)) \n \\stg2_target_r[4]_i_3 \n (.I0(\\stg3_dec_val_reg[2] ),\n .O(\\oclk_calib.u_ddr_phy_oclkdelay_cal/wl_po_fine_cnt_sel_0__0 [3]));\n LUT2 #(\n .INIT(4'h9)) \n \\stg2_target_r[4]_i_4 \n (.I0(\\stg2_r_reg[4] ),\n .I1(O[2]),\n .O(\\stg2_target_r[4]_i_4_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\stg2_target_r[4]_i_5 \n (.I0(\\stg3_dec_val_reg[2] ),\n .I1(O[1]),\n .O(\\stg2_target_r[4]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'hBF8FBC8CB383B080)) \n \\stg2_target_r[8]_i_2 \n (.I0(wl_po_fine_cnt[23]),\n .I1(\\byte_r_reg[1] ),\n .I2(\\byte_r_reg[0] ),\n .I3(wl_po_fine_cnt[11]),\n .I4(wl_po_fine_cnt[5]),\n .I5(wl_po_fine_cnt[17]),\n .O(\\oclk_calib.u_ddr_phy_oclkdelay_cal/wl_po_fine_cnt_sel_0__0 [5]));\n LUT2 #(\n .INIT(4'h9)) \n \\stg2_target_r[8]_i_6 \n (.I0(\\stg2_r_reg[5] ),\n .I1(O[3]),\n .O(\\stg2_target_r[8]_i_6_n_0 ));\n CARRY4 \\stg2_target_r_reg[4]_i_1 \n (.CI(1'b0),\n .CO({\\stg2_target_r_reg[4]_i_1_n_0 ,\\stg2_target_r_reg[4]_i_1_n_1 ,\\stg2_target_r_reg[4]_i_1_n_2 ,\\stg2_target_r_reg[4]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({\\oclk_calib.u_ddr_phy_oclkdelay_cal/wl_po_fine_cnt_sel_0__0 [4:3],\\stg2_target_r_reg[4] }),\n .O({D[3:1],\\NLW_stg2_target_r_reg[4]_i_1_O_UNCONNECTED [0]}),\n .S({\\stg2_target_r[4]_i_4_n_0 ,\\stg2_target_r[4]_i_5_n_0 ,\\u_ocd_po_cntlr/stg2_target_r[4]_i_6_n_0 ,S}));\n CARRY4 \\stg2_target_r_reg[8]_i_1 \n (.CI(\\stg2_target_r_reg[4]_i_1_n_0 ),\n .CO({\\NLW_stg2_target_r_reg[8]_i_1_CO_UNCONNECTED [3],\\stg2_target_r_reg[8]_i_1_n_1 ,\\stg2_target_r_reg[8]_i_1_n_2 ,\\stg2_target_r_reg[8]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,\\oclk_calib.u_ddr_phy_oclkdelay_cal/wl_po_fine_cnt_sel_0__0 [5]}),\n .O(D[7:4]),\n .S({\\stg3_r_reg[5] ,\\stg2_target_r[8]_i_6_n_0 }));\n (* SOFT_HLUTNM = \"soft_lutpair319\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\stg3_dec_val[0]_i_1 \n (.I0(\\stg2_target_r_reg[4] [0]),\n .I1(Q[0]),\n .O(\\stg3_dec_val_reg[2]_0 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair319\" *) \n LUT4 #(\n .INIT(16'hE11E)) \n \\stg3_dec_val[1]_i_1 \n (.I0(\\stg2_target_r_reg[4] [0]),\n .I1(Q[0]),\n .I2(\\stg2_target_r_reg[4] [1]),\n .I3(Q[1]),\n .O(\\stg3_dec_val_reg[2]_0 [1]));\n LUT6 #(\n .INIT(64'h1117EEE8EEE81117)) \n \\stg3_dec_val[2]_i_1 \n (.I0(\\stg2_target_r_reg[4] [1]),\n .I1(Q[1]),\n .I2(\\stg2_target_r_reg[4] [0]),\n .I3(Q[0]),\n .I4(\\stg3_dec_val_reg[2] ),\n .I5(Q[2]),\n .O(\\stg3_dec_val_reg[2]_0 [2]));\n LUT2 #(\n .INIT(4'h6)) \n \\u_ocd_po_cntlr/stg2_target_r[4]_i_6 \n (.I0(\\stg2_target_r_reg[4] [1]),\n .I1(O[0]),\n .O(\\u_ocd_po_cntlr/stg2_target_r[4]_i_6_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\wait_cnt[0]_i_1 \n (.I0(wait_cnt_reg__0[0]),\n .O(wait_cnt0__0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair351\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\wait_cnt[1]_i_1 \n (.I0(wait_cnt_reg__0[0]),\n .I1(wait_cnt_reg__0[1]),\n .O(\\wait_cnt[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair351\" *) \n LUT3 #(\n .INIT(8'hA9)) \n \\wait_cnt[2]_i_1 \n (.I0(wait_cnt_reg__0[2]),\n .I1(wait_cnt_reg__0[1]),\n .I2(wait_cnt_reg__0[0]),\n .O(wait_cnt0__0[2]));\n LUT5 #(\n .INIT(32'hAAAAAAA8)) \n \\wait_cnt[3]_i_2 \n (.I0(phy_ctl_ready_r6_reg_n_0),\n .I1(wait_cnt_reg__0[3]),\n .I2(wait_cnt_reg__0[1]),\n .I3(wait_cnt_reg__0[0]),\n .I4(wait_cnt_reg__0[2]),\n .O(wait_cnt0));\n (* SOFT_HLUTNM = \"soft_lutpair316\" *) \n LUT4 #(\n .INIT(16'hAAA9)) \n \\wait_cnt[3]_i_3 \n (.I0(wait_cnt_reg__0[3]),\n .I1(wait_cnt_reg__0[2]),\n .I2(wait_cnt_reg__0[0]),\n .I3(wait_cnt_reg__0[1]),\n .O(wait_cnt0__0[3]));\n FDRE \\wait_cnt_reg[0] \n (.C(CLK),\n .CE(wait_cnt0),\n .D(wait_cnt0__0[0]),\n .Q(wait_cnt_reg__0[0]),\n .R(po_cnt_dec_reg_1));\n FDRE \\wait_cnt_reg[1] \n (.C(CLK),\n .CE(wait_cnt0),\n .D(\\wait_cnt[1]_i_1_n_0 ),\n .Q(wait_cnt_reg__0[1]),\n .R(po_cnt_dec_reg_1));\n FDRE \\wait_cnt_reg[2] \n (.C(CLK),\n .CE(wait_cnt0),\n .D(wait_cnt0__0[2]),\n .Q(wait_cnt_reg__0[2]),\n .R(po_cnt_dec_reg_1));\n FDSE \\wait_cnt_reg[3] \n (.C(CLK),\n .CE(wait_cnt0),\n .D(wait_cnt0__0[3]),\n .Q(wait_cnt_reg__0[3]),\n .S(po_cnt_dec_reg_1));\n LUT6 #(\n .INIT(64'hF0FFF000AACCAACC)) \n \\wl_corse_cnt[0][0][0]_i_1 \n (.I0(\\corse_cnt_reg_n_0_[2][0] ),\n .I1(\\corse_cnt_reg_n_0_[0][0] ),\n .I2(\\corse_cnt_reg_n_0_[3][0] ),\n .I3(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I4(\\corse_cnt_reg_n_0_[1][0] ),\n .I5(\\dqs_count_r_reg[0]_rep_n_0 ),\n .O(\\wl_corse_cnt[0][0][0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\wl_corse_cnt[0][0][1]_i_1 \n (.I0(\\corse_cnt_reg_n_0_[3][1] ),\n .I1(\\corse_cnt_reg_n_0_[1][1] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\corse_cnt_reg_n_0_[2][1] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\corse_cnt_reg_n_0_[0][1] ),\n .O(\\wl_corse_cnt[0][0][1]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h0100)) \n \\wl_corse_cnt[0][0][2]_i_1 \n (.I0(dqs_count_r[0]),\n .I1(dqs_count_r[1]),\n .I2(dqs_count_r[2]),\n .I3(\\wl_corse_cnt[0][0][2]_i_3_n_0 ),\n .O(wl_corse_cnt));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\wl_corse_cnt[0][0][2]_i_2 \n (.I0(\\corse_cnt_reg_n_0_[3][2] ),\n .I1(\\corse_cnt_reg_n_0_[1][2] ),\n .I2(\\dqs_count_r_reg[0]_rep_n_0 ),\n .I3(\\corse_cnt_reg_n_0_[2][2] ),\n .I4(\\dqs_count_r_reg[1]_rep_n_0 ),\n .I5(\\corse_cnt_reg_n_0_[0][2] ),\n .O(\\wl_corse_cnt[0][0][2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0200088000800000)) \n \\wl_corse_cnt[0][0][2]_i_3 \n (.I0(\\wl_corse_cnt[0][0][2]_i_4_n_0 ),\n .I1(out[1]),\n .I2(out[2]),\n .I3(out[4]),\n .I4(out[0]),\n .I5(out[3]),\n .O(\\wl_corse_cnt[0][0][2]_i_3_n_0 ));\n LUT2 #(\n .INIT(4'h1)) \n \\wl_corse_cnt[0][0][2]_i_4 \n (.I0(\\rank_cnt_r_reg[0]_0 ),\n .I1(\\rank_cnt_r_reg[0]_1 ),\n .O(\\wl_corse_cnt[0][0][2]_i_4_n_0 ));\n LUT4 #(\n .INIT(16'h0020)) \n \\wl_corse_cnt[0][1][2]_i_1 \n (.I0(\\wl_corse_cnt[0][0][2]_i_3_n_0 ),\n .I1(dqs_count_r[1]),\n .I2(dqs_count_r[0]),\n .I3(dqs_count_r[2]),\n .O(\\wl_corse_cnt[0][1][2]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h0020)) \n \\wl_corse_cnt[0][2][2]_i_1 \n (.I0(\\wl_corse_cnt[0][0][2]_i_3_n_0 ),\n .I1(dqs_count_r[0]),\n .I2(dqs_count_r[1]),\n .I3(dqs_count_r[2]),\n .O(\\wl_corse_cnt[0][2][2]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h0080)) \n \\wl_corse_cnt[0][3][2]_i_1 \n (.I0(\\wl_corse_cnt[0][0][2]_i_3_n_0 ),\n .I1(dqs_count_r[0]),\n .I2(dqs_count_r[1]),\n .I3(dqs_count_r[2]),\n .O(\\wl_corse_cnt[0][3][2]_i_1_n_0 ));\n FDRE \\wl_corse_cnt_reg[0][0][0] \n (.C(CLK),\n .CE(wl_corse_cnt),\n .D(\\wl_corse_cnt[0][0][0]_i_1_n_0 ),\n .Q(\\wl_corse_cnt_reg[0][0]__0 [0]),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\wl_corse_cnt_reg[0][0][1] \n (.C(CLK),\n .CE(wl_corse_cnt),\n .D(\\wl_corse_cnt[0][0][1]_i_1_n_0 ),\n .Q(\\wl_corse_cnt_reg[0][0]__0 [1]),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\wl_corse_cnt_reg[0][0][2] \n (.C(CLK),\n .CE(wl_corse_cnt),\n .D(\\wl_corse_cnt[0][0][2]_i_2_n_0 ),\n .Q(\\wl_corse_cnt_reg[0][0]__0 [2]),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\wl_corse_cnt_reg[0][1][0] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][1][2]_i_1_n_0 ),\n .D(\\wl_corse_cnt[0][0][0]_i_1_n_0 ),\n .Q(\\wl_corse_cnt_reg[0][1]__0 [0]),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\wl_corse_cnt_reg[0][1][1] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][1][2]_i_1_n_0 ),\n .D(\\wl_corse_cnt[0][0][1]_i_1_n_0 ),\n .Q(\\wl_corse_cnt_reg[0][1]__0 [1]),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\wl_corse_cnt_reg[0][1][2] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][1][2]_i_1_n_0 ),\n .D(\\wl_corse_cnt[0][0][2]_i_2_n_0 ),\n .Q(\\wl_corse_cnt_reg[0][1]__0 [2]),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\wl_corse_cnt_reg[0][2][0] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][2][2]_i_1_n_0 ),\n .D(\\wl_corse_cnt[0][0][0]_i_1_n_0 ),\n .Q(\\wl_corse_cnt_reg[0][2]__0 [0]),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\wl_corse_cnt_reg[0][2][1] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][2][2]_i_1_n_0 ),\n .D(\\wl_corse_cnt[0][0][1]_i_1_n_0 ),\n .Q(\\wl_corse_cnt_reg[0][2]__0 [1]),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\wl_corse_cnt_reg[0][2][2] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][2][2]_i_1_n_0 ),\n .D(\\wl_corse_cnt[0][0][2]_i_2_n_0 ),\n .Q(\\wl_corse_cnt_reg[0][2]__0 [2]),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\wl_corse_cnt_reg[0][3][0] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][3][2]_i_1_n_0 ),\n .D(\\wl_corse_cnt[0][0][0]_i_1_n_0 ),\n .Q(\\wl_corse_cnt_reg[0][3]__0 [0]),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\wl_corse_cnt_reg[0][3][1] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][3][2]_i_1_n_0 ),\n .D(\\wl_corse_cnt[0][0][1]_i_1_n_0 ),\n .Q(\\wl_corse_cnt_reg[0][3]__0 [1]),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\wl_corse_cnt_reg[0][3][2] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][3][2]_i_1_n_0 ),\n .D(\\wl_corse_cnt[0][0][2]_i_2_n_0 ),\n .Q(\\wl_corse_cnt_reg[0][3]__0 [2]),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\wl_dqs_tap_count_r_reg[0][0][0] \n (.C(CLK),\n .CE(wl_corse_cnt),\n .D(\\wl_tap_count_r_reg_n_0_[0] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][0][0] ),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\wl_dqs_tap_count_r_reg[0][0][1] \n (.C(CLK),\n .CE(wl_corse_cnt),\n .D(\\wl_tap_count_r_reg_n_0_[1] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][0][1] ),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\wl_dqs_tap_count_r_reg[0][0][2] \n (.C(CLK),\n .CE(wl_corse_cnt),\n .D(\\wl_tap_count_r_reg_n_0_[2] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][0][2] ),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\wl_dqs_tap_count_r_reg[0][0][3] \n (.C(CLK),\n .CE(wl_corse_cnt),\n .D(\\wl_tap_count_r_reg_n_0_[3] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][0][3] ),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\wl_dqs_tap_count_r_reg[0][0][4] \n (.C(CLK),\n .CE(wl_corse_cnt),\n .D(\\wl_tap_count_r_reg_n_0_[4] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][0][4] ),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\wl_dqs_tap_count_r_reg[0][0][5] \n (.C(CLK),\n .CE(wl_corse_cnt),\n .D(\\wl_tap_count_r_reg_n_0_[5] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][0][5] ),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\wl_dqs_tap_count_r_reg[0][1][0] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][1][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[0] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][1][0] ),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\wl_dqs_tap_count_r_reg[0][1][1] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][1][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[1] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][1][1] ),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\wl_dqs_tap_count_r_reg[0][1][2] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][1][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[2] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][1][2] ),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\wl_dqs_tap_count_r_reg[0][1][3] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][1][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[3] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][1][3] ),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\wl_dqs_tap_count_r_reg[0][1][4] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][1][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[4] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][1][4] ),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\wl_dqs_tap_count_r_reg[0][1][5] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][1][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[5] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][1][5] ),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\wl_dqs_tap_count_r_reg[0][2][0] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][2][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[0] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][2][0] ),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\wl_dqs_tap_count_r_reg[0][2][1] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][2][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[1] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][2][1] ),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\wl_dqs_tap_count_r_reg[0][2][2] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][2][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[2] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][2][2] ),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\wl_dqs_tap_count_r_reg[0][2][3] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][2][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[3] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][2][3] ),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\wl_dqs_tap_count_r_reg[0][2][4] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][2][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[4] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][2][4] ),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\wl_dqs_tap_count_r_reg[0][2][5] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][2][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[5] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][2][5] ),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\wl_dqs_tap_count_r_reg[0][3][0] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][3][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[0] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][3][0] ),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\wl_dqs_tap_count_r_reg[0][3][1] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][3][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[1] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][3][1] ),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\wl_dqs_tap_count_r_reg[0][3][2] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][3][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[2] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][3][2] ),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\wl_dqs_tap_count_r_reg[0][3][3] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][3][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[3] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][3][3] ),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\wl_dqs_tap_count_r_reg[0][3][4] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][3][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[4] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][3][4] ),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\wl_dqs_tap_count_r_reg[0][3][5] \n (.C(CLK),\n .CE(\\wl_corse_cnt[0][3][2]_i_1_n_0 ),\n .D(\\wl_tap_count_r_reg_n_0_[5] ),\n .Q(\\wl_dqs_tap_count_r_reg_n_0_[0][3][5] ),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE wl_edge_detect_valid_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_wl_state_r_reg[2]_0 ),\n .Q(\\FSM_sequential_wl_state_r_reg[0]_0 ),\n .R(rstdiv0_sync_r1_reg_rep__16));\n FDRE \\wl_po_fine_cnt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[0]__0 [0]),\n .Q(wl_po_fine_cnt[0]),\n .R(1'b0));\n FDRE \\wl_po_fine_cnt_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[1]__0 [4]),\n .Q(wl_po_fine_cnt[10]),\n .R(1'b0));\n FDRE \\wl_po_fine_cnt_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[1]__0 [5]),\n .Q(wl_po_fine_cnt[11]),\n .R(1'b0));\n FDRE \\wl_po_fine_cnt_reg[12] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[2]__0 [0]),\n .Q(wl_po_fine_cnt[12]),\n .R(1'b0));\n FDRE \\wl_po_fine_cnt_reg[13] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[2]__0 [1]),\n .Q(wl_po_fine_cnt[13]),\n .R(1'b0));\n FDRE \\wl_po_fine_cnt_reg[14] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[2]__0 [2]),\n .Q(wl_po_fine_cnt[14]),\n .R(1'b0));\n FDRE \\wl_po_fine_cnt_reg[15] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[2]__0 [3]),\n .Q(wl_po_fine_cnt[15]),\n .R(1'b0));\n FDRE \\wl_po_fine_cnt_reg[16] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[2]__0 [4]),\n .Q(wl_po_fine_cnt[16]),\n .R(1'b0));\n FDRE \\wl_po_fine_cnt_reg[17] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[2]__0 [5]),\n .Q(wl_po_fine_cnt[17]),\n .R(1'b0));\n FDRE \\wl_po_fine_cnt_reg[18] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[3]__0 [0]),\n .Q(wl_po_fine_cnt[18]),\n .R(1'b0));\n FDRE \\wl_po_fine_cnt_reg[19] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[3]__0 [1]),\n .Q(wl_po_fine_cnt[19]),\n .R(1'b0));\n FDRE \\wl_po_fine_cnt_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[0]__0 [1]),\n .Q(wl_po_fine_cnt[1]),\n .R(1'b0));\n FDRE \\wl_po_fine_cnt_reg[20] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[3]__0 [2]),\n .Q(wl_po_fine_cnt[20]),\n .R(1'b0));\n FDRE \\wl_po_fine_cnt_reg[21] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[3]__0 [3]),\n .Q(wl_po_fine_cnt[21]),\n .R(1'b0));\n FDRE \\wl_po_fine_cnt_reg[22] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[3]__0 [4]),\n .Q(wl_po_fine_cnt[22]),\n .R(1'b0));\n FDRE \\wl_po_fine_cnt_reg[23] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[3]__0 [5]),\n .Q(wl_po_fine_cnt[23]),\n .R(1'b0));\n FDRE \\wl_po_fine_cnt_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[0]__0 [2]),\n .Q(wl_po_fine_cnt[2]),\n .R(1'b0));\n FDRE \\wl_po_fine_cnt_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[0]__0 [3]),\n .Q(wl_po_fine_cnt[3]),\n .R(1'b0));\n FDRE \\wl_po_fine_cnt_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[0]__0 [4]),\n .Q(wl_po_fine_cnt[4]),\n .R(1'b0));\n FDRE \\wl_po_fine_cnt_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[0]__0 [5]),\n .Q(wl_po_fine_cnt[5]),\n .R(1'b0));\n FDRE \\wl_po_fine_cnt_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[1]__0 [0]),\n .Q(wl_po_fine_cnt[6]),\n .R(1'b0));\n FDRE \\wl_po_fine_cnt_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[1]__0 [1]),\n .Q(wl_po_fine_cnt[7]),\n .R(1'b0));\n FDRE \\wl_po_fine_cnt_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[1]__0 [2]),\n .Q(wl_po_fine_cnt[8]),\n .R(1'b0));\n FDRE \\wl_po_fine_cnt_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(\\smallest_reg[1]__0 [3]),\n .Q(wl_po_fine_cnt[9]),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h1B15D560)) \n \\wl_state_r1[0]_i_1 \n (.I0(out[1]),\n .I1(out[2]),\n .I2(out[4]),\n .I3(out[0]),\n .I4(out[3]),\n .O(\\wl_state_r1[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h293CEA22)) \n \\wl_state_r1[1]_i_1 \n (.I0(out[1]),\n .I1(out[4]),\n .I2(out[3]),\n .I3(out[0]),\n .I4(out[2]),\n .O(\\wl_state_r1[1]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h0505C478)) \n \\wl_state_r1[2]_i_1 \n (.I0(out[2]),\n .I1(out[1]),\n .I2(out[3]),\n .I3(out[0]),\n .I4(out[4]),\n .O(\\wl_state_r1[2]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h67425208)) \n \\wl_state_r1[3]_i_1 \n (.I0(out[4]),\n .I1(out[2]),\n .I2(out[1]),\n .I3(out[0]),\n .I4(out[3]),\n .O(\\wl_state_r1[3]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h55512B08)) \n \\wl_state_r1[4]_i_1 \n (.I0(out[3]),\n .I1(out[0]),\n .I2(out[1]),\n .I3(out[2]),\n .I4(out[4]),\n .O(\\wl_state_r1[4]_i_1_n_0 ));\n FDRE \\wl_state_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_state_r1[0]_i_1_n_0 ),\n .Q(\\wl_state_r1_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\wl_state_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_state_r1[1]_i_1_n_0 ),\n .Q(\\wl_state_r1_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\wl_state_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_state_r1[2]_i_1_n_0 ),\n .Q(\\wl_state_r1_reg_n_0_[2] ),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\wl_state_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_state_r1[3]_i_1_n_0 ),\n .Q(\\wl_state_r1_reg_n_0_[3] ),\n .R(rstdiv0_sync_r1_reg_rep__15));\n FDRE \\wl_state_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wl_state_r1[4]_i_1_n_0 ),\n .Q(\\wl_state_r1_reg_n_0_[4] ),\n .R(rstdiv0_sync_r1_reg_rep__15));\n LUT4 #(\n .INIT(16'hFF10)) \n \\wl_tap_count_r[0]_i_1 \n (.I0(out[3]),\n .I1(out[1]),\n .I2(\\wl_tap_count_r[0]_i_2_n_0 ),\n .I3(\\wl_tap_count_r[0]_i_3_n_0 ),\n .O(wl_tap_count_r[0]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\wl_tap_count_r[0]_i_2 \n (.I0(\\smallest_reg[3]__0 [0]),\n .I1(\\smallest_reg[1]__0 [0]),\n .I2(\\po_stg2_wrcal_cnt_reg[2] [0]),\n .I3(\\smallest_reg[2]__0 [0]),\n .I4(\\po_stg2_wrcal_cnt_reg[2] [1]),\n .I5(\\smallest_reg[0]__0 [0]),\n .O(\\wl_tap_count_r[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0003000005050000)) \n \\wl_tap_count_r[0]_i_3 \n (.I0(out[0]),\n .I1(out[4]),\n .I2(\\wl_tap_count_r_reg_n_0_[0] ),\n .I3(wr_level_done_r5),\n .I4(out[1]),\n .I5(out[3]),\n .O(\\wl_tap_count_r[0]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hCCCFCCEECCCCCCEE)) \n \\wl_tap_count_r[1]_i_1 \n (.I0(\\wl_tap_count_r[1]_i_2_n_0 ),\n .I1(\\wl_tap_count_r[1]_i_3_n_0 ),\n .I2(out[0]),\n .I3(out[3]),\n .I4(out[1]),\n .I5(\\wl_tap_count_r[1]_i_4_n_0 ),\n .O(wl_tap_count_r[1]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\wl_tap_count_r[1]_i_2 \n (.I0(\\smallest_reg[3]__0 [1]),\n .I1(\\smallest_reg[1]__0 [1]),\n .I2(\\po_stg2_wrcal_cnt_reg[2] [0]),\n .I3(\\smallest_reg[2]__0 [1]),\n .I4(\\po_stg2_wrcal_cnt_reg[2] [1]),\n .I5(\\smallest_reg[0]__0 [1]),\n .O(\\wl_tap_count_r[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000000880)) \n \\wl_tap_count_r[1]_i_3 \n (.I0(out[3]),\n .I1(out[1]),\n .I2(\\wl_tap_count_r_reg_n_0_[0] ),\n .I3(\\wl_tap_count_r_reg_n_0_[1] ),\n .I4(wr_level_done_r5),\n .I5(out[4]),\n .O(\\wl_tap_count_r[1]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair343\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\wl_tap_count_r[1]_i_4 \n (.I0(\\wl_tap_count_r_reg_n_0_[1] ),\n .I1(\\wl_tap_count_r_reg_n_0_[0] ),\n .O(\\wl_tap_count_r[1]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h02C232F202C202C2)) \n \\wl_tap_count_r[2]_i_1 \n (.I0(\\wl_tap_count_r[2]_i_2_n_0 ),\n .I1(out[3]),\n .I2(out[1]),\n .I3(\\wl_tap_count_r[2]_i_3_n_0 ),\n .I4(out[0]),\n .I5(\\wl_tap_count_r[2]_i_4_n_0 ),\n .O(wl_tap_count_r[2]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\wl_tap_count_r[2]_i_2 \n (.I0(\\smallest_reg[3]__0 [2]),\n .I1(\\smallest_reg[1]__0 [2]),\n .I2(\\po_stg2_wrcal_cnt_reg[2] [0]),\n .I3(\\smallest_reg[2]__0 [2]),\n .I4(\\po_stg2_wrcal_cnt_reg[2] [1]),\n .I5(\\smallest_reg[0]__0 [2]),\n .O(\\wl_tap_count_r[2]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFEEFEFEF)) \n \\wl_tap_count_r[2]_i_3 \n (.I0(out[4]),\n .I1(wr_level_done_r5),\n .I2(\\wl_tap_count_r_reg_n_0_[2] ),\n .I3(\\wl_tap_count_r_reg_n_0_[0] ),\n .I4(\\wl_tap_count_r_reg_n_0_[1] ),\n .O(\\wl_tap_count_r[2]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair343\" *) \n LUT3 #(\n .INIT(8'h6A)) \n \\wl_tap_count_r[2]_i_4 \n (.I0(\\wl_tap_count_r_reg_n_0_[2] ),\n .I1(\\wl_tap_count_r_reg_n_0_[0] ),\n .I2(\\wl_tap_count_r_reg_n_0_[1] ),\n .O(\\wl_tap_count_r[2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h02C202C202C232F2)) \n \\wl_tap_count_r[3]_i_1 \n (.I0(\\wl_tap_count_r[3]_i_2_n_0 ),\n .I1(out[3]),\n .I2(out[1]),\n .I3(\\wl_tap_count_r[3]_i_3_n_0 ),\n .I4(out[0]),\n .I5(\\wl_tap_count_r[3]_i_4_n_0 ),\n .O(wl_tap_count_r[3]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\wl_tap_count_r[3]_i_2 \n (.I0(\\smallest_reg[3]__0 [3]),\n .I1(\\smallest_reg[1]__0 [3]),\n .I2(\\po_stg2_wrcal_cnt_reg[2] [0]),\n .I3(\\smallest_reg[2]__0 [3]),\n .I4(\\po_stg2_wrcal_cnt_reg[2] [1]),\n .I5(\\smallest_reg[0]__0 [3]),\n .O(\\wl_tap_count_r[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFEBBBBBBB)) \n \\wl_tap_count_r[3]_i_3 \n (.I0(out[4]),\n .I1(\\wl_tap_count_r_reg_n_0_[3] ),\n .I2(\\wl_tap_count_r_reg_n_0_[2] ),\n .I3(\\wl_tap_count_r_reg_n_0_[1] ),\n .I4(\\wl_tap_count_r_reg_n_0_[0] ),\n .I5(wr_level_done_r5),\n .O(\\wl_tap_count_r[3]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair317\" *) \n LUT4 #(\n .INIT(16'h9555)) \n \\wl_tap_count_r[3]_i_4 \n (.I0(\\wl_tap_count_r_reg_n_0_[3] ),\n .I1(\\wl_tap_count_r_reg_n_0_[2] ),\n .I2(\\wl_tap_count_r_reg_n_0_[1] ),\n .I3(\\wl_tap_count_r_reg_n_0_[0] ),\n .O(\\wl_tap_count_r[3]_i_4_n_0 ));\n LUT4 #(\n .INIT(16'hFF10)) \n \\wl_tap_count_r[4]_i_1 \n (.I0(out[3]),\n .I1(out[1]),\n .I2(\\wl_tap_count_r[4]_i_2_n_0 ),\n .I3(\\wl_tap_count_r[4]_i_3_n_0 ),\n .O(wl_tap_count_r[4]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\wl_tap_count_r[4]_i_2 \n (.I0(\\smallest_reg[3]__0 [4]),\n .I1(\\smallest_reg[1]__0 [4]),\n .I2(\\po_stg2_wrcal_cnt_reg[2] [0]),\n .I3(\\smallest_reg[2]__0 [4]),\n .I4(\\po_stg2_wrcal_cnt_reg[2] [1]),\n .I5(\\smallest_reg[0]__0 [4]),\n .O(\\wl_tap_count_r[4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0003000005050000)) \n \\wl_tap_count_r[4]_i_3 \n (.I0(out[0]),\n .I1(out[4]),\n .I2(\\wl_tap_count_r[4]_i_4_n_0 ),\n .I3(wr_level_done_r5),\n .I4(out[1]),\n .I5(out[3]),\n .O(\\wl_tap_count_r[4]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair317\" *) \n LUT5 #(\n .INIT(32'h95555555)) \n \\wl_tap_count_r[4]_i_4 \n (.I0(\\wl_tap_count_r_reg_n_0_[4] ),\n .I1(\\wl_tap_count_r_reg_n_0_[0] ),\n .I2(\\wl_tap_count_r_reg_n_0_[1] ),\n .I3(\\wl_tap_count_r_reg_n_0_[2] ),\n .I4(\\wl_tap_count_r_reg_n_0_[3] ),\n .O(\\wl_tap_count_r[4]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h4400000044551110)) \n \\wl_tap_count_r[5]_i_1 \n (.I0(out[2]),\n .I1(out[0]),\n .I2(done_dqs_dec239_out),\n .I3(out[3]),\n .I4(out[1]),\n .I5(out[4]),\n .O(\\wl_tap_count_r[5]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'hFF10)) \n \\wl_tap_count_r[5]_i_2 \n (.I0(out[3]),\n .I1(out[1]),\n .I2(\\wl_tap_count_r[5]_i_4_n_0 ),\n .I3(\\wl_tap_count_r[5]_i_5_n_0 ),\n .O(wl_tap_count_r[5]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\wl_tap_count_r[5]_i_4 \n (.I0(\\smallest_reg[3]__0 [5]),\n .I1(\\smallest_reg[1]__0 [5]),\n .I2(\\po_stg2_wrcal_cnt_reg[2] [0]),\n .I3(\\smallest_reg[2]__0 [5]),\n .I4(\\po_stg2_wrcal_cnt_reg[2] [1]),\n .I5(\\smallest_reg[0]__0 [5]),\n .O(\\wl_tap_count_r[5]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'h0300000055000000)) \n \\wl_tap_count_r[5]_i_5 \n (.I0(out[0]),\n .I1(out[4]),\n .I2(wr_level_done_r5),\n .I3(\\wl_tap_count_r[5]_i_6_n_0 ),\n .I4(out[1]),\n .I5(out[3]),\n .O(\\wl_tap_count_r[5]_i_5_n_0 ));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n \\wl_tap_count_r[5]_i_6 \n (.I0(\\wl_tap_count_r_reg_n_0_[5] ),\n .I1(\\wl_tap_count_r_reg_n_0_[4] ),\n .I2(\\wl_tap_count_r_reg_n_0_[3] ),\n .I3(\\wl_tap_count_r_reg_n_0_[2] ),\n .I4(\\wl_tap_count_r_reg_n_0_[1] ),\n .I5(\\wl_tap_count_r_reg_n_0_[0] ),\n .O(\\wl_tap_count_r[5]_i_6_n_0 ));\n FDRE \\wl_tap_count_r_reg[0] \n (.C(CLK),\n .CE(\\wl_tap_count_r[5]_i_1_n_0 ),\n .D(wl_tap_count_r[0]),\n .Q(\\wl_tap_count_r_reg_n_0_[0] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\wl_tap_count_r_reg[1] \n (.C(CLK),\n .CE(\\wl_tap_count_r[5]_i_1_n_0 ),\n .D(wl_tap_count_r[1]),\n .Q(\\wl_tap_count_r_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\wl_tap_count_r_reg[2] \n (.C(CLK),\n .CE(\\wl_tap_count_r[5]_i_1_n_0 ),\n .D(wl_tap_count_r[2]),\n .Q(\\wl_tap_count_r_reg_n_0_[2] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\wl_tap_count_r_reg[3] \n (.C(CLK),\n .CE(\\wl_tap_count_r[5]_i_1_n_0 ),\n .D(wl_tap_count_r[3]),\n .Q(\\wl_tap_count_r_reg_n_0_[3] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\wl_tap_count_r_reg[4] \n (.C(CLK),\n .CE(\\wl_tap_count_r[5]_i_1_n_0 ),\n .D(wl_tap_count_r[4]),\n .Q(\\wl_tap_count_r_reg_n_0_[4] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE \\wl_tap_count_r_reg[5] \n (.C(CLK),\n .CE(\\wl_tap_count_r[5]_i_1_n_0 ),\n .D(wl_tap_count_r[5]),\n .Q(\\wl_tap_count_r_reg_n_0_[5] ),\n .R(rstdiv0_sync_r1_reg_rep__17));\n FDRE wr_level_done_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wr_level_done_r1_reg_0),\n .Q(wr_level_done_r1),\n .R(1'b0));\n FDRE wr_level_done_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wr_level_done_r1),\n .Q(wr_level_done_r2),\n .R(1'b0));\n FDRE wr_level_done_r3_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wr_level_done_r2),\n .Q(wr_level_done_r3),\n .R(1'b0));\n FDRE wr_level_done_r4_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wr_level_done_r3),\n .Q(wr_level_done_r4),\n .R(1'b0));\n FDRE wr_level_done_r5_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wr_level_done_r4),\n .Q(wr_level_done_r5),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hF5FFFFFFFFFFFFBB)) \n wr_level_done_r_i_2\n (.I0(out[4]),\n .I1(wr_level_done0),\n .I2(p_0_in),\n .I3(out[3]),\n .I4(out[1]),\n .I5(out[0]),\n .O(wr_level_done_r_reg_0));\n FDRE wr_level_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_wl_state_r_reg[0]_1 ),\n .Q(wr_level_done_r1_reg_0),\n .R(rstdiv0_sync_r1_reg_rep__16));\n (* syn_maxfan = \"2\" *) \n FDRE wr_level_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\single_rank.done_dqs_dec_reg_0 ),\n .Q(wrlvl_done_r_reg),\n .R(1'b0));\n FDRE wr_level_start_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wr_lvl_start_reg),\n .Q(wr_level_start_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000AEAA00AA)) \n wrlvl_byte_done_i_1\n (.I0(wrlvl_byte_done),\n .I1(wr_level_done_r3),\n .I2(wr_level_done_r4),\n .I3(wrlvl_byte_redo),\n .I4(wrlvl_byte_redo_r),\n .I5(rstdiv0_sync_r1_reg_rep__23),\n .O(wrlvl_byte_done_i_1_n_0));\n FDRE wrlvl_byte_done_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrlvl_byte_done_i_1_n_0),\n .Q(wrlvl_byte_done),\n .R(1'b0));\n FDRE wrlvl_byte_redo_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrlvl_byte_redo),\n .Q(wrlvl_byte_redo_r),\n .R(1'b0));\n FDRE wrlvl_final_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wrlvl_final_mux),\n .Q(wrlvl_final_r),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0000400000050005)) \n wrlvl_rank_done_r_i_2\n (.I0(out[2]),\n .I1(out[0]),\n .I2(out[1]),\n .I3(out[3]),\n .I4(p_0_in),\n .I5(out[4]),\n .O(wrlvl_rank_done_r_reg_0));\n FDRE wrlvl_rank_done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\FSM_sequential_wl_state_r_reg[2]_1 ),\n .Q(wrlvl_rank_done),\n .R(rstdiv0_sync_r1_reg_rep__15));\n LUT4 #(\n .INIT(16'h0F40)) \n \\wrlvl_redo_corse_inc[0]_i_1 \n (.I0(out[4]),\n .I1(out[2]),\n .I2(\\wrlvl_redo_corse_inc[2]_i_4_n_0 ),\n .I3(wrlvl_redo_corse_inc__0[0]),\n .O(\\wrlvl_redo_corse_inc[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'h45FF1500)) \n \\wrlvl_redo_corse_inc[1]_i_1 \n (.I0(out[4]),\n .I1(wrlvl_redo_corse_inc__0[0]),\n .I2(out[2]),\n .I3(\\wrlvl_redo_corse_inc[2]_i_4_n_0 ),\n .I4(wrlvl_redo_corse_inc__0[1]),\n .O(\\wrlvl_redo_corse_inc[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0074FFFF00B80000)) \n \\wrlvl_redo_corse_inc[2]_i_1 \n (.I0(\\wrlvl_redo_corse_inc[2]_i_2_n_0 ),\n .I1(out[2]),\n .I2(\\wrlvl_redo_corse_inc[2]_i_3_n_0 ),\n .I3(out[4]),\n .I4(\\wrlvl_redo_corse_inc[2]_i_4_n_0 ),\n .I5(wrlvl_redo_corse_inc__0[2]),\n .O(\\wrlvl_redo_corse_inc[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair336\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\wrlvl_redo_corse_inc[2]_i_2 \n (.I0(wrlvl_redo_corse_inc__0[0]),\n .I1(wrlvl_redo_corse_inc__0[1]),\n .O(\\wrlvl_redo_corse_inc[2]_i_2_n_0 ));\n LUT3 #(\n .INIT(8'hD5)) \n \\wrlvl_redo_corse_inc[2]_i_3 \n (.I0(early1_data_reg_0),\n .I1(\\wrlvl_redo_corse_inc_reg[2]_0 [0]),\n .I2(\\wrlvl_redo_corse_inc_reg[2]_0 [1]),\n .O(\\wrlvl_redo_corse_inc[2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h00000020A0A00020)) \n \\wrlvl_redo_corse_inc[2]_i_4 \n (.I0(\\wrlvl_redo_corse_inc[2]_i_7_n_0 ),\n .I1(early1_data_reg),\n .I2(wrlvl_byte_redo),\n .I3(wrlvl_byte_redo_r),\n .I4(out[2]),\n .I5(\\FSM_sequential_wl_state_r[2]_i_6_n_0 ),\n .O(\\wrlvl_redo_corse_inc[2]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\wrlvl_redo_corse_inc[2]_i_5 \n (.I0(\\final_coarse_tap_reg_n_0_[3][1] ),\n .I1(\\final_coarse_tap_reg_n_0_[1][1] ),\n .I2(\\po_stg2_wrcal_cnt_reg[2] [0]),\n .I3(\\final_coarse_tap_reg_n_0_[2][1] ),\n .I4(\\po_stg2_wrcal_cnt_reg[2] [1]),\n .I5(\\final_coarse_tap_reg_n_0_[0][1] ),\n .O(\\wrlvl_redo_corse_inc_reg[2]_0 [0]));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\wrlvl_redo_corse_inc[2]_i_6 \n (.I0(\\final_coarse_tap_reg_n_0_[3][2] ),\n .I1(\\final_coarse_tap_reg_n_0_[1][2] ),\n .I2(\\po_stg2_wrcal_cnt_reg[2] [0]),\n .I3(\\final_coarse_tap_reg_n_0_[2][2] ),\n .I4(\\po_stg2_wrcal_cnt_reg[2] [1]),\n .I5(\\final_coarse_tap_reg_n_0_[0][2] ),\n .O(\\wrlvl_redo_corse_inc_reg[2]_0 [1]));\n LUT4 #(\n .INIT(16'h0001)) \n \\wrlvl_redo_corse_inc[2]_i_7 \n (.I0(out[4]),\n .I1(out[3]),\n .I2(out[0]),\n .I3(out[1]),\n .O(\\wrlvl_redo_corse_inc[2]_i_7_n_0 ));\n FDRE \\wrlvl_redo_corse_inc_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wrlvl_redo_corse_inc[0]_i_1_n_0 ),\n .Q(wrlvl_redo_corse_inc__0[0]),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\wrlvl_redo_corse_inc_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wrlvl_redo_corse_inc[1]_i_1_n_0 ),\n .Q(wrlvl_redo_corse_inc__0[1]),\n .R(rstdiv0_sync_r1_reg_rep__18));\n FDRE \\wrlvl_redo_corse_inc_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wrlvl_redo_corse_inc[2]_i_1_n_0 ),\n .Q(wrlvl_redo_corse_inc__0[2]),\n .R(rstdiv0_sync_r1_reg_rep__18));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_ddr_prbs_gen\n (\\rd_addr_reg[0]_0 ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[120] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[124] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[249] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[253] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[190] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[251] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[255] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[24] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[27] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[28] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[31] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[89] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[93] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[154] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[158] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[90] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[94] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[222] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[218] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[156] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[152] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[25] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[29] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[30] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[26] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[95] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[121] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[123] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[125] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[127] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[184] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[188] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[216] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[219] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[220] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[223] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[185] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[189] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[157] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[153] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[58] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[59] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[62] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[63] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[248] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[252] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[217] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[159] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[155] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[92] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[88] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[61] ,\n Q,\n \\gen_mux_rd[0].compare_data_rise0_r1_reg[0] ,\n \\gen_mux_rd[1].compare_data_rise0_r1_reg[1] ,\n \\gen_mux_rd[2].compare_data_rise0_r1_reg[2] ,\n \\gen_mux_rd[3].compare_data_rise0_r1_reg[3] ,\n \\gen_mux_rd[4].compare_data_rise0_r1_reg[4] ,\n \\gen_mux_rd[5].compare_data_rise0_r1_reg[5] ,\n \\gen_mux_rd[6].compare_data_rise0_r1_reg[6] ,\n \\gen_mux_rd[7].compare_data_rise0_r1_reg[7] ,\n \\gen_mux_rd[0].compare_data_fall0_r1_reg[0] ,\n \\gen_mux_rd[1].compare_data_fall0_r1_reg[1] ,\n \\gen_mux_rd[2].compare_data_fall0_r1_reg[2] ,\n \\gen_mux_rd[3].compare_data_fall0_r1_reg[3] ,\n \\gen_mux_rd[4].compare_data_fall0_r1_reg[4] ,\n \\gen_mux_rd[5].compare_data_fall0_r1_reg[5] ,\n \\gen_mux_rd[6].compare_data_fall0_r1_reg[6] ,\n \\gen_mux_rd[7].compare_data_fall0_r1_reg[7] ,\n \\gen_mux_rd[0].compare_data_rise1_r1_reg[0] ,\n \\gen_mux_rd[1].compare_data_rise1_r1_reg[1] ,\n \\gen_mux_rd[2].compare_data_rise1_r1_reg[2] ,\n \\gen_mux_rd[3].compare_data_rise1_r1_reg[3] ,\n \\gen_mux_rd[4].compare_data_rise1_r1_reg[4] ,\n \\gen_mux_rd[5].compare_data_rise1_r1_reg[5] ,\n \\gen_mux_rd[6].compare_data_rise1_r1_reg[6] ,\n \\gen_mux_rd[7].compare_data_rise1_r1_reg[7] ,\n \\gen_mux_rd[0].compare_data_fall1_r1_reg[0] ,\n \\gen_mux_rd[1].compare_data_fall1_r1_reg[1] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[122] ,\n \\gen_mux_rd[3].compare_data_fall1_r1_reg[3] ,\n \\gen_mux_rd[4].compare_data_fall1_r1_reg[4] ,\n \\gen_mux_rd[5].compare_data_fall1_r1_reg[5] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[126] ,\n \\gen_mux_rd[7].compare_data_fall1_r1_reg[7] ,\n \\gen_mux_rd[0].compare_data_rise2_r1_reg[0] ,\n \\gen_mux_rd[1].compare_data_rise2_r1_reg[1] ,\n \\gen_mux_rd[2].compare_data_rise2_r1_reg[2] ,\n \\gen_mux_rd[3].compare_data_rise2_r1_reg[3] ,\n \\gen_mux_rd[4].compare_data_rise2_r1_reg[4] ,\n \\gen_mux_rd[5].compare_data_rise2_r1_reg[5] ,\n \\gen_mux_rd[6].compare_data_rise2_r1_reg[6] ,\n \\gen_mux_rd[7].compare_data_rise2_r1_reg[7] ,\n \\gen_mux_rd[0].compare_data_fall2_r1_reg[0] ,\n \\gen_mux_rd[1].compare_data_fall2_r1_reg[1] ,\n \\gen_mux_rd[2].compare_data_fall2_r1_reg[2] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187] ,\n \\gen_mux_rd[4].compare_data_fall2_r1_reg[4] ,\n \\gen_mux_rd[5].compare_data_fall2_r1_reg[5] ,\n \\gen_mux_rd[6].compare_data_fall2_r1_reg[6] ,\n \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] ,\n \\gen_mux_rd[0].compare_data_rise3_r1_reg[0] ,\n \\gen_mux_rd[1].compare_data_rise3_r1_reg[1] ,\n \\gen_mux_rd[2].compare_data_rise3_r1_reg[2] ,\n \\gen_mux_rd[3].compare_data_rise3_r1_reg[3] ,\n \\gen_mux_rd[4].compare_data_rise3_r1_reg[4] ,\n \\gen_mux_rd[5].compare_data_rise3_r1_reg[5] ,\n \\gen_mux_rd[6].compare_data_rise3_r1_reg[6] ,\n \\gen_mux_rd[7].compare_data_rise3_r1_reg[7] ,\n \\gen_mux_rd[0].compare_data_fall3_r1_reg[0] ,\n \\gen_mux_rd[1].compare_data_fall3_r1_reg[1] ,\n \\gen_mux_rd[2].compare_data_fall3_r1_reg[2] ,\n \\gen_mux_rd[3].compare_data_fall3_r1_reg[3] ,\n \\gen_mux_rd[4].compare_data_fall3_r1_reg[4] ,\n \\gen_mux_rd[5].compare_data_fall3_r1_reg[5] ,\n \\gen_mux_rd[6].compare_data_fall3_r1_reg[6] ,\n \\gen_mux_rd[7].compare_data_fall3_r1_reg[7] ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,\n CLK,\n rdlvl_stg1_done_int_reg,\n wrcal_done_reg,\n first_rdlvl_pat_r,\n oclkdelay_calib_done_r_reg,\n \\rd_addr_reg[3]_0 ,\n rstdiv0_sync_r1_reg_rep__19,\n D,\n SR,\n E);\n output \\rd_addr_reg[0]_0 ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[120] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[124] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[249] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[253] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[190] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[251] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[255] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[24] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[27] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[28] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[31] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[89] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[93] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[154] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[158] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[90] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[94] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[222] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[218] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[156] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[152] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[25] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[29] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[30] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[26] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[95] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[121] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[123] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[125] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[127] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[184] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[188] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[216] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[219] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[220] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[223] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[185] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[189] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[157] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[153] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[58] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[59] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[62] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[63] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[248] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[252] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[217] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[159] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[155] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[92] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[88] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[61] ;\n output [0:0]Q;\n output \\gen_mux_rd[0].compare_data_rise0_r1_reg[0] ;\n output \\gen_mux_rd[1].compare_data_rise0_r1_reg[1] ;\n output \\gen_mux_rd[2].compare_data_rise0_r1_reg[2] ;\n output \\gen_mux_rd[3].compare_data_rise0_r1_reg[3] ;\n output \\gen_mux_rd[4].compare_data_rise0_r1_reg[4] ;\n output \\gen_mux_rd[5].compare_data_rise0_r1_reg[5] ;\n output \\gen_mux_rd[6].compare_data_rise0_r1_reg[6] ;\n output \\gen_mux_rd[7].compare_data_rise0_r1_reg[7] ;\n output \\gen_mux_rd[0].compare_data_fall0_r1_reg[0] ;\n output \\gen_mux_rd[1].compare_data_fall0_r1_reg[1] ;\n output \\gen_mux_rd[2].compare_data_fall0_r1_reg[2] ;\n output \\gen_mux_rd[3].compare_data_fall0_r1_reg[3] ;\n output \\gen_mux_rd[4].compare_data_fall0_r1_reg[4] ;\n output \\gen_mux_rd[5].compare_data_fall0_r1_reg[5] ;\n output \\gen_mux_rd[6].compare_data_fall0_r1_reg[6] ;\n output \\gen_mux_rd[7].compare_data_fall0_r1_reg[7] ;\n output \\gen_mux_rd[0].compare_data_rise1_r1_reg[0] ;\n output \\gen_mux_rd[1].compare_data_rise1_r1_reg[1] ;\n output \\gen_mux_rd[2].compare_data_rise1_r1_reg[2] ;\n output \\gen_mux_rd[3].compare_data_rise1_r1_reg[3] ;\n output \\gen_mux_rd[4].compare_data_rise1_r1_reg[4] ;\n output \\gen_mux_rd[5].compare_data_rise1_r1_reg[5] ;\n output \\gen_mux_rd[6].compare_data_rise1_r1_reg[6] ;\n output \\gen_mux_rd[7].compare_data_rise1_r1_reg[7] ;\n output \\gen_mux_rd[0].compare_data_fall1_r1_reg[0] ;\n output \\gen_mux_rd[1].compare_data_fall1_r1_reg[1] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[122] ;\n output \\gen_mux_rd[3].compare_data_fall1_r1_reg[3] ;\n output \\gen_mux_rd[4].compare_data_fall1_r1_reg[4] ;\n output \\gen_mux_rd[5].compare_data_fall1_r1_reg[5] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[126] ;\n output \\gen_mux_rd[7].compare_data_fall1_r1_reg[7] ;\n output \\gen_mux_rd[0].compare_data_rise2_r1_reg[0] ;\n output \\gen_mux_rd[1].compare_data_rise2_r1_reg[1] ;\n output \\gen_mux_rd[2].compare_data_rise2_r1_reg[2] ;\n output \\gen_mux_rd[3].compare_data_rise2_r1_reg[3] ;\n output \\gen_mux_rd[4].compare_data_rise2_r1_reg[4] ;\n output \\gen_mux_rd[5].compare_data_rise2_r1_reg[5] ;\n output \\gen_mux_rd[6].compare_data_rise2_r1_reg[6] ;\n output \\gen_mux_rd[7].compare_data_rise2_r1_reg[7] ;\n output \\gen_mux_rd[0].compare_data_fall2_r1_reg[0] ;\n output \\gen_mux_rd[1].compare_data_fall2_r1_reg[1] ;\n output \\gen_mux_rd[2].compare_data_fall2_r1_reg[2] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187] ;\n output \\gen_mux_rd[4].compare_data_fall2_r1_reg[4] ;\n output \\gen_mux_rd[5].compare_data_fall2_r1_reg[5] ;\n output \\gen_mux_rd[6].compare_data_fall2_r1_reg[6] ;\n output \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] ;\n output \\gen_mux_rd[0].compare_data_rise3_r1_reg[0] ;\n output \\gen_mux_rd[1].compare_data_rise3_r1_reg[1] ;\n output \\gen_mux_rd[2].compare_data_rise3_r1_reg[2] ;\n output \\gen_mux_rd[3].compare_data_rise3_r1_reg[3] ;\n output \\gen_mux_rd[4].compare_data_rise3_r1_reg[4] ;\n output \\gen_mux_rd[5].compare_data_rise3_r1_reg[5] ;\n output \\gen_mux_rd[6].compare_data_rise3_r1_reg[6] ;\n output \\gen_mux_rd[7].compare_data_rise3_r1_reg[7] ;\n output \\gen_mux_rd[0].compare_data_fall3_r1_reg[0] ;\n output \\gen_mux_rd[1].compare_data_fall3_r1_reg[1] ;\n output \\gen_mux_rd[2].compare_data_fall3_r1_reg[2] ;\n output \\gen_mux_rd[3].compare_data_fall3_r1_reg[3] ;\n output \\gen_mux_rd[4].compare_data_fall3_r1_reg[4] ;\n output \\gen_mux_rd[5].compare_data_fall3_r1_reg[5] ;\n output \\gen_mux_rd[6].compare_data_fall3_r1_reg[6] ;\n output \\gen_mux_rd[7].compare_data_fall3_r1_reg[7] ;\n input \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n input CLK;\n input rdlvl_stg1_done_int_reg;\n input wrcal_done_reg;\n input first_rdlvl_pat_r;\n input oclkdelay_calib_done_r_reg;\n input \\rd_addr_reg[3]_0 ;\n input [0:0]rstdiv0_sync_r1_reg_rep__19;\n input [7:0]D;\n input [0:0]SR;\n input [0:0]E;\n\n wire CLK;\n wire [7:0]D;\n wire [0:0]E;\n wire [0:0]Q;\n wire [0:0]SR;\n wire \\dout_o[0]_i_1_n_0 ;\n wire \\dout_o[0]_i_2_n_0 ;\n wire \\dout_o[0]_i_3_n_0 ;\n wire \\dout_o[0]_i_4_n_0 ;\n wire \\dout_o[10]_i_1_n_0 ;\n wire \\dout_o[10]_i_2_n_0 ;\n wire \\dout_o[10]_i_3_n_0 ;\n wire \\dout_o[11]_i_1_n_0 ;\n wire \\dout_o[11]_i_2_n_0 ;\n wire \\dout_o[11]_i_3_n_0 ;\n wire \\dout_o[11]_i_4_n_0 ;\n wire \\dout_o[12]_i_1_n_0 ;\n wire \\dout_o[12]_i_2_n_0 ;\n wire \\dout_o[12]_i_3_n_0 ;\n wire \\dout_o[12]_i_4_n_0 ;\n wire \\dout_o[13]_i_1_n_0 ;\n wire \\dout_o[13]_i_2_n_0 ;\n wire \\dout_o[13]_i_3_n_0 ;\n wire \\dout_o[13]_i_4_n_0 ;\n wire \\dout_o[14]_i_1_n_0 ;\n wire \\dout_o[14]_i_2_n_0 ;\n wire \\dout_o[14]_i_3_n_0 ;\n wire \\dout_o[14]_i_4_n_0 ;\n wire \\dout_o[15]_i_1_n_0 ;\n wire \\dout_o[15]_i_2_n_0 ;\n wire \\dout_o[15]_i_3_n_0 ;\n wire \\dout_o[15]_i_4_n_0 ;\n wire \\dout_o[1]_i_1_n_0 ;\n wire \\dout_o[1]_i_2_n_0 ;\n wire \\dout_o[1]_i_3_n_0 ;\n wire \\dout_o[1]_i_4_n_0 ;\n wire \\dout_o[2]_i_1_n_0 ;\n wire \\dout_o[2]_i_2_n_0 ;\n wire \\dout_o[2]_i_3_n_0 ;\n wire \\dout_o[2]_i_4_n_0 ;\n wire \\dout_o[3]_i_1_n_0 ;\n wire \\dout_o[3]_i_2_n_0 ;\n wire \\dout_o[3]_i_3_n_0 ;\n wire \\dout_o[3]_i_4_n_0 ;\n wire \\dout_o[4]_i_1_n_0 ;\n wire \\dout_o[4]_i_2_n_0 ;\n wire \\dout_o[4]_i_3_n_0 ;\n wire \\dout_o[4]_i_4_n_0 ;\n wire \\dout_o[5]_i_1_n_0 ;\n wire \\dout_o[5]_i_2_n_0 ;\n wire \\dout_o[5]_i_3_n_0 ;\n wire \\dout_o[5]_i_4_n_0 ;\n wire \\dout_o[6]_i_1_n_0 ;\n wire \\dout_o[6]_i_2_n_0 ;\n wire \\dout_o[6]_i_3_n_0 ;\n wire \\dout_o[6]_i_4_n_0 ;\n wire \\dout_o[7]_i_1_n_0 ;\n wire \\dout_o[7]_i_2_n_0 ;\n wire \\dout_o[7]_i_3_n_0 ;\n wire \\dout_o[7]_i_4_n_0 ;\n wire \\dout_o[8]_i_1_n_0 ;\n wire \\dout_o[8]_i_2_n_0 ;\n wire \\dout_o[8]_i_3_n_0 ;\n wire \\dout_o[8]_i_4_n_0 ;\n wire \\dout_o[9]_i_1_n_0 ;\n wire \\dout_o[9]_i_2_n_0 ;\n wire \\dout_o[9]_i_3_n_0 ;\n wire \\dout_o[9]_i_4_n_0 ;\n wire \\dout_o_reg_n_0_[0] ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n wire first_rdlvl_pat_r;\n wire \\gen_mux_rd[0].compare_data_fall0_r1_reg[0] ;\n wire \\gen_mux_rd[0].compare_data_fall1_r1_reg[0] ;\n wire \\gen_mux_rd[0].compare_data_fall2_r1_reg[0] ;\n wire \\gen_mux_rd[0].compare_data_fall3_r1_reg[0] ;\n wire \\gen_mux_rd[0].compare_data_rise0_r1_reg[0] ;\n wire \\gen_mux_rd[0].compare_data_rise1_r1_reg[0] ;\n wire \\gen_mux_rd[0].compare_data_rise2_r1_reg[0] ;\n wire \\gen_mux_rd[0].compare_data_rise3_r1_reg[0] ;\n wire \\gen_mux_rd[1].compare_data_fall0_r1_reg[1] ;\n wire \\gen_mux_rd[1].compare_data_fall1_r1_reg[1] ;\n wire \\gen_mux_rd[1].compare_data_fall2_r1_reg[1] ;\n wire \\gen_mux_rd[1].compare_data_fall3_r1_reg[1] ;\n wire \\gen_mux_rd[1].compare_data_rise0_r1_reg[1] ;\n wire \\gen_mux_rd[1].compare_data_rise1_r1_reg[1] ;\n wire \\gen_mux_rd[1].compare_data_rise2_r1_reg[1] ;\n wire \\gen_mux_rd[1].compare_data_rise3_r1_reg[1] ;\n wire \\gen_mux_rd[2].compare_data_fall0_r1_reg[2] ;\n wire \\gen_mux_rd[2].compare_data_fall2_r1_reg[2] ;\n wire \\gen_mux_rd[2].compare_data_fall3_r1_reg[2] ;\n wire \\gen_mux_rd[2].compare_data_rise0_r1_reg[2] ;\n wire \\gen_mux_rd[2].compare_data_rise1_r1_reg[2] ;\n wire \\gen_mux_rd[2].compare_data_rise2_r1_reg[2] ;\n wire \\gen_mux_rd[2].compare_data_rise3_r1_reg[2] ;\n wire \\gen_mux_rd[3].compare_data_fall0_r1_reg[3] ;\n wire \\gen_mux_rd[3].compare_data_fall1_r1_reg[3] ;\n wire \\gen_mux_rd[3].compare_data_fall3_r1_reg[3] ;\n wire \\gen_mux_rd[3].compare_data_rise0_r1_reg[3] ;\n wire \\gen_mux_rd[3].compare_data_rise1_r1_reg[3] ;\n wire \\gen_mux_rd[3].compare_data_rise2_r1_reg[3] ;\n wire \\gen_mux_rd[3].compare_data_rise3_r1_reg[3] ;\n wire \\gen_mux_rd[4].compare_data_fall0_r1_reg[4] ;\n wire \\gen_mux_rd[4].compare_data_fall1_r1_reg[4] ;\n wire \\gen_mux_rd[4].compare_data_fall2_r1_reg[4] ;\n wire \\gen_mux_rd[4].compare_data_fall3_r1_reg[4] ;\n wire \\gen_mux_rd[4].compare_data_rise0_r1_reg[4] ;\n wire \\gen_mux_rd[4].compare_data_rise1_r1_reg[4] ;\n wire \\gen_mux_rd[4].compare_data_rise2_r1_reg[4] ;\n wire \\gen_mux_rd[4].compare_data_rise3_r1_reg[4] ;\n wire \\gen_mux_rd[5].compare_data_fall0_r1_reg[5] ;\n wire \\gen_mux_rd[5].compare_data_fall1_r1_reg[5] ;\n wire \\gen_mux_rd[5].compare_data_fall2_r1_reg[5] ;\n wire \\gen_mux_rd[5].compare_data_fall3_r1_reg[5] ;\n wire \\gen_mux_rd[5].compare_data_rise0_r1_reg[5] ;\n wire \\gen_mux_rd[5].compare_data_rise1_r1_reg[5] ;\n wire \\gen_mux_rd[5].compare_data_rise2_r1_reg[5] ;\n wire \\gen_mux_rd[5].compare_data_rise3_r1_reg[5] ;\n wire \\gen_mux_rd[6].compare_data_fall0_r1_reg[6] ;\n wire \\gen_mux_rd[6].compare_data_fall2_r1_reg[6] ;\n wire \\gen_mux_rd[6].compare_data_fall3_r1_reg[6] ;\n wire \\gen_mux_rd[6].compare_data_rise0_r1_reg[6] ;\n wire \\gen_mux_rd[6].compare_data_rise1_r1_reg[6] ;\n wire \\gen_mux_rd[6].compare_data_rise2_r1_reg[6] ;\n wire \\gen_mux_rd[6].compare_data_rise3_r1_reg[6] ;\n wire \\gen_mux_rd[7].compare_data_fall0_r1_reg[7] ;\n wire \\gen_mux_rd[7].compare_data_fall1_r1_reg[7] ;\n wire \\gen_mux_rd[7].compare_data_fall3_r1_reg[7] ;\n wire \\gen_mux_rd[7].compare_data_rise0_r1_reg[7] ;\n wire \\gen_mux_rd[7].compare_data_rise1_r1_reg[7] ;\n wire \\gen_mux_rd[7].compare_data_rise2_r1_reg[7] ;\n wire \\gen_mux_rd[7].compare_data_rise3_r1_reg[7] ;\n wire oclkdelay_calib_done_r_reg;\n wire p_0_in102_in;\n wire p_0_in106_in;\n wire p_0_in110_in;\n wire p_0_in114_in;\n wire p_0_in118_in;\n wire p_0_in122_in;\n wire p_0_in94_in;\n wire p_0_in98_in;\n wire p_1_in;\n wire p_1_in124_in;\n wire p_1_in190_in;\n wire p_1_in256_in;\n wire p_1_in322_in;\n wire p_1_in388_in;\n wire p_1_in454_in;\n wire p_1_in520_in;\n wire [7:0]p_1_in__0;\n wire p_2_in;\n wire p_2_in126_in;\n wire p_2_in192_in;\n wire p_2_in258_in;\n wire p_2_in324_in;\n wire p_2_in390_in;\n wire p_2_in456_in;\n wire \\rd_addr[7]_i_4_n_0 ;\n wire \\rd_addr[7]_i_5_n_0 ;\n wire \\rd_addr[7]_i_6_n_0 ;\n wire \\rd_addr_reg[0]_0 ;\n wire \\rd_addr_reg[3]_0 ;\n wire \\rd_addr_reg_n_0_[0] ;\n wire \\rd_addr_reg_n_0_[1] ;\n wire \\rd_addr_reg_n_0_[2] ;\n wire \\rd_addr_reg_n_0_[4] ;\n wire \\rd_addr_reg_n_0_[5] ;\n wire \\rd_addr_reg_n_0_[6] ;\n wire \\rd_addr_reg_n_0_[7] ;\n wire \\rd_addr_reg_rep_n_0_[0] ;\n wire \\rd_addr_reg_rep_n_0_[1] ;\n wire \\rd_addr_reg_rep_n_0_[2] ;\n wire \\rd_addr_reg_rep_n_0_[3] ;\n wire \\rd_addr_reg_rep_n_0_[4] ;\n wire \\rd_addr_reg_rep_n_0_[5] ;\n wire \\rd_addr_reg_rep_n_0_[6] ;\n wire \\rd_addr_reg_rep_n_0_[7] ;\n wire rdlvl_stg1_done_int_reg;\n wire [0:0]rstdiv0_sync_r1_reg_rep__19;\n wire wrcal_done_reg;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[120] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[121] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[122] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[123] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[124] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[125] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[126] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[127] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[152] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[153] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[154] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[155] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[156] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[157] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[158] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[159] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[184] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[185] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[188] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[189] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[190] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[216] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[217] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[218] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[219] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[220] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[222] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[223] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[248] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[249] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[24] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[251] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[252] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[253] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[255] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[25] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[26] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[27] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[28] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[29] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[30] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[31] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[58] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[59] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[61] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[62] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[63] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[88] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[89] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[90] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[92] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[93] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[94] ;\n wire \\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[95] ;\n\n LUT5 #(\n .INIT(32'hFCBBFC88)) \n \\dout_o[0]_i_1 \n (.I0(\\dout_o[0]_i_2_n_0 ),\n .I1(\\rd_addr_reg_rep_n_0_[6] ),\n .I2(\\dout_o[0]_i_3_n_0 ),\n .I3(\\rd_addr_reg_rep_n_0_[7] ),\n .I4(\\dout_o[0]_i_4_n_0 ),\n .O(\\dout_o[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFBA702DC40FD7BA7)) \n \\dout_o[0]_i_2 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[1] ),\n .I5(\\rd_addr_reg_rep_n_0_[4] ),\n .O(\\dout_o[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFF941DDE1)) \n \\dout_o[0]_i_3 \n (.I0(\\rd_addr_reg_rep_n_0_[4] ),\n .I1(\\rd_addr_reg_rep_n_0_[1] ),\n .I2(\\rd_addr_reg_rep_n_0_[0] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[3] ),\n .I5(\\rd_addr_reg_rep_n_0_[5] ),\n .O(\\dout_o[0]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h5F74ABA8D4EB4862)) \n \\dout_o[0]_i_4 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[4] ),\n .I5(\\rd_addr_reg_rep_n_0_[1] ),\n .O(\\dout_o[0]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\dout_o[10]_i_1 \n (.I0(\\dout_o[12]_i_2_n_0 ),\n .I1(\\rd_addr_reg_rep_n_0_[6] ),\n .I2(\\dout_o[10]_i_2_n_0 ),\n .I3(\\rd_addr_reg_rep_n_0_[7] ),\n .I4(\\dout_o[10]_i_3_n_0 ),\n .O(\\dout_o[10]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h000000004599CD27)) \n \\dout_o[10]_i_2 \n (.I0(\\rd_addr_reg_rep_n_0_[4] ),\n .I1(\\rd_addr_reg_rep_n_0_[1] ),\n .I2(\\rd_addr_reg_rep_n_0_[0] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[3] ),\n .I5(\\rd_addr_reg_rep_n_0_[5] ),\n .O(\\dout_o[10]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h139126016C0923FA)) \n \\dout_o[10]_i_3 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[1] ),\n .I5(\\rd_addr_reg_rep_n_0_[4] ),\n .O(\\dout_o[10]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\dout_o[11]_i_1 \n (.I0(\\dout_o[11]_i_2_n_0 ),\n .I1(\\rd_addr_reg_rep_n_0_[6] ),\n .I2(\\dout_o[11]_i_3_n_0 ),\n .I3(\\rd_addr_reg_rep_n_0_[7] ),\n .I4(\\dout_o[11]_i_4_n_0 ),\n .O(\\dout_o[11]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h713DD3CC4AE43A65)) \n \\dout_o[11]_i_2 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[4] ),\n .I5(\\rd_addr_reg_rep_n_0_[1] ),\n .O(\\dout_o[11]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00000000322002AD)) \n \\dout_o[11]_i_3 \n (.I0(\\rd_addr_reg_rep_n_0_[1] ),\n .I1(\\rd_addr_reg_rep_n_0_[4] ),\n .I2(\\rd_addr_reg_rep_n_0_[0] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[3] ),\n .I5(\\rd_addr_reg_rep_n_0_[5] ),\n .O(\\dout_o[11]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h7BB6E4333589857B)) \n \\dout_o[11]_i_4 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[1] ),\n .I4(\\rd_addr_reg_rep_n_0_[4] ),\n .I5(\\rd_addr_reg_rep_n_0_[0] ),\n .O(\\dout_o[11]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\dout_o[12]_i_1 \n (.I0(\\dout_o[12]_i_2_n_0 ),\n .I1(\\rd_addr_reg_rep_n_0_[6] ),\n .I2(\\dout_o[12]_i_3_n_0 ),\n .I3(\\rd_addr_reg_rep_n_0_[7] ),\n .I4(\\dout_o[12]_i_4_n_0 ),\n .O(\\dout_o[12]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h9100E82800132190)) \n \\dout_o[12]_i_2 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[4] ),\n .I5(\\rd_addr_reg_rep_n_0_[1] ),\n .O(\\dout_o[12]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000031C1E208)) \n \\dout_o[12]_i_3 \n (.I0(\\rd_addr_reg_rep_n_0_[0] ),\n .I1(\\rd_addr_reg_rep_n_0_[4] ),\n .I2(\\rd_addr_reg_rep_n_0_[1] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[3] ),\n .I5(\\rd_addr_reg_rep_n_0_[5] ),\n .O(\\dout_o[12]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h447C4014C71C60A6)) \n \\dout_o[12]_i_4 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[4] ),\n .I4(\\rd_addr_reg_rep_n_0_[1] ),\n .I5(\\rd_addr_reg_rep_n_0_[0] ),\n .O(\\dout_o[12]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\dout_o[13]_i_1 \n (.I0(\\dout_o[13]_i_2_n_0 ),\n .I1(\\rd_addr_reg_rep_n_0_[6] ),\n .I2(\\dout_o[13]_i_3_n_0 ),\n .I3(\\rd_addr_reg_rep_n_0_[7] ),\n .I4(\\dout_o[13]_i_4_n_0 ),\n .O(\\dout_o[13]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h5D37E7F8E29A3F4D)) \n \\dout_o[13]_i_2 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[2] ),\n .I2(\\rd_addr_reg_rep_n_0_[3] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[4] ),\n .I5(\\rd_addr_reg_rep_n_0_[1] ),\n .O(\\dout_o[13]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000040055161)) \n \\dout_o[13]_i_3 \n (.I0(\\rd_addr_reg_rep_n_0_[4] ),\n .I1(\\rd_addr_reg_rep_n_0_[1] ),\n .I2(\\rd_addr_reg_rep_n_0_[0] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[3] ),\n .I5(\\rd_addr_reg_rep_n_0_[5] ),\n .O(\\dout_o[13]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h6EEDFF5CF2C694A7)) \n \\dout_o[13]_i_4 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[4] ),\n .I5(\\rd_addr_reg_rep_n_0_[1] ),\n .O(\\dout_o[13]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\dout_o[14]_i_1 \n (.I0(\\dout_o[14]_i_2_n_0 ),\n .I1(\\rd_addr_reg_rep_n_0_[6] ),\n .I2(\\dout_o[14]_i_3_n_0 ),\n .I3(\\rd_addr_reg_rep_n_0_[7] ),\n .I4(\\dout_o[14]_i_4_n_0 ),\n .O(\\dout_o[14]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h9100682100130190)) \n \\dout_o[14]_i_2 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[4] ),\n .I5(\\rd_addr_reg_rep_n_0_[1] ),\n .O(\\dout_o[14]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00000000118A8B19)) \n \\dout_o[14]_i_3 \n (.I0(\\rd_addr_reg_rep_n_0_[1] ),\n .I1(\\rd_addr_reg_rep_n_0_[4] ),\n .I2(\\rd_addr_reg_rep_n_0_[0] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[3] ),\n .I5(\\rd_addr_reg_rep_n_0_[5] ),\n .O(\\dout_o[14]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hD473D375410D7424)) \n \\dout_o[14]_i_4 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[4] ),\n .I4(\\rd_addr_reg_rep_n_0_[0] ),\n .I5(\\rd_addr_reg_rep_n_0_[1] ),\n .O(\\dout_o[14]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\dout_o[15]_i_1 \n (.I0(\\dout_o[15]_i_2_n_0 ),\n .I1(\\rd_addr_reg_rep_n_0_[6] ),\n .I2(\\dout_o[15]_i_3_n_0 ),\n .I3(\\rd_addr_reg_rep_n_0_[7] ),\n .I4(\\dout_o[15]_i_4_n_0 ),\n .O(\\dout_o[15]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h5D27F5EADA9A3F4D)) \n \\dout_o[15]_i_2 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[2] ),\n .I2(\\rd_addr_reg_rep_n_0_[3] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[4] ),\n .I5(\\rd_addr_reg_rep_n_0_[1] ),\n .O(\\dout_o[15]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h000000004115533E)) \n \\dout_o[15]_i_3 \n (.I0(\\rd_addr_reg_rep_n_0_[4] ),\n .I1(\\rd_addr_reg_rep_n_0_[1] ),\n .I2(\\rd_addr_reg_rep_n_0_[0] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[3] ),\n .I5(\\rd_addr_reg_rep_n_0_[5] ),\n .O(\\dout_o[15]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h5EF9FF567BFFCDB5)) \n \\dout_o[15]_i_4 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[1] ),\n .I5(\\rd_addr_reg_rep_n_0_[4] ),\n .O(\\dout_o[15]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\dout_o[1]_i_1 \n (.I0(\\dout_o[1]_i_2_n_0 ),\n .I1(\\rd_addr_reg_rep_n_0_[6] ),\n .I2(\\dout_o[1]_i_3_n_0 ),\n .I3(\\rd_addr_reg_rep_n_0_[7] ),\n .I4(\\dout_o[1]_i_4_n_0 ),\n .O(\\dout_o[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hE7E55AE75A58865A)) \n \\dout_o[1]_i_2 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[4] ),\n .I4(\\rd_addr_reg_rep_n_0_[1] ),\n .I5(\\rd_addr_reg_rep_n_0_[0] ),\n .O(\\dout_o[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000051880521)) \n \\dout_o[1]_i_3 \n (.I0(\\rd_addr_reg_rep_n_0_[4] ),\n .I1(\\rd_addr_reg_rep_n_0_[1] ),\n .I2(\\rd_addr_reg_rep_n_0_[0] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[3] ),\n .I5(\\rd_addr_reg_rep_n_0_[5] ),\n .O(\\dout_o[1]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h7ADF52E8C4A8E711)) \n \\dout_o[1]_i_4 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[4] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[0] ),\n .I5(\\rd_addr_reg_rep_n_0_[1] ),\n .O(\\dout_o[1]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\dout_o[2]_i_1 \n (.I0(\\dout_o[2]_i_2_n_0 ),\n .I1(\\rd_addr_reg_rep_n_0_[6] ),\n .I2(\\dout_o[2]_i_3_n_0 ),\n .I3(\\rd_addr_reg_rep_n_0_[7] ),\n .I4(\\dout_o[2]_i_4_n_0 ),\n .O(\\dout_o[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFB02235842E57B02)) \n \\dout_o[2]_i_2 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[1] ),\n .I5(\\rd_addr_reg_rep_n_0_[4] ),\n .O(\\dout_o[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00000000020DCBD5)) \n \\dout_o[2]_i_3 \n (.I0(\\rd_addr_reg_rep_n_0_[0] ),\n .I1(\\rd_addr_reg_rep_n_0_[1] ),\n .I2(\\rd_addr_reg_rep_n_0_[4] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[3] ),\n .I5(\\rd_addr_reg_rep_n_0_[5] ),\n .O(\\dout_o[2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hCF45D0CFCE2B8950)) \n \\dout_o[2]_i_4 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[1] ),\n .I5(\\rd_addr_reg_rep_n_0_[4] ),\n .O(\\dout_o[2]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\dout_o[3]_i_1 \n (.I0(\\dout_o[3]_i_2_n_0 ),\n .I1(\\rd_addr_reg_rep_n_0_[6] ),\n .I2(\\dout_o[3]_i_3_n_0 ),\n .I3(\\rd_addr_reg_rep_n_0_[7] ),\n .I4(\\dout_o[3]_i_4_n_0 ),\n .O(\\dout_o[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h46E55AC658188658)) \n \\dout_o[3]_i_2 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[4] ),\n .I4(\\rd_addr_reg_rep_n_0_[1] ),\n .I5(\\rd_addr_reg_rep_n_0_[0] ),\n .O(\\dout_o[3]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00000000019C0421)) \n \\dout_o[3]_i_3 \n (.I0(\\rd_addr_reg_rep_n_0_[4] ),\n .I1(\\rd_addr_reg_rep_n_0_[1] ),\n .I2(\\rd_addr_reg_rep_n_0_[0] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[3] ),\n .I5(\\rd_addr_reg_rep_n_0_[5] ),\n .O(\\dout_o[3]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h2DCA4E194B652751)) \n \\dout_o[3]_i_4 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[1] ),\n .I4(\\rd_addr_reg_rep_n_0_[4] ),\n .I5(\\rd_addr_reg_rep_n_0_[0] ),\n .O(\\dout_o[3]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\dout_o[4]_i_1 \n (.I0(\\dout_o[4]_i_2_n_0 ),\n .I1(\\rd_addr_reg_rep_n_0_[6] ),\n .I2(\\dout_o[4]_i_3_n_0 ),\n .I3(\\rd_addr_reg_rep_n_0_[7] ),\n .I4(\\dout_o[4]_i_4_n_0 ),\n .O(\\dout_o[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hD87BBD58DE86587B)) \n \\dout_o[4]_i_2 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[4] ),\n .I5(\\rd_addr_reg_rep_n_0_[1] ),\n .O(\\dout_o[4]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h000000000455F0E2)) \n \\dout_o[4]_i_3 \n (.I0(\\rd_addr_reg_rep_n_0_[4] ),\n .I1(\\rd_addr_reg_rep_n_0_[0] ),\n .I2(\\rd_addr_reg_rep_n_0_[1] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[3] ),\n .I5(\\rd_addr_reg_rep_n_0_[5] ),\n .O(\\dout_o[4]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h1A563E3E1BBEA40C)) \n \\dout_o[4]_i_4 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[4] ),\n .I4(\\rd_addr_reg_rep_n_0_[1] ),\n .I5(\\rd_addr_reg_rep_n_0_[0] ),\n .O(\\dout_o[4]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\dout_o[5]_i_1 \n (.I0(\\dout_o[5]_i_2_n_0 ),\n .I1(\\rd_addr_reg_rep_n_0_[6] ),\n .I2(\\dout_o[5]_i_3_n_0 ),\n .I3(\\rd_addr_reg_rep_n_0_[7] ),\n .I4(\\dout_o[5]_i_4_n_0 ),\n .O(\\dout_o[5]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h42588642FDA55AFD)) \n \\dout_o[5]_i_2 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[4] ),\n .I4(\\rd_addr_reg_rep_n_0_[1] ),\n .I5(\\rd_addr_reg_rep_n_0_[0] ),\n .O(\\dout_o[5]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000013A810A9)) \n \\dout_o[5]_i_3 \n (.I0(\\rd_addr_reg_rep_n_0_[1] ),\n .I1(\\rd_addr_reg_rep_n_0_[4] ),\n .I2(\\rd_addr_reg_rep_n_0_[0] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[3] ),\n .I5(\\rd_addr_reg_rep_n_0_[5] ),\n .O(\\dout_o[5]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h183B5DF6A40A3E0D)) \n \\dout_o[5]_i_4 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[4] ),\n .I5(\\rd_addr_reg_rep_n_0_[1] ),\n .O(\\dout_o[5]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\dout_o[6]_i_1 \n (.I0(\\dout_o[6]_i_2_n_0 ),\n .I1(\\rd_addr_reg_rep_n_0_[6] ),\n .I2(\\dout_o[6]_i_3_n_0 ),\n .I3(\\rd_addr_reg_rep_n_0_[7] ),\n .I4(\\dout_o[6]_i_4_n_0 ),\n .O(\\dout_o[6]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hA35A585A84A7235A)) \n \\dout_o[6]_i_2 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[4] ),\n .I5(\\rd_addr_reg_rep_n_0_[1] ),\n .O(\\dout_o[6]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h000000004441C9B1)) \n \\dout_o[6]_i_3 \n (.I0(\\rd_addr_reg_rep_n_0_[4] ),\n .I1(\\rd_addr_reg_rep_n_0_[1] ),\n .I2(\\rd_addr_reg_rep_n_0_[0] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[3] ),\n .I5(\\rd_addr_reg_rep_n_0_[5] ),\n .O(\\dout_o[6]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h00D98F5FB527B08E)) \n \\dout_o[6]_i_4 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[4] ),\n .I4(\\rd_addr_reg_rep_n_0_[0] ),\n .I5(\\rd_addr_reg_rep_n_0_[1] ),\n .O(\\dout_o[6]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\dout_o[7]_i_1 \n (.I0(\\dout_o[7]_i_2_n_0 ),\n .I1(\\rd_addr_reg_rep_n_0_[6] ),\n .I2(\\dout_o[7]_i_3_n_0 ),\n .I3(\\rd_addr_reg_rep_n_0_[7] ),\n .I4(\\dout_o[7]_i_4_n_0 ),\n .O(\\dout_o[7]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h5C00BF1AFFA5DC00)) \n \\dout_o[7]_i_2 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[4] ),\n .I5(\\rd_addr_reg_rep_n_0_[1] ),\n .O(\\dout_o[7]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h0000000016D00494)) \n \\dout_o[7]_i_3 \n (.I0(\\rd_addr_reg_rep_n_0_[4] ),\n .I1(\\rd_addr_reg_rep_n_0_[1] ),\n .I2(\\rd_addr_reg_rep_n_0_[0] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[3] ),\n .I5(\\rd_addr_reg_rep_n_0_[5] ),\n .O(\\dout_o[7]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hAA852B305155E79F)) \n \\dout_o[7]_i_4 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[1] ),\n .I5(\\rd_addr_reg_rep_n_0_[4] ),\n .O(\\dout_o[7]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'hFCBBFC88)) \n \\dout_o[8]_i_1 \n (.I0(\\dout_o[8]_i_2_n_0 ),\n .I1(\\rd_addr_reg_rep_n_0_[6] ),\n .I2(\\dout_o[8]_i_3_n_0 ),\n .I3(\\rd_addr_reg_rep_n_0_[7] ),\n .I4(\\dout_o[8]_i_4_n_0 ),\n .O(\\dout_o[8]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h91C9002800211311)) \n \\dout_o[8]_i_2 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[4] ),\n .I4(\\rd_addr_reg_rep_n_0_[0] ),\n .I5(\\rd_addr_reg_rep_n_0_[1] ),\n .O(\\dout_o[8]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFD8D3F245)) \n \\dout_o[8]_i_3 \n (.I0(\\rd_addr_reg_rep_n_0_[0] ),\n .I1(\\rd_addr_reg_rep_n_0_[4] ),\n .I2(\\rd_addr_reg_rep_n_0_[1] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[3] ),\n .I5(\\rd_addr_reg_rep_n_0_[5] ),\n .O(\\dout_o[8]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h0A06800432120528)) \n \\dout_o[8]_i_4 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[1] ),\n .I3(\\rd_addr_reg_rep_n_0_[4] ),\n .I4(\\rd_addr_reg_rep_n_0_[0] ),\n .I5(\\rd_addr_reg_rep_n_0_[2] ),\n .O(\\dout_o[8]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h30BB3088)) \n \\dout_o[9]_i_1 \n (.I0(\\dout_o[9]_i_2_n_0 ),\n .I1(\\rd_addr_reg_rep_n_0_[6] ),\n .I2(\\dout_o[9]_i_3_n_0 ),\n .I3(\\rd_addr_reg_rep_n_0_[7] ),\n .I4(\\dout_o[9]_i_4_n_0 ),\n .O(\\dout_o[9]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hF3F5C3DC0AE47A65)) \n \\dout_o[9]_i_2 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[2] ),\n .I3(\\rd_addr_reg_rep_n_0_[0] ),\n .I4(\\rd_addr_reg_rep_n_0_[4] ),\n .I5(\\rd_addr_reg_rep_n_0_[1] ),\n .O(\\dout_o[9]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00000000040E06D5)) \n \\dout_o[9]_i_3 \n (.I0(\\rd_addr_reg_rep_n_0_[0] ),\n .I1(\\rd_addr_reg_rep_n_0_[1] ),\n .I2(\\rd_addr_reg_rep_n_0_[4] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[3] ),\n .I5(\\rd_addr_reg_rep_n_0_[5] ),\n .O(\\dout_o[9]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h20350802BEE285FB)) \n \\dout_o[9]_i_4 \n (.I0(\\rd_addr_reg_rep_n_0_[5] ),\n .I1(\\rd_addr_reg_rep_n_0_[3] ),\n .I2(\\rd_addr_reg_rep_n_0_[4] ),\n .I3(\\rd_addr_reg_rep_n_0_[2] ),\n .I4(\\rd_addr_reg_rep_n_0_[0] ),\n .I5(\\rd_addr_reg_rep_n_0_[1] ),\n .O(\\dout_o[9]_i_4_n_0 ));\n FDRE \\dout_o_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o[0]_i_1_n_0 ),\n .Q(\\dout_o_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\dout_o_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o[10]_i_1_n_0 ),\n .Q(p_1_in388_in),\n .R(1'b0));\n FDRE \\dout_o_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o[11]_i_1_n_0 ),\n .Q(p_1_in322_in),\n .R(1'b0));\n FDRE \\dout_o_reg[12] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o[12]_i_1_n_0 ),\n .Q(p_1_in256_in),\n .R(1'b0));\n FDRE \\dout_o_reg[13] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o[13]_i_1_n_0 ),\n .Q(p_1_in190_in),\n .R(1'b0));\n FDRE \\dout_o_reg[14] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o[14]_i_1_n_0 ),\n .Q(p_1_in124_in),\n .R(1'b0));\n FDRE \\dout_o_reg[15] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o[15]_i_1_n_0 ),\n .Q(p_1_in),\n .R(1'b0));\n FDRE \\dout_o_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o[1]_i_1_n_0 ),\n .Q(p_2_in456_in),\n .R(1'b0));\n FDRE \\dout_o_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o[2]_i_1_n_0 ),\n .Q(p_2_in390_in),\n .R(1'b0));\n FDRE \\dout_o_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o[3]_i_1_n_0 ),\n .Q(p_2_in324_in),\n .R(1'b0));\n FDRE \\dout_o_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o[4]_i_1_n_0 ),\n .Q(p_2_in258_in),\n .R(1'b0));\n FDRE \\dout_o_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o[5]_i_1_n_0 ),\n .Q(p_2_in192_in),\n .R(1'b0));\n FDRE \\dout_o_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o[6]_i_1_n_0 ),\n .Q(p_2_in126_in),\n .R(1'b0));\n FDRE \\dout_o_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o[7]_i_1_n_0 ),\n .Q(p_2_in),\n .R(1'b0));\n FDRE \\dout_o_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o[8]_i_1_n_0 ),\n .Q(p_1_in520_in),\n .R(1'b0));\n FDRE \\dout_o_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dout_o[9]_i_1_n_0 ),\n .Q(p_1_in454_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair686\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[0].compare_data_fall0_r1[0]_i_1 \n (.I0(p_2_in126_in),\n .I1(p_0_in94_in),\n .I2(p_1_in124_in),\n .O(\\gen_mux_rd[0].compare_data_fall0_r1_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair639\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[0].compare_data_fall1_r1[0]_i_1 \n (.I0(p_2_in258_in),\n .I1(p_0_in94_in),\n .I2(p_1_in256_in),\n .O(\\gen_mux_rd[0].compare_data_fall1_r1_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair693\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[0].compare_data_fall2_r1[0]_i_1 \n (.I0(p_2_in390_in),\n .I1(p_0_in94_in),\n .I2(p_1_in388_in),\n .O(\\gen_mux_rd[0].compare_data_fall2_r1_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair662\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[0].compare_data_fall3_r1[0]_i_1 \n (.I0(\\dout_o_reg_n_0_[0] ),\n .I1(p_0_in94_in),\n .I2(p_1_in520_in),\n .O(\\gen_mux_rd[0].compare_data_fall3_r1_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair647\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[0].compare_data_rise0_r1[0]_i_1 \n (.I0(p_2_in),\n .I1(p_0_in94_in),\n .I2(p_1_in),\n .O(\\gen_mux_rd[0].compare_data_rise0_r1_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair682\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[0].compare_data_rise1_r1[0]_i_1 \n (.I0(p_2_in192_in),\n .I1(p_0_in94_in),\n .I2(p_1_in190_in),\n .O(\\gen_mux_rd[0].compare_data_rise1_r1_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair638\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[0].compare_data_rise2_r1[0]_i_1 \n (.I0(p_2_in324_in),\n .I1(p_0_in94_in),\n .I2(p_1_in322_in),\n .O(\\gen_mux_rd[0].compare_data_rise2_r1_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair675\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[0].compare_data_rise3_r1[0]_i_1 \n (.I0(p_2_in456_in),\n .I1(p_0_in94_in),\n .I2(p_1_in454_in),\n .O(\\gen_mux_rd[0].compare_data_rise3_r1_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair691\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[1].compare_data_fall0_r1[1]_i_1 \n (.I0(p_2_in126_in),\n .I1(p_0_in98_in),\n .I2(p_1_in124_in),\n .O(\\gen_mux_rd[1].compare_data_fall0_r1_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair688\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[1].compare_data_fall1_r1[1]_i_1 \n (.I0(p_2_in258_in),\n .I1(p_0_in98_in),\n .I2(p_1_in256_in),\n .O(\\gen_mux_rd[1].compare_data_fall1_r1_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair695\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[1].compare_data_fall2_r1[1]_i_1 \n (.I0(p_2_in390_in),\n .I1(p_0_in98_in),\n .I2(p_1_in388_in),\n .O(\\gen_mux_rd[1].compare_data_fall2_r1_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair641\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[1].compare_data_fall3_r1[1]_i_1 \n (.I0(\\dout_o_reg_n_0_[0] ),\n .I1(p_0_in98_in),\n .I2(p_1_in520_in),\n .O(\\gen_mux_rd[1].compare_data_fall3_r1_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair690\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[1].compare_data_rise0_r1[1]_i_1 \n (.I0(p_2_in),\n .I1(p_0_in98_in),\n .I2(p_1_in),\n .O(\\gen_mux_rd[1].compare_data_rise0_r1_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair651\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[1].compare_data_rise1_r1[1]_i_1 \n (.I0(p_2_in192_in),\n .I1(p_0_in98_in),\n .I2(p_1_in190_in),\n .O(\\gen_mux_rd[1].compare_data_rise1_r1_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair694\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[1].compare_data_rise2_r1[1]_i_1 \n (.I0(p_2_in324_in),\n .I1(p_0_in98_in),\n .I2(p_1_in322_in),\n .O(\\gen_mux_rd[1].compare_data_rise2_r1_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair680\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[1].compare_data_rise3_r1[1]_i_1 \n (.I0(p_2_in456_in),\n .I1(p_0_in98_in),\n .I2(p_1_in454_in),\n .O(\\gen_mux_rd[1].compare_data_rise3_r1_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair665\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[2].compare_data_fall0_r1[2]_i_1 \n (.I0(p_2_in126_in),\n .I1(p_0_in102_in),\n .I2(p_1_in124_in),\n .O(\\gen_mux_rd[2].compare_data_fall0_r1_reg[2] ));\n (* SOFT_HLUTNM = \"soft_lutpair643\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[2].compare_data_fall2_r1[2]_i_1 \n (.I0(p_2_in390_in),\n .I1(p_0_in102_in),\n .I2(p_1_in388_in),\n .O(\\gen_mux_rd[2].compare_data_fall2_r1_reg[2] ));\n (* SOFT_HLUTNM = \"soft_lutpair687\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[2].compare_data_fall3_r1[2]_i_1 \n (.I0(\\dout_o_reg_n_0_[0] ),\n .I1(p_0_in102_in),\n .I2(p_1_in520_in),\n .O(\\gen_mux_rd[2].compare_data_fall3_r1_reg[2] ));\n (* SOFT_HLUTNM = \"soft_lutpair664\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[2].compare_data_rise0_r1[2]_i_1 \n (.I0(p_2_in),\n .I1(p_0_in102_in),\n .I2(p_1_in),\n .O(\\gen_mux_rd[2].compare_data_rise0_r1_reg[2] ));\n (* SOFT_HLUTNM = \"soft_lutpair655\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[2].compare_data_rise1_r1[2]_i_1 \n (.I0(p_2_in192_in),\n .I1(p_0_in102_in),\n .I2(p_1_in190_in),\n .O(\\gen_mux_rd[2].compare_data_rise1_r1_reg[2] ));\n (* SOFT_HLUTNM = \"soft_lutpair653\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[2].compare_data_rise2_r1[2]_i_1 \n (.I0(p_2_in324_in),\n .I1(p_0_in102_in),\n .I2(p_1_in322_in),\n .O(\\gen_mux_rd[2].compare_data_rise2_r1_reg[2] ));\n (* SOFT_HLUTNM = \"soft_lutpair658\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[2].compare_data_rise3_r1[2]_i_1 \n (.I0(p_2_in456_in),\n .I1(p_0_in102_in),\n .I2(p_1_in454_in),\n .O(\\gen_mux_rd[2].compare_data_rise3_r1_reg[2] ));\n (* SOFT_HLUTNM = \"soft_lutpair667\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[3].compare_data_fall0_r1[3]_i_1 \n (.I0(p_2_in126_in),\n .I1(p_0_in106_in),\n .I2(p_1_in124_in),\n .O(\\gen_mux_rd[3].compare_data_fall0_r1_reg[3] ));\n (* SOFT_HLUTNM = \"soft_lutpair692\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[3].compare_data_fall1_r1[3]_i_1 \n (.I0(p_2_in258_in),\n .I1(p_0_in106_in),\n .I2(p_1_in256_in),\n .O(\\gen_mux_rd[3].compare_data_fall1_r1_reg[3] ));\n (* SOFT_HLUTNM = \"soft_lutpair645\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[3].compare_data_fall3_r1[3]_i_1 \n (.I0(\\dout_o_reg_n_0_[0] ),\n .I1(p_0_in106_in),\n .I2(p_1_in520_in),\n .O(\\gen_mux_rd[3].compare_data_fall3_r1_reg[3] ));\n (* SOFT_HLUTNM = \"soft_lutpair648\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[3].compare_data_rise0_r1[3]_i_1 \n (.I0(p_2_in),\n .I1(p_0_in106_in),\n .I2(p_1_in),\n .O(\\gen_mux_rd[3].compare_data_rise0_r1_reg[3] ));\n (* SOFT_HLUTNM = \"soft_lutpair679\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[3].compare_data_rise1_r1[3]_i_1 \n (.I0(p_2_in192_in),\n .I1(p_0_in106_in),\n .I2(p_1_in190_in),\n .O(\\gen_mux_rd[3].compare_data_rise1_r1_reg[3] ));\n (* SOFT_HLUTNM = \"soft_lutpair685\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[3].compare_data_rise2_r1[3]_i_1 \n (.I0(p_2_in324_in),\n .I1(p_0_in106_in),\n .I2(p_1_in322_in),\n .O(\\gen_mux_rd[3].compare_data_rise2_r1_reg[3] ));\n (* SOFT_HLUTNM = \"soft_lutpair678\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[3].compare_data_rise3_r1[3]_i_1 \n (.I0(p_2_in456_in),\n .I1(p_0_in106_in),\n .I2(p_1_in454_in),\n .O(\\gen_mux_rd[3].compare_data_rise3_r1_reg[3] ));\n (* SOFT_HLUTNM = \"soft_lutpair686\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[4].compare_data_fall0_r1[4]_i_1 \n (.I0(p_2_in126_in),\n .I1(p_0_in110_in),\n .I2(p_1_in124_in),\n .O(\\gen_mux_rd[4].compare_data_fall0_r1_reg[4] ));\n (* SOFT_HLUTNM = \"soft_lutpair640\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[4].compare_data_fall1_r1[4]_i_1 \n (.I0(p_2_in258_in),\n .I1(p_0_in110_in),\n .I2(p_1_in256_in),\n .O(\\gen_mux_rd[4].compare_data_fall1_r1_reg[4] ));\n (* SOFT_HLUTNM = \"soft_lutpair696\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[4].compare_data_fall2_r1[4]_i_1 \n (.I0(p_2_in390_in),\n .I1(p_0_in110_in),\n .I2(p_1_in388_in),\n .O(\\gen_mux_rd[4].compare_data_fall2_r1_reg[4] ));\n (* SOFT_HLUTNM = \"soft_lutpair661\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[4].compare_data_fall3_r1[4]_i_1 \n (.I0(\\dout_o_reg_n_0_[0] ),\n .I1(p_0_in110_in),\n .I2(p_1_in520_in),\n .O(\\gen_mux_rd[4].compare_data_fall3_r1_reg[4] ));\n (* SOFT_HLUTNM = \"soft_lutpair649\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[4].compare_data_rise0_r1[4]_i_1 \n (.I0(p_2_in),\n .I1(p_0_in110_in),\n .I2(p_1_in),\n .O(\\gen_mux_rd[4].compare_data_rise0_r1_reg[4] ));\n (* SOFT_HLUTNM = \"soft_lutpair684\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[4].compare_data_rise1_r1[4]_i_1 \n (.I0(p_2_in192_in),\n .I1(p_0_in110_in),\n .I2(p_1_in190_in),\n .O(\\gen_mux_rd[4].compare_data_rise1_r1_reg[4] ));\n (* SOFT_HLUTNM = \"soft_lutpair659\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[4].compare_data_rise2_r1[4]_i_1 \n (.I0(p_2_in324_in),\n .I1(p_0_in110_in),\n .I2(p_1_in322_in),\n .O(\\gen_mux_rd[4].compare_data_rise2_r1_reg[4] ));\n (* SOFT_HLUTNM = \"soft_lutpair672\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[4].compare_data_rise3_r1[4]_i_1 \n (.I0(p_2_in456_in),\n .I1(p_0_in110_in),\n .I2(p_1_in454_in),\n .O(\\gen_mux_rd[4].compare_data_rise3_r1_reg[4] ));\n (* SOFT_HLUTNM = \"soft_lutpair691\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[5].compare_data_fall0_r1[5]_i_1 \n (.I0(p_2_in126_in),\n .I1(p_0_in114_in),\n .I2(p_1_in124_in),\n .O(\\gen_mux_rd[5].compare_data_fall0_r1_reg[5] ));\n (* SOFT_HLUTNM = \"soft_lutpair692\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[5].compare_data_fall1_r1[5]_i_1 \n (.I0(p_2_in258_in),\n .I1(p_0_in114_in),\n .I2(p_1_in256_in),\n .O(\\gen_mux_rd[5].compare_data_fall1_r1_reg[5] ));\n (* SOFT_HLUTNM = \"soft_lutpair693\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[5].compare_data_fall2_r1[5]_i_1 \n (.I0(p_2_in390_in),\n .I1(p_0_in114_in),\n .I2(p_1_in388_in),\n .O(\\gen_mux_rd[5].compare_data_fall2_r1_reg[5] ));\n (* SOFT_HLUTNM = \"soft_lutpair642\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[5].compare_data_fall3_r1[5]_i_1 \n (.I0(\\dout_o_reg_n_0_[0] ),\n .I1(p_0_in114_in),\n .I2(p_1_in520_in),\n .O(\\gen_mux_rd[5].compare_data_fall3_r1_reg[5] ));\n (* SOFT_HLUTNM = \"soft_lutpair690\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[5].compare_data_rise0_r1[5]_i_1 \n (.I0(p_2_in),\n .I1(p_0_in114_in),\n .I2(p_1_in),\n .O(\\gen_mux_rd[5].compare_data_rise0_r1_reg[5] ));\n (* SOFT_HLUTNM = \"soft_lutpair652\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[5].compare_data_rise1_r1[5]_i_1 \n (.I0(p_2_in192_in),\n .I1(p_0_in114_in),\n .I2(p_1_in190_in),\n .O(\\gen_mux_rd[5].compare_data_rise1_r1_reg[5] ));\n (* SOFT_HLUTNM = \"soft_lutpair694\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[5].compare_data_rise2_r1[5]_i_1 \n (.I0(p_2_in324_in),\n .I1(p_0_in114_in),\n .I2(p_1_in322_in),\n .O(\\gen_mux_rd[5].compare_data_rise2_r1_reg[5] ));\n (* SOFT_HLUTNM = \"soft_lutpair683\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[5].compare_data_rise3_r1[5]_i_1 \n (.I0(p_2_in456_in),\n .I1(p_0_in114_in),\n .I2(p_1_in454_in),\n .O(\\gen_mux_rd[5].compare_data_rise3_r1_reg[5] ));\n (* SOFT_HLUTNM = \"soft_lutpair668\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[6].compare_data_fall0_r1[6]_i_1 \n (.I0(p_2_in126_in),\n .I1(p_0_in118_in),\n .I2(p_1_in124_in),\n .O(\\gen_mux_rd[6].compare_data_fall0_r1_reg[6] ));\n (* SOFT_HLUTNM = \"soft_lutpair644\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[6].compare_data_fall2_r1[6]_i_1 \n (.I0(p_2_in390_in),\n .I1(p_0_in118_in),\n .I2(p_1_in388_in),\n .O(\\gen_mux_rd[6].compare_data_fall2_r1_reg[6] ));\n (* SOFT_HLUTNM = \"soft_lutpair687\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[6].compare_data_fall3_r1[6]_i_1 \n (.I0(\\dout_o_reg_n_0_[0] ),\n .I1(p_0_in118_in),\n .I2(p_1_in520_in),\n .O(\\gen_mux_rd[6].compare_data_fall3_r1_reg[6] ));\n (* SOFT_HLUTNM = \"soft_lutpair663\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[6].compare_data_rise0_r1[6]_i_1 \n (.I0(p_2_in),\n .I1(p_0_in118_in),\n .I2(p_1_in),\n .O(\\gen_mux_rd[6].compare_data_rise0_r1_reg[6] ));\n (* SOFT_HLUTNM = \"soft_lutpair656\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[6].compare_data_rise1_r1[6]_i_1 \n (.I0(p_2_in192_in),\n .I1(p_0_in118_in),\n .I2(p_1_in190_in),\n .O(\\gen_mux_rd[6].compare_data_rise1_r1_reg[6] ));\n (* SOFT_HLUTNM = \"soft_lutpair654\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[6].compare_data_rise2_r1[6]_i_1 \n (.I0(p_2_in324_in),\n .I1(p_0_in118_in),\n .I2(p_1_in322_in),\n .O(\\gen_mux_rd[6].compare_data_rise2_r1_reg[6] ));\n (* SOFT_HLUTNM = \"soft_lutpair657\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[6].compare_data_rise3_r1[6]_i_1 \n (.I0(p_2_in456_in),\n .I1(p_0_in118_in),\n .I2(p_1_in454_in),\n .O(\\gen_mux_rd[6].compare_data_rise3_r1_reg[6] ));\n (* SOFT_HLUTNM = \"soft_lutpair666\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[7].compare_data_fall0_r1[7]_i_1 \n (.I0(p_2_in126_in),\n .I1(p_0_in122_in),\n .I2(p_1_in124_in),\n .O(\\gen_mux_rd[7].compare_data_fall0_r1_reg[7] ));\n (* SOFT_HLUTNM = \"soft_lutpair688\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[7].compare_data_fall1_r1[7]_i_1 \n (.I0(p_2_in258_in),\n .I1(p_0_in122_in),\n .I2(p_1_in256_in),\n .O(\\gen_mux_rd[7].compare_data_fall1_r1_reg[7] ));\n (* SOFT_HLUTNM = \"soft_lutpair646\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[7].compare_data_fall3_r1[7]_i_1 \n (.I0(\\dout_o_reg_n_0_[0] ),\n .I1(p_0_in122_in),\n .I2(p_1_in520_in),\n .O(\\gen_mux_rd[7].compare_data_fall3_r1_reg[7] ));\n (* SOFT_HLUTNM = \"soft_lutpair650\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[7].compare_data_rise0_r1[7]_i_1 \n (.I0(p_2_in),\n .I1(p_0_in122_in),\n .I2(p_1_in),\n .O(\\gen_mux_rd[7].compare_data_rise0_r1_reg[7] ));\n (* SOFT_HLUTNM = \"soft_lutpair674\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[7].compare_data_rise1_r1[7]_i_1 \n (.I0(p_2_in192_in),\n .I1(p_0_in122_in),\n .I2(p_1_in190_in),\n .O(\\gen_mux_rd[7].compare_data_rise1_r1_reg[7] ));\n (* SOFT_HLUTNM = \"soft_lutpair681\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[7].compare_data_rise2_r1[7]_i_1 \n (.I0(p_2_in324_in),\n .I1(p_0_in122_in),\n .I2(p_1_in322_in),\n .O(\\gen_mux_rd[7].compare_data_rise2_r1_reg[7] ));\n (* SOFT_HLUTNM = \"soft_lutpair673\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\gen_mux_rd[7].compare_data_rise3_r1[7]_i_1 \n (.I0(p_2_in456_in),\n .I1(p_0_in122_in),\n .I2(p_1_in454_in),\n .O(\\gen_mux_rd[7].compare_data_rise3_r1_reg[7] ));\n FDRE phy_if_empty_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .Q(\\rd_addr_reg[0]_0 ),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h1)) \n \\rd_addr[0]_i_1 \n (.I0(\\rd_addr_reg_n_0_[0] ),\n .I1(\\rd_addr[7]_i_5_n_0 ),\n .O(p_1_in__0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair676\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\rd_addr[1]_i_1 \n (.I0(\\rd_addr_reg_n_0_[0] ),\n .I1(\\rd_addr_reg_n_0_[1] ),\n .O(p_1_in__0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair660\" *) \n LUT4 #(\n .INIT(16'h1540)) \n \\rd_addr[2]_i_1 \n (.I0(\\rd_addr[7]_i_5_n_0 ),\n .I1(\\rd_addr_reg_n_0_[0] ),\n .I2(\\rd_addr_reg_n_0_[1] ),\n .I3(\\rd_addr_reg_n_0_[2] ),\n .O(p_1_in__0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair660\" *) \n LUT5 #(\n .INIT(32'h15554000)) \n \\rd_addr[3]_i_1 \n (.I0(\\rd_addr[7]_i_5_n_0 ),\n .I1(\\rd_addr_reg_n_0_[1] ),\n .I2(\\rd_addr_reg_n_0_[0] ),\n .I3(\\rd_addr_reg_n_0_[2] ),\n .I4(Q),\n .O(p_1_in__0[3]));\n LUT6 #(\n .INIT(64'h1555555540000000)) \n \\rd_addr[4]_i_1 \n (.I0(\\rd_addr[7]_i_5_n_0 ),\n .I1(\\rd_addr_reg_n_0_[2] ),\n .I2(\\rd_addr_reg_n_0_[0] ),\n .I3(\\rd_addr_reg_n_0_[1] ),\n .I4(Q),\n .I5(\\rd_addr_reg_n_0_[4] ),\n .O(p_1_in__0[4]));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n \\rd_addr[5]_i_1 \n (.I0(\\rd_addr_reg_n_0_[5] ),\n .I1(Q),\n .I2(\\rd_addr_reg_n_0_[1] ),\n .I3(\\rd_addr_reg_n_0_[0] ),\n .I4(\\rd_addr_reg_n_0_[2] ),\n .I5(\\rd_addr_reg_n_0_[4] ),\n .O(p_1_in__0[5]));\n (* SOFT_HLUTNM = \"soft_lutpair677\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\rd_addr[6]_i_1 \n (.I0(\\rd_addr_reg_n_0_[6] ),\n .I1(\\rd_addr[7]_i_4_n_0 ),\n .O(p_1_in__0[6]));\n (* SOFT_HLUTNM = \"soft_lutpair677\" *) \n LUT4 #(\n .INIT(16'h006A)) \n \\rd_addr[7]_i_3 \n (.I0(\\rd_addr_reg_n_0_[7] ),\n .I1(\\rd_addr[7]_i_4_n_0 ),\n .I2(\\rd_addr_reg_n_0_[6] ),\n .I3(\\rd_addr[7]_i_5_n_0 ),\n .O(p_1_in__0[7]));\n LUT6 #(\n .INIT(64'h8000000000000000)) \n \\rd_addr[7]_i_4 \n (.I0(\\rd_addr_reg_n_0_[5] ),\n .I1(\\rd_addr_reg_n_0_[4] ),\n .I2(\\rd_addr_reg_n_0_[2] ),\n .I3(\\rd_addr_reg_n_0_[0] ),\n .I4(\\rd_addr_reg_n_0_[1] ),\n .I5(Q),\n .O(\\rd_addr[7]_i_4_n_0 ));\n LUT5 #(\n .INIT(32'h00000010)) \n \\rd_addr[7]_i_5 \n (.I0(\\rd_addr[7]_i_6_n_0 ),\n .I1(\\rd_addr_reg_n_0_[5] ),\n .I2(\\rd_addr_reg_n_0_[7] ),\n .I3(\\rd_addr_reg_n_0_[6] ),\n .I4(\\rd_addr_reg[3]_0 ),\n .O(\\rd_addr[7]_i_5_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair676\" *) \n LUT4 #(\n .INIT(16'hEFFF)) \n \\rd_addr[7]_i_6 \n (.I0(\\rd_addr_reg_n_0_[1] ),\n .I1(\\rd_addr_reg_n_0_[0] ),\n .I2(\\rd_addr_reg_n_0_[4] ),\n .I3(\\rd_addr_reg_n_0_[2] ),\n .O(\\rd_addr[7]_i_6_n_0 ));\n (* RAM_STYLE = \"distributed\" *) \n FDRE \\rd_addr_reg[0] \n (.C(CLK),\n .CE(E),\n .D(p_1_in__0[0]),\n .Q(\\rd_addr_reg_n_0_[0] ),\n .R(SR));\n (* RAM_STYLE = \"distributed\" *) \n FDRE \\rd_addr_reg[1] \n (.C(CLK),\n .CE(E),\n .D(p_1_in__0[1]),\n .Q(\\rd_addr_reg_n_0_[1] ),\n .R(SR));\n (* RAM_STYLE = \"distributed\" *) \n FDRE \\rd_addr_reg[2] \n (.C(CLK),\n .CE(E),\n .D(p_1_in__0[2]),\n .Q(\\rd_addr_reg_n_0_[2] ),\n .R(SR));\n (* RAM_STYLE = \"distributed\" *) \n FDRE \\rd_addr_reg[3] \n (.C(CLK),\n .CE(E),\n .D(p_1_in__0[3]),\n .Q(Q),\n .R(SR));\n (* RAM_STYLE = \"distributed\" *) \n FDRE \\rd_addr_reg[4] \n (.C(CLK),\n .CE(E),\n .D(p_1_in__0[4]),\n .Q(\\rd_addr_reg_n_0_[4] ),\n .R(SR));\n (* RAM_STYLE = \"distributed\" *) \n FDRE \\rd_addr_reg[5] \n (.C(CLK),\n .CE(E),\n .D(p_1_in__0[5]),\n .Q(\\rd_addr_reg_n_0_[5] ),\n .R(SR));\n (* RAM_STYLE = \"distributed\" *) \n FDRE \\rd_addr_reg[6] \n (.C(CLK),\n .CE(E),\n .D(p_1_in__0[6]),\n .Q(\\rd_addr_reg_n_0_[6] ),\n .R(SR));\n (* RAM_STYLE = \"distributed\" *) \n FDRE \\rd_addr_reg[7] \n (.C(CLK),\n .CE(E),\n .D(p_1_in__0[7]),\n .Q(\\rd_addr_reg_n_0_[7] ),\n .R(SR));\n (* equivalent_register_removal = \"no\" *) \n FDRE \\rd_addr_reg_rep[0] \n (.C(CLK),\n .CE(E),\n .D(p_1_in__0[0]),\n .Q(\\rd_addr_reg_rep_n_0_[0] ),\n .R(SR));\n (* equivalent_register_removal = \"no\" *) \n FDRE \\rd_addr_reg_rep[1] \n (.C(CLK),\n .CE(E),\n .D(p_1_in__0[1]),\n .Q(\\rd_addr_reg_rep_n_0_[1] ),\n .R(SR));\n (* equivalent_register_removal = \"no\" *) \n FDRE \\rd_addr_reg_rep[2] \n (.C(CLK),\n .CE(E),\n .D(p_1_in__0[2]),\n .Q(\\rd_addr_reg_rep_n_0_[2] ),\n .R(SR));\n (* equivalent_register_removal = \"no\" *) \n FDRE \\rd_addr_reg_rep[3] \n (.C(CLK),\n .CE(E),\n .D(p_1_in__0[3]),\n .Q(\\rd_addr_reg_rep_n_0_[3] ),\n .R(SR));\n (* equivalent_register_removal = \"no\" *) \n FDRE \\rd_addr_reg_rep[4] \n (.C(CLK),\n .CE(E),\n .D(p_1_in__0[4]),\n .Q(\\rd_addr_reg_rep_n_0_[4] ),\n .R(SR));\n (* equivalent_register_removal = \"no\" *) \n FDRE \\rd_addr_reg_rep[5] \n (.C(CLK),\n .CE(E),\n .D(p_1_in__0[5]),\n .Q(\\rd_addr_reg_rep_n_0_[5] ),\n .R(SR));\n (* equivalent_register_removal = \"no\" *) \n FDRE \\rd_addr_reg_rep[6] \n (.C(CLK),\n .CE(E),\n .D(p_1_in__0[6]),\n .Q(\\rd_addr_reg_rep_n_0_[6] ),\n .R(SR));\n (* equivalent_register_removal = \"no\" *) \n FDRE \\rd_addr_reg_rep[7] \n (.C(CLK),\n .CE(E),\n .D(p_1_in__0[7]),\n .Q(\\rd_addr_reg_rep_n_0_[7] ),\n .R(SR));\n FDRE \\victim_sel_rotate.sel_reg[24] \n (.C(CLK),\n .CE(1'b1),\n .D(D[0]),\n .Q(p_0_in94_in),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE \\victim_sel_rotate.sel_reg[25] \n (.C(CLK),\n .CE(1'b1),\n .D(D[1]),\n .Q(p_0_in98_in),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE \\victim_sel_rotate.sel_reg[26] \n (.C(CLK),\n .CE(1'b1),\n .D(D[2]),\n .Q(p_0_in102_in),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE \\victim_sel_rotate.sel_reg[27] \n (.C(CLK),\n .CE(1'b1),\n .D(D[3]),\n .Q(p_0_in106_in),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE \\victim_sel_rotate.sel_reg[28] \n (.C(CLK),\n .CE(1'b1),\n .D(D[4]),\n .Q(p_0_in110_in),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE \\victim_sel_rotate.sel_reg[29] \n (.C(CLK),\n .CE(1'b1),\n .D(D[5]),\n .Q(p_0_in114_in),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE \\victim_sel_rotate.sel_reg[30] \n (.C(CLK),\n .CE(1'b1),\n .D(D[6]),\n .Q(p_0_in118_in),\n .R(rstdiv0_sync_r1_reg_rep__19));\n FDRE \\victim_sel_rotate.sel_reg[31] \n (.C(CLK),\n .CE(1'b1),\n .D(D[7]),\n .Q(p_0_in122_in),\n .R(rstdiv0_sync_r1_reg_rep__19));\n (* SOFT_HLUTNM = \"soft_lutpair639\" *) \n LUT5 #(\n .INIT(32'hE2000000)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[120]_i_1 \n (.I0(p_1_in256_in),\n .I1(p_0_in94_in),\n .I2(p_2_in258_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[120] ));\n (* SOFT_HLUTNM = \"soft_lutpair669\" *) \n LUT4 #(\n .INIT(16'hA808)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[121]_i_1 \n (.I0(wrcal_done_reg),\n .I1(p_1_in256_in),\n .I2(p_0_in98_in),\n .I3(p_2_in258_in),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[121] ));\n (* SOFT_HLUTNM = \"soft_lutpair689\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[122]_i_1 \n (.I0(p_2_in258_in),\n .I1(p_0_in102_in),\n .I2(p_1_in256_in),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[122] ));\n (* SOFT_HLUTNM = \"soft_lutpair669\" *) \n LUT4 #(\n .INIT(16'hA808)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[123]_i_1 \n (.I0(wrcal_done_reg),\n .I1(p_1_in256_in),\n .I2(p_0_in106_in),\n .I3(p_2_in258_in),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[123] ));\n (* SOFT_HLUTNM = \"soft_lutpair640\" *) \n LUT5 #(\n .INIT(32'hE2000000)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[124]_i_1 \n (.I0(p_1_in256_in),\n .I1(p_0_in110_in),\n .I2(p_2_in258_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[124] ));\n (* SOFT_HLUTNM = \"soft_lutpair670\" *) \n LUT4 #(\n .INIT(16'hA808)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[125]_i_1 \n (.I0(wrcal_done_reg),\n .I1(p_1_in256_in),\n .I2(p_0_in114_in),\n .I3(p_2_in258_in),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[125] ));\n (* SOFT_HLUTNM = \"soft_lutpair689\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[126]_i_1 \n (.I0(p_2_in258_in),\n .I1(p_0_in118_in),\n .I2(p_1_in256_in),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[126] ));\n (* SOFT_HLUTNM = \"soft_lutpair670\" *) \n LUT4 #(\n .INIT(16'hA808)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[127]_i_1 \n (.I0(wrcal_done_reg),\n .I1(p_1_in256_in),\n .I2(p_0_in122_in),\n .I3(p_2_in258_in),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[127] ));\n (* SOFT_HLUTNM = \"soft_lutpair638\" *) \n LUT5 #(\n .INIT(32'hB800FFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[152]_i_1 \n (.I0(p_2_in324_in),\n .I1(p_0_in94_in),\n .I2(p_1_in322_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[152] ));\n LUT6 #(\n .INIT(64'hE200000000000000)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[153]_i_1 \n (.I0(p_1_in322_in),\n .I1(p_0_in98_in),\n .I2(p_2_in324_in),\n .I3(oclkdelay_calib_done_r_reg),\n .I4(wrcal_done_reg),\n .I5(rdlvl_stg1_done_int_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[153] ));\n (* SOFT_HLUTNM = \"soft_lutpair653\" *) \n LUT5 #(\n .INIT(32'hE2FFFFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[154]_i_1 \n (.I0(p_1_in322_in),\n .I1(p_0_in102_in),\n .I2(p_2_in324_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[154] ));\n (* SOFT_HLUTNM = \"soft_lutpair685\" *) \n LUT4 #(\n .INIT(16'hE2FF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[155]_i_1 \n (.I0(p_1_in322_in),\n .I1(p_0_in106_in),\n .I2(p_2_in324_in),\n .I3(rdlvl_stg1_done_int_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[155] ));\n (* SOFT_HLUTNM = \"soft_lutpair659\" *) \n LUT5 #(\n .INIT(32'hB800FFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[156]_i_2 \n (.I0(p_2_in324_in),\n .I1(p_0_in110_in),\n .I2(p_1_in322_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[156] ));\n LUT6 #(\n .INIT(64'hE200000000000000)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[157]_i_1 \n (.I0(p_1_in322_in),\n .I1(p_0_in114_in),\n .I2(p_2_in324_in),\n .I3(oclkdelay_calib_done_r_reg),\n .I4(wrcal_done_reg),\n .I5(rdlvl_stg1_done_int_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[157] ));\n (* SOFT_HLUTNM = \"soft_lutpair654\" *) \n LUT5 #(\n .INIT(32'hE2FFFFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[158]_i_2 \n (.I0(p_1_in322_in),\n .I1(p_0_in118_in),\n .I2(p_2_in324_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[158] ));\n (* SOFT_HLUTNM = \"soft_lutpair681\" *) \n LUT4 #(\n .INIT(16'hE2FF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[159]_i_1 \n (.I0(p_1_in322_in),\n .I1(p_0_in122_in),\n .I2(p_2_in324_in),\n .I3(rdlvl_stg1_done_int_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[159] ));\n (* SOFT_HLUTNM = \"soft_lutpair671\" *) \n LUT4 #(\n .INIT(16'hA808)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[184]_i_1 \n (.I0(wrcal_done_reg),\n .I1(p_1_in388_in),\n .I2(p_0_in94_in),\n .I3(p_2_in390_in),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[184] ));\n LUT6 #(\n .INIT(64'hF7FFF77777777777)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[185]_i_1 \n (.I0(oclkdelay_calib_done_r_reg),\n .I1(wrcal_done_reg),\n .I2(p_2_in390_in),\n .I3(p_0_in98_in),\n .I4(p_1_in388_in),\n .I5(rdlvl_stg1_done_int_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[185] ));\n (* SOFT_HLUTNM = \"soft_lutpair643\" *) \n LUT5 #(\n .INIT(32'hE2000000)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[186]_i_1 \n (.I0(p_1_in388_in),\n .I1(p_0_in102_in),\n .I2(p_2_in390_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] ));\n (* SOFT_HLUTNM = \"soft_lutpair695\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[187]_i_1 \n (.I0(p_2_in390_in),\n .I1(p_0_in106_in),\n .I2(p_1_in388_in),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187] ));\n (* SOFT_HLUTNM = \"soft_lutpair671\" *) \n LUT4 #(\n .INIT(16'hA808)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[188]_i_1 \n (.I0(wrcal_done_reg),\n .I1(p_1_in388_in),\n .I2(p_0_in110_in),\n .I3(p_2_in390_in),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[188] ));\n LUT6 #(\n .INIT(64'hF7FFF77777777777)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[189]_i_1 \n (.I0(oclkdelay_calib_done_r_reg),\n .I1(wrcal_done_reg),\n .I2(p_2_in390_in),\n .I3(p_0_in114_in),\n .I4(p_1_in388_in),\n .I5(rdlvl_stg1_done_int_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[189] ));\n (* SOFT_HLUTNM = \"soft_lutpair644\" *) \n LUT5 #(\n .INIT(32'hE2000000)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_1 \n (.I0(p_1_in388_in),\n .I1(p_0_in118_in),\n .I2(p_2_in390_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[190] ));\n (* SOFT_HLUTNM = \"soft_lutpair696\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[191]_i_2 \n (.I0(p_2_in390_in),\n .I1(p_0_in122_in),\n .I2(p_1_in388_in),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] ));\n (* SOFT_HLUTNM = \"soft_lutpair675\" *) \n LUT4 #(\n .INIT(16'hE2FF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[216]_i_1 \n (.I0(p_1_in454_in),\n .I1(p_0_in94_in),\n .I2(p_2_in456_in),\n .I3(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[216] ));\n (* SOFT_HLUTNM = \"soft_lutpair680\" *) \n LUT4 #(\n .INIT(16'hE2FF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[217]_i_1 \n (.I0(p_1_in454_in),\n .I1(p_0_in98_in),\n .I2(p_2_in456_in),\n .I3(rdlvl_stg1_done_int_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[217] ));\n (* SOFT_HLUTNM = \"soft_lutpair658\" *) \n LUT5 #(\n .INIT(32'hB800FFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[218]_i_1 \n (.I0(p_2_in456_in),\n .I1(p_0_in102_in),\n .I2(p_1_in454_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[218] ));\n (* SOFT_HLUTNM = \"soft_lutpair678\" *) \n LUT4 #(\n .INIT(16'hE2FF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[219]_i_1 \n (.I0(p_1_in454_in),\n .I1(p_0_in106_in),\n .I2(p_2_in456_in),\n .I3(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[219] ));\n (* SOFT_HLUTNM = \"soft_lutpair672\" *) \n LUT4 #(\n .INIT(16'hE2FF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[220]_i_1 \n (.I0(p_1_in454_in),\n .I1(p_0_in110_in),\n .I2(p_2_in456_in),\n .I3(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[220] ));\n (* SOFT_HLUTNM = \"soft_lutpair683\" *) \n LUT4 #(\n .INIT(16'hE2FF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[221]_i_2 \n (.I0(p_1_in454_in),\n .I1(p_0_in114_in),\n .I2(p_2_in456_in),\n .I3(rdlvl_stg1_done_int_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[221] ));\n (* SOFT_HLUTNM = \"soft_lutpair657\" *) \n LUT5 #(\n .INIT(32'hB800FFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[222]_i_2 \n (.I0(p_2_in456_in),\n .I1(p_0_in118_in),\n .I2(p_1_in454_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[222] ));\n (* SOFT_HLUTNM = \"soft_lutpair673\" *) \n LUT4 #(\n .INIT(16'hE2FF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[223]_i_2 \n (.I0(p_1_in454_in),\n .I1(p_0_in122_in),\n .I2(p_2_in456_in),\n .I3(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[223] ));\n (* SOFT_HLUTNM = \"soft_lutpair662\" *) \n LUT5 #(\n .INIT(32'hE2000000)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[248]_i_1 \n (.I0(p_1_in520_in),\n .I1(p_0_in94_in),\n .I2(\\dout_o_reg_n_0_[0] ),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[248] ));\n (* SOFT_HLUTNM = \"soft_lutpair641\" *) \n LUT5 #(\n .INIT(32'hE2000000)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[249]_i_1 \n (.I0(p_1_in520_in),\n .I1(p_0_in98_in),\n .I2(\\dout_o_reg_n_0_[0] ),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[249] ));\n (* SOFT_HLUTNM = \"soft_lutpair647\" *) \n LUT5 #(\n .INIT(32'hE2FFFFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[24]_i_1 \n (.I0(p_1_in),\n .I1(p_0_in94_in),\n .I2(p_2_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[24] ));\n (* SOFT_HLUTNM = \"soft_lutpair645\" *) \n LUT5 #(\n .INIT(32'hE2000000)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[251]_i_1 \n (.I0(p_1_in520_in),\n .I1(p_0_in106_in),\n .I2(\\dout_o_reg_n_0_[0] ),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[251] ));\n (* SOFT_HLUTNM = \"soft_lutpair661\" *) \n LUT5 #(\n .INIT(32'hE2000000)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[252]_i_1 \n (.I0(p_1_in520_in),\n .I1(p_0_in110_in),\n .I2(\\dout_o_reg_n_0_[0] ),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[252] ));\n (* SOFT_HLUTNM = \"soft_lutpair642\" *) \n LUT5 #(\n .INIT(32'hE2000000)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[253]_i_1 \n (.I0(p_1_in520_in),\n .I1(p_0_in114_in),\n .I2(\\dout_o_reg_n_0_[0] ),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[253] ));\n (* SOFT_HLUTNM = \"soft_lutpair646\" *) \n LUT5 #(\n .INIT(32'hE2000000)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[255]_i_1 \n (.I0(p_1_in520_in),\n .I1(p_0_in122_in),\n .I2(\\dout_o_reg_n_0_[0] ),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[255] ));\n LUT6 #(\n .INIT(64'hB800B8FFFFFFFFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[25]_i_1 \n (.I0(p_2_in),\n .I1(p_0_in98_in),\n .I2(p_1_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(first_rdlvl_pat_r),\n .I5(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[25] ));\n (* SOFT_HLUTNM = \"soft_lutpair664\" *) \n LUT5 #(\n .INIT(32'hB800FFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[26]_i_1 \n (.I0(p_2_in),\n .I1(p_0_in102_in),\n .I2(p_1_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[26] ));\n (* SOFT_HLUTNM = \"soft_lutpair648\" *) \n LUT5 #(\n .INIT(32'hE2FFFFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[27]_i_1 \n (.I0(p_1_in),\n .I1(p_0_in106_in),\n .I2(p_2_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[27] ));\n (* SOFT_HLUTNM = \"soft_lutpair649\" *) \n LUT5 #(\n .INIT(32'hE2FFFFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[28]_i_1 \n (.I0(p_1_in),\n .I1(p_0_in110_in),\n .I2(p_2_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[28] ));\n LUT6 #(\n .INIT(64'hB800B8FFFFFFFFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[29]_i_1 \n (.I0(p_2_in),\n .I1(p_0_in114_in),\n .I2(p_1_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(first_rdlvl_pat_r),\n .I5(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[29] ));\n (* SOFT_HLUTNM = \"soft_lutpair663\" *) \n LUT5 #(\n .INIT(32'hB800FFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[30]_i_1 \n (.I0(p_2_in),\n .I1(p_0_in118_in),\n .I2(p_1_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[30] ));\n (* SOFT_HLUTNM = \"soft_lutpair650\" *) \n LUT5 #(\n .INIT(32'hE2FFFFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[31]_i_1 \n (.I0(p_1_in),\n .I1(p_0_in122_in),\n .I2(p_2_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[31] ));\n LUT6 #(\n .INIT(64'hC0CCC00088888888)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[57]_i_1 \n (.I0(first_rdlvl_pat_r),\n .I1(wrcal_done_reg),\n .I2(p_2_in126_in),\n .I3(p_0_in98_in),\n .I4(p_1_in124_in),\n .I5(rdlvl_stg1_done_int_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] ));\n (* SOFT_HLUTNM = \"soft_lutpair665\" *) \n LUT5 #(\n .INIT(32'hE2000000)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[58]_i_1 \n (.I0(p_1_in124_in),\n .I1(p_0_in102_in),\n .I2(p_2_in126_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[58] ));\n (* SOFT_HLUTNM = \"soft_lutpair667\" *) \n LUT5 #(\n .INIT(32'hE2000000)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[59]_i_1 \n (.I0(p_1_in124_in),\n .I1(p_0_in106_in),\n .I2(p_2_in126_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[59] ));\n LUT6 #(\n .INIT(64'hB8FFB80000000000)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[61]_i_1 \n (.I0(p_2_in126_in),\n .I1(p_0_in114_in),\n .I2(p_1_in124_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(first_rdlvl_pat_r),\n .I5(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[61] ));\n (* SOFT_HLUTNM = \"soft_lutpair668\" *) \n LUT5 #(\n .INIT(32'hE2000000)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[62]_i_1 \n (.I0(p_1_in124_in),\n .I1(p_0_in118_in),\n .I2(p_2_in126_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[62] ));\n (* SOFT_HLUTNM = \"soft_lutpair666\" *) \n LUT5 #(\n .INIT(32'hE2000000)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[63]_i_1 \n (.I0(p_1_in124_in),\n .I1(p_0_in122_in),\n .I2(p_2_in126_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[63] ));\n (* SOFT_HLUTNM = \"soft_lutpair682\" *) \n LUT4 #(\n .INIT(16'hE2FF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[88]_i_1 \n (.I0(p_1_in190_in),\n .I1(p_0_in94_in),\n .I2(p_2_in192_in),\n .I3(rdlvl_stg1_done_int_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[88] ));\n (* SOFT_HLUTNM = \"soft_lutpair651\" *) \n LUT5 #(\n .INIT(32'hE2FFFFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[89]_i_1 \n (.I0(p_1_in190_in),\n .I1(p_0_in98_in),\n .I2(p_2_in192_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[89] ));\n (* SOFT_HLUTNM = \"soft_lutpair655\" *) \n LUT5 #(\n .INIT(32'hE2FFFFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[90]_i_1 \n (.I0(p_1_in190_in),\n .I1(p_0_in102_in),\n .I2(p_2_in192_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[90] ));\n (* SOFT_HLUTNM = \"soft_lutpair679\" *) \n LUT4 #(\n .INIT(16'hE2FF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[91]_i_1 \n (.I0(p_1_in190_in),\n .I1(p_0_in106_in),\n .I2(p_2_in192_in),\n .I3(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[91] ));\n (* SOFT_HLUTNM = \"soft_lutpair684\" *) \n LUT4 #(\n .INIT(16'hE2FF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[92]_i_1 \n (.I0(p_1_in190_in),\n .I1(p_0_in110_in),\n .I2(p_2_in192_in),\n .I3(rdlvl_stg1_done_int_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[92] ));\n (* SOFT_HLUTNM = \"soft_lutpair652\" *) \n LUT5 #(\n .INIT(32'hE2FFFFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[93]_i_1 \n (.I0(p_1_in190_in),\n .I1(p_0_in114_in),\n .I2(p_2_in192_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[93] ));\n (* SOFT_HLUTNM = \"soft_lutpair656\" *) \n LUT5 #(\n .INIT(32'hE2FFFFFF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[94]_i_1 \n (.I0(p_1_in190_in),\n .I1(p_0_in118_in),\n .I2(p_2_in192_in),\n .I3(rdlvl_stg1_done_int_reg),\n .I4(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[94] ));\n (* SOFT_HLUTNM = \"soft_lutpair674\" *) \n LUT4 #(\n .INIT(16'hE2FF)) \n \\wrdq_div1_4to1_wrcal_first.phy_wrdata[95]_i_1 \n (.I0(p_1_in190_in),\n .I1(p_0_in122_in),\n .I2(p_2_in192_in),\n .I3(wrcal_done_reg),\n .O(\\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[95] ));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_infrastructure\n (mmcm_locked,\n psdone,\n CLK,\n mmcm_ps_clk,\n freq_refclk,\n mem_refclk,\n sync_pulse,\n poc_sample_pd,\n rst_sync_r1,\n \\stg3_tap_cnt_reg[0] ,\n reset_reg,\n \\simp_stg3_final_r_reg[17] ,\n in0,\n \\read_fifo.head_r_reg[0] ,\n SR,\n \\rd_ptr_timing_reg[2] ,\n SS,\n cal2_if_reset_reg,\n cal2_done_r_reg,\n \\wrcal_dqs_cnt_r_reg[2] ,\n \\two_dec_max_limit_reg[11] ,\n \\fine_pi_dec_cnt_reg[0] ,\n rst_out_reg,\n \\en_cnt_div4.enable_wrlvl_cnt_reg[2] ,\n \\complex_address_reg[0] ,\n complex_sample_cnt_inc_reg,\n \\dec_cnt_reg[0] ,\n mpr_rank_done_r_reg,\n \\gen_final_tap[2].final_val_reg[2][0] ,\n \\wl_tap_count_r_reg[0] ,\n \\complex_num_reads_dec_reg[0] ,\n \\victim_sel_rotate.sel_reg[31] ,\n \\rtp_timer_r_reg[0] ,\n \\last_master_r_reg[2] ,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ,\n \\wait_cnt_reg[3] ,\n \\wrcal_reads_reg[0] ,\n \\oneeighty_r_reg[0] ,\n RST0,\n \\stg3_r_reg[1] ,\n \\oneeighty_r_reg[0]_0 ,\n pll_locked,\n rtp_timer_ns1,\n pre_wait_r_reg,\n rtp_timer_ns1_0,\n rtp_timer_ns1_1,\n ras_timer_zero_r_reg,\n ras_timer_zero_r_reg_0,\n ras_timer_zero_r_reg_1,\n ras_timer_zero_r_reg_2,\n \\pi_rst_stg1_cal_r_reg[1] ,\n \\samp_edge_cnt0_r_reg[11] ,\n \\wait_cnt_r_reg[3] ,\n \\en_cnt_div4.enable_wrlvl_cnt_reg[4] ,\n p_81_in,\n \\wr_victim_sel_ocal_reg[2] ,\n cnt_pwron_reset_done_r0,\n \\wait_cnt_reg[3]_0 ,\n E,\n mmcm_clk,\n AS,\n \\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ,\n \\lim_state_reg[0] ,\n poc_backup_r_reg,\n \\resume_wait_r_reg[10] ,\n sm_r,\n pass_open_bank_r,\n pass_open_bank_r_2,\n pass_open_bank_r_3,\n pass_open_bank_r_4,\n bm_end_r1,\n bm_end_r1_5,\n bm_end_r1_6,\n bm_end_r1_7,\n fine_adjust_reg,\n samp_edge_cnt0_en_r,\n pi_cnt_dec,\n \\en_cnt_div4.wrlvl_odt_reg ,\n \\row_cnt_victim_rotate.complex_row_cnt_reg[7] ,\n wr_victim_inc_reg,\n phy_mc_go,\n po_cnt_dec);\n output mmcm_locked;\n output psdone;\n output CLK;\n output mmcm_ps_clk;\n output freq_refclk;\n output mem_refclk;\n output sync_pulse;\n output poc_sample_pd;\n output rst_sync_r1;\n output \\stg3_tap_cnt_reg[0] ;\n output reset_reg;\n output \\simp_stg3_final_r_reg[17] ;\n output in0;\n output \\read_fifo.head_r_reg[0] ;\n output [0:0]SR;\n output \\rd_ptr_timing_reg[2] ;\n output [0:0]SS;\n output cal2_if_reset_reg;\n output [0:0]cal2_done_r_reg;\n output \\wrcal_dqs_cnt_r_reg[2] ;\n output \\two_dec_max_limit_reg[11] ;\n output \\fine_pi_dec_cnt_reg[0] ;\n output rst_out_reg;\n output \\en_cnt_div4.enable_wrlvl_cnt_reg[2] ;\n output [0:0]\\complex_address_reg[0] ;\n output complex_sample_cnt_inc_reg;\n output \\dec_cnt_reg[0] ;\n output [1:0]mpr_rank_done_r_reg;\n output [0:0]\\gen_final_tap[2].final_val_reg[2][0] ;\n output [0:0]\\wl_tap_count_r_reg[0] ;\n output [0:0]\\complex_num_reads_dec_reg[0] ;\n output [0:0]\\victim_sel_rotate.sel_reg[31] ;\n output \\rtp_timer_r_reg[0] ;\n output \\last_master_r_reg[2] ;\n output \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ;\n output \\wait_cnt_reg[3] ;\n output \\wrcal_reads_reg[0] ;\n output \\oneeighty_r_reg[0] ;\n output RST0;\n output \\stg3_r_reg[1] ;\n output [0:0]\\oneeighty_r_reg[0]_0 ;\n output pll_locked;\n output rtp_timer_ns1;\n output pre_wait_r_reg;\n output rtp_timer_ns1_0;\n output rtp_timer_ns1_1;\n output ras_timer_zero_r_reg;\n output ras_timer_zero_r_reg_0;\n output ras_timer_zero_r_reg_1;\n output ras_timer_zero_r_reg_2;\n output \\pi_rst_stg1_cal_r_reg[1] ;\n output \\samp_edge_cnt0_r_reg[11] ;\n output [0:0]\\wait_cnt_r_reg[3] ;\n output \\en_cnt_div4.enable_wrlvl_cnt_reg[4] ;\n output p_81_in;\n output \\wr_victim_sel_ocal_reg[2] ;\n output cnt_pwron_reset_done_r0;\n output [0:0]\\wait_cnt_reg[3]_0 ;\n input [0:0]E;\n input mmcm_clk;\n input [0:0]AS;\n input \\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ;\n input \\lim_state_reg[0] ;\n input poc_backup_r_reg;\n input \\resume_wait_r_reg[10] ;\n input sm_r;\n input pass_open_bank_r;\n input pass_open_bank_r_2;\n input pass_open_bank_r_3;\n input pass_open_bank_r_4;\n input bm_end_r1;\n input bm_end_r1_5;\n input bm_end_r1_6;\n input bm_end_r1_7;\n input fine_adjust_reg;\n input samp_edge_cnt0_en_r;\n input pi_cnt_dec;\n input \\en_cnt_div4.wrlvl_odt_reg ;\n input \\row_cnt_victim_rotate.complex_row_cnt_reg[7] ;\n input wr_victim_inc_reg;\n input phy_mc_go;\n input po_cnt_dec;\n\n wire [0:0]AS;\n wire CLK;\n wire [0:0]E;\n wire RST0;\n wire RST0_0;\n wire [0:0]SR;\n wire [0:0]SS;\n wire bm_end_r1;\n wire bm_end_r1_5;\n wire bm_end_r1_6;\n wire bm_end_r1_7;\n wire [0:0]cal2_done_r_reg;\n wire cal2_if_reset_reg;\n wire clk_div2_bufg_in;\n wire clk_pll_i;\n wire cnt_pwron_reset_done_r0;\n wire [0:0]\\complex_address_reg[0] ;\n wire [0:0]\\complex_num_reads_dec_reg[0] ;\n wire complex_sample_cnt_inc_reg;\n wire \\dec_cnt_reg[0] ;\n wire \\en_cnt_div4.enable_wrlvl_cnt_reg[2] ;\n wire \\en_cnt_div4.enable_wrlvl_cnt_reg[4] ;\n wire \\en_cnt_div4.wrlvl_odt_reg ;\n wire fine_adjust_reg;\n wire \\fine_pi_dec_cnt_reg[0] ;\n wire first_rising_ps_clk_ns;\n wire first_rising_ps_clk_r;\n wire freq_refclk;\n wire [0:0]\\gen_final_tap[2].final_val_reg[2][0] ;\n wire \\gen_mmcm.u_bufg_clk_div2_n_0 ;\n wire in0;\n wire inv_poc_sample_ns0_out;\n wire inv_poc_sample_r;\n wire inv_poc_sample_r_i_2_n_0;\n wire \\last_master_r_reg[2] ;\n wire \\lim_state_reg[0] ;\n wire mem_refclk;\n wire mmcm_clk;\n wire mmcm_hi0_r;\n wire mmcm_hi0_r_i_1_n_0;\n wire mmcm_locked;\n wire mmcm_ps_clk;\n wire mmcm_ps_clk_bufg_in;\n wire [1:0]mpr_rank_done_r_reg;\n wire \\oneeighty_r_reg[0] ;\n wire [0:0]\\oneeighty_r_reg[0]_0 ;\n wire [7:0]p_0_in__2;\n wire p_81_in;\n wire pass_open_bank_r;\n wire pass_open_bank_r_2;\n wire pass_open_bank_r_3;\n wire pass_open_bank_r_4;\n wire phy_mc_go;\n wire pi_cnt_dec;\n wire \\pi_rst_stg1_cal_r_reg[1] ;\n wire pll_clk3;\n wire pll_clk3_out;\n wire pll_clkfbout;\n wire pll_locked;\n wire pll_locked_i;\n wire po_cnt_dec;\n wire poc_backup_r_reg;\n wire poc_sample_pd;\n wire poc_sample_pd_ns;\n wire poc_sample_pd_r_i_2_n_0;\n wire pre_wait_r_reg;\n wire psdone;\n wire qcntr_ns;\n wire \\qcntr_r[2]_i_1_n_0 ;\n wire \\qcntr_r[3]_i_1_n_0 ;\n wire \\qcntr_r[4]_i_1_n_0 ;\n wire \\qcntr_r[5]_i_1_n_0 ;\n wire \\qcntr_r[7]_i_3_n_0 ;\n wire [7:0]qcntr_r_reg__0;\n wire ras_timer_zero_r_reg;\n wire ras_timer_zero_r_reg_0;\n wire ras_timer_zero_r_reg_1;\n wire ras_timer_zero_r_reg_2;\n wire \\rd_ptr_timing_reg[2] ;\n wire \\read_fifo.head_r_reg[0] ;\n wire reset_reg;\n wire \\resume_wait_r_reg[10] ;\n wire \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ;\n wire \\row_cnt_victim_rotate.complex_row_cnt_reg[7] ;\n wire rst_out_reg;\n wire \\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ;\n wire [11:0]rst_sync_r;\n wire rst_sync_r1;\n wire [11:0]rstdiv0_sync_r;\n wire rstdiv0_sync_r1_reg_rep__0_n_0;\n wire rstdiv0_sync_r1_reg_rep__10_n_0;\n wire rstdiv0_sync_r1_reg_rep__11_n_0;\n wire rstdiv0_sync_r1_reg_rep__12_n_0;\n wire rstdiv0_sync_r1_reg_rep__13_n_0;\n wire rstdiv0_sync_r1_reg_rep__14_n_0;\n wire rstdiv0_sync_r1_reg_rep__15_n_0;\n wire rstdiv0_sync_r1_reg_rep__16_n_0;\n wire rstdiv0_sync_r1_reg_rep__17_n_0;\n wire rstdiv0_sync_r1_reg_rep__18_n_0;\n wire rstdiv0_sync_r1_reg_rep__19_n_0;\n wire rstdiv0_sync_r1_reg_rep__1_n_0;\n wire rstdiv0_sync_r1_reg_rep__20_n_0;\n wire rstdiv0_sync_r1_reg_rep__21_n_0;\n wire rstdiv0_sync_r1_reg_rep__22_n_0;\n wire rstdiv0_sync_r1_reg_rep__23_n_0;\n wire rstdiv0_sync_r1_reg_rep__24_n_0;\n wire rstdiv0_sync_r1_reg_rep__25_n_0;\n wire rstdiv0_sync_r1_reg_rep__26_n_0;\n wire rstdiv0_sync_r1_reg_rep__2_n_0;\n wire rstdiv0_sync_r1_reg_rep__3_n_0;\n wire rstdiv0_sync_r1_reg_rep__4_n_0;\n wire rstdiv0_sync_r1_reg_rep__5_n_0;\n wire rstdiv0_sync_r1_reg_rep__6_n_0;\n wire rstdiv0_sync_r1_reg_rep__7_n_0;\n wire rstdiv0_sync_r1_reg_rep__8_n_0;\n wire rstdiv0_sync_r1_reg_rep__9_n_0;\n wire rstdiv0_sync_r1_reg_rep_n_0;\n wire [11:0]rstdiv2_sync_r;\n (* MAX_FANOUT = \"10\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire rstdiv2_sync_r1;\n wire rtp_timer_ns1;\n wire rtp_timer_ns1_0;\n wire rtp_timer_ns1_1;\n wire \\rtp_timer_r_reg[0] ;\n wire samp_edge_cnt0_en_r;\n wire \\samp_edge_cnt0_r_reg[11] ;\n wire \\simp_stg3_final_r_reg[17] ;\n wire sm_r;\n wire \\stg3_r_reg[1] ;\n wire \\stg3_tap_cnt_reg[0] ;\n wire sync_pulse;\n wire \\two_dec_max_limit_reg[11] ;\n wire [0:0]\\victim_sel_rotate.sel_reg[31] ;\n wire [0:0]\\wait_cnt_r_reg[3] ;\n wire \\wait_cnt_reg[3] ;\n wire [0:0]\\wait_cnt_reg[3]_0 ;\n wire [0:0]\\wl_tap_count_r_reg[0] ;\n wire wr_victim_inc_reg;\n wire \\wr_victim_sel_ocal_reg[2] ;\n wire \\wrcal_dqs_cnt_r_reg[2] ;\n wire \\wrcal_reads_reg[0] ;\n wire \\NLW_gen_mmcm.mmcm_i_CLKFBOUTB_UNCONNECTED ;\n wire \\NLW_gen_mmcm.mmcm_i_CLKFBSTOPPED_UNCONNECTED ;\n wire \\NLW_gen_mmcm.mmcm_i_CLKINSTOPPED_UNCONNECTED ;\n wire \\NLW_gen_mmcm.mmcm_i_CLKOUT0B_UNCONNECTED ;\n wire \\NLW_gen_mmcm.mmcm_i_CLKOUT1B_UNCONNECTED ;\n wire \\NLW_gen_mmcm.mmcm_i_CLKOUT2_UNCONNECTED ;\n wire \\NLW_gen_mmcm.mmcm_i_CLKOUT2B_UNCONNECTED ;\n wire \\NLW_gen_mmcm.mmcm_i_CLKOUT3_UNCONNECTED ;\n wire \\NLW_gen_mmcm.mmcm_i_CLKOUT3B_UNCONNECTED ;\n wire \\NLW_gen_mmcm.mmcm_i_CLKOUT4_UNCONNECTED ;\n wire \\NLW_gen_mmcm.mmcm_i_CLKOUT5_UNCONNECTED ;\n wire \\NLW_gen_mmcm.mmcm_i_CLKOUT6_UNCONNECTED ;\n wire \\NLW_gen_mmcm.mmcm_i_DRDY_UNCONNECTED ;\n wire [15:0]\\NLW_gen_mmcm.mmcm_i_DO_UNCONNECTED ;\n wire NLW_plle2_i_CLKOUT4_UNCONNECTED;\n wire NLW_plle2_i_CLKOUT5_UNCONNECTED;\n wire NLW_plle2_i_DRDY_UNCONNECTED;\n wire [15:0]NLW_plle2_i_DO_UNCONNECTED;\n\n (* SOFT_HLUTNM = \"soft_lutpair9\" *) \n LUT2 #(\n .INIT(4'hE)) \n act_wait_r_lcl_i_3\n (.I0(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ),\n .I1(bm_end_r1),\n .O(ras_timer_zero_r_reg));\n (* SOFT_HLUTNM = \"soft_lutpair12\" *) \n LUT2 #(\n .INIT(4'hE)) \n act_wait_r_lcl_i_3__0\n (.I0(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ),\n .I1(bm_end_r1_5),\n .O(ras_timer_zero_r_reg_0));\n LUT2 #(\n .INIT(4'hE)) \n act_wait_r_lcl_i_3__1\n (.I0(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ),\n .I1(bm_end_r1_6),\n .O(ras_timer_zero_r_reg_1));\n (* SOFT_HLUTNM = \"soft_lutpair9\" *) \n LUT2 #(\n .INIT(4'hE)) \n act_wait_r_lcl_i_3__2\n (.I0(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ),\n .I1(bm_end_r1_7),\n .O(ras_timer_zero_r_reg_2));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\cal1_cnt_cpt_r[1]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__14_n_0),\n .O(mpr_rank_done_r_reg[1]));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n cal2_prech_req_r_i_1\n (.I0(rstdiv0_sync_r1_reg_rep__4_n_0),\n .O(cal2_if_reset_reg));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\cal2_state_r[3]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__5_n_0),\n .O(cal2_done_r_reg));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n cke_r_i_1\n (.I0(rstdiv0_sync_r1_reg_rep__0_n_0),\n .O(\\read_fifo.head_r_reg[0] ));\n LUT2 #(\n .INIT(4'hB)) \n cnt_pwron_cke_done_r_i_3\n (.I0(\\wrcal_reads_reg[0] ),\n .I1(phy_mc_go),\n .O(cnt_pwron_reset_done_r0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\complex_num_reads_dec[3]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__18_n_0),\n .O(\\complex_num_reads_dec_reg[0] ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n complex_victim_inc_i_1\n (.I0(rstdiv0_sync_r1_reg_rep__7_n_0),\n .O(\\two_dec_max_limit_reg[11] ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\dqs_count_r[2]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__17_n_0),\n .O(\\wl_tap_count_r_reg[0] ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\en_cnt_div4.enable_wrlvl_cnt[3]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__10_n_0),\n .O(\\en_cnt_div4.enable_wrlvl_cnt_reg[2] ));\n (* SOFT_HLUTNM = \"soft_lutpair11\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\en_cnt_div4.enable_wrlvl_cnt[4]_i_2 \n (.I0(\\wrcal_reads_reg[0] ),\n .I1(\\en_cnt_div4.wrlvl_odt_reg ),\n .O(\\en_cnt_div4.enable_wrlvl_cnt_reg[4] ));\n LUT1 #(\n .INIT(2'h1)) \n first_rising_ps_clk_r_i_1\n (.I0(reset_reg),\n .O(first_rising_ps_clk_ns));\n FDRE first_rising_ps_clk_r_reg\n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(first_rising_ps_clk_ns),\n .Q(first_rising_ps_clk_r),\n .R(1'b0));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n MMCME2_ADV #(\n .BANDWIDTH(\"HIGH\"),\n .CLKFBOUT_MULT_F(4.000000),\n .CLKFBOUT_PHASE(0.000000),\n .CLKFBOUT_USE_FINE_PS(\"FALSE\"),\n .CLKIN1_PERIOD(4.448000),\n .CLKIN2_PERIOD(0.000000),\n .CLKOUT0_DIVIDE_F(8.000000),\n .CLKOUT0_DUTY_CYCLE(0.500000),\n .CLKOUT0_PHASE(0.000000),\n .CLKOUT0_USE_FINE_PS(\"TRUE\"),\n .CLKOUT1_DIVIDE(2),\n .CLKOUT1_DUTY_CYCLE(0.500000),\n .CLKOUT1_PHASE(0.000000),\n .CLKOUT1_USE_FINE_PS(\"FALSE\"),\n .CLKOUT2_DIVIDE(1),\n .CLKOUT2_DUTY_CYCLE(0.500000),\n .CLKOUT2_PHASE(0.000000),\n .CLKOUT2_USE_FINE_PS(\"FALSE\"),\n .CLKOUT3_DIVIDE(1),\n .CLKOUT3_DUTY_CYCLE(0.500000),\n .CLKOUT3_PHASE(0.000000),\n .CLKOUT3_USE_FINE_PS(\"FALSE\"),\n .CLKOUT4_CASCADE(\"FALSE\"),\n .CLKOUT4_DIVIDE(1),\n .CLKOUT4_DUTY_CYCLE(0.500000),\n .CLKOUT4_PHASE(0.000000),\n .CLKOUT4_USE_FINE_PS(\"FALSE\"),\n .CLKOUT5_DIVIDE(1),\n .CLKOUT5_DUTY_CYCLE(0.500000),\n .CLKOUT5_PHASE(0.000000),\n .CLKOUT5_USE_FINE_PS(\"FALSE\"),\n .CLKOUT6_DIVIDE(1),\n .CLKOUT6_DUTY_CYCLE(0.500000),\n .CLKOUT6_PHASE(0.000000),\n .CLKOUT6_USE_FINE_PS(\"FALSE\"),\n .COMPENSATION(\"BUF_IN\"),\n .DIVCLK_DIVIDE(1),\n .IS_CLKINSEL_INVERTED(1'b0),\n .IS_PSEN_INVERTED(1'b0),\n .IS_PSINCDEC_INVERTED(1'b0),\n .IS_PWRDWN_INVERTED(1'b0),\n .IS_RST_INVERTED(1'b0),\n .REF_JITTER1(0.000000),\n .REF_JITTER2(0.010000),\n .SS_EN(\"FALSE\"),\n .SS_MODE(\"CENTER_HIGH\"),\n .SS_MOD_PERIOD(10000),\n .STARTUP_WAIT(\"FALSE\")) \n \\gen_mmcm.mmcm_i \n (.CLKFBIN(CLK),\n .CLKFBOUT(clk_pll_i),\n .CLKFBOUTB(\\NLW_gen_mmcm.mmcm_i_CLKFBOUTB_UNCONNECTED ),\n .CLKFBSTOPPED(\\NLW_gen_mmcm.mmcm_i_CLKFBSTOPPED_UNCONNECTED ),\n .CLKIN1(pll_clk3),\n .CLKIN2(1'b0),\n .CLKINSEL(1'b1),\n .CLKINSTOPPED(\\NLW_gen_mmcm.mmcm_i_CLKINSTOPPED_UNCONNECTED ),\n .CLKOUT0(mmcm_ps_clk_bufg_in),\n .CLKOUT0B(\\NLW_gen_mmcm.mmcm_i_CLKOUT0B_UNCONNECTED ),\n .CLKOUT1(clk_div2_bufg_in),\n .CLKOUT1B(\\NLW_gen_mmcm.mmcm_i_CLKOUT1B_UNCONNECTED ),\n .CLKOUT2(\\NLW_gen_mmcm.mmcm_i_CLKOUT2_UNCONNECTED ),\n .CLKOUT2B(\\NLW_gen_mmcm.mmcm_i_CLKOUT2B_UNCONNECTED ),\n .CLKOUT3(\\NLW_gen_mmcm.mmcm_i_CLKOUT3_UNCONNECTED ),\n .CLKOUT3B(\\NLW_gen_mmcm.mmcm_i_CLKOUT3B_UNCONNECTED ),\n .CLKOUT4(\\NLW_gen_mmcm.mmcm_i_CLKOUT4_UNCONNECTED ),\n .CLKOUT5(\\NLW_gen_mmcm.mmcm_i_CLKOUT5_UNCONNECTED ),\n .CLKOUT6(\\NLW_gen_mmcm.mmcm_i_CLKOUT6_UNCONNECTED ),\n .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DCLK(1'b0),\n .DEN(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DO(\\NLW_gen_mmcm.mmcm_i_DO_UNCONNECTED [15:0]),\n .DRDY(\\NLW_gen_mmcm.mmcm_i_DRDY_UNCONNECTED ),\n .DWE(1'b0),\n .LOCKED(mmcm_locked),\n .PSCLK(CLK),\n .PSDONE(psdone),\n .PSEN(E),\n .PSINCDEC(1'b1),\n .PWRDWN(1'b0),\n .RST(RST0_0));\n LUT1 #(\n .INIT(2'h1)) \n \\gen_mmcm.mmcm_i_i_2 \n (.I0(pll_locked_i),\n .O(RST0_0));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n BUFG \\gen_mmcm.u_bufg_clk_div2 \n (.I(clk_div2_bufg_in),\n .O(\\gen_mmcm.u_bufg_clk_div2_n_0 ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n BUFG \\gen_mmcm.u_bufg_mmcm_ps_clk \n (.I(mmcm_ps_clk_bufg_in),\n .O(mmcm_ps_clk));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n i___114_i_1\n (.I0(rstdiv0_sync_r1_reg_rep__23_n_0),\n .O(\\wait_cnt_reg[3] ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n i___3_i_1\n (.I0(rstdiv0_sync_r1_reg_rep__20_n_0),\n .O(\\rtp_timer_r_reg[0] ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n i___4_i_1\n (.I0(rstdiv0_sync_r1_reg_rep__21_n_0),\n .O(\\last_master_r_reg[2] ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n i___77_i_1\n (.I0(rstdiv0_sync_r1_reg_rep__22_n_0),\n .O(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ));\n LUT6 #(\n .INIT(64'h000000007FFF8000)) \n inv_poc_sample_r_i_1\n (.I0(qcntr_r_reg__0[7]),\n .I1(qcntr_r_reg__0[6]),\n .I2(inv_poc_sample_r_i_2_n_0),\n .I3(E),\n .I4(inv_poc_sample_r),\n .I5(reset_reg),\n .O(inv_poc_sample_ns0_out));\n LUT6 #(\n .INIT(64'hEAAAAAAAAAAAAAAA)) \n inv_poc_sample_r_i_2\n (.I0(qcntr_r_reg__0[5]),\n .I1(qcntr_r_reg__0[4]),\n .I2(qcntr_r_reg__0[2]),\n .I3(qcntr_r_reg__0[0]),\n .I4(qcntr_r_reg__0[1]),\n .I5(qcntr_r_reg__0[3]),\n .O(inv_poc_sample_r_i_2_n_0));\n FDRE inv_poc_sample_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(inv_poc_sample_ns0_out),\n .Q(inv_poc_sample_r),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h7)) \n mmcm_hi0_r_i_1\n (.I0(mmcm_hi0_r),\n .I1(first_rising_ps_clk_r),\n .O(mmcm_hi0_r_i_1_n_0));\n FDRE mmcm_hi0_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mmcm_hi0_r_i_1_n_0),\n .Q(mmcm_hi0_r),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n ocal_last_byte_done_i_1\n (.I0(rstdiv0_sync_r1_reg_rep__11_n_0),\n .O(\\complex_address_reg[0] ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n ofs_rdy_r_i_1\n (.I0(rstdiv0_sync_r1_reg_rep__1_n_0),\n .O(SR));\n (* SOFT_HLUTNM = \"soft_lutpair16\" *) \n LUT2 #(\n .INIT(4'h7)) \n phaser_ref_i_i_1\n (.I0(pll_locked_i),\n .I1(mmcm_locked),\n .O(RST0));\n (* SOFT_HLUTNM = \"soft_lutpair16\" *) \n LUT2 #(\n .INIT(4'h8)) \n phy_control_i_i_1\n (.I0(pll_locked_i),\n .I1(mmcm_locked),\n .O(pll_locked));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\pi_dqs_found_all_bank[1]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__13_n_0),\n .O(\\dec_cnt_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair11\" *) \n LUT2 #(\n .INIT(4'h1)) \n \\pi_rst_stg1_cal_r[1]_i_3 \n (.I0(\\wrcal_reads_reg[0] ),\n .I1(fine_adjust_reg),\n .O(\\pi_rst_stg1_cal_r_reg[1] ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n PLLE2_ADV #(\n .BANDWIDTH(\"OPTIMIZED\"),\n .CLKFBOUT_MULT(9),\n .CLKFBOUT_PHASE(0.000000),\n .CLKIN1_PERIOD(5.004000),\n .CLKIN2_PERIOD(0.000000),\n .CLKOUT0_DIVIDE(2),\n .CLKOUT0_DUTY_CYCLE(0.500000),\n .CLKOUT0_PHASE(337.500000),\n .CLKOUT1_DIVIDE(2),\n .CLKOUT1_DUTY_CYCLE(0.500000),\n .CLKOUT1_PHASE(0.000000),\n .CLKOUT2_DIVIDE(32),\n .CLKOUT2_DUTY_CYCLE(0.062500),\n .CLKOUT2_PHASE(9.843750),\n .CLKOUT3_DIVIDE(8),\n .CLKOUT3_DUTY_CYCLE(0.500000),\n .CLKOUT3_PHASE(0.000000),\n .CLKOUT4_DIVIDE(4),\n .CLKOUT4_DUTY_CYCLE(0.500000),\n .CLKOUT4_PHASE(168.750000),\n .CLKOUT5_DIVIDE(1),\n .CLKOUT5_DUTY_CYCLE(0.500000),\n .CLKOUT5_PHASE(0.000000),\n .COMPENSATION(\"INTERNAL\"),\n .DIVCLK_DIVIDE(1),\n .IS_CLKINSEL_INVERTED(1'b0),\n .IS_PWRDWN_INVERTED(1'b0),\n .IS_RST_INVERTED(1'b0),\n .REF_JITTER1(0.010000),\n .REF_JITTER2(0.010000),\n .STARTUP_WAIT(\"FALSE\")) \n plle2_i\n (.CLKFBIN(pll_clkfbout),\n .CLKFBOUT(pll_clkfbout),\n .CLKIN1(mmcm_clk),\n .CLKIN2(1'b0),\n .CLKINSEL(1'b1),\n .CLKOUT0(freq_refclk),\n .CLKOUT1(mem_refclk),\n .CLKOUT2(sync_pulse),\n .CLKOUT3(pll_clk3_out),\n .CLKOUT4(NLW_plle2_i_CLKOUT4_UNCONNECTED),\n .CLKOUT5(NLW_plle2_i_CLKOUT5_UNCONNECTED),\n .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DCLK(1'b0),\n .DEN(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DO(NLW_plle2_i_DO_UNCONNECTED[15:0]),\n .DRDY(NLW_plle2_i_DRDY_UNCONNECTED),\n .DWE(1'b0),\n .LOCKED(pll_locked_i),\n .PWRDWN(1'b0),\n .RST(AS));\n LUT6 #(\n .INIT(64'hBBBBEBBB44441444)) \n poc_sample_pd_r_i_1\n (.I0(reset_reg),\n .I1(inv_poc_sample_r),\n .I2(E),\n .I3(inv_poc_sample_r_i_2_n_0),\n .I4(poc_sample_pd_r_i_2_n_0),\n .I5(mmcm_hi0_r),\n .O(poc_sample_pd_ns));\n LUT2 #(\n .INIT(4'h7)) \n poc_sample_pd_r_i_2\n (.I0(qcntr_r_reg__0[6]),\n .I1(qcntr_r_reg__0[7]),\n .O(poc_sample_pd_r_i_2_n_0));\n FDRE poc_sample_pd_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(poc_sample_pd_ns),\n .Q(poc_sample_pd),\n .R(1'b0));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\prbs_state_r[4]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__8_n_0),\n .O(\\fine_pi_dec_cnt_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair12\" *) \n LUT2 #(\n .INIT(4'h1)) \n pre_wait_r_i_2__0\n (.I0(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ),\n .I1(pass_open_bank_r_2),\n .O(pre_wait_r_reg));\n LUT2 #(\n .INIT(4'hE)) \n pre_wait_r_i_3\n (.I0(\\last_master_r_reg[2] ),\n .I1(pass_open_bank_r),\n .O(rtp_timer_ns1));\n (* SOFT_HLUTNM = \"soft_lutpair13\" *) \n LUT2 #(\n .INIT(4'hE)) \n pre_wait_r_i_3__1\n (.I0(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ),\n .I1(pass_open_bank_r_3),\n .O(rtp_timer_ns1_0));\n (* SOFT_HLUTNM = \"soft_lutpair13\" *) \n LUT2 #(\n .INIT(4'hE)) \n pre_wait_r_i_3__2\n (.I0(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ),\n .I1(pass_open_bank_r_4),\n .O(rtp_timer_ns1_1));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n pwron_ce_r_i_1\n (.I0(rstdiv0_sync_r1_reg_rep__12_n_0),\n .O(complex_sample_cnt_inc_reg));\n (* SOFT_HLUTNM = \"soft_lutpair15\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\qcntr_r[0]_i_1 \n (.I0(qcntr_r_reg__0[0]),\n .O(p_0_in__2[0]));\n (* SOFT_HLUTNM = \"soft_lutpair15\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\qcntr_r[1]_i_1 \n (.I0(qcntr_r_reg__0[0]),\n .I1(qcntr_r_reg__0[1]),\n .O(p_0_in__2[1]));\n (* SOFT_HLUTNM = \"soft_lutpair7\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\qcntr_r[2]_i_1 \n (.I0(qcntr_r_reg__0[1]),\n .I1(qcntr_r_reg__0[0]),\n .I2(qcntr_r_reg__0[2]),\n .O(\\qcntr_r[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair7\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\qcntr_r[3]_i_1 \n (.I0(qcntr_r_reg__0[2]),\n .I1(qcntr_r_reg__0[0]),\n .I2(qcntr_r_reg__0[1]),\n .I3(qcntr_r_reg__0[3]),\n .O(\\qcntr_r[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair6\" *) \n LUT5 #(\n .INIT(32'h7FFF8000)) \n \\qcntr_r[4]_i_1 \n (.I0(qcntr_r_reg__0[3]),\n .I1(qcntr_r_reg__0[1]),\n .I2(qcntr_r_reg__0[0]),\n .I3(qcntr_r_reg__0[2]),\n .I4(qcntr_r_reg__0[4]),\n .O(\\qcntr_r[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h7FFFFFFF80000000)) \n \\qcntr_r[5]_i_1 \n (.I0(qcntr_r_reg__0[4]),\n .I1(qcntr_r_reg__0[2]),\n .I2(qcntr_r_reg__0[0]),\n .I3(qcntr_r_reg__0[1]),\n .I4(qcntr_r_reg__0[3]),\n .I5(qcntr_r_reg__0[5]),\n .O(\\qcntr_r[5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair8\" *) \n LUT3 #(\n .INIT(8'hB4)) \n \\qcntr_r[6]_i_1 \n (.I0(\\qcntr_r[7]_i_3_n_0 ),\n .I1(qcntr_r_reg__0[5]),\n .I2(qcntr_r_reg__0[6]),\n .O(p_0_in__2[6]));\n LUT6 #(\n .INIT(64'hFFFFFFFFB0000000)) \n \\qcntr_r[7]_i_1 \n (.I0(qcntr_r_reg__0[5]),\n .I1(\\qcntr_r[7]_i_3_n_0 ),\n .I2(E),\n .I3(qcntr_r_reg__0[7]),\n .I4(qcntr_r_reg__0[6]),\n .I5(reset_reg),\n .O(qcntr_ns));\n (* SOFT_HLUTNM = \"soft_lutpair8\" *) \n LUT4 #(\n .INIT(16'hBF40)) \n \\qcntr_r[7]_i_2 \n (.I0(\\qcntr_r[7]_i_3_n_0 ),\n .I1(qcntr_r_reg__0[5]),\n .I2(qcntr_r_reg__0[6]),\n .I3(qcntr_r_reg__0[7]),\n .O(p_0_in__2[7]));\n (* SOFT_HLUTNM = \"soft_lutpair6\" *) \n LUT5 #(\n .INIT(32'h7FFFFFFF)) \n \\qcntr_r[7]_i_3 \n (.I0(qcntr_r_reg__0[3]),\n .I1(qcntr_r_reg__0[1]),\n .I2(qcntr_r_reg__0[0]),\n .I3(qcntr_r_reg__0[2]),\n .I4(qcntr_r_reg__0[4]),\n .O(\\qcntr_r[7]_i_3_n_0 ));\n FDRE \\qcntr_r_reg[0] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__2[0]),\n .Q(qcntr_r_reg__0[0]),\n .R(qcntr_ns));\n FDRE \\qcntr_r_reg[1] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__2[1]),\n .Q(qcntr_r_reg__0[1]),\n .R(qcntr_ns));\n FDRE \\qcntr_r_reg[2] \n (.C(CLK),\n .CE(E),\n .D(\\qcntr_r[2]_i_1_n_0 ),\n .Q(qcntr_r_reg__0[2]),\n .R(qcntr_ns));\n FDRE \\qcntr_r_reg[3] \n (.C(CLK),\n .CE(E),\n .D(\\qcntr_r[3]_i_1_n_0 ),\n .Q(qcntr_r_reg__0[3]),\n .R(qcntr_ns));\n FDRE \\qcntr_r_reg[4] \n (.C(CLK),\n .CE(E),\n .D(\\qcntr_r[4]_i_1_n_0 ),\n .Q(qcntr_r_reg__0[4]),\n .R(qcntr_ns));\n FDRE \\qcntr_r_reg[5] \n (.C(CLK),\n .CE(E),\n .D(\\qcntr_r[5]_i_1_n_0 ),\n .Q(qcntr_r_reg__0[5]),\n .R(qcntr_ns));\n FDRE \\qcntr_r_reg[6] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__2[6]),\n .Q(qcntr_r_reg__0[6]),\n .R(qcntr_ns));\n FDRE \\qcntr_r_reg[7] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__2[7]),\n .Q(qcntr_r_reg__0[7]),\n .R(qcntr_ns));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\rd_ptr_timing[2]_i_1__4 \n (.I0(rstdiv0_sync_r1_reg_rep__2_n_0),\n .O(\\rd_ptr_timing_reg[2] ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\rdlvl_dqs_tap_cnt_r[0][0][0]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__15_n_0),\n .O(mpr_rank_done_r_reg[0]));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n reset_i_1\n (.I0(rstdiv0_sync_r1_reg_rep__26_n_0),\n .O(reset_reg));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n rst_out_i_2\n (.I0(rstdiv0_sync_r1_reg_rep__9_n_0),\n .O(rst_out_reg));\n FDPE rst_sync_r1_reg\n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(rst_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rst_sync_r1));\n FDPE \\rst_sync_r_reg[0] \n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(1'b0),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rst_sync_r[0]));\n FDPE \\rst_sync_r_reg[10] \n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(rst_sync_r[9]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rst_sync_r[10]));\n FDPE \\rst_sync_r_reg[11] \n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(rst_sync_r[10]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rst_sync_r[11]));\n FDPE \\rst_sync_r_reg[1] \n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(rst_sync_r[0]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rst_sync_r[1]));\n FDPE \\rst_sync_r_reg[2] \n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(rst_sync_r[1]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rst_sync_r[2]));\n FDPE \\rst_sync_r_reg[3] \n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(rst_sync_r[2]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rst_sync_r[3]));\n FDPE \\rst_sync_r_reg[4] \n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(rst_sync_r[3]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rst_sync_r[4]));\n FDPE \\rst_sync_r_reg[5] \n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(rst_sync_r[4]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rst_sync_r[5]));\n FDPE \\rst_sync_r_reg[6] \n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(rst_sync_r[5]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rst_sync_r[6]));\n FDPE \\rst_sync_r_reg[7] \n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(rst_sync_r[6]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rst_sync_r[7]));\n FDPE \\rst_sync_r_reg[8] \n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(rst_sync_r[7]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rst_sync_r[8]));\n FDPE \\rst_sync_r_reg[9] \n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(rst_sync_r[8]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rst_sync_r[9]));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE rstdiv0_sync_r1_reg_rep\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE rstdiv0_sync_r1_reg_rep__0\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__0_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE rstdiv0_sync_r1_reg_rep__1\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__1_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE rstdiv0_sync_r1_reg_rep__10\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__10_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE rstdiv0_sync_r1_reg_rep__11\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__11_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE rstdiv0_sync_r1_reg_rep__12\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__12_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE rstdiv0_sync_r1_reg_rep__13\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__13_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE rstdiv0_sync_r1_reg_rep__14\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__14_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE rstdiv0_sync_r1_reg_rep__15\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__15_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE rstdiv0_sync_r1_reg_rep__16\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__16_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE rstdiv0_sync_r1_reg_rep__17\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__17_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE rstdiv0_sync_r1_reg_rep__18\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__18_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE rstdiv0_sync_r1_reg_rep__19\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__19_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE rstdiv0_sync_r1_reg_rep__2\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__2_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE rstdiv0_sync_r1_reg_rep__20\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__20_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE rstdiv0_sync_r1_reg_rep__21\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__21_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE rstdiv0_sync_r1_reg_rep__22\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__22_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE rstdiv0_sync_r1_reg_rep__23\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__23_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE rstdiv0_sync_r1_reg_rep__24\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__24_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE rstdiv0_sync_r1_reg_rep__25\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__25_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE rstdiv0_sync_r1_reg_rep__26\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__26_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE rstdiv0_sync_r1_reg_rep__3\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__3_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE rstdiv0_sync_r1_reg_rep__4\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__4_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE rstdiv0_sync_r1_reg_rep__5\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__5_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE rstdiv0_sync_r1_reg_rep__6\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__6_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE rstdiv0_sync_r1_reg_rep__7\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__7_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE rstdiv0_sync_r1_reg_rep__8\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__8_n_0));\n (* ORIG_CELL_NAME = \"rstdiv0_sync_r1_reg\" *) \n FDPE rstdiv0_sync_r1_reg_rep__9\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r1_reg_rep__9_n_0));\n FDPE \\rstdiv0_sync_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(1'b0),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r[0]));\n FDPE \\rstdiv0_sync_r_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[9]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r[10]));\n FDPE \\rstdiv0_sync_r_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[10]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r[11]));\n FDPE \\rstdiv0_sync_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[0]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r[1]));\n FDPE \\rstdiv0_sync_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[1]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r[2]));\n FDPE \\rstdiv0_sync_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[2]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r[3]));\n FDPE \\rstdiv0_sync_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[3]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r[4]));\n FDPE \\rstdiv0_sync_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[4]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r[5]));\n FDPE \\rstdiv0_sync_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[5]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r[6]));\n FDPE \\rstdiv0_sync_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[6]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r[7]));\n FDPE \\rstdiv0_sync_r_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[7]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r[8]));\n FDPE \\rstdiv0_sync_r_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r[8]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv0_sync_r[9]));\n (* RTL_MAX_FANOUT = \"found\" *) \n (* syn_maxfan = \"10\" *) \n FDPE rstdiv2_sync_r1_reg\n (.C(\\gen_mmcm.u_bufg_clk_div2_n_0 ),\n .CE(1'b1),\n .D(rstdiv2_sync_r[11]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv2_sync_r1));\n FDPE \\rstdiv2_sync_r_reg[0] \n (.C(\\gen_mmcm.u_bufg_clk_div2_n_0 ),\n .CE(1'b1),\n .D(1'b0),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv2_sync_r[0]));\n FDPE \\rstdiv2_sync_r_reg[10] \n (.C(\\gen_mmcm.u_bufg_clk_div2_n_0 ),\n .CE(1'b1),\n .D(rstdiv2_sync_r[9]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv2_sync_r[10]));\n FDPE \\rstdiv2_sync_r_reg[11] \n (.C(\\gen_mmcm.u_bufg_clk_div2_n_0 ),\n .CE(1'b1),\n .D(rstdiv2_sync_r[10]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv2_sync_r[11]));\n FDPE \\rstdiv2_sync_r_reg[1] \n (.C(\\gen_mmcm.u_bufg_clk_div2_n_0 ),\n .CE(1'b1),\n .D(rstdiv2_sync_r[0]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv2_sync_r[1]));\n FDPE \\rstdiv2_sync_r_reg[2] \n (.C(\\gen_mmcm.u_bufg_clk_div2_n_0 ),\n .CE(1'b1),\n .D(rstdiv2_sync_r[1]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv2_sync_r[2]));\n FDPE \\rstdiv2_sync_r_reg[3] \n (.C(\\gen_mmcm.u_bufg_clk_div2_n_0 ),\n .CE(1'b1),\n .D(rstdiv2_sync_r[2]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv2_sync_r[3]));\n FDPE \\rstdiv2_sync_r_reg[4] \n (.C(\\gen_mmcm.u_bufg_clk_div2_n_0 ),\n .CE(1'b1),\n .D(rstdiv2_sync_r[3]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv2_sync_r[4]));\n FDPE \\rstdiv2_sync_r_reg[5] \n (.C(\\gen_mmcm.u_bufg_clk_div2_n_0 ),\n .CE(1'b1),\n .D(rstdiv2_sync_r[4]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv2_sync_r[5]));\n FDPE \\rstdiv2_sync_r_reg[6] \n (.C(\\gen_mmcm.u_bufg_clk_div2_n_0 ),\n .CE(1'b1),\n .D(rstdiv2_sync_r[5]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv2_sync_r[6]));\n FDPE \\rstdiv2_sync_r_reg[7] \n (.C(\\gen_mmcm.u_bufg_clk_div2_n_0 ),\n .CE(1'b1),\n .D(rstdiv2_sync_r[6]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv2_sync_r[7]));\n FDPE \\rstdiv2_sync_r_reg[8] \n (.C(\\gen_mmcm.u_bufg_clk_div2_n_0 ),\n .CE(1'b1),\n .D(rstdiv2_sync_r[7]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv2_sync_r[8]));\n FDPE \\rstdiv2_sync_r_reg[9] \n (.C(\\gen_mmcm.u_bufg_clk_div2_n_0 ),\n .CE(1'b1),\n .D(rstdiv2_sync_r[8]),\n .PRE(\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .Q(rstdiv2_sync_r[9]));\n (* SOFT_HLUTNM = \"soft_lutpair10\" *) \n LUT2 #(\n .INIT(4'hB)) \n \\samp_edge_cnt0_r[0]_i_1 \n (.I0(\\wait_cnt_reg[3] ),\n .I1(samp_edge_cnt0_en_r),\n .O(\\samp_edge_cnt0_r_reg[11] ));\n LUT2 #(\n .INIT(4'h1)) \n \\simp_stg3_final_r[23]_i_2 \n (.I0(reset_reg),\n .I1(poc_backup_r_reg),\n .O(\\simp_stg3_final_r_reg[17] ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\smallest[0][5]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__16_n_0),\n .O(\\gen_final_tap[2].final_val_reg[2][0] ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\stg2_tap_cnt[5]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__19_n_0),\n .O(\\victim_sel_rotate.sel_reg[31] ));\n LUT2 #(\n .INIT(4'hE)) \n \\stg3_r[5]_i_13 \n (.I0(reset_reg),\n .I1(\\resume_wait_r_reg[10] ),\n .O(\\stg3_r_reg[1] ));\n LUT2 #(\n .INIT(4'h1)) \n \\stg3_tap_cnt[5]_i_3 \n (.I0(reset_reg),\n .I1(\\lim_state_reg[0] ),\n .O(\\stg3_tap_cnt_reg[0] ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\tempmon_state[0]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__3_n_0),\n .O(SS));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n BUFG u_bufg_clkdiv0\n (.I(clk_pll_i),\n .O(CLK));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n BUFH u_bufh_pll_clk3\n (.I(pll_clk3_out),\n .O(pll_clk3));\n LUT1 #(\n .INIT(2'h2)) \n ui_clk_sync_rst_INST_0\n (.I0(rstdiv0_sync_r1_reg_rep_n_0),\n .O(in0));\n LUT2 #(\n .INIT(4'hE)) \n \\wait_cnt[3]_i_1 \n (.I0(\\wait_cnt_reg[3] ),\n .I1(po_cnt_dec),\n .O(\\wait_cnt_reg[3]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair10\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\wait_cnt_r[3]_i_1__1 \n (.I0(\\wait_cnt_reg[3] ),\n .I1(pi_cnt_dec),\n .O(\\wait_cnt_r_reg[3] ));\n (* SOFT_HLUTNM = \"soft_lutpair14\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\wr_victim_sel[2]_i_2 \n (.I0(\\wrcal_reads_reg[0] ),\n .I1(\\row_cnt_victim_rotate.complex_row_cnt_reg[7] ),\n .O(p_81_in));\n (* SOFT_HLUTNM = \"soft_lutpair14\" *) \n LUT2 #(\n .INIT(4'hE)) \n \\wr_victim_sel_ocal[2]_i_2 \n (.I0(\\wrcal_reads_reg[0] ),\n .I1(wr_victim_inc_reg),\n .O(\\wr_victim_sel_ocal_reg[2] ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\wrcal_dqs_cnt_r[2]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__6_n_0),\n .O(\\wrcal_dqs_cnt_r_reg[2] ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\wrcal_reads[7]_i_4 \n (.I0(rstdiv0_sync_r1_reg_rep__24_n_0),\n .O(\\wrcal_reads_reg[0] ));\n LUT2 #(\n .INIT(4'h1)) \n \\zero_r[9]_i_1 \n (.I0(\\oneeighty_r_reg[0] ),\n .I1(sm_r),\n .O(\\oneeighty_r_reg[0]_0 ));\n (* IS_FANOUT_CONSTRAINED = \"1\" *) \n LUT1 #(\n .INIT(2'h2)) \n \\zero_r[9]_i_4 \n (.I0(rstdiv0_sync_r1_reg_rep__25_n_0),\n .O(\\oneeighty_r_reg[0] ));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_iodelay_ctrl\n (AS,\n rst_sync_r1_reg,\n mmcm_clk,\n sys_rst);\n output [0:0]AS;\n output [0:0]rst_sync_r1_reg;\n input mmcm_clk;\n input sys_rst;\n\n wire [0:0]AS;\n wire \\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ;\n wire clk_ref_mmcm_400;\n wire [0:0]iodelay_ctrl_rdy;\n wire mmcm_clk;\n wire mmcm_clkfbout;\n wire rst_ref_0;\n wire rst_ref_1;\n wire \\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][0] ;\n wire \\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][10] ;\n wire \\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][11] ;\n wire \\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][12] ;\n wire \\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][13] ;\n wire \\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][1] ;\n wire \\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][2] ;\n wire \\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][3] ;\n wire \\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][4] ;\n wire \\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][5] ;\n wire \\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][6] ;\n wire \\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][7] ;\n wire \\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][8] ;\n wire \\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][9] ;\n wire \\rst_ref_sync_r_reg_n_0_[0][0] ;\n wire \\rst_ref_sync_r_reg_n_0_[0][10] ;\n wire \\rst_ref_sync_r_reg_n_0_[0][11] ;\n wire \\rst_ref_sync_r_reg_n_0_[0][12] ;\n wire \\rst_ref_sync_r_reg_n_0_[0][13] ;\n wire \\rst_ref_sync_r_reg_n_0_[0][1] ;\n wire \\rst_ref_sync_r_reg_n_0_[0][2] ;\n wire \\rst_ref_sync_r_reg_n_0_[0][3] ;\n wire \\rst_ref_sync_r_reg_n_0_[0][4] ;\n wire \\rst_ref_sync_r_reg_n_0_[0][5] ;\n wire \\rst_ref_sync_r_reg_n_0_[0][6] ;\n wire \\rst_ref_sync_r_reg_n_0_[0][7] ;\n wire \\rst_ref_sync_r_reg_n_0_[0][8] ;\n wire \\rst_ref_sync_r_reg_n_0_[0][9] ;\n wire [0:0]rst_sync_r1_reg;\n wire sys_rst;\n wire \\NLW_clk_ref_mmcm_gen.mmcm_i_CLKFBOUTB_UNCONNECTED ;\n wire \\NLW_clk_ref_mmcm_gen.mmcm_i_CLKFBSTOPPED_UNCONNECTED ;\n wire \\NLW_clk_ref_mmcm_gen.mmcm_i_CLKINSTOPPED_UNCONNECTED ;\n wire \\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT0_UNCONNECTED ;\n wire \\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT0B_UNCONNECTED ;\n wire \\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT1B_UNCONNECTED ;\n wire \\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT2_UNCONNECTED ;\n wire \\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT2B_UNCONNECTED ;\n wire \\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT3_UNCONNECTED ;\n wire \\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT3B_UNCONNECTED ;\n wire \\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT4_UNCONNECTED ;\n wire \\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT5_UNCONNECTED ;\n wire \\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT6_UNCONNECTED ;\n wire \\NLW_clk_ref_mmcm_gen.mmcm_i_DRDY_UNCONNECTED ;\n wire \\NLW_clk_ref_mmcm_gen.mmcm_i_LOCKED_UNCONNECTED ;\n wire \\NLW_clk_ref_mmcm_gen.mmcm_i_PSDONE_UNCONNECTED ;\n wire [15:0]\\NLW_clk_ref_mmcm_gen.mmcm_i_DO_UNCONNECTED ;\n\n (* BOX_TYPE = \"PRIMITIVE\" *) \n BUFG \\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400 \n (.I(clk_ref_mmcm_400),\n .O(\\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n MMCME2_ADV #(\n .BANDWIDTH(\"HIGH\"),\n .CLKFBOUT_MULT_F(6.000000),\n .CLKFBOUT_PHASE(0.000000),\n .CLKFBOUT_USE_FINE_PS(\"FALSE\"),\n .CLKIN1_PERIOD(5.000000),\n .CLKIN2_PERIOD(0.000000),\n .CLKOUT0_DIVIDE_F(4.000000),\n .CLKOUT0_DUTY_CYCLE(0.500000),\n .CLKOUT0_PHASE(0.000000),\n .CLKOUT0_USE_FINE_PS(\"FALSE\"),\n .CLKOUT1_DIVIDE(3),\n .CLKOUT1_DUTY_CYCLE(0.500000),\n .CLKOUT1_PHASE(0.000000),\n .CLKOUT1_USE_FINE_PS(\"FALSE\"),\n .CLKOUT2_DIVIDE(1),\n .CLKOUT2_DUTY_CYCLE(0.500000),\n .CLKOUT2_PHASE(0.000000),\n .CLKOUT2_USE_FINE_PS(\"FALSE\"),\n .CLKOUT3_DIVIDE(1),\n .CLKOUT3_DUTY_CYCLE(0.500000),\n .CLKOUT3_PHASE(0.000000),\n .CLKOUT3_USE_FINE_PS(\"FALSE\"),\n .CLKOUT4_CASCADE(\"FALSE\"),\n .CLKOUT4_DIVIDE(1),\n .CLKOUT4_DUTY_CYCLE(0.500000),\n .CLKOUT4_PHASE(0.000000),\n .CLKOUT4_USE_FINE_PS(\"FALSE\"),\n .CLKOUT5_DIVIDE(1),\n .CLKOUT5_DUTY_CYCLE(0.500000),\n .CLKOUT5_PHASE(0.000000),\n .CLKOUT5_USE_FINE_PS(\"FALSE\"),\n .CLKOUT6_DIVIDE(1),\n .CLKOUT6_DUTY_CYCLE(0.500000),\n .CLKOUT6_PHASE(0.000000),\n .CLKOUT6_USE_FINE_PS(\"FALSE\"),\n .COMPENSATION(\"INTERNAL\"),\n .DIVCLK_DIVIDE(1),\n .IS_CLKINSEL_INVERTED(1'b0),\n .IS_PSEN_INVERTED(1'b0),\n .IS_PSINCDEC_INVERTED(1'b0),\n .IS_PWRDWN_INVERTED(1'b0),\n .IS_RST_INVERTED(1'b0),\n .REF_JITTER1(0.000000),\n .REF_JITTER2(0.010000),\n .SS_EN(\"FALSE\"),\n .SS_MODE(\"CENTER_HIGH\"),\n .SS_MOD_PERIOD(10000),\n .STARTUP_WAIT(\"FALSE\")) \n \\clk_ref_mmcm_gen.mmcm_i \n (.CLKFBIN(mmcm_clkfbout),\n .CLKFBOUT(mmcm_clkfbout),\n .CLKFBOUTB(\\NLW_clk_ref_mmcm_gen.mmcm_i_CLKFBOUTB_UNCONNECTED ),\n .CLKFBSTOPPED(\\NLW_clk_ref_mmcm_gen.mmcm_i_CLKFBSTOPPED_UNCONNECTED ),\n .CLKIN1(mmcm_clk),\n .CLKIN2(1'b0),\n .CLKINSEL(1'b1),\n .CLKINSTOPPED(\\NLW_clk_ref_mmcm_gen.mmcm_i_CLKINSTOPPED_UNCONNECTED ),\n .CLKOUT0(\\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT0_UNCONNECTED ),\n .CLKOUT0B(\\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT0B_UNCONNECTED ),\n .CLKOUT1(clk_ref_mmcm_400),\n .CLKOUT1B(\\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT1B_UNCONNECTED ),\n .CLKOUT2(\\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT2_UNCONNECTED ),\n .CLKOUT2B(\\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT2B_UNCONNECTED ),\n .CLKOUT3(\\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT3_UNCONNECTED ),\n .CLKOUT3B(\\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT3B_UNCONNECTED ),\n .CLKOUT4(\\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT4_UNCONNECTED ),\n .CLKOUT5(\\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT5_UNCONNECTED ),\n .CLKOUT6(\\NLW_clk_ref_mmcm_gen.mmcm_i_CLKOUT6_UNCONNECTED ),\n .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DCLK(1'b0),\n .DEN(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DO(\\NLW_clk_ref_mmcm_gen.mmcm_i_DO_UNCONNECTED [15:0]),\n .DRDY(\\NLW_clk_ref_mmcm_gen.mmcm_i_DRDY_UNCONNECTED ),\n .DWE(1'b0),\n .LOCKED(\\NLW_clk_ref_mmcm_gen.mmcm_i_LOCKED_UNCONNECTED ),\n .PSCLK(1'b0),\n .PSDONE(\\NLW_clk_ref_mmcm_gen.mmcm_i_PSDONE_UNCONNECTED ),\n .PSEN(1'b0),\n .PSINCDEC(1'b0),\n .PWRDWN(1'b0),\n .RST(AS));\n LUT1 #(\n .INIT(2'h1)) \n \\clk_ref_mmcm_gen.mmcm_i_i_1 \n (.I0(sys_rst),\n .O(AS));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG1\" *) \n IDELAYCTRL #(\n .SIM_DEVICE(\"7SERIES\")) \n \\idelayctrl_gen_1.u_idelayctrl_300_400 \n (.RDY(rst_sync_r1_reg),\n .REFCLK(\\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ),\n .RST(rst_ref_1));\n (* syn_maxfan = \"10\" *) \n FDPE \\rst_ref_gen_1.rst_ref_sync_r_reg[1][0] \n (.C(\\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ),\n .CE(1'b1),\n .D(1'b0),\n .PRE(AS),\n .Q(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][0] ));\n (* syn_maxfan = \"10\" *) \n FDPE \\rst_ref_gen_1.rst_ref_sync_r_reg[1][10] \n (.C(\\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ),\n .CE(1'b1),\n .D(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][9] ),\n .PRE(AS),\n .Q(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][10] ));\n (* syn_maxfan = \"10\" *) \n FDPE \\rst_ref_gen_1.rst_ref_sync_r_reg[1][11] \n (.C(\\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ),\n .CE(1'b1),\n .D(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][10] ),\n .PRE(AS),\n .Q(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][11] ));\n (* syn_maxfan = \"10\" *) \n FDPE \\rst_ref_gen_1.rst_ref_sync_r_reg[1][12] \n (.C(\\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ),\n .CE(1'b1),\n .D(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][11] ),\n .PRE(AS),\n .Q(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][12] ));\n (* syn_maxfan = \"10\" *) \n FDPE \\rst_ref_gen_1.rst_ref_sync_r_reg[1][13] \n (.C(\\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ),\n .CE(1'b1),\n .D(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][12] ),\n .PRE(AS),\n .Q(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][13] ));\n (* syn_maxfan = \"10\" *) \n FDPE \\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] \n (.C(\\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ),\n .CE(1'b1),\n .D(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][13] ),\n .PRE(AS),\n .Q(rst_ref_1));\n (* syn_maxfan = \"10\" *) \n FDPE \\rst_ref_gen_1.rst_ref_sync_r_reg[1][1] \n (.C(\\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ),\n .CE(1'b1),\n .D(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][0] ),\n .PRE(AS),\n .Q(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][1] ));\n (* syn_maxfan = \"10\" *) \n FDPE \\rst_ref_gen_1.rst_ref_sync_r_reg[1][2] \n (.C(\\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ),\n .CE(1'b1),\n .D(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][1] ),\n .PRE(AS),\n .Q(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][2] ));\n (* syn_maxfan = \"10\" *) \n FDPE \\rst_ref_gen_1.rst_ref_sync_r_reg[1][3] \n (.C(\\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ),\n .CE(1'b1),\n .D(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][2] ),\n .PRE(AS),\n .Q(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][3] ));\n (* syn_maxfan = \"10\" *) \n FDPE \\rst_ref_gen_1.rst_ref_sync_r_reg[1][4] \n (.C(\\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ),\n .CE(1'b1),\n .D(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][3] ),\n .PRE(AS),\n .Q(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][4] ));\n (* syn_maxfan = \"10\" *) \n FDPE \\rst_ref_gen_1.rst_ref_sync_r_reg[1][5] \n (.C(\\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ),\n .CE(1'b1),\n .D(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][4] ),\n .PRE(AS),\n .Q(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][5] ));\n (* syn_maxfan = \"10\" *) \n FDPE \\rst_ref_gen_1.rst_ref_sync_r_reg[1][6] \n (.C(\\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ),\n .CE(1'b1),\n .D(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][5] ),\n .PRE(AS),\n .Q(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][6] ));\n (* syn_maxfan = \"10\" *) \n FDPE \\rst_ref_gen_1.rst_ref_sync_r_reg[1][7] \n (.C(\\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ),\n .CE(1'b1),\n .D(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][6] ),\n .PRE(AS),\n .Q(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][7] ));\n (* syn_maxfan = \"10\" *) \n FDPE \\rst_ref_gen_1.rst_ref_sync_r_reg[1][8] \n (.C(\\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ),\n .CE(1'b1),\n .D(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][7] ),\n .PRE(AS),\n .Q(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][8] ));\n (* syn_maxfan = \"10\" *) \n FDPE \\rst_ref_gen_1.rst_ref_sync_r_reg[1][9] \n (.C(\\clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400_n_0 ),\n .CE(1'b1),\n .D(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][8] ),\n .PRE(AS),\n .Q(\\rst_ref_gen_1.rst_ref_sync_r_reg_n_0_[1][9] ));\n (* syn_maxfan = \"10\" *) \n FDPE \\rst_ref_sync_r_reg[0][0] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(1'b0),\n .PRE(AS),\n .Q(\\rst_ref_sync_r_reg_n_0_[0][0] ));\n (* syn_maxfan = \"10\" *) \n FDPE \\rst_ref_sync_r_reg[0][10] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(\\rst_ref_sync_r_reg_n_0_[0][9] ),\n .PRE(AS),\n .Q(\\rst_ref_sync_r_reg_n_0_[0][10] ));\n (* syn_maxfan = \"10\" *) \n FDPE \\rst_ref_sync_r_reg[0][11] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(\\rst_ref_sync_r_reg_n_0_[0][10] ),\n .PRE(AS),\n .Q(\\rst_ref_sync_r_reg_n_0_[0][11] ));\n (* syn_maxfan = \"10\" *) \n FDPE \\rst_ref_sync_r_reg[0][12] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(\\rst_ref_sync_r_reg_n_0_[0][11] ),\n .PRE(AS),\n .Q(\\rst_ref_sync_r_reg_n_0_[0][12] ));\n (* syn_maxfan = \"10\" *) \n FDPE \\rst_ref_sync_r_reg[0][13] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(\\rst_ref_sync_r_reg_n_0_[0][12] ),\n .PRE(AS),\n .Q(\\rst_ref_sync_r_reg_n_0_[0][13] ));\n (* syn_maxfan = \"10\" *) \n FDPE \\rst_ref_sync_r_reg[0][14] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(\\rst_ref_sync_r_reg_n_0_[0][13] ),\n .PRE(AS),\n .Q(rst_ref_0));\n (* syn_maxfan = \"10\" *) \n FDPE \\rst_ref_sync_r_reg[0][1] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(\\rst_ref_sync_r_reg_n_0_[0][0] ),\n .PRE(AS),\n .Q(\\rst_ref_sync_r_reg_n_0_[0][1] ));\n (* syn_maxfan = \"10\" *) \n FDPE \\rst_ref_sync_r_reg[0][2] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(\\rst_ref_sync_r_reg_n_0_[0][1] ),\n .PRE(AS),\n .Q(\\rst_ref_sync_r_reg_n_0_[0][2] ));\n (* syn_maxfan = \"10\" *) \n FDPE \\rst_ref_sync_r_reg[0][3] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(\\rst_ref_sync_r_reg_n_0_[0][2] ),\n .PRE(AS),\n .Q(\\rst_ref_sync_r_reg_n_0_[0][3] ));\n (* syn_maxfan = \"10\" *) \n FDPE \\rst_ref_sync_r_reg[0][4] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(\\rst_ref_sync_r_reg_n_0_[0][3] ),\n .PRE(AS),\n .Q(\\rst_ref_sync_r_reg_n_0_[0][4] ));\n (* syn_maxfan = \"10\" *) \n FDPE \\rst_ref_sync_r_reg[0][5] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(\\rst_ref_sync_r_reg_n_0_[0][4] ),\n .PRE(AS),\n .Q(\\rst_ref_sync_r_reg_n_0_[0][5] ));\n (* syn_maxfan = \"10\" *) \n FDPE \\rst_ref_sync_r_reg[0][6] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(\\rst_ref_sync_r_reg_n_0_[0][5] ),\n .PRE(AS),\n .Q(\\rst_ref_sync_r_reg_n_0_[0][6] ));\n (* syn_maxfan = \"10\" *) \n FDPE \\rst_ref_sync_r_reg[0][7] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(\\rst_ref_sync_r_reg_n_0_[0][6] ),\n .PRE(AS),\n .Q(\\rst_ref_sync_r_reg_n_0_[0][7] ));\n (* syn_maxfan = \"10\" *) \n FDPE \\rst_ref_sync_r_reg[0][8] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(\\rst_ref_sync_r_reg_n_0_[0][7] ),\n .PRE(AS),\n .Q(\\rst_ref_sync_r_reg_n_0_[0][8] ));\n (* syn_maxfan = \"10\" *) \n FDPE \\rst_ref_sync_r_reg[0][9] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(\\rst_ref_sync_r_reg_n_0_[0][8] ),\n .PRE(AS),\n .Q(\\rst_ref_sync_r_reg_n_0_[0][9] ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* IODELAY_GROUP = \"DDR3_IF_IODELAY_MIG0\" *) \n IDELAYCTRL #(\n .SIM_DEVICE(\"7SERIES\")) \n u_idelayctrl_200\n (.RDY(iodelay_ctrl_rdy),\n .REFCLK(mmcm_clk),\n .RST(rst_ref_0));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_mc\n (accept_ns,\n sent_col,\n bm_end_r1,\n act_wait_r_lcl_reg,\n bm_end_r1_0,\n act_wait_r_lcl_reg_0,\n \\ras_timer_r_reg[2] ,\n act_wait_r_lcl_reg_1,\n bm_end_r1_4,\n act_wait_r_lcl_reg_2,\n app_ref_ack,\n app_zq_ack,\n mc_cmd,\n E,\n tempmon_sample_en,\n mc_ras_n,\n mc_cs_n,\n mc_cke,\n mc_wrdata_en,\n mc_cas_n,\n idle,\n mc_odt,\n app_sr_active,\n Q,\n \\cmd_pipe_plus.mc_bank_reg[2]_0 ,\n \\read_fifo.tail_r_reg[1] ,\n \\rd_ptr_timing_reg[0] ,\n mc_we_n,\n \\rd_ptr_timing_reg[0]_0 ,\n phy_dout,\n \\my_full_reg[3] ,\n \\my_empty_reg[7] ,\n bypass__0,\n \\not_strict_mode.app_rd_data_end_reg ,\n \\cmd_pipe_plus.mc_bank_reg[8]_0 ,\n \\cmd_pipe_plus.mc_bank_reg[8]_1 ,\n pointer_we,\n app_rd_data_end_ns,\n \\write_buffer.wr_buf_out_data_reg[287] ,\n \\rd_ptr_timing_reg[0]_1 ,\n \\phy_ctl_wd_i1_reg[22] ,\n \\phy_ctl_wd_i1_reg[21] ,\n \\phy_ctl_wd_i1_reg[18] ,\n \\phy_ctl_wd_i1_reg[17] ,\n \\phy_ctl_wd_i1_reg[20] ,\n \\phy_ctl_wd_i1_reg[19] ,\n \\data_offset_1_i1_reg[5] ,\n \\data_offset_1_i1_reg[4] ,\n \\data_offset_1_i1_reg[1] ,\n \\data_offset_1_i1_reg[0] ,\n \\data_offset_1_i1_reg[3] ,\n \\data_offset_1_i1_reg[2] ,\n CLK,\n rstdiv0_sync_r1_reg_rep__0,\n hi_priority,\n SR,\n of_ctl_full_v,\n phy_mc_ctl_full,\n maint_prescaler_r1,\n rstdiv0_sync_r1_reg_rep__20,\n rstdiv0_sync_r1_reg_rep__21,\n init_calib_complete_reg_rep__6,\n app_ref_req,\n app_zq_req,\n app_hi_pri_r2,\n use_addr,\n \\app_cmd_r1_reg[0] ,\n app_sr_req,\n rstdiv0_sync_r1_reg_rep__22,\n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ,\n \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ,\n rstdiv0_sync_r1_reg_rep__23,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,\n in0,\n init_calib_complete_reg_rep__7,\n \\req_bank_r_lcl_reg[2] ,\n \\req_bank_r_lcl_reg[2]_0 ,\n \\req_bank_r_lcl_reg[0] ,\n \\req_bank_r_lcl_reg[0]_0 ,\n \\rd_buf_indx.rd_buf_indx_r_reg[4] ,\n \\entry_cnt_reg[2] ,\n \\entry_cnt_reg[2]_0 ,\n bm_end_r1_reg,\n bm_end_r1_reg_0,\n bm_end_r1_reg_1,\n pass_open_bank_r_lcl_reg,\n \\app_cmd_r2_reg[1] ,\n bm_end_r1_reg_2,\n rtp_timer_ns1,\n rtp_timer_ns1_6,\n rtp_timer_ns1_7,\n \\app_addr_r1_reg[27] ,\n ram_init_done_r,\n \\not_strict_mode.status_ram.rd_buf_we_r1_reg ,\n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ,\n \\app_addr_r1_reg[12] ,\n \\app_addr_r1_reg[9] ,\n \\read_fifo.tail_r_reg[0] ,\n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4] ,\n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ,\n \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 ,\n granted_col_r_reg,\n granted_col_r_reg_0,\n \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10] ,\n \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] ,\n \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0 ,\n granted_col_r_reg_1,\n granted_col_r_reg_2);\n output accept_ns;\n output sent_col;\n output bm_end_r1;\n output act_wait_r_lcl_reg;\n output bm_end_r1_0;\n output act_wait_r_lcl_reg_0;\n output \\ras_timer_r_reg[2] ;\n output act_wait_r_lcl_reg_1;\n output bm_end_r1_4;\n output act_wait_r_lcl_reg_2;\n output app_ref_ack;\n output app_zq_ack;\n output [1:0]mc_cmd;\n output [0:0]E;\n output tempmon_sample_en;\n output [2:0]mc_ras_n;\n output [0:0]mc_cs_n;\n output [0:0]mc_cke;\n output mc_wrdata_en;\n output [2:0]mc_cas_n;\n output idle;\n output [0:0]mc_odt;\n output app_sr_active;\n output [2:0]Q;\n output [2:0]\\cmd_pipe_plus.mc_bank_reg[2]_0 ;\n output [0:0]\\read_fifo.tail_r_reg[1] ;\n output [2:0]\\rd_ptr_timing_reg[0] ;\n output [2:0]mc_we_n;\n output [3:0]\\rd_ptr_timing_reg[0]_0 ;\n output [1:0]phy_dout;\n output [37:0]\\my_full_reg[3] ;\n output [1:0]\\my_empty_reg[7] ;\n output bypass__0;\n output [7:0]\\not_strict_mode.app_rd_data_end_reg ;\n output [2:0]\\cmd_pipe_plus.mc_bank_reg[8]_0 ;\n output [2:0]\\cmd_pipe_plus.mc_bank_reg[8]_1 ;\n output pointer_we;\n output app_rd_data_end_ns;\n output [3:0]\\write_buffer.wr_buf_out_data_reg[287] ;\n output [8:0]\\rd_ptr_timing_reg[0]_1 ;\n output \\phy_ctl_wd_i1_reg[22] ;\n output \\phy_ctl_wd_i1_reg[21] ;\n output \\phy_ctl_wd_i1_reg[18] ;\n output \\phy_ctl_wd_i1_reg[17] ;\n output \\phy_ctl_wd_i1_reg[20] ;\n output \\phy_ctl_wd_i1_reg[19] ;\n output \\data_offset_1_i1_reg[5] ;\n output \\data_offset_1_i1_reg[4] ;\n output \\data_offset_1_i1_reg[1] ;\n output \\data_offset_1_i1_reg[0] ;\n output \\data_offset_1_i1_reg[3] ;\n output \\data_offset_1_i1_reg[2] ;\n input CLK;\n input rstdiv0_sync_r1_reg_rep__0;\n input hi_priority;\n input [0:0]SR;\n input [0:0]of_ctl_full_v;\n input phy_mc_ctl_full;\n input maint_prescaler_r1;\n input rstdiv0_sync_r1_reg_rep__20;\n input rstdiv0_sync_r1_reg_rep__21;\n input init_calib_complete_reg_rep__6;\n input app_ref_req;\n input app_zq_req;\n input app_hi_pri_r2;\n input use_addr;\n input \\app_cmd_r1_reg[0] ;\n input app_sr_req;\n input rstdiv0_sync_r1_reg_rep__22;\n input [5:0]\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ;\n input [5:0]\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ;\n input rstdiv0_sync_r1_reg_rep__23;\n input \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n input in0;\n input init_calib_complete_reg_rep__7;\n input \\req_bank_r_lcl_reg[2] ;\n input \\req_bank_r_lcl_reg[2]_0 ;\n input \\req_bank_r_lcl_reg[0] ;\n input \\req_bank_r_lcl_reg[0]_0 ;\n input [4:0]\\rd_buf_indx.rd_buf_indx_r_reg[4] ;\n input \\entry_cnt_reg[2] ;\n input \\entry_cnt_reg[2]_0 ;\n input bm_end_r1_reg;\n input bm_end_r1_reg_0;\n input bm_end_r1_reg_1;\n input pass_open_bank_r_lcl_reg;\n input [0:0]\\app_cmd_r2_reg[1] ;\n input bm_end_r1_reg_2;\n input rtp_timer_ns1;\n input rtp_timer_ns1_6;\n input rtp_timer_ns1_7;\n input [14:0]\\app_addr_r1_reg[27] ;\n input ram_init_done_r;\n input [0:0]\\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n input [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n input [2:0]\\app_addr_r1_reg[12] ;\n input [6:0]\\app_addr_r1_reg[9] ;\n input \\read_fifo.tail_r_reg[0] ;\n input \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4] ;\n input \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ;\n input \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 ;\n input granted_col_r_reg;\n input granted_col_r_reg_0;\n input \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10] ;\n input \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] ;\n input \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0 ;\n input granted_col_r_reg_1;\n input granted_col_r_reg_2;\n\n wire CLK;\n wire [0:0]E;\n wire [2:0]Q;\n wire [0:0]SR;\n wire accept_internal_r;\n wire accept_ns;\n wire act_wait_r_lcl_reg;\n wire act_wait_r_lcl_reg_0;\n wire act_wait_r_lcl_reg_1;\n wire act_wait_r_lcl_reg_2;\n wire [2:0]\\app_addr_r1_reg[12] ;\n wire [14:0]\\app_addr_r1_reg[27] ;\n wire [6:0]\\app_addr_r1_reg[9] ;\n wire \\app_cmd_r1_reg[0] ;\n wire [0:0]\\app_cmd_r2_reg[1] ;\n wire app_hi_pri_r2;\n wire app_rd_data_end_ns;\n wire app_ref_ack;\n wire app_ref_req;\n wire app_sr_active;\n wire app_sr_req;\n wire app_zq_ack;\n wire app_zq_req;\n wire [3:3]\\arb_mux0/arb_row_col0/pre_4_1_1T_arb.pre_arb0/last_master_r ;\n wire [3:3]\\arb_mux0/arb_row_col0/row_arb0/last_master_r ;\n wire \\arb_mux0/arb_select0/cke_r ;\n wire \\arb_mux0/cs_en2 ;\n wire \\bank_cntrl[0].bank0/auto_pre_r ;\n wire \\bank_cntrl[0].bank0/bank_queue0/pre_bm_end_r ;\n wire \\bank_cntrl[0].bank0/bank_state0/col_wait_r ;\n wire \\bank_cntrl[0].bank0/bank_state0/demand_priority_r ;\n wire \\bank_cntrl[0].bank0/bank_state0/demanded_prior_r ;\n wire \\bank_cntrl[0].bank0/bank_state0/ras_timer_zero_r ;\n wire \\bank_cntrl[0].bank0/q_has_priority ;\n wire \\bank_cntrl[0].bank0/q_has_rd ;\n wire [1:1]\\bank_cntrl[0].bank0/rb_hit_busies_r ;\n wire \\bank_cntrl[0].bank0/row_hit_r ;\n wire \\bank_cntrl[0].bank0/tail_r ;\n wire \\bank_cntrl[0].bank0/wait_for_maint_r ;\n wire \\bank_cntrl[1].bank0/auto_pre_r ;\n wire \\bank_cntrl[1].bank0/bank_queue0/pre_bm_end_r ;\n wire \\bank_cntrl[1].bank0/bank_state0/col_wait_r ;\n wire \\bank_cntrl[1].bank0/bank_state0/demand_priority_r ;\n wire [1:0]\\bank_cntrl[1].bank0/bank_state0/rtp_timer_r ;\n wire \\bank_cntrl[1].bank0/q_has_priority ;\n wire \\bank_cntrl[1].bank0/q_has_rd ;\n wire [3:3]\\bank_cntrl[1].bank0/rb_hit_busies_r ;\n wire \\bank_cntrl[1].bank0/row_hit_r ;\n wire \\bank_cntrl[1].bank0/tail_r ;\n wire \\bank_cntrl[1].bank0/wait_for_maint_r ;\n wire \\bank_cntrl[2].bank0/auto_pre_r ;\n wire \\bank_cntrl[2].bank0/bank_queue0/pre_bm_end_r ;\n wire \\bank_cntrl[2].bank0/bank_state0/col_wait_r ;\n wire \\bank_cntrl[2].bank0/bank_state0/demand_priority_r ;\n wire \\bank_cntrl[2].bank0/bank_state0/demanded_prior_r ;\n wire \\bank_cntrl[2].bank0/bank_state0/override_demand_r ;\n wire \\bank_cntrl[2].bank0/bank_state0/ras_timer_zero_r ;\n wire [1:0]\\bank_cntrl[2].bank0/q_entry_r ;\n wire \\bank_cntrl[2].bank0/q_has_priority ;\n wire \\bank_cntrl[2].bank0/q_has_rd ;\n wire [5:5]\\bank_cntrl[2].bank0/rb_hit_busies_r ;\n wire \\bank_cntrl[2].bank0/row_hit_r ;\n wire \\bank_cntrl[2].bank0/tail_r ;\n wire \\bank_cntrl[2].bank0/wait_for_maint_r ;\n wire \\bank_cntrl[3].bank0/auto_pre_r ;\n wire \\bank_cntrl[3].bank0/bank_queue0/pre_bm_end_r ;\n wire \\bank_cntrl[3].bank0/bank_state0/col_wait_r ;\n wire \\bank_cntrl[3].bank0/bank_state0/demand_priority_r ;\n wire \\bank_cntrl[3].bank0/bank_state0/demanded_prior_r ;\n wire [1:0]\\bank_cntrl[3].bank0/q_entry_r ;\n wire \\bank_cntrl[3].bank0/q_has_priority ;\n wire \\bank_cntrl[3].bank0/q_has_rd ;\n wire [5:5]\\bank_cntrl[3].bank0/rb_hit_busies_r ;\n wire \\bank_cntrl[3].bank0/row_hit_r ;\n wire \\bank_cntrl[3].bank0/tail_r ;\n wire \\bank_cntrl[3].bank0/wait_for_maint_r ;\n wire [3:0]\\bank_common0/maint_hit_busies_r ;\n wire \\bank_common0/periodic_rd_cntr_r ;\n wire [0:0]\\bank_common0/rfc_zq_xsdll_timer_ns ;\n wire [4:0]\\bank_common0/rfc_zq_xsdll_timer_r ;\n wire bank_mach0_n_100;\n wire bank_mach0_n_105;\n wire bank_mach0_n_106;\n wire bank_mach0_n_108;\n wire bank_mach0_n_109;\n wire bank_mach0_n_111;\n wire bank_mach0_n_113;\n wire bank_mach0_n_115;\n wire bank_mach0_n_116;\n wire bank_mach0_n_118;\n wire bank_mach0_n_121;\n wire bank_mach0_n_122;\n wire bank_mach0_n_126;\n wire bank_mach0_n_127;\n wire bank_mach0_n_128;\n wire bank_mach0_n_129;\n wire bank_mach0_n_130;\n wire bank_mach0_n_131;\n wire bank_mach0_n_132;\n wire bank_mach0_n_135;\n wire bank_mach0_n_136;\n wire bank_mach0_n_137;\n wire bank_mach0_n_138;\n wire bank_mach0_n_141;\n wire bank_mach0_n_144;\n wire bank_mach0_n_145;\n wire bank_mach0_n_146;\n wire bank_mach0_n_147;\n wire bank_mach0_n_148;\n wire bank_mach0_n_149;\n wire bank_mach0_n_150;\n wire bank_mach0_n_151;\n wire bank_mach0_n_152;\n wire bank_mach0_n_153;\n wire bank_mach0_n_154;\n wire bank_mach0_n_155;\n wire bank_mach0_n_156;\n wire bank_mach0_n_157;\n wire bank_mach0_n_158;\n wire bank_mach0_n_159;\n wire bank_mach0_n_160;\n wire bank_mach0_n_161;\n wire bank_mach0_n_162;\n wire bank_mach0_n_2;\n wire bank_mach0_n_259;\n wire bank_mach0_n_265;\n wire bank_mach0_n_266;\n wire bank_mach0_n_267;\n wire bank_mach0_n_268;\n wire bank_mach0_n_269;\n wire bank_mach0_n_275;\n wire bank_mach0_n_276;\n wire bank_mach0_n_278;\n wire bank_mach0_n_279;\n wire bank_mach0_n_280;\n wire bank_mach0_n_281;\n wire bank_mach0_n_282;\n wire bank_mach0_n_283;\n wire bank_mach0_n_284;\n wire bank_mach0_n_98;\n wire bank_mach0_n_99;\n wire bm_end_r1;\n wire bm_end_r1_0;\n wire bm_end_r1_4;\n wire bm_end_r1_reg;\n wire bm_end_r1_reg_0;\n wire bm_end_r1_reg_1;\n wire bm_end_r1_reg_2;\n wire bypass__0;\n wire clear_periodic_rd_request;\n wire [2:0]\\cmd_pipe_plus.mc_bank_reg[2]_0 ;\n wire [2:0]\\cmd_pipe_plus.mc_bank_reg[8]_0 ;\n wire [2:0]\\cmd_pipe_plus.mc_bank_reg[8]_1 ;\n wire \\cmd_pipe_plus.mc_data_offset_2_reg_n_0_[3] ;\n wire [4:0]col_data_buf_addr;\n wire col_mach0_n_16;\n wire col_mach0_n_21;\n wire col_periodic_rd;\n wire col_rd_wr;\n wire col_rd_wr_r1;\n wire col_rd_wr_r2;\n wire [3:0]col_wr_data_buf_addr_r;\n wire \\data_offset_1_i1_reg[0] ;\n wire \\data_offset_1_i1_reg[1] ;\n wire \\data_offset_1_i1_reg[2] ;\n wire \\data_offset_1_i1_reg[3] ;\n wire \\data_offset_1_i1_reg[4] ;\n wire \\data_offset_1_i1_reg[5] ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n wire \\entry_cnt_reg[2] ;\n wire \\entry_cnt_reg[2]_0 ;\n wire [2:0]faw_cnt_r;\n wire granted_col_r_reg;\n wire granted_col_r_reg_0;\n wire granted_col_r_reg_1;\n wire granted_col_r_reg_2;\n wire [3:0]head_r;\n wire hi_priority;\n wire i___0_n_0;\n wire i___100_n_0;\n wire i___101_n_0;\n wire i___102_n_0;\n wire i___103_n_0;\n wire i___104_n_0;\n wire i___105_n_0;\n wire i___106_n_0;\n wire i___107_n_0;\n wire i___108_n_0;\n wire i___109_n_0;\n wire i___10_n_0;\n wire i___110_n_0;\n wire i___111_n_0;\n wire i___112_n_0;\n wire i___113_n_0;\n wire i___114_n_0;\n wire i___115_n_0;\n wire i___116_n_0;\n wire i___117_n_0;\n wire i___118_n_0;\n wire i___119_n_0;\n wire i___11_n_0;\n wire i___120_n_0;\n wire i___12_n_0;\n wire i___13_n_0;\n wire i___14_n_0;\n wire i___15_n_0;\n wire i___16_n_0;\n wire i___17_n_0;\n wire i___18_n_0;\n wire i___19_n_0;\n wire i___1_n_0;\n wire i___20_n_0;\n wire i___21_n_0;\n wire i___22_n_0;\n wire i___23_n_0;\n wire i___24_n_0;\n wire i___25_n_0;\n wire i___26_n_0;\n wire i___27_n_0;\n wire i___28_n_0;\n wire i___29_n_0;\n wire i___2_n_0;\n wire i___30_n_0;\n wire i___31_n_0;\n wire i___32_n_0;\n wire i___33_n_0;\n wire i___34_n_0;\n wire i___35_n_0;\n wire i___36_n_0;\n wire i___37_n_0;\n wire i___38_n_0;\n wire i___39_n_0;\n wire i___3_n_0;\n wire i___40_n_0;\n wire i___41_n_0;\n wire i___42_n_0;\n wire i___43_n_0;\n wire i___44_n_0;\n wire i___45_n_0;\n wire i___46_n_0;\n wire i___47_n_0;\n wire i___48_n_0;\n wire i___49_n_0;\n wire i___4_n_0;\n wire i___50_n_0;\n wire i___51_n_0;\n wire i___52_n_0;\n wire i___53_n_0;\n wire i___54_n_0;\n wire i___55_n_0;\n wire i___56_n_0;\n wire i___57_n_0;\n wire i___58_n_0;\n wire i___59_n_0;\n wire i___5_n_0;\n wire i___60_n_0;\n wire i___61_n_0;\n wire i___62_n_0;\n wire i___63_n_0;\n wire i___64_n_0;\n wire i___65_n_0;\n wire i___66_n_0;\n wire i___67_n_0;\n wire i___68_n_0;\n wire i___69_n_0;\n wire i___6_n_0;\n wire i___70_n_0;\n wire i___71_n_0;\n wire i___72_n_0;\n wire i___73_n_0;\n wire i___74_n_0;\n wire i___75_n_0;\n wire i___76_n_0;\n wire i___77_n_0;\n wire i___78_n_0;\n wire i___79_n_0;\n wire i___7_n_0;\n wire i___80_n_0;\n wire i___81_n_0;\n wire i___82_n_0;\n wire i___83_n_0;\n wire i___84_n_0;\n wire i___85_n_0;\n wire i___86_n_0;\n wire i___87_n_0;\n wire i___88_n_0;\n wire i___89_n_0;\n wire i___8_n_0;\n wire i___90_n_0;\n wire i___91_n_0;\n wire i___92_n_0;\n wire i___93_n_0;\n wire i___94_n_0;\n wire i___95_n_0;\n wire i___96_n_0;\n wire i___97_n_0;\n wire i___98_n_0;\n wire i___99_n_0;\n wire i___9_n_0;\n wire idle;\n wire [3:0]idle_r;\n wire in0;\n wire inhbt_act_faw_r;\n wire init_calib_complete_reg_rep__6;\n wire init_calib_complete_reg_rep__7;\n wire insert_maint_r;\n wire insert_maint_r1;\n wire maint_prescaler_r1;\n wire maint_ref_zq_wip;\n wire maint_req_r;\n wire maint_sre_r;\n wire maint_srx_r;\n wire maint_wip_r;\n wire maint_zq_r;\n wire [44:0]mc_address_ns;\n wire [8:0]mc_bank_ns;\n wire [2:0]mc_cas_n;\n wire [1:0]mc_cas_n_ns;\n wire [0:0]mc_cke;\n wire [1:1]mc_cke_ns;\n wire [1:0]mc_cmd;\n wire [1:1]mc_cmd_ns;\n wire [0:0]mc_cs_n;\n wire [0:0]mc_cs_n_ns;\n wire [0:0]mc_odt;\n wire [2:0]mc_ras_n;\n wire [2:0]mc_ras_n_ns;\n wire mc_ref_zq_wip_ns;\n wire [2:0]mc_we_n;\n wire [2:0]mc_we_n_ns;\n wire mc_wrdata_en;\n wire [1:0]\\my_empty_reg[7] ;\n wire [37:0]\\my_full_reg[3] ;\n wire [7:0]\\not_strict_mode.app_rd_data_end_reg ;\n wire [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n wire [0:0]\\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n wire [0:0]of_ctl_full_v;\n wire [3:0]ordered_r;\n wire pass_open_bank_r_lcl_reg;\n wire periodic_rd_ack_r;\n wire periodic_rd_r;\n wire \\phy_ctl_wd_i1_reg[17] ;\n wire \\phy_ctl_wd_i1_reg[18] ;\n wire \\phy_ctl_wd_i1_reg[19] ;\n wire \\phy_ctl_wd_i1_reg[20] ;\n wire \\phy_ctl_wd_i1_reg[21] ;\n wire \\phy_ctl_wd_i1_reg[22] ;\n wire [1:0]phy_dout;\n wire phy_mc_ctl_full;\n wire pointer_we;\n wire ram_init_done_r;\n wire \\rank_cntrl[0].rank_cntrl0/act_delayed ;\n wire \\rank_cntrl[0].rank_cntrl0/act_this_rank ;\n wire \\rank_cntrl[0].rank_cntrl0/periodic_rd_cntr1_r ;\n wire \\rank_cntrl[0].rank_cntrl0/periodic_rd_request_r ;\n wire \\rank_cntrl[0].rank_cntrl0/read_this_rank ;\n wire \\rank_cntrl[0].rank_cntrl0/read_this_rank_r ;\n wire \\rank_cntrl[0].rank_cntrl0/refresh_bank_r ;\n wire \\rank_common0/app_ref_r ;\n wire \\rank_common0/app_zq_r ;\n wire [2:0]\\rank_common0/maint_grant_r ;\n wire [1:0]\\rank_common0/maint_prescaler.maint_prescaler_r_reg__0 ;\n wire \\rank_common0/maint_prescaler_tick_ns ;\n wire [2:0]\\rank_common0/maintenance_request.maint_arb0/last_master_r ;\n wire \\rank_common0/new_maint_rank_r ;\n wire \\rank_common0/periodic_rd_grant_r ;\n wire \\rank_common0/periodic_rd_r_cnt ;\n wire [1:0]\\rank_common0/refresh_timer.refresh_timer_r_reg__0 ;\n wire \\rank_common0/sre_request_r ;\n wire \\rank_common0/upd_last_master_r ;\n wire \\rank_common0/zq_request_r ;\n wire \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ;\n wire \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 ;\n wire \\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4] ;\n wire [5:0]\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ;\n wire \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10] ;\n wire [5:0]\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ;\n wire \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] ;\n wire \\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0 ;\n wire rank_mach0_n_27;\n wire rank_mach0_n_30;\n wire rank_mach0_n_34;\n wire rank_mach0_n_40;\n wire rank_mach0_n_42;\n wire rank_mach0_n_43;\n wire rank_mach0_n_44;\n wire rank_mach0_n_45;\n wire rank_mach0_n_46;\n wire rank_mach0_n_47;\n wire rank_mach0_n_48;\n wire rank_mach0_n_49;\n wire rank_mach0_n_5;\n wire rank_mach0_n_50;\n wire rank_mach0_n_51;\n wire rank_mach0_n_52;\n wire rank_mach0_n_53;\n wire rank_mach0_n_54;\n wire rank_mach0_n_55;\n wire rank_mach0_n_56;\n wire rank_mach0_n_57;\n wire rank_mach0_n_58;\n wire rank_mach0_n_59;\n wire rank_mach0_n_60;\n wire rank_mach0_n_61;\n wire rank_mach0_n_62;\n wire rank_mach0_n_63;\n wire rank_mach0_n_64;\n wire rank_mach0_n_71;\n wire \\ras_timer_r_reg[2] ;\n wire [3:0]rb_hit_busy_r;\n wire [4:0]\\rd_buf_indx.rd_buf_indx_r_reg[4] ;\n wire [2:0]\\rd_ptr_timing_reg[0] ;\n wire [3:0]\\rd_ptr_timing_reg[0]_0 ;\n wire [8:0]\\rd_ptr_timing_reg[0]_1 ;\n wire [3:0]rd_wr_r;\n wire \\read_fifo.tail_r_reg[0] ;\n wire [0:0]\\read_fifo.tail_r_reg[1] ;\n wire \\req_bank_r_lcl_reg[0] ;\n wire \\req_bank_r_lcl_reg[0]_0 ;\n wire \\req_bank_r_lcl_reg[2] ;\n wire \\req_bank_r_lcl_reg[2]_0 ;\n wire [55:0]req_row_r;\n wire [3:0]req_wr_r;\n wire rnk_config_valid_r;\n wire [3:0]row_cmd_wr;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire rstdiv0_sync_r1_reg_rep__22;\n wire rstdiv0_sync_r1_reg_rep__23;\n wire rtp_timer_ns1;\n wire rtp_timer_ns1_6;\n wire rtp_timer_ns1_7;\n wire [1:1]rtw_cnt_r;\n wire [3:0]sending_col;\n wire [3:0]sending_pre;\n wire [3:1]sending_row;\n wire sent_col;\n wire sent_col_r2;\n wire sent_row;\n wire [2:1]tail_r;\n wire tempmon_sample_en;\n wire use_addr;\n wire was_wr;\n wire [3:0]\\write_buffer.wr_buf_out_data_reg[287] ;\n wire [2:0]wtr_cnt_r;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_0 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_1 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_2 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_3 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_4 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_5 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_6 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_7 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_0 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_1 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_2 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_3 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_4 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_5 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_6 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_7 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_1 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_2 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_3 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_4 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_5 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_6 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_7 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_0 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_1 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_2 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_3 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_4 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_5 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_6 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_7 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_0 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_1 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_2 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_3 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_4 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_5 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_6 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_7 ;\n wire [3:3]\\NLW_zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_CO_UNCONNECTED ;\n\n ddr3_if_mig_7series_v4_0_bank_mach bank_mach0\n (.CLK(CLK),\n .D({i___53_n_0,i___50_n_0,i___40_n_0,i___55_n_0}),\n .DIC(col_periodic_rd),\n .E(mc_cmd_ns),\n .Q(sending_col),\n .SR(SR),\n .accept_internal_r(accept_internal_r),\n .accept_internal_r_reg(bank_mach0_n_106),\n .accept_ns(accept_ns),\n .accept_r_reg(i___75_n_0),\n .accept_r_reg_0(i___76_n_0),\n .act_this_rank(\\rank_cntrl[0].rank_cntrl0/act_this_rank ),\n .\\act_this_rank_r_reg[0] ({row_cmd_wr[3:2],row_cmd_wr[0]}),\n .act_wait_r_lcl_reg(act_wait_r_lcl_reg),\n .act_wait_r_lcl_reg_0(act_wait_r_lcl_reg_0),\n .act_wait_r_lcl_reg_1(act_wait_r_lcl_reg_1),\n .act_wait_r_lcl_reg_2(act_wait_r_lcl_reg_2),\n .act_wait_r_lcl_reg_3(i___113_n_0),\n .\\app_addr_r1_reg[12] (\\app_addr_r1_reg[12] ),\n .\\app_addr_r1_reg[27] (\\app_addr_r1_reg[27] ),\n .\\app_addr_r1_reg[9] (\\app_addr_r1_reg[9] ),\n .\\app_cmd_r1_reg[0] (\\app_cmd_r1_reg[0] ),\n .\\app_cmd_r2_reg[1] (\\app_cmd_r2_reg[1] ),\n .auto_pre_r(\\bank_cntrl[0].bank0/auto_pre_r ),\n .auto_pre_r_25(\\bank_cntrl[1].bank0/auto_pre_r ),\n .auto_pre_r_27(\\bank_cntrl[2].bank0/auto_pre_r ),\n .auto_pre_r_29(\\bank_cntrl[3].bank0/auto_pre_r ),\n .auto_pre_r_lcl_reg(bank_mach0_n_265),\n .auto_pre_r_lcl_reg_0(bank_mach0_n_266),\n .auto_pre_r_lcl_reg_1(bank_mach0_n_268),\n .auto_pre_r_lcl_reg_2(bank_mach0_n_269),\n .auto_pre_r_lcl_reg_3(i___2_n_0),\n .auto_pre_r_lcl_reg_4(i___7_n_0),\n .auto_pre_r_lcl_reg_5(i___11_n_0),\n .auto_pre_r_lcl_reg_6(i___15_n_0),\n .bm_end_r1(bm_end_r1),\n .bm_end_r1_0(bm_end_r1_0),\n .bm_end_r1_4(bm_end_r1_4),\n .bm_end_r1_reg(bm_end_r1_reg),\n .bm_end_r1_reg_0(bm_end_r1_reg_0),\n .bm_end_r1_reg_1(bm_end_r1_reg_1),\n .bm_end_r1_reg_2(bm_end_r1_reg_2),\n .cke_r(\\arb_mux0/arb_select0/cke_r ),\n .clear_periodic_rd_request(clear_periodic_rd_request),\n .\\cmd_pipe_plus.mc_address_reg[10] ({req_row_r[55],req_row_r[29:26],req_row_r[24:11],req_row_r[9:0]}),\n .\\cmd_pipe_plus.mc_address_reg[44] ({mc_address_ns[44:30],mc_address_ns[25:18],mc_address_ns[14:0]}),\n .\\cmd_pipe_plus.mc_bank_reg[2] (Q),\n .\\cmd_pipe_plus.mc_bank_reg[2]_0 (\\cmd_pipe_plus.mc_bank_reg[2]_0 ),\n .\\cmd_pipe_plus.mc_bank_reg[7] (sending_pre),\n .\\cmd_pipe_plus.mc_bank_reg[8] (mc_bank_ns),\n .\\cmd_pipe_plus.mc_bank_reg[8]_0 (\\cmd_pipe_plus.mc_bank_reg[8]_0 ),\n .\\cmd_pipe_plus.mc_bank_reg[8]_1 (\\cmd_pipe_plus.mc_bank_reg[8]_1 ),\n .\\cmd_pipe_plus.mc_cmd_reg[0] (sent_col),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[0] (bank_mach0_n_98),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 (bank_mach0_n_99),\n .\\cmd_pipe_plus.mc_we_n_reg[1] (bank_mach0_n_284),\n .col_data_buf_addr(col_data_buf_addr),\n .col_rd_wr(col_rd_wr),\n .col_wait_r(\\bank_cntrl[0].bank0/bank_state0/col_wait_r ),\n .col_wait_r_21(\\bank_cntrl[1].bank0/bank_state0/col_wait_r ),\n .col_wait_r_22(\\bank_cntrl[2].bank0/bank_state0/col_wait_r ),\n .col_wait_r_23(\\bank_cntrl[3].bank0/bank_state0/col_wait_r ),\n .col_wait_r_reg(i___38_n_0),\n .col_wait_r_reg_0(i___56_n_0),\n .col_wait_r_reg_1(i___36_n_0),\n .col_wait_r_reg_2(i___37_n_0),\n .\\compute_tail.tail_r_lcl_reg (bank_mach0_n_157),\n .cs_en2(\\arb_mux0/cs_en2 ),\n .\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] (col_wr_data_buf_addr_r),\n .demand_priority_r(\\bank_cntrl[0].bank0/bank_state0/demand_priority_r ),\n .demand_priority_r_1(\\bank_cntrl[1].bank0/bank_state0/demand_priority_r ),\n .demand_priority_r_13(\\bank_cntrl[3].bank0/bank_state0/demand_priority_r ),\n .demand_priority_r_7(\\bank_cntrl[2].bank0/bank_state0/demand_priority_r ),\n .demanded_prior_r(\\bank_cntrl[0].bank0/bank_state0/demanded_prior_r ),\n .demanded_prior_r_14(\\bank_cntrl[3].bank0/bank_state0/demanded_prior_r ),\n .demanded_prior_r_8(\\bank_cntrl[2].bank0/bank_state0/demanded_prior_r ),\n .demanded_prior_r_reg(bank_mach0_n_276),\n .demanded_prior_r_reg_0(bank_mach0_n_283),\n .\\entry_cnt_reg[2] (\\entry_cnt_reg[2] ),\n .\\entry_cnt_reg[2]_0 (\\entry_cnt_reg[2]_0 ),\n .\\generate_maint_cmds.insert_maint_r_lcl_reg (rank_mach0_n_40),\n .\\grant_r_reg[0] (i___111_n_0),\n .\\grant_r_reg[0]_0 (i___110_n_0),\n .\\grant_r_reg[0]_1 (i___109_n_0),\n .\\grant_r_reg[0]_10 (i___100_n_0),\n .\\grant_r_reg[0]_11 (i___99_n_0),\n .\\grant_r_reg[0]_12 (i___98_n_0),\n .\\grant_r_reg[0]_2 (i___108_n_0),\n .\\grant_r_reg[0]_3 (i___107_n_0),\n .\\grant_r_reg[0]_4 (i___106_n_0),\n .\\grant_r_reg[0]_5 (i___105_n_0),\n .\\grant_r_reg[0]_6 (i___104_n_0),\n .\\grant_r_reg[0]_7 (i___103_n_0),\n .\\grant_r_reg[0]_8 (i___102_n_0),\n .\\grant_r_reg[0]_9 (i___101_n_0),\n .\\grant_r_reg[1] (bank_mach0_n_158),\n .\\grant_r_reg[1]_0 (bank_mach0_n_160),\n .\\grant_r_reg[1]_1 (bank_mach0_n_275),\n .\\grant_r_reg[2] (bank_mach0_n_154),\n .\\grant_r_reg[3] (bank_mach0_n_161),\n .\\grant_r_reg[3]_0 (bank_mach0_n_259),\n .granted_row_r_reg(i___71_n_0),\n .granted_row_r_reg_0(i___70_n_0),\n .head_r(head_r),\n .head_r_lcl_reg(bank_mach0_n_135),\n .head_r_lcl_reg_0(bank_mach0_n_144),\n .head_r_lcl_reg_1(bank_mach0_n_148),\n .head_r_lcl_reg_2(bank_mach0_n_149),\n .head_r_lcl_reg_3(bank_mach0_n_152),\n .head_r_lcl_reg_4(bank_mach0_n_153),\n .head_r_lcl_reg_5(bank_mach0_n_267),\n .head_r_lcl_reg_6(i___1_n_0),\n .head_r_lcl_reg_7(i___6_n_0),\n .head_r_lcl_reg_8(i___10_n_0),\n .head_r_lcl_reg_9(i___14_n_0),\n .hi_priority(hi_priority),\n .idle_r(idle_r),\n .idle_r_lcl_reg(i___0_n_0),\n .idle_r_lcl_reg_0(i___5_n_0),\n .idle_r_lcl_reg_1(i___9_n_0),\n .idle_r_lcl_reg_2(i___13_n_0),\n .idle_r_lcl_reg_3(i___92_n_0),\n .idle_r_lcl_reg_4(i___91_n_0),\n .idle_r_lcl_reg_5(i___57_n_0),\n .idle_r_lcl_reg_6(i___39_n_0),\n .idle_r_lcl_reg_7(i___52_n_0),\n .\\inhbt_act_faw.inhbt_act_faw_r_reg (bank_mach0_n_278),\n .inhbt_act_faw_r(inhbt_act_faw_r),\n .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6),\n .insert_maint_r(insert_maint_r),\n .insert_maint_r1(insert_maint_r1),\n .\\last_master_r_reg[3] (sending_row),\n .\\last_master_r_reg[3]_0 (\\arb_mux0/arb_row_col0/row_arb0/last_master_r ),\n .\\last_master_r_reg[3]_1 (\\arb_mux0/arb_row_col0/pre_4_1_1T_arb.pre_arb0/last_master_r ),\n .\\last_master_r_reg[3]_2 (i___78_n_0),\n .\\last_master_r_reg[3]_3 (i___79_n_0),\n .\\maint_controller.maint_hit_busies_r_reg[3] (\\bank_common0/maint_hit_busies_r ),\n .\\maint_controller.maint_rdy_r1_reg (bank_mach0_n_141),\n .maint_req_r(maint_req_r),\n .maint_srx_r(maint_srx_r),\n .maint_wip_r(maint_wip_r),\n .maint_zq_r(maint_zq_r),\n .\\maintenance_request.maint_req_r_lcl_reg (i___77_n_0),\n .\\maintenance_request.maint_zq_r_lcl_reg (rank_mach0_n_42),\n .mc_cas_n_ns(mc_cas_n_ns),\n .mc_cke_ns(mc_cke_ns),\n .mc_cs_n_ns(mc_cs_n_ns),\n .mc_ras_n_ns({mc_ras_n_ns[2],mc_ras_n_ns[0]}),\n .mc_we_n_ns({mc_we_n_ns[2],mc_we_n_ns[0]}),\n .\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),\n .of_ctl_full_v(of_ctl_full_v),\n .ordered_r(ordered_r),\n .ordered_r_lcl_reg(bank_mach0_n_132),\n .ordered_r_lcl_reg_0(bank_mach0_n_138),\n .ordered_r_lcl_reg_1(bank_mach0_n_147),\n .ordered_r_lcl_reg_2(i___3_n_0),\n .ordered_r_lcl_reg_3(i___8_n_0),\n .ordered_r_lcl_reg_4(i___12_n_0),\n .ordered_r_lcl_reg_5(i___16_n_0),\n .override_demand_r(\\bank_cntrl[2].bank0/bank_state0/override_demand_r ),\n .override_demand_r_reg(i___90_n_0),\n .override_demand_r_reg_0(i___89_n_0),\n .override_demand_r_reg_1(i___88_n_0),\n .pass_open_bank_r_lcl_reg(bank_mach0_n_159),\n .pass_open_bank_r_lcl_reg_0(bank_mach0_n_162),\n .pass_open_bank_r_lcl_reg_1(pass_open_bank_r_lcl_reg),\n .pass_open_bank_r_lcl_reg_2(i___4_n_0),\n .periodic_rd_ack_r(periodic_rd_ack_r),\n .periodic_rd_ack_r_lcl_reg(i___69_n_0),\n .periodic_rd_cntr_r(\\bank_common0/periodic_rd_cntr_r ),\n .\\periodic_rd_generation.periodic_rd_timer_r_reg[2] (bank_mach0_n_118),\n .periodic_rd_grant_r(\\rank_common0/periodic_rd_grant_r ),\n .periodic_rd_r(periodic_rd_r),\n .\\periodic_read_request.periodic_rd_r_lcl_reg (i___68_n_0),\n .phy_mc_ctl_full(phy_mc_ctl_full),\n .pre_bm_end_r(\\bank_cntrl[0].bank0/bank_queue0/pre_bm_end_r ),\n .pre_bm_end_r_15(\\bank_cntrl[3].bank0/bank_queue0/pre_bm_end_r ),\n .pre_bm_end_r_2(\\bank_cntrl[1].bank0/bank_queue0/pre_bm_end_r ),\n .pre_bm_end_r_9(\\bank_cntrl[2].bank0/bank_queue0/pre_bm_end_r ),\n .q_entry_r(\\bank_cntrl[2].bank0/q_entry_r ),\n .q_entry_r_30(\\bank_cntrl[3].bank0/q_entry_r ),\n .\\q_entry_r_reg[0] (bank_mach0_n_108),\n .\\q_entry_r_reg[0]_0 (bank_mach0_n_116),\n .\\q_entry_r_reg[0]_1 (bank_mach0_n_151),\n .\\q_entry_r_reg[1] (bank_mach0_n_2),\n .\\q_entry_r_reg[1]_0 (bank_mach0_n_113),\n .\\q_entry_r_reg[1]_1 (bank_mach0_n_115),\n .\\q_entry_r_reg[1]_2 (bank_mach0_n_136),\n .\\q_entry_r_reg[1]_3 (bank_mach0_n_137),\n .\\q_entry_r_reg[1]_4 (bank_mach0_n_145),\n .\\q_entry_r_reg[1]_5 (bank_mach0_n_146),\n .\\q_entry_r_reg[1]_6 (bank_mach0_n_150),\n .q_has_priority(\\bank_cntrl[0].bank0/q_has_priority ),\n .q_has_priority_11(\\bank_cntrl[2].bank0/q_has_priority ),\n .q_has_priority_17(\\bank_cntrl[3].bank0/q_has_priority ),\n .q_has_priority_4(\\bank_cntrl[1].bank0/q_has_priority ),\n .q_has_priority_r_reg(i___59_n_0),\n .q_has_priority_r_reg_0(i___42_n_0),\n .q_has_priority_r_reg_1(i___65_n_0),\n .q_has_priority_r_reg_2(i___62_n_0),\n .q_has_rd(\\bank_cntrl[0].bank0/q_has_rd ),\n .q_has_rd_10(\\bank_cntrl[2].bank0/q_has_rd ),\n .q_has_rd_16(\\bank_cntrl[3].bank0/q_has_rd ),\n .q_has_rd_3(\\bank_cntrl[1].bank0/q_has_rd ),\n .q_has_rd_r_reg(i___58_n_0),\n .q_has_rd_r_reg_0(i___41_n_0),\n .q_has_rd_r_reg_1(i___64_n_0),\n .q_has_rd_r_reg_2(i___61_n_0),\n .\\ras_timer_r_reg[0] (bank_mach0_n_126),\n .\\ras_timer_r_reg[0]_0 (bank_mach0_n_127),\n .\\ras_timer_r_reg[0]_1 (bank_mach0_n_128),\n .\\ras_timer_r_reg[0]_2 (bank_mach0_n_129),\n .\\ras_timer_r_reg[0]_3 (bank_mach0_n_130),\n .\\ras_timer_r_reg[0]_4 (bank_mach0_n_131),\n .\\ras_timer_r_reg[0]_5 (bank_mach0_n_155),\n .\\ras_timer_r_reg[0]_6 (bank_mach0_n_156),\n .\\ras_timer_r_reg[2] (\\ras_timer_r_reg[2] ),\n .ras_timer_zero_r(\\bank_cntrl[0].bank0/bank_state0/ras_timer_zero_r ),\n .ras_timer_zero_r_6(\\bank_cntrl[2].bank0/bank_state0/ras_timer_zero_r ),\n .ras_timer_zero_r_reg(i___74_n_0),\n .ras_timer_zero_r_reg_0(i___73_n_0),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] (\\bank_cntrl[0].bank0/rb_hit_busies_r ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] (\\bank_cntrl[1].bank0/rb_hit_busies_r ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] (\\bank_cntrl[2].bank0/rb_hit_busies_r ),\n .\\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 (\\bank_cntrl[3].bank0/rb_hit_busies_r ),\n .rb_hit_busy_r(rb_hit_busy_r),\n .rb_hit_busy_r_reg(bank_mach0_n_105),\n .rb_hit_busy_r_reg_0(bank_mach0_n_109),\n .rb_hit_busy_r_reg_1(bank_mach0_n_111),\n .rb_hit_busy_r_reg_2(i___44_n_0),\n .rd_wr_r(rd_wr_r),\n .rd_wr_r_lcl_reg(i___33_n_0),\n .read_this_rank(\\rank_cntrl[0].rank_cntrl0/read_this_rank ),\n .read_this_rank_r(\\rank_cntrl[0].rank_cntrl0/read_this_rank_r ),\n .\\req_bank_r_lcl_reg[0] (\\req_bank_r_lcl_reg[0] ),\n .\\req_bank_r_lcl_reg[0]_0 (\\req_bank_r_lcl_reg[0]_0 ),\n .\\req_bank_r_lcl_reg[0]_1 (i___97_n_0),\n .\\req_bank_r_lcl_reg[1] (i___96_n_0),\n .\\req_bank_r_lcl_reg[2] (\\req_bank_r_lcl_reg[2] ),\n .\\req_bank_r_lcl_reg[2]_0 (\\req_bank_r_lcl_reg[2]_0 ),\n .\\req_bank_r_lcl_reg[2]_1 (i___95_n_0),\n .req_wr_r(req_wr_r),\n .req_wr_r_lcl_reg(i___43_n_0),\n .req_wr_r_lcl_reg_0(i___66_n_0),\n .req_wr_r_lcl_reg_1(i___63_n_0),\n .req_wr_r_lcl_reg_2(i___60_n_0),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] (bank_mach0_n_282),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] (i___87_n_0),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ({i___25_n_0,i___24_n_0,\\bank_common0/rfc_zq_xsdll_timer_ns }),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6] (\\bank_common0/rfc_zq_xsdll_timer_r ),\n .\\rnk_config_strobe_r_reg[0] (bank_mach0_n_121),\n .rnk_config_valid_r(rnk_config_valid_r),\n .rnk_config_valid_r_lcl_reg(bank_mach0_n_122),\n .rnk_config_valid_r_lcl_reg_0(i___34_n_0),\n .row_hit_r(\\bank_cntrl[0].bank0/row_hit_r ),\n .row_hit_r_0(\\bank_cntrl[1].bank0/row_hit_r ),\n .row_hit_r_12(\\bank_cntrl[3].bank0/row_hit_r ),\n .row_hit_r_5(\\bank_cntrl[2].bank0/row_hit_r ),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22),\n .rtp_timer_ns1(rtp_timer_ns1),\n .rtp_timer_ns1_6(rtp_timer_ns1_6),\n .rtp_timer_ns1_7(rtp_timer_ns1_7),\n .rtp_timer_r(\\bank_cntrl[1].bank0/bank_state0/rtp_timer_r ),\n .\\rtw_timer.rtw_cnt_r_reg[1] (bank_mach0_n_100),\n .\\rtw_timer.rtw_cnt_r_reg[1]_0 (rtw_cnt_r),\n .sent_row(sent_row),\n .tail_r(\\bank_cntrl[0].bank0/tail_r ),\n .tail_r_24(\\bank_cntrl[1].bank0/tail_r ),\n .tail_r_26(\\bank_cntrl[2].bank0/tail_r ),\n .tail_r_28(\\bank_cntrl[3].bank0/tail_r ),\n .use_addr(use_addr),\n .wait_for_maint_r(\\bank_cntrl[0].bank0/wait_for_maint_r ),\n .wait_for_maint_r_18(\\bank_cntrl[1].bank0/wait_for_maint_r ),\n .wait_for_maint_r_19(\\bank_cntrl[2].bank0/wait_for_maint_r ),\n .wait_for_maint_r_20(\\bank_cntrl[3].bank0/wait_for_maint_r ),\n .wait_for_maint_r_lcl_reg(i___54_n_0),\n .wait_for_maint_r_lcl_reg_0(i___48_n_0),\n .wait_for_maint_r_lcl_reg_1(i___49_n_0),\n .wait_for_maint_r_lcl_reg_2(i___51_n_0),\n .was_wr(was_wr),\n .\\wtr_timer.wtr_cnt_r_reg[0] (bank_mach0_n_279),\n .\\wtr_timer.wtr_cnt_r_reg[1] (bank_mach0_n_280),\n .\\wtr_timer.wtr_cnt_r_reg[1]_0 (bank_mach0_n_281),\n .\\wtr_timer.wtr_cnt_r_reg[1]_1 (rank_mach0_n_71));\n FDRE \\cmd_pipe_plus.mc_address_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[0]),\n .Q(\\my_full_reg[3] [0]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[10]),\n .Q(\\my_full_reg[3] [10]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[11]),\n .Q(\\my_full_reg[3] [11]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[12] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[12]),\n .Q(\\my_full_reg[3] [12]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[13] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[13]),\n .Q(\\my_full_reg[3] [13]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[14] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[14]),\n .Q(\\my_full_reg[3] [14]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[18] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[18]),\n .Q(\\my_full_reg[3] [15]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[19] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[19]),\n .Q(\\my_full_reg[3] [16]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[1]),\n .Q(\\my_full_reg[3] [1]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[20] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[20]),\n .Q(\\my_full_reg[3] [17]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[21] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[21]),\n .Q(\\my_full_reg[3] [18]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[22] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[22]),\n .Q(\\my_full_reg[3] [19]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[23] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[23]),\n .Q(\\my_full_reg[3] [20]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[24] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[24]),\n .Q(\\my_full_reg[3] [21]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[25] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[25]),\n .Q(\\my_full_reg[3] [22]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[2]),\n .Q(\\my_full_reg[3] [2]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[30] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[30]),\n .Q(\\my_full_reg[3] [23]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[31] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[31]),\n .Q(\\my_full_reg[3] [24]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[32] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[32]),\n .Q(\\my_full_reg[3] [25]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[33] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[33]),\n .Q(\\my_full_reg[3] [26]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[34] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[34]),\n .Q(\\my_full_reg[3] [27]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[35] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[35]),\n .Q(\\my_full_reg[3] [28]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[36] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[36]),\n .Q(\\my_full_reg[3] [29]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[37] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[37]),\n .Q(\\my_full_reg[3] [30]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[38] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[38]),\n .Q(\\my_full_reg[3] [31]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[39] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[39]),\n .Q(\\my_full_reg[3] [32]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[3]),\n .Q(\\my_full_reg[3] [3]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[40] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[40]),\n .Q(\\my_full_reg[3] [33]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[41] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[41]),\n .Q(\\my_full_reg[3] [34]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[42] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[42]),\n .Q(\\my_full_reg[3] [35]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[43] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[43]),\n .Q(\\my_full_reg[3] [36]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[44] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[44]),\n .Q(\\my_full_reg[3] [37]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[4]),\n .Q(\\my_full_reg[3] [4]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[5]),\n .Q(\\my_full_reg[3] [5]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[6]),\n .Q(\\my_full_reg[3] [6]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[7]),\n .Q(\\my_full_reg[3] [7]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[8]),\n .Q(\\my_full_reg[3] [8]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_address_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_address_ns[9]),\n .Q(\\my_full_reg[3] [9]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_bank_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_bank_ns[0]),\n .Q(\\rd_ptr_timing_reg[0]_1 [0]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_bank_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_bank_ns[1]),\n .Q(\\rd_ptr_timing_reg[0]_1 [1]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_bank_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_bank_ns[2]),\n .Q(\\rd_ptr_timing_reg[0]_1 [2]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_bank_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_bank_ns[3]),\n .Q(\\rd_ptr_timing_reg[0]_1 [3]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_bank_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_bank_ns[4]),\n .Q(\\rd_ptr_timing_reg[0]_1 [4]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_bank_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_bank_ns[5]),\n .Q(\\rd_ptr_timing_reg[0]_1 [5]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_bank_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_bank_ns[6]),\n .Q(\\rd_ptr_timing_reg[0]_1 [6]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_bank_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_bank_ns[7]),\n .Q(\\rd_ptr_timing_reg[0]_1 [7]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_bank_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_bank_ns[8]),\n .Q(\\rd_ptr_timing_reg[0]_1 [8]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_cas_n_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_cas_n_ns[0]),\n .Q(mc_cas_n[0]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_cas_n_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_cas_n_ns[1]),\n .Q(mc_cas_n[1]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_cas_n_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(i___112_n_0),\n .Q(mc_cas_n[2]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_cke_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_cke_ns),\n .Q(mc_cke),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_cmd_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(sent_col),\n .Q(mc_cmd[0]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_cmd_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_cmd_ns),\n .Q(mc_cmd[1]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_cs_n_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_cs_n_ns),\n .Q(mc_cs_n),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_data_offset_1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0 ),\n .Q(\\data_offset_1_i1_reg[0] ),\n .R(bank_mach0_n_98));\n FDRE \\cmd_pipe_plus.mc_data_offset_1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] ),\n .Q(\\data_offset_1_i1_reg[1] ),\n .R(bank_mach0_n_98));\n FDSE \\cmd_pipe_plus.mc_data_offset_1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(granted_col_r_reg_2),\n .Q(\\data_offset_1_i1_reg[2] ),\n .S(i___32_n_0));\n FDSE \\cmd_pipe_plus.mc_data_offset_1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(granted_col_r_reg_1),\n .Q(\\data_offset_1_i1_reg[3] ),\n .S(i___32_n_0));\n FDRE \\cmd_pipe_plus.mc_data_offset_1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10] ),\n .Q(\\data_offset_1_i1_reg[4] ),\n .R(bank_mach0_n_98));\n FDRE \\cmd_pipe_plus.mc_data_offset_1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(i___94_n_0),\n .Q(\\data_offset_1_i1_reg[5] ),\n .R(bank_mach0_n_98));\n FDRE \\cmd_pipe_plus.mc_data_offset_2_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(i___32_n_0),\n .Q(\\cmd_pipe_plus.mc_data_offset_2_reg_n_0_[3] ),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_data_offset_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 ),\n .Q(\\phy_ctl_wd_i1_reg[17] ),\n .R(bank_mach0_n_98));\n FDRE \\cmd_pipe_plus.mc_data_offset_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ),\n .Q(\\phy_ctl_wd_i1_reg[18] ),\n .R(bank_mach0_n_98));\n FDSE \\cmd_pipe_plus.mc_data_offset_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(granted_col_r_reg_0),\n .Q(\\phy_ctl_wd_i1_reg[19] ),\n .S(i___32_n_0));\n FDSE \\cmd_pipe_plus.mc_data_offset_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(granted_col_r_reg),\n .Q(\\phy_ctl_wd_i1_reg[20] ),\n .S(i___32_n_0));\n FDRE \\cmd_pipe_plus.mc_data_offset_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4] ),\n .Q(\\phy_ctl_wd_i1_reg[21] ),\n .R(bank_mach0_n_98));\n FDRE \\cmd_pipe_plus.mc_data_offset_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(i___93_n_0),\n .Q(\\phy_ctl_wd_i1_reg[22] ),\n .R(bank_mach0_n_98));\n FDSE \\cmd_pipe_plus.mc_odt_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\cmd_pipe_plus.mc_data_offset_2_reg_n_0_[3] ),\n .Q(mc_odt),\n .S(i___32_n_0));\n FDRE \\cmd_pipe_plus.mc_ras_n_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_ras_n_ns[0]),\n .Q(mc_ras_n[0]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_ras_n_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(i___35_n_0),\n .Q(mc_ras_n[1]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_ras_n_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_ras_n_ns[2]),\n .Q(mc_ras_n[2]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_we_n_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_we_n_ns[0]),\n .Q(mc_we_n[0]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_we_n_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(bank_mach0_n_284),\n .Q(mc_we_n[1]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_we_n_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(mc_we_n_ns[2]),\n .Q(mc_we_n[2]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.mc_wrdata_en_reg \n (.C(CLK),\n .CE(1'b1),\n .D(i___117_n_0),\n .Q(mc_wrdata_en),\n .R(1'b0));\n (* syn_maxfan = \"30\" *) \n FDRE \\cmd_pipe_plus.wr_data_addr_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(col_wr_data_buf_addr_r[0]),\n .Q(\\write_buffer.wr_buf_out_data_reg[287] [0]),\n .R(1'b0));\n (* syn_maxfan = \"30\" *) \n FDRE \\cmd_pipe_plus.wr_data_addr_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(col_wr_data_buf_addr_r[1]),\n .Q(\\write_buffer.wr_buf_out_data_reg[287] [1]),\n .R(1'b0));\n (* syn_maxfan = \"30\" *) \n FDRE \\cmd_pipe_plus.wr_data_addr_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(col_wr_data_buf_addr_r[2]),\n .Q(\\write_buffer.wr_buf_out_data_reg[287] [2]),\n .R(1'b0));\n (* syn_maxfan = \"30\" *) \n FDRE \\cmd_pipe_plus.wr_data_addr_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(col_wr_data_buf_addr_r[3]),\n .Q(\\write_buffer.wr_buf_out_data_reg[287] [3]),\n .R(1'b0));\n FDRE \\cmd_pipe_plus.wr_data_en_reg \n (.C(CLK),\n .CE(1'b1),\n .D(i___118_n_0),\n .Q(E),\n .R(1'b0));\n ddr3_if_mig_7series_v4_0_col_mach col_mach0\n (.ADDRA({i___115_n_0,i___114_n_0,i___116_n_0}),\n .CLK(CLK),\n .D(col_wr_data_buf_addr_r),\n .DIC(col_periodic_rd),\n .E(mc_cmd_ns),\n .SR(SR),\n .app_rd_data_end_ns(app_rd_data_end_ns),\n .bypass__0(bypass__0),\n .col_data_buf_addr(col_data_buf_addr),\n .col_rd_wr(col_rd_wr),\n .col_rd_wr_r1(col_rd_wr_r1),\n .col_rd_wr_r2(col_rd_wr_r2),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .maint_ref_zq_wip(maint_ref_zq_wip),\n .mc_cmd(mc_cmd[0]),\n .mc_read_idle_r_reg(col_mach0_n_16),\n .mc_ref_zq_wip_ns(mc_ref_zq_wip_ns),\n .\\not_strict_mode.app_rd_data_end_reg (\\not_strict_mode.app_rd_data_end_reg ),\n .\\not_strict_mode.status_ram.rd_buf_we_r1_reg (\\not_strict_mode.status_ram.rd_buf_we_r1_reg ),\n .\\rd_buf_indx.rd_buf_indx_r_reg[4] (\\rd_buf_indx.rd_buf_indx_r_reg[4] ),\n .\\read_fifo.fifo_out_data_r_reg[7]_0 (col_mach0_n_21),\n .\\read_fifo.tail_r_reg[0]_0 (\\read_fifo.tail_r_reg[0] ),\n .\\read_fifo.tail_r_reg[1]_0 (\\read_fifo.tail_r_reg[1] ),\n .\\read_fifo.tail_r_reg[2]_0 (tail_r),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23),\n .sent_col_r2(sent_col_r2));\n LUT6 #(\n .INIT(64'hDDCCFFCFDDCCDDCC)) \n i___0\n (.I0(bank_mach0_n_116),\n .I1(bank_mach0_n_151),\n .I2(idle_r[0]),\n .I3(i___47_n_0),\n .I4(i___76_n_0),\n .I5(\\bank_cntrl[0].bank0/tail_r ),\n .O(i___0_n_0));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n i___1\n (.I0(bank_mach0_n_148),\n .I1(bank_mach0_n_116),\n .I2(bank_mach0_n_267),\n .I3(bank_mach0_n_150),\n .I4(head_r[0]),\n .O(i___1_n_0));\n LUT6 #(\n .INIT(64'hB888FFFFB8880000)) \n i___10\n (.I0(bank_mach0_n_135),\n .I1(bank_mach0_n_113),\n .I2(bank_mach0_n_267),\n .I3(bank_mach0_n_152),\n .I4(bank_mach0_n_137),\n .I5(head_r[2]),\n .O(i___10_n_0));\n LUT6 #(\n .INIT(64'h000000000000F808)) \n i___100\n (.I0(sending_pre[0]),\n .I1(req_row_r[12]),\n .I2(sending_pre[1]),\n .I3(req_row_r[27]),\n .I4(sending_pre[3]),\n .I5(sending_pre[2]),\n .O(i___100_n_0));\n LUT6 #(\n .INIT(64'h000000000000F808)) \n i___101\n (.I0(sending_pre[0]),\n .I1(req_row_r[11]),\n .I2(sending_pre[1]),\n .I3(req_row_r[26]),\n .I4(sending_pre[3]),\n .I5(sending_pre[2]),\n .O(i___101_n_0));\n LUT6 #(\n .INIT(64'h000000000000F808)) \n i___102\n (.I0(sending_pre[0]),\n .I1(req_row_r[9]),\n .I2(sending_pre[1]),\n .I3(req_row_r[24]),\n .I4(sending_pre[3]),\n .I5(sending_pre[2]),\n .O(i___102_n_0));\n LUT6 #(\n .INIT(64'h000000000000F808)) \n i___103\n (.I0(sending_pre[0]),\n .I1(req_row_r[8]),\n .I2(sending_pre[1]),\n .I3(req_row_r[23]),\n .I4(sending_pre[3]),\n .I5(sending_pre[2]),\n .O(i___103_n_0));\n LUT6 #(\n .INIT(64'h000000000000F808)) \n i___104\n (.I0(sending_pre[0]),\n .I1(req_row_r[7]),\n .I2(sending_pre[1]),\n .I3(req_row_r[22]),\n .I4(sending_pre[3]),\n .I5(sending_pre[2]),\n .O(i___104_n_0));\n LUT6 #(\n .INIT(64'h000000000000F808)) \n i___105\n (.I0(sending_pre[0]),\n .I1(req_row_r[6]),\n .I2(sending_pre[1]),\n .I3(req_row_r[21]),\n .I4(sending_pre[3]),\n .I5(sending_pre[2]),\n .O(i___105_n_0));\n LUT6 #(\n .INIT(64'h000000000000F808)) \n i___106\n (.I0(sending_pre[0]),\n .I1(req_row_r[5]),\n .I2(sending_pre[1]),\n .I3(req_row_r[20]),\n .I4(sending_pre[3]),\n .I5(sending_pre[2]),\n .O(i___106_n_0));\n LUT6 #(\n .INIT(64'h000000000000F808)) \n i___107\n (.I0(sending_pre[0]),\n .I1(req_row_r[4]),\n .I2(sending_pre[1]),\n .I3(req_row_r[19]),\n .I4(sending_pre[3]),\n .I5(sending_pre[2]),\n .O(i___107_n_0));\n LUT6 #(\n .INIT(64'h000000000000F808)) \n i___108\n (.I0(sending_pre[0]),\n .I1(req_row_r[3]),\n .I2(sending_pre[1]),\n .I3(req_row_r[18]),\n .I4(sending_pre[3]),\n .I5(sending_pre[2]),\n .O(i___108_n_0));\n LUT6 #(\n .INIT(64'h000000000000F808)) \n i___109\n (.I0(sending_pre[0]),\n .I1(req_row_r[2]),\n .I2(sending_pre[1]),\n .I3(req_row_r[17]),\n .I4(sending_pre[3]),\n .I5(sending_pre[2]),\n .O(i___109_n_0));\n LUT6 #(\n .INIT(64'h00000000AEAAEEEE)) \n i___11\n (.I0(\\bank_cntrl[2].bank0/auto_pre_r ),\n .I1(bank_mach0_n_269),\n .I2(\\bank_cntrl[2].bank0/wait_for_maint_r ),\n .I3(bank_mach0_n_141),\n .I4(\\bank_cntrl[2].bank0/row_hit_r ),\n .I5(i___66_n_0),\n .O(i___11_n_0));\n LUT6 #(\n .INIT(64'h000000000000F808)) \n i___110\n (.I0(sending_pre[0]),\n .I1(req_row_r[1]),\n .I2(sending_pre[1]),\n .I3(req_row_r[16]),\n .I4(sending_pre[3]),\n .I5(sending_pre[2]),\n .O(i___110_n_0));\n LUT6 #(\n .INIT(64'h000000000000F808)) \n i___111\n (.I0(sending_pre[0]),\n .I1(req_row_r[0]),\n .I2(sending_pre[1]),\n .I3(req_row_r[15]),\n .I4(sending_pre[3]),\n .I5(sending_pre[2]),\n .O(i___111_n_0));\n LUT5 #(\n .INIT(32'hFFFFFFFB)) \n i___112\n (.I0(sending_pre[1]),\n .I1(\\arb_mux0/cs_en2 ),\n .I2(sending_pre[0]),\n .I3(sending_pre[3]),\n .I4(sending_pre[2]),\n .O(i___112_n_0));\n LUT4 #(\n .INIT(16'h80FF)) \n i___113\n (.I0(row_cmd_wr[3]),\n .I1(sending_pre[3]),\n .I2(req_row_r[55]),\n .I3(\\arb_mux0/cs_en2 ),\n .O(i___113_n_0));\n LUT5 #(\n .INIT(32'h15554000)) \n i___114\n (.I0(rstdiv0_sync_r1_reg_rep__23),\n .I1(\\read_fifo.tail_r_reg[1] ),\n .I2(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I3(tail_r[1]),\n .I4(tail_r[2]),\n .O(i___114_n_0));\n LUT2 #(\n .INIT(4'h1)) \n i___115\n (.I0(rstdiv0_sync_r1_reg_rep__23),\n .I1(col_mach0_n_21),\n .O(i___115_n_0));\n LUT4 #(\n .INIT(16'h1540)) \n i___116\n (.I0(rstdiv0_sync_r1_reg_rep__23),\n .I1(\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .I2(\\read_fifo.tail_r_reg[1] ),\n .I3(tail_r[1]),\n .O(i___116_n_0));\n LUT2 #(\n .INIT(4'h2)) \n i___117\n (.I0(sent_col_r2),\n .I1(col_rd_wr_r2),\n .O(i___117_n_0));\n LUT2 #(\n .INIT(4'h2)) \n i___118\n (.I0(mc_cmd[0]),\n .I1(col_rd_wr_r1),\n .O(i___118_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___119\n (.I0(\\rank_common0/maint_prescaler.maint_prescaler_r_reg__0 [0]),\n .I1(\\rank_common0/maint_prescaler.maint_prescaler_r_reg__0 [1]),\n .O(i___119_n_0));\n LUT6 #(\n .INIT(64'h00000000EAEA0AEA)) \n i___12\n (.I0(ordered_r[2]),\n .I1(bank_mach0_n_132),\n .I2(req_wr_r[2]),\n .I3(sending_col[2]),\n .I4(rd_wr_r[2]),\n .I5(rstdiv0_sync_r1_reg_rep__21),\n .O(i___12_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___120\n (.I0(\\rank_common0/refresh_timer.refresh_timer_r_reg__0 [0]),\n .I1(\\rank_common0/refresh_timer.refresh_timer_r_reg__0 [1]),\n .O(i___120_n_0));\n LUT6 #(\n .INIT(64'hDDCCFFCFDDCCDDCC)) \n i___13\n (.I0(bank_mach0_n_115),\n .I1(bank_mach0_n_138),\n .I2(idle_r[3]),\n .I3(i___46_n_0),\n .I4(bank_mach0_n_159),\n .I5(\\bank_cntrl[3].bank0/tail_r ),\n .O(i___13_n_0));\n LUT6 #(\n .INIT(64'hB888FFFFB8880000)) \n i___14\n (.I0(bank_mach0_n_144),\n .I1(bank_mach0_n_115),\n .I2(i___46_n_0),\n .I3(bank_mach0_n_267),\n .I4(bank_mach0_n_145),\n .I5(head_r[3]),\n .O(i___14_n_0));\n LUT6 #(\n .INIT(64'h00000000AEAAEEEE)) \n i___15\n (.I0(\\bank_cntrl[3].bank0/auto_pre_r ),\n .I1(bank_mach0_n_268),\n .I2(\\bank_cntrl[3].bank0/wait_for_maint_r ),\n .I3(bank_mach0_n_141),\n .I4(\\bank_cntrl[3].bank0/row_hit_r ),\n .I5(i___63_n_0),\n .O(i___15_n_0));\n LUT6 #(\n .INIT(64'h00000000EE0EAAAA)) \n i___16\n (.I0(ordered_r[3]),\n .I1(bank_mach0_n_138),\n .I2(sending_col[3]),\n .I3(rd_wr_r[3]),\n .I4(req_wr_r[3]),\n .I5(rstdiv0_sync_r1_reg_rep__21),\n .O(i___16_n_0));\n LUT5 #(\n .INIT(32'hFFFF0008)) \n i___17\n (.I0(\\rank_cntrl[0].rank_cntrl0/periodic_rd_request_r ),\n .I1(init_calib_complete_reg_rep__6),\n .I2(rank_mach0_n_5),\n .I3(periodic_rd_r),\n .I4(\\rank_common0/periodic_rd_grant_r ),\n .O(i___17_n_0));\n LUT4 #(\n .INIT(16'h2F20)) \n i___18\n (.I0(maint_sre_r),\n .I1(maint_srx_r),\n .I2(insert_maint_r1),\n .I3(app_sr_active),\n .O(i___18_n_0));\n LUT6 #(\n .INIT(64'hFFFFC400C400C400)) \n i___19\n (.I0(\\rank_cntrl[0].rank_cntrl0/refresh_bank_r ),\n .I1(init_calib_complete_reg_rep__6),\n .I2(\\rank_common0/zq_request_r ),\n .I3(insert_maint_r1),\n .I4(maint_wip_r),\n .I5(maint_ref_zq_wip),\n .O(i___19_n_0));\n LUT6 #(\n .INIT(64'h00000000AEAAEEEE)) \n i___2\n (.I0(\\bank_cntrl[0].bank0/auto_pre_r ),\n .I1(bank_mach0_n_266),\n .I2(\\bank_cntrl[0].bank0/wait_for_maint_r ),\n .I3(bank_mach0_n_141),\n .I4(\\bank_cntrl[0].bank0/row_hit_r ),\n .I5(i___60_n_0),\n .O(i___2_n_0));\n LUT2 #(\n .INIT(4'hB)) \n i___20\n (.I0(\\rank_common0/maint_prescaler_tick_ns ),\n .I1(init_calib_complete_reg_rep__6),\n .O(i___20_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1113\" *) \n LUT5 #(\n .INIT(32'h88820008)) \n i___21\n (.I0(init_calib_complete_reg_rep__6),\n .I1(\\rank_cntrl[0].rank_cntrl0/refresh_bank_r ),\n .I2(app_ref_req),\n .I3(rank_mach0_n_27),\n .I4(rank_mach0_n_43),\n .O(i___21_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1113\" *) \n LUT2 #(\n .INIT(4'hB)) \n i___22\n (.I0(rank_mach0_n_27),\n .I1(init_calib_complete_reg_rep__6),\n .O(i___22_n_0));\n LUT5 #(\n .INIT(32'hFF2AFFFF)) \n i___23\n (.I0(\\rank_common0/zq_request_r ),\n .I1(insert_maint_r1),\n .I2(maint_zq_r),\n .I3(app_zq_req),\n .I4(rank_mach0_n_30),\n .O(i___23_n_0));\n LUT5 #(\n .INIT(32'h00415541)) \n i___24\n (.I0(rstdiv0_sync_r1_reg_rep__21),\n .I1(\\bank_common0/rfc_zq_xsdll_timer_r [1]),\n .I2(\\bank_common0/rfc_zq_xsdll_timer_r [0]),\n .I3(insert_maint_r),\n .I4(rank_mach0_n_34),\n .O(i___24_n_0));\n LUT5 #(\n .INIT(32'h00415541)) \n i___25\n (.I0(rstdiv0_sync_r1_reg_rep__21),\n .I1(i___87_n_0),\n .I2(\\bank_common0/rfc_zq_xsdll_timer_r [4]),\n .I3(insert_maint_r),\n .I4(rank_mach0_n_34),\n .O(i___25_n_0));\n LUT5 #(\n .INIT(32'h45444044)) \n i___26\n (.I0(rstdiv0_sync_r1_reg_rep__21),\n .I1(\\rank_common0/maintenance_request.maint_arb0/last_master_r [0]),\n .I2(\\rank_common0/new_maint_rank_r ),\n .I3(\\rank_common0/upd_last_master_r ),\n .I4(\\rank_common0/maint_grant_r [0]),\n .O(i___26_n_0));\n LUT5 #(\n .INIT(32'h45444044)) \n i___27\n (.I0(rstdiv0_sync_r1_reg_rep__21),\n .I1(\\rank_common0/maintenance_request.maint_arb0/last_master_r [1]),\n .I2(\\rank_common0/new_maint_rank_r ),\n .I3(\\rank_common0/upd_last_master_r ),\n .I4(\\rank_common0/maint_grant_r [1]),\n .O(i___27_n_0));\n LUT5 #(\n .INIT(32'h10111511)) \n i___28\n (.I0(rstdiv0_sync_r1_reg_rep__21),\n .I1(\\rank_common0/maintenance_request.maint_arb0/last_master_r [2]),\n .I2(\\rank_common0/new_maint_rank_r ),\n .I3(\\rank_common0/upd_last_master_r ),\n .I4(\\rank_common0/maint_grant_r [2]),\n .O(i___28_n_0));\n LUT5 #(\n .INIT(32'h54005500)) \n i___29\n (.I0(maint_wip_r),\n .I1(\\rank_common0/zq_request_r ),\n .I2(\\rank_common0/sre_request_r ),\n .I3(init_calib_complete_reg_rep__6),\n .I4(\\rank_cntrl[0].rank_cntrl0/refresh_bank_r ),\n .O(i___29_n_0));\n LUT6 #(\n .INIT(64'h00000000EAEA0AEA)) \n i___3\n (.I0(ordered_r[0]),\n .I1(bank_mach0_n_151),\n .I2(req_wr_r[0]),\n .I3(sending_col[0]),\n .I4(rd_wr_r[0]),\n .I5(rstdiv0_sync_r1_reg_rep__20),\n .O(i___3_n_0));\n LUT6 #(\n .INIT(64'h00545454FFFFFFFF)) \n i___30\n (.I0(bank_mach0_n_118),\n .I1(rank_mach0_n_64),\n .I2(\\rank_cntrl[0].rank_cntrl0/periodic_rd_request_r ),\n .I3(clear_periodic_rd_request),\n .I4(\\rank_cntrl[0].rank_cntrl0/periodic_rd_cntr1_r ),\n .I5(init_calib_complete_reg_rep__6),\n .O(i___30_n_0));\n LUT3 #(\n .INIT(8'h78)) \n i___31\n (.I0(\\rank_common0/periodic_rd_grant_r ),\n .I1(periodic_rd_ack_r),\n .I2(\\rank_cntrl[0].rank_cntrl0/periodic_rd_cntr1_r ),\n .O(i___31_n_0));\n LUT2 #(\n .INIT(4'h8)) \n i___32\n (.I0(bank_mach0_n_99),\n .I1(sent_col),\n .O(i___32_n_0));\n LUT4 #(\n .INIT(16'h04F4)) \n i___33\n (.I0(rd_wr_r[2]),\n .I1(sending_col[2]),\n .I2(sending_col[3]),\n .I3(rd_wr_r[3]),\n .O(i___33_n_0));\n LUT3 #(\n .INIT(8'hFB)) \n i___34\n (.I0(rnk_config_valid_r),\n .I1(bank_mach0_n_121),\n .I2(bank_mach0_n_122),\n .O(i___34_n_0));\n LUT5 #(\n .INIT(32'hFFFEFFFF)) \n i___35\n (.I0(sending_col[1]),\n .I1(sending_col[0]),\n .I2(sending_col[3]),\n .I3(sending_col[2]),\n .I4(sent_col),\n .O(i___35_n_0));\n LUT6 #(\n .INIT(64'h4444444444445455)) \n i___36\n (.I0(\\bank_cntrl[2].bank0/bank_state0/col_wait_r ),\n .I1(i___92_n_0),\n .I2(bank_mach0_n_127),\n .I3(\\bank_cntrl[2].bank0/rb_hit_busies_r ),\n .I4(bank_mach0_n_126),\n .I5(bank_mach0_n_154),\n .O(i___36_n_0));\n LUT6 #(\n .INIT(64'h4444444444445455)) \n i___37\n (.I0(\\bank_cntrl[0].bank0/bank_state0/col_wait_r ),\n .I1(bank_mach0_n_130),\n .I2(bank_mach0_n_127),\n .I3(\\bank_cntrl[0].bank0/rb_hit_busies_r ),\n .I4(bank_mach0_n_129),\n .I5(bank_mach0_n_158),\n .O(i___37_n_0));\n LUT6 #(\n .INIT(64'h4444444444445455)) \n i___38\n (.I0(\\bank_cntrl[3].bank0/bank_state0/col_wait_r ),\n .I1(i___91_n_0),\n .I2(bank_mach0_n_127),\n .I3(\\bank_cntrl[3].bank0/rb_hit_busies_r ),\n .I4(bank_mach0_n_131),\n .I5(bank_mach0_n_161),\n .O(i___38_n_0));\n LUT6 #(\n .INIT(64'h6996966996696996)) \n i___39\n (.I0(bank_mach0_n_108),\n .I1(idle_r[0]),\n .I2(idle_r[1]),\n .I3(idle_r[2]),\n .I4(idle_r[3]),\n .I5(bank_mach0_n_116),\n .O(i___39_n_0));\n LUT5 #(\n .INIT(32'h11000010)) \n i___4\n (.I0(act_wait_r_lcl_reg_0),\n .I1(rstdiv0_sync_r1_reg_rep__21),\n .I2(sending_col[1]),\n .I3(\\bank_cntrl[1].bank0/bank_state0/rtp_timer_r [1]),\n .I4(\\bank_cntrl[1].bank0/bank_state0/rtp_timer_r [0]),\n .O(i___4_n_0));\n LUT6 #(\n .INIT(64'h4444554544444444)) \n i___40\n (.I0(i___43_n_0),\n .I1(\\bank_common0/maint_hit_busies_r [1]),\n .I2(maint_req_r),\n .I3(\\bank_common0/periodic_rd_cntr_r ),\n .I4(maint_wip_r),\n .I5(bank_mach0_n_105),\n .O(i___40_n_0));\n LUT6 #(\n .INIT(64'h4454555544544454)) \n i___41\n (.I0(i___43_n_0),\n .I1(\\bank_cntrl[1].bank0/q_has_rd ),\n .I2(maint_req_r),\n .I3(idle_r[1]),\n .I4(was_wr),\n .I5(i___75_n_0),\n .O(i___41_n_0));\n LUT6 #(\n .INIT(64'h2220202020202020)) \n i___42\n (.I0(bank_mach0_n_108),\n .I1(rstdiv0_sync_r1_reg_rep__21),\n .I2(\\bank_cntrl[1].bank0/q_has_priority ),\n .I3(app_hi_pri_r2),\n .I4(rb_hit_busy_r[1]),\n .I5(bank_mach0_n_136),\n .O(i___42_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFFBFAAAAAA)) \n i___43\n (.I0(rstdiv0_sync_r1_reg_rep__21),\n .I1(req_wr_r[1]),\n .I2(rd_wr_r[1]),\n .I3(act_wait_r_lcl_reg_0),\n .I4(sending_col[1]),\n .I5(\\bank_cntrl[1].bank0/bank_queue0/pre_bm_end_r ),\n .O(i___43_n_0));\n LUT5 #(\n .INIT(32'h69969669)) \n i___44\n (.I0(bank_mach0_n_149),\n .I1(rb_hit_busy_r[3]),\n .I2(rb_hit_busy_r[2]),\n .I3(rb_hit_busy_r[1]),\n .I4(rb_hit_busy_r[0]),\n .O(i___44_n_0));\n LUT3 #(\n .INIT(8'h80)) \n i___45\n (.I0(bank_mach0_n_108),\n .I1(bank_mach0_n_116),\n .I2(bank_mach0_n_115),\n .O(i___45_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1118\" *) \n LUT3 #(\n .INIT(8'h80)) \n i___46\n (.I0(bank_mach0_n_108),\n .I1(bank_mach0_n_113),\n .I2(bank_mach0_n_116),\n .O(i___46_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1118\" *) \n LUT3 #(\n .INIT(8'h80)) \n i___47\n (.I0(bank_mach0_n_108),\n .I1(bank_mach0_n_113),\n .I2(bank_mach0_n_115),\n .O(i___47_n_0));\n LUT6 #(\n .INIT(64'hEAAAEAAAEAAAAAAA)) \n i___48\n (.I0(\\bank_cntrl[1].bank0/wait_for_maint_r ),\n .I1(idle_r[1]),\n .I2(head_r[1]),\n .I3(accept_internal_r),\n .I4(use_addr),\n .I5(periodic_rd_ack_r),\n .O(i___48_n_0));\n LUT6 #(\n .INIT(64'hEAAAEAAAEAAAAAAA)) \n i___49\n (.I0(\\bank_cntrl[2].bank0/wait_for_maint_r ),\n .I1(idle_r[2]),\n .I2(head_r[2]),\n .I3(accept_internal_r),\n .I4(use_addr),\n .I5(periodic_rd_ack_r),\n .O(i___49_n_0));\n LUT6 #(\n .INIT(64'hDDCCFFCFDDCCDDCC)) \n i___5\n (.I0(bank_mach0_n_108),\n .I1(bank_mach0_n_147),\n .I2(idle_r[1]),\n .I3(bank_mach0_n_157),\n .I4(i___75_n_0),\n .I5(\\bank_cntrl[1].bank0/tail_r ),\n .O(i___5_n_0));\n LUT6 #(\n .INIT(64'h4444554544444444)) \n i___50\n (.I0(i___66_n_0),\n .I1(\\bank_common0/maint_hit_busies_r [2]),\n .I2(maint_req_r),\n .I3(\\bank_common0/periodic_rd_cntr_r ),\n .I4(maint_wip_r),\n .I5(bank_mach0_n_109),\n .O(i___50_n_0));\n LUT6 #(\n .INIT(64'hEAAAEAAAEAAAAAAA)) \n i___51\n (.I0(\\bank_cntrl[3].bank0/wait_for_maint_r ),\n .I1(idle_r[3]),\n .I2(head_r[3]),\n .I3(accept_internal_r),\n .I4(use_addr),\n .I5(periodic_rd_ack_r),\n .O(i___51_n_0));\n LUT6 #(\n .INIT(64'h8080800000000000)) \n i___52\n (.I0(idle_r[3]),\n .I1(head_r[3]),\n .I2(accept_internal_r),\n .I3(use_addr),\n .I4(periodic_rd_ack_r),\n .I5(req_wr_r[3]),\n .O(i___52_n_0));\n LUT6 #(\n .INIT(64'h4444554544444444)) \n i___53\n (.I0(i___63_n_0),\n .I1(\\bank_common0/maint_hit_busies_r [3]),\n .I2(maint_req_r),\n .I3(\\bank_common0/periodic_rd_cntr_r ),\n .I4(maint_wip_r),\n .I5(bank_mach0_n_111),\n .O(i___53_n_0));\n LUT6 #(\n .INIT(64'hEAAAEAAAEAAAAAAA)) \n i___54\n (.I0(\\bank_cntrl[0].bank0/wait_for_maint_r ),\n .I1(idle_r[0]),\n .I2(head_r[0]),\n .I3(accept_internal_r),\n .I4(use_addr),\n .I5(periodic_rd_ack_r),\n .O(i___54_n_0));\n LUT6 #(\n .INIT(64'h4444554544444444)) \n i___55\n (.I0(i___60_n_0),\n .I1(\\bank_common0/maint_hit_busies_r [0]),\n .I2(maint_req_r),\n .I3(\\bank_common0/periodic_rd_cntr_r ),\n .I4(maint_wip_r),\n .I5(bank_mach0_n_106),\n .O(i___55_n_0));\n LUT6 #(\n .INIT(64'h4444444444445455)) \n i___56\n (.I0(\\bank_cntrl[1].bank0/bank_state0/col_wait_r ),\n .I1(bank_mach0_n_156),\n .I2(bank_mach0_n_128),\n .I3(\\bank_cntrl[1].bank0/rb_hit_busies_r ),\n .I4(bank_mach0_n_155),\n .I5(bank_mach0_n_160),\n .O(i___56_n_0));\n LUT5 #(\n .INIT(32'h69969669)) \n i___57\n (.I0(bank_mach0_n_116),\n .I1(idle_r[3]),\n .I2(idle_r[2]),\n .I3(idle_r[1]),\n .I4(idle_r[0]),\n .O(i___57_n_0));\n LUT6 #(\n .INIT(64'h4454555544544454)) \n i___58\n (.I0(i___60_n_0),\n .I1(\\bank_cntrl[0].bank0/q_has_rd ),\n .I2(maint_req_r),\n .I3(idle_r[0]),\n .I4(was_wr),\n .I5(i___76_n_0),\n .O(i___58_n_0));\n LUT6 #(\n .INIT(64'h2220202020202020)) \n i___59\n (.I0(bank_mach0_n_116),\n .I1(rstdiv0_sync_r1_reg_rep__21),\n .I2(\\bank_cntrl[0].bank0/q_has_priority ),\n .I3(app_hi_pri_r2),\n .I4(rb_hit_busy_r[0]),\n .I5(bank_mach0_n_136),\n .O(i___59_n_0));\n LUT6 #(\n .INIT(64'hB888FFFFB8880000)) \n i___6\n (.I0(bank_mach0_n_153),\n .I1(bank_mach0_n_108),\n .I2(bank_mach0_n_267),\n .I3(bank_mach0_n_116),\n .I4(bank_mach0_n_146),\n .I5(head_r[1]),\n .O(i___6_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFFBFAAAAAA)) \n i___60\n (.I0(rstdiv0_sync_r1_reg_rep__21),\n .I1(req_wr_r[0]),\n .I2(rd_wr_r[0]),\n .I3(act_wait_r_lcl_reg),\n .I4(sending_col[0]),\n .I5(\\bank_cntrl[0].bank0/bank_queue0/pre_bm_end_r ),\n .O(i___60_n_0));\n LUT6 #(\n .INIT(64'h4454555544544454)) \n i___61\n (.I0(i___63_n_0),\n .I1(\\bank_cntrl[3].bank0/q_has_rd ),\n .I2(maint_req_r),\n .I3(idle_r[3]),\n .I4(was_wr),\n .I5(bank_mach0_n_159),\n .O(i___61_n_0));\n LUT6 #(\n .INIT(64'h2220202020202020)) \n i___62\n (.I0(bank_mach0_n_115),\n .I1(rstdiv0_sync_r1_reg_rep__21),\n .I2(\\bank_cntrl[3].bank0/q_has_priority ),\n .I3(app_hi_pri_r2),\n .I4(bank_mach0_n_136),\n .I5(rb_hit_busy_r[3]),\n .O(i___62_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFFBFAAAAAA)) \n i___63\n (.I0(rstdiv0_sync_r1_reg_rep__21),\n .I1(req_wr_r[3]),\n .I2(rd_wr_r[3]),\n .I3(act_wait_r_lcl_reg_2),\n .I4(sending_col[3]),\n .I5(\\bank_cntrl[3].bank0/bank_queue0/pre_bm_end_r ),\n .O(i___63_n_0));\n LUT6 #(\n .INIT(64'h4454555544544454)) \n i___64\n (.I0(i___66_n_0),\n .I1(\\bank_cntrl[2].bank0/q_has_rd ),\n .I2(maint_req_r),\n .I3(idle_r[2]),\n .I4(was_wr),\n .I5(bank_mach0_n_162),\n .O(i___64_n_0));\n LUT6 #(\n .INIT(64'h2220202020202020)) \n i___65\n (.I0(bank_mach0_n_113),\n .I1(rstdiv0_sync_r1_reg_rep__21),\n .I2(\\bank_cntrl[2].bank0/q_has_priority ),\n .I3(app_hi_pri_r2),\n .I4(bank_mach0_n_136),\n .I5(rb_hit_busy_r[2]),\n .O(i___65_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFFBFAAAAAA)) \n i___66\n (.I0(rstdiv0_sync_r1_reg_rep__21),\n .I1(req_wr_r[2]),\n .I2(rd_wr_r[2]),\n .I3(act_wait_r_lcl_reg_1),\n .I4(sending_col[2]),\n .I5(\\bank_cntrl[2].bank0/bank_queue0/pre_bm_end_r ),\n .O(i___66_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1117\" *) \n LUT3 #(\n .INIT(8'h78)) \n i___67\n (.I0(periodic_rd_r),\n .I1(periodic_rd_ack_r),\n .I2(\\rank_common0/periodic_rd_r_cnt ),\n .O(i___67_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1116\" *) \n LUT3 #(\n .INIT(8'h78)) \n i___68\n (.I0(periodic_rd_r),\n .I1(periodic_rd_ack_r),\n .I2(\\bank_common0/periodic_rd_cntr_r ),\n .O(i___68_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1116\" *) \n LUT4 #(\n .INIT(16'hBFAA)) \n i___69\n (.I0(\\app_cmd_r1_reg[0] ),\n .I1(periodic_rd_ack_r),\n .I2(\\bank_common0/periodic_rd_cntr_r ),\n .I3(periodic_rd_r),\n .O(i___69_n_0));\n LUT6 #(\n .INIT(64'h00000000AEAAEEEE)) \n i___7\n (.I0(\\bank_cntrl[1].bank0/auto_pre_r ),\n .I1(bank_mach0_n_265),\n .I2(\\bank_cntrl[1].bank0/wait_for_maint_r ),\n .I3(bank_mach0_n_141),\n .I4(\\bank_cntrl[1].bank0/row_hit_r ),\n .I5(i___43_n_0),\n .O(i___7_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1112\" *) \n LUT5 #(\n .INIT(32'hEEEEEEE0)) \n i___70\n (.I0(sent_row),\n .I1(insert_maint_r1),\n .I2(sending_row[1]),\n .I3(sending_row[2]),\n .I4(sending_row[3]),\n .O(i___70_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1112\" *) \n LUT5 #(\n .INIT(32'hFFFFFFF1)) \n i___71\n (.I0(sent_row),\n .I1(insert_maint_r1),\n .I2(sending_row[1]),\n .I3(sending_row[2]),\n .I4(sending_row[3]),\n .O(i___71_n_0));\n LUT5 #(\n .INIT(32'h00F0F8F8)) \n i___72\n (.I0(app_sr_req),\n .I1(init_calib_complete_reg_rep__6),\n .I2(\\rank_common0/sre_request_r ),\n .I3(insert_maint_r1),\n .I4(maint_sre_r),\n .O(i___72_n_0));\n LUT6 #(\n .INIT(64'h0000040000000000)) \n i___73\n (.I0(bank_mach0_n_259),\n .I1(\\bank_cntrl[2].bank0/bank_state0/ras_timer_zero_r ),\n .I2(idle_r[2]),\n .I3(row_cmd_wr[2]),\n .I4(\\bank_cntrl[2].bank0/wait_for_maint_r ),\n .I5(head_r[2]),\n .O(i___73_n_0));\n LUT6 #(\n .INIT(64'h0000040000000000)) \n i___74\n (.I0(bank_mach0_n_275),\n .I1(\\bank_cntrl[0].bank0/bank_state0/ras_timer_zero_r ),\n .I2(idle_r[0]),\n .I3(row_cmd_wr[0]),\n .I4(\\bank_cntrl[0].bank0/wait_for_maint_r ),\n .I5(head_r[0]),\n .O(i___74_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1115\" *) \n LUT4 #(\n .INIT(16'hF800)) \n i___75\n (.I0(use_addr),\n .I1(bank_mach0_n_2),\n .I2(periodic_rd_ack_r),\n .I3(rb_hit_busy_r[1]),\n .O(i___75_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1115\" *) \n LUT4 #(\n .INIT(16'hF800)) \n i___76\n (.I0(use_addr),\n .I1(bank_mach0_n_2),\n .I2(periodic_rd_ack_r),\n .I3(rb_hit_busy_r[0]),\n .O(i___76_n_0));\n LUT4 #(\n .INIT(16'hAAFB)) \n i___77\n (.I0(rstdiv0_sync_r1_reg_rep__22),\n .I1(maint_req_r),\n .I2(\\bank_common0/periodic_rd_cntr_r ),\n .I3(maint_wip_r),\n .O(i___77_n_0));\n LUT4 #(\n .INIT(16'h0151)) \n i___78\n (.I0(rstdiv0_sync_r1_reg_rep__22),\n .I1(\\arb_mux0/arb_row_col0/row_arb0/last_master_r ),\n .I2(sent_row),\n .I3(sending_row[3]),\n .O(i___78_n_0));\n LUT4 #(\n .INIT(16'h0151)) \n i___79\n (.I0(rstdiv0_sync_r1_reg_rep__22),\n .I1(\\arb_mux0/arb_row_col0/pre_4_1_1T_arb.pre_arb0/last_master_r ),\n .I2(\\arb_mux0/cs_en2 ),\n .I3(sending_pre[3]),\n .O(i___79_n_0));\n LUT6 #(\n .INIT(64'h00000000EAEA0AEA)) \n i___8\n (.I0(ordered_r[1]),\n .I1(bank_mach0_n_147),\n .I2(req_wr_r[1]),\n .I3(sending_col[1]),\n .I4(rd_wr_r[1]),\n .I5(rstdiv0_sync_r1_reg_rep__21),\n .O(i___8_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1117\" *) \n LUT4 #(\n .INIT(16'hFF4C)) \n i___80\n (.I0(periodic_rd_ack_r),\n .I1(periodic_rd_r),\n .I2(\\rank_common0/periodic_rd_r_cnt ),\n .I3(rank_mach0_n_5),\n .O(i___80_n_0));\n LUT3 #(\n .INIT(8'hBA)) \n i___81\n (.I0(app_ref_req),\n .I1(\\rank_cntrl[0].rank_cntrl0/refresh_bank_r ),\n .I2(\\rank_common0/app_ref_r ),\n .O(i___81_n_0));\n LUT3 #(\n .INIT(8'hEA)) \n i___82\n (.I0(app_zq_req),\n .I1(\\rank_common0/app_zq_r ),\n .I2(\\rank_common0/zq_request_r ),\n .O(i___82_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1114\" *) \n LUT4 #(\n .INIT(16'h1441)) \n i___83\n (.I0(rstdiv0_sync_r1_reg_rep__22),\n .I1(\\rank_cntrl[0].rank_cntrl0/act_delayed ),\n .I2(bank_mach0_n_278),\n .I3(faw_cnt_r[0]),\n .O(i___83_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair1114\" *) \n LUT5 #(\n .INIT(32'h44411444)) \n i___84\n (.I0(rstdiv0_sync_r1_reg_rep__22),\n .I1(faw_cnt_r[1]),\n .I2(bank_mach0_n_278),\n .I3(\\rank_cntrl[0].rank_cntrl0/act_delayed ),\n .I4(faw_cnt_r[0]),\n .O(i___84_n_0));\n LUT6 #(\n .INIT(64'h5050501441505050)) \n i___85\n (.I0(rstdiv0_sync_r1_reg_rep__22),\n .I1(faw_cnt_r[1]),\n .I2(faw_cnt_r[2]),\n .I3(\\rank_cntrl[0].rank_cntrl0/act_delayed ),\n .I4(bank_mach0_n_278),\n .I5(faw_cnt_r[0]),\n .O(i___85_n_0));\n LUT6 #(\n .INIT(64'h5554555455545454)) \n i___86\n (.I0(rstdiv0_sync_r1_reg_rep__22),\n .I1(bank_mach0_n_281),\n .I2(bank_mach0_n_280),\n .I3(wtr_cnt_r[2]),\n .I4(wtr_cnt_r[1]),\n .I5(wtr_cnt_r[0]),\n .O(i___86_n_0));\n LUT4 #(\n .INIT(16'hFFFE)) \n i___87\n (.I0(\\bank_common0/rfc_zq_xsdll_timer_r [3]),\n .I1(\\bank_common0/rfc_zq_xsdll_timer_r [2]),\n .I2(\\bank_common0/rfc_zq_xsdll_timer_r [0]),\n .I3(\\bank_common0/rfc_zq_xsdll_timer_r [1]),\n .O(i___87_n_0));\n LUT6 #(\n .INIT(64'h0000000044444544)) \n i___88\n (.I0(\\bank_cntrl[2].bank0/bank_state0/override_demand_r ),\n .I1(bank_mach0_n_283),\n .I2(\\bank_cntrl[2].bank0/bank_state0/demanded_prior_r ),\n .I3(\\bank_cntrl[2].bank0/bank_state0/demand_priority_r ),\n .I4(sending_col[2]),\n .I5(\\bank_cntrl[0].bank0/bank_state0/demand_priority_r ),\n .O(i___88_n_0));\n LUT6 #(\n .INIT(64'h0000000055550010)) \n i___89\n (.I0(\\bank_cntrl[2].bank0/bank_state0/override_demand_r ),\n .I1(\\bank_cntrl[0].bank0/bank_state0/demanded_prior_r ),\n .I2(\\bank_cntrl[0].bank0/bank_state0/demand_priority_r ),\n .I3(sending_col[0]),\n .I4(bank_mach0_n_283),\n .I5(\\bank_cntrl[2].bank0/bank_state0/demand_priority_r ),\n .O(i___89_n_0));\n LUT6 #(\n .INIT(64'hDDCCFFCFDDCCDDCC)) \n i___9\n (.I0(bank_mach0_n_113),\n .I1(bank_mach0_n_132),\n .I2(idle_r[2]),\n .I3(i___45_n_0),\n .I4(bank_mach0_n_162),\n .I5(\\bank_cntrl[2].bank0/tail_r ),\n .O(i___9_n_0));\n LUT6 #(\n .INIT(64'h0000000055550010)) \n i___90\n (.I0(\\bank_cntrl[2].bank0/bank_state0/override_demand_r ),\n .I1(\\bank_cntrl[3].bank0/bank_state0/demanded_prior_r ),\n .I2(\\bank_cntrl[3].bank0/bank_state0/demand_priority_r ),\n .I3(sending_col[3]),\n .I4(bank_mach0_n_276),\n .I5(\\bank_cntrl[1].bank0/bank_state0/demand_priority_r ),\n .O(i___90_n_0));\n LUT3 #(\n .INIT(8'hEF)) \n i___91\n (.I0(idle_r[3]),\n .I1(\\bank_cntrl[3].bank0/q_entry_r [1]),\n .I2(\\bank_cntrl[3].bank0/q_entry_r [0]),\n .O(i___91_n_0));\n LUT3 #(\n .INIT(8'hEF)) \n i___92\n (.I0(idle_r[2]),\n .I1(\\bank_cntrl[2].bank0/q_entry_r [1]),\n .I2(\\bank_cntrl[2].bank0/q_entry_r [0]),\n .O(i___92_n_0));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n i___93\n (.I0(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [5]),\n .I1(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [2]),\n .I2(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [0]),\n .I3(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [1]),\n .I4(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [3]),\n .I5(\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [4]),\n .O(i___93_n_0));\n LUT6 #(\n .INIT(64'h6AAAAAAAAAAAAAAA)) \n i___94\n (.I0(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [5]),\n .I1(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [2]),\n .I2(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [0]),\n .I3(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [1]),\n .I4(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [3]),\n .I5(\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [4]),\n .O(i___94_n_0));\n LUT6 #(\n .INIT(64'h000000000000F808)) \n i___95\n (.I0(Q[2]),\n .I1(sending_pre[0]),\n .I2(sending_pre[1]),\n .I3(\\cmd_pipe_plus.mc_bank_reg[2]_0 [2]),\n .I4(sending_pre[3]),\n .I5(sending_pre[2]),\n .O(i___95_n_0));\n LUT6 #(\n .INIT(64'h000000000000F808)) \n i___96\n (.I0(Q[1]),\n .I1(sending_pre[0]),\n .I2(sending_pre[1]),\n .I3(\\cmd_pipe_plus.mc_bank_reg[2]_0 [1]),\n .I4(sending_pre[3]),\n .I5(sending_pre[2]),\n .O(i___96_n_0));\n LUT6 #(\n .INIT(64'h000000000000F808)) \n i___97\n (.I0(Q[0]),\n .I1(sending_pre[0]),\n .I2(sending_pre[1]),\n .I3(\\cmd_pipe_plus.mc_bank_reg[2]_0 [0]),\n .I4(sending_pre[3]),\n .I5(sending_pre[2]),\n .O(i___97_n_0));\n LUT6 #(\n .INIT(64'h000000000000F808)) \n i___98\n (.I0(sending_pre[0]),\n .I1(req_row_r[14]),\n .I2(sending_pre[1]),\n .I3(req_row_r[29]),\n .I4(sending_pre[3]),\n .I5(sending_pre[2]),\n .O(i___98_n_0));\n LUT6 #(\n .INIT(64'h000000000000F808)) \n i___99\n (.I0(sending_pre[0]),\n .I1(req_row_r[13]),\n .I2(sending_pre[1]),\n .I3(req_row_r[28]),\n .I4(sending_pre[3]),\n .I5(sending_pre[2]),\n .O(i___99_n_0));\n FDRE mc_read_idle_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(col_mach0_n_16),\n .Q(idle),\n .R(maint_prescaler_r1));\n FDRE mc_ref_zq_wip_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mc_ref_zq_wip_ns),\n .Q(tempmon_sample_en),\n .R(1'b0));\n LUT2 #(\n .INIT(4'hB)) \n mem_reg_0_15_0_5_i_2__0\n (.I0(mc_cs_n),\n .I1(init_calib_complete_reg_rep__7),\n .O(\\rd_ptr_timing_reg[0] [0]));\n LUT2 #(\n .INIT(4'hB)) \n mem_reg_0_15_0_5_i_3__0\n (.I0(mc_ras_n[2]),\n .I1(init_calib_complete_reg_rep__7),\n .O(\\rd_ptr_timing_reg[0]_0 [3]));\n LUT2 #(\n .INIT(4'hB)) \n mem_reg_0_15_12_17_i_2__4\n (.I0(mc_cas_n[0]),\n .I1(init_calib_complete_reg_rep__7),\n .O(\\rd_ptr_timing_reg[0]_0 [0]));\n LUT2 #(\n .INIT(4'hB)) \n mem_reg_0_15_18_23_i_1__4\n (.I0(mc_cas_n[2]),\n .I1(init_calib_complete_reg_rep__7),\n .O(\\rd_ptr_timing_reg[0]_0 [1]));\n LUT2 #(\n .INIT(4'hB)) \n mem_reg_0_15_24_29_i_2__4\n (.I0(mc_ras_n[0]),\n .I1(init_calib_complete_reg_rep__7),\n .O(\\rd_ptr_timing_reg[0]_0 [2]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_30_35_i_1__5\n (.I0(\\my_full_reg[3] [14]),\n .I1(init_calib_complete_reg_rep__7),\n .O(phy_dout[0]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_30_35_i_2__5\n (.I0(\\my_full_reg[3] [37]),\n .I1(init_calib_complete_reg_rep__7),\n .O(phy_dout[1]));\n LUT2 #(\n .INIT(4'hB)) \n mem_reg_0_15_6_11_i_2__4\n (.I0(mc_we_n[0]),\n .I1(init_calib_complete_reg_rep__7),\n .O(\\rd_ptr_timing_reg[0] [1]));\n LUT2 #(\n .INIT(4'hB)) \n mem_reg_0_15_6_11_i_3__4\n (.I0(mc_we_n[2]),\n .I1(init_calib_complete_reg_rep__7),\n .O(\\rd_ptr_timing_reg[0] [2]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_2__0\n (.I0(\\my_full_reg[3] [13]),\n .I1(init_calib_complete_reg_rep__7),\n .O(\\my_empty_reg[7] [0]));\n LUT2 #(\n .INIT(4'h8)) \n mem_reg_0_15_72_77_i_3__0\n (.I0(\\my_full_reg[3] [36]),\n .I1(init_calib_complete_reg_rep__7),\n .O(\\my_empty_reg[7] [1]));\n LUT2 #(\n .INIT(4'hB)) \n \\pointer_ram.rams[0].RAM32M0_i_1 \n (.I0(E),\n .I1(ram_init_done_r),\n .O(pointer_we));\n ddr3_if_mig_7series_v4_0_rank_mach rank_mach0\n (.CLK(CLK),\n .D({i___27_n_0,i___26_n_0}),\n .O({\\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_4 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_5 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_6 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_7 }),\n .Q(\\rank_common0/maint_prescaler.maint_prescaler_r_reg__0 ),\n .S({rank_mach0_n_44,rank_mach0_n_45,rank_mach0_n_46,rank_mach0_n_47}),\n .SR(SR),\n .SS(i___20_n_0),\n .act_delayed(\\rank_cntrl[0].rank_cntrl0/act_delayed ),\n .act_this_rank(\\rank_cntrl[0].rank_cntrl0/act_this_rank ),\n .app_ref_ack(app_ref_ack),\n .app_ref_r(\\rank_common0/app_ref_r ),\n .app_sr_active(app_sr_active),\n .app_sr_req(app_sr_req),\n .app_zq_ack(app_zq_ack),\n .app_zq_r(\\rank_common0/app_zq_r ),\n .app_zq_r_reg(i___82_n_0),\n .cke_r(\\arb_mux0/arb_select0/cke_r ),\n .\\grant_r_reg[0] (bank_mach0_n_100),\n .\\grant_r_reg[2] (bank_mach0_n_278),\n .\\grant_r_reg[3] (rank_mach0_n_71),\n .in0(in0),\n .\\inhbt_act_faw.faw_cnt_r_reg[1] ({i___85_n_0,i___84_n_0,i___83_n_0}),\n .\\inhbt_act_faw.inhbt_act_faw_r_reg (faw_cnt_r),\n .inhbt_act_faw_r(inhbt_act_faw_r),\n .init_calib_complete_reg_rep__6(i___72_n_0),\n .init_calib_complete_reg_rep__6_0(i___21_n_0),\n .init_calib_complete_reg_rep__6_1(init_calib_complete_reg_rep__6),\n .init_calib_complete_reg_rep__6_2(i___22_n_0),\n .insert_maint_r(insert_maint_r),\n .insert_maint_r1(insert_maint_r1),\n .\\last_master_r_reg[2] (\\rank_common0/maintenance_request.maint_arb0/last_master_r ),\n .\\last_master_r_reg[2]_0 (i___28_n_0),\n .\\maint_controller.maint_wip_r_lcl_reg (i___29_n_0),\n .\\maint_prescaler.maint_prescaler_r_reg[0] (i___119_n_0),\n .maint_prescaler_r1(maint_prescaler_r1),\n .maint_prescaler_tick_ns(\\rank_common0/maint_prescaler_tick_ns ),\n .maint_ref_zq_wip(maint_ref_zq_wip),\n .maint_req_r(maint_req_r),\n .maint_sre_r(maint_sre_r),\n .maint_srx_r(maint_srx_r),\n .maint_zq_r(maint_zq_r),\n .\\maintenance_request.maint_sre_r_lcl_reg (\\rank_common0/maint_grant_r ),\n .\\maintenance_request.maint_sre_r_lcl_reg_0 (i___18_n_0),\n .mc_cke_ns(mc_cke_ns),\n .new_maint_rank_r(\\rank_common0/new_maint_rank_r ),\n .periodic_rd_ack_r_lcl_reg(i___80_n_0),\n .periodic_rd_cntr1_r(\\rank_cntrl[0].rank_cntrl0/periodic_rd_cntr1_r ),\n .\\periodic_rd_generation.periodic_rd_request_r_reg (rank_mach0_n_64),\n .\\periodic_rd_generation.periodic_rd_request_r_reg_0 (i___30_n_0),\n .\\periodic_rd_generation.periodic_rd_request_r_reg_1 (i___17_n_0),\n .\\periodic_rd_generation.read_this_rank_r_reg (bank_mach0_n_118),\n .periodic_rd_grant_r(\\rank_common0/periodic_rd_grant_r ),\n .periodic_rd_r(periodic_rd_r),\n .periodic_rd_r_cnt(\\rank_common0/periodic_rd_r_cnt ),\n .periodic_rd_request_r(\\rank_cntrl[0].rank_cntrl0/periodic_rd_request_r ),\n .\\periodic_read_request.periodic_rd_grant_r_reg[0] (i___31_n_0),\n .\\periodic_read_request.periodic_rd_r_lcl_reg (i___67_n_0),\n .\\periodic_read_request.upd_last_master_r_reg (rank_mach0_n_5),\n .read_this_rank(\\rank_cntrl[0].rank_cntrl0/read_this_rank ),\n .read_this_rank_r(\\rank_cntrl[0].rank_cntrl0/read_this_rank_r ),\n .refresh_bank_r(\\rank_cntrl[0].rank_cntrl0/refresh_bank_r ),\n .\\refresh_generation.refresh_bank_r_reg[0] (rank_mach0_n_43),\n .\\refresh_generation.refresh_bank_r_reg[0]_0 (i___81_n_0),\n .\\refresh_generation.refresh_bank_r_reg[0]_1 (i___19_n_0),\n .\\refresh_timer.refresh_timer_r_reg[0] (i___120_n_0),\n .\\refresh_timer.refresh_timer_r_reg[4] (\\rank_common0/refresh_timer.refresh_timer_r_reg__0 ),\n .\\refresh_timer.refresh_timer_r_reg[5] (rank_mach0_n_27),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] (\\bank_common0/rfc_zq_xsdll_timer_ns ),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 (\\bank_common0/rfc_zq_xsdll_timer_r [0]),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] (bank_mach0_n_282),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] (rank_mach0_n_34),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] (rank_mach0_n_42),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] (rank_mach0_n_40),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22),\n .\\rtw_timer.rtw_cnt_r_reg[1] (rtw_cnt_r),\n .sre_request_r(\\rank_common0/sre_request_r ),\n .upd_last_master_r(\\rank_common0/upd_last_master_r ),\n .\\wr_this_rank_r_reg[0] (bank_mach0_n_279),\n .\\wr_this_rank_r_reg[0]_0 (bank_mach0_n_281),\n .\\wr_this_rank_r_reg[0]_1 (bank_mach0_n_280),\n .\\wtr_timer.wtr_cnt_r_reg[1] (wtr_cnt_r),\n .\\wtr_timer.wtr_cnt_r_reg[2] (i___86_n_0),\n .\\zq_cntrl.zq_request_logic.zq_request_r_reg (i___23_n_0),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[0] (rank_mach0_n_30),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[11] ({rank_mach0_n_52,rank_mach0_n_53,rank_mach0_n_54,rank_mach0_n_55}),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ({\\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_4 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_5 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_6 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_7 }),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[15] ({rank_mach0_n_56,rank_mach0_n_57,rank_mach0_n_58,rank_mach0_n_59}),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ({\\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_4 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_5 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_6 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_7 }),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[19] ({rank_mach0_n_60,rank_mach0_n_61,rank_mach0_n_62,rank_mach0_n_63}),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ({\\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_4 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_5 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_6 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_7 }),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[7] ({rank_mach0_n_48,rank_mach0_n_49,rank_mach0_n_50,rank_mach0_n_51}),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ({\\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_4 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_5 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_6 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_7 }),\n .zq_request_r(\\rank_common0/zq_request_r ));\n CARRY4 \\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3 \n (.CI(1'b0),\n .CO({\\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_0 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_1 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_2 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b1,1'b1,1'b1,1'b1}),\n .O({\\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_4 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_5 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_6 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_7 }),\n .S({rank_mach0_n_44,rank_mach0_n_45,rank_mach0_n_46,rank_mach0_n_47}));\n CARRY4 \\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1 \n (.CI(\\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_0 ),\n .CO({\\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_0 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_1 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_2 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b1,1'b1,1'b1,1'b1}),\n .O({\\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_4 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_5 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_6 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_7 }),\n .S({rank_mach0_n_56,rank_mach0_n_57,rank_mach0_n_58,rank_mach0_n_59}));\n CARRY4 \\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1 \n (.CI(\\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_0 ),\n .CO({\\NLW_zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_CO_UNCONNECTED [3],\\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_1 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_2 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b1,1'b1,1'b1}),\n .O({\\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_4 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_5 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_6 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_7 }),\n .S({rank_mach0_n_60,rank_mach0_n_61,rank_mach0_n_62,rank_mach0_n_63}));\n CARRY4 \\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1 \n (.CI(\\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_0 ),\n .CO({\\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_0 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_1 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_2 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b1,1'b1,1'b1,1'b1}),\n .O({\\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_4 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_5 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_6 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_7 }),\n .S({rank_mach0_n_48,rank_mach0_n_49,rank_mach0_n_50,rank_mach0_n_51}));\n CARRY4 \\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1 \n (.CI(\\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_0 ),\n .CO({\\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_0 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_1 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_2 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b1,1'b1,1'b1,1'b1}),\n .O({\\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_4 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_5 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_6 ,\\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_7 }),\n .S({rank_mach0_n_52,rank_mach0_n_53,rank_mach0_n_54,rank_mach0_n_55}));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_mem_intfc\n (accept_ns,\n bm_end_r1,\n act_wait_r_lcl_reg,\n bm_end_r1_0,\n act_wait_r_lcl_reg_0,\n \\ras_timer_r_reg[2] ,\n act_wait_r_lcl_reg_1,\n bm_end_r1_4,\n act_wait_r_lcl_reg_2,\n app_ref_ack,\n app_zq_ack,\n E,\n app_sr_active,\n req_bank_r,\n ddr3_reset_n,\n ddr3_cas_n,\n ddr3_ras_n,\n ddr3_we_n,\n ddr3_addr,\n ddr3_ba,\n ddr3_cs_n,\n ddr3_odt,\n ddr3_cke,\n ddr3_dm,\n \\rd_ptr_timing_reg[2] ,\n \\rd_ptr_timing_reg[2]_0 ,\n \\rd_ptr_timing_reg[2]_1 ,\n \\rd_ptr_timing_reg[2]_2 ,\n \\rd_ptr_timing_reg[2]_3 ,\n \\rd_ptr_timing_reg[2]_4 ,\n \\rd_ptr_timing_reg[2]_5 ,\n \\rd_ptr_timing_reg[2]_6 ,\n \\rd_ptr_timing_reg[2]_7 ,\n \\rd_ptr_timing_reg[2]_8 ,\n \\rd_ptr_timing_reg[2]_9 ,\n \\rd_ptr_timing_reg[2]_10 ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,\n phy_dout,\n \\samps_r_reg[9] ,\n init_calib_complete_r_reg,\n \\calib_seq_reg[0] ,\n \\pi_rst_stg1_cal_r_reg[0] ,\n samp_edge_cnt0_en_r,\n pi_en_stg2_f_timing_reg,\n dqs_po_en_stg2_f_reg,\n \\rd_ptr_timing_reg[0] ,\n \\rd_ptr_timing_reg[0]_0 ,\n \\resume_wait_r_reg[5] ,\n stg3_dec2init_val_r_reg,\n stg3_inc2init_val_r_reg,\n bypass__0,\n \\not_strict_mode.app_rd_data_end_reg ,\n rd_buf_we,\n rst_sync_r1_reg,\n \\stg2_tap_cnt_reg[0] ,\n \\sm_r_reg[0] ,\n D,\n \\not_strict_mode.app_rd_data_reg[255] ,\n \\not_strict_mode.app_rd_data_reg[239] ,\n \\not_strict_mode.app_rd_data_reg[247] ,\n \\not_strict_mode.app_rd_data_reg[231] ,\n \\not_strict_mode.app_rd_data_reg[254] ,\n \\not_strict_mode.app_rd_data_reg[238] ,\n \\not_strict_mode.app_rd_data_reg[246] ,\n \\not_strict_mode.app_rd_data_reg[230] ,\n \\not_strict_mode.app_rd_data_reg[253] ,\n \\not_strict_mode.app_rd_data_reg[237] ,\n \\not_strict_mode.app_rd_data_reg[245] ,\n \\not_strict_mode.app_rd_data_reg[229] ,\n \\not_strict_mode.app_rd_data_reg[252] ,\n \\not_strict_mode.app_rd_data_reg[236] ,\n \\not_strict_mode.app_rd_data_reg[244] ,\n \\not_strict_mode.app_rd_data_reg[228] ,\n \\not_strict_mode.app_rd_data_reg[251] ,\n \\not_strict_mode.app_rd_data_reg[235] ,\n \\not_strict_mode.app_rd_data_reg[243] ,\n \\not_strict_mode.app_rd_data_reg[227] ,\n \\not_strict_mode.app_rd_data_reg[250] ,\n \\not_strict_mode.app_rd_data_reg[234] ,\n \\not_strict_mode.app_rd_data_reg[242] ,\n \\not_strict_mode.app_rd_data_reg[226] ,\n \\not_strict_mode.app_rd_data_reg[249] ,\n \\not_strict_mode.app_rd_data_reg[233] ,\n \\not_strict_mode.app_rd_data_reg[241] ,\n \\not_strict_mode.app_rd_data_reg[225] ,\n \\not_strict_mode.app_rd_data_reg[248] ,\n \\not_strict_mode.app_rd_data_reg[232] ,\n \\not_strict_mode.app_rd_data_reg[240] ,\n \\not_strict_mode.app_rd_data_reg[224] ,\n \\not_strict_mode.app_rd_data_reg[223] ,\n \\not_strict_mode.app_rd_data_reg[207] ,\n \\not_strict_mode.app_rd_data_reg[215] ,\n \\not_strict_mode.app_rd_data_reg[199] ,\n \\not_strict_mode.app_rd_data_reg[222] ,\n \\not_strict_mode.app_rd_data_reg[206] ,\n \\not_strict_mode.app_rd_data_reg[214] ,\n \\not_strict_mode.app_rd_data_reg[198] ,\n \\not_strict_mode.app_rd_data_reg[221] ,\n \\not_strict_mode.app_rd_data_reg[205] ,\n \\not_strict_mode.app_rd_data_reg[213] ,\n \\not_strict_mode.app_rd_data_reg[197] ,\n \\not_strict_mode.app_rd_data_reg[220] ,\n \\not_strict_mode.app_rd_data_reg[204] ,\n \\not_strict_mode.app_rd_data_reg[212] ,\n \\not_strict_mode.app_rd_data_reg[196] ,\n \\not_strict_mode.app_rd_data_reg[219] ,\n \\not_strict_mode.app_rd_data_reg[203] ,\n \\not_strict_mode.app_rd_data_reg[211] ,\n \\not_strict_mode.app_rd_data_reg[195] ,\n \\not_strict_mode.app_rd_data_reg[218] ,\n \\not_strict_mode.app_rd_data_reg[202] ,\n \\not_strict_mode.app_rd_data_reg[210] ,\n \\not_strict_mode.app_rd_data_reg[194] ,\n \\not_strict_mode.app_rd_data_reg[217] ,\n \\not_strict_mode.app_rd_data_reg[201] ,\n \\not_strict_mode.app_rd_data_reg[209] ,\n \\not_strict_mode.app_rd_data_reg[193] ,\n \\not_strict_mode.app_rd_data_reg[216] ,\n \\not_strict_mode.app_rd_data_reg[200] ,\n \\not_strict_mode.app_rd_data_reg[208] ,\n \\not_strict_mode.app_rd_data_reg[192] ,\n \\not_strict_mode.app_rd_data_reg[191] ,\n \\not_strict_mode.app_rd_data_reg[175] ,\n \\not_strict_mode.app_rd_data_reg[183] ,\n \\not_strict_mode.app_rd_data_reg[167] ,\n \\not_strict_mode.app_rd_data_reg[190] ,\n \\not_strict_mode.app_rd_data_reg[174] ,\n \\not_strict_mode.app_rd_data_reg[182] ,\n \\not_strict_mode.app_rd_data_reg[166] ,\n \\not_strict_mode.app_rd_data_reg[189] ,\n \\not_strict_mode.app_rd_data_reg[173] ,\n \\not_strict_mode.app_rd_data_reg[181] ,\n \\not_strict_mode.app_rd_data_reg[165] ,\n \\not_strict_mode.app_rd_data_reg[188] ,\n \\not_strict_mode.app_rd_data_reg[172] ,\n \\not_strict_mode.app_rd_data_reg[180] ,\n \\not_strict_mode.app_rd_data_reg[164] ,\n \\not_strict_mode.app_rd_data_reg[187] ,\n \\not_strict_mode.app_rd_data_reg[171] ,\n \\not_strict_mode.app_rd_data_reg[179] ,\n \\not_strict_mode.app_rd_data_reg[163] ,\n \\not_strict_mode.app_rd_data_reg[186] ,\n \\not_strict_mode.app_rd_data_reg[170] ,\n \\not_strict_mode.app_rd_data_reg[178] ,\n \\not_strict_mode.app_rd_data_reg[162] ,\n \\not_strict_mode.app_rd_data_reg[185] ,\n \\not_strict_mode.app_rd_data_reg[169] ,\n \\not_strict_mode.app_rd_data_reg[177] ,\n \\not_strict_mode.app_rd_data_reg[161] ,\n \\not_strict_mode.app_rd_data_reg[184] ,\n \\not_strict_mode.app_rd_data_reg[168] ,\n \\not_strict_mode.app_rd_data_reg[176] ,\n \\not_strict_mode.app_rd_data_reg[160] ,\n \\not_strict_mode.app_rd_data_reg[159] ,\n \\not_strict_mode.app_rd_data_reg[143] ,\n \\not_strict_mode.app_rd_data_reg[151] ,\n \\not_strict_mode.app_rd_data_reg[135] ,\n \\not_strict_mode.app_rd_data_reg[158] ,\n \\not_strict_mode.app_rd_data_reg[142] ,\n \\not_strict_mode.app_rd_data_reg[150] ,\n \\not_strict_mode.app_rd_data_reg[134] ,\n \\not_strict_mode.app_rd_data_reg[157] ,\n \\not_strict_mode.app_rd_data_reg[141] ,\n \\not_strict_mode.app_rd_data_reg[149] ,\n \\not_strict_mode.app_rd_data_reg[133] ,\n \\not_strict_mode.app_rd_data_reg[156] ,\n \\not_strict_mode.app_rd_data_reg[140] ,\n \\not_strict_mode.app_rd_data_reg[148] ,\n \\not_strict_mode.app_rd_data_reg[132] ,\n \\not_strict_mode.app_rd_data_reg[155] ,\n \\not_strict_mode.app_rd_data_reg[139] ,\n \\not_strict_mode.app_rd_data_reg[147] ,\n \\not_strict_mode.app_rd_data_reg[131] ,\n \\not_strict_mode.app_rd_data_reg[154] ,\n \\not_strict_mode.app_rd_data_reg[138] ,\n \\not_strict_mode.app_rd_data_reg[146] ,\n \\not_strict_mode.app_rd_data_reg[130] ,\n \\not_strict_mode.app_rd_data_reg[153] ,\n \\not_strict_mode.app_rd_data_reg[137] ,\n \\not_strict_mode.app_rd_data_reg[145] ,\n \\not_strict_mode.app_rd_data_reg[129] ,\n \\not_strict_mode.app_rd_data_reg[152] ,\n \\not_strict_mode.app_rd_data_reg[136] ,\n \\not_strict_mode.app_rd_data_reg[144] ,\n \\not_strict_mode.app_rd_data_reg[128] ,\n \\not_strict_mode.app_rd_data_reg[127] ,\n \\not_strict_mode.app_rd_data_reg[111] ,\n \\not_strict_mode.app_rd_data_reg[119] ,\n \\not_strict_mode.app_rd_data_reg[103] ,\n \\not_strict_mode.app_rd_data_reg[126] ,\n \\not_strict_mode.app_rd_data_reg[110] ,\n \\not_strict_mode.app_rd_data_reg[118] ,\n \\not_strict_mode.app_rd_data_reg[102] ,\n \\not_strict_mode.app_rd_data_reg[125] ,\n \\not_strict_mode.app_rd_data_reg[109] ,\n \\not_strict_mode.app_rd_data_reg[117] ,\n \\not_strict_mode.app_rd_data_reg[101] ,\n \\not_strict_mode.app_rd_data_reg[124] ,\n \\not_strict_mode.app_rd_data_reg[108] ,\n \\not_strict_mode.app_rd_data_reg[116] ,\n \\not_strict_mode.app_rd_data_reg[100] ,\n \\not_strict_mode.app_rd_data_reg[123] ,\n \\not_strict_mode.app_rd_data_reg[107] ,\n \\not_strict_mode.app_rd_data_reg[115] ,\n \\not_strict_mode.app_rd_data_reg[99] ,\n \\not_strict_mode.app_rd_data_reg[122] ,\n \\not_strict_mode.app_rd_data_reg[106] ,\n \\not_strict_mode.app_rd_data_reg[114] ,\n \\not_strict_mode.app_rd_data_reg[98] ,\n \\not_strict_mode.app_rd_data_reg[121] ,\n \\not_strict_mode.app_rd_data_reg[105] ,\n \\not_strict_mode.app_rd_data_reg[113] ,\n \\not_strict_mode.app_rd_data_reg[97] ,\n \\not_strict_mode.app_rd_data_reg[120] ,\n \\not_strict_mode.app_rd_data_reg[104] ,\n \\not_strict_mode.app_rd_data_reg[112] ,\n \\not_strict_mode.app_rd_data_reg[96] ,\n \\not_strict_mode.app_rd_data_reg[95] ,\n \\not_strict_mode.app_rd_data_reg[79] ,\n \\not_strict_mode.app_rd_data_reg[87] ,\n \\not_strict_mode.app_rd_data_reg[71] ,\n \\not_strict_mode.app_rd_data_reg[94] ,\n \\not_strict_mode.app_rd_data_reg[78] ,\n \\not_strict_mode.app_rd_data_reg[86] ,\n \\not_strict_mode.app_rd_data_reg[70] ,\n \\not_strict_mode.app_rd_data_reg[93] ,\n \\not_strict_mode.app_rd_data_reg[77] ,\n \\not_strict_mode.app_rd_data_reg[85] ,\n \\not_strict_mode.app_rd_data_reg[69] ,\n \\not_strict_mode.app_rd_data_reg[92] ,\n \\not_strict_mode.app_rd_data_reg[76] ,\n \\not_strict_mode.app_rd_data_reg[84] ,\n \\not_strict_mode.app_rd_data_reg[68] ,\n \\not_strict_mode.app_rd_data_reg[91] ,\n \\not_strict_mode.app_rd_data_reg[75] ,\n \\not_strict_mode.app_rd_data_reg[83] ,\n \\not_strict_mode.app_rd_data_reg[67] ,\n \\not_strict_mode.app_rd_data_reg[90] ,\n \\not_strict_mode.app_rd_data_reg[74] ,\n \\not_strict_mode.app_rd_data_reg[82] ,\n \\not_strict_mode.app_rd_data_reg[66] ,\n \\not_strict_mode.app_rd_data_reg[89] ,\n \\not_strict_mode.app_rd_data_reg[73] ,\n \\not_strict_mode.app_rd_data_reg[81] ,\n \\not_strict_mode.app_rd_data_reg[65] ,\n \\not_strict_mode.app_rd_data_reg[88] ,\n \\not_strict_mode.app_rd_data_reg[72] ,\n \\not_strict_mode.app_rd_data_reg[80] ,\n \\not_strict_mode.app_rd_data_reg[64] ,\n \\not_strict_mode.app_rd_data_reg[63] ,\n \\not_strict_mode.app_rd_data_reg[47] ,\n \\not_strict_mode.app_rd_data_reg[55] ,\n \\not_strict_mode.app_rd_data_reg[39] ,\n \\not_strict_mode.app_rd_data_reg[62] ,\n \\not_strict_mode.app_rd_data_reg[46] ,\n \\not_strict_mode.app_rd_data_reg[54] ,\n \\not_strict_mode.app_rd_data_reg[38] ,\n \\not_strict_mode.app_rd_data_reg[61] ,\n \\not_strict_mode.app_rd_data_reg[45] ,\n \\not_strict_mode.app_rd_data_reg[53] ,\n \\not_strict_mode.app_rd_data_reg[37] ,\n \\not_strict_mode.app_rd_data_reg[60] ,\n \\not_strict_mode.app_rd_data_reg[44] ,\n \\not_strict_mode.app_rd_data_reg[52] ,\n \\not_strict_mode.app_rd_data_reg[36] ,\n \\not_strict_mode.app_rd_data_reg[59] ,\n \\not_strict_mode.app_rd_data_reg[43] ,\n \\not_strict_mode.app_rd_data_reg[51] ,\n \\not_strict_mode.app_rd_data_reg[35] ,\n \\not_strict_mode.app_rd_data_reg[58] ,\n \\not_strict_mode.app_rd_data_reg[42] ,\n \\not_strict_mode.app_rd_data_reg[50] ,\n \\not_strict_mode.app_rd_data_reg[34] ,\n \\not_strict_mode.app_rd_data_reg[57] ,\n \\not_strict_mode.app_rd_data_reg[41] ,\n \\not_strict_mode.app_rd_data_reg[49] ,\n \\not_strict_mode.app_rd_data_reg[33] ,\n \\not_strict_mode.app_rd_data_reg[56] ,\n \\not_strict_mode.app_rd_data_reg[40] ,\n \\not_strict_mode.app_rd_data_reg[48] ,\n \\not_strict_mode.app_rd_data_reg[32] ,\n \\not_strict_mode.app_rd_data_reg[31] ,\n \\not_strict_mode.app_rd_data_reg[15] ,\n \\not_strict_mode.app_rd_data_reg[23] ,\n \\not_strict_mode.app_rd_data_reg[7] ,\n \\not_strict_mode.app_rd_data_reg[30] ,\n \\not_strict_mode.app_rd_data_reg[14] ,\n \\not_strict_mode.app_rd_data_reg[22] ,\n \\not_strict_mode.app_rd_data_reg[6] ,\n \\not_strict_mode.app_rd_data_reg[29] ,\n \\not_strict_mode.app_rd_data_reg[13] ,\n \\not_strict_mode.app_rd_data_reg[21] ,\n \\not_strict_mode.app_rd_data_reg[5] ,\n \\not_strict_mode.app_rd_data_reg[28] ,\n \\not_strict_mode.app_rd_data_reg[12] ,\n \\not_strict_mode.app_rd_data_reg[20] ,\n \\not_strict_mode.app_rd_data_reg[4] ,\n \\not_strict_mode.app_rd_data_reg[27] ,\n \\not_strict_mode.app_rd_data_reg[11] ,\n \\not_strict_mode.app_rd_data_reg[19] ,\n \\not_strict_mode.app_rd_data_reg[3] ,\n \\not_strict_mode.app_rd_data_reg[26] ,\n \\not_strict_mode.app_rd_data_reg[10] ,\n \\not_strict_mode.app_rd_data_reg[18] ,\n \\not_strict_mode.app_rd_data_reg[2] ,\n \\not_strict_mode.app_rd_data_reg[25] ,\n \\not_strict_mode.app_rd_data_reg[9] ,\n \\not_strict_mode.app_rd_data_reg[17] ,\n \\not_strict_mode.app_rd_data_reg[1] ,\n \\not_strict_mode.app_rd_data_reg[24] ,\n \\not_strict_mode.app_rd_data_reg[8] ,\n \\not_strict_mode.app_rd_data_reg[16] ,\n \\not_strict_mode.app_rd_data_reg[0] ,\n \\en_cnt_div4.enable_wrlvl_cnt_reg[3] ,\n \\complex_row_cnt_ocal_reg[0] ,\n \\row_cnt_victim_rotate.complex_row_cnt_reg[4] ,\n pointer_we,\n \\not_strict_mode.app_rd_data_reg[255]_0 ,\n app_rd_data_end_ns,\n \\write_buffer.wr_buf_out_data_reg[287] ,\n \\wr_ptr_timing_reg[2] ,\n \\wr_ptr_timing_reg[2]_0 ,\n \\wr_ptr_timing_reg[2]_1 ,\n wr_en,\n wr_en_5,\n wr_en_6,\n ddr_ck_out,\n \\qcntr_r_reg[0] ,\n ddr3_dq,\n ddr3_dqs_p,\n ddr3_dqs_n,\n CLK,\n rstdiv0_sync_r1_reg_rep__0,\n hi_priority,\n SR,\n rstdiv0_sync_r1_reg_rep__20,\n rstdiv0_sync_r1_reg_rep__21,\n app_ref_req,\n app_zq_req,\n app_hi_pri_r2,\n use_addr,\n \\app_cmd_r1_reg[0] ,\n app_sr_req,\n rstdiv0_sync_r1_reg_rep__22,\n rstdiv0_sync_r1_reg_rep__23,\n mmcm_ps_clk,\n rst_sync_r1,\n poc_sample_pd,\n freq_refclk,\n mem_refclk,\n sync_pulse,\n pll_locked,\n in0,\n CLKB0,\n CLKB0_7,\n CLKB0_8,\n CLKB0_9,\n RST0,\n rstdiv0_sync_r1_reg_rep__9,\n rstdiv0_sync_r1_reg_rep__10,\n rstdiv0_sync_r1_reg_rep__12,\n rstdiv0_sync_r1_reg_rep__2,\n rstdiv0_sync_r1_reg_rep__24,\n rstdiv0_sync_r1_reg_rep__13,\n rstdiv0_sync_r1_reg_rep__14,\n rstdiv0_sync_r1_reg_rep__11,\n cnt_pwron_reset_done_r0,\n rstdiv0_sync_r1_reg_rep__18,\n rstdiv0_sync_r1_reg_rep__16,\n SS,\n rstdiv0_sync_r1_reg_rep__7,\n Q,\n mem_out,\n \\rd_ptr_reg[3] ,\n rstdiv0_sync_r1_reg_rep__26,\n rstdiv0_sync_r1_reg_rep__26_0,\n rstdiv0_sync_r1_reg_rep__25,\n \\sm_r_reg[0]_0 ,\n \\rd_ptr_reg[3]_0 ,\n \\req_bank_r_lcl_reg[2] ,\n \\req_bank_r_lcl_reg[2]_0 ,\n \\req_bank_r_lcl_reg[0] ,\n \\req_bank_r_lcl_reg[0]_0 ,\n \\rd_buf_indx.rd_buf_indx_r_reg[4] ,\n ram_init_done_r,\n sys_rst,\n \\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ,\n mmcm_locked,\n rstdiv0_sync_r1_reg_rep__26_1,\n rstdiv0_sync_r1_reg_rep__26_2,\n \\mmcm_init_trail_reg[0] ,\n \\mmcm_current_reg[0] ,\n bm_end_r1_reg,\n bm_end_r1_reg_0,\n bm_end_r1_reg_1,\n pass_open_bank_r_lcl_reg,\n \\app_cmd_r2_reg[1] ,\n bm_end_r1_reg_2,\n rtp_timer_ns1,\n rtp_timer_ns1_6,\n rtp_timer_ns1_7,\n \\app_addr_r1_reg[27] ,\n DOC,\n DOB,\n DOA,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ,\n \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ,\n \\not_strict_mode.status_ram.rd_buf_we_r1_reg ,\n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ,\n \\app_addr_r1_reg[12] ,\n \\app_addr_r1_reg[9] ,\n psdone,\n rstdiv0_sync_r1_reg_rep__19,\n fine_adjust_reg,\n samp_edge_cnt0_en_r_reg,\n pi_cnt_dec_reg,\n rstdiv0_sync_r1_reg_rep__24_0,\n p_81_in,\n rstdiv0_sync_r1_reg_rep__24_1,\n rstdiv0_sync_r1_reg_rep__17,\n po_cnt_dec_reg,\n rstdiv0_sync_r1_reg_rep__5,\n \\device_temp_r_reg[11] ,\n rstdiv0_sync_r1_reg_rep__4,\n rstdiv0_sync_r1_reg_rep__6,\n \\stg3_r_reg[0] ,\n rstdiv0_sync_r1_reg_rep__8);\n output accept_ns;\n output bm_end_r1;\n output act_wait_r_lcl_reg;\n output bm_end_r1_0;\n output act_wait_r_lcl_reg_0;\n output \\ras_timer_r_reg[2] ;\n output act_wait_r_lcl_reg_1;\n output bm_end_r1_4;\n output act_wait_r_lcl_reg_2;\n output app_ref_ack;\n output app_zq_ack;\n output [0:0]E;\n output app_sr_active;\n output [11:0]req_bank_r;\n output ddr3_reset_n;\n output ddr3_cas_n;\n output ddr3_ras_n;\n output ddr3_we_n;\n output [14:0]ddr3_addr;\n output [2:0]ddr3_ba;\n output [0:0]ddr3_cs_n;\n output [0:0]ddr3_odt;\n output [0:0]ddr3_cke;\n output [3:0]ddr3_dm;\n output \\rd_ptr_timing_reg[2] ;\n output \\rd_ptr_timing_reg[2]_0 ;\n output \\rd_ptr_timing_reg[2]_1 ;\n output \\rd_ptr_timing_reg[2]_2 ;\n output \\rd_ptr_timing_reg[2]_3 ;\n output \\rd_ptr_timing_reg[2]_4 ;\n output \\rd_ptr_timing_reg[2]_5 ;\n output \\rd_ptr_timing_reg[2]_6 ;\n output \\rd_ptr_timing_reg[2]_7 ;\n output \\rd_ptr_timing_reg[2]_8 ;\n output \\rd_ptr_timing_reg[2]_9 ;\n output \\rd_ptr_timing_reg[2]_10 ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;\n output [5:0]phy_dout;\n output \\samps_r_reg[9] ;\n output init_calib_complete_r_reg;\n output \\calib_seq_reg[0] ;\n output \\pi_rst_stg1_cal_r_reg[0] ;\n output samp_edge_cnt0_en_r;\n output pi_en_stg2_f_timing_reg;\n output dqs_po_en_stg2_f_reg;\n output [37:0]\\rd_ptr_timing_reg[0] ;\n output [4:0]\\rd_ptr_timing_reg[0]_0 ;\n output [0:0]\\resume_wait_r_reg[5] ;\n output stg3_dec2init_val_r_reg;\n output stg3_inc2init_val_r_reg;\n output bypass__0;\n output [6:0]\\not_strict_mode.app_rd_data_end_reg ;\n output rd_buf_we;\n output rst_sync_r1_reg;\n output \\stg2_tap_cnt_reg[0] ;\n output \\sm_r_reg[0] ;\n output [0:0]D;\n output \\not_strict_mode.app_rd_data_reg[255] ;\n output \\not_strict_mode.app_rd_data_reg[239] ;\n output \\not_strict_mode.app_rd_data_reg[247] ;\n output \\not_strict_mode.app_rd_data_reg[231] ;\n output \\not_strict_mode.app_rd_data_reg[254] ;\n output \\not_strict_mode.app_rd_data_reg[238] ;\n output \\not_strict_mode.app_rd_data_reg[246] ;\n output \\not_strict_mode.app_rd_data_reg[230] ;\n output \\not_strict_mode.app_rd_data_reg[253] ;\n output \\not_strict_mode.app_rd_data_reg[237] ;\n output \\not_strict_mode.app_rd_data_reg[245] ;\n output \\not_strict_mode.app_rd_data_reg[229] ;\n output \\not_strict_mode.app_rd_data_reg[252] ;\n output \\not_strict_mode.app_rd_data_reg[236] ;\n output \\not_strict_mode.app_rd_data_reg[244] ;\n output \\not_strict_mode.app_rd_data_reg[228] ;\n output \\not_strict_mode.app_rd_data_reg[251] ;\n output \\not_strict_mode.app_rd_data_reg[235] ;\n output \\not_strict_mode.app_rd_data_reg[243] ;\n output \\not_strict_mode.app_rd_data_reg[227] ;\n output \\not_strict_mode.app_rd_data_reg[250] ;\n output \\not_strict_mode.app_rd_data_reg[234] ;\n output \\not_strict_mode.app_rd_data_reg[242] ;\n output \\not_strict_mode.app_rd_data_reg[226] ;\n output \\not_strict_mode.app_rd_data_reg[249] ;\n output \\not_strict_mode.app_rd_data_reg[233] ;\n output \\not_strict_mode.app_rd_data_reg[241] ;\n output \\not_strict_mode.app_rd_data_reg[225] ;\n output \\not_strict_mode.app_rd_data_reg[248] ;\n output \\not_strict_mode.app_rd_data_reg[232] ;\n output \\not_strict_mode.app_rd_data_reg[240] ;\n output \\not_strict_mode.app_rd_data_reg[224] ;\n output \\not_strict_mode.app_rd_data_reg[223] ;\n output \\not_strict_mode.app_rd_data_reg[207] ;\n output \\not_strict_mode.app_rd_data_reg[215] ;\n output \\not_strict_mode.app_rd_data_reg[199] ;\n output \\not_strict_mode.app_rd_data_reg[222] ;\n output \\not_strict_mode.app_rd_data_reg[206] ;\n output \\not_strict_mode.app_rd_data_reg[214] ;\n output \\not_strict_mode.app_rd_data_reg[198] ;\n output \\not_strict_mode.app_rd_data_reg[221] ;\n output \\not_strict_mode.app_rd_data_reg[205] ;\n output \\not_strict_mode.app_rd_data_reg[213] ;\n output \\not_strict_mode.app_rd_data_reg[197] ;\n output \\not_strict_mode.app_rd_data_reg[220] ;\n output \\not_strict_mode.app_rd_data_reg[204] ;\n output \\not_strict_mode.app_rd_data_reg[212] ;\n output \\not_strict_mode.app_rd_data_reg[196] ;\n output \\not_strict_mode.app_rd_data_reg[219] ;\n output \\not_strict_mode.app_rd_data_reg[203] ;\n output \\not_strict_mode.app_rd_data_reg[211] ;\n output \\not_strict_mode.app_rd_data_reg[195] ;\n output \\not_strict_mode.app_rd_data_reg[218] ;\n output \\not_strict_mode.app_rd_data_reg[202] ;\n output \\not_strict_mode.app_rd_data_reg[210] ;\n output \\not_strict_mode.app_rd_data_reg[194] ;\n output \\not_strict_mode.app_rd_data_reg[217] ;\n output \\not_strict_mode.app_rd_data_reg[201] ;\n output \\not_strict_mode.app_rd_data_reg[209] ;\n output \\not_strict_mode.app_rd_data_reg[193] ;\n output \\not_strict_mode.app_rd_data_reg[216] ;\n output \\not_strict_mode.app_rd_data_reg[200] ;\n output \\not_strict_mode.app_rd_data_reg[208] ;\n output \\not_strict_mode.app_rd_data_reg[192] ;\n output \\not_strict_mode.app_rd_data_reg[191] ;\n output \\not_strict_mode.app_rd_data_reg[175] ;\n output \\not_strict_mode.app_rd_data_reg[183] ;\n output \\not_strict_mode.app_rd_data_reg[167] ;\n output \\not_strict_mode.app_rd_data_reg[190] ;\n output \\not_strict_mode.app_rd_data_reg[174] ;\n output \\not_strict_mode.app_rd_data_reg[182] ;\n output \\not_strict_mode.app_rd_data_reg[166] ;\n output \\not_strict_mode.app_rd_data_reg[189] ;\n output \\not_strict_mode.app_rd_data_reg[173] ;\n output \\not_strict_mode.app_rd_data_reg[181] ;\n output \\not_strict_mode.app_rd_data_reg[165] ;\n output \\not_strict_mode.app_rd_data_reg[188] ;\n output \\not_strict_mode.app_rd_data_reg[172] ;\n output \\not_strict_mode.app_rd_data_reg[180] ;\n output \\not_strict_mode.app_rd_data_reg[164] ;\n output \\not_strict_mode.app_rd_data_reg[187] ;\n output \\not_strict_mode.app_rd_data_reg[171] ;\n output \\not_strict_mode.app_rd_data_reg[179] ;\n output \\not_strict_mode.app_rd_data_reg[163] ;\n output \\not_strict_mode.app_rd_data_reg[186] ;\n output \\not_strict_mode.app_rd_data_reg[170] ;\n output \\not_strict_mode.app_rd_data_reg[178] ;\n output \\not_strict_mode.app_rd_data_reg[162] ;\n output \\not_strict_mode.app_rd_data_reg[185] ;\n output \\not_strict_mode.app_rd_data_reg[169] ;\n output \\not_strict_mode.app_rd_data_reg[177] ;\n output \\not_strict_mode.app_rd_data_reg[161] ;\n output \\not_strict_mode.app_rd_data_reg[184] ;\n output \\not_strict_mode.app_rd_data_reg[168] ;\n output \\not_strict_mode.app_rd_data_reg[176] ;\n output \\not_strict_mode.app_rd_data_reg[160] ;\n output \\not_strict_mode.app_rd_data_reg[159] ;\n output \\not_strict_mode.app_rd_data_reg[143] ;\n output \\not_strict_mode.app_rd_data_reg[151] ;\n output \\not_strict_mode.app_rd_data_reg[135] ;\n output \\not_strict_mode.app_rd_data_reg[158] ;\n output \\not_strict_mode.app_rd_data_reg[142] ;\n output \\not_strict_mode.app_rd_data_reg[150] ;\n output \\not_strict_mode.app_rd_data_reg[134] ;\n output \\not_strict_mode.app_rd_data_reg[157] ;\n output \\not_strict_mode.app_rd_data_reg[141] ;\n output \\not_strict_mode.app_rd_data_reg[149] ;\n output \\not_strict_mode.app_rd_data_reg[133] ;\n output \\not_strict_mode.app_rd_data_reg[156] ;\n output \\not_strict_mode.app_rd_data_reg[140] ;\n output \\not_strict_mode.app_rd_data_reg[148] ;\n output \\not_strict_mode.app_rd_data_reg[132] ;\n output \\not_strict_mode.app_rd_data_reg[155] ;\n output \\not_strict_mode.app_rd_data_reg[139] ;\n output \\not_strict_mode.app_rd_data_reg[147] ;\n output \\not_strict_mode.app_rd_data_reg[131] ;\n output \\not_strict_mode.app_rd_data_reg[154] ;\n output \\not_strict_mode.app_rd_data_reg[138] ;\n output \\not_strict_mode.app_rd_data_reg[146] ;\n output \\not_strict_mode.app_rd_data_reg[130] ;\n output \\not_strict_mode.app_rd_data_reg[153] ;\n output \\not_strict_mode.app_rd_data_reg[137] ;\n output \\not_strict_mode.app_rd_data_reg[145] ;\n output \\not_strict_mode.app_rd_data_reg[129] ;\n output \\not_strict_mode.app_rd_data_reg[152] ;\n output \\not_strict_mode.app_rd_data_reg[136] ;\n output \\not_strict_mode.app_rd_data_reg[144] ;\n output \\not_strict_mode.app_rd_data_reg[128] ;\n output \\not_strict_mode.app_rd_data_reg[127] ;\n output \\not_strict_mode.app_rd_data_reg[111] ;\n output \\not_strict_mode.app_rd_data_reg[119] ;\n output \\not_strict_mode.app_rd_data_reg[103] ;\n output \\not_strict_mode.app_rd_data_reg[126] ;\n output \\not_strict_mode.app_rd_data_reg[110] ;\n output \\not_strict_mode.app_rd_data_reg[118] ;\n output \\not_strict_mode.app_rd_data_reg[102] ;\n output \\not_strict_mode.app_rd_data_reg[125] ;\n output \\not_strict_mode.app_rd_data_reg[109] ;\n output \\not_strict_mode.app_rd_data_reg[117] ;\n output \\not_strict_mode.app_rd_data_reg[101] ;\n output \\not_strict_mode.app_rd_data_reg[124] ;\n output \\not_strict_mode.app_rd_data_reg[108] ;\n output \\not_strict_mode.app_rd_data_reg[116] ;\n output \\not_strict_mode.app_rd_data_reg[100] ;\n output \\not_strict_mode.app_rd_data_reg[123] ;\n output \\not_strict_mode.app_rd_data_reg[107] ;\n output \\not_strict_mode.app_rd_data_reg[115] ;\n output \\not_strict_mode.app_rd_data_reg[99] ;\n output \\not_strict_mode.app_rd_data_reg[122] ;\n output \\not_strict_mode.app_rd_data_reg[106] ;\n output \\not_strict_mode.app_rd_data_reg[114] ;\n output \\not_strict_mode.app_rd_data_reg[98] ;\n output \\not_strict_mode.app_rd_data_reg[121] ;\n output \\not_strict_mode.app_rd_data_reg[105] ;\n output \\not_strict_mode.app_rd_data_reg[113] ;\n output \\not_strict_mode.app_rd_data_reg[97] ;\n output \\not_strict_mode.app_rd_data_reg[120] ;\n output \\not_strict_mode.app_rd_data_reg[104] ;\n output \\not_strict_mode.app_rd_data_reg[112] ;\n output \\not_strict_mode.app_rd_data_reg[96] ;\n output \\not_strict_mode.app_rd_data_reg[95] ;\n output \\not_strict_mode.app_rd_data_reg[79] ;\n output \\not_strict_mode.app_rd_data_reg[87] ;\n output \\not_strict_mode.app_rd_data_reg[71] ;\n output \\not_strict_mode.app_rd_data_reg[94] ;\n output \\not_strict_mode.app_rd_data_reg[78] ;\n output \\not_strict_mode.app_rd_data_reg[86] ;\n output \\not_strict_mode.app_rd_data_reg[70] ;\n output \\not_strict_mode.app_rd_data_reg[93] ;\n output \\not_strict_mode.app_rd_data_reg[77] ;\n output \\not_strict_mode.app_rd_data_reg[85] ;\n output \\not_strict_mode.app_rd_data_reg[69] ;\n output \\not_strict_mode.app_rd_data_reg[92] ;\n output \\not_strict_mode.app_rd_data_reg[76] ;\n output \\not_strict_mode.app_rd_data_reg[84] ;\n output \\not_strict_mode.app_rd_data_reg[68] ;\n output \\not_strict_mode.app_rd_data_reg[91] ;\n output \\not_strict_mode.app_rd_data_reg[75] ;\n output \\not_strict_mode.app_rd_data_reg[83] ;\n output \\not_strict_mode.app_rd_data_reg[67] ;\n output \\not_strict_mode.app_rd_data_reg[90] ;\n output \\not_strict_mode.app_rd_data_reg[74] ;\n output \\not_strict_mode.app_rd_data_reg[82] ;\n output \\not_strict_mode.app_rd_data_reg[66] ;\n output \\not_strict_mode.app_rd_data_reg[89] ;\n output \\not_strict_mode.app_rd_data_reg[73] ;\n output \\not_strict_mode.app_rd_data_reg[81] ;\n output \\not_strict_mode.app_rd_data_reg[65] ;\n output \\not_strict_mode.app_rd_data_reg[88] ;\n output \\not_strict_mode.app_rd_data_reg[72] ;\n output \\not_strict_mode.app_rd_data_reg[80] ;\n output \\not_strict_mode.app_rd_data_reg[64] ;\n output \\not_strict_mode.app_rd_data_reg[63] ;\n output \\not_strict_mode.app_rd_data_reg[47] ;\n output \\not_strict_mode.app_rd_data_reg[55] ;\n output \\not_strict_mode.app_rd_data_reg[39] ;\n output \\not_strict_mode.app_rd_data_reg[62] ;\n output \\not_strict_mode.app_rd_data_reg[46] ;\n output \\not_strict_mode.app_rd_data_reg[54] ;\n output \\not_strict_mode.app_rd_data_reg[38] ;\n output \\not_strict_mode.app_rd_data_reg[61] ;\n output \\not_strict_mode.app_rd_data_reg[45] ;\n output \\not_strict_mode.app_rd_data_reg[53] ;\n output \\not_strict_mode.app_rd_data_reg[37] ;\n output \\not_strict_mode.app_rd_data_reg[60] ;\n output \\not_strict_mode.app_rd_data_reg[44] ;\n output \\not_strict_mode.app_rd_data_reg[52] ;\n output \\not_strict_mode.app_rd_data_reg[36] ;\n output \\not_strict_mode.app_rd_data_reg[59] ;\n output \\not_strict_mode.app_rd_data_reg[43] ;\n output \\not_strict_mode.app_rd_data_reg[51] ;\n output \\not_strict_mode.app_rd_data_reg[35] ;\n output \\not_strict_mode.app_rd_data_reg[58] ;\n output \\not_strict_mode.app_rd_data_reg[42] ;\n output \\not_strict_mode.app_rd_data_reg[50] ;\n output \\not_strict_mode.app_rd_data_reg[34] ;\n output \\not_strict_mode.app_rd_data_reg[57] ;\n output \\not_strict_mode.app_rd_data_reg[41] ;\n output \\not_strict_mode.app_rd_data_reg[49] ;\n output \\not_strict_mode.app_rd_data_reg[33] ;\n output \\not_strict_mode.app_rd_data_reg[56] ;\n output \\not_strict_mode.app_rd_data_reg[40] ;\n output \\not_strict_mode.app_rd_data_reg[48] ;\n output \\not_strict_mode.app_rd_data_reg[32] ;\n output \\not_strict_mode.app_rd_data_reg[31] ;\n output \\not_strict_mode.app_rd_data_reg[15] ;\n output \\not_strict_mode.app_rd_data_reg[23] ;\n output \\not_strict_mode.app_rd_data_reg[7] ;\n output \\not_strict_mode.app_rd_data_reg[30] ;\n output \\not_strict_mode.app_rd_data_reg[14] ;\n output \\not_strict_mode.app_rd_data_reg[22] ;\n output \\not_strict_mode.app_rd_data_reg[6] ;\n output \\not_strict_mode.app_rd_data_reg[29] ;\n output \\not_strict_mode.app_rd_data_reg[13] ;\n output \\not_strict_mode.app_rd_data_reg[21] ;\n output \\not_strict_mode.app_rd_data_reg[5] ;\n output \\not_strict_mode.app_rd_data_reg[28] ;\n output \\not_strict_mode.app_rd_data_reg[12] ;\n output \\not_strict_mode.app_rd_data_reg[20] ;\n output \\not_strict_mode.app_rd_data_reg[4] ;\n output \\not_strict_mode.app_rd_data_reg[27] ;\n output \\not_strict_mode.app_rd_data_reg[11] ;\n output \\not_strict_mode.app_rd_data_reg[19] ;\n output \\not_strict_mode.app_rd_data_reg[3] ;\n output \\not_strict_mode.app_rd_data_reg[26] ;\n output \\not_strict_mode.app_rd_data_reg[10] ;\n output \\not_strict_mode.app_rd_data_reg[18] ;\n output \\not_strict_mode.app_rd_data_reg[2] ;\n output \\not_strict_mode.app_rd_data_reg[25] ;\n output \\not_strict_mode.app_rd_data_reg[9] ;\n output \\not_strict_mode.app_rd_data_reg[17] ;\n output \\not_strict_mode.app_rd_data_reg[1] ;\n output \\not_strict_mode.app_rd_data_reg[24] ;\n output \\not_strict_mode.app_rd_data_reg[8] ;\n output \\not_strict_mode.app_rd_data_reg[16] ;\n output \\not_strict_mode.app_rd_data_reg[0] ;\n output \\en_cnt_div4.enable_wrlvl_cnt_reg[3] ;\n output \\complex_row_cnt_ocal_reg[0] ;\n output \\row_cnt_victim_rotate.complex_row_cnt_reg[4] ;\n output pointer_we;\n output [255:0]\\not_strict_mode.app_rd_data_reg[255]_0 ;\n output app_rd_data_end_ns;\n output [3:0]\\write_buffer.wr_buf_out_data_reg[287] ;\n output [3:0]\\wr_ptr_timing_reg[2] ;\n output [3:0]\\wr_ptr_timing_reg[2]_0 ;\n output [3:0]\\wr_ptr_timing_reg[2]_1 ;\n output wr_en;\n output wr_en_5;\n output wr_en_6;\n output [1:0]ddr_ck_out;\n output [0:0]\\qcntr_r_reg[0] ;\n inout [31:0]ddr3_dq;\n inout [3:0]ddr3_dqs_p;\n inout [3:0]ddr3_dqs_n;\n input CLK;\n input rstdiv0_sync_r1_reg_rep__0;\n input hi_priority;\n input [0:0]SR;\n input rstdiv0_sync_r1_reg_rep__20;\n input rstdiv0_sync_r1_reg_rep__21;\n input app_ref_req;\n input app_zq_req;\n input app_hi_pri_r2;\n input use_addr;\n input \\app_cmd_r1_reg[0] ;\n input app_sr_req;\n input rstdiv0_sync_r1_reg_rep__22;\n input rstdiv0_sync_r1_reg_rep__23;\n input mmcm_ps_clk;\n input rst_sync_r1;\n input poc_sample_pd;\n input freq_refclk;\n input mem_refclk;\n input sync_pulse;\n input pll_locked;\n input in0;\n input CLKB0;\n input CLKB0_7;\n input CLKB0_8;\n input CLKB0_9;\n input RST0;\n input rstdiv0_sync_r1_reg_rep__9;\n input rstdiv0_sync_r1_reg_rep__10;\n input rstdiv0_sync_r1_reg_rep__12;\n input rstdiv0_sync_r1_reg_rep__2;\n input rstdiv0_sync_r1_reg_rep__24;\n input rstdiv0_sync_r1_reg_rep__13;\n input [1:0]rstdiv0_sync_r1_reg_rep__14;\n input [0:0]rstdiv0_sync_r1_reg_rep__11;\n input cnt_pwron_reset_done_r0;\n input [0:0]rstdiv0_sync_r1_reg_rep__18;\n input [0:0]rstdiv0_sync_r1_reg_rep__16;\n input [0:0]SS;\n input rstdiv0_sync_r1_reg_rep__7;\n input [287:0]Q;\n input [17:0]mem_out;\n input [71:0]\\rd_ptr_reg[3] ;\n input rstdiv0_sync_r1_reg_rep__26;\n input rstdiv0_sync_r1_reg_rep__26_0;\n input rstdiv0_sync_r1_reg_rep__25;\n input [0:0]\\sm_r_reg[0]_0 ;\n input [29:0]\\rd_ptr_reg[3]_0 ;\n input \\req_bank_r_lcl_reg[2] ;\n input \\req_bank_r_lcl_reg[2]_0 ;\n input \\req_bank_r_lcl_reg[0] ;\n input \\req_bank_r_lcl_reg[0]_0 ;\n input [4:0]\\rd_buf_indx.rd_buf_indx_r_reg[4] ;\n input ram_init_done_r;\n input sys_rst;\n input [0:0]\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ;\n input mmcm_locked;\n input rstdiv0_sync_r1_reg_rep__26_1;\n input rstdiv0_sync_r1_reg_rep__26_2;\n input \\mmcm_init_trail_reg[0] ;\n input \\mmcm_current_reg[0] ;\n input bm_end_r1_reg;\n input bm_end_r1_reg_0;\n input bm_end_r1_reg_1;\n input pass_open_bank_r_lcl_reg;\n input [0:0]\\app_cmd_r2_reg[1] ;\n input bm_end_r1_reg_2;\n input rtp_timer_ns1;\n input rtp_timer_ns1_6;\n input rtp_timer_ns1_7;\n input [14:0]\\app_addr_r1_reg[27] ;\n input [1:0]DOC;\n input [1:0]DOB;\n input [1:0]DOA;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ;\n input [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ;\n input [0:0]\\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n input [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n input [2:0]\\app_addr_r1_reg[12] ;\n input [6:0]\\app_addr_r1_reg[9] ;\n input psdone;\n input [0:0]rstdiv0_sync_r1_reg_rep__19;\n input fine_adjust_reg;\n input samp_edge_cnt0_en_r_reg;\n input [0:0]pi_cnt_dec_reg;\n input rstdiv0_sync_r1_reg_rep__24_0;\n input p_81_in;\n input rstdiv0_sync_r1_reg_rep__24_1;\n input [0:0]rstdiv0_sync_r1_reg_rep__17;\n input [0:0]po_cnt_dec_reg;\n input [0:0]rstdiv0_sync_r1_reg_rep__5;\n input [11:0]\\device_temp_r_reg[11] ;\n input rstdiv0_sync_r1_reg_rep__4;\n input rstdiv0_sync_r1_reg_rep__6;\n input \\stg3_r_reg[0] ;\n input rstdiv0_sync_r1_reg_rep__8;\n\n wire CLK;\n wire CLKB0;\n wire CLKB0_7;\n wire CLKB0_8;\n wire CLKB0_9;\n wire [0:0]D;\n wire [1:0]DOA;\n wire [1:0]DOB;\n wire [1:0]DOC;\n wire [0:0]E;\n wire [287:0]Q;\n wire RST0;\n wire [0:0]SR;\n wire [0:0]SS;\n wire accept_ns;\n wire act_wait_r_lcl_reg;\n wire act_wait_r_lcl_reg_0;\n wire act_wait_r_lcl_reg_1;\n wire act_wait_r_lcl_reg_2;\n wire [2:0]\\app_addr_r1_reg[12] ;\n wire [14:0]\\app_addr_r1_reg[27] ;\n wire [6:0]\\app_addr_r1_reg[9] ;\n wire \\app_cmd_r1_reg[0] ;\n wire [0:0]\\app_cmd_r2_reg[1] ;\n wire app_hi_pri_r2;\n wire app_rd_data_end_ns;\n wire app_ref_ack;\n wire app_ref_req;\n wire app_sr_active;\n wire app_sr_req;\n wire app_zq_ack;\n wire app_zq_req;\n wire bm_end_r1;\n wire bm_end_r1_0;\n wire bm_end_r1_4;\n wire bm_end_r1_reg;\n wire bm_end_r1_reg_0;\n wire bm_end_r1_reg_1;\n wire bm_end_r1_reg_2;\n wire bypass__0;\n wire \\calib_seq_reg[0] ;\n wire cnt_pwron_reset_done_r0;\n wire \\col_mach0/p_0_in ;\n wire \\complex_row_cnt_ocal_reg[0] ;\n wire [14:0]ddr3_addr;\n wire [2:0]ddr3_ba;\n wire ddr3_cas_n;\n wire [0:0]ddr3_cke;\n wire [0:0]ddr3_cs_n;\n wire [3:0]ddr3_dm;\n wire [31:0]ddr3_dq;\n wire [3:0]ddr3_dqs_n;\n wire [3:0]ddr3_dqs_p;\n wire [0:0]ddr3_odt;\n wire ddr3_ras_n;\n wire ddr3_reset_n;\n wire ddr3_we_n;\n wire [1:0]ddr_ck_out;\n wire ddr_phy_top0_n_359;\n wire ddr_phy_top0_n_360;\n wire ddr_phy_top0_n_361;\n wire ddr_phy_top0_n_362;\n wire ddr_phy_top0_n_363;\n wire ddr_phy_top0_n_364;\n wire ddr_phy_top0_n_365;\n wire ddr_phy_top0_n_366;\n wire ddr_phy_top0_n_367;\n wire ddr_phy_top0_n_368;\n wire ddr_phy_top0_n_369;\n wire ddr_phy_top0_n_370;\n wire ddr_phy_top0_n_371;\n wire ddr_phy_top0_n_372;\n wire ddr_phy_top0_n_373;\n wire ddr_phy_top0_n_374;\n wire ddr_phy_top0_n_375;\n wire ddr_phy_top0_n_376;\n wire ddr_phy_top0_n_377;\n wire ddr_phy_top0_n_378;\n wire ddr_phy_top0_n_379;\n wire ddr_phy_top0_n_380;\n wire ddr_phy_top0_n_381;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire ddr_phy_top0_n_50;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire ddr_phy_top0_n_51;\n wire ddr_phy_top0_n_641;\n wire ddr_phy_top0_n_642;\n wire ddr_phy_top0_n_97;\n wire [11:0]\\device_temp_r_reg[11] ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;\n wire dqs_po_en_stg2_f_reg;\n wire \\en_cnt_div4.enable_wrlvl_cnt_reg[3] ;\n wire fine_adjust_reg;\n wire freq_refclk;\n wire hi_priority;\n wire idle;\n wire in0;\n wire init_calib_complete_r_reg;\n wire mc0_n_117;\n wire mc0_n_118;\n wire mc0_n_119;\n wire mc0_n_120;\n wire mc0_n_121;\n wire mc0_n_122;\n wire mc0_n_123;\n wire mc0_n_124;\n wire mc0_n_125;\n wire mc0_n_126;\n wire mc0_n_127;\n wire mc0_n_128;\n wire [44:0]mc_address;\n wire [8:0]mc_bank;\n wire [2:0]mc_cas_n;\n wire [3:3]mc_cke;\n wire [1:0]mc_cmd;\n wire [0:0]mc_cs_n;\n wire [0:0]mc_odt;\n wire [2:0]mc_ras_n;\n wire [2:0]mc_we_n;\n wire mc_wrdata_en;\n wire [17:0]mem_out;\n wire mem_refclk;\n wire \\mmcm_current_reg[0] ;\n wire \\mmcm_init_trail_reg[0] ;\n wire mmcm_locked;\n wire mmcm_ps_clk;\n wire [43:13]mux_address;\n wire [6:0]\\not_strict_mode.app_rd_data_end_reg ;\n wire \\not_strict_mode.app_rd_data_reg[0] ;\n wire \\not_strict_mode.app_rd_data_reg[100] ;\n wire \\not_strict_mode.app_rd_data_reg[101] ;\n wire \\not_strict_mode.app_rd_data_reg[102] ;\n wire \\not_strict_mode.app_rd_data_reg[103] ;\n wire \\not_strict_mode.app_rd_data_reg[104] ;\n wire \\not_strict_mode.app_rd_data_reg[105] ;\n wire \\not_strict_mode.app_rd_data_reg[106] ;\n wire \\not_strict_mode.app_rd_data_reg[107] ;\n wire \\not_strict_mode.app_rd_data_reg[108] ;\n wire \\not_strict_mode.app_rd_data_reg[109] ;\n wire \\not_strict_mode.app_rd_data_reg[10] ;\n wire \\not_strict_mode.app_rd_data_reg[110] ;\n wire \\not_strict_mode.app_rd_data_reg[111] ;\n wire \\not_strict_mode.app_rd_data_reg[112] ;\n wire \\not_strict_mode.app_rd_data_reg[113] ;\n wire \\not_strict_mode.app_rd_data_reg[114] ;\n wire \\not_strict_mode.app_rd_data_reg[115] ;\n wire \\not_strict_mode.app_rd_data_reg[116] ;\n wire \\not_strict_mode.app_rd_data_reg[117] ;\n wire \\not_strict_mode.app_rd_data_reg[118] ;\n wire \\not_strict_mode.app_rd_data_reg[119] ;\n wire \\not_strict_mode.app_rd_data_reg[11] ;\n wire \\not_strict_mode.app_rd_data_reg[120] ;\n wire \\not_strict_mode.app_rd_data_reg[121] ;\n wire \\not_strict_mode.app_rd_data_reg[122] ;\n wire \\not_strict_mode.app_rd_data_reg[123] ;\n wire \\not_strict_mode.app_rd_data_reg[124] ;\n wire \\not_strict_mode.app_rd_data_reg[125] ;\n wire \\not_strict_mode.app_rd_data_reg[126] ;\n wire \\not_strict_mode.app_rd_data_reg[127] ;\n wire \\not_strict_mode.app_rd_data_reg[128] ;\n wire \\not_strict_mode.app_rd_data_reg[129] ;\n wire \\not_strict_mode.app_rd_data_reg[12] ;\n wire \\not_strict_mode.app_rd_data_reg[130] ;\n wire \\not_strict_mode.app_rd_data_reg[131] ;\n wire \\not_strict_mode.app_rd_data_reg[132] ;\n wire \\not_strict_mode.app_rd_data_reg[133] ;\n wire \\not_strict_mode.app_rd_data_reg[134] ;\n wire \\not_strict_mode.app_rd_data_reg[135] ;\n wire \\not_strict_mode.app_rd_data_reg[136] ;\n wire \\not_strict_mode.app_rd_data_reg[137] ;\n wire \\not_strict_mode.app_rd_data_reg[138] ;\n wire \\not_strict_mode.app_rd_data_reg[139] ;\n wire \\not_strict_mode.app_rd_data_reg[13] ;\n wire \\not_strict_mode.app_rd_data_reg[140] ;\n wire \\not_strict_mode.app_rd_data_reg[141] ;\n wire \\not_strict_mode.app_rd_data_reg[142] ;\n wire \\not_strict_mode.app_rd_data_reg[143] ;\n wire \\not_strict_mode.app_rd_data_reg[144] ;\n wire \\not_strict_mode.app_rd_data_reg[145] ;\n wire \\not_strict_mode.app_rd_data_reg[146] ;\n wire \\not_strict_mode.app_rd_data_reg[147] ;\n wire \\not_strict_mode.app_rd_data_reg[148] ;\n wire \\not_strict_mode.app_rd_data_reg[149] ;\n wire \\not_strict_mode.app_rd_data_reg[14] ;\n wire \\not_strict_mode.app_rd_data_reg[150] ;\n wire \\not_strict_mode.app_rd_data_reg[151] ;\n wire \\not_strict_mode.app_rd_data_reg[152] ;\n wire \\not_strict_mode.app_rd_data_reg[153] ;\n wire \\not_strict_mode.app_rd_data_reg[154] ;\n wire \\not_strict_mode.app_rd_data_reg[155] ;\n wire \\not_strict_mode.app_rd_data_reg[156] ;\n wire \\not_strict_mode.app_rd_data_reg[157] ;\n wire \\not_strict_mode.app_rd_data_reg[158] ;\n wire \\not_strict_mode.app_rd_data_reg[159] ;\n wire \\not_strict_mode.app_rd_data_reg[15] ;\n wire \\not_strict_mode.app_rd_data_reg[160] ;\n wire \\not_strict_mode.app_rd_data_reg[161] ;\n wire \\not_strict_mode.app_rd_data_reg[162] ;\n wire \\not_strict_mode.app_rd_data_reg[163] ;\n wire \\not_strict_mode.app_rd_data_reg[164] ;\n wire \\not_strict_mode.app_rd_data_reg[165] ;\n wire \\not_strict_mode.app_rd_data_reg[166] ;\n wire \\not_strict_mode.app_rd_data_reg[167] ;\n wire \\not_strict_mode.app_rd_data_reg[168] ;\n wire \\not_strict_mode.app_rd_data_reg[169] ;\n wire \\not_strict_mode.app_rd_data_reg[16] ;\n wire \\not_strict_mode.app_rd_data_reg[170] ;\n wire \\not_strict_mode.app_rd_data_reg[171] ;\n wire \\not_strict_mode.app_rd_data_reg[172] ;\n wire \\not_strict_mode.app_rd_data_reg[173] ;\n wire \\not_strict_mode.app_rd_data_reg[174] ;\n wire \\not_strict_mode.app_rd_data_reg[175] ;\n wire \\not_strict_mode.app_rd_data_reg[176] ;\n wire \\not_strict_mode.app_rd_data_reg[177] ;\n wire \\not_strict_mode.app_rd_data_reg[178] ;\n wire \\not_strict_mode.app_rd_data_reg[179] ;\n wire \\not_strict_mode.app_rd_data_reg[17] ;\n wire \\not_strict_mode.app_rd_data_reg[180] ;\n wire \\not_strict_mode.app_rd_data_reg[181] ;\n wire \\not_strict_mode.app_rd_data_reg[182] ;\n wire \\not_strict_mode.app_rd_data_reg[183] ;\n wire \\not_strict_mode.app_rd_data_reg[184] ;\n wire \\not_strict_mode.app_rd_data_reg[185] ;\n wire \\not_strict_mode.app_rd_data_reg[186] ;\n wire \\not_strict_mode.app_rd_data_reg[187] ;\n wire \\not_strict_mode.app_rd_data_reg[188] ;\n wire \\not_strict_mode.app_rd_data_reg[189] ;\n wire \\not_strict_mode.app_rd_data_reg[18] ;\n wire \\not_strict_mode.app_rd_data_reg[190] ;\n wire \\not_strict_mode.app_rd_data_reg[191] ;\n wire \\not_strict_mode.app_rd_data_reg[192] ;\n wire \\not_strict_mode.app_rd_data_reg[193] ;\n wire \\not_strict_mode.app_rd_data_reg[194] ;\n wire \\not_strict_mode.app_rd_data_reg[195] ;\n wire \\not_strict_mode.app_rd_data_reg[196] ;\n wire \\not_strict_mode.app_rd_data_reg[197] ;\n wire \\not_strict_mode.app_rd_data_reg[198] ;\n wire \\not_strict_mode.app_rd_data_reg[199] ;\n wire \\not_strict_mode.app_rd_data_reg[19] ;\n wire \\not_strict_mode.app_rd_data_reg[1] ;\n wire \\not_strict_mode.app_rd_data_reg[200] ;\n wire \\not_strict_mode.app_rd_data_reg[201] ;\n wire \\not_strict_mode.app_rd_data_reg[202] ;\n wire \\not_strict_mode.app_rd_data_reg[203] ;\n wire \\not_strict_mode.app_rd_data_reg[204] ;\n wire \\not_strict_mode.app_rd_data_reg[205] ;\n wire \\not_strict_mode.app_rd_data_reg[206] ;\n wire \\not_strict_mode.app_rd_data_reg[207] ;\n wire \\not_strict_mode.app_rd_data_reg[208] ;\n wire \\not_strict_mode.app_rd_data_reg[209] ;\n wire \\not_strict_mode.app_rd_data_reg[20] ;\n wire \\not_strict_mode.app_rd_data_reg[210] ;\n wire \\not_strict_mode.app_rd_data_reg[211] ;\n wire \\not_strict_mode.app_rd_data_reg[212] ;\n wire \\not_strict_mode.app_rd_data_reg[213] ;\n wire \\not_strict_mode.app_rd_data_reg[214] ;\n wire \\not_strict_mode.app_rd_data_reg[215] ;\n wire \\not_strict_mode.app_rd_data_reg[216] ;\n wire \\not_strict_mode.app_rd_data_reg[217] ;\n wire \\not_strict_mode.app_rd_data_reg[218] ;\n wire \\not_strict_mode.app_rd_data_reg[219] ;\n wire \\not_strict_mode.app_rd_data_reg[21] ;\n wire \\not_strict_mode.app_rd_data_reg[220] ;\n wire \\not_strict_mode.app_rd_data_reg[221] ;\n wire \\not_strict_mode.app_rd_data_reg[222] ;\n wire \\not_strict_mode.app_rd_data_reg[223] ;\n wire \\not_strict_mode.app_rd_data_reg[224] ;\n wire \\not_strict_mode.app_rd_data_reg[225] ;\n wire \\not_strict_mode.app_rd_data_reg[226] ;\n wire \\not_strict_mode.app_rd_data_reg[227] ;\n wire \\not_strict_mode.app_rd_data_reg[228] ;\n wire \\not_strict_mode.app_rd_data_reg[229] ;\n wire \\not_strict_mode.app_rd_data_reg[22] ;\n wire \\not_strict_mode.app_rd_data_reg[230] ;\n wire \\not_strict_mode.app_rd_data_reg[231] ;\n wire \\not_strict_mode.app_rd_data_reg[232] ;\n wire \\not_strict_mode.app_rd_data_reg[233] ;\n wire \\not_strict_mode.app_rd_data_reg[234] ;\n wire \\not_strict_mode.app_rd_data_reg[235] ;\n wire \\not_strict_mode.app_rd_data_reg[236] ;\n wire \\not_strict_mode.app_rd_data_reg[237] ;\n wire \\not_strict_mode.app_rd_data_reg[238] ;\n wire \\not_strict_mode.app_rd_data_reg[239] ;\n wire \\not_strict_mode.app_rd_data_reg[23] ;\n wire \\not_strict_mode.app_rd_data_reg[240] ;\n wire \\not_strict_mode.app_rd_data_reg[241] ;\n wire \\not_strict_mode.app_rd_data_reg[242] ;\n wire \\not_strict_mode.app_rd_data_reg[243] ;\n wire \\not_strict_mode.app_rd_data_reg[244] ;\n wire \\not_strict_mode.app_rd_data_reg[245] ;\n wire \\not_strict_mode.app_rd_data_reg[246] ;\n wire \\not_strict_mode.app_rd_data_reg[247] ;\n wire \\not_strict_mode.app_rd_data_reg[248] ;\n wire \\not_strict_mode.app_rd_data_reg[249] ;\n wire \\not_strict_mode.app_rd_data_reg[24] ;\n wire \\not_strict_mode.app_rd_data_reg[250] ;\n wire \\not_strict_mode.app_rd_data_reg[251] ;\n wire \\not_strict_mode.app_rd_data_reg[252] ;\n wire \\not_strict_mode.app_rd_data_reg[253] ;\n wire \\not_strict_mode.app_rd_data_reg[254] ;\n wire \\not_strict_mode.app_rd_data_reg[255] ;\n wire [255:0]\\not_strict_mode.app_rd_data_reg[255]_0 ;\n wire \\not_strict_mode.app_rd_data_reg[25] ;\n wire \\not_strict_mode.app_rd_data_reg[26] ;\n wire \\not_strict_mode.app_rd_data_reg[27] ;\n wire \\not_strict_mode.app_rd_data_reg[28] ;\n wire \\not_strict_mode.app_rd_data_reg[29] ;\n wire \\not_strict_mode.app_rd_data_reg[2] ;\n wire \\not_strict_mode.app_rd_data_reg[30] ;\n wire \\not_strict_mode.app_rd_data_reg[31] ;\n wire \\not_strict_mode.app_rd_data_reg[32] ;\n wire \\not_strict_mode.app_rd_data_reg[33] ;\n wire \\not_strict_mode.app_rd_data_reg[34] ;\n wire \\not_strict_mode.app_rd_data_reg[35] ;\n wire \\not_strict_mode.app_rd_data_reg[36] ;\n wire \\not_strict_mode.app_rd_data_reg[37] ;\n wire \\not_strict_mode.app_rd_data_reg[38] ;\n wire \\not_strict_mode.app_rd_data_reg[39] ;\n wire \\not_strict_mode.app_rd_data_reg[3] ;\n wire \\not_strict_mode.app_rd_data_reg[40] ;\n wire \\not_strict_mode.app_rd_data_reg[41] ;\n wire \\not_strict_mode.app_rd_data_reg[42] ;\n wire \\not_strict_mode.app_rd_data_reg[43] ;\n wire \\not_strict_mode.app_rd_data_reg[44] ;\n wire \\not_strict_mode.app_rd_data_reg[45] ;\n wire \\not_strict_mode.app_rd_data_reg[46] ;\n wire \\not_strict_mode.app_rd_data_reg[47] ;\n wire \\not_strict_mode.app_rd_data_reg[48] ;\n wire \\not_strict_mode.app_rd_data_reg[49] ;\n wire \\not_strict_mode.app_rd_data_reg[4] ;\n wire \\not_strict_mode.app_rd_data_reg[50] ;\n wire \\not_strict_mode.app_rd_data_reg[51] ;\n wire \\not_strict_mode.app_rd_data_reg[52] ;\n wire \\not_strict_mode.app_rd_data_reg[53] ;\n wire \\not_strict_mode.app_rd_data_reg[54] ;\n wire \\not_strict_mode.app_rd_data_reg[55] ;\n wire \\not_strict_mode.app_rd_data_reg[56] ;\n wire \\not_strict_mode.app_rd_data_reg[57] ;\n wire \\not_strict_mode.app_rd_data_reg[58] ;\n wire \\not_strict_mode.app_rd_data_reg[59] ;\n wire \\not_strict_mode.app_rd_data_reg[5] ;\n wire \\not_strict_mode.app_rd_data_reg[60] ;\n wire \\not_strict_mode.app_rd_data_reg[61] ;\n wire \\not_strict_mode.app_rd_data_reg[62] ;\n wire \\not_strict_mode.app_rd_data_reg[63] ;\n wire \\not_strict_mode.app_rd_data_reg[64] ;\n wire \\not_strict_mode.app_rd_data_reg[65] ;\n wire \\not_strict_mode.app_rd_data_reg[66] ;\n wire \\not_strict_mode.app_rd_data_reg[67] ;\n wire \\not_strict_mode.app_rd_data_reg[68] ;\n wire \\not_strict_mode.app_rd_data_reg[69] ;\n wire \\not_strict_mode.app_rd_data_reg[6] ;\n wire \\not_strict_mode.app_rd_data_reg[70] ;\n wire \\not_strict_mode.app_rd_data_reg[71] ;\n wire \\not_strict_mode.app_rd_data_reg[72] ;\n wire \\not_strict_mode.app_rd_data_reg[73] ;\n wire \\not_strict_mode.app_rd_data_reg[74] ;\n wire \\not_strict_mode.app_rd_data_reg[75] ;\n wire \\not_strict_mode.app_rd_data_reg[76] ;\n wire \\not_strict_mode.app_rd_data_reg[77] ;\n wire \\not_strict_mode.app_rd_data_reg[78] ;\n wire \\not_strict_mode.app_rd_data_reg[79] ;\n wire \\not_strict_mode.app_rd_data_reg[7] ;\n wire \\not_strict_mode.app_rd_data_reg[80] ;\n wire \\not_strict_mode.app_rd_data_reg[81] ;\n wire \\not_strict_mode.app_rd_data_reg[82] ;\n wire \\not_strict_mode.app_rd_data_reg[83] ;\n wire \\not_strict_mode.app_rd_data_reg[84] ;\n wire \\not_strict_mode.app_rd_data_reg[85] ;\n wire \\not_strict_mode.app_rd_data_reg[86] ;\n wire \\not_strict_mode.app_rd_data_reg[87] ;\n wire \\not_strict_mode.app_rd_data_reg[88] ;\n wire \\not_strict_mode.app_rd_data_reg[89] ;\n wire \\not_strict_mode.app_rd_data_reg[8] ;\n wire \\not_strict_mode.app_rd_data_reg[90] ;\n wire \\not_strict_mode.app_rd_data_reg[91] ;\n wire \\not_strict_mode.app_rd_data_reg[92] ;\n wire \\not_strict_mode.app_rd_data_reg[93] ;\n wire \\not_strict_mode.app_rd_data_reg[94] ;\n wire \\not_strict_mode.app_rd_data_reg[95] ;\n wire \\not_strict_mode.app_rd_data_reg[96] ;\n wire \\not_strict_mode.app_rd_data_reg[97] ;\n wire \\not_strict_mode.app_rd_data_reg[98] ;\n wire \\not_strict_mode.app_rd_data_reg[99] ;\n wire \\not_strict_mode.app_rd_data_reg[9] ;\n wire [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ;\n wire [1:0]\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ;\n wire [0:0]\\not_strict_mode.status_ram.rd_buf_we_r1_reg ;\n wire p_81_in;\n wire pass_open_bank_r_lcl_reg;\n wire [5:0]phy_dout;\n wire phy_mc_ctl_full;\n wire [0:0]pi_cnt_dec_reg;\n wire pi_en_stg2_f_timing_reg;\n wire \\pi_rst_stg1_cal_r_reg[0] ;\n wire pll_locked;\n wire [0:0]po_cnt_dec_reg;\n wire poc_sample_pd;\n wire pointer_we;\n wire psdone;\n wire [0:0]\\qcntr_r_reg[0] ;\n wire ram_init_done_r;\n wire \\rank_mach0/rank_common0/maint_prescaler_r1 ;\n wire \\ras_timer_r_reg[2] ;\n wire [4:0]\\rd_buf_indx.rd_buf_indx_r_reg[4] ;\n wire rd_buf_we;\n wire [71:0]\\rd_ptr_reg[3] ;\n wire [29:0]\\rd_ptr_reg[3]_0 ;\n wire [37:0]\\rd_ptr_timing_reg[0] ;\n wire [4:0]\\rd_ptr_timing_reg[0]_0 ;\n wire \\rd_ptr_timing_reg[2] ;\n wire \\rd_ptr_timing_reg[2]_0 ;\n wire \\rd_ptr_timing_reg[2]_1 ;\n wire \\rd_ptr_timing_reg[2]_10 ;\n wire \\rd_ptr_timing_reg[2]_2 ;\n wire \\rd_ptr_timing_reg[2]_3 ;\n wire \\rd_ptr_timing_reg[2]_4 ;\n wire \\rd_ptr_timing_reg[2]_5 ;\n wire \\rd_ptr_timing_reg[2]_6 ;\n wire \\rd_ptr_timing_reg[2]_7 ;\n wire \\rd_ptr_timing_reg[2]_8 ;\n wire \\rd_ptr_timing_reg[2]_9 ;\n wire [11:0]req_bank_r;\n wire \\req_bank_r_lcl_reg[0] ;\n wire \\req_bank_r_lcl_reg[0]_0 ;\n wire \\req_bank_r_lcl_reg[2] ;\n wire \\req_bank_r_lcl_reg[2]_0 ;\n wire [0:0]\\resume_wait_r_reg[5] ;\n wire \\row_cnt_victim_rotate.complex_row_cnt_reg[4] ;\n wire [0:0]\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ;\n wire rst_sync_r1;\n wire rst_sync_r1_reg;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__10;\n wire [0:0]rstdiv0_sync_r1_reg_rep__11;\n wire rstdiv0_sync_r1_reg_rep__12;\n wire rstdiv0_sync_r1_reg_rep__13;\n wire [1:0]rstdiv0_sync_r1_reg_rep__14;\n wire [0:0]rstdiv0_sync_r1_reg_rep__16;\n wire [0:0]rstdiv0_sync_r1_reg_rep__17;\n wire [0:0]rstdiv0_sync_r1_reg_rep__18;\n wire [0:0]rstdiv0_sync_r1_reg_rep__19;\n wire rstdiv0_sync_r1_reg_rep__2;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire rstdiv0_sync_r1_reg_rep__22;\n wire rstdiv0_sync_r1_reg_rep__23;\n wire rstdiv0_sync_r1_reg_rep__24;\n wire rstdiv0_sync_r1_reg_rep__24_0;\n wire rstdiv0_sync_r1_reg_rep__24_1;\n wire rstdiv0_sync_r1_reg_rep__25;\n wire rstdiv0_sync_r1_reg_rep__26;\n wire rstdiv0_sync_r1_reg_rep__26_0;\n wire rstdiv0_sync_r1_reg_rep__26_1;\n wire rstdiv0_sync_r1_reg_rep__26_2;\n wire rstdiv0_sync_r1_reg_rep__4;\n wire [0:0]rstdiv0_sync_r1_reg_rep__5;\n wire rstdiv0_sync_r1_reg_rep__6;\n wire rstdiv0_sync_r1_reg_rep__7;\n wire rstdiv0_sync_r1_reg_rep__8;\n wire rstdiv0_sync_r1_reg_rep__9;\n wire rtp_timer_ns1;\n wire rtp_timer_ns1_6;\n wire rtp_timer_ns1_7;\n wire samp_edge_cnt0_en_r;\n wire samp_edge_cnt0_en_r_reg;\n wire \\samps_r_reg[9] ;\n wire sent_col;\n wire \\sm_r_reg[0] ;\n wire [0:0]\\sm_r_reg[0]_0 ;\n wire \\stg2_tap_cnt_reg[0] ;\n wire stg3_dec2init_val_r_reg;\n wire stg3_inc2init_val_r_reg;\n wire \\stg3_r_reg[0] ;\n wire sync_pulse;\n wire sys_rst;\n wire [0:0]tail_r;\n wire tempmon_sample_en;\n wire [1:1]\\u_ddr_mc_phy_wrapper/u_ddr_mc_phy/of_ctl_full_v ;\n wire use_addr;\n wire wr_en;\n wire wr_en_5;\n wire wr_en_6;\n wire [3:0]\\wr_ptr_timing_reg[2] ;\n wire [3:0]\\wr_ptr_timing_reg[2]_0 ;\n wire [3:0]\\wr_ptr_timing_reg[2]_1 ;\n wire [3:0]\\write_buffer.wr_buf_out_data_reg[287] ;\n\n ddr3_if_mig_7series_v4_0_ddr_phy_top ddr_phy_top0\n (.CLK(CLK),\n .CLKB0(CLKB0),\n .CLKB0_7(CLKB0_7),\n .CLKB0_8(CLKB0_8),\n .CLKB0_9(CLKB0_9),\n .D(D),\n .DOA(DOA),\n .DOB(DOB),\n .DOC(DOC),\n .Q(Q),\n .RST0(RST0),\n .SR(SR),\n .SS(SS),\n .app_zq_r_reg(ddr_phy_top0_n_50),\n .\\calib_seq_reg[0] (\\calib_seq_reg[0] ),\n .\\cmd_pipe_plus.mc_address_reg[43] ({mux_address[43],mux_address[13]}),\n .\\cmd_pipe_plus.mc_address_reg[44] ({mc_address[44:30],mc_address[25:18],mc_address[14:0]}),\n .\\cmd_pipe_plus.mc_bank_reg[8] (mc_bank),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[0] (ddr_phy_top0_n_381),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 (mc0_n_126),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[1] (ddr_phy_top0_n_378),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[1]_0 (mc0_n_125),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[2] (ddr_phy_top0_n_377),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[2]_0 (mc0_n_128),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[3] (ddr_phy_top0_n_369),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[3]_0 (mc0_n_127),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[4] (ddr_phy_top0_n_376),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[4]_0 (mc0_n_124),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[5] ({ddr_phy_top0_n_370,ddr_phy_top0_n_371,ddr_phy_top0_n_372,ddr_phy_top0_n_373,ddr_phy_top0_n_374,ddr_phy_top0_n_375}),\n .\\cmd_pipe_plus.mc_data_offset_1_reg[5]_0 (mc0_n_123),\n .\\cmd_pipe_plus.mc_data_offset_reg[0] (ddr_phy_top0_n_380),\n .\\cmd_pipe_plus.mc_data_offset_reg[0]_0 (mc0_n_120),\n .\\cmd_pipe_plus.mc_data_offset_reg[1] (ddr_phy_top0_n_368),\n .\\cmd_pipe_plus.mc_data_offset_reg[1]_0 (mc0_n_119),\n .\\cmd_pipe_plus.mc_data_offset_reg[2] (ddr_phy_top0_n_367),\n .\\cmd_pipe_plus.mc_data_offset_reg[2]_0 (mc0_n_122),\n .\\cmd_pipe_plus.mc_data_offset_reg[3] (ddr_phy_top0_n_359),\n .\\cmd_pipe_plus.mc_data_offset_reg[3]_0 (mc0_n_121),\n .\\cmd_pipe_plus.mc_data_offset_reg[4] (ddr_phy_top0_n_366),\n .\\cmd_pipe_plus.mc_data_offset_reg[4]_0 (mc0_n_118),\n .\\cmd_pipe_plus.mc_data_offset_reg[5] ({ddr_phy_top0_n_360,ddr_phy_top0_n_361,ddr_phy_top0_n_362,ddr_phy_top0_n_363,ddr_phy_top0_n_364,ddr_phy_top0_n_365}),\n .\\cmd_pipe_plus.mc_data_offset_reg[5]_0 (mc0_n_117),\n .cnt_pwron_reset_done_r0(cnt_pwron_reset_done_r0),\n .\\complex_row_cnt_ocal_reg[0] (\\complex_row_cnt_ocal_reg[0] ),\n .ddr3_addr(ddr3_addr),\n .ddr3_ba(ddr3_ba),\n .ddr3_cas_n(ddr3_cas_n),\n .ddr3_cke(ddr3_cke),\n .ddr3_cs_n(ddr3_cs_n),\n .ddr3_dm(ddr3_dm),\n .ddr3_dq(ddr3_dq),\n .ddr3_dqs_n(ddr3_dqs_n),\n .ddr3_dqs_p(ddr3_dqs_p),\n .ddr3_odt(ddr3_odt),\n .ddr3_ras_n(ddr3_ras_n),\n .ddr3_reset_n(ddr3_reset_n),\n .ddr3_we_n(ddr3_we_n),\n .ddr_ck_out(ddr_ck_out),\n .\\device_temp_r_reg[11] (\\device_temp_r_reg[11] ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ),\n .dqs_po_en_stg2_f_reg(dqs_po_en_stg2_f_reg),\n .\\en_cnt_div4.enable_wrlvl_cnt_reg[3] (\\en_cnt_div4.enable_wrlvl_cnt_reg[3] ),\n .fine_adjust_reg(fine_adjust_reg),\n .freq_refclk(freq_refclk),\n .idle(idle),\n .in0(in0),\n .init_calib_complete_r_reg(init_calib_complete_r_reg),\n .maint_prescaler_r1(\\rank_mach0/rank_common0/maint_prescaler_r1 ),\n .mc_cas_n(mc_cas_n),\n .mc_cke(mc_cke),\n .mc_cmd(mc_cmd),\n .mc_cs_n(mc_cs_n),\n .mc_odt(mc_odt),\n .mc_ras_n(mc_ras_n),\n .mc_we_n(mc_we_n),\n .mc_wrdata_en(mc_wrdata_en),\n .mem_out(mem_out),\n .mem_refclk(mem_refclk),\n .\\mmcm_current_reg[0] (\\mmcm_current_reg[0] ),\n .\\mmcm_init_trail_reg[0] (\\mmcm_init_trail_reg[0] ),\n .mmcm_locked(mmcm_locked),\n .mmcm_ps_clk(mmcm_ps_clk),\n .\\my_empty_reg[7] (ddr_phy_top0_n_51),\n .\\not_strict_mode.app_rd_data_reg[0] (\\not_strict_mode.app_rd_data_reg[0] ),\n .\\not_strict_mode.app_rd_data_reg[100] (\\not_strict_mode.app_rd_data_reg[100] ),\n .\\not_strict_mode.app_rd_data_reg[101] (\\not_strict_mode.app_rd_data_reg[101] ),\n .\\not_strict_mode.app_rd_data_reg[102] (\\not_strict_mode.app_rd_data_reg[102] ),\n .\\not_strict_mode.app_rd_data_reg[103] (\\not_strict_mode.app_rd_data_reg[103] ),\n .\\not_strict_mode.app_rd_data_reg[104] (\\not_strict_mode.app_rd_data_reg[104] ),\n .\\not_strict_mode.app_rd_data_reg[105] (\\not_strict_mode.app_rd_data_reg[105] ),\n .\\not_strict_mode.app_rd_data_reg[106] (\\not_strict_mode.app_rd_data_reg[106] ),\n .\\not_strict_mode.app_rd_data_reg[107] (\\not_strict_mode.app_rd_data_reg[107] ),\n .\\not_strict_mode.app_rd_data_reg[108] (\\not_strict_mode.app_rd_data_reg[108] ),\n .\\not_strict_mode.app_rd_data_reg[109] (\\not_strict_mode.app_rd_data_reg[109] ),\n .\\not_strict_mode.app_rd_data_reg[10] (\\not_strict_mode.app_rd_data_reg[10] ),\n .\\not_strict_mode.app_rd_data_reg[110] (\\not_strict_mode.app_rd_data_reg[110] ),\n .\\not_strict_mode.app_rd_data_reg[111] (\\not_strict_mode.app_rd_data_reg[111] ),\n .\\not_strict_mode.app_rd_data_reg[112] (\\not_strict_mode.app_rd_data_reg[112] ),\n .\\not_strict_mode.app_rd_data_reg[113] (\\not_strict_mode.app_rd_data_reg[113] ),\n .\\not_strict_mode.app_rd_data_reg[114] (\\not_strict_mode.app_rd_data_reg[114] ),\n .\\not_strict_mode.app_rd_data_reg[115] (\\not_strict_mode.app_rd_data_reg[115] ),\n .\\not_strict_mode.app_rd_data_reg[116] (\\not_strict_mode.app_rd_data_reg[116] ),\n .\\not_strict_mode.app_rd_data_reg[117] (\\not_strict_mode.app_rd_data_reg[117] ),\n .\\not_strict_mode.app_rd_data_reg[118] (\\not_strict_mode.app_rd_data_reg[118] ),\n .\\not_strict_mode.app_rd_data_reg[119] (\\not_strict_mode.app_rd_data_reg[119] ),\n .\\not_strict_mode.app_rd_data_reg[11] (\\not_strict_mode.app_rd_data_reg[11] ),\n .\\not_strict_mode.app_rd_data_reg[120] (\\not_strict_mode.app_rd_data_reg[120] ),\n .\\not_strict_mode.app_rd_data_reg[121] (\\not_strict_mode.app_rd_data_reg[121] ),\n .\\not_strict_mode.app_rd_data_reg[122] (\\not_strict_mode.app_rd_data_reg[122] ),\n .\\not_strict_mode.app_rd_data_reg[123] (\\not_strict_mode.app_rd_data_reg[123] ),\n .\\not_strict_mode.app_rd_data_reg[124] (\\not_strict_mode.app_rd_data_reg[124] ),\n .\\not_strict_mode.app_rd_data_reg[125] (\\not_strict_mode.app_rd_data_reg[125] ),\n .\\not_strict_mode.app_rd_data_reg[126] (\\not_strict_mode.app_rd_data_reg[126] ),\n .\\not_strict_mode.app_rd_data_reg[127] (\\not_strict_mode.app_rd_data_reg[127] ),\n .\\not_strict_mode.app_rd_data_reg[128] (\\not_strict_mode.app_rd_data_reg[128] ),\n .\\not_strict_mode.app_rd_data_reg[129] (\\not_strict_mode.app_rd_data_reg[129] ),\n .\\not_strict_mode.app_rd_data_reg[12] (\\not_strict_mode.app_rd_data_reg[12] ),\n .\\not_strict_mode.app_rd_data_reg[130] (\\not_strict_mode.app_rd_data_reg[130] ),\n .\\not_strict_mode.app_rd_data_reg[131] (\\not_strict_mode.app_rd_data_reg[131] ),\n .\\not_strict_mode.app_rd_data_reg[132] (\\not_strict_mode.app_rd_data_reg[132] ),\n .\\not_strict_mode.app_rd_data_reg[133] (\\not_strict_mode.app_rd_data_reg[133] ),\n .\\not_strict_mode.app_rd_data_reg[134] (\\not_strict_mode.app_rd_data_reg[134] ),\n .\\not_strict_mode.app_rd_data_reg[135] (\\not_strict_mode.app_rd_data_reg[135] ),\n .\\not_strict_mode.app_rd_data_reg[136] (\\not_strict_mode.app_rd_data_reg[136] ),\n .\\not_strict_mode.app_rd_data_reg[137] (\\not_strict_mode.app_rd_data_reg[137] ),\n .\\not_strict_mode.app_rd_data_reg[138] (\\not_strict_mode.app_rd_data_reg[138] ),\n .\\not_strict_mode.app_rd_data_reg[139] (\\not_strict_mode.app_rd_data_reg[139] ),\n .\\not_strict_mode.app_rd_data_reg[13] (\\not_strict_mode.app_rd_data_reg[13] ),\n .\\not_strict_mode.app_rd_data_reg[140] (\\not_strict_mode.app_rd_data_reg[140] ),\n .\\not_strict_mode.app_rd_data_reg[141] (\\not_strict_mode.app_rd_data_reg[141] ),\n .\\not_strict_mode.app_rd_data_reg[142] (\\not_strict_mode.app_rd_data_reg[142] ),\n .\\not_strict_mode.app_rd_data_reg[143] (\\not_strict_mode.app_rd_data_reg[143] ),\n .\\not_strict_mode.app_rd_data_reg[144] (\\not_strict_mode.app_rd_data_reg[144] ),\n .\\not_strict_mode.app_rd_data_reg[145] (\\not_strict_mode.app_rd_data_reg[145] ),\n .\\not_strict_mode.app_rd_data_reg[146] (\\not_strict_mode.app_rd_data_reg[146] ),\n .\\not_strict_mode.app_rd_data_reg[147] (\\not_strict_mode.app_rd_data_reg[147] ),\n .\\not_strict_mode.app_rd_data_reg[148] (\\not_strict_mode.app_rd_data_reg[148] ),\n .\\not_strict_mode.app_rd_data_reg[149] (\\not_strict_mode.app_rd_data_reg[149] ),\n .\\not_strict_mode.app_rd_data_reg[14] (\\not_strict_mode.app_rd_data_reg[14] ),\n .\\not_strict_mode.app_rd_data_reg[150] (\\not_strict_mode.app_rd_data_reg[150] ),\n .\\not_strict_mode.app_rd_data_reg[151] (\\not_strict_mode.app_rd_data_reg[151] ),\n .\\not_strict_mode.app_rd_data_reg[152] (\\not_strict_mode.app_rd_data_reg[152] ),\n .\\not_strict_mode.app_rd_data_reg[153] (\\not_strict_mode.app_rd_data_reg[153] ),\n .\\not_strict_mode.app_rd_data_reg[154] (\\not_strict_mode.app_rd_data_reg[154] ),\n .\\not_strict_mode.app_rd_data_reg[155] (\\not_strict_mode.app_rd_data_reg[155] ),\n .\\not_strict_mode.app_rd_data_reg[156] (\\not_strict_mode.app_rd_data_reg[156] ),\n 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.\\not_strict_mode.app_rd_data_reg[83] (\\not_strict_mode.app_rd_data_reg[83] ),\n .\\not_strict_mode.app_rd_data_reg[84] (\\not_strict_mode.app_rd_data_reg[84] ),\n .\\not_strict_mode.app_rd_data_reg[85] (\\not_strict_mode.app_rd_data_reg[85] ),\n .\\not_strict_mode.app_rd_data_reg[86] (\\not_strict_mode.app_rd_data_reg[86] ),\n .\\not_strict_mode.app_rd_data_reg[87] (\\not_strict_mode.app_rd_data_reg[87] ),\n .\\not_strict_mode.app_rd_data_reg[88] (\\not_strict_mode.app_rd_data_reg[88] ),\n .\\not_strict_mode.app_rd_data_reg[89] (\\not_strict_mode.app_rd_data_reg[89] ),\n .\\not_strict_mode.app_rd_data_reg[8] (\\not_strict_mode.app_rd_data_reg[8] ),\n .\\not_strict_mode.app_rd_data_reg[90] (\\not_strict_mode.app_rd_data_reg[90] ),\n .\\not_strict_mode.app_rd_data_reg[91] (\\not_strict_mode.app_rd_data_reg[91] ),\n .\\not_strict_mode.app_rd_data_reg[92] (\\not_strict_mode.app_rd_data_reg[92] ),\n .\\not_strict_mode.app_rd_data_reg[93] (\\not_strict_mode.app_rd_data_reg[93] ),\n .\\not_strict_mode.app_rd_data_reg[94] (\\not_strict_mode.app_rd_data_reg[94] ),\n .\\not_strict_mode.app_rd_data_reg[95] (\\not_strict_mode.app_rd_data_reg[95] ),\n .\\not_strict_mode.app_rd_data_reg[96] (\\not_strict_mode.app_rd_data_reg[96] ),\n .\\not_strict_mode.app_rd_data_reg[97] (\\not_strict_mode.app_rd_data_reg[97] ),\n .\\not_strict_mode.app_rd_data_reg[98] (\\not_strict_mode.app_rd_data_reg[98] ),\n .\\not_strict_mode.app_rd_data_reg[99] (\\not_strict_mode.app_rd_data_reg[99] ),\n .\\not_strict_mode.app_rd_data_reg[9] (\\not_strict_mode.app_rd_data_reg[9] ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 (\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 ),\n .\\not_strict_mode.status_ram.rd_buf_we_r1_reg (ddr_phy_top0_n_97),\n .of_ctl_full_v(\\u_ddr_mc_phy_wrapper/u_ddr_mc_phy/of_ctl_full_v ),\n .ofs_rdy_r_reg(ddr_phy_top0_n_641),\n .ofs_rdy_r_reg_0(ddr_phy_top0_n_642),\n .p_81_in(p_81_in),\n .phy_dout({phy_dout[5:3],phy_dout[1]}),\n .phy_mc_ctl_full(phy_mc_ctl_full),\n .pi_cnt_dec_reg(pi_cnt_dec_reg),\n .pi_en_stg2_f_timing_reg(pi_en_stg2_f_timing_reg),\n .\\pi_rst_stg1_cal_r_reg[0] (\\pi_rst_stg1_cal_r_reg[0] ),\n .pll_locked(pll_locked),\n .po_cnt_dec_reg(po_cnt_dec_reg),\n .poc_sample_pd(poc_sample_pd),\n .psdone(psdone),\n .\\qcntr_r_reg[0] (\\qcntr_r_reg[0] ),\n .ram_init_done_r(ram_init_done_r),\n .rd_buf_we(rd_buf_we),\n .\\rd_ptr_reg[3] (\\rd_ptr_reg[3] ),\n .\\rd_ptr_reg[3]_0 (\\rd_ptr_reg[3]_0 ),\n .\\rd_ptr_timing_reg[0] ({\\rd_ptr_timing_reg[0] [37:6],\\rd_ptr_timing_reg[0] [4],\\rd_ptr_timing_reg[0] [1]}),\n .\\rd_ptr_timing_reg[0]_0 ({\\rd_ptr_timing_reg[0]_0 [3],\\rd_ptr_timing_reg[0]_0 [1]}),\n .\\rd_ptr_timing_reg[2] (\\rd_ptr_timing_reg[2] ),\n .\\rd_ptr_timing_reg[2]_0 (\\rd_ptr_timing_reg[2]_0 ),\n .\\rd_ptr_timing_reg[2]_1 (\\rd_ptr_timing_reg[2]_1 ),\n .\\rd_ptr_timing_reg[2]_10 (\\rd_ptr_timing_reg[2]_10 ),\n .\\rd_ptr_timing_reg[2]_2 (\\rd_ptr_timing_reg[2]_2 ),\n .\\rd_ptr_timing_reg[2]_3 (\\rd_ptr_timing_reg[2]_3 ),\n .\\rd_ptr_timing_reg[2]_4 (\\rd_ptr_timing_reg[2]_4 ),\n .\\rd_ptr_timing_reg[2]_5 (\\rd_ptr_timing_reg[2]_5 ),\n .\\rd_ptr_timing_reg[2]_6 (\\rd_ptr_timing_reg[2]_6 ),\n .\\rd_ptr_timing_reg[2]_7 (\\rd_ptr_timing_reg[2]_7 ),\n .\\rd_ptr_timing_reg[2]_8 (\\rd_ptr_timing_reg[2]_8 ),\n .\\rd_ptr_timing_reg[2]_9 (\\rd_ptr_timing_reg[2]_9 ),\n .\\read_fifo.fifo_out_data_r_reg[6] (\\col_mach0/p_0_in ),\n .\\read_fifo.fifo_out_data_r_reg[6]_0 (bypass__0),\n .\\read_fifo.tail_r_reg[0] (ddr_phy_top0_n_379),\n .\\resume_wait_r_reg[5] (\\resume_wait_r_reg[5] ),\n .\\row_cnt_victim_rotate.complex_row_cnt_reg[4] (\\row_cnt_victim_rotate.complex_row_cnt_reg[4] ),\n .\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] (\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .rst_sync_r1(rst_sync_r1),\n .rst_sync_r1_reg(rst_sync_r1_reg),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10),\n .rstdiv0_sync_r1_reg_rep__11(rstdiv0_sync_r1_reg_rep__11),\n .rstdiv0_sync_r1_reg_rep__12(rstdiv0_sync_r1_reg_rep__12),\n .rstdiv0_sync_r1_reg_rep__13(rstdiv0_sync_r1_reg_rep__13),\n .rstdiv0_sync_r1_reg_rep__14(rstdiv0_sync_r1_reg_rep__14),\n .rstdiv0_sync_r1_reg_rep__16(rstdiv0_sync_r1_reg_rep__16),\n .rstdiv0_sync_r1_reg_rep__17(rstdiv0_sync_r1_reg_rep__17),\n .rstdiv0_sync_r1_reg_rep__18(rstdiv0_sync_r1_reg_rep__18),\n .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),\n .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23),\n .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),\n .rstdiv0_sync_r1_reg_rep__24_0(rstdiv0_sync_r1_reg_rep__24_0),\n .rstdiv0_sync_r1_reg_rep__24_1(rstdiv0_sync_r1_reg_rep__24_1),\n .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25),\n .rstdiv0_sync_r1_reg_rep__26(rstdiv0_sync_r1_reg_rep__26),\n .rstdiv0_sync_r1_reg_rep__26_0(rstdiv0_sync_r1_reg_rep__26_0),\n .rstdiv0_sync_r1_reg_rep__26_1(rstdiv0_sync_r1_reg_rep__26_1),\n .rstdiv0_sync_r1_reg_rep__26_2(rstdiv0_sync_r1_reg_rep__26_2),\n .rstdiv0_sync_r1_reg_rep__4(rstdiv0_sync_r1_reg_rep__4),\n .rstdiv0_sync_r1_reg_rep__5(rstdiv0_sync_r1_reg_rep__5),\n .rstdiv0_sync_r1_reg_rep__6(rstdiv0_sync_r1_reg_rep__6),\n .rstdiv0_sync_r1_reg_rep__7(rstdiv0_sync_r1_reg_rep__7),\n .rstdiv0_sync_r1_reg_rep__8(rstdiv0_sync_r1_reg_rep__8),\n .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9),\n .samp_edge_cnt0_en_r(samp_edge_cnt0_en_r),\n .samp_edge_cnt0_en_r_reg(samp_edge_cnt0_en_r_reg),\n .\\samps_r_reg[9] (\\samps_r_reg[9] ),\n .sent_col(sent_col),\n .\\sm_r_reg[0] (\\sm_r_reg[0] ),\n .\\sm_r_reg[0]_0 (\\sm_r_reg[0]_0 ),\n .\\stg2_tap_cnt_reg[0] (\\stg2_tap_cnt_reg[0] ),\n .stg3_dec2init_val_r_reg(stg3_dec2init_val_r_reg),\n .stg3_inc2init_val_r_reg(stg3_inc2init_val_r_reg),\n .\\stg3_r_reg[0] (\\stg3_r_reg[0] ),\n .sync_pulse(sync_pulse),\n .sys_rst(sys_rst),\n .tail_r(tail_r),\n .tempmon_sample_en(tempmon_sample_en),\n .wr_en(wr_en),\n .wr_en_5(wr_en_5),\n .wr_en_6(wr_en_6),\n .\\wr_ptr_timing_reg[2] (\\wr_ptr_timing_reg[2] ),\n .\\wr_ptr_timing_reg[2]_0 (\\wr_ptr_timing_reg[2]_0 ),\n .\\wr_ptr_timing_reg[2]_1 (\\wr_ptr_timing_reg[2]_1 ));\n ddr3_if_mig_7series_v4_0_mc mc0\n (.CLK(CLK),\n .E(E),\n .Q(req_bank_r[2:0]),\n .SR(SR),\n .accept_ns(accept_ns),\n .act_wait_r_lcl_reg(act_wait_r_lcl_reg),\n .act_wait_r_lcl_reg_0(act_wait_r_lcl_reg_0),\n .act_wait_r_lcl_reg_1(act_wait_r_lcl_reg_1),\n .act_wait_r_lcl_reg_2(act_wait_r_lcl_reg_2),\n .\\app_addr_r1_reg[12] (\\app_addr_r1_reg[12] ),\n .\\app_addr_r1_reg[27] (\\app_addr_r1_reg[27] ),\n .\\app_addr_r1_reg[9] (\\app_addr_r1_reg[9] ),\n .\\app_cmd_r1_reg[0] (\\app_cmd_r1_reg[0] ),\n .\\app_cmd_r2_reg[1] (\\app_cmd_r2_reg[1] ),\n .app_hi_pri_r2(app_hi_pri_r2),\n .app_rd_data_end_ns(app_rd_data_end_ns),\n .app_ref_ack(app_ref_ack),\n .app_ref_req(app_ref_req),\n .app_sr_active(app_sr_active),\n .app_sr_req(app_sr_req),\n .app_zq_ack(app_zq_ack),\n .app_zq_req(app_zq_req),\n .bm_end_r1(bm_end_r1),\n .bm_end_r1_0(bm_end_r1_0),\n .bm_end_r1_4(bm_end_r1_4),\n .bm_end_r1_reg(bm_end_r1_reg),\n .bm_end_r1_reg_0(bm_end_r1_reg_0),\n .bm_end_r1_reg_1(bm_end_r1_reg_1),\n .bm_end_r1_reg_2(bm_end_r1_reg_2),\n .bypass__0(bypass__0),\n .\\cmd_pipe_plus.mc_bank_reg[2]_0 (req_bank_r[5:3]),\n .\\cmd_pipe_plus.mc_bank_reg[8]_0 (req_bank_r[8:6]),\n .\\cmd_pipe_plus.mc_bank_reg[8]_1 (req_bank_r[11:9]),\n .\\data_offset_1_i1_reg[0] (mc0_n_126),\n .\\data_offset_1_i1_reg[1] (mc0_n_125),\n .\\data_offset_1_i1_reg[2] (mc0_n_128),\n .\\data_offset_1_i1_reg[3] (mc0_n_127),\n .\\data_offset_1_i1_reg[4] (mc0_n_124),\n .\\data_offset_1_i1_reg[5] (mc0_n_123),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (ddr_phy_top0_n_97),\n .\\entry_cnt_reg[2] (ddr_phy_top0_n_642),\n .\\entry_cnt_reg[2]_0 (ddr_phy_top0_n_641),\n .granted_col_r_reg(ddr_phy_top0_n_359),\n .granted_col_r_reg_0(ddr_phy_top0_n_367),\n .granted_col_r_reg_1(ddr_phy_top0_n_369),\n .granted_col_r_reg_2(ddr_phy_top0_n_377),\n .hi_priority(hi_priority),\n .idle(idle),\n .in0(in0),\n .init_calib_complete_reg_rep__6(ddr_phy_top0_n_50),\n .init_calib_complete_reg_rep__7(ddr_phy_top0_n_51),\n .maint_prescaler_r1(\\rank_mach0/rank_common0/maint_prescaler_r1 ),\n .mc_cas_n(mc_cas_n),\n .mc_cke(mc_cke),\n .mc_cmd(mc_cmd),\n .mc_cs_n(mc_cs_n),\n .mc_odt(mc_odt),\n .mc_ras_n(mc_ras_n),\n .mc_we_n(mc_we_n),\n .mc_wrdata_en(mc_wrdata_en),\n .\\my_empty_reg[7] ({mux_address[43],mux_address[13]}),\n .\\my_full_reg[3] ({mc_address[44:30],mc_address[25:18],mc_address[14:0]}),\n .\\not_strict_mode.app_rd_data_end_reg ({\\not_strict_mode.app_rd_data_end_reg [6],\\col_mach0/p_0_in ,\\not_strict_mode.app_rd_data_end_reg [5:0]}),\n .\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),\n .\\not_strict_mode.status_ram.rd_buf_we_r1_reg (\\not_strict_mode.status_ram.rd_buf_we_r1_reg ),\n .of_ctl_full_v(\\u_ddr_mc_phy_wrapper/u_ddr_mc_phy/of_ctl_full_v ),\n .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg),\n .\\phy_ctl_wd_i1_reg[17] (mc0_n_120),\n .\\phy_ctl_wd_i1_reg[18] (mc0_n_119),\n .\\phy_ctl_wd_i1_reg[19] (mc0_n_122),\n .\\phy_ctl_wd_i1_reg[20] (mc0_n_121),\n .\\phy_ctl_wd_i1_reg[21] (mc0_n_118),\n .\\phy_ctl_wd_i1_reg[22] (mc0_n_117),\n .phy_dout({phy_dout[2],phy_dout[0]}),\n .phy_mc_ctl_full(phy_mc_ctl_full),\n .pointer_we(pointer_we),\n .ram_init_done_r(ram_init_done_r),\n .\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] (ddr_phy_top0_n_368),\n .\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 (ddr_phy_top0_n_380),\n .\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4] (ddr_phy_top0_n_366),\n .\\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ({ddr_phy_top0_n_360,ddr_phy_top0_n_361,ddr_phy_top0_n_362,ddr_phy_top0_n_363,ddr_phy_top0_n_364,ddr_phy_top0_n_365}),\n .\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10] (ddr_phy_top0_n_376),\n .\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ({ddr_phy_top0_n_370,ddr_phy_top0_n_371,ddr_phy_top0_n_372,ddr_phy_top0_n_373,ddr_phy_top0_n_374,ddr_phy_top0_n_375}),\n .\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] (ddr_phy_top0_n_378),\n .\\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0 (ddr_phy_top0_n_381),\n .\\ras_timer_r_reg[2] (\\ras_timer_r_reg[2] ),\n .\\rd_buf_indx.rd_buf_indx_r_reg[4] (\\rd_buf_indx.rd_buf_indx_r_reg[4] ),\n .\\rd_ptr_timing_reg[0] ({\\rd_ptr_timing_reg[0]_0 [4],\\rd_ptr_timing_reg[0]_0 [2],\\rd_ptr_timing_reg[0]_0 [0]}),\n .\\rd_ptr_timing_reg[0]_0 ({\\rd_ptr_timing_reg[0] [5],\\rd_ptr_timing_reg[0] [3:2],\\rd_ptr_timing_reg[0] [0]}),\n .\\rd_ptr_timing_reg[0]_1 (mc_bank),\n .\\read_fifo.tail_r_reg[0] (ddr_phy_top0_n_379),\n .\\read_fifo.tail_r_reg[1] (tail_r),\n .\\req_bank_r_lcl_reg[0] (\\req_bank_r_lcl_reg[0] ),\n .\\req_bank_r_lcl_reg[0]_0 (\\req_bank_r_lcl_reg[0]_0 ),\n .\\req_bank_r_lcl_reg[2] (\\req_bank_r_lcl_reg[2] ),\n .\\req_bank_r_lcl_reg[2]_0 (\\req_bank_r_lcl_reg[2]_0 ),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22),\n .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23),\n .rtp_timer_ns1(rtp_timer_ns1),\n .rtp_timer_ns1_6(rtp_timer_ns1_6),\n .rtp_timer_ns1_7(rtp_timer_ns1_7),\n .sent_col(sent_col),\n .tempmon_sample_en(tempmon_sample_en),\n .use_addr(use_addr),\n .\\write_buffer.wr_buf_out_data_reg[287] (\\write_buffer.wr_buf_out_data_reg[287] ));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_memc_ui_top_axi\n (bm_end_r1,\n pass_open_bank_r,\n bm_end_r1_0,\n pass_open_bank_r_1,\n bm_end_r1_2,\n pass_open_bank_r_3,\n bm_end_r1_4,\n pass_open_bank_r_5,\n app_ref_ack,\n app_zq_ack,\n app_sr_active,\n ddr3_reset_n,\n ddr3_cas_n,\n ddr3_ras_n,\n ddr3_we_n,\n ddr3_addr,\n ddr3_ba,\n ddr3_cs_n,\n ddr3_odt,\n ddr3_cke,\n ddr3_dm,\n \\rd_ptr_timing_reg[2] ,\n \\rd_ptr_timing_reg[2]_0 ,\n \\rd_ptr_timing_reg[2]_1 ,\n \\rd_ptr_timing_reg[2]_2 ,\n \\rd_ptr_timing_reg[2]_3 ,\n \\rd_ptr_timing_reg[2]_4 ,\n \\rd_ptr_timing_reg[2]_5 ,\n \\rd_ptr_timing_reg[2]_6 ,\n \\rd_ptr_timing_reg[2]_7 ,\n \\rd_ptr_timing_reg[2]_8 ,\n \\rd_ptr_timing_reg[2]_9 ,\n \\rd_ptr_timing_reg[2]_10 ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,\n \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,\n phy_dout,\n sm_r,\n phy_mc_go,\n \\pi_rst_stg1_cal_r_reg[0] ,\n samp_edge_cnt0_en_r,\n pi_cnt_dec,\n po_cnt_dec,\n \\rd_ptr_timing_reg[0] ,\n \\rd_ptr_timing_reg[0]_0 ,\n \\resume_wait_r_reg[5] ,\n stg3_dec2init_val_r_reg,\n stg3_inc2init_val_r_reg,\n rst_sync_r1_reg,\n s_axi_arready,\n \\stg2_tap_cnt_reg[0] ,\n \\sm_r_reg[0] ,\n D,\n \\en_cnt_div4.enable_wrlvl_cnt_reg[3] ,\n \\complex_row_cnt_ocal_reg[0] ,\n \\row_cnt_victim_rotate.complex_row_cnt_reg[4] ,\n Q,\n \\wr_ptr_timing_reg[2] ,\n \\wr_ptr_timing_reg[2]_0 ,\n wr_en,\n wr_en_5,\n wr_en_6,\n ddr_ck_out,\n E,\n s_axi_awready,\n s_axi_wready,\n out,\n s_axi_rid,\n s_axi_bid,\n s_axi_bvalid,\n s_axi_rvalid,\n s_axi_rlast,\n ddr3_dq,\n ddr3_dqs_p,\n ddr3_dqs_n,\n CLK,\n rstdiv0_sync_r1_reg_rep__0,\n SR,\n rstdiv0_sync_r1_reg_rep__20,\n rstdiv0_sync_r1_reg_rep__21,\n app_ref_req,\n app_zq_req,\n app_sr_req,\n rstdiv0_sync_r1_reg_rep__22,\n rstdiv0_sync_r1_reg_rep__23,\n mmcm_ps_clk,\n rst_sync_r1,\n poc_sample_pd,\n freq_refclk,\n mem_refclk,\n sync_pulse,\n pll_locked,\n in0,\n CLKB0,\n CLKB0_7,\n CLKB0_8,\n CLKB0_9,\n RST0,\n rstdiv0_sync_r1_reg_rep__9,\n rstdiv0_sync_r1_reg_rep__10,\n rstdiv0_sync_r1_reg_rep__26,\n rstdiv0_sync_r1_reg_rep__12,\n rstdiv0_sync_r1_reg_rep__2,\n rstdiv0_sync_r1_reg_rep__24,\n rstdiv0_sync_r1_reg_rep__13,\n rstdiv0_sync_r1_reg_rep__14,\n rstdiv0_sync_r1_reg_rep__11,\n cnt_pwron_reset_done_r0,\n rstdiv0_sync_r1_reg_rep__18,\n rstdiv0_sync_r1_reg_rep__16,\n SS,\n rstdiv0_sync_r1_reg_rep__7,\n mem_out,\n \\rd_ptr_reg[3] ,\n rstdiv0_sync_r1_reg_rep__26_0,\n rstdiv0_sync_r1_reg_rep__25,\n \\sm_r_reg[0]_0 ,\n \\rd_ptr_reg[3]_0 ,\n sys_rst,\n \\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ,\n mmcm_locked,\n s_axi_arvalid,\n rstdiv0_sync_r1_reg_rep__26_1,\n rstdiv0_sync_r1_reg_rep__26_2,\n \\mmcm_init_trail_reg[0] ,\n \\mmcm_current_reg[0] ,\n bm_end_r1_reg,\n bm_end_r1_reg_0,\n bm_end_r1_reg_1,\n pass_open_bank_r_lcl_reg,\n bm_end_r1_reg_2,\n rtp_timer_ns1,\n rtp_timer_ns1_6,\n rtp_timer_ns1_7,\n psdone,\n rstdiv0_sync_r1_reg_rep__19,\n fine_adjust_reg,\n samp_edge_cnt0_en_r_reg,\n pi_cnt_dec_reg,\n rstdiv0_sync_r1_reg_rep__24_0,\n p_81_in,\n rstdiv0_sync_r1_reg_rep__24_1,\n rstdiv0_sync_r1_reg_rep__17,\n po_cnt_dec_reg,\n rstdiv0_sync_r1_reg_rep__5,\n \\device_temp_r_reg[11] ,\n rstdiv0_sync_r1_reg_rep__4,\n rstdiv0_sync_r1_reg_rep__6,\n \\stg3_r_reg[0] ,\n rstdiv0_sync_r1_reg_rep__8,\n s_axi_awlen,\n s_axi_bready,\n s_axi_awvalid,\n s_axi_awaddr,\n s_axi_awburst,\n s_axi_wvalid,\n s_axi_awid,\n s_axi_arlen,\n s_axi_araddr,\n s_axi_arburst,\n s_axi_rready,\n s_axi_wstrb,\n s_axi_wdata,\n aresetn,\n s_axi_arid);\n output bm_end_r1;\n output pass_open_bank_r;\n output bm_end_r1_0;\n output pass_open_bank_r_1;\n output bm_end_r1_2;\n output pass_open_bank_r_3;\n output bm_end_r1_4;\n output pass_open_bank_r_5;\n output app_ref_ack;\n output app_zq_ack;\n output app_sr_active;\n output ddr3_reset_n;\n output ddr3_cas_n;\n output ddr3_ras_n;\n output ddr3_we_n;\n output [14:0]ddr3_addr;\n output [2:0]ddr3_ba;\n output [0:0]ddr3_cs_n;\n output [0:0]ddr3_odt;\n output [0:0]ddr3_cke;\n output [3:0]ddr3_dm;\n output \\rd_ptr_timing_reg[2] ;\n output \\rd_ptr_timing_reg[2]_0 ;\n output \\rd_ptr_timing_reg[2]_1 ;\n output \\rd_ptr_timing_reg[2]_2 ;\n output \\rd_ptr_timing_reg[2]_3 ;\n output \\rd_ptr_timing_reg[2]_4 ;\n output \\rd_ptr_timing_reg[2]_5 ;\n output \\rd_ptr_timing_reg[2]_6 ;\n output \\rd_ptr_timing_reg[2]_7 ;\n output \\rd_ptr_timing_reg[2]_8 ;\n output \\rd_ptr_timing_reg[2]_9 ;\n output \\rd_ptr_timing_reg[2]_10 ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;\n output \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;\n output [5:0]phy_dout;\n output sm_r;\n output phy_mc_go;\n output \\pi_rst_stg1_cal_r_reg[0] ;\n output samp_edge_cnt0_en_r;\n output pi_cnt_dec;\n output po_cnt_dec;\n output [37:0]\\rd_ptr_timing_reg[0] ;\n output [4:0]\\rd_ptr_timing_reg[0]_0 ;\n output \\resume_wait_r_reg[5] ;\n output stg3_dec2init_val_r_reg;\n output stg3_inc2init_val_r_reg;\n output rst_sync_r1_reg;\n output s_axi_arready;\n output \\stg2_tap_cnt_reg[0] ;\n output \\sm_r_reg[0] ;\n output [0:0]D;\n output \\en_cnt_div4.enable_wrlvl_cnt_reg[3] ;\n output \\complex_row_cnt_ocal_reg[0] ;\n output \\row_cnt_victim_rotate.complex_row_cnt_reg[4] ;\n output [3:0]Q;\n output [3:0]\\wr_ptr_timing_reg[2] ;\n output [3:0]\\wr_ptr_timing_reg[2]_0 ;\n output wr_en;\n output wr_en_5;\n output wr_en_6;\n output [1:0]ddr_ck_out;\n output [0:0]E;\n output s_axi_awready;\n output s_axi_wready;\n output [256:0]out;\n output [0:0]s_axi_rid;\n output [0:0]s_axi_bid;\n output s_axi_bvalid;\n output s_axi_rvalid;\n output s_axi_rlast;\n inout [31:0]ddr3_dq;\n inout [3:0]ddr3_dqs_p;\n inout [3:0]ddr3_dqs_n;\n input CLK;\n input rstdiv0_sync_r1_reg_rep__0;\n input [0:0]SR;\n input rstdiv0_sync_r1_reg_rep__20;\n input rstdiv0_sync_r1_reg_rep__21;\n input app_ref_req;\n input app_zq_req;\n input app_sr_req;\n input rstdiv0_sync_r1_reg_rep__22;\n input rstdiv0_sync_r1_reg_rep__23;\n input mmcm_ps_clk;\n input rst_sync_r1;\n input poc_sample_pd;\n input freq_refclk;\n input mem_refclk;\n input sync_pulse;\n input pll_locked;\n input in0;\n input CLKB0;\n input CLKB0_7;\n input CLKB0_8;\n input CLKB0_9;\n input RST0;\n input rstdiv0_sync_r1_reg_rep__9;\n input rstdiv0_sync_r1_reg_rep__10;\n input rstdiv0_sync_r1_reg_rep__26;\n input rstdiv0_sync_r1_reg_rep__12;\n input rstdiv0_sync_r1_reg_rep__2;\n input rstdiv0_sync_r1_reg_rep__24;\n input rstdiv0_sync_r1_reg_rep__13;\n input [1:0]rstdiv0_sync_r1_reg_rep__14;\n input [0:0]rstdiv0_sync_r1_reg_rep__11;\n input cnt_pwron_reset_done_r0;\n input [0:0]rstdiv0_sync_r1_reg_rep__18;\n input [0:0]rstdiv0_sync_r1_reg_rep__16;\n input [0:0]SS;\n input rstdiv0_sync_r1_reg_rep__7;\n input [17:0]mem_out;\n input [71:0]\\rd_ptr_reg[3] ;\n input rstdiv0_sync_r1_reg_rep__26_0;\n input rstdiv0_sync_r1_reg_rep__25;\n input [0:0]\\sm_r_reg[0]_0 ;\n input [29:0]\\rd_ptr_reg[3]_0 ;\n input sys_rst;\n input [0:0]\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ;\n input mmcm_locked;\n input s_axi_arvalid;\n input rstdiv0_sync_r1_reg_rep__26_1;\n input rstdiv0_sync_r1_reg_rep__26_2;\n input \\mmcm_init_trail_reg[0] ;\n input \\mmcm_current_reg[0] ;\n input bm_end_r1_reg;\n input bm_end_r1_reg_0;\n input bm_end_r1_reg_1;\n input pass_open_bank_r_lcl_reg;\n input bm_end_r1_reg_2;\n input rtp_timer_ns1;\n input rtp_timer_ns1_6;\n input rtp_timer_ns1_7;\n input psdone;\n input [0:0]rstdiv0_sync_r1_reg_rep__19;\n input fine_adjust_reg;\n input samp_edge_cnt0_en_r_reg;\n input [0:0]pi_cnt_dec_reg;\n input rstdiv0_sync_r1_reg_rep__24_0;\n input p_81_in;\n input rstdiv0_sync_r1_reg_rep__24_1;\n input [0:0]rstdiv0_sync_r1_reg_rep__17;\n input [0:0]po_cnt_dec_reg;\n input [0:0]rstdiv0_sync_r1_reg_rep__5;\n input [11:0]\\device_temp_r_reg[11] ;\n input rstdiv0_sync_r1_reg_rep__4;\n input rstdiv0_sync_r1_reg_rep__6;\n input \\stg3_r_reg[0] ;\n input rstdiv0_sync_r1_reg_rep__8;\n input [7:0]s_axi_awlen;\n input s_axi_bready;\n input s_axi_awvalid;\n input [29:0]s_axi_awaddr;\n input [0:0]s_axi_awburst;\n input s_axi_wvalid;\n input [0:0]s_axi_awid;\n input [7:0]s_axi_arlen;\n input [29:0]s_axi_araddr;\n input [0:0]s_axi_arburst;\n input s_axi_rready;\n input [31:0]s_axi_wstrb;\n input [255:0]s_axi_wdata;\n input aresetn;\n input [0:0]s_axi_arid;\n\n wire CLK;\n wire CLKB0;\n wire CLKB0_7;\n wire CLKB0_8;\n wire CLKB0_9;\n wire [0:0]D;\n wire [0:0]E;\n wire [3:0]Q;\n wire RST0;\n wire [0:0]SR;\n wire [0:0]SS;\n wire accept_ns;\n wire [27:3]app_addr;\n wire [0:0]app_cmd;\n wire [255:0]app_rd_data;\n wire [255:0]app_rd_data_ns;\n wire app_rd_data_valid;\n wire app_rdy;\n wire app_ref_ack;\n wire app_ref_req;\n wire app_sr_active;\n wire app_sr_req;\n wire [255:0]app_wdf_data;\n wire [31:0]app_wdf_mask;\n wire app_wdf_rdy;\n wire app_zq_ack;\n wire app_zq_req;\n wire aresetn;\n wire [255:0]\\axi_mc_w_channel_0/mc_app_wdf_data_reg ;\n wire [31:0]\\axi_mc_w_channel_0/mc_app_wdf_mask_reg ;\n wire \\axi_mc_w_channel_0/mc_app_wdf_wren_reg ;\n wire [255:0]\\axi_mc_w_channel_0/next_wdf_data ;\n wire [31:0]\\axi_mc_w_channel_0/next_wdf_mask ;\n wire [2:0]bank;\n wire bm_end_r1;\n wire bm_end_r1_0;\n wire bm_end_r1_2;\n wire bm_end_r1_4;\n wire bm_end_r1_reg;\n wire bm_end_r1_reg_0;\n wire bm_end_r1_reg_1;\n wire bm_end_r1_reg_2;\n wire [1:1]cmd;\n wire cnt_pwron_reset_done_r0;\n wire [9:3]col;\n wire \\complex_row_cnt_ocal_reg[0] ;\n wire [4:0]data_buf_addr;\n wire [14:0]ddr3_addr;\n wire [2:0]ddr3_ba;\n wire ddr3_cas_n;\n wire [0:0]ddr3_cke;\n wire [0:0]ddr3_cs_n;\n wire [3:0]ddr3_dm;\n wire [31:0]ddr3_dq;\n wire [3:0]ddr3_dqs_n;\n wire [3:0]ddr3_dqs_p;\n wire [0:0]ddr3_odt;\n wire ddr3_ras_n;\n wire ddr3_reset_n;\n wire ddr3_we_n;\n wire [1:0]ddr_ck_out;\n wire [11:0]\\device_temp_r_reg[11] ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;\n wire \\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;\n wire \\en_cnt_div4.enable_wrlvl_cnt_reg[3] ;\n wire fine_adjust_reg;\n wire freq_refclk;\n wire hi_priority;\n wire in0;\n wire init_calib_complete_r;\n wire [11:0]\\mc0/bank_mach0/req_bank_r ;\n wire mem_intfc0_n_142;\n wire mem_intfc0_n_143;\n wire mem_intfc0_n_144;\n wire mem_intfc0_n_145;\n wire mem_intfc0_n_146;\n wire mem_intfc0_n_147;\n wire mem_intfc0_n_148;\n wire mem_intfc0_n_149;\n wire mem_intfc0_n_150;\n wire mem_intfc0_n_151;\n wire mem_intfc0_n_152;\n wire mem_intfc0_n_153;\n wire mem_intfc0_n_154;\n wire mem_intfc0_n_155;\n wire mem_intfc0_n_156;\n wire mem_intfc0_n_157;\n wire mem_intfc0_n_158;\n wire mem_intfc0_n_159;\n wire mem_intfc0_n_160;\n wire mem_intfc0_n_161;\n wire mem_intfc0_n_162;\n wire mem_intfc0_n_163;\n wire mem_intfc0_n_164;\n wire mem_intfc0_n_165;\n wire mem_intfc0_n_166;\n wire mem_intfc0_n_167;\n wire mem_intfc0_n_168;\n wire mem_intfc0_n_169;\n wire mem_intfc0_n_170;\n wire mem_intfc0_n_171;\n wire mem_intfc0_n_172;\n wire mem_intfc0_n_173;\n wire mem_intfc0_n_174;\n wire mem_intfc0_n_175;\n wire mem_intfc0_n_176;\n wire mem_intfc0_n_177;\n wire mem_intfc0_n_178;\n wire mem_intfc0_n_179;\n wire mem_intfc0_n_180;\n wire mem_intfc0_n_181;\n wire mem_intfc0_n_182;\n wire mem_intfc0_n_183;\n wire mem_intfc0_n_184;\n wire mem_intfc0_n_185;\n wire mem_intfc0_n_186;\n wire mem_intfc0_n_187;\n wire mem_intfc0_n_188;\n wire mem_intfc0_n_189;\n wire mem_intfc0_n_190;\n wire mem_intfc0_n_191;\n wire mem_intfc0_n_192;\n wire mem_intfc0_n_193;\n wire mem_intfc0_n_194;\n wire mem_intfc0_n_195;\n wire mem_intfc0_n_196;\n wire mem_intfc0_n_197;\n wire mem_intfc0_n_198;\n wire mem_intfc0_n_199;\n wire mem_intfc0_n_200;\n wire mem_intfc0_n_201;\n wire mem_intfc0_n_202;\n wire mem_intfc0_n_203;\n wire mem_intfc0_n_204;\n wire mem_intfc0_n_205;\n wire mem_intfc0_n_206;\n wire mem_intfc0_n_207;\n wire mem_intfc0_n_208;\n wire mem_intfc0_n_209;\n wire mem_intfc0_n_210;\n wire mem_intfc0_n_211;\n wire mem_intfc0_n_212;\n wire mem_intfc0_n_213;\n wire mem_intfc0_n_214;\n wire mem_intfc0_n_215;\n wire mem_intfc0_n_216;\n wire mem_intfc0_n_217;\n wire mem_intfc0_n_218;\n wire mem_intfc0_n_219;\n wire mem_intfc0_n_220;\n wire mem_intfc0_n_221;\n wire mem_intfc0_n_222;\n wire mem_intfc0_n_223;\n wire mem_intfc0_n_224;\n wire mem_intfc0_n_225;\n wire mem_intfc0_n_226;\n wire mem_intfc0_n_227;\n wire mem_intfc0_n_228;\n wire mem_intfc0_n_229;\n wire mem_intfc0_n_230;\n wire mem_intfc0_n_231;\n wire mem_intfc0_n_232;\n wire mem_intfc0_n_233;\n wire mem_intfc0_n_234;\n wire mem_intfc0_n_235;\n wire mem_intfc0_n_236;\n wire mem_intfc0_n_237;\n wire mem_intfc0_n_238;\n wire mem_intfc0_n_239;\n wire mem_intfc0_n_240;\n wire mem_intfc0_n_241;\n wire mem_intfc0_n_242;\n wire mem_intfc0_n_243;\n wire mem_intfc0_n_244;\n wire mem_intfc0_n_245;\n wire mem_intfc0_n_246;\n wire mem_intfc0_n_247;\n wire mem_intfc0_n_248;\n wire mem_intfc0_n_249;\n wire mem_intfc0_n_250;\n wire mem_intfc0_n_251;\n wire mem_intfc0_n_252;\n wire mem_intfc0_n_253;\n wire mem_intfc0_n_254;\n wire mem_intfc0_n_255;\n wire mem_intfc0_n_256;\n wire mem_intfc0_n_257;\n wire mem_intfc0_n_258;\n wire mem_intfc0_n_259;\n wire mem_intfc0_n_260;\n wire mem_intfc0_n_261;\n wire mem_intfc0_n_262;\n wire mem_intfc0_n_263;\n wire mem_intfc0_n_264;\n wire mem_intfc0_n_265;\n wire mem_intfc0_n_266;\n wire mem_intfc0_n_267;\n wire mem_intfc0_n_268;\n wire mem_intfc0_n_269;\n wire mem_intfc0_n_270;\n wire mem_intfc0_n_271;\n wire mem_intfc0_n_272;\n wire mem_intfc0_n_273;\n wire mem_intfc0_n_274;\n wire mem_intfc0_n_275;\n wire mem_intfc0_n_276;\n wire mem_intfc0_n_277;\n wire mem_intfc0_n_278;\n wire mem_intfc0_n_279;\n wire mem_intfc0_n_280;\n wire mem_intfc0_n_281;\n wire mem_intfc0_n_282;\n wire mem_intfc0_n_283;\n wire mem_intfc0_n_284;\n wire mem_intfc0_n_285;\n wire mem_intfc0_n_286;\n wire mem_intfc0_n_287;\n wire mem_intfc0_n_288;\n wire mem_intfc0_n_289;\n wire mem_intfc0_n_290;\n wire mem_intfc0_n_291;\n wire mem_intfc0_n_292;\n wire mem_intfc0_n_293;\n wire mem_intfc0_n_294;\n wire mem_intfc0_n_295;\n wire mem_intfc0_n_296;\n wire mem_intfc0_n_297;\n wire mem_intfc0_n_298;\n wire mem_intfc0_n_299;\n wire mem_intfc0_n_300;\n wire mem_intfc0_n_301;\n wire mem_intfc0_n_302;\n wire mem_intfc0_n_303;\n wire mem_intfc0_n_304;\n wire mem_intfc0_n_305;\n wire mem_intfc0_n_306;\n wire mem_intfc0_n_307;\n wire mem_intfc0_n_308;\n wire mem_intfc0_n_309;\n wire mem_intfc0_n_310;\n wire mem_intfc0_n_311;\n wire mem_intfc0_n_312;\n wire mem_intfc0_n_313;\n wire mem_intfc0_n_314;\n wire mem_intfc0_n_315;\n wire mem_intfc0_n_316;\n wire mem_intfc0_n_317;\n wire mem_intfc0_n_318;\n wire mem_intfc0_n_319;\n wire mem_intfc0_n_320;\n wire mem_intfc0_n_321;\n wire mem_intfc0_n_322;\n wire mem_intfc0_n_323;\n wire mem_intfc0_n_324;\n wire mem_intfc0_n_325;\n wire mem_intfc0_n_326;\n wire mem_intfc0_n_327;\n wire mem_intfc0_n_328;\n wire mem_intfc0_n_329;\n wire mem_intfc0_n_330;\n wire mem_intfc0_n_331;\n wire mem_intfc0_n_332;\n wire mem_intfc0_n_333;\n wire mem_intfc0_n_334;\n wire mem_intfc0_n_335;\n wire mem_intfc0_n_336;\n wire mem_intfc0_n_337;\n wire mem_intfc0_n_338;\n wire mem_intfc0_n_339;\n wire mem_intfc0_n_340;\n wire mem_intfc0_n_341;\n wire mem_intfc0_n_342;\n wire mem_intfc0_n_343;\n wire mem_intfc0_n_344;\n wire mem_intfc0_n_345;\n wire mem_intfc0_n_346;\n wire mem_intfc0_n_347;\n wire mem_intfc0_n_348;\n wire mem_intfc0_n_349;\n wire mem_intfc0_n_350;\n wire mem_intfc0_n_351;\n wire mem_intfc0_n_352;\n wire mem_intfc0_n_353;\n wire mem_intfc0_n_354;\n wire mem_intfc0_n_355;\n wire mem_intfc0_n_356;\n wire mem_intfc0_n_357;\n wire mem_intfc0_n_358;\n wire mem_intfc0_n_359;\n wire mem_intfc0_n_360;\n wire mem_intfc0_n_361;\n wire mem_intfc0_n_362;\n wire mem_intfc0_n_363;\n wire mem_intfc0_n_364;\n wire mem_intfc0_n_365;\n wire mem_intfc0_n_366;\n wire mem_intfc0_n_367;\n wire mem_intfc0_n_368;\n wire mem_intfc0_n_369;\n wire mem_intfc0_n_370;\n wire mem_intfc0_n_371;\n wire mem_intfc0_n_372;\n wire mem_intfc0_n_373;\n wire mem_intfc0_n_374;\n wire mem_intfc0_n_375;\n wire mem_intfc0_n_376;\n wire mem_intfc0_n_377;\n wire mem_intfc0_n_378;\n wire mem_intfc0_n_379;\n wire mem_intfc0_n_380;\n wire mem_intfc0_n_381;\n wire mem_intfc0_n_382;\n wire mem_intfc0_n_383;\n wire mem_intfc0_n_384;\n wire mem_intfc0_n_385;\n wire mem_intfc0_n_386;\n wire mem_intfc0_n_387;\n wire mem_intfc0_n_388;\n wire mem_intfc0_n_389;\n wire mem_intfc0_n_390;\n wire mem_intfc0_n_391;\n wire mem_intfc0_n_392;\n wire mem_intfc0_n_393;\n wire mem_intfc0_n_394;\n wire mem_intfc0_n_395;\n wire mem_intfc0_n_396;\n wire mem_intfc0_n_397;\n (* MAX_FANOUT = \"50\" *) (* RTL_MAX_FANOUT = \"found\" *) (* syn_maxfan = \"10\" *) wire mem_intfc0_n_77;\n wire [17:0]mem_out;\n wire mem_refclk;\n wire \\mmcm_current_reg[0] ;\n wire \\mmcm_init_trail_reg[0] ;\n wire mmcm_locked;\n wire mmcm_ps_clk;\n wire [256:0]out;\n wire p_81_in;\n wire pass_open_bank_r;\n wire pass_open_bank_r_1;\n wire pass_open_bank_r_3;\n wire pass_open_bank_r_5;\n wire pass_open_bank_r_lcl_reg;\n wire [5:0]phy_dout;\n wire phy_mc_go;\n wire pi_cnt_dec;\n wire [0:0]pi_cnt_dec_reg;\n wire \\pi_rst_stg1_cal_r_reg[0] ;\n wire pll_locked;\n wire po_cnt_dec;\n wire [0:0]po_cnt_dec_reg;\n wire poc_sample_pd;\n wire psdone;\n wire [3:0]ram_init_addr;\n wire ram_init_done_r;\n wire [4:0]rd_data_addr;\n wire rd_data_end;\n wire rd_data_offset;\n wire [71:0]\\rd_ptr_reg[3] ;\n wire [29:0]\\rd_ptr_reg[3]_0 ;\n wire [37:0]\\rd_ptr_timing_reg[0] ;\n wire [4:0]\\rd_ptr_timing_reg[0]_0 ;\n wire \\rd_ptr_timing_reg[2] ;\n wire \\rd_ptr_timing_reg[2]_0 ;\n wire \\rd_ptr_timing_reg[2]_1 ;\n wire \\rd_ptr_timing_reg[2]_10 ;\n wire \\rd_ptr_timing_reg[2]_2 ;\n wire \\rd_ptr_timing_reg[2]_3 ;\n wire \\rd_ptr_timing_reg[2]_4 ;\n wire \\rd_ptr_timing_reg[2]_5 ;\n wire \\rd_ptr_timing_reg[2]_6 ;\n wire \\rd_ptr_timing_reg[2]_7 ;\n wire \\rd_ptr_timing_reg[2]_8 ;\n wire \\rd_ptr_timing_reg[2]_9 ;\n wire reset_reg_n_0;\n wire \\resume_wait_r_reg[5] ;\n wire [14:0]row;\n wire \\row_cnt_victim_rotate.complex_row_cnt_reg[4] ;\n wire [0:0]\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ;\n wire rst_sync_r1;\n wire rst_sync_r1_reg;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__10;\n wire [0:0]rstdiv0_sync_r1_reg_rep__11;\n wire rstdiv0_sync_r1_reg_rep__12;\n wire rstdiv0_sync_r1_reg_rep__13;\n wire [1:0]rstdiv0_sync_r1_reg_rep__14;\n wire [0:0]rstdiv0_sync_r1_reg_rep__16;\n wire [0:0]rstdiv0_sync_r1_reg_rep__17;\n wire [0:0]rstdiv0_sync_r1_reg_rep__18;\n wire [0:0]rstdiv0_sync_r1_reg_rep__19;\n wire rstdiv0_sync_r1_reg_rep__2;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire rstdiv0_sync_r1_reg_rep__22;\n wire rstdiv0_sync_r1_reg_rep__23;\n wire rstdiv0_sync_r1_reg_rep__24;\n wire rstdiv0_sync_r1_reg_rep__24_0;\n wire rstdiv0_sync_r1_reg_rep__24_1;\n wire rstdiv0_sync_r1_reg_rep__25;\n wire rstdiv0_sync_r1_reg_rep__26;\n wire rstdiv0_sync_r1_reg_rep__26_0;\n wire rstdiv0_sync_r1_reg_rep__26_1;\n wire rstdiv0_sync_r1_reg_rep__26_2;\n wire rstdiv0_sync_r1_reg_rep__4;\n wire [0:0]rstdiv0_sync_r1_reg_rep__5;\n wire rstdiv0_sync_r1_reg_rep__6;\n wire rstdiv0_sync_r1_reg_rep__7;\n wire rstdiv0_sync_r1_reg_rep__8;\n wire rstdiv0_sync_r1_reg_rep__9;\n wire rtp_timer_ns1;\n wire rtp_timer_ns1_6;\n wire rtp_timer_ns1_7;\n wire [29:0]s_axi_araddr;\n wire [0:0]s_axi_arburst;\n wire [0:0]s_axi_arid;\n wire [7:0]s_axi_arlen;\n wire s_axi_arready;\n wire s_axi_arvalid;\n wire [29:0]s_axi_awaddr;\n wire [0:0]s_axi_awburst;\n wire [0:0]s_axi_awid;\n wire [7:0]s_axi_awlen;\n wire s_axi_awready;\n wire s_axi_awvalid;\n wire [0:0]s_axi_bid;\n wire s_axi_bready;\n wire s_axi_bvalid;\n wire [0:0]s_axi_rid;\n wire s_axi_rlast;\n wire s_axi_rready;\n wire s_axi_rvalid;\n wire [255:0]s_axi_wdata;\n wire s_axi_wready;\n wire [31:0]s_axi_wstrb;\n wire s_axi_wvalid;\n wire samp_edge_cnt0_en_r;\n wire samp_edge_cnt0_en_r_reg;\n wire sm_r;\n wire \\sm_r_reg[0] ;\n wire [0:0]\\sm_r_reg[0]_0 ;\n wire \\stg2_tap_cnt_reg[0] ;\n wire stg3_dec2init_val_r_reg;\n wire stg3_inc2init_val_r_reg;\n wire \\stg3_r_reg[0] ;\n wire sync_pulse;\n wire sys_rst;\n wire u_ui_top_n_1;\n wire u_ui_top_n_260;\n wire u_ui_top_n_261;\n wire u_ui_top_n_269;\n wire u_ui_top_n_270;\n wire u_ui_top_n_274;\n wire u_ui_top_n_275;\n wire u_ui_top_n_276;\n wire \\ui_cmd0/app_addr_r10 ;\n wire \\ui_cmd0/app_en_ns1 ;\n wire \\ui_cmd0/app_en_r1 ;\n wire \\ui_cmd0/app_hi_pri_r2 ;\n wire \\ui_rd_data0/app_rd_data_end_ns ;\n wire \\ui_rd_data0/bypass__0 ;\n wire [1:0]\\ui_rd_data0/p_100_out ;\n wire [1:0]\\ui_rd_data0/p_101_out ;\n wire [1:0]\\ui_rd_data0/p_102_out ;\n wire [1:0]\\ui_rd_data0/p_103_out ;\n wire [1:0]\\ui_rd_data0/p_104_out ;\n wire [1:0]\\ui_rd_data0/p_105_out ;\n wire [1:0]\\ui_rd_data0/p_106_out ;\n wire [1:0]\\ui_rd_data0/p_107_out ;\n wire [1:0]\\ui_rd_data0/p_108_out ;\n wire [1:0]\\ui_rd_data0/p_109_out ;\n wire [1:0]\\ui_rd_data0/p_10_out ;\n wire [1:0]\\ui_rd_data0/p_110_out ;\n wire [1:0]\\ui_rd_data0/p_111_out ;\n wire [1:0]\\ui_rd_data0/p_112_out ;\n wire [1:0]\\ui_rd_data0/p_113_out ;\n wire [1:0]\\ui_rd_data0/p_114_out ;\n wire [1:0]\\ui_rd_data0/p_115_out ;\n wire [1:0]\\ui_rd_data0/p_116_out ;\n wire [1:0]\\ui_rd_data0/p_117_out ;\n wire [1:0]\\ui_rd_data0/p_118_out ;\n wire [1:0]\\ui_rd_data0/p_119_out ;\n wire [1:0]\\ui_rd_data0/p_11_out ;\n wire [1:0]\\ui_rd_data0/p_120_out ;\n wire [1:0]\\ui_rd_data0/p_121_out ;\n wire [1:0]\\ui_rd_data0/p_122_out ;\n wire [1:0]\\ui_rd_data0/p_123_out ;\n wire [1:0]\\ui_rd_data0/p_124_out ;\n wire [1:0]\\ui_rd_data0/p_125_out ;\n wire [1:0]\\ui_rd_data0/p_127_out ;\n wire [1:0]\\ui_rd_data0/p_128_out ;\n wire [1:0]\\ui_rd_data0/p_129_out ;\n wire [1:0]\\ui_rd_data0/p_12_out ;\n wire [1:0]\\ui_rd_data0/p_13_out ;\n wire [1:0]\\ui_rd_data0/p_14_out ;\n wire [1:0]\\ui_rd_data0/p_15_out ;\n wire [1:0]\\ui_rd_data0/p_16_out ;\n wire [1:0]\\ui_rd_data0/p_17_out ;\n wire [1:0]\\ui_rd_data0/p_18_out ;\n wire [1:0]\\ui_rd_data0/p_19_out ;\n wire [1:0]\\ui_rd_data0/p_1_out ;\n wire [1:0]\\ui_rd_data0/p_20_out ;\n wire [1:0]\\ui_rd_data0/p_21_out ;\n wire [1:0]\\ui_rd_data0/p_22_out ;\n wire [1:0]\\ui_rd_data0/p_23_out ;\n wire [1:0]\\ui_rd_data0/p_24_out ;\n wire [1:0]\\ui_rd_data0/p_25_out ;\n wire [1:0]\\ui_rd_data0/p_26_out ;\n wire [1:0]\\ui_rd_data0/p_27_out ;\n wire [1:0]\\ui_rd_data0/p_28_out ;\n wire [1:0]\\ui_rd_data0/p_29_out ;\n wire [1:0]\\ui_rd_data0/p_30_out ;\n wire [1:0]\\ui_rd_data0/p_31_out ;\n wire [1:0]\\ui_rd_data0/p_32_out ;\n wire [1:0]\\ui_rd_data0/p_33_out ;\n wire [1:0]\\ui_rd_data0/p_34_out ;\n wire [1:0]\\ui_rd_data0/p_35_out ;\n wire [1:0]\\ui_rd_data0/p_36_out ;\n wire [1:0]\\ui_rd_data0/p_37_out ;\n wire [1:0]\\ui_rd_data0/p_38_out ;\n wire [1:0]\\ui_rd_data0/p_39_out ;\n wire [1:0]\\ui_rd_data0/p_3_out ;\n wire [1:0]\\ui_rd_data0/p_40_out ;\n wire [1:0]\\ui_rd_data0/p_41_out ;\n wire [1:0]\\ui_rd_data0/p_42_out ;\n wire [1:0]\\ui_rd_data0/p_43_out ;\n wire [1:0]\\ui_rd_data0/p_44_out ;\n wire [1:0]\\ui_rd_data0/p_45_out ;\n wire [1:0]\\ui_rd_data0/p_46_out ;\n wire [1:0]\\ui_rd_data0/p_47_out ;\n wire [1:0]\\ui_rd_data0/p_48_out ;\n wire [1:0]\\ui_rd_data0/p_49_out ;\n wire [1:0]\\ui_rd_data0/p_4_out ;\n wire [1:0]\\ui_rd_data0/p_50_out ;\n wire [1:0]\\ui_rd_data0/p_51_out ;\n wire [1:0]\\ui_rd_data0/p_52_out ;\n wire [1:0]\\ui_rd_data0/p_53_out ;\n wire [1:0]\\ui_rd_data0/p_54_out ;\n wire [1:0]\\ui_rd_data0/p_55_out ;\n wire [1:0]\\ui_rd_data0/p_56_out ;\n wire [1:0]\\ui_rd_data0/p_57_out ;\n wire [1:0]\\ui_rd_data0/p_58_out ;\n wire [1:0]\\ui_rd_data0/p_59_out ;\n wire [1:0]\\ui_rd_data0/p_5_out ;\n wire [1:0]\\ui_rd_data0/p_60_out ;\n wire [1:0]\\ui_rd_data0/p_61_out ;\n wire [1:0]\\ui_rd_data0/p_62_out ;\n wire [1:0]\\ui_rd_data0/p_63_out ;\n wire [1:0]\\ui_rd_data0/p_64_out ;\n wire [1:0]\\ui_rd_data0/p_65_out ;\n wire [1:0]\\ui_rd_data0/p_66_out ;\n wire [1:0]\\ui_rd_data0/p_67_out ;\n wire [1:0]\\ui_rd_data0/p_68_out ;\n wire [1:0]\\ui_rd_data0/p_69_out ;\n wire [1:0]\\ui_rd_data0/p_6_out ;\n wire [1:0]\\ui_rd_data0/p_70_out ;\n wire [1:0]\\ui_rd_data0/p_71_out ;\n wire [1:0]\\ui_rd_data0/p_72_out ;\n wire [1:0]\\ui_rd_data0/p_73_out ;\n wire [1:0]\\ui_rd_data0/p_74_out ;\n wire [1:0]\\ui_rd_data0/p_75_out ;\n wire [1:0]\\ui_rd_data0/p_76_out ;\n wire [1:0]\\ui_rd_data0/p_77_out ;\n wire [1:0]\\ui_rd_data0/p_78_out ;\n wire [1:0]\\ui_rd_data0/p_79_out ;\n wire [1:0]\\ui_rd_data0/p_7_out ;\n wire [1:0]\\ui_rd_data0/p_80_out ;\n wire [1:0]\\ui_rd_data0/p_81_out ;\n wire [1:0]\\ui_rd_data0/p_82_out ;\n wire [1:0]\\ui_rd_data0/p_83_out ;\n wire [1:0]\\ui_rd_data0/p_84_out ;\n wire [1:0]\\ui_rd_data0/p_85_out ;\n wire [1:0]\\ui_rd_data0/p_86_out ;\n wire [1:0]\\ui_rd_data0/p_87_out ;\n wire [1:0]\\ui_rd_data0/p_88_out ;\n wire [1:0]\\ui_rd_data0/p_89_out ;\n wire [1:0]\\ui_rd_data0/p_8_out ;\n wire [1:0]\\ui_rd_data0/p_90_out ;\n wire [1:0]\\ui_rd_data0/p_91_out ;\n wire [1:0]\\ui_rd_data0/p_92_out ;\n wire [1:0]\\ui_rd_data0/p_93_out ;\n wire [1:0]\\ui_rd_data0/p_94_out ;\n wire [1:0]\\ui_rd_data0/p_95_out ;\n wire [1:0]\\ui_rd_data0/p_96_out ;\n wire [1:0]\\ui_rd_data0/p_97_out ;\n wire [1:0]\\ui_rd_data0/p_98_out ;\n wire [1:0]\\ui_rd_data0/p_99_out ;\n wire [1:0]\\ui_rd_data0/p_9_out ;\n wire \\ui_rd_data0/rd_buf_we ;\n wire [1:1]\\ui_rd_data0/rd_status ;\n wire \\ui_wr_data0/pointer_we ;\n wire use_addr;\n wire w_cmd_rdy;\n wire [255:0]wr_data;\n wire [3:0]wr_data_addr;\n wire wr_data_en;\n wire [31:0]wr_data_mask;\n wire wr_en;\n wire wr_en_5;\n wire wr_en_6;\n wire [3:0]\\wr_ptr_timing_reg[2] ;\n wire [3:0]\\wr_ptr_timing_reg[2]_0 ;\n\n FDRE init_calib_complete_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(mem_intfc0_n_77),\n .Q(init_calib_complete_r),\n .R(1'b0));\n ddr3_if_mig_7series_v4_0_mem_intfc mem_intfc0\n (.CLK(CLK),\n .CLKB0(CLKB0),\n .CLKB0_7(CLKB0_7),\n .CLKB0_8(CLKB0_8),\n .CLKB0_9(CLKB0_9),\n .D(D),\n .DOA(\\ui_rd_data0/p_129_out ),\n .DOB(\\ui_rd_data0/p_128_out ),\n .DOC(\\ui_rd_data0/p_127_out ),\n .E(wr_data_en),\n .Q({wr_data_mask,wr_data}),\n .RST0(RST0),\n .SR(SR),\n .SS(SS),\n .accept_ns(accept_ns),\n .act_wait_r_lcl_reg(pass_open_bank_r),\n .act_wait_r_lcl_reg_0(pass_open_bank_r_1),\n .act_wait_r_lcl_reg_1(pass_open_bank_r_3),\n .act_wait_r_lcl_reg_2(pass_open_bank_r_5),\n .\\app_addr_r1_reg[12] (bank),\n .\\app_addr_r1_reg[27] (row),\n .\\app_addr_r1_reg[9] (col),\n .\\app_cmd_r1_reg[0] (u_ui_top_n_269),\n .\\app_cmd_r2_reg[1] (cmd),\n .app_hi_pri_r2(\\ui_cmd0/app_hi_pri_r2 ),\n .app_rd_data_end_ns(\\ui_rd_data0/app_rd_data_end_ns ),\n .app_ref_ack(app_ref_ack),\n .app_ref_req(app_ref_req),\n .app_sr_active(app_sr_active),\n .app_sr_req(app_sr_req),\n .app_zq_ack(app_zq_ack),\n .app_zq_req(app_zq_req),\n .bm_end_r1(bm_end_r1),\n .bm_end_r1_0(bm_end_r1_0),\n .bm_end_r1_4(bm_end_r1_4),\n .bm_end_r1_reg(bm_end_r1_reg),\n .bm_end_r1_reg_0(bm_end_r1_reg_0),\n .bm_end_r1_reg_1(bm_end_r1_reg_1),\n .bm_end_r1_reg_2(bm_end_r1_reg_2),\n .bypass__0(\\ui_rd_data0/bypass__0 ),\n .\\calib_seq_reg[0] (phy_mc_go),\n .cnt_pwron_reset_done_r0(cnt_pwron_reset_done_r0),\n .\\complex_row_cnt_ocal_reg[0] (\\complex_row_cnt_ocal_reg[0] ),\n .ddr3_addr(ddr3_addr),\n .ddr3_ba(ddr3_ba),\n .ddr3_cas_n(ddr3_cas_n),\n .ddr3_cke(ddr3_cke),\n .ddr3_cs_n(ddr3_cs_n),\n .ddr3_dm(ddr3_dm),\n .ddr3_dq(ddr3_dq),\n .ddr3_dqs_n(ddr3_dqs_n),\n .ddr3_dqs_p(ddr3_dqs_p),\n .ddr3_odt(ddr3_odt),\n .ddr3_ras_n(ddr3_ras_n),\n .ddr3_reset_n(ddr3_reset_n),\n .ddr3_we_n(ddr3_we_n),\n .ddr_ck_out(ddr_ck_out),\n .\\device_temp_r_reg[11] (\\device_temp_r_reg[11] ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ),\n .dqs_po_en_stg2_f_reg(po_cnt_dec),\n .\\en_cnt_div4.enable_wrlvl_cnt_reg[3] (\\en_cnt_div4.enable_wrlvl_cnt_reg[3] ),\n .fine_adjust_reg(fine_adjust_reg),\n .freq_refclk(freq_refclk),\n .hi_priority(hi_priority),\n .in0(in0),\n .init_calib_complete_r_reg(mem_intfc0_n_77),\n .mem_out(mem_out),\n .mem_refclk(mem_refclk),\n .\\mmcm_current_reg[0] (\\mmcm_current_reg[0] ),\n .\\mmcm_init_trail_reg[0] (\\mmcm_init_trail_reg[0] ),\n .mmcm_locked(mmcm_locked),\n .mmcm_ps_clk(mmcm_ps_clk),\n .\\not_strict_mode.app_rd_data_end_reg ({rd_data_end,rd_data_addr,rd_data_offset}),\n .\\not_strict_mode.app_rd_data_reg[0] (mem_intfc0_n_397),\n .\\not_strict_mode.app_rd_data_reg[100] (mem_intfc0_n_285),\n .\\not_strict_mode.app_rd_data_reg[101] (mem_intfc0_n_281),\n .\\not_strict_mode.app_rd_data_reg[102] (mem_intfc0_n_277),\n .\\not_strict_mode.app_rd_data_reg[103] (mem_intfc0_n_273),\n .\\not_strict_mode.app_rd_data_reg[104] (mem_intfc0_n_299),\n .\\not_strict_mode.app_rd_data_reg[105] (mem_intfc0_n_295),\n .\\not_strict_mode.app_rd_data_reg[106] (mem_intfc0_n_291),\n .\\not_strict_mode.app_rd_data_reg[107] (mem_intfc0_n_287),\n .\\not_strict_mode.app_rd_data_reg[108] (mem_intfc0_n_283),\n .\\not_strict_mode.app_rd_data_reg[109] (mem_intfc0_n_279),\n .\\not_strict_mode.app_rd_data_reg[10] (mem_intfc0_n_387),\n .\\not_strict_mode.app_rd_data_reg[110] (mem_intfc0_n_275),\n .\\not_strict_mode.app_rd_data_reg[111] (mem_intfc0_n_271),\n .\\not_strict_mode.app_rd_data_reg[112] (mem_intfc0_n_300),\n .\\not_strict_mode.app_rd_data_reg[113] (mem_intfc0_n_296),\n .\\not_strict_mode.app_rd_data_reg[114] (mem_intfc0_n_292),\n .\\not_strict_mode.app_rd_data_reg[115] (mem_intfc0_n_288),\n .\\not_strict_mode.app_rd_data_reg[116] (mem_intfc0_n_284),\n .\\not_strict_mode.app_rd_data_reg[117] (mem_intfc0_n_280),\n .\\not_strict_mode.app_rd_data_reg[118] (mem_intfc0_n_276),\n .\\not_strict_mode.app_rd_data_reg[119] (mem_intfc0_n_272),\n .\\not_strict_mode.app_rd_data_reg[11] (mem_intfc0_n_383),\n .\\not_strict_mode.app_rd_data_reg[120] (mem_intfc0_n_298),\n .\\not_strict_mode.app_rd_data_reg[121] (mem_intfc0_n_294),\n .\\not_strict_mode.app_rd_data_reg[122] (mem_intfc0_n_290),\n .\\not_strict_mode.app_rd_data_reg[123] (mem_intfc0_n_286),\n .\\not_strict_mode.app_rd_data_reg[124] (mem_intfc0_n_282),\n .\\not_strict_mode.app_rd_data_reg[125] (mem_intfc0_n_278),\n .\\not_strict_mode.app_rd_data_reg[126] (mem_intfc0_n_274),\n .\\not_strict_mode.app_rd_data_reg[127] (mem_intfc0_n_270),\n .\\not_strict_mode.app_rd_data_reg[128] (mem_intfc0_n_269),\n .\\not_strict_mode.app_rd_data_reg[129] (mem_intfc0_n_265),\n .\\not_strict_mode.app_rd_data_reg[12] (mem_intfc0_n_379),\n .\\not_strict_mode.app_rd_data_reg[130] (mem_intfc0_n_261),\n .\\not_strict_mode.app_rd_data_reg[131] (mem_intfc0_n_257),\n .\\not_strict_mode.app_rd_data_reg[132] (mem_intfc0_n_253),\n .\\not_strict_mode.app_rd_data_reg[133] (mem_intfc0_n_249),\n .\\not_strict_mode.app_rd_data_reg[134] (mem_intfc0_n_245),\n .\\not_strict_mode.app_rd_data_reg[135] (mem_intfc0_n_241),\n .\\not_strict_mode.app_rd_data_reg[136] (mem_intfc0_n_267),\n .\\not_strict_mode.app_rd_data_reg[137] (mem_intfc0_n_263),\n .\\not_strict_mode.app_rd_data_reg[138] (mem_intfc0_n_259),\n .\\not_strict_mode.app_rd_data_reg[139] (mem_intfc0_n_255),\n .\\not_strict_mode.app_rd_data_reg[13] (mem_intfc0_n_375),\n .\\not_strict_mode.app_rd_data_reg[140] (mem_intfc0_n_251),\n .\\not_strict_mode.app_rd_data_reg[141] (mem_intfc0_n_247),\n .\\not_strict_mode.app_rd_data_reg[142] (mem_intfc0_n_243),\n .\\not_strict_mode.app_rd_data_reg[143] (mem_intfc0_n_239),\n .\\not_strict_mode.app_rd_data_reg[144] (mem_intfc0_n_268),\n .\\not_strict_mode.app_rd_data_reg[145] (mem_intfc0_n_264),\n .\\not_strict_mode.app_rd_data_reg[146] (mem_intfc0_n_260),\n .\\not_strict_mode.app_rd_data_reg[147] (mem_intfc0_n_256),\n .\\not_strict_mode.app_rd_data_reg[148] (mem_intfc0_n_252),\n .\\not_strict_mode.app_rd_data_reg[149] (mem_intfc0_n_248),\n .\\not_strict_mode.app_rd_data_reg[14] (mem_intfc0_n_371),\n .\\not_strict_mode.app_rd_data_reg[150] (mem_intfc0_n_244),\n .\\not_strict_mode.app_rd_data_reg[151] (mem_intfc0_n_240),\n .\\not_strict_mode.app_rd_data_reg[152] (mem_intfc0_n_266),\n .\\not_strict_mode.app_rd_data_reg[153] (mem_intfc0_n_262),\n .\\not_strict_mode.app_rd_data_reg[154] (mem_intfc0_n_258),\n .\\not_strict_mode.app_rd_data_reg[155] (mem_intfc0_n_254),\n .\\not_strict_mode.app_rd_data_reg[156] (mem_intfc0_n_250),\n .\\not_strict_mode.app_rd_data_reg[157] (mem_intfc0_n_246),\n .\\not_strict_mode.app_rd_data_reg[158] (mem_intfc0_n_242),\n .\\not_strict_mode.app_rd_data_reg[159] (mem_intfc0_n_238),\n .\\not_strict_mode.app_rd_data_reg[15] (mem_intfc0_n_367),\n .\\not_strict_mode.app_rd_data_reg[160] (mem_intfc0_n_237),\n .\\not_strict_mode.app_rd_data_reg[161] (mem_intfc0_n_233),\n .\\not_strict_mode.app_rd_data_reg[162] (mem_intfc0_n_229),\n .\\not_strict_mode.app_rd_data_reg[163] (mem_intfc0_n_225),\n .\\not_strict_mode.app_rd_data_reg[164] (mem_intfc0_n_221),\n .\\not_strict_mode.app_rd_data_reg[165] (mem_intfc0_n_217),\n .\\not_strict_mode.app_rd_data_reg[166] (mem_intfc0_n_213),\n .\\not_strict_mode.app_rd_data_reg[167] (mem_intfc0_n_209),\n .\\not_strict_mode.app_rd_data_reg[168] (mem_intfc0_n_235),\n .\\not_strict_mode.app_rd_data_reg[169] (mem_intfc0_n_231),\n .\\not_strict_mode.app_rd_data_reg[16] (mem_intfc0_n_396),\n .\\not_strict_mode.app_rd_data_reg[170] (mem_intfc0_n_227),\n .\\not_strict_mode.app_rd_data_reg[171] (mem_intfc0_n_223),\n .\\not_strict_mode.app_rd_data_reg[172] (mem_intfc0_n_219),\n .\\not_strict_mode.app_rd_data_reg[173] (mem_intfc0_n_215),\n .\\not_strict_mode.app_rd_data_reg[174] (mem_intfc0_n_211),\n .\\not_strict_mode.app_rd_data_reg[175] (mem_intfc0_n_207),\n .\\not_strict_mode.app_rd_data_reg[176] (mem_intfc0_n_236),\n .\\not_strict_mode.app_rd_data_reg[177] (mem_intfc0_n_232),\n .\\not_strict_mode.app_rd_data_reg[178] (mem_intfc0_n_228),\n .\\not_strict_mode.app_rd_data_reg[179] (mem_intfc0_n_224),\n .\\not_strict_mode.app_rd_data_reg[17] (mem_intfc0_n_392),\n .\\not_strict_mode.app_rd_data_reg[180] (mem_intfc0_n_220),\n .\\not_strict_mode.app_rd_data_reg[181] (mem_intfc0_n_216),\n .\\not_strict_mode.app_rd_data_reg[182] (mem_intfc0_n_212),\n .\\not_strict_mode.app_rd_data_reg[183] (mem_intfc0_n_208),\n .\\not_strict_mode.app_rd_data_reg[184] (mem_intfc0_n_234),\n .\\not_strict_mode.app_rd_data_reg[185] (mem_intfc0_n_230),\n .\\not_strict_mode.app_rd_data_reg[186] (mem_intfc0_n_226),\n .\\not_strict_mode.app_rd_data_reg[187] (mem_intfc0_n_222),\n .\\not_strict_mode.app_rd_data_reg[188] (mem_intfc0_n_218),\n .\\not_strict_mode.app_rd_data_reg[189] (mem_intfc0_n_214),\n .\\not_strict_mode.app_rd_data_reg[18] (mem_intfc0_n_388),\n .\\not_strict_mode.app_rd_data_reg[190] (mem_intfc0_n_210),\n .\\not_strict_mode.app_rd_data_reg[191] (mem_intfc0_n_206),\n .\\not_strict_mode.app_rd_data_reg[192] (mem_intfc0_n_205),\n .\\not_strict_mode.app_rd_data_reg[193] (mem_intfc0_n_201),\n .\\not_strict_mode.app_rd_data_reg[194] (mem_intfc0_n_197),\n .\\not_strict_mode.app_rd_data_reg[195] (mem_intfc0_n_193),\n .\\not_strict_mode.app_rd_data_reg[196] (mem_intfc0_n_189),\n .\\not_strict_mode.app_rd_data_reg[197] (mem_intfc0_n_185),\n .\\not_strict_mode.app_rd_data_reg[198] (mem_intfc0_n_181),\n .\\not_strict_mode.app_rd_data_reg[199] (mem_intfc0_n_177),\n .\\not_strict_mode.app_rd_data_reg[19] (mem_intfc0_n_384),\n .\\not_strict_mode.app_rd_data_reg[1] (mem_intfc0_n_393),\n .\\not_strict_mode.app_rd_data_reg[200] (mem_intfc0_n_203),\n .\\not_strict_mode.app_rd_data_reg[201] (mem_intfc0_n_199),\n .\\not_strict_mode.app_rd_data_reg[202] (mem_intfc0_n_195),\n .\\not_strict_mode.app_rd_data_reg[203] (mem_intfc0_n_191),\n .\\not_strict_mode.app_rd_data_reg[204] (mem_intfc0_n_187),\n .\\not_strict_mode.app_rd_data_reg[205] (mem_intfc0_n_183),\n .\\not_strict_mode.app_rd_data_reg[206] (mem_intfc0_n_179),\n .\\not_strict_mode.app_rd_data_reg[207] (mem_intfc0_n_175),\n .\\not_strict_mode.app_rd_data_reg[208] (mem_intfc0_n_204),\n .\\not_strict_mode.app_rd_data_reg[209] (mem_intfc0_n_200),\n .\\not_strict_mode.app_rd_data_reg[20] (mem_intfc0_n_380),\n .\\not_strict_mode.app_rd_data_reg[210] (mem_intfc0_n_196),\n .\\not_strict_mode.app_rd_data_reg[211] (mem_intfc0_n_192),\n .\\not_strict_mode.app_rd_data_reg[212] (mem_intfc0_n_188),\n .\\not_strict_mode.app_rd_data_reg[213] (mem_intfc0_n_184),\n .\\not_strict_mode.app_rd_data_reg[214] (mem_intfc0_n_180),\n .\\not_strict_mode.app_rd_data_reg[215] (mem_intfc0_n_176),\n .\\not_strict_mode.app_rd_data_reg[216] (mem_intfc0_n_202),\n .\\not_strict_mode.app_rd_data_reg[217] (mem_intfc0_n_198),\n .\\not_strict_mode.app_rd_data_reg[218] (mem_intfc0_n_194),\n .\\not_strict_mode.app_rd_data_reg[219] (mem_intfc0_n_190),\n .\\not_strict_mode.app_rd_data_reg[21] (mem_intfc0_n_376),\n .\\not_strict_mode.app_rd_data_reg[220] (mem_intfc0_n_186),\n .\\not_strict_mode.app_rd_data_reg[221] (mem_intfc0_n_182),\n .\\not_strict_mode.app_rd_data_reg[222] (mem_intfc0_n_178),\n .\\not_strict_mode.app_rd_data_reg[223] (mem_intfc0_n_174),\n .\\not_strict_mode.app_rd_data_reg[224] (mem_intfc0_n_173),\n .\\not_strict_mode.app_rd_data_reg[225] (mem_intfc0_n_169),\n .\\not_strict_mode.app_rd_data_reg[226] (mem_intfc0_n_165),\n .\\not_strict_mode.app_rd_data_reg[227] (mem_intfc0_n_161),\n .\\not_strict_mode.app_rd_data_reg[228] (mem_intfc0_n_157),\n .\\not_strict_mode.app_rd_data_reg[229] (mem_intfc0_n_153),\n .\\not_strict_mode.app_rd_data_reg[22] (mem_intfc0_n_372),\n .\\not_strict_mode.app_rd_data_reg[230] (mem_intfc0_n_149),\n .\\not_strict_mode.app_rd_data_reg[231] (mem_intfc0_n_145),\n .\\not_strict_mode.app_rd_data_reg[232] (mem_intfc0_n_171),\n .\\not_strict_mode.app_rd_data_reg[233] (mem_intfc0_n_167),\n .\\not_strict_mode.app_rd_data_reg[234] (mem_intfc0_n_163),\n .\\not_strict_mode.app_rd_data_reg[235] (mem_intfc0_n_159),\n .\\not_strict_mode.app_rd_data_reg[236] (mem_intfc0_n_155),\n .\\not_strict_mode.app_rd_data_reg[237] (mem_intfc0_n_151),\n .\\not_strict_mode.app_rd_data_reg[238] (mem_intfc0_n_147),\n .\\not_strict_mode.app_rd_data_reg[239] (mem_intfc0_n_143),\n .\\not_strict_mode.app_rd_data_reg[23] (mem_intfc0_n_368),\n .\\not_strict_mode.app_rd_data_reg[240] (mem_intfc0_n_172),\n .\\not_strict_mode.app_rd_data_reg[241] (mem_intfc0_n_168),\n .\\not_strict_mode.app_rd_data_reg[242] (mem_intfc0_n_164),\n .\\not_strict_mode.app_rd_data_reg[243] (mem_intfc0_n_160),\n .\\not_strict_mode.app_rd_data_reg[244] (mem_intfc0_n_156),\n .\\not_strict_mode.app_rd_data_reg[245] (mem_intfc0_n_152),\n .\\not_strict_mode.app_rd_data_reg[246] (mem_intfc0_n_148),\n .\\not_strict_mode.app_rd_data_reg[247] (mem_intfc0_n_144),\n .\\not_strict_mode.app_rd_data_reg[248] (mem_intfc0_n_170),\n .\\not_strict_mode.app_rd_data_reg[249] (mem_intfc0_n_166),\n .\\not_strict_mode.app_rd_data_reg[24] (mem_intfc0_n_394),\n .\\not_strict_mode.app_rd_data_reg[250] (mem_intfc0_n_162),\n .\\not_strict_mode.app_rd_data_reg[251] (mem_intfc0_n_158),\n .\\not_strict_mode.app_rd_data_reg[252] (mem_intfc0_n_154),\n .\\not_strict_mode.app_rd_data_reg[253] (mem_intfc0_n_150),\n .\\not_strict_mode.app_rd_data_reg[254] (mem_intfc0_n_146),\n .\\not_strict_mode.app_rd_data_reg[255] (mem_intfc0_n_142),\n .\\not_strict_mode.app_rd_data_reg[255]_0 (app_rd_data_ns),\n .\\not_strict_mode.app_rd_data_reg[25] (mem_intfc0_n_390),\n .\\not_strict_mode.app_rd_data_reg[26] (mem_intfc0_n_386),\n .\\not_strict_mode.app_rd_data_reg[27] (mem_intfc0_n_382),\n .\\not_strict_mode.app_rd_data_reg[28] (mem_intfc0_n_378),\n .\\not_strict_mode.app_rd_data_reg[29] (mem_intfc0_n_374),\n .\\not_strict_mode.app_rd_data_reg[2] (mem_intfc0_n_389),\n .\\not_strict_mode.app_rd_data_reg[30] (mem_intfc0_n_370),\n .\\not_strict_mode.app_rd_data_reg[31] (mem_intfc0_n_366),\n .\\not_strict_mode.app_rd_data_reg[32] (mem_intfc0_n_365),\n .\\not_strict_mode.app_rd_data_reg[33] (mem_intfc0_n_361),\n .\\not_strict_mode.app_rd_data_reg[34] (mem_intfc0_n_357),\n .\\not_strict_mode.app_rd_data_reg[35] (mem_intfc0_n_353),\n .\\not_strict_mode.app_rd_data_reg[36] (mem_intfc0_n_349),\n .\\not_strict_mode.app_rd_data_reg[37] (mem_intfc0_n_345),\n .\\not_strict_mode.app_rd_data_reg[38] (mem_intfc0_n_341),\n .\\not_strict_mode.app_rd_data_reg[39] (mem_intfc0_n_337),\n .\\not_strict_mode.app_rd_data_reg[3] (mem_intfc0_n_385),\n .\\not_strict_mode.app_rd_data_reg[40] (mem_intfc0_n_363),\n .\\not_strict_mode.app_rd_data_reg[41] (mem_intfc0_n_359),\n .\\not_strict_mode.app_rd_data_reg[42] (mem_intfc0_n_355),\n .\\not_strict_mode.app_rd_data_reg[43] (mem_intfc0_n_351),\n .\\not_strict_mode.app_rd_data_reg[44] (mem_intfc0_n_347),\n .\\not_strict_mode.app_rd_data_reg[45] (mem_intfc0_n_343),\n .\\not_strict_mode.app_rd_data_reg[46] (mem_intfc0_n_339),\n .\\not_strict_mode.app_rd_data_reg[47] (mem_intfc0_n_335),\n .\\not_strict_mode.app_rd_data_reg[48] (mem_intfc0_n_364),\n .\\not_strict_mode.app_rd_data_reg[49] (mem_intfc0_n_360),\n .\\not_strict_mode.app_rd_data_reg[4] (mem_intfc0_n_381),\n .\\not_strict_mode.app_rd_data_reg[50] (mem_intfc0_n_356),\n .\\not_strict_mode.app_rd_data_reg[51] (mem_intfc0_n_352),\n .\\not_strict_mode.app_rd_data_reg[52] (mem_intfc0_n_348),\n .\\not_strict_mode.app_rd_data_reg[53] (mem_intfc0_n_344),\n .\\not_strict_mode.app_rd_data_reg[54] (mem_intfc0_n_340),\n .\\not_strict_mode.app_rd_data_reg[55] (mem_intfc0_n_336),\n .\\not_strict_mode.app_rd_data_reg[56] (mem_intfc0_n_362),\n .\\not_strict_mode.app_rd_data_reg[57] (mem_intfc0_n_358),\n .\\not_strict_mode.app_rd_data_reg[58] (mem_intfc0_n_354),\n .\\not_strict_mode.app_rd_data_reg[59] (mem_intfc0_n_350),\n .\\not_strict_mode.app_rd_data_reg[5] (mem_intfc0_n_377),\n .\\not_strict_mode.app_rd_data_reg[60] (mem_intfc0_n_346),\n .\\not_strict_mode.app_rd_data_reg[61] (mem_intfc0_n_342),\n .\\not_strict_mode.app_rd_data_reg[62] (mem_intfc0_n_338),\n .\\not_strict_mode.app_rd_data_reg[63] (mem_intfc0_n_334),\n .\\not_strict_mode.app_rd_data_reg[64] (mem_intfc0_n_333),\n .\\not_strict_mode.app_rd_data_reg[65] (mem_intfc0_n_329),\n .\\not_strict_mode.app_rd_data_reg[66] (mem_intfc0_n_325),\n .\\not_strict_mode.app_rd_data_reg[67] (mem_intfc0_n_321),\n .\\not_strict_mode.app_rd_data_reg[68] (mem_intfc0_n_317),\n .\\not_strict_mode.app_rd_data_reg[69] (mem_intfc0_n_313),\n .\\not_strict_mode.app_rd_data_reg[6] (mem_intfc0_n_373),\n .\\not_strict_mode.app_rd_data_reg[70] (mem_intfc0_n_309),\n .\\not_strict_mode.app_rd_data_reg[71] (mem_intfc0_n_305),\n .\\not_strict_mode.app_rd_data_reg[72] (mem_intfc0_n_331),\n .\\not_strict_mode.app_rd_data_reg[73] (mem_intfc0_n_327),\n .\\not_strict_mode.app_rd_data_reg[74] (mem_intfc0_n_323),\n .\\not_strict_mode.app_rd_data_reg[75] (mem_intfc0_n_319),\n .\\not_strict_mode.app_rd_data_reg[76] (mem_intfc0_n_315),\n .\\not_strict_mode.app_rd_data_reg[77] (mem_intfc0_n_311),\n .\\not_strict_mode.app_rd_data_reg[78] (mem_intfc0_n_307),\n .\\not_strict_mode.app_rd_data_reg[79] (mem_intfc0_n_303),\n .\\not_strict_mode.app_rd_data_reg[7] (mem_intfc0_n_369),\n .\\not_strict_mode.app_rd_data_reg[80] (mem_intfc0_n_332),\n .\\not_strict_mode.app_rd_data_reg[81] (mem_intfc0_n_328),\n .\\not_strict_mode.app_rd_data_reg[82] (mem_intfc0_n_324),\n .\\not_strict_mode.app_rd_data_reg[83] (mem_intfc0_n_320),\n .\\not_strict_mode.app_rd_data_reg[84] (mem_intfc0_n_316),\n .\\not_strict_mode.app_rd_data_reg[85] (mem_intfc0_n_312),\n .\\not_strict_mode.app_rd_data_reg[86] (mem_intfc0_n_308),\n .\\not_strict_mode.app_rd_data_reg[87] (mem_intfc0_n_304),\n .\\not_strict_mode.app_rd_data_reg[88] (mem_intfc0_n_330),\n .\\not_strict_mode.app_rd_data_reg[89] (mem_intfc0_n_326),\n .\\not_strict_mode.app_rd_data_reg[8] (mem_intfc0_n_395),\n .\\not_strict_mode.app_rd_data_reg[90] (mem_intfc0_n_322),\n .\\not_strict_mode.app_rd_data_reg[91] (mem_intfc0_n_318),\n .\\not_strict_mode.app_rd_data_reg[92] (mem_intfc0_n_314),\n .\\not_strict_mode.app_rd_data_reg[93] (mem_intfc0_n_310),\n .\\not_strict_mode.app_rd_data_reg[94] (mem_intfc0_n_306),\n .\\not_strict_mode.app_rd_data_reg[95] (mem_intfc0_n_302),\n .\\not_strict_mode.app_rd_data_reg[96] (mem_intfc0_n_301),\n .\\not_strict_mode.app_rd_data_reg[97] (mem_intfc0_n_297),\n .\\not_strict_mode.app_rd_data_reg[98] (mem_intfc0_n_293),\n .\\not_strict_mode.app_rd_data_reg[99] (mem_intfc0_n_289),\n .\\not_strict_mode.app_rd_data_reg[9] (mem_intfc0_n_391),\n .\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (data_buf_addr),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] (\\ui_rd_data0/p_123_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0 (\\ui_rd_data0/p_124_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1 (\\ui_rd_data0/p_125_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10 (\\ui_rd_data0/p_116_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_100 (\\ui_rd_data0/p_26_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_101 (\\ui_rd_data0/p_21_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_102 (\\ui_rd_data0/p_22_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_103 (\\ui_rd_data0/p_23_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_104 (\\ui_rd_data0/p_18_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_105 (\\ui_rd_data0/p_19_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_106 (\\ui_rd_data0/p_20_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_107 (\\ui_rd_data0/p_15_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_108 (\\ui_rd_data0/p_16_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_109 (\\ui_rd_data0/p_17_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11 (\\ui_rd_data0/p_111_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_110 (\\ui_rd_data0/p_12_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_111 (\\ui_rd_data0/p_13_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_112 (\\ui_rd_data0/p_14_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_113 (\\ui_rd_data0/p_9_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_114 (\\ui_rd_data0/p_10_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_115 (\\ui_rd_data0/p_11_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_116 (\\ui_rd_data0/p_6_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_117 (\\ui_rd_data0/p_7_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_118 (\\ui_rd_data0/p_8_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_119 (\\ui_rd_data0/p_3_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12 (\\ui_rd_data0/p_112_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_120 (\\ui_rd_data0/p_4_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_121 (\\ui_rd_data0/p_5_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_122 ({u_ui_top_n_260,u_ui_top_n_261}),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_123 (\\ui_rd_data0/p_1_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13 (\\ui_rd_data0/p_113_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14 (\\ui_rd_data0/p_108_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15 (\\ui_rd_data0/p_109_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16 (\\ui_rd_data0/p_110_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17 (\\ui_rd_data0/p_105_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18 (\\ui_rd_data0/p_106_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19 (\\ui_rd_data0/p_107_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2 (\\ui_rd_data0/p_120_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20 (\\ui_rd_data0/p_102_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21 (\\ui_rd_data0/p_103_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22 (\\ui_rd_data0/p_104_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23 (\\ui_rd_data0/p_99_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24 (\\ui_rd_data0/p_100_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25 (\\ui_rd_data0/p_101_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26 (\\ui_rd_data0/p_96_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27 (\\ui_rd_data0/p_97_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28 (\\ui_rd_data0/p_98_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29 (\\ui_rd_data0/p_93_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3 (\\ui_rd_data0/p_121_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30 (\\ui_rd_data0/p_94_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31 (\\ui_rd_data0/p_95_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32 (\\ui_rd_data0/p_90_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33 (\\ui_rd_data0/p_91_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34 (\\ui_rd_data0/p_92_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35 (\\ui_rd_data0/p_87_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36 (\\ui_rd_data0/p_88_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37 (\\ui_rd_data0/p_89_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38 (\\ui_rd_data0/p_84_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39 (\\ui_rd_data0/p_85_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4 (\\ui_rd_data0/p_122_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40 (\\ui_rd_data0/p_86_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41 (\\ui_rd_data0/p_81_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42 (\\ui_rd_data0/p_82_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43 (\\ui_rd_data0/p_83_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44 (\\ui_rd_data0/p_78_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45 (\\ui_rd_data0/p_79_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46 (\\ui_rd_data0/p_80_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47 (\\ui_rd_data0/p_75_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48 (\\ui_rd_data0/p_76_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49 (\\ui_rd_data0/p_77_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5 (\\ui_rd_data0/p_117_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50 (\\ui_rd_data0/p_72_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51 (\\ui_rd_data0/p_73_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52 (\\ui_rd_data0/p_74_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53 (\\ui_rd_data0/p_69_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54 (\\ui_rd_data0/p_70_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55 (\\ui_rd_data0/p_71_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56 (\\ui_rd_data0/p_66_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57 (\\ui_rd_data0/p_67_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58 (\\ui_rd_data0/p_68_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59 (\\ui_rd_data0/p_63_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6 (\\ui_rd_data0/p_118_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60 (\\ui_rd_data0/p_64_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_61 (\\ui_rd_data0/p_65_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_62 (\\ui_rd_data0/p_60_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_63 (\\ui_rd_data0/p_61_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_64 (\\ui_rd_data0/p_62_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_65 (\\ui_rd_data0/p_57_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_66 (\\ui_rd_data0/p_58_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_67 (\\ui_rd_data0/p_59_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_68 (\\ui_rd_data0/p_54_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_69 (\\ui_rd_data0/p_55_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7 (\\ui_rd_data0/p_119_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_70 (\\ui_rd_data0/p_56_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_71 (\\ui_rd_data0/p_51_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_72 (\\ui_rd_data0/p_52_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_73 (\\ui_rd_data0/p_53_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_74 (\\ui_rd_data0/p_48_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_75 (\\ui_rd_data0/p_49_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_76 (\\ui_rd_data0/p_50_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_77 (\\ui_rd_data0/p_45_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_78 (\\ui_rd_data0/p_46_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_79 (\\ui_rd_data0/p_47_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8 (\\ui_rd_data0/p_114_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_80 (\\ui_rd_data0/p_42_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_81 (\\ui_rd_data0/p_43_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_82 (\\ui_rd_data0/p_44_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_83 (\\ui_rd_data0/p_39_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_84 (\\ui_rd_data0/p_40_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_85 (\\ui_rd_data0/p_41_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_86 (\\ui_rd_data0/p_36_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_87 (\\ui_rd_data0/p_37_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_88 (\\ui_rd_data0/p_38_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_89 (\\ui_rd_data0/p_33_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9 (\\ui_rd_data0/p_115_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_90 (\\ui_rd_data0/p_34_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_91 (\\ui_rd_data0/p_35_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_92 (\\ui_rd_data0/p_30_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_93 (\\ui_rd_data0/p_31_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_94 (\\ui_rd_data0/p_32_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_95 (\\ui_rd_data0/p_27_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_96 (\\ui_rd_data0/p_28_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_97 (\\ui_rd_data0/p_29_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_98 (\\ui_rd_data0/p_24_out ),\n .\\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_99 (\\ui_rd_data0/p_25_out ),\n .\\not_strict_mode.status_ram.rd_buf_we_r1_reg (\\ui_rd_data0/rd_status ),\n .p_81_in(p_81_in),\n .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg),\n .phy_dout(phy_dout),\n .pi_cnt_dec_reg(pi_cnt_dec_reg),\n .pi_en_stg2_f_timing_reg(pi_cnt_dec),\n .\\pi_rst_stg1_cal_r_reg[0] (\\pi_rst_stg1_cal_r_reg[0] ),\n .pll_locked(pll_locked),\n .po_cnt_dec_reg(po_cnt_dec_reg),\n .poc_sample_pd(poc_sample_pd),\n .pointer_we(\\ui_wr_data0/pointer_we ),\n .psdone(psdone),\n .\\qcntr_r_reg[0] (E),\n .ram_init_done_r(ram_init_done_r),\n .\\ras_timer_r_reg[2] (bm_end_r1_2),\n .\\rd_buf_indx.rd_buf_indx_r_reg[4] ({u_ui_top_n_1,ram_init_addr}),\n .rd_buf_we(\\ui_rd_data0/rd_buf_we ),\n .\\rd_ptr_reg[3] (\\rd_ptr_reg[3] ),\n .\\rd_ptr_reg[3]_0 (\\rd_ptr_reg[3]_0 ),\n .\\rd_ptr_timing_reg[0] (\\rd_ptr_timing_reg[0] ),\n .\\rd_ptr_timing_reg[0]_0 (\\rd_ptr_timing_reg[0]_0 ),\n .\\rd_ptr_timing_reg[2] (\\rd_ptr_timing_reg[2] ),\n .\\rd_ptr_timing_reg[2]_0 (\\rd_ptr_timing_reg[2]_0 ),\n .\\rd_ptr_timing_reg[2]_1 (\\rd_ptr_timing_reg[2]_1 ),\n .\\rd_ptr_timing_reg[2]_10 (\\rd_ptr_timing_reg[2]_10 ),\n .\\rd_ptr_timing_reg[2]_2 (\\rd_ptr_timing_reg[2]_2 ),\n .\\rd_ptr_timing_reg[2]_3 (\\rd_ptr_timing_reg[2]_3 ),\n .\\rd_ptr_timing_reg[2]_4 (\\rd_ptr_timing_reg[2]_4 ),\n .\\rd_ptr_timing_reg[2]_5 (\\rd_ptr_timing_reg[2]_5 ),\n .\\rd_ptr_timing_reg[2]_6 (\\rd_ptr_timing_reg[2]_6 ),\n .\\rd_ptr_timing_reg[2]_7 (\\rd_ptr_timing_reg[2]_7 ),\n .\\rd_ptr_timing_reg[2]_8 (\\rd_ptr_timing_reg[2]_8 ),\n .\\rd_ptr_timing_reg[2]_9 (\\rd_ptr_timing_reg[2]_9 ),\n .req_bank_r(\\mc0/bank_mach0/req_bank_r ),\n .\\req_bank_r_lcl_reg[0] (u_ui_top_n_276),\n .\\req_bank_r_lcl_reg[0]_0 (u_ui_top_n_270),\n .\\req_bank_r_lcl_reg[2] (u_ui_top_n_274),\n .\\req_bank_r_lcl_reg[2]_0 (u_ui_top_n_275),\n .\\resume_wait_r_reg[5] (\\resume_wait_r_reg[5] ),\n .\\row_cnt_victim_rotate.complex_row_cnt_reg[4] (\\row_cnt_victim_rotate.complex_row_cnt_reg[4] ),\n .\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] (\\rst_ref_gen_1.rst_ref_sync_r_reg[1][14] ),\n .rst_sync_r1(rst_sync_r1),\n .rst_sync_r1_reg(rst_sync_r1_reg),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__10(rstdiv0_sync_r1_reg_rep__10),\n .rstdiv0_sync_r1_reg_rep__11(rstdiv0_sync_r1_reg_rep__11),\n .rstdiv0_sync_r1_reg_rep__12(rstdiv0_sync_r1_reg_rep__12),\n .rstdiv0_sync_r1_reg_rep__13(rstdiv0_sync_r1_reg_rep__13),\n .rstdiv0_sync_r1_reg_rep__14(rstdiv0_sync_r1_reg_rep__14),\n .rstdiv0_sync_r1_reg_rep__16(rstdiv0_sync_r1_reg_rep__16),\n .rstdiv0_sync_r1_reg_rep__17(rstdiv0_sync_r1_reg_rep__17),\n .rstdiv0_sync_r1_reg_rep__18(rstdiv0_sync_r1_reg_rep__18),\n .rstdiv0_sync_r1_reg_rep__19(rstdiv0_sync_r1_reg_rep__19),\n .rstdiv0_sync_r1_reg_rep__2(rstdiv0_sync_r1_reg_rep__2),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22),\n .rstdiv0_sync_r1_reg_rep__23(rstdiv0_sync_r1_reg_rep__23),\n .rstdiv0_sync_r1_reg_rep__24(rstdiv0_sync_r1_reg_rep__24),\n .rstdiv0_sync_r1_reg_rep__24_0(rstdiv0_sync_r1_reg_rep__24_0),\n .rstdiv0_sync_r1_reg_rep__24_1(rstdiv0_sync_r1_reg_rep__24_1),\n .rstdiv0_sync_r1_reg_rep__25(rstdiv0_sync_r1_reg_rep__25),\n .rstdiv0_sync_r1_reg_rep__26(rstdiv0_sync_r1_reg_rep__26),\n .rstdiv0_sync_r1_reg_rep__26_0(rstdiv0_sync_r1_reg_rep__26_0),\n .rstdiv0_sync_r1_reg_rep__26_1(rstdiv0_sync_r1_reg_rep__26_1),\n .rstdiv0_sync_r1_reg_rep__26_2(rstdiv0_sync_r1_reg_rep__26_2),\n .rstdiv0_sync_r1_reg_rep__4(rstdiv0_sync_r1_reg_rep__4),\n .rstdiv0_sync_r1_reg_rep__5(rstdiv0_sync_r1_reg_rep__5),\n .rstdiv0_sync_r1_reg_rep__6(rstdiv0_sync_r1_reg_rep__6),\n .rstdiv0_sync_r1_reg_rep__7(rstdiv0_sync_r1_reg_rep__7),\n .rstdiv0_sync_r1_reg_rep__8(rstdiv0_sync_r1_reg_rep__8),\n .rstdiv0_sync_r1_reg_rep__9(rstdiv0_sync_r1_reg_rep__9),\n .rtp_timer_ns1(rtp_timer_ns1),\n .rtp_timer_ns1_6(rtp_timer_ns1_6),\n .rtp_timer_ns1_7(rtp_timer_ns1_7),\n .samp_edge_cnt0_en_r(samp_edge_cnt0_en_r),\n .samp_edge_cnt0_en_r_reg(samp_edge_cnt0_en_r_reg),\n .\\samps_r_reg[9] (sm_r),\n .\\sm_r_reg[0] (\\sm_r_reg[0] ),\n .\\sm_r_reg[0]_0 (\\sm_r_reg[0]_0 ),\n .\\stg2_tap_cnt_reg[0] (\\stg2_tap_cnt_reg[0] ),\n .stg3_dec2init_val_r_reg(stg3_dec2init_val_r_reg),\n .stg3_inc2init_val_r_reg(stg3_inc2init_val_r_reg),\n .\\stg3_r_reg[0] (\\stg3_r_reg[0] ),\n .sync_pulse(sync_pulse),\n .sys_rst(sys_rst),\n .use_addr(use_addr),\n .wr_en(wr_en),\n .wr_en_5(wr_en_5),\n .wr_en_6(wr_en_6),\n .\\wr_ptr_timing_reg[2] (Q),\n .\\wr_ptr_timing_reg[2]_0 (\\wr_ptr_timing_reg[2] ),\n .\\wr_ptr_timing_reg[2]_1 (\\wr_ptr_timing_reg[2]_0 ),\n .\\write_buffer.wr_buf_out_data_reg[287] (wr_data_addr));\n (* syn_maxfan = \"10\" *) \n FDRE reset_reg\n (.C(CLK),\n .CE(1'b1),\n .D(rstdiv0_sync_r1_reg_rep__26),\n .Q(reset_reg_n_0),\n .R(1'b0));\n ddr3_if_mig_7series_v4_0_axi_mc u_axi_mc\n (.CLK(CLK),\n .D(\\axi_mc_w_channel_0/next_wdf_mask ),\n .E(\\ui_cmd0/app_addr_r10 ),\n .Q(app_rd_data),\n .\\app_addr_r1_reg[27] (app_addr),\n .app_en_ns1(\\ui_cmd0/app_en_ns1 ),\n .app_en_r1(\\ui_cmd0/app_en_r1 ),\n .app_rd_data_valid(app_rd_data_valid),\n .app_rdy(app_rdy),\n .app_wdf_data(app_wdf_data),\n .app_wdf_mask(app_wdf_mask),\n .app_wdf_rdy(app_wdf_rdy),\n .aresetn(aresetn),\n .mc_app_cmd(app_cmd),\n .mc_app_wdf_data_reg(\\axi_mc_w_channel_0/mc_app_wdf_data_reg ),\n .\\mc_app_wdf_data_reg_reg[255] (\\axi_mc_w_channel_0/next_wdf_data ),\n .mc_app_wdf_mask_reg(\\axi_mc_w_channel_0/mc_app_wdf_mask_reg ),\n .mc_app_wdf_wren_reg(\\axi_mc_w_channel_0/mc_app_wdf_wren_reg ),\n .mc_init_complete(init_calib_complete_r),\n .out(out),\n .reset_reg(reset_reg_n_0),\n .s_axi_araddr(s_axi_araddr),\n .s_axi_arburst(s_axi_arburst),\n .s_axi_arid(s_axi_arid),\n .s_axi_arlen(s_axi_arlen),\n .s_axi_arready(s_axi_arready),\n .s_axi_arvalid(s_axi_arvalid),\n .s_axi_awaddr(s_axi_awaddr),\n .s_axi_awburst(s_axi_awburst),\n .s_axi_awid(s_axi_awid),\n .s_axi_awlen(s_axi_awlen),\n .s_axi_awready(s_axi_awready),\n .s_axi_awvalid(s_axi_awvalid),\n .s_axi_bid(s_axi_bid),\n .s_axi_bready(s_axi_bready),\n .s_axi_bvalid(s_axi_bvalid),\n .s_axi_rid(s_axi_rid),\n .s_axi_rlast(s_axi_rlast),\n .s_axi_rready(s_axi_rready),\n .s_axi_rvalid(s_axi_rvalid),\n .s_axi_wdata(s_axi_wdata),\n .s_axi_wready(s_axi_wready),\n .s_axi_wstrb(s_axi_wstrb),\n .s_axi_wvalid(s_axi_wvalid),\n .w_cmd_rdy(w_cmd_rdy));\n ddr3_if_mig_7series_v4_0_ui_top u_ui_top\n (.CLK(CLK),\n .D(\\axi_mc_w_channel_0/next_wdf_mask ),\n .DIA({mem_intfc0_n_377,mem_intfc0_n_381}),\n .DIB({mem_intfc0_n_385,mem_intfc0_n_389}),\n .DIC({mem_intfc0_n_393,mem_intfc0_n_397}),\n .DOA(\\ui_rd_data0/p_129_out ),\n .DOB(\\ui_rd_data0/p_128_out ),\n .DOC(\\ui_rd_data0/p_127_out ),\n .E(wr_data_en),\n .Q({u_ui_top_n_1,ram_init_addr}),\n .accept_ns(accept_ns),\n .\\app_cmd_r2_reg[0] (u_ui_top_n_269),\n .\\app_cmd_r2_reg[1] (cmd),\n .app_en_ns1(\\ui_cmd0/app_en_ns1 ),\n .app_en_r1(\\ui_cmd0/app_en_r1 ),\n .app_hi_pri_r2(\\ui_cmd0/app_hi_pri_r2 ),\n .app_rd_data_end_ns(\\ui_rd_data0/app_rd_data_end_ns ),\n .app_rd_data_valid(app_rd_data_valid),\n .app_rdy(app_rdy),\n .app_rdy_r_reg(\\ui_cmd0/app_addr_r10 ),\n .app_wdf_data(app_wdf_data),\n .app_wdf_mask(app_wdf_mask),\n .app_wdf_rdy(app_wdf_rdy),\n .\\axaddr_incr_reg[29] (app_addr),\n .bypass__0(\\ui_rd_data0/bypass__0 ),\n .\\cmd_pipe_plus.wr_data_addr_reg[3] (wr_data_addr),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ({mem_intfc0_n_366,mem_intfc0_n_370}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ({mem_intfc0_n_305,mem_intfc0_n_309}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ({mem_intfc0_n_303,mem_intfc0_n_307}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ({mem_intfc0_n_304,mem_intfc0_n_308}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ({mem_intfc0_n_273,mem_intfc0_n_277}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ({mem_intfc0_n_271,mem_intfc0_n_275}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ({mem_intfc0_n_272,mem_intfc0_n_276}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ({mem_intfc0_n_241,mem_intfc0_n_245}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ({mem_intfc0_n_239,mem_intfc0_n_243}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ({mem_intfc0_n_240,mem_intfc0_n_244}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ({mem_intfc0_n_209,mem_intfc0_n_213}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ({mem_intfc0_n_207,mem_intfc0_n_211}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ({mem_intfc0_n_208,mem_intfc0_n_212}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ({mem_intfc0_n_177,mem_intfc0_n_181}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ({mem_intfc0_n_175,mem_intfc0_n_179}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ({mem_intfc0_n_176,mem_intfc0_n_180}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ({mem_intfc0_n_145,mem_intfc0_n_149}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ({mem_intfc0_n_143,mem_intfc0_n_147}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ({mem_intfc0_n_144,mem_intfc0_n_148}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ({mem_intfc0_n_374,mem_intfc0_n_378}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ({mem_intfc0_n_342,mem_intfc0_n_346}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ({mem_intfc0_n_310,mem_intfc0_n_314}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ({mem_intfc0_n_278,mem_intfc0_n_282}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ({mem_intfc0_n_334,mem_intfc0_n_338}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ({mem_intfc0_n_246,mem_intfc0_n_250}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ({mem_intfc0_n_214,mem_intfc0_n_218}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ({mem_intfc0_n_182,mem_intfc0_n_186}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ({mem_intfc0_n_150,mem_intfc0_n_154}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ({mem_intfc0_n_375,mem_intfc0_n_379}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ({mem_intfc0_n_376,mem_intfc0_n_380}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ({mem_intfc0_n_345,mem_intfc0_n_349}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ({mem_intfc0_n_343,mem_intfc0_n_347}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ({mem_intfc0_n_344,mem_intfc0_n_348}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ({mem_intfc0_n_313,mem_intfc0_n_317}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ({mem_intfc0_n_311,mem_intfc0_n_315}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ({mem_intfc0_n_312,mem_intfc0_n_316}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ({mem_intfc0_n_281,mem_intfc0_n_285}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ({mem_intfc0_n_279,mem_intfc0_n_283}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ({mem_intfc0_n_280,mem_intfc0_n_284}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ({mem_intfc0_n_249,mem_intfc0_n_253}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ({mem_intfc0_n_247,mem_intfc0_n_251}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ({mem_intfc0_n_248,mem_intfc0_n_252}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ({mem_intfc0_n_217,mem_intfc0_n_221}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ({mem_intfc0_n_215,mem_intfc0_n_219}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ({mem_intfc0_n_216,mem_intfc0_n_220}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ({mem_intfc0_n_302,mem_intfc0_n_306}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ({mem_intfc0_n_185,mem_intfc0_n_189}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ({mem_intfc0_n_183,mem_intfc0_n_187}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ({mem_intfc0_n_184,mem_intfc0_n_188}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ({mem_intfc0_n_153,mem_intfc0_n_157}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ({mem_intfc0_n_151,mem_intfc0_n_155}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ({mem_intfc0_n_152,mem_intfc0_n_156}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ({mem_intfc0_n_382,mem_intfc0_n_386}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ({mem_intfc0_n_350,mem_intfc0_n_354}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ({mem_intfc0_n_318,mem_intfc0_n_322}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ({mem_intfc0_n_286,mem_intfc0_n_290}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ({mem_intfc0_n_254,mem_intfc0_n_258}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ({mem_intfc0_n_222,mem_intfc0_n_226}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ({mem_intfc0_n_190,mem_intfc0_n_194}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ({mem_intfc0_n_158,mem_intfc0_n_162}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ({mem_intfc0_n_270,mem_intfc0_n_274}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ({mem_intfc0_n_383,mem_intfc0_n_387}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ({mem_intfc0_n_384,mem_intfc0_n_388}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ({mem_intfc0_n_353,mem_intfc0_n_357}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ({mem_intfc0_n_351,mem_intfc0_n_355}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ({mem_intfc0_n_352,mem_intfc0_n_356}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ({mem_intfc0_n_321,mem_intfc0_n_325}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ({mem_intfc0_n_319,mem_intfc0_n_323}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ({mem_intfc0_n_320,mem_intfc0_n_324}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ({mem_intfc0_n_289,mem_intfc0_n_293}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ({mem_intfc0_n_287,mem_intfc0_n_291}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ({mem_intfc0_n_288,mem_intfc0_n_292}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ({mem_intfc0_n_257,mem_intfc0_n_261}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ({mem_intfc0_n_255,mem_intfc0_n_259}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ({mem_intfc0_n_256,mem_intfc0_n_260}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ({mem_intfc0_n_225,mem_intfc0_n_229}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ({mem_intfc0_n_223,mem_intfc0_n_227}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ({mem_intfc0_n_224,mem_intfc0_n_228}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ({mem_intfc0_n_193,mem_intfc0_n_197}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ({mem_intfc0_n_191,mem_intfc0_n_195}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ({mem_intfc0_n_192,mem_intfc0_n_196}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ({mem_intfc0_n_161,mem_intfc0_n_165}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ({mem_intfc0_n_159,mem_intfc0_n_163}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ({mem_intfc0_n_160,mem_intfc0_n_164}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ({mem_intfc0_n_390,mem_intfc0_n_394}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ({mem_intfc0_n_358,mem_intfc0_n_362}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ({mem_intfc0_n_238,mem_intfc0_n_242}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ({mem_intfc0_n_326,mem_intfc0_n_330}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ({mem_intfc0_n_294,mem_intfc0_n_298}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ({mem_intfc0_n_262,mem_intfc0_n_266}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ({mem_intfc0_n_230,mem_intfc0_n_234}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ({mem_intfc0_n_198,mem_intfc0_n_202}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ({mem_intfc0_n_166,mem_intfc0_n_170}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ({mem_intfc0_n_391,mem_intfc0_n_395}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ({mem_intfc0_n_392,mem_intfc0_n_396}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ({mem_intfc0_n_361,mem_intfc0_n_365}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ({mem_intfc0_n_359,mem_intfc0_n_363}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ({mem_intfc0_n_360,mem_intfc0_n_364}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ({mem_intfc0_n_329,mem_intfc0_n_333}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ({mem_intfc0_n_327,mem_intfc0_n_331}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ({mem_intfc0_n_328,mem_intfc0_n_332}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ({mem_intfc0_n_297,mem_intfc0_n_301}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ({mem_intfc0_n_295,mem_intfc0_n_299}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ({mem_intfc0_n_296,mem_intfc0_n_300}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ({mem_intfc0_n_206,mem_intfc0_n_210}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ({mem_intfc0_n_265,mem_intfc0_n_269}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ({mem_intfc0_n_263,mem_intfc0_n_267}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ({mem_intfc0_n_264,mem_intfc0_n_268}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ({mem_intfc0_n_233,mem_intfc0_n_237}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ({mem_intfc0_n_231,mem_intfc0_n_235}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ({mem_intfc0_n_232,mem_intfc0_n_236}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ({mem_intfc0_n_201,mem_intfc0_n_205}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ({mem_intfc0_n_199,mem_intfc0_n_203}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ({mem_intfc0_n_200,mem_intfc0_n_204}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ({mem_intfc0_n_169,mem_intfc0_n_173}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ({mem_intfc0_n_167,mem_intfc0_n_171}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ({mem_intfc0_n_168,mem_intfc0_n_172}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ({mem_intfc0_n_174,mem_intfc0_n_178}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ({mem_intfc0_n_142,mem_intfc0_n_146}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 (app_rd_data_ns),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ({mem_intfc0_n_369,mem_intfc0_n_373}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ({mem_intfc0_n_367,mem_intfc0_n_371}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ({mem_intfc0_n_368,mem_intfc0_n_372}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ({mem_intfc0_n_337,mem_intfc0_n_341}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ({mem_intfc0_n_335,mem_intfc0_n_339}),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ({mem_intfc0_n_336,mem_intfc0_n_340}),\n .hi_priority(hi_priority),\n .mc_app_cmd(app_cmd),\n .mc_app_wdf_data_reg(\\axi_mc_w_channel_0/mc_app_wdf_data_reg ),\n .mc_app_wdf_mask_reg(\\axi_mc_w_channel_0/mc_app_wdf_mask_reg ),\n .mc_app_wdf_wren_reg(\\axi_mc_w_channel_0/mc_app_wdf_wren_reg ),\n .\\my_empty_reg[7] ({wr_data_mask,wr_data}),\n .\\not_strict_mode.app_rd_data_end_reg (\\ui_rd_data0/rd_status ),\n .\\not_strict_mode.app_rd_data_reg[101] (\\ui_rd_data0/p_80_out ),\n .\\not_strict_mode.app_rd_data_reg[103] (\\ui_rd_data0/p_75_out ),\n .\\not_strict_mode.app_rd_data_reg[105] (\\ui_rd_data0/p_76_out ),\n .\\not_strict_mode.app_rd_data_reg[107] (\\ui_rd_data0/p_77_out ),\n .\\not_strict_mode.app_rd_data_reg[109] (\\ui_rd_data0/p_72_out ),\n .\\not_strict_mode.app_rd_data_reg[111] (\\ui_rd_data0/p_73_out ),\n .\\not_strict_mode.app_rd_data_reg[113] (\\ui_rd_data0/p_74_out ),\n .\\not_strict_mode.app_rd_data_reg[115] (\\ui_rd_data0/p_69_out ),\n .\\not_strict_mode.app_rd_data_reg[117] (\\ui_rd_data0/p_70_out ),\n .\\not_strict_mode.app_rd_data_reg[119] (\\ui_rd_data0/p_71_out ),\n .\\not_strict_mode.app_rd_data_reg[11] (\\ui_rd_data0/p_125_out ),\n .\\not_strict_mode.app_rd_data_reg[121] (\\ui_rd_data0/p_66_out ),\n .\\not_strict_mode.app_rd_data_reg[123] (\\ui_rd_data0/p_67_out ),\n .\\not_strict_mode.app_rd_data_reg[125] (\\ui_rd_data0/p_68_out ),\n .\\not_strict_mode.app_rd_data_reg[127] (\\ui_rd_data0/p_63_out ),\n .\\not_strict_mode.app_rd_data_reg[129] (\\ui_rd_data0/p_64_out ),\n .\\not_strict_mode.app_rd_data_reg[131] (\\ui_rd_data0/p_65_out ),\n .\\not_strict_mode.app_rd_data_reg[133] (\\ui_rd_data0/p_60_out ),\n .\\not_strict_mode.app_rd_data_reg[135] (\\ui_rd_data0/p_61_out ),\n .\\not_strict_mode.app_rd_data_reg[137] (\\ui_rd_data0/p_62_out ),\n .\\not_strict_mode.app_rd_data_reg[139] (\\ui_rd_data0/p_57_out ),\n .\\not_strict_mode.app_rd_data_reg[13] (\\ui_rd_data0/p_120_out ),\n .\\not_strict_mode.app_rd_data_reg[141] (\\ui_rd_data0/p_58_out ),\n .\\not_strict_mode.app_rd_data_reg[143] (\\ui_rd_data0/p_59_out ),\n .\\not_strict_mode.app_rd_data_reg[145] (\\ui_rd_data0/p_54_out ),\n .\\not_strict_mode.app_rd_data_reg[147] (\\ui_rd_data0/p_55_out ),\n .\\not_strict_mode.app_rd_data_reg[149] (\\ui_rd_data0/p_56_out ),\n .\\not_strict_mode.app_rd_data_reg[151] (\\ui_rd_data0/p_51_out ),\n .\\not_strict_mode.app_rd_data_reg[153] (\\ui_rd_data0/p_52_out ),\n .\\not_strict_mode.app_rd_data_reg[155] (\\ui_rd_data0/p_53_out ),\n .\\not_strict_mode.app_rd_data_reg[157] (\\ui_rd_data0/p_48_out ),\n .\\not_strict_mode.app_rd_data_reg[159] (\\ui_rd_data0/p_49_out ),\n .\\not_strict_mode.app_rd_data_reg[15] (\\ui_rd_data0/p_121_out ),\n .\\not_strict_mode.app_rd_data_reg[161] (\\ui_rd_data0/p_50_out ),\n .\\not_strict_mode.app_rd_data_reg[163] (\\ui_rd_data0/p_45_out ),\n .\\not_strict_mode.app_rd_data_reg[165] (\\ui_rd_data0/p_46_out ),\n .\\not_strict_mode.app_rd_data_reg[167] (\\ui_rd_data0/p_47_out ),\n .\\not_strict_mode.app_rd_data_reg[169] (\\ui_rd_data0/p_42_out ),\n .\\not_strict_mode.app_rd_data_reg[171] (\\ui_rd_data0/p_43_out ),\n .\\not_strict_mode.app_rd_data_reg[173] (\\ui_rd_data0/p_44_out ),\n .\\not_strict_mode.app_rd_data_reg[175] (\\ui_rd_data0/p_39_out ),\n .\\not_strict_mode.app_rd_data_reg[177] (\\ui_rd_data0/p_40_out ),\n .\\not_strict_mode.app_rd_data_reg[179] (\\ui_rd_data0/p_41_out ),\n .\\not_strict_mode.app_rd_data_reg[17] (\\ui_rd_data0/p_122_out ),\n .\\not_strict_mode.app_rd_data_reg[181] (\\ui_rd_data0/p_36_out ),\n .\\not_strict_mode.app_rd_data_reg[183] (\\ui_rd_data0/p_37_out ),\n .\\not_strict_mode.app_rd_data_reg[185] (\\ui_rd_data0/p_38_out ),\n .\\not_strict_mode.app_rd_data_reg[187] (\\ui_rd_data0/p_33_out ),\n .\\not_strict_mode.app_rd_data_reg[189] (\\ui_rd_data0/p_34_out ),\n .\\not_strict_mode.app_rd_data_reg[191] (\\ui_rd_data0/p_35_out ),\n .\\not_strict_mode.app_rd_data_reg[193] (\\ui_rd_data0/p_30_out ),\n .\\not_strict_mode.app_rd_data_reg[195] (\\ui_rd_data0/p_31_out ),\n .\\not_strict_mode.app_rd_data_reg[197] (\\ui_rd_data0/p_32_out ),\n .\\not_strict_mode.app_rd_data_reg[199] (\\ui_rd_data0/p_27_out ),\n .\\not_strict_mode.app_rd_data_reg[19] (\\ui_rd_data0/p_117_out ),\n .\\not_strict_mode.app_rd_data_reg[201] (\\ui_rd_data0/p_28_out ),\n .\\not_strict_mode.app_rd_data_reg[203] (\\ui_rd_data0/p_29_out ),\n .\\not_strict_mode.app_rd_data_reg[205] (\\ui_rd_data0/p_24_out ),\n .\\not_strict_mode.app_rd_data_reg[207] (\\ui_rd_data0/p_25_out ),\n .\\not_strict_mode.app_rd_data_reg[209] (\\ui_rd_data0/p_26_out ),\n .\\not_strict_mode.app_rd_data_reg[211] (\\ui_rd_data0/p_21_out ),\n .\\not_strict_mode.app_rd_data_reg[213] (\\ui_rd_data0/p_22_out ),\n .\\not_strict_mode.app_rd_data_reg[215] (\\ui_rd_data0/p_23_out ),\n .\\not_strict_mode.app_rd_data_reg[217] (\\ui_rd_data0/p_18_out ),\n .\\not_strict_mode.app_rd_data_reg[219] (\\ui_rd_data0/p_19_out ),\n .\\not_strict_mode.app_rd_data_reg[21] (\\ui_rd_data0/p_118_out ),\n .\\not_strict_mode.app_rd_data_reg[221] (\\ui_rd_data0/p_20_out ),\n .\\not_strict_mode.app_rd_data_reg[223] (\\ui_rd_data0/p_15_out ),\n .\\not_strict_mode.app_rd_data_reg[225] (\\ui_rd_data0/p_16_out ),\n .\\not_strict_mode.app_rd_data_reg[227] (\\ui_rd_data0/p_17_out ),\n .\\not_strict_mode.app_rd_data_reg[229] (\\ui_rd_data0/p_12_out ),\n .\\not_strict_mode.app_rd_data_reg[231] (\\ui_rd_data0/p_13_out ),\n .\\not_strict_mode.app_rd_data_reg[233] (\\ui_rd_data0/p_14_out ),\n .\\not_strict_mode.app_rd_data_reg[235] (\\ui_rd_data0/p_9_out ),\n .\\not_strict_mode.app_rd_data_reg[237] (\\ui_rd_data0/p_10_out ),\n .\\not_strict_mode.app_rd_data_reg[239] (\\ui_rd_data0/p_11_out ),\n .\\not_strict_mode.app_rd_data_reg[23] (\\ui_rd_data0/p_119_out ),\n .\\not_strict_mode.app_rd_data_reg[241] (\\ui_rd_data0/p_6_out ),\n .\\not_strict_mode.app_rd_data_reg[243] (\\ui_rd_data0/p_7_out ),\n .\\not_strict_mode.app_rd_data_reg[245] (\\ui_rd_data0/p_8_out ),\n .\\not_strict_mode.app_rd_data_reg[247] (\\ui_rd_data0/p_3_out ),\n .\\not_strict_mode.app_rd_data_reg[249] (\\ui_rd_data0/p_4_out ),\n .\\not_strict_mode.app_rd_data_reg[251] (\\ui_rd_data0/p_5_out ),\n .\\not_strict_mode.app_rd_data_reg[253] ({u_ui_top_n_260,u_ui_top_n_261}),\n .\\not_strict_mode.app_rd_data_reg[255] (\\ui_rd_data0/p_1_out ),\n .\\not_strict_mode.app_rd_data_reg[25] (\\ui_rd_data0/p_114_out ),\n .\\not_strict_mode.app_rd_data_reg[27] (\\ui_rd_data0/p_115_out ),\n .\\not_strict_mode.app_rd_data_reg[29] (\\ui_rd_data0/p_116_out ),\n .\\not_strict_mode.app_rd_data_reg[31] (\\ui_rd_data0/p_111_out ),\n .\\not_strict_mode.app_rd_data_reg[33] (\\ui_rd_data0/p_112_out ),\n .\\not_strict_mode.app_rd_data_reg[35] (\\ui_rd_data0/p_113_out ),\n .\\not_strict_mode.app_rd_data_reg[37] (\\ui_rd_data0/p_108_out ),\n .\\not_strict_mode.app_rd_data_reg[39] (\\ui_rd_data0/p_109_out ),\n .\\not_strict_mode.app_rd_data_reg[41] (\\ui_rd_data0/p_110_out ),\n .\\not_strict_mode.app_rd_data_reg[43] (\\ui_rd_data0/p_105_out ),\n .\\not_strict_mode.app_rd_data_reg[45] (\\ui_rd_data0/p_106_out ),\n .\\not_strict_mode.app_rd_data_reg[47] (\\ui_rd_data0/p_107_out ),\n .\\not_strict_mode.app_rd_data_reg[49] (\\ui_rd_data0/p_102_out ),\n .\\not_strict_mode.app_rd_data_reg[51] (\\ui_rd_data0/p_103_out ),\n .\\not_strict_mode.app_rd_data_reg[53] (\\ui_rd_data0/p_104_out ),\n .\\not_strict_mode.app_rd_data_reg[55] (\\ui_rd_data0/p_99_out ),\n .\\not_strict_mode.app_rd_data_reg[57] (\\ui_rd_data0/p_100_out ),\n .\\not_strict_mode.app_rd_data_reg[59] (\\ui_rd_data0/p_101_out ),\n .\\not_strict_mode.app_rd_data_reg[61] (\\ui_rd_data0/p_96_out ),\n .\\not_strict_mode.app_rd_data_reg[63] (\\ui_rd_data0/p_97_out ),\n .\\not_strict_mode.app_rd_data_reg[65] (\\ui_rd_data0/p_98_out ),\n .\\not_strict_mode.app_rd_data_reg[67] (\\ui_rd_data0/p_93_out ),\n .\\not_strict_mode.app_rd_data_reg[69] (\\ui_rd_data0/p_94_out ),\n .\\not_strict_mode.app_rd_data_reg[71] (\\ui_rd_data0/p_95_out ),\n .\\not_strict_mode.app_rd_data_reg[73] (\\ui_rd_data0/p_90_out ),\n .\\not_strict_mode.app_rd_data_reg[75] (\\ui_rd_data0/p_91_out ),\n .\\not_strict_mode.app_rd_data_reg[77] (\\ui_rd_data0/p_92_out ),\n .\\not_strict_mode.app_rd_data_reg[79] (\\ui_rd_data0/p_87_out ),\n .\\not_strict_mode.app_rd_data_reg[7] (\\ui_rd_data0/p_123_out ),\n .\\not_strict_mode.app_rd_data_reg[81] (\\ui_rd_data0/p_88_out ),\n .\\not_strict_mode.app_rd_data_reg[83] (\\ui_rd_data0/p_89_out ),\n .\\not_strict_mode.app_rd_data_reg[85] (\\ui_rd_data0/p_84_out ),\n .\\not_strict_mode.app_rd_data_reg[87] (\\ui_rd_data0/p_85_out ),\n .\\not_strict_mode.app_rd_data_reg[89] (\\ui_rd_data0/p_86_out ),\n .\\not_strict_mode.app_rd_data_reg[91] (\\ui_rd_data0/p_81_out ),\n .\\not_strict_mode.app_rd_data_reg[93] (\\ui_rd_data0/p_82_out ),\n .\\not_strict_mode.app_rd_data_reg[95] (\\ui_rd_data0/p_83_out ),\n .\\not_strict_mode.app_rd_data_reg[97] (\\ui_rd_data0/p_78_out ),\n .\\not_strict_mode.app_rd_data_reg[99] (\\ui_rd_data0/p_79_out ),\n .\\not_strict_mode.app_rd_data_reg[9] (\\ui_rd_data0/p_124_out ),\n .pointer_we(\\ui_wr_data0/pointer_we ),\n .ram_init_done_r(ram_init_done_r),\n .rb_hit_busy_r_reg(u_ui_top_n_270),\n .rb_hit_busy_r_reg_0(u_ui_top_n_274),\n .rb_hit_busy_r_reg_1(u_ui_top_n_275),\n .rb_hit_busy_r_reg_2(u_ui_top_n_276),\n .rd_buf_we(\\ui_rd_data0/rd_buf_we ),\n .\\read_fifo.fifo_out_data_r_reg[7] ({rd_data_end,rd_data_addr,rd_data_offset}),\n .req_bank_r(\\mc0/bank_mach0/req_bank_r ),\n .\\req_bank_r_lcl_reg[2] (bank),\n .\\req_col_r_reg[9] (col),\n .\\req_data_buf_addr_r_reg[4] (data_buf_addr),\n .\\req_row_r_lcl_reg[14] (row),\n .reset_reg(reset_reg_n_0),\n .\\s_axi_rdata[255] (app_rd_data),\n .use_addr(use_addr),\n .w_cmd_rdy(w_cmd_rdy),\n .wready_reg_rep__1(\\axi_mc_w_channel_0/next_wdf_data ));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_poc_edge_store\n (Q,\n \\rise_trail_center_offset_r_reg[3] ,\n E,\n \\tap_r_reg[5] ,\n CLK,\n run_polarity_r_reg,\n D);\n output [5:0]Q;\n output [5:0]\\rise_trail_center_offset_r_reg[3] ;\n input [0:0]E;\n input [5:0]\\tap_r_reg[5] ;\n input CLK;\n input [0:0]run_polarity_r_reg;\n input [5:0]D;\n\n wire CLK;\n wire [5:0]D;\n wire [0:0]E;\n wire [5:0]Q;\n wire [5:0]\\rise_trail_center_offset_r_reg[3] ;\n wire [0:0]run_polarity_r_reg;\n wire [5:0]\\tap_r_reg[5] ;\n\n FDRE \\rise_lead_r_reg[0] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [0]),\n .Q(Q[0]),\n .R(1'b0));\n FDRE \\rise_lead_r_reg[1] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [1]),\n .Q(Q[1]),\n .R(1'b0));\n FDRE \\rise_lead_r_reg[2] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [2]),\n .Q(Q[2]),\n .R(1'b0));\n FDRE \\rise_lead_r_reg[3] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [3]),\n .Q(Q[3]),\n .R(1'b0));\n FDRE \\rise_lead_r_reg[4] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [4]),\n .Q(Q[4]),\n .R(1'b0));\n FDRE \\rise_lead_r_reg[5] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [5]),\n .Q(Q[5]),\n .R(1'b0));\n FDRE \\rise_trail_r_reg[0] \n (.C(CLK),\n .CE(run_polarity_r_reg),\n .D(D[0]),\n .Q(\\rise_trail_center_offset_r_reg[3] [0]),\n .R(1'b0));\n FDRE \\rise_trail_r_reg[1] \n (.C(CLK),\n .CE(run_polarity_r_reg),\n .D(D[1]),\n .Q(\\rise_trail_center_offset_r_reg[3] [1]),\n .R(1'b0));\n FDRE \\rise_trail_r_reg[2] \n (.C(CLK),\n .CE(run_polarity_r_reg),\n .D(D[2]),\n .Q(\\rise_trail_center_offset_r_reg[3] [2]),\n .R(1'b0));\n FDRE \\rise_trail_r_reg[3] \n (.C(CLK),\n .CE(run_polarity_r_reg),\n .D(D[3]),\n .Q(\\rise_trail_center_offset_r_reg[3] [3]),\n .R(1'b0));\n FDRE \\rise_trail_r_reg[4] \n (.C(CLK),\n .CE(run_polarity_r_reg),\n .D(D[4]),\n .Q(\\rise_trail_center_offset_r_reg[3] [4]),\n .R(1'b0));\n FDRE \\rise_trail_r_reg[5] \n (.C(CLK),\n .CE(run_polarity_r_reg),\n .D(D[5]),\n .Q(\\rise_trail_center_offset_r_reg[3] [5]),\n .R(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_poc_edge_store\" *) \nmodule ddr3_if_mig_7series_v4_0_poc_edge_store_10\n (trailing_edge00_in,\n D,\n \\center_diff_r_reg[1] ,\n \\mmcm_init_trail_reg[5] ,\n \\mmcm_init_lead_reg[5] ,\n \\center_diff_r_reg[5] ,\n \\center_diff_r_reg[3] ,\n \\center_diff_r_reg[0] ,\n \\center_diff_r_reg[0]_0 ,\n \\center_diff_r_reg[3]_0 ,\n \\center_diff_r_reg[5]_0 ,\n Q,\n \\tap_r_reg[5] ,\n S,\n DI,\n \\tap_r_reg[5]_0 ,\n O,\n \\rise_trail_r_reg[5]_0 ,\n \\rise_lead_r_reg[1]_0 ,\n \\rise_lead_r_reg[4]_0 ,\n \\rise_trail_r_reg[3]_0 ,\n \\rise_lead_r_reg[3]_0 ,\n use_noise_window,\n \\rise_lead_r_reg[4]_1 ,\n \\rise_lead_r_reg[5]_0 ,\n \\rise_trail_r_reg[5]_1 ,\n E,\n CLK,\n samps_zero_r_reg,\n \\tap_r_reg[4] );\n output [4:0]trailing_edge00_in;\n output [2:0]D;\n output \\center_diff_r_reg[1] ;\n output [5:0]\\mmcm_init_trail_reg[5] ;\n output [5:0]\\mmcm_init_lead_reg[5] ;\n output [0:0]\\center_diff_r_reg[5] ;\n output [3:0]\\center_diff_r_reg[3] ;\n output \\center_diff_r_reg[0] ;\n output \\center_diff_r_reg[0]_0 ;\n output [2:0]\\center_diff_r_reg[3]_0 ;\n output [0:0]\\center_diff_r_reg[5]_0 ;\n input [0:0]Q;\n input [5:0]\\tap_r_reg[5] ;\n input [3:0]S;\n input [0:0]DI;\n input [1:0]\\tap_r_reg[5]_0 ;\n input [2:0]O;\n input \\rise_trail_r_reg[5]_0 ;\n input \\rise_lead_r_reg[1]_0 ;\n input \\rise_lead_r_reg[4]_0 ;\n input [2:0]\\rise_trail_r_reg[3]_0 ;\n input [0:0]\\rise_lead_r_reg[3]_0 ;\n input use_noise_window;\n input \\rise_lead_r_reg[4]_1 ;\n input [0:0]\\rise_lead_r_reg[5]_0 ;\n input [0:0]\\rise_trail_r_reg[5]_1 ;\n input [0:0]E;\n input CLK;\n input [0:0]samps_zero_r_reg;\n input [5:0]\\tap_r_reg[4] ;\n\n wire CLK;\n wire [2:0]D;\n wire [0:0]DI;\n wire [0:0]E;\n wire [2:0]O;\n wire [0:0]Q;\n wire [3:0]S;\n wire \\center_diff_r[5]_i_13_n_0 ;\n wire \\center_diff_r_reg[0] ;\n wire \\center_diff_r_reg[0]_0 ;\n wire \\center_diff_r_reg[1] ;\n wire [3:0]\\center_diff_r_reg[3] ;\n wire [2:0]\\center_diff_r_reg[3]_0 ;\n wire [0:0]\\center_diff_r_reg[5] ;\n wire [0:0]\\center_diff_r_reg[5]_0 ;\n wire [5:0]\\mmcm_init_lead_reg[5] ;\n wire [5:0]\\mmcm_init_trail_reg[5] ;\n wire \\rise_lead_r_reg[1]_0 ;\n wire [0:0]\\rise_lead_r_reg[3]_0 ;\n wire \\rise_lead_r_reg[4]_0 ;\n wire \\rise_lead_r_reg[4]_1 ;\n wire [0:0]\\rise_lead_r_reg[5]_0 ;\n wire [2:0]\\rise_trail_r_reg[3]_0 ;\n wire \\rise_trail_r_reg[5]_0 ;\n wire [0:0]\\rise_trail_r_reg[5]_1 ;\n wire [0:0]samps_zero_r_reg;\n wire [5:0]\\tap_r_reg[4] ;\n wire [5:0]\\tap_r_reg[5] ;\n wire [1:0]\\tap_r_reg[5]_0 ;\n wire [4:0]trailing_edge00_in;\n wire \\trailing_edge0_inferred__0/i__carry__0_n_3 ;\n wire \\trailing_edge0_inferred__0/i__carry_n_0 ;\n wire \\trailing_edge0_inferred__0/i__carry_n_1 ;\n wire \\trailing_edge0_inferred__0/i__carry_n_2 ;\n wire \\trailing_edge0_inferred__0/i__carry_n_3 ;\n wire use_noise_window;\n wire [0:0]\\NLW_trailing_edge0_inferred__0/i__carry_O_UNCONNECTED ;\n wire [3:1]\\NLW_trailing_edge0_inferred__0/i__carry__0_CO_UNCONNECTED ;\n wire [3:2]\\NLW_trailing_edge0_inferred__0/i__carry__0_O_UNCONNECTED ;\n\n LUT6 #(\n .INIT(64'hFFBFBBBB00808888)) \n \\center_diff_r[1]_i_1 \n (.I0(O[0]),\n .I1(\\rise_trail_r_reg[5]_0 ),\n .I2(\\rise_lead_r_reg[1]_0 ),\n .I3(\\center_diff_r_reg[1] ),\n .I4(\\rise_lead_r_reg[4]_0 ),\n .I5(\\rise_trail_r_reg[3]_0 [0]),\n .O(D[0]));\n LUT6 #(\n .INIT(64'hFFBFBBBB00808888)) \n \\center_diff_r[2]_i_1 \n (.I0(O[1]),\n .I1(\\rise_trail_r_reg[5]_0 ),\n .I2(\\rise_lead_r_reg[1]_0 ),\n .I3(\\center_diff_r_reg[1] ),\n .I4(\\rise_lead_r_reg[4]_0 ),\n .I5(\\rise_trail_r_reg[3]_0 [1]),\n .O(D[1]));\n LUT6 #(\n .INIT(64'hFFBFBBBB00808888)) \n \\center_diff_r[3]_i_1 \n (.I0(O[2]),\n .I1(\\rise_trail_r_reg[5]_0 ),\n .I2(\\rise_lead_r_reg[1]_0 ),\n .I3(\\center_diff_r_reg[1] ),\n .I4(\\rise_lead_r_reg[4]_0 ),\n .I5(\\rise_trail_r_reg[3]_0 [2]),\n .O(D[2]));\n (* SOFT_HLUTNM = \"soft_lutpair443\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\center_diff_r[5]_i_10 \n (.I0(\\mmcm_init_trail_reg[5] [2]),\n .I1(use_noise_window),\n .I2(\\mmcm_init_lead_reg[5] [2]),\n .O(\\center_diff_r_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair443\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\center_diff_r[5]_i_13 \n (.I0(\\mmcm_init_trail_reg[5] [4]),\n .I1(use_noise_window),\n .I2(\\mmcm_init_lead_reg[5] [4]),\n .O(\\center_diff_r[5]_i_13_n_0 ));\n LUT6 #(\n .INIT(64'h4540FFFF45404540)) \n \\center_diff_r[5]_i_4 \n (.I0(\\rise_lead_r_reg[3]_0 ),\n .I1(\\mmcm_init_trail_reg[5] [3]),\n .I2(use_noise_window),\n .I3(\\mmcm_init_lead_reg[5] [3]),\n .I4(\\rise_lead_r_reg[4]_1 ),\n .I5(\\center_diff_r[5]_i_13_n_0 ),\n .O(\\center_diff_r_reg[1] ));\n LUT3 #(\n .INIT(8'hB8)) \n \\center_diff_r[5]_i_7 \n (.I0(\\mmcm_init_trail_reg[5] [1]),\n .I1(use_noise_window),\n .I2(\\mmcm_init_lead_reg[5] [1]),\n .O(\\center_diff_r_reg[0]_0 ));\n LUT3 #(\n .INIT(8'hB8)) \n mod_sub1_return0__0_carry__0_i_1\n (.I0(\\mmcm_init_trail_reg[5] [4]),\n .I1(use_noise_window),\n .I2(\\mmcm_init_lead_reg[5] [4]),\n .O(\\center_diff_r_reg[5]_0 ));\n LUT5 #(\n .INIT(32'hB8748B47)) \n mod_sub1_return0__0_carry__0_i_2\n (.I0(\\mmcm_init_trail_reg[5] [5]),\n .I1(use_noise_window),\n .I2(\\mmcm_init_lead_reg[5] [5]),\n .I3(\\rise_lead_r_reg[5]_0 ),\n .I4(\\rise_trail_r_reg[5]_1 ),\n .O(\\center_diff_r_reg[5] ));\n LUT3 #(\n .INIT(8'hB8)) \n mod_sub1_return0__0_carry_i_1\n (.I0(\\mmcm_init_trail_reg[5] [3]),\n .I1(use_noise_window),\n .I2(\\mmcm_init_lead_reg[5] [3]),\n .O(\\center_diff_r_reg[3] [3]));\n LUT3 #(\n .INIT(8'hB8)) \n mod_sub1_return0__0_carry_i_2\n (.I0(\\mmcm_init_trail_reg[5] [2]),\n .I1(use_noise_window),\n .I2(\\mmcm_init_lead_reg[5] [2]),\n .O(\\center_diff_r_reg[3] [2]));\n LUT3 #(\n .INIT(8'hB8)) \n mod_sub1_return0__0_carry_i_3\n (.I0(\\mmcm_init_trail_reg[5] [1]),\n .I1(use_noise_window),\n .I2(\\mmcm_init_lead_reg[5] [1]),\n .O(\\center_diff_r_reg[3] [1]));\n LUT3 #(\n .INIT(8'hB8)) \n mod_sub1_return0__0_carry_i_4\n (.I0(\\mmcm_init_trail_reg[5] [0]),\n .I1(use_noise_window),\n .I2(\\mmcm_init_lead_reg[5] [0]),\n .O(\\center_diff_r_reg[3] [0]));\n LUT3 #(\n .INIT(8'hB8)) \n mod_sub1_return0_carry_i_2\n (.I0(\\mmcm_init_trail_reg[5] [2]),\n .I1(use_noise_window),\n .I2(\\mmcm_init_lead_reg[5] [2]),\n .O(\\center_diff_r_reg[3]_0 [2]));\n LUT3 #(\n .INIT(8'hB8)) \n mod_sub1_return0_carry_i_3\n (.I0(\\mmcm_init_trail_reg[5] [1]),\n .I1(use_noise_window),\n .I2(\\mmcm_init_lead_reg[5] [1]),\n .O(\\center_diff_r_reg[3]_0 [1]));\n LUT3 #(\n .INIT(8'hB8)) \n mod_sub1_return0_carry_i_4\n (.I0(\\mmcm_init_trail_reg[5] [0]),\n .I1(use_noise_window),\n .I2(\\mmcm_init_lead_reg[5] [0]),\n .O(\\center_diff_r_reg[3]_0 [0]));\n FDRE \\rise_lead_r_reg[0] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [0]),\n .Q(\\mmcm_init_lead_reg[5] [0]),\n .R(1'b0));\n FDRE \\rise_lead_r_reg[1] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [1]),\n .Q(\\mmcm_init_lead_reg[5] [1]),\n .R(1'b0));\n FDRE \\rise_lead_r_reg[2] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [2]),\n .Q(\\mmcm_init_lead_reg[5] [2]),\n .R(1'b0));\n FDRE \\rise_lead_r_reg[3] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [3]),\n .Q(\\mmcm_init_lead_reg[5] [3]),\n .R(1'b0));\n FDRE \\rise_lead_r_reg[4] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [4]),\n .Q(\\mmcm_init_lead_reg[5] [4]),\n .R(1'b0));\n FDRE \\rise_lead_r_reg[5] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [5]),\n .Q(\\mmcm_init_lead_reg[5] [5]),\n .R(1'b0));\n FDRE \\rise_trail_r_reg[0] \n (.C(CLK),\n .CE(samps_zero_r_reg),\n .D(\\tap_r_reg[4] [0]),\n .Q(\\mmcm_init_trail_reg[5] [0]),\n .R(1'b0));\n FDRE \\rise_trail_r_reg[1] \n (.C(CLK),\n .CE(samps_zero_r_reg),\n .D(\\tap_r_reg[4] [1]),\n .Q(\\mmcm_init_trail_reg[5] [1]),\n .R(1'b0));\n FDRE \\rise_trail_r_reg[2] \n (.C(CLK),\n .CE(samps_zero_r_reg),\n .D(\\tap_r_reg[4] [2]),\n .Q(\\mmcm_init_trail_reg[5] [2]),\n .R(1'b0));\n FDRE \\rise_trail_r_reg[3] \n (.C(CLK),\n .CE(samps_zero_r_reg),\n .D(\\tap_r_reg[4] [3]),\n .Q(\\mmcm_init_trail_reg[5] [3]),\n .R(1'b0));\n FDRE \\rise_trail_r_reg[4] \n (.C(CLK),\n .CE(samps_zero_r_reg),\n .D(\\tap_r_reg[4] [4]),\n .Q(\\mmcm_init_trail_reg[5] [4]),\n .R(1'b0));\n FDRE \\rise_trail_r_reg[5] \n (.C(CLK),\n .CE(samps_zero_r_reg),\n .D(\\tap_r_reg[4] [5]),\n .Q(\\mmcm_init_trail_reg[5] [5]),\n .R(1'b0));\n CARRY4 \\trailing_edge0_inferred__0/i__carry \n (.CI(1'b0),\n .CO({\\trailing_edge0_inferred__0/i__carry_n_0 ,\\trailing_edge0_inferred__0/i__carry_n_1 ,\\trailing_edge0_inferred__0/i__carry_n_2 ,\\trailing_edge0_inferred__0/i__carry_n_3 }),\n .CYINIT(1'b1),\n .DI({Q,\\tap_r_reg[5] [2:0]}),\n .O({trailing_edge00_in[2:0],\\NLW_trailing_edge0_inferred__0/i__carry_O_UNCONNECTED [0]}),\n .S(S));\n CARRY4 \\trailing_edge0_inferred__0/i__carry__0 \n (.CI(\\trailing_edge0_inferred__0/i__carry_n_0 ),\n .CO({\\NLW_trailing_edge0_inferred__0/i__carry__0_CO_UNCONNECTED [3:1],\\trailing_edge0_inferred__0/i__carry__0_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,DI}),\n .O({\\NLW_trailing_edge0_inferred__0/i__carry__0_O_UNCONNECTED [3:2],trailing_edge00_in[4:3]}),\n .S({1'b0,1'b0,\\tap_r_reg[5]_0 }));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_poc_edge_store\" *) \nmodule ddr3_if_mig_7series_v4_0_poc_edge_store_9\n (DI,\n \\center_diff_r_reg[5] ,\n \\window_center_r_reg[6] ,\n \\window_center_r_reg[6]_0 ,\n S,\n D,\n \\center_diff_r_reg[0] ,\n \\center_diff_r_reg[0]_0 ,\n \\center_diff_r_reg[0]_1 ,\n \\center_diff_r_reg[5]_0 ,\n \\center_diff_r_reg[1] ,\n \\window_center_r_reg[6]_1 ,\n \\window_center_r_reg[3] ,\n \\window_center_r_reg[0] ,\n \\window_center_r_reg[6]_2 ,\n \\center_diff_r_reg[3] ,\n \\center_diff_r_reg[3]_0 ,\n Q,\n center0_return3,\n use_noise_window,\n \\rise_trail_r_reg[5]_0 ,\n \\rise_lead_r_reg[5]_0 ,\n O,\n \\rise_trail_r_reg[3]_0 ,\n \\rise_lead_r_reg[0]_0 ,\n \\rise_lead_r_reg[4]_0 ,\n \\rise_trail_r_reg[4]_0 ,\n \\rise_trail_r_reg[1]_0 ,\n \\rise_trail_r_reg[2]_0 ,\n E,\n \\tap_r_reg[5] ,\n CLK,\n samps_zero_r_reg,\n \\tap_r_reg[4] );\n output [1:0]DI;\n output [0:0]\\center_diff_r_reg[5] ;\n output [5:0]\\window_center_r_reg[6] ;\n output [5:0]\\window_center_r_reg[6]_0 ;\n output [0:0]S;\n output [2:0]D;\n output \\center_diff_r_reg[0] ;\n output \\center_diff_r_reg[0]_0 ;\n output \\center_diff_r_reg[0]_1 ;\n output [0:0]\\center_diff_r_reg[5]_0 ;\n output \\center_diff_r_reg[1] ;\n output [0:0]\\window_center_r_reg[6]_1 ;\n output [2:0]\\window_center_r_reg[3] ;\n output [2:0]\\window_center_r_reg[0] ;\n output [1:0]\\window_center_r_reg[6]_2 ;\n output [0:0]\\center_diff_r_reg[3] ;\n output [0:0]\\center_diff_r_reg[3]_0 ;\n input [1:0]Q;\n input [3:0]center0_return3;\n input use_noise_window;\n input [3:0]\\rise_trail_r_reg[5]_0 ;\n input [3:0]\\rise_lead_r_reg[5]_0 ;\n input [0:0]O;\n input \\rise_trail_r_reg[3]_0 ;\n input \\rise_lead_r_reg[0]_0 ;\n input [1:0]\\rise_lead_r_reg[4]_0 ;\n input [1:0]\\rise_trail_r_reg[4]_0 ;\n input \\rise_trail_r_reg[1]_0 ;\n input \\rise_trail_r_reg[2]_0 ;\n input [0:0]E;\n input [5:0]\\tap_r_reg[5] ;\n input CLK;\n input [0:0]samps_zero_r_reg;\n input [5:0]\\tap_r_reg[4] ;\n\n wire CLK;\n wire [2:0]D;\n wire [1:0]DI;\n wire [0:0]E;\n wire [0:0]O;\n wire [1:0]Q;\n wire [0:0]S;\n wire [3:0]center0_return3;\n wire \\center_diff_r[5]_i_11_n_0 ;\n wire \\center_diff_r[5]_i_6_n_0 ;\n wire \\center_diff_r[5]_i_8_n_0 ;\n wire \\center_diff_r[5]_i_9_n_0 ;\n wire \\center_diff_r_reg[0] ;\n wire \\center_diff_r_reg[0]_0 ;\n wire \\center_diff_r_reg[0]_1 ;\n wire \\center_diff_r_reg[1] ;\n wire [0:0]\\center_diff_r_reg[3] ;\n wire [0:0]\\center_diff_r_reg[3]_0 ;\n wire [0:0]\\center_diff_r_reg[5] ;\n wire [0:0]\\center_diff_r_reg[5]_0 ;\n wire mod_sub1_return0_carry__0_i_3_n_0;\n wire \\rise_lead_r_reg[0]_0 ;\n wire [1:0]\\rise_lead_r_reg[4]_0 ;\n wire [3:0]\\rise_lead_r_reg[5]_0 ;\n wire \\rise_trail_r_reg[1]_0 ;\n wire \\rise_trail_r_reg[2]_0 ;\n wire \\rise_trail_r_reg[3]_0 ;\n wire [1:0]\\rise_trail_r_reg[4]_0 ;\n wire [3:0]\\rise_trail_r_reg[5]_0 ;\n wire [0:0]samps_zero_r_reg;\n wire [5:0]\\tap_r_reg[4] ;\n wire [5:0]\\tap_r_reg[5] ;\n wire use_noise_window;\n wire [2:0]\\window_center_r_reg[0] ;\n wire [2:0]\\window_center_r_reg[3] ;\n wire [5:0]\\window_center_r_reg[6] ;\n wire [5:0]\\window_center_r_reg[6]_0 ;\n wire [0:0]\\window_center_r_reg[6]_1 ;\n wire [1:0]\\window_center_r_reg[6]_2 ;\n\n LUT5 #(\n .INIT(32'hAAAA8000)) \n center0_return1__0_carry__0_i_1\n (.I0(Q[0]),\n .I1(center0_return3[2]),\n .I2(center0_return3[1]),\n .I3(center0_return3[0]),\n .I4(center0_return3[3]),\n .O(DI[1]));\n LUT3 #(\n .INIT(8'hB8)) \n center0_return1__0_carry__0_i_2\n (.I0(\\window_center_r_reg[6] [3]),\n .I1(use_noise_window),\n .I2(\\window_center_r_reg[6]_0 [3]),\n .O(DI[0]));\n LUT6 #(\n .INIT(64'h5F5F3FC0A0A03FC0)) \n center0_return1__0_carry__0_i_3\n (.I0(\\window_center_r_reg[6] [4]),\n .I1(\\window_center_r_reg[6]_0 [4]),\n .I2(Q[1]),\n .I3(\\window_center_r_reg[6]_0 [5]),\n .I4(use_noise_window),\n .I5(\\window_center_r_reg[6] [5]),\n .O(S));\n LUT3 #(\n .INIT(8'hB8)) \n center0_return1__0_carry_i_1\n (.I0(\\window_center_r_reg[6] [2]),\n .I1(use_noise_window),\n .I2(\\window_center_r_reg[6]_0 [2]),\n .O(\\window_center_r_reg[3] [2]));\n LUT3 #(\n .INIT(8'hB8)) \n center0_return1__0_carry_i_2\n (.I0(\\window_center_r_reg[6] [1]),\n .I1(use_noise_window),\n .I2(\\window_center_r_reg[6]_0 [1]),\n .O(\\window_center_r_reg[3] [1]));\n LUT3 #(\n .INIT(8'hB8)) \n center0_return1__0_carry_i_3\n (.I0(\\window_center_r_reg[6] [0]),\n .I1(use_noise_window),\n .I2(\\window_center_r_reg[6]_0 [0]),\n .O(\\window_center_r_reg[3] [0]));\n LUT3 #(\n .INIT(8'hB8)) \n center0_return1__1_carry__0_i_1\n (.I0(\\window_center_r_reg[6] [4]),\n .I1(use_noise_window),\n .I2(\\window_center_r_reg[6]_0 [4]),\n .O(\\window_center_r_reg[6]_2 [1]));\n LUT3 #(\n .INIT(8'hB8)) \n center0_return1__1_carry__0_i_2\n (.I0(\\window_center_r_reg[6] [3]),\n .I1(use_noise_window),\n .I2(\\window_center_r_reg[6]_0 [3]),\n .O(\\window_center_r_reg[6]_2 [0]));\n LUT3 #(\n .INIT(8'hB8)) \n center0_return1__1_carry__0_i_3\n (.I0(\\window_center_r_reg[6] [5]),\n .I1(use_noise_window),\n .I2(\\window_center_r_reg[6]_0 [5]),\n .O(\\window_center_r_reg[6]_1 ));\n LUT3 #(\n .INIT(8'hB8)) \n center0_return1__1_carry_i_1\n (.I0(\\window_center_r_reg[6] [2]),\n .I1(use_noise_window),\n .I2(\\window_center_r_reg[6]_0 [2]),\n .O(\\window_center_r_reg[0] [2]));\n LUT3 #(\n .INIT(8'hB8)) \n center0_return1__1_carry_i_2\n (.I0(\\window_center_r_reg[6] [1]),\n .I1(use_noise_window),\n .I2(\\window_center_r_reg[6]_0 [1]),\n .O(\\window_center_r_reg[0] [1]));\n LUT3 #(\n .INIT(8'hB8)) \n center0_return1__1_carry_i_3\n (.I0(\\window_center_r_reg[6] [0]),\n .I1(use_noise_window),\n .I2(\\window_center_r_reg[6]_0 [0]),\n .O(\\window_center_r_reg[0] [0]));\n LUT6 #(\n .INIT(64'hFFBFBBBB00808888)) \n \\center_diff_r[0]_i_1 \n (.I0(O),\n .I1(\\center_diff_r_reg[0] ),\n .I2(\\center_diff_r_reg[0]_0 ),\n .I3(\\rise_trail_r_reg[3]_0 ),\n .I4(\\center_diff_r_reg[0]_1 ),\n .I5(\\rise_lead_r_reg[0]_0 ),\n .O(D[0]));\n LUT6 #(\n .INIT(64'hFFBFBBBB00808888)) \n \\center_diff_r[4]_i_1 \n (.I0(\\rise_lead_r_reg[4]_0 [0]),\n .I1(\\center_diff_r_reg[0] ),\n .I2(\\center_diff_r_reg[0]_0 ),\n .I3(\\rise_trail_r_reg[3]_0 ),\n .I4(\\center_diff_r_reg[0]_1 ),\n .I5(\\rise_trail_r_reg[4]_0 [0]),\n .O(D[1]));\n LUT6 #(\n .INIT(64'hFFBFBBBB00808888)) \n \\center_diff_r[5]_i_1 \n (.I0(\\rise_lead_r_reg[4]_0 [1]),\n .I1(\\center_diff_r_reg[0] ),\n .I2(\\center_diff_r_reg[0]_0 ),\n .I3(\\rise_trail_r_reg[3]_0 ),\n .I4(\\center_diff_r_reg[0]_1 ),\n .I5(\\rise_trail_r_reg[4]_0 [1]),\n .O(D[2]));\n LUT5 #(\n .INIT(32'h335ACC5A)) \n \\center_diff_r[5]_i_11 \n (.I0(\\window_center_r_reg[6]_0 [3]),\n .I1(\\window_center_r_reg[6] [3]),\n .I2(\\rise_lead_r_reg[5]_0 [1]),\n .I3(use_noise_window),\n .I4(\\rise_trail_r_reg[5]_0 [1]),\n .O(\\center_diff_r[5]_i_11_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair442\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\center_diff_r[5]_i_12 \n (.I0(\\window_center_r_reg[6] [4]),\n .I1(use_noise_window),\n .I2(\\window_center_r_reg[6]_0 [4]),\n .O(\\center_diff_r_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair441\" *) \n LUT5 #(\n .INIT(32'hCCAFFFAF)) \n \\center_diff_r[5]_i_2 \n (.I0(\\window_center_r_reg[6]_0 [5]),\n .I1(\\window_center_r_reg[6] [5]),\n .I2(\\rise_lead_r_reg[5]_0 [3]),\n .I3(use_noise_window),\n .I4(\\rise_trail_r_reg[5]_0 [3]),\n .O(\\center_diff_r_reg[0] ));\n LUT6 #(\n .INIT(64'hFFFFFFFFB200FFB2)) \n \\center_diff_r[5]_i_3 \n (.I0(\\center_diff_r[5]_i_6_n_0 ),\n .I1(\\rise_trail_r_reg[1]_0 ),\n .I2(\\center_diff_r[5]_i_8_n_0 ),\n .I3(\\center_diff_r[5]_i_9_n_0 ),\n .I4(\\rise_trail_r_reg[2]_0 ),\n .I5(\\center_diff_r[5]_i_11_n_0 ),\n .O(\\center_diff_r_reg[0]_0 ));\n LUT6 #(\n .INIT(64'h00000000FF77CF47)) \n \\center_diff_r[5]_i_5 \n (.I0(\\window_center_r_reg[6] [4]),\n .I1(use_noise_window),\n .I2(\\window_center_r_reg[6]_0 [4]),\n .I3(\\rise_trail_r_reg[5]_0 [2]),\n .I4(\\rise_lead_r_reg[5]_0 [2]),\n .I5(mod_sub1_return0_carry__0_i_3_n_0),\n .O(\\center_diff_r_reg[0]_1 ));\n LUT3 #(\n .INIT(8'hB8)) \n \\center_diff_r[5]_i_6 \n (.I0(\\window_center_r_reg[6] [1]),\n .I1(use_noise_window),\n .I2(\\window_center_r_reg[6]_0 [1]),\n .O(\\center_diff_r[5]_i_6_n_0 ));\n LUT5 #(\n .INIT(32'h000ACC0A)) \n \\center_diff_r[5]_i_8 \n (.I0(\\window_center_r_reg[6]_0 [0]),\n .I1(\\window_center_r_reg[6] [0]),\n .I2(\\rise_lead_r_reg[5]_0 [0]),\n .I3(use_noise_window),\n .I4(\\rise_trail_r_reg[5]_0 [0]),\n .O(\\center_diff_r[5]_i_8_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair442\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\center_diff_r[5]_i_9 \n (.I0(\\window_center_r_reg[6] [2]),\n .I1(use_noise_window),\n .I2(\\window_center_r_reg[6]_0 [2]),\n .O(\\center_diff_r[5]_i_9_n_0 ));\n LUT5 #(\n .INIT(32'h478B74B8)) \n mod_sub1_return0_carry__0_i_1\n (.I0(\\window_center_r_reg[6] [4]),\n .I1(use_noise_window),\n .I2(\\window_center_r_reg[6]_0 [4]),\n .I3(\\rise_trail_r_reg[5]_0 [2]),\n .I4(\\rise_lead_r_reg[5]_0 [2]),\n .O(\\center_diff_r_reg[5] ));\n LUT6 #(\n .INIT(64'h555595955A559A95)) \n mod_sub1_return0_carry__0_i_2\n (.I0(mod_sub1_return0_carry__0_i_3_n_0),\n .I1(\\window_center_r_reg[6] [4]),\n .I2(use_noise_window),\n .I3(\\window_center_r_reg[6]_0 [4]),\n .I4(\\rise_trail_r_reg[5]_0 [2]),\n .I5(\\rise_lead_r_reg[5]_0 [2]),\n .O(\\center_diff_r_reg[5]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair441\" *) \n LUT5 #(\n .INIT(32'h335ACC5A)) \n mod_sub1_return0_carry__0_i_3\n (.I0(\\window_center_r_reg[6]_0 [5]),\n .I1(\\window_center_r_reg[6] [5]),\n .I2(\\rise_lead_r_reg[5]_0 [3]),\n .I3(use_noise_window),\n .I4(\\rise_trail_r_reg[5]_0 [3]),\n .O(mod_sub1_return0_carry__0_i_3_n_0));\n LUT3 #(\n .INIT(8'hB8)) \n mod_sub1_return0_carry_i_1\n (.I0(\\window_center_r_reg[6] [3]),\n .I1(use_noise_window),\n .I2(\\window_center_r_reg[6]_0 [3]),\n .O(\\center_diff_r_reg[3]_0 ));\n LUT5 #(\n .INIT(32'h335ACC5A)) \n mod_sub1_return0_carry_i_5\n (.I0(\\window_center_r_reg[6]_0 [3]),\n .I1(\\window_center_r_reg[6] [3]),\n .I2(\\rise_lead_r_reg[5]_0 [1]),\n .I3(use_noise_window),\n .I4(\\rise_trail_r_reg[5]_0 [1]),\n .O(\\center_diff_r_reg[3] ));\n FDRE \\rise_lead_r_reg[0] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [0]),\n .Q(\\window_center_r_reg[6] [0]),\n .R(1'b0));\n FDRE \\rise_lead_r_reg[1] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [1]),\n .Q(\\window_center_r_reg[6] [1]),\n .R(1'b0));\n FDRE \\rise_lead_r_reg[2] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [2]),\n .Q(\\window_center_r_reg[6] [2]),\n .R(1'b0));\n FDRE \\rise_lead_r_reg[3] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [3]),\n .Q(\\window_center_r_reg[6] [3]),\n .R(1'b0));\n FDRE \\rise_lead_r_reg[4] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [4]),\n .Q(\\window_center_r_reg[6] [4]),\n .R(1'b0));\n FDRE \\rise_lead_r_reg[5] \n (.C(CLK),\n .CE(E),\n .D(\\tap_r_reg[5] [5]),\n .Q(\\window_center_r_reg[6] [5]),\n .R(1'b0));\n FDRE \\rise_trail_r_reg[0] \n (.C(CLK),\n .CE(samps_zero_r_reg),\n .D(\\tap_r_reg[4] [0]),\n .Q(\\window_center_r_reg[6]_0 [0]),\n .R(1'b0));\n FDRE \\rise_trail_r_reg[1] \n (.C(CLK),\n .CE(samps_zero_r_reg),\n .D(\\tap_r_reg[4] [1]),\n .Q(\\window_center_r_reg[6]_0 [1]),\n .R(1'b0));\n FDRE \\rise_trail_r_reg[2] \n (.C(CLK),\n .CE(samps_zero_r_reg),\n .D(\\tap_r_reg[4] [2]),\n .Q(\\window_center_r_reg[6]_0 [2]),\n .R(1'b0));\n FDRE \\rise_trail_r_reg[3] \n (.C(CLK),\n .CE(samps_zero_r_reg),\n .D(\\tap_r_reg[4] [3]),\n .Q(\\window_center_r_reg[6]_0 [3]),\n .R(1'b0));\n FDRE \\rise_trail_r_reg[4] \n (.C(CLK),\n .CE(samps_zero_r_reg),\n .D(\\tap_r_reg[4] [4]),\n .Q(\\window_center_r_reg[6]_0 [4]),\n .R(1'b0));\n FDRE \\rise_trail_r_reg[5] \n (.C(CLK),\n .CE(samps_zero_r_reg),\n .D(\\tap_r_reg[4] [5]),\n .Q(\\window_center_r_reg[6]_0 [5]),\n .R(1'b0));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_poc_meta\n (detect_done_r_reg,\n \\sm_r_reg[1] ,\n poc_backup_r_reg_0,\n run_polarity_held_r,\n Q,\n center_return3,\n \\edge_diff_r_reg[0]_0 ,\n center0_return3,\n O,\n \\center_diff_r_reg[5]_0 ,\n \\center_diff_r_reg[3]_0 ,\n \\center_diff_r_reg[5]_1 ,\n \\diff_r_reg[7]_0 ,\n \\diff_r_reg[7]_1 ,\n \\edge_center_r_reg[6]_0 ,\n \\prev_r_reg[0]_0 ,\n \\prev_r_reg[0]_1 ,\n \\prev_r_reg[2]_0 ,\n \\window_center_r_reg[6]_0 ,\n CLK,\n samps_zero_r_reg,\n samps_zero_r_reg_0,\n S,\n \\rise_lead_center_offset_r_reg[4]_0 ,\n \\rise_lead_center_offset_r_reg[2]_0 ,\n DI,\n \\edge_diff_r_reg[4]_0 ,\n \\rise_trail_center_offset_r_reg[2]_0 ,\n \\rise_lead_center_offset_r_reg[4]_1 ,\n \\rise_trail_center_offset_r_reg[3]_0 ,\n \\rise_trail_center_offset_r_reg[5]_0 ,\n \\rise_lead_r_reg[2] ,\n \\rise_trail_r_reg[2] ,\n \\rise_lead_r_reg[4] ,\n \\rise_lead_r_reg[5] ,\n \\rise_lead_r_reg[2]_0 ,\n \\rise_trail_r_reg[2]_0 ,\n \\center_diff_r_reg[4]_0 ,\n \\rise_lead_r_reg[4]_0 ,\n \\rise_lead_r_reg[3] ,\n \\rise_trail_r_reg[3] ,\n \\rise_lead_r_reg[4]_1 ,\n \\rise_lead_r_reg[4]_2 ,\n \\rise_trail_r_reg[3]_0 ,\n \\rise_lead_r_reg[3]_0 ,\n \\rise_trail_r_reg[4] ,\n \\rise_trail_r_reg[5] ,\n \\edge_center_r_reg[6]_1 ,\n \\window_center_r_reg[6]_1 ,\n \\edge_center_r_reg[3]_0 ,\n \\edge_center_r_reg[5]_0 ,\n \\window_center_r_reg[6]_2 ,\n \\edge_center_r_reg[0]_0 ,\n \\edge_center_r_reg[3]_1 ,\n \\edge_center_r_reg[6]_2 ,\n ocd_ktap_right_r_reg,\n ocd_ktap_left_r_reg,\n \\run_ends_r_reg[1]_0 ,\n rstdiv0_sync_r1_reg_rep__20,\n ocd_ktap_left_r_reg_0,\n ocd_edge_detect_rdy_r_reg,\n \\diff_r_reg[2]_0 ,\n run_too_small_r_reg,\n D,\n \\rise_lead_r_reg[3]_1 ,\n \\rise_trail_r_reg[3]_1 ,\n \\rise_trail_center_offset_r_reg[0]_0 );\n output detect_done_r_reg;\n output \\sm_r_reg[1] ;\n output poc_backup_r_reg_0;\n output run_polarity_held_r;\n output [5:0]Q;\n output [3:0]center_return3;\n output [5:0]\\edge_diff_r_reg[0]_0 ;\n output [3:0]center0_return3;\n output [3:0]O;\n output [1:0]\\center_diff_r_reg[5]_0 ;\n output [2:0]\\center_diff_r_reg[3]_0 ;\n output [1:0]\\center_diff_r_reg[5]_1 ;\n output [6:0]\\diff_r_reg[7]_0 ;\n output [6:0]\\diff_r_reg[7]_1 ;\n output [4:0]\\edge_center_r_reg[6]_0 ;\n output \\prev_r_reg[0]_0 ;\n output \\prev_r_reg[0]_1 ;\n output [2:0]\\prev_r_reg[2]_0 ;\n output [4:0]\\window_center_r_reg[6]_0 ;\n input CLK;\n input samps_zero_r_reg;\n input samps_zero_r_reg_0;\n input [2:0]S;\n input [1:0]\\rise_lead_center_offset_r_reg[4]_0 ;\n input [2:0]\\rise_lead_center_offset_r_reg[2]_0 ;\n input [0:0]DI;\n input [1:0]\\edge_diff_r_reg[4]_0 ;\n input [2:0]\\rise_trail_center_offset_r_reg[2]_0 ;\n input [1:0]\\rise_lead_center_offset_r_reg[4]_1 ;\n input [3:0]\\rise_trail_center_offset_r_reg[3]_0 ;\n input [1:0]\\rise_trail_center_offset_r_reg[5]_0 ;\n input [2:0]\\rise_lead_r_reg[2] ;\n input [2:0]\\rise_trail_r_reg[2] ;\n input [1:0]\\rise_lead_r_reg[4] ;\n input [2:0]\\rise_lead_r_reg[5] ;\n input [2:0]\\rise_lead_r_reg[2]_0 ;\n input [2:0]\\rise_trail_r_reg[2]_0 ;\n input [1:0]\\center_diff_r_reg[4]_0 ;\n input [2:0]\\rise_lead_r_reg[4]_0 ;\n input [3:0]\\rise_lead_r_reg[3] ;\n input [3:0]\\rise_trail_r_reg[3] ;\n input [0:0]\\rise_lead_r_reg[4]_1 ;\n input [1:0]\\rise_lead_r_reg[4]_2 ;\n input [3:0]\\rise_trail_r_reg[3]_0 ;\n input [3:0]\\rise_lead_r_reg[3]_0 ;\n input [0:0]\\rise_trail_r_reg[4] ;\n input [1:0]\\rise_trail_r_reg[5] ;\n input [3:0]\\edge_center_r_reg[6]_1 ;\n input [3:0]\\window_center_r_reg[6]_1 ;\n input [3:0]\\edge_center_r_reg[3]_0 ;\n input [1:0]\\edge_center_r_reg[5]_0 ;\n input [3:0]\\window_center_r_reg[6]_2 ;\n input [0:0]\\edge_center_r_reg[0]_0 ;\n input [3:0]\\edge_center_r_reg[3]_1 ;\n input [2:0]\\edge_center_r_reg[6]_2 ;\n input ocd_ktap_right_r_reg;\n input ocd_ktap_left_r_reg;\n input \\run_ends_r_reg[1]_0 ;\n input rstdiv0_sync_r1_reg_rep__20;\n input ocd_ktap_left_r_reg_0;\n input ocd_edge_detect_rdy_r_reg;\n input \\diff_r_reg[2]_0 ;\n input run_too_small_r_reg;\n input [5:0]D;\n input [5:0]\\rise_lead_r_reg[3]_1 ;\n input [5:0]\\rise_trail_r_reg[3]_1 ;\n input \\rise_trail_center_offset_r_reg[0]_0 ;\n\n wire CLK;\n wire [5:0]D;\n wire [0:0]DI;\n wire [3:0]O;\n wire [5:0]Q;\n wire [2:0]S;\n wire [6:0]center0_return0;\n wire center0_return1__0_carry__0_n_2;\n wire center0_return1__0_carry__0_n_3;\n wire center0_return1__0_carry_i_7_n_0;\n wire center0_return1__0_carry_n_0;\n wire center0_return1__0_carry_n_1;\n wire center0_return1__0_carry_n_2;\n wire center0_return1__0_carry_n_3;\n wire center0_return1__1_carry__0_n_2;\n wire center0_return1__1_carry__0_n_3;\n wire center0_return1__1_carry_i_7_n_0;\n wire center0_return1__1_carry_n_0;\n wire center0_return1__1_carry_n_1;\n wire center0_return1__1_carry_n_2;\n wire center0_return1__1_carry_n_3;\n wire [3:0]center0_return3;\n wire [2:0]\\center_diff_r_reg[3]_0 ;\n wire [1:0]\\center_diff_r_reg[4]_0 ;\n wire [1:0]\\center_diff_r_reg[5]_0 ;\n wire [1:0]\\center_diff_r_reg[5]_1 ;\n wire \\center_diff_r_reg_n_0_[0] ;\n wire [6:0]center_return0;\n wire center_return1__0_carry__0_i_1_n_0;\n wire center_return1__0_carry__0_n_2;\n wire center_return1__0_carry__0_n_3;\n wire center_return1__0_carry_i_4_n_0;\n wire center_return1__0_carry_n_0;\n wire center_return1__0_carry_n_1;\n wire center_return1__0_carry_n_2;\n wire center_return1__0_carry_n_3;\n wire center_return1__1_carry__0_i_1_n_0;\n wire center_return1__1_carry__0_n_2;\n wire center_return1__1_carry__0_n_3;\n wire center_return1__1_carry_i_4_n_0;\n wire center_return1__1_carry_n_0;\n wire center_return1__1_carry_n_1;\n wire center_return1__1_carry_n_2;\n wire center_return1__1_carry_n_3;\n wire [3:0]center_return3;\n wire detect_done_r_reg;\n wire [0:0]diff;\n wire [7:0]diff_ns;\n wire [7:0]diff_ns0;\n wire [6:1]diff_ns00_in;\n wire diff_ns0_carry__0_n_1;\n wire diff_ns0_carry__0_n_2;\n wire diff_ns0_carry__0_n_3;\n wire diff_ns0_carry_n_0;\n wire diff_ns0_carry_n_1;\n wire diff_ns0_carry_n_2;\n wire diff_ns0_carry_n_3;\n wire \\diff_ns0_inferred__0/i__carry__0_n_0 ;\n wire \\diff_ns0_inferred__0/i__carry__0_n_2 ;\n wire \\diff_ns0_inferred__0/i__carry__0_n_3 ;\n wire \\diff_ns0_inferred__0/i__carry_n_0 ;\n wire \\diff_ns0_inferred__0/i__carry_n_1 ;\n wire \\diff_ns0_inferred__0/i__carry_n_2 ;\n wire \\diff_ns0_inferred__0/i__carry_n_3 ;\n wire diff_ns1;\n wire diff_ns1_carry_n_1;\n wire diff_ns1_carry_n_2;\n wire diff_ns1_carry_n_3;\n wire \\diff_r_reg[2]_0 ;\n wire [6:0]\\diff_r_reg[7]_0 ;\n wire [6:0]\\diff_r_reg[7]_1 ;\n wire \\diff_r_reg_n_0_[3] ;\n wire \\diff_r_reg_n_0_[4] ;\n wire \\diff_r_reg_n_0_[5] ;\n wire \\diff_r_reg_n_0_[6] ;\n wire \\diff_r_reg_n_0_[7] ;\n wire diffs_eq_ns;\n wire diffs_eq_r;\n wire done_ns;\n wire edge_aligned_ns;\n wire edge_aligned_r_i_2_n_0;\n wire edge_aligned_r_i_3_n_0;\n wire [0:0]\\edge_center_r_reg[0]_0 ;\n wire [3:0]\\edge_center_r_reg[3]_0 ;\n wire [3:0]\\edge_center_r_reg[3]_1 ;\n wire [1:0]\\edge_center_r_reg[5]_0 ;\n wire [4:0]\\edge_center_r_reg[6]_0 ;\n wire [3:0]\\edge_center_r_reg[6]_1 ;\n wire [2:0]\\edge_center_r_reg[6]_2 ;\n wire \\edge_diff_r[5]_i_2_n_0 ;\n wire \\edge_diff_r[5]_i_3_n_0 ;\n wire [5:0]\\edge_diff_r_reg[0]_0 ;\n wire [1:0]\\edge_diff_r_reg[4]_0 ;\n wire mod_sub1_return0__0_carry__0_n_3;\n wire mod_sub1_return0__0_carry_n_0;\n wire mod_sub1_return0__0_carry_n_1;\n wire mod_sub1_return0__0_carry_n_2;\n wire mod_sub1_return0__0_carry_n_3;\n wire mod_sub1_return0_carry__0_n_3;\n wire mod_sub1_return0_carry_n_0;\n wire mod_sub1_return0_carry_n_1;\n wire mod_sub1_return0_carry_n_2;\n wire mod_sub1_return0_carry_n_3;\n wire [5:0]mod_sub_return;\n wire mod_sub_return0__0_carry__0_n_3;\n wire mod_sub_return0__0_carry__0_n_6;\n wire mod_sub_return0__0_carry__0_n_7;\n wire mod_sub_return0__0_carry_n_0;\n wire mod_sub_return0__0_carry_n_1;\n wire mod_sub_return0__0_carry_n_2;\n wire mod_sub_return0__0_carry_n_3;\n wire mod_sub_return0__0_carry_n_4;\n wire mod_sub_return0__0_carry_n_5;\n wire mod_sub_return0__0_carry_n_6;\n wire mod_sub_return0_carry__0_i_1_n_0;\n wire mod_sub_return0_carry__0_n_3;\n wire mod_sub_return0_carry__0_n_6;\n wire mod_sub_return0_carry__0_n_7;\n wire mod_sub_return0_carry_i_1_n_0;\n wire mod_sub_return0_carry_n_0;\n wire mod_sub_return0_carry_n_1;\n wire mod_sub_return0_carry_n_2;\n wire mod_sub_return0_carry_n_3;\n wire mod_sub_return0_carry_n_4;\n wire mod_sub_return0_carry_n_5;\n wire mod_sub_return0_carry_n_6;\n wire mod_sub_return0_carry_n_7;\n wire ocd_edge_detect_rdy_r_reg;\n wire ocd_ktap_left_r_reg;\n wire ocd_ktap_left_r_reg_0;\n wire ocd_ktap_right_r_reg;\n wire poc_backup_ns;\n wire poc_backup_ns0;\n wire poc_backup_ns0_carry_i_10_n_0;\n wire poc_backup_ns0_carry_i_11_n_0;\n wire poc_backup_ns0_carry_i_12_n_0;\n wire poc_backup_ns0_carry_i_13_n_0;\n wire poc_backup_ns0_carry_i_14_n_0;\n wire poc_backup_ns0_carry_i_15_n_0;\n wire poc_backup_ns0_carry_i_16_n_0;\n wire poc_backup_ns0_carry_i_1_n_0;\n wire poc_backup_ns0_carry_i_2_n_0;\n wire poc_backup_ns0_carry_i_3_n_0;\n wire poc_backup_ns0_carry_i_4_n_0;\n wire poc_backup_ns0_carry_i_5_n_0;\n wire poc_backup_ns0_carry_i_6_n_0;\n wire poc_backup_ns0_carry_i_7_n_0;\n wire poc_backup_ns0_carry_i_8_n_0;\n wire poc_backup_ns0_carry_i_9_n_0;\n wire poc_backup_ns0_carry_n_1;\n wire poc_backup_ns0_carry_n_2;\n wire poc_backup_ns0_carry_n_3;\n wire poc_backup_r_reg_0;\n wire [7:0]prev_r;\n wire \\prev_r_reg[0]_0 ;\n wire \\prev_r_reg[0]_1 ;\n wire [2:0]\\prev_r_reg[2]_0 ;\n wire reset_run_ends;\n wire [2:0]\\rise_lead_center_offset_r_reg[2]_0 ;\n wire [1:0]\\rise_lead_center_offset_r_reg[4]_0 ;\n wire [1:0]\\rise_lead_center_offset_r_reg[4]_1 ;\n wire [2:0]\\rise_lead_r_reg[2] ;\n wire [2:0]\\rise_lead_r_reg[2]_0 ;\n wire [3:0]\\rise_lead_r_reg[3] ;\n wire [3:0]\\rise_lead_r_reg[3]_0 ;\n wire [5:0]\\rise_lead_r_reg[3]_1 ;\n wire [1:0]\\rise_lead_r_reg[4] ;\n wire [2:0]\\rise_lead_r_reg[4]_0 ;\n wire [0:0]\\rise_lead_r_reg[4]_1 ;\n wire [1:0]\\rise_lead_r_reg[4]_2 ;\n wire [2:0]\\rise_lead_r_reg[5] ;\n wire \\rise_trail_center_offset_r_reg[0]_0 ;\n wire [2:0]\\rise_trail_center_offset_r_reg[2]_0 ;\n wire [3:0]\\rise_trail_center_offset_r_reg[3]_0 ;\n wire [1:0]\\rise_trail_center_offset_r_reg[5]_0 ;\n wire [2:0]\\rise_trail_r_reg[2] ;\n wire [2:0]\\rise_trail_r_reg[2]_0 ;\n wire [3:0]\\rise_trail_r_reg[3] ;\n wire [3:0]\\rise_trail_r_reg[3]_0 ;\n wire [5:0]\\rise_trail_r_reg[3]_1 ;\n wire [0:0]\\rise_trail_r_reg[4] ;\n wire [1:0]\\rise_trail_r_reg[5] ;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire run_end_r2_reg_srl3_n_0;\n wire run_end_r3;\n wire \\run_ends_r[0]_i_1_n_0 ;\n wire \\run_ends_r[1]_i_1_n_0 ;\n wire \\run_ends_r_reg[1]_0 ;\n wire run_polarity_held_r;\n wire run_too_small_r10;\n wire run_too_small_r2_reg_srl2_n_0;\n wire run_too_small_r3;\n wire run_too_small_r_reg;\n wire samps_zero_r_reg;\n wire samps_zero_r_reg_0;\n wire \\sm_r_reg[1] ;\n wire [4:0]\\window_center_r_reg[6]_0 ;\n wire [3:0]\\window_center_r_reg[6]_1 ;\n wire [3:0]\\window_center_r_reg[6]_2 ;\n wire [0:0]NLW_center0_return1__0_carry_O_UNCONNECTED;\n wire [3:2]NLW_center0_return1__0_carry__0_CO_UNCONNECTED;\n wire [3:3]NLW_center0_return1__0_carry__0_O_UNCONNECTED;\n wire [3:1]NLW_center0_return1__1_carry_O_UNCONNECTED;\n wire [2:2]NLW_center0_return1__1_carry__0_CO_UNCONNECTED;\n wire [3:3]NLW_center0_return1__1_carry__0_O_UNCONNECTED;\n wire [0:0]NLW_center_return1__0_carry_O_UNCONNECTED;\n wire [3:2]NLW_center_return1__0_carry__0_CO_UNCONNECTED;\n wire [3:3]NLW_center_return1__0_carry__0_O_UNCONNECTED;\n wire [3:1]NLW_center_return1__1_carry_O_UNCONNECTED;\n wire [2:2]NLW_center_return1__1_carry__0_CO_UNCONNECTED;\n wire [3:3]NLW_center_return1__1_carry__0_O_UNCONNECTED;\n wire [3:3]NLW_diff_ns0_carry__0_CO_UNCONNECTED;\n wire [0:0]\\NLW_diff_ns0_inferred__0/i__carry_O_UNCONNECTED ;\n wire [2:2]\\NLW_diff_ns0_inferred__0/i__carry__0_CO_UNCONNECTED ;\n wire [3:3]\\NLW_diff_ns0_inferred__0/i__carry__0_O_UNCONNECTED ;\n wire [3:0]NLW_diff_ns1_carry_O_UNCONNECTED;\n wire [0:0]NLW_mod_sub1_return0__0_carry_O_UNCONNECTED;\n wire [3:1]NLW_mod_sub1_return0__0_carry__0_CO_UNCONNECTED;\n wire [3:2]NLW_mod_sub1_return0__0_carry__0_O_UNCONNECTED;\n wire [3:1]NLW_mod_sub1_return0_carry__0_CO_UNCONNECTED;\n wire [3:2]NLW_mod_sub1_return0_carry__0_O_UNCONNECTED;\n wire [0:0]NLW_mod_sub_return0__0_carry_O_UNCONNECTED;\n wire [3:1]NLW_mod_sub_return0__0_carry__0_CO_UNCONNECTED;\n wire [3:2]NLW_mod_sub_return0__0_carry__0_O_UNCONNECTED;\n wire [3:1]NLW_mod_sub_return0_carry__0_CO_UNCONNECTED;\n wire [3:2]NLW_mod_sub_return0_carry__0_O_UNCONNECTED;\n wire [3:0]NLW_poc_backup_ns0_carry_O_UNCONNECTED;\n\n CARRY4 center0_return1__0_carry\n (.CI(1'b0),\n .CO({center0_return1__0_carry_n_0,center0_return1__0_carry_n_1,center0_return1__0_carry_n_2,center0_return1__0_carry_n_3}),\n .CYINIT(1'b0),\n .DI({\\rise_lead_r_reg[2]_0 ,1'b0}),\n .O({center0_return0[3:1],NLW_center0_return1__0_carry_O_UNCONNECTED[0]}),\n .S({\\rise_trail_r_reg[2]_0 ,center0_return1__0_carry_i_7_n_0}));\n CARRY4 center0_return1__0_carry__0\n (.CI(center0_return1__0_carry_n_0),\n .CO({NLW_center0_return1__0_carry__0_CO_UNCONNECTED[3:2],center0_return1__0_carry__0_n_2,center0_return1__0_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,\\center_diff_r_reg[4]_0 }),\n .O({NLW_center0_return1__0_carry__0_O_UNCONNECTED[3],center0_return0[6:4]}),\n .S({1'b0,\\rise_lead_r_reg[4]_0 }));\n LUT1 #(\n .INIT(2'h2)) \n center0_return1__0_carry_i_7\n (.I0(\\center_diff_r_reg_n_0_[0] ),\n .O(center0_return1__0_carry_i_7_n_0));\n CARRY4 center0_return1__1_carry\n (.CI(1'b0),\n .CO({center0_return1__1_carry_n_0,center0_return1__1_carry_n_1,center0_return1__1_carry_n_2,center0_return1__1_carry_n_3}),\n .CYINIT(1'b0),\n .DI({\\rise_lead_r_reg[2] ,1'b0}),\n .O({NLW_center0_return1__1_carry_O_UNCONNECTED[3:1],center0_return0[0]}),\n .S({\\rise_trail_r_reg[2] ,center0_return1__1_carry_i_7_n_0}));\n CARRY4 center0_return1__1_carry__0\n (.CI(center0_return1__1_carry_n_0),\n .CO({center0_return3[3],NLW_center0_return1__1_carry__0_CO_UNCONNECTED[2],center0_return1__1_carry__0_n_2,center0_return1__1_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,\\rise_lead_r_reg[4] }),\n .O({NLW_center0_return1__1_carry__0_O_UNCONNECTED[3],center0_return3[2:0]}),\n .S({1'b1,\\rise_lead_r_reg[5] }));\n LUT1 #(\n .INIT(2'h2)) \n center0_return1__1_carry_i_7\n (.I0(\\center_diff_r_reg_n_0_[0] ),\n .O(center0_return1__1_carry_i_7_n_0));\n FDRE \\center_diff_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(D[0]),\n .Q(\\center_diff_r_reg_n_0_[0] ),\n .R(1'b0));\n FDRE \\center_diff_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(D[1]),\n .Q(\\window_center_r_reg[6]_0 [0]),\n .R(1'b0));\n FDRE \\center_diff_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(D[2]),\n .Q(\\window_center_r_reg[6]_0 [1]),\n .R(1'b0));\n FDRE \\center_diff_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(D[3]),\n .Q(\\window_center_r_reg[6]_0 [2]),\n .R(1'b0));\n FDRE \\center_diff_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(D[4]),\n .Q(\\window_center_r_reg[6]_0 [3]),\n .R(1'b0));\n FDRE \\center_diff_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(D[5]),\n .Q(\\window_center_r_reg[6]_0 [4]),\n .R(1'b0));\n CARRY4 center_return1__0_carry\n (.CI(1'b0),\n .CO({center_return1__0_carry_n_0,center_return1__0_carry_n_1,center_return1__0_carry_n_2,center_return1__0_carry_n_3}),\n .CYINIT(1'b0),\n .DI({Q[2:0],1'b0}),\n .O({center_return0[3:1],NLW_center_return1__0_carry_O_UNCONNECTED[0]}),\n .S({\\rise_lead_center_offset_r_reg[2]_0 ,center_return1__0_carry_i_4_n_0}));\n CARRY4 center_return1__0_carry__0\n (.CI(center_return1__0_carry_n_0),\n .CO({NLW_center_return1__0_carry__0_CO_UNCONNECTED[3:2],center_return1__0_carry__0_n_2,center_return1__0_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,DI,Q[3]}),\n .O({NLW_center_return1__0_carry__0_O_UNCONNECTED[3],center_return0[6:4]}),\n .S({1'b0,center_return1__0_carry__0_i_1_n_0,\\edge_diff_r_reg[4]_0 }));\n LUT3 #(\n .INIT(8'h78)) \n center_return1__0_carry__0_i_1\n (.I0(Q[4]),\n .I1(\\edge_center_r_reg[6]_0 [4]),\n .I2(Q[5]),\n .O(center_return1__0_carry__0_i_1_n_0));\n LUT1 #(\n .INIT(2'h2)) \n center_return1__0_carry_i_4\n (.I0(diff),\n .O(center_return1__0_carry_i_4_n_0));\n CARRY4 center_return1__1_carry\n (.CI(1'b0),\n .CO({center_return1__1_carry_n_0,center_return1__1_carry_n_1,center_return1__1_carry_n_2,center_return1__1_carry_n_3}),\n .CYINIT(1'b0),\n .DI({Q[2:0],1'b0}),\n .O({NLW_center_return1__1_carry_O_UNCONNECTED[3:1],center_return0[0]}),\n .S({S,center_return1__1_carry_i_4_n_0}));\n CARRY4 center_return1__1_carry__0\n (.CI(center_return1__1_carry_n_0),\n .CO({center_return3[3],NLW_center_return1__1_carry__0_CO_UNCONNECTED[2],center_return1__1_carry__0_n_2,center_return1__1_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,Q[4:3]}),\n .O({NLW_center_return1__1_carry__0_O_UNCONNECTED[3],center_return3[2:0]}),\n .S({1'b1,center_return1__1_carry__0_i_1_n_0,\\rise_lead_center_offset_r_reg[4]_0 }));\n LUT1 #(\n .INIT(2'h2)) \n center_return1__1_carry__0_i_1\n (.I0(Q[5]),\n .O(center_return1__1_carry__0_i_1_n_0));\n LUT1 #(\n .INIT(2'h2)) \n center_return1__1_carry_i_4\n (.I0(diff),\n .O(center_return1__1_carry_i_4_n_0));\n CARRY4 diff_ns0_carry\n (.CI(1'b0),\n .CO({diff_ns0_carry_n_0,diff_ns0_carry_n_1,diff_ns0_carry_n_2,diff_ns0_carry_n_3}),\n .CYINIT(1'b1),\n .DI(\\diff_r_reg[7]_0 [3:0]),\n .O(diff_ns0[3:0]),\n .S(\\edge_center_r_reg[3]_0 ));\n CARRY4 diff_ns0_carry__0\n (.CI(diff_ns0_carry_n_0),\n .CO({NLW_diff_ns0_carry__0_CO_UNCONNECTED[3],diff_ns0_carry__0_n_1,diff_ns0_carry__0_n_2,diff_ns0_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,\\edge_center_r_reg[5]_0 ,\\diff_r_reg[7]_1 [4]}),\n .O(diff_ns0[7:4]),\n .S(\\window_center_r_reg[6]_2 ));\n CARRY4 \\diff_ns0_inferred__0/i__carry \n (.CI(1'b0),\n .CO({\\diff_ns0_inferred__0/i__carry_n_0 ,\\diff_ns0_inferred__0/i__carry_n_1 ,\\diff_ns0_inferred__0/i__carry_n_2 ,\\diff_ns0_inferred__0/i__carry_n_3 }),\n .CYINIT(1'b1),\n .DI(\\diff_r_reg[7]_0 [3:0]),\n .O({diff_ns00_in[3:1],\\NLW_diff_ns0_inferred__0/i__carry_O_UNCONNECTED [0]}),\n .S(\\edge_center_r_reg[3]_1 ));\n CARRY4 \\diff_ns0_inferred__0/i__carry__0 \n (.CI(\\diff_ns0_inferred__0/i__carry_n_0 ),\n .CO({\\diff_ns0_inferred__0/i__carry__0_n_0 ,\\NLW_diff_ns0_inferred__0/i__carry__0_CO_UNCONNECTED [2],\\diff_ns0_inferred__0/i__carry__0_n_2 ,\\diff_ns0_inferred__0/i__carry__0_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,\\diff_r_reg[7]_0 [6:4]}),\n .O({\\NLW_diff_ns0_inferred__0/i__carry__0_O_UNCONNECTED [3],diff_ns00_in[6:4]}),\n .S({1'b1,\\edge_center_r_reg[6]_2 }));\n CARRY4 diff_ns1_carry\n (.CI(1'b0),\n .CO({diff_ns1,diff_ns1_carry_n_1,diff_ns1_carry_n_2,diff_ns1_carry_n_3}),\n .CYINIT(1'b1),\n .DI(\\edge_center_r_reg[6]_1 ),\n .O(NLW_diff_ns1_carry_O_UNCONNECTED[3:0]),\n .S(\\window_center_r_reg[6]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair447\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\diff_r[0]_i_1 \n (.I0(\\edge_center_r_reg[0]_0 ),\n .I1(diff_ns0[0]),\n .I2(diff_ns1),\n .O(diff_ns[0]));\n (* SOFT_HLUTNM = \"soft_lutpair448\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\diff_r[1]_i_1 \n (.I0(diff_ns00_in[1]),\n .I1(diff_ns0[1]),\n .I2(diff_ns1),\n .O(diff_ns[1]));\n (* SOFT_HLUTNM = \"soft_lutpair446\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\diff_r[2]_i_1 \n (.I0(diff_ns00_in[2]),\n .I1(diff_ns0[2]),\n .I2(diff_ns1),\n .O(diff_ns[2]));\n (* SOFT_HLUTNM = \"soft_lutpair449\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\diff_r[3]_i_1 \n (.I0(diff_ns00_in[3]),\n .I1(diff_ns0[3]),\n .I2(diff_ns1),\n .O(diff_ns[3]));\n (* SOFT_HLUTNM = \"soft_lutpair449\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\diff_r[4]_i_1 \n (.I0(diff_ns00_in[4]),\n .I1(diff_ns0[4]),\n .I2(diff_ns1),\n .O(diff_ns[4]));\n (* SOFT_HLUTNM = \"soft_lutpair446\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\diff_r[5]_i_1 \n (.I0(diff_ns00_in[5]),\n .I1(diff_ns0[5]),\n .I2(diff_ns1),\n .O(diff_ns[5]));\n (* SOFT_HLUTNM = \"soft_lutpair448\" *) \n LUT3 #(\n .INIT(8'hAC)) \n \\diff_r[6]_i_1 \n (.I0(diff_ns00_in[6]),\n .I1(diff_ns0[6]),\n .I2(diff_ns1),\n .O(diff_ns[6]));\n (* SOFT_HLUTNM = \"soft_lutpair447\" *) \n LUT3 #(\n .INIT(8'h5C)) \n \\diff_r[7]_i_1 \n (.I0(\\diff_ns0_inferred__0/i__carry__0_n_0 ),\n .I1(diff_ns0[7]),\n .I2(diff_ns1),\n .O(diff_ns[7]));\n FDRE \\diff_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(diff_ns[0]),\n .Q(\\prev_r_reg[2]_0 [0]),\n .R(1'b0));\n FDRE \\diff_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(diff_ns[1]),\n .Q(\\prev_r_reg[2]_0 [1]),\n .R(1'b0));\n FDRE \\diff_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(diff_ns[2]),\n .Q(\\prev_r_reg[2]_0 [2]),\n .R(1'b0));\n FDRE \\diff_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(diff_ns[3]),\n .Q(\\diff_r_reg_n_0_[3] ),\n .R(1'b0));\n FDRE \\diff_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(diff_ns[4]),\n .Q(\\diff_r_reg_n_0_[4] ),\n .R(1'b0));\n FDRE \\diff_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(diff_ns[5]),\n .Q(\\diff_r_reg_n_0_[5] ),\n .R(1'b0));\n FDRE \\diff_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(diff_ns[6]),\n .Q(\\diff_r_reg_n_0_[6] ),\n .R(1'b0));\n FDRE \\diff_r_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(diff_ns[7]),\n .Q(\\diff_r_reg_n_0_[7] ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h000000000000BF80)) \n diffs_eq_r_i_1\n (.I0(edge_aligned_r_i_2_n_0),\n .I1(done_ns),\n .I2(detect_done_r_reg),\n .I3(diffs_eq_r),\n .I4(ocd_ktap_right_r_reg),\n .I5(ocd_ktap_left_r_reg),\n .O(diffs_eq_ns));\n FDRE diffs_eq_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(diffs_eq_ns),\n .Q(diffs_eq_r),\n .R(1'b0));\n LUT3 #(\n .INIT(8'h80)) \n done_r_i_1\n (.I0(ocd_edge_detect_rdy_r_reg),\n .I1(\\prev_r_reg[0]_0 ),\n .I2(\\prev_r_reg[0]_1 ),\n .O(done_ns));\n FDRE done_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(done_ns),\n .Q(detect_done_r_reg),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h000000F400000000)) \n edge_aligned_r_i_1\n (.I0(edge_aligned_r_i_2_n_0),\n .I1(diffs_eq_r),\n .I2(edge_aligned_r_i_3_n_0),\n .I3(rstdiv0_sync_r1_reg_rep__20),\n .I4(ocd_ktap_left_r_reg_0),\n .I5(done_ns),\n .O(edge_aligned_ns));\n LUT6 #(\n .INIT(64'h4000000055551555)) \n edge_aligned_r_i_2\n (.I0(\\diff_r_reg_n_0_[6] ),\n .I1(\\diff_r_reg_n_0_[5] ),\n .I2(\\diff_r_reg_n_0_[4] ),\n .I3(\\diff_r_reg_n_0_[3] ),\n .I4(\\diff_r_reg[2]_0 ),\n .I5(\\diff_r_reg_n_0_[7] ),\n .O(edge_aligned_r_i_2_n_0));\n LUT6 #(\n .INIT(64'h0000000000000004)) \n edge_aligned_r_i_3\n (.I0(\\diff_r_reg_n_0_[3] ),\n .I1(\\diff_r_reg[2]_0 ),\n .I2(\\diff_r_reg_n_0_[4] ),\n .I3(\\diff_r_reg_n_0_[5] ),\n .I4(\\diff_r_reg_n_0_[6] ),\n .I5(\\diff_r_reg_n_0_[7] ),\n .O(edge_aligned_r_i_3_n_0));\n FDRE edge_aligned_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(edge_aligned_ns),\n .Q(\\sm_r_reg[1] ),\n .R(1'b0));\n FDRE \\edge_center_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(center_return0[0]),\n .Q(\\diff_r_reg[7]_0 [0]),\n .R(1'b0));\n FDRE \\edge_center_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(center_return0[1]),\n .Q(\\diff_r_reg[7]_0 [1]),\n .R(1'b0));\n FDRE \\edge_center_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(center_return0[2]),\n .Q(\\diff_r_reg[7]_0 [2]),\n .R(1'b0));\n FDRE \\edge_center_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(center_return0[3]),\n .Q(\\diff_r_reg[7]_0 [3]),\n .R(1'b0));\n FDRE \\edge_center_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(center_return0[4]),\n .Q(\\diff_r_reg[7]_0 [4]),\n .R(1'b0));\n FDRE \\edge_center_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(center_return0[5]),\n .Q(\\diff_r_reg[7]_0 [5]),\n .R(1'b0));\n FDRE \\edge_center_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(center_return0[6]),\n .Q(\\diff_r_reg[7]_0 [6]),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hBAFB8A08)) \n \\edge_diff_r[0]_i_1 \n (.I0(\\rise_trail_center_offset_r_reg[0]_0 ),\n .I1(\\edge_diff_r[5]_i_2_n_0 ),\n .I2(Q[5]),\n .I3(\\edge_diff_r_reg[0]_0 [5]),\n .I4(mod_sub_return0_carry_n_7),\n .O(mod_sub_return[0]));\n LUT5 #(\n .INIT(32'hBAFB8A08)) \n \\edge_diff_r[1]_i_1 \n (.I0(mod_sub_return0__0_carry_n_6),\n .I1(\\edge_diff_r[5]_i_2_n_0 ),\n .I2(Q[5]),\n .I3(\\edge_diff_r_reg[0]_0 [5]),\n .I4(mod_sub_return0_carry_n_6),\n .O(mod_sub_return[1]));\n LUT5 #(\n .INIT(32'hBAFB8A08)) \n \\edge_diff_r[2]_i_1 \n (.I0(mod_sub_return0__0_carry_n_5),\n .I1(\\edge_diff_r[5]_i_2_n_0 ),\n .I2(Q[5]),\n .I3(\\edge_diff_r_reg[0]_0 [5]),\n .I4(mod_sub_return0_carry_n_5),\n .O(mod_sub_return[2]));\n LUT5 #(\n .INIT(32'hBAFB8A08)) \n \\edge_diff_r[3]_i_1 \n (.I0(mod_sub_return0__0_carry_n_4),\n .I1(\\edge_diff_r[5]_i_2_n_0 ),\n .I2(Q[5]),\n .I3(\\edge_diff_r_reg[0]_0 [5]),\n .I4(mod_sub_return0_carry_n_4),\n .O(mod_sub_return[3]));\n LUT5 #(\n .INIT(32'hBAFB8A08)) \n \\edge_diff_r[4]_i_1 \n (.I0(mod_sub_return0__0_carry__0_n_7),\n .I1(\\edge_diff_r[5]_i_2_n_0 ),\n .I2(Q[5]),\n .I3(\\edge_diff_r_reg[0]_0 [5]),\n .I4(mod_sub_return0_carry__0_n_7),\n .O(mod_sub_return[4]));\n LUT5 #(\n .INIT(32'hBAFB8A08)) \n \\edge_diff_r[5]_i_1 \n (.I0(mod_sub_return0__0_carry__0_n_6),\n .I1(\\edge_diff_r[5]_i_2_n_0 ),\n .I2(Q[5]),\n .I3(\\edge_diff_r_reg[0]_0 [5]),\n .I4(mod_sub_return0_carry__0_n_6),\n .O(mod_sub_return[5]));\n LUT5 #(\n .INIT(32'hB2FF00B2)) \n \\edge_diff_r[5]_i_2 \n (.I0(\\edge_diff_r[5]_i_3_n_0 ),\n .I1(Q[3]),\n .I2(\\edge_diff_r_reg[0]_0 [3]),\n .I3(Q[4]),\n .I4(\\edge_diff_r_reg[0]_0 [4]),\n .O(\\edge_diff_r[5]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hDF0DFFFF0000DF0D)) \n \\edge_diff_r[5]_i_3 \n (.I0(Q[0]),\n .I1(\\edge_diff_r_reg[0]_0 [0]),\n .I2(Q[1]),\n .I3(\\edge_diff_r_reg[0]_0 [1]),\n .I4(Q[2]),\n .I5(\\edge_diff_r_reg[0]_0 [2]),\n .O(\\edge_diff_r[5]_i_3_n_0 ));\n FDRE \\edge_diff_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(mod_sub_return[0]),\n .Q(diff),\n .R(1'b0));\n FDRE \\edge_diff_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(mod_sub_return[1]),\n .Q(\\edge_center_r_reg[6]_0 [0]),\n .R(1'b0));\n FDRE \\edge_diff_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(mod_sub_return[2]),\n .Q(\\edge_center_r_reg[6]_0 [1]),\n .R(1'b0));\n FDRE \\edge_diff_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(mod_sub_return[3]),\n .Q(\\edge_center_r_reg[6]_0 [2]),\n .R(1'b0));\n FDRE \\edge_diff_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(mod_sub_return[4]),\n .Q(\\edge_center_r_reg[6]_0 [3]),\n .R(1'b0));\n FDRE \\edge_diff_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(mod_sub_return[5]),\n .Q(\\edge_center_r_reg[6]_0 [4]),\n .R(1'b0));\n CARRY4 mod_sub1_return0__0_carry\n (.CI(1'b0),\n .CO({mod_sub1_return0__0_carry_n_0,mod_sub1_return0__0_carry_n_1,mod_sub1_return0__0_carry_n_2,mod_sub1_return0__0_carry_n_3}),\n .CYINIT(1'b1),\n .DI(\\rise_trail_r_reg[3]_0 ),\n .O({\\center_diff_r_reg[3]_0 ,NLW_mod_sub1_return0__0_carry_O_UNCONNECTED[0]}),\n .S(\\rise_lead_r_reg[3]_0 ));\n CARRY4 mod_sub1_return0__0_carry__0\n (.CI(mod_sub1_return0__0_carry_n_0),\n .CO({NLW_mod_sub1_return0__0_carry__0_CO_UNCONNECTED[3:1],mod_sub1_return0__0_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,\\rise_trail_r_reg[4] }),\n .O({NLW_mod_sub1_return0__0_carry__0_O_UNCONNECTED[3:2],\\center_diff_r_reg[5]_1 }),\n .S({1'b0,1'b0,\\rise_trail_r_reg[5] }));\n CARRY4 mod_sub1_return0_carry\n (.CI(1'b0),\n .CO({mod_sub1_return0_carry_n_0,mod_sub1_return0_carry_n_1,mod_sub1_return0_carry_n_2,mod_sub1_return0_carry_n_3}),\n .CYINIT(1'b1),\n .DI(\\rise_lead_r_reg[3] ),\n .O(O),\n .S(\\rise_trail_r_reg[3] ));\n CARRY4 mod_sub1_return0_carry__0\n (.CI(mod_sub1_return0_carry_n_0),\n .CO({NLW_mod_sub1_return0_carry__0_CO_UNCONNECTED[3:1],mod_sub1_return0_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,\\rise_lead_r_reg[4]_1 }),\n .O({NLW_mod_sub1_return0_carry__0_O_UNCONNECTED[3:2],\\center_diff_r_reg[5]_0 }),\n .S({1'b0,1'b0,\\rise_lead_r_reg[4]_2 }));\n CARRY4 mod_sub_return0__0_carry\n (.CI(1'b0),\n .CO({mod_sub_return0__0_carry_n_0,mod_sub_return0__0_carry_n_1,mod_sub_return0__0_carry_n_2,mod_sub_return0__0_carry_n_3}),\n .CYINIT(1'b1),\n .DI(\\edge_diff_r_reg[0]_0 [3:0]),\n .O({mod_sub_return0__0_carry_n_4,mod_sub_return0__0_carry_n_5,mod_sub_return0__0_carry_n_6,NLW_mod_sub_return0__0_carry_O_UNCONNECTED[0]}),\n .S(\\rise_trail_center_offset_r_reg[3]_0 ));\n CARRY4 mod_sub_return0__0_carry__0\n (.CI(mod_sub_return0__0_carry_n_0),\n .CO({NLW_mod_sub_return0__0_carry__0_CO_UNCONNECTED[3:1],mod_sub_return0__0_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,\\edge_diff_r_reg[0]_0 [4]}),\n .O({NLW_mod_sub_return0__0_carry__0_O_UNCONNECTED[3:2],mod_sub_return0__0_carry__0_n_6,mod_sub_return0__0_carry__0_n_7}),\n .S({1'b0,1'b0,\\rise_trail_center_offset_r_reg[5]_0 }));\n CARRY4 mod_sub_return0_carry\n (.CI(1'b0),\n .CO({mod_sub_return0_carry_n_0,mod_sub_return0_carry_n_1,mod_sub_return0_carry_n_2,mod_sub_return0_carry_n_3}),\n .CYINIT(1'b1),\n .DI({Q[3],\\edge_diff_r_reg[0]_0 [2:0]}),\n .O({mod_sub_return0_carry_n_4,mod_sub_return0_carry_n_5,mod_sub_return0_carry_n_6,mod_sub_return0_carry_n_7}),\n .S({mod_sub_return0_carry_i_1_n_0,\\rise_trail_center_offset_r_reg[2]_0 }));\n CARRY4 mod_sub_return0_carry__0\n (.CI(mod_sub_return0_carry_n_0),\n .CO({NLW_mod_sub_return0_carry__0_CO_UNCONNECTED[3:1],mod_sub_return0_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,mod_sub_return0_carry__0_i_1_n_0}),\n .O({NLW_mod_sub_return0_carry__0_O_UNCONNECTED[3:2],mod_sub_return0_carry__0_n_6,mod_sub_return0_carry__0_n_7}),\n .S({1'b0,1'b0,\\rise_lead_center_offset_r_reg[4]_1 }));\n LUT2 #(\n .INIT(4'h6)) \n mod_sub_return0_carry__0_i_1\n (.I0(Q[4]),\n .I1(\\edge_diff_r_reg[0]_0 [4]),\n .O(mod_sub_return0_carry__0_i_1_n_0));\n LUT2 #(\n .INIT(4'h6)) \n mod_sub_return0_carry_i_1\n (.I0(\\edge_diff_r_reg[0]_0 [3]),\n .I1(Q[3]),\n .O(mod_sub_return0_carry_i_1_n_0));\n CARRY4 poc_backup_ns0_carry\n (.CI(1'b0),\n .CO({poc_backup_ns0,poc_backup_ns0_carry_n_1,poc_backup_ns0_carry_n_2,poc_backup_ns0_carry_n_3}),\n .CYINIT(1'b0),\n .DI({poc_backup_ns0_carry_i_1_n_0,poc_backup_ns0_carry_i_2_n_0,poc_backup_ns0_carry_i_3_n_0,poc_backup_ns0_carry_i_4_n_0}),\n .O(NLW_poc_backup_ns0_carry_O_UNCONNECTED[3:0]),\n .S({poc_backup_ns0_carry_i_5_n_0,poc_backup_ns0_carry_i_6_n_0,poc_backup_ns0_carry_i_7_n_0,poc_backup_ns0_carry_i_8_n_0}));\n LUT6 #(\n .INIT(64'h154015407FD51540)) \n poc_backup_ns0_carry_i_1\n (.I0(prev_r[7]),\n .I1(\\diff_r_reg_n_0_[6] ),\n .I2(poc_backup_ns0_carry_i_9_n_0),\n .I3(\\diff_r_reg_n_0_[7] ),\n .I4(poc_backup_ns0_carry_i_10_n_0),\n .I5(prev_r[6]),\n .O(poc_backup_ns0_carry_i_1_n_0));\n LUT6 #(\n .INIT(64'hF00C0C0C580C0C0C)) \n poc_backup_ns0_carry_i_10\n (.I0(\\diff_r_reg[2]_0 ),\n .I1(\\diff_r_reg_n_0_[7] ),\n .I2(\\diff_r_reg_n_0_[6] ),\n .I3(\\diff_r_reg_n_0_[4] ),\n .I4(\\diff_r_reg_n_0_[5] ),\n .I5(\\diff_r_reg_n_0_[3] ),\n .O(poc_backup_ns0_carry_i_10_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair444\" *) \n LUT2 #(\n .INIT(4'h1)) \n poc_backup_ns0_carry_i_11\n (.I0(\\diff_r_reg_n_0_[6] ),\n .I1(\\diff_r_reg_n_0_[7] ),\n .O(poc_backup_ns0_carry_i_11_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair445\" *) \n LUT4 #(\n .INIT(16'h0001)) \n poc_backup_ns0_carry_i_12\n (.I0(\\prev_r_reg[2]_0 [1]),\n .I1(\\prev_r_reg[2]_0 [0]),\n .I2(\\prev_r_reg[2]_0 [2]),\n .I3(\\diff_r_reg_n_0_[3] ),\n .O(poc_backup_ns0_carry_i_12_n_0));\n LUT6 #(\n .INIT(64'h0FF00FF00FF00F8F)) \n poc_backup_ns0_carry_i_13\n (.I0(\\diff_r_reg_n_0_[4] ),\n .I1(\\diff_r_reg_n_0_[5] ),\n .I2(\\diff_r_reg_n_0_[3] ),\n .I3(\\diff_r_reg[2]_0 ),\n .I4(\\diff_r_reg_n_0_[6] ),\n .I5(\\diff_r_reg_n_0_[7] ),\n .O(poc_backup_ns0_carry_i_13_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair445\" *) \n LUT4 #(\n .INIT(16'h6663)) \n poc_backup_ns0_carry_i_14\n (.I0(poc_backup_ns0_carry_i_15_n_0),\n .I1(\\prev_r_reg[2]_0 [2]),\n .I2(\\prev_r_reg[2]_0 [0]),\n .I3(\\prev_r_reg[2]_0 [1]),\n .O(poc_backup_ns0_carry_i_14_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair444\" *) \n LUT5 #(\n .INIT(32'h01111111)) \n poc_backup_ns0_carry_i_15\n (.I0(\\diff_r_reg_n_0_[7] ),\n .I1(\\diff_r_reg_n_0_[6] ),\n .I2(\\diff_r_reg_n_0_[4] ),\n .I3(\\diff_r_reg_n_0_[5] ),\n .I4(\\diff_r_reg_n_0_[3] ),\n .O(poc_backup_ns0_carry_i_15_n_0));\n LUT6 #(\n .INIT(64'hA556A956A956A956)) \n poc_backup_ns0_carry_i_16\n (.I0(prev_r[3]),\n .I1(poc_backup_ns0_carry_i_11_n_0),\n .I2(\\diff_r_reg[2]_0 ),\n .I3(\\diff_r_reg_n_0_[3] ),\n .I4(\\diff_r_reg_n_0_[5] ),\n .I5(\\diff_r_reg_n_0_[4] ),\n .O(poc_backup_ns0_carry_i_16_n_0));\n LUT6 #(\n .INIT(64'h44541101C5F45351)) \n poc_backup_ns0_carry_i_2\n (.I0(prev_r[5]),\n .I1(poc_backup_ns0_carry_i_11_n_0),\n .I2(\\diff_r_reg_n_0_[4] ),\n .I3(poc_backup_ns0_carry_i_12_n_0),\n .I4(\\diff_r_reg_n_0_[5] ),\n .I5(prev_r[4]),\n .O(poc_backup_ns0_carry_i_2_n_0));\n LUT4 #(\n .INIT(16'h1117)) \n poc_backup_ns0_carry_i_3\n (.I0(prev_r[3]),\n .I1(poc_backup_ns0_carry_i_13_n_0),\n .I2(prev_r[2]),\n .I3(poc_backup_ns0_carry_i_14_n_0),\n .O(poc_backup_ns0_carry_i_3_n_0));\n LUT5 #(\n .INIT(32'h5014D45C)) \n poc_backup_ns0_carry_i_4\n (.I0(prev_r[1]),\n .I1(\\prev_r_reg[2]_0 [0]),\n .I2(\\prev_r_reg[2]_0 [1]),\n .I3(poc_backup_ns0_carry_i_15_n_0),\n .I4(prev_r[0]),\n .O(poc_backup_ns0_carry_i_4_n_0));\n LUT6 #(\n .INIT(64'h6A95000000006A95)) \n poc_backup_ns0_carry_i_5\n (.I0(\\diff_r_reg_n_0_[7] ),\n .I1(poc_backup_ns0_carry_i_9_n_0),\n .I2(\\diff_r_reg_n_0_[6] ),\n .I3(prev_r[7]),\n .I4(poc_backup_ns0_carry_i_10_n_0),\n .I5(prev_r[6]),\n .O(poc_backup_ns0_carry_i_5_n_0));\n LUT6 #(\n .INIT(64'h9006990006900096)) \n poc_backup_ns0_carry_i_6\n (.I0(\\diff_r_reg_n_0_[5] ),\n .I1(prev_r[5]),\n .I2(poc_backup_ns0_carry_i_11_n_0),\n .I3(\\diff_r_reg_n_0_[4] ),\n .I4(poc_backup_ns0_carry_i_12_n_0),\n .I5(prev_r[4]),\n .O(poc_backup_ns0_carry_i_6_n_0));\n LUT6 #(\n .INIT(64'h828282A02828280A)) \n poc_backup_ns0_carry_i_7\n (.I0(poc_backup_ns0_carry_i_16_n_0),\n .I1(poc_backup_ns0_carry_i_15_n_0),\n .I2(\\prev_r_reg[2]_0 [2]),\n .I3(\\prev_r_reg[2]_0 [0]),\n .I4(\\prev_r_reg[2]_0 [1]),\n .I5(prev_r[2]),\n .O(poc_backup_ns0_carry_i_7_n_0));\n LUT5 #(\n .INIT(32'h960000C3)) \n poc_backup_ns0_carry_i_8\n (.I0(poc_backup_ns0_carry_i_15_n_0),\n .I1(\\prev_r_reg[2]_0 [1]),\n .I2(prev_r[1]),\n .I3(\\prev_r_reg[2]_0 [0]),\n .I4(prev_r[0]),\n .O(poc_backup_ns0_carry_i_8_n_0));\n LUT6 #(\n .INIT(64'h8888888888888880)) \n poc_backup_ns0_carry_i_9\n (.I0(\\diff_r_reg_n_0_[5] ),\n .I1(\\diff_r_reg_n_0_[4] ),\n .I2(\\diff_r_reg_n_0_[3] ),\n .I3(\\prev_r_reg[2]_0 [2]),\n .I4(\\prev_r_reg[2]_0 [0]),\n .I5(\\prev_r_reg[2]_0 [1]),\n .O(poc_backup_ns0_carry_i_9_n_0));\n LUT5 #(\n .INIT(32'h20202220)) \n poc_backup_r_i_1\n (.I0(poc_backup_ns0),\n .I1(\\run_ends_r_reg[1]_0 ),\n .I2(edge_aligned_r_i_3_n_0),\n .I3(diffs_eq_r),\n .I4(edge_aligned_r_i_2_n_0),\n .O(poc_backup_ns));\n FDRE poc_backup_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(poc_backup_ns),\n .Q(poc_backup_r_reg_0),\n .R(1'b0));\n FDRE \\prev_r_reg[0] \n (.C(CLK),\n .CE(done_ns),\n .D(\\prev_r_reg[2]_0 [0]),\n .Q(prev_r[0]),\n .R(1'b0));\n FDRE \\prev_r_reg[1] \n (.C(CLK),\n .CE(done_ns),\n .D(\\prev_r_reg[2]_0 [1]),\n .Q(prev_r[1]),\n .R(1'b0));\n FDRE \\prev_r_reg[2] \n (.C(CLK),\n .CE(done_ns),\n .D(\\prev_r_reg[2]_0 [2]),\n .Q(prev_r[2]),\n .R(1'b0));\n FDRE \\prev_r_reg[3] \n (.C(CLK),\n .CE(done_ns),\n .D(\\diff_r_reg_n_0_[3] ),\n .Q(prev_r[3]),\n .R(1'b0));\n FDRE \\prev_r_reg[4] \n (.C(CLK),\n .CE(done_ns),\n .D(\\diff_r_reg_n_0_[4] ),\n .Q(prev_r[4]),\n .R(1'b0));\n FDRE \\prev_r_reg[5] \n (.C(CLK),\n .CE(done_ns),\n .D(\\diff_r_reg_n_0_[5] ),\n .Q(prev_r[5]),\n .R(1'b0));\n FDRE \\prev_r_reg[6] \n (.C(CLK),\n .CE(done_ns),\n .D(\\diff_r_reg_n_0_[6] ),\n .Q(prev_r[6]),\n .R(1'b0));\n FDRE \\prev_r_reg[7] \n (.C(CLK),\n .CE(done_ns),\n .D(\\diff_r_reg_n_0_[7] ),\n .Q(prev_r[7]),\n .R(1'b0));\n FDRE \\rise_lead_center_offset_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rise_lead_r_reg[3]_1 [0]),\n .Q(Q[0]),\n .R(1'b0));\n FDRE \\rise_lead_center_offset_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rise_lead_r_reg[3]_1 [1]),\n .Q(Q[1]),\n .R(1'b0));\n FDRE \\rise_lead_center_offset_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rise_lead_r_reg[3]_1 [2]),\n .Q(Q[2]),\n .R(1'b0));\n FDRE \\rise_lead_center_offset_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rise_lead_r_reg[3]_1 [3]),\n .Q(Q[3]),\n .R(1'b0));\n FDRE \\rise_lead_center_offset_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rise_lead_r_reg[3]_1 [4]),\n .Q(Q[4]),\n .R(1'b0));\n FDRE \\rise_lead_center_offset_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rise_lead_r_reg[3]_1 [5]),\n .Q(Q[5]),\n .R(1'b0));\n FDRE \\rise_trail_center_offset_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rise_trail_r_reg[3]_1 [0]),\n .Q(\\edge_diff_r_reg[0]_0 [0]),\n .R(1'b0));\n FDRE \\rise_trail_center_offset_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rise_trail_r_reg[3]_1 [1]),\n .Q(\\edge_diff_r_reg[0]_0 [1]),\n .R(1'b0));\n FDRE \\rise_trail_center_offset_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rise_trail_r_reg[3]_1 [2]),\n .Q(\\edge_diff_r_reg[0]_0 [2]),\n .R(1'b0));\n FDRE \\rise_trail_center_offset_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rise_trail_r_reg[3]_1 [3]),\n .Q(\\edge_diff_r_reg[0]_0 [3]),\n .R(1'b0));\n FDRE \\rise_trail_center_offset_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rise_trail_r_reg[3]_1 [4]),\n .Q(\\edge_diff_r_reg[0]_0 [4]),\n .R(1'b0));\n FDRE \\rise_trail_center_offset_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\rise_trail_r_reg[3]_1 [5]),\n .Q(\\edge_diff_r_reg[0]_0 [5]),\n .R(1'b0));\n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_poc/u_poc_meta/run_end_r2_reg_srl3 \" *) \n SRL16E run_end_r2_reg_srl3\n (.A0(1'b0),\n .A1(1'b1),\n .A2(1'b0),\n .A3(1'b0),\n .CE(1'b1),\n .CLK(CLK),\n .D(samps_zero_r_reg_0),\n .Q(run_end_r2_reg_srl3_n_0));\n FDRE run_end_r3_reg\n (.C(CLK),\n .CE(1'b1),\n .D(run_end_r2_reg_srl3_n_0),\n .Q(run_end_r3),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h0000DACA)) \n \\run_ends_r[0]_i_1 \n (.I0(\\prev_r_reg[0]_0 ),\n .I1(\\prev_r_reg[0]_1 ),\n .I2(run_end_r3),\n .I3(run_polarity_held_r),\n .I4(reset_run_ends),\n .O(\\run_ends_r[0]_i_1_n_0 ));\n LUT3 #(\n .INIT(8'hFB)) \n \\run_ends_r[0]_i_2 \n (.I0(run_too_small_r3),\n .I1(ocd_edge_detect_rdy_r_reg),\n .I2(rstdiv0_sync_r1_reg_rep__20),\n .O(reset_run_ends));\n LUT6 #(\n .INIT(64'h0000000000EC0000)) \n \\run_ends_r[1]_i_1 \n (.I0(\\prev_r_reg[0]_0 ),\n .I1(\\prev_r_reg[0]_1 ),\n .I2(run_end_r3),\n .I3(rstdiv0_sync_r1_reg_rep__20),\n .I4(ocd_edge_detect_rdy_r_reg),\n .I5(run_too_small_r3),\n .O(\\run_ends_r[1]_i_1_n_0 ));\n FDRE \\run_ends_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\run_ends_r[0]_i_1_n_0 ),\n .Q(\\prev_r_reg[0]_0 ),\n .R(1'b0));\n FDRE \\run_ends_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\run_ends_r[1]_i_1_n_0 ),\n .Q(\\prev_r_reg[0]_1 ),\n .R(1'b0));\n FDRE run_polarity_held_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(samps_zero_r_reg),\n .Q(run_polarity_held_r),\n .R(1'b0));\n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_poc/u_poc_meta/run_too_small_r2_reg_srl2 \" *) \n SRL16E run_too_small_r2_reg_srl2\n (.A0(1'b1),\n .A1(1'b0),\n .A2(1'b0),\n .A3(1'b0),\n .CE(1'b1),\n .CLK(CLK),\n .D(run_too_small_r10),\n .Q(run_too_small_r2_reg_srl2_n_0));\n LUT3 #(\n .INIT(8'h08)) \n run_too_small_r2_reg_srl2_i_1\n (.I0(run_too_small_r_reg),\n .I1(\\prev_r_reg[0]_0 ),\n .I2(\\prev_r_reg[0]_1 ),\n .O(run_too_small_r10));\n FDRE run_too_small_r3_reg\n (.C(CLK),\n .CE(1'b1),\n .D(run_too_small_r2_reg_srl2_n_0),\n .Q(run_too_small_r3),\n .R(1'b0));\n FDRE \\window_center_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(center0_return0[0]),\n .Q(\\diff_r_reg[7]_1 [0]),\n .R(1'b0));\n FDRE \\window_center_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(center0_return0[1]),\n .Q(\\diff_r_reg[7]_1 [1]),\n .R(1'b0));\n FDRE \\window_center_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(center0_return0[2]),\n .Q(\\diff_r_reg[7]_1 [2]),\n .R(1'b0));\n FDRE \\window_center_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(center0_return0[3]),\n .Q(\\diff_r_reg[7]_1 [3]),\n .R(1'b0));\n FDRE \\window_center_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(center0_return0[4]),\n .Q(\\diff_r_reg[7]_1 [4]),\n .R(1'b0));\n FDRE \\window_center_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(center0_return0[5]),\n .Q(\\diff_r_reg[7]_1 [5]),\n .R(1'b0));\n FDRE \\window_center_r_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(center0_return0[6]),\n .Q(\\diff_r_reg[7]_1 [6]),\n .R(1'b0));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_poc_pd\n (pd_out_pre,\n mmcm_ps_clk,\n in_dqs_lpbk_to_iddr_0,\n rst_sync_r1,\n CLK);\n output [0:0]pd_out_pre;\n input mmcm_ps_clk;\n input in_dqs_lpbk_to_iddr_0;\n input rst_sync_r1;\n input CLK;\n\n wire CLK;\n wire in_dqs_lpbk_to_iddr_0;\n wire mmcm_ps_clk;\n wire [0:0]pd_out_pre;\n wire pos_edge_samp;\n wire q1;\n wire rst_sync_r1;\n wire NLW_u_phase_detector_Q2_UNCONNECTED;\n\n FDRE \\no_eXes.pos_edge_samp_reg \n (.C(CLK),\n .CE(1'b1),\n .D(q1),\n .Q(pos_edge_samp),\n .R(1'b0));\n FDRE pd_out_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(pos_edge_samp),\n .Q(pd_out_pre),\n .R(1'b0));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* __SRVAL = \"FALSE\" *) \n IDDR #(\n .DDR_CLK_EDGE(\"OPPOSITE_EDGE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .IS_C_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .SRTYPE(\"SYNC\")) \n u_phase_detector\n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(in_dqs_lpbk_to_iddr_0),\n .Q1(q1),\n .Q2(NLW_u_phase_detector_Q2_UNCONNECTED),\n .R(rst_sync_r1),\n .S(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_poc_pd\" *) \nmodule ddr3_if_mig_7series_v4_0_poc_pd_3\n (pd_out_pre,\n mmcm_ps_clk,\n in_dqs_lpbk_to_iddr_1,\n rst_sync_r1,\n CLK);\n output [0:0]pd_out_pre;\n input mmcm_ps_clk;\n input in_dqs_lpbk_to_iddr_1;\n input rst_sync_r1;\n input CLK;\n\n wire CLK;\n wire in_dqs_lpbk_to_iddr_1;\n wire mmcm_ps_clk;\n wire \\no_eXes.pos_edge_samp_reg_n_0 ;\n wire [0:0]pd_out_pre;\n wire q1;\n wire rst_sync_r1;\n wire NLW_u_phase_detector_Q2_UNCONNECTED;\n\n FDRE \\no_eXes.pos_edge_samp_reg \n (.C(CLK),\n .CE(1'b1),\n .D(q1),\n .Q(\\no_eXes.pos_edge_samp_reg_n_0 ),\n .R(1'b0));\n FDRE pd_out_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\no_eXes.pos_edge_samp_reg_n_0 ),\n .Q(pd_out_pre),\n .R(1'b0));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* __SRVAL = \"FALSE\" *) \n IDDR #(\n .DDR_CLK_EDGE(\"OPPOSITE_EDGE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .IS_C_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .SRTYPE(\"SYNC\")) \n u_phase_detector\n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(in_dqs_lpbk_to_iddr_1),\n .Q1(q1),\n .Q2(NLW_u_phase_detector_Q2_UNCONNECTED),\n .R(rst_sync_r1),\n .S(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_poc_pd\" *) \nmodule ddr3_if_mig_7series_v4_0_poc_pd_4\n (pd_out_pre,\n mmcm_ps_clk,\n in_dqs_lpbk_to_iddr_2,\n rst_sync_r1,\n CLK);\n output [0:0]pd_out_pre;\n input mmcm_ps_clk;\n input in_dqs_lpbk_to_iddr_2;\n input rst_sync_r1;\n input CLK;\n\n wire CLK;\n wire in_dqs_lpbk_to_iddr_2;\n wire mmcm_ps_clk;\n wire \\no_eXes.pos_edge_samp_reg_n_0 ;\n wire [0:0]pd_out_pre;\n wire q1;\n wire rst_sync_r1;\n wire NLW_u_phase_detector_Q2_UNCONNECTED;\n\n FDRE \\no_eXes.pos_edge_samp_reg \n (.C(CLK),\n .CE(1'b1),\n .D(q1),\n .Q(\\no_eXes.pos_edge_samp_reg_n_0 ),\n .R(1'b0));\n FDRE pd_out_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\no_eXes.pos_edge_samp_reg_n_0 ),\n .Q(pd_out_pre),\n .R(1'b0));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* __SRVAL = \"FALSE\" *) \n IDDR #(\n .DDR_CLK_EDGE(\"OPPOSITE_EDGE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .IS_C_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .SRTYPE(\"SYNC\")) \n u_phase_detector\n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(in_dqs_lpbk_to_iddr_2),\n .Q1(q1),\n .Q2(NLW_u_phase_detector_Q2_UNCONNECTED),\n .R(rst_sync_r1),\n .S(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_poc_pd\" *) \nmodule ddr3_if_mig_7series_v4_0_poc_pd_5\n (pd_out,\n mmcm_ps_clk,\n in_dqs_lpbk_to_iddr_3,\n rst_sync_r1,\n CLK,\n pd_out_r_reg_0,\n \\gen_byte_sel_div1.byte_sel_cnt_reg[1] );\n output pd_out;\n input mmcm_ps_clk;\n input in_dqs_lpbk_to_iddr_3;\n input rst_sync_r1;\n input CLK;\n input [2:0]pd_out_r_reg_0;\n input [1:0]\\gen_byte_sel_div1.byte_sel_cnt_reg[1] ;\n\n wire CLK;\n wire [1:0]\\gen_byte_sel_div1.byte_sel_cnt_reg[1] ;\n wire in_dqs_lpbk_to_iddr_3;\n wire mmcm_ps_clk;\n wire \\no_eXes.pos_edge_samp_reg_n_0 ;\n wire pd_out;\n wire [3:3]pd_out_pre;\n wire [2:0]pd_out_r_reg_0;\n wire q1;\n wire rst_sync_r1;\n wire NLW_u_phase_detector_Q2_UNCONNECTED;\n\n FDRE \\no_eXes.pos_edge_samp_reg \n (.C(CLK),\n .CE(1'b1),\n .D(q1),\n .Q(\\no_eXes.pos_edge_samp_reg_n_0 ),\n .R(1'b0));\n FDRE pd_out_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\no_eXes.pos_edge_samp_reg_n_0 ),\n .Q(pd_out_pre),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hAFA0CFCFAFA0C0C0)) \n \\samps_hi_r[3]_i_7 \n (.I0(pd_out_pre),\n .I1(pd_out_r_reg_0[2]),\n .I2(\\gen_byte_sel_div1.byte_sel_cnt_reg[1] [1]),\n .I3(pd_out_r_reg_0[1]),\n .I4(\\gen_byte_sel_div1.byte_sel_cnt_reg[1] [0]),\n .I5(pd_out_r_reg_0[0]),\n .O(pd_out));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* __SRVAL = \"FALSE\" *) \n IDDR #(\n .DDR_CLK_EDGE(\"OPPOSITE_EDGE\"),\n .INIT_Q1(1'b0),\n .INIT_Q2(1'b0),\n .IS_C_INVERTED(1'b0),\n .IS_D_INVERTED(1'b0),\n .SRTYPE(\"SYNC\")) \n u_phase_detector\n (.C(mmcm_ps_clk),\n .CE(1'b1),\n .D(in_dqs_lpbk_to_iddr_3),\n .Q1(q1),\n .Q2(NLW_u_phase_detector_Q2_UNCONNECTED),\n .R(rst_sync_r1),\n .S(1'b0));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_poc_tap_base\n (\\run_r_reg[0]_0 ,\n run_too_small_r3_reg,\n \\run_r_reg[0]_1 ,\n \\run_r_reg[0]_2 ,\n Q,\n S,\n \\samp_cntr_r_reg[8]_0 ,\n \\samp_cntr_r_reg[12]_0 ,\n \\samp_cntr_r_reg[16]_0 ,\n \\samps_hi_r_reg[3]_0 ,\n \\samps_hi_r_reg[7]_0 ,\n \\samps_hi_r_reg[11]_0 ,\n \\samps_hi_r_reg[15]_0 ,\n \\samps_hi_r_reg[17]_0 ,\n samps_zero_r_reg_0,\n \\tap_r_reg[0]_0 ,\n \\run_r_reg[4]_0 ,\n run_too_small_r_reg_0,\n \\rise_trail_r_reg[0] ,\n \\sm_r_reg[0]_0 ,\n \\sm_r_reg[0]_1 ,\n \\qcntr_r_reg[0] ,\n \\rise_lead_r_reg[5] ,\n DI,\n samps_zero_r_reg_1,\n samps_zero_r_reg_2,\n samps_zero_r_reg_3,\n samps_zero_r_reg_4,\n samps_zero_r_reg_5,\n \\samp_cntr_r_reg[0]_0 ,\n \\rise_trail_r_reg[5] ,\n \\rise_trail_r_reg[5]_0 ,\n \\rise_trail_r_reg[5]_1 ,\n \\rise_trail_r_reg[3] ,\n \\samp_wait_r_reg[6]_0 ,\n \\samp_wait_r_reg[7]_0 ,\n \\rise_trail_r_reg[5]_2 ,\n \\rise_trail_r_reg[5]_3 ,\n CLK,\n samps_lo,\n rstdiv0_sync_r1_reg_rep__20,\n \\run_r_reg[2]_0 ,\n ocd_ktap_left_r_reg,\n ocd_ktap_right_r_reg,\n trailing_edge0,\n trailing_edge00_in,\n poc_sample_pd,\n \\samp_wait_r_reg[4]_0 ,\n samp_cntr_ns0,\n samps_hi_ns0,\n psdone,\n rstdiv0_sync_r1_reg_rep,\n D,\n rstdiv0_sync_r1_reg_rep__0,\n E);\n output \\run_r_reg[0]_0 ;\n output run_too_small_r3_reg;\n output \\run_r_reg[0]_1 ;\n output \\run_r_reg[0]_2 ;\n output [4:0]Q;\n output [3:0]S;\n output [3:0]\\samp_cntr_r_reg[8]_0 ;\n output [3:0]\\samp_cntr_r_reg[12]_0 ;\n output [3:0]\\samp_cntr_r_reg[16]_0 ;\n output [2:0]\\samps_hi_r_reg[3]_0 ;\n output [3:0]\\samps_hi_r_reg[7]_0 ;\n output [3:0]\\samps_hi_r_reg[11]_0 ;\n output [3:0]\\samps_hi_r_reg[15]_0 ;\n output [1:0]\\samps_hi_r_reg[17]_0 ;\n output [3:0]samps_zero_r_reg_0;\n output \\tap_r_reg[0]_0 ;\n output [4:0]\\run_r_reg[4]_0 ;\n output run_too_small_r_reg_0;\n output [0:0]\\rise_trail_r_reg[0] ;\n output \\sm_r_reg[0]_0 ;\n output \\sm_r_reg[0]_1 ;\n output [0:0]\\qcntr_r_reg[0] ;\n output [5:0]\\rise_lead_r_reg[5] ;\n output [0:0]DI;\n output [3:0]samps_zero_r_reg_1;\n output [2:0]samps_zero_r_reg_2;\n output [2:0]samps_zero_r_reg_3;\n output [0:0]samps_zero_r_reg_4;\n output [0:0]samps_zero_r_reg_5;\n output [0:0]\\samp_cntr_r_reg[0]_0 ;\n output [5:0]\\rise_trail_r_reg[5] ;\n output [0:0]\\rise_trail_r_reg[5]_0 ;\n output [0:0]\\rise_trail_r_reg[5]_1 ;\n output [0:0]\\rise_trail_r_reg[3] ;\n output \\samp_wait_r_reg[6]_0 ;\n output [6:0]\\samp_wait_r_reg[7]_0 ;\n output [0:0]\\rise_trail_r_reg[5]_2 ;\n output [0:0]\\rise_trail_r_reg[5]_3 ;\n input CLK;\n input [14:0]samps_lo;\n input rstdiv0_sync_r1_reg_rep__20;\n input \\run_r_reg[2]_0 ;\n input ocd_ktap_left_r_reg;\n input ocd_ktap_right_r_reg;\n input [5:0]trailing_edge0;\n input [5:0]trailing_edge00_in;\n input poc_sample_pd;\n input \\samp_wait_r_reg[4]_0 ;\n input [15:0]samp_cntr_ns0;\n input [17:0]samps_hi_ns0;\n input psdone;\n input rstdiv0_sync_r1_reg_rep;\n input [1:0]D;\n input rstdiv0_sync_r1_reg_rep__0;\n input [0:0]E;\n\n wire CLK;\n wire [1:0]D;\n wire [0:0]DI;\n wire [0:0]E;\n wire [4:0]Q;\n wire [3:0]S;\n wire ocd_ktap_left_r_reg;\n wire ocd_ktap_right_r_reg;\n wire [5:0]p_0_in;\n wire [5:0]p_0_in__0;\n wire [7:0]p_1_in;\n wire poc_sample_pd;\n wire psdone;\n wire [0:0]\\qcntr_r_reg[0] ;\n wire [5:0]\\rise_lead_r_reg[5] ;\n wire \\rise_trail_r[5]_i_4_n_0 ;\n wire \\rise_trail_r[5]_i_6_n_0 ;\n wire \\rise_trail_r[5]_i_7_n_0 ;\n wire \\rise_trail_r[5]_i_8_n_0 ;\n wire \\rise_trail_r[5]_i_9_n_0 ;\n wire [0:0]\\rise_trail_r_reg[0] ;\n wire [0:0]\\rise_trail_r_reg[3] ;\n wire [5:0]\\rise_trail_r_reg[5] ;\n wire [0:0]\\rise_trail_r_reg[5]_0 ;\n wire [0:0]\\rise_trail_r_reg[5]_1 ;\n wire [0:0]\\rise_trail_r_reg[5]_2 ;\n wire [0:0]\\rise_trail_r_reg[5]_3 ;\n wire rstdiv0_sync_r1_reg_rep;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire run_polarity_ns2_out;\n wire \\run_r[5]_i_2_n_0 ;\n wire \\run_r_reg[0]_0 ;\n wire \\run_r_reg[0]_1 ;\n wire \\run_r_reg[0]_2 ;\n wire \\run_r_reg[2]_0 ;\n wire [4:0]\\run_r_reg[4]_0 ;\n wire \\run_r_reg_n_0_[5] ;\n wire run_too_small_ns;\n wire run_too_small_r3_reg;\n wire run_too_small_r_reg_0;\n wire [16:16]samp_cntr;\n wire [15:0]samp_cntr_ns0;\n wire \\samp_cntr_r[0]_i_1_n_0 ;\n wire \\samp_cntr_r[10]_i_1_n_0 ;\n wire \\samp_cntr_r[11]_i_1_n_0 ;\n wire \\samp_cntr_r[12]_i_1_n_0 ;\n wire \\samp_cntr_r[13]_i_1_n_0 ;\n wire \\samp_cntr_r[14]_i_1_n_0 ;\n wire \\samp_cntr_r[15]_i_1_n_0 ;\n wire \\samp_cntr_r[16]_i_1_n_0 ;\n wire \\samp_cntr_r[1]_i_1_n_0 ;\n wire \\samp_cntr_r[2]_i_1_n_0 ;\n wire \\samp_cntr_r[3]_i_1_n_0 ;\n wire \\samp_cntr_r[4]_i_1_n_0 ;\n wire \\samp_cntr_r[5]_i_1_n_0 ;\n wire \\samp_cntr_r[6]_i_1_n_0 ;\n wire \\samp_cntr_r[7]_i_1_n_0 ;\n wire \\samp_cntr_r[8]_i_1_n_0 ;\n wire \\samp_cntr_r[9]_i_1_n_0 ;\n wire [0:0]\\samp_cntr_r_reg[0]_0 ;\n wire [3:0]\\samp_cntr_r_reg[12]_0 ;\n wire [3:0]\\samp_cntr_r_reg[16]_0 ;\n wire [3:0]\\samp_cntr_r_reg[8]_0 ;\n wire \\samp_cntr_r_reg_n_0_[10] ;\n wire \\samp_cntr_r_reg_n_0_[11] ;\n wire \\samp_cntr_r_reg_n_0_[12] ;\n wire \\samp_cntr_r_reg_n_0_[13] ;\n wire \\samp_cntr_r_reg_n_0_[14] ;\n wire \\samp_cntr_r_reg_n_0_[15] ;\n wire \\samp_cntr_r_reg_n_0_[1] ;\n wire \\samp_cntr_r_reg_n_0_[2] ;\n wire \\samp_cntr_r_reg_n_0_[3] ;\n wire \\samp_cntr_r_reg_n_0_[4] ;\n wire \\samp_cntr_r_reg_n_0_[5] ;\n wire \\samp_cntr_r_reg_n_0_[6] ;\n wire \\samp_cntr_r_reg_n_0_[7] ;\n wire \\samp_cntr_r_reg_n_0_[8] ;\n wire \\samp_cntr_r_reg_n_0_[9] ;\n wire [5:5]samp_wait_r;\n wire \\samp_wait_r[4]_i_2_n_0 ;\n wire \\samp_wait_r[7]_i_1_n_0 ;\n wire \\samp_wait_r_reg[4]_0 ;\n wire \\samp_wait_r_reg[6]_0 ;\n wire [6:0]\\samp_wait_r_reg[7]_0 ;\n wire [17:17]samps_hi;\n wire [17:0]samps_hi_ns0;\n wire \\samps_hi_r[0]_i_1_n_0 ;\n wire \\samps_hi_r[10]_i_1_n_0 ;\n wire \\samps_hi_r[11]_i_1_n_0 ;\n wire \\samps_hi_r[12]_i_1_n_0 ;\n wire \\samps_hi_r[13]_i_1_n_0 ;\n wire \\samps_hi_r[14]_i_1_n_0 ;\n wire \\samps_hi_r[15]_i_1_n_0 ;\n wire \\samps_hi_r[16]_i_1_n_0 ;\n wire \\samps_hi_r[17]_i_1_n_0 ;\n wire \\samps_hi_r[1]_i_1_n_0 ;\n wire \\samps_hi_r[2]_i_1_n_0 ;\n wire \\samps_hi_r[3]_i_1_n_0 ;\n wire \\samps_hi_r[4]_i_1_n_0 ;\n wire \\samps_hi_r[5]_i_1_n_0 ;\n wire \\samps_hi_r[6]_i_1_n_0 ;\n wire \\samps_hi_r[7]_i_1_n_0 ;\n wire \\samps_hi_r[8]_i_1_n_0 ;\n wire \\samps_hi_r[9]_i_1_n_0 ;\n wire [3:0]\\samps_hi_r_reg[11]_0 ;\n wire [3:0]\\samps_hi_r_reg[15]_0 ;\n wire [1:0]\\samps_hi_r_reg[17]_0 ;\n wire [2:0]\\samps_hi_r_reg[3]_0 ;\n wire [3:0]\\samps_hi_r_reg[7]_0 ;\n wire \\samps_hi_r_reg_n_0_[11] ;\n wire \\samps_hi_r_reg_n_0_[12] ;\n wire \\samps_hi_r_reg_n_0_[13] ;\n wire \\samps_hi_r_reg_n_0_[14] ;\n wire \\samps_hi_r_reg_n_0_[15] ;\n wire \\samps_hi_r_reg_n_0_[16] ;\n wire \\samps_hi_r_reg_n_0_[3] ;\n wire \\samps_hi_r_reg_n_0_[4] ;\n wire \\samps_hi_r_reg_n_0_[5] ;\n wire \\samps_hi_r_reg_n_0_[6] ;\n wire \\samps_hi_r_reg_n_0_[7] ;\n wire \\samps_hi_r_reg_n_0_[8] ;\n wire [14:0]samps_lo;\n wire samps_one_ns;\n wire samps_one_r0_carry__0_i_1_n_0;\n wire samps_one_r0_carry__0_i_2_n_0;\n wire samps_one_r0_carry__0_i_3_n_0;\n wire samps_one_r0_carry__0_i_4_n_0;\n wire samps_one_r0_carry__0_i_5_n_0;\n wire samps_one_r0_carry__0_i_6_n_0;\n wire samps_one_r0_carry__0_i_7_n_0;\n wire samps_one_r0_carry__0_n_0;\n wire samps_one_r0_carry__0_n_1;\n wire samps_one_r0_carry__0_n_2;\n wire samps_one_r0_carry__0_n_3;\n wire samps_one_r0_carry__1_i_1_n_0;\n wire samps_one_r0_carry__1_i_2_n_0;\n wire samps_one_r0_carry_i_1_n_0;\n wire samps_one_r0_carry_i_2_n_0;\n wire samps_one_r0_carry_i_3_n_0;\n wire samps_one_r0_carry_i_4_n_0;\n wire samps_one_r0_carry_i_5_n_0;\n wire samps_one_r0_carry_i_6_n_0;\n wire samps_one_r0_carry_i_7_n_0;\n wire samps_one_r0_carry_n_0;\n wire samps_one_r0_carry_n_1;\n wire samps_one_r0_carry_n_2;\n wire samps_one_r0_carry_n_3;\n wire samps_zero_ns;\n wire samps_zero_r0_carry__0_i_1_n_0;\n wire samps_zero_r0_carry__0_i_2_n_0;\n wire samps_zero_r0_carry__0_i_3_n_0;\n wire samps_zero_r0_carry__0_i_5_n_0;\n wire samps_zero_r0_carry__0_i_6_n_0;\n wire samps_zero_r0_carry__0_i_7_n_0;\n wire samps_zero_r0_carry__0_i_8_n_0;\n wire samps_zero_r0_carry__0_n_0;\n wire samps_zero_r0_carry__0_n_1;\n wire samps_zero_r0_carry__0_n_2;\n wire samps_zero_r0_carry__0_n_3;\n wire samps_zero_r0_carry__1_i_1_n_0;\n wire samps_zero_r0_carry__1_i_2_n_0;\n wire samps_zero_r0_carry_i_1_n_0;\n wire samps_zero_r0_carry_i_3_n_0;\n wire samps_zero_r0_carry_i_4_n_0;\n wire samps_zero_r0_carry_i_5_n_0;\n wire samps_zero_r0_carry_i_6_n_0;\n wire samps_zero_r0_carry_i_7_n_0;\n wire samps_zero_r0_carry_i_8_n_0;\n wire samps_zero_r0_carry_n_0;\n wire samps_zero_r0_carry_n_1;\n wire samps_zero_r0_carry_n_2;\n wire samps_zero_r0_carry_n_3;\n wire [3:0]samps_zero_r_reg_0;\n wire [3:0]samps_zero_r_reg_1;\n wire [2:0]samps_zero_r_reg_2;\n wire [2:0]samps_zero_r_reg_3;\n wire [0:0]samps_zero_r_reg_4;\n wire [0:0]samps_zero_r_reg_5;\n wire sm_ns0_carry__0_i_1_n_0;\n wire sm_ns0_carry__0_i_2_n_0;\n wire sm_ns0_carry__0_n_2;\n wire sm_ns0_carry__0_n_3;\n wire sm_ns0_carry_i_1_n_0;\n wire sm_ns0_carry_i_2_n_0;\n wire sm_ns0_carry_i_3_n_0;\n wire sm_ns0_carry_i_4_n_0;\n wire sm_ns0_carry_n_0;\n wire sm_ns0_carry_n_1;\n wire sm_ns0_carry_n_2;\n wire sm_ns0_carry_n_3;\n wire \\sm_r[0]_i_1_n_0 ;\n wire \\sm_r[0]_i_2_n_0 ;\n wire \\sm_r[1]_i_1_n_0 ;\n wire \\sm_r_reg[0]_0 ;\n wire \\sm_r_reg[0]_1 ;\n wire \\tap_r_reg[0]_0 ;\n wire [5:0]trailing_edge0;\n wire [5:0]trailing_edge00_in;\n wire [3:0]NLW_samps_one_r0_carry_O_UNCONNECTED;\n wire [3:0]NLW_samps_one_r0_carry__0_O_UNCONNECTED;\n wire [3:1]NLW_samps_one_r0_carry__1_CO_UNCONNECTED;\n wire [3:0]NLW_samps_one_r0_carry__1_O_UNCONNECTED;\n wire [3:0]NLW_samps_zero_r0_carry_O_UNCONNECTED;\n wire [3:0]NLW_samps_zero_r0_carry__0_O_UNCONNECTED;\n wire [3:1]NLW_samps_zero_r0_carry__1_CO_UNCONNECTED;\n wire [3:0]NLW_samps_zero_r0_carry__1_O_UNCONNECTED;\n wire [3:0]NLW_sm_ns0_carry_O_UNCONNECTED;\n wire [3:2]NLW_sm_ns0_carry__0_CO_UNCONNECTED;\n wire [3:0]NLW_sm_ns0_carry__0_O_UNCONNECTED;\n\n (* SOFT_HLUTNM = \"soft_lutpair453\" *) \n LUT3 #(\n .INIT(8'h04)) \n \\gen_mmcm.mmcm_i_i_1 \n (.I0(\\sm_r_reg[0]_0 ),\n .I1(\\sm_r_reg[0]_1 ),\n .I2(rstdiv0_sync_r1_reg_rep__20),\n .O(\\qcntr_r_reg[0] ));\n LUT6 #(\n .INIT(64'h0000000000000001)) \n i___12_i_1\n (.I0(\\samp_wait_r_reg[7]_0 [3]),\n .I1(\\samp_wait_r_reg[7]_0 [0]),\n .I2(\\samp_wait_r_reg[7]_0 [1]),\n .I3(\\samp_wait_r_reg[7]_0 [2]),\n .I4(\\samp_wait_r_reg[7]_0 [4]),\n .I5(samp_wait_r),\n .O(\\samp_wait_r_reg[6]_0 ));\n LUT6 #(\n .INIT(64'h0000000000B80000)) \n i___7_i_1__0\n (.I0(\\run_r_reg[0]_1 ),\n .I1(\\run_r_reg[0]_0 ),\n .I2(\\run_r_reg[0]_2 ),\n .I3(\\sm_r_reg[0]_0 ),\n .I4(\\sm_r_reg[0]_1 ),\n .I5(rstdiv0_sync_r1_reg_rep__20),\n .O(run_too_small_r_reg_0));\n LUT1 #(\n .INIT(2'h1)) \n i__carry__0_i_1\n (.I0(\\run_r_reg[4]_0 [3]),\n .O(DI));\n LUT4 #(\n .INIT(16'h9699)) \n i__carry__0_i_2\n (.I0(\\rise_lead_r_reg[5] [5]),\n .I1(\\run_r_reg_n_0_[5] ),\n .I2(\\rise_lead_r_reg[5] [4]),\n .I3(\\run_r_reg[4]_0 [4]),\n .O(\\rise_trail_r_reg[5]_0 ));\n LUT2 #(\n .INIT(4'h6)) \n i__carry_i_1\n (.I0(\\rise_lead_r_reg[5] [3]),\n .I1(\\run_r_reg[4]_0 [3]),\n .O(\\rise_trail_r_reg[3] ));\n (* SOFT_HLUTNM = \"soft_lutpair460\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\rise_trail_r[0]_i_1 \n (.I0(trailing_edge0[0]),\n .I1(\\rise_trail_r[5]_i_4_n_0 ),\n .I2(trailing_edge00_in[0]),\n .O(\\rise_trail_r_reg[5] [0]));\n (* SOFT_HLUTNM = \"soft_lutpair460\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\rise_trail_r[1]_i_1 \n (.I0(trailing_edge0[1]),\n .I1(\\rise_trail_r[5]_i_4_n_0 ),\n .I2(trailing_edge00_in[1]),\n .O(\\rise_trail_r_reg[5] [1]));\n (* SOFT_HLUTNM = \"soft_lutpair459\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\rise_trail_r[2]_i_1 \n (.I0(trailing_edge0[2]),\n .I1(\\rise_trail_r[5]_i_4_n_0 ),\n .I2(trailing_edge00_in[2]),\n .O(\\rise_trail_r_reg[5] [2]));\n (* SOFT_HLUTNM = \"soft_lutpair459\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\rise_trail_r[3]_i_1 \n (.I0(trailing_edge0[3]),\n .I1(\\rise_trail_r[5]_i_4_n_0 ),\n .I2(trailing_edge00_in[3]),\n .O(\\rise_trail_r_reg[5] [3]));\n (* SOFT_HLUTNM = \"soft_lutpair458\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\rise_trail_r[4]_i_1 \n (.I0(trailing_edge0[4]),\n .I1(\\rise_trail_r[5]_i_4_n_0 ),\n .I2(trailing_edge00_in[4]),\n .O(\\rise_trail_r_reg[5] [4]));\n LUT4 #(\n .INIT(16'h0008)) \n \\rise_trail_r[5]_i_1 \n (.I0(\\run_r_reg[0]_0 ),\n .I1(run_too_small_r_reg_0),\n .I2(ocd_ktap_left_r_reg),\n .I3(ocd_ktap_right_r_reg),\n .O(\\rise_trail_r_reg[0] ));\n LUT5 #(\n .INIT(32'h00800000)) \n \\rise_trail_r[5]_i_1__0 \n (.I0(\\run_r_reg[0]_1 ),\n .I1(\\run_r_reg[0]_0 ),\n .I2(\\tap_r_reg[0]_0 ),\n .I3(rstdiv0_sync_r1_reg_rep__20),\n .I4(ocd_ktap_right_r_reg),\n .O(\\rise_trail_r_reg[5]_2 ));\n LUT5 #(\n .INIT(32'h00800000)) \n \\rise_trail_r[5]_i_1__1 \n (.I0(\\run_r_reg[0]_1 ),\n .I1(\\run_r_reg[0]_0 ),\n .I2(\\tap_r_reg[0]_0 ),\n .I3(rstdiv0_sync_r1_reg_rep__20),\n .I4(ocd_ktap_left_r_reg),\n .O(\\rise_trail_r_reg[5]_3 ));\n (* SOFT_HLUTNM = \"soft_lutpair458\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\rise_trail_r[5]_i_2 \n (.I0(trailing_edge0[5]),\n .I1(\\rise_trail_r[5]_i_4_n_0 ),\n .I2(trailing_edge00_in[5]),\n .O(\\rise_trail_r_reg[5] [5]));\n LUT6 #(\n .INIT(64'h88888888A8AA88A8)) \n \\rise_trail_r[5]_i_4 \n (.I0(\\rise_trail_r[5]_i_6_n_0 ),\n .I1(\\rise_trail_r[5]_i_7_n_0 ),\n .I2(\\rise_trail_r[5]_i_8_n_0 ),\n .I3(\\run_r_reg[4]_0 [3]),\n .I4(\\rise_lead_r_reg[5] [3]),\n .I5(\\rise_trail_r[5]_i_9_n_0 ),\n .O(\\rise_trail_r[5]_i_4_n_0 ));\n LUT2 #(\n .INIT(4'h9)) \n \\rise_trail_r[5]_i_5 \n (.I0(\\run_r_reg_n_0_[5] ),\n .I1(\\rise_lead_r_reg[5] [5]),\n .O(\\rise_trail_r_reg[5]_1 ));\n (* SOFT_HLUTNM = \"soft_lutpair454\" *) \n LUT2 #(\n .INIT(4'hB)) \n \\rise_trail_r[5]_i_6 \n (.I0(\\rise_lead_r_reg[5] [5]),\n .I1(\\run_r_reg_n_0_[5] ),\n .O(\\rise_trail_r[5]_i_6_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair454\" *) \n LUT4 #(\n .INIT(16'h4F44)) \n \\rise_trail_r[5]_i_7 \n (.I0(\\run_r_reg_n_0_[5] ),\n .I1(\\rise_lead_r_reg[5] [5]),\n .I2(\\run_r_reg[4]_0 [4]),\n .I3(\\rise_lead_r_reg[5] [4]),\n .O(\\rise_trail_r[5]_i_7_n_0 ));\n LUT6 #(\n .INIT(64'hDF0D4F04DF0DDF0D)) \n \\rise_trail_r[5]_i_8 \n (.I0(\\run_r_reg[4]_0 [1]),\n .I1(\\rise_lead_r_reg[5] [1]),\n .I2(\\run_r_reg[4]_0 [2]),\n .I3(\\rise_lead_r_reg[5] [2]),\n .I4(\\rise_lead_r_reg[5] [0]),\n .I5(\\run_r_reg[4]_0 [0]),\n .O(\\rise_trail_r[5]_i_8_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair457\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\rise_trail_r[5]_i_9 \n (.I0(\\run_r_reg[4]_0 [4]),\n .I1(\\rise_lead_r_reg[5] [4]),\n .O(\\rise_trail_r[5]_i_9_n_0 ));\n LUT6 #(\n .INIT(64'h5151040055550400)) \n run_polarity_r_i_1\n (.I0(rstdiv0_sync_r1_reg_rep__20),\n .I1(\\sm_r_reg[0]_1 ),\n .I2(\\sm_r_reg[0]_0 ),\n .I3(\\run_r_reg[0]_2 ),\n .I4(\\run_r_reg[0]_0 ),\n .I5(\\run_r_reg[0]_1 ),\n .O(run_polarity_ns2_out));\n FDRE run_polarity_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(run_polarity_ns2_out),\n .Q(\\run_r_reg[0]_0 ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00000000333347FF)) \n \\run_r[0]_i_1 \n (.I0(\\run_r_reg[0]_1 ),\n .I1(\\run_r_reg[0]_0 ),\n .I2(\\run_r_reg[0]_2 ),\n .I3(\\tap_r_reg[0]_0 ),\n .I4(rstdiv0_sync_r1_reg_rep__20),\n .I5(\\run_r_reg[4]_0 [0]),\n .O(p_0_in__0[0]));\n LUT3 #(\n .INIT(8'h28)) \n \\run_r[1]_i_1 \n (.I0(\\run_r[5]_i_2_n_0 ),\n .I1(\\run_r_reg[4]_0 [0]),\n .I2(\\run_r_reg[4]_0 [1]),\n .O(p_0_in__0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair451\" *) \n LUT4 #(\n .INIT(16'h2A80)) \n \\run_r[2]_i_1 \n (.I0(\\run_r[5]_i_2_n_0 ),\n .I1(\\run_r_reg[4]_0 [1]),\n .I2(\\run_r_reg[4]_0 [0]),\n .I3(\\run_r_reg[4]_0 [2]),\n .O(p_0_in__0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair451\" *) \n LUT5 #(\n .INIT(32'h2AAA8000)) \n \\run_r[3]_i_1 \n (.I0(\\run_r[5]_i_2_n_0 ),\n .I1(\\run_r_reg[4]_0 [0]),\n .I2(\\run_r_reg[4]_0 [1]),\n .I3(\\run_r_reg[4]_0 [2]),\n .I4(\\run_r_reg[4]_0 [3]),\n .O(p_0_in__0[3]));\n LUT6 #(\n .INIT(64'h2AAAAAAA80000000)) \n \\run_r[4]_i_1 \n (.I0(\\run_r[5]_i_2_n_0 ),\n .I1(\\run_r_reg[4]_0 [2]),\n .I2(\\run_r_reg[4]_0 [1]),\n .I3(\\run_r_reg[4]_0 [0]),\n .I4(\\run_r_reg[4]_0 [3]),\n .I5(\\run_r_reg[4]_0 [4]),\n .O(p_0_in__0[4]));\n (* SOFT_HLUTNM = \"soft_lutpair457\" *) \n LUT4 #(\n .INIT(16'h8A20)) \n \\run_r[5]_i_1 \n (.I0(\\run_r[5]_i_2_n_0 ),\n .I1(\\run_r_reg[2]_0 ),\n .I2(\\run_r_reg[4]_0 [4]),\n .I3(\\run_r_reg_n_0_[5] ),\n .O(p_0_in__0[5]));\n LUT6 #(\n .INIT(64'h5151FBFF5555FBFF)) \n \\run_r[5]_i_2 \n (.I0(rstdiv0_sync_r1_reg_rep__20),\n .I1(\\sm_r_reg[0]_1 ),\n .I2(\\sm_r_reg[0]_0 ),\n .I3(\\run_r_reg[0]_2 ),\n .I4(\\run_r_reg[0]_0 ),\n .I5(\\run_r_reg[0]_1 ),\n .O(\\run_r[5]_i_2_n_0 ));\n FDRE \\run_r_reg[0] \n (.C(CLK),\n .CE(\\tap_r_reg[0]_0 ),\n .D(p_0_in__0[0]),\n .Q(\\run_r_reg[4]_0 [0]),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE \\run_r_reg[1] \n (.C(CLK),\n .CE(\\tap_r_reg[0]_0 ),\n .D(p_0_in__0[1]),\n .Q(\\run_r_reg[4]_0 [1]),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE \\run_r_reg[2] \n (.C(CLK),\n .CE(\\tap_r_reg[0]_0 ),\n .D(p_0_in__0[2]),\n .Q(\\run_r_reg[4]_0 [2]),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE \\run_r_reg[3] \n (.C(CLK),\n .CE(\\tap_r_reg[0]_0 ),\n .D(p_0_in__0[3]),\n .Q(\\run_r_reg[4]_0 [3]),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE \\run_r_reg[4] \n (.C(CLK),\n .CE(\\tap_r_reg[0]_0 ),\n .D(p_0_in__0[4]),\n .Q(\\run_r_reg[4]_0 [4]),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE \\run_r_reg[5] \n (.C(CLK),\n .CE(\\tap_r_reg[0]_0 ),\n .D(p_0_in__0[5]),\n .Q(\\run_r_reg_n_0_[5] ),\n .R(rstdiv0_sync_r1_reg_rep));\n LUT6 #(\n .INIT(64'h0002020202020202)) \n run_too_small_r_i_1\n (.I0(run_too_small_r_reg_0),\n .I1(\\run_r_reg[4]_0 [4]),\n .I2(\\run_r_reg_n_0_[5] ),\n .I3(\\run_r_reg[4]_0 [3]),\n .I4(\\run_r_reg[4]_0 [2]),\n .I5(\\run_r_reg[4]_0 [1]),\n .O(run_too_small_ns));\n FDRE run_too_small_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(run_too_small_ns),\n .Q(run_too_small_r3_reg),\n .R(1'b0));\n LUT2 #(\n .INIT(4'h1)) \n \\samp_cntr_r[0]_i_1 \n (.I0(\\sm_r_reg[0]_1 ),\n .I1(\\samp_cntr_r_reg[0]_0 ),\n .O(\\samp_cntr_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair477\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samp_cntr_r[10]_i_1 \n (.I0(samp_cntr_ns0[9]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samp_cntr_r[10]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair469\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samp_cntr_r[11]_i_1 \n (.I0(samp_cntr_ns0[10]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samp_cntr_r[11]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair472\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samp_cntr_r[12]_i_1 \n (.I0(samp_cntr_ns0[11]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samp_cntr_r[12]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_cntr_r[12]_i_3 \n (.I0(\\samp_cntr_r_reg_n_0_[12] ),\n .O(\\samp_cntr_r_reg[12]_0 [3]));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_cntr_r[12]_i_4 \n (.I0(\\samp_cntr_r_reg_n_0_[11] ),\n .O(\\samp_cntr_r_reg[12]_0 [2]));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_cntr_r[12]_i_5 \n (.I0(\\samp_cntr_r_reg_n_0_[10] ),\n .O(\\samp_cntr_r_reg[12]_0 [1]));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_cntr_r[12]_i_6 \n (.I0(\\samp_cntr_r_reg_n_0_[9] ),\n .O(\\samp_cntr_r_reg[12]_0 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair473\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samp_cntr_r[13]_i_1 \n (.I0(samp_cntr_ns0[12]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samp_cntr_r[13]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair473\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samp_cntr_r[14]_i_1 \n (.I0(samp_cntr_ns0[13]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samp_cntr_r[14]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair476\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samp_cntr_r[15]_i_1 \n (.I0(samp_cntr_ns0[14]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samp_cntr_r[15]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair474\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samp_cntr_r[16]_i_1 \n (.I0(samp_cntr_ns0[15]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samp_cntr_r[16]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_cntr_r[16]_i_3 \n (.I0(samp_cntr),\n .O(\\samp_cntr_r_reg[16]_0 [3]));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_cntr_r[16]_i_4 \n (.I0(\\samp_cntr_r_reg_n_0_[15] ),\n .O(\\samp_cntr_r_reg[16]_0 [2]));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_cntr_r[16]_i_5 \n (.I0(\\samp_cntr_r_reg_n_0_[14] ),\n .O(\\samp_cntr_r_reg[16]_0 [1]));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_cntr_r[16]_i_6 \n (.I0(\\samp_cntr_r_reg_n_0_[13] ),\n .O(\\samp_cntr_r_reg[16]_0 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair466\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samp_cntr_r[1]_i_1 \n (.I0(samp_cntr_ns0[0]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samp_cntr_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair464\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samp_cntr_r[2]_i_1 \n (.I0(samp_cntr_ns0[1]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samp_cntr_r[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair468\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samp_cntr_r[3]_i_1 \n (.I0(samp_cntr_ns0[2]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samp_cntr_r[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair477\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samp_cntr_r[4]_i_1 \n (.I0(samp_cntr_ns0[3]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samp_cntr_r[4]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_cntr_r[4]_i_3 \n (.I0(\\samp_cntr_r_reg_n_0_[4] ),\n .O(S[3]));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_cntr_r[4]_i_4 \n (.I0(\\samp_cntr_r_reg_n_0_[3] ),\n .O(S[2]));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_cntr_r[4]_i_5 \n (.I0(\\samp_cntr_r_reg_n_0_[2] ),\n .O(S[1]));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_cntr_r[4]_i_6 \n (.I0(\\samp_cntr_r_reg_n_0_[1] ),\n .O(S[0]));\n (* SOFT_HLUTNM = \"soft_lutpair467\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samp_cntr_r[5]_i_1 \n (.I0(samp_cntr_ns0[4]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samp_cntr_r[5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair471\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samp_cntr_r[6]_i_1 \n (.I0(samp_cntr_ns0[5]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samp_cntr_r[6]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair475\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samp_cntr_r[7]_i_1 \n (.I0(samp_cntr_ns0[6]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samp_cntr_r[7]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair462\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samp_cntr_r[8]_i_1 \n (.I0(samp_cntr_ns0[7]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samp_cntr_r[8]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_cntr_r[8]_i_3 \n (.I0(\\samp_cntr_r_reg_n_0_[8] ),\n .O(\\samp_cntr_r_reg[8]_0 [3]));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_cntr_r[8]_i_4 \n (.I0(\\samp_cntr_r_reg_n_0_[7] ),\n .O(\\samp_cntr_r_reg[8]_0 [2]));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_cntr_r[8]_i_5 \n (.I0(\\samp_cntr_r_reg_n_0_[6] ),\n .O(\\samp_cntr_r_reg[8]_0 [1]));\n LUT1 #(\n .INIT(2'h2)) \n \\samp_cntr_r[8]_i_6 \n (.I0(\\samp_cntr_r_reg_n_0_[5] ),\n .O(\\samp_cntr_r_reg[8]_0 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair465\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samp_cntr_r[9]_i_1 \n (.I0(samp_cntr_ns0[8]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samp_cntr_r[9]_i_1_n_0 ));\n FDRE \\samp_cntr_r_reg[0] \n (.C(CLK),\n .CE(E),\n .D(\\samp_cntr_r[0]_i_1_n_0 ),\n .Q(\\samp_cntr_r_reg[0]_0 ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\samp_cntr_r_reg[10] \n (.C(CLK),\n .CE(E),\n .D(\\samp_cntr_r[10]_i_1_n_0 ),\n .Q(\\samp_cntr_r_reg_n_0_[10] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\samp_cntr_r_reg[11] \n (.C(CLK),\n .CE(E),\n .D(\\samp_cntr_r[11]_i_1_n_0 ),\n .Q(\\samp_cntr_r_reg_n_0_[11] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\samp_cntr_r_reg[12] \n (.C(CLK),\n .CE(E),\n .D(\\samp_cntr_r[12]_i_1_n_0 ),\n .Q(\\samp_cntr_r_reg_n_0_[12] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\samp_cntr_r_reg[13] \n (.C(CLK),\n .CE(E),\n .D(\\samp_cntr_r[13]_i_1_n_0 ),\n .Q(\\samp_cntr_r_reg_n_0_[13] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\samp_cntr_r_reg[14] \n (.C(CLK),\n .CE(E),\n .D(\\samp_cntr_r[14]_i_1_n_0 ),\n .Q(\\samp_cntr_r_reg_n_0_[14] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\samp_cntr_r_reg[15] \n (.C(CLK),\n .CE(E),\n .D(\\samp_cntr_r[15]_i_1_n_0 ),\n .Q(\\samp_cntr_r_reg_n_0_[15] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\samp_cntr_r_reg[16] \n (.C(CLK),\n .CE(E),\n .D(\\samp_cntr_r[16]_i_1_n_0 ),\n .Q(samp_cntr),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\samp_cntr_r_reg[1] \n (.C(CLK),\n .CE(E),\n .D(\\samp_cntr_r[1]_i_1_n_0 ),\n .Q(\\samp_cntr_r_reg_n_0_[1] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\samp_cntr_r_reg[2] \n (.C(CLK),\n .CE(E),\n .D(\\samp_cntr_r[2]_i_1_n_0 ),\n .Q(\\samp_cntr_r_reg_n_0_[2] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\samp_cntr_r_reg[3] \n (.C(CLK),\n .CE(E),\n .D(\\samp_cntr_r[3]_i_1_n_0 ),\n .Q(\\samp_cntr_r_reg_n_0_[3] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\samp_cntr_r_reg[4] \n (.C(CLK),\n .CE(E),\n .D(\\samp_cntr_r[4]_i_1_n_0 ),\n .Q(\\samp_cntr_r_reg_n_0_[4] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\samp_cntr_r_reg[5] \n (.C(CLK),\n .CE(E),\n .D(\\samp_cntr_r[5]_i_1_n_0 ),\n .Q(\\samp_cntr_r_reg_n_0_[5] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\samp_cntr_r_reg[6] \n (.C(CLK),\n .CE(E),\n .D(\\samp_cntr_r[6]_i_1_n_0 ),\n .Q(\\samp_cntr_r_reg_n_0_[6] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\samp_cntr_r_reg[7] \n (.C(CLK),\n .CE(E),\n .D(\\samp_cntr_r[7]_i_1_n_0 ),\n .Q(\\samp_cntr_r_reg_n_0_[7] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\samp_cntr_r_reg[8] \n (.C(CLK),\n .CE(E),\n .D(\\samp_cntr_r[8]_i_1_n_0 ),\n .Q(\\samp_cntr_r_reg_n_0_[8] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\samp_cntr_r_reg[9] \n (.C(CLK),\n .CE(E),\n .D(\\samp_cntr_r[9]_i_1_n_0 ),\n .Q(\\samp_cntr_r_reg_n_0_[9] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n (* SOFT_HLUTNM = \"soft_lutpair456\" *) \n LUT3 #(\n .INIT(8'h8F)) \n \\samp_wait_r[0]_i_1 \n (.I0(\\sm_r_reg[0]_1 ),\n .I1(\\sm_r_reg[0]_0 ),\n .I2(\\samp_wait_r_reg[7]_0 [0]),\n .O(p_1_in[0]));\n (* SOFT_HLUTNM = \"soft_lutpair456\" *) \n LUT4 #(\n .INIT(16'hF88F)) \n \\samp_wait_r[1]_i_1 \n (.I0(\\sm_r_reg[0]_1 ),\n .I1(\\sm_r_reg[0]_0 ),\n .I2(\\samp_wait_r_reg[7]_0 [1]),\n .I3(\\samp_wait_r_reg[7]_0 [0]),\n .O(p_1_in[1]));\n LUT6 #(\n .INIT(64'hFFFFFFFEAAAAAAAB)) \n \\samp_wait_r[4]_i_1 \n (.I0(\\samp_wait_r[4]_i_2_n_0 ),\n .I1(\\samp_wait_r_reg[7]_0 [3]),\n .I2(\\samp_wait_r_reg[7]_0 [0]),\n .I3(\\samp_wait_r_reg[7]_0 [1]),\n .I4(\\samp_wait_r_reg[7]_0 [2]),\n .I5(\\samp_wait_r_reg[7]_0 [4]),\n .O(p_1_in[4]));\n (* SOFT_HLUTNM = \"soft_lutpair455\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\samp_wait_r[4]_i_2 \n (.I0(\\sm_r_reg[0]_0 ),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samp_wait_r[4]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair455\" *) \n LUT4 #(\n .INIT(16'h8FF8)) \n \\samp_wait_r[5]_i_1 \n (.I0(\\sm_r_reg[0]_1 ),\n .I1(\\sm_r_reg[0]_0 ),\n .I2(\\samp_wait_r_reg[4]_0 ),\n .I3(samp_wait_r),\n .O(p_1_in[5]));\n (* SOFT_HLUTNM = \"soft_lutpair450\" *) \n LUT4 #(\n .INIT(16'h8FF8)) \n \\samp_wait_r[6]_i_1 \n (.I0(\\sm_r_reg[0]_1 ),\n .I1(\\sm_r_reg[0]_0 ),\n .I2(\\samp_wait_r_reg[6]_0 ),\n .I3(\\samp_wait_r_reg[7]_0 [5]),\n .O(p_1_in[6]));\n LUT5 #(\n .INIT(32'hFFFFFF8F)) \n \\samp_wait_r[7]_i_1 \n (.I0(\\sm_r_reg[0]_1 ),\n .I1(\\sm_r_reg[0]_0 ),\n .I2(\\samp_wait_r_reg[6]_0 ),\n .I3(\\samp_wait_r_reg[7]_0 [5]),\n .I4(\\samp_wait_r_reg[7]_0 [6]),\n .O(\\samp_wait_r[7]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair450\" *) \n LUT5 #(\n .INIT(32'hFF8F88F8)) \n \\samp_wait_r[7]_i_2 \n (.I0(\\sm_r_reg[0]_1 ),\n .I1(\\sm_r_reg[0]_0 ),\n .I2(\\samp_wait_r_reg[6]_0 ),\n .I3(\\samp_wait_r_reg[7]_0 [5]),\n .I4(\\samp_wait_r_reg[7]_0 [6]),\n .O(p_1_in[7]));\n FDRE \\samp_wait_r_reg[0] \n (.C(CLK),\n .CE(\\samp_wait_r[7]_i_1_n_0 ),\n .D(p_1_in[0]),\n .Q(\\samp_wait_r_reg[7]_0 [0]),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE \\samp_wait_r_reg[1] \n (.C(CLK),\n .CE(\\samp_wait_r[7]_i_1_n_0 ),\n .D(p_1_in[1]),\n .Q(\\samp_wait_r_reg[7]_0 [1]),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE \\samp_wait_r_reg[2] \n (.C(CLK),\n .CE(\\samp_wait_r[7]_i_1_n_0 ),\n .D(D[0]),\n .Q(\\samp_wait_r_reg[7]_0 [2]),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE \\samp_wait_r_reg[3] \n (.C(CLK),\n .CE(\\samp_wait_r[7]_i_1_n_0 ),\n .D(D[1]),\n .Q(\\samp_wait_r_reg[7]_0 [3]),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE \\samp_wait_r_reg[4] \n (.C(CLK),\n .CE(\\samp_wait_r[7]_i_1_n_0 ),\n .D(p_1_in[4]),\n .Q(\\samp_wait_r_reg[7]_0 [4]),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE \\samp_wait_r_reg[5] \n (.C(CLK),\n .CE(\\samp_wait_r[7]_i_1_n_0 ),\n .D(p_1_in[5]),\n .Q(samp_wait_r),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE \\samp_wait_r_reg[6] \n (.C(CLK),\n .CE(\\samp_wait_r[7]_i_1_n_0 ),\n .D(p_1_in[6]),\n .Q(\\samp_wait_r_reg[7]_0 [5]),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE \\samp_wait_r_reg[7] \n (.C(CLK),\n .CE(\\samp_wait_r[7]_i_1_n_0 ),\n .D(p_1_in[7]),\n .Q(\\samp_wait_r_reg[7]_0 [6]),\n .R(rstdiv0_sync_r1_reg_rep));\n (* SOFT_HLUTNM = \"soft_lutpair474\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[0]_i_1 \n (.I0(samps_hi_ns0[0]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair470\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[10]_i_1 \n (.I0(samps_hi_ns0[10]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[10]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair468\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[11]_i_1 \n (.I0(samps_hi_ns0[11]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[11]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samps_hi_r[11]_i_3 \n (.I0(\\samps_hi_r_reg_n_0_[11] ),\n .O(\\samps_hi_r_reg[11]_0 [3]));\n LUT1 #(\n .INIT(2'h2)) \n \\samps_hi_r[11]_i_4 \n (.I0(Q[4]),\n .O(\\samps_hi_r_reg[11]_0 [2]));\n LUT1 #(\n .INIT(2'h2)) \n \\samps_hi_r[11]_i_5 \n (.I0(Q[3]),\n .O(\\samps_hi_r_reg[11]_0 [1]));\n LUT1 #(\n .INIT(2'h2)) \n \\samps_hi_r[11]_i_6 \n (.I0(\\samps_hi_r_reg_n_0_[8] ),\n .O(\\samps_hi_r_reg[11]_0 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair467\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[12]_i_1 \n (.I0(samps_hi_ns0[12]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[12]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair462\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[13]_i_1 \n (.I0(samps_hi_ns0[13]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[13]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair466\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[14]_i_1 \n (.I0(samps_hi_ns0[14]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[14]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair464\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[15]_i_1 \n (.I0(samps_hi_ns0[15]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[15]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samps_hi_r[15]_i_3 \n (.I0(\\samps_hi_r_reg_n_0_[15] ),\n .O(\\samps_hi_r_reg[15]_0 [3]));\n LUT1 #(\n .INIT(2'h2)) \n \\samps_hi_r[15]_i_4 \n (.I0(\\samps_hi_r_reg_n_0_[14] ),\n .O(\\samps_hi_r_reg[15]_0 [2]));\n LUT1 #(\n .INIT(2'h2)) \n \\samps_hi_r[15]_i_5 \n (.I0(\\samps_hi_r_reg_n_0_[13] ),\n .O(\\samps_hi_r_reg[15]_0 [1]));\n LUT1 #(\n .INIT(2'h2)) \n \\samps_hi_r[15]_i_6 \n (.I0(\\samps_hi_r_reg_n_0_[12] ),\n .O(\\samps_hi_r_reg[15]_0 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair463\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[16]_i_1 \n (.I0(samps_hi_ns0[16]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[16]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair461\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[17]_i_1 \n (.I0(samps_hi_ns0[17]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[17]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samps_hi_r[17]_i_3 \n (.I0(samps_hi),\n .O(\\samps_hi_r_reg[17]_0 [1]));\n LUT1 #(\n .INIT(2'h2)) \n \\samps_hi_r[17]_i_4 \n (.I0(\\samps_hi_r_reg_n_0_[16] ),\n .O(\\samps_hi_r_reg[17]_0 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair463\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[1]_i_1 \n (.I0(samps_hi_ns0[1]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair461\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[2]_i_1 \n (.I0(samps_hi_ns0[2]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[2]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair470\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[3]_i_1 \n (.I0(samps_hi_ns0[3]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[3]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samps_hi_r[3]_i_3 \n (.I0(\\samps_hi_r_reg_n_0_[3] ),\n .O(\\samps_hi_r_reg[3]_0 [2]));\n LUT1 #(\n .INIT(2'h2)) \n \\samps_hi_r[3]_i_4 \n (.I0(Q[2]),\n .O(\\samps_hi_r_reg[3]_0 [1]));\n LUT1 #(\n .INIT(2'h2)) \n \\samps_hi_r[3]_i_5 \n (.I0(Q[1]),\n .O(\\samps_hi_r_reg[3]_0 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair476\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[4]_i_1 \n (.I0(samps_hi_ns0[4]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[4]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair469\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[5]_i_1 \n (.I0(samps_hi_ns0[5]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[5]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair475\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[6]_i_1 \n (.I0(samps_hi_ns0[6]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[6]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair472\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[7]_i_1 \n (.I0(samps_hi_ns0[7]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[7]_i_1_n_0 ));\n LUT1 #(\n .INIT(2'h2)) \n \\samps_hi_r[7]_i_3 \n (.I0(\\samps_hi_r_reg_n_0_[7] ),\n .O(\\samps_hi_r_reg[7]_0 [3]));\n LUT1 #(\n .INIT(2'h2)) \n \\samps_hi_r[7]_i_4 \n (.I0(\\samps_hi_r_reg_n_0_[6] ),\n .O(\\samps_hi_r_reg[7]_0 [2]));\n LUT1 #(\n .INIT(2'h2)) \n \\samps_hi_r[7]_i_5 \n (.I0(\\samps_hi_r_reg_n_0_[5] ),\n .O(\\samps_hi_r_reg[7]_0 [1]));\n LUT1 #(\n .INIT(2'h2)) \n \\samps_hi_r[7]_i_6 \n (.I0(\\samps_hi_r_reg_n_0_[4] ),\n .O(\\samps_hi_r_reg[7]_0 [0]));\n (* SOFT_HLUTNM = \"soft_lutpair471\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[8]_i_1 \n (.I0(samps_hi_ns0[8]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[8]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair465\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\samps_hi_r[9]_i_1 \n (.I0(samps_hi_ns0[9]),\n .I1(\\sm_r_reg[0]_1 ),\n .O(\\samps_hi_r[9]_i_1_n_0 ));\n FDRE \\samps_hi_r_reg[0] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[0]_i_1_n_0 ),\n .Q(Q[0]),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\samps_hi_r_reg[10] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[10]_i_1_n_0 ),\n .Q(Q[4]),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\samps_hi_r_reg[11] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[11]_i_1_n_0 ),\n .Q(\\samps_hi_r_reg_n_0_[11] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\samps_hi_r_reg[12] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[12]_i_1_n_0 ),\n .Q(\\samps_hi_r_reg_n_0_[12] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\samps_hi_r_reg[13] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[13]_i_1_n_0 ),\n .Q(\\samps_hi_r_reg_n_0_[13] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\samps_hi_r_reg[14] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[14]_i_1_n_0 ),\n .Q(\\samps_hi_r_reg_n_0_[14] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\samps_hi_r_reg[15] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[15]_i_1_n_0 ),\n .Q(\\samps_hi_r_reg_n_0_[15] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\samps_hi_r_reg[16] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[16]_i_1_n_0 ),\n .Q(\\samps_hi_r_reg_n_0_[16] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\samps_hi_r_reg[17] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[17]_i_1_n_0 ),\n .Q(samps_hi),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\samps_hi_r_reg[1] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[1]_i_1_n_0 ),\n .Q(Q[1]),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\samps_hi_r_reg[2] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[2]_i_1_n_0 ),\n .Q(Q[2]),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\samps_hi_r_reg[3] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[3]_i_1_n_0 ),\n .Q(\\samps_hi_r_reg_n_0_[3] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\samps_hi_r_reg[4] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[4]_i_1_n_0 ),\n .Q(\\samps_hi_r_reg_n_0_[4] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\samps_hi_r_reg[5] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[5]_i_1_n_0 ),\n .Q(\\samps_hi_r_reg_n_0_[5] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\samps_hi_r_reg[6] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[6]_i_1_n_0 ),\n .Q(\\samps_hi_r_reg_n_0_[6] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\samps_hi_r_reg[7] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[7]_i_1_n_0 ),\n .Q(\\samps_hi_r_reg_n_0_[7] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\samps_hi_r_reg[8] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[8]_i_1_n_0 ),\n .Q(\\samps_hi_r_reg_n_0_[8] ),\n .R(rstdiv0_sync_r1_reg_rep__0));\n FDRE \\samps_hi_r_reg[9] \n (.C(CLK),\n .CE(E),\n .D(\\samps_hi_r[9]_i_1_n_0 ),\n .Q(Q[3]),\n .R(rstdiv0_sync_r1_reg_rep__0));\n CARRY4 samps_one_r0_carry\n (.CI(1'b0),\n .CO({samps_one_r0_carry_n_0,samps_one_r0_carry_n_1,samps_one_r0_carry_n_2,samps_one_r0_carry_n_3}),\n .CYINIT(1'b1),\n .DI({samps_one_r0_carry_i_1_n_0,\\samps_hi_r_reg_n_0_[5] ,samps_one_r0_carry_i_2_n_0,samps_one_r0_carry_i_3_n_0}),\n .O(NLW_samps_one_r0_carry_O_UNCONNECTED[3:0]),\n .S({samps_one_r0_carry_i_4_n_0,samps_one_r0_carry_i_5_n_0,samps_one_r0_carry_i_6_n_0,samps_one_r0_carry_i_7_n_0}));\n CARRY4 samps_one_r0_carry__0\n (.CI(samps_one_r0_carry_n_0),\n .CO({samps_one_r0_carry__0_n_0,samps_one_r0_carry__0_n_1,samps_one_r0_carry__0_n_2,samps_one_r0_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({samps_one_r0_carry__0_i_1_n_0,samps_one_r0_carry__0_i_2_n_0,samps_one_r0_carry__0_i_3_n_0,Q[3]}),\n .O(NLW_samps_one_r0_carry__0_O_UNCONNECTED[3:0]),\n .S({samps_one_r0_carry__0_i_4_n_0,samps_one_r0_carry__0_i_5_n_0,samps_one_r0_carry__0_i_6_n_0,samps_one_r0_carry__0_i_7_n_0}));\n LUT2 #(\n .INIT(4'hE)) \n samps_one_r0_carry__0_i_1\n (.I0(\\samps_hi_r_reg_n_0_[15] ),\n .I1(\\samps_hi_r_reg_n_0_[14] ),\n .O(samps_one_r0_carry__0_i_1_n_0));\n LUT2 #(\n .INIT(4'hE)) \n samps_one_r0_carry__0_i_2\n (.I0(\\samps_hi_r_reg_n_0_[13] ),\n .I1(\\samps_hi_r_reg_n_0_[12] ),\n .O(samps_one_r0_carry__0_i_2_n_0));\n LUT2 #(\n .INIT(4'hE)) \n samps_one_r0_carry__0_i_3\n (.I0(\\samps_hi_r_reg_n_0_[11] ),\n .I1(Q[4]),\n .O(samps_one_r0_carry__0_i_3_n_0));\n LUT2 #(\n .INIT(4'h1)) \n samps_one_r0_carry__0_i_4\n (.I0(\\samps_hi_r_reg_n_0_[14] ),\n .I1(\\samps_hi_r_reg_n_0_[15] ),\n .O(samps_one_r0_carry__0_i_4_n_0));\n LUT2 #(\n .INIT(4'h1)) \n samps_one_r0_carry__0_i_5\n (.I0(\\samps_hi_r_reg_n_0_[12] ),\n .I1(\\samps_hi_r_reg_n_0_[13] ),\n .O(samps_one_r0_carry__0_i_5_n_0));\n LUT2 #(\n .INIT(4'h1)) \n samps_one_r0_carry__0_i_6\n (.I0(Q[4]),\n .I1(\\samps_hi_r_reg_n_0_[11] ),\n .O(samps_one_r0_carry__0_i_6_n_0));\n LUT2 #(\n .INIT(4'h2)) \n samps_one_r0_carry__0_i_7\n (.I0(\\samps_hi_r_reg_n_0_[8] ),\n .I1(Q[3]),\n .O(samps_one_r0_carry__0_i_7_n_0));\n CARRY4 samps_one_r0_carry__1\n (.CI(samps_one_r0_carry__0_n_0),\n .CO({NLW_samps_one_r0_carry__1_CO_UNCONNECTED[3:1],samps_one_ns}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,samps_one_r0_carry__1_i_1_n_0}),\n .O(NLW_samps_one_r0_carry__1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,1'b0,samps_one_r0_carry__1_i_2_n_0}));\n LUT2 #(\n .INIT(4'hE)) \n samps_one_r0_carry__1_i_1\n (.I0(samps_hi),\n .I1(\\samps_hi_r_reg_n_0_[16] ),\n .O(samps_one_r0_carry__1_i_1_n_0));\n LUT2 #(\n .INIT(4'h1)) \n samps_one_r0_carry__1_i_2\n (.I0(\\samps_hi_r_reg_n_0_[16] ),\n .I1(samps_hi),\n .O(samps_one_r0_carry__1_i_2_n_0));\n LUT2 #(\n .INIT(4'h8)) \n samps_one_r0_carry_i_1\n (.I0(\\samps_hi_r_reg_n_0_[7] ),\n .I1(\\samps_hi_r_reg_n_0_[6] ),\n .O(samps_one_r0_carry_i_1_n_0));\n LUT2 #(\n .INIT(4'h8)) \n samps_one_r0_carry_i_2\n (.I0(\\samps_hi_r_reg_n_0_[3] ),\n .I1(Q[2]),\n .O(samps_one_r0_carry_i_2_n_0));\n LUT2 #(\n .INIT(4'h8)) \n samps_one_r0_carry_i_3\n (.I0(Q[0]),\n .I1(Q[1]),\n .O(samps_one_r0_carry_i_3_n_0));\n LUT2 #(\n .INIT(4'h2)) \n samps_one_r0_carry_i_4\n (.I0(\\samps_hi_r_reg_n_0_[7] ),\n .I1(\\samps_hi_r_reg_n_0_[6] ),\n .O(samps_one_r0_carry_i_4_n_0));\n LUT2 #(\n .INIT(4'h2)) \n samps_one_r0_carry_i_5\n (.I0(\\samps_hi_r_reg_n_0_[4] ),\n .I1(\\samps_hi_r_reg_n_0_[5] ),\n .O(samps_one_r0_carry_i_5_n_0));\n LUT2 #(\n .INIT(4'h2)) \n samps_one_r0_carry_i_6\n (.I0(\\samps_hi_r_reg_n_0_[3] ),\n .I1(Q[2]),\n .O(samps_one_r0_carry_i_6_n_0));\n LUT2 #(\n .INIT(4'h2)) \n samps_one_r0_carry_i_7\n (.I0(Q[1]),\n .I1(Q[0]),\n .O(samps_one_r0_carry_i_7_n_0));\n FDRE samps_one_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(samps_one_ns),\n .Q(\\run_r_reg[0]_2 ),\n .R(1'b0));\n CARRY4 samps_zero_r0_carry\n (.CI(1'b0),\n .CO({samps_zero_r0_carry_n_0,samps_zero_r0_carry_n_1,samps_zero_r0_carry_n_2,samps_zero_r0_carry_n_3}),\n .CYINIT(1'b1),\n .DI({samps_zero_r0_carry_i_1_n_0,samps_lo[2],samps_zero_r0_carry_i_3_n_0,samps_zero_r0_carry_i_4_n_0}),\n .O(NLW_samps_zero_r0_carry_O_UNCONNECTED[3:0]),\n .S({samps_zero_r0_carry_i_5_n_0,samps_zero_r0_carry_i_6_n_0,samps_zero_r0_carry_i_7_n_0,samps_zero_r0_carry_i_8_n_0}));\n CARRY4 samps_zero_r0_carry__0\n (.CI(samps_zero_r0_carry_n_0),\n .CO({samps_zero_r0_carry__0_n_0,samps_zero_r0_carry__0_n_1,samps_zero_r0_carry__0_n_2,samps_zero_r0_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({samps_zero_r0_carry__0_i_1_n_0,samps_zero_r0_carry__0_i_2_n_0,samps_zero_r0_carry__0_i_3_n_0,samps_lo[6]}),\n .O(NLW_samps_zero_r0_carry__0_O_UNCONNECTED[3:0]),\n .S({samps_zero_r0_carry__0_i_5_n_0,samps_zero_r0_carry__0_i_6_n_0,samps_zero_r0_carry__0_i_7_n_0,samps_zero_r0_carry__0_i_8_n_0}));\n LUT2 #(\n .INIT(4'hE)) \n samps_zero_r0_carry__0_i_1\n (.I0(samps_lo[12]),\n .I1(samps_lo[11]),\n .O(samps_zero_r0_carry__0_i_1_n_0));\n LUT1 #(\n .INIT(2'h2)) \n samps_zero_r0_carry__0_i_11\n (.I0(Q[3]),\n .O(samps_zero_r_reg_0[3]));\n LUT1 #(\n .INIT(2'h1)) \n samps_zero_r0_carry__0_i_12\n (.I0(\\samps_hi_r_reg_n_0_[8] ),\n .O(samps_zero_r_reg_0[2]));\n LUT1 #(\n .INIT(2'h1)) \n samps_zero_r0_carry__0_i_13\n (.I0(\\samps_hi_r_reg_n_0_[7] ),\n .O(samps_zero_r_reg_0[1]));\n LUT1 #(\n .INIT(2'h1)) \n samps_zero_r0_carry__0_i_14\n (.I0(\\samps_hi_r_reg_n_0_[6] ),\n .O(samps_zero_r_reg_0[0]));\n LUT1 #(\n .INIT(2'h1)) \n samps_zero_r0_carry__0_i_15\n (.I0(samps_hi),\n .O(samps_zero_r_reg_1[3]));\n LUT1 #(\n .INIT(2'h1)) \n samps_zero_r0_carry__0_i_16\n (.I0(\\samps_hi_r_reg_n_0_[16] ),\n .O(samps_zero_r_reg_1[2]));\n LUT1 #(\n .INIT(2'h1)) \n samps_zero_r0_carry__0_i_17\n (.I0(\\samps_hi_r_reg_n_0_[15] ),\n .O(samps_zero_r_reg_1[1]));\n LUT1 #(\n .INIT(2'h1)) \n samps_zero_r0_carry__0_i_18\n (.I0(\\samps_hi_r_reg_n_0_[14] ),\n .O(samps_zero_r_reg_1[0]));\n LUT1 #(\n .INIT(2'h1)) \n samps_zero_r0_carry__0_i_19\n (.I0(Q[3]),\n .O(samps_zero_r_reg_5));\n LUT2 #(\n .INIT(4'hE)) \n samps_zero_r0_carry__0_i_2\n (.I0(samps_lo[10]),\n .I1(samps_lo[9]),\n .O(samps_zero_r0_carry__0_i_2_n_0));\n LUT1 #(\n .INIT(2'h1)) \n samps_zero_r0_carry__0_i_20\n (.I0(\\samps_hi_r_reg_n_0_[13] ),\n .O(samps_zero_r_reg_2[2]));\n LUT1 #(\n .INIT(2'h1)) \n samps_zero_r0_carry__0_i_21\n (.I0(\\samps_hi_r_reg_n_0_[12] ),\n .O(samps_zero_r_reg_2[1]));\n LUT1 #(\n .INIT(2'h1)) \n samps_zero_r0_carry__0_i_22\n (.I0(\\samps_hi_r_reg_n_0_[11] ),\n .O(samps_zero_r_reg_2[0]));\n LUT2 #(\n .INIT(4'hE)) \n samps_zero_r0_carry__0_i_3\n (.I0(samps_lo[8]),\n .I1(samps_lo[7]),\n .O(samps_zero_r0_carry__0_i_3_n_0));\n LUT2 #(\n .INIT(4'h1)) \n samps_zero_r0_carry__0_i_5\n (.I0(samps_lo[11]),\n .I1(samps_lo[12]),\n .O(samps_zero_r0_carry__0_i_5_n_0));\n LUT2 #(\n .INIT(4'h1)) \n samps_zero_r0_carry__0_i_6\n (.I0(samps_lo[9]),\n .I1(samps_lo[10]),\n .O(samps_zero_r0_carry__0_i_6_n_0));\n LUT2 #(\n .INIT(4'h1)) \n samps_zero_r0_carry__0_i_7\n (.I0(samps_lo[7]),\n .I1(samps_lo[8]),\n .O(samps_zero_r0_carry__0_i_7_n_0));\n LUT2 #(\n .INIT(4'h2)) \n samps_zero_r0_carry__0_i_8\n (.I0(samps_lo[5]),\n .I1(samps_lo[6]),\n .O(samps_zero_r0_carry__0_i_8_n_0));\n CARRY4 samps_zero_r0_carry__1\n (.CI(samps_zero_r0_carry__0_n_0),\n .CO({NLW_samps_zero_r0_carry__1_CO_UNCONNECTED[3:1],samps_zero_ns}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,samps_zero_r0_carry__1_i_1_n_0}),\n .O(NLW_samps_zero_r0_carry__1_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,1'b0,samps_zero_r0_carry__1_i_2_n_0}));\n LUT2 #(\n .INIT(4'hE)) \n samps_zero_r0_carry__1_i_1\n (.I0(samps_lo[14]),\n .I1(samps_lo[13]),\n .O(samps_zero_r0_carry__1_i_1_n_0));\n LUT2 #(\n .INIT(4'h1)) \n samps_zero_r0_carry__1_i_2\n (.I0(samps_lo[13]),\n .I1(samps_lo[14]),\n .O(samps_zero_r0_carry__1_i_2_n_0));\n LUT2 #(\n .INIT(4'h8)) \n samps_zero_r0_carry_i_1\n (.I0(samps_lo[4]),\n .I1(samps_lo[3]),\n .O(samps_zero_r0_carry_i_1_n_0));\n LUT1 #(\n .INIT(2'h1)) \n samps_zero_r0_carry_i_10\n (.I0(\\samps_hi_r_reg_n_0_[5] ),\n .O(samps_zero_r_reg_3[2]));\n LUT1 #(\n .INIT(2'h1)) \n samps_zero_r0_carry_i_11\n (.I0(\\samps_hi_r_reg_n_0_[4] ),\n .O(samps_zero_r_reg_3[1]));\n LUT1 #(\n .INIT(2'h1)) \n samps_zero_r0_carry_i_12\n (.I0(\\samps_hi_r_reg_n_0_[3] ),\n .O(samps_zero_r_reg_3[0]));\n LUT3 #(\n .INIT(8'h28)) \n samps_zero_r0_carry_i_3\n (.I0(samps_lo[0]),\n .I1(Q[2]),\n .I2(Q[1]),\n .O(samps_zero_r0_carry_i_3_n_0));\n LUT2 #(\n .INIT(4'h2)) \n samps_zero_r0_carry_i_4\n (.I0(Q[1]),\n .I1(Q[0]),\n .O(samps_zero_r0_carry_i_4_n_0));\n LUT2 #(\n .INIT(4'h2)) \n samps_zero_r0_carry_i_5\n (.I0(samps_lo[4]),\n .I1(samps_lo[3]),\n .O(samps_zero_r0_carry_i_5_n_0));\n LUT2 #(\n .INIT(4'h2)) \n samps_zero_r0_carry_i_6\n (.I0(samps_lo[1]),\n .I1(samps_lo[2]),\n .O(samps_zero_r0_carry_i_6_n_0));\n LUT3 #(\n .INIT(8'h82)) \n samps_zero_r0_carry_i_7\n (.I0(samps_lo[0]),\n .I1(Q[2]),\n .I2(Q[1]),\n .O(samps_zero_r0_carry_i_7_n_0));\n LUT2 #(\n .INIT(4'h8)) \n samps_zero_r0_carry_i_8\n (.I0(Q[0]),\n .I1(Q[1]),\n .O(samps_zero_r0_carry_i_8_n_0));\n LUT1 #(\n .INIT(2'h1)) \n samps_zero_r0_carry_i_9\n (.I0(Q[1]),\n .O(samps_zero_r_reg_4));\n FDRE samps_zero_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(samps_zero_ns),\n .Q(\\run_r_reg[0]_1 ),\n .R(1'b0));\n CARRY4 sm_ns0_carry\n (.CI(1'b0),\n .CO({sm_ns0_carry_n_0,sm_ns0_carry_n_1,sm_ns0_carry_n_2,sm_ns0_carry_n_3}),\n .CYINIT(1'b1),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(NLW_sm_ns0_carry_O_UNCONNECTED[3:0]),\n .S({sm_ns0_carry_i_1_n_0,sm_ns0_carry_i_2_n_0,sm_ns0_carry_i_3_n_0,sm_ns0_carry_i_4_n_0}));\n CARRY4 sm_ns0_carry__0\n (.CI(sm_ns0_carry_n_0),\n .CO({NLW_sm_ns0_carry__0_CO_UNCONNECTED[3:2],sm_ns0_carry__0_n_2,sm_ns0_carry__0_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(NLW_sm_ns0_carry__0_O_UNCONNECTED[3:0]),\n .S({1'b0,1'b0,sm_ns0_carry__0_i_1_n_0,sm_ns0_carry__0_i_2_n_0}));\n LUT2 #(\n .INIT(4'h1)) \n sm_ns0_carry__0_i_1\n (.I0(samp_cntr),\n .I1(\\samp_cntr_r_reg_n_0_[15] ),\n .O(sm_ns0_carry__0_i_1_n_0));\n LUT3 #(\n .INIT(8'h01)) \n sm_ns0_carry__0_i_2\n (.I0(\\samp_cntr_r_reg_n_0_[13] ),\n .I1(\\samp_cntr_r_reg_n_0_[14] ),\n .I2(\\samp_cntr_r_reg_n_0_[12] ),\n .O(sm_ns0_carry__0_i_2_n_0));\n LUT3 #(\n .INIT(8'h04)) \n sm_ns0_carry_i_1\n (.I0(\\samp_cntr_r_reg_n_0_[11] ),\n .I1(\\samp_cntr_r_reg_n_0_[9] ),\n .I2(\\samp_cntr_r_reg_n_0_[10] ),\n .O(sm_ns0_carry_i_1_n_0));\n LUT3 #(\n .INIT(8'h01)) \n sm_ns0_carry_i_2\n (.I0(\\samp_cntr_r_reg_n_0_[7] ),\n .I1(\\samp_cntr_r_reg_n_0_[8] ),\n .I2(\\samp_cntr_r_reg_n_0_[6] ),\n .O(sm_ns0_carry_i_2_n_0));\n LUT3 #(\n .INIT(8'h01)) \n sm_ns0_carry_i_3\n (.I0(\\samp_cntr_r_reg_n_0_[4] ),\n .I1(\\samp_cntr_r_reg_n_0_[5] ),\n .I2(\\samp_cntr_r_reg_n_0_[3] ),\n .O(sm_ns0_carry_i_3_n_0));\n LUT3 #(\n .INIT(8'h01)) \n sm_ns0_carry_i_4\n (.I0(\\samp_cntr_r_reg_n_0_[1] ),\n .I1(\\samp_cntr_r_reg_n_0_[2] ),\n .I2(\\samp_cntr_r_reg[0]_0 ),\n .O(sm_ns0_carry_i_4_n_0));\n LUT6 #(\n .INIT(64'h000000002F2A2A2A)) \n \\sm_r[0]_i_1 \n (.I0(\\sm_r_reg[0]_1 ),\n .I1(psdone),\n .I2(\\sm_r_reg[0]_0 ),\n .I3(\\sm_r[0]_i_2_n_0 ),\n .I4(sm_ns0_carry__0_n_2),\n .I5(rstdiv0_sync_r1_reg_rep__20),\n .O(\\sm_r[0]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h0008)) \n \\sm_r[0]_i_2 \n (.I0(poc_sample_pd),\n .I1(\\samp_wait_r_reg[6]_0 ),\n .I2(\\samp_wait_r_reg[7]_0 [5]),\n .I3(\\samp_wait_r_reg[7]_0 [6]),\n .O(\\sm_r[0]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair453\" *) \n LUT4 #(\n .INIT(16'h007A)) \n \\sm_r[1]_i_1 \n (.I0(\\sm_r_reg[0]_1 ),\n .I1(psdone),\n .I2(\\sm_r_reg[0]_0 ),\n .I3(rstdiv0_sync_r1_reg_rep__20),\n .O(\\sm_r[1]_i_1_n_0 ));\n FDRE \\sm_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\sm_r[0]_i_1_n_0 ),\n .Q(\\sm_r_reg[0]_0 ),\n .R(1'b0));\n FDRE \\sm_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\sm_r[1]_i_1_n_0 ),\n .Q(\\sm_r_reg[0]_1 ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair452\" *) \n LUT4 #(\n .INIT(16'h070F)) \n \\tap_r[0]_i_1 \n (.I0(\\rise_lead_r_reg[5] [4]),\n .I1(\\rise_lead_r_reg[5] [5]),\n .I2(\\rise_lead_r_reg[5] [0]),\n .I3(\\rise_lead_r_reg[5] [3]),\n .O(p_0_in[0]));\n (* SOFT_HLUTNM = \"soft_lutpair452\" *) \n LUT5 #(\n .INIT(32'h07700FF0)) \n \\tap_r[1]_i_1 \n (.I0(\\rise_lead_r_reg[5] [4]),\n .I1(\\rise_lead_r_reg[5] [5]),\n .I2(\\rise_lead_r_reg[5] [1]),\n .I3(\\rise_lead_r_reg[5] [0]),\n .I4(\\rise_lead_r_reg[5] [3]),\n .O(p_0_in[1]));\n LUT6 #(\n .INIT(64'h077070700FF0F0F0)) \n \\tap_r[2]_i_1 \n (.I0(\\rise_lead_r_reg[5] [4]),\n .I1(\\rise_lead_r_reg[5] [5]),\n .I2(\\rise_lead_r_reg[5] [2]),\n .I3(\\rise_lead_r_reg[5] [1]),\n .I4(\\rise_lead_r_reg[5] [0]),\n .I5(\\rise_lead_r_reg[5] [3]),\n .O(p_0_in[2]));\n LUT6 #(\n .INIT(64'h0770707070707070)) \n \\tap_r[3]_i_1 \n (.I0(\\rise_lead_r_reg[5] [4]),\n .I1(\\rise_lead_r_reg[5] [5]),\n .I2(\\rise_lead_r_reg[5] [3]),\n .I3(\\rise_lead_r_reg[5] [0]),\n .I4(\\rise_lead_r_reg[5] [1]),\n .I5(\\rise_lead_r_reg[5] [2]),\n .O(p_0_in[3]));\n LUT6 #(\n .INIT(64'h15557FFFC0000000)) \n \\tap_r[4]_i_1 \n (.I0(\\rise_lead_r_reg[5] [5]),\n .I1(\\rise_lead_r_reg[5] [2]),\n .I2(\\rise_lead_r_reg[5] [1]),\n .I3(\\rise_lead_r_reg[5] [0]),\n .I4(\\rise_lead_r_reg[5] [3]),\n .I5(\\rise_lead_r_reg[5] [4]),\n .O(p_0_in[4]));\n LUT2 #(\n .INIT(4'h2)) \n \\tap_r[5]_i_1 \n (.I0(\\sm_r_reg[0]_1 ),\n .I1(\\sm_r_reg[0]_0 ),\n .O(\\tap_r_reg[0]_0 ));\n LUT6 #(\n .INIT(64'h644444444CCCCCCC)) \n \\tap_r[5]_i_2 \n (.I0(\\rise_lead_r_reg[5] [4]),\n .I1(\\rise_lead_r_reg[5] [5]),\n .I2(\\rise_lead_r_reg[5] [2]),\n .I3(\\rise_lead_r_reg[5] [1]),\n .I4(\\rise_lead_r_reg[5] [0]),\n .I5(\\rise_lead_r_reg[5] [3]),\n .O(p_0_in[5]));\n FDRE \\tap_r_reg[0] \n (.C(CLK),\n .CE(\\tap_r_reg[0]_0 ),\n .D(p_0_in[0]),\n .Q(\\rise_lead_r_reg[5] [0]),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE \\tap_r_reg[1] \n (.C(CLK),\n .CE(\\tap_r_reg[0]_0 ),\n .D(p_0_in[1]),\n .Q(\\rise_lead_r_reg[5] [1]),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE \\tap_r_reg[2] \n (.C(CLK),\n .CE(\\tap_r_reg[0]_0 ),\n .D(p_0_in[2]),\n .Q(\\rise_lead_r_reg[5] [2]),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE \\tap_r_reg[3] \n (.C(CLK),\n .CE(\\tap_r_reg[0]_0 ),\n .D(p_0_in[3]),\n .Q(\\rise_lead_r_reg[5] [3]),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE \\tap_r_reg[4] \n (.C(CLK),\n .CE(\\tap_r_reg[0]_0 ),\n .D(p_0_in[4]),\n .Q(\\rise_lead_r_reg[5] [4]),\n .R(rstdiv0_sync_r1_reg_rep));\n FDRE \\tap_r_reg[5] \n (.C(CLK),\n .CE(\\tap_r_reg[0]_0 ),\n .D(p_0_in[5]),\n .Q(\\rise_lead_r_reg[5] [5]),\n .R(rstdiv0_sync_r1_reg_rep));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_poc_top\n (detect_done_r_reg,\n \\sm_r_reg[1] ,\n poc_backup_r_reg,\n Q,\n \\mmcm_init_lead_reg[5] ,\n \\qcntr_r_reg[0] ,\n \\prev_r_reg[0] ,\n \\prev_r_reg[0]_0 ,\n CLK,\n rstdiv0_sync_r1_reg_rep__20,\n ocd_ktap_left_r_reg,\n ocd_ktap_right_r_reg,\n poc_sample_pd,\n use_noise_window,\n pd_out,\n \\run_ends_r_reg[1] ,\n ocd_ktap_left_r_reg_0,\n ocd_edge_detect_rdy_r_reg,\n psdone,\n rstdiv0_sync_r1_reg_rep,\n rstdiv0_sync_r1_reg_rep__0,\n ninety_offsets);\n output detect_done_r_reg;\n output \\sm_r_reg[1] ;\n output poc_backup_r_reg;\n output [5:0]Q;\n output [5:0]\\mmcm_init_lead_reg[5] ;\n output [0:0]\\qcntr_r_reg[0] ;\n output \\prev_r_reg[0] ;\n output \\prev_r_reg[0]_0 ;\n input CLK;\n input rstdiv0_sync_r1_reg_rep__20;\n input ocd_ktap_left_r_reg;\n input ocd_ktap_right_r_reg;\n input poc_sample_pd;\n input use_noise_window;\n input pd_out;\n input \\run_ends_r_reg[1] ;\n input ocd_ktap_left_r_reg_0;\n input ocd_edge_detect_rdy_r_reg;\n input psdone;\n input rstdiv0_sync_r1_reg_rep;\n input rstdiv0_sync_r1_reg_rep__0;\n input [1:0]ninety_offsets;\n\n wire CLK;\n wire [5:0]Q;\n wire center0_return1__0_carry__0_i_4_n_0;\n wire center0_return1__0_carry__0_i_5_n_0;\n wire center0_return1__0_carry__0_i_6_n_0;\n wire center0_return1__0_carry_i_4_n_0;\n wire center0_return1__0_carry_i_5_n_0;\n wire center0_return1__0_carry_i_6_n_0;\n wire center0_return1__1_carry__0_i_4_n_0;\n wire center0_return1__1_carry__0_i_5_n_0;\n wire center0_return1__1_carry_i_4_n_0;\n wire center0_return1__1_carry_i_5_n_0;\n wire center0_return1__1_carry_i_6_n_0;\n wire [7:4]center0_return3;\n wire \\center_diff_r_reg[0]_i_2_n_0 ;\n wire center_return1__0_carry__0_i_2_n_0;\n wire center_return1__0_carry__0_i_3_n_0;\n wire center_return1__0_carry__0_i_4_n_0;\n wire center_return1__0_carry_i_1_n_0;\n wire center_return1__0_carry_i_2_n_0;\n wire center_return1__0_carry_i_3_n_0;\n wire center_return1__1_carry__0_i_2_n_0;\n wire center_return1__1_carry__0_i_3_n_0;\n wire center_return1__1_carry_i_1_n_0;\n wire center_return1__1_carry_i_2_n_0;\n wire center_return1__1_carry_i_3_n_0;\n wire [7:4]center_return3;\n wire detect_done_r_reg;\n wire [5:1]diff;\n wire [0:0]diff_ns00_in;\n wire diff_ns0_carry__0_i_1_n_0;\n wire diff_ns0_carry__0_i_2_n_0;\n wire diff_ns1_carry_i_1_n_0;\n wire diff_ns1_carry_i_2_n_0;\n wire diff_ns1_carry_i_3_n_0;\n wire diff_ns1_carry_i_4_n_0;\n wire diff_ns1_carry_i_5_n_0;\n wire diff_ns1_carry_i_6_n_0;\n wire diff_ns1_carry_i_7_n_0;\n wire [6:0]edge_center;\n wire \\edge_diff_r_reg[0]_i_2_n_0 ;\n wire fall_lead_r0;\n wire i___10_n_0;\n wire i___11_n_0;\n wire i___12_n_0;\n wire i___13_n_0;\n wire i___14_n_0;\n wire i___15_n_0;\n wire i___16_n_0;\n wire i___17_n_0;\n wire i___18_n_0;\n wire i___18_rep_n_0;\n wire i___19_n_0;\n wire i___19_rep_n_0;\n wire i___20_n_0;\n wire i___20_rep__0_n_0;\n wire i___20_rep_n_0;\n wire i___21_n_0;\n wire i___21_rep_n_0;\n wire i___22_n_0;\n wire i___23_n_0;\n wire i___24_n_0;\n wire i___25_n_0;\n wire i___25_rep_n_0;\n wire i___26_n_0;\n wire i___26_rep__0_n_0;\n wire i___26_rep_n_0;\n wire i___27_n_0;\n wire i___28_n_0;\n wire i___29_n_0;\n wire i___30_n_0;\n wire i___31_n_0;\n wire i___32_n_0;\n wire i___33_n_0;\n wire i___34_n_0;\n wire i___34_rep_n_0;\n wire i___35_n_0;\n wire i___35_rep_n_0;\n wire i___36_n_0;\n wire i___36_rep__0_n_0;\n wire i___36_rep_n_0;\n wire i___37_n_0;\n wire i___38_n_0;\n wire i___38_rep_n_0;\n wire i___39_n_0;\n wire i___39_rep_n_0;\n wire i___40_n_0;\n wire i___41_n_0;\n wire i___42_n_0;\n wire i___43_n_0;\n wire i___44_n_0;\n wire i___45_n_0;\n wire i___46_n_0;\n wire i___47_n_0;\n wire i___47_rep_n_0;\n wire i___48_n_0;\n wire i___48_rep__0_n_0;\n wire i___48_rep_n_0;\n wire i___4_n_0;\n wire i___5_n_0;\n wire i___6_n_0;\n wire i___7_n_0;\n wire i___8_n_0;\n wire i___9_n_0;\n wire [5:0]\\mmcm_init_lead_reg[5] ;\n wire [5:0]mod_sub1_return;\n wire [1:0]ninety_offsets;\n wire ocd_edge_detect_rdy_r_reg;\n wire ocd_ktap_left_r_reg;\n wire ocd_ktap_left_r_reg_0;\n wire ocd_ktap_right_r_reg;\n wire [5:1]offset0_return0;\n wire [5:1]offset_return0;\n wire [6:1]p_0_in1_in;\n wire pd_out;\n wire poc_backup_r_reg;\n wire poc_sample_pd;\n wire \\prev_r_reg[0] ;\n wire \\prev_r_reg[0]_0 ;\n wire psdone;\n wire [0:0]\\qcntr_r_reg[0] ;\n wire [5:0]rise_lead_center_0;\n wire \\rise_lead_center_offset_r[5]_i_2_n_0 ;\n wire [5:0]rise_lead_left_0;\n wire [5:0]rise_trail_center_0;\n wire \\rise_trail_center_offset_r[5]_i_2_n_0 ;\n wire [5:0]rise_trail_left_0;\n wire \\rise_trail_r_reg[3]_i_2_n_0 ;\n wire \\rise_trail_r_reg[3]_i_2_n_1 ;\n wire \\rise_trail_r_reg[3]_i_2_n_2 ;\n wire \\rise_trail_r_reg[3]_i_2_n_3 ;\n wire \\rise_trail_r_reg[5]_i_3_n_3 ;\n wire rstdiv0_sync_r1_reg_rep;\n wire rstdiv0_sync_r1_reg_rep__0;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire \\run_ends_r_reg[1] ;\n wire run_polarity_held_r;\n wire [16:1]samp_cntr_ns0;\n wire \\samp_cntr_r_reg[12]_i_2_n_0 ;\n wire \\samp_cntr_r_reg[12]_i_2_n_1 ;\n wire \\samp_cntr_r_reg[12]_i_2_n_2 ;\n wire \\samp_cntr_r_reg[12]_i_2_n_3 ;\n wire \\samp_cntr_r_reg[16]_i_2_n_1 ;\n wire \\samp_cntr_r_reg[16]_i_2_n_2 ;\n wire \\samp_cntr_r_reg[16]_i_2_n_3 ;\n wire \\samp_cntr_r_reg[4]_i_2_n_0 ;\n wire \\samp_cntr_r_reg[4]_i_2_n_1 ;\n wire \\samp_cntr_r_reg[4]_i_2_n_2 ;\n wire \\samp_cntr_r_reg[4]_i_2_n_3 ;\n wire \\samp_cntr_r_reg[8]_i_2_n_0 ;\n wire \\samp_cntr_r_reg[8]_i_2_n_1 ;\n wire \\samp_cntr_r_reg[8]_i_2_n_2 ;\n wire \\samp_cntr_r_reg[8]_i_2_n_3 ;\n wire [7:0]samp_wait_r;\n wire [17:0]samps_hi_ns0;\n wire \\samps_hi_r[3]_i_6_n_0 ;\n wire \\samps_hi_r_reg[11]_i_2_n_0 ;\n wire \\samps_hi_r_reg[11]_i_2_n_1 ;\n wire \\samps_hi_r_reg[11]_i_2_n_2 ;\n wire \\samps_hi_r_reg[11]_i_2_n_3 ;\n wire \\samps_hi_r_reg[15]_i_2_n_0 ;\n wire \\samps_hi_r_reg[15]_i_2_n_1 ;\n wire \\samps_hi_r_reg[15]_i_2_n_2 ;\n wire \\samps_hi_r_reg[15]_i_2_n_3 ;\n wire \\samps_hi_r_reg[17]_i_2_n_3 ;\n wire \\samps_hi_r_reg[3]_i_2_n_0 ;\n wire \\samps_hi_r_reg[3]_i_2_n_1 ;\n wire \\samps_hi_r_reg[3]_i_2_n_2 ;\n wire \\samps_hi_r_reg[3]_i_2_n_3 ;\n wire \\samps_hi_r_reg[7]_i_2_n_0 ;\n wire \\samps_hi_r_reg[7]_i_2_n_1 ;\n wire \\samps_hi_r_reg[7]_i_2_n_2 ;\n wire \\samps_hi_r_reg[7]_i_2_n_3 ;\n wire [17:3]samps_lo;\n wire samps_zero_r0_carry__0_i_10_n_0;\n wire samps_zero_r0_carry__0_i_10_n_1;\n wire samps_zero_r0_carry__0_i_10_n_2;\n wire samps_zero_r0_carry__0_i_10_n_3;\n wire samps_zero_r0_carry__0_i_4_n_0;\n wire samps_zero_r0_carry__0_i_4_n_1;\n wire samps_zero_r0_carry__0_i_4_n_2;\n wire samps_zero_r0_carry__0_i_4_n_3;\n wire samps_zero_r0_carry__0_i_9_n_1;\n wire samps_zero_r0_carry__0_i_9_n_2;\n wire samps_zero_r0_carry__0_i_9_n_3;\n wire samps_zero_r0_carry_i_2_n_0;\n wire samps_zero_r0_carry_i_2_n_1;\n wire samps_zero_r0_carry_i_2_n_2;\n wire samps_zero_r0_carry_i_2_n_3;\n wire \\sm_r_reg[1] ;\n wire [5:0]trailing_edge;\n wire [5:0]trailing_edge0;\n wire [5:0]trailing_edge00_in;\n wire u_edge_left_n_0;\n wire u_edge_left_n_1;\n wire u_edge_left_n_15;\n wire u_edge_left_n_19;\n wire u_edge_left_n_2;\n wire u_edge_left_n_20;\n wire u_edge_left_n_21;\n wire u_edge_left_n_22;\n wire u_edge_left_n_23;\n wire u_edge_left_n_24;\n wire u_edge_left_n_25;\n wire u_edge_left_n_26;\n wire u_edge_left_n_27;\n wire u_edge_left_n_28;\n wire u_edge_left_n_29;\n wire u_edge_left_n_30;\n wire u_edge_left_n_31;\n wire u_edge_left_n_32;\n wire u_edge_left_n_33;\n wire u_edge_left_n_34;\n wire u_edge_right_n_21;\n wire u_edge_right_n_22;\n wire u_edge_right_n_23;\n wire u_edge_right_n_24;\n wire u_edge_right_n_25;\n wire u_edge_right_n_26;\n wire u_edge_right_n_27;\n wire u_edge_right_n_28;\n wire u_edge_right_n_29;\n wire u_edge_right_n_30;\n wire u_edge_right_n_31;\n wire u_edge_right_n_8;\n wire u_poc_meta_n_14;\n wire u_poc_meta_n_15;\n wire u_poc_meta_n_16;\n wire u_poc_meta_n_17;\n wire u_poc_meta_n_18;\n wire u_poc_meta_n_19;\n wire u_poc_meta_n_24;\n wire u_poc_meta_n_25;\n wire u_poc_meta_n_26;\n wire u_poc_meta_n_27;\n wire u_poc_meta_n_28;\n wire u_poc_meta_n_29;\n wire u_poc_meta_n_30;\n wire u_poc_meta_n_31;\n wire u_poc_meta_n_32;\n wire u_poc_meta_n_33;\n wire u_poc_meta_n_34;\n wire u_poc_meta_n_56;\n wire u_poc_meta_n_57;\n wire u_poc_meta_n_58;\n wire u_poc_meta_n_59;\n wire u_poc_meta_n_60;\n wire u_poc_meta_n_61;\n wire u_poc_meta_n_62;\n wire u_poc_meta_n_63;\n wire u_poc_tap_base_n_0;\n wire u_poc_tap_base_n_1;\n wire u_poc_tap_base_n_10;\n wire u_poc_tap_base_n_11;\n wire u_poc_tap_base_n_12;\n wire u_poc_tap_base_n_13;\n wire u_poc_tap_base_n_14;\n wire u_poc_tap_base_n_15;\n wire u_poc_tap_base_n_16;\n wire u_poc_tap_base_n_17;\n wire u_poc_tap_base_n_18;\n wire u_poc_tap_base_n_19;\n wire u_poc_tap_base_n_2;\n wire u_poc_tap_base_n_20;\n wire u_poc_tap_base_n_21;\n wire u_poc_tap_base_n_22;\n wire u_poc_tap_base_n_23;\n wire u_poc_tap_base_n_24;\n wire u_poc_tap_base_n_25;\n wire u_poc_tap_base_n_26;\n wire u_poc_tap_base_n_27;\n wire u_poc_tap_base_n_28;\n wire u_poc_tap_base_n_29;\n wire u_poc_tap_base_n_3;\n wire u_poc_tap_base_n_30;\n wire u_poc_tap_base_n_31;\n wire u_poc_tap_base_n_32;\n wire u_poc_tap_base_n_33;\n wire u_poc_tap_base_n_34;\n wire u_poc_tap_base_n_35;\n wire u_poc_tap_base_n_36;\n wire u_poc_tap_base_n_37;\n wire u_poc_tap_base_n_38;\n wire u_poc_tap_base_n_39;\n wire u_poc_tap_base_n_4;\n wire u_poc_tap_base_n_40;\n wire u_poc_tap_base_n_41;\n wire u_poc_tap_base_n_42;\n wire u_poc_tap_base_n_43;\n wire u_poc_tap_base_n_44;\n wire u_poc_tap_base_n_45;\n wire u_poc_tap_base_n_46;\n wire u_poc_tap_base_n_47;\n wire u_poc_tap_base_n_48;\n wire u_poc_tap_base_n_49;\n wire u_poc_tap_base_n_5;\n wire u_poc_tap_base_n_50;\n wire u_poc_tap_base_n_51;\n wire u_poc_tap_base_n_52;\n wire u_poc_tap_base_n_53;\n wire u_poc_tap_base_n_54;\n wire u_poc_tap_base_n_55;\n wire u_poc_tap_base_n_57;\n wire u_poc_tap_base_n_58;\n wire u_poc_tap_base_n_59;\n wire u_poc_tap_base_n_6;\n wire u_poc_tap_base_n_60;\n wire u_poc_tap_base_n_61;\n wire u_poc_tap_base_n_62;\n wire u_poc_tap_base_n_63;\n wire u_poc_tap_base_n_64;\n wire u_poc_tap_base_n_65;\n wire u_poc_tap_base_n_66;\n wire u_poc_tap_base_n_67;\n wire u_poc_tap_base_n_68;\n wire u_poc_tap_base_n_69;\n wire u_poc_tap_base_n_7;\n wire u_poc_tap_base_n_70;\n wire u_poc_tap_base_n_71;\n wire u_poc_tap_base_n_72;\n wire u_poc_tap_base_n_73;\n wire u_poc_tap_base_n_74;\n wire u_poc_tap_base_n_75;\n wire u_poc_tap_base_n_76;\n wire u_poc_tap_base_n_8;\n wire u_poc_tap_base_n_83;\n wire u_poc_tap_base_n_84;\n wire u_poc_tap_base_n_85;\n wire u_poc_tap_base_n_86;\n wire u_poc_tap_base_n_9;\n wire u_poc_tap_base_n_95;\n wire use_noise_window;\n wire [6:0]window_center;\n wire [3:1]\\NLW_rise_trail_r_reg[5]_i_3_CO_UNCONNECTED ;\n wire [3:2]\\NLW_rise_trail_r_reg[5]_i_3_O_UNCONNECTED ;\n wire [3:3]\\NLW_samp_cntr_r_reg[16]_i_2_CO_UNCONNECTED ;\n wire [3:1]\\NLW_samps_hi_r_reg[17]_i_2_CO_UNCONNECTED ;\n wire [3:2]\\NLW_samps_hi_r_reg[17]_i_2_O_UNCONNECTED ;\n wire [3:3]NLW_samps_zero_r0_carry__0_i_9_CO_UNCONNECTED;\n wire [0:0]NLW_samps_zero_r0_carry_i_2_O_UNCONNECTED;\n\n LUT6 #(\n .INIT(64'h1555FFFFEAAA0000)) \n center0_return1__0_carry__0_i_4\n (.I0(center0_return3[7]),\n .I1(center0_return3[4]),\n .I2(center0_return3[5]),\n .I3(center0_return3[6]),\n .I4(u_poc_meta_n_60),\n .I5(center0_return1__0_carry__0_i_6_n_0),\n .O(center0_return1__0_carry__0_i_4_n_0));\n LUT6 #(\n .INIT(64'hA999999956666666)) \n center0_return1__0_carry__0_i_5\n (.I0(u_poc_meta_n_60),\n .I1(center0_return3[7]),\n .I2(center0_return3[4]),\n .I3(center0_return3[5]),\n .I4(center0_return3[6]),\n .I5(u_edge_left_n_1),\n .O(center0_return1__0_carry__0_i_5_n_0));\n LUT4 #(\n .INIT(16'h1DE2)) \n center0_return1__0_carry__0_i_6\n (.I0(rise_trail_left_0[4]),\n .I1(use_noise_window),\n .I2(rise_lead_left_0[4]),\n .I3(u_poc_meta_n_59),\n .O(center0_return1__0_carry__0_i_6_n_0));\n LUT4 #(\n .INIT(16'h1DE2)) \n center0_return1__0_carry_i_4\n (.I0(rise_trail_left_0[2]),\n .I1(use_noise_window),\n .I2(rise_lead_left_0[2]),\n .I3(u_poc_meta_n_61),\n .O(center0_return1__0_carry_i_4_n_0));\n LUT4 #(\n .INIT(16'h1DE2)) \n center0_return1__0_carry_i_5\n (.I0(rise_trail_left_0[1]),\n .I1(use_noise_window),\n .I2(rise_lead_left_0[1]),\n .I3(u_poc_meta_n_62),\n .O(center0_return1__0_carry_i_5_n_0));\n LUT4 #(\n .INIT(16'h1DE2)) \n center0_return1__0_carry_i_6\n (.I0(rise_trail_left_0[0]),\n .I1(use_noise_window),\n .I2(rise_lead_left_0[0]),\n .I3(u_poc_meta_n_63),\n .O(center0_return1__0_carry_i_6_n_0));\n LUT4 #(\n .INIT(16'h1DE2)) \n center0_return1__1_carry__0_i_4\n (.I0(rise_trail_left_0[4]),\n .I1(use_noise_window),\n .I2(rise_lead_left_0[4]),\n .I3(u_poc_meta_n_59),\n .O(center0_return1__1_carry__0_i_4_n_0));\n LUT4 #(\n .INIT(16'h1DE2)) \n center0_return1__1_carry__0_i_5\n (.I0(rise_trail_left_0[3]),\n .I1(use_noise_window),\n .I2(rise_lead_left_0[3]),\n .I3(u_poc_meta_n_60),\n .O(center0_return1__1_carry__0_i_5_n_0));\n LUT4 #(\n .INIT(16'h1DE2)) \n center0_return1__1_carry_i_4\n (.I0(rise_trail_left_0[2]),\n .I1(use_noise_window),\n .I2(rise_lead_left_0[2]),\n .I3(u_poc_meta_n_61),\n .O(center0_return1__1_carry_i_4_n_0));\n LUT4 #(\n .INIT(16'h1DE2)) \n center0_return1__1_carry_i_5\n (.I0(rise_trail_left_0[1]),\n .I1(use_noise_window),\n .I2(rise_lead_left_0[1]),\n .I3(u_poc_meta_n_62),\n .O(center0_return1__1_carry_i_5_n_0));\n LUT4 #(\n .INIT(16'h1DE2)) \n center0_return1__1_carry_i_6\n (.I0(rise_trail_left_0[0]),\n .I1(use_noise_window),\n .I2(rise_lead_left_0[0]),\n .I3(u_poc_meta_n_63),\n .O(center0_return1__1_carry_i_6_n_0));\n LUT1 #(\n .INIT(2'h1)) \n \\center_diff_r_reg[0]_i_2 \n (.I0(i___20_n_0),\n .O(\\center_diff_r_reg[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h007FFFFFFF800000)) \n center_return1__0_carry__0_i_2\n (.I0(center_return3[5]),\n .I1(center_return3[4]),\n .I2(center_return3[6]),\n .I3(center_return3[7]),\n .I4(diff[4]),\n .I5(center_return1__0_carry__0_i_4_n_0),\n .O(center_return1__0_carry__0_i_2_n_0));\n LUT6 #(\n .INIT(64'hAAAA955555556AAA)) \n center_return1__0_carry__0_i_3\n (.I0(diff[4]),\n .I1(center_return3[5]),\n .I2(center_return3[4]),\n .I3(center_return3[6]),\n .I4(center_return3[7]),\n .I5(p_0_in1_in[4]),\n .O(center_return1__0_carry__0_i_3_n_0));\n LUT2 #(\n .INIT(4'h6)) \n center_return1__0_carry__0_i_4\n (.I0(p_0_in1_in[5]),\n .I1(diff[5]),\n .O(center_return1__0_carry__0_i_4_n_0));\n LUT2 #(\n .INIT(4'h6)) \n center_return1__0_carry_i_1\n (.I0(p_0_in1_in[3]),\n .I1(diff[3]),\n .O(center_return1__0_carry_i_1_n_0));\n LUT2 #(\n .INIT(4'h6)) \n center_return1__0_carry_i_2\n (.I0(p_0_in1_in[2]),\n .I1(diff[2]),\n .O(center_return1__0_carry_i_2_n_0));\n LUT2 #(\n .INIT(4'h6)) \n center_return1__0_carry_i_3\n (.I0(p_0_in1_in[1]),\n .I1(diff[1]),\n .O(center_return1__0_carry_i_3_n_0));\n LUT2 #(\n .INIT(4'h6)) \n center_return1__1_carry__0_i_2\n (.I0(p_0_in1_in[5]),\n .I1(diff[5]),\n .O(center_return1__1_carry__0_i_2_n_0));\n LUT2 #(\n .INIT(4'h6)) \n center_return1__1_carry__0_i_3\n (.I0(p_0_in1_in[4]),\n .I1(diff[4]),\n .O(center_return1__1_carry__0_i_3_n_0));\n LUT2 #(\n .INIT(4'h6)) \n center_return1__1_carry_i_1\n (.I0(p_0_in1_in[3]),\n .I1(diff[3]),\n .O(center_return1__1_carry_i_1_n_0));\n LUT2 #(\n .INIT(4'h6)) \n center_return1__1_carry_i_2\n (.I0(p_0_in1_in[2]),\n .I1(diff[2]),\n .O(center_return1__1_carry_i_2_n_0));\n LUT2 #(\n .INIT(4'h6)) \n center_return1__1_carry_i_3\n (.I0(p_0_in1_in[1]),\n .I1(diff[1]),\n .O(center_return1__1_carry_i_3_n_0));\n LUT2 #(\n .INIT(4'h6)) \n diff_ns0_carry__0_i_1\n (.I0(window_center[5]),\n .I1(edge_center[5]),\n .O(diff_ns0_carry__0_i_1_n_0));\n LUT2 #(\n .INIT(4'h6)) \n diff_ns0_carry__0_i_2\n (.I0(edge_center[4]),\n .I1(window_center[4]),\n .O(diff_ns0_carry__0_i_2_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n diff_ns1_carry_i_1\n (.I0(edge_center[4]),\n .I1(window_center[4]),\n .I2(window_center[5]),\n .I3(edge_center[5]),\n .O(diff_ns1_carry_i_1_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n diff_ns1_carry_i_2\n (.I0(edge_center[2]),\n .I1(window_center[2]),\n .I2(window_center[3]),\n .I3(edge_center[3]),\n .O(diff_ns1_carry_i_2_n_0));\n LUT4 #(\n .INIT(16'h2F02)) \n diff_ns1_carry_i_3\n (.I0(edge_center[0]),\n .I1(window_center[0]),\n .I2(window_center[1]),\n .I3(edge_center[1]),\n .O(diff_ns1_carry_i_3_n_0));\n LUT2 #(\n .INIT(4'h9)) \n diff_ns1_carry_i_4\n (.I0(window_center[6]),\n .I1(edge_center[6]),\n .O(diff_ns1_carry_i_4_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n diff_ns1_carry_i_5\n (.I0(edge_center[4]),\n .I1(window_center[4]),\n .I2(edge_center[5]),\n .I3(window_center[5]),\n .O(diff_ns1_carry_i_5_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n diff_ns1_carry_i_6\n (.I0(edge_center[2]),\n .I1(window_center[2]),\n .I2(edge_center[3]),\n .I3(window_center[3]),\n .O(diff_ns1_carry_i_6_n_0));\n LUT4 #(\n .INIT(16'h9009)) \n diff_ns1_carry_i_7\n (.I0(edge_center[0]),\n .I1(window_center[0]),\n .I2(edge_center[1]),\n .I3(window_center[1]),\n .O(diff_ns1_carry_i_7_n_0));\n LUT1 #(\n .INIT(2'h1)) \n \\diff_r_reg[0]_i_2 \n (.I0(i___48_n_0),\n .O(diff_ns00_in));\n LUT1 #(\n .INIT(2'h1)) \n \\edge_diff_r_reg[0]_i_2 \n (.I0(i___36_n_0),\n .O(\\edge_diff_r_reg[0]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFF8888F)) \n i___10\n (.I0(u_poc_tap_base_n_55),\n .I1(u_poc_tap_base_n_54),\n .I2(samp_wait_r[0]),\n .I3(samp_wait_r[1]),\n .I4(samp_wait_r[2]),\n .O(i___10_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFF88888888F)) \n i___11\n (.I0(u_poc_tap_base_n_55),\n .I1(u_poc_tap_base_n_54),\n .I2(samp_wait_r[2]),\n .I3(samp_wait_r[1]),\n .I4(samp_wait_r[0]),\n .I5(samp_wait_r[3]),\n .O(i___11_n_0));\n LUT6 #(\n .INIT(64'h5555555500000040)) \n i___12\n (.I0(u_poc_tap_base_n_54),\n .I1(poc_sample_pd),\n .I2(u_poc_tap_base_n_86),\n .I3(samp_wait_r[6]),\n .I4(samp_wait_r[7]),\n .I5(u_poc_tap_base_n_55),\n .O(i___12_n_0));\n LUT5 #(\n .INIT(32'h00000001)) \n i___13\n (.I0(samp_wait_r[4]),\n .I1(samp_wait_r[2]),\n .I2(samp_wait_r[1]),\n .I3(samp_wait_r[0]),\n .I4(samp_wait_r[3]),\n .O(i___13_n_0));\n LUT5 #(\n .INIT(32'hA8888888)) \n i___14\n (.I0(diff[4]),\n .I1(center_return3[7]),\n .I2(center_return3[6]),\n .I3(center_return3[4]),\n .I4(center_return3[5]),\n .O(i___14_n_0));\n LUT6 #(\n .INIT(64'h478B74B8B8748B47)) \n i___15\n (.I0(rise_lead_left_0[4]),\n .I1(use_noise_window),\n .I2(rise_trail_left_0[4]),\n .I3(Q[4]),\n .I4(\\mmcm_init_lead_reg[5] [4]),\n .I5(u_edge_left_n_1),\n .O(i___15_n_0));\n LUT5 #(\n .INIT(32'hCCA533A5)) \n i___16\n (.I0(\\mmcm_init_lead_reg[5] [4]),\n .I1(Q[4]),\n .I2(rise_trail_left_0[4]),\n .I3(use_noise_window),\n .I4(rise_lead_left_0[4]),\n .O(i___16_n_0));\n LUT5 #(\n .INIT(32'hCCA533A5)) \n i___17\n (.I0(\\mmcm_init_lead_reg[5] [3]),\n .I1(Q[3]),\n .I2(rise_trail_left_0[3]),\n .I3(use_noise_window),\n .I4(rise_lead_left_0[3]),\n .O(i___17_n_0));\n LUT5 #(\n .INIT(32'hCCA533A5)) \n i___18\n (.I0(\\mmcm_init_lead_reg[5] [2]),\n .I1(Q[2]),\n .I2(rise_trail_left_0[2]),\n .I3(use_noise_window),\n .I4(rise_lead_left_0[2]),\n .O(i___18_n_0));\n LUT5 #(\n .INIT(32'hCCA533A5)) \n i___18_rep\n (.I0(\\mmcm_init_lead_reg[5] [2]),\n .I1(Q[2]),\n .I2(rise_trail_left_0[2]),\n .I3(use_noise_window),\n .I4(rise_lead_left_0[2]),\n .O(i___18_rep_n_0));\n LUT5 #(\n .INIT(32'hCCA533A5)) \n i___19\n (.I0(\\mmcm_init_lead_reg[5] [1]),\n .I1(Q[1]),\n .I2(rise_trail_left_0[1]),\n .I3(use_noise_window),\n .I4(rise_lead_left_0[1]),\n .O(i___19_n_0));\n LUT5 #(\n .INIT(32'hCCA533A5)) \n i___19_rep\n (.I0(\\mmcm_init_lead_reg[5] [1]),\n .I1(Q[1]),\n .I2(rise_trail_left_0[1]),\n .I3(use_noise_window),\n .I4(rise_lead_left_0[1]),\n .O(i___19_rep_n_0));\n LUT5 #(\n .INIT(32'hCCA533A5)) \n i___20\n (.I0(\\mmcm_init_lead_reg[5] [0]),\n .I1(Q[0]),\n .I2(rise_trail_left_0[0]),\n .I3(use_noise_window),\n .I4(rise_lead_left_0[0]),\n .O(i___20_n_0));\n LUT5 #(\n .INIT(32'hCCA533A5)) \n i___20_rep\n (.I0(\\mmcm_init_lead_reg[5] [0]),\n .I1(Q[0]),\n .I2(rise_trail_left_0[0]),\n .I3(use_noise_window),\n .I4(rise_lead_left_0[0]),\n .O(i___20_rep_n_0));\n LUT5 #(\n .INIT(32'hCCA533A5)) \n i___20_rep__0\n (.I0(\\mmcm_init_lead_reg[5] [0]),\n .I1(Q[0]),\n .I2(rise_trail_left_0[0]),\n .I3(use_noise_window),\n .I4(rise_lead_left_0[0]),\n .O(i___20_rep__0_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___21\n (.I0(u_poc_tap_base_n_60),\n .I1(u_poc_tap_base_n_49),\n .O(i___21_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___21_rep\n (.I0(u_poc_tap_base_n_60),\n .I1(u_poc_tap_base_n_49),\n .O(i___21_rep_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___22\n (.I0(u_poc_tap_base_n_59),\n .I1(u_poc_tap_base_n_48),\n .O(i___22_n_0));\n LUT3 #(\n .INIT(8'h69)) \n i___23\n (.I0(u_poc_tap_base_n_47),\n .I1(u_poc_tap_base_n_58),\n .I2(u_poc_tap_base_n_48),\n .O(i___23_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___24\n (.I0(u_poc_tap_base_n_58),\n .I1(u_poc_tap_base_n_47),\n .O(i___24_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___25\n (.I0(u_poc_tap_base_n_61),\n .I1(u_poc_tap_base_n_50),\n .O(i___25_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___25_rep\n (.I0(u_poc_tap_base_n_61),\n .I1(u_poc_tap_base_n_50),\n .O(i___25_rep_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair478\" *) \n LUT2 #(\n .INIT(4'h9)) \n i___26\n (.I0(u_poc_tap_base_n_62),\n .I1(u_poc_tap_base_n_51),\n .O(i___26_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___26_rep\n (.I0(u_poc_tap_base_n_62),\n .I1(u_poc_tap_base_n_51),\n .O(i___26_rep_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___26_rep__0\n (.I0(u_poc_tap_base_n_62),\n .I1(u_poc_tap_base_n_51),\n .O(i___26_rep__0_n_0));\n LUT2 #(\n .INIT(4'h6)) \n i___27\n (.I0(u_poc_tap_base_n_7),\n .I1(u_poc_tap_base_n_6),\n .O(i___27_n_0));\n LUT2 #(\n .INIT(4'h6)) \n i___28\n (.I0(u_poc_tap_base_n_5),\n .I1(u_poc_tap_base_n_4),\n .O(i___28_n_0));\n LUT4 #(\n .INIT(16'hD22D)) \n i___29\n (.I0(p_0_in1_in[5]),\n .I1(u_poc_meta_n_15),\n .I2(p_0_in1_in[6]),\n .I3(u_poc_meta_n_14),\n .O(i___29_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___30\n (.I0(u_poc_meta_n_14),\n .I1(p_0_in1_in[6]),\n .O(i___30_n_0));\n LUT3 #(\n .INIT(8'h69)) \n i___31\n (.I0(p_0_in1_in[5]),\n .I1(u_poc_meta_n_15),\n .I2(p_0_in1_in[4]),\n .O(i___31_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___32\n (.I0(u_poc_meta_n_15),\n .I1(p_0_in1_in[5]),\n .O(i___32_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___33\n (.I0(u_poc_meta_n_16),\n .I1(p_0_in1_in[4]),\n .O(i___33_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___34\n (.I0(u_poc_meta_n_17),\n .I1(p_0_in1_in[3]),\n .O(i___34_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___34_rep\n (.I0(u_poc_meta_n_17),\n .I1(p_0_in1_in[3]),\n .O(i___34_rep_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___35\n (.I0(u_poc_meta_n_18),\n .I1(p_0_in1_in[2]),\n .O(i___35_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___35_rep\n (.I0(u_poc_meta_n_18),\n .I1(p_0_in1_in[2]),\n .O(i___35_rep_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___36\n (.I0(u_poc_meta_n_19),\n .I1(p_0_in1_in[1]),\n .O(i___36_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___36_rep\n (.I0(u_poc_meta_n_19),\n .I1(p_0_in1_in[1]),\n .O(i___36_rep_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___36_rep__0\n (.I0(u_poc_meta_n_19),\n .I1(p_0_in1_in[1]),\n .O(i___36_rep__0_n_0));\n LUT4 #(\n .INIT(16'hD22D)) \n i___37\n (.I0(window_center[5]),\n .I1(edge_center[5]),\n .I2(window_center[6]),\n .I3(edge_center[6]),\n .O(i___37_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___38\n (.I0(edge_center[2]),\n .I1(window_center[2]),\n .O(i___38_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___38_rep\n (.I0(edge_center[2]),\n .I1(window_center[2]),\n .O(i___38_rep_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___39\n (.I0(edge_center[1]),\n .I1(window_center[1]),\n .O(i___39_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___39_rep\n (.I0(edge_center[1]),\n .I1(window_center[1]),\n .O(i___39_rep_n_0));\n LUT6 #(\n .INIT(64'hFFFFCFFF00008800)) \n i___4\n (.I0(u_poc_tap_base_n_2),\n .I1(u_poc_tap_base_n_0),\n .I2(u_poc_tap_base_n_3),\n .I3(u_poc_tap_base_n_46),\n .I4(rstdiv0_sync_r1_reg_rep__20),\n .I5(run_polarity_held_r),\n .O(i___4_n_0));\n LUT2 #(\n .INIT(4'h2)) \n i___40\n (.I0(window_center[6]),\n .I1(edge_center[6]),\n .O(i___40_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___41\n (.I0(edge_center[6]),\n .I1(window_center[6]),\n .O(i___41_n_0));\n LUT2 #(\n .INIT(4'h2)) \n i___42\n (.I0(edge_center[6]),\n .I1(window_center[6]),\n .O(i___42_n_0));\n LUT3 #(\n .INIT(8'h69)) \n i___43\n (.I0(window_center[5]),\n .I1(edge_center[5]),\n .I2(window_center[4]),\n .O(i___43_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___44\n (.I0(edge_center[5]),\n .I1(window_center[5]),\n .O(i___44_n_0));\n LUT2 #(\n .INIT(4'hB)) \n i___45\n (.I0(edge_center[5]),\n .I1(window_center[5]),\n .O(i___45_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___46\n (.I0(edge_center[4]),\n .I1(window_center[4]),\n .O(i___46_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___47\n (.I0(edge_center[3]),\n .I1(window_center[3]),\n .O(i___47_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___47_rep\n (.I0(edge_center[3]),\n .I1(window_center[3]),\n .O(i___47_rep_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___48\n (.I0(edge_center[0]),\n .I1(window_center[0]),\n .O(i___48_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___48_rep\n (.I0(edge_center[0]),\n .I1(window_center[0]),\n .O(i___48_rep_n_0));\n LUT2 #(\n .INIT(4'h9)) \n i___48_rep__0\n (.I0(edge_center[0]),\n .I1(window_center[0]),\n .O(i___48_rep__0_n_0));\n LUT5 #(\n .INIT(32'h00400000)) \n i___5\n (.I0(u_poc_tap_base_n_0),\n .I1(u_poc_tap_base_n_3),\n .I2(u_poc_tap_base_n_46),\n .I3(rstdiv0_sync_r1_reg_rep__20),\n .I4(ocd_ktap_right_r_reg),\n .O(i___5_n_0));\n LUT5 #(\n .INIT(32'h00400000)) \n i___6\n (.I0(u_poc_tap_base_n_0),\n .I1(u_poc_tap_base_n_3),\n .I2(u_poc_tap_base_n_46),\n .I3(rstdiv0_sync_r1_reg_rep__20),\n .I4(ocd_ktap_left_r_reg),\n .O(i___6_n_0));\n LUT4 #(\n .INIT(16'h0004)) \n i___7\n (.I0(u_poc_tap_base_n_0),\n .I1(u_poc_tap_base_n_52),\n .I2(ocd_ktap_left_r_reg),\n .I3(ocd_ktap_right_r_reg),\n .O(i___7_n_0));\n LUT3 #(\n .INIT(8'h01)) \n i___8\n (.I0(u_poc_meta_n_56),\n .I1(u_poc_meta_n_58),\n .I2(u_poc_meta_n_57),\n .O(i___8_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair478\" *) \n LUT4 #(\n .INIT(16'h7FFF)) \n i___9\n (.I0(u_poc_tap_base_n_49),\n .I1(u_poc_tap_base_n_50),\n .I2(u_poc_tap_base_n_51),\n .I3(u_poc_tap_base_n_48),\n .O(i___9_n_0));\n (* SOFT_HLUTNM = \"soft_lutpair481\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\rise_lead_center_offset_r[1]_i_1 \n (.I0(rise_lead_center_0[1]),\n .I1(ninety_offsets[0]),\n .O(offset_return0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair479\" *) \n LUT4 #(\n .INIT(16'h4BB4)) \n \\rise_lead_center_offset_r[2]_i_1 \n (.I0(rise_lead_center_0[1]),\n .I1(ninety_offsets[0]),\n .I2(ninety_offsets[1]),\n .I3(rise_lead_center_0[2]),\n .O(offset_return0[2]));\n LUT6 #(\n .INIT(64'h5A4969254969925A)) \n \\rise_lead_center_offset_r[3]_i_1 \n (.I0(rise_lead_center_0[3]),\n .I1(rise_lead_center_0[5]),\n .I2(\\rise_lead_center_offset_r[5]_i_2_n_0 ),\n .I3(rise_lead_center_0[4]),\n .I4(ninety_offsets[1]),\n .I5(ninety_offsets[0]),\n .O(offset_return0[3]));\n LUT6 #(\n .INIT(64'h998564666466621A)) \n \\rise_lead_center_offset_r[4]_i_1 \n (.I0(rise_lead_center_0[4]),\n .I1(ninety_offsets[0]),\n .I2(ninety_offsets[1]),\n .I3(rise_lead_center_0[5]),\n .I4(rise_lead_center_0[3]),\n .I5(\\rise_lead_center_offset_r[5]_i_2_n_0 ),\n .O(offset_return0[4]));\n LUT6 #(\n .INIT(64'hF00E871887700EF0)) \n \\rise_lead_center_offset_r[5]_i_1 \n (.I0(rise_lead_center_0[3]),\n .I1(\\rise_lead_center_offset_r[5]_i_2_n_0 ),\n .I2(rise_lead_center_0[5]),\n .I3(ninety_offsets[1]),\n .I4(ninety_offsets[0]),\n .I5(rise_lead_center_0[4]),\n .O(offset_return0[5]));\n (* SOFT_HLUTNM = \"soft_lutpair479\" *) \n LUT4 #(\n .INIT(16'hE460)) \n \\rise_lead_center_offset_r[5]_i_2 \n (.I0(ninety_offsets[1]),\n .I1(ninety_offsets[0]),\n .I2(rise_lead_center_0[2]),\n .I3(rise_lead_center_0[1]),\n .O(\\rise_lead_center_offset_r[5]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair481\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\rise_trail_center_offset_r[1]_i_1 \n (.I0(rise_trail_center_0[1]),\n .I1(ninety_offsets[0]),\n .O(offset0_return0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair480\" *) \n LUT4 #(\n .INIT(16'h4BB4)) \n \\rise_trail_center_offset_r[2]_i_1 \n (.I0(rise_trail_center_0[1]),\n .I1(ninety_offsets[0]),\n .I2(ninety_offsets[1]),\n .I3(rise_trail_center_0[2]),\n .O(offset0_return0[2]));\n LUT6 #(\n .INIT(64'h5A4969254969925A)) \n \\rise_trail_center_offset_r[3]_i_1 \n (.I0(rise_trail_center_0[3]),\n .I1(rise_trail_center_0[5]),\n .I2(\\rise_trail_center_offset_r[5]_i_2_n_0 ),\n .I3(rise_trail_center_0[4]),\n .I4(ninety_offsets[1]),\n .I5(ninety_offsets[0]),\n .O(offset0_return0[3]));\n LUT6 #(\n .INIT(64'h998564666466621A)) \n \\rise_trail_center_offset_r[4]_i_1 \n (.I0(rise_trail_center_0[4]),\n .I1(ninety_offsets[0]),\n .I2(ninety_offsets[1]),\n .I3(rise_trail_center_0[5]),\n .I4(rise_trail_center_0[3]),\n .I5(\\rise_trail_center_offset_r[5]_i_2_n_0 ),\n .O(offset0_return0[4]));\n LUT6 #(\n .INIT(64'hF00E871887700EF0)) \n \\rise_trail_center_offset_r[5]_i_1 \n (.I0(rise_trail_center_0[3]),\n .I1(\\rise_trail_center_offset_r[5]_i_2_n_0 ),\n .I2(rise_trail_center_0[5]),\n .I3(ninety_offsets[1]),\n .I4(ninety_offsets[0]),\n .I5(rise_trail_center_0[4]),\n .O(offset0_return0[5]));\n (* SOFT_HLUTNM = \"soft_lutpair480\" *) \n LUT4 #(\n .INIT(16'hE460)) \n \\rise_trail_center_offset_r[5]_i_2 \n (.I0(ninety_offsets[1]),\n .I1(ninety_offsets[0]),\n .I2(rise_trail_center_0[2]),\n .I3(rise_trail_center_0[1]),\n .O(\\rise_trail_center_offset_r[5]_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\rise_trail_r_reg[0]_i_2 \n (.I0(i___26_n_0),\n .O(trailing_edge00_in[0]));\n CARRY4 \\rise_trail_r_reg[3]_i_2 \n (.CI(1'b0),\n .CO({\\rise_trail_r_reg[3]_i_2_n_0 ,\\rise_trail_r_reg[3]_i_2_n_1 ,\\rise_trail_r_reg[3]_i_2_n_2 ,\\rise_trail_r_reg[3]_i_2_n_3 }),\n .CYINIT(1'b1),\n .DI({u_poc_tap_base_n_59,u_poc_tap_base_n_60,u_poc_tap_base_n_61,u_poc_tap_base_n_62}),\n .O(trailing_edge0[3:0]),\n .S({i___22_n_0,i___21_rep_n_0,i___25_rep_n_0,i___26_rep_n_0}));\n CARRY4 \\rise_trail_r_reg[5]_i_3 \n (.CI(\\rise_trail_r_reg[3]_i_2_n_0 ),\n .CO({\\NLW_rise_trail_r_reg[5]_i_3_CO_UNCONNECTED [3:1],\\rise_trail_r_reg[5]_i_3_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,u_poc_tap_base_n_58}),\n .O({\\NLW_rise_trail_r_reg[5]_i_3_O_UNCONNECTED [3:2],trailing_edge0[5:4]}),\n .S({1'b0,1'b0,u_poc_tap_base_n_84,i___24_n_0}));\n CARRY4 \\samp_cntr_r_reg[12]_i_2 \n (.CI(\\samp_cntr_r_reg[8]_i_2_n_0 ),\n .CO({\\samp_cntr_r_reg[12]_i_2_n_0 ,\\samp_cntr_r_reg[12]_i_2_n_1 ,\\samp_cntr_r_reg[12]_i_2_n_2 ,\\samp_cntr_r_reg[12]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(samp_cntr_ns0[12:9]),\n .S({u_poc_tap_base_n_17,u_poc_tap_base_n_18,u_poc_tap_base_n_19,u_poc_tap_base_n_20}));\n CARRY4 \\samp_cntr_r_reg[16]_i_2 \n (.CI(\\samp_cntr_r_reg[12]_i_2_n_0 ),\n .CO({\\NLW_samp_cntr_r_reg[16]_i_2_CO_UNCONNECTED [3],\\samp_cntr_r_reg[16]_i_2_n_1 ,\\samp_cntr_r_reg[16]_i_2_n_2 ,\\samp_cntr_r_reg[16]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(samp_cntr_ns0[16:13]),\n .S({u_poc_tap_base_n_21,u_poc_tap_base_n_22,u_poc_tap_base_n_23,u_poc_tap_base_n_24}));\n CARRY4 \\samp_cntr_r_reg[4]_i_2 \n (.CI(1'b0),\n .CO({\\samp_cntr_r_reg[4]_i_2_n_0 ,\\samp_cntr_r_reg[4]_i_2_n_1 ,\\samp_cntr_r_reg[4]_i_2_n_2 ,\\samp_cntr_r_reg[4]_i_2_n_3 }),\n .CYINIT(u_poc_tap_base_n_76),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(samp_cntr_ns0[4:1]),\n .S({u_poc_tap_base_n_9,u_poc_tap_base_n_10,u_poc_tap_base_n_11,u_poc_tap_base_n_12}));\n CARRY4 \\samp_cntr_r_reg[8]_i_2 \n (.CI(\\samp_cntr_r_reg[4]_i_2_n_0 ),\n .CO({\\samp_cntr_r_reg[8]_i_2_n_0 ,\\samp_cntr_r_reg[8]_i_2_n_1 ,\\samp_cntr_r_reg[8]_i_2_n_2 ,\\samp_cntr_r_reg[8]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(samp_cntr_ns0[8:5]),\n .S({u_poc_tap_base_n_13,u_poc_tap_base_n_14,u_poc_tap_base_n_15,u_poc_tap_base_n_16}));\n LUT2 #(\n .INIT(4'h6)) \n \\samps_hi_r[3]_i_6 \n (.I0(u_poc_tap_base_n_8),\n .I1(pd_out),\n .O(\\samps_hi_r[3]_i_6_n_0 ));\n CARRY4 \\samps_hi_r_reg[11]_i_2 \n (.CI(\\samps_hi_r_reg[7]_i_2_n_0 ),\n .CO({\\samps_hi_r_reg[11]_i_2_n_0 ,\\samps_hi_r_reg[11]_i_2_n_1 ,\\samps_hi_r_reg[11]_i_2_n_2 ,\\samps_hi_r_reg[11]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(samps_hi_ns0[11:8]),\n .S({u_poc_tap_base_n_32,u_poc_tap_base_n_33,u_poc_tap_base_n_34,u_poc_tap_base_n_35}));\n CARRY4 \\samps_hi_r_reg[15]_i_2 \n (.CI(\\samps_hi_r_reg[11]_i_2_n_0 ),\n .CO({\\samps_hi_r_reg[15]_i_2_n_0 ,\\samps_hi_r_reg[15]_i_2_n_1 ,\\samps_hi_r_reg[15]_i_2_n_2 ,\\samps_hi_r_reg[15]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(samps_hi_ns0[15:12]),\n .S({u_poc_tap_base_n_36,u_poc_tap_base_n_37,u_poc_tap_base_n_38,u_poc_tap_base_n_39}));\n CARRY4 \\samps_hi_r_reg[17]_i_2 \n (.CI(\\samps_hi_r_reg[15]_i_2_n_0 ),\n .CO({\\NLW_samps_hi_r_reg[17]_i_2_CO_UNCONNECTED [3:1],\\samps_hi_r_reg[17]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O({\\NLW_samps_hi_r_reg[17]_i_2_O_UNCONNECTED [3:2],samps_hi_ns0[17:16]}),\n .S({1'b0,1'b0,u_poc_tap_base_n_40,u_poc_tap_base_n_41}));\n CARRY4 \\samps_hi_r_reg[3]_i_2 \n (.CI(1'b0),\n .CO({\\samps_hi_r_reg[3]_i_2_n_0 ,\\samps_hi_r_reg[3]_i_2_n_1 ,\\samps_hi_r_reg[3]_i_2_n_2 ,\\samps_hi_r_reg[3]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,u_poc_tap_base_n_8}),\n .O(samps_hi_ns0[3:0]),\n .S({u_poc_tap_base_n_25,u_poc_tap_base_n_26,u_poc_tap_base_n_27,\\samps_hi_r[3]_i_6_n_0 }));\n CARRY4 \\samps_hi_r_reg[7]_i_2 \n (.CI(\\samps_hi_r_reg[3]_i_2_n_0 ),\n .CO({\\samps_hi_r_reg[7]_i_2_n_0 ,\\samps_hi_r_reg[7]_i_2_n_1 ,\\samps_hi_r_reg[7]_i_2_n_2 ,\\samps_hi_r_reg[7]_i_2_n_3 }),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(samps_hi_ns0[7:4]),\n .S({u_poc_tap_base_n_28,u_poc_tap_base_n_29,u_poc_tap_base_n_30,u_poc_tap_base_n_31}));\n CARRY4 samps_zero_r0_carry__0_i_10\n (.CI(samps_zero_r0_carry__0_i_4_n_0),\n .CO({samps_zero_r0_carry__0_i_10_n_0,samps_zero_r0_carry__0_i_10_n_1,samps_zero_r0_carry__0_i_10_n_2,samps_zero_r0_carry__0_i_10_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,u_poc_tap_base_n_75}),\n .O(samps_lo[13:10]),\n .S({u_poc_tap_base_n_68,u_poc_tap_base_n_69,u_poc_tap_base_n_70,i___28_n_0}));\n CARRY4 samps_zero_r0_carry__0_i_4\n (.CI(samps_zero_r0_carry_i_2_n_0),\n .CO({samps_zero_r0_carry__0_i_4_n_0,samps_zero_r0_carry__0_i_4_n_1,samps_zero_r0_carry__0_i_4_n_2,samps_zero_r0_carry__0_i_4_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(samps_lo[9:6]),\n .S({u_poc_tap_base_n_42,u_poc_tap_base_n_43,u_poc_tap_base_n_44,u_poc_tap_base_n_45}));\n CARRY4 samps_zero_r0_carry__0_i_9\n (.CI(samps_zero_r0_carry__0_i_10_n_0),\n .CO({NLW_samps_zero_r0_carry__0_i_9_CO_UNCONNECTED[3],samps_zero_r0_carry__0_i_9_n_1,samps_zero_r0_carry__0_i_9_n_2,samps_zero_r0_carry__0_i_9_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0}),\n .O(samps_lo[17:14]),\n .S({u_poc_tap_base_n_64,u_poc_tap_base_n_65,u_poc_tap_base_n_66,u_poc_tap_base_n_67}));\n CARRY4 samps_zero_r0_carry_i_2\n (.CI(1'b0),\n .CO({samps_zero_r0_carry_i_2_n_0,samps_zero_r0_carry_i_2_n_1,samps_zero_r0_carry_i_2_n_2,samps_zero_r0_carry_i_2_n_3}),\n .CYINIT(1'b0),\n .DI({1'b0,1'b0,1'b0,u_poc_tap_base_n_74}),\n .O({samps_lo[5:3],NLW_samps_zero_r0_carry_i_2_O_UNCONNECTED[0]}),\n .S({u_poc_tap_base_n_71,u_poc_tap_base_n_72,u_poc_tap_base_n_73,i___27_n_0}));\n ddr3_if_mig_7series_v4_0_poc_edge_store u_edge_center\n (.CLK(CLK),\n .D(trailing_edge),\n .E(i___7_n_0),\n .Q(rise_lead_center_0),\n .\\rise_trail_center_offset_r_reg[3] (rise_trail_center_0),\n .run_polarity_r_reg(u_poc_tap_base_n_53),\n .\\tap_r_reg[5] ({u_poc_tap_base_n_57,u_poc_tap_base_n_58,u_poc_tap_base_n_59,u_poc_tap_base_n_60,u_poc_tap_base_n_61,u_poc_tap_base_n_62}));\n ddr3_if_mig_7series_v4_0_poc_edge_store_9 u_edge_left\n (.CLK(CLK),\n .D({mod_sub1_return[5:4],mod_sub1_return[0]}),\n .DI({u_edge_left_n_0,u_edge_left_n_1}),\n .E(i___6_n_0),\n .O(u_poc_meta_n_27),\n .Q({u_poc_meta_n_59,u_poc_meta_n_60}),\n .S(u_edge_left_n_15),\n .center0_return3(center0_return3),\n .\\center_diff_r_reg[0] (u_edge_left_n_19),\n .\\center_diff_r_reg[0]_0 (u_edge_left_n_20),\n .\\center_diff_r_reg[0]_1 (u_edge_left_n_21),\n .\\center_diff_r_reg[1] (u_edge_left_n_23),\n .\\center_diff_r_reg[3] (u_edge_left_n_33),\n .\\center_diff_r_reg[3]_0 (u_edge_left_n_34),\n .\\center_diff_r_reg[5] (u_edge_left_n_2),\n .\\center_diff_r_reg[5]_0 (u_edge_left_n_22),\n .\\rise_lead_r_reg[0]_0 (\\center_diff_r_reg[0]_i_2_n_0 ),\n .\\rise_lead_r_reg[4]_0 ({u_poc_meta_n_28,u_poc_meta_n_29}),\n .\\rise_lead_r_reg[5]_0 ({\\mmcm_init_lead_reg[5] [5:3],\\mmcm_init_lead_reg[5] [0]}),\n .\\rise_trail_r_reg[1]_0 (u_edge_right_n_27),\n .\\rise_trail_r_reg[2]_0 (u_edge_right_n_26),\n .\\rise_trail_r_reg[3]_0 (u_edge_right_n_8),\n .\\rise_trail_r_reg[4]_0 ({u_poc_meta_n_33,u_poc_meta_n_34}),\n .\\rise_trail_r_reg[5]_0 ({Q[5:3],Q[0]}),\n .samps_zero_r_reg(u_poc_tap_base_n_95),\n .\\tap_r_reg[4] (trailing_edge),\n .\\tap_r_reg[5] ({u_poc_tap_base_n_57,u_poc_tap_base_n_58,u_poc_tap_base_n_59,u_poc_tap_base_n_60,u_poc_tap_base_n_61,u_poc_tap_base_n_62}),\n .use_noise_window(use_noise_window),\n .\\window_center_r_reg[0] ({u_edge_left_n_28,u_edge_left_n_29,u_edge_left_n_30}),\n .\\window_center_r_reg[3] ({u_edge_left_n_25,u_edge_left_n_26,u_edge_left_n_27}),\n .\\window_center_r_reg[6] (rise_lead_left_0),\n .\\window_center_r_reg[6]_0 (rise_trail_left_0),\n .\\window_center_r_reg[6]_1 (u_edge_left_n_24),\n .\\window_center_r_reg[6]_2 ({u_edge_left_n_31,u_edge_left_n_32}));\n ddr3_if_mig_7series_v4_0_poc_edge_store_10 u_edge_right\n (.CLK(CLK),\n .D(mod_sub1_return[3:1]),\n .DI(u_poc_tap_base_n_63),\n .E(i___5_n_0),\n .O({u_poc_meta_n_24,u_poc_meta_n_25,u_poc_meta_n_26}),\n .Q(u_poc_tap_base_n_48),\n .S({u_poc_tap_base_n_85,i___21_n_0,i___25_n_0,i___26_rep__0_n_0}),\n .\\center_diff_r_reg[0] (u_edge_right_n_26),\n .\\center_diff_r_reg[0]_0 (u_edge_right_n_27),\n .\\center_diff_r_reg[1] (u_edge_right_n_8),\n .\\center_diff_r_reg[3] ({u_edge_right_n_22,u_edge_right_n_23,u_edge_right_n_24,u_edge_right_n_25}),\n .\\center_diff_r_reg[3]_0 ({u_edge_right_n_28,u_edge_right_n_29,u_edge_right_n_30}),\n .\\center_diff_r_reg[5] (u_edge_right_n_21),\n .\\center_diff_r_reg[5]_0 (u_edge_right_n_31),\n .\\mmcm_init_lead_reg[5] (\\mmcm_init_lead_reg[5] ),\n .\\mmcm_init_trail_reg[5] (Q),\n .\\rise_lead_r_reg[1]_0 (u_edge_left_n_20),\n .\\rise_lead_r_reg[3]_0 (u_edge_left_n_1),\n .\\rise_lead_r_reg[4]_0 (u_edge_left_n_21),\n .\\rise_lead_r_reg[4]_1 (u_edge_left_n_23),\n .\\rise_lead_r_reg[5]_0 (rise_lead_left_0[5]),\n .\\rise_trail_r_reg[3]_0 ({u_poc_meta_n_30,u_poc_meta_n_31,u_poc_meta_n_32}),\n .\\rise_trail_r_reg[5]_0 (u_edge_left_n_19),\n .\\rise_trail_r_reg[5]_1 (rise_trail_left_0[5]),\n .samps_zero_r_reg(fall_lead_r0),\n .\\tap_r_reg[4] (trailing_edge),\n .\\tap_r_reg[5] ({u_poc_tap_base_n_57,u_poc_tap_base_n_58,u_poc_tap_base_n_59,u_poc_tap_base_n_60,u_poc_tap_base_n_61,u_poc_tap_base_n_62}),\n .\\tap_r_reg[5]_0 ({u_poc_tap_base_n_83,i___23_n_0}),\n .trailing_edge00_in(trailing_edge00_in[5:1]),\n .use_noise_window(use_noise_window));\n ddr3_if_mig_7series_v4_0_poc_meta u_poc_meta\n (.CLK(CLK),\n .D(mod_sub1_return),\n .DI(i___14_n_0),\n .O({u_poc_meta_n_24,u_poc_meta_n_25,u_poc_meta_n_26,u_poc_meta_n_27}),\n .Q(p_0_in1_in),\n .S({center_return1__1_carry_i_1_n_0,center_return1__1_carry_i_2_n_0,center_return1__1_carry_i_3_n_0}),\n .center0_return3(center0_return3),\n .\\center_diff_r_reg[3]_0 ({u_poc_meta_n_30,u_poc_meta_n_31,u_poc_meta_n_32}),\n .\\center_diff_r_reg[4]_0 ({u_edge_left_n_0,u_edge_left_n_1}),\n .\\center_diff_r_reg[5]_0 ({u_poc_meta_n_28,u_poc_meta_n_29}),\n .\\center_diff_r_reg[5]_1 ({u_poc_meta_n_33,u_poc_meta_n_34}),\n .center_return3(center_return3),\n .detect_done_r_reg(detect_done_r_reg),\n .\\diff_r_reg[2]_0 (i___8_n_0),\n .\\diff_r_reg[7]_0 (edge_center),\n .\\diff_r_reg[7]_1 (window_center),\n .\\edge_center_r_reg[0]_0 (diff_ns00_in),\n .\\edge_center_r_reg[3]_0 ({i___47_rep_n_0,i___38_rep_n_0,i___39_rep_n_0,i___48_rep_n_0}),\n .\\edge_center_r_reg[3]_1 ({i___47_n_0,i___38_n_0,i___39_n_0,i___48_rep__0_n_0}),\n .\\edge_center_r_reg[5]_0 ({i___45_n_0,diff_ns0_carry__0_i_1_n_0}),\n .\\edge_center_r_reg[6]_0 (diff),\n .\\edge_center_r_reg[6]_1 ({i___42_n_0,diff_ns1_carry_i_1_n_0,diff_ns1_carry_i_2_n_0,diff_ns1_carry_i_3_n_0}),\n .\\edge_center_r_reg[6]_2 ({i___41_n_0,i___44_n_0,i___46_n_0}),\n .\\edge_diff_r_reg[0]_0 ({u_poc_meta_n_14,u_poc_meta_n_15,u_poc_meta_n_16,u_poc_meta_n_17,u_poc_meta_n_18,u_poc_meta_n_19}),\n .\\edge_diff_r_reg[4]_0 ({center_return1__0_carry__0_i_2_n_0,center_return1__0_carry__0_i_3_n_0}),\n .ocd_edge_detect_rdy_r_reg(ocd_edge_detect_rdy_r_reg),\n .ocd_ktap_left_r_reg(ocd_ktap_left_r_reg),\n .ocd_ktap_left_r_reg_0(ocd_ktap_left_r_reg_0),\n .ocd_ktap_right_r_reg(ocd_ktap_right_r_reg),\n .poc_backup_r_reg_0(poc_backup_r_reg),\n .\\prev_r_reg[0]_0 (\\prev_r_reg[0] ),\n .\\prev_r_reg[0]_1 (\\prev_r_reg[0]_0 ),\n .\\prev_r_reg[2]_0 ({u_poc_meta_n_56,u_poc_meta_n_57,u_poc_meta_n_58}),\n .\\rise_lead_center_offset_r_reg[2]_0 ({center_return1__0_carry_i_1_n_0,center_return1__0_carry_i_2_n_0,center_return1__0_carry_i_3_n_0}),\n .\\rise_lead_center_offset_r_reg[4]_0 ({center_return1__1_carry__0_i_2_n_0,center_return1__1_carry__0_i_3_n_0}),\n .\\rise_lead_center_offset_r_reg[4]_1 ({i___29_n_0,i___31_n_0}),\n .\\rise_lead_r_reg[2] ({u_edge_left_n_28,u_edge_left_n_29,u_edge_left_n_30}),\n .\\rise_lead_r_reg[2]_0 ({u_edge_left_n_25,u_edge_left_n_26,u_edge_left_n_27}),\n .\\rise_lead_r_reg[3] ({u_edge_left_n_34,u_edge_right_n_28,u_edge_right_n_29,u_edge_right_n_30}),\n .\\rise_lead_r_reg[3]_0 ({i___17_n_0,i___18_n_0,i___19_n_0,i___20_rep__0_n_0}),\n .\\rise_lead_r_reg[3]_1 ({offset_return0,rise_lead_center_0[0]}),\n .\\rise_lead_r_reg[4] ({u_edge_left_n_31,u_edge_left_n_32}),\n .\\rise_lead_r_reg[4]_0 ({u_edge_left_n_15,center0_return1__0_carry__0_i_4_n_0,center0_return1__0_carry__0_i_5_n_0}),\n .\\rise_lead_r_reg[4]_1 (u_edge_left_n_2),\n .\\rise_lead_r_reg[4]_2 ({u_edge_left_n_22,i___15_n_0}),\n .\\rise_lead_r_reg[5] ({u_edge_left_n_24,center0_return1__1_carry__0_i_4_n_0,center0_return1__1_carry__0_i_5_n_0}),\n .\\rise_trail_center_offset_r_reg[0]_0 (\\edge_diff_r_reg[0]_i_2_n_0 ),\n .\\rise_trail_center_offset_r_reg[2]_0 ({i___34_rep_n_0,i___35_rep_n_0,i___36_rep_n_0}),\n .\\rise_trail_center_offset_r_reg[3]_0 ({i___33_n_0,i___34_n_0,i___35_n_0,i___36_rep__0_n_0}),\n .\\rise_trail_center_offset_r_reg[5]_0 ({i___30_n_0,i___32_n_0}),\n .\\rise_trail_r_reg[2] ({center0_return1__1_carry_i_4_n_0,center0_return1__1_carry_i_5_n_0,center0_return1__1_carry_i_6_n_0}),\n .\\rise_trail_r_reg[2]_0 ({center0_return1__0_carry_i_4_n_0,center0_return1__0_carry_i_5_n_0,center0_return1__0_carry_i_6_n_0}),\n .\\rise_trail_r_reg[3] ({u_edge_left_n_33,i___18_rep_n_0,i___19_rep_n_0,i___20_rep_n_0}),\n .\\rise_trail_r_reg[3]_0 ({u_edge_right_n_22,u_edge_right_n_23,u_edge_right_n_24,u_edge_right_n_25}),\n .\\rise_trail_r_reg[3]_1 ({offset0_return0,rise_trail_center_0[0]}),\n .\\rise_trail_r_reg[4] (u_edge_right_n_31),\n .\\rise_trail_r_reg[5] ({u_edge_right_n_21,i___16_n_0}),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .\\run_ends_r_reg[1]_0 (\\run_ends_r_reg[1] ),\n .run_polarity_held_r(run_polarity_held_r),\n .run_too_small_r_reg(u_poc_tap_base_n_1),\n .samps_zero_r_reg(i___4_n_0),\n .samps_zero_r_reg_0(u_poc_tap_base_n_52),\n .\\sm_r_reg[1] (\\sm_r_reg[1] ),\n .\\window_center_r_reg[6]_0 ({u_poc_meta_n_59,u_poc_meta_n_60,u_poc_meta_n_61,u_poc_meta_n_62,u_poc_meta_n_63}),\n .\\window_center_r_reg[6]_1 ({diff_ns1_carry_i_4_n_0,diff_ns1_carry_i_5_n_0,diff_ns1_carry_i_6_n_0,diff_ns1_carry_i_7_n_0}),\n .\\window_center_r_reg[6]_2 ({i___40_n_0,i___37_n_0,i___43_n_0,diff_ns0_carry__0_i_2_n_0}));\n ddr3_if_mig_7series_v4_0_poc_tap_base u_poc_tap_base\n (.CLK(CLK),\n .D({i___11_n_0,i___10_n_0}),\n .DI(u_poc_tap_base_n_63),\n .E(i___12_n_0),\n .Q({u_poc_tap_base_n_4,u_poc_tap_base_n_5,u_poc_tap_base_n_6,u_poc_tap_base_n_7,u_poc_tap_base_n_8}),\n .S({u_poc_tap_base_n_9,u_poc_tap_base_n_10,u_poc_tap_base_n_11,u_poc_tap_base_n_12}),\n .ocd_ktap_left_r_reg(ocd_ktap_left_r_reg),\n .ocd_ktap_right_r_reg(ocd_ktap_right_r_reg),\n .poc_sample_pd(poc_sample_pd),\n .psdone(psdone),\n .\\qcntr_r_reg[0] (\\qcntr_r_reg[0] ),\n .\\rise_lead_r_reg[5] ({u_poc_tap_base_n_57,u_poc_tap_base_n_58,u_poc_tap_base_n_59,u_poc_tap_base_n_60,u_poc_tap_base_n_61,u_poc_tap_base_n_62}),\n .\\rise_trail_r_reg[0] (u_poc_tap_base_n_53),\n .\\rise_trail_r_reg[3] (u_poc_tap_base_n_85),\n .\\rise_trail_r_reg[5] (trailing_edge),\n .\\rise_trail_r_reg[5]_0 (u_poc_tap_base_n_83),\n .\\rise_trail_r_reg[5]_1 (u_poc_tap_base_n_84),\n .\\rise_trail_r_reg[5]_2 (fall_lead_r0),\n .\\rise_trail_r_reg[5]_3 (u_poc_tap_base_n_95),\n .rstdiv0_sync_r1_reg_rep(rstdiv0_sync_r1_reg_rep),\n .rstdiv0_sync_r1_reg_rep__0(rstdiv0_sync_r1_reg_rep__0),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .\\run_r_reg[0]_0 (u_poc_tap_base_n_0),\n .\\run_r_reg[0]_1 (u_poc_tap_base_n_2),\n .\\run_r_reg[0]_2 (u_poc_tap_base_n_3),\n .\\run_r_reg[2]_0 (i___9_n_0),\n .\\run_r_reg[4]_0 ({u_poc_tap_base_n_47,u_poc_tap_base_n_48,u_poc_tap_base_n_49,u_poc_tap_base_n_50,u_poc_tap_base_n_51}),\n .run_too_small_r3_reg(u_poc_tap_base_n_1),\n .run_too_small_r_reg_0(u_poc_tap_base_n_52),\n .samp_cntr_ns0(samp_cntr_ns0),\n .\\samp_cntr_r_reg[0]_0 (u_poc_tap_base_n_76),\n .\\samp_cntr_r_reg[12]_0 ({u_poc_tap_base_n_17,u_poc_tap_base_n_18,u_poc_tap_base_n_19,u_poc_tap_base_n_20}),\n .\\samp_cntr_r_reg[16]_0 ({u_poc_tap_base_n_21,u_poc_tap_base_n_22,u_poc_tap_base_n_23,u_poc_tap_base_n_24}),\n .\\samp_cntr_r_reg[8]_0 ({u_poc_tap_base_n_13,u_poc_tap_base_n_14,u_poc_tap_base_n_15,u_poc_tap_base_n_16}),\n .\\samp_wait_r_reg[4]_0 (i___13_n_0),\n .\\samp_wait_r_reg[6]_0 (u_poc_tap_base_n_86),\n .\\samp_wait_r_reg[7]_0 ({samp_wait_r[7:6],samp_wait_r[4:0]}),\n .samps_hi_ns0(samps_hi_ns0),\n .\\samps_hi_r_reg[11]_0 ({u_poc_tap_base_n_32,u_poc_tap_base_n_33,u_poc_tap_base_n_34,u_poc_tap_base_n_35}),\n .\\samps_hi_r_reg[15]_0 ({u_poc_tap_base_n_36,u_poc_tap_base_n_37,u_poc_tap_base_n_38,u_poc_tap_base_n_39}),\n .\\samps_hi_r_reg[17]_0 ({u_poc_tap_base_n_40,u_poc_tap_base_n_41}),\n .\\samps_hi_r_reg[3]_0 ({u_poc_tap_base_n_25,u_poc_tap_base_n_26,u_poc_tap_base_n_27}),\n .\\samps_hi_r_reg[7]_0 ({u_poc_tap_base_n_28,u_poc_tap_base_n_29,u_poc_tap_base_n_30,u_poc_tap_base_n_31}),\n .samps_lo(samps_lo),\n .samps_zero_r_reg_0({u_poc_tap_base_n_42,u_poc_tap_base_n_43,u_poc_tap_base_n_44,u_poc_tap_base_n_45}),\n .samps_zero_r_reg_1({u_poc_tap_base_n_64,u_poc_tap_base_n_65,u_poc_tap_base_n_66,u_poc_tap_base_n_67}),\n .samps_zero_r_reg_2({u_poc_tap_base_n_68,u_poc_tap_base_n_69,u_poc_tap_base_n_70}),\n .samps_zero_r_reg_3({u_poc_tap_base_n_71,u_poc_tap_base_n_72,u_poc_tap_base_n_73}),\n .samps_zero_r_reg_4(u_poc_tap_base_n_74),\n .samps_zero_r_reg_5(u_poc_tap_base_n_75),\n .\\sm_r_reg[0]_0 (u_poc_tap_base_n_54),\n .\\sm_r_reg[0]_1 (u_poc_tap_base_n_55),\n .\\tap_r_reg[0]_0 (u_poc_tap_base_n_46),\n .trailing_edge0(trailing_edge0),\n .trailing_edge00_in(trailing_edge00_in));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_rank_cntrl\n (act_delayed,\n read_this_rank_r,\n inhbt_act_faw_r,\n periodic_rd_request_r,\n periodic_rd_cntr1_r,\n \\grant_r_reg[0] ,\n \\rtw_timer.rtw_cnt_r_reg[1]_0 ,\n \\periodic_rd_generation.periodic_rd_request_r_reg_0 ,\n \\inhbt_act_faw.inhbt_act_faw_r_reg_0 ,\n \\wtr_timer.wtr_cnt_r_reg[1]_0 ,\n \\grant_r_reg[3] ,\n act_this_rank,\n CLK,\n read_this_rank,\n SR,\n \\periodic_rd_generation.periodic_rd_request_r_reg_1 ,\n \\periodic_read_request.periodic_rd_grant_r_reg[0] ,\n init_calib_complete_reg_rep__6,\n \\periodic_rd_generation.read_this_rank_r_reg_0 ,\n init_calib_complete_reg_rep__6_0,\n maint_prescaler_tick_r,\n \\grant_r_reg[0]_0 ,\n rstdiv0_sync_r1_reg_rep__21,\n rstdiv0_sync_r1_reg_rep__22,\n \\grant_r_reg[2] ,\n \\wr_this_rank_r_reg[0] ,\n \\wr_this_rank_r_reg[0]_0 ,\n \\wr_this_rank_r_reg[0]_1 ,\n rstdiv0_sync_r1_reg_rep__20,\n \\inhbt_act_faw.faw_cnt_r_reg[1]_0 ,\n \\wtr_timer.wtr_cnt_r_reg[2]_0 );\n output act_delayed;\n output read_this_rank_r;\n output inhbt_act_faw_r;\n output periodic_rd_request_r;\n output periodic_rd_cntr1_r;\n output \\grant_r_reg[0] ;\n output [0:0]\\rtw_timer.rtw_cnt_r_reg[1]_0 ;\n output \\periodic_rd_generation.periodic_rd_request_r_reg_0 ;\n output [2:0]\\inhbt_act_faw.inhbt_act_faw_r_reg_0 ;\n output [2:0]\\wtr_timer.wtr_cnt_r_reg[1]_0 ;\n output \\grant_r_reg[3] ;\n input act_this_rank;\n input CLK;\n input read_this_rank;\n input [0:0]SR;\n input \\periodic_rd_generation.periodic_rd_request_r_reg_1 ;\n input \\periodic_read_request.periodic_rd_grant_r_reg[0] ;\n input init_calib_complete_reg_rep__6;\n input \\periodic_rd_generation.read_this_rank_r_reg_0 ;\n input init_calib_complete_reg_rep__6_0;\n input maint_prescaler_tick_r;\n input \\grant_r_reg[0]_0 ;\n input rstdiv0_sync_r1_reg_rep__21;\n input rstdiv0_sync_r1_reg_rep__22;\n input \\grant_r_reg[2] ;\n input \\wr_this_rank_r_reg[0] ;\n input \\wr_this_rank_r_reg[0]_0 ;\n input \\wr_this_rank_r_reg[0]_1 ;\n input rstdiv0_sync_r1_reg_rep__20;\n input [2:0]\\inhbt_act_faw.faw_cnt_r_reg[1]_0 ;\n input [0:0]\\wtr_timer.wtr_cnt_r_reg[2]_0 ;\n\n wire CLK;\n wire [0:0]SR;\n wire act_delayed;\n wire act_this_rank;\n wire \\grant_r_reg[0] ;\n wire \\grant_r_reg[0]_0 ;\n wire \\grant_r_reg[2] ;\n wire \\grant_r_reg[3] ;\n wire [2:0]\\inhbt_act_faw.faw_cnt_r_reg[1]_0 ;\n wire \\inhbt_act_faw.inhbt_act_faw_r_i_1_n_0 ;\n wire [2:0]\\inhbt_act_faw.inhbt_act_faw_r_reg_0 ;\n wire inhbt_act_faw_r;\n wire init_calib_complete_reg_rep__6;\n wire init_calib_complete_reg_rep__6_0;\n wire maint_prescaler_tick_r;\n wire periodic_rd_cntr1_r;\n wire \\periodic_rd_generation.periodic_rd_request_r_reg_0 ;\n wire \\periodic_rd_generation.periodic_rd_request_r_reg_1 ;\n wire \\periodic_rd_generation.periodic_rd_timer_r[0]_i_1_n_0 ;\n wire \\periodic_rd_generation.periodic_rd_timer_r[1]_i_1_n_0 ;\n wire \\periodic_rd_generation.periodic_rd_timer_r[2]_i_1_n_0 ;\n wire \\periodic_rd_generation.read_this_rank_r_reg_0 ;\n wire periodic_rd_request_r;\n wire [2:0]periodic_rd_timer_r;\n wire \\periodic_read_request.periodic_rd_grant_r_reg[0] ;\n wire read_this_rank;\n wire read_this_rank_r;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire rstdiv0_sync_r1_reg_rep__22;\n wire [1:0]rtw_cnt_ns;\n wire [0:0]rtw_cnt_r;\n wire [0:0]\\rtw_timer.rtw_cnt_r_reg[1]_0 ;\n wire \\wr_this_rank_r_reg[0] ;\n wire \\wr_this_rank_r_reg[0]_0 ;\n wire \\wr_this_rank_r_reg[0]_1 ;\n wire [1:0]wtr_cnt_ns;\n wire [2:0]\\wtr_timer.wtr_cnt_r_reg[1]_0 ;\n wire [0:0]\\wtr_timer.wtr_cnt_r_reg[2]_0 ;\n\n LUT5 #(\n .INIT(32'hFFFF0001)) \n \\grant_r[3]_i_8 \n (.I0(\\wtr_timer.wtr_cnt_r_reg[1]_0 [1]),\n .I1(\\wtr_timer.wtr_cnt_r_reg[1]_0 [2]),\n .I2(\\wr_this_rank_r_reg[0]_0 ),\n .I3(\\wr_this_rank_r_reg[0]_1 ),\n .I4(rstdiv0_sync_r1_reg_rep__20),\n .O(\\grant_r_reg[3] ));\n LUT4 #(\n .INIT(16'h0040)) \n i___30_i_2\n (.I0(periodic_rd_timer_r[1]),\n .I1(periodic_rd_timer_r[0]),\n .I2(maint_prescaler_tick_r),\n .I3(periodic_rd_timer_r[2]),\n .O(\\periodic_rd_generation.periodic_rd_request_r_reg_0 ));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n (* XILINX_LEGACY_PRIM = \"SRLC32E\" *) \n (* srl_bus_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/mc0/rank_mach0/rank_cntrl \" *) \n (* srl_name = \"\\u_ddr3_if_mig/u_memc_ui_top_axi/mem_intfc0/mc0/rank_mach0/rank_cntrl[0].rank_cntrl0/inhbt_act_faw.SRLC32E0 \" *) \n SRL16E #(\n .INIT(16'h0000),\n .IS_CLK_INVERTED(1'b0)) \n \\inhbt_act_faw.SRLC32E0 \n (.A0(1'b1),\n .A1(1'b0),\n .A2(1'b1),\n .A3(1'b0),\n .CE(1'b1),\n .CLK(CLK),\n .D(act_this_rank),\n .Q(act_delayed));\n FDRE \\inhbt_act_faw.faw_cnt_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\inhbt_act_faw.faw_cnt_r_reg[1]_0 [0]),\n .Q(\\inhbt_act_faw.inhbt_act_faw_r_reg_0 [0]),\n .R(1'b0));\n FDRE \\inhbt_act_faw.faw_cnt_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\inhbt_act_faw.faw_cnt_r_reg[1]_0 [1]),\n .Q(\\inhbt_act_faw.inhbt_act_faw_r_reg_0 [1]),\n .R(1'b0));\n FDRE \\inhbt_act_faw.faw_cnt_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\inhbt_act_faw.faw_cnt_r_reg[1]_0 [2]),\n .Q(\\inhbt_act_faw.inhbt_act_faw_r_reg_0 [2]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0001000020000220)) \n \\inhbt_act_faw.inhbt_act_faw_r_i_1 \n (.I0(\\inhbt_act_faw.inhbt_act_faw_r_reg_0 [2]),\n .I1(rstdiv0_sync_r1_reg_rep__22),\n .I2(act_delayed),\n .I3(\\grant_r_reg[2] ),\n .I4(\\inhbt_act_faw.inhbt_act_faw_r_reg_0 [0]),\n .I5(\\inhbt_act_faw.inhbt_act_faw_r_reg_0 [1]),\n .O(\\inhbt_act_faw.inhbt_act_faw_r_i_1_n_0 ));\n FDRE \\inhbt_act_faw.inhbt_act_faw_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\inhbt_act_faw.inhbt_act_faw_r_i_1_n_0 ),\n .Q(inhbt_act_faw_r),\n .R(1'b0));\n FDRE \\periodic_rd_generation.periodic_rd_cntr1_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\periodic_read_request.periodic_rd_grant_r_reg[0] ),\n .Q(periodic_rd_cntr1_r),\n .R(SR));\n FDRE \\periodic_rd_generation.periodic_rd_request_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\periodic_rd_generation.periodic_rd_request_r_reg_1 ),\n .Q(periodic_rd_request_r),\n .R(SR));\n LUT6 #(\n .INIT(64'hBBFFFFBBBFFBFFBB)) \n \\periodic_rd_generation.periodic_rd_timer_r[0]_i_1 \n (.I0(\\periodic_rd_generation.read_this_rank_r_reg_0 ),\n .I1(init_calib_complete_reg_rep__6_0),\n .I2(periodic_rd_timer_r[1]),\n .I3(periodic_rd_timer_r[0]),\n .I4(maint_prescaler_tick_r),\n .I5(periodic_rd_timer_r[2]),\n .O(\\periodic_rd_generation.periodic_rd_timer_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h4004404040004040)) \n \\periodic_rd_generation.periodic_rd_timer_r[1]_i_1 \n (.I0(\\periodic_rd_generation.read_this_rank_r_reg_0 ),\n .I1(init_calib_complete_reg_rep__6_0),\n .I2(periodic_rd_timer_r[1]),\n .I3(periodic_rd_timer_r[0]),\n .I4(maint_prescaler_tick_r),\n .I5(periodic_rd_timer_r[2]),\n .O(\\periodic_rd_generation.periodic_rd_timer_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFBFFFFBFBBBBBB)) \n \\periodic_rd_generation.periodic_rd_timer_r[2]_i_1 \n (.I0(\\periodic_rd_generation.read_this_rank_r_reg_0 ),\n .I1(init_calib_complete_reg_rep__6_0),\n .I2(periodic_rd_timer_r[1]),\n .I3(periodic_rd_timer_r[0]),\n .I4(maint_prescaler_tick_r),\n .I5(periodic_rd_timer_r[2]),\n .O(\\periodic_rd_generation.periodic_rd_timer_r[2]_i_1_n_0 ));\n FDRE \\periodic_rd_generation.periodic_rd_timer_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\periodic_rd_generation.periodic_rd_timer_r[0]_i_1_n_0 ),\n .Q(periodic_rd_timer_r[0]),\n .R(1'b0));\n FDRE \\periodic_rd_generation.periodic_rd_timer_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\periodic_rd_generation.periodic_rd_timer_r[1]_i_1_n_0 ),\n .Q(periodic_rd_timer_r[1]),\n .R(1'b0));\n FDRE \\periodic_rd_generation.periodic_rd_timer_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\periodic_rd_generation.periodic_rd_timer_r[2]_i_1_n_0 ),\n .Q(periodic_rd_timer_r[2]),\n .R(1'b0));\n FDRE \\periodic_rd_generation.read_this_rank_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(read_this_rank),\n .Q(read_this_rank_r),\n .R(1'b0));\n FDRE \\refresh_generation.refresh_bank_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(init_calib_complete_reg_rep__6),\n .Q(\\grant_r_reg[0] ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1103\" *) \n LUT4 #(\n .INIT(16'h0008)) \n \\rtw_timer.rtw_cnt_r[0]_i_1 \n (.I0(\\grant_r_reg[0]_0 ),\n .I1(\\rtw_timer.rtw_cnt_r_reg[1]_0 ),\n .I2(rstdiv0_sync_r1_reg_rep__21),\n .I3(rtw_cnt_r),\n .O(rtw_cnt_ns[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1103\" *) \n LUT4 #(\n .INIT(16'h0D05)) \n \\rtw_timer.rtw_cnt_r[1]_i_1 \n (.I0(\\grant_r_reg[0]_0 ),\n .I1(\\rtw_timer.rtw_cnt_r_reg[1]_0 ),\n .I2(rstdiv0_sync_r1_reg_rep__21),\n .I3(rtw_cnt_r),\n .O(rtw_cnt_ns[1]));\n FDRE \\rtw_timer.rtw_cnt_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(rtw_cnt_ns[0]),\n .Q(rtw_cnt_r),\n .R(1'b0));\n FDRE \\rtw_timer.rtw_cnt_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(rtw_cnt_ns[1]),\n .Q(\\rtw_timer.rtw_cnt_r_reg[1]_0 ),\n .R(1'b0));\n LUT4 #(\n .INIT(16'h0054)) \n \\wtr_timer.wtr_cnt_r[0]_i_1 \n (.I0(\\wtr_timer.wtr_cnt_r_reg[1]_0 [0]),\n .I1(\\wtr_timer.wtr_cnt_r_reg[1]_0 [1]),\n .I2(\\wtr_timer.wtr_cnt_r_reg[1]_0 [2]),\n .I3(\\wr_this_rank_r_reg[0] ),\n .O(wtr_cnt_ns[0]));\n LUT6 #(\n .INIT(64'h0000000000000098)) \n \\wtr_timer.wtr_cnt_r[1]_i_1 \n (.I0(\\wtr_timer.wtr_cnt_r_reg[1]_0 [0]),\n .I1(\\wtr_timer.wtr_cnt_r_reg[1]_0 [1]),\n .I2(\\wtr_timer.wtr_cnt_r_reg[1]_0 [2]),\n .I3(\\wr_this_rank_r_reg[0]_0 ),\n .I4(\\wr_this_rank_r_reg[0]_1 ),\n .I5(rstdiv0_sync_r1_reg_rep__22),\n .O(wtr_cnt_ns[1]));\n FDRE \\wtr_timer.wtr_cnt_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(wtr_cnt_ns[0]),\n .Q(\\wtr_timer.wtr_cnt_r_reg[1]_0 [0]),\n .R(1'b0));\n FDRE \\wtr_timer.wtr_cnt_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(wtr_cnt_ns[1]),\n .Q(\\wtr_timer.wtr_cnt_r_reg[1]_0 [1]),\n .R(1'b0));\n FDRE \\wtr_timer.wtr_cnt_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wtr_timer.wtr_cnt_r_reg[2]_0 ),\n .Q(\\wtr_timer.wtr_cnt_r_reg[1]_0 [2]),\n .R(1'b0));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_rank_common\n (maint_prescaler_tick_r,\n maint_prescaler_tick_ns,\n \\maintenance_request.new_maint_rank_r_reg_0 ,\n \\maintenance_request.maint_req_r_lcl_reg_0 ,\n maint_req_r,\n \\periodic_read_request.upd_last_master_r_reg_0 ,\n app_ref_ack,\n app_zq_ack,\n \\maint_controller.maint_srx_r1_reg ,\n \\maintenance_request.maint_sre_r_lcl_reg_0 ,\n \\grant_r_reg[0] ,\n \\grant_r_reg[0]_0 ,\n \\maintenance_request.maint_zq_r_lcl_reg_0 ,\n periodic_rd_r,\n app_ref_r,\n app_zq_r,\n periodic_rd_r_cnt,\n periodic_rd_grant_r,\n app_sr_active,\n maint_ref_zq_wip,\n Q,\n \\refresh_timer.refresh_timer_r_reg[5]_0 ,\n \\refresh_timer.refresh_timer_r_reg[4]_0 ,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[0]_0 ,\n \\maintenance_request.maint_sre_r_lcl_reg_1 ,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ,\n \\last_master_r_reg[2] ,\n mc_cke_ns,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] ,\n \\refresh_generation.refresh_bank_r_reg[0] ,\n S,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ,\n CLK,\n \\maint_controller.maint_wip_r_lcl_reg ,\n SR,\n \\zq_cntrl.zq_request_logic.zq_request_r_reg_0 ,\n init_calib_complete_reg_rep__6,\n maint_prescaler_r1,\n periodic_rd_ack_r_lcl_reg,\n \\refresh_generation.refresh_bank_r_reg[0]_0 ,\n app_zq_r_reg_0,\n \\periodic_read_request.periodic_rd_r_lcl_reg_0 ,\n \\periodic_rd_generation.periodic_rd_request_r_reg ,\n \\maintenance_request.maint_sre_r_lcl_reg_2 ,\n in0,\n \\refresh_generation.refresh_bank_r_reg[0]_1 ,\n O,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 ,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 ,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 ,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 ,\n init_calib_complete_reg_rep__6_0,\n app_sr_req,\n D,\n \\refresh_generation.refresh_bank_r_reg[0]_2 ,\n \\last_master_r_reg[2]_0 ,\n rstdiv0_sync_r1_reg_rep__21,\n periodic_rd_request_r,\n cke_r,\n insert_maint_r1,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] ,\n insert_maint_r,\n rstdiv0_sync_r1_reg_rep__22,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ,\n SS,\n \\maint_prescaler.maint_prescaler_r_reg[0]_0 ,\n init_calib_complete_reg_rep__6_1,\n \\refresh_timer.refresh_timer_r_reg[0]_0 );\n output maint_prescaler_tick_r;\n output maint_prescaler_tick_ns;\n output \\maintenance_request.new_maint_rank_r_reg_0 ;\n output \\maintenance_request.maint_req_r_lcl_reg_0 ;\n output maint_req_r;\n output \\periodic_read_request.upd_last_master_r_reg_0 ;\n output app_ref_ack;\n output app_zq_ack;\n output \\maint_controller.maint_srx_r1_reg ;\n output \\maintenance_request.maint_sre_r_lcl_reg_0 ;\n output \\grant_r_reg[0] ;\n output \\grant_r_reg[0]_0 ;\n output \\maintenance_request.maint_zq_r_lcl_reg_0 ;\n output periodic_rd_r;\n output app_ref_r;\n output app_zq_r;\n output periodic_rd_r_cnt;\n output periodic_rd_grant_r;\n output app_sr_active;\n output maint_ref_zq_wip;\n output [1:0]Q;\n output \\refresh_timer.refresh_timer_r_reg[5]_0 ;\n output [1:0]\\refresh_timer.refresh_timer_r_reg[4]_0 ;\n output \\zq_cntrl.zq_timer.zq_timer_r_reg[0]_0 ;\n output [2:0]\\maintenance_request.maint_sre_r_lcl_reg_1 ;\n output \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ;\n output [2:0]\\last_master_r_reg[2] ;\n output [0:0]mc_cke_ns;\n output \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ;\n output [0:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ;\n output \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] ;\n output \\refresh_generation.refresh_bank_r_reg[0] ;\n output [3:0]S;\n output [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ;\n output [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ;\n output [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ;\n output [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ;\n input CLK;\n input \\maint_controller.maint_wip_r_lcl_reg ;\n input [0:0]SR;\n input \\zq_cntrl.zq_request_logic.zq_request_r_reg_0 ;\n input init_calib_complete_reg_rep__6;\n input maint_prescaler_r1;\n input periodic_rd_ack_r_lcl_reg;\n input \\refresh_generation.refresh_bank_r_reg[0]_0 ;\n input app_zq_r_reg_0;\n input \\periodic_read_request.periodic_rd_r_lcl_reg_0 ;\n input \\periodic_rd_generation.periodic_rd_request_r_reg ;\n input \\maintenance_request.maint_sre_r_lcl_reg_2 ;\n input in0;\n input \\refresh_generation.refresh_bank_r_reg[0]_1 ;\n input [3:0]O;\n input [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 ;\n input [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 ;\n input [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 ;\n input [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 ;\n input init_calib_complete_reg_rep__6_0;\n input app_sr_req;\n input [1:0]D;\n input \\refresh_generation.refresh_bank_r_reg[0]_2 ;\n input \\last_master_r_reg[2]_0 ;\n input rstdiv0_sync_r1_reg_rep__21;\n input periodic_rd_request_r;\n input cke_r;\n input insert_maint_r1;\n input [0:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] ;\n input insert_maint_r;\n input rstdiv0_sync_r1_reg_rep__22;\n input [0:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ;\n input [0:0]SS;\n input [0:0]\\maint_prescaler.maint_prescaler_r_reg[0]_0 ;\n input [0:0]init_calib_complete_reg_rep__6_1;\n input [0:0]\\refresh_timer.refresh_timer_r_reg[0]_0 ;\n\n wire CLK;\n wire [1:0]D;\n wire [3:0]O;\n wire [1:0]Q;\n wire [3:0]S;\n wire [0:0]SR;\n wire [0:0]SS;\n wire app_ref_ack;\n wire app_ref_ack_ns;\n wire app_ref_r;\n wire app_sr_active;\n wire app_sr_req;\n wire app_zq_ack;\n wire app_zq_ack_ns;\n wire app_zq_r;\n wire app_zq_r_reg_0;\n wire cke_r;\n wire [1:0]ckesr_timer_r;\n wire \\grant_r_reg[0] ;\n wire \\grant_r_reg[0]_0 ;\n wire i___21_i_3_n_0;\n wire in0;\n wire inhbt_srx;\n wire init_calib_complete_reg_rep__6;\n wire init_calib_complete_reg_rep__6_0;\n wire [0:0]init_calib_complete_reg_rep__6_1;\n wire insert_maint_r;\n wire insert_maint_r1;\n wire [2:0]\\last_master_r_reg[2] ;\n wire \\last_master_r_reg[2]_0 ;\n wire \\maint_controller.maint_srx_r1_reg ;\n wire \\maint_controller.maint_wip_r_lcl_reg ;\n wire [0:0]\\maint_prescaler.maint_prescaler_r_reg[0]_0 ;\n wire [5:2]\\maint_prescaler.maint_prescaler_r_reg__0 ;\n wire [5:0]maint_prescaler_r0;\n wire maint_prescaler_r1;\n wire maint_prescaler_tick_ns;\n wire maint_prescaler_tick_r;\n wire maint_ref_zq_wip;\n wire maint_req_r;\n wire \\maintenance_request.maint_arb0_n_0 ;\n wire \\maintenance_request.maint_arb0_n_4 ;\n wire \\maintenance_request.maint_arb0_n_8 ;\n wire \\maintenance_request.maint_req_r_lcl_reg_0 ;\n wire \\maintenance_request.maint_sre_r_lcl_reg_0 ;\n wire [2:0]\\maintenance_request.maint_sre_r_lcl_reg_1 ;\n wire \\maintenance_request.maint_sre_r_lcl_reg_2 ;\n wire \\maintenance_request.maint_srx_r_lcl_i_2_n_0 ;\n wire \\maintenance_request.maint_zq_r_lcl_reg_0 ;\n wire \\maintenance_request.new_maint_rank_r_reg_0 ;\n wire [0:0]mc_cke_ns;\n wire periodic_rd_ack_r_lcl_reg;\n wire \\periodic_rd_generation.periodic_rd_request_r_reg ;\n wire periodic_rd_grant_r;\n wire periodic_rd_r;\n wire periodic_rd_r_cnt;\n wire periodic_rd_request_r;\n wire \\periodic_read_request.periodic_rd_r_lcl_reg_0 ;\n wire \\periodic_read_request.upd_last_master_r_reg_0 ;\n wire \\refresh_generation.refresh_bank_r_reg[0] ;\n wire \\refresh_generation.refresh_bank_r_reg[0]_0 ;\n wire \\refresh_generation.refresh_bank_r_reg[0]_1 ;\n wire \\refresh_generation.refresh_bank_r_reg[0]_2 ;\n wire \\refresh_timer.refresh_timer_r[5]_i_3_n_0 ;\n wire [0:0]\\refresh_timer.refresh_timer_r_reg[0]_0 ;\n wire [1:0]\\refresh_timer.refresh_timer_r_reg[4]_0 ;\n wire \\refresh_timer.refresh_timer_r_reg[5]_0 ;\n wire [5:2]\\refresh_timer.refresh_timer_r_reg__0 ;\n wire [5:0]refresh_timer_r0;\n wire refresh_timer_r0_0;\n wire [0:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ;\n wire [0:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ;\n wire [0:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] ;\n wire \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ;\n wire \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] ;\n wire \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire rstdiv0_sync_r1_reg_rep__22;\n wire sel;\n wire \\sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1_n_0 ;\n wire \\sr_cntrl.ckesr_timer.ckesr_timer_r[1]_i_1_n_0 ;\n wire upd_last_master_ns;\n wire \\zq_cntrl.zq_request_logic.zq_request_r_reg_0 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r[0]_i_11_n_0 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r[0]_i_5_n_0 ;\n wire \\zq_cntrl.zq_timer.zq_timer_r[0]_i_6_n_0 ;\n wire [19:0]\\zq_cntrl.zq_timer.zq_timer_r_reg ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[0]_0 ;\n wire [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ;\n wire [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 ;\n wire [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ;\n wire [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 ;\n wire [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ;\n wire [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 ;\n wire [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ;\n wire [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 ;\n wire zq_timer_r0;\n\n (* SOFT_HLUTNM = \"soft_lutpair1110\" *) \n LUT3 #(\n .INIT(8'h8A)) \n app_ref_ack_r_i_1\n (.I0(app_ref_r),\n .I1(\\refresh_generation.refresh_bank_r_reg[0]_2 ),\n .I2(init_calib_complete_reg_rep__6_0),\n .O(app_ref_ack_ns));\n FDRE #(\n .INIT(1'b0)) \n app_ref_ack_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(app_ref_ack_ns),\n .Q(app_ref_ack),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n app_ref_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\refresh_generation.refresh_bank_r_reg[0]_0 ),\n .Q(app_ref_r),\n .R(maint_prescaler_r1));\n FDRE app_sr_active_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\maintenance_request.maint_sre_r_lcl_reg_2 ),\n .Q(app_sr_active),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1110\" *) \n LUT3 #(\n .INIT(8'h2A)) \n app_zq_ack_r_i_1\n (.I0(app_zq_r),\n .I1(init_calib_complete_reg_rep__6_0),\n .I2(\\grant_r_reg[0] ),\n .O(app_zq_ack_ns));\n FDRE #(\n .INIT(1'b0)) \n app_zq_ack_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(app_zq_ack_ns),\n .Q(app_zq_ack),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n app_zq_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(app_zq_r_reg_0),\n .Q(app_zq_r),\n .R(maint_prescaler_r1));\n (* SOFT_HLUTNM = \"soft_lutpair1107\" *) \n LUT4 #(\n .INIT(16'h0ECC)) \n cke_r_i_2\n (.I0(\\maint_controller.maint_srx_r1_reg ),\n .I1(cke_r),\n .I2(\\maintenance_request.maint_sre_r_lcl_reg_0 ),\n .I3(insert_maint_r1),\n .O(mc_cke_ns));\n LUT6 #(\n .INIT(64'h0000000000100000)) \n i___21_i_1\n (.I0(\\refresh_timer.refresh_timer_r_reg__0 [2]),\n .I1(\\refresh_timer.refresh_timer_r_reg__0 [5]),\n .I2(maint_prescaler_tick_r),\n .I3(\\refresh_timer.refresh_timer_r_reg[4]_0 [1]),\n .I4(\\refresh_timer.refresh_timer_r_reg[4]_0 [0]),\n .I5(i___21_i_3_n_0),\n .O(\\refresh_timer.refresh_timer_r_reg[5]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1107\" *) \n LUT4 #(\n .INIT(16'h0100)) \n i___21_i_2\n (.I0(\\maintenance_request.maint_zq_r_lcl_reg_0 ),\n .I1(\\maintenance_request.maint_sre_r_lcl_reg_0 ),\n .I2(\\maint_controller.maint_srx_r1_reg ),\n .I3(insert_maint_r1),\n .O(\\refresh_generation.refresh_bank_r_reg[0] ));\n LUT2 #(\n .INIT(4'hE)) \n i___21_i_3\n (.I0(\\refresh_timer.refresh_timer_r_reg__0 [3]),\n .I1(\\refresh_timer.refresh_timer_r_reg__0 [4]),\n .O(i___21_i_3_n_0));\n LUT6 #(\n .INIT(64'hAAAA8AAAAAAAAAAA)) \n i___23_i_1\n (.I0(init_calib_complete_reg_rep__6_0),\n .I1(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0 ),\n .I2(maint_prescaler_tick_r),\n .I3(\\zq_cntrl.zq_timer.zq_timer_r_reg [0]),\n .I4(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_5_n_0 ),\n .I5(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_6_n_0 ),\n .O(\\zq_cntrl.zq_timer.zq_timer_r_reg[0]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1104\" *) \n LUT3 #(\n .INIT(8'h54)) \n i___24_i_1\n (.I0(\\maintenance_request.maint_zq_r_lcl_reg_0 ),\n .I1(\\maint_controller.maint_srx_r1_reg ),\n .I2(\\maintenance_request.maint_sre_r_lcl_reg_0 ),\n .O(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ));\n (* SOFT_HLUTNM = \"soft_lutpair1106\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\maint_prescaler.maint_prescaler_r[0]_i_1 \n (.I0(Q[0]),\n .O(maint_prescaler_r0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1109\" *) \n LUT3 #(\n .INIT(8'hA9)) \n \\maint_prescaler.maint_prescaler_r[2]_i_1 \n (.I0(\\maint_prescaler.maint_prescaler_r_reg__0 [2]),\n .I1(Q[1]),\n .I2(Q[0]),\n .O(maint_prescaler_r0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1109\" *) \n LUT4 #(\n .INIT(16'hAAA9)) \n \\maint_prescaler.maint_prescaler_r[3]_i_1 \n (.I0(\\maint_prescaler.maint_prescaler_r_reg__0 [3]),\n .I1(\\maint_prescaler.maint_prescaler_r_reg__0 [2]),\n .I2(Q[0]),\n .I3(Q[1]),\n .O(maint_prescaler_r0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1106\" *) \n LUT5 #(\n .INIT(32'hAAAAAAA9)) \n \\maint_prescaler.maint_prescaler_r[4]_i_1 \n (.I0(\\maint_prescaler.maint_prescaler_r_reg__0 [4]),\n .I1(\\maint_prescaler.maint_prescaler_r_reg__0 [3]),\n .I2(Q[1]),\n .I3(Q[0]),\n .I4(\\maint_prescaler.maint_prescaler_r_reg__0 [2]),\n .O(maint_prescaler_r0[4]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\maint_prescaler.maint_prescaler_r[5]_i_1 \n (.I0(\\maint_prescaler.maint_prescaler_r_reg__0 [5]),\n .I1(\\maint_prescaler.maint_prescaler_r_reg__0 [3]),\n .I2(\\maint_prescaler.maint_prescaler_r_reg__0 [4]),\n .I3(\\maint_prescaler.maint_prescaler_r_reg__0 [2]),\n .I4(Q[0]),\n .I5(Q[1]),\n .O(sel));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAAAAA9)) \n \\maint_prescaler.maint_prescaler_r[5]_i_2 \n (.I0(\\maint_prescaler.maint_prescaler_r_reg__0 [5]),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(\\maint_prescaler.maint_prescaler_r_reg__0 [2]),\n .I4(\\maint_prescaler.maint_prescaler_r_reg__0 [3]),\n .I5(\\maint_prescaler.maint_prescaler_r_reg__0 [4]),\n .O(maint_prescaler_r0[5]));\n FDRE \\maint_prescaler.maint_prescaler_r_reg[0] \n (.C(CLK),\n .CE(sel),\n .D(maint_prescaler_r0[0]),\n .Q(Q[0]),\n .R(SS));\n FDRE \\maint_prescaler.maint_prescaler_r_reg[1] \n (.C(CLK),\n .CE(sel),\n .D(\\maint_prescaler.maint_prescaler_r_reg[0]_0 ),\n .Q(Q[1]),\n .R(SS));\n FDSE \\maint_prescaler.maint_prescaler_r_reg[2] \n (.C(CLK),\n .CE(sel),\n .D(maint_prescaler_r0[2]),\n .Q(\\maint_prescaler.maint_prescaler_r_reg__0 [2]),\n .S(SS));\n FDSE \\maint_prescaler.maint_prescaler_r_reg[3] \n (.C(CLK),\n .CE(sel),\n .D(maint_prescaler_r0[3]),\n .Q(\\maint_prescaler.maint_prescaler_r_reg__0 [3]),\n .S(SS));\n FDRE \\maint_prescaler.maint_prescaler_r_reg[4] \n (.C(CLK),\n .CE(sel),\n .D(maint_prescaler_r0[4]),\n .Q(\\maint_prescaler.maint_prescaler_r_reg__0 [4]),\n .R(SS));\n FDSE \\maint_prescaler.maint_prescaler_r_reg[5] \n (.C(CLK),\n .CE(sel),\n .D(maint_prescaler_r0[5]),\n .Q(\\maint_prescaler.maint_prescaler_r_reg__0 [5]),\n .S(SS));\n LUT6 #(\n .INIT(64'h0000000000010000)) \n \\maint_prescaler.maint_prescaler_tick_r_lcl_i_1 \n (.I0(\\maint_prescaler.maint_prescaler_r_reg__0 [5]),\n .I1(\\maint_prescaler.maint_prescaler_r_reg__0 [3]),\n .I2(\\maint_prescaler.maint_prescaler_r_reg__0 [4]),\n .I3(Q[1]),\n .I4(Q[0]),\n .I5(\\maint_prescaler.maint_prescaler_r_reg__0 [2]),\n .O(maint_prescaler_tick_ns));\n FDRE \\maint_prescaler.maint_prescaler_tick_r_lcl_reg \n (.C(CLK),\n .CE(1'b1),\n .D(maint_prescaler_tick_ns),\n .Q(maint_prescaler_tick_r),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n maint_ref_zq_wip_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(\\refresh_generation.refresh_bank_r_reg[0]_1 ),\n .Q(maint_ref_zq_wip),\n .R(in0));\n ddr3_if_mig_7series_v4_0_round_robin_arb \\maintenance_request.maint_arb0 \n (.CLK(CLK),\n .D(D),\n .Q(\\maintenance_request.maint_sre_r_lcl_reg_1 ),\n .app_sr_req(app_sr_req),\n .ckesr_timer_r(ckesr_timer_r),\n .inhbt_srx(inhbt_srx),\n .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6_0),\n .\\last_master_r_reg[2]_0 (\\last_master_r_reg[2] ),\n .\\last_master_r_reg[2]_1 (\\last_master_r_reg[2]_0 ),\n .\\maintenance_request.maint_sre_r_lcl_reg (\\maintenance_request.maint_arb0_n_0 ),\n .\\maintenance_request.maint_sre_r_lcl_reg_0 (\\maintenance_request.maint_sre_r_lcl_reg_0 ),\n .\\maintenance_request.maint_srx_r_lcl_reg (\\maintenance_request.maint_arb0_n_4 ),\n .\\maintenance_request.maint_srx_r_lcl_reg_0 (\\maint_controller.maint_srx_r1_reg ),\n .\\maintenance_request.maint_zq_r_lcl_reg (\\maintenance_request.maint_arb0_n_8 ),\n .\\maintenance_request.maint_zq_r_lcl_reg_0 (\\maintenance_request.maint_zq_r_lcl_reg_0 ),\n .\\maintenance_request.new_maint_rank_r_reg (\\maintenance_request.maint_req_r_lcl_reg_0 ),\n .\\maintenance_request.upd_last_master_r_reg (\\maintenance_request.maint_srx_r_lcl_i_2_n_0 ),\n .\\maintenance_request.upd_last_master_r_reg_0 (\\maintenance_request.new_maint_rank_r_reg_0 ),\n .\\refresh_generation.refresh_bank_r_reg[0] (\\refresh_generation.refresh_bank_r_reg[0]_2 ),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .\\sr_cntrl.sre_request_logic.sre_request_r_reg (\\grant_r_reg[0]_0 ),\n .\\zq_cntrl.zq_request_logic.zq_request_r_reg (\\grant_r_reg[0] ));\n FDRE \\maintenance_request.maint_req_r_lcl_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\maintenance_request.maint_req_r_lcl_reg_0 ),\n .Q(maint_req_r),\n .R(1'b0));\n FDRE \\maintenance_request.maint_sre_r_lcl_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\maintenance_request.maint_arb0_n_0 ),\n .Q(\\maintenance_request.maint_sre_r_lcl_reg_0 ),\n .R(SR));\n LUT2 #(\n .INIT(4'h2)) \n \\maintenance_request.maint_srx_r_lcl_i_2 \n (.I0(\\maintenance_request.new_maint_rank_r_reg_0 ),\n .I1(\\maintenance_request.maint_req_r_lcl_reg_0 ),\n .O(\\maintenance_request.maint_srx_r_lcl_i_2_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\maintenance_request.maint_srx_r_lcl_i_3 \n (.I0(ckesr_timer_r[0]),\n .I1(ckesr_timer_r[1]),\n .O(inhbt_srx));\n FDRE \\maintenance_request.maint_srx_r_lcl_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\maintenance_request.maint_arb0_n_4 ),\n .Q(\\maint_controller.maint_srx_r1_reg ),\n .R(SR));\n FDRE \\maintenance_request.maint_zq_r_lcl_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\maintenance_request.maint_arb0_n_8 ),\n .Q(\\maintenance_request.maint_zq_r_lcl_reg_0 ),\n .R(SR));\n FDRE \\maintenance_request.new_maint_rank_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\maintenance_request.new_maint_rank_r_reg_0 ),\n .Q(\\maintenance_request.maint_req_r_lcl_reg_0 ),\n .R(1'b0));\n FDRE \\maintenance_request.upd_last_master_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\maint_controller.maint_wip_r_lcl_reg ),\n .Q(\\maintenance_request.new_maint_rank_r_reg_0 ),\n .R(1'b0));\n FDRE \\periodic_read_request.periodic_rd_grant_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\periodic_rd_generation.periodic_rd_request_r_reg ),\n .Q(periodic_rd_grant_r),\n .R(1'b0));\n FDRE \\periodic_read_request.periodic_rd_r_cnt_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\periodic_read_request.periodic_rd_r_lcl_reg_0 ),\n .Q(periodic_rd_r_cnt),\n .R(SR));\n FDRE \\periodic_read_request.periodic_rd_r_lcl_reg \n (.C(CLK),\n .CE(1'b1),\n .D(periodic_rd_ack_r_lcl_reg),\n .Q(periodic_rd_r),\n .R(maint_prescaler_r1));\n LUT4 #(\n .INIT(16'h0008)) \n \\periodic_read_request.upd_last_master_r_i_1 \n (.I0(periodic_rd_request_r),\n .I1(init_calib_complete_reg_rep__6_0),\n .I2(\\periodic_read_request.upd_last_master_r_reg_0 ),\n .I3(periodic_rd_r),\n .O(upd_last_master_ns));\n FDRE \\periodic_read_request.upd_last_master_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(upd_last_master_ns),\n .Q(\\periodic_read_request.upd_last_master_r_reg_0 ),\n .R(1'b0));\n LUT1 #(\n .INIT(2'h1)) \n \\refresh_timer.refresh_timer_r[0]_i_1 \n (.I0(\\refresh_timer.refresh_timer_r_reg[4]_0 [0]),\n .O(refresh_timer_r0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1111\" *) \n LUT3 #(\n .INIT(8'hA9)) \n \\refresh_timer.refresh_timer_r[2]_i_1 \n (.I0(\\refresh_timer.refresh_timer_r_reg__0 [2]),\n .I1(\\refresh_timer.refresh_timer_r_reg[4]_0 [1]),\n .I2(\\refresh_timer.refresh_timer_r_reg[4]_0 [0]),\n .O(refresh_timer_r0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1105\" *) \n LUT4 #(\n .INIT(16'hAAA9)) \n \\refresh_timer.refresh_timer_r[3]_i_1 \n (.I0(\\refresh_timer.refresh_timer_r_reg__0 [3]),\n .I1(\\refresh_timer.refresh_timer_r_reg__0 [2]),\n .I2(\\refresh_timer.refresh_timer_r_reg[4]_0 [0]),\n .I3(\\refresh_timer.refresh_timer_r_reg[4]_0 [1]),\n .O(refresh_timer_r0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1105\" *) \n LUT5 #(\n .INIT(32'hAAAAAAA9)) \n \\refresh_timer.refresh_timer_r[4]_i_1 \n (.I0(\\refresh_timer.refresh_timer_r_reg__0 [4]),\n .I1(\\refresh_timer.refresh_timer_r_reg__0 [3]),\n .I2(\\refresh_timer.refresh_timer_r_reg[4]_0 [1]),\n .I3(\\refresh_timer.refresh_timer_r_reg[4]_0 [0]),\n .I4(\\refresh_timer.refresh_timer_r_reg__0 [2]),\n .O(refresh_timer_r0[4]));\n LUT5 #(\n .INIT(32'hAAAAAA8A)) \n \\refresh_timer.refresh_timer_r[5]_i_1 \n (.I0(maint_prescaler_tick_r),\n .I1(\\refresh_timer.refresh_timer_r_reg__0 [5]),\n .I2(\\refresh_timer.refresh_timer_r[5]_i_3_n_0 ),\n .I3(\\refresh_timer.refresh_timer_r_reg__0 [4]),\n .I4(\\refresh_timer.refresh_timer_r_reg__0 [3]),\n .O(refresh_timer_r0_0));\n LUT6 #(\n .INIT(64'hAAAAAAAAAAAAAAA9)) \n \\refresh_timer.refresh_timer_r[5]_i_2 \n (.I0(\\refresh_timer.refresh_timer_r_reg__0 [5]),\n .I1(\\refresh_timer.refresh_timer_r_reg__0 [3]),\n .I2(\\refresh_timer.refresh_timer_r_reg__0 [4]),\n .I3(\\refresh_timer.refresh_timer_r_reg[4]_0 [1]),\n .I4(\\refresh_timer.refresh_timer_r_reg[4]_0 [0]),\n .I5(\\refresh_timer.refresh_timer_r_reg__0 [2]),\n .O(refresh_timer_r0[5]));\n (* SOFT_HLUTNM = \"soft_lutpair1111\" *) \n LUT3 #(\n .INIT(8'h01)) \n \\refresh_timer.refresh_timer_r[5]_i_3 \n (.I0(\\refresh_timer.refresh_timer_r_reg[4]_0 [1]),\n .I1(\\refresh_timer.refresh_timer_r_reg[4]_0 [0]),\n .I2(\\refresh_timer.refresh_timer_r_reg__0 [2]),\n .O(\\refresh_timer.refresh_timer_r[5]_i_3_n_0 ));\n FDRE \\refresh_timer.refresh_timer_r_reg[0] \n (.C(CLK),\n .CE(refresh_timer_r0_0),\n .D(refresh_timer_r0[0]),\n .Q(\\refresh_timer.refresh_timer_r_reg[4]_0 [0]),\n .R(init_calib_complete_reg_rep__6_1));\n FDSE \\refresh_timer.refresh_timer_r_reg[1] \n (.C(CLK),\n .CE(refresh_timer_r0_0),\n .D(\\refresh_timer.refresh_timer_r_reg[0]_0 ),\n .Q(\\refresh_timer.refresh_timer_r_reg[4]_0 [1]),\n .S(init_calib_complete_reg_rep__6_1));\n FDSE \\refresh_timer.refresh_timer_r_reg[2] \n (.C(CLK),\n .CE(refresh_timer_r0_0),\n .D(refresh_timer_r0[2]),\n .Q(\\refresh_timer.refresh_timer_r_reg__0 [2]),\n .S(init_calib_complete_reg_rep__6_1));\n FDRE \\refresh_timer.refresh_timer_r_reg[3] \n (.C(CLK),\n .CE(refresh_timer_r0_0),\n .D(refresh_timer_r0[3]),\n .Q(\\refresh_timer.refresh_timer_r_reg__0 [3]),\n .R(init_calib_complete_reg_rep__6_1));\n FDRE \\refresh_timer.refresh_timer_r_reg[4] \n (.C(CLK),\n .CE(refresh_timer_r0_0),\n .D(refresh_timer_r0[4]),\n .Q(\\refresh_timer.refresh_timer_r_reg__0 [4]),\n .R(init_calib_complete_reg_rep__6_1));\n FDSE \\refresh_timer.refresh_timer_r_reg[5] \n (.C(CLK),\n .CE(refresh_timer_r0_0),\n .D(refresh_timer_r0[5]),\n .Q(\\refresh_timer.refresh_timer_r_reg__0 [5]),\n .S(init_calib_complete_reg_rep__6_1));\n LUT6 #(\n .INIT(64'h00000000010100FF)) \n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[0]_i_1 \n (.I0(\\maint_controller.maint_srx_r1_reg ),\n .I1(\\maintenance_request.maint_sre_r_lcl_reg_0 ),\n .I2(\\maintenance_request.maint_zq_r_lcl_reg_0 ),\n .I3(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ),\n .I4(insert_maint_r),\n .I5(rstdiv0_sync_r1_reg_rep__22),\n .O(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair1104\" *) \n LUT5 #(\n .INIT(32'h00000100)) \n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[5]_i_2 \n (.I0(\\maintenance_request.maint_zq_r_lcl_reg_0 ),\n .I1(\\maintenance_request.maint_sre_r_lcl_reg_0 ),\n .I2(\\maint_controller.maint_srx_r1_reg ),\n .I3(insert_maint_r),\n .I4(rstdiv0_sync_r1_reg_rep__22),\n .O(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] ));\n LUT6 #(\n .INIT(64'h5555555555555D55)) \n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_5 \n (.I0(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] ),\n .I1(insert_maint_r),\n .I2(rstdiv0_sync_r1_reg_rep__22),\n .I3(\\maint_controller.maint_srx_r1_reg ),\n .I4(\\maintenance_request.maint_zq_r_lcl_reg_0 ),\n .I5(\\maintenance_request.maint_sre_r_lcl_reg_0 ),\n .O(\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ));\n (* SOFT_HLUTNM = \"soft_lutpair1108\" *) \n LUT4 #(\n .INIT(16'h0222)) \n \\sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1 \n (.I0(ckesr_timer_r[1]),\n .I1(ckesr_timer_r[0]),\n .I2(\\maintenance_request.maint_sre_r_lcl_reg_0 ),\n .I3(insert_maint_r1),\n .O(\\sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1108\" *) \n LUT4 #(\n .INIT(16'hF888)) \n \\sr_cntrl.ckesr_timer.ckesr_timer_r[1]_i_1 \n (.I0(ckesr_timer_r[1]),\n .I1(ckesr_timer_r[0]),\n .I2(\\maintenance_request.maint_sre_r_lcl_reg_0 ),\n .I3(insert_maint_r1),\n .O(\\sr_cntrl.ckesr_timer.ckesr_timer_r[1]_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\sr_cntrl.ckesr_timer.ckesr_timer_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1_n_0 ),\n .Q(ckesr_timer_r[0]),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\sr_cntrl.ckesr_timer.ckesr_timer_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\sr_cntrl.ckesr_timer.ckesr_timer_r[1]_i_1_n_0 ),\n .Q(ckesr_timer_r[1]),\n .R(1'b0));\n FDRE \\sr_cntrl.sre_request_logic.sre_request_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(init_calib_complete_reg_rep__6),\n .Q(\\grant_r_reg[0]_0 ),\n .R(SR));\n FDRE \\zq_cntrl.zq_request_logic.zq_request_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(\\zq_cntrl.zq_request_logic.zq_request_r_reg_0 ),\n .Q(\\grant_r_reg[0] ),\n .R(SR));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[0]_i_1 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg[0]_0 ),\n .O(zq_timer_r0));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[0]_i_10 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [0]),\n .O(S[0]));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFFE)) \n \\zq_cntrl.zq_timer.zq_timer_r[0]_i_11 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [5]),\n .I1(\\zq_cntrl.zq_timer.zq_timer_r_reg [4]),\n .I2(\\zq_cntrl.zq_timer.zq_timer_r_reg [7]),\n .I3(\\zq_cntrl.zq_timer.zq_timer_r_reg [17]),\n .I4(\\zq_cntrl.zq_timer.zq_timer_r_reg [3]),\n .I5(\\zq_cntrl.zq_timer.zq_timer_r_reg [18]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_11_n_0 ));\n LUT5 #(\n .INIT(32'hAAA8AAAA)) \n \\zq_cntrl.zq_timer.zq_timer_r[0]_i_2 \n (.I0(maint_prescaler_tick_r),\n .I1(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0 ),\n .I2(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_5_n_0 ),\n .I3(\\zq_cntrl.zq_timer.zq_timer_r_reg [0]),\n .I4(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_6_n_0 ),\n .O(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFFFFE)) \n \\zq_cntrl.zq_timer.zq_timer_r[0]_i_4 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [13]),\n .I1(\\zq_cntrl.zq_timer.zq_timer_r_reg [10]),\n .I2(\\zq_cntrl.zq_timer.zq_timer_r_reg [11]),\n .I3(\\zq_cntrl.zq_timer.zq_timer_r_reg [12]),\n .I4(\\zq_cntrl.zq_timer.zq_timer_r_reg [14]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0 ));\n LUT4 #(\n .INIT(16'hFFFE)) \n \\zq_cntrl.zq_timer.zq_timer_r[0]_i_5 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [19]),\n .I1(\\zq_cntrl.zq_timer.zq_timer_r_reg [1]),\n .I2(\\zq_cntrl.zq_timer.zq_timer_r_reg [16]),\n .I3(\\zq_cntrl.zq_timer.zq_timer_r_reg [15]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'h00000001)) \n \\zq_cntrl.zq_timer.zq_timer_r[0]_i_6 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [6]),\n .I1(\\zq_cntrl.zq_timer.zq_timer_r_reg [8]),\n .I2(\\zq_cntrl.zq_timer.zq_timer_r_reg [2]),\n .I3(\\zq_cntrl.zq_timer.zq_timer_r_reg [9]),\n .I4(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_11_n_0 ),\n .O(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_6_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[0]_i_7 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [3]),\n .O(S[3]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[0]_i_8 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [2]),\n .O(S[2]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[0]_i_9 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [1]),\n .O(S[1]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[12]_i_2 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [15]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 [3]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[12]_i_3 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [14]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 [2]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[12]_i_4 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [13]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 [1]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[12]_i_5 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [12]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 [0]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[16]_i_2 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [19]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 [3]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[16]_i_3 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [18]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 [2]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[16]_i_4 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [17]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 [1]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[16]_i_5 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [16]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 [0]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[4]_i_2 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [7]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 [3]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[4]_i_3 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [6]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 [2]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[4]_i_4 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [5]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 [1]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[4]_i_5 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [4]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 [0]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[8]_i_2 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [11]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 [3]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[8]_i_3 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [10]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 [2]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[8]_i_4 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [9]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 [1]));\n LUT1 #(\n .INIT(2'h1)) \n \\zq_cntrl.zq_timer.zq_timer_r[8]_i_5 \n (.I0(\\zq_cntrl.zq_timer.zq_timer_r_reg [8]),\n .O(\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 [0]));\n FDRE \\zq_cntrl.zq_timer.zq_timer_r_reg[0] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(O[0]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [0]),\n .R(zq_timer_r0));\n FDSE \\zq_cntrl.zq_timer.zq_timer_r_reg[10] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 [2]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [10]),\n .S(zq_timer_r0));\n FDRE \\zq_cntrl.zq_timer.zq_timer_r_reg[11] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 [3]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [11]),\n .R(zq_timer_r0));\n FDRE \\zq_cntrl.zq_timer.zq_timer_r_reg[12] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 [0]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [12]),\n .R(zq_timer_r0));\n FDRE \\zq_cntrl.zq_timer.zq_timer_r_reg[13] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 [1]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [13]),\n .R(zq_timer_r0));\n FDSE \\zq_cntrl.zq_timer.zq_timer_r_reg[14] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 [2]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [14]),\n .S(zq_timer_r0));\n FDSE \\zq_cntrl.zq_timer.zq_timer_r_reg[15] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 [3]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [15]),\n .S(zq_timer_r0));\n FDSE \\zq_cntrl.zq_timer.zq_timer_r_reg[16] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 [0]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [16]),\n .S(zq_timer_r0));\n FDRE \\zq_cntrl.zq_timer.zq_timer_r_reg[17] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 [1]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [17]),\n .R(zq_timer_r0));\n FDRE \\zq_cntrl.zq_timer.zq_timer_r_reg[18] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 [2]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [18]),\n .R(zq_timer_r0));\n FDSE \\zq_cntrl.zq_timer.zq_timer_r_reg[19] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 [3]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [19]),\n .S(zq_timer_r0));\n FDRE \\zq_cntrl.zq_timer.zq_timer_r_reg[1] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(O[1]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [1]),\n .R(zq_timer_r0));\n FDRE \\zq_cntrl.zq_timer.zq_timer_r_reg[2] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(O[2]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [2]),\n .R(zq_timer_r0));\n FDRE \\zq_cntrl.zq_timer.zq_timer_r_reg[3] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(O[3]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [3]),\n .R(zq_timer_r0));\n FDRE \\zq_cntrl.zq_timer.zq_timer_r_reg[4] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 [0]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [4]),\n .R(zq_timer_r0));\n FDRE \\zq_cntrl.zq_timer.zq_timer_r_reg[5] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 [1]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [5]),\n .R(zq_timer_r0));\n FDRE \\zq_cntrl.zq_timer.zq_timer_r_reg[6] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 [2]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [6]),\n .R(zq_timer_r0));\n FDRE \\zq_cntrl.zq_timer.zq_timer_r_reg[7] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 [3]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [7]),\n .R(zq_timer_r0));\n FDRE \\zq_cntrl.zq_timer.zq_timer_r_reg[8] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 [0]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [8]),\n .R(zq_timer_r0));\n FDRE \\zq_cntrl.zq_timer.zq_timer_r_reg[9] \n (.C(CLK),\n .CE(\\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),\n .D(\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 [1]),\n .Q(\\zq_cntrl.zq_timer.zq_timer_r_reg [9]),\n .R(zq_timer_r0));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_rank_mach\n (act_delayed,\n maint_prescaler_tick_ns,\n upd_last_master_r,\n new_maint_rank_r,\n maint_req_r,\n \\periodic_read_request.upd_last_master_r_reg ,\n app_ref_ack,\n app_zq_ack,\n read_this_rank_r,\n inhbt_act_faw_r,\n maint_srx_r,\n maint_sre_r,\n zq_request_r,\n sre_request_r,\n maint_zq_r,\n periodic_rd_request_r,\n periodic_rd_r,\n app_ref_r,\n app_zq_r,\n periodic_rd_r_cnt,\n periodic_rd_grant_r,\n app_sr_active,\n maint_ref_zq_wip,\n periodic_rd_cntr1_r,\n refresh_bank_r,\n Q,\n \\refresh_timer.refresh_timer_r_reg[5] ,\n \\refresh_timer.refresh_timer_r_reg[4] ,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[0] ,\n \\maintenance_request.maint_sre_r_lcl_reg ,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ,\n \\last_master_r_reg[2] ,\n \\rtw_timer.rtw_cnt_r_reg[1] ,\n mc_cke_ns,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] ,\n \\refresh_generation.refresh_bank_r_reg[0] ,\n S,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[7] ,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[11] ,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[15] ,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[19] ,\n \\periodic_rd_generation.periodic_rd_request_r_reg ,\n \\inhbt_act_faw.inhbt_act_faw_r_reg ,\n \\wtr_timer.wtr_cnt_r_reg[1] ,\n \\grant_r_reg[3] ,\n act_this_rank,\n CLK,\n \\maint_controller.maint_wip_r_lcl_reg ,\n read_this_rank,\n SR,\n \\zq_cntrl.zq_request_logic.zq_request_r_reg ,\n init_calib_complete_reg_rep__6,\n \\periodic_rd_generation.periodic_rd_request_r_reg_0 ,\n maint_prescaler_r1,\n periodic_rd_ack_r_lcl_reg,\n \\refresh_generation.refresh_bank_r_reg[0]_0 ,\n app_zq_r_reg,\n \\periodic_read_request.periodic_rd_r_lcl_reg ,\n \\periodic_rd_generation.periodic_rd_request_r_reg_1 ,\n \\maintenance_request.maint_sre_r_lcl_reg_0 ,\n in0,\n \\refresh_generation.refresh_bank_r_reg[0]_1 ,\n \\periodic_read_request.periodic_rd_grant_r_reg[0] ,\n init_calib_complete_reg_rep__6_0,\n O,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ,\n \\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ,\n \\periodic_rd_generation.read_this_rank_r_reg ,\n init_calib_complete_reg_rep__6_1,\n app_sr_req,\n D,\n \\last_master_r_reg[2]_0 ,\n rstdiv0_sync_r1_reg_rep__21,\n \\grant_r_reg[0] ,\n cke_r,\n insert_maint_r1,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] ,\n insert_maint_r,\n rstdiv0_sync_r1_reg_rep__22,\n \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ,\n \\grant_r_reg[2] ,\n \\wr_this_rank_r_reg[0] ,\n \\wr_this_rank_r_reg[0]_0 ,\n \\wr_this_rank_r_reg[0]_1 ,\n rstdiv0_sync_r1_reg_rep__20,\n \\inhbt_act_faw.faw_cnt_r_reg[1] ,\n \\wtr_timer.wtr_cnt_r_reg[2] ,\n SS,\n \\maint_prescaler.maint_prescaler_r_reg[0] ,\n init_calib_complete_reg_rep__6_2,\n \\refresh_timer.refresh_timer_r_reg[0] );\n output act_delayed;\n output maint_prescaler_tick_ns;\n output upd_last_master_r;\n output new_maint_rank_r;\n output maint_req_r;\n output \\periodic_read_request.upd_last_master_r_reg ;\n output app_ref_ack;\n output app_zq_ack;\n output read_this_rank_r;\n output inhbt_act_faw_r;\n output maint_srx_r;\n output maint_sre_r;\n output zq_request_r;\n output sre_request_r;\n output maint_zq_r;\n output periodic_rd_request_r;\n output periodic_rd_r;\n output app_ref_r;\n output app_zq_r;\n output periodic_rd_r_cnt;\n output periodic_rd_grant_r;\n output app_sr_active;\n output maint_ref_zq_wip;\n output periodic_rd_cntr1_r;\n output refresh_bank_r;\n output [1:0]Q;\n output \\refresh_timer.refresh_timer_r_reg[5] ;\n output [1:0]\\refresh_timer.refresh_timer_r_reg[4] ;\n output \\zq_cntrl.zq_timer.zq_timer_r_reg[0] ;\n output [2:0]\\maintenance_request.maint_sre_r_lcl_reg ;\n output \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ;\n output [2:0]\\last_master_r_reg[2] ;\n output [0:0]\\rtw_timer.rtw_cnt_r_reg[1] ;\n output [0:0]mc_cke_ns;\n output \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ;\n output [0:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ;\n output \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] ;\n output \\refresh_generation.refresh_bank_r_reg[0] ;\n output [3:0]S;\n output [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[7] ;\n output [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[11] ;\n output [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[15] ;\n output [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[19] ;\n output \\periodic_rd_generation.periodic_rd_request_r_reg ;\n output [2:0]\\inhbt_act_faw.inhbt_act_faw_r_reg ;\n output [2:0]\\wtr_timer.wtr_cnt_r_reg[1] ;\n output \\grant_r_reg[3] ;\n input act_this_rank;\n input CLK;\n input \\maint_controller.maint_wip_r_lcl_reg ;\n input read_this_rank;\n input [0:0]SR;\n input \\zq_cntrl.zq_request_logic.zq_request_r_reg ;\n input init_calib_complete_reg_rep__6;\n input \\periodic_rd_generation.periodic_rd_request_r_reg_0 ;\n input maint_prescaler_r1;\n input periodic_rd_ack_r_lcl_reg;\n input \\refresh_generation.refresh_bank_r_reg[0]_0 ;\n input app_zq_r_reg;\n input \\periodic_read_request.periodic_rd_r_lcl_reg ;\n input \\periodic_rd_generation.periodic_rd_request_r_reg_1 ;\n input \\maintenance_request.maint_sre_r_lcl_reg_0 ;\n input in0;\n input \\refresh_generation.refresh_bank_r_reg[0]_1 ;\n input \\periodic_read_request.periodic_rd_grant_r_reg[0] ;\n input init_calib_complete_reg_rep__6_0;\n input [3:0]O;\n input [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ;\n input [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ;\n input [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ;\n input [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ;\n input \\periodic_rd_generation.read_this_rank_r_reg ;\n input init_calib_complete_reg_rep__6_1;\n input app_sr_req;\n input [1:0]D;\n input \\last_master_r_reg[2]_0 ;\n input rstdiv0_sync_r1_reg_rep__21;\n input \\grant_r_reg[0] ;\n input cke_r;\n input insert_maint_r1;\n input [0:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] ;\n input insert_maint_r;\n input rstdiv0_sync_r1_reg_rep__22;\n input [0:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ;\n input \\grant_r_reg[2] ;\n input \\wr_this_rank_r_reg[0] ;\n input \\wr_this_rank_r_reg[0]_0 ;\n input \\wr_this_rank_r_reg[0]_1 ;\n input rstdiv0_sync_r1_reg_rep__20;\n input [2:0]\\inhbt_act_faw.faw_cnt_r_reg[1] ;\n input [0:0]\\wtr_timer.wtr_cnt_r_reg[2] ;\n input [0:0]SS;\n input [0:0]\\maint_prescaler.maint_prescaler_r_reg[0] ;\n input [0:0]init_calib_complete_reg_rep__6_2;\n input [0:0]\\refresh_timer.refresh_timer_r_reg[0] ;\n\n wire CLK;\n wire [1:0]D;\n wire [3:0]O;\n wire [1:0]Q;\n wire [3:0]S;\n wire [0:0]SR;\n wire [0:0]SS;\n wire act_delayed;\n wire act_this_rank;\n wire app_ref_ack;\n wire app_ref_r;\n wire app_sr_active;\n wire app_sr_req;\n wire app_zq_ack;\n wire app_zq_r;\n wire app_zq_r_reg;\n wire cke_r;\n wire \\grant_r_reg[0] ;\n wire \\grant_r_reg[2] ;\n wire \\grant_r_reg[3] ;\n wire in0;\n wire [2:0]\\inhbt_act_faw.faw_cnt_r_reg[1] ;\n wire [2:0]\\inhbt_act_faw.inhbt_act_faw_r_reg ;\n wire inhbt_act_faw_r;\n wire init_calib_complete_reg_rep__6;\n wire init_calib_complete_reg_rep__6_0;\n wire init_calib_complete_reg_rep__6_1;\n wire [0:0]init_calib_complete_reg_rep__6_2;\n wire insert_maint_r;\n wire insert_maint_r1;\n wire [2:0]\\last_master_r_reg[2] ;\n wire \\last_master_r_reg[2]_0 ;\n wire \\maint_controller.maint_wip_r_lcl_reg ;\n wire [0:0]\\maint_prescaler.maint_prescaler_r_reg[0] ;\n wire maint_prescaler_r1;\n wire maint_prescaler_tick_ns;\n wire maint_prescaler_tick_r;\n wire maint_ref_zq_wip;\n wire maint_req_r;\n wire maint_sre_r;\n wire maint_srx_r;\n wire maint_zq_r;\n wire [2:0]\\maintenance_request.maint_sre_r_lcl_reg ;\n wire \\maintenance_request.maint_sre_r_lcl_reg_0 ;\n wire [0:0]mc_cke_ns;\n wire new_maint_rank_r;\n wire periodic_rd_ack_r_lcl_reg;\n wire periodic_rd_cntr1_r;\n wire \\periodic_rd_generation.periodic_rd_request_r_reg ;\n wire \\periodic_rd_generation.periodic_rd_request_r_reg_0 ;\n wire \\periodic_rd_generation.periodic_rd_request_r_reg_1 ;\n wire \\periodic_rd_generation.read_this_rank_r_reg ;\n wire periodic_rd_grant_r;\n wire periodic_rd_r;\n wire periodic_rd_r_cnt;\n wire periodic_rd_request_r;\n wire \\periodic_read_request.periodic_rd_grant_r_reg[0] ;\n wire \\periodic_read_request.periodic_rd_r_lcl_reg ;\n wire \\periodic_read_request.upd_last_master_r_reg ;\n wire read_this_rank;\n wire read_this_rank_r;\n wire refresh_bank_r;\n wire \\refresh_generation.refresh_bank_r_reg[0] ;\n wire \\refresh_generation.refresh_bank_r_reg[0]_0 ;\n wire \\refresh_generation.refresh_bank_r_reg[0]_1 ;\n wire [0:0]\\refresh_timer.refresh_timer_r_reg[0] ;\n wire [1:0]\\refresh_timer.refresh_timer_r_reg[4] ;\n wire \\refresh_timer.refresh_timer_r_reg[5] ;\n wire [0:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ;\n wire [0:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ;\n wire [0:0]\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] ;\n wire \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ;\n wire \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] ;\n wire \\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ;\n wire rstdiv0_sync_r1_reg_rep__20;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire rstdiv0_sync_r1_reg_rep__22;\n wire [0:0]\\rtw_timer.rtw_cnt_r_reg[1] ;\n wire sre_request_r;\n wire upd_last_master_r;\n wire \\wr_this_rank_r_reg[0] ;\n wire \\wr_this_rank_r_reg[0]_0 ;\n wire \\wr_this_rank_r_reg[0]_1 ;\n wire [2:0]\\wtr_timer.wtr_cnt_r_reg[1] ;\n wire [0:0]\\wtr_timer.wtr_cnt_r_reg[2] ;\n wire \\zq_cntrl.zq_request_logic.zq_request_r_reg ;\n wire \\zq_cntrl.zq_timer.zq_timer_r_reg[0] ;\n wire [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[11] ;\n wire [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ;\n wire [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[15] ;\n wire [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ;\n wire [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[19] ;\n wire [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ;\n wire [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[7] ;\n wire [3:0]\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ;\n wire zq_request_r;\n\n ddr3_if_mig_7series_v4_0_rank_cntrl \\rank_cntrl[0].rank_cntrl0 \n (.CLK(CLK),\n .SR(SR),\n .act_delayed(act_delayed),\n .act_this_rank(act_this_rank),\n .\\grant_r_reg[0] (refresh_bank_r),\n .\\grant_r_reg[0]_0 (\\grant_r_reg[0] ),\n .\\grant_r_reg[2] (\\grant_r_reg[2] ),\n .\\grant_r_reg[3] (\\grant_r_reg[3] ),\n .\\inhbt_act_faw.faw_cnt_r_reg[1]_0 (\\inhbt_act_faw.faw_cnt_r_reg[1] ),\n .\\inhbt_act_faw.inhbt_act_faw_r_reg_0 (\\inhbt_act_faw.inhbt_act_faw_r_reg ),\n .inhbt_act_faw_r(inhbt_act_faw_r),\n .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6_0),\n .init_calib_complete_reg_rep__6_0(init_calib_complete_reg_rep__6_1),\n .maint_prescaler_tick_r(maint_prescaler_tick_r),\n .periodic_rd_cntr1_r(periodic_rd_cntr1_r),\n .\\periodic_rd_generation.periodic_rd_request_r_reg_0 (\\periodic_rd_generation.periodic_rd_request_r_reg ),\n .\\periodic_rd_generation.periodic_rd_request_r_reg_1 (\\periodic_rd_generation.periodic_rd_request_r_reg_0 ),\n .\\periodic_rd_generation.read_this_rank_r_reg_0 (\\periodic_rd_generation.read_this_rank_r_reg ),\n .periodic_rd_request_r(periodic_rd_request_r),\n .\\periodic_read_request.periodic_rd_grant_r_reg[0] (\\periodic_read_request.periodic_rd_grant_r_reg[0] ),\n .read_this_rank(read_this_rank),\n .read_this_rank_r(read_this_rank_r),\n .rstdiv0_sync_r1_reg_rep__20(rstdiv0_sync_r1_reg_rep__20),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22),\n .\\rtw_timer.rtw_cnt_r_reg[1]_0 (\\rtw_timer.rtw_cnt_r_reg[1] ),\n .\\wr_this_rank_r_reg[0] (\\wr_this_rank_r_reg[0] ),\n .\\wr_this_rank_r_reg[0]_0 (\\wr_this_rank_r_reg[0]_0 ),\n .\\wr_this_rank_r_reg[0]_1 (\\wr_this_rank_r_reg[0]_1 ),\n .\\wtr_timer.wtr_cnt_r_reg[1]_0 (\\wtr_timer.wtr_cnt_r_reg[1] ),\n .\\wtr_timer.wtr_cnt_r_reg[2]_0 (\\wtr_timer.wtr_cnt_r_reg[2] ));\n ddr3_if_mig_7series_v4_0_rank_common rank_common0\n (.CLK(CLK),\n .D(D),\n .O(O),\n .Q(Q),\n .S(S),\n .SR(SR),\n .SS(SS),\n .app_ref_ack(app_ref_ack),\n .app_ref_r(app_ref_r),\n .app_sr_active(app_sr_active),\n .app_sr_req(app_sr_req),\n .app_zq_ack(app_zq_ack),\n .app_zq_r(app_zq_r),\n .app_zq_r_reg_0(app_zq_r_reg),\n .cke_r(cke_r),\n .\\grant_r_reg[0] (zq_request_r),\n .\\grant_r_reg[0]_0 (sre_request_r),\n .in0(in0),\n .init_calib_complete_reg_rep__6(init_calib_complete_reg_rep__6),\n .init_calib_complete_reg_rep__6_0(init_calib_complete_reg_rep__6_1),\n .init_calib_complete_reg_rep__6_1(init_calib_complete_reg_rep__6_2),\n .insert_maint_r(insert_maint_r),\n .insert_maint_r1(insert_maint_r1),\n .\\last_master_r_reg[2] (\\last_master_r_reg[2] ),\n .\\last_master_r_reg[2]_0 (\\last_master_r_reg[2]_0 ),\n .\\maint_controller.maint_srx_r1_reg (maint_srx_r),\n .\\maint_controller.maint_wip_r_lcl_reg (\\maint_controller.maint_wip_r_lcl_reg ),\n .\\maint_prescaler.maint_prescaler_r_reg[0]_0 (\\maint_prescaler.maint_prescaler_r_reg[0] ),\n .maint_prescaler_r1(maint_prescaler_r1),\n .maint_prescaler_tick_ns(maint_prescaler_tick_ns),\n .maint_prescaler_tick_r(maint_prescaler_tick_r),\n .maint_ref_zq_wip(maint_ref_zq_wip),\n .maint_req_r(maint_req_r),\n .\\maintenance_request.maint_req_r_lcl_reg_0 (new_maint_rank_r),\n .\\maintenance_request.maint_sre_r_lcl_reg_0 (maint_sre_r),\n .\\maintenance_request.maint_sre_r_lcl_reg_1 (\\maintenance_request.maint_sre_r_lcl_reg ),\n .\\maintenance_request.maint_sre_r_lcl_reg_2 (\\maintenance_request.maint_sre_r_lcl_reg_0 ),\n .\\maintenance_request.maint_zq_r_lcl_reg_0 (maint_zq_r),\n .\\maintenance_request.new_maint_rank_r_reg_0 (upd_last_master_r),\n .mc_cke_ns(mc_cke_ns),\n .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg),\n .\\periodic_rd_generation.periodic_rd_request_r_reg (\\periodic_rd_generation.periodic_rd_request_r_reg_1 ),\n .periodic_rd_grant_r(periodic_rd_grant_r),\n .periodic_rd_r(periodic_rd_r),\n .periodic_rd_r_cnt(periodic_rd_r_cnt),\n .periodic_rd_request_r(periodic_rd_request_r),\n .\\periodic_read_request.periodic_rd_r_lcl_reg_0 (\\periodic_read_request.periodic_rd_r_lcl_reg ),\n .\\periodic_read_request.upd_last_master_r_reg_0 (\\periodic_read_request.upd_last_master_r_reg ),\n .\\refresh_generation.refresh_bank_r_reg[0] (\\refresh_generation.refresh_bank_r_reg[0] ),\n .\\refresh_generation.refresh_bank_r_reg[0]_0 (\\refresh_generation.refresh_bank_r_reg[0]_0 ),\n .\\refresh_generation.refresh_bank_r_reg[0]_1 (\\refresh_generation.refresh_bank_r_reg[0]_1 ),\n .\\refresh_generation.refresh_bank_r_reg[0]_2 (refresh_bank_r),\n .\\refresh_timer.refresh_timer_r_reg[0]_0 (\\refresh_timer.refresh_timer_r_reg[0] ),\n .\\refresh_timer.refresh_timer_r_reg[4]_0 (\\refresh_timer.refresh_timer_r_reg[4] ),\n .\\refresh_timer.refresh_timer_r_reg[5]_0 (\\refresh_timer.refresh_timer_r_reg[5] ),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] (\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 (\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] (\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] ),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] (\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] (\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] ),\n .\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] (\\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ),\n .rstdiv0_sync_r1_reg_rep__21(rstdiv0_sync_r1_reg_rep__21),\n .rstdiv0_sync_r1_reg_rep__22(rstdiv0_sync_r1_reg_rep__22),\n .\\zq_cntrl.zq_request_logic.zq_request_r_reg_0 (\\zq_cntrl.zq_request_logic.zq_request_r_reg ),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[0]_0 (\\zq_cntrl.zq_timer.zq_timer_r_reg[0] ),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 (\\zq_cntrl.zq_timer.zq_timer_r_reg[11] ),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 (\\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 (\\zq_cntrl.zq_timer.zq_timer_r_reg[15] ),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 (\\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 (\\zq_cntrl.zq_timer.zq_timer_r_reg[19] ),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 (\\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 (\\zq_cntrl.zq_timer.zq_timer_r_reg[7] ),\n .\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 (\\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_round_robin_arb\n (\\maintenance_request.maint_sre_r_lcl_reg ,\n Q,\n \\maintenance_request.maint_srx_r_lcl_reg ,\n \\last_master_r_reg[2]_0 ,\n \\maintenance_request.maint_zq_r_lcl_reg ,\n \\maintenance_request.upd_last_master_r_reg ,\n \\maintenance_request.maint_sre_r_lcl_reg_0 ,\n ckesr_timer_r,\n app_sr_req,\n \\maintenance_request.maint_srx_r_lcl_reg_0 ,\n inhbt_srx,\n D,\n init_calib_complete_reg_rep__6,\n \\refresh_generation.refresh_bank_r_reg[0] ,\n \\sr_cntrl.sre_request_logic.sre_request_r_reg ,\n \\zq_cntrl.zq_request_logic.zq_request_r_reg ,\n \\last_master_r_reg[2]_1 ,\n \\maintenance_request.upd_last_master_r_reg_0 ,\n \\maintenance_request.new_maint_rank_r_reg ,\n rstdiv0_sync_r1_reg_rep__21,\n \\maintenance_request.maint_zq_r_lcl_reg_0 ,\n CLK);\n output \\maintenance_request.maint_sre_r_lcl_reg ;\n output [2:0]Q;\n output \\maintenance_request.maint_srx_r_lcl_reg ;\n output [2:0]\\last_master_r_reg[2]_0 ;\n output \\maintenance_request.maint_zq_r_lcl_reg ;\n input \\maintenance_request.upd_last_master_r_reg ;\n input \\maintenance_request.maint_sre_r_lcl_reg_0 ;\n input [1:0]ckesr_timer_r;\n input app_sr_req;\n input \\maintenance_request.maint_srx_r_lcl_reg_0 ;\n input inhbt_srx;\n input [1:0]D;\n input init_calib_complete_reg_rep__6;\n input \\refresh_generation.refresh_bank_r_reg[0] ;\n input \\sr_cntrl.sre_request_logic.sre_request_r_reg ;\n input \\zq_cntrl.zq_request_logic.zq_request_r_reg ;\n input \\last_master_r_reg[2]_1 ;\n input \\maintenance_request.upd_last_master_r_reg_0 ;\n input \\maintenance_request.new_maint_rank_r_reg ;\n input rstdiv0_sync_r1_reg_rep__21;\n input \\maintenance_request.maint_zq_r_lcl_reg_0 ;\n input CLK;\n\n wire CLK;\n wire [1:0]D;\n wire [2:0]Q;\n wire app_sr_req;\n wire [1:0]ckesr_timer_r;\n wire \\grant_r[0]_i_1_n_0 ;\n wire \\grant_r[1]_i_1_n_0 ;\n wire \\grant_r[2]_i_1_n_0 ;\n wire inhbt_srx;\n wire init_calib_complete_reg_rep__6;\n wire \\last_master_r[2]_i_1_n_0 ;\n wire [2:0]\\last_master_r_reg[2]_0 ;\n wire \\last_master_r_reg[2]_1 ;\n wire \\maintenance_request.maint_sre_r_lcl_reg ;\n wire \\maintenance_request.maint_sre_r_lcl_reg_0 ;\n wire \\maintenance_request.maint_srx_r_lcl_reg ;\n wire \\maintenance_request.maint_srx_r_lcl_reg_0 ;\n wire \\maintenance_request.maint_zq_r_lcl_reg ;\n wire \\maintenance_request.maint_zq_r_lcl_reg_0 ;\n wire \\maintenance_request.new_maint_rank_r_reg ;\n wire \\maintenance_request.upd_last_master_r_reg ;\n wire \\maintenance_request.upd_last_master_r_reg_0 ;\n wire \\refresh_generation.refresh_bank_r_reg[0] ;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire \\sr_cntrl.sre_request_logic.sre_request_r_reg ;\n wire \\zq_cntrl.zq_request_logic.zq_request_r_reg ;\n\n LUT6 #(\n .INIT(64'h0000000C040C040C)) \n \\grant_r[0]_i_1 \n (.I0(D[1]),\n .I1(init_calib_complete_reg_rep__6),\n .I2(\\refresh_generation.refresh_bank_r_reg[0] ),\n .I3(\\sr_cntrl.sre_request_logic.sre_request_r_reg ),\n .I4(\\zq_cntrl.zq_request_logic.zq_request_r_reg ),\n .I5(D[0]),\n .O(\\grant_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0000A0808080A080)) \n \\grant_r[1]_i_1 \n (.I0(\\zq_cntrl.zq_request_logic.zq_request_r_reg ),\n .I1(\\refresh_generation.refresh_bank_r_reg[0] ),\n .I2(init_calib_complete_reg_rep__6),\n .I3(\\last_master_r_reg[2]_1 ),\n .I4(D[1]),\n .I5(\\sr_cntrl.sre_request_logic.sre_request_r_reg ),\n .O(\\grant_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h0EAE000000000000)) \n \\grant_r[2]_i_1 \n (.I0(\\last_master_r_reg[2]_1 ),\n .I1(\\refresh_generation.refresh_bank_r_reg[0] ),\n .I2(\\zq_cntrl.zq_request_logic.zq_request_r_reg ),\n .I3(D[0]),\n .I4(init_calib_complete_reg_rep__6),\n .I5(\\sr_cntrl.sre_request_logic.sre_request_r_reg ),\n .O(\\grant_r[2]_i_1_n_0 ));\n FDRE \\grant_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\grant_r[0]_i_1_n_0 ),\n .Q(Q[0]),\n .R(1'b0));\n FDRE \\grant_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\grant_r[1]_i_1_n_0 ),\n .Q(Q[1]),\n .R(1'b0));\n FDRE \\grant_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\grant_r[2]_i_1_n_0 ),\n .Q(Q[2]),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hFFFFFB08)) \n \\last_master_r[2]_i_1 \n (.I0(Q[2]),\n .I1(\\maintenance_request.upd_last_master_r_reg_0 ),\n .I2(\\maintenance_request.new_maint_rank_r_reg ),\n .I3(\\last_master_r_reg[2]_0 [2]),\n .I4(rstdiv0_sync_r1_reg_rep__21),\n .O(\\last_master_r[2]_i_1_n_0 ));\n FDRE \\last_master_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(D[0]),\n .Q(\\last_master_r_reg[2]_0 [0]),\n .R(1'b0));\n FDRE \\last_master_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(D[1]),\n .Q(\\last_master_r_reg[2]_0 [1]),\n .R(1'b0));\n FDRE \\last_master_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\last_master_r[2]_i_1_n_0 ),\n .Q(\\last_master_r_reg[2]_0 [2]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hB8B8B8B8B8B8B888)) \n \\maintenance_request.maint_sre_r_lcl_i_1 \n (.I0(Q[2]),\n .I1(\\maintenance_request.upd_last_master_r_reg ),\n .I2(\\maintenance_request.maint_sre_r_lcl_reg_0 ),\n .I3(ckesr_timer_r[0]),\n .I4(ckesr_timer_r[1]),\n .I5(app_sr_req),\n .O(\\maintenance_request.maint_sre_r_lcl_reg ));\n LUT6 #(\n .INIT(64'h000000FFA2A2A2A2)) \n \\maintenance_request.maint_srx_r_lcl_i_1 \n (.I0(\\maintenance_request.maint_srx_r_lcl_reg_0 ),\n .I1(\\maintenance_request.upd_last_master_r_reg ),\n .I2(Q[2]),\n .I3(app_sr_req),\n .I4(inhbt_srx),\n .I5(\\maintenance_request.maint_sre_r_lcl_reg_0 ),\n .O(\\maintenance_request.maint_srx_r_lcl_reg ));\n LUT4 #(\n .INIT(16'hBA8A)) \n \\maintenance_request.maint_zq_r_lcl_i_1 \n (.I0(\\maintenance_request.maint_zq_r_lcl_reg_0 ),\n .I1(\\maintenance_request.new_maint_rank_r_reg ),\n .I2(\\maintenance_request.upd_last_master_r_reg_0 ),\n .I3(Q[1]),\n .O(\\maintenance_request.maint_zq_r_lcl_reg ));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_round_robin_arb\" *) \nmodule ddr3_if_mig_7series_v4_0_round_robin_arb__parameterized1\n (D,\n \\last_master_r_reg[3]_0 ,\n Q,\n mc_we_n_ns,\n \\cmd_pipe_plus.mc_bank_reg[8] ,\n \\cmd_pipe_plus.mc_address_reg[44] ,\n \\last_master_r_reg[3]_1 ,\n auto_pre_r_lcl_reg,\n auto_pre_r_lcl_reg_0,\n ras_timer_zero_r_reg,\n ras_timer_zero_r_reg_0,\n ras_timer_zero_r_reg_1,\n auto_pre_r_lcl_reg_1,\n ras_timer_zero_r_reg_2,\n auto_pre_r_lcl_reg_2,\n rstdiv0_sync_r1_reg_rep__21,\n \\pre_4_1_1T_arb.granted_pre_r_reg ,\n act_wait_r_lcl_reg,\n act_wait_r_lcl_reg_0,\n act_wait_r_lcl_reg_1,\n row_cmd_wr,\n rstdiv0_sync_r1_reg_rep__22,\n \\req_bank_r_lcl_reg[2] ,\n \\req_bank_r_lcl_reg[2]_0 ,\n \\req_bank_r_lcl_reg[2]_1 ,\n \\grant_r_reg[0]_0 ,\n req_row_r,\n \\grant_r_reg[0]_1 ,\n \\grant_r_reg[0]_2 ,\n \\grant_r_reg[0]_3 ,\n \\grant_r_reg[0]_4 ,\n \\grant_r_reg[0]_5 ,\n \\grant_r_reg[0]_6 ,\n \\grant_r_reg[0]_7 ,\n \\grant_r_reg[0]_8 ,\n \\grant_r_reg[0]_9 ,\n \\grant_r_reg[0]_10 ,\n \\grant_r_reg[0]_11 ,\n \\grant_r_reg[0]_12 ,\n \\grant_r_reg[0]_13 ,\n \\req_bank_r_lcl_reg[0] ,\n \\req_bank_r_lcl_reg[1] ,\n CLK);\n output [1:0]D;\n output [0:0]\\last_master_r_reg[3]_0 ;\n output [3:0]Q;\n output [0:0]mc_we_n_ns;\n output [2:0]\\cmd_pipe_plus.mc_bank_reg[8] ;\n output [13:0]\\cmd_pipe_plus.mc_address_reg[44] ;\n input \\last_master_r_reg[3]_1 ;\n input auto_pre_r_lcl_reg;\n input auto_pre_r_lcl_reg_0;\n input ras_timer_zero_r_reg;\n input ras_timer_zero_r_reg_0;\n input ras_timer_zero_r_reg_1;\n input auto_pre_r_lcl_reg_1;\n input ras_timer_zero_r_reg_2;\n input auto_pre_r_lcl_reg_2;\n input rstdiv0_sync_r1_reg_rep__21;\n input \\pre_4_1_1T_arb.granted_pre_r_reg ;\n input act_wait_r_lcl_reg;\n input act_wait_r_lcl_reg_0;\n input act_wait_r_lcl_reg_1;\n input [0:0]row_cmd_wr;\n input rstdiv0_sync_r1_reg_rep__22;\n input \\req_bank_r_lcl_reg[2] ;\n input [2:0]\\req_bank_r_lcl_reg[2]_0 ;\n input [2:0]\\req_bank_r_lcl_reg[2]_1 ;\n input \\grant_r_reg[0]_0 ;\n input [27:0]req_row_r;\n input \\grant_r_reg[0]_1 ;\n input \\grant_r_reg[0]_2 ;\n input \\grant_r_reg[0]_3 ;\n input \\grant_r_reg[0]_4 ;\n input \\grant_r_reg[0]_5 ;\n input \\grant_r_reg[0]_6 ;\n input \\grant_r_reg[0]_7 ;\n input \\grant_r_reg[0]_8 ;\n input \\grant_r_reg[0]_9 ;\n input \\grant_r_reg[0]_10 ;\n input \\grant_r_reg[0]_11 ;\n input \\grant_r_reg[0]_12 ;\n input \\grant_r_reg[0]_13 ;\n input \\req_bank_r_lcl_reg[0] ;\n input \\req_bank_r_lcl_reg[1] ;\n input CLK;\n\n wire CLK;\n wire [1:0]D;\n wire [3:0]Q;\n wire act_wait_r_lcl_reg;\n wire act_wait_r_lcl_reg_0;\n wire act_wait_r_lcl_reg_1;\n wire auto_pre_r_lcl_reg;\n wire auto_pre_r_lcl_reg_0;\n wire auto_pre_r_lcl_reg_1;\n wire auto_pre_r_lcl_reg_2;\n wire [13:0]\\cmd_pipe_plus.mc_address_reg[44] ;\n wire [2:0]\\cmd_pipe_plus.mc_bank_reg[8] ;\n wire \\cmd_pipe_plus.mc_we_n[2]_i_2_n_0 ;\n wire \\grant_r[0]_i_1__2_n_0 ;\n wire \\grant_r[1]_i_1__2_n_0 ;\n wire \\grant_r[1]_i_2__1_n_0 ;\n wire \\grant_r[2]_i_1__2_n_0 ;\n wire \\grant_r[3]_i_1__1_n_0 ;\n wire \\grant_r[3]_i_2__1_n_0 ;\n wire \\grant_r_reg[0]_0 ;\n wire \\grant_r_reg[0]_1 ;\n wire \\grant_r_reg[0]_10 ;\n wire \\grant_r_reg[0]_11 ;\n wire \\grant_r_reg[0]_12 ;\n wire \\grant_r_reg[0]_13 ;\n wire \\grant_r_reg[0]_2 ;\n wire \\grant_r_reg[0]_3 ;\n wire \\grant_r_reg[0]_4 ;\n wire \\grant_r_reg[0]_5 ;\n wire \\grant_r_reg[0]_6 ;\n wire \\grant_r_reg[0]_7 ;\n wire \\grant_r_reg[0]_8 ;\n wire \\grant_r_reg[0]_9 ;\n wire [2:0]last_master_r;\n wire \\last_master_r[1]_i_1__1_n_0 ;\n wire \\last_master_r[3]_i_1__1_n_0 ;\n wire [0:0]\\last_master_r_reg[3]_0 ;\n wire \\last_master_r_reg[3]_1 ;\n wire [0:0]mc_we_n_ns;\n wire \\pre_4_1_1T_arb.granted_pre_r_reg ;\n wire ras_timer_zero_r_reg;\n wire ras_timer_zero_r_reg_0;\n wire ras_timer_zero_r_reg_1;\n wire ras_timer_zero_r_reg_2;\n wire \\req_bank_r_lcl_reg[0] ;\n wire \\req_bank_r_lcl_reg[1] ;\n wire \\req_bank_r_lcl_reg[2] ;\n wire [2:0]\\req_bank_r_lcl_reg[2]_0 ;\n wire [2:0]\\req_bank_r_lcl_reg[2]_1 ;\n wire [27:0]req_row_r;\n wire [0:0]row_cmd_wr;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire rstdiv0_sync_r1_reg_rep__22;\n\n LUT6 #(\n .INIT(64'hFBFFEAFFEAFFEAFF)) \n \\cmd_pipe_plus.mc_address[30]_i_1 \n (.I0(\\grant_r_reg[0]_0 ),\n .I1(Q[3]),\n .I2(req_row_r[14]),\n .I3(\\pre_4_1_1T_arb.granted_pre_r_reg ),\n .I4(req_row_r[0]),\n .I5(Q[2]),\n .O(\\cmd_pipe_plus.mc_address_reg[44] [0]));\n LUT6 #(\n .INIT(64'hFBFFEAFFEAFFEAFF)) \n \\cmd_pipe_plus.mc_address[31]_i_1 \n (.I0(\\grant_r_reg[0]_1 ),\n .I1(Q[3]),\n .I2(req_row_r[15]),\n .I3(\\pre_4_1_1T_arb.granted_pre_r_reg ),\n .I4(req_row_r[1]),\n .I5(Q[2]),\n .O(\\cmd_pipe_plus.mc_address_reg[44] [1]));\n LUT6 #(\n .INIT(64'hFBFFEAFFEAFFEAFF)) \n \\cmd_pipe_plus.mc_address[32]_i_1 \n (.I0(\\grant_r_reg[0]_2 ),\n .I1(Q[3]),\n .I2(req_row_r[16]),\n .I3(\\pre_4_1_1T_arb.granted_pre_r_reg ),\n .I4(req_row_r[2]),\n .I5(Q[2]),\n .O(\\cmd_pipe_plus.mc_address_reg[44] [2]));\n LUT6 #(\n .INIT(64'hFBFFEAFFEAFFEAFF)) \n \\cmd_pipe_plus.mc_address[33]_i_1 \n (.I0(\\grant_r_reg[0]_3 ),\n .I1(Q[3]),\n .I2(req_row_r[17]),\n .I3(\\pre_4_1_1T_arb.granted_pre_r_reg ),\n .I4(req_row_r[3]),\n .I5(Q[2]),\n .O(\\cmd_pipe_plus.mc_address_reg[44] [3]));\n LUT6 #(\n .INIT(64'hFBFFEAFFEAFFEAFF)) \n \\cmd_pipe_plus.mc_address[34]_i_1 \n (.I0(\\grant_r_reg[0]_4 ),\n .I1(Q[3]),\n .I2(req_row_r[18]),\n .I3(\\pre_4_1_1T_arb.granted_pre_r_reg ),\n .I4(req_row_r[4]),\n .I5(Q[2]),\n .O(\\cmd_pipe_plus.mc_address_reg[44] [4]));\n LUT6 #(\n .INIT(64'hFBFFEAFFEAFFEAFF)) \n \\cmd_pipe_plus.mc_address[35]_i_1 \n (.I0(\\grant_r_reg[0]_5 ),\n .I1(Q[3]),\n .I2(req_row_r[19]),\n .I3(\\pre_4_1_1T_arb.granted_pre_r_reg ),\n .I4(req_row_r[5]),\n .I5(Q[2]),\n .O(\\cmd_pipe_plus.mc_address_reg[44] [5]));\n LUT6 #(\n .INIT(64'hFBFFEAFFEAFFEAFF)) \n \\cmd_pipe_plus.mc_address[36]_i_1 \n (.I0(\\grant_r_reg[0]_6 ),\n .I1(Q[3]),\n .I2(req_row_r[20]),\n .I3(\\pre_4_1_1T_arb.granted_pre_r_reg ),\n .I4(req_row_r[6]),\n .I5(Q[2]),\n .O(\\cmd_pipe_plus.mc_address_reg[44] [6]));\n LUT6 #(\n .INIT(64'hFBFFEAFFEAFFEAFF)) \n \\cmd_pipe_plus.mc_address[37]_i_1 \n (.I0(\\grant_r_reg[0]_7 ),\n .I1(Q[3]),\n .I2(req_row_r[21]),\n .I3(\\pre_4_1_1T_arb.granted_pre_r_reg ),\n .I4(req_row_r[7]),\n .I5(Q[2]),\n .O(\\cmd_pipe_plus.mc_address_reg[44] [7]));\n LUT6 #(\n .INIT(64'hFBFFEAFFEAFFEAFF)) \n \\cmd_pipe_plus.mc_address[38]_i_1 \n (.I0(\\grant_r_reg[0]_8 ),\n .I1(Q[3]),\n .I2(req_row_r[22]),\n .I3(\\pre_4_1_1T_arb.granted_pre_r_reg ),\n .I4(req_row_r[8]),\n .I5(Q[2]),\n .O(\\cmd_pipe_plus.mc_address_reg[44] [8]));\n LUT6 #(\n .INIT(64'hFBFFEAFFEAFFEAFF)) \n \\cmd_pipe_plus.mc_address[39]_i_1 \n (.I0(\\grant_r_reg[0]_9 ),\n .I1(Q[3]),\n .I2(req_row_r[23]),\n .I3(\\pre_4_1_1T_arb.granted_pre_r_reg ),\n .I4(req_row_r[9]),\n .I5(Q[2]),\n .O(\\cmd_pipe_plus.mc_address_reg[44] [9]));\n LUT6 #(\n .INIT(64'hFBFFEAFFEAFFEAFF)) \n \\cmd_pipe_plus.mc_address[41]_i_1 \n (.I0(\\grant_r_reg[0]_10 ),\n .I1(Q[3]),\n .I2(req_row_r[24]),\n .I3(\\pre_4_1_1T_arb.granted_pre_r_reg ),\n .I4(req_row_r[10]),\n .I5(Q[2]),\n .O(\\cmd_pipe_plus.mc_address_reg[44] [10]));\n LUT6 #(\n .INIT(64'hFBFFEAFFEAFFEAFF)) \n \\cmd_pipe_plus.mc_address[42]_i_1 \n (.I0(\\grant_r_reg[0]_11 ),\n .I1(Q[3]),\n .I2(req_row_r[25]),\n .I3(\\pre_4_1_1T_arb.granted_pre_r_reg ),\n .I4(req_row_r[11]),\n .I5(Q[2]),\n .O(\\cmd_pipe_plus.mc_address_reg[44] [11]));\n LUT6 #(\n .INIT(64'hFBFFEAFFEAFFEAFF)) \n \\cmd_pipe_plus.mc_address[43]_i_1 \n (.I0(\\grant_r_reg[0]_12 ),\n .I1(Q[3]),\n .I2(req_row_r[26]),\n .I3(\\pre_4_1_1T_arb.granted_pre_r_reg ),\n .I4(req_row_r[12]),\n .I5(Q[2]),\n .O(\\cmd_pipe_plus.mc_address_reg[44] [12]));\n LUT6 #(\n .INIT(64'hFBFFEAFFEAFFEAFF)) \n \\cmd_pipe_plus.mc_address[44]_i_1 \n (.I0(\\grant_r_reg[0]_13 ),\n .I1(Q[3]),\n .I2(req_row_r[27]),\n .I3(\\pre_4_1_1T_arb.granted_pre_r_reg ),\n .I4(req_row_r[13]),\n .I5(Q[2]),\n .O(\\cmd_pipe_plus.mc_address_reg[44] [13]));\n LUT6 #(\n .INIT(64'hEFFFEAFFEAFFEAFF)) \n \\cmd_pipe_plus.mc_bank[6]_i_1 \n (.I0(\\req_bank_r_lcl_reg[0] ),\n .I1(\\req_bank_r_lcl_reg[2]_0 [0]),\n .I2(Q[3]),\n .I3(\\pre_4_1_1T_arb.granted_pre_r_reg ),\n .I4(\\req_bank_r_lcl_reg[2]_1 [0]),\n .I5(Q[2]),\n .O(\\cmd_pipe_plus.mc_bank_reg[8] [0]));\n LUT6 #(\n .INIT(64'hEFFFEAFFEAFFEAFF)) \n \\cmd_pipe_plus.mc_bank[7]_i_1 \n (.I0(\\req_bank_r_lcl_reg[1] ),\n .I1(\\req_bank_r_lcl_reg[2]_0 [1]),\n .I2(Q[3]),\n .I3(\\pre_4_1_1T_arb.granted_pre_r_reg ),\n .I4(\\req_bank_r_lcl_reg[2]_1 [1]),\n .I5(Q[2]),\n .O(\\cmd_pipe_plus.mc_bank_reg[8] [1]));\n LUT6 #(\n .INIT(64'hEFFFEAFFEAFFEAFF)) \n \\cmd_pipe_plus.mc_bank[8]_i_1 \n (.I0(\\req_bank_r_lcl_reg[2] ),\n .I1(\\req_bank_r_lcl_reg[2]_0 [2]),\n .I2(Q[3]),\n .I3(\\pre_4_1_1T_arb.granted_pre_r_reg ),\n .I4(\\req_bank_r_lcl_reg[2]_1 [2]),\n .I5(Q[2]),\n .O(\\cmd_pipe_plus.mc_bank_reg[8] [2]));\n LUT6 #(\n .INIT(64'hFBFFEAFFEAFFEAFF)) \n \\cmd_pipe_plus.mc_we_n[2]_i_1 \n (.I0(\\cmd_pipe_plus.mc_we_n[2]_i_2_n_0 ),\n .I1(Q[3]),\n .I2(act_wait_r_lcl_reg),\n .I3(\\pre_4_1_1T_arb.granted_pre_r_reg ),\n .I4(act_wait_r_lcl_reg_0),\n .I5(Q[2]),\n .O(mc_we_n_ns));\n LUT6 #(\n .INIT(64'h1111100000001000)) \n \\cmd_pipe_plus.mc_we_n[2]_i_2 \n (.I0(Q[3]),\n .I1(Q[2]),\n .I2(Q[0]),\n .I3(act_wait_r_lcl_reg_1),\n .I4(Q[1]),\n .I5(row_cmd_wr),\n .O(\\cmd_pipe_plus.mc_we_n[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'h00F10000F0F10000)) \n \\grant_r[0]_i_1__2 \n (.I0(\\last_master_r[1]_i_1__1_n_0 ),\n .I1(ras_timer_zero_r_reg),\n .I2(ras_timer_zero_r_reg_0),\n .I3(D[0]),\n .I4(auto_pre_r_lcl_reg),\n .I5(auto_pre_r_lcl_reg_0),\n .O(\\grant_r[0]_i_1__2_n_0 ));\n LUT6 #(\n .INIT(64'h0020AAAA00000000)) \n \\grant_r[1]_i_1__2 \n (.I0(\\grant_r[1]_i_2__1_n_0 ),\n .I1(D[1]),\n .I2(\\last_master_r_reg[3]_1 ),\n .I3(\\last_master_r[1]_i_1__1_n_0 ),\n .I4(auto_pre_r_lcl_reg),\n .I5(auto_pre_r_lcl_reg_0),\n .O(\\grant_r[1]_i_1__2_n_0 ));\n LUT6 #(\n .INIT(64'hBBBBBBBBAAABBBAB)) \n \\grant_r[1]_i_2__1 \n (.I0(ras_timer_zero_r_reg_0),\n .I1(ras_timer_zero_r_reg),\n .I2(last_master_r[1]),\n .I3(\\pre_4_1_1T_arb.granted_pre_r_reg ),\n .I4(Q[1]),\n .I5(rstdiv0_sync_r1_reg_rep__22),\n .O(\\grant_r[1]_i_2__1_n_0 ));\n LUT6 #(\n .INIT(64'h00F00020F0F00020)) \n \\grant_r[2]_i_1__2 \n (.I0(\\last_master_r_reg[3]_1 ),\n .I1(ras_timer_zero_r_reg_1),\n .I2(auto_pre_r_lcl_reg_1),\n .I3(D[1]),\n .I4(ras_timer_zero_r_reg_2),\n .I5(auto_pre_r_lcl_reg_2),\n .O(\\grant_r[2]_i_1__2_n_0 ));\n LUT6 #(\n .INIT(64'h0020AAAA00000000)) \n \\grant_r[3]_i_1__1 \n (.I0(\\grant_r[3]_i_2__1_n_0 ),\n .I1(D[0]),\n .I2(\\last_master_r_reg[3]_1 ),\n .I3(\\last_master_r[1]_i_1__1_n_0 ),\n .I4(auto_pre_r_lcl_reg_1),\n .I5(auto_pre_r_lcl_reg_2),\n .O(\\grant_r[3]_i_1__1_n_0 ));\n LUT6 #(\n .INIT(64'hAAAAAAABABABAAAB)) \n \\grant_r[3]_i_2__1 \n (.I0(ras_timer_zero_r_reg_2),\n .I1(ras_timer_zero_r_reg_1),\n .I2(rstdiv0_sync_r1_reg_rep__21),\n .I3(\\last_master_r_reg[3]_0 ),\n .I4(\\pre_4_1_1T_arb.granted_pre_r_reg ),\n .I5(Q[3]),\n .O(\\grant_r[3]_i_2__1_n_0 ));\n FDRE \\grant_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\grant_r[0]_i_1__2_n_0 ),\n .Q(Q[0]),\n .R(1'b0));\n FDRE \\grant_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\grant_r[1]_i_1__2_n_0 ),\n .Q(Q[1]),\n .R(1'b0));\n FDRE \\grant_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\grant_r[2]_i_1__2_n_0 ),\n .Q(Q[2]),\n .R(1'b0));\n FDRE \\grant_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\grant_r[3]_i_1__1_n_0 ),\n .Q(Q[3]),\n .R(1'b0));\n LUT4 #(\n .INIT(16'h00E2)) \n \\last_master_r[0]_i_1__1 \n (.I0(last_master_r[0]),\n .I1(\\pre_4_1_1T_arb.granted_pre_r_reg ),\n .I2(Q[0]),\n .I3(rstdiv0_sync_r1_reg_rep__22),\n .O(D[0]));\n LUT4 #(\n .INIT(16'h00E2)) \n \\last_master_r[1]_i_1__1 \n (.I0(last_master_r[1]),\n .I1(\\pre_4_1_1T_arb.granted_pre_r_reg ),\n .I2(Q[1]),\n .I3(rstdiv0_sync_r1_reg_rep__22),\n .O(\\last_master_r[1]_i_1__1_n_0 ));\n LUT4 #(\n .INIT(16'h00E2)) \n \\last_master_r[2]_i_1__2 \n (.I0(last_master_r[2]),\n .I1(\\pre_4_1_1T_arb.granted_pre_r_reg ),\n .I2(Q[2]),\n .I3(rstdiv0_sync_r1_reg_rep__22),\n .O(D[1]));\n LUT4 #(\n .INIT(16'hFFB8)) \n \\last_master_r[3]_i_1__1 \n (.I0(Q[3]),\n .I1(\\pre_4_1_1T_arb.granted_pre_r_reg ),\n .I2(\\last_master_r_reg[3]_0 ),\n .I3(rstdiv0_sync_r1_reg_rep__22),\n .O(\\last_master_r[3]_i_1__1_n_0 ));\n FDRE \\last_master_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(D[0]),\n .Q(last_master_r[0]),\n .R(1'b0));\n FDRE \\last_master_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\last_master_r[1]_i_1__1_n_0 ),\n .Q(last_master_r[1]),\n .R(1'b0));\n FDRE \\last_master_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(D[1]),\n .Q(last_master_r[2]),\n .R(1'b0));\n FDRE \\last_master_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\last_master_r[3]_i_1__1_n_0 ),\n .Q(\\last_master_r_reg[3]_0 ),\n .R(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_round_robin_arb\" *) \nmodule ddr3_if_mig_7series_v4_0_round_robin_arb__parameterized2\n (mc_we_n_ns,\n Q,\n mc_cas_n_ns,\n mc_ras_n_ns,\n \\cmd_pipe_plus.mc_bank_reg[2] ,\n \\cmd_pipe_plus.mc_bank_reg[1] ,\n \\cmd_pipe_plus.mc_address_reg[14] ,\n \\grant_r_reg[2]_0 ,\n \\grant_r_reg[3]_0 ,\n \\grant_r_reg[3]_1 ,\n \\grant_r_reg[1]_0 ,\n \\last_master_r_reg[3]_0 ,\n act_this_rank,\n \\inhbt_act_faw.inhbt_act_faw_r_reg ,\n row_cmd_wr,\n insert_maint_r1_lcl_reg,\n rstdiv0_sync_r1_reg_rep__21,\n maint_zq_r,\n act_wait_r_lcl_reg,\n granted_row_r_reg,\n maint_srx_r,\n granted_row_r_reg_0,\n \\req_bank_r_lcl_reg[2] ,\n granted_row_r_reg_1,\n \\req_bank_r_lcl_reg[2]_0 ,\n \\req_bank_r_lcl_reg[2]_1 ,\n \\req_bank_r_lcl_reg[2]_2 ,\n \\req_row_r_lcl_reg[14] ,\n req_row_r,\n act_wait_r_lcl_reg_0,\n act_wait_r_lcl_reg_1,\n act_wait_r_lcl_reg_2,\n ras_timer_zero_r_reg,\n ras_timer_zero_r_reg_0,\n ras_timer_zero_r_reg_1,\n \\last_master_r_reg[3]_1 ,\n ras_timer_zero_r_reg_2,\n ras_timer_zero_r_reg_3,\n \\generate_maint_cmds.insert_maint_r_lcl_reg ,\n inhbt_act_faw_r,\n rstdiv0_sync_r1_reg_rep__22,\n act_this_rank_r,\n CLK);\n output [0:0]mc_we_n_ns;\n output [3:0]Q;\n output [0:0]mc_cas_n_ns;\n output [0:0]mc_ras_n_ns;\n output [2:0]\\cmd_pipe_plus.mc_bank_reg[2] ;\n output \\cmd_pipe_plus.mc_bank_reg[1] ;\n output [14:0]\\cmd_pipe_plus.mc_address_reg[14] ;\n output \\grant_r_reg[2]_0 ;\n output \\grant_r_reg[3]_0 ;\n output \\grant_r_reg[3]_1 ;\n output \\grant_r_reg[1]_0 ;\n output [0:0]\\last_master_r_reg[3]_0 ;\n output act_this_rank;\n output \\inhbt_act_faw.inhbt_act_faw_r_reg ;\n input [0:0]row_cmd_wr;\n input insert_maint_r1_lcl_reg;\n input rstdiv0_sync_r1_reg_rep__21;\n input maint_zq_r;\n input act_wait_r_lcl_reg;\n input granted_row_r_reg;\n input maint_srx_r;\n input granted_row_r_reg_0;\n input [2:0]\\req_bank_r_lcl_reg[2] ;\n input granted_row_r_reg_1;\n input [2:0]\\req_bank_r_lcl_reg[2]_0 ;\n input [2:0]\\req_bank_r_lcl_reg[2]_1 ;\n input [2:0]\\req_bank_r_lcl_reg[2]_2 ;\n input [27:0]\\req_row_r_lcl_reg[14] ;\n input [29:0]req_row_r;\n input act_wait_r_lcl_reg_0;\n input act_wait_r_lcl_reg_1;\n input act_wait_r_lcl_reg_2;\n input ras_timer_zero_r_reg;\n input ras_timer_zero_r_reg_0;\n input ras_timer_zero_r_reg_1;\n input \\last_master_r_reg[3]_1 ;\n input ras_timer_zero_r_reg_2;\n input ras_timer_zero_r_reg_3;\n input \\generate_maint_cmds.insert_maint_r_lcl_reg ;\n input inhbt_act_faw_r;\n input rstdiv0_sync_r1_reg_rep__22;\n input [3:0]act_this_rank_r;\n input CLK;\n\n wire CLK;\n wire [3:0]Q;\n wire act_this_rank;\n wire [3:0]act_this_rank_r;\n wire act_wait_r_lcl_reg;\n wire act_wait_r_lcl_reg_0;\n wire act_wait_r_lcl_reg_1;\n wire act_wait_r_lcl_reg_2;\n wire \\cmd_pipe_plus.mc_address[0]_i_2_n_0 ;\n wire \\cmd_pipe_plus.mc_address[10]_i_2_n_0 ;\n wire \\cmd_pipe_plus.mc_address[11]_i_2_n_0 ;\n wire \\cmd_pipe_plus.mc_address[12]_i_2_n_0 ;\n wire \\cmd_pipe_plus.mc_address[13]_i_2_n_0 ;\n wire \\cmd_pipe_plus.mc_address[14]_i_2_n_0 ;\n wire \\cmd_pipe_plus.mc_address[1]_i_2_n_0 ;\n wire \\cmd_pipe_plus.mc_address[2]_i_2_n_0 ;\n wire \\cmd_pipe_plus.mc_address[3]_i_2_n_0 ;\n wire \\cmd_pipe_plus.mc_address[4]_i_2_n_0 ;\n wire \\cmd_pipe_plus.mc_address[5]_i_2_n_0 ;\n wire \\cmd_pipe_plus.mc_address[6]_i_2_n_0 ;\n wire \\cmd_pipe_plus.mc_address[7]_i_2_n_0 ;\n wire \\cmd_pipe_plus.mc_address[8]_i_2_n_0 ;\n wire \\cmd_pipe_plus.mc_address[9]_i_2_n_0 ;\n wire [14:0]\\cmd_pipe_plus.mc_address_reg[14] ;\n wire \\cmd_pipe_plus.mc_bank[0]_i_2_n_0 ;\n wire \\cmd_pipe_plus.mc_bank[1]_i_2_n_0 ;\n wire \\cmd_pipe_plus.mc_bank[2]_i_2_n_0 ;\n wire \\cmd_pipe_plus.mc_bank_reg[1] ;\n wire [2:0]\\cmd_pipe_plus.mc_bank_reg[2] ;\n wire \\cmd_pipe_plus.mc_ras_n[0]_i_2_n_0 ;\n wire \\cmd_pipe_plus.mc_we_n[0]_i_2_n_0 ;\n wire \\cmd_pipe_plus.mc_we_n[0]_i_3_n_0 ;\n wire \\generate_maint_cmds.insert_maint_r_lcl_reg ;\n wire \\grant_r[0]_i_1__1_n_0 ;\n wire \\grant_r[1]_i_1__1_n_0 ;\n wire \\grant_r[1]_i_3__0_n_0 ;\n wire \\grant_r[2]_i_1__1_n_0 ;\n wire \\grant_r[2]_i_2__1_n_0 ;\n wire \\grant_r[2]_i_3_n_0 ;\n wire \\grant_r[3]_i_1__0_n_0 ;\n wire \\grant_r[3]_i_4__1_n_0 ;\n wire \\grant_r[3]_i_5__0_n_0 ;\n wire \\grant_r[3]_i_6__0_n_0 ;\n wire \\grant_r_reg[1]_0 ;\n wire \\grant_r_reg[2]_0 ;\n wire \\grant_r_reg[3]_0 ;\n wire \\grant_r_reg[3]_1 ;\n wire granted_row_r_reg;\n wire granted_row_r_reg_0;\n wire granted_row_r_reg_1;\n wire i___73_i_2_n_0;\n wire i___74_i_2_n_0;\n wire i___83_i_2_n_0;\n wire \\inhbt_act_faw.inhbt_act_faw_r_reg ;\n wire inhbt_act_faw_r;\n wire insert_maint_r1_lcl_reg;\n wire [2:0]last_master_r;\n wire \\last_master_r[0]_i_1__0_n_0 ;\n wire \\last_master_r[1]_i_1__0_n_0 ;\n wire \\last_master_r[2]_i_1__1_n_0 ;\n wire \\last_master_r[3]_i_1__0_n_0 ;\n wire [0:0]\\last_master_r_reg[3]_0 ;\n wire \\last_master_r_reg[3]_1 ;\n wire maint_srx_r;\n wire maint_zq_r;\n wire [0:0]mc_cas_n_ns;\n wire [0:0]mc_ras_n_ns;\n wire [0:0]mc_we_n_ns;\n wire ras_timer_zero_r_reg;\n wire ras_timer_zero_r_reg_0;\n wire ras_timer_zero_r_reg_1;\n wire ras_timer_zero_r_reg_2;\n wire ras_timer_zero_r_reg_3;\n wire [2:0]\\req_bank_r_lcl_reg[2] ;\n wire [2:0]\\req_bank_r_lcl_reg[2]_0 ;\n wire [2:0]\\req_bank_r_lcl_reg[2]_1 ;\n wire [2:0]\\req_bank_r_lcl_reg[2]_2 ;\n wire [29:0]req_row_r;\n wire [27:0]\\req_row_r_lcl_reg[14] ;\n wire [0:0]row_cmd_wr;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire rstdiv0_sync_r1_reg_rep__22;\n\n LUT5 #(\n .INIT(32'hF800F8F8)) \n \\cmd_pipe_plus.mc_address[0]_i_1 \n (.I0(Q[0]),\n .I1(\\req_row_r_lcl_reg[14] [0]),\n .I2(granted_row_r_reg),\n .I3(\\cmd_pipe_plus.mc_address[0]_i_2_n_0 ),\n .I4(granted_row_r_reg_1),\n .O(\\cmd_pipe_plus.mc_address_reg[14] [0]));\n LUT6 #(\n .INIT(64'hFFFFF0880000F088)) \n \\cmd_pipe_plus.mc_address[0]_i_2 \n (.I0(Q[1]),\n .I1(\\req_row_r_lcl_reg[14] [14]),\n .I2(req_row_r[1]),\n .I3(Q[2]),\n .I4(Q[3]),\n .I5(req_row_r[16]),\n .O(\\cmd_pipe_plus.mc_address[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFF800000FF80FF80)) \n \\cmd_pipe_plus.mc_address[10]_i_1 \n (.I0(req_row_r[0]),\n .I1(Q[0]),\n .I2(act_wait_r_lcl_reg),\n .I3(granted_row_r_reg),\n .I4(\\cmd_pipe_plus.mc_address[10]_i_2_n_0 ),\n .I5(act_wait_r_lcl_reg_0),\n .O(\\cmd_pipe_plus.mc_address_reg[14] [10]));\n LUT5 #(\n .INIT(32'h0800FFFF)) \n \\cmd_pipe_plus.mc_address[10]_i_2 \n (.I0(act_wait_r_lcl_reg_1),\n .I1(Q[2]),\n .I2(Q[3]),\n .I3(req_row_r[11]),\n .I4(granted_row_r_reg_1),\n .O(\\cmd_pipe_plus.mc_address[10]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hF800F8F8)) \n \\cmd_pipe_plus.mc_address[11]_i_1 \n (.I0(Q[0]),\n .I1(\\req_row_r_lcl_reg[14] [10]),\n .I2(granted_row_r_reg),\n .I3(\\cmd_pipe_plus.mc_address[11]_i_2_n_0 ),\n .I4(granted_row_r_reg_1),\n .O(\\cmd_pipe_plus.mc_address_reg[14] [11]));\n LUT6 #(\n .INIT(64'hFFFFF0880000F088)) \n \\cmd_pipe_plus.mc_address[11]_i_2 \n (.I0(Q[1]),\n .I1(\\req_row_r_lcl_reg[14] [24]),\n .I2(req_row_r[12]),\n .I3(Q[2]),\n .I4(Q[3]),\n .I5(req_row_r[26]),\n .O(\\cmd_pipe_plus.mc_address[11]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hF800F8F8)) \n \\cmd_pipe_plus.mc_address[12]_i_1 \n (.I0(Q[0]),\n .I1(\\req_row_r_lcl_reg[14] [11]),\n .I2(granted_row_r_reg),\n .I3(\\cmd_pipe_plus.mc_address[12]_i_2_n_0 ),\n .I4(granted_row_r_reg_1),\n .O(\\cmd_pipe_plus.mc_address_reg[14] [12]));\n LUT6 #(\n .INIT(64'hFFFFF0880000F088)) \n \\cmd_pipe_plus.mc_address[12]_i_2 \n (.I0(Q[1]),\n .I1(\\req_row_r_lcl_reg[14] [25]),\n .I2(req_row_r[13]),\n .I3(Q[2]),\n .I4(Q[3]),\n .I5(req_row_r[27]),\n .O(\\cmd_pipe_plus.mc_address[12]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hF800F8F8F800F800)) \n \\cmd_pipe_plus.mc_address[13]_i_1 \n (.I0(Q[0]),\n .I1(\\req_row_r_lcl_reg[14] [12]),\n .I2(granted_row_r_reg),\n .I3(\\cmd_pipe_plus.mc_address[13]_i_2_n_0 ),\n .I4(\\cmd_pipe_plus.mc_bank_reg[1] ),\n .I5(\\req_row_r_lcl_reg[14] [26]),\n .O(\\cmd_pipe_plus.mc_address_reg[14] [13]));\n LUT5 #(\n .INIT(32'hF808FFFF)) \n \\cmd_pipe_plus.mc_address[13]_i_2 \n (.I0(req_row_r[14]),\n .I1(Q[2]),\n .I2(Q[3]),\n .I3(req_row_r[28]),\n .I4(granted_row_r_reg_1),\n .O(\\cmd_pipe_plus.mc_address[13]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hF800F8F8F800F800)) \n \\cmd_pipe_plus.mc_address[14]_i_1 \n (.I0(Q[0]),\n .I1(\\req_row_r_lcl_reg[14] [13]),\n .I2(granted_row_r_reg),\n .I3(\\cmd_pipe_plus.mc_address[14]_i_2_n_0 ),\n .I4(\\cmd_pipe_plus.mc_bank_reg[1] ),\n .I5(\\req_row_r_lcl_reg[14] [27]),\n .O(\\cmd_pipe_plus.mc_address_reg[14] [14]));\n LUT5 #(\n .INIT(32'hF808FFFF)) \n \\cmd_pipe_plus.mc_address[14]_i_2 \n (.I0(req_row_r[15]),\n .I1(Q[2]),\n .I2(Q[3]),\n .I3(req_row_r[29]),\n .I4(granted_row_r_reg_1),\n .O(\\cmd_pipe_plus.mc_address[14]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1048\" *) \n LUT3 #(\n .INIT(8'hFB)) \n \\cmd_pipe_plus.mc_address[14]_i_3 \n (.I0(Q[3]),\n .I1(Q[1]),\n .I2(Q[2]),\n .O(\\cmd_pipe_plus.mc_bank_reg[1] ));\n LUT5 #(\n .INIT(32'hF800F8F8)) \n \\cmd_pipe_plus.mc_address[1]_i_1 \n (.I0(Q[0]),\n .I1(\\req_row_r_lcl_reg[14] [1]),\n .I2(granted_row_r_reg),\n .I3(\\cmd_pipe_plus.mc_address[1]_i_2_n_0 ),\n .I4(granted_row_r_reg_1),\n .O(\\cmd_pipe_plus.mc_address_reg[14] [1]));\n LUT6 #(\n .INIT(64'hFFFFF0880000F088)) \n \\cmd_pipe_plus.mc_address[1]_i_2 \n (.I0(Q[1]),\n .I1(\\req_row_r_lcl_reg[14] [15]),\n .I2(req_row_r[2]),\n .I3(Q[2]),\n .I4(Q[3]),\n .I5(req_row_r[17]),\n .O(\\cmd_pipe_plus.mc_address[1]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hF800F8F8F800F800)) \n \\cmd_pipe_plus.mc_address[2]_i_1 \n (.I0(Q[0]),\n .I1(\\req_row_r_lcl_reg[14] [2]),\n .I2(granted_row_r_reg),\n .I3(\\cmd_pipe_plus.mc_address[2]_i_2_n_0 ),\n .I4(\\cmd_pipe_plus.mc_bank_reg[1] ),\n .I5(\\req_row_r_lcl_reg[14] [16]),\n .O(\\cmd_pipe_plus.mc_address_reg[14] [2]));\n LUT5 #(\n .INIT(32'hF808FFFF)) \n \\cmd_pipe_plus.mc_address[2]_i_2 \n (.I0(req_row_r[3]),\n .I1(Q[2]),\n .I2(Q[3]),\n .I3(req_row_r[18]),\n .I4(granted_row_r_reg_1),\n .O(\\cmd_pipe_plus.mc_address[2]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hF800F8F8)) \n \\cmd_pipe_plus.mc_address[3]_i_1 \n (.I0(Q[0]),\n .I1(\\req_row_r_lcl_reg[14] [3]),\n .I2(granted_row_r_reg),\n .I3(\\cmd_pipe_plus.mc_address[3]_i_2_n_0 ),\n .I4(granted_row_r_reg_1),\n .O(\\cmd_pipe_plus.mc_address_reg[14] [3]));\n LUT6 #(\n .INIT(64'hFFFFF0880000F088)) \n \\cmd_pipe_plus.mc_address[3]_i_2 \n (.I0(Q[1]),\n .I1(\\req_row_r_lcl_reg[14] [17]),\n .I2(req_row_r[4]),\n .I3(Q[2]),\n .I4(Q[3]),\n .I5(req_row_r[19]),\n .O(\\cmd_pipe_plus.mc_address[3]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hF800F8F8)) \n \\cmd_pipe_plus.mc_address[4]_i_1 \n (.I0(Q[0]),\n .I1(\\req_row_r_lcl_reg[14] [4]),\n .I2(granted_row_r_reg),\n .I3(\\cmd_pipe_plus.mc_address[4]_i_2_n_0 ),\n .I4(granted_row_r_reg_1),\n .O(\\cmd_pipe_plus.mc_address_reg[14] [4]));\n LUT6 #(\n .INIT(64'hFFFFF0880000F088)) \n \\cmd_pipe_plus.mc_address[4]_i_2 \n (.I0(Q[1]),\n .I1(\\req_row_r_lcl_reg[14] [18]),\n .I2(req_row_r[5]),\n .I3(Q[2]),\n .I4(Q[3]),\n .I5(req_row_r[20]),\n .O(\\cmd_pipe_plus.mc_address[4]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hF800F8F8)) \n \\cmd_pipe_plus.mc_address[5]_i_1 \n (.I0(Q[0]),\n .I1(\\req_row_r_lcl_reg[14] [5]),\n .I2(granted_row_r_reg),\n .I3(\\cmd_pipe_plus.mc_address[5]_i_2_n_0 ),\n .I4(granted_row_r_reg_1),\n .O(\\cmd_pipe_plus.mc_address_reg[14] [5]));\n LUT6 #(\n .INIT(64'hFFFFF0880000F088)) \n \\cmd_pipe_plus.mc_address[5]_i_2 \n (.I0(Q[1]),\n .I1(\\req_row_r_lcl_reg[14] [19]),\n .I2(req_row_r[6]),\n .I3(Q[2]),\n .I4(Q[3]),\n .I5(req_row_r[21]),\n .O(\\cmd_pipe_plus.mc_address[5]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hF800F8F8)) \n \\cmd_pipe_plus.mc_address[6]_i_1 \n (.I0(Q[0]),\n .I1(\\req_row_r_lcl_reg[14] [6]),\n .I2(granted_row_r_reg),\n .I3(\\cmd_pipe_plus.mc_address[6]_i_2_n_0 ),\n .I4(granted_row_r_reg_1),\n .O(\\cmd_pipe_plus.mc_address_reg[14] [6]));\n LUT6 #(\n .INIT(64'hFFFFF0880000F088)) \n \\cmd_pipe_plus.mc_address[6]_i_2 \n (.I0(Q[1]),\n .I1(\\req_row_r_lcl_reg[14] [20]),\n .I2(req_row_r[7]),\n .I3(Q[2]),\n .I4(Q[3]),\n .I5(req_row_r[22]),\n .O(\\cmd_pipe_plus.mc_address[6]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hF800F8F8)) \n \\cmd_pipe_plus.mc_address[7]_i_1 \n (.I0(Q[0]),\n .I1(\\req_row_r_lcl_reg[14] [7]),\n .I2(granted_row_r_reg),\n .I3(\\cmd_pipe_plus.mc_address[7]_i_2_n_0 ),\n .I4(granted_row_r_reg_1),\n .O(\\cmd_pipe_plus.mc_address_reg[14] [7]));\n LUT6 #(\n .INIT(64'hFFFFF0880000F088)) \n \\cmd_pipe_plus.mc_address[7]_i_2 \n (.I0(Q[1]),\n .I1(\\req_row_r_lcl_reg[14] [21]),\n .I2(req_row_r[8]),\n .I3(Q[2]),\n .I4(Q[3]),\n .I5(req_row_r[23]),\n .O(\\cmd_pipe_plus.mc_address[7]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hF800F8F8)) \n \\cmd_pipe_plus.mc_address[8]_i_1 \n (.I0(Q[0]),\n .I1(\\req_row_r_lcl_reg[14] [8]),\n .I2(granted_row_r_reg),\n .I3(\\cmd_pipe_plus.mc_address[8]_i_2_n_0 ),\n .I4(granted_row_r_reg_1),\n .O(\\cmd_pipe_plus.mc_address_reg[14] [8]));\n LUT6 #(\n .INIT(64'hFFFFF0880000F088)) \n \\cmd_pipe_plus.mc_address[8]_i_2 \n (.I0(Q[1]),\n .I1(\\req_row_r_lcl_reg[14] [22]),\n .I2(req_row_r[9]),\n .I3(Q[2]),\n .I4(Q[3]),\n .I5(req_row_r[24]),\n .O(\\cmd_pipe_plus.mc_address[8]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hF800F8F8)) \n \\cmd_pipe_plus.mc_address[9]_i_1 \n (.I0(Q[0]),\n .I1(\\req_row_r_lcl_reg[14] [9]),\n .I2(granted_row_r_reg),\n .I3(\\cmd_pipe_plus.mc_address[9]_i_2_n_0 ),\n .I4(granted_row_r_reg_1),\n .O(\\cmd_pipe_plus.mc_address_reg[14] [9]));\n LUT6 #(\n .INIT(64'hFFFFF0880000F088)) \n \\cmd_pipe_plus.mc_address[9]_i_2 \n (.I0(Q[1]),\n .I1(\\req_row_r_lcl_reg[14] [23]),\n .I2(req_row_r[10]),\n .I3(Q[2]),\n .I4(Q[3]),\n .I5(req_row_r[25]),\n .O(\\cmd_pipe_plus.mc_address[9]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hF800F8F8)) \n \\cmd_pipe_plus.mc_bank[0]_i_1 \n (.I0(Q[0]),\n .I1(\\req_bank_r_lcl_reg[2] [0]),\n .I2(granted_row_r_reg),\n .I3(\\cmd_pipe_plus.mc_bank[0]_i_2_n_0 ),\n .I4(granted_row_r_reg_1),\n .O(\\cmd_pipe_plus.mc_bank_reg[2] [0]));\n LUT6 #(\n .INIT(64'hFFFFF0880000F088)) \n \\cmd_pipe_plus.mc_bank[0]_i_2 \n (.I0(Q[1]),\n .I1(\\req_bank_r_lcl_reg[2]_0 [0]),\n .I2(\\req_bank_r_lcl_reg[2]_1 [0]),\n .I3(Q[2]),\n .I4(Q[3]),\n .I5(\\req_bank_r_lcl_reg[2]_2 [0]),\n .O(\\cmd_pipe_plus.mc_bank[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hF800F8F8F800F800)) \n \\cmd_pipe_plus.mc_bank[1]_i_1 \n (.I0(Q[0]),\n .I1(\\req_bank_r_lcl_reg[2] [1]),\n .I2(granted_row_r_reg),\n .I3(\\cmd_pipe_plus.mc_bank[1]_i_2_n_0 ),\n .I4(\\cmd_pipe_plus.mc_bank_reg[1] ),\n .I5(\\req_bank_r_lcl_reg[2]_0 [1]),\n .O(\\cmd_pipe_plus.mc_bank_reg[2] [1]));\n LUT5 #(\n .INIT(32'hF808FFFF)) \n \\cmd_pipe_plus.mc_bank[1]_i_2 \n (.I0(\\req_bank_r_lcl_reg[2]_1 [1]),\n .I1(Q[2]),\n .I2(Q[3]),\n .I3(\\req_bank_r_lcl_reg[2]_2 [1]),\n .I4(granted_row_r_reg_1),\n .O(\\cmd_pipe_plus.mc_bank[1]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hEA00EAEA)) \n \\cmd_pipe_plus.mc_bank[2]_i_1 \n (.I0(granted_row_r_reg),\n .I1(Q[0]),\n .I2(\\req_bank_r_lcl_reg[2] [2]),\n .I3(\\cmd_pipe_plus.mc_bank[2]_i_2_n_0 ),\n .I4(granted_row_r_reg_1),\n .O(\\cmd_pipe_plus.mc_bank_reg[2] [2]));\n LUT6 #(\n .INIT(64'hFFFFF0880000F088)) \n \\cmd_pipe_plus.mc_bank[2]_i_2 \n (.I0(Q[1]),\n .I1(\\req_bank_r_lcl_reg[2]_0 [2]),\n .I2(\\req_bank_r_lcl_reg[2]_1 [2]),\n .I3(Q[2]),\n .I4(Q[3]),\n .I5(\\req_bank_r_lcl_reg[2]_2 [2]),\n .O(\\cmd_pipe_plus.mc_bank[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hEFEFEEEEEFEEEEEE)) \n \\cmd_pipe_plus.mc_cas_n[0]_i_1 \n (.I0(granted_row_r_reg),\n .I1(Q[0]),\n .I2(rstdiv0_sync_r1_reg_rep__21),\n .I3(maint_zq_r),\n .I4(insert_maint_r1_lcl_reg),\n .I5(maint_srx_r),\n .O(mc_cas_n_ns));\n LUT6 #(\n .INIT(64'h000200020002FFFF)) \n \\cmd_pipe_plus.mc_ras_n[0]_i_1 \n (.I0(\\cmd_pipe_plus.mc_ras_n[0]_i_2_n_0 ),\n .I1(Q[3]),\n .I2(Q[2]),\n .I3(Q[1]),\n .I4(insert_maint_r1_lcl_reg),\n .I5(granted_row_r_reg_0),\n .O(mc_ras_n_ns));\n LUT5 #(\n .INIT(32'h11001000)) \n \\cmd_pipe_plus.mc_ras_n[0]_i_2 \n (.I0(Q[0]),\n .I1(rstdiv0_sync_r1_reg_rep__21),\n .I2(maint_zq_r),\n .I3(insert_maint_r1_lcl_reg),\n .I4(maint_srx_r),\n .O(\\cmd_pipe_plus.mc_ras_n[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hCCCCCCCCCCFCCCDD)) \n \\cmd_pipe_plus.mc_we_n[0]_i_1 \n (.I0(\\cmd_pipe_plus.mc_we_n[0]_i_2_n_0 ),\n .I1(\\cmd_pipe_plus.mc_we_n[0]_i_3_n_0 ),\n .I2(row_cmd_wr),\n .I3(Q[2]),\n .I4(Q[1]),\n .I5(Q[3]),\n .O(mc_we_n_ns));\n LUT5 #(\n .INIT(32'h00FDFFFD)) \n \\cmd_pipe_plus.mc_we_n[0]_i_2 \n (.I0(insert_maint_r1_lcl_reg),\n .I1(rstdiv0_sync_r1_reg_rep__21),\n .I2(maint_zq_r),\n .I3(Q[0]),\n .I4(act_wait_r_lcl_reg),\n .O(\\cmd_pipe_plus.mc_we_n[0]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hF088F088F088FFFF)) \n \\cmd_pipe_plus.mc_we_n[0]_i_3 \n (.I0(Q[2]),\n .I1(act_wait_r_lcl_reg_1),\n .I2(act_wait_r_lcl_reg_2),\n .I3(Q[3]),\n .I4(insert_maint_r1_lcl_reg),\n .I5(granted_row_r_reg_0),\n .O(\\cmd_pipe_plus.mc_we_n[0]_i_3_n_0 ));\n LUT5 #(\n .INIT(32'h0000F100)) \n \\grant_r[0]_i_1__1 \n (.I0(\\grant_r[3]_i_5__0_n_0 ),\n .I1(ras_timer_zero_r_reg),\n .I2(\\grant_r[3]_i_4__1_n_0 ),\n .I3(ras_timer_zero_r_reg_0),\n .I4(\\grant_r[2]_i_3_n_0 ),\n .O(\\grant_r[0]_i_1__1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000003000707)) \n \\grant_r[1]_i_1__1 \n (.I0(ras_timer_zero_r_reg),\n .I1(\\last_master_r[1]_i_1__0_n_0 ),\n .I2(\\grant_r[1]_i_3__0_n_0 ),\n .I3(\\grant_r[2]_i_2__1_n_0 ),\n .I4(ras_timer_zero_r_reg_0),\n .I5(\\grant_r[2]_i_3_n_0 ),\n .O(\\grant_r[1]_i_1__1_n_0 ));\n LUT5 #(\n .INIT(32'hFFFFFEEE)) \n \\grant_r[1]_i_3__0 \n (.I0(ras_timer_zero_r_reg_2),\n .I1(Q[1]),\n .I2(Q[3]),\n .I3(act_wait_r_lcl_reg_2),\n .I4(\\grant_r[3]_i_6__0_n_0 ),\n .O(\\grant_r[1]_i_3__0_n_0 ));\n LUT5 #(\n .INIT(32'h40444040)) \n \\grant_r[2]_i_1__1 \n (.I0(\\grant_r[3]_i_5__0_n_0 ),\n .I1(ras_timer_zero_r_reg_1),\n .I2(\\grant_r[2]_i_2__1_n_0 ),\n .I3(\\grant_r[2]_i_3_n_0 ),\n .I4(\\grant_r_reg[2]_0 ),\n .O(\\grant_r[2]_i_1__1_n_0 ));\n LUT6 #(\n .INIT(64'h0005000000050303)) \n \\grant_r[2]_i_2__1 \n (.I0(Q[3]),\n .I1(\\last_master_r_reg[3]_0 ),\n .I2(rstdiv0_sync_r1_reg_rep__22),\n .I3(Q[2]),\n .I4(granted_row_r_reg_0),\n .I5(last_master_r[2]),\n .O(\\grant_r[2]_i_2__1_n_0 ));\n LUT5 #(\n .INIT(32'h00004540)) \n \\grant_r[2]_i_3 \n (.I0(rstdiv0_sync_r1_reg_rep__21),\n .I1(Q[2]),\n .I2(granted_row_r_reg_0),\n .I3(last_master_r[2]),\n .I4(\\grant_r_reg[3]_0 ),\n .O(\\grant_r[2]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'h000000000C000E0E)) \n \\grant_r[3]_i_1__0 \n (.I0(\\grant_r_reg[2]_0 ),\n .I1(\\last_master_r_reg[3]_1 ),\n .I2(\\grant_r_reg[3]_0 ),\n .I3(\\grant_r[3]_i_4__1_n_0 ),\n .I4(ras_timer_zero_r_reg_1),\n .I5(\\grant_r[3]_i_5__0_n_0 ),\n .O(\\grant_r[3]_i_1__0_n_0 ));\n LUT2 #(\n .INIT(4'h2)) \n \\grant_r[3]_i_2__0 \n (.I0(\\grant_r[1]_i_3__0_n_0 ),\n .I1(ras_timer_zero_r_reg_0),\n .O(\\grant_r_reg[2]_0 ));\n LUT5 #(\n .INIT(32'hFFFFFEEE)) \n \\grant_r[3]_i_3__0 \n (.I0(\\grant_r[3]_i_6__0_n_0 ),\n .I1(Q[3]),\n .I2(Q[1]),\n .I3(row_cmd_wr),\n .I4(ras_timer_zero_r_reg_3),\n .O(\\grant_r_reg[3]_0 ));\n LUT6 #(\n .INIT(64'hF0F5F0F0F0F5F3F3)) \n \\grant_r[3]_i_4__1 \n (.I0(Q[1]),\n .I1(last_master_r[1]),\n .I2(rstdiv0_sync_r1_reg_rep__22),\n .I3(Q[0]),\n .I4(granted_row_r_reg_0),\n .I5(last_master_r[0]),\n .O(\\grant_r[3]_i_4__1_n_0 ));\n LUT5 #(\n .INIT(32'h00004540)) \n \\grant_r[3]_i_5__0 \n (.I0(rstdiv0_sync_r1_reg_rep__21),\n .I1(Q[0]),\n .I2(granted_row_r_reg_0),\n .I3(last_master_r[0]),\n .I4(\\grant_r[1]_i_3__0_n_0 ),\n .O(\\grant_r[3]_i_5__0_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFF8FFF8FFF8)) \n \\grant_r[3]_i_6__0 \n (.I0(Q[2]),\n .I1(act_wait_r_lcl_reg_1),\n .I2(\\generate_maint_cmds.insert_maint_r_lcl_reg ),\n .I3(inhbt_act_faw_r),\n .I4(act_wait_r_lcl_reg),\n .I5(Q[0]),\n .O(\\grant_r[3]_i_6__0_n_0 ));\n FDRE \\grant_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\grant_r[0]_i_1__1_n_0 ),\n .Q(Q[0]),\n .R(1'b0));\n FDRE \\grant_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\grant_r[1]_i_1__1_n_0 ),\n .Q(Q[1]),\n .R(1'b0));\n FDRE \\grant_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\grant_r[2]_i_1__1_n_0 ),\n .Q(Q[2]),\n .R(1'b0));\n FDRE \\grant_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\grant_r[3]_i_1__0_n_0 ),\n .Q(Q[3]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFF888)) \n i___73_i_1\n (.I0(act_wait_r_lcl_reg_2),\n .I1(Q[3]),\n .I2(row_cmd_wr),\n .I3(Q[1]),\n .I4(i___73_i_2_n_0),\n .I5(Q[2]),\n .O(\\grant_r_reg[3]_1 ));\n LUT4 #(\n .INIT(16'hFFF8)) \n i___73_i_2\n (.I0(Q[0]),\n .I1(act_wait_r_lcl_reg),\n .I2(inhbt_act_faw_r),\n .I3(\\generate_maint_cmds.insert_maint_r_lcl_reg ),\n .O(i___73_i_2_n_0));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFEEE)) \n i___74_i_1\n (.I0(i___74_i_2_n_0),\n .I1(Q[0]),\n .I2(Q[2]),\n .I3(act_wait_r_lcl_reg_1),\n .I4(\\generate_maint_cmds.insert_maint_r_lcl_reg ),\n .I5(inhbt_act_faw_r),\n .O(\\grant_r_reg[1]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1048\" *) \n LUT4 #(\n .INIT(16'hF888)) \n i___74_i_2\n (.I0(Q[1]),\n .I1(row_cmd_wr),\n .I2(Q[3]),\n .I3(act_wait_r_lcl_reg_2),\n .O(i___74_i_2_n_0));\n LUT5 #(\n .INIT(32'h00000777)) \n i___83_i_1\n (.I0(Q[2]),\n .I1(act_this_rank_r[2]),\n .I2(Q[1]),\n .I3(act_this_rank_r[1]),\n .I4(i___83_i_2_n_0),\n .O(\\inhbt_act_faw.inhbt_act_faw_r_reg ));\n LUT4 #(\n .INIT(16'hF888)) \n i___83_i_2\n (.I0(act_this_rank_r[0]),\n .I1(Q[0]),\n .I2(act_this_rank_r[3]),\n .I3(Q[3]),\n .O(i___83_i_2_n_0));\n LUT1 #(\n .INIT(2'h1)) \n \\inhbt_act_faw.SRLC32E0_i_1 \n (.I0(\\inhbt_act_faw.inhbt_act_faw_r_reg ),\n .O(act_this_rank));\n LUT4 #(\n .INIT(16'h00E2)) \n \\last_master_r[0]_i_1__0 \n (.I0(last_master_r[0]),\n .I1(granted_row_r_reg_0),\n .I2(Q[0]),\n .I3(rstdiv0_sync_r1_reg_rep__22),\n .O(\\last_master_r[0]_i_1__0_n_0 ));\n LUT4 #(\n .INIT(16'h00E2)) \n \\last_master_r[1]_i_1__0 \n (.I0(last_master_r[1]),\n .I1(granted_row_r_reg_0),\n .I2(Q[1]),\n .I3(rstdiv0_sync_r1_reg_rep__22),\n .O(\\last_master_r[1]_i_1__0_n_0 ));\n LUT4 #(\n .INIT(16'h00E2)) \n \\last_master_r[2]_i_1__1 \n (.I0(last_master_r[2]),\n .I1(granted_row_r_reg_0),\n .I2(Q[2]),\n .I3(rstdiv0_sync_r1_reg_rep__22),\n .O(\\last_master_r[2]_i_1__1_n_0 ));\n LUT4 #(\n .INIT(16'hFFB8)) \n \\last_master_r[3]_i_1__0 \n (.I0(Q[3]),\n .I1(granted_row_r_reg_0),\n .I2(\\last_master_r_reg[3]_0 ),\n .I3(rstdiv0_sync_r1_reg_rep__22),\n .O(\\last_master_r[3]_i_1__0_n_0 ));\n FDRE \\last_master_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\last_master_r[0]_i_1__0_n_0 ),\n .Q(last_master_r[0]),\n .R(1'b0));\n FDRE \\last_master_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\last_master_r[1]_i_1__0_n_0 ),\n .Q(last_master_r[1]),\n .R(1'b0));\n FDRE \\last_master_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\last_master_r[2]_i_1__1_n_0 ),\n .Q(last_master_r[2]),\n .R(1'b0));\n FDRE \\last_master_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\last_master_r[3]_i_1__0_n_0 ),\n .Q(\\last_master_r_reg[3]_0 ),\n .R(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"mig_7series_v4_0_round_robin_arb\" *) \nmodule ddr3_if_mig_7series_v4_0_round_robin_arb__parameterized4\n (\\cmd_pipe_plus.mc_data_offset_1_reg[0] ,\n \\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ,\n \\rtw_timer.rtw_cnt_r_reg[1] ,\n Q,\n \\periodic_rd_generation.periodic_rd_timer_r_reg[2] ,\n read_this_rank,\n \\grant_r_reg[3]_0 ,\n E,\n col_rd_wr,\n DIC,\n \\grant_r_reg[3]_1 ,\n \\grant_r_reg[1]_0 ,\n \\grant_r_reg[1]_1 ,\n \\grant_r_reg[2]_0 ,\n col_data_buf_addr,\n \\wtr_timer.wtr_cnt_r_reg[0] ,\n \\wtr_timer.wtr_cnt_r_reg[1] ,\n \\wtr_timer.wtr_cnt_r_reg[1]_0 ,\n \\cmd_pipe_plus.mc_address_reg[25] ,\n \\cmd_pipe_plus.mc_bank_reg[5] ,\n demand_priority_r_reg,\n \\cmd_pipe_plus.mc_we_n_reg[1] ,\n granted_col_r_reg,\n rd_wr_r_lcl_reg,\n read_this_rank_r,\n rd_this_rank_r,\n rd_wr_r_lcl_reg_0,\n rd_wr_r_lcl_reg_1,\n rd_wr_r_lcl_reg_2,\n rd_wr_r_lcl_reg_3,\n rd_wr_r_lcl_reg_4,\n rstdiv0_sync_r1_reg_rep__21,\n rd_wr_r_lcl_reg_5,\n \\rtw_timer.rtw_cnt_r_reg[1]_0 ,\n rd_wr_r_lcl_reg_6,\n rd_wr_r_lcl_reg_7,\n req_periodic_rd_r,\n col_periodic_rd_r,\n col_rd_wr_r,\n rnk_config_valid_r_lcl_reg,\n ofs_rdy_r,\n \\genblk3[1].rnk_config_strobe_r_reg ,\n \\genblk3[2].rnk_config_strobe_r_reg ,\n rnk_config_strobe,\n ofs_rdy_r_3,\n ofs_rdy_r_4,\n ofs_rdy_r_5,\n rstdiv0_sync_r1_reg_rep__22,\n req_data_buf_addr_r,\n col_data_buf_addr_r,\n \\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ,\n wr_this_rank_r,\n \\req_col_r_reg[9] ,\n \\req_col_r_reg[9]_0 ,\n \\req_col_r_reg[9]_1 ,\n \\req_col_r_reg[9]_2 ,\n auto_pre_r_lcl_reg,\n auto_pre_r_lcl_reg_0,\n auto_pre_r_lcl_reg_1,\n auto_pre_r_lcl_reg_2,\n \\req_bank_r_lcl_reg[2] ,\n \\req_bank_r_lcl_reg[2]_0 ,\n \\req_bank_r_lcl_reg[2]_1 ,\n \\req_bank_r_lcl_reg[2]_2 ,\n req_bank_rdy_r,\n CLK);\n output \\cmd_pipe_plus.mc_data_offset_1_reg[0] ;\n output \\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ;\n output \\rtw_timer.rtw_cnt_r_reg[1] ;\n output [3:0]Q;\n output \\periodic_rd_generation.periodic_rd_timer_r_reg[2] ;\n output read_this_rank;\n output \\grant_r_reg[3]_0 ;\n output [0:0]E;\n output col_rd_wr;\n output [0:0]DIC;\n output \\grant_r_reg[3]_1 ;\n output \\grant_r_reg[1]_0 ;\n output \\grant_r_reg[1]_1 ;\n output \\grant_r_reg[2]_0 ;\n output [4:0]col_data_buf_addr;\n output \\wtr_timer.wtr_cnt_r_reg[0] ;\n output \\wtr_timer.wtr_cnt_r_reg[1] ;\n output \\wtr_timer.wtr_cnt_r_reg[1]_0 ;\n output [7:0]\\cmd_pipe_plus.mc_address_reg[25] ;\n output [2:0]\\cmd_pipe_plus.mc_bank_reg[5] ;\n output demand_priority_r_reg;\n output \\cmd_pipe_plus.mc_we_n_reg[1] ;\n input granted_col_r_reg;\n input rd_wr_r_lcl_reg;\n input read_this_rank_r;\n input [3:0]rd_this_rank_r;\n input rd_wr_r_lcl_reg_0;\n input rd_wr_r_lcl_reg_1;\n input rd_wr_r_lcl_reg_2;\n input rd_wr_r_lcl_reg_3;\n input rd_wr_r_lcl_reg_4;\n input rstdiv0_sync_r1_reg_rep__21;\n input rd_wr_r_lcl_reg_5;\n input [0:0]\\rtw_timer.rtw_cnt_r_reg[1]_0 ;\n input rd_wr_r_lcl_reg_6;\n input rd_wr_r_lcl_reg_7;\n input [3:0]req_periodic_rd_r;\n input col_periodic_rd_r;\n input col_rd_wr_r;\n input rnk_config_valid_r_lcl_reg;\n input ofs_rdy_r;\n input \\genblk3[1].rnk_config_strobe_r_reg ;\n input \\genblk3[2].rnk_config_strobe_r_reg ;\n input rnk_config_strobe;\n input ofs_rdy_r_3;\n input ofs_rdy_r_4;\n input ofs_rdy_r_5;\n input rstdiv0_sync_r1_reg_rep__22;\n input [19:0]req_data_buf_addr_r;\n input [0:0]col_data_buf_addr_r;\n input [3:0]\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ;\n input [3:0]wr_this_rank_r;\n input [6:0]\\req_col_r_reg[9] ;\n input [6:0]\\req_col_r_reg[9]_0 ;\n input [6:0]\\req_col_r_reg[9]_1 ;\n input [6:0]\\req_col_r_reg[9]_2 ;\n input auto_pre_r_lcl_reg;\n input auto_pre_r_lcl_reg_0;\n input auto_pre_r_lcl_reg_1;\n input auto_pre_r_lcl_reg_2;\n input [2:0]\\req_bank_r_lcl_reg[2] ;\n input [2:0]\\req_bank_r_lcl_reg[2]_0 ;\n input [2:0]\\req_bank_r_lcl_reg[2]_1 ;\n input [2:0]\\req_bank_r_lcl_reg[2]_2 ;\n input req_bank_rdy_r;\n input CLK;\n\n wire CLK;\n wire [0:0]DIC;\n wire [0:0]E;\n wire [3:0]Q;\n wire auto_pre_r_lcl_reg;\n wire auto_pre_r_lcl_reg_0;\n wire auto_pre_r_lcl_reg_1;\n wire auto_pre_r_lcl_reg_2;\n wire \\cmd_pipe_plus.mc_address[18]_i_2_n_0 ;\n wire \\cmd_pipe_plus.mc_address[19]_i_2_n_0 ;\n wire \\cmd_pipe_plus.mc_address[20]_i_2_n_0 ;\n wire \\cmd_pipe_plus.mc_address[21]_i_2_n_0 ;\n wire \\cmd_pipe_plus.mc_address[22]_i_2_n_0 ;\n wire \\cmd_pipe_plus.mc_address[23]_i_2_n_0 ;\n wire \\cmd_pipe_plus.mc_address[24]_i_2_n_0 ;\n wire \\cmd_pipe_plus.mc_address[25]_i_2_n_0 ;\n wire [7:0]\\cmd_pipe_plus.mc_address_reg[25] ;\n wire \\cmd_pipe_plus.mc_bank[3]_i_2_n_0 ;\n wire \\cmd_pipe_plus.mc_bank[4]_i_2_n_0 ;\n wire \\cmd_pipe_plus.mc_bank[5]_i_2_n_0 ;\n wire [2:0]\\cmd_pipe_plus.mc_bank_reg[5] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[0] ;\n wire \\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ;\n wire \\cmd_pipe_plus.mc_we_n_reg[1] ;\n wire [4:0]col_data_buf_addr;\n wire [0:0]col_data_buf_addr_r;\n wire \\col_mux.col_data_buf_addr_r[4]_i_2_n_0 ;\n wire \\col_mux.col_periodic_rd_r_i_2_n_0 ;\n wire col_periodic_rd_r;\n wire col_rd_wr;\n wire col_rd_wr_r;\n wire [3:0]\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ;\n wire demand_priority_r_reg;\n wire \\genblk3[1].rnk_config_strobe_r_reg ;\n wire \\genblk3[2].rnk_config_strobe_r_reg ;\n wire \\grant_r[0]_i_1__0_n_0 ;\n wire \\grant_r[1]_i_1__0_n_0 ;\n wire \\grant_r[2]_i_1__0_n_0 ;\n wire \\grant_r[2]_i_2_n_0 ;\n wire \\grant_r[2]_i_3__1_n_0 ;\n wire \\grant_r[3]_i_12_n_0 ;\n wire \\grant_r[3]_i_1_n_0 ;\n wire \\grant_r[3]_i_4__0_n_0 ;\n wire \\grant_r[3]_i_6_n_0 ;\n wire \\grant_r_reg[1]_0 ;\n wire \\grant_r_reg[1]_1 ;\n wire \\grant_r_reg[2]_0 ;\n wire \\grant_r_reg[3]_0 ;\n wire \\grant_r_reg[3]_1 ;\n wire granted_col_r_reg;\n wire i___32_i_2_n_0;\n wire [3:0]last_master_r;\n wire \\last_master_r[0]_i_1_n_0 ;\n wire \\last_master_r[1]_i_1_n_0 ;\n wire \\last_master_r[2]_i_1__0_n_0 ;\n wire \\last_master_r[3]_i_1_n_0 ;\n wire ofs_rdy_r;\n wire ofs_rdy_r_3;\n wire ofs_rdy_r_4;\n wire ofs_rdy_r_5;\n wire \\periodic_rd_generation.periodic_rd_timer_r_reg[2] ;\n wire \\periodic_rd_generation.read_this_rank_r_i_2_n_0 ;\n wire [3:0]rd_this_rank_r;\n wire rd_wr_r_lcl_reg;\n wire rd_wr_r_lcl_reg_0;\n wire rd_wr_r_lcl_reg_1;\n wire rd_wr_r_lcl_reg_2;\n wire rd_wr_r_lcl_reg_3;\n wire rd_wr_r_lcl_reg_4;\n wire rd_wr_r_lcl_reg_5;\n wire rd_wr_r_lcl_reg_6;\n wire rd_wr_r_lcl_reg_7;\n wire \\read_fifo.fifo_ram[0].RAM32M0_i_10_n_0 ;\n wire \\read_fifo.fifo_ram[0].RAM32M0_i_7_n_0 ;\n wire \\read_fifo.fifo_ram[0].RAM32M0_i_8_n_0 ;\n wire \\read_fifo.fifo_ram[0].RAM32M0_i_9_n_0 ;\n wire read_this_rank;\n wire read_this_rank_r;\n wire [2:0]\\req_bank_r_lcl_reg[2] ;\n wire [2:0]\\req_bank_r_lcl_reg[2]_0 ;\n wire [2:0]\\req_bank_r_lcl_reg[2]_1 ;\n wire [2:0]\\req_bank_r_lcl_reg[2]_2 ;\n wire req_bank_rdy_r;\n wire [6:0]\\req_col_r_reg[9] ;\n wire [6:0]\\req_col_r_reg[9]_0 ;\n wire [6:0]\\req_col_r_reg[9]_1 ;\n wire [6:0]\\req_col_r_reg[9]_2 ;\n wire [19:0]req_data_buf_addr_r;\n wire [3:0]req_periodic_rd_r;\n wire rnk_config_strobe;\n wire rnk_config_valid_r_lcl_reg;\n wire rstdiv0_sync_r1_reg_rep__21;\n wire rstdiv0_sync_r1_reg_rep__22;\n wire \\rtw_timer.rtw_cnt_r[1]_i_3_n_0 ;\n wire \\rtw_timer.rtw_cnt_r_reg[1] ;\n wire [0:0]\\rtw_timer.rtw_cnt_r_reg[1]_0 ;\n wire [3:0]wr_this_rank_r;\n wire \\wtr_timer.wtr_cnt_r_reg[0] ;\n wire \\wtr_timer.wtr_cnt_r_reg[1] ;\n wire \\wtr_timer.wtr_cnt_r_reg[1]_0 ;\n\n (* SOFT_HLUTNM = \"soft_lutpair1046\" *) \n LUT4 #(\n .INIT(16'hF737)) \n \\cmd_pipe_plus.mc_address[18]_i_1 \n (.I0(\\cmd_pipe_plus.mc_address[18]_i_2_n_0 ),\n .I1(granted_col_r_reg),\n .I2(Q[3]),\n .I3(\\req_col_r_reg[9] [0]),\n .O(\\cmd_pipe_plus.mc_address_reg[25] [0]));\n LUT6 #(\n .INIT(64'h00000F77FFFF0F77)) \n \\cmd_pipe_plus.mc_address[18]_i_2 \n (.I0(\\req_col_r_reg[9]_0 [0]),\n .I1(Q[0]),\n .I2(\\req_col_r_reg[9]_1 [0]),\n .I3(Q[1]),\n .I4(Q[2]),\n .I5(\\req_col_r_reg[9]_2 [0]),\n .O(\\cmd_pipe_plus.mc_address[18]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1047\" *) \n LUT4 #(\n .INIT(16'hF737)) \n \\cmd_pipe_plus.mc_address[19]_i_1 \n (.I0(\\cmd_pipe_plus.mc_address[19]_i_2_n_0 ),\n .I1(granted_col_r_reg),\n .I2(Q[3]),\n .I3(\\req_col_r_reg[9] [1]),\n .O(\\cmd_pipe_plus.mc_address_reg[25] [1]));\n LUT6 #(\n .INIT(64'h00000F77FFFF0F77)) \n \\cmd_pipe_plus.mc_address[19]_i_2 \n (.I0(\\req_col_r_reg[9]_0 [1]),\n .I1(Q[0]),\n .I2(\\req_col_r_reg[9]_1 [1]),\n .I3(Q[1]),\n .I4(Q[2]),\n .I5(\\req_col_r_reg[9]_2 [1]),\n .O(\\cmd_pipe_plus.mc_address[19]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'hF737)) \n \\cmd_pipe_plus.mc_address[20]_i_1 \n (.I0(\\cmd_pipe_plus.mc_address[20]_i_2_n_0 ),\n .I1(granted_col_r_reg),\n .I2(Q[3]),\n .I3(\\req_col_r_reg[9] [2]),\n .O(\\cmd_pipe_plus.mc_address_reg[25] [2]));\n LUT6 #(\n .INIT(64'h00000F77FFFF0F77)) \n \\cmd_pipe_plus.mc_address[20]_i_2 \n (.I0(\\req_col_r_reg[9]_0 [2]),\n .I1(Q[0]),\n .I2(\\req_col_r_reg[9]_1 [2]),\n .I3(Q[1]),\n .I4(Q[2]),\n .I5(\\req_col_r_reg[9]_2 [2]),\n .O(\\cmd_pipe_plus.mc_address[20]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'hF737)) \n \\cmd_pipe_plus.mc_address[21]_i_1 \n (.I0(\\cmd_pipe_plus.mc_address[21]_i_2_n_0 ),\n .I1(granted_col_r_reg),\n .I2(Q[3]),\n .I3(\\req_col_r_reg[9] [3]),\n .O(\\cmd_pipe_plus.mc_address_reg[25] [3]));\n LUT6 #(\n .INIT(64'h00000F77FFFF0F77)) \n \\cmd_pipe_plus.mc_address[21]_i_2 \n (.I0(\\req_col_r_reg[9]_0 [3]),\n .I1(Q[0]),\n .I2(\\req_col_r_reg[9]_1 [3]),\n .I3(Q[1]),\n .I4(Q[2]),\n .I5(\\req_col_r_reg[9]_2 [3]),\n .O(\\cmd_pipe_plus.mc_address[21]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'hF737)) \n \\cmd_pipe_plus.mc_address[22]_i_1 \n (.I0(\\cmd_pipe_plus.mc_address[22]_i_2_n_0 ),\n .I1(granted_col_r_reg),\n .I2(Q[3]),\n .I3(\\req_col_r_reg[9] [4]),\n .O(\\cmd_pipe_plus.mc_address_reg[25] [4]));\n LUT6 #(\n .INIT(64'h00000F77FFFF0F77)) \n \\cmd_pipe_plus.mc_address[22]_i_2 \n (.I0(\\req_col_r_reg[9]_0 [4]),\n .I1(Q[0]),\n .I2(\\req_col_r_reg[9]_1 [4]),\n .I3(Q[1]),\n .I4(Q[2]),\n .I5(\\req_col_r_reg[9]_2 [4]),\n .O(\\cmd_pipe_plus.mc_address[22]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'hF737)) \n \\cmd_pipe_plus.mc_address[23]_i_1 \n (.I0(\\cmd_pipe_plus.mc_address[23]_i_2_n_0 ),\n .I1(granted_col_r_reg),\n .I2(Q[3]),\n .I3(\\req_col_r_reg[9] [5]),\n .O(\\cmd_pipe_plus.mc_address_reg[25] [5]));\n LUT6 #(\n .INIT(64'h00000F77FFFF0F77)) \n \\cmd_pipe_plus.mc_address[23]_i_2 \n (.I0(\\req_col_r_reg[9]_0 [5]),\n .I1(Q[0]),\n .I2(\\req_col_r_reg[9]_1 [5]),\n .I3(Q[1]),\n .I4(Q[2]),\n .I5(\\req_col_r_reg[9]_2 [5]),\n .O(\\cmd_pipe_plus.mc_address[23]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'hF737)) \n \\cmd_pipe_plus.mc_address[24]_i_1 \n (.I0(\\cmd_pipe_plus.mc_address[24]_i_2_n_0 ),\n .I1(granted_col_r_reg),\n .I2(Q[3]),\n .I3(\\req_col_r_reg[9] [6]),\n .O(\\cmd_pipe_plus.mc_address_reg[25] [6]));\n LUT6 #(\n .INIT(64'h00000F77FFFF0F77)) \n \\cmd_pipe_plus.mc_address[24]_i_2 \n (.I0(\\req_col_r_reg[9]_0 [6]),\n .I1(Q[0]),\n .I2(\\req_col_r_reg[9]_1 [6]),\n .I3(Q[1]),\n .I4(Q[2]),\n .I5(\\req_col_r_reg[9]_2 [6]),\n .O(\\cmd_pipe_plus.mc_address[24]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'hF737)) \n \\cmd_pipe_plus.mc_address[25]_i_1 \n (.I0(\\cmd_pipe_plus.mc_address[25]_i_2_n_0 ),\n .I1(granted_col_r_reg),\n .I2(Q[3]),\n .I3(auto_pre_r_lcl_reg),\n .O(\\cmd_pipe_plus.mc_address_reg[25] [7]));\n LUT6 #(\n .INIT(64'h00000F77FFFF0F77)) \n \\cmd_pipe_plus.mc_address[25]_i_2 \n (.I0(auto_pre_r_lcl_reg_0),\n .I1(Q[0]),\n .I2(auto_pre_r_lcl_reg_1),\n .I3(Q[1]),\n .I4(Q[2]),\n .I5(auto_pre_r_lcl_reg_2),\n .O(\\cmd_pipe_plus.mc_address[25]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'hF737)) \n \\cmd_pipe_plus.mc_bank[3]_i_1 \n (.I0(\\cmd_pipe_plus.mc_bank[3]_i_2_n_0 ),\n .I1(granted_col_r_reg),\n .I2(Q[3]),\n .I3(\\req_bank_r_lcl_reg[2] [0]),\n .O(\\cmd_pipe_plus.mc_bank_reg[5] [0]));\n LUT6 #(\n .INIT(64'h00000F77FFFF0F77)) \n \\cmd_pipe_plus.mc_bank[3]_i_2 \n (.I0(\\req_bank_r_lcl_reg[2]_0 [0]),\n .I1(Q[0]),\n .I2(\\req_bank_r_lcl_reg[2]_1 [0]),\n .I3(Q[1]),\n .I4(Q[2]),\n .I5(\\req_bank_r_lcl_reg[2]_2 [0]),\n .O(\\cmd_pipe_plus.mc_bank[3]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'hF737)) \n \\cmd_pipe_plus.mc_bank[4]_i_1 \n (.I0(\\cmd_pipe_plus.mc_bank[4]_i_2_n_0 ),\n .I1(granted_col_r_reg),\n .I2(Q[3]),\n .I3(\\req_bank_r_lcl_reg[2] [1]),\n .O(\\cmd_pipe_plus.mc_bank_reg[5] [1]));\n LUT6 #(\n .INIT(64'h00000F77FFFF0F77)) \n \\cmd_pipe_plus.mc_bank[4]_i_2 \n (.I0(\\req_bank_r_lcl_reg[2]_0 [1]),\n .I1(Q[0]),\n .I2(\\req_bank_r_lcl_reg[2]_1 [1]),\n .I3(Q[1]),\n .I4(Q[2]),\n .I5(\\req_bank_r_lcl_reg[2]_2 [1]),\n .O(\\cmd_pipe_plus.mc_bank[4]_i_2_n_0 ));\n LUT4 #(\n .INIT(16'hF737)) \n \\cmd_pipe_plus.mc_bank[5]_i_1 \n (.I0(\\cmd_pipe_plus.mc_bank[5]_i_2_n_0 ),\n .I1(granted_col_r_reg),\n .I2(Q[3]),\n .I3(\\req_bank_r_lcl_reg[2] [2]),\n .O(\\cmd_pipe_plus.mc_bank_reg[5] [2]));\n LUT6 #(\n .INIT(64'h00000F77FFFF0F77)) \n \\cmd_pipe_plus.mc_bank[5]_i_2 \n (.I0(\\req_bank_r_lcl_reg[2]_0 [2]),\n .I1(Q[0]),\n .I2(\\req_bank_r_lcl_reg[2]_1 [2]),\n .I3(Q[1]),\n .I4(Q[2]),\n .I5(\\req_bank_r_lcl_reg[2]_2 [2]),\n .O(\\cmd_pipe_plus.mc_bank[5]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1045\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\cmd_pipe_plus.mc_cmd[1]_i_1 \n (.I0(granted_col_r_reg),\n .I1(\\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ),\n .O(E));\n (* SOFT_HLUTNM = \"soft_lutpair1047\" *) \n LUT2 #(\n .INIT(4'hD)) \n \\cmd_pipe_plus.mc_data_offset[5]_i_1 \n (.I0(granted_col_r_reg),\n .I1(\\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ),\n .O(\\cmd_pipe_plus.mc_data_offset_1_reg[0] ));\n LUT6 #(\n .INIT(64'h55555554FFFFFFFF)) \n \\cmd_pipe_plus.mc_we_n[1]_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ),\n .I1(Q[2]),\n .I2(Q[3]),\n .I3(Q[0]),\n .I4(Q[1]),\n .I5(granted_col_r_reg),\n .O(\\cmd_pipe_plus.mc_we_n_reg[1] ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\col_mux.col_data_buf_addr_r[4]_i_1 \n (.I0(req_data_buf_addr_r[19]),\n .I1(Q[3]),\n .I2(req_data_buf_addr_r[14]),\n .I3(Q[2]),\n .I4(\\col_mux.col_data_buf_addr_r[4]_i_2_n_0 ),\n .O(col_data_buf_addr[4]));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\col_mux.col_data_buf_addr_r[4]_i_2 \n (.I0(req_data_buf_addr_r[9]),\n .I1(Q[1]),\n .I2(req_data_buf_addr_r[4]),\n .I3(Q[0]),\n .I4(col_data_buf_addr_r),\n .O(\\col_mux.col_data_buf_addr_r[4]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hFFCA00CA)) \n \\col_mux.col_periodic_rd_r_i_1 \n (.I0(\\col_mux.col_periodic_rd_r_i_2_n_0 ),\n .I1(req_periodic_rd_r[2]),\n .I2(Q[2]),\n .I3(Q[3]),\n .I4(req_periodic_rd_r[3]),\n .O(DIC));\n LUT6 #(\n .INIT(64'hAAAAFF00AAAA3030)) \n \\col_mux.col_periodic_rd_r_i_2 \n (.I0(req_periodic_rd_r[1]),\n .I1(rstdiv0_sync_r1_reg_rep__21),\n .I2(col_periodic_rd_r),\n .I3(req_periodic_rd_r[0]),\n .I4(Q[1]),\n .I5(Q[0]),\n .O(\\col_mux.col_periodic_rd_r_i_2_n_0 ));\n LUT1 #(\n .INIT(2'h1)) \n \\col_mux.col_rd_wr_r_i_1 \n (.I0(\\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ),\n .O(col_rd_wr));\n (* SOFT_HLUTNM = \"soft_lutpair1046\" *) \n LUT3 #(\n .INIT(8'hDF)) \n demand_priority_r_i_5__2\n (.I0(req_bank_rdy_r),\n .I1(Q[3]),\n .I2(granted_col_r_reg),\n .O(demand_priority_r_reg));\n LUT5 #(\n .INIT(32'h00000E00)) \n \\grant_r[0]_i_1__0 \n (.I0(rd_wr_r_lcl_reg_0),\n .I1(\\grant_r[3]_i_4__0_n_0 ),\n .I2(\\grant_r[2]_i_2_n_0 ),\n .I3(rd_wr_r_lcl_reg_2),\n .I4(\\grant_r[3]_i_6_n_0 ),\n .O(\\grant_r[0]_i_1__0_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000032323)) \n \\grant_r[1]_i_1__0 \n (.I0(rd_wr_r_lcl_reg_0),\n .I1(rd_wr_r_lcl_reg_1),\n .I2(\\last_master_r[1]_i_1_n_0 ),\n .I3(\\grant_r[2]_i_3__1_n_0 ),\n .I4(rd_wr_r_lcl_reg_2),\n .I5(\\grant_r[2]_i_2_n_0 ),\n .O(\\grant_r[1]_i_1__0_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFDF)) \n \\grant_r[1]_i_7 \n (.I0(rnk_config_valid_r_lcl_reg),\n .I1(Q[1]),\n .I2(ofs_rdy_r_3),\n .I3(\\genblk3[1].rnk_config_strobe_r_reg ),\n .I4(\\genblk3[2].rnk_config_strobe_r_reg ),\n .I5(rnk_config_strobe),\n .O(\\grant_r_reg[1]_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFDF)) \n \\grant_r[1]_i_8 \n (.I0(rnk_config_valid_r_lcl_reg),\n .I1(Q[0]),\n .I2(ofs_rdy_r_4),\n .I3(\\genblk3[1].rnk_config_strobe_r_reg ),\n .I4(\\genblk3[2].rnk_config_strobe_r_reg ),\n .I5(rnk_config_strobe),\n .O(\\grant_r_reg[1]_1 ));\n LUT5 #(\n .INIT(32'h00044444)) \n \\grant_r[2]_i_1__0 \n (.I0(\\grant_r[3]_i_6_n_0 ),\n .I1(rd_wr_r_lcl_reg_3),\n .I2(rd_wr_r_lcl_reg_4),\n .I3(\\grant_r[2]_i_2_n_0 ),\n .I4(\\grant_r[2]_i_3__1_n_0 ),\n .O(\\grant_r[2]_i_1__0_n_0 ));\n LUT5 #(\n .INIT(32'h00004540)) \n \\grant_r[2]_i_2 \n (.I0(rstdiv0_sync_r1_reg_rep__21),\n .I1(Q[2]),\n .I2(granted_col_r_reg),\n .I3(last_master_r[2]),\n .I4(rd_wr_r_lcl_reg_5),\n .O(\\grant_r[2]_i_2_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFAFFFACC)) \n \\grant_r[2]_i_3__1 \n (.I0(Q[2]),\n .I1(last_master_r[2]),\n .I2(Q[3]),\n .I3(granted_col_r_reg),\n .I4(last_master_r[3]),\n .I5(rstdiv0_sync_r1_reg_rep__22),\n .O(\\grant_r[2]_i_3__1_n_0 ));\n LUT6 #(\n .INIT(64'h0000000000001F15)) \n \\grant_r[3]_i_1 \n (.I0(rd_wr_r_lcl_reg_3),\n .I1(rd_wr_r_lcl_reg_4),\n .I2(\\last_master_r[3]_i_1_n_0 ),\n .I3(\\grant_r[3]_i_4__0_n_0 ),\n .I4(rd_wr_r_lcl_reg_5),\n .I5(\\grant_r[3]_i_6_n_0 ),\n .O(\\grant_r[3]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1044\" *) \n LUT4 #(\n .INIT(16'h0001)) \n \\grant_r[3]_i_12 \n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(Q[3]),\n .I3(Q[2]),\n .O(\\grant_r[3]_i_12_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFDF)) \n \\grant_r[3]_i_14 \n (.I0(rnk_config_valid_r_lcl_reg),\n .I1(Q[2]),\n .I2(ofs_rdy_r_5),\n .I3(\\genblk3[1].rnk_config_strobe_r_reg ),\n .I4(\\genblk3[2].rnk_config_strobe_r_reg ),\n .I5(rnk_config_strobe),\n .O(\\grant_r_reg[2]_0 ));\n LUT6 #(\n .INIT(64'hFFFFFFFFFFFFFFDF)) \n \\grant_r[3]_i_16 \n (.I0(rnk_config_valid_r_lcl_reg),\n .I1(Q[3]),\n .I2(ofs_rdy_r),\n .I3(\\genblk3[1].rnk_config_strobe_r_reg ),\n .I4(\\genblk3[2].rnk_config_strobe_r_reg ),\n .I5(rnk_config_strobe),\n .O(\\grant_r_reg[3]_1 ));\n LUT6 #(\n .INIT(64'hF0F5F0F0F0F5F3F3)) \n \\grant_r[3]_i_4__0 \n (.I0(Q[0]),\n .I1(last_master_r[0]),\n .I2(rstdiv0_sync_r1_reg_rep__22),\n .I3(Q[1]),\n .I4(granted_col_r_reg),\n .I5(last_master_r[1]),\n .O(\\grant_r[3]_i_4__0_n_0 ));\n LUT5 #(\n .INIT(32'h00004540)) \n \\grant_r[3]_i_6 \n (.I0(rstdiv0_sync_r1_reg_rep__21),\n .I1(Q[0]),\n .I2(granted_col_r_reg),\n .I3(last_master_r[0]),\n .I4(rd_wr_r_lcl_reg_1),\n .O(\\grant_r[3]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF0000FFFFFFAB)) \n \\grant_r[3]_i_7 \n (.I0(rd_wr_r_lcl_reg),\n .I1(\\rtw_timer.rtw_cnt_r[1]_i_3_n_0 ),\n .I2(i___32_i_2_n_0),\n .I3(\\grant_r[3]_i_12_n_0 ),\n .I4(rstdiv0_sync_r1_reg_rep__21),\n .I5(\\rtw_timer.rtw_cnt_r_reg[1]_0 ),\n .O(\\grant_r_reg[3]_0 ));\n FDRE \\grant_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\grant_r[0]_i_1__0_n_0 ),\n .Q(Q[0]),\n .R(1'b0));\n FDRE \\grant_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\grant_r[1]_i_1__0_n_0 ),\n .Q(Q[1]),\n .R(1'b0));\n FDRE \\grant_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\grant_r[2]_i_1__0_n_0 ),\n .Q(Q[2]),\n .R(1'b0));\n FDRE \\grant_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\grant_r[3]_i_1_n_0 ),\n .Q(Q[3]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'hAAAAA888A888A888)) \n i___30_i_1\n (.I0(read_this_rank_r),\n .I1(\\periodic_rd_generation.read_this_rank_r_i_2_n_0 ),\n .I2(rd_this_rank_r[1]),\n .I3(Q[1]),\n .I4(rd_this_rank_r[2]),\n .I5(Q[2]),\n .O(\\periodic_rd_generation.periodic_rd_timer_r_reg[2] ));\n LUT6 #(\n .INIT(64'hFFFFFFFF00155515)) \n i___32_i_1\n (.I0(i___32_i_2_n_0),\n .I1(Q[0]),\n .I2(rd_wr_r_lcl_reg_6),\n .I3(Q[1]),\n .I4(rd_wr_r_lcl_reg_7),\n .I5(rd_wr_r_lcl_reg),\n .O(\\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1044\" *) \n LUT5 #(\n .INIT(32'hEEEFEEEE)) \n i___32_i_2\n (.I0(Q[3]),\n .I1(Q[2]),\n .I2(Q[0]),\n .I3(Q[1]),\n .I4(col_rd_wr_r),\n .O(i___32_i_2_n_0));\n LUT4 #(\n .INIT(16'hF888)) \n i___86_i_1\n (.I0(wr_this_rank_r[3]),\n .I1(Q[3]),\n .I2(wr_this_rank_r[1]),\n .I3(Q[1]),\n .O(\\wtr_timer.wtr_cnt_r_reg[1]_0 ));\n LUT4 #(\n .INIT(16'hF888)) \n i___86_i_2\n (.I0(wr_this_rank_r[0]),\n .I1(Q[0]),\n .I2(wr_this_rank_r[2]),\n .I3(Q[2]),\n .O(\\wtr_timer.wtr_cnt_r_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair1045\" *) \n LUT4 #(\n .INIT(16'h00E2)) \n \\last_master_r[0]_i_1 \n (.I0(last_master_r[0]),\n .I1(granted_col_r_reg),\n .I2(Q[0]),\n .I3(rstdiv0_sync_r1_reg_rep__22),\n .O(\\last_master_r[0]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h00E2)) \n \\last_master_r[1]_i_1 \n (.I0(last_master_r[1]),\n .I1(granted_col_r_reg),\n .I2(Q[1]),\n .I3(rstdiv0_sync_r1_reg_rep__22),\n .O(\\last_master_r[1]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h00E2)) \n \\last_master_r[2]_i_1__0 \n (.I0(last_master_r[2]),\n .I1(granted_col_r_reg),\n .I2(Q[2]),\n .I3(rstdiv0_sync_r1_reg_rep__22),\n .O(\\last_master_r[2]_i_1__0_n_0 ));\n LUT4 #(\n .INIT(16'hFEAE)) \n \\last_master_r[3]_i_1 \n (.I0(rstdiv0_sync_r1_reg_rep__22),\n .I1(last_master_r[3]),\n .I2(granted_col_r_reg),\n .I3(Q[3]),\n .O(\\last_master_r[3]_i_1_n_0 ));\n FDRE \\last_master_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\last_master_r[0]_i_1_n_0 ),\n .Q(last_master_r[0]),\n .R(1'b0));\n FDRE \\last_master_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\last_master_r[1]_i_1_n_0 ),\n .Q(last_master_r[1]),\n .R(1'b0));\n FDRE \\last_master_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\last_master_r[2]_i_1__0_n_0 ),\n .Q(last_master_r[2]),\n .R(1'b0));\n FDRE \\last_master_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\last_master_r[3]_i_1_n_0 ),\n .Q(last_master_r[3]),\n .R(1'b0));\n LUT5 #(\n .INIT(32'hFFEAEAEA)) \n \\periodic_rd_generation.read_this_rank_r_i_1 \n (.I0(\\periodic_rd_generation.read_this_rank_r_i_2_n_0 ),\n .I1(rd_this_rank_r[1]),\n .I2(Q[1]),\n .I3(rd_this_rank_r[2]),\n .I4(Q[2]),\n .O(read_this_rank));\n LUT4 #(\n .INIT(16'hF888)) \n \\periodic_rd_generation.read_this_rank_r_i_2 \n (.I0(rd_this_rank_r[0]),\n .I1(Q[0]),\n .I2(rd_this_rank_r[3]),\n .I3(Q[3]),\n .O(\\periodic_rd_generation.read_this_rank_r_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\read_fifo.fifo_ram[0].RAM32M0_i_1 \n (.I0(req_data_buf_addr_r[18]),\n .I1(Q[3]),\n .I2(req_data_buf_addr_r[13]),\n .I3(Q[2]),\n .I4(\\read_fifo.fifo_ram[0].RAM32M0_i_7_n_0 ),\n .O(col_data_buf_addr[3]));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\read_fifo.fifo_ram[0].RAM32M0_i_10 \n (.I0(req_data_buf_addr_r[5]),\n .I1(Q[1]),\n .I2(req_data_buf_addr_r[0]),\n .I3(Q[0]),\n .I4(\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] [0]),\n .O(\\read_fifo.fifo_ram[0].RAM32M0_i_10_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\read_fifo.fifo_ram[0].RAM32M0_i_2 \n (.I0(req_data_buf_addr_r[17]),\n .I1(Q[3]),\n .I2(req_data_buf_addr_r[12]),\n .I3(Q[2]),\n .I4(\\read_fifo.fifo_ram[0].RAM32M0_i_8_n_0 ),\n .O(col_data_buf_addr[2]));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\read_fifo.fifo_ram[0].RAM32M0_i_3 \n (.I0(req_data_buf_addr_r[16]),\n .I1(Q[3]),\n .I2(req_data_buf_addr_r[11]),\n .I3(Q[2]),\n .I4(\\read_fifo.fifo_ram[0].RAM32M0_i_9_n_0 ),\n .O(col_data_buf_addr[1]));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\read_fifo.fifo_ram[0].RAM32M0_i_4 \n (.I0(req_data_buf_addr_r[15]),\n .I1(Q[3]),\n .I2(req_data_buf_addr_r[10]),\n .I3(Q[2]),\n .I4(\\read_fifo.fifo_ram[0].RAM32M0_i_10_n_0 ),\n .O(col_data_buf_addr[0]));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\read_fifo.fifo_ram[0].RAM32M0_i_7 \n (.I0(req_data_buf_addr_r[8]),\n .I1(Q[1]),\n .I2(req_data_buf_addr_r[3]),\n .I3(Q[0]),\n .I4(\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] [3]),\n .O(\\read_fifo.fifo_ram[0].RAM32M0_i_7_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\read_fifo.fifo_ram[0].RAM32M0_i_8 \n (.I0(req_data_buf_addr_r[7]),\n .I1(Q[1]),\n .I2(req_data_buf_addr_r[2]),\n .I3(Q[0]),\n .I4(\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] [2]),\n .O(\\read_fifo.fifo_ram[0].RAM32M0_i_8_n_0 ));\n LUT5 #(\n .INIT(32'hB8BBB888)) \n \\read_fifo.fifo_ram[0].RAM32M0_i_9 \n (.I0(req_data_buf_addr_r[6]),\n .I1(Q[1]),\n .I2(req_data_buf_addr_r[1]),\n .I3(Q[0]),\n .I4(\\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] [1]),\n .O(\\read_fifo.fifo_ram[0].RAM32M0_i_9_n_0 ));\n LUT6 #(\n .INIT(64'hF0F0F0F0F0F0F1FF)) \n \\rtw_timer.rtw_cnt_r[1]_i_2 \n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(rd_wr_r_lcl_reg),\n .I3(\\rtw_timer.rtw_cnt_r[1]_i_3_n_0 ),\n .I4(Q[2]),\n .I5(Q[3]),\n .O(\\rtw_timer.rtw_cnt_r_reg[1] ));\n LUT4 #(\n .INIT(16'hF808)) \n \\rtw_timer.rtw_cnt_r[1]_i_3 \n (.I0(Q[0]),\n .I1(rd_wr_r_lcl_reg_6),\n .I2(Q[1]),\n .I3(rd_wr_r_lcl_reg_7),\n .O(\\rtw_timer.rtw_cnt_r[1]_i_3_n_0 ));\n LUT6 #(\n .INIT(64'hFFFFFEEEFEEEFEEE)) \n \\wtr_timer.wtr_cnt_r[0]_i_2 \n (.I0(rstdiv0_sync_r1_reg_rep__22),\n .I1(\\wtr_timer.wtr_cnt_r_reg[1] ),\n .I2(wr_this_rank_r[3]),\n .I3(Q[3]),\n .I4(wr_this_rank_r[1]),\n .I5(Q[1]),\n .O(\\wtr_timer.wtr_cnt_r_reg[0] ));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_tempmon\n (out,\n D,\n mmcm_clk,\n in0,\n CLK);\n output [11:0]out;\n output [11:0]D;\n input mmcm_clk;\n input in0;\n input CLK;\n\n wire CLK;\n wire [11:0]D;\n wire \\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 ;\n (* RTL_KEEP = \"yes\" *) wire \\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ;\n (* RTL_KEEP = \"yes\" *) wire \\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[1] ;\n (* RTL_KEEP = \"yes\" *) wire \\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2] ;\n wire \\device_temp_101[11]_i_4_n_0 ;\n wire \\device_temp_101[11]_i_5_n_0 ;\n wire \\device_temp_101[11]_i_6_n_0 ;\n wire \\device_temp_101[11]_i_7_n_0 ;\n wire \\device_temp_101[11]_i_8_n_0 ;\n wire [11:0]device_temp_lcl;\n (* async_reg = \"true\" *) wire [11:0]device_temp_r;\n wire \\device_temp_r[11]_i_1_n_0 ;\n (* async_reg = \"true\" *) wire [11:0]device_temp_sync_r1;\n (* async_reg = \"true\" *) wire [11:0]device_temp_sync_r2;\n (* async_reg = \"true\" *) (* syn_srlstyle = \"registers\" *) wire [11:0]device_temp_sync_r3;\n (* async_reg = \"true\" *) wire [11:0]device_temp_sync_r4;\n wire device_temp_sync_r4_neq_r3;\n wire device_temp_sync_r4_neq_r3_i_2_n_0;\n wire device_temp_sync_r4_neq_r3_i_3_n_0;\n wire device_temp_sync_r4_neq_r3_i_4_n_0;\n wire device_temp_sync_r4_neq_r3_i_5_n_0;\n wire device_temp_sync_r4_neq_r3_reg_i_1_n_0;\n wire device_temp_sync_r4_neq_r3_reg_i_1_n_1;\n wire device_temp_sync_r4_neq_r3_reg_i_1_n_2;\n wire device_temp_sync_r4_neq_r3_reg_i_1_n_3;\n (* async_reg = \"true\" *) wire [11:0]device_temp_sync_r5;\n wire in0;\n wire mmcm_clk;\n wire [11:0]p_0_in;\n wire [10:1]p_0_in__0;\n wire [1:0]p_0_in__1;\n (* async_reg = \"true\" *) wire rst_r1;\n (* async_reg = \"true\" *) wire rst_r2;\n wire sample_en;\n wire sample_en0;\n wire sample_timer0;\n wire sample_timer_en;\n wire sync_cntr0;\n wire \\sync_cntr[2]_i_1_n_0 ;\n wire \\sync_cntr[3]_i_2_n_0 ;\n wire \\sync_cntr[3]_i_3_n_0 ;\n wire [3:0]sync_cntr_reg__0;\n (* RTL_KEEP = \"yes\" *) wire temperature;\n wire \\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ;\n wire \\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ;\n wire xadc_den;\n wire [15:0]xadc_do;\n wire xadc_drdy;\n wire xadc_drdy_r;\n wire \\xadc_supplied_temperature.sample_en_i_2_n_0 ;\n wire \\xadc_supplied_temperature.sample_timer[0]_i_1_n_0 ;\n wire \\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ;\n wire \\xadc_supplied_temperature.sample_timer_clr_i_1_n_0 ;\n wire \\xadc_supplied_temperature.sample_timer_en_i_1_n_0 ;\n wire [10:0]\\xadc_supplied_temperature.sample_timer_reg__0 ;\n wire [3:0]NLW_device_temp_sync_r4_neq_r3_reg_i_1_O_UNCONNECTED;\n wire \\NLW_xadc_supplied_temperature.XADC_inst_BUSY_UNCONNECTED ;\n wire \\NLW_xadc_supplied_temperature.XADC_inst_EOC_UNCONNECTED ;\n wire \\NLW_xadc_supplied_temperature.XADC_inst_EOS_UNCONNECTED ;\n wire \\NLW_xadc_supplied_temperature.XADC_inst_JTAGBUSY_UNCONNECTED ;\n wire \\NLW_xadc_supplied_temperature.XADC_inst_JTAGLOCKED_UNCONNECTED ;\n wire \\NLW_xadc_supplied_temperature.XADC_inst_JTAGMODIFIED_UNCONNECTED ;\n wire \\NLW_xadc_supplied_temperature.XADC_inst_OT_UNCONNECTED ;\n wire [7:0]\\NLW_xadc_supplied_temperature.XADC_inst_ALM_UNCONNECTED ;\n wire [4:0]\\NLW_xadc_supplied_temperature.XADC_inst_CHANNEL_UNCONNECTED ;\n wire [4:0]\\NLW_xadc_supplied_temperature.XADC_inst_MUXADDR_UNCONNECTED ;\n\n assign out[11:0] = device_temp_r;\n LUT6 #(\n .INIT(64'hFFFFFEEEFEEEFEEE)) \n \\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1 \n (.I0(\\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[1] ),\n .I1(temperature),\n .I2(\\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ),\n .I3(sample_en),\n .I4(\\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2] ),\n .I5(xadc_drdy_r),\n .O(\\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 ));\n (* KEEP = \"yes\" *) \n FDSE #(\n .INIT(1'b1)) \n \\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[0] \n (.C(mmcm_clk),\n .CE(\\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 ),\n .D(temperature),\n .Q(\\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ),\n .S(rst_r2));\n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[1] \n (.C(mmcm_clk),\n .CE(\\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 ),\n .D(\\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ),\n .Q(\\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[1] ),\n .R(rst_r2));\n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[2] \n (.C(mmcm_clk),\n .CE(\\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 ),\n .D(\\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[1] ),\n .Q(\\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2] ),\n .R(rst_r2));\n (* KEEP = \"yes\" *) \n FDRE #(\n .INIT(1'b0)) \n \\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[3] \n (.C(mmcm_clk),\n .CE(\\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 ),\n .D(\\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2] ),\n .Q(temperature),\n .R(rst_r2));\n LUT3 #(\n .INIT(8'h10)) \n \\device_temp_101[0]_i_1 \n (.I0(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),\n .I1(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),\n .I2(device_temp_r[0]),\n .O(D[0]));\n LUT3 #(\n .INIT(8'hBA)) \n \\device_temp_101[10]_i_1 \n (.I0(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),\n .I1(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),\n .I2(device_temp_r[10]),\n .O(D[10]));\n LUT3 #(\n .INIT(8'hFE)) \n \\device_temp_101[11]_i_1 \n (.I0(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),\n .I1(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),\n .I2(device_temp_r[11]),\n .O(D[11]));\n LUT6 #(\n .INIT(64'h0000000011111115)) \n \\device_temp_101[11]_i_2 \n (.I0(\\device_temp_101[11]_i_4_n_0 ),\n .I1(device_temp_r[11]),\n .I2(device_temp_r[8]),\n .I3(device_temp_r[10]),\n .I4(device_temp_r[9]),\n .I5(\\device_temp_101[11]_i_5_n_0 ),\n .O(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ));\n LUT5 #(\n .INIT(32'h0000FD55)) \n \\device_temp_101[11]_i_3 \n (.I0(\\device_temp_101[11]_i_6_n_0 ),\n .I1(device_temp_r[1]),\n .I2(device_temp_r[0]),\n .I3(device_temp_r[2]),\n .I4(\\device_temp_101[11]_i_7_n_0 ),\n .O(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ));\n LUT4 #(\n .INIT(16'h8000)) \n \\device_temp_101[11]_i_4 \n (.I0(device_temp_r[4]),\n .I1(device_temp_r[11]),\n .I2(device_temp_r[7]),\n .I3(device_temp_r[5]),\n .O(\\device_temp_101[11]_i_4_n_0 ));\n LUT6 #(\n .INIT(64'hE000A000A000A000)) \n \\device_temp_101[11]_i_5 \n (.I0(device_temp_r[6]),\n .I1(device_temp_r[5]),\n .I2(device_temp_r[7]),\n .I3(device_temp_r[11]),\n .I4(device_temp_r[2]),\n .I5(device_temp_r[3]),\n .O(\\device_temp_101[11]_i_5_n_0 ));\n LUT5 #(\n .INIT(32'h00000001)) \n \\device_temp_101[11]_i_6 \n (.I0(device_temp_r[6]),\n .I1(device_temp_r[9]),\n .I2(device_temp_r[8]),\n .I3(device_temp_r[4]),\n .I4(device_temp_r[3]),\n .O(\\device_temp_101[11]_i_6_n_0 ));\n LUT6 #(\n .INIT(64'h7F777F777F77FF77)) \n \\device_temp_101[11]_i_7 \n (.I0(device_temp_r[11]),\n .I1(device_temp_r[10]),\n .I2(device_temp_r[7]),\n .I3(\\device_temp_101[11]_i_8_n_0 ),\n .I4(device_temp_r[6]),\n .I5(device_temp_r[5]),\n .O(\\device_temp_101[11]_i_7_n_0 ));\n LUT2 #(\n .INIT(4'h1)) \n \\device_temp_101[11]_i_8 \n (.I0(device_temp_r[9]),\n .I1(device_temp_r[8]),\n .O(\\device_temp_101[11]_i_8_n_0 ));\n LUT3 #(\n .INIT(8'h10)) \n \\device_temp_101[1]_i_1 \n (.I0(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),\n .I1(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),\n .I2(device_temp_r[1]),\n .O(D[1]));\n LUT3 #(\n .INIT(8'hFE)) \n \\device_temp_101[2]_i_1 \n (.I0(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),\n .I1(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),\n .I2(device_temp_r[2]),\n .O(D[2]));\n LUT3 #(\n .INIT(8'hDC)) \n \\device_temp_101[3]_i_1 \n (.I0(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),\n .I1(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),\n .I2(device_temp_r[3]),\n .O(D[3]));\n LUT3 #(\n .INIT(8'h10)) \n \\device_temp_101[4]_i_1 \n (.I0(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),\n .I1(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),\n .I2(device_temp_r[4]),\n .O(D[4]));\n LUT3 #(\n .INIT(8'hFE)) \n \\device_temp_101[5]_i_1 \n (.I0(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),\n .I1(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),\n .I2(device_temp_r[5]),\n .O(D[5]));\n LUT3 #(\n .INIT(8'h10)) \n \\device_temp_101[6]_i_1 \n (.I0(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),\n .I1(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),\n .I2(device_temp_r[6]),\n .O(D[6]));\n LUT3 #(\n .INIT(8'hFE)) \n \\device_temp_101[7]_i_1 \n (.I0(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),\n .I1(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),\n .I2(device_temp_r[7]),\n .O(D[7]));\n LUT3 #(\n .INIT(8'h10)) \n \\device_temp_101[8]_i_1 \n (.I0(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),\n .I1(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),\n .I2(device_temp_r[8]),\n .O(D[8]));\n LUT3 #(\n .INIT(8'h10)) \n \\device_temp_101[9]_i_1 \n (.I0(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_high ),\n .I1(\\u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),\n .I2(device_temp_r[9]),\n .O(D[9]));\n LUT4 #(\n .INIT(16'h8000)) \n \\device_temp_r[11]_i_1 \n (.I0(sync_cntr_reg__0[3]),\n .I1(sync_cntr_reg__0[2]),\n .I2(sync_cntr_reg__0[0]),\n .I3(sync_cntr_reg__0[1]),\n .O(\\device_temp_r[11]_i_1_n_0 ));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_r_reg[0] \n (.C(CLK),\n .CE(\\device_temp_r[11]_i_1_n_0 ),\n .D(device_temp_sync_r5[0]),\n .Q(device_temp_r[0]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_r_reg[10] \n (.C(CLK),\n .CE(\\device_temp_r[11]_i_1_n_0 ),\n .D(device_temp_sync_r5[10]),\n .Q(device_temp_r[10]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_r_reg[11] \n (.C(CLK),\n .CE(\\device_temp_r[11]_i_1_n_0 ),\n .D(device_temp_sync_r5[11]),\n .Q(device_temp_r[11]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_r_reg[1] \n (.C(CLK),\n .CE(\\device_temp_r[11]_i_1_n_0 ),\n .D(device_temp_sync_r5[1]),\n .Q(device_temp_r[1]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_r_reg[2] \n (.C(CLK),\n .CE(\\device_temp_r[11]_i_1_n_0 ),\n .D(device_temp_sync_r5[2]),\n .Q(device_temp_r[2]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_r_reg[3] \n (.C(CLK),\n .CE(\\device_temp_r[11]_i_1_n_0 ),\n .D(device_temp_sync_r5[3]),\n .Q(device_temp_r[3]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_r_reg[4] \n (.C(CLK),\n .CE(\\device_temp_r[11]_i_1_n_0 ),\n .D(device_temp_sync_r5[4]),\n .Q(device_temp_r[4]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_r_reg[5] \n (.C(CLK),\n .CE(\\device_temp_r[11]_i_1_n_0 ),\n .D(device_temp_sync_r5[5]),\n .Q(device_temp_r[5]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_r_reg[6] \n (.C(CLK),\n .CE(\\device_temp_r[11]_i_1_n_0 ),\n .D(device_temp_sync_r5[6]),\n .Q(device_temp_r[6]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_r_reg[7] \n (.C(CLK),\n .CE(\\device_temp_r[11]_i_1_n_0 ),\n .D(device_temp_sync_r5[7]),\n .Q(device_temp_r[7]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_r_reg[8] \n (.C(CLK),\n .CE(\\device_temp_r[11]_i_1_n_0 ),\n .D(device_temp_sync_r5[8]),\n .Q(device_temp_r[8]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_r_reg[9] \n (.C(CLK),\n .CE(\\device_temp_r[11]_i_1_n_0 ),\n .D(device_temp_sync_r5[9]),\n .Q(device_temp_r[9]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_lcl[0]),\n .Q(device_temp_sync_r1[0]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r1_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_lcl[10]),\n .Q(device_temp_sync_r1[10]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r1_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_lcl[11]),\n .Q(device_temp_sync_r1[11]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r1_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_lcl[1]),\n .Q(device_temp_sync_r1[1]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r1_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_lcl[2]),\n .Q(device_temp_sync_r1[2]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r1_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_lcl[3]),\n .Q(device_temp_sync_r1[3]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r1_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_lcl[4]),\n .Q(device_temp_sync_r1[4]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r1_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_lcl[5]),\n .Q(device_temp_sync_r1[5]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r1_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_lcl[6]),\n .Q(device_temp_sync_r1[6]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r1_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_lcl[7]),\n .Q(device_temp_sync_r1[7]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r1_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_lcl[8]),\n .Q(device_temp_sync_r1[8]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r1_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_lcl[9]),\n .Q(device_temp_sync_r1[9]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r2_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r1[0]),\n .Q(device_temp_sync_r2[0]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r2_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r1[10]),\n .Q(device_temp_sync_r2[10]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r2_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r1[11]),\n .Q(device_temp_sync_r2[11]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r2_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r1[1]),\n .Q(device_temp_sync_r2[1]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r2_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r1[2]),\n .Q(device_temp_sync_r2[2]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r2_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r1[3]),\n .Q(device_temp_sync_r2[3]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r2_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r1[4]),\n .Q(device_temp_sync_r2[4]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r2_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r1[5]),\n .Q(device_temp_sync_r2[5]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r2_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r1[6]),\n .Q(device_temp_sync_r2[6]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r2_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r1[7]),\n .Q(device_temp_sync_r2[7]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r2_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r1[8]),\n .Q(device_temp_sync_r2[8]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r2_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r1[9]),\n .Q(device_temp_sync_r2[9]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* syn_srlstyle = \"registers\" *) \n FDRE \\device_temp_sync_r3_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r2[0]),\n .Q(device_temp_sync_r3[0]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* syn_srlstyle = \"registers\" *) \n FDRE \\device_temp_sync_r3_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r2[10]),\n .Q(device_temp_sync_r3[10]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* syn_srlstyle = \"registers\" *) \n FDRE \\device_temp_sync_r3_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r2[11]),\n .Q(device_temp_sync_r3[11]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* syn_srlstyle = \"registers\" *) \n FDRE \\device_temp_sync_r3_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r2[1]),\n .Q(device_temp_sync_r3[1]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* syn_srlstyle = \"registers\" *) \n FDRE \\device_temp_sync_r3_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r2[2]),\n .Q(device_temp_sync_r3[2]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* syn_srlstyle = \"registers\" *) \n FDRE \\device_temp_sync_r3_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r2[3]),\n .Q(device_temp_sync_r3[3]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* syn_srlstyle = \"registers\" *) \n FDRE \\device_temp_sync_r3_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r2[4]),\n .Q(device_temp_sync_r3[4]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* syn_srlstyle = \"registers\" *) \n FDRE \\device_temp_sync_r3_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r2[5]),\n .Q(device_temp_sync_r3[5]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* syn_srlstyle = \"registers\" *) \n FDRE \\device_temp_sync_r3_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r2[6]),\n .Q(device_temp_sync_r3[6]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* syn_srlstyle = \"registers\" *) \n FDRE \\device_temp_sync_r3_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r2[7]),\n .Q(device_temp_sync_r3[7]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* syn_srlstyle = \"registers\" *) \n FDRE \\device_temp_sync_r3_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r2[8]),\n .Q(device_temp_sync_r3[8]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n (* syn_srlstyle = \"registers\" *) \n FDRE \\device_temp_sync_r3_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r2[9]),\n .Q(device_temp_sync_r3[9]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n device_temp_sync_r4_neq_r3_i_2\n (.I0(device_temp_sync_r4[9]),\n .I1(device_temp_sync_r3[9]),\n .I2(device_temp_sync_r3[11]),\n .I3(device_temp_sync_r4[11]),\n .I4(device_temp_sync_r3[10]),\n .I5(device_temp_sync_r4[10]),\n .O(device_temp_sync_r4_neq_r3_i_2_n_0));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n device_temp_sync_r4_neq_r3_i_3\n (.I0(device_temp_sync_r4[6]),\n .I1(device_temp_sync_r3[6]),\n .I2(device_temp_sync_r3[8]),\n .I3(device_temp_sync_r4[8]),\n .I4(device_temp_sync_r3[7]),\n .I5(device_temp_sync_r4[7]),\n .O(device_temp_sync_r4_neq_r3_i_3_n_0));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n device_temp_sync_r4_neq_r3_i_4\n (.I0(device_temp_sync_r4[3]),\n .I1(device_temp_sync_r3[3]),\n .I2(device_temp_sync_r3[5]),\n .I3(device_temp_sync_r4[5]),\n .I4(device_temp_sync_r3[4]),\n .I5(device_temp_sync_r4[4]),\n .O(device_temp_sync_r4_neq_r3_i_4_n_0));\n LUT6 #(\n .INIT(64'h9009000000009009)) \n device_temp_sync_r4_neq_r3_i_5\n (.I0(device_temp_sync_r4[0]),\n .I1(device_temp_sync_r3[0]),\n .I2(device_temp_sync_r3[2]),\n .I3(device_temp_sync_r4[2]),\n .I4(device_temp_sync_r3[1]),\n .I5(device_temp_sync_r4[1]),\n .O(device_temp_sync_r4_neq_r3_i_5_n_0));\n FDRE device_temp_sync_r4_neq_r3_reg\n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r4_neq_r3_reg_i_1_n_0),\n .Q(device_temp_sync_r4_neq_r3),\n .R(1'b0));\n CARRY4 device_temp_sync_r4_neq_r3_reg_i_1\n (.CI(1'b0),\n .CO({device_temp_sync_r4_neq_r3_reg_i_1_n_0,device_temp_sync_r4_neq_r3_reg_i_1_n_1,device_temp_sync_r4_neq_r3_reg_i_1_n_2,device_temp_sync_r4_neq_r3_reg_i_1_n_3}),\n .CYINIT(1'b0),\n .DI({1'b1,1'b1,1'b1,1'b1}),\n .O(NLW_device_temp_sync_r4_neq_r3_reg_i_1_O_UNCONNECTED[3:0]),\n .S({device_temp_sync_r4_neq_r3_i_2_n_0,device_temp_sync_r4_neq_r3_i_3_n_0,device_temp_sync_r4_neq_r3_i_4_n_0,device_temp_sync_r4_neq_r3_i_5_n_0}));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r4_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r3[0]),\n .Q(device_temp_sync_r4[0]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r4_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r3[10]),\n .Q(device_temp_sync_r4[10]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r4_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r3[11]),\n .Q(device_temp_sync_r4[11]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r4_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r3[1]),\n .Q(device_temp_sync_r4[1]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r4_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r3[2]),\n .Q(device_temp_sync_r4[2]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r4_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r3[3]),\n .Q(device_temp_sync_r4[3]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r4_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r3[4]),\n .Q(device_temp_sync_r4[4]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r4_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r3[5]),\n .Q(device_temp_sync_r4[5]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r4_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r3[6]),\n .Q(device_temp_sync_r4[6]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r4_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r3[7]),\n .Q(device_temp_sync_r4[7]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r4_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r3[8]),\n .Q(device_temp_sync_r4[8]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r4_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r3[9]),\n .Q(device_temp_sync_r4[9]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r5_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r4[0]),\n .Q(device_temp_sync_r5[0]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r5_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r4[10]),\n .Q(device_temp_sync_r5[10]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r5_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r4[11]),\n .Q(device_temp_sync_r5[11]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r5_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r4[1]),\n .Q(device_temp_sync_r5[1]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r5_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r4[2]),\n .Q(device_temp_sync_r5[2]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r5_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r4[3]),\n .Q(device_temp_sync_r5[3]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r5_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r4[4]),\n .Q(device_temp_sync_r5[4]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r5_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r4[5]),\n .Q(device_temp_sync_r5[5]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r5_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r4[6]),\n .Q(device_temp_sync_r5[6]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r5_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r4[7]),\n .Q(device_temp_sync_r5[7]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r5_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r4[8]),\n .Q(device_temp_sync_r5[8]),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\device_temp_sync_r5_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(device_temp_sync_r4[9]),\n .Q(device_temp_sync_r5[9]),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair5\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\sync_cntr[0]_i_1 \n (.I0(sync_cntr_reg__0[0]),\n .O(p_0_in__1[0]));\n (* SOFT_HLUTNM = \"soft_lutpair5\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\sync_cntr[1]_i_1 \n (.I0(sync_cntr_reg__0[0]),\n .I1(sync_cntr_reg__0[1]),\n .O(p_0_in__1[1]));\n (* SOFT_HLUTNM = \"soft_lutpair2\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\sync_cntr[2]_i_1 \n (.I0(sync_cntr_reg__0[1]),\n .I1(sync_cntr_reg__0[0]),\n .I2(sync_cntr_reg__0[2]),\n .O(\\sync_cntr[2]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\sync_cntr[3]_i_1 \n (.I0(in0),\n .I1(device_temp_sync_r4_neq_r3),\n .O(sync_cntr0));\n LUT4 #(\n .INIT(16'h7FFF)) \n \\sync_cntr[3]_i_2 \n (.I0(sync_cntr_reg__0[1]),\n .I1(sync_cntr_reg__0[0]),\n .I2(sync_cntr_reg__0[2]),\n .I3(sync_cntr_reg__0[3]),\n .O(\\sync_cntr[3]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair2\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\sync_cntr[3]_i_3 \n (.I0(sync_cntr_reg__0[2]),\n .I1(sync_cntr_reg__0[0]),\n .I2(sync_cntr_reg__0[1]),\n .I3(sync_cntr_reg__0[3]),\n .O(\\sync_cntr[3]_i_3_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\sync_cntr_reg[0] \n (.C(CLK),\n .CE(\\sync_cntr[3]_i_2_n_0 ),\n .D(p_0_in__1[0]),\n .Q(sync_cntr_reg__0[0]),\n .R(sync_cntr0));\n FDRE #(\n .INIT(1'b0)) \n \\sync_cntr_reg[1] \n (.C(CLK),\n .CE(\\sync_cntr[3]_i_2_n_0 ),\n .D(p_0_in__1[1]),\n .Q(sync_cntr_reg__0[1]),\n .R(sync_cntr0));\n FDRE #(\n .INIT(1'b0)) \n \\sync_cntr_reg[2] \n (.C(CLK),\n .CE(\\sync_cntr[3]_i_2_n_0 ),\n .D(\\sync_cntr[2]_i_1_n_0 ),\n .Q(sync_cntr_reg__0[2]),\n .R(sync_cntr0));\n FDRE #(\n .INIT(1'b0)) \n \\sync_cntr_reg[3] \n (.C(CLK),\n .CE(\\sync_cntr[3]_i_2_n_0 ),\n .D(\\sync_cntr[3]_i_3_n_0 ),\n .Q(sync_cntr_reg__0[3]),\n .R(sync_cntr0));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n XADC #(\n .INIT_40(16'h1000),\n .INIT_41(16'h2FFF),\n .INIT_42(16'h0800),\n .INIT_43(16'h0000),\n .INIT_44(16'h0000),\n .INIT_45(16'h0000),\n .INIT_46(16'h0000),\n .INIT_47(16'h0000),\n .INIT_48(16'h0101),\n .INIT_49(16'h0000),\n .INIT_4A(16'h0100),\n .INIT_4B(16'h0000),\n .INIT_4C(16'h0000),\n .INIT_4D(16'h0000),\n .INIT_4E(16'h0000),\n .INIT_4F(16'h0000),\n .INIT_50(16'hB5ED),\n .INIT_51(16'h57E4),\n .INIT_52(16'hA147),\n .INIT_53(16'hCA33),\n .INIT_54(16'hA93A),\n .INIT_55(16'h52C6),\n .INIT_56(16'h9555),\n .INIT_57(16'hAE4E),\n .INIT_58(16'h5999),\n .INIT_59(16'h0000),\n .INIT_5A(16'h0000),\n .INIT_5B(16'h0000),\n .INIT_5C(16'h5111),\n .INIT_5D(16'h0000),\n .INIT_5E(16'h0000),\n .INIT_5F(16'h0000),\n .IS_CONVSTCLK_INVERTED(1'b0),\n .IS_DCLK_INVERTED(1'b0),\n .SIM_DEVICE(\"7SERIES\"),\n .SIM_MONITOR_FILE(\"design.txt\")) \n \\xadc_supplied_temperature.XADC_inst \n (.ALM(\\NLW_xadc_supplied_temperature.XADC_inst_ALM_UNCONNECTED [7:0]),\n .BUSY(\\NLW_xadc_supplied_temperature.XADC_inst_BUSY_UNCONNECTED ),\n .CHANNEL(\\NLW_xadc_supplied_temperature.XADC_inst_CHANNEL_UNCONNECTED [4:0]),\n .CONVST(1'b0),\n .CONVSTCLK(1'b0),\n .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DCLK(mmcm_clk),\n .DEN(xadc_den),\n .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DO(xadc_do),\n .DRDY(xadc_drdy),\n .DWE(1'b0),\n .EOC(\\NLW_xadc_supplied_temperature.XADC_inst_EOC_UNCONNECTED ),\n .EOS(\\NLW_xadc_supplied_temperature.XADC_inst_EOS_UNCONNECTED ),\n .JTAGBUSY(\\NLW_xadc_supplied_temperature.XADC_inst_JTAGBUSY_UNCONNECTED ),\n .JTAGLOCKED(\\NLW_xadc_supplied_temperature.XADC_inst_JTAGLOCKED_UNCONNECTED ),\n .JTAGMODIFIED(\\NLW_xadc_supplied_temperature.XADC_inst_JTAGMODIFIED_UNCONNECTED ),\n .MUXADDR(\\NLW_xadc_supplied_temperature.XADC_inst_MUXADDR_UNCONNECTED [4:0]),\n .OT(\\NLW_xadc_supplied_temperature.XADC_inst_OT_UNCONNECTED ),\n .RESET(1'b0),\n .VAUXN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .VAUXP({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .VN(1'b0),\n .VP(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\xadc_supplied_temperature.rst_r1_reg \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(in0),\n .Q(rst_r1),\n .R(1'b0));\n (* ASYNC_REG *) \n (* KEEP = \"yes\" *) \n FDRE \\xadc_supplied_temperature.rst_r2_reg \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(rst_r1),\n .Q(rst_r2),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h0000020000000000)) \n \\xadc_supplied_temperature.sample_en_i_1 \n (.I0(\\xadc_supplied_temperature.sample_timer_reg__0 [3]),\n .I1(\\xadc_supplied_temperature.sample_timer_reg__0 [4]),\n .I2(\\xadc_supplied_temperature.sample_timer_reg__0 [2]),\n .I3(\\xadc_supplied_temperature.sample_timer_reg__0 [1]),\n .I4(\\xadc_supplied_temperature.sample_timer_reg__0 [0]),\n .I5(\\xadc_supplied_temperature.sample_en_i_2_n_0 ),\n .O(sample_en0));\n LUT6 #(\n .INIT(64'h0080000000000000)) \n \\xadc_supplied_temperature.sample_en_i_2 \n (.I0(\\xadc_supplied_temperature.sample_timer_reg__0 [7]),\n .I1(\\xadc_supplied_temperature.sample_timer_reg__0 [8]),\n .I2(\\xadc_supplied_temperature.sample_timer_reg__0 [6]),\n .I3(\\xadc_supplied_temperature.sample_timer_reg__0 [5]),\n .I4(\\xadc_supplied_temperature.sample_timer_reg__0 [10]),\n .I5(\\xadc_supplied_temperature.sample_timer_reg__0 [9]),\n .O(\\xadc_supplied_temperature.sample_en_i_2_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.sample_en_reg \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(sample_en0),\n .Q(sample_en),\n .R(1'b0));\n LUT1 #(\n .INIT(2'h1)) \n \\xadc_supplied_temperature.sample_timer[0]_i_1 \n (.I0(\\xadc_supplied_temperature.sample_timer_reg__0 [0]),\n .O(\\xadc_supplied_temperature.sample_timer[0]_i_1_n_0 ));\n LUT2 #(\n .INIT(4'hE)) \n \\xadc_supplied_temperature.sample_timer[10]_i_1 \n (.I0(rst_r2),\n .I1(xadc_den),\n .O(sample_timer0));\n LUT6 #(\n .INIT(64'hF7FFFFFF08000000)) \n \\xadc_supplied_temperature.sample_timer[10]_i_2 \n (.I0(\\xadc_supplied_temperature.sample_timer_reg__0 [9]),\n .I1(\\xadc_supplied_temperature.sample_timer_reg__0 [7]),\n .I2(\\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ),\n .I3(\\xadc_supplied_temperature.sample_timer_reg__0 [6]),\n .I4(\\xadc_supplied_temperature.sample_timer_reg__0 [8]),\n .I5(\\xadc_supplied_temperature.sample_timer_reg__0 [10]),\n .O(p_0_in__0[10]));\n LUT6 #(\n .INIT(64'h7FFFFFFFFFFFFFFF)) \n \\xadc_supplied_temperature.sample_timer[10]_i_3 \n (.I0(\\xadc_supplied_temperature.sample_timer_reg__0 [4]),\n .I1(\\xadc_supplied_temperature.sample_timer_reg__0 [2]),\n .I2(\\xadc_supplied_temperature.sample_timer_reg__0 [0]),\n .I3(\\xadc_supplied_temperature.sample_timer_reg__0 [1]),\n .I4(\\xadc_supplied_temperature.sample_timer_reg__0 [3]),\n .I5(\\xadc_supplied_temperature.sample_timer_reg__0 [5]),\n .O(\\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair4\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\xadc_supplied_temperature.sample_timer[1]_i_1 \n (.I0(\\xadc_supplied_temperature.sample_timer_reg__0 [0]),\n .I1(\\xadc_supplied_temperature.sample_timer_reg__0 [1]),\n .O(p_0_in__0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair4\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\xadc_supplied_temperature.sample_timer[2]_i_1 \n (.I0(\\xadc_supplied_temperature.sample_timer_reg__0 [1]),\n .I1(\\xadc_supplied_temperature.sample_timer_reg__0 [0]),\n .I2(\\xadc_supplied_temperature.sample_timer_reg__0 [2]),\n .O(p_0_in__0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair0\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\xadc_supplied_temperature.sample_timer[3]_i_1 \n (.I0(\\xadc_supplied_temperature.sample_timer_reg__0 [2]),\n .I1(\\xadc_supplied_temperature.sample_timer_reg__0 [0]),\n .I2(\\xadc_supplied_temperature.sample_timer_reg__0 [1]),\n .I3(\\xadc_supplied_temperature.sample_timer_reg__0 [3]),\n .O(p_0_in__0[3]));\n (* SOFT_HLUTNM = \"soft_lutpair0\" *) \n LUT5 #(\n .INIT(32'h7FFF8000)) \n \\xadc_supplied_temperature.sample_timer[4]_i_1 \n (.I0(\\xadc_supplied_temperature.sample_timer_reg__0 [3]),\n .I1(\\xadc_supplied_temperature.sample_timer_reg__0 [1]),\n .I2(\\xadc_supplied_temperature.sample_timer_reg__0 [0]),\n .I3(\\xadc_supplied_temperature.sample_timer_reg__0 [2]),\n .I4(\\xadc_supplied_temperature.sample_timer_reg__0 [4]),\n .O(p_0_in__0[4]));\n LUT6 #(\n .INIT(64'h7FFFFFFF80000000)) \n \\xadc_supplied_temperature.sample_timer[5]_i_1 \n (.I0(\\xadc_supplied_temperature.sample_timer_reg__0 [4]),\n .I1(\\xadc_supplied_temperature.sample_timer_reg__0 [2]),\n .I2(\\xadc_supplied_temperature.sample_timer_reg__0 [0]),\n .I3(\\xadc_supplied_temperature.sample_timer_reg__0 [1]),\n .I4(\\xadc_supplied_temperature.sample_timer_reg__0 [3]),\n .I5(\\xadc_supplied_temperature.sample_timer_reg__0 [5]),\n .O(p_0_in__0[5]));\n (* SOFT_HLUTNM = \"soft_lutpair3\" *) \n LUT2 #(\n .INIT(4'h9)) \n \\xadc_supplied_temperature.sample_timer[6]_i_1 \n (.I0(\\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ),\n .I1(\\xadc_supplied_temperature.sample_timer_reg__0 [6]),\n .O(p_0_in__0[6]));\n (* SOFT_HLUTNM = \"soft_lutpair3\" *) \n LUT3 #(\n .INIT(8'hD2)) \n \\xadc_supplied_temperature.sample_timer[7]_i_1 \n (.I0(\\xadc_supplied_temperature.sample_timer_reg__0 [6]),\n .I1(\\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ),\n .I2(\\xadc_supplied_temperature.sample_timer_reg__0 [7]),\n .O(p_0_in__0[7]));\n (* SOFT_HLUTNM = \"soft_lutpair1\" *) \n LUT4 #(\n .INIT(16'hDF20)) \n \\xadc_supplied_temperature.sample_timer[8]_i_1 \n (.I0(\\xadc_supplied_temperature.sample_timer_reg__0 [7]),\n .I1(\\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ),\n .I2(\\xadc_supplied_temperature.sample_timer_reg__0 [6]),\n .I3(\\xadc_supplied_temperature.sample_timer_reg__0 [8]),\n .O(p_0_in__0[8]));\n (* SOFT_HLUTNM = \"soft_lutpair1\" *) \n LUT5 #(\n .INIT(32'hF7FF0800)) \n \\xadc_supplied_temperature.sample_timer[9]_i_1 \n (.I0(\\xadc_supplied_temperature.sample_timer_reg__0 [8]),\n .I1(\\xadc_supplied_temperature.sample_timer_reg__0 [6]),\n .I2(\\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ),\n .I3(\\xadc_supplied_temperature.sample_timer_reg__0 [7]),\n .I4(\\xadc_supplied_temperature.sample_timer_reg__0 [9]),\n .O(p_0_in__0[9]));\n LUT4 #(\n .INIT(16'h000E)) \n \\xadc_supplied_temperature.sample_timer_clr_i_1 \n (.I0(xadc_den),\n .I1(\\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[1] ),\n .I2(\\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2] ),\n .I3(rst_r2),\n .O(\\xadc_supplied_temperature.sample_timer_clr_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.sample_timer_clr_reg \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(\\xadc_supplied_temperature.sample_timer_clr_i_1_n_0 ),\n .Q(xadc_den),\n .R(1'b0));\n LUT5 #(\n .INIT(32'h000000FE)) \n \\xadc_supplied_temperature.sample_timer_en_i_1 \n (.I0(sample_timer_en),\n .I1(\\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ),\n .I2(temperature),\n .I3(\\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[1] ),\n .I4(rst_r2),\n .O(\\xadc_supplied_temperature.sample_timer_en_i_1_n_0 ));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.sample_timer_en_reg \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(\\xadc_supplied_temperature.sample_timer_en_i_1_n_0 ),\n .Q(sample_timer_en),\n .R(1'b0));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.sample_timer_reg[0] \n (.C(mmcm_clk),\n .CE(sample_timer_en),\n .D(\\xadc_supplied_temperature.sample_timer[0]_i_1_n_0 ),\n .Q(\\xadc_supplied_temperature.sample_timer_reg__0 [0]),\n .R(sample_timer0));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.sample_timer_reg[10] \n (.C(mmcm_clk),\n .CE(sample_timer_en),\n .D(p_0_in__0[10]),\n .Q(\\xadc_supplied_temperature.sample_timer_reg__0 [10]),\n .R(sample_timer0));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.sample_timer_reg[1] \n (.C(mmcm_clk),\n .CE(sample_timer_en),\n .D(p_0_in__0[1]),\n .Q(\\xadc_supplied_temperature.sample_timer_reg__0 [1]),\n .R(sample_timer0));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.sample_timer_reg[2] \n (.C(mmcm_clk),\n .CE(sample_timer_en),\n .D(p_0_in__0[2]),\n .Q(\\xadc_supplied_temperature.sample_timer_reg__0 [2]),\n .R(sample_timer0));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.sample_timer_reg[3] \n (.C(mmcm_clk),\n .CE(sample_timer_en),\n .D(p_0_in__0[3]),\n .Q(\\xadc_supplied_temperature.sample_timer_reg__0 [3]),\n .R(sample_timer0));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.sample_timer_reg[4] \n (.C(mmcm_clk),\n .CE(sample_timer_en),\n .D(p_0_in__0[4]),\n .Q(\\xadc_supplied_temperature.sample_timer_reg__0 [4]),\n .R(sample_timer0));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.sample_timer_reg[5] \n (.C(mmcm_clk),\n .CE(sample_timer_en),\n .D(p_0_in__0[5]),\n .Q(\\xadc_supplied_temperature.sample_timer_reg__0 [5]),\n .R(sample_timer0));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.sample_timer_reg[6] \n (.C(mmcm_clk),\n .CE(sample_timer_en),\n .D(p_0_in__0[6]),\n .Q(\\xadc_supplied_temperature.sample_timer_reg__0 [6]),\n .R(sample_timer0));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.sample_timer_reg[7] \n (.C(mmcm_clk),\n .CE(sample_timer_en),\n .D(p_0_in__0[7]),\n .Q(\\xadc_supplied_temperature.sample_timer_reg__0 [7]),\n .R(sample_timer0));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.sample_timer_reg[8] \n (.C(mmcm_clk),\n .CE(sample_timer_en),\n .D(p_0_in__0[8]),\n .Q(\\xadc_supplied_temperature.sample_timer_reg__0 [8]),\n .R(sample_timer0));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.sample_timer_reg[9] \n (.C(mmcm_clk),\n .CE(sample_timer_en),\n .D(p_0_in__0[9]),\n .Q(\\xadc_supplied_temperature.sample_timer_reg__0 [9]),\n .R(sample_timer0));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.temperature_reg[0] \n (.C(mmcm_clk),\n .CE(temperature),\n .D(p_0_in[0]),\n .Q(device_temp_lcl[0]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.temperature_reg[10] \n (.C(mmcm_clk),\n .CE(temperature),\n .D(p_0_in[10]),\n .Q(device_temp_lcl[10]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.temperature_reg[11] \n (.C(mmcm_clk),\n .CE(temperature),\n .D(p_0_in[11]),\n .Q(device_temp_lcl[11]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.temperature_reg[1] \n (.C(mmcm_clk),\n .CE(temperature),\n .D(p_0_in[1]),\n .Q(device_temp_lcl[1]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.temperature_reg[2] \n (.C(mmcm_clk),\n .CE(temperature),\n .D(p_0_in[2]),\n .Q(device_temp_lcl[2]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.temperature_reg[3] \n (.C(mmcm_clk),\n .CE(temperature),\n .D(p_0_in[3]),\n .Q(device_temp_lcl[3]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.temperature_reg[4] \n (.C(mmcm_clk),\n .CE(temperature),\n .D(p_0_in[4]),\n .Q(device_temp_lcl[4]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.temperature_reg[5] \n (.C(mmcm_clk),\n .CE(temperature),\n .D(p_0_in[5]),\n .Q(device_temp_lcl[5]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.temperature_reg[6] \n (.C(mmcm_clk),\n .CE(temperature),\n .D(p_0_in[6]),\n .Q(device_temp_lcl[6]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.temperature_reg[7] \n (.C(mmcm_clk),\n .CE(temperature),\n .D(p_0_in[7]),\n .Q(device_temp_lcl[7]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.temperature_reg[8] \n (.C(mmcm_clk),\n .CE(temperature),\n .D(p_0_in[8]),\n .Q(device_temp_lcl[8]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.temperature_reg[9] \n (.C(mmcm_clk),\n .CE(temperature),\n .D(p_0_in[9]),\n .Q(device_temp_lcl[9]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.xadc_do_r_reg[10] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(xadc_do[10]),\n .Q(p_0_in[6]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.xadc_do_r_reg[11] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(xadc_do[11]),\n .Q(p_0_in[7]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.xadc_do_r_reg[12] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(xadc_do[12]),\n .Q(p_0_in[8]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.xadc_do_r_reg[13] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(xadc_do[13]),\n .Q(p_0_in[9]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.xadc_do_r_reg[14] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(xadc_do[14]),\n .Q(p_0_in[10]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.xadc_do_r_reg[15] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(xadc_do[15]),\n .Q(p_0_in[11]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.xadc_do_r_reg[4] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(xadc_do[4]),\n .Q(p_0_in[0]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.xadc_do_r_reg[5] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(xadc_do[5]),\n .Q(p_0_in[1]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.xadc_do_r_reg[6] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(xadc_do[6]),\n .Q(p_0_in[2]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.xadc_do_r_reg[7] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(xadc_do[7]),\n .Q(p_0_in[3]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.xadc_do_r_reg[8] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(xadc_do[8]),\n .Q(p_0_in[4]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.xadc_do_r_reg[9] \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(xadc_do[9]),\n .Q(p_0_in[5]),\n .R(rst_r2));\n FDRE #(\n .INIT(1'b0)) \n \\xadc_supplied_temperature.xadc_drdy_r_reg \n (.C(mmcm_clk),\n .CE(1'b1),\n .D(xadc_drdy),\n .Q(xadc_drdy_r),\n .R(rst_r2));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_ui_cmd\n (E,\n app_en_r1,\n app_hi_pri_r2,\n hi_priority,\n \\app_cmd_r2_reg[0]_0 ,\n rb_hit_busy_r_reg,\n \\req_bank_r_lcl_reg[0] ,\n \\req_bank_r_lcl_reg[1] ,\n \\req_bank_r_lcl_reg[2] ,\n rb_hit_busy_r_reg_0,\n rb_hit_busy_r_reg_1,\n rb_hit_busy_r_reg_2,\n \\wr_req_counter.wr_req_cnt_r_reg[4] ,\n \\wr_req_counter.wr_req_cnt_r_reg[3] ,\n wr_accepted,\n \\not_strict_mode.occupied_counter.occ_cnt_r_reg[3] ,\n rd_accepted,\n use_addr,\n \\req_data_buf_addr_r_reg[4] ,\n \\app_cmd_r2_reg[1]_0 ,\n \\req_row_r_lcl_reg[14] ,\n \\req_col_r_reg[9] ,\n app_rdy_ns,\n CLK,\n app_en_ns1,\n mc_app_cmd,\n req_bank_r,\n reset_reg,\n p_0_in,\n wr_req_cnt_r,\n Q,\n wr_data_buf_addr,\n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ,\n app_rdy_r_reg_0,\n \\axaddr_incr_reg[29] );\n output [0:0]E;\n output app_en_r1;\n output app_hi_pri_r2;\n output hi_priority;\n output \\app_cmd_r2_reg[0]_0 ;\n output rb_hit_busy_r_reg;\n output \\req_bank_r_lcl_reg[0] ;\n output \\req_bank_r_lcl_reg[1] ;\n output \\req_bank_r_lcl_reg[2] ;\n output rb_hit_busy_r_reg_0;\n output rb_hit_busy_r_reg_1;\n output rb_hit_busy_r_reg_2;\n output \\wr_req_counter.wr_req_cnt_r_reg[4] ;\n output \\wr_req_counter.wr_req_cnt_r_reg[3] ;\n output wr_accepted;\n output \\not_strict_mode.occupied_counter.occ_cnt_r_reg[3] ;\n output rd_accepted;\n output use_addr;\n output [4:0]\\req_data_buf_addr_r_reg[4] ;\n output [0:0]\\app_cmd_r2_reg[1]_0 ;\n output [14:0]\\req_row_r_lcl_reg[14] ;\n output [6:0]\\req_col_r_reg[9] ;\n input app_rdy_ns;\n input CLK;\n input app_en_ns1;\n input [0:0]mc_app_cmd;\n input [11:0]req_bank_r;\n input reset_reg;\n input [0:0]p_0_in;\n input [1:0]wr_req_cnt_r;\n input [1:0]Q;\n input [3:0]wr_data_buf_addr;\n input [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n input [0:0]app_rdy_r_reg_0;\n input [24:0]\\axaddr_incr_reg[29] ;\n\n wire CLK;\n wire [0:0]E;\n wire [1:0]Q;\n wire \\app_addr_r1_reg_n_0_[13] ;\n wire \\app_addr_r1_reg_n_0_[14] ;\n wire \\app_addr_r1_reg_n_0_[15] ;\n wire \\app_addr_r1_reg_n_0_[16] ;\n wire \\app_addr_r1_reg_n_0_[17] ;\n wire \\app_addr_r1_reg_n_0_[18] ;\n wire \\app_addr_r1_reg_n_0_[19] ;\n wire \\app_addr_r1_reg_n_0_[20] ;\n wire \\app_addr_r1_reg_n_0_[21] ;\n wire \\app_addr_r1_reg_n_0_[22] ;\n wire \\app_addr_r1_reg_n_0_[23] ;\n wire \\app_addr_r1_reg_n_0_[24] ;\n wire \\app_addr_r1_reg_n_0_[25] ;\n wire \\app_addr_r1_reg_n_0_[26] ;\n wire \\app_addr_r1_reg_n_0_[27] ;\n wire \\app_addr_r1_reg_n_0_[3] ;\n wire \\app_addr_r1_reg_n_0_[4] ;\n wire \\app_addr_r1_reg_n_0_[5] ;\n wire \\app_addr_r1_reg_n_0_[6] ;\n wire \\app_addr_r1_reg_n_0_[7] ;\n wire \\app_addr_r1_reg_n_0_[8] ;\n wire \\app_addr_r1_reg_n_0_[9] ;\n wire \\app_addr_r2_reg_n_0_[13] ;\n wire \\app_addr_r2_reg_n_0_[14] ;\n wire \\app_addr_r2_reg_n_0_[15] ;\n wire \\app_addr_r2_reg_n_0_[16] ;\n wire \\app_addr_r2_reg_n_0_[17] ;\n wire \\app_addr_r2_reg_n_0_[18] ;\n wire \\app_addr_r2_reg_n_0_[19] ;\n wire \\app_addr_r2_reg_n_0_[20] ;\n wire \\app_addr_r2_reg_n_0_[21] ;\n wire \\app_addr_r2_reg_n_0_[22] ;\n wire \\app_addr_r2_reg_n_0_[23] ;\n wire \\app_addr_r2_reg_n_0_[24] ;\n wire \\app_addr_r2_reg_n_0_[25] ;\n wire \\app_addr_r2_reg_n_0_[26] ;\n wire \\app_addr_r2_reg_n_0_[27] ;\n wire \\app_addr_r2_reg_n_0_[3] ;\n wire \\app_addr_r2_reg_n_0_[4] ;\n wire \\app_addr_r2_reg_n_0_[5] ;\n wire \\app_addr_r2_reg_n_0_[6] ;\n wire \\app_addr_r2_reg_n_0_[7] ;\n wire \\app_addr_r2_reg_n_0_[8] ;\n wire \\app_addr_r2_reg_n_0_[9] ;\n wire [0:0]app_cmd_r1;\n wire \\app_cmd_r1[0]_i_1_n_0 ;\n wire [1:0]app_cmd_r2;\n wire \\app_cmd_r2_reg[0]_0 ;\n wire [0:0]\\app_cmd_r2_reg[1]_0 ;\n wire app_en_ns1;\n wire app_en_ns2;\n wire app_en_r1;\n wire app_en_r2;\n wire app_hi_pri_r2;\n wire app_rdy_ns;\n wire [0:0]app_rdy_r_reg_0;\n wire [24:0]\\axaddr_incr_reg[29] ;\n wire hi_priority;\n wire [0:0]mc_app_cmd;\n wire [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;\n wire \\not_strict_mode.occupied_counter.occ_cnt_r_reg[3] ;\n wire [0:0]p_0_in;\n wire [2:0]p_0_in_0;\n wire [2:0]p_1_in;\n wire rb_hit_busy_r_reg;\n wire rb_hit_busy_r_reg_0;\n wire rb_hit_busy_r_reg_1;\n wire rb_hit_busy_r_reg_2;\n wire rd_accepted;\n wire [11:0]req_bank_r;\n wire \\req_bank_r_lcl_reg[0] ;\n wire \\req_bank_r_lcl_reg[1] ;\n wire \\req_bank_r_lcl_reg[2] ;\n wire [6:0]\\req_col_r_reg[9] ;\n wire [4:0]\\req_data_buf_addr_r_reg[4] ;\n wire [14:0]\\req_row_r_lcl_reg[14] ;\n wire reset_reg;\n wire use_addr;\n wire wr_accepted;\n wire [3:0]wr_data_buf_addr;\n wire [1:0]wr_req_cnt_r;\n wire \\wr_req_counter.wr_req_cnt_r_reg[3] ;\n wire \\wr_req_counter.wr_req_cnt_r_reg[4] ;\n\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[10] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [7]),\n .Q(p_1_in[0]),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[11] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [8]),\n .Q(p_1_in[1]),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[12] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [9]),\n .Q(p_1_in[2]),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[13] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [10]),\n .Q(\\app_addr_r1_reg_n_0_[13] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[14] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [11]),\n .Q(\\app_addr_r1_reg_n_0_[14] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[15] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [12]),\n .Q(\\app_addr_r1_reg_n_0_[15] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[16] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [13]),\n .Q(\\app_addr_r1_reg_n_0_[16] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[17] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [14]),\n .Q(\\app_addr_r1_reg_n_0_[17] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[18] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [15]),\n .Q(\\app_addr_r1_reg_n_0_[18] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[19] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [16]),\n .Q(\\app_addr_r1_reg_n_0_[19] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[20] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [17]),\n .Q(\\app_addr_r1_reg_n_0_[20] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[21] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [18]),\n .Q(\\app_addr_r1_reg_n_0_[21] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[22] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [19]),\n .Q(\\app_addr_r1_reg_n_0_[22] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[23] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [20]),\n .Q(\\app_addr_r1_reg_n_0_[23] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[24] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [21]),\n .Q(\\app_addr_r1_reg_n_0_[24] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[25] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [22]),\n .Q(\\app_addr_r1_reg_n_0_[25] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[26] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [23]),\n .Q(\\app_addr_r1_reg_n_0_[26] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[27] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [24]),\n .Q(\\app_addr_r1_reg_n_0_[27] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[3] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [0]),\n .Q(\\app_addr_r1_reg_n_0_[3] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[4] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [1]),\n .Q(\\app_addr_r1_reg_n_0_[4] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[5] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [2]),\n .Q(\\app_addr_r1_reg_n_0_[5] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[6] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [3]),\n .Q(\\app_addr_r1_reg_n_0_[6] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[7] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [4]),\n .Q(\\app_addr_r1_reg_n_0_[7] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[8] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [5]),\n .Q(\\app_addr_r1_reg_n_0_[8] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r1_reg[9] \n (.C(CLK),\n .CE(app_rdy_r_reg_0),\n .D(\\axaddr_incr_reg[29] [6]),\n .Q(\\app_addr_r1_reg_n_0_[9] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[10] \n (.C(CLK),\n .CE(E),\n .D(p_1_in[0]),\n .Q(p_0_in_0[0]),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[11] \n (.C(CLK),\n .CE(E),\n .D(p_1_in[1]),\n .Q(p_0_in_0[1]),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[12] \n (.C(CLK),\n .CE(E),\n .D(p_1_in[2]),\n .Q(p_0_in_0[2]),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[13] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[13] ),\n .Q(\\app_addr_r2_reg_n_0_[13] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[14] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[14] ),\n .Q(\\app_addr_r2_reg_n_0_[14] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[15] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[15] ),\n .Q(\\app_addr_r2_reg_n_0_[15] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[16] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[16] ),\n .Q(\\app_addr_r2_reg_n_0_[16] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[17] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[17] ),\n .Q(\\app_addr_r2_reg_n_0_[17] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[18] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[18] ),\n .Q(\\app_addr_r2_reg_n_0_[18] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[19] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[19] ),\n .Q(\\app_addr_r2_reg_n_0_[19] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[20] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[20] ),\n .Q(\\app_addr_r2_reg_n_0_[20] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[21] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[21] ),\n .Q(\\app_addr_r2_reg_n_0_[21] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[22] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[22] ),\n .Q(\\app_addr_r2_reg_n_0_[22] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[23] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[23] ),\n .Q(\\app_addr_r2_reg_n_0_[23] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[24] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[24] ),\n .Q(\\app_addr_r2_reg_n_0_[24] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[25] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[25] ),\n .Q(\\app_addr_r2_reg_n_0_[25] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[26] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[26] ),\n .Q(\\app_addr_r2_reg_n_0_[26] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[27] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[27] ),\n .Q(\\app_addr_r2_reg_n_0_[27] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[3] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[3] ),\n .Q(\\app_addr_r2_reg_n_0_[3] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[4] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[4] ),\n .Q(\\app_addr_r2_reg_n_0_[4] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[5] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[5] ),\n .Q(\\app_addr_r2_reg_n_0_[5] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[6] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[6] ),\n .Q(\\app_addr_r2_reg_n_0_[6] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[7] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[7] ),\n .Q(\\app_addr_r2_reg_n_0_[7] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[8] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[8] ),\n .Q(\\app_addr_r2_reg_n_0_[8] ),\n .R(reset_reg));\n FDRE #(\n .INIT(1'b0)) \n \\app_addr_r2_reg[9] \n (.C(CLK),\n .CE(E),\n .D(\\app_addr_r1_reg_n_0_[9] ),\n .Q(\\app_addr_r2_reg_n_0_[9] ),\n .R(reset_reg));\n (* SOFT_HLUTNM = \"soft_lutpair1498\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\app_cmd_r1[0]_i_1 \n (.I0(mc_app_cmd),\n .I1(E),\n .I2(app_cmd_r1),\n .O(\\app_cmd_r1[0]_i_1_n_0 ));\n FDRE \\app_cmd_r1_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\app_cmd_r1[0]_i_1_n_0 ),\n .Q(app_cmd_r1),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1489\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\app_cmd_r2[1]_i_1 \n (.I0(app_cmd_r2[1]),\n .I1(E),\n .O(\\app_cmd_r2_reg[1]_0 ));\n FDRE \\app_cmd_r2_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\app_cmd_r2_reg[0]_0 ),\n .Q(app_cmd_r2[0]),\n .R(1'b0));\n FDRE \\app_cmd_r2_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\app_cmd_r2_reg[1]_0 ),\n .Q(app_cmd_r2[1]),\n .R(1'b0));\n FDRE app_en_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(app_en_ns1),\n .Q(app_en_r1),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1490\" *) \n LUT4 #(\n .INIT(16'h2230)) \n app_en_r2_i_1\n (.I0(app_en_r1),\n .I1(reset_reg),\n .I2(app_en_r2),\n .I3(E),\n .O(app_en_ns2));\n FDRE app_en_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(app_en_ns2),\n .Q(app_en_r2),\n .R(1'b0));\n FDRE app_hi_pri_r2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(hi_priority),\n .Q(app_hi_pri_r2),\n .R(1'b0));\n (* syn_maxfan = \"10\" *) \n FDRE #(\n .INIT(1'b0)) \n app_rdy_r_reg\n (.C(CLK),\n .CE(1'b1),\n .D(app_rdy_ns),\n .Q(E),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1487\" *) \n LUT4 #(\n .INIT(16'h8008)) \n \\data_buf_address_counter.data_buf_addr_cnt_r[3]_i_1 \n (.I0(E),\n .I1(app_en_r2),\n .I2(app_cmd_r2[0]),\n .I3(app_cmd_r2[1]),\n .O(wr_accepted));\n (* SOFT_HLUTNM = \"soft_lutpair1487\" *) \n LUT2 #(\n .INIT(4'h8)) \n i___48_i_1\n (.I0(app_en_r2),\n .I1(E),\n .O(use_addr));\n (* SOFT_HLUTNM = \"soft_lutpair1498\" *) \n LUT3 #(\n .INIT(8'hB8)) \n i___69_i_1\n (.I0(app_cmd_r1),\n .I1(E),\n .I2(app_cmd_r2[0]),\n .O(\\app_cmd_r2_reg[0]_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1486\" *) \n LUT4 #(\n .INIT(16'h4000)) \n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[4]_i_1 \n (.I0(app_cmd_r2[1]),\n .I1(app_cmd_r2[0]),\n .I2(E),\n .I3(app_en_r2),\n .O(rd_accepted));\n LUT6 #(\n .INIT(64'h7555555510000000)) \n \\not_strict_mode.occupied_counter.occ_cnt_r[3]_i_2 \n (.I0(Q[1]),\n .I1(app_cmd_r2[1]),\n .I2(app_cmd_r2[0]),\n .I3(E),\n .I4(app_en_r2),\n .I5(Q[0]),\n .O(\\not_strict_mode.occupied_counter.occ_cnt_r_reg[3] ));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\rb_hit_busies.rb_hit_busies_r_lcl[1]_i_2 \n (.I0(\\req_bank_r_lcl_reg[2] ),\n .I1(req_bank_r[5]),\n .I2(req_bank_r[4]),\n .I3(\\req_bank_r_lcl_reg[1] ),\n .I4(req_bank_r[3]),\n .I5(\\req_bank_r_lcl_reg[0] ),\n .O(rb_hit_busy_r_reg_0));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\rb_hit_busies.rb_hit_busies_r_lcl[2]_i_2 \n (.I0(\\req_bank_r_lcl_reg[2] ),\n .I1(req_bank_r[8]),\n .I2(req_bank_r[7]),\n .I3(\\req_bank_r_lcl_reg[1] ),\n .I4(req_bank_r[6]),\n .I5(\\req_bank_r_lcl_reg[0] ),\n .O(rb_hit_busy_r_reg_1));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n \\rb_hit_busies.rb_hit_busies_r_lcl[3]_i_2 \n (.I0(\\req_bank_r_lcl_reg[0] ),\n .I1(req_bank_r[9]),\n .I2(req_bank_r[10]),\n .I3(\\req_bank_r_lcl_reg[1] ),\n .I4(req_bank_r[11]),\n .I5(\\req_bank_r_lcl_reg[2] ),\n .O(rb_hit_busy_r_reg_2));\n LUT6 #(\n .INIT(64'h6FF6FFFFFFFF6FF6)) \n rb_hit_busy_r_i_2\n (.I0(\\req_bank_r_lcl_reg[0] ),\n .I1(req_bank_r[0]),\n .I2(req_bank_r[1]),\n .I3(\\req_bank_r_lcl_reg[1] ),\n .I4(req_bank_r[2]),\n .I5(\\req_bank_r_lcl_reg[2] ),\n .O(rb_hit_busy_r_reg));\n (* SOFT_HLUTNM = \"soft_lutpair1500\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_bank_r_lcl[0]_i_1 \n (.I0(p_1_in[0]),\n .I1(E),\n .I2(p_0_in_0[0]),\n .O(\\req_bank_r_lcl_reg[0] ));\n (* SOFT_HLUTNM = \"soft_lutpair1500\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_bank_r_lcl[1]_i_1 \n (.I0(p_1_in[1]),\n .I1(E),\n .I2(p_0_in_0[1]),\n .O(\\req_bank_r_lcl_reg[1] ));\n (* SOFT_HLUTNM = \"soft_lutpair1499\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_bank_r_lcl[2]_i_1 \n (.I0(p_1_in[2]),\n .I1(E),\n .I2(p_0_in_0[2]),\n .O(\\req_bank_r_lcl_reg[2] ));\n (* SOFT_HLUTNM = \"soft_lutpair1501\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_col_r[3]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[3] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[3] ),\n .O(\\req_col_r_reg[9] [0]));\n LUT3 #(\n .INIT(8'hB8)) \n \\req_col_r[4]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[4] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[4] ),\n .O(\\req_col_r_reg[9] [1]));\n (* SOFT_HLUTNM = \"soft_lutpair1503\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_col_r[5]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[5] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[5] ),\n .O(\\req_col_r_reg[9] [2]));\n (* SOFT_HLUTNM = \"soft_lutpair1503\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_col_r[6]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[6] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[6] ),\n .O(\\req_col_r_reg[9] [3]));\n (* SOFT_HLUTNM = \"soft_lutpair1502\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_col_r[7]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[7] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[7] ),\n .O(\\req_col_r_reg[9] [4]));\n (* SOFT_HLUTNM = \"soft_lutpair1502\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_col_r[8]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[8] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[8] ),\n .O(\\req_col_r_reg[9] [5]));\n (* SOFT_HLUTNM = \"soft_lutpair1501\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_col_r[9]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[9] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[9] ),\n .O(\\req_col_r_reg[9] [6]));\n LUT4 #(\n .INIT(16'hBE82)) \n \\req_data_buf_addr_r[0]_i_1 \n (.I0(wr_data_buf_addr[0]),\n .I1(app_cmd_r2[1]),\n .I2(app_cmd_r2[0]),\n .I3(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [0]),\n .O(\\req_data_buf_addr_r_reg[4] [0]));\n (* SOFT_HLUTNM = \"soft_lutpair1488\" *) \n LUT4 #(\n .INIT(16'hBE82)) \n \\req_data_buf_addr_r[1]_i_1 \n (.I0(wr_data_buf_addr[1]),\n .I1(app_cmd_r2[1]),\n .I2(app_cmd_r2[0]),\n .I3(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [1]),\n .O(\\req_data_buf_addr_r_reg[4] [1]));\n (* SOFT_HLUTNM = \"soft_lutpair1489\" *) \n LUT4 #(\n .INIT(16'hBE82)) \n \\req_data_buf_addr_r[2]_i_1 \n (.I0(wr_data_buf_addr[2]),\n .I1(app_cmd_r2[1]),\n .I2(app_cmd_r2[0]),\n .I3(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [2]),\n .O(\\req_data_buf_addr_r_reg[4] [2]));\n LUT4 #(\n .INIT(16'hBE82)) \n \\req_data_buf_addr_r[3]_i_1 \n (.I0(wr_data_buf_addr[3]),\n .I1(app_cmd_r2[1]),\n .I2(app_cmd_r2[0]),\n .I3(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [3]),\n .O(\\req_data_buf_addr_r_reg[4] [3]));\n (* SOFT_HLUTNM = \"soft_lutpair1488\" *) \n LUT3 #(\n .INIT(8'h28)) \n \\req_data_buf_addr_r[4]_i_1 \n (.I0(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] [4]),\n .I1(app_cmd_r2[0]),\n .I2(app_cmd_r2[1]),\n .O(\\req_data_buf_addr_r_reg[4] [4]));\n (* SOFT_HLUTNM = \"soft_lutpair1490\" *) \n LUT2 #(\n .INIT(4'h2)) \n req_priority_r_i_1\n (.I0(app_hi_pri_r2),\n .I1(E),\n .O(hi_priority));\n (* SOFT_HLUTNM = \"soft_lutpair1496\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_row_r_lcl[0]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[13] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[13] ),\n .O(\\req_row_r_lcl_reg[14] [0]));\n (* SOFT_HLUTNM = \"soft_lutpair1491\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_row_r_lcl[10]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[23] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[23] ),\n .O(\\req_row_r_lcl_reg[14] [10]));\n (* SOFT_HLUTNM = \"soft_lutpair1499\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_row_r_lcl[11]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[24] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[24] ),\n .O(\\req_row_r_lcl_reg[14] [11]));\n (* SOFT_HLUTNM = \"soft_lutpair1497\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_row_r_lcl[12]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[25] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[25] ),\n .O(\\req_row_r_lcl_reg[14] [12]));\n (* SOFT_HLUTNM = \"soft_lutpair1495\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_row_r_lcl[13]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[26] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[26] ),\n .O(\\req_row_r_lcl_reg[14] [13]));\n (* SOFT_HLUTNM = \"soft_lutpair1493\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_row_r_lcl[14]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[27] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[27] ),\n .O(\\req_row_r_lcl_reg[14] [14]));\n (* SOFT_HLUTNM = \"soft_lutpair1495\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_row_r_lcl[1]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[14] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[14] ),\n .O(\\req_row_r_lcl_reg[14] [1]));\n (* SOFT_HLUTNM = \"soft_lutpair1494\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_row_r_lcl[2]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[15] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[15] ),\n .O(\\req_row_r_lcl_reg[14] [2]));\n (* SOFT_HLUTNM = \"soft_lutpair1493\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_row_r_lcl[3]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[16] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[16] ),\n .O(\\req_row_r_lcl_reg[14] [3]));\n (* SOFT_HLUTNM = \"soft_lutpair1492\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_row_r_lcl[4]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[17] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[17] ),\n .O(\\req_row_r_lcl_reg[14] [4]));\n (* SOFT_HLUTNM = \"soft_lutpair1491\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_row_r_lcl[5]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[18] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[18] ),\n .O(\\req_row_r_lcl_reg[14] [5]));\n (* SOFT_HLUTNM = \"soft_lutpair1497\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_row_r_lcl[6]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[19] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[19] ),\n .O(\\req_row_r_lcl_reg[14] [6]));\n (* SOFT_HLUTNM = \"soft_lutpair1496\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_row_r_lcl[7]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[20] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[20] ),\n .O(\\req_row_r_lcl_reg[14] [7]));\n (* SOFT_HLUTNM = \"soft_lutpair1494\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_row_r_lcl[8]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[21] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[21] ),\n .O(\\req_row_r_lcl_reg[14] [8]));\n (* SOFT_HLUTNM = \"soft_lutpair1492\" *) \n LUT3 #(\n .INIT(8'hB8)) \n \\req_row_r_lcl[9]_i_1 \n (.I0(\\app_addr_r1_reg_n_0_[22] ),\n .I1(E),\n .I2(\\app_addr_r2_reg_n_0_[22] ),\n .O(\\req_row_r_lcl_reg[14] [9]));\n LUT6 #(\n .INIT(64'hD55555D540000040)) \n \\wr_req_counter.wr_req_cnt_r[3]_i_2 \n (.I0(wr_req_cnt_r[1]),\n .I1(E),\n .I2(app_en_r2),\n .I3(app_cmd_r2[0]),\n .I4(app_cmd_r2[1]),\n .I5(wr_req_cnt_r[0]),\n .O(\\wr_req_counter.wr_req_cnt_r_reg[3] ));\n (* SOFT_HLUTNM = \"soft_lutpair1486\" *) \n LUT5 #(\n .INIT(32'h96555555)) \n \\wr_req_counter.wr_req_cnt_r[3]_i_3 \n (.I0(p_0_in),\n .I1(app_cmd_r2[1]),\n .I2(app_cmd_r2[0]),\n .I3(app_en_r2),\n .I4(E),\n .O(\\wr_req_counter.wr_req_cnt_r_reg[4] ));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_ui_rd_data\n (\\not_strict_mode.app_rd_data_end_reg_0 ,\n Q,\n DOA,\n DOB,\n DOC,\n \\not_strict_mode.app_rd_data_reg[11]_0 ,\n \\not_strict_mode.app_rd_data_reg[9]_0 ,\n \\not_strict_mode.app_rd_data_reg[7]_0 ,\n \\not_strict_mode.app_rd_data_reg[17]_0 ,\n \\not_strict_mode.app_rd_data_reg[15]_0 ,\n \\not_strict_mode.app_rd_data_reg[13]_0 ,\n \\not_strict_mode.app_rd_data_reg[23]_0 ,\n \\not_strict_mode.app_rd_data_reg[21]_0 ,\n \\not_strict_mode.app_rd_data_reg[19]_0 ,\n \\not_strict_mode.app_rd_data_reg[29]_0 ,\n \\not_strict_mode.app_rd_data_reg[27]_0 ,\n \\not_strict_mode.app_rd_data_reg[25]_0 ,\n \\not_strict_mode.app_rd_data_reg[35]_0 ,\n \\not_strict_mode.app_rd_data_reg[33]_0 ,\n \\not_strict_mode.app_rd_data_reg[31]_0 ,\n \\not_strict_mode.app_rd_data_reg[41]_0 ,\n \\not_strict_mode.app_rd_data_reg[39]_0 ,\n \\not_strict_mode.app_rd_data_reg[37]_0 ,\n \\not_strict_mode.app_rd_data_reg[47]_0 ,\n \\not_strict_mode.app_rd_data_reg[45]_0 ,\n \\not_strict_mode.app_rd_data_reg[43]_0 ,\n \\not_strict_mode.app_rd_data_reg[53]_0 ,\n \\not_strict_mode.app_rd_data_reg[51]_0 ,\n \\not_strict_mode.app_rd_data_reg[49]_0 ,\n \\not_strict_mode.app_rd_data_reg[59]_0 ,\n \\not_strict_mode.app_rd_data_reg[57]_0 ,\n \\not_strict_mode.app_rd_data_reg[55]_0 ,\n \\not_strict_mode.app_rd_data_reg[65]_0 ,\n \\not_strict_mode.app_rd_data_reg[63]_0 ,\n \\not_strict_mode.app_rd_data_reg[61]_0 ,\n \\not_strict_mode.app_rd_data_reg[71]_0 ,\n \\not_strict_mode.app_rd_data_reg[69]_0 ,\n \\not_strict_mode.app_rd_data_reg[67]_0 ,\n \\not_strict_mode.app_rd_data_reg[77]_0 ,\n \\not_strict_mode.app_rd_data_reg[75]_0 ,\n \\not_strict_mode.app_rd_data_reg[73]_0 ,\n \\not_strict_mode.app_rd_data_reg[83]_0 ,\n \\not_strict_mode.app_rd_data_reg[81]_0 ,\n \\not_strict_mode.app_rd_data_reg[79]_0 ,\n \\not_strict_mode.app_rd_data_reg[89]_0 ,\n \\not_strict_mode.app_rd_data_reg[87]_0 ,\n \\not_strict_mode.app_rd_data_reg[85]_0 ,\n \\not_strict_mode.app_rd_data_reg[95]_0 ,\n \\not_strict_mode.app_rd_data_reg[93]_0 ,\n \\not_strict_mode.app_rd_data_reg[91]_0 ,\n \\not_strict_mode.app_rd_data_reg[101]_0 ,\n \\not_strict_mode.app_rd_data_reg[99]_0 ,\n \\not_strict_mode.app_rd_data_reg[97]_0 ,\n \\not_strict_mode.app_rd_data_reg[107]_0 ,\n \\not_strict_mode.app_rd_data_reg[105]_0 ,\n \\not_strict_mode.app_rd_data_reg[103]_0 ,\n \\not_strict_mode.app_rd_data_reg[113]_0 ,\n \\not_strict_mode.app_rd_data_reg[111]_0 ,\n \\not_strict_mode.app_rd_data_reg[109]_0 ,\n \\not_strict_mode.app_rd_data_reg[119]_0 ,\n \\not_strict_mode.app_rd_data_reg[117]_0 ,\n \\not_strict_mode.app_rd_data_reg[115]_0 ,\n \\not_strict_mode.app_rd_data_reg[125]_0 ,\n \\not_strict_mode.app_rd_data_reg[123]_0 ,\n \\not_strict_mode.app_rd_data_reg[121]_0 ,\n \\not_strict_mode.app_rd_data_reg[131]_0 ,\n \\not_strict_mode.app_rd_data_reg[129]_0 ,\n \\not_strict_mode.app_rd_data_reg[127]_0 ,\n \\not_strict_mode.app_rd_data_reg[137]_0 ,\n \\not_strict_mode.app_rd_data_reg[135]_0 ,\n \\not_strict_mode.app_rd_data_reg[133]_0 ,\n \\not_strict_mode.app_rd_data_reg[143]_0 ,\n \\not_strict_mode.app_rd_data_reg[141]_0 ,\n \\not_strict_mode.app_rd_data_reg[139]_0 ,\n \\not_strict_mode.app_rd_data_reg[149]_0 ,\n \\not_strict_mode.app_rd_data_reg[147]_0 ,\n \\not_strict_mode.app_rd_data_reg[145]_0 ,\n \\not_strict_mode.app_rd_data_reg[155]_0 ,\n \\not_strict_mode.app_rd_data_reg[153]_0 ,\n \\not_strict_mode.app_rd_data_reg[151]_0 ,\n \\not_strict_mode.app_rd_data_reg[161]_0 ,\n \\not_strict_mode.app_rd_data_reg[159]_0 ,\n \\not_strict_mode.app_rd_data_reg[157]_0 ,\n \\not_strict_mode.app_rd_data_reg[167]_0 ,\n \\not_strict_mode.app_rd_data_reg[165]_0 ,\n \\not_strict_mode.app_rd_data_reg[163]_0 ,\n \\not_strict_mode.app_rd_data_reg[173]_0 ,\n \\not_strict_mode.app_rd_data_reg[171]_0 ,\n \\not_strict_mode.app_rd_data_reg[169]_0 ,\n \\not_strict_mode.app_rd_data_reg[179]_0 ,\n \\not_strict_mode.app_rd_data_reg[177]_0 ,\n \\not_strict_mode.app_rd_data_reg[175]_0 ,\n \\not_strict_mode.app_rd_data_reg[185]_0 ,\n \\not_strict_mode.app_rd_data_reg[183]_0 ,\n \\not_strict_mode.app_rd_data_reg[181]_0 ,\n \\not_strict_mode.app_rd_data_reg[191]_0 ,\n \\not_strict_mode.app_rd_data_reg[189]_0 ,\n \\not_strict_mode.app_rd_data_reg[187]_0 ,\n \\not_strict_mode.app_rd_data_reg[197]_0 ,\n \\not_strict_mode.app_rd_data_reg[195]_0 ,\n \\not_strict_mode.app_rd_data_reg[193]_0 ,\n \\not_strict_mode.app_rd_data_reg[203]_0 ,\n \\not_strict_mode.app_rd_data_reg[201]_0 ,\n \\not_strict_mode.app_rd_data_reg[199]_0 ,\n \\not_strict_mode.app_rd_data_reg[209]_0 ,\n \\not_strict_mode.app_rd_data_reg[207]_0 ,\n \\not_strict_mode.app_rd_data_reg[205]_0 ,\n \\not_strict_mode.app_rd_data_reg[215]_0 ,\n \\not_strict_mode.app_rd_data_reg[213]_0 ,\n \\not_strict_mode.app_rd_data_reg[211]_0 ,\n \\not_strict_mode.app_rd_data_reg[221]_0 ,\n \\not_strict_mode.app_rd_data_reg[219]_0 ,\n \\not_strict_mode.app_rd_data_reg[217]_0 ,\n \\not_strict_mode.app_rd_data_reg[227]_0 ,\n \\not_strict_mode.app_rd_data_reg[225]_0 ,\n \\not_strict_mode.app_rd_data_reg[223]_0 ,\n \\not_strict_mode.app_rd_data_reg[233]_0 ,\n \\not_strict_mode.app_rd_data_reg[231]_0 ,\n \\not_strict_mode.app_rd_data_reg[229]_0 ,\n \\not_strict_mode.app_rd_data_reg[239]_0 ,\n \\not_strict_mode.app_rd_data_reg[237]_0 ,\n \\not_strict_mode.app_rd_data_reg[235]_0 ,\n \\not_strict_mode.app_rd_data_reg[245]_0 ,\n \\not_strict_mode.app_rd_data_reg[243]_0 ,\n \\not_strict_mode.app_rd_data_reg[241]_0 ,\n \\not_strict_mode.app_rd_data_reg[251]_0 ,\n \\not_strict_mode.app_rd_data_reg[249]_0 ,\n \\not_strict_mode.app_rd_data_reg[247]_0 ,\n \\not_strict_mode.app_rd_data_reg[255]_0 ,\n \\not_strict_mode.app_rd_data_reg[253]_0 ,\n \\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ,\n app_rd_data_valid,\n D,\n \\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 ,\n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 ,\n \\rd_buf_indx.ram_init_done_r_lcl_reg_0 ,\n ADDRD,\n pointer_wr_data,\n \\s_axi_rdata[255] ,\n CLK,\n rd_buf_we,\n DIA,\n DIB,\n DIC,\n \\read_fifo.fifo_out_data_r_reg[7] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ,\n app_rd_data_end_ns,\n rd_accepted,\n reset_reg,\n \\not_strict_mode.occupied_counter.occ_cnt_r_reg[1]_0 ,\n bypass__0,\n \\read_data_indx.rd_data_indx_r_reg[3] ,\n \\cmd_pipe_plus.wr_data_addr_reg[3] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 );\n output [0:0]\\not_strict_mode.app_rd_data_end_reg_0 ;\n output [4:0]Q;\n output [1:0]DOA;\n output [1:0]DOB;\n output [1:0]DOC;\n output [1:0]\\not_strict_mode.app_rd_data_reg[11]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[9]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[7]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[17]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[15]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[13]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[23]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[21]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[19]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[29]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[27]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[25]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[35]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[33]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[31]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[41]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[39]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[37]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[47]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[45]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[43]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[53]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[51]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[49]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[59]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[57]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[55]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[65]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[63]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[61]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[71]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[69]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[67]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[77]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[75]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[73]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[83]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[81]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[79]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[89]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[87]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[85]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[95]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[93]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[91]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[101]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[99]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[97]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[107]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[105]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[103]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[113]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[111]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[109]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[119]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[117]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[115]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[125]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[123]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[121]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[131]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[129]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[127]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[137]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[135]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[133]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[143]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[141]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[139]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[149]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[147]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[145]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[155]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[153]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[151]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[161]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[159]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[157]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[167]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[165]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[163]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[173]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[171]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[169]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[179]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[177]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[175]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[185]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[183]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[181]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[191]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[189]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[187]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[197]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[195]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[193]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[203]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[201]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[199]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[209]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[207]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[205]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[215]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[213]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[211]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[221]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[219]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[217]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[227]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[225]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[223]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[233]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[231]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[229]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[239]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[237]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[235]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[245]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[243]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[241]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[251]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[249]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[247]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[255]_0 ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[253]_0 ;\n output \\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ;\n output app_rd_data_valid;\n output [0:0]D;\n output [1:0]\\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 ;\n output [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 ;\n output \\rd_buf_indx.ram_init_done_r_lcl_reg_0 ;\n output [3:0]ADDRD;\n output [3:0]pointer_wr_data;\n output [255:0]\\s_axi_rdata[255] ;\n input CLK;\n input rd_buf_we;\n input [1:0]DIA;\n input [1:0]DIB;\n input [1:0]DIC;\n input [6:0]\\read_fifo.fifo_out_data_r_reg[7] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;\n input app_rd_data_end_ns;\n input rd_accepted;\n input reset_reg;\n input \\not_strict_mode.occupied_counter.occ_cnt_r_reg[1]_0 ;\n input bypass__0;\n input [3:0]\\read_data_indx.rd_data_indx_r_reg[3] ;\n input [3:0]\\cmd_pipe_plus.wr_data_addr_reg[3] ;\n input [255:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ;\n\n wire [3:0]ADDRD;\n wire CLK;\n wire [0:0]D;\n wire [1:0]DIA;\n wire [1:0]DIB;\n wire [1:0]DIC;\n wire [1:0]DOA;\n wire [1:0]DOB;\n wire [1:0]DOC;\n wire [4:0]Q;\n wire app_rd_data_end;\n wire app_rd_data_end_ns;\n wire app_rd_data_valid;\n wire app_rd_data_valid_copy;\n wire app_rd_data_valid_ns;\n wire bypass__0;\n wire [3:0]\\cmd_pipe_plus.wr_data_addr_reg[3] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ;\n wire [255:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ;\n wire [0:0]\\not_strict_mode.app_rd_data_end_reg_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[101]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[103]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[105]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[107]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[109]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[111]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[113]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[115]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[117]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[119]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[11]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[121]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[123]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[125]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[127]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[129]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[131]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[133]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[135]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[137]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[139]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[13]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[141]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[143]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[145]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[147]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[149]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[151]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[153]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[155]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[157]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[159]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[15]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[161]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[163]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[165]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[167]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[169]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[171]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[173]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[175]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[177]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[179]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[17]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[181]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[183]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[185]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[187]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[189]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[191]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[193]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[195]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[197]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[199]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[19]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[201]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[203]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[205]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[207]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[209]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[211]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[213]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[215]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[217]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[219]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[21]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[221]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[223]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[225]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[227]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[229]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[231]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[233]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[235]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[237]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[239]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[23]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[241]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[243]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[245]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[247]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[249]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[251]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[253]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[255]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[25]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[27]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[29]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[31]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[33]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[35]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[37]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[39]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[41]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[43]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[45]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[47]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[49]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[51]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[53]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[55]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[57]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[59]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[61]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[63]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[65]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[67]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[69]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[71]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[73]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[75]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[77]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[79]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[7]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[81]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[83]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[85]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[87]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[89]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[91]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[93]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[95]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[97]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[99]_0 ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[9]_0 ;\n wire [4:0]\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 ;\n wire \\not_strict_mode.occupied_counter.occ_cnt_r[0]_i_1_n_0 ;\n wire \\not_strict_mode.occupied_counter.occ_cnt_r[1]_i_1_n_0 ;\n wire \\not_strict_mode.occupied_counter.occ_cnt_r[2]_i_1_n_0 ;\n wire \\not_strict_mode.occupied_counter.occ_cnt_r[3]_i_1_n_0 ;\n wire \\not_strict_mode.occupied_counter.occ_cnt_r[4]_i_1_n_0 ;\n wire \\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_2_n_0 ;\n wire \\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_3_n_0 ;\n wire \\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_4_n_0 ;\n wire \\not_strict_mode.occupied_counter.occ_cnt_r_reg[1]_0 ;\n wire [1:0]\\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 ;\n wire \\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ;\n wire [5:2]occ_cnt_r;\n wire [4:0]p_0_in__2;\n wire [3:0]pointer_wr_data;\n wire ram_init_done_ns;\n wire rd_accepted;\n wire \\rd_buf_indx.ram_init_done_r_lcl_i_2_n_0 ;\n wire \\rd_buf_indx.ram_init_done_r_lcl_reg_0 ;\n wire \\rd_buf_indx.rd_buf_indx_r[1]_i_2_n_0 ;\n wire \\rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0 ;\n wire \\rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ;\n (* RTL_KEEP = \"true\" *) (* syn_keep = \"true\" *) wire [4:0]rd_buf_indx_copy_r;\n wire [5:0]rd_buf_indx_ns;\n wire rd_buf_we;\n wire rd_buf_we_r1;\n wire [0:0]rd_status;\n wire [3:0]\\read_data_indx.rd_data_indx_r_reg[3] ;\n wire [6:0]\\read_fifo.fifo_out_data_r_reg[7] ;\n wire reset_reg;\n wire [255:0]\\s_axi_rdata[255] ;\n wire [4:0]status_ram_wr_addr_ns;\n wire [4:0]status_ram_wr_addr_r;\n wire [1:0]status_ram_wr_data_ns;\n wire [1:0]status_ram_wr_data_r;\n wire wr_status;\n wire wr_status_r1;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_DOA_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.status_ram.RAM32M0_DOB_UNCONNECTED ;\n wire [1:1]\\NLW_not_strict_mode.status_ram.RAM32M0_DOC_UNCONNECTED ;\n wire [1:0]\\NLW_not_strict_mode.status_ram.RAM32M0_DOD_UNCONNECTED ;\n\n FDRE \\not_strict_mode.app_rd_data_end_reg \n (.C(CLK),\n .CE(1'b1),\n .D(app_rd_data_end_ns),\n .Q(app_rd_data_end),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [0]),\n .Q(\\s_axi_rdata[255] [0]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[100] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [100]),\n .Q(\\s_axi_rdata[255] [100]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[101] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [101]),\n .Q(\\s_axi_rdata[255] [101]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[102] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [102]),\n .Q(\\s_axi_rdata[255] [102]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[103] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [103]),\n .Q(\\s_axi_rdata[255] [103]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[104] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [104]),\n .Q(\\s_axi_rdata[255] [104]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[105] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [105]),\n .Q(\\s_axi_rdata[255] [105]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[106] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [106]),\n .Q(\\s_axi_rdata[255] [106]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[107] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [107]),\n .Q(\\s_axi_rdata[255] [107]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[108] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [108]),\n .Q(\\s_axi_rdata[255] [108]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[109] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [109]),\n .Q(\\s_axi_rdata[255] [109]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [10]),\n .Q(\\s_axi_rdata[255] [10]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[110] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [110]),\n .Q(\\s_axi_rdata[255] [110]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[111] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [111]),\n .Q(\\s_axi_rdata[255] [111]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[112] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [112]),\n .Q(\\s_axi_rdata[255] [112]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[113] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [113]),\n .Q(\\s_axi_rdata[255] [113]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[114] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [114]),\n .Q(\\s_axi_rdata[255] [114]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[115] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [115]),\n .Q(\\s_axi_rdata[255] [115]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[116] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [116]),\n .Q(\\s_axi_rdata[255] [116]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[117] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [117]),\n .Q(\\s_axi_rdata[255] [117]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[118] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [118]),\n .Q(\\s_axi_rdata[255] [118]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[119] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [119]),\n .Q(\\s_axi_rdata[255] [119]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [11]),\n .Q(\\s_axi_rdata[255] [11]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[120] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [120]),\n .Q(\\s_axi_rdata[255] [120]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[121] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [121]),\n .Q(\\s_axi_rdata[255] [121]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[122] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [122]),\n .Q(\\s_axi_rdata[255] [122]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[123] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [123]),\n .Q(\\s_axi_rdata[255] [123]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[124] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [124]),\n .Q(\\s_axi_rdata[255] [124]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[125] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [125]),\n .Q(\\s_axi_rdata[255] [125]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[126] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [126]),\n .Q(\\s_axi_rdata[255] [126]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[127] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [127]),\n .Q(\\s_axi_rdata[255] [127]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[128] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [128]),\n .Q(\\s_axi_rdata[255] [128]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[129] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [129]),\n .Q(\\s_axi_rdata[255] [129]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[12] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [12]),\n .Q(\\s_axi_rdata[255] [12]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[130] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [130]),\n .Q(\\s_axi_rdata[255] [130]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[131] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [131]),\n .Q(\\s_axi_rdata[255] [131]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[132] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [132]),\n .Q(\\s_axi_rdata[255] [132]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[133] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [133]),\n .Q(\\s_axi_rdata[255] [133]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[134] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [134]),\n .Q(\\s_axi_rdata[255] [134]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[135] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [135]),\n .Q(\\s_axi_rdata[255] [135]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[136] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [136]),\n .Q(\\s_axi_rdata[255] [136]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[137] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [137]),\n .Q(\\s_axi_rdata[255] [137]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[138] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [138]),\n .Q(\\s_axi_rdata[255] [138]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[139] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [139]),\n .Q(\\s_axi_rdata[255] [139]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[13] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [13]),\n .Q(\\s_axi_rdata[255] [13]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[140] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [140]),\n .Q(\\s_axi_rdata[255] [140]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[141] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [141]),\n .Q(\\s_axi_rdata[255] [141]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[142] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [142]),\n .Q(\\s_axi_rdata[255] [142]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[143] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [143]),\n .Q(\\s_axi_rdata[255] [143]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[144] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [144]),\n .Q(\\s_axi_rdata[255] [144]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[145] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [145]),\n .Q(\\s_axi_rdata[255] [145]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[146] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [146]),\n .Q(\\s_axi_rdata[255] [146]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[147] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [147]),\n .Q(\\s_axi_rdata[255] [147]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[148] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [148]),\n .Q(\\s_axi_rdata[255] [148]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[149] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [149]),\n .Q(\\s_axi_rdata[255] [149]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[14] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [14]),\n .Q(\\s_axi_rdata[255] [14]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[150] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [150]),\n .Q(\\s_axi_rdata[255] [150]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[151] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [151]),\n .Q(\\s_axi_rdata[255] [151]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[152] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [152]),\n .Q(\\s_axi_rdata[255] [152]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[153] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [153]),\n .Q(\\s_axi_rdata[255] [153]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[154] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [154]),\n .Q(\\s_axi_rdata[255] [154]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[155] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [155]),\n .Q(\\s_axi_rdata[255] [155]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[156] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [156]),\n .Q(\\s_axi_rdata[255] [156]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[157] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [157]),\n .Q(\\s_axi_rdata[255] [157]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[158] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [158]),\n .Q(\\s_axi_rdata[255] [158]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[159] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [159]),\n .Q(\\s_axi_rdata[255] [159]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[15] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [15]),\n .Q(\\s_axi_rdata[255] [15]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[160] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [160]),\n .Q(\\s_axi_rdata[255] [160]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[161] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [161]),\n .Q(\\s_axi_rdata[255] [161]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[162] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [162]),\n .Q(\\s_axi_rdata[255] [162]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[163] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [163]),\n .Q(\\s_axi_rdata[255] [163]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[164] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [164]),\n .Q(\\s_axi_rdata[255] [164]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[165] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [165]),\n .Q(\\s_axi_rdata[255] [165]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[166] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [166]),\n .Q(\\s_axi_rdata[255] [166]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[167] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [167]),\n .Q(\\s_axi_rdata[255] [167]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[168] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [168]),\n .Q(\\s_axi_rdata[255] [168]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[169] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [169]),\n .Q(\\s_axi_rdata[255] [169]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[16] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [16]),\n .Q(\\s_axi_rdata[255] [16]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[170] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [170]),\n .Q(\\s_axi_rdata[255] [170]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[171] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [171]),\n .Q(\\s_axi_rdata[255] [171]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[172] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [172]),\n .Q(\\s_axi_rdata[255] [172]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[173] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [173]),\n .Q(\\s_axi_rdata[255] [173]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[174] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [174]),\n .Q(\\s_axi_rdata[255] [174]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[175] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [175]),\n .Q(\\s_axi_rdata[255] [175]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[176] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [176]),\n .Q(\\s_axi_rdata[255] [176]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[177] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [177]),\n .Q(\\s_axi_rdata[255] [177]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[178] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [178]),\n .Q(\\s_axi_rdata[255] [178]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[179] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [179]),\n .Q(\\s_axi_rdata[255] [179]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[17] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [17]),\n .Q(\\s_axi_rdata[255] [17]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[180] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [180]),\n .Q(\\s_axi_rdata[255] [180]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[181] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [181]),\n .Q(\\s_axi_rdata[255] [181]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[182] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [182]),\n .Q(\\s_axi_rdata[255] [182]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[183] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [183]),\n .Q(\\s_axi_rdata[255] [183]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[184] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [184]),\n .Q(\\s_axi_rdata[255] [184]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[185] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [185]),\n .Q(\\s_axi_rdata[255] [185]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[186] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [186]),\n .Q(\\s_axi_rdata[255] [186]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[187] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [187]),\n .Q(\\s_axi_rdata[255] [187]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[188] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [188]),\n .Q(\\s_axi_rdata[255] [188]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[189] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [189]),\n .Q(\\s_axi_rdata[255] [189]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[18] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [18]),\n .Q(\\s_axi_rdata[255] [18]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[190] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [190]),\n .Q(\\s_axi_rdata[255] [190]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[191] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [191]),\n .Q(\\s_axi_rdata[255] [191]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[192] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [192]),\n .Q(\\s_axi_rdata[255] [192]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[193] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [193]),\n .Q(\\s_axi_rdata[255] [193]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[194] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [194]),\n .Q(\\s_axi_rdata[255] [194]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[195] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [195]),\n .Q(\\s_axi_rdata[255] [195]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[196] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [196]),\n .Q(\\s_axi_rdata[255] [196]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[197] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [197]),\n .Q(\\s_axi_rdata[255] [197]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[198] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [198]),\n .Q(\\s_axi_rdata[255] [198]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[199] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [199]),\n .Q(\\s_axi_rdata[255] [199]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[19] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [19]),\n .Q(\\s_axi_rdata[255] [19]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [1]),\n .Q(\\s_axi_rdata[255] [1]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[200] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [200]),\n .Q(\\s_axi_rdata[255] [200]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[201] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [201]),\n .Q(\\s_axi_rdata[255] [201]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[202] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [202]),\n .Q(\\s_axi_rdata[255] [202]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[203] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [203]),\n .Q(\\s_axi_rdata[255] [203]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[204] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [204]),\n .Q(\\s_axi_rdata[255] [204]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[205] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [205]),\n .Q(\\s_axi_rdata[255] [205]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[206] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [206]),\n .Q(\\s_axi_rdata[255] [206]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[207] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [207]),\n .Q(\\s_axi_rdata[255] [207]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[208] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [208]),\n .Q(\\s_axi_rdata[255] [208]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[209] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [209]),\n .Q(\\s_axi_rdata[255] [209]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[20] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [20]),\n .Q(\\s_axi_rdata[255] [20]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[210] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [210]),\n .Q(\\s_axi_rdata[255] [210]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[211] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [211]),\n .Q(\\s_axi_rdata[255] [211]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[212] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [212]),\n .Q(\\s_axi_rdata[255] [212]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[213] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [213]),\n .Q(\\s_axi_rdata[255] [213]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[214] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [214]),\n .Q(\\s_axi_rdata[255] [214]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[215] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [215]),\n .Q(\\s_axi_rdata[255] [215]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[216] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [216]),\n .Q(\\s_axi_rdata[255] [216]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[217] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [217]),\n .Q(\\s_axi_rdata[255] [217]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[218] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [218]),\n .Q(\\s_axi_rdata[255] [218]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[219] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [219]),\n .Q(\\s_axi_rdata[255] [219]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[21] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [21]),\n .Q(\\s_axi_rdata[255] [21]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[220] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [220]),\n .Q(\\s_axi_rdata[255] [220]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[221] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [221]),\n .Q(\\s_axi_rdata[255] [221]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[222] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [222]),\n .Q(\\s_axi_rdata[255] [222]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[223] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [223]),\n .Q(\\s_axi_rdata[255] [223]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[224] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [224]),\n .Q(\\s_axi_rdata[255] [224]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[225] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [225]),\n .Q(\\s_axi_rdata[255] [225]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[226] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [226]),\n .Q(\\s_axi_rdata[255] [226]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[227] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [227]),\n .Q(\\s_axi_rdata[255] [227]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[228] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [228]),\n .Q(\\s_axi_rdata[255] [228]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[229] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [229]),\n .Q(\\s_axi_rdata[255] [229]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[22] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [22]),\n .Q(\\s_axi_rdata[255] [22]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[230] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [230]),\n .Q(\\s_axi_rdata[255] [230]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[231] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [231]),\n .Q(\\s_axi_rdata[255] [231]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[232] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [232]),\n .Q(\\s_axi_rdata[255] [232]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[233] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [233]),\n .Q(\\s_axi_rdata[255] [233]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[234] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [234]),\n .Q(\\s_axi_rdata[255] [234]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[235] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [235]),\n .Q(\\s_axi_rdata[255] [235]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[236] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [236]),\n .Q(\\s_axi_rdata[255] [236]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[237] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [237]),\n .Q(\\s_axi_rdata[255] [237]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[238] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [238]),\n .Q(\\s_axi_rdata[255] [238]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[239] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [239]),\n .Q(\\s_axi_rdata[255] [239]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[23] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [23]),\n .Q(\\s_axi_rdata[255] [23]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[240] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [240]),\n .Q(\\s_axi_rdata[255] [240]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[241] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [241]),\n .Q(\\s_axi_rdata[255] [241]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[242] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [242]),\n .Q(\\s_axi_rdata[255] [242]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[243] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [243]),\n .Q(\\s_axi_rdata[255] [243]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[244] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [244]),\n .Q(\\s_axi_rdata[255] [244]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[245] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [245]),\n .Q(\\s_axi_rdata[255] [245]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[246] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [246]),\n .Q(\\s_axi_rdata[255] [246]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[247] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [247]),\n .Q(\\s_axi_rdata[255] [247]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[248] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [248]),\n .Q(\\s_axi_rdata[255] [248]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[249] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [249]),\n .Q(\\s_axi_rdata[255] [249]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[24] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [24]),\n .Q(\\s_axi_rdata[255] [24]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[250] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [250]),\n .Q(\\s_axi_rdata[255] [250]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[251] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [251]),\n .Q(\\s_axi_rdata[255] [251]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[252] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [252]),\n .Q(\\s_axi_rdata[255] [252]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[253] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [253]),\n .Q(\\s_axi_rdata[255] [253]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[254] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [254]),\n .Q(\\s_axi_rdata[255] [254]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[255] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [255]),\n .Q(\\s_axi_rdata[255] [255]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[25] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [25]),\n .Q(\\s_axi_rdata[255] [25]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[26] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [26]),\n .Q(\\s_axi_rdata[255] [26]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[27] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [27]),\n .Q(\\s_axi_rdata[255] [27]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[28] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [28]),\n .Q(\\s_axi_rdata[255] [28]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[29] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [29]),\n .Q(\\s_axi_rdata[255] [29]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [2]),\n .Q(\\s_axi_rdata[255] [2]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[30] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [30]),\n .Q(\\s_axi_rdata[255] [30]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[31] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [31]),\n .Q(\\s_axi_rdata[255] [31]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[32] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [32]),\n .Q(\\s_axi_rdata[255] [32]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[33] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [33]),\n .Q(\\s_axi_rdata[255] [33]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[34] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [34]),\n .Q(\\s_axi_rdata[255] [34]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[35] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [35]),\n .Q(\\s_axi_rdata[255] [35]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[36] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [36]),\n .Q(\\s_axi_rdata[255] [36]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[37] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [37]),\n .Q(\\s_axi_rdata[255] [37]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[38] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [38]),\n .Q(\\s_axi_rdata[255] [38]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[39] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [39]),\n .Q(\\s_axi_rdata[255] [39]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [3]),\n .Q(\\s_axi_rdata[255] [3]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[40] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [40]),\n .Q(\\s_axi_rdata[255] [40]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[41] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [41]),\n .Q(\\s_axi_rdata[255] [41]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[42] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [42]),\n .Q(\\s_axi_rdata[255] [42]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[43] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [43]),\n .Q(\\s_axi_rdata[255] [43]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[44] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [44]),\n .Q(\\s_axi_rdata[255] [44]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[45] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [45]),\n .Q(\\s_axi_rdata[255] [45]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[46] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [46]),\n .Q(\\s_axi_rdata[255] [46]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[47] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [47]),\n .Q(\\s_axi_rdata[255] [47]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[48] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [48]),\n .Q(\\s_axi_rdata[255] [48]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[49] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [49]),\n .Q(\\s_axi_rdata[255] [49]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [4]),\n .Q(\\s_axi_rdata[255] [4]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[50] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [50]),\n .Q(\\s_axi_rdata[255] [50]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[51] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [51]),\n .Q(\\s_axi_rdata[255] [51]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[52] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [52]),\n .Q(\\s_axi_rdata[255] [52]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[53] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [53]),\n .Q(\\s_axi_rdata[255] [53]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[54] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [54]),\n .Q(\\s_axi_rdata[255] [54]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[55] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [55]),\n .Q(\\s_axi_rdata[255] [55]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[56] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [56]),\n .Q(\\s_axi_rdata[255] [56]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[57] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [57]),\n .Q(\\s_axi_rdata[255] [57]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[58] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [58]),\n .Q(\\s_axi_rdata[255] [58]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[59] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [59]),\n .Q(\\s_axi_rdata[255] [59]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [5]),\n .Q(\\s_axi_rdata[255] [5]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[60] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [60]),\n .Q(\\s_axi_rdata[255] [60]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[61] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [61]),\n .Q(\\s_axi_rdata[255] [61]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[62] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [62]),\n .Q(\\s_axi_rdata[255] [62]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[63] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [63]),\n .Q(\\s_axi_rdata[255] [63]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[64] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [64]),\n .Q(\\s_axi_rdata[255] [64]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[65] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [65]),\n .Q(\\s_axi_rdata[255] [65]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[66] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [66]),\n .Q(\\s_axi_rdata[255] [66]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[67] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [67]),\n .Q(\\s_axi_rdata[255] [67]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[68] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [68]),\n .Q(\\s_axi_rdata[255] [68]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[69] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [69]),\n .Q(\\s_axi_rdata[255] [69]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [6]),\n .Q(\\s_axi_rdata[255] [6]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[70] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [70]),\n .Q(\\s_axi_rdata[255] [70]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[71] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [71]),\n .Q(\\s_axi_rdata[255] [71]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[72] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [72]),\n .Q(\\s_axi_rdata[255] [72]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[73] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [73]),\n .Q(\\s_axi_rdata[255] [73]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[74] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [74]),\n .Q(\\s_axi_rdata[255] [74]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[75] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [75]),\n .Q(\\s_axi_rdata[255] [75]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[76] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [76]),\n .Q(\\s_axi_rdata[255] [76]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[77] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [77]),\n .Q(\\s_axi_rdata[255] [77]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[78] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [78]),\n .Q(\\s_axi_rdata[255] [78]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[79] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [79]),\n .Q(\\s_axi_rdata[255] [79]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [7]),\n .Q(\\s_axi_rdata[255] [7]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[80] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [80]),\n .Q(\\s_axi_rdata[255] [80]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[81] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [81]),\n .Q(\\s_axi_rdata[255] [81]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[82] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [82]),\n .Q(\\s_axi_rdata[255] [82]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[83] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [83]),\n .Q(\\s_axi_rdata[255] [83]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[84] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [84]),\n .Q(\\s_axi_rdata[255] [84]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[85] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [85]),\n .Q(\\s_axi_rdata[255] [85]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[86] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [86]),\n .Q(\\s_axi_rdata[255] [86]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[87] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [87]),\n .Q(\\s_axi_rdata[255] [87]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[88] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [88]),\n .Q(\\s_axi_rdata[255] [88]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[89] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [89]),\n .Q(\\s_axi_rdata[255] [89]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [8]),\n .Q(\\s_axi_rdata[255] [8]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[90] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [90]),\n .Q(\\s_axi_rdata[255] [90]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[91] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [91]),\n .Q(\\s_axi_rdata[255] [91]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[92] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [92]),\n .Q(\\s_axi_rdata[255] [92]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[93] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [93]),\n .Q(\\s_axi_rdata[255] [93]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[94] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [94]),\n .Q(\\s_axi_rdata[255] [94]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[95] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [95]),\n .Q(\\s_axi_rdata[255] [95]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[96] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [96]),\n .Q(\\s_axi_rdata[255] [96]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[97] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [97]),\n .Q(\\s_axi_rdata[255] [97]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[98] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [98]),\n .Q(\\s_axi_rdata[255] [98]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[99] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [99]),\n .Q(\\s_axi_rdata[255] [99]),\n .R(1'b0));\n FDRE \\not_strict_mode.app_rd_data_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 [9]),\n .Q(\\s_axi_rdata[255] [9]),\n .R(1'b0));\n (* equivalent_register_removal = \"no\" *) \n FDRE \\not_strict_mode.app_rd_data_valid_copy_reg \n (.C(CLK),\n .CE(1'b1),\n .D(app_rd_data_valid_ns),\n .Q(app_rd_data_valid_copy),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1505\" *) \n LUT4 #(\n .INIT(16'hEB00)) \n \\not_strict_mode.app_rd_data_valid_i_1 \n (.I0(bypass__0),\n .I1(\\rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ),\n .I2(rd_status),\n .I3(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .O(app_rd_data_valid_ns));\n (* syn_maxfan = \"10\" *) \n FDRE \\not_strict_mode.app_rd_data_valid_reg \n (.C(CLK),\n .CE(1'b1),\n .D(app_rd_data_valid_ns),\n .Q(app_rd_data_valid),\n .R(1'b0));\n LUT1 #(\n .INIT(2'h1)) \n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[0]_i_1 \n (.I0(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [0]),\n .O(p_0_in__2[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1511\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[1]_i_1 \n (.I0(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [0]),\n .I1(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [1]),\n .O(p_0_in__2[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1511\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[2]_i_1 \n (.I0(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [0]),\n .I1(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [1]),\n .I2(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [2]),\n .O(p_0_in__2[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1506\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[3]_i_1 \n (.I0(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [1]),\n .I1(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [0]),\n .I2(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [2]),\n .I3(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [3]),\n .O(p_0_in__2[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1506\" *) \n LUT5 #(\n .INIT(32'h7FFF8000)) \n \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[4]_i_2 \n (.I0(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [2]),\n .I1(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [0]),\n .I2(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [1]),\n .I3(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [3]),\n .I4(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [4]),\n .O(p_0_in__2[4]));\n FDRE \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[0] \n (.C(CLK),\n .CE(rd_accepted),\n .D(p_0_in__2[0]),\n .Q(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [0]),\n .R(reset_reg));\n FDRE \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[1] \n (.C(CLK),\n .CE(rd_accepted),\n .D(p_0_in__2[1]),\n .Q(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [1]),\n .R(reset_reg));\n FDRE \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[2] \n (.C(CLK),\n .CE(rd_accepted),\n .D(p_0_in__2[2]),\n .Q(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [2]),\n .R(reset_reg));\n FDRE \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[3] \n (.C(CLK),\n .CE(rd_accepted),\n .D(p_0_in__2[3]),\n .Q(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [3]),\n .R(reset_reg));\n FDRE \\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] \n (.C(CLK),\n .CE(rd_accepted),\n .D(p_0_in__2[4]),\n .Q(\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [4]),\n .R(reset_reg));\n (* SOFT_HLUTNM = \"soft_lutpair1507\" *) \n LUT5 #(\n .INIT(32'h00009666)) \n \\not_strict_mode.occupied_counter.occ_cnt_r[0]_i_1 \n (.I0(\\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [0]),\n .I1(rd_accepted),\n .I2(app_rd_data_valid_copy),\n .I3(app_rd_data_end),\n .I4(reset_reg),\n .O(\\not_strict_mode.occupied_counter.occ_cnt_r[0]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00000000C96C6C6C)) \n \\not_strict_mode.occupied_counter.occ_cnt_r[1]_i_1 \n (.I0(\\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [0]),\n .I1(\\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [1]),\n .I2(rd_accepted),\n .I3(app_rd_data_valid_copy),\n .I4(app_rd_data_end),\n .I5(reset_reg),\n .O(\\not_strict_mode.occupied_counter.occ_cnt_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF81007E008100)) \n \\not_strict_mode.occupied_counter.occ_cnt_r[2]_i_1 \n (.I0(\\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [0]),\n .I1(rd_accepted),\n .I2(\\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [1]),\n .I3(\\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_3_n_0 ),\n .I4(occ_cnt_r[2]),\n .I5(\\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_4_n_0 ),\n .O(\\not_strict_mode.occupied_counter.occ_cnt_r[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF81007E008100)) \n \\not_strict_mode.occupied_counter.occ_cnt_r[3]_i_1 \n (.I0(occ_cnt_r[2]),\n .I1(\\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [1]),\n .I2(\\not_strict_mode.occupied_counter.occ_cnt_r_reg[1]_0 ),\n .I3(\\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_3_n_0 ),\n .I4(occ_cnt_r[3]),\n .I5(\\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_4_n_0 ),\n .O(\\not_strict_mode.occupied_counter.occ_cnt_r[3]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hFF906090)) \n \\not_strict_mode.occupied_counter.occ_cnt_r[4]_i_1 \n (.I0(occ_cnt_r[3]),\n .I1(\\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_2_n_0 ),\n .I2(\\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_3_n_0 ),\n .I3(occ_cnt_r[4]),\n .I4(\\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_4_n_0 ),\n .O(\\not_strict_mode.occupied_counter.occ_cnt_r[4]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'hFFFF81007E008100)) \n \\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_1 \n (.I0(occ_cnt_r[4]),\n .I1(occ_cnt_r[3]),\n .I2(\\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_2_n_0 ),\n .I3(\\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_3_n_0 ),\n .I4(occ_cnt_r[5]),\n .I5(\\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_4_n_0 ),\n .O(D));\n LUT5 #(\n .INIT(32'h8000FFFE)) \n \\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_2 \n (.I0(\\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [1]),\n .I1(rd_accepted),\n .I2(\\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [0]),\n .I3(occ_cnt_r[2]),\n .I4(occ_cnt_r[3]),\n .O(\\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1507\" *) \n LUT4 #(\n .INIT(16'h006A)) \n \\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_3 \n (.I0(rd_accepted),\n .I1(app_rd_data_valid_copy),\n .I2(app_rd_data_end),\n .I3(reset_reg),\n .O(\\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_3_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1508\" *) \n LUT4 #(\n .INIT(16'h0095)) \n \\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_4 \n (.I0(rd_accepted),\n .I1(app_rd_data_valid_copy),\n .I2(app_rd_data_end),\n .I3(reset_reg),\n .O(\\not_strict_mode.occupied_counter.occ_cnt_r[5]_i_4_n_0 ));\n FDRE \\not_strict_mode.occupied_counter.occ_cnt_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\not_strict_mode.occupied_counter.occ_cnt_r[0]_i_1_n_0 ),\n .Q(\\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [0]),\n .R(1'b0));\n FDRE \\not_strict_mode.occupied_counter.occ_cnt_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\not_strict_mode.occupied_counter.occ_cnt_r[1]_i_1_n_0 ),\n .Q(\\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 [1]),\n .R(1'b0));\n FDRE \\not_strict_mode.occupied_counter.occ_cnt_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\not_strict_mode.occupied_counter.occ_cnt_r[2]_i_1_n_0 ),\n .Q(occ_cnt_r[2]),\n .R(1'b0));\n FDRE \\not_strict_mode.occupied_counter.occ_cnt_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\not_strict_mode.occupied_counter.occ_cnt_r[3]_i_1_n_0 ),\n .Q(occ_cnt_r[3]),\n .R(1'b0));\n FDRE \\not_strict_mode.occupied_counter.occ_cnt_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\not_strict_mode.occupied_counter.occ_cnt_r[4]_i_1_n_0 ),\n .Q(occ_cnt_r[4]),\n .R(1'b0));\n FDRE \\not_strict_mode.occupied_counter.occ_cnt_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(D),\n .Q(occ_cnt_r[5]),\n .R(1'b0));\n (* KEEP = \"yes\" *) \n (* syn_keep = \"true\" *) \n FDRE \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_buf_indx_ns[0]),\n .Q(rd_buf_indx_copy_r[0]),\n .R(1'b0));\n (* KEEP = \"yes\" *) \n (* syn_keep = \"true\" *) \n FDRE \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_buf_indx_ns[1]),\n .Q(rd_buf_indx_copy_r[1]),\n .R(1'b0));\n (* KEEP = \"yes\" *) \n (* syn_keep = \"true\" *) \n FDRE \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_buf_indx_ns[2]),\n .Q(rd_buf_indx_copy_r[2]),\n .R(1'b0));\n (* KEEP = \"yes\" *) \n (* syn_keep = \"true\" *) \n FDRE \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_buf_indx_ns[3]),\n .Q(rd_buf_indx_copy_r[3]),\n .R(1'b0));\n (* KEEP = \"yes\" *) \n (* syn_keep = \"true\" *) \n FDRE \\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_buf_indx_ns[4]),\n .Q(rd_buf_indx_copy_r[4]),\n .R(1'b0));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(DIA),\n .DIB(DIB),\n .DIC(DIC),\n .DID({1'b0,1'b0}),\n .DOA(DOA),\n .DOB(DOB),\n .DOC(DOC),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[65]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[63]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[61]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[71]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[69]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[67]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[77]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[75]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[73]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[83]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[81]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[79]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[89]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[87]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[85]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[95]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[93]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[91]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[101]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[99]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[97]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[107]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[105]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[103]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[113]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[111]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[109]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[119]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[117]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[115]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[11]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[9]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[7]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[125]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[123]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[121]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[131]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[129]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[127]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[137]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[135]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[133]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[143]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[141]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[139]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[149]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[147]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[145]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[155]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[153]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[151]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[161]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[159]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[157]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[167]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[165]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[163]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[173]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[171]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[169]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[179]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[177]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[175]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[17]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[15]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[13]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[185]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[183]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[181]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[191]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[189]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[187]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[197]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[195]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[193]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[203]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[201]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[199]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[209]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[207]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[205]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[215]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[213]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[211]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[221]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[219]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[217]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[227]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[225]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[223]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[233]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[231]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[229]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[239]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[237]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[235]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[23]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[21]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[19]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[245]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[243]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[241]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[251]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[249]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[247]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA({1'b0,1'b0}),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ),\n .DID({1'b0,1'b0}),\n .DOA(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_DOA_UNCONNECTED [1:0]),\n .DOB(\\not_strict_mode.app_rd_data_reg[255]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[253]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[29]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[27]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[25]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[35]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[33]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[31]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[41]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[39]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[37]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[47]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[45]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[43]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[53]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[51]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[49]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0 \n (.ADDRA(rd_buf_indx_copy_r),\n .ADDRB(rd_buf_indx_copy_r),\n .ADDRC(rd_buf_indx_copy_r),\n .ADDRD(\\read_fifo.fifo_out_data_r_reg[7] [5:1]),\n .DIA(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ),\n .DIB(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ),\n .DIC(\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ),\n .DID({1'b0,1'b0}),\n .DOA(\\not_strict_mode.app_rd_data_reg[59]_0 ),\n .DOB(\\not_strict_mode.app_rd_data_reg[57]_0 ),\n .DOC(\\not_strict_mode.app_rd_data_reg[55]_0 ),\n .DOD(\\NLW_not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\not_strict_mode.status_ram.RAM32M0 \n (.ADDRA(Q),\n .ADDRB({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .ADDRC(status_ram_wr_addr_ns),\n .ADDRD(status_ram_wr_addr_r),\n .DIA(status_ram_wr_data_r),\n .DIB({1'b0,1'b0}),\n .DIC(status_ram_wr_data_r),\n .DID(status_ram_wr_data_r),\n .DOA({\\not_strict_mode.app_rd_data_end_reg_0 ,rd_status}),\n .DOB(\\NLW_not_strict_mode.status_ram.RAM32M0_DOB_UNCONNECTED [1:0]),\n .DOC({\\NLW_not_strict_mode.status_ram.RAM32M0_DOC_UNCONNECTED [1],wr_status}),\n .DOD(\\NLW_not_strict_mode.status_ram.RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(rd_buf_we_r1));\n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.status_ram.RAM32M0_i_1 \n (.I0(\\read_fifo.fifo_out_data_r_reg[7] [5]),\n .I1(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I2(Q[4]),\n .O(status_ram_wr_addr_ns[4]));\n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.status_ram.RAM32M0_i_2 \n (.I0(\\read_fifo.fifo_out_data_r_reg[7] [4]),\n .I1(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I2(Q[3]),\n .O(status_ram_wr_addr_ns[3]));\n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.status_ram.RAM32M0_i_3 \n (.I0(\\read_fifo.fifo_out_data_r_reg[7] [3]),\n .I1(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I2(Q[2]),\n .O(status_ram_wr_addr_ns[2]));\n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.status_ram.RAM32M0_i_4 \n (.I0(\\read_fifo.fifo_out_data_r_reg[7] [2]),\n .I1(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I2(Q[1]),\n .O(status_ram_wr_addr_ns[1]));\n LUT3 #(\n .INIT(8'hB8)) \n \\not_strict_mode.status_ram.RAM32M0_i_5 \n (.I0(\\read_fifo.fifo_out_data_r_reg[7] [1]),\n .I1(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I2(Q[0]),\n .O(status_ram_wr_addr_ns[0]));\n FDRE \\not_strict_mode.status_ram.rd_buf_we_r1_reg \n (.C(CLK),\n .CE(1'b1),\n .D(rd_buf_we),\n .Q(rd_buf_we_r1),\n .R(1'b0));\n FDRE \\not_strict_mode.status_ram.status_ram_wr_addr_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(status_ram_wr_addr_ns[0]),\n .Q(status_ram_wr_addr_r[0]),\n .R(1'b0));\n FDRE \\not_strict_mode.status_ram.status_ram_wr_addr_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(status_ram_wr_addr_ns[1]),\n .Q(status_ram_wr_addr_r[1]),\n .R(1'b0));\n FDRE \\not_strict_mode.status_ram.status_ram_wr_addr_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(status_ram_wr_addr_ns[2]),\n .Q(status_ram_wr_addr_r[2]),\n .R(1'b0));\n FDRE \\not_strict_mode.status_ram.status_ram_wr_addr_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(status_ram_wr_addr_ns[3]),\n .Q(status_ram_wr_addr_r[3]),\n .R(1'b0));\n FDRE \\not_strict_mode.status_ram.status_ram_wr_addr_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(status_ram_wr_addr_ns[4]),\n .Q(status_ram_wr_addr_r[4]),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1509\" *) \n LUT4 #(\n .INIT(16'h404C)) \n \\not_strict_mode.status_ram.status_ram_wr_data_r[0]_i_1 \n (.I0(wr_status_r1),\n .I1(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I2(\\read_fifo.fifo_out_data_r_reg[7] [0]),\n .I3(wr_status),\n .O(status_ram_wr_data_ns[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1509\" *) \n LUT2 #(\n .INIT(4'h8)) \n \\not_strict_mode.status_ram.status_ram_wr_data_r[1]_i_1 \n (.I0(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I1(\\read_fifo.fifo_out_data_r_reg[7] [6]),\n .O(status_ram_wr_data_ns[1]));\n FDRE \\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(status_ram_wr_data_ns[0]),\n .Q(status_ram_wr_data_r[0]),\n .R(1'b0));\n FDRE \\not_strict_mode.status_ram.status_ram_wr_data_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(status_ram_wr_data_ns[1]),\n .Q(status_ram_wr_data_r[1]),\n .R(1'b0));\n FDRE \\not_strict_mode.status_ram.wr_status_r1_reg \n (.C(CLK),\n .CE(1'b1),\n .D(wr_status),\n .Q(wr_status_r1),\n .R(1'b0));\n LUT3 #(\n .INIT(8'hB8)) \n \\pointer_ram.rams[0].RAM32M0_i_2 \n (.I0(\\cmd_pipe_plus.wr_data_addr_reg[3] [1]),\n .I1(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I2(Q[1]),\n .O(pointer_wr_data[1]));\n LUT3 #(\n .INIT(8'hB8)) \n \\pointer_ram.rams[0].RAM32M0_i_3 \n (.I0(\\cmd_pipe_plus.wr_data_addr_reg[3] [0]),\n .I1(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I2(Q[0]),\n .O(pointer_wr_data[0]));\n LUT3 #(\n .INIT(8'hB8)) \n \\pointer_ram.rams[0].RAM32M0_i_4 \n (.I0(\\read_data_indx.rd_data_indx_r_reg[3] [3]),\n .I1(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I2(Q[3]),\n .O(ADDRD[3]));\n LUT3 #(\n .INIT(8'hB8)) \n \\pointer_ram.rams[0].RAM32M0_i_5 \n (.I0(\\read_data_indx.rd_data_indx_r_reg[3] [2]),\n .I1(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I2(Q[2]),\n .O(ADDRD[2]));\n LUT3 #(\n .INIT(8'hB8)) \n \\pointer_ram.rams[0].RAM32M0_i_6 \n (.I0(\\read_data_indx.rd_data_indx_r_reg[3] [1]),\n .I1(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I2(Q[1]),\n .O(ADDRD[1]));\n LUT3 #(\n .INIT(8'hB8)) \n \\pointer_ram.rams[0].RAM32M0_i_7 \n (.I0(\\read_data_indx.rd_data_indx_r_reg[3] [0]),\n .I1(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I2(Q[0]),\n .O(ADDRD[0]));\n LUT3 #(\n .INIT(8'hB8)) \n \\pointer_ram.rams[1].RAM32M0_i_1 \n (.I0(\\cmd_pipe_plus.wr_data_addr_reg[3] [3]),\n .I1(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I2(Q[3]),\n .O(pointer_wr_data[3]));\n LUT3 #(\n .INIT(8'hB8)) \n \\pointer_ram.rams[1].RAM32M0_i_2 \n (.I0(\\cmd_pipe_plus.wr_data_addr_reg[3] [2]),\n .I1(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I2(Q[2]),\n .O(pointer_wr_data[2]));\n LUT6 #(\n .INIT(64'hFFFFFFFF80000000)) \n \\rd_buf_indx.ram_init_done_r_lcl_i_1 \n (.I0(Q[3]),\n .I1(Q[4]),\n .I2(\\rd_buf_indx.ram_init_done_r_lcl_i_2_n_0 ),\n .I3(Q[2]),\n .I4(Q[1]),\n .I5(\\rd_buf_indx.ram_init_done_r_lcl_reg_0 ),\n .O(ram_init_done_ns));\n LUT2 #(\n .INIT(4'h2)) \n \\rd_buf_indx.ram_init_done_r_lcl_i_2 \n (.I0(Q[0]),\n .I1(reset_reg),\n .O(\\rd_buf_indx.ram_init_done_r_lcl_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1508\" *) \n LUT2 #(\n .INIT(4'h2)) \n \\rd_buf_indx.ram_init_done_r_lcl_i_3 \n (.I0(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I1(reset_reg),\n .O(\\rd_buf_indx.ram_init_done_r_lcl_reg_0 ));\n (* syn_maxfan = \"10\" *) \n FDRE \\rd_buf_indx.ram_init_done_r_lcl_reg \n (.C(CLK),\n .CE(1'b1),\n .D(ram_init_done_ns),\n .Q(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h000000001400EBFF)) \n \\rd_buf_indx.rd_buf_indx_r[0]_i_1 \n (.I0(bypass__0),\n .I1(\\rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ),\n .I2(rd_status),\n .I3(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I4(Q[0]),\n .I5(reset_reg),\n .O(rd_buf_indx_ns[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1510\" *) \n LUT3 #(\n .INIT(8'h09)) \n \\rd_buf_indx.rd_buf_indx_r[1]_i_1 \n (.I0(\\rd_buf_indx.rd_buf_indx_r[1]_i_2_n_0 ),\n .I1(Q[1]),\n .I2(reset_reg),\n .O(rd_buf_indx_ns[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1505\" *) \n LUT5 #(\n .INIT(32'h0028FFFF)) \n \\rd_buf_indx.rd_buf_indx_r[1]_i_2 \n (.I0(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .I1(rd_status),\n .I2(\\rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ),\n .I3(bypass__0),\n .I4(Q[0]),\n .O(\\rd_buf_indx.rd_buf_indx_r[1]_i_2_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1510\" *) \n LUT3 #(\n .INIT(8'h06)) \n \\rd_buf_indx.rd_buf_indx_r[2]_i_1 \n (.I0(\\rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0 ),\n .I1(Q[2]),\n .I2(reset_reg),\n .O(rd_buf_indx_ns[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1504\" *) \n LUT4 #(\n .INIT(16'h0078)) \n \\rd_buf_indx.rd_buf_indx_r[3]_i_1 \n (.I0(\\rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0 ),\n .I1(Q[2]),\n .I2(Q[3]),\n .I3(reset_reg),\n .O(rd_buf_indx_ns[3]));\n (* SOFT_HLUTNM = \"soft_lutpair1504\" *) \n LUT5 #(\n .INIT(32'h00007F80)) \n \\rd_buf_indx.rd_buf_indx_r[4]_i_1 \n (.I0(Q[3]),\n .I1(Q[2]),\n .I2(\\rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0 ),\n .I3(Q[4]),\n .I4(reset_reg),\n .O(rd_buf_indx_ns[4]));\n LUT6 #(\n .INIT(64'h000000007FFF8000)) \n \\rd_buf_indx.rd_buf_indx_r[5]_i_1 \n (.I0(\\rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0 ),\n .I1(Q[2]),\n .I2(Q[3]),\n .I3(Q[4]),\n .I4(\\rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ),\n .I5(reset_reg),\n .O(rd_buf_indx_ns[5]));\n LUT6 #(\n .INIT(64'h8880808888888888)) \n \\rd_buf_indx.rd_buf_indx_r[5]_i_2 \n (.I0(Q[1]),\n .I1(Q[0]),\n .I2(bypass__0),\n .I3(\\rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ),\n .I4(rd_status),\n .I5(\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 ),\n .O(\\rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0 ));\n FDRE \\rd_buf_indx.rd_buf_indx_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_buf_indx_ns[0]),\n .Q(Q[0]),\n .R(1'b0));\n FDRE \\rd_buf_indx.rd_buf_indx_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_buf_indx_ns[1]),\n .Q(Q[1]),\n .R(1'b0));\n FDRE \\rd_buf_indx.rd_buf_indx_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_buf_indx_ns[2]),\n .Q(Q[2]),\n .R(1'b0));\n FDRE \\rd_buf_indx.rd_buf_indx_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_buf_indx_ns[3]),\n .Q(Q[3]),\n .R(1'b0));\n FDRE \\rd_buf_indx.rd_buf_indx_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_buf_indx_ns[4]),\n .Q(Q[4]),\n .R(1'b0));\n FDRE \\rd_buf_indx.rd_buf_indx_r_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(rd_buf_indx_ns[5]),\n .Q(\\rd_buf_indx.rd_buf_indx_r_reg_n_0_[5] ),\n .R(1'b0));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_ui_top\n (\\not_strict_mode.app_rd_data_end_reg ,\n Q,\n DOA,\n DOB,\n DOC,\n \\not_strict_mode.app_rd_data_reg[11] ,\n \\not_strict_mode.app_rd_data_reg[9] ,\n \\not_strict_mode.app_rd_data_reg[7] ,\n \\not_strict_mode.app_rd_data_reg[17] ,\n \\not_strict_mode.app_rd_data_reg[15] ,\n \\not_strict_mode.app_rd_data_reg[13] ,\n \\not_strict_mode.app_rd_data_reg[23] ,\n \\not_strict_mode.app_rd_data_reg[21] ,\n \\not_strict_mode.app_rd_data_reg[19] ,\n \\not_strict_mode.app_rd_data_reg[29] ,\n \\not_strict_mode.app_rd_data_reg[27] ,\n \\not_strict_mode.app_rd_data_reg[25] ,\n \\not_strict_mode.app_rd_data_reg[35] ,\n \\not_strict_mode.app_rd_data_reg[33] ,\n \\not_strict_mode.app_rd_data_reg[31] ,\n \\not_strict_mode.app_rd_data_reg[41] ,\n \\not_strict_mode.app_rd_data_reg[39] ,\n \\not_strict_mode.app_rd_data_reg[37] ,\n \\not_strict_mode.app_rd_data_reg[47] ,\n \\not_strict_mode.app_rd_data_reg[45] ,\n \\not_strict_mode.app_rd_data_reg[43] ,\n \\not_strict_mode.app_rd_data_reg[53] ,\n \\not_strict_mode.app_rd_data_reg[51] ,\n \\not_strict_mode.app_rd_data_reg[49] ,\n \\not_strict_mode.app_rd_data_reg[59] ,\n \\not_strict_mode.app_rd_data_reg[57] ,\n \\not_strict_mode.app_rd_data_reg[55] ,\n \\not_strict_mode.app_rd_data_reg[65] ,\n \\not_strict_mode.app_rd_data_reg[63] ,\n \\not_strict_mode.app_rd_data_reg[61] ,\n \\not_strict_mode.app_rd_data_reg[71] ,\n \\not_strict_mode.app_rd_data_reg[69] ,\n \\not_strict_mode.app_rd_data_reg[67] ,\n \\not_strict_mode.app_rd_data_reg[77] ,\n \\not_strict_mode.app_rd_data_reg[75] ,\n \\not_strict_mode.app_rd_data_reg[73] ,\n \\not_strict_mode.app_rd_data_reg[83] ,\n \\not_strict_mode.app_rd_data_reg[81] ,\n \\not_strict_mode.app_rd_data_reg[79] ,\n \\not_strict_mode.app_rd_data_reg[89] ,\n \\not_strict_mode.app_rd_data_reg[87] ,\n \\not_strict_mode.app_rd_data_reg[85] ,\n \\not_strict_mode.app_rd_data_reg[95] ,\n \\not_strict_mode.app_rd_data_reg[93] ,\n \\not_strict_mode.app_rd_data_reg[91] ,\n \\not_strict_mode.app_rd_data_reg[101] ,\n \\not_strict_mode.app_rd_data_reg[99] ,\n \\not_strict_mode.app_rd_data_reg[97] ,\n \\not_strict_mode.app_rd_data_reg[107] ,\n \\not_strict_mode.app_rd_data_reg[105] ,\n \\not_strict_mode.app_rd_data_reg[103] ,\n \\not_strict_mode.app_rd_data_reg[113] ,\n \\not_strict_mode.app_rd_data_reg[111] ,\n \\not_strict_mode.app_rd_data_reg[109] ,\n \\not_strict_mode.app_rd_data_reg[119] ,\n \\not_strict_mode.app_rd_data_reg[117] ,\n \\not_strict_mode.app_rd_data_reg[115] ,\n \\not_strict_mode.app_rd_data_reg[125] ,\n \\not_strict_mode.app_rd_data_reg[123] ,\n \\not_strict_mode.app_rd_data_reg[121] ,\n \\not_strict_mode.app_rd_data_reg[131] ,\n \\not_strict_mode.app_rd_data_reg[129] ,\n \\not_strict_mode.app_rd_data_reg[127] ,\n \\not_strict_mode.app_rd_data_reg[137] ,\n \\not_strict_mode.app_rd_data_reg[135] ,\n \\not_strict_mode.app_rd_data_reg[133] ,\n \\not_strict_mode.app_rd_data_reg[143] ,\n \\not_strict_mode.app_rd_data_reg[141] ,\n \\not_strict_mode.app_rd_data_reg[139] ,\n \\not_strict_mode.app_rd_data_reg[149] ,\n \\not_strict_mode.app_rd_data_reg[147] ,\n \\not_strict_mode.app_rd_data_reg[145] ,\n \\not_strict_mode.app_rd_data_reg[155] ,\n \\not_strict_mode.app_rd_data_reg[153] ,\n \\not_strict_mode.app_rd_data_reg[151] ,\n \\not_strict_mode.app_rd_data_reg[161] ,\n \\not_strict_mode.app_rd_data_reg[159] ,\n \\not_strict_mode.app_rd_data_reg[157] ,\n \\not_strict_mode.app_rd_data_reg[167] ,\n \\not_strict_mode.app_rd_data_reg[165] ,\n \\not_strict_mode.app_rd_data_reg[163] ,\n \\not_strict_mode.app_rd_data_reg[173] ,\n \\not_strict_mode.app_rd_data_reg[171] ,\n \\not_strict_mode.app_rd_data_reg[169] ,\n \\not_strict_mode.app_rd_data_reg[179] ,\n \\not_strict_mode.app_rd_data_reg[177] ,\n \\not_strict_mode.app_rd_data_reg[175] ,\n \\not_strict_mode.app_rd_data_reg[185] ,\n \\not_strict_mode.app_rd_data_reg[183] ,\n \\not_strict_mode.app_rd_data_reg[181] ,\n \\not_strict_mode.app_rd_data_reg[191] ,\n \\not_strict_mode.app_rd_data_reg[189] ,\n \\not_strict_mode.app_rd_data_reg[187] ,\n \\not_strict_mode.app_rd_data_reg[197] ,\n \\not_strict_mode.app_rd_data_reg[195] ,\n \\not_strict_mode.app_rd_data_reg[193] ,\n \\not_strict_mode.app_rd_data_reg[203] ,\n \\not_strict_mode.app_rd_data_reg[201] ,\n \\not_strict_mode.app_rd_data_reg[199] ,\n \\not_strict_mode.app_rd_data_reg[209] ,\n \\not_strict_mode.app_rd_data_reg[207] ,\n \\not_strict_mode.app_rd_data_reg[205] ,\n \\not_strict_mode.app_rd_data_reg[215] ,\n \\not_strict_mode.app_rd_data_reg[213] ,\n \\not_strict_mode.app_rd_data_reg[211] ,\n \\not_strict_mode.app_rd_data_reg[221] ,\n \\not_strict_mode.app_rd_data_reg[219] ,\n \\not_strict_mode.app_rd_data_reg[217] ,\n \\not_strict_mode.app_rd_data_reg[227] ,\n \\not_strict_mode.app_rd_data_reg[225] ,\n \\not_strict_mode.app_rd_data_reg[223] ,\n \\not_strict_mode.app_rd_data_reg[233] ,\n \\not_strict_mode.app_rd_data_reg[231] ,\n \\not_strict_mode.app_rd_data_reg[229] ,\n \\not_strict_mode.app_rd_data_reg[239] ,\n \\not_strict_mode.app_rd_data_reg[237] ,\n \\not_strict_mode.app_rd_data_reg[235] ,\n \\not_strict_mode.app_rd_data_reg[245] ,\n \\not_strict_mode.app_rd_data_reg[243] ,\n \\not_strict_mode.app_rd_data_reg[241] ,\n \\not_strict_mode.app_rd_data_reg[251] ,\n \\not_strict_mode.app_rd_data_reg[249] ,\n \\not_strict_mode.app_rd_data_reg[247] ,\n \\not_strict_mode.app_rd_data_reg[255] ,\n \\not_strict_mode.app_rd_data_reg[253] ,\n app_rdy,\n app_en_r1,\n app_hi_pri_r2,\n hi_priority,\n ram_init_done_r,\n app_wdf_rdy,\n app_rd_data_valid,\n \\app_cmd_r2_reg[0] ,\n rb_hit_busy_r_reg,\n \\req_bank_r_lcl_reg[2] ,\n rb_hit_busy_r_reg_0,\n rb_hit_busy_r_reg_1,\n rb_hit_busy_r_reg_2,\n use_addr,\n \\req_data_buf_addr_r_reg[4] ,\n \\app_cmd_r2_reg[1] ,\n \\req_row_r_lcl_reg[14] ,\n \\req_col_r_reg[9] ,\n \\my_empty_reg[7] ,\n \\s_axi_rdata[255] ,\n CLK,\n pointer_we,\n \\cmd_pipe_plus.wr_data_addr_reg[3] ,\n rd_buf_we,\n DIA,\n DIB,\n DIC,\n \\read_fifo.fifo_out_data_r_reg[7] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ,\n app_en_ns1,\n E,\n app_rd_data_end_ns,\n reset_reg,\n mc_app_cmd,\n req_bank_r,\n mc_app_wdf_wren_reg,\n w_cmd_rdy,\n D,\n mc_app_wdf_mask_reg,\n wready_reg_rep__1,\n mc_app_wdf_data_reg,\n accept_ns,\n bypass__0,\n app_rdy_r_reg,\n \\axaddr_incr_reg[29] ,\n app_wdf_data,\n app_wdf_mask,\n \\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 );\n output [0:0]\\not_strict_mode.app_rd_data_end_reg ;\n output [4:0]Q;\n output [1:0]DOA;\n output [1:0]DOB;\n output [1:0]DOC;\n output [1:0]\\not_strict_mode.app_rd_data_reg[11] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[9] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[7] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[17] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[15] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[13] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[23] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[21] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[19] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[29] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[27] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[25] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[35] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[33] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[31] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[41] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[39] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[37] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[47] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[45] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[43] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[53] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[51] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[49] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[59] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[57] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[55] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[65] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[63] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[61] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[71] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[69] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[67] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[77] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[75] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[73] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[83] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[81] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[79] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[89] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[87] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[85] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[95] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[93] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[91] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[101] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[99] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[97] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[107] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[105] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[103] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[113] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[111] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[109] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[119] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[117] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[115] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[125] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[123] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[121] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[131] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[129] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[127] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[137] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[135] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[133] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[143] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[141] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[139] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[149] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[147] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[145] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[155] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[153] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[151] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[161] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[159] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[157] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[167] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[165] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[163] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[173] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[171] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[169] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[179] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[177] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[175] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[185] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[183] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[181] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[191] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[189] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[187] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[197] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[195] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[193] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[203] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[201] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[199] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[209] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[207] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[205] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[215] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[213] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[211] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[221] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[219] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[217] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[227] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[225] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[223] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[233] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[231] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[229] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[239] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[237] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[235] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[245] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[243] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[241] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[251] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[249] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[247] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[255] ;\n output [1:0]\\not_strict_mode.app_rd_data_reg[253] ;\n output app_rdy;\n output app_en_r1;\n output app_hi_pri_r2;\n output hi_priority;\n output ram_init_done_r;\n output app_wdf_rdy;\n output app_rd_data_valid;\n output \\app_cmd_r2_reg[0] ;\n output rb_hit_busy_r_reg;\n output [2:0]\\req_bank_r_lcl_reg[2] ;\n output rb_hit_busy_r_reg_0;\n output rb_hit_busy_r_reg_1;\n output rb_hit_busy_r_reg_2;\n output use_addr;\n output [4:0]\\req_data_buf_addr_r_reg[4] ;\n output [0:0]\\app_cmd_r2_reg[1] ;\n output [14:0]\\req_row_r_lcl_reg[14] ;\n output [6:0]\\req_col_r_reg[9] ;\n output [287:0]\\my_empty_reg[7] ;\n output [255:0]\\s_axi_rdata[255] ;\n input CLK;\n input pointer_we;\n input [3:0]\\cmd_pipe_plus.wr_data_addr_reg[3] ;\n input rd_buf_we;\n input [1:0]DIA;\n input [1:0]DIB;\n input [1:0]DIC;\n input [6:0]\\read_fifo.fifo_out_data_r_reg[7] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ;\n input [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;\n input app_en_ns1;\n input [0:0]E;\n input app_rd_data_end_ns;\n input reset_reg;\n input [0:0]mc_app_cmd;\n input [11:0]req_bank_r;\n input mc_app_wdf_wren_reg;\n input w_cmd_rdy;\n input [31:0]D;\n input [31:0]mc_app_wdf_mask_reg;\n input [255:0]wready_reg_rep__1;\n input [255:0]mc_app_wdf_data_reg;\n input accept_ns;\n input bypass__0;\n input [0:0]app_rdy_r_reg;\n input [24:0]\\axaddr_incr_reg[29] ;\n input [255:0]app_wdf_data;\n input [31:0]app_wdf_mask;\n input [255:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ;\n\n wire CLK;\n wire [31:0]D;\n wire [1:0]DIA;\n wire [1:0]DIB;\n wire [1:0]DIC;\n wire [1:0]DOA;\n wire [1:0]DOB;\n wire [1:0]DOC;\n wire [0:0]E;\n wire [4:0]Q;\n wire accept_ns;\n wire \\app_cmd_r2_reg[0] ;\n wire [0:0]\\app_cmd_r2_reg[1] ;\n wire app_en_ns1;\n wire app_en_r1;\n wire app_hi_pri_r2;\n wire app_rd_data_end_ns;\n wire app_rd_data_valid;\n wire app_rdy;\n wire app_rdy_ns;\n wire [0:0]app_rdy_r_reg;\n wire [255:0]app_wdf_data;\n wire [31:0]app_wdf_mask;\n wire app_wdf_rdy;\n wire [24:0]\\axaddr_incr_reg[29] ;\n wire bypass__0;\n wire [3:0]\\cmd_pipe_plus.wr_data_addr_reg[3] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ;\n wire [255:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;\n wire [1:0]\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ;\n wire hi_priority;\n wire [0:0]mc_app_cmd;\n wire [255:0]mc_app_wdf_data_reg;\n wire [31:0]mc_app_wdf_mask_reg;\n wire mc_app_wdf_wren_reg;\n wire [287:0]\\my_empty_reg[7] ;\n wire [0:0]\\not_strict_mode.app_rd_data_end_reg ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[101] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[103] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[105] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[107] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[109] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[111] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[113] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[115] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[117] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[119] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[11] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[121] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[123] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[125] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[127] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[129] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[131] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[133] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[135] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[137] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[139] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[13] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[141] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[143] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[145] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[147] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[149] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[151] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[153] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[155] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[157] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[159] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[15] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[161] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[163] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[165] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[167] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[169] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[171] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[173] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[175] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[177] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[179] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[17] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[181] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[183] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[185] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[187] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[189] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[191] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[193] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[195] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[197] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[199] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[19] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[201] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[203] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[205] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[207] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[209] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[211] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[213] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[215] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[217] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[219] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[21] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[221] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[223] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[225] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[227] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[229] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[231] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[233] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[235] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[237] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[239] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[23] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[241] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[243] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[245] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[247] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[249] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[251] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[253] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[255] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[25] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[27] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[29] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[31] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[33] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[35] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[37] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[39] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[41] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[43] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[45] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[47] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[49] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[51] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[53] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[55] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[57] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[59] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[61] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[63] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[65] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[67] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[69] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[71] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[73] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[75] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[77] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[79] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[7] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[81] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[83] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[85] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[87] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[89] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[91] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[93] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[95] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[97] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[99] ;\n wire [1:0]\\not_strict_mode.app_rd_data_reg[9] ;\n wire [1:0]occ_cnt_r;\n wire [0:0]p_0_in;\n wire pointer_we;\n wire [3:0]pointer_wr_addr;\n wire [3:0]pointer_wr_data;\n wire ram_init_done_r;\n wire rb_hit_busy_r_reg;\n wire rb_hit_busy_r_reg_0;\n wire rb_hit_busy_r_reg_1;\n wire rb_hit_busy_r_reg_2;\n wire rd_accepted;\n wire rd_buf_we;\n wire [4:0]rd_data_buf_addr_r;\n wire [3:0]\\read_data_indx.rd_data_indx_r_reg__0 ;\n wire [6:0]\\read_fifo.fifo_out_data_r_reg[7] ;\n wire [11:0]req_bank_r;\n wire [2:0]\\req_bank_r_lcl_reg[2] ;\n wire [6:0]\\req_col_r_reg[9] ;\n wire [4:0]\\req_data_buf_addr_r_reg[4] ;\n wire [14:0]\\req_row_r_lcl_reg[14] ;\n wire reset_reg;\n wire [255:0]\\s_axi_rdata[255] ;\n wire ui_cmd0_n_12;\n wire ui_cmd0_n_13;\n wire ui_cmd0_n_15;\n wire ui_rd_data0_n_264;\n wire ui_rd_data0_n_272;\n wire use_addr;\n wire w_cmd_rdy;\n wire wr_accepted;\n wire [3:0]wr_data_buf_addr;\n wire [1:0]wr_req_cnt_r;\n wire [255:0]wready_reg_rep__1;\n\n ddr3_if_mig_7series_v4_0_ui_cmd ui_cmd0\n (.CLK(CLK),\n .E(app_rdy),\n .Q(occ_cnt_r),\n .\\app_cmd_r2_reg[0]_0 (\\app_cmd_r2_reg[0] ),\n .\\app_cmd_r2_reg[1]_0 (\\app_cmd_r2_reg[1] ),\n .app_en_ns1(app_en_ns1),\n .app_en_r1(app_en_r1),\n .app_hi_pri_r2(app_hi_pri_r2),\n .app_rdy_ns(app_rdy_ns),\n .app_rdy_r_reg_0(app_rdy_r_reg),\n .\\axaddr_incr_reg[29] (\\axaddr_incr_reg[29] ),\n .hi_priority(hi_priority),\n .mc_app_cmd(mc_app_cmd),\n .\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (rd_data_buf_addr_r),\n .\\not_strict_mode.occupied_counter.occ_cnt_r_reg[3] (ui_cmd0_n_15),\n .p_0_in(p_0_in),\n .rb_hit_busy_r_reg(rb_hit_busy_r_reg),\n .rb_hit_busy_r_reg_0(rb_hit_busy_r_reg_0),\n .rb_hit_busy_r_reg_1(rb_hit_busy_r_reg_1),\n .rb_hit_busy_r_reg_2(rb_hit_busy_r_reg_2),\n .rd_accepted(rd_accepted),\n .req_bank_r(req_bank_r),\n .\\req_bank_r_lcl_reg[0] (\\req_bank_r_lcl_reg[2] [0]),\n .\\req_bank_r_lcl_reg[1] (\\req_bank_r_lcl_reg[2] [1]),\n .\\req_bank_r_lcl_reg[2] (\\req_bank_r_lcl_reg[2] [2]),\n .\\req_col_r_reg[9] (\\req_col_r_reg[9] ),\n .\\req_data_buf_addr_r_reg[4] (\\req_data_buf_addr_r_reg[4] ),\n .\\req_row_r_lcl_reg[14] (\\req_row_r_lcl_reg[14] ),\n .reset_reg(reset_reg),\n .use_addr(use_addr),\n .wr_accepted(wr_accepted),\n .wr_data_buf_addr(wr_data_buf_addr),\n .wr_req_cnt_r(wr_req_cnt_r),\n .\\wr_req_counter.wr_req_cnt_r_reg[3] (ui_cmd0_n_13),\n .\\wr_req_counter.wr_req_cnt_r_reg[4] (ui_cmd0_n_12));\n ddr3_if_mig_7series_v4_0_ui_rd_data ui_rd_data0\n (.ADDRD(pointer_wr_addr),\n .CLK(CLK),\n .D(ui_rd_data0_n_264),\n .DIA(DIA),\n .DIB(DIB),\n .DIC(DIC),\n .DOA(DOA),\n .DOB(DOB),\n .DOC(DOC),\n .Q(Q),\n .app_rd_data_end_ns(app_rd_data_end_ns),\n .app_rd_data_valid(app_rd_data_valid),\n .bypass__0(bypass__0),\n .\\cmd_pipe_plus.wr_data_addr_reg[3] (\\cmd_pipe_plus.wr_data_addr_reg[3] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_1 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ),\n .\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 (\\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_1 ),\n .\\not_strict_mode.app_rd_data_end_reg_0 (\\not_strict_mode.app_rd_data_end_reg ),\n .\\not_strict_mode.app_rd_data_reg[101]_0 (\\not_strict_mode.app_rd_data_reg[101] ),\n .\\not_strict_mode.app_rd_data_reg[103]_0 (\\not_strict_mode.app_rd_data_reg[103] ),\n .\\not_strict_mode.app_rd_data_reg[105]_0 (\\not_strict_mode.app_rd_data_reg[105] ),\n .\\not_strict_mode.app_rd_data_reg[107]_0 (\\not_strict_mode.app_rd_data_reg[107] ),\n .\\not_strict_mode.app_rd_data_reg[109]_0 (\\not_strict_mode.app_rd_data_reg[109] ),\n .\\not_strict_mode.app_rd_data_reg[111]_0 (\\not_strict_mode.app_rd_data_reg[111] ),\n .\\not_strict_mode.app_rd_data_reg[113]_0 (\\not_strict_mode.app_rd_data_reg[113] ),\n .\\not_strict_mode.app_rd_data_reg[115]_0 (\\not_strict_mode.app_rd_data_reg[115] ),\n .\\not_strict_mode.app_rd_data_reg[117]_0 (\\not_strict_mode.app_rd_data_reg[117] ),\n .\\not_strict_mode.app_rd_data_reg[119]_0 (\\not_strict_mode.app_rd_data_reg[119] ),\n .\\not_strict_mode.app_rd_data_reg[11]_0 (\\not_strict_mode.app_rd_data_reg[11] ),\n .\\not_strict_mode.app_rd_data_reg[121]_0 (\\not_strict_mode.app_rd_data_reg[121] ),\n .\\not_strict_mode.app_rd_data_reg[123]_0 (\\not_strict_mode.app_rd_data_reg[123] ),\n .\\not_strict_mode.app_rd_data_reg[125]_0 (\\not_strict_mode.app_rd_data_reg[125] ),\n .\\not_strict_mode.app_rd_data_reg[127]_0 (\\not_strict_mode.app_rd_data_reg[127] ),\n .\\not_strict_mode.app_rd_data_reg[129]_0 (\\not_strict_mode.app_rd_data_reg[129] ),\n .\\not_strict_mode.app_rd_data_reg[131]_0 (\\not_strict_mode.app_rd_data_reg[131] ),\n .\\not_strict_mode.app_rd_data_reg[133]_0 (\\not_strict_mode.app_rd_data_reg[133] ),\n .\\not_strict_mode.app_rd_data_reg[135]_0 (\\not_strict_mode.app_rd_data_reg[135] ),\n .\\not_strict_mode.app_rd_data_reg[137]_0 (\\not_strict_mode.app_rd_data_reg[137] ),\n .\\not_strict_mode.app_rd_data_reg[139]_0 (\\not_strict_mode.app_rd_data_reg[139] ),\n .\\not_strict_mode.app_rd_data_reg[13]_0 (\\not_strict_mode.app_rd_data_reg[13] ),\n .\\not_strict_mode.app_rd_data_reg[141]_0 (\\not_strict_mode.app_rd_data_reg[141] ),\n .\\not_strict_mode.app_rd_data_reg[143]_0 (\\not_strict_mode.app_rd_data_reg[143] ),\n .\\not_strict_mode.app_rd_data_reg[145]_0 (\\not_strict_mode.app_rd_data_reg[145] ),\n .\\not_strict_mode.app_rd_data_reg[147]_0 (\\not_strict_mode.app_rd_data_reg[147] ),\n .\\not_strict_mode.app_rd_data_reg[149]_0 (\\not_strict_mode.app_rd_data_reg[149] ),\n .\\not_strict_mode.app_rd_data_reg[151]_0 (\\not_strict_mode.app_rd_data_reg[151] ),\n .\\not_strict_mode.app_rd_data_reg[153]_0 (\\not_strict_mode.app_rd_data_reg[153] ),\n .\\not_strict_mode.app_rd_data_reg[155]_0 (\\not_strict_mode.app_rd_data_reg[155] ),\n .\\not_strict_mode.app_rd_data_reg[157]_0 (\\not_strict_mode.app_rd_data_reg[157] ),\n .\\not_strict_mode.app_rd_data_reg[159]_0 (\\not_strict_mode.app_rd_data_reg[159] ),\n .\\not_strict_mode.app_rd_data_reg[15]_0 (\\not_strict_mode.app_rd_data_reg[15] ),\n .\\not_strict_mode.app_rd_data_reg[161]_0 (\\not_strict_mode.app_rd_data_reg[161] ),\n .\\not_strict_mode.app_rd_data_reg[163]_0 (\\not_strict_mode.app_rd_data_reg[163] ),\n .\\not_strict_mode.app_rd_data_reg[165]_0 (\\not_strict_mode.app_rd_data_reg[165] ),\n .\\not_strict_mode.app_rd_data_reg[167]_0 (\\not_strict_mode.app_rd_data_reg[167] ),\n .\\not_strict_mode.app_rd_data_reg[169]_0 (\\not_strict_mode.app_rd_data_reg[169] ),\n .\\not_strict_mode.app_rd_data_reg[171]_0 (\\not_strict_mode.app_rd_data_reg[171] ),\n .\\not_strict_mode.app_rd_data_reg[173]_0 (\\not_strict_mode.app_rd_data_reg[173] ),\n .\\not_strict_mode.app_rd_data_reg[175]_0 (\\not_strict_mode.app_rd_data_reg[175] ),\n .\\not_strict_mode.app_rd_data_reg[177]_0 (\\not_strict_mode.app_rd_data_reg[177] ),\n .\\not_strict_mode.app_rd_data_reg[179]_0 (\\not_strict_mode.app_rd_data_reg[179] ),\n .\\not_strict_mode.app_rd_data_reg[17]_0 (\\not_strict_mode.app_rd_data_reg[17] ),\n .\\not_strict_mode.app_rd_data_reg[181]_0 (\\not_strict_mode.app_rd_data_reg[181] ),\n .\\not_strict_mode.app_rd_data_reg[183]_0 (\\not_strict_mode.app_rd_data_reg[183] ),\n .\\not_strict_mode.app_rd_data_reg[185]_0 (\\not_strict_mode.app_rd_data_reg[185] ),\n .\\not_strict_mode.app_rd_data_reg[187]_0 (\\not_strict_mode.app_rd_data_reg[187] ),\n .\\not_strict_mode.app_rd_data_reg[189]_0 (\\not_strict_mode.app_rd_data_reg[189] ),\n .\\not_strict_mode.app_rd_data_reg[191]_0 (\\not_strict_mode.app_rd_data_reg[191] ),\n .\\not_strict_mode.app_rd_data_reg[193]_0 (\\not_strict_mode.app_rd_data_reg[193] ),\n .\\not_strict_mode.app_rd_data_reg[195]_0 (\\not_strict_mode.app_rd_data_reg[195] ),\n .\\not_strict_mode.app_rd_data_reg[197]_0 (\\not_strict_mode.app_rd_data_reg[197] ),\n .\\not_strict_mode.app_rd_data_reg[199]_0 (\\not_strict_mode.app_rd_data_reg[199] ),\n .\\not_strict_mode.app_rd_data_reg[19]_0 (\\not_strict_mode.app_rd_data_reg[19] ),\n .\\not_strict_mode.app_rd_data_reg[201]_0 (\\not_strict_mode.app_rd_data_reg[201] ),\n .\\not_strict_mode.app_rd_data_reg[203]_0 (\\not_strict_mode.app_rd_data_reg[203] ),\n .\\not_strict_mode.app_rd_data_reg[205]_0 (\\not_strict_mode.app_rd_data_reg[205] ),\n .\\not_strict_mode.app_rd_data_reg[207]_0 (\\not_strict_mode.app_rd_data_reg[207] ),\n .\\not_strict_mode.app_rd_data_reg[209]_0 (\\not_strict_mode.app_rd_data_reg[209] ),\n .\\not_strict_mode.app_rd_data_reg[211]_0 (\\not_strict_mode.app_rd_data_reg[211] ),\n .\\not_strict_mode.app_rd_data_reg[213]_0 (\\not_strict_mode.app_rd_data_reg[213] ),\n .\\not_strict_mode.app_rd_data_reg[215]_0 (\\not_strict_mode.app_rd_data_reg[215] ),\n .\\not_strict_mode.app_rd_data_reg[217]_0 (\\not_strict_mode.app_rd_data_reg[217] ),\n .\\not_strict_mode.app_rd_data_reg[219]_0 (\\not_strict_mode.app_rd_data_reg[219] ),\n .\\not_strict_mode.app_rd_data_reg[21]_0 (\\not_strict_mode.app_rd_data_reg[21] ),\n .\\not_strict_mode.app_rd_data_reg[221]_0 (\\not_strict_mode.app_rd_data_reg[221] ),\n .\\not_strict_mode.app_rd_data_reg[223]_0 (\\not_strict_mode.app_rd_data_reg[223] ),\n .\\not_strict_mode.app_rd_data_reg[225]_0 (\\not_strict_mode.app_rd_data_reg[225] ),\n .\\not_strict_mode.app_rd_data_reg[227]_0 (\\not_strict_mode.app_rd_data_reg[227] ),\n .\\not_strict_mode.app_rd_data_reg[229]_0 (\\not_strict_mode.app_rd_data_reg[229] ),\n .\\not_strict_mode.app_rd_data_reg[231]_0 (\\not_strict_mode.app_rd_data_reg[231] ),\n .\\not_strict_mode.app_rd_data_reg[233]_0 (\\not_strict_mode.app_rd_data_reg[233] ),\n .\\not_strict_mode.app_rd_data_reg[235]_0 (\\not_strict_mode.app_rd_data_reg[235] ),\n .\\not_strict_mode.app_rd_data_reg[237]_0 (\\not_strict_mode.app_rd_data_reg[237] ),\n .\\not_strict_mode.app_rd_data_reg[239]_0 (\\not_strict_mode.app_rd_data_reg[239] ),\n .\\not_strict_mode.app_rd_data_reg[23]_0 (\\not_strict_mode.app_rd_data_reg[23] ),\n .\\not_strict_mode.app_rd_data_reg[241]_0 (\\not_strict_mode.app_rd_data_reg[241] ),\n .\\not_strict_mode.app_rd_data_reg[243]_0 (\\not_strict_mode.app_rd_data_reg[243] ),\n .\\not_strict_mode.app_rd_data_reg[245]_0 (\\not_strict_mode.app_rd_data_reg[245] ),\n .\\not_strict_mode.app_rd_data_reg[247]_0 (\\not_strict_mode.app_rd_data_reg[247] ),\n .\\not_strict_mode.app_rd_data_reg[249]_0 (\\not_strict_mode.app_rd_data_reg[249] ),\n .\\not_strict_mode.app_rd_data_reg[251]_0 (\\not_strict_mode.app_rd_data_reg[251] ),\n .\\not_strict_mode.app_rd_data_reg[253]_0 (\\not_strict_mode.app_rd_data_reg[253] ),\n .\\not_strict_mode.app_rd_data_reg[255]_0 (\\not_strict_mode.app_rd_data_reg[255] ),\n .\\not_strict_mode.app_rd_data_reg[25]_0 (\\not_strict_mode.app_rd_data_reg[25] ),\n .\\not_strict_mode.app_rd_data_reg[27]_0 (\\not_strict_mode.app_rd_data_reg[27] ),\n .\\not_strict_mode.app_rd_data_reg[29]_0 (\\not_strict_mode.app_rd_data_reg[29] ),\n .\\not_strict_mode.app_rd_data_reg[31]_0 (\\not_strict_mode.app_rd_data_reg[31] ),\n .\\not_strict_mode.app_rd_data_reg[33]_0 (\\not_strict_mode.app_rd_data_reg[33] ),\n .\\not_strict_mode.app_rd_data_reg[35]_0 (\\not_strict_mode.app_rd_data_reg[35] ),\n .\\not_strict_mode.app_rd_data_reg[37]_0 (\\not_strict_mode.app_rd_data_reg[37] ),\n .\\not_strict_mode.app_rd_data_reg[39]_0 (\\not_strict_mode.app_rd_data_reg[39] ),\n .\\not_strict_mode.app_rd_data_reg[41]_0 (\\not_strict_mode.app_rd_data_reg[41] ),\n .\\not_strict_mode.app_rd_data_reg[43]_0 (\\not_strict_mode.app_rd_data_reg[43] ),\n .\\not_strict_mode.app_rd_data_reg[45]_0 (\\not_strict_mode.app_rd_data_reg[45] ),\n .\\not_strict_mode.app_rd_data_reg[47]_0 (\\not_strict_mode.app_rd_data_reg[47] ),\n .\\not_strict_mode.app_rd_data_reg[49]_0 (\\not_strict_mode.app_rd_data_reg[49] ),\n .\\not_strict_mode.app_rd_data_reg[51]_0 (\\not_strict_mode.app_rd_data_reg[51] ),\n .\\not_strict_mode.app_rd_data_reg[53]_0 (\\not_strict_mode.app_rd_data_reg[53] ),\n .\\not_strict_mode.app_rd_data_reg[55]_0 (\\not_strict_mode.app_rd_data_reg[55] ),\n .\\not_strict_mode.app_rd_data_reg[57]_0 (\\not_strict_mode.app_rd_data_reg[57] ),\n .\\not_strict_mode.app_rd_data_reg[59]_0 (\\not_strict_mode.app_rd_data_reg[59] ),\n .\\not_strict_mode.app_rd_data_reg[61]_0 (\\not_strict_mode.app_rd_data_reg[61] ),\n .\\not_strict_mode.app_rd_data_reg[63]_0 (\\not_strict_mode.app_rd_data_reg[63] ),\n .\\not_strict_mode.app_rd_data_reg[65]_0 (\\not_strict_mode.app_rd_data_reg[65] ),\n .\\not_strict_mode.app_rd_data_reg[67]_0 (\\not_strict_mode.app_rd_data_reg[67] ),\n .\\not_strict_mode.app_rd_data_reg[69]_0 (\\not_strict_mode.app_rd_data_reg[69] ),\n .\\not_strict_mode.app_rd_data_reg[71]_0 (\\not_strict_mode.app_rd_data_reg[71] ),\n .\\not_strict_mode.app_rd_data_reg[73]_0 (\\not_strict_mode.app_rd_data_reg[73] ),\n .\\not_strict_mode.app_rd_data_reg[75]_0 (\\not_strict_mode.app_rd_data_reg[75] ),\n .\\not_strict_mode.app_rd_data_reg[77]_0 (\\not_strict_mode.app_rd_data_reg[77] ),\n .\\not_strict_mode.app_rd_data_reg[79]_0 (\\not_strict_mode.app_rd_data_reg[79] ),\n .\\not_strict_mode.app_rd_data_reg[7]_0 (\\not_strict_mode.app_rd_data_reg[7] ),\n .\\not_strict_mode.app_rd_data_reg[81]_0 (\\not_strict_mode.app_rd_data_reg[81] ),\n .\\not_strict_mode.app_rd_data_reg[83]_0 (\\not_strict_mode.app_rd_data_reg[83] ),\n .\\not_strict_mode.app_rd_data_reg[85]_0 (\\not_strict_mode.app_rd_data_reg[85] ),\n .\\not_strict_mode.app_rd_data_reg[87]_0 (\\not_strict_mode.app_rd_data_reg[87] ),\n .\\not_strict_mode.app_rd_data_reg[89]_0 (\\not_strict_mode.app_rd_data_reg[89] ),\n .\\not_strict_mode.app_rd_data_reg[91]_0 (\\not_strict_mode.app_rd_data_reg[91] ),\n .\\not_strict_mode.app_rd_data_reg[93]_0 (\\not_strict_mode.app_rd_data_reg[93] ),\n .\\not_strict_mode.app_rd_data_reg[95]_0 (\\not_strict_mode.app_rd_data_reg[95] ),\n .\\not_strict_mode.app_rd_data_reg[97]_0 (\\not_strict_mode.app_rd_data_reg[97] ),\n .\\not_strict_mode.app_rd_data_reg[99]_0 (\\not_strict_mode.app_rd_data_reg[99] ),\n .\\not_strict_mode.app_rd_data_reg[9]_0 (\\not_strict_mode.app_rd_data_reg[9] ),\n .\\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 (rd_data_buf_addr_r),\n .\\not_strict_mode.occupied_counter.occ_cnt_r_reg[1]_0 (ui_cmd0_n_15),\n .\\not_strict_mode.occupied_counter.occ_cnt_r_reg[3]_0 (occ_cnt_r),\n .\\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]_0 (ram_init_done_r),\n .pointer_wr_data(pointer_wr_data),\n .rd_accepted(rd_accepted),\n .\\rd_buf_indx.ram_init_done_r_lcl_reg_0 (ui_rd_data0_n_272),\n .rd_buf_we(rd_buf_we),\n .\\read_data_indx.rd_data_indx_r_reg[3] (\\read_data_indx.rd_data_indx_r_reg__0 ),\n .\\read_fifo.fifo_out_data_r_reg[7] (\\read_fifo.fifo_out_data_r_reg[7] ),\n .reset_reg(reset_reg),\n .\\s_axi_rdata[255] (\\s_axi_rdata[255] ));\n ddr3_if_mig_7series_v4_0_ui_wr_data ui_wr_data0\n (.ADDRD(pointer_wr_addr),\n .CLK(CLK),\n .D(D),\n .E(E),\n .Q(\\read_data_indx.rd_data_indx_r_reg__0 ),\n .accept_ns(accept_ns),\n .app_rdy_ns(app_rdy_ns),\n .app_wdf_data(app_wdf_data),\n .app_wdf_mask(app_wdf_mask),\n .\\cmd_pipe_plus.wr_data_addr_reg[3] (\\cmd_pipe_plus.wr_data_addr_reg[3] ),\n .mc_app_wdf_data_reg(mc_app_wdf_data_reg),\n .mc_app_wdf_mask_reg(mc_app_wdf_mask_reg),\n .\\mc_app_wdf_mask_reg_reg[0] (app_wdf_rdy),\n .mc_app_wdf_wren_reg(mc_app_wdf_wren_reg),\n .\\my_empty_reg[7] (\\my_empty_reg[7] ),\n .\\not_strict_mode.occupied_counter.occ_cnt_r_reg[4] (ui_rd_data0_n_264),\n .p_0_in(p_0_in),\n .pointer_we(pointer_we),\n .pointer_wr_data(pointer_wr_data),\n .ram_init_done_r(ram_init_done_r),\n .\\rd_buf_indx.ram_init_done_r_lcl_reg (ui_rd_data0_n_272),\n .\\read_data_indx.rd_data_upd_indx_r_reg_0 (ui_cmd0_n_12),\n .reset_reg(reset_reg),\n .w_cmd_rdy(w_cmd_rdy),\n .wr_accepted(wr_accepted),\n .wr_data_buf_addr(wr_data_buf_addr),\n .\\wr_req_counter.wr_req_cnt_r_reg[1]_0 (wr_req_cnt_r),\n .\\wr_req_counter.wr_req_cnt_r_reg[1]_1 (ui_cmd0_n_13),\n .wready_reg_rep__1(wready_reg_rep__1));\nendmodule\n\nmodule ddr3_if_mig_7series_v4_0_ui_wr_data\n (wr_data_buf_addr,\n p_0_in,\n \\mc_app_wdf_mask_reg_reg[0] ,\n app_rdy_ns,\n \\wr_req_counter.wr_req_cnt_r_reg[1]_0 ,\n Q,\n \\my_empty_reg[7] ,\n CLK,\n pointer_we,\n pointer_wr_data,\n ADDRD,\n \\cmd_pipe_plus.wr_data_addr_reg[3] ,\n E,\n mc_app_wdf_wren_reg,\n w_cmd_rdy,\n reset_reg,\n D,\n mc_app_wdf_mask_reg,\n wready_reg_rep__1,\n mc_app_wdf_data_reg,\n \\not_strict_mode.occupied_counter.occ_cnt_r_reg[4] ,\n accept_ns,\n wr_accepted,\n \\wr_req_counter.wr_req_cnt_r_reg[1]_1 ,\n \\read_data_indx.rd_data_upd_indx_r_reg_0 ,\n \\rd_buf_indx.ram_init_done_r_lcl_reg ,\n ram_init_done_r,\n app_wdf_data,\n app_wdf_mask);\n output [3:0]wr_data_buf_addr;\n output [0:0]p_0_in;\n output \\mc_app_wdf_mask_reg_reg[0] ;\n output app_rdy_ns;\n output [1:0]\\wr_req_counter.wr_req_cnt_r_reg[1]_0 ;\n output [3:0]Q;\n output [287:0]\\my_empty_reg[7] ;\n input CLK;\n input pointer_we;\n input [3:0]pointer_wr_data;\n input [3:0]ADDRD;\n input [3:0]\\cmd_pipe_plus.wr_data_addr_reg[3] ;\n input [0:0]E;\n input mc_app_wdf_wren_reg;\n input w_cmd_rdy;\n input reset_reg;\n input [31:0]D;\n input [31:0]mc_app_wdf_mask_reg;\n input [255:0]wready_reg_rep__1;\n input [255:0]mc_app_wdf_data_reg;\n input [0:0]\\not_strict_mode.occupied_counter.occ_cnt_r_reg[4] ;\n input accept_ns;\n input wr_accepted;\n input \\wr_req_counter.wr_req_cnt_r_reg[1]_1 ;\n input \\read_data_indx.rd_data_upd_indx_r_reg_0 ;\n input \\rd_buf_indx.ram_init_done_r_lcl_reg ;\n input ram_init_done_r;\n input [255:0]app_wdf_data;\n input [31:0]app_wdf_mask;\n\n wire [3:0]ADDRD;\n wire CLK;\n wire [31:0]D;\n wire [0:0]E;\n wire [3:0]Q;\n wire accept_ns;\n wire app_rdy_ns;\n wire app_rdy_r_i_2_n_0;\n wire app_rdy_r_i_3_n_0;\n wire [255:0]app_wdf_data;\n wire [255:0]app_wdf_data_r1;\n wire app_wdf_end_ns1;\n wire app_wdf_end_r1;\n wire [31:0]app_wdf_mask;\n wire [31:0]app_wdf_mask_r1;\n wire app_wdf_rdy_r_copy1;\n wire app_wdf_rdy_r_copy2;\n wire app_wdf_rdy_r_copy3;\n wire app_wdf_wren_ns1;\n wire app_wdf_wren_r1;\n wire [3:0]\\cmd_pipe_plus.wr_data_addr_reg[3] ;\n wire [3:0]\\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 ;\n wire [255:0]mc_app_wdf_data_reg;\n wire [31:0]mc_app_wdf_mask_reg;\n wire \\mc_app_wdf_mask_reg_reg[0] ;\n wire mc_app_wdf_wren_reg;\n wire [287:0]\\my_empty_reg[7] ;\n wire [0:0]\\not_strict_mode.occupied_counter.occ_cnt_r_reg[4] ;\n wire \\occupied_counter.occ_cnt[0]_i_1_n_0 ;\n wire \\occupied_counter.occ_cnt[10]_i_1_n_0 ;\n wire \\occupied_counter.occ_cnt[11]_i_1_n_0 ;\n wire \\occupied_counter.occ_cnt[12]_i_1_n_0 ;\n wire \\occupied_counter.occ_cnt[13]_i_1_n_0 ;\n wire \\occupied_counter.occ_cnt[14]_i_1_n_0 ;\n wire \\occupied_counter.occ_cnt[15]_i_1_n_0 ;\n wire \\occupied_counter.occ_cnt[15]_i_2_n_0 ;\n wire \\occupied_counter.occ_cnt[1]_i_1_n_0 ;\n wire \\occupied_counter.occ_cnt[2]_i_1_n_0 ;\n wire \\occupied_counter.occ_cnt[3]_i_1_n_0 ;\n wire \\occupied_counter.occ_cnt[4]_i_1_n_0 ;\n wire \\occupied_counter.occ_cnt[5]_i_1_n_0 ;\n wire \\occupied_counter.occ_cnt[6]_i_1_n_0 ;\n wire \\occupied_counter.occ_cnt[7]_i_1_n_0 ;\n wire \\occupied_counter.occ_cnt[8]_i_1_n_0 ;\n wire \\occupied_counter.occ_cnt[9]_i_1_n_0 ;\n wire \\occupied_counter.occ_cnt_reg_n_0_[0] ;\n wire \\occupied_counter.occ_cnt_reg_n_0_[10] ;\n wire \\occupied_counter.occ_cnt_reg_n_0_[11] ;\n wire \\occupied_counter.occ_cnt_reg_n_0_[12] ;\n wire \\occupied_counter.occ_cnt_reg_n_0_[13] ;\n wire \\occupied_counter.occ_cnt_reg_n_0_[15] ;\n wire \\occupied_counter.occ_cnt_reg_n_0_[1] ;\n wire \\occupied_counter.occ_cnt_reg_n_0_[2] ;\n wire \\occupied_counter.occ_cnt_reg_n_0_[3] ;\n wire \\occupied_counter.occ_cnt_reg_n_0_[4] ;\n wire \\occupied_counter.occ_cnt_reg_n_0_[5] ;\n wire \\occupied_counter.occ_cnt_reg_n_0_[6] ;\n wire \\occupied_counter.occ_cnt_reg_n_0_[7] ;\n wire \\occupied_counter.occ_cnt_reg_n_0_[8] ;\n wire \\occupied_counter.occ_cnt_reg_n_0_[9] ;\n wire [0:0]p_0_in;\n wire [3:0]p_0_in__0;\n wire [1:1]p_0_in__0_0;\n wire [3:0]p_0_in__0__0;\n wire [3:0]p_0_in__1;\n wire p_4_in;\n wire pointer_we;\n wire [3:0]pointer_wr_data;\n wire ram_init_done_r;\n wire \\rd_buf_indx.ram_init_done_r_lcl_reg ;\n wire \\read_data_indx.rd_data_upd_indx_r_reg_0 ;\n wire reset_reg;\n wire w_cmd_rdy;\n wire wb_wr_data_addr0_ns;\n wire wb_wr_data_addr0_r;\n wire [4:1]wb_wr_data_addr_r;\n wire [4:1]wb_wr_data_addr_w;\n wire wdf_rdy_ns;\n wire wr_accepted;\n wire [287:0]wr_buf_in_data;\n wire [287:0]wr_buf_out_data_w;\n wire wr_data_addr_le;\n wire [3:0]wr_data_buf_addr;\n wire [3:0]wr_data_pntr;\n wire [4:2]wr_req_cnt_r;\n wire \\wr_req_counter.wr_req_cnt_r[0]_i_1_n_0 ;\n wire \\wr_req_counter.wr_req_cnt_r[1]_i_1_n_0 ;\n wire \\wr_req_counter.wr_req_cnt_r[2]_i_1_n_0 ;\n wire \\wr_req_counter.wr_req_cnt_r[3]_i_1_n_0 ;\n wire \\wr_req_counter.wr_req_cnt_r[4]_i_1_n_0 ;\n wire \\wr_req_counter.wr_req_cnt_r[4]_i_2_n_0 ;\n wire [1:0]\\wr_req_counter.wr_req_cnt_r_reg[1]_0 ;\n wire \\wr_req_counter.wr_req_cnt_r_reg[1]_1 ;\n wire [255:0]wready_reg_rep__1;\n wire [3:0]\\write_data_control.wr_data_indx_r_reg__0 ;\n wire [1:0]\\NLW_pointer_ram.rams[0].RAM32M0_DOA_UNCONNECTED ;\n wire [1:0]\\NLW_pointer_ram.rams[0].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_pointer_ram.rams[1].RAM32M0_DOA_UNCONNECTED ;\n wire [1:0]\\NLW_pointer_ram.rams[1].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[0].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[10].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[11].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[12].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[13].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[14].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[15].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[16].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[17].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[18].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[19].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[1].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[20].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[21].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[22].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[23].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[24].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[25].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[26].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[27].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[28].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[29].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[2].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[30].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[31].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[32].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[33].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[34].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[35].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[36].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[37].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[38].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[39].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[3].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[40].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[41].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[42].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[43].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[44].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[45].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[46].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[47].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[4].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[5].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[6].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[7].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[8].RAM32M0_DOD_UNCONNECTED ;\n wire [1:0]\\NLW_write_buffer.wr_buffer_ram[9].RAM32M0_DOD_UNCONNECTED ;\n\n LUT5 #(\n .INIT(32'h44440444)) \n app_rdy_r_i_1\n (.I0(\\not_strict_mode.occupied_counter.occ_cnt_r_reg[4] ),\n .I1(accept_ns),\n .I2(app_rdy_r_i_2_n_0),\n .I3(app_rdy_r_i_3_n_0),\n .I4(\\wr_req_counter.wr_req_cnt_r[3]_i_1_n_0 ),\n .O(app_rdy_ns));\n LUT6 #(\n .INIT(64'hFFFF00007FFE8001)) \n app_rdy_r_i_2\n (.I0(wr_req_cnt_r[3]),\n .I1(wr_req_cnt_r[2]),\n .I2(\\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]),\n .I3(\\wr_req_counter.wr_req_cnt_r_reg[1]_1 ),\n .I4(wr_req_cnt_r[4]),\n .I5(\\read_data_indx.rd_data_upd_indx_r_reg_0 ),\n .O(app_rdy_r_i_2_n_0));\n LUT6 #(\n .INIT(64'h0040010000001001)) \n app_rdy_r_i_3\n (.I0(reset_reg),\n .I1(wr_req_cnt_r[2]),\n .I2(wr_accepted),\n .I3(p_0_in),\n .I4(\\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]),\n .I5(\\wr_req_counter.wr_req_cnt_r_reg[1]_0 [0]),\n .O(app_rdy_r_i_3_n_0));\n FDRE \\app_wdf_data_r1_reg[0] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[0]),\n .Q(app_wdf_data_r1[0]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[100] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[100]),\n .Q(app_wdf_data_r1[100]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[101] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[101]),\n .Q(app_wdf_data_r1[101]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[102] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[102]),\n .Q(app_wdf_data_r1[102]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[103] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[103]),\n .Q(app_wdf_data_r1[103]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[104] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[104]),\n .Q(app_wdf_data_r1[104]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[105] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[105]),\n .Q(app_wdf_data_r1[105]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[106] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[106]),\n .Q(app_wdf_data_r1[106]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[107] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[107]),\n .Q(app_wdf_data_r1[107]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[108] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[108]),\n .Q(app_wdf_data_r1[108]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[109] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[109]),\n .Q(app_wdf_data_r1[109]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[10] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[10]),\n .Q(app_wdf_data_r1[10]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[110] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[110]),\n .Q(app_wdf_data_r1[110]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[111] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[111]),\n .Q(app_wdf_data_r1[111]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[112] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[112]),\n .Q(app_wdf_data_r1[112]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[113] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[113]),\n .Q(app_wdf_data_r1[113]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[114] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[114]),\n .Q(app_wdf_data_r1[114]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[115] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[115]),\n .Q(app_wdf_data_r1[115]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[116] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[116]),\n .Q(app_wdf_data_r1[116]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[117] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[117]),\n .Q(app_wdf_data_r1[117]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[118] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[118]),\n .Q(app_wdf_data_r1[118]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[119] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[119]),\n .Q(app_wdf_data_r1[119]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[11] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[11]),\n .Q(app_wdf_data_r1[11]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[120] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[120]),\n .Q(app_wdf_data_r1[120]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[121] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[121]),\n .Q(app_wdf_data_r1[121]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[122] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[122]),\n .Q(app_wdf_data_r1[122]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[123] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[123]),\n .Q(app_wdf_data_r1[123]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[124] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[124]),\n .Q(app_wdf_data_r1[124]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[125] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[125]),\n .Q(app_wdf_data_r1[125]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[126] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[126]),\n .Q(app_wdf_data_r1[126]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[127] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[127]),\n .Q(app_wdf_data_r1[127]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[128] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[128]),\n .Q(app_wdf_data_r1[128]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[129] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[129]),\n .Q(app_wdf_data_r1[129]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[12] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[12]),\n .Q(app_wdf_data_r1[12]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[130] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[130]),\n .Q(app_wdf_data_r1[130]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[131] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[131]),\n .Q(app_wdf_data_r1[131]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[132] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[132]),\n .Q(app_wdf_data_r1[132]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[133] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[133]),\n .Q(app_wdf_data_r1[133]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[134] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[134]),\n .Q(app_wdf_data_r1[134]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[135] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[135]),\n .Q(app_wdf_data_r1[135]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[136] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[136]),\n .Q(app_wdf_data_r1[136]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[137] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[137]),\n .Q(app_wdf_data_r1[137]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[138] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[138]),\n .Q(app_wdf_data_r1[138]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[139] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[139]),\n .Q(app_wdf_data_r1[139]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[13] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[13]),\n .Q(app_wdf_data_r1[13]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[140] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[140]),\n .Q(app_wdf_data_r1[140]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[141] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[141]),\n .Q(app_wdf_data_r1[141]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[142] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[142]),\n .Q(app_wdf_data_r1[142]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[143] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[143]),\n .Q(app_wdf_data_r1[143]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[144] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[144]),\n .Q(app_wdf_data_r1[144]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[145] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[145]),\n .Q(app_wdf_data_r1[145]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[146] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[146]),\n .Q(app_wdf_data_r1[146]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[147] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[147]),\n .Q(app_wdf_data_r1[147]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[148] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[148]),\n .Q(app_wdf_data_r1[148]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[149] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[149]),\n .Q(app_wdf_data_r1[149]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[14] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[14]),\n .Q(app_wdf_data_r1[14]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[150] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[150]),\n .Q(app_wdf_data_r1[150]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[151] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[151]),\n .Q(app_wdf_data_r1[151]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[152] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[152]),\n .Q(app_wdf_data_r1[152]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[153] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[153]),\n .Q(app_wdf_data_r1[153]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[154] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[154]),\n .Q(app_wdf_data_r1[154]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[155] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[155]),\n .Q(app_wdf_data_r1[155]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[156] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[156]),\n .Q(app_wdf_data_r1[156]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[157] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[157]),\n .Q(app_wdf_data_r1[157]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[158] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[158]),\n .Q(app_wdf_data_r1[158]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[159] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[159]),\n .Q(app_wdf_data_r1[159]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[15] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[15]),\n .Q(app_wdf_data_r1[15]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[160] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[160]),\n .Q(app_wdf_data_r1[160]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[161] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[161]),\n .Q(app_wdf_data_r1[161]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[162] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[162]),\n .Q(app_wdf_data_r1[162]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[163] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[163]),\n .Q(app_wdf_data_r1[163]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[164] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[164]),\n .Q(app_wdf_data_r1[164]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[165] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[165]),\n .Q(app_wdf_data_r1[165]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[166] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[166]),\n .Q(app_wdf_data_r1[166]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[167] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[167]),\n .Q(app_wdf_data_r1[167]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[168] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[168]),\n .Q(app_wdf_data_r1[168]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[169] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[169]),\n .Q(app_wdf_data_r1[169]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[16] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[16]),\n .Q(app_wdf_data_r1[16]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[170] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[170]),\n .Q(app_wdf_data_r1[170]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[171] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[171]),\n .Q(app_wdf_data_r1[171]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[172] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[172]),\n .Q(app_wdf_data_r1[172]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[173] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[173]),\n .Q(app_wdf_data_r1[173]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[174] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[174]),\n .Q(app_wdf_data_r1[174]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[175] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[175]),\n .Q(app_wdf_data_r1[175]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[176] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[176]),\n .Q(app_wdf_data_r1[176]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[177] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[177]),\n .Q(app_wdf_data_r1[177]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[178] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[178]),\n .Q(app_wdf_data_r1[178]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[179] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[179]),\n .Q(app_wdf_data_r1[179]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[17] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[17]),\n .Q(app_wdf_data_r1[17]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[180] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[180]),\n .Q(app_wdf_data_r1[180]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[181] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[181]),\n .Q(app_wdf_data_r1[181]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[182] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[182]),\n .Q(app_wdf_data_r1[182]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[183] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[183]),\n .Q(app_wdf_data_r1[183]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[184] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[184]),\n .Q(app_wdf_data_r1[184]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[185] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[185]),\n .Q(app_wdf_data_r1[185]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[186] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[186]),\n .Q(app_wdf_data_r1[186]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[187] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[187]),\n .Q(app_wdf_data_r1[187]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[188] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[188]),\n .Q(app_wdf_data_r1[188]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[189] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[189]),\n .Q(app_wdf_data_r1[189]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[18] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[18]),\n .Q(app_wdf_data_r1[18]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[190] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[190]),\n .Q(app_wdf_data_r1[190]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[191] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[191]),\n .Q(app_wdf_data_r1[191]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[192] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[192]),\n .Q(app_wdf_data_r1[192]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[193] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[193]),\n .Q(app_wdf_data_r1[193]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[194] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[194]),\n .Q(app_wdf_data_r1[194]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[195] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[195]),\n .Q(app_wdf_data_r1[195]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[196] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[196]),\n .Q(app_wdf_data_r1[196]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[197] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[197]),\n .Q(app_wdf_data_r1[197]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[198] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[198]),\n .Q(app_wdf_data_r1[198]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[199] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[199]),\n .Q(app_wdf_data_r1[199]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[19] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[19]),\n .Q(app_wdf_data_r1[19]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[1] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[1]),\n .Q(app_wdf_data_r1[1]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[200] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[200]),\n .Q(app_wdf_data_r1[200]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[201] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[201]),\n .Q(app_wdf_data_r1[201]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[202] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[202]),\n .Q(app_wdf_data_r1[202]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[203] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[203]),\n .Q(app_wdf_data_r1[203]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[204] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[204]),\n .Q(app_wdf_data_r1[204]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[205] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[205]),\n .Q(app_wdf_data_r1[205]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[206] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[206]),\n .Q(app_wdf_data_r1[206]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[207] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[207]),\n .Q(app_wdf_data_r1[207]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[208] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[208]),\n .Q(app_wdf_data_r1[208]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[209] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[209]),\n .Q(app_wdf_data_r1[209]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[20] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[20]),\n .Q(app_wdf_data_r1[20]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[210] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[210]),\n .Q(app_wdf_data_r1[210]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[211] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[211]),\n .Q(app_wdf_data_r1[211]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[212] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[212]),\n .Q(app_wdf_data_r1[212]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[213] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[213]),\n .Q(app_wdf_data_r1[213]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[214] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[214]),\n .Q(app_wdf_data_r1[214]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[215] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[215]),\n .Q(app_wdf_data_r1[215]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[216] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[216]),\n .Q(app_wdf_data_r1[216]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[217] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[217]),\n .Q(app_wdf_data_r1[217]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[218] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[218]),\n .Q(app_wdf_data_r1[218]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[219] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[219]),\n .Q(app_wdf_data_r1[219]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[21] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[21]),\n .Q(app_wdf_data_r1[21]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[220] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[220]),\n .Q(app_wdf_data_r1[220]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[221] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[221]),\n .Q(app_wdf_data_r1[221]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[222] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[222]),\n .Q(app_wdf_data_r1[222]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[223] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[223]),\n .Q(app_wdf_data_r1[223]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[224] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[224]),\n .Q(app_wdf_data_r1[224]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[225] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[225]),\n .Q(app_wdf_data_r1[225]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[226] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[226]),\n .Q(app_wdf_data_r1[226]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[227] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[227]),\n .Q(app_wdf_data_r1[227]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[228] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[228]),\n .Q(app_wdf_data_r1[228]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[229] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[229]),\n .Q(app_wdf_data_r1[229]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[22] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[22]),\n .Q(app_wdf_data_r1[22]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[230] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[230]),\n .Q(app_wdf_data_r1[230]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[231] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[231]),\n .Q(app_wdf_data_r1[231]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[232] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[232]),\n .Q(app_wdf_data_r1[232]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[233] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[233]),\n .Q(app_wdf_data_r1[233]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[234] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[234]),\n .Q(app_wdf_data_r1[234]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[235] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[235]),\n .Q(app_wdf_data_r1[235]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[236] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[236]),\n .Q(app_wdf_data_r1[236]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[237] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[237]),\n .Q(app_wdf_data_r1[237]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[238] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[238]),\n .Q(app_wdf_data_r1[238]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[239] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[239]),\n .Q(app_wdf_data_r1[239]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[23] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[23]),\n .Q(app_wdf_data_r1[23]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[240] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[240]),\n .Q(app_wdf_data_r1[240]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[241] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[241]),\n .Q(app_wdf_data_r1[241]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[242] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[242]),\n .Q(app_wdf_data_r1[242]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[243] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[243]),\n .Q(app_wdf_data_r1[243]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[244] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[244]),\n .Q(app_wdf_data_r1[244]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[245] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[245]),\n .Q(app_wdf_data_r1[245]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[246] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[246]),\n .Q(app_wdf_data_r1[246]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[247] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[247]),\n .Q(app_wdf_data_r1[247]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[248] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[248]),\n .Q(app_wdf_data_r1[248]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[249] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[249]),\n .Q(app_wdf_data_r1[249]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[24] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[24]),\n .Q(app_wdf_data_r1[24]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[250] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[250]),\n .Q(app_wdf_data_r1[250]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[251] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[251]),\n .Q(app_wdf_data_r1[251]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[252] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[252]),\n .Q(app_wdf_data_r1[252]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[253] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[253]),\n .Q(app_wdf_data_r1[253]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[254] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[254]),\n .Q(app_wdf_data_r1[254]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[255] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[255]),\n .Q(app_wdf_data_r1[255]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[25] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[25]),\n .Q(app_wdf_data_r1[25]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[26] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[26]),\n .Q(app_wdf_data_r1[26]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[27] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[27]),\n .Q(app_wdf_data_r1[27]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[28] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[28]),\n .Q(app_wdf_data_r1[28]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[29] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[29]),\n .Q(app_wdf_data_r1[29]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[2] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[2]),\n .Q(app_wdf_data_r1[2]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[30] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[30]),\n .Q(app_wdf_data_r1[30]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[31] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[31]),\n .Q(app_wdf_data_r1[31]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[32] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[32]),\n .Q(app_wdf_data_r1[32]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[33] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[33]),\n .Q(app_wdf_data_r1[33]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[34] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[34]),\n .Q(app_wdf_data_r1[34]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[35] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[35]),\n .Q(app_wdf_data_r1[35]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[36] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[36]),\n .Q(app_wdf_data_r1[36]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[37] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[37]),\n .Q(app_wdf_data_r1[37]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[38] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[38]),\n .Q(app_wdf_data_r1[38]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[39] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[39]),\n .Q(app_wdf_data_r1[39]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[3] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[3]),\n .Q(app_wdf_data_r1[3]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[40] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[40]),\n .Q(app_wdf_data_r1[40]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[41] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[41]),\n .Q(app_wdf_data_r1[41]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[42] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[42]),\n .Q(app_wdf_data_r1[42]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[43] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[43]),\n .Q(app_wdf_data_r1[43]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[44] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[44]),\n .Q(app_wdf_data_r1[44]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[45] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[45]),\n .Q(app_wdf_data_r1[45]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[46] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[46]),\n .Q(app_wdf_data_r1[46]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[47] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[47]),\n .Q(app_wdf_data_r1[47]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[48] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[48]),\n .Q(app_wdf_data_r1[48]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[49] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[49]),\n .Q(app_wdf_data_r1[49]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[4] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[4]),\n .Q(app_wdf_data_r1[4]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[50] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[50]),\n .Q(app_wdf_data_r1[50]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[51] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[51]),\n .Q(app_wdf_data_r1[51]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[52] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[52]),\n .Q(app_wdf_data_r1[52]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[53] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[53]),\n .Q(app_wdf_data_r1[53]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[54] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[54]),\n .Q(app_wdf_data_r1[54]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[55] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[55]),\n .Q(app_wdf_data_r1[55]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[56] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[56]),\n .Q(app_wdf_data_r1[56]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[57] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[57]),\n .Q(app_wdf_data_r1[57]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[58] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[58]),\n .Q(app_wdf_data_r1[58]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[59] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[59]),\n .Q(app_wdf_data_r1[59]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[5] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[5]),\n .Q(app_wdf_data_r1[5]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[60] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[60]),\n .Q(app_wdf_data_r1[60]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[61] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[61]),\n .Q(app_wdf_data_r1[61]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[62] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[62]),\n .Q(app_wdf_data_r1[62]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[63] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[63]),\n .Q(app_wdf_data_r1[63]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[64] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[64]),\n .Q(app_wdf_data_r1[64]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[65] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[65]),\n .Q(app_wdf_data_r1[65]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[66] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[66]),\n .Q(app_wdf_data_r1[66]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[67] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[67]),\n .Q(app_wdf_data_r1[67]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[68] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[68]),\n .Q(app_wdf_data_r1[68]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[69] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[69]),\n .Q(app_wdf_data_r1[69]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[6] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[6]),\n .Q(app_wdf_data_r1[6]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[70] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[70]),\n .Q(app_wdf_data_r1[70]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[71] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[71]),\n .Q(app_wdf_data_r1[71]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[72] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[72]),\n .Q(app_wdf_data_r1[72]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[73] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[73]),\n .Q(app_wdf_data_r1[73]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[74] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[74]),\n .Q(app_wdf_data_r1[74]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[75] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[75]),\n .Q(app_wdf_data_r1[75]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[76] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[76]),\n .Q(app_wdf_data_r1[76]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[77] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[77]),\n .Q(app_wdf_data_r1[77]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[78] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[78]),\n .Q(app_wdf_data_r1[78]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[79] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[79]),\n .Q(app_wdf_data_r1[79]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[7] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[7]),\n .Q(app_wdf_data_r1[7]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[80] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[80]),\n .Q(app_wdf_data_r1[80]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[81] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[81]),\n .Q(app_wdf_data_r1[81]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[82] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[82]),\n .Q(app_wdf_data_r1[82]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[83] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[83]),\n .Q(app_wdf_data_r1[83]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[84] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[84]),\n .Q(app_wdf_data_r1[84]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[85] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[85]),\n .Q(app_wdf_data_r1[85]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[86] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[86]),\n .Q(app_wdf_data_r1[86]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[87] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[87]),\n .Q(app_wdf_data_r1[87]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[88] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[88]),\n .Q(app_wdf_data_r1[88]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[89] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[89]),\n .Q(app_wdf_data_r1[89]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[8] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[8]),\n .Q(app_wdf_data_r1[8]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[90] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[90]),\n .Q(app_wdf_data_r1[90]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[91] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[91]),\n .Q(app_wdf_data_r1[91]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[92] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[92]),\n .Q(app_wdf_data_r1[92]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[93] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[93]),\n .Q(app_wdf_data_r1[93]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[94] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[94]),\n .Q(app_wdf_data_r1[94]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[95] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[95]),\n .Q(app_wdf_data_r1[95]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[96] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[96]),\n .Q(app_wdf_data_r1[96]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[97] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[97]),\n .Q(app_wdf_data_r1[97]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[98] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[98]),\n .Q(app_wdf_data_r1[98]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[99] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[99]),\n .Q(app_wdf_data_r1[99]),\n .R(1'b0));\n FDRE \\app_wdf_data_r1_reg[9] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_data[9]),\n .Q(app_wdf_data_r1[9]),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00E200E200FF0000)) \n app_wdf_end_r1_i_1\n (.I0(mc_app_wdf_wren_reg),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(w_cmd_rdy),\n .I3(reset_reg),\n .I4(app_wdf_end_r1),\n .I5(app_wdf_rdy_r_copy2),\n .O(app_wdf_end_ns1));\n FDRE app_wdf_end_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(app_wdf_end_ns1),\n .Q(app_wdf_end_r1),\n .R(1'b0));\n FDRE \\app_wdf_mask_r1_reg[0] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[0]),\n .Q(app_wdf_mask_r1[0]),\n .R(1'b0));\n FDRE \\app_wdf_mask_r1_reg[10] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[10]),\n .Q(app_wdf_mask_r1[10]),\n .R(1'b0));\n FDRE \\app_wdf_mask_r1_reg[11] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[11]),\n .Q(app_wdf_mask_r1[11]),\n .R(1'b0));\n FDRE \\app_wdf_mask_r1_reg[12] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[12]),\n .Q(app_wdf_mask_r1[12]),\n .R(1'b0));\n FDRE \\app_wdf_mask_r1_reg[13] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[13]),\n .Q(app_wdf_mask_r1[13]),\n .R(1'b0));\n FDRE \\app_wdf_mask_r1_reg[14] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[14]),\n .Q(app_wdf_mask_r1[14]),\n .R(1'b0));\n FDRE \\app_wdf_mask_r1_reg[15] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[15]),\n .Q(app_wdf_mask_r1[15]),\n .R(1'b0));\n FDRE \\app_wdf_mask_r1_reg[16] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[16]),\n .Q(app_wdf_mask_r1[16]),\n .R(1'b0));\n FDRE \\app_wdf_mask_r1_reg[17] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[17]),\n .Q(app_wdf_mask_r1[17]),\n .R(1'b0));\n FDRE \\app_wdf_mask_r1_reg[18] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[18]),\n .Q(app_wdf_mask_r1[18]),\n .R(1'b0));\n FDRE \\app_wdf_mask_r1_reg[19] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[19]),\n .Q(app_wdf_mask_r1[19]),\n .R(1'b0));\n FDRE \\app_wdf_mask_r1_reg[1] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[1]),\n .Q(app_wdf_mask_r1[1]),\n .R(1'b0));\n FDRE \\app_wdf_mask_r1_reg[20] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[20]),\n .Q(app_wdf_mask_r1[20]),\n .R(1'b0));\n FDRE \\app_wdf_mask_r1_reg[21] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[21]),\n .Q(app_wdf_mask_r1[21]),\n .R(1'b0));\n FDRE \\app_wdf_mask_r1_reg[22] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[22]),\n .Q(app_wdf_mask_r1[22]),\n .R(1'b0));\n FDRE \\app_wdf_mask_r1_reg[23] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[23]),\n .Q(app_wdf_mask_r1[23]),\n .R(1'b0));\n FDRE \\app_wdf_mask_r1_reg[24] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[24]),\n .Q(app_wdf_mask_r1[24]),\n .R(1'b0));\n FDRE \\app_wdf_mask_r1_reg[25] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[25]),\n .Q(app_wdf_mask_r1[25]),\n .R(1'b0));\n FDRE \\app_wdf_mask_r1_reg[26] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[26]),\n .Q(app_wdf_mask_r1[26]),\n .R(1'b0));\n FDRE \\app_wdf_mask_r1_reg[27] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[27]),\n .Q(app_wdf_mask_r1[27]),\n .R(1'b0));\n FDRE \\app_wdf_mask_r1_reg[28] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[28]),\n .Q(app_wdf_mask_r1[28]),\n .R(1'b0));\n FDRE \\app_wdf_mask_r1_reg[29] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[29]),\n .Q(app_wdf_mask_r1[29]),\n .R(1'b0));\n FDRE \\app_wdf_mask_r1_reg[2] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[2]),\n .Q(app_wdf_mask_r1[2]),\n .R(1'b0));\n FDRE \\app_wdf_mask_r1_reg[30] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[30]),\n .Q(app_wdf_mask_r1[30]),\n .R(1'b0));\n FDRE \\app_wdf_mask_r1_reg[31] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[31]),\n .Q(app_wdf_mask_r1[31]),\n .R(1'b0));\n FDRE \\app_wdf_mask_r1_reg[3] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[3]),\n .Q(app_wdf_mask_r1[3]),\n .R(1'b0));\n FDRE \\app_wdf_mask_r1_reg[4] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[4]),\n .Q(app_wdf_mask_r1[4]),\n .R(1'b0));\n FDRE \\app_wdf_mask_r1_reg[5] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[5]),\n .Q(app_wdf_mask_r1[5]),\n .R(1'b0));\n FDRE \\app_wdf_mask_r1_reg[6] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[6]),\n .Q(app_wdf_mask_r1[6]),\n .R(1'b0));\n FDRE \\app_wdf_mask_r1_reg[7] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[7]),\n .Q(app_wdf_mask_r1[7]),\n .R(1'b0));\n FDRE \\app_wdf_mask_r1_reg[8] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[8]),\n .Q(app_wdf_mask_r1[8]),\n .R(1'b0));\n FDRE \\app_wdf_mask_r1_reg[9] \n (.C(CLK),\n .CE(app_wdf_rdy_r_copy2),\n .D(app_wdf_mask[9]),\n .Q(app_wdf_mask_r1[9]),\n .R(1'b0));\n (* equivalent_register_removal = \"no\" *) \n FDRE app_wdf_rdy_r_copy1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wdf_rdy_ns),\n .Q(app_wdf_rdy_r_copy1),\n .R(1'b0));\n (* equivalent_register_removal = \"no\" *) \n FDRE app_wdf_rdy_r_copy2_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wdf_rdy_ns),\n .Q(app_wdf_rdy_r_copy2),\n .R(1'b0));\n (* equivalent_register_removal = \"no\" *) \n FDRE app_wdf_rdy_r_copy3_reg\n (.C(CLK),\n .CE(1'b1),\n .D(wdf_rdy_ns),\n .Q(app_wdf_rdy_r_copy3),\n .R(1'b0));\n LUT6 #(\n .INIT(64'h00E200E200FF0000)) \n app_wdf_wren_r1_i_1\n (.I0(mc_app_wdf_wren_reg),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(w_cmd_rdy),\n .I3(reset_reg),\n .I4(app_wdf_wren_r1),\n .I5(app_wdf_rdy_r_copy2),\n .O(app_wdf_wren_ns1));\n FDRE app_wdf_wren_r1_reg\n (.C(CLK),\n .CE(1'b1),\n .D(app_wdf_wren_ns1),\n .Q(app_wdf_wren_r1),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1519\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\data_buf_address_counter.data_buf_addr_cnt_r[0]_i_1 \n (.I0(\\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [0]),\n .O(p_0_in__0[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1519\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\data_buf_address_counter.data_buf_addr_cnt_r[1]_i_1 \n (.I0(\\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [0]),\n .I1(\\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [1]),\n .O(p_0_in__0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1518\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\data_buf_address_counter.data_buf_addr_cnt_r[2]_i_1 \n (.I0(\\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [0]),\n .I1(\\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [1]),\n .I2(\\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [2]),\n .O(p_0_in__0[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1518\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\data_buf_address_counter.data_buf_addr_cnt_r[3]_i_2 \n (.I0(\\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [2]),\n .I1(\\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [1]),\n .I2(\\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [0]),\n .I3(\\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [3]),\n .O(p_0_in__0[3]));\n FDRE \\data_buf_address_counter.data_buf_addr_cnt_r_reg[0] \n (.C(CLK),\n .CE(wr_accepted),\n .D(p_0_in__0[0]),\n .Q(\\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [0]),\n .R(reset_reg));\n FDRE \\data_buf_address_counter.data_buf_addr_cnt_r_reg[1] \n (.C(CLK),\n .CE(wr_accepted),\n .D(p_0_in__0[1]),\n .Q(\\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [1]),\n .R(reset_reg));\n FDRE \\data_buf_address_counter.data_buf_addr_cnt_r_reg[2] \n (.C(CLK),\n .CE(wr_accepted),\n .D(p_0_in__0[2]),\n .Q(\\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [2]),\n .R(reset_reg));\n FDRE \\data_buf_address_counter.data_buf_addr_cnt_r_reg[3] \n (.C(CLK),\n .CE(wr_accepted),\n .D(p_0_in__0[3]),\n .Q(\\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 [3]),\n .R(reset_reg));\n (* equivalent_register_removal = \"no\" *) \n FDRE \\occupied_counter.app_wdf_rdy_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(wdf_rdy_ns),\n .Q(\\mc_app_wdf_mask_reg_reg[0] ),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1515\" *) \n LUT4 #(\n .INIT(16'hEAAA)) \n \\occupied_counter.occ_cnt[0]_i_1 \n (.I0(\\occupied_counter.occ_cnt_reg_n_0_[1] ),\n .I1(app_wdf_rdy_r_copy1),\n .I2(app_wdf_end_r1),\n .I3(app_wdf_wren_r1),\n .O(\\occupied_counter.occ_cnt[0]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hBFFF8000)) \n \\occupied_counter.occ_cnt[10]_i_1 \n (.I0(\\occupied_counter.occ_cnt_reg_n_0_[9] ),\n .I1(app_wdf_wren_r1),\n .I2(app_wdf_end_r1),\n .I3(app_wdf_rdy_r_copy1),\n .I4(\\occupied_counter.occ_cnt_reg_n_0_[11] ),\n .O(\\occupied_counter.occ_cnt[10]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hBFFF8000)) \n \\occupied_counter.occ_cnt[11]_i_1 \n (.I0(\\occupied_counter.occ_cnt_reg_n_0_[10] ),\n .I1(app_wdf_wren_r1),\n .I2(app_wdf_end_r1),\n .I3(app_wdf_rdy_r_copy1),\n .I4(\\occupied_counter.occ_cnt_reg_n_0_[12] ),\n .O(\\occupied_counter.occ_cnt[11]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hBFFF8000)) \n \\occupied_counter.occ_cnt[12]_i_1 \n (.I0(\\occupied_counter.occ_cnt_reg_n_0_[11] ),\n .I1(app_wdf_wren_r1),\n .I2(app_wdf_end_r1),\n .I3(app_wdf_rdy_r_copy1),\n .I4(\\occupied_counter.occ_cnt_reg_n_0_[13] ),\n .O(\\occupied_counter.occ_cnt[12]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1514\" *) \n LUT5 #(\n .INIT(32'hBFFF8000)) \n \\occupied_counter.occ_cnt[13]_i_1 \n (.I0(\\occupied_counter.occ_cnt_reg_n_0_[12] ),\n .I1(app_wdf_wren_r1),\n .I2(app_wdf_end_r1),\n .I3(app_wdf_rdy_r_copy1),\n .I4(p_4_in),\n .O(\\occupied_counter.occ_cnt[13]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hBFFF8000)) \n \\occupied_counter.occ_cnt[14]_i_1 \n (.I0(\\occupied_counter.occ_cnt_reg_n_0_[13] ),\n .I1(app_wdf_wren_r1),\n .I2(app_wdf_end_r1),\n .I3(app_wdf_rdy_r_copy1),\n .I4(\\occupied_counter.occ_cnt_reg_n_0_[15] ),\n .O(\\occupied_counter.occ_cnt[14]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h6AAA)) \n \\occupied_counter.occ_cnt[15]_i_1 \n (.I0(p_0_in),\n .I1(app_wdf_rdy_r_copy1),\n .I2(app_wdf_end_r1),\n .I3(app_wdf_wren_r1),\n .O(\\occupied_counter.occ_cnt[15]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1514\" *) \n LUT4 #(\n .INIT(16'h8000)) \n \\occupied_counter.occ_cnt[15]_i_2 \n (.I0(app_wdf_wren_r1),\n .I1(app_wdf_end_r1),\n .I2(app_wdf_rdy_r_copy1),\n .I3(p_4_in),\n .O(\\occupied_counter.occ_cnt[15]_i_2_n_0 ));\n LUT5 #(\n .INIT(32'hBFFF8000)) \n \\occupied_counter.occ_cnt[1]_i_1 \n (.I0(\\occupied_counter.occ_cnt_reg_n_0_[0] ),\n .I1(app_wdf_wren_r1),\n .I2(app_wdf_end_r1),\n .I3(app_wdf_rdy_r_copy1),\n .I4(\\occupied_counter.occ_cnt_reg_n_0_[2] ),\n .O(\\occupied_counter.occ_cnt[1]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1515\" *) \n LUT5 #(\n .INIT(32'hBFFF8000)) \n \\occupied_counter.occ_cnt[2]_i_1 \n (.I0(\\occupied_counter.occ_cnt_reg_n_0_[1] ),\n .I1(app_wdf_wren_r1),\n .I2(app_wdf_end_r1),\n .I3(app_wdf_rdy_r_copy1),\n .I4(\\occupied_counter.occ_cnt_reg_n_0_[3] ),\n .O(\\occupied_counter.occ_cnt[2]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hBFFF8000)) \n \\occupied_counter.occ_cnt[3]_i_1 \n (.I0(\\occupied_counter.occ_cnt_reg_n_0_[2] ),\n .I1(app_wdf_wren_r1),\n .I2(app_wdf_end_r1),\n .I3(app_wdf_rdy_r_copy1),\n .I4(\\occupied_counter.occ_cnt_reg_n_0_[4] ),\n .O(\\occupied_counter.occ_cnt[3]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hBFFF8000)) \n \\occupied_counter.occ_cnt[4]_i_1 \n (.I0(\\occupied_counter.occ_cnt_reg_n_0_[3] ),\n .I1(app_wdf_wren_r1),\n .I2(app_wdf_end_r1),\n .I3(app_wdf_rdy_r_copy1),\n .I4(\\occupied_counter.occ_cnt_reg_n_0_[5] ),\n .O(\\occupied_counter.occ_cnt[4]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hBFFF8000)) \n \\occupied_counter.occ_cnt[5]_i_1 \n (.I0(\\occupied_counter.occ_cnt_reg_n_0_[4] ),\n .I1(app_wdf_wren_r1),\n .I2(app_wdf_end_r1),\n .I3(app_wdf_rdy_r_copy1),\n .I4(\\occupied_counter.occ_cnt_reg_n_0_[6] ),\n .O(\\occupied_counter.occ_cnt[5]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hBFFF8000)) \n \\occupied_counter.occ_cnt[6]_i_1 \n (.I0(\\occupied_counter.occ_cnt_reg_n_0_[5] ),\n .I1(app_wdf_wren_r1),\n .I2(app_wdf_end_r1),\n .I3(app_wdf_rdy_r_copy1),\n .I4(\\occupied_counter.occ_cnt_reg_n_0_[7] ),\n .O(\\occupied_counter.occ_cnt[6]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hBFFF8000)) \n \\occupied_counter.occ_cnt[7]_i_1 \n (.I0(\\occupied_counter.occ_cnt_reg_n_0_[6] ),\n .I1(app_wdf_wren_r1),\n .I2(app_wdf_end_r1),\n .I3(app_wdf_rdy_r_copy1),\n .I4(\\occupied_counter.occ_cnt_reg_n_0_[8] ),\n .O(\\occupied_counter.occ_cnt[7]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1512\" *) \n LUT5 #(\n .INIT(32'hBFFF8000)) \n \\occupied_counter.occ_cnt[8]_i_1 \n (.I0(\\occupied_counter.occ_cnt_reg_n_0_[7] ),\n .I1(app_wdf_wren_r1),\n .I2(app_wdf_end_r1),\n .I3(app_wdf_rdy_r_copy1),\n .I4(\\occupied_counter.occ_cnt_reg_n_0_[9] ),\n .O(\\occupied_counter.occ_cnt[8]_i_1_n_0 ));\n LUT5 #(\n .INIT(32'hBFFF8000)) \n \\occupied_counter.occ_cnt[9]_i_1 \n (.I0(\\occupied_counter.occ_cnt_reg_n_0_[8] ),\n .I1(app_wdf_wren_r1),\n .I2(app_wdf_end_r1),\n .I3(app_wdf_rdy_r_copy1),\n .I4(\\occupied_counter.occ_cnt_reg_n_0_[10] ),\n .O(\\occupied_counter.occ_cnt[9]_i_1_n_0 ));\n FDRE \\occupied_counter.occ_cnt_reg[0] \n (.C(CLK),\n .CE(\\occupied_counter.occ_cnt[15]_i_1_n_0 ),\n .D(\\occupied_counter.occ_cnt[0]_i_1_n_0 ),\n .Q(\\occupied_counter.occ_cnt_reg_n_0_[0] ),\n .R(reset_reg));\n FDRE \\occupied_counter.occ_cnt_reg[10] \n (.C(CLK),\n .CE(\\occupied_counter.occ_cnt[15]_i_1_n_0 ),\n .D(\\occupied_counter.occ_cnt[10]_i_1_n_0 ),\n .Q(\\occupied_counter.occ_cnt_reg_n_0_[10] ),\n .R(reset_reg));\n FDRE \\occupied_counter.occ_cnt_reg[11] \n (.C(CLK),\n .CE(\\occupied_counter.occ_cnt[15]_i_1_n_0 ),\n .D(\\occupied_counter.occ_cnt[11]_i_1_n_0 ),\n .Q(\\occupied_counter.occ_cnt_reg_n_0_[11] ),\n .R(reset_reg));\n FDRE \\occupied_counter.occ_cnt_reg[12] \n (.C(CLK),\n .CE(\\occupied_counter.occ_cnt[15]_i_1_n_0 ),\n .D(\\occupied_counter.occ_cnt[12]_i_1_n_0 ),\n .Q(\\occupied_counter.occ_cnt_reg_n_0_[12] ),\n .R(reset_reg));\n FDRE \\occupied_counter.occ_cnt_reg[13] \n (.C(CLK),\n .CE(\\occupied_counter.occ_cnt[15]_i_1_n_0 ),\n .D(\\occupied_counter.occ_cnt[13]_i_1_n_0 ),\n .Q(\\occupied_counter.occ_cnt_reg_n_0_[13] ),\n .R(reset_reg));\n FDRE \\occupied_counter.occ_cnt_reg[14] \n (.C(CLK),\n .CE(\\occupied_counter.occ_cnt[15]_i_1_n_0 ),\n .D(\\occupied_counter.occ_cnt[14]_i_1_n_0 ),\n .Q(p_4_in),\n .R(reset_reg));\n FDRE \\occupied_counter.occ_cnt_reg[15] \n (.C(CLK),\n .CE(\\occupied_counter.occ_cnt[15]_i_1_n_0 ),\n .D(\\occupied_counter.occ_cnt[15]_i_2_n_0 ),\n .Q(\\occupied_counter.occ_cnt_reg_n_0_[15] ),\n .R(reset_reg));\n FDRE \\occupied_counter.occ_cnt_reg[1] \n (.C(CLK),\n .CE(\\occupied_counter.occ_cnt[15]_i_1_n_0 ),\n .D(\\occupied_counter.occ_cnt[1]_i_1_n_0 ),\n .Q(\\occupied_counter.occ_cnt_reg_n_0_[1] ),\n .R(reset_reg));\n FDRE \\occupied_counter.occ_cnt_reg[2] \n (.C(CLK),\n .CE(\\occupied_counter.occ_cnt[15]_i_1_n_0 ),\n .D(\\occupied_counter.occ_cnt[2]_i_1_n_0 ),\n .Q(\\occupied_counter.occ_cnt_reg_n_0_[2] ),\n .R(reset_reg));\n FDRE \\occupied_counter.occ_cnt_reg[3] \n (.C(CLK),\n .CE(\\occupied_counter.occ_cnt[15]_i_1_n_0 ),\n .D(\\occupied_counter.occ_cnt[3]_i_1_n_0 ),\n .Q(\\occupied_counter.occ_cnt_reg_n_0_[3] ),\n .R(reset_reg));\n FDRE \\occupied_counter.occ_cnt_reg[4] \n (.C(CLK),\n .CE(\\occupied_counter.occ_cnt[15]_i_1_n_0 ),\n .D(\\occupied_counter.occ_cnt[4]_i_1_n_0 ),\n .Q(\\occupied_counter.occ_cnt_reg_n_0_[4] ),\n .R(reset_reg));\n FDRE \\occupied_counter.occ_cnt_reg[5] \n (.C(CLK),\n .CE(\\occupied_counter.occ_cnt[15]_i_1_n_0 ),\n .D(\\occupied_counter.occ_cnt[5]_i_1_n_0 ),\n .Q(\\occupied_counter.occ_cnt_reg_n_0_[5] ),\n .R(reset_reg));\n FDRE \\occupied_counter.occ_cnt_reg[6] \n (.C(CLK),\n .CE(\\occupied_counter.occ_cnt[15]_i_1_n_0 ),\n .D(\\occupied_counter.occ_cnt[6]_i_1_n_0 ),\n .Q(\\occupied_counter.occ_cnt_reg_n_0_[6] ),\n .R(reset_reg));\n FDRE \\occupied_counter.occ_cnt_reg[7] \n (.C(CLK),\n .CE(\\occupied_counter.occ_cnt[15]_i_1_n_0 ),\n .D(\\occupied_counter.occ_cnt[7]_i_1_n_0 ),\n .Q(\\occupied_counter.occ_cnt_reg_n_0_[7] ),\n .R(reset_reg));\n FDRE \\occupied_counter.occ_cnt_reg[8] \n (.C(CLK),\n .CE(\\occupied_counter.occ_cnt[15]_i_1_n_0 ),\n .D(\\occupied_counter.occ_cnt[8]_i_1_n_0 ),\n .Q(\\occupied_counter.occ_cnt_reg_n_0_[8] ),\n .R(reset_reg));\n FDRE \\occupied_counter.occ_cnt_reg[9] \n (.C(CLK),\n .CE(\\occupied_counter.occ_cnt[15]_i_1_n_0 ),\n .D(\\occupied_counter.occ_cnt[9]_i_1_n_0 ),\n .Q(\\occupied_counter.occ_cnt_reg_n_0_[9] ),\n .R(reset_reg));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\pointer_ram.rams[0].RAM32M0 \n (.ADDRA({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .ADDRB({1'b0,\\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 }),\n .ADDRC({1'b0,\\write_data_control.wr_data_indx_r_reg__0 }),\n .ADDRD({1'b0,ADDRD}),\n .DIA({1'b0,1'b0}),\n .DIB(pointer_wr_data[1:0]),\n .DIC(pointer_wr_data[1:0]),\n .DID({1'b0,1'b0}),\n .DOA(\\NLW_pointer_ram.rams[0].RAM32M0_DOA_UNCONNECTED [1:0]),\n .DOB(wr_data_buf_addr[1:0]),\n .DOC(wr_data_pntr[1:0]),\n .DOD(\\NLW_pointer_ram.rams[0].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(pointer_we));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\pointer_ram.rams[1].RAM32M0 \n (.ADDRA({1'b0,1'b0,1'b0,1'b0,1'b0}),\n .ADDRB({1'b0,\\data_buf_address_counter.data_buf_addr_cnt_r_reg__0 }),\n .ADDRC({1'b0,\\write_data_control.wr_data_indx_r_reg__0 }),\n .ADDRD({1'b0,ADDRD}),\n .DIA({1'b0,1'b0}),\n .DIB(pointer_wr_data[3:2]),\n .DIC(pointer_wr_data[3:2]),\n .DID({1'b0,1'b0}),\n .DOA(\\NLW_pointer_ram.rams[1].RAM32M0_DOA_UNCONNECTED [1:0]),\n .DOB(wr_data_buf_addr[3:2]),\n .DOC(wr_data_pntr[3:2]),\n .DOD(\\NLW_pointer_ram.rams[1].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(pointer_we));\n (* SOFT_HLUTNM = \"soft_lutpair1520\" *) \n LUT1 #(\n .INIT(2'h1)) \n \\read_data_indx.rd_data_indx_r[0]_i_1 \n (.I0(Q[0]),\n .O(p_0_in__1[0]));\n (* SOFT_HLUTNM = \"soft_lutpair1520\" *) \n LUT2 #(\n .INIT(4'h6)) \n \\read_data_indx.rd_data_indx_r[1]_i_1 \n (.I0(Q[0]),\n .I1(Q[1]),\n .O(p_0_in__1[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1517\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\read_data_indx.rd_data_indx_r[2]_i_1 \n (.I0(Q[0]),\n .I1(Q[1]),\n .I2(Q[2]),\n .O(p_0_in__1[2]));\n (* SOFT_HLUTNM = \"soft_lutpair1517\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\read_data_indx.rd_data_indx_r[3]_i_1 \n (.I0(Q[2]),\n .I1(Q[1]),\n .I2(Q[0]),\n .I3(Q[3]),\n .O(p_0_in__1[3]));\n FDRE \\read_data_indx.rd_data_indx_r_reg[0] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__1[0]),\n .Q(Q[0]),\n .R(reset_reg));\n FDRE \\read_data_indx.rd_data_indx_r_reg[1] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__1[1]),\n .Q(Q[1]),\n .R(reset_reg));\n FDRE \\read_data_indx.rd_data_indx_r_reg[2] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__1[2]),\n .Q(Q[2]),\n .R(reset_reg));\n FDRE \\read_data_indx.rd_data_indx_r_reg[3] \n (.C(CLK),\n .CE(E),\n .D(p_0_in__1[3]),\n .Q(Q[3]),\n .R(reset_reg));\n FDRE \\read_data_indx.rd_data_upd_indx_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(E),\n .Q(p_0_in),\n .R(1'b0));\n (* SOFT_HLUTNM = \"soft_lutpair1513\" *) \n LUT4 #(\n .INIT(16'h0096)) \n \\wr_req_counter.wr_req_cnt_r[0]_i_1 \n (.I0(p_0_in),\n .I1(wr_accepted),\n .I2(\\wr_req_counter.wr_req_cnt_r_reg[1]_0 [0]),\n .I3(reset_reg),\n .O(\\wr_req_counter.wr_req_cnt_r[0]_i_1_n_0 ));\n (* SOFT_HLUTNM = \"soft_lutpair1513\" *) \n LUT5 #(\n .INIT(32'h0000D2B4)) \n \\wr_req_counter.wr_req_cnt_r[1]_i_1 \n (.I0(wr_accepted),\n .I1(p_0_in),\n .I2(\\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]),\n .I3(\\wr_req_counter.wr_req_cnt_r_reg[1]_0 [0]),\n .I4(reset_reg),\n .O(\\wr_req_counter.wr_req_cnt_r[1]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00000000F7EF0810)) \n \\wr_req_counter.wr_req_cnt_r[2]_i_1 \n (.I0(\\wr_req_counter.wr_req_cnt_r_reg[1]_0 [0]),\n .I1(\\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]),\n .I2(p_0_in),\n .I3(wr_accepted),\n .I4(wr_req_cnt_r[2]),\n .I5(reset_reg),\n .O(\\wr_req_counter.wr_req_cnt_r[2]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h00000000FF7E0081)) \n \\wr_req_counter.wr_req_cnt_r[3]_i_1 \n (.I0(wr_req_cnt_r[2]),\n .I1(\\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]),\n .I2(\\wr_req_counter.wr_req_cnt_r_reg[1]_1 ),\n .I3(\\read_data_indx.rd_data_upd_indx_r_reg_0 ),\n .I4(wr_req_cnt_r[3]),\n .I5(reset_reg),\n .O(\\wr_req_counter.wr_req_cnt_r[3]_i_1_n_0 ));\n LUT6 #(\n .INIT(64'h000000009CCCCCC9)) \n \\wr_req_counter.wr_req_cnt_r[4]_i_1 \n (.I0(\\read_data_indx.rd_data_upd_indx_r_reg_0 ),\n .I1(wr_req_cnt_r[4]),\n .I2(\\wr_req_counter.wr_req_cnt_r[4]_i_2_n_0 ),\n .I3(wr_req_cnt_r[2]),\n .I4(wr_req_cnt_r[3]),\n .I5(reset_reg),\n .O(\\wr_req_counter.wr_req_cnt_r[4]_i_1_n_0 ));\n LUT4 #(\n .INIT(16'h80FE)) \n \\wr_req_counter.wr_req_cnt_r[4]_i_2 \n (.I0(\\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]),\n .I1(wr_accepted),\n .I2(\\wr_req_counter.wr_req_cnt_r_reg[1]_0 [0]),\n .I3(wr_req_cnt_r[2]),\n .O(\\wr_req_counter.wr_req_cnt_r[4]_i_2_n_0 ));\n FDRE \\wr_req_counter.wr_req_cnt_r_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_req_counter.wr_req_cnt_r[0]_i_1_n_0 ),\n .Q(\\wr_req_counter.wr_req_cnt_r_reg[1]_0 [0]),\n .R(1'b0));\n FDRE \\wr_req_counter.wr_req_cnt_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_req_counter.wr_req_cnt_r[1]_i_1_n_0 ),\n .Q(\\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]),\n .R(1'b0));\n FDRE \\wr_req_counter.wr_req_cnt_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_req_counter.wr_req_cnt_r[2]_i_1_n_0 ),\n .Q(wr_req_cnt_r[2]),\n .R(1'b0));\n FDRE \\wr_req_counter.wr_req_cnt_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_req_counter.wr_req_cnt_r[3]_i_1_n_0 ),\n .Q(wr_req_cnt_r[3]),\n .R(1'b0));\n FDRE \\wr_req_counter.wr_req_cnt_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(\\wr_req_counter.wr_req_cnt_r[4]_i_1_n_0 ),\n .Q(wr_req_cnt_r[4]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[0] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[0]),\n .Q(\\my_empty_reg[7] [0]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[100] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[100]),\n .Q(\\my_empty_reg[7] [100]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[101] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[101]),\n .Q(\\my_empty_reg[7] [101]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[102] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[102]),\n .Q(\\my_empty_reg[7] [102]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[103] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[103]),\n .Q(\\my_empty_reg[7] [103]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[104] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[104]),\n .Q(\\my_empty_reg[7] [104]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[105] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[105]),\n .Q(\\my_empty_reg[7] [105]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[106] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[106]),\n .Q(\\my_empty_reg[7] [106]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[107] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[107]),\n .Q(\\my_empty_reg[7] [107]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[108] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[108]),\n .Q(\\my_empty_reg[7] [108]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[109] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[109]),\n .Q(\\my_empty_reg[7] [109]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[10] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[10]),\n .Q(\\my_empty_reg[7] [10]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[110] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[110]),\n .Q(\\my_empty_reg[7] [110]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[111] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[111]),\n .Q(\\my_empty_reg[7] [111]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[112] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[112]),\n .Q(\\my_empty_reg[7] [112]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[113] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[113]),\n .Q(\\my_empty_reg[7] [113]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[114] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[114]),\n .Q(\\my_empty_reg[7] [114]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[115] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[115]),\n .Q(\\my_empty_reg[7] [115]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[116] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[116]),\n .Q(\\my_empty_reg[7] [116]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[117] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[117]),\n .Q(\\my_empty_reg[7] [117]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[118] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[118]),\n .Q(\\my_empty_reg[7] [118]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[119] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[119]),\n .Q(\\my_empty_reg[7] [119]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[11] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[11]),\n .Q(\\my_empty_reg[7] [11]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[120] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[120]),\n .Q(\\my_empty_reg[7] [120]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[121] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[121]),\n .Q(\\my_empty_reg[7] [121]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[122] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[122]),\n .Q(\\my_empty_reg[7] [122]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[123] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[123]),\n .Q(\\my_empty_reg[7] [123]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[124] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[124]),\n .Q(\\my_empty_reg[7] [124]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[125] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[125]),\n .Q(\\my_empty_reg[7] [125]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[126] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[126]),\n .Q(\\my_empty_reg[7] [126]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[127] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[127]),\n .Q(\\my_empty_reg[7] [127]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[128] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[128]),\n .Q(\\my_empty_reg[7] [128]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[129] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[129]),\n .Q(\\my_empty_reg[7] [129]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[12] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[12]),\n .Q(\\my_empty_reg[7] [12]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[130] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[130]),\n .Q(\\my_empty_reg[7] [130]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[131] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[131]),\n .Q(\\my_empty_reg[7] [131]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[132] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[132]),\n .Q(\\my_empty_reg[7] [132]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[133] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[133]),\n .Q(\\my_empty_reg[7] [133]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[134] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[134]),\n .Q(\\my_empty_reg[7] [134]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[135] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[135]),\n .Q(\\my_empty_reg[7] [135]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[136] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[136]),\n .Q(\\my_empty_reg[7] [136]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[137] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[137]),\n .Q(\\my_empty_reg[7] [137]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[138] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[138]),\n .Q(\\my_empty_reg[7] [138]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[139] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[139]),\n .Q(\\my_empty_reg[7] [139]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[13] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[13]),\n .Q(\\my_empty_reg[7] [13]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[140] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[140]),\n .Q(\\my_empty_reg[7] [140]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[141] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[141]),\n .Q(\\my_empty_reg[7] [141]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[142] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[142]),\n .Q(\\my_empty_reg[7] [142]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[143] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[143]),\n .Q(\\my_empty_reg[7] [143]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[144] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[144]),\n .Q(\\my_empty_reg[7] [144]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[145] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[145]),\n .Q(\\my_empty_reg[7] [145]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[146] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[146]),\n .Q(\\my_empty_reg[7] [146]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[147] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[147]),\n .Q(\\my_empty_reg[7] [147]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[148] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[148]),\n .Q(\\my_empty_reg[7] [148]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[149] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[149]),\n .Q(\\my_empty_reg[7] [149]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[14] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[14]),\n .Q(\\my_empty_reg[7] [14]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[150] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[150]),\n .Q(\\my_empty_reg[7] [150]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[151] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[151]),\n .Q(\\my_empty_reg[7] [151]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[152] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[152]),\n .Q(\\my_empty_reg[7] [152]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[153] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[153]),\n .Q(\\my_empty_reg[7] [153]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[154] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[154]),\n .Q(\\my_empty_reg[7] [154]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[155] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[155]),\n .Q(\\my_empty_reg[7] [155]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[156] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[156]),\n .Q(\\my_empty_reg[7] [156]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[157] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[157]),\n .Q(\\my_empty_reg[7] [157]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[158] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[158]),\n .Q(\\my_empty_reg[7] [158]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[159] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[159]),\n .Q(\\my_empty_reg[7] [159]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[15] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[15]),\n .Q(\\my_empty_reg[7] [15]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[160] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[160]),\n .Q(\\my_empty_reg[7] [160]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[161] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[161]),\n .Q(\\my_empty_reg[7] [161]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[162] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[162]),\n .Q(\\my_empty_reg[7] [162]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[163] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[163]),\n .Q(\\my_empty_reg[7] [163]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[164] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[164]),\n .Q(\\my_empty_reg[7] [164]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[165] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[165]),\n .Q(\\my_empty_reg[7] [165]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[166] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[166]),\n .Q(\\my_empty_reg[7] [166]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[167] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[167]),\n .Q(\\my_empty_reg[7] [167]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[168] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[168]),\n .Q(\\my_empty_reg[7] [168]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[169] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[169]),\n .Q(\\my_empty_reg[7] [169]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[16] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[16]),\n .Q(\\my_empty_reg[7] [16]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[170] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[170]),\n .Q(\\my_empty_reg[7] [170]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[171] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[171]),\n .Q(\\my_empty_reg[7] [171]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[172] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[172]),\n .Q(\\my_empty_reg[7] [172]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[173] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[173]),\n .Q(\\my_empty_reg[7] [173]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[174] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[174]),\n .Q(\\my_empty_reg[7] [174]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[175] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[175]),\n .Q(\\my_empty_reg[7] [175]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[176] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[176]),\n .Q(\\my_empty_reg[7] [176]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[177] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[177]),\n .Q(\\my_empty_reg[7] [177]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[178] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[178]),\n .Q(\\my_empty_reg[7] [178]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[179] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[179]),\n .Q(\\my_empty_reg[7] [179]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[17] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[17]),\n .Q(\\my_empty_reg[7] [17]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[180] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[180]),\n .Q(\\my_empty_reg[7] [180]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[181] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[181]),\n .Q(\\my_empty_reg[7] [181]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[182] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[182]),\n .Q(\\my_empty_reg[7] [182]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[183] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[183]),\n .Q(\\my_empty_reg[7] [183]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[184] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[184]),\n .Q(\\my_empty_reg[7] [184]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[185] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[185]),\n .Q(\\my_empty_reg[7] [185]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[186] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[186]),\n .Q(\\my_empty_reg[7] [186]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[187] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[187]),\n .Q(\\my_empty_reg[7] [187]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[188] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[188]),\n .Q(\\my_empty_reg[7] [188]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[189] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[189]),\n .Q(\\my_empty_reg[7] [189]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[18] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[18]),\n .Q(\\my_empty_reg[7] [18]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[190] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[190]),\n .Q(\\my_empty_reg[7] [190]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[191] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[191]),\n .Q(\\my_empty_reg[7] [191]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[192] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[192]),\n .Q(\\my_empty_reg[7] [192]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[193] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[193]),\n .Q(\\my_empty_reg[7] [193]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[194] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[194]),\n .Q(\\my_empty_reg[7] [194]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[195] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[195]),\n .Q(\\my_empty_reg[7] [195]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[196] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[196]),\n .Q(\\my_empty_reg[7] [196]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[197] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[197]),\n .Q(\\my_empty_reg[7] [197]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[198] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[198]),\n .Q(\\my_empty_reg[7] [198]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[199] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[199]),\n .Q(\\my_empty_reg[7] [199]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[19] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[19]),\n .Q(\\my_empty_reg[7] [19]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[1]),\n .Q(\\my_empty_reg[7] [1]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[200] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[200]),\n .Q(\\my_empty_reg[7] [200]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[201] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[201]),\n .Q(\\my_empty_reg[7] [201]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[202] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[202]),\n .Q(\\my_empty_reg[7] [202]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[203] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[203]),\n .Q(\\my_empty_reg[7] [203]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[204] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[204]),\n .Q(\\my_empty_reg[7] [204]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[205] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[205]),\n .Q(\\my_empty_reg[7] [205]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[206] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[206]),\n .Q(\\my_empty_reg[7] [206]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[207] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[207]),\n .Q(\\my_empty_reg[7] [207]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[208] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[208]),\n .Q(\\my_empty_reg[7] [208]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[209] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[209]),\n .Q(\\my_empty_reg[7] [209]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[20] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[20]),\n .Q(\\my_empty_reg[7] [20]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[210] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[210]),\n .Q(\\my_empty_reg[7] [210]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[211] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[211]),\n .Q(\\my_empty_reg[7] [211]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[212] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[212]),\n .Q(\\my_empty_reg[7] [212]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[213] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[213]),\n .Q(\\my_empty_reg[7] [213]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[214] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[214]),\n .Q(\\my_empty_reg[7] [214]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[215] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[215]),\n .Q(\\my_empty_reg[7] [215]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[216] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[216]),\n .Q(\\my_empty_reg[7] [216]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[217] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[217]),\n .Q(\\my_empty_reg[7] [217]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[218] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[218]),\n .Q(\\my_empty_reg[7] [218]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[219] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[219]),\n .Q(\\my_empty_reg[7] [219]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[21] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[21]),\n .Q(\\my_empty_reg[7] [21]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[220] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[220]),\n .Q(\\my_empty_reg[7] [220]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[221] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[221]),\n .Q(\\my_empty_reg[7] [221]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[222] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[222]),\n .Q(\\my_empty_reg[7] [222]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[223] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[223]),\n .Q(\\my_empty_reg[7] [223]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[224] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[224]),\n .Q(\\my_empty_reg[7] [224]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[225] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[225]),\n .Q(\\my_empty_reg[7] [225]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[226] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[226]),\n .Q(\\my_empty_reg[7] [226]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[227] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[227]),\n .Q(\\my_empty_reg[7] [227]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[228] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[228]),\n .Q(\\my_empty_reg[7] [228]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[229] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[229]),\n .Q(\\my_empty_reg[7] [229]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[22] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[22]),\n .Q(\\my_empty_reg[7] [22]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[230] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[230]),\n .Q(\\my_empty_reg[7] [230]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[231] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[231]),\n .Q(\\my_empty_reg[7] [231]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[232] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[232]),\n .Q(\\my_empty_reg[7] [232]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[233] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[233]),\n .Q(\\my_empty_reg[7] [233]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[234] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[234]),\n .Q(\\my_empty_reg[7] [234]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[235] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[235]),\n .Q(\\my_empty_reg[7] [235]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[236] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[236]),\n .Q(\\my_empty_reg[7] [236]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[237] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[237]),\n .Q(\\my_empty_reg[7] [237]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[238] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[238]),\n .Q(\\my_empty_reg[7] [238]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[239] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[239]),\n .Q(\\my_empty_reg[7] [239]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[23] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[23]),\n .Q(\\my_empty_reg[7] [23]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[240] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[240]),\n .Q(\\my_empty_reg[7] [240]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[241] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[241]),\n .Q(\\my_empty_reg[7] [241]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[242] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[242]),\n .Q(\\my_empty_reg[7] [242]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[243] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[243]),\n .Q(\\my_empty_reg[7] [243]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[244] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[244]),\n .Q(\\my_empty_reg[7] [244]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[245] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[245]),\n .Q(\\my_empty_reg[7] [245]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[246] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[246]),\n .Q(\\my_empty_reg[7] [246]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[247] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[247]),\n .Q(\\my_empty_reg[7] [247]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[248] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[248]),\n .Q(\\my_empty_reg[7] [248]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[249] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[249]),\n .Q(\\my_empty_reg[7] [249]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[24] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[24]),\n .Q(\\my_empty_reg[7] [24]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[250] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[250]),\n .Q(\\my_empty_reg[7] [250]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[251] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[251]),\n .Q(\\my_empty_reg[7] [251]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[252] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[252]),\n .Q(\\my_empty_reg[7] [252]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[253] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[253]),\n .Q(\\my_empty_reg[7] [253]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[254] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[254]),\n .Q(\\my_empty_reg[7] [254]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[255] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[255]),\n .Q(\\my_empty_reg[7] [255]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[256] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[256]),\n .Q(\\my_empty_reg[7] [256]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[257] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[257]),\n .Q(\\my_empty_reg[7] [257]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[258] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[258]),\n .Q(\\my_empty_reg[7] [258]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[259] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[259]),\n .Q(\\my_empty_reg[7] [259]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[25] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[25]),\n .Q(\\my_empty_reg[7] [25]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[260] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[260]),\n .Q(\\my_empty_reg[7] [260]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[261] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[261]),\n .Q(\\my_empty_reg[7] [261]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[262] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[262]),\n .Q(\\my_empty_reg[7] [262]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[263] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[263]),\n .Q(\\my_empty_reg[7] [263]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[264] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[264]),\n .Q(\\my_empty_reg[7] [264]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[265] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[265]),\n .Q(\\my_empty_reg[7] [265]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[266] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[266]),\n .Q(\\my_empty_reg[7] [266]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[267] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[267]),\n .Q(\\my_empty_reg[7] [267]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[268] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[268]),\n .Q(\\my_empty_reg[7] [268]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[269] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[269]),\n .Q(\\my_empty_reg[7] [269]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[26] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[26]),\n .Q(\\my_empty_reg[7] [26]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[270] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[270]),\n .Q(\\my_empty_reg[7] [270]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[271] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[271]),\n .Q(\\my_empty_reg[7] [271]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[272] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[272]),\n .Q(\\my_empty_reg[7] [272]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[273] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[273]),\n .Q(\\my_empty_reg[7] [273]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[274] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[274]),\n .Q(\\my_empty_reg[7] [274]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[275] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[275]),\n .Q(\\my_empty_reg[7] [275]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[276] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[276]),\n .Q(\\my_empty_reg[7] [276]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[277] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[277]),\n .Q(\\my_empty_reg[7] [277]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[278] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[278]),\n .Q(\\my_empty_reg[7] [278]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[279] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[279]),\n .Q(\\my_empty_reg[7] [279]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[27] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[27]),\n .Q(\\my_empty_reg[7] [27]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[280] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[280]),\n .Q(\\my_empty_reg[7] [280]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[281] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[281]),\n .Q(\\my_empty_reg[7] [281]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[282] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[282]),\n .Q(\\my_empty_reg[7] [282]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[283] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[283]),\n .Q(\\my_empty_reg[7] [283]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[284] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[284]),\n .Q(\\my_empty_reg[7] [284]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[285] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[285]),\n .Q(\\my_empty_reg[7] [285]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[286] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[286]),\n .Q(\\my_empty_reg[7] [286]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[287] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[287]),\n .Q(\\my_empty_reg[7] [287]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[28] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[28]),\n .Q(\\my_empty_reg[7] [28]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[29] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[29]),\n .Q(\\my_empty_reg[7] [29]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[2]),\n .Q(\\my_empty_reg[7] [2]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[30] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[30]),\n .Q(\\my_empty_reg[7] [30]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[31] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[31]),\n .Q(\\my_empty_reg[7] [31]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[32] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[32]),\n .Q(\\my_empty_reg[7] [32]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[33] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[33]),\n .Q(\\my_empty_reg[7] [33]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[34] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[34]),\n .Q(\\my_empty_reg[7] [34]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[35] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[35]),\n .Q(\\my_empty_reg[7] [35]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[36] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[36]),\n .Q(\\my_empty_reg[7] [36]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[37] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[37]),\n .Q(\\my_empty_reg[7] [37]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[38] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[38]),\n .Q(\\my_empty_reg[7] [38]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[39] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[39]),\n .Q(\\my_empty_reg[7] [39]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[3]),\n .Q(\\my_empty_reg[7] [3]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[40] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[40]),\n .Q(\\my_empty_reg[7] [40]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[41] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[41]),\n .Q(\\my_empty_reg[7] [41]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[42] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[42]),\n .Q(\\my_empty_reg[7] [42]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[43] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[43]),\n .Q(\\my_empty_reg[7] [43]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[44] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[44]),\n .Q(\\my_empty_reg[7] [44]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[45] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[45]),\n .Q(\\my_empty_reg[7] [45]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[46] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[46]),\n .Q(\\my_empty_reg[7] [46]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[47] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[47]),\n .Q(\\my_empty_reg[7] [47]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[48] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[48]),\n .Q(\\my_empty_reg[7] [48]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[49] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[49]),\n .Q(\\my_empty_reg[7] [49]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[4]),\n .Q(\\my_empty_reg[7] [4]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[50] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[50]),\n .Q(\\my_empty_reg[7] [50]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[51] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[51]),\n .Q(\\my_empty_reg[7] [51]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[52] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[52]),\n .Q(\\my_empty_reg[7] [52]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[53] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[53]),\n .Q(\\my_empty_reg[7] [53]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[54] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[54]),\n .Q(\\my_empty_reg[7] [54]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[55] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[55]),\n .Q(\\my_empty_reg[7] [55]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[56] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[56]),\n .Q(\\my_empty_reg[7] [56]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[57] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[57]),\n .Q(\\my_empty_reg[7] [57]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[58] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[58]),\n .Q(\\my_empty_reg[7] [58]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[59] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[59]),\n .Q(\\my_empty_reg[7] [59]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[5] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[5]),\n .Q(\\my_empty_reg[7] [5]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[60] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[60]),\n .Q(\\my_empty_reg[7] [60]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[61] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[61]),\n .Q(\\my_empty_reg[7] [61]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[62] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[62]),\n .Q(\\my_empty_reg[7] [62]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[63] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[63]),\n .Q(\\my_empty_reg[7] [63]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[64] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[64]),\n .Q(\\my_empty_reg[7] [64]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[65] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[65]),\n .Q(\\my_empty_reg[7] [65]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[66] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[66]),\n .Q(\\my_empty_reg[7] [66]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[67] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[67]),\n .Q(\\my_empty_reg[7] [67]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[68] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[68]),\n .Q(\\my_empty_reg[7] [68]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[69] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[69]),\n .Q(\\my_empty_reg[7] [69]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[6] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[6]),\n .Q(\\my_empty_reg[7] [6]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[70] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[70]),\n .Q(\\my_empty_reg[7] [70]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[71] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[71]),\n .Q(\\my_empty_reg[7] [71]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[72] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[72]),\n .Q(\\my_empty_reg[7] [72]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[73] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[73]),\n .Q(\\my_empty_reg[7] [73]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[74] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[74]),\n .Q(\\my_empty_reg[7] [74]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[75] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[75]),\n .Q(\\my_empty_reg[7] [75]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[76] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[76]),\n .Q(\\my_empty_reg[7] [76]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[77] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[77]),\n .Q(\\my_empty_reg[7] [77]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[78] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[78]),\n .Q(\\my_empty_reg[7] [78]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[79] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[79]),\n .Q(\\my_empty_reg[7] [79]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[7] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[7]),\n .Q(\\my_empty_reg[7] [7]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[80] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[80]),\n .Q(\\my_empty_reg[7] [80]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[81] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[81]),\n .Q(\\my_empty_reg[7] [81]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[82] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[82]),\n .Q(\\my_empty_reg[7] [82]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[83] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[83]),\n .Q(\\my_empty_reg[7] [83]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[84] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[84]),\n .Q(\\my_empty_reg[7] [84]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[85] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[85]),\n .Q(\\my_empty_reg[7] [85]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[86] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[86]),\n .Q(\\my_empty_reg[7] [86]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[87] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[87]),\n .Q(\\my_empty_reg[7] [87]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[88] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[88]),\n .Q(\\my_empty_reg[7] [88]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[89] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[89]),\n .Q(\\my_empty_reg[7] [89]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[8] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[8]),\n .Q(\\my_empty_reg[7] [8]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[90] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[90]),\n .Q(\\my_empty_reg[7] [90]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[91] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[91]),\n .Q(\\my_empty_reg[7] [91]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[92] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[92]),\n .Q(\\my_empty_reg[7] [92]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[93] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[93]),\n .Q(\\my_empty_reg[7] [93]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[94] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[94]),\n .Q(\\my_empty_reg[7] [94]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[95] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[95]),\n .Q(\\my_empty_reg[7] [95]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[96] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[96]),\n .Q(\\my_empty_reg[7] [96]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[97] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[97]),\n .Q(\\my_empty_reg[7] [97]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[98] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[98]),\n .Q(\\my_empty_reg[7] [98]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[99] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[99]),\n .Q(\\my_empty_reg[7] [99]),\n .R(1'b0));\n FDRE \\write_buffer.wr_buf_out_data_reg[9] \n (.C(CLK),\n .CE(1'b1),\n .D(wr_buf_out_data_w[9]),\n .Q(\\my_empty_reg[7] [9]),\n .R(1'b0));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[0].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[5:4]),\n .DIB(wr_buf_in_data[3:2]),\n .DIC(wr_buf_in_data[1:0]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[5:4]),\n .DOB(wr_buf_out_data_w[3:2]),\n .DOC(wr_buf_out_data_w[1:0]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[0].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT6 #(\n .INIT(64'h4040404040444444)) \n \\write_buffer.wr_buffer_ram[0].RAM32M0_i_1 \n (.I0(reset_reg),\n .I1(ram_init_done_r),\n .I2(p_0_in),\n .I3(p_0_in__0_0),\n .I4(p_4_in),\n .I5(\\occupied_counter.occ_cnt_reg_n_0_[15] ),\n .O(wdf_rdy_ns));\n LUT4 #(\n .INIT(16'h00AC)) \n \\write_buffer.wr_buffer_ram[0].RAM32M0_i_10 \n (.I0(wr_data_pntr[1]),\n .I1(wb_wr_data_addr_r[2]),\n .I2(wr_data_addr_le),\n .I3(reset_reg),\n .O(wb_wr_data_addr_w[2]));\n LUT4 #(\n .INIT(16'h00AC)) \n \\write_buffer.wr_buffer_ram[0].RAM32M0_i_11 \n (.I0(wr_data_pntr[0]),\n .I1(wb_wr_data_addr_r[1]),\n .I2(wr_data_addr_le),\n .I3(reset_reg),\n .O(wb_wr_data_addr_w[1]));\n LUT5 #(\n .INIT(32'h02020F00)) \n \\write_buffer.wr_buffer_ram[0].RAM32M0_i_12 \n (.I0(app_wdf_rdy_r_copy3),\n .I1(app_wdf_end_r1),\n .I2(reset_reg),\n .I3(wb_wr_data_addr0_r),\n .I4(app_wdf_wren_r1),\n .O(wb_wr_data_addr0_ns));\n (* SOFT_HLUTNM = \"soft_lutpair1512\" *) \n LUT3 #(\n .INIT(8'h80)) \n \\write_buffer.wr_buffer_ram[0].RAM32M0_i_13 \n (.I0(app_wdf_wren_r1),\n .I1(app_wdf_end_r1),\n .I2(app_wdf_rdy_r_copy1),\n .O(p_0_in__0_0));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[0].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[5]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[5]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[5]),\n .O(wr_buf_in_data[5]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[0].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[4]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[4]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[4]),\n .O(wr_buf_in_data[4]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[0].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[3]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[3]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[3]),\n .O(wr_buf_in_data[3]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[0].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[2]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[2]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[2]),\n .O(wr_buf_in_data[2]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[0].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[1]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[1]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[1]),\n .O(wr_buf_in_data[1]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[0].RAM32M0_i_7 \n (.I0(wready_reg_rep__1[0]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[0]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[0]),\n .O(wr_buf_in_data[0]));\n LUT4 #(\n .INIT(16'h00AC)) \n \\write_buffer.wr_buffer_ram[0].RAM32M0_i_8 \n (.I0(wr_data_pntr[3]),\n .I1(wb_wr_data_addr_r[4]),\n .I2(wr_data_addr_le),\n .I3(reset_reg),\n .O(wb_wr_data_addr_w[4]));\n LUT4 #(\n .INIT(16'h00AC)) \n \\write_buffer.wr_buffer_ram[0].RAM32M0_i_9 \n (.I0(wr_data_pntr[2]),\n .I1(wb_wr_data_addr_r[3]),\n .I2(wr_data_addr_le),\n .I3(reset_reg),\n .O(wb_wr_data_addr_w[3]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[10].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[65:64]),\n .DIB(wr_buf_in_data[63:62]),\n .DIC(wr_buf_in_data[61:60]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[65:64]),\n .DOB(wr_buf_out_data_w[63:62]),\n .DOC(wr_buf_out_data_w[61:60]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[10].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[10].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[65]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[65]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[65]),\n .O(wr_buf_in_data[65]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[10].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[64]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[64]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[64]),\n .O(wr_buf_in_data[64]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[10].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[63]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[63]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[63]),\n .O(wr_buf_in_data[63]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[10].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[62]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[62]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[62]),\n .O(wr_buf_in_data[62]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[10].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[61]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[61]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[61]),\n .O(wr_buf_in_data[61]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[10].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[60]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[60]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[60]),\n .O(wr_buf_in_data[60]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[11].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[71:70]),\n .DIB(wr_buf_in_data[69:68]),\n .DIC(wr_buf_in_data[67:66]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[71:70]),\n .DOB(wr_buf_out_data_w[69:68]),\n .DOC(wr_buf_out_data_w[67:66]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[11].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[11].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[71]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[71]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[71]),\n .O(wr_buf_in_data[71]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[11].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[70]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[70]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[70]),\n .O(wr_buf_in_data[70]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[11].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[69]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[69]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[69]),\n .O(wr_buf_in_data[69]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[11].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[68]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[68]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[68]),\n .O(wr_buf_in_data[68]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[11].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[67]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[67]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[67]),\n .O(wr_buf_in_data[67]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[11].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[66]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[66]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[66]),\n .O(wr_buf_in_data[66]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[12].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[77:76]),\n .DIB(wr_buf_in_data[75:74]),\n .DIC(wr_buf_in_data[73:72]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[77:76]),\n .DOB(wr_buf_out_data_w[75:74]),\n .DOC(wr_buf_out_data_w[73:72]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[12].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[12].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[77]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[77]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[77]),\n .O(wr_buf_in_data[77]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[12].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[76]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[76]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[76]),\n .O(wr_buf_in_data[76]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[12].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[75]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[75]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[75]),\n .O(wr_buf_in_data[75]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[12].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[74]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[74]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[74]),\n .O(wr_buf_in_data[74]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[12].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[73]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[73]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[73]),\n .O(wr_buf_in_data[73]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[12].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[72]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[72]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[72]),\n .O(wr_buf_in_data[72]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[13].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[83:82]),\n .DIB(wr_buf_in_data[81:80]),\n .DIC(wr_buf_in_data[79:78]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[83:82]),\n .DOB(wr_buf_out_data_w[81:80]),\n .DOC(wr_buf_out_data_w[79:78]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[13].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[13].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[83]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[83]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[83]),\n .O(wr_buf_in_data[83]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[13].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[82]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[82]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[82]),\n .O(wr_buf_in_data[82]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[13].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[81]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[81]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[81]),\n .O(wr_buf_in_data[81]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[13].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[80]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[80]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[80]),\n .O(wr_buf_in_data[80]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[13].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[79]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[79]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[79]),\n .O(wr_buf_in_data[79]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[13].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[78]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[78]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[78]),\n .O(wr_buf_in_data[78]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[14].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[89:88]),\n .DIB(wr_buf_in_data[87:86]),\n .DIC(wr_buf_in_data[85:84]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[89:88]),\n .DOB(wr_buf_out_data_w[87:86]),\n .DOC(wr_buf_out_data_w[85:84]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[14].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[14].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[89]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[89]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[89]),\n .O(wr_buf_in_data[89]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[14].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[88]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[88]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[88]),\n .O(wr_buf_in_data[88]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[14].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[87]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[87]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[87]),\n .O(wr_buf_in_data[87]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[14].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[86]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[86]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[86]),\n .O(wr_buf_in_data[86]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[14].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[85]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[85]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[85]),\n .O(wr_buf_in_data[85]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[14].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[84]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[84]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[84]),\n .O(wr_buf_in_data[84]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[15].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[95:94]),\n .DIB(wr_buf_in_data[93:92]),\n .DIC(wr_buf_in_data[91:90]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[95:94]),\n .DOB(wr_buf_out_data_w[93:92]),\n .DOC(wr_buf_out_data_w[91:90]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[15].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[15].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[95]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[95]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[95]),\n .O(wr_buf_in_data[95]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[15].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[94]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[94]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[94]),\n .O(wr_buf_in_data[94]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[15].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[93]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[93]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[93]),\n .O(wr_buf_in_data[93]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[15].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[92]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[92]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[92]),\n .O(wr_buf_in_data[92]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[15].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[91]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[91]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[91]),\n .O(wr_buf_in_data[91]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[15].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[90]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[90]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[90]),\n .O(wr_buf_in_data[90]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[16].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[101:100]),\n .DIB(wr_buf_in_data[99:98]),\n .DIC(wr_buf_in_data[97:96]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[101:100]),\n .DOB(wr_buf_out_data_w[99:98]),\n .DOC(wr_buf_out_data_w[97:96]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[16].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[16].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[101]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[101]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[101]),\n .O(wr_buf_in_data[101]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[16].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[100]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[100]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[100]),\n .O(wr_buf_in_data[100]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[16].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[99]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[99]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[99]),\n .O(wr_buf_in_data[99]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[16].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[98]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[98]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[98]),\n .O(wr_buf_in_data[98]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[16].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[97]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[97]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[97]),\n .O(wr_buf_in_data[97]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[16].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[96]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[96]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[96]),\n .O(wr_buf_in_data[96]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[17].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[107:106]),\n .DIB(wr_buf_in_data[105:104]),\n .DIC(wr_buf_in_data[103:102]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[107:106]),\n .DOB(wr_buf_out_data_w[105:104]),\n .DOC(wr_buf_out_data_w[103:102]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[17].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[17].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[107]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[107]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[107]),\n .O(wr_buf_in_data[107]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[17].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[106]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[106]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[106]),\n .O(wr_buf_in_data[106]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[17].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[105]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[105]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[105]),\n .O(wr_buf_in_data[105]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[17].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[104]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[104]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[104]),\n .O(wr_buf_in_data[104]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[17].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[103]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[103]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[103]),\n .O(wr_buf_in_data[103]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[17].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[102]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[102]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[102]),\n .O(wr_buf_in_data[102]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[18].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[113:112]),\n .DIB(wr_buf_in_data[111:110]),\n .DIC(wr_buf_in_data[109:108]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[113:112]),\n .DOB(wr_buf_out_data_w[111:110]),\n .DOC(wr_buf_out_data_w[109:108]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[18].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[18].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[113]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[113]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[113]),\n .O(wr_buf_in_data[113]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[18].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[112]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[112]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[112]),\n .O(wr_buf_in_data[112]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[18].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[111]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[111]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[111]),\n .O(wr_buf_in_data[111]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[18].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[110]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[110]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[110]),\n .O(wr_buf_in_data[110]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[18].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[109]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[109]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[109]),\n .O(wr_buf_in_data[109]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[18].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[108]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[108]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[108]),\n .O(wr_buf_in_data[108]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[19].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[119:118]),\n .DIB(wr_buf_in_data[117:116]),\n .DIC(wr_buf_in_data[115:114]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[119:118]),\n .DOB(wr_buf_out_data_w[117:116]),\n .DOC(wr_buf_out_data_w[115:114]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[19].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[19].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[119]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[119]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[119]),\n .O(wr_buf_in_data[119]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[19].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[118]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[118]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[118]),\n .O(wr_buf_in_data[118]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[19].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[117]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[117]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[117]),\n .O(wr_buf_in_data[117]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[19].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[116]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[116]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[116]),\n .O(wr_buf_in_data[116]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[19].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[115]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[115]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[115]),\n .O(wr_buf_in_data[115]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[19].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[114]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[114]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[114]),\n .O(wr_buf_in_data[114]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[1].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[11:10]),\n .DIB(wr_buf_in_data[9:8]),\n .DIC(wr_buf_in_data[7:6]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[11:10]),\n .DOB(wr_buf_out_data_w[9:8]),\n .DOC(wr_buf_out_data_w[7:6]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[1].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[1].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[11]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[11]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[11]),\n .O(wr_buf_in_data[11]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[1].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[10]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[10]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[10]),\n .O(wr_buf_in_data[10]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[1].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[9]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[9]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[9]),\n .O(wr_buf_in_data[9]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[1].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[8]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[8]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[8]),\n .O(wr_buf_in_data[8]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[1].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[7]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[7]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[7]),\n .O(wr_buf_in_data[7]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[1].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[6]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[6]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[6]),\n .O(wr_buf_in_data[6]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[20].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[125:124]),\n .DIB(wr_buf_in_data[123:122]),\n .DIC(wr_buf_in_data[121:120]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[125:124]),\n .DOB(wr_buf_out_data_w[123:122]),\n .DOC(wr_buf_out_data_w[121:120]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[20].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[20].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[125]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[125]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[125]),\n .O(wr_buf_in_data[125]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[20].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[124]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[124]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[124]),\n .O(wr_buf_in_data[124]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[20].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[123]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[123]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[123]),\n .O(wr_buf_in_data[123]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[20].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[122]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[122]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[122]),\n .O(wr_buf_in_data[122]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[20].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[121]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[121]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[121]),\n .O(wr_buf_in_data[121]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[20].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[120]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[120]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[120]),\n .O(wr_buf_in_data[120]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[21].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[131:130]),\n .DIB(wr_buf_in_data[129:128]),\n .DIC(wr_buf_in_data[127:126]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[131:130]),\n .DOB(wr_buf_out_data_w[129:128]),\n .DOC(wr_buf_out_data_w[127:126]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[21].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[21].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[131]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[131]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[131]),\n .O(wr_buf_in_data[131]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[21].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[130]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[130]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[130]),\n .O(wr_buf_in_data[130]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[21].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[129]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[129]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[129]),\n .O(wr_buf_in_data[129]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[21].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[128]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[128]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[128]),\n .O(wr_buf_in_data[128]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[21].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[127]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[127]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[127]),\n .O(wr_buf_in_data[127]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[21].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[126]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[126]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[126]),\n .O(wr_buf_in_data[126]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[22].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[137:136]),\n .DIB(wr_buf_in_data[135:134]),\n .DIC(wr_buf_in_data[133:132]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[137:136]),\n .DOB(wr_buf_out_data_w[135:134]),\n .DOC(wr_buf_out_data_w[133:132]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[22].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[22].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[137]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[137]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[137]),\n .O(wr_buf_in_data[137]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[22].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[136]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[136]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[136]),\n .O(wr_buf_in_data[136]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[22].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[135]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[135]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[135]),\n .O(wr_buf_in_data[135]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[22].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[134]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[134]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[134]),\n .O(wr_buf_in_data[134]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[22].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[133]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[133]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[133]),\n .O(wr_buf_in_data[133]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[22].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[132]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[132]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[132]),\n .O(wr_buf_in_data[132]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[23].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[143:142]),\n .DIB(wr_buf_in_data[141:140]),\n .DIC(wr_buf_in_data[139:138]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[143:142]),\n .DOB(wr_buf_out_data_w[141:140]),\n .DOC(wr_buf_out_data_w[139:138]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[23].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[23].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[143]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[143]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[143]),\n .O(wr_buf_in_data[143]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[23].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[142]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[142]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[142]),\n .O(wr_buf_in_data[142]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[23].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[141]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[141]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[141]),\n .O(wr_buf_in_data[141]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[23].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[140]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[140]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[140]),\n .O(wr_buf_in_data[140]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[23].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[139]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[139]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[139]),\n .O(wr_buf_in_data[139]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[23].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[138]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[138]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[138]),\n .O(wr_buf_in_data[138]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[24].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[149:148]),\n .DIB(wr_buf_in_data[147:146]),\n .DIC(wr_buf_in_data[145:144]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[149:148]),\n .DOB(wr_buf_out_data_w[147:146]),\n .DOC(wr_buf_out_data_w[145:144]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[24].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[24].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[149]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[149]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[149]),\n .O(wr_buf_in_data[149]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[24].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[148]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[148]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[148]),\n .O(wr_buf_in_data[148]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[24].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[147]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[147]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[147]),\n .O(wr_buf_in_data[147]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[24].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[146]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[146]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[146]),\n .O(wr_buf_in_data[146]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[24].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[145]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[145]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[145]),\n .O(wr_buf_in_data[145]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[24].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[144]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[144]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[144]),\n .O(wr_buf_in_data[144]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[25].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[155:154]),\n .DIB(wr_buf_in_data[153:152]),\n .DIC(wr_buf_in_data[151:150]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[155:154]),\n .DOB(wr_buf_out_data_w[153:152]),\n .DOC(wr_buf_out_data_w[151:150]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[25].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[25].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[155]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[155]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[155]),\n .O(wr_buf_in_data[155]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[25].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[154]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[154]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[154]),\n .O(wr_buf_in_data[154]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[25].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[153]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[153]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[153]),\n .O(wr_buf_in_data[153]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[25].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[152]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[152]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[152]),\n .O(wr_buf_in_data[152]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[25].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[151]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[151]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[151]),\n .O(wr_buf_in_data[151]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[25].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[150]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[150]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[150]),\n .O(wr_buf_in_data[150]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[26].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[161:160]),\n .DIB(wr_buf_in_data[159:158]),\n .DIC(wr_buf_in_data[157:156]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[161:160]),\n .DOB(wr_buf_out_data_w[159:158]),\n .DOC(wr_buf_out_data_w[157:156]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[26].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[26].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[161]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[161]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[161]),\n .O(wr_buf_in_data[161]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[26].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[160]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[160]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[160]),\n .O(wr_buf_in_data[160]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[26].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[159]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[159]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[159]),\n .O(wr_buf_in_data[159]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[26].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[158]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[158]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[158]),\n .O(wr_buf_in_data[158]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[26].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[157]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[157]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[157]),\n .O(wr_buf_in_data[157]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[26].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[156]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[156]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[156]),\n .O(wr_buf_in_data[156]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[27].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[167:166]),\n .DIB(wr_buf_in_data[165:164]),\n .DIC(wr_buf_in_data[163:162]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[167:166]),\n .DOB(wr_buf_out_data_w[165:164]),\n .DOC(wr_buf_out_data_w[163:162]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[27].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[27].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[167]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[167]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[167]),\n .O(wr_buf_in_data[167]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[27].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[166]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[166]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[166]),\n .O(wr_buf_in_data[166]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[27].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[165]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[165]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[165]),\n .O(wr_buf_in_data[165]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[27].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[164]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[164]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[164]),\n .O(wr_buf_in_data[164]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[27].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[163]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[163]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[163]),\n .O(wr_buf_in_data[163]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[27].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[162]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[162]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[162]),\n .O(wr_buf_in_data[162]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[28].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[173:172]),\n .DIB(wr_buf_in_data[171:170]),\n .DIC(wr_buf_in_data[169:168]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[173:172]),\n .DOB(wr_buf_out_data_w[171:170]),\n .DOC(wr_buf_out_data_w[169:168]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[28].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[28].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[173]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[173]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[173]),\n .O(wr_buf_in_data[173]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[28].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[172]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[172]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[172]),\n .O(wr_buf_in_data[172]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[28].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[171]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[171]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[171]),\n .O(wr_buf_in_data[171]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[28].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[170]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[170]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[170]),\n .O(wr_buf_in_data[170]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[28].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[169]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[169]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[169]),\n .O(wr_buf_in_data[169]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[28].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[168]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[168]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[168]),\n .O(wr_buf_in_data[168]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[29].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[179:178]),\n .DIB(wr_buf_in_data[177:176]),\n .DIC(wr_buf_in_data[175:174]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[179:178]),\n .DOB(wr_buf_out_data_w[177:176]),\n .DOC(wr_buf_out_data_w[175:174]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[29].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[29].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[179]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[179]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[179]),\n .O(wr_buf_in_data[179]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[29].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[178]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[178]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[178]),\n .O(wr_buf_in_data[178]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[29].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[177]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[177]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[177]),\n .O(wr_buf_in_data[177]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[29].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[176]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[176]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[176]),\n .O(wr_buf_in_data[176]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[29].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[175]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[175]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[175]),\n .O(wr_buf_in_data[175]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[29].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[174]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[174]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[174]),\n .O(wr_buf_in_data[174]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[2].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[17:16]),\n .DIB(wr_buf_in_data[15:14]),\n .DIC(wr_buf_in_data[13:12]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[17:16]),\n .DOB(wr_buf_out_data_w[15:14]),\n .DOC(wr_buf_out_data_w[13:12]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[2].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[2].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[17]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[17]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[17]),\n .O(wr_buf_in_data[17]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[2].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[16]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[16]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[16]),\n .O(wr_buf_in_data[16]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[2].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[15]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[15]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[15]),\n .O(wr_buf_in_data[15]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[2].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[14]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[14]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[14]),\n .O(wr_buf_in_data[14]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[2].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[13]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[13]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[13]),\n .O(wr_buf_in_data[13]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[2].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[12]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[12]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[12]),\n .O(wr_buf_in_data[12]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[30].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[185:184]),\n .DIB(wr_buf_in_data[183:182]),\n .DIC(wr_buf_in_data[181:180]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[185:184]),\n .DOB(wr_buf_out_data_w[183:182]),\n .DOC(wr_buf_out_data_w[181:180]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[30].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[30].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[185]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[185]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[185]),\n .O(wr_buf_in_data[185]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[30].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[184]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[184]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[184]),\n .O(wr_buf_in_data[184]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[30].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[183]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[183]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[183]),\n .O(wr_buf_in_data[183]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[30].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[182]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[182]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[182]),\n .O(wr_buf_in_data[182]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[30].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[181]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[181]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[181]),\n .O(wr_buf_in_data[181]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[30].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[180]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[180]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[180]),\n .O(wr_buf_in_data[180]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[31].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[191:190]),\n .DIB(wr_buf_in_data[189:188]),\n .DIC(wr_buf_in_data[187:186]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[191:190]),\n .DOB(wr_buf_out_data_w[189:188]),\n .DOC(wr_buf_out_data_w[187:186]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[31].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[31].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[191]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[191]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[191]),\n .O(wr_buf_in_data[191]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[31].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[190]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[190]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[190]),\n .O(wr_buf_in_data[190]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[31].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[189]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[189]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[189]),\n .O(wr_buf_in_data[189]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[31].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[188]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[188]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[188]),\n .O(wr_buf_in_data[188]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[31].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[187]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[187]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[187]),\n .O(wr_buf_in_data[187]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[31].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[186]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[186]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[186]),\n .O(wr_buf_in_data[186]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[32].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[197:196]),\n .DIB(wr_buf_in_data[195:194]),\n .DIC(wr_buf_in_data[193:192]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[197:196]),\n .DOB(wr_buf_out_data_w[195:194]),\n .DOC(wr_buf_out_data_w[193:192]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[32].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[32].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[197]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[197]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[197]),\n .O(wr_buf_in_data[197]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[32].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[196]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[196]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[196]),\n .O(wr_buf_in_data[196]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[32].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[195]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[195]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[195]),\n .O(wr_buf_in_data[195]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[32].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[194]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[194]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[194]),\n .O(wr_buf_in_data[194]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[32].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[193]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[193]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[193]),\n .O(wr_buf_in_data[193]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[32].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[192]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[192]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[192]),\n .O(wr_buf_in_data[192]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[33].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[203:202]),\n .DIB(wr_buf_in_data[201:200]),\n .DIC(wr_buf_in_data[199:198]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[203:202]),\n .DOB(wr_buf_out_data_w[201:200]),\n .DOC(wr_buf_out_data_w[199:198]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[33].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[33].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[203]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[203]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[203]),\n .O(wr_buf_in_data[203]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[33].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[202]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[202]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[202]),\n .O(wr_buf_in_data[202]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[33].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[201]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[201]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[201]),\n .O(wr_buf_in_data[201]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[33].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[200]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[200]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[200]),\n .O(wr_buf_in_data[200]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[33].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[199]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[199]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[199]),\n .O(wr_buf_in_data[199]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[33].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[198]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[198]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[198]),\n .O(wr_buf_in_data[198]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[34].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[209:208]),\n .DIB(wr_buf_in_data[207:206]),\n .DIC(wr_buf_in_data[205:204]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[209:208]),\n .DOB(wr_buf_out_data_w[207:206]),\n .DOC(wr_buf_out_data_w[205:204]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[34].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[34].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[209]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[209]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[209]),\n .O(wr_buf_in_data[209]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[34].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[208]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[208]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[208]),\n .O(wr_buf_in_data[208]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[34].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[207]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[207]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[207]),\n .O(wr_buf_in_data[207]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[34].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[206]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[206]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[206]),\n .O(wr_buf_in_data[206]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[34].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[205]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[205]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[205]),\n .O(wr_buf_in_data[205]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[34].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[204]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[204]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[204]),\n .O(wr_buf_in_data[204]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[35].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[215:214]),\n .DIB(wr_buf_in_data[213:212]),\n .DIC(wr_buf_in_data[211:210]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[215:214]),\n .DOB(wr_buf_out_data_w[213:212]),\n .DOC(wr_buf_out_data_w[211:210]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[35].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[35].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[215]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[215]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[215]),\n .O(wr_buf_in_data[215]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[35].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[214]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[214]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[214]),\n .O(wr_buf_in_data[214]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[35].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[213]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[213]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[213]),\n .O(wr_buf_in_data[213]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[35].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[212]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[212]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[212]),\n .O(wr_buf_in_data[212]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[35].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[211]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[211]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[211]),\n .O(wr_buf_in_data[211]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[35].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[210]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[210]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[210]),\n .O(wr_buf_in_data[210]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[36].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[221:220]),\n .DIB(wr_buf_in_data[219:218]),\n .DIC(wr_buf_in_data[217:216]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[221:220]),\n .DOB(wr_buf_out_data_w[219:218]),\n .DOC(wr_buf_out_data_w[217:216]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[36].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[36].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[221]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[221]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[221]),\n .O(wr_buf_in_data[221]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[36].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[220]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[220]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[220]),\n .O(wr_buf_in_data[220]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[36].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[219]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[219]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[219]),\n .O(wr_buf_in_data[219]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[36].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[218]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[218]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[218]),\n .O(wr_buf_in_data[218]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[36].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[217]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[217]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[217]),\n .O(wr_buf_in_data[217]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[36].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[216]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[216]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[216]),\n .O(wr_buf_in_data[216]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[37].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[227:226]),\n .DIB(wr_buf_in_data[225:224]),\n .DIC(wr_buf_in_data[223:222]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[227:226]),\n .DOB(wr_buf_out_data_w[225:224]),\n .DOC(wr_buf_out_data_w[223:222]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[37].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[37].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[227]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[227]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[227]),\n .O(wr_buf_in_data[227]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[37].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[226]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[226]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[226]),\n .O(wr_buf_in_data[226]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[37].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[225]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[225]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[225]),\n .O(wr_buf_in_data[225]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[37].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[224]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[224]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[224]),\n .O(wr_buf_in_data[224]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[37].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[223]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[223]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[223]),\n .O(wr_buf_in_data[223]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[37].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[222]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[222]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[222]),\n .O(wr_buf_in_data[222]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[38].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[233:232]),\n .DIB(wr_buf_in_data[231:230]),\n .DIC(wr_buf_in_data[229:228]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[233:232]),\n .DOB(wr_buf_out_data_w[231:230]),\n .DOC(wr_buf_out_data_w[229:228]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[38].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[38].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[233]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[233]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[233]),\n .O(wr_buf_in_data[233]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[38].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[232]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[232]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[232]),\n .O(wr_buf_in_data[232]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[38].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[231]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[231]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[231]),\n .O(wr_buf_in_data[231]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[38].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[230]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[230]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[230]),\n .O(wr_buf_in_data[230]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[38].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[229]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[229]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[229]),\n .O(wr_buf_in_data[229]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[38].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[228]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[228]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[228]),\n .O(wr_buf_in_data[228]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[39].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[239:238]),\n .DIB(wr_buf_in_data[237:236]),\n .DIC(wr_buf_in_data[235:234]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[239:238]),\n .DOB(wr_buf_out_data_w[237:236]),\n .DOC(wr_buf_out_data_w[235:234]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[39].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[39].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[239]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[239]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[239]),\n .O(wr_buf_in_data[239]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[39].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[238]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[238]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[238]),\n .O(wr_buf_in_data[238]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[39].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[237]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[237]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[237]),\n .O(wr_buf_in_data[237]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[39].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[236]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[236]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[236]),\n .O(wr_buf_in_data[236]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[39].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[235]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[235]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[235]),\n .O(wr_buf_in_data[235]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[39].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[234]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[234]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[234]),\n .O(wr_buf_in_data[234]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[3].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[23:22]),\n .DIB(wr_buf_in_data[21:20]),\n .DIC(wr_buf_in_data[19:18]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[23:22]),\n .DOB(wr_buf_out_data_w[21:20]),\n .DOC(wr_buf_out_data_w[19:18]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[3].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[3].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[23]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[23]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[23]),\n .O(wr_buf_in_data[23]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[3].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[22]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[22]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[22]),\n .O(wr_buf_in_data[22]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[3].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[21]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[21]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[21]),\n .O(wr_buf_in_data[21]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[3].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[20]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[20]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[20]),\n .O(wr_buf_in_data[20]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[3].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[19]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[19]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[19]),\n .O(wr_buf_in_data[19]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[3].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[18]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[18]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[18]),\n .O(wr_buf_in_data[18]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[40].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[245:244]),\n .DIB(wr_buf_in_data[243:242]),\n .DIC(wr_buf_in_data[241:240]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[245:244]),\n .DOB(wr_buf_out_data_w[243:242]),\n .DOC(wr_buf_out_data_w[241:240]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[40].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[40].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[245]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[245]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[245]),\n .O(wr_buf_in_data[245]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[40].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[244]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[244]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[244]),\n .O(wr_buf_in_data[244]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[40].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[243]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[243]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[243]),\n .O(wr_buf_in_data[243]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[40].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[242]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[242]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[242]),\n .O(wr_buf_in_data[242]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[40].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[241]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[241]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[241]),\n .O(wr_buf_in_data[241]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[40].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[240]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[240]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[240]),\n .O(wr_buf_in_data[240]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[41].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[251:250]),\n .DIB(wr_buf_in_data[249:248]),\n .DIC(wr_buf_in_data[247:246]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[251:250]),\n .DOB(wr_buf_out_data_w[249:248]),\n .DOC(wr_buf_out_data_w[247:246]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[41].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[41].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[251]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[251]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[251]),\n .O(wr_buf_in_data[251]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[41].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[250]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[250]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[250]),\n .O(wr_buf_in_data[250]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[41].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[249]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[249]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[249]),\n .O(wr_buf_in_data[249]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[41].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[248]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[248]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[248]),\n .O(wr_buf_in_data[248]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[41].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[247]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[247]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[247]),\n .O(wr_buf_in_data[247]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[41].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[246]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[246]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[246]),\n .O(wr_buf_in_data[246]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[42].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[257:256]),\n .DIB(wr_buf_in_data[255:254]),\n .DIC(wr_buf_in_data[253:252]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[257:256]),\n .DOB(wr_buf_out_data_w[255:254]),\n .DOC(wr_buf_out_data_w[253:252]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[42].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[42].RAM32M0_i_1 \n (.I0(D[1]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[1]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[1]),\n .O(wr_buf_in_data[257]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[42].RAM32M0_i_2 \n (.I0(D[0]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[0]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[0]),\n .O(wr_buf_in_data[256]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[42].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[255]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[255]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[255]),\n .O(wr_buf_in_data[255]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[42].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[254]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[254]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[254]),\n .O(wr_buf_in_data[254]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[42].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[253]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[253]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[253]),\n .O(wr_buf_in_data[253]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[42].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[252]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[252]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[252]),\n .O(wr_buf_in_data[252]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[43].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[263:262]),\n .DIB(wr_buf_in_data[261:260]),\n .DIC(wr_buf_in_data[259:258]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[263:262]),\n .DOB(wr_buf_out_data_w[261:260]),\n .DOC(wr_buf_out_data_w[259:258]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[43].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[43].RAM32M0_i_1 \n (.I0(D[7]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[7]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[7]),\n .O(wr_buf_in_data[263]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[43].RAM32M0_i_2 \n (.I0(D[6]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[6]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[6]),\n .O(wr_buf_in_data[262]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[43].RAM32M0_i_3 \n (.I0(D[5]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[5]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[5]),\n .O(wr_buf_in_data[261]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[43].RAM32M0_i_4 \n (.I0(D[4]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[4]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[4]),\n .O(wr_buf_in_data[260]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[43].RAM32M0_i_5 \n (.I0(D[3]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[3]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[3]),\n .O(wr_buf_in_data[259]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[43].RAM32M0_i_6 \n (.I0(D[2]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[2]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[2]),\n .O(wr_buf_in_data[258]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[44].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[269:268]),\n .DIB(wr_buf_in_data[267:266]),\n .DIC(wr_buf_in_data[265:264]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[269:268]),\n .DOB(wr_buf_out_data_w[267:266]),\n .DOC(wr_buf_out_data_w[265:264]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[44].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[44].RAM32M0_i_1 \n (.I0(D[13]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[13]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[13]),\n .O(wr_buf_in_data[269]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[44].RAM32M0_i_2 \n (.I0(D[12]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[12]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[12]),\n .O(wr_buf_in_data[268]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[44].RAM32M0_i_3 \n (.I0(D[11]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[11]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[11]),\n .O(wr_buf_in_data[267]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[44].RAM32M0_i_4 \n (.I0(D[10]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[10]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[10]),\n .O(wr_buf_in_data[266]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[44].RAM32M0_i_5 \n (.I0(D[9]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[9]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[9]),\n .O(wr_buf_in_data[265]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[44].RAM32M0_i_6 \n (.I0(D[8]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[8]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[8]),\n .O(wr_buf_in_data[264]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[45].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[275:274]),\n .DIB(wr_buf_in_data[273:272]),\n .DIC(wr_buf_in_data[271:270]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[275:274]),\n .DOB(wr_buf_out_data_w[273:272]),\n .DOC(wr_buf_out_data_w[271:270]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[45].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[45].RAM32M0_i_1 \n (.I0(D[19]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[19]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[19]),\n .O(wr_buf_in_data[275]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[45].RAM32M0_i_2 \n (.I0(D[18]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[18]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[18]),\n .O(wr_buf_in_data[274]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[45].RAM32M0_i_3 \n (.I0(D[17]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[17]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[17]),\n .O(wr_buf_in_data[273]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[45].RAM32M0_i_4 \n (.I0(D[16]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[16]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[16]),\n .O(wr_buf_in_data[272]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[45].RAM32M0_i_5 \n (.I0(D[15]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[15]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[15]),\n .O(wr_buf_in_data[271]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[45].RAM32M0_i_6 \n (.I0(D[14]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[14]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[14]),\n .O(wr_buf_in_data[270]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[46].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[281:280]),\n .DIB(wr_buf_in_data[279:278]),\n .DIC(wr_buf_in_data[277:276]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[281:280]),\n .DOB(wr_buf_out_data_w[279:278]),\n .DOC(wr_buf_out_data_w[277:276]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[46].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[46].RAM32M0_i_1 \n (.I0(D[25]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[25]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[25]),\n .O(wr_buf_in_data[281]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[46].RAM32M0_i_2 \n (.I0(D[24]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[24]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[24]),\n .O(wr_buf_in_data[280]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[46].RAM32M0_i_3 \n (.I0(D[23]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[23]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[23]),\n .O(wr_buf_in_data[279]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[46].RAM32M0_i_4 \n (.I0(D[22]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[22]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[22]),\n .O(wr_buf_in_data[278]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[46].RAM32M0_i_5 \n (.I0(D[21]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[21]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[21]),\n .O(wr_buf_in_data[277]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[46].RAM32M0_i_6 \n (.I0(D[20]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[20]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[20]),\n .O(wr_buf_in_data[276]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[47].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[287:286]),\n .DIB(wr_buf_in_data[285:284]),\n .DIC(wr_buf_in_data[283:282]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[287:286]),\n .DOB(wr_buf_out_data_w[285:284]),\n .DOC(wr_buf_out_data_w[283:282]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[47].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[47].RAM32M0_i_1 \n (.I0(D[31]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[31]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[31]),\n .O(wr_buf_in_data[287]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[47].RAM32M0_i_2 \n (.I0(D[30]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[30]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[30]),\n .O(wr_buf_in_data[286]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[47].RAM32M0_i_3 \n (.I0(D[29]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[29]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[29]),\n .O(wr_buf_in_data[285]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[47].RAM32M0_i_4 \n (.I0(D[28]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[28]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[28]),\n .O(wr_buf_in_data[284]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[47].RAM32M0_i_5 \n (.I0(D[27]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[27]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[27]),\n .O(wr_buf_in_data[283]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[47].RAM32M0_i_6 \n (.I0(D[26]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_mask_reg[26]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_mask_r1[26]),\n .O(wr_buf_in_data[282]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[4].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[29:28]),\n .DIB(wr_buf_in_data[27:26]),\n .DIC(wr_buf_in_data[25:24]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[29:28]),\n .DOB(wr_buf_out_data_w[27:26]),\n .DOC(wr_buf_out_data_w[25:24]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[4].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[4].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[29]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[29]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[29]),\n .O(wr_buf_in_data[29]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[4].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[28]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[28]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[28]),\n .O(wr_buf_in_data[28]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[4].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[27]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[27]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[27]),\n .O(wr_buf_in_data[27]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[4].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[26]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[26]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[26]),\n .O(wr_buf_in_data[26]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[4].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[25]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[25]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[25]),\n .O(wr_buf_in_data[25]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[4].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[24]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[24]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[24]),\n .O(wr_buf_in_data[24]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[5].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[35:34]),\n .DIB(wr_buf_in_data[33:32]),\n .DIC(wr_buf_in_data[31:30]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[35:34]),\n .DOB(wr_buf_out_data_w[33:32]),\n .DOC(wr_buf_out_data_w[31:30]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[5].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[5].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[35]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[35]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[35]),\n .O(wr_buf_in_data[35]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[5].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[34]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[34]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[34]),\n .O(wr_buf_in_data[34]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[5].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[33]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[33]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[33]),\n .O(wr_buf_in_data[33]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[5].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[32]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[32]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[32]),\n .O(wr_buf_in_data[32]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[5].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[31]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[31]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[31]),\n .O(wr_buf_in_data[31]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[5].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[30]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[30]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[30]),\n .O(wr_buf_in_data[30]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[6].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[41:40]),\n .DIB(wr_buf_in_data[39:38]),\n .DIC(wr_buf_in_data[37:36]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[41:40]),\n .DOB(wr_buf_out_data_w[39:38]),\n .DOC(wr_buf_out_data_w[37:36]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[6].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[6].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[41]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[41]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[41]),\n .O(wr_buf_in_data[41]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[6].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[40]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[40]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[40]),\n .O(wr_buf_in_data[40]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[6].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[39]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[39]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[39]),\n .O(wr_buf_in_data[39]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[6].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[38]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[38]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[38]),\n .O(wr_buf_in_data[38]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[6].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[37]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[37]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[37]),\n .O(wr_buf_in_data[37]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[6].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[36]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[36]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[36]),\n .O(wr_buf_in_data[36]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[7].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[47:46]),\n .DIB(wr_buf_in_data[45:44]),\n .DIC(wr_buf_in_data[43:42]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[47:46]),\n .DOB(wr_buf_out_data_w[45:44]),\n .DOC(wr_buf_out_data_w[43:42]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[7].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[7].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[47]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[47]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[47]),\n .O(wr_buf_in_data[47]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[7].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[46]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[46]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[46]),\n .O(wr_buf_in_data[46]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[7].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[45]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[45]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[45]),\n .O(wr_buf_in_data[45]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[7].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[44]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[44]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[44]),\n .O(wr_buf_in_data[44]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[7].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[43]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[43]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[43]),\n .O(wr_buf_in_data[43]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[7].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[42]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[42]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[42]),\n .O(wr_buf_in_data[42]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[8].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[53:52]),\n .DIB(wr_buf_in_data[51:50]),\n .DIC(wr_buf_in_data[49:48]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[53:52]),\n .DOB(wr_buf_out_data_w[51:50]),\n .DOC(wr_buf_out_data_w[49:48]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[8].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[8].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[53]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[53]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[53]),\n .O(wr_buf_in_data[53]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[8].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[52]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[52]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[52]),\n .O(wr_buf_in_data[52]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[8].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[51]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[51]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[51]),\n .O(wr_buf_in_data[51]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[8].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[50]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[50]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[50]),\n .O(wr_buf_in_data[50]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[8].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[49]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[49]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[49]),\n .O(wr_buf_in_data[49]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[8].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[48]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[48]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[48]),\n .O(wr_buf_in_data[48]));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n RAM32M #(\n .INIT_A(64'h0000000000000000),\n .INIT_B(64'h0000000000000000),\n .INIT_C(64'h0000000000000000),\n .INIT_D(64'h0000000000000000),\n .IS_WCLK_INVERTED(1'b0)) \n \\write_buffer.wr_buffer_ram[9].RAM32M0 \n (.ADDRA({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRB({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRC({\\cmd_pipe_plus.wr_data_addr_reg[3] ,1'b0}),\n .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),\n .DIA(wr_buf_in_data[59:58]),\n .DIB(wr_buf_in_data[57:56]),\n .DIC(wr_buf_in_data[55:54]),\n .DID({1'b0,1'b0}),\n .DOA(wr_buf_out_data_w[59:58]),\n .DOB(wr_buf_out_data_w[57:56]),\n .DOC(wr_buf_out_data_w[55:54]),\n .DOD(\\NLW_write_buffer.wr_buffer_ram[9].RAM32M0_DOD_UNCONNECTED [1:0]),\n .WCLK(CLK),\n .WE(wdf_rdy_ns));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[9].RAM32M0_i_1 \n (.I0(wready_reg_rep__1[59]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[59]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[59]),\n .O(wr_buf_in_data[59]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[9].RAM32M0_i_2 \n (.I0(wready_reg_rep__1[58]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[58]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[58]),\n .O(wr_buf_in_data[58]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[9].RAM32M0_i_3 \n (.I0(wready_reg_rep__1[57]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[57]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[57]),\n .O(wr_buf_in_data[57]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[9].RAM32M0_i_4 \n (.I0(wready_reg_rep__1[56]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[56]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[56]),\n .O(wr_buf_in_data[56]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[9].RAM32M0_i_5 \n (.I0(wready_reg_rep__1[55]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[55]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[55]),\n .O(wr_buf_in_data[55]));\n LUT5 #(\n .INIT(32'hB8FFB800)) \n \\write_buffer.wr_buffer_ram[9].RAM32M0_i_6 \n (.I0(wready_reg_rep__1[54]),\n .I1(\\mc_app_wdf_mask_reg_reg[0] ),\n .I2(mc_app_wdf_data_reg[54]),\n .I3(app_wdf_rdy_r_copy2),\n .I4(app_wdf_data_r1[54]),\n .O(wr_buf_in_data[54]));\n FDRE \\write_data_control.wb_wr_data_addr0_r_reg \n (.C(CLK),\n .CE(1'b1),\n .D(wb_wr_data_addr0_ns),\n .Q(wb_wr_data_addr0_r),\n .R(1'b0));\n FDRE \\write_data_control.wb_wr_data_addr_r_reg[1] \n (.C(CLK),\n .CE(1'b1),\n .D(wb_wr_data_addr_w[1]),\n .Q(wb_wr_data_addr_r[1]),\n .R(1'b0));\n FDRE \\write_data_control.wb_wr_data_addr_r_reg[2] \n (.C(CLK),\n .CE(1'b1),\n .D(wb_wr_data_addr_w[2]),\n .Q(wb_wr_data_addr_r[2]),\n .R(1'b0));\n FDRE \\write_data_control.wb_wr_data_addr_r_reg[3] \n (.C(CLK),\n .CE(1'b1),\n .D(wb_wr_data_addr_w[3]),\n .Q(wb_wr_data_addr_r[3]),\n .R(1'b0));\n FDRE \\write_data_control.wb_wr_data_addr_r_reg[4] \n (.C(CLK),\n .CE(1'b1),\n .D(wb_wr_data_addr_w[4]),\n .Q(wb_wr_data_addr_r[4]),\n .R(1'b0));\n LUT1 #(\n .INIT(2'h1)) \n \\write_data_control.wr_data_indx_r[0]_i_1 \n (.I0(\\write_data_control.wr_data_indx_r_reg__0 [0]),\n .O(p_0_in__0__0[0]));\n LUT2 #(\n .INIT(4'h6)) \n \\write_data_control.wr_data_indx_r[1]_i_1 \n (.I0(\\write_data_control.wr_data_indx_r_reg__0 [0]),\n .I1(\\write_data_control.wr_data_indx_r_reg__0 [1]),\n .O(p_0_in__0__0[1]));\n (* SOFT_HLUTNM = \"soft_lutpair1516\" *) \n LUT3 #(\n .INIT(8'h78)) \n \\write_data_control.wr_data_indx_r[2]_i_1 \n (.I0(\\write_data_control.wr_data_indx_r_reg__0 [0]),\n .I1(\\write_data_control.wr_data_indx_r_reg__0 [1]),\n .I2(\\write_data_control.wr_data_indx_r_reg__0 [2]),\n .O(p_0_in__0__0[2]));\n LUT6 #(\n .INIT(64'hF000FFFF10001000)) \n \\write_data_control.wr_data_indx_r[3]_i_1 \n (.I0(\\occupied_counter.occ_cnt_reg_n_0_[15] ),\n .I1(p_4_in),\n .I2(p_0_in__0_0),\n .I3(\\rd_buf_indx.ram_init_done_r_lcl_reg ),\n .I4(app_wdf_rdy_r_copy1),\n .I5(p_0_in),\n .O(wr_data_addr_le));\n (* SOFT_HLUTNM = \"soft_lutpair1516\" *) \n LUT4 #(\n .INIT(16'h7F80)) \n \\write_data_control.wr_data_indx_r[3]_i_2 \n (.I0(\\write_data_control.wr_data_indx_r_reg__0 [2]),\n .I1(\\write_data_control.wr_data_indx_r_reg__0 [1]),\n .I2(\\write_data_control.wr_data_indx_r_reg__0 [0]),\n .I3(\\write_data_control.wr_data_indx_r_reg__0 [3]),\n .O(p_0_in__0__0[3]));\n FDSE \\write_data_control.wr_data_indx_r_reg[0] \n (.C(CLK),\n .CE(wr_data_addr_le),\n .D(p_0_in__0__0[0]),\n .Q(\\write_data_control.wr_data_indx_r_reg__0 [0]),\n .S(reset_reg));\n FDRE \\write_data_control.wr_data_indx_r_reg[1] \n (.C(CLK),\n .CE(wr_data_addr_le),\n .D(p_0_in__0__0[1]),\n .Q(\\write_data_control.wr_data_indx_r_reg__0 [1]),\n .R(reset_reg));\n FDRE \\write_data_control.wr_data_indx_r_reg[2] \n (.C(CLK),\n .CE(wr_data_addr_le),\n .D(p_0_in__0__0[2]),\n .Q(\\write_data_control.wr_data_indx_r_reg__0 [2]),\n .R(reset_reg));\n FDRE \\write_data_control.wr_data_indx_r_reg[3] \n (.C(CLK),\n .CE(wr_data_addr_le),\n .D(p_0_in__0__0[3]),\n .Q(\\write_data_control.wr_data_indx_r_reg__0 [3]),\n .R(reset_reg));\nendmodule\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if_stub.v", "content": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// --------------------------------------------------------------------------------\n// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016\n// Date : Tue Nov 15 09:09:09 2016\n// Host : david-xilinx-vm running 64-bit unknown\n// Command : write_verilog -force -mode synth_stub -rename_top ddr3_if -prefix\n// ddr3_if_ ddr3_if_stub.v\n// Design : ddr3_if\n// Purpose : Stub declaration of top-level module interface\n// Device : xc7k325tffg900-2\n// --------------------------------------------------------------------------------\n\n// This empty module with port declaration file causes synthesis tools to infer a black box for IP.\n// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.\n// Please paste the declaration into a Verilog source file or add the file as an additional source.\nmodule ddr3_if(ddr3_dq, ddr3_dqs_n, ddr3_dqs_p, ddr3_addr, \n ddr3_ba, ddr3_ras_n, ddr3_cas_n, ddr3_we_n, ddr3_reset_n, ddr3_ck_p, ddr3_ck_n, ddr3_cke, \n ddr3_cs_n, ddr3_dm, ddr3_odt, sys_clk_i, ui_clk, ui_clk_sync_rst, mmcm_locked, aresetn, \n app_sr_req, app_ref_req, app_zq_req, app_sr_active, app_ref_ack, app_zq_ack, s_axi_awid, \n s_axi_awaddr, s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, \n s_axi_awprot, s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, \n s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bready, s_axi_bid, s_axi_bresp, s_axi_bvalid, \n s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, \n s_axi_arcache, s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rready, \n s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, init_calib_complete, \n device_temp, sys_rst)\n/* synthesis syn_black_box black_box_pad_pin=\"ddr3_dq[31:0],ddr3_dqs_n[3:0],ddr3_dqs_p[3:0],ddr3_addr[14:0],ddr3_ba[2:0],ddr3_ras_n,ddr3_cas_n,ddr3_we_n,ddr3_reset_n,ddr3_ck_p[0:0],ddr3_ck_n[0:0],ddr3_cke[0:0],ddr3_cs_n[0:0],ddr3_dm[3:0],ddr3_odt[0:0],sys_clk_i,ui_clk,ui_clk_sync_rst,mmcm_locked,aresetn,app_sr_req,app_ref_req,app_zq_req,app_sr_active,app_ref_ack,app_zq_ack,s_axi_awid[0:0],s_axi_awaddr[29:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[255:0],s_axi_wstrb[31:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bready,s_axi_bid[0:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_arid[0:0],s_axi_araddr[29:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rready,s_axi_rid[0:0],s_axi_rdata[255:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,init_calib_complete,device_temp[11:0],sys_rst\" */;\n inout [31:0]ddr3_dq;\n inout [3:0]ddr3_dqs_n;\n inout [3:0]ddr3_dqs_p;\n output [14:0]ddr3_addr;\n output [2:0]ddr3_ba;\n output ddr3_ras_n;\n output ddr3_cas_n;\n output ddr3_we_n;\n output ddr3_reset_n;\n output [0:0]ddr3_ck_p;\n output [0:0]ddr3_ck_n;\n output [0:0]ddr3_cke;\n output [0:0]ddr3_cs_n;\n output [3:0]ddr3_dm;\n output [0:0]ddr3_odt;\n input sys_clk_i;\n output ui_clk;\n output ui_clk_sync_rst;\n output mmcm_locked;\n input aresetn;\n input app_sr_req;\n input app_ref_req;\n input app_zq_req;\n output app_sr_active;\n output app_ref_ack;\n output app_zq_ack;\n input [0:0]s_axi_awid;\n input [29:0]s_axi_awaddr;\n input [7:0]s_axi_awlen;\n input [2:0]s_axi_awsize;\n input [1:0]s_axi_awburst;\n input [0:0]s_axi_awlock;\n input [3:0]s_axi_awcache;\n input [2:0]s_axi_awprot;\n input [3:0]s_axi_awqos;\n input s_axi_awvalid;\n output s_axi_awready;\n input [255:0]s_axi_wdata;\n input [31:0]s_axi_wstrb;\n input s_axi_wlast;\n input s_axi_wvalid;\n output s_axi_wready;\n input s_axi_bready;\n output [0:0]s_axi_bid;\n output [1:0]s_axi_bresp;\n output s_axi_bvalid;\n input [0:0]s_axi_arid;\n input [29:0]s_axi_araddr;\n input [7:0]s_axi_arlen;\n input [2:0]s_axi_arsize;\n input [1:0]s_axi_arburst;\n input [0:0]s_axi_arlock;\n input [3:0]s_axi_arcache;\n input [2:0]s_axi_arprot;\n input [3:0]s_axi_arqos;\n input s_axi_arvalid;\n output s_axi_arready;\n input s_axi_rready;\n output [0:0]s_axi_rid;\n output [255:0]s_axi_rdata;\n output [1:0]s_axi_rresp;\n output s_axi_rlast;\n output s_axi_rvalid;\n output init_calib_complete;\n output [11:0]device_temp;\n input sys_rst;\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/mig_a.prj", "content": "\n\n\n ddr3_if\n 1\n 1\n OFF\n 1024\n ON\n Enabled\n xc7k325t-ffg900/-2\n 4.0\n No Buffer\n Use System Clock\n ACTIVE LOW\n FALSE\n 0\n OFF\n 0\n \n DDR3_SDRAM/Components/MT41J256m16XX-107\n 1112\n 2.0V\n 4:1\n 199.84\n 0\n 899\n 1.000\n 1\n 1\n 1\n 1\n 32\n 1\n 1\n Disabled\n Normal\n 4\n FALSE\n \n 15\n 10\n 3\n 1.5V\n ROW_BANK_COLUMN\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 8 - Fixed\n Sequential\n 13\n Normal\n No\n Slow Exit\n Enable\n RZQ/7\n Disable\n Enable\n RZQ/6\n 0\n Disabled\n Enabled\n Output Buffer Enabled\n Full Array\n 9\n Enabled\n Normal\n Dynamic ODT off\n AXI\n \n RD_PRI_REG_STARVE_LIMIT\n 30\n 256\n 1\n 0\n \n \n\n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll.v", "content": "\n// file: dvi_pll.v\n// \n// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n//----------------------------------------------------------------------------\n// User entered comments\n//----------------------------------------------------------------------------\n// None\n//\n//----------------------------------------------------------------------------\n// Output Output Phase Duty Cycle Pk-to-Pk Phase\n// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)\n//----------------------------------------------------------------------------\n// pixel_clock___148.000______0.000______50.0______111.449____139.507\n// dvi_bit_clock___740.000______0.000______50.0_______87.091____139.507\n//\n//----------------------------------------------------------------------------\n// Input Clock Freq (MHz) Input Jitter (UI)\n//----------------------------------------------------------------------------\n// __primary_____________200____________0.010\n\n`timescale 1ps/1ps\n\n(* CORE_GENERATION_INFO = \"dvi_pll,clk_wiz_v5_3_2_0,{component_name=dvi_pll,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=2,clkin1_period=5.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}\" *)\n\nmodule dvi_pll \n (\n // Clock out ports\n output pixel_clock,\n output dvi_bit_clock,\n // Clock in ports\n input sysclk\n );\n\n dvi_pll_clk_wiz inst\n (\n // Clock out ports \n .pixel_clock(pixel_clock),\n .dvi_bit_clock(dvi_bit_clock),\n // Clock in ports\n .sysclk(sysclk)\n );\n\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll.xci", "content": "\n\n xilinx.com\n xci\n unknown\n 1.0\n \n \n dvi_pll\n \n \n MMCM\n cddcdone\n cddcreq\n 0000\n 0080\n clkfb_in_n\n clkfb_in\n clkfb_in_p\n SINGLE\n clkfb_out_n\n clkfb_out\n clkfb_out_p\n clkfb_stopped\n 50.0\n 100.0\n 1145\n 0000\n 148.000\n 1041\n 0000\n 740.000\n BUFG\n 50.0\n false\n 148.000\n 0.000\n 50.000\n 148\n 0.000\n 1\n 1041\n 00c0\n 100.000\n BUFG\n 50.0\n false\n 740.000\n 0.000\n 50.000\n 740\n 0.000\n 1\n 1\n 1041\n 00c0\n 100.000\n BUFG\n 50.000\n false\n 100.000\n 0.000\n 50.000\n 100.000\n 0.000\n 1\n 0\n 1041\n 00c0\n 100.000\n BUFG\n 50.000\n false\n 100.000\n 0.000\n 50.000\n 100.000\n 0.000\n 1\n 0\n 1041\n 00c0\n 100.000\n BUFG\n 50.000\n false\n 100.000\n 0.000\n 50.000\n 100.000\n 0.000\n 1\n 0\n 1041\n 00c0\n 100.000\n BUFG\n 50.000\n false\n 100.000\n 0.000\n 50.000\n 100.000\n 0.000\n 1\n 0\n BUFG\n 50.000\n false\n 100.000\n 0.000\n 50.000\n 100.000\n 0.000\n 1\n 0\n VCO\n clk_in_sel\n pixel_clock\n dvi_bit_clock\n clk_out3\n clk_out4\n clk_out5\n clk_out6\n clk_out7\n CLK_VALID\n NA\n daddr\n dclk\n den\n din\n 0083\n 1\n 0.2\n 1.48\n 1.48\n 1.48\n 1.48\n 1.48\n dout\n drdy\n dwe\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n FDBK_AUTO\n 0800\n 1890\n 0\n Input Clock Freq (MHz) Input Jitter (UI)\n __primary_____________200____________0.010\n no_secondary_input_clock \n input_clk_stopped\n 0\n Units_MHz\n No_Jitter\n locked\n 00fa\n 7c01\n 7fe9\n false\n false\n false\n false\n false\n false\n false\n false\n OPTIMIZED\n 37.000\n 0.000\n FALSE\n 5.0\n 10.0\n 10.000\n 0.500\n 0.000\n FALSE\n 2\n 0.500\n 0.000\n FALSE\n 1\n 0.500\n 0.000\n FALSE\n 1\n 0.500\n 0.000\n FALSE\n FALSE\n 1\n 0.500\n 0.000\n FALSE\n 1\n 0.500\n 0.000\n FALSE\n 1\n 0.500\n 0.000\n FALSE\n FALSE\n ZHOLD\n 5\n None\n 0.010\n 0.010\n FALSE\n 2\n Output Output Phase Duty Cycle Pk-to-Pk Phase\n Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)\n pixel_clock___148.000______0.000______50.0______111.449____139.507\n dvi_bit_clock___740.000______0.000______50.0_______87.091____139.507\n no_CLK_OUT3_output\n no_CLK_OUT4_output\n no_CLK_OUT5_output\n no_CLK_OUT6_output\n no_CLK_OUT7_output\n 0\n 0\n WAVEFORM\n UNKNOWN\n false\n false\n false\n false\n false\n OPTIMIZED\n 1\n 0.000\n 1.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n CLKFBOUT\n SYSTEM_SYNCHRONOUS\n 1\n No notes\n 0.010\n power_down\n FFFF\n 1\n sysclk\n PLL\n AUTO\n 200\n 0.010\n 10.000\n Global_buffer\n psclk\n psdone\n psen\n psincdec\n 100.0\n 0\n reset\n 100.000\n 0.010\n 10.000\n clk_in2\n Single_ended_clock_capable_pin\n CENTER_HIGH\n 4000\n 0.004\n STATUS\n 11\n 32\n 100.0\n 100.0\n 100.0\n 100.0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n dvi_pll\n MMCM\n false\n empty\n cddcdone\n cddcreq\n clkfb_in_n\n clkfb_in\n clkfb_in_p\n SINGLE\n clkfb_out_n\n clkfb_out\n clkfb_out_p\n clkfb_stopped\n 50.0\n 0.010\n 100.0\n 0.010\n BUFG\n 111.449\n false\n 139.507\n 50.000\n 148\n 0.000\n 1\n true\n BUFG\n 87.091\n false\n 139.507\n 50.000\n 740\n 0.000\n 1\n true\n BUFG\n 0.0\n false\n 0.0\n 50.000\n 100.000\n 0.000\n 1\n false\n BUFG\n 0.0\n false\n 0.0\n 50.000\n 100.000\n 0.000\n 1\n false\n BUFG\n 0.0\n false\n 0.0\n 50.000\n 100.000\n 0.000\n 1\n false\n BUFG\n 0.0\n false\n 0.0\n 50.000\n 100.000\n 0.000\n 1\n false\n BUFG\n 0.0\n false\n 0.0\n 50.000\n 100.000\n 0.000\n 1\n false\n 600.000\n Custom\n Custom\n clk_in_sel\n pixel_clock\n false\n dvi_bit_clock\n false\n clk_out3\n false\n clk_out4\n false\n clk_out5\n false\n clk_out6\n false\n clk_out7\n false\n CLK_VALID\n auto\n dvi_pll\n daddr\n dclk\n den\n Custom\n Custom\n din\n dout\n drdy\n dwe\n false\n false\n false\n false\n false\n false\n false\n false\n false\n FDBK_AUTO\n input_clk_stopped\n frequency\n Enable_AXI\n Units_MHz\n Units_UI\n UI\n No_Jitter\n locked\n OPTIMIZED\n 37\n 0.000\n false\n 5.0\n 10.0\n 10\n 0.500\n 0.000\n false\n 2\n 0.500\n 0.000\n false\n 1\n 0.500\n 0.000\n false\n 1\n 0.500\n 0.000\n false\n false\n 1\n 0.500\n 0.000\n false\n 1\n 0.500\n 0.000\n false\n 1\n 0.500\n 0.000\n false\n false\n ZHOLD\n 5\n None\n 0.010\n 0.010\n false\n 2\n false\n false\n WAVEFORM\n false\n UNKNOWN\n OPTIMIZED\n 4\n 0.000\n 10.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n 1\n 0.500\n 0.000\n CLKFBOUT\n SYSTEM_SYNCHRONOUS\n 1\n None\n 0.010\n power_down\n 1\n sysclk\n PLL\n mmcm_adv\n 200\n 0.010\n 10.000\n Global_buffer\n psclk\n psdone\n psen\n psincdec\n 100.0\n REL_PRIMARY\n Custom\n reset\n ACTIVE_HIGH\n 100.000\n 0.010\n 10.000\n clk_in2\n Single_ended_clock_capable_pin\n CENTER_HIGH\n 250\n 0.004\n STATUS\n empty\n 100.0\n 100.0\n 100.0\n 100.0\n false\n false\n false\n false\n false\n false\n false\n true\n false\n false\n false\n false\n false\n false\n true\n false\n false\n false\n false\n false\n kintex7\n \n xc7k325t\n ffg900\n VERILOG\n \n MIXED\n -2\n \n TRUE\n TRUE\n IP_Flow\n 2\n TRUE\n .\n \n .\n 2016.3\n OUT_OF_CONTEXT\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll.xdc", "content": "\n# file: dvi_pll.xdc\n# \n# (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n# \n# This file contains confidential and proprietary information\n# of Xilinx, Inc. and is protected under U.S. and\n# international copyright and other intellectual property\n# laws.\n# \n# DISCLAIMER\n# This disclaimer is not a license and does not grant any\n# rights to the materials distributed herewith. Except as\n# otherwise provided in a valid license issued to you by\n# Xilinx, and to the maximum extent permitted by applicable\n# law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n# (2) Xilinx shall not be liable (whether in contract or tort,\n# including negligence, or under any other theory of\n# liability) for any loss or damage of any kind or nature\n# related to, arising under or in connection with these\n# materials, including for any direct, or any indirect,\n# special, incidental, or consequential loss or damage\n# (including loss of data, profits, goodwill, or any type of\n# loss or damage suffered as a result of any action brought\n# by a third party) even if such damage or loss was\n# reasonably foreseeable or Xilinx had been advised of the\n# possibility of the same.\n# \n# CRITICAL APPLICATIONS\n# Xilinx products are not designed or intended to be fail-\n# safe, or for use in any application requiring fail-safe\n# performance, such as life-support or safety devices or\n# systems, Class III medical devices, nuclear facilities,\n# applications related to the deployment of airbags, or any\n# other applications that could lead to death, personal\n# injury, or severe property or environmental damage\n# (individually and collectively, \"Critical\n# Applications\"). Customer assumes the sole risk and\n# liability of any use of Xilinx products in Critical\n# Applications, subject only to applicable laws and\n# regulations governing limitations on product liability.\n# \n# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n# PART OF THIS FILE AT ALL TIMES.\n# \n\n# Input clock periods. These duplicate the values entered for the\n# input clocks. You can use these to time your system. If required\n# commented constraints can be used in the top level xdc \n#----------------------------------------------------------------\n#create_clock -period 5.0 [get_ports sysclk]\n#set_input_jitter [get_clocks -of_objects [get_ports sysclk]] 0.05\n\n\nset_property PHASESHIFT_MODE WAVEFORM [get_cells -hierarchical *adv*]\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_board.xdc", "content": "#--------------------Physical Constraints-----------------\n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_clk_wiz.v", "content": "\n// file: dvi_pll.v\n// \n// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n//----------------------------------------------------------------------------\n// User entered comments\n//----------------------------------------------------------------------------\n// None\n//\n//----------------------------------------------------------------------------\n// Output Output Phase Duty Cycle Pk-to-Pk Phase\n// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)\n//----------------------------------------------------------------------------\n// pixel_clock___148.000______0.000______50.0______111.449____139.507\n// dvi_bit_clock___740.000______0.000______50.0_______87.091____139.507\n//\n//----------------------------------------------------------------------------\n// Input Clock Freq (MHz) Input Jitter (UI)\n//----------------------------------------------------------------------------\n// __primary_____________200____________0.010\n\n`timescale 1ps/1ps\n\nmodule dvi_pll_clk_wiz \n\n (// Clock in ports\n // Clock out ports\n output pixel_clock,\n output dvi_bit_clock,\n input sysclk\n );\n // Input buffering\n //------------------------------------\nwire sysclk_dvi_pll;\nwire clk_in2_dvi_pll;\n BUFG clkin1_bufg\n (.O (sysclk_dvi_pll),\n .I (sysclk));\n\n\n // Clocking PRIMITIVE\n //------------------------------------\n\n // Instantiation of the MMCM PRIMITIVE\n // * Unused inputs are tied off\n // * Unused outputs are labeled unused\n\n wire pixel_clock_dvi_pll;\n wire dvi_bit_clock_dvi_pll;\n wire clk_out3_dvi_pll;\n wire clk_out4_dvi_pll;\n wire clk_out5_dvi_pll;\n wire clk_out6_dvi_pll;\n wire clk_out7_dvi_pll;\n\n wire [15:0] do_unused;\n wire drdy_unused;\n wire psdone_unused;\n wire locked_int;\n wire clkfbout_dvi_pll;\n wire clkfbout_buf_dvi_pll;\n wire clkfboutb_unused;\n wire clkout2_unused;\n wire clkout3_unused;\n wire clkout4_unused;\n wire clkout5_unused;\n wire clkout6_unused;\n wire clkfbstopped_unused;\n wire clkinstopped_unused;\n\n PLLE2_ADV\n #(.BANDWIDTH (\"OPTIMIZED\"),\n .COMPENSATION (\"ZHOLD\"),\n .DIVCLK_DIVIDE (5),\n .CLKFBOUT_MULT (37),\n .CLKFBOUT_PHASE (0.000),\n .CLKOUT0_DIVIDE (10),\n .CLKOUT0_PHASE (0.000),\n .CLKOUT0_DUTY_CYCLE (0.500),\n .CLKOUT1_DIVIDE (2),\n .CLKOUT1_PHASE (0.000),\n .CLKOUT1_DUTY_CYCLE (0.500),\n .CLKIN1_PERIOD (5.0))\n plle2_adv_inst\n // Output clocks\n (\n .CLKFBOUT (clkfbout_dvi_pll),\n .CLKOUT0 (pixel_clock_dvi_pll),\n .CLKOUT1 (dvi_bit_clock_dvi_pll),\n .CLKOUT2 (clkout2_unused),\n .CLKOUT3 (clkout3_unused),\n .CLKOUT4 (clkout4_unused),\n .CLKOUT5 (clkout5_unused),\n // Input clock control\n .CLKFBIN (clkfbout_buf_dvi_pll),\n .CLKIN1 (sysclk_dvi_pll),\n .CLKIN2 (1'b0),\n // Tied to always select the primary input clock\n .CLKINSEL (1'b1),\n // Ports for dynamic reconfiguration\n .DADDR (7'h0),\n .DCLK (1'b0),\n .DEN (1'b0),\n .DI (16'h0),\n .DO (do_unused),\n .DRDY (drdy_unused),\n .DWE (1'b0),\n // Other control and status signals\n .LOCKED (locked_int),\n .PWRDWN (1'b0),\n .RST (1'b0));\n\n// Clock Monitor clock assigning\n//--------------------------------------\n // Output buffering\n //-----------------------------------\n\n BUFG clkf_buf\n (.O (clkfbout_buf_dvi_pll),\n .I (clkfbout_dvi_pll));\n\n\n\n BUFG clkout1_buf\n (.O (pixel_clock),\n .I (pixel_clock_dvi_pll));\n\n\n BUFG clkout2_buf\n (.O (dvi_bit_clock),\n .I (dvi_bit_clock_dvi_pll));\n\n\n\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_ooc.xdc", "content": "\n# file: dvi_pll_ooc.xdc\n# \n# (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n# \n# This file contains confidential and proprietary information\n# of Xilinx, Inc. and is protected under U.S. and\n# international copyright and other intellectual property\n# laws.\n# \n# DISCLAIMER\n# This disclaimer is not a license and does not grant any\n# rights to the materials distributed herewith. Except as\n# otherwise provided in a valid license issued to you by\n# Xilinx, and to the maximum extent permitted by applicable\n# law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n# (2) Xilinx shall not be liable (whether in contract or tort,\n# including negligence, or under any other theory of\n# liability) for any loss or damage of any kind or nature\n# related to, arising under or in connection with these\n# materials, including for any direct, or any indirect,\n# special, incidental, or consequential loss or damage\n# (including loss of data, profits, goodwill, or any type of\n# loss or damage suffered as a result of any action brought\n# by a third party) even if such damage or loss was\n# reasonably foreseeable or Xilinx had been advised of the\n# possibility of the same.\n# \n# CRITICAL APPLICATIONS\n# Xilinx products are not designed or intended to be fail-\n# safe, or for use in any application requiring fail-safe\n# performance, such as life-support or safety devices or\n# systems, Class III medical devices, nuclear facilities,\n# applications related to the deployment of airbags, or any\n# other applications that could lead to death, personal\n# injury, or severe property or environmental damage\n# (individually and collectively, \"Critical\n# Applications\"). Customer assumes the sole risk and\n# liability of any use of Xilinx products in Critical\n# Applications, subject only to applicable laws and\n# regulations governing limitations on product liability.\n# \n# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n# PART OF THIS FILE AT ALL TIMES.\n# \n\n#################\n#DEFAULT CLOCK CONSTRAINTS\n\n############################################################\n# Clock Period Constraints #\n############################################################\ncreate_clock -period 5.0 [get_ports sysclk]\n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_sim_netlist.v", "content": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// --------------------------------------------------------------------------------\n// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016\n// Date : Tue Nov 15 17:05:27 2016\n// Host : david-desktop-arch running 64-bit unknown\n// Command : write_verilog -force -mode funcsim\n// /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_sim_netlist.v\n// Design : dvi_pll\n// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified\n// or synthesized. This netlist cannot be used for SDF annotated simulation.\n// Device : xc7k325tffg900-2\n// --------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* NotValidForBitStream *)\nmodule dvi_pll\n (pixel_clock,\n dvi_bit_clock,\n sysclk);\n output pixel_clock;\n output dvi_bit_clock;\n input sysclk;\n\n wire dvi_bit_clock;\n wire pixel_clock;\n wire sysclk;\n\n dvi_pll_dvi_pll_clk_wiz inst\n (.dvi_bit_clock(dvi_bit_clock),\n .pixel_clock(pixel_clock),\n .sysclk(sysclk));\nendmodule\n\n(* ORIG_REF_NAME = \"dvi_pll_clk_wiz\" *) \nmodule dvi_pll_dvi_pll_clk_wiz\n (pixel_clock,\n dvi_bit_clock,\n sysclk);\n output pixel_clock;\n output dvi_bit_clock;\n input sysclk;\n\n wire clkfbout_buf_dvi_pll;\n wire clkfbout_dvi_pll;\n wire dvi_bit_clock;\n wire dvi_bit_clock_dvi_pll;\n wire pixel_clock;\n wire pixel_clock_dvi_pll;\n wire sysclk;\n wire sysclk_dvi_pll;\n wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED;\n wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED;\n wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED;\n wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED;\n wire NLW_plle2_adv_inst_DRDY_UNCONNECTED;\n wire NLW_plle2_adv_inst_LOCKED_UNCONNECTED;\n wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED;\n\n (* BOX_TYPE = \"PRIMITIVE\" *) \n BUFG clkf_buf\n (.I(clkfbout_dvi_pll),\n .O(clkfbout_buf_dvi_pll));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n BUFG clkin1_bufg\n (.I(sysclk),\n .O(sysclk_dvi_pll));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n BUFG clkout1_buf\n (.I(pixel_clock_dvi_pll),\n .O(pixel_clock));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n BUFG clkout2_buf\n (.I(dvi_bit_clock_dvi_pll),\n .O(dvi_bit_clock));\n (* BOX_TYPE = \"PRIMITIVE\" *) \n PLLE2_ADV #(\n .BANDWIDTH(\"OPTIMIZED\"),\n .CLKFBOUT_MULT(37),\n .CLKFBOUT_PHASE(0.000000),\n .CLKIN1_PERIOD(5.000000),\n .CLKIN2_PERIOD(0.000000),\n .CLKOUT0_DIVIDE(10),\n .CLKOUT0_DUTY_CYCLE(0.500000),\n .CLKOUT0_PHASE(0.000000),\n .CLKOUT1_DIVIDE(2),\n .CLKOUT1_DUTY_CYCLE(0.500000),\n .CLKOUT1_PHASE(0.000000),\n .CLKOUT2_DIVIDE(1),\n .CLKOUT2_DUTY_CYCLE(0.500000),\n .CLKOUT2_PHASE(0.000000),\n .CLKOUT3_DIVIDE(1),\n .CLKOUT3_DUTY_CYCLE(0.500000),\n .CLKOUT3_PHASE(0.000000),\n .CLKOUT4_DIVIDE(1),\n .CLKOUT4_DUTY_CYCLE(0.500000),\n .CLKOUT4_PHASE(0.000000),\n .CLKOUT5_DIVIDE(1),\n .CLKOUT5_DUTY_CYCLE(0.500000),\n .CLKOUT5_PHASE(0.000000),\n .COMPENSATION(\"BUF_IN\"),\n .DIVCLK_DIVIDE(5),\n .IS_CLKINSEL_INVERTED(1'b0),\n .IS_PWRDWN_INVERTED(1'b0),\n .IS_RST_INVERTED(1'b0),\n .REF_JITTER1(0.010000),\n .REF_JITTER2(0.010000),\n .STARTUP_WAIT(\"FALSE\")) \n plle2_adv_inst\n (.CLKFBIN(clkfbout_buf_dvi_pll),\n .CLKFBOUT(clkfbout_dvi_pll),\n .CLKIN1(sysclk_dvi_pll),\n .CLKIN2(1'b0),\n .CLKINSEL(1'b1),\n .CLKOUT0(pixel_clock_dvi_pll),\n .CLKOUT1(dvi_bit_clock_dvi_pll),\n .CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED),\n .CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED),\n .CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED),\n .CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED),\n .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DCLK(1'b0),\n .DEN(1'b0),\n .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]),\n .DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED),\n .DWE(1'b0),\n .LOCKED(NLW_plle2_adv_inst_LOCKED_UNCONNECTED),\n .PWRDWN(1'b0),\n .RST(1'b0));\nendmodule\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_stub.v", "content": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// --------------------------------------------------------------------------------\n// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016\n// Date : Tue Nov 15 17:05:27 2016\n// Host : david-desktop-arch running 64-bit unknown\n// Command : write_verilog -force -mode synth_stub\n// /home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_stub.v\n// Design : dvi_pll\n// Purpose : Stub declaration of top-level module interface\n// Device : xc7k325tffg900-2\n// --------------------------------------------------------------------------------\n\n// This empty module with port declaration file causes synthesis tools to infer a black box for IP.\n// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.\n// Please paste the declaration into a Verilog source file or add the file as an additional source.\nmodule dvi_pll(pixel_clock, dvi_bit_clock, sysclk)\n/* synthesis syn_black_box black_box_pad_pin=\"pixel_clock,dvi_bit_clock,sysclk\" */;\n output pixel_clock;\n output dvi_bit_clock;\n input sysclk;\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer.xci", "content": "\n\n xilinx.com\n xci\n unknown\n 1.0\n \n \n input_line_buffer\n \n \n 4096\n 12\n 10\n 1\n 4\n 0\n 1\n 9\n 0\n 1\n 7\n NONE\n 0\n 0\n 0\n ./\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n Estimated Power for IP : 36.714252 mW\n kintex7\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n input_line_buffer.mem\n no_coe_file_loaded\n 0\n 0\n 1\n 0\n 1\n 4096\n 1024\n 64\n 256\n 0\n 0\n CE\n CE\n ALL\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 1\n 4096\n 1024\n NO_CHANGE\n WRITE_FIRST\n 64\n 256\n kintex7\n 4\n Memory_Slave\n AXI4_Full\n false\n Minimum_Area\n false\n 9\n NONE\n no_coe_file_loaded\n ALL\n input_line_buffer\n false\n false\n false\n false\n false\n false\n false\n false\n false\n Use_ENA_Pin\n Always_Enabled\n Single_Bit_Error_Injection\n false\n Native\n false\n no_mem_loaded\n Simple_Dual_Port_RAM\n NO_CHANGE\n WRITE_FIRST\n 0\n 0\n BRAM\n 0\n 100\n 100\n 50\n 100\n 100\n 0\n 8kx2\n false\n false\n 64\n 256\n false\n false\n false\n false\n 0\n false\n false\n CE\n CE\n SYNC\n false\n false\n false\n false\n false\n false\n false\n 4096\n 64\n 256\n No_ECC\n false\n false\n false\n Stand_Alone\n kintex7\n \n xc7k325t\n ffg900\n VERILOG\n \n MIXED\n -2\n \n TRUE\n TRUE\n IP_Flow\n 4\n TRUE\n .\n \n .\n 2016.3\n OUT_OF_CONTEXT\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_ooc.xdc", "content": "################################################################################\n#\n# (c) Copyright 2002 - 2013 Xilinx, Inc. All rights reserved.\n# \n# This file contains confidential and proprietary information\n# of Xilinx, Inc. and is protected under U.S. and\n# international copyright and other intellectual property\n# laws.\n# \n# DISCLAIMER\n# This disclaimer is not a license and does not grant any\n# rights to the materials distributed herewith. Except as\n# otherwise provided in a valid license issued to you by\n# Xilinx, and to the maximum extent permitted by applicable\n# law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n# (2) Xilinx shall not be liable (whether in contract or tort,\n# including negligence, or under any other theory of\n# liability) for any loss or damage of any kind or nature\n# related to, arising under or in connection with these\n# materials, including for any direct, or any indirect,\n# special, incidental, or consequential loss or damage\n# (including loss of data, profits, goodwill, or any type of\n# loss or damage suffered as a result of any action brought\n# by a third party) even if such damage or loss was\n# reasonably foreseeable or Xilinx had been advised of the\n# possibility of the same.\n# \n# CRITICAL APPLICATIONS\n# Xilinx products are not designed or intended to be fail-\n# safe, or for use in any application requiring fail-safe\n# performance, such as life-support or safety devices or\n# systems, Class III medical devices, nuclear facilities,\n# applications related to the deployment of airbags, or any\n# other applications that could lead to death, personal\n# injury, or severe property or environmental damage\n# (individually and collectively, \"Critical\n# Applications\"). Customer assumes the sole risk and\n# liability of any use of Xilinx products in Critical\n# Applications, subject only to applicable laws and\n# regulations governing limitations on product liability.\n# \n# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n# PART OF THIS FILE AT ALL TIMES.\n#\n################################################################################\n\n# Core Period Constraint. This constraint can be modified, and is\n# valid as long as it is met after place and route.\ncreate_clock -name \"TS_CLKA\" -period 20.0 [ get_ports clka ]\n set_property HD.CLK_SRC BUFGCTRL_X0Y0 [ get_ports clka ]\n \ncreate_clock -name \"TS_CLKB\" -period 20.0 [ get_ports clkb ]\n set_property HD.CLK_SRC BUFGCTRL_X0Y1 [ get_ports clkb ]\n################################################################################\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_sim_netlist.v", "content": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// --------------------------------------------------------------------------------\n// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016\n// Date : Tue Nov 15 09:41:00 2016\n// Host : david-desktop-arch running 64-bit unknown\n// Command : write_verilog -force -mode funcsim\n// /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_sim_netlist.v\n// Design : input_line_buffer\n// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified\n// or synthesized. This netlist cannot be used for SDF annotated simulation.\n// Device : xc7k325tffg900-2\n// --------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CHECK_LICENSE_TYPE = \"input_line_buffer,blk_mem_gen_v8_3_4,{}\" *) (* downgradeipidentifiedwarnings = \"yes\" *) (* x_core_info = \"blk_mem_gen_v8_3_4,Vivado 2016.3\" *) \n(* NotValidForBitStream *)\nmodule input_line_buffer\n (clka,\n ena,\n wea,\n addra,\n dina,\n clkb,\n addrb,\n doutb);\n (* x_interface_info = \"xilinx.com:interface:bram:1.0 BRAM_PORTA CLK\" *) input clka;\n (* x_interface_info = \"xilinx.com:interface:bram:1.0 BRAM_PORTA EN\" *) input ena;\n (* x_interface_info = \"xilinx.com:interface:bram:1.0 BRAM_PORTA WE\" *) input [0:0]wea;\n (* x_interface_info = \"xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR\" *) input [11:0]addra;\n (* x_interface_info = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DIN\" *) input [63:0]dina;\n (* x_interface_info = \"xilinx.com:interface:bram:1.0 BRAM_PORTB CLK\" *) input clkb;\n (* x_interface_info = \"xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR\" *) input [9:0]addrb;\n (* x_interface_info = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT\" *) output [255:0]doutb;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [63:0]dina;\n wire [255:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire NLW_U0_dbiterr_UNCONNECTED;\n wire NLW_U0_rsta_busy_UNCONNECTED;\n wire NLW_U0_rstb_busy_UNCONNECTED;\n wire NLW_U0_s_axi_arready_UNCONNECTED;\n wire NLW_U0_s_axi_awready_UNCONNECTED;\n wire NLW_U0_s_axi_bvalid_UNCONNECTED;\n wire NLW_U0_s_axi_dbiterr_UNCONNECTED;\n wire NLW_U0_s_axi_rlast_UNCONNECTED;\n wire NLW_U0_s_axi_rvalid_UNCONNECTED;\n wire NLW_U0_s_axi_sbiterr_UNCONNECTED;\n wire NLW_U0_s_axi_wready_UNCONNECTED;\n wire NLW_U0_sbiterr_UNCONNECTED;\n wire [63:0]NLW_U0_douta_UNCONNECTED;\n wire [9:0]NLW_U0_rdaddrecc_UNCONNECTED;\n wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;\n wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;\n wire [9:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;\n wire [255:0]NLW_U0_s_axi_rdata_UNCONNECTED;\n wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;\n wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;\n\n (* C_ADDRA_WIDTH = \"12\" *) \n (* C_ADDRB_WIDTH = \"10\" *) \n (* C_ALGORITHM = \"1\" *) \n (* C_AXI_ID_WIDTH = \"4\" *) \n (* C_AXI_SLAVE_TYPE = \"0\" *) \n (* C_AXI_TYPE = \"1\" *) \n (* C_BYTE_SIZE = \"9\" *) \n (* C_COMMON_CLK = \"0\" *) \n (* C_COUNT_18K_BRAM = \"1\" *) \n (* C_COUNT_36K_BRAM = \"7\" *) \n (* C_CTRL_ECC_ALGO = \"NONE\" *) \n (* C_DEFAULT_DATA = \"0\" *) \n (* C_DISABLE_WARN_BHV_COLL = \"0\" *) \n (* C_DISABLE_WARN_BHV_RANGE = \"0\" *) \n (* C_ELABORATION_DIR = \"./\" *) \n (* C_ENABLE_32BIT_ADDRESS = \"0\" *) \n (* C_EN_DEEPSLEEP_PIN = \"0\" *) \n (* C_EN_ECC_PIPE = \"0\" *) \n (* C_EN_RDADDRA_CHG = \"0\" *) \n (* C_EN_RDADDRB_CHG = \"0\" *) \n (* C_EN_SAFETY_CKT = \"0\" *) \n (* C_EN_SHUTDOWN_PIN = \"0\" *) \n (* C_EN_SLEEP_PIN = \"0\" *) \n (* C_EST_POWER_SUMMARY = \"Estimated Power for IP : 36.714252 mW\" *) \n (* C_FAMILY = \"kintex7\" *) \n (* C_HAS_AXI_ID = \"0\" *) \n (* C_HAS_ENA = \"1\" *) \n (* C_HAS_ENB = \"0\" *) \n (* C_HAS_INJECTERR = \"0\" *) \n (* C_HAS_MEM_OUTPUT_REGS_A = \"0\" *) \n (* C_HAS_MEM_OUTPUT_REGS_B = \"0\" *) \n (* C_HAS_MUX_OUTPUT_REGS_A = \"0\" *) \n (* C_HAS_MUX_OUTPUT_REGS_B = \"0\" *) \n (* C_HAS_REGCEA = \"0\" *) \n (* C_HAS_REGCEB = \"0\" *) \n (* C_HAS_RSTA = \"0\" *) \n (* C_HAS_RSTB = \"0\" *) \n (* C_HAS_SOFTECC_INPUT_REGS_A = \"0\" *) \n (* C_HAS_SOFTECC_OUTPUT_REGS_B = \"0\" *) \n (* C_INITA_VAL = \"0\" *) \n (* C_INITB_VAL = \"0\" *) \n (* C_INIT_FILE = \"input_line_buffer.mem\" *) \n (* C_INIT_FILE_NAME = \"no_coe_file_loaded\" *) \n (* C_INTERFACE_TYPE = \"0\" *) \n (* C_LOAD_INIT_FILE = \"0\" *) \n (* C_MEM_TYPE = \"1\" *) \n (* C_MUX_PIPELINE_STAGES = \"0\" *) \n (* C_PRIM_TYPE = \"1\" *) \n (* C_READ_DEPTH_A = \"4096\" *) \n (* C_READ_DEPTH_B = \"1024\" *) \n (* C_READ_WIDTH_A = \"64\" *) \n (* C_READ_WIDTH_B = \"256\" *) \n (* C_RSTRAM_A = \"0\" *) \n (* C_RSTRAM_B = \"0\" *) \n (* C_RST_PRIORITY_A = \"CE\" *) \n (* C_RST_PRIORITY_B = \"CE\" *) \n (* C_SIM_COLLISION_CHECK = \"ALL\" *) \n (* C_USE_BRAM_BLOCK = \"0\" *) \n (* C_USE_BYTE_WEA = \"0\" *) \n (* C_USE_BYTE_WEB = \"0\" *) \n (* C_USE_DEFAULT_DATA = \"0\" *) \n (* C_USE_ECC = \"0\" *) \n (* C_USE_SOFTECC = \"0\" *) \n (* C_USE_URAM = \"0\" *) \n (* C_WEA_WIDTH = \"1\" *) \n (* C_WEB_WIDTH = \"1\" *) \n (* C_WRITE_DEPTH_A = \"4096\" *) \n (* C_WRITE_DEPTH_B = \"1024\" *) \n (* C_WRITE_MODE_A = \"NO_CHANGE\" *) \n (* C_WRITE_MODE_B = \"WRITE_FIRST\" *) \n (* C_WRITE_WIDTH_A = \"64\" *) \n (* C_WRITE_WIDTH_B = \"256\" *) \n (* C_XDEVICEFAMILY = \"kintex7\" *) \n (* downgradeipidentifiedwarnings = \"yes\" *) \n input_line_buffer_blk_mem_gen_v8_3_4 U0\n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dbiterr(NLW_U0_dbiterr_UNCONNECTED),\n .deepsleep(1'b0),\n .dina(dina),\n .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .douta(NLW_U0_douta_UNCONNECTED[63:0]),\n .doutb(doutb),\n .eccpipece(1'b0),\n .ena(ena),\n .enb(1'b0),\n .injectdbiterr(1'b0),\n .injectsbiterr(1'b0),\n .rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[9:0]),\n .regcea(1'b0),\n .regceb(1'b0),\n .rsta(1'b0),\n .rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),\n .rstb(1'b0),\n .rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),\n .s_aclk(1'b0),\n .s_aresetn(1'b0),\n .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axi_arburst({1'b0,1'b0}),\n .s_axi_arid({1'b0,1'b0,1'b0,1'b0}),\n .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),\n .s_axi_arsize({1'b0,1'b0,1'b0}),\n .s_axi_arvalid(1'b0),\n .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axi_awburst({1'b0,1'b0}),\n .s_axi_awid({1'b0,1'b0,1'b0,1'b0}),\n .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),\n .s_axi_awsize({1'b0,1'b0,1'b0}),\n .s_axi_awvalid(1'b0),\n .s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),\n .s_axi_bready(1'b0),\n .s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),\n .s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),\n .s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),\n .s_axi_injectdbiterr(1'b0),\n .s_axi_injectsbiterr(1'b0),\n .s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[9:0]),\n .s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[255:0]),\n .s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),\n .s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),\n .s_axi_rready(1'b0),\n .s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),\n .s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),\n .s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),\n .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axi_wlast(1'b0),\n .s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),\n .s_axi_wstrb(1'b0),\n .s_axi_wvalid(1'b0),\n .sbiterr(NLW_U0_sbiterr_UNCONNECTED),\n .shutdown(1'b0),\n .sleep(1'b0),\n .wea(wea),\n .web(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_generic_cstr\" *) \nmodule input_line_buffer_blk_mem_gen_generic_cstr\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [255:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [63:0]dina;\n input [0:0]wea;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [63:0]dina;\n wire [255:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n input_line_buffer_blk_mem_gen_prim_width \\ramloop[0].ram.r \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina[3:0]),\n .doutb({doutb[195:192],doutb[131:128],doutb[67:64],doutb[3:0]}),\n .ena(ena),\n .wea(wea));\n input_line_buffer_blk_mem_gen_prim_width__parameterized0 \\ramloop[1].ram.r \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina[12:4]),\n .doutb({doutb[204:196],doutb[140:132],doutb[76:68],doutb[12:4]}),\n .ena(ena),\n .wea(wea));\n input_line_buffer_blk_mem_gen_prim_width__parameterized1 \\ramloop[2].ram.r \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina[21:13]),\n .doutb({doutb[213:205],doutb[149:141],doutb[85:77],doutb[21:13]}),\n .ena(ena),\n .wea(wea));\n input_line_buffer_blk_mem_gen_prim_width__parameterized2 \\ramloop[3].ram.r \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina[30:22]),\n .doutb({doutb[222:214],doutb[158:150],doutb[94:86],doutb[30:22]}),\n .ena(ena),\n .wea(wea));\n input_line_buffer_blk_mem_gen_prim_width__parameterized3 \\ramloop[4].ram.r \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina[39:31]),\n .doutb({doutb[231:223],doutb[167:159],doutb[103:95],doutb[39:31]}),\n .ena(ena),\n .wea(wea));\n input_line_buffer_blk_mem_gen_prim_width__parameterized4 \\ramloop[5].ram.r \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina[48:40]),\n .doutb({doutb[240:232],doutb[176:168],doutb[112:104],doutb[48:40]}),\n .ena(ena),\n .wea(wea));\n input_line_buffer_blk_mem_gen_prim_width__parameterized5 \\ramloop[6].ram.r \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina[57:49]),\n .doutb({doutb[249:241],doutb[185:177],doutb[121:113],doutb[57:49]}),\n .ena(ena),\n .wea(wea));\n input_line_buffer_blk_mem_gen_prim_width__parameterized6 \\ramloop[7].ram.r \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina[63:58]),\n .doutb({doutb[255:250],doutb[191:186],doutb[127:122],doutb[63:58]}),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule input_line_buffer_blk_mem_gen_prim_width\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [15:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [3:0]dina;\n input [0:0]wea;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [3:0]dina;\n wire [15:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n input_line_buffer_blk_mem_gen_prim_wrapper \\prim_noinit.ram \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule input_line_buffer_blk_mem_gen_prim_width__parameterized0\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [35:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [8:0]dina;\n input [0:0]wea;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [8:0]dina;\n wire [35:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n input_line_buffer_blk_mem_gen_prim_wrapper__parameterized0 \\prim_noinit.ram \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule input_line_buffer_blk_mem_gen_prim_width__parameterized1\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [35:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [8:0]dina;\n input [0:0]wea;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [8:0]dina;\n wire [35:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n input_line_buffer_blk_mem_gen_prim_wrapper__parameterized1 \\prim_noinit.ram \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule input_line_buffer_blk_mem_gen_prim_width__parameterized2\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [35:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [8:0]dina;\n input [0:0]wea;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [8:0]dina;\n wire [35:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n input_line_buffer_blk_mem_gen_prim_wrapper__parameterized2 \\prim_noinit.ram \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule input_line_buffer_blk_mem_gen_prim_width__parameterized3\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [35:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [8:0]dina;\n input [0:0]wea;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [8:0]dina;\n wire [35:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n input_line_buffer_blk_mem_gen_prim_wrapper__parameterized3 \\prim_noinit.ram \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule input_line_buffer_blk_mem_gen_prim_width__parameterized4\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [35:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [8:0]dina;\n input [0:0]wea;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [8:0]dina;\n wire [35:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n input_line_buffer_blk_mem_gen_prim_wrapper__parameterized4 \\prim_noinit.ram \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule input_line_buffer_blk_mem_gen_prim_width__parameterized5\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [35:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [8:0]dina;\n input [0:0]wea;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [8:0]dina;\n wire [35:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n input_line_buffer_blk_mem_gen_prim_wrapper__parameterized5 \\prim_noinit.ram \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule input_line_buffer_blk_mem_gen_prim_width__parameterized6\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [23:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [5:0]dina;\n input [0:0]wea;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [5:0]dina;\n wire [23:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n input_line_buffer_blk_mem_gen_prim_wrapper__parameterized6 \\prim_noinit.ram \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule input_line_buffer_blk_mem_gen_prim_wrapper\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [15:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [3:0]dina;\n input [0:0]wea;\n\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_34 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_35 ;\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [3:0]dina;\n wire [15:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire [15:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ;\n wire [1:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB18E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(18'h00000),\n .INIT_B(18'h00000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_MODE(\"TDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(18),\n .READ_WIDTH_B(18),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(18'h00000),\n .SRVAL_B(18'h00000),\n .WRITE_MODE_A(\"NO_CHANGE\"),\n .WRITE_MODE_B(\"NO_CHANGE\"),\n .WRITE_WIDTH_A(4),\n .WRITE_WIDTH_B(4)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram \n (.ADDRARDADDR({addra,1'b0,1'b0}),\n .ADDRBWRADDR({addrb,1'b0,1'b0,1'b0,1'b0}),\n .CLKARDCLK(clka),\n .CLKBWRCLK(clkb),\n .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIPADIP({1'b0,1'b0}),\n .DIPBDIP({1'b0,1'b0}),\n .DOADO(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:0]),\n .DOBDO(doutb),\n .DOPADOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]),\n .DOPBDOP({\\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_34 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_35 }),\n .ENARDEN(ena),\n .ENBWREN(1'b1),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(1'b0),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .WEA({wea,wea}),\n .WEBWE({1'b0,1'b0,1'b0,1'b0}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule input_line_buffer_blk_mem_gen_prim_wrapper__parameterized0\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [35:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [8:0]dina;\n input [0:0]wea;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [8:0]dina;\n wire [35:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;\n wire [31:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;\n wire [3:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;\n wire [7:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;\n wire [8:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB36E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .EN_ECC_READ(\"FALSE\"),\n .EN_ECC_WRITE(\"FALSE\"),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(36'h000000000),\n .INIT_B(36'h000000000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_EXTENSION_A(\"NONE\"),\n .RAM_EXTENSION_B(\"NONE\"),\n .RAM_MODE(\"TDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(36),\n .READ_WIDTH_B(36),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(36'h000000000),\n .SRVAL_B(36'h000000000),\n .WRITE_MODE_A(\"NO_CHANGE\"),\n .WRITE_MODE_B(\"NO_CHANGE\"),\n .WRITE_WIDTH_A(9),\n .WRITE_WIDTH_B(9)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram \n (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),\n .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .CASCADEINA(1'b0),\n .CASCADEINB(1'b0),\n .CASCADEOUTA(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),\n .CASCADEOUTB(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),\n .CLKARDCLK(clka),\n .CLKBWRCLK(clkb),\n .DBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),\n .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIPADIP({1'b0,1'b0,1'b0,dina[8]}),\n .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),\n .DOADO(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),\n .DOBDO({doutb[34:27],doutb[25:18],doutb[16:9],doutb[7:0]}),\n .DOPADOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),\n .DOPBDOP({doutb[35],doutb[26],doutb[17],doutb[8]}),\n .ECCPARITY(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),\n .ENARDEN(ena),\n .ENBWREN(1'b1),\n .INJECTDBITERR(1'b0),\n .INJECTSBITERR(1'b0),\n .RDADDRECC(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(1'b0),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .SBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),\n .WEA({wea,wea,wea,wea}),\n .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule input_line_buffer_blk_mem_gen_prim_wrapper__parameterized1\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [35:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [8:0]dina;\n input [0:0]wea;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [8:0]dina;\n wire [35:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;\n wire [31:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;\n wire [3:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;\n wire [7:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;\n wire [8:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB36E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .EN_ECC_READ(\"FALSE\"),\n .EN_ECC_WRITE(\"FALSE\"),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(36'h000000000),\n .INIT_B(36'h000000000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_EXTENSION_A(\"NONE\"),\n .RAM_EXTENSION_B(\"NONE\"),\n .RAM_MODE(\"TDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(36),\n .READ_WIDTH_B(36),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(36'h000000000),\n .SRVAL_B(36'h000000000),\n .WRITE_MODE_A(\"NO_CHANGE\"),\n .WRITE_MODE_B(\"NO_CHANGE\"),\n .WRITE_WIDTH_A(9),\n .WRITE_WIDTH_B(9)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram \n (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),\n .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .CASCADEINA(1'b0),\n .CASCADEINB(1'b0),\n .CASCADEOUTA(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),\n .CASCADEOUTB(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),\n .CLKARDCLK(clka),\n .CLKBWRCLK(clkb),\n .DBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),\n .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIPADIP({1'b0,1'b0,1'b0,dina[8]}),\n .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),\n .DOADO(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),\n .DOBDO({doutb[34:27],doutb[25:18],doutb[16:9],doutb[7:0]}),\n .DOPADOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),\n .DOPBDOP({doutb[35],doutb[26],doutb[17],doutb[8]}),\n .ECCPARITY(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),\n .ENARDEN(ena),\n .ENBWREN(1'b1),\n .INJECTDBITERR(1'b0),\n .INJECTSBITERR(1'b0),\n .RDADDRECC(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(1'b0),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .SBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),\n .WEA({wea,wea,wea,wea}),\n .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule input_line_buffer_blk_mem_gen_prim_wrapper__parameterized2\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [35:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [8:0]dina;\n input [0:0]wea;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [8:0]dina;\n wire [35:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;\n wire [31:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;\n wire [3:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;\n wire [7:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;\n wire [8:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB36E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .EN_ECC_READ(\"FALSE\"),\n .EN_ECC_WRITE(\"FALSE\"),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(36'h000000000),\n .INIT_B(36'h000000000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_EXTENSION_A(\"NONE\"),\n .RAM_EXTENSION_B(\"NONE\"),\n .RAM_MODE(\"TDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(36),\n .READ_WIDTH_B(36),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(36'h000000000),\n .SRVAL_B(36'h000000000),\n .WRITE_MODE_A(\"NO_CHANGE\"),\n .WRITE_MODE_B(\"NO_CHANGE\"),\n .WRITE_WIDTH_A(9),\n .WRITE_WIDTH_B(9)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram \n (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),\n .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .CASCADEINA(1'b0),\n .CASCADEINB(1'b0),\n .CASCADEOUTA(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),\n .CASCADEOUTB(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),\n .CLKARDCLK(clka),\n .CLKBWRCLK(clkb),\n .DBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),\n .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIPADIP({1'b0,1'b0,1'b0,dina[8]}),\n .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),\n .DOADO(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),\n .DOBDO({doutb[34:27],doutb[25:18],doutb[16:9],doutb[7:0]}),\n .DOPADOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),\n .DOPBDOP({doutb[35],doutb[26],doutb[17],doutb[8]}),\n .ECCPARITY(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),\n .ENARDEN(ena),\n .ENBWREN(1'b1),\n .INJECTDBITERR(1'b0),\n .INJECTSBITERR(1'b0),\n .RDADDRECC(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(1'b0),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .SBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),\n .WEA({wea,wea,wea,wea}),\n .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule input_line_buffer_blk_mem_gen_prim_wrapper__parameterized3\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [35:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [8:0]dina;\n input [0:0]wea;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [8:0]dina;\n wire [35:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;\n wire [31:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;\n wire [3:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;\n wire [7:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;\n wire [8:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB36E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .EN_ECC_READ(\"FALSE\"),\n .EN_ECC_WRITE(\"FALSE\"),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(36'h000000000),\n .INIT_B(36'h000000000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_EXTENSION_A(\"NONE\"),\n .RAM_EXTENSION_B(\"NONE\"),\n .RAM_MODE(\"TDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(36),\n .READ_WIDTH_B(36),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(36'h000000000),\n .SRVAL_B(36'h000000000),\n .WRITE_MODE_A(\"NO_CHANGE\"),\n .WRITE_MODE_B(\"NO_CHANGE\"),\n .WRITE_WIDTH_A(9),\n .WRITE_WIDTH_B(9)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram \n (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),\n .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .CASCADEINA(1'b0),\n .CASCADEINB(1'b0),\n .CASCADEOUTA(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),\n .CASCADEOUTB(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),\n .CLKARDCLK(clka),\n .CLKBWRCLK(clkb),\n .DBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),\n .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIPADIP({1'b0,1'b0,1'b0,dina[8]}),\n .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),\n .DOADO(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),\n .DOBDO({doutb[34:27],doutb[25:18],doutb[16:9],doutb[7:0]}),\n .DOPADOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),\n .DOPBDOP({doutb[35],doutb[26],doutb[17],doutb[8]}),\n .ECCPARITY(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),\n .ENARDEN(ena),\n .ENBWREN(1'b1),\n .INJECTDBITERR(1'b0),\n .INJECTSBITERR(1'b0),\n .RDADDRECC(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(1'b0),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .SBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),\n .WEA({wea,wea,wea,wea}),\n .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule input_line_buffer_blk_mem_gen_prim_wrapper__parameterized4\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [35:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [8:0]dina;\n input [0:0]wea;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [8:0]dina;\n wire [35:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;\n wire [31:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;\n wire [3:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;\n wire [7:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;\n wire [8:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB36E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .EN_ECC_READ(\"FALSE\"),\n .EN_ECC_WRITE(\"FALSE\"),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(36'h000000000),\n .INIT_B(36'h000000000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_EXTENSION_A(\"NONE\"),\n .RAM_EXTENSION_B(\"NONE\"),\n .RAM_MODE(\"TDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(36),\n .READ_WIDTH_B(36),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(36'h000000000),\n .SRVAL_B(36'h000000000),\n .WRITE_MODE_A(\"NO_CHANGE\"),\n .WRITE_MODE_B(\"NO_CHANGE\"),\n .WRITE_WIDTH_A(9),\n .WRITE_WIDTH_B(9)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram \n (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),\n .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .CASCADEINA(1'b0),\n .CASCADEINB(1'b0),\n .CASCADEOUTA(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),\n .CASCADEOUTB(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),\n .CLKARDCLK(clka),\n .CLKBWRCLK(clkb),\n .DBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),\n .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIPADIP({1'b0,1'b0,1'b0,dina[8]}),\n .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),\n .DOADO(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),\n .DOBDO({doutb[34:27],doutb[25:18],doutb[16:9],doutb[7:0]}),\n .DOPADOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),\n .DOPBDOP({doutb[35],doutb[26],doutb[17],doutb[8]}),\n .ECCPARITY(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),\n .ENARDEN(ena),\n .ENBWREN(1'b1),\n .INJECTDBITERR(1'b0),\n .INJECTSBITERR(1'b0),\n .RDADDRECC(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(1'b0),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .SBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),\n .WEA({wea,wea,wea,wea}),\n .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule input_line_buffer_blk_mem_gen_prim_wrapper__parameterized5\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [35:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [8:0]dina;\n input [0:0]wea;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [8:0]dina;\n wire [35:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;\n wire [31:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;\n wire [3:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;\n wire [7:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;\n wire [8:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB36E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .EN_ECC_READ(\"FALSE\"),\n .EN_ECC_WRITE(\"FALSE\"),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(36'h000000000),\n .INIT_B(36'h000000000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_EXTENSION_A(\"NONE\"),\n .RAM_EXTENSION_B(\"NONE\"),\n .RAM_MODE(\"TDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(36),\n .READ_WIDTH_B(36),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(36'h000000000),\n .SRVAL_B(36'h000000000),\n .WRITE_MODE_A(\"NO_CHANGE\"),\n .WRITE_MODE_B(\"NO_CHANGE\"),\n .WRITE_WIDTH_A(9),\n .WRITE_WIDTH_B(9)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram \n (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),\n .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .CASCADEINA(1'b0),\n .CASCADEINB(1'b0),\n .CASCADEOUTA(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),\n .CASCADEOUTB(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),\n .CLKARDCLK(clka),\n .CLKBWRCLK(clkb),\n .DBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),\n .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIPADIP({1'b0,1'b0,1'b0,dina[8]}),\n .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),\n .DOADO(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),\n .DOBDO({doutb[34:27],doutb[25:18],doutb[16:9],doutb[7:0]}),\n .DOPADOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),\n .DOPBDOP({doutb[35],doutb[26],doutb[17],doutb[8]}),\n .ECCPARITY(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),\n .ENARDEN(ena),\n .ENBWREN(1'b1),\n .INJECTDBITERR(1'b0),\n .INJECTSBITERR(1'b0),\n .RDADDRECC(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(1'b0),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .SBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),\n .WEA({wea,wea,wea,wea}),\n .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule input_line_buffer_blk_mem_gen_prim_wrapper__parameterized6\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [23:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [5:0]dina;\n input [0:0]wea;\n\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_54 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_62 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_70 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ;\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [5:0]dina;\n wire [23:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;\n wire [31:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;\n wire [3:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;\n wire [7:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;\n wire [8:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB36E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .EN_ECC_READ(\"FALSE\"),\n .EN_ECC_WRITE(\"FALSE\"),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(36'h000000000),\n .INIT_B(36'h000000000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_EXTENSION_A(\"NONE\"),\n .RAM_EXTENSION_B(\"NONE\"),\n .RAM_MODE(\"TDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(36),\n .READ_WIDTH_B(36),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(36'h000000000),\n .SRVAL_B(36'h000000000),\n .WRITE_MODE_A(\"NO_CHANGE\"),\n .WRITE_MODE_B(\"NO_CHANGE\"),\n .WRITE_WIDTH_A(9),\n .WRITE_WIDTH_B(9)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram \n (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),\n .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .CASCADEINA(1'b0),\n .CASCADEINB(1'b0),\n .CASCADEOUTA(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),\n .CASCADEOUTB(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),\n .CLKARDCLK(clka),\n .CLKBWRCLK(clkb),\n .DBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),\n .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIPADIP({1'b0,1'b0,1'b0,1'b0}),\n .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),\n .DOADO(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),\n .DOBDO({\\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_54 ,doutb[23:18],\\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_62 ,doutb[17:12],\\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_70 ,doutb[11:6],\\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78 ,doutb[5:0]}),\n .DOPADOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),\n .DOPBDOP({\\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }),\n .ECCPARITY(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),\n .ENARDEN(ena),\n .ENBWREN(1'b1),\n .INJECTDBITERR(1'b0),\n .INJECTSBITERR(1'b0),\n .RDADDRECC(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(1'b0),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .SBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),\n .WEA({wea,wea,wea,wea}),\n .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_top\" *) \nmodule input_line_buffer_blk_mem_gen_top\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [255:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [63:0]dina;\n input [0:0]wea;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [63:0]dina;\n wire [255:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n input_line_buffer_blk_mem_gen_generic_cstr \\valid.cstr \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* C_ADDRA_WIDTH = \"12\" *) (* C_ADDRB_WIDTH = \"10\" *) (* C_ALGORITHM = \"1\" *) \n(* C_AXI_ID_WIDTH = \"4\" *) (* C_AXI_SLAVE_TYPE = \"0\" *) (* C_AXI_TYPE = \"1\" *) \n(* C_BYTE_SIZE = \"9\" *) (* C_COMMON_CLK = \"0\" *) (* C_COUNT_18K_BRAM = \"1\" *) \n(* C_COUNT_36K_BRAM = \"7\" *) (* C_CTRL_ECC_ALGO = \"NONE\" *) (* C_DEFAULT_DATA = \"0\" *) \n(* C_DISABLE_WARN_BHV_COLL = \"0\" *) (* C_DISABLE_WARN_BHV_RANGE = \"0\" *) (* C_ELABORATION_DIR = \"./\" *) \n(* C_ENABLE_32BIT_ADDRESS = \"0\" *) (* C_EN_DEEPSLEEP_PIN = \"0\" *) (* C_EN_ECC_PIPE = \"0\" *) \n(* C_EN_RDADDRA_CHG = \"0\" *) (* C_EN_RDADDRB_CHG = \"0\" *) (* C_EN_SAFETY_CKT = \"0\" *) \n(* C_EN_SHUTDOWN_PIN = \"0\" *) (* C_EN_SLEEP_PIN = \"0\" *) (* C_EST_POWER_SUMMARY = \"Estimated Power for IP : 36.714252 mW\" *) \n(* C_FAMILY = \"kintex7\" *) (* C_HAS_AXI_ID = \"0\" *) (* C_HAS_ENA = \"1\" *) \n(* C_HAS_ENB = \"0\" *) (* C_HAS_INJECTERR = \"0\" *) (* C_HAS_MEM_OUTPUT_REGS_A = \"0\" *) \n(* C_HAS_MEM_OUTPUT_REGS_B = \"0\" *) (* C_HAS_MUX_OUTPUT_REGS_A = \"0\" *) (* C_HAS_MUX_OUTPUT_REGS_B = \"0\" *) \n(* C_HAS_REGCEA = \"0\" *) (* C_HAS_REGCEB = \"0\" *) (* C_HAS_RSTA = \"0\" *) \n(* C_HAS_RSTB = \"0\" *) (* C_HAS_SOFTECC_INPUT_REGS_A = \"0\" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = \"0\" *) \n(* C_INITA_VAL = \"0\" *) (* C_INITB_VAL = \"0\" *) (* C_INIT_FILE = \"input_line_buffer.mem\" *) \n(* C_INIT_FILE_NAME = \"no_coe_file_loaded\" *) (* C_INTERFACE_TYPE = \"0\" *) (* C_LOAD_INIT_FILE = \"0\" *) \n(* C_MEM_TYPE = \"1\" *) (* C_MUX_PIPELINE_STAGES = \"0\" *) (* C_PRIM_TYPE = \"1\" *) \n(* C_READ_DEPTH_A = \"4096\" *) (* C_READ_DEPTH_B = \"1024\" *) (* C_READ_WIDTH_A = \"64\" *) \n(* C_READ_WIDTH_B = \"256\" *) (* C_RSTRAM_A = \"0\" *) (* C_RSTRAM_B = \"0\" *) \n(* C_RST_PRIORITY_A = \"CE\" *) (* C_RST_PRIORITY_B = \"CE\" *) (* C_SIM_COLLISION_CHECK = \"ALL\" *) \n(* C_USE_BRAM_BLOCK = \"0\" *) (* C_USE_BYTE_WEA = \"0\" *) (* C_USE_BYTE_WEB = \"0\" *) \n(* C_USE_DEFAULT_DATA = \"0\" *) (* C_USE_ECC = \"0\" *) (* C_USE_SOFTECC = \"0\" *) \n(* C_USE_URAM = \"0\" *) (* C_WEA_WIDTH = \"1\" *) (* C_WEB_WIDTH = \"1\" *) \n(* C_WRITE_DEPTH_A = \"4096\" *) (* C_WRITE_DEPTH_B = \"1024\" *) (* C_WRITE_MODE_A = \"NO_CHANGE\" *) \n(* C_WRITE_MODE_B = \"WRITE_FIRST\" *) (* C_WRITE_WIDTH_A = \"64\" *) (* C_WRITE_WIDTH_B = \"256\" *) \n(* C_XDEVICEFAMILY = \"kintex7\" *) (* ORIG_REF_NAME = \"blk_mem_gen_v8_3_4\" *) (* downgradeipidentifiedwarnings = \"yes\" *) \nmodule input_line_buffer_blk_mem_gen_v8_3_4\n (clka,\n rsta,\n ena,\n regcea,\n wea,\n addra,\n dina,\n douta,\n clkb,\n rstb,\n enb,\n regceb,\n web,\n addrb,\n dinb,\n doutb,\n injectsbiterr,\n injectdbiterr,\n eccpipece,\n sbiterr,\n dbiterr,\n rdaddrecc,\n sleep,\n deepsleep,\n shutdown,\n rsta_busy,\n rstb_busy,\n s_aclk,\n s_aresetn,\n s_axi_awid,\n s_axi_awaddr,\n s_axi_awlen,\n s_axi_awsize,\n s_axi_awburst,\n s_axi_awvalid,\n s_axi_awready,\n s_axi_wdata,\n s_axi_wstrb,\n s_axi_wlast,\n s_axi_wvalid,\n s_axi_wready,\n s_axi_bid,\n s_axi_bresp,\n s_axi_bvalid,\n s_axi_bready,\n s_axi_arid,\n s_axi_araddr,\n s_axi_arlen,\n s_axi_arsize,\n s_axi_arburst,\n s_axi_arvalid,\n s_axi_arready,\n s_axi_rid,\n s_axi_rdata,\n s_axi_rresp,\n s_axi_rlast,\n s_axi_rvalid,\n s_axi_rready,\n s_axi_injectsbiterr,\n s_axi_injectdbiterr,\n s_axi_sbiterr,\n s_axi_dbiterr,\n s_axi_rdaddrecc);\n input clka;\n input rsta;\n input ena;\n input regcea;\n input [0:0]wea;\n input [11:0]addra;\n input [63:0]dina;\n output [63:0]douta;\n input clkb;\n input rstb;\n input enb;\n input regceb;\n input [0:0]web;\n input [9:0]addrb;\n input [255:0]dinb;\n output [255:0]doutb;\n input injectsbiterr;\n input injectdbiterr;\n input eccpipece;\n output sbiterr;\n output dbiterr;\n output [9:0]rdaddrecc;\n input sleep;\n input deepsleep;\n input shutdown;\n output rsta_busy;\n output rstb_busy;\n input s_aclk;\n input s_aresetn;\n input [3:0]s_axi_awid;\n input [31:0]s_axi_awaddr;\n input [7:0]s_axi_awlen;\n input [2:0]s_axi_awsize;\n input [1:0]s_axi_awburst;\n input s_axi_awvalid;\n output s_axi_awready;\n input [63:0]s_axi_wdata;\n input [0:0]s_axi_wstrb;\n input s_axi_wlast;\n input s_axi_wvalid;\n output s_axi_wready;\n output [3:0]s_axi_bid;\n output [1:0]s_axi_bresp;\n output s_axi_bvalid;\n input s_axi_bready;\n input [3:0]s_axi_arid;\n input [31:0]s_axi_araddr;\n input [7:0]s_axi_arlen;\n input [2:0]s_axi_arsize;\n input [1:0]s_axi_arburst;\n input s_axi_arvalid;\n output s_axi_arready;\n output [3:0]s_axi_rid;\n output [255:0]s_axi_rdata;\n output [1:0]s_axi_rresp;\n output s_axi_rlast;\n output s_axi_rvalid;\n input s_axi_rready;\n input s_axi_injectsbiterr;\n input s_axi_injectdbiterr;\n output s_axi_sbiterr;\n output s_axi_dbiterr;\n output [9:0]s_axi_rdaddrecc;\n\n wire \\ ;\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [63:0]dina;\n wire [255:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n assign dbiterr = \\ ;\n assign douta[63] = \\ ;\n assign douta[62] = \\ ;\n assign douta[61] = \\ ;\n assign douta[60] = \\ ;\n assign douta[59] = \\ ;\n assign douta[58] = \\ ;\n assign douta[57] = \\ ;\n assign douta[56] = \\ ;\n assign douta[55] = \\ ;\n assign douta[54] = \\ ;\n assign douta[53] = \\ ;\n assign douta[52] = \\ ;\n assign douta[51] = \\ ;\n assign douta[50] = \\ ;\n assign douta[49] = \\ ;\n assign douta[48] = \\ ;\n assign douta[47] = \\ ;\n assign douta[46] = \\ ;\n assign douta[45] = \\ ;\n assign douta[44] = \\ ;\n assign douta[43] = \\ ;\n assign douta[42] = \\ ;\n assign douta[41] = \\ ;\n assign douta[40] = \\ ;\n assign douta[39] = \\ ;\n assign douta[38] = \\ ;\n assign douta[37] = \\ ;\n assign douta[36] = \\ ;\n assign douta[35] = \\ ;\n assign douta[34] = \\ ;\n assign douta[33] = \\ ;\n assign douta[32] = \\ ;\n assign douta[31] = \\ ;\n assign douta[30] = \\ ;\n assign douta[29] = \\ ;\n assign douta[28] = \\ ;\n assign douta[27] = \\ ;\n assign douta[26] = \\ ;\n assign douta[25] = \\ ;\n assign douta[24] = \\ ;\n assign douta[23] = \\ ;\n assign douta[22] = \\ ;\n assign douta[21] = \\ ;\n assign douta[20] = \\ ;\n assign douta[19] = \\ ;\n assign douta[18] = \\ ;\n assign douta[17] = \\ ;\n assign douta[16] = \\ ;\n assign douta[15] = \\ ;\n assign douta[14] = \\ ;\n assign douta[13] = \\ ;\n assign douta[12] = \\ ;\n assign douta[11] = \\ ;\n assign douta[10] = \\ ;\n assign douta[9] = \\ ;\n assign douta[8] = \\ ;\n assign douta[7] = \\ ;\n assign douta[6] = \\ ;\n assign douta[5] = \\ ;\n assign douta[4] = \\ ;\n assign douta[3] = \\ ;\n assign douta[2] = \\ ;\n assign douta[1] = \\ ;\n assign douta[0] = \\ ;\n assign rdaddrecc[9] = \\ ;\n assign rdaddrecc[8] = \\ ;\n assign rdaddrecc[7] = \\ ;\n assign rdaddrecc[6] = \\ ;\n assign rdaddrecc[5] = \\ ;\n assign rdaddrecc[4] = \\ ;\n assign rdaddrecc[3] = \\ ;\n assign rdaddrecc[2] = \\ ;\n assign rdaddrecc[1] = \\ ;\n assign rdaddrecc[0] = \\ ;\n assign rsta_busy = \\ ;\n assign rstb_busy = \\ ;\n assign s_axi_arready = \\ ;\n assign s_axi_awready = \\ ;\n assign s_axi_bid[3] = \\ ;\n assign s_axi_bid[2] = \\ ;\n assign s_axi_bid[1] = \\ ;\n assign s_axi_bid[0] = \\ ;\n assign s_axi_bresp[1] = \\ ;\n assign s_axi_bresp[0] = \\ ;\n assign s_axi_bvalid = \\ ;\n assign s_axi_dbiterr = \\ ;\n assign s_axi_rdaddrecc[9] = \\ ;\n assign s_axi_rdaddrecc[8] = \\ ;\n assign s_axi_rdaddrecc[7] = \\ ;\n assign s_axi_rdaddrecc[6] = \\ ;\n assign s_axi_rdaddrecc[5] = \\ ;\n assign s_axi_rdaddrecc[4] = \\ ;\n assign s_axi_rdaddrecc[3] = \\ ;\n assign s_axi_rdaddrecc[2] = \\ ;\n assign s_axi_rdaddrecc[1] = \\ ;\n assign s_axi_rdaddrecc[0] = \\ ;\n assign s_axi_rdata[255] = \\ ;\n assign s_axi_rdata[254] = \\ ;\n assign s_axi_rdata[253] = \\ ;\n assign s_axi_rdata[252] = \\ ;\n assign s_axi_rdata[251] = \\ ;\n assign s_axi_rdata[250] = \\ ;\n assign s_axi_rdata[249] = \\ ;\n assign s_axi_rdata[248] = \\ ;\n assign s_axi_rdata[247] = \\ ;\n assign s_axi_rdata[246] = \\ ;\n assign s_axi_rdata[245] = \\ ;\n assign s_axi_rdata[244] = \\ ;\n assign s_axi_rdata[243] = \\ ;\n assign s_axi_rdata[242] = \\ ;\n assign s_axi_rdata[241] = \\ ;\n assign s_axi_rdata[240] = \\ ;\n assign s_axi_rdata[239] = \\ ;\n assign s_axi_rdata[238] = \\ ;\n assign s_axi_rdata[237] = \\ ;\n assign s_axi_rdata[236] = \\ ;\n assign s_axi_rdata[235] = \\ ;\n assign s_axi_rdata[234] = \\ ;\n assign s_axi_rdata[233] = \\ ;\n assign s_axi_rdata[232] = \\ ;\n assign s_axi_rdata[231] = \\ ;\n assign s_axi_rdata[230] = \\ ;\n assign s_axi_rdata[229] = \\ ;\n assign s_axi_rdata[228] = \\ ;\n assign s_axi_rdata[227] = \\ ;\n assign s_axi_rdata[226] = \\ ;\n assign s_axi_rdata[225] = \\ ;\n assign s_axi_rdata[224] = \\ ;\n assign s_axi_rdata[223] = \\ ;\n assign s_axi_rdata[222] = \\ ;\n assign s_axi_rdata[221] = \\ ;\n assign s_axi_rdata[220] = \\ ;\n assign s_axi_rdata[219] = \\ ;\n assign s_axi_rdata[218] = \\ ;\n assign s_axi_rdata[217] = \\ ;\n assign s_axi_rdata[216] = \\ ;\n assign s_axi_rdata[215] = \\ ;\n assign s_axi_rdata[214] = \\ ;\n assign s_axi_rdata[213] = \\ ;\n assign s_axi_rdata[212] = \\ ;\n assign s_axi_rdata[211] = \\ ;\n assign s_axi_rdata[210] = \\ ;\n assign s_axi_rdata[209] = \\ ;\n assign s_axi_rdata[208] = \\ ;\n assign s_axi_rdata[207] = \\ ;\n assign s_axi_rdata[206] = \\ ;\n assign s_axi_rdata[205] = \\ ;\n assign s_axi_rdata[204] = \\ ;\n assign s_axi_rdata[203] = \\ ;\n assign s_axi_rdata[202] = \\ ;\n assign s_axi_rdata[201] = \\ ;\n assign s_axi_rdata[200] = \\ ;\n assign s_axi_rdata[199] = \\ ;\n assign s_axi_rdata[198] = \\ ;\n assign s_axi_rdata[197] = \\ ;\n assign s_axi_rdata[196] = \\ ;\n assign s_axi_rdata[195] = \\ ;\n assign s_axi_rdata[194] = \\ ;\n assign s_axi_rdata[193] = \\ ;\n assign s_axi_rdata[192] = \\ ;\n assign s_axi_rdata[191] = \\ ;\n assign s_axi_rdata[190] = \\ ;\n assign s_axi_rdata[189] = \\ ;\n assign s_axi_rdata[188] = \\ ;\n assign s_axi_rdata[187] = \\ ;\n assign s_axi_rdata[186] = \\ ;\n assign s_axi_rdata[185] = \\ ;\n assign s_axi_rdata[184] = \\ ;\n assign s_axi_rdata[183] = \\ ;\n assign s_axi_rdata[182] = \\ ;\n assign s_axi_rdata[181] = \\ ;\n assign s_axi_rdata[180] = \\ ;\n assign s_axi_rdata[179] = \\ ;\n assign s_axi_rdata[178] = \\ ;\n assign s_axi_rdata[177] = \\ ;\n assign s_axi_rdata[176] = \\ ;\n assign s_axi_rdata[175] = \\ ;\n assign s_axi_rdata[174] = \\ ;\n assign s_axi_rdata[173] = \\ ;\n assign s_axi_rdata[172] = \\ ;\n assign s_axi_rdata[171] = \\ ;\n assign s_axi_rdata[170] = \\ ;\n assign s_axi_rdata[169] = \\ ;\n assign s_axi_rdata[168] = \\ ;\n assign s_axi_rdata[167] = \\ ;\n assign s_axi_rdata[166] = \\ ;\n assign s_axi_rdata[165] = \\ ;\n assign s_axi_rdata[164] = \\ ;\n assign s_axi_rdata[163] = \\ ;\n assign s_axi_rdata[162] = \\ ;\n assign s_axi_rdata[161] = \\ ;\n assign s_axi_rdata[160] = \\ ;\n assign s_axi_rdata[159] = \\ ;\n assign s_axi_rdata[158] = \\ ;\n assign s_axi_rdata[157] = \\ ;\n assign s_axi_rdata[156] = \\ ;\n assign s_axi_rdata[155] = \\ ;\n assign s_axi_rdata[154] = \\ ;\n assign s_axi_rdata[153] = \\ ;\n assign s_axi_rdata[152] = \\ ;\n assign s_axi_rdata[151] = \\ ;\n assign s_axi_rdata[150] = \\ ;\n assign s_axi_rdata[149] = \\ ;\n assign s_axi_rdata[148] = \\ ;\n assign s_axi_rdata[147] = \\ ;\n assign s_axi_rdata[146] = \\ ;\n assign s_axi_rdata[145] = \\ ;\n assign s_axi_rdata[144] = \\ ;\n assign s_axi_rdata[143] = \\ ;\n assign s_axi_rdata[142] = \\ ;\n assign s_axi_rdata[141] = \\ ;\n assign s_axi_rdata[140] = \\ ;\n assign s_axi_rdata[139] = \\ ;\n assign s_axi_rdata[138] = \\ ;\n assign s_axi_rdata[137] = \\ ;\n assign s_axi_rdata[136] = \\ ;\n assign s_axi_rdata[135] = \\ ;\n assign s_axi_rdata[134] = \\ ;\n assign s_axi_rdata[133] = \\ ;\n assign s_axi_rdata[132] = \\ ;\n assign s_axi_rdata[131] = \\ ;\n assign s_axi_rdata[130] = \\ ;\n assign s_axi_rdata[129] = \\ ;\n assign s_axi_rdata[128] = \\ ;\n assign s_axi_rdata[127] = \\ ;\n assign s_axi_rdata[126] = \\ ;\n assign s_axi_rdata[125] = \\ ;\n assign s_axi_rdata[124] = \\ ;\n assign s_axi_rdata[123] = \\ ;\n assign s_axi_rdata[122] = \\ ;\n assign s_axi_rdata[121] = \\ ;\n assign s_axi_rdata[120] = \\ ;\n assign s_axi_rdata[119] = \\ ;\n assign s_axi_rdata[118] = \\ ;\n assign s_axi_rdata[117] = \\ ;\n assign s_axi_rdata[116] = \\ ;\n assign s_axi_rdata[115] = \\ ;\n assign s_axi_rdata[114] = \\ ;\n assign s_axi_rdata[113] = \\ ;\n assign s_axi_rdata[112] = \\ ;\n assign s_axi_rdata[111] = \\ ;\n assign s_axi_rdata[110] = \\ ;\n assign s_axi_rdata[109] = \\ ;\n assign s_axi_rdata[108] = \\ ;\n assign s_axi_rdata[107] = \\ ;\n assign s_axi_rdata[106] = \\ ;\n assign s_axi_rdata[105] = \\ ;\n assign s_axi_rdata[104] = \\ ;\n assign s_axi_rdata[103] = \\ ;\n assign s_axi_rdata[102] = \\ ;\n assign s_axi_rdata[101] = \\ ;\n assign s_axi_rdata[100] = \\ ;\n assign s_axi_rdata[99] = \\ ;\n assign s_axi_rdata[98] = \\ ;\n assign s_axi_rdata[97] = \\ ;\n assign s_axi_rdata[96] = \\ ;\n assign s_axi_rdata[95] = \\ ;\n assign s_axi_rdata[94] = \\ ;\n assign s_axi_rdata[93] = \\ ;\n assign s_axi_rdata[92] = \\ ;\n assign s_axi_rdata[91] = \\ ;\n assign s_axi_rdata[90] = \\ ;\n assign s_axi_rdata[89] = \\ ;\n assign s_axi_rdata[88] = \\ ;\n assign s_axi_rdata[87] = \\ ;\n assign s_axi_rdata[86] = \\ ;\n assign s_axi_rdata[85] = \\ ;\n assign s_axi_rdata[84] = \\ ;\n assign s_axi_rdata[83] = \\ ;\n assign s_axi_rdata[82] = \\ ;\n assign s_axi_rdata[81] = \\ ;\n assign s_axi_rdata[80] = \\ ;\n assign s_axi_rdata[79] = \\ ;\n assign s_axi_rdata[78] = \\ ;\n assign s_axi_rdata[77] = \\ ;\n assign s_axi_rdata[76] = \\ ;\n assign s_axi_rdata[75] = \\ ;\n assign s_axi_rdata[74] = \\ ;\n assign s_axi_rdata[73] = \\ ;\n assign s_axi_rdata[72] = \\ ;\n assign s_axi_rdata[71] = \\ ;\n assign s_axi_rdata[70] = \\ ;\n assign s_axi_rdata[69] = \\ ;\n assign s_axi_rdata[68] = \\ ;\n assign s_axi_rdata[67] = \\ ;\n assign s_axi_rdata[66] = \\ ;\n assign s_axi_rdata[65] = \\ ;\n assign s_axi_rdata[64] = \\ ;\n assign s_axi_rdata[63] = \\ ;\n assign s_axi_rdata[62] = \\ ;\n assign s_axi_rdata[61] = \\ ;\n assign s_axi_rdata[60] = \\ ;\n assign s_axi_rdata[59] = \\ ;\n assign s_axi_rdata[58] = \\ ;\n assign s_axi_rdata[57] = \\ ;\n assign s_axi_rdata[56] = \\ ;\n assign s_axi_rdata[55] = \\ ;\n assign s_axi_rdata[54] = \\ ;\n assign s_axi_rdata[53] = \\ ;\n assign s_axi_rdata[52] = \\ ;\n assign s_axi_rdata[51] = \\ ;\n assign s_axi_rdata[50] = \\ ;\n assign s_axi_rdata[49] = \\ ;\n assign s_axi_rdata[48] = \\ ;\n assign s_axi_rdata[47] = \\ ;\n assign s_axi_rdata[46] = \\ ;\n assign s_axi_rdata[45] = \\ ;\n assign s_axi_rdata[44] = \\ ;\n assign s_axi_rdata[43] = \\ ;\n assign s_axi_rdata[42] = \\ ;\n assign s_axi_rdata[41] = \\ ;\n assign s_axi_rdata[40] = \\ ;\n assign s_axi_rdata[39] = \\ ;\n assign s_axi_rdata[38] = \\ ;\n assign s_axi_rdata[37] = \\ ;\n assign s_axi_rdata[36] = \\ ;\n assign s_axi_rdata[35] = \\ ;\n assign s_axi_rdata[34] = \\ ;\n assign s_axi_rdata[33] = \\ ;\n assign s_axi_rdata[32] = \\ ;\n assign s_axi_rdata[31] = \\ ;\n assign s_axi_rdata[30] = \\ ;\n assign s_axi_rdata[29] = \\ ;\n assign s_axi_rdata[28] = \\ ;\n assign s_axi_rdata[27] = \\ ;\n assign s_axi_rdata[26] = \\ ;\n assign s_axi_rdata[25] = \\ ;\n assign s_axi_rdata[24] = \\ ;\n assign s_axi_rdata[23] = \\ ;\n assign s_axi_rdata[22] = \\ ;\n assign s_axi_rdata[21] = \\ ;\n assign s_axi_rdata[20] = \\ ;\n assign s_axi_rdata[19] = \\ ;\n assign s_axi_rdata[18] = \\ ;\n assign s_axi_rdata[17] = \\ ;\n assign s_axi_rdata[16] = \\ ;\n assign s_axi_rdata[15] = \\ ;\n assign s_axi_rdata[14] = \\ ;\n assign s_axi_rdata[13] = \\ ;\n assign s_axi_rdata[12] = \\ ;\n assign s_axi_rdata[11] = \\ ;\n assign s_axi_rdata[10] = \\ ;\n assign s_axi_rdata[9] = \\ ;\n assign s_axi_rdata[8] = \\ ;\n assign s_axi_rdata[7] = \\ ;\n assign s_axi_rdata[6] = \\ ;\n assign s_axi_rdata[5] = \\ ;\n assign s_axi_rdata[4] = \\ ;\n assign s_axi_rdata[3] = \\ ;\n assign s_axi_rdata[2] = \\ ;\n assign s_axi_rdata[1] = \\ ;\n assign s_axi_rdata[0] = \\ ;\n assign s_axi_rid[3] = \\ ;\n assign s_axi_rid[2] = \\ ;\n assign s_axi_rid[1] = \\ ;\n assign s_axi_rid[0] = \\ ;\n assign s_axi_rlast = \\ ;\n assign s_axi_rresp[1] = \\ ;\n assign s_axi_rresp[0] = \\ ;\n assign s_axi_rvalid = \\ ;\n assign s_axi_sbiterr = \\ ;\n assign s_axi_wready = \\ ;\n assign sbiterr = \\ ;\n GND GND\n (.G(\\ ));\n input_line_buffer_blk_mem_gen_v8_3_4_synth inst_blk_mem_gen\n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_v8_3_4_synth\" *) \nmodule input_line_buffer_blk_mem_gen_v8_3_4_synth\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [255:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [11:0]addra;\n input [9:0]addrb;\n input [63:0]dina;\n input [0:0]wea;\n\n wire [11:0]addra;\n wire [9:0]addrb;\n wire clka;\n wire clkb;\n wire [63:0]dina;\n wire [255:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n input_line_buffer_blk_mem_gen_top \\gnbram.gnativebmg.native_blk_mem_gen \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_stub.v", "content": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// --------------------------------------------------------------------------------\n// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016\n// Date : Tue Nov 15 09:41:00 2016\n// Host : david-desktop-arch running 64-bit unknown\n// Command : write_verilog -force -mode synth_stub\n// /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/input_line_buffer_stub.v\n// Design : input_line_buffer\n// Purpose : Stub declaration of top-level module interface\n// Device : xc7k325tffg900-2\n// --------------------------------------------------------------------------------\n\n// This empty module with port declaration file causes synthesis tools to infer a black box for IP.\n// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.\n// Please paste the declaration into a Verilog source file or add the file as an additional source.\n(* x_core_info = \"blk_mem_gen_v8_3_4,Vivado 2016.3\" *)\nmodule input_line_buffer(clka, ena, wea, addra, dina, clkb, addrb, doutb)\n/* synthesis syn_black_box black_box_pad_pin=\"clka,ena,wea[0:0],addra[11:0],dina[63:0],clkb,addrb[9:0],doutb[255:0]\" */;\n input clka;\n input ena;\n input [0:0]wea;\n input [11:0]addra;\n input [63:0]dina;\n input clkb;\n input [9:0]addrb;\n output [255:0]doutb;\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/input_line_buffer_1/misc/blk_mem_gen_v8_3.vhd", "content": "library ieee;\nuse ieee.std_logic_1164.all;\n\nentity blk_mem_gen_v8_3_4 is\n generic (\n C_FAMILY : string := \"virtex7\";\n C_XDEVICEFAMILY : string := \"virtex7\";\n C_ELABORATION_DIR : string := \"\";\n C_INTERFACE_TYPE : integer := 0;\n C_AXI_TYPE : integer := 1;\n C_AXI_SLAVE_TYPE : integer := 0;\n C_USE_BRAM_BLOCK : integer := 0;\n C_ENABLE_32BIT_ADDRESS : integer := 0;\n C_CTRL_ECC_ALGO : string := \"ECCHSIAO32-7\";\n C_HAS_AXI_ID : integer := 0;\n C_AXI_ID_WIDTH : integer := 4;\n C_MEM_TYPE : integer := 2;\n C_BYTE_SIZE : integer := 9;\n C_ALGORITHM : integer := 0;\n C_PRIM_TYPE : integer := 3;\n C_LOAD_INIT_FILE : integer := 0;\n C_INIT_FILE_NAME : string := \"no_coe_file_loaded\";\n C_INIT_FILE : string := \"no_mem_file_loaded\";\n C_USE_DEFAULT_DATA : integer := 0;\n C_DEFAULT_DATA : string := \"0\";\n C_HAS_RSTA : integer := 0;\n C_RST_PRIORITY_A : string := \"ce\";\n C_RSTRAM_A : integer := 0;\n C_INITA_VAL : string := \"0\";\n C_HAS_ENA : integer := 1;\n C_HAS_REGCEA : integer := 0;\n C_USE_BYTE_WEA : integer := 0;\n C_WEA_WIDTH : integer := 1;\n C_WRITE_MODE_A : string := \"WRITE_FIRST\";\n C_WRITE_WIDTH_A : integer := 9;\n C_READ_WIDTH_A : integer := 9;\n C_WRITE_DEPTH_A : integer := 2048;\n C_READ_DEPTH_A : integer := 2048;\n C_ADDRA_WIDTH : integer := 11;\n C_HAS_RSTB : integer := 0;\n C_RST_PRIORITY_B : string := \"ce\";\n C_RSTRAM_B : integer := 0;\n C_INITB_VAL : string := \"0\";\n C_HAS_ENB : integer := 1;\n C_HAS_REGCEB : integer := 0;\n C_USE_BYTE_WEB : integer := 0;\n C_WEB_WIDTH : integer := 1;\n C_WRITE_MODE_B : string := \"WRITE_FIRST\";\n C_WRITE_WIDTH_B : integer := 9;\n C_READ_WIDTH_B : integer := 9;\n C_WRITE_DEPTH_B : integer := 2048;\n C_READ_DEPTH_B : integer := 2048;\n C_ADDRB_WIDTH : integer := 11;\n C_HAS_MEM_OUTPUT_REGS_A : integer := 0;\n C_HAS_MEM_OUTPUT_REGS_B : integer := 0;\n C_HAS_MUX_OUTPUT_REGS_A : integer := 0;\n C_HAS_MUX_OUTPUT_REGS_B : integer := 0;\n C_MUX_PIPELINE_STAGES : integer := 0;\n C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;\n C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;\n C_USE_SOFTECC : integer := 0;\n C_USE_ECC : integer := 0;\n C_EN_ECC_PIPE : integer := 0;\n C_HAS_INJECTERR : integer := 0;\n C_SIM_COLLISION_CHECK : string := \"none\";\n C_COMMON_CLK : integer := 0;\n C_DISABLE_WARN_BHV_COLL : integer := 0;\n C_EN_SLEEP_PIN : integer := 0;\n C_USE_URAM : integer := 0;\n C_EN_RDADDRA_CHG : integer := 0;\n C_EN_RDADDRB_CHG : integer := 0;\n C_EN_DEEPSLEEP_PIN : integer := 0;\n C_EN_SHUTDOWN_PIN : integer := 0;\n C_EN_SAFETY_CKT : integer := 0;\n C_DISABLE_WARN_BHV_RANGE : integer := 0;\n C_COUNT_36K_BRAM : string := \"\";\n C_COUNT_18K_BRAM : string := \"\";\n C_EST_POWER_SUMMARY : string := \"\"\n );\n port (\n clka : in std_logic := '0';\n rsta : in std_logic := '0';\n ena : in std_logic := '0';\n regcea : in std_logic := '0';\n wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');\n addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');\n dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');\n douta : out std_logic_vector(c_read_width_a - 1 downto 0);\n clkb : in std_logic := '0';\n rstb : in std_logic := '0';\n enb : in std_logic := '0';\n regceb : in std_logic := '0';\n web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');\n addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');\n dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');\n doutb : out std_logic_vector(c_read_width_b - 1 downto 0);\n injectsbiterr : in std_logic := '0';\n injectdbiterr : in std_logic := '0';\n eccpipece : in std_logic := '0';\n sbiterr : out std_logic;\n dbiterr : out std_logic;\n rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);\n sleep : in std_logic := '0';\n deepsleep : in std_logic := '0';\n shutdown : in std_logic := '0';\n rsta_busy : out std_logic;\n rstb_busy : out std_logic;\n s_aclk : in std_logic := '0';\n s_aresetn : in std_logic := '0';\n s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');\n s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');\n s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');\n s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');\n s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');\n s_axi_awvalid : in std_logic := '0';\n s_axi_awready : out std_logic;\n s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');\n s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');\n s_axi_wlast : in std_logic := '0';\n s_axi_wvalid : in std_logic := '0';\n s_axi_wready : out std_logic;\n s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);\n s_axi_bresp : out std_logic_vector(1 downto 0);\n s_axi_bvalid : out std_logic;\n s_axi_bready : in std_logic := '0';\n s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');\n s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');\n s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');\n s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');\n s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');\n s_axi_arvalid : in std_logic := '0';\n s_axi_arready : out std_logic;\n s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);\n s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);\n s_axi_rresp : out std_logic_vector(2 - 1 downto 0);\n s_axi_rlast : out std_logic;\n s_axi_rvalid : out std_logic;\n s_axi_rready : in std_logic := '0';\n s_axi_injectsbiterr : in std_logic := '0';\n s_axi_injectdbiterr : in std_logic := '0';\n s_axi_sbiterr : out std_logic;\n s_axi_dbiterr : out std_logic;\n s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)\n );\nend entity blk_mem_gen_v8_3_4;\n\narchitecture xilinx of blk_mem_gen_v8_3_4 is\n begin\n end \narchitecture xilinx;\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/input_line_buffer_1/sim/input_line_buffer.v", "content": "// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:blk_mem_gen:8.3\n// IP Revision: 4\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule input_line_buffer (\n clka,\n ena,\n wea,\n addra,\n dina,\n clkb,\n addrb,\n doutb\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA CLK\" *)\ninput wire clka;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA EN\" *)\ninput wire ena;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA WE\" *)\ninput wire [0 : 0] wea;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR\" *)\ninput wire [11 : 0] addra;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DIN\" *)\ninput wire [63 : 0] dina;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB CLK\" *)\ninput wire clkb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR\" *)\ninput wire [9 : 0] addrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT\" *)\noutput wire [255 : 0] doutb;\n\n blk_mem_gen_v8_3_4 #(\n .C_FAMILY(\"kintex7\"),\n .C_XDEVICEFAMILY(\"kintex7\"),\n .C_ELABORATION_DIR(\"./\"),\n .C_INTERFACE_TYPE(0),\n .C_AXI_TYPE(1),\n .C_AXI_SLAVE_TYPE(0),\n .C_USE_BRAM_BLOCK(0),\n .C_ENABLE_32BIT_ADDRESS(0),\n .C_CTRL_ECC_ALGO(\"NONE\"),\n .C_HAS_AXI_ID(0),\n .C_AXI_ID_WIDTH(4),\n .C_MEM_TYPE(1),\n .C_BYTE_SIZE(9),\n .C_ALGORITHM(1),\n .C_PRIM_TYPE(1),\n .C_LOAD_INIT_FILE(0),\n .C_INIT_FILE_NAME(\"no_coe_file_loaded\"),\n .C_INIT_FILE(\"input_line_buffer.mem\"),\n .C_USE_DEFAULT_DATA(0),\n .C_DEFAULT_DATA(\"0\"),\n .C_HAS_RSTA(0),\n .C_RST_PRIORITY_A(\"CE\"),\n .C_RSTRAM_A(0),\n .C_INITA_VAL(\"0\"),\n .C_HAS_ENA(1),\n .C_HAS_REGCEA(0),\n .C_USE_BYTE_WEA(0),\n .C_WEA_WIDTH(1),\n .C_WRITE_MODE_A(\"NO_CHANGE\"),\n .C_WRITE_WIDTH_A(64),\n .C_READ_WIDTH_A(64),\n .C_WRITE_DEPTH_A(4096),\n .C_READ_DEPTH_A(4096),\n .C_ADDRA_WIDTH(12),\n .C_HAS_RSTB(0),\n .C_RST_PRIORITY_B(\"CE\"),\n .C_RSTRAM_B(0),\n .C_INITB_VAL(\"0\"),\n .C_HAS_ENB(0),\n .C_HAS_REGCEB(0),\n .C_USE_BYTE_WEB(0),\n .C_WEB_WIDTH(1),\n .C_WRITE_MODE_B(\"WRITE_FIRST\"),\n .C_WRITE_WIDTH_B(256),\n .C_READ_WIDTH_B(256),\n .C_WRITE_DEPTH_B(1024),\n .C_READ_DEPTH_B(1024),\n .C_ADDRB_WIDTH(10),\n .C_HAS_MEM_OUTPUT_REGS_A(0),\n .C_HAS_MEM_OUTPUT_REGS_B(0),\n .C_HAS_MUX_OUTPUT_REGS_A(0),\n .C_HAS_MUX_OUTPUT_REGS_B(0),\n .C_MUX_PIPELINE_STAGES(0),\n .C_HAS_SOFTECC_INPUT_REGS_A(0),\n .C_HAS_SOFTECC_OUTPUT_REGS_B(0),\n .C_USE_SOFTECC(0),\n .C_USE_ECC(0),\n .C_EN_ECC_PIPE(0),\n .C_HAS_INJECTERR(0),\n .C_SIM_COLLISION_CHECK(\"ALL\"),\n .C_COMMON_CLK(0),\n .C_DISABLE_WARN_BHV_COLL(0),\n .C_EN_SLEEP_PIN(0),\n .C_USE_URAM(0),\n .C_EN_RDADDRA_CHG(0),\n .C_EN_RDADDRB_CHG(0),\n .C_EN_DEEPSLEEP_PIN(0),\n .C_EN_SHUTDOWN_PIN(0),\n .C_EN_SAFETY_CKT(0),\n .C_DISABLE_WARN_BHV_RANGE(0),\n .C_COUNT_36K_BRAM(\"7\"),\n .C_COUNT_18K_BRAM(\"1\"),\n .C_EST_POWER_SUMMARY(\"Estimated Power for IP : 36.714252 mW\")\n ) inst (\n .clka(clka),\n .rsta(1'D0),\n .ena(ena),\n .regcea(1'D0),\n .wea(wea),\n .addra(addra),\n .dina(dina),\n .douta(),\n .clkb(clkb),\n .rstb(1'D0),\n .enb(1'D0),\n .regceb(1'D0),\n .web(1'B0),\n .addrb(addrb),\n .dinb(256'B0),\n .doutb(doutb),\n .injectsbiterr(1'D0),\n .injectdbiterr(1'D0),\n .eccpipece(1'D0),\n .sbiterr(),\n .dbiterr(),\n .rdaddrecc(),\n .sleep(1'D0),\n .deepsleep(1'D0),\n .shutdown(1'D0),\n .rsta_busy(),\n .rstb_busy(),\n .s_aclk(1'H0),\n .s_aresetn(1'D0),\n .s_axi_awid(4'B0),\n .s_axi_awaddr(32'B0),\n .s_axi_awlen(8'B0),\n .s_axi_awsize(3'B0),\n .s_axi_awburst(2'B0),\n .s_axi_awvalid(1'D0),\n .s_axi_awready(),\n .s_axi_wdata(64'B0),\n .s_axi_wstrb(1'B0),\n .s_axi_wlast(1'D0),\n .s_axi_wvalid(1'D0),\n .s_axi_wready(),\n .s_axi_bid(),\n .s_axi_bresp(),\n .s_axi_bvalid(),\n .s_axi_bready(1'D0),\n .s_axi_arid(4'B0),\n .s_axi_araddr(32'B0),\n .s_axi_arlen(8'B0),\n .s_axi_arsize(3'B0),\n .s_axi_arburst(2'B0),\n .s_axi_arvalid(1'D0),\n .s_axi_arready(),\n .s_axi_rid(),\n .s_axi_rdata(),\n .s_axi_rresp(),\n .s_axi_rlast(),\n .s_axi_rvalid(),\n .s_axi_rready(1'D0),\n .s_axi_injectsbiterr(1'D0),\n .s_axi_injectdbiterr(1'D0),\n .s_axi_sbiterr(),\n .s_axi_dbiterr(),\n .s_axi_rdaddrecc()\n );\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/input_line_buffer_1/simulation/blk_mem_gen_v8_3.v", "content": "/******************************************************************************\n-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n--\n *****************************************************************************\n *\n * Filename: blk_mem_gen_v8_3_4.v\n *\n * Description:\n * This file is the Verilog behvarial model for the\n * Block Memory Generator Core.\n *\n *****************************************************************************\n * Author: Xilinx\n *\n * History: Jan 11, 2006 Initial revision\n * Jun 11, 2007 Added independent register stages for \n * Port A and Port B (IP1_Jm/v2.5)\n * Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)\n * Mar 13, 2008 Behavioral model optimizations\n * April 07, 2009 : Added support for Spartan-6 and Virtex-6\n * features, including the following:\n * (i) error injection, detection and/or correction\n * (ii) reset priority\n * (iii) special reset behavior\n * \n *****************************************************************************/\n`timescale 1ps/1ps\n\nmodule STATE_LOGIC_v8_3 (O, I0, I1, I2, I3, I4, I5);\n\n parameter INIT = 64'h0000000000000000;\n\n input I0, I1, I2, I3, I4, I5;\n\n output O;\n\n reg O;\n reg tmp;\n\n always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin\n \n tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5;\n\n if ( tmp == 0 || tmp == 1)\n\n O = INIT[{I5, I4, I3, I2, I1, I0}];\n\n end\nendmodule\n\nmodule beh_vlog_muxf7_v8_3 (O, I0, I1, S);\n\n output O;\n reg O;\n\n input I0, I1, S;\n\n\talways @(I0 or I1 or S) \n\t if (S)\n\t\tO = I1;\n\t else\n\t\tO = I0;\nendmodule\n\nmodule beh_vlog_ff_clr_v8_3 (Q, C, CLR, D);\n parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n output Q;\n\n input C, CLR, D;\n\n reg Q;\n\n initial Q= 1'b0;\n\n always @(posedge C )\n if (CLR)\n\tQ<= 1'b0;\n else\n\tQ<= #FLOP_DELAY D;\n\n\nendmodule\n\nmodule beh_vlog_ff_pre_v8_3 (Q, C, D, PRE);\n\n parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n output Q;\n input C, D, PRE;\n\n reg Q;\n\n initial Q= 1'b0;\n\n always @(posedge C )\n if (PRE)\n Q <= 1'b1;\n else\n\t Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule beh_vlog_ff_ce_clr_v8_3 (Q, C, CE, CLR, D);\n\n parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n output Q;\n input C, CE, CLR, D;\n\n reg Q;\n\n initial Q= 1'b0;\n always @(posedge C )\n if (CLR)\n Q <= 1'b0;\n else if (CE)\n\t Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule write_netlist_v8_3\n#(\n parameter\t C_AXI_TYPE = 0\n )\n (\n S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,\n w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,\n S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c \n );\n\n input S_ACLK;\n input S_ARESETN;\n input S_AXI_AWVALID;\n input S_AXI_WVALID;\n input S_AXI_BREADY;\n input w_last_c;\n input bready_timeout_c;\n output aw_ready_r;\n output S_AXI_WREADY;\n output S_AXI_BVALID;\n output S_AXI_WR_EN;\n output addr_en_c;\n output incr_addr_c;\n output bvalid_c;\n //-------------------------------------------------------------------------\n //AXI LITE\n //-------------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm\n wire w_ready_r_7;\n wire w_ready_c;\n wire aw_ready_c;\n wire NlwRenamedSignal_bvalid_c;\n wire NlwRenamedSignal_incr_addr_c;\n wire present_state_FSM_FFd3_13;\n wire present_state_FSM_FFd2_14;\n wire present_state_FSM_FFd1_15;\n wire present_state_FSM_FFd4_16;\n wire present_state_FSM_FFd4_In;\n wire present_state_FSM_FFd3_In;\n wire present_state_FSM_FFd2_In;\n wire present_state_FSM_FFd1_In;\n wire present_state_FSM_FFd4_In1_21;\n wire [0:0] Mmux_aw_ready_c ; \nbegin\n assign\n S_AXI_WREADY = w_ready_r_7,\n S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,\n S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,\n incr_addr_c = NlwRenamedSignal_incr_addr_c,\n bvalid_c = NlwRenamedSignal_bvalid_c;\n\n assign NlwRenamedSignal_incr_addr_c = 1'b0;\n\n beh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n aw_ready_r_2 (\n .C ( S_ACLK), \n .CLR ( S_ARESETN), \n .D ( aw_ready_c), \n .Q ( aw_ready_r)\n );\n beh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n w_ready_r (\n .C ( S_ACLK), \n .CLR ( S_ARESETN), \n .D ( w_ready_c), \n .Q ( w_ready_r_7)\n );\n beh_vlog_ff_pre_v8_3 #(\n .INIT (1'b1))\n present_state_FSM_FFd4 (\n .C ( S_ACLK), \n .D ( present_state_FSM_FFd4_In), \n .PRE ( S_ARESETN), \n .Q ( present_state_FSM_FFd4_16)\n );\n beh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n present_state_FSM_FFd3 (\n .C ( S_ACLK), \n .CLR ( S_ARESETN), \n .D ( present_state_FSM_FFd3_In), \n .Q ( present_state_FSM_FFd3_13)\n );\n beh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n present_state_FSM_FFd2 (\n .C ( S_ACLK), \n .CLR ( S_ARESETN), \n .D ( present_state_FSM_FFd2_In), \n .Q ( present_state_FSM_FFd2_14)\n );\nbeh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n present_state_FSM_FFd1 (\n .C ( S_ACLK), \n .CLR ( S_ARESETN), \n .D ( present_state_FSM_FFd1_In), \n .Q ( present_state_FSM_FFd1_15)\n );\nSTATE_LOGIC_v8_3 #(\n .INIT (64'h0000000055554440))\n present_state_FSM_FFd3_In1 (\n .I0 ( S_AXI_WVALID), \n .I1 ( S_AXI_AWVALID), \n .I2 ( present_state_FSM_FFd2_14), \n .I3 ( present_state_FSM_FFd4_16), \n .I4 ( present_state_FSM_FFd3_13), \n .I5 (1'b0), \n .O ( present_state_FSM_FFd3_In)\n );\nSTATE_LOGIC_v8_3 #(\n .INIT (64'h0000000088880800))\n present_state_FSM_FFd2_In1 (\n .I0 ( S_AXI_AWVALID), \n .I1 ( S_AXI_WVALID), \n .I2 ( bready_timeout_c), \n .I3 ( present_state_FSM_FFd2_14), \n .I4 ( present_state_FSM_FFd4_16), \n .I5 (1'b0), \n .O ( present_state_FSM_FFd2_In)\n );\nSTATE_LOGIC_v8_3 #(\n .INIT (64'h00000000AAAA2000))\n Mmux_addr_en_c_0_1 (\n .I0 ( S_AXI_AWVALID), \n .I1 ( bready_timeout_c), \n .I2 ( present_state_FSM_FFd2_14), \n .I3 ( S_AXI_WVALID), \n .I4 ( present_state_FSM_FFd4_16), \n .I5 (1'b0), \n .O ( addr_en_c)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'hF5F07570F5F05500))\n Mmux_w_ready_c_0_1 (\n .I0 ( S_AXI_WVALID), \n .I1 ( bready_timeout_c), \n .I2 ( S_AXI_AWVALID), \n .I3 ( present_state_FSM_FFd3_13), \n .I4 ( present_state_FSM_FFd4_16), \n .I5 ( present_state_FSM_FFd2_14), \n .O ( w_ready_c)\n );\nSTATE_LOGIC_v8_3 #(\n .INIT (64'h88808880FFFF8880))\n present_state_FSM_FFd1_In1 (\n .I0 ( S_AXI_WVALID), \n .I1 ( bready_timeout_c), \n .I2 ( present_state_FSM_FFd3_13), \n .I3 ( present_state_FSM_FFd2_14), \n .I4 ( present_state_FSM_FFd1_15), \n .I5 ( S_AXI_BREADY), \n .O ( present_state_FSM_FFd1_In)\n );\nSTATE_LOGIC_v8_3 #(\n .INIT (64'h00000000000000A8))\n Mmux_S_AXI_WR_EN_0_1 (\n .I0 ( S_AXI_WVALID), \n .I1 ( present_state_FSM_FFd2_14), \n .I2 ( present_state_FSM_FFd3_13), \n .I3 (1'b0), \n .I4 (1'b0), \n .I5 (1'b0), \n .O ( NlwRenamedSignal_bvalid_c)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h2F0F27072F0F2200))\n present_state_FSM_FFd4_In1 (\n .I0 ( S_AXI_WVALID), \n .I1 ( bready_timeout_c), \n .I2 ( S_AXI_AWVALID), \n .I3 ( present_state_FSM_FFd3_13), \n .I4 ( present_state_FSM_FFd4_16), \n .I5 ( present_state_FSM_FFd2_14), \n .O ( present_state_FSM_FFd4_In1_21)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h00000000000000F8))\n present_state_FSM_FFd4_In2 ( \n .I0 ( present_state_FSM_FFd1_15), \n .I1 ( S_AXI_BREADY), \n .I2 ( present_state_FSM_FFd4_In1_21), \n .I3 (1'b0), \n .I4 (1'b0), \n .I5 (1'b0), \n .O ( present_state_FSM_FFd4_In)\n );\nSTATE_LOGIC_v8_3 #(\n .INIT (64'h7535753575305500))\n Mmux_aw_ready_c_0_1 ( \n .I0 ( S_AXI_AWVALID), \n .I1 ( bready_timeout_c), \n .I2 ( S_AXI_WVALID), \n .I3 ( present_state_FSM_FFd4_16), \n .I4 ( present_state_FSM_FFd3_13), \n .I5 ( present_state_FSM_FFd2_14), \n .O ( Mmux_aw_ready_c[0])\n );\nSTATE_LOGIC_v8_3 #(\n .INIT (64'h00000000000000F8))\n Mmux_aw_ready_c_0_2 (\n .I0 ( present_state_FSM_FFd1_15), \n .I1 ( S_AXI_BREADY), \n .I2 ( Mmux_aw_ready_c[0]), \n .I3 (1'b0), \n .I4 (1'b0), \n .I5 (1'b0), \n .O ( aw_ready_c)\n );\nend \nend \nendgenerate\n\n //---------------------------------------------------------------------\n // AXI FULL\n //---------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm\n wire w_ready_r_8; \n wire w_ready_c; \n wire aw_ready_c; \n wire NlwRenamedSig_OI_bvalid_c; \n wire present_state_FSM_FFd1_16; \n wire present_state_FSM_FFd4_17; \n wire present_state_FSM_FFd3_18; \n wire present_state_FSM_FFd2_19; \n wire present_state_FSM_FFd4_In; \n wire present_state_FSM_FFd3_In; \n wire present_state_FSM_FFd2_In; \n wire present_state_FSM_FFd1_In; \n wire present_state_FSM_FFd2_In1_24; \n wire present_state_FSM_FFd4_In1_25; \n wire N2; \n wire N4; \nbegin\nassign\n S_AXI_WREADY = w_ready_r_8,\n bvalid_c = NlwRenamedSig_OI_bvalid_c,\n S_AXI_BVALID = 1'b0;\n\nbeh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n aw_ready_r_2\n (\n .C ( S_ACLK),\n .CLR ( S_ARESETN),\n .D ( aw_ready_c),\n .Q ( aw_ready_r)\n );\nbeh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n w_ready_r\n (\n .C ( S_ACLK),\n .CLR ( S_ARESETN),\n .D ( w_ready_c),\n .Q ( w_ready_r_8)\n );\n beh_vlog_ff_pre_v8_3 #(\n .INIT (1'b1))\n present_state_FSM_FFd4\n (\n .C ( S_ACLK),\n .D ( present_state_FSM_FFd4_In),\n .PRE ( S_ARESETN),\n .Q ( present_state_FSM_FFd4_17)\n );\nbeh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n present_state_FSM_FFd3\n (\n .C ( S_ACLK),\n .CLR ( S_ARESETN),\n .D ( present_state_FSM_FFd3_In),\n .Q ( present_state_FSM_FFd3_18)\n );\nbeh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n present_state_FSM_FFd2\n (\n .C ( S_ACLK),\n .CLR ( S_ARESETN),\n .D ( present_state_FSM_FFd2_In),\n .Q ( present_state_FSM_FFd2_19)\n );\n beh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n present_state_FSM_FFd1\n (\n .C ( S_ACLK),\n .CLR ( S_ARESETN),\n .D ( present_state_FSM_FFd1_In),\n .Q ( present_state_FSM_FFd1_16)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000000005540))\n present_state_FSM_FFd3_In1\n (\n .I0 ( S_AXI_WVALID),\n .I1 ( present_state_FSM_FFd4_17),\n .I2 ( S_AXI_AWVALID),\n .I3 ( present_state_FSM_FFd3_18),\n .I4 (1'b0),\n .I5 (1'b0),\n .O ( present_state_FSM_FFd3_In)\n );\nSTATE_LOGIC_v8_3 #(\n .INIT (64'hBF3FBB33AF0FAA00))\n Mmux_aw_ready_c_0_2\n (\n .I0 ( S_AXI_BREADY),\n .I1 ( bready_timeout_c),\n .I2 ( S_AXI_AWVALID),\n .I3 ( present_state_FSM_FFd1_16),\n .I4 ( present_state_FSM_FFd4_17),\n .I5 ( NlwRenamedSig_OI_bvalid_c),\n .O ( aw_ready_c)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'hAAAAAAAA20000000))\n Mmux_addr_en_c_0_1\n (\n .I0 ( S_AXI_AWVALID),\n .I1 ( bready_timeout_c),\n .I2 ( present_state_FSM_FFd2_19),\n .I3 ( S_AXI_WVALID),\n .I4 ( w_last_c),\n .I5 ( present_state_FSM_FFd4_17),\n .O ( addr_en_c)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h00000000000000A8))\n Mmux_S_AXI_WR_EN_0_1\n (\n .I0 ( S_AXI_WVALID),\n .I1 ( present_state_FSM_FFd2_19),\n .I2 ( present_state_FSM_FFd3_18),\n .I3 (1'b0),\n .I4 (1'b0),\n .I5 (1'b0),\n .O ( S_AXI_WR_EN)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000000002220))\n Mmux_incr_addr_c_0_1\n (\n .I0 ( S_AXI_WVALID),\n .I1 ( w_last_c),\n .I2 ( present_state_FSM_FFd2_19),\n .I3 ( present_state_FSM_FFd3_18),\n .I4 (1'b0),\n .I5 (1'b0),\n .O ( incr_addr_c)\n );\nSTATE_LOGIC_v8_3 #(\n .INIT (64'h0000000000008880))\n Mmux_aw_ready_c_0_11\n (\n .I0 ( S_AXI_WVALID),\n .I1 ( w_last_c),\n .I2 ( present_state_FSM_FFd2_19),\n .I3 ( present_state_FSM_FFd3_18),\n .I4 (1'b0),\n .I5 (1'b0),\n .O ( NlwRenamedSig_OI_bvalid_c)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h000000000000D5C0))\n present_state_FSM_FFd2_In1\n (\n .I0 ( w_last_c),\n .I1 ( S_AXI_AWVALID),\n .I2 ( present_state_FSM_FFd4_17),\n .I3 ( present_state_FSM_FFd3_18),\n .I4 (1'b0),\n .I5 (1'b0),\n .O ( present_state_FSM_FFd2_In1_24)\n );\nSTATE_LOGIC_v8_3 #(\n .INIT (64'hFFFFAAAA08AAAAAA))\n present_state_FSM_FFd2_In2\n (\n .I0 ( present_state_FSM_FFd2_19),\n .I1 ( S_AXI_AWVALID),\n .I2 ( bready_timeout_c),\n .I3 ( w_last_c),\n .I4 ( S_AXI_WVALID),\n .I5 ( present_state_FSM_FFd2_In1_24),\n .O ( present_state_FSM_FFd2_In)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h00C0004000C00000))\n present_state_FSM_FFd4_In1\n (\n .I0 ( S_AXI_AWVALID),\n .I1 ( w_last_c),\n .I2 ( S_AXI_WVALID),\n .I3 ( bready_timeout_c),\n .I4 ( present_state_FSM_FFd3_18),\n .I5 ( present_state_FSM_FFd2_19),\n .O ( present_state_FSM_FFd4_In1_25)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h00000000FFFF88F8))\n present_state_FSM_FFd4_In2\n (\n .I0 ( present_state_FSM_FFd1_16),\n .I1 ( S_AXI_BREADY),\n .I2 ( present_state_FSM_FFd4_17),\n .I3 ( S_AXI_AWVALID),\n .I4 ( present_state_FSM_FFd4_In1_25),\n .I5 (1'b0),\n .O ( present_state_FSM_FFd4_In)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000000000007))\n Mmux_w_ready_c_0_SW0\n (\n .I0 ( w_last_c),\n .I1 ( S_AXI_WVALID),\n .I2 (1'b0),\n .I3 (1'b0),\n .I4 (1'b0),\n .I5 (1'b0),\n .O ( N2)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'hFABAFABAFAAAF000))\n Mmux_w_ready_c_0_Q\n (\n .I0 ( N2),\n .I1 ( bready_timeout_c),\n .I2 ( S_AXI_AWVALID),\n .I3 ( present_state_FSM_FFd4_17),\n .I4 ( present_state_FSM_FFd3_18),\n .I5 ( present_state_FSM_FFd2_19),\n .O ( w_ready_c)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000000000008))\n Mmux_aw_ready_c_0_11_SW0\n (\n .I0 ( bready_timeout_c),\n .I1 ( S_AXI_WVALID),\n .I2 (1'b0),\n .I3 (1'b0),\n .I4 (1'b0),\n .I5 (1'b0),\n .O ( N4)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h88808880FFFF8880))\n present_state_FSM_FFd1_In1\n (\n .I0 ( w_last_c),\n .I1 ( N4),\n .I2 ( present_state_FSM_FFd2_19),\n .I3 ( present_state_FSM_FFd3_18),\n .I4 ( present_state_FSM_FFd1_16),\n .I5 ( S_AXI_BREADY),\n .O ( present_state_FSM_FFd1_In)\n );\nend\nend\nendgenerate\nendmodule\n\n\nmodule read_netlist_v8_3 #(\n parameter C_AXI_TYPE = 1,\n parameter C_ADDRB_WIDTH = 12\n ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,\n S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,\n S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,\n S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);\n\n input S_AXI_R_LAST_INT;\n input S_ACLK;\n input S_ARESETN;\n input S_AXI_ARVALID;\n input S_AXI_RREADY;\n output S_AXI_INCR_ADDR;\n output S_AXI_ADDR_EN;\n output S_AXI_SINGLE_TRANS;\n output S_AXI_MUX_SEL;\n output S_AXI_R_LAST;\n output S_AXI_ARREADY;\n output S_AXI_RLAST;\n output S_AXI_RVALID;\n output S_AXI_RD_EN;\n input [7:0] S_AXI_ARLEN;\n\n wire present_state_FSM_FFd1_13 ; \n wire present_state_FSM_FFd2_14 ; \n wire gaxi_full_sm_outstanding_read_r_15 ; \n wire gaxi_full_sm_ar_ready_r_16 ; \n wire gaxi_full_sm_r_last_r_17 ; \n wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; \n wire gaxi_full_sm_r_valid_c ; \n wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; \n wire gaxi_full_sm_ar_ready_c ; \n wire gaxi_full_sm_outstanding_read_c ; \n wire NlwRenamedSig_OI_S_AXI_R_LAST ; \n wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; \n wire present_state_FSM_FFd2_In ; \n wire present_state_FSM_FFd1_In ; \n wire Mmux_S_AXI_R_LAST13 ; \n wire N01 ; \n wire N2 ; \n wire Mmux_gaxi_full_sm_ar_ready_c11 ; \n wire N4 ; \n wire N8 ; \n wire N9 ; \n wire N10 ; \n wire N11 ; \n wire N12 ; \n wire N13 ; \n assign\n S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,\n S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,\n S_AXI_RLAST = gaxi_full_sm_r_last_r_17,\n S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;\n\n beh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n gaxi_full_sm_outstanding_read_r (\n .C (S_ACLK),\n .CLR(S_ARESETN),\n .D(gaxi_full_sm_outstanding_read_c),\n .Q(gaxi_full_sm_outstanding_read_r_15)\n );\n beh_vlog_ff_ce_clr_v8_3 #(\n .INIT (1'b0))\n gaxi_full_sm_r_valid_r (\n .C (S_ACLK),\n .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n .CLR (S_ARESETN),\n .D (gaxi_full_sm_r_valid_c),\n .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)\n );\n beh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n gaxi_full_sm_ar_ready_r (\n .C (S_ACLK),\n .CLR (S_ARESETN),\n .D (gaxi_full_sm_ar_ready_c),\n .Q (gaxi_full_sm_ar_ready_r_16)\n );\n beh_vlog_ff_ce_clr_v8_3 #(\n .INIT(1'b0))\n gaxi_full_sm_r_last_r (\n .C (S_ACLK),\n .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n .CLR (S_ARESETN),\n .D (NlwRenamedSig_OI_S_AXI_R_LAST),\n .Q (gaxi_full_sm_r_last_r_17)\n );\n beh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n present_state_FSM_FFd2 (\n .C ( S_ACLK),\n .CLR ( S_ARESETN),\n .D ( present_state_FSM_FFd2_In),\n .Q ( present_state_FSM_FFd2_14)\n );\n beh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n present_state_FSM_FFd1 (\n .C (S_ACLK),\n .CLR (S_ARESETN),\n .D (present_state_FSM_FFd1_In),\n .Q (present_state_FSM_FFd1_13)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h000000000000000B))\n S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (\n .I0 ( S_AXI_RREADY),\n .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I2 (1'b0),\n .I3 (1'b0),\n .I4 (1'b0),\n .I5 (1'b0),\n .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000000000008))\n Mmux_S_AXI_SINGLE_TRANS11 (\n .I0 (S_AXI_ARVALID),\n .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n .I2 (1'b0),\n .I3 (1'b0),\n .I4 (1'b0),\n .I5 (1'b0),\n .O (S_AXI_SINGLE_TRANS)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000000000004))\n Mmux_S_AXI_ADDR_EN11 (\n .I0 (present_state_FSM_FFd1_13),\n .I1 (S_AXI_ARVALID),\n .I2 (1'b0),\n .I3 (1'b0),\n .I4 (1'b0),\n .I5 (1'b0),\n .O (S_AXI_ADDR_EN)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'hECEE2022EEEE2022))\n present_state_FSM_FFd2_In1 (\n .I0 ( S_AXI_ARVALID),\n .I1 ( present_state_FSM_FFd1_13),\n .I2 ( S_AXI_RREADY),\n .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n .I4 ( present_state_FSM_FFd2_14),\n .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .O ( present_state_FSM_FFd2_In)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000044440444))\n Mmux_S_AXI_R_LAST131 (\n .I0 ( present_state_FSM_FFd1_13),\n .I1 ( S_AXI_ARVALID),\n .I2 ( present_state_FSM_FFd2_14),\n .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I4 ( S_AXI_RREADY),\n .I5 (1'b0),\n .O ( Mmux_S_AXI_R_LAST13)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h4000FFFF40004000))\n Mmux_S_AXI_INCR_ADDR11 (\n .I0 ( S_AXI_R_LAST_INT),\n .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n .I2 ( present_state_FSM_FFd2_14),\n .I3 ( present_state_FSM_FFd1_13),\n .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n .I5 ( Mmux_S_AXI_R_LAST13),\n .O ( S_AXI_INCR_ADDR)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h00000000000000FE))\n S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (\n .I0 ( S_AXI_ARLEN[2]),\n .I1 ( S_AXI_ARLEN[1]),\n .I2 ( S_AXI_ARLEN[0]),\n .I3 ( 1'b0),\n .I4 ( 1'b0),\n .I5 ( 1'b0),\n .O ( N01)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000000000001))\n S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (\n .I0 ( S_AXI_ARLEN[7]),\n .I1 ( S_AXI_ARLEN[6]),\n .I2 ( S_AXI_ARLEN[5]),\n .I3 ( S_AXI_ARLEN[4]),\n .I4 ( S_AXI_ARLEN[3]),\n .I5 ( N01),\n .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000000000007))\n Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (\n .I0 ( S_AXI_ARVALID),\n .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n .I2 ( 1'b0),\n .I3 ( 1'b0),\n .I4 ( 1'b0),\n .I5 ( 1'b0),\n .O ( N2)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0020000002200200))\n Mmux_gaxi_full_sm_outstanding_read_c1 (\n .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I1 ( S_AXI_RREADY),\n .I2 ( present_state_FSM_FFd1_13),\n .I3 ( present_state_FSM_FFd2_14),\n .I4 ( gaxi_full_sm_outstanding_read_r_15),\n .I5 ( N2),\n .O ( gaxi_full_sm_outstanding_read_c)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000000004555))\n Mmux_gaxi_full_sm_ar_ready_c12 (\n .I0 ( S_AXI_ARVALID),\n .I1 ( S_AXI_RREADY),\n .I2 ( present_state_FSM_FFd2_14),\n .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I4 ( 1'b0),\n .I5 ( 1'b0),\n .O ( Mmux_gaxi_full_sm_ar_ready_c11)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h00000000000000EF))\n Mmux_S_AXI_R_LAST11_SW0 (\n .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n .I1 ( S_AXI_RREADY),\n .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I3 ( 1'b0),\n .I4 ( 1'b0),\n .I5 ( 1'b0),\n .O ( N4)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'hFCAAFC0A00AA000A))\n Mmux_S_AXI_R_LAST11 (\n .I0 ( S_AXI_ARVALID),\n .I1 ( gaxi_full_sm_outstanding_read_r_15),\n .I2 ( present_state_FSM_FFd2_14),\n .I3 ( present_state_FSM_FFd1_13),\n .I4 ( N4),\n .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n .O ( gaxi_full_sm_r_valid_c)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h00000000AAAAAA08))\n S_AXI_MUX_SEL1 (\n .I0 (present_state_FSM_FFd1_13),\n .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I2 (S_AXI_RREADY),\n .I3 (present_state_FSM_FFd2_14),\n .I4 (gaxi_full_sm_outstanding_read_r_15),\n .I5 (1'b0),\n .O (S_AXI_MUX_SEL)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'hF3F3F755A2A2A200))\n Mmux_S_AXI_RD_EN11 (\n .I0 ( present_state_FSM_FFd1_13),\n .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I2 ( S_AXI_RREADY),\n .I3 ( gaxi_full_sm_outstanding_read_r_15),\n .I4 ( present_state_FSM_FFd2_14),\n .I5 ( S_AXI_ARVALID),\n .O ( S_AXI_RD_EN)\n );\n beh_vlog_muxf7_v8_3 present_state_FSM_FFd1_In3 (\n .I0 ( N8),\n .I1 ( N9),\n .S ( present_state_FSM_FFd1_13),\n .O ( present_state_FSM_FFd1_In)\n );\n\n STATE_LOGIC_v8_3 #(\n .INIT (64'h000000005410F4F0))\n present_state_FSM_FFd1_In3_F (\n .I0 ( S_AXI_RREADY),\n .I1 ( present_state_FSM_FFd2_14),\n .I2 ( S_AXI_ARVALID),\n .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n .I5 ( 1'b0),\n .O ( N8)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000072FF7272))\n present_state_FSM_FFd1_In3_G (\n .I0 ( present_state_FSM_FFd2_14),\n .I1 ( S_AXI_R_LAST_INT),\n .I2 ( gaxi_full_sm_outstanding_read_r_15),\n .I3 ( S_AXI_RREADY),\n .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I5 ( 1'b0),\n .O ( N9)\n );\n beh_vlog_muxf7_v8_3 Mmux_gaxi_full_sm_ar_ready_c14 (\n .I0 ( N10),\n .I1 ( N11),\n .S ( present_state_FSM_FFd1_13),\n .O ( gaxi_full_sm_ar_ready_c)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h00000000FFFF88A8))\n Mmux_gaxi_full_sm_ar_ready_c14_F (\n .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n .I1 ( S_AXI_RREADY),\n .I2 ( present_state_FSM_FFd2_14),\n .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I4 ( Mmux_gaxi_full_sm_ar_ready_c11),\n .I5 ( 1'b0),\n .O ( N10)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h000000008D008D8D))\n Mmux_gaxi_full_sm_ar_ready_c14_G (\n .I0 ( present_state_FSM_FFd2_14),\n .I1 ( S_AXI_R_LAST_INT),\n .I2 ( gaxi_full_sm_outstanding_read_r_15),\n .I3 ( S_AXI_RREADY),\n .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I5 ( 1'b0),\n .O ( N11)\n );\n beh_vlog_muxf7_v8_3 Mmux_S_AXI_R_LAST1 (\n .I0 ( N12),\n .I1 ( N13),\n .S ( present_state_FSM_FFd1_13),\n .O ( NlwRenamedSig_OI_S_AXI_R_LAST)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000088088888))\n Mmux_S_AXI_R_LAST1_F (\n .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n .I1 ( S_AXI_ARVALID),\n .I2 ( present_state_FSM_FFd2_14),\n .I3 ( S_AXI_RREADY),\n .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I5 ( 1'b0),\n .O ( N12)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h00000000E400E4E4))\n Mmux_S_AXI_R_LAST1_G (\n .I0 ( present_state_FSM_FFd2_14),\n .I1 ( gaxi_full_sm_outstanding_read_r_15),\n .I2 ( S_AXI_R_LAST_INT),\n .I3 ( S_AXI_RREADY),\n .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I5 ( 1'b0),\n .O ( N13)\n );\n\nendmodule\n\n\nmodule blk_mem_axi_write_wrapper_beh_v8_3\n # (\n // AXI Interface related parameters start here\n parameter C_INTERFACE_TYPE = 0, // 0: Native Interface; 1: AXI Interface\n parameter C_AXI_TYPE = 0, // 0: AXI Lite; 1: AXI Full;\n parameter C_AXI_SLAVE_TYPE = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;\n parameter C_MEMORY_TYPE = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;\n parameter C_WRITE_DEPTH_A = 0,\n parameter C_AXI_AWADDR_WIDTH = 32,\n parameter C_ADDRA_WIDTH \t = 12,\n parameter C_AXI_WDATA_WIDTH = 32,\n parameter C_HAS_AXI_ID = 0,\n parameter C_AXI_ID_WIDTH = 4,\n // AXI OUTSTANDING WRITES\n parameter C_AXI_OS_WR = 2\n )\n (\n // AXI Global Signals\n input S_ACLK, \n input S_ARESETN,\n // AXI Full/Lite Slave Write Channel (write side)\n input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,\n input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,\n input [8-1:0] S_AXI_AWLEN,\n input [2:0] S_AXI_AWSIZE,\n input [1:0] S_AXI_AWBURST,\n input S_AXI_AWVALID,\n output S_AXI_AWREADY,\n input S_AXI_WVALID,\n output S_AXI_WREADY, \n output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,\n output S_AXI_BVALID,\n input S_AXI_BREADY,\n // Signals for BMG interface\n output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,\n output S_AXI_WR_EN\n );\n\n localparam FLOP_DELAY = 100; // 100 ps\n\n localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:\n ((C_AXI_WDATA_WIDTH==16)?1:\n ((C_AXI_WDATA_WIDTH==32)?2:\n ((C_AXI_WDATA_WIDTH==64)?3:\n ((C_AXI_WDATA_WIDTH==128)?4:\n ((C_AXI_WDATA_WIDTH==256)?5:0))))));\n\n\n\n\n wire bvalid_c ;\n reg bready_timeout_c = 0;\n wire [1:0] bvalid_rd_cnt_c;\n reg bvalid_r \t= 0;\n reg [2:0] bvalid_count_r = 0;\n reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;\n reg [1:0] bvalid_wr_cnt_r = 0;\n reg [1:0] bvalid_rd_cnt_r = 0;\n wire w_last_c ;\n wire addr_en_c ;\n wire incr_addr_c ;\n wire aw_ready_r \t ;\n wire dec_alen_c ;\n reg bvalid_d1_c = 0;\n reg [7:0] awlen_cntr_r = 0;\n reg [7:0] awlen_int = 0;\n reg [1:0] awburst_int = 0;\n\n integer total_bytes = 0;\n integer wrap_boundary = 0;\n integer wrap_base_addr = 0;\n integer num_of_bytes_c = 0;\n integer num_of_bytes_r = 0;\n // Array to store BIDs\n reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;\n wire S_AXI_BVALID_axi_wr_fsm;\n\n //-------------------------------------\n //AXI WRITE FSM COMPONENT INSTANTIATION\n //-------------------------------------\n write_netlist_v8_3 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm\n (\n .S_ACLK(S_ACLK),\n .S_ARESETN(S_ARESETN),\n .S_AXI_AWVALID(S_AXI_AWVALID),\n .aw_ready_r(aw_ready_r),\n .S_AXI_WVALID(S_AXI_WVALID),\n .S_AXI_WREADY(S_AXI_WREADY),\n .S_AXI_BREADY(S_AXI_BREADY),\n .S_AXI_WR_EN(S_AXI_WR_EN),\n .w_last_c(w_last_c),\n .bready_timeout_c(bready_timeout_c),\n .addr_en_c(addr_en_c),\n .incr_addr_c(incr_addr_c),\n .bvalid_c(bvalid_c),\n .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) \n\t ); \n \n \n //Wrap Address boundary calculation \n always@(*) begin\n num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);\n total_bytes = (num_of_bytes_r)*(awlen_int+1);\n wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);\n wrap_boundary = wrap_base_addr+total_bytes;\n end\n \n //-------------------------------------------------------------------------\n // BMG address generation\n //-------------------------------------------------------------------------\n always @(posedge S_ACLK or S_ARESETN) begin\n if (S_ARESETN == 1'b1) begin\n awaddr_reg <= 0;\n\t num_of_bytes_r <= 0;\n\t awburst_int <= 0; \n\t end else begin\n if (addr_en_c == 1'b1) begin\n awaddr_reg <= #FLOP_DELAY S_AXI_AWADDR ;\n\t num_of_bytes_r <= num_of_bytes_c;\n\t awburst_int <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);\n\t end else if (incr_addr_c == 1'b1) begin\n\t if (awburst_int == 2'b10) begin\n\t\tif(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin\n\t\t awaddr_reg <= wrap_base_addr;\n\t\tend else begin\n\t\t awaddr_reg <= awaddr_reg + num_of_bytes_r;\n\t\tend\n\t end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin\n\t\tawaddr_reg <= awaddr_reg + num_of_bytes_r;\n\t end\n end\n end\n end\n \n \n assign S_AXI_AWADDR_OUT = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n\t\t\t \t awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);\n\n //-------------------------------------------------------------------------\n // AXI wlast generation\n //-------------------------------------------------------------------------\n always @(posedge S_ACLK or S_ARESETN) begin\n if (S_ARESETN == 1'b1) begin\n awlen_cntr_r <= 0;\n\t awlen_int <= 0;\n\t end else begin\n if (addr_en_c == 1'b1) begin\n\t awlen_int <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t awlen_cntr_r <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t end else if (dec_alen_c == 1'b1) begin\n awlen_cntr_r <= #FLOP_DELAY awlen_cntr_r - 1 ;\n end\n end\n end\n\n assign w_last_c = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;\n \n assign dec_alen_c = (incr_addr_c | w_last_c);\n\n //-------------------------------------------------------------------------\n // Generation of bvalid counter for outstanding transactions \n //-------------------------------------------------------------------------\n always @(posedge S_ACLK or S_ARESETN) begin\n if (S_ARESETN == 1'b1) begin\n\tbvalid_count_r <= 0;\n\tend else begin\n\t// bvalid_count_r generation\n\tif (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin\n\t bvalid_count_r <= #FLOP_DELAY bvalid_count_r ;\n\t end else if (bvalid_c == 1'b1) begin \n\t bvalid_count_r <= #FLOP_DELAY bvalid_count_r + 1 ;\n\t end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin\n\t bvalid_count_r <= #FLOP_DELAY bvalid_count_r - 1 ;\n\tend\n end\n end\n\n //-------------------------------------------------------------------------\n // Generation of bvalid when BID is used \n //-------------------------------------------------------------------------\n generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n always @(posedge S_ACLK or S_ARESETN) begin\n if (S_ARESETN == 1'b1) begin\n bvalid_r <= 0;\n bvalid_d1_c <= 0;\n\tend else begin\n // Delay the generation o bvalid_r for generation for BID \n bvalid_d1_c <= bvalid_c;\n \n //external bvalid signal generation\n if (bvalid_d1_c == 1'b1) begin\n bvalid_r <= #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n bvalid_r <= #FLOP_DELAY 0 ;\n end\n end\n end\n end\n endgenerate\n \n //-------------------------------------------------------------------------\n // Generation of bvalid when BID is not used \n //-------------------------------------------------------------------------\n generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r\n always @(posedge S_ACLK or S_ARESETN) begin\n if (S_ARESETN == 1'b1) begin\n bvalid_r <= 0;\n\tend else begin\n //external bvalid signal generation\n if (bvalid_c == 1'b1) begin\n bvalid_r <= #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n bvalid_r <= #FLOP_DELAY 0 ;\n end\n end\n end\n end\n endgenerate\n \n //-------------------------------------------------------------------------\n // Generation of Bready timeout\n //-------------------------------------------------------------------------\n always @(bvalid_count_r) begin\n \t// bready_timeout_c generation\n\tif(bvalid_count_r == C_AXI_OS_WR-1) begin\n\t bready_timeout_c <= 1'b1;\n\tend else begin\n\t bready_timeout_c <= 1'b0;\n\tend\n end\n \n //-------------------------------------------------------------------------\n // Generation of BID \n //-------------------------------------------------------------------------\n generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen\n\n always @(posedge S_ACLK or S_ARESETN) begin\n if (S_ARESETN == 1'b1) begin\n bvalid_wr_cnt_r <= 0;\n bvalid_rd_cnt_r <= 0;\n\tend else begin\n // STORE AWID IN AN ARRAY\n if(bvalid_c == 1'b1) begin\n bvalid_wr_cnt_r <= bvalid_wr_cnt_r + 1;\n end\n\t // generate BID FROM AWID ARRAY\n\t bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;\n\t S_AXI_BID <= axi_bid_array[bvalid_rd_cnt_c];\n end \n end\n \n assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;\n \n //-------------------------------------------------------------------------\n // Storing AWID for generation of BID\n //-------------------------------------------------------------------------\n always @(posedge S_ACLK or S_ARESETN) begin\n if(S_ARESETN == 1'b1) begin\n\taxi_bid_array[0] = 0;\n\taxi_bid_array[1] = 0;\n\taxi_bid_array[2] = 0;\n\taxi_bid_array[3] = 0;\n\tend else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin\n\taxi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;\n end\n end\n \n end\n endgenerate\n\n assign S_AXI_BVALID = bvalid_r;\n assign S_AXI_AWREADY = aw_ready_r;\n\n endmodule\n\nmodule blk_mem_axi_read_wrapper_beh_v8_3\n# (\n //// AXI Interface related parameters start here\n parameter C_INTERFACE_TYPE = 0,\n parameter C_AXI_TYPE = 0,\n parameter C_AXI_SLAVE_TYPE = 0,\n parameter C_MEMORY_TYPE = 0,\n parameter C_WRITE_WIDTH_A = 4,\n parameter C_WRITE_DEPTH_A = 32,\n parameter C_ADDRA_WIDTH = 12,\n parameter C_AXI_PIPELINE_STAGES = 0,\n parameter C_AXI_ARADDR_WIDTH = 12,\n parameter C_HAS_AXI_ID = 0,\n parameter C_AXI_ID_WIDTH = 4,\n parameter C_ADDRB_WIDTH = 12\n )\n (\n\n //// AXI Global Signals\n input S_ACLK,\n input S_ARESETN,\n //// AXI Full/Lite Slave Read (Read side)\n input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,\n input [7:0] S_AXI_ARLEN,\n input [2:0] S_AXI_ARSIZE,\n input [1:0] S_AXI_ARBURST,\n input S_AXI_ARVALID,\n output S_AXI_ARREADY,\n output S_AXI_RLAST, \n output S_AXI_RVALID,\n input S_AXI_RREADY,\n input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,\n output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,\n //// AXI Full/Lite Read Address Signals to BRAM\n output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,\n output S_AXI_RD_EN\n );\n\n localparam FLOP_DELAY = 100; // 100 ps\n localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:\n ((C_WRITE_WIDTH_A==16)?1:\n ((C_WRITE_WIDTH_A==32)?2:\n ((C_WRITE_WIDTH_A==64)?3:\n ((C_WRITE_WIDTH_A==128)?4:\n ((C_WRITE_WIDTH_A==256)?5:0))))));\n\n\n\n reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;\n wire addr_en_c; \n wire rd_en_c; \n wire incr_addr_c; \n wire single_trans_c; \n wire dec_alen_c; \n wire mux_sel_c; \n wire r_last_c; \n wire r_last_int_c; \n wire [C_ADDRB_WIDTH-1 : 0] araddr_out; \n\n reg [7:0] arlen_int_r=0; \n reg [7:0] arlen_cntr=8'h01; \n reg [1:0] arburst_int_c=0; \n reg [1:0] arburst_int_r=0; \n reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;\n integer num_of_bytes_c = 0;\n integer total_bytes = 0;\n integer num_of_bytes_r = 0;\n integer wrap_base_addr_r = 0;\n integer wrap_boundary_r = 0;\n\n reg [7:0] arlen_int_c=0; \n integer total_bytes_c = 0;\n integer wrap_base_addr_c = 0;\n integer wrap_boundary_c = 0;\n\n assign dec_alen_c = incr_addr_c | r_last_int_c;\n\n\n read_netlist_v8_3\n #(.C_AXI_TYPE (1),\n .C_ADDRB_WIDTH (C_ADDRB_WIDTH)) \n axi_read_fsm (\n .S_AXI_INCR_ADDR(incr_addr_c),\n .S_AXI_ADDR_EN(addr_en_c),\n .S_AXI_SINGLE_TRANS(single_trans_c),\n .S_AXI_MUX_SEL(mux_sel_c),\n .S_AXI_R_LAST(r_last_c),\n .S_AXI_R_LAST_INT(r_last_int_c),\n\n //// AXI Global Signals\n .S_ACLK(S_ACLK),\n .S_ARESETN(S_ARESETN),\n //// AXI Full/Lite Slave Read (Read side)\n .S_AXI_ARLEN(S_AXI_ARLEN),\n .S_AXI_ARVALID(S_AXI_ARVALID),\n .S_AXI_ARREADY(S_AXI_ARREADY),\n .S_AXI_RLAST(S_AXI_RLAST),\n .S_AXI_RVALID(S_AXI_RVALID),\n .S_AXI_RREADY(S_AXI_RREADY),\n //// AXI Full/Lite Read Address Signals to BRAM\n .S_AXI_RD_EN(rd_en_c)\n );\n\n always@(*) begin\n num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);\n total_bytes = (num_of_bytes_r)*(arlen_int_r+1);\n wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);\n wrap_boundary_r = wrap_base_addr_r+total_bytes;\n\n //////// combinatorial from interface\n arlen_int_c = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);\n total_bytes_c = (num_of_bytes_c)*(arlen_int_c+1);\n wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);\n wrap_boundary_c = wrap_base_addr_c+total_bytes_c;\n \n arburst_int_c = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1); \n end\n\n ////-------------------------------------------------------------------------\n //// BMG address generation\n ////-------------------------------------------------------------------------\n always @(posedge S_ACLK or S_ARESETN) begin\n if (S_ARESETN == 1'b1) begin\n araddr_reg \t<= 0;\n \tarburst_int_r <= 0;\n\tnum_of_bytes_r <= 0;\n end else begin\n if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin\n\t arburst_int_r <= arburst_int_c;\n\t num_of_bytes_r <= num_of_bytes_c;\n\t if (arburst_int_c == 2'b10) begin\n\t\t if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin\n\t\t araddr_reg <= wrap_base_addr_c;\n\t\t end else begin\n\t\t araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t\t end\n\t end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin\n\t\t araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t end\n\n end else if (addr_en_c == 1'b1) begin\n araddr_reg <= S_AXI_ARADDR;\n\t num_of_bytes_r <= num_of_bytes_c;\n\t arburst_int_r <= arburst_int_c;\n\t end else if (incr_addr_c == 1'b1) begin\n\t if (arburst_int_r == 2'b10) begin\n\t \tif(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin\n\t \t araddr_reg <= wrap_base_addr_r;\n\t \tend else begin\n\t \t araddr_reg <= araddr_reg + num_of_bytes_r;\n\t \tend\n\t end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin\n\t\t araddr_reg <= araddr_reg + num_of_bytes_r;\n\t end\n end\n end\n end\n\nassign araddr_out = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);\n \n\n ////-----------------------------------------------------------------------\n //// Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM\n ////-----------------------------------------------------------------------\n always @(posedge S_ACLK or S_ARESETN) begin\n if (S_ARESETN == 1'b1) begin\n arlen_cntr <= 8'h01;\n\t arlen_int_r <= 0;\n\tend else begin\n if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin\n\t arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n arlen_cntr <= S_AXI_ARLEN - 1'b1;\n\t end else if (addr_en_c == 1'b1) begin\n\t arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t arlen_cntr <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t end else if (dec_alen_c == 1'b1) begin\n arlen_cntr <= arlen_cntr - 1'b1 ;\n end\n\t else begin\n\t arlen_cntr <= arlen_cntr;\n\t end\n end\n end\n\n assign r_last_int_c = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;\n\n\n ////------------------------------------------------------------------------\n //// AXI FULL FSM\n //// Mux Selection of ARADDR\n //// ARADDR is driven out from the read fsm based on the mux_sel_c\n //// Based on mux_sel either ARADDR is given out or the latched ARADDR is\n //// given out to BRAM\n ////------------------------------------------------------------------------\n\tassign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;\n \n ////------------------------------------------------------------------------\n //// Assign output signals - AXI FULL FSM\n ////------------------------------------------------------------------------\n assign S_AXI_RD_EN = rd_en_c;\n\n generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n always @(posedge S_ACLK or S_ARESETN) begin\n if (S_ARESETN == 1'b1) begin\n S_AXI_RID <= 0;\n ar_id_r <= 0;\n\tend else begin\n if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin\n S_AXI_RID <= S_AXI_ARID;\n ar_id_r <= S_AXI_ARID;\n end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin\n\t ar_id_r <= S_AXI_ARID;\n end else if (rd_en_c == 1'b1) begin\n S_AXI_RID <= ar_id_r;\n end\n end\n end \n end \n endgenerate \n\nendmodule\n\nmodule blk_mem_axi_regs_fwd_v8_3\n #(parameter C_DATA_WIDTH = 8\n )(\n input ACLK,\n input ARESET,\n input S_VALID,\n output S_READY,\n input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n output M_VALID,\n input M_READY,\n output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n );\n\n reg [C_DATA_WIDTH-1:0] STORAGE_DATA;\n wire S_READY_I;\n reg M_VALID_I;\n reg [1:0] ARESET_D;\n\n //assign local signal to its output signal\n assign S_READY = S_READY_I;\n assign M_VALID = M_VALID_I;\n\n always @(posedge ACLK) begin\n\t ARESET_D <= {ARESET_D[0], ARESET};\n\tend\n \n //Save payload data whenever we have a transaction on the slave side\n always @(posedge ACLK or ARESET) begin\n if (ARESET == 1'b1) begin\n \t STORAGE_DATA <= 0;\n\tend else begin\n\t if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin\n \t STORAGE_DATA <= S_PAYLOAD_DATA;\n \t end\n \tend\n end\n\n always @(posedge ACLK) begin\n M_PAYLOAD_DATA = STORAGE_DATA;\n end\n \n //M_Valid set to high when we have a completed transfer on slave side\n //Is removed on a M_READY except if we have a new transfer on the slave side\n \n always @(posedge ACLK or ARESET_D) begin\n\tif (ARESET_D != 2'b00) begin\n \t M_VALID_I <= 1'b0;\n\tend else begin\n\t if (S_VALID == 1'b1) begin\n\t //Always set M_VALID_I when slave side is valid\n M_VALID_I <= 1'b1;\n\t end else if (M_READY == 1'b1 ) begin\n\t //Clear (or keep) when no slave side is valid but master side is ready\n\t M_VALID_I <= 1'b0;\n\t end\n\tend\n end\n\n //Slave Ready is either when Master side drives M_READY or we have space in our storage data\n assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));\n\n endmodule\n\n//*****************************************************************************\n// Output Register Stage module\n//\n// This module builds the output register stages of the memory. This module is \n// instantiated in the main memory module (blk_mem_gen_v8_3_4) which is\n// declared/implemented further down in this file.\n//*****************************************************************************\nmodule blk_mem_gen_v8_3_4_output_stage\n #(parameter C_FAMILY = \"virtex7\",\n parameter C_XDEVICEFAMILY = \"virtex7\",\n parameter C_RST_TYPE = \"SYNC\",\n parameter C_HAS_RST = 0,\n parameter C_RSTRAM = 0,\n parameter C_RST_PRIORITY = \"CE\",\n parameter C_INIT_VAL = \"0\",\n parameter C_HAS_EN = 0,\n parameter C_HAS_REGCE = 0,\n parameter C_DATA_WIDTH = 32,\n parameter C_ADDRB_WIDTH = 10,\n parameter C_HAS_MEM_OUTPUT_REGS = 0,\n parameter C_USE_SOFTECC = 0,\n parameter C_USE_ECC = 0,\n parameter NUM_STAGES = 1,\n\tparameter C_EN_ECC_PIPE = 0,\n parameter FLOP_DELAY = 100\n )\n (\n input CLK,\n input RST,\n input EN,\n input REGCE,\n input [C_DATA_WIDTH-1:0] DIN_I,\n output reg [C_DATA_WIDTH-1:0] DOUT,\n input SBITERR_IN_I,\n input DBITERR_IN_I,\n output reg SBITERR,\n output reg DBITERR,\n input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN_I,\n input ECCPIPECE, \n output reg [C_ADDRB_WIDTH-1:0] RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n //////////////////////////////////////////////////////////////////////////\n // Generic Definitions\n //////////////////////////////////////////////////////////////////////////\n // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n // options are available - \"spartan3\", \"spartan6\", \n // \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n // C_RST_TYPE : Type of reset - Synchronous or Asynchronous\n // C_HAS_RST : Determines the presence of the RST port\n // C_RSTRAM : Determines if special reset behavior is used\n // C_RST_PRIORITY : Determines the priority between CE and SR\n // C_INIT_VAL : Initialization value\n // C_HAS_EN : Determines the presence of the EN port\n // C_HAS_REGCE : Determines the presence of the REGCE port\n // C_DATA_WIDTH : Memory write/read width\n // C_ADDRB_WIDTH : Width of the ADDRB input port\n // C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output \n // of the RAM primitive\n // C_USE_SOFTECC : Determines if the Soft ECC feature is used or\n // not. Only applicable Spartan-6\n // C_USE_ECC : Determines if the ECC feature is used or\n // not. Only applicable for V5 and V6\n // NUM_STAGES : Determines the number of output stages\n // FLOP_DELAY : Constant delay for register assignments\n //////////////////////////////////////////////////////////////////////////\n // Port Definitions\n //////////////////////////////////////////////////////////////////////////\n // CLK : Clock to synchronize all read and write operations\n // RST : Reset input to reset memory outputs to a user-defined \n // reset state\n // EN : Enable all read and write operations\n // REGCE : Register Clock Enable to control each pipeline output\n // register stages\n // DIN : Data input to the Output stage.\n // DOUT : Final Data output\n // SBITERR_IN : SBITERR input signal to the Output stage.\n // SBITERR : Final SBITERR Output signal.\n // DBITERR_IN : DBITERR input signal to the Output stage.\n // DBITERR : Final DBITERR Output signal.\n // RDADDRECC_IN : RDADDRECC input signal to the Output stage.\n // RDADDRECC : Final RDADDRECC Output signal.\n //////////////////////////////////////////////////////////////////////////\n\n// Fix for CR-509792\n\n localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;\n \n // Declare the pipeline registers \n // (includes mem output reg, mux pipeline stages, and mux output reg)\n reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;\n reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;\n reg [REG_STAGES-1:0] sbiterr_regs;\n reg [REG_STAGES-1:0] dbiterr_regs;\n\n reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL;\n reg [C_DATA_WIDTH-1:0] init_val ;\n\n //*********************************************\n // Wire off optional inputs based on parameters\n //*********************************************\n wire en_i;\n wire regce_i;\n wire rst_i;\n \n // Internal signals\n reg [C_DATA_WIDTH-1:0] DIN;\n reg [C_ADDRB_WIDTH-1:0] RDADDRECC_IN;\n reg SBITERR_IN;\n reg DBITERR_IN;\n\n\n // Internal enable for output registers is tied to user EN or '1' depending\n // on parameters\n assign en_i = (C_HAS_EN==0 || EN);\n\n // Internal register enable for output registers is tied to user REGCE, EN or\n // '1' depending on parameters\n // For V4 ECC, REGCE is always 1\n // Virtex-4 ECC Not Yet Supported\n assign regce_i = ((C_HAS_REGCE==1) && REGCE) ||\n ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));\n \n //Internal SRR is tied to user RST or '0' depending on parameters\n assign rst_i = (C_HAS_RST==1) && RST;\n\n //****************************************************\n // Power on: load up the output registers and latches\n //****************************************************\n initial begin\n if (!($sscanf(init_str, \"%h\", init_val))) begin\n init_val = 0;\n end\n DOUT = init_val;\n RDADDRECC = 0;\n SBITERR = 1'b0;\n DBITERR = 1'b0;\n\tDIN = {(C_DATA_WIDTH){1'b0}};\n RDADDRECC_IN = 0;\n SBITERR_IN = 0;\n\tDBITERR_IN = 0;\n\t// This will be one wider than need, but 0 is an error\n out_regs = {(REG_STAGES+1){init_val}};\n rdaddrecc_regs = 0;\n sbiterr_regs = {(REG_STAGES+1){1'b0}};\n dbiterr_regs = {(REG_STAGES+1){1'b0}};\n end\n\n //***********************************************\n // NUM_STAGES = 0 (No output registers. RAM only)\n //***********************************************\n generate if (NUM_STAGES == 0) begin : zero_stages\n always @* begin\n DOUT = DIN;\n RDADDRECC = RDADDRECC_IN;\n SBITERR = SBITERR_IN;\n DBITERR = DBITERR_IN;\n end\n end\n endgenerate\n\n generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg\n always @* begin\n DIN = DIN_I;\n\t SBITERR_IN = SBITERR_IN_I;\n DBITERR_IN = DBITERR_IN_I;\n RDADDRECC_IN = RDADDRECC_IN_I;\n end\n end\n endgenerate\n\n generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg\n always @(posedge CLK) begin\n if(ECCPIPECE == 1) begin\n\t DIN <= #FLOP_DELAY DIN_I;\n SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;\n DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;\n RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;\n end\n\tend\n end\n endgenerate\n\n\n //***********************************************\n // NUM_STAGES = 1 \n // (Mem Output Reg only or Mux Output Reg only)\n //***********************************************\n\n // Possible valid combinations: \n // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)\n // +-----------------------------------------+\n // | C_RSTRAM_* | Reset Behavior |\n // +----------------+------------------------+\n // | 0 | Normal Behavior |\n // +----------------+------------------------+\n // | 1 | Special Behavior |\n // +----------------+------------------------+\n //\n // Normal = REGCE gates reset, as in the case of all families except S3ADSP.\n // Special = EN gates reset, as in the case of S3ADSP.\n\n generate if (NUM_STAGES == 1 && \n (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != \"spartan3adsp\" && C_XDEVICEFAMILY != \"aspartan3adsp\" )) ||\n C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))\n begin : one_stages_norm\n\n always @(posedge CLK) begin\n if (C_RST_PRIORITY == \"CE\") begin //REGCE has priority\n if (regce_i && rst_i) begin\n DOUT <= #FLOP_DELAY init_val;\n RDADDRECC <= #FLOP_DELAY 0;\n SBITERR <= #FLOP_DELAY 1'b0;\n DBITERR <= #FLOP_DELAY 1'b0;\n end else if (regce_i) begin\n DOUT <= #FLOP_DELAY DIN;\n RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n SBITERR <= #FLOP_DELAY SBITERR_IN;\n DBITERR <= #FLOP_DELAY DBITERR_IN;\n end //Output signal assignments\n end else begin //RST has priority\n if (rst_i) begin\n DOUT <= #FLOP_DELAY init_val;\n RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n SBITERR <= #FLOP_DELAY 1'b0;\n DBITERR <= #FLOP_DELAY 1'b0;\n end else if (regce_i) begin\n DOUT <= #FLOP_DELAY DIN;\n RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n SBITERR <= #FLOP_DELAY SBITERR_IN;\n DBITERR <= #FLOP_DELAY DBITERR_IN;\n end //Output signal assignments\n end //end Priority conditions\n end //end RST Type conditions\n end //end one_stages_norm generate statement\n endgenerate\n\n // Special Reset Behavior for S3ADSP\n generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY ==\"spartan3adsp\" || C_XDEVICEFAMILY ==\"aspartan3adsp\"))\n begin : one_stage_splbhv\n always @(posedge CLK) begin\n if (en_i && rst_i) begin\n DOUT <= #FLOP_DELAY init_val;\n end else if (regce_i && !rst_i) begin\n DOUT <= #FLOP_DELAY DIN;\n end //Output signal assignments\n end //end CLK\n end //end one_stage_splbhv generate statement\n endgenerate\n\n //************************************************************\n // NUM_STAGES > 1 \n // Mem Output Reg + Mux Output Reg\n // or \n // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg\n // or \n // Mux Pipeline Stages (>0) + Mux Output Reg\n //*************************************************************\n generate if (NUM_STAGES > 1) begin : multi_stage\n //Asynchronous Reset\n always @(posedge CLK) begin\n if (C_RST_PRIORITY == \"CE\") begin //REGCE has priority\n if (regce_i && rst_i) begin\n DOUT <= #FLOP_DELAY init_val;\n RDADDRECC <= #FLOP_DELAY 0;\n SBITERR <= #FLOP_DELAY 1'b0;\n DBITERR <= #FLOP_DELAY 1'b0;\n end else if (regce_i) begin\n DOUT <= #FLOP_DELAY\n out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n end //Output signal assignments\n end else begin //RST has priority\n if (rst_i) begin\n DOUT <= #FLOP_DELAY init_val;\n RDADDRECC <= #FLOP_DELAY 0;\n SBITERR <= #FLOP_DELAY 1'b0;\n DBITERR <= #FLOP_DELAY 1'b0;\n end else if (regce_i) begin\n DOUT <= #FLOP_DELAY\n out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n end //Output signal assignments\n end //end Priority conditions\n // Shift the data through the output stages\n if (en_i) begin\n out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;\n rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;\n sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;\n dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;\n end\n end //end CLK\n end //end multi_stage generate statement\n endgenerate\nendmodule\n\nmodule blk_mem_gen_v8_3_4_softecc_output_reg_stage\n #(parameter C_DATA_WIDTH = 32,\n parameter C_ADDRB_WIDTH = 10,\n parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n parameter C_USE_SOFTECC = 0,\n parameter FLOP_DELAY = 100\n )\n (\n input CLK,\n input [C_DATA_WIDTH-1:0] DIN,\n output reg [C_DATA_WIDTH-1:0] DOUT,\n input SBITERR_IN,\n input DBITERR_IN,\n output reg SBITERR,\n output reg DBITERR,\n input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,\n output reg [C_ADDRB_WIDTH-1:0] RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n //////////////////////////////////////////////////////////////////////////\n // Generic Definitions\n //////////////////////////////////////////////////////////////////////////\n // C_DATA_WIDTH : Memory write/read width\n // C_ADDRB_WIDTH : Width of the ADDRB input port\n // C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output \n // of the RAM primitive\n // C_USE_SOFTECC : Determines if the Soft ECC feature is used or\n // not. Only applicable Spartan-6\n // FLOP_DELAY : Constant delay for register assignments\n //////////////////////////////////////////////////////////////////////////\n // Port Definitions\n //////////////////////////////////////////////////////////////////////////\n // CLK : Clock to synchronize all read and write operations\n // DIN : Data input to the Output stage.\n // DOUT : Final Data output\n // SBITERR_IN : SBITERR input signal to the Output stage.\n // SBITERR : Final SBITERR Output signal.\n // DBITERR_IN : DBITERR input signal to the Output stage.\n // DBITERR : Final DBITERR Output signal.\n // RDADDRECC_IN : RDADDRECC input signal to the Output stage.\n // RDADDRECC : Final RDADDRECC Output signal.\n //////////////////////////////////////////////////////////////////////////\n\n reg [C_DATA_WIDTH-1:0] dout_i = 0;\n reg sbiterr_i = 0;\n reg dbiterr_i = 0;\n reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;\n\n //***********************************************\n // NO OUTPUT REGISTERS.\n //***********************************************\n generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage\n always @* begin\n DOUT = DIN;\n RDADDRECC = RDADDRECC_IN;\n SBITERR = SBITERR_IN;\n DBITERR = DBITERR_IN;\n end\n end\n endgenerate\n\n //***********************************************\n // WITH OUTPUT REGISTERS.\n //***********************************************\n generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage\n always @(posedge CLK) begin\n dout_i <= #FLOP_DELAY DIN;\n rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;\n sbiterr_i <= #FLOP_DELAY SBITERR_IN;\n dbiterr_i <= #FLOP_DELAY DBITERR_IN;\n end\n\n always @* begin\n DOUT = dout_i;\n RDADDRECC = rdaddrecc_i;\n SBITERR = sbiterr_i;\n DBITERR = dbiterr_i;\n end //end always\n end //end in_or_out_stage generate statement\n endgenerate\n\nendmodule\n\n\n//*****************************************************************************\n// Main Memory module\n//\n// This module is the top-level behavioral model and this implements the RAM \n//*****************************************************************************\nmodule blk_mem_gen_v8_3_4_mem_module\n #(parameter C_CORENAME = \"blk_mem_gen_v8_3_4\",\n parameter C_FAMILY = \"virtex7\",\n parameter C_XDEVICEFAMILY = \"virtex7\",\n parameter C_MEM_TYPE = 2,\n parameter C_BYTE_SIZE = 9,\n parameter C_USE_BRAM_BLOCK = 0,\n parameter C_ALGORITHM = 1,\n parameter C_PRIM_TYPE = 3,\n parameter C_LOAD_INIT_FILE = 0,\n parameter C_INIT_FILE_NAME = \"\",\n parameter C_INIT_FILE = \"\",\n parameter C_USE_DEFAULT_DATA = 0,\n parameter C_DEFAULT_DATA = \"0\",\n parameter C_RST_TYPE = \"SYNC\",\n parameter C_HAS_RSTA = 0,\n parameter C_RST_PRIORITY_A = \"CE\",\n parameter C_RSTRAM_A = 0,\n parameter C_INITA_VAL = \"0\",\n parameter C_HAS_ENA = 1,\n parameter C_HAS_REGCEA = 0,\n parameter C_USE_BYTE_WEA = 0,\n parameter C_WEA_WIDTH = 1,\n parameter C_WRITE_MODE_A = \"WRITE_FIRST\",\n parameter C_WRITE_WIDTH_A = 32,\n parameter C_READ_WIDTH_A = 32,\n parameter C_WRITE_DEPTH_A = 64,\n parameter C_READ_DEPTH_A = 64,\n parameter C_ADDRA_WIDTH = 5,\n parameter C_HAS_RSTB = 0,\n parameter C_RST_PRIORITY_B = \"CE\",\n parameter C_RSTRAM_B = 0,\n parameter C_INITB_VAL = \"\",\n parameter C_HAS_ENB = 1,\n parameter C_HAS_REGCEB = 0,\n parameter C_USE_BYTE_WEB = 0,\n parameter C_WEB_WIDTH = 1,\n parameter C_WRITE_MODE_B = \"WRITE_FIRST\",\n parameter C_WRITE_WIDTH_B = 32,\n parameter C_READ_WIDTH_B = 32,\n parameter C_WRITE_DEPTH_B = 64,\n parameter C_READ_DEPTH_B = 64,\n parameter C_ADDRB_WIDTH = 5,\n parameter C_HAS_MEM_OUTPUT_REGS_A = 0,\n parameter C_HAS_MEM_OUTPUT_REGS_B = 0,\n parameter C_HAS_MUX_OUTPUT_REGS_A = 0,\n parameter C_HAS_MUX_OUTPUT_REGS_B = 0,\n parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n parameter C_MUX_PIPELINE_STAGES = 0,\n parameter C_USE_SOFTECC = 0,\n parameter C_USE_ECC = 0,\n parameter C_HAS_INJECTERR = 0,\n parameter C_SIM_COLLISION_CHECK = \"NONE\",\n parameter C_COMMON_CLK = 1,\n parameter FLOP_DELAY = 100,\n parameter C_DISABLE_WARN_BHV_COLL = 0,\n\tparameter C_EN_ECC_PIPE = 0,\n parameter C_DISABLE_WARN_BHV_RANGE = 0\n )\n (input CLKA,\n input RSTA,\n input ENA,\n input REGCEA,\n input [C_WEA_WIDTH-1:0] WEA,\n input [C_ADDRA_WIDTH-1:0] ADDRA,\n input [C_WRITE_WIDTH_A-1:0] DINA,\n output [C_READ_WIDTH_A-1:0] DOUTA,\n input CLKB,\n input RSTB,\n input ENB,\n input REGCEB,\n input [C_WEB_WIDTH-1:0] WEB,\n input [C_ADDRB_WIDTH-1:0] ADDRB,\n input [C_WRITE_WIDTH_B-1:0] DINB,\n output [C_READ_WIDTH_B-1:0] DOUTB,\n input INJECTSBITERR,\n input INJECTDBITERR,\n input ECCPIPECE,\n input SLEEP,\n output SBITERR,\n output DBITERR,\n output [C_ADDRB_WIDTH-1:0] RDADDRECC\n );\n//******************************\n// Port and Generic Definitions\n//******************************\n //////////////////////////////////////////////////////////////////////////\n // Generic Definitions\n //////////////////////////////////////////////////////////////////////////\n // C_CORENAME : Instance name of the Block Memory Generator core\n // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n // options are available - \"spartan3\", \"spartan6\", \n // \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n // C_MEM_TYPE : Designates memory type.\n // It can be\n // 0 - Single Port Memory\n // 1 - Simple Dual Port Memory\n // 2 - True Dual Port Memory\n // 3 - Single Port Read Only Memory\n // 4 - Dual Port Read Only Memory\n // C_BYTE_SIZE : Size of a byte (8 or 9 bits)\n // C_ALGORITHM : Designates the algorithm method used\n // for constructing the memory.\n // It can be Fixed_Primitives, Minimum_Area or \n // Low_Power\n // C_PRIM_TYPE : Designates the user selected primitive used to \n // construct the memory.\n //\n // C_LOAD_INIT_FILE : Designates the use of an initialization file to\n // initialize memory contents.\n // C_INIT_FILE_NAME : Memory initialization file name.\n // C_USE_DEFAULT_DATA : Designates whether to fill remaining\n // initialization space with default data\n // C_DEFAULT_DATA : Default value of all memory locations\n // not initialized by the memory\n // initialization file.\n // C_RST_TYPE : Type of reset - Synchronous or Asynchronous\n // C_HAS_RSTA : Determines the presence of the RSTA port\n // C_RST_PRIORITY_A : Determines the priority between CE and SR for \n // Port A.\n // C_RSTRAM_A : Determines if special reset behavior is used for\n // Port A\n // C_INITA_VAL : The initialization value for Port A\n // C_HAS_ENA : Determines the presence of the ENA port\n // C_HAS_REGCEA : Determines the presence of the REGCEA port\n // C_USE_BYTE_WEA : Determines if the Byte Write is used or not.\n // C_WEA_WIDTH : The width of the WEA port\n // C_WRITE_MODE_A : Configurable write mode for Port A. It can be\n // WRITE_FIRST, READ_FIRST or NO_CHANGE.\n // C_WRITE_WIDTH_A : Memory write width for Port A.\n // C_READ_WIDTH_A : Memory read width for Port A.\n // C_WRITE_DEPTH_A : Memory write depth for Port A.\n // C_READ_DEPTH_A : Memory read depth for Port A.\n // C_ADDRA_WIDTH : Width of the ADDRA input port\n // C_HAS_RSTB : Determines the presence of the RSTB port\n // C_RST_PRIORITY_B : Determines the priority between CE and SR for \n // Port B.\n // C_RSTRAM_B : Determines if special reset behavior is used for\n // Port B\n // C_INITB_VAL : The initialization value for Port B\n // C_HAS_ENB : Determines the presence of the ENB port\n // C_HAS_REGCEB : Determines the presence of the REGCEB port\n // C_USE_BYTE_WEB : Determines if the Byte Write is used or not.\n // C_WEB_WIDTH : The width of the WEB port\n // C_WRITE_MODE_B : Configurable write mode for Port B. It can be\n // WRITE_FIRST, READ_FIRST or NO_CHANGE.\n // C_WRITE_WIDTH_B : Memory write width for Port B.\n // C_READ_WIDTH_B : Memory read width for Port B.\n // C_WRITE_DEPTH_B : Memory write depth for Port B.\n // C_READ_DEPTH_B : Memory read depth for Port B.\n // C_ADDRB_WIDTH : Width of the ADDRB input port\n // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n // of the RAM primitive for Port A.\n // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n // of the RAM primitive for Port B.\n // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n // of the MUX for Port A.\n // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n // of the MUX for Port B.\n // C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in \n // between the muxes.\n // C_USE_SOFTECC : Determines if the Soft ECC feature is used or\n // not. Only applicable Spartan-6\n // C_USE_ECC : Determines if the ECC feature is used or\n // not. Only applicable for V5 and V6\n // C_HAS_INJECTERR : Determines if the error injection pins\n // are present or not. If the ECC feature\n // is not used, this value is defaulted to\n // 0, else the following are the allowed \n // values:\n // 0 : No INJECTSBITERR or INJECTDBITERR pins\n // 1 : Only INJECTSBITERR pin exists\n // 2 : Only INJECTDBITERR pin exists\n // 3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n // C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision\n // warnings. It can be \"ALL\", \"NONE\", \n // \"Warnings_Only\" or \"Generate_X_Only\".\n // C_COMMON_CLK : Determins if the core has a single CLK input.\n // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n // warnings\n //////////////////////////////////////////////////////////////////////////\n // Port Definitions\n //////////////////////////////////////////////////////////////////////////\n // CLKA : Clock to synchronize all read and write operations of Port A.\n // RSTA : Reset input to reset memory outputs to a user-defined \n // reset state for Port A.\n // ENA : Enable all read and write operations of Port A.\n // REGCEA : Register Clock Enable to control each pipeline output\n // register stages for Port A.\n // WEA : Write Enable to enable all write operations of Port A.\n // ADDRA : Address of Port A.\n // DINA : Data input of Port A.\n // DOUTA : Data output of Port A.\n // CLKB : Clock to synchronize all read and write operations of Port B.\n // RSTB : Reset input to reset memory outputs to a user-defined \n // reset state for Port B.\n // ENB : Enable all read and write operations of Port B.\n // REGCEB : Register Clock Enable to control each pipeline output\n // register stages for Port B.\n // WEB : Write Enable to enable all write operations of Port B.\n // ADDRB : Address of Port B.\n // DINB : Data input of Port B.\n // DOUTB : Data output of Port B.\n // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n // SBITERR : Output signal indicating that a Single Bit ECC Error has been\n // detected and corrected.\n // DBITERR : Output signal indicating that a Double Bit ECC Error has been\n // detected.\n // RDADDRECC : Read Address Output signal indicating address at which an\n // ECC error has occurred.\n //////////////////////////////////////////////////////////////////////////\n\n\n// Note: C_CORENAME parameter is hard-coded to \"blk_mem_gen_v8_3_4\" and it is\n// only used by this module to print warning messages. It is neither passed \n// down from blk_mem_gen_v8_3_4_xst.v nor present in the instantiation template\n// coregen generates\n \n //***************************************************************************\n // constants for the core behavior\n //***************************************************************************\n // file handles for logging\n //--------------------------------------------------\n localparam ADDRFILE = 32'h8000_0001; //stdout for addr out of range\n localparam COLLFILE = 32'h8000_0001; //stdout for coll detection\n localparam ERRFILE = 32'h8000_0001; //stdout for file I/O errors\n\n // other constants\n //--------------------------------------------------\n localparam COLL_DELAY = 100; // 100 ps\n\n // locally derived parameters to determine memory shape\n //-----------------------------------------------------\n\n localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); \n\n localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?\n C_WRITE_WIDTH_A : C_READ_WIDTH_A;\n localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?\n C_WRITE_WIDTH_B : C_READ_WIDTH_B;\n localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?\n MIN_WIDTH_A : MIN_WIDTH_B;\n\n localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?\n C_WRITE_DEPTH_A : C_READ_DEPTH_A;\n localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?\n C_WRITE_DEPTH_B : C_READ_DEPTH_B;\n localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?\n MAX_DEPTH_A : MAX_DEPTH_B;\n\n\n // locally derived parameters to assist memory access\n //----------------------------------------------------\n // Calculate the width ratios of each port with respect to the narrowest\n // port\n localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;\n localparam READ_WIDTH_RATIO_A = C_READ_WIDTH_A/MIN_WIDTH;\n localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;\n localparam READ_WIDTH_RATIO_B = C_READ_WIDTH_B/MIN_WIDTH;\n\n // To modify the LSBs of the 'wider' data to the actual\n // address value\n //----------------------------------------------------\n localparam WRITE_ADDR_A_DIV = C_WRITE_WIDTH_A/MIN_WIDTH_A;\n localparam READ_ADDR_A_DIV = C_READ_WIDTH_A/MIN_WIDTH_A;\n localparam WRITE_ADDR_B_DIV = C_WRITE_WIDTH_B/MIN_WIDTH_B;\n localparam READ_ADDR_B_DIV = C_READ_WIDTH_B/MIN_WIDTH_B;\n\n // If byte writes aren't being used, make sure BYTE_SIZE is not\n // wider than the memory elements to avoid compilation warnings\n localparam BYTE_SIZE = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;\n\n // The memory\n reg [MIN_WIDTH-1:0] memory [0:MAX_DEPTH-1];\n reg [MIN_WIDTH-1:0] temp_mem_array [0:MAX_DEPTH-1];\n reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;\n // ECC error arrays\n reg sbiterr_arr [0:MAX_DEPTH-1];\n reg dbiterr_arr [0:MAX_DEPTH-1];\n\n reg softecc_sbiterr_arr [0:MAX_DEPTH-1];\n reg softecc_dbiterr_arr [0:MAX_DEPTH-1];\n // Memory output 'latches'\n reg [C_READ_WIDTH_A-1:0] memory_out_a;\n reg [C_READ_WIDTH_B-1:0] memory_out_b;\n\n // ECC error inputs and outputs from output_stage module:\n reg sbiterr_in;\n wire sbiterr_sdp;\n reg dbiterr_in;\n wire dbiterr_sdp;\n\n wire [C_READ_WIDTH_B-1:0] dout_i;\n wire dbiterr_i;\n wire sbiterr_i;\n wire [C_ADDRB_WIDTH-1:0] rdaddrecc_i;\n\n reg [C_ADDRB_WIDTH-1:0] rdaddrecc_in;\n wire [C_ADDRB_WIDTH-1:0] rdaddrecc_sdp;\n\n // Reset values\n reg [C_READ_WIDTH_A-1:0] inita_val;\n reg [C_READ_WIDTH_B-1:0] initb_val;\n\n // Collision detect\n reg is_collision;\n reg is_collision_a, is_collision_delay_a;\n reg is_collision_b, is_collision_delay_b;\n\n // Temporary variables for initialization\n //---------------------------------------\n integer status;\n integer initfile;\n integer meminitfile;\n // data input buffer\n reg [C_WRITE_WIDTH_A-1:0] mif_data;\n reg [C_WRITE_WIDTH_A-1:0] mem_data;\n // string values in hex\n reg [C_READ_WIDTH_A*8-1:0] inita_str = C_INITA_VAL;\n reg [C_READ_WIDTH_B*8-1:0] initb_str = C_INITB_VAL;\n reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA;\n // initialization filename\n reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME;\n reg [1023*8-1:0] mem_init_file_str = C_INIT_FILE;\n\n\n //Constants used to calculate the effective address widths for each of the \n //four ports. \n integer cnt = 1;\n integer write_addr_a_width, read_addr_a_width;\n integer write_addr_b_width, read_addr_b_width;\n\n localparam C_FAMILY_LOCALPARAM = (C_FAMILY==\"zynquplus\"?\"virtex7\":(C_FAMILY==\"kintexuplus\"?\"virtex7\":(C_FAMILY==\"virtexuplus\"?\"virtex7\":(C_FAMILY==\"virtexu\"?\"virtex7\":(C_FAMILY==\"kintexu\" ? \"virtex7\":(C_FAMILY==\"virtex7\" ? \"virtex7\" : (C_FAMILY==\"virtex7l\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7l\" ? \"virtex7\" : (C_FAMILY==\"kintex7\" ? \"virtex7\" : (C_FAMILY==\"kintex7l\" ? \"virtex7\" : (C_FAMILY==\"qkintex7\" ? \"virtex7\" : (C_FAMILY==\"qkintex7l\" ? \"virtex7\" : (C_FAMILY==\"artix7\" ? \"virtex7\" : (C_FAMILY==\"artix7l\" ? \"virtex7\" : (C_FAMILY==\"qartix7\" ? \"virtex7\" : (C_FAMILY==\"qartix7l\" ? \"virtex7\" : (C_FAMILY==\"aartix7\" ? \"virtex7\" : (C_FAMILY==\"zynq\" ? \"virtex7\" : (C_FAMILY==\"azynq\" ? \"virtex7\" : (C_FAMILY==\"qzynq\" ? \"virtex7\" : C_FAMILY)))))))))))))))))))));\n\n // Internal configuration parameters\n //---------------------------------------------\n localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);\n localparam IS_ROM = (C_MEM_TYPE==3 || C_MEM_TYPE==4);\n localparam HAS_A_WRITE = (!IS_ROM);\n localparam HAS_B_WRITE = (C_MEM_TYPE==2);\n localparam HAS_A_READ = (C_MEM_TYPE!=1);\n localparam HAS_B_READ = (!SINGLE_PORT);\n localparam HAS_B_PORT = (HAS_B_READ || HAS_B_WRITE);\n\n // Calculate the mux pipeline register stages for Port A and Port B\n //------------------------------------------------------------------\n localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?\n C_MUX_PIPELINE_STAGES : 0;\n localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?\n C_MUX_PIPELINE_STAGES : 0;\n \n // Calculate total number of register stages in the core\n // -----------------------------------------------------\n localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);\n\n localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);\n\n wire ena_i;\n wire enb_i;\n wire reseta_i;\n wire resetb_i;\n wire [C_WEA_WIDTH-1:0] wea_i;\n wire [C_WEB_WIDTH-1:0] web_i;\n wire rea_i;\n wire reb_i;\n wire rsta_outp_stage;\n wire rstb_outp_stage;\n // ECC SBITERR/DBITERR Outputs\n // The ECC Behavior is modeled by the behavioral models only for Virtex-6.\n // For Virtex-5, these outputs will be tied to 0.\n assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;\n assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;\n assign RDADDRECC = (((C_FAMILY_LOCALPARAM == \"virtex7\") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;\n\n\n // This effectively wires off optional inputs\n assign ena_i = (C_HAS_ENA==0) || ENA;\n assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;\n //assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;\n // To Fix CR855535\n assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;\n assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;\n assign rea_i = (HAS_A_READ) ? ena_i : 'b0;\n assign reb_i = (HAS_B_READ) ? enb_i : 'b0;\n\n // These signals reset the memory latches\n\n assign reseta_i = \n ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||\n (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));\n\n assign resetb_i = \n ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||\n (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));\n\n // Tasks to access the memory\n //---------------------------\n //**************\n // write_a\n //**************\n task write_a\n (input reg [C_ADDRA_WIDTH-1:0] addr,\n input reg [C_WEA_WIDTH-1:0] byte_en,\n input reg [C_WRITE_WIDTH_A-1:0] data,\n input inj_sbiterr,\n input inj_dbiterr);\n reg [C_WRITE_WIDTH_A-1:0] current_contents;\n reg [C_ADDRA_WIDTH-1:0] address;\n integer i;\n begin\n // Shift the address by the ratio\n address = (addr/WRITE_ADDR_A_DIV);\n if (address >= C_WRITE_DEPTH_A) begin\n if (!C_DISABLE_WARN_BHV_RANGE) begin\n $fdisplay(ADDRFILE,\n \"%0s WARNING: Address %0h is outside range for A Write\",\n C_CORENAME, addr);\n end\n\n // valid address\n end else begin\n\n // Combine w/ byte writes\n if (C_USE_BYTE_WEA) begin\n\n // Get the current memory contents\n if (WRITE_WIDTH_RATIO_A == 1) begin\n // Workaround for IUS 5.5 part-select issue\n current_contents = memory[address];\n end else begin\n for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n = memory[address*WRITE_WIDTH_RATIO_A + i];\n end\n end\n\n // Apply incoming bytes\n if (C_WEA_WIDTH == 1) begin\n // Workaround for IUS 5.5 part-select issue\n if (byte_en[0]) begin\n current_contents = data;\n end\n end else begin\n for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin\n if (byte_en[i]) begin\n current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n = data[BYTE_SIZE*i+:BYTE_SIZE];\n end\n end\n end\n\n // No byte-writes, overwrite the whole word\n end else begin\n current_contents = data;\n end\n\n // Insert double bit errors:\n if (C_USE_ECC == 1) begin\n if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n// Modified for Implementing CR_859399 \n current_contents[0] = !(current_contents[30]);\n current_contents[1] = !(current_contents[62]);\n \n /*current_contents[0] = !(current_contents[0]);\n current_contents[1] = !(current_contents[1]);*/\n end\n end\n \n // Insert softecc double bit errors:\n if (C_USE_SOFTECC == 1) begin\n if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];\n doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];\n doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];\n current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];\n end\n end\n \n // Write data to memory\n if (WRITE_WIDTH_RATIO_A == 1) begin\n // Workaround for IUS 5.5 part-select issue\n memory[address*WRITE_WIDTH_RATIO_A] = current_contents;\n end else begin\n for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n memory[address*WRITE_WIDTH_RATIO_A + i]\n = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n end\n end\n\n // Store the address at which error is injected:\n if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n begin\n sbiterr_arr[addr] = 1;\n end else begin\n sbiterr_arr[addr] = 0;\n end\n \n if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n dbiterr_arr[addr] = 1;\n end else begin\n dbiterr_arr[addr] = 0;\n end\n end\n\n // Store the address at which softecc error is injected:\n if (C_USE_SOFTECC == 1) begin\n if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n begin\n softecc_sbiterr_arr[addr] = 1;\n end else begin\n softecc_sbiterr_arr[addr] = 0;\n end\n \n if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n softecc_dbiterr_arr[addr] = 1;\n end else begin\n softecc_dbiterr_arr[addr] = 0;\n end\n end\n\n end\n end\n endtask\n\n //**************\n // write_b\n //**************\n task write_b\n (input reg [C_ADDRB_WIDTH-1:0] addr,\n input reg [C_WEB_WIDTH-1:0] byte_en,\n input reg [C_WRITE_WIDTH_B-1:0] data);\n reg [C_WRITE_WIDTH_B-1:0] current_contents;\n reg [C_ADDRB_WIDTH-1:0] address;\n integer i;\n begin\n // Shift the address by the ratio\n address = (addr/WRITE_ADDR_B_DIV);\n if (address >= C_WRITE_DEPTH_B) begin\n if (!C_DISABLE_WARN_BHV_RANGE) begin\n $fdisplay(ADDRFILE,\n \"%0s WARNING: Address %0h is outside range for B Write\",\n C_CORENAME, addr);\n end\n\n // valid address\n end else begin\n\n // Combine w/ byte writes\n if (C_USE_BYTE_WEB) begin\n\n // Get the current memory contents\n if (WRITE_WIDTH_RATIO_B == 1) begin\n // Workaround for IUS 5.5 part-select issue\n current_contents = memory[address];\n end else begin\n for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n = memory[address*WRITE_WIDTH_RATIO_B + i];\n end\n end\n\n // Apply incoming bytes\n if (C_WEB_WIDTH == 1) begin\n // Workaround for IUS 5.5 part-select issue\n if (byte_en[0]) begin\n current_contents = data;\n end\n end else begin\n for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin\n if (byte_en[i]) begin\n current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n = data[BYTE_SIZE*i+:BYTE_SIZE];\n end\n end\n end\n\n // No byte-writes, overwrite the whole word\n end else begin\n current_contents = data;\n end\n\n // Write data to memory\n if (WRITE_WIDTH_RATIO_B == 1) begin\n // Workaround for IUS 5.5 part-select issue\n memory[address*WRITE_WIDTH_RATIO_B] = current_contents;\n end else begin\n for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n memory[address*WRITE_WIDTH_RATIO_B + i]\n = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n end\n end\n end\n end\n endtask\n\n //**************\n // read_a\n //**************\n task read_a\n (input reg [C_ADDRA_WIDTH-1:0] addr,\n input reg reset);\n reg [C_ADDRA_WIDTH-1:0] address;\n integer i;\n begin\n\n if (reset) begin\n memory_out_a <= #FLOP_DELAY inita_val;\n end else begin\n // Shift the address by the ratio\n address = (addr/READ_ADDR_A_DIV);\n if (address >= C_READ_DEPTH_A) begin\n if (!C_DISABLE_WARN_BHV_RANGE) begin\n $fdisplay(ADDRFILE,\n \"%0s WARNING: Address %0h is outside range for A Read\",\n C_CORENAME, addr);\n end\n memory_out_a <= #FLOP_DELAY 'bX;\n // valid address\n end else begin\n if (READ_WIDTH_RATIO_A==1) begin\n memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];\n end else begin\n // Increment through the 'partial' words in the memory\n for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin\n memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]\n <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];\n end\n end //end READ_WIDTH_RATIO_A==1 loop\n\n end //end valid address loop\n end //end reset-data assignment loops\n end\n endtask\n\n //**************\n // read_b\n //**************\n task read_b\n (input reg [C_ADDRB_WIDTH-1:0] addr,\n input reg reset);\n reg [C_ADDRB_WIDTH-1:0] address;\n integer i;\n begin\n\n if (reset) begin\n memory_out_b <= #FLOP_DELAY initb_val;\n sbiterr_in <= #FLOP_DELAY 1'b0;\n dbiterr_in <= #FLOP_DELAY 1'b0;\n rdaddrecc_in <= #FLOP_DELAY 0;\n end else begin\n // Shift the address\n address = (addr/READ_ADDR_B_DIV);\n if (address >= C_READ_DEPTH_B) begin\n if (!C_DISABLE_WARN_BHV_RANGE) begin\n $fdisplay(ADDRFILE,\n \"%0s WARNING: Address %0h is outside range for B Read\",\n C_CORENAME, addr);\n end\n memory_out_b <= #FLOP_DELAY 'bX;\n sbiterr_in <= #FLOP_DELAY 1'bX;\n dbiterr_in <= #FLOP_DELAY 1'bX;\n rdaddrecc_in <= #FLOP_DELAY 'bX;\n // valid address\n end else begin\n if (READ_WIDTH_RATIO_B==1) begin\n memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];\n end else begin\n // Increment through the 'partial' words in the memory\n for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin\n memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]\n <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];\n end\n end\n\n if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n rdaddrecc_in <= #FLOP_DELAY addr;\n if (sbiterr_arr[addr] == 1) begin\n sbiterr_in <= #FLOP_DELAY 1'b1;\n end else begin\n sbiterr_in <= #FLOP_DELAY 1'b0;\n end\n\n if (dbiterr_arr[addr] == 1) begin\n dbiterr_in <= #FLOP_DELAY 1'b1;\n end else begin\n dbiterr_in <= #FLOP_DELAY 1'b0;\n end\n\n end else if (C_USE_SOFTECC == 1) begin\n rdaddrecc_in <= #FLOP_DELAY addr;\n if (softecc_sbiterr_arr[addr] == 1) begin\n sbiterr_in <= #FLOP_DELAY 1'b1;\n end else begin\n sbiterr_in <= #FLOP_DELAY 1'b0;\n end\n\n if (softecc_dbiterr_arr[addr] == 1) begin\n dbiterr_in <= #FLOP_DELAY 1'b1;\n end else begin\n dbiterr_in <= #FLOP_DELAY 1'b0;\n end\n end else begin\n rdaddrecc_in <= #FLOP_DELAY 0;\n dbiterr_in <= #FLOP_DELAY 1'b0;\n sbiterr_in <= #FLOP_DELAY 1'b0;\n end //end SOFTECC Loop\n end //end Valid address loop\n end //end reset-data assignment loops\n end\n endtask\n\n //**************\n // reset_a\n //**************\n task reset_a (input reg reset);\n begin\n if (reset) memory_out_a <= #FLOP_DELAY inita_val;\n end\n endtask\n\n //**************\n // reset_b\n //**************\n task reset_b (input reg reset);\n begin\n if (reset) memory_out_b <= #FLOP_DELAY initb_val;\n end\n endtask\n\n //**************\n // init_memory\n //**************\n task init_memory;\n integer i, j, addr_step;\n integer status;\n reg [C_WRITE_WIDTH_A-1:0] default_data;\n begin\n default_data = 0;\n\n //Display output message indicating that the behavioral model is being \n //initialized\n if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(\" Block Memory Generator module loading initial data...\");\n\n // Convert the default to hex\n if (C_USE_DEFAULT_DATA) begin\n if (default_data_str == \"\") begin\n $fdisplay(ERRFILE, \"%0s ERROR: C_DEFAULT_DATA is empty!\", C_CORENAME);\n $finish;\n end else begin\n status = $sscanf(default_data_str, \"%h\", default_data);\n if (status == 0) begin\n $fdisplay(ERRFILE, {\"%0s ERROR: Unsuccessful hexadecimal read\",\n \"from C_DEFAULT_DATA: %0s\"},\n C_CORENAME, C_DEFAULT_DATA);\n $finish;\n end\n end\n end\n\n // Step by WRITE_ADDR_A_DIV through the memory via the\n // Port A write interface to hit every location once\n addr_step = WRITE_ADDR_A_DIV;\n\n // 'write' to every location with default (or 0)\n for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);\n end\n\n // Get specialized data from the MIF file\n if (C_LOAD_INIT_FILE) begin\n if (init_file_str == \"\") begin\n $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE_NAME is empty!\",\n C_CORENAME);\n $finish;\n end else begin\n initfile = $fopen(init_file_str, \"r\");\n if (initfile == 0) begin\n $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n \"C_INIT_FILE_NAME: %0s!\"},\n C_CORENAME, init_file_str);\n $finish;\n end else begin\n // loop through the mif file, loading in the data\n for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n status = $fscanf(initfile, \"%b\", mif_data);\n if (status > 0) begin\n write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);\n end\n end\n $fclose(initfile);\n end //initfile\n end //init_file_str\n end //C_LOAD_INIT_FILE\n\n\n if (C_USE_BRAM_BLOCK) begin\n // Get specialized data from the MIF file\n if (C_INIT_FILE != \"NONE\") begin\n if (mem_init_file_str == \"\") begin\n $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE is empty!\",\n C_CORENAME);\n $finish;\n end else begin\n meminitfile = $fopen(mem_init_file_str, \"r\");\n if (meminitfile == 0) begin\n $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n \"C_INIT_FILE: %0s!\"},\n C_CORENAME, mem_init_file_str);\n $finish;\n end else begin\n // loop through the mif file, loading in the data\n $readmemh(mem_init_file_str, memory );\n for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin\n end \n $fclose(meminitfile);\n end //meminitfile\n end //mem_init_file_str\n end //C_INIT_FILE\n end //C_USE_BRAM_BLOCK\n\n //Display output message indicating that the behavioral model is done \n //initializing\n if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) \n $display(\" Block Memory Generator data initialization complete.\");\n end\n endtask\n\n //**************\n // log2roundup\n //**************\n function integer log2roundup (input integer data_value);\n integer width;\n integer cnt;\n begin\n width = 0;\n\n if (data_value > 1) begin\n for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n width = width + 1;\n end //loop\n end //if\n\n log2roundup = width;\n\n end //log2roundup\n endfunction\n\n\n //*******************\n // collision_check\n //*******************\n function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,\n input integer iswrite_a,\n input reg [C_ADDRB_WIDTH-1:0] addr_b,\n input integer iswrite_b);\n reg c_aw_bw, c_aw_br, c_ar_bw;\n integer scaled_addra_to_waddrb_width;\n integer scaled_addrb_to_waddrb_width;\n integer scaled_addra_to_waddra_width;\n integer scaled_addrb_to_waddra_width;\n integer scaled_addra_to_raddrb_width;\n integer scaled_addrb_to_raddrb_width;\n integer scaled_addra_to_raddra_width;\n integer scaled_addrb_to_raddra_width;\n\n\n\n begin\n\n c_aw_bw = 0;\n c_aw_br = 0;\n c_ar_bw = 0;\n\n //If write_addr_b_width is smaller, scale both addresses to that width for \n //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n //scale it down to write_addr_b_width. Once both are scaled to \n //write_addr_b_width, compare.\n scaled_addra_to_waddrb_width = ((addr_a)/\n 2**(C_ADDRA_WIDTH-write_addr_b_width));\n scaled_addrb_to_waddrb_width = ((addr_b)/\n 2**(C_ADDRB_WIDTH-write_addr_b_width));\n\n //If write_addr_a_width is smaller, scale both addresses to that width for \n //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n //scale it down to write_addr_a_width. Once both are scaled to \n //write_addr_a_width, compare.\n scaled_addra_to_waddra_width = ((addr_a)/\n 2**(C_ADDRA_WIDTH-write_addr_a_width));\n scaled_addrb_to_waddra_width = ((addr_b)/\n 2**(C_ADDRB_WIDTH-write_addr_a_width));\n\n //If read_addr_b_width is smaller, scale both addresses to that width for \n //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,\n //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n //scale it down to read_addr_b_width. Once both are scaled to \n //read_addr_b_width, compare.\n scaled_addra_to_raddrb_width = ((addr_a)/\n 2**(C_ADDRA_WIDTH-read_addr_b_width));\n scaled_addrb_to_raddrb_width = ((addr_b)/\n 2**(C_ADDRB_WIDTH-read_addr_b_width));\n\n //If read_addr_a_width is smaller, scale both addresses to that width for \n //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n //scale it down to read_addr_a_width. Once both are scaled to \n //read_addr_a_width, compare.\n scaled_addra_to_raddra_width = ((addr_a)/\n 2**(C_ADDRA_WIDTH-read_addr_a_width));\n scaled_addrb_to_raddra_width = ((addr_b)/\n 2**(C_ADDRB_WIDTH-read_addr_a_width));\n\n //Look for a write-write collision. In order for a write-write\n //collision to exist, both ports must have a write transaction.\n if (iswrite_a && iswrite_b) begin\n if (write_addr_a_width > write_addr_b_width) begin\n if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n c_aw_bw = 1;\n end else begin\n c_aw_bw = 0;\n end\n end else begin\n if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n c_aw_bw = 1;\n end else begin\n c_aw_bw = 0;\n end\n end //width\n end //iswrite_a and iswrite_b\n\n //If the B port is reading (which means it is enabled - so could be\n //a TX_WRITE or TX_READ), then check for a write-read collision).\n //This could happen whether or not a write-write collision exists due\n //to asymmetric write/read ports.\n if (iswrite_a) begin\n if (write_addr_a_width > read_addr_b_width) begin\n if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin\n c_aw_br = 1;\n end else begin\n c_aw_br = 0;\n end\n end else begin\n if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n c_aw_br = 1;\n end else begin\n c_aw_br = 0;\n end\n end //width\n end //iswrite_a\n\n //If the A port is reading (which means it is enabled - so could be\n // a TX_WRITE or TX_READ), then check for a write-read collision).\n //This could happen whether or not a write-write collision exists due\n // to asymmetric write/read ports.\n if (iswrite_b) begin\n if (read_addr_a_width > write_addr_b_width) begin\n if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n c_ar_bw = 1;\n end else begin\n c_ar_bw = 0;\n end\n end else begin\n if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin\n c_ar_bw = 1;\n end else begin\n c_ar_bw = 0;\n end\n end //width\n end //iswrite_b\n\n\n\n collision_check = c_aw_bw | c_aw_br | c_ar_bw;\n\n end\n endfunction\n\n //*******************************\n // power on values\n //*******************************\n initial begin\n // Load up the memory\n init_memory;\n // Load up the output registers and latches\n if ($sscanf(inita_str, \"%h\", inita_val)) begin\n memory_out_a = inita_val;\n end else begin\n memory_out_a = 0;\n end\n if ($sscanf(initb_str, \"%h\", initb_val)) begin\n memory_out_b = initb_val;\n end else begin\n memory_out_b = 0;\n end\n\n sbiterr_in = 1'b0;\n dbiterr_in = 1'b0;\n rdaddrecc_in = 0;\n\n // Determine the effective address widths for each of the 4 ports\n write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);\n read_addr_a_width = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);\n write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);\n read_addr_b_width = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);\n\n $display(\"Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.\");\n\n end\n\n //***************************************************************************\n // These are the main blocks which schedule read and write operations\n // Note that the reset priority feature at the latch stage is only supported\n // for Spartan-6. For other families, the default priority at the latch stage\n // is \"CE\"\n //***************************************************************************\n // Synchronous clocks: schedule port operations with respect to\n // both write operating modes\n generate\n if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n \"WRITE_FIRST\")) begin : com_clk_sched_wf_wf\n always @(posedge CLKA) begin\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n \n if (rea_i) read_a(ADDRA, reseta_i);\n \n //Read B\n if (reb_i) read_b(ADDRB, resetb_i);\n end\n end\n else \n if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n \"WRITE_FIRST\")) begin : com_clk_sched_rf_wf\n always @(posedge CLKA) begin\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n //Read B\n if (reb_i) read_b(ADDRB, resetb_i);\n //Read A\n if (rea_i) read_a(ADDRA, reseta_i);\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n end\n end\n else \n if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n \"READ_FIRST\")) begin : com_clk_sched_wf_rf\n always @(posedge CLKA) begin\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n //Read A\n if (rea_i) read_a(ADDRA, reseta_i);\n //Read B\n if (reb_i) read_b(ADDRB, resetb_i);\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n end\n end\n else \n if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n \"READ_FIRST\")) begin : com_clk_sched_rf_rf\n always @(posedge CLKA) begin\n //Read A\n if (rea_i) read_a(ADDRA, reseta_i);\n //Read B\n if (reb_i) read_b(ADDRB, resetb_i);\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n end\n end\n else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n \"NO_CHANGE\")) begin : com_clk_sched_wf_nc\n always @(posedge CLKA) begin\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n //Read A\n if (rea_i) read_a(ADDRA, reseta_i);\n //Read B\n if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n end\n end\n else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"READ_FIRST\") && (C_WRITE_MODE_B ==\n \"NO_CHANGE\")) begin : com_clk_sched_rf_nc\n always @(posedge CLKA) begin\n //Read A\n if (rea_i) read_a(ADDRA, reseta_i);\n //Read B\n if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n end\n end\n else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n \"WRITE_FIRST\")) begin : com_clk_sched_nc_wf\n always @(posedge CLKA) begin\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n //Read A\n if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n //Read B\n if (reb_i) read_b(ADDRB, resetb_i);\n end\n end\n else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B == \n \"READ_FIRST\")) begin : com_clk_sched_nc_rf\n always @(posedge CLKA) begin\n //Read B\n if (reb_i) read_b(ADDRB, resetb_i);\n //Read A\n if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n end\n end\n else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n \"NO_CHANGE\")) begin : com_clk_sched_nc_nc\n always @(posedge CLKA) begin\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n //Read A\n if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n //Read B\n if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n end\n end\n else if(C_COMMON_CLK) begin: com_clk_sched_default\n always @(posedge CLKA) begin\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n //Read A\n if (rea_i) read_a(ADDRA, reseta_i);\n //Read B\n if (reb_i) read_b(ADDRB, resetb_i);\n end\n end\n endgenerate\n\n // Asynchronous clocks: port operation is independent\n generate\n if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"WRITE_FIRST\")) begin : async_clk_sched_clka_wf\n always @(posedge CLKA) begin\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n //Read A\n if (rea_i) read_a(ADDRA, reseta_i);\n end\n end\n else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"READ_FIRST\")) begin : async_clk_sched_clka_rf\n always @(posedge CLKA) begin\n //Read A\n if (rea_i) read_a(ADDRA, reseta_i);\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n end\n end\n else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"NO_CHANGE\")) begin : async_clk_sched_clka_nc\n always @(posedge CLKA) begin\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n //Read A\n if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n end\n end\n endgenerate\n\n generate \n if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"WRITE_FIRST\")) begin: async_clk_sched_clkb_wf\n always @(posedge CLKB) begin\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n //Read B\n if (reb_i) read_b(ADDRB, resetb_i);\n end\n end\n else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"READ_FIRST\")) begin: async_clk_sched_clkb_rf\n always @(posedge CLKB) begin\n //Read B\n if (reb_i) read_b(ADDRB, resetb_i);\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n end\n end\n else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"NO_CHANGE\")) begin: async_clk_sched_clkb_nc\n always @(posedge CLKB) begin\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n //Read B\n if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n end\n end\n endgenerate\n\n \n //***************************************************************\n // Instantiate the variable depth output register stage module\n //***************************************************************\n // Port A\n \n assign rsta_outp_stage = RSTA & (~SLEEP);\n\n blk_mem_gen_v8_3_4_output_stage\n #(.C_FAMILY (C_FAMILY),\n .C_XDEVICEFAMILY (C_XDEVICEFAMILY),\n .C_RST_TYPE (\"SYNC\"),\n .C_HAS_RST (C_HAS_RSTA),\n .C_RSTRAM (C_RSTRAM_A),\n .C_RST_PRIORITY (C_RST_PRIORITY_A),\n .C_INIT_VAL (C_INITA_VAL),\n .C_HAS_EN (C_HAS_ENA),\n .C_HAS_REGCE (C_HAS_REGCEA),\n .C_DATA_WIDTH (C_READ_WIDTH_A),\n .C_ADDRB_WIDTH (C_ADDRB_WIDTH),\n .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A),\n .C_USE_SOFTECC (C_USE_SOFTECC),\n .C_USE_ECC (C_USE_ECC),\n .NUM_STAGES (NUM_OUTPUT_STAGES_A),\n\t .C_EN_ECC_PIPE (0),\n .FLOP_DELAY (FLOP_DELAY))\n reg_a\n (.CLK (CLKA),\n .RST (rsta_outp_stage),//(RSTA),\n .EN (ENA),\n .REGCE (REGCEA),\n .DIN_I (memory_out_a),\n .DOUT (DOUTA),\n .SBITERR_IN_I (1'b0),\n .DBITERR_IN_I (1'b0),\n .SBITERR (),\n .DBITERR (),\n .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),\n\t\t .ECCPIPECE (1'b0),\n .RDADDRECC ()\n );\n\n assign rstb_outp_stage = RSTB & (~SLEEP);\n\n // Port B \n blk_mem_gen_v8_3_4_output_stage\n #(.C_FAMILY (C_FAMILY),\n .C_XDEVICEFAMILY (C_XDEVICEFAMILY),\n .C_RST_TYPE (\"SYNC\"),\n .C_HAS_RST (C_HAS_RSTB),\n .C_RSTRAM (C_RSTRAM_B),\n .C_RST_PRIORITY (C_RST_PRIORITY_B),\n .C_INIT_VAL (C_INITB_VAL),\n .C_HAS_EN (C_HAS_ENB),\n .C_HAS_REGCE (C_HAS_REGCEB),\n .C_DATA_WIDTH (C_READ_WIDTH_B),\n .C_ADDRB_WIDTH (C_ADDRB_WIDTH),\n .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B),\n .C_USE_SOFTECC (C_USE_SOFTECC),\n .C_USE_ECC (C_USE_ECC),\n .NUM_STAGES (NUM_OUTPUT_STAGES_B),\n .C_EN_ECC_PIPE (C_EN_ECC_PIPE),\n .FLOP_DELAY (FLOP_DELAY))\n reg_b\n (.CLK (CLKB),\n .RST (rstb_outp_stage),//(RSTB),\n .EN (ENB),\n .REGCE (REGCEB),\n .DIN_I (memory_out_b),\n .DOUT (dout_i),\n .SBITERR_IN_I (sbiterr_in),\n .DBITERR_IN_I (dbiterr_in),\n .SBITERR (sbiterr_i),\n .DBITERR (dbiterr_i),\n .RDADDRECC_IN_I (rdaddrecc_in),\n .ECCPIPECE (ECCPIPECE),\n .RDADDRECC (rdaddrecc_i)\n );\n\n //***************************************************************\n // Instantiate the Input and Output register stages\n //***************************************************************\nblk_mem_gen_v8_3_4_softecc_output_reg_stage\n #(.C_DATA_WIDTH (C_READ_WIDTH_B),\n .C_ADDRB_WIDTH (C_ADDRB_WIDTH),\n .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),\n .C_USE_SOFTECC (C_USE_SOFTECC),\n .FLOP_DELAY (FLOP_DELAY))\n has_softecc_output_reg_stage\n (.CLK (CLKB),\n .DIN (dout_i),\n .DOUT (DOUTB),\n .SBITERR_IN (sbiterr_i),\n .DBITERR_IN (dbiterr_i),\n .SBITERR (sbiterr_sdp),\n .DBITERR (dbiterr_sdp),\n .RDADDRECC_IN (rdaddrecc_i),\n .RDADDRECC (rdaddrecc_sdp)\n);\n\n //****************************************************\n // Synchronous collision checks\n //****************************************************\n// CR 780544 : To make verilog model's collison warnings in consistant with\n// vhdl model, the non-blocking assignments are replaced with blocking \n// assignments.\n generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll\n always @(posedge CLKA) begin\n // Possible collision if both are enabled and the addresses match\n if (ena_i && enb_i) begin\n if (wea_i || web_i) begin\n is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);\n end else begin\n is_collision = 0;\n end\n end else begin\n is_collision = 0;\n end\n\n // If the write port is in READ_FIRST mode, there is no collision\n if (C_WRITE_MODE_A==\"READ_FIRST\" && wea_i && !web_i) begin\n is_collision = 0;\n end\n if (C_WRITE_MODE_B==\"READ_FIRST\" && web_i && !wea_i) begin\n is_collision = 0;\n end\n\n // Only flag if one of the accesses is a write\n if (is_collision && (wea_i || web_i)) begin\n $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n C_CORENAME, $time);\n $fwrite(COLLFILE, \"A %0s address: %0h, B %0s address: %0h\\n\",\n wea_i ? \"write\" : \"read\", ADDRA,\n web_i ? \"write\" : \"read\", ADDRB);\n end\n end\n\n //****************************************************\n // Asynchronous collision checks\n //****************************************************\n end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll\n\n // Delay A and B addresses in order to mimic setup/hold times\n wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA;\n wire [0:0] #COLL_DELAY wea_delay = wea_i;\n wire #COLL_DELAY ena_delay = ena_i;\n wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB;\n wire [0:0] #COLL_DELAY web_delay = web_i;\n wire #COLL_DELAY enb_delay = enb_i;\n\n // Do the checks w/rt A\n always @(posedge CLKA) begin\n // Possible collision if both are enabled and the addresses match\n if (ena_i && enb_i) begin\n if (wea_i || web_i) begin\n is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);\n end else begin\n is_collision_a = 0;\n end\n end else begin\n is_collision_a = 0;\n end\n\n if (ena_i && enb_delay) begin\n if(wea_i || web_delay) begin\n is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,\n web_delay);\n end else begin\n is_collision_delay_a = 0;\n end\n end else begin\n is_collision_delay_a = 0;\n end\n\n // Only flag if B access is a write\n if (is_collision_a && web_i) begin\n $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n C_CORENAME, $time);\n $fwrite(COLLFILE, \"A %0s address: %0h, B write address: %0h\\n\",\n wea_i ? \"write\" : \"read\", ADDRA, ADDRB);\n\n end else if (is_collision_delay_a && web_delay) begin\n $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n C_CORENAME, $time);\n $fwrite(COLLFILE, \"A %0s address: %0h, B write address: %0h\\n\",\n wea_i ? \"write\" : \"read\", ADDRA, addrb_delay);\n end\n\n end\n\n // Do the checks w/rt B\n always @(posedge CLKB) begin\n\n // Possible collision if both are enabled and the addresses match\n if (ena_i && enb_i) begin\n if (wea_i || web_i) begin\n is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);\n end else begin\n is_collision_b = 0;\n end\n end else begin\n is_collision_b = 0;\n end\n\n if (ena_delay && enb_i) begin\n if (wea_delay || web_i) begin\n is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,\n web_i);\n end else begin\n is_collision_delay_b = 0;\n end\n end else begin\n is_collision_delay_b = 0;\n end\n\n\n // Only flag if A access is a write\n if (is_collision_b && wea_i) begin\n $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n C_CORENAME, $time);\n $fwrite(COLLFILE, \"A write address: %0h, B %s address: %0h\\n\",\n ADDRA, web_i ? \"write\" : \"read\", ADDRB);\n\n end else if (is_collision_delay_b && wea_delay) begin\n $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n C_CORENAME, $time);\n $fwrite(COLLFILE, \"A write address: %0h, B %s address: %0h\\n\",\n addra_delay, web_i ? \"write\" : \"read\", ADDRB);\n end\n\n end\n end\n endgenerate\n\nendmodule\n//*****************************************************************************\n// Top module wraps Input register and Memory module\n//\n// This module is the top-level behavioral model and this implements the memory \n// module and the input registers\n//*****************************************************************************\nmodule blk_mem_gen_v8_3_4\n #(parameter C_CORENAME = \"blk_mem_gen_v8_3_4\",\n parameter C_FAMILY = \"virtex7\",\n parameter C_XDEVICEFAMILY = \"virtex7\",\n parameter C_ELABORATION_DIR = \"\",\n parameter C_INTERFACE_TYPE = 0,\n parameter C_USE_BRAM_BLOCK = 0,\n parameter C_CTRL_ECC_ALGO = \"NONE\",\n parameter C_ENABLE_32BIT_ADDRESS = 0,\n parameter C_AXI_TYPE = 0,\n parameter C_AXI_SLAVE_TYPE = 0,\n parameter C_HAS_AXI_ID = 0,\n parameter C_AXI_ID_WIDTH = 4,\n parameter C_MEM_TYPE = 2,\n parameter C_BYTE_SIZE = 9,\n parameter C_ALGORITHM = 1,\n parameter C_PRIM_TYPE = 3,\n parameter C_LOAD_INIT_FILE = 0,\n parameter C_INIT_FILE_NAME = \"\",\n parameter C_INIT_FILE = \"\",\n parameter C_USE_DEFAULT_DATA = 0,\n parameter C_DEFAULT_DATA = \"0\",\n //parameter C_RST_TYPE = \"SYNC\",\n parameter C_HAS_RSTA = 0,\n parameter C_RST_PRIORITY_A = \"CE\",\n parameter C_RSTRAM_A = 0,\n parameter C_INITA_VAL = \"0\",\n parameter C_HAS_ENA = 1,\n parameter C_HAS_REGCEA = 0,\n parameter C_USE_BYTE_WEA = 0,\n parameter C_WEA_WIDTH = 1,\n parameter C_WRITE_MODE_A = \"WRITE_FIRST\",\n parameter C_WRITE_WIDTH_A = 32,\n parameter C_READ_WIDTH_A = 32,\n parameter C_WRITE_DEPTH_A = 64,\n parameter C_READ_DEPTH_A = 64,\n parameter C_ADDRA_WIDTH = 5,\n parameter C_HAS_RSTB = 0,\n parameter C_RST_PRIORITY_B = \"CE\",\n parameter C_RSTRAM_B = 0,\n parameter C_INITB_VAL = \"\",\n parameter C_HAS_ENB = 1,\n parameter C_HAS_REGCEB = 0,\n parameter C_USE_BYTE_WEB = 0,\n parameter C_WEB_WIDTH = 1,\n parameter C_WRITE_MODE_B = \"WRITE_FIRST\",\n parameter C_WRITE_WIDTH_B = 32,\n parameter C_READ_WIDTH_B = 32,\n parameter C_WRITE_DEPTH_B = 64,\n parameter C_READ_DEPTH_B = 64,\n parameter C_ADDRB_WIDTH = 5,\n parameter C_HAS_MEM_OUTPUT_REGS_A = 0,\n parameter C_HAS_MEM_OUTPUT_REGS_B = 0,\n parameter C_HAS_MUX_OUTPUT_REGS_A = 0,\n parameter C_HAS_MUX_OUTPUT_REGS_B = 0,\n parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n parameter C_MUX_PIPELINE_STAGES = 0,\n parameter C_USE_SOFTECC = 0,\n parameter C_USE_ECC = 0,\n\tparameter C_EN_ECC_PIPE = 0,\n parameter C_HAS_INJECTERR = 0,\n parameter C_SIM_COLLISION_CHECK = \"NONE\",\n parameter C_COMMON_CLK = 1,\n parameter C_DISABLE_WARN_BHV_COLL = 0,\n\tparameter C_EN_SLEEP_PIN = 0,\n parameter C_USE_URAM = 0,\n parameter C_EN_RDADDRA_CHG = 0,\n parameter C_EN_RDADDRB_CHG = 0,\n parameter C_EN_DEEPSLEEP_PIN = 0,\n parameter C_EN_SHUTDOWN_PIN = 0,\n\tparameter C_EN_SAFETY_CKT = 0,\n\tparameter C_COUNT_36K_BRAM = \"\",\n\tparameter C_COUNT_18K_BRAM = \"\",\n\tparameter C_EST_POWER_SUMMARY = \"\",\n\tparameter C_DISABLE_WARN_BHV_RANGE = 0\n\t\n )\n (input clka,\n input rsta,\n input ena,\n input regcea,\n input [C_WEA_WIDTH-1:0] wea,\n input [C_ADDRA_WIDTH-1:0] addra,\n input [C_WRITE_WIDTH_A-1:0] dina,\n output [C_READ_WIDTH_A-1:0] douta,\n input clkb,\n input rstb,\n input enb,\n input regceb,\n input [C_WEB_WIDTH-1:0] web,\n input [C_ADDRB_WIDTH-1:0] addrb,\n input [C_WRITE_WIDTH_B-1:0] dinb,\n output [C_READ_WIDTH_B-1:0] doutb,\n input injectsbiterr,\n input injectdbiterr,\n output sbiterr,\n output dbiterr,\n output [C_ADDRB_WIDTH-1:0] rdaddrecc,\n input eccpipece,\n input sleep,\n input deepsleep,\n input shutdown,\n output rsta_busy, \n output rstb_busy, \n //AXI BMG Input and Output Port Declarations\n \n //AXI Global Signals\n input s_aclk,\n input s_aresetn,\n \n //AXI Full/lite slave write (write side)\n input [C_AXI_ID_WIDTH-1:0] s_axi_awid,\n input [31:0] s_axi_awaddr,\n input [7:0] s_axi_awlen,\n input [2:0] s_axi_awsize,\n input [1:0] s_axi_awburst,\n input s_axi_awvalid,\n output s_axi_awready,\n input [C_WRITE_WIDTH_A-1:0] s_axi_wdata,\n input [C_WEA_WIDTH-1:0] s_axi_wstrb,\n input s_axi_wlast,\n input s_axi_wvalid,\n output s_axi_wready,\n output [C_AXI_ID_WIDTH-1:0] s_axi_bid,\n output [1:0] s_axi_bresp,\n output s_axi_bvalid,\n input s_axi_bready,\n \n //AXI Full/lite slave read (write side)\n input [C_AXI_ID_WIDTH-1:0] s_axi_arid,\n input [31:0] s_axi_araddr,\n input [7:0] s_axi_arlen,\n input [2:0] s_axi_arsize,\n input [1:0] s_axi_arburst,\n input s_axi_arvalid,\n output s_axi_arready,\n output [C_AXI_ID_WIDTH-1:0] s_axi_rid,\n output [C_WRITE_WIDTH_B-1:0] s_axi_rdata,\n output [1:0] s_axi_rresp,\n output s_axi_rlast,\n output s_axi_rvalid,\n input s_axi_rready,\n \n //AXI Full/lite sideband signals\n input s_axi_injectsbiterr,\n input s_axi_injectdbiterr,\n output s_axi_sbiterr,\n output s_axi_dbiterr,\n output [C_ADDRB_WIDTH-1:0] s_axi_rdaddrecc \n \n );\n//******************************\n// Port and Generic Definitions\n//******************************\n //////////////////////////////////////////////////////////////////////////\n // Generic Definitions\n //////////////////////////////////////////////////////////////////////////\n // C_CORENAME : Instance name of the Block Memory Generator core\n // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n // options are available - \"spartan3\", \"spartan6\", \n // \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n // C_MEM_TYPE : Designates memory type.\n // It can be\n // 0 - Single Port Memory\n // 1 - Simple Dual Port Memory\n // 2 - True Dual Port Memory\n // 3 - Single Port Read Only Memory\n // 4 - Dual Port Read Only Memory\n // C_BYTE_SIZE : Size of a byte (8 or 9 bits)\n // C_ALGORITHM : Designates the algorithm method used\n // for constructing the memory.\n // It can be Fixed_Primitives, Minimum_Area or \n // Low_Power\n // C_PRIM_TYPE : Designates the user selected primitive used to \n // construct the memory.\n //\n // C_LOAD_INIT_FILE : Designates the use of an initialization file to\n // initialize memory contents.\n // C_INIT_FILE_NAME : Memory initialization file name.\n // C_USE_DEFAULT_DATA : Designates whether to fill remaining\n // initialization space with default data\n // C_DEFAULT_DATA : Default value of all memory locations\n // not initialized by the memory\n // initialization file.\n // C_RST_TYPE : Type of reset - Synchronous or Asynchronous\n // C_HAS_RSTA : Determines the presence of the RSTA port\n // C_RST_PRIORITY_A : Determines the priority between CE and SR for \n // Port A.\n // C_RSTRAM_A : Determines if special reset behavior is used for\n // Port A\n // C_INITA_VAL : The initialization value for Port A\n // C_HAS_ENA : Determines the presence of the ENA port\n // C_HAS_REGCEA : Determines the presence of the REGCEA port\n // C_USE_BYTE_WEA : Determines if the Byte Write is used or not.\n // C_WEA_WIDTH : The width of the WEA port\n // C_WRITE_MODE_A : Configurable write mode for Port A. It can be\n // WRITE_FIRST, READ_FIRST or NO_CHANGE.\n // C_WRITE_WIDTH_A : Memory write width for Port A.\n // C_READ_WIDTH_A : Memory read width for Port A.\n // C_WRITE_DEPTH_A : Memory write depth for Port A.\n // C_READ_DEPTH_A : Memory read depth for Port A.\n // C_ADDRA_WIDTH : Width of the ADDRA input port\n // C_HAS_RSTB : Determines the presence of the RSTB port\n // C_RST_PRIORITY_B : Determines the priority between CE and SR for \n // Port B.\n // C_RSTRAM_B : Determines if special reset behavior is used for\n // Port B\n // C_INITB_VAL : The initialization value for Port B\n // C_HAS_ENB : Determines the presence of the ENB port\n // C_HAS_REGCEB : Determines the presence of the REGCEB port\n // C_USE_BYTE_WEB : Determines if the Byte Write is used or not.\n // C_WEB_WIDTH : The width of the WEB port\n // C_WRITE_MODE_B : Configurable write mode for Port B. It can be\n // WRITE_FIRST, READ_FIRST or NO_CHANGE.\n // C_WRITE_WIDTH_B : Memory write width for Port B.\n // C_READ_WIDTH_B : Memory read width for Port B.\n // C_WRITE_DEPTH_B : Memory write depth for Port B.\n // C_READ_DEPTH_B : Memory read depth for Port B.\n // C_ADDRB_WIDTH : Width of the ADDRB input port\n // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n // of the RAM primitive for Port A.\n // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n // of the RAM primitive for Port B.\n // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n // of the MUX for Port A.\n // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n // of the MUX for Port B.\n // C_HAS_SOFTECC_INPUT_REGS_A : \n // C_HAS_SOFTECC_OUTPUT_REGS_B : \n // C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in \n // between the muxes.\n // C_USE_SOFTECC : Determines if the Soft ECC feature is used or\n // not. Only applicable Spartan-6\n // C_USE_ECC : Determines if the ECC feature is used or\n // not. Only applicable for V5 and V6\n // C_HAS_INJECTERR : Determines if the error injection pins\n // are present or not. If the ECC feature\n // is not used, this value is defaulted to\n // 0, else the following are the allowed \n // values:\n // 0 : No INJECTSBITERR or INJECTDBITERR pins\n // 1 : Only INJECTSBITERR pin exists\n // 2 : Only INJECTDBITERR pin exists\n // 3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n // C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision\n // warnings. It can be \"ALL\", \"NONE\", \n // \"Warnings_Only\" or \"Generate_X_Only\".\n // C_COMMON_CLK : Determins if the core has a single CLK input.\n // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n // warnings\n //////////////////////////////////////////////////////////////////////////\n // Port Definitions\n //////////////////////////////////////////////////////////////////////////\n // CLKA : Clock to synchronize all read and write operations of Port A.\n // RSTA : Reset input to reset memory outputs to a user-defined \n // reset state for Port A.\n // ENA : Enable all read and write operations of Port A.\n // REGCEA : Register Clock Enable to control each pipeline output\n // register stages for Port A.\n // WEA : Write Enable to enable all write operations of Port A.\n // ADDRA : Address of Port A.\n // DINA : Data input of Port A.\n // DOUTA : Data output of Port A.\n // CLKB : Clock to synchronize all read and write operations of Port B.\n // RSTB : Reset input to reset memory outputs to a user-defined \n // reset state for Port B.\n // ENB : Enable all read and write operations of Port B.\n // REGCEB : Register Clock Enable to control each pipeline output\n // register stages for Port B.\n // WEB : Write Enable to enable all write operations of Port B.\n // ADDRB : Address of Port B.\n // DINB : Data input of Port B.\n // DOUTB : Data output of Port B.\n // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n // SBITERR : Output signal indicating that a Single Bit ECC Error has been\n // detected and corrected.\n // DBITERR : Output signal indicating that a Double Bit ECC Error has been\n // detected.\n // RDADDRECC : Read Address Output signal indicating address at which an\n // ECC error has occurred.\n //////////////////////////////////////////////////////////////////////////\n\n wire SBITERR;\n wire DBITERR;\n wire S_AXI_AWREADY;\n wire S_AXI_WREADY;\n wire S_AXI_BVALID;\n wire S_AXI_ARREADY;\n wire S_AXI_RLAST;\n wire S_AXI_RVALID;\n wire S_AXI_SBITERR;\n wire S_AXI_DBITERR;\n\n wire [C_WEA_WIDTH-1:0] WEA = wea;\n wire [C_ADDRA_WIDTH-1:0] ADDRA = addra;\n wire [C_WRITE_WIDTH_A-1:0] DINA = dina;\n wire [C_READ_WIDTH_A-1:0] DOUTA;\n wire [C_WEB_WIDTH-1:0] WEB = web;\n wire [C_ADDRB_WIDTH-1:0] ADDRB = addrb;\n wire [C_WRITE_WIDTH_B-1:0] DINB = dinb;\n wire [C_READ_WIDTH_B-1:0] DOUTB;\n wire [C_ADDRB_WIDTH-1:0] RDADDRECC;\n wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID = s_axi_awid;\n wire [31:0] S_AXI_AWADDR = s_axi_awaddr;\n wire [7:0] S_AXI_AWLEN = s_axi_awlen;\n wire [2:0] S_AXI_AWSIZE = s_axi_awsize;\n wire [1:0] S_AXI_AWBURST = s_axi_awburst;\n wire [C_WRITE_WIDTH_A-1:0] S_AXI_WDATA = s_axi_wdata;\n wire [C_WEA_WIDTH-1:0] S_AXI_WSTRB = s_axi_wstrb;\n wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;\n wire [1:0] S_AXI_BRESP;\n wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID = s_axi_arid;\n wire [31:0] S_AXI_ARADDR = s_axi_araddr;\n wire [7:0] S_AXI_ARLEN = s_axi_arlen;\n wire [2:0] S_AXI_ARSIZE = s_axi_arsize;\n wire [1:0] S_AXI_ARBURST = s_axi_arburst;\n wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;\n wire [C_WRITE_WIDTH_B-1:0] S_AXI_RDATA;\n wire [1:0] S_AXI_RRESP;\n wire [C_ADDRB_WIDTH-1:0] S_AXI_RDADDRECC;\n // Added to fix the simulation warning #CR731605\n wire [C_WEB_WIDTH-1:0] WEB_parameterized = 0;\n wire ECCPIPECE;\n wire SLEEP;\n reg RSTA_BUSY = 0;\n reg RSTB_BUSY = 0;\n // Declaration of internal signals to avoid warnings #927399\n wire CLKA;\n wire RSTA;\n wire ENA;\n wire REGCEA;\n wire CLKB;\n wire RSTB;\n wire ENB;\n wire REGCEB;\n wire INJECTSBITERR;\n wire INJECTDBITERR;\n wire S_ACLK;\n wire S_ARESETN;\n wire S_AXI_AWVALID;\n wire S_AXI_WLAST;\n wire S_AXI_WVALID;\n wire S_AXI_BREADY;\n wire S_AXI_ARVALID;\n wire S_AXI_RREADY;\n wire S_AXI_INJECTSBITERR;\n wire S_AXI_INJECTDBITERR;\n\n assign CLKA = clka;\n assign RSTA = rsta;\n assign ENA = ena;\n assign REGCEA = regcea;\n assign CLKB = clkb;\n assign RSTB = rstb;\n assign ENB = enb;\n assign REGCEB = regceb;\n assign INJECTSBITERR = injectsbiterr;\n assign INJECTDBITERR = injectdbiterr;\n assign ECCPIPECE = eccpipece;\n assign SLEEP = sleep;\n assign sbiterr = SBITERR;\n assign dbiterr = DBITERR;\n assign S_ACLK = s_aclk;\n assign S_ARESETN = s_aresetn;\n assign S_AXI_AWVALID = s_axi_awvalid;\n assign s_axi_awready = S_AXI_AWREADY;\n assign S_AXI_WLAST = s_axi_wlast;\n assign S_AXI_WVALID = s_axi_wvalid;\n assign s_axi_wready = S_AXI_WREADY;\n assign s_axi_bvalid = S_AXI_BVALID;\n assign S_AXI_BREADY = s_axi_bready;\n assign S_AXI_ARVALID = s_axi_arvalid;\n assign s_axi_arready = S_AXI_ARREADY;\n assign s_axi_rlast = S_AXI_RLAST;\n assign s_axi_rvalid = S_AXI_RVALID;\n assign S_AXI_RREADY = s_axi_rready;\n assign S_AXI_INJECTSBITERR = s_axi_injectsbiterr;\n assign S_AXI_INJECTDBITERR = s_axi_injectdbiterr;\n assign s_axi_sbiterr = S_AXI_SBITERR;\n assign s_axi_dbiterr = S_AXI_DBITERR;\n\n assign rsta_busy = RSTA_BUSY;\n assign rstb_busy = RSTB_BUSY;\n\n assign doutb = DOUTB;\n assign douta = DOUTA;\n assign rdaddrecc = RDADDRECC;\n assign s_axi_bid = S_AXI_BID;\n assign s_axi_bresp = S_AXI_BRESP;\n assign s_axi_rid = S_AXI_RID;\n assign s_axi_rdata = S_AXI_RDATA;\n assign s_axi_rresp = S_AXI_RRESP;\n assign s_axi_rdaddrecc = S_AXI_RDADDRECC;\n\n localparam FLOP_DELAY = 100; // 100 ps\n\n reg injectsbiterr_in;\n reg injectdbiterr_in;\n reg rsta_in;\n reg ena_in;\n reg regcea_in;\n reg [C_WEA_WIDTH-1:0] wea_in;\n reg [C_ADDRA_WIDTH-1:0] addra_in;\n reg [C_WRITE_WIDTH_A-1:0] dina_in;\n\n wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;\n wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;\n wire s_axi_wr_en_c;\n wire s_axi_rd_en_c;\n wire s_aresetn_a_c;\n wire [7:0] s_axi_arlen_c ;\n\n\n wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;\n wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;\n wire [1:0] s_axi_rresp_c;\n wire s_axi_rlast_c;\n wire s_axi_rvalid_c;\n wire s_axi_rready_c;\n wire regceb_c;\n\n localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;\n wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;\n wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;\n\n// Safety logic related signals\n\n reg [4:0] RSTA_SHFT_REG = 0;\n reg POR_A = 0; \n reg [4:0] RSTB_SHFT_REG = 0;\n reg POR_B = 0;\n \n reg ENA_dly = 0;\n reg ENA_dly_D = 0;\n\n reg ENB_dly = 0;\n reg ENB_dly_D = 0;\n\n wire RSTA_I_SAFE;\n wire RSTB_I_SAFE;\n\n wire ENA_I_SAFE;\n wire ENB_I_SAFE;\n \n reg ram_rstram_a_busy = 0;\n reg ram_rstreg_a_busy = 0;\n reg ram_rstram_b_busy = 0;\n reg ram_rstreg_b_busy = 0;\n\n reg ENA_dly_reg = 0;\n reg ENB_dly_reg = 0;\n \n reg ENA_dly_reg_D = 0;\n reg ENB_dly_reg_D = 0;\n\n //**************\n // log2roundup\n //**************\n function integer log2roundup (input integer data_value);\n integer width;\n integer cnt;\n begin\n width = 0;\n\n if (data_value > 1) begin\n for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n width = width + 1;\n end //loop\n end //if\n\n log2roundup = width;\n\n end //log2roundup\n endfunction\n\n //**************\n // log2int\n //**************\n function integer log2int (input integer data_value);\n integer width;\n integer cnt;\n begin\n width = 0;\n\t\t cnt= data_value;\n\n for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin\n width = width + 1;\n end //loop\n\n log2int = width;\n\n end //log2int\n endfunction\n\n //**************************************************************************\n // FUNCTION : divroundup\n // Returns the ceiling value of the division\n // Data_value - the quantity to be divided, dividend\n // Divisor - the value to divide the data_value by\n //**************************************************************************\n function integer divroundup (input integer data_value,input integer divisor);\n integer div;\n begin\n div = data_value/divisor;\n if ((data_value % divisor) != 0) begin\n div = div+1;\n end //if\n divroundup = div;\n end //if\n endfunction\n\n localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);\n localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);\n localparam C_AXI_ADDR_WIDTH = C_AXI_ADDR_WIDTH_MSB;\n \n //Data Width Number of LSB address bits to be discarded\n //1 to 16 1\n //17 to 32 2\n //33 to 64 3\n //65 to 128 4\n //129 to 256 5\n //257 to 512 6\n //513 to 1024 7\n // The following two constants determine this.\n\n localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));\n localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);\n localparam C_AXI_OS_WR = 2;\n\n //***********************************************\n // INPUT REGISTERS.\n //***********************************************\n generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage\n always @* begin\n injectsbiterr_in = INJECTSBITERR;\n injectdbiterr_in = INJECTDBITERR;\n rsta_in = RSTA;\n ena_in = ENA;\n regcea_in = REGCEA;\n wea_in = WEA;\n addra_in = ADDRA;\n dina_in = DINA;\n end //end always\n end //end no_softecc_input_reg_stage\n endgenerate\n\n generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage\n always @(posedge CLKA) begin\n injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;\n injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;\n rsta_in <= #FLOP_DELAY RSTA;\n ena_in <= #FLOP_DELAY ENA;\n regcea_in <= #FLOP_DELAY REGCEA;\n wea_in <= #FLOP_DELAY WEA;\n addra_in <= #FLOP_DELAY ADDRA;\n dina_in <= #FLOP_DELAY DINA;\n end //end always\n end //end input_reg_stages generate statement\n endgenerate\n\n //**************************************************************************\n // NO SAFETY LOGIC\n //**************************************************************************\n\n generate \n if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN\n assign ENA_I_SAFE = ena_in;\n assign ENB_I_SAFE = ENB;\n assign RSTA_I_SAFE = rsta_in;\n assign RSTB_I_SAFE = RSTB;\n end\n endgenerate\n\n //***************************************************************************\n // SAFETY LOGIC\n // Power-ON Reset Generation\n //***************************************************************************\n generate \n if (C_EN_SAFETY_CKT == 1) begin\n always @(posedge clka) RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;\n always @(posedge clka) POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];\n always @(posedge clkb) RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;\n always @(posedge clkb) POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; \n \n assign RSTA_I_SAFE = rsta_in | POR_A; \n assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);\n end\n endgenerate\n\n //-----------------------------------------------------------------------------\n // -- RSTA/B_BUSY Generation\n //-----------------------------------------------------------------------------\n\n generate \n if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG\n always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;\n always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;\n end\n endgenerate\n \n generate \n if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG\n always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;\n always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;\n end\n endgenerate\n\n generate \n if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY\n always @(*) RSTB_BUSY = 1'b0;\n end\n endgenerate\n\n generate \n if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_NO_REG\n always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;\n always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;\n end\n endgenerate\n \n generate \n if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG \n always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;\n always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;\n end\n endgenerate\n\n //-----------------------------------------------------------------------------\n // -- ENA/ENB Generation\n //-----------------------------------------------------------------------------\n \n generate \n if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG \n always @(posedge clka) begin\n ENA_dly <= #FLOP_DELAY RSTA_I_SAFE;\n ENA_dly_D <= #FLOP_DELAY ENA_dly;\n end\n assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);\n end\n endgenerate\n\n generate \n if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG\n always @(posedge clka) begin\n ENA_dly_reg <= #FLOP_DELAY RSTA_I_SAFE;\n ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;\n end\n assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);\n end\n endgenerate\n\n generate \n if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB\n assign ENB_I_SAFE = 1'b0;\n end\n endgenerate\n\n generate \n if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG\n always @(posedge clkb) begin : PROC_ENB_GEN\n ENB_dly <= #FLOP_DELAY RSTB_I_SAFE;\n ENB_dly_D <= #FLOP_DELAY ENB_dly;\n end\n assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);\n end\n endgenerate\n \n generate \n if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG\n always @(posedge clkb) begin : PROC_ENB_GEN\n ENB_dly_reg <= #FLOP_DELAY RSTB_I_SAFE;\n ENB_dly_reg_D <= #FLOP_DELAY ENB_dly_reg;\n end\n assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);\n end\n endgenerate\n\n generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module\nblk_mem_gen_v8_3_4_mem_module\n #(.C_CORENAME (C_CORENAME),\n .C_FAMILY (C_FAMILY),\n .C_XDEVICEFAMILY (C_XDEVICEFAMILY),\n .C_MEM_TYPE (C_MEM_TYPE),\n .C_BYTE_SIZE (C_BYTE_SIZE),\n .C_ALGORITHM (C_ALGORITHM),\n .C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),\n .C_PRIM_TYPE (C_PRIM_TYPE),\n .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),\n .C_INIT_FILE_NAME (C_INIT_FILE_NAME),\n .C_INIT_FILE (C_INIT_FILE),\n .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),\n .C_DEFAULT_DATA (C_DEFAULT_DATA),\n .C_RST_TYPE (\"SYNC\"),\n .C_HAS_RSTA (C_HAS_RSTA),\n .C_RST_PRIORITY_A (C_RST_PRIORITY_A),\n .C_RSTRAM_A (C_RSTRAM_A),\n .C_INITA_VAL (C_INITA_VAL),\n .C_HAS_ENA (C_HAS_ENA),\n .C_HAS_REGCEA (C_HAS_REGCEA),\n .C_USE_BYTE_WEA (C_USE_BYTE_WEA),\n .C_WEA_WIDTH (C_WEA_WIDTH),\n .C_WRITE_MODE_A (C_WRITE_MODE_A),\n .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),\n .C_READ_WIDTH_A (C_READ_WIDTH_A),\n .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),\n .C_READ_DEPTH_A (C_READ_DEPTH_A),\n .C_ADDRA_WIDTH (C_ADDRA_WIDTH),\n .C_HAS_RSTB (C_HAS_RSTB),\n .C_RST_PRIORITY_B (C_RST_PRIORITY_B),\n .C_RSTRAM_B (C_RSTRAM_B),\n .C_INITB_VAL (C_INITB_VAL),\n .C_HAS_ENB (C_HAS_ENB),\n .C_HAS_REGCEB (C_HAS_REGCEB),\n .C_USE_BYTE_WEB (C_USE_BYTE_WEB),\n .C_WEB_WIDTH (C_WEB_WIDTH),\n .C_WRITE_MODE_B (C_WRITE_MODE_B),\n .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),\n .C_READ_WIDTH_B (C_READ_WIDTH_B),\n .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),\n .C_READ_DEPTH_B (C_READ_DEPTH_B),\n .C_ADDRB_WIDTH (C_ADDRB_WIDTH),\n .C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),\n .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),\n .C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),\n .C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),\n .C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),\n .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),\n .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),\n .C_USE_SOFTECC (C_USE_SOFTECC),\n .C_USE_ECC (C_USE_ECC),\n .C_HAS_INJECTERR (C_HAS_INJECTERR),\n .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),\n .C_COMMON_CLK (C_COMMON_CLK),\n .FLOP_DELAY (FLOP_DELAY),\n .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE (C_EN_ECC_PIPE),\n .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))\n blk_mem_gen_v8_3_4_inst\n (.CLKA (CLKA),\n .RSTA (RSTA_I_SAFE),//(rsta_in),\n .ENA (ENA_I_SAFE),//(ena_in),\n .REGCEA (regcea_in),\n .WEA (wea_in),\n .ADDRA (addra_in),\n .DINA (dina_in),\n .DOUTA (DOUTA),\n .CLKB (CLKB),\n .RSTB (RSTB_I_SAFE),//(RSTB),\n .ENB (ENB_I_SAFE),//(ENB),\n .REGCEB (REGCEB),\n .WEB (WEB),\n .ADDRB (ADDRB),\n .DINB (DINB),\n .DOUTB (DOUTB),\n .INJECTSBITERR (injectsbiterr_in),\n .INJECTDBITERR (injectdbiterr_in),\n .ECCPIPECE (ECCPIPECE),\n .SLEEP (SLEEP),\n .SBITERR (SBITERR),\n .DBITERR (DBITERR),\n .RDADDRECC (RDADDRECC)\n );\n end\n endgenerate\n\n generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module\n\n localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);\n localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);\n\n localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);\n localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);\n // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);\n // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);\n localparam C_MEM_MAP_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_MSB;\n localparam C_MEM_MAP_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_MSB;\n\n // Data Width Number of LSB address bits to be discarded\n // 1 to 16 1\n // 17 to 32 2\n // 33 to 64 3\n // 65 to 128 4\n // 129 to 256 5\n // 257 to 512 6\n // 513 to 1024 7\n // The following two constants determine this.\n\n localparam MEM_MAP_LOWER_BOUND_VAL_A = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));\n localparam MEM_MAP_LOWER_BOUND_VAL_B = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));\n localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;\n localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;\n\n wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;\n wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;\n wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;\n \n assign msb_zero_i = 0;\n assign lsb_zero_i = 0;\n assign RDADDRECC = {msb_zero_i,rdaddrecc_i,lsb_zero_i};\n\nblk_mem_gen_v8_3_4_mem_module\n #(.C_CORENAME (C_CORENAME),\n .C_FAMILY (C_FAMILY),\n .C_XDEVICEFAMILY (C_XDEVICEFAMILY),\n .C_MEM_TYPE (C_MEM_TYPE),\n .C_BYTE_SIZE (C_BYTE_SIZE),\n .C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),\n .C_ALGORITHM (C_ALGORITHM),\n .C_PRIM_TYPE (C_PRIM_TYPE),\n .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),\n .C_INIT_FILE_NAME (C_INIT_FILE_NAME),\n .C_INIT_FILE (C_INIT_FILE),\n .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),\n .C_DEFAULT_DATA (C_DEFAULT_DATA),\n .C_RST_TYPE (\"SYNC\"),\n .C_HAS_RSTA (C_HAS_RSTA),\n .C_RST_PRIORITY_A (C_RST_PRIORITY_A),\n .C_RSTRAM_A (C_RSTRAM_A),\n .C_INITA_VAL (C_INITA_VAL),\n .C_HAS_ENA (C_HAS_ENA),\n .C_HAS_REGCEA (C_HAS_REGCEA),\n .C_USE_BYTE_WEA (C_USE_BYTE_WEA),\n .C_WEA_WIDTH (C_WEA_WIDTH),\n .C_WRITE_MODE_A (C_WRITE_MODE_A),\n .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),\n .C_READ_WIDTH_A (C_READ_WIDTH_A),\n .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),\n .C_READ_DEPTH_A (C_READ_DEPTH_A),\n .C_ADDRA_WIDTH (C_ADDRA_WIDTH_ACTUAL),\n .C_HAS_RSTB (C_HAS_RSTB),\n .C_RST_PRIORITY_B (C_RST_PRIORITY_B),\n .C_RSTRAM_B (C_RSTRAM_B),\n .C_INITB_VAL (C_INITB_VAL),\n .C_HAS_ENB (C_HAS_ENB),\n .C_HAS_REGCEB (C_HAS_REGCEB),\n .C_USE_BYTE_WEB (C_USE_BYTE_WEB),\n .C_WEB_WIDTH (C_WEB_WIDTH),\n .C_WRITE_MODE_B (C_WRITE_MODE_B),\n .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),\n .C_READ_WIDTH_B (C_READ_WIDTH_B),\n .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),\n .C_READ_DEPTH_B (C_READ_DEPTH_B),\n .C_ADDRB_WIDTH (C_ADDRB_WIDTH_ACTUAL),\n .C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),\n .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),\n .C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),\n .C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),\n .C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),\n .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),\n .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),\n .C_USE_SOFTECC (C_USE_SOFTECC),\n .C_USE_ECC (C_USE_ECC),\n .C_HAS_INJECTERR (C_HAS_INJECTERR),\n .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),\n .C_COMMON_CLK (C_COMMON_CLK),\n .FLOP_DELAY (FLOP_DELAY),\n .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE (C_EN_ECC_PIPE),\n .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))\n blk_mem_gen_v8_3_4_inst\n (.CLKA (CLKA),\n .RSTA (RSTA_I_SAFE),//(rsta_in),\n .ENA (ENA_I_SAFE),//(ena_in),\n .REGCEA (regcea_in),\n .WEA (wea_in),\n .ADDRA (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),\n .DINA (dina_in),\n .DOUTA (DOUTA),\n .CLKB (CLKB),\n .RSTB (RSTB_I_SAFE),//(RSTB),\n .ENB (ENB_I_SAFE),//(ENB),\n .REGCEB (REGCEB),\n .WEB (WEB),\n .ADDRB (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),\n .DINB (DINB),\n .DOUTB (DOUTB),\n .INJECTSBITERR (injectsbiterr_in),\n .INJECTDBITERR (injectdbiterr_in),\n .ECCPIPECE (ECCPIPECE),\n .SLEEP (SLEEP),\n .SBITERR (SBITERR),\n .DBITERR (DBITERR),\n .RDADDRECC (rdaddrecc_i)\n );\n end\n endgenerate\n\n generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs\n assign S_AXI_RDATA = s_axi_rdata_c;\n assign S_AXI_RLAST = s_axi_rlast_c;\n assign S_AXI_RVALID = s_axi_rvalid_c;\n assign S_AXI_RID = s_axi_rid_c;\n assign S_AXI_RRESP = s_axi_rresp_c;\n assign s_axi_rready_c = S_AXI_RREADY;\n end\n endgenerate\n\n generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb\n assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;\n end\n endgenerate\n\n generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb\n assign regceb_c = REGCEB;\n end\n endgenerate\n\n generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs\n assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};\n assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n assign S_AXI_RDATA = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];\n assign S_AXI_RRESP = m_axi_payload_c[2:1];\n assign S_AXI_RLAST = m_axi_payload_c[0];\n end\n endgenerate\n\n generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs\n assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};\n assign S_AXI_RDATA = s_axi_rdata_c;\n assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n assign S_AXI_RRESP = m_axi_payload_c[2:1];\n assign S_AXI_RLAST = m_axi_payload_c[0];\n end\n endgenerate\n\n generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd\n\n blk_mem_axi_regs_fwd_v8_3\n #(.C_DATA_WIDTH (C_AXI_PAYLOAD))\n axi_regs_inst (\n .ACLK (S_ACLK), \n .ARESET (s_aresetn_a_c),\n .S_VALID (s_axi_rvalid_c), \n .S_READY (s_axi_rready_c),\n .S_PAYLOAD_DATA (s_axi_payload_c),\n .M_VALID (S_AXI_RVALID),\n .M_READY (S_AXI_RREADY),\n .M_PAYLOAD_DATA (m_axi_payload_c)\n );\n end\n endgenerate\n\n generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module\n\nassign s_aresetn_a_c = !S_ARESETN;\nassign S_AXI_BRESP = 2'b00;\nassign s_axi_rresp_c = 2'b00;\nassign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;\n\n blk_mem_axi_write_wrapper_beh_v8_3\n #(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),\n .C_AXI_TYPE (C_AXI_TYPE),\n .C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),\n .C_MEMORY_TYPE (C_MEM_TYPE),\n .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),\n .C_AXI_AWADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),\n .C_HAS_AXI_ID (C_HAS_AXI_ID),\n .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),\n .C_ADDRA_WIDTH (C_ADDRA_WIDTH),\n .C_AXI_WDATA_WIDTH (C_WRITE_WIDTH_A),\n .C_AXI_OS_WR (C_AXI_OS_WR))\n axi_wr_fsm (\n // AXI Global Signals\n .S_ACLK (S_ACLK),\n .S_ARESETN (s_aresetn_a_c),\n // AXI Full/Lite Slave Write interface\n .S_AXI_AWADDR (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n .S_AXI_AWLEN (S_AXI_AWLEN),\n .S_AXI_AWID (S_AXI_AWID),\n .S_AXI_AWSIZE (S_AXI_AWSIZE),\n .S_AXI_AWBURST (S_AXI_AWBURST),\n .S_AXI_AWVALID (S_AXI_AWVALID),\n .S_AXI_AWREADY (S_AXI_AWREADY),\n .S_AXI_WVALID (S_AXI_WVALID),\n .S_AXI_WREADY (S_AXI_WREADY),\n .S_AXI_BVALID (S_AXI_BVALID),\n .S_AXI_BREADY (S_AXI_BREADY),\n .S_AXI_BID (S_AXI_BID),\n // Signals for BRAM interfac(\n .S_AXI_AWADDR_OUT (s_axi_awaddr_out_c),\n .S_AXI_WR_EN (s_axi_wr_en_c)\n );\n\n blk_mem_axi_read_wrapper_beh_v8_3\n #(.C_INTERFACE_TYPE (C_INTERFACE_TYPE), \n .C_AXI_TYPE\t\t (C_AXI_TYPE), \n .C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE), \n .C_MEMORY_TYPE (C_MEM_TYPE), \n .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), \n .C_ADDRA_WIDTH (C_ADDRA_WIDTH), \n .C_AXI_PIPELINE_STAGES (1), \n .C_AXI_ARADDR_WIDTH\t ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), \n .C_HAS_AXI_ID (C_HAS_AXI_ID), \n .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), \n .C_ADDRB_WIDTH (C_ADDRB_WIDTH)) \n axi_rd_sm(\n //AXI Global Signals\n .S_ACLK (S_ACLK), \n .S_ARESETN (s_aresetn_a_c),\n //AXI Full/Lite Read Side\n .S_AXI_ARADDR (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n .S_AXI_ARLEN (s_axi_arlen_c),\n .S_AXI_ARSIZE (S_AXI_ARSIZE),\n .S_AXI_ARBURST (S_AXI_ARBURST),\n .S_AXI_ARVALID (S_AXI_ARVALID),\n .S_AXI_ARREADY (S_AXI_ARREADY),\n .S_AXI_RLAST (s_axi_rlast_c),\n .S_AXI_RVALID (s_axi_rvalid_c),\n .S_AXI_RREADY (s_axi_rready_c),\n .S_AXI_ARID (S_AXI_ARID),\n .S_AXI_RID (s_axi_rid_c),\n //AXI Full/Lite Read FSM Outputs\n .S_AXI_ARADDR_OUT (s_axi_araddr_out_c),\n .S_AXI_RD_EN (s_axi_rd_en_c)\n );\n\nblk_mem_gen_v8_3_4_mem_module\n #(.C_CORENAME (C_CORENAME),\n .C_FAMILY (C_FAMILY),\n .C_XDEVICEFAMILY (C_XDEVICEFAMILY),\n .C_MEM_TYPE (C_MEM_TYPE),\n .C_BYTE_SIZE (C_BYTE_SIZE),\n .C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),\n .C_ALGORITHM (C_ALGORITHM),\n .C_PRIM_TYPE (C_PRIM_TYPE),\n .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),\n .C_INIT_FILE_NAME (C_INIT_FILE_NAME),\n .C_INIT_FILE (C_INIT_FILE),\n .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),\n .C_DEFAULT_DATA (C_DEFAULT_DATA),\n .C_RST_TYPE (\"SYNC\"),\n .C_HAS_RSTA (C_HAS_RSTA),\n .C_RST_PRIORITY_A (C_RST_PRIORITY_A),\n .C_RSTRAM_A (C_RSTRAM_A),\n .C_INITA_VAL (C_INITA_VAL),\n .C_HAS_ENA (1),\n .C_HAS_REGCEA (C_HAS_REGCEA),\n .C_USE_BYTE_WEA (1),\n .C_WEA_WIDTH (C_WEA_WIDTH),\n .C_WRITE_MODE_A (C_WRITE_MODE_A),\n .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),\n .C_READ_WIDTH_A (C_READ_WIDTH_A),\n .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),\n .C_READ_DEPTH_A (C_READ_DEPTH_A),\n .C_ADDRA_WIDTH (C_ADDRA_WIDTH),\n .C_HAS_RSTB (C_HAS_RSTB),\n .C_RST_PRIORITY_B (C_RST_PRIORITY_B),\n .C_RSTRAM_B (C_RSTRAM_B),\n .C_INITB_VAL (C_INITB_VAL),\n .C_HAS_ENB (1),\n .C_HAS_REGCEB (C_HAS_MEM_OUTPUT_REGS_B),\n .C_USE_BYTE_WEB (1),\n .C_WEB_WIDTH (C_WEB_WIDTH),\n .C_WRITE_MODE_B (C_WRITE_MODE_B),\n .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),\n .C_READ_WIDTH_B (C_READ_WIDTH_B),\n .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),\n .C_READ_DEPTH_B (C_READ_DEPTH_B),\n .C_ADDRB_WIDTH (C_ADDRB_WIDTH),\n .C_HAS_MEM_OUTPUT_REGS_A (0),\n .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),\n .C_HAS_MUX_OUTPUT_REGS_A (0),\n .C_HAS_MUX_OUTPUT_REGS_B (0),\n .C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),\n .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),\n .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),\n .C_USE_SOFTECC (C_USE_SOFTECC),\n .C_USE_ECC (C_USE_ECC),\n .C_HAS_INJECTERR (C_HAS_INJECTERR),\n .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),\n .C_COMMON_CLK (C_COMMON_CLK),\n .FLOP_DELAY (FLOP_DELAY),\n .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),\n\t.C_EN_ECC_PIPE (0),\n .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))\n blk_mem_gen_v8_3_4_inst\n (.CLKA (S_ACLK),\n .RSTA (s_aresetn_a_c),\n .ENA (s_axi_wr_en_c),\n .REGCEA (regcea_in),\n .WEA (S_AXI_WSTRB),\n .ADDRA (s_axi_awaddr_out_c),\n .DINA (S_AXI_WDATA),\n .DOUTA (DOUTA),\n .CLKB (S_ACLK),\n .RSTB (s_aresetn_a_c),\n .ENB (s_axi_rd_en_c),\n .REGCEB (regceb_c),\n .WEB (WEB_parameterized),\n .ADDRB (s_axi_araddr_out_c),\n .DINB (DINB),\n .DOUTB (s_axi_rdata_c),\n .INJECTSBITERR (injectsbiterr_in),\n .INJECTDBITERR (injectdbiterr_in),\n .SBITERR (SBITERR),\n .DBITERR (DBITERR),\n .ECCPIPECE (1'b0),\n .SLEEP (1'b0),\n .RDADDRECC (RDADDRECC)\n );\n end\n endgenerate\nendmodule\n\n\n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/input_line_buffer_1/synth/input_line_buffer.vhd", "content": "-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.\n-- \n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n-- \n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n-- \n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n-- \n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n-- \n-- DO NOT MODIFY THIS FILE.\n\n-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3\n-- IP Revision: 4\n\nLIBRARY ieee;\nUSE ieee.std_logic_1164.ALL;\nUSE ieee.numeric_std.ALL;\n\nLIBRARY blk_mem_gen_v8_3_4;\nUSE blk_mem_gen_v8_3_4.blk_mem_gen_v8_3_4;\n\nENTITY input_line_buffer IS\n PORT (\n clka : IN STD_LOGIC;\n ena : IN STD_LOGIC;\n wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);\n addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);\n dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);\n clkb : IN STD_LOGIC;\n addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);\n doutb : OUT STD_LOGIC_VECTOR(255 DOWNTO 0)\n );\nEND input_line_buffer;\n\nARCHITECTURE input_line_buffer_arch OF input_line_buffer IS\n ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;\n ATTRIBUTE DowngradeIPIdentifiedWarnings OF input_line_buffer_arch: ARCHITECTURE IS \"yes\";\n COMPONENT blk_mem_gen_v8_3_4 IS\n GENERIC (\n C_FAMILY : STRING;\n C_XDEVICEFAMILY : STRING;\n C_ELABORATION_DIR : STRING;\n C_INTERFACE_TYPE : INTEGER;\n C_AXI_TYPE : INTEGER;\n C_AXI_SLAVE_TYPE : INTEGER;\n C_USE_BRAM_BLOCK : INTEGER;\n C_ENABLE_32BIT_ADDRESS : INTEGER;\n C_CTRL_ECC_ALGO : STRING;\n C_HAS_AXI_ID : INTEGER;\n C_AXI_ID_WIDTH : INTEGER;\n C_MEM_TYPE : INTEGER;\n C_BYTE_SIZE : INTEGER;\n C_ALGORITHM : INTEGER;\n C_PRIM_TYPE : INTEGER;\n C_LOAD_INIT_FILE : INTEGER;\n C_INIT_FILE_NAME : STRING;\n C_INIT_FILE : STRING;\n C_USE_DEFAULT_DATA : INTEGER;\n C_DEFAULT_DATA : STRING;\n C_HAS_RSTA : INTEGER;\n C_RST_PRIORITY_A : STRING;\n C_RSTRAM_A : INTEGER;\n C_INITA_VAL : STRING;\n C_HAS_ENA : INTEGER;\n C_HAS_REGCEA : INTEGER;\n C_USE_BYTE_WEA : INTEGER;\n C_WEA_WIDTH : INTEGER;\n C_WRITE_MODE_A : STRING;\n C_WRITE_WIDTH_A : INTEGER;\n C_READ_WIDTH_A : INTEGER;\n C_WRITE_DEPTH_A : INTEGER;\n C_READ_DEPTH_A : INTEGER;\n C_ADDRA_WIDTH : INTEGER;\n C_HAS_RSTB : INTEGER;\n C_RST_PRIORITY_B : STRING;\n C_RSTRAM_B : INTEGER;\n C_INITB_VAL : STRING;\n C_HAS_ENB : INTEGER;\n C_HAS_REGCEB : INTEGER;\n C_USE_BYTE_WEB : INTEGER;\n C_WEB_WIDTH : INTEGER;\n C_WRITE_MODE_B : STRING;\n C_WRITE_WIDTH_B : INTEGER;\n C_READ_WIDTH_B : INTEGER;\n C_WRITE_DEPTH_B : INTEGER;\n C_READ_DEPTH_B : INTEGER;\n C_ADDRB_WIDTH : INTEGER;\n C_HAS_MEM_OUTPUT_REGS_A : INTEGER;\n C_HAS_MEM_OUTPUT_REGS_B : INTEGER;\n C_HAS_MUX_OUTPUT_REGS_A : INTEGER;\n C_HAS_MUX_OUTPUT_REGS_B : INTEGER;\n C_MUX_PIPELINE_STAGES : INTEGER;\n C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;\n C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;\n C_USE_SOFTECC : INTEGER;\n C_USE_ECC : INTEGER;\n C_EN_ECC_PIPE : INTEGER;\n C_HAS_INJECTERR : INTEGER;\n C_SIM_COLLISION_CHECK : STRING;\n C_COMMON_CLK : INTEGER;\n C_DISABLE_WARN_BHV_COLL : INTEGER;\n C_EN_SLEEP_PIN : INTEGER;\n C_USE_URAM : INTEGER;\n C_EN_RDADDRA_CHG : INTEGER;\n C_EN_RDADDRB_CHG : INTEGER;\n C_EN_DEEPSLEEP_PIN : INTEGER;\n C_EN_SHUTDOWN_PIN : INTEGER;\n C_EN_SAFETY_CKT : INTEGER;\n C_DISABLE_WARN_BHV_RANGE : INTEGER;\n C_COUNT_36K_BRAM : STRING;\n C_COUNT_18K_BRAM : STRING;\n C_EST_POWER_SUMMARY : STRING\n );\n PORT (\n clka : IN STD_LOGIC;\n rsta : IN STD_LOGIC;\n ena : IN STD_LOGIC;\n regcea : IN STD_LOGIC;\n wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);\n addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);\n dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);\n douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);\n clkb : IN STD_LOGIC;\n rstb : IN STD_LOGIC;\n enb : IN STD_LOGIC;\n regceb : IN STD_LOGIC;\n web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);\n addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);\n dinb : IN STD_LOGIC_VECTOR(255 DOWNTO 0);\n doutb : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);\n injectsbiterr : IN STD_LOGIC;\n injectdbiterr : IN STD_LOGIC;\n eccpipece : IN STD_LOGIC;\n sbiterr : OUT STD_LOGIC;\n dbiterr : OUT STD_LOGIC;\n rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);\n sleep : IN STD_LOGIC;\n deepsleep : IN STD_LOGIC;\n shutdown : IN STD_LOGIC;\n rsta_busy : OUT STD_LOGIC;\n rstb_busy : OUT STD_LOGIC;\n s_aclk : IN STD_LOGIC;\n s_aresetn : IN STD_LOGIC;\n s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);\n s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);\n s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);\n s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);\n s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);\n s_axi_awvalid : IN STD_LOGIC;\n s_axi_awready : OUT STD_LOGIC;\n s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);\n s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);\n s_axi_wlast : IN STD_LOGIC;\n s_axi_wvalid : IN STD_LOGIC;\n s_axi_wready : OUT STD_LOGIC;\n s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);\n s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);\n s_axi_bvalid : OUT STD_LOGIC;\n s_axi_bready : IN STD_LOGIC;\n s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);\n s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);\n s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);\n s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);\n s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);\n s_axi_arvalid : IN STD_LOGIC;\n s_axi_arready : OUT STD_LOGIC;\n s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);\n s_axi_rdata : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);\n s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);\n s_axi_rlast : OUT STD_LOGIC;\n s_axi_rvalid : OUT STD_LOGIC;\n s_axi_rready : IN STD_LOGIC;\n s_axi_injectsbiterr : IN STD_LOGIC;\n s_axi_injectdbiterr : IN STD_LOGIC;\n s_axi_sbiterr : OUT STD_LOGIC;\n s_axi_dbiterr : OUT STD_LOGIC;\n s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)\n );\n END COMPONENT blk_mem_gen_v8_3_4;\n ATTRIBUTE X_CORE_INFO : STRING;\n ATTRIBUTE X_CORE_INFO OF input_line_buffer_arch: ARCHITECTURE IS \"blk_mem_gen_v8_3_4,Vivado 2016.3\";\n ATTRIBUTE CHECK_LICENSE_TYPE : STRING;\n ATTRIBUTE CHECK_LICENSE_TYPE OF input_line_buffer_arch : ARCHITECTURE IS \"input_line_buffer,blk_mem_gen_v8_3_4,{}\";\n ATTRIBUTE CORE_GENERATION_INFO : STRING;\n ATTRIBUTE CORE_GENERATION_INFO OF input_line_buffer_arch: ARCHITECTURE IS \"input_line_buffer,blk_mem_gen_v8_3_4,{x_ipProduct=Vivado 2016.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=kintex7,C_XDEVICEFAMILY=kintex7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME\" & \n\"=no_coe_file_loaded,C_INIT_FILE=input_line_buffer.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=64,C_READ_WIDTH_A=64,C_WRITE_DEPTH_A=4096,C_READ_DEPTH_A=4096,C_ADDRA_WIDTH=12,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=256,C_REA\" & \n\"D_WIDTH_B=256,C_WRITE_DEPTH_B=1024,C_READ_DEPTH_B=1024,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_E\" & \n\"N_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=7,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 36.714252 mW}\";\n ATTRIBUTE X_INTERFACE_INFO : STRING;\n ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS \"xilinx.com:interface:bram:1.0 BRAM_PORTA CLK\";\n ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS \"xilinx.com:interface:bram:1.0 BRAM_PORTA EN\";\n ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS \"xilinx.com:interface:bram:1.0 BRAM_PORTA WE\";\n ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS \"xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR\";\n ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS \"xilinx.com:interface:bram:1.0 BRAM_PORTA DIN\";\n ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS \"xilinx.com:interface:bram:1.0 BRAM_PORTB CLK\";\n ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS \"xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR\";\n ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS \"xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT\";\nBEGIN\n U0 : blk_mem_gen_v8_3_4\n GENERIC MAP (\n C_FAMILY => \"kintex7\",\n C_XDEVICEFAMILY => \"kintex7\",\n C_ELABORATION_DIR => \"./\",\n C_INTERFACE_TYPE => 0,\n C_AXI_TYPE => 1,\n C_AXI_SLAVE_TYPE => 0,\n C_USE_BRAM_BLOCK => 0,\n C_ENABLE_32BIT_ADDRESS => 0,\n C_CTRL_ECC_ALGO => \"NONE\",\n C_HAS_AXI_ID => 0,\n C_AXI_ID_WIDTH => 4,\n C_MEM_TYPE => 1,\n C_BYTE_SIZE => 9,\n C_ALGORITHM => 1,\n C_PRIM_TYPE => 1,\n C_LOAD_INIT_FILE => 0,\n C_INIT_FILE_NAME => \"no_coe_file_loaded\",\n C_INIT_FILE => \"input_line_buffer.mem\",\n C_USE_DEFAULT_DATA => 0,\n C_DEFAULT_DATA => \"0\",\n C_HAS_RSTA => 0,\n C_RST_PRIORITY_A => \"CE\",\n C_RSTRAM_A => 0,\n C_INITA_VAL => \"0\",\n C_HAS_ENA => 1,\n C_HAS_REGCEA => 0,\n C_USE_BYTE_WEA => 0,\n C_WEA_WIDTH => 1,\n C_WRITE_MODE_A => \"NO_CHANGE\",\n C_WRITE_WIDTH_A => 64,\n C_READ_WIDTH_A => 64,\n C_WRITE_DEPTH_A => 4096,\n C_READ_DEPTH_A => 4096,\n C_ADDRA_WIDTH => 12,\n C_HAS_RSTB => 0,\n C_RST_PRIORITY_B => \"CE\",\n C_RSTRAM_B => 0,\n C_INITB_VAL => \"0\",\n C_HAS_ENB => 0,\n C_HAS_REGCEB => 0,\n C_USE_BYTE_WEB => 0,\n C_WEB_WIDTH => 1,\n C_WRITE_MODE_B => \"WRITE_FIRST\",\n C_WRITE_WIDTH_B => 256,\n C_READ_WIDTH_B => 256,\n C_WRITE_DEPTH_B => 1024,\n C_READ_DEPTH_B => 1024,\n C_ADDRB_WIDTH => 10,\n C_HAS_MEM_OUTPUT_REGS_A => 0,\n C_HAS_MEM_OUTPUT_REGS_B => 0,\n C_HAS_MUX_OUTPUT_REGS_A => 0,\n C_HAS_MUX_OUTPUT_REGS_B => 0,\n C_MUX_PIPELINE_STAGES => 0,\n C_HAS_SOFTECC_INPUT_REGS_A => 0,\n C_HAS_SOFTECC_OUTPUT_REGS_B => 0,\n C_USE_SOFTECC => 0,\n C_USE_ECC => 0,\n C_EN_ECC_PIPE => 0,\n C_HAS_INJECTERR => 0,\n C_SIM_COLLISION_CHECK => \"ALL\",\n C_COMMON_CLK => 0,\n C_DISABLE_WARN_BHV_COLL => 0,\n C_EN_SLEEP_PIN => 0,\n C_USE_URAM => 0,\n C_EN_RDADDRA_CHG => 0,\n C_EN_RDADDRB_CHG => 0,\n C_EN_DEEPSLEEP_PIN => 0,\n C_EN_SHUTDOWN_PIN => 0,\n C_EN_SAFETY_CKT => 0,\n C_DISABLE_WARN_BHV_RANGE => 0,\n C_COUNT_36K_BRAM => \"7\",\n C_COUNT_18K_BRAM => \"1\",\n C_EST_POWER_SUMMARY => \"Estimated Power for IP : 36.714252 mW\"\n )\n PORT MAP (\n clka => clka,\n rsta => '0',\n ena => ena,\n regcea => '0',\n wea => wea,\n addra => addra,\n dina => dina,\n clkb => clkb,\n rstb => '0',\n enb => '0',\n regceb => '0',\n web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),\n addrb => addrb,\n dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 256)),\n doutb => doutb,\n injectsbiterr => '0',\n injectdbiterr => '0',\n eccpipece => '0',\n sleep => '0',\n deepsleep => '0',\n shutdown => '0',\n s_aclk => '0',\n s_aresetn => '0',\n s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),\n s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),\n s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),\n s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),\n s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),\n s_axi_awvalid => '0',\n s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),\n s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),\n s_axi_wlast => '0',\n s_axi_wvalid => '0',\n s_axi_bready => '0',\n s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),\n s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),\n s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),\n s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),\n s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),\n s_axi_arvalid => '0',\n s_axi_rready => '0',\n s_axi_injectsbiterr => '0',\n s_axi_injectdbiterr => '0'\n );\nEND input_line_buffer_arch;\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/output_line_buffer_1/misc/blk_mem_gen_v8_3.vhd", "content": "library ieee;\nuse ieee.std_logic_1164.all;\n\nentity blk_mem_gen_v8_3_4 is\n generic (\n C_FAMILY : string := \"virtex7\";\n C_XDEVICEFAMILY : string := \"virtex7\";\n C_ELABORATION_DIR : string := \"\";\n C_INTERFACE_TYPE : integer := 0;\n C_AXI_TYPE : integer := 1;\n C_AXI_SLAVE_TYPE : integer := 0;\n C_USE_BRAM_BLOCK : integer := 0;\n C_ENABLE_32BIT_ADDRESS : integer := 0;\n C_CTRL_ECC_ALGO : string := \"ECCHSIAO32-7\";\n C_HAS_AXI_ID : integer := 0;\n C_AXI_ID_WIDTH : integer := 4;\n C_MEM_TYPE : integer := 2;\n C_BYTE_SIZE : integer := 9;\n C_ALGORITHM : integer := 0;\n C_PRIM_TYPE : integer := 3;\n C_LOAD_INIT_FILE : integer := 0;\n C_INIT_FILE_NAME : string := \"no_coe_file_loaded\";\n C_INIT_FILE : string := \"no_mem_file_loaded\";\n C_USE_DEFAULT_DATA : integer := 0;\n C_DEFAULT_DATA : string := \"0\";\n C_HAS_RSTA : integer := 0;\n C_RST_PRIORITY_A : string := \"ce\";\n C_RSTRAM_A : integer := 0;\n C_INITA_VAL : string := \"0\";\n C_HAS_ENA : integer := 1;\n C_HAS_REGCEA : integer := 0;\n C_USE_BYTE_WEA : integer := 0;\n C_WEA_WIDTH : integer := 1;\n C_WRITE_MODE_A : string := \"WRITE_FIRST\";\n C_WRITE_WIDTH_A : integer := 9;\n C_READ_WIDTH_A : integer := 9;\n C_WRITE_DEPTH_A : integer := 2048;\n C_READ_DEPTH_A : integer := 2048;\n C_ADDRA_WIDTH : integer := 11;\n C_HAS_RSTB : integer := 0;\n C_RST_PRIORITY_B : string := \"ce\";\n C_RSTRAM_B : integer := 0;\n C_INITB_VAL : string := \"0\";\n C_HAS_ENB : integer := 1;\n C_HAS_REGCEB : integer := 0;\n C_USE_BYTE_WEB : integer := 0;\n C_WEB_WIDTH : integer := 1;\n C_WRITE_MODE_B : string := \"WRITE_FIRST\";\n C_WRITE_WIDTH_B : integer := 9;\n C_READ_WIDTH_B : integer := 9;\n C_WRITE_DEPTH_B : integer := 2048;\n C_READ_DEPTH_B : integer := 2048;\n C_ADDRB_WIDTH : integer := 11;\n C_HAS_MEM_OUTPUT_REGS_A : integer := 0;\n C_HAS_MEM_OUTPUT_REGS_B : integer := 0;\n C_HAS_MUX_OUTPUT_REGS_A : integer := 0;\n C_HAS_MUX_OUTPUT_REGS_B : integer := 0;\n C_MUX_PIPELINE_STAGES : integer := 0;\n C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;\n C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;\n C_USE_SOFTECC : integer := 0;\n C_USE_ECC : integer := 0;\n C_EN_ECC_PIPE : integer := 0;\n C_HAS_INJECTERR : integer := 0;\n C_SIM_COLLISION_CHECK : string := \"none\";\n C_COMMON_CLK : integer := 0;\n C_DISABLE_WARN_BHV_COLL : integer := 0;\n C_EN_SLEEP_PIN : integer := 0;\n C_USE_URAM : integer := 0;\n C_EN_RDADDRA_CHG : integer := 0;\n C_EN_RDADDRB_CHG : integer := 0;\n C_EN_DEEPSLEEP_PIN : integer := 0;\n C_EN_SHUTDOWN_PIN : integer := 0;\n C_EN_SAFETY_CKT : integer := 0;\n C_DISABLE_WARN_BHV_RANGE : integer := 0;\n C_COUNT_36K_BRAM : string := \"\";\n C_COUNT_18K_BRAM : string := \"\";\n C_EST_POWER_SUMMARY : string := \"\"\n );\n port (\n clka : in std_logic := '0';\n rsta : in std_logic := '0';\n ena : in std_logic := '0';\n regcea : in std_logic := '0';\n wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');\n addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');\n dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');\n douta : out std_logic_vector(c_read_width_a - 1 downto 0);\n clkb : in std_logic := '0';\n rstb : in std_logic := '0';\n enb : in std_logic := '0';\n regceb : in std_logic := '0';\n web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');\n addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');\n dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');\n doutb : out std_logic_vector(c_read_width_b - 1 downto 0);\n injectsbiterr : in std_logic := '0';\n injectdbiterr : in std_logic := '0';\n eccpipece : in std_logic := '0';\n sbiterr : out std_logic;\n dbiterr : out std_logic;\n rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);\n sleep : in std_logic := '0';\n deepsleep : in std_logic := '0';\n shutdown : in std_logic := '0';\n rsta_busy : out std_logic;\n rstb_busy : out std_logic;\n s_aclk : in std_logic := '0';\n s_aresetn : in std_logic := '0';\n s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');\n s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');\n s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');\n s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');\n s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');\n s_axi_awvalid : in std_logic := '0';\n s_axi_awready : out std_logic;\n s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');\n s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');\n s_axi_wlast : in std_logic := '0';\n s_axi_wvalid : in std_logic := '0';\n s_axi_wready : out std_logic;\n s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);\n s_axi_bresp : out std_logic_vector(1 downto 0);\n s_axi_bvalid : out std_logic;\n s_axi_bready : in std_logic := '0';\n s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');\n s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');\n s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');\n s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');\n s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');\n s_axi_arvalid : in std_logic := '0';\n s_axi_arready : out std_logic;\n s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);\n s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);\n s_axi_rresp : out std_logic_vector(2 - 1 downto 0);\n s_axi_rlast : out std_logic;\n s_axi_rvalid : out std_logic;\n s_axi_rready : in std_logic := '0';\n s_axi_injectsbiterr : in std_logic := '0';\n s_axi_injectdbiterr : in std_logic := '0';\n s_axi_sbiterr : out std_logic;\n s_axi_dbiterr : out std_logic;\n s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)\n );\nend entity blk_mem_gen_v8_3_4;\n\narchitecture xilinx of blk_mem_gen_v8_3_4 is\n begin\n end \narchitecture xilinx;\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer.xci", "content": "\n\n xilinx.com\n xci\n unknown\n 1.0\n \n \n output_line_buffer\n \n \n 4096\n 10\n 12\n 1\n 4\n 0\n 1\n 9\n 0\n 1\n 7\n NONE\n 0\n 0\n 0\n ./\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n Estimated Power for IP : 33.580152 mW\n kintex7\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n output_line_buffer.mem\n no_coe_file_loaded\n 0\n 0\n 1\n 0\n 1\n 1024\n 4096\n 256\n 64\n 0\n 0\n CE\n CE\n ALL\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 1\n 1024\n 4096\n NO_CHANGE\n WRITE_FIRST\n 256\n 64\n kintex7\n 4\n Memory_Slave\n AXI4_Full\n false\n Minimum_Area\n false\n 9\n NONE\n no_coe_file_loaded\n ALL\n output_line_buffer\n false\n false\n false\n false\n false\n false\n false\n false\n false\n Use_ENA_Pin\n Always_Enabled\n Single_Bit_Error_Injection\n false\n Native\n false\n no_mem_loaded\n Simple_Dual_Port_RAM\n NO_CHANGE\n WRITE_FIRST\n 0\n 0\n BRAM\n 0\n 100\n 100\n 50\n 100\n 100\n 0\n 8kx2\n false\n false\n 256\n 64\n false\n false\n false\n false\n 0\n false\n false\n CE\n CE\n SYNC\n false\n false\n false\n false\n false\n false\n false\n 1024\n 256\n 64\n No_ECC\n false\n false\n false\n Stand_Alone\n kintex7\n \n xc7k325t\n ffg900\n VERILOG\n \n MIXED\n -2\n \n TRUE\n TRUE\n IP_Flow\n 4\n TRUE\n .\n \n .\n 2016.3\n OUT_OF_CONTEXT\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_ooc.xdc", "content": "################################################################################\n#\n# (c) Copyright 2002 - 2013 Xilinx, Inc. All rights reserved.\n# \n# This file contains confidential and proprietary information\n# of Xilinx, Inc. and is protected under U.S. and\n# international copyright and other intellectual property\n# laws.\n# \n# DISCLAIMER\n# This disclaimer is not a license and does not grant any\n# rights to the materials distributed herewith. Except as\n# otherwise provided in a valid license issued to you by\n# Xilinx, and to the maximum extent permitted by applicable\n# law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n# (2) Xilinx shall not be liable (whether in contract or tort,\n# including negligence, or under any other theory of\n# liability) for any loss or damage of any kind or nature\n# related to, arising under or in connection with these\n# materials, including for any direct, or any indirect,\n# special, incidental, or consequential loss or damage\n# (including loss of data, profits, goodwill, or any type of\n# loss or damage suffered as a result of any action brought\n# by a third party) even if such damage or loss was\n# reasonably foreseeable or Xilinx had been advised of the\n# possibility of the same.\n# \n# CRITICAL APPLICATIONS\n# Xilinx products are not designed or intended to be fail-\n# safe, or for use in any application requiring fail-safe\n# performance, such as life-support or safety devices or\n# systems, Class III medical devices, nuclear facilities,\n# applications related to the deployment of airbags, or any\n# other applications that could lead to death, personal\n# injury, or severe property or environmental damage\n# (individually and collectively, \"Critical\n# Applications\"). Customer assumes the sole risk and\n# liability of any use of Xilinx products in Critical\n# Applications, subject only to applicable laws and\n# regulations governing limitations on product liability.\n# \n# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n# PART OF THIS FILE AT ALL TIMES.\n#\n################################################################################\n\n# Core Period Constraint. This constraint can be modified, and is\n# valid as long as it is met after place and route.\ncreate_clock -name \"TS_CLKA\" -period 20.0 [ get_ports clka ]\n set_property HD.CLK_SRC BUFGCTRL_X0Y0 [ get_ports clka ]\n \ncreate_clock -name \"TS_CLKB\" -period 20.0 [ get_ports clkb ]\n set_property HD.CLK_SRC BUFGCTRL_X0Y1 [ get_ports clkb ]\n################################################################################\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_sim_netlist.v", "content": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// --------------------------------------------------------------------------------\n// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016\n// Date : Tue Nov 15 09:42:01 2016\n// Host : david-desktop-arch running 64-bit unknown\n// Command : write_verilog -force -mode funcsim\n// /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_sim_netlist.v\n// Design : output_line_buffer\n// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified\n// or synthesized. This netlist cannot be used for SDF annotated simulation.\n// Device : xc7k325tffg900-2\n// --------------------------------------------------------------------------------\n`timescale 1 ps / 1 ps\n\n(* CHECK_LICENSE_TYPE = \"output_line_buffer,blk_mem_gen_v8_3_4,{}\" *) (* downgradeipidentifiedwarnings = \"yes\" *) (* x_core_info = \"blk_mem_gen_v8_3_4,Vivado 2016.3\" *) \n(* NotValidForBitStream *)\nmodule output_line_buffer\n (clka,\n ena,\n wea,\n addra,\n dina,\n clkb,\n addrb,\n doutb);\n (* x_interface_info = \"xilinx.com:interface:bram:1.0 BRAM_PORTA CLK\" *) input clka;\n (* x_interface_info = \"xilinx.com:interface:bram:1.0 BRAM_PORTA EN\" *) input ena;\n (* x_interface_info = \"xilinx.com:interface:bram:1.0 BRAM_PORTA WE\" *) input [0:0]wea;\n (* x_interface_info = \"xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR\" *) input [9:0]addra;\n (* x_interface_info = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DIN\" *) input [255:0]dina;\n (* x_interface_info = \"xilinx.com:interface:bram:1.0 BRAM_PORTB CLK\" *) input clkb;\n (* x_interface_info = \"xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR\" *) input [11:0]addrb;\n (* x_interface_info = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT\" *) output [63:0]doutb;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [255:0]dina;\n wire [63:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire NLW_U0_dbiterr_UNCONNECTED;\n wire NLW_U0_rsta_busy_UNCONNECTED;\n wire NLW_U0_rstb_busy_UNCONNECTED;\n wire NLW_U0_s_axi_arready_UNCONNECTED;\n wire NLW_U0_s_axi_awready_UNCONNECTED;\n wire NLW_U0_s_axi_bvalid_UNCONNECTED;\n wire NLW_U0_s_axi_dbiterr_UNCONNECTED;\n wire NLW_U0_s_axi_rlast_UNCONNECTED;\n wire NLW_U0_s_axi_rvalid_UNCONNECTED;\n wire NLW_U0_s_axi_sbiterr_UNCONNECTED;\n wire NLW_U0_s_axi_wready_UNCONNECTED;\n wire NLW_U0_sbiterr_UNCONNECTED;\n wire [255:0]NLW_U0_douta_UNCONNECTED;\n wire [11:0]NLW_U0_rdaddrecc_UNCONNECTED;\n wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;\n wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;\n wire [11:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;\n wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;\n wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;\n wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;\n\n (* C_ADDRA_WIDTH = \"10\" *) \n (* C_ADDRB_WIDTH = \"12\" *) \n (* C_ALGORITHM = \"1\" *) \n (* C_AXI_ID_WIDTH = \"4\" *) \n (* C_AXI_SLAVE_TYPE = \"0\" *) \n (* C_AXI_TYPE = \"1\" *) \n (* C_BYTE_SIZE = \"9\" *) \n (* C_COMMON_CLK = \"0\" *) \n (* C_COUNT_18K_BRAM = \"1\" *) \n (* C_COUNT_36K_BRAM = \"7\" *) \n (* C_CTRL_ECC_ALGO = \"NONE\" *) \n (* C_DEFAULT_DATA = \"0\" *) \n (* C_DISABLE_WARN_BHV_COLL = \"0\" *) \n (* C_DISABLE_WARN_BHV_RANGE = \"0\" *) \n (* C_ELABORATION_DIR = \"./\" *) \n (* C_ENABLE_32BIT_ADDRESS = \"0\" *) \n (* C_EN_DEEPSLEEP_PIN = \"0\" *) \n (* C_EN_ECC_PIPE = \"0\" *) \n (* C_EN_RDADDRA_CHG = \"0\" *) \n (* C_EN_RDADDRB_CHG = \"0\" *) \n (* C_EN_SAFETY_CKT = \"0\" *) \n (* C_EN_SHUTDOWN_PIN = \"0\" *) \n (* C_EN_SLEEP_PIN = \"0\" *) \n (* C_EST_POWER_SUMMARY = \"Estimated Power for IP : 33.580152 mW\" *) \n (* C_FAMILY = \"kintex7\" *) \n (* C_HAS_AXI_ID = \"0\" *) \n (* C_HAS_ENA = \"1\" *) \n (* C_HAS_ENB = \"0\" *) \n (* C_HAS_INJECTERR = \"0\" *) \n (* C_HAS_MEM_OUTPUT_REGS_A = \"0\" *) \n (* C_HAS_MEM_OUTPUT_REGS_B = \"0\" *) \n (* C_HAS_MUX_OUTPUT_REGS_A = \"0\" *) \n (* C_HAS_MUX_OUTPUT_REGS_B = \"0\" *) \n (* C_HAS_REGCEA = \"0\" *) \n (* C_HAS_REGCEB = \"0\" *) \n (* C_HAS_RSTA = \"0\" *) \n (* C_HAS_RSTB = \"0\" *) \n (* C_HAS_SOFTECC_INPUT_REGS_A = \"0\" *) \n (* C_HAS_SOFTECC_OUTPUT_REGS_B = \"0\" *) \n (* C_INITA_VAL = \"0\" *) \n (* C_INITB_VAL = \"0\" *) \n (* C_INIT_FILE = \"output_line_buffer.mem\" *) \n (* C_INIT_FILE_NAME = \"no_coe_file_loaded\" *) \n (* C_INTERFACE_TYPE = \"0\" *) \n (* C_LOAD_INIT_FILE = \"0\" *) \n (* C_MEM_TYPE = \"1\" *) \n (* C_MUX_PIPELINE_STAGES = \"0\" *) \n (* C_PRIM_TYPE = \"1\" *) \n (* C_READ_DEPTH_A = \"1024\" *) \n (* C_READ_DEPTH_B = \"4096\" *) \n (* C_READ_WIDTH_A = \"256\" *) \n (* C_READ_WIDTH_B = \"64\" *) \n (* C_RSTRAM_A = \"0\" *) \n (* C_RSTRAM_B = \"0\" *) \n (* C_RST_PRIORITY_A = \"CE\" *) \n (* C_RST_PRIORITY_B = \"CE\" *) \n (* C_SIM_COLLISION_CHECK = \"ALL\" *) \n (* C_USE_BRAM_BLOCK = \"0\" *) \n (* C_USE_BYTE_WEA = \"0\" *) \n (* C_USE_BYTE_WEB = \"0\" *) \n (* C_USE_DEFAULT_DATA = \"0\" *) \n (* C_USE_ECC = \"0\" *) \n (* C_USE_SOFTECC = \"0\" *) \n (* C_USE_URAM = \"0\" *) \n (* C_WEA_WIDTH = \"1\" *) \n (* C_WEB_WIDTH = \"1\" *) \n (* C_WRITE_DEPTH_A = \"1024\" *) \n (* C_WRITE_DEPTH_B = \"4096\" *) \n (* C_WRITE_MODE_A = \"NO_CHANGE\" *) \n (* C_WRITE_MODE_B = \"WRITE_FIRST\" *) \n (* C_WRITE_WIDTH_A = \"256\" *) \n (* C_WRITE_WIDTH_B = \"64\" *) \n (* C_XDEVICEFAMILY = \"kintex7\" *) \n (* downgradeipidentifiedwarnings = \"yes\" *) \n output_line_buffer_blk_mem_gen_v8_3_4 U0\n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dbiterr(NLW_U0_dbiterr_UNCONNECTED),\n .deepsleep(1'b0),\n .dina(dina),\n .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .douta(NLW_U0_douta_UNCONNECTED[255:0]),\n .doutb(doutb),\n .eccpipece(1'b0),\n .ena(ena),\n .enb(1'b0),\n .injectdbiterr(1'b0),\n .injectsbiterr(1'b0),\n .rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[11:0]),\n .regcea(1'b0),\n .regceb(1'b0),\n .rsta(1'b0),\n .rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),\n .rstb(1'b0),\n .rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),\n .s_aclk(1'b0),\n .s_aresetn(1'b0),\n .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axi_arburst({1'b0,1'b0}),\n .s_axi_arid({1'b0,1'b0,1'b0,1'b0}),\n .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),\n .s_axi_arsize({1'b0,1'b0,1'b0}),\n .s_axi_arvalid(1'b0),\n .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axi_awburst({1'b0,1'b0}),\n .s_axi_awid({1'b0,1'b0,1'b0,1'b0}),\n .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),\n .s_axi_awsize({1'b0,1'b0,1'b0}),\n .s_axi_awvalid(1'b0),\n .s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),\n .s_axi_bready(1'b0),\n .s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),\n .s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),\n .s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),\n .s_axi_injectdbiterr(1'b0),\n .s_axi_injectsbiterr(1'b0),\n .s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[11:0]),\n .s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),\n .s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),\n .s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),\n .s_axi_rready(1'b0),\n .s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),\n .s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),\n .s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),\n .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .s_axi_wlast(1'b0),\n .s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),\n .s_axi_wstrb(1'b0),\n .s_axi_wvalid(1'b0),\n .sbiterr(NLW_U0_sbiterr_UNCONNECTED),\n .shutdown(1'b0),\n .sleep(1'b0),\n .wea(wea),\n .web(1'b0));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_generic_cstr\" *) \nmodule output_line_buffer_blk_mem_gen_generic_cstr\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [63:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [255:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [255:0]dina;\n wire [63:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n output_line_buffer_blk_mem_gen_prim_width \\ramloop[0].ram.r \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina({dina[195:192],dina[131:128],dina[67:64],dina[3:0]}),\n .doutb(doutb[3:0]),\n .ena(ena),\n .wea(wea));\n output_line_buffer_blk_mem_gen_prim_width__parameterized0 \\ramloop[1].ram.r \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina({dina[204:196],dina[140:132],dina[76:68],dina[12:4]}),\n .doutb(doutb[12:4]),\n .ena(ena),\n .wea(wea));\n output_line_buffer_blk_mem_gen_prim_width__parameterized1 \\ramloop[2].ram.r \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina({dina[213:205],dina[149:141],dina[85:77],dina[21:13]}),\n .doutb(doutb[21:13]),\n .ena(ena),\n .wea(wea));\n output_line_buffer_blk_mem_gen_prim_width__parameterized2 \\ramloop[3].ram.r \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina({dina[222:214],dina[158:150],dina[94:86],dina[30:22]}),\n .doutb(doutb[30:22]),\n .ena(ena),\n .wea(wea));\n output_line_buffer_blk_mem_gen_prim_width__parameterized3 \\ramloop[4].ram.r \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina({dina[231:223],dina[167:159],dina[103:95],dina[39:31]}),\n .doutb(doutb[39:31]),\n .ena(ena),\n .wea(wea));\n output_line_buffer_blk_mem_gen_prim_width__parameterized4 \\ramloop[5].ram.r \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina({dina[240:232],dina[176:168],dina[112:104],dina[48:40]}),\n .doutb(doutb[48:40]),\n .ena(ena),\n .wea(wea));\n output_line_buffer_blk_mem_gen_prim_width__parameterized5 \\ramloop[6].ram.r \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina({dina[249:241],dina[185:177],dina[121:113],dina[57:49]}),\n .doutb(doutb[57:49]),\n .ena(ena),\n .wea(wea));\n output_line_buffer_blk_mem_gen_prim_width__parameterized6 \\ramloop[7].ram.r \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina({dina[255:250],dina[191:186],dina[127:122],dina[63:58]}),\n .doutb(doutb[63:58]),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule output_line_buffer_blk_mem_gen_prim_width\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [3:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [15:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [15:0]dina;\n wire [3:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n output_line_buffer_blk_mem_gen_prim_wrapper \\prim_noinit.ram \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule output_line_buffer_blk_mem_gen_prim_width__parameterized0\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [8:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [35:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [35:0]dina;\n wire [8:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n output_line_buffer_blk_mem_gen_prim_wrapper__parameterized0 \\prim_noinit.ram \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule output_line_buffer_blk_mem_gen_prim_width__parameterized1\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [8:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [35:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [35:0]dina;\n wire [8:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n output_line_buffer_blk_mem_gen_prim_wrapper__parameterized1 \\prim_noinit.ram \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule output_line_buffer_blk_mem_gen_prim_width__parameterized2\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [8:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [35:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [35:0]dina;\n wire [8:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n output_line_buffer_blk_mem_gen_prim_wrapper__parameterized2 \\prim_noinit.ram \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule output_line_buffer_blk_mem_gen_prim_width__parameterized3\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [8:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [35:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [35:0]dina;\n wire [8:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n output_line_buffer_blk_mem_gen_prim_wrapper__parameterized3 \\prim_noinit.ram \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule output_line_buffer_blk_mem_gen_prim_width__parameterized4\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [8:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [35:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [35:0]dina;\n wire [8:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n output_line_buffer_blk_mem_gen_prim_wrapper__parameterized4 \\prim_noinit.ram \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule output_line_buffer_blk_mem_gen_prim_width__parameterized5\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [8:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [35:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [35:0]dina;\n wire [8:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n output_line_buffer_blk_mem_gen_prim_wrapper__parameterized5 \\prim_noinit.ram \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_width\" *) \nmodule output_line_buffer_blk_mem_gen_prim_width__parameterized6\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [5:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [23:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [23:0]dina;\n wire [5:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n output_line_buffer_blk_mem_gen_prim_wrapper__parameterized6 \\prim_noinit.ram \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule output_line_buffer_blk_mem_gen_prim_wrapper\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [3:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [15:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [15:0]dina;\n wire [3:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire [15:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ;\n wire [15:4]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;\n wire [1:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ;\n wire [1:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB18E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(18'h00000),\n .INIT_B(18'h00000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_MODE(\"TDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(4),\n .READ_WIDTH_B(4),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(18'h00000),\n .SRVAL_B(18'h00000),\n .WRITE_MODE_A(\"NO_CHANGE\"),\n .WRITE_MODE_B(\"NO_CHANGE\"),\n .WRITE_WIDTH_A(18),\n .WRITE_WIDTH_B(18)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram \n (.ADDRARDADDR({addra,1'b0,1'b0,1'b0,1'b0}),\n .ADDRBWRADDR({addrb,1'b0,1'b0}),\n .CLKARDCLK(clka),\n .CLKBWRCLK(clkb),\n .DIADI(dina),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIPADIP({1'b0,1'b0}),\n .DIPBDIP({1'b0,1'b0}),\n .DOADO(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:0]),\n .DOBDO({\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:4],doutb}),\n .DOPADOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]),\n .DOPBDOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]),\n .ENARDEN(ena),\n .ENBWREN(1'b1),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(1'b0),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .WEA({wea,wea}),\n .WEBWE({1'b0,1'b0,1'b0,1'b0}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule output_line_buffer_blk_mem_gen_prim_wrapper__parameterized0\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [8:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [35:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [35:0]dina;\n wire [8:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;\n wire [31:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;\n wire [31:8]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;\n wire [3:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;\n wire [3:1]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;\n wire [7:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;\n wire [8:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB36E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .EN_ECC_READ(\"FALSE\"),\n .EN_ECC_WRITE(\"FALSE\"),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(36'h000000000),\n .INIT_B(36'h000000000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_EXTENSION_A(\"NONE\"),\n .RAM_EXTENSION_B(\"NONE\"),\n .RAM_MODE(\"TDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(9),\n .READ_WIDTH_B(9),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(36'h000000000),\n .SRVAL_B(36'h000000000),\n .WRITE_MODE_A(\"NO_CHANGE\"),\n .WRITE_MODE_B(\"NO_CHANGE\"),\n .WRITE_WIDTH_A(36),\n .WRITE_WIDTH_B(36)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram \n (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}),\n .CASCADEINA(1'b0),\n .CASCADEINB(1'b0),\n .CASCADEOUTA(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),\n .CASCADEOUTB(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),\n .CLKARDCLK(clka),\n .CLKBWRCLK(clkb),\n .DBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),\n .DIADI({dina[34:27],dina[25:18],dina[16:9],dina[7:0]}),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIPADIP({dina[35],dina[26],dina[17],dina[8]}),\n .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),\n .DOADO(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),\n .DOBDO({\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb[7:0]}),\n .DOPADOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),\n .DOPBDOP({\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb[8]}),\n .ECCPARITY(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),\n .ENARDEN(ena),\n .ENBWREN(1'b1),\n .INJECTDBITERR(1'b0),\n .INJECTSBITERR(1'b0),\n .RDADDRECC(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(1'b0),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .SBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),\n .WEA({wea,wea,wea,wea}),\n .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule output_line_buffer_blk_mem_gen_prim_wrapper__parameterized1\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [8:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [35:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [35:0]dina;\n wire [8:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;\n wire [31:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;\n wire [31:8]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;\n wire [3:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;\n wire [3:1]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;\n wire [7:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;\n wire [8:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB36E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .EN_ECC_READ(\"FALSE\"),\n .EN_ECC_WRITE(\"FALSE\"),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(36'h000000000),\n .INIT_B(36'h000000000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_EXTENSION_A(\"NONE\"),\n .RAM_EXTENSION_B(\"NONE\"),\n .RAM_MODE(\"TDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(9),\n .READ_WIDTH_B(9),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(36'h000000000),\n .SRVAL_B(36'h000000000),\n .WRITE_MODE_A(\"NO_CHANGE\"),\n .WRITE_MODE_B(\"NO_CHANGE\"),\n .WRITE_WIDTH_A(36),\n .WRITE_WIDTH_B(36)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram \n (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}),\n .CASCADEINA(1'b0),\n .CASCADEINB(1'b0),\n .CASCADEOUTA(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),\n .CASCADEOUTB(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),\n .CLKARDCLK(clka),\n .CLKBWRCLK(clkb),\n .DBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),\n .DIADI({dina[34:27],dina[25:18],dina[16:9],dina[7:0]}),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIPADIP({dina[35],dina[26],dina[17],dina[8]}),\n .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),\n .DOADO(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),\n .DOBDO({\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb[7:0]}),\n .DOPADOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),\n .DOPBDOP({\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb[8]}),\n .ECCPARITY(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),\n .ENARDEN(ena),\n .ENBWREN(1'b1),\n .INJECTDBITERR(1'b0),\n .INJECTSBITERR(1'b0),\n .RDADDRECC(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(1'b0),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .SBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),\n .WEA({wea,wea,wea,wea}),\n .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule output_line_buffer_blk_mem_gen_prim_wrapper__parameterized2\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [8:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [35:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [35:0]dina;\n wire [8:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;\n wire [31:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;\n wire [31:8]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;\n wire [3:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;\n wire [3:1]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;\n wire [7:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;\n wire [8:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB36E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .EN_ECC_READ(\"FALSE\"),\n .EN_ECC_WRITE(\"FALSE\"),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(36'h000000000),\n .INIT_B(36'h000000000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_EXTENSION_A(\"NONE\"),\n .RAM_EXTENSION_B(\"NONE\"),\n .RAM_MODE(\"TDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(9),\n .READ_WIDTH_B(9),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(36'h000000000),\n .SRVAL_B(36'h000000000),\n .WRITE_MODE_A(\"NO_CHANGE\"),\n .WRITE_MODE_B(\"NO_CHANGE\"),\n .WRITE_WIDTH_A(36),\n .WRITE_WIDTH_B(36)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram \n (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}),\n .CASCADEINA(1'b0),\n .CASCADEINB(1'b0),\n .CASCADEOUTA(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),\n .CASCADEOUTB(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),\n .CLKARDCLK(clka),\n .CLKBWRCLK(clkb),\n .DBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),\n .DIADI({dina[34:27],dina[25:18],dina[16:9],dina[7:0]}),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIPADIP({dina[35],dina[26],dina[17],dina[8]}),\n .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),\n .DOADO(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),\n .DOBDO({\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb[7:0]}),\n .DOPADOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),\n .DOPBDOP({\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb[8]}),\n .ECCPARITY(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),\n .ENARDEN(ena),\n .ENBWREN(1'b1),\n .INJECTDBITERR(1'b0),\n .INJECTSBITERR(1'b0),\n .RDADDRECC(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(1'b0),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .SBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),\n .WEA({wea,wea,wea,wea}),\n .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule output_line_buffer_blk_mem_gen_prim_wrapper__parameterized3\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [8:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [35:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [35:0]dina;\n wire [8:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;\n wire [31:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;\n wire [31:8]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;\n wire [3:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;\n wire [3:1]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;\n wire [7:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;\n wire [8:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB36E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .EN_ECC_READ(\"FALSE\"),\n .EN_ECC_WRITE(\"FALSE\"),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(36'h000000000),\n .INIT_B(36'h000000000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_EXTENSION_A(\"NONE\"),\n .RAM_EXTENSION_B(\"NONE\"),\n .RAM_MODE(\"TDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(9),\n .READ_WIDTH_B(9),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(36'h000000000),\n .SRVAL_B(36'h000000000),\n .WRITE_MODE_A(\"NO_CHANGE\"),\n .WRITE_MODE_B(\"NO_CHANGE\"),\n .WRITE_WIDTH_A(36),\n .WRITE_WIDTH_B(36)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram \n (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}),\n .CASCADEINA(1'b0),\n .CASCADEINB(1'b0),\n .CASCADEOUTA(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),\n .CASCADEOUTB(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),\n .CLKARDCLK(clka),\n .CLKBWRCLK(clkb),\n .DBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),\n .DIADI({dina[34:27],dina[25:18],dina[16:9],dina[7:0]}),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIPADIP({dina[35],dina[26],dina[17],dina[8]}),\n .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),\n .DOADO(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),\n .DOBDO({\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb[7:0]}),\n .DOPADOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),\n .DOPBDOP({\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb[8]}),\n .ECCPARITY(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),\n .ENARDEN(ena),\n .ENBWREN(1'b1),\n .INJECTDBITERR(1'b0),\n .INJECTSBITERR(1'b0),\n .RDADDRECC(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(1'b0),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .SBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),\n .WEA({wea,wea,wea,wea}),\n .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule output_line_buffer_blk_mem_gen_prim_wrapper__parameterized4\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [8:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [35:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [35:0]dina;\n wire [8:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;\n wire [31:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;\n wire [31:8]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;\n wire [3:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;\n wire [3:1]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;\n wire [7:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;\n wire [8:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB36E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .EN_ECC_READ(\"FALSE\"),\n .EN_ECC_WRITE(\"FALSE\"),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(36'h000000000),\n .INIT_B(36'h000000000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_EXTENSION_A(\"NONE\"),\n .RAM_EXTENSION_B(\"NONE\"),\n .RAM_MODE(\"TDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(9),\n .READ_WIDTH_B(9),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(36'h000000000),\n .SRVAL_B(36'h000000000),\n .WRITE_MODE_A(\"NO_CHANGE\"),\n .WRITE_MODE_B(\"NO_CHANGE\"),\n .WRITE_WIDTH_A(36),\n .WRITE_WIDTH_B(36)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram \n (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}),\n .CASCADEINA(1'b0),\n .CASCADEINB(1'b0),\n .CASCADEOUTA(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),\n .CASCADEOUTB(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),\n .CLKARDCLK(clka),\n .CLKBWRCLK(clkb),\n .DBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),\n .DIADI({dina[34:27],dina[25:18],dina[16:9],dina[7:0]}),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIPADIP({dina[35],dina[26],dina[17],dina[8]}),\n .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),\n .DOADO(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),\n .DOBDO({\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb[7:0]}),\n .DOPADOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),\n .DOPBDOP({\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb[8]}),\n .ECCPARITY(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),\n .ENARDEN(ena),\n .ENBWREN(1'b1),\n .INJECTDBITERR(1'b0),\n .INJECTSBITERR(1'b0),\n .RDADDRECC(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(1'b0),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .SBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),\n .WEA({wea,wea,wea,wea}),\n .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule output_line_buffer_blk_mem_gen_prim_wrapper__parameterized5\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [8:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [35:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [35:0]dina;\n wire [8:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;\n wire [31:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;\n wire [31:8]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;\n wire [3:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;\n wire [3:1]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;\n wire [7:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;\n wire [8:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB36E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .EN_ECC_READ(\"FALSE\"),\n .EN_ECC_WRITE(\"FALSE\"),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(36'h000000000),\n .INIT_B(36'h000000000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_EXTENSION_A(\"NONE\"),\n .RAM_EXTENSION_B(\"NONE\"),\n .RAM_MODE(\"TDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(9),\n .READ_WIDTH_B(9),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(36'h000000000),\n .SRVAL_B(36'h000000000),\n .WRITE_MODE_A(\"NO_CHANGE\"),\n .WRITE_MODE_B(\"NO_CHANGE\"),\n .WRITE_WIDTH_A(36),\n .WRITE_WIDTH_B(36)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram \n (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}),\n .CASCADEINA(1'b0),\n .CASCADEINB(1'b0),\n .CASCADEOUTA(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),\n .CASCADEOUTB(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),\n .CLKARDCLK(clka),\n .CLKBWRCLK(clkb),\n .DBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),\n .DIADI({dina[34:27],dina[25:18],dina[16:9],dina[7:0]}),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIPADIP({dina[35],dina[26],dina[17],dina[8]}),\n .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),\n .DOADO(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),\n .DOBDO({\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb[7:0]}),\n .DOPADOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),\n .DOPBDOP({\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb[8]}),\n .ECCPARITY(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),\n .ENARDEN(ena),\n .ENBWREN(1'b1),\n .INJECTDBITERR(1'b0),\n .INJECTSBITERR(1'b0),\n .RDADDRECC(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(1'b0),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .SBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),\n .WEA({wea,wea,wea,wea}),\n .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_prim_wrapper\" *) \nmodule output_line_buffer_blk_mem_gen_prim_wrapper__parameterized6\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [5:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [23:0]dina;\n input [0:0]wea;\n\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78 ;\n wire \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ;\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [23:0]dina;\n wire [5:0]doutb;\n wire ena;\n wire [0:0]wea;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;\n wire \\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;\n wire [31:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;\n wire [31:8]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;\n wire [3:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;\n wire [3:1]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;\n wire [7:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;\n wire [8:0]\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;\n\n (* CLOCK_DOMAINS = \"INDEPENDENT\" *) \n (* box_type = \"PRIMITIVE\" *) \n RAMB36E1 #(\n .DOA_REG(0),\n .DOB_REG(0),\n .EN_ECC_READ(\"FALSE\"),\n .EN_ECC_WRITE(\"FALSE\"),\n .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),\n .INIT_A(36'h000000000),\n .INIT_B(36'h000000000),\n .INIT_FILE(\"NONE\"),\n .IS_CLKARDCLK_INVERTED(1'b0),\n .IS_CLKBWRCLK_INVERTED(1'b0),\n .IS_ENARDEN_INVERTED(1'b0),\n .IS_ENBWREN_INVERTED(1'b0),\n .IS_RSTRAMARSTRAM_INVERTED(1'b0),\n .IS_RSTRAMB_INVERTED(1'b0),\n .IS_RSTREGARSTREG_INVERTED(1'b0),\n .IS_RSTREGB_INVERTED(1'b0),\n .RAM_EXTENSION_A(\"NONE\"),\n .RAM_EXTENSION_B(\"NONE\"),\n .RAM_MODE(\"TDP\"),\n .RDADDR_COLLISION_HWCONFIG(\"DELAYED_WRITE\"),\n .READ_WIDTH_A(9),\n .READ_WIDTH_B(9),\n .RSTREG_PRIORITY_A(\"REGCE\"),\n .RSTREG_PRIORITY_B(\"REGCE\"),\n .SIM_COLLISION_CHECK(\"ALL\"),\n .SIM_DEVICE(\"7SERIES\"),\n .SRVAL_A(36'h000000000),\n .SRVAL_B(36'h000000000),\n .WRITE_MODE_A(\"NO_CHANGE\"),\n .WRITE_MODE_B(\"NO_CHANGE\"),\n .WRITE_WIDTH_A(36),\n .WRITE_WIDTH_B(36)) \n \\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram \n (.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),\n .ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}),\n .CASCADEINA(1'b0),\n .CASCADEINB(1'b0),\n .CASCADEOUTA(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),\n .CASCADEOUTB(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),\n .CLKARDCLK(clka),\n .CLKBWRCLK(clkb),\n .DBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),\n .DIADI({1'b0,1'b0,dina[23:18],1'b0,1'b0,dina[17:12],1'b0,1'b0,dina[11:6],1'b0,1'b0,dina[5:0]}),\n .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),\n .DIPADIP({1'b0,1'b0,1'b0,1'b0}),\n .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),\n .DOADO(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),\n .DOBDO({\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ,\\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78 ,doutb}),\n .DOPADOP(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),\n .DOPBDOP({\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }),\n .ECCPARITY(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),\n .ENARDEN(ena),\n .ENBWREN(1'b1),\n .INJECTDBITERR(1'b0),\n .INJECTSBITERR(1'b0),\n .RDADDRECC(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),\n .REGCEAREGCE(1'b0),\n .REGCEB(1'b0),\n .RSTRAMARSTRAM(1'b0),\n .RSTRAMB(1'b0),\n .RSTREGARSTREG(1'b0),\n .RSTREGB(1'b0),\n .SBITERR(\\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),\n .WEA({wea,wea,wea,wea}),\n .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_top\" *) \nmodule output_line_buffer_blk_mem_gen_top\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [63:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [255:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [255:0]dina;\n wire [63:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n output_line_buffer_blk_mem_gen_generic_cstr \\valid.cstr \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* C_ADDRA_WIDTH = \"10\" *) (* C_ADDRB_WIDTH = \"12\" *) (* C_ALGORITHM = \"1\" *) \n(* C_AXI_ID_WIDTH = \"4\" *) (* C_AXI_SLAVE_TYPE = \"0\" *) (* C_AXI_TYPE = \"1\" *) \n(* C_BYTE_SIZE = \"9\" *) (* C_COMMON_CLK = \"0\" *) (* C_COUNT_18K_BRAM = \"1\" *) \n(* C_COUNT_36K_BRAM = \"7\" *) (* C_CTRL_ECC_ALGO = \"NONE\" *) (* C_DEFAULT_DATA = \"0\" *) \n(* C_DISABLE_WARN_BHV_COLL = \"0\" *) (* C_DISABLE_WARN_BHV_RANGE = \"0\" *) (* C_ELABORATION_DIR = \"./\" *) \n(* C_ENABLE_32BIT_ADDRESS = \"0\" *) (* C_EN_DEEPSLEEP_PIN = \"0\" *) (* C_EN_ECC_PIPE = \"0\" *) \n(* C_EN_RDADDRA_CHG = \"0\" *) (* C_EN_RDADDRB_CHG = \"0\" *) (* C_EN_SAFETY_CKT = \"0\" *) \n(* C_EN_SHUTDOWN_PIN = \"0\" *) (* C_EN_SLEEP_PIN = \"0\" *) (* C_EST_POWER_SUMMARY = \"Estimated Power for IP : 33.580152 mW\" *) \n(* C_FAMILY = \"kintex7\" *) (* C_HAS_AXI_ID = \"0\" *) (* C_HAS_ENA = \"1\" *) \n(* C_HAS_ENB = \"0\" *) (* C_HAS_INJECTERR = \"0\" *) (* C_HAS_MEM_OUTPUT_REGS_A = \"0\" *) \n(* C_HAS_MEM_OUTPUT_REGS_B = \"0\" *) (* C_HAS_MUX_OUTPUT_REGS_A = \"0\" *) (* C_HAS_MUX_OUTPUT_REGS_B = \"0\" *) \n(* C_HAS_REGCEA = \"0\" *) (* C_HAS_REGCEB = \"0\" *) (* C_HAS_RSTA = \"0\" *) \n(* C_HAS_RSTB = \"0\" *) (* C_HAS_SOFTECC_INPUT_REGS_A = \"0\" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = \"0\" *) \n(* C_INITA_VAL = \"0\" *) (* C_INITB_VAL = \"0\" *) (* C_INIT_FILE = \"output_line_buffer.mem\" *) \n(* C_INIT_FILE_NAME = \"no_coe_file_loaded\" *) (* C_INTERFACE_TYPE = \"0\" *) (* C_LOAD_INIT_FILE = \"0\" *) \n(* C_MEM_TYPE = \"1\" *) (* C_MUX_PIPELINE_STAGES = \"0\" *) (* C_PRIM_TYPE = \"1\" *) \n(* C_READ_DEPTH_A = \"1024\" *) (* C_READ_DEPTH_B = \"4096\" *) (* C_READ_WIDTH_A = \"256\" *) \n(* C_READ_WIDTH_B = \"64\" *) (* C_RSTRAM_A = \"0\" *) (* C_RSTRAM_B = \"0\" *) \n(* C_RST_PRIORITY_A = \"CE\" *) (* C_RST_PRIORITY_B = \"CE\" *) (* C_SIM_COLLISION_CHECK = \"ALL\" *) \n(* C_USE_BRAM_BLOCK = \"0\" *) (* C_USE_BYTE_WEA = \"0\" *) (* C_USE_BYTE_WEB = \"0\" *) \n(* C_USE_DEFAULT_DATA = \"0\" *) (* C_USE_ECC = \"0\" *) (* C_USE_SOFTECC = \"0\" *) \n(* C_USE_URAM = \"0\" *) (* C_WEA_WIDTH = \"1\" *) (* C_WEB_WIDTH = \"1\" *) \n(* C_WRITE_DEPTH_A = \"1024\" *) (* C_WRITE_DEPTH_B = \"4096\" *) (* C_WRITE_MODE_A = \"NO_CHANGE\" *) \n(* C_WRITE_MODE_B = \"WRITE_FIRST\" *) (* C_WRITE_WIDTH_A = \"256\" *) (* C_WRITE_WIDTH_B = \"64\" *) \n(* C_XDEVICEFAMILY = \"kintex7\" *) (* ORIG_REF_NAME = \"blk_mem_gen_v8_3_4\" *) (* downgradeipidentifiedwarnings = \"yes\" *) \nmodule output_line_buffer_blk_mem_gen_v8_3_4\n (clka,\n rsta,\n ena,\n regcea,\n wea,\n addra,\n dina,\n douta,\n clkb,\n rstb,\n enb,\n regceb,\n web,\n addrb,\n dinb,\n doutb,\n injectsbiterr,\n injectdbiterr,\n eccpipece,\n sbiterr,\n dbiterr,\n rdaddrecc,\n sleep,\n deepsleep,\n shutdown,\n rsta_busy,\n rstb_busy,\n s_aclk,\n s_aresetn,\n s_axi_awid,\n s_axi_awaddr,\n s_axi_awlen,\n s_axi_awsize,\n s_axi_awburst,\n s_axi_awvalid,\n s_axi_awready,\n s_axi_wdata,\n s_axi_wstrb,\n s_axi_wlast,\n s_axi_wvalid,\n s_axi_wready,\n s_axi_bid,\n s_axi_bresp,\n s_axi_bvalid,\n s_axi_bready,\n s_axi_arid,\n s_axi_araddr,\n s_axi_arlen,\n s_axi_arsize,\n s_axi_arburst,\n s_axi_arvalid,\n s_axi_arready,\n s_axi_rid,\n s_axi_rdata,\n s_axi_rresp,\n s_axi_rlast,\n s_axi_rvalid,\n s_axi_rready,\n s_axi_injectsbiterr,\n s_axi_injectdbiterr,\n s_axi_sbiterr,\n s_axi_dbiterr,\n s_axi_rdaddrecc);\n input clka;\n input rsta;\n input ena;\n input regcea;\n input [0:0]wea;\n input [9:0]addra;\n input [255:0]dina;\n output [255:0]douta;\n input clkb;\n input rstb;\n input enb;\n input regceb;\n input [0:0]web;\n input [11:0]addrb;\n input [63:0]dinb;\n output [63:0]doutb;\n input injectsbiterr;\n input injectdbiterr;\n input eccpipece;\n output sbiterr;\n output dbiterr;\n output [11:0]rdaddrecc;\n input sleep;\n input deepsleep;\n input shutdown;\n output rsta_busy;\n output rstb_busy;\n input s_aclk;\n input s_aresetn;\n input [3:0]s_axi_awid;\n input [31:0]s_axi_awaddr;\n input [7:0]s_axi_awlen;\n input [2:0]s_axi_awsize;\n input [1:0]s_axi_awburst;\n input s_axi_awvalid;\n output s_axi_awready;\n input [255:0]s_axi_wdata;\n input [0:0]s_axi_wstrb;\n input s_axi_wlast;\n input s_axi_wvalid;\n output s_axi_wready;\n output [3:0]s_axi_bid;\n output [1:0]s_axi_bresp;\n output s_axi_bvalid;\n input s_axi_bready;\n input [3:0]s_axi_arid;\n input [31:0]s_axi_araddr;\n input [7:0]s_axi_arlen;\n input [2:0]s_axi_arsize;\n input [1:0]s_axi_arburst;\n input s_axi_arvalid;\n output s_axi_arready;\n output [3:0]s_axi_rid;\n output [63:0]s_axi_rdata;\n output [1:0]s_axi_rresp;\n output s_axi_rlast;\n output s_axi_rvalid;\n input s_axi_rready;\n input s_axi_injectsbiterr;\n input s_axi_injectdbiterr;\n output s_axi_sbiterr;\n output s_axi_dbiterr;\n output [11:0]s_axi_rdaddrecc;\n\n wire \\ ;\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [255:0]dina;\n wire [63:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n assign dbiterr = \\ ;\n assign douta[255] = \\ ;\n assign douta[254] = \\ ;\n assign douta[253] = \\ ;\n assign douta[252] = \\ ;\n assign douta[251] = \\ ;\n assign douta[250] = \\ ;\n assign douta[249] = \\ ;\n assign douta[248] = \\ ;\n assign douta[247] = \\ ;\n assign douta[246] = \\ ;\n assign douta[245] = \\ ;\n assign douta[244] = \\ ;\n assign douta[243] = \\ ;\n assign douta[242] = \\ ;\n assign douta[241] = \\ ;\n assign douta[240] = \\ ;\n assign douta[239] = \\ ;\n assign douta[238] = \\ ;\n assign douta[237] = \\ ;\n assign douta[236] = \\ ;\n assign douta[235] = \\ ;\n assign douta[234] = \\ ;\n assign douta[233] = \\ ;\n assign douta[232] = \\ ;\n assign douta[231] = \\ ;\n assign douta[230] = \\ ;\n assign douta[229] = \\ ;\n assign douta[228] = \\ ;\n assign douta[227] = \\ ;\n assign douta[226] = \\ ;\n assign douta[225] = \\ ;\n assign douta[224] = \\ ;\n assign douta[223] = \\ ;\n assign douta[222] = \\ ;\n assign douta[221] = \\ ;\n assign douta[220] = \\ ;\n assign douta[219] = \\ ;\n assign douta[218] = \\ ;\n assign douta[217] = \\ ;\n assign douta[216] = \\ ;\n assign douta[215] = \\ ;\n assign douta[214] = \\ ;\n assign douta[213] = \\ ;\n assign douta[212] = \\ ;\n assign douta[211] = \\ ;\n assign douta[210] = \\ ;\n assign douta[209] = \\ ;\n assign douta[208] = \\ ;\n assign douta[207] = \\ ;\n assign douta[206] = \\ ;\n assign douta[205] = \\ ;\n assign douta[204] = \\ ;\n assign douta[203] = \\ ;\n assign douta[202] = \\ ;\n assign douta[201] = \\ ;\n assign douta[200] = \\ ;\n assign douta[199] = \\ ;\n assign douta[198] = \\ ;\n assign douta[197] = \\ ;\n assign douta[196] = \\ ;\n assign douta[195] = \\ ;\n assign douta[194] = \\ ;\n assign douta[193] = \\ ;\n assign douta[192] = \\ ;\n assign douta[191] = \\ ;\n assign douta[190] = \\ ;\n assign douta[189] = \\ ;\n assign douta[188] = \\ ;\n assign douta[187] = \\ ;\n assign douta[186] = \\ ;\n assign douta[185] = \\ ;\n assign douta[184] = \\ ;\n assign douta[183] = \\ ;\n assign douta[182] = \\ ;\n assign douta[181] = \\ ;\n assign douta[180] = \\ ;\n assign douta[179] = \\ ;\n assign douta[178] = \\ ;\n assign douta[177] = \\ ;\n assign douta[176] = \\ ;\n assign douta[175] = \\ ;\n assign douta[174] = \\ ;\n assign douta[173] = \\ ;\n assign douta[172] = \\ ;\n assign douta[171] = \\ ;\n assign douta[170] = \\ ;\n assign douta[169] = \\ ;\n assign douta[168] = \\ ;\n assign douta[167] = \\ ;\n assign douta[166] = \\ ;\n assign douta[165] = \\ ;\n assign douta[164] = \\ ;\n assign douta[163] = \\ ;\n assign douta[162] = \\ ;\n assign douta[161] = \\ ;\n assign douta[160] = \\ ;\n assign douta[159] = \\ ;\n assign douta[158] = \\ ;\n assign douta[157] = \\ ;\n assign douta[156] = \\ ;\n assign douta[155] = \\ ;\n assign douta[154] = \\ ;\n assign douta[153] = \\ ;\n assign douta[152] = \\ ;\n assign douta[151] = \\ ;\n assign douta[150] = \\ ;\n assign douta[149] = \\ ;\n assign douta[148] = \\ ;\n assign douta[147] = \\ ;\n assign douta[146] = \\ ;\n assign douta[145] = \\ ;\n assign douta[144] = \\ ;\n assign douta[143] = \\ ;\n assign douta[142] = \\ ;\n assign douta[141] = \\ ;\n assign douta[140] = \\ ;\n assign douta[139] = \\ ;\n assign douta[138] = \\ ;\n assign douta[137] = \\ ;\n assign douta[136] = \\ ;\n assign douta[135] = \\ ;\n assign douta[134] = \\ ;\n assign douta[133] = \\ ;\n assign douta[132] = \\ ;\n assign douta[131] = \\ ;\n assign douta[130] = \\ ;\n assign douta[129] = \\ ;\n assign douta[128] = \\ ;\n assign douta[127] = \\ ;\n assign douta[126] = \\ ;\n assign douta[125] = \\ ;\n assign douta[124] = \\ ;\n assign douta[123] = \\ ;\n assign douta[122] = \\ ;\n assign douta[121] = \\ ;\n assign douta[120] = \\ ;\n assign douta[119] = \\ ;\n assign douta[118] = \\ ;\n assign douta[117] = \\ ;\n assign douta[116] = \\ ;\n assign douta[115] = \\ ;\n assign douta[114] = \\ ;\n assign douta[113] = \\ ;\n assign douta[112] = \\ ;\n assign douta[111] = \\ ;\n assign douta[110] = \\ ;\n assign douta[109] = \\ ;\n assign douta[108] = \\ ;\n assign douta[107] = \\ ;\n assign douta[106] = \\ ;\n assign douta[105] = \\ ;\n assign douta[104] = \\ ;\n assign douta[103] = \\ ;\n assign douta[102] = \\ ;\n assign douta[101] = \\ ;\n assign douta[100] = \\ ;\n assign douta[99] = \\ ;\n assign douta[98] = \\ ;\n assign douta[97] = \\ ;\n assign douta[96] = \\ ;\n assign douta[95] = \\ ;\n assign douta[94] = \\ ;\n assign douta[93] = \\ ;\n assign douta[92] = \\ ;\n assign douta[91] = \\ ;\n assign douta[90] = \\ ;\n assign douta[89] = \\ ;\n assign douta[88] = \\ ;\n assign douta[87] = \\ ;\n assign douta[86] = \\ ;\n assign douta[85] = \\ ;\n assign douta[84] = \\ ;\n assign douta[83] = \\ ;\n assign douta[82] = \\ ;\n assign douta[81] = \\ ;\n assign douta[80] = \\ ;\n assign douta[79] = \\ ;\n assign douta[78] = \\ ;\n assign douta[77] = \\ ;\n assign douta[76] = \\ ;\n assign douta[75] = \\ ;\n assign douta[74] = \\ ;\n assign douta[73] = \\ ;\n assign douta[72] = \\ ;\n assign douta[71] = \\ ;\n assign douta[70] = \\ ;\n assign douta[69] = \\ ;\n assign douta[68] = \\ ;\n assign douta[67] = \\ ;\n assign douta[66] = \\ ;\n assign douta[65] = \\ ;\n assign douta[64] = \\ ;\n assign douta[63] = \\ ;\n assign douta[62] = \\ ;\n assign douta[61] = \\ ;\n assign douta[60] = \\ ;\n assign douta[59] = \\ ;\n assign douta[58] = \\ ;\n assign douta[57] = \\ ;\n assign douta[56] = \\ ;\n assign douta[55] = \\ ;\n assign douta[54] = \\ ;\n assign douta[53] = \\ ;\n assign douta[52] = \\ ;\n assign douta[51] = \\ ;\n assign douta[50] = \\ ;\n assign douta[49] = \\ ;\n assign douta[48] = \\ ;\n assign douta[47] = \\ ;\n assign douta[46] = \\ ;\n assign douta[45] = \\ ;\n assign douta[44] = \\ ;\n assign douta[43] = \\ ;\n assign douta[42] = \\ ;\n assign douta[41] = \\ ;\n assign douta[40] = \\ ;\n assign douta[39] = \\ ;\n assign douta[38] = \\ ;\n assign douta[37] = \\ ;\n assign douta[36] = \\ ;\n assign douta[35] = \\ ;\n assign douta[34] = \\ ;\n assign douta[33] = \\ ;\n assign douta[32] = \\ ;\n assign douta[31] = \\ ;\n assign douta[30] = \\ ;\n assign douta[29] = \\ ;\n assign douta[28] = \\ ;\n assign douta[27] = \\ ;\n assign douta[26] = \\ ;\n assign douta[25] = \\ ;\n assign douta[24] = \\ ;\n assign douta[23] = \\ ;\n assign douta[22] = \\ ;\n assign douta[21] = \\ ;\n assign douta[20] = \\ ;\n assign douta[19] = \\ ;\n assign douta[18] = \\ ;\n assign douta[17] = \\ ;\n assign douta[16] = \\ ;\n assign douta[15] = \\ ;\n assign douta[14] = \\ ;\n assign douta[13] = \\ ;\n assign douta[12] = \\ ;\n assign douta[11] = \\ ;\n assign douta[10] = \\ ;\n assign douta[9] = \\ ;\n assign douta[8] = \\ ;\n assign douta[7] = \\ ;\n assign douta[6] = \\ ;\n assign douta[5] = \\ ;\n assign douta[4] = \\ ;\n assign douta[3] = \\ ;\n assign douta[2] = \\ ;\n assign douta[1] = \\ ;\n assign douta[0] = \\ ;\n assign rdaddrecc[11] = \\ ;\n assign rdaddrecc[10] = \\ ;\n assign rdaddrecc[9] = \\ ;\n assign rdaddrecc[8] = \\ ;\n assign rdaddrecc[7] = \\ ;\n assign rdaddrecc[6] = \\ ;\n assign rdaddrecc[5] = \\ ;\n assign rdaddrecc[4] = \\ ;\n assign rdaddrecc[3] = \\ ;\n assign rdaddrecc[2] = \\ ;\n assign rdaddrecc[1] = \\ ;\n assign rdaddrecc[0] = \\ ;\n assign rsta_busy = \\ ;\n assign rstb_busy = \\ ;\n assign s_axi_arready = \\ ;\n assign s_axi_awready = \\ ;\n assign s_axi_bid[3] = \\ ;\n assign s_axi_bid[2] = \\ ;\n assign s_axi_bid[1] = \\ ;\n assign s_axi_bid[0] = \\ ;\n assign s_axi_bresp[1] = \\ ;\n assign s_axi_bresp[0] = \\ ;\n assign s_axi_bvalid = \\ ;\n assign s_axi_dbiterr = \\ ;\n assign s_axi_rdaddrecc[11] = \\ ;\n assign s_axi_rdaddrecc[10] = \\ ;\n assign s_axi_rdaddrecc[9] = \\ ;\n assign s_axi_rdaddrecc[8] = \\ ;\n assign s_axi_rdaddrecc[7] = \\ ;\n assign s_axi_rdaddrecc[6] = \\ ;\n assign s_axi_rdaddrecc[5] = \\ ;\n assign s_axi_rdaddrecc[4] = \\ ;\n assign s_axi_rdaddrecc[3] = \\ ;\n assign s_axi_rdaddrecc[2] = \\ ;\n assign s_axi_rdaddrecc[1] = \\ ;\n assign s_axi_rdaddrecc[0] = \\ ;\n assign s_axi_rdata[63] = \\ ;\n assign s_axi_rdata[62] = \\ ;\n assign s_axi_rdata[61] = \\ ;\n assign s_axi_rdata[60] = \\ ;\n assign s_axi_rdata[59] = \\ ;\n assign s_axi_rdata[58] = \\ ;\n assign s_axi_rdata[57] = \\ ;\n assign s_axi_rdata[56] = \\ ;\n assign s_axi_rdata[55] = \\ ;\n assign s_axi_rdata[54] = \\ ;\n assign s_axi_rdata[53] = \\ ;\n assign s_axi_rdata[52] = \\ ;\n assign s_axi_rdata[51] = \\ ;\n assign s_axi_rdata[50] = \\ ;\n assign s_axi_rdata[49] = \\ ;\n assign s_axi_rdata[48] = \\ ;\n assign s_axi_rdata[47] = \\ ;\n assign s_axi_rdata[46] = \\ ;\n assign s_axi_rdata[45] = \\ ;\n assign s_axi_rdata[44] = \\ ;\n assign s_axi_rdata[43] = \\ ;\n assign s_axi_rdata[42] = \\ ;\n assign s_axi_rdata[41] = \\ ;\n assign s_axi_rdata[40] = \\ ;\n assign s_axi_rdata[39] = \\ ;\n assign s_axi_rdata[38] = \\ ;\n assign s_axi_rdata[37] = \\ ;\n assign s_axi_rdata[36] = \\ ;\n assign s_axi_rdata[35] = \\ ;\n assign s_axi_rdata[34] = \\ ;\n assign s_axi_rdata[33] = \\ ;\n assign s_axi_rdata[32] = \\ ;\n assign s_axi_rdata[31] = \\ ;\n assign s_axi_rdata[30] = \\ ;\n assign s_axi_rdata[29] = \\ ;\n assign s_axi_rdata[28] = \\ ;\n assign s_axi_rdata[27] = \\ ;\n assign s_axi_rdata[26] = \\ ;\n assign s_axi_rdata[25] = \\ ;\n assign s_axi_rdata[24] = \\ ;\n assign s_axi_rdata[23] = \\ ;\n assign s_axi_rdata[22] = \\ ;\n assign s_axi_rdata[21] = \\ ;\n assign s_axi_rdata[20] = \\ ;\n assign s_axi_rdata[19] = \\ ;\n assign s_axi_rdata[18] = \\ ;\n assign s_axi_rdata[17] = \\ ;\n assign s_axi_rdata[16] = \\ ;\n assign s_axi_rdata[15] = \\ ;\n assign s_axi_rdata[14] = \\ ;\n assign s_axi_rdata[13] = \\ ;\n assign s_axi_rdata[12] = \\ ;\n assign s_axi_rdata[11] = \\ ;\n assign s_axi_rdata[10] = \\ ;\n assign s_axi_rdata[9] = \\ ;\n assign s_axi_rdata[8] = \\ ;\n assign s_axi_rdata[7] = \\ ;\n assign s_axi_rdata[6] = \\ ;\n assign s_axi_rdata[5] = \\ ;\n assign s_axi_rdata[4] = \\ ;\n assign s_axi_rdata[3] = \\ ;\n assign s_axi_rdata[2] = \\ ;\n assign s_axi_rdata[1] = \\ ;\n assign s_axi_rdata[0] = \\ ;\n assign s_axi_rid[3] = \\ ;\n assign s_axi_rid[2] = \\ ;\n assign s_axi_rid[1] = \\ ;\n assign s_axi_rid[0] = \\ ;\n assign s_axi_rlast = \\ ;\n assign s_axi_rresp[1] = \\ ;\n assign s_axi_rresp[0] = \\ ;\n assign s_axi_rvalid = \\ ;\n assign s_axi_sbiterr = \\ ;\n assign s_axi_wready = \\ ;\n assign sbiterr = \\ ;\n GND GND\n (.G(\\ ));\n output_line_buffer_blk_mem_gen_v8_3_4_synth inst_blk_mem_gen\n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n\n(* ORIG_REF_NAME = \"blk_mem_gen_v8_3_4_synth\" *) \nmodule output_line_buffer_blk_mem_gen_v8_3_4_synth\n (doutb,\n clka,\n clkb,\n ena,\n addra,\n addrb,\n dina,\n wea);\n output [63:0]doutb;\n input clka;\n input clkb;\n input ena;\n input [9:0]addra;\n input [11:0]addrb;\n input [255:0]dina;\n input [0:0]wea;\n\n wire [9:0]addra;\n wire [11:0]addrb;\n wire clka;\n wire clkb;\n wire [255:0]dina;\n wire [63:0]doutb;\n wire ena;\n wire [0:0]wea;\n\n output_line_buffer_blk_mem_gen_top \\gnbram.gnativebmg.native_blk_mem_gen \n (.addra(addra),\n .addrb(addrb),\n .clka(clka),\n .clkb(clkb),\n .dina(dina),\n .doutb(doutb),\n .ena(ena),\n .wea(wea));\nendmodule\n`ifndef GLBL\n`define GLBL\n`timescale 1 ps / 1 ps\n\nmodule glbl ();\n\n parameter ROC_WIDTH = 100000;\n parameter TOC_WIDTH = 0;\n\n//-------- STARTUP Globals --------------\n wire GSR;\n wire GTS;\n wire GWE;\n wire PRLD;\n tri1 p_up_tmp;\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n\n wire PROGB_GLBL;\n wire CCLKO_GLBL;\n wire FCSBO_GLBL;\n wire [3:0] DO_GLBL;\n wire [3:0] DI_GLBL;\n \n reg GSR_int;\n reg GTS_int;\n reg PRLD_int;\n\n//-------- JTAG Globals --------------\n wire JTAG_TDO_GLBL;\n wire JTAG_TCK_GLBL;\n wire JTAG_TDI_GLBL;\n wire JTAG_TMS_GLBL;\n wire JTAG_TRST_GLBL;\n\n reg JTAG_CAPTURE_GLBL;\n reg JTAG_RESET_GLBL;\n reg JTAG_SHIFT_GLBL;\n reg JTAG_UPDATE_GLBL;\n reg JTAG_RUNTEST_GLBL;\n\n reg JTAG_SEL1_GLBL = 0;\n reg JTAG_SEL2_GLBL = 0 ;\n reg JTAG_SEL3_GLBL = 0;\n reg JTAG_SEL4_GLBL = 0;\n\n reg JTAG_USER_TDO1_GLBL = 1'bz;\n reg JTAG_USER_TDO2_GLBL = 1'bz;\n reg JTAG_USER_TDO3_GLBL = 1'bz;\n reg JTAG_USER_TDO4_GLBL = 1'bz;\n\n assign (weak1, weak0) GSR = GSR_int;\n assign (weak1, weak0) GTS = GTS_int;\n assign (weak1, weak0) PRLD = PRLD_int;\n\n initial begin\n\tGSR_int = 1'b1;\n\tPRLD_int = 1'b1;\n\t#(ROC_WIDTH)\n\tGSR_int = 1'b0;\n\tPRLD_int = 1'b0;\n end\n\n initial begin\n\tGTS_int = 1'b1;\n\t#(TOC_WIDTH)\n\tGTS_int = 1'b0;\n end\n\nendmodule\n`endif\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_stub.v", "content": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// --------------------------------------------------------------------------------\n// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016\n// Date : Tue Nov 15 09:42:01 2016\n// Host : david-desktop-arch running 64-bit unknown\n// Command : write_verilog -force -mode synth_stub\n// /home/dave/ip/examples/framebuffer_test/framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/output_line_buffer_stub.v\n// Design : output_line_buffer\n// Purpose : Stub declaration of top-level module interface\n// Device : xc7k325tffg900-2\n// --------------------------------------------------------------------------------\n\n// This empty module with port declaration file causes synthesis tools to infer a black box for IP.\n// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.\n// Please paste the declaration into a Verilog source file or add the file as an additional source.\n(* x_core_info = \"blk_mem_gen_v8_3_4,Vivado 2016.3\" *)\nmodule output_line_buffer(clka, ena, wea, addra, dina, clkb, addrb, doutb)\n/* synthesis syn_black_box black_box_pad_pin=\"clka,ena,wea[0:0],addra[9:0],dina[255:0],clkb,addrb[11:0],doutb[63:0]\" */;\n input clka;\n input ena;\n input [0:0]wea;\n input [9:0]addra;\n input [255:0]dina;\n input clkb;\n input [11:0]addrb;\n output [63:0]doutb;\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/output_line_buffer_1/sim/output_line_buffer.v", "content": "// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n// DO NOT MODIFY THIS FILE.\n\n\n// IP VLNV: xilinx.com:ip:blk_mem_gen:8.3\n// IP Revision: 4\n\n`timescale 1ns/1ps\n\n(* DowngradeIPIdentifiedWarnings = \"yes\" *)\nmodule output_line_buffer (\n clka,\n ena,\n wea,\n addra,\n dina,\n clkb,\n addrb,\n doutb\n);\n\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA CLK\" *)\ninput wire clka;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA EN\" *)\ninput wire ena;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA WE\" *)\ninput wire [0 : 0] wea;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR\" *)\ninput wire [9 : 0] addra;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTA DIN\" *)\ninput wire [255 : 0] dina;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB CLK\" *)\ninput wire clkb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR\" *)\ninput wire [11 : 0] addrb;\n(* X_INTERFACE_INFO = \"xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT\" *)\noutput wire [63 : 0] doutb;\n\n blk_mem_gen_v8_3_4 #(\n .C_FAMILY(\"kintex7\"),\n .C_XDEVICEFAMILY(\"kintex7\"),\n .C_ELABORATION_DIR(\"./\"),\n .C_INTERFACE_TYPE(0),\n .C_AXI_TYPE(1),\n .C_AXI_SLAVE_TYPE(0),\n .C_USE_BRAM_BLOCK(0),\n .C_ENABLE_32BIT_ADDRESS(0),\n .C_CTRL_ECC_ALGO(\"NONE\"),\n .C_HAS_AXI_ID(0),\n .C_AXI_ID_WIDTH(4),\n .C_MEM_TYPE(1),\n .C_BYTE_SIZE(9),\n .C_ALGORITHM(1),\n .C_PRIM_TYPE(1),\n .C_LOAD_INIT_FILE(0),\n .C_INIT_FILE_NAME(\"no_coe_file_loaded\"),\n .C_INIT_FILE(\"output_line_buffer.mem\"),\n .C_USE_DEFAULT_DATA(0),\n .C_DEFAULT_DATA(\"0\"),\n .C_HAS_RSTA(0),\n .C_RST_PRIORITY_A(\"CE\"),\n .C_RSTRAM_A(0),\n .C_INITA_VAL(\"0\"),\n .C_HAS_ENA(1),\n .C_HAS_REGCEA(0),\n .C_USE_BYTE_WEA(0),\n .C_WEA_WIDTH(1),\n .C_WRITE_MODE_A(\"NO_CHANGE\"),\n .C_WRITE_WIDTH_A(256),\n .C_READ_WIDTH_A(256),\n .C_WRITE_DEPTH_A(1024),\n .C_READ_DEPTH_A(1024),\n .C_ADDRA_WIDTH(10),\n .C_HAS_RSTB(0),\n .C_RST_PRIORITY_B(\"CE\"),\n .C_RSTRAM_B(0),\n .C_INITB_VAL(\"0\"),\n .C_HAS_ENB(0),\n .C_HAS_REGCEB(0),\n .C_USE_BYTE_WEB(0),\n .C_WEB_WIDTH(1),\n .C_WRITE_MODE_B(\"WRITE_FIRST\"),\n .C_WRITE_WIDTH_B(64),\n .C_READ_WIDTH_B(64),\n .C_WRITE_DEPTH_B(4096),\n .C_READ_DEPTH_B(4096),\n .C_ADDRB_WIDTH(12),\n .C_HAS_MEM_OUTPUT_REGS_A(0),\n .C_HAS_MEM_OUTPUT_REGS_B(0),\n .C_HAS_MUX_OUTPUT_REGS_A(0),\n .C_HAS_MUX_OUTPUT_REGS_B(0),\n .C_MUX_PIPELINE_STAGES(0),\n .C_HAS_SOFTECC_INPUT_REGS_A(0),\n .C_HAS_SOFTECC_OUTPUT_REGS_B(0),\n .C_USE_SOFTECC(0),\n .C_USE_ECC(0),\n .C_EN_ECC_PIPE(0),\n .C_HAS_INJECTERR(0),\n .C_SIM_COLLISION_CHECK(\"ALL\"),\n .C_COMMON_CLK(0),\n .C_DISABLE_WARN_BHV_COLL(0),\n .C_EN_SLEEP_PIN(0),\n .C_USE_URAM(0),\n .C_EN_RDADDRA_CHG(0),\n .C_EN_RDADDRB_CHG(0),\n .C_EN_DEEPSLEEP_PIN(0),\n .C_EN_SHUTDOWN_PIN(0),\n .C_EN_SAFETY_CKT(0),\n .C_DISABLE_WARN_BHV_RANGE(0),\n .C_COUNT_36K_BRAM(\"7\"),\n .C_COUNT_18K_BRAM(\"1\"),\n .C_EST_POWER_SUMMARY(\"Estimated Power for IP : 33.580152 mW\")\n ) inst (\n .clka(clka),\n .rsta(1'D0),\n .ena(ena),\n .regcea(1'D0),\n .wea(wea),\n .addra(addra),\n .dina(dina),\n .douta(),\n .clkb(clkb),\n .rstb(1'D0),\n .enb(1'D0),\n .regceb(1'D0),\n .web(1'B0),\n .addrb(addrb),\n .dinb(64'B0),\n .doutb(doutb),\n .injectsbiterr(1'D0),\n .injectdbiterr(1'D0),\n .eccpipece(1'D0),\n .sbiterr(),\n .dbiterr(),\n .rdaddrecc(),\n .sleep(1'D0),\n .deepsleep(1'D0),\n .shutdown(1'D0),\n .rsta_busy(),\n .rstb_busy(),\n .s_aclk(1'H0),\n .s_aresetn(1'D0),\n .s_axi_awid(4'B0),\n .s_axi_awaddr(32'B0),\n .s_axi_awlen(8'B0),\n .s_axi_awsize(3'B0),\n .s_axi_awburst(2'B0),\n .s_axi_awvalid(1'D0),\n .s_axi_awready(),\n .s_axi_wdata(256'B0),\n .s_axi_wstrb(1'B0),\n .s_axi_wlast(1'D0),\n .s_axi_wvalid(1'D0),\n .s_axi_wready(),\n .s_axi_bid(),\n .s_axi_bresp(),\n .s_axi_bvalid(),\n .s_axi_bready(1'D0),\n .s_axi_arid(4'B0),\n .s_axi_araddr(32'B0),\n .s_axi_arlen(8'B0),\n .s_axi_arsize(3'B0),\n .s_axi_arburst(2'B0),\n .s_axi_arvalid(1'D0),\n .s_axi_arready(),\n .s_axi_rid(),\n .s_axi_rdata(),\n .s_axi_rresp(),\n .s_axi_rlast(),\n .s_axi_rvalid(),\n .s_axi_rready(1'D0),\n .s_axi_injectsbiterr(1'D0),\n .s_axi_injectdbiterr(1'D0),\n .s_axi_sbiterr(),\n .s_axi_dbiterr(),\n .s_axi_rdaddrecc()\n );\nendmodule\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/output_line_buffer_1/simulation/blk_mem_gen_v8_3.v", "content": "/******************************************************************************\n-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.\n--\n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n--\n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n--\n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n--\n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n--\n *****************************************************************************\n *\n * Filename: blk_mem_gen_v8_3_4.v\n *\n * Description:\n * This file is the Verilog behvarial model for the\n * Block Memory Generator Core.\n *\n *****************************************************************************\n * Author: Xilinx\n *\n * History: Jan 11, 2006 Initial revision\n * Jun 11, 2007 Added independent register stages for \n * Port A and Port B (IP1_Jm/v2.5)\n * Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)\n * Mar 13, 2008 Behavioral model optimizations\n * April 07, 2009 : Added support for Spartan-6 and Virtex-6\n * features, including the following:\n * (i) error injection, detection and/or correction\n * (ii) reset priority\n * (iii) special reset behavior\n * \n *****************************************************************************/\n`timescale 1ps/1ps\n\nmodule STATE_LOGIC_v8_3 (O, I0, I1, I2, I3, I4, I5);\n\n parameter INIT = 64'h0000000000000000;\n\n input I0, I1, I2, I3, I4, I5;\n\n output O;\n\n reg O;\n reg tmp;\n\n always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin\n \n tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5;\n\n if ( tmp == 0 || tmp == 1)\n\n O = INIT[{I5, I4, I3, I2, I1, I0}];\n\n end\nendmodule\n\nmodule beh_vlog_muxf7_v8_3 (O, I0, I1, S);\n\n output O;\n reg O;\n\n input I0, I1, S;\n\n\talways @(I0 or I1 or S) \n\t if (S)\n\t\tO = I1;\n\t else\n\t\tO = I0;\nendmodule\n\nmodule beh_vlog_ff_clr_v8_3 (Q, C, CLR, D);\n parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n output Q;\n\n input C, CLR, D;\n\n reg Q;\n\n initial Q= 1'b0;\n\n always @(posedge C )\n if (CLR)\n\tQ<= 1'b0;\n else\n\tQ<= #FLOP_DELAY D;\n\n\nendmodule\n\nmodule beh_vlog_ff_pre_v8_3 (Q, C, D, PRE);\n\n parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n output Q;\n input C, D, PRE;\n\n reg Q;\n\n initial Q= 1'b0;\n\n always @(posedge C )\n if (PRE)\n Q <= 1'b1;\n else\n\t Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule beh_vlog_ff_ce_clr_v8_3 (Q, C, CE, CLR, D);\n\n parameter INIT = 0;\nlocalparam FLOP_DELAY = 100;\n output Q;\n input C, CE, CLR, D;\n\n reg Q;\n\n initial Q= 1'b0;\n always @(posedge C )\n if (CLR)\n Q <= 1'b0;\n else if (CE)\n\t Q <= #FLOP_DELAY D;\n\nendmodule\n\nmodule write_netlist_v8_3\n#(\n parameter\t C_AXI_TYPE = 0\n )\n (\n S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,\n w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,\n S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c \n );\n\n input S_ACLK;\n input S_ARESETN;\n input S_AXI_AWVALID;\n input S_AXI_WVALID;\n input S_AXI_BREADY;\n input w_last_c;\n input bready_timeout_c;\n output aw_ready_r;\n output S_AXI_WREADY;\n output S_AXI_BVALID;\n output S_AXI_WR_EN;\n output addr_en_c;\n output incr_addr_c;\n output bvalid_c;\n //-------------------------------------------------------------------------\n //AXI LITE\n //-------------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm\n wire w_ready_r_7;\n wire w_ready_c;\n wire aw_ready_c;\n wire NlwRenamedSignal_bvalid_c;\n wire NlwRenamedSignal_incr_addr_c;\n wire present_state_FSM_FFd3_13;\n wire present_state_FSM_FFd2_14;\n wire present_state_FSM_FFd1_15;\n wire present_state_FSM_FFd4_16;\n wire present_state_FSM_FFd4_In;\n wire present_state_FSM_FFd3_In;\n wire present_state_FSM_FFd2_In;\n wire present_state_FSM_FFd1_In;\n wire present_state_FSM_FFd4_In1_21;\n wire [0:0] Mmux_aw_ready_c ; \nbegin\n assign\n S_AXI_WREADY = w_ready_r_7,\n S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,\n S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,\n incr_addr_c = NlwRenamedSignal_incr_addr_c,\n bvalid_c = NlwRenamedSignal_bvalid_c;\n\n assign NlwRenamedSignal_incr_addr_c = 1'b0;\n\n beh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n aw_ready_r_2 (\n .C ( S_ACLK), \n .CLR ( S_ARESETN), \n .D ( aw_ready_c), \n .Q ( aw_ready_r)\n );\n beh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n w_ready_r (\n .C ( S_ACLK), \n .CLR ( S_ARESETN), \n .D ( w_ready_c), \n .Q ( w_ready_r_7)\n );\n beh_vlog_ff_pre_v8_3 #(\n .INIT (1'b1))\n present_state_FSM_FFd4 (\n .C ( S_ACLK), \n .D ( present_state_FSM_FFd4_In), \n .PRE ( S_ARESETN), \n .Q ( present_state_FSM_FFd4_16)\n );\n beh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n present_state_FSM_FFd3 (\n .C ( S_ACLK), \n .CLR ( S_ARESETN), \n .D ( present_state_FSM_FFd3_In), \n .Q ( present_state_FSM_FFd3_13)\n );\n beh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n present_state_FSM_FFd2 (\n .C ( S_ACLK), \n .CLR ( S_ARESETN), \n .D ( present_state_FSM_FFd2_In), \n .Q ( present_state_FSM_FFd2_14)\n );\nbeh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n present_state_FSM_FFd1 (\n .C ( S_ACLK), \n .CLR ( S_ARESETN), \n .D ( present_state_FSM_FFd1_In), \n .Q ( present_state_FSM_FFd1_15)\n );\nSTATE_LOGIC_v8_3 #(\n .INIT (64'h0000000055554440))\n present_state_FSM_FFd3_In1 (\n .I0 ( S_AXI_WVALID), \n .I1 ( S_AXI_AWVALID), \n .I2 ( present_state_FSM_FFd2_14), \n .I3 ( present_state_FSM_FFd4_16), \n .I4 ( present_state_FSM_FFd3_13), \n .I5 (1'b0), \n .O ( present_state_FSM_FFd3_In)\n );\nSTATE_LOGIC_v8_3 #(\n .INIT (64'h0000000088880800))\n present_state_FSM_FFd2_In1 (\n .I0 ( S_AXI_AWVALID), \n .I1 ( S_AXI_WVALID), \n .I2 ( bready_timeout_c), \n .I3 ( present_state_FSM_FFd2_14), \n .I4 ( present_state_FSM_FFd4_16), \n .I5 (1'b0), \n .O ( present_state_FSM_FFd2_In)\n );\nSTATE_LOGIC_v8_3 #(\n .INIT (64'h00000000AAAA2000))\n Mmux_addr_en_c_0_1 (\n .I0 ( S_AXI_AWVALID), \n .I1 ( bready_timeout_c), \n .I2 ( present_state_FSM_FFd2_14), \n .I3 ( S_AXI_WVALID), \n .I4 ( present_state_FSM_FFd4_16), \n .I5 (1'b0), \n .O ( addr_en_c)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'hF5F07570F5F05500))\n Mmux_w_ready_c_0_1 (\n .I0 ( S_AXI_WVALID), \n .I1 ( bready_timeout_c), \n .I2 ( S_AXI_AWVALID), \n .I3 ( present_state_FSM_FFd3_13), \n .I4 ( present_state_FSM_FFd4_16), \n .I5 ( present_state_FSM_FFd2_14), \n .O ( w_ready_c)\n );\nSTATE_LOGIC_v8_3 #(\n .INIT (64'h88808880FFFF8880))\n present_state_FSM_FFd1_In1 (\n .I0 ( S_AXI_WVALID), \n .I1 ( bready_timeout_c), \n .I2 ( present_state_FSM_FFd3_13), \n .I3 ( present_state_FSM_FFd2_14), \n .I4 ( present_state_FSM_FFd1_15), \n .I5 ( S_AXI_BREADY), \n .O ( present_state_FSM_FFd1_In)\n );\nSTATE_LOGIC_v8_3 #(\n .INIT (64'h00000000000000A8))\n Mmux_S_AXI_WR_EN_0_1 (\n .I0 ( S_AXI_WVALID), \n .I1 ( present_state_FSM_FFd2_14), \n .I2 ( present_state_FSM_FFd3_13), \n .I3 (1'b0), \n .I4 (1'b0), \n .I5 (1'b0), \n .O ( NlwRenamedSignal_bvalid_c)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h2F0F27072F0F2200))\n present_state_FSM_FFd4_In1 (\n .I0 ( S_AXI_WVALID), \n .I1 ( bready_timeout_c), \n .I2 ( S_AXI_AWVALID), \n .I3 ( present_state_FSM_FFd3_13), \n .I4 ( present_state_FSM_FFd4_16), \n .I5 ( present_state_FSM_FFd2_14), \n .O ( present_state_FSM_FFd4_In1_21)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h00000000000000F8))\n present_state_FSM_FFd4_In2 ( \n .I0 ( present_state_FSM_FFd1_15), \n .I1 ( S_AXI_BREADY), \n .I2 ( present_state_FSM_FFd4_In1_21), \n .I3 (1'b0), \n .I4 (1'b0), \n .I5 (1'b0), \n .O ( present_state_FSM_FFd4_In)\n );\nSTATE_LOGIC_v8_3 #(\n .INIT (64'h7535753575305500))\n Mmux_aw_ready_c_0_1 ( \n .I0 ( S_AXI_AWVALID), \n .I1 ( bready_timeout_c), \n .I2 ( S_AXI_WVALID), \n .I3 ( present_state_FSM_FFd4_16), \n .I4 ( present_state_FSM_FFd3_13), \n .I5 ( present_state_FSM_FFd2_14), \n .O ( Mmux_aw_ready_c[0])\n );\nSTATE_LOGIC_v8_3 #(\n .INIT (64'h00000000000000F8))\n Mmux_aw_ready_c_0_2 (\n .I0 ( present_state_FSM_FFd1_15), \n .I1 ( S_AXI_BREADY), \n .I2 ( Mmux_aw_ready_c[0]), \n .I3 (1'b0), \n .I4 (1'b0), \n .I5 (1'b0), \n .O ( aw_ready_c)\n );\nend \nend \nendgenerate\n\n //---------------------------------------------------------------------\n // AXI FULL\n //---------------------------------------------------------------------\ngenerate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm\n wire w_ready_r_8; \n wire w_ready_c; \n wire aw_ready_c; \n wire NlwRenamedSig_OI_bvalid_c; \n wire present_state_FSM_FFd1_16; \n wire present_state_FSM_FFd4_17; \n wire present_state_FSM_FFd3_18; \n wire present_state_FSM_FFd2_19; \n wire present_state_FSM_FFd4_In; \n wire present_state_FSM_FFd3_In; \n wire present_state_FSM_FFd2_In; \n wire present_state_FSM_FFd1_In; \n wire present_state_FSM_FFd2_In1_24; \n wire present_state_FSM_FFd4_In1_25; \n wire N2; \n wire N4; \nbegin\nassign\n S_AXI_WREADY = w_ready_r_8,\n bvalid_c = NlwRenamedSig_OI_bvalid_c,\n S_AXI_BVALID = 1'b0;\n\nbeh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n aw_ready_r_2\n (\n .C ( S_ACLK),\n .CLR ( S_ARESETN),\n .D ( aw_ready_c),\n .Q ( aw_ready_r)\n );\nbeh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n w_ready_r\n (\n .C ( S_ACLK),\n .CLR ( S_ARESETN),\n .D ( w_ready_c),\n .Q ( w_ready_r_8)\n );\n beh_vlog_ff_pre_v8_3 #(\n .INIT (1'b1))\n present_state_FSM_FFd4\n (\n .C ( S_ACLK),\n .D ( present_state_FSM_FFd4_In),\n .PRE ( S_ARESETN),\n .Q ( present_state_FSM_FFd4_17)\n );\nbeh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n present_state_FSM_FFd3\n (\n .C ( S_ACLK),\n .CLR ( S_ARESETN),\n .D ( present_state_FSM_FFd3_In),\n .Q ( present_state_FSM_FFd3_18)\n );\nbeh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n present_state_FSM_FFd2\n (\n .C ( S_ACLK),\n .CLR ( S_ARESETN),\n .D ( present_state_FSM_FFd2_In),\n .Q ( present_state_FSM_FFd2_19)\n );\n beh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n present_state_FSM_FFd1\n (\n .C ( S_ACLK),\n .CLR ( S_ARESETN),\n .D ( present_state_FSM_FFd1_In),\n .Q ( present_state_FSM_FFd1_16)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000000005540))\n present_state_FSM_FFd3_In1\n (\n .I0 ( S_AXI_WVALID),\n .I1 ( present_state_FSM_FFd4_17),\n .I2 ( S_AXI_AWVALID),\n .I3 ( present_state_FSM_FFd3_18),\n .I4 (1'b0),\n .I5 (1'b0),\n .O ( present_state_FSM_FFd3_In)\n );\nSTATE_LOGIC_v8_3 #(\n .INIT (64'hBF3FBB33AF0FAA00))\n Mmux_aw_ready_c_0_2\n (\n .I0 ( S_AXI_BREADY),\n .I1 ( bready_timeout_c),\n .I2 ( S_AXI_AWVALID),\n .I3 ( present_state_FSM_FFd1_16),\n .I4 ( present_state_FSM_FFd4_17),\n .I5 ( NlwRenamedSig_OI_bvalid_c),\n .O ( aw_ready_c)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'hAAAAAAAA20000000))\n Mmux_addr_en_c_0_1\n (\n .I0 ( S_AXI_AWVALID),\n .I1 ( bready_timeout_c),\n .I2 ( present_state_FSM_FFd2_19),\n .I3 ( S_AXI_WVALID),\n .I4 ( w_last_c),\n .I5 ( present_state_FSM_FFd4_17),\n .O ( addr_en_c)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h00000000000000A8))\n Mmux_S_AXI_WR_EN_0_1\n (\n .I0 ( S_AXI_WVALID),\n .I1 ( present_state_FSM_FFd2_19),\n .I2 ( present_state_FSM_FFd3_18),\n .I3 (1'b0),\n .I4 (1'b0),\n .I5 (1'b0),\n .O ( S_AXI_WR_EN)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000000002220))\n Mmux_incr_addr_c_0_1\n (\n .I0 ( S_AXI_WVALID),\n .I1 ( w_last_c),\n .I2 ( present_state_FSM_FFd2_19),\n .I3 ( present_state_FSM_FFd3_18),\n .I4 (1'b0),\n .I5 (1'b0),\n .O ( incr_addr_c)\n );\nSTATE_LOGIC_v8_3 #(\n .INIT (64'h0000000000008880))\n Mmux_aw_ready_c_0_11\n (\n .I0 ( S_AXI_WVALID),\n .I1 ( w_last_c),\n .I2 ( present_state_FSM_FFd2_19),\n .I3 ( present_state_FSM_FFd3_18),\n .I4 (1'b0),\n .I5 (1'b0),\n .O ( NlwRenamedSig_OI_bvalid_c)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h000000000000D5C0))\n present_state_FSM_FFd2_In1\n (\n .I0 ( w_last_c),\n .I1 ( S_AXI_AWVALID),\n .I2 ( present_state_FSM_FFd4_17),\n .I3 ( present_state_FSM_FFd3_18),\n .I4 (1'b0),\n .I5 (1'b0),\n .O ( present_state_FSM_FFd2_In1_24)\n );\nSTATE_LOGIC_v8_3 #(\n .INIT (64'hFFFFAAAA08AAAAAA))\n present_state_FSM_FFd2_In2\n (\n .I0 ( present_state_FSM_FFd2_19),\n .I1 ( S_AXI_AWVALID),\n .I2 ( bready_timeout_c),\n .I3 ( w_last_c),\n .I4 ( S_AXI_WVALID),\n .I5 ( present_state_FSM_FFd2_In1_24),\n .O ( present_state_FSM_FFd2_In)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h00C0004000C00000))\n present_state_FSM_FFd4_In1\n (\n .I0 ( S_AXI_AWVALID),\n .I1 ( w_last_c),\n .I2 ( S_AXI_WVALID),\n .I3 ( bready_timeout_c),\n .I4 ( present_state_FSM_FFd3_18),\n .I5 ( present_state_FSM_FFd2_19),\n .O ( present_state_FSM_FFd4_In1_25)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h00000000FFFF88F8))\n present_state_FSM_FFd4_In2\n (\n .I0 ( present_state_FSM_FFd1_16),\n .I1 ( S_AXI_BREADY),\n .I2 ( present_state_FSM_FFd4_17),\n .I3 ( S_AXI_AWVALID),\n .I4 ( present_state_FSM_FFd4_In1_25),\n .I5 (1'b0),\n .O ( present_state_FSM_FFd4_In)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000000000007))\n Mmux_w_ready_c_0_SW0\n (\n .I0 ( w_last_c),\n .I1 ( S_AXI_WVALID),\n .I2 (1'b0),\n .I3 (1'b0),\n .I4 (1'b0),\n .I5 (1'b0),\n .O ( N2)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'hFABAFABAFAAAF000))\n Mmux_w_ready_c_0_Q\n (\n .I0 ( N2),\n .I1 ( bready_timeout_c),\n .I2 ( S_AXI_AWVALID),\n .I3 ( present_state_FSM_FFd4_17),\n .I4 ( present_state_FSM_FFd3_18),\n .I5 ( present_state_FSM_FFd2_19),\n .O ( w_ready_c)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000000000008))\n Mmux_aw_ready_c_0_11_SW0\n (\n .I0 ( bready_timeout_c),\n .I1 ( S_AXI_WVALID),\n .I2 (1'b0),\n .I3 (1'b0),\n .I4 (1'b0),\n .I5 (1'b0),\n .O ( N4)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h88808880FFFF8880))\n present_state_FSM_FFd1_In1\n (\n .I0 ( w_last_c),\n .I1 ( N4),\n .I2 ( present_state_FSM_FFd2_19),\n .I3 ( present_state_FSM_FFd3_18),\n .I4 ( present_state_FSM_FFd1_16),\n .I5 ( S_AXI_BREADY),\n .O ( present_state_FSM_FFd1_In)\n );\nend\nend\nendgenerate\nendmodule\n\n\nmodule read_netlist_v8_3 #(\n parameter C_AXI_TYPE = 1,\n parameter C_ADDRB_WIDTH = 12\n ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,\n S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,\n S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,\n S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);\n\n input S_AXI_R_LAST_INT;\n input S_ACLK;\n input S_ARESETN;\n input S_AXI_ARVALID;\n input S_AXI_RREADY;\n output S_AXI_INCR_ADDR;\n output S_AXI_ADDR_EN;\n output S_AXI_SINGLE_TRANS;\n output S_AXI_MUX_SEL;\n output S_AXI_R_LAST;\n output S_AXI_ARREADY;\n output S_AXI_RLAST;\n output S_AXI_RVALID;\n output S_AXI_RD_EN;\n input [7:0] S_AXI_ARLEN;\n\n wire present_state_FSM_FFd1_13 ; \n wire present_state_FSM_FFd2_14 ; \n wire gaxi_full_sm_outstanding_read_r_15 ; \n wire gaxi_full_sm_ar_ready_r_16 ; \n wire gaxi_full_sm_r_last_r_17 ; \n wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; \n wire gaxi_full_sm_r_valid_c ; \n wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; \n wire gaxi_full_sm_ar_ready_c ; \n wire gaxi_full_sm_outstanding_read_c ; \n wire NlwRenamedSig_OI_S_AXI_R_LAST ; \n wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; \n wire present_state_FSM_FFd2_In ; \n wire present_state_FSM_FFd1_In ; \n wire Mmux_S_AXI_R_LAST13 ; \n wire N01 ; \n wire N2 ; \n wire Mmux_gaxi_full_sm_ar_ready_c11 ; \n wire N4 ; \n wire N8 ; \n wire N9 ; \n wire N10 ; \n wire N11 ; \n wire N12 ; \n wire N13 ; \n assign\n S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,\n S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,\n S_AXI_RLAST = gaxi_full_sm_r_last_r_17,\n S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;\n\n beh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n gaxi_full_sm_outstanding_read_r (\n .C (S_ACLK),\n .CLR(S_ARESETN),\n .D(gaxi_full_sm_outstanding_read_c),\n .Q(gaxi_full_sm_outstanding_read_r_15)\n );\n beh_vlog_ff_ce_clr_v8_3 #(\n .INIT (1'b0))\n gaxi_full_sm_r_valid_r (\n .C (S_ACLK),\n .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n .CLR (S_ARESETN),\n .D (gaxi_full_sm_r_valid_c),\n .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)\n );\n beh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n gaxi_full_sm_ar_ready_r (\n .C (S_ACLK),\n .CLR (S_ARESETN),\n .D (gaxi_full_sm_ar_ready_c),\n .Q (gaxi_full_sm_ar_ready_r_16)\n );\n beh_vlog_ff_ce_clr_v8_3 #(\n .INIT(1'b0))\n gaxi_full_sm_r_last_r (\n .C (S_ACLK),\n .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n .CLR (S_ARESETN),\n .D (NlwRenamedSig_OI_S_AXI_R_LAST),\n .Q (gaxi_full_sm_r_last_r_17)\n );\n beh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n present_state_FSM_FFd2 (\n .C ( S_ACLK),\n .CLR ( S_ARESETN),\n .D ( present_state_FSM_FFd2_In),\n .Q ( present_state_FSM_FFd2_14)\n );\n beh_vlog_ff_clr_v8_3 #(\n .INIT (1'b0))\n present_state_FSM_FFd1 (\n .C (S_ACLK),\n .CLR (S_ARESETN),\n .D (present_state_FSM_FFd1_In),\n .Q (present_state_FSM_FFd1_13)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h000000000000000B))\n S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (\n .I0 ( S_AXI_RREADY),\n .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I2 (1'b0),\n .I3 (1'b0),\n .I4 (1'b0),\n .I5 (1'b0),\n .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000000000008))\n Mmux_S_AXI_SINGLE_TRANS11 (\n .I0 (S_AXI_ARVALID),\n .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n .I2 (1'b0),\n .I3 (1'b0),\n .I4 (1'b0),\n .I5 (1'b0),\n .O (S_AXI_SINGLE_TRANS)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000000000004))\n Mmux_S_AXI_ADDR_EN11 (\n .I0 (present_state_FSM_FFd1_13),\n .I1 (S_AXI_ARVALID),\n .I2 (1'b0),\n .I3 (1'b0),\n .I4 (1'b0),\n .I5 (1'b0),\n .O (S_AXI_ADDR_EN)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'hECEE2022EEEE2022))\n present_state_FSM_FFd2_In1 (\n .I0 ( S_AXI_ARVALID),\n .I1 ( present_state_FSM_FFd1_13),\n .I2 ( S_AXI_RREADY),\n .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n .I4 ( present_state_FSM_FFd2_14),\n .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .O ( present_state_FSM_FFd2_In)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000044440444))\n Mmux_S_AXI_R_LAST131 (\n .I0 ( present_state_FSM_FFd1_13),\n .I1 ( S_AXI_ARVALID),\n .I2 ( present_state_FSM_FFd2_14),\n .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I4 ( S_AXI_RREADY),\n .I5 (1'b0),\n .O ( Mmux_S_AXI_R_LAST13)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h4000FFFF40004000))\n Mmux_S_AXI_INCR_ADDR11 (\n .I0 ( S_AXI_R_LAST_INT),\n .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n .I2 ( present_state_FSM_FFd2_14),\n .I3 ( present_state_FSM_FFd1_13),\n .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n .I5 ( Mmux_S_AXI_R_LAST13),\n .O ( S_AXI_INCR_ADDR)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h00000000000000FE))\n S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (\n .I0 ( S_AXI_ARLEN[2]),\n .I1 ( S_AXI_ARLEN[1]),\n .I2 ( S_AXI_ARLEN[0]),\n .I3 ( 1'b0),\n .I4 ( 1'b0),\n .I5 ( 1'b0),\n .O ( N01)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000000000001))\n S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (\n .I0 ( S_AXI_ARLEN[7]),\n .I1 ( S_AXI_ARLEN[6]),\n .I2 ( S_AXI_ARLEN[5]),\n .I3 ( S_AXI_ARLEN[4]),\n .I4 ( S_AXI_ARLEN[3]),\n .I5 ( N01),\n .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000000000007))\n Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (\n .I0 ( S_AXI_ARVALID),\n .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n .I2 ( 1'b0),\n .I3 ( 1'b0),\n .I4 ( 1'b0),\n .I5 ( 1'b0),\n .O ( N2)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0020000002200200))\n Mmux_gaxi_full_sm_outstanding_read_c1 (\n .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I1 ( S_AXI_RREADY),\n .I2 ( present_state_FSM_FFd1_13),\n .I3 ( present_state_FSM_FFd2_14),\n .I4 ( gaxi_full_sm_outstanding_read_r_15),\n .I5 ( N2),\n .O ( gaxi_full_sm_outstanding_read_c)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000000004555))\n Mmux_gaxi_full_sm_ar_ready_c12 (\n .I0 ( S_AXI_ARVALID),\n .I1 ( S_AXI_RREADY),\n .I2 ( present_state_FSM_FFd2_14),\n .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I4 ( 1'b0),\n .I5 ( 1'b0),\n .O ( Mmux_gaxi_full_sm_ar_ready_c11)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h00000000000000EF))\n Mmux_S_AXI_R_LAST11_SW0 (\n .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n .I1 ( S_AXI_RREADY),\n .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I3 ( 1'b0),\n .I4 ( 1'b0),\n .I5 ( 1'b0),\n .O ( N4)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'hFCAAFC0A00AA000A))\n Mmux_S_AXI_R_LAST11 (\n .I0 ( S_AXI_ARVALID),\n .I1 ( gaxi_full_sm_outstanding_read_r_15),\n .I2 ( present_state_FSM_FFd2_14),\n .I3 ( present_state_FSM_FFd1_13),\n .I4 ( N4),\n .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),\n .O ( gaxi_full_sm_r_valid_c)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h00000000AAAAAA08))\n S_AXI_MUX_SEL1 (\n .I0 (present_state_FSM_FFd1_13),\n .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I2 (S_AXI_RREADY),\n .I3 (present_state_FSM_FFd2_14),\n .I4 (gaxi_full_sm_outstanding_read_r_15),\n .I5 (1'b0),\n .O (S_AXI_MUX_SEL)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'hF3F3F755A2A2A200))\n Mmux_S_AXI_RD_EN11 (\n .I0 ( present_state_FSM_FFd1_13),\n .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I2 ( S_AXI_RREADY),\n .I3 ( gaxi_full_sm_outstanding_read_r_15),\n .I4 ( present_state_FSM_FFd2_14),\n .I5 ( S_AXI_ARVALID),\n .O ( S_AXI_RD_EN)\n );\n beh_vlog_muxf7_v8_3 present_state_FSM_FFd1_In3 (\n .I0 ( N8),\n .I1 ( N9),\n .S ( present_state_FSM_FFd1_13),\n .O ( present_state_FSM_FFd1_In)\n );\n\n STATE_LOGIC_v8_3 #(\n .INIT (64'h000000005410F4F0))\n present_state_FSM_FFd1_In3_F (\n .I0 ( S_AXI_RREADY),\n .I1 ( present_state_FSM_FFd2_14),\n .I2 ( S_AXI_ARVALID),\n .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n .I5 ( 1'b0),\n .O ( N8)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000072FF7272))\n present_state_FSM_FFd1_In3_G (\n .I0 ( present_state_FSM_FFd2_14),\n .I1 ( S_AXI_R_LAST_INT),\n .I2 ( gaxi_full_sm_outstanding_read_r_15),\n .I3 ( S_AXI_RREADY),\n .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I5 ( 1'b0),\n .O ( N9)\n );\n beh_vlog_muxf7_v8_3 Mmux_gaxi_full_sm_ar_ready_c14 (\n .I0 ( N10),\n .I1 ( N11),\n .S ( present_state_FSM_FFd1_13),\n .O ( gaxi_full_sm_ar_ready_c)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h00000000FFFF88A8))\n Mmux_gaxi_full_sm_ar_ready_c14_F (\n .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n .I1 ( S_AXI_RREADY),\n .I2 ( present_state_FSM_FFd2_14),\n .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I4 ( Mmux_gaxi_full_sm_ar_ready_c11),\n .I5 ( 1'b0),\n .O ( N10)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h000000008D008D8D))\n Mmux_gaxi_full_sm_ar_ready_c14_G (\n .I0 ( present_state_FSM_FFd2_14),\n .I1 ( S_AXI_R_LAST_INT),\n .I2 ( gaxi_full_sm_outstanding_read_r_15),\n .I3 ( S_AXI_RREADY),\n .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I5 ( 1'b0),\n .O ( N11)\n );\n beh_vlog_muxf7_v8_3 Mmux_S_AXI_R_LAST1 (\n .I0 ( N12),\n .I1 ( N13),\n .S ( present_state_FSM_FFd1_13),\n .O ( NlwRenamedSig_OI_S_AXI_R_LAST)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h0000000088088888))\n Mmux_S_AXI_R_LAST1_F (\n .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),\n .I1 ( S_AXI_ARVALID),\n .I2 ( present_state_FSM_FFd2_14),\n .I3 ( S_AXI_RREADY),\n .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I5 ( 1'b0),\n .O ( N12)\n );\n STATE_LOGIC_v8_3 #(\n .INIT (64'h00000000E400E4E4))\n Mmux_S_AXI_R_LAST1_G (\n .I0 ( present_state_FSM_FFd2_14),\n .I1 ( gaxi_full_sm_outstanding_read_r_15),\n .I2 ( S_AXI_R_LAST_INT),\n .I3 ( S_AXI_RREADY),\n .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),\n .I5 ( 1'b0),\n .O ( N13)\n );\n\nendmodule\n\n\nmodule blk_mem_axi_write_wrapper_beh_v8_3\n # (\n // AXI Interface related parameters start here\n parameter C_INTERFACE_TYPE = 0, // 0: Native Interface; 1: AXI Interface\n parameter C_AXI_TYPE = 0, // 0: AXI Lite; 1: AXI Full;\n parameter C_AXI_SLAVE_TYPE = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;\n parameter C_MEMORY_TYPE = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;\n parameter C_WRITE_DEPTH_A = 0,\n parameter C_AXI_AWADDR_WIDTH = 32,\n parameter C_ADDRA_WIDTH \t = 12,\n parameter C_AXI_WDATA_WIDTH = 32,\n parameter C_HAS_AXI_ID = 0,\n parameter C_AXI_ID_WIDTH = 4,\n // AXI OUTSTANDING WRITES\n parameter C_AXI_OS_WR = 2\n )\n (\n // AXI Global Signals\n input S_ACLK, \n input S_ARESETN,\n // AXI Full/Lite Slave Write Channel (write side)\n input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,\n input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,\n input [8-1:0] S_AXI_AWLEN,\n input [2:0] S_AXI_AWSIZE,\n input [1:0] S_AXI_AWBURST,\n input S_AXI_AWVALID,\n output S_AXI_AWREADY,\n input S_AXI_WVALID,\n output S_AXI_WREADY, \n output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,\n output S_AXI_BVALID,\n input S_AXI_BREADY,\n // Signals for BMG interface\n output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,\n output S_AXI_WR_EN\n );\n\n localparam FLOP_DELAY = 100; // 100 ps\n\n localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:\n ((C_AXI_WDATA_WIDTH==16)?1:\n ((C_AXI_WDATA_WIDTH==32)?2:\n ((C_AXI_WDATA_WIDTH==64)?3:\n ((C_AXI_WDATA_WIDTH==128)?4:\n ((C_AXI_WDATA_WIDTH==256)?5:0))))));\n\n\n\n\n wire bvalid_c ;\n reg bready_timeout_c = 0;\n wire [1:0] bvalid_rd_cnt_c;\n reg bvalid_r \t= 0;\n reg [2:0] bvalid_count_r = 0;\n reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;\n reg [1:0] bvalid_wr_cnt_r = 0;\n reg [1:0] bvalid_rd_cnt_r = 0;\n wire w_last_c ;\n wire addr_en_c ;\n wire incr_addr_c ;\n wire aw_ready_r \t ;\n wire dec_alen_c ;\n reg bvalid_d1_c = 0;\n reg [7:0] awlen_cntr_r = 0;\n reg [7:0] awlen_int = 0;\n reg [1:0] awburst_int = 0;\n\n integer total_bytes = 0;\n integer wrap_boundary = 0;\n integer wrap_base_addr = 0;\n integer num_of_bytes_c = 0;\n integer num_of_bytes_r = 0;\n // Array to store BIDs\n reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;\n wire S_AXI_BVALID_axi_wr_fsm;\n\n //-------------------------------------\n //AXI WRITE FSM COMPONENT INSTANTIATION\n //-------------------------------------\n write_netlist_v8_3 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm\n (\n .S_ACLK(S_ACLK),\n .S_ARESETN(S_ARESETN),\n .S_AXI_AWVALID(S_AXI_AWVALID),\n .aw_ready_r(aw_ready_r),\n .S_AXI_WVALID(S_AXI_WVALID),\n .S_AXI_WREADY(S_AXI_WREADY),\n .S_AXI_BREADY(S_AXI_BREADY),\n .S_AXI_WR_EN(S_AXI_WR_EN),\n .w_last_c(w_last_c),\n .bready_timeout_c(bready_timeout_c),\n .addr_en_c(addr_en_c),\n .incr_addr_c(incr_addr_c),\n .bvalid_c(bvalid_c),\n .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) \n\t ); \n \n \n //Wrap Address boundary calculation \n always@(*) begin\n num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);\n total_bytes = (num_of_bytes_r)*(awlen_int+1);\n wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);\n wrap_boundary = wrap_base_addr+total_bytes;\n end\n \n //-------------------------------------------------------------------------\n // BMG address generation\n //-------------------------------------------------------------------------\n always @(posedge S_ACLK or S_ARESETN) begin\n if (S_ARESETN == 1'b1) begin\n awaddr_reg <= 0;\n\t num_of_bytes_r <= 0;\n\t awburst_int <= 0; \n\t end else begin\n if (addr_en_c == 1'b1) begin\n awaddr_reg <= #FLOP_DELAY S_AXI_AWADDR ;\n\t num_of_bytes_r <= num_of_bytes_c;\n\t awburst_int <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);\n\t end else if (incr_addr_c == 1'b1) begin\n\t if (awburst_int == 2'b10) begin\n\t\tif(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin\n\t\t awaddr_reg <= wrap_base_addr;\n\t\tend else begin\n\t\t awaddr_reg <= awaddr_reg + num_of_bytes_r;\n\t\tend\n\t end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin\n\t\tawaddr_reg <= awaddr_reg + num_of_bytes_r;\n\t end\n end\n end\n end\n \n \n assign S_AXI_AWADDR_OUT = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n\t\t\t \t awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);\n\n //-------------------------------------------------------------------------\n // AXI wlast generation\n //-------------------------------------------------------------------------\n always @(posedge S_ACLK or S_ARESETN) begin\n if (S_ARESETN == 1'b1) begin\n awlen_cntr_r <= 0;\n\t awlen_int <= 0;\n\t end else begin\n if (addr_en_c == 1'b1) begin\n\t awlen_int <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t awlen_cntr_r <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;\n\t end else if (dec_alen_c == 1'b1) begin\n awlen_cntr_r <= #FLOP_DELAY awlen_cntr_r - 1 ;\n end\n end\n end\n\n assign w_last_c = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;\n \n assign dec_alen_c = (incr_addr_c | w_last_c);\n\n //-------------------------------------------------------------------------\n // Generation of bvalid counter for outstanding transactions \n //-------------------------------------------------------------------------\n always @(posedge S_ACLK or S_ARESETN) begin\n if (S_ARESETN == 1'b1) begin\n\tbvalid_count_r <= 0;\n\tend else begin\n\t// bvalid_count_r generation\n\tif (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin\n\t bvalid_count_r <= #FLOP_DELAY bvalid_count_r ;\n\t end else if (bvalid_c == 1'b1) begin \n\t bvalid_count_r <= #FLOP_DELAY bvalid_count_r + 1 ;\n\t end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin\n\t bvalid_count_r <= #FLOP_DELAY bvalid_count_r - 1 ;\n\tend\n end\n end\n\n //-------------------------------------------------------------------------\n // Generation of bvalid when BID is used \n //-------------------------------------------------------------------------\n generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n always @(posedge S_ACLK or S_ARESETN) begin\n if (S_ARESETN == 1'b1) begin\n bvalid_r <= 0;\n bvalid_d1_c <= 0;\n\tend else begin\n // Delay the generation o bvalid_r for generation for BID \n bvalid_d1_c <= bvalid_c;\n \n //external bvalid signal generation\n if (bvalid_d1_c == 1'b1) begin\n bvalid_r <= #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n bvalid_r <= #FLOP_DELAY 0 ;\n end\n end\n end\n end\n endgenerate\n \n //-------------------------------------------------------------------------\n // Generation of bvalid when BID is not used \n //-------------------------------------------------------------------------\n generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r\n always @(posedge S_ACLK or S_ARESETN) begin\n if (S_ARESETN == 1'b1) begin\n bvalid_r <= 0;\n\tend else begin\n //external bvalid signal generation\n if (bvalid_c == 1'b1) begin\n bvalid_r <= #FLOP_DELAY 1'b1 ;\n\t end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin\n bvalid_r <= #FLOP_DELAY 0 ;\n end\n end\n end\n end\n endgenerate\n \n //-------------------------------------------------------------------------\n // Generation of Bready timeout\n //-------------------------------------------------------------------------\n always @(bvalid_count_r) begin\n \t// bready_timeout_c generation\n\tif(bvalid_count_r == C_AXI_OS_WR-1) begin\n\t bready_timeout_c <= 1'b1;\n\tend else begin\n\t bready_timeout_c <= 1'b0;\n\tend\n end\n \n //-------------------------------------------------------------------------\n // Generation of BID \n //-------------------------------------------------------------------------\n generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen\n\n always @(posedge S_ACLK or S_ARESETN) begin\n if (S_ARESETN == 1'b1) begin\n bvalid_wr_cnt_r <= 0;\n bvalid_rd_cnt_r <= 0;\n\tend else begin\n // STORE AWID IN AN ARRAY\n if(bvalid_c == 1'b1) begin\n bvalid_wr_cnt_r <= bvalid_wr_cnt_r + 1;\n end\n\t // generate BID FROM AWID ARRAY\n\t bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;\n\t S_AXI_BID <= axi_bid_array[bvalid_rd_cnt_c];\n end \n end\n \n assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;\n \n //-------------------------------------------------------------------------\n // Storing AWID for generation of BID\n //-------------------------------------------------------------------------\n always @(posedge S_ACLK or S_ARESETN) begin\n if(S_ARESETN == 1'b1) begin\n\taxi_bid_array[0] = 0;\n\taxi_bid_array[1] = 0;\n\taxi_bid_array[2] = 0;\n\taxi_bid_array[3] = 0;\n\tend else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin\n\taxi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;\n end\n end\n \n end\n endgenerate\n\n assign S_AXI_BVALID = bvalid_r;\n assign S_AXI_AWREADY = aw_ready_r;\n\n endmodule\n\nmodule blk_mem_axi_read_wrapper_beh_v8_3\n# (\n //// AXI Interface related parameters start here\n parameter C_INTERFACE_TYPE = 0,\n parameter C_AXI_TYPE = 0,\n parameter C_AXI_SLAVE_TYPE = 0,\n parameter C_MEMORY_TYPE = 0,\n parameter C_WRITE_WIDTH_A = 4,\n parameter C_WRITE_DEPTH_A = 32,\n parameter C_ADDRA_WIDTH = 12,\n parameter C_AXI_PIPELINE_STAGES = 0,\n parameter C_AXI_ARADDR_WIDTH = 12,\n parameter C_HAS_AXI_ID = 0,\n parameter C_AXI_ID_WIDTH = 4,\n parameter C_ADDRB_WIDTH = 12\n )\n (\n\n //// AXI Global Signals\n input S_ACLK,\n input S_ARESETN,\n //// AXI Full/Lite Slave Read (Read side)\n input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,\n input [7:0] S_AXI_ARLEN,\n input [2:0] S_AXI_ARSIZE,\n input [1:0] S_AXI_ARBURST,\n input S_AXI_ARVALID,\n output S_AXI_ARREADY,\n output S_AXI_RLAST, \n output S_AXI_RVALID,\n input S_AXI_RREADY,\n input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,\n output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,\n //// AXI Full/Lite Read Address Signals to BRAM\n output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,\n output S_AXI_RD_EN\n );\n\n localparam FLOP_DELAY = 100; // 100 ps\n localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:\n ((C_WRITE_WIDTH_A==16)?1:\n ((C_WRITE_WIDTH_A==32)?2:\n ((C_WRITE_WIDTH_A==64)?3:\n ((C_WRITE_WIDTH_A==128)?4:\n ((C_WRITE_WIDTH_A==256)?5:0))))));\n\n\n\n reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;\n wire addr_en_c; \n wire rd_en_c; \n wire incr_addr_c; \n wire single_trans_c; \n wire dec_alen_c; \n wire mux_sel_c; \n wire r_last_c; \n wire r_last_int_c; \n wire [C_ADDRB_WIDTH-1 : 0] araddr_out; \n\n reg [7:0] arlen_int_r=0; \n reg [7:0] arlen_cntr=8'h01; \n reg [1:0] arburst_int_c=0; \n reg [1:0] arburst_int_r=0; \n reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?\n C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;\n integer num_of_bytes_c = 0;\n integer total_bytes = 0;\n integer num_of_bytes_r = 0;\n integer wrap_base_addr_r = 0;\n integer wrap_boundary_r = 0;\n\n reg [7:0] arlen_int_c=0; \n integer total_bytes_c = 0;\n integer wrap_base_addr_c = 0;\n integer wrap_boundary_c = 0;\n\n assign dec_alen_c = incr_addr_c | r_last_int_c;\n\n\n read_netlist_v8_3\n #(.C_AXI_TYPE (1),\n .C_ADDRB_WIDTH (C_ADDRB_WIDTH)) \n axi_read_fsm (\n .S_AXI_INCR_ADDR(incr_addr_c),\n .S_AXI_ADDR_EN(addr_en_c),\n .S_AXI_SINGLE_TRANS(single_trans_c),\n .S_AXI_MUX_SEL(mux_sel_c),\n .S_AXI_R_LAST(r_last_c),\n .S_AXI_R_LAST_INT(r_last_int_c),\n\n //// AXI Global Signals\n .S_ACLK(S_ACLK),\n .S_ARESETN(S_ARESETN),\n //// AXI Full/Lite Slave Read (Read side)\n .S_AXI_ARLEN(S_AXI_ARLEN),\n .S_AXI_ARVALID(S_AXI_ARVALID),\n .S_AXI_ARREADY(S_AXI_ARREADY),\n .S_AXI_RLAST(S_AXI_RLAST),\n .S_AXI_RVALID(S_AXI_RVALID),\n .S_AXI_RREADY(S_AXI_RREADY),\n //// AXI Full/Lite Read Address Signals to BRAM\n .S_AXI_RD_EN(rd_en_c)\n );\n\n always@(*) begin\n num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);\n total_bytes = (num_of_bytes_r)*(arlen_int_r+1);\n wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);\n wrap_boundary_r = wrap_base_addr_r+total_bytes;\n\n //////// combinatorial from interface\n arlen_int_c = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);\n total_bytes_c = (num_of_bytes_c)*(arlen_int_c+1);\n wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);\n wrap_boundary_c = wrap_base_addr_c+total_bytes_c;\n \n arburst_int_c = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1); \n end\n\n ////-------------------------------------------------------------------------\n //// BMG address generation\n ////-------------------------------------------------------------------------\n always @(posedge S_ACLK or S_ARESETN) begin\n if (S_ARESETN == 1'b1) begin\n araddr_reg \t<= 0;\n \tarburst_int_r <= 0;\n\tnum_of_bytes_r <= 0;\n end else begin\n if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin\n\t arburst_int_r <= arburst_int_c;\n\t num_of_bytes_r <= num_of_bytes_c;\n\t if (arburst_int_c == 2'b10) begin\n\t\t if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin\n\t\t araddr_reg <= wrap_base_addr_c;\n\t\t end else begin\n\t\t araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t\t end\n\t end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin\n\t\t araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;\n\t end\n\n end else if (addr_en_c == 1'b1) begin\n araddr_reg <= S_AXI_ARADDR;\n\t num_of_bytes_r <= num_of_bytes_c;\n\t arburst_int_r <= arburst_int_c;\n\t end else if (incr_addr_c == 1'b1) begin\n\t if (arburst_int_r == 2'b10) begin\n\t \tif(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin\n\t \t araddr_reg <= wrap_base_addr_r;\n\t \tend else begin\n\t \t araddr_reg <= araddr_reg + num_of_bytes_r;\n\t \tend\n\t end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin\n\t\t araddr_reg <= araddr_reg + num_of_bytes_r;\n\t end\n end\n end\n end\n\nassign araddr_out = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);\n \n\n ////-----------------------------------------------------------------------\n //// Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM\n ////-----------------------------------------------------------------------\n always @(posedge S_ACLK or S_ARESETN) begin\n if (S_ARESETN == 1'b1) begin\n arlen_cntr <= 8'h01;\n\t arlen_int_r <= 0;\n\tend else begin\n if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin\n\t arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n arlen_cntr <= S_AXI_ARLEN - 1'b1;\n\t end else if (addr_en_c == 1'b1) begin\n\t arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t arlen_cntr <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;\n\t end else if (dec_alen_c == 1'b1) begin\n arlen_cntr <= arlen_cntr - 1'b1 ;\n end\n\t else begin\n\t arlen_cntr <= arlen_cntr;\n\t end\n end\n end\n\n assign r_last_int_c = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;\n\n\n ////------------------------------------------------------------------------\n //// AXI FULL FSM\n //// Mux Selection of ARADDR\n //// ARADDR is driven out from the read fsm based on the mux_sel_c\n //// Based on mux_sel either ARADDR is given out or the latched ARADDR is\n //// given out to BRAM\n ////------------------------------------------------------------------------\n\tassign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;\n \n ////------------------------------------------------------------------------\n //// Assign output signals - AXI FULL FSM\n ////------------------------------------------------------------------------\n assign S_AXI_RD_EN = rd_en_c;\n\n generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r\n always @(posedge S_ACLK or S_ARESETN) begin\n if (S_ARESETN == 1'b1) begin\n S_AXI_RID <= 0;\n ar_id_r <= 0;\n\tend else begin\n if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin\n S_AXI_RID <= S_AXI_ARID;\n ar_id_r <= S_AXI_ARID;\n end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin\n\t ar_id_r <= S_AXI_ARID;\n end else if (rd_en_c == 1'b1) begin\n S_AXI_RID <= ar_id_r;\n end\n end\n end \n end \n endgenerate \n\nendmodule\n\nmodule blk_mem_axi_regs_fwd_v8_3\n #(parameter C_DATA_WIDTH = 8\n )(\n input ACLK,\n input ARESET,\n input S_VALID,\n output S_READY,\n input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,\n output M_VALID,\n input M_READY,\n output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA\n );\n\n reg [C_DATA_WIDTH-1:0] STORAGE_DATA;\n wire S_READY_I;\n reg M_VALID_I;\n reg [1:0] ARESET_D;\n\n //assign local signal to its output signal\n assign S_READY = S_READY_I;\n assign M_VALID = M_VALID_I;\n\n always @(posedge ACLK) begin\n\t ARESET_D <= {ARESET_D[0], ARESET};\n\tend\n \n //Save payload data whenever we have a transaction on the slave side\n always @(posedge ACLK or ARESET) begin\n if (ARESET == 1'b1) begin\n \t STORAGE_DATA <= 0;\n\tend else begin\n\t if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin\n \t STORAGE_DATA <= S_PAYLOAD_DATA;\n \t end\n \tend\n end\n\n always @(posedge ACLK) begin\n M_PAYLOAD_DATA = STORAGE_DATA;\n end\n \n //M_Valid set to high when we have a completed transfer on slave side\n //Is removed on a M_READY except if we have a new transfer on the slave side\n \n always @(posedge ACLK or ARESET_D) begin\n\tif (ARESET_D != 2'b00) begin\n \t M_VALID_I <= 1'b0;\n\tend else begin\n\t if (S_VALID == 1'b1) begin\n\t //Always set M_VALID_I when slave side is valid\n M_VALID_I <= 1'b1;\n\t end else if (M_READY == 1'b1 ) begin\n\t //Clear (or keep) when no slave side is valid but master side is ready\n\t M_VALID_I <= 1'b0;\n\t end\n\tend\n end\n\n //Slave Ready is either when Master side drives M_READY or we have space in our storage data\n assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));\n\n endmodule\n\n//*****************************************************************************\n// Output Register Stage module\n//\n// This module builds the output register stages of the memory. This module is \n// instantiated in the main memory module (blk_mem_gen_v8_3_4) which is\n// declared/implemented further down in this file.\n//*****************************************************************************\nmodule blk_mem_gen_v8_3_4_output_stage\n #(parameter C_FAMILY = \"virtex7\",\n parameter C_XDEVICEFAMILY = \"virtex7\",\n parameter C_RST_TYPE = \"SYNC\",\n parameter C_HAS_RST = 0,\n parameter C_RSTRAM = 0,\n parameter C_RST_PRIORITY = \"CE\",\n parameter C_INIT_VAL = \"0\",\n parameter C_HAS_EN = 0,\n parameter C_HAS_REGCE = 0,\n parameter C_DATA_WIDTH = 32,\n parameter C_ADDRB_WIDTH = 10,\n parameter C_HAS_MEM_OUTPUT_REGS = 0,\n parameter C_USE_SOFTECC = 0,\n parameter C_USE_ECC = 0,\n parameter NUM_STAGES = 1,\n\tparameter C_EN_ECC_PIPE = 0,\n parameter FLOP_DELAY = 100\n )\n (\n input CLK,\n input RST,\n input EN,\n input REGCE,\n input [C_DATA_WIDTH-1:0] DIN_I,\n output reg [C_DATA_WIDTH-1:0] DOUT,\n input SBITERR_IN_I,\n input DBITERR_IN_I,\n output reg SBITERR,\n output reg DBITERR,\n input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN_I,\n input ECCPIPECE, \n output reg [C_ADDRB_WIDTH-1:0] RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n //////////////////////////////////////////////////////////////////////////\n // Generic Definitions\n //////////////////////////////////////////////////////////////////////////\n // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n // options are available - \"spartan3\", \"spartan6\", \n // \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n // C_RST_TYPE : Type of reset - Synchronous or Asynchronous\n // C_HAS_RST : Determines the presence of the RST port\n // C_RSTRAM : Determines if special reset behavior is used\n // C_RST_PRIORITY : Determines the priority between CE and SR\n // C_INIT_VAL : Initialization value\n // C_HAS_EN : Determines the presence of the EN port\n // C_HAS_REGCE : Determines the presence of the REGCE port\n // C_DATA_WIDTH : Memory write/read width\n // C_ADDRB_WIDTH : Width of the ADDRB input port\n // C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output \n // of the RAM primitive\n // C_USE_SOFTECC : Determines if the Soft ECC feature is used or\n // not. Only applicable Spartan-6\n // C_USE_ECC : Determines if the ECC feature is used or\n // not. Only applicable for V5 and V6\n // NUM_STAGES : Determines the number of output stages\n // FLOP_DELAY : Constant delay for register assignments\n //////////////////////////////////////////////////////////////////////////\n // Port Definitions\n //////////////////////////////////////////////////////////////////////////\n // CLK : Clock to synchronize all read and write operations\n // RST : Reset input to reset memory outputs to a user-defined \n // reset state\n // EN : Enable all read and write operations\n // REGCE : Register Clock Enable to control each pipeline output\n // register stages\n // DIN : Data input to the Output stage.\n // DOUT : Final Data output\n // SBITERR_IN : SBITERR input signal to the Output stage.\n // SBITERR : Final SBITERR Output signal.\n // DBITERR_IN : DBITERR input signal to the Output stage.\n // DBITERR : Final DBITERR Output signal.\n // RDADDRECC_IN : RDADDRECC input signal to the Output stage.\n // RDADDRECC : Final RDADDRECC Output signal.\n //////////////////////////////////////////////////////////////////////////\n\n// Fix for CR-509792\n\n localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;\n \n // Declare the pipeline registers \n // (includes mem output reg, mux pipeline stages, and mux output reg)\n reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;\n reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;\n reg [REG_STAGES-1:0] sbiterr_regs;\n reg [REG_STAGES-1:0] dbiterr_regs;\n\n reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL;\n reg [C_DATA_WIDTH-1:0] init_val ;\n\n //*********************************************\n // Wire off optional inputs based on parameters\n //*********************************************\n wire en_i;\n wire regce_i;\n wire rst_i;\n \n // Internal signals\n reg [C_DATA_WIDTH-1:0] DIN;\n reg [C_ADDRB_WIDTH-1:0] RDADDRECC_IN;\n reg SBITERR_IN;\n reg DBITERR_IN;\n\n\n // Internal enable for output registers is tied to user EN or '1' depending\n // on parameters\n assign en_i = (C_HAS_EN==0 || EN);\n\n // Internal register enable for output registers is tied to user REGCE, EN or\n // '1' depending on parameters\n // For V4 ECC, REGCE is always 1\n // Virtex-4 ECC Not Yet Supported\n assign regce_i = ((C_HAS_REGCE==1) && REGCE) ||\n ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));\n \n //Internal SRR is tied to user RST or '0' depending on parameters\n assign rst_i = (C_HAS_RST==1) && RST;\n\n //****************************************************\n // Power on: load up the output registers and latches\n //****************************************************\n initial begin\n if (!($sscanf(init_str, \"%h\", init_val))) begin\n init_val = 0;\n end\n DOUT = init_val;\n RDADDRECC = 0;\n SBITERR = 1'b0;\n DBITERR = 1'b0;\n\tDIN = {(C_DATA_WIDTH){1'b0}};\n RDADDRECC_IN = 0;\n SBITERR_IN = 0;\n\tDBITERR_IN = 0;\n\t// This will be one wider than need, but 0 is an error\n out_regs = {(REG_STAGES+1){init_val}};\n rdaddrecc_regs = 0;\n sbiterr_regs = {(REG_STAGES+1){1'b0}};\n dbiterr_regs = {(REG_STAGES+1){1'b0}};\n end\n\n //***********************************************\n // NUM_STAGES = 0 (No output registers. RAM only)\n //***********************************************\n generate if (NUM_STAGES == 0) begin : zero_stages\n always @* begin\n DOUT = DIN;\n RDADDRECC = RDADDRECC_IN;\n SBITERR = SBITERR_IN;\n DBITERR = DBITERR_IN;\n end\n end\n endgenerate\n\n generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg\n always @* begin\n DIN = DIN_I;\n\t SBITERR_IN = SBITERR_IN_I;\n DBITERR_IN = DBITERR_IN_I;\n RDADDRECC_IN = RDADDRECC_IN_I;\n end\n end\n endgenerate\n\n generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg\n always @(posedge CLK) begin\n if(ECCPIPECE == 1) begin\n\t DIN <= #FLOP_DELAY DIN_I;\n SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;\n DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;\n RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;\n end\n\tend\n end\n endgenerate\n\n\n //***********************************************\n // NUM_STAGES = 1 \n // (Mem Output Reg only or Mux Output Reg only)\n //***********************************************\n\n // Possible valid combinations: \n // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)\n // +-----------------------------------------+\n // | C_RSTRAM_* | Reset Behavior |\n // +----------------+------------------------+\n // | 0 | Normal Behavior |\n // +----------------+------------------------+\n // | 1 | Special Behavior |\n // +----------------+------------------------+\n //\n // Normal = REGCE gates reset, as in the case of all families except S3ADSP.\n // Special = EN gates reset, as in the case of S3ADSP.\n\n generate if (NUM_STAGES == 1 && \n (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != \"spartan3adsp\" && C_XDEVICEFAMILY != \"aspartan3adsp\" )) ||\n C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))\n begin : one_stages_norm\n\n always @(posedge CLK) begin\n if (C_RST_PRIORITY == \"CE\") begin //REGCE has priority\n if (regce_i && rst_i) begin\n DOUT <= #FLOP_DELAY init_val;\n RDADDRECC <= #FLOP_DELAY 0;\n SBITERR <= #FLOP_DELAY 1'b0;\n DBITERR <= #FLOP_DELAY 1'b0;\n end else if (regce_i) begin\n DOUT <= #FLOP_DELAY DIN;\n RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n SBITERR <= #FLOP_DELAY SBITERR_IN;\n DBITERR <= #FLOP_DELAY DBITERR_IN;\n end //Output signal assignments\n end else begin //RST has priority\n if (rst_i) begin\n DOUT <= #FLOP_DELAY init_val;\n RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n SBITERR <= #FLOP_DELAY 1'b0;\n DBITERR <= #FLOP_DELAY 1'b0;\n end else if (regce_i) begin\n DOUT <= #FLOP_DELAY DIN;\n RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;\n SBITERR <= #FLOP_DELAY SBITERR_IN;\n DBITERR <= #FLOP_DELAY DBITERR_IN;\n end //Output signal assignments\n end //end Priority conditions\n end //end RST Type conditions\n end //end one_stages_norm generate statement\n endgenerate\n\n // Special Reset Behavior for S3ADSP\n generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY ==\"spartan3adsp\" || C_XDEVICEFAMILY ==\"aspartan3adsp\"))\n begin : one_stage_splbhv\n always @(posedge CLK) begin\n if (en_i && rst_i) begin\n DOUT <= #FLOP_DELAY init_val;\n end else if (regce_i && !rst_i) begin\n DOUT <= #FLOP_DELAY DIN;\n end //Output signal assignments\n end //end CLK\n end //end one_stage_splbhv generate statement\n endgenerate\n\n //************************************************************\n // NUM_STAGES > 1 \n // Mem Output Reg + Mux Output Reg\n // or \n // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg\n // or \n // Mux Pipeline Stages (>0) + Mux Output Reg\n //*************************************************************\n generate if (NUM_STAGES > 1) begin : multi_stage\n //Asynchronous Reset\n always @(posedge CLK) begin\n if (C_RST_PRIORITY == \"CE\") begin //REGCE has priority\n if (regce_i && rst_i) begin\n DOUT <= #FLOP_DELAY init_val;\n RDADDRECC <= #FLOP_DELAY 0;\n SBITERR <= #FLOP_DELAY 1'b0;\n DBITERR <= #FLOP_DELAY 1'b0;\n end else if (regce_i) begin\n DOUT <= #FLOP_DELAY\n out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n end //Output signal assignments\n end else begin //RST has priority\n if (rst_i) begin\n DOUT <= #FLOP_DELAY init_val;\n RDADDRECC <= #FLOP_DELAY 0;\n SBITERR <= #FLOP_DELAY 1'b0;\n DBITERR <= #FLOP_DELAY 1'b0;\n end else if (regce_i) begin\n DOUT <= #FLOP_DELAY\n out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];\n RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];\n SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];\n DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];\n end //Output signal assignments\n end //end Priority conditions\n // Shift the data through the output stages\n if (en_i) begin\n out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;\n rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;\n sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;\n dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;\n end\n end //end CLK\n end //end multi_stage generate statement\n endgenerate\nendmodule\n\nmodule blk_mem_gen_v8_3_4_softecc_output_reg_stage\n #(parameter C_DATA_WIDTH = 32,\n parameter C_ADDRB_WIDTH = 10,\n parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n parameter C_USE_SOFTECC = 0,\n parameter FLOP_DELAY = 100\n )\n (\n input CLK,\n input [C_DATA_WIDTH-1:0] DIN,\n output reg [C_DATA_WIDTH-1:0] DOUT,\n input SBITERR_IN,\n input DBITERR_IN,\n output reg SBITERR,\n output reg DBITERR,\n input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,\n output reg [C_ADDRB_WIDTH-1:0] RDADDRECC\n);\n\n//******************************\n// Port and Generic Definitions\n//******************************\n //////////////////////////////////////////////////////////////////////////\n // Generic Definitions\n //////////////////////////////////////////////////////////////////////////\n // C_DATA_WIDTH : Memory write/read width\n // C_ADDRB_WIDTH : Width of the ADDRB input port\n // C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output \n // of the RAM primitive\n // C_USE_SOFTECC : Determines if the Soft ECC feature is used or\n // not. Only applicable Spartan-6\n // FLOP_DELAY : Constant delay for register assignments\n //////////////////////////////////////////////////////////////////////////\n // Port Definitions\n //////////////////////////////////////////////////////////////////////////\n // CLK : Clock to synchronize all read and write operations\n // DIN : Data input to the Output stage.\n // DOUT : Final Data output\n // SBITERR_IN : SBITERR input signal to the Output stage.\n // SBITERR : Final SBITERR Output signal.\n // DBITERR_IN : DBITERR input signal to the Output stage.\n // DBITERR : Final DBITERR Output signal.\n // RDADDRECC_IN : RDADDRECC input signal to the Output stage.\n // RDADDRECC : Final RDADDRECC Output signal.\n //////////////////////////////////////////////////////////////////////////\n\n reg [C_DATA_WIDTH-1:0] dout_i = 0;\n reg sbiterr_i = 0;\n reg dbiterr_i = 0;\n reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;\n\n //***********************************************\n // NO OUTPUT REGISTERS.\n //***********************************************\n generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage\n always @* begin\n DOUT = DIN;\n RDADDRECC = RDADDRECC_IN;\n SBITERR = SBITERR_IN;\n DBITERR = DBITERR_IN;\n end\n end\n endgenerate\n\n //***********************************************\n // WITH OUTPUT REGISTERS.\n //***********************************************\n generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage\n always @(posedge CLK) begin\n dout_i <= #FLOP_DELAY DIN;\n rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;\n sbiterr_i <= #FLOP_DELAY SBITERR_IN;\n dbiterr_i <= #FLOP_DELAY DBITERR_IN;\n end\n\n always @* begin\n DOUT = dout_i;\n RDADDRECC = rdaddrecc_i;\n SBITERR = sbiterr_i;\n DBITERR = dbiterr_i;\n end //end always\n end //end in_or_out_stage generate statement\n endgenerate\n\nendmodule\n\n\n//*****************************************************************************\n// Main Memory module\n//\n// This module is the top-level behavioral model and this implements the RAM \n//*****************************************************************************\nmodule blk_mem_gen_v8_3_4_mem_module\n #(parameter C_CORENAME = \"blk_mem_gen_v8_3_4\",\n parameter C_FAMILY = \"virtex7\",\n parameter C_XDEVICEFAMILY = \"virtex7\",\n parameter C_MEM_TYPE = 2,\n parameter C_BYTE_SIZE = 9,\n parameter C_USE_BRAM_BLOCK = 0,\n parameter C_ALGORITHM = 1,\n parameter C_PRIM_TYPE = 3,\n parameter C_LOAD_INIT_FILE = 0,\n parameter C_INIT_FILE_NAME = \"\",\n parameter C_INIT_FILE = \"\",\n parameter C_USE_DEFAULT_DATA = 0,\n parameter C_DEFAULT_DATA = \"0\",\n parameter C_RST_TYPE = \"SYNC\",\n parameter C_HAS_RSTA = 0,\n parameter C_RST_PRIORITY_A = \"CE\",\n parameter C_RSTRAM_A = 0,\n parameter C_INITA_VAL = \"0\",\n parameter C_HAS_ENA = 1,\n parameter C_HAS_REGCEA = 0,\n parameter C_USE_BYTE_WEA = 0,\n parameter C_WEA_WIDTH = 1,\n parameter C_WRITE_MODE_A = \"WRITE_FIRST\",\n parameter C_WRITE_WIDTH_A = 32,\n parameter C_READ_WIDTH_A = 32,\n parameter C_WRITE_DEPTH_A = 64,\n parameter C_READ_DEPTH_A = 64,\n parameter C_ADDRA_WIDTH = 5,\n parameter C_HAS_RSTB = 0,\n parameter C_RST_PRIORITY_B = \"CE\",\n parameter C_RSTRAM_B = 0,\n parameter C_INITB_VAL = \"\",\n parameter C_HAS_ENB = 1,\n parameter C_HAS_REGCEB = 0,\n parameter C_USE_BYTE_WEB = 0,\n parameter C_WEB_WIDTH = 1,\n parameter C_WRITE_MODE_B = \"WRITE_FIRST\",\n parameter C_WRITE_WIDTH_B = 32,\n parameter C_READ_WIDTH_B = 32,\n parameter C_WRITE_DEPTH_B = 64,\n parameter C_READ_DEPTH_B = 64,\n parameter C_ADDRB_WIDTH = 5,\n parameter C_HAS_MEM_OUTPUT_REGS_A = 0,\n parameter C_HAS_MEM_OUTPUT_REGS_B = 0,\n parameter C_HAS_MUX_OUTPUT_REGS_A = 0,\n parameter C_HAS_MUX_OUTPUT_REGS_B = 0,\n parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n parameter C_MUX_PIPELINE_STAGES = 0,\n parameter C_USE_SOFTECC = 0,\n parameter C_USE_ECC = 0,\n parameter C_HAS_INJECTERR = 0,\n parameter C_SIM_COLLISION_CHECK = \"NONE\",\n parameter C_COMMON_CLK = 1,\n parameter FLOP_DELAY = 100,\n parameter C_DISABLE_WARN_BHV_COLL = 0,\n\tparameter C_EN_ECC_PIPE = 0,\n parameter C_DISABLE_WARN_BHV_RANGE = 0\n )\n (input CLKA,\n input RSTA,\n input ENA,\n input REGCEA,\n input [C_WEA_WIDTH-1:0] WEA,\n input [C_ADDRA_WIDTH-1:0] ADDRA,\n input [C_WRITE_WIDTH_A-1:0] DINA,\n output [C_READ_WIDTH_A-1:0] DOUTA,\n input CLKB,\n input RSTB,\n input ENB,\n input REGCEB,\n input [C_WEB_WIDTH-1:0] WEB,\n input [C_ADDRB_WIDTH-1:0] ADDRB,\n input [C_WRITE_WIDTH_B-1:0] DINB,\n output [C_READ_WIDTH_B-1:0] DOUTB,\n input INJECTSBITERR,\n input INJECTDBITERR,\n input ECCPIPECE,\n input SLEEP,\n output SBITERR,\n output DBITERR,\n output [C_ADDRB_WIDTH-1:0] RDADDRECC\n );\n//******************************\n// Port and Generic Definitions\n//******************************\n //////////////////////////////////////////////////////////////////////////\n // Generic Definitions\n //////////////////////////////////////////////////////////////////////////\n // C_CORENAME : Instance name of the Block Memory Generator core\n // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n // options are available - \"spartan3\", \"spartan6\", \n // \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n // C_MEM_TYPE : Designates memory type.\n // It can be\n // 0 - Single Port Memory\n // 1 - Simple Dual Port Memory\n // 2 - True Dual Port Memory\n // 3 - Single Port Read Only Memory\n // 4 - Dual Port Read Only Memory\n // C_BYTE_SIZE : Size of a byte (8 or 9 bits)\n // C_ALGORITHM : Designates the algorithm method used\n // for constructing the memory.\n // It can be Fixed_Primitives, Minimum_Area or \n // Low_Power\n // C_PRIM_TYPE : Designates the user selected primitive used to \n // construct the memory.\n //\n // C_LOAD_INIT_FILE : Designates the use of an initialization file to\n // initialize memory contents.\n // C_INIT_FILE_NAME : Memory initialization file name.\n // C_USE_DEFAULT_DATA : Designates whether to fill remaining\n // initialization space with default data\n // C_DEFAULT_DATA : Default value of all memory locations\n // not initialized by the memory\n // initialization file.\n // C_RST_TYPE : Type of reset - Synchronous or Asynchronous\n // C_HAS_RSTA : Determines the presence of the RSTA port\n // C_RST_PRIORITY_A : Determines the priority between CE and SR for \n // Port A.\n // C_RSTRAM_A : Determines if special reset behavior is used for\n // Port A\n // C_INITA_VAL : The initialization value for Port A\n // C_HAS_ENA : Determines the presence of the ENA port\n // C_HAS_REGCEA : Determines the presence of the REGCEA port\n // C_USE_BYTE_WEA : Determines if the Byte Write is used or not.\n // C_WEA_WIDTH : The width of the WEA port\n // C_WRITE_MODE_A : Configurable write mode for Port A. It can be\n // WRITE_FIRST, READ_FIRST or NO_CHANGE.\n // C_WRITE_WIDTH_A : Memory write width for Port A.\n // C_READ_WIDTH_A : Memory read width for Port A.\n // C_WRITE_DEPTH_A : Memory write depth for Port A.\n // C_READ_DEPTH_A : Memory read depth for Port A.\n // C_ADDRA_WIDTH : Width of the ADDRA input port\n // C_HAS_RSTB : Determines the presence of the RSTB port\n // C_RST_PRIORITY_B : Determines the priority between CE and SR for \n // Port B.\n // C_RSTRAM_B : Determines if special reset behavior is used for\n // Port B\n // C_INITB_VAL : The initialization value for Port B\n // C_HAS_ENB : Determines the presence of the ENB port\n // C_HAS_REGCEB : Determines the presence of the REGCEB port\n // C_USE_BYTE_WEB : Determines if the Byte Write is used or not.\n // C_WEB_WIDTH : The width of the WEB port\n // C_WRITE_MODE_B : Configurable write mode for Port B. It can be\n // WRITE_FIRST, READ_FIRST or NO_CHANGE.\n // C_WRITE_WIDTH_B : Memory write width for Port B.\n // C_READ_WIDTH_B : Memory read width for Port B.\n // C_WRITE_DEPTH_B : Memory write depth for Port B.\n // C_READ_DEPTH_B : Memory read depth for Port B.\n // C_ADDRB_WIDTH : Width of the ADDRB input port\n // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n // of the RAM primitive for Port A.\n // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n // of the RAM primitive for Port B.\n // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n // of the MUX for Port A.\n // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n // of the MUX for Port B.\n // C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in \n // between the muxes.\n // C_USE_SOFTECC : Determines if the Soft ECC feature is used or\n // not. Only applicable Spartan-6\n // C_USE_ECC : Determines if the ECC feature is used or\n // not. Only applicable for V5 and V6\n // C_HAS_INJECTERR : Determines if the error injection pins\n // are present or not. If the ECC feature\n // is not used, this value is defaulted to\n // 0, else the following are the allowed \n // values:\n // 0 : No INJECTSBITERR or INJECTDBITERR pins\n // 1 : Only INJECTSBITERR pin exists\n // 2 : Only INJECTDBITERR pin exists\n // 3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n // C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision\n // warnings. It can be \"ALL\", \"NONE\", \n // \"Warnings_Only\" or \"Generate_X_Only\".\n // C_COMMON_CLK : Determins if the core has a single CLK input.\n // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n // warnings\n //////////////////////////////////////////////////////////////////////////\n // Port Definitions\n //////////////////////////////////////////////////////////////////////////\n // CLKA : Clock to synchronize all read and write operations of Port A.\n // RSTA : Reset input to reset memory outputs to a user-defined \n // reset state for Port A.\n // ENA : Enable all read and write operations of Port A.\n // REGCEA : Register Clock Enable to control each pipeline output\n // register stages for Port A.\n // WEA : Write Enable to enable all write operations of Port A.\n // ADDRA : Address of Port A.\n // DINA : Data input of Port A.\n // DOUTA : Data output of Port A.\n // CLKB : Clock to synchronize all read and write operations of Port B.\n // RSTB : Reset input to reset memory outputs to a user-defined \n // reset state for Port B.\n // ENB : Enable all read and write operations of Port B.\n // REGCEB : Register Clock Enable to control each pipeline output\n // register stages for Port B.\n // WEB : Write Enable to enable all write operations of Port B.\n // ADDRB : Address of Port B.\n // DINB : Data input of Port B.\n // DOUTB : Data output of Port B.\n // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n // SBITERR : Output signal indicating that a Single Bit ECC Error has been\n // detected and corrected.\n // DBITERR : Output signal indicating that a Double Bit ECC Error has been\n // detected.\n // RDADDRECC : Read Address Output signal indicating address at which an\n // ECC error has occurred.\n //////////////////////////////////////////////////////////////////////////\n\n\n// Note: C_CORENAME parameter is hard-coded to \"blk_mem_gen_v8_3_4\" and it is\n// only used by this module to print warning messages. It is neither passed \n// down from blk_mem_gen_v8_3_4_xst.v nor present in the instantiation template\n// coregen generates\n \n //***************************************************************************\n // constants for the core behavior\n //***************************************************************************\n // file handles for logging\n //--------------------------------------------------\n localparam ADDRFILE = 32'h8000_0001; //stdout for addr out of range\n localparam COLLFILE = 32'h8000_0001; //stdout for coll detection\n localparam ERRFILE = 32'h8000_0001; //stdout for file I/O errors\n\n // other constants\n //--------------------------------------------------\n localparam COLL_DELAY = 100; // 100 ps\n\n // locally derived parameters to determine memory shape\n //-----------------------------------------------------\n\n localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); \n\n localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?\n C_WRITE_WIDTH_A : C_READ_WIDTH_A;\n localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?\n C_WRITE_WIDTH_B : C_READ_WIDTH_B;\n localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?\n MIN_WIDTH_A : MIN_WIDTH_B;\n\n localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?\n C_WRITE_DEPTH_A : C_READ_DEPTH_A;\n localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?\n C_WRITE_DEPTH_B : C_READ_DEPTH_B;\n localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?\n MAX_DEPTH_A : MAX_DEPTH_B;\n\n\n // locally derived parameters to assist memory access\n //----------------------------------------------------\n // Calculate the width ratios of each port with respect to the narrowest\n // port\n localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;\n localparam READ_WIDTH_RATIO_A = C_READ_WIDTH_A/MIN_WIDTH;\n localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;\n localparam READ_WIDTH_RATIO_B = C_READ_WIDTH_B/MIN_WIDTH;\n\n // To modify the LSBs of the 'wider' data to the actual\n // address value\n //----------------------------------------------------\n localparam WRITE_ADDR_A_DIV = C_WRITE_WIDTH_A/MIN_WIDTH_A;\n localparam READ_ADDR_A_DIV = C_READ_WIDTH_A/MIN_WIDTH_A;\n localparam WRITE_ADDR_B_DIV = C_WRITE_WIDTH_B/MIN_WIDTH_B;\n localparam READ_ADDR_B_DIV = C_READ_WIDTH_B/MIN_WIDTH_B;\n\n // If byte writes aren't being used, make sure BYTE_SIZE is not\n // wider than the memory elements to avoid compilation warnings\n localparam BYTE_SIZE = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;\n\n // The memory\n reg [MIN_WIDTH-1:0] memory [0:MAX_DEPTH-1];\n reg [MIN_WIDTH-1:0] temp_mem_array [0:MAX_DEPTH-1];\n reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;\n // ECC error arrays\n reg sbiterr_arr [0:MAX_DEPTH-1];\n reg dbiterr_arr [0:MAX_DEPTH-1];\n\n reg softecc_sbiterr_arr [0:MAX_DEPTH-1];\n reg softecc_dbiterr_arr [0:MAX_DEPTH-1];\n // Memory output 'latches'\n reg [C_READ_WIDTH_A-1:0] memory_out_a;\n reg [C_READ_WIDTH_B-1:0] memory_out_b;\n\n // ECC error inputs and outputs from output_stage module:\n reg sbiterr_in;\n wire sbiterr_sdp;\n reg dbiterr_in;\n wire dbiterr_sdp;\n\n wire [C_READ_WIDTH_B-1:0] dout_i;\n wire dbiterr_i;\n wire sbiterr_i;\n wire [C_ADDRB_WIDTH-1:0] rdaddrecc_i;\n\n reg [C_ADDRB_WIDTH-1:0] rdaddrecc_in;\n wire [C_ADDRB_WIDTH-1:0] rdaddrecc_sdp;\n\n // Reset values\n reg [C_READ_WIDTH_A-1:0] inita_val;\n reg [C_READ_WIDTH_B-1:0] initb_val;\n\n // Collision detect\n reg is_collision;\n reg is_collision_a, is_collision_delay_a;\n reg is_collision_b, is_collision_delay_b;\n\n // Temporary variables for initialization\n //---------------------------------------\n integer status;\n integer initfile;\n integer meminitfile;\n // data input buffer\n reg [C_WRITE_WIDTH_A-1:0] mif_data;\n reg [C_WRITE_WIDTH_A-1:0] mem_data;\n // string values in hex\n reg [C_READ_WIDTH_A*8-1:0] inita_str = C_INITA_VAL;\n reg [C_READ_WIDTH_B*8-1:0] initb_str = C_INITB_VAL;\n reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA;\n // initialization filename\n reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME;\n reg [1023*8-1:0] mem_init_file_str = C_INIT_FILE;\n\n\n //Constants used to calculate the effective address widths for each of the \n //four ports. \n integer cnt = 1;\n integer write_addr_a_width, read_addr_a_width;\n integer write_addr_b_width, read_addr_b_width;\n\n localparam C_FAMILY_LOCALPARAM = (C_FAMILY==\"zynquplus\"?\"virtex7\":(C_FAMILY==\"kintexuplus\"?\"virtex7\":(C_FAMILY==\"virtexuplus\"?\"virtex7\":(C_FAMILY==\"virtexu\"?\"virtex7\":(C_FAMILY==\"kintexu\" ? \"virtex7\":(C_FAMILY==\"virtex7\" ? \"virtex7\" : (C_FAMILY==\"virtex7l\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7\" ? \"virtex7\" : (C_FAMILY==\"qvirtex7l\" ? \"virtex7\" : (C_FAMILY==\"kintex7\" ? \"virtex7\" : (C_FAMILY==\"kintex7l\" ? \"virtex7\" : (C_FAMILY==\"qkintex7\" ? \"virtex7\" : (C_FAMILY==\"qkintex7l\" ? \"virtex7\" : (C_FAMILY==\"artix7\" ? \"virtex7\" : (C_FAMILY==\"artix7l\" ? \"virtex7\" : (C_FAMILY==\"qartix7\" ? \"virtex7\" : (C_FAMILY==\"qartix7l\" ? \"virtex7\" : (C_FAMILY==\"aartix7\" ? \"virtex7\" : (C_FAMILY==\"zynq\" ? \"virtex7\" : (C_FAMILY==\"azynq\" ? \"virtex7\" : (C_FAMILY==\"qzynq\" ? \"virtex7\" : C_FAMILY)))))))))))))))))))));\n\n // Internal configuration parameters\n //---------------------------------------------\n localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);\n localparam IS_ROM = (C_MEM_TYPE==3 || C_MEM_TYPE==4);\n localparam HAS_A_WRITE = (!IS_ROM);\n localparam HAS_B_WRITE = (C_MEM_TYPE==2);\n localparam HAS_A_READ = (C_MEM_TYPE!=1);\n localparam HAS_B_READ = (!SINGLE_PORT);\n localparam HAS_B_PORT = (HAS_B_READ || HAS_B_WRITE);\n\n // Calculate the mux pipeline register stages for Port A and Port B\n //------------------------------------------------------------------\n localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?\n C_MUX_PIPELINE_STAGES : 0;\n localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?\n C_MUX_PIPELINE_STAGES : 0;\n \n // Calculate total number of register stages in the core\n // -----------------------------------------------------\n localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);\n\n localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);\n\n wire ena_i;\n wire enb_i;\n wire reseta_i;\n wire resetb_i;\n wire [C_WEA_WIDTH-1:0] wea_i;\n wire [C_WEB_WIDTH-1:0] web_i;\n wire rea_i;\n wire reb_i;\n wire rsta_outp_stage;\n wire rstb_outp_stage;\n // ECC SBITERR/DBITERR Outputs\n // The ECC Behavior is modeled by the behavioral models only for Virtex-6.\n // For Virtex-5, these outputs will be tied to 0.\n assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;\n assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;\n assign RDADDRECC = (((C_FAMILY_LOCALPARAM == \"virtex7\") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;\n\n\n // This effectively wires off optional inputs\n assign ena_i = (C_HAS_ENA==0) || ENA;\n assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;\n //assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;\n // To Fix CR855535\n assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;\n assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;\n assign rea_i = (HAS_A_READ) ? ena_i : 'b0;\n assign reb_i = (HAS_B_READ) ? enb_i : 'b0;\n\n // These signals reset the memory latches\n\n assign reseta_i = \n ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||\n (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));\n\n assign resetb_i = \n ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||\n (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));\n\n // Tasks to access the memory\n //---------------------------\n //**************\n // write_a\n //**************\n task write_a\n (input reg [C_ADDRA_WIDTH-1:0] addr,\n input reg [C_WEA_WIDTH-1:0] byte_en,\n input reg [C_WRITE_WIDTH_A-1:0] data,\n input inj_sbiterr,\n input inj_dbiterr);\n reg [C_WRITE_WIDTH_A-1:0] current_contents;\n reg [C_ADDRA_WIDTH-1:0] address;\n integer i;\n begin\n // Shift the address by the ratio\n address = (addr/WRITE_ADDR_A_DIV);\n if (address >= C_WRITE_DEPTH_A) begin\n if (!C_DISABLE_WARN_BHV_RANGE) begin\n $fdisplay(ADDRFILE,\n \"%0s WARNING: Address %0h is outside range for A Write\",\n C_CORENAME, addr);\n end\n\n // valid address\n end else begin\n\n // Combine w/ byte writes\n if (C_USE_BYTE_WEA) begin\n\n // Get the current memory contents\n if (WRITE_WIDTH_RATIO_A == 1) begin\n // Workaround for IUS 5.5 part-select issue\n current_contents = memory[address];\n end else begin\n for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n = memory[address*WRITE_WIDTH_RATIO_A + i];\n end\n end\n\n // Apply incoming bytes\n if (C_WEA_WIDTH == 1) begin\n // Workaround for IUS 5.5 part-select issue\n if (byte_en[0]) begin\n current_contents = data;\n end\n end else begin\n for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin\n if (byte_en[i]) begin\n current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n = data[BYTE_SIZE*i+:BYTE_SIZE];\n end\n end\n end\n\n // No byte-writes, overwrite the whole word\n end else begin\n current_contents = data;\n end\n\n // Insert double bit errors:\n if (C_USE_ECC == 1) begin\n if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n// Modified for Implementing CR_859399 \n current_contents[0] = !(current_contents[30]);\n current_contents[1] = !(current_contents[62]);\n \n /*current_contents[0] = !(current_contents[0]);\n current_contents[1] = !(current_contents[1]);*/\n end\n end\n \n // Insert softecc double bit errors:\n if (C_USE_SOFTECC == 1) begin\n if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];\n doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];\n doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];\n current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];\n end\n end\n \n // Write data to memory\n if (WRITE_WIDTH_RATIO_A == 1) begin\n // Workaround for IUS 5.5 part-select issue\n memory[address*WRITE_WIDTH_RATIO_A] = current_contents;\n end else begin\n for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin\n memory[address*WRITE_WIDTH_RATIO_A + i]\n = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n end\n end\n\n // Store the address at which error is injected:\n if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n begin\n sbiterr_arr[addr] = 1;\n end else begin\n sbiterr_arr[addr] = 0;\n end\n \n if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n dbiterr_arr[addr] = 1;\n end else begin\n dbiterr_arr[addr] = 0;\n end\n end\n\n // Store the address at which softecc error is injected:\n if (C_USE_SOFTECC == 1) begin\n if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || \n (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))\n begin\n softecc_sbiterr_arr[addr] = 1;\n end else begin\n softecc_sbiterr_arr[addr] = 0;\n end\n \n if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin\n softecc_dbiterr_arr[addr] = 1;\n end else begin\n softecc_dbiterr_arr[addr] = 0;\n end\n end\n\n end\n end\n endtask\n\n //**************\n // write_b\n //**************\n task write_b\n (input reg [C_ADDRB_WIDTH-1:0] addr,\n input reg [C_WEB_WIDTH-1:0] byte_en,\n input reg [C_WRITE_WIDTH_B-1:0] data);\n reg [C_WRITE_WIDTH_B-1:0] current_contents;\n reg [C_ADDRB_WIDTH-1:0] address;\n integer i;\n begin\n // Shift the address by the ratio\n address = (addr/WRITE_ADDR_B_DIV);\n if (address >= C_WRITE_DEPTH_B) begin\n if (!C_DISABLE_WARN_BHV_RANGE) begin\n $fdisplay(ADDRFILE,\n \"%0s WARNING: Address %0h is outside range for B Write\",\n C_CORENAME, addr);\n end\n\n // valid address\n end else begin\n\n // Combine w/ byte writes\n if (C_USE_BYTE_WEB) begin\n\n // Get the current memory contents\n if (WRITE_WIDTH_RATIO_B == 1) begin\n // Workaround for IUS 5.5 part-select issue\n current_contents = memory[address];\n end else begin\n for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n current_contents[MIN_WIDTH*i+:MIN_WIDTH]\n = memory[address*WRITE_WIDTH_RATIO_B + i];\n end\n end\n\n // Apply incoming bytes\n if (C_WEB_WIDTH == 1) begin\n // Workaround for IUS 5.5 part-select issue\n if (byte_en[0]) begin\n current_contents = data;\n end\n end else begin\n for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin\n if (byte_en[i]) begin\n current_contents[BYTE_SIZE*i+:BYTE_SIZE]\n = data[BYTE_SIZE*i+:BYTE_SIZE];\n end\n end\n end\n\n // No byte-writes, overwrite the whole word\n end else begin\n current_contents = data;\n end\n\n // Write data to memory\n if (WRITE_WIDTH_RATIO_B == 1) begin\n // Workaround for IUS 5.5 part-select issue\n memory[address*WRITE_WIDTH_RATIO_B] = current_contents;\n end else begin\n for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin\n memory[address*WRITE_WIDTH_RATIO_B + i]\n = current_contents[MIN_WIDTH*i+:MIN_WIDTH];\n end\n end\n end\n end\n endtask\n\n //**************\n // read_a\n //**************\n task read_a\n (input reg [C_ADDRA_WIDTH-1:0] addr,\n input reg reset);\n reg [C_ADDRA_WIDTH-1:0] address;\n integer i;\n begin\n\n if (reset) begin\n memory_out_a <= #FLOP_DELAY inita_val;\n end else begin\n // Shift the address by the ratio\n address = (addr/READ_ADDR_A_DIV);\n if (address >= C_READ_DEPTH_A) begin\n if (!C_DISABLE_WARN_BHV_RANGE) begin\n $fdisplay(ADDRFILE,\n \"%0s WARNING: Address %0h is outside range for A Read\",\n C_CORENAME, addr);\n end\n memory_out_a <= #FLOP_DELAY 'bX;\n // valid address\n end else begin\n if (READ_WIDTH_RATIO_A==1) begin\n memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];\n end else begin\n // Increment through the 'partial' words in the memory\n for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin\n memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]\n <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];\n end\n end //end READ_WIDTH_RATIO_A==1 loop\n\n end //end valid address loop\n end //end reset-data assignment loops\n end\n endtask\n\n //**************\n // read_b\n //**************\n task read_b\n (input reg [C_ADDRB_WIDTH-1:0] addr,\n input reg reset);\n reg [C_ADDRB_WIDTH-1:0] address;\n integer i;\n begin\n\n if (reset) begin\n memory_out_b <= #FLOP_DELAY initb_val;\n sbiterr_in <= #FLOP_DELAY 1'b0;\n dbiterr_in <= #FLOP_DELAY 1'b0;\n rdaddrecc_in <= #FLOP_DELAY 0;\n end else begin\n // Shift the address\n address = (addr/READ_ADDR_B_DIV);\n if (address >= C_READ_DEPTH_B) begin\n if (!C_DISABLE_WARN_BHV_RANGE) begin\n $fdisplay(ADDRFILE,\n \"%0s WARNING: Address %0h is outside range for B Read\",\n C_CORENAME, addr);\n end\n memory_out_b <= #FLOP_DELAY 'bX;\n sbiterr_in <= #FLOP_DELAY 1'bX;\n dbiterr_in <= #FLOP_DELAY 1'bX;\n rdaddrecc_in <= #FLOP_DELAY 'bX;\n // valid address\n end else begin\n if (READ_WIDTH_RATIO_B==1) begin\n memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];\n end else begin\n // Increment through the 'partial' words in the memory\n for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin\n memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]\n <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];\n end\n end\n\n if ((C_FAMILY_LOCALPARAM == \"virtex7\") && C_USE_ECC == 1) begin\n rdaddrecc_in <= #FLOP_DELAY addr;\n if (sbiterr_arr[addr] == 1) begin\n sbiterr_in <= #FLOP_DELAY 1'b1;\n end else begin\n sbiterr_in <= #FLOP_DELAY 1'b0;\n end\n\n if (dbiterr_arr[addr] == 1) begin\n dbiterr_in <= #FLOP_DELAY 1'b1;\n end else begin\n dbiterr_in <= #FLOP_DELAY 1'b0;\n end\n\n end else if (C_USE_SOFTECC == 1) begin\n rdaddrecc_in <= #FLOP_DELAY addr;\n if (softecc_sbiterr_arr[addr] == 1) begin\n sbiterr_in <= #FLOP_DELAY 1'b1;\n end else begin\n sbiterr_in <= #FLOP_DELAY 1'b0;\n end\n\n if (softecc_dbiterr_arr[addr] == 1) begin\n dbiterr_in <= #FLOP_DELAY 1'b1;\n end else begin\n dbiterr_in <= #FLOP_DELAY 1'b0;\n end\n end else begin\n rdaddrecc_in <= #FLOP_DELAY 0;\n dbiterr_in <= #FLOP_DELAY 1'b0;\n sbiterr_in <= #FLOP_DELAY 1'b0;\n end //end SOFTECC Loop\n end //end Valid address loop\n end //end reset-data assignment loops\n end\n endtask\n\n //**************\n // reset_a\n //**************\n task reset_a (input reg reset);\n begin\n if (reset) memory_out_a <= #FLOP_DELAY inita_val;\n end\n endtask\n\n //**************\n // reset_b\n //**************\n task reset_b (input reg reset);\n begin\n if (reset) memory_out_b <= #FLOP_DELAY initb_val;\n end\n endtask\n\n //**************\n // init_memory\n //**************\n task init_memory;\n integer i, j, addr_step;\n integer status;\n reg [C_WRITE_WIDTH_A-1:0] default_data;\n begin\n default_data = 0;\n\n //Display output message indicating that the behavioral model is being \n //initialized\n if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(\" Block Memory Generator module loading initial data...\");\n\n // Convert the default to hex\n if (C_USE_DEFAULT_DATA) begin\n if (default_data_str == \"\") begin\n $fdisplay(ERRFILE, \"%0s ERROR: C_DEFAULT_DATA is empty!\", C_CORENAME);\n $finish;\n end else begin\n status = $sscanf(default_data_str, \"%h\", default_data);\n if (status == 0) begin\n $fdisplay(ERRFILE, {\"%0s ERROR: Unsuccessful hexadecimal read\",\n \"from C_DEFAULT_DATA: %0s\"},\n C_CORENAME, C_DEFAULT_DATA);\n $finish;\n end\n end\n end\n\n // Step by WRITE_ADDR_A_DIV through the memory via the\n // Port A write interface to hit every location once\n addr_step = WRITE_ADDR_A_DIV;\n\n // 'write' to every location with default (or 0)\n for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);\n end\n\n // Get specialized data from the MIF file\n if (C_LOAD_INIT_FILE) begin\n if (init_file_str == \"\") begin\n $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE_NAME is empty!\",\n C_CORENAME);\n $finish;\n end else begin\n initfile = $fopen(init_file_str, \"r\");\n if (initfile == 0) begin\n $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n \"C_INIT_FILE_NAME: %0s!\"},\n C_CORENAME, init_file_str);\n $finish;\n end else begin\n // loop through the mif file, loading in the data\n for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin\n status = $fscanf(initfile, \"%b\", mif_data);\n if (status > 0) begin\n write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);\n end\n end\n $fclose(initfile);\n end //initfile\n end //init_file_str\n end //C_LOAD_INIT_FILE\n\n\n if (C_USE_BRAM_BLOCK) begin\n // Get specialized data from the MIF file\n if (C_INIT_FILE != \"NONE\") begin\n if (mem_init_file_str == \"\") begin\n $fdisplay(ERRFILE, \"%0s ERROR: C_INIT_FILE is empty!\",\n C_CORENAME);\n $finish;\n end else begin\n meminitfile = $fopen(mem_init_file_str, \"r\");\n if (meminitfile == 0) begin\n $fdisplay(ERRFILE, {\"%0s, ERROR: Problem opening\",\n \"C_INIT_FILE: %0s!\"},\n C_CORENAME, mem_init_file_str);\n $finish;\n end else begin\n // loop through the mif file, loading in the data\n $readmemh(mem_init_file_str, memory );\n for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin\n end \n $fclose(meminitfile);\n end //meminitfile\n end //mem_init_file_str\n end //C_INIT_FILE\n end //C_USE_BRAM_BLOCK\n\n //Display output message indicating that the behavioral model is done \n //initializing\n if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) \n $display(\" Block Memory Generator data initialization complete.\");\n end\n endtask\n\n //**************\n // log2roundup\n //**************\n function integer log2roundup (input integer data_value);\n integer width;\n integer cnt;\n begin\n width = 0;\n\n if (data_value > 1) begin\n for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n width = width + 1;\n end //loop\n end //if\n\n log2roundup = width;\n\n end //log2roundup\n endfunction\n\n\n //*******************\n // collision_check\n //*******************\n function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,\n input integer iswrite_a,\n input reg [C_ADDRB_WIDTH-1:0] addr_b,\n input integer iswrite_b);\n reg c_aw_bw, c_aw_br, c_ar_bw;\n integer scaled_addra_to_waddrb_width;\n integer scaled_addrb_to_waddrb_width;\n integer scaled_addra_to_waddra_width;\n integer scaled_addrb_to_waddra_width;\n integer scaled_addra_to_raddrb_width;\n integer scaled_addrb_to_raddrb_width;\n integer scaled_addra_to_raddra_width;\n integer scaled_addrb_to_raddra_width;\n\n\n\n begin\n\n c_aw_bw = 0;\n c_aw_br = 0;\n c_ar_bw = 0;\n\n //If write_addr_b_width is smaller, scale both addresses to that width for \n //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n //scale it down to write_addr_b_width. Once both are scaled to \n //write_addr_b_width, compare.\n scaled_addra_to_waddrb_width = ((addr_a)/\n 2**(C_ADDRA_WIDTH-write_addr_b_width));\n scaled_addrb_to_waddrb_width = ((addr_b)/\n 2**(C_ADDRB_WIDTH-write_addr_b_width));\n\n //If write_addr_a_width is smaller, scale both addresses to that width for \n //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n //scale it down to write_addr_a_width. Once both are scaled to \n //write_addr_a_width, compare.\n scaled_addra_to_waddra_width = ((addr_a)/\n 2**(C_ADDRA_WIDTH-write_addr_a_width));\n scaled_addrb_to_waddra_width = ((addr_b)/\n 2**(C_ADDRB_WIDTH-write_addr_a_width));\n\n //If read_addr_b_width is smaller, scale both addresses to that width for \n //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,\n //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,\n //scale it down to read_addr_b_width. Once both are scaled to \n //read_addr_b_width, compare.\n scaled_addra_to_raddrb_width = ((addr_a)/\n 2**(C_ADDRA_WIDTH-read_addr_b_width));\n scaled_addrb_to_raddrb_width = ((addr_b)/\n 2**(C_ADDRB_WIDTH-read_addr_b_width));\n\n //If read_addr_a_width is smaller, scale both addresses to that width for \n //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,\n //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,\n //scale it down to read_addr_a_width. Once both are scaled to \n //read_addr_a_width, compare.\n scaled_addra_to_raddra_width = ((addr_a)/\n 2**(C_ADDRA_WIDTH-read_addr_a_width));\n scaled_addrb_to_raddra_width = ((addr_b)/\n 2**(C_ADDRB_WIDTH-read_addr_a_width));\n\n //Look for a write-write collision. In order for a write-write\n //collision to exist, both ports must have a write transaction.\n if (iswrite_a && iswrite_b) begin\n if (write_addr_a_width > write_addr_b_width) begin\n if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n c_aw_bw = 1;\n end else begin\n c_aw_bw = 0;\n end\n end else begin\n if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n c_aw_bw = 1;\n end else begin\n c_aw_bw = 0;\n end\n end //width\n end //iswrite_a and iswrite_b\n\n //If the B port is reading (which means it is enabled - so could be\n //a TX_WRITE or TX_READ), then check for a write-read collision).\n //This could happen whether or not a write-write collision exists due\n //to asymmetric write/read ports.\n if (iswrite_a) begin\n if (write_addr_a_width > read_addr_b_width) begin\n if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin\n c_aw_br = 1;\n end else begin\n c_aw_br = 0;\n end\n end else begin\n if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin\n c_aw_br = 1;\n end else begin\n c_aw_br = 0;\n end\n end //width\n end //iswrite_a\n\n //If the A port is reading (which means it is enabled - so could be\n // a TX_WRITE or TX_READ), then check for a write-read collision).\n //This could happen whether or not a write-write collision exists due\n // to asymmetric write/read ports.\n if (iswrite_b) begin\n if (read_addr_a_width > write_addr_b_width) begin\n if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin\n c_ar_bw = 1;\n end else begin\n c_ar_bw = 0;\n end\n end else begin\n if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin\n c_ar_bw = 1;\n end else begin\n c_ar_bw = 0;\n end\n end //width\n end //iswrite_b\n\n\n\n collision_check = c_aw_bw | c_aw_br | c_ar_bw;\n\n end\n endfunction\n\n //*******************************\n // power on values\n //*******************************\n initial begin\n // Load up the memory\n init_memory;\n // Load up the output registers and latches\n if ($sscanf(inita_str, \"%h\", inita_val)) begin\n memory_out_a = inita_val;\n end else begin\n memory_out_a = 0;\n end\n if ($sscanf(initb_str, \"%h\", initb_val)) begin\n memory_out_b = initb_val;\n end else begin\n memory_out_b = 0;\n end\n\n sbiterr_in = 1'b0;\n dbiterr_in = 1'b0;\n rdaddrecc_in = 0;\n\n // Determine the effective address widths for each of the 4 ports\n write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);\n read_addr_a_width = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);\n write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);\n read_addr_b_width = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);\n\n $display(\"Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.\");\n\n end\n\n //***************************************************************************\n // These are the main blocks which schedule read and write operations\n // Note that the reset priority feature at the latch stage is only supported\n // for Spartan-6. For other families, the default priority at the latch stage\n // is \"CE\"\n //***************************************************************************\n // Synchronous clocks: schedule port operations with respect to\n // both write operating modes\n generate\n if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n \"WRITE_FIRST\")) begin : com_clk_sched_wf_wf\n always @(posedge CLKA) begin\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n \n if (rea_i) read_a(ADDRA, reseta_i);\n \n //Read B\n if (reb_i) read_b(ADDRB, resetb_i);\n end\n end\n else \n if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n \"WRITE_FIRST\")) begin : com_clk_sched_rf_wf\n always @(posedge CLKA) begin\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n //Read B\n if (reb_i) read_b(ADDRB, resetb_i);\n //Read A\n if (rea_i) read_a(ADDRA, reseta_i);\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n end\n end\n else \n if(C_COMMON_CLK && (C_WRITE_MODE_A == \"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n \"READ_FIRST\")) begin : com_clk_sched_wf_rf\n always @(posedge CLKA) begin\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n //Read A\n if (rea_i) read_a(ADDRA, reseta_i);\n //Read B\n if (reb_i) read_b(ADDRB, resetb_i);\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n end\n end\n else \n if(C_COMMON_CLK && (C_WRITE_MODE_A == \"READ_FIRST\") && (C_WRITE_MODE_B ==\n \"READ_FIRST\")) begin : com_clk_sched_rf_rf\n always @(posedge CLKA) begin\n //Read A\n if (rea_i) read_a(ADDRA, reseta_i);\n //Read B\n if (reb_i) read_b(ADDRB, resetb_i);\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n end\n end\n else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"WRITE_FIRST\") && (C_WRITE_MODE_B ==\n \"NO_CHANGE\")) begin : com_clk_sched_wf_nc\n always @(posedge CLKA) begin\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n //Read A\n if (rea_i) read_a(ADDRA, reseta_i);\n //Read B\n if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n end\n end\n else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"READ_FIRST\") && (C_WRITE_MODE_B ==\n \"NO_CHANGE\")) begin : com_clk_sched_rf_nc\n always @(posedge CLKA) begin\n //Read A\n if (rea_i) read_a(ADDRA, reseta_i);\n //Read B\n if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n end\n end\n else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n \"WRITE_FIRST\")) begin : com_clk_sched_nc_wf\n always @(posedge CLKA) begin\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n //Read A\n if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n //Read B\n if (reb_i) read_b(ADDRB, resetb_i);\n end\n end\n else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B == \n \"READ_FIRST\")) begin : com_clk_sched_nc_rf\n always @(posedge CLKA) begin\n //Read B\n if (reb_i) read_b(ADDRB, resetb_i);\n //Read A\n if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n end\n end\n else if(C_COMMON_CLK && (C_WRITE_MODE_A ==\"NO_CHANGE\") && (C_WRITE_MODE_B ==\n \"NO_CHANGE\")) begin : com_clk_sched_nc_nc\n always @(posedge CLKA) begin\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n //Read A\n if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n //Read B\n if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n end\n end\n else if(C_COMMON_CLK) begin: com_clk_sched_default\n always @(posedge CLKA) begin\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n //Read A\n if (rea_i) read_a(ADDRA, reseta_i);\n //Read B\n if (reb_i) read_b(ADDRB, resetb_i);\n end\n end\n endgenerate\n\n // Asynchronous clocks: port operation is independent\n generate\n if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"WRITE_FIRST\")) begin : async_clk_sched_clka_wf\n always @(posedge CLKA) begin\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n //Read A\n if (rea_i) read_a(ADDRA, reseta_i);\n end\n end\n else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"READ_FIRST\")) begin : async_clk_sched_clka_rf\n always @(posedge CLKA) begin\n //Read A\n if (rea_i) read_a(ADDRA, reseta_i);\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n end\n end\n else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == \"NO_CHANGE\")) begin : async_clk_sched_clka_nc\n always @(posedge CLKA) begin\n //Write A\n if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);\n //Read A\n if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);\n end\n end\n endgenerate\n\n generate \n if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"WRITE_FIRST\")) begin: async_clk_sched_clkb_wf\n always @(posedge CLKB) begin\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n //Read B\n if (reb_i) read_b(ADDRB, resetb_i);\n end\n end\n else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"READ_FIRST\")) begin: async_clk_sched_clkb_rf\n always @(posedge CLKB) begin\n //Read B\n if (reb_i) read_b(ADDRB, resetb_i);\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n end\n end\n else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == \"NO_CHANGE\")) begin: async_clk_sched_clkb_nc\n always @(posedge CLKB) begin\n //Write B\n if (web_i) write_b(ADDRB, web_i, DINB);\n //Read B\n if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);\n end\n end\n endgenerate\n\n \n //***************************************************************\n // Instantiate the variable depth output register stage module\n //***************************************************************\n // Port A\n \n assign rsta_outp_stage = RSTA & (~SLEEP);\n\n blk_mem_gen_v8_3_4_output_stage\n #(.C_FAMILY (C_FAMILY),\n .C_XDEVICEFAMILY (C_XDEVICEFAMILY),\n .C_RST_TYPE (\"SYNC\"),\n .C_HAS_RST (C_HAS_RSTA),\n .C_RSTRAM (C_RSTRAM_A),\n .C_RST_PRIORITY (C_RST_PRIORITY_A),\n .C_INIT_VAL (C_INITA_VAL),\n .C_HAS_EN (C_HAS_ENA),\n .C_HAS_REGCE (C_HAS_REGCEA),\n .C_DATA_WIDTH (C_READ_WIDTH_A),\n .C_ADDRB_WIDTH (C_ADDRB_WIDTH),\n .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A),\n .C_USE_SOFTECC (C_USE_SOFTECC),\n .C_USE_ECC (C_USE_ECC),\n .NUM_STAGES (NUM_OUTPUT_STAGES_A),\n\t .C_EN_ECC_PIPE (0),\n .FLOP_DELAY (FLOP_DELAY))\n reg_a\n (.CLK (CLKA),\n .RST (rsta_outp_stage),//(RSTA),\n .EN (ENA),\n .REGCE (REGCEA),\n .DIN_I (memory_out_a),\n .DOUT (DOUTA),\n .SBITERR_IN_I (1'b0),\n .DBITERR_IN_I (1'b0),\n .SBITERR (),\n .DBITERR (),\n .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),\n\t\t .ECCPIPECE (1'b0),\n .RDADDRECC ()\n );\n\n assign rstb_outp_stage = RSTB & (~SLEEP);\n\n // Port B \n blk_mem_gen_v8_3_4_output_stage\n #(.C_FAMILY (C_FAMILY),\n .C_XDEVICEFAMILY (C_XDEVICEFAMILY),\n .C_RST_TYPE (\"SYNC\"),\n .C_HAS_RST (C_HAS_RSTB),\n .C_RSTRAM (C_RSTRAM_B),\n .C_RST_PRIORITY (C_RST_PRIORITY_B),\n .C_INIT_VAL (C_INITB_VAL),\n .C_HAS_EN (C_HAS_ENB),\n .C_HAS_REGCE (C_HAS_REGCEB),\n .C_DATA_WIDTH (C_READ_WIDTH_B),\n .C_ADDRB_WIDTH (C_ADDRB_WIDTH),\n .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B),\n .C_USE_SOFTECC (C_USE_SOFTECC),\n .C_USE_ECC (C_USE_ECC),\n .NUM_STAGES (NUM_OUTPUT_STAGES_B),\n .C_EN_ECC_PIPE (C_EN_ECC_PIPE),\n .FLOP_DELAY (FLOP_DELAY))\n reg_b\n (.CLK (CLKB),\n .RST (rstb_outp_stage),//(RSTB),\n .EN (ENB),\n .REGCE (REGCEB),\n .DIN_I (memory_out_b),\n .DOUT (dout_i),\n .SBITERR_IN_I (sbiterr_in),\n .DBITERR_IN_I (dbiterr_in),\n .SBITERR (sbiterr_i),\n .DBITERR (dbiterr_i),\n .RDADDRECC_IN_I (rdaddrecc_in),\n .ECCPIPECE (ECCPIPECE),\n .RDADDRECC (rdaddrecc_i)\n );\n\n //***************************************************************\n // Instantiate the Input and Output register stages\n //***************************************************************\nblk_mem_gen_v8_3_4_softecc_output_reg_stage\n #(.C_DATA_WIDTH (C_READ_WIDTH_B),\n .C_ADDRB_WIDTH (C_ADDRB_WIDTH),\n .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),\n .C_USE_SOFTECC (C_USE_SOFTECC),\n .FLOP_DELAY (FLOP_DELAY))\n has_softecc_output_reg_stage\n (.CLK (CLKB),\n .DIN (dout_i),\n .DOUT (DOUTB),\n .SBITERR_IN (sbiterr_i),\n .DBITERR_IN (dbiterr_i),\n .SBITERR (sbiterr_sdp),\n .DBITERR (dbiterr_sdp),\n .RDADDRECC_IN (rdaddrecc_i),\n .RDADDRECC (rdaddrecc_sdp)\n);\n\n //****************************************************\n // Synchronous collision checks\n //****************************************************\n// CR 780544 : To make verilog model's collison warnings in consistant with\n// vhdl model, the non-blocking assignments are replaced with blocking \n// assignments.\n generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll\n always @(posedge CLKA) begin\n // Possible collision if both are enabled and the addresses match\n if (ena_i && enb_i) begin\n if (wea_i || web_i) begin\n is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);\n end else begin\n is_collision = 0;\n end\n end else begin\n is_collision = 0;\n end\n\n // If the write port is in READ_FIRST mode, there is no collision\n if (C_WRITE_MODE_A==\"READ_FIRST\" && wea_i && !web_i) begin\n is_collision = 0;\n end\n if (C_WRITE_MODE_B==\"READ_FIRST\" && web_i && !wea_i) begin\n is_collision = 0;\n end\n\n // Only flag if one of the accesses is a write\n if (is_collision && (wea_i || web_i)) begin\n $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n C_CORENAME, $time);\n $fwrite(COLLFILE, \"A %0s address: %0h, B %0s address: %0h\\n\",\n wea_i ? \"write\" : \"read\", ADDRA,\n web_i ? \"write\" : \"read\", ADDRB);\n end\n end\n\n //****************************************************\n // Asynchronous collision checks\n //****************************************************\n end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll\n\n // Delay A and B addresses in order to mimic setup/hold times\n wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA;\n wire [0:0] #COLL_DELAY wea_delay = wea_i;\n wire #COLL_DELAY ena_delay = ena_i;\n wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB;\n wire [0:0] #COLL_DELAY web_delay = web_i;\n wire #COLL_DELAY enb_delay = enb_i;\n\n // Do the checks w/rt A\n always @(posedge CLKA) begin\n // Possible collision if both are enabled and the addresses match\n if (ena_i && enb_i) begin\n if (wea_i || web_i) begin\n is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);\n end else begin\n is_collision_a = 0;\n end\n end else begin\n is_collision_a = 0;\n end\n\n if (ena_i && enb_delay) begin\n if(wea_i || web_delay) begin\n is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,\n web_delay);\n end else begin\n is_collision_delay_a = 0;\n end\n end else begin\n is_collision_delay_a = 0;\n end\n\n // Only flag if B access is a write\n if (is_collision_a && web_i) begin\n $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n C_CORENAME, $time);\n $fwrite(COLLFILE, \"A %0s address: %0h, B write address: %0h\\n\",\n wea_i ? \"write\" : \"read\", ADDRA, ADDRB);\n\n end else if (is_collision_delay_a && web_delay) begin\n $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n C_CORENAME, $time);\n $fwrite(COLLFILE, \"A %0s address: %0h, B write address: %0h\\n\",\n wea_i ? \"write\" : \"read\", ADDRA, addrb_delay);\n end\n\n end\n\n // Do the checks w/rt B\n always @(posedge CLKB) begin\n\n // Possible collision if both are enabled and the addresses match\n if (ena_i && enb_i) begin\n if (wea_i || web_i) begin\n is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);\n end else begin\n is_collision_b = 0;\n end\n end else begin\n is_collision_b = 0;\n end\n\n if (ena_delay && enb_i) begin\n if (wea_delay || web_i) begin\n is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,\n web_i);\n end else begin\n is_collision_delay_b = 0;\n end\n end else begin\n is_collision_delay_b = 0;\n end\n\n\n // Only flag if A access is a write\n if (is_collision_b && wea_i) begin\n $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n C_CORENAME, $time);\n $fwrite(COLLFILE, \"A write address: %0h, B %s address: %0h\\n\",\n ADDRA, web_i ? \"write\" : \"read\", ADDRB);\n\n end else if (is_collision_delay_b && wea_delay) begin\n $fwrite(COLLFILE, \"%0s collision detected at time: %0d, \",\n C_CORENAME, $time);\n $fwrite(COLLFILE, \"A write address: %0h, B %s address: %0h\\n\",\n addra_delay, web_i ? \"write\" : \"read\", ADDRB);\n end\n\n end\n end\n endgenerate\n\nendmodule\n//*****************************************************************************\n// Top module wraps Input register and Memory module\n//\n// This module is the top-level behavioral model and this implements the memory \n// module and the input registers\n//*****************************************************************************\nmodule blk_mem_gen_v8_3_4\n #(parameter C_CORENAME = \"blk_mem_gen_v8_3_4\",\n parameter C_FAMILY = \"virtex7\",\n parameter C_XDEVICEFAMILY = \"virtex7\",\n parameter C_ELABORATION_DIR = \"\",\n parameter C_INTERFACE_TYPE = 0,\n parameter C_USE_BRAM_BLOCK = 0,\n parameter C_CTRL_ECC_ALGO = \"NONE\",\n parameter C_ENABLE_32BIT_ADDRESS = 0,\n parameter C_AXI_TYPE = 0,\n parameter C_AXI_SLAVE_TYPE = 0,\n parameter C_HAS_AXI_ID = 0,\n parameter C_AXI_ID_WIDTH = 4,\n parameter C_MEM_TYPE = 2,\n parameter C_BYTE_SIZE = 9,\n parameter C_ALGORITHM = 1,\n parameter C_PRIM_TYPE = 3,\n parameter C_LOAD_INIT_FILE = 0,\n parameter C_INIT_FILE_NAME = \"\",\n parameter C_INIT_FILE = \"\",\n parameter C_USE_DEFAULT_DATA = 0,\n parameter C_DEFAULT_DATA = \"0\",\n //parameter C_RST_TYPE = \"SYNC\",\n parameter C_HAS_RSTA = 0,\n parameter C_RST_PRIORITY_A = \"CE\",\n parameter C_RSTRAM_A = 0,\n parameter C_INITA_VAL = \"0\",\n parameter C_HAS_ENA = 1,\n parameter C_HAS_REGCEA = 0,\n parameter C_USE_BYTE_WEA = 0,\n parameter C_WEA_WIDTH = 1,\n parameter C_WRITE_MODE_A = \"WRITE_FIRST\",\n parameter C_WRITE_WIDTH_A = 32,\n parameter C_READ_WIDTH_A = 32,\n parameter C_WRITE_DEPTH_A = 64,\n parameter C_READ_DEPTH_A = 64,\n parameter C_ADDRA_WIDTH = 5,\n parameter C_HAS_RSTB = 0,\n parameter C_RST_PRIORITY_B = \"CE\",\n parameter C_RSTRAM_B = 0,\n parameter C_INITB_VAL = \"\",\n parameter C_HAS_ENB = 1,\n parameter C_HAS_REGCEB = 0,\n parameter C_USE_BYTE_WEB = 0,\n parameter C_WEB_WIDTH = 1,\n parameter C_WRITE_MODE_B = \"WRITE_FIRST\",\n parameter C_WRITE_WIDTH_B = 32,\n parameter C_READ_WIDTH_B = 32,\n parameter C_WRITE_DEPTH_B = 64,\n parameter C_READ_DEPTH_B = 64,\n parameter C_ADDRB_WIDTH = 5,\n parameter C_HAS_MEM_OUTPUT_REGS_A = 0,\n parameter C_HAS_MEM_OUTPUT_REGS_B = 0,\n parameter C_HAS_MUX_OUTPUT_REGS_A = 0,\n parameter C_HAS_MUX_OUTPUT_REGS_B = 0,\n parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,\n parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,\n parameter C_MUX_PIPELINE_STAGES = 0,\n parameter C_USE_SOFTECC = 0,\n parameter C_USE_ECC = 0,\n\tparameter C_EN_ECC_PIPE = 0,\n parameter C_HAS_INJECTERR = 0,\n parameter C_SIM_COLLISION_CHECK = \"NONE\",\n parameter C_COMMON_CLK = 1,\n parameter C_DISABLE_WARN_BHV_COLL = 0,\n\tparameter C_EN_SLEEP_PIN = 0,\n parameter C_USE_URAM = 0,\n parameter C_EN_RDADDRA_CHG = 0,\n parameter C_EN_RDADDRB_CHG = 0,\n parameter C_EN_DEEPSLEEP_PIN = 0,\n parameter C_EN_SHUTDOWN_PIN = 0,\n\tparameter C_EN_SAFETY_CKT = 0,\n\tparameter C_COUNT_36K_BRAM = \"\",\n\tparameter C_COUNT_18K_BRAM = \"\",\n\tparameter C_EST_POWER_SUMMARY = \"\",\n\tparameter C_DISABLE_WARN_BHV_RANGE = 0\n\t\n )\n (input clka,\n input rsta,\n input ena,\n input regcea,\n input [C_WEA_WIDTH-1:0] wea,\n input [C_ADDRA_WIDTH-1:0] addra,\n input [C_WRITE_WIDTH_A-1:0] dina,\n output [C_READ_WIDTH_A-1:0] douta,\n input clkb,\n input rstb,\n input enb,\n input regceb,\n input [C_WEB_WIDTH-1:0] web,\n input [C_ADDRB_WIDTH-1:0] addrb,\n input [C_WRITE_WIDTH_B-1:0] dinb,\n output [C_READ_WIDTH_B-1:0] doutb,\n input injectsbiterr,\n input injectdbiterr,\n output sbiterr,\n output dbiterr,\n output [C_ADDRB_WIDTH-1:0] rdaddrecc,\n input eccpipece,\n input sleep,\n input deepsleep,\n input shutdown,\n output rsta_busy, \n output rstb_busy, \n //AXI BMG Input and Output Port Declarations\n \n //AXI Global Signals\n input s_aclk,\n input s_aresetn,\n \n //AXI Full/lite slave write (write side)\n input [C_AXI_ID_WIDTH-1:0] s_axi_awid,\n input [31:0] s_axi_awaddr,\n input [7:0] s_axi_awlen,\n input [2:0] s_axi_awsize,\n input [1:0] s_axi_awburst,\n input s_axi_awvalid,\n output s_axi_awready,\n input [C_WRITE_WIDTH_A-1:0] s_axi_wdata,\n input [C_WEA_WIDTH-1:0] s_axi_wstrb,\n input s_axi_wlast,\n input s_axi_wvalid,\n output s_axi_wready,\n output [C_AXI_ID_WIDTH-1:0] s_axi_bid,\n output [1:0] s_axi_bresp,\n output s_axi_bvalid,\n input s_axi_bready,\n \n //AXI Full/lite slave read (write side)\n input [C_AXI_ID_WIDTH-1:0] s_axi_arid,\n input [31:0] s_axi_araddr,\n input [7:0] s_axi_arlen,\n input [2:0] s_axi_arsize,\n input [1:0] s_axi_arburst,\n input s_axi_arvalid,\n output s_axi_arready,\n output [C_AXI_ID_WIDTH-1:0] s_axi_rid,\n output [C_WRITE_WIDTH_B-1:0] s_axi_rdata,\n output [1:0] s_axi_rresp,\n output s_axi_rlast,\n output s_axi_rvalid,\n input s_axi_rready,\n \n //AXI Full/lite sideband signals\n input s_axi_injectsbiterr,\n input s_axi_injectdbiterr,\n output s_axi_sbiterr,\n output s_axi_dbiterr,\n output [C_ADDRB_WIDTH-1:0] s_axi_rdaddrecc \n \n );\n//******************************\n// Port and Generic Definitions\n//******************************\n //////////////////////////////////////////////////////////////////////////\n // Generic Definitions\n //////////////////////////////////////////////////////////////////////////\n // C_CORENAME : Instance name of the Block Memory Generator core\n // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following\n // options are available - \"spartan3\", \"spartan6\", \n // \"virtex4\", \"virtex5\", \"virtex6\" and \"virtex6l\".\n // C_MEM_TYPE : Designates memory type.\n // It can be\n // 0 - Single Port Memory\n // 1 - Simple Dual Port Memory\n // 2 - True Dual Port Memory\n // 3 - Single Port Read Only Memory\n // 4 - Dual Port Read Only Memory\n // C_BYTE_SIZE : Size of a byte (8 or 9 bits)\n // C_ALGORITHM : Designates the algorithm method used\n // for constructing the memory.\n // It can be Fixed_Primitives, Minimum_Area or \n // Low_Power\n // C_PRIM_TYPE : Designates the user selected primitive used to \n // construct the memory.\n //\n // C_LOAD_INIT_FILE : Designates the use of an initialization file to\n // initialize memory contents.\n // C_INIT_FILE_NAME : Memory initialization file name.\n // C_USE_DEFAULT_DATA : Designates whether to fill remaining\n // initialization space with default data\n // C_DEFAULT_DATA : Default value of all memory locations\n // not initialized by the memory\n // initialization file.\n // C_RST_TYPE : Type of reset - Synchronous or Asynchronous\n // C_HAS_RSTA : Determines the presence of the RSTA port\n // C_RST_PRIORITY_A : Determines the priority between CE and SR for \n // Port A.\n // C_RSTRAM_A : Determines if special reset behavior is used for\n // Port A\n // C_INITA_VAL : The initialization value for Port A\n // C_HAS_ENA : Determines the presence of the ENA port\n // C_HAS_REGCEA : Determines the presence of the REGCEA port\n // C_USE_BYTE_WEA : Determines if the Byte Write is used or not.\n // C_WEA_WIDTH : The width of the WEA port\n // C_WRITE_MODE_A : Configurable write mode for Port A. It can be\n // WRITE_FIRST, READ_FIRST or NO_CHANGE.\n // C_WRITE_WIDTH_A : Memory write width for Port A.\n // C_READ_WIDTH_A : Memory read width for Port A.\n // C_WRITE_DEPTH_A : Memory write depth for Port A.\n // C_READ_DEPTH_A : Memory read depth for Port A.\n // C_ADDRA_WIDTH : Width of the ADDRA input port\n // C_HAS_RSTB : Determines the presence of the RSTB port\n // C_RST_PRIORITY_B : Determines the priority between CE and SR for \n // Port B.\n // C_RSTRAM_B : Determines if special reset behavior is used for\n // Port B\n // C_INITB_VAL : The initialization value for Port B\n // C_HAS_ENB : Determines the presence of the ENB port\n // C_HAS_REGCEB : Determines the presence of the REGCEB port\n // C_USE_BYTE_WEB : Determines if the Byte Write is used or not.\n // C_WEB_WIDTH : The width of the WEB port\n // C_WRITE_MODE_B : Configurable write mode for Port B. It can be\n // WRITE_FIRST, READ_FIRST or NO_CHANGE.\n // C_WRITE_WIDTH_B : Memory write width for Port B.\n // C_READ_WIDTH_B : Memory read width for Port B.\n // C_WRITE_DEPTH_B : Memory write depth for Port B.\n // C_READ_DEPTH_B : Memory read depth for Port B.\n // C_ADDRB_WIDTH : Width of the ADDRB input port\n // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output \n // of the RAM primitive for Port A.\n // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output \n // of the RAM primitive for Port B.\n // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output\n // of the MUX for Port A.\n // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output\n // of the MUX for Port B.\n // C_HAS_SOFTECC_INPUT_REGS_A : \n // C_HAS_SOFTECC_OUTPUT_REGS_B : \n // C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in \n // between the muxes.\n // C_USE_SOFTECC : Determines if the Soft ECC feature is used or\n // not. Only applicable Spartan-6\n // C_USE_ECC : Determines if the ECC feature is used or\n // not. Only applicable for V5 and V6\n // C_HAS_INJECTERR : Determines if the error injection pins\n // are present or not. If the ECC feature\n // is not used, this value is defaulted to\n // 0, else the following are the allowed \n // values:\n // 0 : No INJECTSBITERR or INJECTDBITERR pins\n // 1 : Only INJECTSBITERR pin exists\n // 2 : Only INJECTDBITERR pin exists\n // 3 : Both INJECTSBITERR and INJECTDBITERR pins exist\n // C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision\n // warnings. It can be \"ALL\", \"NONE\", \n // \"Warnings_Only\" or \"Generate_X_Only\".\n // C_COMMON_CLK : Determins if the core has a single CLK input.\n // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings\n // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range \n // warnings\n //////////////////////////////////////////////////////////////////////////\n // Port Definitions\n //////////////////////////////////////////////////////////////////////////\n // CLKA : Clock to synchronize all read and write operations of Port A.\n // RSTA : Reset input to reset memory outputs to a user-defined \n // reset state for Port A.\n // ENA : Enable all read and write operations of Port A.\n // REGCEA : Register Clock Enable to control each pipeline output\n // register stages for Port A.\n // WEA : Write Enable to enable all write operations of Port A.\n // ADDRA : Address of Port A.\n // DINA : Data input of Port A.\n // DOUTA : Data output of Port A.\n // CLKB : Clock to synchronize all read and write operations of Port B.\n // RSTB : Reset input to reset memory outputs to a user-defined \n // reset state for Port B.\n // ENB : Enable all read and write operations of Port B.\n // REGCEB : Register Clock Enable to control each pipeline output\n // register stages for Port B.\n // WEB : Write Enable to enable all write operations of Port B.\n // ADDRB : Address of Port B.\n // DINB : Data input of Port B.\n // DOUTB : Data output of Port B.\n // INJECTSBITERR : Single Bit ECC Error Injection Pin.\n // INJECTDBITERR : Double Bit ECC Error Injection Pin.\n // SBITERR : Output signal indicating that a Single Bit ECC Error has been\n // detected and corrected.\n // DBITERR : Output signal indicating that a Double Bit ECC Error has been\n // detected.\n // RDADDRECC : Read Address Output signal indicating address at which an\n // ECC error has occurred.\n //////////////////////////////////////////////////////////////////////////\n\n wire SBITERR;\n wire DBITERR;\n wire S_AXI_AWREADY;\n wire S_AXI_WREADY;\n wire S_AXI_BVALID;\n wire S_AXI_ARREADY;\n wire S_AXI_RLAST;\n wire S_AXI_RVALID;\n wire S_AXI_SBITERR;\n wire S_AXI_DBITERR;\n\n wire [C_WEA_WIDTH-1:0] WEA = wea;\n wire [C_ADDRA_WIDTH-1:0] ADDRA = addra;\n wire [C_WRITE_WIDTH_A-1:0] DINA = dina;\n wire [C_READ_WIDTH_A-1:0] DOUTA;\n wire [C_WEB_WIDTH-1:0] WEB = web;\n wire [C_ADDRB_WIDTH-1:0] ADDRB = addrb;\n wire [C_WRITE_WIDTH_B-1:0] DINB = dinb;\n wire [C_READ_WIDTH_B-1:0] DOUTB;\n wire [C_ADDRB_WIDTH-1:0] RDADDRECC;\n wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID = s_axi_awid;\n wire [31:0] S_AXI_AWADDR = s_axi_awaddr;\n wire [7:0] S_AXI_AWLEN = s_axi_awlen;\n wire [2:0] S_AXI_AWSIZE = s_axi_awsize;\n wire [1:0] S_AXI_AWBURST = s_axi_awburst;\n wire [C_WRITE_WIDTH_A-1:0] S_AXI_WDATA = s_axi_wdata;\n wire [C_WEA_WIDTH-1:0] S_AXI_WSTRB = s_axi_wstrb;\n wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;\n wire [1:0] S_AXI_BRESP;\n wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID = s_axi_arid;\n wire [31:0] S_AXI_ARADDR = s_axi_araddr;\n wire [7:0] S_AXI_ARLEN = s_axi_arlen;\n wire [2:0] S_AXI_ARSIZE = s_axi_arsize;\n wire [1:0] S_AXI_ARBURST = s_axi_arburst;\n wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;\n wire [C_WRITE_WIDTH_B-1:0] S_AXI_RDATA;\n wire [1:0] S_AXI_RRESP;\n wire [C_ADDRB_WIDTH-1:0] S_AXI_RDADDRECC;\n // Added to fix the simulation warning #CR731605\n wire [C_WEB_WIDTH-1:0] WEB_parameterized = 0;\n wire ECCPIPECE;\n wire SLEEP;\n reg RSTA_BUSY = 0;\n reg RSTB_BUSY = 0;\n // Declaration of internal signals to avoid warnings #927399\n wire CLKA;\n wire RSTA;\n wire ENA;\n wire REGCEA;\n wire CLKB;\n wire RSTB;\n wire ENB;\n wire REGCEB;\n wire INJECTSBITERR;\n wire INJECTDBITERR;\n wire S_ACLK;\n wire S_ARESETN;\n wire S_AXI_AWVALID;\n wire S_AXI_WLAST;\n wire S_AXI_WVALID;\n wire S_AXI_BREADY;\n wire S_AXI_ARVALID;\n wire S_AXI_RREADY;\n wire S_AXI_INJECTSBITERR;\n wire S_AXI_INJECTDBITERR;\n\n assign CLKA = clka;\n assign RSTA = rsta;\n assign ENA = ena;\n assign REGCEA = regcea;\n assign CLKB = clkb;\n assign RSTB = rstb;\n assign ENB = enb;\n assign REGCEB = regceb;\n assign INJECTSBITERR = injectsbiterr;\n assign INJECTDBITERR = injectdbiterr;\n assign ECCPIPECE = eccpipece;\n assign SLEEP = sleep;\n assign sbiterr = SBITERR;\n assign dbiterr = DBITERR;\n assign S_ACLK = s_aclk;\n assign S_ARESETN = s_aresetn;\n assign S_AXI_AWVALID = s_axi_awvalid;\n assign s_axi_awready = S_AXI_AWREADY;\n assign S_AXI_WLAST = s_axi_wlast;\n assign S_AXI_WVALID = s_axi_wvalid;\n assign s_axi_wready = S_AXI_WREADY;\n assign s_axi_bvalid = S_AXI_BVALID;\n assign S_AXI_BREADY = s_axi_bready;\n assign S_AXI_ARVALID = s_axi_arvalid;\n assign s_axi_arready = S_AXI_ARREADY;\n assign s_axi_rlast = S_AXI_RLAST;\n assign s_axi_rvalid = S_AXI_RVALID;\n assign S_AXI_RREADY = s_axi_rready;\n assign S_AXI_INJECTSBITERR = s_axi_injectsbiterr;\n assign S_AXI_INJECTDBITERR = s_axi_injectdbiterr;\n assign s_axi_sbiterr = S_AXI_SBITERR;\n assign s_axi_dbiterr = S_AXI_DBITERR;\n\n assign rsta_busy = RSTA_BUSY;\n assign rstb_busy = RSTB_BUSY;\n\n assign doutb = DOUTB;\n assign douta = DOUTA;\n assign rdaddrecc = RDADDRECC;\n assign s_axi_bid = S_AXI_BID;\n assign s_axi_bresp = S_AXI_BRESP;\n assign s_axi_rid = S_AXI_RID;\n assign s_axi_rdata = S_AXI_RDATA;\n assign s_axi_rresp = S_AXI_RRESP;\n assign s_axi_rdaddrecc = S_AXI_RDADDRECC;\n\n localparam FLOP_DELAY = 100; // 100 ps\n\n reg injectsbiterr_in;\n reg injectdbiterr_in;\n reg rsta_in;\n reg ena_in;\n reg regcea_in;\n reg [C_WEA_WIDTH-1:0] wea_in;\n reg [C_ADDRA_WIDTH-1:0] addra_in;\n reg [C_WRITE_WIDTH_A-1:0] dina_in;\n\n wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;\n wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;\n wire s_axi_wr_en_c;\n wire s_axi_rd_en_c;\n wire s_aresetn_a_c;\n wire [7:0] s_axi_arlen_c ;\n\n\n wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;\n wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;\n wire [1:0] s_axi_rresp_c;\n wire s_axi_rlast_c;\n wire s_axi_rvalid_c;\n wire s_axi_rready_c;\n wire regceb_c;\n\n localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;\n wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;\n wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;\n\n// Safety logic related signals\n\n reg [4:0] RSTA_SHFT_REG = 0;\n reg POR_A = 0; \n reg [4:0] RSTB_SHFT_REG = 0;\n reg POR_B = 0;\n \n reg ENA_dly = 0;\n reg ENA_dly_D = 0;\n\n reg ENB_dly = 0;\n reg ENB_dly_D = 0;\n\n wire RSTA_I_SAFE;\n wire RSTB_I_SAFE;\n\n wire ENA_I_SAFE;\n wire ENB_I_SAFE;\n \n reg ram_rstram_a_busy = 0;\n reg ram_rstreg_a_busy = 0;\n reg ram_rstram_b_busy = 0;\n reg ram_rstreg_b_busy = 0;\n\n reg ENA_dly_reg = 0;\n reg ENB_dly_reg = 0;\n \n reg ENA_dly_reg_D = 0;\n reg ENB_dly_reg_D = 0;\n\n //**************\n // log2roundup\n //**************\n function integer log2roundup (input integer data_value);\n integer width;\n integer cnt;\n begin\n width = 0;\n\n if (data_value > 1) begin\n for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin\n width = width + 1;\n end //loop\n end //if\n\n log2roundup = width;\n\n end //log2roundup\n endfunction\n\n //**************\n // log2int\n //**************\n function integer log2int (input integer data_value);\n integer width;\n integer cnt;\n begin\n width = 0;\n\t\t cnt= data_value;\n\n for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin\n width = width + 1;\n end //loop\n\n log2int = width;\n\n end //log2int\n endfunction\n\n //**************************************************************************\n // FUNCTION : divroundup\n // Returns the ceiling value of the division\n // Data_value - the quantity to be divided, dividend\n // Divisor - the value to divide the data_value by\n //**************************************************************************\n function integer divroundup (input integer data_value,input integer divisor);\n integer div;\n begin\n div = data_value/divisor;\n if ((data_value % divisor) != 0) begin\n div = div+1;\n end //if\n divroundup = div;\n end //if\n endfunction\n\n localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);\n localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);\n localparam C_AXI_ADDR_WIDTH = C_AXI_ADDR_WIDTH_MSB;\n \n //Data Width Number of LSB address bits to be discarded\n //1 to 16 1\n //17 to 32 2\n //33 to 64 3\n //65 to 128 4\n //129 to 256 5\n //257 to 512 6\n //513 to 1024 7\n // The following two constants determine this.\n\n localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));\n localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);\n localparam C_AXI_OS_WR = 2;\n\n //***********************************************\n // INPUT REGISTERS.\n //***********************************************\n generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage\n always @* begin\n injectsbiterr_in = INJECTSBITERR;\n injectdbiterr_in = INJECTDBITERR;\n rsta_in = RSTA;\n ena_in = ENA;\n regcea_in = REGCEA;\n wea_in = WEA;\n addra_in = ADDRA;\n dina_in = DINA;\n end //end always\n end //end no_softecc_input_reg_stage\n endgenerate\n\n generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage\n always @(posedge CLKA) begin\n injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;\n injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;\n rsta_in <= #FLOP_DELAY RSTA;\n ena_in <= #FLOP_DELAY ENA;\n regcea_in <= #FLOP_DELAY REGCEA;\n wea_in <= #FLOP_DELAY WEA;\n addra_in <= #FLOP_DELAY ADDRA;\n dina_in <= #FLOP_DELAY DINA;\n end //end always\n end //end input_reg_stages generate statement\n endgenerate\n\n //**************************************************************************\n // NO SAFETY LOGIC\n //**************************************************************************\n\n generate \n if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN\n assign ENA_I_SAFE = ena_in;\n assign ENB_I_SAFE = ENB;\n assign RSTA_I_SAFE = rsta_in;\n assign RSTB_I_SAFE = RSTB;\n end\n endgenerate\n\n //***************************************************************************\n // SAFETY LOGIC\n // Power-ON Reset Generation\n //***************************************************************************\n generate \n if (C_EN_SAFETY_CKT == 1) begin\n always @(posedge clka) RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;\n always @(posedge clka) POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];\n always @(posedge clkb) RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;\n always @(posedge clkb) POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; \n \n assign RSTA_I_SAFE = rsta_in | POR_A; \n assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);\n end\n endgenerate\n\n //-----------------------------------------------------------------------------\n // -- RSTA/B_BUSY Generation\n //-----------------------------------------------------------------------------\n\n generate \n if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG\n always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;\n always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;\n end\n endgenerate\n \n generate \n if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG\n always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;\n always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;\n end\n endgenerate\n\n generate \n if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY\n always @(*) RSTB_BUSY = 1'b0;\n end\n endgenerate\n\n generate \n if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_NO_REG\n always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;\n always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;\n end\n endgenerate\n \n generate \n if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG \n always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;\n always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;\n end\n endgenerate\n\n //-----------------------------------------------------------------------------\n // -- ENA/ENB Generation\n //-----------------------------------------------------------------------------\n \n generate \n if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG \n always @(posedge clka) begin\n ENA_dly <= #FLOP_DELAY RSTA_I_SAFE;\n ENA_dly_D <= #FLOP_DELAY ENA_dly;\n end\n assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);\n end\n endgenerate\n\n generate \n if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG\n always @(posedge clka) begin\n ENA_dly_reg <= #FLOP_DELAY RSTA_I_SAFE;\n ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;\n end\n assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);\n end\n endgenerate\n\n generate \n if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB\n assign ENB_I_SAFE = 1'b0;\n end\n endgenerate\n\n generate \n if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG\n always @(posedge clkb) begin : PROC_ENB_GEN\n ENB_dly <= #FLOP_DELAY RSTB_I_SAFE;\n ENB_dly_D <= #FLOP_DELAY ENB_dly;\n end\n assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);\n end\n endgenerate\n \n generate \n if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG\n always @(posedge clkb) begin : PROC_ENB_GEN\n ENB_dly_reg <= #FLOP_DELAY RSTB_I_SAFE;\n ENB_dly_reg_D <= #FLOP_DELAY ENB_dly_reg;\n end\n assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);\n end\n endgenerate\n\n generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module\nblk_mem_gen_v8_3_4_mem_module\n #(.C_CORENAME (C_CORENAME),\n .C_FAMILY (C_FAMILY),\n .C_XDEVICEFAMILY (C_XDEVICEFAMILY),\n .C_MEM_TYPE (C_MEM_TYPE),\n .C_BYTE_SIZE (C_BYTE_SIZE),\n .C_ALGORITHM (C_ALGORITHM),\n .C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),\n .C_PRIM_TYPE (C_PRIM_TYPE),\n .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),\n .C_INIT_FILE_NAME (C_INIT_FILE_NAME),\n .C_INIT_FILE (C_INIT_FILE),\n .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),\n .C_DEFAULT_DATA (C_DEFAULT_DATA),\n .C_RST_TYPE (\"SYNC\"),\n .C_HAS_RSTA (C_HAS_RSTA),\n .C_RST_PRIORITY_A (C_RST_PRIORITY_A),\n .C_RSTRAM_A (C_RSTRAM_A),\n .C_INITA_VAL (C_INITA_VAL),\n .C_HAS_ENA (C_HAS_ENA),\n .C_HAS_REGCEA (C_HAS_REGCEA),\n .C_USE_BYTE_WEA (C_USE_BYTE_WEA),\n .C_WEA_WIDTH (C_WEA_WIDTH),\n .C_WRITE_MODE_A (C_WRITE_MODE_A),\n .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),\n .C_READ_WIDTH_A (C_READ_WIDTH_A),\n .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),\n .C_READ_DEPTH_A (C_READ_DEPTH_A),\n .C_ADDRA_WIDTH (C_ADDRA_WIDTH),\n .C_HAS_RSTB (C_HAS_RSTB),\n .C_RST_PRIORITY_B (C_RST_PRIORITY_B),\n .C_RSTRAM_B (C_RSTRAM_B),\n .C_INITB_VAL (C_INITB_VAL),\n .C_HAS_ENB (C_HAS_ENB),\n .C_HAS_REGCEB (C_HAS_REGCEB),\n .C_USE_BYTE_WEB (C_USE_BYTE_WEB),\n .C_WEB_WIDTH (C_WEB_WIDTH),\n .C_WRITE_MODE_B (C_WRITE_MODE_B),\n .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),\n .C_READ_WIDTH_B (C_READ_WIDTH_B),\n .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),\n .C_READ_DEPTH_B (C_READ_DEPTH_B),\n .C_ADDRB_WIDTH (C_ADDRB_WIDTH),\n .C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),\n .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),\n .C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),\n .C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),\n .C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),\n .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),\n .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),\n .C_USE_SOFTECC (C_USE_SOFTECC),\n .C_USE_ECC (C_USE_ECC),\n .C_HAS_INJECTERR (C_HAS_INJECTERR),\n .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),\n .C_COMMON_CLK (C_COMMON_CLK),\n .FLOP_DELAY (FLOP_DELAY),\n .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE (C_EN_ECC_PIPE),\n .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))\n blk_mem_gen_v8_3_4_inst\n (.CLKA (CLKA),\n .RSTA (RSTA_I_SAFE),//(rsta_in),\n .ENA (ENA_I_SAFE),//(ena_in),\n .REGCEA (regcea_in),\n .WEA (wea_in),\n .ADDRA (addra_in),\n .DINA (dina_in),\n .DOUTA (DOUTA),\n .CLKB (CLKB),\n .RSTB (RSTB_I_SAFE),//(RSTB),\n .ENB (ENB_I_SAFE),//(ENB),\n .REGCEB (REGCEB),\n .WEB (WEB),\n .ADDRB (ADDRB),\n .DINB (DINB),\n .DOUTB (DOUTB),\n .INJECTSBITERR (injectsbiterr_in),\n .INJECTDBITERR (injectdbiterr_in),\n .ECCPIPECE (ECCPIPECE),\n .SLEEP (SLEEP),\n .SBITERR (SBITERR),\n .DBITERR (DBITERR),\n .RDADDRECC (RDADDRECC)\n );\n end\n endgenerate\n\n generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module\n\n localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);\n localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);\n\n localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);\n localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);\n // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);\n // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);\n localparam C_MEM_MAP_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_MSB;\n localparam C_MEM_MAP_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_MSB;\n\n // Data Width Number of LSB address bits to be discarded\n // 1 to 16 1\n // 17 to 32 2\n // 33 to 64 3\n // 65 to 128 4\n // 129 to 256 5\n // 257 to 512 6\n // 513 to 1024 7\n // The following two constants determine this.\n\n localparam MEM_MAP_LOWER_BOUND_VAL_A = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));\n localparam MEM_MAP_LOWER_BOUND_VAL_B = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));\n localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;\n localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;\n\n wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;\n wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;\n wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;\n \n assign msb_zero_i = 0;\n assign lsb_zero_i = 0;\n assign RDADDRECC = {msb_zero_i,rdaddrecc_i,lsb_zero_i};\n\nblk_mem_gen_v8_3_4_mem_module\n #(.C_CORENAME (C_CORENAME),\n .C_FAMILY (C_FAMILY),\n .C_XDEVICEFAMILY (C_XDEVICEFAMILY),\n .C_MEM_TYPE (C_MEM_TYPE),\n .C_BYTE_SIZE (C_BYTE_SIZE),\n .C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),\n .C_ALGORITHM (C_ALGORITHM),\n .C_PRIM_TYPE (C_PRIM_TYPE),\n .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),\n .C_INIT_FILE_NAME (C_INIT_FILE_NAME),\n .C_INIT_FILE (C_INIT_FILE),\n .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),\n .C_DEFAULT_DATA (C_DEFAULT_DATA),\n .C_RST_TYPE (\"SYNC\"),\n .C_HAS_RSTA (C_HAS_RSTA),\n .C_RST_PRIORITY_A (C_RST_PRIORITY_A),\n .C_RSTRAM_A (C_RSTRAM_A),\n .C_INITA_VAL (C_INITA_VAL),\n .C_HAS_ENA (C_HAS_ENA),\n .C_HAS_REGCEA (C_HAS_REGCEA),\n .C_USE_BYTE_WEA (C_USE_BYTE_WEA),\n .C_WEA_WIDTH (C_WEA_WIDTH),\n .C_WRITE_MODE_A (C_WRITE_MODE_A),\n .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),\n .C_READ_WIDTH_A (C_READ_WIDTH_A),\n .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),\n .C_READ_DEPTH_A (C_READ_DEPTH_A),\n .C_ADDRA_WIDTH (C_ADDRA_WIDTH_ACTUAL),\n .C_HAS_RSTB (C_HAS_RSTB),\n .C_RST_PRIORITY_B (C_RST_PRIORITY_B),\n .C_RSTRAM_B (C_RSTRAM_B),\n .C_INITB_VAL (C_INITB_VAL),\n .C_HAS_ENB (C_HAS_ENB),\n .C_HAS_REGCEB (C_HAS_REGCEB),\n .C_USE_BYTE_WEB (C_USE_BYTE_WEB),\n .C_WEB_WIDTH (C_WEB_WIDTH),\n .C_WRITE_MODE_B (C_WRITE_MODE_B),\n .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),\n .C_READ_WIDTH_B (C_READ_WIDTH_B),\n .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),\n .C_READ_DEPTH_B (C_READ_DEPTH_B),\n .C_ADDRB_WIDTH (C_ADDRB_WIDTH_ACTUAL),\n .C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),\n .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),\n .C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),\n .C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),\n .C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),\n .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),\n .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),\n .C_USE_SOFTECC (C_USE_SOFTECC),\n .C_USE_ECC (C_USE_ECC),\n .C_HAS_INJECTERR (C_HAS_INJECTERR),\n .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),\n .C_COMMON_CLK (C_COMMON_CLK),\n .FLOP_DELAY (FLOP_DELAY),\n .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),\n .C_EN_ECC_PIPE (C_EN_ECC_PIPE),\n .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))\n blk_mem_gen_v8_3_4_inst\n (.CLKA (CLKA),\n .RSTA (RSTA_I_SAFE),//(rsta_in),\n .ENA (ENA_I_SAFE),//(ena_in),\n .REGCEA (regcea_in),\n .WEA (wea_in),\n .ADDRA (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),\n .DINA (dina_in),\n .DOUTA (DOUTA),\n .CLKB (CLKB),\n .RSTB (RSTB_I_SAFE),//(RSTB),\n .ENB (ENB_I_SAFE),//(ENB),\n .REGCEB (REGCEB),\n .WEB (WEB),\n .ADDRB (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),\n .DINB (DINB),\n .DOUTB (DOUTB),\n .INJECTSBITERR (injectsbiterr_in),\n .INJECTDBITERR (injectdbiterr_in),\n .ECCPIPECE (ECCPIPECE),\n .SLEEP (SLEEP),\n .SBITERR (SBITERR),\n .DBITERR (DBITERR),\n .RDADDRECC (rdaddrecc_i)\n );\n end\n endgenerate\n\n generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs\n assign S_AXI_RDATA = s_axi_rdata_c;\n assign S_AXI_RLAST = s_axi_rlast_c;\n assign S_AXI_RVALID = s_axi_rvalid_c;\n assign S_AXI_RID = s_axi_rid_c;\n assign S_AXI_RRESP = s_axi_rresp_c;\n assign s_axi_rready_c = S_AXI_RREADY;\n end\n endgenerate\n\n generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb\n assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;\n end\n endgenerate\n\n generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb\n assign regceb_c = REGCEB;\n end\n endgenerate\n\n generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs\n assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};\n assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n assign S_AXI_RDATA = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];\n assign S_AXI_RRESP = m_axi_payload_c[2:1];\n assign S_AXI_RLAST = m_axi_payload_c[0];\n end\n endgenerate\n\n generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs\n assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};\n assign S_AXI_RDATA = s_axi_rdata_c;\n assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];\n assign S_AXI_RRESP = m_axi_payload_c[2:1];\n assign S_AXI_RLAST = m_axi_payload_c[0];\n end\n endgenerate\n\n generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd\n\n blk_mem_axi_regs_fwd_v8_3\n #(.C_DATA_WIDTH (C_AXI_PAYLOAD))\n axi_regs_inst (\n .ACLK (S_ACLK), \n .ARESET (s_aresetn_a_c),\n .S_VALID (s_axi_rvalid_c), \n .S_READY (s_axi_rready_c),\n .S_PAYLOAD_DATA (s_axi_payload_c),\n .M_VALID (S_AXI_RVALID),\n .M_READY (S_AXI_RREADY),\n .M_PAYLOAD_DATA (m_axi_payload_c)\n );\n end\n endgenerate\n\n generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module\n\nassign s_aresetn_a_c = !S_ARESETN;\nassign S_AXI_BRESP = 2'b00;\nassign s_axi_rresp_c = 2'b00;\nassign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;\n\n blk_mem_axi_write_wrapper_beh_v8_3\n #(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),\n .C_AXI_TYPE (C_AXI_TYPE),\n .C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),\n .C_MEMORY_TYPE (C_MEM_TYPE),\n .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),\n .C_AXI_AWADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),\n .C_HAS_AXI_ID (C_HAS_AXI_ID),\n .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),\n .C_ADDRA_WIDTH (C_ADDRA_WIDTH),\n .C_AXI_WDATA_WIDTH (C_WRITE_WIDTH_A),\n .C_AXI_OS_WR (C_AXI_OS_WR))\n axi_wr_fsm (\n // AXI Global Signals\n .S_ACLK (S_ACLK),\n .S_ARESETN (s_aresetn_a_c),\n // AXI Full/Lite Slave Write interface\n .S_AXI_AWADDR (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n .S_AXI_AWLEN (S_AXI_AWLEN),\n .S_AXI_AWID (S_AXI_AWID),\n .S_AXI_AWSIZE (S_AXI_AWSIZE),\n .S_AXI_AWBURST (S_AXI_AWBURST),\n .S_AXI_AWVALID (S_AXI_AWVALID),\n .S_AXI_AWREADY (S_AXI_AWREADY),\n .S_AXI_WVALID (S_AXI_WVALID),\n .S_AXI_WREADY (S_AXI_WREADY),\n .S_AXI_BVALID (S_AXI_BVALID),\n .S_AXI_BREADY (S_AXI_BREADY),\n .S_AXI_BID (S_AXI_BID),\n // Signals for BRAM interfac(\n .S_AXI_AWADDR_OUT (s_axi_awaddr_out_c),\n .S_AXI_WR_EN (s_axi_wr_en_c)\n );\n\n blk_mem_axi_read_wrapper_beh_v8_3\n #(.C_INTERFACE_TYPE (C_INTERFACE_TYPE), \n .C_AXI_TYPE\t\t (C_AXI_TYPE), \n .C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE), \n .C_MEMORY_TYPE (C_MEM_TYPE), \n .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), \n .C_ADDRA_WIDTH (C_ADDRA_WIDTH), \n .C_AXI_PIPELINE_STAGES (1), \n .C_AXI_ARADDR_WIDTH\t ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), \n .C_HAS_AXI_ID (C_HAS_AXI_ID), \n .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), \n .C_ADDRB_WIDTH (C_ADDRB_WIDTH)) \n axi_rd_sm(\n //AXI Global Signals\n .S_ACLK (S_ACLK), \n .S_ARESETN (s_aresetn_a_c),\n //AXI Full/Lite Read Side\n .S_AXI_ARADDR (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),\n .S_AXI_ARLEN (s_axi_arlen_c),\n .S_AXI_ARSIZE (S_AXI_ARSIZE),\n .S_AXI_ARBURST (S_AXI_ARBURST),\n .S_AXI_ARVALID (S_AXI_ARVALID),\n .S_AXI_ARREADY (S_AXI_ARREADY),\n .S_AXI_RLAST (s_axi_rlast_c),\n .S_AXI_RVALID (s_axi_rvalid_c),\n .S_AXI_RREADY (s_axi_rready_c),\n .S_AXI_ARID (S_AXI_ARID),\n .S_AXI_RID (s_axi_rid_c),\n //AXI Full/Lite Read FSM Outputs\n .S_AXI_ARADDR_OUT (s_axi_araddr_out_c),\n .S_AXI_RD_EN (s_axi_rd_en_c)\n );\n\nblk_mem_gen_v8_3_4_mem_module\n #(.C_CORENAME (C_CORENAME),\n .C_FAMILY (C_FAMILY),\n .C_XDEVICEFAMILY (C_XDEVICEFAMILY),\n .C_MEM_TYPE (C_MEM_TYPE),\n .C_BYTE_SIZE (C_BYTE_SIZE),\n .C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),\n .C_ALGORITHM (C_ALGORITHM),\n .C_PRIM_TYPE (C_PRIM_TYPE),\n .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),\n .C_INIT_FILE_NAME (C_INIT_FILE_NAME),\n .C_INIT_FILE (C_INIT_FILE),\n .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),\n .C_DEFAULT_DATA (C_DEFAULT_DATA),\n .C_RST_TYPE (\"SYNC\"),\n .C_HAS_RSTA (C_HAS_RSTA),\n .C_RST_PRIORITY_A (C_RST_PRIORITY_A),\n .C_RSTRAM_A (C_RSTRAM_A),\n .C_INITA_VAL (C_INITA_VAL),\n .C_HAS_ENA (1),\n .C_HAS_REGCEA (C_HAS_REGCEA),\n .C_USE_BYTE_WEA (1),\n .C_WEA_WIDTH (C_WEA_WIDTH),\n .C_WRITE_MODE_A (C_WRITE_MODE_A),\n .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),\n .C_READ_WIDTH_A (C_READ_WIDTH_A),\n .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),\n .C_READ_DEPTH_A (C_READ_DEPTH_A),\n .C_ADDRA_WIDTH (C_ADDRA_WIDTH),\n .C_HAS_RSTB (C_HAS_RSTB),\n .C_RST_PRIORITY_B (C_RST_PRIORITY_B),\n .C_RSTRAM_B (C_RSTRAM_B),\n .C_INITB_VAL (C_INITB_VAL),\n .C_HAS_ENB (1),\n .C_HAS_REGCEB (C_HAS_MEM_OUTPUT_REGS_B),\n .C_USE_BYTE_WEB (1),\n .C_WEB_WIDTH (C_WEB_WIDTH),\n .C_WRITE_MODE_B (C_WRITE_MODE_B),\n .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),\n .C_READ_WIDTH_B (C_READ_WIDTH_B),\n .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),\n .C_READ_DEPTH_B (C_READ_DEPTH_B),\n .C_ADDRB_WIDTH (C_ADDRB_WIDTH),\n .C_HAS_MEM_OUTPUT_REGS_A (0),\n .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),\n .C_HAS_MUX_OUTPUT_REGS_A (0),\n .C_HAS_MUX_OUTPUT_REGS_B (0),\n .C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),\n .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),\n .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),\n .C_USE_SOFTECC (C_USE_SOFTECC),\n .C_USE_ECC (C_USE_ECC),\n .C_HAS_INJECTERR (C_HAS_INJECTERR),\n .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),\n .C_COMMON_CLK (C_COMMON_CLK),\n .FLOP_DELAY (FLOP_DELAY),\n .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),\n\t.C_EN_ECC_PIPE (0),\n .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))\n blk_mem_gen_v8_3_4_inst\n (.CLKA (S_ACLK),\n .RSTA (s_aresetn_a_c),\n .ENA (s_axi_wr_en_c),\n .REGCEA (regcea_in),\n .WEA (S_AXI_WSTRB),\n .ADDRA (s_axi_awaddr_out_c),\n .DINA (S_AXI_WDATA),\n .DOUTA (DOUTA),\n .CLKB (S_ACLK),\n .RSTB (s_aresetn_a_c),\n .ENB (s_axi_rd_en_c),\n .REGCEB (regceb_c),\n .WEB (WEB_parameterized),\n .ADDRB (s_axi_araddr_out_c),\n .DINB (DINB),\n .DOUTB (s_axi_rdata_c),\n .INJECTSBITERR (injectsbiterr_in),\n .INJECTDBITERR (injectdbiterr_in),\n .SBITERR (SBITERR),\n .DBITERR (DBITERR),\n .ECCPIPECE (1'b0),\n .SLEEP (1'b0),\n .RDADDRECC (RDADDRECC)\n );\n end\n endgenerate\nendmodule\n\n\n\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/output_line_buffer_1/synth/output_line_buffer.vhd", "content": "-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.\n-- \n-- This file contains confidential and proprietary information\n-- of Xilinx, Inc. and is protected under U.S. and\n-- international copyright and other intellectual property\n-- laws.\n-- \n-- DISCLAIMER\n-- This disclaimer is not a license and does not grant any\n-- rights to the materials distributed herewith. Except as\n-- otherwise provided in a valid license issued to you by\n-- Xilinx, and to the maximum extent permitted by applicable\n-- law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n-- (2) Xilinx shall not be liable (whether in contract or tort,\n-- including negligence, or under any other theory of\n-- liability) for any loss or damage of any kind or nature\n-- related to, arising under or in connection with these\n-- materials, including for any direct, or any indirect,\n-- special, incidental, or consequential loss or damage\n-- (including loss of data, profits, goodwill, or any type of\n-- loss or damage suffered as a result of any action brought\n-- by a third party) even if such damage or loss was\n-- reasonably foreseeable or Xilinx had been advised of the\n-- possibility of the same.\n-- \n-- CRITICAL APPLICATIONS\n-- Xilinx products are not designed or intended to be fail-\n-- safe, or for use in any application requiring fail-safe\n-- performance, such as life-support or safety devices or\n-- systems, Class III medical devices, nuclear facilities,\n-- applications related to the deployment of airbags, or any\n-- other applications that could lead to death, personal\n-- injury, or severe property or environmental damage\n-- (individually and collectively, \"Critical\n-- Applications\"). Customer assumes the sole risk and\n-- liability of any use of Xilinx products in Critical\n-- Applications, subject only to applicable laws and\n-- regulations governing limitations on product liability.\n-- \n-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n-- PART OF THIS FILE AT ALL TIMES.\n-- \n-- DO NOT MODIFY THIS FILE.\n\n-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3\n-- IP Revision: 4\n\nLIBRARY ieee;\nUSE ieee.std_logic_1164.ALL;\nUSE ieee.numeric_std.ALL;\n\nLIBRARY blk_mem_gen_v8_3_4;\nUSE blk_mem_gen_v8_3_4.blk_mem_gen_v8_3_4;\n\nENTITY output_line_buffer IS\n PORT (\n clka : IN STD_LOGIC;\n ena : IN STD_LOGIC;\n wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);\n addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);\n dina : IN STD_LOGIC_VECTOR(255 DOWNTO 0);\n clkb : IN STD_LOGIC;\n addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);\n doutb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)\n );\nEND output_line_buffer;\n\nARCHITECTURE output_line_buffer_arch OF output_line_buffer IS\n ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;\n ATTRIBUTE DowngradeIPIdentifiedWarnings OF output_line_buffer_arch: ARCHITECTURE IS \"yes\";\n COMPONENT blk_mem_gen_v8_3_4 IS\n GENERIC (\n C_FAMILY : STRING;\n C_XDEVICEFAMILY : STRING;\n C_ELABORATION_DIR : STRING;\n C_INTERFACE_TYPE : INTEGER;\n C_AXI_TYPE : INTEGER;\n C_AXI_SLAVE_TYPE : INTEGER;\n C_USE_BRAM_BLOCK : INTEGER;\n C_ENABLE_32BIT_ADDRESS : INTEGER;\n C_CTRL_ECC_ALGO : STRING;\n C_HAS_AXI_ID : INTEGER;\n C_AXI_ID_WIDTH : INTEGER;\n C_MEM_TYPE : INTEGER;\n C_BYTE_SIZE : INTEGER;\n C_ALGORITHM : INTEGER;\n C_PRIM_TYPE : INTEGER;\n C_LOAD_INIT_FILE : INTEGER;\n C_INIT_FILE_NAME : STRING;\n C_INIT_FILE : STRING;\n C_USE_DEFAULT_DATA : INTEGER;\n C_DEFAULT_DATA : STRING;\n C_HAS_RSTA : INTEGER;\n C_RST_PRIORITY_A : STRING;\n C_RSTRAM_A : INTEGER;\n C_INITA_VAL : STRING;\n C_HAS_ENA : INTEGER;\n C_HAS_REGCEA : INTEGER;\n C_USE_BYTE_WEA : INTEGER;\n C_WEA_WIDTH : INTEGER;\n C_WRITE_MODE_A : STRING;\n C_WRITE_WIDTH_A : INTEGER;\n C_READ_WIDTH_A : INTEGER;\n C_WRITE_DEPTH_A : INTEGER;\n C_READ_DEPTH_A : INTEGER;\n C_ADDRA_WIDTH : INTEGER;\n C_HAS_RSTB : INTEGER;\n C_RST_PRIORITY_B : STRING;\n C_RSTRAM_B : INTEGER;\n C_INITB_VAL : STRING;\n C_HAS_ENB : INTEGER;\n C_HAS_REGCEB : INTEGER;\n C_USE_BYTE_WEB : INTEGER;\n C_WEB_WIDTH : INTEGER;\n C_WRITE_MODE_B : STRING;\n C_WRITE_WIDTH_B : INTEGER;\n C_READ_WIDTH_B : INTEGER;\n C_WRITE_DEPTH_B : INTEGER;\n C_READ_DEPTH_B : INTEGER;\n C_ADDRB_WIDTH : INTEGER;\n C_HAS_MEM_OUTPUT_REGS_A : INTEGER;\n C_HAS_MEM_OUTPUT_REGS_B : INTEGER;\n C_HAS_MUX_OUTPUT_REGS_A : INTEGER;\n C_HAS_MUX_OUTPUT_REGS_B : INTEGER;\n C_MUX_PIPELINE_STAGES : INTEGER;\n C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;\n C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;\n C_USE_SOFTECC : INTEGER;\n C_USE_ECC : INTEGER;\n C_EN_ECC_PIPE : INTEGER;\n C_HAS_INJECTERR : INTEGER;\n C_SIM_COLLISION_CHECK : STRING;\n C_COMMON_CLK : INTEGER;\n C_DISABLE_WARN_BHV_COLL : INTEGER;\n C_EN_SLEEP_PIN : INTEGER;\n C_USE_URAM : INTEGER;\n C_EN_RDADDRA_CHG : INTEGER;\n C_EN_RDADDRB_CHG : INTEGER;\n C_EN_DEEPSLEEP_PIN : INTEGER;\n C_EN_SHUTDOWN_PIN : INTEGER;\n C_EN_SAFETY_CKT : INTEGER;\n C_DISABLE_WARN_BHV_RANGE : INTEGER;\n C_COUNT_36K_BRAM : STRING;\n C_COUNT_18K_BRAM : STRING;\n C_EST_POWER_SUMMARY : STRING\n );\n PORT (\n clka : IN STD_LOGIC;\n rsta : IN STD_LOGIC;\n ena : IN STD_LOGIC;\n regcea : IN STD_LOGIC;\n wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);\n addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);\n dina : IN STD_LOGIC_VECTOR(255 DOWNTO 0);\n douta : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);\n clkb : IN STD_LOGIC;\n rstb : IN STD_LOGIC;\n enb : IN STD_LOGIC;\n regceb : IN STD_LOGIC;\n web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);\n addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);\n dinb : IN STD_LOGIC_VECTOR(63 DOWNTO 0);\n doutb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);\n injectsbiterr : IN STD_LOGIC;\n injectdbiterr : IN STD_LOGIC;\n eccpipece : IN STD_LOGIC;\n sbiterr : OUT STD_LOGIC;\n dbiterr : OUT STD_LOGIC;\n rdaddrecc : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);\n sleep : IN STD_LOGIC;\n deepsleep : IN STD_LOGIC;\n shutdown : IN STD_LOGIC;\n rsta_busy : OUT STD_LOGIC;\n rstb_busy : OUT STD_LOGIC;\n s_aclk : IN STD_LOGIC;\n s_aresetn : IN STD_LOGIC;\n s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);\n s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);\n s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);\n s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);\n s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);\n s_axi_awvalid : IN STD_LOGIC;\n s_axi_awready : OUT STD_LOGIC;\n s_axi_wdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0);\n s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);\n s_axi_wlast : IN STD_LOGIC;\n s_axi_wvalid : IN STD_LOGIC;\n s_axi_wready : OUT STD_LOGIC;\n s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);\n s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);\n s_axi_bvalid : OUT STD_LOGIC;\n s_axi_bready : IN STD_LOGIC;\n s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);\n s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);\n s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);\n s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);\n s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);\n s_axi_arvalid : IN STD_LOGIC;\n s_axi_arready : OUT STD_LOGIC;\n s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);\n s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);\n s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);\n s_axi_rlast : OUT STD_LOGIC;\n s_axi_rvalid : OUT STD_LOGIC;\n s_axi_rready : IN STD_LOGIC;\n s_axi_injectsbiterr : IN STD_LOGIC;\n s_axi_injectdbiterr : IN STD_LOGIC;\n s_axi_sbiterr : OUT STD_LOGIC;\n s_axi_dbiterr : OUT STD_LOGIC;\n s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)\n );\n END COMPONENT blk_mem_gen_v8_3_4;\n ATTRIBUTE X_CORE_INFO : STRING;\n ATTRIBUTE X_CORE_INFO OF output_line_buffer_arch: ARCHITECTURE IS \"blk_mem_gen_v8_3_4,Vivado 2016.3\";\n ATTRIBUTE CHECK_LICENSE_TYPE : STRING;\n ATTRIBUTE CHECK_LICENSE_TYPE OF output_line_buffer_arch : ARCHITECTURE IS \"output_line_buffer,blk_mem_gen_v8_3_4,{}\";\n ATTRIBUTE CORE_GENERATION_INFO : STRING;\n ATTRIBUTE CORE_GENERATION_INFO OF output_line_buffer_arch: ARCHITECTURE IS \"output_line_buffer,blk_mem_gen_v8_3_4,{x_ipProduct=Vivado 2016.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=kintex7,C_XDEVICEFAMILY=kintex7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAM\" & \n\"E=no_coe_file_loaded,C_INIT_FILE=output_line_buffer.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=256,C_READ_WIDTH_A=256,C_WRITE_DEPTH_A=1024,C_READ_DEPTH_A=1024,C_ADDRA_WIDTH=10,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=64,C_\" & \n\"READ_WIDTH_B=64,C_WRITE_DEPTH_B=4096,C_READ_DEPTH_B=4096,C_ADDRB_WIDTH=12,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C\" & \n\"_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=7,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 33.580152 mW}\";\n ATTRIBUTE X_INTERFACE_INFO : STRING;\n ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS \"xilinx.com:interface:bram:1.0 BRAM_PORTA CLK\";\n ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS \"xilinx.com:interface:bram:1.0 BRAM_PORTA EN\";\n ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS \"xilinx.com:interface:bram:1.0 BRAM_PORTA WE\";\n ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS \"xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR\";\n ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS \"xilinx.com:interface:bram:1.0 BRAM_PORTA DIN\";\n ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS \"xilinx.com:interface:bram:1.0 BRAM_PORTB CLK\";\n ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS \"xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR\";\n ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS \"xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT\";\nBEGIN\n U0 : blk_mem_gen_v8_3_4\n GENERIC MAP (\n C_FAMILY => \"kintex7\",\n C_XDEVICEFAMILY => \"kintex7\",\n C_ELABORATION_DIR => \"./\",\n C_INTERFACE_TYPE => 0,\n C_AXI_TYPE => 1,\n C_AXI_SLAVE_TYPE => 0,\n C_USE_BRAM_BLOCK => 0,\n C_ENABLE_32BIT_ADDRESS => 0,\n C_CTRL_ECC_ALGO => \"NONE\",\n C_HAS_AXI_ID => 0,\n C_AXI_ID_WIDTH => 4,\n C_MEM_TYPE => 1,\n C_BYTE_SIZE => 9,\n C_ALGORITHM => 1,\n C_PRIM_TYPE => 1,\n C_LOAD_INIT_FILE => 0,\n C_INIT_FILE_NAME => \"no_coe_file_loaded\",\n C_INIT_FILE => \"output_line_buffer.mem\",\n C_USE_DEFAULT_DATA => 0,\n C_DEFAULT_DATA => \"0\",\n C_HAS_RSTA => 0,\n C_RST_PRIORITY_A => \"CE\",\n C_RSTRAM_A => 0,\n C_INITA_VAL => \"0\",\n C_HAS_ENA => 1,\n C_HAS_REGCEA => 0,\n C_USE_BYTE_WEA => 0,\n C_WEA_WIDTH => 1,\n C_WRITE_MODE_A => \"NO_CHANGE\",\n C_WRITE_WIDTH_A => 256,\n C_READ_WIDTH_A => 256,\n C_WRITE_DEPTH_A => 1024,\n C_READ_DEPTH_A => 1024,\n C_ADDRA_WIDTH => 10,\n C_HAS_RSTB => 0,\n C_RST_PRIORITY_B => \"CE\",\n C_RSTRAM_B => 0,\n C_INITB_VAL => \"0\",\n C_HAS_ENB => 0,\n C_HAS_REGCEB => 0,\n C_USE_BYTE_WEB => 0,\n C_WEB_WIDTH => 1,\n C_WRITE_MODE_B => \"WRITE_FIRST\",\n C_WRITE_WIDTH_B => 64,\n C_READ_WIDTH_B => 64,\n C_WRITE_DEPTH_B => 4096,\n C_READ_DEPTH_B => 4096,\n C_ADDRB_WIDTH => 12,\n C_HAS_MEM_OUTPUT_REGS_A => 0,\n C_HAS_MEM_OUTPUT_REGS_B => 0,\n C_HAS_MUX_OUTPUT_REGS_A => 0,\n C_HAS_MUX_OUTPUT_REGS_B => 0,\n C_MUX_PIPELINE_STAGES => 0,\n C_HAS_SOFTECC_INPUT_REGS_A => 0,\n C_HAS_SOFTECC_OUTPUT_REGS_B => 0,\n C_USE_SOFTECC => 0,\n C_USE_ECC => 0,\n C_EN_ECC_PIPE => 0,\n C_HAS_INJECTERR => 0,\n C_SIM_COLLISION_CHECK => \"ALL\",\n C_COMMON_CLK => 0,\n C_DISABLE_WARN_BHV_COLL => 0,\n C_EN_SLEEP_PIN => 0,\n C_USE_URAM => 0,\n C_EN_RDADDRA_CHG => 0,\n C_EN_RDADDRB_CHG => 0,\n C_EN_DEEPSLEEP_PIN => 0,\n C_EN_SHUTDOWN_PIN => 0,\n C_EN_SAFETY_CKT => 0,\n C_DISABLE_WARN_BHV_RANGE => 0,\n C_COUNT_36K_BRAM => \"7\",\n C_COUNT_18K_BRAM => \"1\",\n C_EST_POWER_SUMMARY => \"Estimated Power for IP : 33.580152 mW\"\n )\n PORT MAP (\n clka => clka,\n rsta => '0',\n ena => ena,\n regcea => '0',\n wea => wea,\n addra => addra,\n dina => dina,\n clkb => clkb,\n rstb => '0',\n enb => '0',\n regceb => '0',\n web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),\n addrb => addrb,\n dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),\n doutb => doutb,\n injectsbiterr => '0',\n injectdbiterr => '0',\n eccpipece => '0',\n sleep => '0',\n deepsleep => '0',\n shutdown => '0',\n s_aclk => '0',\n s_aresetn => '0',\n s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),\n s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),\n s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),\n s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),\n s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),\n s_axi_awvalid => '0',\n s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 256)),\n s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),\n s_axi_wlast => '0',\n s_axi_wvalid => '0',\n s_axi_bready => '0',\n s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),\n s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),\n s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),\n s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),\n s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),\n s_axi_arvalid => '0',\n s_axi_rready => '0',\n s_axi_injectsbiterr => '0',\n s_axi_injectdbiterr => '0'\n );\nEND output_line_buffer_arch;\n" }, { "path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.xpr", "content": "\n\n\n\n\n\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "vhdl_rx/framebuffer-ctrl/framebuffer_ctrl.vhd", "content": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.NUMERIC_STD.ALL;\n\n--Framebuffer Controller for 4k camera demo\n--Copyright (C) 2016 David Shah\n--Licensed under the MIT License\n\n--This controls a AXI4 compliant framebuffer (implemented in DDR3) for the purposes\n--of processing the 4k camera stream to display on a 1080p monitor. It supports either\n--a 1x crop mode or a 0.5x zoom-out mode implemented by skipping lines and pixels\n\n--The input port is two pixels wide and the output port one pixel wide. VSYNC and DE inputs in both\n--cases are active high\n\nentity framebuffer_ctrl_crop_scale is\n generic(\n burst_len : natural := 16;\n input_width : natural := 3840; --Pixel size of input video\n input_height : natural := 2160;\n output_width : natural := 1920; --Pixel size of output video\n output_height : natural := 1080;\n crop_xoffset : natural := 1024; --X/Y offset in crop mode (chosen to avoid bursts crossing a 4k boundary)\n crop_yoffset : natural := 540;\n scale_xoffset : natural := 0; --X/Y offset in scale mode (not used, for future purposes only)\n scale_yoffset : natural := 0\n );\n port(\n --Input pixel port\n input_clock : in std_logic;\n input_vsync : in std_logic;\n input_line_start : in std_logic;\n input_den : in std_logic;\n input_data_even : in std_logic_vector(23 downto 0);\n input_data_odd : in std_logic_vector(23 downto 0);\n\n --Output pixel port\n output_clock : in std_logic;\n output_vsync : in std_logic;\n output_line_start : in std_logic;\n output_den : in std_logic;\n output_data : out std_logic_vector(23 downto 0);\n\n --AXI4 master general\n axi_clock : in std_logic;\n axi_resetn : in std_logic;\n --AXI4 write address\n axi_awid : out std_logic_vector(0 downto 0);\n axi_awaddr : out std_logic_vector(29 downto 0);\n axi_awlen : out std_logic_vector(7 downto 0);\n axi_awsize : out std_logic_vector(2 downto 0);\n axi_awburst : out std_logic_vector(1 downto 0);\n axi_awlock : out std_logic_vector(0 downto 0);\n axi_awcache : out std_logic_vector(3 downto 0);\n axi_awprot : out std_logic_vector(2 downto 0);\n axi_awqos : out std_logic_vector(3 downto 0);\n axi_awvalid : out std_logic;\n axi_awready : in std_logic;\n --AXI4 write data\n axi_wdata : out std_logic_vector(255 downto 0);\n axi_wstrb : out std_logic_vector(31 downto 0);\n axi_wlast : out std_logic;\n axi_wvalid : out std_logic;\n axi_wready : in std_logic;\n --AXI4 write response\n axi_bid : in std_logic_vector(0 downto 0);\n axi_bresp : in std_logic_vector(1 downto 0);\n axi_bvalid : in std_logic;\n axi_bready : out std_logic;\n --AXI4 read address\n axi_arid : out std_logic_vector(0 downto 0);\n axi_araddr : out std_logic_vector(29 downto 0);\n axi_arlen : out std_logic_vector(7 downto 0);\n axi_arsize : out std_logic_vector(2 downto 0);\n axi_arburst : out std_logic_vector(1 downto 0);\n axi_arlock : out std_logic_vector(0 downto 0);\n axi_arcache : out std_logic_vector(3 downto 0);\n axi_arprot : out std_logic_vector(2 downto 0);\n axi_arqos : out std_logic_vector(3 downto 0);\n axi_arvalid : out std_logic;\n axi_arready : in std_logic;\n --AXI4 read data\n axi_rid : in std_logic_vector(0 downto 0);\n axi_rdata : in std_logic_vector(255 downto 0);\n axi_rresp : in std_logic_vector(1 downto 0);\n axi_rlast : in std_logic;\n axi_rvalid : in std_logic;\n axi_rready : out std_logic;\n --Misc\n zoom_mode : in std_logic; --0=scale, 1=crop\n freeze : in std_logic --assert to disable writing\n );\nend framebuffer_ctrl_crop_scale;\n\narchitecture Behavioral of framebuffer_ctrl_crop_scale is\n\n COMPONENT input_line_buffer\n PORT (\n clka : IN STD_LOGIC;\n ena : IN STD_LOGIC;\n wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);\n addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);\n dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);\n clkb : IN STD_LOGIC;\n addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);\n doutb : OUT STD_LOGIC_VECTOR(255 DOWNTO 0)\n );\n END COMPONENT;\n\n COMPONENT output_line_buffer\n PORT (\n clka : IN STD_LOGIC;\n ena : IN STD_LOGIC;\n wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);\n addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);\n dina : IN STD_LOGIC_VECTOR(255 DOWNTO 0);\n clkb : IN STD_LOGIC;\n addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);\n doutb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)\n );\n END COMPONENT;\n\n signal global_reset : std_logic;\n\n signal write_state : natural range 0 to 4;\n signal write_count : natural range 0 to burst_len-1;\n signal read_state : natural range 0 to 3;\n\n\n signal input_linebuf_read_high, input_linebuf_write_high, output_linebuf_read_high, output_linebuf_write_high : std_logic_vector(0 downto 0);\n\n signal input_read_x, input_write_x, output_read_x, output_write_x : natural range 0 to 4095;\n signal input_read_y, input_write_y, output_read_y, output_write_y : natural range 0 to 4095;\n\n signal input_write_y_curr, input_write_y_last, output_read_y_curr, output_read_y_last : natural range 0 to 4095;\n\n signal input_linebuf_write_addr : std_logic_vector(11 downto 0);\n signal input_linebuf_read_addr : std_logic_vector(9 downto 0);\n signal output_linebuf_write_addr : std_logic_vector(9 downto 0);\n signal output_linebuf_read_addr : std_logic_vector(11 downto 0);\n\n signal input_linebuf_din : std_logic_vector(63 downto 0);\n signal input_linebuf_wren : std_logic_vector(0 downto 0);\n signal input_linebuf_q : std_logic_vector(255 downto 0);\n\n signal output_linebuf_din : std_logic_vector(255 downto 0);\n signal output_linebuf_wren : std_logic_vector(0 downto 0);\n signal output_linebuf_q : std_logic_vector(63 downto 0);\n\n signal fb_read_address : std_logic_vector(23 downto 0);\n signal fb_write_address : std_logic_vector(23 downto 0);\n\n signal output_write_end_x : natural range 0 to 4095;\n\n signal axi_wready_last : std_logic;\n signal input_linebuf_ready : std_logic;\n\n --Average two pixels for downscaling purposes\n function rgb_average(pixel_1, pixel_2 : std_logic_vector)\n return std_logic_vector is\n variable pixel_1_t, pixel_2_t : std_logic_vector(23 downto 0);\n variable sum : unsigned(8 downto 0);\n variable result : std_logic_vector(23 downto 0);\n begin\n pixel_1_t := pixel_1;\n pixel_2_t := pixel_2;\n for i in 0 to 2 loop\n sum := resize(unsigned(pixel_1_t((8*i+7) downto (8*i))), 9) + resize(unsigned(pixel_2_t((8*i+7) downto (8*i))), 9);\n result((8*i+7) downto (8*i)) := std_logic_vector(sum(8 downto 1));\n end loop;\n return result;\n end function;\n\nbegin\n\n global_reset <= not axi_resetn;\n\n input_linebuf_write_addr <= input_linebuf_write_high & std_logic_vector(to_unsigned(input_write_x, 12)(11 downto 1));\n input_linebuf_read_addr <= input_linebuf_read_high & std_logic_vector(to_unsigned(input_read_x, 12)(11 downto 3));\n output_linebuf_write_addr <= output_linebuf_write_high & std_logic_vector(to_unsigned(output_write_x, 12)(11 downto 3));\n output_linebuf_read_addr <= output_linebuf_read_high & std_logic_vector(to_unsigned(output_read_x, 12)(11 downto 1));\n\n fb_write_address <= std_logic_vector(to_unsigned((input_read_y * input_width) + input_read_x, 24));\n\n fb_read_address <= std_logic_vector(to_unsigned((output_write_y * input_width * 2) + output_write_x, 24)) when zoom_mode = '0' else\n std_logic_vector(to_unsigned(((output_write_y + crop_yoffset) * input_width) + output_write_x + crop_xoffset, 24));\n\n output_write_end_x <= (output_width * 2) when zoom_mode = '0' else output_width;\n\n process(input_clock)\n begin\n if rising_edge(input_clock) then\n if input_vsync = '1' then\n input_write_x <= 0;\n input_write_y <= 4095;\n input_linebuf_write_high <= \"1\";\n elsif input_line_start = '1' then\n input_write_x <= 0;\n input_linebuf_write_high <= not input_linebuf_write_high;\n if input_write_y = 4095 then\n input_write_y <= 0;\n else\n input_write_y <= input_write_y + 1;\n end if;\n elsif input_den = '1' then\n input_write_x <= input_write_x + 2; --2 pixels per clock\n end if;\n end if;\n end process;\n\n process(output_clock)\n begin\n if rising_edge(output_clock) then\n if output_vsync = '1' then\n output_read_x <= 0;\n output_read_y <= 4095;\n output_linebuf_read_high <= \"1\";\n elsif output_line_start = '1' then\n output_read_x <= 0;\n output_linebuf_read_high <= not output_linebuf_read_high;\n if output_read_y = 4095 then\n output_read_y <= 0;\n else\n output_read_y <= output_read_y + 1;\n end if;\n elsif output_den = '1' then\n if zoom_mode = '0' then\n output_read_x <= output_read_x + 2; --2 pixels per clock for downscaling\n else\n output_read_x <= output_read_x + 1;\n end if;\n end if;\n end if;\n end process;\n\n process(axi_clock)\n begin\n if rising_edge(axi_clock) then\n input_write_y_curr <= input_write_y;\n input_write_y_last <= input_write_y_curr;\n output_read_y_curr <= output_read_y;\n output_read_y_last <= output_read_y_curr;\n --Only make changes not during writes/reads\n if write_state = 0 then\n --Has write y (i.e. other side) changed?\n if input_write_y_curr /= input_write_y_last then\n input_read_x <= 0;\n end if;\n input_read_y <= input_write_y_curr - 1;\n input_linebuf_read_high <= not input_linebuf_write_high;\n input_linebuf_ready <= '1';\n elsif write_state = 3 then\n if axi_wready = '1' and input_linebuf_ready = '1' then\n input_read_x <= input_read_x + 8;\n input_linebuf_ready <= '0';\n else\n input_linebuf_ready <= '1';\n end if;\n else\n input_linebuf_ready <= '1';\n end if;\n\n -- if axi_wready = '1' and axi_wready_last = '0' then\n -- input_linebuf_ready <= '0';\n -- else\n -- input_linebuf_ready <= '1';\n -- end if;\n\n if read_state = 0 then\n if output_read_y_curr /= output_read_y_last then\n output_write_x <= 0;\n end if;\n if output_read_y_curr = 4095 then\n output_write_y <= 0;\n else\n output_write_y <= output_read_y_curr + 1;\n end if;\n output_linebuf_write_high <= not output_linebuf_read_high;\n elsif read_state = 2 then\n if axi_rvalid = '1' then\n output_write_x <= output_write_x + 8;\n end if;\n end if;\n end if;\n end process;\n\n process(output_linebuf_q, zoom_mode, output_read_x)\n begin\n if zoom_mode = '1' then --crop, alternate between LSW and MSW\n if output_read_x mod 2 = 0 then\n output_data <= output_linebuf_q(31 downto 8);\n else\n output_data <= output_linebuf_q(63 downto 40);\n end if;\n else --zoom, average between both pixels\n output_data <= rgb_average(output_linebuf_q(63 downto 40), output_linebuf_q(31 downto 8));\n end if;\n end process;\n\n input_linebuf_din <= input_data_odd & x\"00\" & input_data_even & x\"00\";\n input_linebuf_wren <= \"\" & input_den;\n\n axi_awaddr <= \"0000\" & fb_write_address & \"00\";\n axi_araddr <= \"0000\" & fb_read_address & \"00\";\n --Write state machine\n process(axi_clock)\n begin\n if rising_edge(axi_clock) then\n axi_wready_last <= axi_wready;\n if global_reset = '1' then\n write_state <= 0;\n write_count <= 0;\n else\n case write_state is\n when 0 => --wait to be able to start writing\n if input_read_x < input_width and input_read_y < input_height and freeze = '0' then\n write_state <= 1;\n end if;\n when 1 => --assert awvalid, wait for awready\n if axi_awready = '1' then\n write_state <= 2;\n write_count <= 0;\n end if;\n when 2 => --begin write\n write_state <= 3;\n when 3 => --write in progress\n if input_linebuf_ready = '1' and axi_wready = '1' then\n if write_count = burst_len - 1 then\n write_state <= 4;\n else\n write_count <= write_count + 1;\n end if;\n end if;\n when 4 =>\n write_state <= 0;\n end case;\n end if;\n end if;\n end process;\n\n axi_awvalid <= '1' when write_state = 1 else '0';\n axi_wvalid <= input_linebuf_ready when write_state = 3 else '0';\n axi_wlast <= '1' when write_state = 3 and write_count = burst_len - 1 else '0';\n axi_wdata <= input_linebuf_q;\n\n --Read state machine\n process(axi_clock)\n begin\n if rising_edge(axi_clock) then\n if global_reset = '1' then\n read_state <= 0;\n else\n case read_state is\n when 0 => --wait to be able to start reading\n if output_write_x < output_write_end_x and output_write_y < output_height then\n read_state <= 1;\n end if;\n when 1 => --assert arvalid, wait for arready\n if axi_arready = '1' then\n read_state <= 2;\n end if;\n\n when 2 => --read in progress\n\n if axi_rvalid = '1' and axi_rlast = '1' then\n read_state <= 3;\n end if;\n when 3 =>\n read_state <= 0;\n end case;\n end if;\n end if;\n end process;\n\n axi_arvalid <= '1' when read_state = 1 else '0';\n output_linebuf_wren <= \"1\" when ((read_state = 1) or (read_state = 2)) and (axi_rvalid = '1') else \"0\";\n --Split pixels between the two fifos\n output_linebuf_din <= axi_rdata;\n\n inbuf : input_line_buffer\n port map(\n clka => input_clock,\n ena => '1',\n wea => input_linebuf_wren,\n addra => input_linebuf_write_addr,\n dina => input_linebuf_din,\n\n clkb => axi_clock,\n addrb => input_linebuf_read_addr,\n doutb => input_linebuf_q\n );\n\n outbuf : output_line_buffer\n port map(\n clka => axi_clock,\n ena => '1',\n wea => output_linebuf_wren,\n addra => output_linebuf_write_addr,\n dina => output_linebuf_din,\n\n clkb => output_clock,\n addrb => output_linebuf_read_addr,\n doutb => output_linebuf_q\n );\n\n --Hardwired AXI4 signals (useful)\n axi_awlen <= std_logic_vector(to_unsigned(burst_len - 1, 8)); --burst len of 16 transfers (128 32-bit words)\n axi_arlen <= std_logic_vector(to_unsigned(burst_len - 1, 8));\n axi_awsize <= \"010\"; --not sure about this - AXI4 spec does not consider 256-bit datapath\n axi_arsize <= \"010\";\n axi_awburst <= \"01\"; --INCR burst type\n axi_arburst <= \"01\";\n axi_rready <= '1'; --we're always ready\n axi_bready <= '1';\n axi_wstrb <= (others => '1'); --all data bytes always valid\n axi_awid <= \"0\";\n axi_arid <= \"1\";\n\n --Hardwired AXI4 signals (useless)\n axi_awlock <= \"0\";\n axi_awcache <= \"0011\";\n axi_awprot <= \"000\";\n axi_awqos <= \"0000\";\n axi_arlock <= \"0\";\n axi_arcache <= \"0011\";\n axi_arprot <= \"000\";\n axi_arqos <= \"0000\";\nend Behavioral;\n" }, { "path": "vhdl_rx/framebuffer-ctrl/input_line_buffer.xci", "content": "\n\n xilinx.com\n xci\n unknown\n 1.0\n \n \n input_line_buffer\n \n \n 4096\n 12\n 10\n 1\n 4\n 0\n 1\n 9\n 0\n 1\n 7\n NONE\n 0\n 0\n 0\n ./\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n Estimated Power for IP : 36.714252 mW\n kintex7\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n input_line_buffer.mem\n no_coe_file_loaded\n 0\n 0\n 1\n 0\n 1\n 4096\n 1024\n 64\n 256\n 0\n 0\n CE\n CE\n ALL\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 1\n 4096\n 1024\n NO_CHANGE\n WRITE_FIRST\n 64\n 256\n kintex7\n 4\n Memory_Slave\n AXI4_Full\n false\n Minimum_Area\n false\n 9\n NONE\n no_coe_file_loaded\n ALL\n input_line_buffer\n false\n false\n false\n false\n false\n false\n false\n false\n false\n Use_ENA_Pin\n Always_Enabled\n Single_Bit_Error_Injection\n false\n Native\n false\n no_mem_loaded\n Simple_Dual_Port_RAM\n NO_CHANGE\n WRITE_FIRST\n 0\n 0\n BRAM\n 0\n 100\n 100\n 50\n 100\n 100\n 0\n 8kx2\n false\n false\n 64\n 256\n false\n false\n false\n false\n 0\n false\n false\n CE\n CE\n SYNC\n false\n false\n false\n false\n false\n false\n false\n 4096\n 64\n 256\n No_ECC\n false\n false\n false\n Stand_Alone\n kintex7\n \n xc7k325t\n ffg900\n VERILOG\n \n MIXED\n -2\n \n TRUE\n TRUE\n IP_Flow\n 4\n TRUE\n .\n \n .\n 2016.3\n OUT_OF_CONTEXT\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "vhdl_rx/framebuffer-ctrl/output_line_buffer.xci", "content": "\n\n xilinx.com\n xci\n unknown\n 1.0\n \n \n output_line_buffer\n \n \n 4096\n 10\n 12\n 1\n 4\n 0\n 1\n 9\n 0\n 1\n 7\n NONE\n 0\n 0\n 0\n ./\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n Estimated Power for IP : 33.580152 mW\n kintex7\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n output_line_buffer.mem\n no_coe_file_loaded\n 0\n 0\n 1\n 0\n 1\n 1024\n 4096\n 256\n 64\n 0\n 0\n CE\n CE\n ALL\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 1\n 1024\n 4096\n NO_CHANGE\n WRITE_FIRST\n 256\n 64\n kintex7\n 4\n Memory_Slave\n AXI4_Full\n false\n Minimum_Area\n false\n 9\n NONE\n no_coe_file_loaded\n ALL\n output_line_buffer\n false\n false\n false\n false\n false\n false\n false\n false\n false\n Use_ENA_Pin\n Always_Enabled\n Single_Bit_Error_Injection\n false\n Native\n false\n no_mem_loaded\n Simple_Dual_Port_RAM\n NO_CHANGE\n WRITE_FIRST\n 0\n 0\n BRAM\n 0\n 100\n 100\n 50\n 100\n 100\n 0\n 8kx2\n false\n false\n 256\n 64\n false\n false\n false\n false\n 0\n false\n false\n CE\n CE\n SYNC\n false\n false\n false\n false\n false\n false\n false\n 1024\n 256\n 64\n No_ECC\n false\n false\n false\n Stand_Alone\n kintex7\n \n xc7k325t\n ffg900\n VERILOG\n \n MIXED\n -2\n \n TRUE\n TRUE\n IP_Flow\n 4\n TRUE\n .\n \n .\n 2016.3\n OUT_OF_CONTEXT\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n" }, { "path": "vhdl_rx/mipi-csi-rx/csi_rx_10bit_unpack.vhd", "content": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.NUMERIC_STD.ALL;\n\n--MIPI CSI-2 10bit pixel unpacker\n--Copyright (C) 2016 David Shah\n--Licensed under the MIT License\n\n--This receives 32-bit words from the long video packet payload in; and unpacks them\n--into 40 bits of output (which is only active - signified with the 'dout_valid' output -\n--80% of the time). It is intended that the dout_valid signal drives the write enable for a linebuffer\n--or FIFO.\n\n--At the moment only MIPI 10bit RAW format is supported, other formats may be\n--supported in the future (for 8bit you could simply bypass this entity)\n\n\nentity csi_rx_10bit_unpack is\n Port ( clock : in STD_LOGIC; --word clock in\n reset : in STD_LOGIC; --synchronous active high reset\n enable : in STD_LOGIC; --active high enable\n data_in : in STD_LOGIC_VECTOR (31 downto 0); --packet payload in\n din_valid : in STD_LOGIC; --payload in valid\n data_out : out STD_LOGIC_VECTOR (39 downto 0); --unpacked data out\n dout_valid : out STD_LOGIC); --data out valid (see above)\nend csi_rx_10bit_unpack;\n\narchitecture Behavioral of csi_rx_10bit_unpack is\n signal dout_int : std_logic_vector(39 downto 0);\n signal bytes_int : std_logic_vector(31 downto 0);\n signal byte_count_int : integer range 0 to 4;\n signal dout_valid_int : std_logic;\n signal dout_unpacked : std_logic_vector(39 downto 0);\n signal dout_valid_up : std_logic;\n\n --Unpack CSI packed 10-bit to 4 sequential 10-bit pixels\n function mipi_unpack(packed : std_logic_vector)\n return std_logic_vector is\n variable result : std_logic_vector(39 downto 0);\n begin\n result(9 downto 0) := packed(7 downto 0) & packed(33 downto 32);\n result(19 downto 10) := packed(15 downto 8) & packed(35 downto 34);\n result(29 downto 20) := packed(23 downto 16) & packed(37 downto 36);\n result(39 downto 30) := packed(31 downto 24) & packed(39 downto 38);\n\n return result;\n end mipi_unpack;\n\nbegin\n\n process(clock, reset)\n begin\n if rising_edge(clock) then\n if reset = '1' then\n dout_int <= x\"0000000000\";\n byte_count_int <= 0;\n dout_valid_int <= '0';\n elsif enable = '1' then\n if din_valid = '1' then\n --Behaviour is based on the number of bytes in the buffer\n case byte_count_int is\n when 0 =>\n dout_int <= x\"0000000000\";\n dout_valid_int <= '0';\n bytes_int <= data_in;\n byte_count_int <= 4;\n when 1 =>\n dout_int <= data_in & bytes_int(7 downto 0);\n dout_valid_int <= '1';\n bytes_int <= x\"00000000\";\n byte_count_int <= 0;\n when 2 =>\n dout_int <= data_in(23 downto 0) & bytes_int(15 downto 0);\n dout_valid_int <= '1';\n bytes_int <= x\"000000\" & data_in(31 downto 24);\n byte_count_int <= 1;\n when 3 =>\n dout_int <= data_in(15 downto 0) & bytes_int(23 downto 0);\n dout_valid_int <= '1';\n bytes_int <= x\"0000\" & data_in(31 downto 16);\n byte_count_int <= 2;\n when 4 =>\n dout_int <= data_in(7 downto 0) & bytes_int(31 downto 0);\n dout_valid_int <= '1';\n bytes_int <= x\"00\" & data_in(31 downto 8);\n byte_count_int <= 3;\n end case;\n else\n byte_count_int <= 0;\n dout_valid_int <= '0';\n end if;\n\n dout_unpacked <= mipi_unpack(dout_int);\n dout_valid_up <= dout_valid_int;\n data_out <= dout_unpacked;\n dout_valid <= dout_valid_up;\n end if;\n end if;\n end process;\nend Behavioral;\n" }, { "path": "vhdl_rx/mipi-csi-rx/csi_rx_4_lane_link.vhd", "content": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.NUMERIC_STD.ALL;\n\nlibrary UNISIM;\nuse UNISIM.VComponents.all;\n\n--MIPI CSI-2 Rx 4 lane link layer\n--Copyright (C) 2016 David Shah\n--Licensed under the MIT License\n\n--This combines the clock and data PHYs; byte aligners and word aligner to\n--form the lower levels of the CSI Rx link layer\n\nentity csi_rx_4_lane_link is\n generic(\n fpga_series : string := \"7SERIES\";\n\n dphy_term_en : boolean := true;\n\n d0_invert : boolean := false;\n d1_invert : boolean := false;\n d2_invert : boolean := false;\n d3_invert : boolean := false;\n\n d0_skew : natural := 0;\n d1_skew : natural := 0;\n d2_skew : natural := 0;\n d3_skew : natural := 0;\n\n generate_idelayctrl : boolean := false\n );\n port(\n dphy_clk : in STD_LOGIC_VECTOR (1 downto 0); --clock lane (1 is P, 0 is N)\n dphy_d0 : in STD_LOGIC_VECTOR (1 downto 0); --data lanes (1 is P, 0 is N)\n dphy_d1 : in STD_LOGIC_VECTOR (1 downto 0);\n dphy_d2 : in STD_LOGIC_VECTOR (1 downto 0);\n dphy_d3 : in STD_LOGIC_VECTOR (1 downto 0);\n ref_clock : in STD_LOGIC; --reference clock for clock detection and IDELAYCTRLs (nominally ~200MHz)\n reset : in STD_LOGIC; --active high synchronous reset in\n enable : in STD_LOGIC; --active high enable out\n wait_for_sync : in STD_LOGIC; --sync wait signal from packet handler\n packet_done : in STD_LOGIC; --packet done signal from packet handler\n reset_out : out STD_LOGIC; --reset output based on clock detection\n word_clock : out STD_LOGIC; --divided word clock output\n word_data : out STD_LOGIC_VECTOR (31 downto 0); --aligned word data output\n word_valid : out STD_LOGIC --whether or not above data is synced and aligned\n );\nend csi_rx_4_lane_link;\n\narchitecture Behavioral of csi_rx_4_lane_link is\n\n signal ddr_bit_clock : std_logic;\n signal ddr_bit_clock_b : std_logic;\n signal word_clock_int : std_logic;\n signal serdes_reset : std_logic;\n\n signal deser_data : std_logic_vector(31 downto 0);\n signal deser_data_rev : std_logic_vector(31 downto 0);\n\n signal byte_align_data : std_logic_vector(31 downto 0);\n signal byte_valid : std_logic_vector(3 downto 0);\n signal word_align_data : std_logic_vector(31 downto 0);\n\n signal byte_packet_done : std_logic;\n\nbegin\n\n clkphy : entity work.csi_rx_hs_clk_phy\n generic map(\n series => fpga_series,\n term_en => dphy_term_en)\n port map(\n dphy_clk => dphy_clk,\n reset => reset,\n ddr_bit_clock => ddr_bit_clock,\n ddr_bit_clock_b => ddr_bit_clock_b,\n byte_clock => word_clock_int);\n\n clkdet : entity work.csi_rx_clock_det\n port map(\n ref_clock => ref_clock,\n ext_clock => word_clock_int,\n enable => enable,\n reset_in => reset,\n reset_out => serdes_reset);\n\n\n d0phy : entity work.csi_rx_hs_lane_phy\n generic map(\n series => fpga_series,\n invert => d0_invert,\n term_en => dphy_term_en,\n delay => d0_skew)\n port map (\n ddr_bit_clock => ddr_bit_clock,\n ddr_bit_clock_b => ddr_bit_clock_b,\n byte_clock => word_clock_int,\n enable => enable,\n reset => serdes_reset,\n dphy_hs => dphy_d0,\n deser_out => deser_data(7 downto 0));\n\n d1phy : entity work.csi_rx_hs_lane_phy\n generic map(\n series => fpga_series,\n invert => d1_invert,\n term_en => dphy_term_en,\n delay => d1_skew)\n port map (\n ddr_bit_clock => ddr_bit_clock,\n ddr_bit_clock_b => ddr_bit_clock_b,\n byte_clock => word_clock_int,\n enable => enable,\n reset => serdes_reset,\n dphy_hs => dphy_d1,\n deser_out => deser_data(15 downto 8));\n\n d2phy : entity work.csi_rx_hs_lane_phy\n generic map(\n series => fpga_series,\n invert => d2_invert,\n term_en => dphy_term_en,\n delay => d2_skew)\n port map (\n ddr_bit_clock => ddr_bit_clock,\n ddr_bit_clock_b => ddr_bit_clock_b,\n byte_clock => word_clock_int,\n enable => enable,\n reset => serdes_reset,\n dphy_hs => dphy_d2,\n deser_out => deser_data(23 downto 16));\n\n d3phy : entity work.csi_rx_hs_lane_phy\n generic map(\n series => fpga_series,\n invert => d3_invert,\n term_en => dphy_term_en,\n delay => d3_skew)\n port map (\n ddr_bit_clock => ddr_bit_clock,\n ddr_bit_clock_b => ddr_bit_clock_b,\n byte_clock => word_clock_int,\n enable => enable,\n reset => serdes_reset,\n dphy_hs => dphy_d3,\n deser_out => deser_data(31 downto 24));\n\n gen_bytealign : for i in 0 to 3 generate\n ba : entity work.csi_rx_byte_align\n port map (\n clock => word_clock_int,\n reset => serdes_reset,\n enable => enable,\n deser_in => deser_data((8*i) + 7 downto 8 * i),\n wait_for_sync => wait_for_sync,\n packet_done => byte_packet_done,\n valid_data => byte_valid(i),\n data_out => byte_align_data((8*i) + 7 downto 8 * i));\n end generate;\n\n wordalign : entity work.csi_rx_word_align\n port map (\n word_clock => word_clock_int,\n reset => serdes_reset,\n enable => enable,\n packet_done => packet_done,\n wait_for_sync => wait_for_sync,\n packet_done_out => byte_packet_done,\n word_in => byte_align_data,\n valid_in => byte_valid,\n word_out => word_align_data,\n valid_out => word_valid);\n\n word_clock <= word_clock_int;\n word_data <= word_align_data;\n reset_out <= serdes_reset;\n\n gen_idctl : if generate_idelayctrl generate\n idctrl : entity work.csi_rx_idelayctrl_gen\n port map(\n ref_clock => ref_clock,\n reset => reset);\n end generate;\nend Behavioral;\n" }, { "path": "vhdl_rx/mipi-csi-rx/csi_rx_byte_align.vhd", "content": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.NUMERIC_STD.ALL;\n\n--MIPI CSI-2 byte aligner\n--Copyright (C) 2016 David Shah\n--Licensed under the MIT License\n\n--This receives raw, unaligned bytes (which could contain part of two actual bytes)\n--from the SERDES and aligns them by looking for the D-PHY sync pattern\n\n--When wait_for_sync is high the entity will wait until it sees the valid header at some alignment,\n--at which point the found alignment is locked until packet_done is asserted\n\n--valid_data is asserted as soon as the sync pattern is found, so the next byte\n--contains the CSI packet header\n\n--In reality to avoid false triggers we must look for a valid sync pattern on all 4 lanes,\n--if this does not occur the word aligner (a seperate entity) will assert packet_done immediately\n\nentity csi_rx_byte_align is\n port ( clock : in STD_LOGIC; --byte clock in\n reset : in STD_LOGIC; --synchronous active high reset\n enable : in STD_LOGIC; --active high enable\n deser_in : in STD_LOGIC_VECTOR (7 downto 0); --raw data from ISERDES\n wait_for_sync : in STD_LOGIC; --when high will look for a sync pattern if sync not already found\n packet_done : in STD_LOGIC; --assert to reset synchronisation status\n valid_data : out STD_LOGIC; --goes high as soon as sync pattern is found (so data out on next cycle contains header)\n data_out : out STD_LOGIC_VECTOR (7 downto 0)); --aligned data out, typically delayed by 2 cycles\nend csi_rx_byte_align;\n\narchitecture Behavioral of csi_rx_byte_align is\n\nsignal curr_byte : std_logic_vector(7 downto 0);\nsignal last_byte : std_logic_vector(7 downto 0);\nsignal shifted_byte : std_logic_vector(7 downto 0);\n\nsignal found_hdr : std_logic;\nsignal valid_data_int : std_logic;\nsignal hdr_offs : unsigned(2 downto 0);\nsignal data_offs : unsigned(2 downto 0);\n\nbegin\n\n process(clock)\n begin\n if rising_edge(clock) then\n if reset = '1' then\n valid_data_int <= '0';\n elsif enable = '1' then\n last_byte <= curr_byte;\n curr_byte <= deser_in;\n\t\t\t\t\t data_out <= shifted_byte;\n\n if packet_done = '1' then\n valid_data_int <= found_hdr;\n elsif wait_for_sync = '1' and found_hdr = '1' and valid_data_int = '0' then\n valid_data_int <= '1';\n data_offs <= hdr_offs;\n end if;\n end if;\n end if;\n end process;\n valid_data <= valid_data_int;\n --This assumes that data is arranged correctly (chronologically last bit in MSB)\n --and looks for the \"10111000\" sync sequence\n process(curr_byte, last_byte)\n constant sync : std_logic_vector(7 downto 0) := \"10111000\";\n variable was_found : boolean := false;\n variable offset : integer range 0 to 7;\n begin\n offset := 0;\n was_found := false;\n for i in 0 to 7 loop\n if (curr_byte(i downto 0) & last_byte(7 downto i + 1) = sync) and (unsigned(last_byte(i downto 0)) = 0) then\n was_found := true;\n offset := i;\n end if;\n end loop;\n if was_found then\n found_hdr <= '1';\n hdr_offs <= to_unsigned(offset, 3);\n else\n found_hdr <= '0';\n hdr_offs <= \"000\";\n end if;\n end process;\n\n --This aligns the data correctly\n shifted_byte <= curr_byte when data_offs = 7 else\n curr_byte(6 downto 0) & last_byte(7 downto 7) when data_offs = 6 else\n curr_byte(5 downto 0) & last_byte(7 downto 6) when data_offs = 5 else\n curr_byte(4 downto 0) & last_byte(7 downto 5) when data_offs = 4 else\n curr_byte(3 downto 0) & last_byte(7 downto 4) when data_offs = 3 else\n curr_byte(2 downto 0) & last_byte(7 downto 3) when data_offs = 2 else\n curr_byte(1 downto 0) & last_byte(7 downto 2) when data_offs = 1 else\n curr_byte(0 downto 0) & last_byte(7 downto 1);\n\n\nend Behavioral;\n" }, { "path": "vhdl_rx/mipi-csi-rx/csi_rx_clock_det.vhd", "content": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.NUMERIC_STD.ALL;\n\n--Simple Clock Detector for CSI-2 Rx\n--Copyright (C) 2016 David Shah\n--Licensed under the MIT License\n\n--This is designed to hold the ISERDES in reset until at least 3 byte clock\n--cycles have been detected; to ensure proper ISERDES behaviour\n--It will reassert reset once the byte clock has not toggled compared to the reference clock\n--for at least 200 reference clock cycles\n\nentity csi_rx_clock_det is\n port ( ref_clock : in std_logic; --reference clock in; must not be synchronised to ext_clock\n ext_clock : in STD_LOGIC; --external byte clock input for detection\n enable : in STD_LOGIC; --active high enable\n reset_in : in STD_LOGIC; --active high asynchronous reset in\n reset_out : out STD_LOGIC); --active high reset out to ISERDESs\nend csi_rx_clock_det;\n\narchitecture Behavioral of csi_rx_clock_det is\nsignal count_value : unsigned(3 downto 0);\nsignal clk_fail : std_logic;\nsignal ext_clk_lat : std_logic;\nsignal last_ext_clk : std_logic;\nsignal clk_fail_count : unsigned(7 downto 0);\nbegin\n process(ext_clock, reset_in, clk_fail)\n begin\n if reset_in = '1' or clk_fail = '1' then\n count_value <= x\"0\";\n elsif rising_edge(ext_clock) then\n\t\t\t\tif enable = '1' then\n\t\t\t\t\tif count_value < 3 then\n\t\t\t\t\t\t count_value <= count_value + 1;\n\t\t\t\t\tend if;\n\t\t\t\tend if;\n end if;\n end process;\n\t --Reset in between frames, by detecting the loss of the high speed clock\n\t process(ref_clock)\n\t begin\n\t\tif rising_edge(ref_clock) then\n\t\t\text_clk_lat <= ext_clock;\n\t\t\tlast_ext_clk <= ext_clk_lat;\n\t\t\tif last_ext_clk /= ext_clk_lat then\n\t\t\t\tclk_fail_count <= (others => '0');\n\t\t\telse\n\t\t\t\tif clk_fail_count < 250 then\n\t\t\t\t\tclk_fail_count <= clk_fail_count + 1;\n\t\t\t\tend if;\n\t\t\tend if;\n\t\tend if;\n\t end process;\n\n\t clk_fail <= '1' when clk_fail_count >= 200 else '0';\n reset_out <= '0' when count_value >= 2\t else '1';\nend Behavioral;\n" }, { "path": "vhdl_rx/mipi-csi-rx/csi_rx_hdr_ecc.vhd", "content": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\n\n--MIPI CSI-2 Header ECC calculation\n--Copyright (C) 2016 David Shah\n--Licensed under the MIT License\n\nentity csi_rx_hdr_ecc is\n Port ( data : in STD_LOGIC_VECTOR (23 downto 0);\n ecc : out STD_LOGIC_VECTOR (7 downto 0));\nend csi_rx_hdr_ecc;\n\narchitecture Behavioral of csi_rx_hdr_ecc is\n\nbegin\n ecc(7) <= '0';\n ecc(6) <= '0';\n ecc(5) <= data(10) xor data(11) xor data(12) xor data(13) xor data(14) xor data(15) xor data(16) xor data(17) xor data(18) xor data(19) xor data(21) xor data(22) xor data(23);\n ecc(4) <= data(4) xor data(5) xor data(6) xor data(7) xor data(8) xor data(9) xor data(16) xor data(17) xor data(18) xor data(19) xor data(20) xor data(22) xor data(23);\n ecc(3) <= data(1) xor data(2) xor data(3) xor data(7) xor data(8) xor data(9) xor data(13) xor data(14) xor data(15) xor data(19) xor data(20) xor data(21) xor data(23);\n ecc(2) <= data(0) xor data(2) xor data(3) xor data(5) xor data(6) xor data(9) xor data(11) xor data(12) xor data(15) xor data(18) xor data(20) xor data(21) xor data(22);\n ecc(1) <= data(0) xor data(1) xor data(3) xor data(4) xor data(6) xor data(8) xor data(10) xor data(12) xor data(14) xor data(17) xor data(20) xor data(21) xor data(22) xor data(23);\n ecc(0) <= data(0) xor data(1) xor data(2) xor data(4) xor data(5) xor data(7) xor data(10) xor data(11) xor data(13) xor data(16) xor data(20) xor data(21) xor data(22) xor data(23);\nend Behavioral;\n" }, { "path": "vhdl_rx/mipi-csi-rx/csi_rx_hs_clk_phy.vhd", "content": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\n\nlibrary UNISIM;\nuse UNISIM.VComponents.all;\n\n--High-Speed D-PHY clock RX PHY for MIPI CSI-2 Rx core\n--Copyright (C) 2016 David Shah\n--Licensed under the MIT License\n\n-- This receives the input clock and produces both real and complement DDR bit\n-- clocks and an SDR (i.e. in/4) byte clock for the SERDES and other downstream devices\n\n\nentity csi_rx_hs_clk_phy is\n\t generic (\n series : string := \"7SERIES\"; --FPGA series, 7SERIES or VIRTEX6\n\t\tterm_en : boolean := true\n );\n port (\n dphy_clk : in STD_LOGIC_VECTOR (1 downto 0); --D-PHY clock input; 1 is P, 0 is N\n reset : in STD_LOGIC; --reset input for BUFR\n ddr_bit_clock : out STD_LOGIC; --DDR bit clock (i.e. input clock buffered) out\n ddr_bit_clock_b : out STD_LOGIC; --Inverted DDR bit clock out\n byte_clock : out STD_LOGIC --SDR byte clock (i.e. input clock / 4) out\n );\nend csi_rx_hs_clk_phy;\n\narchitecture Behavioral of csi_rx_hs_clk_phy is\nsignal bit_clock_int_pre : std_logic;\nsignal bit_clock_int : std_logic;\nsignal bit_clock_b_int : std_logic;\nsignal byte_clock_int : std_logic;\nbegin\n\ticlkdbuf : IBUFDS\n\t\tgeneric map (\n\t\t\tDIFF_TERM => term_en,\n\t\t\tIBUF_LOW_PWR => FALSE,\n\t\t\tIOSTANDARD => \"DEFAULT\"\n\t\t)\n\t\tport map(\n\t\t\tO => bit_clock_int_pre,\n\t\t\tI => dphy_clk(1),\n\t\t\tIB => dphy_clk(0)\n\t\t);\n\n\ticlkbufio: BUFIO\n\t\tport map (\n\t\t\tO => bit_clock_int,\n\t\t\tI => bit_clock_int_pre\n\t\t);\n\n\n bit_clock_b_int <= NOT bit_clock_int;\n\n clkdiv : BUFR\n\t\tgeneric map (\n\t\t\tBUFR_DIVIDE => \"4\",\n\t\t\tSIM_DEVICE => series\n\t\t)\n\t\tport map (\n\t\t\tO => byte_clock_int,\n\t\t\tCE => '1',\n\t\t\tCLR => reset,\n\t\t\tI => bit_clock_int_pre\n\t\t);\n\n ddr_bit_clock <= bit_clock_int;\n ddr_bit_clock_b <= bit_clock_b_int;\n byte_clock <= byte_clock_int;\nend Behavioral;\n" }, { "path": "vhdl_rx/mipi-csi-rx/csi_rx_hs_lane_phy.vhd", "content": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.NUMERIC_STD.ALL;\n\nlibrary UNISIM;\nuse UNISIM.VComponents.all;\n\n--High-Speed D-PHY lane RX PHY for MIPI CSI-2 Rx core\n--Copyright (C) 2016 David Shah\n--Licensed under the MIT License\n\n--This entity handles input skew compensation and deserialisation for the\n--CSI data input lanes. Output is has arbitrary alignment which must be fixed later on\n--in the processing chain\nentity csi_rx_hs_lane_phy is\ngeneric(\n series : string := \"7SERIES\"; --FPGA series, 7SERIES or VIRTEX6\n invert : boolean := false; --Whether or not to invert output (i.e. if pairs are swapped)\n term_en : boolean := true; --Whether or not to enable internal input termination\n delay : natural --IDELAY delay value for skew compensation\n);\n\nport (\n ddr_bit_clock : in STD_LOGIC; --true and complement DDR bit clocks, buffered from D-PHY clock\n ddr_bit_clock_b : in STD_LOGIC;\n byte_clock : in STD_LOGIC; --byte clock; i.e. input clock /4\n enable : in STD_LOGIC; --active high enable for SERDES\n reset : in STD_LOGIC; --reset, latched internally to byte clock\n dphy_hs : in STD_LOGIC_VECTOR (1 downto 0); --lane input, 1 is P, 0 is N\n deser_out : out STD_LOGIC_VECTOR (7 downto 0) --deserialised byte output\n);\n\nend csi_rx_hs_lane_phy;\n\narchitecture Behavioral of csi_rx_hs_lane_phy is\nsignal reset_lat : std_logic; --reset synchronised to byte clock\nsignal in_se : std_logic; --input after differential buffer\nsignal in_delayed : std_logic; --input after deskew\n\n--for Virtex-6 devices where we cascade two ISERDESs\nsignal shift_1 : std_logic;\nsignal shift_2 : std_logic;\n\nsignal serdes_out_int : std_logic_vector(7 downto 0);\nbegin\n\n process(byte_clock)\n begin\n if rising_edge(byte_clock) then\n reset_lat <= reset;\n end if;\n end process;\n\n inbuf : IBUFDS\n generic map(\n DIFF_TERM => term_en,\n IBUF_LOW_PWR => FALSE,\n IOSTANDARD => \"DEFAULT\")\n port map(\n O => in_se,\n I => dphy_hs(1),\n IB => dphy_hs(0));\n\n\n --7 series specific blocks\n gen_7s : if series = \"7SERIES\" generate\n\n indelay : IDELAYE2\n generic map (\n CINVCTRL_SEL => \"FALSE\",\n DELAY_SRC => \"IDATAIN\",\n HIGH_PERFORMANCE_MODE => \"TRUE\",\n IDELAY_TYPE => \"FIXED\",\n IDELAY_VALUE => delay,\n REFCLK_FREQUENCY => 200.0,\n SIGNAL_PATTERN => \"DATA\",\n PIPE_SEL => \"FALSE\"\n )\n port map (\n DATAOUT => in_delayed,\n DATAIN => '0',\n C => byte_clock,\n CE => '0',\n INC => '0',\n IDATAIN => in_se,\n CNTVALUEIN => \"00000\",\n CNTVALUEOUT => open,\n CINVCTRL => '0',\n LD => '0',\n LDPIPEEN => '0',\n REGRST => '0'\n );\n\n ideser : ISERDESE2\n generic map (\n DATA_RATE => \"DDR\",\n DATA_WIDTH => 8,\n DYN_CLKDIV_INV_EN => \"FALSE\",\n DYN_CLK_INV_EN => \"FALSE\",\n INIT_Q1 => '0',\n INIT_Q2 => '0',\n INIT_Q3 => '0',\n INIT_Q4 => '0',\n INTERFACE_TYPE => \"NETWORKING\",\n IOBDELAY => \"IFD\",\n NUM_CE => 1,\n OFB_USED => \"FALSE\",\n SERDES_MODE => \"MASTER\",\n SRVAL_Q1 => '0',\n SRVAL_Q2 => '0',\n SRVAL_Q3 => '0',\n SRVAL_Q4 => '0')\n port map (\n O => open,\n --In the ISERDESE2, Q8 is the oldest bit but in the CSI spec\n --the MSB is the most recent bit. So we mirror the output\n Q1 => serdes_out_int(7),\n Q2 => serdes_out_int(6),\n Q3 => serdes_out_int(5),\n Q4 => serdes_out_int(4),\n Q5 => serdes_out_int(3),\n Q6 => serdes_out_int(2),\n Q7 => serdes_out_int(1),\n Q8 => serdes_out_int(0),\n SHIFTOUT1 => open,\n SHIFTOUT2 => open,\n BITSLIP => '0',\n CE1 => enable,\n CE2 => '1',\n CLKDIVP => '0',\n CLK => ddr_bit_clock,\n CLKB => ddr_bit_clock_b,\n CLKDIV => byte_clock,\n OCLK => '0',\n DYNCLKDIVSEL => '0',\n DYNCLKSEL => '0',\n D => '0',\n DDLY => in_delayed,\n OFB => '0',\n OCLKB => '0',\n RST => reset_lat,\n SHIFTIN1 => '0',\n SHIFTIN2 => '0'\n );\n\n end generate;\n\n\n --Legacy Virtex-6 specific blocks\n gen_v6 : if series = \"VIRTEX6\" generate\n --Input delay for skew compensation\n indelay : IODELAYE1\n generic map (\n CINVCTRL_SEL => FALSE,\n DELAY_SRC => \"I\",\n HIGH_PERFORMANCE_MODE => TRUE,\n IDELAY_TYPE => \"FIXED\",\n IDELAY_VALUE => delay,\n ODELAY_TYPE => \"FIXED\",\n ODELAY_VALUE => 0,\n REFCLK_FREQUENCY => 200.0,\n SIGNAL_PATTERN => \"DATA\"\n )\n port map (\n DATAOUT => in_delayed,\n DATAIN => '0',\n C => byte_clock,\n CE => '0',\n INC => '0',\n IDATAIN => in_se,\n ODATAIN => '0',\n RST => '0',\n T => '1',\n CNTVALUEIN => \"00000\",\n CNTVALUEOUT => open,\n CLKIN => '0',\n CINVCTRL => '0'\n );\n\n --Input deserialisation\n ideser1 : ISERDESE1\n generic map (\n DATA_RATE => \"DDR\",\n DATA_WIDTH => 8,\n DYN_CLKDIV_INV_EN => FALSE,\n DYN_CLK_INV_EN => FALSE,\n INIT_Q1 => '0',\n INIT_Q2 => '0',\n INIT_Q3 => '0',\n INIT_Q4 => '0',\n\n INTERFACE_TYPE => \"NETWORKING\",\n IOBDELAY => \"IFD\",\n NUM_CE => 2,\n OFB_USED => FALSE,\n SERDES_MODE => \"MASTER\",\n SRVAL_Q1 => '0',\n SRVAL_Q2 => '0',\n SRVAL_Q3 => '0',\n SRVAL_Q4 => '0'\n\n )\n port map(\n O => open,\n Q1 => serdes_out_int(7),\n Q2 => serdes_out_int(6),\n Q3 => serdes_out_int(5),\n Q4 => serdes_out_int(4),\n Q5 => serdes_out_int(3),\n Q6 => serdes_out_int(2),\n SHIFTOUT1 => shift_1,\n SHIFTOUT2 => shift_2,\n BITSLIP => '0',\n CE1 => enable,\n CE2 => enable,\n CLK => ddr_bit_clock,\n CLKB => ddr_bit_clock_b,\n CLKDIV => byte_clock,\n D => '0',\n DDLY => in_delayed,\n DYNCLKDIVSEL => '0',\n DYNCLKSEL => '0',\n OCLK => '0',\n OFB => '0',\n RST => reset_lat,\n SHIFTIN1 => '0',\n SHIFTIN2 => '0');\n\n ideser2\t\t\t: ISERDESE1\n generic map (\n DATA_RATE => \"DDR\",\n DATA_WIDTH => 8,\n DYN_CLKDIV_INV_EN => FALSE,\n DYN_CLK_INV_EN => FALSE,\n\n INIT_Q1 => '0',\n INIT_Q2 => '0',\n INIT_Q3 => '0',\n INIT_Q4 => '0',\n INTERFACE_TYPE => \"NETWORKING\",\n IOBDELAY => \"IFD\",\n NUM_CE => 2,\n OFB_USED => FALSE,\n SERDES_MODE => \"SLAVE\",\n\n SRVAL_Q1 => '0',\n SRVAL_Q2 => '0',\n SRVAL_Q3 => '0',\n SRVAL_Q4 => '0'\n )\n port map(\n O => open,\n Q1 => open,\n Q2 => open,\n Q3 => serdes_out_int(1),\n Q4 => serdes_out_int(0),\n Q5 => open,\n Q6 => open,\n SHIFTOUT1 => open,\n SHIFTOUT2 => open,\n BITSLIP => '0',\n CE1 => enable,\n CE2 => enable,\n CLK => ddr_bit_clock,\n CLKB => ddr_bit_clock_b,\n CLKDIV => byte_clock,\n D => '0',\n DDLY => '0',\n DYNCLKDIVSEL => '0',\n DYNCLKSEL => '0',\n OCLK => '0',\n OFB => '0',\n RST => reset_lat,\n SHIFTIN1 => shift_1,\n SHIFTIN2 => shift_2);\n end generate;\n\n\n --Inversion of output based on generic\n gen_true : if not invert generate\n deser_out <= serdes_out_int;\n end generate;\n\n gen_inv : if invert generate\n deser_out <= not serdes_out_int;\n end generate;\nend architecture;\n" }, { "path": "vhdl_rx/mipi-csi-rx/csi_rx_idelayctrl_gen.vhd", "content": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\n\nlibrary UNISIM;\nuse UNISIM.VComponents.all;\n\n--Core-specific IDELAYCTRL wrapper\n--Copyright (C) 2016 David Shah\n--Licensed under the MIT License\n\nentity csi_rx_idelayctrl_gen is\n generic(\n fpga_series : string := \"7SERIES\"\n );\n port(\n ref_clock : in std_logic; --IDELAYCTRL reference clock\n reset : in std_logic --IDELAYCTRL reset\n );\nend csi_rx_idelayctrl_gen;\n\narchitecture Behavioral of csi_rx_idelayctrl_gen is\nbegin\n gen_v6_7s: if fpga_series = \"VIRTEX6\" or fpga_series = \"7SERIES\" generate\n delayctrl : IDELAYCTRL\n port map (\n RDY => open,\n REFCLK => ref_clock,\n RST => reset\n );\n end generate;\nend architecture;\n" }, { "path": "vhdl_rx/mipi-csi-rx/csi_rx_line_buffer.vhd", "content": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.NUMERIC_STD.ALL;\n\n--MIPI CSI-2 Rx Line Buffer\n--Copyright (C) 2016 David Shah\n--Licensed under the MIT License\n\nentity csi_rx_line_buffer is\n generic(\n line_width : natural := 3840; --width of a single line\n pixels_per_clock : natural := 2 --number of pixels output every clock cycle; either 1, 2 or 4\n );\n port(\n write_clock : in std_logic;\n write_addr : in natural range 0 to (line_width / 4) - 1;\n write_data : in std_logic_vector(39 downto 0); --write port is always 4 pixels wide\n write_en : in std_logic;\n\n read_clock : in std_logic;\n read_addr : in natural range 0 to (line_width / pixels_per_clock) - 1;\n read_q : out std_logic_vector((10 * pixels_per_clock) - 1 downto 0)\n );\nend csi_rx_line_buffer;\n\narchitecture Behavioral of csi_rx_line_buffer is\n type linebuf_t is array(0 to (line_width / 4) - 1) of std_logic_vector(39 downto 0);\n signal linebuf : linebuf_t;\n\n signal linebuf_read_address : natural range 0 to (line_width / 4) - 1;\n signal read_address_lat : natural range 0 to (line_width / pixels_per_clock) - 1;\n\n signal linebuf_read_q : std_logic_vector(39 downto 0);\nbegin\n\n process(write_clock)\n begin\n if rising_edge(write_clock) then\n if write_en = '1' then\n linebuf(write_addr) <= write_data;\n end if;\n end if;\n end process;\n\n process(read_clock)\n begin\n if rising_edge(read_clock) then\n read_address_lat <= read_addr;\n linebuf_read_q <= linebuf(linebuf_read_address);\n end if;\n end process;\n\n sppc : if pixels_per_clock = 1 generate\n linebuf_read_address <= read_addr / 4;\n read_q <= linebuf_read_q(9 downto 0) when read_address_lat mod 4 = 0 else\n linebuf_read_q(19 downto 10) when read_address_lat mod 4 = 1 else\n linebuf_read_q(29 downto 20) when read_address_lat mod 4 = 2 else\n linebuf_read_q(39 downto 30);\n end generate;\n\n dppc : if pixels_per_clock = 2 generate\n linebuf_read_address <= read_addr / 2;\n read_q <= linebuf_read_q(19 downto 0) when read_address_lat mod 2 = 0 else\n linebuf_read_q(39 downto 20);\n end generate;\n\n qppc : if pixels_per_clock = 4 generate\n linebuf_read_address <= read_addr;\n read_q <= linebuf_read_q;\n end generate;\nend architecture;\n" }, { "path": "vhdl_rx/mipi-csi-rx/csi_rx_packet_handler.vhd", "content": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.NUMERIC_STD.ALL;\n\n--MIPI CSI-2 Rx Packet Handler\n--Copyright (C) 2016 David Shah\n--Licensed under the MIT License\n\n--This controls the wait_for_sync and packet_done inputs to the byte/word aligners;\n--receives aligned words and processes them\n--It keeps track of whether or not we are currently in a video line or frame;\n--and pulls the video payload out of long packets of the correct type\n\nentity csi_rx_packet_handler is\n Port ( clock : in STD_LOGIC; --word clock in\n reset : in STD_LOGIC; --asynchronous active high reset\n enable : in STD_LOGIC; --active high enable\n data : in STD_LOGIC_VECTOR (31 downto 0); --data in from word aligner\n data_valid : in STD_LOGIC; --data valid in from word aligner\n sync_wait : out STD_LOGIC; --drives byte and word aligner wait_for_sync\n packet_done : out STD_LOGIC; --drives word aligner packet_done\n payload_out : out STD_LOGIC_VECTOR(31 downto 0); --payload out from long video packets\n payload_valid : out STD_LOGIC; --whether or not payload output is valid (i.e. currently receiving a long packet)\n vsync_out : out STD_LOGIC; --vsync output to timing controller\n in_frame : out STD_LOGIC; --whether or not currently in video frame (i.e. got FS but not FE)\n\t\t\t in_line : out STD_LOGIC); --whether or not receiving video line\nend csi_rx_packet_handler;\n\n\narchitecture Behavioral of csi_rx_packet_handler is\n signal is_hdr : std_logic;\n signal packet_type : std_logic_vector(7 downto 0);\n signal long_packet : std_logic;\n signal packet_len : unsigned(15 downto 0);\n signal packet_len_q : unsigned(15 downto 0) := x\"0000\";\n signal state : std_logic_vector(2 downto 0) := \"000\";\n signal bytes_read : unsigned(15 downto 0);\n signal in_frame_d : std_logic;\n signal in_line_d : std_logic;\n signal valid_packet : std_logic;\n\n\n signal packet_for_ecc : std_logic_vector(23 downto 0);\n signal expected_ecc : std_logic_vector(7 downto 0);\n\n function is_allowed_type(packet_type : std_logic_vector)\n return std_logic is\n variable result : std_logic;\n variable packet_type_temp : std_logic_vector(7 downto 0);\n begin\n packet_type_temp := packet_type; --keep GHDL happy\n case packet_type_temp is\n when x\"00\" | x\"01\" | x\"02\" | x\"03\" => --sync\n \tresult := '1';\n when x\"10\" | x\"11\" | x\"12\" => --non image\n \tresult := '1';\n when x\"28\" | x\"29\" | x\"2A\" | x\"2B\" | x\"2C\" | x\"2D\" => --RAW\n \tresult := '1';\n when others =>\n \tresult := '0';\n end case;\n return result;\n end is_allowed_type;\n\nbegin\n --Main state machine process\n process(reset, clock)\n begin\n if rising_edge(clock) then\n if reset = '1' then\n state <= \"000\";\n elsif enable = '1' then\n case state is\n when \"000\" => --waiting to init\n state <= \"001\";\n when \"001\" => --waiting for start\n bytes_read <= x\"0000\";\n if data_valid = '1' then\n packet_len_q <= packet_len;\n if long_packet = '1' then\n state <= \"010\";\n else\n state <= \"011\";\n end if;\n end if;\n when \"010\" => --rx long packet\n if (bytes_read < (packet_len_q - 4)) and(bytes_read < 8192) then\n bytes_read <= bytes_read + 4;\n else\n state <= \"011\";\n end if;\n when \"011\" => --packet done, assert packet_done\n state <= \"100\";\n when \"100\" => --wait one cycle and reset\n state <= \"001\";\n when others =>\n state <= \"000\";\n end case;\n end if;\n end if;\n end process;\n\n --At the moment we only calculate the expected ECC and compare it to the received ECC,\n --rejecting the packet if this fails. In the future it would be better to also correct\n --single bit errors\n ecc : entity work.csi_rx_hdr_ecc port map(\n data => packet_for_ecc,\n ecc => expected_ecc);\n\n packet_type <= \"00\" & data(5 downto 0);\n valid_packet <= '1' when (data(31 downto 24) = expected_ecc) and\n (is_allowed_type(packet_type) = '1') and\n (data(7 downto 6) = \"00\")\n else '0';\n\n is_hdr <= '1' when data_valid = '1' and state = \"001\"\n else '0';\n\n long_packet <= '1' when (packet_type > x\"0F\") and (valid_packet = '1')\n else '0';\n\n vsync_out <= '1' when is_hdr = '1' and packet_type = x\"00\"\n else '0';\n\n packet_for_ecc <= data(23 downto 0);\n packet_len <= unsigned(data(23 downto 8));\n\n process(reset, clock)\n begin\n if rising_edge(clock) then\n if reset = '1' then\n in_frame_d <= '0';\n in_line_d <= '0';\n elsif enable = '1' then\n if is_hdr = '1' and packet_type = x\"00\" and valid_packet = '1' then --FS\n in_frame_d <= '1';\n elsif is_hdr = '1' and packet_type = x\"01\" and valid_packet = '1' then --FE\n in_frame_d <= '0';\n end if;\n\n if is_hdr = '1' and (packet_type(7 downto 4) = x\"2\") and valid_packet = '1' then\n in_line_d <= '1';\n elsif state /= \"010\" and state /= \"001\" then\n in_line_d <= '0';\n end if;\n end if;\n end if;\n end process;\n\n in_frame <= in_frame_d;\n in_line <= in_line_d;\n sync_wait <= '1' when state = \"001\" else '0';\n packet_done <= '1' when state = \"011\" else '0';\n payload_out <= data when state = \"010\" else x\"00000000\";\n payload_valid <= '1' when state = \"010\" else '0';\n\nend Behavioral;\n" }, { "path": "vhdl_rx/mipi-csi-rx/csi_rx_top.vhd", "content": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.NUMERIC_STD.ALL;\n\n--VHDL MIPI CSI-2 Rx designed for Xilinx 7-series FPGAs\n--Copyright (C) 2016 David Shah\n--Licensed under the MIT License\n\n--This driver is designed for 4 lane links and has been tested with the Omnivison OV13850\n--It supports resolutions up to 4k at 30fps (higher has not been tested but may work) with\n--10-bit Bayer data (support for other output formats is not yet implemented). This is output\n--in traditional parallel video format with a few tweaks\n\n--For improved timing performance up to 4 pixels per clock can be output. For the ease of debayering blocks,\n--the previous line's data; and whether the current line is even (BGBG) or odd (GRGR) is also output.\n\n--At minimum you will need to provide it with suitable clocks from a PLL (the pixel clock input\n--should in general either be phase locked to the master clock input to the camera or the CSI byte clock)\n--and configure skew parameters and video port timings for your camera setup\n\n--The primary testing platform is a Digilent Genesys 2 (Kintex-7 XC7K325T) with a\n--custom FMC breakout board to connect two Firefly OV13850 modules.\n--A previous version has also been tested on a ML605 Virtex-6 development board;\n--however functioning support is not guaranteed\n\nentity csi_rx_4lane is\n generic (\n --FPGA series to control SERDES/buffer generation\n --either \"VIRTEX6\" or \"7SERIES\"\n fpga_series : string := \"7SERIES\";\n\n --Low-level PHY parameters\n\n dphy_term_en : boolean := true; --Enable internal termination on all pairs\n\n --Use these to invert channels if needed on your PCB\n d0_invert : boolean := false;\n d1_invert : boolean := false;\n d2_invert : boolean := false;\n d3_invert : boolean := false;\n\n --These skew values are the delay settings for the IDELAYs on each lane\n --Adjust these for optimum stability with your PCB layout and cameras\n d0_skew : natural := 0;\n d1_skew : natural := 0;\n d2_skew : natural := 0;\n d3_skew : natural := 0;\n\n --Output port pixel timings (for included OV13850 config at 23.98fps with MCLK 24.399MHz and output clock 145Mz)\n video_hlength : natural := 4041; --total visible and blanking pixels per line\n video_vlength : natural := 2992; --total visible and blanking lines per frame\n\n video_hsync_pol : boolean := true; --hsync polarity: true for positive sync, false for negative sync\n video_hsync_len : natural := 48; --horizontal sync length in pixels\n video_hbp_len : natural := 122; --horizontal back porch length (excluding sync)\n video_h_visible : natural := 3840; --number of visible pixels per line\n\n video_vsync_pol : boolean := true; --vsync polarity: true for positive sync, false for negative sync\n video_vsync_len : natural := 3; --vertical sync length in lines\n video_vbp_len : natural := 23; --vertical back porch length (excluding sync)\n video_v_visible : natural := 2160; --number of visible lines per frame\n\n pixels_per_clock : natural := 2; --Number of pixels per clock to output; 1, 2 or 4\n\n\n --Set this to false if this is not the first CSI rx or other IDELAY using device in the system\n generate_idelayctrl : boolean := false\n\n );\n port(\n ref_clock_in : in std_logic; --IDELAY reference clock (nominally 200MHz)\n pixel_clock_in : in std_logic; --Output pixel clock from PLL\n byte_clock_out : out std_logic; --DSI byte clock output\n\n enable : in std_logic; --system enable input\n reset : in std_logic; --synchronous active high reset input\n\n video_valid : out std_logic; --goes high when valid frames are being received\n\n --DSI signals, signal 1 is P and signal 0 is N\n dphy_clk : in std_logic_vector(1 downto 0);\n dphy_d0 : in std_logic_vector(1 downto 0);\n dphy_d1 : in std_logic_vector(1 downto 0);\n dphy_d2 : in std_logic_vector(1 downto 0);\n dphy_d3 : in std_logic_vector(1 downto 0);\n\n --Pixel data output\n video_hsync : out std_logic;\n video_vsync : out std_logic;\n video_den : out std_logic;\n video_line_start : out std_logic; --like hsync but asserted for one clock period only and only for visible lines\n video_odd_line : out std_logic; --LSB of y-coordinate for a downstream debayering block\n video_data : out std_logic_vector(((10 * pixels_per_clock) - 1) downto 0); --LSW is leftmost pixel\n video_prev_line_data : out std_logic_vector(((10 * pixels_per_clock) - 1) downto 0) --last line's data at this point, for a debayering block to use\n );\nend csi_rx_4lane;\n\narchitecture Behavioral of csi_rx_4lane is\n signal csi_byte_clock : std_logic;\n signal link_reset_out : std_logic;\n signal wait_for_sync : std_logic;\n signal packet_done : std_logic;\n signal word_clock : std_logic;\n signal word_data : std_logic_vector(31 downto 0);\n signal word_valid : std_logic;\n\n signal packet_payload : std_logic_vector(31 downto 0);\n signal packet_payload_valid : std_logic;\n signal csi_vsync : std_logic;\n signal csi_in_frame, csi_in_line : std_logic;\n\n signal unpack_data : std_logic_vector(39 downto 0);\n signal unpack_data_valid : std_logic;\nbegin\n link : entity work.csi_rx_4_lane_link\n generic map(\n fpga_series => fpga_series,\n dphy_term_en => dphy_term_en,\n d0_invert => d0_invert,\n d1_invert => d1_invert,\n d2_invert => d2_invert,\n d3_invert => d3_invert,\n d0_skew => d0_skew,\n d1_skew => d1_skew,\n d2_skew => d2_skew,\n d3_skew => d3_skew,\n generate_idelayctrl => generate_idelayctrl)\n port map(\n dphy_clk => dphy_clk,\n dphy_d0 => dphy_d0,\n dphy_d1 => dphy_d1,\n dphy_d2 => dphy_d2,\n dphy_d3 => dphy_d3,\n ref_clock => ref_clock_in,\n reset => reset,\n enable => enable,\n wait_for_sync => wait_for_sync,\n packet_done => packet_done,\n reset_out => link_reset_out,\n word_clock => csi_byte_clock,\n word_data => word_data,\n word_valid => word_valid);\n\n depacket : entity work.csi_rx_packet_handler\n port map (\n clock => csi_byte_clock,\n reset => link_reset_out,\n enable => enable,\n data => word_data,\n data_valid => word_valid,\n sync_wait => wait_for_sync,\n packet_done => packet_done,\n payload_out => packet_payload,\n payload_valid => packet_payload_valid,\n vsync_out => csi_vsync,\n in_frame => csi_in_frame,\n in_line => csi_in_line);\n\n unpack10 : entity work.csi_rx_10bit_unpack\n port map (\n clock => csi_byte_clock,\n reset => link_reset_out,\n enable => enable,\n data_in => packet_payload,\n din_valid => packet_payload_valid,\n data_out => unpack_data,\n dout_valid => unpack_data_valid);\n\n vout : entity work.csi_rx_video_output\n generic map (\n video_hlength => video_hlength,\n video_vlength => video_vlength,\n video_hsync_pol => video_hsync_pol,\n video_hsync_len => video_hsync_len,\n video_hbp_len => video_hbp_len,\n video_h_visible => video_h_visible,\n video_vsync_pol => video_vsync_pol,\n video_vsync_len => video_vsync_len,\n video_vbp_len => video_vbp_len,\n video_v_visible => video_v_visible,\n pixels_per_clock => pixels_per_clock)\n port map (\n output_clock => pixel_clock_in,\n csi_byte_clock => csi_byte_clock,\n enable => enable,\n reset => reset,\n pixel_data_in => unpack_data,\n pixel_data_valid => unpack_data_valid,\n csi_in_frame => csi_in_frame,\n csi_in_line => csi_in_line,\n csi_vsync => csi_vsync,\n video_valid => video_valid,\n video_hsync => video_hsync,\n video_vsync => video_vsync,\n video_den => video_den,\n video_line_start => video_line_start,\n video_odd_line => video_odd_line,\n video_data => video_data,\n video_prev_line_data => video_prev_line_data\n );\n\n byte_clock_out <= csi_byte_clock;\nend Behavioral;\n" }, { "path": "vhdl_rx/mipi-csi-rx/csi_rx_video_output.vhd", "content": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.NUMERIC_STD.ALL;\n\n--MIPI CSI-2 Rx Video Output Controller\n--Copyright (C) 2016 David Shah\n--Licensed under the MIT License\n\n--This receives unpacked 10bit pixel data from the unpacker and framing signals from the packet handler,\n--and writes it into a dual-port line buffer to cross it from the byte clock into the pixel clock domain\n--It also generates all the necessary video output signals\n\nentity csi_rx_video_output is\n generic(\n video_hlength : natural := 4046; --total visible and blanking pixels per line\n video_vlength : natural := 2190; --total visible and blanking lines per frame\n\n video_hsync_pol : boolean := true; --hsync polarity: true for positive sync, false for negative sync\n video_hsync_len : natural := 48; --horizontal sync length in pixels\n video_hbp_len : natural := 122; --horizontal back porch length (excluding sync)\n video_h_visible : natural := 3840; --number of visible pixels per line\n\n video_vsync_pol : boolean := true; --vsync polarity: true for positive sync, false for negative sync\n video_vsync_len : natural := 3; --vertical sync length in lines\n video_vbp_len : natural := 23; --vertical back porch length (excluding sync)\n video_v_visible : natural := 2160; --number of visible lines per frame\n\n pixels_per_clock : natural := 2 --Number of pixels per clock to output; 1, 2 or 4\n );\n port(\n output_clock : in std_logic; --Output pixel clock\n csi_byte_clock : in std_logic; --CSI byte clock\n\n enable : in std_logic; --system enable input\n reset : in std_logic; --synchronous active high reset input\n\n pixel_data_in : in std_logic_vector(39 downto 0); --Unpacked 10 bit data\n pixel_data_valid : in std_logic;\n\n csi_in_frame : in std_logic;\n csi_in_line : in std_logic;\n csi_vsync : in std_logic;\n\n video_valid : out std_logic; --goes high when valid frames are being received\n\n --Pixel data output\n video_hsync : out std_logic;\n video_vsync : out std_logic;\n video_den : out std_logic;\n video_line_start : out std_logic; --like hsync but asserted for one clock period only and only for visible lines\n video_odd_line : out std_logic; --LSB of y-coordinate for a downstream debayering block\n video_data : out std_logic_vector(((10 * pixels_per_clock) - 1) downto 0); --LSW is leftmost pixel\n video_prev_line_data : out std_logic_vector(((10 * pixels_per_clock) - 1) downto 0) --last line's data at this point, for a debayering block to use\n );\nend csi_rx_video_output;\n\narchitecture Behavioral of csi_rx_video_output is\n signal csi_in_line_last, csi_in_frame_last, csi_odd_line, csi_frame_started : std_logic := '0';\n signal video_fsync_pre, video_fsync : std_logic := '0';\n\n signal csi_x_pos : natural range 0 to video_h_visible - 1;\n\n constant output_width : natural := video_h_visible / pixels_per_clock;\n constant output_tmg_hlength : natural := video_hlength / pixels_per_clock;\n constant output_hvis_begin : natural := (video_hsync_len + video_hbp_len) / pixels_per_clock;\n\n signal output_timing_h : natural range 0 to output_tmg_hlength - 1;\n signal output_pixel_y : natural range 0 to video_v_visible - 1;\n\n signal linebuf_write_address : natural range 0 to video_h_visible / 4 - 1;\n signal linebuf_read_address : natural range 0 to output_width - 1;\n\n signal even_linebuf_wren, odd_linebuf_wren : std_logic := '0';\n signal even_linebuf_q, odd_linebuf_q : std_logic_vector(((10 * pixels_per_clock) - 1) downto 0);\n\n signal output_hsync, output_vsync, output_den, output_line_start, output_odd_line : std_logic;\n signal output_data, output_prev_line_data : std_logic_vector(((10 * pixels_per_clock) - 1) downto 0);\nbegin\n\n process(csi_byte_clock)\n begin\n if rising_edge(csi_byte_clock) then\n if reset = '1' then\n csi_in_line_last <= '0';\n csi_in_frame_last <= '0';\n csi_frame_started <= '0';\n csi_odd_line <= '1';\n elsif enable = '1' then\n\n csi_in_frame_last <= csi_in_frame;\n csi_in_line_last <= csi_in_line;\n\n if csi_in_frame_last = '0' and csi_in_frame = '1' then --Start of frame\n csi_x_pos <= 0;\n csi_odd_line <= '1';\n csi_frame_started <= '0';\n elsif csi_in_line_last = '0' and csi_in_line = '1' then --Start of line\n csi_x_pos <= 0;\n csi_odd_line <= not csi_odd_line;\n csi_frame_started <= '1';\n elsif pixel_data_valid = '1' then\n csi_x_pos <= csi_x_pos + 4;\n end if;\n\n end if;\n end if;\n end process;\n linebuf_write_address <= csi_x_pos / 4;\n even_linebuf_wren <= pixel_data_valid when csi_odd_line = '0' else '0';\n odd_linebuf_wren <= pixel_data_valid when csi_odd_line = '1' else '0';\n\n process(output_clock)\n begin\n if rising_edge(output_clock) then\n if reset = '1' then\n video_fsync_pre <= '0';\n video_fsync <= '0';\n elsif enable = '1' then\n video_fsync_pre <= csi_frame_started;\n video_fsync <= video_fsync_pre;\n\n --Register video output\n video_hsync <= output_hsync;\n video_vsync <= output_vsync;\n video_den <= output_den;\n video_line_start <= output_line_start;\n video_odd_line <= output_odd_line;\n video_data <= output_data;\n video_prev_line_data <= output_prev_line_data;\n end if;\n end if;\n end process;\n\n output_odd_line <= '1' when output_pixel_y mod 2 = 1 else '0';\n output_data <= odd_linebuf_q when output_odd_line = '1' else even_linebuf_q;\n output_prev_line_data <= even_linebuf_q when output_odd_line = '1' else odd_linebuf_q;\n linebuf_read_address <= (output_timing_h - (output_hvis_begin - 1)); -- the -1 accounts for the RAM read latency\n\n output_timing : entity work.video_timing_ctrl\n generic map(\n video_hlength => output_tmg_hlength,\n video_vlength => video_vlength,\n\n video_hsync_pol => video_hsync_pol,\n video_hsync_len => video_hsync_len / pixels_per_clock,\n video_hbp_len => video_hbp_len / pixels_per_clock,\n video_h_visible => video_h_visible / pixels_per_clock,\n\n video_vsync_pol => video_vsync_pol,\n video_vsync_len => video_vsync_len,\n video_vbp_len => video_vbp_len,\n video_v_visible => video_v_visible,\n\n sync_v_pos => (video_vbp_len + video_vsync_len - 1), --keep output 1 line behind input\n sync_h_pos => (output_tmg_hlength - 5)\n )\n port map(\n pixel_clock => output_clock,\n reset => reset,\n\n ext_sync => video_fsync,\n\n timing_h_pos => output_timing_h,\n timing_v_pos => open,\n pixel_x => open,\n pixel_y => output_pixel_y,\n\n video_vsync => output_vsync,\n video_hsync => output_hsync,\n video_den => output_den,\n video_line_start => output_line_start\n );\n\n\n even_linebuf : entity work.csi_rx_line_buffer\n generic map(\n line_width => video_h_visible,\n pixels_per_clock => pixels_per_clock\n )\n port map(\n write_clock => csi_byte_clock,\n write_addr => linebuf_write_address,\n write_data => pixel_data_in,\n write_en => even_linebuf_wren,\n\n read_clock => output_clock,\n read_addr => linebuf_read_address,\n read_q => even_linebuf_q\n );\n\n odd_linebuf : entity work.csi_rx_line_buffer\n generic map(\n line_width => video_h_visible,\n pixels_per_clock => pixels_per_clock\n )\n port map(\n write_clock => csi_byte_clock,\n write_addr => linebuf_write_address,\n write_data => pixel_data_in,\n write_en => odd_linebuf_wren,\n\n read_clock => output_clock,\n read_addr => linebuf_read_address,\n read_q => odd_linebuf_q\n );\n\n video_valid <= '1'; --not yet implemented\nend Behavioral;\n" }, { "path": "vhdl_rx/mipi-csi-rx/csi_rx_word_align.vhd", "content": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.STD_LOGIC_MISC.ALL;\n\n--MIPI CSI-2 word aligner\n--Copyright (C) 2016 David Shah\n--Licensed under the MIT License\n\n--This receives aligned bytes and status signals from the 4 byte aligners\n--and compensates for up to 2 clock cycles of skew between channels. It also\n--controls the packet_done input to the byte aligner, resetting byte aligners'\n--sync status if all 4 byte aligners fail to find the sync pattern\n\n--Similar to the byte aligner, this locks the alignment once a valid alignment\n--has been found until packet_done is asserted\n\nentity csi_rx_word_align is\n Port ( word_clock : in STD_LOGIC; --byte/word clock in\n reset : in STD_LOGIC; --active high synchronous reset\n enable : in STD_LOGIC; --active high enable\n packet_done : in STD_LOGIC; --packet done input from packet handler entity\n wait_for_sync : in STD_LOGIC; --whether or not to be looking for an alignment\n\t\t\t packet_done_out : out STD_LOGIC; --packet done output to byte aligners\n word_in : in STD_LOGIC_VECTOR (31 downto 0); --unaligned word from the 4 byte aligners\n valid_in : in STD_LOGIC_VECTOR (3 downto 0); --valid_out from the byte aligners (MSB is index 3, LSB index 0)\n word_out : out STD_LOGIC_VECTOR (31 downto 0); --aligned word out to packet handler\n valid_out : out STD_LOGIC); --goes high once alignment is valid, such that the first word with it high is the CSI packet header\nend csi_rx_word_align;\n\narchitecture Behavioral of csi_rx_word_align is\nsignal word_dly_0 : std_logic_vector(31 downto 0);\nsignal word_dly_1 : std_logic_vector(31 downto 0);\nsignal word_dly_2 : std_logic_vector(31 downto 0);\n\nsignal valid_dly_0 : std_logic_vector (3 downto 0);\nsignal valid_dly_1 : std_logic_vector (3 downto 0);\nsignal valid_dly_2 : std_logic_vector (3 downto 0);\n\ntype taps_t is array(0 to 3) of std_logic_vector(1 downto 0);\n\nsignal taps : taps_t;\nsignal next_taps : taps_t;\n\nsignal valid : std_logic := '0';\nsignal next_valid : std_logic;\nsignal invalid_start : std_logic := '0';\nsignal aligned_word : std_logic_vector(31 downto 0);\n\nbegin\n process(word_clock)\n begin\n if rising_edge(word_clock) then\n if reset = '1' then\n valid <= '0';\n taps <= (\"00\", \"00\", \"00\", \"00\");\n elsif enable = '1' then\n word_dly_0 <= word_in;\n valid_dly_0 <= valid_in;\n word_dly_1 <= word_dly_0;\n valid_dly_1 <= valid_dly_0;\n word_dly_2 <= word_dly_1;\n valid_dly_2 <= valid_dly_1;\n valid_out <= valid;\n word_out <= aligned_word;\n if next_valid = '1' and valid = '0' and wait_for_sync = '1' then\n valid <= '1';\n taps <= next_taps;\n elsif packet_done = '1' then\n valid <= '0';\n end if;\n end if;\n end if;\n end process;\n\n process(valid_dly_0, valid_dly_1, valid_dly_2)\n variable next_valid_int : std_logic;\n variable is_triggered : std_logic := '0';\n\t begin\n next_valid_int := and_reduce(valid_dly_0);\n\t\t --Reset if all channels fail to sync\n\t\t is_triggered := '0';\n\t\t for i in 0 to 3 loop\n\t\t\tif valid_dly_0(i) = '1' and valid_dly_1(i) = '1' and valid_dly_2(i) = '1' then\n\t\t\t\tis_triggered := '1';\n\t\t\tend if;\n\t\t end loop;\n\t\t invalid_start <= (not next_valid_int) and is_triggered;\n\t\t next_valid <= next_valid_int;\n for i in 0 to 3 loop\n if valid_dly_2(i) = '1' then\n next_taps(i) <= \"10\";\n elsif valid_dly_1(i) = '1' then\n next_taps(i) <= \"01\";\n else\n next_taps(i) <= \"00\";\n end if;\n end loop;\n end process;\n\n\t packet_done_out <= packet_done or invalid_start;\n\n process(word_dly_0, word_dly_1, word_dly_2, taps)\n begin\n for i in 0 to 3 loop\n if taps(i) = \"10\" then\n aligned_word((8*i) + 7 downto 8 * i) <= word_dly_2((8*i) + 7 downto 8 * i);\n elsif taps(i) = \"01\" then\n aligned_word((8*i) + 7 downto 8 * i) <= word_dly_1((8*i) + 7 downto 8 * i);\n else\n aligned_word((8*i) + 7 downto 8 * i) <= word_dly_0((8*i) + 7 downto 8 * i);\n end if;\n end loop;\n end process;\nend Behavioral;\n" }, { "path": "vhdl_rx/mipi-csi-rx/synth.ys", "content": "read -vhdl csi_rx_hdr_ecc.vhd csi_rx_packet_handler.vhd csi_rx_10bit_unpack.vhd csi_rx_video_output.vhd csi_rx_line_buffer.vhd\n" }, { "path": "vhdl_rx/ov-cam-control/manual_focus.vhd", "content": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.NUMERIC_STD.ALL;\n\n--Manual focus controller\n--Copyright (C) 2016 David Shah\n--Licensed under the MIT License\n\n--This reads two buttons and outputs a current value for the focus voice\n--coil driver\n\nentity manual_focus is\n Port ( clock : in STD_LOGIC;\n enable : in STD_LOGIC;\n reset : in STD_LOGIC;\n i2c_start : out STD_LOGIC;\n vcm_value : out STD_LOGIC_VECTOR (9 downto 0);\n btn_inc : in STD_LOGIC;\n btn_dec : in STD_LOGIC);\nend manual_focus;\n\narchitecture Behavioral of manual_focus is\nsignal int_focus_value : unsigned(22 downto 0);\nsignal last_focus_value : unsigned(9 downto 0);\nsignal out_focus_value : std_logic_vector(9 downto 0);\nsignal i2c_wait_ctr : unsigned(8 downto 0);\nbegin\n\n\tprocess(reset, clock)\n\tbegin\n\t\tif reset = '1' then\n\t\t\tint_focus_value <= (others => '0');\n\t\t\tlast_focus_value <= (others => '0');\n\t\t\tout_focus_value <= (others => '0');\n\t\t\ti2c_wait_ctr <= (others => '0');\n\t\telsif rising_edge(clock) then\n\t\t\tif enable = '1' then\n\n\t\t\t\t--User side\n\t\t\t\tif btn_inc = '1' then\n\t\t\t\t\tif int_focus_value < 8388607 then\n\t\t\t\t\t\tint_focus_value <= int_focus_value + 1;\n\t\t\t\t\tend if;\n\t\t\t\telsif btn_dec = '1' then\n\t\t\t\t\tif int_focus_value > 0 then\n\t\t\t\t\t\tint_focus_value <= int_focus_value - 1;\n\t\t\t\t\tend if;\n\t\t\t\tend if;\n\n\t\t\t\t--I2C side\n\t\t\t\tif i2c_wait_ctr = 0 then\n\t\t\t\t\tif int_focus_value(22 downto 13) /= last_focus_value then\n\t\t\t\t\t\tout_focus_value <= std_logic_vector(int_focus_value(22 downto 13));\n\t\t\t\t\t\tlast_focus_value <= int_focus_value(22 downto 13);\n\t\t\t\t\t\ti2c_start <= '1';\n\t\t\t\t\telse\n\t\t\t\t\t\ti2c_start <= '0';\n\t\t\t\t\tend if;\n\t\t\t\telse\n\t\t\t\t\ti2c_start <= '0';\n\t\t\t\tend if;\n\n\t\t\t\ti2c_wait_ctr <= i2c_wait_ctr + 1;\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n\tvcm_value <= out_focus_value;\nend Behavioral;\n" }, { "path": "vhdl_rx/ov-cam-control/ov13850_4k_regs.vhd", "content": "library ieee ;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\n--OV13850 Camera Configuration\n\n--This configuration is for 4k24/4k30, 10-bit, 4-lane with a total horizontal length of 6800 pixels\n--and a total vertical length of 2992 lines\n\nentity ov13850_4k_regs is\nport (clock : in std_logic; --this allows a blockram to be elaborated\n \t\taddress : in std_logic_vector(8 downto 0);\n \t\t--This is the I2C data to be written\n \t\t--2 MSBs are address, 1 MSB is data\n \t\tdata : out std_logic_vector(23 downto 0));\nend ov13850_4k_regs;\n\narchitecture behv_cd of ov13850_4k_regs is\nbegin\n\tprocess(clock)\n\tbegin\n\t\tif rising_edge(clock) then\n\t\t\tcase address(8 downto 0) is\n\t\t\t\t\t\twhen \"0\" & x\"00\" =>\n\t\t\t\t\t\t\tdata <= x\"010301\"; --software reset\n\t when \"0\" & x\"01\" =>\n\t\t\t\t data <= x\"030a00\";\n\t when \"0\" & x\"02\" =>\n\t\t\t data <= x\"300f11\"; --MIPI 10 bit mode\n\t when \"0\" & x\"03\" =>\n\t\t\t\t data <= x\"301003\"; --MIPI PHY\n\t when \"0\" & x\"04\" =>\n\t\t\t\t data <= x\"301176\"; --MIPI PHY\n\t\t\t\t\t\twhen \"0\" & x\"05\" =>\n\t\t\t\t data <= x\"301241\"; --MIPI 4 lane\n\t\t\t\t\t\twhen \"0\" & x\"06\" =>\n\t\t\t\t\t\t\tdata <= x\"301312\";\n\t\t\t\t\t\twhen \"0\" & x\"07\" =>\n\t\t\t\t\t\t\tdata <= x\"301411\";\n\t\t\t\t\t\twhen \"0\" & x\"08\" =>\n\t\t\t\t\t\t\tdata <= x\"301f03\";\n\t\t\t\t\t\twhen \"0\" & x\"09\" =>\n\t\t\t\t\t\t\tdata <= x\"310600\";\n\t\t\t\t\t\twhen \"0\" & x\"0a\" =>\n\t\t\t\t\t\t\tdata <= x\"321047\";\n\t\t\t\t\t\twhen \"0\" & x\"0b\" =>\n\t\t\t\t\t\t\tdata <= x\"350000\";\n\t\t\t\t\t\twhen \"0\" & x\"0c\" =>\n\t\t\t\t\t\t\tdata <= x\"3501b0\";\n\t\t\t\t\t\twhen \"0\" & x\"0d\" =>\n\t\t\t\t\t\t\tdata <= x\"350200\";\n\t\t\t\t\t\twhen \"0\" & x\"0e\" =>\n\t\t\t\t\t\t\tdata <= x\"350600\";\n\t\t\t\t\t\twhen \"0\" & x\"0f\" =>\n\t\t\t\t\t\t\tdata <= x\"35070a\";\n\t\t\t\t\t\twhen \"0\" & x\"10\" =>\n\t\t\t\t\t\t\tdata <= x\"350800\";\n\t\t\t\t\t\twhen \"0\" & x\"11\" =>\n\t\t\t\t\t\t\tdata <= x\"350910\";\n\t\t\t\t\t\twhen \"0\" & x\"12\" =>\n\t\t\t\t\t\t\tdata <= x\"350a00\";\n\t\t\t\t\t\twhen \"0\" & x\"13\" =>\n\t\t\t\t\t\t\tdata <= x\"350ba0\";\n\t\t\t\t\t\twhen \"0\" & x\"14\" =>\n\t\t\t\t\t\t\tdata <= x\"350e00\";\n\t\t\t\t\t\twhen \"0\" & x\"15\" =>\n\t\t\t\t\t\t\tdata <= x\"350fa0\";\n\t\t\t\t\t\twhen \"0\" & x\"16\" =>\n\t\t\t\t\t\t\tdata <= x\"360040\";\n\t\t\t\t\t\twhen \"0\" & x\"17\" =>\n\t\t\t\t\t\t\tdata <= x\"3601fc\";\n\t\t\t\t\t\twhen \"0\" & x\"18\" =>\n\t\t\t\t\t\t\tdata <= x\"360202\";\n\t\t\t\t\t\twhen \"0\" & x\"19\" =>\n\t\t\t\t\t\t\tdata <= x\"360348\";\n\t\t\t\t\t\twhen \"0\" & x\"1a\" =>\n\t\t\t\t\t\t\tdata <= x\"3604a5\";\n\t\t\t\t\t\twhen \"0\" & x\"1b\" =>\n\t\t\t\t\t\t\tdata <= x\"36059f\";\n\t\t\t\t\t\twhen \"0\" & x\"1c\" =>\n\t\t\t\t\t\t\tdata <= x\"360700\";\n\t\t\t\t\t\twhen \"0\" & x\"1d\" =>\n\t\t\t\t\t\t\tdata <= x\"360a40\";\n\t\t\t\t\t\twhen \"0\" & x\"1e\" =>\n\t\t\t\t\t\t\tdata <= x\"360b91\";\n\t\t\t\t\t\twhen \"0\" & x\"1f\" =>\n\t\t\t\t\t\t\tdata <= x\"360c49\";\n\t\t\t\t\t\twhen \"0\" & x\"20\" =>\n\t\t\t\t\t\t\tdata <= x\"360f8a\";\n\t\t\t\t\t\twhen \"0\" & x\"21\" =>\n\t\t\t\t\t\t\tdata <= x\"361110\";\n\t\t\t\t\t\twhen \"0\" & x\"22\" =>\n\t\t\t\t\t\t\tdata <= x\"361311\";\n\t\t\t\t\t\t--wait\n\t\t\t\t\t\twhen \"0\" & x\"30\" =>\n\t\t\t\t\t\t\tdata <= x\"361508\";\n\t\t\t\t\t\twhen \"0\" & x\"31\" =>\n\t\t\t\t\t\t\tdata <= x\"364102\";\n\t\t\t\t\t\twhen \"0\" & x\"32\" =>\n\t\t\t\t\t\t\tdata <= x\"366082\";\n\t\t\t\t\t\twhen \"0\" & x\"33\" =>\n\t\t\t\t\t\t\tdata <= x\"366854\";\n\t\t\t\t\t\twhen \"0\" & x\"34\" =>\n\t\t\t\t\t\t\tdata <= x\"366940\";\n\t\t\t\t\t\twhen \"0\" & x\"35\" =>\n\t\t\t\t\t\t\tdata <= x\"3667a0\";\n\t\t\t\t\t\twhen \"0\" & x\"36\" =>\n\t\t\t\t\t\t\tdata <= x\"370240\";\n\t\t\t\t\t\twhen \"0\" & x\"37\" =>\n\t\t\t\t\t\t\tdata <= x\"370344\";\n\t\t\t\t\t\twhen \"0\" & x\"38\" =>\n\t\t\t\t\t\t\tdata <= x\"37042c\";\n\t\t\t\t\t\twhen \"0\" & x\"39\" =>\n\t\t\t\t\t\t\tdata <= x\"370524\";\n\t\t\t\t\t\twhen \"0\" & x\"3a\" =>\n\t\t\t\t\t\t\tdata <= x\"370650\";\n\t\t\t\t\t\twhen \"0\" & x\"3b\" =>\n\t\t\t\t\t\t\tdata <= x\"370744\";\n\t\t\t\t\t\twhen \"0\" & x\"3c\" =>\n\t\t\t\t\t\t\tdata <= x\"37083c\";\n\t\t\t\t\t\twhen \"0\" & x\"3d\" =>\n\t\t\t\t\t\t\tdata <= x\"37091f\";\n\t\t\t\t\t\twhen \"0\" & x\"3e\" =>\n\t\t\t\t\t\t\tdata <= x\"370a26\";\n\t\t\t\t\t\twhen \"0\" & x\"3f\" =>\n\t\t\t\t\t\t\tdata <= x\"370b3c\";\n\t\t\t\t\t\twhen \"0\" & x\"40\" =>\n\t\t\t\t\t\t\tdata <= x\"372066\";\n\t\t\t\t\t\twhen \"0\" & x\"41\" =>\n\t\t\t\t\t\t\tdata <= x\"372284\";\n\t\t\t\t\t\twhen \"0\" & x\"42\" =>\n\t\t\t\t\t\t\tdata <= x\"372840\";\n\t\t\t\t\t\twhen \"0\" & x\"43\" =>\n\t\t\t\t\t\t\tdata <= x\"372a00\";\n\t\t\t\t\t\twhen \"0\" & x\"44\" =>\n\t\t\t\t\t\t\tdata <= x\"372f90\";\n\t\t\t\t\t\twhen \"0\" & x\"45\" =>\n\t\t\t\t\t\t\tdata <= x\"371028\";\n\t\t\t\t\t\twhen \"0\" & x\"46\" =>\n\t\t\t\t\t\t\tdata <= x\"371603\";\n\t\t\t\t\t\twhen \"0\" & x\"47\" =>\n\t\t\t\t\t\t\tdata <= x\"371810\";\n\t\t\t\t\t\twhen \"0\" & x\"48\" =>\n\t\t\t\t\t\t\tdata <= x\"371908\";\n\t\t\t\t\t\twhen \"0\" & x\"49\" =>\n\t\t\t\t\t\t\tdata <= x\"371cfc\";\n\t\t\t\t\t\twhen \"0\" & x\"4a\" =>\n\t\t\t\t\t\t\tdata <= x\"376013\";\n\t\t\t\t\t\twhen \"0\" & x\"4b\" =>\n\t\t\t\t\t\t\tdata <= x\"376134\";\n\t\t\t\t\t\twhen \"0\" & x\"4c\" =>\n\t\t\t\t\t\t\tdata <= x\"376724\";\n\t\t\t\t\t\twhen \"0\" & x\"4d\" =>\n\t\t\t\t\t\t\tdata <= x\"376806\";\n\t\t\t\t\t\twhen \"0\" & x\"4e\" =>\n\t\t\t\t\t\t\tdata <= x\"376945\";\n\t\t\t\t\t\twhen \"0\" & x\"4f\" =>\n\t\t\t\t\t\t\tdata <= x\"376c23\";\n\t\t\t\t\t\twhen \"0\" & x\"50\" =>\n\t\t\t\t\t\t\tdata <= x\"3d8400\";\n\t\t\t\t\t\twhen \"0\" & x\"51\" =>\n\t\t\t\t\t\t\tdata <= x\"3d8517\";\n\t\t\t\t\t\twhen \"0\" & x\"52\" =>\n\t\t\t\t\t\t\tdata <= x\"3d8c73\";\n\t\t\t\t\t\twhen \"0\" & x\"53\" =>\n\t\t\t\t\t\t\tdata <= x\"3d8dbf\";\n\t\t\t\t\t\twhen \"0\" & x\"54\" =>\n\t\t\t\t\t\t\tdata <= x\"380000\";\n\t\t\t\t\t\twhen \"0\" & x\"55\" =>\n\t\t\t\t\t\t\tdata <= x\"380108\";\n\t\t\t\t\t\twhen \"0\" & x\"56\" =>\n\t\t\t\t\t\t\tdata <= x\"380200\";\n\t\t\t\t\t\twhen \"0\" & x\"57\" =>\n\t\t\t\t\t\t\tdata <= x\"380304\";\n\t\t\t\t\t\twhen \"0\" & x\"58\" =>\n\t\t\t\t\t\t\tdata <= x\"380410\";\n\t\t\t\t\t\twhen \"0\" & x\"59\" =>\n\t\t\t\t\t\t\tdata <= x\"380597\";\n\t\t\t\t\t\twhen \"0\" & x\"5a\" =>\n\t\t\t\t\t\t\tdata <= x\"38060c\";\n\t\t\t\t\t\twhen \"0\" & x\"5b\" =>\n\t\t\t\t\t\t\tdata <= x\"38074b\";\n\t\t\t\t\t\twhen \"0\" & x\"5c\" =>\n\t\t\t\t\t\t\tdata <= x\"380808\";\n\t\t\t\t\t\twhen \"0\" & x\"5d\" =>\n\t\t\t\t\t\t\tdata <= x\"380940\";\n\t\t\t\t\t\twhen \"0\" & x\"5e\" =>\n\t\t\t\t\t\t\tdata <= x\"380a06\";\n\t\t\t\t\t\twhen \"0\" & x\"5f\" =>\n\t\t\t\t\t\t\tdata <= x\"380b20\";\n\t\t\t\t\t\twhen \"0\" & x\"60\" =>\n\t\t\t\t\t\t\tdata <= x\"380c25\";\n\t\t\t\t\t\twhen \"0\" & x\"61\" =>\n\t\t\t\t\t\t\tdata <= x\"380d80\";\n\t\t\t\t\t\twhen \"0\" & x\"62\" =>\n\t\t\t\t\t\t\tdata <= x\"380e06\";\n\t\t\t\t\t\twhen \"0\" & x\"63\" =>\n\t\t\t\t\t\t\tdata <= x\"380f80\";\n\t\t\t\t\t\twhen \"0\" & x\"64\" =>\n\t\t\t\t\t\t\tdata <= x\"381000\";\n\t\t\t\t\t\twhen \"0\" & x\"65\" =>\n\t\t\t\t\t\t\tdata <= x\"381104\";\n\t\t\t\t\t\twhen \"0\" & x\"66\" =>\n\t\t\t\t\t\t\tdata <= x\"381200\";\n\t\t\t\t\t\twhen \"0\" & x\"67\" =>\n\t\t\t\t\t\t\tdata <= x\"381302\";\n\t\t\t\t\t\twhen \"0\" & x\"68\" =>\n\t\t\t\t\t\t\tdata <= x\"381431\";\n\t\t\t\t\t\twhen \"0\" & x\"69\" =>\n\t\t\t\t\t\t\tdata <= x\"381531\";\n\t\t\t\t\t\twhen \"0\" & x\"6a\" =>\n\t\t\t\t\t\t\tdata <= x\"382002\";\n\t\t\t\t\t\twhen \"0\" & x\"6b\" =>\n\t\t\t\t\t\t\tdata <= x\"382105\"; --mirror off\n\t\t\t\t\t\twhen \"0\" & x\"6c\" =>\n\t\t\t\t\t\t\tdata <= x\"383400\";\n\t\t\t\t\t\twhen \"0\" & x\"6d\" =>\n\t\t\t\t\t\t\tdata <= x\"38351c\";\n\t\t\t\t\t\twhen \"0\" & x\"6e\" =>\n\t\t\t\t\t\t\tdata <= x\"383608\";\n\t\t\t\t\t\twhen \"0\" & x\"6f\" =>\n\t\t\t\t\t\t\tdata <= x\"383702\";\n\t\t\t\t\t\twhen \"0\" & x\"70\" =>\n\t\t\t\t\t\t\tdata <= x\"4000f1\";\n\t\t\t\t\t\twhen \"0\" & x\"71\" =>\n\t\t\t\t\t\t\tdata <= x\"400100\";\n\t\t\t\t\t\twhen \"0\" & x\"72\" =>\n\t\t\t\t\t\t\tdata <= x\"400b0c\";\n\t\t\t\t\t\twhen \"0\" & x\"73\" =>\n\t\t\t\t\t\t\tdata <= x\"401100\";\n\t\t\t\t\t\twhen \"0\" & x\"74\" =>\n\t\t\t\t\t\t\tdata <= x\"401a00\";\n\t\t\t\t\t\twhen \"0\" & x\"75\" =>\n\t\t\t\t\t\t\tdata <= x\"401b00\";\n\t\t\t\t\t\twhen \"0\" & x\"76\" =>\n\t\t\t\t\t\t\tdata <= x\"401c00\";\n\t\t\t\t\t\twhen \"0\" & x\"77\" =>\n\t\t\t\t\t\t\tdata <= x\"401d00\";\n\t\t\t\t\t\twhen \"0\" & x\"78\" =>\n\t\t\t\t\t\t\tdata <= x\"402000\";\n\t\t\t\t\t\twhen \"0\" & x\"79\" =>\n\t\t\t\t\t\t\tdata <= x\"4021e4\";\n\t\t\t\t\t\twhen \"0\" & x\"7a\" =>\n\t\t\t\t\t\t\tdata <= x\"402207\";\n\t\t\t\t\t\twhen \"0\" & x\"7b\" =>\n\t\t\t\t\t\t\tdata <= x\"40235f\";\n\t\t\t\t\t\twhen \"0\" & x\"7c\" =>\n\t\t\t\t\t\t\tdata <= x\"402408\";\n\t\t\t\t\t\twhen \"0\" & x\"7d\" =>\n\t\t\t\t\t\t\tdata <= x\"402544\";\n\t\t\t\t\t\twhen \"0\" & x\"7e\" =>\n\t\t\t\t\t\t\tdata <= x\"402608\";\n\t\t\t\t\t\twhen \"0\" & x\"7f\" =>\n\t\t\t\t\t\t\tdata <= x\"402747\";\n\t\t\t\t\t\twhen \"0\" & x\"80\" =>\n\t\t\t\t\t\t\tdata <= x\"402800\";\n\t\t\t\t\t\twhen \"0\" & x\"81\" =>\n\t\t\t\t\t\t\tdata <= x\"402902\";\n\t\t\t\t\t\twhen \"0\" & x\"82\" =>\n\t\t\t\t\t\t\tdata <= x\"402a04\";\n\t\t\t\t\t\twhen \"0\" & x\"83\" =>\n\t\t\t\t\t\t\tdata <= x\"402b08\";\n\t\t\t\t\t\twhen \"0\" & x\"84\" =>\n\t\t\t\t\t\t\tdata <= x\"402c02\";\n\t\t\t\t\t\twhen \"0\" & x\"85\" =>\n\t\t\t\t\t\t\tdata <= x\"402d02\";\n\t\t\t\t\t\twhen \"0\" & x\"86\" =>\n\t\t\t\t\t\t\tdata <= x\"402e0c\";\n\t\t\t\t\t\twhen \"0\" & x\"87\" =>\n\t\t\t\t\t\t\tdata <= x\"402f08\";\n\t\t\t\t\t\twhen \"0\" & x\"88\" =>\n\t\t\t\t\t\t\tdata <= x\"403d2c\";\n\t\t\t\t\t\twhen \"0\" & x\"89\" =>\n\t\t\t\t\t\t\tdata <= x\"403f7f\";\n\t\t\t\t\t\twhen \"0\" & x\"8a\" =>\n\t\t\t\t\t\t\tdata <= x\"450082\";\n\t\t\t\t\t\twhen \"0\" & x\"8b\" =>\n\t\t\t\t\t\t\tdata <= x\"450138\";\n\t\t\t\t\t\twhen \"0\" & x\"8c\" =>\n\t\t\t\t\t\t\tdata <= x\"460104\";\n\t\t\t\t\t\twhen \"0\" & x\"8d\" =>\n\t\t\t\t\t\t\tdata <= x\"460222\";\n\t\t\t\t\t\twhen \"0\" & x\"8e\" =>\n\t\t\t\t\t\t\tdata <= x\"460301\";\n\t\t\t\t\t\twhen \"0\" & x\"8f\" =>\n\t\t\t\t\t\t\tdata <= x\"483719\";\n\t\t\t\t\t\twhen \"0\" & x\"90\" =>\n\t\t\t\t\t\t\tdata <= x\"480004\";\n\t\t\t\t\t\twhen \"0\" & x\"91\" =>\n\t\t\t\t\t\t\tdata <= x\"480242\";\n\t\t\t\t\t\twhen \"0\" & x\"92\" =>\n\t\t\t\t\t\t\tdata <= x\"481a00\";\n\t\t\t\t\t\twhen \"0\" & x\"93\" =>\n\t\t\t\t\t\t\tdata <= x\"481b1c\";\n\t\t\t\t\t\twhen \"0\" & x\"94\" =>\n\t\t\t\t\t\t\tdata <= x\"482612\";\n\t\t\t\t\t\twhen \"0\" & x\"95\" =>\n\t\t\t\t\t\t\tdata <= x\"4d0004\";\n\t\t\t\t\t\twhen \"0\" & x\"96\" =>\n\t\t\t\t\t\t\tdata <= x\"4d0142\";\n\t\t\t\t\t\twhen \"0\" & x\"97\" =>\n\t\t\t\t\t\t\tdata <= x\"4d02d1\";\n\t\t\t\t\t\twhen \"0\" & x\"98\" =>\n\t\t\t\t\t\t\tdata <= x\"4d0390\";\n\t\t\t\t\t\twhen \"0\" & x\"99\" =>\n\t\t\t\t\t\t\tdata <= x\"4d0466\";\n\t\t\t\t\t\twhen \"0\" & x\"9a\" =>\n\t\t\t\t\t\t\tdata <= x\"4d0565\";\n\t\t\t\t\t\twhen \"0\" & x\"9b\" =>\n\t\t\t\t\t\t\tdata <= x\"50000e\";\n\t\t\t\t\t\twhen \"0\" & x\"9c\" =>\n\t\t\t\t\t\t\tdata <= x\"500103\";\n\t\t\t\t\t\twhen \"0\" & x\"9d\" =>\n\t\t\t\t\t\t\tdata <= x\"500207\";\n\t\t\t\t\t\twhen \"0\" & x\"9e\" =>\n\t\t\t\t\t\t\tdata <= x\"501340\";\n\t\t\t\t\t\twhen \"0\" & x\"9f\" =>\n\t\t\t\t\t\t\tdata <= x\"501c00\";\n\t\t\t\t\t\twhen \"0\" & x\"a0\" =>\n\t\t\t\t\t\t\tdata <= x\"501d10\";\n\t\t\t\t\t\twhen \"0\" & x\"a1\" =>\n\t\t\t\t\t\t\tdata <= x\"524200\";\n\t\t\t\t\t\twhen \"0\" & x\"a2\" =>\n\t\t\t\t\t\t\tdata <= x\"5243b8\";\n\t\t\t\t\t\twhen \"0\" & x\"a3\" =>\n\t\t\t\t\t\t\tdata <= x\"524400\";\n\t\t\t\t\t\twhen \"0\" & x\"a4\" =>\n\t\t\t\t\t\t\tdata <= x\"5245f9\";\n\t\t\t\t\t\twhen \"0\" & x\"a5\" =>\n\t\t\t\t\t\t\tdata <= x\"524600\";\n\t\t\t\t\t\twhen \"0\" & x\"a6\" =>\n\t\t\t\t\t\t\tdata <= x\"5247f6\";\n\t\t\t\t\t\twhen \"0\" & x\"a7\" =>\n\t\t\t\t\t\t\tdata <= x\"524800\";\n\t\t\t\t\t\twhen \"0\" & x\"a8\" =>\n\t\t\t\t\t\t\tdata <= x\"5249a6\";\n\t\t\t\t\t\twhen \"0\" & x\"a9\" =>\n\t\t\t\t\t\t\tdata <= x\"5300fc\";\n\t\t\t\t\t\twhen \"0\" & x\"aa\" =>\n\t\t\t\t\t\t\tdata <= x\"5301df\";\n\t\t\t\t\t\twhen \"0\" & x\"ab\" =>\n\t\t\t\t\t\t\tdata <= x\"53023f\";\n\t\t\t\t\t\twhen \"0\" & x\"ac\" =>\n\t\t\t\t\t\t\tdata <= x\"530308\";\n\t\t\t\t\t\twhen \"0\" & x\"ad\" =>\n\t\t\t\t\t\t\tdata <= x\"53040c\";\n\t\t\t\t\t\twhen \"0\" & x\"ae\" =>\n\t\t\t\t\t\t\tdata <= x\"530510\";\n\t\t\t\t\t\twhen \"0\" & x\"af\" =>\n\t\t\t\t\t\t\tdata <= x\"530620\";\n\t\t\t\t\t\twhen \"0\" & x\"b0\" =>\n\t\t\t\t\t\t\tdata <= x\"530740\";\n\t\t\t\t\t\twhen \"0\" & x\"b1\" =>\n\t\t\t\t\t\t\tdata <= x\"530808\";\n\t\t\t\t\t\twhen \"0\" & x\"b2\" =>\n\t\t\t\t\t\t\tdata <= x\"530908\";\n\t\t\t\t\t\twhen \"0\" & x\"b3\" =>\n\t\t\t\t\t\t\tdata <= x\"530a02\";\n\t\t\t\t\t\twhen \"0\" & x\"b4\" =>\n\t\t\t\t\t\t\tdata <= x\"530b01\";\n\t\t\t\t\t\twhen \"0\" & x\"b5\" =>\n\t\t\t\t\t\t\tdata <= x\"530c01\";\n\t\t\t\t\t\twhen \"0\" & x\"b6\" =>\n\t\t\t\t\t\t\tdata <= x\"530d0c\";\n\t\t\t\t\t\twhen \"0\" & x\"b7\" =>\n\t\t\t\t\t\t\tdata <= x\"530e02\";\n\t\t\t\t\t\twhen \"0\" & x\"b8\" =>\n\t\t\t\t\t\t\tdata <= x\"530f01\";\n\t\t\t\t\t\twhen \"0\" & x\"b9\" =>\n\t\t\t\t\t\t\tdata <= x\"531001\";\n\t\t\t\t\t\twhen \"0\" & x\"ba\" =>\n\t\t\t\t\t\t\tdata <= x\"540000\";\n\t\t\t\t\t\twhen \"0\" & x\"bb\" =>\n\t\t\t\t\t\t\tdata <= x\"540161\";\n\t\t\t\t\t\twhen \"0\" & x\"bc\" =>\n\t\t\t\t\t\t\tdata <= x\"540200\";\n\t\t\t\t\t\twhen \"0\" & x\"bd\" =>\n\t\t\t\t\t\t\tdata <= x\"540300\";\n\t\t\t\t\t\twhen \"0\" & x\"be\" =>\n\t\t\t\t\t\t\tdata <= x\"540400\";\n\t\t\t\t\t\twhen \"0\" & x\"bf\" =>\n\t\t\t\t\t\t\tdata <= x\"540540\";\n\t\t\t\t\t\twhen \"0\" & x\"c0\" =>\n\t\t\t\t\t\t\tdata <= x\"540c05\";\n\t\t\t\t\t\twhen \"0\" & x\"c1\" =>\n\t\t\t\t\t\t\tdata <= x\"5b0000\";\n\t\t\t\t\t\twhen \"0\" & x\"c2\" =>\n\t\t\t\t\t\t\tdata <= x\"5b0100\";\n\t\t\t\t\t\twhen \"0\" & x\"c3\" =>\n\t\t\t\t\t\t\tdata <= x\"5b0201\";\n\t\t\t\t\t\twhen \"0\" & x\"c4\" =>\n\t\t\t\t\t\t\tdata <= x\"5b03ff\";\n\t\t\t\t\t\twhen \"0\" & x\"c5\" =>\n\t\t\t\t\t\t\tdata <= x\"5b0402\";\n\t\t\t\t\t\twhen \"0\" & x\"c6\" =>\n\t\t\t\t\t\t\tdata <= x\"5b056c\";\n\t\t\t\t\t\twhen \"0\" & x\"c7\" =>\n\t\t\t\t\t\t\tdata <= x\"5b0902\";\n\t\t\t\t\t\twhen \"0\" & x\"c8\" =>\n\t\t\t\t\t\t\tdata <= x\"5e0000\"; --test pattern off\n\t\t\t\t\t\twhen \"0\" & x\"c9\" =>\n\t\t\t\t\t\t\tdata <= x\"5e101c\";\n\t\t\t\t\t\twhen \"0\" & x\"ca\" =>\n\t\t\t\t\t\t\tdata <= x\"381304\";\n\t\t\t\t\t\twhen \"0\" & x\"cb\" =>\n\t\t\t\t\t\t\tdata <= x\"381411\";\n\t\t\t\t\t\twhen \"0\" & x\"cc\" =>\n\t\t\t\t\t\t\tdata <= x\"381511\";\n\t\t\t\t\t\twhen \"0\" & x\"cd\" =>\n\t\t\t\t\t\t\tdata <= x\"382004\";\n\t\t\t\t\t\twhen \"0\" & x\"ce\" =>\n\t\t\t\t\t\t\tdata <= x\"382104\"; --mirror off\n\t\t\t\t\t\twhen \"0\" & x\"cf\" =>\n\t\t\t\t\t\t\tdata <= x\"383604\";\n\t\t\t\t\t\twhen \"0\" & x\"d0\" =>\n\t\t\t\t\t\t\tdata <= x\"383701\";\n\t\t\t\t\t\twhen \"0\" & x\"d1\" =>\n\t\t\t\t\t\t\tdata <= x\"48370a\";\n\t\t\t\t\t\twhen \"0\" & x\"d2\" =>\n\t\t\t\t\t\t\tdata <= x\"482612\";\n\t\t\t\t\t\twhen \"0\" & x\"d3\" =>\n\t\t\t\t\t\t\tdata <= x\"540171\";\n\t\t\t\t\t\twhen \"0\" & x\"d4\" =>\n\t\t\t\t\t\t\tdata <= x\"540580\";\n\t\t\t\t\t\twhen \"0\" & x\"d5\" =>\n\t\t\t\t\t\t\tdata <= x\"361207\";\n\t\t\t\t\t\twhen \"0\" & x\"d6\" =>\n\t\t\t\t\t\t\tdata <= x\"030000\";\n\t\t\t\t\t\twhen \"0\" & x\"d7\" =>\n\t\t\t\t\t\t\tdata <= x\"030100\";\n\t\t\t\t\t\twhen \"0\" & x\"d8\" =>\n\t\t\t\t\t\t\tdata <= x\"030220\";\n\t\t\t\t\t\twhen \"0\" & x\"d9\" =>\n\t\t\t\t\t\t\tdata <= x\"030300\";\n\t\t\t\t\t\twhen \"0\" & x\"e0\" =>\n\t\t\t\t\t\t\tdata <= x\"48370d\";\n\t\t\t\t\t\twhen \"0\" & x\"e1\" =>\n\t\t\t\t\t\t\tdata <= x\"370a24\";\n\t\t\t\t\t\twhen \"0\" & x\"e2\" =>\n\t\t\t\t\t\t\tdata <= x\"372a04\";\n\t\t\t\t\t\twhen \"0\" & x\"e3\" =>\n\t\t\t\t\t\t\tdata <= x\"372fa0\";\n\t\t\t\t\t\twhen \"0\" & x\"e4\" =>\n\t\t\t\t\t\t\tdata <= x\"380001\";\n\t\t\t\t\t\twhen \"0\" & x\"e5\" =>\n\t\t\t\t\t\t\tdata <= x\"38014c\";\n\t\t\t\t\t\twhen \"0\" & x\"e6\" =>\n\t\t\t\t\t\t\tdata <= x\"380202\";\n\t\t\t\t\t\twhen \"0\" & x\"e7\" =>\n\t\t\t\t\t\t\tdata <= x\"38038c\";\n\t\t\t\t\t\twhen \"0\" & x\"e8\" =>\n\t\t\t\t\t\t\tdata <= x\"380410\";\n\t\t\t\t\t\twhen \"0\" & x\"e9\" =>\n\t\t\t\t\t\t\tdata <= x\"380553\";\n\t\t\t\t\t\twhen \"0\" & x\"f0\" =>\n\t\t\t\t\t\t\tdata <= x\"38060b\";\n\t\t\t\t\t\twhen \"0\" & x\"f1\" =>\n\t\t\t\t\t\t\tdata <= x\"380703\";\n\t\t\t\t\t\twhen \"0\" & x\"f2\" =>\n\t\t\t\t\t\t\tdata <= x\"38080f\";\n\t\t\t\t\t\twhen \"0\" & x\"f3\" =>\n\t\t\t\t\t\t\tdata <= x\"380900\";\n\t\t\t\t\t\twhen \"0\" & x\"f4\" =>\n\t\t\t\t\t\t\tdata <= x\"380a08\";\n\t\t\t\t\t\twhen \"0\" & x\"f5\" =>\n\t\t\t\t\t\t\tdata <= x\"380b70\";\n\t\t\t\t\t\twhen \"0\" & x\"f6\" =>\n\t\t\t\t\t\t\tdata <= x\"380c1a\"; --HTS MSB\n\t\t\t\t\t\twhen \"0\" & x\"f7\" =>\n\t\t\t\t\t\t\tdata <= x\"380d90\"; --HTS LSB\n\t\t\t\t\t\twhen \"0\" & x\"f8\" =>\n\t\t\t\t\t\t\tdata <= x\"380e0b\"; --VTS MSB\n\t\t\t\t\t\twhen \"0\" & x\"f9\" =>\n\t\t\t\t\t\t\tdata <= x\"380fb0\"; --VTS LSB\n\t\t\t\t\t\twhen \"1\" & x\"00\" =>\n\t\t\t\t\t\t\tdata <= x\"381000\";\n\t\t\t\t\t\twhen \"1\" & x\"01\" =>\n\t\t\t\t\t\t\tdata <= x\"381104\";\n\t\t\t\t\t\twhen \"1\" & x\"02\" =>\n\t\t\t\t\t\t\tdata <= x\"381200\";\n\t\t\t\t\t\twhen \"1\" & x\"03\" =>\n\t\t\t\t\t\t\tdata <= x\"381304\";\n\t\t\t\t\t\twhen \"1\" & x\"04\" =>\n\t\t\t\t\t\t\tdata <= x\"383604\";\n\t\t\t\t\t\twhen \"1\" & x\"05\" =>\n\t\t\t\t\t\t\tdata <= x\"383701\";\n\t\t\t\t\t\twhen \"1\" & x\"06\" =>\n\t\t\t\t\t\t\tdata <= x\"402000\";\n\t\t\t\t\t\twhen \"1\" & x\"07\" =>\n\t\t\t\t\t\t\tdata <= x\"4021e6\";\n\t\t\t\t\t\twhen \"1\" & x\"08\" =>\n\t\t\t\t\t\t\tdata <= x\"40220e\";\n\t\t\t\t\t\twhen \"1\" & x\"09\" =>\n\t\t\t\t\t\t\tdata <= x\"40231e\";\n\t\t\t\t\t\twhen \"1\" & x\"0a\" =>\n\t\t\t\t\t\t\tdata <= x\"40240f\";\n\t\t\t\t\t\twhen \"1\" & x\"0b\" =>\n\t\t\t\t\t\t\tdata <= x\"402500\";\n\t\t\t\t\t\twhen \"1\" & x\"0c\" =>\n\t\t\t\t\t\t\tdata <= x\"40260f\";\n\t\t\t\t\t\twhen \"1\" & x\"0d\" =>\n\t\t\t\t\t\t\tdata <= x\"402706\";\n\t\t\t\t\t\twhen \"1\" & x\"0e\" =>\n\t\t\t\t\t\t\tdata <= x\"010001\";\n\t\t\t\t\t\twhen others =>\n\t\t\t\t\t\t\tdata <= x\"000000\";\n\t\t\t\t\tend case;\n\n\t\tend if;\n\tend process;\nend behv_cd;\n" }, { "path": "vhdl_rx/ov-cam-control/ov13850_control_top.vhd", "content": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.NUMERIC_STD.ALL;\n\n--Low speed Omnivision camera reset sequencing and control\n--Copyright (C) 2016 David Shah\n--Licensed under the MIT License\n\nentity ov13850_control_top is\nport(reset : in std_logic;\n clock : in std_logic; --400kHz clock\n i2c_sda : inout std_logic;\n i2c_sck : inout std_logic;\n rst_out : out std_logic;\n loading_out : out std_logic\n );\nend ov13850_control_top;\n\narchitecture Behavioral of ov13850_control_top is\n\nsignal current_cmd : std_logic_vector(23 downto 0);\nsignal statecntr : unsigned(17 downto 0) := (others => '0');\nsignal cmd_addr : std_logic_vector(8 downto 0);\n\nsignal i2c_en : std_logic;\nsignal i2c_start : std_logic;\nsignal i2c_done : std_logic;\n\nconstant state_end : integer := 262000;\n\nbegin\n\n i2c_if : entity work.ov_i2c_control\n generic map(\n slave_addr => x\"20\")\n port map(\n clock_in => clock,\n data_in => current_cmd,\n enable => i2c_en,\n start_xfer => i2c_start,\n xfer_done => i2c_done,\n i2c_sck => i2c_sck,\n i2c_sda => i2c_sda);\n\n regs : entity work.ov13850_4k_regs\n port map(\n clock => clock,\n address => cmd_addr,\n data => current_cmd);\n\n loading_out <= '1' when statecntr < state_end else '0';\n\n --Keep track of where we are in the setup procedure\n process(clock, reset)\n begin\n if reset = '1' then\n statecntr <= (others => '0');\n elsif rising_edge(clock) then\n if statecntr < state_end then\n statecntr <= statecntr + 1;\n end if;\n end if;\n end process;\n\n --Power on reset\n process(statecntr)\n begin\n if statecntr < 16384 then\n rst_out <= '0';\n else\n rst_out <= '1';\n end if;\n end process;\n\n --I2C command selection\n process(statecntr, current_cmd)\n variable statecntr_sub : unsigned(17 downto 0);\n begin\n if statecntr < 32768 then\n i2c_en <= '0';\n i2c_start <= '0';\n cmd_addr <= \"0\" & x\"00\";\n else\n statecntr_sub := statecntr - 32768;\n --We output a new command over I2C every 128 cycles\n cmd_addr <= std_logic_vector(statecntr_sub(17 downto 9));\n --All zeroes indicate a dummy command\n if current_cmd = x\"000000\" then\n i2c_en <= '0';\n i2c_start <= '0';\n else\n i2c_en <= '1';\n --Output a start transaction signal for cycles 1&2\n if statecntr_sub(8 downto 2) = 1 or statecntr_sub(8 downto 2) = 2 then\n i2c_start <= '1';\n else\n i2c_start <= '0';\n end if;\n end if;\n end if;\n end process;\nend Behavioral;\n" }, { "path": "vhdl_rx/ov-cam-control/ov16825_1080p120_regs.vhd", "content": "library ieee ;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\n--OV16825 Camera Configuration\n\n--This configuration is for 1080p, 120fps, 10-bit, 4-lane with a total horizontal length of 4224 pixels\n--and a total vertical length of 1248 lines\n\nentity ov16825_1080p120_regs is\nport (clock : in std_logic; --this allows a blockram to be elaborated\n \t\taddress : in std_logic_vector(8 downto 0);\n \t\t--This is the I2C data to be written\n \t\t--2 MSBs are address, 1 MSB is data\n \t\tdata : out std_logic_vector(23 downto 0));\nend ov16825_1080p120_regs;\n\narchitecture behv_cd of ov16825_1080p120_regs is\nbegin\n\tprocess(clock)\n\tbegin\n\t\tif rising_edge(clock) then\n\t\t\tcase address(8 downto 0) is\n --Global init\n when \"0\" & x\"00\" =>\n data <= x\"010301\"; --software reset\n\n when \"0\" & x\"10\" => --PLL setup\n data <= x\"010000\";\n when \"0\" & x\"11\" =>\n data <= x\"030002\";\n when \"0\" & x\"12\" =>\n data <= x\"030250\";\n when \"0\" & x\"13\" =>\n data <= x\"030501\";\n when \"0\" & x\"14\" =>\n data <= x\"030600\";\n when \"0\" & x\"15\" =>\n data <= x\"030b02\";\n when \"0\" & x\"16\" =>\n data <= x\"030c14\";\n when \"0\" & x\"17\" =>\n data <= x\"030e00\";\n when \"0\" & x\"18\" =>\n data <= x\"031302\";\n when \"0\" & x\"19\" =>\n data <= x\"031414\";\n when \"0\" & x\"1a\" =>\n data <= x\"031f00\";\n\n when \"0\" & x\"20\" =>\n data <= x\"302201\";\n when \"0\" & x\"21\" =>\n data <= x\"303280\";\n when \"0\" & x\"22\" =>\n data <= x\"3601f8\";\n when \"0\" & x\"23\" =>\n data <= x\"360200\";\n when \"0\" & x\"24\" =>\n data <= x\"360550\";\n when \"0\" & x\"25\" =>\n data <= x\"360600\";\n when \"0\" & x\"26\" =>\n data <= x\"36072b\";\n when \"0\" & x\"27\" =>\n data <= x\"360816\";\n when \"0\" & x\"28\" =>\n data <= x\"360900\";\n when \"0\" & x\"29\" =>\n data <= x\"360e99\";\n when \"0\" & x\"2a\" =>\n data <= x\"360f75\";\n when \"0\" & x\"2b\" =>\n data <= x\"361069\";\n when \"0\" & x\"2c\" =>\n data <= x\"361159\";\n when \"0\" & x\"2d\" =>\n data <= x\"361240\";\n when \"0\" & x\"2e\" =>\n data <= x\"361389\";\n when \"0\" & x\"2f\" =>\n data <= x\"361544\";\n when \"0\" & x\"30\" =>\n data <= x\"361700\";\n when \"0\" & x\"31\" =>\n data <= x\"361820\";\n when \"0\" & x\"32\" =>\n data <= x\"361900\";\n when \"0\" & x\"33\" =>\n data <= x\"361a10\";\n when \"0\" & x\"34\" =>\n data <= x\"361c10\";\n when \"0\" & x\"35\" =>\n data <= x\"361d00\";\n when \"0\" & x\"36\" =>\n data <= x\"361e00\";\n when \"0\" & x\"37\" =>\n data <= x\"364015\";\n when \"0\" & x\"38\" =>\n data <= x\"364154\";\n when \"0\" & x\"39\" =>\n data <= x\"364263\";\n when \"0\" & x\"3a\" =>\n data <= x\"364332\";\n when \"0\" & x\"3b\" =>\n data <= x\"364403\";\n when \"0\" & x\"3c\" =>\n data <= x\"364504\";\n when \"0\" & x\"3d\" =>\n data <= x\"364685\";\n when \"0\" & x\"3e\" =>\n data <= x\"364a07\";\n when \"0\" & x\"3f\" =>\n data <= x\"370708\";\n when \"0\" & x\"40\" =>\n data <= x\"371875\";\n when \"0\" & x\"41\" =>\n data <= x\"371a55\";\n when \"0\" & x\"42\" =>\n data <= x\"371c55\";\n when \"0\" & x\"43\" =>\n data <= x\"373380\";\n when \"0\" & x\"44\" =>\n data <= x\"376000\";\n when \"0\" & x\"45\" =>\n data <= x\"376130\";\n when \"0\" & x\"46\" =>\n data <= x\"376200\";\n when \"0\" & x\"47\" =>\n data <= x\"3763c0\";\n when \"0\" & x\"48\" =>\n data <= x\"376403\";\n when \"0\" & x\"49\" =>\n data <= x\"376500\";\n\n when \"0\" & x\"50\" =>\n data <= x\"382308\";\n when \"0\" & x\"51\" =>\n data <= x\"382702\";\n when \"0\" & x\"52\" =>\n data <= x\"382800\";\n when \"0\" & x\"53\" =>\n data <= x\"383200\";\n when \"0\" & x\"54\" =>\n data <= x\"383300\";\n when \"0\" & x\"55\" =>\n data <= x\"383400\";\n when \"0\" & x\"56\" =>\n data <= x\"3d8517\";\n when \"0\" & x\"57\" =>\n data <= x\"3d8c70\";\n when \"0\" & x\"58\" =>\n data <= x\"3d8da0\";\n when \"0\" & x\"59\" =>\n data <= x\"3f0002\";\n\n when \"0\" & x\"60\" =>\n data <= x\"400183\";\n when \"0\" & x\"61\" =>\n data <= x\"400e00\";\n when \"0\" & x\"62\" =>\n data <= x\"401100\";\n when \"0\" & x\"63\" =>\n data <= x\"401200\";\n when \"0\" & x\"64\" =>\n data <= x\"420008\";\n when \"0\" & x\"65\" =>\n data <= x\"43027f\";\n when \"0\" & x\"66\" =>\n data <= x\"4303ff\";\n when \"0\" & x\"67\" =>\n data <= x\"430400\";\n when \"0\" & x\"68\" =>\n data <= x\"430500\";\n when \"0\" & x\"69\" =>\n data <= x\"450130\";\n when \"0\" & x\"6a\" =>\n data <= x\"460320\";\n when \"0\" & x\"6b\" =>\n data <= x\"4b0022\";\n when \"0\" & x\"6c\" =>\n data <= x\"490300\";\n when \"0\" & x\"6d\" =>\n data <= x\"50007f\";\n when \"0\" & x\"6e\" =>\n data <= x\"500101\";\n when \"0\" & x\"6f\" =>\n data <= x\"500400\";\n when \"0\" & x\"70\" =>\n data <= x\"501320\";\n when \"0\" & x\"71\" =>\n data <= x\"505100\";\n when \"0\" & x\"72\" =>\n data <= x\"550001\";\n when \"0\" & x\"73\" =>\n data <= x\"550100\";\n when \"0\" & x\"74\" =>\n data <= x\"550207\";\n when \"0\" & x\"75\" =>\n data <= x\"5503ff\";\n when \"0\" & x\"76\" =>\n data <= x\"55056c\";\n when \"0\" & x\"77\" =>\n data <= x\"550902\";\n when \"0\" & x\"78\" =>\n data <= x\"5780fc\";\n when \"0\" & x\"79\" =>\n data <= x\"5781ff\";\n when \"0\" & x\"7a\" =>\n data <= x\"578740\";\n when \"0\" & x\"7b\" =>\n data <= x\"578808\";\n when \"0\" & x\"7c\" =>\n data <= x\"578a02\";\n when \"0\" & x\"7d\" =>\n data <= x\"578b01\";\n when \"0\" & x\"7e\" =>\n data <= x\"578c01\";\n when \"0\" & x\"7f\" =>\n data <= x\"578e02\";\n when \"0\" & x\"80\" =>\n data <= x\"578f01\";\n when \"0\" & x\"81\" =>\n data <= x\"579001\";\n when \"0\" & x\"82\" =>\n data <= x\"579200\";\n when \"0\" & x\"83\" =>\n data <= x\"598000\";\n when \"0\" & x\"84\" =>\n data <= x\"598121\";\n when \"0\" & x\"85\" =>\n data <= x\"598200\";\n when \"0\" & x\"86\" =>\n data <= x\"598300\";\n when \"0\" & x\"87\" =>\n data <= x\"598400\";\n when \"0\" & x\"88\" =>\n data <= x\"598500\";\n when \"0\" & x\"89\" =>\n data <= x\"598600\";\n when \"0\" & x\"8a\" =>\n data <= x\"598700\";\n when \"0\" & x\"8b\" =>\n data <= x\"598800\";\n\n when \"0\" & x\"90\" =>\n data <= x\"320115\";\n when \"0\" & x\"91\" =>\n data <= x\"32022a\";\n\n --1080p120 specific config\n when \"0\" & x\"a0\" =>\n data <= x\"010000\";\n\n when \"0\" & x\"b0\" =>\n data <= x\"320800\";\n when \"0\" & x\"b1\" =>\n data <= x\"301afb\";\n when \"0\" & x\"b2\" =>\n data <= x\"030264\";\n when \"0\" & x\"b3\" =>\n data <= x\"030501\";\n when \"0\" & x\"b4\" =>\n data <= x\"030e00\";\n when \"0\" & x\"b5\" =>\n data <= x\"30187a\";\n when \"0\" & x\"b6\" =>\n data <= x\"30310a\";\n when \"0\" & x\"b7\" =>\n data <= x\"360305\";\n when \"0\" & x\"b8\" =>\n data <= x\"360402\";\n when \"0\" & x\"b9\" =>\n data <= x\"360a02\";\n when \"0\" & x\"ba\" =>\n data <= x\"360b02\";\n when \"0\" & x\"bb\" =>\n data <= x\"360c12\";\n when \"0\" & x\"bc\" =>\n data <= x\"360d04\";\n when \"0\" & x\"bd\" =>\n data <= x\"361477\";\n when \"0\" & x\"be\" =>\n data <= x\"361631\";\n when \"0\" & x\"bf\" =>\n data <= x\"363140\";\n\n when \"0\" & x\"c0\" =>\n data <= x\"370060\";\n when \"0\" & x\"c1\" =>\n data <= x\"370110\";\n when \"0\" & x\"c2\" =>\n data <= x\"370222\";\n when \"0\" & x\"c3\" =>\n data <= x\"370340\";\n when \"0\" & x\"c4\" =>\n data <= x\"370410\";\n when \"0\" & x\"c5\" =>\n data <= x\"370501\";\n when \"0\" & x\"c6\" =>\n data <= x\"370604\";\n when \"0\" & x\"c7\" =>\n data <= x\"370840\";\n when \"0\" & x\"c8\" =>\n data <= x\"370978\";\n when \"0\" & x\"c9\" =>\n data <= x\"370a02\";\n when \"0\" & x\"ca\" =>\n data <= x\"370bb2\";\n when \"0\" & x\"cb\" =>\n data <= x\"370c06\";\n when \"0\" & x\"cc\" =>\n data <= x\"370e40\";\n when \"0\" & x\"cd\" =>\n data <= x\"370f0a\";\n\n when \"0\" & x\"d0\" =>\n data <= x\"371030\";\n when \"0\" & x\"d1\" =>\n data <= x\"371140\";\n when \"0\" & x\"d2\" =>\n data <= x\"371431\";\n when \"0\" & x\"d3\" =>\n data <= x\"371925\";\n when \"0\" & x\"d4\" =>\n data <= x\"371b05\";\n when \"0\" & x\"d5\" =>\n data <= x\"371d05\";\n when \"0\" & x\"d6\" =>\n data <= x\"371e11\";\n when \"0\" & x\"d7\" =>\n data <= x\"371f2d\";\n\n when \"0\" & x\"e0\" =>\n data <= x\"372015\";\n when \"0\" & x\"e1\" =>\n data <= x\"372130\";\n when \"0\" & x\"e2\" =>\n data <= x\"372215\";\n when \"0\" & x\"e3\" =>\n data <= x\"372330\";\n when \"0\" & x\"e4\" =>\n data <= x\"372408\";\n when \"0\" & x\"e5\" =>\n data <= x\"372508\";\n when \"0\" & x\"e6\" =>\n data <= x\"372604\";\n when \"0\" & x\"e7\" =>\n data <= x\"372704\";\n when \"0\" & x\"e8\" =>\n data <= x\"372804\";\n when \"0\" & x\"e9\" =>\n data <= x\"372904\";\n when \"0\" & x\"ea\" =>\n data <= x\"372a29\";\n when \"0\" & x\"eb\" =>\n data <= x\"372bc9\";\n when \"0\" & x\"ec\" =>\n data <= x\"372ca9\";\n when \"0\" & x\"ed\" =>\n data <= x\"372db9\";\n when \"0\" & x\"ee\" =>\n data <= x\"372e95\";\n when \"0\" & x\"ef\" =>\n data <= x\"372f55\";\n when \"0\" & x\"f0\" =>\n data <= x\"373055\";\n when \"0\" & x\"f1\" =>\n data <= x\"373155\";\n when \"0\" & x\"f2\" =>\n data <= x\"373205\";\n when \"0\" & x\"f3\" =>\n data <= x\"373410\";\n when \"0\" & x\"f4\" =>\n data <= x\"373905\";\n when \"0\" & x\"f5\" =>\n data <= x\"373a40\";\n when \"0\" & x\"f6\" =>\n data <= x\"373b18\";\n when \"0\" & x\"f7\" =>\n data <= x\"373c38\";\n when \"0\" & x\"f8\" =>\n data <= x\"373e15\";\n when \"0\" & x\"f9\" =>\n data <= x\"373f80\";\n\n when \"1\" & x\"00\" =>\n data <= x\"380001\";\n when \"1\" & x\"01\" =>\n data <= x\"380180\";\n when \"1\" & x\"02\" =>\n data <= x\"380202\";\n when \"1\" & x\"03\" =>\n data <= x\"380394\";\n when \"1\" & x\"04\" =>\n data <= x\"380410\";\n when \"1\" & x\"05\" =>\n data <= x\"3805bf\";\n when \"1\" & x\"06\" =>\n data <= x\"38060b\";\n when \"1\" & x\"07\" =>\n data <= x\"38070f\";\n when \"1\" & x\"08\" =>\n data <= x\"380807\";\n when \"1\" & x\"09\" =>\n data <= x\"380980\";\n when \"1\" & x\"0a\" =>\n data <= x\"380a04\";\n when \"1\" & x\"0b\" =>\n data <= x\"380b38\";\n when \"1\" & x\"0c\" =>\n data <= x\"380c04\";\n when \"1\" & x\"0d\" =>\n data <= x\"380d20\";\n when \"1\" & x\"0e\" =>\n data <= x\"380e04\";\n when \"1\" & x\"0f\" =>\n data <= x\"380fe0\";\n when \"1\" & x\"10\" =>\n data <= x\"381117\";\n when \"1\" & x\"11\" =>\n data <= x\"381302\";\n when \"1\" & x\"12\" =>\n data <= x\"381403\";\n when \"1\" & x\"13\" =>\n data <= x\"381501\";\n when \"1\" & x\"14\" =>\n data <= x\"382000\";\n when \"1\" & x\"15\" =>\n data <= x\"382107\";\n when \"1\" & x\"16\" =>\n data <= x\"382900\";\n when \"1\" & x\"17\" =>\n data <= x\"382a03\";\n when \"1\" & x\"18\" =>\n data <= x\"382b01\";\n when \"1\" & x\"19\" =>\n data <= x\"383008\";\n when \"1\" & x\"1a\" =>\n data <= x\"3f0840\";\n\n when \"1\" & x\"20\" =>\n data <= x\"400202\";\n when \"1\" & x\"21\" =>\n data <= x\"400304\";\n when \"1\" & x\"22\" =>\n data <= x\"483714\";\n when \"1\" & x\"23\" =>\n data <= x\"350144\";\n when \"1\" & x\"24\" =>\n data <= x\"350808\";\n when \"1\" & x\"25\" =>\n data <= x\"3509ff\";\n when \"1\" & x\"26\" =>\n data <= x\"363800\";\n when \"1\" & x\"27\" =>\n data <= x\"301af0\";\n when \"1\" & x\"28\" =>\n data <= x\"320810\";\n when \"1\" & x\"29\" =>\n data <= x\"3208a0\";\n\n when \"1\" & x\"30\" =>\n data <= x\"380807\";\n when \"1\" & x\"31\" =>\n data <= x\"380980\";\n when \"1\" & x\"32\" =>\n data <= x\"380a04\";\n when \"1\" & x\"33\" =>\n data <= x\"380b38\";\n when \"1\" & x\"34\" =>\n data <= x\"381000\";\n when \"1\" & x\"35\" =>\n data <= x\"381117\";\n when \"1\" & x\"36\" =>\n data <= x\"381200\";\n when \"1\" & x\"37\" =>\n data <= x\"381302\";\n when \"1\" & x\"38\" =>\n data <= x\"46032f\";\n when \"1\" & x\"39\" =>\n data <= x\"50007f\";\n\n when \"1\" & x\"40\" =>\n data <= x\"010001\";\n \t\t\t\twhen others =>\n\t\t\t\t\t\tdata <= x\"000000\";\n\t\t\t\tend case;\n\t\tend if;\n\tend process;\nend behv_cd;\n" }, { "path": "vhdl_rx/ov-cam-control/ov_i2c_control.vhd", "content": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.NUMERIC_STD.ALL;\n\n--I2C controller for Omnivision camera control (used in the OV13850 demo)\n--Ugly but it works :). This is actually from a OV5640 driver I wrote a while ago,\n--so it's from when I was still learning VHDL...\n\n--Copyright (C) 2016 David Shah\n--Licensed under the MIT License\n\nentity ov_i2c_control is\n generic (\n slave_addr : std_logic_vector(7 downto 0) := x\"20\"); --OV13850 slave address\n port (clock_in : in std_logic;\n data_in : in std_logic_vector(23 downto 0); -- 16 bit address followed by 8 bit data\n enable : in std_logic;\n start_xfer : in std_logic; --pull high, then low to reset and start xfer\n xfer_done : out std_logic; --signifies that the transfer is done\n i2c_sck : inout std_logic; --I2C SCK pin\n i2c_sda : inout std_logic); --I2C SDA pin\nend ov_i2c_control;\n\narchitecture Behavioral of ov_i2c_control is\n signal sys_en : std_logic;\n signal sda_int : std_logic; --Internal I2C data, 0=low, 1=tristate\n signal sck_int : std_logic; --Internal I2C clock, 0=low, 1=tristate\n signal sck_force : std_logic; --Used to force I2C clock\n\n signal state_cntr : unsigned(7 downto 0); --Internal counter for keeping track of state\n\n constant state_done : integer := 168; --value of state_cntr when transfer finished\n\nbegin\n\n process(enable, start_xfer, state_cntr)\n begin\n if enable = '1' and start_xfer = '0' then\n if state_cntr >= state_done then\n sys_en <= '0';\n xfer_done <= '1';\n else\n sys_en <= '1';\n xfer_done <= '0';\n end if;\n else\n sys_en <= '0';\n xfer_done <= '0';\n end if;\n end process;\n\n process(start_xfer, clock_in)\n begin\n if start_xfer = '1' then\n state_cntr <= \"00000000\";\n else\n if rising_edge(clock_in) then\n if state_cntr < state_done then\n state_cntr <= state_cntr + 1;\n end if;\n end if;\n end if;\n end process;\n\n process(sda_int, sck_int, sys_en)\n begin\n if sys_en = '1' then\n if sda_int = '1' then\n i2c_sda <= 'Z';\n else\n i2c_sda <= '0';\n end if;\n\n if sck_int = '1' then\n i2c_sck <= 'Z';\n else\n i2c_sck <= '0';\n end if;\n else\n i2c_sda <= 'Z';\n i2c_sck <= 'Z';\n end if;\n end process;\n\n process(state_cntr, clock_in, sck_force)\n\n begin\n if state_cntr(7 downto 2) >= 4 and state_cntr(7 downto 2) <= 39 then\n sck_int <= sck_force or (state_cntr(1) xor state_cntr(0));\n else\n sck_int <= sck_force;\n end if;\n end process;\n\n process(start_xfer, clock_in)\n begin\n if start_xfer = '1' then\n sda_int <= '1';\n sck_force <= '1';\n elsif rising_edge(clock_in) then\n if state_cntr(1 downto 0) = 3 then\n case state_cntr(7 downto 2) is\n --start sequence\n when \"000000\" =>\n sda_int <= '1';\n sck_force <= '1';\n when \"000001\" =>\n sda_int <= '0';\n when \"000010\" =>\n sck_force <= '0';\n --I2C slave address\n when \"000011\" =>\n sda_int <= slave_addr(7);\n when \"000100\" =>\n sda_int <= slave_addr(6);\n when \"000101\" =>\n sda_int <= slave_addr(5);\n when \"000110\" =>\n sda_int <= slave_addr(4);\n when \"000111\" =>\n sda_int <= slave_addr(3);\n when \"001000\" =>\n sda_int <= slave_addr(2);\n when \"001001\" =>\n sda_int <= slave_addr(1);\n when \"001010\" =>\n sda_int <= '0'; --WRITE transaction\n when \"001011\" =>\n sda_int <= '1';\n --Register address MSB\n when \"001100\" =>\n sda_int <= data_in(23);\n when \"001101\" =>\n sda_int <= data_in(22);\n when \"001110\" =>\n sda_int <= data_in(21);\n when \"001111\" =>\n sda_int <= data_in(20);\n when \"010000\" =>\n sda_int <= data_in(19);\n when \"010001\" =>\n sda_int <= data_in(18);\n when \"010010\" =>\n sda_int <= data_in(17);\n when \"010011\" =>\n sda_int <= data_in(16);\n when \"010100\" =>\n sda_int <= '1';\n --Register address LSB\n when \"010101\" =>\n sda_int <= data_in(15);\n when \"010110\" =>\n sda_int <= data_in(14);\n when \"010111\" =>\n sda_int <= data_in(13);\n when \"011000\" =>\n sda_int <= data_in(12);\n when \"011001\" =>\n sda_int <= data_in(11);\n when \"011010\" =>\n sda_int <= data_in(10);\n when \"011011\" =>\n sda_int <= data_in(9);\n when \"011100\" =>\n sda_int <= data_in(8);\n when \"011101\" =>\n sda_int <= '1';\n --Register value\n when \"011110\" =>\n sda_int <= data_in(7);\n when \"011111\" =>\n sda_int <= data_in(6);\n when \"100000\" =>\n sda_int <= data_in(5);\n when \"100001\" =>\n sda_int <= data_in(4);\n when \"100010\" =>\n sda_int <= data_in(3);\n when \"100011\" =>\n sda_int <= data_in(2);\n when \"100100\" =>\n sda_int <= data_in(1);\n when \"100101\" =>\n sda_int <= data_in(0);\n when \"100110\" =>\n sda_int <= '1';\n --STOP\n when \"100111\" =>\n sda_int <= '0';\n sck_force <= '0';\n when \"101000\" =>\n sck_force <= '1';\n when \"101001\" =>\n sda_int <= '1';\n when others =>\n end case;\n end if;\n end if;\n end process;\nend Behavioral;\n" }, { "path": "vhdl_rx/ov-cam-control/vcm_i2c_control.vhd", "content": "library ieee ;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\n--I2C controller for the VCM driver inside the camera module, responsible for\n--focusing\n--Copyright (C) 2016 David Shah\n--Licensed under the MIT License\n\n\nentity vcm_i2c_control is\nport (clock_in : in std_logic;\n data_in : in std_logic_vector(9 downto 0); -- 10 bit VCM setting\n enable : in std_logic;\n start_xfer : in std_logic; --pull high, then low to reset and start xfer\n xfer_done : out std_logic; --signifies that the transfer is done\n i2c_sck : inout std_logic; --I2C SCK pin\n i2c_sda : inout std_logic); --I2C SDA pin\nend vcm_i2c_control;\n\narchitecture behv_i2c of vcm_i2c_control is\nsignal sys_en : std_logic;\nsignal sda_int : std_logic; --Internal I2C data, 0=low, 1=tristate\nsignal sck_int : std_logic; --Internal I2C clock, 0=low, 1=tristate\nsignal sck_force : std_logic; --Used to force I2C clock\n\nsignal state_cntr : unsigned(7 downto 0); --Internal counter for keeping track of state\n\nconstant state_done : integer := 168; --value of state_cntr when transfer finished\n\nconstant slave_addr : std_logic_vector(7 downto 0) := x\"18\"; --VCM driver slave address\n\nbegin\n\nprocess(enable, start_xfer, state_cntr)\nbegin\n if enable = '1' and start_xfer = '0' then\n if state_cntr >= state_done then\n sys_en <= '0';\n xfer_done <= '1';\n else\n sys_en <= '1';\n xfer_done <= '0';\n end if;\n else\n sys_en <= '0';\n xfer_done <= '0';\n end if;\nend process;\n\nprocess(start_xfer, clock_in)\nbegin\n if start_xfer = '1' then\n state_cntr <= \"00000000\";\n else\n if rising_edge(clock_in) then\n if state_cntr < state_done then\n state_cntr <= state_cntr + 1;\n end if;\n end if;\n end if;\nend process;\n\nprocess(sda_int, sck_int, sys_en)\nbegin\n if sys_en = '1' then\n if sda_int = '1' then\n i2c_sda <= 'Z';\n else\n i2c_sda <= '0';\n end if;\n\n if sck_int = '1' then\n i2c_sck <= 'Z';\n else\n i2c_sck <= '0';\n end if;\n else\n i2c_sda <= 'Z';\n i2c_sck <= 'Z';\n end if;\nend process;\n\nprocess(state_cntr, clock_in, sck_force)\n\nbegin\n if state_cntr(7 downto 2) >= 13 and state_cntr(7 downto 2) <= 39 then\n sck_int <= sck_force or (state_cntr(1) xor state_cntr(0));\n else\n sck_int <= sck_force;\n end if;\nend process;\n\nprocess(start_xfer, clock_in)\nbegin\n if start_xfer = '1' then\n sda_int <= '1';\n sck_force <= '1';\n elsif rising_edge(clock_in) then\n if state_cntr(1 downto 0) = 3 then\n case state_cntr(7 downto 2) is\n --start sequence\n when \"001001\" =>\n sda_int <= '1';\n sck_force <= '1';\n when \"001010\" =>\n sda_int <= '0';\n when \"001011\" =>\n sck_force <= '0';\n --I2C slave address\n when \"001100\" =>\n sda_int <= slave_addr(7);\n when \"001101\" =>\n sda_int <= slave_addr(6);\n when \"001110\" =>\n sda_int <= slave_addr(5);\n when \"001111\" =>\n sda_int <= slave_addr(4);\n when \"010000\" =>\n sda_int <= slave_addr(3);\n when \"010001\" =>\n sda_int <= slave_addr(2);\n when \"010010\" =>\n sda_int <= slave_addr(1);\n when \"010011\" =>\n sda_int <= slave_addr(0);\n when \"010100\" =>\n sda_int <= '1';\n --Register address LSB\n when \"010101\" =>\n sda_int <= '0';\n when \"010110\" =>\n sda_int <= '0';\n when \"010111\" =>\n sda_int <= data_in(9);\n when \"011000\" =>\n sda_int <= data_in(8);\n when \"011001\" =>\n sda_int <= data_in(7);\n when \"011010\" =>\n sda_int <= data_in(6);\n when \"011011\" =>\n sda_int <= data_in(5);\n when \"011100\" =>\n sda_int <= data_in(4);\n when \"011101\" =>\n sda_int <= '1';\n --Register value\n when \"011110\" =>\n sda_int <= data_in(3);\n when \"011111\" =>\n sda_int <= data_in(2);\n when \"100000\" =>\n sda_int <= data_in(1);\n when \"100001\" =>\n sda_int <= data_in(0);\n when \"100010\" =>\n sda_int <= '0';\n when \"100011\" =>\n sda_int <= '1';\n when \"100100\" =>\n sda_int <= '1';\n when \"100101\" =>\n sda_int <= '1';\n when \"100110\" =>\n sda_int <= '1';\n --STOP\n when \"100111\" =>\n sda_int <= '0';\n sck_force <= '0';\n when \"101000\" =>\n sck_force <= '1';\n when \"101001\" =>\n sda_int <= '1';\n when others =>\n end case;\n end if;\n end if;\nend process;\nend behv_i2c;\n" }, { "path": "vhdl_rx/video-misc/image_gain_wb.vhd", "content": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.NUMERIC_STD.ALL;\n\n--Gain/White Balance for CSI-2 Rx Example\n--Copyright (C) 2016 David Shah\n--Licensed under the MIT License\n\n--This applies simple gain and white balance adjustments to the image, also converting 10-bit\n--RGB to 8-bit RGB. Like other processing blocks this operates on two pixels per clock\n\nentity image_gain_wb is\n generic (\n --Red, green and blue channel gains in units of 1/8\n red_gain : natural := 10;\n green_gain : natural := 7;\n blue_gain : natural := 9\n );\n port(\n clock : in std_logic;\n\n input_vsync : in std_logic;\n input_hsync : in std_logic;\n input_den : in std_logic;\n input_line_start : in std_logic;\n input_data_even : in std_logic_vector(29 downto 0);\n input_data_odd : in std_logic_vector(29 downto 0);\n\n output_vsync : out std_logic;\n output_hsync : out std_logic;\n output_den : out std_logic;\n output_line_start : out std_logic;\n output_data_even : out std_logic_vector(23 downto 0);\n output_data_odd : out std_logic_vector(23 downto 0)\n\n );\nend image_gain_wb;\n\narchitecture Behavioral of image_gain_wb is\n\n --Multiply a 10-bit number by a 4-bit natural and shift right to a 11-bit result\n function channel_mul(ch : std_logic_vector; gain : natural)\n return std_logic_vector is\n variable chvalue : unsigned(9 downto 0);\n variable gvalue : unsigned(3 downto 0);\n variable mul : unsigned(13 downto 0);\n variable result : std_logic_vector(10 downto 0);\n begin\n chvalue := unsigned(ch);\n gvalue := to_unsigned(gain, 4);\n mul := chvalue * gvalue;\n result := std_logic_vector(mul(13 downto 3));\n return result;\n end channel_mul;\n\n --Divide an 11-bit number by 4 and clamp it to an 8 bit unsigned value\n function clamp_to_8bit(inp : std_logic_vector)\n return std_logic_vector is\n variable result : std_logic_vector(7 downto 0);\n variable value : unsigned(10 downto 0);\n begin\n value := unsigned(inp);\n if value > 1023 then\n result := x\"FF\";\n else\n result := std_logic_vector(value(9 downto 2));\n end if;\n return result;\n end clamp_to_8bit;\n\nbegin\n\n process(clock)\n begin\n if rising_edge(clock) then\n output_vsync <= input_vsync;\n output_hsync <= input_hsync;\n output_den <= input_den;\n output_line_start <= input_line_start;\n\n output_data_even(7 downto 0) <= clamp_to_8bit(channel_mul(input_data_even(9 downto 0), blue_gain));\n output_data_even(15 downto 8) <= clamp_to_8bit(channel_mul(input_data_even(19 downto 10), green_gain));\n output_data_even(23 downto 16) <= clamp_to_8bit(channel_mul(input_data_even(29 downto 20), red_gain));\n\n output_data_odd(7 downto 0) <= clamp_to_8bit(channel_mul(input_data_odd(9 downto 0), blue_gain));\n output_data_odd(15 downto 8) <= clamp_to_8bit(channel_mul(input_data_odd(19 downto 10), green_gain));\n output_data_odd(23 downto 16) <= clamp_to_8bit(channel_mul(input_data_odd(29 downto 20), red_gain));\n end if;\n end process;\n\nend Behavioral;\n" }, { "path": "vhdl_rx/video-misc/simple_debayer.vhd", "content": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.NUMERIC_STD.ALL;\n\n--Minimal Debayering Block for CSI-2 Rx\n--Copyright (C) 2016 David Shah\n--Licensed under the MIT License\n\n--This uses the simplest possible method to debayer two pixels per clock,\n--purely as a proof of concept to demo the CSI-2 Rx core. It is designed to go between\n--the CSI-2 Rx and the white balance/gain controller, also included in the example\n\nentity simple_debayer is\n port(\n clock : in std_logic;\n\n input_hsync : in std_logic;\n input_vsync : in std_logic;\n input_den : in std_logic;\n input_line_start : in std_logic;\n input_odd_line : in std_logic;\n input_data : in std_logic_vector(19 downto 0);\n input_prev_line_data : in std_logic_vector(19 downto 0);\n\n output_hsync : out std_logic;\n output_vsync : out std_logic;\n output_den : out std_logic;\n output_line_start : out std_logic;\n output_data_even : out std_logic_vector(29 downto 0); --10bit R:G:B\n output_data_odd : out std_logic_vector(29 downto 0) --10bit R:G:B\n );\nend simple_debayer;\n\narchitecture Behavioral of simple_debayer is\nsignal last_block_c, last_block_p : std_logic_vector(19 downto 0);\nsignal pre_hsync, pre_vsync, pre_den, pre_line_start : std_logic;\nsignal pre_data_even, pre_data_odd : std_logic_vector(29 downto 0);\nfunction channel_average(val_1, val_2 : std_logic_vector)\n return std_logic_vector is\n variable sum : unsigned(10 downto 0);\n variable result : std_logic_vector(9 downto 0);\n begin\n sum := resize(unsigned(val_1), 11) + resize(unsigned(val_2), 11);\n result := std_logic_vector(sum(10 downto 1));\n return result;\nend function;\n\n\nbegin\n process(clock)\n variable pixel_0_R, pixel_0_G, pixel_0_B : std_logic_vector(9 downto 0);\n variable pixel_1_R, pixel_1_G, pixel_1_B : std_logic_vector(9 downto 0);\n\n begin\n if rising_edge(clock) then\n pre_hsync <= input_hsync;\n pre_vsync <= input_vsync;\n pre_den <= input_den;\n pre_line_start <= input_line_start;\n\n if input_odd_line = '1' then\n pixel_0_R := channel_average(input_data(19 downto 10), last_block_c(19 downto 10));\n pixel_0_G := input_data(9 downto 0);\n pixel_0_B := input_prev_line_data(9 downto 0);\n\n pixel_1_R := input_data(19 downto 10);\n pixel_1_G := channel_average(input_data(9 downto 0), last_block_p(19 downto 10));\n pixel_1_B := input_prev_line_data(9 downto 0);\n else\n pixel_0_R := channel_average(input_prev_line_data(19 downto 10), last_block_p(19 downto 10));\n pixel_0_G := channel_average(input_data(19 downto 10), last_block_c(19 downto 10));\n pixel_0_B := input_data(9 downto 0);\n\n pixel_1_R := input_prev_line_data(19 downto 10);\n pixel_1_G := input_data(19 downto 10);\n pixel_1_B := input_data(9 downto 0);\n end if;\n\n pre_data_even <= pixel_0_R & pixel_0_G & pixel_0_B;\n pre_data_odd <= pixel_1_R & pixel_1_G & pixel_1_B;\n\n output_hsync <= pre_hsync;\n output_vsync <= pre_vsync;\n output_den <= pre_den;\n output_line_start <= pre_line_start;\n output_data_even <= pre_data_even;\n output_data_odd <= pre_data_odd;\n\n if input_den = '1' then\n last_block_c <= input_data;\n last_block_p <= input_prev_line_data;\n end if;\n end if;\n end process;\nend architecture;\n" }, { "path": "vhdl_rx/video-misc/test_pattern_gen.vhd", "content": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.NUMERIC_STD.ALL;\n\n--Simple Test Square Generator\n--Copyright (C) 2016 David Shah\n--Licensed under the MIT License\n\nentity test_pattern_gen is\n generic(\n video_hlength : natural := 4046; --total visible and blanking pixels per line\n video_vlength : natural := 2190; --total visible and blanking lines per frame\n\n video_hsync_pol : boolean := true; --hsync polarity: true for positive sync, false for negative sync\n video_hsync_len : natural := 48; --horizontal sync length in pixels\n video_hbp_len : natural := 122; --horizontal back porch length (excluding sync)\n video_h_visible : natural := 3840; --number of visible pixels per line\n\n video_vsync_pol : boolean := true; --vsync polarity: true for positive sync, false for negative sync\n video_vsync_len : natural := 3; --vertical sync length in lines\n video_vbp_len : natural := 23; --vertical back porch length (excluding sync)\n video_v_visible : natural := 2160 --number of visible lines per frame\n );\n\n port(\n pixel_clock : in std_logic;\n reset : in std_logic; --active high async reset\n\n video_vsync : out std_logic;\n video_hsync : out std_logic;\n video_den : out std_logic;\n video_line_start : out std_logic;\n\n --2 pixel per clock output\n video_pixel_even : out std_logic_vector(23 downto 0);\n video_pixel_odd : out std_logic_vector(23 downto 0)\n );\nend test_pattern_gen;\n\narchitecture Behavioral of test_pattern_gen is\n type pattern_colours_t is array(0 to 15) of std_logic_vector(23 downto 0);\n\n constant pattern_colours : pattern_colours_t := (x\"FF0000\", x\"00FF00\", x\"0000FF\", x\"FFFFFF\",\n x\"AA0000\", x\"00AA00\", x\"0000AA\", x\"AAAAAA\",\n x\"550000\", x\"005500\", x\"000055\", x\"555555\",\n x\"FFFF00\", x\"FF00FF\", x\"00FFFF\", x\"000000\");\n\n\n signal pattern_index : unsigned(3 downto 0);\n signal pattern_value : std_logic_vector(23 downto 0);\n\n signal den_int : std_logic;\n signal pixel_x_div : natural range 0 to (video_h_visible / 2) - 1;\n signal pixel_x : natural range 0 to video_h_visible - 1;\n signal pixel_y : natural range 0 to video_v_visible - 1;\n\n\nbegin\n\n pixel_x <= pixel_x_div * 2;\n\n pattern_index(1 downto 0) <= to_unsigned(pixel_x, 14)(4 downto 3);\n pattern_index(3 downto 2) <= to_unsigned(pixel_y, 14)(4 downto 3);\n\n pattern_value <= pattern_colours(to_integer(pattern_index));\n\n video_pixel_even <= pattern_value when den_int = '1' else x\"000000\";\n video_pixel_odd <= pattern_value when den_int = '1' else x\"000000\";\n\n video_den <= den_int;\n\n tmg_gen : entity work.video_timing_ctrl\n generic map (\n video_hlength => video_hlength / 2, --divide by two because two pixels per clock\n video_vlength => video_vlength,\n\n video_hsync_pol => video_hsync_pol,\n video_hsync_len => video_hsync_len / 2,\n video_hbp_len => video_hbp_len / 2,\n video_h_visible => video_h_visible / 2,\n\n video_vsync_pol => video_vsync_pol,\n video_vsync_len => video_vsync_len,\n video_vbp_len => video_vbp_len,\n video_v_visible => video_v_visible)\n port map(\n pixel_clock => pixel_clock,\n reset => reset,\n ext_sync => '0',\n\n timing_h_pos => open,\n timing_v_pos => open,\n pixel_x => pixel_x_div,\n pixel_y => pixel_y,\n\n video_vsync => video_vsync,\n video_hsync => video_hsync,\n video_den => den_int,\n video_line_start => video_line_start);\nend Behavioral;\n" }, { "path": "vhdl_rx/video-misc/video_fb_output.vhd", "content": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.NUMERIC_STD.ALL;\n\n--Framebuffer video output controller\n--Copyright (C) 2016 David Shah\n--Licensed under the MIT License\n\n\nentity video_fb_output is\n generic(\n video_hlength : natural := 2200; --total visible and blanking pixels per line\n video_vlength : natural := 1125; --total visible and blanking lines per frame\n\n video_hsync_pol : boolean := true; --hsync polarity: true for positive sync, false for negative sync (does not affect framebuffer outputs)\n video_hsync_len : natural := 44; --horizontal sync length in pixels\n video_hbp_len : natural := 88; --horizontal back porch length (excluding sync)\n video_h_visible : natural := 1920; --number of visible pixels per line\n\n video_vsync_pol : boolean := true; --vsync polarity: true for positive sync, false for negative sync\n video_vsync_len : natural := 5; --vertical sync length in lines\n video_vbp_len : natural := 4; --vertical back porch length (excluding sync)\n video_v_visible : natural := 1080 --number of visible lines per frame\n\n );\n\n port(\n pixel_clock : in std_logic;\n reset : in std_logic; --active high async reset\n\n --Framebuffer controller interface\n fbc_vsync : out std_logic;\n fbc_data : in std_logic_vector(23 downto 0);\n\n --Output port timing signals\n --line_start is like hsync but always active high and only asserted for visible lines and for 1 clock cycle\n video_vsync : out std_logic;\n video_hsync : out std_logic;\n video_den : out std_logic;\n video_line_start : out std_logic;\n\n --Pixel output port\n video_data : out std_logic_vector(23 downto 0)\n );\nend video_fb_output;\n\narchitecture Behavioral of video_fb_output is\n signal timing_v_pos : natural range 0 to video_vlength - 1;\n signal timing_h_pos : natural range 0 to video_hlength - 1;\n\n\n signal den_int : std_logic;\nbegin\n fbc_vsync <= '1' when timing_v_pos = 0 else '0';\n\n video_data <= fbc_data when den_int = '1' else x\"000000\";\n video_den <= den_int;\n\n tmg_gen : entity work.video_timing_ctrl\n generic map (\n video_hlength => video_hlength,\n video_vlength => video_vlength,\n\n video_hsync_pol => video_hsync_pol,\n video_hsync_len => video_hsync_len,\n video_hbp_len => video_hbp_len,\n video_h_visible => video_h_visible,\n\n video_vsync_pol => video_vsync_pol,\n video_vsync_len => video_vsync_len,\n video_vbp_len => video_vbp_len,\n video_v_visible => video_v_visible)\n port map(\n pixel_clock => pixel_clock,\n reset => reset,\n ext_sync => '0',\n\n timing_h_pos => timing_h_pos,\n timing_v_pos => timing_v_pos,\n pixel_x => open,\n pixel_y => open,\n\n video_vsync => video_vsync,\n video_hsync => video_hsync,\n video_den => den_int,\n video_line_start => video_line_start);\nend Behavioral;\n" }, { "path": "vhdl_rx/video-misc/video_register.vhd", "content": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\n\n--Pipeline register for video systems (supports up to 2 pixels per clock)\n--Copyright (C) 2016 David Shah\n--Licensed under the MIT License\n\n--Insert this where needed to obtain timing closure for the design\n\nentity video_register is\n port(\n clock : in std_logic;\n\n den_in : in std_logic;\n vsync_in : in std_logic;\n hsync_in : in std_logic;\n line_start_in : in std_logic;\n pixel_1_in : in std_logic_vector(23 downto 0);\n pixel_2_in : in std_logic_vector(23 downto 0);\n\n den_out : out std_logic;\n vsync_out : out std_logic;\n hsync_out : out std_logic;\n line_start_out : out std_logic;\n pixel_1_out : out std_logic_vector(23 downto 0);\n pixel_2_out : out std_logic_vector(23 downto 0)\n );\nend entity;\n\narchitecture Behavioral of video_register is\n\nbegin\n process(clock)\n begin\n if rising_edge(clock) then\n den_out <= den_in;\n vsync_out <= vsync_in;\n hsync_out <= hsync_in;\n line_start_out <= line_start_in;\n pixel_1_out <= pixel_1_in;\n pixel_2_out <= pixel_2_in;\n end if;\n end process;\nend Behavioral;\n" }, { "path": "vhdl_rx/video-misc/video_timing_ctrl.vhd", "content": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.NUMERIC_STD.ALL;\n\n--Flexible Video Timing Controller\n--Copyright (C) 2016 David Shah\n--Licensed under the MIT License\n\n\nentity video_timing_ctrl is\n generic(\n video_hlength : natural := 2200; --total visible and blanking pixels per line\n video_vlength : natural := 1125; --total visible and blanking lines per frame\n\n video_hsync_pol : boolean := true; --hsync polarity: true for positive sync, false for negative sync (does not affect framebuffer outputs)\n video_hsync_len : natural := 44; --horizontal sync length in pixels\n video_hbp_len : natural := 88; --horizontal back porch length (excluding sync)\n video_h_visible : natural := 1920; --number of visible pixels per line\n\n video_vsync_pol : boolean := true; --vsync polarity: true for positive sync, false for negative sync\n video_vsync_len : natural := 5; --vertical sync length in lines\n video_vbp_len : natural := 4; --vertical back porch length (excluding sync)\n video_v_visible : natural := 1080; --number of visible lines per frame\n\n --H and V timing coordinates at rising edge of external sync input\n sync_v_pos : natural := 132;\n sync_h_pos : natural := 1079\n );\n\n port(\n pixel_clock : in std_logic;\n reset : in std_logic; --active high async reset\n\n --External sync input\n ext_sync : in std_logic;\n\n --Timing and pixel coordinate outputs\n timing_h_pos : out natural range 0 to video_hlength - 1;\n timing_v_pos : out natural range 0 to video_vlength - 1;\n pixel_x : out natural range 0 to video_h_visible - 1;\n pixel_y : out natural range 0 to video_v_visible - 1;\n\n --Traditional timing signals\n --line_start is like hsync but always active high and only asserted for visible lines and for 1 clock cycle\n video_vsync : out std_logic;\n video_hsync : out std_logic;\n video_den : out std_logic;\n video_line_start : out std_logic\n );\nend video_timing_ctrl;\n\narchitecture Behavioral of video_timing_ctrl is\n constant t_hsync_end : natural := video_hsync_len - 1;\n constant t_hvis_begin : natural := video_hsync_len + video_hbp_len;\n constant t_hvis_end : natural := t_hvis_begin + video_h_visible - 1;\n\n constant t_vsync_end : natural := video_vsync_len - 1;\n constant t_vvis_begin : natural := video_vsync_len + video_vbp_len;\n constant t_vvis_end : natural := t_vvis_begin + video_v_visible - 1;\n\n signal h_pos : natural range 0 to video_hlength - 1;\n signal v_pos : natural range 0 to video_vlength - 1;\n\n signal x_int : natural range 0 to video_h_visible - 1;\n signal y_int : natural range 0 to video_h_visible - 1;\n\n signal h_visible, v_visible : std_logic;\n signal hsync_pos, vsync_pos : std_logic;\n\n signal ext_sync_last : std_logic;\n signal ext_sync_curr : std_logic;\nbegin\n --Basic counters\n process(pixel_clock, reset)\n begin\n if reset = '1' then\n h_pos <= 0;\n v_pos <= 0;\n elsif rising_edge(pixel_clock) then\n if ext_sync_curr = '1' and ext_sync_last = '0' then\n h_pos <= sync_h_pos;\n v_pos <= sync_v_pos;\n else\n if h_pos = video_hlength - 1 then\n h_pos <= 0;\n if v_pos = video_vlength - 1 then\n v_pos <= 0;\n else\n v_pos <= v_pos + 1;\n end if;\n else\n h_pos <= h_pos + 1;\n end if;\n end if;\n ext_sync_curr <= ext_sync;\n ext_sync_last <= ext_sync_curr;\n end if;\n end process;\n\n --Visible signals\n v_visible <= '1' when (v_pos >= t_vvis_begin) and (v_pos <= t_vvis_end) else '0';\n h_visible <= '1' when (h_pos >= t_hvis_begin) and (h_pos <= t_hvis_end) else '0';\n\n --Pixel coordinates\n x_int <= (h_pos - t_hvis_begin) when (h_visible = '1') and (v_visible = '1') else 0;\n y_int <= (v_pos - t_vvis_begin) when v_visible = '1' else 0;\n\n --den and line_start signals\n video_den <= h_visible and v_visible;\n video_line_start <= '1' when (v_visible = '1') and (h_pos = 0) else '0';\n\n --Sync signals\n vsync_pos <= '1' when v_pos <= t_vsync_end else '0';\n hsync_pos <= '1' when h_pos <= t_hsync_end else '0';\n video_vsync <= vsync_pos when video_vsync_pol else not vsync_pos;\n video_hsync <= hsync_pos when video_hsync_pol else not hsync_pos;\n\n --External outputs\n timing_h_pos <= h_pos;\n timing_v_pos <= v_pos;\n pixel_x <= x_int;\n pixel_y <= y_int;\nend Behavioral;\n" } ]